Abstract:
A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a reworking method for integrated circuit devices, and more particularly, to a reworking method for removing defects on layers of metal interconnections of the integrated circuit devices. 
     2. Description of the Prior Art 
     The fabrication procedure of integrated circuit (IC) devices is very complicated. Generally, it requires hundreds of different processes to complete the integrated circuit devices. Whenever the quality requirements of those processes are not being met, a reworking method is thereby needed. 
     Please refer to  FIG. 1 , which is a cross-sectional drawing of a conventional metal interconnection. In recent years, integrated circuit devices are formed as a plurality of multi-layered metal interconnections in accordance with a tendency toward higher density and higher integration, and to thereby increase the electrical connections between the metal interconnections themselves or between the integrated circuit devices and the metal interconnections. In a conventional method for fabricating a metal interconnection, a substrate  100  is provided with a base layer  101  and a dielectric layer  102  sequentially formed thereon, and procedures such as the photolithography process and the etching process are performed to form a plurality of vias/trenches for defining the metal interconnection patterns. Then, a barrier layer  104  and a metal layer  106  are sequentially formed in the vias/trenches, and a desired metal interconnection is obtained. As shown in  FIG. 1 , a base layer  110 , a dielectric layer  112 , a cap layer  114 , and a hard mask layer (not shown) are sequentially deposited on the substrate  100 , followed by the performing of procedures such as the photolithograph process and the etching process to form a metal interconnection pattern  116  for preparing another metal interconnection. 
     Please refer to  FIG. 1  again. However, whenever some events such as particle contamination occurring in the above described deposition process, the existence of masking effect resulting from the existence of particles which leads to the forming of incomplete metal interconnection pattern  116  during etching, or having scratches formed on the wafer surface due to any external factor, the wafer thereby cannot be transferred to the next processing step. Thus, a reworking method is needed. Otherwise, the yield of the integrated circuit devices is to by significantly reduced. Sometimes the wafer even has to be discarded as scrape due to serious defects. 
     SUMMARY OF THE INVENTION 
     It is therefore a primary objective of the claimed invention to provide a reworking method for integrated circuit devices having defects in the metal interconnection layers for reducing cost associated with the discarding as scrap of the integrated circuit devices. 
     According to the claimed invention, a reworking method for integrated circuit devices is provided. The method comprises providing a substrate having a first base layer and a first dielectric layer sequentially formed thereon; performing a first dry etching to remove the first dielectric layer; performing a chemical mechanic polish (CMP) process to remove the first base layer; and sequentially reforming a second base layer and a second dielectric layer on the substrate. 
     According to the claimed invention, another reworking method for integrated circuit devices is provided. The reworking method comprises providing a substrate having a first base layer, a first dielectric layer, and a first cap layer sequentially formed thereon, and at least a metal interconnection pattern is being formed in the first cap layer and the first dielectric layer; performing a first dry etching process to remove the first cap layer; performing a second dry etching process to remove the first dielectric layer; performing a CMP process to remove the first base layer; and reforming a second base layer, a second dielectric layer and a second cap layer sequentially. 
     According to the reworking method provided by the present invention, when defects are found in the layers of the metal interconnection, or when the metal interconnection pattern has failed the after-etching-inspection (AEI), those undesired layers are effectively removed by the reworking method provided by the present invention. Therefore the corresponding IC devices are prevented from being discarded as scrap, and thus the cost is reduced. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic cross-sectional drawing of a conventional metal interconnection. 
         FIGS. 2-6  are schematic drawings illustrating a reworking method for integrated circuit devices according to a first preferred embodiment of the invention. 
         FIGS. 7-10  are schematic drawings illustrating a reworking method for integrated circuit devices according to a second preferred embodiment of the invention. 
         FIGS. 11-16  are schematic drawings illustrating a reworking method for integrated circuit devices according to a third preferred embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 2-6 , which are schematic drawings illustrating a reworking method for integrated circuit devices according to a first preferred embodiment of the invention. As shown in  FIG. 2 , an integrated circuit device  200  having a substrate  202  and at least a metal interconnection layer  204  formed thereon is provided. The substrate  202  also comprises a first base layer  206  and a first dielectric layer  208  sequentially formed thereon. The first base layer  206  can comprise silicon nitride (SiN); and the first dielectric layer  208  can comprise fluoride silicon glass (FSG). 
     Please refer to  FIGS. 2-3 . When the integrated circuit device  200  has failed an after-deposition-inspection, a dry etching process  250  is performed to remove the first dielectric layer  208 . It is noteworthy that the dry etching process  250  is performed having a high selectivity between the first dielectric layer  208  and the first base layer  206 . For example, oxygen and fluorocarbon, such as octafluorocyclopentene (C 5 F 8 ), with a preferred ratio of 2:3 can be introduced into the dry etching process  250  for serving as the reaction gases. The dry etching process  250  utilizing the above-mentioned reaction gases has an etching rate for the first dielectric layer  208  comprising of FSG of 65 A/sec and an etching rate for the first base layer  206  which comprises SiN of 4 A/sec. 
     Please refer to  FIG. 4 . After the first dielectric layer  208  is removed, a second dielectric layer  220  is reformed on the first base layer  206  as shown in  FIG. 4 . The second dielectric layer  220 , which is similar to the first dielectric layer  208 , can comprise FSG. And both of the first dielectric layer  208  and the second dielectric layer  220  serve as the inter metal dielectric (IMD) layers. 
     Please refer to  FIGS. 3 and 5 . After the dry etching process  250  is performed for removing the first dielectric layer  208 , a chemical mechanic polish (CMP) process can be performed to remove the first base layer  206 . Due to the high selectivity between the first dielectric layer  208  and the first base layer  206  as found in the dry etching process  250 , even if the first base layer  206  is slightly consumed in the dry etching process  250 , the uniformity of the first base layer  206  would not be overly negatively affected. Thus the first base layer  206  can be removed by the CMP process. Please refer to  FIG. 6 . When the layers which have failed in the after-deposition-inspection are removed, a second base layer  222  is reformed on the substrate  202 . The second base layer  222 , similar to the first base layer  206 , can comprise SiN. Then a second dielectric layer  220  is reformed on the second base layer  222 . 
     Please refer to  FIGS. 7-10 , which are schematic drawings illustrating a reworking method for integrated circuit devices according to a second preferred embodiment of the invention. As shown in  FIG. 7 , an integrated circuit device  200  having a substrate  202  and at least a metal interconnection  204  layer formed thereon is provided. The substrate  202  also comprises a first base layer  206 , a first dielectric layer  208 , and a first cap layer  210  sequentially formed thereon. The first base layer  206  can comprise SiN; the first dielectric layer  208  can comprise FSG; and the first cap layer  210  can comprise silicon oxynitride (SiON). 
     Please refer to  FIGS. 7-8 . When the integrated circuit device  200  has failed an after-deposition-inspection, a dry etching process  260  is performed to remove the first cap layer  210 . After removing the first cap layer  210 , another dry etching process  250  is performed to remove the first dielectric layer  208 . It is noteworthy that the dry etching process  250  is performed having a high selectivity between the first dielectric layer  208  and the first base layer  206 . For example, oxygen and fluorocarbon such as C 5 F 8  with a preferred ratio of 2:3 can be introduced in the dry etching process  250  for serving as the reaction gases. The dry etching process  250  utilizing the above-mentioned reaction gases has an etching rate for the first dielectric layer  208  which comprises FSG of 65 A/sec, and an etching rate for the first base layer  206  which comprises SiN of 4 A/sec. 
     Please refer to  FIG. 9 . After the first cap layer  210  and the first dielectric layer  208  are removed, a second dielectric layer  220  and a second cap layer  224  are sequentially reformed on the first base layer  206  as shown in  FIG. 9 . The second dielectric layer  220 , which is similar to the first dielectric layer  208 , can comprise FSG. And both of the first dielectric layer  208  and the second dielectric layer  220  serve as IMD layers. The second cap layer  224  can comprise SiON, similar as the first cap layer  210 . 
     Moreover, after the first dielectric layer  208  is removed by the dry etching process  250 , a CMP process can be performed to remove the first base layer  206 . Since the CMP result is similar with that shown in  FIG. 5 , thereby additional drawings are omitted in the interest of brevity. Due to the high selectivity between the first dielectric layer  208  and the first base layer  206  as found in the dry etching process  250 , even if the first base layer  206  is slightly consumed in the dry etching process  250 , the uniformity of the first base layer  206  would not be overly negatively affected. Thus the first base layer  206  can be removed by the CMP process. Please refer to  FIG. 10 . When the layers which have failed the after-deposition-inspection are removed, a second base layer  222 , a second dielectric layer  220 , and a second cap layer  224  are sequentially reformed on the substrate  202 . The second base layer  222 , similar to the first base layer  206 , can comprise SiN. 
     According to the first and second preferred embodiments of by the present invention, when the layers, such as the first base layer  206 , the first dielectric layer  208 , or the first cap layer  208  of the integrated circuit device  200  has failed the after-deposition-inspection, or is scrapped or damaged by other factors, the reworking method provided by the present invention is performed to remove the undesired layers, thereby preventing the integrated circuit device  200  from being discarded as scrap and cost is reduced. 
     Please refer to  FIGS. 11-16 , which are schematic drawings illustrating a reworking method for integrated circuit devices according to a third preferred embodiment of the invention. As shown in  FIG. 11 , an integrated circuit device  300  having a substrate  302  and at least a metal interconnection layer  304  formed thereon is provided. The substrate  302  also comprises a first base layer  306 , a first dielectric layer  308  serving as IMD, and a first cap layer  310  sequentially formed thereon. As mentioned above, the first base layer  306  can comprise SiN, the first dielectric layer  308  can comprise FSG, and the first cap layer  310  can comprise SiON. In addition, a metal interconnection pattern  320  is formed in the first cap layer  310  and the first dielectric layer  308  by procedures such as the photolithograph process and the etching process. As shown in  FIG. 11 , the first base layer  306  is exposed at the bottom of the metal interconnection pattern  320 . 
     Please refer to  FIG. 12 . When the integrated circuit device  300  has failed an after-etching-inspection (AEI), a reworking method provided by the present invention is performed. First, a protecting layer  322  is formed on the first cap layer  310 . The protecting layer  322  can be a photoresist, and is to be formed on the first cap layer  310  by a spin on coating method. Then an etching back process is performed to etch back the protecting layer  322  to be below an opening of the metal interconnection pattern  320 . 
     Please refer to  FIGS. 12-13 , when a dry etching process  350  is performed to remove the first cap layer  310 . The dry etching process  350  is performed having a high selectivity between the first cap layer  310  and the protecting layer  322 . For example, Oxygen, fluoroform (CH 3 F), and nitrogen with a preferred ratio of 1:12:24 can be introduced into the dry etching process  350  for serving as the reaction gases. The dry etching process utilizing the above-mentioned reaction gases has an etching rate for the first cap layer  310  which comprises SiON of 45 A/sec, and an etching rate for the protecting layer  322  which comprises photoresist of 0 A/sec. 
     It is noteworthy that the reaction gases used to etch SiON are capable of etching SiN. For example, the reaction gases comprising oxygen, CH 3 F, and nitrogen have an etching rate of 35 A/sec for SiN. Therefore the first base layer  306  is also etched during the dry etching process  350 . In an undesirable scenario, the first base layer  306  is consumed to the point of exposing the copper wire underneath. However, according to the third preferred embodiment, the dry etching process  320  has a very low etching rate for the protecting layer  322 , which is formed in the metal interconnection pattern  320 ; therefore, the protecting layer  322  protects the first base layer  306  from coming into contact with the reaction gases of the dry etching process  350  and prevents the first base layer  306  from being etched. Consequently, the copper wire underneath the first base layer  306  is protected. Furthermore, since the protecting layer  322  is etched back to be below the opening of the metal interconnection pattern  320 , there would be no remnants of the protecting layer  322  to be remained on the first cap layer  310 ; therefore, the dry etching process  350  is able to remove the first cap layer  310  completely. 
     Please refer to  FIGS. 13-14 . After removing the first cap layer  310 , another dry etching process  360  is performed to remove the first dielectric layer  308 . And a second dielectric layer  330  and a second cap layer  334  are sequentially reformed on the first base layer  306  after removing the protecting layer  322  in order to prepare for the forming of a metal interconnection pattern again as shown in  FIG. 14 . The second dielectric layer  330  can comprise FSG, and to serve as IMD layer as the first dielectric layer  308  does. The second cap layer  334 , which is similar to the first cap layer  310 , can comprise SiON. 
     The dry etching process  360  is performed having a high selectivity between the first dielectric layer  308  and the first base layer  306 . For example, oxygen and fluorocarbon such as C 5 F 8  with a preferred ratio of 2:3 can be introduced into the dry etching process  360  for serving as the reaction gases. The dry etching process  360  utilizing the above-mentioned reaction gases has an etching rate for the first dielectric layer  308  which comprises FSG of 65 A/sec, and an etching rate for the first base layer  306  which comprises SiN of 4 A/sec. 
     Furthermore, as shown in  FIG. 15 , after the first dielectric layer  308  is removed by using the dry etching process  360 , a CMP process is performed to remove the first base layer  306 . Due to the high selectivity between the first dielectric layer  308  and the first base layer  306  as found in the dry etching process  360 , even if the first base layer  306  is slightly consumed during the dry etching process  360 , the uniformity of the first base layer  306  would not be overly negatively affected. Thus the first base layer  306  can be removed by the CMP process. Please refer to  FIG. 16 . When the layers which have failed the AEI are removed, a second base layer  332 , a second dielectric layer  330 , and a second cap layer  334  are sequentially reformed on the substrate  302 . The second base layer  306 , similar to the first base layer  306 , can comprise SiN. Thus the reworked integrated circuit device  300  is prepared for forming a metal interconnection pattern again. 
     According to the third preferred embodiments of the present invention, when the metal interconnection pattern  320  has failed the AEI due to the masking effect by the particles or due to any other factors, the reworking method provided by the present invention is performed to remove the undesired layers; therefore, the integrated circuit device  300  is prevented from being discarded as scrap, and cost is reduced. 
     As mentioned above, the reworking method provided by the present invention can be used for removing any of the undesired layers, such as the base layer, the dielectric layer, or the cap layer on the integrated circuit device when it failed in the after-deposition-inspection or is damaged by other factors. The reworking method also can be applied to integrated circuit device having metal interconnection pattern upon failures in AEI or is damaged by other factors for removing the undesired layers. The integrated circuit devices undergoing the reworking method provided by the present invention are used for reforming layers of the metal interconnection or reforming metal interconnection patterns. Therefore, the integrated circuit device is prevented from being discarded as scrap, and the cost is reduced. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.