Abstract:
To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package.

Description:
BACKGROUND OF THE INVENTION 
     This application relates to semiconductor die package that contain multiple semiconductor dice. 
     In semiconductor packages, a semiconductor die is sometimes mounted on a highly heat-conductive (typically metal) die pad that is exposed at the bottom of the package. Particularly when the die contains a device that generates significant amounts of heat—for example, a power MOSFET or other semiconductor power device—the die pad (or metal slug) serves as a thermal conductive path that allows heat generated in the die to flow to the structure on which the package is mounted, typically a printed circuit board (PCB). This helps to prevent the die from overheating, which can damage or destroy the die. 
     In some cases two or more dice are housed in a single package. For example, a single package may contain a power MOSFET die together with a control die that contains circuitry for turning the power MOSFET off and on. This type of circuit is represented schematically by control die  2  and power MOSFET die  3  shown in  FIG. 1 . Power MOSFET die  3  contains a power MOSFET  6  whose source and body terminals are shorted together and connected to ground and whose drain terminal is connected to a load  8 . The source-body short in MOSFET  6  creates an intrinsic diode  7  that is in parallel with the source-body and drain terminals of MOSFET  6 . 
     MOSFET  6  is controlled by control die  2 , which contains a control element  4  and a buffer  5 , an output terminal of buffer  5  being connected to the gate terminal of MOSFET  6 . As shown, control die  2  is connected between a positive supply voltage V CC  and ground. 
       FIG. 2A  illustrates a cross-sectional view of buffer  5  in control die  2 , which includes a P substrate  2 . Buffer  5  includes an N-channel MOSFET  26 A and a P-channel MOSFET  26 B, MOSFET  26 A being formed in a P-well  23  and MOSFET  26 B being formed in an N-well  22 , which serve as the body regions of the respective MOSFETs. In MOSFET  26 A, an N+ source region  25 C and a P+ body contact region  24 A are shorted together and connected to ground. In MOSFET  26 B, a P+ source region  24 C and an N+ body contact region  25 A are shorted together and connected to V CC . An N+ drain region  25 B of MOSFET  26 A and a P+ drain region  24 B of MOSFET  26 B are connected together and provide an output voltage V OUT  that is delivered to the gate terminal of power MOSFET  6 . An input voltage V IN  from control element  4  is delivered to the respective gate terminals of MOSFETs  26 A and  26 B. Thus when V IN  is high, MOSFET  26 A is turned on and MOSFET  26 B is turned off and V OUT  is approximately equal to ground; and when V IN  is low, MOSFET  26 A is turned off and MOSFET  26 B is turned on and V OUT  is approximately equal to V CC . 
       FIG. 2B  illustrates a cross-sectional view of MOSFET  6  in die  3 , which includes an N+ substrate  31 . An N-epitaxial layer  32  is grown on N+ substrate  31 . N+ source regions  35 , P-body regions  33  and P+ body contact regions  34  are implanted into N-epitaxial layer  32 , and trenches  38  are etched from the surface of die  3  through N+ source regions  35  and P-body regions  33 . Each of trenches  38  contains a gate terminal  37  and a gate oxide layer  36 , which insulates gate terminal  37  from N-epitaxial layer  32 . A metal layer  39  overlies the surface of N-epitaxial layer  32  and shorts together N+ source regions  35 , P-body regions  33  and P+ body contact regions  34 . The N+ substrate  31  represents the drain terminal of MOSFET  6 . Consistent with  FIG. 1 , metal layer  39  (the source-body terminal) is connected to ground and N+ substrate  31  (the drain terminal) is connected to the load  8 . 
     The gate electrodes  37  are accessed in the third dimension, outside the plane of  FIG. 2B , and this connection is shown schematically. 
     Thus power MOSFET  6  is an N-channel MOSFET. V OUT  from buffer  5  is connected to gate electrodes  37 . When V OUT  is high (V CC ), MOSFET  6  is turned on; when V OUT  is low (ground), the gate-to-source voltage of MOSFET  6  is equal to zero and MOSFET  6  is turned off. 
     A key aspect of dice  2  and  3  is that in this arrangement the P substrate  21  of die  2  is connected to ground and the N+ substrate  31  of die  3  is connected to the load  8 . As shown in  FIG. 1 , since the source-body terminal of MOSFET  6  is grounded, the N+ substrate  31  (drain) in on the high side of MOSFET  6 . As a result, when MOSFET  6  is turned off, the voltage at N+ substrate  31  approaches the high voltage (+HV) that drives the load  8 . 
       FIG. 3A  shows a cross-sectional view of a conventional semiconductor package  50  containing dice  2  and  3 . Die  2  is mounted on a die pad  51 B and die  3  is mounted on a die pad  51 C. Dice  2  and  3  and die pads  51 B and  51 C are encased in a capsule  53  made of a molding compound, typically a plastic material. Since power MOSFET  6  generates a significant amount of heat, die pad  51 C is exposed at a bottom surface  53 B of capsule  53  thereby providing a thermal conduction path for the heat generated in die  3  to escape to the PCB or other structure (not shown) on which package  50  is mounted. Likewise, die pad  51 B is exposed at the bottom surface  53 B of capsule  53 . Apart from their thermal functions, die pads  51 B and  51 C also provide electrical contact to terminals on the bottom surfaces of dice  2  and  3 . 
     The top surface of die  2  is connected via a bonding wire  52 A to a contact  51 A, and the top surface of die  3  is connected via a bonding wire  52 B to a contact  51 D. Since package  50  is a “no-lead” type of package, the outside surfaces of contacts  51 A and  51 D are flush with the bottom surface  53 B and side surfaces  53 S of capsule  53 . Consistent with  FIG. 1 , bonding wire  52 A connects to the source-body terminal of MOSFET  26 B, and thus contact  51 A is connected to V CC . (Another bonding wire and contact (not shown) connect the source-body terminal of MOSFET  26 A to ground.) Bonding wire  52 B connects to the source-body terminal of MOSFET  6 , and thus contact  51 D is connected to ground. 
     P substrate  21  of die  2  is connected via die pad  51 B to ground, and N+ substrate  31  of die  3  is connected via die pad  51 C to a voltage that can approach the high voltage +HV. As noted above, both die pad  51 B and die pad  51 C are exposed at the bottom of package  50 . 
       FIG. 3B  is a bottom view of package  50 . The exposed bottom surfaces of die pads  51 B and  51 C as well as the cross-section  3 A- 3 A of  FIG. 3A  are shown. 
     Having exposed die pads that may assume different voltages in operation can create problems. When the package is mounted onto a PCB or other supporting structure, bits or pieces of metal or other conductive materials may become trapped between the package and the PCB and may create a short between the die pads. These latent shorts may remain undetected, visually hidden beneath the plastic package. While X-rays may be used to identify the shorts, X-ray inspection is expensive and potentially hazardous to workers. 
     BRIEF SUMMARY OF THE INVENTION 
     In a multi-die package according to this invention, at least one of the die pads remains embedded in the capsule such that its bottom surface is not exposed. Typically, this will be the die pad that is attached to the die that generates less heat. In the above example, the die pad attached to the control die would be left embedded in the capsule. This invention is not limited in this way, however. In a multi-die package, any one or more of the die pads may be left embedded in the capsule to prevent a possible short with an exposed die pad. 
     Leaving a die pad embedded in the capsule eliminates the risk of shorts between the embedded die pad and other die pads in the package when the package is mounted onto a PCB or other supporting structure. 
     To provide electrical contact with a terminal on the bottom of the die that is mounted on the embedded die pad, one or more of the contacts or leads in the package may be formed as an integral part of the embedded die pad. 
     The invention includes a process for fabricating a multi-die package as described above. The process includes a partial etch that defines the bottom surface of the embedded die pad and may include a through-etch that leaves one or more of the contacts or leads integrally connected to the embedded die pad. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIG. 1  is a circuit diagram of a conventional circuit that includes a power MOSFET, a load that is switched by the power MOSFET, and control circuitry for the power MOSFET. 
         FIG. 2A  is a cross-sectional view of a portion of the control circuitry for the power MOSFET. 
         FIG. 2B  is a cross-sectional view of the power MOSFET. 
         FIGS. 3A and 3B  are cross-sectional and bottom views, respectively, of a conventional multi-die package. 
         FIGS. 4A and 4B  are cross-sectional views of no-lead multi-die semiconductor packages in accordance with the invention. 
         FIGS. 5A and 5B  are bottom and top views, respectively, of the semiconductor package shown in  FIGS. 4A and 4B . 
         FIG. 6  is a flowchart of a process for fabricating the semiconductor package. 
         FIGS. 7A-7F  illustrate several steps in a three-mask fabrication process. 
         FIGS. 8 and 9  illustrate embodiments fabricated by an alternative two-mask process. 
         FIG. 10  illustrates an embodiment wherein a peripheral shelf is formed around the exposed die pad. 
         FIG. 11  illustrates the application of the invention to a “gull-winged” multi-die package such as a small-outline transistor (SOT) package or any various small outline packages (SOP, SSOP, TSOP, TSSOP, etc.). 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 4A  is a cross-sectional view of a semiconductor package  100  in accordance with the invention. A control die  103  is mounted on a die pad  101 C. A power MOSFET die  104  is mounted on a die pad  101 D. In this embodiment, control die  102  is similar to control die  2  and power MOSFET die  104  is similar to power MOSFET die  3 . 
     Circuitry on the top surface of die  103  is connected via a bonding wire  105 A to a contact  101 A, which includes a horizontal cantilever extension  101 B. Circuitry on the top surface of die  104  is connected via a bonding wire  105 B to a contact  101 F, which includes a horizontal cantilever extension  101 G. All of the foregoing components are encased in a capsule  102 , consisting of a polymer material, which has side edges  102 S and a bottom surface  102 B. 
     Package  100  is a “no-lead” package. Accordingly contacts  101 A and  101 F do not protrude from capsule  102 ; instead, the side edges of contacts  101 A and  101 F are flush (coplanar) with the side edges  102 S of capsule  102  and the bottom surfaces of contacts  101 A and  101 F are flush with the bottom surface  102 B of capsule  102 . 
     The bottom of die pad  101 D is exposed at the bottom surface  102 B of capsule  102 , whereas die pad  101 C is embedded in capsule  102 . Therefore, there is no risk of forming a short between die pad  101 C and die pad  101 D when package  100  is mounted onto a PCB (not shown). 
       FIG. 5A  is a bottom view and  FIG. 5B  is a top view of package  100 , each drawing showing the cross-section  4 - 4  at which  FIG. 4  is taken. As is evident from  FIGS. 5A and 5B , contacts  101 A and  101 F are but two contacts of 16 contacts  101  that line the periphery of package  100 , with four contacts on each side of package  100 . In  FIG. 5A  die pad  101 C is shown in dashed lines to indicate that die pad  101 C is not actually visible in this bottom view.  FIG. 5B  shows tie bars  131 A and  131 B that connect die pad  101 D to the leadframe during the fabrication of package  100 . Similarly, a tie bar  131 C connects die pad  101 C to the leadframe. As explained below, tie bars  131 A- 131 C are severed in the normal way when package  100  is singulated from the other semiconductor packages that are fabricated from the leadframe. 
     As shown in the top view of  FIG. 5B , contacts  101 H and  101 I are directly connected to die pad  101 C and in fact are formed as integral parts of die pad  101 C. The structure of contact  101 I is shown in  FIG. 4B , which is cross-sectional view of package  100  taken at cross-section  4 B- 4 B in  FIG. 5B . As shown in  FIG. 4B , contact  101 I includes a horizontal cantilever extension  101 K that joins die pad  101 C. Thus contact  101 I is in reality an integral extension of the die pad  101 C. This allows electrical contact to be made to the bottom side of die  103  through contact  101 I. Consistent with  FIGS. 1 and 2A , contact  101 I is shown as being connected to ground. 
     Since the exposed surfaces of contacts  101 I and  101 H at the bottom of capsule  102  are more distant from the exposed surface of die pad  101 D than die pad  101 C would be if its bottom surface were exposed, the risks of an electrical short being created between die pads  101 C and  101 D when package  100  is mounted on a PCB are far less than they are in a package of the type shown in  FIG. 3A . 
       FIG. 6  is a flowchart of a possible process for fabricating a semiconductor package of this invention. 
     The process begins with a conventional copper leadframe (box  150 ). The leadframe is masked where the exposed die pads and the exposed bottom surfaces of the contacts will be located and is then partially etched for example, using ammonium persulfate, sodium persulfate, ferric chloride, or other etchants comprising hydrochloric acid, nitric acid or sulfuric acid to define the bottom surface of the embedded die pads. This is referred to as the “shallow moat” (box  155 ). The leadframe is masked again to cover the bottom surfaces of the contacts and the exposed and embedded die pads, and a second, “deep moat” partial etch is performed to define the lower surfaces of the horizontal cantilever extensions of the contacts (box  160 ). The exposed die pad can also referred to as the heat slug, and the embedded die pad can also be referred to as a non-exposed die pad. 
     The shallow moat etch may also be used to define the lower surfaces of the horizontal cantilever extensions of the contacts as well as the bottom surfaces of the embedded die pads, in which case the “deep moat” etch is omitted. The leadframe is masked again to cover the bottoms of the exposed and embedded die pads and the exposed bottom surfaces and undersides of the cantilever extensions of the contacts, and a through-etch is performed to separate the die pads and contacts from each other (box  165 ). The dice are then attached to the die pads and wire-bonded to the contacts (box  170 ). The entire leadframe at this point typically consists of a rectangular array of die pads and contacts that will form numerous packages when completed. The leadframe is then encased in a polymer molding compound, typically using an injection-molding process, and the individual packages are singulated by sawing or punching the polymer-coated leadframe along perpendicular lines (box  175 ). 
     One version of the process is shown in greater detail in the cross-sectional views of  FIGS. 7A-7F . 
       FIG. 7A  shows a copper sheet  151 , typically 0.2 to 0.4 mm thick, from which the leadframe will be fabricated. A first mask layer  160 , typically organic photoresist, is deposited on a surface of copper sheet  151  and then photolithographically patterned to leave mask layer in place where the exposed die pads and the bottom surfaces of the contacts are to be located. Alternatively, the masking material may be silkscreened to define the pattern. Copper sheet  151  is then partially etched to form a “first moat” including trenches  152 A and  152 B, etching away between 10% to 60% of the copper&#39;s thickness and preferably around 30%. The first mask layer material  160  may be removed or alternatively left in place to mask subsequent etching steps. The resulting structure is shown in  FIG. 7B  where regions  152 A and  152 B have a thickness equal to 40% to 90% of the starting thickness of copper sheet  151 . 
     A second mask layer  161  is deposited and photolithographically patterned to leave mask layer  161  in place where the embedded die pads are to be located. Copper sheet  151  is then partially etched again to form a “second moat” including trenches  153 A,  153 B and  153 C. The resulting thickness of the copper regions etched twice  153 A,  153 B, and  153 C is thinner than the regions etched once, having a final thickness of 10% to 60% of the original thickness of copper sheet  151 . The result is shown in  FIG. 7C . Region  152 A remains unaffected by this operation, retaining the same thickness as shown in  FIG. 7B . Other portions, not etched during the first or the second etch, remain at the original thickness of copper sheet  151 . 
     In a preferred embodiment, the twice-etched regions  153 A,  153 B and  153 C, are contained entirely within first etched regions  152 A and  152 B, so that only regions of copper sheet  151  that are already thinned during the first etch receive the second etching step. Mask layer  161  covers and protects the isolated die pad portion (e.g. die pad  101 C in  FIG. 4A ). In the event that masking material  160  is removed after the first etching step, mask layer  161  must also cover the portions of copper sheet  151  originally protected by mask layer  160 . 
     A third mask layer  163  is deposited and photolithographically patterned to leave mask layer  163  in place during a third copper etch, designed to selectively separate the contacts from the heat slug and from the non-exposed die pad. After the third mask layer  163  is applied, copper sheet  151  is then etched completely through to separate embedded die pad  101 C from exposed die pad  101 D and from contacts  101 A and  101 F. Specifically, the third etch completely removes the copper from the unprotected portions of previously etched regions  153 A,  153 B and  153 C, to form the fully etched regions  154 A,  154 B and  154 C as shown in  FIG. 7D . Mask  163  results in a horizontal cantilever extension  101 B of lead  101 A and a horizontal cantilever extension  101 G of lead  101 F. 
     In a preferred embodiment, second etched regions  154 A,  154 B and  154 C, are contained entirely within the twice-etched regions  153 A,  153 B and  153 C, so that only regions of copper sheet  151  thinned during the first and second copper etch receive the third etching step. Mask layer  163  covers and protects the horizontal cantilever extensions  101 B and  101 G. 
     In the event that mask layer  160  is removed after the first etch step and mask layer  161  is removed after the second etch step, mask layer  163  must also cover the portions of copper sheet  151  originally protected by mask layers  160  and  161 . Alternatively, provided the thickness of cantilever sections  101 B and  101 G are a small fraction of embedded die pad  101 C, then the bottom side of copper elements  101 A,  101 C,  101 D and  101 F may be allowed to erode during the third etch. The final package thickness in such an instance will be thinner than if the same regions are protected during the third etch. 
     If one or more of the contacts are to be formed as integral extensions of the embedded die pad  101 C, as shown by contact  101 I in  FIG. 4B , then it will be understood that the third mask layer  163  will also be patterned to remain over horizontal cantilever extension  101 K. As a result the contact  101 I will remain as an integral extension of die pad  101 C after the final through-etch. 
     It will also be understood that although die pads  101 C and  101 D appear in  FIG. 7D  as being completely separated from contacts  101 A and  101 F, die pads  101 C and  101 D remain connected to the lead frame by tie bars  131 A- 131 C, shown in  FIG. 5B , that are outside the plane of  FIG. 7D . 
     Next, mask layers  161 - 163  are removed, and control die  103  is attached to embedded die pad  101 C and power MOSFET die  104  is attached to exposed die pad  101 D. Wire bonds  105 A and  105 B are created, leaving the structure shown in  FIG. 7E . 
     Using an injection molding process, all of the elements of the package are then encased in a polymer molding compound, with the bottom surfaces of the exposed die pad  101 D and the contacts  101 A and  101 F remaining exposed after the molding process is completed. The result is a polymer sheet containing many packages positioned in a rectangular array. To complete the fabrication process, the polymer sheet is sawn along perpendicular lines to separate the packages from each other, a process often referred to as “singulation.” The result is package  100 , shown in  FIG. 7F . The saw cuts would be made at the side edges  102 S of the package, cutting through contact metal regions  101 A and  101 F on adjacent packages, and it will be understood that there are packages identical to package  100  on the left and right side of package  100 . 
     In an alternative version of the process, the second and third mask layers are combined into a single second mask layer, and there is only one partial etch, which defines the bottom surfaces of both the embedded die pad and the horizontal cantilever extension of the contacts. The resulting package is exemplified by package  200 , shown in  FIG. 8 , wherein the bottom surfaces of the horizontal cantilever extensions  201 B and  210 G of the contacts  201 A and  201 F, respectively, are coplanar with the bottom surface of the embedded die  201 C. Also shown in  FIG. 8  are an exposed die  201 D, dice  203  and  204 , bonding wires  205 A and  205 B, and a polymer capsule  202 . 
     In package  200 , the embedded die pad  201 C is of approximately the same as the embedded die pad  101 C in package  100 . As a result the horizontal cantilever extensions  201 B and  201 G in package  200  are thicker than the horizontal cantilever extensions  101 B and  101 G in package  100 . Etching through thicker layers, however, generally requires a larger space between the various copper elements, thereby reducing the useable area for silicon devices within the same package footprint. 
     Alternatively, using the simplified two-mask process the horizontal cantilever extension can have the same thickness as horizontal cantilever extensions  101 B and  101 G in package  100 . The result is package  220 , shown in  FIG. 9 , wherein horizontal cantilever extensions  221 B and  221 G of contacts  221 A and  221 G, respectively, are of the same thickness as horizontal cantilever extensions  101 B and  101 G in package  100 . As a result, embedded die pad  221 C in package  220  is thinner than embedded die pad  101 C in package  100 . A thinner embedded die pad  101 C exposes the silicon die to more stress and deformation during handling and the assembly process, increasing the chances of die cracking, plastic delamination, and plastic cracking. Also shown in  FIG. 9  are an exposed die  221 D, dice  203  and  204 , bonding wires  205 A and  205 B, and a polymer capsule  222 . 
     In another alternative, the third mask layer (in the three-mask process shown in  FIGS. 7A-7F ) or the second mask layer (in the two-mask process) can be used to define a peripheral shelf around the exposed die. The result (using the two-mask process) is package  240 , shown in  FIG. 10 , wherein the exposed die  241 E has a peripheral shelf  241 D,  241 F, which helps to anchor exposed die  241 E in the capsule  242 . Also shown in  FIG. 10  are an embedded die  241 C, dice  203  and  204 , bonding wires  205 A and  205 B, contacts  241 A and  241 G, and a polymer capsule  242 . 
     The embodiments of this invention described above are so-called “no lead” semiconductor packages such as the DFN or QFN, an acronym for dual or quad sided flat no-lead packages, wherein the contacts do not protrude from the polymer capsule. This invention, however, is also applicable to other types of packages.  FIG. 11 , for example, shows a traditional “gull wing” package  260  wherein the leads  261 A and  261 D protrude laterally from a capsule  262  and are bent downward towards a mounting surface  265 , shown by the dashed line. Such packages include the small-outline transistor (SOT) package, the SC70 package, or any various leaded surface mount packages including the small outline package (SOP), super small outline package (SSOP), the thin small outline package (TSOP), and the thin super small outline package (TSSOP). The method is also applicable to non-surface mount leaded packages like the dual in-line package (DIP), or the single in-line package (SIP). 
     The process of fabricating the embedded die pad  261 B, exposed die pad  261 C and leads  261 A and  261 D is similar to that described above for the “no-lead” package  100 , except that the final etch leaves leads  261 A and  261 D extending laterally outward from die pads  261 B and  261 C, and leads  261 A and  261 D and then bent downward so that they mate with mounting surface  265 . Another difference in the fabrication process is that capsule  262  is formed initially as a separate capsule; the singulation process described above does not occur. 
     The embodiments of this invention described above are to be viewed as illustrative and not limiting. Numerous alternative embodiments within the broad scope of this invention will be apparent to persons of skill in the art.