Abstract:
Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]    The present invention is related to the following U.S. patent applications which are incorporated by reference:  
         [0002]    Ser. No. 10/116,612, filed Apr. 4, 2002, entitled, “Circuits And Systems For Limited Switch Dynamic Logic;” and  
         [0003]    Ser. No._______(Attorney Docket No. AUS920020430US1) entitled “A Limited Switch Dynamic Logic Circuit” filed concurrently herewith. 
     
    
     
       TECHNICAL FIELD  
         [0004]    The present invention relates to dynamic logic circuits, and in particular, to dynamic logic circuits for single and multilevel selection where the dynamic logic circuits have a dynamic switching factor to reduce power consumption.  
         BACKGROUND INFORMATION  
         [0005]    Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically, by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock each cycle may consume power even when the logical value of the output is otherwise unchanged.  
           [0006]    This may be appreciated by referring to FIG. 1. 1  illustrating an exemplary three-input OR dynamic logic gate, and the accompanying timing diagram, FIG. 1. 2 . Dynamic logic  100 , FIG. 1. 1 , includes three inputs a, b and c coupled to a corresponding gate of NFETs  102   a - 102   c . During an evaluate phase of clock  104 , N 1 , NFET  106  is active, and if any of inputs a, b or c are active, dynamic node  108  is pulled low, and the output OUT goes “high” via inverter  110 . Thus, referring to FIG. 1. 2 , which is illustrative, at t 1  input a goes high during a precharge phase N 2  of clock  104 . During the precharge phase N 2  of clock  104 , dynamic node  108  is precharged via PFET  112 . Half-latch PFET  114  maintains the charge on dynamic node  108  through the evaluate phase, unless one or more of inputs a, b or c is asserted. In the illustrative timing diagrams in FIG. 1. 2 , input a is “high” having a time interval t 1  through t 2  that spans approximately 2½ cycles of clock  104 , which includes evaluation phases,  116  and  118 . Consequently, dynamic node  108  undergoes two discharge-precharge cycles,  124  and  126 . The output node similarly undergoes two discharge-precharge cycles, albeit with opposite phase,  124  and  126 . Because the output is discharged during the precharge phase of dynamic node  108 , even though the Boolean value of the logical function is “true” (that is, “high” in the embodiment of OR gate  100 ) the dynamic logic dissipates power even when the input signal states are unchanged.  
           [0007]    Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments.  
           [0008]    Selection circuits, including shifting circuits and multiplexors, are used extensively within computer systems. Some of these selection circuits require multiple levels of selection, for example, a first input is selected from a plurality of first inputs wherein each of the first inputs are additionally selected from a plurality of second inputs. Computer systems employing dynamic logic may find that it is difficult to implement selection circuits for single and multilevel selection from many inputs because of the limitations of required precharge and evaluation times as well as the fact that outputs are not held during the precharge cycle.  
           [0009]    Limited switching dynamic logic (LSDL) circuits produce circuits which mitigate the dynamic switching factor of dynamic logic gates with the addition of static logic devices which serve to isolate the dynamic node from the output node. Co-pending U.S. patent application entitled, “CIRCUITS AND SYSTEMS FOR LIMITED SWITCH DYNAMIC LOGIC,” Ser. No. 10/116,612 filed Apr. 4, 2002 and commonly owned, recites such circuits. Additionally, LSDL circuits and systems maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement. Therefore, there is a need for the advantages of LSDL to be used to implement multilevel selection circuits with large numbers of inputs.  
         SUMMARY OF THE INVENTION  
         [0010]    The aforementioned needs are addressed by the present invention. Accordingly, there is an LSDL circuit configuration with a dynamic logic circuit having a corresponding dynamic node, and a plurality of logic input signals and selection signals, wherein the dynamic node has a precharge value during a first phase of a clock signal and an asserted value corresponding to a Boolean function of one or more input signals during the second phase of the clock signal. The value of the Boolean function is generated on one or more common nodes that are exclusively coupled to the dynamic node in response to one or more select signals. The dynamic node is further coupled to a static logic circuit which further generates an output and complement output of the LSDL circuit that is the value corresponding to the Boolean function of the values of the input signals selected by one of the select signals. The static logic section outputs the values of the dynamic node during the first phase of the clock signal and holds the value of the dynamic node during the second phase of the clock signal.  
           [0011]    Additionally, there are provided an integrated circuit (IC) and a data processing system including a plurality of logic devices for asserting a selected Boolean function of one or more input signals on a dynamic node. Also included is a static logic circuit coupled to the dynamic node wherein the static logic is configured to output the value of the dynamic node during a first phase of the clock signal while maintaining the output value of the logic device during a second phase of the clock signal; the output value represents the selected Boolean function of one or more input signals asserted on the dynamic node. Also a duration of the first phase of the clock signal is less than a duration of the second phase of the clock signal.  
           [0012]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which:  
         [0014]    [0014]FIG. 1. 1  illustrates, in partial schematic form, a dynamic logic gate which may be used in conjunction with the present invention;  
         [0015]    [0015]FIG. 1. 2  illustrates a timing diagram corresponding to the logic gate embodiment illustrated in FIG. 1. 1 ;  
         [0016]    [0016]FIG. 2. 1  illustrates, in partial schematic form, a standard LSDL device illustrating the static logic devices for isolating the dynamic node from the output node;  
         [0017]    [0017]FIG. 2. 2 . 1  illustrates, in partial schematic form, circuitry for incorporation in the logic tree of FIG. 2. 1  whereby the logic function performed is the logical OR of three input signals;  
         [0018]    [0018]FIG. 2. 2 . 2  illustrates, in partial schematic form, another circuit for incorporation in the logic tree of FIG. 2. 1  whereby the logic function performed is the logical AND of three input signals;  
         [0019]    [0019]FIG. 2. 3  illustrates a timing diagram corresponding to an embodiment of the dynamic logic device of FIG. 2. 1  in which the logic function performed is the logical OR of three input signals;  
         [0020]    [0020]FIG. 3. 1  illustrates, in block diagram form, an LSDL system that may incorporate LSDL selection circuits in accordance with embodiments of the present invention;  
         [0021]    [0021]FIG. 3. 2  illustrates a two-phase clock which may be used in conjunction with the logic system of FIG. 3. 1 ;  
         [0022]    [0022]FIG. 4 illustrates a high level block diagram of selected operational blocks within a central processing unit (CPU) incorporating the present inventive principles;  
         [0023]    [0023]FIG. 5 illustrates a data processing system configured in accordance with the present invention;  
         [0024]    [0024]FIG. 6. 1  and  6 . 2  are block diagrams of selection options used between an input and output word in an LSDL system employing embodiments of the present invention;  
         [0025]    [0025]FIG. 7. 1  is a circuit diagram of a selection circuit according to embodiments of the present invention;  
         [0026]    [0026]FIG. 7. 2  is a circuit diagram of another selection circuit according to embodiments of the present invention; and  
         [0027]    [0027]FIG. 8 is a generalized circuit diagram of a selection circuit according to embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0028]    In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. For example, specific logic functions and the circuitry for generating them may be described; however, it would be recognized by those of ordinary skill in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral by the several views.  
         [0029]    [0029]FIG. 2. 1  illustrates a limited switch dynamic logic (LSDL) device  200  used in accordance with the present inventive principles. In general, LSDL device  200  receives a plurality, n, of inputs  202   a  . . .  202   d  provided to logic tree  204 , and outputs a Boolean combination of the inputs. The particular Boolean function performed by LSDL device  200  is reflected in the implementation of logic tree  204  (accounting for the inversion performed by the inverter formed by n-channel field effect transistor (NFET)  206  and p-channel field effect transistor (PFET)  208 ). Logic tree  204  is coupled between the drain of PFET  212  and the drain of NFET  214 , node  216 . The junction of the logic tree  204  and the drain of PFET  212  forms dynamic node  210 .  
         [0030]    For example, FIG. 2. 2 . 1  illustrates logic tree  230  including three parallel connected NFETs,  231 ,  233  and  235 . Logic tree  230  may be used to provide a logic device generating the logical NOR of the three input signals coupled to corresponding ones of the gates of NFETs  231 ,  233  and  235 , a, b and c (as indicated by the Boolean expression  250  in FIG. 2. 2 . 1 ) and accounting for the inversion via NFET  206  and PFET  208 . Similarly, FIG. 2. 2 . 2  illustrates a logic tree  240  including three serially connected NFETs  237 ,  239  and  241 . Logic tree  240  may be used in conjunction with the logic device  200  to generate the logical NAND of the three input signals a, b and c (as indicated by the Boolean expression  260  in FIG. 2. 2 . 2 ).  
         [0031]    Returning to FIG. 2. 2 . 1 , dynamic node  210  is coupled to the common junction of the gates of NFET  206  and PFET  208  which invert the signal on dynamic node  210 . The inversion of the signal on dynamic node  210  is provided on Out  218   a . The transistor pair,  206  and  208 , is serially coupled to parallel NFETs  220  and  222 . NFET  220  is switched by clock signal  224 . Thus, during the evaluate phase of clock signal  224 , the inverter pair, NFET  206  and PFET  208  are coupled between the supply rails by the action of NFET  220 .  
         [0032]    The operation of LSDL device  200  during the evaluate phase, N 1 , may be further understood by referring to FIG. 2. 3  illustrating an exemplary timing diagram corresponding to the dynamic logic circuit of FIG. 2. 1  in combination with a logic tree embodiment  230  of FIG. 2. 2 . 1 . In this way, for purposes of illustration, the timing diagram in FIG. 2. 3  is the counterpart to the timing diagram in FIG. 1. 2  for the three-input OR gate  100  depicted in FIG. 1. 1 . As shown, input a is “high” or “true” between t 1 , and t 2 . In the evaluate phase, N 1  of clock signal  224 , dynamic node  210  is pulled down (intervals T 1 ). In these intervals, Out  218   a  is held high by the action of the inverter formed by transistors  206  and  208 , which inverter is active through the action of NFET  220  as previously described. In the intervening intervals, T 2 , dynamic node  210  is pulled up via the action of the precharge phase, N 2  of clock signal  224 , and PFET  212 . In these intervals, the inverter is inactive as NFET  220  is off. Out  218   a  is held “high” by the action of inverter  226  and PFET  228 . Note also that the output of inverter  226  may provide a complementary output, Out N  218   b . (Thus, with respect to the three-input logic trees in FIGS. 2. 2 . 1  and  2 . 2 . 2 , the corresponding logic device represents a three-input OR gate and a three-input AND gate, respectively.)  
         [0033]    Returning to FIG. 2. 1 , if the logic tree evaluates “high”, that is the Boolean combination of inputs  202   a  . . .  202   d  represented by logic tree  204 , evaluate high, whereby dynamic node  210  maintains its precharge, Out  218   a  is discharged via NFET  206  and NFET  220 . In the subsequent precharge phase, N 2 , of clock signal  224 , Out  218   a  is latched via the action of inverter  226  and NFET  222 . Thus, referring again to FIG. 2. 3 , corresponding to the three input OR embodiment of logic device  200  and logic tree  230  (FIG. 2. 2 . 1 ) at t 2  input a falls, and in the succeeding evaluate phase of clock signal  224 , dynamic node  210  is held high by the precharge. The inverter pair, NFETs  206  and  208 , are active in the evaluate phase of N 1 , of clock signal  224  because of the action of NFET  220 . Consequently, Out  218   a  falls (t 3 ). In the succeeding precharge phase, N 2  of clock signal  224 , Out  218   a  is latched in the “low” state, as previously described.  
         [0034]    In this way, LSDL device  200  in FIG. 2. 1 , may provide a static switching factor on Out  218   a , and likewise with respect to the complementary output Out N  218   b . It would also be recognized by artisans of ordinary skill that although LSDL device  200 , FIG. 2. 1 , has been described in conjunction with the particular logic tree embodiments of FIG. 2. 2 . 1  and FIG. 2. 2 . 2 , the principles of the present invention apply to alternative embodiments having other logic tree implementations, and such alternative embodiments fall within the spirit and the scope of the present invention.  
         [0035]    Note too, as illustrated in the exemplary timing diagram in FIG. 2. 3 , the duty factor of the clock signal may have a value that is less than fifty percent (50%). In such an embodiment, the evaluate phase, N 1 , of the clock signal may be shorter in duration than the precharge phase, N 2 . A clock signal having a duty factor less than fifty percent (50%) may be referred to as a pulse (or pulsed) clock signal. Note that a width of the evaluate phase may be sufficiently short that leakage from the dynamic node may be inconsequential. That is, leakage does not affect the evaluation of the node.  
         [0036]    In such a clock signal embodiment, the size of the precharge device (PFET  212  in the embodiment of FIG. 2. 1 ) may be reduced. It would be recognized by those of ordinary skill in the art that a symmetric clock signal has a fifty percent (50%) duty cycle; in an embodiment in which the duty cycle of the clock signal is less than fifty percent (50%), the size of the precharge device may be reduced concomitantly. In particular, an embodiment of the present invention may be implemented with a clock signal duty cycle of approximately thirty percent (30%). Additionally, while logic device  200  has been described from the perspective of “positive” logic, alternative embodiments in accordance with the present inventive principles may be implemented in the context of “negative” logic and such embodiments would also fall within the spirit and scope of the present invention.  
         [0037]    PFETs  208  and  228 , NFETs  206 ,  220 , and  222 , and inverter  226  make an implementation of a static latching portion of LSDL  200  that is used in LSDL selection circuits according to embodiments of the present invention. A dotted line has been drawn around this group of devices designating it as static latch portion (SLP)  250 . This designation is used in the following sections to simplify explanation of principles of the present invention.  
         [0038]    The preceding example in FIG. 2. 1  explains the operation of an LSDL circuit used to generate a Boolean combination of a number of inputs. In other logic circuits, it is desirable to generate selector functions wherein LSDL circuits are used to select between multiple inputs and direct the inputs to selected outputs. A selection circuit is often called a multiplexor (MUX) if it makes a selection between a plurality of inputs and directs one of the inputs to a particular output. MUX circuits are used extensively in computers. Because of the wide data busses used in modem computers, MUX circuits may require a large number of inputs. MUX circuits may be used to direct a particular bit (e.g., bit IB 0 ) from multiple input bytes (e.g., input byte  0  through byte N) to same bit (e.g., bit OB 0 ) in an output byte (e.g., output byte  0 ). Other types of selector circuits are used to permutate bits such that a particular bit (e.g., bit B 0 ) in a byte may be selected from multiple bits in another byte (e.g., bit B 0  or B 1 ). These selector circuits may be termed shift circuits or permutation circuits. Generally in logic permutation, a binary word has its bits reordered (permuted) and the number of possibilities is N factorial (N!) where N is the total number of bits in the word. Shifting may be thought of as a sub-set of general permutation.  
         [0039]    [0039]FIGS. 6. 1  and  6 . 2  are block diagrams illustrating how bits in an input word  620  comprising Byte  0   601 , Byte  1   602  through Byte N  603  may be directed to an output word  630  comprising Bytes  0   604 , Byte  1   605  through Byte N  606 . In FIG. 6. 1 , bit  0  of Byte  0   601  may be directed on path  610  to bit  0  of Byte  0   604 , path  611  to bit  0  of Byte  1   605  through Byte N  606 . FIG. 6. 1  represents a MUX function where one input (e.g., bit  0  of Byte  0   601 ) may be selectively directed to several outputs (e.g., bit  0  of Byte  0   604  to bit  0  of Byte N  606 ). FIG. 6. 2  represents more of a shift or permute function where multiple bits in particular bytes (e.g., bits  0  and  1  of Byte  0   601 ) may be directed to a particular bit (e.g., bit  0  of Byte  0   601 ). The operation illustrated in FIG. 6. 1  requires N selection devices (not shown) between the N bytes of the input word  620  and a particular bit (e.g., bit  0  of Byte  0   604 ) in the output word  630 .  
         [0040]    [0040]FIG. 7. 1  is a circuit diagram of an LSDL selection circuit according to embodiments of the present invention. Byte  0   701  represents an output byte of an output word (e.g., output word  630 ) which is selectively receiving data from a plurality of bytes from an input word (e.g., input word  620 ). Exemplary Byte  0   701  has eight bits, bit  0   702  through bit  7   704 . Each bit has a corresponding SLP circuit (e.g., SLP  706 ) substantially the same as SLP  280  explained in FIG. 2. 1 . The selection circuitry is shown for only SLP  706  and SLP  708 . Clock  705  is directed to each SLP circuit in Byte  0   701 . While each SLP circuit generates an output and complement output, only one output is shown for simplicity.  
         [0041]    The input to SLP  706  is coupled to dynamic node  711  which is precharged with precharge PFET  709  during the logic zero phase of clock signal  705 . Clock signal  705  is also coupled to the gate of NFET  731  which serves to isolate the circuitry between dynamic node  711  and node  733 . During the logic zero phase of clock signal  705 , NFET  731  is gated OFF allowing dynamic node  711  to precharge regardless of the states of the devices between dynamic node  711  and node  733 . A plurality of logic trees are coupled between dynamic node  711  and node  733 . In this example, the logic trees make up a MUX for data bit  0  from N input bytes. In the circuit of FIG. 7. 1 , data bit  0  from the N input bytes may be selectively coupled to bit  0   702  of Byte  0   701 . Since there are N bit zeroes (bit  0 ), there are N logic trees. NFET  713  and NFET  725  make up the logic tree for data bit  0  of input Byte  0  (D B 00 ), NFET  714  and NFET  726  make up the logic tree for data bit  0  of input Byte  1  (D B 10 ), and sequentially through to NFET  715  and NFET  727  which make up the logic tree from data bit  0  of input Byte N (D BN 0 ). NFET  713 , NFET  714 , and NFET  715  selectively couple their corresponding common nodes  719 ,  720  and  721  to dynamic node  711  in response to their select signals S 1  B 00 , S 1  B 10  and S 1  BN 0 , respectively. The select signals (S 1  B 00 , S 1  B 10  and S 1  BN 0 ) are termed “one hot” signals which indicates that at any one select time only one signal is a logic true activating its corresponding select device (e.g., NFET  713 ). Because of the previously explained latching function of the SLP circuits, the precharge portion of the clock signal  705  is longer than the evaluate portion. Since the precharge time is longer, the precharge devices are smaller and have less capacitance. This allows many parallel devices to be coupled to dynamic node  711  resulting in a large number of inputs forming a many to one MUX function.  
         [0042]    All the bits in Byte  0   701  have a corresponding selection circuit. The circuitry for bit  7  of Byte  0   701  is also shown for example. Similar to bit  0 , data bit  7  from the N input bytes may be selectively coupled to bit  7   704  of Byte  0   701 . Since there are N bit sevens (bit  7 ), again there are N logic trees. NFET  716  and NFET  728  make up the logic tree for data bit  7  of input Byte  0  (D B 07 ), NFET  717  and NFET  729  make up the logic tree for data bit  7  of input Byte  1  (D B 17 ), and sequentially through to NFET  718  and NFET  730  which make up the logic tree from data bit  7  of input Byte N (D BN 7 ). NFET  716 , NFET  717 , and NFET  718  selectively couple their corresponding common nodes  722 ,  723  and  724  to dynamic node  712  in response to their select signals S 1  B 00 , S 1  B 10  and S 1  BN 0 , respectively. In the example of FIG. 7. 1 , the selection is byte-wise. This means that if any bit in a particular input byte (e.g., input Byte  1 ) is directed to output Byte  0   701 , then all the bits of that byte are directed to Byte  0   701 . This would insure that all the select signals (S 1  B 00 -S 1  BN 0 ) are the same for each bit in the byte.  
         [0043]    To further explain the operation of the selection circuitry of FIG. 7. 1 , only one bit need be explained in detail as the selection of all other bits operate the same. Assume then that S 1  B 10  is a logic one and all other selection signals are a logic zero (one-hot principle). This means that the bits from input Byte  1  are directed to output Byte  0   701 . Also assume that the particular bit  0  from Byte  1  of the input word (D B 10 ) is also a logic one. S 1  B 00  is activated coincident with the precharge phase (logic zero) of clock signal  705 . PFET  709  turns ON and NFET  731  turns OFF isolating the logic trees, and in particular, the logic tree comprising the series connection of NFET  714  and NFET  726 . Since S 1  B 10  is a logic one both dynamic node  711  and common node  720  are precharged during the precharge phase of clock signal  705 . This insures that when the values asserted on dynamic node  711  by the state of D B 10  during the evaluation phase of clock signal  705  is correct. For example, assume the previous state of D B 10  was a logic one and common node  720  was discharged to ground. If the next state of D B 10  is a logic zero, then node  720  would modify dynamic node  711  if it had not also been precharged along with dynamic node  711  during the precharge phase of clock signal  705 . When clock signal  705  transitions to its evaluate phase, PFET  709  is turned OFF and NFET  731  is turned on allowing a logic one state of D B 10  to discharge dynamic node  711  or a logic zero state of D B 10  to leave dynamic node  711  in a logic one charged state. SLP  706  asserts the logic one value of dynamic node  711  to output bit  0   702  of Byte  0   701 . Feedback from the output of SLP  706  then latches the output state so that it remains during the next precharge phase of clock signal  705 .  
         [0044]    [0044]FIG. 7. 2  is another selection circuit according to embodiments of the present invention illustrating multilevel selection. Again, Byte  0   701  represents an output byte of an output word (e.g., output word  630 ) which is selectively receiving data from a plurality of bytes from an input word (e.g., input word  620 ). Exemplary Byte  0   701  has eight bits, bit  0   702  through bit  7   704 . Each bit has a corresponding SLP circuit (e.g., SLP  706 ) substantially the same as SLP  280 , explained in FIG. 2. 1 . The selection circuitry is shown for only SLP  706  and SLP  708 . Clock  705  is directed to each SLP circuit in Byte  0   701 . While each SLP circuit generates an output and complement output, only one output is shown for simplicity.  
         [0045]    PFET  709  turns ON and NFETs  760  and  761  are gated OFF during the precharge phase of clock signal  705 . Dynamic node  741  is precharged by PFET  709  during the precharge phase of clock signal  705 . Section circuit  772 , comprising NFET  750  and NFET  751 , selectively couples dynamic node  741  to node  763  and  762  in response to select signals S 20  and S 20 N. S 20  and S 20 N are complement logic signals and therefore are one-hot select signals. The logic tree coupled to common node  763  selects between D B 01  and D B 11  (bit  0  and bit  1  of input Byte  1 ) in response to select signals S 10  and S 10 N. Likewise, the logic tree coupled to common node  762  selects between D B 02  and D B 12  (bit  0  and bit  1  of input Byte  2 ) in response to select signals S 10  and S 10 N. If S 10  is a logic one, then the value of D B 01  or D B 02  will be asserted on dynamic node  741  depending on the states of S 20  and S 20 N during the assertion phase of clock signal  705 . During the precharge phase, either common node  763  or  762  will be precharged along with dynamic node  741  guaranteeing that whichever logic tree is selected by S 20 /S 20 N will have its common node precharged. Other logic tree configurations may be used with the one-hot selection and still be within the scope of the present invention.  
         [0046]    [0046]FIG. 8 is a circuit diagram illustrating a generalized selection circuit according to embodiments of the present invention. An SLP  801  having output  818  and complementary output  819  is coupled to clock signal  804  and a dynamic node  806 . A plurality of logic trees (e.g.,  802  and  803 ) are coupled to dynamic node  806  with devices NFETs  810  and  811  in response to one-hot selection signals  1  HS 1  and  1  HSn. The logic trees coupled to a dynamic node  806  may have different numbers of multiple inputs (e.g.,  814  and  815 ) and may differ in their functionality. There is a practical limit in the number of series devices between a dynamic node  806  and an assertion device (e.g., NFET  816  and NFET  817 ). The one-hot principle for controlling the selection devices (e.g.,  1 HS 1  and  1 HSn) is required to insure that the common node on the logic trees is precharged along with the dynamic node.  
         [0047]    [0047]FIG. 3. 1  illustrates a portion  300  of a data processing system incorporating LSDL circuits in accordance with the present inventive principles. System portion  300  may be implemented using a two-phase clock signal (denoted clock  1  and clock  2 ). A timing diagram which may be associated with system portion  300  will be discussed in conjunction with FIG. 3. 2 . LSDL blocks  302   b  that may be clocked by a second clock signal phase, clock  2 , alternates with LSDL block  302   a  clocked by the first clock signal phase, clock  1 . Additionally, system portion  300  may include static logic elements  304  between LSDL blocks. Typically, static circuit blocks  304  may include gain stages, inverters or static logic gates. Static circuit blocks  304  are differentiated from LSDL blocks  302   a  and  302   b  as they do not have dynamic nodes that have a precharge cycle. However, alternative embodiments may include any amounts of static logic. Additionally, as previously mentioned, an embodiment of system portion  300  may be implemented without static circuit blocks  304 .  
         [0048]    [0048]FIG. 3. 2  illustrates a timing diagram which may correspond to logic system employing a two-phase, pulsed clock signal, such as system portion  300 , FIG. 3. 1 , in accordance with the present inventive principles. The LSDL circuits evaluate during the LSDL evaluate, or drive, portion  306  of their respective clock signals. As previously described, the duty factor of each of clock  1  and clock  2  may be less than fifty percent (50%). The width of the LSDL drive portions  306  of the clock signals need only be sufficiently wide to allow the evaluate node (such as dynamic node  210 , FIG. 2. 1 ) to be discharged through the logic tree (for example, logic tree  204 , FIG. 2. 1 ). As previously described, the duration of the drive portion may be sufficiently narrow that leakage from the evaluation may be inconsequential. Consequently, LSDL circuits are not particularly sensitive to the falling edge of the clock signals, and in FIG. 3. 2 , the falling portion of the evaluate phase  306  of the clock signals has been depicted with cross-hatching. As noted herein above, the duty factor of clock  1  and clock  2  may be approximately thirty percent (30%) in an exemplary embodiment of the present invention. (It would be appreciated, however, that the present inventive principles may be incorporated in alternative embodiments which have other duty factors.) During the precharge portion  308  of the clock signals, the dynamic node (for example, dynamic node  210 , FIG. 2. 1 ) is precharged, as previously discussed. Clock  2  is 180° (π radians) out of phase with clock  1  (shifted in time one-half of period T). Thus as shown, the evaluate portion  306  of clock  2  occurs during the precharge phase  308  of clock  1 . Because in LSDL circuits, the output states may not change during the evaluate phase of the driving clock signal; the inputs to LSDL blocks, for example, LSDL blocks  302   b , FIG. 3. 1 , are stable during the evaluate phase of the corresponding driving clock signal, clock  2 . The time interval, between the end of the evaluate portion  306  of clock  1  and the rising edge of clock  2  may be established by the setup time of the LSDL, and the evaluation time of the static blocks, if any (for example, static blocks  304 , FIG. 3. 1 ). The time, Tau  301 , together with duty factor may determine the minimum clock signal period for a particular LSDL circuit implementation. Thus, a system portion  300 , FIG. 3. 1  having a two-phase clock signal effects two dynamic evaluations per period, T, of the driving clock signals. It would be further appreciated by those of ordinary skill in the art that, in general, the present inventive principles may be incorporated in alternative embodiments of an LSDL system having a plurality, n, of clock signal phases. Such alternative embodiments would fall within the spirit and scope of the present invention.  
         [0049]    An LSDL system in accordance with the principles of the present invention, such as system  300 , FIG. 3. 1 , may be used, in an exemplary embodiment, in an arithmetic logic unit (ALU). A typical ALU architecture requires a significant number of exclusive-OR (XOR) operations. The XOR of two Boolean values requires having both senses of each of the Boolean values, that is, both the value and its complement (a⊕b=ab′+a′b). As previously described, use of dual rail dynamic logic to implement such functionality obviates the advantages in area and power otherwise obtained by dynamic logic. A data processing system including an ALU embodying the present inventive principles is illustrated in FIG. 4. The MUX function illustrated in FIG. 7. 1  is also used in many areas of a data processing system when data from many sources may be selectively coupled to a single processing unit. The function illustrated in FIG. 7. 2  may be used to modify or permutate the bits in a byte for example by shifting bit  1  to bit  0 , bit  2  to bit  1 , etc. The permute function is common in many microprocessor media units.  
         [0050]    [0050]FIG. 4 is a high level functional block diagram of selected operational blocks that may be included in a central processing unit (CPU)  400 . In the illustrated embodiment, CPU  400  includes internal instruction cache (I-cache)  440  and data cache (D-cache)  442  which are accessible to memory (not shown in FIG. 4) through bus  412 , bus interface unit  444 , memory subsystem  438 , load/store unit  446  and corresponding memory management units: data MMU  450  and instruction MMU  452 . In the depicted architecture, CPU  400  operates on data in response to instructions retrieved from I-cache  440  through instruction dispatch unit  448 . Dispatch unit  448  may be included in instruction unit  454  which may also incorporate fetch unit  456  and branch processing unit  458  which controls instruction branching. An instruction queue  460  may interface fetch unit  456  and dispatch unit  448 . In response to dispatched instructions, data retrieved from D-cache  442  by load/store unit  446  can be operated upon by one of fixed point unit (FXU)  460 , FXU  462  or floating point execution unit (FPU)  464 . Additionally, CPU  400  provides for parallel processing of multiple data items via vector execution unit (VXU)  466 . VXU  466  includes vector permute unit  468  which performs permutation operations on vector operands, and vector arithmetic logic unit (VALU)  470  which performs vector arithmetic operations, which may include both fixed-point and floating-point operations on vector operands. VALU  470  may be implemented using LSDL in accordance with the present inventive principles, and in particular may incorporate LSDL systems, of which LSDL system  300 , FIG. 3. 1  is exemplary. Other units may employ LSDL selection circuits according to embodiments of the present invention.  
         [0051]    A representative hardware environment  500  for practicing the present invention is depicted in FIG. 5, which illustrates a typical hardware configuration of a data processing system in accordance with the subject invention having CPU  400 , incorporating LSDL selection circuits according to the present inventive principles, and a number of other units interconnected via system bus  412 . The data processing system shown in FIG. 5 includes random access memory (RAM)  514 , read only memory (ROM)  516 , and input/output (I/O) adapter  518  for connecting peripheral devices such as disk units  520  to bus  412 , user interface adapter  522  for connecting keyboard  524 , mouse  526 , and/or other user interface devices such as a touch screen device (not shown) to bus  412 , communication adapter  534  for connecting the system to a data processing network, and display adapter  536  for connecting bus  412  to display device  538 . Note that CPU  400  may reside on a single integrated circuit.  
         [0052]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.