Abstract:
A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary comparator according to an enable signal.

Description:
FIELD OF INVENTION  
       [0001]     The present invention relates to a 2-bit binary comparator and a binary comparing device using the same to apply to digital logic circuit design.  
       DESCRIPTION OF PRIOR ART  
       [0002]     A binary comparing device in digital logic circuit design may have various forms depending on designer&#39;s intension.  
         [0003]     For example,  FIG. 1  shows a typical binary comparing device in which a number of parallel-coupled exclusive NORs (XNORs) are ANDed. That is, the typical comparing device includes a first exclusive NOR gate  110  receiving two signals A 0 , B 0 , a second exclusive NOR gate  111  receiving two signals A 1 , B 1 , a third exclusive NOR gate  112  receiving two signals A 2 , B 2 , a fourth exclusive NOR gate  113  receiving two signals A 3 , B 3 , a first AND gate  115  receiving the outputs of the first and second exclusive NOR gates  110 ,  111 , a second AND gate  116  receiving the outputs of the third and fourth exclusive NOR gates  112 ,  113 , and a third AND gate  117  receiving the first and second AND gates  115 ,  116 .  
         [0004]     In such a binary comparing device, if the inputs of one or more XNOR gates are identical even though the entire bits do not coincide with each other when the respective input signals transit, the output signal levels of the coinciding XNOR gates transit so as to generate transition current and, accordingly, lead power consumption. Particularly, if the compared signal is a periodic recursive signal such as a count signal from a counter, there is power consumption due to transition current whenever the count signal changes though the entire bits do not coincide.  
         [0005]     To solve such a problem, as shown in  FIG. 2 , there is introduced a 2-bit comparator for comparing two signals that are inputted only when an enable signal is applied (see FIG. 1 in U.S. Pat. No. 4,797,650).  
         [0006]     The 2-bit comparator shown in  FIG. 2  operates as will be described below. When a carry-in port  210  is “H”, both of MOSFETs  211 ,  217  are turned on. When a first bit IN 1  is low potential, a MOSFET  221  is turned off and a MOSFET  226  is turned on. When a second bit IN 2  is “L”, both of MOSFETs  220 ,  225  are turned off. Thus, a carry-out port  212  outputs the high potential on the IN 2  BAR through the transistors  226 ,  217  so that the circuit can indicate coincidence of the bits.  
         [0007]     On the contrary, when the second bit IN 2  is “H”, both of MOSFETs  220 ,  225  are turned on and low potential is applied on the IN 2  BAR. Thus, the carry-out port  212  is to be connected to a ground voltage through three paths, i.e., the MOSFETs  226 ,  217 , the MOSFETs  225 ,  217  and the MOSFETS  211 ,  220 , so as to output a ground potential and finally indicate discordance of the bits exactly.  
         [0008]     On the other hand, the 2-bit comparator such as in  FIG. 2  uses 9 MOSFETs and one inverter. In other words, since the inverter should use two transistors, the 2-bit comparator should include 11 transistors, which leads large layout area.  
         [0009]     Further, when the entire coincide in  FIG. 1 , operating speed is decreased due to a number of stages that the output signal should go through.  
       SUMMARY OF INVENTION  
       [0010]     It is, therefore, an object of the present invention to provide a 2-bit binary comparator capable of reducing power consumption and layout area by using an enable signal.  
         [0011]     It is another object of the present invention to provide a 2-bit binary comparator capable of improving operational speed.  
         [0012]     In accordance with an aspect of the present invention, there is provided a 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary comparator according to an enable signal.  
         [0013]     In accordance with another aspect of the present invention, there is provided a binary comparing device, including: a first 2-bit binary comparator for logically combining a first and a second input signals by using a power voltage as an enable signal; and a second 2-bit binary comparator for logically combining a third and a fourth input signals by using the output of the first 2-bit binary comparator as an enable signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0015]      FIG. 1  is a typical binary comparing device;  
         [0016]      FIG. 2  is a 2-bit comparator;  
         [0017]      FIG. 3A  is a detailed circuit diagram of a 2-bit binary comparator in accordance with the present invention;  
         [0018]      FIG. 3B  represents symbols of  FIG. 3A ;  
         [0019]      FIG. 4  is a binary comparing device in accordance with present invention; and  
         [0020]      FIG. 5  is a simulation waveform diagram of a 2-bit binary comparator in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0021]     Hereinafter, a 2-bit binary comparator in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0022]     A 2-bit binary comparator of the present invention further includes an enable port to perform a comparison operation when input signals of a previous stage 2-bit binary comparator coincide with each other. Accordingly, even if the input bits of the corresponding 2-bit binary comparator coincide with each other, the output of the comparator does not change when the input bits of the previous stage 2-bit binary comparator does not coincide with each other. Therefore, unnecessary transition current can be avoided. Further, since the output of the final stage comparator is the output of the entire comparator, the transfer delay can be improved.  
         [0023]     There is provided Table 1 showing the truth table of a 2-bit binary comparator in accordance with the present invention.  
                                   TABLE 1                                   EN   A   B   Z                           0   X   X   0           1   0   0   1           1   0   1   0           1   1   0   0           1   1   1   1                         where X means don’t-care condition.             
 
         [0024]     As can be seen in Table 1, the 2-bit binary comparator of the present invention operates as a typical XOR gate only when an enable signal EN is applied but has no output Z if there is applied no enable signal EN. That is, when the enable signal is “0”, the output signal maintains “0” state, constantly. When the enable signal is “1”, the output signal has its state depending on logic state of two input signals. If the logic state of the two input signals are identical, “1” is outputted and, if other wise, “0” is outputted.  
         [0025]      FIG. 3A  is a detailed circuit diagram of a 2-bit binary comparator in accordance with the present invention and  FIG. 3B  represents symbols of  FIG. 3A .  
         [0026]     It will be described for construction and operation of the 2-bit binary comparator of the present invention.  
         [0027]     Sources of a first and a second P-channel MOSFETs  301 ,  302  are coupled to input ports A, B, respectively. The gate of the first P-channel MOSFET  301  is coupled to the source of the second P-channel MOSFET  302  and the gate of the second P-channel MOSFET  302  is coupled to the source of the first P-channel MOSFET  301 . Drains of the first and second P-channel MOSFETs  301 ,  302  are coupled to a first node Node 1 .  
         [0028]     Further, a first and a second N-channel MOSFETs  303  and  304  are serially coupled to each other. The first N-channel MOSFET  303  has a first terminal coupled to a first node Node 1  and a second terminal coupled to a first terminal of the second N-channel MOSFET  304 . A second terminal of the second N-channel MOSFET  304  is coupled to a ground voltage. The first and second N-channel MOSFETs  303 ,  304  are controlled with the input signals A and B respectively.  
         [0029]     A third N-channel MOSFET  305  is controlled with the enable signal EN and has a source coupled to the first node Node 1  and a drain coupled to a second node Node 2 . A third P-channel MOSFET  306  is controlled with enable signal EN and has a source coupled to a power voltage Vdd and a drain coupled to the second node Node 2 . An inverter  307  inverts the logic value of the second node Node 2 .  
         [0030]     When the enable signal is “0”, the third N-channel MOSFET  305  is turned off and the third P-channel MOSFET  306  is turned on to make the second node Node 2  “1” so as to make the output Z “0”.  
         [0031]     When the enable signal is “1”, the third N-channel MOSFET  305  is turned on and the third P-channel MOSFET  306  is turned off so that the output Z is determined depending on the logic level of the first node Node 1 . For example, if both of the two input signal A, B are “0”, both of the first and second P-channel MOSFETs  301 ,  302  are turned on and both of the first and second N-channel MOSFETs  303 ,  304  are turned off to make the first node Node 1  “0” so as to make the output Z “1”. Otherwise, if the two input signals A, B are “1” and “0”, respectively, the first P-channel MOSFET  301  is turned on, the second P-channel MOSFET  302  is turned off, the first N-channel MOSFET  303  is turned off and the second N-channel MOSFET  304  is turned on to make the first node Node 1  “1” so as to make the output Z “0”. On the other hand, if both of the two input signals A, B are “1”, both of the first and second P-channel MOSFETs  301 ,  302  are turned off and the first and second N-channel MOSFETs  303 ,  304  are turned on to make the first node Node 1  “0” so as to make the output Z “1”.  
         [0032]      FIG. 4  is a binary comparing device in accordance with present invention.  
         [0033]     The binary comparing device of the present invention includes a first 2-bit binary comparator  401  enabled by the power voltage for logically combining a first and a second input signals, and a second 2-bit binary comparator  402  enabled by the output of the first 2-bit binary comparator  401  for logically combining a third and a fourth input signals.  
         [0034]     It will be described for the operation of the binary comparing device as shown in  FIG. 4 .  
         [0035]     When the logic state of the first and second input signals coincide with each other, the first 2-bit binary comparator  401  outputs “1”. The second 2-bit binary comparator  402  outputs “1” when the third and fourth input signals coincide with each other by using the output of the first 2-bit binary comparator  401  as an enable signal. Further, a third to a N-th 2-bit binary comparators  403 , . . . ,  40 N operate as similar as the second 2-bit binary comparator  402 . Accordingly, the number of transitions of the entire comparators is reduced to decrease power consumption. Particularly, if the input signals are provided from a recursive up/down-counter, the optimal operation can be obtained. That is, assuming the up-counter be used, if the most significant bit is inputted to the first 2-bit binary comparator, the second significant bit to the second 2-bit binary comparator and so on, the final output can be obtained after minimal N times of comparator transition operations since the input values changes from the most significant bit to the least significant bit. From this, fast comparison can be accomplished.  
         [0036]      FIG. 5  is a simulation waveform diagram of a 2-bit D binary comparator in accordance with the present invention.  
         [0037]     As can be seen, when the enable signal EN is “0”, the output is “0”, and when the enable signal EN is “1”, the output exists.  
         [0038]     As described above, by using the enable signal, the present invention can avoid unnecessary transition current and accordingly reduce power consumption. Further, by forming the 2-bit binary comparator with 6 transistors and one inverter, i.e., 8 transistors, the circuit area can be reduced. Further, the 2-bit binary comparing device of the present invention can improve operational speed with improved transfer delay.  
         [0039]     The present application contains subject matter related to the Korean patent application No. KR 2004-59527, filed in the Korean Patent Office on Jul. 29, 2004, the entire contents of which being incorporated herein by reference.  
         [0040]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.