Abstract:
A controlling circuit for a fan includes three comparators, a capacitor, and a thermistor. When the temperature around the thermistor changes, the resistance of the thermistor changes. The comparators control the charging and discharging time of the capacitor, thereby generating a corresponding pulse width modulation signal to the fan according to the temperature, to adjust the speed of the fan.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a controlling circuit for a fan. 
     2. Description of Related Art 
     Electronic elements, such as central processing units, generate a lot of heat when operating; hence, a fan may be used to dissipate the heat. A control chip, such as a south bridge chip, together with a temperature sensor, may be used to control the speed of a fan to regulate the temperature of an electronic element. However, if the control chip malfunctions, the speed of the fan may not be able to dissipate the heat adequately, which may result in damage to the electronic elements. Also, the fan may continuously run at maximum speed and thereby wasting energy. 
     Therefore, there is room for improvement in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views. 
       The FIGURE is a circuit diagram of an embodiment of a controlling circuit for a fan of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The FIGURE illustrates an embodiment of a controlling circuit for a fan  20  arranged in a computer. The controlling circuit includes an amplifier U 1 , three comparators U 2 -U 4 , seven resistors R 1 -R 7 , three capacitors C 1 -C 3 , and a thermistor RT 1 . In the embodiment, the thermistor RT 1  is a positive temperature coefficient thermistor. Resistance of the thermistor RT 1  will increase when the temperature of the surrounding area where the thermistor RT 1  is deposited increases. Alternatively, the resistance of the thermistor RT 1  will decrease when the temperature decreases. 
     An inverting input terminal of the comparator U 4  is coupled to a power terminal 6 Vd, and also coupled to a non-inverting input terminal of the comparator U 3 . A power terminal of the comparator U 4  is coupled to a power source 12 Vd, and a ground terminal of the comparator U 4  is connected to ground. An output terminal of the comparator U 4  is coupled to a non-inverting input terminal of the comparator U 4  through the resistor R 6 , and is also coupled to an inverting input terminal of the comparator U 3  through the resistor R 7  and the thermistor RT 1  in that order. A non-inverting input terminal of the comparator U 3  is connected to ground through the capacitors C 1  and C 2  connected in parallel. A ground terminal of the comparator U 3  is connected to ground. A power terminal of the comparator U 3  is connected to the power source 12 Vd. An output terminal of the comparator U 3  is coupled to the inverting input terminal of the comparator U 3  through the capacitor C 3  and is coupled to the non-inverting input terminal of the comparator U 4  through the resistor R 5 . The output terminal of the comparator U 3  is also coupled to an output terminal of the comparator U 2  through the resistors R 4  and R 3  in that order. 
     An inverting input terminal of the amplifier U 1  is coupled to a power source 3 Vd through the resistor R 1 . A non-inverting input terminal of the amplifier U 1  is coupled to a power source 3.3 Vd. A ground terminal of the amplifier U 1  is connected to ground, and a power terminal of the amplifier U 1  is coupled to the power source 12 Vd. An output terminal of the amplifier U 1  is coupled to an inverting input terminal of the comparator U 2 , and is also coupled to the inverting input terminal of the amplifier U 1  through the resistor R 2 . The output terminal of the amplifier U 1  is configured to output an amplified voltage to the inverting input terminal of the comparator U 2 . A power terminal of the comparator U 2  is coupled to the power source 12 Vd, and a ground terminal of the comparator U 2  is connected to ground. The output terminal of the comparator U 2  is connected to the fan  20  in order to output a pulse width modulation (PWM) signal to the fan  20 , thereby controlling the speed of the fan  20 . The non-inverting input terminal of the comparator U 2  is connected to a node between the resistors R 4  and R 3 . 
     When the computer is turned on, the power sources 6 Vd and 12 Vd provide power, the output terminal of the comparator U 4  and the inverting input terminal of the comparator U 3  have no voltage, and the voltage of the non-inverting input terminal of the comparator U 3  is greater than that of the inverting input terminal of the comparator U 3 . Hence, the output terminal of the comparator U 3  outputs a high voltage, thereby charging the capacitor C 3 , where the charging time T1 of the capacitor C 3  is (R 7 +RT 1 )*C 3 , C 3  stands for the capacitance of the capacitor C 3 , R 7  stands for the resistance of the resistor R 7 , and RT 1  stands for the resistance of the thermistor RT 1 . At the same time, the voltages of the non-inverting input terminals of the comparators U 2  and U 4  are increased when the capacitor C 3  is charged. When the voltage of the non-inverting input terminal of the comparator U 4  is greater than the voltage of the inverting input terminal of the comparator U 4 , the comparator U 4  outputs a high voltage to the inverting input terminal of the comparator U 3 . The output terminal of the comparator U 3  will output a low voltage when the voltage of the inverting input terminal of the comparator U 3  is greater than that of the non-inverting input terminal of the comparator U 3 . Accordingly, as the voltage of the output terminal of the comparator U 3  changes from high level to low level, the capacitor C 3  discharges, and the discharging time T2 of the capacitor C 3  is R 4 *C 3 , where R 4  stands for the resistance of the resistor R 4  and C 3  stands for the capacitance of the capacitor C 3 . The voltages of the non-inverting input terminal of the comparators U 2  and U 4  decrease gradually. On the condition that the voltage of the non-inverting input terminal of the comparator U 4  is less than the voltage of the inverting input terminal of the comparator U 4 , the output terminal of the comparator U 4  will output no voltage, and the output terminal of the comparator U 3  outputs a high voltage to charge the capacitor C 3 . 
     When the voltage of the non-inverting input terminal of the comparator U 2  is greater than the voltage of the inverting input terminal of the amplifier U 1 , the comparator U 2  outputs a high pulse width modulation (PWM) signal. Otherwise, the output terminal of the comparator U 2  outputs a low PWM signal. Accordingly, the PWM signal with a duty cycle of T1/(T1+T2) is transmitted to the fan  20  through the output terminal of the comparator U 2 . 
     On the condition that the temperature increases, the resistance of the thermistor RT 1  is increased, the charging time T1 of the capacitor C 3  is increased, and the value of the duty cycle of T1/(T1+T2) is increased. Hence a duty cycle of the PWM signal is also increased, and the fan  20  will speed up to dissipate more heat. Otherwise, when the temperature decreases, the resistance of the thermistor RT 1  decreases, the charging time T1 of the capacitor C 3  decreases, and the value of the duty cycle of T1/(T1+T2) decreases. Accordingly, the duty cycle of the PWM signal also decreases, and the fan  20  will slow down, to save energy. 
     While the disclosure has been described by way of example and in terms of a preferred embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.