Abstract:
Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate.

Description:
CROSS REFERENCE TO OTHER APPLICATIONS 
       [0001]    This application claims priority to U.S. Provisional Patent Application No. 61/703,708 entitled EXTREMELY THIN PACKAGE filed Sep. 20, 2012 which is incorporated herein by reference for all purposes. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    Typical chip manufacturing assembly processes include applying EMC (Epoxy Molding Compound) to cover the entire area of a device, submitting the device for plating on lead, and then separating the device via a sawing blade. EMC fillers protect an integrated circuit from light emission induced leakage and moisture penetration but also contribute to overall package thickness.  FIG. 1  illustrates a typical device structure resulting from the aforementioned assembly process. As depicted, the EMC surrounding the integrated circuit (i.e., chip) significantly contributes to the resulting device dimensions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings. 
           [0004]      FIG. 1  illustrates a prior art device structure resulting from a typical assembly process. 
           [0005]      FIG. 2A  illustrates an embodiment of a package structure resulting from an assembly process that includes a grinding process. 
           [0006]      FIG. 2B  illustrates an embodiment of a package structure resulting from an assembly process that includes a grinding process. 
           [0007]      FIGS. 3A-3Q  illustrate an embodiment of an assembly process for generating extremely thin package structures. 
           [0008]      FIG. 3R  illustrates example dimensions of devices resulting from the disclosed assembly process. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions. 
         [0010]    A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims, and the invention encompasses numerous alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example, and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. 
         [0011]    Various techniques for achieving thinner package thicknesses are disclosed herein. As further described, the disclosed assembly process includes a grinding process for reducing the total device thickness. The grinding process facilitates a plurality of types of thinner package structures. In some embodiments, the grinding process is employed to leave the backside of an integrated circuit (i.e., chip) exposed, which may be acceptable for a non-sensitive light emission device. Alternatively, adhesion tape may be applied on a ground surface, for example, to protect an integrated circuit from light emission induced leakage and moisture penetration. 
         [0012]      FIG. 2A  illustrates an embodiment of a package structure resulting from an assembly process that includes a grinding process. As depicted, package structure  200  includes an integrated circuit (i.e., chip)  202  in part surrounded by EMC (Epoxy Molding Compound)  204  and connected to leadframe (L/F) or substrate  206  via bumps  208 . In some embodiments, package structure  200  results from submitting the entire leadframe or substrate for top-side grinding after EMC injection until at least the backside of the chip is exposed and/or the desired thickness is achieved. In the given example, package structure  200  includes adhesion tape (i.e., laminating film)  210  applied on top of the device (i.e., the backside of flipped chip  202 ) to protect the chip. Package structure  200  may comprise, for example, an extremely thin DFN (dual flat no-lead) or QFN (quad flat no-lead) package. 
         [0013]      FIG. 2B  illustrates an embodiment of a package structure resulting from an assembly process that includes a grinding process. As depicted, package structure  220  includes an integrated circuit (i.e., chip)  222  in part surrounded by EMC  224  and connected to leadframe or substrate  226  via bumps  228 . In some embodiments, package structure  220  results from submitting the entire leadframe or substrate for top-side grinding after EMC injection until at least the backside of the chip is exposed and/or the desired thickness is achieved. In this example, the backside of integrated circuit  222  is left exposed, i.e., no adhesion tape is applied as in the embodiment of  FIG. 2A . Package structure  220  may comprise, for example, an exposed silicon extremely thin DFN or QFN package. 
         [0014]      FIGS. 3A-3Q  illustrate an embodiment of an assembly process for generating extremely thin package structures such as those described with respect to  FIGS. 2A-2B .  FIG. 3A  illustrates dicing a wafer  300  to separate each chip  302  in wafer  300 . As further depicted in  FIG. 3A , each chip  302  subsequently undergoes flipping, flux dipping, and mounting onto a leadframe or substrate  304 .  FIG. 3B  illustrates flip chip mounting onto the leadframe or substrate  304 .  FIG. 3C  illustrates a reflow step to connect the bumps between chip  302  and leadframe or substrate  304 . The reflow temperature profile depends on bump composition and character.  FIG. 3D  illustrates a molding step, which is performed, for example, by an injection mold tool. As depicted, chip  302  is surrounded by EMC  306  during this step. 
         [0015]      FIGS. 3A-3D  also illustrate backside adhesion tape  305 , which is applicable for the embodiments in which chip  302  is mounted to leadframe  304 .  FIG. 3E  illustrates a step for removing backside adhesion tape  305 .  FIG. 3F  illustrates a lead plating step for providing a lead finish  307  in the embodiments in which chip  302  is mounted to leadframe  304 . In embodiments in which chip  302  is mounted to substrate  304 , the substrate&#39;s terminals/leads already have a pre-plated finish.  FIG. 3G  illustrates a leadframe/substrate mounting (i.e., backside laminating) step. As depicted, backside mounting tape  308  is applied in preparation for subsequent top-side grinding. 
         [0016]      FIG. 3H  illustrates a grinding step via which top-side grinding is performed using grinding wheel  310 . This top-side grinding process is specially introduced into the assembly process to achieve a desired package thickness and is not used in other existing DFN/QFN processes.  FIG. 31  illustrates continued top-side grinding until desired chip and/or total device thicknesses are achieved. In some embodiments, the grinding is stopped once the backside of chip  302  is exposed. Alternative, as depicted in  FIG. 31 , the grinding is stopped once a desired chip thickness is achieved. Once the grinding is complete, the ground surface is polished, for example, to release the shear stress introduced during grinding and/or increase the adhesion between the ground surface and a top adhesion film (which is used for extremely thin DFN/QFN packages such as package structure  200  depicted in  FIG. 2A ). 
         [0017]      FIG. 3J  illustrates a de-taping step in which backside mounting tape  308  is removed.  FIG. 3K  illustrates a laminating step in which a top-side adhesion film  312  is placed to protect the device from light emission induced leakage (for devices that are sensitive to light emission) and moisture penetration.  FIG. 3L  illustrates a laminate cure  313  step in which top-side adhesion film  312  is treated to ensure adherence to the underlying EMC and chip backside.  FIG. 3M  illustrates a marking step in which the top-side is marked for device identification and traceability purposes and illustrates a top view  314  after marking. 
         [0018]      FIG. 3N  illustrates a mounting step in which leadframe/substrate  304  is flipped around and mounting tape  316  is applied for holding the device in place during a subsequent package sawing step. The sawing process is performed on leadframe/substrate  304 .  FIG. 3O  illustrates a sawing step in which each device is separated via sawing blade  318 .  FIG. 3P  illustrates the completion of a package saw singulation step.  FIG. 3Q  illustrates a step in which mounting tape  316  is manually scrubbed and/or a pick-and-place handler is employed to remove the devices from tape  316  for bulk packing, (electrical) testing, and/or taping/packing  320 . 
         [0019]    Although a particular order of steps is illustrated in the assembly process depicted in  FIGS. 3A-3Q , the order of the steps may be altered in other embodiments. For example, the grinding process of  FIGS. 3H-3I  may be performed at any appropriate stage of the assembly process. Furthermore, inclusion of top-side adhesion film  312  is optional. That is, top-side adhesion film  312  is not included in exposed silicon package structures such as package structure  220  depicted in  FIG. 2B . 
         [0020]      FIG. 3R  illustrates example dimensions of devices resulting from the assembly process of  FIGS. 3A-3Q . The given table provides example dimensions for extremely thin DFN (ETDFN) and extremely thin QFN (ETQFN) as well as exposed silicon extremely thin DFN (ESETDFN) and exposed silicon extremely thin QFN (ESETQFN) packages. Overall, thinner packages are achievable due to the included grinding process. 
         [0021]    Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.