Abstract:
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to integer or fixed-point arithmetic devices for electronic processors, and particularly to integrated circuits that perform high speed fixed-point arithmetic operations with minimal logic gates.  
         BACKGROUND OF THE INVENTION  
         [0002]    Standard application specific integrated circuit (ASIC) modules that perform fixed-point arithmetic functions on numbers having N bits require at least log N levels of logic, producing a delay proportional to log N. It is known that the delay can be reduced by using long number formats, but long number formats require additional hardware (gates). Consequently, the ASIC design is usually selected as a trade-off of the delay and module size.  
           [0003]    One design technique for faster fixed-point arithmetic modules is to use a “double size” representation in place of a standard N-bit representation of N-bit number. Integers of the range 0 . . . 2 N −1, or −2 N-1  . . . 2 N-1 −1, are considered as pairs (A and B), where A and B each have N bits. Adders (and subtractors) can be implemented with a fixed delay that is not dependant on N.  
           [0004]    A similar effect takes place for multipliers. For example, a “standard” multiplier implemented in the form of a Wallace tree with a final adder can be reduced to single Wallace tree, reducing the delay by about 30%. However, this faster multiplier will require approximately four times as many logic gates as the standard multiplier. Since a given multiplier already contains a high gate count, this faster multiplier is usually unacceptable.  
           [0005]    Most integer arithmetic units employ redundant number representations. The algebraic value of an N-bit redundant number [X n-1 , X n-2 , . . . X 1 , X 0 ] (where X i  ε {−1, 0, 1}) is equal to  
         ∑     i   =   0       x   -   1              X   i     *       2   i     .                             
 
           [0006]    Redundant numbers are quite useful in adders (and subtractors) because of the property of performing additions without carry propagation. They are also useful in multipliers (and dividers) because redundant numbers do not require 2&#39;s complement methods to handle negative numbers. However, integer arithmetic units operate in what is referred to herein as a 1-redundant number system. Thus, the prior double-size adder designs and the multipliers employed 1-redundant concepts.  
           [0007]    The present invention is directed to sparce-redundant arithmetic units that provide faster fixed-point arithmetic operations without significantly increasing the hardware implementation.  
         SUMMARY OF THE INVENTION  
         [0008]    The present invention provides a series of “intermediate” representations for integers and other fixed-point numbers that allow implementation of the fixed-point arithmetic module as a good compromise between simpler logic of standard integer arithmetic modules and speed-up benefits of double-size representations.  
           [0009]    In one embodiment, a fixed-point arithmetic unit, which may be an adder or multiplier, performs arithmetic operations on N-bit integers. The arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a (1/K)-redundant representation of the integer, where K is an integer greater than 1 and less than N.  
           [0010]    In other embodiments a converter, which may be coupled to the plurality of inputs of the arithmetic unit, converts 1-redundant representations of the integer to the (1/K)-redundant representations. The converter includes a (K-1)-bit adder receiving the (K-1) least significant bits of the 1-redundant representation of the integer to provide a group of K least significant bits of the (1/K)-redundant representation. A K′-bit adder receives the K′ most significant bits of the 1-redundant representation to provide a group of K′+1 most significant bits of the (1/K)-redundant representation. At least one K-bit adder receives a group of K bits of the 1-redundant representation between the K′ most significant bits and the K-1 least significant bits to provide a group K+1 bits of the (1/K)-redundant representation between the group of most significant bits and the group of least significant bits.  
           [0011]    In another embodiment, rows of a multiplier in an integrated circuit are designed by identifying a distribution of multiplication product groups, if a number of multiplication products in any group is 3 or more, the distribution of multiplication product groups is transformed to adders to occupy a highest unoccupied row of the multiplier.  
           [0012]    For the highest row of the multiplier, the distribution of multiplication product groups is achieved by bit-by-bit multiplication on the two input binary numbers. A plurality of multiplication products is identified, and the multiplication products resulting are distributed into groups by powers of 2. The number of multiplication products in each group is then identified. For second and subsequent rows, the number of multiplication products resulting from the transformation for the next higher row is identified.  
           [0013]    The transformation is performed by applying as many full-adders as possible for each group having at least 3 multiplication products, starting with a group with the lowest power of 2, and adding any carry output to the number of multiplication products of the next higher group. Half-adders are applied to each group having 2 multiplication products and to any remainder outputs.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    [0014]FIG. 1 is a block diagram of a conversion circuit from 1-redundant representations to (1/K)-redundant representations of N-bit numbers.  
         [0015]    FIGS.  2 - 4  are diagrams addition circuits for 1-redundant, (1/2)-redundant and (1/3)-redundant inputs, respectively.  
         [0016]    [0016]FIG. 5 is a flowchart of a process of implementing a multiplier for (1/K)-redundant numbers.  
         [0017]    FIGS.  6 - 12  illustrate steps of the process shown in FIG. 5. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]    A sparce-redundant representation of an N-bit integer, in the form of a (1/K)-redundant representation of a positive N-bit integer X=2 N-1 x N-1 + . . . +4x 2 +2x 1 +x 0 , is a set of binary values (y 0 , . . . , y N-1 ; z K , z 2K , . . . , z [N/K]K ) , where  
             X   =                2     N   -   1            y     N   -   1         +   …   +     4        y   2       +     2        y   1       +     y   0     +                              2   K          z   K       +       2     2      K            z     2      K         +   …   +       2       [     N   /   K     ]        K              z       [     N   /   K     ]        K       .                                     
 
         [0019]    Thus, a (1/K)-redundant representation of an N-bit number has approximately N+N/K bits, where each K-th position in the expansion on the power of 2 can have three different values:  
                                                       00 represents a value of   0           01 and 10 each represents a value of   1           11 represents a value of    2.                      
 
         [0020]    It will be appreciated that the (1/K)-redundant representation is a general case of both a standard binary number (where K is large, i.e., K&gt;N) and the double size input (where K=1, thus a 1-redundant representation).  
         [0021]    [0021]FIG. 1 illustrates a conversion circuit  100  that converts 1-redundant representations (K=1) of N-bit numbers to (1/K)-redundant representations. Circuit  100  uses approximately N/K (rounded up) binary adders comprising adders  102 ,  104  and  106 . Each adder  102  has K input pairs (x 1  and y 1 , x 2  and y 2 , x 3  and y 3 , . . . , x K  and y K ) and (K+1) outputs (z 1 , Z 2 , . . . , z K , z K+1 ) to implement the addition operation:  
         +                                           z     K   +   1                                     x   K         …         x   2           x   1               y   K         …         y   2           y   1               z   K         …         z   2           z   1                                 
 
         [0022]    The leftmost, or most significant, adder  104  has K′ input pairs and K′+1 outputs, where K′≦K. The rightmost, or least significant, adder  106  has K-1 input pairs and K outputs. The most significant input bit pair (x N , y N ) is pair  108  at the leftmost, or most significant, input of adder  104  and the least significant input bit pair (x 1 , y 1 ) is pair  110  at the rightmost, or least significant, input of adder  106 . Since adders  102 ,  104  and  106  can be implemented with linear complexity and logarithmic delay, the conversion circuit has complexity and delay not more than C 1 N and C 2 logK, respectively, where C 1  and C 2  are constants. If each adder  102  has four input pairs (K=4) and the number N of input pairs is 14, N/K is 4 (rounded up), meaning circuit  100  can be constructed using four adders with the leftmost adder  104  having three input pairs (K′=3) and the rightmost adder  106  having K−1=3 input pairs. If N=13 and K=3, N/K is 5, meaning there are five adders composed of three adders  102 , a leftmost adder  104  having two input pairs (K′=2) and a rightmost adder  106  having K−1=2 input pairs.  
         [0023]    A 1-redundant addition of two (1/K)-redundant numbers can be accomplished using structures comprising full adders (FA) and half-adders (HA). Each full adder has three inputs, x, y and z, and each half-adder has two inputs x and y. Each full and half-adder provides two output bits, the left, or most significant, output bit being a carry bit and right, or least significant, output bit being a summation bit. Each full adder computes  
         carry=xy OR xz OR yz, and sum=x+y+z (mod 2).  
         [0024]    Each half-adder  122  computes  
         carry=xy, and sum=x+y (mod 2).  
         [0025]    Each half- and full-adder has the same (constant) depth and complexity.  
         [0026]    [0026]FIG. 2 illustrates an example (for N=7) of an adder circuit  200  having two 1-redundant (K=1) N-bit inputs X and Y. Input X is formed of binary pairs x 1 , x 2 , . . . , x 7  having bits a 1 , a 2 , . . . , a 7  and b 1 , b 2 , . . . , b 7  and input Y is formed of binary pairs y 1 , y 2 , . . . , y 7  having bits c 1 , c 2 , . . . , c 7  and d 1 , d 2 , . . . , d 7 . Circuit  200  produces a 1-redundant (N+1)-bit output Z composed of binary pairs z 1 , z 2 , . . . , z 8  having bits e 1 , e 2 , . . . , e 8  and f 1 , f 2 , . . . , f 8 . In this case, adder circuit  200  requires 13 adders (12 full-adders  120  and one half-adder  122 . FIG. 3 is an example (for K=2 and N=7) of an adder circuit  300  having two (1/K)-redundant N-bit inputs X and Y and a 1-redundant (N+1)-bit output Z. In this case, half of the inputs (x 2 , x 4 , x 6 , . . . and y 2 , y 4 , y 6 , . . . ) are composed of respective binary pairs a 2 ,b 2 , a 4 ,b 4 , a 6 ,b 6 , . . . and c 2 ,d 2 , c 4 ,d 4 , c 6 ,d 6 , . . . , whereas the other half of the inputs (x 1 , x 3 , x 5 , . . . and y 1 , y 3 , y 5 , . . . ) are not binary pairs. Adder circuit  300  requires nine adders: five full-adders  120  and four half-adders  122 . The circuit of FIG. 3 can be implemented for even values of N by elimination of the leftmost full adder and by supplying the left output of leftmost half adder directly to the output of the entire circuit. Thus, for N=6 adder circuit could be implemented in eight adders, four each of full-adders and half-adders. FIG. 4 is an example of an adder circuit  400  having two (1/K)-redundant N-bit inputs and 1-redundant (N+1)-bit output, where K=3, N=10. In this case, one-third of the inputs are binary pairs and the rest are not. As shown in FIG. 4, the configuration of left side of the circuit will depend on N mod K.  
         [0027]    The adders  300  and  400  of FIGS. 3 and 4 can be implemented with the conversion circuit  100  of FIG. 1 by converting each of the numbers being added (or subtracted) from 1-redundant to (1/K)-redundant numbers using respective conversion circuits  100  and applying the appropriate (1/K)-redundant to 1-redundant number adder  300  or  400  to the converted (1/K)-redundant numbers to arrive at the summed result in 1-redundant number format. Consequently the adder circuit has a constant depth and linear complexity.  
         [0028]    1-redundant subtraction can be reduced to addition, because bit-wise negation ˜X of an N-bit (1/K)-redundant number X satisfies the equation X+˜X+const(N, K)=0 for some constant that depends only on N and K; that is, −X=˜X+const(N, K) and Y−X=Y+˜X+const(N, K). Therefore, a subtractor also has constant depth and linear complexity.  
         [0029]    Comparison of two (1/K)-redundant numbers is almost as fast as “standard” comparison, because calculation of 1-redundant difference of A-B requires only a constant delay, and a comparison of a 1-redundant number with 0 is the same operation as comparison of two “usual” numbers.  
         [0030]    FIGS.  5 - 12  consider the case of 1-redundant multiplication of two (1/K)-redundant numbers. Consider a 1-redundant multiplication of two 0-redundant N-bit numbers has a delay D(N) and complexity C(N) over a given set of logical gates when implemented using the Wallace tree method. Consequently, 1-redundant multiplication of two (1/K)-redundant numbers can be implemented with delay D(N)+const using approximately (1+1/K) 2  C(N) gates.  
         [0031]    Ordinary multiplication starts from producing N 2  bit-by-bit products a i ·b i , which can be organized into N N-bit numbers. The Wallace tree reduces these N 2  bits to a pair of 2N-bit numbers using approximately N 2  full adders; the tree has depth (or delay) of about const * log N (where the value of the constant depends on the full adder&#39;s delays).  
         [0032]    This approach requires only a minor modification for (1/K)-redundant case. More particularly, the (1/K)-redundant case produces approximately (1+1/K) 2 N 2  bit-by-bit products which can be organized into (1+1/K) 2 N N-bit numbers. A Wallace tree implementing the multiplier will require approximately (1+1/K) 2 N 2  full adders, and depth (or delay) of const * log (N(1+1/K) 2 ) . Thus, the total complexity will be multiplied by (1+1/K) 2 , but the delay (or depth) will grow not more than 2 * const * log (1+1/K).  
         [0033]    [0033]FIG. 5 is a flowchart of the process of constructing a 1-redundant multiplier for two (1/K)-redundant numbers, and FIGS.  6 - 12  compare 10-bit 1-redundant multipliers for “regular” inputs (case (a)) and for (1/K)-redundant inputs (case (b)). More particularly, case (b) is in the specific form where K=3 using (1/3)-redundant inputs. At step  500 , bit-by-bit multiplication products are generated. There will be 100 such products in the case (a) and 169 products in the case (b). At step  502 , the products are grouped by the powers of 2, with a maximum product value of 2 18  (thus, there are 19 groups) and the groups are distributed as shown in FIG. 6 to identify the number of products in each group. At step  504 , if there is at least one instance of at least 3 products having the same power of 2, the distribution is transformed into the first row of the multiplier in as many full adders as possible, with any carry outputs applied directly to the values for the next higher power of 2. A half-adder is applied to any remainder values, and where there are exactly two values for the same power of 2. FIG. 7 shows the example of this transformation to reduce 100 bits of case (a) to 27 full adders and 6 half-adders in the first row, and will reduce 169 bits of case (b) to 50 full adders and 7 half-adders in the first row.  
         [0034]    At step  506 , if the output distribution still contains at least one instance of at least 3 products having the same power of 2, the process loops back to repeat step  504  and transform the distribution into the next row of the multiplier.  
         [0035]    In the example, the output distribution from FIG. 7 becomes the input distribution for FIG. 8, and the transformation is applied again, providing 18 full adders and 6 half-adders to the second row of case (a) and 32 full adders and 7 half-adders to the second row of case (b). In the case of the second and following rows, it will be necessary to consider one more power of 2 value (2 19  in the example). As shown in FIGS. 8 and 12, the process continues to apply iterations of transformation process of step  504  until the output distributions contain a value of no more than 2 products for any given power of 2. Hence, case (a) will require 11 full adders and 6 half-adders in row three (FIG. 9), 7 full adders and 9 half-adders in row four (FIG. 10) and 1 full adder and 14 half-adders in row five (FIG. 11). Case (b) will require 22 full adders and 6 half-adders in row three (FIG. 9), 14 full adders and 7 half-adders in row four (FIG. 10), 10 full adders and 5 half-adders in row five (FIG. 11) and 5 full adders and 9 half-adders in row six (FIG. 12). Case (a) does not require a sixth row.  
         [0036]    The total number of adders required to implement the circuits are 64 full adders and 41 half-adders (105 total elementary adders) to implement case (a) and 133 full adders and 41 half-adders (174 total elementary adders) to implement case (b). Thus, the number of adders necessary to implement the functions is approximately the same as the number of bits of either number being multiplied (100 bits in 105 adders for case (a) and 169 bits in 174 adders for case (b)) . The delay (or depth) in the case (b) is greater by the one level of elementary adders than the delay or depth of case (a).  
         [0037]    The (1/K)-redundant adder with a (1/K)-redundant input can be implemented using the circuit of FIGS. 3 and 4 with the conversion described in connection with FIG. 1. The resulting adder has a complexity proportional to N (almost without dependence on K), and a delay proportional to log K.  
         [0038]    The (1/K)-redundant multiplier with a (1/K)-redundant output can be implemented by the process described in FIG. 5, also using the conversion described in connection with FIG. 1. The resulting circuit has complexity proportional to N 2 (1+1/K) 2 , and a delay proportional to C 3  log N+C 4  log K, where parameter C 3  describes delay of a Wallace tree with N leafs and parameter C 4  characterizes the delay of the K-bit adders) . Since multipliers often are most space- and time-consuming logical units, the area and timing of the multiplier can be adjusted such that larger values of K leads to more compact implementation, but with a larger bit delay.  
         [0039]    The present invention thus provides a sparce-redundant ((1/K)-redundant) fixed point arithmetic module, such as an adder, subtractor, comparator or multiplier. The process is preferably carried out using a processor operating under the control of a computer program code embedded memory, such as a magnetic disk to generate the design of the arithmetic module based on the size (N) of the input and K.  
         [0040]    Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.