Abstract:
Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a division of U.S. patent application Ser. No. 09/808,484 filed Mar. 14, 2001. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates to the field of semiconductor manufacture and, more particularly, to a flash memory device and method of fabrication.  
           [0003]    As computers become increasingly complex, the need for improved memory storage, and in particular the need for an increased number of memory cells per unit area, increases. At the same time, there is a continuing drive to minimize the size of computers and memory devices. Accordingly, it is a goal of memory device fabrication to increase the number of memory cells per unit area or wafer area.  
           [0004]    A conventional non-volatile semiconductor memory device in which contents are electrically programmable and simultaneously erased by one operation is a flash memory device. Flash memory allows for blocks of memory cells to be erased in one operation. Flash memory devices have the characteristics of low power and fast operation making them ideal for portable devices. Flash memory is commonly used in portable devices such as laptop or notebook computers, digital audio players and personal digital assistant (PDA) devices.  
           [0005]    In flash memory, a charged floating gate is one logic state, typically represented by the binary digit 1, while a non-charged floating gate is the opposite logic state typically represented by the binary digit 0. Charges are injected or written to a floating gate by any number of methods, including avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron injection, for example.  
           [0006]    An important parameter for a flash memory cell is the capacitive coupling of the memory cell. It is difficult to reduce the size or scale down the memory cell while maintaining a desired or required capacitive coupling. This parameter can be a significant factor in the drive to reduce memory cell size. Accordingly, there is a need for a memory cell production scheme directed to reducing the size of a memory cell while maintaining or improving the capacitive coupling of the memory cell.  
         SUMMARY OF THE INVENTION  
         [0007]    This need is met by the present invention, wherein a stacked gate region of a memory cell is disclosed. The flash memory device includes a substrate, at least one trench, an oxide layer, at least one floating gate and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate and over the oxide layer. Other methods and devices are disclosed.  
           [0008]    The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.  
           [0009]    According to one embodiment of the invention, a stacked gate region of a memory cell is disclosed having a substrate, at least one trench, a field oxide region, a tunnel oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate. The field oxide region is formed in the trench. The tunnel oxide layer is formed over the substrate. The at least one floating gate is formed over the tunnel oxide layer. The at least one polysilicon wing is formed adjacent to the at least one floating gate layer and over a portion of the field oxide region.  
           [0010]    According to another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, at least one trench, field oxide, a tunnel oxide layer, at least one floating gate and at least one polysilicon ear. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate. The field oxide is deposited in the at least one trench and extends above an upper surface of the substrate. The tunnel oxide layer is formed over at least a portion of the substrate. The at least one floating gate layer is formed over the tunnel oxide layer. The at least one polysilicon ear is formed on the at least one floating gate layer and adjacent to the field oxide.  
           [0011]    According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, at least one trench, a tunnel oxide layer, at least one floating gate layer, field oxide and at least on polysilicon ear. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate. The tunnel oxide layer is formed over at least a portion of the substrate. The at least one floating gate layer is formed over the oxide layer. The field oxide is deposited in the at least one trench. The at least one polysilicon ear is formed on the at least one floating gate layer.  
           [0012]    According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, a plurality of trenches, a tunnel oxide layer, at least one floating gate layer, field oxide regions and a pair of polysilicon wings. The substrate has at least one semiconductor layer. The plurality of trenches are formed in the substrate. The respective field oxide regions are formed in the trenches. The tunnel oxide layer is formed over the substrate. The floating gate layer is formed over the tunnel oxide layer. The pair of polysilicon wings are located adjacent to opposite ends of the floating gate layer, co-planer with the floating gate layer and over a portion of corresponding ones of the field oxide regions.  
           [0013]    According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, a plurality of trenches, a tunnel oxide layer, at least one floating gate layer, field oxide regions and a pair of polysilicon ears. The substrate has at least one semiconductor layer. The plurality of trenches are formed in the substrate. The respective field oxide regions are formed in the trenches. The tunnel oxide layer is formed over the substrate. The floating gate layer is formed over the tunnel oxide layer. The pair of polysilicon ears are formed adjacent to corresponding ones of the field oxide regions on the floating gate layer and projecting perpendicular to an upper surface of the floating gate layer.  
           [0014]    According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, a plurality of trenches, a tunnel oxide layer, at least one floating gate layer, field oxide regions and a pair of polysilicon ears. The substrate has at least one semiconductor layer. The plurality of trenches are formed in the substrate. The respective field oxide regions are formed in the trenches. The tunnel oxide layer is formed over the substrate. The floating gate layer is formed over the tunnel oxide layer. The pair of polysilicon ears are formed adjacent to the floating gate layer.  
           [0015]    According to yet another embodiment of the invention, a memory cell is disclosed. The memory cell includes a substrate, a source, a drain, at least one trench, a field oxide region, a tunnel oxide layer, at least one floating gate layer, at least one polysilicon wing, a dielectric layer and a control gate. The substrate has at least one semiconductor layer. The source is formed in the substrate. The drain is formed in the substrate. The at least one trench is formed in the substrate. The field oxide region is formed in the trench. The tunnel oxide layer is formed over the substrate. The at least one floating gate layer is formed over the tunnel oxide layer. The at least one polysilicon wing is formed adjacent to the at least one floating gate layer and over a portion of the field oxide region. The dielectric layer is formed over the substrate and the floating gate layer. The control gate layer is formed over the dielectric layer.  
           [0016]    According to yet another embodiment of the invention, a memory cell is disclosed. The memory cell includes a substrate, a source, a drain, at least one trench, a field oxide region, a tunnel oxide layer, at least one floating gate layer, at least one polysilicon wing, a dielectric layer and a control gate. The substrate has at least one semiconductor layer. The source is formed in the substrate. The drain is formed in the substrate. The at least one trench is formed in the substrate. The field oxide region is formed in the trench. The tunnel oxide layer is formed over the substrate. The at least one floating gate layer is formed over the tunnel oxide layer. The at least one polysilicon ear is formed on the at least one floating gate layer and adjacent to the field oxide. The dielectric layer is formed over the substrate and the floating gate layer. The control gate layer is formed over the dielectric layer.  
           [0017]    According to yet another embodiment of the invention, a memory cell is disclosed. The memory cell includes a substrate, a source, a drain, at least one trench, a field oxide region, a tunnel oxide layer, at least one floating gate layer, at least one polysilicon wing, a dielectric layer and a control gate. The substrate has at least one semiconductor layer. The source is formed in the substrate. The drain is formed in the substrate. The at least one trench is formed in the substrate. The field oxide region is formed in the trench. The tunnel oxide layer is formed over the substrate. The at least one floating gate layer is formed over the tunnel oxide layer. The at least one polysilicon ear is formed on the at least one floating gate layer. The dielectric layer is formed over the substrate and the floating gate layer. The control gate layer is formed over the dielectric layer.  
           [0018]    According to yet another embodiment of the invention, a method of fabricating a stacked gate region is disclosed. A substrate having at least one semiconductor layer is provided. A tunnel oxide layer is formed over the substrate. A first polysilicon layer is formed over the tunnel oxide layer. A nitride layer is formed over the first polysilicon layer. Selected areas of the first polysilicon layer are masked. Unmasked areas of the first polysilicon layer are etched leaving at least one floating gate layer. Trench areas are patterned in the substrate. Field oxide is deposited in the trench. A surface of the stacked gate structure is planarized. An oxide etch back is performed to remove selected amounts of the field oxide. The nitride layer is removed. A second polysilicon layer is deposited over the substrate. Selected portions of the second polysilicon layer are removed so as to leave polysilicon wings formed adjacent to the at least one floating gate layer and over a portion of the field oxide.  
           [0019]    According to another embodiment of the invention, a method of fabricating a stacked gate region is disclosed. A substrate having at least one semiconductor layer is provided. A tunnel oxide layer is formed over the substrate. A first polysilicon layer is formed over the tunnel oxide layer. A nitride layer is formed over the first polysilicon layer. Areas of the nitride layer and first polysilicon layer are selectively removed leaving at least one floating gate layer. Trench areas are patterned in the substrate. Field oxide is deposited in the trench areas. A surface of the stacked gate region is planarized. The nitride layer is removed. A second polysilicon layer is deposited over the substrate. Portions of the second polysilicon layer are selectively removed leaving single sided ears, each having one vertical side adjacent to sides of the field oxide and one lower side on one of the at least one floating gate layer.  
           [0020]    According to yet another embodiment of the invention, a method of fabricating a stacked gate region is disclosed. A substrate having at least one semiconductor layer is provided. A tunnel oxide layer is formed over the substrate. A first polysilicon layer is formed over the substrate. A nitride layer is formed over the first polysilicon layer. Selected portions of the tunnel oxide layer, the first polysilicon layer, the nitride layer and the substrate are removed to form the at least one trench to a desired depth. Field oxide is deposited into the at least one trench. The field oxide and the nitride layer are planarized. The nitride layer is removed. A second polysilicon layer is deposited over the substrate and portions of the second polysilicon layer are selectively removed leaving single sided ears, each having one vertical side adjacent to sides of the field oxide and one lower side on one of the at least one floating gate layer. A portion of the field oxide is removed such that an upper surface of the field oxide is substantially co-planer with an upper surface of the at least one floating gate layer leaving double sided ears.  
           [0021]    According to another embodiment of the invention, a method of fabricating a memory cell is disclosed. A substrate having at least one semiconductor layer is provided. A floating gate layer is formed over the substrate. A trench is formed in the substrate. A polysilicon wing is formed adjacent to a vertical edge of the floating gate.  
           [0022]    According to still yet another embodiment of the present invention, a method of fabricating a memory cell is disclosed. A substrate having at least one semiconductor layer is provided. A floating gate layer is formed over a substrate without using photolithography. A trench is formed in the substrate. Field oxide is deposited into the trench beyond an upper surface of the floating gate layer. A polysilicon ear is formed over the floating gate layer and adjacent to an exposed vertical edge of the field oxide.  
           [0023]    According to another embodiment of the invention, a method of fabricating a memory cell is disclosed. A substrate having at least one semiconductor layer is provided. A floating gate layer is formed over the substrate without using photolithography. A trench is formed in the substrate. Field oxide is deposited into the trench beyond an upper surface of the floating gate layer. A polysilicon ear is formed over the floating gate layer and adjacent to an exposed vertical edge of the field oxide. Field oxide is removed such that an upper surface of the field oxide is substantially planar to the upper surface of the floating gate layer.  
           [0024]    According to another embodiment of the invention, a method of fabricating a memory cell is disclosed. A substrate having at least one semiconductor layer is provided. A source and drain are formed in the substrate. A tunnel oxide layer is formed over the substrate. A first polysilicon layer is formed over the tunnel oxide layer. A nitride layer is formed over the first polysilicon layer. Selected areas of the first polysilicon layer are masked. Unmasked areas of the first polysilicon layer are etched leaving at least one floating gate layer. Trench areas are patterned in the substrate. Field oxide is deposited in the trench areas. A surface of the stacked gate structure is planarized. An oxide etch back is performed to remove selected amounts of the field oxide. The nitride layer is removed. A second polysilicon layer is deposited over the substrate and selected portions of the second polysilicon layer are removed so as to leave polysilicon wings formed adjacent to the at least one floating gate layer and over a portion of the field oxide. A dielectric layer is formed over the floating gate layer. A control gate layer is formed over the dielectric layer.  
           [0025]    According to yet another embodiment of the invention, a method of fabricating a memory cell is disclosed. A substrate having at least one semiconductor layer is provided. A source and drain are formed in the substrate. A tunnel oxide layer is formed over the substrate. A first polysilicon layer is formed over the tunnel oxide layer. A nitride layer is formed over the first polysilicon layer. Areas of the nitride layer and first polysilicon layer are selectively removed leaving at least one floating gate layer. Trench areas are patterned in the substrate. Field oxide is deposited in the trench areas. Planarization is performed. The nitride layer is removed. A second polysilicon layer is deposited over the substrate. Portions of the second polysilicon layer are removed leaving single sided ears, each having one vertical side adjacent to sides of the field oxide and one lower side on one of the at least one floating gate layer. A dielectric layer is formed over the floating gate layer, the polysilicon ears and the substrate. A control gate layer is formed over the dielectric layer.  
           [0026]    According to another embodiment of the invention, a method of fabricating a memory cell is disclosed. A substrate having at least one semiconductor layer is provided. A source and a drain are formed in the substrate. A tunnel oxide layer is formed over the substrate. A first polysilicon layer is formed over the substrate. A nitride layer is formed over the first polysilicon layer. Selected portions of the tunnel oxide layer, the first polysilicon layer, the nitride layer and the substrate are removed to form at least one shallow trench to a desired depth. Field oxide is deposited into the at least one shallow trench. The field oxide and the nitride layer are planarized to create a planar surface of the stacked gate structure. The nitride layer is removed. A second polysilicon layer is formed over the substrate and portions of the second polysilicon layer are removed leaving single sided ears, each having one vertical side adjacent to sides of the field oxide and one lower side on one of the at least one floating gate layer. A portion of the field oxide is removed such that an upper surface of the field oxide is substantially co-planer with an upper surface of the at least one floating gate layer leaving double sided ears. A dielectric layer is formed over the floating gate layer, the polysilicon wings and the substrate. A control gate layer is formed over the dielectric layer.  
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0027]    The following detailed description of the present invention can be best understood when read in conjunction with the accompanying drawings, where like structure is indicated with like reference numerals.  
         [0028]    [0028]FIG. 1A illustrates a memory array according to one embodiment of the invention.  
         [0029]    [0029]FIG. 1B illustrates a cross section of a selected portion of a memory cell according to one embodiment of the invention.  
         [0030]    [0030]FIG. 2 illustrates a cross section of selected portion of a memory cell according to another embodiment of the invention.  
         [0031]    [0031]FIG. 3 illustrates a cross section of selected portion of a memory cell according to another embodiment of the invention.  
         [0032]    [0032]FIG. 4 illustrates a method of fabricating a memory cell according to one embodiment of the invention.  
         [0033]    [0033]FIG. 5A illustrates a stage of fabrication of the method of FIG. 4.  
         [0034]    [0034]FIG. 5B illustrates a stage of fabrication of the method of FIG. 4.  
         [0035]    [0035]FIG. 5C illustrates a stage of fabrication of the method of FIG. 4.  
         [0036]    [0036]FIG. 5D illustrates a stage of fabrication of the method of FIG. 4.  
         [0037]    [0037]FIG. 5E illustrates a stage of fabrication of the method of FIG. 4.  
         [0038]    [0038]FIG. 5F illustrates a stage of fabrication of the method of FIG. 4.  
         [0039]    [0039]FIG. 5G illustrates a stage of fabrication of the method of FIG. 4.  
         [0040]    [0040]FIG. 6 illustrates a method of fabricating a selected portion of a memory cell according to another embodiment of the invention.  
         [0041]    [0041]FIG. 7A illustrates a stage of fabrication of the method of FIG. 6.  
         [0042]    [0042]FIG. 7B illustrates a stage of fabrication of the method of FIG. 6.  
         [0043]    [0043]FIG. 7C illustrates a stage of fabrication of the method of FIG. 6.  
         [0044]    [0044]FIG. 7D illustrates a stage of fabrication of the method of FIG. 6.  
         [0045]    [0045]FIG. 7E illustrates a stage of fabrication of the method of FIG. 6.  
         [0046]    [0046]FIG. 7F illustrates a stage of fabrication of the method of FIG. 6.  
         [0047]    [0047]FIG. 8 illustrates a method of fabricating selected portion of a memory cell according to another embodiment of the invention.  
         [0048]    [0048]FIG. 9A illustrates a stage of fabrication of the method of FIG. 8.  
         [0049]    [0049]FIG. 9B illustrates a stage of fabrication of the method of FIG. 8.  
         [0050]    [0050]FIG. 9C illustrates a stage of fabrication of the method of FIG. 8.  
         [0051]    [0051]FIG. 9D illustrates a stage of fabrication of the method of FIG. 8.  
         [0052]    [0052]FIG. 9E illustrates a stage of fabrication of the method of FIG. 8.  
         [0053]    [0053]FIG. 9F illustrates a stage of fabrication of the method of FIG. 8.  
         [0054]    [0054]FIG. 9G illustrates a stage of fabrication of the method of FIG. 8.  
         [0055]    [0055]FIG. 10 is a computer system with which embodiments of the invention may be used.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0056]    [0056]FIG. 1A illustrates a memory array  260  according to one embodiment of the invention. The memory array  260  includes a plurality of memory cells  190 . Each memory cell  190  includes a source  210 , drain  220  and a stacked gate region or gate structure  200 . The gate structure  200  includes a floating gate  250  and a control gate  240 . The floating gate  250  includes polysilicon wings or ears, described in further detail herein, which increase the capacitive coupling of the memory cell  190 . The control gates  240  of the respective cells  190  in a row are formed integral to a common word line (WL) associated with the row. In the completed memory array, the source  210  of each memory cell  190  in a column is formed in a common region with the source  210  of one of the adjacent memory cells. Similarly, the drain  220  of each memory cell is formed in a common region with the drain  220  of another adjacent memory cell. Additionally, the sources  210  of each memory cell  190  in a row, and hence pair of rows, are formed as a common region, facilitating formation of a common source line CS. The drain of each cell in a row of cells is connected by a conductive bit line (BL). A memory array of this nature, but without polysilicon wings or ears, is illustrated in further detail in U.S. Pat. No. 5,680,345, the disclosure of which is incorporated herein by reference.  
         [0057]    To effect a charge on floating gate  250 , the voltage on control gate  240  is capacitively coupled to floating gate  250 , which permits control gate  240  to control the voltage on floating gate  250 . Inadequate capacitive coupling between control gate  240  and floating gate  250  may inhibit proper operation of memory cell  190 . The degree or amount of capacitive coupling is increased by increasing the overlapping surface area of control gates  240  to floating gates  250 . Control gate  240  and floating gate  250  generally comprise parallel planes of conductive material separated by a dielectric layer. If the floating gate  250  is too small, the effectiveness of the coupling degrades and adversely affects the threshold voltage. Consequently, each floating gate  250  must provide sufficient area to effectively couple control gate  240  to floating gate  250 . By including polysilicon wings or ears of the present invention, as described in further detail herein, with the floating gate  250 , the lateral dimensions of the floating gate  250  can be reduced, thereby reducing the size of the memory cell, while maintaining an appropriate capacitive coupling.  
         [0058]    [0058]FIG. 1B illustrates a stacked region of a memory cell according to one embodiment of the invention. The illustrated portion of the memory cell includes a substrate  101 , a tunnel oxide layer  102 , a floating gate (FG) polysilicon (poly) layer  103 , floating gate poly wings  104 , a field oxide region  105 , a dielectric layer  106  and a control gate layer  107 . The substrate  101  is generally silicon, but other types of semiconductor materials may be used and has an upper surface  108 . The field oxide region  105  electrically isolates individual memory cells. The FG poly layer  103  includes an upper surface  109 . The FG poly layer  103  and the FG poly wings  104  typically comprise conductive polysilicon but need not be made of the same material. The configuration of the FG poly layer  103  and the FG poly wings  104  enables formation of a memory cell characterized by higher capacitive coupling between the FG structure and the control gate layer  107 . The FG poly wings  104  overlap the field oxide region  105 . For the purpose of defining and describing the present invention, “wings” comprise regions of material located adjacent to and generally coplanar with an associated material. Wings are described herein as merely “generally” coplanar because it is contemplated that portions of a wing may extend beyond or outside the bounds of the plane of the associated material. In the embodiment of FIG. 1B, for example, the wings  104  are located adjacent to and are generally coplanar with the FG poly layer  103 . The stacked gate region of a memory cell is able to be fabricated without using a floating gate photolithography step.  
         [0059]    [0059]FIG. 2 illustrates a stacked region of a memory cell according to another embodiment of the invention. The illustrated portion of the memory cell includes a substrate  201 , a tunnel oxide layer  202 , a floating gate (FG) polysilicon (poly) layer  203 , floating gate poly ears  204 , a field oxide region  205 , a dielectric layer  206  and a control gate layer  207 . The substrate  201  is generally silicon, but other types of semiconductor materials may be used. The substrate  201  has an upper surface  208 . The FG poly layer  203  includes an upper surface  209 . The FG poly layer  203  and the FG poly ears  204  may be made of the same material or different material. The configuration of the FG poly layer  203  and the FG poly ears  204  results in a higher capacitive coupling between the FG poly structure and the control gate layer  207 . A single side of the FG poly ears  204  contacts the field oxide region  205 . For the purposes of describing and defining the present invention, “ears” comprises regions of material positioned adjacent to a portion of an associated material and projecting from or extending substantially beyond the bounds of the plane of the associated material. In the embodiment of FIG. 2, for example, the ears  204  are adjacent to a portion of the FG poly layer  203  and project from the FG poly layer  203  in a substantially perpendicular fashion. The poly ears  204  of FIG. 2 may also be identified as “single-sided” ears because they are adjacent to field oxide on a single side. The memory cell of FIG. 2 may also be fabricated without using a floating gate photolithography step.  
         [0060]    [0060]FIG. 3 illustrates a stacked region of a memory cell according to another embodiment of the invention. The stacked region of a memory cell includes a substrate  301 , a tunnel oxide layer  302 , a floating gate (FG) polysilicon (poly) layer  303 , floating gate poly ears  304 , a field oxide region  305 , a dielectric layer  306  and a control gate layer  307 . The substrate  301  is generally silicon, but other types of semiconductor materials may be used. The substrate  301  has an upper surface  308 . The FG poly layer  303  includes an upper surface  309 . The FG poly layer  303  and the FG poly ears  304  may be made of the same material or different material. The configuration of the FG poly layer  303  and the FG poly ears  304  results in a higher capacitive coupling between the FG poly layer  303  and the control gate layer  307  for memory cells of the flash memory device. The poly ears of FIG. 3 may also be identified as double sided ears because both vertical sides avoid contact with the field oxide region  305 . Neither side of the FG poly ears  304  overlap or contact the field oxide region  305 , further increasing the capacitive coupling of the memory cells. The memory cell of FIG. 3 may also be fabricated without using a floating gate photolithography step.  
         [0061]    [0061]FIG. 4 illustrates a method of fabricating the stacked gate region illustrated in FIG. 1B. FIGS. 5A, 5B,  5 C,  5 D,  5 E,  5 F and  5 G illustrate stages of the method of FIG. 4.  
         [0062]    A substrate  501  is provided at  401 . The substrate  501  is, generally, a silicon substrate. A tunnel oxide layer  502  is formed over the substrate  501  at  402 . A self aligned floating gate (SA-FG) poly layer  503  is formed over the tunnel oxide layer  502  at  403 . A nitride layer  504  is formed over the SA-FG poly layer  503  at block  404 . FIG. 5A illustrates the stacked gate region at this stage of the method.  
         [0063]    A layer of photo resist  505  is deposited over the nitride layer  504  in selected areas by utilizing a mask at block  405 . The areas covered by the photo resist indicate areas not to be etched and permit forming gates of the flash memory device. The flash memory device is etched at block  406 . Layers and substrate are removed by the etch to form a shallow trench as shown by  506  in FIG. 5B. The etch performed at block  406 , may also be referred to as a shallow trench isolation (STI) etch. FIG. 5B illustrates the stacked gate region at this stage of the method.  
         [0064]    The photo resist  505  is removed, field oxide  507  is deposited into the trenches and mechanical planarization is performed at block  407 . For example, chemical mechanical planarization (CMP) could be used as one type of mechanical planarization. FIG. 5C illustrates the stacked gate region at this stage of the method.  
         [0065]    An oxide etch back is performed at block  408  to remove a determined amount of the field oxide  507  so that the field oxide  507  is below an upper surface of the FG poly layer  503  and above the upper surface of the tunnel oxide layer  503 . FIG. 5D illustrates the stacked gate region after the oxide etch back has been performed. The nitride layer  504  is removed at block  409 . The nitride layer  504  can be removed by a process such as etching. FIG. 5E illustrates the stacked gate region after the nitride layer  504  has been removed.  
         [0066]    After the nitride layer  504  has been removed, a second polysilicon layer  508  is deposited over the stacked gate region at block  410 . The second polysilicon layer  508  may also be referred to as FG poly  2 . FIG. 5F illustrates the stacked gate region at this stage of the method.  
         [0067]    A spacer etch is performed to remove portions of the second poly layer  508  at block  411  leaving the floating gate poly wings  509  of FIG. 5G. A spacer etch is a method of selectively etching.  
         [0068]    Other conventional steps of processing may be performed on the stacked gate region such as, oxide nitride oxide (ONO) formation, control gate (CG) poly deposition, CG poly photolithography and etch, and the like.  
         [0069]    [0069]FIG. 6 illustrates a method of fabricating the stacked gate region illustrated in FIG. 2. FIGS. 7A, 7B,  7 C,  7 D,  7 E and  7 F illustrate stages of the method of FIG. 6.  
         [0070]    A substrate  701  is provided at  601 . The substrate  701  is, generally, a silicon substrate. A tunnel oxide layer  702  is formed over the substrate  701  at  602 . A self aligned floating gate (SA-FG) poly layer  703  is formed over the tunnel oxide layer  702  at  603 . A nitride layer  704  is formed over the SA-FG poly layer  703  at block  604 . FIG. 7A illustrates the stacked gate region at this stage of the method.  
         [0071]    A layer of photo resist  705  is deposited over the nitride layer  704  in selected areas by utilizing a mask at block  605 . The areas covered by the photo resist indicate areas not to be etched and permit forming gates of the stacked gate region. The stacked gate region is etched at block  606 . Layers and substrate are removed by the etch to form a shallow trench as shown by  706  in FIG. 7B. The etch performed at block  606 , is also referred to as a shallow trench isolation (STI) etch. FIG. 7B illustrates the stacked gate region at this stage of the method.  
         [0072]    The photo resist  705  is removed, field oxide  707  is deposited into the trenches and a mechanical planarization is performed at block  607 . An example of mechanical planarization which may be used is CMP. FIG. 7C illustrates the stacked gate region at this stage of the method. An oxide etch back is not performed.  
         [0073]    The nitride layer  704  is removed at block  608 . The nitride layer  704  can be removed by a process such as etching. FIG. 7D illustrates the stacked gate region after the nitride layer  704  has been removed.  
         [0074]    After the nitride layer  704  has been removed, a second polysilicon layer  708  is deposited over the stacked gate region at block  609 . The second polysilicon layer  708  may also be referred to as FG poly  2 . FIG. 7E illustrates the stacked gate region at this stage of the method.  
         [0075]    A spacer etch is performed to remove portions of the second poly layer  708  at block  611  leaving FG poly single sided ears  709  of FIG. 7F to increase capacitive coupling of memory cells of the stacked gate region. FIG. 7F illustrates a stacked gate region after the method has been performed.  
         [0076]    Other standard steps of processing may be performed on the stacked gate region such as, oxide nitride oxide (ONO) formation, CG Poly deposition, CG poly photolithography and etch, and the like.  
         [0077]    [0077]FIG. 8 illustrates a method of fabricating the stacked gate region illustrated in FIG. 3. FIGS. 9A, 9B,  9 C,  9 D,  9 E,  9 F and  9 G illustrate stages of the method of FIG. 8.  
         [0078]    A substrate  901  is provided at  801 . The substrate  901  is, generally, a silicon substrate. A tunnel oxide layer  902  is formed over the substrate  901  at  802 . A self aligned floating gate (SA-FG) poly layer  903  is formed over the tunnel oxide layer  902  at  803 . A nitride layer  904  is formed over the SA-FG poly layer  903  at block  804 . FIG. 9A illustrates the stacked gate region at this stage of the method.  
         [0079]    A layer of photo resist  905  is deposited over the nitride layer  904  in selected areas by utilizing a mask at block  805 . The areas covered by the photo resist indicate areas not to be etched and form gates of the stacked gate region. The stacked gate region is etched at block  806 . Layers and substrate are removed by the etch to form a shallow trench as shown by  906  in FIG. 9B. The etch performed at block  806 , is also referred to as a shallow trench isolation (STI) etch. FIG. 9B illustrates the stacked gate region at this stage of the method.  
         [0080]    The photo resist  905  is removed, field oxide  907  is deposited into the trenches and mechanical planarization is performed at block  807 . CMP is an example of a type of mechanical planarization that may be used. FIG. 9C illustrates the stacked gate region at this stage of the method.  
         [0081]    The nitride layer  904  is removed at block  808 . The nitride layer  904  can be removed by a process such as etching. FIG. 9D illustrates the stacked gate region after the nitride layer  904  has been removed.  
         [0082]    After the nitride layer  904  has been removed, a second polysilicon layer  908  is deposited over the stacked gate region at block  809 . The second polysilicon layer  908  may also be referred to as FG poly  2 . The second polysilicon layer  908  is deposited to a selected thickness or height which corresponds to a desired capacitive coupling. FIG. 9E illustrates the stacked gate region at this stage of the method.  
         [0083]    A spacer etch is performed to remove portions of the second poly layer  908  at block  810  leaving FG poly single sided ears  909  in FIG. 9F.  
         [0084]    A field oxide etch back is performed at block  811  to remove a selected amount of field oxide such that the field oxide is below the SA-FG poly  903  but above the tunnel oxide  902 . The selected amount of field oxide is removed to create FG poly double sided ears  910  as shown in FIG. 9G by removing the field oxide  707 .  
         [0085]    Other standard steps of processing may be performed on the stacked gate region such as, oxide nitride oxide (ONO) formation, CG Poly deposition, CG poly photolithography and etch, and the like.  
         [0086]    [0086]FIG. 10 is an illustration of a computer system  1012  that can use and be used with embodiments of the present invention. As will be appreciated by those skilled in the art, the computer system  1012  would include ROM  1014 , mass memory  1016 , peripheral devices  1018 , and I/O devices  1020  in communication with a microprocessor  1022  via a data bus  1024  or another suitable data communication path. The memory devices  1014  and  1016  can include stacked gate regions fabricated according to the various embodiments of the present invention. ROM  1014  can include EPROM or EEPROM or flash memory. Mass memory  1016  can include DRAM, synchronous RAM or flash memory.  
         [0087]    For the purposes of describing and defining the present invention, formation of a material “on” a substrate or layer refers to formation in contact with a surface of the substrate or layer. Formation “over” a substrate or layer refers to formation above or in contact with a surface of the substrate. A “flash memory device” includes a plurality of memory cells. Each “memory cell” of a flash memory device can comprise components such as a gate, floating gate, control gate, wordline, channel region, a source, self aligned source and a drain. The term “patterning” refers to one or more steps that result in the removal of selected portions of layers. The patterning process is also known by the names photomasking, masking, photolithography and microlithography. The term “self-aligned gate” refers to a memory device where the gate electrodes are formed before the source/drain diffusions are made.  
         [0088]    Many other electronic devices can be fabricated utilizing various embodiments of the present invention. For example, memory devices according to embodiments of the invention can be used in electronic devices such as cell phones, digital cameras, digital video cameras, digital audio players, cable television set top boxes, digital satellite receivers, personal digital assistants and the like.  
         [0089]    Having described the invention in detail and by reference to preferred embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims. Other suitable materials may be substituted for those specifically recited herein. For example, the substrate may be composed of semiconductors such as gallium arsenide or germanium. Additionally, other dopants may be utilized besides those specifically stated. Generally, dopants are found in groups III and V of the periodic table. Other placements of the polysilicon wings or ears with respect to a floating gate may be used and still be encompassed by the present invention.