Abstract:
A transient blocking unit (TBU) is a circuit having series-connected transistors that normally conduct current, but automatically switch to a high-impedance current blocking state in response to an over-current condition. Here enhancement mode devices are used in the primary TBU current path, as opposed to the conventional use of depletion mode devices in this context. This approach provides two main advantages. The first advantage is that the dependence of TBU parameters on poorly controlled depletion mode device parameters can be reduced or eliminated. The second advantage is that such TBUs can provide over-voltage protection in addition to over-current protection.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation in part of application Ser. No. 12/456,882, filed on Jun. 23, 2009, entitled “Voltage Triggered Transient Blocking Unit”, and hereby incorporated by reference in its entirety. Application Ser. No. 12/456,882 claims the benefit of U.S. provisional patent application Ser. No. 61/133,400, filed on Jun. 26, 2008, entitled “Voltage Triggered Transient Blocking Unit”, and hereby incorporated by reference in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to protection of electrical loads from electrical transients. 
       BACKGROUND 
       [0003]    A transient blocking unit (TBU) is an arrangement of two or more transistors connected to each other in series such that they automatically switch off when a TBU current passing through these transistors exceeds a predetermined threshold. As the TBU current increases, voltage drops across the TBU transistors are provided as gate voltages to the TBU transistors that tend to turn these transistors off. When the TBU current is below threshold, this turning-off effect is negligible, and the TBU resistance is low. When the TBU current goes above threshold, the turning-off effect is strong enough to cause positive feedback, which leads to rapid and automatic switching of the TBU to a high-resistance off state. The positive feedback in this situation arises from the tendency of an increasing gate voltage on a TBU transistor to increase the voltage drop across that TBU transistor, and this increased voltage drop is provided as a gate voltage to another TBU transistor. The TBU circuit connections are such that positive feedback can result from these increasing transistor and gate voltages. 
         [0004]      FIG. 1  shows a simple example of a conventional TBU. In this example, two depletion mode (i.e., normally-on) transistors, Q 1  and Q 3 , are connected in series such that the same current I TBU  flows through Q 1  and Q 3 . As I TBU  increases, V DS  of Q 1  and V SD  of Q 3  both increase. The transistor types are selected such that as V DS  of Q 1  increases, the voltage applied to the gate of Q 3  acts to shut off Q 3 . Similarly, as V SD  of Q 3  increases, the voltage applied to the gate of Q 1  acts to shut off Q 1 . The positive feedback inherent in this arrangement leads to a rapid transition of the TBU from a normal low-impedance state to a high-impedance current blocking state once I TBU  exceeds a predetermined threshold. In operation, a TBU can switch to its high-impedance state in response to an over-current condition from an electrical transient, thereby protecting electrical devices or circuits connected to the TBU. 
         [0005]    The TBU example of  FIG. 1  is a unipolar (or uni-directional) TBU because it is only effective to block surges having a predetermined polarity (i.e., either positive surges or negative surges).  FIG. 2  shows a conventional bipolar TBU. The circuit of  FIG. 2  can be understood as providing two unipolar TBUs having opposite polarity in series. The first unipolar TBU is formed by depletion mode transistors Q 1  and Q 3 , and the second unipolar TBU is formed by depletion mode transistors Q 2  and Q 3 .  FIG. 2  also shows a typical application for a TBU, where it is placed in series between an electrical device  202  and a load  204  in order to protect device  202  from transients from load  204 . Protection of device  202  is also provided from transients that may develop between the TBU and load  204  (e.g., on a transmission line). If a transient from the load causes the TBU current to exceed the TBU threshold, the TBU will switch to its off state, thereby protecting the device from the transient. Some early examples of TBUs include U.S. Pat. No. 3,916,220, U.S. Pat. No. 4,533,970, and U.S. Pat. No. 5,742,463. 
       SUMMARY 
       [0006]    As indicated above, conventional TBUs rely on the use of depletion mode devices (i.e., normally-on transistors) in the primary current path to provide over-current protection. However, depletion mode MOSFETs tend to be more difficult to fabricate than enhancement mode (i.e., normally-off) MOSFETs. This difficulty leads to higher cost and/or greater parameter variability for depletion mode MOSFETs as compared to enhancement mode MOSFETs. In particular, the TBU threshold current depends on the threshold voltages of the primary path transistors. A poorly controlled depletion mode MOSFET threshold can directly lead to a poorly controlled TBU current threshold, with highly undesirable effects on TBU yield. 
         [0007]    Another problem that can arise in connection with conventional TBUs is that a conventional TBU will only switch off if the current passing through the TBU exceeds the TBU threshold. This behavior can lead to impaired device protection in certain circumstances. More specifically, a device being protected by a TBU may not always be able to source or sink the TBU threshold current (e.g., if the protected device is in a standby or sleep mode). In such a situation, a transient on the interface side of the TBU can reach the protected device and possibly damage it. 
         [0008]    In the present application, both of these problems can be addressed by incorporating one or more enhancement mode transistors into the primary TBU current path.  FIG. 3  shows an exemplary schematic diagram of this concept. Here, transistors M 1  and M 2  are enhancement mode MOSFETs, and M 3  is a depletion mode junction field effect transistor (JFET). The primary TBU current path passes through transistors M 1  and M 3 . The gate of M 2  is connected to the node between M 1  and M 3 , and the gate of M 1  is connected to M 2 . With appropriate biasing (e.g., as shown), a gate voltage at M 1  sufficient to turn M 1  on is present during normal operation (i.e., TBU current below threshold) and M 2  is in the off state. When the TBU current exceeds threshold, the gate voltage at M 2  increases due to the voltage drop caused by the current in M 3 , thereby tending to turn M 2  on. As M 2  turns on, the gate voltage of M 1  is decreased below the turn on threshold of M 1 , causing it to turn off. The increased voltage developed across M 1  as a result of this change causes M 3  to turn off. As the impedance of M 3  increases, M 2  is turned fully on, and the gate voltage at M 1  further decreases. The resulting positive feedback leads to rapid and automatic switching of this circuit to a high-impedance current blocking state when the TBU current exceeds threshold. The voltage triggering capability provided by this kind of circuit is explained in connection with the examples described below. 
         [0009]    To better appreciate the present approach, it is helpful to compare it to other approaches where enhancement mode transistors have been employed in connection with a TBU. In U.S. Pat. No. 7,342,433, a TBU having depletion mode transistors in the primary current path is modified by adding enhancement mode devices to control gate voltages of the main TBU transistors. More specifically, the gate voltages of the main depletion mode TBU transistors can be controlled by enhancement mode devices to reduce the on-resistance of the TBU. 
         [0010]    In US 2009/0231773, auxiliary enhancement mode transistors are added to the basic TBU configuration in order to reduce the dependence of the TBU threshold current on poorly controlled parameters of the depletion mode TBU transistors. Further details relating to enhancement mode assisted TBUs can be found in US published application 2009/0231773, filed on Jan. 27, 2009, and hereby incorporated by reference in its entirety. 
         [0011]    In both of these cases, the primary TBU transistors (i.e., the transistors through which the TBU current flows) are all depletion mode devices, as in the examples of  FIGS. 1 and 2 . The use of depletion mode transistors as the primary transistors in a TBU reduces part count (e.g., as seen by comparing  FIGS. 1 and 3 ), which ordinarily would decisively favor the use of depletion mode devices as the primary TBU transistors. However, it has been found, surprisingly, that the advantages of using enhancement mode devices as primary TBU transistors can often outweigh the disadvantage of increased part count. More specifically, there are two main advantages: 
         [0000]    1) enhancement mode MOSFETs with tightly controlled thresholds are easier and lower cost to make than depletion mode MOSFETs, requiring less processing steps; and
 
2) the enhancement mode devices can be configured such that they form a TBU that switches off when a TBU voltage goes out of range (in addition to the normal TBU capability of providing over-current protection).
 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a schematic of a prior art transient blocking unit. 
           [0013]      FIG. 2  is another schematic of a prior art transient blocking unit. 
           [0014]      FIG. 3  shows a schematic relating to embodiments of the invention. 
           [0015]      FIG. 4  is a schematic of a first embodiment of the invention. 
           [0016]      FIG. 5  is a schematic of a second embodiment of the invention. 
           [0017]      FIG. 6  is a schematic of a third embodiment of the invention. 
           [0018]      FIG. 7  is a schematic of a fourth embodiment of the invention. 
           [0019]      FIG. 8  is a schematic of a fifth embodiment of the invention. 
           [0020]      FIG. 9  is a schematic of a sixth embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]      FIG. 4  is a schematic of a first embodiment of the invention. In this circuit, +V indicates that this is the positive rail. M 2  and M 4  are enhancement mode devices, and M 3  is a depletion mode device. Preferably, M 2  and M 4  are n-channel metal-oxide field effect transistors (NMOS), and J 1  is preferably a p-channel junction field effect transistor (JFET). J 1  and M 2  are in the primary TBU current path, so these transistors can be referred to as primary transistors. M 4  is not in the primary TBU current path, so it is convenient to refer to this transistor as an auxiliary transistor. Here the gate of M 2  is connected to M 4 , and the gate of M 4  is connected to the node between J 1  and M 2 . R 4  is connected to the positive rail, +V. As long as M 4  is off (normal TBU on mode), the gate of M 2  is pulled high, which turns it on. (In practice, a zener clamp diode across the drain-source of M 4  may be used (not shown) to prevent excessive voltage, or M 4  may be allowed to avalanche, in order to protect the gate of M 2 ). The “protected” terminal is the protected side of the TBU, as may be connected to an IC or other equipment being protected. The “interface” terminal is the exposed side of the TBU, where surges may be experienced. 
         [0022]    If a surge occurs that pulls the interface positively, if sufficient current flows, then the TBU will act in the normal way of the enhancement mode assisted TBU, in that voltage will be developed across J 1  due to the current, which if sufficient, will turn on M 4 ; that in turn will effectively connect (i.e. short) the gate of M 2  to the source (or drain) of J 1 , which in turn will turn off M 2 . In this way, it is possible to provide TBU current protection capability without the use of depletion mode NMOS devices. 
         [0023]    If the protected terminal of the TBU is connected to a high resistance protected device, then current flow may not suffice to trip the TBU. In this case, the protected terminal will also be dragged positive towards +V. If the rate of change of voltage is relatively slow, then when the source of M 2  approaches +V, R 4  will hold the gate of M 2  at +V, thus causing M 2  to turn off. Thus the TBU is also turned off by any surge which forces the TBU above the positive rail. 
         [0024]    In practice, M 2  is usually a fairly large NMOS and thus has significant gate capacitance. In this case, because of the long RC time constant formed by the gate capacitance and R 4 , the TBU will only turn off as a result of slow moving surges, but may not be fast enough to react to, say 60 Hz mains AC, which is a prime requirement for protection devices. To increase turn off speed, the circuit can be modified by the use of two addition small enhancement mode devices M 5  and M 6  devices. 
         [0025]    The resulting circuit is shown in  FIG. 5 . Here, M 5  and M 6  act as a simple comparator. In this circuit, M 5  is normally turned fully on by the positive bias applied through resistor R 13 , which turns M 6  fully off, and the circuit behaves as described above, with the exception that now a potential divider is formed by R 4  and R 12 . This difference does not substantially alter the operation or effect of the circuit. 
         [0026]    Now when the positive surge occurs, M 5  is turned off as its source approaches +V, because the gate of M 5  is tied to +V through R 13 . M 5  is relatively very small, so its gate capacitance is low. Hence it reacts quickly as the gate drive decreases, and turns off as the interface node approaches +V. When M 5  turns off, M 6  is turned on, by voltage applied through R 12 , sinking current and discharging any gate charge of NMOS M 2  through R 11 , which is of relatively low value. In this manner, a low resistance gate capacitance discharge path can be provided for M 2 . 
         [0027]    In the preceding examples, a TBU with uni-directional current blocking capability is considered. The present approach is also applicable to bi-directional TBUs. 
         [0028]    One example of a bi-directional TBU according to the present work is shown on  FIG. 6 . In this circuit, +V indicates that this is the positive rail. M 1 , M 2  and J 1  are in the primary TBU current path. M 1  and M 2  are enhancement mode devices, and J 1  is a depletion mode device. Auxiliary transistors M 3  and M 4  are also enhancement mode devices, but they are not in the primary TBU current path. Auxiliary transistors M 3  and M 4  correspond to primary transistors M 1  and M 2  respectively. Preferably, M 1 , M 2 , M 3 , and M 4  are NMOS devices, and J 1  is preferably a p-channel JFET. R 3  and R 4  are connected to the positive rail, +V. As long as M 3  and M 4  are off (normal TBU on mode), the gates of the two HV NMOS M 1  and M 2  are pulled high, which turns them on. (In practice, a zener clamp diode across the drain-source of M 3  and M 4  may be used (not shown) to prevent excessive voltage, or these devices may be allowed to avalanche, in order to protect the gates of M 1  and M 2 ). 
         [0029]    For surges that pull the interface positively, this circuit operates substantially like the circuit of  FIG. 4 , and provides both over-current and over-voltage protection. The network formed by R 6 , R 7 , D 1 , and D 2  ensures proper TBU feedback voltages are present at the gate of J 1 . Diodes D 1  and D 2  prevent the resistors from acting as a potential divider, which would decrease the feedback voltage by a factor of 2, thereby decreasing the sensitivity of the TBU. If a negative surge occurs and sufficient current flows, the voltage developed across J 1  will turn on M 3 , which in turn will short the gate of M 1  to the source of M 2 , which in turn will turn off M 1 . In this way, it is possible to provide bi-directional TBU current protection capability without the use of depletion mode NMOS devices. 
         [0030]    The circuit of  FIG. 6  can be modified to improve the switching speed of M 2  by providing a low resistance gate capacitance discharge path. 
         [0031]      FIG. 7  is an example of such a modified circuit. In this circuit, the network formed by R 1 , R 2 , and R 5  provides a voltage reference to transistors M 4 , M 5 , and M 6  so they can act as a voltage comparator as described above in connection with  FIG. 5 . 
         [0032]    In the examples of  FIGS. 6 and 7 , bi-directional protection for over-current conditions is provided, but over-voltage protection is uni-directional. For example, a negative going surge that causes over-voltage but not over-current would be passed to the protected device. In situations where preventing this possibility is important, a voltage comparison capability can be added. 
         [0033]      FIGS. 8 and 9  show examples of such modified circuits that correspond to the examples of  FIGS. 6 and 7 , respectively. Here the positive voltage rail is referenced as +V 2  and the negative voltage rail is referenced as −V 1 . In these examples, enhancement mode MOS transistors M 7  and M 8  in combination with resistors R 1 , R 2 , R 5 , R 8 -R 10  and diodes D 4 -D 6  act as a voltage comparison circuit. More specifically, this comparison circuit causes the TBU to turn off if the TBU output voltage goes close to or beyond the negative rail (−V 1 ). When the TBU output voltage (Vout) drops below a voltage such that V diode −V th =(Vout)−(−V 1 ), the NMOS M 7  is turned on, turning off NMOS M 8 . The rising voltage at the drain of M 8  then turns off JFET J 1 . The diode voltage drop of D 4 , V diode , can be chosen to compensate the threshold voltage, V th , of M 7 , such that the TBU turns off as the output voltage Vout is pulled close to or lower than −V 1 . It may be advantageous to set this threshold either slightly higher or slightly lower than −V 1  in certain applications for best protection performance by setting an appropriate diode voltage drop. In some cases, D 4  may be connected as forward biased and a forward voltage diode drop can be used as the reference. In other cases, a combination of multiple forward biased diodes or forward and reverse biased diodes may be used for best compensation. 
         [0034]    It can be seen that both functions of turning off the TBU in response to a voltage surge either above +V 2  or below −V 1  are achieved by devices M 5 / 6  and M 7 / 8  respectively. The resulting TBU circuit is readily integratable with a simple process that allows for simple low voltage auxiliary NMOS devices and high voltage, high value resistors. 
         [0035]    The preceding description is by way of example as opposed to limitation. Many variations of the given examples will be apparent based on the preceding principles. Practice of the invention does not depend critically on the polarity and/or type of transistors employed in a TBU circuit. For example, the polarities of devices and voltage inputs can all be consistently reversed. PMOS transistors can be employed in place of NMOS transistors, such as M 1  and M 2 , although NMOS devices are typically preferred because they tend to provide better electrical performance than PMOS devices for TBUs. In such a case of reversed polarities, the V 1  and V 2  polarities would now also be reversed, such that V 2  becomes negative with respect to V 1 .