Abstract:
An energy harvesting system is provided that includes a startup module for starting the energy harvesting system operation from a completely OFF state. The startup module uses mechanical vibrations due to motion to trigger a switch which permits the startup module to charge one or more first capacitive elements so to as reach a first defined voltage. A storage module buffers energy obtained from a thermoelectric harvester to be used by a load device. The storage module commences storing energy from the thermoelectric harvester when the first defined voltage has been reached allowing charging of one or more second capacitive elements to reach a second defined voltage. A DC-DC converter module provides regulated voltage to the load device after energy has been transferred from the thermoelectric harvester. The DC-DC converter module determines whether the second defined voltage has been reached and releases stored energy in the one or more first capacitive elements and the load device.

Description:
PRIORITY INFORMATION 
       [0001]    This application claims priority from provisional application Ser. No. 61/173,321 filed Apr. 28, 2009, which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The invention is related to the field of energy harvesting, and in particular to a thermoelectric energy harvesting system using low voltages to efficiently harvest energy. 
         [0003]    Energy harvesting is an area of growing importance because of its potential to reduce the usage of batteries in portable electronic devices. Ambient thermal energy can be harvested using thermoelectric means.  FIG. 1  shows a typical thermoelectric harvester  2  using temperature differences to produce electrical energy and vice-versa. It can be modeled as a voltage source V T  in series with resistance R T . 
         [0004]    The open-circuit voltage output V T  of the harvester  2  is proportional to the temperature difference defined as: 
         [0000]      V T =SΔT  (1) 
         [0000]    where S is the Seebeck coefficient of the material and ΔT is the temperature difference on the thermoelectric device. For most commercial thermoelectric harvesters, the Seebeck coefficient S is in the order of 10-30 mV/K. The harvester  2  can be used to extract electrical power from places with very little temperature difference but the output voltage that can be obtained from the harvester  2  might be as low as 25-50 mV. 
         [0005]    The electrical circuit that interfaces with the thermoelectric harvester must be able to operate from this extremely low voltage. Also, batteries must be avoided to reduce cost. This issue presents a problem of how to startup from very low voltages and transfer energy to circuits that are powered by the thermoelectric harvester  2 . 
         [0006]      FIG. 2  shows a known circuit  4  used to startup from low voltages. In this circuit  4 , the essential components are the coupled inductors being coupled to an always-on junction FET (JFET) such as M 1 . If a small voltage is present at the terminal V TH  of the voltage converter, current flows through the primary winding L 1  of the transformer TR 1 . The current is associated with an increasing exponential function and the voltage decreases with the same exponential function. The change of this current is positive, which lead to a positive voltage being induced in the secondary winding L 2 . The positive terminal of the inductor L 2 , which is connected to the gate of M 1 , is driven to a fixed voltage level by the diode of the JFET M 1 . Also, the negative terminal is shifted to a negative voltage level, charging the capacitor C 2  to a negative level. When the current in the primary winding L 1  saturates, the deviation and the induced voltage in the secondary winding L 2  is zero, which leads to a drop in the secondary voltage. 
         [0007]    Eventually, the transistor M 1  switches off because the sum of the voltage of capacitor C 2  and the secondary winding L 2  becomes negative. This leads to the current through the primary inductor to decrease and a positive voltage is induced in the primary winding L 1 , delaying the current decrease. The output capacitor C OUT  is charged via diode D 1  because the transistor M 1  has a high resistance. The primary current reaches zero which results in the induced voltage in L 2  becoming zero and C 2  being discharged by R 1  to the level of the input voltage. Thus the JFET M 1  starts conducting again and the operation cycle repeats. 
         [0008]    However, the circuit  4  requires a transformer with a large turns ratio to achieve startup from low voltages. In addition, the JFET transistor M 1  is required to be normally ON to supply a large current with 0 V GS  and very low V DS  (˜25 mV). This is extremely difficult to achieve startup using this circuit and not suitable for use with portable devices. 
       SUMMARY OF THE INVENTION 
       [0009]    According to one aspect of the invention, there is provided an energy harvesting system. The system includes a startup module for starting the energy harvesting system operation from a completely OFF state. The startup module uses mechanical vibrations due to motion to activate a switch which permits the startup module to charge one or more first capacitive elements so to as reach a first defined voltage. A storage module buffers energy obtained from a thermoelectric harvester to be used by a load device. The storage module commences storing energy from the thermoelectric harvester when the first defined voltage has been reached allowing charging of one or more second capacitive elements to reach a second defined voltage. A DC-DC converter module provides regulated voltage to the load device after energy has been transferred from the thermoelectric harvester. The DC-DC converter module determines whether the second defined voltage has been reached and releases stored energy in the one or more first capacitive elements and the load device. 
         [0010]    According to another aspect of the invention, there is provided a method of energy harvesting. The method includes using a startup module to start the energy harvesting system operation from a completely OFF state. The startup module uses mechanical vibrations due to motion to trigger a switch which permits the startup module to charge one or more first capacitive elements so to reach a first define voltage. Also, the method includes buffering energy obtained from a thermoelectric harvester to be used by a load device using a storage module. The storage module commences storing energy from the thermoelectric harvester when the first defined voltage has been reached allowing charging of one or more second capacitive elements to reach a second defined voltage. Moreover, the method includes providing regulated voltage to the load device after energy has been transferred from the thermoelectric harvester using a DC-DC converter module. The DC-DC converter module determines whether the second defined voltage has been reached and releases stored energy in the one or more first capacitive elements and the load device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram illustrating a model of a thermoelectric harvester; 
           [0012]      FIG. 2  is a circuit diagram illustrating a commonly known circuit used to startup from low voltages; 
           [0013]      FIG. 3  is a schematic diagram illustrating the architecture of the inventive thermoelectric energy harvesting system; 
           [0014]      FIG. 4  is a circuit diagram illustrating a mechanically assisted startup circuit; 
           [0015]      FIG. 5  is a schematic diagram illustrating a mechanical switch used in accordance with the invention; 
           [0016]      FIGS. 6A-6C  are circuit diagrams illustrating the various circuits used by the startup module in accordance with the invention; 
           [0017]      FIGS. 7A-7B  are circuit diagrams illustrating the various circuits used by the storage module in accordance with the invention; and 
           [0018]      FIG. 8  is a circuit diagram illustrating the closed-loop zero-current switching block used by the storage module in accordance with the invention; and 
           [0019]      FIG. 9  is a circuit diagram illustrating a circuit used by DC-DC converter module in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The invention provides a thermoelectric energy harvesting system that allows for efficient energy extraction of thermal energy. The inventive thermoelectric harvesting system eliminates the need for batteries used by portable devices altogether and has many applications in areas where very low voltages are output as in thermoelectric energy harvesters, fuel cells, or the like. 
         [0021]      FIG. 3  shows the architecture of a thermoelectric energy harvesting system  6  in accordance with the invention. The thermoelectric energy harvesting system  6  includes a startup module  10  that starts the system operation from a completely OFF state where the voltage in all the main capacitors is below usable values. The startup module  10  uses mechanical vibration due to motion to trigger switch S 1  that permits the startup module  10  to charge C DD  above 1V. An internal clock is triggered within the start module  10  powering CMOS switches to allow charge into capacitor C DD  through the inductor L. This is repeated as long as V DD  is less than 1.8V. 
         [0022]    A storage module  12  activates when V DD  reaches 1.8V. A storage capacitor C STO  is required to be significantly higher than capacitor C DD . The storage module  12  acts as a buffer to energy obtained from a thermoelectric harvester  8 . It is not permissible to use the voltage V DD  to directly power load circuits, as the value of C DD  is very small. The voltage across C DD  would drain very fast on connecting a significant load current across it. The power from the thermoelectric harvester  8  is directed towards C STO  when V DD  goes above 1.8V. This essentially builds up the voltage V STO . Depending on the power available from the thermoelectric harvester  8  and the power consumed by the load, the voltage V STO  can vary based on these factors making it not suitable to directly power load devices. 
         [0023]    Constant voltage is attained using a DC-DC converter  14  after the storage capacitor C STO  transfer energy to the load at a constant voltage. The DC-DC converter  14  only triggers after V STO  goes above 2.4V. The DC-DC converter  14  can be used to regulate V L  to an arbitrarily set voltage and when that occurs the capacitors C DD  and C L  are shorted to improve the energy harvesting efficiency of the thermoelectric harvester. 
         [0024]    Thermoelectric inputs present an issue when the voltage it outputs for temperature differences is around 25-50 mV. CMOS switches are unable to operate out of these low voltages to use conventional boosting techniques. The voltage available needs to be close to 1V to suitably operate CMOS devices. However, vibrations produced by human or other mechanism can be used for switching purposes. These vibrations are put into use in a mechanically assisted startup circuit  22  shown in  FIG. 4 . 
         [0025]    In particular,  FIG. 4  shows the switch S 1  being a mechanical switch that turns ON and OFF on the application of very small amount of vibration of less than 0.1 g in acceleration. The vibrations can be induced when a force is applied, for example, by a hand or on the body of a person or any other agent that produces a force. If the switch S is ON, the voltage available from the thermoelectric harvester causes current to flow in the inductor L. If the switch turns OFF, the current in the inductor has to find an alternate path to flow. This action turns ON the transistor M 1  which is connected as a diode, and the capacitor C DD  is allowed to charge. If the diode is considered ideal, assuming that there was no initial voltage across C DD , the voltage obtained at C DD  at the end of the ON/OFF cycle is defined as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       C 
                     
                      
                     
                       ( 
                       final 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             L 
                             / 
                             
                               C 
                               DD 
                             
                           
                         
                         
                           
                             
                               R 
                               T 
                             
                              
                             
                               R 
                               L 
                             
                           
                           + 
                           
                             R 
                             SW 
                           
                         
                       
                        
                       
                         V 
                         T 
                       
                     
                     = 
                     
                       
                         Q 
                         T 
                       
                        
                       
                         V 
                         T 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0000]    where Q T  is the Q-factor of the startup network, R T  is the internal resistance of the thermoelectric harvester, R L , and R SW  are the parasitic series resistances of the inductor and the switch. Q T  needs to be at least 34 to get more than 1V across C DD  with a 30 mV input. In this case, the diode formed by M 1  is not ideal and has a voltage drop across it. In addition, Q T  requires to be higher than 34 to get 1V across C DD . In the presence of diode losses, the voltage across the capacitor is defined as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       O 
                     
                      
                     
                       ( 
                       final 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           D 
                           2 
                         
                         + 
                         
                           
                             Q 
                             T 
                             2 
                           
                            
                           
                             V 
                             T 
                             2 
                           
                         
                       
                     
                     - 
                     
                       V 
                       D 
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   2 
                 
               
             
           
         
       
     
         [0026]    As an example, if V D  is 0.6V, then with a Q T  of 42, the input open circuit voltage needs to be at least 35 mV to obtain a 1V output. In this case, the value of L used is 22 μH and that of C DD  is 470 pF. Thermal harvester  24  has a resistance of 5Ω, and the parasitic resistances add up to 1Ω. This gives a Q T  of 42. The voltage gain can be increased by increasing L or decreasing C DD . Increasing L too much increases the size of the system and cost. C DD  on the other hand cannot be decreased arbitrarily as it needs to have a moderate amount of energy to power circuits. Reducing V D  also helps in decreasing the input voltage required for startup. Synchronous rectifiers cannot be used during startup due to the lack of suitable voltage to turn ON the switches. With a 35 mV of open-circuit voltage that corresponds to a temperature difference of 1.5K across the thermoelectric harvester, which should be feasible in body-worn applications. However, in other embodiments larger open-circuit voltage with higher temperature differences can be used in other applications. 
         [0027]    Once S 1  turns ON and OFF, the capacitor C DD  gets charged to above 1V. After this point the switch S 1  is not needed. The voltage across C DD  starts off an internal clock generator module which is used to drive on-chip CMOS switches to help transfer power from V TH  to V DD . 
         [0028]      FIG. 5  shows an example design of a MEMS switch that can be used as the mechanical startup switch S 1 . The switch is designed to be motion activated. Any slight motion can cause bending beams  32  to twist, which allows the switch S 1  to make contact and break it after a short time. This helps to trigger the startup circuit and build voltage across C DD . Other designs of motion-activated switches can be thought of and implemented with the harvester interface circuit. 
         [0029]    With the help of the mechanical switch S 1 , the voltage across C DD  can be raised to 1V and above. Once this happens, the electronics within the startup module  10  takes over.  FIGS. 6A-6C  show the circuit elements defining the startup module  10 . In particular,  FIG. 6A  shows a clock generation module (CLKGEN)  42  and voltage reference generation module (REFGEN)  44 . The voltage V DD  powers the CLKGEN and REFGEN modules. The voltage reference module (REFGEN)  44  generates a voltage V REF  being approximately 0.7V which is used as the reference voltage throughout the circuit. The REFGEN module  44  uses an arrangement having an on-chip P+/N-well diode to generate the reference voltage which stays nearly constant as the input voltage (V DD ) changes. It is not necessary for V REF  to be constant across all V DD  as comparisons only take place close to when V DD  is around 1.8V. The REFGEN module  44  maintains V REF  such that it does not change significantly with changes in V DD  or temperature. 
         [0030]    V DD  simultaneously powers the CLKGEN module  42  shown in  FIG. 6A . The CLKGEN module  42  can include multiple delays arranged to form a ring oscillator. The clock frequency is controlled by a 2-bit signal CLK&lt;0:1&gt;. The frequency can be adjusted to correct for process variations and to achieve maximum power transfer. When V DD  is charged to above 1V, the CLKGEN module  42  turns ON and outputs the CLK signal. This signal is used to clock the comparator COMP shown in  FIG. 6B . 
         [0031]      FIG. 6B  shows a circuit diagram  46  where a comparison is performed by the comparator COMP using a divided version of V DD  (V DIV ) and the reference voltage V REF . It is assumed that the signal V DD  VL_SHORTb is held high for the moment. As long as V DD  is less than 1.8V, the CHG_V DD  signal is triggered which is used to transfer energy from the thermal input on to C DD . When CHG_V DD  goes high, the CMOS switch M 2  turns ON and causes current to flow in the inductor L. When the signal CHG_V DD  is low that turns the switch M 2  OFF thereby turning ON the diode M 1  and charging C DD . This is repeated whenever V DD  falls below 1.8V. 
         [0032]      FIG. 6C  shows a circuit diagram  48  of the startup circuit used in accordance with the invention in the startup module  10 . The startup circuit  48  includes a motion activated switch S 1  that is connected to the drain of the CMOS switch M 2 . The source of the transistor M 2  is connected to ground. The gate of transistor M 2  is connected to CHG_V DD . A capacitor C TH  is connected to the thermo harvester output voltage V TH . An inductor L is coupled connected the capacitor C TH  and switch S 1 . The source of the diode M 1  is connected to the switch S 1  and the source of the transistor M 2 . The gate and drain of the diode M 1  is connected to the capacitor C DD . Also, the capacitor C DD  is connected to ground. 
         [0033]    The startup circuit  48  starts in an OFF state where the energy in all the main capacitors is below usable values. Mechanical vibrations due to motion triggers the switch S 1  to start the startup module  10 . The system starts off and the startup module  10  charges V DD  up to 1.8V. When V DD  is less than 1.8V, the CHG_V DD  signal is triggered which is used to transfer energy from the thermal input on to C DD . When CHG_V DD  goes high, the CMOS switch M 2  turns ON and causes current to flow in the inductor L. CHG_V DD  going low turns the switch M 2  OFF thereby turning on the diode M 1  and charging C DD . This is repeated when V DD  falls below 1.8V. 
         [0034]    When using thermoelectric harvesters, it is important to retrieve the energy available from the thermal harvester regardless whether the load circuit needs it at that point of time or not. This excess energy can be stored and used at a later time when the load demands increase. An efficient storage module  12  acts as a buffer needing a large amount of capacitance to smoothen the instantaneous power spurts 
         [0035]      FIGS. 7A-7B  show circuit elements that define the storage module  12 . In particular,  FIG. 7A  shows the circuit diagram of a storage circuit  56  used in accordance with the invention. The storage circuit  56  includes a NMOS switch M 4  whose drain is connected to an inductor L STO . The source of the transistor M 4  is connected to ground. The gate of transistor M 4  is connected to CHG_VSTO. A capacitor C TH  is connected to the thermoelectric harvester output voltage V TH  and ground. The inductor L STO  is connected to the capacitor C TH . The source of the CMOS transistor M 3  is connected to the inductor L STO  and the source of the transistor M 4 . The drain of the CMOS transistor M 3  is connected to the capacitor C sto . Also, the capacitor C DD  is connected to ground. A mechanical switch is not necessary in the storage module  12  because by the time the storage module  12  is activated, there is enough energy across C DD  to power the electronics. The power flow path from the thermal harvester to the storage capacitor C STO  is similar to that in the startup module  10 . 
         [0036]    When the storage module  12  is activated V DD  goes above 1.8V. During the rising edge of the CLK signal, if the comparator COMP senses that V DD  is greater than 1.8V, the CHG_VSTO signal goes high, which turns on transistor M 4  of the storage module. This causes current to flow in the inductor L STO . When CHG_VSTO goes low, the switch M 4  turns OFF. The switch M 3  in the storage module is not configured as a diode. The switch is turned ON using a PG signal. The switch M 4  needs to be ON long enough for the current in L STO  to reach zero. It should then turn OFF. 
         [0037]      FIG. 7B  shows a zero-current switching (ZCS) module  58  and a PULSEGEN module  60 . Both of these modules  58 ,  60  manage the timing and width of the PG pulse to achieve zero-current switching of the inductor current. The zero-current switching module  58  receives as input the PG signal and a VX_STO signal. The zero-current switching module  58  allows the switch M 4  to be ON long enough for the current in L STO  to reach zero by increasing or decreasing the pulse width of PG to achieve ZCS of the inductor current. The PULSEGEN module  60  receives as input the CHG_VSTO signal, DIS_STO signal, and a delay signal DEL to produce the PG signal that allows timing for zero-current switching. 
         [0038]    Achieving zero-current switching (ZCS) of the current in inductor L STO  requires the time for which the switch M 4  is ON (τ N ) to be related to the time for which the switch M 3  is ON (τ P ) by the following relation: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       τ 
                        
                       
                           
                       
                        
                       P 
                     
                     
                       τ 
                        
                       
                           
                       
                        
                       N 
                     
                   
                   = 
                   
                     
                       V 
                       TH 
                     
                     
                       
                         V 
                         STO 
                       
                       - 
                       
                         V 
                         TH 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   3 
                 
               
             
           
         
       
     
         [0039]    In this relation, both the voltages V TH  and V STO  are variable. The time for which the NMOS switch M 4  is ON is fixed by setting it to be equal to the pulse width of the CHG_VSTO signal, which is one-half the time period of the CLK signal. 
         [0040]    The width of PG (τ P ) needs to be equal to that given by EQ. 3 to achieve. This is achieved by observing the voltage at the node VX_STO immediately after the switch M 3  is turned OFF. If the switch M 3  is turned OFF too quick, for example if the pulse width τ P  is lower than that required, the remaining inductor current in L STO  turns ON the parasitic diode across M 3 . The voltage at VX_STO reaches above VSTO. If the switch M 3  is turned OFF too late, the current reverses direction in the inductor L STO . This drains the parasitic capacitor on the drain node first before turning ON the parasitic diode across M 4 . The voltage VX_STO goes below VSTO and eventually to below zero if τ P  is too large. 
         [0041]    Moreover, one can determine whether the pulse width τ P  is larger or smaller than necessary by comparing VX_STO with V STO .  FIG. 8  shows the circuit implementation of the ZCS module  80  which detects and compares this difference. The comparator  82  within the ZCS module performs the comparison within a fixed delay after the rising edge of PG signal. Depending on whether VX_STO is higher or lower than V STO , the 3-bit delay signal DEL&lt;0:2&gt; is either incremented or decremented by 1 using the ADD/SUBTRACT  84  block. 
         [0042]    The DEL&lt;0:2&gt; signal controls the PULSEGEN module  60  which provides the PG signal. The PG pulse is generated during the falling edge of CHG_VSTO. The width of the PG pulse is controlled using the DEL&lt;0:2&gt; signal. The PULSEGEN module  60  uses a delay line being tapered such that τ 1 &lt;τ 2 &lt; . . . &lt;τ 8 . Finer control of the pulse width in the lower order bits and coarser control in the higher order bits is provided. If the delay line is kept uniform, then the resolution of the delay line affects the efficiency of the boost converter much more when the width of PG is small. The delay line is made tapered to keep the percentage increase of the delay almost constant. The DIS_STO signal is used to disable the PULSEGEN module  60  till V STO  reaches 1.8V. This is because at low values of V STO , the switch M 3  cannot be turned ON. 
         [0043]    The PG signal is at V STO  when the PULSEGEN module  60  is disabled. This makes the switch M 3  to behave like a diode and V STO  gets charged through the diode M 3 . The PULSEGEN module  60  can use a comparator which compares V STO  with 1.8V and when found to be lower, makes the DIS_STO signal go high. The PULSEGEN module  60  behaves normally when V STO  goes above 1.8V and the DIS_STO signal is brought low. 
         [0044]    The maximum power that can be obtained from the thermoelectric harvester  2  shown in  FIG. 2  can be given by 
         [0000]    
       
         
           
             
               
                 
                   
                     P 
                     max 
                   
                   = 
                   
                     
                       V 
                       T 
                       2 
                     
                     
                       4 
                        
                       
                           
                       
                        
                       
                         R 
                         T 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   4 
                 
               
             
           
         
       
     
         [0045]    EQ. 4 follows the maximum power transfer theory. To get this maximum power, the load circuit and the thermoelectric harvester needs to present an impedance equal to R T . The maximum power can be extracted if the output voltage of the harvester (V TH ) is regulated close to V T /2. 
         [0046]    If the switch M 4  is constantly switched ON and OFF with the help of the CHG_VDD signal. The CHG_VDD signal is generated by the comparator COMP, as shown in  FIG. 6A , clocked at a frequency fs. When the comparator COMP triggers CHG_VDD at every cycle, then the frequency of CHG_VDD is also fs. Let the pulse width of the ON-time of CHG_VDD be τ n . This means that the time for which M 4  is ON every cycle is τ n . In steady state V STO  is regulated to be much higher than V TH . Thus, the time for which the switch M 3  is ON is very small compared to τ n . This can be seen from EQ. 3. 
         [0047]    The energy delivered to C STO  at every cycle assumes ideal modules being defined approximately as: 
         [0000]    
       
         
           
             
               
                 
                   
                     E 
                     cycle 
                   
                   = 
                   
                     
                       
                         V 
                         TH 
                         
                           
                               
                           
                           2 
                         
                       
                        
                       
                         τ 
                         N 
                         2 
                       
                     
                     
                       2 
                        
                       
                           
                       
                        
                       
                         L 
                         STO 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   5 
                 
               
             
           
         
       
     
         [0048]    This is repeated at every cycle which to leads the energy delivered to C STO  to be defined as: 
         [0000]    
       
         
           
             
               
                 
                   
                     P 
                     STO 
                   
                   = 
                   
                     
                       
                         E 
                         cycle 
                       
                       · 
                       
                         f 
                         s 
                       
                     
                     = 
                     
                       
                         
                           
                             V 
                             TH 
                             
                               
                                   
                               
                               2 
                             
                           
                            
                           
                             τ 
                             N 
                             2 
                           
                         
                         
                           2 
                            
                           
                               
                           
                            
                           
                             L 
                             STO 
                           
                         
                       
                        
                       
                         f 
                         s 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   6 
                 
               
             
           
         
       
     
         [0049]    The power delivered to C STO  during steady state is equal to the power extracted from the thermoelectric harvester. Using EQs. 4 and 6, one can get the following relation: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       TH 
                       2 
                     
                     
                       R 
                       T 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             
                               V 
                               TH 
                               
                                 
                                     
                                 
                                 2 
                               
                             
                              
                             
                               τ 
                               N 
                               2 
                             
                           
                           
                             2 
                              
                             
                                 
                             
                              
                             
                               L 
                               STO 
                             
                           
                         
                          
                         
                           f 
                           s 
                         
                       
                       ⇒ 
                       
                         
                           τ 
                           N 
                           2 
                         
                          
                         
                           f 
                           s 
                         
                       
                     
                     = 
                     
                       
                         2 
                          
                         
                             
                         
                          
                         
                           L 
                           STO 
                         
                       
                       
                         R 
                         T 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   7 
                 
               
             
           
         
       
     
         [0050]    When τ n  is designed to be one half the period of the CLK signal, then τ n =½f s . Therefore, under maximum power extraction f s  is defined as: 
         [0000]    
       
         
           
             
               
                 
                   
                     f 
                     s 
                   
                   = 
                   
                     
                       R 
                       T 
                     
                     
                       8 
                        
                       
                           
                       
                        
                       
                         L 
                         STO 
                       
                     
                   
                 
               
               
                 
                   EQ 
                   . 
                   
                       
                   
                    
                   8 
                 
               
             
           
         
       
     
         [0051]    By selecting the appropriate L STO  and R T , one can extract the maximum power from a thermoelectric harvester. For an R T  of 5Ω and an LSTO of 22 μH, f s  should be 28.4 kHz. The CLKGEN module  42  of  FIG. 6A  outputs the CLK signal having a frequency f s  in the nominal state. The extra bits of control are provided in the CLKGEN module  42  not only to account for process variations but also to adjust the clock frequency with change in R T  and L STO . 
         [0052]    The clock frequency can be set to achieve maximum power transfer once an appropriate thermoelectric harvester has been selected. The invention simplifies the means to extract maximum power, instead of using the more complex maximum power tracking loops. Given EQ. 8 is independent of V T , the circuit will settle at the maximum power regardless of changes in V T  due to temperature. 
         [0053]      FIG. 9  shows a circuit arrangement  64  of the DC-DC converter module  14 . The circuit arrangement  64  includes two comparators COMP 1  and COMP 2 . The input node VP of COMP 1  is connected to resistive divider network having two resistors with resistances of 2.5 MΩ and 1.6 MΩ. A capacitor C DIV1  is connected to one of the resistors of the divider network (1.6 MΩ) and ground. The 2.5 MΩ resistive element is connected to voltage V L . The input node VN of COMP 1  is connected to voltage V REF . The input node VP of COMP 2  is connected to another resistive divider network having two resistors with resistances of 2.9 MΩ and 1.2 MΩ. A capacitor C DIV2  is connected to one of the resistors of the divider network (1.2 MΩ) and ground. The 2.5 MΩ resistive element is connected to voltage V STO . The input node VN of COMP 2  is connected to voltage V REF . The output node OUTP of COMP 2  outputs the VSTO_ 2 P 4 + signal and delivers this signal is to the output node OUTN of COMP 1 . The output node OUTN is connected to the CLK signal. The output node OUTP of COMP 1  outputs the signal VL_ 1 P 8 +. 
         [0054]    A pulse-width control module  66  receives as input the signal from the output node OUTN of COMP 1  and a delay signal DEL_DCDC. The pulse-width control module  66  provides an output signal to an integrator as input and a NOT gate  72 . An integrator  68  also receives as input the signals V DD  and V STO . The NOT gate  72  provides its output signal to a NOT gate  74 . The output signal of the NOT gate  74  is connected to the gate of CMOS power transistor M 7 . The pulse-width control module  66  provides its output signal to a NOT gate  70 . The NOT gate  70  also receives as input the signal DIS_DCDC. The NOT gate  70  provides its output signal to a NOT gate  76 . The NOT gate  76  provides its output signal to a NOT gate  78 . The output signal of the NOT gate  78  is connected to the gate of the NMOS power transistor M 8 . The source of M 8  is connected to the V STO . The drains of the M 7  and M 8  are coupled at the voltage point VX_DCDC. An inductor L DCDC  is connected to the drains of M 7  and M 8  as well the capacitor C L . Also, the capacitor CL is connected to ground. 
         [0055]    The voltage V STO  at the output of the storage module  12  is not suitable for power circuits directly because it is unregulated and variable. It is necessary that the DC-DC converter module  14  provides a regulated power to the load elements. The DC-DC converter module  14  regulates the output voltage V L . Also, the DC-DC converter module  14  employs a closed-loop control technique to do zero-current switching of the inductor current. The DC-DC converter module  14  employs pulse-frequency modulation mode of control to regulate V L . 
         [0056]    The comparator COMP 1 &#39;s output feeds the clock to comparator COMP 2 . The DC-DC converter module  14  is designed to be activated only when V STO  is above 2.4V. The comparator COMP 1  compares a suitably divided version of V STO  with the reference voltage V REF . Only when V STO  goes above 2.4V does the signal VSTO_ 2 P 4 + gets activated. The clock to the comparator COMP 2  is gated when V STO  is less than 2.4V thereby disabling the DC-DC converter module  14 . The overhead of using multiple comparators is not too large. The area occupied by the comparator itself is minuscule. Also, the power consumed by them is much less than 1 μW. 
         [0057]    The comparator COMP 2  is used to regulate V L  to 1.8V. The output voltage is set at 1.8V, but this can be easily changed to an arbitrary value by varying the resistance divider network of the comparator COMP 2 . When V L  falls below 1.8V, The comparator COMP 1  proceeds to send a pulse, via output node OUTN, to the pulse-width control module  66  when V L  falls below 1.8V. This turns ON the power transistors M 7 , M 8  to transfer charge from V STO  to V L . The pulse-width control module  66  employs a closed-loop control to achieve ZCS similar to the that described for the ZCS module  58  of  FIG. 7A . However, since the control here is for a DC-DC converter module  14 , the process of accomplishing ZCS is rather different then the storage module  12 . In this case, the voltage at the drain nodes of the power transistors M 7  and M 8  (VX_DCDC) is compared to ground instead of VX_STO. The comparison takes place immediately after the NMOS power transistor M 7  is turned OFF by the pulse-width control module  66 . If the NMOS transistor M 7  is turned OFF too quick, the remaining inductor current in L DCDC  turns ON the parasitic diode across the NMOS transistor M 7 . This forces the voltage at VX_DCDC to fall to a diode drop below ground. 
         [0058]    When the NMOS transistor M 7  is turned OFF too late, the inductor current reverses direction and the parasitic diode across the PMOS transistor M 8  turns ON after the parasitic capacitance at the drain node gets charged to V STO . This brings the voltage VX_DCDC to go above V STO . Thus, by comparing VX_DCDC with ground, one can determine whether the NMOS pulse width is larger or smaller than necessary. The comparison takes place a fixed delay after the falling edge of NIN. Depending on whether VX_DCDC is higher or lower than ground. Based on this, the 3-bit delay signal DEL_DCDC is either incremented or decremented by 1. This 3-bit DEL_DCDC signal controls the PULSEGEN module  60 , of  FIG. 6A , which provides the drive signals for the PMOS M 8  and NMOS M 7  power transistors. The PMOS ON-time is set to a fixed value. The rising edge of the PMOS M 8  pulse triggers the PULSEGEN module  60 . The pulse-width control module  66  controls the width of the pulse produced by the PULSEGEN module  60  using the 3-bit DEL_DCDC signal to achieve ZCS. 
         [0059]    When V DD  reaches 1.8V, the VL 1P8+ signal goes high to short the capacitors C L  and C DD . V DD  and V L  are shorted and the power to V DD  flows through the storage module  12  and not directly from the thermal harvester. This eliminates the time sharing of the thermal input between the startup and storage modules  10 ,  12 . This happens because once V L  and V DD  are just above 1.8V, the CHG_VDD signal never gets triggered. Under this arrangement, the storage circuit  56  of the storage module  12  is always active all the time instead of time-sharing it with the startup circuit  48 . The storage circuit  56  can switch at a constant frequency determined by the maximum power transfer considerations. 
         [0060]    Thus, efficient operation of the thermoelectric energy harvester circuit is achievable. Also, this arrangement further improves efficiency because transferring power to V DD  through the startup module  10  is inefficient owing to using a free-wheeling diode. The shorting is disabled once the voltage V DD  falls below 1.6V. 
         [0061]    The invention allows thermoelectric elements to harvest thermal energy present in everyday surroundings like on the human body to provide usable electrical power. The voltage output by the thermoelectric elements is proportional to the temperature difference across them. This is of concern while using thermal harvesters in body-worn applications as the voltage output by the harvester is only 25-50 mV in most cases. The invention allows circuits to interface directly with and extract power out of thermoelectric generators. This enables load circuits like processors and radios to operate directly using a thermoelectric generator without the aid of a battery. 
         [0062]    Moreover, the invention provides a complete power management solution that could extract electrical power efficiently from the harvester independent of the input voltage conditions. With a regulated output voltage makes it easier to interface to load circuits on the other end. With the help of closed-loop control techniques, the energy processing circuit is able to maintain efficiency over a wide range of load voltage and process variations. The power management solution provided is ideal for low-power applications. 
         [0063]    Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.