Abstract:
A semiconductor device assembly package includes a semiconductor device having components thereon which are generic to a variety of applications by manipulation of the pinout configuration. The lead frame includes redundant leads for connection to the semiconductor device, as desired. The semiconductor device may include redundant wire bond pads, each redundant pair including one pad on a lateral edge and one pad on a non-lateral edge of the die. In applications requiring less than all of the available leads, the pinout configuration of the leadframe is adjusted to use the extra space from unused NC leads and missing pins for providing wider, shorter leads with reduced inductance, and wider paddle arms for reduced bending and breakage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of application Ser. No. 09/016,678 filed Jan. 30, 1998, pending. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to semiconductor devices in general, and more particularly to redundant pinout package configurations for connecting the semiconductor device to a host electronic apparatus or substrate.  
           [0004]    2. State of the Art  
           [0005]    Modern packaged integrated circuits (IC) comprise one or more encapsulated semiconductor devices or chips within a protective “package” of plastic, ceramic, other moldable material, or hermetically sealed package. Typically, a large number of semiconductor devices are formed from a wafer made from a semiconductor material such as silicon, germanium or gallium arsenide. Microscopic circuits are formed on a surface of each semiconductor device by photolithographic techniques and are typically attached to a lead frame with conductive wires. More particularly, a plurality of leads of the lead frame is connected to bond pads on the semiconductor device or semiconductor dice, enabling the dice to be electrically interconnected to an external electrical apparatus.  
           [0006]    On first generation IC devices, the semiconductor devices were relatively large, consuming most of the package space. The number of leads attached to the semiconductor device was also very limited. Thus, wide, short leads located adjacent the bond pads of the semiconductor device were used. The resulting wire bonds were short, and the inductance between the semiconductor device and the host apparatus was low.  
           [0007]    In later generation IC devices, the semiconductor devices have become progressively smaller while the numbers of leads have typically increased. As a result, the lead frame leads of such semiconductor devices must, of necessity, be much narrower and much longer, both of which increase the lead inductance and slow the speed of the device. In addition, the high density of wire connections typically makes wire bonding more difficult and results in an increase in bond failures. Furthermore, with very small semiconductor devices, the very fine wires connecting the semiconductor device to the leads of the lead frame may be very long, resulting in “wire sweep,” sagging, short circuiting, and bond failure during encapsulation.  
           [0008]    High inductance and reduced speed limit the usefulness of the packaged semiconductor device while shorting or destruction of the wire bonds will make the semiconductor device useless.  
           [0009]    In the conventional package having a semiconductor device attached to a paddle, a reduction in device size and increase in bond pad density have also resulted in the die paddle support arms being longer, narrower, and weaker. Thus, problems in supporting the semiconductor device during attachment and wire bonding have increased.  
           [0010]    The required spacing, width, and length of leads and wires have become a serious limitation in the further size reduction of semiconductor devices. While complex integrated circuits may be formed in very small semiconductor devices, connecting such a device or devices to a host apparatus while maintaining the semiconductor device characterization may be very difficult.  
           [0011]    There have been various attempts at overcoming the high inductance or interactive conductance effects of small semiconductor devices. For example, in U.S. Pat. No. 5,521,426 to Russell, a leads-over-chip (LOC) semiconductor device with long, narrow leads is disclosed. In order to decrease the capacitance between the leads and the semiconductor device and increase lead strength, the leads are stamped or rolled to have a non-rectangular cross-section, such as a “U” configuration. Thus, the strength of the lead and its cross-sectional area are increased, resulting in less lead sag and reduced capacitative interaction. However, the cost of producing such leads is considerable, and the package thickness is increased. Furthermore, the method does not increase the size of wire bonding areas on the lead fingers of the lead frame, and the wire bonding operation is no easier.  
           [0012]    While custom and semi-custom semiconductor devices are widely used in the electronics industry, a large part of the semiconductor device market is filled by semiconductor devices which may be used in a variety of applications, by using less than the maximum number of functions provided by the circuits thereon. Such a versatile semiconductor device may generally be made more cheaply than each of the custom semiconductor devices which it replaces. The current practice in the semiconductor industry is to produce semiconductor devices which have a generally wide versatility, i.e. they may be connected in different apparatus for performing a variety of electronic functions.  
           [0013]    In a semiconductor device, more than one bond pad may be connected to a single a lead frame, or more than one exterior lead may be connected to a single bond pad. In many cases, however, each bond pad is connected to a single exterior lead of a lead frame.  
           [0014]    The particular lead finger of a lead frame with which a bond pad is connected determines the “pinout” for that bond pad for the packaged semiconductor device. For example, in a dynamic random access memory (DRAM), if a bond pad on the semiconductor device which corresponds to Address 0 (AO) is bonded to the lead finger of a lead frame corresponding to Output Pin  5 , the pin  5  on the package is used as AO. This hard wires the bond pad on the semiconductor device to the output of the lead frame, and remains that way for the life of the packaged semiconductor device.  
           [0015]    U.S. Pat. No. 5,360,992 of Lowrey et al. proposes a two-part or three-part semiconductor package by which a semiconductor device circuit may be adapted to a variety of host apparatis following encapsulation of the device. Various “lead frames” of differing configurations are alternatively joined or attached to the encapsulated semiconductor device to provide the required pinout pattern. This method does nothing to reduce lead length (lengths may be increased) or increase the lead width.  
           [0016]    In U.S. Pat. No. 5,256,598 of Famworth et al., the concept of using a single “generic” lead frame for semiconductor devices of various sizes, cutting a device placement hole in the lead frame to match a particular device size, is illustrated. The number of lead fingers is fixed, and must be the maximum usable with the variety of semiconductor devices to be accommodated. As the semiconductor device size is decreased, the lead lengths must, of necessity, be increased and their widths decreased, so the problem of high inductance is not solved.  
           [0017]    It has been proposed to build functional redundancy into semiconductor devices, whereby extra circuit components are included to be used if one or more components are defective or inoperable. A larger semiconductor device must be used to accommodate the extra components as well as the extra circuitry for detecting functioning/non-functioning components and direct the selection of a functioning component. In addition, it may be necessary to provide means, such as a fuse, to internally disconnect unused circuitry. While such redundancy in electronic devices may be very useful at the design and development stages, it is of limited use in large scale production.  
           [0018]    Whether the semiconductor device is configured to have a “generic” register for adaptation to many applications, or has functional redundancy, or both, in nearly all cases there are “No Connects” (NC) and/or missing pins identified in the registration. “No Connect” leads are typically found in a central portion of the lead frame, where bonding wires are usually short. Examples of such are the 20/26L SOJ (small outline J-bend) and 44/50L TSOP II (thin small outline package) devices.  
         BRIEF SUMMARY OF THE INVENTION  
         [0019]    The present invention is directed to a configuration for a semiconductor device where the package pinout registration has redundancy for critical signals to provide low inductance and high yield for all generations of the packaged semiconductor device.  
           [0020]    The invention comprises the configuration of a semiconductor device wherein central lead locations normally identified in the register as “No Connects” (NC) or missing pin locations (MP) are used to provide redundancy for critical leads in the packaged semiconductor device. “No Connect” pin locations of the semiconductor device are reassigned to be those closer to the periphery of the lead frame, and cropped to allow the use of wider, shorter lead fingers for the other longer, narrower lead fingers of the lead frame. As a result of this redundant pinout scheme for the packaged semiconductor device, (a) wire bonding is faster and easier, (b) wire bond integrity and reliability are enhanced, (c) the shorter wires avoid problems with “wire sweep,” (d) the lead frame is stronger and less subject to damage in handling, (e) signal integrity is increased, (f) the speed grade of the device is increased because of the reduced lead/wire inductance, and (g) a higher value product may be manufactured at lower cost. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0021]    In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:  
         [0022]    [0022]FIG. 1 is a plan view of a semiconductor device and attached lead frame of a first generation prior art semiconductor device;  
         [0023]    [0023]FIG. 2 is a plan view of a semiconductor device and attached lead frame of a later generation prior art semiconductor device;  
         [0024]    [0024]FIG. 3 is a plan view of a semiconductor device and attached lead frame of a semiconductor device of the present invention; and  
         [0025]    [0025]FIG. 4 is an enlarged plan view of the active surface of an exemplary semiconductor device having redundant bond pads enabling a pinout configuration of the invention which provides signal and construction enhancement. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]    A semiconductor device and lead frame configuration of an early generation prior art semiconductor device  10  is illustrated in drawing FIG. 1. As shown, the relatively large semiconductor device  12  is mounted on a paddle  14  of a lead frame  16  having a typical width  34  of less than one inch to several inches or more. A lead frame  16  typically has a recurring pattern of paddles  14  and leads  18  (including inner leads  18 A and outer leads or pins  18 B) for accommodating a plurality of semiconductor dice  12 , and has index holes  36  in the outer, supportive lead frame rails  38  for sequential positioning of the lead frame in a wire bonding machine. The edges of the semiconductor device  12  facing the lead frame rails  38  will be known herein as lateral edges  13 . The relatively short and wide lead fingers, i.e. inner leads  18 A, are shown with enlarged wire bond areas  22 . Conductive wires  26  connect the wire bond areas  22  of the inner leads  18 A to the peripheral bond pads  28  on the active surface of the semiconductor device  12 . Following wire bonding, the semiconductor device  12  and lead frame  16  are encapsulated, typically with a polymeric or ceramic material, to form a package  20 . The dam bars  30  between the outer leads  18 B are cut away, and the tie-bars  32  are trimmed to singulate each lead  18 , enabling electrical connection of each bond pad  28  to an electronic apparatus, not shown, with minimum lead inductance. In addition, the paddle arms  15  are excised from the frame rails  38 . The use of a large semiconductor device  12  with a relatively small number of peripheral bond pads  28  permits the use of relatively short, wide inner leads  18 A having low inductance.  
         [0027]    The leads  18  may be conventionally designated in the lead register as power supply voltage VCC, reference voltage VSS, data input DIN, data output DOUT, write enable signal WE, raw address strobe RAS, address signal A, column address strobe CAS, output enable OE, and other labels as required. The particular labels designated in the lead register may differ from manufacturer to manufacturer and differ depending upon the use to which the device is applied.  
         [0028]    In order to lower their overall cost, semiconductor devices  10  are typically made to be used in a variety of applications, and in most applications, only some of the leads  18  are used. This is particularly true of the address signal A leads. Thus, while some leads  18  such as VCC, VSS, DIN, DOUT and WE may be used in all or nearly all applications, only some of the address signal (A) leads are typically used, leaving some leads as unused no-connect NC leads  24 . The leads  18  most prone to causing induction noise, i.e. Vcc, Vss, DIN, DOUT and WE, are conventionally located nearest the lead frame rails  38  to minimize inductive interaction with the signal A leads. Thus, in a particular application, the longest inner leads  18 A (most prone to induction effects) are used while some of the shortest inner leads  18 A near the center of the lead frame  16  (least prone to induction effects) become unused as NC leads  24 .  
         [0029]    An exemplary semiconductor device  40  of a later generation is shown in drawing FIG. 2 following a wire bonding step. For purposes of comparison, the lead frame width  65  is the same as the lead frame width  34  of drawing FIG. 1. The semiconductor device  42  is much smaller than the semiconductor device  12  of drawing FIG. 1, and is shown attached to a die paddle  44  of the lead frame  46 . Peripheral bond pads  58  on the semiconductor device  42  are connected by bond wires  56  to wire bond areas  52  on the inner leads  48 A of the lead frame  46 . Due to the narrow spacing of inner leads  48 A attached to the lateral edges  43  of the semiconductor device  42 , the wire bond areas typically comprise unenlarged lead ends  64  for most of the inner leads  48 A. Each lead  48  comprises an inner lead  48 A and an outer lead  48 B, the latter ultimately configured for attachment to a host electronic apparatus, not shown.  
         [0030]    The leads  48  of the conductive lead frame  46  are attached to the side rails  68  by dam bars  60  and tie bars  62 . The paddles  44  are attached to the side rails  68  by the paddle arms  45 , as known in the art, and the side rails  68  include index holes  66 .  
         [0031]    The package  50  is formed following wire bonding, by encapsulation and subsequent excision of dam bars  60 , tie bars  62  and paddle arms  45  from rails  68 .  
         [0032]    The much reduced size of the semiconductor device  42  results in much longer paddle arms  45 . Thus, the propensity to bending and breakage of the paddle arms  45  is increased as the semiconductor device  42  becomes smaller. In some cases, it may even be necessary to reduce the width of the paddle arms  45  to accommodate the inner leads  48 A, further exacerbating the problem.  
         [0033]    The semiconductor device  40  is shown with eight No Connect (NC) leads  54 , most located generally centrally between the rails  68  adjacent the non-lateral edges  51  of the semiconductor device  42 . The leads  48  generally most subject to induction effects are those designated as VCC, VSS, DIN, DOUT, WE, RAS, and CAS. These leads, being generally closest to the rails  68  and connected to bond pads  58  along the lateral semiconductor device edges  51 , are, of necessity, increased in length and decreased in width from devices using larger semiconductor devices (such as shown in drawing FIG. 1). Thus, in the device of drawing FIG. 2, the propensity for generated induction is significantly increased, while at the same time, leads which may be both shorter and wider are unused, i.e. are NC leads  54 . These difficulties are addressed by the redundant pinout configuration of the invention.  
         [0034]    Turning now to drawing FIGS. 3 and 4, a device  70  having the semiconductor device  72 /leadframe  76  configuration of the invention is depicted as a modification of the device  40  of drawing FIG. 2. The semiconductor device  72 , substantially square in shape, is shown as having a substantially similar outline as the semiconductor device  42  of drawing FIG. 2. The semiconductor device  72  has a “generic” circuit, logic, memory, or both, which may be useful in a variety of applications by using less than the entire circuit. The semiconductor device  70  may have redundant functions in its circuit, each with its own bond pad  88 A. Alternatively, the semiconductor device  72  may have redundant bond pads  88 A for an individual functional area of the semiconductor device circuit. The former type of redundancy typically requires a larger semiconductor device  72 , is considerably more expensive to manufacture, and may require a provision for electrical disconnection of some unused internal conductors, e.g. by fuses installed within the die. On the other hand, bond pad redundancy typically requires only that additional small areas of the metallization semiconductor device circuit be exposed as bond pads by removal of an overlying passivation layer. Thus, bond pad redundancy rather than function redundancy in the semiconductor device  72  is preferred.  
         [0035]    When compared with drawing FIG. 2, the semiconductor device  72  of drawing FIGS. 3 and 4 is shown with bond pads  88  as well as bond wires  86  connected thereto. Some of the bond pads  88  are redundant bond pads  88 A connected to the same portion of the semiconductor device circuit. These redundant bond pads  88 A are identified by enclosed circles and are redundant to bond pads which they have replaced. The latter are identified as pads  88 B, and are now unused Non Connect (NC) bond pads (shown with blank centers). Bond pads  88 C are shown as being unchanged from the semiconductor device  40  of drawing FIG. 2 to device  70  of drawing FIG. 3, and are connected by wires  86  to the corresponding inner leads  78  (drawing FIG. 3). These bond pads  88 C are represented by filled-in squares.  
         [0036]    In the example depicted in drawing FIGS. 3 and 4, redundant bond pads  88 A are connected to semiconductor device circuit functions designated as DIN, DOUT, WE, A 2 , A 3 , A 4 , A 5 , A 0 , A 1 , A 7 , A 8 , A 10 , and A 6 , previously identified. The inner leads  78 A which are wire bonded to these redundant bond pads  88 A are primarily in the central portion of the lead frame  76  between the two rails  98 , i.e. along axis  102 . Most or all of the redundant bond pads  88 A are positioned along the non-lateral edges  91  of the semiconductor device  72 , to be aligned with the corresponding inner leads  78 A. Thus, the inner leads  78 A for the DIN, WE, DOUT, and A 2  through A 6  functions are each shorter and/or wider than the comparable prior art leads  48  of drawing FIG. 2. Leads  48  which represented these functions in the prior design of drawing FIG. 2 are in drawing FIG. 3 excised as No Connect (NC) leads  78 B. Additional room is thus created for the remaining leads  78 C connected to bond pads  88 C on the lateral edges  90  of the semiconductor device  72 ; these leads may be made wider to further reduce the inductance.  
         [0037]    In the example shown, the minimum width  94  of the critical function leads in semiconductor device  70  is about 30-60 percent greater than the minimum width  92  of the comparable leads in semiconductor device  40 .  
         [0038]    Likewise, the maximum total length  100  of the critical function leads in semiconductor device  70  is typically less than about 90 percent of the maximum length  96  of the comparable leads in semiconductor device  40 .  
         [0039]    Following the wire bonding operation, the lead frame  76  and attached die  72  are encapsulated and extraneous lead frame portions excised to form a semiconductor device package  80 .  
         [0040]    In an additional advantage of this invention, a portion of the additional space adjacent the lateral semiconductor device edges  90  may be used to widen the paddle arms  75  for increasing their strength and rigidity. This is evident by comparing the paddle arms  75  of FIG. 3 with paddle arms  45  of drawing FIG. 2. The wider paddle arms  75  provide a more sturdy platform for the die  72 , resulting in less breakage from handling and fewer wire bond failures.  
         [0041]    A semiconductor device  10 ,  40  may be installed in an electronic apparatus whereby all of the outer leads or pins are used. However, the more usual applications require connection to less than all of the available pins. In such cases, the redundant pinout configuration of the semiconductor package results in signal enhancement and manufacture with a lower reject rate.  
         [0042]    It is evident that the present invention may be applied to semiconductor device configurations and packages other than those illustrated herein. For example, a lead over chip (LOC) package with outer leads, i.e. pins, on four sides may benefit from the invention. No Connect (NC) leads and missing pins are replaced by leads connected to redundant bond pads on the semiconductor device, and/or the otherwise wasted space is used to accommodate widened existing leads.  
         [0043]    It is apparent to those skilled in the art that there is provided herein according to the invention a redundant pinout configuration for enhancing the operability and construction of a semiconductor device package. Although the semiconductor device has been described and illustrated with reference to a specific embodiment thereof, it is not intended that the invention be limited by the illustrated embodiment. Those skilled in the art will recognize that various modifications can be made without departing from the spirit and intent of the invention. For example, the invention is not limited to devices having peripheral bond pads nor to a specific number or types of leads, bond pads, dies, encapsulant, etc. Also, the invention may be used in semiconductor devices in which the device is attached to the leadframe by a non-conductive plastic layer, eliminating the paddle. Furthermore, the particular lead register may differ. Thus, it is intended that this invention encompass all such modifications and variations which fall within the scope of the appended claims.