Abstract:
A digitally controlled oscillator (DCO) generating an output clock includes a jitter shaping module for shifting low frequency digital jitter on the output clock into higher frequency jitter.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to the field of signal processing, and in particular to a digitally controlled oscillator (DCO) for generating clock signals. 
       BACKGROUND OF THE INVENTION 
       [0002]    In processing mixed analog and digital signals, one of the most important factors for good performance of an analog circuit, as part of a mixed signal circuit, is the amount of jitter in bandwidth of interest of the analog circuit. Jitter manifests itself as unwanted variation in the interval between clock pulses. This factor is extremely important in situations where the analog part of the circuitry uses a digital clock for its sampling or over-sampling clock (e.g. analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). 
         [0003]    In the digital era, where the trend is to use as many digital circuits as possible, digital clock synthesizers (i.e. DCOs) are used more and more to create sampling clocks for different analog circuits. DCO generated clocks have uniformly distributed jitter ranging from DC up to half of the clock carrier frequency. Since this bandwidth always includes the range of interest of most mixed signal circuits, there is a need for a circuit that can shift digital jitter into high frequency area, outside the range of interest, where the performance of the circuits is not affected. 
         [0004]    In previous implementations, e.g. ADC and DAC converters, a clean clock from a crystal oscillator was used as a sampling clock. When a network clock, or clock from a digital source, such as DCO, had to be used as sampling clock, the DCO output clock was first filtered with an analog phase locked loop (APLL) before being used. 
         [0005]    U.S. Pat. No. 6,396,313 describes a jitter shaping circuit. This jitter shaper has a peak-to-peak jitter that increases with order with  2  master clock cycles per order. 
       SUMMARY OF THE INVENTION 
       [0006]    The invention provides a digitally controlled oscillator (DCO) with the capability of shifting low frequency digital jitter, on its output clock, into higher frequency jitter. Embodiments of the invention permit the reduction of the sampling clock jitter, within the bandwidth of interest for a mixed signal circuit, with fully digital circuit, which is smaller in size and consumes less power than an equivalent circuit with DCO followed by an APLL. In addition to size and power advantages, embodiments of this invention give better results of jitter suppression at the bandwidth of interest due to the fact that APLLs have jitter gain in low frequency area. The invention allows mixed signal circuits to perform better in removing other type of noise that needs to be removed from signals that are being processed. 
         [0007]    Accordingly therefore the invention provides a digitally controlled oscillator (DCO) for generating an output clock, comprising an overflow counter for generating an output signal determined by a clock frequency signal; a frequency control adder responsive to a frequency control input value to determine the frequency of said output clock; a DCO accumulator for accumulating the output of said frequency control adder and generating an enable signal for said overflow counter, said DCO accumulator also outputting a remainder value with said enable signal; and a jitter shaping circuit for shifting low frequency digital jitter on the output clock into higher frequency jitter, said jitter shaping circuit comprising: a jitter shaping accumulator for accumulating an error in edge placement; a clock advancement circuit for advancing the output signal from the overflow counter whenever there is an overflow of the jitter shaping accumulator; and an error resolution circuit for normally setting the input to said jitter shaping accumulator as the remainder value or the difference between said remainder value and said frequency value when an adjustment in edge placement of said output signal occurs. 
         [0008]    The invention can be used in mixed signal circuits to generate clocks that are necessary for analog part of the circuit, as well as in digital circuits to generate clock that can be used by external analog or mixed signal devices. 
         [0009]    Functionality of the DCO can be simplified by presenting it as an accumulator that can have fixed numerical value on its input, run by a high frequency master clock. Depending on the input value, the accumulator will overflow after certain number of master clock cycles. The overflow bit can be used as gating signal for the master clock in order to generate the output clock (logical AND function), which will on average have desired clock frequency. 
         [0010]    The input value to the accumulator is proportional to the desired clock frequency. The phase difference between the output clock and the ideal clock is proportional to the accumulator value at the time of overflow, named remainder. When the remainder value is zero at the time of the overflow the output clock edge is phase aligned with the ideal clock edge. The maximum value of the remainder represents the biggest phase error in the output clock edge position. Each different value in the accumulator, at the point of the overflow, also represents amplitude of the output clock jitter. Since the accumulator can have any possible value at the overflow, the output clock jitter amplitude will have any value between zero and one master clock period. When the output clock frequency does not have common denominator with the master clock frequency, all jitter components will be randomly distributed with equal probability; therefore the output clock jitter will have uniform distribution. 
         [0011]    The invention is based on the use of the DCO accumulator remainder to change the output clock position, such that additional clock edge repositioning will be performed for low frequency changes, therefore shifting low frequency jitter into high frequency jitter. 
         [0012]    The DCO accumulator remainder value, representing error in the output clock edge placement, is additionally accumulated. Overflow value of the additional remainder accumulator is used to determine whether the edge repositioning is necessary or not. The overflow signal is also used as the feedback signal to the remainder accumulator, by changing the remainder accumulator input value when the overflow happens. 
         [0013]    The invention is more efficient than the shaper described in U.S. Pat. No. 6,396,313 because maximum peak-to-peak jitter produced by is in one embodiment 2 master clock cycles, regardless of jitter shaping order (jittershaper produces maximally master clock cycle peak-to-peak of high frequency jitter on top of one master clock generally uniformly distributed frequency coming from the DCO). In case of the prior art jittershaper, peak-to-peak jitter increases with order with 2 master clock cycles per order. The jitter shaper of the present invention will just increase high frequency components when order is increased—it will never advance output clock for more than one master clock cycle. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The invention will now be described in more detail, by way of example only, with references to the following drawings, in which: 
           [0015]      FIG. 1  is a top-level block diagram of the DCO circuit according to the preferred embodiment; and 
           [0016]      FIG. 2  is the block diagram of the Jitter Shaping module from  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0017]    The noise reduction circuit comprises three main blocks, namely a digital controlled oscillator (DCO), a noise activity detector, and a spectral gain estimator. 
       DCO Overview 
       [0018]    As shown in  FIG. 1 , the DCO in accordance with an embodiment of the invention consists of a Frequency Control Adder  10 , the DCO Accumulator  11 , the Overflow Counter  12  and the Jitter Shaping Module  13  of first or higher orders. All static control signals for the DCO come through the Control Bus  14 , from external registers (not shown). In addition to the static control signals, there is an additional control bus  15  for the DCO center frequency control—feedback frequency control bus (‘fbk_freq_ctrl’). By using the feedback frequency control bus  15 , the DCO can be part of a digital phase locked loop (DPLL) that locks its output clock to an input reference clock. The feedback frequency control usually comes from a phase detector. Its value (2&#39;s complement binary number) is proportional to a phase difference between the DCO output clock and the input reference clock, such that the DCO center frequency is adjusted toward reducing the phase difference. 
         [0019]    The static control signals are:
   Freerun control signal  16  (‘freerun’), which determines whether the DCO output clock (‘clk_out’)  17  will be locked to an input reference signal (represented by ‘fbk_freq_ctrl’ control bus  15 ), or whether it will be free-running (based on local frequency oscillator).   Center frequency number (CFN)  18 , which is a 2&#39;s complement binary number that represents the desired DCO center frequency, which is binary divided inside the Overflow Counter to get required output clock frequency.   Output clock frequency control (‘clk_freq’)  19 , which is a control word that selects the desired output clock frequency.   Jitter shaping enable signal (‘on/off’), which is used to turn the jitter shaping on or off.   
 
         [0024]    The DCO center frequency, the highest DCO frequency that can be binary divided to a desired output clock frequency, can be chosen, based on the master clock frequency (‘mclk’), by programming appropriate CFN value into one of the control registers, using the following equation: 
         [0000]    
       
         
           
             
               f 
               DCO 
             
             = 
             
               
                 
                   CFN 
                   + 
                   
                     fbk_freq 
                      
                     _ctrl 
                   
                 
                 
                   2 
                   
                     DCO_ACC 
                      
                     _WIDTH 
                   
                 
               
               * 
               
                 f 
                 mclk 
               
             
           
         
       
     
         [0000]    where, f DCO  represents the DCO center frequency, DCO_ACC_WIDTH represents width of the DCO Accumulator, and f mlck  represents the master clock frequency. 
         [0025]    In the DCO freerunning mode, when the ‘fbk_freq_ctrl’ value is zeroed, the DCO center frequency is proportional to the master clock frequency. 
         [0026]    The feedback frequency control word (‘fbk_freq_ctrl’) is being added to the DCO Center Frequency Number (‘dco_cfn’) inside the Frequency Control Adder. The resulting bus ‘frequency’ is used as one of the Jitter Shaping Module inputs. The output of the adder (‘frequency’) is accumulated in the DCO Accumulator, consisting of the second adder and the register running on the master clock frequency (‘mclk’). The carry bit (‘dco_overflow’) of the accumulator is used as enable signal for the Overflow Counter  12 , which counts how many times the DCO has overflowed. The counter wraps around when it reaches the maximum (2 DCO     —     ACC     —     WIDTH −1). The overflow signal (‘dco_overflow’) and the remainder (‘remainder’) of the DCO Accumulator are also used as Jitter Shaping Module inputs. The ‘remainder’ consists of all bits of the Accumulator, excluding the most significant bit (‘dco_overflow’). 
         [0027]    The Overflow Counter output (‘low_freq_ovf’), coming directly from one of the counter bits, represents an output clock with desired frequency, which is chosen by the output clock frequency control bus (‘clk_freq’). The ‘low_freq_ovf’ is also used as the Jitter Shaping Module input. The Overflow Counter is a basic binary counter, running on the master clock frequency (‘mclk’), with counting enable signal (‘dco_overflow’). 
         [0028]    To perform jitter shaping on the Overflow Counter output (‘low_freq_ovf’), the Jitter Shaping module is used. 
       Jitter Shaping 
       [0029]    For a given clock frequency and accumulator width, the DCO output clock frequency can only have discrete values. Therefore, the desired output clock frequency has limited accuracy. The remaining value in the DCO Accumulator at a carry (‘remainder’) represents the exact phase error of the carry pulse (‘dco_overflow’) with respect to an ideal signal. 
         [0030]    The error is maximally 1/f mclk  [sec] and it represents the intrinsic jitter of the DCO. Increasing the master clock frequency (‘fmclk’) reduces the intrinsic jitter. The ‘remainder’ can be used to correct the phase of the carry pulse, thereby allowing output jitter to be shaped. The remaining quantization error (jitter) can be removed over time by taking the rounding-error into account at the next rounding. 
         [0031]    The Jitter Shaping circuit, shown in  FIG. 2 , is used for clock generation. In the embodiment shown in  FIG. 2 , the Jitter Shaping module  13  consists of the Error Resolution circuit  20  containing subtractor  31  and registers  32 ,  33 , the Clock Advancement circuit  21  containing flip flops  23 ,  24 ,  25  and the Jitter Shaping Accumulator  22  containing adder  34  and register  35 . 
         [0032]    The error in the edge placement is accumulated in the Jitter Shaping module  13 . Input to the Jitter Shaping Accumulator  22  is the error in the edge placement. As determined by the Error Resolution circuit, the error is represented by either the DCO ‘remainder’ or difference between the DCO ‘remainder’ and the DCO ‘frequency’. 
         [0033]    Jitter shaping is carried out by advancing the output signal from the DCO Overflow counter whenever there is an overflow of the Jitter Shaping Accumulator  22 . The DCO Overflow Counter output signal ‘low_freq_ovf’ is actually a bit in the counter that has the desired output clock frequency. 
         [0034]    Having in mind that advancement is not possible in a circuit without a feedback loop, the Overflow counter signal (‘low_freq_ovf’) is additionally delayed for two master clock cycles by flip flops  23 ,  24 . The most delayed signal (‘low_freq_ovf_del3’) is used when no advancement is necessary, and the signal that is delayed for one master clock cycle less (‘low_freq_ovf_del2’) is used when advancement needs to happen. This is achieved by passing the third flip flop  25  with the aid of multiplexer  26   
         [0035]    The jitter shaping process can be interpreted such that an advancement operation is required whenever the total (accumulated) difference between the output clock edge, when jitter shaping is not used, and an ideal edge position of that particular frequency clock reaches one master clock cycle. 
         [0036]    The same Jitter Shaping Accumulator ‘js_overflow’ signal is used to select the error that is accumulated. Basically, when there is no adjustment (the Jitter Shaping Accumulator ‘js_overflow’ signal is low) the error representing the difference between the output clock edge and the ideal clock edge is equal to the DCO ‘remainder’. The DCO ‘remainder’ is the DCO phase value at the time of the DCO overflow. 
         [0037]    When the adjustment happens, the edge placement error is equal to the difference between the DCO ‘remainder’ value and the DCO ‘frequency’ value. The DCO ‘frequency’ is the value that is accumulated inside the DCO on every master clock cycle, so it represents one master clock cycle, while the DCO ‘remainder’ is a fraction of the master clock cycle, and is always less than or equal to the DCO ’frequency’. Therefore, when the adjustment happens, the error is always negative number or zero. 
         [0038]    Since the error is equal to the ‘remainder’ when there is no advancement, and the ‘frequency’ represents one master clock cycle, the error during advancement (when the Jitter Shaping Accumulator ‘js_overflow’ signal is high) must be represented as the difference between the two, because the advancement size is one master clock cycle. The Jitter Shaping Accumulator ‘js_overflow’ signal can also be seen as the feedback signal of the resulting advancement to the jitter shaping process, represented by the accumulator. 
         [0039]    When jitter shaping is turned off, the Jitter Shaping circuit simply delays the DCO Overflow Counter signal for a couple of clock cycles. This delay comes as result of already mentioned delaying of the DCO Overflow Counter signal in order to make advancing possible. 
         [0040]    The jittershaper according to the invention is more efficient since it is self contained using feedback information in the way that different value of phase error is being accumulated in the jittershaping accumulator depending on status of overflow of the accumulator (error is being either the DCO remainder or the DCO remainder minus DCO frequency). The DCO frequency value represents one master clock cycle phase in the output clock, while the DCO remainder represents fraction of the master clock period in the output clock phase, based on the ideal clock with the same frequency. 
         [0041]    When jittershaping happens (output clock edge advancement), the accumulation error is being changed to compensate for that one master clock in order to keep output frequency with no additional jitter being added. Every unnecessary additional jitter degrades output clock. 
         [0042]    The DCO in accordance with the invention can be part of a DPLL. This allows the DCO to suppress also components of jitter coming from the reference line to the DPLL.