Abstract:
A method and related apparatus for different lane and access port configurations of a bus. Such different configurations can apply to different applications requirements. In a preferred embodiment of the invention, a chipset can con figure 18  lanes to 4 access ports of a peripheral communication interconnect express bus for selectively 4 different configurations. A first configuration provides single access port with 16 lanes, and two access ports for each has one lane. A second configuration provides two access ports for each has eight lanes, and two access ports for each has single lane. A third configuration provides one access port with eight lanes, two access ports for each has four lanes and another one access port with single lane. And a fourth configuration provides four access ports for each has four lanes.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   (1) This is a Non-provisional of U.S. provisional application No. 60/522,771, filed Nov. 5, 2004. (2) This a Non-provisional of U.S. provisional application No. 60/522,812, filed Nov. 9, 2004. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method and apparatus for configuring a number of lanes to be connected to each access port of a bus, and more particularly, to a method and apparatus for realizing different lane configurations with an identical circuit design. 
   2. Description of the Prior Art 
   A computer system is one of the most important hardware devices in modern information society. As the computer system is widely used in various applications, different requirements of different applications are demanded. For example, a personal computer is often used to play multi-media video and audio, so the efficiency of network information transmission management is regarded, on the other hand, the efficiency of image signal processing is ignored. Therefore, how to satisfy various requirements of different applications in the computer system is becoming more important. 
   In general, a computer system includes: a central processing unit, a system memory for providing memory resources, a chipset, and various peripheral devices/circuits. The central processing unit executes programs, processes data and handles the computer functions. The system memory can be a dynamic random access memory. The peripheral devices/circuits includes: a display card with capable of accelerating an image processing efficiency, a network card with able to be connected to a network for manipulating network data transmission, and a variety of input/output interfaces and nonvolatile storage devices. The chipset is connected between the central processing unit, the system memory, and the peripheral devices/circuits for coordinating and managing data transmission among these devices. 
   In order to manage the data transmission, the chipset is connected to the peripheral devices/circuits via a bus, so that each peripheral device/circuit can access the central processing unit and the system memory via the bus and the chipset. 
   In order to improve the efficiency for each peripheral device/circuit to access the data from the bus, a modern bus standard is designed to realize a scalable data transmission bandwidth (total data flew in a unit period). For example, in a new generation peripheral communication interconnect-express (PCIE) standard, the chipset is connected to a peripheral device via a bus of an access port. The bus of different access ports may have different numbers of physical signal transmission lanes. Access ports with different numbers of lanes can serve different bandwidths to a corresponding peripheral device. For example, there have an access port A with a lane and an access port B with two lanes. Since any two lanes have equal data transmission bandwidths, the access port B can transmit data by the two lanes at the same time. That is, data transmission bandwidth of access port B is twice of the data transmission bandwidth of the access port A. Likewise, an access port with four lanes can transmit data over four times (×4) data transmission bandwidth; and an access port with eight lanes can transmit data over a eight times (×8) data transmission bandwidth; and an access port with sixteen lanes can transmit data over a sixteen times (×16) data transmission bandwidth. 
   In a conventional chipset, the access port configured to a fixed numbers of lanes. For example, a conventional chipset provides an access port with 16 lanes, and one or two access ports with single lane. The access port with 16 lanes is used to connect to a display card, so that the chipset can use 16 times data transmission bandwidth to transmit data to improve the image processing efficiency of the computer system. However, as mentioned previously, many applications do not need to ultimate image processing efficiency. Instead, in some applications, four or eight times data transmission bandwidth is needed to serve the other kinds of peripheral devices. For example, a computer system being as a server needs more than one access port with 4 lanes to manage its network peripheral devices. That is to say, since the conventional chipset has fixed numbers of lanes, the access port can neither provide various data transmission bandwidths applied in different applications, nor meet the requirements of different computer systems in different applications. 
   SUMMARY OF THE INVENTION 
   The invention provides a method and related apparatus to overcome the above-mentioned problems. 
   The present invention provides an apparatus for configuring lanes to an access port, the apparatus includes: a plurality of lanes for transmitting data; a plurality of access modules; and a configuration module coupled to the lanes and the access modules, determining a number of lanes for each access modules; wherein the configuration module receives a setting signal and configuring each lanes to one of the access modules or to none of the access modules. 
   The present invention also provides a method for configuring M lanes to N access modules, said access module couples to an access port for connecting to an external peripheral device, the method includes: configuring said lane to one or none of the N access modules according to a setting signal. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a functional block diagram of an embodiment according to the present invention. 
       FIG. 2  to  FIG. 5  are four schematic diagrams showing a variety of lane configurations realized by a chipset connected to a variety of access ports shown in  FIG. 1 . 
       FIG. 6  is a table listing the access ports configured to the lanes under different configuration shown in  FIG. 2  to  FIG. 5 . 
       FIG. 7  is another table listing the access port configuration supported by the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 1 , which is a functional block diagram of an embodiment of a computer system  10  according to the present invention. The computer system  10  includes a central processing unit  12 , a memory  14 , a chipset  16 , and a plurality of peripheral devices/circuits (ex. P 0 ˜P 3  as shown in  FIG. 1 ). 
   The central processing unit  12  is used for processing data, and executing programs to control the computer system  10 . As a system memory of the computer system  10 , the memory  14  can be a dynamic random access memory, which provides the memory resources for the computer system  10 . For example, the memory  14  stores the programs and data for the central processing unit  12  operating. The peripheral devices P 0  to P 3  can include a variety of add-on cards and circuits, such as a network card used to connect the computer system  10  to a network, a display card or a sound card used to accelerate image and audio processing efficiency, or an interface card for a storage device, such as hard disk array control card for managing hard disk array. The chipset  16 , regarding as a bus management circuit, coordinates data transmission between the peripheral devices and the central processing unit  12  and the memory  14 . 
   The chipset  16  includes a control module  18 , a plurality of access modules (ex. four access modules  22 A to  22 D as shown in  FIG. 1 ), and a plurality of input/output circuit  30  which form a plurality of lanes, so that the chipset  16  can communicate with the peripheral devices. 
   As shown in  FIG. 1 , the chipset  16  haves 18 lanes L 00 ˜L 17 . The control module  18  accesses the central processing unit  12  and the memory  14  to exchange data with the central processing unit  12  and the memory  14 . Each of the access modules  22 A to  22 D is used to serve one corresponding peripheral device. When an access module connects to a peripheral device via one or a plurality of lanes, the access module can help data exchanging via the control module  18  between peripheral device and the central processing unit  12  and the memory  14 . 
   Besides the access modules and lanes/input/output circuits, in order to realize a bus configuration management mechanism of the present invention, the chipset  16  in the present invention further includes a configuration module  20  coupled between the access ports  22 A˜ 22 D and the input/output circuits  30 . The configuration module  20  would receive a setting signal. According to the setting signal, the configuration module  20  assigns lanes to each access ports  22 A˜ 22 D with connected to the peripheral devices P 0 ˜P 3 . That is, according to the setting signal, the configuration module  20  assigns numbers of lanes to each access ports  22 A˜ 22 D. More numbers of lanes are assigned to an access port wider data transmission bandwidth is served to the corresponding peripheral device. 
   The embodiment shown in  FIG. 1 , the configuration module  20  includes multiplexing modules  24 A˜ 24 C,  26  and  28 . The multiplexing module  24 A assigns the lanes L 04 ˜L 07  to either the access port PE 0  or the access port PE 1  (that is, either to the access module  22 A or to the access module  22 B) according to the setting signal. The multiplexing module  24 B assigns the lanes L 08 ˜L 11  to either the access port PE 0  or the access port PE 2  according to the setting signal. The multiplexing module  24 C assigns the lanes L 12 ˜L 15  to the access ports PE 0 , PE 2 , or PE 3  according to the setting signal. The multiplexing module  26  assigns the lane L 16  to the access port PE 1  or not according to the setting signal. The multiplexing module  28  assigns the lane L 17  to the access port PE 3  or not according to the setting signal. 
   Please refer to  FIG. 2  to  FIG. 5  for more detail showing lane configuring conditions in the present invention. 
   As shown in  FIG. 2 , if the setting signal complies with a configuration A (as shown in  FIG. 6 ), the multiplexing module  24 A assigns the lanes L 04 ˜L 07  to the access port PE 0 , instead of assigning to the access port PE 1 ; the multiplexing module  24 B assigns the lanes L 08 ˜L 11  to be the access port PE 0 , instead of assigning the access port PE; the multiplexing module  24 C assigns the lanes L 12 ˜L 15  to the access port PE 0  instead of assigning to the access port PE 2  or the access port PE 3 ; the multiplexing module  26  assigns the lane L 16  to the access port PE 1 ; and the multiplexing module  28  assigns the lane L 17  to the access port PE 3 . Therefore, the access port PE 0  has 16 connected lanes (lanes L 00  to L 15 ), and can provides 16 times data transmission bandwidth by those 16 lanes to serve the peripheral device P 0 . Furthermore, the access ports PE 1  and PE 3  with single lane can respectively serve single data transmission bandwidth to the peripheral devices P 1  and P 2 . In the embodiment, under the configuration A, the access module  22 C is configured to none of the lanes, so the access port PE 2  is idle. 
   In  FIG. 3 , if a setting signal complies with a configuration B (as shown in  FIG. 6 ), the multiplexing module  24 A assigns the lanes L 04 ˜L 07  to the access port PE 0 ; the multiplexing module  24 B assigns the lanes L 08 ˜L 11  to the access port PE 2 ; the multiplexing module  24 C assigns the lanes L 12 ˜L 15  to the access port PE 2 ; the multiplexing module  26  assigns the lane L 16  to the access port PE 1 ; and the multiplexing module  28  assigns the lane L 17  to the access port PE 3 . That is, under configuration B, the access port PE 0  and the access port PE 1  are configured to eight lanes, so that, the access port PE 0  and the access port PE 2  can serve 8 times data transmission bandwidth for the peripheral devices P 0  and P 1 . Furthermore, access port PE 1  and the access port PE 3  can serve single data transmission bandwidth for the peripheral devices P 2  and P 3 . In some applications, a computer system can use two display cards with eight times data transmission bandwidth to accelerate the video/audio processing efficiency. The configuration B shown in  FIG. 3  can support two eight-lane access ports, and is useful for such computer system as mentioned above. 
   In  FIG. 4 , a setting signal complies with a configuration C (as shown in  FIG. 6 ), the multiplexing module  24 A assigns the lanes L 04 ˜L 07  to the access port PE 0 ; the multiplexing module  24 B assigns the lanes L 08 ˜L 11  to the access port PE 2 ; the multiplexing module  24 C assigns the lanes L 12 ˜L 15  to the access port PE 3 ; the multiplexing module  26  assigns the lane L 16  to the access port PE 1 ; and the multiplexing module  28  assigns the lane L 17  to none of the access ports (idle). Under the configuration C, the chipset  16  of the embodiment provides the access port PE 0  with eight lanes, the access ports PE 1  and PE 2  for each has four lanes, and the access port PE 1  with single lane. As a result, the chipset  16  supports eight times data transmission bandwidth for the peripheral device P 0 , four times data transmission bandwidth for the peripheral devices P 1  and P 2  respectively, single data transmission bandwidth for the peripheral device P 3 . 
   In  FIG. 5 , a setting signal complies with a configuration D (as shown in  FIG. 6 ), the multiplexing module  24 A assigns the lanes L 04 ˜L 07  to the access port PE 1 ; the multiplexing module  24 B assigns the lanes L 08 ˜L 11  to the access port PE 2 ; the multiplexing module  24 C assigns the lanes L 12 ˜L 15  to the access port PE 3 ; the multiplexing module  26  assigns the lane L 16  to be idle (assigns L 16  to none of the access ports); and the multiplexing module  28  assigns the lane L 17  to be idle (assigns L 17  to none of the access ports). Under the configuration D, the chipset  16  of the embodiment provides the access ports PE 0 , PE 1 , PE 2  and PE 3  for each has four lanes, respectively serving four times data transmission bandwidth for each corresponding peripheral device P 0 , P 1 , P 2  and P 3 . 
   When a computer system applied in server, the computer system should include multiple access ports of four times data transmission bandwidth to support various network peripheral devices. The configuration D shown in  FIG. 5  can be applied to the computer system. 
     FIG. 6  and  FIG. 7  summarize the bus configurations of the chipset  16  shown in  FIG. 1 .  FIG. 6  lists configurations of the lanes assigned to access ports.  FIG. 7  lists the access port configurations supported by the present invention. 
   As shown in  FIG. 6  and  FIG. 7 , under the configuration A, the lanes L 00 ˜L 15  are assigned to the access port PE 0 , the lane L 16  is assigned to the access port PE 1 , and the lane L 17  is assigned to the access port PE 3 ; in such case, one access port with 16 lanes, and two access port for each has single lanes are provided (the access port PE 2  is idle). Under the configuration B, the lanes L 00 ˜L 07  are assigned to the access port PE 0 , the lanes L 08 ˜L 15  are assigned to the access port PE 2 , the lane L 16  is assigned to the access port PE 1 , and the lane L 17  is assigned to the access port PE; in such case, two access ports for each has eight lanes and another two access ports for each has single lane are provided. Under the configuration C, the lanes L 00 ˜L 07  are assigned to the access port PE 0 , the lanes L 08 ˜L 11  are assigned to the access port PE 2 , the lanes L 12 ˜L 15  are assigned to the access port PE 3 , the lane L 16  is assigned to the access port PE 1 , and the lane L 17  is idle; in such case, one access port with eight lanes, two access port for each has four lanes, and one access port with single lane are provided. Under the configuration D, the lanes L 00 ˜L 03 , L 04 ˜L 07 , L 08 ˜L 11 , and L 12 ˜L 15  are respectively assigned to the access ports PE 0 , PE 1 , PE 2  and PE 3  (wherein the lanes L 16  and L 17  are idle); in such case, four access ports for each has four lanes are provided. 
   Furthermore, the chipset  16  of the present invention still has another configuration C′. Under the configuration C′, the lanes L 00 ˜L 03  and L 04 ˜L 07  are assigned to the access ports PE 0  and PE 1  respectively, the lanes L 08 ˜L 15  are assigned to the access port PE 2 , and the lane L 17  is assigned to the access port PE 3  (wherein the lane L 16  is idle). Similar to the configuration C, the configuration C′ also provides one access port with eight lanes, two access ports for each has four lanes, and one access port with single lane. 
   As shown in  FIG. 6 , lanes assigning are seriously considerate in embodiments of the present invention. Thus, designs of multiplexing module and configuration module can be simplified; further gate counts of the configuration module can be reduced. 
   Otherwise, there is another embodiment for setting an independent multiplexing module on each lane. In this embodiment, each lane can be directly assigned to one of the access ports independently. Although such design makes more various configurations of the lanes and the access ports, the more complicated circuit layout and more gate counts are needed. In comparison with other embodiments of the present invention mentioned above,  FIG. 6  shows the preferred design, which not only be used to assemble a variety of practical configurations, but also simplify the circuit of the configuration module. For example, it can be seen from  FIG. 6  that the lanes L 00 ˜L 03  are always configured to the access port PE 0  under all configurations A, B, C (or C′) and D, so that, there has no multiplexing module setting on the lanes L 00 ˜L 03 . The lanes L 04 ˜L 07  are assigned to either the access port PE 0  or the access port PE 1 . This can simplify the design of the multiplexing module  24 A (shown in  FIG. 1 ). Basically, the present invention groups each four lanes as a set, and installs four changeable lane sets and one or more than one independently changeable lane (such as the lane L 16 , L 17  shown in  FIG. 1 ) on the chipset  16  to assemble a variety of configurations of practical value. 
   In practice, the chipset  16  of the present invention can set pins for receiving the setting signals. By using a jumper mounted onto these pins, the configuration module can be controlled to perform any configuration. 
   For example, a motherboard manufacturer can mount the jumper onto specific pins to implement the configuration B (as shown in  FIG. 3 ). That is, the configuration module  20  is set to the configuration B by the setting signal to perform appropriate switching functions. 
   In summary, the chipset of the present invention can includes N access ports (access modules) and M lanes with able to be connected to peripheral devices, and the configurations between the access ports and the lanes can be switched. That is, each access port is configured to have different numbers of lanes under different configurations. In contrast to the prior art, which adopts a fixed configuration of access ports and lanes, the present invention has different configurations of access ports with the same circuit design which can satisfy different requirements of a variety of computer systems. In addition to being applied to the chipset, the present invention can be applied to a switch of a bus. For example, according to the PCIE standard, a switch (or a fabric) supports an upstream access port and a plurality of downstream access ports. The upstream access port can be connected to an access port of the chipset, and the downstream access ports can be connected to a variety of peripheral devices to enable the peripheral devices to share an identical access port of the chipset. When designing such a switch, a designer can use the merits of the present invention to have different configurations of downstream access ports. In the present invention, the functions of the modules can be realized by hardware and firmware. For example, the multiplexing module can be realized by a plurality of multiplexers. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.