Abstract:
A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.

Description:
This application claims the benefit of Taiwan application Serial No. 092124694, filed Sep. 8, 2003, the subject matter of which is incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates in general to a method for checking an IC layout, and more particularly to a method for checking a wire layout causing high power wire resistance in the IC layout. 
   2. Description of the Related Art 
     FIG. 1  is a partially equivalent circuit diagram showing a conventional integrated circuit (IC). Referring to  FIG. 1 , the equivalent circuit  10  includes a voltage source  11 , a plurality of equivalent wire resistors R 11 , R 12 , R 13 , R 21 , R 22  and R 23 , and a plurality of device units  12 ,  13  and  14 . Theoretically, the equivalent resistance of an ideal wire is zero in the circuit property. In fact, however, each wire has an equivalent resistance. If the electric currents flowing through the device units  12 ,  13  and  14  are I 1 , I 2  and I 3 , respectively, because the equivalent wire resistors R 11 , R 12  and R 13  cause voltage drops and the equivalent wire resistors R 21 , R 22  and R 23  cause ground bounces, the voltages V G3  and V′ G3  are represented in the following equations according to the ohm&#39;s law:
   V   G3   =V−R   11 ( I   1   +I   2   +I   3 ) −R 12 ( I   2   +I   3 )− R   13   *I   3   (1), and   V′   G3   =R   21 ( I   1   +I   2   +I   3 ) + R   22 ( I   2   +I   3 )+ R   23   *I   3   (2). 
   Thus, the operation voltage (the voltage drop across two ends) of the device unit  14  is not the ideal, voltage (VDD-GND), but is (V G3 −V′ G3 ), which is dropped by (R 21 +R 11 )(I 1 +I 2 +I 3 )+(R 22 +R 12 ) (I 2 +I 3 )+(R 23 +R 13 )*I 3 . Hence, the larger the equivalent wire resistance is, the larger the voltage drop is. The large equivalent wire resistance may cause the timing problems&#39; and the functional failures of the device unit. The above-mentioned problem becomes serious when the IC manufacturing technology is getting more and more advanced such that the line width is getting smaller and smaller, and the wire&#39;s equivalent resistance is getting larger and larger. Thus, the difference between the actual operation voltage of the device and the ideal operation voltage thereof is getting larger and larger. 
   Consequently, it is an important subject of the circuit layout to effectively reduce the wire&#39;s resistance. 
   However, When the IC layout is done according to the currently used IC CAD (computer aided design) software, there are no known objective and effective rules and methods to judge whether or not the circuit layout causes the wire resistance too high. Instead, the circuit layout engineer can only check the complicated circuit layout with his/her naked eyes according to his/her experience for the subjective assertion. Thus, the prior art method is time-consuming, laborious, inefficient, and ineffective. 
   SUMMARY OF THE INVENTION 
   It is therefore an object of the invention to provide a method for checking an IC layout so as to check out the missed connection region, the region having insufficient via area, and the region of too-narrow wire width, which will cause the high wire resistance in the circuit layout. Thus, the layout engineer can modify the design according to the checking result so as to reduce the power source&#39;s voltage drop. 
   The invention achieves the above-identified object by providing a method for checking an IC layout. The IC includes at least a first metal layer having at least a wire, and the wire has a number of wire segments. The method includes the steps of: checking each wire segment, and if at least a narrow wire segment has a width smaller than a predetermined width, removing the narrow wire segment; and if at least a non-coupling wire segment is not coupled to a voltage source, outputting the non-coupling wire segment, so as to dispose a coupling wire to couple the non-coupling wire segment and the voltage source. 
   Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a partially equivalent circuit diagram showing a conventional integrated circuit (IC). 
       FIG. 2A  shows a layout having three metal layers. 
       FIG. 2B  shows another layout, which has lower equivalent resistance of the wire compared to that of the layout shown in  FIG. 2A . 
       FIG. 3A  shows a layout that is well designed and includes the power supply layers M i+3  and M i+1 , and a signal layer M i+2 . 
       FIG. 3B  shows the output region after the process of checking the overlapped region of the power layers in the layout of  FIG. 3A . 
       FIG. 4A  shows the protected and overlapped layout of the upper and lower metal layers M i  and M i+1 , which are conducted by vias. 
       FIG. 4B  shows the layout with one more via compared to that of  FIG. 4A . 
       FIG. 5A  shows the projected and overlapped layout of the upper and lower metal layers M i  and M i+1 , which are conducted by vias. 
       FIG. 5B  shows the region of the vials in the layout of  FIG. 5A . 
       FIG. 5C  shows the projected and overlapped region of the metal layers in the layout of  FIG. 5A . 
       FIG. 6A  shows the layout of one metal layer. 
       FIG. 6B  shows another layout of one metal layer with a wider wire compared to that of  FIG. 6A . 
       FIG. 7A  shows the layout to be checked. 
       FIG. 7B  shows the layout after checking the wire line width. 
       FIGS. 8A and 8B  are network diagrams of the metal wires illustrated according to  FIG. 7B . 
       FIG. 9  shows the steps of the method for checking the IC layout according to an embodiment of in the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The method for checking an IC layout according to the embodiments of the invention will be described with reference to the accompanying drawings. The layout polygon checking method of the invention includes, steps of checking a projected and overlapped region of power layers, checking an area ratio of a via area, and checking the wire line width. The invention performs the checks according to a graphic design system file (GDS file) and a rule file and outputs a file that may be understood by the user. 
     FIG. 2A  shows a layout having three metal layers comprising an upper metal layer M i+3 , a lower metal layer M i+1 , and a wire region of the middle metal layer M i+2 . Of course, an insulation layer is interposed between two adjacent layers. ΔV 2A  is the voltage difference from a point in the metal layer M i+3  or M i+1  to the positive or negative terminal of the voltage source.  FIG. 2B  shows another layout having three metal layers comprising an upper metal layer M i+3 , a lower metal layer M i+1 , and a wire region of the middle metal layer M i+2 . Of course, an insulation layer is interposed between two adjacent layers. ΔV 2B  is the voltage difference from a point in the layer M i+3  or M i+1  to the positive or negative terminal of the voltage source. The layout of  FIG. 2B  is almost the same as that of  FIG. 2A  except for the metal layer  21  added to the middle layer M i+2  exclusive of the wire region of  FIG. 2B . Thus, if the upper and lower metal layers are conducted by vias through the metal layer  21 , ΔV 2B  is smaller than ΔV 2A  because the metal layer  21  helps to conducts the two layers to reduce the wire&#39;s equivalent resistance. In other words, as long as positions in the middle layer with no wire are checked, one or more additional conductive metal layers  21  may be added to these positions and help to conduct the upper and lower metal layers M i+3  and M i+1  through vias, so that the power source&#39;s voltage drop caused by the wire&#39;s equivalent resistance can be effectively reduced. 
   The method for checking the overlapped region of the power layers according to an embodiment of the invention will be described in  FIG. 3 .  FIG. 3A  shows a circuit layout that is well designed and includes the power supply layers of an upper metal layer M i+3  and a lower metal layer M i+1 , and a wire regions of a middle layer M i+2 . Of course, an insulation layer is interposed between two adjacent layers. As shown in  FIG. 3A , the signal layer M i+2  has two wire regions  31  and  32 . The method of the invention for checking the overlapped region of the power layers is to search the overlapped region of the upper and lower layers M i+3  and M i+1  without the wire regions  31  and  32  disposed between the upper and lower layers M i+3  and M i+1 . That is,
 
(M i+1 ∩M i+3 !(31 and 32 of M i+2 ))  (3).
 
   It is possible to search the total overlapped region of the upper metal layer M i+3  and the lower metal layer M i+1 , and then filter out the wire regions  31  or  32  of the middle layer M i+2 .  FIG. 3B  shows the regions  33 ,  34  and  35 , which are outputted after checking the layout shown in  FIG. 3A . Of course, the wires to be checked in the upper metal layer M i+3  and the lower metal layer M i+1  are power lines. Since it&#39;s not necessary to output the overlapped region with small area, the CAD software may set an adjustable threshold area and output the region having an area larger than the threshold area after comparing the area of each overlapped region to the area threshold value. The layout engineer may refer to the region marked by the CAD software to modify the original circuit layout, such as adding a conductive metal layer in the region marked by the CAD software in the middle layer M i+2 , and providing vias between the metal layer and the upper metal layer M i+3  and between the metal layer and the lower metal layer M i+1 . Thus, the wire&#39;s equivalent resistance causing the power source&#39;s voltage drop can be reduced. 
     FIG. 4A  shows the layout, wherein the upper and lower metal layers M i  and M i+1  are overlapped and conducted by vias. As shown in this drawing, the metal layer M i  is conducted to the metal layer M i+1  by the vias  41 ,  42  and  43 , and the equivalent wire resistance between the metal layers M i  and M i+1  is defined as R i,i+1 .  FIG. 4B  shows the layout similar to  FIG. 4A , wherein the upper and lower metal layers M i  and M i+1  are overlapped and conducted using vias. As shown in this drawing, the metal layer M i  is conducted to the metal layer M i+1  by the vias  41 ,  42 ,  43  and  44 , and the equivalent wire resistance between the metal layers M i  and M i+1  are defined as R′ i,i+1 . Because the circuit layout in  FIG. 4B  has one more via compared to the layout shown in  FIG. 4A , the equivalent resistance R′ i,i+1  is smaller than the equivalent resistance R i,i+1  according to the above-mentioned description. So, the method for checking the area ratio of the via area in the invention is used for checking a region with a smaller area ratio of the via area, so as to reduce the equivalent resistance by adding vias in this region and thus to reduce the voltage drop. 
   The method for checking the ratio of the via area according to an embodiment of the invention will be described with reference to  FIG. 5 .  FIG. 5A  shows the layout; wherein the upper and lower metal layers M i  and M i+1  are overlapped and conducted by vias  51 ,  52 ,  53  and  54 . The method for checking the ratio of the via area is to search the overlapped region of the metal layers M i  and M i+1  such as the overlapped region  57  shown in  FIG. 5C , wherein the overlapped region  57  excludes the region overlapped the metal slots  55  and  56  and the area of the overlapped region  57  is calculated as A over . Next, the vias in the overlapped region,  57  are found as shown in  FIG. 5B , and the area of the vias  51 ,  52 ,  53  and  54  are calculated as A via . Then, the area ratio R A  is calculated by:
 
 R   A   =A   via   /A   over   (4).
 
   Since the region having large area ratio R A  is not necessary to be output; a threshold value is set in advance and the CAD software can mark and output the overlapped region having an area ratio R A  smaller than the threshold value. So, the layout engineer may increase the number of the vias in the output region, so as to reduce the equivalent wire resistance and thus reduce the voltage drop induced by the equivalent wire resistance. 
     FIG. 6A  shows the layout of one metal layer. As shown in this drawing, the metal layer M i  includes a contact pad  61  and wires  62 ,  63  and  64 .  FIG. 6B  shows another layout of one metal layer. Referring to  FIG. 6B , the metal layer M i  includes a contact pad  61  and wires  62 ,  63 ′ and  64 . The layout  15 , of  FIG. 6A  is almost the same as that of  FIG. 6B  except for the difference that the wire  63 ′ of  FIG. 6B  is wider than the wire  63  of  FIG. 6A . According to the resistor&#39;s law, the smaller the cross-sectional area, the larger the resistance. So, the equivalent resistance of the wire  63  in  FIG. 6A  is larger than that of the wire  63 ′ in  FIG. 6B . If the contact pad  61  is a power connection pad, the electric current flowing through the wire  63  will be relatively large because the wire  63  is quite close to the power connection pad  61 . Consequently, the voltage drop of the overall circuit is greatly influenced (increased) by the equivalent resistance of the wire  63 . Thus, the wire line width can be checked according to the present invention, so as to find out the wire with narrow line width. The layout engineer may correct the designed circuit layout diagram according to the checked result. 
     FIG. 7A  shows the layout to be checked and  FIG. 7B  shows the layout after checking the wire line width. Referring to  FIG. 7A , the layout includes a first layer of wires M 10 , M 11 , M 12  and M 13 , and a second layer of wires M 21 , M 22  and M 23 , wherein the wire M 10  has a voltage source connection pad  71  coupled to the voltage source, and the wire M 22  is narrow. Referring to  FIG. 7B , the layout includes a first layer of wires M 10 , M 11 , M 12  and M 13 , and a second layer of wires M 21  and M 23 . Obviously, the  FIG. 7B  lacks the wire M 22  compared to  FIG. 7A . 
   The method for checking the wire line width in the embodiment of the invention comprise: reading the circuit layout diagram of the power metal layer as shown in  FIG. 7A , narrowing the wire line widths of all wires shown in  15 , the  FIG. 7A  according to a line width threshold value determined by the user, regaining the original wire line width of the wire whose line width isn&#39;t narrowed to zero previously. Consequently, the wire (e.g., M 21 ) having a line width larger than the line width threshold value recovers to have its original line width, and the wire (e.g., M 22 ) having a line width smaller than the line width threshold value is eliminated as shown, in  FIG. 7B . 
   Finally, a corresponding metal wire network diagram is created according to the checked circuit layout diagram as shown in  FIG. 7B , and each independent network in the drawing is further checked. If there is an independent network that does not contain the voltage source, the independent network is outputted as a problem network. 
     FIGS. 8A and 8B  are network diagrams of the metal wires in accordance with  FIG. 7B . In  FIGS. 8A and 8B , each node corresponds to one metal wire of  FIG. 7B , and two nodes are connected by a line segment if the nodes are coupled through a via. Hence, the circuit layout diagram of  FIG. 7B  may be illustrated as two independent networks of  FIGS. 8A and 8B . The independent network of  FIG. 8A  includes the wire Mao having the voltage source connection pad. Therefore, it means that the line width of the metal wire is all right in this independent network. In the independent network of  FIG. 8B , however, no wire has a voltage source connection pad coupled to the voltage source. Thus, it means that the line width of the metal wire coupled to the voltage source connection pad is too narrow. So, the non-coupling metal wires in  FIG. 8B  is marked and outputted, and the layout engineer may dispose a coupling wire to couple the non-coupling wires to the voltage source according to the output information. 
     FIG. 9  shows the steps, of the method for checking the circuit layout in the invention. First, a DRC (Design Rule Check) tool is used to dump the GDS file and the rule file. The DRC tool generates the necessary ASCII database. In the layout polygon check, the desired items, such as the power layers overlapped region checking, the via area ratio checking and the wire line width checking, may be checked according to the necessary ASCII database and the threshold value inputted by the user. Consequently, the associated data are then output. 
   While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.