Abstract:
There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.

Description:
FIELD OF INVENTION 
       [0001]    The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for manufacturing a semiconductor wafer. 
       BACKGROUND 
       [0002]    In semiconductor manufacturing process, semiconductor wafers, which serve as fundamental materials, will be contaminated by various factors such as metal impurities. Those contaminants will cause defects in chips made from the wafers, such that the chips may fail electrical tests. As a result, the yield of chips is reduced and thus the cost of manufacturing chips is increased. 
         [0003]    Metals tend to generate positive ions due to their active chemical property. Such positive ions may cause various problems such as increase in the leakage current, reduction of the life time of minority carriers, and the like. Furthermore, the metal ions may move across a device for a long time after electrical tests and transportation of the device, which may cause failure of devices. 
         [0004]    From this point of view, there is a need for a novel method for manufacturing a semiconductor wafer, by which it is possible to purify the semiconductor wafer, and especially to remove the metal impurities therein. 
       SUMMARY OF THE INVENTION 
       [0005]    An object of the present invention is to provide a method for manufacturing a semiconductor wafer, by which it is possible to remove or remove at least partially impurities in the wafer, especially metal impurities in the wafer. 
         [0006]    According to an aspect of the invention, there is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. 
         [0007]    With this configuration, the semiconductor-metal compound retrogradely melts so that liquid droplets are generated, and various metal elements (impurities) included in the wafer are absorbed into the liquid portion by means of the solid-liquid segregation for example. As a result, it is possible to manufacture wafers of a high purity. 
         [0008]    Preferably, the semiconductor material may comprise silicon, and the metals may comprise copper, nickel and iron elements. Therefore, the present invention can be easily applied to the conventional semiconductor processes. Further, the heating may be performed to a temperature above 1000° C. and lower than the melting portion of Si, and the cooling may be performed to a temperature below 900° C. 
         [0009]    The metals may be provided in various ways. For example, the metals may be provided by a metal layer formed on the wafer. Alternatively, the metals may be provided by a metal layer filled into a trench which is formed in the wafer, or the metals may provide by a metal layer filled into a trench which is formed in a hard mask formed on the wafer. The location of the trench may correspond to that of a Shallow Trench Isolation to be formed in the wafer. Alternatively, the metals may be provided to the wafer by ion implantation. The location of the implantation may correspond to that of a Shallow Trench Isolation to be formed in the wafer. 
         [0010]    Preferably, after the cooling, the method may further comprise: removing the mixture of the metals and the semiconductors and a portion of the wafer close to the surface of the wafer. Thus, the wafer of a high purity is left. 
         [0011]    Preferably, a portion of the wafer from a balance line to the surface of the wafer is removed, wherein the concentration of the metal elements above the balance line is greater than that in the wafer body. 
         [0012]    Preferably, the metals dissolve into the semiconductors of the wafer to be oversaturated. 
         [0013]    The present invention is applicable to various wafers such as Silicon on Insulator wafer, bulk silicon wafer, GaN wafer and GaAs wafer. 
         [0014]    According to embodiments of the present invention, the impurities, especially the metal impurities such as Cu, Ni and Fe, in the wafer can be absorbed out by means of the retrograde melting of the semiconductor (for example, Si)—metal (for example, Cu, Ni and Fe, or the like) compound, so that the wafer of a high purity is fabricated. The method according to the present invention is simple to be implemented, and is easy to be incorporated into the semiconductor manufacture processes. Further, it is possible to improve the yield of chips and thus reduce the manufacture cost by manufacturing wafers according to the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The above and other objects, features and advantages of the present invention will be more apparent from the following descriptions of embodiments of the present invention with reference to the drawings, wherein. 
           [0016]      FIGS. 1-5  are schematic diagrams showing structures obtained in various steps in a processing flow of manufacturing a wafer according to a first embodiment of the present invention respectively, wherein in each of the diagrams, Fig. (a) is a top down view, and Fig. (b) is a cross section view taken along line A-A′ in Fig. (a); 
           [0017]      FIGS. 6-11  are schematic diagrams showing structures obtained in various steps in a processing flow of manufacturing a wafer according to a second embodiment of the present invention, respectively, wherein in each of the diagrams, Fig. (a) is a top down view, and Fig. (b) is a cross section view taken along line A-A′ in Fig. (a); 
           [0018]      FIGS. 12-16  are schematic diagrams showing structures obtained in various steps in a processing flow of manufacturing a wafer according to a third embodiment of the present invention, respectively, wherein in each of the diagrams, Fig. (a) is a top down view, and Fig. (b) is a cross section view taken along line A-A′ in Fig. (a); and 
           [0019]      FIGS. 17-21  are schematic diagrams showing structures obtained in various steps in a processing flow of manufacturing a wafer according to a fourth embodiment of the present invention respectively, wherein in each of the diagrams, Fig. (a) is a top down view, and Fig. (b) is a cross section view taken along line A-A′ in Fig. (a). 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0020]    Hereinafter, the present invention is described with reference to embodiments shown in the attached drawings. However, it should be noted that those descriptions are just provided for illustrative purpose, rather than limiting the present invention. Further, in the following, descriptions of known structures and techniques are omitted so as not to obscure the concept of the present invention. 
         [0021]    In the drawings, various layer structures according to embodiments of the present invention are schematically shown. However, they are not drawn to scale, and some features may be enlarged while some features may be omitted for clarity. Shapes, sizes and relative locations of respective regions and layers shown in the drawings are just illustrative, and deviations therefrom may occur due to manufacture tolerances and technical limits. Those skilled in the art can also devise regions/layers of different shapes, sizes and relative locations as desired. 
         [0022]    The present invention is based on the following observation. Some semiconductor-metal compounds would have the so-called “retrograde melting” property, that is, transition from the solid phase to the liquid phase when being cooled from melted state. Examples of such semiconductor include silicon (Si) and/or germanium (Ge), and examples of such metal include copper (Cu), nickel (Ni) and/or iron (Fe). For example, a compound obtained by introducing at least one of Cu, Ni and Fe materials into Si (where Si has a melting point of about 1414° C.) will exhibit the “retrograde melting” property when being cooled (below about 900° C., for example), so that liquid droplets occur therein. When the liquid droplets occur due to retrograde melting, other metal impurities dissolved in Si tend to move into the liquid portion (which is called solid-liquid segregation). In other words, the liquid droplets generated within Si serve as a “vacuum cleaner” which absorbs the impurities. 
         [0023]    Hereinafter, methods for manufacturing a semiconductor wafer according to various embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the semiconductor material is exemplified by Si which is most commonly used in the semiconductor processes. Further, the metal material comprises at least one of Cu, Ni and Fe materials. However, it is to be noted that the present invention is not limited thereto. For example, the semiconductor material may comprise Ge, GaN, GaAs, or the like. And it is not necessary for the metal material to include all of Cu, Ni and Fe, which may comprise only some of them, or may comprise other metal materials, for example, transition metal elements which can exhibit, together with the semiconductor material, retrograde melting property. 
       First Embodiment 
       [0024]      FIGS. 1-5  are schematic diagrams showing structures obtained in various steps in a flow of manufacturing a wafer according to a first embodiment of the present invention, respectively, wherein in each of the diagrams, portion (a) is a top view, and portion (b) is a section view taken along line A-A′ in portion (a). 
         [0025]    As shown in  FIG. 1 , in the first embodiment, the processes in the method are performed on a prepared wafer  1001 . That is, the wafer has been subjected to various processes such as Shallow Trench Isolation (STI) formation, and thus it is possible to make various semiconductor devices thereon. The wafer  1001  may comprise various types such as Semiconductor on Insulator (SOI) wafer, bulk silicon wafer, GaN wafer, GaAs wafer, or the like. 
         [0026]    Next, as shown in  FIG. 2 , a metal layer  1002  is formed on a surface of the wafer  1001 . The metal layer  1002  may comprise at least one of Cu, Ni and Fe elements For example, the metal layer  1002  may comprise a mixture of at least one of Cu, Ni and Fe elements formed by multi-target sputtering, or a metal stack formed by sputtering multiple layers of metals sequentially. 
         [0027]    Then, the structure shown in  FIG. 2  is heated to a sufficiently high temperature (above 1000° C., for example) so that the metal material (Cu, Ni and Fe) of the metal layer  1002  may dissolve into the semiconductor material (Si) of the underlying wafer  1001 . Here, the heating temperature should be lower than the melting point of Si (about 1414° C.) so that Si may not melt. This procedure is shown in  FIG. 3 , where the dissolving of the metal elements into the wafer  1001  is indicated by the arrows shown in the figure. Therefore, in a portion  1001 ′ of the wafer  1001  close to the surface, a compound of Si and at least one of Cu, Ni and Fe elements is formed. 
         [0028]    Here, preferably, the dissolving of the metal material from the metal layer  1002  into the wafer  1001  becomes oversaturated due to the big amount of the metal. That is, the amount of the metal material dissolved into Si is more than that under stable conditions. 
         [0029]    Subsequently, as shown in  FIG. 4 , the whole structure is cooled down gradually, for example, below 900° C., so that retrograde melting occurs. Specifically, when the structure is cooled down below 900° C., liquid droplets may be generated in the wafer  1001  due to the retrograde melting of the compound containing Si, Cu, Ni and Fe, so that the portion  1001 ′ may transform from a solid state to a slurry-like mix of solid and liquid. As shown by arrows in  FIG. 4(   b ), impurities (metal elements) in the underlying portion of the wafer are absorbed into the liquid portion, and thus the wafer is purified. 
         [0030]    Of course, although most of the impurities are absorbed, a certain amount of impurities may still be distributed therein. The dashed line  1003  in  FIG. 4(   b ) shows a “balance line” above which the concentration of the metal elements is greater than that in the wafer body. The balance line may be measured on site, or may be obtained statistically by a plurality of tests made in advance. 
         [0031]    Finally, as shown in  FIG. 5 , the metal layer  1002  and the portion  1001 ′ including the compound of Si, Cu, Ni and Fe and having the metal elements absorbed therein are removed. Preferably, a portion of the wafer  1001  close to the surface is removed along the balance line  1003 . The removal may be performed by means of dry etching, Chemical Mechanical Polishing (CMP) or the like. 
         [0032]    Thus, the wafer  1001  shown in  FIG. 5  is completed. Most of the impurities in the wafer  1001  are absorbed due to the retrograde melting as described above, and thus the wafer is purified. 
       Second Embodiment 
       [0033]      FIGS. 6-11  are schematic diagrams showing structures obtained in various steps in a flow of manufacturing a wafer according to a second embodiment of the present invention, respectively, wherein in each of the diagrams, portion (a) is a top view, and portion (b) is a section view taken along line A-A′ in portion (a). 
         [0034]    As shown in  FIG. 6 , in the second embodiment, the processes in the method are performed on a wafer  2001 . In  FIG. 6 , two hard mask layers  2002  and  2003  are also formed on the wafer  2001 . For example, the first hard mask layer  2002  may comprise silicon oxide, and the second hard mask layer  2003  may comprise silicon nitride. 
         [0035]    Next, as shown in  FIG. 7 , shallow trenches  2004  are formed by etching into the hard mask layers  2002  and  2003 . The etching may be carried out by various means such as dry etching. 
         [0036]    The depth of the trenches into the wafer  2001  (as shown by an arrow in  FIG. 7(   b )) to may vary between 10 nm and 1000 nm. Sidewalls of the trenches are vertical. 
         [0037]    Then, as shown in  FIG. 8 , a metal layer  2005  is filled into the trenches  2004 . The metal layer  2005  may comprise at least one of Cu, Ni and Fe elements. The filling of the trench may be performed by means of deposition, for example. 
         [0038]    Next, the structure shown in  FIG. 8  is heated to a sufficiently high temperature (above 1000° C., for example) so that the metal elements (Cu, Ni and Fe) of the metal layer  2005  may dissolve into the silicon of the wafer  2001 . Here, the heating temperature should be lower than the melting point of the silicon (about 1414° C.) so that the silicon may not melt. This procedure is shown in  FIG. 9 , where arrows show the dissolving of the metal elements into the wafer  2001 . Therefore, in a portion of the wafer surrounding the trenches  2004 , a compound of Si, Cu, Ni and Fe is formed. 
         [0039]    Here, preferably, the dissolving of the metal material into the wafer  2001  becomes oversaturated due to the big amount of the metals in the metal layer  2005 . That is, the amount of the metal material dissolved into the silicon is more than that under stable conditions. 
         [0040]    Subsequently, as shown in  FIG. 10 , the whole structure is cooled down gradually, for example, below 900° C., so that retrograde melting occurs. Specifically, when the structure is cooled down below 900° C., the portion of the wafer  2001  including the compound of Si, Cu, Ni and Fe may transform from a solid state to a slurry-like mix of solid and liquid. As shown by arrows in  FIG. 10(   b ), impurities in the wafer are absorbed into the liquid portion, and thus the wafer is purified. 
         [0041]    Finally, as shown in  FIG. 11 , the hard mask layers  2002  and  2003 , and the metal layer  2005  are removed. The removal may be performed by means of dry etching, CMP or the like. 
         [0042]    Preferably, a portion of the wafer  1001  close to the surface is removed along a balance line. For example, the portion of the wafer above the balance line may be subjected to oxidation, for example, thermal oxidation, to form an oxide, which may be removed by means of etching or the like. 
         [0043]    Thus, the wafer  2001  shown in  FIG. 11  is completed. Most of the impurities in the wafer  2001  are absorbed due to the retrograde melting as described above, and thus the wafer is purified. 
         [0044]    Further, the process according to this embodiment is compatible with the STI process. Specifically, trenches  2006  may be formed in the wafer  2001 . For example, it is possible to form STIs by filling insulator materials (for example, silicon oxide) into the trenches  2006 . 
       Third Embodiment 
       [0045]      FIGS. 12-16  are schematic diagrams showing structures obtained in various steps in a flow of manufacturing a wafer according to a third embodiment of the present invention, respectively, wherein in each of the diagrams, portion (a) is a top down view, and portion (b) is a cross section view taken along line A-A′ in portion (a). 
         [0046]    As shown in  FIG. 12 , in the third embodiment, the processes in the method are performed to the wafer  3001 , like the second embodiment Likewise, two hard mask layers  3002  and  3003  are also formed on the wafer  3001 . For example, the first hard mask layer  3002  may comprise silicon oxide, and the second hard mask layer  3003  may comprise silicon nitride. 
         [0047]    Next, as shown in  FIG. 13 , openings  3004  are formed in the first and second hard mask layers  3002  and  3003 . For example, the openings  3004  may be formed corresponding to locations where STIs are designed to form. Here, unlike the second embodiment, the openings  3004  may not cut into the wafer  3001 . In this embodiment, the metal materials such as Cu, Ni and Fe may be introduced into the wafer  3001  by means of ion implantation, as shown by arrows in  FIG. 13(   b ), so that a portion  3005  containing Cu, Ni and Fe is formed in the wafer  3001 . The depth of the metal implantation may be adjusted by controlling the implantation energy. 
         [0048]    Then, the structure shown in  FIG. 13  is heated to a sufficiently high temperature (above 1000° C., for example) so that the metal elements (Cu, Ni and Fe) of the portion  3005  may dissolve into the silicon. Here, the heating temperature should be lower than the melting point of the silicon (about 1414° C.) such that the silicon may not melt. This procedure is shown in  FIG. 14 , where arrows show the dissolving of the metal elements into the silicon. Therefore, in a portion of the wafer  3001  surrounding the portion  3005 , a compound of Si, Cu, Ni and Fe is formed. 
         [0049]    Here, preferably, the dissolving of the metal material into the wafer  3001  becomes oversaturated due to the big amount of the metals. That is, the amount of the metal materials dissolved into the silicon is more than that under stable conditions. 
         [0050]    Subsequently, as shown in  FIG. 15 , the whole structure is cooled down gradually, for example, below 900° C., so that retrograde melting occurs. Specifically, when the structure is cooled down below 900° C., the portion of the wafer  3001  including the compound of Si, Cu, Ni and Fe may transit from a solid state to a slurry-like mix of solid and liquid. As shown by arrows in  FIG. 15(   b ), impurities in the wafer are absorbed into the liquid portion, and thus the wafer is purified. 
         [0051]    Finally, as shown in  FIG. 16 , the hard mask layers  3002  and  3003 , and the portion  3005  affected by ion implantation are removed. The removal may be performed by means of dry etching, CMP or the like. 
         [0052]    Preferably, a portion of the wafer close to the surface is removed along a balance line. For example, the portion of the wafer above the balance line may be subjected to oxidation, for example, thermal oxidation, to farm an oxide, which may be removed by means of etching or the like. 
         [0053]    Thus, the wafer  3001  shown in  FIG. 16  is completed. Most of the impurities in the wafer  3001  are absorbed due to the retrograde melting as described above, and thus the wafer is purified. Further, trenches  3006  are formed in the wafer  3001 . For example, STIs may be formed by filling insulator materials (for example, silicon oxide) into the trenches  3006 . 
       Fourth Embodiment 
       [0054]      FIGS. 17-21  are schematic diagrams showing structures obtained in various steps in a flow of manufacturing a wafer according to a fourth embodiment of the present invention, respectively, wherein in each of the diagrams, portion (a) is a top down view, and portion (b) is a cross section view taken along line A-A′ in portion (a). 
         [0055]    As shown in  FIG. 17 , in the fourth embodiment, the processes in the method are performed in a wafer  4001 , like the third embodiment. Likewise, two hard mask layers  4002  and  4003  are also formed on the wafer  4001 . For example, the first hard mask layer  4002  may comprise silicon oxide, and the second hard mask layer  4003  may comprise silicon nitride. 
         [0056]    Next, as shown in  FIG. 18 , openings are formed in the first and second hard mask layers  4002  and  4003 . For example, the openings may be formed corresponding to locations where STIs are designed to form. Here, unlike the second embodiment, the openings may not cut into the wafer  4001 . In this embodiment, the openings are filled with a metal layer  4002  including at least one of Cu, Ni and Fe elements. The filling may be performed by means of deposition. 
         [0057]    Then, the structure shown in  FIG. 18  is heated to a sufficiently high temperature (above 1000° C., for example) so that the metal elements (Cu, Ni and Fe) of the metal layer  4004  may dissolve into the silicon of the wafer  4001 . Here, the heating temperature should be lower than the melting point of the silicon (about 1414° C.) so that the silicon may not melt. This procedure is shown in  FIG. 19 , where arrows show the dissolving of the metal elements into the wafer. Therefore, in a portion of the wafer  4005  adjacent to the metal layer  4004 , a compound of Si, Cu, Ni and Fe is formed. 
         [0058]    Here, preferably, the dissolving of the metal material into the wafer  4001  becomes oversaturated due to the big amount of the metals. That is, the amount of the metal material dissolved into the silicon is more than that under stable conditions. 
         [0059]    Subsequently, as shown in  FIG. 20 , the whole structure is cooled down gradually, for example, below 900° C., so that retrograde melting occurs. Specifically, when the structure is cooled down below 900° C., the portion  4005  of the wafer  4001  including the compound of Si, Cu, Ni and Fe may transform from a solid state to a slurry-like mix of solid and liquid. As shown by arrows in  FIG. 20(   b ), impurities in the wafer are absorbed into the liquid portion, and thus the wafer is purified. 
         [0060]    Finally, as shown in  FIG. 21 , the hard mask layers  4002  and  4003 , and the portion  4005  of the wafer having the impurities absorbed therein are removed. The removal may be performed by means of dry etching, CMP or the like. 
         [0061]    Preferably, a portion of the wafer close to the surface is removed along a balance line. For example, the portion of the wafer above the balance line may be subjected to oxidation, for example, thermal oxidation, to form an oxide, which may be removed by means of etching or the like. 
         [0062]    Thus, the wafer  4001  shown in  FIG. 21  is completed. Most of the impurities in the wafer  4001  are absorbed due to the retrograde melting as described above, and thus the wafer is purified. Further, trenches  4006  may be formed in the wafer  4001 . For example, STIs may be formed by filling insulator materials (for example, silicon oxide) into the trenches  4006 . 
         [0063]    According to the embodiments of the present invention, the metal materials such as Cu, Ni and Fe elements may dissolve into Si of the wafer by heating (above 1000° C., for example), so that a compound of Si and at least one of Cu, Ni and Fe elements is formed. Then, retrograde melting may occur to the formed compound when structure is gradually cooled down (below 900° C., for example) to form a slurry-like mix of solid and liquid, which absorbs the impurities from the wafer. As a result, the wafer is purified. 
         [0064]    In the above description, details of patterning and etching of the respective layers are not provided. It is to be understood by those skilled in the art that various means in the prior art may be utilized to form the layers and regions in desired shapes. Further, to achieve the same structure, those skilled can devise different methods from those described above. Although the respective embodiments are described above respectively, it does not necessarily mean that advantageous features of those embodiments cannot be used in combination. 
         [0065]    The present invention is described above with reference to the embodiments thereof. However, those embodiments are provided just for illustrative purpose, rather than limiting the present invention. The scope of the invention is defined by the attached claims as well as equivalents thereof. Those skilled in the art can make various alternations and modifications without departing from the scope of the invention, which all fall within the scope of the invention.