Abstract:
A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device including a plurality of input buffers to which internally-generated reference voltages are applied. 
     2. Description of the Related Art 
     Generally, in a semiconductor device, a plurality of input buffers are constructed by differential amplifiers for amplifying the difference between input voltages and respective reference voltages. Also, in order to decrease the number of external pads, the reference voltages are generated within the semiconductor device. In this case, the reference voltages are important parameters for determining whether the operation of the input buffers is normal or abnormal, i.e., whether the semiconductor device is normal or abnormal. Therefore, each of the input buffers monitors its reference voltage which is transmitted to an external pad in a test mode. This will be explained later in detail. 
     In the above-described prior art semiconductor device, however, the larger the number of input buffers, the larger the number of external pads for monitored reference voltages. For example, if the semiconductor device constitutes a processor, the number of input buffers is several hundreds. As a result, the semiconductor device including such input buffers would be increased in size. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor device having a plurality of input buffers with a reduced number of external pads. 
     According to the present invention, a semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal. 
     Thus, the reference voltage is transmitted by the control signal from the reference voltage generating circuit to the input voltage pads. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram illustrating a prior art semiconductor device; 
     FIG. 2 is a detailed circuit diagram of the input buffer of FIG. 1; 
     FIG. 3 is a block circuit diagram illustrating a first embodiment of the semiconductor device according to the present invention; 
     FIG. 4 is a detailed circuit diagram of the input buffer of FIG. 3; 
     FIGS. 5 and 6 are circuit diagrams illustrating modifications of the input buffer of FIG. 4; 
     FIG. 7 is a block circuit diagram illustrating a second embodiment of the semiconductor device according to the present invention; 
     FIG. 8 is a circuit diagram illustrating a modification of the input buffer of FIGS.  4  and  6 ; 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, a prior art semiconductor device will be explained with reference to FIGS. 1 and 2. 
     In FIG. 1, which illustrates a prior art semiconductor device, a plurality of input buffers such as input buffers  1 ,  2 , . . . ,  8  are provided. 
     For example, the input buffers  1 ,  2 ,  3  and  4  for the same interface receive input voltages IN 1 , IN 2 , IN 3  and IN 4 , respectively, so that the input voltages IN 1 , IN 2 , IN 3  and IN 4  are compared with a reference voltage V REFA  generated from a voltage divider by resistors R A1  and R A2 . Thus, the input buffers  1 ,  2 ,  3  and  4  generate output voltages OUT 1 , OUT 2 , OUT 3  and OUT 4  in accordance with differences between the input voltages IN 1 , IN 2 , IN 3  and IN 4  and the reference voltage V REFA . 
     Similarly, the input buffers  5 ,  6 ,  7  and  8  for the same interface receive input voltages IN 5 , IN 6 , IN 7  and IN 8  respectively, so that the input voltages IN 5 , IN 6 , IN 7  and IN 8  are compared with a reference voltage V REFB  generated from a voltage divider by resistors RB 1  and RB 2 . Thus, the input buffers  5 ,  6 ,  7  and  8  generate output voltages OUT 5 , OUT 6 , OUT 7  and OUT 8  in accordance with differences between the input voltages IN 5 , IN 6 , IN 7  and IN 8  and the reference voltage V REFB . 
     Since the reference voltages V REFA  and V REFB  are generated within the semiconductor device, each of the input buffers  1 ,  2 ,  3 ,  4 ,  5 ,  6 ,  7  and  8  monitors its reference voltage to generate a monitored reference voltage MV REFi  (i=1, 2, . . . , 8). Thus, in a test mode, it is possible for the internally-generated reference voltage V REFA  (or V REFB ) to be within a predetermined range. 
     In FIG. 2, which is a detailed circuit diagram of the input buffer i (=1, 2, . . . , 8) of FIG. 1, the input buffer i is constructed by N-channel MOS transistors Q 1  and Q 2  forming a current mirror circuit, P-channel MOS transistors Q 3  and Q 4  whose gates receive the input voltage IN i  and the reference voltage V REFA  (or V REFB ), respectively, and a P-channel MOS transistor Q 5  serving as a current source. Therefore, the input buffer i amplifies the difference between the input voltage IN i  and the reference voltage V REFA  (or V REFB ) to generate the output voltage OUT i  in response to this difference. For example, the input voltage IN i  of an emitter coupled logic (ECL) level whose amplitude is small is converted into the output voltage OUT i  of a CMOS level whose amplitude is large. 
     In FIGS. 1 and 2, however, the larger the number of input buffers, the larger the number of external pads for monitored reference voltages MV REF1 , MV REF2 , . . . . Therefore, a semiconductor device including such input buffers is increased in size. 
     In FIGS. 1 and 2, even if only the pads for the monitored reference voltages MV REF1  and MV REF5  are provided and the pads for the monitored reference voltage MV REF2 , MV REF3 , MV REF4 , MV REF6 , MV REF7  and MV REF8  are not provided, the reference voltages MV REFA  and MV REFB  can be monitored, In this case, however, the layouts of the input buffers  1 ,  2 , . . . ,  8  are not uniform. In view of a semiconductor design rule that the layouts of the input buffers are all the same, the above-mentioned configuration in which the input buffers  1  and  5  are different from the other input buffers is not preferable. 
     In FIG. 3, which illustrates a first embodiment of the semiconductor device according to the present invention, the input buffers  1 ,  2 ,  3 ,  4 ,  5 ,  6 ,  7  and  8  of FIG. 1 are replaced by input buffers  1 ′,  2 ′,  3 ′,  4 ′,  5 ′,  6 ′,  7 ′ and  8 ′, respectively, where the external pads for the monitored reference voltages MV REF1 , MV REF2 , MV REF3 , MV REF4 , MV REF5 , MV REF6 , MV REF7 , and MV REF8  of FIG. 1 are replaced by a single external pad for a control signal CNT. 
     In FIG. 4, which is a detailed circuit diagram of the input buffer i′ (i′=1, 2, . . . , 8) of FIG. 3, an N-channel MOS transistor Q 6  as a switch is added to the elements of the input buffer i of FIG.  2 . 
     In a normal operation mode, the control signal CNT is made low, so that the transistor Q 6  is turned OFF. Therefore, the input buffer i′ (i′=1, 2, . . . , 8) operates normally. 
     In a reference voltage monitoring mode, the control signal CNT is made high, so that the transistor Q 6  is turned ON. Therefore, the reference voltage V REFA (or V   REFB ) is transmitted to the pads for the input voltages IN 1 , IN 2 , . . . , IN 8 , thus monitoring the reference voltage V REFA  (or V REFB ). 
     In FIG. 5, which is a modification of the input buffer i′ (i′=1, 2, . . . , 8) of FIG. 4, a P-channel MOS transistor Q 7  as a switch is added to the elements of the input buffer i of FIG.  2 . 
     In a normal operation mode, the control signal CNT is made high, so that the transistor Q 7  is turned OFF. Therefore, the input buffer i′ (i′=1, 2, . . . , 8) operates normally. 
     In a reference voltage monitoring mode, the control signal CNT is made low, so that the transistor Q 7  is turned ON. Therefore, the reference voltage V REFA  (or V REFB ) is transmitted to the pads for the input voltages IN 1 , IN 2 , . . . , IN 8 , thus monitoring the reference voltage V REFA  (or V REFB ). 
     In FIG. 6, which is another modification of the input buffer i′ (i′=1, 2, . . . , 8) of FIG. 4, a transfer gate T formed by a P-channel MOS transistor and an N-channel MOS transistor as a switch is added to the elements of the input buffer i of FIG.  2 . 
     In a normal operation mode, the control signal CNT is made high, so that the transistor gate T is closed. Therefore, the input buffer i′ (i′=1, 2, . . . , 8) operates normally. 
     In a reference voltage monitoring mode, the control signal CNT is made low, so that the transistor gate T is opened. Therefore, the reference voltage V REFA  (or V REFB ) is transmitted to the pads for the input voltages IN 1 , IN 2 , . . . , IN 8 , thus monitoring the reference voltage V REFA  (or V REFB ). 
     The input buffer i′ of FIG. 6 is increased in size as compared with those of FIGS. 4 and 5; however, the input buffer i′ of FIG. 6 has an advantage in that the monitored range of the reference voltage V REFA  (or V REFB ) can be increased. 
     In FIG. 7, which illustrates a second embodiment of the semiconductor device according to the present invention, registers, i.e., D-type flip-flops  9  and  10  connected in series and a pad for a clock signal CK for the D-type flip-flops  9  and  10  are added to the elements of FIG.  3 . That is, the D-type flip-flops  9  and  10  store the control signal CNT in synchronization with the clock signal CK. 
     If “0” is stored in the D-type flip-flops  9  and  10 , the switches within the input buffers  1 ′,  2 ′,  3 ′,  4 ′,  5 ′,  6 ′,  7 ′ and  8 ′ are turned OFF, so that the input buffers  1 ′,  2 ′,  3 ′,  4 ′,  5 ′,  6 ′,  7 ′ and  8 ′ normally operate. 
     If “0” and “1” are stored in the D-type flip-flops  9  and  10 , respectively, the switches within the input buffers  1 ′,  2 ′,  3 ′ and  4 ′ are turned OFF, so that the input buffers  1 ′,  2 ′,  3 ′ and  4 ′ normally operate, while the switches within the input buffers  5 ′,  6 ′,  7 ′ and  8 ′ are turned ON, so that the reference voltage V REFB  is transmitted to the pads for the input voltages IN 5 , IN 6 , IN 7  and IN 8 , thus performing a reference voltage monitoring operation upon the reference voltage V REFB . 
     If “1” and “0” are stored in the D-type flip-flops  9  and  10 , respectively, the switches within the input buffers  1 ′,  2 ′,  3 ′ and  4 ′ are turned ON, so that the reference voltage V REFA  is transmitted to the pads for the input voltages IN 1 , IN 2 , IN 3  and IN 4 , thus performing a reference voltage monitoring operation upon the reference voltage V REFA , while the switches within the input buffers  5 ′,  6 ′,  7 ′ and  8 ′ are turned OFF, so that the input buffers  5 ′,  6 ′,  7 ′ and  8 ′ normally operate. 
     If “1” is stored in the D-type flip-flops  9  and  10 , the switches within the input buffers  1 ′,  2 ′,  3 ′,  4 ′,  5 ′,  6 ′,  7 ′ and  8 ′ are turned ON, so that the reference voltage V REFA  is transmitted to the pads for the input voltages IN 1 , IN 2 , IN 3  and IN 4 , thus performing a reference voltage monitoring operation upon the reference voltage V REFA  and simultaneously, the switches within the input buffers  5 ′,  6 ′,  7 ′ and  8 ′ are turned ON, so that the reference voltage V REFB  is transmitted to the pads for the input voltages IN 5 , IN 6 , IN 7  and IN 8  thus performing a reference voltage monitoring operation upon the reference voltage V REFB . 
     In FIGS. 3 and 7, the number of pads for monitored reference voltages is decreased as compared with that of FIG.  1 . 
     In the above-described embodiments, the transistors Q 1  and Q 2  can be of a P-channel type and the transistors Q 3 , Q 4  and Q 5  can be of an N-channel type, as illustrated in FIG. 8 which corresponds to FIG.  4 . Also, in FIG. 3, the voltage dividers can be constructed by a series of P-channel MOS transistors whose gates are connected to a high power supply voltage terminal or a series of N-channel MOS transistors whose gates are connected to a low power supply voltage terminal. 
     As explained hereinabove, according to the present invention, since the number of pads for monitoring internally-generated reference voltages is decreased, the semiconductor device can be decreased in size.