Abstract:
The general inventive concept relates to an organic light emitting display that has the same area where the upper and lower electrodes of a capacitor are overlapped for adjacent pixels, for respective pixels that constitute the organic light emitting display but implements the sizes of the upper and lower electrodes to be different. This thereby prevents the display quality of horizontal line shaped spot generated due to the effects of a critical dimension (CD) distribution from being degraded.

Description:
CLAIM OF PRIORITY 
       [0001]    This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application earlier filed in the Korean Intellectual Property Office on 30 Jul. 2009 and there duly assigned Serial No. 10-2009-0069926. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The general inventive concept relates to an organic light emitting display, and more particularly, to an organic light emitting display that prevents the display quality of horizontal line shaped spot generated due to the effects of a critical dimension (CD) distribution from being degraded. 
         [0004]    2. Description of the Related Art 
         [0005]    Recently, flat panel displays (FPD), which solve weight and volume disadvantages of the cathode ray tube (CRT), and have the advantages of being compact and lightweight, have been spotlighted. Among flat panel displays, there are liquid crystal displays (LCD), organic light emitting diode displays (OLED), field emitter displays (FED), plasma display panels (PDP), etc. 
         [0006]    Among other advantages, the organic light emitting display has advantages in that it has a wider use temperature range and is stronger against impact or vibration when compared to other flat panel displays. It also has a wide viewing angle and a rapid response speed which enable it to provide a clean moving image, and it has therefore been spotlighted as a next generation flat panel display. 
         [0007]    The organic light emitting display is a display using the phenomenon that when an electron and a hole injected into a thin film of an organic material through an anode and a cathode are recombined, they form an exciton, and light having a specific wavelength is generated from the exciton. The organic light emitting display as described above is constituted using self-light emitting elements, so that it does not require a separate light source in contrast to a liquid crystal display. The brightness of the organic light emitting elements that constitute the organic light emitting display are controlled by the amount of current flowing in the organic light emitting elements. 
         [0008]    Therefore, since the brightness of the organic light emitting display is controlled by the amount of current flowing in the organic light emitting elements, a more precise deposition process should be performed when forming the respective pixels. 
         [0009]    The respective pixels of the organic light emitting display are made by including various constituents such as a transistor, a capacitor, etc., wherein they are formed through a deposition process using a shadow mask or a fine metal mask (FMM). 
         [0010]    In this case, the capacity of the capacitor for each pixel may be different due to the critical dimension distribution which is generated as a result of the deposition process using the mask. 
         [0011]    For example, in the case of a capacitor formed on the scan line for each pixel region, a problem arises in that a horizontal line shaped spot is generated according to the CD distribution generated in forming the electrode of the capacitor. 
         [0012]    In order to reduce the effects of the CD distribution, there is a method to lower the tolerance of the mask, that is, to manufacture the mask more precisely, but this method is disadvantageous in view of considerably higher manufacturing costs. 
       SUMMARY OF THE INVENTION 
       [0013]    An embodiment of the invention provides an organic light emitting display that has the same area where the upper and lower electrodes of a capacitor are overlapped per adjacent pixels for respective pixels that constitute the organic light emitting display but implements the sizes of the upper and lower electrodes to be different, thereby preventing the display quality of horizontal line shaped spot generated due to the effects of a critical dimension (CD) distribution from being degraded. 
         [0014]    According to one aspect, there is provided an organic light emitting display that includes at least one capacitor for each pixel, including: a semiconductor layer that is formed on a substrate and serves as a lower electrode of the capacitor; a dielectric layer formed on the semiconductor layer; and a first electrode layer that serves as an upper electrode of the capacitor formed in the region on the dielectric layer overlapped with the semiconductor layer, wherein the width of the semiconductor layer and the width of the first electrode layer overlapped therewith are implemented to be different per adjacent pixels. 
         [0015]    Further, the adjacent pixels may be an odd pixel of the pixels arranged per respective scan line and an even pixel adjacent to the odd pixel, wherein in the capacitor provided in the even pixel, the width of the semiconductor layer is formed to be wider than the width of the first electrode, and in the capacitor provided in the odd pixel, the width of the first electrode is formed to be wider than the width of the semiconductor layer. 
         [0016]    Moreover, the first electrode layer may be coupled to the scan lines arranged in a row direction to be implemented in a form where a portion thereof is projected from the scan lines, and the capacitor may be a boosting capacitor Cb that is provided in each pixel. 
         [0017]    With the embodiment as described above, the organic light emitting display has the same area where the upper and lower electrodes of a capacitor are overlapped per adjacent pixels for respective pixels that constitute the organic light emitting display but implements the sizes of the upper and lower electrodes to be different. Therefore, the above described embodiment of the invention has the advantage of preventing the display quality of horizontal line shaped spot generated from being degraded due to the effects of a critical dimension (CD) distribution. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which like reference symbols indicate the same or similar components, wherein: 
           [0019]      FIG. 1  is a circuit view of each pixel of an organic light emitting display according to an embodiment of the present invention; 
           [0020]      FIG. 2  is a cross-sectional view showing capacitors formed in each pixel of  FIG. 1 ; and 
           [0021]      FIGS. 3A and 3B  are plan views of a boosting capacitor according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]    In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. In addition, when an element is referred to as being “on” another element, it can be directly on the other element or be indirectly on the other element with one or more intervening elements interposed in between. Also, when an element is referred to as being “connected to” another element, it can be directly connected to the other element or be indirectly connected to the other element with one or more intervening elements interposed in between. Hereinafter, like reference numerals refer to like elements. 
         [0023]    Hereinafter, exemplary embodiments according to the present invention will be described with reference to the accompanying drawings. 
         [0024]      FIG. 1  is a circuit view of each pixel of an organic light emitting display according to an embodiment of the present invention. 
         [0025]    However, the pixel circuit shown in  FIG. 1  is merely one embodiment of the invention. The pixel circuit provided in the organic light emitting display according to the embodiment shown in  FIG. 1  is not always limited thereto. 
         [0026]    Referring to  FIG. 1 , the pixels  140  according to an embodiment of the present invention include an organic light emitting diode OLED and a pixel circuit  142  that is coupled to a data line D, a scan line Sn, and a light emitting control line En to control the organic light emitting diode OLED. 
         [0027]    The anode electrode of the organic light emitting diode OLED is coupled to the pixel circuit  142  and the cathode electrode thereof is coupled to a second power supply ELVSS. The second power supply ELVSS is set to a voltage lower than that of a first power supply ELVDD. Such an organic light emitting diode OLED generates light having any one of red, green and blue corresponding to the amount of current supplied from the pixel circuit  142 . 
         [0028]    The pixel circuit  142  includes a storage capacitor Cst and a sixth transistor M 6  coupled between the first power supply ELVDD and an initialization power supply Vint, a fourth transistor M 4 , a first transistor M 1 , and a fifth transistor M 5  coupled between the first power supply ELVDD and the organic light emitting diode OLED, a third transistor M 3  coupled between the gate electrode and the second electrode of the first transistor M 1 , a second transistor M 2  coupled between the data line D and the first electrode of the first transistor M 1 , and a boosting capacitor Cb coupled between the gate electrode of the first transistor M 1  and the gate electrode of the second transistor M 2 . 
         [0029]    Herein, the first electrode is set to any one of the drain electrode and the source electrode, and the second electrode is set to an electrode other than the first electrode. For example, if the first electrode is set to the source electrode, the second electrode is set to the drain electrode. Furthermore, although the first to sixth transistors M 1  to M 6  are illustrated as P-type MOSFET&#39;s in  FIG. 1 , the embodiment is not limited thereto. If the first to sixth transistors M 1  to M 6  are N type MOSFET&#39;s, the polarity of the driving waveform is inversed as known to those skilled in the art. 
         [0030]    The first electrode of the first transistor M 1  is coupled to the first power supply ELVDD via the fourth transistor M 4 , and the second electrode thereof is coupled to the organic light emitting diode OLED via the fifth transistor M 5 . The gate electrode of the first transistor M 1  is coupled to a first node N 1 . Such a first transistor M 1  supplies the voltage charged in a storage capacitor Cst, that is, the current corresponding to the voltage applied to the first node N 1 , to the organic light emitting diode OLED. 
         [0031]    The first electrode of the third transistor M 3  is coupled to the second electrode of the first transistor M 1 , and the second electrode thereof is coupled to the gate electrode of the first transistor M 1 . And, the gate electrode of the third transistor M 3  is coupled to the s scan line Sn. When the scan signal is supplied to the n scan line Sn, such a third transistor M 3  is turned on to couple the first transistor M 1  in a diode form. In other words, when the third transistor M 3  is turned on, the first transistor M 1  is coupled in a diode form. 
         [0032]    The first electrode of the second transistor M 2  is coupled to the data line D, and the second electrode thereof is coupled to the first electrode of the first transistor M 1 . The gate electrode of the second transistor M 2  is coupled to the n scan line Sn. When the scan signal is supplied to the n scan line Sn, such a second transistor M 2  is turned on to supply the data signal supplied to the data line D to the first electrode of the first transistor M 1 . 
         [0033]    The first electrode of the fourth transistor M 4  is coupled to the first power supply ELVDD, and the second electrode thereof is coupled to the first electrode of the first transistor M 1 . The gate electrode of the fourth transistor M 4  is coupled to the light emitting control line En. When the light emitting control signal is not supplied (that is, when the low light emitting control signal is supplied), the fourth transistor M 4  is turned on to couple the first power supply ELVDD electrically to the first transistor M 1 . 
         [0034]    The first electrode of the fifth transistor M 5  is coupled to the first transistor M 1 , and the second electrode thereof is coupled to the organic light emitting diode OLED. The gate electrode of the fifth transistor M 5  is coupled to the light emitting control line En. When the light emitting control signal is not supplied (that is, when the low light emitting control signal is supplied), the fifth transistor M 5  is turned on to couple the first transistor electrically to the organic light emitting diode OLED. 
         [0035]    The first electrode of the sixth transistor M 6  is coupled to the storage capacitor Cst and the gate electrode of the first transistor M 1  (that is, the first node N 1 ), and the second electrode thereof is coupled to the initialization power supply Vint. The gate electrode of the sixth transistor M 6  is coupled to an n−1 scan line Sn−1. When the scan signal is supplied to the n−1 scan line Sn−1, the sixth transistor M 6  is turned on to initialize the first node N 1 . To this end, the voltage value of the initialization power supply Vint is set to be lower than the voltage value of the data signal. 
         [0036]    The storage capacitor Cst is coupled between the first power supply ELVDD and the first node N 1 , wherein the voltage corresponding to the data signal input per pixel is stored therein. 
         [0037]    Further, the boosting capacitor Cb is coupled between the first node N 1  and the n scan line Sn. The boosting capacitor Cb is provided in order to solve the problem that the data signal stored in the storage capacitor Cst is charged with the voltage lower than the desired voltage to lead in accuracy in displaying low gray scale. Therefore, the boosting capacitor Cb serves to increase the voltage of the first node N 1  when the supply of the scan signal stops, making it possible to solve the problem. 
         [0038]      FIG. 2  is a cross-sectional view showing capacitors formed in each pixel of  FIG. 1 . Although only capacitors are illustrated in  FIG. 2  for convenience, a plurality of transistors are additionally formed in each actual pixel. 
         [0039]    Referring to  FIG. 2 , each pixel of the embodiment includes a semiconductor layer  212 , a first electrode layer  216   a , a second electrode layer  216   b , and a third electrode layer  220 , that are formed on a substrate  210  to form the capacitors Cb and Cst. In other words, at least one of the capacitors Cb and Cst may be formed in a dual capacitor form so that it may secure sufficient capacity. 
         [0040]    Moreover, each pixel further includes a first dielectric layer  214  and a second dielectric layer  218  so that the semiconductor layer  212 , the first electrode layer  216   a , the second electrode layer  216   b , and the third electrode layer  220  can be isolated therefrom. 
         [0041]    First, the semiconductor layer  212  is formed on the substrate  210 . The semiconductor layer  212 , which is formed using the same material as that of a semiconductor layer forming the channel of the transistors, is formed simultaneously with the transistor channel and serves as the lower electrode of the capacitor. As an example, the semiconductor layer  212  can be made of poly-Si. 
         [0042]    After the semiconductor layer  212  is formed on the substrate  210 , the first dielectric layer  214  is formed on the semiconductor layer  212 . The first dielectric layer  214  isolates the first electrode layer  216   a  and the second electrode layer  216  to be formed later from the semiconductor layer  212 . 
         [0043]    Thereafter, the first electrode layer  216   a  is formed in the region where the boosting capacitor Cb is formed simultaneously with forming the second electrode layer  216   b  in the region where the storage capacitor Cst is formed. In this case, the capacity of the storage capacitor Cst is set to be larger than the capacity of the boosting capacitor Cb so that the length of the second electrode layer  216   b  is set to be longer than the length of the first electrode layer  216   a . Meanwhile, the first electrode layer  216   a  and the second electrode layer  216   b  are made of the same material as that of the gate electrodes of the transistors and the scan line. 
         [0044]    In particular, the first electrode layer  216   a  is implemented by being coupled to the scan line as shown in  FIG. 1 . In other words, the first electrode layer  216   a  is formed in a shape where a portion thereof is projected from the scan line per pixel coupled to the scan lines for the scan lines arranged in a row direction. 
         [0045]    After the first electrode layer  216   a  and the second electrode layer  216   b  are formed, the second dielectric layer  218  is formed to cover the first electrode layer  216   a  and the second electrode layer  216   b . The second dielectric layer  218  isolates the first electrode layer  216   a  and the second electrode layer  216   b  electrically from a third electrode layer  220  to be formed later. 
         [0046]    After the second dielectric layer  218  is formed, a contact hole is formed so that the semiconductor layer  212  is exposed between the first dielectric layer  216   a  and the second dielectric layer  216   b . And, a third electrode layer  220  is formed to be coupled to the semiconductor layer  212  through the contact hole. 
         [0047]    Herein, the third electrode layer  220  is formed to implement a dual capacitor. The capacity of the storage capacitor Cst is set to be larger than the capacity of the boosting capacitor Cb so that the third electrode layer  220  is formed on the position overlapped with the second electrode layer  216   b , as shown in the drawing. 
         [0048]    If the third electrode layer  220  is formed as described above, the forming of the storage capacitor Cst and the boosting capacitor Cb is completed. 
         [0049]    In other words, the boosting capacitor Cb is formed through the region where the semiconductor layer  212  is overlapped with the first electrode layer  216   a , and the storage capacitor Cst is formed through the region where the semiconductor layer  212  is overlapped with the second electrode layer  216   b  and the region where the second electrode layer  216   b  is overlapped with the third electrode layer  220 . 
         [0050]    In the case of the pixel described with reference to  FIGS. 1 and 2 , the upper electrode  216   a  of the boosting capacitor Cb is implemented in the form to be coupled to the scan line. Therefore, during the process of forming the upper or the lower electrode of the boosting capacitor Cb, a problem may arise in that a horizontal line shaped spot per scan line may be generated according to the CD distribution. 
         [0051]    In other words, there may be a difference in the overlapped area of the upper electrode and the lower electrode that determines the capacity of the boosting capacitor according to the CD distribution. In this case, the capacity of the boosting capacitor becomes different so that a horizontal line shaped spot may be displayed. 
         [0052]    In order to solve the problem, an embodiment of the present invention has the same area where the upper and the lower electrodes of the boosting capacitor are overlapped per adjacent pixels for the pixels arranged per the respective scan lines but alternately arranges the pixels so that the sizes of the upper and the lower electrodes of the capacitor become different. Therefore, although the CD distribution is generated in the process of forming any one layer, that is, any one electrode of the upper electrode and the lower electrode, the embodiment can prevent line spot from being generated in the entirety in the row direction. 
         [0053]      FIGS. 3A and 3B  are plan views of a boosting capacitor according to an embodiment of the present invention. 
         [0054]    First, referring to  FIG. 3A , the width of the semiconductor layer  212  serving as the lower electrode is formed to be wider than the width of the first electrode layer  216   a  serving as the upper electrode. 
         [0055]    At this time, the first electrode layer  216   a  is implemented in the form where it is coupled to the scan line  310  and a portion thereof is projected from the scan line  310 , as described with reference to  FIG. 2 . 
         [0056]    In other words, in  FIG. 3A , the capacity of the boosting capacitor Ch is determined by the overlapped area of the semiconductor layer  212  and the first electrode layer  216   a.    
         [0057]    In this case, since the width of the semiconductor layer  212  is formed to be wider than the width of the first electrode layer  216   a , the overlapped area becomes different according to the CD distribution when forming the first electrode layer  216   a  so that the capacity of the boosting capacitor Cb becomes different. 
         [0058]    In other words, when the width of the first electrode layer  216   a  becomes narrow according to the CD distribution, the overlapped area of the semiconductor layer  212  and the first electrode layer  216   a  becomes small and makes the capacity of the boosting capacitor Cb small. 
         [0059]    Next, referring to  FIG. 3B , the width of the first electrode  216   a ′ serving as the upper electrode is formed to be wider than the width of the semiconductor layer  212 ′ serving as the lower electrode. 
         [0060]    In this case, since the width of the first electrode layer  216   a ′ is formed to be wider than the width of the semiconductor layer  212 ′, the overlapped area becomes different according to the CD distribution when forming the semiconductor layer  212 ′ so that the capacity of the boosting capacitor Cb becomes different. 
         [0061]    In other words, when the width of the semiconductor layer  212 ′ becomes narrow according to the CD distribution, the overlapped area of the semiconductor layer  212 ′ and the first electrode layer  216   a ′ becomes small and makes the capacity of the boosting capacitor Cb small. 
         [0062]    Therefore, the embodiment has the same area where the upper and lower electrodes of the boosting capacitor are overlapped per adjacent pixels for the pixels arranged per the respective scan lines but allows the even pixels per the respective scan lines to adopt the boosting capacitor shown in  FIG. 3A  and allows the odd pixels per the respective scan lines to adopt the boosting capacitor shown in  FIG. 3B  so that the sizes of the upper and lower electrodes become different. Therefore, although a CD distribution is generated in the process of forming any one layer, that is, any one electrode of the upper electrode and the lower electrode, the embodiment can prevent the horizontal line spot from being generated in the entirety in the row direction. 
         [0063]    While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof.