Abstract:
A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional application of U.S. Ser. No. 15/194,772, filed Jun. 28, 2016 the contents of which are hereby incorporated by reference. The patent application Ser. No. 15/194,772 in turn claims the benefit of priority under 35 USC 119 from U. S. Patent Application No. 62/220,261, 62/220,257, 62/220,258, 62/220,259, all filed on Sep. 18, 2015. 
     
    
     FIELD 
       [0002]    The subject matter herein generally relates to an array substrate, a display device having the array substrate, and method for making the array substrate, more particularly to an array substrate for an organic light emitting diode (OLED) display device. 
       BACKGROUND 
       [0003]    Two common kinds of display devices are a liquid crystal display (LCD) device and an OLED display device. The OLED display device usually includes a substrate, a pixel array, and a driving circuit formed on the substrate. The OLED fabrication process is prone to damage from the high temperature fabrication process which results in degradation in display performance and quality. Furthermore, there is room for improvement in display, operation, and luminance of an OLED device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
           [0005]      FIG. 1  is a plan view of an array substrate. 
           [0006]      FIG. 2  is a circuit diagram of a pixel unit of  FIG. 1 . 
           [0007]      FIG. 3  is a cross-sectional view of a first exemplary embodiment of an array substrate. 
           [0008]      FIG. 4  is a flow chart of a method for making the array substrate of  FIG. 3 . 
           [0009]      FIG. 5  illustrates a step for manufacturing the array substrate of  FIG. 3  at block  601  of  FIG. 4 . 
           [0010]      FIG. 6  illustrates a step for manufacturing the array substrate of  FIG. 3  at block  603  of  FIG. 4 . 
           [0011]      FIG. 7  illustrates a step for manufacturing the array substrate of  FIG. 3  at block  605  of  FIG. 4 . 
           [0012]      FIG. 8  illustrates a step for manufacturing the array substrate of  FIG. 3  at block  607  of  FIG. 4 . 
           [0013]      FIG. 9  illustrates a step for manufacturing the array substrate of  FIG. 3  at block  609  of  FIG. 4 . 
           [0014]      FIG. 10  illustrates a step for manufacturing the array substrate of  FIG. 3  at block  611  of  FIG. 4 . 
           [0015]      FIG. 11  is a cross-sectional view of a second exemplary embodiment of an array substrate. 
           [0016]      FIG. 12  is a cross-sectional view of a third exemplary embodiment of an array substrate. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure. 
         [0018]    Several definitions that apply throughout this disclosure will now be presented. 
         [0019]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. 
         [0020]      FIG. 1  illustrates a display device  1000 . The display device  1000  is an OLED display device and comprises an array substrate  100 . The array substrate  100  comprises a substrate  10 , a pixel array  20 , and a driving circuit  30 . The pixel array  20  and the driving circuit  30  are formed on the substrate  10 . The substrate  10  can be made of a material which is commonly used, such as glass, quartz, or flexible material. The pixel array  20  is configured to display images and comprises a plurality of pixel units  22  arranged in rows and columns. The driving circuit  30  comprises at least one gate driver  38  and at least one source driver  36 . The driving circuit  30  comprises one or more thin film transistors formed on the substrate  10 . The array substrate  100  is a hybrid thin film transistor (TFT) array substrate, and comprises low-temperature poly-silicon TFTs and metal oxide TFTs formed on the substrate  10 . 
         [0021]      FIG. 2  illustrates an equivalent circuit diagram of one of the pixel units  22 . Each pixel unit  22  comprises a light emitting diode  221 , a driving TFT  222 , a switch TFT  223 , and a capacitor C. The switch TFT  223  is electrically connected between the driving circuit  30  (shown as in  FIG. 1 ) and the driving TFT  222  to switch the driving TFT  222  on or off. The driving TFT  222  is electrically connected between a power source VDD and the light emitting diode  221 . The capacitor C is a storage capacitor and is electrically connected between a gate electrode of the driving TFT  222  and a drain electrode of the driving TFT  222 . The capacitor C is configured to control an electrical current of the driving TFT  222 , thus the driving TFT  222  can control a luminance of the light emitting diode  221 . The driving TFT  222  is a metal oxide TFT. In this embodiment, a sub-threshold swing of the driving TFT  222  is larger than that of the switch TFT  223 , which is obtained by adjusting the thicknesses of gate insulator layers in the driving TFT  222  and the switch TFT  223 . The sub-threshold swing indicates the increment of applied voltage to the gate electrode for increasing electrical current of the drain electrode by one order of magnitude. 
         [0022]      FIG. 3  illustrates a cross-sectional view of a first embodiment of the array substrate  100  in part. The array substrate  100  comprises a plurality of poly-silicon TFTs  31 , a plurality of switch TFTs  223 , and a plurality of driving TFTs  222 .  FIG. 3  only shows one poly-silicon TFT  31 , one switch TFT  223 , and one driving TFT  222 . The poly-silicon TFTs  31  may be included in the driving circuit  30  as switches to power on or power off the gate driver  38  and the source driver  36 , and the poly-silicon TFTs  31  may also be included in the pixel units  22 . 
         [0023]    The light emitting diode  221  comprises an anode (not shown), a cathode (not shown), and light-emitting material (not shown) between the anode and the cathode. The anode is electrically coupled to the drain electrode of the driving TFT  222 . The array substrate  100  further comprises dielectric layers (not shown) and a planar layer  90 . The dielectric layers are formed on opposite sides of the light-emitting material. The planar layer  90  forms a top of the array substrate  100 . 
         [0024]    In this embodiment, the poly-silicon TFTs  31  are low-temperature poly-silicon TFTs, the switch TFTs  223  are metal oxide TFTs, and the driving TFTs  222  are metal oxide TFTs. 
         [0025]    Each poly-silicon TFT  31  comprises a poly-silicon semiconductor layer  301 , a buffer layer  303 , a gate electrode  305 , a first gate insulator layer  307 , a second gate insulator layer  308 , a source electrode  309 , and a drain electrode  311 . The poly-silicon semiconductor layer  301 , the buffer layer  303 , the gate electrode  305 , the first gate insulator layer  307 , and the second gate insulator layer  308  are stacked on the substrate  10  in that order. A first through hole  313  and a second through hole  315  passing through the buffer layer  303 , the first gate insulator layer  307 , and the second gate insulator layer  308  are therein defined. The source electrode  309  is formed on the second gate insulator layer  308  and extends through the first through hole  313  to couple to the poly-silicon semiconductor layer  301 . The drain electrode  311  is formed on the second gate insulator layer  308  and extends through the second through hole  315  to couple to the poly-silicon semiconductor layer  301 . 
         [0026]    Each driving TFT  222  comprises a buffer layer  403 , a gate electrode  405 , a first gate insulator layer  407 , a second gate insulator layer  408 , a source electrode  409 , a drain electrode  411 , and a metal oxide semiconductor layer  413 . The buffer layer  403 , the gate electrode  405 , the first gate insulator layer  407 , the second gate insulator layer  408 , and the metal oxide semiconductor layer  413  are stacked on the substrate  10  in that order. The source electrode  409  and the drain electrode  411  are defined by a single layer and are positioned at opposite sides of the metal oxide semiconductor layer  413 . The metal oxide semiconductor layer  413  is coupled to the source electrode  409  and the drain electrode  411 . The metal oxide semiconductor layer  413  may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. 
         [0027]    Each switch TFT  223  comprises a buffer layer  503 , a gate electrode  505 , a second gate insulator layer  508 , a source electrode  509 , a drain electrode  511 , and a metal oxide semiconductor layer  513 . The buffer layer  503 , the gate electrode  505 , the second gate insulator layer  508 , and the metal oxide semiconductor layer  513  are stacked on the substrate  10  in that order. The source electrode  509  and the drain electrode  511  are defined by a single layer and are positioned at opposite sides of the metal oxide semiconductor layer  513 . The metal oxide semiconductor layer  513  is coupled to the source electrode  509  and the drain electrode  511 . The metal oxide semiconductor layer  513  may be made of IGZO, zinc oxide, indium oxide, or gallium oxide. 
         [0028]    In this embodiment, the buffer layer  303 , the buffer layer  403 , and the buffer layer  503  are defined by a single layer and are formed by a single process. The first gate insulator layer  307  and the first gate insulator layer  407  are defined by a single layer and are formed by a single process. The second gate insulator layer  308 , the second gate insulator layer  408 , and the second gate insulator layer  508  are defined by a single layer and are formed by a single process. The first gate insulator layer  307  and the first gate insulator layer  407  are made of silicon nitride; and the second gate insulator layer  308 , the second gate insulator layer  408 , and the second gate insulator layer  508  are made of silicon oxide. Alternatively, the first gate insulator layer  307  and the first gate insulator layer  407  can be made of silicon oxide; and the second gate insulator layer  308 , the second gate insulator layer  408 , and the second gate insulator layer  508  can be made of silicon nitride. 
         [0029]      FIG. 4  illustrates a flow chart of an exemplary method for making the array substrate  100  shown in  FIG. 3 . The method is provided by way of example, as there are a variety of ways for carrying out the method. Each block shown in  FIG. 4  represents one or more processes, methods, or subroutines, carried out in the exemplary method. The exemplary method can begin at block  601 . 
         [0030]    At block  601 , a poly-silicon semiconductor layer  301  is formed on a substrate  10 , as shown  FIG. 5 . The process of forming the poly-silicon semiconductor layer  301  on the substrate  10  may comprise depositing an amorphous silicon layer, annealing, and ion doping the amorphous silicon layer. The substrate  10  can be made of a material which is commonly used, such as glass, quartz, or other flexible material. 
         [0031]    At block  603 , as shown in  FIG. 6 , a buffer layer  303 , a buffer layer  403 , and a buffer layer  503  are formed on the substrate  10 . A gate  305  is then formed on the buffer layer  303 , a gate  405  is formed on the buffer layer  403 , and a gate  505  is formed on the buffer layer  503 . The buffer layer  303  covers the poly-silicon semiconductor layer  301 . The buffer layer  303 , the buffer layer  403 , and the buffer layer  503  are made of an electrically insulative material. An electrically insulative material is deposited or coated on the substrate  10  to form the buffer layer  303 , the buffer layer  403 , and the buffer layer  503 . The process of forming the gate  305 , the gate  405 , and the gate  505  on the substrate  10  may comprise depositing a first metal layer on the buffer layer  303 , the buffer layer  403 , and the buffer layer  503 , and etching and patterning the first metal layer to form the gate  305 , the gate  405 , and the gate  505 . The metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd). The etching process can be a photolithographic etching process. 
         [0032]    At block  605 , as shown in  FIG. 7 , a first gate insulator layer  307  and a first gate insulator layer  407  are formed. The process of forming the first gate insulator layer  307  and the first gate insulator layer  407  may comprise depositing a first insulator layer on the substrate  10 , the gate  305 , the gate  405 , and the gate  505 , and removing a portion of the insulator layer which covers the gate  505 . The first insulator layer is made of silicon nitride or silicon oxide. In this embodiment, the first insulator layer is made of silicon nitride. 
         [0033]    At block  607 , as shown in  FIG. 8 , a second gate insulator layer  308 , a second gate insulator layer  408 , and a second gate insulator layer  508  are formed, and a first through hole  313  and a second through hole  315  are created to expose the poly-silicon semiconductor layer  301 . The second gate insulator layer  308  is formed on the first gate insulator layer  307 , the second gate insulator layer  408  is formed on the first gate insulator layer  407 , and the second gate insulator layer  508  is formed on the buffer layer  503 , and covers the gate  505 . Both the first through hole  313  and the second through hole  315  pass through the second gate insulator layer  308 , the first gate insulator layer  307 , and the buffer layer  303 . The second insulator layer is made of silicon nitride or silicon oxide. In this embodiment, the second insulator layer is made of silicon oxide. 
         [0034]    At block  609 , as shown in  FIG. 9 , a metal oxide semiconductor layer  413  and a metal oxide semiconductor layer  513  are formed. The process of forming the metal oxide semiconductor layer  413  and the metal oxide semiconductor layer  513  may comprise depositing a metal oxide layer, and patterning the metal oxide layer to form the metal oxide semiconductor layer  413  and the metal oxide semiconductor layer  513 . The metal oxide semiconductor layer  413  is formed on the second gate insulator layer  408  and corresponds to the gate  405 . The metal oxide semiconductor layer  513  is formed on the second gate insulator layer  508  and corresponds to the gate  505 . Both the metal oxide semiconductor layer  413  and the metal oxide semiconductor layer  513  can be made of IGZO, zinc oxide, indium oxide, or gallium oxide. 
         [0035]    At block  611 , as shown in  FIG. 10 , a source electrode  309 , a source electrode  409 , a source electrode  509 , a drain electrode  311 , a drain electrode  411 , and a drain electrode  511  are formed. The process of forming the source electrode  309 , the source electrode  409 , the source electrode  509 , the drain electrode  311 , the drain electrode  411 , and the drain electrode  511  may comprise depositing a second metal oxide layer and etching and patterning the second metal layer to form the source electrode  309 , the source electrode  409 , the source electrode  509 , the drain electrode  311 , the drain electrode  411 , and the drain electrode  511 . The source electrode  309  is formed in the first through hole  313 , and the drain electrode  311  is formed in the second through hole  315 . The source electrode  309  and the drain electrode  311  are coupled to the poly-silicon semiconductor layer  301 . The source electrode  409  and the drain electrode  411  are coupled to the metal oxide semiconductor layer  413 . The source electrode  509  and the drain electrode  511  are coupled to the metal oxide semiconductor layer  513 . 
         [0036]    At block  613 , as shown in  FIG. 3 , a planar layer  90  is formed to cover the poly-silicon TFT  31 , the switch TFT  223 , and the driving TFT  222 . The method further comprises forming an anode (not shown), a cathode (not shown), and a light-emitting material (not shown) for the light emitting diode  221 . 
         [0037]    In this embodiment, the poly-silicon TFTs  31  are low-temperature poly-silicon TFTs, which can be positioned in a non-display region of the display device  1000 . The poly-silicon TFTs  31  have high electron mobility and can improve a reaction rate of the driving circuit. The poly-silicon TFTs  31  have a small volume, allowing a narrowing of the non-display region. 
         [0038]    The switch TFT  223  comprises only one gate insulator layer and the driving TFT  222  comprises two gate insulator layers. That is, the thicknesses of the gate insulator layers of the driving TFT  222  is greater than that of the switch TFT  223 , thus a gate capacitance of the driving TFT  222  is less than that of the switch TFT  223 , and a sub-threshold swing of the driving TFT  222  is higher than that of the switch TFT  223 . Therefore, the driving TFT  222  can, with very fine precision, control the luminance of the light emitting diode  221 , and the switch TFT  223  can reduce operating voltage and increase operating rate of the circuit. 
         [0039]      FIG. 11  illustrates a cross-sectional view of a second embodiment of an array substrate (array substrate  200 ) in part. The array substrate  200  is substantially the same as the array substrate  100 , except that the metal oxide semiconductor layer  413  of the driving TFT  222  is formed on the second gate insulator layer  408 , the source electrode  409  and the drain electrode  411 , and partially covers the source electrode  409  and the drain electrode  411 . In the array substrate  100 , the source electrode  409  and the drain electrode  411  partially cover the metal oxide semiconductor layer  413 . In the array substrate  200 , the metal oxide semiconductor layer  413  is formed after the source electrode  409  and the drain electrode  411  have been formed, this protects the metal oxide semiconductor layer  413  from damage during the process of forming the source electrode  409  and the drain electrode  411 . 
         [0040]      FIG. 12  illustrates a cross-sectional view of a third embodiment of an array substrate (array substrate  300 ) in part. The array substrate  300  is substantially the same as the array substrate  100 , except that the metal oxide semiconductor layer  413  of the driving TFT  222  is formed on the second gate insulator layer  408 , the source electrode  409 , and the drain electrode  411 , and partially covers the source electrode  409  and the drain electrode  411 ; and the metal oxide semiconductor layer  513  of the switch TFT  223  is formed on the second gate insulator layer  508 , the source electrode  509  and the drain electrode  511 , and partially covers the source electrode  509  and the drain electrode  511 . In the array substrate  100 , the source electrode  409  and the drain electrode  411  partially cover the metal oxide semiconductor layer  413 ; and the source electrode  509  and the drain electrode  511  partially cover the metal oxide semiconductor layer  513 . In the array substrate  300 , the metal oxide semiconductor layer  413  is formed after the source electrode  409  and the drain electrode  411  have been formed. The metal oxide semiconductor layer  513  is formed after the source electrode  509  and the drain electrode  511  have been formed. 
         [0041]    The embodiments shown and described above are only examples. Many details are often found in the art such as other features of a display device. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.