Abstract:
A resettable electronic counter employing an integrated solid state calculator circuit element, or chip, includes counter reset circuitry for automatically resetting the counter. The calculator circuit provides timing signals and is responsive to timing signals selectively connected to an arithmetic and control section thereof for clearing a count stored in registers thereof and display means external thereto, for storing a selected count in the registers, and for cumulatively adding indexing signals to the stored count. The counter reset circuitry includes control logic and a sequence counter actuated by a reset signal to generate a series of step signals. The step signals and certain timing signals are connected to the control logic which is in turn connected to the arithmetic and control section of the calculator circuit. The reset circuitry is operable to apply, to the arithmetic and control section, in predetermined sequence, those timing signals for clearing and for storing a count, and additionally to control the application of count indexing signals.

Description:
BRIEF SUMMARY OF THE INVENTION 
     The invention relates to electronic counters and more particularly to resettable electronic counters. 
     It is a primary object of the invention to provide a low cost electronic counter. 
     It is another object of the invention to provide an improved electronic counter of reduced cost and size relative to a comparable electromechanical counter. 
     It is a further object to provide an improved counter according to the invention which exhibits longer life and greater accuracy than a comparable electromechanical counter. 
     It is an even further object to provide an improved counter according to the invention which is easily reset. 
     It is still another object of the invention to provide an improved counter according to the invention which employs LSI circuitry. 
     It is a still further object to provide an improved counter according to the invention which includes reset sequencing circuitry for automatically clearing a previous count and conditioning the counter for counting in preselected steps or increments. 
     Other objects will be in part obvious and in part pointed out more in detail hereinafter. 
    
    
     A better understanding of the invention will be obtained from the following detailed description and the accompanying drawing of an illustrative application of the invention. 
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing: 
     The FIGURE is a functional diagram or schematic of the counter of the invention including conventional logic elements. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the drawing in detail wherein like numerals and/or letters are used to designate like parts or logic signals, the FIGURE shows a counter 100 according to the invention which receives electrical count input or indexing signals from some pulse source 10. Pulse source 10 typically provides count pulses caused by contact closures, photoelectric beam interruptions or the like, as indications of events or quantities to be counted. The indexing signal pulses IP from source 10 are connected with and applied to the counter 100 through an input circuit, generally designated 80, which includes an isolating circuit 12 typically including light emitting and light responsive circuit elements, for electrically isolating the pulse source circuitry 10 from the counter while serving to couple the input pulses thereto. A DC power supply 14, such as a small battery, provides a positive DC potential of 9 volts and is connected to the isolating circuit 12. Isolating circuit 12 outputs a positive signal symbolic of the logic 1 state, and also designated IP, each time an input pulse is generated by pulse source 10. The output of isolating circuit 12 is connected as one of the inputs to AND gate 16 for controlling introduction of count-indexing signals to an electronic calculator circuit 18 following conditioning of the circuit 18 to begin a counting operation. Calculator circuit 18 forms a core counter circuit for incrementally counting input signal pulses IP. 
     Calculator circuit 18, shown here in block diagram form in the interest of brevity, is in the form of a single LSI solid state element, commonly referred to as a &#34;chip,&#34; of the type commonly used in electronic calculators. Circuit 18, hereinafter referred to as &#34;chip 18,&#34; uses state of the art LSI technology employing PMOS, CMOS or the like. In the embodiment being described, chip 18 comprises a PMOS/LSI 6 digit calculator circuit (MM5736) by National Semiconductor Corporation. 
     Chip circuit 18 includes an arithmetic and control circuit section 66 (hereinafter A and C section) and an internal clock 68. A and C circuit 66 receives data signals for entry via the conductor circuits of chip input terminals K 1 , K 2  and K 3 . A and C section 66 includes, in addition to control logic, several (in this instance three) registers, generally designated as register group 70. Registers 70 serve a count storage function for counts entered directly and for those resulting from an arithmetic operation of previously entered counts, both capable of concurrent storage in separate registers. 
     Clock or timing generator 68 provides the synchronizing signals required to enter, process and display a count. Clock 68 repetitively generates a sequence of six binary signals in the logic 1 state. Each of these timing or digit signals appears respectively at a corresponding one of the terminals D 1 , D 2 , D 3 , D 4 , D 5  and D 6  on chip 18. Similarly, these timing signals, which will be referred to by the terminals D 1-6  at which they appear, always are internally connected to the registers 70 of A and C section 66. The word D 1  to D 6 ) cycle frequency is about 1-2 KHz, corresponding with a word time or period of about 1/2 - 1 millisecond. Each digit or timing signal D 1-6  has a period of slightly less than one-sixth of the full word period. 
     At least one of the registers of register group 70 of chip 18 is connected to seven output connectors or terminals S 1 , S 2 , S 3 , S 4 , S 5 , S 6  and S 7  for outputting, to a display panel or register 22, binary coded signals indicative of the number or digit counts of a count stored in the registers 70. The data signals S 1-7 , designated in accordance with the terminals at which they appear, are all connected to corresponding binary inputs of each of six digit display devices 20 which comprise the readout display of regiser 22. Each display device 20 comprises an LED seven segment display, each of the seven LED segments being connected to a corresponding terminal S 1-7  of chip 18. Accordingly, in this embodiment, the binary coded signals S 1-7  collectively comprise a seven segment coded decimal representation. 
     Entry and display at register 22 of each particular digit of a count stored in a register of group 70 is affected by sequentially providing groups of segment signals S 1-7 , each group corresponding with a particular digit of the count stored in the register and being coded to energize the appropriate segments of a particular display device 20. Each particular display device 20 is sequentially enabled to receive and display the appropriate group of segment signals S 1-7  by means of a different one of the timing signals D 1-6  respectively connected thereto through driver circuits 24. Each group of segment signals S 1-7  which corresponds with a particular digit is in synchronism with one of the timing signals D 1-6 . In this manner, the segment signals S 1-7  corresponding with a particular digit of a stored count will be outputted from chip 18 and entered into the appropriately positioned display device 20 through the control timing of a particular corresponding one of the timing signals D 1-6 . 
     Referring more specifically to the arithmetic and control section 66 of chip 18, selective application of timing signals D 1-6  to the data entry terminals K 1  and K 2  thereof is effective to store a selected count in the registers 70 and to display it on display register 22. Further, such selective application of signals D 1-6  to terminal K 3  is effective to enter mathematical operation instruction signals to A and C section 66. The particular chip used in the preferred embodiment is capable of entering any digit from 0-9 by selective connection of a timing signal D 1-6  to one of the terminals K 1  or K 2 . The operation instructions, which include add, subtract, multiply, divide and clear, are entered via a terminal K 3 . The digit 1 is entered by applying timing signal D 2  to terminal K 1 . Because the counter 100 is intended, in this instance, to count in steps or increments of one, the 1 digit is the only digit requiring entry and the K 2  input is accordingly blocked by connection to ground. It will be appreciated, however, that an input pulse IP to counter 100 might be indicative of some quantity other than 1 and that such pulse, through association with the appropriate one of digit signals D 1-6  and with chip input K 1  or K 2 , may advance the count by that of the quantity. Power terminals Vss and Vdd of chip 18 are respectively connected to the positive DC potential of power supply 14 and to ground. 
     The A and C section 66 converts a count input into BCD form and processes the count in the BCD form. A count to be displayed is transcoded from BCD form to the requisite binary seven segment coded decimal form. For use as a counter and particularly in the preferred embodiment thereof, only the &#34;add&#34; instruction of the four aforementioned basic arithmetic operators is employed. The &#34;clear&#34; instruction is also required. The &#34;add&#34; instruction is entered by applying timing signal D 4  to terminal K 3 . The &#34;clear&#34; instruction is entered by applying timing signal D 1  to terminal K 3 . In fact, to enter any digit or instruction into chip 18, the appropriate timing signal must be repeated for eight consecutive word cycles, this being required to avoid errors which might be introduced by contact noise, as during keying or switch actuation. Accordingly, when it is said that the occurrence of a timing signal at an input to the chip is effective to enter some number or instruction, it is implied that the required eight occurrences of that timing signal do occur. Also, the inputs (K 1  and K 3 ) to chip 18 must be &#34;open&#34; with no input signal present between each successive digit or instruction to be entered. This permits recognition of successive digits and is obtained by maintaining the &#34;open&#34; status for at least eight word periods. 
     Generally speaking, a number consisting of one or more digits (up to six) may be entered into a register of group 70, with that number being displayed on display register 22. To add two numbers, it is generally necessary to enter the first number; enter the &#34;add&#34; instruction; enter the second number; and again enter the &#34;add&#34; instruction to effect the arithmetic addition, the sum being displayed on display register 22. However, in the particular chip 18 used in the embodiment described herein, if the successive counts or numbers to be added are all the same, as is the case, it is only necessary to enter the selected number or count radix one time and an auto summing capability of the chip serves to arithmetically add the count radix to any previous sum, stored in registers 70, and to display the new count sum upon the second and each successive time the &#34;add&#34; instruction is entered, so long as no other number or instruction is entered therebetween. The initial entry of the &#34;add&#34; function serves to condition the registers 70 to receive the next number or count entry and, in the arrangement of the invention, will also redisplay the count radix following its removal from display by a single intermediate &#34;clear&#34; instruction. 
     In order to clear a number from display register 22 and the associated storage register in the A and C section 66 of chip 18, a &#34;clear&#34; function instruction must be entered through input terminal K 3 . If the entry of the &#34;clear&#34; instruction comes immediately after entry of another instruction, as opposed to a number, it will clear all registers in the C and A section 66. However, if the &#34;clear&#34; instruction is entered immediately after entry of a number, it clears only that register of group 70 which contains and displays that number immediately previously entered, and does not clear the other register or registers of group 70. The registers of group 70 which are not cleared by the single &#34;clear&#34; instruction contain either that number immediately previously entered, if it was the first number entered following clearance of all registers, or else an earlier entered number. In this latter situation, it then is necessary to provide two consecutive entries of the &#34;clear&#34; instruction in order to clear all registers. 
     Referring now to the reset sequence circuitry of counter 100, generally designated 26, a reset sequencing binary counter 28 is operative, with associated control logic, generally designated 60, to clear all of the registers 70 of chip 18 to an &#34;empty,&#34; or zeroed, state and to subsequently enter a selected number, in this instance a &#34;one,&#34; into the chip to establish the integer by which the count is advanced with receipt of each input counting pulse. In this manner, counter 28 automatically establishes and controls several data entry modes during the reset mode. To facilitate an understanding of counter 28, it is depicted and described as a compound counter comprising a first, lower order, divide-by-8, or 8 step, counter 30, and a second, higher order, divide-by-16, or 16 step, counter 32 connected serially to the output of counter 30 and having a four conductor binary output. In fact, counter 28 is preferably a seven stage electronic counter having outputs from each of the last four stages (i.e. counter 32) and employing MOS integrated circuitry. The first three stages of counter 28 (i.e., counter 30) are needed to permit each particular selected digit signal to appear eight successive times at an input in order to be entered in chip 18, as earlier noted. 
     Counters 30 and 32 of counter 28 are set to an initial zeroed condition by application thereto of a reset signal, or pulse, R. Pulse R is selectively provided by closing a normally open push button switch 34 having one contact connected to ground and the other contact connected to counter 30 through reset pulse circuit 36. Circuit 36 and logic negation element 37 are operative to apply the R signal in the logic 1 or positive potential state to the several stages of counters 30 and 32 when and while the push button switch 34 is closed and to remove the R signal when the push button is released. Application of the R signal to counters 30 and 32 results in all of their stages being set (or reset) to a zero count condition. 
     More specifically, reset pulse circuit 36 includes capacitor 57 connected to ground at one side and through resistor 58 to power supply 14 at the other side. The ungrounded contact of push button switch 34 is connected to the junction of resistor 58 and capacitor 57 as is the input to negation element 37. This arrangement is operative to filter any noise which might be picked up on the ungrounded contact of push button switch 34 and which otherwise might generate false reset signals. Also, it retards the rate of voltage rise at the input to negation device 37 when power is turned on, thereby providing a transitory reset pulse R which automatically disappears shortly after power is applied. Diode 59 is connected in parallel with resistor 58 to rapidly discharge capacitor 57 during any brief power losses, thereby ensuring the transitory reset pulse described in the previous sentence. 
     The input stepping pulses to counter 30 of sequencing counter 28 are provided by timing signal D 5  from chip 18. Signal D 5  is connected to one input of a two-input AND gate 38. The output conductor from the last stage of counter 32 having the binary encoded value of 8 is connected to the other input of AND gate 38 through a logic negation element 40. When the counters 30 and 32 are set to a logic 0 level by reset pulse R, negation element 40 is operative to apply a logic 1 at that input to AND gate 38, thereby enabling each D 5  pulse in the logic 1 state to be passed by the AND gate, the output of which is connected to the input of counter 30. Each D 5  signal passed by AND gate 38 steps counter 30. The output or final stage of ÷ 8 counter 30 is connected to the input or first stage of ÷ 16 counter 32. Following receipt of eight D 5  signals by counter 30, that counter is effective to provide a stepping signal or pulse to the input of counter 32. Similarly, for each eight D 5  signals thereafter, counter 32 is stepped an additional step. Further reference to the steps of counter 32 will inherently infer the presence of eight times as many steps of counter 30. The stepping of counter 32 continues until its eighth step at which point its output having the binary encoded value of 8 changes from the logic 0 to the logic 1 state. This attainment of the logic 1 state is effective, through logic negation element 40, to prevent further transmission of D 5  signals through AND gate 38 to counter 30 and thus represents completion of the reset sequence for counter 100. 
     In addition to AND gate 16, the reset sequence control logic includes NAND gate 42, AND gate 44, AND gate 46 and OR gate 48. NAND gate 42 receives, at its three inputs, the binary encoded outputs 1, 2 and 4 of counter 32. Outputs 1 and 4 are applied to NAND gate 42 in the normal state, whereas the binary encoded 2 output is inverted by logic negation element 50 prior to its connection as an input to the NAND gate. 
     Table I appearing hereinafter correlates the several counter resetting operations to be discussed with the various outputs or steps of the ÷ 16 reset counter 32. 
     
                                           TABLE I__________________________________________________________________________STEP    BINARY STATE OF EACH(of ÷ 16   OUTPUT OF COUNTER 32Counter 32)   8   4   2   1 RESET SEQUENCE OPERATIONS__________________________________________________________________________0       0   0   0   0 Reset Counters 30 and 32 and                  Open Input to Counter 301       0   0   0   1 Clear (Display Register)                  (D.sub.1 -K.sub.3)2       0   0   1   0 Open3       0   0   1   1 Clear (All Registers)                  (D.sub.1 -K.sub.3)4       0   1   0   0 Open5       0   1   0   1 Enter 1 (D.sub.2 -K.sub.1)6       0   1   1   0 Open7       0   1   1   1 Clear (Display Register)                  (D.sub.1 -K.sub.3)8       1   0   0   0 Close Input to Counter 30__________________________________________________________________________ 
    
     From Table I, it is readily determined that the output of NAND gate 42 will be logic 1 for steps 1-4 and 6-8 of counter 32 and a logic 0 only for step 5. The output of NAND gate 42 is connected as one of the three inputs to AND gate 44. The binary encoded 1 output of counter 32 is connected as another of the inputs of AND gate 44 and the D 1  digit signal is connected as the remaining input to the AND gate. Signal D 1 , as a logic 1, is passed to the output of AND gate 44 during each odd numbered step of counter 32 except step 4, or in other words, it appears as an output during steps 1, 3 and 7 of the counter. 
     The output of AND gate 44 is connected as an input to OR gate 48. Accordingly, each D 1  signal passed by AND gate 44 is also passed by OR gate 48 and appears at its output for connection via conductor 54 to input K 3  of chip 18. In this manner, a logic 1 signal corresponding in time with signal D 1  is applied to the K 3  input of chip 18 during steps 1, 3 and 7 of counter 32. As hereinbefore discussed, a D 1  signal applied to the K 3  input of chip 18 is effective in the first instance to clear either some or all of the registers 70 of the chip 18 and to remove the display from register 22, and in the immediately succeeding instance to clear any remaining registers not initially cleared. 
     The output of NAND gate 42 is additionally inverted by logic negation element 52 and then applied as one of the two inputs to AND gate 46. The other input to AND gate 46 is provided by the D 2  digit signal connected thereto from chip 18. The inverted output of NAND gate 42 will exist as a logic 1 only during the fifth step of ÷ 16 counter 32 and accordingly, D 2  as a logic 1 is passed by AND gate 46 to its output only during that fifth step of the counter 32. Conductor 56 is connected from the output of AND gate 46 to the K 1  input of chip 18 for applying the D 2  signal to the K 1  input during the fifth step of counter 32. As earlier discussed, a D 2  signal applied to the K 1  input is effective to enter the selected count digit one (1) in the registers of chip 18 and to display the 1 on display panel 22. 
     The &#34;clear&#34; operation resulting from the D 1  signal on the K 3  input during the seventh step of counter 32 is effective to clear that register of A and C section 66 which provides the output display, thereby removing display of the digit 1 from register 22; however, as earlier mentioned, it does not entirely clear the digit from storage in chip 18, but allows it to remain in storage in another of the registers 70 of the A and C section preparatory to the subsequent auto summing of the digit in response to the input pulses to be counted. It will be noted that steps 2, 4 and 6 (as well as 0 and 8) provide the requisite &#34;open&#34; status at inputs K 1  and K 3  between each digit or function input. 
     The input pulses IP from isolating circuit 12 are connected to one of the three inputs of AND gate 16. The binary encoded 8 output of ÷ 16 counter 32 is connected to another input of AND gate 16 and the D 4  timing signal is applied to the remaining input. The output from counter 32 serves to maintain gate 16 closed during the reset sequencing of counter 28, thereby preventing passage of a D 4  signal even though an input pulse IP may be present. However, upon completion of the reset sequencing of counter 28 (at the eighth step of counter 32), gate 16 is conditioned to pass a D 4  signal each time a count indexing input pulse exists concurrently therewith. The input pulses IP are scaled to be at least eight word periods in duration in order to permit the requisite eight successive D 4  timing signals to input to chip 18 in order to effectively input a digit, or in this instance, a mathematical operation instruction. The D 4  signal passed by AND gate 16 is connected from the output thereof to the input of OR gate 48. The output of OR gate 48 is connected via conductor 54 to the K 3  input of chip 18. The application of the D 4  timing signal to the K 3  input serves to input the &#34;add&#34; or &#34;+&#34; instruction to chip 18. As previously indicated, the selected radix count, &#34;one,&#34; was entered in chip 18 during the fifth step of counter 32 and was retained during the seventh step. An &#34;add&#34;instruction occurring immediately thereafter serves to display the initially entered &#34;one&#34; on display register 22. Because of the auto summing capability of chip 18, each consecutively succeeding &#34;add&#34; instruction input serves to advance the count displayed on register 22 by one. Thus, each succeeding input pulse IP inputs an &#34;add&#34; instruction to chip 18, thereby advancing the count in unit increments. This continues until such time as counter 100 is reset by temporarily closing switch 34 to activate reset counter 28, as previously described. 
     Recapitulating, actuation of switch 34 results in the application of a reset signal R to counters 30 and 32 of sequencing counter 28 to set them to an initially zeroed condition. Upon removal of the R signal, counter 30 begins stepping in response to D 5  timing signals and steps counter 32 one step for each eight D 5  signals received. 
     That output of counter 32 having the binary encoded value of &#34;8&#34; operates to block further operation of sequencing counter 28 after eight steps of the counter 32. The outputs of counter 32 which have the binary encoded values of 1, 2 and 4 operate through NAND gate 42 and AND gates 44 and 46 to gate a D 1  -K 3  &#34;clear&#34; signal to chip 18 during steps 1, 3 and 7 of counter 32 and a D 2  -K 1  &#34;one&#34; signal to the chip during step 5 of the counter. No input is made to chip 18 during the resetting of counter 28 to the zeroed condition and during steps 2, 4 and 6 of counter 32 thereafter. When counter 32 reaches step 8, AND gate 16 is conditioned to apply a D 4  -K 3  &#34;add&#34; pulse to chip 18 each time a count input pulse appears at the input to gate 16, thereby advancing the count displayed on display panel 22 in increments of &#34;one.&#34; 
     As will be apparent to persons skilled in the art, various modifications, adaptations and variations of the foregoing specific disclosure can be made without departing from the teachings of the present invention.