Abstract:
An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to electrostatic discharge (ESD) protection generally and, more particularly, to a method and/or apparatus for implementing automatic placement based ESD protection insertion.  
       BACKGROUND OF THE INVENTION  
       [0002]     At the deep sub-micron level, such as 90 nm or 65 nm structures, the protection of transistor gates has become important. One example of a design rule in deep sub-micron technologies is that the gate voltage should not be larger than the supply voltage of a transistor. In an application specific integrated circuit (ASIC) design, thousands of gates and/or pins are each connected either to a static “logic one” or “logic zero” The gate and/or pins need to be connected to a voltage VDD or a voltage VSS. The voltage VDD or VSS is connected to the gate of the transistors. This approach is called “tie up” or “tie down” of a signal and/or gate.  
         [0003]     Conventional tie up and tie down nets generally provide one of the largest contributions to high fanout “signal” nets in designs. In 90 nm or 65 nm technologies, design rules generally prohibit the voltage at a gate from being larger than the voltage for the supply of the transistor. With conventional methods, the gate input of the transistor is tied to the logic zero and/or the logic one. A cell power rail and/or a thick power rail is directly connected to the gate input of a transistor. The transistor is tied to the logic zero and/or logic one. Conventional approaches cannot assure that the gate input voltage of the transistor is lower than the voltage of the power supply.  
         [0004]     Conventional approaches attempt to solve this issue by inserting an electrostatic discharge (ESD) buffer and/or decoupling buffer to avoid the direct connection of the logic gate to the VDD or VSS net. The inserted buffer is a global cell that connects global signals. The buffer is manually inserted in the netlist. The manual connection is made by the designer.  
         [0005]     Referring to  FIG. 1 , a block diagram of a circuit  10  illustrating a conventional approach for connecting one or more standard cells is shown. The circuit  10  generally comprises a number of I/O cells  12   a - 12   n , a global tie down cell  14 , a global tie up cell  16 , a number of standard cells  18   a - 18   n , and a number of standard cells  20   a - 20   n . The standard cells  18   a - 18   n  are coupled to the global tie down cell  14 . The global tie down cell  14  is coupled to the I/O cell  12   c . The voltage VSS is supplied to the I/O cell  12   c . The standard cells  20   a - 20   n  are coupled to the global tie up cell  16 . The global tie up cell  16  is coupled to the I/O cell  12   b . The voltage VDD is supplied to the I/O cell  12   b.    
         [0006]     With the circuit  10 , only one global tie up cell  14  and one global tie down cell  16  are implemented. The single global tie up cell  16  and the single global tie down cell  14  do not link to the real design. The global tie down cell  14  and tie up cell  16  generate interconnect signals that can be the root cause of many issues in the subsequent design flow. The global tie down cell  14  and tie up cell  16  can significantly hurt the design closure flow by generating severe congestion during the design routing phase.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention concerns an apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.  
         [0008]     The objects, features and advantages of the present invention include providing localized tie up and tie down cells that may (i) be connected to the VDD and the VSS net without destruction of the ESD buffer and/or (ii) avoid ESD damage on any input pin of a cell in a register transfer logic (RTL) netlist and/or a pre-layout gate level netlist. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:  
         [0010]      FIG. 1  is a block diagram of a conventional approach for cell connection of standard cells;  
         [0011]      FIG. 2  is a block diagram of a preferred embodiment of the present invention;  
         [0012]      FIG. 3  is a detailed block diagram illustrating ESD protection on localized tie up nets; and  
         [0013]      FIG. 4  is a flow chart illustrating ESD protection in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0014]     Referring to  FIG. 2 , a block diagram of a system  100  is shown in accordance with a preferred embodiment of the present invention. The system  100  generally comprises a number of cells  102   a - 102   n , a number of cells  104   a - 104   n , a number of cells  106   a - 106   n , a number of cells  108   a - 108   n , a number of circuits  120   a - 120   n , and a number of a number of circuits  122   a - 122   n , a number of circuits  124   a - 124   n , a number of circuits  126   a - 126   n , a number of circuits  140   a - 140   n , a number of circuits  142   a - 142   n , a number of circuits  144   a - 144   n  and a number of circuits  146   a - 146   n.    
         [0015]     The circuit  100  may be implemented on a single integrated circuit package. The circuits  120   a - 120   n  may be implemented as local tie up cells. The circuits  122   a - 122   n , the circuits  124   a - 124   n , and the circuits  126   a - 126   n  may be implemented as standard cells. The circuits  140   a - 140   n  may be implemented as local tie down cells. The circuits  142   a - 142   n , the circuits  144   a - 144   n , and the circuits  146   a - 146   n  may be implemented as standard cells.  
         [0016]     The local tie up cell  120   a  may be coupled to the standard cells  122   a - 122   n . The local tie up cell  120   b  may be coupled to the standard cells  124   a - 124   n . The local tie up cell  120   n  may be coupled to the standard cells  126   a - 126   n . The local tie down cell  140   a  may be coupled to the standard cells  142   a - 142   n . The local tie down cell  140   b  may be coupled to the standard cells  144   a - 144   n . The local tie down cell  140   n  may be coupled to the standard cells  146   a - 146   n . The standard cells may be implemented as transistors. The particular type of transistors used may be varied to meet the design criteria of a particular implementation.  
         [0017]     The local tie up cells  120   a - 120   n  and the local tie down cells  140   a - 140   n  may be implemented as buffers (e.g., an electrostatic discharge (ESD) buffer and/or a decoupling buffer). The particular type of buffer implemented may be varied to meet the design criteria of a particular implementation. A voltage (e.g., VDD) may be applied to any one of the cells  102   a - 102   n . The voltage VDD may be presented from a VDD net (not shown) to any one of the cells  102   a - 102   n . The local tie up cell  120   a  may be coupled to one of the cells  102   a - 102   n  which provides the voltage VDD. In general, the local tie up cell  120   a  may buffer the voltage VDD prior to the passing the voltage VDD to the transistors  122   a - 122   n . The voltage VDD may be received by the gate of the transistors  122   a - 122   n . A voltage (e.g., VSS) may be applied to any one of a particular number of cells  102   a - 102   n  from a VCC net. The voltages VSS and VDD may be applied to one or more of the cells  102   a - 102   n . The number of cells  102   a - 102   n  that may present the voltages VSS and VDD may be varied to meet the design criteria of a particular implementation.  
         [0018]     The voltage VSS may be applied to any one of the cells  104   a - 104   n . The local tie down cell  140   a  may be coupled to one of the cells  104   a - 104   n  that provides the voltage VSS. The local tie down cell  140   a  may buffer the voltage VSS prior to passing the voltage VSS to the transistors  142   a - 142   n . The voltage VSS may be received by the gate of the transistors  142   a - 142   n . The voltage VDD may also be applied to any one of the cells  104   a - 104   n . The local tie up cell  120   b  may be coupled to one of the cells  104   a - 104   n  that provides the voltage VDD. The local tie up cell  120   b  may buffer the voltage VDD prior to passing the voltage VDD to the transistors  124   a - 124   n . The voltage VDD may be received by one of the gates of the transistors  124   a - 124   n . The voltages VSS and VDD may be applied to one or more of the cells  104   a - 104   n . The number of cells  104   a - 104   n  that may present the voltages VDD and VSS may be varied to meet the design criteria of a particular implementation.  
         [0019]     The voltage VSS may be applied to any one of a particular number of cells  106   a - 106   n . The local tie down cell  140   b  may be coupled to one of the cells  106   a - 106   n  that provides the voltage VSS. The local tie down cell  140   b  may buffer the voltage VSS prior to passing the voltage VSS to the transistors  144   a - 144   n . The voltage VSS may be received by the gate of one of the transistors  144   a - 144   n . The voltage VDD may also be applied to one of the cells  106   a - 106   n . The local tie up cell  120   n  may be coupled to one of the cells  106   a - 106   n  that provides the voltage VDD. The local tie up cell  120   n  may buffer the voltage VDD prior to passing the voltage VDD to the transistors  126   a - 126   n . The voltage VDD may be received by one of the gates of the transistors  126   a - 126   n . The voltages VSS and VDD may be applied to one or more of the cells  104   a - 104   n . The number of cells  104   a - 104   n  that may present the voltages VDD and VSS may be varied to meet the design criteria of a particular implementation.  
         [0020]     The voltage VSS may be applied to one of the cells  108   a - 108   n . The local tie down cell  140   n  may be coupled to one of the cells  108   a - 108   n  that provides the voltage VSS. The local tie down cell  140   n  may buffer the voltage VSS prior to passing the voltage VSS to the transistors  146   a - 144   n . The voltage VSS may be received by one of the gates of the transistors  146   a - 146   n . The voltage VDD may be applied to any of the cells  108   a - 108   n . The voltages VSS and VDD may be applied to one or more number of cells  102   a - 102   n . The number of cells  102   a - 102   n  that may present the voltages VDD and VSS may be varied to meet the design criteria of a particular implementation.  
         [0021]     Referring to  FIG. 3 , a block diagram of a circuit  300  illustrating ESD protection on local tie up nets is shown. The circuit  300  generally comprises a number of circuits  302   a - 302   n  and a number of standard cell rows  308   a - 308   n . A number of circuits  302   a - 302   n  may be implemented as localized tie up nets. The circuit  300  may include local tie down nets (not shown) The standard cell rows  308   a - 308   n  may include power lines generally connected to a chip power mesh (not shown).  
         [0022]     The tie up net  302   a  generally comprises a local tie up cell  120   a ′ and a number of standard cells  122   a ′- 122   n ′. The local tie up cell  120   a ′ may be coupled to the standard cells  122   a ′- 122   n ′. The tie up net  302   n  generally comprises a local tie up cell  120   n ′ and a number of standard cells  126   a ′- 126   n ′. The local tie up cell  120   n ′ may be coupled to the standard cells  126   a ′- 126   n′.    
         [0023]     A power supply (not shown) may present a plurality of voltages (VSS_A-VSS_N) to the circuit  300 . A plurality of inputs  310   a - 310   n  may receive the voltages VSS_A-VSS_N. A power supply (not shown) may present a plurality of voltages (VDD_A-VDD_N) to the circuit  300 . A plurality of inputs  312   a - 312   n  may receive the voltages VDD_A-VDD_N.  
         [0024]     The circuit  302   a  may receive the voltage VDD_A on the input  312   a . The tie up cell  120   a ′ may receive the voltage VDD_A on the standard cell row  308   b . The circuit  302   n  may receive the voltage VDD_N on the input  312   n . The local tie up cell  120   n ′ may receive the voltage VDD_N on the standard cell row  308   n.    
         [0025]     Generally, each of the voltages VSS_A-VSS_N are not equal in value due to various IR (current and resistance) drops across the circuit  300 . Each of the voltages VDD_A-VDD_N are not equal in value due to various IR drops across the circuit  300 . The voltage VDD_A in the area of the local tie up net  302   a  may be VDD_A+X, where X is a value given to compensate for the IR drop across the circuit  300 . The voltage VDD_N in the area of the tie up net  302   n  may be VDD_N−Y, where Y is a value given to compensate for the IR drop across the circuit  300 . Generally, the tie up net  302   a  may be separated from the tie up net  302   n  by a predetermined distance. If the circuits  302   a  and  302   n  were implemented as tie down nets, the circuits  302   a  and  302   n  may be separated by a predetermined distance.  
         [0026]     In one example, the circuit  302   a  may be implemented as a tie up net and the circuit  302   n  may be implemented as a local tie down net. The circuits  302   a  and the circuit  302   n  may be separated by a predetermined distance. The predetermined distance between the circuits  302   a  and  302   n  may be varied to meet the design criteria of a particular implementation. For example, the predetermined distance may be varied to meet the specification of a particular technology. The change in voltage may also be varied to meet the design criteria of a particular implementation.  
         [0027]     Referring to  FIG. 4 , a method  400  for providing ESD protection is shown. The method  400  generally comprises a state  402 , a state  404 , a state  406 , a state  408 , a state  410 , a state  412  and a decision state  414 . The state  402  generally comprises determining a pre-layout netlist from synthesis without any changes. The state  404  generally comprises performing floor-planning and standard cell placement. The state  406  generally comprises determining timing and post placement optimization. The pre-layout netlist generated in the state  402  may be implemented into the cell placement of the state  404  and into the post placement optimization of state  406 . The state  408  generally comprises implementing a new ESD optimization and tie up/tie down connection after the cell placement and the post optimization phase.  
         [0028]     The new ESD optimization phase in the state  408  may perform an automatic insertion of the ESD protected tie up and/or tie down cells based on the placement of the logic cells. The gates of the transistors in a certain area may be connected to the local tie up and/or tie down cells (e.g., the ESD buffers). The method  400  may ensure that no other design rules are violated. The method  400  may also prevent large fan out nets in the design. A user may no longer need to be concerned with the placement of the standard cells and the connections to the local tie up cells and the local tie down cells.  
         [0029]     The state  410  generally comprises implementing design rules and technology rules as input files. The state  410  generally comprises a substep  410   a  and a substep  410   b . The substep  410   a  generally comprises splitting the tie up nets and/or the tie down nets. The tie up nets and the tie down nets are split to provide ESD protection and to ensure silicon robustness. The substep  410   b  generally comprises splitting the tie up nets and/or the tie down nets to relax congestion on the circuit  400  due to larger tie up nets and/or tie down nets. The state  412  generally comprises the end of the optimization. In the decision state  414 , if an engineering change order (ECO) is submitted, then the method  400  moves to step  408 . A new ESD optimization and tie up and tie down connection may be implemented, which may include the design changes requested in the ECO. If an ECO is not submitted, the method  400  is complete.  
         [0030]     The method  400  may control different voltage values of the voltage VSS of the design due to IR drops. In general, the IR drop is a placement based effect because the IR drop is related to the distribution of the power mesh/supply. The method  400  may take different types of supply voltages into account. A designer may assign logic to 1′b0 or 1′b1. Generally, 1′b0 is a verilog syntax for a net tied to ground. The verilog syntax for a net tied to the voltage VDD is 1′b1. The ESD optimization phase in the state  408  may determine which ESD protected tie up and/or tie down domains are connected to the gate of the transistors.  
         [0031]     The present invention may (i) eliminate high fanout nets implemented with the use of global tie up cells and global tie down cells, (ii) eliminate an ASIC designer&#39;s concerns with ESD protection of tied pins (iii) ensure the approach is correct by construction (iv) provide local tie up and local tie down cells instead of a global interconnect between local tie up and tie down cells to standard cells (v) eliminate IR drop (vi) ensure signal integrity and/or (vii) eliminate severe design closure issues.  
         [0032]     The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals.  
         [0033]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.