Abstract:
A source synchronous external memory device returns data to a memory controller of an electronic device with its own clock signal, which allows the returned data to be captured with a high degree of accuracy. The captured data must then be resynchronized with the clock signal which controls the other components of the electronic device. This problem is particularly acute in the case of high speed memory devices, such as DDR (Double Data Rate) memory devices, and similar memory devices. Test data is written to the external memory device, and is then read back several times. Attempts are made to resynchronize the captured data with the system clock, with different relative variations in the phase of the captured data and the system clock, in order to select a value for the relative phase, which allows for optimum resynchronization.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   Not Applicable 
   STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
   Not Applicable 
   REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK. 
   Not Applicable 
   BACKGROUND OF THE INVENTION 
   1. Technical Field of the Invention 
   This invention relates to a memory controller, and to a method for use in a memory controller, in order to synchronize captured data with a system clock signal. 
   2. Background of the Invention 
   In many electronic devices, it is common for a separate memory device to be provided. Data must then be written to, and read from, this separate memory device, by way of a memory interface. 
   A source synchronous external memory device returns data with its own clock signal, which allows the returned data to be captured with a high degree of accuracy. However, there then remains the problem of resynchronizing the captured data with the clock signal which controls the other components of the electronic device. This can be difficult because, although the clock signal accompanying the returned data is derived originally from the system clock, it is offset by a variable delay. 
   For example, this time delay depends upon the length of the data paths to and from the memory device. In addition, even in devices which have been manufactured to the same specification, the time delay can vary from one device to another, because of manufacturing process variations. Further, the time delay can vary in use of a single device, because of changes in the supply voltage and/or the operating temperature of the device. 
   The problem of resynchronization of the captured data with the system clock is particularly acute in the case of high speed memory devices, such as DDR (Double Data Rate) memory devices, and similar memory devices. 
   One solution to this problem is disclosed in the document ‘DDR SDRAM Controller MegaCore Function User Guide, version 1.2.0’, published by Altera Corporation, at pages 78-86, which describes a timing analysis to resynchronize the captured data with the system clock. 
   However, it is time consuming to perform this analysis. Further, changes in the time delay resulting from changes in the operating voltage and temperature cannot be compensated in this way. 
   BRIEF SUMMARY OF THE INVENTION 
   In accordance with the present invention, test data is written to the external memory device, and is then read back several times. Attempts are made to resynchronize the captured data with the system clock, with relative variations in the phase of the captured data and the system clock, in order to select a value for the relative phase, which allows for optimum resynchronization. 
   In accordance with another aspect of the present invention, there is provided a memory controller, which is adapted to determine the optimum relative phase of the captured data and the system clock, in order to achieve resynchronization. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block schematic diagram of a system incorporating a memory controller in accordance with the present invention. 
       FIG. 2  is a block schematic diagram showing a first embodiment of a memory controller in accordance with the invention. 
       FIG. 3  is a flow chart illustrating the method of operation of the memory controller of  FIG. 2 . 
       FIG. 4  is a block schematic diagram of a part of the memory controller of  FIG. 2 . 
       FIG. 5  is a block schematic diagram of a memory controller in accordance with a second embodiment of the invention. 
       FIG. 6  is a flow chart illustrating a method of operation of the memory controller of  FIG. 5 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  is a block schematic diagram of a part of an electronic device, incorporating a memory controller in accordance with the present invention. 
   In this illustrated embodiment of the invention, the electronic device  2  incorporates a field programmable gate array (FPGA)  4  and an external memory device  6 . 
   As is well known, a FPGA contains an array of logic elements, which can be configured to perform a desired set of functions. In this illustrated example, the FPGA is configured to include a processor (CPU)  8 , connected over a bus  10  to a memory controller  12 . The FPGA  4  also includes a phase locked loop (PLL)  14 , which can provide clock signals. The memory controller  12  is connected via a memory interface  16  to external pins  18  of the FPGA device  4 , and can thus be connected to the external memory device  6 . 
   It will however be appreciated that, although the memory controller  12  described herein is implemented in a FPGA, it can be implemented in other ways, either as a separate integrated circuit, or as part of any larger device. Further, although the memory controller  12  is connected in this example to a CPU  8  over a bus  10 , the memory controller according to the present invention can, if required, be connected directly to another device such as a processor. 
   In this illustrated example, the external memory device  6  is a Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM), although the memory controller of the present invention can be designed to operate with any source synchronous external memory device. In particular, the memory controller of the present invention has advantages when used in connection with any high speed memory device, including DDR-SDRAM, DDR2-SDRAM, Fast Cycle RAM (FCRAM-I/II), or Reduced Latency DRAM (RLDRAM-II). 
     FIG. 2  is a block schematic diagram of a memory controller, in accordance with a first embodiment of the present invention. 
   As is generally conventional, the memory controller  12  includes a capture register block  22 . More specifically, the memory controller  12  is connected to the external memory device  6  by way of a connector which may, for example, be 64 bits wide. In that case, where the external memory device is a DDR device, or a similar device as described above, there is a capture register block  22  for each pair of data bits, although  FIG. 2  shows only one capture register block in detail for ease of illustration. Again, as is conventional, the capture register block  22  includes a first capture register  22   a , a second capture register  22   b , and a third capture register  22   c.    
   The received data signal DQ is passed to the first and second capture registers  22   a ,  22   b , and the output of the second capture register  22   b  is passed to a third capture register  22   c . The second capture register  22   b  is clocked by a strobe signal DQS, while the first capture register  22   a  and the third capture register  22   c  are clocked by the inverse of the strobe signal DQS. As is known, the phase of the strobe signal DQS can be varied in a DQS control block  23  according to a known technique, in order to allow the data to be captured most accurately. This structure allows the memory controller to capture data at the double data rate. 
   The output of the first capture register  22   a  is passed to a first resynchronization register  24   a , whose output in turn passes to a further register  26   a . The output of the third capture register  22   c  is passed to a second resynchronization register  24   b , whose output in turn passes to a further register  26   b.    
   The outputs of the further registers  26   a ,  26   b  are supplied on an output line  28  as Read Data, and is also applied to a dynamic phase alignment control block  30 . 
   As mentioned above, there is a capture register block  22  for each pair of data bits received from the external memory device, and there is also a corresponding pair of resynchronization registers and further registers. The outputs from these further registers are combined with the outputs of the further registers  26   a ,  26   b  as an N-bit wide Read Data output. 
   The resynchronization registers  24   a ,  24   b  are clocked by a resynchronization clock signal, which is output from a delay control block  32 . The delay control block  32  generates the resynchronization clock signal on the basis of a clock signal supplied from the PLL  14 , modified under the control of the dynamic phase alignment control block  30 . The further registers  26   a ,  26   b  are clocked by the system clock, as generated by the PLL  14 , the system clock also being applied to the other components of the device  4 . 
   Write Data is supplied to the memory controller  12  on an input line  34 , which is connected to a multiplexer  36 . The multiplexer  36  also receives data from the dynamic phase alignment control block  30 , and is controlled by a control signal from the dynamic phase alignment control block  30 . The output of the multiplexer  36  is connected to a write controller  38 , which operates in a conventional way to supply data to be written to the external memory device  6 . 
   The dynamic phase alignment control block  30  is also connected to an output line  40 , on which it can supply control signals. 
     FIG. 3  is a flow chart illustrating a method of operation of the memory controller  12  shown in  FIG. 2 . 
   In step  50 , the device  4  is initialized and, in accordance with the invention, steps are taken to resynchronize the data captured by the capture register block  22  with the system clock, as it is used to clock the further registers  26   a ,  26   b.    
   Although, in this illustrated embodiment, the method is described as taking place on initialisation of the device  4 , the steps may be taken at intervals during the operation of the device, in order to ensure that the resynchronization is adapted to take account of any subsequent changes in the operating voltage and/or temperature of the device. 
   During the adaption process, it is not possible to write data to, or read data from the external memory device  6 , and a control signal is sent on the output line  40  to prevent access requests being made. 
   In step  52 , a test data pattern is written to the external memory device  6 , that is, a test data sequence is output from the dynamic phase alignment control block  30  to the multiplexer  36 , which is then controlled such that this test data sequence is sent to the write controller  38 , and written to the external memory device  6 . 
   As will be understood by the person skilled in the art, the test data pattern can be chosen in order to maximize the probability that changes in the phase of the resynchronization clock will lead to changes in the data pattern read back. For example, the test data pattern may contain a sequence in which the data value toggles between the two binary values and/or in which a relatively long sequence of one binary value is followed by the other binary value. 
   As mentioned previously, the capture register block  22  operates on the basis of a DQS signal, which is sent from the external memory device  6 , and is derived from the system clock frequency, but is delayed by an unknown time delay. Although the time delay is not known, it is possible to set upper and lower limits, defining a range within which the time delay must lie. The method according to the present invention is then concerned with determining the phase which allows the captured data to be resynchronized with the system clock most accurately. 
   The clock phase is applied in the resynchronization registers  24   a ,  24   b  which, as described above, are clocked by a resynchronization clock signal, output from the delay control block  32 . In accordance with the invention, the delay control block  32  is used to set various values for this time delay, and these time delays are tested in turn, in order to determine the value which allows the test sequence of data to be read back with the lowest probability of an error. 
   Thus, in step  54 , a trial value is set for the delay. The delay is set in the delay control block  32 , under the control of the dynamic phase alignment control block  30 . 
     FIG. 4  is a block schematic diagram, showing one possible form of the delay control block  32 . Specifically, the delay control block  32  shown in  FIG. 4  receives the clock signal from the PLL  14  on an input line  70 , and contains a series of delay elements  71 - 74 . In this illustrative example, there are four such delay elements, although in practice it will usually be more appropriate to provide more than this. The outputs from the first three delay elements  71 - 73  are passed to the next delay element, and are also passed to a multiplexer  76 . The output from the fourth delay element  74  is also passed to the multiplexer  76 . 
   The multiplexer  76  is controlled, by a control signal on a line  78 , received from the dynamic phase alignment control block  30 , to output one of these delayed signals on an output line  80  to the resynchronization registers  24   a ,  24   b . Thus, in step  54 , a control signal is sent from the dynamic phase alignment control block  30  to the multiplexer  76 , in order to apply a particular delay to the resynchronization clock signal applied to the resynchronization registers  24   a ,  24   b.    
   Then, in step  56 , the test sequence of data is read back from the external memory device  6 , and is supplied from the further registers  26   a ,  26   b  to the dynamic phase alignment control block  30 . The control block  30  can then compare the data read back with the data which was written to the external memory device, and to determine whether it contains any errors. Then, in step  58 , the control block  30  determines whether this trial value of the delay led to a ‘pass’, in which the data read back contains no errors, or to a ‘fail’, in which the data read back contains one or more errors. 
   In step  60 , the control block  30  determines whether all of the required trial values of the delay have been tested in this way. If so, the process passes to step  62  but, if there remain any trial values of the delay to be tested, the process returns to steps  54 , and the further trial value of the delay is tested. 
   When the process eventually reaches step  62 , the control block  30  determines which of the trial values should be used for the further operation of the device. 
   Provided that the trial values have been selected appropriately, it is likely that some of the trial values in a central part of the range will have led to a ‘pass’ condition, while other trial values, towards the two ends of the range, will have lead to a ‘fail’ condition. 
   In a preferred embodiment of the invention, the trial value of the delay which is then selected in step  62  is the trial value which is in the middle of the group of values leading to ‘pass’ conditions. Where there are an even number of trial values leading to ‘pass’ conditions, one of the two values in the middle of this group is selected. 
   When the delay value has been selected, and the adaption is complete, a control signal may be output on the line  40 , to indicate that data may now be written or read. At this point, normal operation of the device can continue, with the resynchronization registers  24   a ,  24   b  being clocked by the selected optimum resynchronization clock signal. 
     FIGS. 2 and 3  show an arrangement in which the resynchronization clock signal is obtained by applying different time delays to the clock signal received from the PLL  14 . However, it will be apparent that the same effect can be achieved by applying different phase shifts to the clock signal received from the PLL  14 . Further, in some cases, the PLL  14  will be adapted to produce multiple clock signals at the same frequency, but with different phases. In that case, the delay control block  32  may simply supply these different clock signals to the resynchronization registers  24   a ,  24   b  at different times to allow a clock signal with the optimum phase to be selected as described above. Further, the delay control block  32  may apply each of these different clock signals with different additional delays (or different additional phase shifts) at different times to allow a clock signal with the optimum phase to be selected as described above. 
     FIGS. 2 and 3  show an arrangement in which the optimum relative phase, between the captured data and the resynchronization clock, is determined by changing the phase of the clock.  FIG. 5  and y show an arrangement in which this is determined by changing the phase of the captured, data. 
   Thus,  FIG. 5  is a block schematic diagram of a memory controller  112 , in accordance with a second embodiment of the present invention. As is generally conventional, the memory controller  112  includes capture register blocks  122 . More specifically, the memory controller  112  is connected to the external memory device  6  by way of a connector which may, for example, be 64 bits wide. In that case, where the external memory device is a DDR device, or a similar device as described above, there is a capture register block  122  for each pair of data bits, although  FIG. 5  shows only one capture register block in detail for ease of illustration. Again, as is conventional, the capture register block  122  includes a first capture register  122   a , a second capture register  122   b , and a third capture register  122   c.    
   Again, as is conventional, the received data signal DQ is passed to the first and second capture registers  122   a ,  122   b , and the output of the second capture register  122   b  is passed to a third capture register  122   c . The second capture register  122   b  is clocked by a strobe signal DQS, while the first capture register  122   a  and the third capture register  122   c  are clocked by the inverse of the strobe signal DQS. As is known, the phase of the strobe signal DQS can be varied in a DQS control block  123  according to a known technique, in order to allow the data to be captured most accurately. This structure allows the memory controller to capture data at the double data rate. 
   The output of the first capture register  122   a  is passed to a first adaptive resynchronization register block  172   a , whose output in turn passes to a further register  126   a . The output of the third capture register  122   c  is passed to a second adaptive resynchronization register block  172   b , whose output in turn passes to a further register  126   b.    
   The outputs of the further registers  126   a ,  126   b  are supplied on an output line  128  as Read Data, and is also applied to a dynamic phase alignment control block  130 . 
   As mentioned above, there is a capture register block  122  for each pair of data bits received from the external memory device, and there is also a corresponding pair of adaptive resynchronization register blocks and further registers. The outputs from these further registers are combined with the outputs of the further registers  126   a ,  126   b  as an N-bit wide Read Data output. 
   The first adaptive resynchronization register block  172   a  receives the data output frond the first capture register  122   a . This data is passed through respective delay elements  174   a ,  176   a , having different delay values to respective resynchronization registers  181   a ,  180   a . Thus, the delay elements  174   a ,  176   a  apply different delays to their respective input signals.  FIG. 4  shows only two delay elements  174   a ,  176   a  and two resynchronization registers  181   a ,  180   a  for ease of illustration, although in practice there will be more than this. 
   The outputs from the resynchronization registers  181   a ,  180   a  are passed to a multiplexer  182   a , which operates under the control of the dynamic phase alignment control block  130 , as will be described in more detail below. The output from the multiplexer  182   a  passes to the further register  126   a.    
   The resynchronization registers  181   a ,  180   a  are clocked by a resynchronization clock, which is output from the PLL  114 . The further register  126   a  is clocked by the system clock, also as generated by the PLL  114 , the system clock also being applied to the other components of the device  4 . 
   Similarly, the second adaptive resynchronization register block  172   b  receives the data output from the third capture register  122   c . This data is passed through respective delay elements  174   b ,  176   b , having different delay values to respective resynchronization registers  181   b ,  180   b . Thus, the delay elements  174   b ,  176   b  apply different delays to their respective input signals.  FIG. 4  shows only two delay elements  174   b ,  176   b  and two resynchronization registers  181   b ,  180   b  for ease of illustration, although in practice there will be more than this. The delay element  174   b  applies the same delay as the delay element  174   a  in the block  172   a , and the delay element  176   b  applies the same delay as the delay element  176   a  in the block  172   a.    
   The outputs from the resynchronization registers  181   b ,  180   b  are passed to a multiplexer  182   b , which operates under the control of the dynamic phase alignment control block  130 , as will be described in more detail below. The output from the multiplexer  182   b  passes to the further register  126   b.    
   The resynchronization registers  181   b ,  180   b  are clocked by a resynchronization clock, which is output from the PLL  114 . The further register  126   b  is clocked by the system clock, also as generated by the PLL  114   
   Write Data is supplied to the memory controller  112  on an input line  134 , which is connected to a multiplexer  136 . The multiplexer  136  also receives data from the dynamic phase alignment control block  130 , and is controlled by a control signal from the dynamic phase alignment control block  130 . The output of the multiplexer  136  is connected to a write controller  138 , which operates in a conventional way to supply data to be written to the external memory device  6 . 
   The dynamic phase alignment control block  130  is also connected to an output line  140 , on which it can supply control signals. 
     FIG. 6  is a flow chart illustrating a method of operation of the memory controller  112  shown in  FIG. 5 . 
   In step  150 , the device  4  is initialized and, in accordance with the invention, steps are taken to resynchronize the data captured by the capture register blocks  122  with the system clock, as it is used to clock the further registers  126   a ,  126   b.    
   Although, in this illustrated embodiment, the method is described as taking place on initialisation of the device  4 , the steps may be taken at intervals during the operation of the device, in order to ensure that the adaption of the resynchronization takes account of any subsequent changes in the operating voltage and/or temperature of the device. 
   During the adaption process, it is not possible to write data to, or read data from the external memory device  6 , and a control signal is sent on the output line  140  to prevent access requests being made. 
   In step  152 , a test data pattern is written to the external memory device  6 , that is, a test data sequence is output from the dynamic phase alignment control block  130  to the multiplexer  136 , which is then controlled such that this test data sequence is sent to the write controller  138 , and written to the external memory device  6 . 
   As will be understood by the person skilled in the art, the test data pattern can be chosen in order to maximize the probability that changes in the phase of the resynchronization clock will lead to changes in the data pattern read back. For example, the test data pattern may contain a sequence in which the data value toggles between the two binary values and/or in which a relatively long sequence of one binary value is followed by the other binary value. 
   As mentioned previously, the capture register blocks  122  operate on the basis of a DQS signal, which is sent from the external memory device  6 , and is derived from the system clock frequency, but is delayed by an unknown time delay. Although the time delay is not known, it is possible to set upper and lower limits, defining a range within which the time delay must lie. The method according to the present invention is then concerned with determining the time delay which allows the captured data to be resynchronized with the system clock most accurately. 
   The delay is applied in the delay elements  174   a ,  176   a ,  174   b ,  176   b , and the resynchronization registers  181   a ,  180   a ,  181   b ,  180   b , which, as described above, are clocked by the resynchronization clock signal. The time delays applied by the delay elements  174   a ,  174   b , and by the delay elements  176   a ,  176   b , are tested in turn, in order to determine the value which allows the test sequence of data to be read back with the lowest probability of an error. 
   Thus, in step  154 , a trial value is set for the delay. Specifically, the multiplexers  182   a ,  182   b  are controlled by a control signal from the dynamic phase alignment control block  130 , to output the signal from a specific respective one of the resynchronization registers  181   a ,  180   a , or  181   b ,  180   b  as the case may be, to which a specific one of the delay values had been applied in the associated delay element  174   a ,  176   a , or  174   b ,  176   b.    
   Then, in step  156 , the test sequence of data is read back from the external memory device  6 , and is supplied from the further registers  126   a ,  126   b  to the dynamic phase alignment control block  130 . The control block  130  can then compare the data read back with the data which was written to the external memory device, and to determine whether it contains any errors. Then, in step  158 , the control block  130  determines whether this trial value of the delay led to a ‘pass’, in which the data read back contains no errors, or to a ‘fall’, in which the data read back contains one or more errors. 
   In step  160 , the control block  130  determines whether all of the required trial values of the delay have been tested in this way. If so, the process passes to step  162  but, if there remain any trial values of the delay to be tested, the process returns to steps  154 , and the further trial value of the delay is tested. 
   When the process eventually reaches step  162 , the control block  130  determines which of the trial values should be used for the further operation of the device. 
   Provided that the trial values have been selected appropriately, it is likely that some of the trial values in a central part of the range will have led to a ‘pass’ condition, while other trial values, towards the two ends of the range, will have lead to a ‘fail’ condition. 
   In a preferred embodiment of the invention, the trial value of the delay which is then selected in step  162  is the trial value which is in the middle of the group of values leading to ‘pass’ conditions. Where there are an even number of trial values leading to ‘pass’ conditions, one of the two values in the middle of this group is selected. 
   When the delay value has been selected, and the resynchronization is complete, a control signal may be output on the line  140 , to indicate that data may now be written or read. 
   There is therefore described a memory controller, and a method of operation thereof, which allows accurate resynchronization of captured data with a system clock.