Abstract:
The present invention provides a logic circuit which is formed by combination of bipolar transistors and CMOS transistors such that conduction of the bipolar transistors is controlled by the MOS transistors and an output load is charged/discharged by the conducting bipolar transistors. A logic part formed by combination of at least one or more NMOS transistors is provided between an output terminal and a low-potential power source, so that fall of output voltage in discharging is prompted by addition of discharge path through the logic part.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a logic circuit which is formed by combination of bipolar transistors and CMOS transistors. 
     2. Description of the Prior Art 
     As is generally known, there are many logic circuits formed by combining bipolar transistors and CMOS transistors. FIG. 4 shows an inverter circuit as such a well-known logic circuit which is disclosed in Japanese Patent Laying-Open Gazette No. 11034/1984. Referring to FIG. 4, a PMOS transistor T 1  has a gate connected with an input terminal IN, a source connected with a high-potential power source 1 and a drain connected with an end of a first resistor R 1 . Another end of the first resistor R 1  is connected to an output terminal OUT. An NMOS transistor T 2  has a gate connected with the input terminal IN, a drain connected with the output terminal OUT and a source connected with an end of a second resistor R 2  . Another end of the second resistor R 2  is connected to a low-potential power source 2 of the ground level. A first NPN transistor T 3  is provided for charging an output load C and a second NPN transistor T 4  is provided for discharging the output load C. The first NPN transistor T 3  has a base connected to the drain of the PMOS transistor T 1 , a collector connected to the high-potential power source 1 and an emitter connected to the output terminal OUT. The second NPN transistor T 4  has a base connected to the source of the NMOS transistor T 2 , a collector connected to the output terminal OUT and an emitter connected to the low-potential power source 2. The output load C is not provided as an actural element, but expressed as the total sum of output capacity parasitic to the inverter itself and input capacity of a gate connected to a subsequent stage of the inverter. 
     When input voltage V IN  of a low level (GND level) is applied to the input terminal IN in the aforementioned circuit, the NMOS transistor T 2  and the NPN transistor T 4  are turned off while the PMOS transistor T 1  is turned on. Since the PMOS transistor T 1  is thus turned on, the high-potential power source 1 supplies current to the base of the NPN transistor T 3  and the first resistor R 1 , to turn on the NPN transistor T 3 . Thus, the output load C between the output terminal OUT and the low-potential power source 2 is charged. 
     Assuming that V DD  represents source voltage of the high-potential power source 1 and V BE (T3) represents forward voltage of the NPN transistor T 3  in the aforementioned process of charging the output load C, charging of the output load C is mainly performed through a current flow path by the NPN transistor T 3  in an interval T OUT1  as shown in FIG. 5 in which the potential of the output terminal OUT, i.e., output voltage V OUT  is: 
     
         V.sub.OUT &lt;V.sub.DD -V.sub.BE(T3)                          ( 1) 
    
     When the current voltage V OUT  becomes: 
     
         V.sub.OUT ≧V.sub.DD -V.sub.BE(T3)                   ( 2) 
    
     in an interval T OUT2  as shown in FIG. 5, the NPN transistor T 3  is turned off and the output load C is charged through a path of the PMOS transistor T 1  and the resistor R 1 . Thus, the output voltage V OUT  is finally raised up to V DD . 
     Then, when input voltage V IN  of a high level (V DD ) is applied to the input terminal IN, the PMOS transistor T 1  and the NPN transistor T 3  are turned off while the NMOS transistor T 2  is turned on. Since the NMOB transistor T 2  is thus turned on, charges in the output load C flow to the base of the NPN transistor T 4  and the second resistor R 2  through the NMOS transistor T 2 . Thus, the NPN transistor T 4  is turned on to rapidly discharge the output load C. 
     Assuming that V BE (T4) represents forward voltage of the NPN transistor T 4  in the aforementioned process of discharging the output load C, discharging is performed mainly through a current flow path by the NPN transistor T 4  in an interval T IN1  as shown in FIG. 5, in which the output V OUT  is: 
     
         V.sub.OUT ≧V.sub.BE(T4)                             ( 3) 
    
     When the output voltage V OUT  becomes: 
     
         V.sub.OUT &lt;V.sub.BE(T4)                                    ( 4) 
    
     in an interval T IN2  as shown in FIG. 5, the NPN transistor T 4  is turned off and discharging is performed through a path of the NMOS transistor T 2  and the resistor R 2 . Thus, the output voltage V OUT  is finally lowered to the GND level. 
     As obvious from the above description, the waveform in rise time of the output voltage V OUT  is substantially determined by the value of resistance of the PMOS transistor T 1  in ON-state and the time constant on the basis of the resistance R 1  and the capacity of the output load C in a range of V OUT  ≧V DD  -V BE (T3) in this inverter circuit. Further, the waveform in fall time of the output voltage V OUT  is substantially determined by the value of resistance of the NMOS transistor T 2  in ON-state and the time constant on the basis of the resistance R 2  and the capacity of the output load C in a range of V OUT  ≦V BE (T4). 
     In the conventional logic circuit as hereinabove described, it takes time for the output voltage V OUT  to reach the V DD  level or the GND level in the rise or fall time. When the input voltage V IN  is increased in frequency, therefore, the input voltage V IN  may be changed before the output voltage V OUT  reaches the GND or V DD  level as shown in FIG. 6 whereby no sufficient output amplitude can be obtained with respect to input amplitude. Thus, if the same logic circuits are connected with each other in multiple stages, for example, decrease in input amplitude to a subsequent stage causes reduction in noise margin in the subsequent stage as shown by symbol A in FIG. 6, or increase in current flowing between the high-potential power source 1 and the low-potential power source 2 through the transistors T 1  and T 2  in the subsequent stage. 
     In order to avoid this, it may be considered to reduce values of the resistances R 1  and R 2  while increasing current flow capacity of the PMOS transistor T 1  and the NMOS transistor T 2 . However, such means leads to increase in current flowing between the high-potential power source 1 and the low-potential power source 2 through the transistors T 1  and T 2  in operation of the logic circuit as well as to increase in transistor area, whereby an integrated circuit formed through the logic circuit is increased in power consumption and chip area. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a logic circuit which is formed by combining bipolar transistors and MOS transistors. 
     A logic circuit according to a first invention comprises an input terminal; an output terminal; a high-potential power source; a low-potential power source; a PMOS transistor having a gate connected to the input terminal and a source connected to the high-potential power source; a first resistor having an end connected to the drain of the PMOS transistor and another end connected to the output terminal; a first NPN transistor having a base connected to a node between the first resistor and the PMOS transistor, a collector connected to the high-potential power source and an emitter connected to the output terminal; a first NMOS transistor having a gate connected to the input terminal and a drain connected to the output terminal; a second resistor having an end connected to the source of the NMOS transistor and another end connected to the low-potential power source; a second NPN transistor having a base connected to a node between the second resistor and the first NMOS transistor, a collector connected to the output terminal and an emitter connected to the low-potential power source; and a second NMOS transistor having a gate connected to the input terminal, a drain connected to the output terminal and a source connected to the low-potential power source. 
     A logic circuit according to a second invention comprises a plurality of input terminals; an output terminal; a high-potential power source; a low-potential power source; a first logic part consisting of a circuit member having an end connected to the high-potential source and being formed by combination of a plurality of PMOS transistors whose gates are connected to the input terminals respectively; a first resistor having an end connected to the other end of the circuit member of the first logic part and another end connected to the output terminal; a first NPN transistor having a base connected to a node between the first resistor and the first logic part, a collector connected to the high-potential power source and an emitter connected to the output terminal; a second logic part consisting of a circuit member having an end connected to the output terminal and being so formed as to be a conducting state when the first logic part is in a non-conducting state by combination of a plurality of NMOS transistors whose gates are connected to the respective input terminals; a second resistor having an end connected to the other end of the circuit member of the second logic part and another end connected to the low-potential power source: a second NPN transistor having a base connected to a node between the second resistor and the second logic part, a collector connected to the output terminal and an emitter connected to the low-potential power source; and a third logic part consisting of a circuit member parallel connected between the collector and the emitter of the second NPN transistor and being so formed as to be a conducting state when the first logic part is in a nonconducting state by combination of a plurality of NMOS transistors whose gates are connected to the input terminals respectively. 
     Accordingly, a principal object of the present invention is to provide a logic circuit whose output voltage quickly falls to enable high speed operation. 
     Another object of the present invention is to provide a logic circuit which causes no reduction in noise margin following increase in operating speed. 
     Still another object of the present invention is to provide a logic circuit which causes no increase in power consumption and chip area upon application to an integrated circuit. 
     According to the logic circuit of the first invention, the first NMOS transistor and the second NPN transistor are turned on when input voltage of a high level is applied to the input terminal. Thus, charges are discharged from an output load provided between the output terminal and the low-potential power source, so that the output voltage falls. The second NMOS transistor connected between the output terminal and the low-potential power source is also turned on in such fall time of the output voltage, whereby falling of the output voltage is prompted by addition of a discharge path through the second NMOS transistor. 
     According to the logic circuit of the second invention, the second logic part and the second NPN transistor enter conducting states when the input terminals are supplied with input voltage for bringing the first logic part into a nonconducting state. Thus, charges are discharged from an output load provided between the output terminal and the low-potential power source, Whereby the output voltage falls. The third logic part connected between the output terminal and the low-potential power source also enters a conducting state in such fall time of the output voltage, whereby falling of the output voltage is prompted by addition of a discharge path through the third logic part. 
     These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an embodiment of a logic circuit according to the present invention; 
     FIG. 2 is a graph showing current characteristics of the logic circuit in a discharge process; 
     FIG. 3 is a circuit diagram showing another embodiment of the logic circuit according to the present invention; 
     FIG. 4 is a circuit diagram showing a conventional logic circuit; 
     FIG. 5 is a waveform diagram in low-speed operation of the conventional logic circuit; and 
     FIG. 6 is a waveform diagram in high-speed operation of the conventional logic circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a circuit diagram showing an embodiment of a logic circuit according to the present invention. Referring to FIG. 1, a high-potential power source 1, a low-potential power source 2, a PMOS transistor T 1 , an NMOS transistor T 2 , NPN transistors T 3  and T 4 , an input terminal IN, an output terminal OUT and resistors R 1  and R 2  are absolutely identical to those of the conventional inverter circuit as hereinabove described. 
     The inverter circuit as shown in FIG. 1 is newly provided with an NMOS transistor T 5 . This NMOS transistor T 5  has a gate connected with the input terminal IN, a drain connected to the output terminal OUT and a source connected to the low-potential power source 2. 
     In this inverter circuit, operation upon application of low-level input voltage V IN  is similar to that of the aforementioned conventional circuit. Namely, the NMOS transistors T 2  and T 5  and the NPN transistor T 4  are turned off while the PMOS transistor T 1  is turned on. Thus, the high-potential power source 1 supplies current to the base of the NPN transistor T 3  and the resistor R 1  to turn on the NPN transistor T 3 , thereby to charge an output load C until the output voltage V OUT  becomes a V DD  level (i.e., high level). 
     When high-level input voltage V IN  is applied to the input terminal IN, the PMOS transistor T 1  and the NPN transistor T 3  are turned off while the NMOS transistors T 2  and T 5  are turned on. Thus, charges at the output load C are discharged through the NMOS transistors T 2  and T 5 , and the NPN transistor T 4  is also turned onto that the output load C is rapidly discharged. When the potential of the output terminal OUT, i.e. the output voltage V OUT  is lager than base-to-emitter forward voltage V BE (T4) of the NPN transistor T 4 , the NFN transistor T 4  is turned off. However, even if the NPN transistor T is thus turned off, the discharge speed is not reduced due to presence of a discharge path through the NMOS transistor T 5  and a discharge path through the NMOS transistor T 2  and the resistor R 2 , whereby the output voltage V OUT  is rapidly lowered to the GND level. 
     FIG. 2 illustrates relation between the output voltage V OUT  and collector current I C  of the NPN transistor T 4 , current I R  flowing through the resistor R 2  and drain current ID (gate-to-source voltage V GS ) =V DD ) of the NMOS transistor T 5  in the aforementioned process of discharging the output load C. It is obvious from FIG. 2 that the NMOS transistor T 5  can sufficiently contribute to discharging even if the output voltage V OUT  goes low, by setting the current characteristic of the NMOS transistor T 5  so that I D  is higher in current value than P at a level of the output voltage V OUT  corresponding to an intersection P between I C  and I R . Namely, operation similar to that of the conventional circuit is performed until the output voltage V OUT  is lowered to a level approximate to the base-to-emitter forward voltage V BE (T4) of the NPN transistor T 4  upon the falling of the output voltage V OUT . When the charges at the output load C are discharged mainly as the collector current I C  of the NPN transistor T 4  and the output voltage V OUT  goes lower than V BE (T4), the ration of discharge current flowing as the drain current I D  of the NMOS transistor T 5  is increased. Thus, the output voltage V OUT  is lowered to the GND level at a speed higher than that in the conventional circuit. 
     Since the NMOS transistor T 5  is parallely connected to the series circuit of the NMOS transistor T 2  and the resistor R 2  in this inverter circuit, discharging can be started in earlier timing by a single-state threshold value of the NMOS transistor T 5  as compared with the conventional case in which discharging is controlled by double-stage threshold values of the NMOS transistor T 2  and the NPN transistor T 4  . The operating speed in the falling of the output voltage V OUT  is increased also in this point. Since the operating speed in the falling of the output voltage V OUT  is thus increased, sufficient output amplitude can be obtained even if the input voltage V IN  is increased in frequency. Therefore, no input amplitude to a subsequent stage is reduced in case of connecting the same logic circuits in multiple stages. Thus, reduction in noise margin and increase in current flowing between the high-potential power source 1 and the low-potential power source 2 through the transistors T 1  and T 2  can be prevented in the subsequent stage. 
     FIG. 3 is a circuit diagram showing another embodiment, in which the resent invention is applied to a two-input NAND gate. This logic circuit is provided with two input terminals IN 1  and I 2 . Further, the transistors T 1 , T 2  and T 5  as shown in FIG. 1 are replaced by first to third logic parts 3, 4 and 5 respectively. The first logic part 3 is formed by two PMOS transistors Ti I  and T 6  which are connected in parallel with each other. The PMOS transistors T 1  and T 6  have sources connected to a high-potential power source 1, and drains connected to a resistor R 1 . Further, the PMOS transistor T 1  has a gate connected to the first input terminal IN l , while the PMOS transistor T 6  has a gate connected to the second input terminal IN 2 . The second logic part 4 is formed by two NMOS transistors T 2  and T 7 , which are connected in series with each other. Namely, the source of the NMOS transistor T 2  is connected with the drain of the NMOS transistor T 7 . The NMOS transistor T 2  has a drain connected to the output terminal OUT, while the NMOS transistor T 7  has a source connected to the resistor R 2 . Further, the NMOS transistor T 2  has a gate connected to the first input terminal IN 1 , while the NMOS transistor T 7  has a gate connected to the second input terminal IN 2 . The third logic part 5 is formed by two NMOS transistors T 5  and T 8  which are connected in series with each other. Namely, the source of the NMOS transistor T 5  is connected with the drain of the NMOS transistor T 8 . The NMOS transistor T 5  has a drain connected to the output terminal OUT, while the NMOS transistor T 8  has a source connected to the low-potential power source 2. Further, the NMOS transistor T 5  has a gate connected to the first input terminal IN 1 , while the NMOS transistor T 8  has a gate connected to the second input terminal IN 2 . Other structure is similar to that of the embodiment as shown in FIG. 1. 
     When high-level input voltages V IN1  and V IN2  are applied to both of the first and second input terminals IN 1  and IN 2  in this two-input NAND gate, the two PMOS transistors T 1  and T 6   forming the first logic part 3 and the NPN transistor T 3  are turned off while both of the two NMOS transistors T 2  and T 7  forming the second logic part 4 and both of the two NMOS transistors T 5  and T 8  forming the third logic part 5 are turned on. Thus, charges at the output load C are discharged through the second and third logic parts 4 and 5, and the NPN transistor T 4  is also turned on to facilitate rapid discharging of the output load C. Then, the NPN transistor T 4  is turned off when the potential at the output terminal OUT, i.e., the output voltage V OUT  becomes lower than the base-to-emitter forward voltage V BE (T4) of the NPN transistor T 4 . However, even if the NPN transistor T 4  is thus turned off, the discharge speed is not reduced due to presence of the discharge path through the third logic part 5 and the discharge path through the second logic part 4 and the resistor R 2 , and the output voltage V OUT  is rapidly lowered to the GND level. 
     When, on the other hand, combination of the input voltages V IN1  and V IN2  applied to the two input terminals IN 1  and IN 2  is (H, L), (L, H) or (L, L), the operation is made as follows: At least one of the two NMOS transistors T 2  and T 7  forming the second logic part 4 is turned off, to cut off the electric path of the second logic part 4. Further, at least one of the two NMOS transistors T 5  and T 8  forming the third logic part 5 is turned off, to cut off the electric path of the third logic part 8. On the other hand, at least one of the two PMOS transistors T 1  and T 6  forming the first logic part 3 is turned on, whereby the electric path of the first logic part 3 is a conducting state. Thus, the high-potential power source 1 supplies current to the base of the NPN transistor T 3  and the resistor R 1  so that the NPN transistor T 3  is turned on. The output load C is thus charged until the output voltage V OUT  becomes the V DD  level (i.e., high level). 
     Although the two PMOS transistors T 1  and T 6  are parallely connected to form the first logic part 3, the two PMOS transistors T 1  and T 6  may be serially connected to form the first logic part 3. In this case, it is necessary to form the second logic part 4 by parallely connecting the two NMOS transistors T 2  and T 7 , and it is necessary to form the third logic part 5 by parallely connecting the two NMOS transistors T 5  and T 8 . Such a logic circuit forms a two-input NOR gate. 
     Although each of the number for the input terminals and those for the transistors forming the first to third logic parts 3 to 5 is set at two, such number may be set at three or more. 
     Further, the number and connecting relation of the PMOS transistors forming the first logic part 3 are not particularly restricted, while the numbers of the NMOS transistors forming the second and third logic parts 4 and 5 and connecting relation thereof are not particularly restricted. However, connecting relation between the first logic part 3 and the second and third logic parts 4 and 5 must be so set that the former must be in a cutoff state when the latter is in a conducting state, and vice versa. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.