Abstract:
The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly. During the time of no input of the differential signal, the threshold adjustment control section changes the first detection level adjustment signal so that the threshold voltage monotonically increases or decreases until the detection signal is inverted, to determine the first detection level adjustment signal that makes the threshold voltage appropriate, and outputs the determined signal.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to a device for receiving digital data, and more particularly, to a signal detection circuit for detecting presence/absence of a reception signal.  
         [0002]     In serial communications, a signal detection circuit for detecting whether or not a prescribed signal is being input is often used. Such a signal detection circuit determines that an input signal is valid if the absolute value of the voltage of the input signal is equal to or more than a predetermined value and is not valid if the absolute value is less than the predetermined value. In Universal Serial Bus (USB) and Serial AT Attachment (serial ATA), the signal detection circuit is used for a return sequence from an initialize sequence and a power management state. In particular, in Serial ATA, the signal detection circuit is used for detecting an out-of-band (OOB) signal, in addition to detecting the signal state during communications.  
         [0003]     The OOB signal is a signal having a fixed-length time period during which a burst signal is transmitted (burst time period) and a non-signal time period repeated alternately, and meaning is given to the lengths of the burst time period and the non-signal time period and the number of times of the repetition. Such an OOB signal is used during initialization and power management.  
         [0004]      FIG. 8  is a circuit diagram of a conventional signal detection circuit, which is one described in the Serial ATA standards. The signal detection circuit of  FIG. 8  detects whether or not the voltage between input signals DRX and NDRX is equal to or more than a predetermined value, and outputs the detection result as a squelch signal SQOUTA.  
         [0005]      FIG. 3  shows an example of the squelch signal obtainable in an ideal case. A squelch signal SQOUT in  FIG. 3  goes high in correspondence with the burst time period and goes low during the non-signal time period.  
         [0006]     A signal detection circuit that outputs a squelch signal required in USB 2.0 Standard is disclosed in Japanese Laid-Open Patent Publication No. 2003-198392, for example. This circuit has a merit that the input signal is less dependent on a common mode voltage and the allowable voltage range of the input signal is wide.  
         [0007]     For a signal detection circuit required to receive a high-frequency signal and respond at high speed, like a signal detection circuit used in Serial ATA and the like, it is necessary to set the voltage used as the reference during detection (threshold value) appropriately considering the signal detection characteristics in high-frequency environments. If the threshold value is not appropriate, the detection result will be as described below.  
         [0008]      FIG. 9A  is a graph showing a squelch signal generated when the input signals have noise and the threshold value is low.  FIG. 9B  is a graph showing a squelch signal generated when the input signals have noise and the threshold voltage is high.  
         [0009]     If the threshold value is set excessively low in the signal detection circuit of  FIG. 8 , noise in the input signals DRX and NDRX will be detected erroneously, resulting in output of the squelch signal SQOUTA as the detection result as shown in  FIG. 9A . On the contrary, if the threshold voltage is set excessively high, high-frequency components of the input signals DRX and NDRX will fail to be detected, resulting in failure in detection of an input signal although the input signals DRX and NDRX are input, as shown in  FIG. 9B .  
         [0010]     As another problem, the signal detection circuit is provided with a comparator and transistors constituting the comparator vary in threshold value. Therefore, a given threshold value, if set for signal detection circuits, is not necessarily appropriate, and the detection result may vary among the signal detection circuits.  
       SUMMARY OF THE INVENTION  
       [0011]     An object of the present invention is avoiding a variation in detection result among signal detection circuits.  
         [0012]     According to the present invention, during the time of no input of a differential signal into the comparator, the threshold voltage of a comparator is increased or decreased until a detection signal from the comparator is inverted, to thereby make the threshold voltage appropriate.  
         [0013]     To state more specifically, the signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly, wherein, during the time of no input of the differential signal, the threshold adjustment control section changes the first detection level adjustment signal so that the threshold voltage monotonically increases or decreases until the detection signal is inverted, to determine the first detection level adjustment signal that makes the threshold voltage appropriate, and outputs the determined signal.  
         [0014]     The present invention suppresses a variation in detection result among signal detection circuits, and thus is useful for a signal detection circuit, such as a squelch circuit for detecting presence/absence of a reception signal, particularly in the case of handling a small-amplitude input signal and requiring high-speed response.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  is a block diagram of a signal detection circuit of the first embodiment of the present invention.  
         [0016]      FIG. 2  is a timing chart showing an example of change of signals during adjustment of the threshold voltage of a comparator in the signal detection circuit of  FIG. 1 .  
         [0017]      FIG. 3  is a timing chart of signals in the signal detection circuit of  FIG. 1  in an ideal case.  
         [0018]      FIG. 4  is a block diagram of a signal detection circuit of the first alteration.  
         [0019]      FIGS. 5A and 5B  are timing charts showing examples of change of signals during adjustment of the threshold voltage of a comparator in the signal detection circuit of  FIG. 4 .  
         [0020]      FIG. 6  is a block diagram of a signal detection circuit of the fourth alteration.  
         [0021]      FIG. 7  is a block diagram of a signal detection circuit of the second embodiment of the present invention.  
         [0022]      FIG. 8  is a circuit diagram of a conventional signal detection circuit.  
         [0023]      FIG. 9A  is a graph showing a squelch signal generated when the input signals have noise and the threshold voltage is low.  FIG. 9B  is a graph showing a squelch signal generated when the input signals have noise and the threshold voltage is high. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]     Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0025]     (First Embodiment)  
         [0026]      FIG. 1  is a block diagram of a signal detection circuit of the first embodiment of the present invention. The signal detection circuit of  FIG. 1  includes a comparator  12  as the comparison section, a detection section  20  and a threshold adjustment control section  32 . The detection section  20  includes an inverter  22 , an AND gate  23 , a diode  24 , a capacitor  26 , a resistance  27  and a buffer  28 .  
         [0027]     Two input signals DRX and NDRX constitute a differential signal. The input signal DRX is input into a positive input terminal + of the comparator  12 , the input signal NDRX into a negative input terminal − thereof, and a detection level adjustment signal OF 1  into a reference input terminal VREF thereof.  
         [0028]     The comparator  12  sets its threshold voltage in response to the detection level adjustment signal OF 1 . Assume herein that the comparator  12  sets a higher threshold voltage as the potential of the detection level adjustment signal OF 1  is higher.  
         [0029]     The comparator  12 , which exhibits hysteresis, compares the absolute value of the difference between the input signals DRX and NDRX with the threshold voltage to detect presence/absence of an input signal, and outputs the detection result to the inverter  22  and the AND gate  23  as a detection signal CM. Specifically, the comparator  12  outputs a high potential (hereinafter, referred to as “H”) indicating that an input signal has been detected if |DRX−NDRX| is equal to or more than a threshold voltage set for the time of input voltage increase, while outputting a low potential (hereinafter, referred to as “L”) indicating that no input signal has been detected if |DRX−NDRX| is less than a threshold voltage set for the time of input voltage decrease. In the following description, for simplification, the threshold voltage for the time of input voltage increase and the threshold voltage for the time of input voltage decrease are assumed identical to each other.  
         [0030]     The detection section  20  detects whether or not the level of the detection signal CM changes repeatedly, and outputs the detection result as a squelch signal SQOUT. The inverter  22  of the detection section  20  inverts the detection signal CM and sends the inverted signal to the AND gate  23  with a slight delay. The AND gate  23  therefore outputs “H” to the diode  24  only at the instant immediately after a change of the detection signal CM from “L” to “H”. The capacitor  26  accumulates charge when the output from the AND gate  23  is “H”. Accordingly, the input level of the buffer  28  rises when the output level of the comparator  12  changes. The resistance  27  gradually releases the charge in the capacitor  26 .  
         [0031]     The buffer  28 , which exhibits hysteresis, outputs “H” when the input signal becomes equal to or higher than a detection level for the time of input voltage increase, and outputs “L” if the input signal becomes lower than a detection level for the time of input signal decrease, externally as the squelch signal SQOUT.  
         [0032]     The threshold adjustment control section  32  receives the detection signal CM output from the comparator  12 , a power-on signal PON indicating that the signal detection circuit has just been powered on, and a hot plug signal PLG. The hot plug signal PLG indicates that a cable for transmitting the differential signal composed of the input signals DRX and NDRX has been connected. Specifically, lines for transmitting the differential signal and a line for transmitting the hot plug signal PLG constitute one cable, and once the lines for transmitting the differential signal are connected to the signal detection circuit of  FIG. 1 , the line for transmitting the hot plug signal PLG is also connected, to allow the threshold adjustment control section  32  to receive the hot plug signal PLG.  
         [0033]     The input signals DRX and NDRX are not yet input at the time immediately after the input of the power-on signal PON and the hot plug signal PLG Therefore, the threshold adjustment control section  32  starts adjustment of the threshold voltage of the comparator  12  upon receiving the power-on signal PON or the hot plug signal PLG.  
         [0034]      FIG. 2  is a timing chart showing an example of change of signals during the adjustment of the threshold voltage of the comparator  12 .  FIG. 2  shows a non-signal state in which the input signals DRX and NDRX are not input (the voltage between the input signals DRX and NDRX is roughly zero), during the time immediately after input of the power-on signal PON, for example. The threshold adjustment control section  32  first sets the potential of the detection level adjustment signal OF 1  at a predetermined initial value VTH. If the initial value VTH is a value close to zero, the detection signal CM will go “H”.  
         [0035]     In the case that the detection signal CM is made “H” as described above, the threshold adjustment control section  32  then raises the potential of the detection level adjustment signal OF 1  so as to increase the threshold voltage of the comparator  12 . The threshold adjustment control section  32  may raise the potential of the detection level adjustment signal OF 1  step by step as shown in  FIG. 2 , or may raise the signal in a smoother manner.  
         [0036]     The detection signal CM goes “L” when the detection level adjustment signal OF 1  reaches a potential TH. Determining that the potential TH is appropriate as the potential of the detection level adjustment signal OF 1 , the threshold adjustment control section  32  fixes the detection level adjustment signal OF 1  at the potential TH.  
         [0037]      FIG. 3  is a timing chart of signals in the signal detection circuit of  FIG. 1  in an ideal case. When the amplitude of the differential signal is equal to or more than the threshold voltage VT, the detection signal CM goes “H” and thus the squelch signal SQOUT as shown in  FIG. 3  is obtained.  
         [0038]     By use of the thus-obtained detection level adjustment signal OF 1 , erroneous detection of noise and failure in detection of high-frequency components can be avoided, and thus a correct squelch signal SQOUT can be obtained.  
         [0039]     (First Alteration)  
         [0040]      FIG. 4  is a block diagram of a signal detection circuit of the first alteration. The signal detection circuit of  FIG. 4  includes a threshold adjustment control section  232  in place of the threshold adjustment control section  32  and further includes a memory  234  in addition to the components of the signal detection circuit of  FIG. 1 .  
         [0041]     An initial value for the detection level adjustment signal OF 1  is stored in the memory  234 . The initial value may be a value appropriate as the detection level adjustment signal OF 1 , determined at the time of design of the signal detection circuit of  FIG. 4 , for example.  
         [0042]      FIGS. 5A and 5B  are timing charts showing examples of change of signals during the adjustment of the threshold voltage of the comparator  12  in the signal detection circuit of  FIG. 4 . During the time of non-signal input, the threshold adjustment control section  232  reads an initial value from the memory  234  to use the value as the initial value DFT of the detection level adjustment signal OF 1 . In this adjustment, when the detection signal CM is “L”, the threshold adjustment control section  232  lowers the potential of the detection level adjustment signal OF 1  as shown in  FIG. 5A  so as to decrease the threshold voltage of the comparator  12 .  
         [0043]     At the time when the detection signal CM goes “H”, the threshold voltage of the comparator  12  has fallen a little excessively. Therefore, the threshold adjustment control section  232  raises the potential of the detection level adjustment signal OF 1  back to an immediately preceding value TH 1 .  
         [0044]     Alternatively, the threshold adjustment control section  232  may continuously lower the potential of the detection level adjustment signal OF 1  within a predetermined range and then adjust the potential of the detection level adjustment signal OF 1  to the appropriate value TH 1 .  
         [0045]     When the detection signal CM is “H” at the setting of the initial value DFT for the detection level adjustment signal OF 1 , the threshold adjustment control section  232  raises the potential of the detection level adjustment signal OF 1  as shown in  FIG. 5B .  
         [0046]     The detection signal CM goes “L” when the detection level adjustment signal OF 1  reaches a potential TH 2 . The threshold adjustment control section  232  therefore fixes the detection level adjustment signal OF 1  at the potential TH 2 .  
         [0047]     As described above, in the signal detection circuit of  FIG. 4 , a value appropriate as the detection level adjustment signal OF 1 , determined at the time of design, is used as the initial value for the adjustment of the threshold voltage. Accordingly, the time required for the adjustment can be shortened.  
         [0048]     (Second Alteration)  
         [0049]     The threshold voltage of the comparator  12  may be adjusted as described above with reference to  FIGS. 5A and 5B  at the time of pre-shipment examination after fabrication of the signal detection circuit of  FIG. 4 , and the resultant value of the detection level adjustment signal OF 1  may be written in the memory  234 . At the time of actual use of the signal detection circuit, the threshold adjustment control section  232  uses the value read from the memory  234  as the value of the detection level adjustment signal OF 1 .  
         [0050]     Otherwise, the value read from the memory  234  may be used as the initial value of the detection level adjustment signal OF 1 , to further adjust the threshold voltage of the comparator  12  as shown in  FIGS. 5A and 5B .  
         [0051]     (Third Alteration)  
         [0052]     The detection signal CM may sometimes remain “H” or “L” despite of the adjustment of the threshold voltage of the comparator  12  as described with reference to  FIGS. 5A and 5B  at the time of pre-shipment examination after fabrication of the signal detection circuit of  FIG. 4 . In this case, such a signal detection circuit, which will be unable to detect a signal, should be regarded as a defective and be blocked from being shipped.  
         [0053]     In view of the above, in the above case, the threshold adjustment control section  232  writes a specific value in the memory  234 . The specific value may be the maximum or minimum value in an adjustment range of the detection level adjustment signal OF 1 , or a value outside the adjustment range.  
         [0054]     After the examination, whether or not the signal detection circuit is a defective is clarified by reading the value written in the memory  234 , and in this way, shipment of a defective can be blocked.  
         [0055]     (Fourth Alteration)  
         [0056]      FIG. 6  is a block diagram of a signal detection circuit of the fourth alteration. The signal detection circuit of  FIG. 6  includes a plural sampling detection circuit  336  in addition to the components of the signal detection circuit of  FIG. 1 .  
         [0057]     The plural sampling detection circuit  336  repeats sampling of the detection signal CM, and determines whether or not the detection signal CM indicates that an input signal has been detected, every predetermined number of times of sampling. For example, if all sample values are “L”, the plural sampling detection circuit  336  determines that a differential signal has not been detected and outputs “L” to the threshold adjustment control section  32  as a plural sampling detection signal OTG. If any one of sample values is “H”, “H” is output.  
         [0058]     In the signal detection circuit of  FIG. 6 , the reliability of the plural sampling detection signal OTG given to the threshold adjustment control section  32  can be enhanced. For example, even in the case that the detection signal CM repeats “H” and “L” alternately during the adjustment of the threshold voltage, correct adjustment of the threshold voltage can be attained.  
         [0059]     The plural sampling detection circuit  336  may output “L” as the plural sampling detection signal OTG only when the sample value is consecutively “L” for a predetermined number of times.  
         [0060]     (Second Embodiment)  
         [0061]     FIG  7  is a block diagram of a signal detection circuit of the second embodiment of the present invention. The signal detection circuit of  FIG. 7  includes a comparison section  410 , the detection section  20  and a threshold adjustment control section  432 . The comparison section  410  includes comparators  411  and  412 , an OR gate  413  and voltage generators  416  and  417 . The detection section  20  is the same as that described ab with reference to  FIG. 1  and therefore description thereof is omitted here.  
         [0062]     The threshold adjustment control section  432  generates detection level adjustment signals OF 1  and OF 2  in response to the detection signal CM and outputs the signals to the voltage generators  416  and  417 , respectively. The voltage generator  416  generates a signal corresponding to the detection level adjustment signal OF 1  and outputs the resultant signal to a reference input terminal of the comparator  411 . The voltage generator  417  generates a signal corresponding to the detection level adjustment signal OF 2  and outputs the resultant signal to a reference input terminal of the comparator  412 .  
         [0063]     The comparators  411  and  412  are substantially the same in configuration as the comparator  12  in  FIG. 1 . Input signals DRX and NDRX are input into positive and negative input terminals, respectively, of the comparator  411 , while the input signals NDRX and DRX are input into positive and negative input terminals, respectively, of the comparator  412 . The OR gate  413  calculates OR of a signal CM 1  output from the comparator  411  and a signal CM 2  output from the comparator  412 , and outputs the result to the threshold adjustment control section  432  and the detection section  20  as the detection signal CM.  
         [0064]     The threshold voltages of transistors in the two comparators  411  and  412  vary independently from each other. Therefore, the threshold voltages of these comparators are made adjustable independently.  
         [0065]     Once receiving the power-on signal PON or the hot plug signal PLG, the threshold adjustment control section  432  starts adjustment of the threshold voltages of the comparators  411  and  412 . The threshold adjustment control section  432  determines the detection level adjustment signal OF 1  and OF 2  independently in the manner described in the first embodiment. Note however that in determination of the detection level adjustment signal OF 1 , the threshold voltage of the comparator  412  (the detection level adjustment signal OF 2 ) should be made maximum, while in determination of the detection level adjustment signal OF 2 , the threshold voltage of the comparator  411  (the detection level adjustment signal OF 1 ) should be made maximum.  
         [0066]     Assuming that after determination of the detection level adjustment signals OF 1  and OF 2 , the threshold voltages of the comparators  411  and  412  are both set at VR, the condition for the detection CM going “H” is 
 
 |V ( DRX ) −V ( NDRX )|&gt; VR  
 
 where V(DRX) and V(NDRX) are the potentials of the input signals DRX and NDRX, respectively. 
 
         [0067]     As described above, with the comparator  411  receiving a differential signal and the comparator  412  receiving a differential signal opposite in polarity to the input differential signal, the signal detection circuit of  FIG. 7  can reliably detect that the voltage of the differential signal exceeds the threshold voltage, and thus can improve the reliability in the detection of the squelch signal SQOUT.  
         [0068]     According to the signal detection circuits of the embodiments described above, the threshold voltages of the comparators  12 ,  411  and  412  can be adjusted to appropriate values. This makes it possible to prevent detection of noise as an input signal or failure in detection of a signal to be detected. Also, detection of an input signal can be made available even in the case that the detection signal CM is “H” during the non-signal time period.