Abstract:
A miniaturized dual-balanced mixer circuit based on a trifilar layout architecture is proposed, which is designed for use to provide a frequency mixing function for millimeter wave (MMW) signals, and which features a downsized circuit layout architecture that allows IC implementation to be more miniaturized than the conventional star-type dual-balanced mixer (DBM). The proposed miniaturized dual-balanced mixer circuit is distinguished from the conventional star-type DBM particularly in the use of a trifilar layout architecture for the layout of two balun circuit units. This feature allows the required layout area to be only about 20% of that of the conventional star-type DBM.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates to a miniaturized dual-balanced mixer circuit which is fully equivalent in function to a conventional star-type dual-balanced mixer (DBM) for frequency mixing of millimeter wave (MMW) signals, except that the construction of the invention is based on a trifilar layout architecture that allows its IC implementation to be more miniaturized than the conventional star-type DBM. 
         [0003]    2. Description of Related Art 
         [0004]    In communications systems, the mixer is an essential circuit component which receives an input of a carrier signal RF and mixes it with a local oscillation signal LO to thereby produce an intermediate-frequency signal IF, where IF is either an up-converted frequency or a down-converted frequency, i.e., IF=RF+LO or IF=RF−LO. 
         [0005]    In millimeter wave (MMW) communications systems, the dual-balanced mixer (DBM) is a widely utilized frequency mixing circuit. Various types of DBM circuits have been proposed, including a ring-type and a star-type. The star-type DBM has better performance than the ring-type so that it is more widely utilized in the industry than the ring-type. The star-type DBM is so named due to the fact that the layout pattering of the microstrip lines used to constitute the mixer circuitry looks like a star. 
         [0006]    In practical applications, however, one drawback of the conventional star-type DBM is that it is based on a dual-balun circuit architecture which is considerably large in size in IC implementation so that it is unsuitable for use in the fabrication of miniaturized IC chips. 
       SUMMARY OF THE INVENTION 
       [0007]    It is therefore an objective of this invention to provide a miniaturized dual-balanced mixer circuit which is constructed on a trifilar layout architecture that allows its IC implementation to have a reduced layout space compared to the conventional star-type DBM for fabrication of miniaturized IC chips. 
         [0008]    In architecture, the miniaturized dual-balanced mixer circuit according to the invention comprises: (A) a first balun circuit unit; (B) a second balun circuit unit; and (C) a frequency-mixing circuit unit. 
         [0009]    The miniaturized dual-balanced mixer circuit of the invention is distinguished from the conventional star-type DBM particularly in that the invention utilizes two balun circuit units that are constructed on a multilayer substrate having at least 2 layers for the layout of a plurality of distributed transmission lines in such a manner as to form a dual Marchand balun circuit architecture whose layout pattern is based on a trifilar topology. 
         [0010]    Compared to the conventional star-type DBM, the miniaturized dual-balanced mixer circuit of the invention is more advantageous to use in that the invention can be implemented in IC fabrication with a reduced layout space compared to the conventional star-type DBM owing to the use of a trifilar layout architecture for the layout of the 2 balun circuit units. Specifically speaking, the invention only requires a layout area of about 20% of that of the conventional star-type DBM. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]    The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a schematic diagram showing the I/O functional model of the invention; 
           [0013]      FIG. 2  is a schematic diagram showing the circuit architecture of the invention; 
           [0014]      FIG. 3A  is a schematic diagram showing the circuit architecture of a first balun circuit unit utilized by the invention as a circuit component; 
           [0015]      FIG. 3B  is a schematic diagram showing the circuit architecture of a second balun circuit unit utilized by the invention as a circuit component; 
           [0016]      FIG. 4A  is a schematic diagram showing the equivalent circuit of a first embodiment of the invention based on a diode-switched type of frequency-mixing circuit unit; 
           [0017]      FIG. 4B  is a schematic diagram showing the equivalent circuit of a second embodiment of the invention based on a transistor-switched type of frequency-mixing circuit unit; 
           [0018]      FIG. 5A  is a schematic diagram showing a plan view of a trifilar layout architecture utilized by the invention for implementing a balun circuit unit; 
           [0019]      FIG. 5B  is a schematic diagram showing a sectional view of the trifilar layout architecture shown in  FIG. 5A ; 
           [0020]      FIG. 6A  is a graph showing the insertion loss versus RF characteristics of each balun circuit unit utilized by the invention; 
           [0021]      FIG. 6B  is a graph showing the phase difference versus RF characteristics of each balun circuit unit utilized by the invention; 
           [0022]      FIG. 7A  is a graph showing the conversion gain versus RF characteristics of the invention; and 
           [0023]      FIG. 7B  is a graph showing the LO-to-RF and IF-to-RF isolation versus RF characteristics of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0024]    The miniaturized dual-balanced mixer circuit based on a trifilar layout architecture according to the invention is disclosed in full details by way of preferred embodiments in the following with reference to the accompanying drawings. 
       FUNCTION OF THE INVENTION  
       [0025]      FIG. 1  shows the I/O (input/output) functional model of the miniaturized dual-balanced mixer circuit of the invention  10 . As shown, the miniaturized dual-balanced mixer circuit of the invention  10  is used for processing an input of a high-frequency signal, such as a millimeter-wave (MMW) carrier signal RF, by mixing it with a local oscillation signal LO to thereby produce an intermediate-frequency signal IF, where IF is either a down-converted frequency, i.e., IF=RF−LO, or an up-converted frequency, i.e., IF=RF+LO. This I/O relationship is the same as conventional types of mixers. 
       ARCHITECTURE OF THE INVENTION  
       [0026]    Referring further to  FIG. 2 , in architecture, the miniaturized dual-balanced mixer circuit of the invention  10  comprises: (A) a first balun circuit unit  100 ; (B) a second balun circuit unit  200 ; and (C) a frequency-mixing circuit unit  300 . Firstly, the respective attributes and functions of these constituent circuit components of the invention are described in details in the following. 
       (A) First Balun Circuit Unit  100   
       [0027]    The first balun circuit unit  100  has an I/O interface including one input port LO and four output ports: a first output port LO 1 (+), a second output port LO 1 (−), a third output port L 02 (+), and a fourth output port LO 2 (−). In operation, the input port LO is used for reception of the local oscillation signal LO while the four output ports are used respectively for outputting four balance-to-unbalance transformed signals [LO 1 (+), LO 1 (−), LO 2 (+), LO 2 (−)], where the first pair of output signals [LO 1 (+), LO 1 (−)] are a pair of differential signals with a phase difference of 180 degrees, while the second pair of output signals [LO 2 (+), LO 2 (−)] are also a pair of differential signals with a phase difference of 180 degrees. 
         [0028]    In practice, the first balun circuit unit  100  is based on a circuit architecture shown in  FIG. 103A  which includes  6  distributed transmission lines, including a first transmission line  121 , a second transmission line  122 , a third transmission line  123 , a fourth transmission line  124 , a fifth transmission line  125 , and a sixth transmission line  126 . These transmission lines ( 121 ,  122 ,  123 ,  124 ,  125 ,  126 ) are each implemented with a quarter-wavelength (λ/4) microstrip line, and which are arranged to constitute a dual Marchand balun circuit architecture whose equivalent circuit is shown in  FIG. 4A . Since the dual Marchand balun circuit architecture is a well-known circuit technology in the field and industry of electronics, detailed description thereof will not be given in this specification. 
         [0029]    It is an important aspect of the invention that in IC realization the first balun circuit unit  100  is implemented with a trifilar layout architecture shown in  FIGS. 5A-5B . As shown, this trifilar layout architecture is based on a multilayer substrate  110  (which is for example a 2-layer substrate in this embodiment) for layout of the six transmission lines ( 121 ,  122 ,  123 ,  124 ,  125 ,  126 ). As illustrated in  FIG. 5B , the multilayer substrate  110  includes at least 2 circuit layout planes: a first circuit layout plane  111  and a second circuit layout plane  112 , and further includes a grounding plane  113 . In practice, for example, the multilayer substrate  110  can be implemented with a commercially-standardized double-layer GaAs substrate specifically used for 0.15 μm (micrometer) pHEMT (pseudomorphic HEMT, where HEMT=High Electron Mobility Transistor) fabrication processes. 
         [0030]    As illustrated in  FIG. 5A , on the multilayer substrate  110 , the first circuit layout plane  111  is used for the layout of the first transmission line  121 , the third transmission line  123 , and the fifth transmission line  125  which are patterned in a trifilar topology; and in a similar manner, the second circuit layout plane  112  is used for the layout of the second transmission line  122 , the fourth transmission line  124 , and the sixth transmission line  126  which are also patterned in the same trifilar topology. 
         [0031]    On the first circuit layout plane  111 , the third transmission line  123  is composed of  3  separate segments which are interconnected by two bridging lines into one single continuous line, and which has a first terminal  123   a  connected to receive the local oscillation signal LO and a second terminal  123   b  connected to the fourth transmission line  124  on the second circuit layout plane  112 . The first transmission line  121  is also composed of 3 separate segments which are interconnected by two bridging lines into one single continuous line, and which has a first terminal  121   a  used for output of the transformed signal LO 1 (+) and a second terminal  121   b  connected to a grounding via  131 . Further, the fifth transmission line  125  is also composed of 3 separate segments which are interconnected by two bridging lines into one single continuous line, and which has a first terminal  125   a  used for output of the transformed signal LO 2 (+) and a second terminal  125   b  connected to a grounding via  132 . 
         [0032]    In the foregoing trifilar layout architecture, the first transmission line  121  and the fifth transmission line  125  are each a quarter-wavelength (λ/4) microstrip line, whereas the third transmission line  123  can have a length slightly longer than quarter-wavelength (λ/4). These three transmission lines ( 121 ,  123 ,  125 ) each has a line width W and a gap distance S. The first transmission line  121  and the fifth transmission line  125  extend on both sides of the third transmission line  123  to form a dual Marchand balun circuit architecture. 
         [0033]    In a similar manner on the second circuit layout plane  112 , the other 3 transmission lines ( 122 ,  124 ,  126 ) are laid in the same trifilar pattern as the forgoing 3 transmission lines ( 121 ,  123 ,  125 ). Details thereof will not be repeatedly described herein. 
       (B) Second Balun Circuit Unit  200   
       [0034]    The second balun circuit unit  200  is based on a circuit architecture shown in  FIG. 3B , which is entirely identical to the circuit architecture of the first balun circuit unit  100  shown in  FIG. 3A  and described above. The second balun circuit unit  200  also has an I/O interface including one input port RF and four output ports: a first output port RF 1 (+), a second output port RF 1 (−), a third output port RF 2 (+), and a fourth output port RF 2 (−). In operation, the input port RF is used for reception of the carrier signal RF and the four output ports are used respectively for outputting four balance-to-unbalance transformed signals [RF 1 (+), RF 1 (−), RF 2 (+), RF 2 (−)], where the first pair of output signals [RF 1 (+), RF 1 (−)] are a pair of differential signals with a phase difference of 180 degrees, while the second pair of signals [RF 2 (+), RF 2 (−)] are also a pair of differential output signals with a phase difference of 180 degrees. 
         [0035]    In circuit architecture, the second balun circuit unit  200  shown in  FIG. 3B  is also composed of 6 distributed transmission lines, including a first transmission line  221 , a second transmission line  222 , a third transmission line  223 , a fourth transmission line  224 , a fifth transmission line  225 , and a sixth transmission line  226 . 
         [0036]    In IC implementation, these six transmission lines ( 221 ,  222 ,  223 ,  224 ,  225 ,  226 ) of the second balun circuit unit  200  are also constructed on the trifilar layout architecture shown in  FIGS. 5A-5B . Since this second balun circuit unit  200  is entirely identical in architecture, function, and layout as the first balun circuit unit  100  described above, description thereof will not be repeated here. 
       (C) Frequency-Mixing Circuit Unit  300   
       [0037]    The frequency-mixing circuit unit  300  is used to process the output signals [LO 1 (+), LO 1 (−), LO 2 (+), LO 2 (−)] and [RF 1 (+), RF 1 (−), RF 2 (+), RF 2 (−)] generated by the first balun circuit unit  100  and the second balun circuit unit  200  to thereby generate an intermediate-frequency signal IF. 
         [0038]    In practice, the frequency-mixing circuit unit  300  can be realized in the following two embodiments: (C1) a diode-switched circuit architecture shown in  FIG. 4A ; and (C2) a transistor-switched circuit architecture shown in  FIG. 4B . 
       (C1) Diode-Switched Type of Frequency-Mixing Circuit Unit  300   
       [0039]    As shown in  FIG. 4A , the first embodiment of the frequency-mixing circuit unit  300  is based on a diode-switched circuit architecture which is composed of 4 diodes arranged in a particular manner that allows the generation of the intermediate-frequency signal IF in response to [LO 1 (+), LO 1 (−), LO 2 (+), LO 2 (−)] and [RF 1 (+), RF 1 (−), RF 2 (+), RF 2 (−)]. This diode-switched circuit architecture is based on a conventional circuit arrangement used in conventional star-type DBM circuitry, so that detailed description thereof will not be given in this specification. 
       (C2) Transistor-Switched Type of Frequency-Mixing Circuit Unit  300   
       [0040]    As shown in  FIG. 4B , the second embodiment of the frequency-mixing circuit unit  300  is based on a transistor-switched circuit architecture which is composed of 4 transistor-based circuit modules (each including a transistor, a resistor, and a capacitor) that are arranged in a particular manner to allow the generation of the intermediate-frequency signal IF in response to [LO 1 (+), LO 1 (−), LO 2 (+), LO 2 (−)] and [RF 1 (+), RF 1 (−), RF 2 (+), RF 2 (−)]. This transistor-switched circuit architecture is also based on a conventional circuit arrangement used in conventional star-type DBM circuitry, so that detailed description thereof will not be given in this specification. 
       OPERATING CHARACTERISTICS OF THE INVENTION  
       [0041]      FIG. 6A  is a graph showing the insertion loss versus RF characteristics of each of the two balun circuit units ( 100 ,  200 ) resulted from both circuit simulation and actual testing. It can be seen from this graph that in the frequency range from 25 GHz to 58 GHz, the simulation result shows an insertion loss of about 7 dB to 8.5 dB, while the actual testing shows an insertion loss of about 9 dB to 11 dB. Moreover, both simulation and actual testing show an amplitude difference of from 1 dB to 2 dB. 
         [0042]    Further,  FIG. 6B  is a graph showing the phase difference versus RF characteristics of each of the two balun circuit units ( 100 ,  200 ) resulted from both circuit simulation and actual testing. It can be seen from this graph that in the frequency range from 20 GHz to 50 GHz, the simulation result shows an output signal phase of from −182° to −178°, while the actual testing shows an output signal phase of from −183° to −171°, which indicates that the output signal phase difference is about 180°±10°. 
         [0043]      FIG. 7A  is a graph showing the conversion gain versus RF characteristics of the miniaturized dual-balanced mixer circuit of the invention  10  resulted from both circuit simulation and actual testing. It can be seen from this graph that the miniaturized dual-balanced mixer circuit of the invention  10  is capable of providing a conversion loss in the range from −7 dB to −12 dB. 
         [0044]      FIG. 7B  is a graph showing the LO-to-RF and LO-to-IF isolation versus RF characteristics of the miniaturized dual-balanced mixer circuit of the invention  10  resulted from both circuit simulation and actual testing. It can be seen from this graph that the miniaturized dual-balanced mixer circuit of the invention  10  is capable of providing a level of LO-to-RF and LO-to-IF isolation greater than 20 dB. 
       ADVANTAGE OF THE INVENTION  
       [0045]    Compared to the conventional star-type DBM, the miniaturized dual-balanced mixer circuit of the invention  10  is more advantageous to use in that the invention requires a smaller layout space in IC implementation owing to the use of a trifilar layout architecture for the layout of the 2 balun circuit units ( 100 ,  200 ). Specifically speaking, the conventional star-type DBM requires a layout area of about the square of (λ/2), whereas the invention only requires a layout area of about the square of (λ/6), i.e., only about 20% of the layout area of the conventional star-type DBM. The invention is therefore more advantageous to use than the prior art. 
         [0046]    The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and functional equivalent arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and functional equivalent arrangements.