Abstract:
A parity predict circuit for an M-level N&#39;th power Galois arithmetic gate using binary logic elements and a method of the designing thereof is disclosed. The method involves an algorithm that the logic designer utilizes to visually analyze the output of the arithmetic gate using a heuristic technique to determine the procedure for intercoupling the outputs of the gate&#39;s 1 through m-1 levels of parity trees as inputs to the parity predict parity tree. This visual analysis obviates the laborious mathematical treatment of the arithmetic gate priorly utilized to design a parity predict network.

Description:
BACKGROUND OF THE INVENTION 
     In the prior art it is known to design parity predict networks for detecting errors in N&#39;th power Galois arithmetic gates. In the publication &#34;A Cellular-Array Multiplier for GF(2 m ),&#34; B. A. Laws, Jr., et al IEEE Transactions on Computers, Dec. 1971, pp. 1573-1578, with particular reference to FIGS. 5 and 6 and the pertinent discussion thereof, there are disclosed methods of designing parity predict networks for a cellular array N&#39;th power Galois multiplication gate. This method of B. A. Laws, et al, is applicable only to a cellular array (as distinguished from a combinatorial array to which the present invention is directed), and, accordingly, is not applicable to all N&#39;th power Galois multiplication gates while yet requiring a rigorous mathematical treatment of the logic terms of the cellular array to determine the appropriate construction of the parity predict network. In contrast, the present invention is directed toward the application of a straight-forward algorithm that by a visual inspection of the manner in which the outputs of the 1 through m-1 levels of parity trees are coupled as inputs to the output, m-level parity trees determines the particular first level parity tree&#39;s outputs that are coupled as inputs to the parity predict network. 
     SUMMARY OF THE INVENTION 
     The method of the present invention is directed toward a parity predict network for an M-level, combinatorial array, N&#39;th power Galois arithmetic (linear or multiplication) gate such as that of the J. T. Ellison U.S. Pat. No. 3,805,037. Such a gate includes a matrix of array of n, X input lines x O , . . . x n   -1  and n, Y input lines y O , . . . y n   -1  that form the n 2  intersections x O  y O , x O  y 1 , . . . x n   -1  y n   -2 , x n   -1  y n   -1  wherein there are n 2 , two-input AND gates, a separate one having its two inputs coupled across the x input line and the y input line of an associated one of the n 2  intersections. The n 2  outputs of the n 2 , two-input AND gates are coupled to a plurality of 1 through m-1 levels of parity trees the outputs of which are coupled to n, m-level parity trees. The n outputs of the n, m-level of parity trees generate the Galois multiplication resultant 
     
         G(XY) = (XY).sub.O, . . . (XY).sub.n.sub.-1, 
    
     of the Galois input on the n, X input lines of 
     
         G(X) = X.sub.O, . . . X.sub.n.sub.-1, 
    
     and of the Galois input on the n, Y input lines of 
     
         G(Y) = Y.sub.O, . . . Y.sub.n.sub.-1. 
    
     In the case where m = 2, the two-level limitation to the Galois arithmetic gate to which the present invention applies implies that certain ones of the outputs of the n 2 , two-input AND gates are coupled as inputs to a plurality of parity trees that are collectively defined as a first level of parity trees -- it is to be appreciated that k-input EXCLUSIVE OR gates, where k is a positive integer of three or greater, are synonymous to a k-input parity gate, and may be comprised of the number (k-1) of two-input EXCLUSIVE OR gates, see the text &#34;Digital Design,&#34; Wiley-Interscience, 1971, R. K. Richards, pp. 198-200 -- while the outputs of the first level of parity trees (and perhaps certain other ones of the outputs of the n 2 , two-input AND gates) are coupled as the inputs to n, second level of parity trees which n, second level parity trees provide as an output therefrom the Galois, e.g., multiplication resultant 
     
         G(XY) = (XY).sub.O, . . . (XY).sub.n.sub.-1. 
    
     The algorithm of the present invention consists of the visual analysis of such, e.g., two-level N&#39;th power Galois arithmetic gate and the method of intercoupling certain outputs of the first level of parity trees to a parity predict network (which also has an input thereto the product of the parities X p  Y p  of the X n , Y n  inputs that are the inputs to the arithmetic gate) to provide as an output therefrom the parity predict P p . This parity predict P p  may then be combined with the parity of the product (XY) p , which is generated from the outputs of the n, second level parity trees, as inputs to a parity error indicator parity tree, e.g., an EXCLUSIVE OR gate, to generate as an output therefrom the parity error indicator E p . The parity predict network is a parity tree whose terms are such that the following properties hold for it in combination with the outputs of the arithmetic gate&#39;s first level of parity trees, the outputs of which are the inputs to the gate&#39;s second level of parity trees: 
     the output of every first level parity tree that is an input to an even number, i.e., has an even fan-out, of second level parity trees is also coupled as an input to the parity predict parity tree; 
     the output of any first level parity tree that is an input to an odd number, i.e., has an odd fan-out, of second level parity trees is not coupled as an input to the parity predict parity tree. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a logic level diagram of a prior art combinatorial array, two-level, N&#39;th power [where GF(2 n ), n = 4] Galois multiplication gate to which the present invention is applicable. 
     FIG. 2 is a logic level diagram of a Galois multiplication gate similar to that of FIG. 1 but in which the first level parity trees and the second level parity trees have a different logic conformation. 
     FIG. 3, comprised of FIGS. 3a and 3b, is a logic level diagram of the gate of FIG. 1 to which the parity predict network of the present invention and the parity of the product network and the parity error indicator network have been added. 
     FIG. 4, comprised of FIGS. 4a and 4b, is an illustration of a modification of a multiplication gate similar to that of FIG. 1 for conversion to a linear gate. 
     FIG. 5, comprised of FIGS. 5a, 5b, and 5c, is a block diagram of another embodiment of the present invention that is directed toward a two-level, N&#39;th power, Galois arithmetic gate, where GF(2 n ), n = 8. 
     FIG. 6, comprised of FIGS. 6a, and 6b, is a block diagram of a prior art combinatorial array, three-level N&#39;th power Galois multiplication gate to which the present invention is applicable. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With particular reference to FIG. 1 there is presented a logic level diagram of a prior art combinatorial array, two-level, N&#39;th power [where GF(2 n ), n = 4] Galois multiplication gate 10 to which the present invention is applicable. In the publication &#34;Galois Logic Design,&#34; J. T. Ellison, et al, AFCRL-70-0583, obtainable from Data Sciences Laboratory, Air Force Cambridge Research Laboratories, Air Force Systems Command, United States Air Force, Bedford, Massachusetts, 01730, there has been developed a general method for configuring a plurality of AND gates and EXCLUSIVE OR gates into an M-level, N&#39;th power, Galois multiplication gate such as the arithmetic gate 10 of FIG. 1. In the J. T. Ellison U.S. Pat. No. 3,805,037, there is disclosed a method of converting such multiplication gate 10 into a linear gate by the addition of n, Z input lines to the n, output EXCLUSIVE OR gates (parity trees). The present invention builds upon these prior art arithmetic (multiplication and linear) gates, a parity predict network for determining the validity vel non of the output of the arithmetic gate 10. Thus, the embodiment of FIG. 1 is acknowledged prior art. 
     With particular reference to FIG. 2 there is presented a logic level diagram of a Galois multiplication gate 12 similar to that of FIG. 1 but in which the first level of parity trees and the second level of parity trees have a different logic conformation. It is to be recognized that the logic design of multiplication gates 10 and 12 are substantially similar, the only distinction being the particular conformation or method of intercoupling the n 2  AND gates to a plurality of first level parity trees and a second level of parity trees -- both conformations generating the same Galois multiplication resultant 
     
         G(XY) = (xy).sub.O, . . . (xy).sub.n.sub.-1. 
    
     Accordingly, for the purpose of defining the applicability of the present invention it is hereby stated that the present invention is limited to an M-level, N&#39;th power, Galois arithmetic gate comprised of 
     a matrix array of n, X input lines x O , . . . x n   -1  and n, Y input lines y O , . . . y n   -1  for forming the n 2  intersections x O  y O , x O  y 1 , . . . x n   -1  y n   -2 , x n   -1  y n   -1  ; 
     n 2 , two-input AND gates, a separate one having its two inputs coupled across the X input line and the Y input line of an associated one of said n 2  intersections; 
     a plurality of 1 through m-1 levels of parity trees; 
     n, output, m-level parity trees; 
     means intercoupling said n 2  AND gates, said plurality of 1 through m-1 levels of parity trees and said n, output, m-level parity trees for generating as the outputs of said n, output, m-level parity trees, the Galois arithmetic resultant; wherein each of said 1 through m levels of parity trees is defined as 
     a level of parity trees whose inputs are the outputs of said Galois arithmetic gate&#39;s n 2  AND gates or the outputs of lower level parity trees and in which there are no internal fan-outs greater than 1 but which has at least one output that has a number of fan-outs greater than 1, and wherein said output, m-level of parity trees is defined as 
     a level of parity trees in which there are no internal fan-outs greater than 1 and whose n, outputs are the outputs of the Galois arithmetic gate. 
     With particular reference to the arithmetic gates 10, 12 of FIGS. 1, 2, J. T. Ellison in the above referenced publication derived a general method for configuring a plurality of AND gates and EXCLUSIVE OR gates into a two-level (first and second level parity trees at the output of the gates 10, 12) N&#39;th power, Galois arithmetic gate. The equations for the outputs are 
     
         (xy).sub.O = x.sub.2 y.sub.2 ⊕x.sub.3 y.sub.1 ⊕x.sub.1 y.sub.3 ⊕x.sub.3 y.sub.O ⊕x.sub.O y.sub.3 ⊕x.sub.2 y.sub.1 ⊕x.sub.1 y.sub.2 
    
     
         (xy).sub.1 = x.sub.O y.sub.O ⊕x.sub.3 y.sub.2 ⊕x.sub.2 y.sub.3 ⊕x.sub.3 y.sub.O ⊕x.sub.O y.sub.3 ⊕x.sub.2 y.sub.1 ⊕x.sub.1 y.sub.2 
    
     
         (xy).sub.2 = x.sub.3 y.sub.3 ⊕x.sub.1 y.sub.O ⊕x.sub.O y.sub.1 ⊕x.sub.3 y.sub.O ⊕x.sub.O y.sub.3 ⊕x.sub.2 y.sub.1 ⊕x.sub.1 y.sub.2 
    
     
         (xy).sub.3 = x.sub.1 y.sub.1 ⊕x.sub.2 y.sub.O ⊕x.sub.O y.sub.2 ⊕x.sub.3 y.sub.O ⊕x.sub.0 y.sub.3 ⊕x.sub.2 y.sub.1 ⊕x.sub.1 y.sub.2. 
    
     The parity equations for the inputs are: 
     
         xp = x.sub.O ⊕x.sub.1 ⊕x.sub.2 ⊕x.sub.3 
    
     
         yp = y.sub.O ⊕y.sub.1 ⊕y.sub.2 ⊕y.sub.3. 
    
     The parity of the product is: 
     
         (xy).sub.p = (xy).sub.O ⊕(xy).sub.1 ⊕(xy).sub.2 ⊕(xy).sub.3. 
    
     The sum of the parity of the product, i.e., (xy) p , and the product of the parities, i.e., x p  y p , is: 
     
         (xy).sub.p ⊕x.sub.p y.sub.p = x.sub.3 y.sub.O ⊕x.sub.O y.sub.3 ⊕x.sub.2 y.sub.1 ⊕x.sub.1 y.sub.2. 
    
     This sum is the output of the first level of parity trees, so identified in FIG. 1, that is coupled as an input to each of the four, second level of parity trees, so identified in FIG. 1, such than an error comparison may be obtained by the following equation: 
     
         (xy).sub.p = x.sub.p y.sub.p ⊕x.sub.3 y.sub.0 ⊕x.sub.0 y.sub.3 ⊕x.sub.2 y.sub.1 ⊕x.sub.1 y.sub.2 
    
     such that any single gate error, e.g., an error caused by the fault or malfunction of any one of the plurality of AND gates and/or EXCLUSIVE OR gates (of the parity trees) may be detected. 
     A similar type of derivation for a cellular array (as distinguished from a combinatorial array to which the present invention is directed) for an N&#39;th power, Galois multiplication gate may be found in the hereinabove B. A. Laws, et al, publication. The method of the present invention builds upon the derivations of the hereinabove referenced J. T. Ellison and B. A. Laws, et al, publications to provide a method for designing a parity predict network for an M-level, N&#39;th power, Galois arithmetic gate. The method or algorithm of the present invention consists of the visual analysis of such two-level, N&#39;th power, Galois arithmetic gates, such as illustrated in FIGS. 1, 2, and a method of intercoupling certain outputs of the first level parity trees to a parity predict network (which also has as an input thereto the product of the parities) X p  X p  of the X n , Y n  inputs that are the inputs to the arithmetic gates) to provide as an output therefrom the parity predict P p . 
     As the algorithm of the present invention involves the visual analysis of the intercoupling of the n 2  AND gates and the outputs of the lowest, first level through the higher m-1 level of parity trees of an M-level N&#39;th power Galois arithmetic gate to the output, m-level of parity trees, the definitions, given hereinabove, of such lowest first through the highest m levels of parity trees are now repeated: 
     the first through the m-1 levels of parity trees are each defined as a level of parity trees whose inputs are the outputs of said Galois arithmetic gates n 2  AND gates or the outputs of lower level parity trees and in which there are no internal fan-outs greater than 1 but which has at least one output that has a number of fan-outs greater than 1, and, 
     the output, m-level of parity trees is defined as a level of parity trees in which there are no internal fan-outs greater than 1 and whose n, outputs are the outputs of the Galois arithmetic gate. 
     The algorithm of the present invention consists of the visual analysis of such, e.g., two-level, N&#39;th power, Galois arithmetic gate and the method of intercoupling certain outputs of the first level parity trees to a parity predict network (which also has as an input thereto the product of the parities) X p  Y p  of the X n , Y n  inputs that are the inputs to the arithmetic gate (to provide as an output therefrom the parity predict P p ). The parity predict network is a parity tree whose terms are such that the following properties hold for it in combination with the outputs of the arithmetic gate&#39;s first level parity trees, the outputs of which are the inputs to the gate&#39;s second level parity trees: 
     the output of every first level parity tree that is an input to an even number, i.e., has an even fan-out, of second level parity trees is also coupled as an input to the parity predict parity tree; 
     the output of any first level parity tree that is an input to an odd number, i.e., has an odd fan-out, of second level parity trees is not coupled as an input to the parity predict parity tree. 
     Using the multiplication gate 10 of FIG. 1 as an example, it can be seen that the first level of parity trees consists of parity trees 20 (e.g., comprised of EXCLUSIVE OR&#39;s 20-1 and 20-2), 21, 22, 23 and 24 while the second level of parity trees consists of parity trees 25 (e.g., comprised of EXCLUSIVE OR 25-1), 26, 27, 28. Also, it can be seen that the first level of parity trees 20, 21, 22, 23 and 24 are a level of parity trees whose inputs are the outputs of the n 2  AND gates and in which there are no internal fan-outs, i.e., fan-outs internal to the first level of parity trees, greater than 1 but which have at least one output, e.g., output 22-0 of parity tree 22, that has a number of fan-outs greater than 1, i.e., four, which four fan-outs are coupled as inputs to parity trees 25, 26, 27 and 28 of the second level of parity trees. Output 22-0 has an even number of fan-outs, accordingly, output 22-0 of parity tree 22 is also coupled in FIG. 3, as a first input, to parity predict parity tree 44, (e.g., consisting of EXCLUSIVE OR 44-1). Coupled as a second input to parity predict parity tree 44 is the product of the parities (x p  y p ) which is the output of parity predict AND gate 45. The product of the parities, at parity predict AND gate 45 is generated, as the inputs, by the two outputs of X p  parity tree 46 and Y p  parity tree 47, whose respective outputs are 
     
         X.sub.p = x.sub.0 ⊕, . . . ⊕x.sub.n.sub.-, 
    
     which is the parity of the Galois input on said n, X input lines, and 
     
         Y.sub.p = y.sub.0 ⊕, . . . ⊕y.sub.n.sub.-1, 
    
     which is the parity of the Galois input on said n, Y input lines, which X input lines and Y input lines are the respective input lines to gate 10. The output of parity predict parity tree 44 is the parity predict P p  which is the output of the parity predict network formed of: 
     Y p  parity predict tree 47, 
     X p  parity predict tree 46, 
     Parity predict AND gate 45, 
     Parity predict parity tree 44. 
     To utilize the parity predict P p  there is further added to multiplication gate 10 the gate resultant parity tree 40 whose inputs are the n, outputs of multiplication gate 10, i.e., the Galois multiplication resultant 
     
         G(XY) = (xy).sub.0, (xy).sub.1, (xy).sub.2, (xy).sub.3 
    
     whose output is the parity of the product (xy) p . Also added is the parity error indicator parity tree 42 whose two inputs are: 
     the parity predict P p  from parity predict parity tree 44, 
     the parity of the product (xy) p  from gate resultant parity tree 40, 
     and which provides as an output therefrom, the parity error indicator E p  which indicates the fault or malfunction vel non of any of the AND gates or EXCLUSIVE OR gates of multiplication gate 10 of FIGS. 1, 3. 
     With particular reference to FIG. 4 there is presented an illustration of a modification of a multiplication gate similar to that of FIG. 1 for conversion to a linear gate. Two-level, N&#39;th power, Galois linear gate 50 is similar to that of the hereinabove referenced J. T. Ellison U.S. Pat. No. 3,805,037. As disclosed in such Ellison patent a Galois multiplication gate, which Galois multiplication gate generates the Galois multiplication resultant 
     
         G(XY) = (xy).sub.0, . . . (xy).sub.n.sub.-1 
    
     as the output of n, output, second level parity trees from the Galois input on n, X input lines of 
     
         G(X) = x.sub.0, . . . x.sub.n.sub.-1, 
    
     and from the Galois input on n, Y input lines of 
     
         G(Y) = Y.sub.0, . . . Y.sub.n.sub.-1, 
    
     may be converted to a Galois linear gate by the addition of n, Z input lines, a separate one coupled as an input to an associated separate one of said n, output, second level parity trees for generating as the output of said n, output, second level parity trees the Galois linear resultant 
     
         G(XY+Z) = (xy+z).sub.0, . . . (xy+z).sub.n.sub.-1. 
    
     In the illustrated configuration of the Galois linear gate 50 of FIG. 4 it can be seen that the first level parity trees consist of parity trees 60, 61, 62, 63 and 64 while the second level parity trees consist of parity trees 65, 66, 67 and 68 with parity tree 62 having an even number of fan-outs greater than 1, e.g., four. Accordingly, as with the above discussion, particularly with respect to FIGS. 1 and 3, the output of parity tree 62 at line 62-0 is coupled, as an input, to parity predict parity tree 80. Also coupled to parity of the product parity tree 82, as inputs, are the outputs 
     
         G(XY+Z) = (xy+z).sub.0, (xy+z).sub.1, (xy+z).sub.2, (xy+z).sub.3 
    
     for providing as an output therefrom the parity of the product (xy+z) p  which is coupled as a first input to parity error indicator parity tree 84. Coupled to parity predict parity tree 80, via parity predict AND gate 90, is the product of the parity x p  y p  that is generated by the X p  parity tree 86 and the Y p  parity tree 88 while coupled to parity predict parity tree 80 as a third input thereto is parity of the Galois input on the n, Z input lines, Z p , generated by Z p  parity tree 92. With the parity predict P p  from parity predict parity tree 80 coupled to parity error indicator parity tree 84 as a second input thereto there is provided as an output therefrom the parity error indicator E p , all in a manner similar to that discussed with particular reference to FIGS. 1, 3 and 4. 
     With particular reference to FIG. 5 there is presented a block diagram of another embodiment of the present invention that is directed toward a two-level, N&#39;th power, Galois arithmetic (multiplication or linear) gate where GF(2 n ), n = 8. In this configuration of Galois arithmetic gate 100, where GF(2 n ), n = 8, there is illustrated a matrix array of eight X input lines and eight Y input lines for forming 64 intersections wherein 64 AND gates (having the associated 64 output lines designated C 00  through C 77 ) are coupled across the X input lines and the Y input lines of an associated one of the 64 intersections. As in previous discussions, there are two-levels of parity trees: first level parity trees consisting of parity trees 110, 111, 112, 113, 114 and 115 and C 77  and output, second level parity trees 116, 117, 118, 119, 120, 121, 122 and 123. 
     Visual analysis of the outputs of the first level parity trees 110 through 115 and of the outputs C 00  through C 77  of the 64 AND gates indicates that parity trees 110, 112, 113, 114 and 115 have an even number of fan-outs: 
     parity tree 110 has four fan-outs: to second level parity trees 116, 117, 118, 123; 
     parity tree 112 has four fan-outs: to second level parity trees 119, 121, 122, 123; 
     parity tree 113 has four fan-outs: to second level parity trees 118, 120, 121, 122; 
     parity tree 114 has four fan-outs: to second level parity trees 117, 119, 120, 121; 
     parity tree 115 has four fan-outs: to second level parity trees 116, 118, 119, 120. 
     Accordingly, the outputs of first level parity trees 110, 112, 113, 114, and 115, i.e., outputs 110-0, 112-0, 113-0, 114-0, and 115-0 are coupled as separate inputs to parity predict parity tree 130. Also, as before, the n, outputs of the n, second level parity trees 116, 117, 118, 119, 120, 121, 122, 123 are coupled as separate inputs to parity of the product parity tree 132 while the parity predict P p  from parity predict parity tree 130 and the parity of the product (xy) p  from the parity of the product parity tree 132 are coupled as separate inputs to the parity error indicator parity tree 134 for generating the error indicator E p  as an output therefrom. 
     Note that as before, the parity of the Galois input on the eight, X input lines from X p  parity tree 136 and the parity of the Galois input on the eight, Y input lines Y p   from Y p  parity tree 138, both via parity predict AND gate 140, and the parity of the Galois input on the eight, Z input lines Z p  from Z p  parity tree 142 are coupled as additional inputs to the parity predict parity tree 130. 
     For ease of reading the logic configuration of the first and second level parity trees, of the arithmetic gate 100 of FIG. 5, the outputs of the 64 AND gates of the matrix array of gate 100 are designated by the references C 00  through C 77  with the corresponding references C 00  through C 77  noted at their respective inputs to the first level parity trees 110-115 and the second level parity trees 116-123. Also, conversion of the multiplication gate to a linear gate is denoted by the optional addition of 8, Z inputs z 0  through z 7  at their respective inputs to the second level parity trees 116-123 and Z p  parity tree 142. This optional conversion, by the addition of the 8, Z inputs z 0  through z 7  which is denoted by the asterisk associated with the associated references, then converts the Galois multiplication resultant 
     
         G(XY) = (xy).sub.0, . . . (xy).sub.7 
    
     to the Galois linear resultant 
     
         G(XY+ Z) = (xy+ z).sub.0, . . . (xy+ z).sub.7 
    
     all in a manner similar to that disclosed in the hereinabove referenced J. T. Ellison U.S. Pat. No. 3,805,037. 
     With particular reference to FIG. 6 there is illustrated a block diagram of a prior art combinatorial array, M-level (M = 3), N&#39;th power (N = 4), Galois multiplication gate 150 to which the present invention is applicable. In this embodiment of the present invention the lowest, first level of parity trees consists of parity trees 160, 161, 162, 163, 164, and 165, the next-lowest, second (m-1) level of parity trees consists of parity trees 166 and 167 and the highest, output, third (m) level of parity trees consists of n (n = 4), parity trees 168, 169, 170 and 171. Also, it can be seen that each of the m = 3 levels of parity trees has no internal fan-out greater than 1, but that the first and the second levels of parity trees each have at least one output that has a fan-out greater than 1: 
     level 1: 
     parity tree 160 has two fan-outs: to second level parity tree 167 and to third level parity tree 168; 
     parity tree 162 has two fan-outs: to second level parity tree 166 and to third level parity tree 171; 
     parity tree 163 has two fan-outs: to second level parity tree 166 and to third level parity tree 169; 
     parity tree 165 has two fan-outs: to second level parity tree 167 and to third level parity tree 170. 
     level 2: 
     parity tree 166 has two fan-outs: to third level parity trees 168 and 170; 
     parity tree 167 has two fan-outs: to third level parity trees 169 and 171. 
     Visual analysis of the outputs of the first and second levels of parity trees and of the outputs of the 16 AND gates is had utilizing an algorithm similar to that given hereinabove with respect to the two-level N&#39;th power Galois arithmetic gates of FIGS. 1, 2, 3, 4 and 5: 
     the input of every level of parity trees that is an input to an even number of parity trees, i.e., has an even fan-out, is coupled as an input to the parity predict tree. Note that by the previous definition of a level of parity trees there are no fan-outs greater than 1 within a level of parity trees and, accordingly fan-outs greater than 1 exist only as inputs to a level of parity trees. 
     Using the multiplication gate 150 of FIG. 6, it can be seen that the above algorithm dictates that the outputs of parity trees 160, 162, 163, 165, 166 and 167, i.e., outputs 160-0, 162-0, 163-0, 165-0, 166-0 and 167-0 and the output of the parity predict AND gate 175 are coupled as separate inputs to parity predict parity tree 172. Also, as before, the n, outputs of the n, third level parity trees 168, 169, 170, 171 are coupled as separate inputs to parity of the product parity tree 173 while the parity predict P p  from parity predict parity tree 172 and the parity of the product (xy) p  from the parity of the product parity tree 173 are coupled as separate inputs to the parity error indicator parity tree 174 for generating the error indicator E p  as an output therefrom.