Abstract:
A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to Indian provisional patent application Number 4755/CHE/2015 filed on Sep. 8, 2015 by Texas Instruments and titled “Low Power Parallelized Architecture For M-By-N Resampler,” which is incorporated by reference. 
       BACKGROUND 
       [0002]    SRC is the process of changing a sampling rate of a discrete signal to obtain a new discrete representation of the underlying continuous signal. A typical SRC implements a rational re-sampling ratio M/N. M is a first sample rate, for instance an up-sampling rate, and N is a second sample rate, for instance a down-sampling rate. Up-sampling, or interpolation, increases a sampling rate of a signal. Down-sampling, or decimation, decreases the sampling rate of the signal. 
         [0003]    Signal chain systems such as communications transceivers and automotive radar receivers use M/N SRC. In those applications, high-performance, RF-sampling ADCs with integrated digital front-ends implement the M/N SRC. In mobile network base stations, the front-ends may change the ADC sampling frequency in a range of, for instance, 2 GHz to 3 GHz depending on the center frequencies of signal bands. That technique prevents second and third harmonic spurs from folding back in to the signal bands. However, interface rates for decimated input signals may be at fixed sample rates, for instance 245.76 MHz, which may necessitate resampling factors of 8/9, 4/5, and 2/3. 
       SUMMARY 
       [0004]    In one embodiment, the disclosure includes a re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. 
         [0005]    In another embodiment, the disclosure includes a re-sampler comprises a first MC-CSD multiplier configured to receive input samples, a second MC-CSD multiplier configured to receive the input samples, and a commutator coupled to the first MC-CSD multiplier and the second MC-CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. 
         [0006]    In another embodiment, the disclosure includes a re-sampler comprises an input commutator configured to receive input samples, a first MC-CSD multiplier coupled to the input commutator, a first intermediate commutator coupled to the first MC-CSD multiplier, a second MC-CSD multiplier coupled to the input commutator, a second intermediate commutator coupled to the second MC-CSD multiplier, and an output commutator coupled to the first intermediate commutator and the second intermediate commutator and configured to generate output samples based on the input samples. 
         [0007]    In yet another embodiment, the disclosure includes a method implemented in a re-sampler, the method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    For a detailed description of various examples, reference will now be made to the accompanying drawings. 
           [0009]      FIG. 1  is a schematic diagram of a DDC. 
           [0010]      FIG. 2  is a schematic diagram of a re-sampler. 
           [0011]      FIG. 3  is a table of coefficient indices for the multipliers in the re-sampler in  FIG. 2 . 
           [0012]      FIG. 4  is a simplified table of coefficient indices for the multipliers in the re-sampler in  FIG. 2 . 
           [0013]      FIG. 5  is a schematic diagram of a re-sampler according to an embodiment of the disclosure. 
           [0014]      FIG. 6  is a simplified table of coefficients for the CSD multipliers in the re-sampler in  FIG. 2 . 
           [0015]      FIG. 7  is a schematic diagram of a re-sampler according to another embodiment of the disclosure. 
           [0016]      FIG. 8  is a table of coefficient indices for a parallelized re-sampler. 
           [0017]      FIG. 9  is a simplified schematic diagram of a re-sampler according to yet another embodiment of the disclosure. 
           [0018]      FIG. 10  is a flowchart illustrating a method of re-sampling according to an embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, different companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. 
         [0020]    The following abbreviations, acronyms, and initialisms apply: 
         [0021]    ADC: analog-to-digital conversion, analog-to-digital converter 
         [0022]    CSD: canonical-signed-digit 
         [0023]    DDC: digital down-converter 
         [0024]    GHz: gigahertz 
         [0025]    I: in-phase 
         [0026]    LUT: look-up table 
         [0027]    MAC: multiplier-accumulator 
         [0028]    MC-CSD: multi-coefficient CSD 
         [0029]    MHz: megahertz 
         [0030]    Q: quadrature 
         [0031]    RF: radio frequency 
         [0032]    SRC: sample-rate conversion. 
         [0033]      FIG. 1  is a schematic diagram of a DDC  100 . The DDC  100  is described in U.S. patent application Ser. No. 15/246,248 filed on Aug. 24, 2016 by Jaiganesh Balakrishnan, et al., and titled “Analog-Digital Compatible Re-Sampling” (“Balakrishnan”), which is incorporated by reference. The DDC  100  comprises multipliers  110 , down-samplers  120 , and a re-sampler  130 . The down-samplers  120  may have a down-sampling rate of 2. The DDC  100  comprises a top branch for a baseband I signal and a bottom branch for a baseband Q signal. The re-sampler  130  comprises up-samplers  140 , filters  150 , and down-samplers  160 . The re-sampler  130  may be referred to as an M/N re-sampler because it comprises the up-samplers  140 , which may have an up-sampling rate of M, and comprises the down-samplers  160 , which may have a down-sampling rate of N, which combine to form an M/N resampling ratio. 
         [0034]    If the re-sampler  130  receives an input signal x(m) and if the sequence {h 0 , h 1 , . . . , h L−1 } represents the coefficients of the filters  150  with L taps, then the filters  150  compute up-sampled and interpolated signals as follows: 
         [0000]        u ( Mm+l )=Σ k=0   └(L−1)/M┘   x ( m−k )* h   Mk+1 ,∀/=0,1, . . . , M− 1  (2)
 
         [0000]    where u is an output signal; M is the up-sampling rate of the up-samplers  140 ; m is an integer sampling index of the input signal x(m); I is an integer that varies from 0 to M−1 and represents the sampling index of the interpolated and filtered output signal u(Mm+l); └ ┘ represents a floor operation, which computes a nearest integer that is less than its operand; L is a positive integer number of taps, or coefficients, of the filters  150 ; k is an integer that varies from 0 to └(L−1)/M┘, represents a delay in the sampling index of x(m) to obtain x(m-k), and is an index of the filter coefficient h Mk+1 ; and h is a tap coefficient. However, because the down-samplers  160  follow the filters  150 , it may be sufficient to compute only every N th  sample of u(Mm+I) in order to generate the output sample y(n). To compute one output sample, up to P=┌L/M┐ multiplication and accumulation operations may be used. The operations may have different phases I of the filter coefficients. The operator ┌ ┐ represents a ceiling operation, which computes a nearest integer that is greater than its operand. 
         [0035]      FIG. 2  is a schematic diagram of a re-sampler  200 . The re-sampler  200  is described in Balakrishnan. The re-sampler  200  may implement the re-sampler  130  and may be referred to as a ripple-down MAC re-sampler. The re-sampler  200  comprises a coefficient LUT  210 , a coefficient index generator  220 , P multiplexers  230 , multipliers  240 , flip-flops  250 , accumulators  260 , a flip-flop  270 , and flip-flops  280 . The re-sampler  200  also comprises P instances of N:1 multiplexers to select the coefficients for the multipliers  240 . P is a positive integer, and N is a positive integer down-sampling rate. The accumulators  260  may instead be referred to as adders, and a combination of the accumulators  260  and the flip-flops  280  may be referred to as accumulators. If the flip-flops  250 ,  270 ,  280  store multiple bits, then they may be referred to as registers. 
         [0036]    In operation, the multiplexers  230 , which are 2:1 multiplexers, select outputs from either their corresponding accumulator  260  or the preceding accumulator  260 . For instance, the second multiplexer  230  selects outputs from either the second accumulator  260  or the first accumulator  260 . That allows the sum of partial products, or the sum of intermediate outputs of the accumulators  260 , to be “rippled down” during every output sample index. However, when M/N=8/9, the re-sampler  200  does not generate output samples y(n) for every ninth input sample index, for instance for the output sample corresponding to the input sample x(m+8). The last accumulator  260  provides the final output sample to the flip-flop  270 . The flip-flop  270  provides samples at the equivalent output clock rate f out . The flip-flops  250  are optional and aid in timing closure of the digital logic at high clocking rates. 
         [0037]      FIG. 3  is a table  300  of coefficient indices for the multipliers  240  in the re-sampler  200  in  FIG. 2 . The coefficient indices are k for each h k . The table  300  is described in Balakrishnan. The table  300  assumes L=63 filter coefficients and a re-sampling ratio M/N=8/9. Thus, P=┌L/N┐=┌63/9┐=┌7┐=7, so there are 7 multipliers  240  as denoted by multiplier  1  to multiplier  7 . The partial products that correspond to each of the output samples have the same hatching scheme. For instance, the partial products  61  for multiplier  1 ,  53  and  45  for multiplier  2 ,  37  for multiplier  3 ,  29  for multiplier  4 ,  21  for multiplier  5 ,  13  for multiplier  6 , and  5  for multiplier  7  correspond to output sample y(n+5). 
         [0038]    When the re-sampler  200  does not generate a final output sample, for instance for the output sample corresponding to the N th  input sample, the select signal of the multiplexers  230  is 1, which causes the re-sampler  200  to retain the sum of partial products in their respective streams. For all other input samples, the select signal for the multiplexers  230  is 0, which causes the re-sampler  200  to ripple down the sum of partial products. One of the inputs to the first multiplexer  230  is 0, which ensures that the output of the first flip-flop  280  is reset when the first partial product corresponding to a new output sample needs to be computed. The multipliers  240  cycle through a different set of only N=9 coefficients, and the entire coefficient selection and multiplexer selection repeats after N input sample instances. In other words, each multiplier  240  uses a different set of N coefficients, and all of the sets of N coefficients make up a total of L coefficients. The index k, which the multiplexers use to select the coefficients {h (P−1)N+k , h (P−2)N+k , . . . , h k } for the multipliers  540 , periodically takes values from (0, 1, . . . , N−1). 
         [0039]      FIG. 4  is a simplified table  400  of coefficient indices for the multipliers  230  in the re-sampler  200  in  FIG. 2 . The table  400  is similar to the table  300  in  FIG. 3 . However, the table  400  is simplified to show the maximum number, N=9, of sets of coefficients that the multipliers  230  need to handle. The column for set 0 in the table  400  corresponds to the column for x(m) in the table  300  in  FIG. 3 , the column for set 1 in the table  400  corresponds to the column for x(m+1) in the table  300 , and so on. 
         [0040]    A dual-channel RF-sampling ADC may support two DDC chains per channel and two streams per DDC chain, where a first stream is an I stream and a second stream is a Q stream. That ADC architecture implements eight M/N re-samplers such as the re-sampler  200 . Because the ADC implements so many re-samplers, there is a need to reduce the power consumption of those re-samplers. 
         [0041]    In addition, the re-sampler  130  in  FIG. 1  may need to operate at a sampling rate of approximately 750 MHz. Current semiconductor technology may not support that sampling rate. As a result, the re-sampler  130  may need to be parallelized to receive two input samples for each clock cycle and therefore operate at f in /2 and may need to replicate its logic to provide two output samples for every clock cycle. 
         [0042]    Disclosed herein are embodiments for re-samplers with reduced power consumption and complexity. In a first embodiment, a re-sampler comprises MC-CSD multipliers, which replace standard multipliers. The MC-CSD multipliers replace multiplication operations with shift, addition, and subtraction operations for a set of fixed coefficients. Though the first embodiment may implement additional adders, unused adders at each instant may be clock gated and data gated. In a second embodiment, a re-sampler comprises a commutator, which provides for a halving of a circuit area used by MC-CSD multipliers. In a third embodiment, a parallelized re-sampler is described. The parallelized re-sampler may reduce the circuit area by, for instance, an additional 40%. Each of the embodiments may reduce power consumption compared to other re-samplers, including other ripple-down MAC re-samplers, by, for instance, 40%. 
         [0043]      FIG. 5  is a schematic diagram of a re-sampler  500  according to an embodiment of the disclosure. The re-sampler  500  may implement the re-sampler  130  in  FIG. 1  and may be referred to as a ripple-down CSD re-sampler. The re-sampler  500  comprises a set index generator  505 , P CSD multipliers  510 , P flip-flops  520 , P accumulators  530 , P multiplexers  540 , an output flip-flop  550 , and P flip-flops  560 . P is a positive integer. The CSD multipliers  510  may be referred to as vector CSD multipliers and may be MC-CSD multipliers. The flip-flops  520  are optional and aid in timing closure of the digital logic at high clocking rates. 
         [0044]    The re-sampler  500  in  FIG. 5  is similar to the re-sampler  200  in  FIG. 2 . However, the re-sampler  500  replaces the multiplication operations of the multipliers  240  in  FIG. 2  with shift, addition, and subtraction operations of the MC-CSD multipliers  510 . Because the MC-CSD multipliers  510  handle 9 sets of coefficients, the implementation of the MC-CSD multipliers  510  may not be as spatially efficient as other multipliers such as the non-MC-CSD multipliers  240  in  FIG. 2 , which may be referred to as generic or common multipliers. For instance, if each coefficient weighting uses approximately 3 adders, then 9 sets of coefficients may require 27 adders, which may require more circuit area than generic multipliers. However, because only the adders corresponding to one set of coefficients are active at each instant, the remainder of the logic may be clock and date gated. Clock gating refers to disabling portions of circuits so that flip-flops in the disabled portions do not have to switch states, which consumes power. Data gating refers to providing a zero, or fixed, input so that the combinatorial logic does not toggle. Toggling consumes power, so a reduction in toggling reduces power consumption. 
         [0045]    Because the same input signal x(m) enters all of the MC-CSD multipliers  510 , x(m) may be treated as a vector MC-CSD multiplier that generates P outputs corresponding to x(m)*[h (P−1)N+k , . . . , h N+k , h k ] T  for k=0, 1, . . . N−1 over a clock cycle. The set index generator  505  generates the coefficient indices k. The N sets of sub-filter coefficients in the table  300  in  FIG. 3  are represented by the P-length column vectors h 0 , h 1 , . . . , h N−1 , where h k =[h (P−1)N+k , . . . , h N+k , h k ] and its I th  element is given as h k (I)=h (P−I)N+k . Typically, the L-tap filter impulse response h would be a symmetric filter so that h k =However, none of the sub-filters h k  would be symmetric except for the middle set h (N−1)/2  for an odd N. 
         [0046]      FIG. 6  is a simplified table  600  of coefficients for the MC-CSD multipliers  510  in the re-sampler  500  in  FIG. 5 . In the table  600 , sub-filters h k  and h N−k−1  have the same coefficients, but in a reverse order, namely h k (I)=h N−k−1 (P−I). For instance, the sub-filter h° has a coefficient value of 0 for a first multiplier, the sub-filter h 8  has the same coefficient value of 0 for a seventh multiplier, the sub-filter h° has a coefficient value of −49 for a second multiplier, the sub-filter h 8  has the same coefficient value of −49 for a sixth multiplier, and so on. Similarly, the sub-filter h 7  has reversed values of the sub-filter h 1 , the sub-filter h 6  has reversed values of the sub-filter h 2 , and the sub-filter h 5  has reversed values of the sub-filter h 3 . 
         [0047]      FIG. 7  is a schematic diagram of a re-sampler  700  according to another embodiment of the disclosure. The re-sampler  700  may implement the re-sampler  130  in  FIG. 1  and may also be referred to as a ripple-down CSD re-sampler. The re-sampler  700  comprises a set index generator  705 , P MC-CSD multipliers  710 , P flip-flops  720 , and a commutator  730 . P is a positive integer. The set index generator  705  generates the coefficient indices k. The commutator  730  may comprise └P/2┘ two-input commutators that either flip or do not flip the set of P inputs. A two-input commutator is a cross-bar switch. When the flip select signal is 0, then the commutator passes (x 1 , x 2 ) from its inputs to its outputs. When the flip select signal is 1, then the commutator flips (x 1 , x 2 ) to (x 2 , x 1 ) and passes (x 2 , x 1 ) from its inputs to its outputs. 
         [0048]    The re-sampler  700  exploits the commonality of coefficients in the table  600  in  FIG. 6 . Specifically, the re-sampler  700  uses the MC-CSD multipliers  710  to generate h k , but uses the commutator  730  to generate h N−k+1  by employing h k  and flipping the inputs of the commutator  730 . As shown, the MC-CSD multipliers  710  implement only ┌N/2┐ coefficients instead of N coefficients. The commutator  730  selectively flips or does not flip outputs from the flip-flops  720  depending on which sub-filter is selected. 
         [0049]    For instance, when sub-filter h k  for k&lt;└N/2┘ is selected the output vector is not flipped, and when sub-filter h k  for k≧└N/2┘ is selected the output vector is flipped. That results in nearly halving a circuit area used by the MC-CSD multipliers  710 . Alternatively, the re-sampler  700  may implement only sub-filter coefficient sets h k , where k=└N/2┘, └N/2┘+1, . . . , N−1, with an appropriately modified flip select signal. 
         [0050]    As shown, for the re-samplers  200 ,  500 ,  700 , the input components receive the same input signal x(m). Some re-samplers, for instance one of the re-samplers described in Balakrishnan, comprise input components that receive different input signals, for instance x(m−P−1), . . . , x(m). For such a re-sampler to exploit the commonality of coefficients, the re-sampler may comprise an input commutator to selectively flip the input signals x(m−k) and x(m−P−1+k). 
         [0051]    MAC-based re-samplers such as the re-samplers  200 ,  500 ,  700  may be parallelized, for instance by a factor of 2. Such a parallelized re-sampler processes two new input samples x(m) and x(m+1) in the same clock cycle. Specifically, the input samples x(m) and x(m+1) are multiplied by two different sets of sub-filter coefficients in the same clock cycle. To implement the parallelization, the re-sampler doubles the logic and thus the components to implement the logic. The doubling of the components doubles the circuit area used. 
         [0052]      FIG. 8  is a table  800  of coefficient indices for a parallelized re-sampler. The re-sampler is an M/N=8/9 re-sampler. In the table  800 , the input samples x(m+2 k) may be referred to as even input samples, and the inputs samples x(m+2 k+1) may be referred to as odd input samples. Processing windows refer to groups of two input indices. For instance, the input indices m and m+1 make up a first processing window, the input indices m+2 and m+3 make up a second processing window, and so on. In the first processing window, the input sample x(m) is scaled by coefficient set h°, while the input sample x(m+1) is scaled by coefficient set h 1 . In the second processing window, the input x(m+2) is scaled by coefficient set h 2 , while the input sample x(m+3) is scaled by coefficient set h 3 , and so on. In the first four processing windows, the even input samples use coefficient sets h 0 , h 2 , . . . , and the odd input samples use coefficient sets h 1 , h 3 , . . . . In the next processing window, the even input sample uses coefficient set h 8 , and the odd input sample uses coefficient set h 0 . In the next four processing windows, the even input samples use coefficient sets h 1 , h 3 , . . . , and the odd input samples use coefficient sets h 2 , h 4 , . . . . 
         [0053]      FIG. 9  is a simplified schematic diagram of a re-sampler  900  according to yet another embodiment of the disclosure. The re-sampler  900  may implement the re-sampler  130  in  FIG. 1  and may also be referred to as a ripple-down CSD re-sampler. The re-sampler  900  comprises an input commutator  910 , an even set index generator  915 , an even group MC-CSD multiplier  920 , an odd set index generator  925 , an odd group MC-CSD multiplier  930 , intermediate commutators  940 , and an output commutator  950 . The even group MC-CSD multiplier  920  and the odd group MC-CSD multiplier  930  may be referred to as vector CSD multipliers. The intermediate commutators  940  may have independent flip select signals. 
         [0054]    The re-sampler  900  exploits the properties described above with respect to the table  800  in  FIG. 8 . Specifically, the re-sampler  900  splits the MC-CSD multipliers into the even group MC-CSD multiplier  920  and the odd group MC-CSD multiplier  930 . The even group CSD multiplier  920  supports the even sub-filters (h 0 , h 2 , h 4 ), and the odd group CSD multiplier  930  supports the odd sub-filters (h 0 , h 1 , h 3 ). The coefficient set h 0  is common to both groups. The input commutator  910  passes even input samples and odd input samples to the even group MC-CSD multiplier  920  and the odd group MC-CSD multiplier  930  as they are, or the input commutator  910  flips the even input samples and the odd input samples. The output commutator  950  similarly processes the vector outputs of the even group MC-CSD multiplier  920  and the odd group MC-CSD multiplier  930 . 
         [0055]    Both the even group MC-CSD multiplier  920  and the odd group MC-CSD multiplier  930  support the coefficient set h 0  in order to handle the transition between processing windows. If N is even, then the duplication of a common coefficient set in the even CSD multiplier  920  and the odd CSD multiplier  930  may not be necessary. The commutator select signal determines whether the commutator  910  passes x(m) or x(m+1) to either the even CSD multiplier  920  or the odd CSD multiplier  930 . The same select signal passes to the output commutator  950 . 
         [0056]    The select signal of the input commutator  910  is zero when the even group MC-CSD multiplier  920  and the odd group MC-CSD multiplier  930  are to scale the input samples x(m+2 k) and x(m+2 k+1), respectively. Alternatively, The select signal of the commutator  910  is one when the odd group MC-CSD multiplier  930  and the even group MC-CSD multiplier  920  are to scale the inputs x(m+2 k) and x(m+2 k+1), respectively. The set index generators  915 ,  925  indicate which of the sub-filter indices k 1 , k 2  are to be selected for the even group and the odd group. For any generic M/N, the even group supports sub-filter coefficient sets h k , where k=0, 2, . . . , 2*└{┌N/2┐−1}/2┘ and the odd group supports filter coefficient sets h k , where k=0, 1, 3, . . . , 2*┌{┌N/2┐−1}/2┐−1. 
         [0057]    As a result, the re-sampler  900  reduces the circuit area by an additional 40%. That enables support for multiple re-sampler ratios such as M/N=8/9, 4/5, and 2/3, while reducing power consumption. Other re-samplers, for instance the re-samplers described in Balakrishnan, may also implement even group MC-CSD multipliers and odd group MC-CSD multipliers. 
         [0058]      FIG. 10  is a flowchart illustrating a method  1000  of re-sampling according to an embodiment of the disclosure. The re-samplers  500 ,  700 ,  900  may implement the method  1000 . At step  1010 , a first CSD multiplier receives input samples. For instance, one of the CSD multipliers  510 ,  710 ,  920 ,  930  receives input samples x(m), x(m+1), . . . . At step  1020 , a second CSD multiplier receives the input samples. For instance, another one of the CSD multipliers  510 ,  710 ,  920 ,  930  receives the input samples x(m), x(m+1), . . . . The first CSD multiplier and the second CSD multiplier may be MC-CSD multipliers. At step  1030 , coefficients are generated. At step  1040 , using the first CSD multiplier and the second CSD multiplier, the input samples are scaled with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples. For instance, one of the CSD multipliers  510 ,  710 ,  920 ,  930  and another one of the CSD multipliers  510 ,  710 ,  920 ,  930  scales input samples with coefficient vectors h 0  through h 8  as shown in the tables  600 . Finally, at step  1050 , output samples are generated based on the coefficient vector scaled input samples. For instance, the output flip-flop  550  generates the output samples y(n), y(n+1), . . . . 
         [0059]    The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.