Abstract:
A DRAM cell structure capable of high integration includes a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate, and a transistor being formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor. A method for fabricating a DRAM cell structure capable of high integration includes the steps of (a) forming a trench vertically and cylindrically in a silicon substrate, (b) forming a trench-type capacitor having a cylindrical plate electrode and a storage node electrode on a lower region of the trench, (c) forming a vertical cylindrical transistor cell structure connected to the trench-type capacitor on an upper region of the trench.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a DRAM cell structure capable of high integration and a fabrication method thereof; and, more particularly, to a vertical cylindrical DRAM cell structure capable of high integration connected to a trench-type capacitor and a fabrication method thereof.  4   
         BACKGROUND OF THE INVENTION  
         [0002]    A DRAM is a device formed by combination of many memory cells composed of a transistor and a capacitor. Recently, DRAMs are being integrated in higher density in response to demands for larger memory capacity. Therefore, techniques for reducing a memory cell size to integrate more memory cells in a confined space have been required.  
           [0003]    [0003]FIG. 1 illustrates a conventional DRAM cell structure. As shown in FIG. 1, a conventional DRAM cell structure includes a transistor device formed horizontally on a silicon substrate, and a capacitor device having a plate electrode and a storage node electrode formed on a stacked layer over the transistor device.  
           [0004]    However, the conventional horizontal DRAM cell structure shown in FIG. 1 has drawbacks. First, integration density is limited due to word-line size and length. Second, it is difficult to secure a large enough size of the capacitor for sufficient capacitance.  
         SUMMARY OF THE INVENTION  
         [0005]    It is, therefore, an object of the present invention to provide a vertical cylindrical DRAM cell structure connected to a trench-type capacitor capable of high integration and a fabrication method thereof.  
           [0006]    In accordance with one aspect of the present invention, there is provided a DRAM cell structure capable of high integration, including: a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate; a transistor formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor.  
           [0007]    In accordance with another aspect of the present invention, there is provided a method for fabricating a DRAM cell structure capable of high integration, including the steps of (a) forming a trench vertically and cylindrically in a silicon substrate; (b) forming a trench-type capacitor having a cylindrical plate electrode and a storage node electrode on a lower region of the trench; (c) forming a vertical cylindrical transistor cell structure connected to the trench-type capacitor on an upper region of the trench. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0009]    [0009]FIG. 1 illustrates a conventional DRAM cell structure;  
         [0010]    [0010]FIG. 2 depicts a silicon substrate on which a vertical cylindrical trench is formed in accordance with a preferred embodiment of the present invention;  
         [0011]    FIGS.  3 A- 3 M explain a method for fabricating a vertical cylindrical DRAM cell in accordance with a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0012]    Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.  
         [0013]    [0013]FIG. 2 illustrates a layout for fabricating a vertical cylindrical DRAM cell having a trench-type capacitor in accordance with a preferred embodiment of the present invention. First, a vertical cylindrical trench is formed on a silicon substrate  208  by using a trench mask  200  and an isolation mask  202  patterned in circular form. Next, employing a damascene method, a word-line contact is formed by using a word-line mask  206  and a bit-line mask  204 . And next, a bit-line contact plug is formed by using a bit-line contact mask  210 . Bit-line electrode material is deposited on the bit-line contact plug, and then a bit-line is formed by using a bit-line formation mask  204 .  
         [0014]    FIGS.  3 A- 3 M illustrate a method for fabricating a DRAM cell connected to a trench-type capacitor and formed vertically and cylindrically on a silicon substrate to thereby increase an integration density in accordance with a preferred embodiment of the present invention. Hereinafter, a transistor device is assumed to be n-type, but the same principle can be applied for p-type case as well.  
         [0015]    In order to form a trench for fabricating a vertical cylindrical DRAM cell in a silicon substrate as shown in FIG. 2, a buried n-well  302  is formed on a silicon substrate  300 , and then a p-well  304  is formed on the buried n-well  302  as illustrated in FIG. 3A. Next, a first oxide film  306 , a first nitride film  308  and a second oxide film  310  are sequentially deposited, and then a photoresist layer for a trench mask patterning is deposited on the second oxide layer  310 . Next, through a photolithography process and an etching process, a trench mask  312  is formed by patterning the photoresist on a portion to be etched for making a trench. Then, the second oxide film  310 , the first nitride film  308  and the first oxide film  306  are sequentially etched by using the patterned trench mask  312 .  
         [0016]    As illustrated in FIG. 3B, the trench mask  312  is then removed, and a cylindrical trench  318  for fabricating a vertical cylindrical DRAM cell is formed by etching a silicon substrate at the portion for making a trench, wherein the second oxide layer  310  is used as an etching mask. The trench etching is performed by using a high dry etching selection ratio of oxide and silicon to a depth of about several micrometers or more. Next, an LPTEOS layer  314  doped with n-type impurity, e.g., phosphorous, is deposited and coated with photoresist, and then etched back down to the p-well region  304 . Next, the photoresist is removed, the exposed LPTEOS is removed by dry etching, and then a third oxide layer  316  is deposited.  
         [0017]    As illustrated in FIG. 3C, a plate electrode  320  is then formed in the buried n-well region  302  by doping the LPTEOS layer  314  with phosphorous and diffusing the phosphorous into the silicon substrate through an annealing process. Next, the p-doped LPTEOS layer  314  and the third oxide layer  316  are removed by wet etching.  
         [0018]    Referring to FIG. 3D, a storage capacitor insulation film  322  and a storage node  324  formed by doping polysilicon are sequentially deposited on a surface of the silicon substrate of FIG. 3C. A fourth oxide layer  326  is then stacked in the capacitor-formed trench to thereby fill the trench. Next, the fourth oxide layer  326  is etched back up to the plate electrode  320  by using a high selection ratio of oxide and poly.  
         [0019]    As illustrated in FIG. 3E, a fifth oxide layer  328 , having a thickness of about several hundred angstroms, is then formed by thermal oxidation on a trench sidewall. Next, a storage node contact plug  330  is sequentially stacked to thereby fill the trench, and the fifth oxide layer  328  is etched back and then removed by wet etching.  
         [0020]    Referring to FIG. 3F, a sixth oxide film  332  is thinly formed by thermal oxidation on the trench sidewall over the storage node contact plug  330 . Next, a seventh oxide film  334  is thickly stacked on the storage node contact plug  330 , and then etched back to thereby form an insulation layer having a thickness of about several hundred angstroms or more. Next, a mask nitride film  336  is stacked on an inner surface of the sixth oxide layer  332  and then etched back.  
         [0021]    Referring to FIG. 3G, the seventh oxide film  334  is wet-etched. Next, the trench is filled with phosphorous-doped polysilsicon  335  on the storage node contact plug, and then it is etched back to thereby form a poly connector  338 .  
         [0022]    As illustrated in FIG. 3H, the poly connector layer  338  is then annealed so that phosphorous with which the poly connector material, i.e., the polysilicon, is doped diffuses into an adjacent trench sidewall silicon substrate to thereby form a source  339 . Next, the mask nitride film  336  is removed by wet etching, and an eighth oxide film  340  is thickly deposited on the poly connector  338  to thereby fill the trench and then etched back. A gate insulation film  342  is then deposited on a trench sidewall over the eighth oxide film  340 . And next, the trench over the eighth oxide film  340  is filled with polysilicon to thereby form a gate electrode  344  and an implanting process is performed to thereby form a drain  346  on a surface of the silicon substrate between consecutive gate electrodes. At this step, the gate electrode  344  is formed to protrude on the surface of the silicon substrate  
         [0023]    Referring to FIG. 3I, a caping nitride film is deposited on the entire silicon substrate, and then patterned to be removed by using a photoresist isolation mask  350  patterned through a photolithography process and an etching process, thereby exposing the drain  346 .  
         [0024]    As illustrated in FIG. 3J, the photoresist isolation mask  350  is removed, and then the silicon substrate is dry-etched by a reactive ion etching (RIE) method employing the patterned caping nitride film  348  as a hard mask, to thereby expose the buried n-well region  302 . The purpose of this etching process is isolating transistor devices in adjacent trenches from each other. A device isolation hole, being made during this etching process, preferably extends down to the buried n-well region  302 . However, it is allowable that it extends down to the self-aligned source  339 . Next, a device-isolating planarization oxide film  352  is thickly stacked in the device isolation hole, and then the silicon surface is planarized through a CMP process.  
         [0025]    Referring to FIG. 3K, the device-isolating planarization oxide film  352  and the caping nitride film  348  are sequentially dry-etched by using a photoresist word-line mask  354  patterned through a photolithography process and an etching process, to thereby expose the gate electrode  344  so that a word-line contact hole  356  is formed.  
         [0026]    As illustrated in FIG. 3L, the photoresist word-line mask  354  is then removed, and the word-line contact hole  356  is filled with word-line electrode material, e.g., poly, poly electrode or tungsten, a word-line contact  359  is formed through a CMP process, and then a planarization oxide film  358  is deposited on the word-line  359 . Next, the planarization oxide film  358  and the device-isolating planarization oxide film  352  are sequentially dry-etched by using a photoresist bit-line contact formation mask  360  patterned through a photolithography process and an etching process, to thereby expose the drain region so that a bit-line contact hole  362  is formed.  
         [0027]    Referring to FIG. 3M, the bit-line contact hole  362  is filled with bit-line electrode material, and then a contact plug  364  is formed by planarization through the CMP process. Next, bit-line electrode material  366  is deposited on the contact plug  364 . Then, performing a bit-line masking process, a bit-line is formed vertically to the word-line  359 .  
         [0028]    While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.  
         [0029]    In accordance with the present invention, a cylindrical trench is formed in a silicon substrate, and a capacitor and a transistor are formed vertically and cylindrically in the trench, to thereby reduce a restraint of word-line size and length so that a high integration can be achieved.