Abstract:
Full duplex transceivers are provided, the transceivers comprising: a transmitter section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; a receiver section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; an analog self-interference canceller that, in response to the analog baseband signals in the analog portion of the transmitter section, produces analog cancellation signals that cancel first self-interference in the analog baseband signals in the analog portion of the receiver section; and a digital self-interference canceller that, in response to the digital baseband signals in the digital portion of the transmitter section, produces digital cancellation signals that cancel second self-interference in the digital baseband signals in the digital portion of the receiver section.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/271,297, filed Dec. 27, 2015, and U.S. Provisional Patent Application No. 62/346,977, filed Jun. 7, 2016, and is a continuation-in-part of International Patent Application No. PCT/US2016/065456, filed Dec. 7, 2016, which claims the benefit of U.S. Provisional Patent Application No. 62/264,312, filed Dec. 7, 2015, U.S. Provisional Patent Application No. 62/271,297, filed Dec. 27, 2015, and U.S. Provisional Patent Application No. 62/346,977, filed Jun. 7, 2016. Each of the applications listed in the foregoing sentence is hereby incorporated by reference herein in its entirety. 
     
    
     STATEMENT REGARDING GOVERNMENT FUNDED RESEARCH 
       [0002]    This invention was made with government support under contracts FA8650-14-1-7414 and HR0011-12-1-0006 awarded by the Defense Advanced Research Projects Agency. The government has certain rights in the invention. 
     
    
     BACKGROUND 
       [0003]    Full-duplex communications, in which a transmitter and a receiver of a transceiver operate simultaneously on the same frequency band, is drawing significant interest for emerging 5G communication networks due to its potential to double network capacity compared to half-duplex communications. 
         [0004]    However, one of the biggest challenges in implementing full-duplex communications is managing self-interference. Self-interference is interference present in a receiver channel of a transceiver that is caused by signals transmitted from a transmitter channel of the transceiver. 
         [0005]    Accordingly, new mechanisms for implementing self-interference cancellation in full-duplex transceivers are desirable. 
       SUMMARY 
       [0006]    In accordance with some embodiments, full duplex transceivers are provided, the transceivers comprising: a transmitter section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; a receiver section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; an analog self-interference canceller that, in response to the analog baseband signals in the analog portion of the transmitter section, produces analog cancellation signals that cancel first self-interference in the analog baseband signals in the analog portion of the receiver section; and a digital self-interference canceller that, in response to the digital baseband signals in the digital portion of the transmitter section, produces digital cancellation signals that cancel second self-interference in the digital baseband signals in the digital portion of the receiver section. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a block diagram of an example of a full duplex transceiver incorporating an analog self-interference canceller and a digital self-interference canceller in accordance with some embodiments. 
           [0008]      FIG. 2  is a schematic of an example of a portion a full duplex transceiver that can be used as a portion of the full duplex transceiver of  FIG. 1  in accordance with some embodiments. 
           [0009]      FIG. 3  is an illustration of a non-linear tapped delay line that can be used to implement digital self-interference cancellation in a full duplex transceiver in accordance with some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    In accordance with some embodiments, mechanisms for providing self-interference cancellation in a full duplex transceiver in accordance with some embodiments are provided. In some embodiments, digital self-interferences can be provided using a non-linear tapped delay line. 
         [0011]    Turning to  FIG. 1 , an example  100  of a block diagram of a full duplex transceiver incorporating self-interference cancellation mechanisms in accordance with some embodiments is shown. As illustrated, transceiver  100  includes a digital-to-analog converter (DAC)  104 , a mixer  106 , a local oscillator generator  108 , a power amplifier (PA)  110 , an antenna interface  112 , an antenna  114 , a low-noise amplifier (LNA)  116 , a mixer  118 , an analog self-interference (SI) canceller  120 , an analog-to-digital converter (ADC)  122 , an adder  124 , and a digital self-interference (SI) canceller  126 . 
         [0012]    During operation of transceiver  100 , DAC  104  converts a signal to be transmitted from digital form to analog form resulting in a transmitter (TX) analog baseband signal  128 . The transmitter analog baseband signal is then upconverted by mixer  106  using a local oscillator from local oscillator generator  108 . The upconverted signal is then amplified by power amplifier (PA)  110 . The signal output by PA  110  is represented in  FIG. 1  by signal  130 , which includes a P TX  component, which is an amplified form of the transmitter signal, and a self-interference (SI) third-order inter-modulation (IM3) distortion component. The signal output by PA  110  is provided to antenna interface  112 , which directs the signal to antenna  114  for transmission. A signal received at antenna  114  is represented in  FIG. 1  by signal  132 , which includes a desired signal component and a noise component. The signal received at the antenna is directed by antenna interface  112  to the input of low noise amplifier  116 , which amplifies the received signal. As illustrated by signals  134 , the signals received at the antenna are combined with interference from the signal output by PA  110  that is not isolated by antenna interface  112 . Mixer  118  then downconverts the amplified signal using a local oscillator from generator  108 . Based on transmitter analog baseband signal  128 , analog self-interference canceller  120  provides a signal that cancels at least some of the self-interference in the output of mixer  118 . The combined output of mixer  118  and canceller  120  is represented by receiver (RX) analog baseband signals  136 . The RX analog baseband signal is then converted to digital form by ADC  122  and provided to adder  124 . Digital SI canceller  126 , based on signals at the input to DAC  104 , provides digital cancellation signals to adder  124  that, when added to the output of ADC  122 , further cancels the self-interference from the P TX  signal and the SI IM3 distortion. The is represented by signals  138 . 
         [0013]    DAC  104  and ADC  122  can be implemented in any suitable manner using any suitable digital-to-analog and analog-to-digital converters. 
         [0014]    In some embodiments, analog self-interference canceller  120  can be implemented as described below in connection with analog baseband self-interference canceller  228  of  FIG. 2 . 
         [0015]    Mixers  106  and  118  can be implemented in any suitable manner using any suitable mixers in some embodiments. 
         [0016]    Generator  108  can be implemented in any suitable manner using any suitable local oscillator generator in some embodiments. 
         [0017]    Power amplifier  110  can be implemented in any suitable manner using any suitable power amplifier in some embodiments. 
         [0018]    LNA  116  can be implemented in any suitable manner using any suitable low noise amplifier in some embodiments. 
         [0019]    Adder  124  can be implemented in any suitable manner using any suitable adder in some embodiments. 
         [0020]    Antenna  114  can be implemented in any suitable manner using any suitable antenna in some embodiments. 
         [0021]    Antenna interface  112  can be implemented in any suitable manner using any suitable antenna interface, such as non-reciprocal circulator or an electrical balance duplexer, in some embodiments. 
         [0022]    In some embodiments, rather than using antenna interface  112  and a single antenna  114 , two antennas  114  can be used, one connected to the output of power amplifier  110  and the other connected to the input of LNA  116 , and antenna interface  112  can be omitted. 
         [0023]    Turning to  FIG. 2 , a more detailed example  200  of portion  140  of transceiver  100  in accordance with some embodiments is shown. Box  299  represents a chip on which the encompassed components can be implemented in some embodiments. In some embodiments, such a chip can be implemented in 65 nm CMOS technology. 
         [0024]    As illustrated, transceiver portion  200  is implemented using transmit baseband buffers  202  and  204 , a transmit modulator  206 , a power amplifier  208 , a non-reciprocal circulator  210  (of which inductors  214  are a part), an antenna  212 , a circulator local oscillator (LO) generator  216 , inductors  218  and  220 , a common-gate, common-source low-noise transconductance amplifier (LNTA)  222 , a receiver (RX) LO generator  224 , a four-phase passive mixer  226 , an analog baseband (BB) self-interference canceller (SIC)  228 , transimpedance amplifiers (TIAs)  234 , and analog baseband recombination circuitry  236 . 
         [0025]    Transmit baseband buffers  202  and  204  can be implemented in any suitable manner using any suitable baseband buffers in some embodiments. 
         [0026]    Transmit modulator  206  can be implemented in any suitable manner using any suitable modulator in some embodiments. For example, in some embodiments, modulator  206  can be implemented using part number TRF370417 available from Texas Instruments (of Dallas, Tex.). 
         [0027]    Power amplifier  208  can be implemented in any suitable manner using any suitable power amplifier in some embodiments. 
         [0028]    Non-reciprocal circulator  210  can be implemented in any suitable manner using any suitable non-reciprocal circulator in some embodiments. For example, in some embodiments, non-reciprocal circulator can be implemented using non-reciprocal circulator as described in connection with  FIG. 4  of International Patent Application No. PCT/US2016/065456, filed Dec. 7, 2016, which is hereby incorporated by reference herein in its entirety. 
         [0029]    Antenna  212  can be implemented in any suitable manner using any suitable antenna in some embodiments. 
         [0030]    Inductors  218  and  220  can be implemented in any suitable manner using any suitable inductors for use with LNTA  222  in some embodiments. 
         [0031]    Common-gate, common-source low-noise transconductance amplifier (LNTA)  222  can be implemented in any suitable manner using any suitable LNTA in some embodiments. For example, in some embodiments, LNTA  222  can be implemented as shown in the schematic of  FIG. 2 . 
         [0032]    Four-phase passive mixer  226  can be any suitable four-phase passive mixer in some embodiments. For example, in some embodiments, mixer  226  can be implemented as shown in the schematic of  FIG. 2 . 
         [0033]    Transimpedance amplifiers (TIAs)  234  can be implemented in any suitable manner using any suitable TIAs in some embodiments. For example, in some embodiments, TIAs  234  can be implemented as shown in the schematic of  FIG. 2 . 
         [0034]    Analog baseband recombination circuitry  236  can be implemented in any suitable manner using any suitable analog baseband recombination circuitry in some embodiments. For example, recombination circuitry  236  can be implemented using voltage to current converting g m  cells as shown in circuitry 734 of FIG. 7 of International Patent Application No. PCT/US2016/065456, filed Dec. 7, 2016, which is hereby incorporated by reference herein in its entirety. The recombination circuit may be formed from multiple pairs of g m s to form I/Q outputs of the receiver. 
         [0035]    During operation, transmit signals received at baseband I and Q inputs  201  are amplified by buffers  202  and  204 , modulated by modulator  206 , amplified by amplifier  208 , directed to antenna  212  by circulator  210 , and transmitted by antenna  212 . Signals received at antenna  212  are directed by circulator  210  to LNTA  222 , amplified by LNTA  222 , down-converted by mixer  226 , amplified by TIAs  234 , converted to I and Q baseband outputs by circuitry  236 , and output at outputs  203 . Analog BB SIC  228  taps from the transmit baseband signals between the baseband buffers  202  and  204 , adjusts the amplitude and the phase of the tapped signals, and injects cancellation currents at the inputs to TIA  234 . 
         [0036]    Amplitude and phase scaling in analog BB SIC  228  is achieved through two five-bit digitally-controlled phase rotators  230  and  232  injecting into the I-paths and the Q-paths of the RX analog BB, respectively. Each phase rotator can include 31 (or any other suitable number) identical cells with independent controls  238  (these controls can determine the contribution of each cell to the analog BB SIC current). Each cell, which can be implemented in any suitable manner in some embodiments (e.g., such as shown in box  229 ), of the phase rotator adopts a noise-canceling common-gate (CG) and common-source (CS) topology, allowing partial cancellation of the noise from the CG devices (dependent on the phase rotator setting at controls  238 ). 
         [0037]    Circulator  210  can be implemented in any suitable manner in some embodiments, such as described in connection with  FIGS. 4 and 6  of International Patent Application No. PCT/US2016/065456, filed Dec. 7, 2016, which is hereby incorporated by reference herein in its entirety. 
         [0038]    Circulator  210  receives from circulator LO generator  216  two sets of eight non-overlapping clock signals each with 12.5% duty cycle. These clock signals are used to control the switches in the eight paths of the N-path filter of circulator  210 . 
         [0039]    Generator  216  can be implemented in any suitable manner in some embodiments. For example, in some embodiments, to generate these clock signals, generator  216  receives two differential (0 degree and 180 degree) input clocks that run at four times the desired commutation frequency. A divide-by-two frequency-divider circuit  244  generates four quadrature clocks with 0 degree, 90 degree, 180 degree, and 270 degree phase relationship. These four clock signals drive two parallel paths for the two sets of switches. 
         [0040]    In a first of the two paths, a programmable phase shifter  246  that allows for arbitrary staggering between the two commutating switch sets is provided. Programmable phase shifter  246  enables switching between −90 degree and +90 degree staggering, which allows dynamic reconfiguration of the circulation direction. The phase shifter also allows for fine tuning of the staggered phase shift to optimize the transmission loss in the circulation direction and isolation in the reverse direction. After phase shifting, another divide-by-two circuit  248  and a non-overlapping 12.5% duty-cycle clock generation circuit  250  create the clock signals that control the commutating transistor switches in the first path. 
         [0041]    In a second of the two paths, directly after first divide-by-two frequency-divider circuit  244 , another divide-by-two circuit  252  and a non-overlapping 12.5% duty-cycle clock generation circuit  254  create the clock signals that control the commutating transistor switches in the second path. 
         [0042]    Divide-by-two circuits  244 ,  248 , and  252 , phase shifter  246 , and non-overlapping 12.5% duty-cycle clock generation circuits  250  and  254  can be implemented in any suitable manner. 
         [0043]    In some embodiments, circulator LO generator  216  may use static 90 degree phase-shifts or digital phase interpolators that preserve the square-wave nature of the clock. 
         [0044]    At RX LO port  242 , RX LO generator  224  receives two differential (0 degree and 180 degree) input clocks that run at two times the operating frequency of the receiver (e.g., 750 MHz). A divide-by-two frequency-divider circuit (which can be implemented in any suitable manner) in generator  224  generates four quadrature clocks with 0 degree, 90 degree, 180 degree, and 270 degree phase relationship. 
         [0045]    In some embodiments, although not shown, an impedance tuner can be provided to counter reflections due to antenna impedance mismatch. The tuner can be used at the ANT port for joint optimization of SIC bandwidth (BW) between the circulator and the analog BB canceller. 
         [0046]    In some embodiments, transceivers take advantage of inherent down-conversion of an N-path filter to merge a circulator and a receiver. 
         [0047]    Turning back to  FIG. 1 , in accordance with some embodiments, digital self-interference canceller  126  can be implemented using a non-linear tapped delay line. In some embodiments, a non-linear tapped delay line can be implemented in any suitable hardware processor (such as a digital signal processor, microprocessor, etc.) that is programmed to perform a non-linear tapped delay line function. For example, in accordance with some embodiments, such a non-linear tapped delay line can be implemented as illustrated in  FIG. 3 , which essentially models the self-interference channel in digital as a truncated Volterra series: 
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         [0000]    where y[n] is the digital SI canceller output, x[n] and x[n−k] (k represents the delay index) are the current and past TX digital baseband signals, N corresponds to the maximum delay in the modeled SI channel, and h i [k] (i=1, 2, 3, . . . , p) is the i-th order digital canceller coefficient for delay index of k. 
         [0048]    In some embodiments, truncating the Volterra series can be used to reduce the digital SI canceller complexity to a manageable level. For example, in some embodiments, non-linear terms up to 4th order (i.e., p=4) can be considered with a delay spread length of 41 samples (i.e., N=40), resulting in 164 total unknown canceller coefficients. 
         [0049]    In some embodiments, the digital SI canceller coefficients can be determined using a two-tone pilot signal. More particularly, given an M-length pilot sequence Y (y[0], y[1], . . . , y[M−1]) and a N-length nonlinear coefficient sequence H (h 1 [0], h 1 [1], . . . ), and taking noise into account, we have the following linear equation: 
         [0000]    
       
      
       Y=XH+n  
      
     
         [0000]    where X is a M*N matrix that consists of TX digital baseband signals (x[0], x[1], x 2 [0], x 3 [0], . . . ), and n is the noise from the SI channel. The goal is to find a Ĥ that minimizes |XĤ−Y|. When the received data points are more than the number of unknown coefficients (M&gt;N), this becomes a least-squares problem, and Ĥ can be found as: 
         [0000]    
       
      
       Ĥ=A 
       + 
       Y  
      
     
         [0000]    where A + is the pseudo-inverse of matrix A. 
         [0050]    Although the disclosed subject matter has been described and illustrated in the foregoing illustrative implementations, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter can be made without departing from the spirit and scope of the disclosed subject matter, which is limited only be the claims that follow. Features of the disclosed implementations can be combined and rearranged in various ways.