Abstract:
A power amplifier circuit whose performance is optimized by operating its stages in substantially close to a Class B mode by reducing quiescent current during low driver signal levels. As the driver signal amplitude increases, the operation of the amplifier is configured to dynamically adjust to be in a Class AB mode, thereby increasing the power efficiency of the overall circuit at kiw drive levels. A further enhancement to the power amplifier circuit includes a temperature compensation circuit to adjust the bias of the amplifier so as to stabilize the performance in a wide temperature range.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to amplifier circuitry and, more particularly, to a low bias current and temperature compensation current mirror for use in a linear power amplifier.  
         BACKGROUND OF THE INVENTION  
         [0002]    Power amplifiers are categorized into several classes of operation. Some of these classes include Class-A, Class-B and Class-AB. A Class A power amplifier is defined as an amplifier with or without negative feedback, and in its ideal case is characterized with the greatest fidelity in faithfully amplifying an input signal with the least distortion. It conducts output current throughout 100% of the input signal waveform. In other words it exhibits a conduction angle of exactly 2 π radians. In most cases it exhibits the greatest gain of all power amplifier classes. Another characteristic of the Class A amplifier is that its DC bias point is generally selected to be at ½ the transistor&#39;s peak current capability and ½ its peak voltage capability. It is however the least efficient of all the classes of amplifiers, in as much that in ideal cases the power delivered to the load is typically only 50% of the D.C. power used.  
           [0003]    A Class AB amplifier is defined in the ideal case as a power amplifier that has an output current flow for more than half, but less than all, of the input cycle. In other words it exhibits a conduction angle between π and 2 π radians. See, e.g., Gilbilisco, Stan, Ed. Amateur Radio Encyclopedia, TAB Books, 1994. Another characteristic of a Class AB amplifier is that it is generally biased at less than ½ of the transistor&#39;s peak current capability. The advantages of a Class AB amplifier include improved high power efficiency over a Class A type amplifier and improved efficiency at low drive levels. The drawbacks of Class AB power amplifiers include the generation of an output signal which is not an exact linear reproduction of the input waveform, lower gain than that of a Class A type, continuous current drain, and lower efficiency compared to other amplifier types.  
           [0004]    An ideal Class B amplifier is defined as an amplifier that has output current flow for ½ the cycle of the input signal wave form. In other words it exhibits a conduction angle of π radians. The advantages of a Class B amplifier are improved high power efficiency over Class A and AB type amplifiers and improved efficiency at low drive levels. The drawbacks of a Class B amplifier include even higher distortion and lower gain compared to Class A and AB amplifiers.  
           [0005]    Class A, AB and B amplifiers are typically used in the transmitters of cellular mobile terminals. The Class selected is often dictated by the communications standard employed by the terminal. Typically a GSM type handset will utilize a Class B amplifier stage as the final amplifier of the transmitter. This is because the GMSK standard employed in a GSM handset embeds the voice or data being transmitted in the phase angle of the signal, which is somemtimes referred to as a constant envelope signal. Such signals are more tolerant to amplitude distortion during the amplification and transmission process. One benefit of using a Class B amplifier in these handsets is that it results in longer battery life and thus longer talk times.  
           [0006]    In an NADC or CDMA cellular mobile terminal the final amplifier in the transmitter chain is typically a Class AB type amplifier. This is because the data or voice being transmitted is encoded in both the amplitude and phase of the signal. This results in a signal with a non-constant envelope, requiring a transmitter having a minimal amount of both amplitude and phase distortion.  
           [0007]    Although Class AB operation improves power efficiency at the cost of some linearity of signal amplification, it has become the amplifier class of choice for non-constant envelope mobile cellular and PCS transmitters. Unlike the Class B type amplifier, the Class AB requires a quiescent current bias. And although it exhibits better efficiency at low drive levels than a Class A type amplifier, the optimum low drive efficiency is limited by the linearity requirement under higher drive. In general, as power efficiency improves under high drive, linearity will suffer. The inverse relationship of efficiency at high drive, low quiescent bias, high efficiency at low drive and the need for high drive linearity makes the selection of a quiescent bias point a critical design parameter. The operation of the Bipolar or FET transistors at low quiescent bias points also exposes the amplifier to greater variability in performance at both low and high operating temperatures.  
           [0008]    Ideally, a power amplifier for use in mobile terminal equipment such as cellular or PCS communication devices employing a non-constant envelope modulation scheme should amplify the input signal linearly with minimal distortion of the signal and with optimum efficiency across a wide range of drive levels.  
           [0009]    In practice, balancing linearity and efficiency across all drive conditions is difficult. Accordingly, a need exists for an improved biasing arrangement that dynamically adjusts the operating mode of the power amplifier as a fimction of drive signal, temperature or other relevant factors. Such a biasing arrangement would both eliminate excessive power dissipation in the output stages at low drive levels and minimize distortion over a broad range of drive levels.  
         SUMMARY OF THE INVENTION  
         [0010]    In one aspect, the present invention comprises an amplifier biasing circuit. The biasing circuit is configured to set a bias point to operate the amplifier in a deep Class AB mode or an almost Class B mode (i.e., a mode substantially close to a Class B mode) during low drive level (quiescent current) conditions. The depth of the Class AB mode is bounded by the worst case allowable distortion at those drive levels. When the drive level increases, the biasing circuit dynamically adjusts the bias point in such a manner that the amplifier operates in a Class AB mode and allows the amplifier to accommodate high drive levels, again bounded by the worst case allowable distortion. Other parameters may be used alternatively or in addition to drive level to adjust the amplification mode. For example, distortion levels may be detected, by means that would be apparent to those of ordinary skill in this field, and may be used to adjust the bias point or other parameters in order to dynamically modify the amplification mode.  
           [0011]    In another aspect, the present invention comprises a circuit to achieve temperature compensation. The temperature compensation circuit is configured to adjust the bias point of the amplifier over a temperature range. In a yet another aspect, the invention is directed to a monolithic integrated circuit comprising the biasing circuit.  
           [0012]    In a further aspect, the invention is a method of dynamically adjusting the bias points of a multi-stage amplifying circuit, comprising the steps of detecting the drive level at a driver stage of the amplifying circuit and dynamically adjusting the bias points of a single stage or all of the stages of the entire multi-stage amplifying circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    These and other objects, features and advantages of the present invention will be more readily apparent from the following detailed description of the preferred embodiments, where like numerals designate like parts, in which,  
         [0014]    [0014]FIG. 1 is a block schematic of a preferred embodiment of the present invention;  
         [0015]    [0015]FIG. 2 is a detailed schematic of a preferred embodiment of the present invention;  
         [0016]    [0016]FIG. 3A shows the characteristics of the V tss  versus peak AC swing;  
         [0017]    [0017]FIG. 3B shows the output power P OUT , Gain, and efficiency characteristics of a temperature compensated power amplifier device constructed according to the principles of the present invention, and contrasted with uncompensated devices; and  
         [0018]    [0018]FIG. 4 is a characteristic of five devices in accordance with the present invention wherein the bias current l dq  is shown as temperature varies between −30° C. and +110° C.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]    [0019]FIG. 1 illustrates a linear power amplifier including the novel dynamic bias features of the present invention. The amplifier includes a pre-amplifier stage  110 , a driver amplifier stage  120 , and an output amplifier stage  130 . In a preferred embodiment, the output of the driver amplifier stage  120  is coupled to a driver output detector  140 . A bias adjustor circuit  150  in accordance with the present invention is coupled to the driver ouptut detector  140 . Additionally, the output of the bias adjustor circuit  150  is coupled to the three-stage amplifier circuit via a coupling circuit comprising resistors R′ and R″. Preferably resistors R′ and R″ are each 2KΩ. Temperature compensation circuit  160  is coupled to the bias adjustor circuit  150 .  
         [0020]    Each of the three stages  110 ,  120 ,  130  is preferably comprised of a depletion mode Gallium Arsenide (GaAs) Field Effect Transistor (FET) gain amplifier. In general, the depletion mode FET current characteristics are such that it draws maximum current (I dss ) when its gate-to-source voltage (V gs ) is zero, and minimum current (zero) when its gate-to-source voltage is negative Vp. The various modes of operation, i.e., Class A, Class B and Class AB, are achieved by applying a suitable amount of gate-to-source voltage. Thus, the modes of operation can be defined by the percentage of the maximum current drawn at each stage.  
         [0021]    In a preferred embodiment, the pre-amplifier stage  110  is designed to operate in a Class A mode and primarily functions as a gain stage. The driver amplifier  120  is configured to operate in a Class AB mode. The output amplifier  130  is configured to operate in a Class AB mode or substantially close to a Class B mode.  
         [0022]    Referring now to FIG. 2, in a preferred embodiment, the driver output detector circuit  140  comprises diode D 1 , resistor R 1 , capacitor C 1 , filter capacitor C 2  and resistive divider comprising resistors R 2  and R 3 .  
         [0023]    The dynamic bias adjustor circuit  150  preferably comprises a pair of Field Effect Transistors (FET) Q 3  and Q 4  considered a reference Field Effect Transistor. Q 3  is bias-coupled to the driver output detector circuit  140 . The drain of Q 3  is preferably coupled to a current limiting resistor R o . In one embodiment, the source of Q 3  is coupled to ground. In an alternative embodiment, the source of Q 3  is coupled to ground via a resistor of suitable size.  
         [0024]    A source-follower circuit, preferably comprising FET Q 5  is coupled to both Q 3  and Q 4  (the reference FET). The source follower is provided with a reference voltage, V refB , applied at the gate of Q 5 . A plurality of diodes and resistors form a level-shifting circuit  170 . In a preferred embodiment, four diodes D 2 , D 3 , D 4 , D 5  and resistor Rs form a levelshifting circuit  170  to produce a combined voltage level drop of about 2.6V. A FET Q 6  with its gate and source tied together acts as a current source establishing the current through diodes D 2 , D 3 , D 4  and D 5 . It is operatively coupled to the level-shifting circuit  170  as shown.  
         [0025]    The temperature compensation circuit  160  preferably comprises an FET Q 7  and a plurality of diodes connected to its gate. In a preferred embodiment, two diodes, D 6  and D 7  are used.  
       OPERATION OF THE CIRCUIT  
       [0026]    One aspect of the present invention is that a master-slave relationship is established between the driver stage  120  and the output stage  130  of the multi-stage power amplifier of FIG. 1. As the driver stage  120  detects a need to generate a larger AC output voltage, it instructs itself and the other stages in the power amplifier to alter their operating modes from a deep Class AB or B mode to a Class AB mode. Thus, the multi-stage power amplifier dynamically adjusts its bias point to deliver optimum efficiency across a broad range of drive level conditions. It has been found that this approach additionally reduces the required idle (quiescent) current by about 60%. Further, this invention minimizes or extends the gain compression characteristics typically exhibited by fixed Class AB or Class B mode power amplifiers. Moreover, the present invention controls and stabilizes the bias point of a multi-stage power amplifier over a wide temperature range of −30° C. to +110° C.  
         [0027]    The driver output detector circuit  140  detects the alternating voltage (AC) signal swing at the driver output and generates a negative Direct Current (DC) voltage proportional to the peak AC swing V ac  (i.e., the voltage range from peak-to-peak). The capacitor C 1  filters out the fundamental frequency component of V ac  and the resistive divider comprising resistors R 2  and R 3  determines the slope of the relationship between the peak AC voltage V ac  and the DC output voltage (V tss ), as well as the maximum value that V tss  can reach. FIG. 3A shows the characteristics of the V tss  versus peak AC power (P in ). The voltage V tss  obtained at the driver output detector is applied to the gate of Q 3 . This gate voltage controls current I l  through Resistor R o . Change in the current I l  results in a change in the voltage V refB  applied at the source follower Q 5 . The output of the source follower Q 5  is level-shifted by the level-shifting circuit  170  to the appropriate gate-tosource voltage V gs . V gs  is used to set the operating mode of the three stages  110 ,  120  and  130  of the power amplifier.  
         [0028]    At no drive or very low drive level conditions at the input of the pre-amplifier stage  110 , the peak AC signal at the output of the driver stage  120  is very small or zero. Therefore, voltage V tss  is also very small or zero. This voltage, V tss , is applied to the gate of the transistor Q 3 . This forces Q 3  to draw a maximum current, causing the voltage V refB  to drop. The drop in V refB  forces the gate-to-source voltage, V gs , for all the stages, to become more negative, thereby making them draw less current. This pushes the operating mode of the output stage of the power amplifier towards a Class B or substantially close to a Class B mode. Operating each power amplifier stage at low currents increases the power-added efficiency of the amplifier and reduces the overall DC operating current at very low drive levels.  
         [0029]    As the drive level to the pre-amplifier stage  110  increases, the driver&#39;s peak AC output voltage V ac  increases. When the peak AC output voltage V ac  exceeds approximately 0.65 V (which is the forward bias voltage drop for a Gallium Arsenide diode), the driver output detector  140  will begin to generate a negative voltage proportional to the peak AC output voltage. As the drive is increased, this voltage becomes more and more negative and approaches the maximum level of DC voltage, which is determined by the resistor R 2 . As V tss  increases, the transistor Q 3  draws less current, causing an increase in the voltage V refB . This increase in voltage in turn increases the voltage Vgs, thereby shifting the bias point of the amplifier stages toward a Class AB mode. Thus, an efficient operation with minimal spectral distortion is achieved under large signal conditions.  
         [0030]    A further feature of the circuit presented here is temperature compensation circuit  160 . The plurality of diodes D 6  and D 7  are configured to bias the transistor Q 7  close to pinch off (Vp), i.e., the point at which Q 7  permits current flow. A negative voltage, supplied by a series resistor Rref connected to Vss is also used to bias the transistor Q 7 . The operating point of transistor Q 7  is similar to that of the output stage  130  of the amplifier. Diodes D 6  and D 7  are selected such that they establish the required rate of change in the voltage drop across them versus temperature. Transistor Q 7  and resistor Rref are selected such that the required slope in temperature compensation is achieved.  
         [0031]    As temperature increases, the voltage drop across the pair of diodes decreases causing the transistor Q 7  to draw more current. This creates a voltage drop in V refB  which is level shifted to Vg causing it also to become more negative, in turn causing the three stages of the amplifier to draw less current and maintain the decreased current level. An opposite result occurs when the temperature decreases. FIG. 3B shows the output power P OUT , Gain, and efficiency characteristics of a temperature-compensated power amplifier constructed according to the principles of the present invention. FIG. 4 illustrates the variation of the bias current I dq  versus temperature for five devices in accordance with the present invention, wherein the bias current I dq  is shown as temperature varies between −30° C. and +110° C. The figure illustrates that the amplifier&#39;s bias point can be controlled using the temperature compensation circuit described above. Also shown for comparison are plots for two uncompensated circuits in which the bias point changes linearly with temperature.  
         [0032]    The embodiments described herein are merely illustrative and not intended to limit the scope of the invention. One skilled in the art may make various changes, rearrangements and modifications without substantially departing from the principles of the invention. For example, a bias adjustment in accordance with the present invention can be achieved by detecting increases or decreases in distortion of the output signal (e.g., by comparing the input signal to the output signal). To reduce AM-AM distortion of a non-constant envelope signal, the instantaneous output AC swing can be detected and the bias point can be dynamically adjusted in order to minimize gain compression (i.e., change from Class B mode to Class AB mode). This would result in reduced AM-AM distortion during the high instantaneous voltage peaks. Alternatively, in another example the output AC voltage swing can be detected to monitor substantial changes in output loading conditions. Variations in load conditions can result in substantial increases in peak output AC voltage swings that can be excessive and cause permanent damage to the output stage. These peak AC swings can be detected and an appropriate bias point change can be applied in order to either turn off the power amplifier or substantially reduce the overall power amplifier gain (i.e., change from Class AB mode to Class B mode).  
         [0033]    Also, certain portions of the described circuitry can be modified to include discrete components, whereas the remaining portion can be etched into a monolithic integrated circuit. Additionally, the materials described herein may be changed. Accordingly, all such deviations and departures should be interpreted to be within the spirit and scope of the following claims.