Abstract:
A capacitive displacement type transducer, wherein the oscillation frequency of a self-excited oscillator circuit including a pair of differential capacitors formed with a movable electrode disposed between two outer electrodes is counted by a counter, the output level of the counter is reversed each time a certain count is attained to cause the differential capacitances to be switched alternatively, and to make identical the respective reversal periods, and application voltage to be applied to the differential capacitors being controlled by an integrator, and a voltage relating to the output of the integrator being applied through a fixed impedance to the movable electrode, thereby eliminating fixed capacitances formed across the difference capacitors. Also, a voltage generated by dividing and averaging the output level of the counter by use of a certain pulse duration of a monostable circuit operating in synchronism with a counter, is used to compensate for static pressure changes. Also, a temperature sensing element is included in a converting section to perform temperature correction. The circuit may be used in a two wire transmission system. The circuit improves upon the prior art by eliminating heretofore used complex circuits, thereby increasing reliability, efficiency and reducing size.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     This invention relates to a capacitive displacement transducer used for converting a displacement caused by a change of a physical quantity, such as pressure, into an electrical signal using electrostatic capacitances; and, more particularly, to a novel capacitive displacement transducer which is capable of eliminating adverse influence due to distributed capacitance, such as appearing between an electrode and a casing, to fixed capacitances, such as appearing between electrodes, and the like, and furthermore, which is capable of compensating for zero point fluctuations and span fluctuations, such as caused by changes in ambient temperature and static pressure. 
     2. Description of the Prior Art 
     Capacitive displacement transducers of the above type have been used, for example, to detect flow rate, pressures, etc, wherein the quantity to be measured causes changes of capacitance which are then converted into electrical signals which are in turn transmitted to remote receiving stations. 
     However, prior capacitive displacement transducers are deficient in that since there exists distributed capacitances between fixed and movable electrodes and a body forming the casing and/or between the fixed and movable electrodes, the conversion characteristics exhibit non-linearity and/or error of measurement arising from such distributed capacitances. 
     One solution to such deficiency is proposed in Japan Patent Application Ser. No. 57-26711 entitled &#34;Capacitive Displacement Transducer&#34; and corresponding U.S. Pat. No. 4,387,601 and is described herein in FIGS. 1, 2, 3 and 4. 
     FIG. 1 depicts a sensor section of a capacitive displacement transducer comprising a body 10 in the form of a single chamber configuration having two diaphragms 11, 12 disposed on either end surface of body 10 for receiving pressures P H  and P L  (see arrows) whose peripheries are welded to body 10. A hollow chamber surrounded by a through hole 13 bored in body 10 and by diaphragms 11,12 is filled with a sealing liquid 14, such as, for example, silicone oil. 
     In the central portion of the hollow chamber there are arranged a movable electrode 16 and fixed electrodes 17,18 disposed opposite to movable electrode 16 to form electrostatic capacitances C 1  and C 2 . Each of these electrodes 16,17, 18, is supported at one end thereof by an insulating material disposed in body 10. A rod 19 passing through the hollow chamber couples together diaphragm 11, 12 at their central portions. The central portion of rod 19 is secured to movable electrode 16 in the inside of an electrode chamber. Displacement of diaphragms 11,12, in response to a differential pressure (P H  -P L ), is transferred to movable electrode 16 to thereby differentially displace capacitances C 1  and C 2 . 
     FIG. 2 is an electrical equivalent circuit diagram of the sensor section of FIG. 1. Between movable electrode 16 and body 10 is formed a distributed capacitance C s . Between movable electrode 16 and fixed electrode 17,18 are formed fixed capacitances C F . These capacitances do not change regardless of the differential pressure (P H  -P L ). On the other hand, capacitances C 1 , C 2  have capacitances which vary differentially in response to the differential pressure (P H  -P L ). 
     FIG. 3 depicts a displacement converting section for converting differential pressure into an electrical signal corresponding thereto, using the sensor section of FIG. 1, wherein the connection point, between capacitances C 1  and C 2 , is connected to the input end (B) of an inverter G 1 . Between the output end (C) and the input end (B) of inverter G 1  is connected a constant value current limiting circuit CC 1  in a negative feedback circuit. Output end (C) of inverter G 1  is connected first to input end C L  of an n-bit counter CT 1 , whose output end Q n  is connected through a NAND gate to fixed electrode 17 to form a first electrode of capacitor C 1 , and second through an inverter G 3  and a NAND gate G 4  to fixed electrode 18 to form a second electrode of capacitor C 2 . The other input end of each of NAND gates G 2  and G 4  is connected to output end (C) of inverter G 1 . 
     A first positive feedback loop acting on inverter G 1  is formed by NAND gate G 2  and capacitance C 1 . A second positive feedback loop acting on inverter G 1  is formed by NAND gate G 4  and capacitance C 2 . These feedback loops are alternately switched by means of the output of counter CT 1  through NAND gates G 2 ,G 4  to sustain oscillation. The output (Q n ) of counter CT 1  is smoothed by a filter circuit FC 1 . 
     The operation of the foregoing will now be described with reference to FIG. 4 and ignoring fixed capacitance C F  to simplify description. As shown in FIG. 4, line (A), when the output (A) of NAND gage G 2  is at a high level H (H will be referred to herein as a high level) and provides a voltage +V z , by its leading edge the composite capacitance C t , comprising capacitance C 1 , distributed capacitance C s  and capacitance C 2 , is charged in series, and the potential of the input end of inverter G 1  reaches up quickly to a certain voltage and rises substantially vertically as shown in FIG. 4, line (B). Consequently, a change e 1  of the terminal voltage of distributed capacitance C s , evaluated while taking a threshold level V TH  of inverter G 1  as a reference, is represented by the following equation: ##EQU1## 
     At this moment, the output (C) of inverter G 1  is at a low level L (L will be referred to herein as a low level). Thus, since the constant value current limiting circuit CC 1  is connected between the input (B) and the output (C) ends of inverter G 1 , the charges stored in distributed capacitance C s  and capacitance C 2  start immediately to discharge through constant value current limiting circuit CC 1  and the output impedance of inverter G 1 . However, since a discharge current i, caused by the foregoing discharge action, is restricted to a certain value by constant value current limiting circuit CC 1 , the voltage at the input end of inverter G 1  is lowered linearly, as shown in FIG. 4, line (B). A discharge time t 1  required for that voltage to go down to threshold level V TH  is given by the following. 
     
         it.sub.1 =e.sub.1 (C.sub.1 +C.sub.t)                       (2) 
    
     By combining equations (1) and (2), the following is obtained. ##EQU2## 
     When that voltage goes down to threshold level V TH  of inverter G 1 , the output (C) of inverter G 1  is inverted and assumes the H level (i.e. high level). (See FIG. 4, line (C)). As a result, output (A) and NAND gate G 2  assumes a low level L, and the voltage at the input end of inverter G 1  takes a value e 1  &#39; identical to that given by equation (1), but opposite in polarity. Thereafter, discharge action of opposite polarity takes place linearly by means of constant value current limiting circuit CC 1 . Subsequently, when threshold level V TH  of inverter G 1  is attained, output (C) of inverter G 1  is inverted, as shown in FIG. 4, line (C). Since this discharge action of opposite polarity takes place also with current i of a certain value, discharge time t 1  &#39; becomes identical to t 1 , namely, 
     
         t.sub.1 =t.sub.1 &#39;                                         (4) 
    
     The foregoing relationships are maintained even after counter CT 1  has counted a given number and the circuit has been switched to the side of capacitor C 2  by means of the output of counter CT 1 . Thus, the following equation holds. ##EQU3## 
     Therefore, the H period of a pulse signal obtained from output Q n  of counter CT 1  corresponds to capacitor C 1  and the L period to capacitor C 2 . By averaging these periods using filter circuit FC 1  there is obtained a calculated result, C 1  /(C 1  +C 2 ) related to the duty ratio of the pulse signal. This calcuated result gives a value proportional to the displacement of movable electrode 16, i.e. the differential pressure (P H  -P L ). In addition, distributed capacitance C s  is eliminated. 
     For reference, the fixed capacitance C F  existing across the capacitances C 1  and C 2  can be eliminated by connecting fixed condensers in parallel across circuit CC 1  and making their capacitances identical to those of the fixed capacitance C F . 
     Further, to compensate for any error resulting from change of ambient temperature or static pressure on the sensor section, the conventional displacement transducer is equipped with an independent temperature sensor for measuring the temperature of body 10 and another independent pressure sensor for measuring the pressure, i.e. static pressure, of the sealing liquid 14. Specifically, the outputs of these sensors are applied to a compesation voltage generating circuit and converted thereby into a zero compensation temperature signal and a zero compensation span signal. These zero compensation signals are algebraically added to the output of an arithmetic circuit for adding and calculating the differential pressure (P H  -P L ), whereby a fluctuation of the zero point resulting from a fluctuation of temperature of static pressure is compensated. 
     In case a span fluctuation resulting from a fluctuation of temperature or static pressure is not negligible, a span compensation temperature signal and a span compensation pressure signal are generated by the foregoing compensation voltage generating circuit to change the voltage/current conversion gain of an output circuit and to thereby compensate for fluctuation of the span. 
     To perform such compensation, the temperature sensor and pressure sensor must be located inside body 10. A conventional system having a temperature sensor disposed inside a body is disclosed, for example, in Japan UM Laid Open No. 55-13317, and another conventional system having a pressure sensor disposed inside a body is disclosed, for example in Japan Laid Open No. 54-67480. 
     Although the transducer shown in FIGS. 1-3, is capable of eliminating adverse influences due to distributed capacitance C s  and fixed capacitance C F , disadvantageously, signals relating to the H time duration and the L time duration of the output of counter CT 1 , which are proporational to the capacitances of capacitors C 1  and C 2 , are determined depending upon the constant value current characteristics of limiting circuit CC 1 . Thus, if the performance of constant value current limiting circuit CC 1  is degraded, errors are likely to be produced. For example, if circuit CC 1  is degraded and a degradation resistance R cc  indicated by the dotted line in FIG. 3 is equivalently formed in the circuit, voltage changes e 1  and e 2  at the input end (B) of inverter G 1  arising when the circuit is switched over to the side of capacitor C 1  and to the side of capacitor C 2  become different from each other. Thus, current flowing through degradation resistor R cc , while bypassing constant value current limiting circuit CC 1 , differs between the side of capacitor C 1  and the side of capacitor C 2 , and accordingly produces an error. 
     Furthermore, to eliminate fixed capacitance C F , fixed condensers are inserted across either end of constant value current limiting circuit CC 1 . However, practically, stray capacitances are also formed at either end of circuit CC 1 . These capacitances change their capacitances in response to temperature variations. Thus, it is impossible to eliminate completely the fixed capacitance C F  and therefore errors are produced due to non-linearity. 
     Moreover, disadvantageously, the conventional transducer includes a temperature sensor and a pressure sensor disposed in the body in order to compensate for errors caused by changes in ambient temperature and static pressure. Thus, the conventional configuration of the sensor section is complicated and expensive. 
     Thus, in the prior art, there is a need for an inexpensive, reliable and simple displacement type transducer which can compensate for changes in ambient temperature and static pressure. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the invention is to overcome the aforementioned and other defects, deficiencies and disadvantages of the prior art. 
     Another object is to eliminate unwanted distributed and fixed capacitances by forming a discharge circuit without using complex circuitry, such as the constant value current limiting circuit; and to compensate for the zero point and span deviations due to changes of ambient temperature and static pressure by the use of information contained in a differential signal. 
     The foregoing and other objects are attined by the invention which encompasses a capacitive displacement transducer comprising a first capacitor and a second capacitor comprising first and second electrodes disposed opposite a movable electrode and having capacitances which change differentially in response to a physical displacement to be detected moving the movable electrode; amplifying means for detecting the potential of the movable electrode; negative feedback means for supplying an inverted current to the input end of the amplifying means; counting means for counting change of the output level of the amplifying means; integrating means for integrating the output of the counting means; first switch means for switching, by means of the output of the amplifying means and the output of the counting means, and for applying a voltage relating to the output of the integrating means and a reference voltage to the first capacitor; second switch means for switching, by means of the output of the amplifying means the output of the counting means, and for applying the voltage relating to the output of the integrating means and a source voltage to the second capacitor; and fixed capacitor correcting means for applying a voltage relating to the difference between the source and the voltage relating to the output of the integrating means to the movable electrode through a fixed resistor. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a sectional view depicting a sensor section of a conventional capacitive displacement transducer. 
     FIG. 2 is an electrical equivalent circuit of the circuit of FIG. 1. 
     FIG. 3 is a circuit diagram depicting a displacement converting section combined with the sensor section of FIG. 1. 
     FIG. 4, comprising lines A,B,C, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 3. 
     FIG. 5 is a circuit diagram depicting an illustrative embodiment of the invention. 
     FIG. 6, comprising lines A through H, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 5. 
     FIGS. 7A, 7B, 7C, 7D, are equivalent circuit diagrams of the switch of FIG. 5 depicting different switched states. 
     FIGS. 8A, 8B, 8C, 8D, are equivalent circuit diagrams of the switch of FIG. 5 having a compensation capacitance added thereto and depicting different switched states. 
     FIG. 9 is a circuit diagram depicting a fixed capacitance correcting circuit capable of correcting non-linearity ranging positively and negatively. 
     FIG. 10 is a circuit diagram depicting a fixed capacitance correcting circuit which corrects non-linearity by use of an analog circuit. 
     FIG. 11 is a circuit diagram depicting a zero correcting circuit for correcting deviation of the zero point resulting from change of temperature or static pressure. 
     FIG. 12, comprising lines A,B, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 11. 
     FIG. 13 is a circuit diagram depicting a zero correcting circuit wherein the relationship of pulse duration is set at T K  &#39;&lt;T 1c . 
     FIG. 14, comprising lines A,B, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 13. 
     FIG. 15 is a circuit diagram depicting a zero correcting circuit wherein the relationship of pulse duration is set at T K  &#34;≈T 1c . 
     FIG. 16, comprising lines A,B, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 15. 
     FIG. 17 is a circuit diagram depicting details of the monostable circuit of FIGS. 11, 13, 15. 
     FIG. 18 is a circuit diagram depicting a monostable circuit used when the amount of correction for zero point is large. 
     FIG. 19 is a circuit diagram depicting a span correcting circuit for correcting deviation of the span resulting from a change of temperature or static pressure. 
     FIG. 20, comprising lines A,B,C,D, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 19. 
     FIG. 21 is a circuit diagram depicting a span correcting circuit when the relationship of pulse duration is set at T K  &#39;&lt;T 1c . 
     FIG. 22, comprising lines A,B,C,D, is a waveform diagram depicting waveforms appearing a different parts of the circuit of FIG. 21. 
     FIG. 23 is a circuit diagram depicting a span correcting circuit when the relationship of upulse duration is set at T K  &#34;≈T 1c . 
     FIG. 24, comprising lines A,B,C, is a waveform diagram depicting waveforms appearing at different parts of the circuit of FIG. 23. 
     FIG. 25 is a circuit diagram depicting a span correcting circuit corresponding to that shown in FIG. 19 without any process section for eliminating constant terms. 
     FIG. 26 is a circuit diagram depicting a span correcting circuit corresponding to that shown in FIG. 21 without any process section for eliminating constant terms. 
     FIG. 27 is a circuit diagram depicting a temperature compensating circuit for compensating for change of zero point and span caused by change of temperature inside the converting section. 
     FIG. 28 is a circuit diagram depicting a modification of the temperature compensating circuit of FIG. 27. 
     FIG. 29 is an overall circuit diagram depicting the invention as applied to a two wire transmission circuit. 
     FIG. 30 is a circuit diagram depicting another illustrative embodiment of a zero point and span (called &#34;zero/span&#34;) circuit. 
     FIG. 31 is a circuit diagram depicting another illustrative zero/span circuit. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     In the drawing similar parts have the same reference numerals and their description is omitted where appropriate for simplicity of description. 
     Turning to FIG. 5, a movable electrode 16 is connected to an input end of an inverter G 5 . The output end of inverter G 5  is connected to an input end of inverter G 6 . Thus, a buffer gate is formed. The output end of inverter G 6  is connected through an inverter G 7  and a resistor R n  to the input end of inverter G 5  in a negative feedback mode. 
     The output end of inverter G 7  is connected to an input end C L  of an n-bit counter CT 1 . The output end Q n  of counter C L  is connected to (1) an input end of AND gate G 8 , (2) an input end of NAND gate G 9 , and (3) to a terminal T o . The other input end of AND gate G 8  and the other input end of NAND gate G 9  are connected to an output end of inverter G 6 . 
     The output end of inverter G 10  is connected to (1) an input end of AND gate G 11 , (2) an input end of NAND gate G 12 , and (3) to a terminal T o  &#39;. The other input end of AND gate G 11  and the other input end of NAND gate G 12  are connected to the output end of inverter G 6 . 
     Output end Q n  of counter CT 1  is also connected to an input end of integrator Q 1 . Integrator Q 1  includes a resistor R 1  connected between the inverting input end (-) of an operational amplifier and output end Q n  of counter CT 1  and a condenser C i  connected between the inverting input end (-) of the operational amplifier and its output end. The non-inverting input end (+) of the operational amplifier is connected to a 1/2 potential point (a midway potential point) having a potential equal to one-half of a source voltage V. 
     Switches SW 1  and SW 2  are connected mutually in series, and their connection point is connected to a fixed electrode 17. The other end of switch SW 1  is connected to the output end of integrator Q 1 . The other end of switch SW 2  is connected to a common potential point COM. These switches SW 1  and SW 2  are controlled, or opened and closed, by means of the outputs of AND gate G 8  and NAND gate G 9 . 
     Switches SW 3  and SW 4  are connected mutually in series, and their connection point is connected to a fixed electrode 18. To the other end of switch SW 3  is applied source voltage V z . The other end of switch SW 4  is connected to the output end of integrator Q 1 . These switches SW 3  and SW 4  are controlled, or opened and closed, by means of the outputs of AND gate G 11  and NAND gate G 12 . 
     A fixed capacitance correcting circuit 20 is provided for correcting fixed capacitances C F  existing across the respective ends of capacitance C 1  and capacitance C 2 . To the inverting input end (-) of an arithmetic unit Q 2  is applied a variable voltage V o  at the output end of integrator Q 1  through a terminal T 1  and a resistor R 2 . A resistor R 3  is connected between the inverting input end (-) and the output end of the arithmetic unit Q 2 . To the non-inverting input end (+) of unit Q 2 , is applied a voltage equal to one-half of the source voltage V z , so that arithmetic unit Q 2  provides at its output end a voltage equal to (V z  -V o ). 
     Switches SW 5 , SW 6  and SW 7  are connected together at their respective one ends, and compensation voltage V c  appearing at these one ends connected together is applied through a terminal T 5  and a compensation capacitance C 3  to movable electrode 16. 
     The other end of switch SW 5  is connected to the output end of arithmetic unit Q 2 . To the other ends of switches SW 6  and SW 7  are applied, respectively, source voltage V z  and variable voltage V o . Switch SW 5  is controlled, or opened and closed, by means of the voltage at the output end of AND gate G 8  applied through a terminal T 4 . Switch SW 6  is controlled, or opened and closed, by means of the voltage at the output end of a NOR gate G 13 . Voltage at the output end of AND gate G 11  is applied through a terminal T 3 , to an input end of NOR gate G 13 . The voltage at the output end of AND gate G 8  is applied through terminal T 4  to the other input end of NOR gate G 13 . Switch SW 7  is controlled, or opened and closed, by means of voltage at the output end of the AND gate G 11  applied through the terminal T 3 . 
     The operation of the circuit shown in FIG. 5 will now be described with reference to FIGS. 6, 7A, 7B, 7C, 7D, 8A, 8B, 8C, 8D, and ignoring the fixed capacitance correcting circuit 20. 
     When the output of counter CT 1  is at a high level H, as indicated at period T 1c  in FIG. 6, line B, and the output of inverter G 6  is at a low level L, the output (see FIG. 6, line A) of AND gate G 8  is in the L state and the circuit connection is in the state shown in FIG. 7A, so that the voltage e i  at the input end of inverter G 5  is in the state indicated by A 1  in FIG. 6, line F. Thus, the capacitances C 1  and C 2  and a distributed capacitance C s  are charged through inverter G 7  and resistor R n , to gradually raise their potentials. When voltage e i  reaches threshold level V TH  of inverter G 7 , the output of inverter G 6  is inverted and the circuit connection becomes that shown in FIG. 7B. Thus, voltage e i  at the input end of inverter G 5  assumes the state shown by A 2  in FIG. 6, line F. 
     Under the foregoing condition, the output of inverter G 10  is in the state shown in FIG. 6, line E, wherein the output of counter CT 1  has been inverted. Thus, both the output (see FIG. 6, line C) of AND gate G 11  and the output (see FIG. 6, line D) of NAND gate G 12  do not change, but, the side of capacitance C 1  only is switches over. 
     If the circuit parameters are set so that the total quantity (see FIG. 7A) of charge of the respective capacitances existing when voltage e i  at the input end of inverter G 5  (being in the state indicated by A 1  in FIG. 6, line F) has reached threshold V TH  is equal to the total quantity (see FIG. 7B) of charge existing immediately after that voltage has shifted to the state A 2 , a voltage V 1 .sup.(+) immediately after inversion is given by the following. ##EQU4## The transient state occurring after switchover from state A 1  to state A 2  results in the circuit connection shown in FIG. 7B. Taking the above V 1 .sup.(+) as the initial value, a discharge time t 1A  during which the voltage e i  goes down to the threshold level V TH , is calculated as follows. ##EQU5## 
     After the discharge time t 1A  has elapsed the output of inverter G 6  is inverted. A voltage V 1 .sup.(-) at the input end of inverter G 5  immediately after the circuit connection has assumed the state shown in FIG. 7A (which corresponds to state A 3  of FIG. 6, line F) is given, similarly to voltage V 1 .sup.(+) by the following. ##EQU6## The transient state occurring after switchover from state A 2  to state A 3  results in the circuit connection shown in FIG. 7A. Taking the above V 1 .sup.(-) as the initial value, a charge time t 1B , when the voltage e i  goes down to the threshold level V TH , is calculated as follows. ##EQU7## 
     Thus, when the output of counter CT 1  is at a low level L as indicated in period T 2c  of FIG. 6, line B, and the output of inverter G 6  is at low level L, the circuit connection is that shown in FIG. 7C, so that voltage e i  at the input end of inverter G 5  is in the state indicated by A 4  in FIG. 6, line F. Thus, the capacitors C 1  and C 2  and distributed capacitance C s  are charged through inverter G 7  and resistor R n  to gradually raise their potentials. When voltage e i  reaches threshold level V TH  of inverter G 7 , the output of inverter G 6  is inverted and the circuit connection assumes the state shown in FIG. 7D. Thus, voltage e i  assumes the state indicated by A 5  in FIG. 6, line F. Discharging continues during discharging time t 2A  of state A 5 . When threshold level V TH  is attached, the output of inverter G 6  is inverted and the respective capacitances are charged during a charge time t 2B  of state A 6  shown in FIG. 6, line F. 
     During period T 1c  the potential of fixed electrode 18 of capacitance C s  goes down to variable voltage V o . On the other hand, during period T 2c , the potential of fixed electrode 17 of capacitance C 1  goes down to that of common potential point COM. 
     A voltage V 2 .sup.(+) immediately after reversal from state A 4  to state A 5  is given, similarly to the case of the period T 1c , by the following. ##EQU8## The discharge time t 2A  in state A 5  is calculated by the use of the foregoing initial value, similarly to the case of equation (6), as follows. ##EQU9## 
     A voltage V 2 .sup.(-) immediately after reversal from state A 5  to state A 6  is given, similarly to the case of period T 1c , by the following. ##EQU10## Discharge time t 2B  in state A 6  is calculated by the use of the initial value, similarly to the case of equation (7), as follows. ##EQU11## 
     Here, the integrator Q 1  regulates the variable voltage V o  so that the output (see FIG. 6, line B) of counters CT 1  becomes identical between period T 1c  and period T 2c . This satisfies the following equilibrium condition. 
     
         t.sub.1A +t.sub.1B =t.sub.2A +t.sub.2B                     (10) 
    
     The potential V o  is obtained by substituting equation (6) through (9) for equation (10) as follows. ##EQU12## If C o  is taken as the capacitance when a differential pressure ΔP is zero and k is a constant, the capacitance C 1  and C 2  are represented by the following. ##EQU13## 
     By substituting these equations (12) and (13) for equation (11), the following is obtained. ##EQU14## That is, variable voltage V o  is proportional to differential pressure ΔP. 
     Equation (14) does not include distributed capacitance C s  which is eliminated during calculation of equation (10). Thus, no influence due to distributed capacitance C s  appears in the results. 
     The operation of the circuit in case the fixed capacitance correcting circuit 20 (see FIG. 5) is effectively included will now be described. Practically, the fixed capacitances C F , which are non-responsive to differential pressure ΔP, are formed across capacitances C 1  and C 2 . Capacitances C H  and C L  corresponding to cpacitances C 1  and C 2 , which must be considered if fixed capacitances C F  are taken into account, are given as follows. ##EQU15## 
     The fixed capacitances C F  increase their ratio of capacitance to the other capacitances when the sensor section is miniaturized and correspondingly, possibility of occurrence of non-linearity also inreases. Thus, the fixed capacitance correcting circuit 20 is used to eliminate fixed capacitances C F . 
     When the output of counter CT 1  is at H level, as indicated by period T 1c  in FIG. 6, line B, the output of AND gate G 11  is at L level, as shown in FIG. 6, line C, not depending upon the output level of inverter G 6 . Thus, switch SW 7  is kept open. In this state, when the output of inverter G 6  is L, switches SW 1  and SW 5  are OFF, and switches SW 2  and SW 6  are ON. The circuit connection in this condition is as shwon in FIG. 8A. Then, when the output of inverter G 6  becomes H, switches SW 1  and SW 5  turn ON and switches SW 2  and SW 6  are turned OFF. The circuit connection in this condition is as shown in FIG. 8B. The state of compensation voltage V c , under the above condition, is as shown in FIG. 6, line H. 
     When the output of counter CT 1  is at the L level, as indicated by period T 2c  in FIG. 6, line B, the output of AND gate G 8  is at the L level, as shown in FIG. 6, line A, not depending upon the output level of inverter G 6 . Thus, switch SW 5  is kept open. In this case, switches SW 6  and SW 7  operate in mutually opposite phases. In this condition, when the output of inverter G 6  is L, switches SW 3  and SW 7  are turned OFF, and switches SW 4  and SW 6  are turned ON. The circuit connection in this case is shown in FIG. 8C. Then, when the output of inverter G 6  becomes H, switches SW 3  and SW 7  are turned ON and switches SW 4  and SW 6  are turned OFF. The circuit connection in this case is shown in FIG. 8A. The state of compensation voltage V c , under the above condition, is shown in FIG. 6, line H. 
     From comparison of the circuit connection shown in FIGS. 7A-7D and 8A-8D, it is clear that both circuit configurations become completely identical mutually if C 1  and C 2  of FIGS. 7A-7D are read substitutively as C L  and C H , respectively, and if compensation capacity C 3  is ignored. That is, the circuits shown in FIGS. 8A-8D are identical in configuration to those of FIGS. 7A-7D with compensation capacitor C 3  added thereto. Accordingly, the calculation procedure used with respect to FIGS. 7A-7D is substantially applicable to FIGS. 8A-8D, as follows. 
     The charge and discharge times, t 1A  &#39;, t 1B  &#39;, t 2A  &#39;, and t 2B  &#39; when fixed capacity correcting circuit 20 is included, corresponding to the discharge time t 1A , charge time t 1B , discharge time t 2A , a and charge time t 2B , respectively, when fixed capacitance correcting circuit 20 is not added, are given as follows. ##EQU16## 
     In the equilibrium state, the following holds. 
     
         t.sub.1A &#39;+t.sub.1B &#39;=t.sub.2A &#39;+t.sub.2B &#39;                (21) 
    
     Thus, by substituting equations (17) through (20) for equation (21) the following is obtained. ##EQU17## 
     By substituting equations (15) and (16) for equation (22), the following is obtained. ##EQU18## By setting C F  =C 3 , the following is obtained. ##EQU19## That is, there is obtained a linearly variable output proportional to differential pressure ΔP, not influenced by either distributed capacitance C s  or fixed capacitances C F . Although there exist stray capacitances C s1  and C s2  between the output ends of inverters G 6  and G 7  and the input end of inverter G 5 , these stray capacitances appear in a common mode between C H  side and the C 1  side. Thus, they are eliminated in the equilibrium state. 
     As will be apparent from consideration of equation (24) which is obtained from equation (23), the output exhibits a non-linear change with respect to differential pressure ΔP if fixed capacitances C F  are not eliminated completely. Further, it is sometimes desired to correct non-linearity ranging positively and negatively by additionally taking into account non-linearity caused by a spring system of the sensor system, and the like. 
     FIG. 9 depicts an illustrative fixed capacity correcting circuit which is capable of additionally correcting non-linearity which may range positive and negative. Fixed capacity correcting circuit 21 is a modification of fixed capacity correcting circuit 20 (of FIG. 5) to which switches SW 8 , SW 9  and SW 10  and a variable resistor VR 1 , are added. One end of switch SW 8  is connected through variable resistor VR 1  to one end of each of switches SW 5 , SW 6 , and SW 7  and directly to one end of each of switches SW 9  and SW 10 , as depicted. To the other end of switch SW 8  is applied variable voltage V o . To the other end of switch SW 9  is applied common potential point COM. To the other end of switch SW 10  is applied output voltage (V z  -V o ) of arithmetic unit Q 2 . Switches SW 8  and SW 5  are switched concurrently, similarly to switches SW 9  and SW 6  and to switches SW 10  and SW 7 . 
     Thus, to variable resistor VR 1  are applied coutput voltage (V z  -V o ) of unit Q 2  and variable voltage V o  (which is opposite in phase to V z  -V o ) by means of switches SW 5  and SW 8 . Accordingly, a desired variable voltage, ranging between the foregoing two voltages, is applied via an intermediate point of resistor VR 1  to compensation capacitor C 3 . Alternatively, by means of switches SW 6  and SW 9 , a desired fixed voltage, ranging between voltage V z  and the potential of common potential point COM, is applied via the intermediate point of resistor VR 1  to compensation capacitance C 3 . Further, alternatively, by means of switches SW 7  and SW 10  a variable voltage ranging between variable voltage V o  and output voltage (V z  -V o ) of unit Q 2  is applied via the intermediate point of resistor VR 1  to capacitance C 3 . Thus, in each case, a desired variable of fixed voltage is applied via the intermediate point of resistor VR 1  to capacitor C 3 . By the foregoing configuration, the magnitude of compensation voltage V c  is adjusted to perform compensation of non-linearity. 
     FIG. 10 depicts another illustrative circuit for compensating for non-linearity using an analog circuit, wherein a variable resistor VR 2  is connected between terminal T 1  and the output end of arithmetic unit Q 2 . The intermediate point of resistor VR 2  is connected through terminal T 5  and a compensation resistor R c , to movable electrode 16. A desired variable voltage ranging between variable voltage V o  and output voltage (V z  -V o ) of arithmetic unit Q 2  is obtained at the intermediate point of variable resistor VR 2 , by which the overall non-linearity is corrected or compensated. 
     FIG. 11 depicts an illustrative zero point correcting circuit 22 for correcting deviations of the zero point of the sensor section resulting from changes of temperature or static pressure. In this connection, let A H  be the effective area of diaphragm 11 on the high pressure side and A L  be the effective area of diaphragm 12 on the low pressure side, as shown in FIG. 1. If the transducer is configured so as to provide the relationship A H  &gt;A L , for example, volume v of the sealing liquid increases in response to temperature change ΔT and rod 19 is moved to the left. On the other hand, the volume v of the sealing liquid decreases due to static pressure change ΔP s  and rod 19 is moved to the right. As a result, the zero point fluctuates or deviates. In case A H  &lt;A L , the foregoing relationships are reversed. That is, it is known that the direction of occurrence of zero point fluctuation caused by the difference of effective areas becomes opposite between a temperature rise and a static pressure rise. This zero point fluctuation is produced as a result of change of internal pressure caused by a change of volume or a change of density of the sealing liquid. 
     In connection with the relationships between the rate of volume change of the sealing liquid due to temperature change and static pressure change, and the rate of change of permittivity ε of the sealing liquid due to temperature change and static pressure change, the following relationships were found. ##EQU20## 
     The foregoing relationships show that the rate of change of permittivity ε of the sealing liquid due to changes of ambient temperature and static pressure is substantially identical to the rate of volume change of the sealing liquid due to the changes of ambient temperature and static pressure. Also from equations (25) and (26) it can be seen that volume change ΔV resulting from change of temperature or static pressure can be detected by detecting the rate of change Δε of permittivity ε. Since a zero point fluctuation occurs when there appears a difference of effective area caused by volume change of the sealing liquid, it is possible to compensate for fluctuation of the zero point on the basis of a detection signal generated by detecting change of Δε of permittivity ε. 
     The procedure for deriving a signal relating to permittivity ε from the illustrative circuit of FIG. 5 will now be described. 
     From equations (6) through (9) is derived period T 1c  with setting V TH  =V z  /2. The following equation is obtained by letting T 1c  =t 1A  =t 1B . ##EQU21## By omitting the terms of second degree and higher, it becomes as follows. ##EQU22## By letting T 2C  =t 2A  +t 2B , similarly, the following is obtained. ##EQU23## Since the circuit shown in FIG. 5 becomes balanced when T 1C  =T 2C  as described above, the following is obtained from equations (27) and (28). ##EQU24## 
     By substituting this equation for equation (27) , the followins obtained. ##EQU25## By letting C v  be a capacitance under vacuum when the differential pressure ΔP is zero, the relation C o  =εC v  is obtained. By substituting this for equations (12) and (13) and the results thereof for equation (29), the following is obtained. ##EQU26## 
     By letting A be a proportional constant, the following is obtained. 
     
         T.sub.1C =Aε                                       (30) 
    
     Accordingly, the pulse duration of output signal V Q  of counter CT 1  is proportional to permittivity ε, which is obtained at terminal T o . 
     In FIG. 11, a monostable circuit Q 3  produces a pulse signal P 1  having a predetermined pulse duration T K  in response to output signal V Q  applied to terminal T o . A resistor R M  and a capacitance C M  are set so that pulse duration T K  becomes larger than pulse duration T 1C  of the output signal V Q  (i.e. T K  &gt;T 1C ) By opening and closing a switch SW 11 , by means of pulse signal P 1 , a voltage V.sub.ε proportional to permittivity ε of the filled sealing liquid is obtained at the output end of a filter made of a resistor R 4  and a capacitor C 4  inserted between the output end of switch SW 11  and the non-inverting input end (+) of amplifier Q 4 . 
     Taking into consideration output signal V Q  and pulse signal P 1  shown in FIG. 12, lines A,B, voltage V.sub.ε  obtained at the non-inverting input end (+) of amplifier Q 4  has a form obtained by dividing output signal V Q  by pulse signal P 1 . Thus, by using equation (30), voltage V.sub.ε becomes as follows. ##EQU27## 
     Accordingly, there is obtained at the non-inverting end (+) of amplifier Q 4  voltage V.sub.ε relating to zero point fluctuation of the sensor section, caused by changes of temperature and static pressure, which can be used as a compensation signal for compensating the zero point. A zero point adjusting circuit for correcting the zero point comprises an amplifier Q 5 , a resistor R 5  connected between the input end and the output end of amplifier Q 5 , a variable resistor VR 3  connected between the output end of amplifier Q 4  and the output end of amplifier Q 5 , a resistor R 6  interposed between the inverting input end (-) of amplifier Q 5 , and a variable resistor VR 4  having one end thereof receive voltage V z  and a variable terminal connected to the non-inverting input end (+) of amplifier Q 5 . By adjusting variable resistor VR 4  there is obtained at output terminal T 6  of the zero adjusting circuit, a fixed voltage for correcting the zero point to which voltage V.sub.ε is added. The voltage obtained at terminal T 6  is added to variable voltage V o , so that the resultant voltage serves as the compensation voltage for the zero point. 
     Although in FIG. 11, terminal T o  is connected to the output end of counter CT 1  (of FIG. 5) to obtain output voltage V Q , the invention is not limited thereto and can use any part of the circuit which generates an identical signal. For example, that signal may be obtained from the output end of inverter G 10  of FIG. 5. 
     FIG. 13 depicts another illustrative zero point correcting circuit 23 wherein the relationship of pulse duration is set at T K  &#39;&lt;T 1C . The FIG. 13 circuit differs from the FIG. 11 circuit in that switch SW 11  is controlled by means of output signal V Q  of counter CT 1 , and the output end of the monostable circuit Q 3  is connected to the input end of switch SW 11  so that a pulse signal P 2  is applied thereto. 
     FIG. 14, lines A and B show waveforms of output signal V Q  and pulse signal P 2  at different parts of the FIG. 13 circuit. Since switch SW 11  is opened and closed by means of output signal V Q , calculation of T K  &#39; and T 1C  is inverse to the case of FIG. 11. Thus, voltage Vε&#39; becomes as follows. ##EQU28## 
     In case the extent of change of permittivity ε is small, 1/ε also varies linearly with change of static pressure and temperature. Thus, the inverse permittivity signal can be used as a compensation signal. 
     FIG. 15 depicts another illustrative zero point correcting circuit 24 wherein the relationship of pulse duration is set at T K  &#34;≈T 1C . The FIG. 15 circuit differs from the FIGS. 11 and 13 circuits in that the switch SW 11  is omitted. The relation T K  &#34;≈T 1C  is realized by suitably selecting the values of resistor R M  and capacitance C M  of monstable circuit Q 3 , and a pulse signal P 3  is applied to resistor R 4  and capacitance C 4  to obtain a voltage V.sub.ε &#34; at the non-inverting input end (+) of amplifier Q 4 . FIG. 16, lines A and B show waveforms of output signal V Q  and pulse signal P 3  at different parts of the circuit of FIG. 15. As is apparent from this waveform diagram, voltage V.sub.ε &#34; is give as follows. ##EQU29## 
     Thus, voltage V.sub.ε &#34; is obtained which relates to a zero point fluctuation of the sensor section caused by changes of temperature and pressure, and can be used as a compensation signal for compensating the zero point. 
     FIG. 17 depicts details of monostable circuit Q 3  of FIGS. 11, 13, 15, and comprises a D-type flip-flop Q 6 , a n-bit counter CT 2 , and an oscillator OSC having an oscillation period which can be adjusted by resistor R M  and capacitor C M . Due to the leading edge of output signal V Q  applied to terminal T o , the voltage at the output end Q of flip-flop Q 6  rises up to voltage V z  applied to data input D. At the same time, an inverted output Q falls and is applied to terminal R of counter CT 2 , and counter CT 2  starts to count a frequency applied from oscillator OSC to its input end C up to a certain count. After completion of counting, the potential of output end Q n  of counter CT 2  is lowered to reset, via terminal R, the flip-flop Q 6 . As a result, the potential of output end Q of flip-flop Q 6  is lowered to thereby generate a pulse of a certain duration T K . Since the oscillation frequency varies as capacitor C M  and/or resistor R M  is changed, it is possible to change the pulse duration. 
     FIG. 18 depicts another illustrative monostable circuit Q 7  used when the amount of correction of the zero point is large. The voltage V.sub.ε for correction of the static pressure zero involves no particular problem with respect to non-linearity when the amount of correction is small. However, voltage V.sub.ε exhibits some non-linearity with respect to differential pressure ΔP when the amount of correction becomes large. In such a case, monostable circuit Q 7  shown in FIG. 18 is used. This circuit differs from the FIG. 17 circuit in that a resistor R 7  is inserted between the output end of oscillator OSC and resistor R M , and one end of a resistor R 8  is connected to the connection point between resistors R M  and R 7  with the other end receiving variable voltage V o , for example from circuit 5. 
     A current supplied from variable voltage V o  through resistor R 8 , is caused to flow and to be added to a current flowing through resistor R M  nornally at fixed level so that pulse duration T K  is made variable depending upon variable voltage V o  to thereby correct errors of non-linearity. 
     FIG. 19 depicts an illustrative span correcting circuit 25 for correcting deviation of the span of the sensor section caused by changes of temperature and static pressure. Switches SW 12  and SW 13  are connected mutually in series and variable voltage V o  is applied to the common point thereof. The connection point between switches SW 12  and SW 13  is connected to one end of a switch SW 14 . A filter made up of a resistor R 9  and a capacitor C 5  is inserted between the other end of switch SW 14  and the non-inverting input end (+) of an amplifier Q 8 . A resistor R 10  is connected between the output end and the inverting input end (-) of amplifier Q 8 . A resistor R 11  is connected between the inverting input end (-) of amplifier Q 8  and the output end of amplifier Q 4 . To the non-inverting end (+) of amplifier Q 9  is applied a voltage generated by dividing voltage V z  means of a variable resistor VR 5 . A resistor R 12  is connected between the inverting input end (-) and the output end of amplifier Q 9 . The output end of amplifier Q 8  is connected through a resistor R 13  to inverting input end (-) of the amplifier Q 9  and also through a variable resistor VR 6  to the output end of amplifier Q 9 . A terminal T 7  is taken out from the intermediate point of variable resistor VR 6 . On the other hand, the input end of switch SW 11  is connected to terminal T o , to which output signal V Q  is applied. 
     Switches SW 14  and SW 11  are controlled by means of monostable circuit Q 3 . Pulse signal P 1  is set by resistor R M  and capacitor C M  of monostable circuit Q 3  so that pulse duration T K  is wider than pulse duration T 1C  of output signal V Q  (T 1C  &lt;&lt;T K ). Switch SW 11  is controlled by means of output signal V Q , whereas switch SW 13  is controlled by means of a signal generated by inverting the output signal V Q  and applied to a terminal T o  &#39;. 
     Operation of the above circuit will now be described with reference to FIG. 20, comprising lines A, B, C, D. By controlling switch SW 12 , by means of output signal V Q  (see FIG. 20, line A) and switch SW 13  by means of the inverted signal V Q  (see FIG. 20, line C) which is generated by inverting output signal V Q , there is obtained a pulse signal P 4  (See FIG. 20, line D) at the connection point between the switches SW 13 , SW 13  whose peak value is V o  and whose pulse duration is proportional to the permittivity ε of the sealing liquid of the sensor section. By controlling further by means of the pulse signal P 1  (see FIG. 20, line B) which is the output of monostable circuit Q 3  there is obtained at the non-inverting input end (+) of amplifier Q 8  a voltage V s ε relating to the differential pressure ΔP and the permittivity ε, which is shown as follows. ##EQU30## By using equations (30) and (24), the following is obtained. ##EQU31## On the other hand, voltage V.sub.ε at the non-inverting input end (+) of amplifier Q 4  is given by equation (31). 
     Then, by processing voltages V s ε and V.sub.ε in accordance with the following equation in amplifier Q 8 , a voltage V os  proportional to permittivity ε and differential pressure ΔP is obtained at the output end of amplifier Q 8 , as follows. ##EQU32## 
     Variable resistor VR 3  is for applying the correction signal of the zero point, which signal is used for correction of span error by means of variable resistor VR 6 . 
     FIG. 21 depicts another illustrative span correcting circuit 26 wherein the relationship of pulse duration is set at T K  &#39;&lt;T 1C . The FIG. 21 circuit differs from the FIG. 19 circuit in that switches SW 11  and SW 14  are controlled by means of output signal V Q  of counter CT 1  (of FIG. 5) and switches SW 12  and SW 13  are controlled by means of pulse signal P 2  of monostable circuit Q 3  and its inverted pulse signal P 2 . 
     FIG. 22, comprising lines A, B, C, D, shows waveforms at different parts of the FIG. 21 circuit. Since switches SW 11  and SW 14  are opened and closed by means of output signal V Q , calculation of T K  &#39; and T 1C  is inverse to the case of FIG. 21, so that a voltage V s ε &#39; generated by smoothing a pulse signal P 5  at the connection between switches SW 12  and SW 13  becomes as follows. ##EQU33## By using equations (30) and (24), the following is obtained. ##EQU34## 
     On the other hand, since voltage V.sub.ε &#39; at the non-inverting input end (+) of amplifier Q 4  is given by equation (32), by using it and performing the following calculations by the use of amplifier Q 8 , there is obtained at the output end of samplifier Q 8  a voltage V os  &#39; relating to permittivity ε and differential pressure ΔP, as follows. ##EQU35## 
     In case the extent of change of permittivity ε is small, 1/ε also relates to the temperature and static pressure and changes linearly. Thus, the inverse permittivity signal is usable as the compensation signal for compensating the span. 
     FIG. 23 depicts another illustrative span correcting circuit 27 wherein the relationship of pulse duration is set at T K  &#34;≈T 1C . The circuit of FIG. 23 differs from that of FIG. 21 in that switches SW 14  and SW 11  are omitted. Specifically, the relation T K  &#34;≈T 1C  is realized by suitably selecting the values of resistor R M  and capacitor C M  of monostable circuit Q 3 . Pulse signal P 3  is used to control variable voltage V o . The resultant pulse signal P 6  is applied to resistor R 9  and capacitor C 5 , to obtain a V s ε &#34; at the non-inverting input end (+) of amplifier Q 8 . FIG. 24, lines A, B, and C show waveforms at different parts of FIG. 23. As is apparent from the waveform diagram, voltage V s ε &#34; is given as follows. ##EQU36## By using equations (30) and (24), the following is obtained. ##EQU37## 
     On the other hand, since voltage V.sub.ε &#34; at the non-inverting input end (+) of amplifier Q 4  is given by equation (33), by using it and performing the following calculations in amplifier Q 8 , there is obtained at the output end of amplifier Q 8  a voltage V os  &#34; relating to permittivity ε and differential pressure ΔP as follows. ##EQU38## 
     Although the results above are identical to that of equation (39), switches SW 11  and SW 14 , are advantageously, removed. 
     FIGS. 25 and 26 correspond to FIGS. 19 and 21, respectively, and show span correcting circuits 28,29, respectively, from which are omitted means for performing calculation of eliminating constant terms, indicated in the equations (35) and (38). That is, the FIG. 25 circuit and the FIG. 26 circuit differ from the FIGS. 19 and 21 circuits in that the order end of switch SW 13  and one end of the variable resistor VR 5  are connected to the midway potential point, whose potential is one-half of the source voltage V z , and to the other end of variable resistor VR 5  is applied variable voltage V o . For reference, if the circuit is modified so as to use the pulse signal P 3  shown in FIG. 23, switch SW 14  can be omitted from the circuit of FIG. 26. 
     FIG. 27 depicts an illustrative temperature compensation circuit for compensating for changes of zero point and span (referred to herein as zero/span) caused by changes in temperature inside the converting section, wherein temperature compensation circuit 30, which generates a temperature compensation signal comprises a temperature sensing element T H  which may be formed by a diode, thermistor, resistor of large temperature coefficient, etc, and is disposed inside the converting section. A source voltage V z  is applied across the series circuit comprising the sensing element T H , resistor R 14 , variable resistor VR 7 , and resistor R 15 . 
     An amplifier Q 10  forms a voltage follower whose non-inverting input end (+) receives the voltage at the intermediate point of variable resistor VR 7  and whose output end is connected to variable resistors VR 8 , and VR 9  and resistor R 15 . The non-inverting input end (+) of amplifier Q 11  is connected to a midway potential point, and its inverting input end (-) is connected through a resistor R 15  to the output end of amplifier Q 10  and further through a resistor R 16  to the output end of amplifier Q 11 , so that a voltage which is the inverse of the voltage at the output end of amplifier Q 10  is obtained at the output end of amplifier Q 11 . Variable resistors VR 8  and VR 9  are connected between the output end of amplifier Q 10  and Q 11 , and a temperature zero point signal V Tz  and a temperature span signal V Ts  are obtained at the intermediate points of the variable resistors VR 8  and VR 9 , respectively. The circuit parameters are set so that the voltage can assume zero at the center of each of variable resistors VR 8  and VR 9  and is adjustable positively and negatively. Temperature zero point signal V Tz  is added so as to be included in variable voltage V o , and the temperature span signal V Ts  is added so as to correct the source voltage V z . Thus, these signals correct zero point and the span, respectively. 
     FIG. 28 depicts an illustrative temperature compensation circuit 31 which is designed so that at the time temperature span signal V Ts , of temperature compensating circuit 30 of FIG. 27, is applied so as to correct the source voltage V z , that span signal V Ts  is applied in a low impedance mode. The non-inverting input end (+) of amplifier Q 12  is connected to a midway potential point. The inverting input end (-) of amplifier Q 12  is connected through a resistor R 17  to the common potential point COM and further through a resistor R 18  to an output end of amplifier Q 12 . The temperature span signal V Ts  is applied through a resistor R 19  to the inverting input end (-) of the amplifier Q 12  so that an impedance converted temperature span signal V Ts  is obtained at its output end. 
     FIG. 29 depicts an overal circuit diagram of the illustrative capacitive displacement transducer as appplied to a two wire transmission system, wherein a power source E b  is connected through a load L to transmission lines l 1  and l 2  of the two wire system. Across terminals T 8  and T 9  on the other end of transmission lines l 1  and l 2  are connected in series, a diode D 1 , Zener diode D 2 , and a feedback resistor R f . Between the cathode of diode D 1  and the common potential point COM are connected in series a constant current circuit CC and a Zener diode D 2 , so that source voltage V z  of the circuit is created across the Zener diode D 2 . This source voltage V z  is applied to a filter made up of a resistor R 20  and a capacitor C 6  , thereby becoming a source voltage V zc . 
     The output signal V Q  of the counter CT 1  is applied through resistor R 1  to the inverting input end (-) of integrator Q 1 . On the other hand, the non-inverting input end (+) of integrator Q 1  is connected to the midway potential point. The midway potential point is realized on the output end of amplifier Q 13  forming a voltage follower which handles a voltage generated by dividing source voltage V z  by use of resistors R 21  and R 22 . 
     The voltage smoothed by the integrator Q 1  `is applied to the base of a transistor Q 14  for controlling the current of the transmission lines l 1  and l 2  of the two wire system. The collector of the transistor Q 14  is connected to the connection point between diode D 1  and the constant current circuit CC, with its emitter connected through a diode D 3  and a resistor R 23  for temperature compensation of transistor Q 14  to the common potential point COM. 
     A feedback voltage V f  generated on the feedback resistor R f  by a load current I L  flowing through load L is applied to a zero/span circuit 32 for adjusting the overall zero/span of the transducer. 
     A voltage generated, by dividing the voltage sum of the feedback voltage V f  and the source voltage V z , by means of resistors, R 24  and R 25 , is applied to the non-inverting input end (+) of an amplifier Q 15  forming a voltage follower. The voltage at the output end of the amplifier Q 15  is applied to the input end of an inverting amplifier Q 16 . The overall span of the transducer is adjusted by means of a variable resistor VR 10  connected between the input end and output end of the inverting amplifier Q 16 . 
     On the other hand, the voltage at the intermediate point of variable resistor VR 11  connected between source voltage V zc  and common potential point COM which is a divided part of the source voltage V zc , is applied through a voltage follower Q 17  to an inverting amplifier Q 18 . The variable resistor VR 11  for zero point adjustment is used to adjust the zero point of the entire circuit, and the inverting amplifier Q 18  is used to correct reversely fluctuations of source voltage V zc  caused by temperature span signal V Ts  of the temperature compensating circuit 30, so as to prevent double compensation which would otherwise take place in conjunction with temperature zero point signal V Tz . 
     The outputs of inverting amplifiers Q 16  and Q 18  are applied through respective resistors R 26  and R 27  to an amplifier Q 19  and added together thereby, and fed back to the sensor section as variable voltage V o . 
     The temperature span signal V Ts  of circuit 30 is applied through resistor R 19  and added as a span compensation voltage to source voltage V zs , and the temperature zero point signal V Tz  is added through a resistor R 28  to amplifier Q 19  to achieve zero point compensation. 
     The zero point correcting circuit 22 for correcting deviation of the zero point resulting from changes of ambient temperature and/or static pressure receives output signal V Q  of counter CT 1  through terminal T o  and supplies the same addingly to amplifier Q 19  through terminal T 6  and resistor R 29 . 
     Between terminals T 8  and T 9  is connected the series circuit comprising capacitors C 7  and C 8  having their connection point at ground. By this configuration, higher harmonic noises entrapped in transmission lines l 1  and l 2  are removed. 
     If it is necessary to correct deviations of the span resulting from changes of ambient temperature and/or static pressure, this is achieved by connecting the output terminal T 7  of the span correcting circuit 25-29 (see FIGS. 19, 21, 23, 25, 26) through a resistor R 32  to the input end of amplifier Q 19 . 
     According to the foregoing circuit, the output signal V Q  of counter CT 1  is applied to the input end of the integrator Q 1  and by the voltage at the output end of integrator Q 1 , is controlled with the current flowing through transistor Q 14 , so that load current I L  is regulated. Feedback voltage V f  generated on the feedback resistor R f  by load current I L  is applied to and is regulated by the zero/span circuit 32, thereby becoming load current I L  of the span corresponding to a differential pressure (ΔP) span, and fed back from amplifier Q 19  to the sensor section as variable voltage V o . By this feedback, the circuit is controlled and balanced so that the voltage at the inverting input end (-) of integrator Q 1  becomes identical to that of midway potential point (i.e. V z  /2), irrespective of which side is switched and selected by counter CT 1  between the sides of capacitors C H  and C L . In the equilibrium state the load current I L  corresponds to the differential pressure ΔP. 
     Zero point fluctuation caused by a temperature change inside the transducer is compensated by regulating temperature zero point signal V Tz  detected by the temperature sensing element T H  by means of the variable resistor VR 8 . Span fluctuation caused by such temperature change is compensated by regulating the temperature span signal V Ts  by means of the variable resistor VR 9 . 
     A deviation of the zero point resulting from changes of temperature or static pressure on the sensor section is compensated through adjustment of the variable resistor VR 3 . 
     The adjustment procedure of static pressure zero point and temperature zero point and span for the circuit of FIG. 29 will now be described. In the first step, variable resistor VR 7  is adjusted so as to cause temperature signal V T  obtained at the output end of amplifier Q 10  of temperature compensating circuit 30 to become 0 volts at the reference temperature, e.g. room temperature. 
     In the second step, variable resistor VR 11  is adjusted while giving differential pressure ΔP, under the condition that the static pressure P s  is zero at the reference temperature so as to cause the load current I L  to become 0%; and then the variable resistor VR 10  is adjusted to cause the load current I L  to become 100%. 
     In the third step, variable resistor VR 3  is adjusted while applying a static pressure P s  to the diaphragm under the condition that differential pressure ΔP at the reference temperature is 0% to cause load current I L  to become 0%, whereby the zero point of the sensor is compensated. 
     In the final, and fourth step, variable resistor VR 8  is adjusted while giving a high temperature change or low temperature change and applying differential pressure ΔP to the diaphragm under the condition that static pressure P s  is zero so as to cause load current I L  to become 0%, and further variable resistor VR 9  is adjusted so as to cause load current I L  to become 100%. 
     This adjustment procedure is sufficient when done once. Thus, it is possible to realize within a short adjustment time, a displacement transducer of superior precision which is not unduly influenced by changes of static pressure and ambient temperature. 
     FIG. 30 depicts another illustrative zero/span circuit 33, which differs from the zero/span circuit 32 of FIG. 29, in that from the connection point between resistors R 24  and R 25 , its voltage is derived by means of a voltage follower Q 20 , and the span is adjusted by means of voltage follower Q 20  and the midway potential point. The voltage at the intermediate point of variable resistor VR 12  is applied to the non-inverting input end (+) of amplifier Q 21  and provided through amplifier Q 21  as variable voltage V o . In this case, a magnification degree smaller than one cannot be obtained, which is different from the case of the zero/span circuit 32 of FIG. 29. 
     FIG. 31 depicts still another illustrative zero/span circuit 34, which differs from he zero/span circuit 32 of FIG. 29 and is used when V zc  /2 is selected by means of amplifier Q 13  as the potential of the midway potential point and V zc  as the source voltage of counter CT 1 . Thus, in contrast to zero/span circuits 32 and 33, in this circuit 34, a voltage generated by dividing the source voltage V z  by means of resistors R 30  and R 31 , is applied through a voltage follower Q 22  to one end of variable resistor VR 12  for span adjustment. 
     As described above, the discharging circuit is constructed without using a complex constant value current limiting circuit such as used in the prior art, thereby eliminating adverse effects of fixed capacitances and distributed capacitances. Also, in the invention, it is possible to compensate for deviation of the zero point and/or span resulting from fluctuation of ambient temperature and/or static pressure, by using information contained in the differential pressure signal, thereby producing a capacitive displacement transducer of superior precision. 
     The foregoing description is illustrative of the principles of the invention. Numerous modifications and extensions thereof would be apparent to the worker skilled in the art. All such modifications and extensions are to be considered to be within the spirit and scope of the invention.