Abstract:
Some advanced integrated circuits are fabricated as silicon-on-insulator structures, which facilitate faster operating speeds, closer component spacing, lower power consumption, and so forth. Unfortunately, current bonded-wafer techniques for making such structures are costly because they waste silicon. Accordingly, one embodiment of the invention provides a smart-bond technique that allows repeated use of a silicon wafer to produce hundreds and potentially thousands of silicon-on-insulator structures, not just one or two as do conventional methods. More precisely, the smart bond technique entails bonding selected first and second regions of a silicon substrate to an insulative substrate and then separating the two substrates to leave silicon protrusions or islands on the insulative substrate. The technique is also suitable to forming three-dimensional integrated circuits, that is, circuits having two or more circuit layers.

Description:
This application is a Divisional of U.S. Ser. No. 09/128,851, filed on Aug. 4, 1998, now U.S. Pat. No. 6,093,623. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention concerns fabrication methods and structures for integrated circuits, particularly methods for making silicon-on-insulator structures. 
     Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, typically a round slice of silicon called a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer processor or memory. 
     The evolution of integrated circuits has been driven by three principal objectives: reducing size, lowering power consumption, and increasing operating speed. Silicon-on-insulator (SOI) technology - - - an emerging technology which entails building silicon devices, such as transistors, on an insulative substrate rather than on a silicon substrate as done typically - - - dramatically advances all three objectives. First, silicon-on-insulator technology provides superior electrical isolation between adjacent components, which, in turn, allows closer component spacing and integrated-circuit size reductions. Second, silicon-on-insulator technology reduces integrated-circuit capacitance, the primary obstacle to faster operating speeds. And third, it enables use of lower operating voltages, which significantly reduces power consumption. 
     Unfortunately, conventional methods for implementing silicon-on-insulator technology waste costly silicon, and therefore have been commercially viable in only a few high-priced applications. For instance, one conventional method forms an insulative layer on the top surface of a silicon wafer and bonds the entire surface of another silicon wafer onto the insulative layer, essentially sandwiching the insulative layer between the two silicon wafers. This method then wastefully grinds down one of the silicon wafers to a thin silicon layer, yielding one silicon-on-insulator structure at the cost of two silicon wafers. 
     A similar method, dubbed “smart cut” by its proponents, is a bit more cost effective. The smart-cut method sandwiches an insulative layer between two silicon wafers, but rather than grinding down one of the wafers, it in effect slices off a thick portion of one wafer, leaving a thin slice of silicon covering the entire insulative layer and saving the thick portion for use in another silicon-insulator-silicon sandwich. Thus, the smart-cut method is emerging as a substitute to the bond-and-grind method. 
     However, the smart-cut method suffers from at least three shortcomings. First, slicing the silicon wafer entails implanting hydrogen ions into the silicon, some of which remain in the bonded silicon after the slicing procedure, and introduce defects into transistors later formed in the silicon. Second, the smart-cut method indiscriminantly bonds a continuous silicon layer to the entire insulative surface, not only to regions where transistors are desired but also to regions where they aren&#39;t. The continuity of the silicon layer forces it to buckle and crack during subsequent processing because the insulation and silicon expand and contract at very different rates in response to temperature changes. Third, the continuity also allows silicon between and around intended transistors to form unintended, or parasitic, devices, for example parasitic diodes and transistors, which compromise isolation, performance, and reliability of the intended transistors. 
     Accordingly, there is a need for more effective methods of making silicon-on-insulator structures. 
     SUMMARY OF THE INVENTION 
     To address these and other needs, the inventor devised a smart-bond technique that allows repeated use of a silicon or more generally a semiconductive wafer to produce hundreds, potentially thousands, of semiconductor-on-insulator structures. Moreover, the smart-bond technique intelligently applies semiconductive material only where semiconductor devices are desired, not only saving semiconductive material, but precluding formation of parasitic devices which would otherwise compromise isolation, performance, and reliability. 
     More particularly, the smart-bond technique entails bonding or fusing selected first and second regions of a semiconductive substrate to an insulative substrate and then separating the two substrates to leave semiconductive protrusions or islands on the insulative substrate. To reuse the semiconductive substrate, one repeats the bonding and separation to form-semiconductive protrusions on another insulative substrate. The semiconductive protrusions can be made into transistors which are interconnected to form integrated circuits which are not only smaller, faster, and more efficient but also less costly than conventional integrated circuits with silicon-on-insulator technology. 
     Other embodiments apply the selective bonding and substrate separation steps two or more times to make an integrated circuit having two or more circuit levels, in other words, a “three-dimensional” integrated circuit. More particularly, this entails bonding selective regions of a semiconductive substrate to a first insulative substrate to form a first set of semiconductive protrusions, which are then made into a first set of interconnected transistors to form a first circuit level. The bonding and separation are then repeated using the same semiconductive substrate to form a second set of semiconductive protrusions on a second insulative substrate positioned over the first set of interconnected transistors. Transistors are formed from the second set of protrusions and subsequently interconnected to complete a second circuit level. Thus, the present invention also offers an efficient method of making three-dimensional integrated circuits with the performance advantages of silicon-on-insulator technology. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a top view of a part of a semiconductive donor substrate  12  having a number of integral semiconductive protrusions  14  for use in fabricating an integrated circuit; 
     FIG. 2 is a cross-sectional view of donor substrate  12  taken along line  2 — 2 , illustrating two particular semiconductive protrusions  14   a  and  14   b,  which include respective top portions  15   a  and  15   b  and respective base portions  16   a  and  16   b;    
     FIG. 3 is a cross-sectional view of an integrated-circuit assembly resulting from bonding or fusing select regions of substrate  12 , specifically top portions  15   a  and  15   b  of protrusions  14   a  and  14   b,  to an insulative substrate  18 ; 
     FIG. 4 is a cross-sectional view of the FIG. 3 assembly after separation of semiconductive substrate  12  from insulative substrate  18  leaves top portions  15   a  and  15   b  of protrusions  14   a  and  14   b  bonded to substrate  18 ; 
     FIG. 5 is a cross-sectional view of the FIG. 4 assembly after planarizing top portions  15   a  and  15   b,  forming drain and source regions  20   d  and  20   s,  and depositing or growing an overlying gate insulation layer  22 . 
     FIG. 6 is a cross-sectional view of the FIG. 5 assembly after forming gates  24   a  and  24   b,  an interconnecting conductor  25 , and an overlying insulative layer  26 ; 
     FIG. 7 is a cross-sectional view of the FIG. 6 assembly after forming new protrusions  28   a  and  28   b  in semiconductive donor substrate  12  and bonding them to insulative layer  26 ; 
     FIG. 8 is a cross-sectional view of the FIG. 7 assembly after separating donor substrate  12  from insulative layer  26 , forming top portions  29   a  and  29   b  of protrusions  28   a  and  28   b  into transistors  29   a′  and  29   b ′, and interconnecting them through conductor  35 ; and 
     FIG. 9 is a block diagram of a generic integrated memory circuit fabricated in accord with the method and structures of FIGS. 1-8. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following detailed description, which references and incorporates FIGS. 1-9, describes and illustrates specific embodiments, or versions, of the invention. These embodiments, offered not to limit but only to exemplify and teach, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art. 
     FIGS. 1-8 show a number of views and structures, which taken collectively and sequentially, illustrate an exemplary method of forming an integrated circuit incorporating silicon-on-insulator, and more generally semiconductor-on-insulator technology. The method, as shown in FIG. 1, begins with a semiconductive donor substrate  12 . (The term “substrate,” as used herein, broadly encompasses any structure or surface, regardless of composition, which may directly or indirectly support all or any portion of an integrated circuit.) Semiconductive donor substrate  12  serves as source of semiconductive material, for example, silicon. However, in other embodiments, donor substrate  12  consists of gallium-arsenic, germanium, silicon-carbide, or combinations of these materials. Thus, the invention is not limited to any particular semiconductive material. 
     Donor substrate  12  includes a number of semiconductive protrusions or islands  14 , which will ultimately be bonded to an insulative substrate to form semiconductor-on-insulator structures. The protrusions are noncontiguous in this embodiment to promote device isolation. FIG. 2, a cross-sectional view of donor substrate  12  taken along line  2 — 2 , particularly shows two semiconductive protrusions  14   a  and  14   b,  not only as being integral to substrate  12  but also as including respective planar top portions  15   a  and  15   b  and respective base portions  16   a  and  16   b.  In this exemplary embodiment, base portions  16   a  and  16   b  are narrower than corresponding top portions  15   a  and  15   b.  The top portions are generally square in shape with sides of one micron or less; the bases are generally rounder with a diameter of one-half micron or less; and the overall height of the protrusions, which is one micron or less, matches that of the top side dimensions. However, other embodiments of the invention provide various protrusions ranging from heterogeneous, amorphous outcroppings to highly congruent geometric solids. In fact, in one embodiment of the invention, the protrusions comprise whole transistors or portions of transistors, with appropriate doping and so forth. Thus, the invention encompasses any form, shape, and size of protrusion or island. 
     Protrusions  14  may be formed using any number of techniques. For example, co-pending and co-assigned patent application Ser. No. 08/745,708, teaches a method of forming silicon protrusions. This application, entitled Silicon-on-Insulator Islands and Method for Their Formation, is incorporated herein by a reference. In addition, U.S. Pat. No. 5,691,230, entitled Technique for Producing Small Islands of Silicon on Insulator, teaches a technique of forming silicon pillars and fully undercutting them with oxide formations to form silicon-on-insulator structures. The exemplary method adapts this technique to form protrusions  14  by only partially undercutting the pillars. 
     More particularly, this technique starts with a lightly doped silicon wafer, for example, a p-type wafer, grows or deposits 10-to-30 nanometer-thick, oxide layer on the wafer, and then grows or deposits a 100-nanometer thick layer of silicon nitride atop the oxide layer. Afterward, a series of perpendicularly intersecting trenches are patterned in the nitride and oxide layers to define individual island formations, with the trenches being directionally etched to a depth of around 200 nanometers, measured from the top of the nitride layer into the silicon substrate. The technique next deposits or grows another silicon nitride layer, with a thickness less than 100 nanometers, on the top and sides of the protrusions and then directionally etches away the silicon nitride on the tops, leaving silicon nitride on the sides of the protrusions. To form the narrow base portions, one isotropically etches into the silicon substrate, with the silicon nitride in place to protect the protrusion tops. 
     Lastly, the nitride and oxide are removed to leave protrusions such as those shown in FIGS. 1 and 2. 
     As FIG. 3 shows, the next step bonds or fuses select regions of semiconductive substrate  12 , specifically top portions  15   a  and  15   b  of protrusions  14   a  and  14   b,  to an insulative carrier substrate  18 . In the exemplary embodiment, insulative carrier substrate  18  is a smooth, polished, and oxidized insulative layer, such as silicon oxide, which has been grown or deposited on a semiconductive wafer. However, other embodiments provide the insulative carrier substrate as a sapphire or quartz structure optically polished to a smooth finish. Pre-bonding preparations also include oxidizing carrier substrate  18  in a high-temperature, that is 800-1100° C., environment and cleaning the donor and carrier substrates in, for example, a standard RCA or hydrophilization clean. 
     The actual bonding may follow any number of techniques. Bonding in the exemplary embodiment occurs in the same temperature range used for oxidation. More specifically, it entails placing semiconductive donor substrate  12 , specifically top portions  15   a  and  15   b,  in contact with portions of the oxidized surface of insulative carrier substrate  18  for a period of time. Some embodiments apply an optional electrostatic force or other clamping force to facilitate a stronger bond than can be achieved under weight of the semiconductive donor substrate alone. A bond between top portions  15   a  and  15   b  of donor substrate  12  and contacting portions of the surface of carrier substrate  18  results after about 5 minutes in the high-temperature environment. 
     After bonding, the semiconductive donor and insulative carrier substrates, which have different thermal-expansion coefficients, are allowed to cool. In the exemplary embodiment, the silicon underlying the insulative layer of the carrier substrate contracts more than the insulative layer, causing carrier substrate  18  to bow and thus to shear, or break, base portions  16   a  and  16   b  of protrusion  14   a  and  14   b  in two. One then separates donor substrate  12  and the lower-most base portions of protrusions  14   a  and  14   b  from carrier substrate  16 , leaving top portions  15   a  and  15   b  of protrusions  14   a  and  14   b  bonded to carrier substrate  18 . 
     Other embodiments break base portions  16   a  and  16   b  by heating substrates  12  and  16  above the bonding temperature, again relying on differences in thermal-expansion coefficients of the donor and insulative substrates. Still other embodiments apply a known smart-cut technique which entails hydrogen-ion implantation to create a heat-activatable cleavage plane through the base portions of the protrusions, prior to bonding. Substrates  12  and  16  are then heated to thermally activate the plane; thereby cleaving the protrusion base portions in two. For more details on this approach, refer, for example, to M. Breul et al., “Smart-Cut: A New Silicon on Insulator material technology based on Hydrogen Implantation and Wafer Bonding,” (Proceedings 1996 International Conference on Solid State Devices and Materials, Japan, Journal of Applied Physics, Part 1, Vol. 36, no. 3B, pp. 1636-41, 1996) which is incorporated herein by reference. Regardless of the chosen separation technique, the resulting structure resembles FIG. 4, which shows top portions  15   a  and  15   b  of the semiconductive protrusions bonded to insulative carrier substrate  18 . 
     FIG. 5 shows that the next steps of the exemplary method entails planarizing the bonded protrusions and forming them into respective transistors  15   a′  and  15   b′ . The exemplary method applies conventional chemical-mechanical polishing to planarize the top (broken) surfaces of the bonded protrusions. However, a variety of other planarization techniques are available. Some entail doping the protrusions to form etch stops and then etching the protrusions using chemical and plasma-assisted processes. Some embodiments apply these known procedures to reduce the bonded protrusions to ultra-thin semiconductive layers with thicknesses of 100 nanometers or less. 
     The transistors formed from the bonded protrusions may be of any type. For example, in some embodiments, the transistors are field-effect transistors, floating-gate transistors, bipolar junction transistors, or combinations of two or more of these transistors as in BiCMOS circuits. In fact, the protrusions may be formed into any device or component which can be made from semiconductive material. 
     The exemplary method forms top portions  15   a  and  15   b  into field-effect transistors  15   a′  and  15   b′  by treating them as wells in a conventional CMOS process. Accordingly, the portions are doped via ion implantation to form n- or p-type drain and source regions  20   d  and  20   s  and a gate insulation layer  22  is deposited or grown over and between the doped protrusions. Notably, the application of oxide or other insulative material over and the between the doped protrusions not only highlights the absence of parasitic devices between the transistors, but also illustrates that the selective, or intelligent, bonding of semiconductive material only where devices are desired simplifies and improves device isolation by omitting material that could form parasitic devices such as transistors and diodes. Parasitic devices compromise reliability by promoting transistor latch-up and other component failures. In contrast, conventional wafer-bond methods, for example those addressed in the Background, indiscriminantly bond silicon to the entire surface on an insulative substrate, fostering parasitic device formation and potentially requiring additional, more costly isolation techniques to achieve isolation comparable to the present “smart-bonding” technique. 
     After forming gate insulation layer  22 , the method forms gates  24   a  and  24   b  and interconnects them via a conductor  25 . The gates and conductor are metal or polysilicon or a combination. Formation of an insulative layer  26  completes fabrication of the structure shown in FIG. 6, which for sake of clarity omits typical drain, source, and body contacts. The structure resembles that of a typical integrated circuit having a single level of components and one or more levels of interconnections. 
     FIG. 7 shows that the basic smart bonding technique for forming semiconductor-on-insulator structures is useful for forming an integrated circuit having two or more circuit levels, with each circuit level including one or more active or passive components and associated interconnections. However, prior to repeating the smart bonding technique with insulative layer  26  serving as a new insulative carrier substrate, semiconductive donor substrate  12  undergoes planarization and protrusion-formation procedures (similar to those already described) to produce a second set of protrusions  28 , of which protrusions  28   a  and  28   b  are representative . Since each sequence of protrusion formation, protrusion separation, and preparatory planarization operations removes only a few microns of semiconductive material, donor substrate  12  may be reused hundreds or even thousands of times. The protrusions are then bonded to insulative layer  26 . 
     Subsequently, the exemplary method, in accord with the procedures outlined for FIGS. 4-6, entails separating the bonded top portions  29   a  and  29   b  of protrusions  28   a  and  28   b  from substrate  12 , forming them into transistors  29   a′  and  29   b′,  and then interconnecting them through conductor  35 , as shown in FIG.  8 . Other structures formed during this series of steps include drain and source regions  30   d  and  30   s,  gate insulation layer  32 , and gates  34   a  and  34   b.  The resulting “three-dimensional” integrated circuit includes two levels of interconnected components. 
     Exemplary Embodiment of a Three-Dimensional Integrated Memory Circuit Incorporating Silicon-on-Insulator Structures 
     FIG. 9 shows one example of the unlimited number of integrated circuits which would benefit from incorporation of the silicon-on-insulator structures of the present invention: a generic integrated memory circuit  40 . Memory circuit  40 , which operates according to well-known and understood principles, is generally coupled to a processor (not shown) to form a computer system. More particularly, circuit  40  includes a memory array  42  which comprises a number of memory cells  43 , a column address decoder  44 , and a row address decoder  45 , bit lines  46 , word lines  47 , and voltage-sense-amplifier circuit  48  coupled to bit lines  46 . 
     In the exemplary embodiment, the memory cells, the address decoders, and amplifier circuit are formed as silicon-on-insulator devices. Moreover, in other embodiments, certain components, for example, decoders  44  and  45  and amplifier  48 , are formed on a different level than memory array  42 , not only to minimize the average distance between the cells of array  42  and these components but also to allow for more cells on a given circuit level. Further embodiments even provide three-dimensional, that is, multi-level memory arrays, with each level of the array having its own decoders and amplifier circuits. 
     CONCLUSION 
     In furtherance of the art, the inventor has presented a smart-bond technique for making silicon-on-insulator, more generally semiconductor-on-insulator structures. Unlike conventional bonding techniques that covered entire insulative surfaces with silicon, the smart-bond technique attaches semiconductive material only where semiconductive devices are desired, avoiding the buckling and cracking that can occur with continuous silicon coverage, while also achieving better device isolation. In addition, the smart-bond technique allows repeated use of a single semiconductive donor wafer to produce hundreds, even thousands, of semiconductor-on-insulator wafers. Moreover, the smart-bond technique allows fabrication of three-dimensional integrated circuits. 
     The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.