Abstract:
An analog signal gain controller and equalizer with an increased signal bandwidth for reducing intersymbol interference (ISI) within a digital data signal.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to analog signal gain adjustment and equalization, in particular, to analog signal gain controllers and equalizers that adaptively compensate for analog signal distortions due to analog signal transmission through a cable. 
   As is well-known, data communication via Ethernet (e.g., 100 Mb and 1 Gb per second) is accomplished by transmitting and receiving data bits as analog signals over cables such as category 5 (CAT5) unshielded twisted pair (UTP), with the receiver recovering the digital data bits and clock from the transmitted analog signal. The signals containing the data are typically distorted in signal gain and phase as they are transmitted over long cable lengths at high frequencies. The received signal usually has a higher amplitude than that for which the receiver circuitry is designed. Accordingly, an automatic gain control (AGC) circuit lowers the gain to a level so that the data processing in subsequent circuit stages, such as an equalizer and analog-to-digital converter (ADC), can be done at lower signal levels, and thus at lower power. Additionally, the channel distortion must be equalized or otherwise corrected so as to allow the data clock signal to be properly recovered from the received signal, thereby minimizing the bit error rate (BER) associated with the recovered data. 
   Such signal equalization is typically done prior to clock or data recovery, with the equalization compensating for the cable loss by reshaping the signal to be closer to its original waveform to minimize intersymbol interface (ISI) within the recovered data signal. 
   Cable dispersion loss is generally linearly proportional to the cable length and to the square root of the data rate, thereby making the maximum data rate or transmission frequency dependent upon the cable length. Accordingly, as is well known in the art, an adaptive equalizer synthesizes a frequency response that is inversely proportional to the frequency response of the cable. Various adaptive signal equalizers have been developed, including those described in U.S. Pat. Nos. 5,455,843, 5,841,810, 6,545,622, and 6,492,876, the disclosures of which are incorporated herein by reference. 
   SUMMARY OF INVENTION 
   In accordance with the presently claimed invention, an analog signal gain controller and equalizer is provided with an increased signal bandwidth for reducing intersymbol interference (ISI) within a digital data signal. 
   In accordance with one embodiment of the presently claimed invention, an analog signal equalizer includes, at least in part, an input signal electrode, operational amplifier circuitry and first equalization circuitry. The input signal electrode is to convey a first input analog signal VI 1 . The operational amplifier circuitry includes first and second input electrodes and first and second output electrodes, wherein the first operational amplifier circuitry output electrode is to convey a first output analog signal VO 1 , and a ratio VO 1 /VI 1  of the first output and input analog signals is proportional to frequency. The first equalization circuitry is coupled to the first input signal electrode and the first operational amplifier circuitry. The first equalization circuitry includes: a first feedback impedance network coupled between the first operational amplifier circuitry input and output electrodes; a first input impedance network coupled to the first input signal electrode and having an impedance magnitude inversely proportional to frequency; a first input resistance coupled in parallel with the first input impedance network; and first input signal summing circuitry coupled between the first input impedance network and the first operational amplifier circuitry input electrode. 
   In accordance with another embodiment of the presently claimed invention, an analog signal equalizer includes, at least in part, operational amplifier means and first equalizer means. The operational amplifier means is for amplifying a first intermediate analog signal to provide a first output analog signal VO 1 . The first equalizer means is for receiving a first input analog signal VI 1  and in response thereto providing the first intermediate analog signal, wherein a ratio VO 1 /VI 1  of the first output and input analog signals is proportional to frequency, and the first equalizer means includes
         first feedback impedance means for feeding back at least a portion of the first output analog signal VO 1 ,   first input impedance means for conveying at least a first portion of the first input analog signal VI 1  with an impedance magnitude inversely proportional to frequency,   first input resistance means for resistively conveying at least a second portion of the first input analog signal VI 1 , and first input signal summing means for summing at least the first and second portions of the first input analog signal VI 1  to provide the first intermediate analog signal.       

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a combined analog signal gain controller and equalizer in accordance with one embodiment of the presently claimed invention. 
       FIG. 2  is a schematic diagram of the input impedance circuitry for the circuit of  FIG. 1 . 
       FIG. 3  is a schematic diagram of the feedback impedance circuitry for the circuit of  FIG. 1 . 
   

   DETAILED DESCRIPTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
   Referring to  FIG. 1 , an analog signal gain controller and equalizer  10  in accordance with one embodiment of the presently claimed invention includes an operational amplifier circuit  12 , input impedance networks  14   p ,  14   n , and feedback impedance networks  16   p ,  16   n , all interconnected substantially as shown. The operational amplifier circuit  12  is fully differential i.e., both the input and output signals are differential. Accordingly, two input impedance networks and two feedback impedance networks are used, as shown, to accommodate the differential input signal  11 , having positive  11   p  and negative  11   n  signal phases, to provide the differential output signal  13 , having positive  13   p  and negative  13   n  signal phases. 
   Referring to  FIG. 2 , in accordance with a preferred embodiment, each of the input impedance networks  14   p  and  14   n , one of which is depicted here, includes a resistance  22   a  (having a resistance value RIp) coupled in parallel with an impedance network implemented with additional resistances  22   b ,  22   c ,  22   d  and capacitances  24   a ,  24   b ,  24   c , interconnected as shown. This network of resistors  22   b ,  22   c ,  22   d  and capacitors  24   a ,  24   b  and  24   c  collectively have an impedance ZIp(f) having an impedance magnitude inversely proportional to frequency, thereby serving as a high pass filter. In accordance with techniques well-known in the art, the resistances  22   a ,  22   b ,  22   c ,  22   d  and capacitances  24   a ,  24   b ,  24   c  can easily be implemented in integrated circuit form (e.g., using appropriately biased or connected metal oxide semiconductor field effect transistors). The primary resistance  22   a  can be made variable through the use of an appropriate control signal  23  (e.g., a digitally controlled analog signal having a variable magnitude for controlling the bias of the device(s) used to implement the resistance  22   a ). Additionally, a more complex impedance network can be implemented using additional resistances and capacitances coupled in a manner similar to that shown. 
   The output signal  15   p  from this impedance network goes to a summing circuit  20   p  (preferably an active summing circuit, many types of which are well-known in the art), which provides the signal  17   p  for the operation amplifier circuit  12  ( FIG. 1 ). The use of this summing circuit  20   p  provides isolation between its input  15   p  and output  17   p  signals, and also allows an additional  15   a  to be introduced via summation with the primary input signal  15   p . Such additional input signal  15 A can be another signal, compensated in a manner similar to the primary compensated signal  15   p , from elsewhere within the receiver. For example, the primary compensated signal  15   p  can be the data signal within the receiver circuitry, while the additional compensated signal  15   a  can be a data signal originating within the transmitter circuitry. 
   Referring to  FIG. 3  a preferred embodiment of the feedback impedance networks includes a variable resistance  26   p  (having a resistance value RF 1 ) coupled in parallel with a variable capacitance  28   p  (having a capacitance value CF 1 ). For purposes of the adaptive equalization process, control signals  27 ,  29  are used to control the variable resistance and capacitance values of the feedback resistance  26   p  and capacitance  28   p  (e.g., digitally controlled analog signals for controlling the respective biasing levels of the devices used to implement the resistance  26   p  and capacitance  28   p ). 
   Using the input  14  and feedback  16  impedance networks discussed above in connection with  FIGS. 2 and 3 , it can be shown that the signal transfer characteristic from the input to the output, e.g., a ratio of the corresponding output and input voltages can be expressed as follows:
 
 V on/ VIp =(− RF 1/ RIp )*(1+ RIp/ZIp ( f ))/(1+ RF 1* S*CF 1)
 
   The factor RF 1 /RIp defines the AGC function, while the factor RIp/ZIp(f) defines the adaptive equalization boost. 
   Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.