Abstract:
A method includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    Not applicable. 
       BACKGROUND 
       [0002]    The disclosed subject matter relates generally to semiconductor devices and, more particularly, to modeling memory cell skew sensitivity. 
         [0003]    Modeling systems are widely used to simulate the performance of integrated circuits, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and combinations thereof. Device modeling allows designers to simulate the feasibility of circuit designs. 
         [0004]    A commonly modeled integrated circuit device is a memory cell, such as a static random access memory (SRAM) cell. A typical SRAM cell includes three transistor pairs, a pass transistor pair, a pull-down transistor pair, and a pull-up transistor pair. Typically, transistors in the cell are fabricated to be substantially the same, but due to process variation, there is a mismatch for the threshold voltages of the transistors. The cell and/or transistor mismatches affect the stability of the memory cell. 
         [0005]    SRAM modeling involves the use of statistical models that address the likely process variation and attempt to identify the operating parameters of the SRAM cell over the expected range of values. When evaluating an SRAM cell design, it is useful to simulate operation of the cell to determine read and write stability. Common stability parameters are access disturb margin (ADM) for read stability and write margin (WRM) for write stability. The margin of the cell is generally defined as a ratio between the critical current to maintain SRAM stability (I CRIT ) to the sigma of I CRIT . 
         [0006]    Typical modeling techniques for modeling cell margin assume a constant I CRIT  sensitivity to transistor mismatch (i.e., threshold voltage skew between the paired transistors). However, because I CRIT  sensitivity does vary with threshold voltage skew, this simplifying assumption introduces error into the simulation, thereby affecting design and hardware correlation. 
         [0007]    This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above. 
       BRIEF SUMMARY 
       [0008]    The following presents a simplified summary of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. 
         [0009]    One aspect of the disclosed subject matter is seen in a method that includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result. 
         [0010]    Another aspect of the disclosed subject matter is seen in a computing apparatus including a processor programmed with instructions for performing a method for simulating a memory cell having a plurality of transistors. The method includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0011]    The disclosed subject matter will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and: 
           [0012]      FIG. 1  is a simplified block diagram of a computing apparatus implementing a simulation application in accordance with one illustrative embodiment of the present subject matter; 
           [0013]      FIG. 2  is a diagram of a memory cell for which individual transistor mismatch parameters are determined by distributing a cell mismatch parameter; 
           [0014]      FIG. 3  is a diagram illustrating critical current sensitivity curves for the transistors in the memory cell of  FIG. 2 ; 
           [0015]      FIG. 4  is a diagram illustrating critical current sensitivity curves for a simplified example with two transistors; and 
           [0016]      FIG. 5  is a simplified flow diagram of a method for determining a disturb margin of the memory cell of  FIG. 2  in accordance with another illustrative embodiment of the present subject matter. 
       
    
    
       [0017]    While the disclosed subject matter is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosed subject matter to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosed subject matter as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0018]    One or more specific embodiments of the disclosed subject matter will be described below. It is specifically intended that the disclosed subject matter not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. Nothing in this application is considered critical or essential to the disclosed subject matter unless explicitly indicated as being “critical” or “essential.” 
         [0019]    The disclosed subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the disclosed subject matter with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the disclosed subject matter. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. 
         [0020]    Referring now to the drawings wherein like reference numbers correspond to similar components throughout the several views and, specifically, referring to  FIG. 1 , the disclosed subject matter shall be described in the context of a modeling computing apparatus  100 .  FIG. 1  provides a simplified diagram of selected portions of the hardware and software architecture of the computing apparatus  100  such as may be employed in some aspects of the present subject matter. The computing apparatus  100  includes a processor  105  communicating with storage  110  over a bus system  115 . The storage  110  may include a hard disk and/or random access memory (RAM) and/or removable storage, such as a magnetic disk  120  or an optical disk  125 . The storage  110  is also encoded with an operating system  130 , user interface software  135 , and a simulation application  140 . The user interface software  135 , in conjunction with a display  150 , implements a user interface  150 . The user interface  150  may include peripheral I/O devices such as a keypad or keyboard  155 , mouse  160 , etc. The processor  105  runs under the control of the operating system  130 , which may be practically any operating system known in the art. The simulation application  140  is invoked by the operating system  130  upon power up, reset, user interaction, etc., depending on the implementation of the operating system  130 . The simulation application  140 , when invoked, performs a method of the present subject matter. The user may invoke the simulation application  140  in conventional fashion through the user interface  150 . Note that although a stand-alone system is illustrated, there is no need for the data to reside on the same computing apparatus  100  as the simulation application  140  by which it is processed. Some embodiments of the present subject matter may therefore be implemented on a distributed computing system with distributed storage and/or processing capabilities. 
         [0021]    It is contemplated that, in some embodiments, the simulation application  140  may be executed by the computing apparatus  100  to implement the device modeling techniques described herein with reference to  FIGS. 2-4 . Data for the simulation may be stored on a computer readable storage device (e.g., storage  110 , disks  120 ,  125 , solid state storage, etc.). 
         [0022]    Turning now to  FIG. 2 , a diagram of an exemplary SRAM memory cell  200  is provided. The SRAM cell  200  includes a wordline  205 , bit lines  210 L,  210 R, pass transistors  215 L,  215 R, pull-up transistors  220 L,  220 R, and pull-down transistors  225 L,  225 R. The cross-coupled pull-up transistors  220 L,  220 R, and pull-down transistors  225 L,  225 R define a storage element of the SRAM cell  200 , and the pass transistors  215 L,  215 R are controlled by the wordline  205  to enable the storage element to be accessed for a read or write operation via the bit lines  210 L,  210 R. The SRAM cell  200  illustrated in  FIG. 2  is a conventional 6T SRAM cell. Other memory cell topologies, may be used for the device simulation, such as a 4T cell. The principles of operation for an SRAM cell are known, so they are not described in detail herein. 
         [0023]    To simulate the operation of the SRAM cell  200 , the simulation application  140  employs nominal threshold voltages for each of the transistors and distributes an overall cell mismatch, σ mm (cell) to generate individual transistor mismatches, σ mm (tr). In determining the stability of the SRAM cell  200 , the simulation application  140  determines the critical current, I CRIT , of the cell. As will be described in greater detail below, the transistor mismatches are generated by statistically distributing the cell mismatch, σ Vtmm (cell), to the individual transistors, while incorporating the dependency between I CRIT  sensitivity and transistor skew. As shown in  FIG. 2 , the transistor mismatches are designated by σ Vtmm (pul), σ Vtmm (pur), σ Vtmm (pdl), σ Vtmm (pdr), σ vtmm (pgl), and σ Vtmm (pgr), where “pu” designates the pull-up transistors  220 L,  220 R, “pd” designates the pull-down transistors  225 L,  225 R, and “pg” designates the pass transistors  215 L,  215 R. 
         [0024]    As illustrated in reference to  FIG. 3 , the I CRIT  sensitivity for each transistor is dependent on the transistor mismatch, σ Vtmm (tr). The sensitivity curves provided in  FIG. 3  are illustrative in nature. The sensitivity curves illustrated in  FIG. 3  may be generated empirically for a particular process node by fabricating and measuring test devices. In other embodiments, an analytical sensitivity function may be derived by calculating or measuring the sensitivities at different sigma mismatch values, and subsequently, using a polynomial or a power law equation to fit the data. The data illustrated in  FIG. 3  may be characterized generally as I CRIT  sensitivity, S x , for a given transistor is a function of transistor mismatch, σ Vtmm (tr). 
         [0000]        S   x   =f (σ Vtmm ( tr )).
 
         [0025]    In the illustrative curves of  FIG. 3 , the sensitivity over the range from zero to four sigma is nearly linear. In one embodiment, the simulation application  140  uses a linear equation to approximate the sensitivity for each transistor. In other embodiments, a non-linear equation or a look-up table may be used. 
         [0026]    To illustrate the distribution of the cell mismatch across the transistors, a simplified example using two transistors will be discussed.  FIG. 4  illustrates a simplified sensitivity curve for the two transistors, Tr 1 , Tr 2 .  FIG. 5  illustrates a simplified flow diagram of a method for distributing the cell mismatch. As will be discussed below, the method of  FIG. 5  may be extended to cover any number of transistors, such as the 6 transistors  215 L,  215 R,  220 L,  22 R,  225 L,  225 R shown in  FIG. 2 . 
         [0027]    In method block  500 , the cell mismatch is designated. The cell mismatch may be an ADM or a WRM parameter. Typically, the margin of the cell  200  is determined by selecting a particular cell mismatch and simulating the cell operation to determine if it passes read and/or write tests and has acceptable yield. If the cell fails, the mismatch is incremented, and the simulation is repeated. The iterative simulation repeats until the cell  200  passes. The designated mismatch at the iteration where the cell fails represents the margin of the cell  200 . The iterative approach may also start in the mismatch range where the cell passes, and iterate until the cell fails. In that case, the mismatch of the first failing iteration represents the cell margin. Using either approach identifies a boundary cell mismatch, where the cell passes at the boundary and fails at the next higher cell mismatch. This boundary cell mismatch represents the cell margin (e.g., ADM or WRM) of the cell  200 . 
         [0028]    In method block  510 , initial values, σ Vtmm (0), for the transistor mismatches are determined. For example, the initial mismatches for all of the transistors may be set at 2 sigma. Using the sensitivity functions illustrated in  FIG. 4  based on the initial transistor mismatches (i.e., step 0), the sensitivities for each transistor are determined in method block  520 . As described above, linear or non-linear models or look-up tables may be used to approximate the sensitivity curves as a function of transistor mismatch. 
         [0029]    Based on the sensitivities determined at step 0 using  FIG. 4 , the cell mismatch is distributed to the individual transistors in method block  530 . The general equation for distributing the cell mismatch to n transistors is: 
         [0000]    
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 TrX 
                 ) 
               
             
             = 
             
               
                 
                   
                     σ 
                     
                       m 
                        
                       
                           
                       
                        
                       m 
                     
                   
                    
                   
                     ( 
                     cell 
                     ) 
                   
                 
                  
                 • 
                  
                 
                     
                 
                  
                 
                   S 
                   X 
                 
               
               
                 
                   
                     S 
                     1 
                     2 
                   
                   + 
                   
                     S 
                     2 
                     2 
                   
                   + 
                   … 
                   + 
                   
                     S 
                     n 
                     2 
                   
                 
               
             
           
         
       
     
         [0030]    Applying the general equation to the two transistor case illustrated in  FIG. 4 , provides specific equations for distributing the cell mismatch: 
         [0000]    
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 
                   Tr 
                    
                   
                       
                   
                    
                   1 
                 
                 ) 
               
             
             = 
             
               
                 
                   
                     σ 
                     
                       m 
                        
                       
                           
                       
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                       m 
                     
                   
                    
                   
                     ( 
                     cell 
                     ) 
                   
                 
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                 • 
                  
                 
                     
                 
                  
                 
                   S 
                   1 
                 
               
               
                 
                   
                     S 
                     1 
                     2 
                   
                   + 
                   
                     S 
                     2 
                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 
                   Tr 
                    
                   
                       
                   
                    
                   2 
                 
                 ) 
               
             
             = 
             
               
                 
                   
                     σ 
                     
                       m 
                        
                       
                           
                       
                        
                       m 
                     
                   
                    
                   
                     ( 
                     cell 
                     ) 
                   
                 
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                 • 
                  
                 
                     
                 
                  
                 
                   S 
                   2 
                 
               
               
                 
                   
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                     1 
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                   + 
                   
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                     2 
                     2 
                   
                 
               
             
           
         
       
     
         [0031]    Based on the new calculated transistor mismatch values, the sensitivity values are updated using the sensitivity function of  FIG. 4 , as represented by step 1. The distributing of the cell mismatch to individual transistors and the determining of the sensitivity values in method blocks  520  and  530  are repeated (e.g., step 2 in  FIG. 4 ) until the change in the transistor mismatches between iterations is less than a predetermined threshold. This condition represents convergence in method block  540 . 
         [0032]    Transistor mismatch equations may be defined for all of the transistors  215 L,  215 R,  220 L,  22 R,  225 L,  225 R in the cell. These equations may be used with the sensitivity functions represented in  FIG. 3  to statistically distribute the cell mismatch. 
         [0000]    
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 PUL 
                 ) 
               
             
             = 
             
               
                 
                   
                     σ 
                     
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                       m 
                     
                   
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                     ( 
                     cell 
                     ) 
                   
                 
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                   S 
                   PUL 
                 
               
               
                 
                   
                     S 
                     PUL 
                     2 
                   
                   + 
                   
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                     PUR 
                     2 
                   
                   + 
                   
                     S 
                     PDL 
                     2 
                   
                   + 
                   
                     S 
                     PDR 
                     2 
                   
                   + 
                   
                     S 
                     PGL 
                     2 
                   
                   + 
                   
                     S 
                     PGR 
                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 PUR 
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                     ( 
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                     PDL 
                     2 
                   
                   + 
                   
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                     PDR 
                     2 
                   
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                     PGL 
                     2 
                   
                   + 
                   
                     S 
                     PGR 
                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 PDL 
                 ) 
               
             
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                     σ 
                     
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                        
                       
                           
                       
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                       m 
                     
                   
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                     ( 
                     cell 
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                     PDL 
                     2 
                   
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                     S 
                     PGL 
                     2 
                   
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                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 PDR 
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                       m 
                     
                   
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                     2 
                   
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                     PDR 
                     2 
                   
                   + 
                   
                     S 
                     PGL 
                     2 
                   
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                     S 
                     PGR 
                     2 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 σ 
                 Vtmm 
               
                
               
                 ( 
                 PGL 
                 ) 
               
             
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                     σ 
                     
                       m 
                        
                       
                           
                       
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                       m 
                     
                   
                    
                   
                     ( 
                     cell 
                     ) 
                   
                 
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                   S 
                   PGL 
                 
               
               
                 
                   
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                     PUL 
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                     PUR 
                     2 
                   
                   + 
                   
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                     PDL 
                     2 
                   
                   + 
                   
                     S 
                     PDR 
                     2 
                   
                   + 
                   
                     S 
                     PGL 
                     2 
                   
                   + 
                   
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                 σ 
                 Vtmm 
               
                
               
                 ( 
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                     ( 
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                     2 
                   
                   + 
                   
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                     2 
                   
                   + 
                   
                     S 
                     PGL 
                     2 
                   
                   + 
                   
                     S 
                     PGR 
                     2 
                   
                 
               
             
           
         
       
     
         [0033]    Techniques for simulating the operation of the cell  200  based on the nominal threshold voltages and the distributed transistor mismatches are known to those of ordinary skill in the art, and therefore they are not described in greater detail herein. By iteratively determining the sensitivities and transistor mismatches, the effects of I CRIT  sensitivity may be incorporated into the model, thereby improving the accuracy of the results. 
         [0034]    The particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the claims below.