Abstract:
A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Description:
BACKGROUND  
       [0001]     Increasing demand for high-performance integrated circuit (“IC”) design may prompt an increase in the number of input/output (“I/O”) connections (i.e., bond pads) for a defined die size. An increased number of I/O connections currently may be accommodated with one of at least two commonly-known techniques. In a first technique, multiple rows of I/O connections are staggered in which the bond pads from one row are offset relative to bond pads from another row. Staggered designs generally require an increase in die size, and thus a staggered design presents an undesirable increase in production costs. Furthermore, additional bond fingers may be necessary to accommodate additional power and ground connections to maintain IC functionality, thereby further increasing manufacturing costs.  
         [0002]     A second technique of increasing the number of I/O connections comprises reducing bond pad size, thereby allowing a greater number of bond pads to be formed on the die. However, decreased bond pad size necessitates a wirebond wire of reduced diameter (i.e., cross-sectional area of the wire). Decreasing wire diameter presents multiple disadvantages. One disadvantage is an increase in resistance and inductance in the wire and thus a decrease in IC performance quality. Another disadvantage is introduced by a wire “sweeping” (i.e., moving out of place) effect during a common molding process. To counteract wire sweeping, wire length must be reduced, thereby increasing complexity of manufacture. A third disadvantage may arise in dies with a staggered design and reduced bond pad size. Due to a dense bond pad pitch, bond wires may be placed closely together, thereby increasing the risk of crossing multiple wires.  
         [0003]     A decrease in wire diameter, which increases wire inductance, may present several additional disadvantages. For example, an increased wire inductance may necessitate an increase in the number of power and ground connections needed for the IC to properly function. In turn, an increase in the number of power and ground connections may limit the amount of die space available for I/O connections. To maintain high performance levels, I/O connections may be dropped to the substrate, thereby reducing available substrate routing area.  
       BRIEF SUMMARY  
       [0004]     The problems noted above are solved in large part by a method that uses multiple wires to connect a die bond pad with a bond post. One exemplary embodiment may comprise bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     For a detailed description of the preferred embodiments of the invention, reference will now be made to the accompanying drawings in which:  
         [0006]      FIGS. 1   a - 1   c  show the formation of a wirebond between a die and substrate bond finger in accordance with two embodiments of the invention;  
         [0007]      FIGS. 2   a - 2   c  illustrate various processes pertaining to the bond pad-to-die connections illustrated in  FIGS. 1   a - 1   c;    
         [0008]      FIGS. 3   a - 3   d  illustrate an alternative embodiment of forming connections between a bond pad and a bond post;  
         [0009]      FIG. 4  illustrates a process pertaining to the embodiments of  FIGS. 3   a - 3   d;    
         [0010]      FIGS. 5   a - 5   d  show an alternative embodiment of forming wirebond connections on bond pads between multiple dies;  
         [0011]      FIG. 6  shows a process that pertains to the embodiment of  FIGS. 5   a - 5   d;    
         [0012]      FIGS. 7   a - 7   c  show another embodiment of forming wirebond connections on bond pads between multiple dies; and  
         [0013]      FIG. 8  shows a process that pertains to the embodiment of  FIGS. 7   a - 7   c.   
     
    
     NOTATION AND NOMENCLATURE  
       [0014]     Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. When used as a noun, the terms “bond” and “wirebond” are intended to indicate an electrical connection of two or more entities. When used as a verb, the term “bond” is intended to indicate the implementation of a bond as defined above. Further, the term “bond post” may be used interchangeably with the term “bond finger” and/or any commonly used, synonymous term. The terms “outer die pad,” “bond pad,” “die bond pad” and/or “outer die bond pad” also may be used interchangeably.  
       DETAILED DESCRIPTION  
       [0015]     The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.  
         [0016]     Presented herein are techniques to create multiple ball bonds atop existing bonds with minimal impact on IC reliability. These techniques increase the number of I/O connections on a die without incurring some or all of the previously mentioned difficulties. In accordance with various preferred embodiments of the invention, by using Stand Off Stitch Wirebond technology (“SSB”) (or other appropriate bonding technology) to conjoin multiple bonds and increase the total amount of wire between these bonds, the techniques presented below substantially increase the cross-sectional area of each wire connection relative to the cross-sectional area of a single wire connection. This increase in cross-sectional area of wire reduces connection resistance, improves connection inductance and allows an increase in the number of I/O connections on a fixed-size die without a loss in performance quality.  
         [0017]      FIGS. 1   a  and  1   b  show one exemplary embodiment and  FIG. 2   a  shows a process associated with this embodiment.  FIGS. 1   a  and  1   b  show an IC package  96  that comprises a pair of dies  100  and  102 . Each die comprises one or more outer die pads  98 . The outer die pads  98  and outer die pads  88  are used to provide electrical connectivity between circuitry formed on the die and devices external to the IC package  96 . The IC package  96  also comprises a plurality of bond posts  104 . Each bond post  104  can be electrically connected to one or more of the outer die pads  98  or one or more of the outer die pads  88 . The purpose of the bond posts is to facilitate connections being made between external devices and the dies&#39; outer die pads. In the example of  FIG. 1   a , a wire  109  within the IC package  96  interconnects one of the die pads  98  to one of the bond posts  104 . As such, one end of the wire  109  is bonded to a die pad  98  and the opposite end of the wire  109  is bonded to a bond post  104 . In at least some embodiments, the outer die pads  98  may be of a size such that a desired number of outer die pads  98  can be formed on the die  102 .  
         [0018]     Referring now to  FIGS. 1   a  and  2   a , a preferred process begins with the creation of a low loop wirebond (block  200  in  FIG. 2   a ) in which the wire  109  is connected between a bond post  104  and an outer die pad  98 . More specifically, a wedge bond  106  is formed on the bond post  104 , thereby electrically mating the wire  109  to the bond post  104 . Further, a ball bond  108  is formed on the outer die pad  98 , thereby electrically mating the other end of the wire  109  to the outer die pad  98 . Thus, a current pathway is formed between the outer die pad  98  and the bond post  104 . In other embodiments, any type of bond may be used for the wedge bond  106  and/or the ball bond  108 . For example, a ball bond may be substituted for a wedge bond as desired. Further, any of a variety of loop profiles (i.e., physical wire arrangements) can be used to implement wires of varying angles and shapes as desired.  
         [0019]     After bonding the wire  109  in place as shown in  FIG. 1   a , a second wire  111  is bonded in place as shown in  FIG. 1   b  and described in block  202  of  FIG. 2   a . In at least one embodiment, the wire  111  is bonded in place with a SSB technique or some other appropriate bonding technique. More specifically, the process includes forming a ball bond  110  on the bond post  104  and forming a wedge bond  112  on top of the ball bond  108 . In the embodiment of  FIG. 1   b , the wires  109  and  111  are adhered to two separate locations on the bond post  104 , while the wires  109  and  111  are adhered to the same location on the outer die pad  98 . Further, because two wires are used to connect the pad  98  to the bond post  104 , the cross-sectional area of the combined wires  109  and  111  is greater than if only one of the wires were used, effectively reducing the resistance between the pad  98  and the bond post  104 . Because of low wire height requirements between dies, the disclosed technique may be useful for stacked die ICs.  
         [0020]      FIG. 1   c  illustrates an alternative embodiment in which the ends of the wires  109  and  111  that adhere to the bond post  104  are adhered to a common location on the bond post  104  rather than, as in  FIG. 1   b , two separate locations. The technique depicted in  FIG. 1   c  is also described in  FIG. 2   b  and comprises creating a low loop wirebond (block  250 ) in which the wire  109  is bonded in place between bond post  104  using a wedge bond  106  and the outer die pad  98  using a ball bond  108  as described above and as shown in  FIG. 1   a . In block  252 , a ball bond or any appropriate type of bond then may be created as illustrated in  FIG. 1   c  in which the wire  111  is bonded in place. More specifically, one end of the wire  111  is adhered to the bond post  104  by way of a ball bond  110  formed on the wedge bond  106 . The other end of the wire  111  is adhered to the outer die post  98  by way of a wedge bond  112  formed on top of the ball bond  108 .  
         [0021]      FIG. 1   d  illustrates yet another alternative embodiment nearly identical to the embodiment presented in  FIG. 1   c  with the exception of an additional wire  113  bonded to the bond post  104  and the wedge bond  112 . The technique depicted in  FIG. 1   d  is also illustrated in  FIG. 2   c  and comprises creating a low loop wirebond (block  276 ) in which the wire  109  is bonded in place between the bond post  104  using a wedge bond  106  and the outer die pad  98  using a ball bond  108  as described above and as shown in  FIG. 1   a . In block  278 , a ball bond  110  or similar bond (e.g., a SSB technique) then may be created as illustrated in  FIG. 1   c , in which the wire  111  is bonded in place as described above. In block  280 , one end of a wire  113  is adhered to the bond post  104  by way of a wedge bond  116 . The other end of the wire  113  is adhered to the outer die pad  98  by way of a ball bond  114  formed atop the wedge bond  112 , as illustrated in  FIG. 1   d . In this way, the cross sectional area of wire connecting the outer die pad  98  and the bond post  104  is greater than if only one of the wires was used, substantially reducing wire inductance, improving conductivity and reducing IC design and manufacturing costs. In this way, performance may be improved by bonding any number of wires to the outer die pad  98  and the bond post  104 .  
         [0022]     Another such technique is illustrated in  FIGS. 3   a - 3   c , with  FIG. 3   a  being generally duplicative of  FIG. 1   a  for ease of following the discussion below.  FIGS. 3   a - 3   c  each show an IC  96  comprising a plurality of bond posts  104  and a die  100  stacked atop a die  102  comprising multiple outer die pads  98 . The technique depicted in  FIGS. 3   a - 3   c  is also illustrated in  FIG. 4  and comprises establishing a ball bond  302  on the outer die pad  98  and removing the wire attached to the ball bond  302  (block  400 ). In block  402 , a ball bond  304  may be formed on the bond post  104  and connected to a wedge bond  310  formed atop the ball bond  302  by way of a wire  303 , as illustrated in  FIG. 3   b . In block  404 , a wire  305  may be adhered to the bond post  104  by way of a wedge bond  306  and to the outer die pad  98  by way of a ball bond  308  formed atop the wedge bond  310 . As previously mentioned, the scope of disclosure is not limited to the types of bonds described above. Bond types may be freely interchanged as desired. For example, in another embodiment, block  404  may comprise electrically connecting the bond post  104  and the bond pad  98  by way of a wire  305  bonded to the bond post  104  with a ball bond and bonded to the wedge bond  310  with any type of bond (not shown).  
         [0023]     In an example, the outer die pad  98  is of a size such that a maximum of a 0.8 mm diameter wire can be bonded to the outer die pad  98 . A wire with a diameter greater than 0.8 mm generally would not be used, because such a wire may touch neighboring wires or outer die pads  98 , causing a short circuit and compromising the functional integrity of the IC  96 . Because a 1 mm diameter wire is considered to be a standard size wire, the thinner 0.8 mm diameter wire has a greater inductance than the standard size wire. However, implementing any of the techniques described above causes the total cross-sectional area of wires connecting the outer die pad  98  to the bond post  104  to be greater than the cross-sectional area of a single wire connecting the outer die pad  98  to the bond post  104 . Thus, the overall inductance of the wires may be equal or superior to the inductance of the 0.8 mm wire or even the 1 mm wire. Similarly, the resistance of the wires may be substantially lower than the resistance of a single wire, thereby allowing a greater amount of current to be transferred between the outer die pad  98  and the bond post  104 .  
         [0024]     The techniques disclosed herein are not limited to bonding die bond pads to bond posts. Such double-bonding techniques also may be applied to wires connecting die bond pads to other die bond pads, as illustrated in  FIGS. 5   a - 5   c .  FIGS. 5   a - 5   c  each show an IC  96  comprising a die  100  stacked atop a die  102 . The die  100  comprises a plurality of outer die pads  88  and the die  102  comprises a plurality of elongated outer die pads  99 . The technique depicted in  FIGS. 5   a - 5   c  is also illustrated in  FIG. 6  and comprises forming a ball bond  500  on an outer die pad  88  and removing the wire attached to the ball bond  500  (block  600 ). In block  602 , a wire  603  is adhered to the outer die pad  99  by way of a ball bond  502  and to the outer die pad  88  by way of a wedge bond  504  formed on top of the ball bond  500 , as shown in  FIG. 5   b . In block  604 , a wire  605  may be adhered to the outer die pad  99  by way of a ball bond  506  formed atop the outer die pad  99  and to the outer die pad  88  by way of a wedge bond  508  formed atop the wedge bond  504 , as illustrated in  FIG. 5   c . In at least some embodiments, any number of wires may be bonded or otherwise electrically connected to the outer die pad  88  and the outer die pad  99 . The scope of disclosure is not limited to the types of bonds previously discussed; bond types may be interchanged with any of a variety of bond types as desired.  
         [0025]     Another die-to-die double-bonding technique is illustrated in  FIGS. 7   a - 7   c .  FIGS. 7   a - 7   c  each show an IC  96  comprising a die  100  stacked atop a die  102 . The die  100  comprises a plurality of outer die pads  88  and the die  102  comprises a plurality of outer die pads  98 . The technique depicted in  FIGS. 7   a - 7   c  is also illustrated in  FIG. 8  and comprises bonding a SSB ball bond  700  or other appropriate bond to an outer die pad  98  of a die  102  and removing the wire, thus leaving only the ball bond  700  on the pad  98  (block  800 ). A second ball bond  702  then is bonded to an outer die pad  88  of a die  100  and is electrically connected by way of a wire  706  to a wedge bond  704  formed atop the ball bond  700  (block  802 ). Finally, a ball bond  708  is bonded to the ball bond  702  and is electrically connected by way of a wire  712  to a wedge bond  710  formed atop the wedge bond  704  (block  804 ).  
         [0026]     The subject matter disclosed herein may be applied to a single die or multiple dies. While the above embodiments describe specific types of bonds, any type of bond may be substituted for a particular bond (e.g., a ball bond substituted for a wedge bond). All bonds and double bonds, described above, may be created using any bonding technique, such as SD wirebond loops and any variations thereof (e.g., all low-loop and ultra-low-loop bond techniques comprising SSB bonds, wedge bonds, UL bonds, escargot bonds, FJ loop bonds and folded loop bonds). For example, a wedge bond described above may be replaced with an escargot bond. The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.