Abstract:
A method of fabricating an X-ray detector array element. The method decreases consumption of masks during photolithography. A first mask defines a gate line on a substrate. A second mask defines a semiconducting island on a gate insulation layer. A third mask defines a common line and a data line on the gate insulation layer, and source and drain electrodes are simultaneously formed on the semiconducting island, thereby obtaining a TFT structure. A fourth mask defines a first conductive layer on a planarization layer. A fifth mask defines first and second via holes penetrating the planarization layer. A sixth mask defines a third conductive layer, a fourth conductive layer, and a first opening.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method of fabricating an image sensor. More particularly, the present invention relates to a method of fabricating an X-ray detector array including a plurality of pixels, each including a storage capacitor and a thin film transistor (TFT).  
           [0003]    2. Description of the Background Art  
           [0004]    Electronic matrix arrays find considerable application in X-ray image sensors. Such devices generally include X and Y (or row and column) address lines transversely and longitudinally spaced apart and across at an angle to one another, thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. a pixel) to be selectively addressed. These elements in many instances are memory cells or pixels of an electronically adjustable memory array or X-ray imaging array.  
           [0005]    Typically, at least one switching or isolation device such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs and diodes act as switching elements for energizing or otherwise addressing corresponding memory cells or storage capacitors.  
           [0006]    In FIG. 1, a background X-ray detector for capturing digital radiographic images is illustrated. The X-ray detector includes a plurality of pixels  3 , each including a thin film transistor (TFT)  5  and a storage capacitor  7 . The storage capacitor  7  in each pixel includes a charge collector electrode  4  that functions as a top plate of the storage capacitor, and a pixel electrode  11  that functions as a bottom electrode of the capacitor.  
           [0007]    [0007]FIG. 2 is a top view of a background X-ray detector pixel. FIG. 2B is a sectional view taken along line C-C′ of FIG. 2A. As shown in FIGS. 2A and 2B, each pixel of the background art includes a substrate  200 , a gate electrode  205 , a gate line  206 , a first gate insulation layer  210 , an a-Si layer  215 , an α-Si (amorphous silicon) layer  215 , an n +  α-Si layer  220 , a common line  225 , a source electrode  230 , a drain electrode  235 , a data line  240 , a planarization layer  245 , a first via hole  250 , a second via hole  255 , a bottom electrode (a pixel electrode)  260 , a dielectric layer  265 , and a top electrode (a charge collector electrode)  270 . In addition, symbol Cs indicates a storage capacitor.  
           [0008]    The method for fabricating the above X-ray detector includes seven steps of photolithography and etching. That is, the background method requires seven masks. The processing steps are concisely described as follows.  
           [0009]    The first photolithography step defines the gate electrode  205  and the gate line  206 .  
           [0010]    The second photolithography step defines the α-Si layer  215  and the n +  α-Si layer  220  to obtain a semiconductor island structure.  
           [0011]    The third photolithography step defines the common line  225 , the source electrode  230 , the drain electrode  235 , and the data line  240 .  
           [0012]    The fourth photolithography step defines the first via hole  250 .  
           [0013]    The fifth photolithography step defines the bottom electrode (the pixel electrode)  260 .  
           [0014]    The sixth photolithography step defines the second via hole  255 .  
           [0015]    The seventh photolithography step defines the top electrode (the charge collector electrode)  270 .  
         SUMMARY OF THE INVENTION  
         [0016]    The inventors of the present invention have recognized that to decrease manufacturing costs, a method that requires utilizing fewer masks than in the background method would be beneficial.  
           [0017]    Thereby, an object of the present invention is to provide a novel method of fabricating an X-ray detector array element.  
           [0018]    Another object of the present invention is to provide a novel method of fabricating an X-ray detector array element, requiring only six masks during photolithography.  
           [0019]    In order to achieve these objects, the present invention provides a novel method of fabricating an X-ray detector array element. A substrate having a capacitor area and a transistor area is provided. A transversely extending gate line is formed on the substrate, wherein the gate line includes a gate electrode in the transistor area. A gate insulation layer is formed on the gate line, the gate electrode, and the substrate. A semiconducting island is formed on the gate insulation layer in the transistor area. A longitudinally extending common line and a longitudinally extending data line are formed on the gate insulation layer, and simultaneously, a source electrode and a drain electrode are formed on the semiconducting island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects to the data line. A planarization layer is formed on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line. A first conductive layer is formed on the planarization layer in the capacitor area. A dielectric layer is formed on the first conductive layer and the planarization layer. A first via hole and a second via hole penetrating the dielectric layer and the planarization layer are formed, wherein the first via hole exposes the surface of the source electrode, and the second via hole exposes part of the surface of the first conductive layer and part of the surface of the common line. A conformal second conductive layer is formed on the dielectric layer, the interior surrounding surface of the first via hole, and the interior surrounding surface of the first via hole. Part of the second conductive layer is removed to form a third conductive layer, a fourth conductive layer, and a first opening. The third conductive layer is isolated from the fourth conductive layer by the first opening, the third conductive layer electrically connects to the source electrode, and the first conductive layer electrically connects to the common line by the fourth conductive layer. Thus, a storage capacitor structure composed of the first conductive layer, the dielectric layer, and the third conductive layer in the capacitor area is obtained.  
           [0020]    The present invention also provides another method of fabricating an X-ray detector array element. A substrate having a capacitor area and a transistor area is provided. A transversely extending gate line is formed on the substrate, wherein the gate line includes a gate electrode in the transistor area. A gate insulation layer is formed on the gate line, the gate electrode, and the substrate. A semiconducting island is formed on the gate insulation layer in the transistor area. A longitudinally extending common line and a longitudinally extending data line are formed on the gate insulation layer, and simultaneously, a source electrode and a drain electrode are formed on the semiconducting island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects the data line. A planarization layer is formed on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line. A first conductive layer having a first opening is formed on the planarization layer in the capacitor area, wherein the first opening exposes the planarization layer above the common line. A dielectric layer is formed on the first conductive layer and the planarization layer. A first via hole and a second via hole penetrating the dielectric layer and the planarization layer are formed. The first via hole exposes the surface of the source electrode, the second via hole exposes part of the surface of the first conductive layer and part of the surface of the common line, and the second via hole and the first opening overlap. A conformal second conductive layer is formed on the dielectric layer, the interior surrounding surface of the first via hole, and the interior surrounding surface of the second via hole. Part of the second conductive layer is removed to form a third conductive layer, a fourth conductive layer, and a second opening. The third conductive layer is isolated from the fourth conductive layer by the second opening, the third conductive layer electrically connects to the source electrode, and the first conductive layer electrically connects to the common line by the fourth conductive layer. Thus, a storage capacitor structure composed of the first conductive layer, the dielectric layer, and the third conductive layer in the capacitor area is obtained. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    A more complete appreciation of the present invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:  
         [0022]    [0022]FIG. 1 is a schematic of a background art imager array in which each pixel includes a TFT and a storage capacitor;  
         [0023]    [0023]FIG. 2A is a perspective top view of an X-ray detector pixel of the background art;  
         [0024]    [0024]FIG. 2B is a sectional view taken along line C-C′ of FIG. 2A;  
         [0025]    FIGS.  3 A- 8 A are perspective top views of an X-ray detector array element according to the first embodiment of the present invention;  
         [0026]    FIGS.  3 B- 8 B are sectional views taken along line c-c′ of FIGS.  3 A- 8 A;  
         [0027]    FIGS.  3 C- 8 C are sectional views taken along line d-d′ of FIGS.  3 A- 8 A;  
         [0028]    [0028]FIG. 8D is a perspective top view, according to a modification of the first embodiment of the present invention;  
         [0029]    [0029]FIG. 8E is a sectional view taken along line f-f of FIG. 8D;  
         [0030]    FIGS.  9 A-  14 A are perspective top views of an X-ray detector array element according to the second embodiment of the present invention;  
         [0031]    FIGS.  9 B- 14 B are sectional views taken along line c-c′ of FIGS.  9 A- 14 A; and  
         [0032]    FIGS.  9 C- 14 C are sectional views taken along line e-e′ of FIGS.  9 A- 14 A. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]    First Embodiment  
         [0034]    FIGS.  3 A- 8 A are perspective top views of an X-ray detector ray element according to the first embodiment of the present invention. FIGS.  3 B- 8 B are sectional views taken along line c-c′ of FIGS.  3 A- 8 A. FIGS.  3 C- 8 C are sectional views taken along line d-d′ of FIGS.  3 A- 8 A. In order to simplify the illustration, the accompanying drawings show a substrate in only one sample pixel region. That is, although only one pixel region is shown, the actual number of pixel regions may be very large.  
         [0035]    In FIGS. 3A, 3B, and  3 C, a substrate  300 , such as a glass substrate, having a capacitor area  301  and a transistor area  302  is provided. Then, deposition and a first photolithography procedure using a first mask (also referred to as a first photo engraving process, PEP I) are performed, and a transversely extending gate line  310  is formed on the substrate  300 . The gate line  310  includes a gate electrode  320  in the transistor area  302 .  
         [0036]    It should be noted that FIG. 3A shows the gate line  310  having a protruding portion  320  in the transistor area  302 , serving as the gate electrode  320 . Nevertheless, the present invention is not intended to limit the position of the gate electrode. For example, the gate line  310  located in the transistor area  302  can also serve as the gate electrode  320 , as shown in FIGS. 8D and 8E. The illustration of the FIGS. 8D and 8E will be described as a modification of the first embodiment.  
         [0037]    In FIGS. 3A, 3B, and  3 C, a gate insulation layer  330  is formed on the gate line  310 , the gate electrode  320 , and the substrate  300 . The gate line  310  and the gate electrode  320  may be metal formed by deposition. The gate insulation layer  330  maybe SiO 2 , SiN x , or SiON formed by deposition.  
         [0038]    In FIGS. 4A, 4B, and  4 C, an amorphous silicon layer (α-Si layer, not shown) is deposited on the gate insulation layer  330 , and then a doped amorphous silicon layer (e.g. n +  α-Si, not shown) is deposited on the amorphous silicon layer. Next, a second photolithography procedure using a second mask (PEP II) is performed, and part of the doped amorphous silicon layer and the amorphous silicon layer are etched to form a semiconducting island on the gate insulation layer  330  in the transistor area  302 . The semiconducting island is composed of a patterned amorphous silicon layer  410  and a patterned doped amorphous silicon layer  420 .  
         [0039]    In FIGS. 5A, 5B, and  5 C, a conductive layer (not shown) is deposited on the gate insulation layer  330  and the semiconducting island. Then, a third photolithography procedure using a third mask (PEP III) is performed to remove part of the conductive layer (not shown), and a longitudinally extending common line  510  and a longitudinally extending data line  520  are formed on the gate insulation layer  330 , and simultaneously, a source electrode  530  and a drain electrode  540  are formed on the doped amorphous silicon layer  420 . Then, using the source electrode  530  and the drain electrode  540  as a mask, part of the doped amorphous silicon layer  420  is etched to expose part of the surface of the amorphous silicon layer  410 . Thus, a thin film transistor (TFT) structure is obtained in the transistor area  302 . Also, the drain electrode  540  electrically connects to the data line  520 .  
         [0040]    In FIGS. 6A, 6B, and  6 C, a planarization layer  610  is formed on the gate insulation layer  330 , the common line  510 , the TFT structure, the data line  520 , and the gate line  310 . The planarization layer  610  may be a spin-on-glass (SOG) or organic layer formed by spin coating. Then, deposition and a fourth photolithography procedure using a fifth mask (PEP IV) are performed, and a first conductive layer  620  is formed on the planarization layer  610  in the capacitor area  301 . The first conductive layer  620  may be indium tin oxide (ITO) or indium zinc oxide (IZO) formed by deposition, serving as a bottom electrode or a pixel electrode.  
         [0041]    In FIGS. 7A, 7B, and  7 C, a dielectric layer  710  is formed on the first conductive layer  620  and the planarization layer  610 . The dielectric layer  710  can be SiN x , SiON, or SiO x  formed by deposition, serving as a dielectric layer of a capacitor. Then, a fifth photolithography procedure using a fifth mask (PEP V) is performed, and a first via hole  720  and a second via hole  730  penetrating the dielectric layer  710  and the planarization layer  610  are formed. The first via  720  exposes the surface of the source electrode  530 , and the second via  730  exposes part of the surface of the first conductive layer  620  and part of the surface of the common line  510 .  
         [0042]    In FIGS. 8A, 8B, and  8 C, a conformal second conductive layer (not shown) is formed on the dielectric layer  710 , the interior surrounding surface of the first via hole  720 , and the interior surrounding surface of the second via hole  730 . The second conductive layer may be indium tin oxide (ITO) or indium zinc oxide (IZO) formed by deposition. Then, a sixth photolithography procedure using a sixth mask (PEP VI) is performed, and part of the second conductive layer is removed to form a third conductive layer  810 , a fourth conductive layer  820 , and an opening  830 . The third conductive layer  810  is isolated from the fourth conductive layer  820  by the opening  830 . The third conductive layer  810  electrically connects to the source electrode  530 , and the first conductive layer  620  electrically connects to the common line  510  by the fourth conductive layer  820 . The third conductive layer  810  serves as a top electrode or a charge collector electrode. Thus, a storage capacitor structure Cs composed of the first conductive layer  620 , the dielectric layer  710 , and the third conductive layer  810  in the capacitor area  301  is obtained.  
         [0043]    Modification of the First Embodiment  
         [0044]    [0044]FIG. 8D is a perspective top view according to a modification of the first embodiment of the present invention. FIG. 8E is a sectional view taken along line f-f′ of FIG. 8D. Elements in FIGS. 8D and 8E repeated from FIGS.  8 A- 8 C use the same reference numbers. Additionally, because the materials of the parts in the modification is the same as in the above first embodiment, the description of the materials is omitted.  
         [0045]    In FIGS. 8D and 8E, a substrate  300  having a capacitor area  301  and a transistor area  302  is provided. Then, a transversely extending gate line  310  is formed on the substrate  300 . The gate line  310  includes a gate electrode  320  in the transistor area  302 .  
         [0046]    Next, a gate insulation layer  330  is formed on the gate line  310 , the gate electrode  320 , and the substrate  300 . Then, an amorphous silicon layer  410  and a doped amorphous silicon layer  420  are formed on part of the gate insulation layer  330 . Thus, a semiconducting island composed of the amorphous silicon layer  410  and the doped amorphous silicon layer  420  is obtained.  
         [0047]    Next, a longitudinally extending common line  510  and a longitudinally extending data line  520  are formed on the gate insulation layer  330 , and simultaneously, a source electrode  530  and a drain electrode  540  are formed on the doped amorphous silicon layer  420 . Then, using the source electrode  530  and the drain electrode  540  as a mask, part of the doped amorphous silicon layer  420  is etched to expose part of the surface of the amorphous silicon  410 . Thus, a thin film transistor (TFT) structure is obtained on the gate line  310 . Also, the drain electrode  540  electrically connects to the data line  520 .  
         [0048]    Next, a planarization layer  610  is formed on the gate insulation layer  330 , the common line  510 , the TFT structure, the data line  520 , and the gate line  310 . Then, a first conductive layer  620  is formed on the planarization layer  610  in the capacitor area  301 . The first conductive layer  620  serves as a bottom electrode or a pixel electrode.  
         [0049]    Next, a dielectric layer  710  is formed on the first conductive layer  620  and the planarization layer  610 . The dielectric layer  710  serves as a dielectric layer of a capacitor. Then, a first via hole  720 ′ and a second via hole  730  (shown in FIG. 8C) penetrating the dielectric layer  710  and the planarization layer  610  are formed. The first via hole  720 ′ exposes the TFT structure including the surface of the source electrode  530 , and the second via hole  730  (shown in FIG. 8C) exposes part of the surface of the first conductive layer  620  and part of the surface of the common line  510 .  
         [0050]    Next, a conformal second conductive layer (not shown) is formed on the dielectric layer  710 , the interior surrounding surface of the first via hole  720 ′, and the interior surrounding surface of the second via hole  730  (shown in FIG. 8C). Then, referring to FIGS. 8C and 8E, part of the second conductive layer is removed to form a third conductive layer  810 , a fourth conductive layer  820 , and an opening  830 . The third conductive layer  810  is isolated from the fourth conductive layer  820  by the opening  830 . The third conductive layer  810  electrically connects to the source electrode  53 , and the first conductive layer  620  electrically connects to the common line  510  by the fourth conductive layer  820 . The third conductive layer  810  serves as top electrode or a charge collector electrode. Thus, a storage capacitor or a charge collector electrode. Thus, a storage capacitor structure Cs composed of the first conductive layer  620 , the dielectric layer  710 , and the third conductive layer  810  in the capacitor area  301  is obtained.  
         [0051]    Second Embodiment  
         [0052]    FIGS.  9 A- 14 A are perspective top views of an X-ray detector array element according to the second embodiment of the present invention. FIGS.  9 B- 14 B are sectional views taken along line c-c′ of FIGS.  9 A- 14 A. FIGS.  9 C- 14 C are sectional views taken along line e-e′ of FIGS.  9 A- 14 A. In order to simplify the illustrations, the accompanying drawings show a substrate in only one sample pixel region. That is, although only one pixel region is shown, the actual number of pixel regions may be very large.  
         [0053]    In FIGS. 9A, 9B, and  9 C, a substrate  900 , such as a glass substrate, having a capacitor area  901  and a transistor area  902  is provided. Then, deposition and a first photolithography procedure using a first mask (also referred to as a first photo engraving process, PEP I) are performed, and a transversely extending gate line  910  is formed on the substrate  900 . The gate line  910  includes a gate electrode  920  in the transistor area  902 .  
         [0054]    It should be noted that FIG. 9A shows the gate line  910  having a protruding portion  920  in the transistor area  902 , serving as the gate electrode  920 . Nevertheless, the present invention is not intended to limit the position of the gate electrode. For example, the gate line  910  located in the transistor area  902  can serve as the gate electrode  920 , whose illustration is similar to the modification of the first embodiment and thus is not described again here.  
         [0055]    In FIGS. 9A, 9B, and  9 C, a gate insulation layer  930  is formed on the gate line  910 , the gate electrode  920 , and the substrate  900 . The gate line  910  and the gate electrode  920  may be metal formed by deposition. The gate insulation layer  930  may be SiO 2 , SiN x , or SiON formed by deposition.  
         [0056]    In FIGS. 10A, 10B, and  10 C, an amorphous silicon layer (α-Si layer, not shown) is deposited on the gate insulation layer  930 , and then a doped amorphous silicon layer (e.g. n +  α-Si, not shown) is deposited on the amorphous silicon layer. Next, a second photolithography procedure using a second mask (PEP II) is performed, and part of the doped amorphous silicon layer and the amorphous silicon layer are etched to form a semiconducting island on the gate insulation layer  930  in the transistor area  902 . The semiconducting island is composed of a patterned amorphous silicon layer  1010  and a patterned doped amorphous silicon layer  1020 .  
         [0057]    In FIGS. 11A, 11B, and  11 C, a conductive layer (not shown) is deposited on the gate insulation layer  930  and the semiconducting island. Then, a third photolithography procedure using a third mask (PEP III) is performed to remove part of the conductive layer (not shown), and a longitudinally extending common line  1110  and a longitudinally extending data line  1120  are formed on the gate insulation layer  930 , and simultaneously, a source electrode  1130  and a drain electrode  1140  are formed on the doped amorphous silicon layer  1020 . Then, using the source electrode  1130  and the drain electrode  1140  as a mask, part of the doped amorphous silicon layer  1020  is etched to expose part of the surface of the amorphous silicon layer  1010 . Thus, a thin film transistor (TFT) structure in the transistor area  902  is obtained. Also, the drain electrode  1140  electrically connects to the data line  1120 .  
         [0058]    In FIGS. 12A, 12B, and  12 C, a planarization layer  1210  is formed on the gate insulation layer  930 , the common line  1110 , the TFT structure, the data line  1120 , and the gate line  910 . The planarization layer  1210  may be a spin-on-glass (SOG) or organic layer by spin coating. Then, deposition and a fourth photolithography procedure using a fourth mask (PEP IV) are performed, and a first conductive layer  1220  having a first opening  1230  is formed on the planarization layer  1210  in the capacitor area  901 . The first conductive layer  1220  may be indium tin oxide (ITO) or indium zinc oxide (IZO) formed by deposition, serving as a bottom electrode or a pixel electrode. The first opening  1230  exposes part of the planarization layer  1210  above the common line  1110 .  
         [0059]    In FIGS. 13A, 13B, and  13 C, a dielectric layer  1310  is formed on the first conductive layer  1220  and the planarization layer  1210 . The dielectric layer  1310  can be SiN x , SiON, or SiO x  formed by deposition, serving as a dielectric layer of a capacitor. Then, a fourth photolithography procedure using a fourth mask (PEP IV) is performed, and a first via hole  1320  and a second via hole  1330  penetrating the dielectric layer  1310  and the planarization layer  1210  are formed. The first via hole  1320  exposes the surface of the source electrode  1130 , and the second via hole  1330  exposes part of the surface of the first conductive layer  1220  and part of the surface of the common line  1110 . Also, the second via hole  1330  and the first opening  1230  overlap (regarding the opening area).  
         [0060]    In FIGS. 14A, 14B, and  14 C, a conformal second conductive layer (not shown) is formed on the dielectric layer  1310 , the interior surrounding surface of the first via hole  1320 , and the interior surrounding surface of the second via hole  1330 . The second conductive layer may be indium tin oxide (ITO) or indium zinc oxide (IZO) formed by deposition. Then, a sixth photolithography procedure using a sixth reticle (PEP VI) is performed, and part of the second conductive layer is removed to form a third conductive layer  1410 , a fourth conductive layer  1420 , and a second opening  1430 . The third conductive layer  1410  is isolated from the fourth conductive layer  1420  by the second opening  1430 . The third conductive layer  1410  electrically connects to the source electrode  1130 , and the first conductive layer  1220  electrically connects to the common line  1110  by the fourth conductive layer  1420 . The third conductive layer  1410  serves as a top electrode or a charge collector electrode. Thus, a storage capacitor structure Cs composed of the first conductive layer  1220 , the dielectric layer  1310 , and the third conductive layer  1410  in the capacitor area  901  is obtained.  
         [0061]    In comparison with the background art, the present invention only uses six masks to form the X-ray detector array, thereby decreasing costs.  
         [0062]    Finally, while the present invention has been described by way of example and in terms of the above, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the present invention covers various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.