Abstract:
A damascene approach is used to form a recessed structure in a substrate for receiving liquid-deposited solution, such as a carbon nanotube (CNT) solution. The liquid-deposited solution is built-up in the recessed structure, simplifying the coating process and providing a more uniform thickness of the liquid-deposited layer.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates generally to semiconductor processing. 
       BACKGROUND 
       [0002]    A conventional method of forming carbon nanotube structures for memory cells is to coat a wafer having a planarized surface with a carbon nanotube solution (liquid) using a spin coating process with a subsequent bake which results in a ˜25ang layer of carbon nanotubes. To achieve a useful thickness of carbon nanotubes, the wafer is coated and baked 20-30 times. The carbon nanotube film is subsequently patterned and etched to form structures in the film. 
         [0003]    This technique is expensive because much of the carbon nanotube solution is wasted as it is spun off the wafer during the spin coating process. The number of repetitions of spin coating is time consuming, limits throughput and increases cost due to lower spin coating tool utilization. The repeated coat applications also result in a high defect level or density. 
       SUMMARY 
       [0004]    A damascene approach is used to form a recessed structure in a substrate for receiving liquid-deposited solution, such as a carbon nanotube (CNT) solution. The liquid-deposited solution is built-up in the recessed structure, simplifying the coating process and providing a more uniform thickness of the liquid-deposited layer. 
         [0005]    Particular implementations of structure formation in liquid solutions using recessed structures provide one or more of the following advantages: 1) the recessed structure is formed with fewer processing steps; 2) at lower cost; and 3) with fewer defects than conventional methods that use a spin coating process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIGS. 1-5  are cross-sectional views illustrating a process for recessed structure formation using liquid-deposited solution. 
           [0007]      FIG. 6  is a cross-sectional view of a memory cell including a liquid-deposited layer. 
       
    
    
     DETAILED DESCRIPTION 
     Example Processes 
       [0008]      FIGS. 1-5  are cross-sectional views illustrating a process for recessed structure formation using liquid-deposited solution. Referring to  FIG. 1 , the process can begin by spin coating photoresist film  102  on dielectric substrate  104  (e.g., a wafer) and then patterning photoresist film  102  (e.g., using lithography) to define locations on substrate  104  for recessed structures. Substrate  104  can be, for example, an inter-layer dielectric (ILD). Substrate  104  is fully or partially etched and stripped according to the pattern in photoresist film  102 , forming recessed structures  106  in substrate  104 , as shown in  FIG. 2 . Only a single recessed structure is shown in the figures. In a practical implementation, however, a wafer substrate (e.g., silicon dioxide (S i O 2 )) can include multiple recessed structures. Recessed structures  106  can be rectangular, circular or any other desired shape. 
         [0009]    Next, liquid solution  108   a  is deposited on substrate  104  such that recessed structure  106  is filled with liquid solution  108   a , as shown in  FIG. 3 . An example of liquid-deposited solution  108   a  is a carbon nanotube solution. 
         [0010]    Substrate  104  is baked to form recessed plug  108   b , where the numerical designation  108   a  designates a solution and the numerical designation  108   b  designates the recessed plug formed after baking solution  108   a.  In some implementations, portions of recessed plug  108   b  not in the recessed structure  106  are removed using a solvent or blanket etch, as shown in  FIG. 4A . 
         [0011]    Referring to  FIG. 4B , in some implementations photoresist  102  is deposited on substrate  104 , such that photoresist  102  is overlying recessed structure  106 . Photoresist  102  is then etched and stripped leaving a portion of recessed plug  108   b  that overlies recessed structure  106 . In some implementations, a portion of recessed plug  108   b  that remains after etching and stripping may “overhang” recessed structure  106 , as shown in  FIG. 5 . 
         [0012]    The semiconductor structure fabricated as described in reference to  FIGS. 1-5  can be used to fabricate semiconductor devices, such as the memory cell described in reference to  FIG. 6 . 
         [0013]      FIG. 6  is a cross-sectional view of an article of manufacture including recessed plug  108   b  fabricated according to the processes described in reference to  FIGS. 1-5 . In some implementations, the article of manufacture is memory cell  600 , as described in the example below. 
         [0014]    In some implementations, memory cell  600  includes first dielectric layer  114   a  (e.g., silicon dioxide (S i O 2 )) over first metal layer  122  (e.g., AlCu). First dielectric layer  114   a  includes via/bottom electrode  112   a  (e.g., titanium nitride (T i N)). Recessed plug  108   b  (e.g., carbon nanotubes) is formed in dielectric well layer  116  (e.g., silicon nitride (S 3 N 4 )). Top electrode metal layer  110   a  (e.g., T i N) is formed on recessed plug  108   b . Dielectric hard-mask layer  114   b  is formed on recessed plug  108   b . Dielectric hard-mask layer  114   b  is formed with top cap  117  and second dielectric layer  114   c . Second metal layer  110   c  (e.g., AlCu) is formed on second dielectric layer  114   c  and includes via  118  including metal liner  110   b  and via plug  120  (e.g., tungsten (W)). 
         [0015]    Via liner/bottom electrode  112   a  is disposed in first dielectric  114   a  such that recessed plug  108   b  is electrically connected to first metal layer  122 . Metal liner  110   b  is disposed in second dielectric  114   c  such that second metal layer  110   c  is electrically connected to top electrode metal layer  110   a.    
         [0016]    While this document contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.