Abstract:
A laser based vascular illumination system utilizing a FPGA for detecting vascular positions, processing an image of such vasculature positions, and projecting the image thereof onto the body of a patient.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application claims priority on U.S. Provisional Application Ser. No. 61/678,726 filed on Aug. 2, 2012, the disclosures of which are incorporated herein by reference. 
     
    
     BACKGROUND 
     Summary 
       [0002]    A laser based vascular illumination system utilizing a FPGA for detecting vascular positions, processing an image of such vasculature positions, and projecting the image thereof onto the body of a patient. 
     
    
     
       BRIEF DESCRIPTION 
         [0003]      FIG. 1  Block diagram of a system for detecting and illuminating the vasculature in a patient. 
           [0004]      FIG. 2  Shows the signal processing flow of the FPGA. 
           [0005]      FIG. 3  shows the internal bus architecture of the FPGA. 
           [0006]      FIG. 4  shows details of the vein processing. 
           [0007]      FIG. 5  shows the vein processing at the boundary of the image frames. 
           [0008]      FIG. 6  shows further detail of the vein processing at the boundary of the image frames. 
           [0009]      FIG. 7  2-D Moving Window Sum Generator. 
           [0010]      FIG. 8  shows a X-sum generator. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]      FIG. 1  shows a block diagram of a system for detecting and illuminating the vasculature in a patient 
         [0012]    The system shown in the block diagram of  FIG. 1  is used for detecting the location of veins on a patient and illuminating the veins. 
         [0013]    The disclosures of U.S. patent application Ser. No. 12/804,506, now issued as U.S. Pat. No. 8,463,364 are incorporated herein by reference. 
         [0014]    In a preferred embodiment, FIGS. 30-47 of application Ser. No. 12/804,506 illustrates an assembly of a housing that may be used in the present invention. In the present invention, circuit boards 43, 44 and 15 of application Ser. No. 12/804,506 may be modified to contain the circuitry described by the block diagram in  FIG. 1 . The remainder of the device in FIGS. 30-47 can remain substantially the same. 
         [0015]    In  FIG. 1  an FPGA  1  (field programmable gate array) is configured to control a red laser drive  2  which in turn drives a red laser  3 . The output of the red laser  3  is controlled in a manner so as to illuminate the detected veins. A red laser feedback  4  detects the output of the red laser  3  and sends the information to the FPGA  1 . Accordingly, a closed loop is formed whereby the FPGA  1  can both drive the Red laser  3  and receive feedback as to the red laser  3  state. 
         [0016]    FPGA  1  outputs data to an IR laser drive  5  which in turn drives an IR laser  6 . The output of the IR laser  6  is controlled to output an intensity of IR light, aimed at the area of the body where veins are located, sufficient to detect the veins. An IR laser feedback  7  detects the output of the IR laser  6  and sends the information to the FPGA  1 . Accordingly, a closed loop is formed whereby the FPGA  1  can both drive the IR Laser  6  and receive feedback as to the IR laser  6  state. 
         [0017]    FPGA  1  communicates to both a x-mirror drive  8  and a y-mirror drive  9  to drive x-mirror  10  and y-mirror  11  in such a manner that a raster pattern is formed on the patient when the Red laser  3  and the IR laser  6  are coaxially projected thereon. X-mirror feedback  12  and y-mirror feedback  13  detect the positions of the x-mirror  10  and y-mirror  11 , respectively, and communicates such information to the FPGA 1 . 
         [0018]    Top photodiode  23  and bottom photodiode  22  receive the IR Laser  6  reflected off the patient, converts the light into an analog signal which is provided to Top FE  25  and Bottom FE  24 , and then to Top ADC  27  and bottom ADC  25 , respectively. The top FE  25  and the bottom FE  24  are front end circuits that provide analog filtering, gain control and threshold of the analog signals. The Top ADC  27  and bottom ADC  26  are analog to digital converters that convert the analog signals to digital representations thereof to be communicated to the FPGA  1 . Control lines are provided from the FPGA  1  to the top FE  25  and the bottom FE  24  to set parameters such as, for example, gain control and analog filtering. 
         [0019]    From a mechanical standpoint, the red laser  3  and the IR laser  6  are co axially aligned and projected off of mirrors X-mirror  10  and Y-mirror  11  to form a pattern, such as for example, a raster pattern on the patient. The IR laser  6  reflects off the patient and is received by top photodiode  23  and photodiode  22 . The reflected IR light contains information as to the location of the veins (IR light is absorbed by the blood in the veins and therefore the amount or reflected IR light is lower when the IR laser  6  is aimed at a vein. The FPGA  1  time sequentially receives in the signal form the top ADC  27  and the bottom ADC and can form two partial and/or full frame images of the reflected IR light (hereinafter a top channel data and a bottom channel data wherein the top channel data is received from the top ADC  27  and the bottom channel data is received from the bottom ADC). The FPGA  1  processes one or both of the partial and/or full image to detect and enhance the image of the veins. The enhanced image is time sequentially projected by the Red laser  3  onto the patient. 
         [0020]    A CPLD is provided for controlling an LCD  19  with displays user information related to the operating status of the device. It also controls an audio  20  output to provide audible tones to the user. Finally the CPLD  18  controls the switches  21  on the unit for turning on and off the units as well as selecting user modes and entering data. 
         [0021]    A microprocessor PIC MCU  17  is provided for receiving and monitoring the IR laser feedback  7  signal, the red laser feedback  4  signal, the x-mirror feedback  12  signal and the y-mirror feedback  13  signal. Since these signals are also provided to the FPGA  1 , redundancy monitoring of the signals is provided by the PIC MCU  17 . This is particularly important when regulatory requirements require redundant monitoring of the laser power and movement to comply with safety requirements. The NC MCU  17  also monitors the device power management  14 , the Li-ion Battery management  15  circuitry and the Li-ion Fuel gauge  16 . 
         [0022]      FIG. 2  Shows an example of the signal processing flow of the FPGA 
         [0023]      FIG. 2  shows an embodiment of the signal processing algorithm of the FPGA of  FIG. 1 . As described with reference to  FIG. 1 , the image of the reflected IR laser  6  is time sequentially stored in the FPGA  1  as top channel data  30 T and bottom channel data  30 B. 
         [0024]    The X-mirror  10  oscillates about a single axis to move the laser beam from the IR laser  6  to form a line. The beam moves first in one direction and then back in the other direction. It is critical that the left to right image data be in convergence with the right to left data. The top line correlator  31 T measures the shift in the convergence of the top channel data  30 T and supplies the information to the mirror convergence control  34 . Similarly, the bottom line correlator  31 B measures the shift in the convergence of the bottom channel data  30 B and supplies the information to the mirror convergence control  34 . The mirror convergence control  34  can adjust the control signals provided from the FPGA  1  to the x-mirror drive  8  so as to converge the data. 
         [0025]    A top histogram  32 T receives the top channel data  30 T and generates a histogram based upon an entire frame of the top channel data  30 T. Similarly, a bottom histogram  32 B receives the top channel data  30 B and generates a histogram based upon an entire frame of the bottom channel data  30 B. The histograms contain information describing the characteristics of the images, including but not limited to contrast and intensity levels. The top histogram  32 T and the bottom histogram  32 B are provided to exposure control  35 . Exposure control  35  communicates appropriate signals the IR laser drive  5  to adjust the power of the IR laser  6  on a frame by frame basis until the histograms indicate appropriate images. The exposure control  35  also communicates with the top FE  25  and bottom FE  24  to adjust parameters such as setting thresholds and setting electrical gain. 
         [0026]    A top vein processing  33 T block receives the top channel data  30 T and performs image processing to detect vein patterns and provides the enhanced vein image to fused vein projection  36 . Similarly, bottom vein processing  33 B block receives the bottom channel data  30 B and performs image processing to detect vein patterns and provides the enhanced vein image to fused vein projection  36 . The fused vein projection  36  forms a single image and communicates the Image to the alpha blended projection  38 . The fused vein projection  36  can form the single image by merging the images from the top vein processing  33 T and bottom vein processing  33 B. Alternative, the fused vein projection  36  can simply select the best image received from the top vein processing  33 T and the bottom vein processing  33 B. 
         [0027]    Alpha channel  37  forms an image that contains graphical data, such as text or characters. Alpha channel  37  and fused vein projection  36  are provided to alpha blended projection  38  with drives the IR laser drive  5  to display an image which is the combination of the fused vein projection  36  and the alpha channel  37 . 
         [0028]      FIG. 3  shows an example of the internal bus architecture of the FPGA 
         [0029]      FIG. 4  shows details of the top vein processing  33 T and bottom vein processing  33 B. 
         [0030]      FIG. 5  shows the vein processing at the boundary of the image frames. 
         [0031]      FIG. 6  shows further detail of the vein processing at the boundary of the image frames. 
         [0032]      FIG. 7  shows the 2-D Moving Window Sum Generator. 
         [0033]      FIG. 8  shows a X-sum generator.