Abstract:
A technique and structure for simplifying the stitching process is disclosed. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout method for a row/column decoder that reduces the number of blocks when stitching.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of the priority of U.S. Provisional Application No. 60/159,134, filed on Oct. 12, 1999, and entitled “A Layout Technique for Row/Column Decoders to Reduce Number of Blocks When Using Stitching”. 
    
    
     BACKGROUND 
     The present disclosure generally relates to image sensors, and more specifically, to layout techniques for image sensor components using stitching. 
     Many semiconductor-processing foundries have a maximum lithographic size that they may use to form a chip. A common limit, for example, is 20×20 mm 2 . Making a chip larger than that maximum size may be carried out using stitching. Stitching forms different portions of the chip in different areas of the wafer. The different areas are then “stitched” together to form the overall chip. 
     Complicated chips may require a large number of stitches to form an entire circuit. The complexity of the chips may mean higher cost, lower throughput, and higher risk to produce the chip. For example, FIG. 1 shows a layout of a prior art system for the 2K×2K sensor  100 . In the illustrated example, the sensor needs a total of 17 blocks on the reticle and needs to be stitched 24 times. 
     SUMMARY 
     The present system teaches a technique and structure for simplifying the stitching process. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout technique for row/column decoder that reduces the number of blocks when stitching. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Different aspects of the disclosure will be described in reference to the accompanying drawings wherein: 
     FIG. 1 shows a layout of a prior system using multiple blocks; 
     FIG. 2 shows a floor layout plan according to an embodiment of the present disclosure; 
     FIG. 3 shows a basic block diagram of a column decoder; 
     FIG. 4 shows a schematic of the stitching block embodying the column decoder; and 
     FIG. 5 shows a layout of the stitched chip. 
    
    
     DETAILED DESCRIPTION 
     The present disclosure describes a layout technique for stitching blocks to form large image sensors. These sensors are often larger than the typical reticle size of 20×20 mm 2 , and thus, need to be stitched together using several blocks. The technique involves designing a floor plan that minimizes the number of blocks for a two-dimensional stitching project. 
     FIG. 2 shows one example of an improved layout technique for laying out a 2K×2K sensor  200  similar to the one  100  shown in FIG.  1 . However in this illustrated embodiment, the sensor  200  is designed with only 9 blocks that are stitched only 16 times. This is one-third less stitching than in the layout technique used in FIG.  1 . 
     The improved technique utilizes routing lines and repeatable blocks to make connections in the blocks that are used more than once. For example, the top  202  and bottom  204  blocks are each used twice. The blocks  202 ,  204  may include analog signal processors, readout registers, column decoders for the readout registers, and output lines. The analog signal processor and the readout registers may be repeated because they are same for each column. However, the column decoders are designed in an interleaving pattern so that the block  202 ,  204  may be repeated and stitched. The interleaving pattern design is further described below. 
     The left side block  206 , which may be used twice, may include row decoders and input lines. The row decoders are also designed in an interleaving pattern as described below. The right side blocks  208 , which are also used twice, may include analog pads and routing lines. 
     The right corner blocks  210 ,  212  may include unique pad and connections. The left corner blocks  214 ,  216  may include digital block, unique pads, drivers, and connections. The middle blocks  218 , which are used four times, include pixel arrays. 
     In the above example, the number of blocks that needs to be patterned on a reticle is reduced to 15 mm×17 mm by using repeatable blocks. This allows the above-described sensor  200  to be designed on a single reticle. 
     One common problem in a row/column decoder is the need for each portion of the decoder to have a different configuration. This may cause highly complex circuits and arrangements. 
     According to the present system, instead of dividing the row/column decoder into different blocks, a generic block is formed that uses interleaving to form the whole row/column decoder. The interleaving is made between generic blocks and effectively turns each generic block into a separate block. 
     An example is described with reference to FIGS. 3 and 4. In the illustrated example, a column decoder chip  300  may use 1024 column decoders  302  with 25 μm pitch. The reticle size being used (typically 20×20 mm 2 ) requires that this block be divided into four different pieces. According to the present system, instead of dividing the block in this way, a single generic block is used four times. This saves area on the reticle. 
     In order to do this, a generic block is formed which has 256 column decoders. This block is stitched together four times. The generic column decoder  400  is shown in FIG.  4 . The column decoders numbered from 0 (column decoder  402 ) to 1023 (column decoder  404 ) are addressed by the lines shown as NB 0 -B 9 . This will be divided according to the present system into one block of 256 that gets used four times. FIG. 4 shows the four generic blocks  410 ,  412 ,  414 ,  416  stitched together. 
     When the generic blocks  410 ,  412 ,  414 ,  416  are connected, the lines cannot simply be stitched together because that would select four columns for each value of B 9 -B 0 . The present system uses interleaving of the lines to stitch the connections between the blocks  410 ,  412 ,  414 ,  416 . To do this, 6 more lines are added to the address lines B 9 -B 0 . Two extra lines may be added to make sure that no line is floating. Each added line shifts down one line  420  before moving to the next block as shown. Further, lines NB 8  and B 8  are switched or interleaved between each block. Added line  4  and NB 9  are connected together as shown  422 . Added line  1  may also be connected to those two lines to make sure that there are no floating lines. Added line  6  and B 9  are also connected  424  in the generic block. 
     This shifting and interleaving allows the alternate addressing of the columns using the generic design. Therefore, all 1024 decoders may be addressed by stitching together four generic blocks  410 ,  412 ,  414 ,  416 , each having 256 decoders. Similar design may be used in the row decoder to provide alternate addressing of the rows. 
     Care must be taken in stitching blocks that are not multiples of 2. For those blocks, a counter must be adjusted to fit the structure. For example, for a block having 129 column decoders in one block, a counter must be configured to run from 0 to 128 and then jump to 256 to 384, and so on. 
     FIG. 5 shows a mask layout  500  of the stitched chip according to the above-described embodiments. The layout  500  also shows the six added address lines  502  and two extra lines  504 . 
     While specific embodiments of the invention have been illustrated and described, other embodiments and variations are possible. 
     All these are intended to be encompassed by the following claims.