Abstract:
A lower-cost and more precise control methodology of regulating the output voltage of a Flyback converter from the primary side is provided, which works accurately in either continuous voltage mode (CCM) and discontinuous mode (DCM), and can be applied to most small, medium and high power applications such cell phone chargers, power management in desktop computers and networking equipment, and, generally, to a wide spectrum of power management applications. Two highly integrated semiconductor chips based on this control methodology are also described that require very few components to build a constant voltage Flyback converter.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present Utility patent application claims priority benefit of the U.S. provisional application for patent No. 60/691,979 filed on Jun. 16, 2005 under 35 U.S.C. 119(e), and entitled “Primary Side Constant Output Voltage Controller.” The contents of this related provisional application are incorporated herein by reference. 
     
    
     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Not applicable.  
       COPYRIGHT NOTICE  
       [0003]     A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or patent disclosure as it appears in the Patent and Trademark Office, patent file or records, but otherwise reserves all copyright rights whatsoever.  
       FIELD OF THE INVENTION  
       [0004]     This invention relates generally to the field of power conversion. More particularly, to switching mode power supplies with regulated output voltage.  
       BACKGROUND OF THE INVENTION  
       [0005]     With the aggressive growth of battery powered portable electronics, e.g., cell phones, the demand for lower cost, lighter weight and better efficiency battery chargers is very high. Historically, linear power supplies have been employed; however, despite their being low in cost they cannot generally outperform switching mode power supplies, which have lower weight and much higher efficiency. For many applications, the Flyback converter is often chosen from among different switching mode topologies to meet this demand due to its simplicity and good efficiency.  
         [0006]     Over the years, various PWM controller IC chips have been developed and used to build constant voltage Flyback power supplies. Known designed require too many additional components to support the PWM controller IC chip, which increases cost and device size.  
         [0007]      FIG. 1  illustrates a schematic of an exemplary prior-art primary side controlled constant output voltage Flyback converter circuit. Such a converter typically comprises a transformer  201  (which has three windings), a secondary side resistor  301  (which represents the copper loss of transformer  201 ), a primary switch  105 , a secondary rectifier  302 , an output capacitor  303 , and a control IC  104 . A resistor  101  and a capacitor  102  provide the initial start-up energy for IC  104 . Once the Flyback converter is stable, IC  104  is powered by the auxiliary winding (with Na turns) of transformer  201  via rectifier  103 . The output voltage is fed back to the primary side via the auxiliary winding, rectified and filtered by rectifier  107  and capacitor  110 , and sensed by voltage divider resistors  108  and  109 . A resistor  106  senses the current flowing through primary switch  105 . IC  104  is a peak current mode PWM controller.  
         [0008]     The circuit of  FIG. 1  works well as long as the requirement of output voltage regulation is not stringent. Typically, 10% load regulation with a loading from 10% to 100% of its rated maximum load can be met. However, this regulation tends to become poor when loading drops below 10% of its rated load both at least because the transformer copper loss varies with output current and input voltage and/or the auxiliary winding of transformer  201  contains an undesired resonant waveform when the Flyback converter operates at discontinuous current mode (DCM).  
         [0009]     In an attempt to meet this tight regulation requirement, the secondary side controlled Flyback converter shown in  FIG. 2  is often used. Using this configuration, 5% or better load regulation with a loading from 10% to 100% of its rated maximum load can be typically achieved. In circuit shown, the output voltage is sensed as an error signal by voltage divider resistors  305  and  307 , and monitored by a secondary IC  306 . The error signal is then fed back to primary IC  104  via an optical coupler  202 . A known disadvantage of this circuit, however, is relatively high cost. For example, IC  306  and safety approved optical coupler  202  add significant cost, which can be up to 10% of the overall material cost in a typical application.  
         [0010]     Some known approaches for primary feedback control of constant output voltage switching regulators teach the use of a reflected auxiliary winding voltage or current to control the peak voltage. One known deficiency of such known methods is that the output voltage constant control is applicable only in discontinuous conduction mode (DCM) operation, thereby limiting the power capability of the power converter. For continuous conduction mode (CCM) operation, current industry solutions almost entirely rely exclusively on the use of an optocoupler as shown in  FIG. 1 . Typically, they will use the auxiliary current/voltage (e.g., via diode and RC filters) to control the peak primary voltage. When auxiliary voltage (i.e., the control voltage) decreases, the primary voltage is reduced. In addition, the output voltage variation versus load change and/or input voltage is often relatively poor; thus, no tight regulation of input voltage is typically possible.  
         [0011]     In view of the foregoing, what is needed is a relatively low-cost and effective control methodology of regulating the primary side output voltage of a Flyback converter. It would be desirable if at least some of the foregoing limitations of the prior art are overcome for both continuous voltage mode (CVM) and discontinuous mode (DCM) operation, preferably with a minimal number of IC chips; e.g., two IC chips. It is further desirable that the need for a secondary circuit and optical coupler are eliminated, and that the output voltage of a Flyback converter be largely insensitive to temperature variations. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The present invention is illustrated by way of example, and not by way of limitations in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:  
         [0013]      FIG. 1  illustrates a schematic of an exemplary prior-art primary side controlled constant output voltage Flyback converter circuit;  
         [0014]      FIG. 2  illustrates a schematic of an exemplary prior-art secondary side controlled constant output voltage Flyback converter circuit;  
         [0015]      FIG. 3  illustrates, in accordance with an embodiment of the present invention, a schematic of an exemplary primary side controlled constant output voltage Flyback converter circuit implementing a first PWM controller IC chip embodiment of the present invention;  
         [0016]      FIG. 4  illustrates an exemplary block diagram of the first PWM controller IC chip embodiment;  
         [0017]      FIG. 5  illustrates exemplary ideal waveforms of the auxiliary winding voltage, primary switch current and secondary rectifier current of the Flyback converter of  FIG. 3  operating in continuous current mode (CCM);  
         [0018]      FIG. 6  illustrates exemplary ideal waveforms of the auxiliary winding voltage, primary switch current and secondary rectifier current of the Flyback converter of  FIG. 3  operating in discontinuous current mode (DCM);  
         [0019]      FIG. 7  illustrates an exemplary schematic of a primary side controlled constant output voltage Flyback converter circuit implementing the first PWM controller IC chip embodiment in an Emitter Switching configuration according to an embodiment of the present invention;  
         [0020]      FIG. 8  illustrates an exemplary block diagram of a second PWM controller IC chip embodiment of the present invention;  
         [0021]      FIG. 9  illustrates an exemplary schematic of a primary side controlled constant output voltage Flyback converter circuit implementing the second PWM controller IC chip embodiment with an external MOSFET and current sensing resistor, in accordance with an embodiment of the present invention;  
         [0022]      FIG. 10  illustrates a schematic diagram of an exemplary digital frequency jittering circuit that is suitable to implement the foregoing jitter functional block, in accordance with an embodiment of the present invention; and  
         [0023]      FIG. 11  illustrates an exemplary jitter frequency control logic diagram for the exemplary digital frequency jittering circuit of  FIG. 10 , in accordance with an embodiment of the present invention 
     
    
       [0024]     Unless otherwise indicated illustrations in the figures are not necessarily drawn to scale.  
       SUMMARY OF THE INVENTION  
       [0025]     To achieve the forgoing and other objects and in accordance with the purpose of the invention, a variety of techniques to regulate the output voltage of a switching regulator are described.  
         [0026]     Some embodiments of the present invention provide for a primary side, constant output voltage PWM controller system and/or IC for a switching regulator with a transformer having at least a primary, a secondary and an auxiliary winding, that include a reference signal for setting the output voltage level of the switching regulator; a timing generator configured to generate a sample timing signal based on a feedback signal, and is operable for controlling sampling in both a discontinuous current mode and a continuous current mode; two sample-and-hold circuits, one operable for sampling the feedback signal and the other operable for sampling the current of a switched power output device, both being configured with a control input that receives said sample timing signal thereby controls the sampling; an error amplifier, which outputs an error signal based on the difference between the reference signal and the sampled feedback signal; a comparator that is configured to compare one or more ramp signals such as, without limitation, the error signal and/or a slope compensation signal; a PWM controller module that outputs a PWM switching regulator control signal based on an oscillator output and the comparator output; and a gate drive module that receives the PWM control signal and generates a corresponding gate drive signal operable for properly turning, on and off a switched power output device of the switching regulator.  
         [0027]     A multiplicity of other embodiments may further provide variations of the prior embodiments in which the reference signal is a programmable current mirror circuit operable to output a programmed current; and/or in which the sample-and-hold circuit for sampling the current of a switched power output device is removed; and/or in which the switched power output device is a power MOSFET that is configured as the main power switch of the switching regulator; and/or further includes a current sensing circuit for generating the output current feedback signal that optionally comprises a MOSFET connected in parallel with the switched power output device; and/or in which the comparator is a peak current mode PWM comparator with a slope-compensation input.  
         [0028]     Another embodiment of the present invention provides means for achieving the functions described in the foregoing embodiments.  
         [0029]     In yet other embodiments of the present invention, a constant output voltage PWM controller printed circuit board (PCB) module is described that includes a PCB and an embodiment of the foregoing integrated circuit device joined onto the PCB, where the PCB can be optionally populated with the necessary electronic components such that, in functional combination with the integrated circuit (IC) device, the PCB module is operable to perform as a constant voltage switching regulator.  
         [0030]     A method, according to another embodiment of the present invention, is provided for regulating the output voltage of a Flyback converter from the primary side, which method includes steps for regulating the output voltage of the Flyback converter to a desired value, and steps for reducing the temperature/copper loss sensitivity of the output voltage.  
         [0031]     Other features, advantages, and object of the present invention will become more apparent and be more readily understood from the following detailed description, which should be read in conjunction with the accompanying drawings.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     The present invention is best understood by reference to the detailed figures and description set forth herein.  
         [0033]     Embodiments of the invention are discussed below with reference to the Figures. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments. For example, it should be appreciated that those skilled in the art will, in light of the teachings of the present invention, recognized a multiplicity of alternate and suitable approaches, depending upon the needs of the particular application, to implement the functionality of any given detail described herein, beyond the particular implementation choices in the following embodiments described and shown. That is, there are numerous modifications and variations of the invention that are too numerous to be listed but that all fit within the scope of the invention. Also, singular words should be read as plural and vice versa and masculine as feminine and vice versa, where appropriate, and alternatives embodiments do not necessarily imply that the two are mutually exclusive.  
         [0034]     The present invention will now be described in detail with reference to embodiments thereof as illustrated in the accompanying drawings.  
         [0035]     An aspect of the present invention is to provide a relatively low-cost and effective control methodology capably of regulating the output voltage of a Flyback converter from the primary side with reasonably good accuracy from 0% to 100% of its rated load in at least some applications. In this way, the secondary side control circuit and the optical coupler may be eliminated, thereby, reducing costs and improving reliability at least due to a lower component count.  
         [0036]     As mentioned above, at least two factors can account for errors in the voltage regulation of a primary side controlled Flyback converter circuit, which factors include: 1) the transformer copper loss varies with output current and input voltage, and 2) the voltage sensing of the DCM operation is not accurate. To address the first problem, a current source derived from the current of the primary switch is used to compensate the variations. To address the second problem, an adaptive sampling and hold circuit is used to capture the feedback voltage when the current of the secondary winding of the transformer discharges to zero. Based on this control methodology, two associated PWM controller IC chip embodiments will be described in some detail below.  
         [0037]      FIG. 3  illustrates, in accordance with an embodiment of the present invention, a schematic of an exemplary primary side controlled constant output voltage Flyback converter circuit implementing a first PWM controller IC chip  204  embodiment of the present invention. The exemplary circuit shown in the Figure comprises a transformer  201  (which has three windings: primary with N p  turns, secondary with N, turns and auxiliary with N a  turns), a secondary side resistor  301  (which represents the copper loss of transformer  201 ), a secondary rectifier  302 , an output capacitor  303 , and a peak current mode PWM control PWM controller IC  204 . Resistor  101  and capacitor  102  provide the initial start-up energy for PWM controller IC  104 . Once the Flyback converter is stable, PWM controller IC  204  is powered by the auxiliary winding of transformer  201  via rectifier  103 . The output voltage is fed back to the FB input pin of PWM controller IC chip  204  via the auxiliary winding and voltage divider resistors  108  and  109 . Those skilled in the art, in light of the teachings of the present invention, will readily recognize that the feedback for the FB input pin may come from any other suitable source beyond the auxiliary winding of the transformer; by way of example, and not limitation, from the primary winding. In alternate embodiments of the present invention (not shown), the transformer does not have any auxiliary windings, and only has a primary and secondary winding. Those skilled in the art will recognize a multiplicity of alternate and suitable transformer types and interface circuit configurations to be operable with connection to the FB input pin.  
         [0038]     PWM controller IC  204  is optionally capable of self-starting from the input line through a relatively large time constant charging resistor  101  and an energy storage capacitor  102  combination  
         [0039]      FIG. 4  illustrates an exemplary block diagram of the first PWM controller IC chip  204  embodiment. The first PWM controller IC embodiment comprises an internal power MOSFET as the main switch and a current sense MOSFET; hence, no external MOSFET or current sense resistor is needed for relatively low power applications. As illustrated in  FIG. 4 , a Vcc supply  401  provides an internal power supply and reference voltage. The feedback voltage FB is amplified by a Buffer  402  and then sampled and held by a PWM controller IC  403 . In the preferred embodiment of the present invention, the feedback voltage is sampled and held at the point that V FB  has the minimum variation with respect to time. At this point the output diode  302  generally has a minimum voltage and its temperature effect is typically the smallest. In applications that do not require such buffering, this buffer stage may be removed in alternate embodiments (not shown). An error amplifier  404  then compares the feedback voltage with a reference voltage (V ref ). A resistor  408  and a capacitor  409  form a compensation network for error amplifier  404 . A comparator  411  serves as a peak current mode PWM comparator with a slope compensation input. In other embodiments of the present invention (not shown), the comparator may be configured by those skilled in the art to compare any suitable ramp signals depending upon the needs of the particular application.  
         [0040]     A system oscillator  410  provides a frequency jittering function that widens the frequency spectrum and achieves a lower conducting EMI emission. The jittering function is preferable implemented as a digital jitter circuit that is configured to achieve more over-all voltage regulation precision and to largely insensitive to temperature variations and other parasitic components. An example of a preferred frequency jittering circuit is described in connection with  FIG. 10 .  
         [0041]     Alternate embodiments of the present invention may not include the frequency jittering function in system oscillator  410  and/or slope compensation. In many applications, slope compensation and the system oscillator jitter function can improve converter operation in certain input/output operating conditions; however, these functions are completely optional, whereby alternate embodiments of the present invention may not include either one or both.  
         [0042]     A PWM control unit  412  then generates the correct PWM waveform by utilizing a cycle-by-cycle current limiting function. A MOSFET  413  is a high speed MOSFET gate driver. A power MOSFET  415  serves as the main switch, while a MOSFET  414  and a resistor  416  form a current sense circuit. As will be readily apparent to the system designer, some applications may not require resistor  416  to generate the current sensing voltage feedback or it may be located in other circuit configurations, or embedded into other system components. As will be readily recognized by those skilled in the art, depending upon the needs of the particular application and available technology, the power MOSFET ma), be formed in any suitable manner; by way of example, and not limitation, the power MOSFET may be comprised of a multiplicity of smaller MOSFET device to form a single power MOSFET.  
         [0043]     A timing generator  405  senses the negative going-edge of V f  waveform and produces triggering signals for sample-and-hold circuits  403  and  406 .  
         [0044]     A voltage controlled current source  407  then programs the current source to β·I p  according to equation (2) described below, and is useful in many applications to make the feedback voltage largely independent of transformer copper loss. This is achieved by inserting a shunt current source at the mid-point of the feedback voltage divider resistors  108  and  109 . The shunt current source is preferably programmed to be proportional to the current of the primary switch. The calculation of the upper resistor  108  of the feedback voltage divider follows equation (5) below. Those skilled in the art will recognize a multiplicity of alternate and suitable means achieving the same function as voltage controlled current source  407  instead of that shown. Sample-and-hold circuits  403  samples the buffered feedback voltage and sample-and-hold circuits  406  samples the current of the primary switch. In present embodiment, the primary current I p  flows through MOSFET  414  and  415 , and the portion of I p  flowing through MOSFET  414  is inversely proportional to the ON resistance of  414  and  415 . Resistor  416  produces a voltage that is also proportional to the primary current Ip. Sample-and-hold circuit  406  then senses the voltage across Resistor  416 , whereby the output voltage of the sample-and-hold  406  controls the output current of voltage controlled current source  407 . In this way, the combination of  406  and  407  work to carry out equation (2) below.  
         [0045]     It should be appreciated that in contrast with conventional approaches that only work in DCM, the present embodiment implements a method for using “sampled Auxiliary Flyback Voltage” to control the primary current. Sampling the Auxiliary Flyback Voltage at a known time point provides a more accurate representation of the actual output voltage in most applications. The present embodiment is largely independent of auxiliary voltage and/or current variations by, for example, basing output current control based only on primary current sensing and the ratio of T_R/T_ON, which works in both DCM &amp; CCM. Hence, embodiments of the present invention preferably do not use auxiliary voltage to control primary current by essentially scaling the peak current (IPEAK) as proportional to square root of the output voltage, as is done in conventional approaches.  
         [0046]      FIG. 5  illustrates exemplary ideal waveforms of the auxiliary winding voltage, primary switch current and secondary rectifier current of the Flyback converter of  FIG. 3  operating in continuous current mode (CCM). With reference to both  FIGS. 4 and 5 , main switch  415  turns on at t 1 , turns off at t 2  and turns on again at t 3 . The switching period is T, the turn-on time is T on  and the turn-off time is T r . The voltage at the auxiliary winding (V a ) at the time just before t 3  can be expressed as, 
   V   a =( N   a   /N   S )·( V   o   +V   DI   +I   S   ·R   S )  (1)  
         [0047]     We may then assume that shunt current source I 407  of current source  407 , as shown in  FIG. 4 , is programmed by, 
 
 I   407   =β·I   p   (2) 
 
 Since, 
 
 I   p =( N   S   /N   P )· I   S   (3) 
 
 The output voltage sense V f  can be expressed by (resistors  108  and  109 , are referenced as R1 and R2, respectively, for the sake of clarity), 
 
 V   f =( R   2 /( R   1   +R   2 ))·( N   a   /N   S )·( V   o   +V   DI   +I   S   ·R   S )−(( R   1   ·R   2 )/( R   1   +R   2 ))·β· I   S ·( N   S   /N   P )  (4) 
 
 If R 1  is chosen as, 
 
 R   1 =( N   p   ·N   a   ·R   S )/(β· N   S   ·N   S )  (5) 
 
 then, 
 
 V   f =( R   2 /( R   1   +R   2 ))·( N   a   /N   S )·( V   o   +V   DI )  (6) 
 
 Therefore, if the shunt current source I 407  of voltage controlled current source  407  is programmed per equation (2) and the value of R 1  is chosen by equation (5), then output voltage sense V f  is practically independent of the copper loss (I S ·R S ) of transformer  201 . It should also be noted that, for CCM operation, V f  is preferably sampled and held at the time just before t 3 , as it is more optimally sense the feedback voltage at the time just before the primary turns on for CCM and at the time when the current of the secondary winding of the transformer discharges to zero. 
 
         [0048]      FIG. 6  illustrates exemplary ideal waveform is of the auxiliary winding voltage, primary switch current and secondary rectifier current of the Flyback converter of  FIG. 3  operating in discontinuous current mode (DCM). With reference to both  FIGS. 4 and 5 , main switch  415  turns on at t 1 , turns off at t 2  and turns on again at t 4 . The switching period is T, the turn-on time is T on  and the turn-off time is equal to (t 4 -t 2 ). T r  is equal to (t 3 -t 2 ). As shown in  FIG. 6 , the current at the secondary winding of transformer  201  discharges to zero at t 3 . The voltage V a  at the auxiliary winding between times t 3  and t 4  oscillates at a frequency determined by the parasitic inductance and capacitance of the circuit. In this case, V f  is preferably sampled and held at the time just before t 3  to achieve a more accurate feedback voltage.  
         [0049]      FIG. 7  illustrates an exemplary schematic of a primary side controlled constant output voltage Flyback converter circuit implementing the first PWM controller IC chip  204  embodiment in an Emitter Switching configuration according to an embodiment of the present invention. As mentioned before, for low power applications, no external power MOSFET or current sense circuit is needed. Shown in the Figure, the first PWM controller IC chip embodiment is configured to drive an NPN bipolar transistor in an Emitter Switching configuration to boost output power for higher power applications. In such a configuration, with reference to both  FIGS. 4 and 5 , internal MOSFET  415  drives the emitter of external NPN transistor  105 , which serves as the main switch. To achieve further power handling capability and/or switching frequency, an external MOSFET must typically be used as the main switch as shown in  FIG. 9 .  
         [0050]      FIG. 8  illustrates an exemplary block diagram of a PWM controller IC chip embodiment  804 , in accordance with a second of the present invention. PWM controller IC chip  804  does not include internal power MOSFET  415 , current sensing MOSFET  414  and current sensing resistor  416  from the first PWM controller IC chip embodiment. In this second embodiment, the current driving capability of Gate Drive  413  results in improved control for larger MOSFETs. In this second embodiment, Gate Drive  413  is designed with appropriate current driving capability suitable for controlling larger MOSFETs.  
         [0051]      FIG. 9  illustrates an exemplary schematic of a primary side controlled constant output voltage Flyback converter circuit implementing PWM CONTROLLER chip  804  with an external MOSFET and current sensing resistor, in accordance with an embodiment of the present invention.  
         [0052]     The functional blocks shown in the prior embodiments may be implemented in accordance known techniques as will be readily apparent to those skilled in the art. However, some embodiments of the present invention include implementation approaches that are not conventional. For example, without limitation, the foregoing jitter functional block may be implemented as follows.  FIG. 10  illustrates a schematic diagram of an exemplary System oscillator  410  having a digital frequency jittering circuit that is suitable to implement the foregoing jitter functional block, in accordance with an embodiment of the present invention. The frequency jittering in the present embodiment is implemented by a digital control scheme, which departs from known approaches. An oscillator  817  is preferably a current controlled oscillator. There is preferably an uncontrolled, base-line, current sources  801 , which, in one aspect, is present to set a minimum oscillator frequency, Fmin, that the switched current sources will jitter from. In the embodiment shown, the current to oscillator  817  is controlled by a multiplicity of switched current sources  802 - 804  that carry out the jittering of the oscillator&#39;s minimum frequency. The frequency of the system oscillator output signal is generally proportional to the total current entering into oscillator  817 . In alternate embodiments, any number of current sources may be implemented depending upon the needed of the particular application. The jitter behavior is generated by feeding back a pseudo random digital signal to a multiplicity of series connected flip-flops (e.g.,  818  to  823 ). Current sources  801 ,  802 ,  803  and  804  are presently preferred to be 100 μA, 2.5 μA, 5 μA and 10 μA, respectively. Each switched current source is presently configured with at four current control switches (e. g, control switches  805 ,  806 ,  811  and  812  for switched current source  802 ) that are arranged in two parallel legs with each leg having two switches in series. In this way, for current to flow into oscillator  817  at least on leg must have both of its switches turned on. In similar fashion, four switches ( 807 ,  808 ,  813  and  814 ) are connected to switched current source  803  and another four switches ( 809 ,  810 ,  815  and  816 ) are connected to switched current source  804 . All of these switches are closed or open by a control input from an output from the series connected flip-flop chain. In the example shown, the  805  switch is open when Q 5  is at logic “1” and is closed when Q 5  is at logics “0”. Similarly, the  806  switch is open when Q 5  is at logic “0” and is closed when Q 5  is at logics “1” and so on. When all the switched current sources are enabled, a maximum frequency, Fmax, of the system oscillator output signal is achieved. As will be readily apparent to those skilled in the art, in light of the present teachings, the choice of which flip-flop outputs that connect to which current control switch will determine a certain jittering pattern. An aspect of this digital frequency jittering scheme is that the period and the step of frequency variation may be relatively precisely controlled, largely insensitive to temperature variations. It should be appreciated that in contrast to conventional analog techniques for jittering the oscillator frequency, the digital jittering approach of the present embodiment always provide digitally calculated frequency step irrespective of the known shortcomings that analog based techniques suffer from; such as, without limitation, temperature, input, output age dependences, and etc. Those skilled in the art, in light of the present teachings, will readily recognize a multiplicity of alternate and suitable implementations that implement the spirit of the present embodiment. By way of example, and not limitation, current based operation may be replaced with a voltage based approach, and the number and topology of the switches and/or current sources and/or flip-flop chain may be altered as needed for the particular application, and other suitable means to selectively control the pattern of current flowing into the current controlled oscillator.  
         [0053]      FIG. 11  illustrates an exemplary jitter frequency control logic diagram for the exemplary digital frequency jittering circuit of  FIG. 10 , in accordance with an embodiment of the present invention. In the example shown, frequency variation from its maximum (Fmax) to minimum (Fmin) corresponding to the logic states “0” or “1” of Q 2 , Q 3 , Q 4  and Q 5 .  
         [0054]     Having fully described at least one embodiment of the present invention, other equivalent or alternative techniques for a primary side constant output voltage controller according to the present invention will be apparent to those skilled in the art. The invention has been described above by way of illustration, and the specific embodiments disclosed are not intended to limit the invention to the particular forms disclosed. The invention is thus to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the following claims.