Abstract:
Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.

Description:
RELATED APPLICATIONS 
       [0001]    This is a divisional application of U.S. patent application Ser. No. 11/322,669,filed Dec. 30, 2005. 
     
    
     FIELD 
       [0002]    Embodiments of the present invention relate generally to the field of computer architecture, and more particularly to managing memory accesses in said architectures through identifiers associated with memory locations. 
       BACKGROUND 
       [0003]    Software programs operating on a host system often interact with other software, firmware, or hardware components executing on the same host system. The software programs may be divided on the operating environment (hardware and/or software) of the host system based on levels of privilege. The software programs are traditionally protected only by the privileged levels associated with executing code. Each different level of privilege allows software executing within that level to perform a certain set of operations. Programs executing within a given privilege level typically have access to some or all of the resources used by other programs executing in that privilege level and/or lower privilege levels. Thus, there is no protection of software programs within privilege levels on the platform, making the software programs vulnerable to compromise if another software program of the same privilege level becomes compromised. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
           [0005]      FIG. 1  illustrates a platform having dual execution environments to secure memory accesses in accordance with an embodiment of the present invention; 
           [0006]      FIG. 2  illustrates data structures of an auxiliary memory in accordance with an embodiment of the present invention; 
           [0007]      FIG. 3  illustrates a platform having dual processors to provide dual execution environments in accordance with an embodiment of the present invention; 
           [0008]      FIG. 4  illustrates operational phases of the host environment in accordance with an embodiment of the present invention; 
           [0009]      FIG. 5  illustrates operational phases of the auxiliary environment in accordance with an embodiment of the present invention; 
           [0010]      FIG. 6  illustrates an access operation from the host environment in accordance with an embodiment of the present invention; 
           [0011]      FIG. 7  illustrates a context-switching operation from an exiting component in accordance with an embodiment of the present invention; 
           [0012]      FIG. 8  illustrates a context-switching operation from an entering component in accordance with an embodiment of the present invention; and 
           [0013]      FIG. 9  illustrates a platform utilizing virtualization to provide dual execution environments in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Embodiments of the present invention may provide a method, apparatus, and system for enabling a secure platform. More specifically, embodiments of the present invention may provide an architecture providing memory access policies based on associated identifiers. 
         [0015]    Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific devices and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments. 
         [0016]    Further, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. 
         [0017]    The phrase “in one embodiment” is used repeatedly. The phrase generally does not refer to the same embodiment; however, it may. The terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise. 
         [0018]    The phrase “A and/or B” means “(A), (B), or (A and B).” The phrase “at least one of A, B and C” means “(A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).” 
         [0019]      FIG. 1  illustrates a platform  100  having dual execution environments to secure memory accesses, in accordance with an embodiment of the present invention. The platform  100  may have a host execution environment, e.g., host environment  104 , an auxiliary execution environment, e.g., auxiliary environment  108 , a main memory  112 , and an auxiliary memory  116 , coupled with each other as shown. The auxiliary memory  116  may have a number of access policies relating to the access of content stored in the main memory  112 . These access policies may be maintained/managed by one or more components of the auxiliary environment  108 . 
         [0020]    The auxiliary environment  108  may be securely partitioned from the host environment  104 , and may include, e.g., a service processor, a virtual partition using a virtual machine manager, or an embedded microcontroller. In an embodiment, the auxiliary environment  108  may be configured to execute code independently and securely isolated from the host environment  104 . In some embodiments, the auxiliary environment  108  may be further configured to prevent components of the host environment  104  from performing operations that would alter, modify, read, or otherwise affect the components of the auxiliary environment  108 . In various embodiments, the auxiliary environment  108  may be partitioned from the host environment  104  via a variety of different types of partitions, including an entirely separate hardware partition (e.g., utilizing Active Management Technologies (AMT), “Manageability Engine” (ME), Platform Resource Layer (PRL) using sequestered platform resources, System Management Mode (SMM), and/or other comparable or similar technologies) and/or a virtualized partition (e.g., a virtual machine in a Virtualization Technology (VT) scheme). In various embodiments, a virtualized host may also be used to implement AMT, ME, and PRL technologies (as described in further detail below). 
         [0021]    In an embodiment, the main memory  112  and the auxiliary memory  116  may be sequestered from one another in a manner to provide different levels of access to components operating in the host environment  104  and components operating in the auxiliary environment  108 . For example, in some embodiments components operating in the auxiliary environment  108  may have read-only access to the main memory  112  and may have read-write access to the auxiliary memory  116  to facilitate management of access policies. Furthermore, in some embodiments components operating in the host environment  104  may have read-write access to the main memory  112  and read-only access to the auxiliary memory  116 . This restriction of components operating in the host environment to modify the access policies found in the auxiliary memory  116  may facilitate maintenance of security on the platform  100 . 
         [0022]    It may be noted that the above access levels may refer to generic environmental access levels with the potential of having more particular access policies being applied to particular components operating in each environment. For example, the host environment  104  may include an operating system (OS)  120  for control and/or management of other components including the mediation of information flow between higher-level components, e.g., user apps  124 , and lower-level components, e.g., a loader  128 , a subject component  132 , a memory manager  136 , and/or a target component  140 . In some embodiments, the subject component  132  and the target component  140  may be software components operating in the same privilege level, or architectural ring. In some embodiments the OS  120  may have no access to the auxiliary memory  116 , while certain other components of the host environment  104 , e.g., subject component  132 , may be provided limited access. 
         [0023]    As used herein, the term “component” is intended to refer to programming logic that may be employed to obtain a desired outcome. The term component may be synonymous with “module” and may refer to programming logic that may be embodied in hardware or firmware, or in a collection of software instructions, possibly having entry and exit points, written in a programming language, such as, for example, C++. 
         [0024]    A software component may be compiled and linked into an executable program, or installed in a dynamic link library, or may be written in an interpretive language such as BASIC. It will be appreciated that software components may be callable from other components/modules or from themselves, and/or may be invoked in response to detected events or interrupts. Software instructions may be embedded in firmware, such as an electrically erasable programmable read-only memory (EEPROM), or may be stored on a readable medium such as a magnetic or optical storage device. It will be further appreciated that hardware components may be comprised of connected logic units, such as gates and flip-flops, and/or may be comprised of programmable units, such as programmable gate arrays or processors. In one embodiment, the components described herein are implemented as software modules, but nonetheless may be represented in hardware or firmware. Furthermore, although only a given number of discrete software/hardware components may be illustrated and/or described, such components may nonetheless be represented by additional components or fewer components without departing from the spirit and scope of embodiments of the invention. 
         [0025]    In an embodiment, the loader  128 , the subject component  132 , the memory manager  136 , and/or the target component  140  may be supervisory-level components, e.g., kernel components. In various embodiments, kernel components may be services (e.g., loader, scheduler, memory manager, etc.), extensions/drivers (e.g., for a network card, a universal serial bus (USB) interface, a disk drive, etc.), or a service-driver hybrid (e.g., intrusion detectors to watch execution of code). 
         [0026]    In some embodiments the main memory  112  may organize content stored therein into a number of groups of memory locations. These organizational groups, which may be fixed- and/or variable sized, may facilitate virtual memory management. The groups of memory locations may be pages, segments, or a combination thereof. 
         [0027]    A virtual memory utilizing paging may facilitate the emulation of a large logical/linear address space with a smaller physical memory page. Therefore, the host environment  104  may provide a virtual execution environment in which the components may operate, which may then be mapped into physical pages of the main memory  112 . The OS  120  may maintain page tables to map the logical/linear addresses provided by components of the host environment  104  to physical address of the main memory  112 . More details of the implementation of paging in accordance with embodiments of the present invention may be given below. 
         [0028]    In an embodiment, the loader  128  may receive a load request, e.g., from the OS  120 , to load content into one or more pages of the main memory  112 , e.g., subject pages  144 . The loaded content may include, e.g., data pages, having static content, and/or code pages, having executable content. The subject pages  144  may be used for providing processor instructions to a host processor in the execution of the subject component  132 . The loader  128  may make a request to the memory manager  136  to allocate subject pages  144 . The loader  128  may then load the content into the allocated subject pages  144 . The content, upon execution in the host environment  104  may be manifested as the subject component  132 . 
         [0029]    In an embodiment, the auxiliary environment  108  may include a code location component  148  to identify the location of the subject pages  144  in the main memory  112 . The code location component  148  may use the capability of the auxiliary environment  108  to access the main memory  112  to read and locate the subject pages  144  in the main memory  112 . The code location component  148  may receive images, e.g., complete images or hashes, of the images or specific subject pages  144 , from the host environment  104  and/or a third-party trusted entity, to facilitate their location and/or state verification in the main memory  112 . A comparison, e.g., byte-by-byte or through cryptographic hashes, may be done between the image received and the subject pages  144  from the perspective of the auxiliary environment  108 . In various embodiments, the code location component  148  may search for the location of the subject pages  144  directly in the main memory  112 , e.g., through a direct memory access and/or a messaging system between the auxiliary environment  108  and the host environment  104 . A messaging system, for example, may search for the location of the subject pages  144  by using the memory mapped registers of a host processor of the host environment  104 . A read of the registers of the host processor may take place through a system management interrupt (SMI), for example. 
         [0030]    As shown in  FIG. 1 , the code location component  148  is located in the auxiliary environment  108 ; however, in some embodiments, the code location component  148 , or portions thereof, may be located elsewhere. Furthermore, in some embodiments, the code location component  148  may additionally/alternatively cooperate with components, e.g., agents, in other execution environments. 
         [0031]    In an embodiment utilizing virtualized memory, the location of the subject component  132  may be reported to the code location component  148  as its linear address. The code location component  148  may receive this linear address and access host page tables setup by the host environment  104  to perform a virtual-to-physical address mapping to determine the physical location of the subject page  144  in main memory  112 . In an embodiment, the code location component  148  may optionally fetch additional information from the subject component  132  to verify the location and/or state, e.g., through hashes, relocation fix-ups, etc. In an embodiment, the determination of the location of the subject page  144  may be facilitated by having the subject pages  144  pinned in main memory  112 . 
         [0032]    In an embodiment, the code location component  148  may report the location and/or state of the subject pages  144  to an auxiliary memory manager, e.g., a micro-context manager  152 . The micro-context manager  152  may assign an identifier, or micro-context (uC), to the subject pages  144  and store the assigned uC in the auxiliary memory  116 , e.g., subject-uC  156 . The subject-uC  156  may facilitate storage and subsequent retrieval of various meta-data associated with the subject page  144 . For example, in an embodiment, the subject-uC  156  may include access control policies that apply to the content stored in the subject pages  144  of the main memory  112 . In various embodiments, these access control policies may be referenced by components of the host environment  104  to control various memory accesses to the subject pages  144  and/or by the subject component  132 . 
         [0033]    The various management components of the auxiliary environment  108 , e.g., the code location component  148  and the uC manager  152 , may operate independently from the OS  120  of the host environment. Therefore, management provided by such components may be referred to as OS-agnostic or “out-of-band” (OOB) management. 
         [0034]    In an embodiment, one or more pages, e.g., target pages  160 , storing data relating to the target component  140  may be located and assigned a target-uC  164  in a manner similar to that discussed above relative to the subject page  144 . In an embodiment, the subject component  132  may issue a request to access, e.g., to read/write from/to, content stored in target pages  160 . The processor of the host environment  104  may perform an access control check, to determine whether to grant/deny this request, based at least in part on reference to the subject-uC  156  and/or a target-uC  164  stored in the auxiliary memory  116 . If the access control check fails, e.g., the subject-uC  156  and the target-uC  164  are incompatible, the processor may issue a page fault exception and/or interrupt the uC manager  152 . If the access control check passes, e.g., the subject-uC  156  and the target-uC  164  are compatible, no faults may be issued and the processor may access the requested content. 
         [0035]      FIG. 2  illustrates data structures of the auxiliary memory  116  in accordance with an embodiment of the present invention. In this embodiment, an array  200  may include micro-context numbers, e.g., uC1  204 -uCN  208 , associated with physical pages in the main memory  112 . It may be noted that the correspondence between physical pages and micro-contexts may not be one-to-one, e.g., multiple physical pages may have the same micro-context. The micro-context numbers of the array  200  may, in turn, be associated with a corresponding array  212  of micro-context data. A micro-context data entry, e.g., uCN  216  may include access policy fields for data such as permissions  220  (e.g., readable/nonreadable, writeable/nonwriteable, hidden/visible, etc.) and/or relational access data  224  (e.g., other micro-contexts that may access this micro-context if marked readable, etc.). 
         [0036]    In some embodiments the relational access data  224  may facilitate a number of different components having access to the same pages in the main memory  112 . This may be achieved by storing one or more micro-contexts in addition to the primary micro-context associated with the particular page. Such a page may then be accessed by any of the micro-contexts listing in its associated access control data structure in the auxiliary memory  116 . This shared access may allow privileged code to be chained together in a chain-of-trust model. For example, if a layered software component A exchanges data with another layered software component B, the auxiliary environment  108  may assign micro-contexts to the layered software components and setup access control policies such that the data pages for A are also marked with a shared micro-context for B-uC. Therefore, when B-uC code accesses A&#39;s data, the accesses may be allowed. 
         [0037]    In some embodiments, this type of shared access may provide some level of assurance that only packets that traverse a firewall or VPN intermediate driver are delivered to the device driver. Likewise, it may provide some level of assurance that only the device driver can access the frame buffer data segments and so on. This may prevent circumvention of security software by network traffic leaving/entering the system. 
         [0038]    In an embodiment uCN  216  may also include fields for data to facilitate context switches, e.g., component entry point data  228  and/or stack state data  232 . Utilization of the information stored in these fields may be further described below in accordance with some embodiments of the present invention. 
         [0039]      FIG. 3  illustrates a platform  300  having dual processors to provide dual execution environments in accordance with an embodiment of the present invention. The platform  300  may have a host processor  304  to execute components within the host environment  104 , and a service processor  308  to execute components within the auxiliary environment  108  described and discussed with reference to  FIG. 1 . Operational phases, noted herein by numerals in parentheses, may refer to host operations illustrated in  FIG. 4  and/or auxiliary operations illustrated in  FIG. 5 . 
         [0040]    Each processor may have associated resources on the platform  300  and may share one or more other resources. Thus, as illustrated in this example, host processor  304  and dedicated processor  308  may each have portions of memory dedicated to them, e.g., main memory  112  and auxiliary memory  116 , respectively, and may share other resources, e.g., a network interface  310 , to communicatively couple the device to a network. 
         [0041]    In various embodiments, a variety of other dedicated and/or shared resources may be included in the platform  300 . For example, in an embodiment, the host processor  304  may be communicatively coupled to a peripheral storage device, e.g., disk drive  314 , which may include a digital versatile disk drive (DVD), a compact disk (CD) drive, a floppy disk drive, etc. 
         [0042]    In an embodiment, the OS  120  may configure and load a page table  312  with the virtual-to-physical mapping of one or more components to be run on the host processor  304 , e.g., subject component  132  ( 404 ). The page table  312  may have page entries  320 , offsets  324 , and/or flags  328  to facilitate this mapping. The page table  312 , or parts thereof, may be stored in a processor cache, e.g., a translation lookaside buffer (TLB)  332 . 
         [0043]    The host processor  304  may also use its read-capability of the auxiliary memory  116  to access and load the subject-uC  156  into the TLB  332  ( 408 ). 
         [0044]    The host processor  304  may utilize the page table  312  for subsequent accesses to the subject pages  144  ( 412 ), pursuant to access control policies associated with the subject-uC  156 . Execution instructions  336 , of the subject component  132 , may be processed by the host processor  304  upon a successful access and loading of the subject pages  144 . 
         [0045]    The host processor  304  may record a micro-context of the page from where the host processor  304  is executing code, e.g., subject-uC  156 , in a uC-register  340  ( 416 ). 
         [0046]    In an embodiment, the code location component  148 , operating in the auxiliary environment  108 , e.g., by being executed by the service processor  308 , may determine that the subject component  132  is executing in the host environment  104  ( 504 ). In an embodiment, the code location component  148  may determine which component is executing in the host environment  104  by reference to the uC-register  340 . In an embodiment, service processor  308  may be prevented from accessing the register directly. Therefore, in this embodiment an SMI may facilitate the provision on this information to the service processor  308 . An SMI may be issued by a system management mode (SMM) component operating in the host environment  104 , the auxiliary environment  108 , or another execution environment. An SMI may cause the host processor  304  to enter the SMM by swapping out the execution instructions  332  for processing instructions related to an interrupt service routine. The host processor  304  may provide data including the state of the uC-register  340 , e.g., the micro-context of the code that was executing prior to the interrupt, to an SMM handler. The SMM handler may provide the state of the uC-register  340  to the service processor  308  via main memory  112 , for example. 
         [0047]    The code location component  148  may locate the subject pages  144  in main memory  112  and verify the state of the subject pages  144  ( 508 ) as described above with reference to  FIG. 1 . The uC manager  152  may then associate a micro-context with the subject page  144  and save the associated micro-context in the auxiliary memory  116  based at least in part on said location and verification of the subject pages  144  ( 512 ). 
         [0048]    In an embodiment, the subject pages  144  may include a data page, or reference to a data page, which may be added to the page table structure for the subject component  132 . This data page may be assigned a micro-context of 0, e.g., not protected, by default. If the subject component  132  intends for the data page to be assigned the same micro-context as the subject component  132 , the subject component  132  may make an assignment request to the service processor  308 . In an embodiment, this request may be made via an SMI handler. The service processor  308  may assign the data page with the requested micro-context if it is determined that a number of assignment preconditions are met. These assignment preconditions may be met if, e.g., the subject component  132  has the same micro-context as it is requesting be assigned to the data page, and the data page does not already have another micro-context assigned to it. 
         [0049]    In an embodiment, a request to remove, or de-assign, a micro-context assignment from a data page, e.g., reassign a protected data page with an unprotected micro-context, may be handled in a similar way. For example, a de-assignment request may be granted by the service processor  308  if a number of de-assignment preconditions are met. These de-assignment preconditions may be met if, e.g., the page was added to the micro-context and/or the data page has the same micro-context as the requestor. 
         [0050]    In an embodiment, if the host processor  304  is to access a mapping to a component&#39;s pages, along with any associated micro-context, from the TLB  336 , the host processor  304  may additionally access the auxiliary memory  116  to determine if any updates to the micro-context have occurred. In various embodiments, updates to the micro-contexts may also be periodically provided to the TLB  336 . Provision of the periodic updates may be as a result from a specific request from the host processor  304  and/or may be pushed into the TLB  336 . 
         [0051]      FIG. 6  illustrates an access operation from the host environment  104  in accordance with an embodiment of the present invention. In an embodiment, the execution instructions  332  may include instructions for the host processor  304  to access content stored in the target pages  160  ( 604 ). When the host processor  304  is in a protected mode, the processing instructions may access memory using logical/virtual addresses. An initial lookup may be performed in the TLB  332  to determine if a mapping to the data sought and an associated micro-context are stored therein ( 608 ). If a mapping to the corresponding physical address of the target pages  160  and associated micro-context are found, the host processor  304  may perform uC access control check ( 612 ). If no uC access violation is present, the host processor  304  may access the target data based on the physical address from the TLB  332  ( 616 ). If a uC access violation does result from the access operation, an exception may be raised, e.g., a processor Page-Fault exception ( 620 ). In an embodiment, these exceptions may be handled by firmware to ensure appropriate alerts and/or events are logged. However, in other embodiments alerts and/or events may be handled by hardware and/or software implementations. 
         [0052]    In an embodiment, for instructions that access data in the main memory  112 , the host processor  304  may compare the micro-contexts of the executing code with the micro-context of the page where the address specified in the instruction lie for compatibility. In an embodiment, accesses across micro-contexts may be generally disallowed, with the exception for shared or remapped pages where a list of micro-contexts may be associated with the same physical page. 
         [0053]    If the virtual-to-physical address mapping is not found in the TLB  332 , the host processor  304  may perform a page walk and cache the mapping to the target pages  160  in the TLB  332  ( 624 ). The host processor  304  may additionally cache the target uC  164 , from the auxiliary memory  116 , in the TLB  332  ( 628 ). The host processor may check for uC access violation ( 612 ). 
         [0054]      FIG. 7  illustrates a context-switching operation in accordance with an embodiment of the present invention. In some embodiments, a number of processes may share the computational resources of the host processor  304 . This sharing of resources may be provided through context switches. Context switches may be precipitated by a switching event  704 . An implicit context switch may have a switching event such as an interrupt. An explicit context switch may have a switching event such as a CALL opcode issued from the executing component explicitly calling another component. 
         [0055]    As discussed herein, a context switch may involve an exiting component, e.g., the component executing prior to context switch, and an entering component, e.g., the component executing following the context switch. 
         [0056]    At the switching event, the host processor may determine whether the exiting component is protected, e.g., is the exiting component associated with a non-zero uC ( 708 ). If the exiting component is protected, the host processor  304  may perform a micro-context save interrupt by saving an entry point, which may be the physical address where the last instruction was fetched from when the context switch occurred, and data for subsequent verification of the stack-state ( 712 ). The entry-point and the stack-state verification data may be saved in the exiting component&#39;s micro-context associated space in the auxiliary memory  116 . 
         [0057]    In various embodiments, data for stack-state verification may include a copy of the entire stack state or an integrity check value (ICV) calculation. An ICV may be calculated on the in parameters of a stack frame by setting the out parameters to default values. Likewise, an ICV may be calculated on the out parameters by setting the in parameters to default values. An ICV calculation and/or verification may be done by the host processor  304  using a key provisioned by the service processor  308  via an SMI, for example. 
         [0058]    Following the micro-context save interrupt, the host processor  304  may switch from the exiting component to the entering component ( 716 ). 
         [0059]    If it is determined that the exiting component is not protected, e.g., has a micro-context of zero, the components may be switched out without a micro-context save interrupt. 
         [0060]      FIG. 8  illustrates a context switching operation on an entering component, in accordance with an embodiment of the present invention. In this embodiment, a context switch from an exiting component to an entering component may occur ( 804 ). A determination may be made as to whether the entering component is protected ( 808 ). If the entering component is protected, the host processor  304  may perform a micro-context recover interrupt ( 812 ). A micro-context recover interrupt may include accessing the stack-state verification data and the entry point location from the entering component&#39;s micro-context. The host processor  304  may verify the state of the stack and, if the stack is verified, resume processing opcodes from the stored entry point location ( 816 ). Verification of the stack-state from data stored in protected memory may provide some level of assurance that the stack has not been modified. 
         [0061]    In some embodiments, the host processor  304  may look ahead in the pipeline by an instruction, e.g., during decode, to determine that the next instruction belongs to a micro-context other than the current one to facilitate the timely issuance of a micro-context save/restore interrupt. 
         [0062]    While the above embodiments, refer generically to implicit and explicit context switches, some embodiments may have a particular rule set governing each type of context switch. For example, in the anticipation of an explicit context switch, entry-point opcodes may be added to verify that the entering component is being executed from special entry points identified in the component&#39;s code. If an entry-point opcode is being decoded by the entering component in response to a CALL opcode from the exiting component, no more checks may be needed. If, however, in response to a CALL opcode from exiting component, the next opcode is not an entry-point opcode, then an exception may be raised. This may be particularly useful in a situation where the exiting component is unprotected and the entering component is protected. 
         [0063]    In some embodiments fixed entry points may be stored with micro-contexts to allow controlled flow from one uC to another. For example, a component of a first uC may jump into or call a component of a second uC at one of these entry points. At these expected entry points, proper control flow may be achieved. A policy for the component may define where the proper entry points are located. Controlled flow transitions from one component to another at a proper entry point may not generate an exception or interrupt a uC manager. 
         [0064]    In some embodiments, fixed entry points may also be referred to as “static entry points” while entry points saved at various switching events, e.g., those saved as a result of a uC save interrupt, may also be referred to as “dynamic entry points.” 
         [0065]      FIG. 9  illustrates a platform  900  utilizing virtualization to provide dual execution environments in accordance with an embodiment of the present invention. The platform  900  may include only a single processor  904  but a virtual machine monitor (VMM)  908  on the device may present multiple abstractions and/or views of the device, such that the underlying hardware of the platform  900  appears as one or more independently operating virtual machines (VMs), e.g., a host VM  912  and an auxiliary VM  916  to provide the host environment  104  and the auxiliary environment  108 , respectively. The VMM  908  may be implemented in software (e.g., as a stand-alone program and/or a component of a host operating system), hardware, firmware and/or any combination thereof. The VMM  908  may manage allocation of resources on the platform  900  and perform context switching as necessary to cycle between the host VM  912  and the auxiliary VM  916  according to a round-robin or other predetermined scheme. Although only processor  904  is illustrated, embodiments of the present invention are not limited to only one processor. In various embodiments, multiple processors may also be utilized within a virtualized environment. For example, if the platform  900  includes two processors the auxiliary VM  916  may be assigned a dedicated processor while the host VM  912  (and other host VMs) may share the resources of a host processor. 
         [0066]    While the platform  900  shows two VMs, e.g., host VM  912  and auxiliary VM  916 , other embodiments may employ any number of VMs. VMs may function as self-contained partitions respectively, running their own components hosted by VMM  908 , illustrated as host components  920  and auxiliary components  924 . 
         [0067]    The host components  920  and auxiliary components  924  may each operate as if the were running on a dedicated computer rather than a virtual machine. That is, host components  920  and auxiliary components  924  may each expect to control various events and have access to hardware resources on the platform  900 , e.g., a wireless network interface card  928 . 
         [0068]    A physical hardware partition with a dedicated processor (as illustrated in  FIG. 3 , for example) may provide a higher level of security than a virtualized partition (as illustrated in  FIG. 9 , for example), but embodiments of the invention may be practiced in either environment and/or a combination of these environments to provide varying levels of security. 
         [0069]    Embodiments of the present invention shown and described above may facilitate association and management of targeted access policies from an auxiliary environment with respect to the physical pages found in main memory. Although the present invention has been described in terms of the above-illustrated embodiments, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those with skill in the art will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This description is intended to be regarded as illustrative instead of restrictive on embodiments of the present invention.