Abstract:
A power Schottky rectifier device having a plurality of first trenches filled in with an un-doped polycrystalline silicon layer and each first trenches also has a p-region beneath the bottom of said first trenches to block out reverse current while a reverse biased is applied and to reduce minority carrier while forward biased is applied. Thus, the power Schottky rectifier device can provide first fast switch speed. The power Schottky rectifier device is formed with termination region at an outer portion of the substrate. The manufacture method is also provided.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a semiconductor process, specifically, to a Schottky barrier power rectifier having buried p-region beneath un-doped polycrystalline trench structure to reduce reverse leakage current, and improve breakdown voltage, and reduce minority current while forward biased, which results in a high switching speed.  
       BACKGROUND OF THE INVENTION  
       [0002]     Schottky diode is an important power device and used extensively as output rectifiers in switching-mode power supplies and in other high-speed power switching applications, such as motor drives, switching of communication device, industry automation and electronic automation and so on. The power devices are usually required characteristics of carrying large forward current, high reverse-biased blocking voltage, such as above 100 volt, and minimizing the reverse-biased leakage current.  
         [0003]     A number of power rectifiers have been used to provide high current and reverse blocking characteristics. An exemplary method to form a Schottky barrier diode is disclosed by Chang et al in U.S. Pat. No. 6,404,033. The processes are shown in  FIG. 1A  to  FIG. 1C . Referring to  FIG. 1A , a semiconductor substrate having an n+ doped layer  10  and an n− drift layer  12  extended to a first surface  13  is prepared. A field oxide layer  14  is then formed on the first surface  13 . Afterward, the field oxide layer  14  is patterned to define positions of guard ring  22  at the termination region. Guard ring regions  22  are then buried into n− drift layer  12  by double implants with B+ and BF 2 +as conductive impurities. Thereafter, a thermal anneal process is then performed to drive in and activate the impurities. Thereafter, a second photoresist pattern  24  is then coated on the resultant surface to define an anode region. The results are shown in  FIG. 1B .  
         [0004]     Referring to  FIG. 1C , a wet etch is then performed to remove those exposed field oxide layer  14 . After stripping away the photoresist pattern  24 , another photoresist pattern  28  having openings is formed on the resultant surface to define trenches at the active region. An etching step is then performed to recess the drift layer  12  using the photoresist pattern  28  as a mask. Another B+ or BF 2 + ion implant is then carried out to form p type region  30  buried into trench bottom.  
         [0005]     Referring to  FIG. 1D , the photoresist pattern  28  is removed. Then, a Schottky barrier metal layer  32  is formed on the resultant surface. Thereafter, a top metal layer formation is followed. A forth photoresist (not shown) and an etch steps are then performed to define the top electrode  36 . After the layers formed on the backside surface during forgoing step are removed, a metal layer  60  is then formed, which is used as a bottom electrode  34 .  
         [0006]     Although the Schottky barrier rectifier disclosed in U.S. Pat. No. 6,404,033 having pluralities of trenches to increase the surface area thereto increases forward current capacity and having buried p layers  30  at the bottom of the trenches to form p-n junction regions to increase breakdown voltage. However, it requires a complex processes at least four to six masks. And also, the buried p-n junctions will introduce many minority carriers when device is under forward bias, which will result in a larger reverse recovery time than the typical Schottky barrier rectifier. The object of the present method is to improve the breakdown voltage and enhance the forward current capacity and simplify the manufacturing processes.  
       SUMMARY OF THE INVENTION  
       [0007]     A power Schottky rectifier device and method of making the same are disclosed. The method of forming the Schottky barrier rectifier comprises the following steps: firstly, an n+ doped substrate formed with an n− drift layer, and an ONO hard mask layer is provided. Subsequently, the n− drift layer is recessed to form a plurality of first trenches and a pair of termination trenches at an outer portion of the substrate by the hard mask. A silicon layer is then deposited till the first trenches are filled in and over the uppermost surface of the hard mask to a predetermined thickness. A thermal oxidation is then carried out to oxidize the silicon layer outside the first trenches.  
         [0008]     The active region is then defined by using the photolithography and dry etching processes. A metallization process is performed to form a silicide layer on the active region.  
         [0009]     In the first preferred embodiment, the active region is an area includes all but the outermost one of the first trenches at both terminals along a cross-sectional view. Next, a top metal layer is formed on all areas. The top metal layer is then patterned to defined anode electrode. The anode electrode covers all of the first trenches  135  but ends before termination trenches  135 A. Then, the backside metallization is formed to serve as cathode electrode.  
         [0010]     In the second preferred embodiment, the processes are similar to the first preferred embodiment but the active region includes all of the first trenches from a cross-sectional view. Next, a top metal layer is formed on all areas. The top metal layer is then patterned to defined anode electrode. The anode electrode covers all of the first trenches and a portion of termination trenches. Then, the backside metallization is formed to serve as cathode electrode.  
         [0011]     In the third preferred embodiment, the processes include using a hard mask defining first trenches and termination trenches and performing an ion implant to form p-regions. The hard mask is then removed. An anneal process to form a thermal oxide lining is then followed. Thereafter, a silicon layer is deposited to fill in the first trenches and over the uppermost surface of the thermal oxide lining to a predetermined thickness. A thermal oxidation is then carried out to oxidize the silicon layer out of the first trenches. Then the active region defined, the metallization process, and the anode electrode formation, cathode electrode formation are the same as the first preferred embodiment.  
         [0012]     In the fourth preferred embodiment, the processes are similar to the third preferred embodiment but the active region includes all of the first trenches from a cross-sectional view. Then the metallization process, and the anode electrode formation, cathode electrode formation are the same as the second preferred embodiment. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0014]      FIGS. 1A  to  1 D show steps of forming a conventional Schottky barrier diode with a plurality of trenches and p-region at the bottom of each trench and p+ guard ring structure at the termination in accordance with prior art.  
         [0015]      FIG. 2A  is a cross-sectional view of forming a hard mask on an n− epi layer in accordance with the present invention.  
         [0016]      FIG. 2B  is a cross-sectional view of patterning the n− epi layer to form first trenches and termination trenches and then performing an ion implant to form p-regions in accordance with the present invention.  
         [0017]      FIG. 2C  is a cross-sectional view of forming a silicon layer in accordance with the present invention.  
         [0018]      FIG. 2D  is a cross-sectional view of performing a thermal oxidation to oxidize the silicon layer out of the first trenches in accordance with the present invention.  
         [0019]      FIG. 2E  is a cross-sectional view of defining an active region in accordance with the present invention.  
         [0020]      FIG. 2F  is a cross-sectional view of forming a barrier metal layer and then thermal anneal to form silicide in accordance with the present invention.  
         [0021]      FIG. 2G  is a cross-sectional view of Schottky diode in accordance with the first preferred embodiment of the present invention.  
         [0022]      FIG. 2H  is a cross-sectional view of Schottky diode in accordance with the second preferred embodiment of the present invention.  
         [0023]      FIG. 3A  is a cross-sectional view of patterning the n− epi layer to form first trenches and termination trenches and then performing an ion implant to form p-regions by using an oxide layer as a hard mask in accordance with the present invention.  
         [0024]      FIG. 3B  is a cross-sectional view of removing the hard mask and then forming a thermal oxide lining in accordance with the present invention.  
         [0025]      FIG. 3C  is a cross-sectional view of forming a silicon layer in accordance with the present invention.  
         [0026]      FIG. 3D  is a cross-sectional view of performing a thermal oxidation to oxidize the silicon layer out of the first trenches in accordance with the present invention.  
         [0027]      FIG. 3E  is a cross-sectional view of defining an active region in accordance with the present invention.  
         [0028]      FIG. 3F  is a cross-sectional view of forming a barrier metal layer and then thermal anneal to form silicide in accordance with the present invention.  
         [0029]      FIG. 3G  is a cross-sectional view of Schottky diode in accordance with the first preferred embodiment of the present invention.  
         [0030]      FIG. 3F  is a cross-sectional view of Schottky diode in accordance with the second preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0031]     As depicted in the forgoing background of the invention, to form a power rectifier device and its termination structure using the conventional technique requires at least four to six photo masks. The present invention can simplify the processes by using only three photo masks. The detailed descriptions are as follows:  
         [0032]     Firstly, an n+ doped substrate  100  formed with an n− drift layer  101  is provided. To define trenches, referring to  FIG. 2A , an ONO stack layer formed of a pad oxide layer  110 , a nitride layer  120 , and a thick oxide layer  130  is formed on the n− drift layer  101 . Preferably, the layers  110 ,  120 , and  130 , are, respectively, between about 5 to 100 nm, 50-300 nm, and 0 to 1000 nm in thickness. A lithographic technique and etching steps are then performed to pattern the ONO stack layer so as to define a hard mask having opening  135 , and  135 A.  
         [0033]     Referring to  FIG. 2B , an etching step is then performed to form first trenches  135 , and termination trenches  135 A which are recessed into the ONO stack layer  110 ,  120 , and  130  and the n− drift layer  101 . The first trenches  135  are located at a core portion of the substrate and the termination trenches  135 A are located at an outermost portion of the substrate. After that a p-type impurity implantation process, for example, is then carried out to implant B+ or BF 2 + ions into the n− epi layer  101  to form a p regions  140 , which are beneath the bottoms of the trenches  135  and  135 A. The dosage and the implant energy are about 5×10 10 -5×10 14 /cm 2  and 10-1000 keV for boron ions and about 5×10 11 -5×10 15 /cm 2  and 30-300 keV for BF 2 + ions.  
         [0034]     Turning to  FIG. 2C , an undoped polycrystalline, or amorphous silicon  145  is then deposited by LPCVD to fill the first trenches  130  and the termination trenches  135 A until the polycrystalline (amorphous) silicon  145  is completely filled in the first trenches  130  and over the lever of the remnant oxide layer  130  to a predetermined thickness.  
         [0035]     Thereafter, referring to  FIG. 2D , a thermal oxidation process is then performed to conduct the polycrystalline (amorphous) silicon  145  which is outside the first trenches into a thermal oxide layer  150 . In the meantime, the ions in the p regions  140  are driven in both laterally and longitudinally into n− epi layer  101  and results in extending the p regions  140 . The amorphous silicon inside the first trenches  135  is transformed to polycrystalline silicon.  
         [0036]     Turning to  FIG. 2E , a photoresist pattern  155  is coated on the thermal oxide layer  150  to define an active region and a termination region. In the first preferred embodiment, the active region begins from the interval between the first and the second trench to the interval between the third and the fourth trench. A dry or wet etching is then performed to etch successively the exposed thermal oxide layer  150 , and the ONO layer  130 ,  120 , and  110  until the polycrystalline silicon layer  145  and the n− drift layer  101  are exposed. Worth to note, the total number of first trenches in context is four which is just for illustrating conveniently. In practice, the numbers of the first trenches are more. Thus the active region will begin from the interval between the first and the second trench to the interval between the n−1 and the n of first trenches for n&gt;4.  
         [0037]     Referring to  FIG. 2F , after stripping the photoresist pattern  155 , a barrier metal layer  160  is then deposited on all areas. The material of the barrier metal, for example, can be selected from Al, AlCu, AlSiCu, Ti, Ni, Cr, Mo, Pt, Zr, W etc. Subsequently, an anneal step is then performed to form metal silicide layer  165  at the active region by reacting the metal layer and the silicon layer. The un-reacted metal layer  160  is then optionally removed by selectively etching.  
         [0038]     Referring to  FIG. 2G , a top metal layer is then coated on all areas. The material of the top metal layer  180  is chosen, for example, from Al, AlCu, AlSiCu, Ti/Ni/Ag etc. An anode electrode  180  defining step by patterning is then conducted to etch the undesired portion of the top metal layer  180  and the metal layer  160  if the un-reacted metal layer  160  is not removed previously. The anode electrode  180  is formed to contact the metal silicide layer  165  of the active region and extended to cover all of the first trenches  135  but terminated before termination trenches  135 A. After backside material milling by a chemical/mechanical polish to expose and thin the n+ substrate  100 , a backside metal layer  190  is formed thereafter as a cathode electrode.  
         [0039]     Alternatively, the active region can be appropriate expanded, as is shown in the second preferred embodiment. For example, the active region includes the region over whole first trenches, as is shown in FIG.  2 H. The processes are similar to those depictions in  FIG. 2E  to  FIG. 2F  of the first embodiment. In the situation, the anode electrode  180  at the active region is extended to cover a portion of termination trenches  135 A.  
         [0040]     The processes of the third preferred embodiment are shown in  FIG. 3A  to  FIG. 3E . Referring to  FIG. 3A , the substrate for the Schottky diode is the same material as the first preferred embodiment used, which includes an n+ doped substrate  100  formed with an n− drift layer  101 . To define trenches, a thick oxide layer  110  is then formed on the n− drift layer  101 , and then patterned to form opening  135  and  135 A by lithographic technique and etching steps. Subsequently, an etching step using the oxide layer  110  as a hard mask is continuous to form the first trenches  135  at a core region of the substrate and termination trenches  135 A at border region of the substrate. After that a p-type impurity implantation process, for example, is then carried out to implant B+ or BF 2 + ions into the n− epi layer  101  to form a p regions  140 , which are beneath the bottoms of the trenches  135  and  135 A.  
         [0041]     Referring to  FIG. 3B , the oxide layer  110  remnant is removed and then an oxidation process to form oxide lining  125  is performed to recover all damage during above etching process. In the meantime, the p regions  140  are extended and ions are activated. Turning to  FIG. 3C , an undoped polycrystalline or amorphous silicon  145  is then deposited by LPCVD to fill the first trenches  130  and the termination trenches  135 A until the polycrystalline (amorphous) silicon  145  is completely filled in the first trenches  130  and over the lever of the remnant oxide layer  130  to a predetermined thickness.  
         [0042]     Thereafter, referring to  FIG. 3D , a thermal oxidation process is then performed to conduct the polycrystalline (amorphous) silicon  145  outside the first trenches  135  into a thermal oxide layer  150 . The p regions  140  are further extended and the amorphous silicon inside the first trenches  135  is transformed to polycrystalline silicon.  
         [0043]     Turning to  FIG. 3E , a photoresist pattern  155  is coated on the thermal oxide layer  150  to define active region. The active region begins from the interval between the first and the second trench to the interval between the third and the fourth trench. A dry or wet etching is then performed to etch successively the exposed thermal oxide layer  150  and the oxide layer  110  until the polycrystalline silicon layer  145  and the n− epi-layer  101  are exposed.  
         [0044]     Referring to  FIG. 3F , after stripping the photoresist pattern  155 , a barrier metal layer  160  is then deposited on all areas. The material of the barrier metal, for example, can be selected from Al, AlCu, AlSiCu, Ti, Ni, Cr, Mo, Pt, Zr, and W etc. Subsequently, an anneal step is then performed to form a silicide layer  165  at the active region. The un-reacted metal layer  160  is then optionally removed by selectively etching.  
         [0045]     Still referring to  FIG. 3F , a top metal layer is then coated on all areas. An anode electrode  180  defining step by patterning is then conducted to etch the undesired portion of the top metal layer  180  and the metal layer  160  if it exists. The anode electrode  180  is formed to contact the metal silicide layer  165  of the active region and extended to cover all of the first trenches  135  but ended before termination trenches  135 A. After backside material milling by a chemical/mechanical polish to expose and thin the n+ substrate  100 , a backside metal layer  190  is formed thereafter as a cathode electrode.  
         [0046]     The fourth preferred embodiment is similar to the second preferred embodiment having the active region over all of the first trenches  135  and the anode electrode  180  is formed on the metal silicide layer and extended to cover a portion of the termination trenches  135 A.  
         [0047]     The benefits of the preferred embodiment:  
         [0048]     The Schottky diode according the present invention is a trench-type, which generally has higher breakdown voltage than conventional planar-type Schottky diode.  
         [0049]     The undoped polycrystalline silicon filled in the first trenches provides high resistance, result in, lower forward minority carrier and reverse recovery time. Consequently, the Schottky diode provides high speed switch performance.  
         [0050]     As is understood by a person skilled in the art, the foregoing preferred embodiment of the present invention is an illustration of the present invention rather than limiting thereon. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.