Abstract:
A ping-pong amplifier employs auto-zeroing and chopping to simultaneously achieve low offset voltage and low frequency noise, as well as low energy at the chopping frequency. The ping-pong amplifier includes respective nulling amplifiers for each of its gain amplifiers, which auto-zero each gain amplifier. In addition, switches are included which allow the inputs and outputs of the active gain amplifier to be chopped. Thus, while one gain amplifier is being auto-zeroed, the other gain amplifier amplifies the input signal and its inputs and outputs are chopped. One of the described embodiments includes circuitry which reduces switching transients that might otherwise appear in the amplifier&#39;s output by ensuring that the common-mode output voltage of each gain amplifier is kept equal to a common-mode reference voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the field of ping-pong amplifiers, and particularly to techniques for reducing low frequency noise and offset voltage errors for such amplifiers. 
     2. Description of the Related Art 
     Ping-pong amplifiers are well known and widely used due to their low input offset voltages. A schematic diagram of a basic ping-pong amplifier  10  is shown in FIG.  1 . Two gain amplifiers A 1  and A 2 , each of which has differential inputs and outputs, receive a differential input signal made up of signals INP and INN. The ping-pong amplifier also typically includes an output amplifier A 0 , which is connectable to the outputs of A 1  via a pair of switches S 1  and S 2 , or to the outputs of A 2  via a pair of switches S 3  and S 4 . 
     A pair of fully differential nulling amplifiers A 3  and A 4  are used to auto-zero A 1  and A 2 , respectively; the inputs of A 3  and A 4  are connected to the outputs of A 1  and A 2  via pairs of switches S 5 /S 6 , and S 7 /S 8 . A pair of memory capacitors C 1  and C 2  are connected to the inputs of A 3 , and capacitors C 3  and C 4  are connected to A 4 &#39;s inputs. A switch S 9  is connected between the inputs of A 1 , and a switch S 10  is connected between the inputs of A 2 . A switch S 11  is connected between the differential input signal and one of A 1 &#39;s inputs, and a switch S 12  is connected between the differential input signal and one of A 2 &#39;s inputs. 
     The switches are controlled with a control circuit (not shown), which operates them in accordance with the timing diagram shown in FIG. 1 a.  The ping-pong amplifier has a two-phase timing cycle. During the first phase (φ1), switches S 5 , S 6  and S 9  are closed, such that amplifier A 1  is auto-zeroed by the output currents of nulling amplifier A 3 , with the error signals stored on memory capacitors C 1  and C 2 . Switches S 3 , S 4  and S 12  are also closed, allowing the differential input signal to be amplified by A 2  followed by A 0 . The roles are reversed during the second phase (φ2): switches S 7 , S 8  and S 10  are closed such that A 2  is auto-zeroed by A 4  (with the error signals stored on memory capacitors C 3  and C 4 ), and switches S 1 , S 2  and S 11  are closed such that the input signal is amplified by A 1  followed by A 0 . 
     Auto-zeroing is effective in reducing offset voltage and  1 /f noise. However, the technique suffers from aliasing of wideband noise into the frequency range between DC and the auto-zeroing frequency. Because of this, the low frequency noise spectral density of a conventional auto-zeroed amplifier is several times higher than the thermal noise of a conventional CMOS op amp. 
     Some amplifiers seek to reduce offset voltage and  1 /f noise by “chopping” the input and output of the amplifier; i.e., modulating a low frequency input signal up to near a chopping frequency, where it is amplified and modulated back down to the original frequency. This technique does not suffer from wideband noise aliasing. However, chopping also modulates the offset voltage up to the chopping frequency, resulting in a large energy at the chopping frequency. This energy limits the usable bandwidth, and often requires filtering. 
     SUMMARY OF THE INVENTION 
     A ping-pong amplifier and method are presented which overcome the problems noted above. The invention employs auto-zeroing and chopping to simultaneously achieve low offset voltage and low low frequency noise, as well as low energy at the chopping frequency. 
     The novel ping-pong amplifier includes respective nulling amplifiers for each of its gain amplifiers, which auto-zero each gain amplifier. In addition, switches are included which allow the differential inputs and outputs of the gain amplifiers to be chopped. Thus, while one gain amplifier is being auto-zeroed, the other gain amplifier amplifies the input signal while its inputs and outputs are chopped. 
     One of the described embodiments includes circuitry which reduces switching transients that might otherwise appear in the amplifier&#39;s output. Here, each of gain amplifiers A 1  and A 2  includes a common-mode reference voltage input CMR connected to receive a common-mode reference voltage VCMR, and a common-mode feedback circuit; VCMR is typically set to a value between the amplifier&#39;s power rails so that the amplifier may have a high gain. The common-mode feedback circuit sets the amplifier&#39;s common-mode output voltage —given by the sum of its differential outputs divided by 2—so that each of its outputs is nominally set to VCMR when the differential output voltage is zero. The ping-pong amplifier includes an error amplifier, which has one input connected to common-mode reference voltage VCMR, its other input switchably connected to the common-mode output of one of the two gain amplifiers A 1  and A 2 , and an output which is switchably connected to the CMR inputs of A 1  and A 2 . Respective memory capacitors are connected to the two CMR inputs. In operation, the error amplifier&#39;s input is periodically connected to the common-mode output of A 1 , and its output is connected to A 1 &#39;s CMR input. This arrangement forms a closed-loop which forces A 1 &#39;s common-mode output voltage (referred to herein as “VCMR 1 ”) to be equal to VCMR; the error amplifier&#39;s output voltage is stored on the memory capacitor connected to A 1 &#39;s CMR input. Similarly, the error amplifier&#39;s input and output are periodically connected to A 2 &#39;s common-mode output and CMR input, respectively, to force A 2 &#39;s common-mode output voltage (referred to herein as “VCMR2”) to be equal to VCMR, with the error amplifier&#39;s output voltage stored on the memory capacitor connected to the A 2 &#39;s CMR input. The voltages stored on the memory capacitors continuously adjust the common-mode output voltages so that VCMR1 and VCMR2 are held equal to VCMR. Keeping VCMR1=VCMR2=VCMR ensures that transients due to mismatch in the common-mode feedback circuit are largely reduced. 
     Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram and timing diagram for a prior art ping-pong amplifier. 
     FIG. 2 a  is a schematic diagram of a ping-pong amplifier in accordance with the present invention. 
     FIG. 2 b  is a timing diagram illustrating the operation of the ping-pong amplifier of FIG. 2 a.    
     FIGS. 3 a-   3   g  are other possible input switch arrangements for a ping-pong amplifier in accordance with the present invention. 
     FIGS. 4 a-   4   e  are other possible timing diagrams for the ping-pong amplifier of FIG. 2 a.    
     FIG. 5 a  is a schematic diagram of an embodiment of a ping-pong amplifier in accordance with the present invention which includes circuitry that reduces switching transients. 
     FIGS. 5 b-   5   e  are possible timing diagrams for the ping-pong amplifier of FIG. 5 a.   
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A schematic diagram of a ping-pong amplifier which illustrates the principles of the invention is shown in FIG. 2 a.  The ping-pong amplifier receives a differential input signal comprising positive and negative lines INP and INN. A pair of fully differential gain amplifiers A 1  and A 2  each receive the differential input signal via an array of switches (discussed below). The differential outputs of A 1  are connected to a fully differential nulling amplifier A 3  via a pair of switches S 1  and S 2 , and the outputs of A 2  are connected to a fully differential nulling amplifier A 4  via a pair of switches S 3  and S 4 . A pair of memory capacitors CM 1  and CM 2  are connected to A 3 &#39;s non-inverting and inverting inputs, respectively, and A 3 &#39;s non-inverting and inverting outputs are connected to the inverting and non-inverting outputs of A 1 , respectively. Similarly, a pair of memory capacitors CM 3  and CM 4  are connected to A 4 &#39;s non-inverting and inverting inputs, respectively, and A 4 &#39;s non-inverting and inverting outputs are connected to the inverting and non-inverting outputs of A 2 , respectively. 
     The ping-pong amplifier produces a differential output signal comprising positive and negative lines OUTP and OUTN. A 1 &#39;s non-inverting and inverting outputs can be connected to OUTP and OUTN, respectively, via a pair of switches S 5  and S 6 , and can be connected to OUTN and OUTP, respectively, via a pair of switches S 7  and S 8 . Similarly, A 2 &#39;s non-inverting and inverting outputs can be connected to OUTP and OUTN, respectively, via a pair of switches S 9  and S 10 , and can be connected to OUTN and OUTP, respectively, via a pair of switches S 11  and S 12 . 
     The non-inverting input of A 1  can be connected to INP via switches S 13  or S 14 , or to INN via a switch S 15 . A 1 &#39;s inverting input can be connected to INP via switches S 16  or S 17 , or to INN via a switch S 18 . Similarly, the non-inverting input of A 2  can be connected to INP via switches S 19  or S 20 , or to INN via a switch S 21 . A 2 &#39;s inverting input can be connected to INP via switches S 22  or S 23 , or to INN via a switch S 24 . 
     The ping-pong amplifier also preferably includes an output amplifier A 0 , which has a single-ended output OUT and differential inputs connected to OUTP and OUTN. A compensation capacitor CC is preferably connected between A 0 &#39;s output OUT and its inverting input. 
     The circuit configuration described above enables the ping-pong amplifier to employ both auto-zeroing and chopping techniques to improve performance. Switches S 1 -S 24  form a switching network, which is controlled by means of a control circuit  10 . Operation of the exemplary ping-pong amplifier of FIG. 2 a  is illustrated in the timing diagram of FIG. 2 b.  A four-phase timing cycle is used. Amplifier A 1  is auto-zeroed during the first and second phases (φ1 and φ2): switches S 14  and S 16  are closed to connect A 1 &#39;s inputs together, and switches S 1  and S 2  are closed to connect A 1 &#39;s outputs to the inputs of nulling amplifier A 3 . The resulting error signals are stored on memory capacitors CM 1  and CM 2 , and thereby applied to the inputs of nulling amplifier A 3 . A 3  converts the stored voltages to a pair of currents, which serve to auto-zero A 1 &#39;s outputs. 
     Note that, though amplifier A 1  is described above as being auto-zeroed during φ1 and φ2, it may also be auto-zeroed during (φ1 only or during φ2 only. Each of these alternatives is functionally equivalent to auto-zeroing A 1  during φ1 and φ2. 
     During φ1, switches S 9 , S 10 , S 19  and S 24  are closed, connecting the non-inverting and inverting outputs of A 2  to OUTP and OUTN, respectively, and A 2 &#39;s non-inverting and inverting inputs to INP and INN, respectively, such that differential input signals INP and INN are amplified by A 2  followed by output amplifier A 0 . 
     During φ2, the input and output connections to A 2  are reversed: S 9 , S 10 , S 19  and S 24  are opened, and switches S 11 , S 12 , S 21  and S 23  are closed, thereby connecting the non-inverting and inverting outputs of A 2  to OUTN and OUTP, respectively, and A 2 &#39;s non-inverting and inverting inputs to INN and INP, respectively. This has the effect of chopping the input and output signals of A 2 , which continues to amplify the input signal throughout φ2. 
     The roles of A 1  and A 2  are reversed during φ3 and φ4. Switches S 3 , S 4 , S 20  and S 22  are closed during φ3 and φ4 to auto-zero A 2 , with the resulting error voltages stored on memory capacitors CM 3  and CM 4  such that auto-zeroing signals are continuously applied to A 2 &#39;s outputs. 
     As discussed above in relation to the auto-zeroing of A 1 , A 2  may be auto-zeroed during φ3 only or during φ4 only. Each of these alternatives is functionally equivalent to auto-zeroing A 2  during φ3 and φ4. 
     During φ3, switches S 5 , S 6 , S 13  and S 18  are closed, connecting the non-inverting and inverting outputs of A 1  to OUTP and OUTN, respectively, and A 1 &#39;s non-inverting and inverting inputs to INP and INN, respectively, such that differential input signals INP and INN are amplified by A 1  followed by output amplifier A 0 . 
     During φ4, the input and output connections to A 1  are reversed: S 5 , S 6 , S 13  and S 18  are opened, and switches S 7 , S 8 , S 15  and S 17  are closed, thereby connecting the non-inverting and inverting outputs of A 1  to OUTN and OUTP, respectively, and A 1 &#39;s non-inverting and inverting inputs to INN and INP, respectively. This has the effect of chopping the input and output signals of A 1 , which continues to amplify the input signal throughout φ4. 
     Other possible arrangements of input switches S 13 -S 24  are shown in FIGS. 3 a-   3   g.  Each of these input switch arrangements is functionally equivalent to that shown in FIG. 2 a,  and will provide equivalent performance. The timing diagram shown in FIG. 2 b  is valid for all of the depicted input switch arrangements. 
     Other possible timing diagrams are shown in FIGS. 4 a-   4   d.  Each of these timing diagrams is functionally equivalent to that shown in FIG. 2 b,  and is valid for the switch arrangements shown in FIG. 2 a  and FIGS. 3 a-   3   g.  In FIG. 4 a,  the chopping sequence performed while A 1  amplifies the input signal is reversed (when compared with FIG. 2 b ), while in FIG. 4 b,  the chopping sequence performed while A 2  amplifies the input signal is reversed. In FIG. 4 c,  both chopping sequences are reversed. 
     The timing diagram shown in FIG. 4 d  is intended to illustrate the auto-zeroing of one of the gain amplifier during just one phase of the timing cycle. In the example shown, amplifier A 1  is auto-zeroed only during φ1, and amplifier A 2  is auto-zeroed only during φ3. 
     Another possible timing diagram is shown in FIG. 4 e.  Here, rather than perform a single chopping cycle during each auto-zero period, as in FIG. 2 b  and FIGS. 4 a-   4   d,  multiple chopping cycles are performed during each auto-zero period. This timing arrangement is functionally similar to that described above, and provides the same low offset and low low frequency noise benefits. Two chopping cycles per auto-zero period are illustrated in FIG. 4 e;  this would require the control circuit to operate the switching network in accordance with an 8-phase timing cycle. 
     An embodiment of the present invention which includes circuitry that reduces switching transients which might otherwise appear in the amplifier&#39;s output is shown in FIG. 5 a.  Here, each of the fully differential gain amplifiers A 1  and A 2  includes a common-mode reference voltage input CMR connected to receive a common-mode reference voltage VCMR, and a common-mode feedback circuit; VCMR is typically set to a value between the amplifier&#39;s power rails so that the amplifier may have a high gain. The common-mode feedback circuit sets the amplifier&#39;s common-mode output voltage so that each of its outputs is nominally set to VCMR when the differential output voltage is zero. 
     This embodiment of the present ping-pong amplifier also includes an error amplifier AS, which has one input connected to common-mode reference voltage VCMR, and its other input switchably connected to the common-mode output of one of the two gain amplifiers A 1  and A 2 . A pair of switches S 25  and S 26  are closed to connect the common-mode output of A 1  to A 5 , and a pair of switches S 27  and S 28  are closed to connect the common-mode output of A 2  to A 5 . A 5 &#39;s output is connected to A 1 &#39;s CMR input via a switch S 29 , and to A 2 &#39;s CMR input via a switch S 30 . Memory capacitors CM 5  and CM 6  are connected to the CMR inputs of A 1  and A 2 , respectively. 
     In operation, error amplifier A 5 &#39;s input is periodically connected to the common-mode output of A 1 , and its output is connected to A 1 &#39;s CMR input. This arrangement forms a closed-loop which forces A 1 &#39;s common-mode output voltage, i.e., VCMR 1 , to be equal to VCMR, with A 5 &#39;s output voltage stored on CM 5 . Similarly, A 5 &#39;s input and output are periodically connected to A 2 &#39;s common-mode output and CMR input, respectively, to force A 2 &#39;s common-mode output voltage, i.e., VCMR 2 , to be equal to VCMR, with A 5 &#39;s output voltage stored on CM 6 . The voltages stored on the memory capacitors continuously adjust the common-mode output voltages so that VCMR 1  and VCMR 2  are held equal to VCMR. Keeping VCMR 1 =VCMR 2 =VCMR ensures that transients due to mismatch in the common-mode feedback circuit are largely reduced. 
     The operation of a ping-pong amplifier which includes the switching transient reduction circuitry described above is shown in FIG. 5 b.  The timing sequence is nearly identical to that shown in FIG. 2 b,  except for the addition of the common-mode voltage adjustments described above. In FIG. 2 b,  amplifier A 1  is auto-zeroed during φ1 and φ2. Here, however, A 1  is only auto-zeroed during φ1; during φ2, switches S 25 , S 26  and S 29  are closed to adjust A 1 &#39;s common-mode voltage as described above. Similarly, A 2  is now auto-zeroed only during φ3; during φ4, switches S 27 , S 28  and S 30  are closed to adjust A 2 &#39;s common-mode voltage. 
     The alternative arrangements of input switches S 13 -S 24  shown in FIGS. 3 a-   3   g  can also be applied to the circuit arrangement shown in FIG. 5 a:  each of these input switch arrangements is functionally equivalent to that shown in FIG. 5 a,  and will provide equivalent performance. The timing diagram shown in FIG. 5 b  is valid for all of the depicted input switch arrangements. 
     Other possible timing diagrams are shown in FIGS. 5 c  and  5   d.  Both of these timing diagrams are valid for the switch arrangements shown in FIG. 5 a  and FIGS. 3 a-   3   g.  These timing diagrams depict alternate sequences for the auto-zero and common-mode output adjustment steps performed for the gain amplifiers, but each sequence is functionally equivalent to that shown in FIG. 5 b.    
     Another possible timing diagram is shown in FIG. 5 e.  Here, rather than perform a single chopping cycle during each auto-zero period, as in FIGS. 5 b-   5   d,  multiple chopping cycles are performed during each auto-zero period. This timing arrangement is functionally similar to that described above, and provides the same low offset and low low frequency noise benefits. Two chopping cycles per auto-zero period are illustrated in FIG. 5 e;  this would require the control circuit to operate the switching network in accordance with an 8-phase timing cycle. 
     While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.