Abstract:
A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.

Description:
This application is a continuation of application Ser. No. 08/948,774, filed on Oct. 10, 1997 (still pending). 
    
    
     The present invention relates to digital memory systems, and more specifically, to synchronous memory systems. 
     BACKGROUND OF THE INVENTION 
     As the operational frequencies of digital computing systems continue to increase, it has become increasingly necessary to use synchronous memory systems instead of the slower asynchronous memory systems. In synchronous memory systems, data is sent between a master device and one or more memory devices in the form of data packets which travel in parallel with, and must maintain precise timing relationships with, a system clock signal. 
     Because synchronous memory systems impose tight timing relationships between the clock and data signals, the memory interface circuits in the memory devices of the synchronous memory system generally require clock recovery and alignment circuits such as phase locked loops (PLLs) or delay locked loops (DLLs). One drawback of these clock recovery and alignment circuits, however, is that they typically operate effectively only over a limited range of frequencies. For example, a PLL may not be able to lock to the system&#39;s clock frequency if the frequency is either too low or too high. Additionally, the performance of these clock recovery and alignment circuits is degraded due to conditions such as temperature, supply voltage, speed binning codes, process, dimensions (i.e. length) of the memory bus, etc. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide for an adjustable synchronous memory control system. 
     It is a further object of this invention to provide for a synchronous memory control system that uses frequency information to improve the performance of the circuits at the system clock frequency. 
     It is a further object of this invention to provide for a synchronous memory system that uses system parameters to improve the performance of the circuits at the system clock frequency. 
     The present invention is a method for adjusting the performance of a synchronous memory control system. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved. 
     Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
     FIG. 1 illustrates one embodiment of the synchronous memory system of the present invention. 
     FIG. 2 illustrates a portion of the synchronous memory system of FIG.  1 . 
     FIG. 3 illustrates one embodiment of the memory interface circuitry inside a memory device of the present invention. 
     FIG. 4 illustrates a block diagram of one embodiment of a phase locked loop (PLL) circuit that may be used in the present invention. 
     FIG. 5 illustrates a block diagram of one embodiment of a delay locked loop (DLL) circuit that may be used in the present invention. 
    
    
     DETAILED DESCRIPTION 
     A method and apparatus for adjusting the performance of a memory system is described. The present invention is for a synchronous memory system wherein the master device has information about its operating frequency and transmits this frequency information to the memory devices. The memory devices then use this frequency information to adjust their clock recovery and alignment circuits to improve their performance at the system clock frequency. The master device may send the memory devices information that specifies the exact frequency of operation, or alternatively, the master device may send the memory devices information that specifies a predetermined range of frequencies which includes the system&#39;s clock frequency. For one embodiment, the frequency information is sent as a digital code that is received, stored, and decoded by the memory devices to produce a control code for adjusting the performance of the clock recovery and alignment circuits. 
     The synchronous memory system operates by sending and receiving data in packets which are synchronized with respect to a system clock. In order to do this properly, the memory master as well as all the slave devices must include circuitry that ensures that the data is read/written synchronously with the system clock. This circuitry is placed within the interface circuits of the memory master and slave devices. The key function of this circuitry is to produce internal clock signals within each device that maintain the proper phase relative to that of the external system clock such that data read or written to the channel by each of the devices is done so at the correct time, thereby preserving synchronization in the memory system. Because the memory devices may be used in different systems which use different operating clock frequencies, this circuitry should function effectively over a large range of possible system clock frequencies. 
     FIG. 1 illustrates one embodiment of the synchronous memory system of the present invention. This system comprises a master device  110 , a memory bus  180 , one or more memory devices  120 ,  130 , a system clock source  150 , and a terminator  140 . 
     The master device  110  can be a memory controller, a microprocessor, a 3-D firmware chip, or any other microchip that accesses the synchronous memory. The master device  110  includes a memory interface circuit  115  for transmitting and receiving data from the memory bus  180 . The master device  110  generates requests to store data into or recover data from the memory devices  120 ,  130  via the memory bus  180 . 
     The memory bus  180  is a data communications channel. For one embodiment, the memory bus  180  is a collection of wires or transmission lines. For one embodiment, the memory bus  180  comprises matched-impedance printed circuit board traces. 
     For one embodiment, the memory devices  120 ,  130  are dynamic random access memories (DRAMs). Alternatively, the memory devices  120 ,  130  are static random access memories (SRAMs) or other memory devices, each memory device  120 ,  130  includes a memory interface circuit  125 ,  135 , respectively, for transmitting and receiving data from the memory bus  180 . For one embodiment, the memory devices  120 ,  130  cannot generate requests for data but instead only respond to requests generated by the master device  110 . 
     The clock source  150  provides the synchronizing clock signal for the memory system at a system clock frequency. In FIG. 1, the clock source  150  is shown providing this clock signal to a signal line called CTM  160  (clock-to-master). In this implementation, the clock signal travels along the memory bus  180  from the clock source  150 , past all the memory devices  120 ,  130 , to the master device  110 . At the master device  110 , CTM  160  connects to another signal line called CFM  170  (clock-from-master). Thus, the clock signal travels back along the memory bus  180  in the opposite direction, away from the master device  110 , past all the memory devices  120 ,  130  and to the terminator  140 . Data sent from the master device  110  to the memory devices  120 ,  130  travels in parallel with the clock signal on CFM  170 . Likewise, data sent from the memory devices  120 ,  130  to the master device  110  travels in parallel with the clock signal of CTM  160 . 
     The terminator  140  provides a matched-impedance termination for the transmission lines of the memory bus  180 . For one embodiment, all signals transmitted on the memory bus  180  eventually terminate at the terminator  140 . Although it is included in the synchronous memory system of FIG. 1, some synchronous memory systems do not use a terminator  140 . For one embodiment, the terminator  140  is a plurality of resistors, coupled to the memory bus  180 , preventing reflection of the signal. 
     FIG. 2 shows a more detailed drawing of a portion of a synchronous memory system. In order to show more detail, only the master device  110 , one memory device  120 , and the portion of the memory bus  180  that connects these two devices is shown. FIG. 2 shows the memory interface circuits  115 ,  125  for both the master device  110  and the memory device  120 . Furthermore, the figure shows the clock recovery and alignment circuits  210 ,  220  (CRA circuits) within the interface circuits  115 ,  125 , respectively. FIG. 2 also shows the internal clock lines  215 ,  225  which are driven by the CRA circuits  210 ,  220 . These internal clock lines  215 ,  225  serve to synchronize the receive and transmit circuitry in the memory interface circuit  115 ,  125  to the system clock signals. 
     The master device  110  further includes information circuitry  290 . The information circuitry holds information about the system&#39;s clock frequency and other system-level information. For one embodiment, the information circuitry  290  holds system clock frequency information. The information circuitry  290  may detect and/or store other information which affects circuit functioning. For one embodiment, the information circuitry  290  may detect and/or store information about the system temperature, or temperature ranges. The information circuitry  290  may detect and/or store information about the supply voltage, or voltage range. The information circuitry  290  may further detect and/or store information about the length of the memory bus  180 , speed binning codes, process, and other factors that may affect the operation of the memory system. For one embodiment, the information circuitry  290  includes a PVTR detector. Detecting and storing this type of information is known in the art, as is the influence of the various factors on system operation. For one embodiment, the data in the information circuitry is also used to tune the performance of the CRAC  210  in the master device&#39;s memory interface  115 . 
     For one embodiment, the same information about frequency, voltage, temperature, etc. that is sent to the memory devices to tune the performance of their CRACs is also made available to a CRAC inside the master device to tune its performance. Chip-specific information about the master device, such as the master device&#39;s process condition may be used along with the information that is sent to the memory devices to tune the performance master device&#39;s CRAC. 
     The master device  110  uses the memory bus  180  to access data and control the memory device  120 . The master device  110  improves the performance of the CRACs in the memory device  120  by sending frequency information though the memory bus  180  to the memory device  120 . For one embodiment, the frequency information is sent as a digital code to the memory device  120 . Alternatively, for more accuracy, the frequency information may be sent as an analog signal. 
     FIG. 2 also shows the memory bus  180  in greater detail. The signal lines shown in FIG. 2 illustrate the types of signal lines present, in one embodiment. However, the number of signal lines illustrated do not correspond to the actual number of signal lines. The memory bus  180  includes the clock signal lines  250 , CTM  160  and CFM  170 , described above. 
     For one embodiment, the memory bus  180  includes a plurality of high-speed data lines  230 ,  270  which transmit data information between the master device  110  and the memory device  120  in parallel with either the CTM  160  or CFM  170  clock signals. The memory bus  180  also includes a plurality of high-speed control signal lines  240 ,  260  for transmitting address, request, acknowledge, and other control signals. Finally, the memory bus  180  includes lower-frequency “sideband” lines  280  for communicating information at lower speed between the master device  110  and the memory device  120 . 
     For one embodiment, the memory channel includes slow speed lines and high speed lines. For one embodiment, the slow speed lines are used for system control such as nap, and the high speed lines are used for data and addressing. The controller is aware of its operating frequency and communicates this information to the slave devices. For one embodiment, the master device communicates this information to the slave devices via the slow speed lines. The slave devices receive, decode, and use this frequency information to adjust the circuits in their CRACs to improve their performance at the system clock frequency and other operating conditions. In other words, frequency control information comes down the slow speed lines to adjust/improve the performance of the high speed lines. For an alternative embodiment, there is only one channel that operates first at low speed to send frequency control information to adjust the CRACs and then operates at high speed after adjustment. For another alternative embodiment, there is only one channel that always operates at high speed, but until the frequency control information has been sent, it operates with lower initial margin. 
     For one embodiment, the master device  110  sends the memory device  120  information that specifies the exact frequency of operation. For another embodiment, the master device  110  sends the memory device  120  information that specifies a predetermined range of frequencies which includes the system&#39;s clock frequency. 
     For one embodiment, the master device further includes a PVTR detector, and the information circuit  290  further sends information from this PVTR circuit to the slave devices. In one embodiment, the master has a PVTR detector or other detector for detecting system operating parameters. The master sends this information to the slave devices so that they can adjust their performance. This data can be sent via any of the 3 ways described above, i.e. over a separate slow speed channel, over a temporarily slow speed channel, or over an initially low margin high speed channel. 
     In an alternative embodiment, each individual slave device has a PVTR detector to control the performance of its own CRAC circuits. 
     In yet another embodiment, the master sends frequency information to the slaves, but each slave ALSO has its own PVTR detector. The frequency data is combined with the PVTR data to properly adjust the CRACs to account for both of these two types of operating information. 
     For one embodiment, such information is sent to the memory device  120  periodically during operation of the memory system. For another embodiment, the information is sent only once, during initialization of the memory system. 
     FIG. 3 shows a close-up view of one embodiment the memory interface circuitry  125  inside a memory device  120  of the present invention. The memory interface circuitry  125  includes a clock recovery and alignment circuit  310  (CRA circuit), transceiver circuitry  330 , an n-bit wide register circuit  340 , and an m-output decoder circuitry  350 . The transceiver circuitry  330  is designed to receive data from and/or transmit data to the memory bus  180 . The m-output decoder circuitry  350  is designed to decode the frequency information sent by the master device  110  and stored in the register circuit  340  to produce a corresponding m-bit control code. 
     The master device  110  (not shown) sends the information about the system&#39;s operating frequency to the memory device  120 . The frequency information is encoded onto n bits as described below. This frequency information is then received by the transceiver circuitry  330  in each memory device  120 . The use of transceiver circuitry  330  for receiving data from the memory bus  180  is well-known in the art. Upon receiving this information about the system&#39;s clock frequency, the transceiver circuitry  330  stores it into the n-bit register circuit  340 . For one embodiment, the frequency information is stored in the register circuit  340  during normal system operation or at the initialization of the system. 
     The n-bit register circuit  340  presents this frequency information to a decoder circuitry  350 . The decoder circuitry  350  translates this frequency information into a m-bit control code for adjusting the performance of the CRA circuitry  310 . For one embodiment, the control code is used to adjust one or more portions of the CRA circuitry  310  such that the circuitry operates effectively at the system&#39;s clock frequency. For another embodiment, the control code adjusts the CRA circuitry  310  to optimize for external factors, such as temperature, memory bus  180  length, supply voltage, etc. 
     There are several ways that the frequency information can be encoded into n bits and then sent to and stored in the memory device  120 . For one embodiment, a binary word indicates the time period of the system clock in pico-seconds (ps), where period=1/frequency. For example, using a 16-bit register, a 16-bit digital word can be sent to the memory device  120  that indicates with 1 ps precision that the system&#39;s clock period is anywhere from 0 ps to 65,535 ps (2 16 -1). Alternatively, a more compact digital code that indicates one of a predetermined range of frequencies which includes the system&#39;s clock frequency may be used. This scheme requires the storage of fewer bits than the first scheme, but only specifies a range of frequencies instead of an exact frequency. One example of a compact code that could be used, and its corresponding range of frequencies, is shown in the table below: 
     
       
         
               
             
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Code Indicating Frequency Range 
               
             
          
           
               
                   
                 Minimum 
                 Maximum 
                 Frequency 
               
               
                 Compact Code Bits 
                 Frequency 
                 Frequency 
                 Range Size 
               
             
          
           
               
                 C1 
                 C0 
                 (fmin) 
                 (fmax) 
                 (Delta_F) 
               
               
                   
               
               
                 0 
                 0 
                 238 MHz 
                 282 MHz 
                 44 MHz 
               
               
                 0 
                 1 
                 278 MHz 
                 327 MHz 
                 49 MHz 
               
               
                 1 
                 0 
                 323 MHz 
                 382 MHz 
                 59 MHz 
               
               
                 1 
                 1 
                 378 MHz 
                 447 MHz 
                 69 MHz 
               
               
                   
               
             
          
         
       
     
     As can be seen, this scheme uses only 2 bits instead of 16 bits. 
     Once the frequency information has been stored in the n-bit register circuit  340 , the decoder circuitry  350  evaluates this n-bit data to produce the required m-bit control code for adjusting the CRA circuitry  310  for optimal operation. For one embodiment, the control code that is decoded from the frequency information specifies a range of operating frequencies. This is simple if the register circuit  340  is given a compact code that specifies a range of frequencies which includes the system&#39;s clock frequency. The decoder circuitry  350  is more complex if the register circuit  340  holds the period of the system&#39;s clock signal. For one embodiment, the decoder circuitry  350  includes a simple look-up table for frequency ranges corresponding to control codes. For one embodiment, these tables are hard wired. For one embodiment, these tables may be altered by a user. The decoded control code is then sent to the CRA circuit  310 . 
     The CRA circuit  310  adjusts the phase of internal clock signals so that the receive and transmit circuitry of the memory device  120  will be synchronized with the system clock signals CTM &amp; CFM. The CRA circuit  310  may include variable delay elements, phase interpolator (mixer) circuits, and slew rate control circuits. By receiving and responding to these control codes, these circuits enable the synchronous memory system to operate effectively over a larger range of system clock frequencies than would be possible without the control codes. For one embodiment, the CRA circuit  310  is a phase locked loop (PLL) circuit. For another embodiment, the CRA circuit  310  is a delay-locked loop (DLL) circuit. 
     The control codes are used to adjust the locking frequency range of the clock recovery and alignment circuits to include the operating clock frequency of the system. The control codes are also used to reduce the jitter of the signals on the high-speed lines, and to improve the timing margin of the signals on the high-speed lines. 
     FIG. 4 illustrates a block diagram of one embodiment of a phase locked loop (PLL) circuit. The phase locked loop  400  is a feed back device that attempts to lock to the phase of an incoming signal. The phase detector compares the phase of the incoming signal  410  to that of the reference signal  460 . The reference signal  460  is the output of the PLL  400 , and it also serves as the feedback signal for the PLL system. 
     An input signal  410  is an input to the phase detector  420 . For one embodiment, the input signal  410  is a system clock signal such as CTM. The output of phase detector  420  is an input to integrator/filter  430 . The output of integrator/filter  430  is input to a voltage controlled oscillator (VCO)  440 . The output of the VCO  440  is the output of the phase locked loop  400 . The output of the VCO  440  is the reference signal  460 , which is input to the phase detector  420 . 
     An example of how the phase locked loop works is as follows. At the beginning the loop is in balance, i.e. the loop error is equal to zero. Assume that the frequency of the incoming signal increases slightly. This means that the phase of that signal changes a little faster—phase is the integral of frequency. Accordingly, the loop error becomes positive because the phase of the reference signal cannot change at once due to inherent delays in the PLL  400 . The frequency generated by the VCO  440  follows the changes in the error signal so that it also increases. The final consequence is that an increase in the incoming signal&#39;s frequency causes an increase in the frequency of the reference signal. Thus, the reference signal  410  and incoming signal  410  converge on the same frequency. The elements of the PLL  440  are known in the art. 
     FIG. 5 illustrates a block diagram of one embodiment of a delay locked loop (DLL) circuit that can be used in the CRAC. An input signal is placed on input line  510  of the delay locked loop  500 . The input signal is also an input to the delay element  550 . The phase detector  520  functions to compare the phase difference between the input signal  510 , and a feedback signal on feedback loop  570 , and to generate two possible outputs, up, and down, representing the phase difference between the input signal and the feedback signal. The up and down signal outputs of the phase detector  520  are input to a charge pump  530 . The charge pump is controlled by the up and down signals to raise or lower the voltage on its output line. The voltage on the output line is an input to a low pass filter  540 , where it is filtered and delivered to delay element  550 . The delay element  550  functions to delay the input signal, in proportion to the voltage delivered by the low pass filter  540 . This delayed signal is the output signal on line  560 , and is fed back to the phase detector  520  via the feedback line  570 . 
     Although this disclosure has stressed the use of frequency information to tune the clock recovery and alignment circuit of the memory device  120 , other relevant information could be transmitted to the memory device  120  and held by its register circuit  340  to tune the performance of clock recovery and alignment circuits. Examples of other types of information that could be sent from the master to the memory device  120  are temperature, supply voltage, speed binning codes, dimensions of the memory bus  180 , etc. Any one or more of these types of information could be sent from the master device  110  to the memory device  120  to tune the memory device  120  circuits to operate more effectively under the system&#39;s operating conditions.