Abstract:
A control circuit which switches a power supply circuit includes: a first control circuit to suspend a switching operation based on an output voltage of the switching power supply circuit; and a second control circuit to change a magnitude of a first load coupled to an output of the switching power supply circuit based on a suspension period of the switching operation, wherein the second control circuit changes the magnitude of the first load in a first suspension period based on a second load, which is updated in a second suspension period prior to the first suspension period.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-270328 filed on Nov. 27, 2009, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     1. Field 
     Embodiments discussed herein relate to a control circuit for a switching power supply circuit. 
     2. Description of Related Art 
     A switching power supply circuit that supplies a load with power, for example, a DC-DC converter that converts a DC voltage into another DC voltage, is provided in an electronic device, etc. 
     A related art is disclosed in Japanese Laid-open Patent Publication No. 2008-253051, etc. 
     SUMMARY 
     According to one aspect of the embodiments, a control circuit which switches a power supply circuit includes: a first control circuit to suspend a switching operation based on an output voltage of the switching power supply circuit; and a second control circuit to change a magnitude of a first load coupled to an output of the switching power supply circuit based on a suspension period of the switching operation, wherein the second control circuit changes the magnitude of the first load in a first suspension period based on a second load that is updated in a second suspension period prior to the first suspension period. 
     Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an exemplary circuit; 
         FIG. 2  illustrates an exemplary operation of a light load; 
         FIG. 3  illustrates an exemplary adjusting suspension period circuit; 
         FIG. 4  illustrates an exemplary adjusting suspension period circuit; 
         FIG. 5  illustrates an exemplary operation of an adjusting suspension period circuit; 
         FIG. 6  illustrates an exemplary operation of an adjusting suspension period circuit; and 
         FIG. 7  illustrates exemplary output voltage waveforms. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     A DC-DC converter may have a PFM function for suspending and performing a switching operation if an output voltage increases and decreases, respectively. Because a period for outputting the decreased output voltage is determined by an output capacitor and a load current, the switching operation is suspended for a longer period of time as the load is reduced. In order to decrease the output voltage in case of a light load, a switching element provided between the output and ground is kept on for a predetermined period of time so that any electric charge stored in the output capacitor is discharged. 
     When, for example, the switching operation is suspended for a period of time longer than a predetermined time period in case of a light load, the switching element is turned on. The decrease of the output voltage for a period of time until the switching element is turned on is determined by the output capacitor and the load current. A ripple waveform of the output voltage may include a low frequency component depending upon the output capacitor and the load current in the period of time until the switching element is turned on. 
       FIG. 1  illustrates an exemplary circuit. An error amplifier ErrAMP amplifies a difference between a feedback voltage, which is obtained by dividing an output voltage Vout with resistors R 1  and R 2 , and a reference voltage Vref. A phase compensating circuit may include a capacitor C 1  coupled between an inverted input terminal and an output terminal of the error amplifier ErrAMP. An output err_out of the error amplifier ErrAMP is input to an inverted input terminal of a comparator Comp  1 . 
     A current which flows through an inductor L is converted into a sensed voltage vsense by a current sensing circuit  4  and a sensing resistor Rs, and is supplied to a slope compensating circuit  5 . The slope compensating circuit  5  may reduce oscillation which occurs when an on-duty ratio is 50 percent or higher. An output slp_out of the slope compensating circuit  5  is supplied to a non-inverted input terminal of the comparator Comp 1 , and is compared with the output err_out of the error amplifier ErrAMP. 
     Set and reset terminals of an RS flip-flop  1  are provided with a clock ck and an output of the comparator Comp  1 , respectively. The RS flip-flop  1  outputs a PWM signal PWM_out. The PWM signal PWM_out is input to a gate of a switching element SW 1  via a logic circuit  2  and an AST (Anti-Shoot-Through) circuit  3 . The switching element SW 1  may include a p-channel MOSFET, for example. 
     A switching element SW 2  carries out a synchronous regulating operation. A comparator Comp 2  compares voltages of both ends of the switching element SW 2  with each other and provides the logic circuit  2  with a signal for stopping the switching element SW 2 , so that a reverse current may be reduced. The switching element SW 2  includes, for example, an n-channel MOSFET. The AST circuit  3  may include a driver, and may reduce the switching elements SW 1  and SW 2  turning on contemporaneously or prevent the switching elements SW 1  and SW 2  from turning on contemporaneously. 
     The DC-DC converter controls the on-duty ratio of the switching element SW 1  depending upon the output voltage Vout, steps down an input voltage Vin so as to produce the output voltage Vout, and supplies the load with the output voltage Vout. 
     A comparator Comp 3  compares the output err_out of the error amplifier ErrAMP and a threshold voltage Vth, so as to provide the logic circuit  2  with a signal pfm for stopping the switching operation of the switching element Sw 1  or SW 2 .  FIG. 2  illustrates an exemplary operation in case of a light load.  FIG. 2  illustrates a PFM function as well. If, for example, the output voltage Vout increases, the output err_out of the error amplifier ErrAMP decreases. If the output err_out of the error amplifier ErrAMP becomes lower than the threshold voltage Vth, the output pfm of the comparator Comp 3  turns from a high level to a low level. As illustrated in  FIG. 2 , the DC-DC converter carries out a PWM operation when the output pfm of the comparator Comp 3  is at a high level and suspends the switching operation when the output pfm of the comparator Comp 3  is at a low level. The PFM function reduces the increase of the output voltage Vout in case of a light load. A waveform LX may correspond to a voltage on a connection node between the switching elements SW 1  and SW 2  and the inductor L. 
     An inclination of the decrease of the output voltage Vout may be determined by an output capacitor Co and a load current Io. The inclination of the decrease of the output voltage Vout becomes small in case of a light load. As the inclination corresponds to the low frequency component, noise may occur in an audible range. The DC-DC converter includes an adjusting suspension period circuit  6  for adjusting a suspension period of the switching operation to a target cycle when the suspension period of the switching operation is extended. The adjusting suspension period circuit  6  compares a frequency fpfm of the output pfm of the comparator Comp 3  and a reference frequency fref of a reference signal. For example, when the switching operation is suspended for a long time, the adjusting suspension period circuit  6  adjusts load resistors RL so that the frequency fpfm agrees with the reference frequency fref. 
       FIG. 3  illustrates an exemplary adjusting suspension period circuit. An F/V converting circuit  11  converts the frequency fpfm of the output pfm of the comparator Comp 3  into a voltage. An F/V converting circuit  12  converts the reference frequency fref of the reference signal into a voltage. An amplifier Amp controls a gate voltage of a transistor M 11  depending upon a difference between the two F/V-converted signals. A drain of the transistor M 11  is coupled to a supply line of the output voltage Vout, and a source of the transistor M 11  is grounded via a resistor R 11 . 
     When an output voltage of the amplifier Amp is set to Va and a threshold voltage of the transistor M 11  is set to Vth 1 , a current I which flows through the resistor R 11  is denoted by I=(Va−Vth 1 )/R 11 . For example, when the frequency fpfm of the output pfm of the comparator Comp 3  is reduced, the output voltage Va of the amplifier Amp increases. Therefore, the current I which flows through the resistor R 11  increases. The load on the load resistors RL adjusted by the adjusting suspension period circuit  6  becomes heavy, and the DC-DC converter may shorten the suspension period of the switching operation. For example, when the frequency fpfm of the output pfm of the comparator Comp  3  grows, the output voltage Va of the amplifier Amp decreases. Therefore, the current I which flows through the resistor R 11  decreases. When the load is heavy and the load current Io is large enough, the current I which flows through the resistor R 11  becomes substantially zero, and the adjusting suspension period circuit  6  may not work during the suspension period of the switching operation. The adjusting suspension period circuit  6  may work when the frequency fpfm of the output pfm of the comparator Comp  3  becomes lower than the reference frequency fref of the reference signal so as to make the frequency fpfm match with the reference frequency fref. 
       FIG. 4  illustrates an exemplary adjusting suspension period circuit. The output pfm of the comparator Comp 3  is input to a counter  21  and a comparing unit  23  via an inverter  20 . When the output pfm of the comparator Comp 3  is at a low level, the counter  21  counts in synchronization with the clock ck. When a counted value reaches a predetermined value Tref 1 , the counter  21  outputs a signal having a high level. The comparing unit  23  compares a period of time for which the output pfm of the comparator Comp 3  is at a high level, for example, a suspension period Tpfm of the switching operation, with an output of the counter  21 , such as a predetermined value Tref 1 , so as to provide an Up/Down counter  25  with a result of the comparison. 
     The output pfm of the comparator Comp 3  is input to a counter  22  and a comparing unit  24 . When the output pfm of the comparator Comp 3  is at a high level, the counter  22  counts synchronously with the clock ck. When a counted value reaches a predetermined value Tref 2 , the counter  22  outputs a signal having a high level. The comparing unit  24  compares a period of time for which the output pfm of the comparator Comp 3  is at a high level, for example, a period Tpwm of the PWM operation, with an output of the counter  22 , for example a predetermined value Tref 2 , so as to provide the Up/Down counter  25  with a result of the comparison. 
     The Up/Down counter  25  counts up or down in accordance with the output of the comparing unit  23  or  24 . A selector  26  selects at least one of transistors M_ 1 , M_ 2 , . . . , and M_N. The drains of the transistors M_ 1 , M_ 2 , . . . , and M_N are coupled to the supply line of the output voltage Vout via resistors RL_ 1 , RL_ 2 , . . . , and RL_N, respectively. The sources are grounded. The Up/Down counter  25  and the selector  26  turns the transistors M_ 1 , M_ 2 , . . . , and M_N on or off in accordance with the output of the comparing unit  23  or  24 , so as to adjust the number N of the load resistors RL coupled in parallel. 
       FIG. 5  illustrates an exemplary operation of an adjusting suspension period circuit. The operation illustrated in  FIG. 5  may be performed by the adjusting suspension period circuit  6  illustrated in  FIG. 4 . The number N of the load resistors RL coupled in parallel may be N=0 in an initial state (operation S 0 ). 
     If the output pfm of the comparator Comp 3  is at a low level (operation S 1 : YES), the counter  21  counts a period of an L-state (operation S 2 ). When the output of the comparing unit  23  indicates that the suspension period Tpfm of the switching operation is longer than a predetermined value Tref 1  which indicates a target period (operation S 3 : NO), the Up/Down counter  25  and the selector  26  increases the number N of the load resistors RL coupled in parallel by one (operation S 4 ). When the output of the comparing unit  23  indicates that the output pfm of the comparator Comp 3  is at a low level (operation S 5 : YES), the Up/Down counter  25  and the selector  26  increases the number N of the load resistors RL coupled in parallel by one (operation S 4 ). When the output of the comparing unit  23  indicates that the output pfm of the comparator Comp 3  is at a high level (operation S 5 : NO), the process proceeds to an operation where the output pfm of the comparator Comp 3  is at a high level (operation S 1 : NO). 
     When the output of the comparing unit  23  indicates that the suspension period Tpfm of the switching operation is shorter than a predetermined value Tref 1  that indicates the target period (operation S 3 : YES), the Up/Down counter  25  and the selector  26  decreases the number N of the load resistors RL coupled in parallel by one (operation S 6 ). The process proceeds to an operation where the output pfm of the comparator Comp 3  is at a high level (operation S 1 : NO). 
     If the output pfm of the comparator Comp 3  is at a high level (operation S 1 : NO), the counter  22  counts a period of an H-state (operation S 7 ). If the output of the comparing unit  24  indicates that the period Tpwm of the PWM operation is longer than a predetermined value Tref 2  (operation S 8 : NO), the Up/Down counter  25  and the selector  26  decreases the number N of the load resistors RL coupled in parallel by one (operation S 9 ). The counter  22  continues counting a period of the H-state (operation S 7 ). The particular value Tref 2  may be any value, and may be as many as ten cycles of the PWM period. 
     Meanwhile, when the output of the comparing unit  24  indicates that the period Tpwm of the PWM operation is shorter than a predetermined value Tref 2  (operation S 8 : YES), the process proceeds to an operation where the output pfm of the comparator Comp 3  is at a low level (operation S 1 : YES). 
       FIG. 6  illustrates an exemplary operation of the adjusting suspension period circuit. The operation illustrated in  FIG. 5  may be performed by the adjusting suspension period circuit  6  illustrated in  FIG. 4 . In  FIG. 6 , for example, the input voltage Vin may be set to 3.6V, the output voltage Vout may be set to 2.8V, the load current Io may be set to 0 mA (no load), a predetermined value Tref 1  may be set to 21.333 μs (46.875 kHz), and the number N of the load resistors RL may be set to eight (8). In the adjusting suspension period circuit  6 , as illustrated in  FIG. 5 , when the output pfm of the comparator Comp 3  is at a high level, the counter  21  counts the period of the L-state, and the comparing unit  23  compares the counted value with a predetermined value Tref 1 , which indicates the target period. Because the load is light when the suspension period Tpfm of the switching operation is longer than a predetermined value Tref 1 , the adjusting suspension period circuit  6  increases the number N of the load resistors RL coupled in parallel until the suspension period Tpfm of the switching operation reaches a high level. As illustrated in  FIG. 6 , a current IRL which flows through the load resistors RL increases in a phased manner, and the inclination of the decrease of the output voltage Vout increases, for example, in a segment between 0 and 100 μs. 
     Then, because the load is heavy when the suspension period Tpfm of the switching operation is shorter than a predetermined particular value Tref 1 , the adjusting suspension period circuit  6  decreases the number N of the load resistors RL coupled in parallel, for example, by one. As illustrated in  FIG. 6 , the current IRL which flows through the load resistors RL decreases in a phased manner, and the inclination of the decrease of the output voltage Vout reduces, for example, in a segment between 100 and 200 μs. 
     In the adjusting suspension period circuit  6 , as illustrated in  FIG. 5 , when the output pfm of the comparator Comp 3  is at a high level, the counter  22  counts the period of the H-state, and the comparing unit  24  compares the counted value with a predetermined value Tref 2 . Because the load is heavy when the period Tpwm of the PWM operation is longer than a predetermined particular value Tref 2 , the adjusting suspension period circuit  6  decreases the number N of the load resistors RL coupled in parallel, for example, by one each time. When the load is heavy, the number N of the load resistors RL coupled in parallel may be zero. 
     The adjusting suspension period circuit  6  adjusts the number N of the load resistors RL coupled in parallel by repeating the above operation, so that the suspension period Tpfm of the switching operation is, for example, 21.2 μs as illustrated in  FIG. 6 . When the suspension period Tpfm of the switching operation is long in case of a light load, the adjusting suspension period circuit  6  performs a control operation so that the suspension period Tpfm of the switching operation converges on a predetermined value Tref 1  which indicates the target period, i.e., Tpfm≈Tref 1 . 
     The adjusting suspension period circuit  6  illustrated in  FIG. 3  monitors the frequency fpfm of the output pfm of the comparator Comp 3 . The adjusting suspension period circuit  6  illustrated in  FIG. 4  monitors the suspension period Tpfm of the switching operation. As illustrated in  FIG. 6 , the suspension period Tpfm of the switching operation and the period Tpwm of the PWM operation may have a relationship such as Tpfm&gt;Tpwm. The suspension period Tpfm of the switching operation may be monitored, and a cycle of the output pfm of the comparator Comp 3  may be monitored. When the suspension period Tpfm of the switching operation and the particular value Tref 1  have a relationship such as Tpfm=Tref 1  at operation S 3 , as illustrated in  FIG. 5 , the process proceeds to operation  6 , and the number N of the load resistors RL coupled in parallel is reduced by one. For example, the process proceeds to operation S 4 , e.g., and the number N of the load resistors RL coupled in parallel may be increased by one. When the suspension period Tpfm of the switching operation and a predetermined value Tref 1  have a relationship such as Tpfm=Tref 1  at the operation S 3 , the process may proceed to operation S 7 . 
       FIG. 7  illustrates exemplary output voltage waveforms. The output voltage illustrated in  FIG. 7  may indicate ripple waveforms of the output voltage Vout which appear after the adjustment of the suspension period of the switching operation. The adjusting suspension period circuit  6  of the DC-DC converter changes a resistance value of the load resistors RL based on the resistance value of the load resistors RL, which is changed in accordance with the suspension period of the switching operation. For example, as illustrated in  FIG. 7 , in case of a light load where the load current Io is small, an inclination of reduction of the output voltage Vout is adjusted. The ripple waveform of the output voltage may track a desired state where no low frequency component is included. If the load current Io is large enough and the suspension period of the switching operation is short, the current may not be subtracted more than is necessary. 
     For example, if the system supplied with power is an audio system, and the low frequency component included in the ripple waveform of the output voltage gets close to an audible frequency range, the low frequency component may appear as noise to the system. The low frequency component included in the ripple waveform of the output voltage is reduced in the period of suspension, and the frequency components included in the ripple waveform of the output voltage may be separated from the audible frequency range. 
     As the output voltage Vout tracks a desired state, the noise caused by the suspension period of the switching operation, in case of a light load, may be reduced. 
     An electronic device including the DC-DC converter described above, a battery which supplies the input voltage Vin, and a load which works upon being supplied with the output voltage Vout may be provided. 
     Example embodiments of the present invention have now been described in accordance with the above advantages. It will be appreciated that these examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.