Abstract:
A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits  0:3 ) and a right half (for storing bits  4:7 ). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM&#39;s defective half are made to a half of a spare DRAM in the DIMM, while the DRAM&#39;s non-defective half continues to be used for subsequently storing data.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates in general to the field of computers, and in particular to memory devices. Still more particularly, the present invention relates to a method and system for self-healing a memory module, which has multiple memory sub-modules, by removing a portion of one of the multiple memory sub-modules from service.  
         [0003]     2. Description of the Related Art  
         [0004]     A key feature of modern computers is modularity. That is, with few or no tools, a computer owner can replace different components inside the computer&#39;s enclosure. By simply snapping in new components into existing sockets and/or cables, a non-expert user can install and/or replace his computer&#39;s hard drive, a wireless modem, and even a main processor. One of the most common components to be replaced, usually due to failure, is the computer&#39;s system memory.  
         [0005]     Early computers primarily used Static Random Access Memory (SRAM) for system memory. While SRAMs are still in common use, particularly where memory speed is essential, they have some drawbacks. For example, SRAM draws a significant amount of power when in stand-by mode, and thus is not very useful in a battery powered device such as a laptop computer or a Personal Digital Assistant (PDA). Similarly, SRAMs are physically large, thus making them difficult to use in small computing devices such as PDAs, as well as in any other computer system, including servers, in which space is limited. Finally, SRAMs are relatively expensive, especially in comparison to Dynamic Random Access Memory (DRAM).  
         [0006]     DRAMs use a network of storage cells that are each made up of a transistor that is under the logical control of a capacitor. Since capacitors tend to lose their charge quickly, DRAMs must refresh the storage cells (replenish the charge to the capacitors) every few milliseconds. Nonetheless, DRAMs draw less operational current than SRAMs.  
         [0007]     As noted above, in modern computers, system memory is packaged to be easily installed and/or replaced. A common type of easily installed system memory comes as a package known as a Single In-line Memory Module (SIMM). Within the SIMM are multiple memory sub-modules of Dynamic Ransom Access Memory (DRAM) memory. Each memory sub-module is typically referred to simply as a DRAM.  
         [0008]     Another popular type of replaceable system memory is a Dual In-line Memory Module (DIMM). A DIMM is similar to a SIMM except that a DIMM has DRAMs on two sides of an interior of the DIMM, rather than on just one side (as is found in the SIMM). By having memory on both sides of its interior, the DIMM obviously can hold more DRAMs and thus more memory is available to the computer.  
         [0009]     A significant problem with DRAMs is that they are somewhat prone to failure. For example, consider a DIMM  100  shown in  FIG. 1   a . DIMM  100  contains n-number of DRAMS  102 . If one or more of the DRAMS  102  fails, then the entire DIMM  100  can be snapped out and replaced. Alternatively, if only one of the DRAMs  102  (e.g., DRAM  102 - 1 ) should fail, then the failed DRAM ( 102 - 1 ) can be taken out of service, and DIMM  100  is able to continue to function at a reduced level. While taking only the failed DRAM  102 - 1  out of service rather than the entire DIMM  100  is a savings improvement, removing the entire DRAM  102 - 1  from service is still be wasteful, particularly if only a portion of the DRAM  102 - 1  is actually defective. For example, assume that, as shown in  FIG. 1   b , only one of the columns of storage cells (column  1 ) is defective. By taking DRAM  102 - 1  out of service, then the rest of the columns that are still good (columns  0  and  2 - 7 ) are now wasted.  
         [0010]     What is needed, therefore, is a method and system for reclaiming a use of a second portion of a memory sub-module (such as a DRAM in a DIMM) when a first portion of the DRAM fails. Preferably, such a method and system will be automatic to allow the DIMM to be self-healing.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention is thus directed to a method and system for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits  0 : 3 ) and a right half (for storing bits  4 : 7 ). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM&#39;s defective half are made to a half of a spare DRAM in the DIMM, while the DRAM&#39;s non-defective half continues to be used for subsequently storing data.  
         [0012]     The above, as well as additional purposes, features, and advantages of the present invention will become apparent in the following detailed written description.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further purposes and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, where:  
         [0014]      FIGS. 1   a - b  illustrate a prior art Dual In-line Memory Module (DIMM) having a defective Dynamic Random Access Memory (DRAM) sub-module;  
         [0015]      FIG. 2  depicts an exemplary computer system in which the present invention may be implemented;  
         [0016]      FIG. 3   a  illustrates a quartet of DIMMs coupled to a memory controller (MC), with the first three DIMMs having primary DRAMs and the fourth DIMM having primary DRAMs and a spare DRAM;  
         [0017]      FIG. 3   b  depicts a first partition and a second partition in a DRAM;  
         [0018]      FIGS. 4   a - b  illustrate a system for detecting and correcting an error in data stored in a primary DRAM in a DIMM, for generating a bit steer signal based on whether the first or second partition of the primary DRAM is defective, and for creating a corrected data unit that includes a first data sub-unit in which the error originally occurred in a defective partition of the primary DRAM and a second data sub-unit that was always error free in a non-defective partition of the primary DRAM;  
         [0019]      FIG. 5   a  depicts a system for selectively storing the first data sub-unit in the spare DRAM and the second data sub-unit in the non-defective half of the primary DRAM;  
         [0020]      FIG. 5   b  depicts a plurality of multiplexers (MUXs) for selectively reading data from the primary or spare DRAMS;  
         [0021]      FIG. 6   a  is a flow-chart of steps taken to store corrected data in the primary and spare DRAMs; and  
         [0022]      FIG. 6   b  is a flow-chart of steps taken to read corrected data from the primary and spare DRAMs.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0023]     With reference now to  FIG. 2 , there is depicted a block diagram of an exemplary data processing system in which a preferred embodiment of the present invention may be implemented. Data processing system  200  may be, for example, one of the models of personal or server computers available from International Business Machines Corporation of Armonk, N.Y. Data processing system  200  includes a central processing unit (CPU)  202 , which is connected to a system bus  208 . In the exemplary embodiment, data processing system  200  includes a graphics adapter  204  also connected to system bus  208 , for providing user interface information to a display  206 .  
         [0024]     Also connected to system bus  208  is a memory controller  210 , which controls data being read from and written to a system memory  212 . System bus  208  is also connected to an input/output (I/O) bus bridge  214 , which couples an I/O bus  216  to system bus  208 , relaying and/or transforming data transactions from one bus to the other. Peripheral devices such as nonvolatile storage  218 , which may be a hard disk drive, and input device  220 , which may include a conventional mouse, a trackball, or the like, is connected to I/O bus  216 . Also connected to I/O bus  216  is a network interface  222 , which permits data communication with a network (not shown), which may be the Internet.  
         [0025]     The exemplary embodiment shown in  FIG. 2  is provided solely for the purposes of explaining the invention and those skilled in the art will recognize that numerous variations are possible, both in form and function. For instance, data processing system  200  might also include a compact disk read-only memory (CD-ROM) or digital versatile disk (DVD) drive, a sound card and audio speakers, and numerous other optional components. All such variations are believed to be within the spirit and scope of the present invention.  
         [0026]     In a preferred embodiment, system memory  212  is composed of multiple Dual In-line Memory Modules (DIMMs) having multiple Dynamic Random Access Memory (DRAM) sub-modules (hereinafter described simply as “DRAMs”). An exemplary system memory  212  is depicted in  FIG. 3   a . System memory  212  is made up of four DIMMs  302 , each of which has multiple DRAMs  304 . Each DIMM  302  processes 72 bits at a time, for a total bandwidth to MC  210  of 288 bits. (Note that in an alternate embodiment, there may be only two DIMMs  302 - 1 , 2 , such that MC  210  receives two passes of data from DIMMs  302 - 1 , 2  for a total of 288 bits.) These 288 bits are allocated as 256 bits for data (4×64), 24 bits (4×6) for Error Correction Code (ECC) bits, and 8 bits (4×2) for spares, for a total of 288 bits. This data, going between system memory  212  and CPU  202 , is coordinated by MC  210 .  
         [0027]     Note that MC  210  also includes an ECC logic  306  for implementing ECC for data going to and from system memory  212 . Details of the use of this ECC  306  logic are shown in the following figures.  
         [0028]     As described in  FIG. 3   b , each DRAM  304  is composed of a first partition  308   a  and a second partition  308   b . As illustrated, each partition  308  is preferably made up of contiguous bit columns. Likewise, first partition  308   a  is preferably the “left half” of DRAM  304  (i.e., bit spaces  0 : 3 ) and second partition  308   b  is preferably the “right half” of DRAM  304  (i.e., bit spaces  4 : 7 ). Alternatively, each partition  308  may be any portion of DRAM  304 .  
         [0029]     Referring now to  FIGS. 4   a - b , some of the components that make up ECC logic  306  are shown, including an ECC generator  402 , an ECC comparator and syndrome generator  404 , and an ECC matrix  406 . As will be described in further detail below, ECC matrix  406  corrects an error in a data unit that was read from DIMM  302  to create a corrected data unit, determines which portion of which DRAM  304  the data error occurred, and generates a bit steer signal and a memory controller (MC) selector for MC  210  based upon which partition(s) of which DRAM(s)  304  originally produced the erroneous data.  
         [0030]     As shown in  FIG. 4   a , DE describes a set of 256 bits of data, which is being sent from MC  210  to DIMMs  302 - 1 , 2 , 3 , 4 , which include DRAM 1   304 - 1  and DRAM 2   304 - 2 . DRAM 1   304 - 1  holds data in bit locations ( 0 : 3 ) and ( 4 : 7 ), while DRAM 2   304 - 2  holds data in bit locations ( 8 : 11 ) and ( 12 : 15 ).  
         [0031]     The 256 bits of data in DE is first input into ECC generator  402 . ECC generator  402  outputs the clear data for DE, as well as ECC check bits for DE. ECC check bits are preferably stored in one or more reserved (not shown) DRAMs  304 , in a DIMM  302 , which exclusively store ECC check bits.  
         [0032]      FIG. 4   b  illustrates the retrieval of DE from DIMMs  302 - 1 , 2 , 3 , 4 . When coming from (being read from) DIMM  302 - 1 , DE is designated as DEM, indicating that it is being sourced from Memory. DEM is input into ECC generator  402 , generating ECC check bits for DEM. The ECC check bits for DEM and the previously generated/stored ECC check bits for DE are compared by ECC comparator and syndrome generator  404 . If the ECC check bits are not equal (preferably by running them through an Exclusive OR-XOR logic to generate a zero if equal and non-zero if not equal), then a syndrome is generated for DEM. A syndrome is a value that is based on the comparison of the ECC check bits for DEM. This syndrome can then be used to correct a single symbol error and detect a double symbol error in DEM. (Note that while the present invention is described as assuming that only an 8-bit symbol can be corrected, by adding additional ECC check bits, multiple bit errors can also be corrected in an 8-bit or larger symbol.) Assume for illustrative purposes that the data error that resulted in the syndrome generation was from a correctable error in data location ( 0 : 3 ) in DRAM 1   304 - 1  and data location ( 8 : 11 ) in DRAM 1   304 - 2 .  
         [0033]     Referring then again to  FIG. 4   b , ECC matrix  406  uses the syndrome generated by ECC comparator and syndrome generator  404 , along with data DEM, to output corrected data (shown as DE′M) as well as bit steer signals and MC selector signals for ( 0 : 3 ) and ( 8 : 11 ). DE′M includes all data stored in DIMMs  302 - 1 , 2 , 3 , 4 , including corrected and tagged data that came out of data location ( 0 : 3 ) and data location ( 8 : 11 ).  
         [0034]     As will be described and used below, bit steer signals are used to direct DE′M (subsequently identified again as DE′) data back into DIMMs  302 , including the data from ( 0 : 3 ) and ( 8 : 11 ). Likewise, MC selector allows MC  210  to bit steer either the data that was originally stored in ( 0 : 3 ) and ( 8 : 11 ) to a spare DRAM  304 , such as DRAM  304 -spare.  
         [0035]     Referring then to  FIG. 5   a , the corrected data DE′M (which is now designated as DE′ since it is sourced from MC  210 , not from system memory  212 ), is input into ECC generator  402 . ECC generator  402  generates a clear copy of DE′ plus ECC check bits for DE′.  
         [0036]     A byte parser  502  parses DE′ into data components for storage into the appropriate DRAM  304  in the appropriate DIMM  302 . The parsing includes parsing out of DE′( 0 : 3 ) and DE′( 8 : 11 ), which represents the corrected data that was read out as shown in  FIG. 4   b . DE′ is input into a Multiplexer “a” (MUX  504   a ) and a Multiplexer “b” (MUX  504   b ). MUXs  504   a - b  are coupled to DRAM  304 -spare in DIMM  302 - 4 . For exemplary purposes, DRAM  304 -spare is the last DRAM  304  in DIMM  302 - 4 , shown in  FIG. 3 . Alternatively DRAM  304 -spare may be any DRAM  304  in any DIMM  302 .  
         [0037]     If the ECC comparator and syndrome generator  404  (shown in  FIG. 4   b ) previously determined that the error in original data DE was in the left data sub-unit of DRAM 1   304 - 1  (bits designated as DE′( 0 : 3 )) and the left data sub-units of DRAM 2   304 - 2  (bits designated as DE′( 8 : 11 )), then ECC matrix  406  generated bit steer select signals that MC  210  stored for use as shown in  FIG. 5   a . That is, MC  210  sends a bit steer signal  1  to MUX  504   a  that directs DE′( 0 : 3 ) to be stored in DRAM  304 -spare (for example, the left half of DRAM  304 -spare), and a bit signal  2  to MUX  504   b  that directs DE′( 8 : 11 ) to also be stored in DRAM  304 -spare (for example, the right half of DRAM  304 -spare).  
         [0038]     Note that corrected data that is stored in Dram  304 -spare may be stored in either the first partition half or second partition half of DRAM  304 -spare. In addition, while it is easiest for MC  210  to map DRAM  304 -spare into two equal 4-bit halves, and to section error data units into left and right 4-bit halves, alternatively any (preferably) contiguous units can be segregated and stored. Note also that while the present invention has been described using 8-bit DRAMs  304 , it can also be used with other sized DRAMs, including 4-bit DRAMs (DRAMs that store 4 columns of data). For example, if the DIMM uses 4-bit DRAMS, then the left two (upper) bits and the right two (lower) bits are each discrete sub-units capable of being independently stored in either partition of a spare (4-bit) DRAM.  
         [0039]      FIG. 5   b  depicts hardware used in an exemplary preferred embodiment of the present invention for reading data out of a DIMMs  302 , including from a DRAM  304 -spare. Memory controller  210  (now shown in  FIG. 5   b ) sends MC selector signals to a plurality of MUXs  506 . Preferably, pairs of MUXs  506  are associated with a single DRAM  304  shown in  FIG. 3 . For example, MUXs  506 - 1 , 2  are associated with DRAM  304 - 1 , which holds data at bit locations ( 0 : 7 ).  
         [0040]     When reading data out of DIMMs  302 , some of the data will be coming from the DRAM  304 -spare. Continuing with the example above, the data that was originally stored in the primary DRAM 1   304 - 1  in the ( 0 : 3 ) address, (i.e., DE( 0 : 3 )), has now been corrected and stored in DRAM  304 -spare. MC  210  has mapped the new location for DE′M( 0 : 3 ) as being in DRAM  304 -spare, and specifically in a particular row in the bit location of ( 280 : 283 ). Similarly, the data that was originally stored in primary DRAMs  304 - 2  in the ( 8 : 11 ) address (i.e., DE( 8 : 11 )), has now been corrected and stored in bit location ( 284 : 287 ) of DRAM  304 -spare.  
         [0041]     Thus, since MC  210  knows that the data sub-unit DE′( 0 : 3 ) has been stored in DRAM  304 -spare at a location identified as DEMspare( 280 : 283 ), and that the data sub-unit DE′( 8 : 11 ) has been stored in DRAM  304 -spare at a location identified as DEMspare( 284 : 287 ), MC  210  can use MC selector signals to correctly steer out the data sub-units stored in DRAM  304 -spare. Thus, an MC selector signal ( 0 : 3 ) causes DEMspare( 280 : 283 ) to be read out as the replacement for DEM(0:3), and MC selector signal ( 8 : 11 ) causes DEMspare( 284 : 287 ) to be read out as the replacement for DEM( 8 : 11 ). The rest of the MUXs  506  select the DEM corresponding to their originally stored data, as indicated.  
         [0042]     Referring now to  FIG. 6   a , a flow-chart is depicted showing steps taken in a preferred embodiment of the present invention for correcting data stored in a DRAM in a DIMM. After initiator block  602 , data and data-derived ECC bits (DE) are stored in specified DRAMs in the DIMM (block  604 ). The location of each DE is stored in a memory controller (MC) for future retrieval use. Upon the DIMM receiving a request from the MC for data from the DRAMs in the DIMM, the data DE is read out and given the annotation DEM, indicating that it is sourced from memory (block  606 ). New ECC bits are generated for the DEM (block  608 ), and the previously stored ECC bits for DE and the new ECC bits for DEM are compared, preferably using an XOR logic (block  610 ). If the old and new ECC bits are the same (query block  612 ), the XOR logic returns a zero and the process ends (terminator block  618 ). If the old and new ECC bits are different (query block  612 ), then an error has occurred and DE is different from DEM. In such a case, a syndrome is created for DEM, and a corrected version (DE′M) of DEM is generated (block  614 ). As shown in block  616 , a logic determines the bit location of the error in DEM (e.g., an erroneous bit in either the left half of DEM or in the right half of DEM) and sends the memory controller a bit steer signal, which will be used later as shown in  FIG. 6   b.    
         [0043]     With reference then to  FIG. 6   b , after initiator block  620 , the corrected data, now designated DE′ since it is sourced from the memory controller rather than the system memory, is received (block  622 ). ECC bits are generated for DE′ and stored in a dedicated DRAM (a DRAM that is reserved for storing only ECC bits) in the DIMM (block  624 ). As shown in block  626 , DE′ is then parsed into, inter alia, data sub-units designated as DE′( 0 : 3 ) and DE′( 8 : 11 ). The memory controller knows if the error in the original DEM occurred in the ( 0 : 3 ) bit columns or the ( 8 : 11 ) bit columns. Using this information, the memory controller can bit steer the sub-units of DE′, which originally had an error in the corresponding DEM, to the spare DRAM in the DIMM (block  628 ).  
         [0044]     Subsequently, a request for the stored data may be received (block  630 ). As described in block  632 , assuming that DE′( 0 : 3 ) and DE′( 8 : 11 ) had the bit errors, and thus were stored in the spare DRAM in the DIMM, then the DE′( 0 : 3 ) and DE′( 8 : 11 ) data (identified above respectively as DEMspare( 280 : 283 ) and DEMspare( 284 : 287 )) are read out of the spare DRAM instead of the primary DRAMs. The process thus ends at terminator block  634 .  
         [0045]     It should be understood that at least some aspects of the present invention may alternatively be implemented in a program product. Programs defining functions on the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., a floppy diskette, hard disk drive, read/write CD ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore in such signal-bearing media when carrying or encoding computer readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.  
         [0046]     The present invention therefore provides an efficient method and system for taking out of service only a portion of a primary memory sub-module (e.g., a DRAM) in a memory module such as a DIMM, and storing data that was originally stored in or destined for the out of service portion to a spare memory sub-module (such as a spare DRAM). Note that the present invention allows for multiple portions from the same or different DRAMs to be taken out of service. For example, a first portion of a first DRAM and a second portion of a second DRAM may be taken out of service, such that the first and second portions are in the same (same column(s)) area of each DRAM, or the first and second portions may be in different (different column(s)) areas of each DRAM. Alternatively, the first and second portions may be from the same DRAM. While the invention has been shown in a preferred embodiment as taking out a half of each DRAM, the portion being taken out may be other fractions of the DRAM. For example, if the DRAM being used is 16 bits wide, then four bit (column) areas may be taken out of service, or alternatively the out of service area may be six bits or two bits or whatever portion desired. Furthermore, while the present invention has been disclosed using two steer events, the present invention is also able to utilize multiple steer events whose number exceeds two.  
         [0047]     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.