Abstract:
A phase locked loop includes a linear phase detector responsive to a first signal having a predetermined range of frequencies and a second signal for comparing the relative phase of the first signal and the second signal, and a loop gain stabilization circuit coupled between the source of the first signal and the linear phase detector for reducing the magnitude of variations in the loop gain of the phase locked loop over the predetermined range of frequencies of the first signal source. An embodiment of the linear phase detector comprises a harmonic sampler/presteer circuit. The construction and operation of the loop gain stabilization circuit depends on whether the phase locked loop is being used in a frequency multiplying or dividing circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field Of the Invention 
     The present invention relates to phase locked loops comprising linear phase detectors/comparators in general and in particular to a phase locked loop comprising a linear phase comparator with a loop gain stabilization circuit for providing a relatively constant loop gain in such circuits over a wide range of frequencies. 
     2. Description of the Related Art 
     A linear phase comparator in the form of a harmonic sampler can be used advantageously in place of a conventional digital detector in a phase locked loop for dividing and multiplying microwave frequencies in ultra low phase noise microwave frequency synthesizers and other microwave circuits so long as a means, i.e. a frequency presteer circuit, is provided for setting the initial nominal frequency of the voltage controlled oscillator (VCO) in the loop. For example, in applicant&#39;s U.S. patent application, Ser. No. 08/060,755, filed May 12, 1993, entitled ULTRA LOW PHASE NOISE MICROWAVE SYNTHESIZER, and in applicant&#39;s U.S. patent application, Ser. No. 08/051,624, filed Apr. 22, 1993, entitled ULTRA LOW NOISE FREQUENCY DIVIDER/MULTIPLIER there are disclosed frequency multiplier and divider circuits comprising harmonic samplers/presteer circuits in otherwise conventional phase locked loops. 
     As discussed in applicant&#39;s above-identified patent applications, the contents of which are included herein by reference, the intermediate frequency (F if ) output of a harmonic sampler becomes a direct current (dc) level, i.e. null, whenever the frequency F rf  of the high frequency input signal of the sampler is a harmonic of the sampling frequency F s . For this reason a presteer circuit is employed to drive the VCO to a selected initial nominal frequency. Once the presteer circuit has driven the VCO to the selected nominal frequency, i.e. selected harmonic of the sampler, the output of the presteer circuit is disabled and the normal output of the sampler takes over and controls the frequency of the VCO. 
     In most, if not all, phase locked loops it is important that the loop gain of the phase locked loop remain relatively stable. As will be appreciated, whenever the loop gain is not constant over a broad operating frequency range of a VCO, the frequency of the VCO becomes an unpredictable function of the phase difference between the frequency of the VCO and a reference frequency, e.g. the sampling frequency, of a harmonic sampler. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, principle objects of the present invention are a method and apparatus comprising a phase locked loop having a linear phase comparator and a loop gain stabilization circuit for stabilizing the loop gain in the phase locked loop over a predetermined range of frequencies, e.g. 600 MHz to 1200 MHz. 
     Other objects of the present invention are a method and apparatus comprising a phase locked loop having a linear phase comparator and a loop gain stabilization circuit for stabilizing the loop gain in the phase locked loop in a frequency multiplier circuit. 
     Other objects of the present invention are a method and apparatus comprising a phase locked loop having a linear phase comparator and a loop gain stabilization circuit for stabilizing the loop gain in the phase locked loop in a frequency divider circuit. 
     In accordance with the above objects there is provided in an embodiment of the present invention a phase locked loop for use in a frequency multiplier circuit comprising a linear phase detector and loop gain stabilization circuit for restricting variations in the loop gain of the phase locked loop to a predetermined maximum positive and negative variation, e.g. approximately ±1 dB, over a predetermined VCO operating frequency range, e.g., 600 MHz to 1200 MHz. 
     In accordance with the above objects there is provided in another embodiment of the present invention a phase locked loop for use in a frequency divider circuit comprising a linear phase detector and a loop gain stabilization circuit for stabilizing the loop gain by attenuating the high frequency input to the linear phase comparator in the phase locked loop at a rate of approximately 6 dB/octave over a predetermined operating frequency range, e.g., 600 MHz to 1200 MHz. 
     In each of the above-described embodiments the linear phase comparator comprises a harmonic sampler/presteer circuit, a linear multiplier, or the like, and the loop gain stabilization circuit comprises a passive network comprising an inductor, a plurality of resistors and a plurality of capacitors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the accompanying drawings, in which: 
     FIG. 1 is a generalized block diagram of a phase locked loop for use in a multiplier circuit according to the present invention; 
     FIG. 2 is a block diagram of a multiplier circuit comprising a linear phase detector and loop gain stabilization circuit according to the present invention; 
     FIG. 3 is a block diagram of a multiplier circuit comprising a sampler/presteer circuit and loop gain stabilization circuit according to the present invention; 
     FIG. 4 is a schematic of a loop gain stabilization filter network for use in the circuits of FIGS. 2 and 3 according to the present invention; 
     FIG. 5 is a diagram of loop gain error v. frequency in the circuits of FIGS. 2 and 3 according to the present invention; 
     FIG. 6 is a generalized block diagram of a phase locked loop for use in a frequency divider circuit according to the present invention; 
     FIG. 7 is a block diagram of a divider circuit comprising a linear phase comparator and loop gain stabilization circuit according to the present invention; 
     FIG. 8 is a block diagram of a divider circuit similar to the circuit of FIG. 6 comprising a sampler/presteer circuit and loop gain stabilization circuit according to the present invention; 
     FIG. 9 is a block diagram of another embodiment of a divider circuit comprising a linear phase comparator and loop gain stabilization circuit according to the present invention; 
     FIG. 10 is a block diagram of a divider circuit similar to the circuit of FIG. 8 comprising a sampler/presteer circuit and loop gain stabilization circuit according to another embodiment of the present invention; 
     FIG. 11 is a block diagram of a loop gain stabilization filter network for use in the divider circuits of FIGS. 6-9 according to the present invention; and 
     FIG. 12 is a diagram of the loop gain v. frequency in the circuits of FIGS. 6-9 according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, there is provided a phase locked loop designated generally as 1 for use in a multiplier circuit in accordance with the present invention. In the phase locked loop 1 there is provided a linear phase comparator 2, a low pass filter 3, a voltage controlled oscillator (VCO) 4 and a loop gain stabilization filter 5. 
     In operation, the phase of an input signal having a frequency F i  is compared with the phase of the output of the VCO 4 having a frequency F o  in the linear phase comparator 2. The low pass filter 3 filters out the high frequency components from the output of the linear phase comparator 2 for controlling the frequency of the VCO 4. As will be further described below in connection with a description of the present invention relating to its embodiment in multiplying circuits, the filter 5 compensates for variations in the loop gain as a function of frequency which result from the linear phase comparator 2 and the VCO 4. 
     Referring to FIG. 2, there is provided in accordance with the present invention a multiplier circuit designated generally as 10. In the circuit 10 there is provided a linear phase comparator 11 for controlling the frequency F o  of a VCO 16 wherein the frequency F o  is the product of a reference frequency F D  and multiplying factor R. 
     As seen in FIG. 2, one input of the phase comparator 11 is coupled to a source 12 of the reference signal having the frequency F D , e.g. 10 megahertz (MHz), and a multiplier 13 for multiplying the output frequency of the source 12 by the multiplying factor R, wherein R ranges from 60 to 118. The second input of the phase comparator 11 is coupled by means of a feedback loop comprising the VCO 16 designated generally as 14, to the output of the phase comparator 11. 
     In the feedback loop 14 there is provided an operational amplifier circuit designated generally as 15, the VCO 16 and a loop gain stabilization filter network 17, the construction and operation of which will be described below. The output of the phase comparator 11 is coupled to the non-inverting input of an operational amplifier 18 in the circuit 15 and to ground through a load resistor R L . The inverting input of the amplifier 18 is coupled to its output by a series coupled capacitor C and resistor R2 and to ground by means of a resistor R1. 
     In operation, the frequency F o  of the VCO 16 is controlled by the phase difference between the two inputs to the comparator 11. Accordingly, a desired frequency F o , within the range of 600 MHz to 1180 MHz, is obtained by selecting a suitable multiplying factor R within the range 60 to 118. 
     Referring to FIG. 3, there is provided in another embodiment of the present invention a multiplier circuit designated generally as 30 which is substantially identical to the multiplier circuit 10 of FIG. 2 but wherein the linear phase comparator 11 and multiplier 13 are replaced by a linear phase comparator comprising a harmonic sampler/presteer circuit 31. All other circuits are identical to the circuits described above with respect to FIG. 2 and therefore are identified using the same numerical designator used in the circuit of FIG. 2. 
     The sampler/presteer circuit 31 comprises an input for receiving a high frequency signal having a frequency F rf  from the network 17, a sampling input for receiving a sampling signal F s  from the source 12 and an output for providing an intermediate frequency (IF) signal having a frequency F IF . As previously described, the IF signal becomes a null signal whenever the input frequency F rf  is a harmonic of the sampling frequency F s . For this reason, a presteer circuit is required to be used in conjunction with the harmonic sampler. As described in applicant&#39;s co-pending applications Ser. No. 08/060,755 and Ser. No. 08/051,624, the presteer circuit in the circuit 31 operates to drive the VCO to a predetermined nominal frequency. Thereafter, the frequency of the output of the VCO 16 is controlled by the harmonic sampler circuit 31. 
     In operation, the VCO 16 is driven and thereafter locked to a desired selected frequency which is a product of the harmonic number H of the sampler 31 and the frequency F s . For example, with a reference frequency F s  of 10 MHz an output frequency F o  within a range of 600 MHz to 1180 MHz can be obtained by selecting a harmonic number H within a range of 60 to 118. 
     Referring to FIG. 4, the gain stabilization filter network 17 in the multiplying circuits 10 and 30 of FIGS. 2 and 3 comprises a resistor R3, a capacitor C1, an inductor L, a capacitor C2, a capacitor C3 and a resistor R4. One end of the resistor R3 is coupled to an input port 26. The opposite end of the resistor R3 is coupled to one end of the inductor L and to ground through the capacitor C1. The opposite end of the inductor L is coupled to one end of the capacitor C2 and to ground through the capacitor C3. A node between the capacitors C2 and C3 is coupled to ground through the resistor R4 and to an output port 27. The resistors, capacitors and inductor in the circuit 17 have the following typical values: 
     
         R3=71 ohms 
    
     
         R4=51 ohms 
    
     
         C1=19 pf 
    
     
         C2=3 pf 
    
     
         C3=5 pf 
    
     
         L=8.8 nh 
    
     Referring to FIG. 5, there is shown a diagram of the loop gain error KVKφ in decibels (dB) v. frequency over the frequency range of 600 MHz to 1200 MHz for the VCO 16 of the circuits of FIGS. 2 and 3. As seen from the following table and the diagram in FIG. 5, the filter 17 essentially makes the loop gain constant over the range of frequencies of 600 MHz to 1180 MHz of the VCO 16 by providing a compensation above and below 900 MHz which restricts the variation in loop gain as a function of the frequency of the VCO 16 to a range of from -1.15 dB at 600 MHz to 0 at 900 MHz and to +1.31 dB at 1100 MHz and -1.15 dB at 1180 MHz. 
     
                       TABLE 1______________________________________                             dB NORMF        FILT    KV       KV-FILT to 900 MHz______________________________________600      .086    42       3.61    -1.15700      .087    42       3.65    -1.05800      .090    42       3.78    -.75900      .098    42       4.12    0.001000     .113    40       4.52    +.801100     .141    39       4.79    +1.311180     .180    20       3.60    -1.15______________________________________ 
    
     Referring to FIG. 6, there is provided a phase locked loop designated generally as 35 for use in dividing circuits according to the present invention. In the phase locked loop 35 there is provided a linear phase comparator 36, a lowpass filter 37, a VCO 38, a filter 34 and a loop gain stabilization circuit 39. The filter 34 is identical to the loop gain stabilization circuit 39 to make the circuit match the characteristics of a sampler in the same circuit. 
     In operation, the frequency of the VCO is controlled in a conventional manner by the phase difference between the signals applied to the inputs of the phase comparator 36. However, unlike the loop gain stabilization circuit 5 in FIG. 1, the loop gain stabilization circuit 39 is removed from the feedback loop of the loop 35 and placed in series with the reference signal input to the comparator 36. As will be further described below in connection with a description of the present invention relating to its embodiment in dividing circuits, the circuit 39 compensates for variations in the loop gain as a function of the frequency of the reference signal applied to the reference signal input of the comparator 36 by attenuating the reference signal at a rate of 6 dB/octave over a predetermined frequency range thereof, e.g. 600 MHz to 1180 MHz. 
     Referring to FIG. 7, there is provided in accordance with another embodiment of the present invention a divider circuit designated generally as 40. The divider circuit 40 comprises a linear phase comparator 41. One input of the comparator 41, the reference signal input, is coupled to an oscillator 42 by means of a gain stabilization circuit 43, the construction and operation of which will be described below. A second input of the comparator 41, the feedback signal input, is coupled to its output by means of a feedback loop designated generally as 44 comprising an operational amplifier 45, a voltage controlled oscillator 46, a multiplier 47 and a filter 48 which is identical to the filter 43. The filter 48 is provided to make the circuit match the characteristics of the sampler in the same circuit as described below with respect to FIG. 8. The output of the comparator 41 is coupled to the non-inverting input of the amplifier 45 and to ground through a load resistor R L . The inverting input of the amplifier 45 is coupled to ground through a resistor R1 and to its output by means of a resistor R2 in series with a capacitor C. 
     The oscillator 42 is designed to provide a selected frequency F idle  within a range of frequencies of 600 MHz to 1180 MHz. The VCO 46 is provided to output a signal having a frequency F o  which ranges from 8.3 MHz to 50 MHz. The multiplier 47 is provided to multiply the frequency of the VCO 46 by a factor R which ranges from 12 to 96. 
     In operation, the difference in the phase of the signals applied to the inputs of the comparator 41 is used to generate an error signal which is applied to the voltage control input of the VCO 46. In response the frequency of the VCO 46 as multiplied by the multiplier 47 is adjusted to cancel the phase difference between the inputs of the phase detector 41. Thus, for example, by a judicious selection of the output frequency of the oscillator 42 and the multiplying factor R within the ranges specified, as may be accomplished by a suitable programmed computer, the VCO 46 can be made to lock into a desired frequency within the range of from 8.3 MHz to 50 MHz. 
     Referring to FIG. 8, there is provided in accordance with another embodiment of the present invention a divider circuit designated generally as 50 which is identical to the divider circuit of FIG. 7 with the exception that the linear phase comparator 41 and multiplier 47 in the circuit 40 of FIG. 6 are replaced by a linear phase comparator comprising a harmonic sampler/presteer circuit 51. Accordingly, all other components of the circuit 50 bear the same numerical identifier as their corresponding components in the circuit 40 of FIG. 7. 
     The harmonic sampler and presteer circuit 51 of FIG. 8 operates in substantially the same way as the harmonic sampler and presteer circuit 31 of FIG. 3, except that the circuit 51 is used to lock the frequency of the VCO 46 to a selected sampling frequency F s  as distinguished from the selected high frequency F rf  obtained from the VCO 16. For example, the sampling frequency F s  can range from 8.3 MHz to 50 MHz depending on the frequency F idle  selected for the oscillator 42 which, for example, can range from 600 MHz to 1180 MHz and the harmonic number H which, for example, can range from 12 to 96. The actual frequency F idle  and the harmonic number H is selected using a computer program. 
     Referring to FIG. 9, there is provided in another embodiment of the present invention a divider circuit designated generally as 60. The divider circuit 60 is substantially identical to the divider circuit 40 of FIG. 7, except that the input applied to the multiplier 47 is provided by a mixer 61 coupled to the output of the VCO 46 and a source 62 of a reference signal having a pair of selectable frequencies, e.g. 900 MHz and 1000 MHz. As described above with respect to the circuits of FIGS. 7 and 8, the filter 48 is provided to make the circuit match the characteristics of the sampler in the same circuit as described below with respect to FIG. 10. 
     The advantage of using the reference oscillator 62 and mixer 61 is that the output frequency range of the oscillator 46 can be substantially increased from a frequency range of 8.3 MHz to 50 MHz to a frequency range of 908.3 MHz to 983 MHz without increasing the multiplication factor R of the multiplier 47. By keeping the multiplication factor R of the multiplier 47 low, lower noise performance is maintained. 
     Referring to FIG. 10, there is provided in accordance with another embodiment of the present invention a divider circuit designated generally as 70 which is identical to the divider circuit 60 of FIG. 9 except that the linear phase detector 41 and multiplier circuit 47 are replaced by a linear phase comparator comprising a harmonic sampler/presteer circuit 71. 
     The harmonic sampler and presteer circuit 70 of FIG. 10 operates in substantially the same way as the harmonic sampler and presteer circuit 51 of FIG. 8 except that the circuit 70 is used to lock the frequency of the VCO 46 to the frequency F coarse  of the VCO 46 of FIG. 9. 
     Referring to FIG. 11, there is provided in the loop gain stabilization circuit 43, a capacitor C1, a resistor R3, an inductor L, a resistor R4, a capacitor C2, a capacitor C3 and a resistor R5. One end of the capacitor C1 is coupled to an input port 48. The opposite end of the capacitor C1 is coupled to ground through the resistor R3 and to one end of the inductor L. The opposite end of the inductor L is coupled to ground through the resistor R4 in parallel with the capacitor C2 and to one end of the capacitor C3. The opposite end of the capacitor C3 is coupled to ground through the resistor R5 and to an output port 49. The capacitors, resistors and the inductor in the circuit 43 have the following typical values: 
     
         C1=10 pf 
    
     
         C2=3.1 pf 
    
     
         C3=10 pf 
    
     
         R3=180 ohms 
    
     
         R4=180 ohms 
    
     
         R5=50 ohms 
    
     
         L=47 nh 
    
     The open loop gain A OL  of the circuits of FIGS. 8 and 10 comprising the samplers 51 and 71 is given by the following equation: ##EQU1## where F s  =sampling frequency 
     H=harmonic number 
     V IN  =input voltage to the sampler 
     and all other parameters are constant. 
     Equation 1 can be rewritten as follows: 
     
         A.sub.OL =F.sub.s ×H×V.sub.IN ×C         (2) 
    
     where ##EQU2## 
     Substituting equation 3 in equation 2, equation 2 can be rewritten as follows: ##EQU3## 
     Thus, to make the loop gain A OL  constant as F idle  increases, it can be seen that V IN  must decrease as a linear function of F idle  or at a rate of 6 dB/octave. The circuit of FIG. 11 provides the necessary attenuation 15 as shown in FIG. 12. 
     Equation (1) also defines the open loop gain for the linear phase detectors in the circuits of FIGS. 7 and 9, provided the harmonic number H is replaced by the multiplying factor R. 
     While preferred embodiments of the present invention are described above, it is contemplated that numerous modifications may be made thereto for particular applications without departing from the spirit and scope of the present invention. Accordingly, it is intended that the embodiments described be considered only as illustrative of the present invention and that the scope thereof should not be limited thereto but be determined by reference to the claims hereinafter provided.