Abstract:
A switch failure detection device configured to be installed in an electric system including an electric storage device, the switch failure detection device including at least one electronic switch to be connected in a path in which a charging current to the electric storage device and a discharging current from the electric storage device flow, the at least one electronic switch including a first electronic switch, at least one rectifier for passing a discharging current by bypassing the electronic switch when the electronic switch is turned off, the at least one rectifier including a first rectifier being connected parallel to or being parasitic to the first electronic switch such that a forward direction thereof corresponds to a direction in which the discharging current flows, a switch voltage detection circuit configured to detect a voltage drop caused by the at least one electronic switch, and a controller.

Description:
The present application is a Continuation Application of U.S. patent application Ser. No. 13/781,558, filed on Feb. 28, 2013, which is based on and claims priority from Japanese patent application No. 2012-45676, filed on Mar. 1, 2012, the entire contents of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The technology described in this specification relates to detection of failure of a switch configured to shut off charging or discharging currents. 
     BACKGROUND 
     An electric storage device such as a lithium-ion battery may be overcharged or over-discharged due to variations in capacity between cells or a failure of a peripheral device such as a charger and a load. Therefore, a known battery pack may include an overcharge/over-discharge protection function. Such a battery pack may include an electronic switch such as an FET and a monitoring unit. The switch is connected in a current path in which a charging current or a discharging current flows. The monitoring unit is configured to measure a terminal voltage of the electric storage device. If the terminal voltage reaches a predetermined level during charging of the electric storage device, the switch is turned off to shut off the charging current so that the electric storage device is protected against overcharge. 
     A known battery pack including a protection function may have the following configuration. If a voltage between an input and an output of an electronic switch, that is, a voltage drop during charging is large, an abnormal condition in which an on resistance is excessively high due to a failure of the switch is determined. If the abnormal condition is determined, the switch is turned off to disable a battery. 
     In such a battery pack, the switch may not be turned off if a short circuit occurs between the input and the output of the switch or for some reasons. If the switch cannot be turned off, the protection function may not be properly performed. As a result, the electric storage device may be overcharged or over-discharged. Even if an abnormal condition of the switch is detected, the battery cannot be disabled because the switch cannot be turned off. 
     A turn-off problem of the switch may be detected in advance by turning the switch from on to off. However, power supply to a load may be stopped if switch failure detection is performed as such on a discharging current shut-off switch during discharging. If the switch failure detection is performed on a charging current shut-off switch during charging, power supply to the electric storage device may be stopped. 
     SUMMARY 
     A switch failure detection device maybe installed in an electric system including an electric storage device. The switch failure detection device includes at least one electronic switch, at least one rectifier, a switch voltage detection circuit, and a controller. 
     The electronic switch is to be connected in a path in which a charging current to the electric storage device and a discharging current from the electric storage device flow. The electronic switch is switched between on and off. The rectifier is configured to pass a discharging current by bypassing the electronic switch when the electronic switch is turned off. The switch voltage detection circuit is configured to detect a voltage between an input and an output of the electronic switch. 
     The controller is configured to: determine whether the electric storage device is in a discharging state; send an off-command signal to the electronic switch to turn off the electronic switch if the electric storage device is in the discharging state; receive the voltage detected by the switch voltage detection circuit while the off-command signal is sent to the electronic switch; determine an input-output voltage of the electronic switch based on the voltage; determine whether the input-output voltage is lower than a reference voltage; and determine the electronic switch has a turn-off problem in which the electronic switch does not turn off according to the off-command signal if the input-output voltage is lower than the reference voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a battery pack according to an embodiment. 
         FIG. 2  is a flowchart of battery protection process. 
         FIG. 3  is a flowchart of a switch failure detection process. 
         FIG. 4  is a circuit diagram of the battery pack with a charging current shutoff FET turned off. 
     
    
    
     DETAILED DESCRIPTION 
     An embodiment will be described with reference to  FIGS. 1 to 4 . A battery pack  1  includes a secondary battery  2  and a battery protection circuit  3 . The battery pack  1  may be installed in an electric vehicle or a hybrid vehicle and supply power to various devices in the vehicle. The secondary battery  2  is an example of an electric storage device. A capacitor may be used instead of the secondary battery  2 . The battery protection circuit  3  is an example of a switch failure detection device. The battery pack  1  may include a connector for electrically connecting the secondary battery  2  to an external device. 
     Electric Configuration of Battery Pack 
     The secondary battery  2  is a lithium-ion battery and an assembled battery including four cells  2 A connected in series. Alternatively, the secondary battery  2  may include only one cell  2 A. Further alternatively, the secondary battery may include two series-connected cells  2 A, three series-connected cells  2 A, or five or more series-connected cells  2 A. 
     The battery protection circuit  3  includes first to fourth connection terminals T 1  to T 4 , a charging current shutoff FET  31 , a discharging current shutoff FET  32 , and a battery monitoring unit  33 . The secondary battery  2  is connected between the first and the second connection terminals T 1  and T 2 . External devices including a charger  5  and a load  6  are selectively connected between the third and the fourth connection terminals T 3  and T 4  via a selector  7 . 
     The charging current shutoff FET  31  and the discharging current shutoff FET  32  are N-channel MOSFETs including parasitic diodes D 1  and D 2 , respectively. The charging current shutoff FET  31  and the discharging current shutoff FET  32  are examples of switches and rectifiers. The drain of the charging current shutoff FET  31  and that of the discharging current shutoff FET  32  are commonly connected. Namely, the charging current shutoff FET  31  and the discharging current shutoff FET  32  are connected back-to-back. The source and the gate of the charging current shutoff FET  31  are connected to the connection terminal T 3  and the battery monitoring unit  33 , respectively. The source and the gate of the discharging current shutoff FET  32  are connected to the connection terminal T 1  and the battery monitoring unit  33 , respectively. 
     The battery monitoring unit  33  includes a controller  34 , a first voltage detection circuit  35 , and a second voltage detection circuit  36 . The controller  34  includes a central processing unit (CPU)  34 A and a memory  34 B. The memory  34 B stores various programs that are provided for controlling operations of the battery monitoring unit  33 . The CPU  34 A reads out the programs from the memory  34 B and controls the components of the battery monitoring unit  33  according to the programs. The memory  34 B includes RAM and ROM. The medium on which the programs are stored is not limited to RAM. A non-volatile memory such as CD-ROM, hard disk drive, and a flash memory can be used. 
     The first voltage detection circuit  35  is an example of switch voltage detection circuit. The first voltage detection circuit  35  detects a first voltage V 1  between the first and the second connection terminals T 1  and T 2 . The first voltage V 1  is an example of a terminal voltage of the electric storage device. The first voltage detection circuit  35  sends a detection signal corresponding to the first voltage V 1  to the controller  34 . The first voltage V 1  is proportional to a terminal voltage of the secondary battery  2 . The second voltage detection circuit  36  detects a second voltage V 2  between the third and the fourth connection terminals T 3  and T 4 . The second voltage detection circuit  36  sends a detection signal to the controller  34 . The second voltage V 2  is proportional to an output voltage of the charger  5  or a voltage across the load  6 . 
     Controls on Battery Monitoring Unit 
     When the battery protection circuit  3  is turned on, the CPU  34 A starts sending on-command signals to the charging current shutoff FET  31  and the discharging current shutoff FET  32 . The on-command signals are for turning on, or closing, the charging current shutoff FET  31  and the discharging current shutoff FET  32 . The charging current shutoff FET  31  and the discharging current shutoff FET  32  remain turned on while receiving the on-command signals. 
     When the selector  7  is thrown to a charger position and connection between the third connection terminal T 3  and the charger  5  is established, the power is supplied from the charger  5  to the secondary battery  2 . As a result, the secondary battery  2  is charged. When the selector  7  is thrown to a load position and connection between the third connection terminal T 3  and the load  6  is established, the secondary battery  2  starts discharging, and the power is supplied from the secondary battery  2  to the load  6  (see  FIG. 1 ). The CPU  34 A reads out the programs from the memory  34 B and performs a battery protection process illustrated in  FIG. 2  and a switch failure detection process illustrated in  FIG. 3 . 
     Battery Protection Process 
     In the battery protection process, the CPU  34 A continuously or periodically detects the first voltage V 1  based on the detection signal from the first voltage detection circuit  35  (S 1 ). The CPU  34 A determines whether the first voltage V 1  is higher than an overcharge threshold (S 2 ). A preferable level of the overcharge threshold is slightly lower than the first voltage V 1  when the secondary battery  2  is in an overcharged state and slightly higher than the first voltage V 1  when the secondary battery  2  is in an over-discharged state. The overcharge threshold may be defined in advance based on an experiment in which the secondary battery  2  is set in the overcharged state and the first voltage V is measured. 
     If the first voltage V 1  is higher than the overcharge threshold (YES in S 1 ), the CPU  34 A performs an overcharge control step to send an off-command signal to the charging current shutoff FET  31  (S 3 ). The CPU  34 A performs the overcharge control step because the secondary battery may enter the overcharged state. The charging current shutoff FET  31  is turned off, that is, opened, and the charging current from the charger  5  is shut off by the parasitic diode D 1 . This terminates the charge of the secondary battery  2 . Therefore, the secondary battery  2  is less likely to enter the overcharged state. The CPU  34 A returns to step S 1  when the overcharge control step is complete. 
     If the first voltage V 1  is lower than an overcharge threshold (NO in S 2 ), the CPU  34 A determines whether the first voltage V 1  is lower than the over-discharge threshold (S 4 ). The over-discharge threshold may be defined in advance based on an experiment in which the secondary battery  2  is set in the over-discharged state and the first voltage V is measured. 
     If the first voltage V 1  is lower than the over-discharge threshold (YES in S 4 ), the CPU  34 A performs an over-discharge control step to send an off-command signal to the discharging current shutoff FET  32  (S 5 ). The CPU  34 A performs the over-discharge control step because the secondary battery may enter the over-discharged state. The discharging current shutoff FET  32  is turned off and the discharging current from the secondary battery  2  is shut off by the parasitic diode D 2 . This terminates the discharge of the secondary battery  2 . Therefore, the secondary battery  2  is less likely to enter the over-discharged state. The CPU  34 A returns to step S 1  when the over-discharge control step is complete. 
     If the first voltage V 1  is higher than the over-discharge threshold (NO in S 4 ), the CPU  34 A returns to step S 1 . In this case, the CPU  34 A continues sending the on-command signals to the charging current shutoff FET  31  and the discharging current shutoff FET  32 . 
     Switch Failure Detection Process 
     The CPU  34 A executes the switch failure detection process illustrated in  FIG. 3  if a specific condition is satisfied while the on-command signals are sent to the charging current shutoff FET  31  and the discharging current shutoff FET  32 . The specific condition may be power-up of the vehicle or predetermined elapsed time since the previous switch failure detection process. 
     The CPU  34 A determines whether the secondary battery  2  is in the discharging state (S 11 ). The CPU  34 A may determine the state of the secondary battery  2  based on an instruction signal from an engine control unit (ECU, not illustrated) or the charger  5 . The discharging state includes a state in which the secondary battery  2  outputs a small current such as a dark current after the load  6  is disconnected. The current protection circuit  3  may include a current sensor to detect the discharging current. With this configuration, the current protection circuit  3  may determine the discharging state based on the current, more specifically, a direction of current, detected by the current sensor. 
     Switch Failure Detection Process for Charging Current Shutoff FET  31   
     If the secondary battery  2  is in the discharging state (YES in S 11 ), the CPU  34 A detects a first on voltage VON 1  between the first connection terminal T 1  and the third connection terminal T 3  (S 12 ). The on voltage VON 1  is an example of a terminal voltage. Specifically, the on voltage VON 1  is a voltage drop between the FETs  31  and  32  while the on-command signals are sent to the FETs  31  and  32 . In this embodiment, a voltage difference between the first voltage V 1  and the second voltage V 2  is calculated based on the detection signals from the first voltage detection circuit  35  and the second voltage detection circuit  36 , and defined as the on voltage VON 1 . 
     The CPU  34  determines whether the on voltage VON 1  is lower than a first threshold TH 1  (S 13 ). The first threshold TH 1  is an example of a second reference value. A preferable level of the first threshold TH 1  is slightly higher than the on voltage VON 1  that is detected when the voltage detection circuits  35  and  36  and the FETs  31  and  32  are not defective and able to perform proper operations. 
     If the on voltage VON 1  is lower than the first threshold TH 1  (YES in S 13 ), the CPU  34 A sends the off-command signal to the charging current shutoff FET  31  to turn off the charging current shutoff FET  31  (S 14 ). The CPU  34 A turns off the charging current shutoff FET  31  because the voltage detection circuits  35  and  36  and the FETs  31  and  32  are in conditions to perform proper operations if the on voltage VON 1  is lower than the first threshold TH 1 . As illustrated in  FIG. 4 , a forward direction of the parasitic diode D 1  corresponds to a direction in which a discharging current I flows. Therefore, the discharging current I continues flowing into the load  6  via the parasitic diode D 1  after the charging current shutoff FET  31  is turned off. 
     The CPU  34 A detects a first off voltage VOFF 1  between the first connection terminal T 1  and the second connection terminal T 3  (S 15 ). The off voltage VOFF 1  is an example of a voltage between an input and an output of an electronic switch. Specifically, the off voltage VOFF 1  is a voltage drop between the FETs  31  and  32  during sending of the off-command signal to the charging current shutoff FET  31  and the on-command signal to the discharging current shutoff FET  32 . In this embodiment, a voltage difference between the first voltage V 1  and the second voltage V 2  is calculated based on the detection signals from the first voltage detection circuit  35  and the second voltage detection circuit  36 , and defined as the off voltage VOFF 1 . The first voltage detection circuit  35  and the second voltage detection circuit  36  are examples of a switch voltage detection circuit. 
     The CPU  34 A sends the on-command signal to the charging current shutoff FET  31  to turn the charging current shutoff FET  31  back on (S 16 ). A preferable period in which the off-command signal is sent to the charging current shutoff FET  31  is several milliseconds or as short as possible. By turning off the charging current shutoff FET  31 , instability in power supply to the load  6  can be reduced. 
     The CPU  34 A determines whether a first on-off voltage difference ΔV 1  is lower than a second threshold TH 2  (S 17 ). The on-off voltage difference ΔV 1  is an example of an input-output voltage determined by a controller based on a voltage detected by the switch voltage detection circuit. Specifically, the on-off voltage difference ΔV 1  is a voltage difference between the on voltage VON 1  and the off voltage VOFF 1 . The second threshold TH 2  is an example of a first reference voltage. A preferable level of the second threshold TH 2  slightly lower than the voltage difference between the on voltage VON 1  and the off voltage VOFF 1  detected in advance when the FETs  31  and  32  are not defective and able to perform proper operations. 
     If the on-off voltage difference ΔV 1  is lower than the second threshold TH 2  (YES in S 17 ), the CPU  34 A executes first error processing (S 18 ). The CPU  34 A executes the first error processing because the charging current shutoff FET  31  has a turn-off problem in which the charging current shutoff FET  31  does not turn off according to the off-command signal due to a short circuit between input and output or for some reason. In the first error processing, the CPU  34  issues a notification about the turn-off problem of the charging current shutoff FET  31  to the external devices including the ECU. When the first error processing is complete, the CPU  34  terminates the switch failure detection process. If the on-off voltage difference ΔV 1  is higher than the second threshold TH 2  (NO in S 17 ), the CPU  34 A terminates the switch failure detection process without executing the first error processing. 
     If the on voltage VON 1  is higher than the first threshold TH 1  (NO in S 13 ), the CPU  34 A executes second error processing (S 19 ). The CPU  34 A executes the second error processing because at least one of the circuits  35  and  36  is defective or at least one of the FETs  31  and  32  is defective and thus the switch failure detection process may not be properly executable. In the second error processing, the CPU  34  issues a notification about the failure of at least one of the circuits  35  and  36  or at least one of the FETs  31  and  32  to the ECU. When the second error processing is complete, the CPU  34  terminates the switch failure detection process. 
     Switch Failure Detection Process for Discharging Current Shutoff FET  32   
     If the secondary battery  2  is not in the discharging state, that is, in the charging state (NO in S 11 ), the CPU  34 A detects an on voltage VON 2  between the first connection terminal T 1  and the third connection terminal T 3  (S 20 ). The on voltage VON 2  is an example of a terminal voltage. Specifically, the on voltage VON 2  is a voltage drop between the FETs  31  and  32  while the on-command signals are sent to the FETs  31  and  32 . In this embodiment, a voltage difference between the first voltage V 1  and the second voltage V 2  is calculated based on the detection signals from the first voltage detection circuit  35  and the second voltage detection circuit  36 , and defined as the on voltage VON 2 . 
     The CPU  34 A determines whether the on voltage VON 2  is lower than a third threshold TH 3  (S 21 ) to determine whether the switch failure detection process is properly executable on the discharging current shutoff FET  32 . The third threshold TH 3  is an example of a second reference voltage. A preferable level of the third threshold TH 3  is slightly higher than the on voltage VON 2  that is detected when the voltage detection circuits  35  and  36  and the FETs  31  and  32  are not defective and able to perform proper operations. 
     If the on voltage VON 2  is lower than the third threshold TH 3  (YES in S 21 ), the CPU  34 A sends the off-command signal to the discharging current shutoff FET  32  to turn off the discharging current shutoff FET  32  (S 22 ). The CPU  34 A turns off the discharging current shutoff FET  32  because the switch failure detection process is properly executable if the on voltage VON 2  is lower than the third threshold TH 3 . A forward direction of the parasitic diode D 2  corresponds to a direction in which a charging current flows. Therefore, the charging current continues flowing into the second battery  2  via the parasitic diode D 2  after the discharging current shutoff FET  32  is turned off. 
     The CPU  34 A detects an off voltage VOFF 2  between the first connection terminal T 1  and the third connection terminal T 3  (S 23 ). The off voltage VOFF 2  is an example of a voltage between an input and an output of an electronic switch. Specifically, the off voltage VOFF 2  is a voltage drop between the FETs  31  and  32  during sending of the on-command signal to the charging current shutoff FET  31  and the off-command signal to the discharging current shutoff FET  32 . In this embodiment, a voltage difference between the first voltage V 2  and the second voltage V 2  is calculated based on the detection signals from the first voltage detection circuit  35  and the second voltage detection circuit  36 , and defined as the off voltage VOFF 2 . 
     The CPU  34 A sends the on-command signal to the discharging current shutoff FET  32  to turn the discharging current shutoff FET  32  back on (S 24 ). A preferable period in which the off-command signal is sent to the discharging current shutoff FET  32  is several milliseconds or as short as possible. By turning off the discharging current shutoff FET  32 , instability in charging of the second battery  2  can be reduced. 
     The CPU  34 A determines whether a second on-off voltage difference ΔV 2  is lower than a fourth threshold TH 4  (S 25 ). The on-off voltage difference ΔV 2  is an example of an input-output voltage determined by a controller based on a voltage detected by the switch voltage detection circuit. Specifically, the on-off voltage difference ΔV 2  is a voltage difference between the on voltage VON 2  and the off voltage VOFF 2 . The fourth threshold TH 4  is an example of a first reference value. A preferable level of the fourth threshold TH 4  slightly lower than the voltage difference between the on voltage VON 2  and the off voltage VOFF 2  detected in advance when the FETs  31  and  32  are not defective and able to perform proper operations. 
     If the on-off voltage difference ΔV 2  is lower than the fourth threshold TH 4  (YES in S 25 ), the CPU  34 A executes third error processing (S 26 ). The CPU  34 A executes the third error processing because the discharging current shutoff FET  32  may have a turn-off problem in which the discharging current shutoff FET  32  does not turn off according to the off-command signal if the on-off voltage difference ΔV 2  is lower than the fourth threshold TH 4 . In the third error processing, the CPU  34  issues a notification about the turn-off problem of the discharging current shutoff FET  32  to the external devices including the ECU. When the third error processing is complete, the CPU  34  terminates the switch failure detection process. If the on-off voltage difference ΔV 2  is higher than the fourth threshold TH 4  (NO in S 25 ), the CPU  34 A terminates the switch failure detection process without executing the third error processing. 
     If the on voltage VON 2  is higher than the third threshold TH 3  (NO in S 21 ), the CPU  34 A executes the second error processing (S 19 ), and terminates the switch failure detection process. The CPU  34 A executes the second error processing because the switch failure detection process cannot be properly performed. 
     In this embodiment, the turn-off problem is determined if the detected on-off voltage difference ΔV 1  is lower than the second threshold TH 2  under the condition that the off-command signal is sent to the charging current shutoff FET  31  while the second battery  2  is in the discharging state. The discharging current I from the secondary battery  2  continues flowing into the load  6  via the parasitic diode D 1  after the charging current shutoff FET  31  is turned off. Therefore, the turn-off problem of the charging current shutoff FET  31  can be detected while the power supply to the load  6  is maintained. 
     The turn-off problem is also determined if the detected on-off voltage difference ΔV 2  is lower than the fourth threshold TH 4  under the condition that the off-command signal is sent to the discharging current shutoff FET  32  while the second battery  2  is in the charging state. The charging current from the charger  5  continues flowing into the secondary battery  2  via the parasitic diode D 2  after the discharging current shutoff FET  32  is turned off. Therefore, the turn-off problem of the discharging current shutoff FET  32  can be detected while the charging of the secondary battery  2  by the charger  5  is maintained. The switch failure detection process is performed in both cases in which the secondary battery  2  is in the charging state and in the discharging state by controlling the FETs  31  and  32 . In comparison to a configuration in which the FETs  31  and  32  are connected in different paths, the number of conductive lines or monitoring devices can be reduced. Namely, the configuration of this embodiment is simpler. 
     If the on-off voltage differences ΔV 1  and ΔV 2  are lower than the respective thresholds TH 2  and TH 4 , the turn-off problem is determined. In comparison to a configuration in which the turn-off problem is determined if the off voltage VOFF 1  or VOFF 2  is lower than a threshold, accuracy in detection of the turn-off problem is less likely to be reduced even the on-resistance of the FET  31  or  32  varies when the FET  31  or  32  becomes defective. 
     If the FET  31  or  32  becomes defective and the on-resistance thereof increases or the voltage detection circuit  35  or  36  becomes defective, the turn-off problem may not be properly detected. In this embodiment, the switch failure detection process is executed if the on voltage VON 1  or VON 2  is lower than the corresponding first threshold TH 1  or TH 3 . Therefore, the switch failure detection process is less likely to be executed in the condition that the turn-off problem is not properly detected. 
     &lt;Other Embodiments&gt; 
     The scope of the present invention is not limited to the above embodiment. The following embodiments are also included in the scope of the technologies described herein. 
     The controller  34  may include a plurality of CPUs or a hardware circuit such as an application specific integrated circuit (ASIC). Alternatively, the controller  34  may include both hardware circuit and CPU. At least two of the overcharge control step, the over-discharge control step, the determination of the state, the sending of the off-command signal, the determination of proper execution of the switch failure detection process, and the determination of the turn-off problem may be performed by different CPUs or hardware circuits. The sequence in which the above operations are performed may be altered. 
     The switches may be bipolar transistors, relays, or any types of switches that do not include parasitic diodes. The rectifiers may be diodes or diode-connected transistors. An output of one of the diode-connected transistors is connected to an input of another of the diode-connected transistors. However, the embodiment described earlier can perform the switch failure detection process using existing components without additional components. 
     The controller  34  may be configured to determine whether the switch failure detection process is properly executable based on a voltage of one of the cells or voltages of the cells in the secondary battery  2 . 
     The controller may be configured to execute the switch failure detection process for only one of the charging current shutoff FET  31  and the discharging current shutoff FET  32 . 
     The input-output voltage may be the off voltage VOFF 1  or the off voltage VOFF 2 .