Abstract:
A static RAM which features an inclusion of a word line driving circuit shared by all the memory cells in the static RAM is disclosed. The static RAM is comprised of a plurality of four-transistor memory cells arranged in an array. Each of the memory cells includes first and second FETs respectively coupled to bit lines and controlled by word line potential. Further, each of the memory cells further comprises third and fourth cross-coupled FETs respectively coupled in series with the first and second FETs and forming a circuit having two stable states. The word line driving circuit reflects a stable state potential change of each of the plurality of memory cells, and controls an output voltage thereof which is applied to the plurality of memory cells in order to maintain the stable state potential in each of the plurality of memory cells.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a static RAM (random access memory) for use in digital computer systems. More specifically, the present invention relates to a static RAM which features an inclusion of improved word line driving circuitry which is shared by all the memory cells provided in the RAM. The memory cell comprises four MOSFETs (metal oxide semiconductor field effect transistors) which have no load. 
     2. Description of the Related Art 
     Memory cells used in digital information processing systems are generally classified into two types: one is dynamic memory cells and the other is static memory cells. The static memory is able to retain the binary data stored therein as long as power is applied thereto. That is, the static memory cell requires no overhead circuitry for periodical refresh as do the dynamic memory cell. Although the static RAM features high speed of memory access time, i.e., the time required to store and/or retrieve a particular bit(s) in the memory array, the area-efficiency of the memory array is poor relative to the dynamic RAM. That is, the number of stored data bits per unit area is one of the key design criteria that determine the overall storage capacity and hence the memory cost per bit. In order to improve the area-efficiency of a static RAM, a four-transistor having no load has been proposed as mentioned below. 
     Before turning to the present invention, it is deemed advantageous to briefly describe conventional static RAMS with reference to FIG. 1, which is provided with four-transistor memory cells without any load and is disclosed in U.S. Pat. No. 4,796,227. 
     As shown in FIG. 1, a memory cell  10  includes a pair of cross-coupled transistors  12  and  14  comprising a circuit having two stable states. The selected state is retained by charge or potential on the gates of the transistors  12  and  14 . The memory cell  10  further includes two bit line coupling transistors  16  and  18 . The channel types of the transistors  12  and  14  are opposite to those of the transistors  16  and  18 . That is, in the case where the transistors  12  and  14  are n-channel types as shown in FIG. 1, the transistors  16  and  18  are p-channel types and vice versa. The sources of the transistors  12  and  14  are grounded, and the drains thereof are respectively coupled to the drains of the transistors  16  and  18 . The gates of the transistors  12  and  14  are respectively coupled to the drains of the transistors  14  and  12 . On the other hand, the sources of the transistors  16  and  18  are respectively coupled to bit lines BL 0  and BL 1 , and the gates thereof are both coupled to a word line WL 1 . 
     For the convenience of simplifying the descriptions, it is assumed that the memory cell  10  is in a standby mode (viz., the memory cell  10  is not being read or written). Further, assuming that the potentials at nodes  20  and  22  are respectively high and low, which indicates that the memory cell  10  stores one of two binary data (vis., logic “1” or “0”). In the standby mode, the potential on the bit lines BL 0  and BL 1  is at Vdd, and a bias voltage is applied to the word select line WL 1 . Under the above-mentioned assumption, only the transistor  12  is in a conducting state, and the other transistors  14 ,  16 , and  18  are in non-conducting states. More specifically, the transistors  14 ,  16 , and  18  are not in a fully non-conducting state, and a bias potential is applied to the word select line WL 1  which is sufficient to cause small currents I 3  and I OFF-P  to flow through the transistors  16  and  18 , respectively. The small current I OFF-P  is used to compensate for a leak current I OFF-N  flowing through the transistor  14 , which would otherwise result in a loss of charge (vis., high potential) at the node  20 . In the above, since the transistor  12  is assumed to be conducting, the current I 3 , flowing through the transistor  16 , which in the ideal case, is equal to the current I OFF-P , is wasted. However, the current I 3  is very small, the overall power dissipation of the memory cell  10  is not significantly effected. 
     On the contrary, if the potentials on the nodes  20  and  22  are respectively low and high, the memory cell  10  stores the other binary information. In this case, it is understood that the leak current flowing through the transistor  12  should be compensated for in the same manner as mentioned above. 
     The bias current I 3  is set with the aid of two “current mirror” circuits. The combination of transistors  24  and  16  forms a first current mirror circuit wherein the load current I 3  is proportional to a current I 2  in a bias circuit  26  times a geometric width ratio which is proportional to the ratio of the widths of the channels of the transistors  24  and  16 . On the other hand, transistors  28  and  30  form a second current mirror circuit in which the current I 2  is proportional to a current I 1  applied from a constant current source (not shown) times a second geometric width ratio which is proportional to the ratio of the widths of the channels of the transistors  28  and  30 . Accordingly, the current I OFF-P , which is ideally equal to the current I 3 , is able to maintain the potential on the node  20  by compensating for the leak current I OFF-N . 
     During the standby mode, each of the bit lines BL 0  and BL 1  is at Vdd as mentioned above. Further, in this mode, there are no reading and writing operations, and AND gate  32  issues no coincidence signal in order that a transistor  34  is conducting and a transistor  36  is non-conducting. Accordingly, the bias voltage continues to be applied to the memory cell  10  by way of the word line WL 1 . The AND gate  32  and the transistors  34  and  36  form a switch. 
     To read the memory cell  10 , the potential on the word line WL 1  is lowered to ground in response to the change of on-and-off state of the transistors  34  and  36 , which is caused by the coincidence issued from the AND gate  32 . Accordingly, the transistors  16  and  18  are brought into conducting state, which exhibits a potential difference on the bit lines BL 0  and BL 1 . This potential difference is detected using a sense amplifier (not shown) and hence, the binary data stored in the memory cell  10  is read. 
     On the other hand, to change the state of the memory cell  10  (viz., the transistors  12  and  14  are respectively turned off and on). the potential on the word the WL 1  is lowered to ground as just mentioned above. Thereafter, a low signal is applied through the transistor  18  to turn off the transistor  12  whose gate is coupled to the node  20 . 
     With the arrangement shown in FIG. 1, the constant current source (not shown) providing the current I 1  and its associated diode connected transistor  28  are shared by all of the memory cells. As a result, the prior art of FIG. 1 has encountered the problem that the peripheral circuitry of the memory cells undesirably occupies a considerable area on the chip. This is because the transistors  24 ,  30 ,  34 , and  36  and the AND gate  32  should be provided for each of the word lines. In view of the ever-increasing demand for increase in the memory capacity of static RAM up to hundreds of thousands and more, it is highly preferable to reduce the area occupied by the peripheral circuitry of the memory cells. Further, the current is applied to the memory cell which comprises n-channel transistors  12 , and  14  having large temperature-depending characteristics. Therefore, the large currents are inevitably needed when the memory chip is placed in high temperature environments because the current applied to each of the memory cells should be previously set to cover the condition of low ambient temperature. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present to provide a static RAM featuring high area-efficiency, i.e., enabling it to increase the number of stored data bits per unit area in order to increase the overall storage capacity and hence to decrease the memory cost per bit. 
     Another object of the present invention is to provide a static RAM featuring low power consumption during the standby mode. 
     Still another object of the present invention is to provide improved word line driving circuitry for use in a static RAM, which is able to realize high area-efficiency thereby increasing the overall storage capacity and hence to decrease the memory cost per bit. 
     Still another object of the present invention is to provide improved word line driving circuitry for use in a static RAM, which enables low power dissipation during the standby mode. 
     In brief, these objects are achieved by a static RAM which features an inclusion of a word line driving circuit shared by all the memory cells in the static RAM is disclosed. The static RAM is comprised of a plurality of four-transistor memory cells arranged in an array. Each of the memory cells includes first and second FETs respectively coupled to bit lines and controlled by word line potential. Further, each of the memory cells further comprises third and fourth cross-coupled FETs respectively coupled in series with the first and second FETs and forming a circuit having two stable states. The word line driving circuit reflects a stable state potential change of each of the plurality of memory cells, and controls a voltage on a word line extending to the plurality of memory cells in order to maintain the stable state potential in each of the plurality of memory cells. 
     One aspect of the present invention resides in a state random access memory comprising: a plurality of four-transistor memory cells arranged in an array, each of the memory cells comprising first and second field effect transistors respectively coupled to bit lines and controlled by word line potential, each of the memory cells further comprising third and fourth cross-coupled field effect transistors respectively coupled in series with the first and second field effect transistors and forming a circuit having two stable states; and a word line driving circuit shared by the plurality of our-transistor memory cells, the word line driving circuit reflecting a stable state potential change of each of the plurality of memory cells, and controlling a voltage on a word line extending to the plurality of memory cells in order to maintain the stable state potential in each of the plurality of memory cells. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will become more clearly appreciated from the following description taken in conjunction with the accompanying drawings in which like elements are denoted by like reference numerals and in which: 
     FIG. 1 is a diagram showing a conventional four-transistor memory cell together with the word line driving circuit, having been referred to in the opening paragraphs; 
     FIG. 2 is a diagram schematically showing an overall arrangement of a memory chip to which the present invention is applied; 
     FIG. 3 is a diagram showing a first embodiment of the present invention; 
     FIG. 4 is a diagram showing a second embodiment of the present invention; and 
     FIG. 5 is a diagram showing a third embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A first embodiment of the present invention will be described with reference to FIGS. 2 and 3. 
     FIG. 2 is a diagram schematically showing an overall arrangement of a memory chip to which the present invention is applied. Generally speaking, the present invention resides in a word line driving circuit  50  which outputs a word line voltage V WD  which is applied to a plurality of memory cells iva word-enable switches provided in a row decoder  52 . A memory cell array  54  consists of individual memory cells arranged in an array of horizontal rows and vertical columns. Each cell is capable of storing one bit of binary information. 
     As is well known in the art, each memory cell shares a common connection with the other cells in the same row, and another common connection with the other cells in the same column. To access a particular memory cell, i.e., a particular data bit in the memory cell array  54 , the corresponding bit and word lines respectively extending from a column decoder  56  and the row decoder  52  must be activated (selected). Once a memory cell (or a group of memory cells) is selected in this fashion, a data read and/or data write operation may be performed on the selected single bit or multiple bits on a particular row. The column decoder  56  serves the double duties of selecting the particular column and routing the corresponding data content in a selected row to the output. 
     The present invention is concerned with the word line voltage control during the standby mode. Accordingly, the data writing and reading will not be given for the sake of simplifying the instant disclosure because these operations may be identical with the prior art of FIG.  1  and have been discussed in the opening paragraphs. 
     Referring to FIG. 3, there is shown in detail the word line driving circuit  50  together with part of the row decoder  40 , and a memory cell  10 ′. It is to be noted that the word line driving circuit  50  is shared by all the memory cells provided in a chip by way of switches  39  in the row decoder  40 . The memory cell  10 ′ and the switch  39  shown in FIG. 3 are substantially identical with those shown in FIG.  1 . However, it is to be noted that an output line  51  of the word line driving circuit  50  extends to all the switches in the row decoder. Therefore, the components already referred to in connection with FIG. 1 are labeled same reference numerals and the descriptions thereof will be omitted for the sake of simplifying the instant disclosure except for becoming necessary in context. 
     As in the case described in the opening paragraphs, it is assumed that the nodes  20  and  22  exhibit respectively high and low potential. Thus, in order to maintain the high potential at the node  20 , it is necessary to supply the leak current I OFF-P  to replenish the leak current I OFF-N . 
     As mentioned above, a memory chip is provided with a very large number of memory cells and as such, it is not practically possible to fabricate the transistors of all the on-chip memory cells so as to exhibit the same leak currents. As is known in the art, the threshold voltage of a MOSFET depends strongly on the gate length of the transistor. More specifically, as the channel length becomes shorter, the threshold voltage is lowered with the result of increase in the leak current. However, when the memory chip is designed, it might be possible to predict the upper and lower limits of scatter in the leak currents of the transistors of all the on-chip memory cells. The upper limit of leak current among the n-channel transistors is designated by I OFF-N(MAX) , and the lower limit of leak current among the p-channel transistors is designated by I OFF-P(MIN) . 
     The word line driving circuit  50  comprises a monitor circuit  60 , a differential amplifier  62 , a p-channel transistor  64 , and an n-channel transistor  66 . The monitor circuit  60  consists of a p-channel transistor  68  and an n-channel transistor  70 , which are coupled in series as the p- and n-channel transistors in each memory cell. During the standby mode, the transistors  64  and  66  are respectively retained on and off (vis., no leak current compensation is not required), and hence, the voltage V WD  on an output line  51  extending to the word line WL  1  is at Vdd. 
     Assuming that the leak currents of the transistors  68  and  70  are represented by MI OFF-P  and MI OFF-N . In order to successfully compensate for each of all the leak currents flowing through the cross-coupled transistors of the on-chip memory cells, the following relationships should be satisfied. 
     
       
         MI OFF-N ≧I OFF-N(MAX)    (1)  
       
     
     
       
         MI OFF-P ≧I OFF-P(MIN)    (2)  
       
     
     In this case, although it appears to be somewhat difficult in practice, it is preferable that MI OFF-N  is equal to I OFF-N(MAX)  and MI OFF-P  is equal to I OFF-P(MIN) . 
     For the convenience of description, it is assumed that the leak current I OFF-N  of the transistor  14  is I OFF-N(MAX) . When the leak current I OFF-N  increases due to the rise of the ambient temperature, the current MI OFF-N  in the monitor current  60  also increases whereby the potential at a node  72  between the drains of the transistors  68  and  70  is lowered. In the case where the potential at the node  72  is lowered below a reference voltage V REF , the output of the differential amplifier  62  is lowered such as to render the transistor  64  partially non-conducting and the transistor  66  partially conducting. Thus, the voltage V WD  on the output line  51  (and hence the voltage on the word line WL 1 ) is slightly lowered and hence, the current I OFF-P  increases in order to replenish the charge at the node  20 . On the other hand, the lowering of the voltage V WP , which is applied to the gate of the transistor  68 , increases the current MI OFF-P  flowing through the transistor  68  and accordingly, the voltage at the node  72  is raised. When this negative feedback causes the potential at the node  72  to exceed the reference voltage V REF , the output of the differential amplifier  62  causes the voltage V WD  to equal the power potential Vdd. When the potential at the node  72  is again lowered below the reference voltage V REF , the above-mentioned feedback operation is iterated in order to maintain the bit information stored in the memory cell  10 ′ by way of replenishing the high voltage at the node  20 . 
     The reference voltage V REF  is determined considering what voltage at the node  72  appropriately decreases the voltage V WD  on the line  51  so as to compensate for the leak current I OFF-N . 
     In the above, the word line driving circuit  50  utilizes the differential amplifier  62 . However, as an alternative, a comparator may be used in place of the differential amplifier  62 . 
     Referring to FIG. 4, there is shown a word line driving circuit  50 ′ according to a second embodiment of the present invention. The driving circuit  50 ′ differs from the counterpart  50  shown in FIG. 3 as follows. First, a plurality of transistors  70 - 1  to  70 -n, which are typically identical with one another, are provided in place of the single transistor  70 . Second, a capacitor  80  is added between the output of the word line driving circuit  50 ′ and ground. Third, one or more than two buffers (two are shown in this particular case which is denoted by  82  and  84 ) are newly provided between the gate of the transistor  64  and the output of the differential amplifier  62  in order to amplify a current applied to the gate of the transistor  64 . Other than this, the word line driving circuit  50 ′ is substantially identical with the counterpart  50  of the first embodiment. 
     The transistors  70 - 1  and  70 -n are provided so as to rapidly lower the potential at the node  72  when the temperature of the memory chip changes due to the chip&#39;s ambient temperature. More specifically, it is necessary to lower the voltage at the node  72  faster than the voltage, at the high node of a memory cell, which is most rapidly lowered among all the memory cells of a chip. 
     The capacitor  80  is provided such as to prevent the voltage V WD  from been temporarily lowered when a large current flows through the word line when the word line is selected. 
     The word line driving circuit  50 ′ is shared by all the memory cells on the chip and this, the transistor  64  is required to flow a large current therethrough. Therefore, the transistor  64  is fabricated such that the channel length is relatively large. If the differential amplifier  62  is fabricated to rapidly bring the transistor  64  into the partial non-conducting state, the channel length of the differential amplifier  62  should also be long. In such a case, the chip area-efficiency is undesirably reduced with the result of raising fabrication cost. In order to avoid this problem, the buffers  82  and  84  are provided so as to amplify the current applied to the gate of the transistor  64 . 
     The above mentioned three modifications of the second embodiment relative to the first embodiment can be sued independently. That is, these modifications are optional and as such, one or two thereof can be omitted depending on the actual application. 
     Referring to FIG. 5, there is shown a word line driving circuit  50 ″ according to a third embodiment of the present invention. The driving circuit  50 ″ differs from the counterpart  50  shown in FIG. 3 in terms of two points. One is that a plurality of transistors  70 - 1  to  70 -n are provided in place of the single transistor  70  as in the second embodiment. This modification has been referred to in connection with FIG.  3  and thus, further descriptions thereof will not be given. The other is that another differential amplifier  90  is added such that one input thereof is coupled to the drains of the transistor  68  and the transistors  70 - 1  to  70 -n (vis., the node  72 ), and the other input thereof is supplied with another reference voltage V REF ′. This reference voltage V REF ′ is set higher than V REF . The values of V REF  and V REF ′ are determined as follows. That is, when the voltage at the node  72  is lowered below V REF , the transistor  64  is in the non-conducting state and the transistor  66  becomes partially conductive thereby slightly lowering the voltage V WD . On the other hand, when the voltage at the node  72  is between V REF  and V REF ′, both the transistors  64  and  66  are in the non-conducting state. Further, when the voltage at the node  72  is higher than both V REF  and V REF ′, the transistor  64  is in the partially conducting state and the transistor  66  is in the non-conducting state. Therefore, it is possible to avoid the case where both the transistors  64  and  66  are rendered conductive at the same time and the large current flows to ground by way of the transistors  64  and  66 . In the above, the plurality of transistors  70 - 1  to  70 -n may be replaced with the single transistor  70 . 
     It will be understood that the above disclosure is representative of three possible embodiments of the present invention and that the concept on which the invention is based is not specifically limited thereto.