Abstract:
The present invention relates to a nonvolatile memory device, and more specifically, to a programmable nonvolatile logic switch memory (register) device using a resistive memory device. The programmable nonvolatile register uses a logic switch or a nonvolatile resistive memory device whose resistive state can be set by flowing a controlled current through it.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a nonvolatile memory device, and more specifically, to a programmable nonvolatile logic switch memory (register) using a resistive memory device. 
     2. Description of the Prior Art 
     Generally, nonvolatile memory such as magnetic memory and phase change memory (PCM) has a data processing speed similar to that of volatile RAM (Random Access Memory). When power is off, data of the nonvolatile memory are preserved. 
       FIG. 1  is a circuit diagram illustrating a conventional volatile logic switch device. Since conventional logic switch and register devices are volatile, data stored in such registers are not preserved when power is off. 
     A volatile logic switch SW 1  connects a node B with a node C in response to a control signal applied to a gate input terminal A. The gate input terminal A of the volatile logic switch SW 1  has no memory device for storing previous and current data. As a result, data stored in the memory device are not preserved when power is off. 
       FIG. 2  is a circuit diagram illustrating a conventional flip-flop volatile memory device which is a SRAM (Static Random Access Memory). 
     The flip-flop volatile memory device comprises a flip-flop unit including PMOS transistors P 1  and P 2 , and NMOS transistors N 1  and N 2 . The flip-flop volatile memory device further comprises NMOS transistors N 3  and N 4  for storing data applied from bitlines BIT and /BIT in the flip-flop unit depending on an enable state of a wordline WL. 
     The conventional flip-flop volatile memory device can store data in both terminals of the flip-flop unit with a static state when power is on. However, the data stored in the terminals both of the flip-flop unit are destroyed when power is off. 
     Nonvolatile memory devices have been developed to overcome the above problem of the conventional volatile memory device.  FIGS. 3   a  to  3   d  are diagrams illustrating a conventional phase change memory (PCM) device. 
     The PCM device  4  comprises a phase change layer (PCL)  2  of phase change material for receiving voltage and current between a top electrode  1  and a bottom electrode  3 . The voltage and current induce high temperature in the PCL  2 , thereby changing electric conductivity of the PCL  2 . 
     As shown in  FIG. 3   c , if low current of less than a threshold value flows in the PCM device  4 , the PCL  2  has a proper temperature to be crystallized. Thus, the PCL  2  comes to have high resistance. 
     Referring to  FIG. 3   d , if high current of more than a threshold value flows in the PCM device  4 , the PCL  2  has a temperature over a melting point of the phase change material. Thus, the PCL  2  becomes uncrystallized to have low resistance. 
     The PCM device  4  can store nonvolatile data corresponding to the two resistances. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a programmable nonvolatile logic switch memory (register) device using a nonvolatile resistance memory device. 
     In an embodiment, there is provided a nonvolatile memory device comprising a write/read controller, a nonvolatile resistive memory device and a logic switch. The write/read controller selectively controls write/read control signals enabled in a write mode. As used herein, a nonvolatile resistive memory device is a circuit element that stores different logic values in the level of electrical resistance of one or more circuit elements, such that the states of resistance of the element or elements can be changed or set (e.g., set to a high resistance or set to a low resistance) by controlling the amount of current that passes through the device when the write/read control signals are enabled. The logic switch selects switching states depending on the different logic values pre-stored in the nonvolatile resistive memory device when the write/read control signals are disabled. 
     In an embodiment, there is also provided a nonvolatile memory device comprising a flip-flop unit, a nonvolatile resistive memory device, an access controller and a current supply unit. The flip-flop unit includes a PMOS latch and a NMOS latch, and latch the opposite data. The nonvolatile resistive memory device, which is connected between the PMOS latch and the NMOS latch, stores different logic values depending on states of resistance changed by the amount of current. The access controller controls connection of a bitline and the flip-flop unit depending on an enable state of a wordline. The current supply unit supplies current for changing data stored in the resistive memory device when the write/read control signals are enabled. 
     In an embodiment, there is also provided a nonvolatile memory device comprising a flip-flop unit, a nonvolatile resistive memory device and an access controller. The flip-flop unit includes a NMOS latch for latching opposite data. The nonvolatile resistive memory device, which is connected between a power voltage terminal and the flip-flop unit, stores different logic values depending on states of resistance changed by the amount of current. The access controller controls a connection of a bitline to the flip-flop unit depending on an enable state of a wordline. 
     In an embodiment, there is provided a nonvolatile memory device comprising a flip-flop unit, an access controller and a nonvolatile resistive memory device. The flip-flop unit includes a NMOS latch for latching opposite data. The access controller controls a connection of a bitline to the flip-flop unit depending on an enable state of a wordline. The nonvolatile resistive memory device, which is connected between the flip-flop unit and the access controller, stores different logic values depending on states of resistance changed by the amount of current. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating a conventional volatile logic switch device. 
         FIG. 2  is a circuit diagram illustrating a conventional flip-flop volatile memory device. 
         FIGS. 3   a  to  3   d  are diagrams illustrating a conventional PCM device. 
         FIGS. 4   a  and  4   b  are circuit diagrams illustrating a nonvolatile memory device according to an embodiment of the present invention. 
         FIGS. 5  to  9  are circuit diagrams illustrating a nonvolatile memory device according to other embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be described in detail with reference to the attached drawings. 
       FIG. 4   a  is a circuit diagram illustrating a nonvolatile memory device used as a nonvolatile logic switch according to an embodiment of the present invention. 
     In an embodiment, the nonvolatile memory device comprises a write/read controller  20 , resistance memory devices R 1  and R 2 , and a logic switch SW 2 . 
     The write/read controller  20  selectively outputs a write/read control signal WRC 1  in response to a write control signal WRC 2  inputted into a gate of a NMOS transistor N 5  and a write control signal WRC 3  inputted into a gate of a PMOS transistor P 3 . The write control signal WRC 2  has an opposite phase to that of the write control signal WRC 3 . 
     The resistive memory device R 1  is connected between a node D and a node F. The resistive memory device R 2  is connected between a node E and a node F. The node F is connected to a gate of the logic switch SW 2 . 
     Next, the write operation according to an embodiment of the present invention is described. 
     When the write control signal WRC 2  inputted in the write/read controller  20  is at a high level, the NMOS transistor N 5  is turned on. When the write control signal WRC 3  is at a low level, the PMOS transistor P 3  is turned on, and the write/read control signal WRC 1  is outputted. 
     If current is applied between the nodes D and F, data is written in the resistive memory device R 1 . If current is applied between the nodes E and F, data is written in the resistive memory device R 2 . 
     The resistive memory devices R 1  and R 2  of  FIG. 4   a  may be represented like those in  FIG. 4   b.    
     When the write control signal WRC 2  is at a low level and the write control signal WRC 3  is at a high level, the NMOS transistor N 5  and the PMOS transistor P 3  of the write/read controller  20  are all turned off. Here, when the resistive memory device R 1  has a low resistance and the resistive memory device R 2  has a high resistance, the states of the logic switch SW 2  are determined depending on states of input signals through the input nodes D and E. 
     Table 1 shows the operation of the logic switch SW 2  depending on input signals when low data is stored in the resistive memory device R 1  and the high data is stored in the resistive memory device R 2 . 
     
       
         
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 D 
                 E 
                 R1 
                 R2 
                 SW2 
               
               
                   
                   
               
             
             
               
                   
                 L 
                 L 
                 L 
                 H 
                 OFF 
               
               
                   
                 H 
                 L 
                 L 
                 H 
                 ON 
               
               
                   
                 L 
                 H 
                 L 
                 H 
                 OFF 
               
               
                   
                 H 
                 H 
                 L 
                 H 
                 ON 
               
               
                   
                   
               
             
          
         
       
     
     When a high level signal is applied to the node D and a high or low level signal is applied to the node E, the logic switch SW 2  is turned on to output a signal of the node ND 1  into the node ND 2 . 
     On the other hand, when a low level signal is applied to the node D and a low or high level signal is a applied to the node E, the logic switch SW 2  is turned off. As a result, the signal of the node ND 1  is not outputted into the node ND 2 . 
     When the resistive memory device R 1  has a high resistance and the resistive memory device R 2  has a low resistance, the states of the logic switch SW 2  are determined depending on states of input signals inputted through the input nodes D and E. 
     Table 2 shows the operation of the logic switch SW 2  depending on the input signals when high data is stored in the resistive memory device R 1  and low data is stored in the resistive memory device R 2 . 
     
       
         
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 D 
                 E 
                 R1 
                 R2 
                 SW2 
               
               
                   
                   
               
             
             
               
                   
                 L 
                 L 
                 H 
                 L 
                 OFF 
               
               
                   
                 H 
                 L 
                 H 
                 L 
                 OFF 
               
               
                   
                 L 
                 H 
                 H 
                 L 
                 ON 
               
               
                   
                 H 
                 H 
                 H 
                 L 
                 ON 
               
               
                   
                   
               
             
          
         
       
     
     When a high or low level signal is applied to the node D and a high level signal is applied to the node E, the logic switch SW 2  is turned on to output a signal of the node ND 1  into the node ND 2 . 
     When the high or low level signal is applied to the node D and a low level signal is applied to the node E, the logic switch SW 2  is turned off. As a result, the signal of the node ND 1  is not outputted into the node ND 2 . 
       FIG. 5  is a circuit diagram illustrating a nonvolatile memory device used as a nonvolatile logic register according to other embodiment of the present invention. 
     In an embodiment, the nonvolatile memory device comprises a flip-flop unit  30 , resistive memory devices R 3  and R 4 , an access controller including NMOS transistors N 8  and N 9 , and a current supply unit including PMOS transistors P 6  and P 7 . 
     The flip-flop unit  30  comprises a NMOS latch including NMOS transistors N 6  and N 7 , and a PMOS latch including PMOS transistors P 4  and P 5 . The NMOS latch and the PMOS latch store opposite data. 
     The resistive memory device R 3 , which is connected to a common drain of the PMOS transistor P 4  and the NMOS transistor N 6 , stores nonvolatile data. The resistive memory device R 4 , which is connected to a common drain of the PMOS transistor P 5  and the NMOS transistor N 7 , stores nonvolatile data. 
     The access controller, including the NMOS transistors N 8  and N 9 , controls a connection of bitlines BIT and /BIT depending on an enable state of a wordline WL. The NMOS transistor N 8  having a gate connected to the wordline WL is connected between the bitline BIT and the drain of the NMOS transistor N 6 . The NMOS transistor N 9  having a gate connected to the wordline WL is connected between the bitline /BIT and the drain of the NMOS transistor N 7 . 
     The current supply unit comprises PMOS transistor P 6  and P 7  for changing data stored in the resistive memory devices R 3  and R 4  in a write mode. The PMOS transistor P 6  connected in parallel to the PMOS transistor P 4  has a gate to receive a write/read control signal WRC. The PMOS transistor P 7  connected in parallel to the PMOS transistor P 5  has a gate to receive the write/read control signal WRC. 
     Gate input signals of the PMOS latch and the NMOS latch are connected to the resistive memory devices R 3  and R 4  with a positive feedback type circuit. 
     When the write/read control signal WRC is at a low level, the PMOS transistors P 6  and P 7  are turned on to apply a predetermined voltage to the bitlines BIT and /BIT. Then, a difference in current flowing in the resistive memory devices R 3  and R 4  is generated by a difference in voltages of the bitlines BIT and /BIT. As a result, the amount of heat applied to the resistive memory devices R 3  and R 4  is also differentiated. 
     Here, voltages of the bitlines BIT and /BIT are determined to generate heat in the resistive memory devices R 3  and R 4  over or below the melting point. 
       FIG. 6  is a circuit diagram illustrating a nonvolatile memory device according to other embodiment of the present invention. 
     The embodiment shown in  FIG. 6  is different from that of  FIG. 5  in that gate input signals of the PMOS latch P 4 ,P 5  and the NMOS latch N 6 ,N 7  are connected to the resistive memory devices R 3  and R 4  with a negative feedback type circuit. The explanation of the rest configuration and operation is omitted because it is similar to that of FIG.  5 . 
       FIG. 7  is a circuit diagram illustrating a nonvolatile memory device according to another embodiment of the present invention. 
     In this embodiment, the nonvolatile memory device comprises a flip-flop unit  30 , resistive memory devices R 3  and R 4 , an access controller including NMOS transistors N 8  and N 9 , and a driver which is a NMOS transistor N 10 . 
     The flip-flop unit  30  comprises a NMOS latch including NMOS transistors N 6  and N 7 . Gate input signals of the NMOS transistors N 6  and N 7  are connected to the resistive memory devices R 3  and R 4  with a positive feedback type circuit. 
     The resistive memory device R 3 , which is connected to a common drain of the NMOS transistors N 6  and N 10 , stores nonvolatile data. The resistive memory device R 4 , which is connected to a common drain of the NMOS transistors N 7  and N 10 , stores nonvolatile data. 
     The access controller comprises NMOS transistors N 8  and N 9  for controlling connection of bitlines BIT and /BIT depending on an enable state of a wordline WL. The NMOS transistor N 8  having a gate connected to the wordline WL is connected between the bitline BIT and a drain of the NMOS transistor N 6 . The NMOS transistor N 9  having a gate connected to the wordline WL is connected between the bitline /BIT and a drain of the NMOS transistor N 7 . 
     The driver comprises a NMOS transistor N 10 . The NMOS transistor N 10 , connected between a power voltage VCC terminal and the resistive memory devices R 3  and R 4 , has a gate to receive a write/read control signal WRC. 
       FIG. 8  is a circuit diagram illustrating a nonvolatile memory device according to another embodiment of the present invention. 
     In the nonvolatile memory device of  FIG. 8 , gate input signals of NMOS transistors N 6  and N 7  are connected to resistive memory devices R 3  and R 4  with a negative feedback type circuit. The nonvolatile memory device of  FIG. 8  does not comprise a NMOS transistor N 10  like that of FIG.  7 . The explanation of the rest configuration and operation is omitted because it is similar to that of FIG.  7 . 
       FIG. 9  is a circuit diagram illustrating a nonvolatile memory device according to another embodiment of the present invention. 
     The nonvolatile memory device of  FIG. 9  comprises a flip-flop unit  30 , resistive memory devices R 3  and R 4 , and an access controller including NMOS transistors N 8  and N 9 . 
     The flip-flop unit  30  comprises a NMOS latch including NMOS transistors N 6  and N 7 . Gate input signals of the NMOS transistors N 6  and N 7  are connected to the resistive memory devices R 3  and R 4  with a positive feedback type circuit. 
     The resistive memory device R 3 , connected between a terminal of the NMOS transistor P 8  and a drain of the NMOS transistor N 6 , stores nonvolatile data. The resistive memory device R 4 , connected between a terminal of the NMOS transistor P 9  and a drain of the NMOS transistor N 7 , stores nonvolatile data. 
     The access controller including the NMOS transistors N 8  and N 9  controls a connection of bitlines BIT and /BIT depending on an enable state of a wordline WL. The NMOS transistor N 8  having a gate connected to the wordline WL is connected between the bitline BIT and a terminal of the resistive memory device R 3 . The NMOS transistor N 9  having a gate connected to the wordline WL is connected between the bitline /BIT and a terminal of the resistive memory device R 4 . 
     Although a PCM device is exemplified as a resistive memory device in the above embodiments, a MTJ (Magnetic Tunneling Junction) or GMR (Giant Magnetic Resistive) device can be used as a resistive memory device alternatively. 
     Additionally, a nonvolatile memory device according to an embodiment of the present invention can be utilized as a nonvolatile programmable gate memory device such as a FPGA (Field Programmable Gate Array). 
     As discussed earlier, a nonvolatile memory device can be embodied using a resistive memory device in an embodiment of the present invention. Such a programmable register is applied to a memory chip in order to program data for regulating redundancy and reference with a software type, thereby improving reliability of the chip. 
     While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.