Abstract:
An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a Continuation-in-Part of application Ser. No. 10/926,407, Filed: Aug. 26, 2004, Titled: RESISTOR LADDER INTERPOLATION FOR PGA AND DAC, which is a Continuation-in-Part of application Ser. No. 10/748,250, Filed: Dec. 31, 2003, Titled: ANALOG TO DIGITAL CONVERTER WITH INTERPOLATION OF REFERENCE LADDER, which is a Continuation of application Ser. No. 10/158,774, Filed: May 31, 2002, Titled: ANALOG TO DIGITAL CONVERTER WITH INTERPOLATION OF REFERENCE LADDER, which is a Continuation-in-Part of application Ser. No. 10/153,709, Filed: May 24, 2002, Titled: DISTRIBUTED AVERAGING ANALOG TO DIGITAL CONVERTER TOPOLOGY, all of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to reference ladders, and more particularly, to interpolation of reference ladder voltages for use in analog to digital converters (ADCs) programmable gain amplifiers (PGAs) and digital to analog converters (DACs).  
         [0004]     2. Related Art  
         [0005]     A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC&#39;s (i.e. high speed, low power, low area, high resolution).  FIG. 1  shows the generic two-step subranging architecture, comprising a reference ladder  104 , a coarse ADC  102 , a switching matrix  103 , a fine ADC  105 , coarse comparators  107 , fine comparators  108  and an encoder  106 . In most cases, a track-and-hold  101  is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC  102 . The coarse ADC  102  compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix  103  connects the fine ADC  105  to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage.  
         [0006]     A flash ADC architecture is the most straightforward implementation of an analog-to-digital converter. Unfortunately, it is very inefficient in terms of area and power. In particular, an N-bit ADC requires 2 N  comparators. Furthermore, it requires a reference ladder with 2 N  taps, which generally causes a lot of wiring parasitic capacitance, slowing down the ADC.  
         [0007]     A subranging ADC architecture is often used as a more power- and area-efficient alternative to the flash ADC architecture. While subranging does help to reduce the number of comparators, it does not help to reduce the number of taps on the reference ladder. In fact, the situation is complicated by the fact that subranging requires a switching matrix with a large number of switches. Parasitic capacitance associated with these switches slows down the ADC even further.  
         [0008]     A conventional way of connecting the first row of amplifiers to the reference ladder is shown in  FIG. 2 : amplifier A 1  connects to reference taps “2m” and “0”, amplifier A 2  connects to a “2m−1” tap and a “1” tap, etc. Thus, in a “brute force” flash ADC, the reference ladder  104  has 2 N =2m taps (e.g., 1024 taps for N=10).  
         [0009]     Three techniques have been published in the literature for decreasing the number of switches in subranging ADC&#39;s. First, interpolation between preamplifier output voltages is often used. Interpolation is often applied in both flash ADC&#39;s, subranging ADC&#39;s and folding ADC&#39;s. This form of interpolation reduces the number of amplifiers in a first array of amplifiers. Since only the first array of amplifiers needs connections to the reference ladder  104 , this technique reduces the required number of reference taps and switches. For example, 4× interpolation within the fine ADC  105  reduces the number of switches by 75%.  
         [0010]     A second technique for reducing the number of switches is referred to as “absolute value processing.” See B. P. Brandt and J. Lutsky. “A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist,”  IEEE Jour. of Solid State Circ.,  34(12):1788-1795 (December 1999). This technique uses the fact that the absolute value function can be implemented simply by a commutator, basically comprising only four switches. This technique reduces the required number of switches in the matrix  103  by another 50%. Note that this technique does not reduce the number of taps on the reference ladder  104 .  
         [0011]     A third technique called “multilevel tree decoding scheme” decreases the number of switches by 62.5%. (See, e.g., Ito et al., “A 10-bit 20 MS/s 3V Supply CMOS A/D converter,”  IEEE J. of Solid State Circ.,  29 (12):1532-36, December 1994) Note that this technique does not reduce the number of taps on the reference ladder  104 .  
         [0012]     For example, a 10-bit analog digital converter in a “brute force” flash type configuration would require 2 10 , or 1024 taps on the reference ladder, which is very awkward. Thus, the problem involves the total number of taps required from the reference ladder, as well as the number of switches in the switch matrix for a subranging analog digital converter. It is therefore desirable to reduce the number of taps, which reduces the amount of parasitic capacitance due to the connections involved.  
         [0013]     Accordingly, a need exists for an ADC circuit topology that significantly reduces the number of switches and taps from the reference ladder  104 .  
       SUMMARY OF THE INVENTION  
       [0014]     The present invention is directed to resistor ladder interpolation for subranging ADC that substantially obviates one or more of the problems and disadvantages of the related art.  
         [0015]     To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided an analog to digital converter including a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.  
         [0016]     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
         [0017]     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:  
         [0019]      FIG. 1  represents a generalized 2-step subranging an ADC architecture;  
         [0020]      FIG. 2  illustrates a conventional way of connecting a first row of amplifiers to a reference ladder;  
         [0021]      FIG. 3  illustrates an auto-zero amplifier used in the present invention;  
         [0022]      FIG. 4  illustrates a first technique for connecting amplifiers of the present invention to the reference ladder;  
         [0023]      FIG. 5  illustrates the approach of  FIG. 4  with split capacitor interpolation;  
         [0024]      FIG. 6  illustrates the approach of  FIG. 5  with interpolation of sampling capacitor outputs;  
         [0025]      FIG. 7  illustrates a circuit diagram corresponding to the approach of  FIG. 6 ;  
         [0026]      FIG. 8  illustrates a reference ladder used in the present invention;  
         [0027]      FIG. 9  illustrates capacitive interpolation as applied to a programmable gate array;  
         [0028]      FIG. 10  illustrates an embodiment of interpolation where differential inputs are used;  
         [0029]      FIG. 11  illustrates an example of active interpolation for a digital to analog converter.  
         [0030]      FIGS. 12-13  illustrate a conventional switch matrix used in a subranging ADC; and  
         [0031]      FIGS. 14-15  illustrate a switch matrix of the present invention used in a subranging ADC.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0032]     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0033]     One of the disadvantages of the subranging ADC architecture is the large number of switches required, resulting in degraded high-frequency performance. This disclosure describes how the required number of switches can be significantly reduced by interpolation of the reference ladder. Three new interpolation techniques are proposed.  
         [0034]     All three techniques accomplish interpolation of the reference ladder taps. Since all three techniques can be applied to both subranging and flash ADC&#39;s, for simplicity they will be illustrated with respect to the flash architecture, showing a reduction in reference ladder taps that can be accomplished. Note that for subranging architectures, a reduction in the required number of switches equals a reduction in number of reference taps.  
         [0035]     The techniques are illustrated based on the auto-zero amplifier shown in  FIG. 3 .  FIG. 3  illustrates the structure of one of the amplifiers in an amplifier array A 1 , A 2 , A 3  . . . of  FIG. 4 , discussed below. As shown in  FIG. 3 , a non-overlapping two-phase clock is used, with non-overlapping phases Φ 1  and Φ 2 . At a “+” input of the amplifier, two NMOS transistors M 1  and M 2  are used, with a source of the transistor M 2  being connected to the “+” input terminal, and a gate of the transistor M 2  being connected to the clock phase Φ 2 . The “+” and “−” inputs are connected to taps from the reference ladder  104 .  
         [0036]     A gate of the transistor M 1  is driven by the clock phase Φ 1 . The drains of the transistors M 1  and M 2  are tied together and connected to one side of a capacitor C+. A source of M 1  is connected to the positive T/H  101  output, and a source of M 7  is connected to the negative T/H  101  output. The gates of M 1  and M 7  are driven by Φ 1 . The other side of the capacitor C+ is connected to a source of a transistor M 3 , and to a gate of a transistor M 4 . A gate of the transistor M 3  is connected to the clock phase Φ 1 . Drains of the transistors M 3  and M 4  are tied together and, through resistor R 1 , to a positive supply voltage V dd . A symmetrical structure is used for the “−” input, as shown in  FIG. 3 , using transistors M 8 , M 7 , M 6  and M 5 , and a capacitor C−. The amplifier has differential outputs V OUT+ , V OUT− . The dashed portion corresponds to the amplifier A 1  shown in subsequent figures.  
         [0037]     During clock phase Φ 1 , the amplifier is in a reset mode and the sampling capacitors are charged to the value of the sampled voltage V sample . More specifically, on Φ 1 , the transistors M 1 , M 3 , M 5  and M 7  are turned on. During the next clock phase, Φ 2 , the transistors M 2  and M 8  are turned on, the amplifier is connected to the reference ladder  104  and the amplifier output voltage V OUT  equals: V OUT =G·(V ref −V sample ),  
         [0038]     where G is the voltage gain of the amplifier, V ref =V +input −V −input  and  
         [0039]     V sample =V TH, pos −V TH, neg , where V TH  is the differential output of the track and hold  101 .  
         [0040]     It will be appreciated that although the auto-zeroing amplifier of  FIG. 3  is shown as using N channel MOSFET&#39;s, P channel MOSFET&#39;s can also be used. Note further that the track-and-hold  101  of  FIG. 1  is typically a differential input and output amplifier that is connected to differential outputs of the track and hold amplifier  110 , V TH, pos  and V TH, neg .  
         [0041]      FIG. 4  illustrates a first interpolation technique, and shows that about 50% reduction in the number of taps can be obtained if only the positive or the negative reference input is changed when going from one amp to the next. That is, amplifier A 1  in  FIG. 4  connects to reference taps “m” and “0”, amplifier A 2  connects to “m” and “1”, so that only the negative input changes from A 1  to A 2 ; amplifier A 3  connects to “m−1” and “1”, etc. In other words, a reference ladder  104  has a plurality of taps V ref,0  through V ref,m .  FIG. 4  also shows each of the amplifiers A 1 , A 2 , A 3  . . . has a capacitor at each input. Thus, the amplifier A 1  has a capacitor C 1  at its “+” input, and capacitor C 2  at its “−” input. The amplifier A 2  has capacitor C 3  at its “+” input, and capacitor C 4  at its “−” input, and so on. The transistors M 1 , M 2 , M 7  and M 8  correspond to the transistors shown in  FIG. 3  (and are only shown for the amplifier A 1  for clarity). The capacitors C 1 , C 2  correspond to the capacitors C−, C+ of  FIG. 3 .  
         [0042]     As may be seen from  FIG. 4 , the amplifier A 1  is connected to taps V ref,m  and V ref,0 . The amplifier A 2  is connected to V ref,m  and V ref,1 . The amplifier A 3  is connected to V ref,m−1  and V ref,1 , and so forth. Comparing  FIG. 2  with  FIG. 4 , in  FIG. 4 , neighboring amplifiers have only one of their inputs changed, compared to neighboring amplifier in  FIG. 2 , where both of the inputs are changed. In other words, with reference to  FIG. 2 , in  FIG. 2  both the “+” inputs on the amplifiers A 1  and A 2  change (from V ref, 2m  to V ref,2m−1 ) as well as the “−” inputs change (from V ref,0  to V ref,1 ). In contrast, in  FIG. 4 , the “+” inputs of the amplifiers A 1  and A 2  are both the same (V ref,m ), while the “−” inputs of the amplifiers A 1  and A 2  change from V ref,0  to V ref,1 . Thus, only one of the inputs changes when going from one amplifier to a neighboring amplifier.  
         [0043]     It will be appreciated that the terms “adjacent” and “neighboring” are used in their hierarchical sense compared to the taps from the reference ladder  104 , rather than in the sense of how the overall circuit is actually laid out. Thus, although an actual layout would most likely have the amplifiers A 1 , A 2 , A 3  . . . laid out close to each other, this need not be the case.  
         [0044]     It will be appreciated that unlike  FIG. 2 , which requires a total of  1024  taps for a 10-bit analog digital converter, e.g., 2 N  in a “brute force” approach, the number of taps required for the circuit of  FIG. 4  to operate is half that (or  2   N ÷2). Note also that the 2 N ÷2 figure assumes that no interpolation is used.  
         [0045]     The proposed technique results in common-mode differences at the inputs of the amplifiers. This is only a minor disadvantage, since the amplifiers generally have good common-mode rejection and the common-mode differences are quite small.  
         [0046]     The outputs of the amplifiers (or, if necessary, cascaded stages of amplifiers) are fed into a comparator array (not shown, see  108  of  FIG. 1 ), and then to an encoder (not shown, see  106  of  FIG. 1 ).  
         [0047]     A second technique accomplishing reference ladder interpolation is illustrated in  FIG. 5 . Here, the input sampling capacitors C 1 , C 2  . . . of the amplifiers A 1 , A 2 , A 3  . . . are split into two parts, effectively providing each amplifier with two positive and two negative reference inputs. The capacitor C 1  is split up into the capacitors C 1   a  and C 1   b , and the capacitor C 2  is split up into the capacitors C 2   a  and C 2   b . The capacitor C 3  is split up into capacitors C 3   a  and C 3   b , the capacitor C 4  is split up into capacitors C 4   a  and C 4   b , and so on. The two positive reference inputs can be connected to different reference taps, thus implementing interpolation of the reference ladder  104 . The same applies to the two negative reference inputs. As an example, the two positive reference inputs shown in  FIG. 5  are connected to taps “m” and “m−1”. The “+” input of A 2  is effectively connected to a “virtual” tap V ref, m−1/2 . The “−” input is effectively connected to a “virtual” tap V ref,1/2 . Thus, this interpolation technique allows an additional reduction of 50% in the number of tap lines from the reference ladder  104 .  
         [0048]     Note that in terms of circuit layout on a semiconductor substrate, it is easier to split up a capacitor into two smaller capacitors, rather than having more taps from a reference ladder, since the primary source of parasitics is the number of tap lines from the reference ladder  104 . A reduction of tap lines therefore results in a reduction in parasitic capacitance associated with the additional tap lines.  
         [0049]     It will also be appreciated by one of ordinary skill in the art that the interpolation approach of  FIG. 5  does not require that the capacitors at the input of each amplifier be equal. Thus, the interpolation technique will work if each capacitor split up into capacitors having different values, as appropriate for the voltage required at the particular input of the amplifier. It will also be appreciated that each input capacitor can be split up into more than two capacitors, e.g., capacitor C 3  may be split up into capacitors C 3   a , C 3   b , C 3   c , although as each capacitor gets smaller, eventually the use of such small capacitors for interpolation will become problematic.  
         [0050]     A third technique accomplishing reference ladder interpolation is illustrated in  FIG. 6 .  FIG. 6  shows that not all input amplifiers need to be connected to the reference taps. Interpolation of the sampling capacitor “outputs” can be used to reduce the required number of reference taps. In the example shown in  FIG. 6 , a reduction of about 50% is obtained.  
         [0051]     As may be seen from  FIG. 6 , not every amplifier in the amplifier array A 1 , A 2 , A 3  . . . needs to have its own tap line, particularly where the adjacent, or neighboring, amplifier uses the same tap line. Thus, the “−” input of the amplifier A 1 , which in  FIG. 4  is connected to V ref,0  tap, can be directly connected to the “+” input of the amplifier A 2 , which in  FIG. 4  is also connected to the V ref,0  tap. Similarly, since the “+” input of A 3  and the “−” input of the amplifier A 2  are connected to the same voltage V ref,m−1  tap, the “−” input of the amplifier A 2  does not require its own tap, but can be directly connected to the “+” input of the amplifier A 3 . This will further reduce the number of tap lines and tap connections from the reference ladder to the amplifier array. The technique shown in  FIG. 6  may be referred to as “interpolate by 2” technique, which results in a 50% reduction in the overall number of tap connections. It also results in the elimination of approximately half of the input capacitors, compared to the technique shown in  FIG. 4 .  
         [0052]      FIG. 7  illustrates the approach of  FIG. 6  in more detail and shows the three amplifiers A 1 , A 2 , A 3  of  FIG. 6  (without the switches driven by the two phase clock). The A 1  and A 3  amplifiers have their own input capacitors (C 1 , C 2 , and C 5 , C 6 , respectively), the A 1  amplifier has differential inputs V ref,m /V ref,0 , the amplifier A 3  has differential inputs V ref,m−1 /V ref,1 . The amplifier A 2  does not have its own input capacitors. Instead, the amplifier A 2  comprises two differential transistor pairs M 4 , M 6  (both half the size of the differential pairs M 4 , M 6  of A 1  and A 3 ). It&#39;s current sources are each half of the current source of A 1  or A 3 . Gates of one of the transistor pairs M 4 , M 6  connect to the gates of the corresponding transistors of the A 1  amplifier, and gates of the other differential transistor pair M 4 , M 6  connect to corresponding gates of transistors of the A 3  amplifier. The drain currents of the two differential transistor pairs of A 2  are summed. As a result, the output of the amplifier A 2  (V OUT,2 ) is (approximately) equal to the average of the outputs of A 1  and A 3  (i.e., the average of V OUT,1  and V OUT,3 ).  
         [0053]     The reference ladder interpolation techniques described here can be applied to various types of ADC architectures. In flash and folding ADC architectures, they can be used to reduce the number of taps on the reference ladder  104 . In subranging ADC architectures, they reduce both the number of reference taps and the number of switches.  
         [0054]     It will be appreciated by one with ordinary skill in the art that techniques described herein are applicable to both flash type ADC&#39;s, folding ADC&#39;s and subranging ADC&#39;s.  
         [0055]      FIG. 8  illustrates a reference ladder arrangement of one embodiment of the present invention. The reference ladder  104  includes a plurality of 65Ω resistors which are connected to a relatively slow amplifier  801 . (The bandwidth of the amplifier  801  as approximately 1-2 MHz). The output of the amplifier  801  is also tied to its “−” input, and to a transistor  802 , whose both source and drain are tied to ground, forming a 22 pF capacitor.  
         [0056]     All three techniques can be applied at the same time, in order to obtain a very significant reduction in the number of reference taps and matrix switches.  
         [0057]     For example, for an N=9 bit ADC, the reduction in number of taps is as follows:  
                                                       full flash for N = 9:   512 taps (2 N )           2x capacitive interpolation at ladder:   256 taps (2 N−1 )           change V ref,p  or V ref,n  only:   128 taps (2 N−2 )           2x interpolation of the “outputs”    64 taps (2 N−3 )           of the sampling caps           4x split differential pair interpolation:    16 taps (2 N−5 )           edge effect (add one or two):    17 taps                      
 
         [0058]     The table below illustrates the tap voltages for the 17-tap case:  
                                                                 Tap #   Tap voltage                                        16   0.95           15   0.90625           14   0.8625           13   0.81875           12   0.775           11   0.73125           10   0.6875           9   0.64375           8   0.6           7   0.55625           6   0.5125           5   0.46875           4   0.425           3   0.38125           2   0.3375           1   0.29375           0   0.25                      
 
         [0059]     In the description above, a resistive ladder was used for voltage interpolation in the context of analog converters. However, the interpolation approach discussed herein is also applicable to other circuits, for example, programmable gate arrays (PGAs) and digital to analog converters (DACs). The advantage of this approach for PGAs and DACs is the same, i.e., reducing the number of voltage taps from the resistive ladder, and consequently, reduction in the number of resistors necessary in the resistive ladder. This has the advantage of reducing the amount of real estate on the integrated circuit that is taken up by the resistive ladder.  
         [0060]      FIG. 9  illustrates capacitive interpolation as applied to a programmable gate array. As shown in  FIG. 9 , a resistive ladder includes five resistors  901 A- 901 E. (It will be appreciated that the invention is not limited to any particular number of resistors in the resistive ladder.) Two capacitors C 902 A and C 902 B are at the input of an amplifier  903 , which outputs an output voltage V OUT . The resistive ladder includes a number of taps, which are connected to the capacitors C 902 A, C 902 B through switches S 1 A, S 1 B through S 5 A, S 5 B, as shown in  FIG. 9 .  
         [0061]     The switches S 1 A-S 5 B can be digitally controlled, to result in a large number of possible interpolated voltages, compared to a conventional resistive ladder, which has just the voltage taps (essentially, a resistor divider network). The circuit in  FIG. 9  may be viewed as an example of a programmable gain amplifier with a capacitive coupling to a buffer amplifier.  
         [0062]      FIG. 10  illustrates an embodiment of a PGA or a DAC, where differential inputs are used. In essence, two resistive ladders such as shown in  FIG. 9 , are used in this circuit, one for the positive input V IN,POS , and one for the negative input V IN,NEG . Two amplifiers  903 A,  903 B (corresponding to the differential analog of the single amplifier  903  shown in  FIG. 9 ) are used. These amplifiers are connected in the same manner to their respective resistive ladders, as shown in  FIG. 9  (these connections are not shown in  FIG. 10  for simplicity). As shown in the lower half of  FIG. 10 , by changing the connections from the taps to the buffer amplifiers  903 A,  903 B, the output voltages V OUT,POS  and V OUT,NEG  can be interpolated (in other words, going from a set of connections shown in position  1  to a set of connections shown in position  2  in  FIG. 10 ). In the example shown in  FIG. 10 , when going from one position to the next, only the “tap” position of the positive or the negative buffer amplifier  903 A,  903 B is changed. This in effect reduces the number of taps required by a factor of 2. Note that this circuit can be used both in a programmable gain amplifier (when having a varying input signal), or in a DAC (when having a DC reference input signal). In the case of a DAC, the capacitors C 902 A, C 902 B would be omitted, since the voltages from the taps are DC voltages.  
         [0063]      FIG. 11  illustrates an example of active interpolation for a digital to analog converter. Similar to  FIG. 9 , a resistive ladder comprising a number of resistors (in this case,  901 A- 901 E) is used, with a number of taps between the resistors  901 A- 901 E. The taps are connected through switches S 1 A-S 5 B to two transistors M 1101 A, M 1101 B (e.g., MOSFET transistors, or bi-polar transistors), as shown in  FIG. 11 . The switches S 1 A-S 5 B are digitally controlled, to be “on” or “off”, to provide a particular gate voltage on the gates of the transistors M 1101 A, M 1101 B. In the simplest case, only one of the switches is “on”, effectively making the resistor ladder a resistor divider. However, by combining several switches, an interpolated voltage may be applied to the gates. A current source  1102  is also used, in combination with the interpolated gate voltages, to generate an interpolated output voltage V OUT .  
         [0064]     In the subranging ADC, the ‘switch matrix’  103  is essentially a big multiplexer that selects a subset of differential reference voltages (swop-swon) from the set of reference ladder voltages.  FIG. 12  illustrates such a conventional switch matrix  103  used in a subranging ADC. For instance, in the 8 bit subranging ADC,  3  different differential reference voltages are selected out of the 17 voltages from the resistor ladder. These selected voltages are used as the reference inputs to the fine ADC  105  of the subranging ADC. The switch matrix  103  is controlled by (in this case) 15 control signals (‘cntrl’); during the clock phase that the fine ADC  105  connects to the reference ladder, only one of these control signals is high.  
         [0065]     For example, the 8 bit subranging ADC has 15 cntrl signals, which means that a total of 90 switches are required in the switch matrix  103 . The description of the switch matrix  103  is shown in the box in  FIG. 12 , and is further illustrated in  FIG. 13 . Note that the switches for ‘swop’ and ‘swon’ are controlled by the same control signals.  
         [0066]     A method and circuit is proposed to reduce the number of switches used in the switch matrix  103 .  FIG. 14  illustrates a switch matrix  103  of the present invention used in the subranging ADC. This approach has advantages of using 2× fewer switches inside the switch matrix  103 , and 2× smaller drivers for the ‘cntrl’ signals.  
         [0067]     The proposed switch matrix  103 , for the  8   b  ADC, is shown in  FIG. 14 .  
         [0068]     In the proposed switch matrix  103 , the ‘swop’ and ‘swon’ signals are controlled by separate control signals (‘cntrl_p’ and ‘cntrl_n’), as further illustrated in  FIG. 15 . (Note that swop&lt; 1 &gt;, swop&lt; 0 &gt;, swon&lt; 1 &gt;, swon&lt; 0 &gt; are not shown in this figure.)  
         [0069]     During the clock phase when the fine ADC  105  connects to the resistor ladder, only one cntrl_p and one cntrl_n signal is high. Each cntrl_p/cntrl_n signal is high for two consecutive subranges. Therefore, one set of reference voltages (in this case, three references voltages), and therefore also set of switches (in this case, three switches), is used in two consecutive subranges (as illustrated by the grey color in  FIG. 14 ). Phrased another way, the switch matrix  103  inputs control signals for selecting at least two voltage subranges at substantially the same time. Hence, since all switches can be used twice, the total number of switches is halved (to 48 switches, vs. 90 in  FIG. 13 ), resulting in using less area. It also results in lower parasitics, which in turn means higher bandwidth for the overall ADC.  
         [0070]     Note that the use of the proposed method and circuit can result in a small difference in common-mode voltages between two consecutive subranges. The difference equals  
           Δ   ⁢           ⁢     V   ⁢   cm       =       V     ref   ,   max         2     M   +   1           ,       
 
 where M is the number of bits in the coarse ADC, and V ref,max  is the maximum ADC input voltage. For instance, for a 5 bit coarse ADC and V ref,max =1.4V, ΔVcm=22 mV. This value is sufficiently small to be handled by the fine ADC  105  amplifiers. 
 
         [0071]     Note also that the switch matrix as described herein is applicable not just to subranging ADCs, but also to PGAs and DACs.  
         [0000]     Conclusion  
         [0072]     It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.