Abstract:
A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 12/113,066, filed Apr. 30, 2008, which is a divisional of U.S. patent application Ser. No. 11/442,510, filed May 25, 2006, U.S. Pat. No. 7,375,573. These applications are incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    This invention relates to digital integrated circuits, and, more particularly, to a system and method for adjusting the waveform of a digital signal before it is coupled though a highly capacitive line to make it easier to correctly detect the signal at a receiving device. 
       BACKGROUND OF THE INVENTION 
       [0003]    As the operating speeds of electronic devices, such as memory devices, continues to increase, the timing of digital signals received by the devices has become ever more critical. For example, in a memory device, such as a dynamic random access memory (“DRAM”) device, command, address and write data signals are transmitted to the memory device by a memory controller, and read data signals are transmitted to the memory controller by the memory device. Conventional memory devices generally operate synchronously with a clock signal, which defines the times that the received signals are considered valid. As the operating speed of memory devices continues to increase, the period during which the command, address and write data signals received by the memory device are considered valid has become ever shorter. As a result, it has become more critical to control the timing at which these signal are received by memory devices. 
         [0004]    The timing of digital signals, such as command, address and data signals, are adversely affected by “jitter,” which is high frequency phase noise that cause rapid changes in the timing at which transitions of the digital signal occur. Jitter can be caused by a number of sources, such as noise coupled to digital circuits along with a digital signal, which causes the switching time of the digital circuit to vary in a random manner. Jitter can also be caused by variations in the shape of digital signals coupled to digital circuits. 
         [0005]    With reference to  FIG. 1 , a digital signal having the waveform shown by the dotted line may be applied into a signal line. When the digital signal is applied to the signal line, its signal levels vary between voltages  0  and V*. As shown in  FIG. 1 , the transmitted waveform has a 50% duty cycle between time t 0  and time t 2 . A “double width” pulse then occurs starting at time t 2  followed by a return to the original waveform starting at time t 4 . If the signal line is highly capacitive, the waveform received by a downstream electronic device may have the waveform shown by the solid line in  FIG. 1 . As a result of the combination of the high frequency of the signal and the high capacitance of the signal line, the received waveform never reaches the full amplitudes of the transmitted waveform. For example, the transmitted signal starts charging the capacitive signal line toward the voltage V* at time t 0 , which is shown by the dotted arrow at time t 0 . However, the amplitude of the received signal never reaches the level V* volts. Instead, it reaches the level V 1  at time t 1 , at which time the transmitted signal starts discharging the signal line toward 0 volts, as again shown by the dotted arrow. Again, the amplitude of the received signal never reaches 0 volts. Instead, it reaches the level V 2  at time t 2 , at which time the transmitted signal again starts charging the signal line. Thus, the capacitive signal line charges toward V* volts from V 2  volts, and it starts discharging toward 0 volts from V 1  volts. 
         [0006]    The symmetrical, unvarying shape of the transmitted signal between times t 0 -t 2 , causes the received signal to cross the midpoint voltage M with the same delay after each corresponding edge of the transmitted signal. This can be seen by the uniform spacing between the dotted arrows and the immediately following solid arrows. As a result, a digital circuit that switches state at the midpoint voltage M will change state with a uniform delay after each transition of the signal applied to the signal line. 
         [0007]    During the double width pulse starting at time t 2 , the signal line is charged toward the voltage V* for a longer period of time. The received signal therefore reaches the amplitude V 3  volts at time  4  at which time the signal line begins being discharged toward 0 volts. The received signal still crosses the midpoint voltage M with the same delay after the corresponding edge of the transmitted signal as shown by the solid arrow following the dotted arrow at time t 2 . However, because the discharge of the signal line starts from V 3  volts rather than the lower amplitude of V 1  volts, it now crosses the midpoint voltage M with a much longer delay after the corresponding edge of the transmitted signal. The skew of the received signal can be seen by the increased spacing of the solid arrow immediately following the dotted arrow at time t 4 . This skew in the midpoint amplitude M crossing delay as function of the bit pattern of the transmitted signal can results in signal jitter at a circuit receiving the signal. As explained above, jitter can adversely affect the receiving circuit&#39;s ability to capture the correct pattern of the transmitted digital signal because the receiving circuit may register the incorrect bit from the received signal. 
         [0008]    This jitter problem is particularly acute in coupling address signal to memory devices. Address signal are typically transmitted to a plurality of memory devices through a signal distribution tree. The relatively large size of the tree when a large number of memory devices are present makes the address lines highly capacitive. In fact, the jitter caused by the high capacitance of address signal trees can defeat the major reason for using a tree, i.e., to ensure that address signal transitions arrive at all of the memory devices at the same time. The memory devices in a system attempt to capture the address signals using a clock signal, which may also be coupled through a clock tree. Ideally, a transition of the clock signal used to capture the address signals occurs at the center of the address signal. However, jitter can cause timing skews that cause the clock signal transition to occur before or after a “window” or “eye” during which the address signals are valid. For example, as shown in  FIG. 2 , if a clock signal CLK does not cause each of several address signals A&lt;0:9&gt; to latch at the proper time, errors in the operation of the memory device may result. Thus, the timing skew of the clock signal CLK relative to the timing skews of the address signals A&lt;0:9&gt; must be limited to allow the CLK signal to latch each of the several address signals A&lt;0:9&gt;. As the data transfer rate increases, the duration of each eye E for which each address signal A&lt; 0 &gt;-A&lt; 9 &gt; is valid decreases by a corresponding amount, as will be understood by one skilled in the art. With further reference to  FIG. 2 , the solid lines indicate the ideal address signals A&lt; 0 &gt;, A&lt; 1 &gt;, and A&lt;9&gt; signals, and the dashed lines indicate the worst case potential time skew for each of these signals. The ideal address signals A&lt; 0 &gt;, A&lt; 1 &gt;, and A&lt; 9 &gt; are centered at the rising edge of the CLK signals. The eyes E during which the address signals A&lt; 0 &gt;, A&lt; 1 &gt;, and A&lt; 9 &gt; are valid are defined by time intervals t 0 -t 3 , t 1 -t 4 , and t 5 -t 7 , respectively. In fact, the eyes E of the applied address signals A&lt; 0 &gt;-A&lt; 9 &gt; may even vary to such an extent that not all of the address signals are simultaneously valid at any time. In other words, there is no time during which the eyes E of all of the address signals overlap. Under these circumstances, the ideal address signals A&lt; 0 &gt;, A&lt; 1 &gt;, and A&lt;9&gt; signals, all of the address signals A&lt; 0 &gt;-A&lt; 9 &gt; cannot possibly be captured by the CLK signal. For example, in  FIG. 2 , the eye E of the A&lt;0&gt; signal from times t 0 -t 3  does not overlap the eye of the A&lt;9&gt; signal from times t 5 -t 7 . It is therefore important to limit the jitter or timing skew of the CLK and address signals A&lt; 0 &gt;-A&lt; 9 &gt;. 
         [0009]    Attempts have been made to solve the jitter problem exemplified by  FIGS. 1 and 2  using various equalization techniques. Two different equalization approaches have been tried. The first approach attempts to modify the characteristics of the signal line by either making it less capacitive or by making a transmitted signal less affected by the capacitance, such as by inserting repeaters or inverters in the line. Unfortunately, this approach can unduly increase the cost of digital devices. The second approach attempts to modify the shape of the transmitted signal so that the capacitance of the signal line causes it to be received with close to its original shape. In one example, every transition of the digital signal is provided with a large overshoot, which is capacitively filtered out by the signal line. The size and complexity of circuitry using this approach can again unduly increase the cost of digital devices, particularly since the nature of the modification must depend on the characteristics of the bit pattern. 
         [0010]    There is therefore a need for a relatively inexpensive system and method for allowing digital signals having an irregular bit pattern to be coupled through highly capacitive signal lines without causing jitter in the received signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a timing diagram illustrating the manner in which signal jitter is created by coupling a digital signal through a highly capacitive signal line. 
           [0012]      FIG. 2  is a timing diagram showing the manner in which timing skew or jitter can prevent a clock signal from capturing address signals during an “eye” when the address signals are valid. 
           [0013]      FIGS. 3A and 3B  are timing diagrams illustrating the manner in which signal jitter is avoided by a signal de-emphasis system and method according to one example of the invention. 
           [0014]      FIG. 4  is a block diagram of a de-emphasis system according to one example of the invention. 
           [0015]      FIG. 5  is a block diagram of a computer system using the de-emphasis system shown in  FIG. 4  or a de-emphasis system according to some other example of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    The manner in which a signal de-emphasis system and method according to one example of the invention avoids creating signal jitter is shown in  FIGS. 3A and 3B . A digital signal that is to be transmitted through a highly capacitive signal line is shown in  FIG. 3A . The signal is assumed to be referenced to a clock signal (not shown) that may be transmitted along with the signal. The signal is high for one clock period between times t 0  and t 1 , is then low for one clock period between times t 1  and t 2 , is high for three clock periods between times t 2  and t 5 , low for one clock period between times t 5  and t 6 , then high for one clock period between times t 6  and t 7 , and finally low for two clock periods between times t 7  and t 9 . 
         [0017]    The de-emphasis system and method applies the digital signal to the signal line with the shape shown by the solid line in  FIG. 3 . As shown therein, when the digital signal is high, it is applied to the signal line with a level of V* volts for the first period of the clock signal, and it then transitions to V 1  volts for any remaining period of the clock signal. Similarly, when the digital signal is low, it is applied to the signal line with a level of 0 volts for the first period of the clock signal, and it then transitions to V 2  volts for any remaining period of the clock signal. Thus, when the digital signal is high for three clock periods between times t 2  and t 5 , it is applied to the signal line as V* volts for the first clock period between times t 2  and t 3  followed by V 1  volts for the remaining two clock periods between times t 3  and t 5 . When the digital signal is low for two clock periods between times t 7  and t 9 , it is applied to the signal line as 0 volts for the first clock period between times t 7  and t 8  followed by V 2  volts for the remaining clock period between times t 8  and t 9 . 
         [0018]    The digital signal as it is received from the highly capacitive signal line at a downstream location is shown by the dotted line in  FIG. 3B . The signal line charges toward V* volts between times t 0  and t 1 , and reaches approximately V 1  volts after one clock period at time t 1 . The digital signal is low during the next clock period between times t 1  and t 2 , so the signal line begins discharging from V 1  volts toward 0 volts, and it reaches approximately V 2  volts after one clock period at time t 2 . The signal line then begins charging from V 2  volts toward V* volts at time t 2 . Therefore, the charging of the signal line always starts from V 2  volts, and the discharging of the signal line always starts from V 1  volts. 
         [0019]    If the digital signal applied to the signal line is high for more than one clock period, e.g., between times t 2  and t 5 , the signal line is again charged to voltage V 1  during the first clock period from times t 2  and t 3 . However, during the next two clock periods between times t 3  and t 5 , the signal line remains at V 1  volts because the digital signal applied to the signal line transitions from V* volts to V 1  volts after one clock period at time t 3 . Therefore, the signal line always starts discharging from V 1  volts regardless of the number of clock period the digital signal is high. Similarly, when the signal line begins discharging from V 1  volts toward 0 Volts at time t 7 , it again reaches approximately V 2  volts after one clock period at time t 8 . During the next clock period between times t 8  and t 9 , the signal line remains at V 2  volts because the digital signal applied to the signal line transitions from 0 volts to V 2  volts after one clock period at time t 8 . Therefore, the signal line always starts charging from V 2  volts regardless of the number of clock period the digital signal is low. It can therefore be seen that the voltages between which the signal line is charged and discharged is the same regardless of the pattern of the digital signal applied to the signal line. For this reason, signal jitter of the type exemplified by  FIGS. 1 and 2  does not occur. 
         [0020]    A de-emphasis system  10  according to one example of the invention is shown in  FIG. 4 . The digital signal to be transmitted is applied to an input terminal  14  and is routed through two signal paths  16 ,  18 . The first signal path  16  includes a multiplier  20  that multiples the digital signal by 1-D 1 , where D 1  is the change in the digital signal after the first clock period that the signal remains high. In the example shown in  FIG. 3 , D 1  is equal to V*−V 1 . For example, if D 1 =0.25, the multiplier  20  multiplies the digital signal by 0.75. Therefore, if the digital signal transitions between 0 and 1 volts, the signal at the output of the multiplier  20  will transition between 0 and 0.75 volts. 
         [0021]    The second signal path  18  includes a delay circuit  24  followed by a second multiplier  26 . The delay circuit  24  delays the digital signal applied to the input terminal  14  by one clock period. The multiplier  26  multiples the digital signal by D 2 , where D 2  is the change in the digital signal after the first clock period that the signal remains low. Although D 2  need not be equal to D 1 , it will be assumed for purposes of illustration that such is the case. In the example shown in  FIG. 3 , D 2  is equal to V 2 . If D 2  is also equal to 0.25, the multiplier will multiply the digital signal by 0.25. 
         [0022]    The respective outputs of the multipliers  20 ,  26  are applied to a differential adder  30  that subtracts the output of the second multiplier  26  from the output of the first multiplier  20 . The resulting output is applied to a level translator circuit  34 . The level translator circuit  34  adds a fixed offset to the signal at the output of the adder  30 , which, for purposes of illustration is presumed to be equal to D, where D=D 1 =D 2 . The voltage levels present in the de-emphasis circuit  10  referenced by the letters shown in  FIG. 4  for the digital signal shown in  FIG. 3  in which D 1 =D 2 =0.25 are as follows 
         [0000]    
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Time 
                 A 
                 B 
                 C 
                 D 
                 E 
                 F 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 t0 
                 1 
                 0.75 
                   
                   
                   
                   
               
               
                 0 
                 0 
                 0 
                 1 
                 0.25 
                 −0.25 
                 0 
               
               
                   
                 1 
                 0.75 
                 0 
                 0 
                 0.75 
                 1 
               
               
                   
                 1 
                 0.75 
                 1 
                 0.25 
                 0.5 
                 0.75 
               
               
                   
                 1 
                 0.75 
                 1 
                 0.25 
                 0.5 
                 0.75 
               
               
                   
                 0 
                 0 
                 1 
                 0.25 
                 −0.25 
                 0 
               
               
                   
                 1 
                 0.75 
                 0 
                 0 
                 0.75 
                 1 
               
               
                   
                 0 
                 0 
                 1 
                 0.25 
                 −0.25 
                 0 
               
               
                   
                 0 
                 0 
                 0 
                 0 
                 0 
                 0.25 
               
               
                   
                 1 
                 0.75 
                 0 
                 0 
                 0.75 
                 1 
               
               
                   
               
             
          
         
       
     
         [0023]    It can be seen that column “F” of Table 1 corresponds to the voltage levels shown in the solid line in  FIG. 3 . 
         [0024]    A computer system  50  using the de-emphasis system  10  shown in  FIG. 4  is shown in  FIG. 5 . The computer system  50  includes a processor  52  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  52  includes a processor bus  54  that normally includes an address bus, a control bus, and a data bus. In addition, the computer system  50  includes one or more input devices  54 , such as a keyboard or a mouse, coupled to the processor  52  to allow an operator to interface with the computer system  50 . Typically, the computer system  50  also includes one or more output devices  56  coupled to the processor  52 , such output devices typically being a printer or a video terminal. One or more data storage devices  58  are also typically coupled to the processor  52  to allow the processor  52  to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices  58  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  52  is also typically coupled to cache memory  66 , which is usually static random access memory (“SRAM”). 
         [0025]    The computer system  50  also includes system memory  70 , which is in the form of several registered double in-line memory modules (“DIMMs”)  74 . Each of the DIMMs  74  includes a register  76  coupled to several dynamic random access memory (“DRAM”) devices  78  by a system of buses  80  that includes a command bus, an address bus and a data bus. The registers  76  each include a respective de-emphasis system  84  coupled to each of the address bus signals lines, which couple addresses to the DRAM devices  78 . The de-emphasis system  84  may also be coupled to each of the command bus lines, which transmit memory commands to the DRAM devices  78 . Finally, the de-emphasis system  84  may be coupled to each of the data bus lines, which transmit write data to the DRAM devices  78 . Therefore, even though the signal lines of the buses  80  may be highly capacitive, the signals are transmitted from the registers  76  to the DRAM devices  78  with very low signal jitter. 
         [0026]    Each of the DIMMs  74  is coupled to a memory controller  90 , which is connected to the processor  52  through the processor bus  54 . The DIMMs  74  are coupled to the memory controller  90  by a system of buses  92  that again includes a command bus, an address bus and a data bus. The memory controller  90  includes a de-emphasis system  94  coupled to each of the address bus signals lines for transmitted addresses to the DIMMs  74  with relatively low jitter. The de-emphasis system  94  may also be coupled to each of the command bus lines and the data bus lines for transmitting memory commands and write data, respectively, to the DIMMs  74  with relatively low jitter. 
         [0027]    Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.