Abstract:
According to this invention, there is provided a semiconductor device having conversion units which change the reference potential of an input signal to a first or second reference potential and outputs the input signal to a first drive unit or second drive unit, change the reference potential of a first control signal output from the first drive unit to the second reference potential and outputs the first control signal to the second drive unit, and changes the reference potential of a second control signal output from the second drive unit to the first reference potential and outputs the second control signal to the first drive unit, wherein the conversion units increase currents flowing through the conversion units on the basis of a time when the input signal changes.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims benefit of priority under 35 USC 119 from the Japanese Patent Application No. 2005-258180, filed on Sep. 6, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     There are DC-DC converters which generate a desired level of DC voltage by converting an externally input DC voltage into a high-frequency AC voltage and smoothing the AC voltage and output the DC voltage to a subsequent circuit. A plurality of DC-DC converters of this type are mounted in, e.g., an electronic device such as a cellular phone handset which uses a battery as its power source and generate a plurality of voltages for respective functional blocks.  
         [0003]     In recent years, the operating frequencies of DC-DC converters have been increasing to cope with the lower voltage and higher current of a power source. For this reason, high-speed operation and high efficiency are required of a control circuit of a DC-DC converter. However, implementation of high-speed operation involves problems such as an increase in current consumption and an increase in circuit scale.  
       SUMMARY OF THE INVENTION  
       [0004]     According to one aspect of the present invention, there is provided a semiconductor device including first and second switching elements connected in series between first and second terminals with a predetermined potential difference between the terminals, and a control unit which controls connection states of the first and second switching elements on the basis of an input signal such that when one of the first and second switching elements enters an off state, the other switching element enters an on state, wherein the control unit has a first drive unit to which a first reference potential is applied as a reference potential and which generates and outputs a first control signal for controlling the connection state of the first switching element on the basis of the input signal and a second control signal, a second drive unit to which a second reference potential different from the first reference potential is applied as a reference potential and which generates and outputs the second control signal for controlling the connection state of the second switching element on the basis of the input signal and the first control signal, and a conversion unit which changes a reference potential of the input signal to one of the first and second reference potentials and outputs the input signal to one of the first and second drive units, changes a reference potential of the first control signal output from the first drive unit to the second reference potential and outputs the first control signal to the second drive unit, and changes a reference potential of the second control signal output from the second drive unit to the first reference potential and outputs the second control signal to the first drive unit, and the conversion unit increases a current flowing through the conversion unit on the basis of a time when the input signal changes. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  is a block diagram showing the configuration of a DC-DC converter according to a first embodiment of the present invention;  
         [0006]      FIG. 2  is a block diagram showing the configuration of a level shift circuit;  
         [0007]      FIG. 3  is a timing chart in the level shift circuit;  
         [0008]      FIG. 4  is a timing chart in a level shift circuit of a comparative example;  
         [0009]      FIG. 5  is a block diagram showing the configuration of a level shift circuit;  
         [0010]      FIG. 6  is a block diagram showing the configuration of a DC-DC converter according to a second embodiment of the present invention;  
         [0011]      FIG. 7  is a block diagram showing the configuration of a DC-DC converter according to a third embodiment of the present invention; and  
         [0012]      FIG. 8  is a block diagram showing the configuration of a DC-DC converter according to a fourth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]     Embodiments of the present invention will be explained below with reference to the drawings.  
       (1) First Embodiment  
       [0014]      FIG. 1  shows the configuration of a DC-DC converter  10  according to a first embodiment of the present invention. The DC-DC converter  10  generates a desired level of DC voltage by converting a DC voltage input from a voltage input terminal VIN into a high-frequency AC voltage and smoothing the AC voltage and outputs the DC voltage from a voltage output terminal VOUT.  
         [0015]     The DC-DC converter  10  has NMOS transistors Tr 10  and Tr 20  as switching elements. A source of the NMOS transistor Tr 10  and a drain of the NMOS transistor Tr 20  are connected, a drain of the NMOS transistor Tr 10  is connected to the voltage input terminal VIN, and a source of the NMOS transistor Tr 20  is connected to a ground terminal GND.  
         [0016]     The DC-DC converter  10  alternates the operation of turning on or off the NMOS transistors Tr 10  and Tr 20  with the reverse operation such that if an NMOS transistor Tr, one of the NMOS transistors Tr 10  and Tr 20  is brought into an off state, the other NMOS transistor Tr is brought into an on state. With this operation, an AC voltage is generated at a node LX which is the junction of the NMOS transistors Tr 10  and Tr 20 .  
         [0017]     More specifically, if the NMOS transistor Tr 10  is brought into the on state, and the NMOS transistor Tr 20  is brought into the off state, the node LX is connected to the voltage input terminal VIN. This changes the potential of the node LX to the same potential as that of the DC voltage applied from the voltage input terminal VIN.  
         [0018]     On the other hand, if the NMOS transistor Tr 10  is brought into the off state, and the NMOS transistor Tr 20  is brought into the on state, the node LX is connected to the ground terminal GND. This changes the potential of the node LX to 0 V.  
         [0019]     An AC voltage obtained in the above-described manner is smoothed by a low-pass filter composed of a coil L 10  connected between the node LX and the voltage output terminal VOUT and a capacitor C 10  connected between the voltage output terminal VOUT and the ground terminal GND. The AC voltage is outputted as a desired level of DC voltage from the voltage output terminal VOUT.  
         [0020]     The voltage level of the DC voltage is determined on the basis of the ratio (i.e., an on/off time ratio) between a period of time (i.e., an on time) during which the NMOS transistor Tr 10  is in the on state, and the DC voltage applied from the voltage input terminal VIN is selected as a potential to be generated at the node LX and a period of time (i.e., an off time) during which the NMOS transistor Tr 20  is in the on state, and 0 V is selected as the potential to be generated at the node LX.  
         [0021]     For this reason, the DC-DC converter  10  has a control circuit  20  which controls on/off operation for the NMOS transistors Tr 10  and Tr 20  in accordance with an on/off control signal for controlling the on/off time ratio supplied from a control signal input terminal ON/OFF.  
         [0022]     To prevent the NMOS transistors Tr 10  and Tr 20  from simultaneously entering the on state, the control circuit  20  first brings one of the NMOS transistors, the NMOS transistor Tr 10  or Tr 20  into the off state in accordance with the on/off control signal. The control circuit  20  notifies a drive circuit  70  or  60  for driving the other NMOS transistor Tr 20  or Tr 10  that the one NMOS transistor Tr 10  or Tr 20  has changed to the off state, thereby bringing the other NMOS transistor Tr 20  or Tr 10  into the on state. The control circuit  20  notifies the drive circuit  60  or  70  for driving the NMOS transistor Tr 10  or Tr 20  that the other NMOS transistor Tr 20  or Tr 10  has changed to the on state.  
         [0023]     As described above, the control circuit  20  notifies one of the NMOS transistors Tr 10  and Tr 20  of the connection state of the other and notifies the other of the connection state of the one. With this operation, the control circuit  20  controls the on/off operation for the NMOS transistors Tr 10  and Tr 20  such that if one of the NMOS transistors, the NMOS transistor Tr 10  or Tr 20  is brought into the off state, the other NMOS transistor Tr 20  or Tr 10  is brought into the on state.  
         [0024]     Of the NMOS transistors Tr 10  and Tr 20 , the NMOS transistor Tr 20  uses, as its reference potential, a potential applied from the ground terminal GND, i.e., 0 V while the NMOS transistor Tr 10  uses, as its reference potential, a potential generated at the node LX.  
         [0025]     The control circuit  20  has a PMOS transistor Tr 50  and an NMOS transistor Tr 60  as circuits for driving the NMOS transistor Tr 20 . A drain of the PMOS transistor Tr 50  and a drain of the NMOS transistor Tr 60  are connected, and the junction of the transistors is connected to a gate of the NMOS transistor Tr 20 . A source of the PMOS transistor Tr 50  is connected to a power supply terminal VDD, and a source of the NMOS transistor Tr 60  is connected to the ground terminal GND. For this reason, the PMOS transistor Tr 50  and NMOS transistor Tr 60  use 0 V as their reference potentials.  
         [0026]     The control circuit  20  also has a PMOS transistor Tr 30  and an NMOS transistor Tr 40  as circuits for driving the NMOS transistor Tr 10 . A drain of the PMOS transistor Tr 30  and a drain of the NMOS transistor Tr 40  are connected, and the junction of the transistors is connected to a gate of the NMOS transistor Tr 10 . A source of the PMOS transistor Tr 30  is connected to a terminal BST, and a source of the NMOS transistor Tr 40  is connected to the node LX. For this reason, the PMOS transistor Tr 30  and NMOS transistor Tr 40  use the potential generated at the node LX as their reference potentials.  
         [0027]     Note that a zener diode ZD is connected between the terminal BST and the power supply terminal VDD. A cathode of the zener diode ZD is connected to the terminal BST while an anode thereof is connected to the power supply terminal VDD. A capacitor C 20  is connected between the terminal BST and the node LX.  
         [0028]     The zener diode ZD and capacitor C 20  form a constant voltage circuit. For this reason, the potential of the terminal BST changes in response to a change in the potential of the node LX such that the potential difference between the terminal BST and the node LX is kept constant.  
         [0029]     As described above, in the control circuit  20 , the circuits for driving the NMOS transistor Tr 20  use, as their reference potentials, 0 V, i.e., a low reference potential while the circuits for driving the NMOS transistor Tr 10  use, as their reference potentials, the potential generated at the node LX, i.e., a high reference potential.  
         [0030]     Accordingly, when transferring a signal with the low reference potential to the drive circuit  60  on the high reference potential side, the control circuit  20  needs to convert the signal with the low reference potential into one with the high reference potential (change the reference potential from the low reference potential to the high reference potential) and transfer the resulting signal to the drive circuit  60  on the high reference potential side.  
         [0031]     When transferring a signal with the high reference potential to the drive circuit  70  on the low reference potential side, the control circuit  20  needs to convert the signal with the high reference potential into one with the low reference potential (change the reference potential from the high reference potential to the low reference potential) and transfer the resulting signal to the drive circuit  70  on the low reference potential side.  
         [0032]     For this reason, the control circuit  20  has level shift circuits  30  and  40  for converting a signal with the low reference potential into one with the high reference potential used to transfer a signal with the low reference potential to the drive circuit  60  on the high reference potential side and a level shift circuit  50  for converting a signal with the high reference potential into one with the low reference potential used to transfer a signal with the high reference potential to the drive circuit  70  on the low reference potential side.  
         [0033]     When a signal of “L” level is input from the control signal input terminal ON/OFF as the on/off control signal with the low reference potential, the control circuit  20  inverts the level of the signal with an inverter INV 10  and outputs the obtained signal of “H” level to the level shift circuit  30  on the high reference potential side. At the same time, the control circuit  20  further inverts the level of the signal from “H” level to “L” level with an inverter INV 20  and outputs the obtained signal of “L” level to the drive circuit  70  on the low reference potential side.  
         [0034]     The level shift circuit  30  converts the signal of “H” level with the low reference potential into one of “H” level with the high reference potential and outputs the resulting signal to the drive circuit  60 . If at least one of two input signals is at “H” level, the drive circuit  60  outputs a signal of “H” level to both the PMOS transistor Tr 30  and NMOS transistor Tr 40 . On the other hand, if both the input signals are at “L” level, the drive circuit  60  outputs a signal of “L” level to both the PMOS transistor Tr 30  and NMOS transistor Tr 40 .  
         [0035]     In this example, the drive circuit  60  outputs a signal of “H” level to both the PMOS transistor Tr 30  and NMOS transistor Tr 40  to bring the PMOS transistor Tr 30  into the off state and the NMOS transistor Tr 40  into the on state.  
         [0036]     This causes the gate of the NMOS transistor Tr 10  to be connected to the node LX via the NMOS transistor Tr 40 , and as a result, the NMOS transistor Tr 10  is brought into the off state.  
         [0037]     An on/off detection circuit  80  is a circuit for detecting whether the NMOS transistor Tr 10  is in the on state or off state. When the on/off detection circuit  80  detects that the NMOS transistor Tr 10  has changed to the off state, it outputs a signal of “L” level with the high reference potential to the level shift circuit  50 .  
         [0038]     The level shift circuit  50  converts the signal of “L” level with the high reference potential into one of “L” level with the low reference potential and outputs the resulting signal to the drive circuit  70 . When the signal of “L” level is supplied from the inverter INV 20 , and the signal of “L” level is supplied from the level shift circuit  50 , the drive circuit  70  outputs a signal of “L” level to both the PMOS transistor Tr 50  and NMOS transistor Tr 60  to bring the PMOS transistor Tr 50  into the on state and the NMOS transistor Tr 60  into the off state.  
         [0039]     This causes the gate of the NMOS transistor Tr 20  to be connected to the power supply terminal VDD via the PMOS transistor Tr 50 , and as a result, the NMOS transistor Tr 20  is brought into the on state.  
         [0040]     When an on/off detection circuit  90  detects that the NMOS transistor Tr 20  has changed to the on state, it outputs a signal of “H” level with the low reference potential to the level shift circuit  40 . After the level shift circuit  40  converts the signal into one of “H” level with the high reference potential, it outputs the resulting signal to the drive circuit  60 .  
         [0041]     In this case, since the drive circuit  60  continues to output the signal of “H” level to both the PMOS transistor Tr 30  and NMOS transistor Tr 40 , the NMOS transistor Tr 10  remains in the off state.  
         [0042]     After that, when the on/off control signal changes from “L” level to “H” level, the control circuit  20  inverts the level of the signal with the inverter INV 10 , converts the obtained signal of “L” level into one of “L” level with the high reference potential in the level shift circuit  30 , and outputs the resulting signal to the drive circuit  60 . At the same time, the control circuit  20  further inverts the level of the signal with the inverter INV 20  and outputs the obtained signal of “H” level to the drive circuit  70 .  
         [0043]     In this case, the drive circuit  70  outputs a signal of “H” level to both the PMOS transistor Tr 50  and NMOS transistor Tr 60  to bring the PMOS transistor Tr 50  into the off state and the NMOS transistor Tr 60  into the on state.  
         [0044]     This causes the gate of the NMOS transistor Tr 20  to be connected to the ground terminal GND via the NMOS transistor Tr 60 , and as a result, the NMOS transistor Tr 20  is brought into the off state.  
         [0045]     When the on/off detection circuit  90  detects that the NMOS transistor Tr 20  has changed to the off state, it outputs a signal of “L” level with the low reference potential to the level shift circuit  40 . After the level shift circuit  40  converts the signal into one of “L” level with the high reference potential, it outputs the resulting signal to the drive circuit  60 .  
         [0046]     When the signal of “L” level is supplied from the level shift circuit  30 , and the signal of “L” level is supplied from the level shift circuit  40 , the drive circuit  60  outputs a signal of “L” level to both the PMOS transistor Tr 30  and NMOS transistor Tr 40  to bring the PMOS transistor Tr 30  into the on state and the NMOS transistor Tr 40  into the off state.  
         [0047]     This causes the gate of the NMOS transistor Tr 10  to be connected to the terminal BST via the PMOS transistor Tr 30 , and as a result, the NMOS transistor Tr 10  is brought into the on state.  
         [0048]     When the on/off detection circuit  80  detects that the NMOS transistor Tr 10  has changed to the on state, it outputs a signal of “H” level with the high reference potential to the level shift circuit  50 . After the level shift circuit  50  converts the signal into one of “H” level with the low reference potential, it outputs the resulting signal to the drive circuit  70 .  
         [0049]     In this case, since the drive circuit  70  continues to output the signal of “H” level to both the PMOS transistor Tr 50  and NMOS transistor Tr 60 , the NMOS transistor Tr 20  remains in the off state.  
         [0050]     In this embodiment, the control circuit  20  inputs the on/off control signal with the low reference potential, having been supplied from the control signal input terminal ON/OFF, to the level shift circuits  30  and  40 . Since the control circuit  20  needs to input the on/off control signal to the level shift circuit  50  after converting the signal into one with the high reference potential, it inputs, to the level shift circuit  50 , a signal output from the level shift circuit  30 . The control circuit  20  also has an LX state determination circuit  100 . The LX state determination circuit  100  determines the state, i.e., potential of the node LX and outputs the determination result as a LX state determination signal to the level shift circuits  30  to  50 .  
         [0051]     To implement high-speed operation and high efficiency, the control circuit  20  needs to shorten time (i.e., dead time) from when one of the NMOS transistors Tr 10  and Tr 20  is brought into the off state to when the other NMOS transistor Tr 20  or Tr 10  is brought into the on state.  
         [0052]     For this reason, the level shift circuits  30  to  50  are required to transfer signals at high speed. The signal transfer speeds of the level shift circuits  30  to  50  depend on respective driving currents in the level shift circuits  30  to  50 .  
         [0053]     Accordingly, each of the level shift circuits  30  to  50  is configured to increase the signal transfer speed by increasing a driving current therein on the basis of a time when the on/off control signal changes.  
         [0054]     In this case, each of the level shift circuits  30  to  50  needs to set a driving current increase time such that the driving current increases at least until the potential of the node LX changes. The level shift circuit  30  to  50  decreases the increased driving current after the potential of the node LX changes, on the basis of the LX state determination signal supplied from the LX state determination circuit  100 .  
         [0055]      FIG. 2  shows the configuration of the level shift circuit  30 , which converts a signal with the low reference potential into one with the high reference potential.  FIG. 3  shows an example of a timing chart in the level shift circuit  30 . An input terminal IN is connected to a gate of an NMOS transistor Tr 90  and also connected to a gate of an NMOS transistor Tr 70  via an inverter INV 30 .  
         [0056]     A source of the NMOS transistor Tr 90  is connected to the ground terminal GND via a constant current source  130 . A drain of an NMOS transistor Tr 100  is connected to the junction of the source of the NMOS transistor Tr 90  and the constant current source  130 , and the ground terminal GND is connected to a source of the NMOS transistor Tr 100 .  
         [0057]     An edge pulse circuit  110  is connected to a gate of the NMOS transistor Tr 100 . The on/off control signal input from the control signal input terminal ON/OFF via an inverter INV 50  and the LX state determination signal input from the LX state determination circuit  100  via a determination input terminal LXDT are input to the edge pulse circuit  110 .  
         [0058]     A source of the NMOS transistor Tr 70  is connected to the ground terminal GND via a constant current source  140 . A drain of the NMOS transistor Tr 80  is connected to the junction of the source of the NMOS transistor Tr 70  and the constant current source  140 , and the ground terminal GND is connected to a source of the NMOS transistor Tr 80 .  
         [0059]     An edge pulse circuit  120  is connected to a gate of the NMOS transistor Tr 80 . The on/off control signal input from the control signal input terminal ON/OFF and the LX state determination signal input from the LX state determination circuit  100  via the determination input terminal LXDT are input to the edge pulse circuit  120 .  
         [0060]     A drain of a PMOS transistor Tr 130  is connected to a drain of the NMOS transistor Tr 90 . The terminal BST is connected to sources of the PMOS transistor Tr 130  and a PMOS transistor Tr 140 . Gates of the PMOS transistors Tr 130  and Tr 140  are connected to each other, and the drain of the PMOS transistor Tr 130  is connected to the junction of the gates. For this reason, the PMOS transistors Tr 130  and Tr 140  form a current mirror circuit.  
         [0061]     A drain of a PMOS transistor Tr 110  is connected to a drain of the NMOS transistor Tr 70 . The terminal BST is connected to sources of the PMOS transistor Tr 110  and a PMOS transistor Tr 120 . Gates of the PMOS transistors Tr 110  and Tr 120  are connected to each other, and the drain of the PMOS transistor Tr 110  is connected to the junction of the gates. For this reason, the PMOS transistors Tr 110  and Tr 120  form a current mirror circuit.  
         [0062]     A drain of an NMOS transistor Tr 150  is connected to a drain of the PMOS transistor Tr 140 , and a drain of an NMOS transistor Tr 160  is connected to a drain of the PMOS transistor Tr 120 . Sources of the NMOS transistors Tr 150  and Tr 160  are connected to the node LX via a terminal LX. An output terminal OUT is connected to the junction of the PMOS transistor Tr 120  and the NMOS transistor Tr 160  via an inverter INV 40 .  
         [0063]     Gates of the NMOS transistors Tr 150  and Tr 160  are connected to each other, and the drain of the NMOS transistor Tr 150  is connected to the junction of the gates. For this reason, the NMOS transistors Tr 150  and Tr 160  form a current mirror circuit.  
         [0064]     When an input signal ( FIG. 3 ( b )) with the low reference potential input from the input terminal IN changes from “L” level to “H” level (time t 20 ), the NMOS transistor Tr 70  enters the off state ( FIG. 3 ( e )), and the NMOS transistor Tr 90  enters the on state ( FIG. 3 ( c )).  
         [0065]     In this case, since the NMOS transistor Tr 70  enters the off state, no current flows through the PMOS transistor Tr 110 . Due to the characteristics of the current mirror circuit, no current flows through the PMOS transistor Tr 120  as well.  
         [0066]     In the meantime, since the NMOS transistor Tr 90  enters the on state, a current equal to one which flows through the NMOS transistor Tr 90  flows through the PMOS transistor Tr 130 . Due to the characteristics of the current mirror circuit, a current equal to that which flows through the NMOS transistor Tr 90  flows through the PMOS transistor Tr 140  as well. Additionally, a current equal to that which flows through the NMOS transistor Tr 90  flows through the NMOS transistor Tr 150 .  
         [0067]     Due to the characteristics of the current mirror circuit, there arises a force trying to feed, to the NMOS transistor Tr 160 , a current equal to that for the NMOS transistor Tr 90 . However, since the PMOS transistor Tr 120  is in the off state, no current flows through the NMOS transistor Tr 160 .  
         [0068]     For this reason, the potential difference between the drain and source of the NMOS transistor Tr 160  becomes almost 0 V, and as a result, the potential of a node ND changes to the same potential as that of the node LX applied from the terminal LX, i.e., a signal of “L” level with the high reference potential. The inverter INV 40  inverts the level of a signal of “L” level with the high reference potential and outputs the obtained signal of “H” level with the high reference potential from the output terminal OUT.  
         [0069]     In this embodiment, at a time when the on/off control signal ( FIG. 3 ( a )) changes from “H” level to “L” level (time t 10 ), the edge pulse circuit  110  outputs a signal of “H” level to the gate of the NMOS transistor Tr 100  ( FIG. 3 ( d )) to bring the NMOS transistor Tr 100  into the on state.  
         [0070]     As a result, a current which is the sum of a current which flows through the constant current source  130  and one which flows through the NMOS transistor Tr 100  flows through the NMOS transistor Tr 90 . The large increase in the current, which flows through the NMOS transistor Tr 90 , i.e., a driving current makes it possible to increase the signal transfer speed. The increase in the driving current before the input signal input from the input terminal IN changes from “L” level to “H” level makes it possible to improve the stability of the operation of the level shift circuit  30 .  
         [0071]     After that, if the potential of the node LX changes from the same potential as that of the DC voltage input from the voltage input terminal VIN to 0 V, and the LX state determination signal ( FIG. 3 ( g )) changes from “H” level to “L” level (time t 30 ), the edge pulse circuit  110  outputs a signal of “L” level to the gate of the NMOS transistor Tr 100  ( FIG. 3 ( d )) to bring the NMOS transistor Tr 100  into the off state (time t 40 ).  
         [0072]     As a result, a current equal to that which flows through the constant current source  130  flows through the NMOS transistor Tr 90 . The current, which flows through the NMOS transistor Tr 90 , decreases to a level just enough to maintain the output state of the output terminal OUT.  
         [0073]     The decrease in the increased driving current on the basis of the time when the potential of the node LX changes makes it possible to suppress the driving current increase time to the minimum necessary and thus implement a decrease in current consumption. The decrease also has the effect of eliminating the need to provide, in the edge pulse circuit  110 , a CR circuit for setting the driving current increase time. This makes it possible to implement a decrease in circuit scale.  
         [0074]     When the input signal ( FIG. 3 ( b )) with the low reference potential input from the input terminal IN changes from “H” level to “L” level (time t 60 ), the NMOS transistor Tr 70  enters the on state ( FIG. 3 ( e )), and the NMOS transistor Tr 90  enters the off state ( FIG. 3 ( c )).  
         [0075]     In this case, since the NMOS transistor Tr 90  enters the off state, no current flows through the PMOS transistor Tr 130 . Due to the characteristics of the current mirror circuit, no current flows through the PMOS transistor Tr 140  as well. For this reason, no current flows through the NMOS transistor Tr 150 . Due to the characteristics of the current mirror circuit, no current flows through the NMOS transistor Tr 160  as well.  
         [0076]     In the meantime, since the NMOS transistor Tr 70  enters the on state, a current equal to one which flows through the NMOS transistor Tr 70  flows through the PMOS transistor Tr 110 . Due to the characteristics of the current mirror circuit, there arises a force trying to feed, to the PMOS transistor Tr 120 , a current equal to that for the NMOS transistor Tr 70 . However, since the NMOS transistor Tr 160  is in the off state, no current flows through the PMOS transistor Tr 120 .  
         [0077]     For this reason, the potential difference between the drain and source of the PMOS transistor Tr 120  becomes almost 0 V, and as a result, the potential of the node ND changes to the same potential as that applied from the terminal BST, i.e., the high reference potential (“H” level). The inverter INV 40  inverts the level of a signal of “H” level with the high reference potential and outputs the obtained signal of “L” level with the high reference potential from the output terminal OUT.  
         [0078]     As in the above-described case, at a time when the on/off control signal ( FIG. 3 ( a )) changes from “L” level to “H” level (time t 50 ), the edge pulse circuit  120  outputs a signal of “H” level to the gate of the NMOS transistor Tr 80  ( FIG. 3 ( f )) to bring the NMOS transistor Tr 80  into the on state.  
         [0079]     As a result, a current which is the sum of a current which flows through the constant current source  140  and one which flows through the NMOS transistor Tr 80  flows through the NMOS transistor Tr 80 . This largely increases the current, which flows through the NMOS transistor Tr 70 , i.e., the driving current.  
         [0080]     After that, if the potential of the node LX changes from 0 V to the same potential as that of the DC voltage input from the voltage input terminal VIN, and the LX state determination signal ( FIG. 3 ( g )) changes from “L” level to “H” level (time t 70 ), the edge pulse circuit  120  outputs a signal of “L” level to the gate of the NMOS transistor Tr 80  ( FIG. 3 ( f )) to bring the NMOS transistor Tr 80  into the off state.  
         [0081]     As a result, a current equal to that which flows through the constant current source  140  flows through the NMOS transistor Tr 70 . The current, which flows through the NMOS transistor Tr 70 , decreases to a level just enough to maintain the output state of the output terminal OUT.  
         [0082]      FIG. 4  shows, as a comparative example, an example of a timing chart in the case (FIGS.  4 ( d ) and  4 ( f )) of increasing the driving current from a time (time t 20  or t 60 ) when a signal input to the level shift circuit ( FIG. 4 ( b )) changes to a time (time t 100  or t 110 ) set by a time constant CR for a CR circuit of the edge pulse circuit.  
         [0083]     In this comparative example, the driving current increase time needs to be set to be longer such that it includes time to spare, in consideration of variations in switching time among the NMOS transistors Tr 10  and Tr 20  and the like and variations in CR elements. Such prolongation of the driving current increase time causes an increase in current consumption and thus creates the need to provide a CR circuit with a large time constant CR. This causes a problem of an increase in circuit scale.  
         [0084]     Note that the level shift circuit  40  has the same configuration as the level shift circuit  30 . However, when the level shift circuit  40  notifies the drive circuit  60  that the NMOS transistor Tr 20  has changed to the on state, the NMOS transistor Tr 10  remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when an increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit having increased the driving current.  
         [0085]      FIG. 5  shows the configuration of the level shift circuit  50 , which converts a signal with the high reference potential into one with the low reference potential. The level shift circuit  50  is formed by reversing the plus and minus signs of circuit elements included in the level shift circuit  30  ( FIG. 2 ) except for an inverter INV 150  provided at the preceding stage of an edge pulse circuit  210 .  
         [0086]     More specifically, the level shift circuit  50  has an inverter INV 130  and the inverter INV 150 , the edge pulse circuit  210  and an edge pulse circuit  220 , constant current sources  230  and  240 , PMOS transistors Tr 170  to TR 200 , NMOS transistors Tr 210  and Tr 220 , NMOS transistors Tr 230  and Tr 240 , and PMOS transistors Tr 250  and Tr 260 . Each of the pair of NMOS transistors, Tr 210  and Tr 220 , the pair of NMOS transistors, Tr 230  and Tr 240 , and the pair of PMOS transistors, Tr 250  and Tr 260  form a current mirror circuit.  
         [0087]     Note that similarly to the level shift circuit  40 , when the level shift circuit  50  notifies the drive circuit  70  that the NMOS transistor Tr 10  has changed to the on state, the NMOS transistor Tr 20  remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when an increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit having increased the driving current.  
         [0088]     As described above, according to this embodiment, it is possible to implement high-speed operation and at the same time implement a decrease in current consumption and circuit scale.  
       (2) Second Embodiment  
       [0089]      FIG. 6  shows the configuration of a DC-DC converter  300  according to a second embodiment of the present invention. Note that the same components as those shown in  FIG. 1  are denoted by the same reference numerals and that an explanation thereof will be omitted. Level shift circuits  320  to  340  have the same configurations as the corresponding level shift circuits  30  to  50  ( FIGS. 2 and 5 ) except for edge pulse circuits.  
         [0090]     The potential of a node LX changes in response to a change in signals indicating the connection states of NMOS transistors Tr 10  and Tr 20  output from on/off detection circuits  80  and  90 . Accordingly, in this embodiment, each of the level shift circuits  320  to  340  determines a time when an increased driving current is decreased using a signal notifying, of the connection state of one of the NMOS transistors Tr 10  and Tr 20 , a drive circuit  70  or  60  for driving the other NMOS transistor Tr 20  or Tr 10 , i.e., a signal output from the on/off detection circuit  80  or  90 .  
         [0091]     The level shift circuit  320  inputs a signal output from the on/off detection circuit  90  to an edge pulse circuit (one corresponding to the edge pulse circuit  110  of the level shift circuit  30  in  FIG. 2 ) used to transfer an on/off control signal of “L” level (one for bringing the NMOS transistor Tr 10  into an off state).  
         [0092]     The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “H” level to “L” level. After that, when the NMOS transistor Tr 20  changes to an on state, and the potential of the node LX changes to 0V, the signal output from the on/off detection circuit  90  changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.  
         [0093]     The level shift circuit  320  inputs a signal output from the on/off detection circuit  80  after converting the signal into one with a low reference potential in the level shift circuit  340  to an edge pulse circuit (one corresponding to the edge pulse circuit  120  of the level shift circuit  30  in  FIG. 2 ) used to transfer the on/off control signal of “H” level (one for bringing the NMOS transistor Tr 10  into the on state).  
         [0094]     The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when the NMOS transistor Tr 10  changes to the on state, and the potential of the node LX changes to the same potential as that of a DC voltage applied from a voltage input terminal VIN, the signal output from the on/off detection circuit  80  via the level shift circuit  340  changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.  
         [0095]     The level shift circuit  330  inputs the signal output from the on/off detection circuit  80  after converting the signal into one with the low reference potential in the level shift circuit  340  to an edge pulse circuit (one corresponding to the edge pulse circuit  120  of the level shift circuit  20  in  FIG. 2 ) used to make a notification that the NMOS transistor Tr 20  has changed to the off state.  
         [0096]     The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when the NMOS transistor Tr 10  changes to the on state, and the potential of the node LX changes to the same potential as that of the DC voltage input from the voltage input terminal VIN, the signal output from the on/off detection circuit  80  via the level shift circuit  340  changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.  
         [0097]     Note that when the level shift circuit  330  notifies the drive circuit  60  that the NMOS transistor Tr 20  has changed to the on state, the NMOS transistor Tr 10  remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when the increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit  110  of the level shift circuit  20  in  FIG. 2 ) used to make a notification that the NMOS transistor Tr 20  has changed to the on state.  
         [0098]     The level shift circuit  340  inputs the signal output from the on/off detection circuit  90  after converting the signal into one with a high reference potential in the level shift circuit  330  to an edge pulse circuit (one corresponding to the edge pulse circuit  210  of the level shift circuit  50  in  FIG. 5 ) used to make a notification that the NMOS transistor Tr 10  has changed to the off state.  
         [0099]     The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “H” level to “L” level. After that, when the NMOS transistor Tr 20  changes to the on state, and the potential of the node LX changes to 0 V, the signal output from the on/off detection circuit  90  via the level shift circuit  330  changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.  
         [0100]     Note that when the level shift circuit  340  notifies the drive circuit  70  that the NMOS transistor Tr 10  has changed to the on state, the NMOS transistor Tr 20  remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when the increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit  220  of the level shift circuit  50  in  FIG. 5 ) used to make a notification that the NMOS transistor Tr 10  has changed to the on state.  
         [0101]     As described above, according to this embodiment, it is possible to increase signal transfer speed and at the same time implement a decrease in current consumption and circuit scale. Also, this embodiment eliminates the need to provide the LX state determination circuit  100  ( FIG. 1 ) and makes it possible to decrease CR circuits in the edge pulse circuits of the level shift circuits  320  to  340 .  
       (3) Third Embodiment  
       [0102]      FIG. 7  shows the configuration of a DC-DC converter  400  according to a third embodiment of the present invention. Note that the same components as those shown in  FIG. 1  are denoted by the same reference numerals and that an explanation thereof will be omitted.  
         [0103]     In this embodiment, a control circuit  410  has a drive circuit  480  for driving a PMOS transistor Tr 50  and a drive circuit  490  for driving an NMOS transistor Tr 60 .  
         [0104]     The drive circuits  480  and  490  are powered by different power sources. The drive circuit  490  uses, as a reference potential, 0 V, i.e., a low reference potential while the drive circuit  480  uses, as a reference potential, a potential between one applied from a power supply terminal VDD and 0 V (to be referred to as an intermediate reference potential hereinafter).  
         [0105]     This makes it possible to increase the gate threshold voltage of an NMOS transistor Tr 20  while maintaining the withstand voltages of the drive circuits  480  and  490 . Accordingly, it is possible to decrease the on-resistance of the NMOS transistor Tr 20  (a resistance generated between the source and drain when the NMOS transistor Tr 20  is brought into an on state).  
         [0106]     The control circuit  410  has a level shift circuit  450  for converting a signal with the low reference potential into one with the intermediate reference potential used to transfer a signal with the low reference potential to the drive circuit  480  on the intermediate reference potential side, and a level shift circuit  460  for converting a signal with the intermediate reference potential into one with the low reference potential used to transfer a signal with the intermediate reference potential to the drive circuit  490  on the low reference potential side.  
         [0107]     Note that the level shift circuit  450  is formed by connecting the inverter INV 50  connected at the preceding stage of the edge pulse circuit  110  in the level shift circuit  30  ( FIG. 2 ) to the preceding stage of the edge pulse circuit  120  and that the level shift circuit  460  has the same configuration as the level shift circuit  50  ( FIG. 5 ).  
         [0108]     When a signal of “L” level is input from a control signal input terminal ON/OFF as an on/off control signal with the low reference potential, the control circuit  410  sequentially inverts the level of the signal with inverters INV 10  and INV 20 . The control circuit  410  inputs the obtained signal of “L” level to the drive circuit  490  on the low reference potential side and the level shift circuit  450 . The level shift circuit  450  converts the signal of “L” level with the low reference potential into one of “L” level with the intermediate reference potential and outputs the resulting signal to the drive circuit  480 .  
         [0109]     When an NMOS transistor Tr 10  changes to an off state, and a signal of “L” level with a high reference potential is supplied from an on/off detection circuit  80 , a level shift circuit  440  converts the signal of “L” level with the high reference potential into one of “L” level with the intermediate reference potential and outputs the resulting signal to the drive circuit  480 .  
         [0110]     In this case, the drive circuit  480  outputs the signal of “L” level to the PMOS transistor Tr 50  to bring the PMOS transistor Tr 50  into the on state and outputs the signal of “L” level to the level shift circuit  460  to notify the level shift circuit  460  that the PMOS transistor Tr 50  has changed to the on state.  
         [0111]     The level shift circuit  460  converts the signal of “L” level with the intermediate reference potential into one of “L” level with the low reference potential and outputs the resulting signal to the drive circuit  490 . In this case, since the drive circuit  490  is supplied with the signals of “L” level from the level shift circuit  460  and inverter INV 20 , it outputs a signal of “L” level to the NMOS transistor Tr 60  to bring the NMOS transistor Tr 60  into the off state. At the same time, the drive circuit  490  outputs the signal of “L” level to the level shift circuit  450  to keep the PMOS transistor Tr 50  in the on state.  
         [0112]     This causes a gate of the NMOS transistor Tr 20  to be connected to the power supply terminal VDD via the PMOS transistor Tr 50 , and as a result, the NMOS transistor Tr 20  is brought into the on state.  
         [0113]     After that, when the on/off control signal changes from “L” level to “H” level, the control circuit  410  sequentially inverts the level of the signal with the inverters INV 10  and INV 20 . The control circuit  410  inputs the obtained signal of “H” level to the drive circuit  490  on the low reference potential side and the level shift circuit  450  on the intermediate reference potential side.  
         [0114]     The level shift circuit  450  converts the signal of “H” level with the low reference potential into one of “H” level with the intermediate reference potential and outputs the resulting signal to the drive circuit  480 . In this case, the drive circuit  480  outputs the signal of “H” level to the PMOS transistor Tr 50  to bring the PMOS transistor Tr 50  into the off state and outputs the signal of “H” level to the level shift circuit  460  to make a notification that the PMOS transistor Tr 50  has changed to the off state.  
         [0115]     The level shift circuit  460  converts the signal of “H” level with the intermediate reference potential into one of “H” level with the low reference potential and outputs the resulting signal to the drive circuit  490 . In this case, the drive circuit  490  outputs the signal of “H” level to the NMOS transistor Tr 60  to bring the NMOS transistor Tr 60  into the on state and outputs the signal of “H” level to the level shift circuit  450  to keep the PMOS transistor Tr 50  in the off state.  
         [0116]     This causes the gate of the NMOS transistor Tr 20  to be connected to a ground terminal GND via the NMOS transistor Tr 60 , and as a result, the NMOS transistor Tr 20  is brought into the off state.  
         [0117]     As in the first embodiment, the control circuit  410  inputs the on/off control signal supplied from the control signal input terminal ON/OFF to the level shift circuit  450 . Since the control circuit  410  needs to input the on/off control signal to the level shift circuit  460  after converting the signal into one with the intermediate reference potential, it inputs, to the level shift circuit  460 , a signal output from the level shift circuit  450 . An LX state determination circuit  100  outputs an LX state determination signal obtained by determining the state, i.e., potential of a node LX to the level shift circuits  450  and  460 .  
         [0118]     For this reason, similarly to the level shift circuits  30  to  50  ( FIG. 1 ) according to the first embodiment, each of the level shift circuits  450  and  460  increases a driving current therein on the basis of a time when the on/off control signal changes. After that, the level shift circuit decreases the increased driving current on the basis of a time when the potential of the node LX changes.  
         [0119]     Note that when the PMOS transistor Tr 50  changes to the on state, and a drive circuit  60  is notified that the NMOS transistor Tr 20  has changed to the on state, the NMOS transistor Tr 10  remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when an increased driving current is decreased in the level shift circuit  460 , which notifies the drive circuit  490  that the PMOS transistor Tr 50  has changed to the on state, is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit  210  of the level shift circuit  50  in  FIG. 5 ) used to make a notification that the PMOS transistor Tr 50  has changed to the on state.  
         [0120]     As described above, according to this embodiment, it is possible to increase signal transfer speed and at the same time implement a decrease in current consumption and circuit scale. Also, this embodiment makes it possible to increase the gate threshold voltage of the NMOS transistor Tr 20  and thus decrease the on-resistance of the NMOS transistor Tr 20 .  
       (4) Fourth Embodiment  
       [0121]      FIG. 8  shows the configuration of a DC-DC converter  500  according to a fourth embodiment of the present invention. Note that the same components as those shown in  FIGS. 1, 6 , and  7  are denoted by the same reference numerals and that an explanation thereof will be omitted.  
         [0122]     In this embodiment, a control circuit  510  has drive circuits  480  and  490  for separately driving a PMOS transistor Tr 50  and an NMOS transistor Tr 60 . Also, the control circuit  510  determines a time when an increased driving current is decreased in each of level shift circuits  320 ,  330 , and  540  to  560 , using signals output from on/off detection circuits  80  and  90 .  
         [0123]     Note that as in the third embodiment, the level shift circuit  550  is formed by connecting the inverter INV 50  connected at the preceding stage of the edge pulse circuit  110  in the level shift circuit  30  ( FIG. 2 ) to the preceding stage of the edge pulse circuit  120  and that the level shift circuit  560  has the same configuration as the level shift circuit  50  ( FIG. 5 ).  
         [0124]     The level shift circuit  550  inputs a signal output from the on/off detection circuit  90  to an edge pulse circuit (one corresponding to the edge pulse circuit  120  of the level shift circuit  30  in  FIG. 2 ) used to transfer an on/off control signal of “L” level (one for bringing an NMOS transistor Tr 20  into an on state).  
         [0125]     The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “H” level to “L” level. After that, when the NMOS transistor Tr 20  changes to the on state, and the potential of a node LX changes to 0 V, the signal output from the on/off detection circuit  90  changes from “L” level to “H” level. The edge pulse circuit decreases the increased driving current on the basis of the time when the signal changes to “H” level.  
         [0126]     The level shift circuit  550  inputs a signal output from the on/off detection circuit  80  after converting the signal into one with an intermediate reference potential in the level shift circuit  540  to an edge pulse circuit (one corresponding to the edge pulse circuit  110  of the level shift circuit  30  in  FIG. 2 ) used to transfer the on/off control signal of “H” level (one for bringing the NMOS transistor Tr 20  into an off state).  
         [0127]     The edge pulse circuit increases the driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when an NMOS transistor Tr 10  changes to the on state, and the potential of the node LX changes to the same potential as that of a DC voltage applied from a voltage input terminal VIN, the signal output from the on/off detection circuit  80  via the level shift circuit  540  changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.  
         [0128]     The level shift circuit  560  inputs the signal output from the on/off detection circuit  80  after converting the signal into one with the intermediate reference potential in the level shift circuit  540  to an edge pulse circuit (one corresponding to the edge pulse circuit  220  of the level shift circuit  50  in  FIG. 5 ) used to make a notification that the PMOS transistor Tr 50  has changed to the off state (the NMOS transistor Tr 20  has changed to the off state).  
         [0129]     The edge pulse circuit increases a driving current at a time when the on/off control signal changes from “L” level to “H” level. After that, when the NMOS transistor Tr 10  changes to the on state, and the potential of the node LX changes to the same potential as that of the DC voltage input from the voltage input terminal VIN, the signal output from the on/off detection circuit  80  via the level shift circuit  540  changes from “L” level to “H” level. The edge pulse circuit decreases the driving current on the basis of the time when the signal changes to “H” level.  
         [0130]     Note that when a notification is made that the PMOS transistor Tr 50  has changed to the on state (the NMOS transistor Tr 20  has changed to the on state), the NMOS transistor Tr 10  remains in the off state, and the potential of the node LX does not change. Accordingly, in this case, a time when the increased driving current is decreased is set by a time constant CR for a CR circuit of an edge pulse circuit (one corresponding to the edge pulse circuit  210  of the level shift circuit  50  in  FIG. 5 ) used to make a notification that the PMOS transistor Tr 50  has changed to the on state.  
         [0131]     As described above, according to this embodiment, it is possible to increase signal transfer speed and at the same time implement a decrease in current consumption and circuit scale. Also, this embodiment makes it possible to increase the gate threshold voltage of the NMOS transistor Tr 20  and thus decrease the on-resistance of the NMOS transistor Tr 20 . Additionally, this embodiment eliminates the need to provide the LX state determination circuit  100  ( FIG. 7 ) and makes it possible to decrease CR circuits in the edge pulse circuits of the level shift circuits  320 ,  330 , and  540  to  560 .  
         [0132]     Note that the above-described embodiments are merely examples and not intended to limit the present invention. For example, although the embodiments use the NMOS transistors Tr 10  and Tr 20  as switching elements, other various switching elements may be used instead.