Abstract:
The second-order inter-modulation distortion, originating in a differential passive mixer core from imbalance between devices, is reduced by compensating for the mismatch or load, by means of tuning the differential output impedance at the mixer core, or the input impedance of a filter coupled to the output of the passive mixer. Compensating for the imbalance allows greater suppression of even-order harmonics in the differential structure, which reduces second-order intermodulation at the output of the mixers. The compensation is achieved by tunable resistive elements that are calibrated by a built-in self-test architecture. The calibration circuit is deactivated during receiver operation.

Description:
TECHNICAL AREA 
       [0001]    The present invention relates generally to RF mixers, and in particular to a system, method, and calibration circuit for reducing second-order inter-modulation distortion, originating from imbalance between devices, in a differential passive mixer. 
       BACKGROUND 
       [0002]    A basic building block of a radio frequency (RF) communication receiver is the mixer. A mixer down-converts an RF signal received at an antenna to an intermediate frequency (IF)—or in some receiver designs, directly down-converts the received RF signal into a zero intermediate frequency (ZIF)—by multiplying the received signal with a local oscillator (LO) signal. A receiver using ZIF is also called homodyne or “direct conversion” receiver. A direct conversion receiver is easier to integrate on a chip than IF designs, as it eliminates pass-band filters and reduces the space and complexity as well as cost. 
         [0003]    A typical prior art receiver architecture  140  is depicted in  FIG. 11 . A received RF signal is amplified by a low noise amplifier (LNA)  142 . A Balun  144  transforms the received signal to one balanced about ground. In-phase (I) and quadrature (Q) mixers  146  down-convert the balanced RF signals to baseband by mixing the I and Q components, respectively, with clock signals having a 90-degree phase offset, from a local oscillator or clock generator/driver  148 . The baseband signals are then filtered by baseband low pass filters  150  to remove high frequency harmonics. 
         [0004]    Mixers  146  in practice may be designed as either active or passive circuits. Active mixers can provide gain while down-converting the RF signal, but are generally less linear and have higher noise figures. In particular, the flicker noise contribution is higher, which is harmful for narrow-band RF applications like GSM. 
         [0005]    RF communication systems usually demand a duplex operation mode in a transceiver, in which the receiver  140  and a transmitter work simultaneously. As the transmitter sends signals at high power levels, the receiver  140  will suffer from interference. As a result, very good linearity is required for both the LNA  142  and the mixer(s)  146 . This is particularly true for the mixer  146 , as the RF signal is amplified by the LNA  142 . For a direct conversion receiver  140 , protecting the receiver  140  from the interference created by a transmitter is very important. In particular, the second order inter-modulation product, IM 2 , must be kept low. The measure of this is known as the second order input intercept point (IIP 2 ). 
         [0006]    In order to obtain better IIP 2 , it is known to process differential RF signals in a balanced, or symmetric topology, to cancel out nonlinearities caused by the devices (e.g., transistors). Thus, a balun  144  is employed to perform single-end to differential conversion of the input RF signal. Ideally, the even orders of nonlinear distortions of differential signals could be cancelled between balanced positive and negative output nodes. This requires a perfect match between the transistors used in mixer cores  146  as well as the clock drivers  148 . In practice, any mismatch of transistors in mixer cores  146  and/or the clock drivers  148  will lead to limited suppression on IM 2 . 
         [0007]    One known approach to reducing the over-all component mismatch is to decrease the device spread by scaling up the device sizes. However, this approach has the disadvantage of consuming larger chip area, and more seriously also results in larger power consumption due to increased capacitive loading. 
         [0008]    For quadrature mixer operation, as shown in  FIG. 11 , a two-phase clock scheme does not work well, since the two output loads will interact with each other, resulting in lower conversion gain, lower linearity, and IQ leakage. Therefore, good isolation between the I and Q channels is required. One known remedy is to use a four-phase clock scheme, wherein four conducting time slots are non-overlapped and evenly spaced between I and Q without short-circuiting the two loads. 
       SUMMARY 
       [0009]    According to embodiments of the present invention, the second-order inter-modulation distortion, originating from imbalance between devices, is reduced by compensating for the mismatch in a differential passive mixer core or load, by means of tuning the differential output impedance at the mixer core, or the input impedance of a filter. Compensating for the imbalance allows greater suppression of even-order harmonics in the differential structure, which reduces second-order intermodulation at the output of the mixers. The compensation is achieved by tunable resistive elements that are calibrated by a built-in self-test architecture. The calibration circuit is deactivated during receiver operation. 
         [0010]    One embodiment relates to a method of reducing second order intermodulation in a differential passive mixer having a signal source, a mixer core including differentially-connected transistors, and a load, wherein the transistors are driven during a calibration mode by a clock driver. One or more tunable resistive elements are provided in the mixer core or load. The resistance of one or more tunable resistive elements is adjusted in a calibration procedure to compensate for mismatches between transistors in the differential mixer or clock driver. 
         [0011]    Another embodiment relates to a calibration circuit for reducing second order intermodulation in a differential passive mixer. The circuit includes a signal source and one or more mixer cores, each including differentially-connected transistors and tunable resistive elements. The circuit also includes a first switching matrix operative to selectively couple a mixer core to a measuring circuit, and a second switching matrix operative to selectively couple outputs of a selected mixer core to the measuring circuit. The circuit further includes a measuring circuit having two inputs, and operative to detect and quantify a current mismatch in signals coupled to the inputs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a schematic diagram of a differential passive mixer core with variable resistive elements in the load. 
           [0013]      FIG. 2  is a schematic diagram of one embodiment of a variable resistive element. 
           [0014]      FIG. 3  is a schematic diagram of differential passive mixer core with variable resistive elements in the core. 
           [0015]      FIG. 4  is a schematic diagram of complimentary differential passive mixer cores with variable resistive elements in the cores. 
           [0016]      FIG. 5  is a schematic diagram of a calibration circuit for a differential passive mixer core having variable resistive elements in the core, according to one embodiment. 
           [0017]      FIG. 6  is a timing diagram of four-phase, non-overlapping clock signals. 
           [0018]      FIG. 7  is a schematic diagram of a calibration circuit for a differential passive mixer core having variable resistive elements in the core, according to another embodiment. 
           [0019]      FIG. 8  is a schematic diagram of an equivalent circuit for the calibration circuit of  FIG. 7 . 
           [0020]      FIG. 9  is a timing diagram of two-phase, non-overlapping clock signals. 
           [0021]      FIG. 10  is a schematic diagram of a calibration circuit for a differential passive mixer core having variable resistive elements in the core, according to another embodiment. 
           [0022]      FIG. 11  is a schematic diagram of a prior art RF receiver circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Embodiments of the present invention use compensation techniques to calibrate the device mismatch present in the mixer cores and clock drivers.  FIG. 1  depicts a receiver circuit  10  including an RF source  14 , a passive mixer core  12  constructed from differentially-connected NMOS transistors, tunable resistor elements  16 , the outputs of the mixer core  12  are connected to load resistances  18  and an amplifier  20 . The inputs of the amplifier  20  represent a virtual ground node. In this embodiment, mismatches in the core  12  transistors, and/or transistors in a clock driver (not shown), give rise to an unbalanced output that fails to fully suppress even orders of nonlinear distortions in the output, giving rise to a second-order inter-modulation product. 
         [0024]    These mismatches in the core  12  may be offset by adjusting the differential output load—deliberately creating an imbalance which will compensate for the mixer core  12  imbalance. This load imbalance is achieved by adjusting the tunable resistor elements  16  in the load. By changing the values of R 1  and/or R 2 , the original balance between R 1  and R 2  can be changed. However, it is essential to realize that the mismatch in the mixer core  12  is very small, mainly determined by the process technology used for integration and device sizes. Hence the tuning of the resistor elements  16  will also be very small. 
         [0025]    One way to implement the tunable resistor elements  16  is depicted in  FIG. 2 . A plurality of large resistors  22  are selectively connected in parallel with a nominal resistor R 1   b  by an array of switches  24 . The value of the resistor element  16  is R 1 =R 1   a +R 1   b.  If R b &lt;&lt;R 1   a,  tuning of R 1   b  by means of connecting large RM resistances  22  in parallel will make fine tuning of R 1  possible. Of course, other means of varying the value of a tunable resistor element  16  are known, and may be applied. 
         [0026]    Note that the nominal resistor  16  of  FIG. 2  can only be tuned in one direction, which is why both R 1  and R 2  must be tunable, in the embodiment of  FIG. 1 . However, by using other tunable resistor elements  16 , in which the resistance value can be tuned in both directions, only one resistor of R 1  and R 2  needs to be tunable. 
         [0027]    The RF source  14  may comprise a differential balun and an LNA which receives the input RF signal from an antenna and amplifies it at the LNA output connected to the balun. The desired DC value of the RF common-mode can easily be set by means of a center tap, and will also be the DC voltage present at the virtual ground, since no DC current is present in the passive mixer core  12 . 
         [0028]    In another embodiment, load tuning is achieved by including the tunable resistor elements within the mixer core and keeping the mixer load constant.  FIG. 3  depicts a receiver  30  comprising an RF source  36 , a differential passive mixer core  32  having tunable resistor elements  34  in the core  32 , constant load resistances  38  and  40  and an amplifier  42  which inputs become a virtual ground node. In this embodiment, mismatches between the mixer core  32  transistors (and or clock driver transistors, not shown) that would deviate from a balanced output and create second-order inter-modulation distortion, are compensated by adjusting the tunable resistor elements  34  in the core  32 . 
         [0029]    For low supply voltage applications, a complementary mixer (including both an NMOS mixer and a PMOS mixer), provides better linearity than a stand-alone NMOS mixer.  FIG. 4  depicts a complementary mixer comprising the differential passive NMOS mixer core  32  of  FIG. 3 , together with a differential passive PMOS mixer core  44 . Both cores  32 ,  44  include tunable resistor elements  34  to compensate for device mismatches and balance the output to suppress second-order inter-modulation distortion. 
         [0030]    In practice, for the embodiments of  FIGS. 1 ,  3 , or  4  to achieve a balanced output and suppress even-order harmonics, the tunable resistor elements  16 ,  34  must be calibrated against the specific transistors in the respective mixer cores  12 ,  32 ,  44  (or their clock drivers). Since the nonlinearities are device-specific, a unique calibration procedure is required for each receiver  10 ,  30 . 
         [0031]      FIG. 5  depicts a differential passive mixer with a calibration circuit  50  according to one embodiment. The circuit  50  includes a balun  56  as a balanced signal source that is connected to the output of an LNA (not shown), one or more differential passive mixer cores  52  including tunable resistor elements  54 , a first switching matrix  58 , load resistors  60 , a second switching matrix  62 , and a measuring circuit  63  including a differential amplifier  64 , low pass filter  66 , analog-to-digital converter  68 , and baseband processor  70 . The calibration circuit  50  additionally includes voltage sources  72 , a common mode resistor  74 , and mode switch  76 . 
         [0032]    The balun  56  generates a balanced source signal from an RF input, and provides a DC ground level via a center tap. For simplicity,  FIG. 5  depicts only an I channel mixer  52 ; however, in a typical implementation, the circuit  50  would include both I and Q mixer cores. The first switching matrix  58  selects between the I channel mixer  52  and Q channel mixer (not shown), in response to the Kiq control signal. The first switching matrix  58  also receives the Kmode control signal, as does the mode switch  76 , which switches the circuit  50  between calibration mode and operating mode. In particular, the first switching matrix  58  can connect Ioutp to vp and Ioutn to vn to test the I channel mixer core  52 , as depicted; connect Qoutp to vp, and Qoutn to vn for Q mixer (not shown) test; or disconnect all inputs from the outputs during operational mode. 
         [0033]    The outputs of the first switching matrix  58  (the outputs of the mixer core  52  under test), the voltages of the load resistors  60 , the common voltage and ground are inputs to the second switching matrix  62 . The outputs of the second switching matrix  62  are coupled to the inputs of the differential amplifier  64 , which measures the voltage difference between its inputs. The differential amplifier  64  is low pass filtered by filter  66 , digitized by ADC circuit  68 , and analyzed by the baseband processor  70 . Voltage sources  72  (Vt 1  and Vt 2 ) inject current into the circuit for testing, and the common mode resistor  74  combines currents flowing in the balun. 
         [0034]    In calibration mode, a common mode current or differential current is injected into the differential passive mixer core  52  (either I or Q), and the current imbalance created by the mixer  52  imbalance, which is related to the IIP 2  performance, is measured by the measuring circuit  63 . 
         [0035]    The second switching matrix  62  is used to configure the desired test. It can be configured to detect the voltage source imbalance (Vt 1  and Vt 2 ), amplifier differential input offset, and also to perform the calibration of the mixer core  52  devices. As the inputs can be swapped, it is feasible for compensation of the error introduced by the measurement circuit  63 . This is important as the mismatch current created by the core  52  under test is very weak. Load resistors  60  convert the test voltages (Vt 1  and Vt 2 ) into currents, which are correlated to the input impedance of the mixer core  52 . Thus it is possible to measure the matching properties of the mixer core  52  by measuring the voltage drops which are proportional to the currents. 
         [0036]    In one embodiment, the second switching matrix  62  is operated in a time interleaved fashion, alternately connecting various inputs to the differential amplifier  64  vinp and vinn terminals. The various possible connections are listed in the table below: 
         [0000]    
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Calibration Test Configurations for Second Switching Module 
               
             
          
           
               
                 Test No. 
                 vinp 
                 vinn 
               
               
                   
               
             
          
           
               
                 1 
                 vp 
                 vn 
               
               
                 2 
                 vp 
                 V1 
               
               
                 3 
                 vn 
                 V2 
               
               
                 4 
                 V1 
                 vc 
               
               
                 5 
                 V2 
                 vc 
               
               
                 6 
                 vc 
                 cg 
               
               
                 7 
                 vinn 
                 vinp 
               
               
                 8 
                 vn 
                 Vp 
               
               
                 9 
                 V1 
                 Vp 
               
               
                 10 
                 V2 
                 Vn 
               
               
                 11 
                 vc 
                 V1 
               
               
                 12 
                 vc 
                 V2 
               
               
                 13 
                 cg 
                 vc 
               
               
                 14 
                 float 
                 float 
               
               
                   
               
             
          
         
       
     
         [0037]    Each amplifier  64  input may be connected to one of six inputs, or may be shorted or floated, depending on the test mode. In an embodiment in which two switching matrices  62  and two amplifiers  64  are provided, two pairs of inputs can be detected simultaneously, e.g., Amp 1  detects vp and V 1 , and Amp 2  detects vn and V 2 . 
         [0038]    The input DC offset of the amplifier(s)  64  leads to an error in the measurement, and must be calibrated. The mismatch of the amplifier  64  can be calibrated with help of a baseband processor. In the amplifier  64  input DC offset calibration mode, the second switching matrix  62  connects the inputs of the amplifier  64  together, and the amplifier  64  output DC offset is digitized by the ADC  68  and recorded by the baseband processor  70 . The output DC offset is then subtracted from measured results when performing the mixer core  52  calibration. 
         [0039]    Voltage sources  72  (Vt 1  and Vt 2 ) used during the tests have three modes: common mode, differential mode and combined mode. In common mode Vt 1 =Vt 2 , and in differential mode Vt 1 =−Vt 2 . The voltage sources  72  could be DC, AC or pulse sources. When voltage sources  72  are connected in differential mode and set to AC or pulse sources, the Vt 1  and Vt 2  are complementary. More generally, the voltage sources  72  can have the combined mode where Vt 1 =Vcom+e/2 and Vt 2 =Vcom−e/2, and e is the differential voltage. 
         [0040]    In the common mode test, Vt 1 =Vt 2 =Vcom(k), k=1, 2, . . . , M, and M is the number of test performed. Each test will take N steps to complete the adjustment of tunable resistor elements  54  Rn 1 -Rn 8 , where Rn 1 -Rn 4  are for tuning I-mixer core  52  and Rn 5 -Rn 8  are for the P-mixer core (not shown). 
         [0041]    Normally M is greater than or equal to 2, meaning that the calibration is done at least at two voltage points to guarantee the behavior fitting. The larger M, the more check points are used, and thereby better behavior fitting accuracy, but at the cost of a longer calibration time. 
         [0042]    In one embodiment, using the calibration circuit  50  of  FIG. 5 , the mixer  52  branches are connected sequentially, one by one, without overlap in time.  FIG. 6  depicts the control signals at nodes En 1 -En 4  for I-mixer in period of P_I(i), and i=1, 2, . . . , N, is the i th  step among the N. The common mode test can be done using a voltage source of type DC, AC or pulse, or a combination. However, DC or pulse sources are preferred for simplicity. 
         [0043]    The simplest way to calibrate the mixer  52  is to make sure that each branch has the same DC resistance. In this case, the common mode test is used, and the voltage sources  72  are set to DC using Vt 1 =Vt 2 =Vdc(k), k=1, 2, . . . , M. For example, during period P_I(i) slot  1  (denoted S 1  in  FIG. 6 ), the second switching matrix  62  is configured to connect the amplifier  64  inputs vinp and vinn to vp and V 1 . Current from the voltage source Vt 1  will flow in a loop, including Rc  74 , the mode switch  76 , Balun, Tn 1 , Rn 1  and Rt 1 . If only this test is employed, the two sources  72  (Vt 1  and Vt 2 ) can be merged together. 
         [0044]    Similarly, during period P_I(i) slot  2  (denoted S 2  in  FIG. 6 ), the second switching matrix  62  is configured to connect the amplifier inputs vinp and vinn to vn and V 2 . The current from the voltage source Vt 2  will flow in a loop, including Rc  74 , the mode switch  76 , Balun, Tn 2 , Rn 2  and Rt 2 . 
         [0045]    During the rest of the slots (S 3 -S 8 ), currents flow similarly through voltage source Vt 1  or Vt 2 , Tn 3 , Rn 3  or Tn 4 , Rn 4  and Rt 1  or Rt 2 . The calculated current ir, r=1, 2, . . . , 8, is recorded when a slot is complete, and based on the results, the tunable resistor elements  54  (Rn 1 -Rn 8 ) will be adjusted in the next step, i+1, to reduce the current spread. After N steps of tuning, the final minimized mismatch error of the currents, Ef(k), is obtained. 
         [0046]    The N step adjustments are repeated M times for different Vdc(k). For production test, if Ef(k) from a mixer core  52  under test is larger than a predetermined threshold, then the core  52  is not qualified and should be removed from the package list. Only cores  52  that pass the test will be packaged. 
         [0047]    For a differential passive mixer core  52  that passes the production test and is packaged, a calibration procedure may be required whenever the circuit  50  is activated from a power off, or a standby, or “sleeping” state. In such a test, after N steps of adjustments, the final setting is saved and used during the operating mode, as described above. Calibrations may also be applied once at a power up, or periodically as necessary during operation, to reduce IM 2  as desired or required by operating conditions. The calibration results will be stored and used until next calibration. As an alternative to performing a calibration test every time a mobile device is initialized, it is possible to perform a one-time calibration test at production, and permanently program the tunable resistor elements  16 ,  54  via fused links. 
         [0048]      FIG. 7  depicts a calibration circuit  80 , which is one of the test configurations derived from  FIG. 5  by setting Vt 1 =Vt 2  and Vbias=0.  FIG. 9  depicts the timing of clock signals applied to the mixer core  52  transistors. In this configuration, and with the clock signals of  FIG. 9  applied, the mixer core  52  operates in a topology similar to a differential amplifier. This is illustrated by the equivalent circuit  82  of  FIG. 8 . As the equivalent circuit  82  shows, the half of the mixer core under test is configured as a differential amplifier, and two branches of the mixer core  52  conduct at same time, and the current imbalance is detected at nodes vp and vn of the differential amplifier  64  in terms of a differential voltage. The tuning procedure is similar to that described above, including N steps, of which the i th  is depicted in  FIG. 9 . It is possible to chop the amplifier  64  so that the DC offset of the amplifier  64  itself can be removed from the test results. By properly setting the conducting voltage at the gates En 1 -En 8 , the mismatch between two transistor devices can be easily detected, and the tunable resistor elements  54  are adjusted to minimize or eliminate it. 
         [0049]      FIG. 10  depicts a calibration circuit  84 , which is another test configuration derived from  FIG. 5  by setting Vt 1 =−Vt 2 . As shown in the circuit  84 , a differential voltage mode is used, where Vt 1 =−Vt 2 , and the timing relation shown in  FIG. 9  is used for the transistor gate control. The current flowing through Vt 2  is opposite to the current flowing through Vt 1 . Thus, in the common mode resistor  74 , the matched current component will be subtracted and only the differential component Vd remains. If Vt 1  and Vt 2  are pulse sources, their polarities can be swapped. Then the differential voltage Vd can be measured as Vdp and Vdn at two opposite polarities of Vt 1  and Vt 2 . The difference between Vdp and Vdn is the imbalance part created by the device mismatch, and the tunable resistor elements  54  are adjusted to eliminate the imbalance. 
         [0050]    By tuning the output loads of a passive differential mixer, the second-order differential distortion that gives rise to second-order intermodulation is minimized. A calibration procedure adjusts tunable resistor elements in the mixer core or load to minimize the imbalance. By reducing the second-order intermodulation, passive differential mixers can be more economically implemented in direct conversion receivers with small device sizes, yielding high linearity, low noise figures, small silicon footprint, and low power consumption. 
         [0051]    The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.