Abstract:
A method and system for transferring frames from a storage device to a host system via a controller is provided. The method includes transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the transport module and it appears to the transport module as if the host system sent the acknowledgement. The frames in the controller are tracked by creating a status entry indicating that a new frame is being created; accumulating data flow information, while a connection to transfer the frame is being established by a link module; and updating frame status as frame build is completed, transferred, and acknowledged. The controller includes, a header array in a transport module of the controller, wherein the header array includes plural layers and one of the layers is selected to process a frame.

Description:
BACKGROUND OF THE INVENTION 
     1. Field Of the Invention 
     The present invention relates generally to storage device controllers, and more particularly, to efficiently reading and writing data. 
     2. Background 
     Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives) (referred to herein as “storage device”). 
     In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system. 
     The storage device is coupled to the host system via a controller that handles complex details of interfacing the storage device to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces. 
     Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into a buffer memory. Data is read from the device and stored in the buffer memory. 
     Various standard interfaces are used to move data from host systems to storage devices. Fibre channel is one such standard. Fibre channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users. 
     Host systems often communicate with storage systems using the “PCI” bus interface. PCI stands for Peripheral Component Interconnect, a local bus standard that was developed by Intel Corporation®. The PCI standard is incorporated herein by reference in its entirety. Most modern computing systems include a PCI bus in addition to a more general expansion bus (e.g. the ISA bus). PCI is a 64-bit bus and can run at clock speeds of 33 or 66 MHz. 
     PCI-X is a standard bus that is compatible with existing PCI cards using the PCI bus. PCI-X improves the data transfer rate of PCI from 132 MBps to as much as 1 GBps. The PCI-X standard (incorporated herein by reference in its entirety) was developed by IBM®, Hewlett Packard Corporation® and Compaq Corporation® to increase performance of high bandwidth devices, such as Gigabit Ethernet standard and Fibre Channel Standard, and processors that are part of a cluster. 
     The iSCSI standard (incorporated herein by reference in its entirety) is based on Small Computer Systems Interface (“SCSI”), which enables host computer systems to perform block data input/output (“I/O”) operations with a variety of peripheral devices including disk and tape devices, optical storage devices, as well as printers and scanners. 
     A traditional SCSI connection between a host system and peripheral device is through parallel cabling and is limited by distance and device support constraints. For storage applications, iSCSI was developed to take advantage of network architectures based on Fibre Channel and Gigabit Ethernet standards. iSCSI leverages the SCSI protocol over established networked infrastructures and defines the means for enabling block storage applications over TCP/IP networks. iSCSI defines mapping of the SCSI protocol with TCP/IP. The iSCSI architecture is based on a client/server model. Typically, the client is a host system such as a file server that issues a read or write command. The server may be a disk array that responds to the client request. 
     Serial ATA (“SATA”) is another standard, incorporated herein by reference in its entirety that has evolved from the parallel ATA interface for storage systems. SATA provides a serial link with a point-to-point connection between devices and data transfer can occur at 150 megabytes per second. 
     Another standard that has been developed is Serial Attached Small Computer Interface (“SAS”), incorporated herein by reference in its entirety. The SAS standard allows data transfer between a host system and a storage device. SAS provides a disk interface technology that leverages SCSI, SATA, and fibre channel interfaces for data transfer. SAS uses a serial, point-to-point topology to overcome the performance barriers associated with storage systems based on parallel bus or arbitrated loop architectures. 
     Conventional controllers are not designed to efficiently handle high throughput that is required by new and upcoming standards. For example, conventional controllers do not keep track of frame status, from the time when a frame build occurs to the time when the frame is transmitted. Also, if an error occurs during frame transmission, conventional controllers are not able to process frames from a known point. 
     Conventional controllers often have poor performance because they wait for a host to acknowledge receipt of a frame. A host does this by sending an ACK (acknowledgement) frame or a “NAK” (non-acknowledgement frame). Often this delays frame processing because when a host receives a frame it may choose to acknowledge the frame immediately or after a significant amount of time. 
     Therefore, there is a need for a controller that can efficiently process data to accommodate high throughput rates. 
     SUMMARY OF THE INVENTION 
     A method for transferring frames from a storage device to a host system via a controller is provided. The method includes, transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the transport module and it appears to the transport module as if the host system sent the acknowledgement. 
     The transport module vacates an entry for a frame after it receives the acknowledgement from the link module. Also, the transport module waits for an acknowledgement from the host system, after a last frame for a read command is transmitted to the host system. 
     In yet another aspect of the present invention, a method for tracking frames in a controller used for facilitating frame transfer between a host system and a storage device is provided. The method includes: creating a status entry indicating that a new frame is being created; accumulating data flow information, while a connection to transfer the frame is being established by a link module; and updating frame status as frame build is completed, transferred, and acknowledged. 
     The method further includes: determining if a frame has been lost after transmission; and using a known good frame build point to process the frame if it was lost in transmission. 
     In yet another aspect of the present invention, a method is provided for processing frames in a transmit path of a controller that is used to facilitate frame transfer between a storage device and host system. The method includes, loading a received frame&#39;s context to a header array; building a frame and selecting a header array for processing the frame; and saving the context to a different header array if the frame processing is complex. 
     In yet another aspect of the present invention, a method for processing frames in a receive path of a controller used for facilitating frame transfer between a storage device and a host system is provided. The method includes: loading a context of a received frame into an header array; verifying received frame header information; and sending Transfer Ready or Response frames to the host system using a frame header context. 
     In yet another aspect of the present invention, a controller for transferring frames between a storage device and a host system is provided. The controller includes a header array in a transport module of the controller, wherein the header array includes plural layers and one of the layers is selected to process a frame. 
     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
         FIG. 1A  shows an example of a storage drive system used with the adaptive aspects of the present invention; 
         FIG. 1B  shows a block diagram of a SAS module used in a controller, according to one aspect of the present invention; 
         FIG. 1C  shows a detailed block diagram of a SAS module, according to one aspect of the present invention; 
         FIG. 1D  shows a SAS frame that is received/transmitted using the SAS module according to one aspect of the present invention; 
         FIG. 1E  shows a block diagram of a transport module according to one aspect of the present invention; 
         FIG. 2  shows a flow diagram for processing a data transfer command in the transmit path, according to one aspect of the present invention; 
         FIG. 3  shows a flow diagram for a link module to acknowledge frame receipt, according to one aspect of the present invention; 
         FIG. 4  shows a flow diagram of process steps in the transmit path of a controller, according to one aspect of the present invention; 
         FIG. 5  shows a flow diagram of the receive process using a header array, according to one aspect of the present invention; 
         FIG. 6  shows a block diagram for selecting a header array, according to one aspect of the present invention; and 
       FIGS.  7 ( 1 )- 7 ( 2 ) (referred to as  FIG. 7 ) shows header array contents, according to one aspect of the present invention; 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Controller Overview: 
     To facilitate an understanding of the preferred embodiment, the general architecture and operation of a controller will initially be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture. 
       FIG. 1A  shows an example of a storage drive system (with an optical disk or tape drive), included in (or coupled to) a computer system. The host computer (not shown) and the storage device  110  (also referred to as disk  110 ) communicate via a port using a disk formatter “DF”  104 . In an alternate embodiment (not shown), the storage device  110  is an external storage device, which is connected to the host computer via a data bus. The data bus, for example, is a bus in accordance with a Small Computer System Interface (SCSI) specification. Those skilled in the art will appreciate that other communication buses known in the art can be used to transfer data between the drive and the host system. 
     As shown in  FIG. 1A , the system includes controller  101 , which is coupled to buffer memory  111  and microprocessor  100 . Interface  109  serves to couple microprocessor bus  107  to microprocessor  100  and a micro-controller  102  and facilitates transfer of data, address, timing and control information. A read only memory (“ROM”) omitted from the drawing is used to store firmware code executed by microprocessor  100 . 
     Controller  101  can be an integrated circuit (IC) that is comprised of various functional modules, which provide for the writing and reading of data stored on storage device  110 . Buffer memory  111  is coupled to controller  101  via ports to facilitate transfer of data, timing and address information. Buffer memory  111  may be a double data rate synchronous dynamic random access memory (“DDR-SDRAM”) or synchronous dynamic random access memory (“SDRAM”), or any other type of memory. 
     Disk formatter  104  is connected to microprocessor bus  107  and to buffer controller  108 . A direct memory access (“DMA”) DMA interface (not shown) is connected to microprocessor bus  107  and to a data and control port (not shown). 
     Buffer controller (also referred to as “BC”)  108  connects buffer memory  111 , channel one (CH 1 ) logic  105 , and error correction code (“ECC”) module  106  to bus  107 . Buffer controller  108  regulates data movement into and out of buffer memory  111 . 
     CH 1  logic  105  is functionally coupled to SAS module  103  that is described below in detail. CH 1  Logic  105  interfaces between buffer memory  111  and SAS module  103 . SAS module  103  interfaces with host interface  104 A to transfer data to and from disk  110 . 
     Data flow between a host and disk passes through buffer memory  111  via channel  0  (CH 0 )logic  106 A. ECC module  106  generates ECC that is saved on disk  110  during a write operation and provides correction mask to BC  108  for disk  110  read operation. 
     The channels (CH 0   106 A and CH 1   105  and Channel  2  (not shown) are granted arbitration turns when they are allowed access to buffer memory  111  in high speed burst write or read operations for a certain number of clocks. The channels use first-in-first out (“FIFO”) type memories to store data that is in transit. Firmware running on processor  100  can access the channels based on bandwidth and other requirements. 
     To read data from device  110 , a host system sends a read command to controller  101 , which stores the read commands in buffer memory  111 . Microprocessor  100  then reads the command out of buffer memory  111  and initializes the various functional blocks of controller  101 . Data is read from device  110  and is passed to buffer controller  108 . 
     To write data, a host system sends a write command to disk controller  101 , which is stored in buffer  111 . Microprocessor  100  reads the command out of buffer  111  and sets up the appropriate registers. Data is transferred from the host and is first stored in buffer  111 , before being written to disk  110 . CRC (cyclic redundancy check code) values are calculated based on a logical block address (“LBA”) for the sector being written. Data is read out of buffer  111 , appended with ECC code and written to disk  110 . 
     Frame Structure: 
       FIG. 1D  shows a SAS frame  129  that is received/transmitted using SAS module  103 . Frame  129  includes a WWN value  129 A, a start of frame (“SOF”) value  129 G, a frame header  129 B that includes a frame type field  129 E, payload/data  129 C, CRC value  129 D and end of frame (“EOF”)  129 F. The SAS specification addresses all devices by a unique World Wide Name (“WWN”) address. 
     Also, a frame may be an interlock or non-interlocked, specified by field  129 E (part of frame header  129 B). For an interlock frame, acknowledgement from a host is required for further processing, after the frame is sent to the host. Non-interlock frames are passed through to a host without host acknowledgement (up to 256 frames per the SAS standard). 
     SAS Module  103 : 
       FIG. 1B  shows a top level block diagram for SAS module  103  used in controller  101 . SAS module  103  includes a physical (“PHY”) module  112 , a link module  113  and a transport module (“TRN”)  114  described below in detail. A micro-controller  115  is used to co-ordinate operations between the various modules. A SAS interface  116  is also provided to the PHY module  112  for interfacing with a host and interface  117  is used to initialize the PHY module  112 . 
       FIG. 1C  shows a detailed block diagram of SAS module  103  with various sub-modules. Incoming data  112 C is received from a host system, while outgoing data  112 D is sent to a host system or another device/component. 
     PHY Module  112 : 
     PHY module  112  includes a serial/deserializer (“SERDES”)  112 A that serializes encoded data for transmission  112 D, and de-serializes received data  112 C. SERDES  112 A also recovers a clock signal from incoming data stream  112 C and performs word alignment. 
     PHY control module  112 B controls SERDES  112 A and provides the functions required by the SATA standard. 
     Link Module  113 : 
     Link module  113  opens and closes connections, exchanges identity frames, maintains ACK/NAK (i.e. acknowledged/not acknowledged) balance and provides credit control. As shown in  FIG. 1C , link module  113  has a receive path  118  that receives incoming frames  112 C and a transmit path  120  that assists in transmitting information  112 D. Addresses  121  and  122  are used for received and transmitted data, respectively. 
     Receive path  118  includes a converter  118 C for converting 10-bit data to 8-bit data, an elasticity buffer/primitive detect segment  118 B that transfers data from a receive clock domain to a transmit block domain and decodes primitives. Descrambler module  118 A unscrambles data and checks for cyclic redundancy check code (“CRC”). 
     Transmit path  120  includes a scrambler  120 A that generates CRC and scrambles (encodes) outgoing data; and primitive mixer module  120 B that generates primitives required by SAS protocol/standard and multiplexes the primitives with the outgoing data. Converter  120 C converts 8-bit data to 10-bit format. 
     Link module  113  uses plural state machines  119  to achieve the various functions of its sub-components. State machines  119  includes a receive state machine for processing receive frames, a transmit state machine for processing transmit frames, a connection state machine for performing various connection related functions and an initialization state machine that becomes active after an initialization request or reset. 
     Transport module  114 : 
     Transport module  114  interfaces with CH 1   105  and link module  113 . In transmit mode, TRN module  114  receives data from CH 1   105 , loads the data (with fibre channel header (FCP)  127 ) in FIFO  125  and sends data to Link module  113  encapsulated with a header ( 129 B) and a CRC value ( 129 D). In receive mode, TRN module  114  receives data from link module  113  (in FIFO  124 ), and re-packages data (extracts header  126  and  128 ) before being sent to CH 1   105 . CH 1   105  then writes the data to buffer  111 . State machine  123  is used to co-ordinate data transfer in the receive and transmit paths. 
       FIG. 1E  shows a detailed block diagram of transport module  114 . Transmit FIFO  125  operates at BCCLK  125 B(BC  108  clock) on the input side and SASCLK  125 A on the output side. FIFO  125  holds one or more frames with a header, payload and CRC value. 
     Transport module  114  includes another FIFO on the transmit side, the Fx FIFO  114 C. Fx FIFO  114 C includes a write pointer, which specifies the entry to use when a new frame is built by transport module  114 . Fx FIFO  114 C also includes an ACK/NAK pointer (“akptr”). When Link module  113  receives an ACK for a frame, the entry is removed from Fx FIFO  114 C and the akptr is increased. 
     Fx FIFO  114 C also includes a “lnkptr” that indicates a frame being sent to link module  113  at a given time. Fx FIFO  114 C also includes a pointer for MP  100  to allow microprocessor  100  to inspect and modify the content of the Fx FIFO  114 C. 
     Transport module  114  also include a multiplier  114 A that is used for hardware assist when firmware initializes transport module  114  registers; and credit logic  114 D (that provides available credit information to Link  113  for received data). 
     A header array  114 B is used for processing data efficiently, as described below in detail, according to one aspect of the present invention. 
     Transmit module  114  can send interrupts and status  130  to MP  100  (or to MC  102 /MC  115 ) on the receive side. Control and configuration information is shown as  133 , while details regarding incoming data (for example, transfer count, burst length, data offset and frame size) is shown as  134 . 
     On the transmit side, interrupts/status are shown as  131 A, control/configuration as  131  and outgoing data attributes (for example, transfer count, burst length, data offset and frame size) is shown as  132 . 
     Frame Processing: 
       FIG. 2  shows a flow diagram for processing a data transfer command in the transmit path, according to one aspect of the present invention. In step S 200 , the process starts and in step S 201 , a data transfer command is received from a host system via host interface  104 A. 
     In step S 202 , a status entry is created in Fx FIFO  114 C. The entry indicates that a new frame has been created. 
     In step S 203 , to reduce latency, WWN index value  129 A is sent to link module  113 . This allows link module  113  and PHY module  112  to initiate a connection, while the frame is being built. 
     In step S 204 , link module  113 /PHY  112  initiates a connection and data flow information is accumulated simultaneously. This reduces latency for transmitting frames. 
     In step S 205 , when the frame is built, the status is updated in FIFO  114 C. The same is performed when the frame is sent. 
     In step S 206 , after the frame is sent, the process (MC  115 ) determines if the frame is lost. This is based on whether the host system indicates that the frame has been received. If the frame is not lost, then in step S 207 , the entry is vacated for the next frame. 
     If the frame is lost, then the process starts again. However, frame processing does not have to begin from step S 200 , instead, the processing is resumed from a known point, since frame status is continuously updated from the time a frame is created to the time it is sent. 
     MC  115  can tag frames using various identifiers. For example, a frame may be tagged so that link module  113  discards the frame; a frame is tagged as an interlock/non-interlock frame; a frame may be tagged as an error frame; or the last frame is tagged as the “last frame” of a read command. 
     The foregoing process allows MC  115  to know who requested a frame, where in buffer  111  did the frame come from, how many blocks comprise the frame and all the information used to build the frame (for example, CRC residue, logical block address and offset from the beginning of the block). This information is used to process the frame if the frame is lost and perform diagnostics on a connection. 
     Process Flow for Link Module  113  Acknowledging Frame Receipt: 
       FIG. 3  shows a flow diagram of process steps where after a frame is sent by transport module  114  to link module  113 , the link module  113  acknowledges frame receipt so that transport module  114  does not wait for host acknowledgement, until the last frame has been sent in a read command. 
     In step S 300 , link module  113  via PHY module  112  transfers frame to a host. 
     In step S 301 , link module  113  sends an ACK frame to transport module  114 . Transport module  114  considers the ACK to be that from a host. Firmware can enable or disable the mode that allows link module  113  to send an ACK frame. If the link module  113  is not enabled to send an ACK frame, then transport module  114  waits for the host to acknowledge frame receipt (for interlock frames). Thereafter, in step S 302 , the entry for the transmitted frame in FIFO  125  is vacated. 
     In step S 303 , data flow information is stored in a register (not shown). Thereafter, in step S 304 , data is released to BC  108  and transport module  114  waits for an ACK/NAK balance condition, after the last frame has been transmitted. 
       FIG. 4  shows a flow diagram of process steps in the transmit path of controller  101 . In step S 400 , receive commands are received from a host. The command includes a context and data. In step S 401 , the context is loaded in header array  114 B (as shown in  FIG. 6 ) by MC  115  or MP  100 . In one aspect the header array  114 B includes one array element each for receive and transmit processes and two for either context switch or spares. Since initializing a header array can take a significant amount of time, extra (spare) arrays are provided allow the microprocessor  100  firmware to overlap initializing the header array for the next processes while transmission and receiving frames for the current processes. 
     In step S 402 , the frame is built and a header row is selected from the header array  114 B. This is performed based on command/signal/bit set in register  601 . 
     In step S 403 , the frame is processed as discussed below with respect to steps S 406  and S 405 . For a non-complex case, for example, where there is no interrupt involved, a response is sent in step S 406  using the selected row from header array  114 B. For a complex case, in step S 404 , the context is saved in another header array  114 B row and then the frame is sent. Thereafter, after the frame is processed in step S 405 , the process reverts back to the previous header row (step S 406 ). 
     It is noteworthy that header array  114 B allows firmware to interrupt what is being transmitted at a given time, save the context into the array in a single access, select a new context, process the new context and then revert back to the old context. Header array  114 B architecture allows generation of different types of frames using the same array element. 
       FIG. 5  shows a flow diagram of the receive process using header array  114 B, according to one aspect of the present invention. In step S 500 , write data command is received from host. In step S 501 , MC  115  or MP  100  loads the context into header array  114 B. In step S 502 , frame header is verified. If the frame header cannot be verified, then an error flag is set in step S 503 . 
     If the frame header can be verified, then in step S 504 , data is saved in buffer  111 . Thereafter, in step S 505 , a XFER-RDY signal is sent to the host. 
     It is noteworthy that a receive operation is split into different bursts paced by the recipient. Header array  114 B can save a current context of a receive operation at the beginning of each burst to allow for retries, in case of errors. 
     It is noteworthy that the transmit and receive processes may use the same or different array elements. While one or two array elements are actively processed at a given time, MP  100  may process other elements for future processing and thus improve overall controller  101  performance. 
     Header Array  114 B: 
     As shown in  FIG. 6 , header array  114 B has plural rows/layers and one row is selected by signal/command/bit generated from header select register  601 . Array addresses are shown as  607 . 
     Various commands/signal/bit (used interchangeably) values,  602 - 606 , are used for processing both receive and transmit operations. For example, when all the data for the write command is received by controller  101 , a “Good Rx” response frame is selected by  604 . “XFER_RDY” frame is selected by  605 , when all data for a burst has been written in buffer  111 . A frame header is selected by  602  and a “Good Tx” response is selected by  603  for data frame transmission. Context header array (row) is selected by bit  606  after a frame is received and the context is checked, based on the selected array. 
     Header array mask  608  is used for determining which information in a header participates in context save and retrieve operations. 
       FIG. 7  shows header array  114 B contents including control context, header context, transfer context, flow control context and input/output context. 
     The header array architecture of  FIG. 6  allows controller  101  to efficiently manage frame headers both on transmit and receive paths. Headers are built ahead in an array, plural headers may be generated for a single connection and incoming headers are checked using an expected header array  114 B. 
     Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure.