Abstract:
Disclosed is a system for fabricating an integrated circuit capacitor ( 100 ). An electrode layer ( 102 ) is formed in the integrated circuit. An anti-reflective coating ( 108 ) is deposited over the electrode layer ( 102 ). An electrode top plate ( 104 ) is formed over the anti-reflective coating ( 108 ).

Description:
FIELD OF THE INVENTION  
         [0001]    The invention is generally related to the field of fabricating integrated circuit capacitors and, more specifically, to improving the efficiency of capacitor fabrication by forming the insulator layer of a capacitor from an anti-reflective coating.  
         BACKGROUND OF THE INVENTION  
         [0002]    Since the invention of integrated circuits, the number of devices on a chip has grown at a near-exponential rate. The fabrication methods of the semiconductor industry have been modified and improved continuously for almost four decades. With each improved method, the capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices. Future improvements will require integrated circuit devices such as transistors, capacitors, and connections between devices to become even smaller and more densely populated on the chip.  
           [0003]    The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. The requirements of high packing density, low heat generation, and low power consumption, with good reliability and long operation life, must be maintained without any functional degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.  
           [0004]    As integrated circuits become denser, the techniques for fabricating the semiconductor devices must become more precise. Lithography, for example, is one fabrication technique that may be used to remove particular areas of deposited material to define various components of the semiconductor device. Overall device size, however, has become so small that reflected light could remove a detrimental amount of material from adjacent structures. An anti-reflective coating (ARC) layer may be deposited to reduce or eliminate the possibility of reflected light damaging adjacent structures and to improve the resolution of the lithography process.  
           [0005]    In addition to more precise manufacturing techniques, semiconductor fabrication must become more efficient to reduce costs for the consumer and remain competitive with other manufacturers. Each step of the fabrication process consumes time, which increases costs and reduces production volume. Because profits are directly related to production volume, any production delay reduces the profits of a manufacturer.  
           [0006]    There are a number of conventional capacitor fabrication processes. Several examples of conventional capacitor fabrication processes are depicted in FIGS.  1 A- 1 D. In particular, FIG. 1A depicts a typical metal-insulator-metal (MIM) capacitor fabrication process in which a capacitor  10  has a first electrode  12 . A second electrode  14  is separated from the first electrode  12  by a dielectric  16 . The first electrode  12  may have multiple layers  18  and  20 , which may be configured according to the desired performance characteristics of the capacitor  10 . Layer  18 , for example, may be a silicided polysilicon or some other type of semiconductor material. Layer  20 , for example, may be a metal such as tungsten or titanium nitride. This particular configuration of layers  18 ,  20 ,  22 , may be combined to fabricate a high capacitance capacitor in an integrated circuit.  
           [0007]    [0007]FIG. 1B depicts another conventional method of fabricating a capacitor  10  in which the capacitor stack ( 12 ,  14 ,  16 , collectively) is deposited immediately after the first half of the via etch. After the capacitor stack ( 12 ,  14 ,  16 ) is deposited and etched, the second half of the via  24  is formed directly above the first half of the via  24 . Fabrication of this particular capacitor  10 , however, requires two additional masking steps. One additional masking step is required for the capacitor stack ( 12 ,  14 ,  16 ) and another additional masking step is required to form the upper half of the vias  24  that connect the second electrode  14  to the semiconductor region  18 . The patterning and etching of the capacitor stack ( 12 ,  14 ,  16 ) may cause damage to the dielectric  16 , which could cause leakage within the capacitor  10 . Leakage may reduce the performance of the capacitor  10  or cause complete failure of the capacitor  10 .  
           [0008]    The conventional capacitor fabrication method depicted in FIG. 1C requires only one additional mask. In this particular design, the capacitor stack ( 12 ,  14 ,  16 ) is deposited and etched immediately prior to the deposition of the metal layer  26 . A metal top  26  is added over the second electrode  14 . The vias  24  may be formed over the metal top  26  and semiconductor layer  18  may then be deposited. As with the method depicted in FIG. 1B, possible damage to the dielectric may occur during the etching of the capacitor stack ( 12 ,  14 ,  16 ). Additionally, the topography of the capacitor  10  produced by this method may cause a residue of conducting layer  26  to remain and result in a bypass of electrical current from the second electrode  14  to the first electrode  12 , which renders the capacitor  10  ineffective.  
           [0009]    Finally, in the conventional capacitor fabrication process depicted in FIG. 1D, the capacitor stack ( 12 ,  14 ,  16 ) is deposited and etched immediately after the pattering of the metal layer  18 . The metal patterning step, however, requires deposition of an ARC (Anti-Reflective Coating) to improve resolution of a lithographic patterning process. Therefore, the ARC used on the metal layer  18  must be removed prior to the deposition of the capacitor stack ( 12 ,  14 ,  16 ) to allow electrical contact with the first electrode  12 .  
         SUMMARY OF THE INVENTION  
         [0010]    Therefore, a system for forming integrated circuit capacitors that does not add excessive costs or procedures to the fabrication process, is now needed, providing for fabrication of more reliable integrated circuit capacitors while overcoming the aforementioned limitations of conventional methods.  
           [0011]    The present invention provides a system for fabricating an integrated circuit capacitor. An electrode layer is formed in the integrated circuit. An anti-reflective coating is deposited over the electrode layer. An electrode top plate is formed over the anti-reflective coating.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    For a more complete understanding of the present invention, including its features and advantages, reference is made to the following detailed description, taken in conjunction with the accompanying drawings. Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated.  
         [0013]    FIGS.  1 A- 1 D depict capacitor fabrication processes in accordance with the prior art; and  
         [0014]    [0014]FIG. 2 depicts an embodiment of a capacitor fabrication process in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0015]    While the making and using of various embodiments of the present invention is discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention, and do not delimit the scope of the invention.  
         [0016]    A process according to the present invention reduces or eliminates the inefficiencies of the prior art processes previously depicted and described.  
         [0017]    It should be understood that the principles and applications disclosed herein may be applied to a wide range of semiconductor device fabrication processes. For purposes of explanation and illustration, the present invention is hereafter described in reference to a particular capacitor fabrication. The present invention, however, is equally applicable to a variety of fabrication processes.  
         [0018]    Turning now to the present invention as depicted in FIG. 2, a capacitor  100  may be formed, for example, using conventional semiconductor fabrication processes. The present invention, however, eliminates a number of costly and time-consuming manufacturing steps required by such conventional capacitor fabrication processes.  
         [0019]    A first electrode  102  may be metallic, polysilicon, or some other semiconductor structure suitable for acting as an electrode of a capacitor. An anti-reflective coating dielectric  108  is formed over the first electrode  102 . The anti-reflective coating dielectric  108  may be formed by sputtering, chemical vapor deposition, or other suitable methods.  
         [0020]    The anti-reflective coating dielectric  108  is formed from silicon oxynitride, although other anti-reflective dielectrics may also be used. The anti-reflective coating dielectric  108  may be deposited prior to patterning, and minimizes the incidence of reflection during photolithography, thus allowing for smaller geometry patterning. The thickness and index of refraction of the anti-reflective coating dielectric  108  are selected for ARC density and thickness, and optimized for capacitance. For example, increasing the thickness of the anti-reflective coating dielectric  108  decreases the capacitance of the capacitor  100 , and increases the durability of the anti-reflective coating dielectric  108  for masking purposes. Furthermore, modifying the index of refraction of the anti-reflective coating dielectric  108  enhances the resolution of lithography processes. As a result, the capacitor  100  may be configured for particular performance characteristics, and the anti-reflective coating dielectric  108  will serve as an ARC in subsequent process steps.  
         [0021]    The second electrode  104  is deposited over the anti-reflective coating dielectric  108 . The second electrode  104  is patterned using a masking step. The second electrode  108  is selectively etched to the anti-reflective coating dielectric  108 . After the patterning of the second electrode  108 , the anti-reflective coating dielectric  108  remains to allow more precise patterning of the metal layer  102 , which may be used for routing. Because the anti-reflective coating dielectric  108  remains at the edges of the electrode  104 , capacitor  100  is more immune to leakage and breakage around the perimeter. The fabrication process, consequently, is more efficient and economical because the anti-reflective coating dielectric  108  acts as the dielectric of the capacitor. Materials and process steps are saved, because the additional masking steps required by conventional processes are not necessary.  
         [0022]    Although this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Upon reference to the description, it will be apparent to persons skilled in the art that various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention can be made without departing from the scope of the invention. It is therefore intended that the appended claims encompass any such modifications or embodiments.