Abstract:
Image sensor with CMOS output, an another circuit receiving input. The circuit operates like a transmission line, in current mode, with substantially zero voltage. The impedances are matched by setting bias currents.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of the U.S. Provisional Application No. 60/093,835, filed on Jul. 22, 1998. 
     
    
     BACKGROUND  
       [0002]     CMOS active pixel sensor cameras can produce a digital output.  
         [0003]     While digital outputs are often relatively noise insensitive, the noise can couple to the analog part of the circuit and cause problems there. Different techniques of minimizing this noise are known in the art.  
         [0004]     One way to address the noise is to use current mode transmission of voltages. The current mode transmission can be configured to operate with less noise in certain circuits. However, when current mode transmission is used, other problems can occur. One such problem is a so called ground bounce caused by surges in the power supply.  
       SUMMARY  
       [0005]     The present system teaches a new way of transmitting data from an image chip. This system can increase the signal-to-noise ratio to thereby increase the rate at which the digital data can be taken off the chip. This enables supporting higher frame rates with high special resolution. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]     These and other aspects will now be described in detail with the accompanying drawings, wherein:  
         [0007]      FIG. 1  shows a basic active pixel sensor architecture;  
         [0008]      FIG. 2  shows a conceptual diagram of current CMOS input/output when viewed as a transmission line;  
         [0009]      FIGS. 3   a  and  3   b  show the ground bounce in the CMOS I/O of  FIG. 2 ;  
         [0010]      FIG. 4  shows a new transmission line mode of CMOS I/O;  
         [0011]      FIG. 5  shows a schematic of a receiver circuit;  
         [0012]      FIG. 6  shows a first transmitter circuit using all CMOS components;  
         [0013]      FIGS. 7   a  and  7   b  show waveforms for the  FIG. 6  transmitter circuit;  
         [0014]      FIG. 8  shows a second transmitter circuit using CMOS components and a class A amplifier; and  
         [0015]      FIGS. 9   a  and  9   b  show waveforms of the circuit of  FIG. 8 .  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]     A disclosed active pixel sensor architecture is shown in  FIG. 1 . This active pixel sensor uses a column parallel approach where an entire column of information is digitized at any one time. More generally, any group of information, where the group could be a column, a partial column, row, partial row or any other group of information, can be simultaneously digitized.  
         [0017]     In the architecture shown, the data is digitized at the bottom of each pixel column. The digitized data is then serialized in the internal bus. Data is transmitted through digital output circuitry.  
         [0018]     In this disclosed mode, the digitized data is transmitted at 100 megahertz and sent to the imager output pads. This data is then transmitted off the chip.  
         [0019]     One bottleneck is caused by the rate at which this digital data can be taken off the imager chip. The design requirements for the I/O circuitry are often more stringent than those in the internal chip. This is because the I/O circuits must be able to drive loads that have large and often unknown parasitic components. The parasitic components can include both capacitive and inductive components. However, the combination of inductive and capacitive parasitics create second order systems that can have ringing oscillatory behavior at the high transmission frequencies.  
         [0020]     The present inventor recognized that the output can be considered as a transmission line. Proper handling of the termination can minimize ringing and oscillatory behavior. The IC  99  shown in  FIG. 2  is transmitting to a receiving IC  200 . A transmission line  210  connects the transmitting IC  99  to the receiving IC  200 .  
         [0021]     Typical CMOS output circuitry, however, is often not suitable for this transmission line environment.  FIG. 2  shows the situation of an unterminated CMOS transmission line.  FIGS. 3A and 3B  shows respectively the output waveforms when driving coax cable and the glitch voltage at the transmitter ground line.  FIG. 3A  shows the transmission sequence at the output of an unterminated CMOS line. In this system, a voltage equal to VDD/2 is launched into the line at the beginning of the transmission. This voltage travels into the unterminated receiver  200 , and at that point is doubled and reflected back. A one-foot length of 50 ohm coaxial cable has a flight time of about 5 nanoseconds. This time increases linearly with the physical length of the cable.  
         [0022]     This system, while usable, has certain drawbacks. The output bandwidth is limited. Moreover, the transmitter must wait for the duration of the flight time before attempting another transition. Also note that the output buffer must supply a current during the entire flight time. This can increase the power consumption of the CMOS output.  
         [0023]      FIG. 3   b  shows the voltage in the receiving IC  200 . The ground level bounces to add a few hundred millivolts. This can add significant noise onto the voltage output.  
         [0024]     Further complication is caused by the characteristic of CMOS that draws current only during the output voltage transitions. Because of the switching variation, there are large variations in current. These variations in current can cause ground bounce and can cause voltage glitches v on the line, of magnitude V=L di/dt where L is the inductance of the signal and/or ground bounce.  FIG. 3   b  shows these glitches in a single output buffer during a transition. While this diagram is only exemplary, it illustrates the general proposition that a unterminated transmission line will include a reflection, and that the switching techniques of CMOS can also cause ground bounce in this way.  
         [0025]     When several buffers switch in tandem, as often happens during digital transmission where multiple bits change state at once, the glitch energies could add. This noise in the power supply line can couple into the analog circuitry in the imager, and can corrupt the pixel outputs.  
         [0026]     The problem is addressed by circuit of  FIG. 4  which shows a current mode signaling system. The voltage swing at the output of a current mode driver can be low or zero, e.g. less than 0.5 volts. This allows the receiver end of the line to be terminated without a large increase in power consumption.  
         [0027]     The circuit of  FIG. 4  can also use a differential mode output. In this situation, the current drawn from the supply is constant. This minimizes glitches on the VDD and on the ground line.  
         [0028]     The transmitting IC  400  in  FIG. 4  drives its transmission line in the form of signal current. The receiver includes, as shown, two common source CMOS transistor pairs, each including an n transistor  410  and p-type transistor  412 . The CMOS pair receives the signals at its common source terminal. The drain of the PMOS transistor  412  is biased with a constant current and the output is defined by the drain of the second NMOS transistor. The input impedance for this receiver is defined as the parallel impedance seen at the sources of the n and p channel transistors.  
         [0029]     The impedance can be set by adjusting the bias current through the transistors via the current source  420 . Once set, the impedance becomes relatively independent of the input current through the configuration. Since the impedance is relatively constant, the reflected signal is minimized and hence transmission speed can be increased.  
         [0030]     A more detailed schematic of the receiver circuit  410  is shown in  FIG. 5 . Common source transistors  500 ,  502  receive the signal at their connected source terminals. The current signal is then mirrored in mirror transistor  504 , to form a conventional CMOS logic level. The input impedance for this circuit is set by bias current through current source  508 . In this embodiment, the bias current is sent to 3 ma, although the bias current can be changed for different applications.  
         [0031]     The circuit  410  shows a dual-ended differential input, with one part on line  503 , and the other part on line  501  driving common source transistors  504 ,  506 . Each of the current mirrors  510 ,  512  change the current to a conventional CMOS level. The circuit can also be used in a single ended mode, by sending only a single line of information.  
         [0032]     The output drivers can operate in a current mode output driver mode.  FIG. 6  shows a first embodiment using a differential pair  600 ,  602  with open drains that form the differential output. The output impedance of the receiver serves as the load for this circuit. The circuit steers a current that is determined by the bias current source  604  for full differential operation. The logic low level corresponds to negative I bias, and logic high level corresponds to no current.  
         [0033]      FIG. 7A  shows the output waveform of the circuit when driving a 50 ohm, 1 foot coax cable.  FIG. 7B  shows the ground glitches which are much less than in the previous circuit. The input CMOS voltage  610  is first connected to two CMOS transistor pairs  612 ,  614 . The output of the first stage  612  is buffered by a follower  616 , and input to one gate of transistor  602  of the differential pair  600 / 602 .  
         [0034]     The voltage V IN  is again inverted by the second CMOS transistor pair  614  and input to a second follower  618 . Hence, this first current design includes CMOS transistors to buffer and invert the signal as well as two differential followers arranged in a push-pull arrangement, driving a differential pair.  
         [0035]     The second embodiment, shown in  FIG. 8 , connects the input CMOS circuit current  604  through a single class A amplifier  800 . Again, the input voltage is buffered by first CMOS transistor pair  802 , and a second CMOS transistor pair  804  to form both an inverted and a non-inverted signal. These signals are connected to PMOS transistors  806  which are connected to current mirror  808 . The output of the current mirror  808  drives the base of a class A transistor  810  which is itself current mirrored by transistor  812 . The current mirroring by  812  drives a PMOS transistor  814  that produces the output voltage. A corresponding negative operation to the above produces the negative output voltage  818 .  
         [0036]      FIG. 9A  shows a exemplary output, and  FIG. 9B  shows the exemplary ground bounce of such a circuit.  
         [0037]     This second embodiment has the additional advantage that is produces a CMOS compatible output voltage when connected to a CMOS IC with high gate impedance.  
                                                                         Power Consumption   Ground Bounce   Bidirectional           mWatts   mVolts   Operation                                    Conventional   33   600   No       CMOS       Current Mode   10   200   Yes       Design I       Current Mode   21   100   Yes       Design II                  
 
         [0038]     Although only a few embodiments have been described in detail above, other embodiments are contemplated by the inventor and are intended to be encompassed within the following claims. In addition, other modifications are contemplated and are also intended to be covered.