Abstract:
A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to semiconductor packaging technology, and more particularly, to a semiconductor package structure with reduced parasite capacitance and method of fabricating the same, which is designed for the fabrication of a flip-chip (FC) type of semiconductor package, and which features the reduction of parasite capacitance in the package structure for ensured electrical performance during actual operation of the packaged integrated circuitry, and also allows the overall package body to be made more compact in size. 
   2. Description of Related Art 
   FC (Flip-Chip) is a more advanced type of semiconductor packaging technology which is characterized by that the semiconductor chip is mounted in an upside-down (i.e., flip chip) manner over the substrate and bonded to the same by means of solder bumps. Further, the flip chip is electrically connected to solder balls (i.e., ball grid array, BGA) implanted on the back side of the substrate for electrical connections to a printed circuit board (PCB). Since flip-chip package can be fabricated without the use of bonding wires, it allows the overall package body to be made more compact in size. 
     FIG. 1  is a schematic diagram showing a sectional view of a conventional flip-chip package structure. As shown, the flip-chip package structure includes a substrate  10 , a passive component  20 , and a semiconductor chip  30 ; wherein the substrate  10  has a front surface  10   a  and a back surface  10   b , and whose front surface  10   a  is formed with a plurality of pads, including at least a pair of passive-component pads  11 ,  12  and a group of signal pads  13 , where the passive-component pads  11 ,  12  are used for ground/power connections with the passive component  20  and the signal pads  13  are used for signal connections. Moreover, these pads  11 ,  12 ,  13  extend from the front surface  10   a  to the back surface  10   b  of the substrate  10  through electrically-conductive vias ((not shown) for electrical connection to solder balls  15  on the back surface  10   b  of the substrate  10 . The passive component  20  can be either a resistor or a capacitor, and which has two connecting ends: a first connecting end  21  and a second connecting end  22  respectively bonded to the passive-component pads  11 ,  12 . The chip  30  has an active surface  30   a  and an inactive surface  30   b , where the active surface  30   a  is defined with a plurality of ground/power pads  31 ,  32  and a plurality of signal pads  33 . Moreover, the chip  130  is formed with a plurality of solder bumps  40  for electrically connecting the signal pads  33  and the ground/power pads  31 ,  32  to corresponding pads  13  on the front surface  10   a  of the substrate  10  to form a flip-chip package structure. In this flip-chip package structure, the electrical connections with external circuitry are conducted through the vias for signal transmission, grounding, and power supply, and the passive component  20  is electrically connected to the chip  30  by connecting the ground/power pads  31 ,  32  by way of vias (not shown) or electrically-conductive traces  14  to the passive-component pads  11 ,  12 . 
   One drawback to the forgoing package structure, however, is that the long length of traces  14  that are interconnected between the passive component  20  and the chip  30  would easily cause parasite capacitance that would adversely degrade the electrical performance of the packaged chip  30  during high-frequency operation. Moreover, since the passive component  20  is mounted outside the die-mounting area on the substrate  10 , it requires the use of a large-area substrate for the mounting of the passive component  20  and the chip  30 , undesirably making the overall package body unsatisfactorily large. 
   SUMMARY OF THE INVENTION 
   It is therefore an objective of this invention to provide a new semiconductor fabrication technology that can help reduce the parasite capacitance in a flip-chip package structure to ensure the electrical performance of the packaged chip during actual operation. 
   It is another objective of this invention to provide a new semiconductor fabrication technology that can help make the overall package body to be more compact in size. 
   The semiconductor fabrication technology according to the invention is characterized by the arrangement of the passive component directly beneath the packaged chip and the direct electrical connection of the passive component  120  with the substrate and the chip, without the provision of electrically-conductive traces that extend beyond the packaged chip. This feature allows the reduction of parasite capacitance in the semiconductor package that can help ensure the electrical performance of the packaged chip during actual operation, as well as allow the overall package body to be made more compact in size compared to the prior art. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram showing a sectional view of a conventional flip-chip package structure; 
       FIG. 2A  is a schematic sectional diagram used to depict a first procedural step in the flip-chip package fabrication technology according to the invention; 
       FIG. 2B  is a schematic sectional diagram used to depict a second procedural step in the flip-chip package fabrication technology according to the invention; 
       FIG. 2C  is a schematic sectional diagram used to depict a third procedural step in the flip-chip package fabrication technology according to the invention; and 
       FIG. 2D  is a schematic sectional diagram used to depict a fourth procedural step in the flip-chip package fabrication technology according to the invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The semiconductor packaging technology with reduced parasite capacitance according to the invention is disclosed in full details by way of preferred embodiments in the following with reference to  FIGS. 2A–2D  (Note that  FIGS. 2A–2D  are simplified schematic diagrams showing the fundamental package structure according to the invention whose components are not shown in actual number, shape, and scale; the actual layout on the package may be much more complex in practical applications). 
   Referring first to  FIG. 2A , in the fabrication process according to the semiconductor packaging technology of the invention, the initial step is to prepare a substrate  110  and a passive component  120  (note that in this embodiment, only one passive component is used; however, it is to be noted that in actual applications, the number of passive components can be an arbitrary design choice). 
   The substrate  110  is a flat plate made of an electrically-insulating material, which has a front surface  110   a  and a back surface  110   b , and whose front surface  110   a  is formed with a plurality of pads, including a pair of passive-component pads  111 ,  112  and a group of signal pads  113 , where the passive-component pads  111 ,  112  are used for ground/power connections with the passive component  120  and the signal pads  113  are used for signal connections. Moreover, these pads  111 ,  112 ,  113  extend from the front surface  110   a  to the back surface  110   b  of the substrate  110  through electrically-conductive vias (not shown) for connection to solder balls (not shown) that are to be implanted on the back surface  110   b . Alternatively, in other design, the substrate  110  can be a multi-layer structure in which the passive-component pads  111 ,  112  are connected to a corresponding ground/power layer (not shown) in the substrate  110 . 
   The key feature of the semiconductor fabrication technology according to the invention is that the passive-component pads  111 ,  112  are located within the die-mounting area (i.e., the area where the chip  130  is to be mounted), and not outside the die-mounting area as in the case of the prior art of  FIG. 1 . 
   The passive component  120  can be either a resistor or a capacitor, which has two connecting ends: a first connecting end  121  and a second connecting end  122 ; and as shown in  FIG. 2B , the chip  130  has an active surface  130   a  and an inactive surface  130   b , where the active surface  130   a  is defined with a ground pad  131  and a power pad  132  corresponding respectively to the first connecting end  121  and the second connecting end  122  of the passive component  120 . Moreover, the active surface  130   a  of the chip  130  is formed with a plurality of signal pads  133  corresponding to the signal pads  113  on the substrate  110 . Furthermore, the chip  130  is formed with a plurality of bumps  141 ,  142 ,  143  having different height through a bumping process utilizing screen-printing or electroplating technology. The first-type bumps  141 ,  142  on the ground pad  131  and the power pad  132  are lower in height, whereas the second-type bumps  143  on the signal pads  133 . 
   As shown in  FIG. 2A , in packaging process, the first step is to mount the passive component  120  onto the front surface  110   a  of the substrate  110 , in such a manner that the first connecting end  121  and the second connecting end  122  of the passive component  120  are bonded by means of solder  123  to the corresponding passive-component pads  111 ,  112  on the front surface  110   a  of the substrate  110 . 
   Subsequently, as shown in  FIGS. 2B and 2C , in the next step, the chip  130  is mounted in a flip-chip manner onto the front surface  110   a  of the substrate  110 , in such a manner that the shorter first-type bumps  141 ,  142  on the ground pad  131  and power pad  132  on the chip  130  are aligned to the first connecting end  121  and the second connecting end  122  of the passive component  120 , and the larger second-type bumps  143  on the signal pads  133  are aligned to the signal pads  113  on the front surface  110   a  of the substrate  110 , whereby the ground pad  131  and the power pad  132  are electrically connected by means of the first-type bumps  141 ,  142  to the first connecting end  121  and the second connecting end  122  of the passive component  120 , while the signal pads  133  on the chip  130  are electrically connected by means of the second-type bumps  143  to the signal pads  113  for signal transmission. This completes the mounting of the chip  130 . 
   Referring next to  FIG. 2D , in the subsequent step, a flip chip underfill process is performed to form a flip-chip underfill layer  150  in the gap between the substrate  110  and the chip  130 . The flip-chip underfill layer  150  extends to the outside of the chip  130  to form an encapsulation body. Since the flip-chip underfill is a conventional technology, detailed description thereof will not be given in this specification. Subsequent steps include solder ball implantation on the back surface  110   b  of the substrate  110 . However, since all these subsequent steps utilize conventional processes and not within the spirit and scope of the invention, detailed description thereof will not be given in this specification. 
   In the fabricated flip-chip package by the invention, refer to  FIG. 2C , since the passive component  120  is arranged in the gap between the substrate  110  and the chip  130  and electrically interconnected with the substrate  110  and the chip  130  by means of solder  123  and bumps  141 ,  142 , it eliminate the use of electrically-conductive traces and therefore can help reduce parasite capacitance, allowing the packaged chip  130  to have ensured electrical performance during high-frequency operation. Moreover, since the passive component  120  is located outside the die-mounting area, and not within the die-mounting area as in the case of the prior art of  FIG. 1 , it allows the use of a smaller substrate  110  for mounting the chip  130  and the passive component  120 , making the overall package body more compact in size compared to the prior art. 
   In conclusion, the invention provides a semiconductor package structure with reduced parasite capacitance and method of fabricating the same, which is used for the fabrication of a flip-chip package structure, and which is characterized by the arrangement of the passive component directly beneath the packaged chip and the direct electrical connection of the passive component  120  with the substrate and the chip, without the provision of electrically-conductive traces that extend beyond the packaged chip. This feature allows the reduction of parasite capacitance in the semiconductor package that can help ensure the electrical performance of the packaged chip during actual operation, as well as allow the overall package body to be made more compact in size compared to the prior art. 
   The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.