Abstract:
A physical layer device comprises a first port that embeds a first clock into data transmitted over a first physical medium; a second port that embeds a second clock into data transmitted over a second physical medium; a first selection module that outputs the first clock to the first port based on one of a locally generated clock and a recovered clock; and a second selection module that outputs the second clock to the second port based on one of the locally generated clock and the recovered clock. A method comprises embedding a first clock into data transmitted over a first physical medium; embedding a second clock into data transmitted over a second physical medium; generating the first clock based on one of a locally generated clock and a recovered clock; and generating the second clock based on one of the locally generated clock and the recovered clock.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/895,861, filed on Mar. 20, 2007. The disclosure of the above application is incorporated herein by reference in its entirety. 
    
    
     FIELD 
     The present disclosure relates to synchronous network devices and more particularly to synchronizing clocks among multiple ports of synchronous network devices. 
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     Referring now to  FIG. 1 , a partial functional block diagram of a single port of a network device is shown. A physical layer (PHY) module  102  for the port is connected to a physical media  104 . For example, the network device may be an Ethernet device, the physical media  104  may include optical fiber and the PHY module  102  may be 1000BASE-X compliant. In another example, the physical media  104  may include twisted pairs of cable while the PHY module may be 1000BASE-T compliant. 
     The PHY module  102  includes a receiver module  110  that receives data over the physical media  104 . The data received over the physical media  104  includes an embedded clock, which is recovered by a clock recovery module  112 . The clock recovery module  112  provides the recovered clock (RX_CLK) to the receiver module  110 . RX_CLK is also output from the PHY module  102 . The receiver module  110  uses RX_CLK to latch data received over the physical media  104 . The latched data is transmitted to a physical medium attachment module  114 . 
     The physical medium attachment module  114  transmits data to and receives data from a physical coding module  116 . The physical coding module  116  transmits data to and receives data from a media access control (MAC) module  118  external to the PHY module  102 . The PHY module  102  includes a transmitter module  120  that transmits data over the physical media  104  from the physical medium attachment module  114 . The transmitter module  120  transmits data using a transmit clock, TX_CLK, received from outside the PHY module  102 . 
     SUMMARY 
     A physical layer device comprises a first port that embeds a first clock into data transmitted over a first physical medium; a second port that embeds a second clock into data transmitted over a second physical medium; a first selection module that outputs the first clock to the first port based on one of a locally generated clock and a recovered clock; and a second selection module that outputs the second clock to the second port based on one of the locally generated clock and the recovered clock. 
     In other features, the physical layer device further comprises a control module that determines a source of a grandmaster clock, that causes the first selection module to output the locally generated clock when the first port is the source, and that causes the second selection module to output the locally generated clock when the second port is the source. The physical layer device further comprises a third selection module that outputs a selected clock based on one of a first recovered clock from the first port and a second recovered clock from the second port. 
     In further features, the first port recovers the first recovered clock from data received over the first physical medium and the second port recovers the second recovered clock from data received over the second physical medium. The physical layer device further comprises a control module that determines a source of a grandmaster clock, that causes the third selection module to output the selected clock based on the first recovered clock when the first port is the source, and that causes the third selection module to output the selected clock based on the second recovered clock when the second port is the source. 
     In still other features, the control module causes the first selection module to output the locally generated clock when the first port is the source, and that causes the second selection module to output the locally generated clock when the second port is the source. The physical layer device further comprises a clock synchronizer that generates the recovered clock based on the selected clock. The first and second ports and the first, second, and third selection modules are implemented in a first integrated circuit. 
     In other features, the physical layer device further comprises a clock synchronizer that generates the recovered clock based on the selected clock and that is implemented in a second integrated circuit. The physical layer device further comprises a third integrated circuit including a fourth selection module that outputs a second selected clock. The clock synchronizer generates the recovered clock based on one of the selected clock and the second selected clock. 
     In further features, the physical layer device further comprises a control module that determines a source of a grandmaster clock, that causes the clock synchronizer to generate the recovered clock based on the selected clock when the source is from the first integrated circuit, and that causes the clock synchronizer to generate the recovered clock based on the second selected clock when the source is from the third integrated circuit. The first and second selection modules perform hitless switching. 
     A method for controlling a physical layer device comprises embedding a first clock into data transmitted over a first physical medium; embedding a second clock into data transmitted over a second physical medium; generating the first clock based on one of a locally generated clock and a recovered clock; and generating the second clock based on one of the locally generated clock and the recovered clock. 
     In other features, the method further comprises determining a source of a grandmaster clock; generating the first clock based on the locally generated clock when the first physical medium is the source; and generating the second clock based on the locally generated clock when the second physical medium is the source. The method further comprises generating a selected clock based on one of a first recovered clock and a second recovered clock. 
     In further features, the method further comprises recovering the first recovered clock from data received over the first physical medium; and recovering the second recovered clock from data received over the second physical medium. The method further comprises determining a source of a grandmaster clock; generating the selected clock based on the first recovered clock when the first physical medium is the source; and generating the selected clock based on the second recovered clock when the second physical medium is the source. 
     In still other features, the method further comprises generating the first clock based on the locally generated clock when the first physical medium is the source; and generating the second clock based on the locally generated clock when the second physical medium is the source. The method further comprises generating the recovered clock based on the selected clock. The method further comprises generating a second selected clock based on a third physical medium; and generating the recovered clock based on one of the selected clock and the second selected clock. 
     In other features, the method further comprises determining a source of a grandmaster clock; generating the recovered clock based on the selected clock when the source is one of the first and second physical mediums; and generating the recovered clock based on the second selected clock when the source is the third physical medium. The method further comprises performing hitless switching for generating the first clock and for generating the second clock. 
     A physical layer device comprises a first port that embeds a first clock into data transmitted over a first physical medium; a second port that embeds a second clock into data transmitted over a second physical medium; first selection means for outputting the first clock to the first port based on one of a locally generated clock and a recovered clock; and second selection means for outputting the second clock to the second port based on one of the locally generated clock and the recovered clock. 
     In other features, the physical layer device further comprises control means for determining a source of a grandmaster clock, for causing the first selection means to output the locally generated clock when the first port is the source, and for causing the second selection means to output the locally generated clock when the second port is the source. The physical layer device further comprises third selection means for outputting a selected clock based on one of a first recovered clock from the first port and a second recovered clock from the second port. 
     In further features, the first port recovers the first recovered clock from data received over the first physical medium and the second port recovers the second recovered clock from data received over the second physical medium. The physical layer device further comprises control means for determining a source of a grandmaster clock, for causing the third selection means to output the selected clock based on the first recovered clock when the first port is the source, and for causing the third selection means to output the selected clock based on the second recovered clock when the second port is the source. 
     In still other features, the control means causes the first selection means to output the locally generated clock when the first port is the source, and that causes the second selection means to output the locally generated clock when the second port is the source. The physical layer device further comprises clock synchronization means for generating the recovered clock based on the selected clock. The first and second ports and the first, second, and third selection means are implemented in a first integrated circuit. 
     In other features, the physical layer device further comprises clock synchronization means for generating the recovered clock based on the selected clock and that is implemented in a second integrated circuit. The physical layer device further comprises a third integrated circuit including fourth selection means for outputting a second selected clock. The clock synchronization means generates the recovered clock based on one of the selected clock and the second selected clock. 
     In further features, the physical layer device further comprises control means for determining a source of a grandmaster clock, for causing the clock synchronization means to generate the recovered clock based on the selected clock when the source is from the first integrated circuit, and for causing the clock synchronization means to generate the recovered clock based on the second selected clock when the source is from the third integrated circuit. The first and second selection means perform hitless switching. 
     Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the disclosure, are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a partial functional block diagram of a single port; 
         FIG. 2  is a functional block diagram of a multiple port PHY module; 
         FIG. 3  is a flowchart that depicts exemplary steps performed in controlling the system of  FIG. 2 ; 
         FIG. 4A  is a functional block diagram of a high definition television; 
         FIG. 4B  is a functional block diagram of a set top box; and 
         FIG. 4C  is a block diagram of a Metro Ethernet network. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure. 
     As used herein, the term module refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. 
     To allow a network device to have the properties of a synchronous network, such as SONET (synchronous optical network), clocks of the devices in the network device are synchronized. For example only, the network device may be a wired Ethernet network device. One method of synchronization is to send packets having time stamps. Using determinations of one-way delay and round-trip delay based on the time stamps, devices in the network can synchronize their internal clocks. These time stamps may be used to decrease latency and variability introduced by a protocol stack. Network based delay, such as delay caused by traffic congestion, may affect the accuracy of the timestamps. 
     Another approach to clock synchronization involves using a recovered clock. In this approach, a single node is chosen as the source of a grandmaster clock. This node may be chosen because of the quality of its clock. For example, a node connected to or receiving time information from an atomic clock may be viewed as the most desirable clock source. This grandmaster clock is then distributed to the other nodes. 
     When the node having the grandmaster clock source links with another node, the grandmaster clock is used when transmitting data. This grandmaster clock is then recovered by the receiving node. The receiving node adjusts its local clock based thereon and then transmits data to nodes linked with the second node (using the clock adjusted by the grandmaster clock). In this way, the grandmaster clock can be distributed to all the nodes. 
     A node may have multiple ports. The grandmaster clock may be received on one port and sent on the remaining ports. Each port from which a node transmits the grandmaster clock may be called a synchronous master, while each port receiving the grandmaster clock may be referred to as a synchronous slave. Synchronous master/slave relationships may be established independent of PHY module. For example, synchronous master/slave relationships may be established for twisted pair physical media and optical fiber physical media. 
     The master/slave relationships may be configured manually by a network administrator. Alternatively, a protocol may be defined where the nodes dynamically determine the node that will be the grandmaster clock source and the tree through which the grandmaster clock source will be distributed. This protocol may be integrated with a protocol such as a spanning tree protocol, which prevents circular loops from being created. 
     In 1000BASE-T, another form of master/slave relationship is defined. This is defined in clause 40 of IEEE 802.3, the disclosure of which is incorporated herein by reference in its entirety. According to clause 40, two nodes that desire to establish a link must decide which will be the master and which will be the slave. Often, personal computers prefer to be the slave while network switches prefer to be the master. 
     If both sides prefer the same role, each may pick a random number and a comparison of the random numbers is used to make the assignment. Instead of preferring to be master, one of the nodes may be forced to be master. In this case, the node will become master unless its linked partner is also being forced to be master. When both nodes are being forced to assume the same role, a link may not be established. 
     The clause 40 master/slave relationship may disagree with the synchronous master/slave relationship. If a protocol is defined to dynamically determine the distribution of the grandmaster clock, the clause 40 master/slave relationships could be assigned to match the synchronous relationships at the same time. The links in the network can then be broken and reestablished, thereby establishing the desired master/slave relationships for both synchronous arrangements and clause 40. Alternatively, the clause 40 master/slave relationships may be manually programmed, such as when the synchronous master/slave relationships are manually programmed. 
     In brief,  FIG. 2  shows a group of multiport PHY integrated circuits (ICs) that allow programmatic control of grandmaster clock distribution. Multiple ports, and in the example of  FIG. 2 , all ports, may be used as the source of the grandmaster clock. The recovered clock from the port that is the source of the grandmaster clock is provided to a clock synchronizer, which cleans up the recovered grandmaster clock. The clock synchronizer may perform such operations as removing jitter, controlling the voltage swing, and establishing fixed edge rates. The improved grandmaster clock may then be provided to all other ports for use in transmission. 
     When these other ports are transmitting using the improved grandmaster clock, their link partners will be receiving the grandmaster clock. The port of a node that is receiving the grandmaster clock may transmit using a local oscillator to prevent a loop from occurring when the recovered clock is passed to the clock synchronizer and back to the same port.  FIG. 3  depicts exemplary steps performed in operating the system of  FIG. 2 , and  FIGS. 4A-4B  provide exemplary environments where the system of  FIG. 2  may be used. 
     Referring now to  FIG. 2 , a functional block diagram of a multiple port PHY module is shown. A multi-port PHY IC  202 - 1  includes multiple PHY ports  204 - 1 . In the example of  FIG. 2 , the multi-port PHY IC  202 - 1  includes four PHY ports  204 - 1 . 
     The RX_CLK from each of the PHY ports  204 - 1  is received by an output multiplexer  220 - 1 . The output multiplexer  220 - 1  is controlled by a control module  230 . The multiplexer  220 - 1  selects the RX_CLK from the port within the multi-port PHY IC  202 - 1  that is receiving the grandmaster clock. This selection may be programmed into the control module  230 , such as by setting a value in a control register. 
     The output multiplexer  220 - 1  transmits the selected RX_CLK to a clock synchronizer  240 . The clock synchronizer  240  cleans up the received clock and transmits the improved clock back to the multi-port PHY IC  202 - 1 . The multi-port PHY IC  202 - 1  also receives a local oscillator clock. The local oscillator clock may be generated by an external crystal oscillator  250 - 1 . In various implementations, only the crystal is external to the multi-port PHY IC  202 - 1 , while the drive circuitry for the crystal is located within the multi-port PHY IC  202 - 1 . In various other implementations, the local oscillator is located entirely within the multiport PHY IC  202 - 1 . 
     Each of the PHY ports  204 - 1  is associated with an input multiplexer  260 - 1 . The input multiplexer  260 - 1  selects the clock from either the local oscillator or the improved grandmaster clock from the clock synchronizer  240  as the TX_CLK for the port  204 - 1 . These multiplexers  260 - 1  are also controlled by the control module. If a port  204 - 1  is designated as the source of the grandmaster clock, the multiplexer  260 - 1  will select the local oscillator to be the TX_CLK for that port. Otherwise, the TX_CLK will be received from the clock synchronizer  240 . 
     The clock synchronizer  240  may use a stable reference clock from a clock reference  270  to process the selected clock input. The reference clock may be used by a phase locked loop within the clock synchronizer  240 . In various implementations, multiple multi-port PHY ICs may be used. In  FIG. 2 , N multi-port PHY ICs from  202 - 1  through  202 -N are shown. The selected output RX_CLK from the multiplexers  220  is received by the clock synchronizer  240 . 
     The control module  230  indicates to the clock synchronizer  240  which of the multi-port PHY ICs  202  will be the source of the grandmaster clock. The RX_CLK from that multi-port PHY IC  202  will be used by the clock synchronizer  240  to provide the improved clock to each of the multi-port PHY ICs  202 . If there are more multi-port PHY ICs  202  than there are inputs to the clock synchronizer  240 , an additional multiplexer may be used. 
     The multiplexers  260  may provide gradual, or hitless, switching from one clock input to another. This can prevent glitches from occurring in the TX_CLK provided to the ports  204 . The multiplexers  220  may also provide hitless switching. In addition, the clock synchronizer  240  may perform hitless switching when switching between received RX_CLKs from the multi-port PHY ICs  202 . 
     Referring now to  FIG. 3 , a flowchart depicts exemplary steps performed in controlling the system of  FIG. 2 . Control begins in step  302 , where a port is selected to be a source of the grandmaster clock. The selected port is assumed to be recovering the grandmaster clock from transmissions by its link partner. Control continues in step  304 , where the multi-port PHY IC is configured to output the RX_CLK of that grandmaster source port. 
     Control continues in step  306 , where the TX_CLK for that grandmaster source port is configured to be taken from the local oscillator. Control continues in step  308 , where the TX_CLK for all other ports is configured to be taken from the output of the clock synchronizer. Control continues in step  310 , where the clock synchronizer is configured to synchronize based on the recovered clock from the multi-port PHY IC that includes the grandmaster source port. 
     In various implementations, the local node may be the original source of the grandmaster clock. In this case, the grandmaster clock may be provided to the clock synchronizer from the source of the grandmaster clock. For example, this may come from an atomic clock or some other stable clock. No ports within the multi-port PHY IC will be the source of the grandmaster clock therefore. Each port will therefore transmit using the output of the clock synchronizer as the TX_CLK. The RX_CLK selected by the multiplexers will be irrelevant because the clock synchronizer is using a local grandmaster clock. 
     Referring now to  FIGS. 4A-4B , various exemplary implementations incorporating the teachings of the present disclosure are shown. Referring now to  FIG. 4A , the teachings of the disclosure can be implemented in a network interface  443  of a high definition television (HDTV)  437 . The HDTV  437  includes an HDTV control module  438 , a display  439 , a power supply  440 , memory  441 , a storage device  442 , the network interface  443 , and an external interface  445 . If the network interface  443  includes a wireless local area network interface, an antenna (not shown) may be included. 
     The HDTV  437  can receive input signals from the network interface  443  and/or the external interface  445 , which can send and receive data via cable, broadband Internet, and/or satellite. The HDTV control module  438  may process the input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of the display  439 , memory  441 , the storage device  442 , the network interface  443 , and the external interface  445 . 
     Memory  441  may include random access memory (RAM) and/or nonvolatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device  442  may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The HDTV control module  438  communicates externally via the network interface  443  and/or the external interface  445 . The power supply  440  provides power to the components of the HDTV  437 . 
     Referring now to  FIG. 4B , the teachings of the disclosure can be implemented in a network interface  485  of a set top box  478 . The set top box  478  includes a set top control module  480 , a display  481 , a power supply  482 , memory  483 , a storage device  484 , and the network interface  485 . If the network interface  485  includes a wireless local area network interface, an antenna (not shown) may be included. 
     The set top control module  480  may receive input signals from the network interface  485  and an external interface  487 , which can send and receive data via cable, broadband Internet, and/or satellite. The set top control module  480  may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may include audio and/or video signals in standard and/or high definition formats. The output signals may be communicated to the network interface  485  and/or to the display  481 . The display  481  may include a television, a projector, and/or a monitor. 
     The power supply  482  provides power to the components of the set top box  478 . Memory  483  may include random access memory (RAM) and/or nonvolatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device  484  may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). 
     Referring now to  FIG. 4C , the teachings of the disclosure can be implemented in a network switch (e.g., any or all of network switches  454 ) of a Metro Ethernet  450 . Generally, a Metro Ethernet is a computer network based on the Ethernet standard and which covers a metropolitan area. A Metro Ethernet is commonly used as a metropolitan access network to connect subscribers and businesses to a Wide Area Network, such as the Internet. 
     In various implementations, each network switch  454  of the Metro Ethernet  450  includes a multiple port PHY module  456  (e.g., as shown in  FIG. 2 ) to distribute a grandmaster clock  458  to other switches  454  and/or end nodes  452 . The teachings of the disclosure can further be implemented in other types of networks—e.g., a synchronous Ethernet. For example, using techniques disclosed herein, some or all laboratory equipment can be synchronized to the same clock, or some or all factory floor robots can be synchronized to the same clock. 
     The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims.