Abstract:
An equivalent circuit for a synthetic inductor is disclosed. The circuit in this invention utilizes a plurality of N-channel and P-channel FET devices, resistors and capacitors that can be easily fabricated using standard integrated circuit processing. The inductances that can be fabricated are on the order of 100 μH to 100 mH with a frequency response achievable to greater than 10 Mhz.

Description:
BACKGROUND OF INVENTION 
     1. Field of Invention 
     This invention relates to the circuits used to simulate the electrical characteristics of an inductor and in particular those circuits that can be easily fabricated using standard integrated circuits processing techniques. 
     2. Description of Related Art 
     The design of electrical filters and similar applications require the 5 use of resistors (R), capacitors (C), and inductors (L). Practical inductors can not be implemented easily on integrated circuits. The use of passive resistors/capacitors (RC) networks while practical, occupy a relatively large amount of space if implemented in integrated circuits. The RC networks generally are limited to simple applications where a low quality factor (Q) is acceptable. 
     Active filters incorporating operational amplifiers have very powerful applications since almost any frequency transfer function can be implemented. The bandwidth of these applications, however, will generally be limited to lower frequencies such as in the audio band because of the limited bandwidth of most operational amplifiers. 
     In FIG. 1A a typical simple series RLC filter is illustrated. The voltage source V in  provides a voltage that is: 
     
         V.sub.in =V.sub.mix sin(ωt). 
    
     where 
     V max  is the maximum value of the voltage of the source; 
     ω is the frequency of the signal in radians per second; 
     t is the time from the application of the voltage source in seconds. 
     The characteristic of an inductor is that current through the inductor is delayed by π/2 radian in phase from the voltage applied to its terminals, the impedance Z L  of the inductor L is: 
     
         Z.sub.L =jωι.sub.L 
    
     where ##EQU1## ω is the frequency of the signal in radians per second. 
     ι L  is the value of the inductance of the inductor L in henries. 
     The impedance Z R  of the resistor R is: 
     
         Z.sub.R =r.sub.R 
    
     where 
     r R  is the value of the resistor R in ohms (Ω). 
     The impedance Z c  of the Capacitor C is: ##EQU2## where ##EQU3## ω is the frequency of the signal in radians per second; C c  is the value of the capacitance of the capacitor C in Farads. 
     The current i through the network formed by the inductor L, Resistor R, and the Capacitor C is: ##EQU4## and the voltage V out  is: ##EQU5## 
     FIG. 2 is a plot of the gain (5 V at  /V in ) of the circuit of FIG. 1A as a function of the frequency (Hz) of the voltage source V in  as expressed in decibels (db). Because of nonidealities in the construction of an inductor, a pure inductance is impossible to achieve. A physical inductor is an ideal inductor in series with a resistor. Theoretically the series resistance can be further reduced with advanced IC processing and further circuit optimization. 
     U.S. Pat. No. 3,448,411 (M. Patterson) teaches a circuit for simulating the electrical characteristics of air core and iron core inductance coils. U.S. Pat. No. 5,093,642 (Mittel) describes a solid state mutually coupled inductor. 
     U.S. Pat. No. 3,835,399 (R. Holmes) demonstrates a network of operational amplifiers coupled to simulate an inductor. 
     U.S. Pat. No. 5,235,223 (C. Maple) describes a tunable circuit using synthetic inductors and capacitor multipliers in place of discrete inductive and capacitive elements. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to provide an equivalent circuit for an inductor that is easily implemented on integrated circuits with efficient use of space. Another object of this invention is to provide a simulated inductor that can replicate the frequency response of an inductor over a wide bandwidth. The schematic circuit for a wideband inductor, as shown in FIG. 4, consists of a first and second P-channel Field Effect Transistor (FET) M 1  and M 2  connected in o such a fashion that the current through the drains of each P-channel FET tracks each other; a first N-Channel FET M 7  and a third P-Channel FET M 8  that has a resistor R connected between the sources; a second N-channel FET M 6  that has its drain connected to the gate of the first N-Channel FET M 7  and to a first connection terminal A; a third N-Channel FET M k  that has its gate connected to the drain of the second P-Channel FET M 2 , a current source I s , and a first terminal of a capacitor C i  ; a dc voltage source V c  coupled between the gate of the second N-Channel FET M 6  and ground. The second terminal B is connected to the gate of the third P-channel FET M 8 . 
     Other objects, features, and advantages of the invention will become evident from the following detailed description of the invention when considered in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A a is schematic drawing of a simple RLC circuit. 
     FIG. 1B is schematic drawing of an RLC circuit showing the connectivity for the synthetic inductor of this invention. 
     FIG. 2 is a logarithmic plot of the gain versus frequency of the circuit shown in FIG. 1. 
     FIG. 3 is an equivalent circuit diagram of this invention. 
     FIG. 4 is a schematic drawing of an embodiment of this invention. 
     FIG. 5 is a modification of the preferred embodiment of this invention. 
     FIG. 6 is a logarithmic plot of the gain versus frequency of the embodiment shown in FIG. 5 with different values of the biasing current I s . 
     FIG. 7 is another logarithmic plot of gain versus frequency of the embodiment shown in FIG. 5 with different values of the voltage source V c . 
     FIGS. 8A and 8B are a logarithmic plots of the equivalent impedance (Z AB ) versus frequency and the phase shift of the equivalent impedance (θ(Z AB )) of the embodiment shown in FIG. 5 as compared with that of a ideal 300 μH inductor in series with a 55Ω, resistor. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 is an equivalent circuit diagram of the synthetic inductor. Terminal A and terminal B are the input terminals of the circuit that will couple to terminals A and B of FIG. 1B. Terminal A is connected to the positive terminal of buffer amplifier X 1  and terminal B is connected to the positive terminal of buffer amplifier X 2 . The buffer amplifiers X 1  and X 2  generate a current I X  through resistor R X . Since buffer amplifiers X 1  and X 2  have unity gain, the current ##EQU6## 
     The linear current controlled current source I y  will source current that is: 
     
         I.sub.Y =N·I.sub.x 
    
     where N is the constant multiplier factor of the current 
     source I Y . 
     The current source I Y  sources its current into capacitor C i  to develop a voltage across capacitor C i  that is V Y . The voltage ##EQU7## where Z Ci  is the impedance of capacitor Ci which is ##EQU8## 
     The AC component of V Y , which is νy, is ##EQU9## where s=jω 
     V AB  is the AC component of V AB . 
     The voltage supply V c  is coupled to operational amplifier X 3 . Operational amplifier X 3  is configured with N-channel FET M 100  such that it will provide the constant voltage V c  to the source of N-channel FET M 100 . The drain of M 100  is coupled to the input terminal A. The voltage controlled resistor R VCR  is connected between the source of the N-channel FET M 100  and the input terminal B. The resistance of the voltage controlled resistor R VCR  is ##EQU10## where K is a constant multiplier of the resistance. Since the source of the N-channel FET M 100  is always at the voltage V c , the current I R  is: ##EQU11## with the AC component being: ##EQU12## 
     In FIG. 4 a circuit schematic of the preferred embodiment of this invention is shown. The currents I d1  and I d2  are equal and ##EQU13## where V AB  is the voltage developed from the first connection terminal A and the second connection terminal B; 
     V gs7  is the voltage developed from the gate to the source of the N-Channel FET M 7  ; 
     kV gs8  is the voltage developed from the gate to the source of the P-Channel FET M 8 . 
     Each current I x  in this schematic is composed of two components, a DC component I x  and an AC component i x  where: 
     
         I.sub.x =I.sub.x +I.sub.x. 
    
     Also, each voltage V x  in this schematic is composed of two components, a DC component V x  and an AC component ν x  where 
     
         V.sub.x =V.sub.x +ν.sub.x 
    
     From the above, then ##EQU14## where i d1  =i d7  =i d8  ; 
     i d7  is the AC component of the drain current of M 7  ; 
     i d8  is the AC component of the drain current of m 8  ; 
     I d1  is the DC component of I d1  ; 
     i d1  is the AC component of I d1  ; 
     V gs7  is the DC component of the gate to source voltage of N-Channel FET M7; 
     V gs8  is the DC component of the gate to source voltage of P-Channel FET M 8  ; 
     gm 7  is the small signal transconductance of N-Channel FET M 7  ; 
     gm 8  is the small signal transconductance of P-Channel FET M 8 . 
     Solving for i d1  : ##EQU15## The DC component of the current source I s  is equal to the DC component of I d2  therefore: 
     
         I.sub.d2 -I.sub.s =i.sub.d2. 
    
     Since i d1  =i d2 , then: ##EQU16## 
     The AC component of the gate to source voltage of the N-Channel FET M k  is: ##EQU17## Substituting for i d2  : ##EQU18## 
     The N-channel FET must be biased such as to operate in the linear region of its operating characteristics i dk  is controllable by the voltage source V c . Therefore 
     
         i.sub.dk =β.sub.k V.sub.dsk ν.sub.gsk 
    
     where 
     i dk  is the drain current of the N-channel FET M k  ; 
     β k  is the transconductance factor of the N-channel FET M k  ; 
     V dsk  is the drain to source voltage of the N-channel FET M k . 
     Since ##EQU19## where V c  is the voltage of the voltage source V c  ; 
     V gs6  is the DC component of the gate source voltage of the 
     N-Channel FET M 6  ; 
     g m6  is the small signal transconductance of the N-Channel FET M 6 . 
     Solving for i dk  ##EQU20## 
     The impedance Z AB  as is present between the terminals A and B is defined as: ##EQU21## Substituting for ν AB  and i dk  then ##EQU22## Let Z AB  be 
     
         Z.sub.AB =sL.sub.AB 
    
     where 
     L AB  is the inductance as observed between terminals A and B. 
     Then ##EQU23## 
     The synthetic inductor of this invention has three sources of nonideality. These are: 
     1. The limited transconductance of the N-channel FET&#39;s which causes the voltage follower created by N-channel FET M6 of FIG. 4 to be nonideal creating the error term: ##EQU24## 
     2. The input impedance Z AB  is in parallel with r dsk  that is the drain to source resistance of N-channel FET M K  of FIG. 4. 
     3. The parasitic capacitance coupling with the circuit causes delay to the synthetic inductor and limits the bandwidth of the synthetic inductor. 
     The nonidealities impact the performance of the synthetic by creating a series resistor and limiting the bandwidth. 
     The synthetic inductor is for use as a small signal equivalent to a real inductor. The synthetic inductor is also polarized wherein the terminal A of FIG. 4 and FIG. 5 must be positive and the terminal B of FIG. 4 and FIG. 5 must be negative. If the circuit terminals are reversed, the circuit can not perform. 
     Additionally, the synthetic inductor requires a small DC bias current to operate. Referring to Fig 1B, a current source I appl--bias  is added to the circuit of FIG. 1A to create the necessary bias for the synthetic inductor L. 
     P-channel FET M 1  is configured as a Metal Oxide Semiconductor diode such that a control current through the diode is the current flowing through the resistor R. 
     FIG. 5 is a schematic used for SPICE simulation, The P-channel FET M 8  of FIG. 4 is replaced with a PNP bipolar junction transistor Q 8  and other modifications have been made to enhance performance. 
     The P channel FET M 10  is added in FIG. 5 to suppress the coupling of AC noise with in the circuit and to create with P-channel FET M2 a better current source than shown in the circuit of FIG. 4. 
     The equation of the equivalent inductance is the same as in FIG. 4. That ##EQU25## where now ##EQU26## gm 7  is the transconductance of N-channel FET M 7  g ms  is the transconductance of PNP bipolar junction transistor Q s . 
     Capacitor C n  and C s  in FIG. 5 are added to the circuit of the synthetic inductor to make the voltage follower formed by N-channel FET M 6  and the voltage followers formed by N-channel FET M 7  and PNP bipolar junction transistor Q 8  resistant to coupling of AC noise. 
     FIG. 6 is a plot of the gain (db) V at  /V in  of FIG. 1B versus the frequency wherein the circuit of FIG. 5 replaces the inductor L and series resistor R of FIG. 1B. The current bias of I s  of FIG. 5 is varied from 15 μA to 20 μA to 25 μA. The change in the biasing current will control the inductance of the synthetic inductor and fine tune the frequency response of the network. 
     FIG. 7 is another plot of the gain (db) V at  /V in  of FIG. 1B versus the frequency wherein the circuit of FIG. 5 replaces the inductor L and series resistor R of FIG. 1B. With this plot, the values of voltage source V c  of FIG. 5 are varied from 1.1 V to 1.3 V in 0.05 V increments. The changes in the values of voltage source V c  of FIG. 5 can be used change the frequency response of the synthetic inductor. 
     In standard integrated circuit process, the parameters of the process can not be controlled precisely. With the ability to add tuning and control circuitry, such as an auto tracking unit, the performance objectives of the synthetic inductor can be met. 
     Referring to FIG. 2, FIG. 6, and FIG. 7 together, the behavior of the synthetic inductor can be seen to be similar to that of ideal inductor L in series with a resistor R up to frequencies above 10 Mhz. This performance is achieved with a total current of less than 25 μA. 
     Referring to FIGS. 8A and 8B, the amplitude and phase shift of the equivalent impedance (Z AB ) of the synthetic inductor of FIG. 5 is compared to that of ideal inductor L in series with a resistor R of FIG. 1A. As can be seen in FIG. 8A, the amplitude 20 of impedance of the synthetic inductor matches the amplitude 10 of the ideal inductor until the operating frequency is above 10 Mhz. Referring to FIG. 8B, the phase shift 40 of the synthetic inductor is nearly identical to that of the ideal inductor until the frequency is beyond 10 Mhz. Improvements in integrated circuits processing will improve this frequency response to well beyond the 10 Mhz shown. 
     The values of components as specified in FIG. 1A, FIG. 1B, and FIG. 5 are for reference only and may be modified to effect changes in the performance of the synthetic inductor. Synthetic inductors can be fabricated with the embodiment of this invention have a range 100 μH to 100 mH with acceptable device geometries in current semiconductor process methods. Advances in semiconductor processing will improve performance and increase the bandwidth. Furthermore, any changes in semiconductor material types will not effect the operation of the circuit with appropriate changes in the design parameters. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.