Abstract:
A phase locked loop includes a buffer that synchronizes the transmission of the new count value to the completion of the previous count to avoid errors caused by dithering. The buffer is connected to a count input of the counter and transmits the new count upon receipt of the carryout signal from the counter. Alternatively, the transmission of the new value of N from the buffer is delayed after receipt by the buffer of a carryout signal from the counter. In another embodiment, a delayed version of the carryout signal is used to trigger the buffer to transmit the new count value to the counter. In another feature, a buffer synchronizes phase data to a reference signal before inputting it to a digital modulator of the phase locked loop.

Description:
FIELD OF THE INVENTION 
     The invention relates generally to phase locked loop systems, and more particularly to signal modification in a fractional-N phase locked loop system. 
     BACKGROUND OF THE INVENTION 
     Phase locked loop systems, also known as phase locked loops, are used for a wide variety of purposes, such as frequency synthesizers and phase modulators in transceivers for wireless communications devices such as GSM (Global System for Mobile communications), PCS (Personal Communication System), PCN (Personal Communications Network), and DECT (Digital Enhanced Cordless Telecommunications) devices. 
     In a divide-by-N phase locked loop (“PLL”), a reference signal at a reference frequency is input to a phase/frequency detector along with a feedback signal derived from the output of the PLL. The output of the frequency/phase detector is connected to a charge pump. The filtered output of the charge pump is applied to a voltage controlled oscillator to generate an output signal at the desired frequency. The output signal frequency is divided by a value of N using a counter that functions as a frequency divider, the carryout signal of which forms the feedback signal input to the phase/frequency detector. 
     In a divide-by-N PLL, the output frequency cannot be varied in steps any smaller than the reference frequency. This limitation has led to the development of fractional-N phase locked loops. In a fractional-N phase locked loop, the value of N is changed over time so that changes in frequency in steps less than the reference frequency can be realized. 
     In this fractional-N type of PLL, it is desirable to synchronize the transmission to the counter of the new value of N with the completion of the previous count. However, it is also necessary to synchronize the generation of the new values of N with the reference frequency. Unfortunately, these two events are asynchronous. This leads to dithering between the completion of the previous count and the generation of the new value of N. This dithering may result in new values of N not being loaded into the counter and/or the same values of N being loaded into the counter twice. Either event can cause frequency and/or phase errors in the output of the voltage controlled oscillator. 
     What is needed is a technique to prevent errors in dithering. Additionally, when such a PLL is used as a digital phase modulator, it is necessary for the phase data to be synchronized to the reference frequency. If phase data is supplied to the PLL asynchronously, a technique for synchronizing the phase data to the reference frequency is also needed. Moreover, it would be helpful to have general techniques for modifying electromagnetic waves in phase locked loop devices as well as other similar devices to meet needs in the art. 
     SUMMARY OF THE INVENTION 
     The present invention meets the aforementioned needs to a great extent, through disclosing methods and apparatus for signal modification in a phase locked loop. For example, the preferred embodiments modify a signal in a phase locked loop by synchronizing an input to a divider in the phase locked loop to a carryout signal generated by the divider. Apparatus of the preferred embodiments comprise a phase/frequency detector, the phase/frequency having a first input and a second input, the first input being connectable to a reference signal; an oscillator for generating a desired output signal; a charge pump and a loop filter connected in series between the output of the phase/frequency detector and an input of the oscillator; a divider connected to receive the output signal generated by the oscillator, the divider having a count input and a carryout output, the carryout output being connected to the second input of the phase/frequency detector; and a buffer connected to supply a count signal to the count input of the divider under the control of the carryout output of the divider. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention and many of the attendant features and advantages thereof will be readily obtained as the same become better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIG. 1  is a block diagram of a fractional-N phase locked loop according to a first embodiment of the invention. 
         FIG. 2  is a block diagram of a fractional-N phase locked loop according to a second embodiment of the invention. 
         FIG. 3  is a block diagram of a digital phase modulator incorporating a fractional-N phase locked loop according to a third embodiment of the invention. 
         FIG. 4  is a block diagram of a digital phase modulator incorporating a fractional-N phase locked loop according to a fourth embodiment of the invention. 
         FIG. 5  is a block diagram of a wideband modulator incorporating a fractional-N phase locked loop according to a fifth embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be discussed with reference to preferred embodiments of the invention. The preferred embodiments discussed herein should not be understood to limit the invention. Furthermore, for ease of understanding, certain method steps are delineated as separate steps; however, these steps should not be construed as necessarily distinct nor order dependent in their performance. 
       FIG. 1  illustrates a fractional-N PLL  100  according to an embodiment of the invention. A reference signal  105  at a reference frequency f ref  is applied to one of the inputs of a phase/frequency detector  110 . A second other input to the phase/frequency detector  110  is supplied by a carryout signal  165 , at a frequency f 1 , from variable divider  160 , which comprises a programmable counter in preferred embodiments. The phase/frequency detector  110  compares both input frequencies f ref  and f 1  and generates an output that is a measure of their phase difference. If there is a difference in frequency between the two signals input to the phase/frequency detector  110 , the output of the phase/frequency detector  110  is a signal that vanes at the difference frequency. 
     The output of the phase/frequency detector  110  is connected to a charge pump  120 . Charge pump  120  outputs current pulses whose width is proportional to the output of the phase/frequency detector. These current pulses are integrated and filtered by the loop filter  130  to provide a control voltage for the VCO  140 . The output of the charge pump  120  is connected to a loop filter  130 . The output of the loop filter  130  is connected to a voltage controlled oscillator (VCO)  140 , which outputs a signal  145  at an output frequency proportional to the voltage supplied by loop filter  130 . The output signal  145  of the VCO  140  is also connected to a pre-scaler  150 . The pre-scaler  150  performs an initial frequency division of the VCO output signal  145 . The output of the pre-scaler  150  is connected to the input of a variable divider  160 . Thus, the value of N by which the frequency of VCO output signal  145  will be divided is determined by pre-scaler  150  and variable divider  160 . The pre-scaler in this embodiment is fixed, but it should be noted that it may be desired in other embodiments to use a programmable pre-scaler. 
     It may be desired, in other embodiments, to realize a fractional-N PLL without a pre-scaler, and so establish a value of N by which the frequency of a VCO output signal will be divided through a variable divider. However, in certain power-critical applications, such as wireless communication device transceivers, the use of a pre-scaler can result in a power savings, among other uses. In yet other applications a pre-scaler embodiment might compensate for possible environments, such as when a desired output signal, e.g.  145 , may be at a frequency that is higher than that at which a variable divider, e.g.,  160 , is capable of functioning. 
     Returning now to the embodiment of  FIG. 1 , variable divider  160  is typically a counter, which counts to a value N received from buffer  171 . Buffer  171  accepts new count values N from the modulator  170  and stores them until the carryout signal  165  is received from the variable divider  160 . When the buffer  171  detects the carryout signal  165 , the new value of N is transmitted from the buffer  171  to the variable divider  160 . Thus, the new value of N will not be transmitted to the variable divider  160  prior to the completion of the previous count. 
     When the count of the variable divider  160  reaches N, the carryout signal  165  is generated. The carryout signal, is input to the phase/frequency detector  170 , and also fed back to the reset input of variable divider  160  so that it resets and inputs a next value count value N from the buffer  171 . The phase/frequency detector  110  measures a difference in frequency between the carryout signal  165  and the reference signal  105 . 
     The modulator  170  generates an output signal comprising a succession of values N such that the long term average of the values N results in a desired frequency and/or phase in the output  145  of the VCO  140 . A sigma delta modulator (SDM) may be used for this purpose. In highly preferred embodiments, the SDM is a digital third order SDM with a three bit output, which implies that the count variable N output by the SDM varies between 2 3 =8 values. 
     The reference signal  105  is also input to modulator  170  such that the new values of N in the output of the modulator  170  are synchronized to the reference signal  105 . 
     Buffer  171  acts to some extent as a delay, and in other embodiments may incorporate a dedicated delay element as well. In yet other embodiments, as further described below, a discrete delay element may be used. 
       FIG. 2  illustrates a PLL  200  according to another embodiment of the invention. The PLL  200  is similar to the PLL  100 , of  FIG. 1 , with a discrete delay element  272  added between the buffer  271  and the variable divider  260 . The delay element can be any circuit (e.g., appropriately clocked data flip flops) that will add a delay between the time the carryout signal  265  is generated and the time when the new count value N reaches the variable divider. 
     The delay element  272  is shown in  FIG. 2  as an addition to the buffer  271 . However, the delay introduced by a delay element may also be used in place of a buffer in some embodiments. In those embodiments, the output of a modulator is connected to an input of the delay element. A maximum expected dither is determined and the delay introduced by delay element is chosen to exceed the maximum expected dither. It should be understood that a delay element may be physically separate from or may be incorporated into a modulator. 
     A PLL  300  according to a third embodiment of the invention is illustrated in  FIG. 3 . The PLL  300  is similar to the PLL  100 , of  FIG. 1 , with the exception that a delay element  374  has been added between the carryout output of the variable divider  360  and the buffer  371 . The delay element  374  of  FIG. 3  achieves the same result as the delay element  272  of FIG.  2 —it delays the time between the generation of the carryout signal from the variable divider  360  and the transmission of the new count N to variable divider  360  to guard against dithering problems. The delay element  374  of  FIG. 3  accomplishes this result by delaying the receipt of the carryout signal at the buffer  371  rather than delaying the output of the buffer  371 . The delay element  374  may be accomplished by any number of circuits (e.g., an appropriately clocked data flip flop). Delay element  374  may be physically separated from or incorporated into buffer  371 . 
     If desired, in yet other embodiments, a delay element similar to delay element  374  of  FIG. 3  may be used in place of or in addition to a delay element similar to delay element  272  of  FIG. 2 . 
     A PLL  400  according to a fourth embodiment of the invention is illustrated in  FIG. 4 . The PLL  400  of  FIG. 4  is believed to be particularly applicable to PLLs used in phase modulators and therefore is so illustrated in  FIG. 4  and discussed in that context below. However, this embodiment of the invention should not be understood to be limited to phase modulators. 
     The PLL  400  is similar to the PLL  100  of  FIG. 1 . A frequency data source  480  and a data synch  481  have been added. In this embodiment, the data from frequency data source  480  is clocked at a different frequency than the reference frequency. Providing different rates for the source and reference frequencies allows for more flexibility in each part of the embodiment, so that, for example, the various components may be optimized independently of one another as the same data rate for each need not be chosen. 
     The frequency data source  480  can be of any type, including, but not limited to, a digital signal processor. The frequency data source  480  supplies data to the PLL  400 . Frequency data source  480  is connected to an input of data synchronizer  481 . A second input of data synchronizer  481  is connected to the reference signal f ref    405 . The output of data synchronizer  481  is connected to the modulator  470 . Data synchronizer  481  synchronizes the input of phase data to the modulator  470 . As will be appreciated by those of skill in the art, the data synchronizer may be a buffer, a bank of data flip flops, a register, or any other circuit capable of performing this function. These embodiments and variants may be desired when the frequency data source  480  is clocked at a different frequency than the reference frequency or located remotely. 
     Embodiments may be used in wideband modulators, such as those appropriate for applications including, but not limited to, transceivers for cell phones, e.g., CDMA, CDMA2000, W-CDMA, GSM, TDMA, and the various types of digital modulation techniques used therein, such as GMSK used in GSM, GFSK used in DECT and Bluetooth, 8-PSK used in EDGE, OQPSK and HPSK used in IS-2000, π/4 DQPSK used in TDMA and OFDM used in 802.11.; as well as, other types of devices, both wired and wireless, e.g. Bluetooth, 802.11a, -b, -g, GPS, radar, 1xRTT, radios, GPRS, computers and computer communication devices, handheld devices, etc. 
       FIG. 5  illustrates an embodiment that may be desirable for use in a cellular phone transceiver. A portion  500  of a transceiver includes three sections: an amplitude/phase signal processor  1101 , a wideband modulator  1102 , and an adaptive phase realignment circuit  1103 . 
     The wideband modulator  1102  comprises a phase locked loop  1126  (comprising a phase/frequency detector  1130 , a low pass filter  1131 , a voltage controlled oscillator  1129 , and a variable divider  1128 ), a reference source  1127 , and a third-order SDM  1125 . The input to the variable divider  1128  of the PLL  1126  is connected to a buffer  1132 , which is controlled by the carryout signal  1133  from the variable divider  1128  to input new count data to the variable divider  1128 . The new count data input to the buffer  1132  comprises a summed integer part corresponding to a desired channel received from amplitude and phase signal processor  1101  (which in turn is received via baseband processor  1100 ) and fractional part from the SDM  1125 . The SDM  1125  is driven by a signal from the amplitude and phase signal processor  1101  based upon the desired channel and desired phase modulation, which is received from data scaler  1120 , differentiator  1123 , modulation compensation (equalization) filter  1121 , and overall modulation response filter  1122 . 
     It should also be noted that, in addition to or in place of the buffer  1132 , a delay element may be connected to the new count input of the divider  1128  to delay transmission of the count signal from a count source in a manner similar to the embodiment described above (see, e.g.,  FIG. 2 . Alternatively, a delay element may be connected to the carryout output of the divider  1128  to delay receipt of the carryout signal to a count source in a manner similar to the embodiments discussed above (see, e.g.  FIG. 3 .) 
     Embodiments may utilize both analog and digital components, where desired, insofar as these embodiments manipulate waves and signals requiring both. For example, cell phone embodiments may utilize both analog and digital components. Various types of technologies may also be utilized for constructing various embodiments. For example, embodiments or various components may be provided on a semiconductor device where desired, such as an integrated circuit or an application-specific integrated circuit composition; some examples include silicon (Si), silicon germanium (SiGe) or gallium arsenide (GaAs) substrates. 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.