Abstract:
A printhead temperature monitoring system includes a processor having a top priority interrupt input, a normal priority interrupt input, and at least one input for receiving temperature related signals. The processor is programmed or otherwise operable to calculate a printhead temperature based at least in part upon temperature related signals read on the input. A single timer circuit provides interrupt signals to the interrupt inputs of the processor. An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor.

Description:
TECHNICAL FIELD 
     The present invention relates generally to temperature control arrangements for printheads and, more particularly, to a temperature monitoring system and method which switches a timer between multiple interrupts of a processor. 
     BACKGROUND OF THE INVENTION 
     Thermal ink jet printer mechanisms which utilize printheads having heater resistors for effecting the ejection of small ink droplets from the printhead are well known. The ejection of a large number of small ink droplets at controlled locations on a printing medium produces a desired printed image. In such printheads it is desirable to control the overall temperature of the printhead in order to assure that ink droplets are delivered as desired. In order to control the printhead temperature it is of course necessary to measure or monitor the printhead temperature in some manner. 
     One manner of monitoring printhead temperature involves the use of one or more detectors located on the printhead. Various circuit arrangements and techniques incorporating various types of detectors can be utilized to produce temperature related signals from which the actual temperature of the printhead can be estimated or determined. One problem encountered in such arrangements is a need to read temperature related signals at specific times or intervals, even while a temperature calculation operation is taking place. 
     Accordingly, it would be advantageous to provide a temperature monitoring system and method which facilitates appropriate reading of temperature related signals without undue complexity or component cost. 
     SUMMARY OF THE INVENTION 
     In one aspect of the invention, a printhead temperature monitoring system includes a processor having a top priority interrupt input, a normal priority interrupt input, and at least one input for receiving temperature related signals. The processor is programmed or otherwise operable to calculate a printhead temperature based at least in part upon temperature related signals read on the input. A single timer circuit provides interrupt signals to the interrupt inputs of the processor. An interrupt control circuit is connected between the single timer circuit and the processor for selectively controlling application of timer circuit interrupt signals to the top priority interrupt of the processor and the normal priority interrupt of the processor. 
     In the foregoing arrangement, the interrupt control circuit may be used to deliver read triggering interrupt signals from the timer circuit to the top priority interrupt of the processor causing the processor to read a temperature related signal from the input, and to deliver temperature calculate triggering interrupt signals to the normal priority interrupt of the processor causing the processor to initiate a temperature calculation operation in a normal priority mode. During the temperature calculation operation of the processor, the processor is operable in response to a read triggering interrupt signal delivered to the top priority interrupt input to temporarily interrupt the temperature calculating operation in order to read another temperature related signal. In this manner the system assures that temperature related signals are read when necessary, but at the same time permits temperature calculating operations, which are not as time dependent as the temperature related signals themselves, to take place in a normal priority mode to reduce interference with other processor functions taking place during operation of a printer. Where a setup triggering interrupt signal is delivered to the top priority interrupt of the processor during a temperature calculating operation, the processor responsively temporarily interrupts the temperature calculating operation to perform a setup function such as clearing a counter. 
     In a preferred embodiment of the foregoing arrangement at least one temperature sensitive resistor is provided on a printhead and a capacitor is operatively connected to be charged through the temperature sensitive resistor. A voltage level detection circuit monitors a voltage level across the capacitor as it is charged and a counter associated with the voltage level detection circuit maintains a running count as the capacitor is charged until the voltage level across the capacitor reaches a threshold level. The count value in the counter is the temperature related signal. The top priority interrupt of the processor is an FIQ interrupt and the normal priority interrupt of the processor is an IRQ interrupt. 
     In another aspect of the present invention, in a printhead temperature monitoring method a step (a) involves establishing a signal which relates to a temperature of a printhead. After step (a), a step (b) involves applying an interrupt signal to a top priority interrupt of a processor which causes the processor to read the established temperature related signal. Subsequent to step (b), a step (c) involves applying an interrupt signal to a normal priority interrupt of the processor which causes the processor to initiate a temperature calculating operation. Subsequent to step (c), a step (d) involves (i) establishing a signal which relates to a temperature of a printhead, and (ii) subsequent to step (d)(i), applying an interrupt signal to a top priority interrupt of the processor which causes the processor to read the established temperature related signal of step (d)(i). During step (d)(ii) the processor temporarily interrupts the temperature calculating operation initiated in step (c) in order to read the temperature related signal of step (d)(i). Again, the subject method assures that temperature related signals are read when necessary, but at the same time permits temperature calculating operations, which are not as time dependent as the temperature related signals themselves, to take place in a normal priority mode to reduce interference with other processor functions taking place during operation of a printer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic representation of a printer system according to one embodiment of the present invention; 
     FIG. 2 is a more detailed schematic illustration of certain portions of the system of FIG. 1; 
     FIG. 3 is a schematic illustration of one embodiment of a timer interrupt control arrangement useful in the system of FIG. 1; 
     FIG. 4 is a flow chart of system operation; 
     FIG. 5 is a flowchart of system operation; and 
     FIG. 6 is a timing diagram corresponding to the system of FIGS. 1-3 and the operations of FIGS.  4  and  5 . 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a schematic diagram of a printhead temperature control system  10  including a printhead temperature monitoring arrangement is shown. Printheads  12  include respective temperature sensitive resistors  14  (TSRs) positioned thereon. One or more calibration resistors  16  are also provided. A resistance value of TSR  14  varies as its respective printhead temperature varies. The calibration resistors  16  provide a stable known resistance value which remains substantially the same regardless of changes in temperature within the printer and are used as a control element in the system as will be described in greater detail below. The TSRs  14  and the calibration resistors  16  are connected in parallel with each other between an analog ASIC  18  and a multiplexer  20 . An output of the multiplexer  20  is connected to a capacitor  22 . The analog ASIC  18  provides a source of charging energy  19  which can be delivered to the capacitor  22  in a selective manner through any one of the resistors  14  and  16 . Thus, by controlling the input-output path of the multiplexer  20 , the charging path of the capacitor  22  can be selected to pass through any one of the resistors  14  and  16 . The charge rate of the capacitor  22  will vary in accordance with the resistance of the selected charge path. Accordingly, the charge rate of the capacitor  22  can be monitored to provide an indicator of the resistance value of the selected charge path. 
     In this regard, the analog ASIC  18  includes a voltage level detection circuit  24  which is connected to monitor the voltage across the capacitor  22 . A count or clock signal generating circuit  26  operates in conjunction with the detection circuit  24  to begin outputting a clock signal when a particular charging operation of the capacitor  22  is initiated and to cease outputting the clock signal when the voltage level across the capacitor reaches a threshold level. A digital ASIC  28  includes a counter  30  which is connected to receive the clock signal produced by circuit  26  and maintains a running count of the clock pulses produced during a charging operation of the capacitor  22 . The clock signal frequency produced is constant and therefore the total count attained by the counter  30  during a charging operation is indicative of the charge rate of the capacitor  22 . The count attained by the counter  30  is therefore indicative of the resistance of the selected charge path, and in the case of a TSR inclusive charge path the count attained by the counter  30  is indicative of the temperature of the printhead. While a single counter is depicted it is recognized that multiple counters may be provided, one for each selectable charge path of the capacitor  22 . 
     A more detailed schematic of the source of charging energy  19  and the voltage level detection circuit  24  are shown in FIG.  2 . In operation, circuit  19  sets the charge voltage. Prior to each charging operation through a selected register  14  or  16 , the multiplexer  20  is controlled to connect capacitor  22  through resistor Rg on channel  8  to ground in order to discharge the capacitor  22 . The output of the voltage level detection circuit  24  controls the clock generator  26 . In particular, when the voltage across capacitor  22  is less than reference voltage V R , circuit  26  outputs a clock signal. When the voltage across capacitor  22  exceeds reference voltage V R , circuit  26  stops outputting its clock signal. The output of circuit  26  is provided to the counter  30  as shown in FIG.  1 . It is recognized that other voltage level detection circuits could be provided, such as a dual voltage comparator circuit which would provide a clock start output when the voltage across capacitor  22  exceeds a first reference voltage and which provides a clock stop output when the voltage across capacitor  22  exceeds a second, higher reference voltage. The charging path on channel  7  of the multiplexer can be selected to provide a count indicative of the internal resistance of the multiplexer  20 . 
     Referring again to FIG. 1, the digital ASIC  28  includes a control circuit  32  which includes a processor  34  such as a microprocessor or microcontroller and also includes a printhead driver for controlling the energization of heater resistors within the printhead  12 . The heater resistors are energized to eject ink droplets and are also energized to provide temperature control of the printhead  12 . The digital ASIC is also connected for controlling the multiplexer  20 . Referring now to FIG. 3, an exemplary processor arrangement is depicted with processor  34  including a fast speed or top priority interrupt input (“Fast IRQ” or “FIQ”) and a lesser speed or normal priority interrupt input (“IRQ”). An exemplary processor of this type is the ARM 7 TDMI processor which includes banked FIQ registers for storing count values. When the processor  34  receives an FIQ interrupt the processor  34  interrupts all other operations to perform a function which is initiated by the FIQ interrupt. That is, the processor  34  interrupts operations being performed in the user mode (but not the FIQ mode) of the processor and also interrupts operations being performed in the normal priority mode or IRQ mode of the processor. When the processor  34  receives an IRQ interrupt the processor  34  interrupts operations being performed in the user mode and all operations being performed in the IRQ mode are performed in a prioritized manner. A single timer  38  is provided for producing interrupt signals for the processor  34 . An interrupt controller  40  is also provided for switching delivery of the timer interrupt signals between the FIQ interrupt of the processor  34  and the IRQ interrupt of the processor  34 . 
     Exemplary operation of the system illustrated in FIGS. 1-3 is described relative to the flowcharts provided in FIGS. 4 and 5 and the timing diagram provided in FIG.  6 . In particular, referring to flowchart  50 A of FIG. 4, when a temperature monitoring operation starts at step  52  the timer is enabled on the FIQ. Such enablement includes configuring interrupt controller  40  to deliver signals to the FIQ interrupt, configuring the processor  34  to be responsive to an FIQ interrupt and starting the timer  38 . A wait for interrupt step  56  is also shown. 
     When an interrupt signal is received at the FIQ interrupt of the processor  34  as indicated at step  58 , a determination is made at step  60  as to whether the processor is awaiting a “Setup FIQ” interrupt. The particular FIQ interrupt mode of the processor  34  is stored as a bit in memory accessible by the processor  34 , and at step  60  the processor reads that stored bit. If the processor is awaiting a “Setup FIQ” interrupt then the YES path is followed and at step  62  the counter  30  is cleared to prepare for the next charging operation. At step  64  the stored FIQ mode bit is flipped to indicate that the processor is now awaiting a Read FIQ interrupt and at step  66  the timer is enabled to provide the next interrupt signal at a specific time. Simultaneously, a charging operation of the capacitor  22  is initiated through a selected resistor. When the timer  38  outputs the next FIQ interrupt at step  58 , the NO path from step  60  will be followed due to the bit flip which took place in step  64 , and at step  68  the count value attained by the counter  30  is read. At step  70  a determination is made as to whether all charge paths have been selected. If not, the NO path is followed and at step  72  the FIQ mode bit is flipped to indicate that the processor  34  is awaiting a “Setup FIQ” interrupt and the timer is again enabled at step  66 . This sequence of steps is followed until a determination is made at step  70  that all necessary charge paths have been selected, meaning the temperature calculation operation can be initiated. 
     Once the system is ready for a temperature calculation operation the YES path from step  70  is followed and the interrupt controller  40  is reconfigured to deliver interrupt signals to the IRQ interrupt of the processor  34 . The timer is enabled at step  66  to produce the next interrupt signal. The next interrupt signal is an IRQ interrupt as depicted in flowchart  50 B at step  76 . The interrupt controller  40  is then reconfigured at step  78  to deliver subsequent interrupt signals to the FIQ interrupt and the timer is enabled at step  80  so that the next counter value can be read at the appropriate time. Steps  78  and  80  are important in that the processor  34  is configured to permit counter values to be read per an FIQ interrupt even as the processor  34  performs a temperature calculation in the IRQ mode. Step  82  identifies the calculation of temperature operation and step  84  indicates a closed loop temperature control operation performed to adjust the temperature of the printheads  12 . 
     Referring to FIG. 6, an exemplary timing diagram  90  of system steps is provided showing expiration times  92  of the timer  38 , voltage level  94  of the capacitor  22 , and durations of the FIQ and IRQ operations initiated by the interrupt signals as indicated at lower portion  96 . The charging operation for the calibration resistors are identified as CR 1  and CR 2  in the capacitor voltage portion  94  of the diagram  90 . Four TSRs  14  are provided and the chargin operation for each is identified as TSR 1 , TSR 2 , TSR 3  and TSR 4  in the diagram. The occurrence and duration of the Setup FIQs (SFIQ) and the Read FIQs (RFIQ) is shown in portion  96 . After a charging operation has been performed for both of the calibration resistors CR 1  and CR 2  and each of the TSRs  14 , the IRQ interrupt occurs at  98  to initiate the temperature calculating operation of the processor  34 . Notably, the IRQ operation overlaps the next Setup FIQ interrupt  100 . At the next Setup FIQ interrupt  100 , the processor  34  temporarily interrupts the IRQ mode temperature calculation in order to perform one or more setup functions such as clearing the counter  30  and delivering a control signal to the multiplexer  20  in order to select the next desired charge path. Likewise, the IRQ operation could also overlap with a next Read FIQ interrupt which will cause the processor  34  to momentarily interrupt the IRQ mode temperature calculation in order to read another count value from the counter  30 . 
     Thus, the system permits excellent timing control of charge path selection and charge operation initiation and also enables temperature related signals to be read quickly by the processor  34  at specific times and at fast speeds which avoid interference with other process or operations. As used herein, the terminology “temperature related signal” is intended to encompass any signal read by the processor  34  and used by the processor  34  in calculating temperature. The terminology “temperature calculation” and “temperature calculating operation” is intended to include all calculations performed based upon one or more temperature related signals, including calculations to determine the resistences of the TSRs, as the resistance determination may merely be a first step towards calculating the final temperature. 
     Although the invention has been described above in detail referencing the preferred embodiments thereof, it is recognized that various changes and modifications could be made without departing from the spirit and scope of the invention.