Abstract:
Provided are a memory system and a method of driving the same. The method includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode.

Description:
PRIORITY CLAIM 
       [0001]    A claim of priority is made to Korean Patent Application No. 10-2007-0106258, filed on Oct. 22, 2007, in the Korean Intellectual Property Office, the subject matter of which is hereby incorporated by reference 
       SUMMARY 
       [0002]    The present invention relates to flash memories, and more particularly, to a memory system, including control sequencers, and a method of driving the same. 
         [0003]    In order to enhance performance, a memory controller may be designed with hard-wired logic to control instruction sequences of a flash memory. However, a hard-wired logic memory controller is complex in design, has limited extendibility, and has difficulty efficiently controlling multiple flash memories. 
         [0004]    In order to enhance extendibility, a memory controller may be designed in firmware to control the instruction sequences of a flash memory. This method is relatively simple in design, but lower in performance. 
         [0005]    Embodiments of the present invention provide a memory system including multiple memory devices and a host connected to the memory devices. Each of the memory devices includes a channel control sequencer. The host includes a top control sequencer that controls the channel control sequencer of each of the memory devices. 
         [0006]    The top control sequencer and the channel control sequencers may store microcodes, decode the microcodes, and execute the decoded microcodes, respectively. 
         [0007]    The host may further include a processor and a direct memory access (DMA). The processor generates the microcodes, and controls the top control sequencer and the memory devices using the microcodes. The DMA transfers the microcodes to the top control sequencer and the channel control sequencer of each of the memory devices. 
         [0008]    Each of the memory devices may further include a memory, an interface block interfacing with the memory, and a DMA. The DMA transfers data of the memory to the host under control of the corresponding channel control sequencer. 
         [0009]    The microcodes may include instructions for controlling the memories of the memory devices. Also, each of the memories may include a OneNAND™ flash memory. 
         [0010]    Each of the memory devices may further include an error correction code (ECC) block for correcting an error in the data. Each of the memories may include a NAND flash memory. 
         [0011]    In other embodiments of the present invention, a method of driving a memory system includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode. 
         [0012]    Setting the microcode in each of the top control sequencer and the channel control sequencers may include generating the microcodes; transferring the generated microcodes to the top control sequencer and the channel control sequencers, respectively; setting a top-level sequencer control register of the top control sequencer; and inputting a start address of the microcode to a current address of the top-level sequencer control register. 
         [0013]    Executing the microcode set in the top control sequencer may include executing the microcode recorded at the current address of the top-level sequencer control register. An interrupt is generated in the top control sequencer when the current address of the top-level sequencer control register is equal to an end address of the microcode. The current address is increased when the current address of the top-level sequencer control register is not equal to the end address of the microcode. 
         [0014]    Checking the execution results of the microcode may include, when an error occurs in the top control sequencer, reporting the error and identifying a status register of the top control sequencer. 
         [0015]    Executing the microcode recorded at the current address of the top-level sequencer control register may include setting a microcode in each of the channel control sequencers, and executing the microcode set in each of the channel control sequencers. Executing the microcode set in each of the channel control sequencers may include checking the execution results of the microcode. 
         [0016]    Setting the microcode in each of the channel control sequencers may include setting a sequencer control register of each of the channel control sequencers, and inputting the start address of the microcode to a current address of the channel sequencer control register. 
         [0017]    Executing the microcode set in each of the channel control sequencers may include executing the microcode recorded at the current address of the channel sequencer control register. An interrupt is generated in the channel control sequencer when the current address of the channel sequencer control register is an end address of the microcode. The current address of the channel sequencer control register is increased when the current address of the channel sequencer control register is not the end address of the microcode. 
         [0018]    Checking the execution results of the microcode may include, when an error occurs in any one of the channel control sequencers, reporting the error and identifying a status register of each of the channel control sequencers. 
         [0019]    The various embodiments of the present invention reduce the load of a host processor in a memory system, including OneNAND™ and/or NAND flash memories, for example. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The embodiments of the present invention will be described with reference to the attached drawings, wherein like reference numerals refer to like parts unless otherwise specified, and in which: 
           [0021]      FIG. 1  is a block diagram of a memory system, according to an embodiment of the present invention; 
           [0022]      FIG. 2  is a diagram illustrating microcodes, according to an embodiment of the present invention; 
           [0023]      FIG. 3  is a diagram illustrating a sequencer control register in a control sequencer illustrated in  FIG. 1 , according to an embodiment of the present invention; 
           [0024]      FIG. 4  is a flow diagram illustrating operation of a top control sequencer illustrated in  FIG. 1 , according to an embodiment of the present invention; 
           [0025]      FIG. 5  is a flow diagram illustrating operation of a channel control sequencer during operation of the top control sequencer illustrated in  FIG. 4 , according to an embodiment of the present invention; and 
           [0026]      FIG. 6  is a block diagram of a memory system, according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0027]    The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Rather, these embodiments are provided as examples, to convey the concept of the invention to one skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments of the present invention. Throughout the drawings and written description, like reference numerals will be used to refer to like or similar elements. 
         [0028]    In order to facilitate extendibility of a memory controller and simultaneously maintain high performance, embodiments of the present invention fix, in an initial design stage, a limited number of specific operation scenarios that are expected to be frequently performed in a flash memory system. These specific operation scenarios are provided in hard-wired logic in the memory controller. Other operation scenarios control a flash memory through firmware. Thus, embodiments of the present invention can rapidly cope with changes in the flash memory system specifications (e.g., interleaving degree and read/write unit operation size) and/or the flash memory device specifications (e.g., page size and block size). 
         [0029]    Therefore, embodiments of the present invention provide high performance with respect to anticipated operations and functionality considered in design stages, and also provide extendibility for operations and functionality not fully considered in the design stages. 
         [0030]      FIG. 1  is a block diagram of a memory system, according to an illustrative embodiment of the invention. 
         [0031]    Referring to  FIG. 1 , a memory system  100  according to an embodiment of the present invention includes a host processor  10 , a top control sequencer  20 , a first memory device  30 , a second memory device  40 , a direct memory access (DMA)  50 , and a system bus  60 . 
         [0032]    The first memory device  30  may include a first flash memory  31  (e.g., first OneNAND™ flash memory), a channel-A (Ch. A) control sequencer  32 , a first interface  33 , and a first device DMA  34 . The second memory device  40  may include a second flash memory  41  (e.g., second OneNAND™ flash memory), a channel-B (Ch. B) control sequencer  42 , a second interface  43 , and a second device DMA  44 . 
         [0033]    The host processor  10  is configured to generate microcodes (μ-codes). The microcodes are instructions that control memories included in the first and second memory devices  30  and  40 , respectively, of the memory system  100 . The microcodes will be described in detail with reference to  FIG. 2 . 
         [0034]    The DMA  50  transfers the microcodes, which have been generated by the host processor  10 , through the system bus  60  to the top control sequencer  20  and to the Ch. A and Ch. B control sequencers  32  and  42  of the first and second memory devices  30  and  40 . The microcodes transferred by the DMA  50  are stored in sequencer internal memories (not shown) of the Ch. A and Ch. B control sequencers  32  and  42 , respectively. The microcodes stored in the sequencer internal memories are fetched and executed by the Ch. A and Ch. B control sequencers  32  and  42 . 
         [0035]    Alternatively, the microcodes may be generated by a user. When the microcodes are generated by the user, the generated microcodes may be previously stored in the top control sequencer  20  and the channel control sequencers  32  and  42 . 
         [0036]    Sequencer control registers (not shown) in each of the Ch. A and Ch. B control sequencers  32  and  42  and the top control sequencer  20  will be described in detail with reference to  FIG. 3 . 
         [0037]    The Ch. A control sequencer  32  of the first memory device  30  executes the microcode transferred by the DMA  50 . In response to the executed microcode of the Ch. A control sequencer  32 , the first device DMA  34  transfers data of the first flash memory  31  through the first interface  33  to the host processor  10  via the system bus  60 . Operation of the Ch. B control sequencer  42  of the second memory device  40  is similar to the operation of the Ch. A control sequencer  32  of the first memory device  30 . That is, the Ch. B control sequencer  42  executes the microcode transferred by the DMA  50 . In response to the executed microcode, the second device DMA  44  transfers data of the second flash memory  41  through the second interface  43  to the host processor  10  via the system bus  60 . 
         [0038]    As described above, the memory system according to the present embodiment uses the microcodes to control the memory devices equipped therein, thus making it possible to reduce the load of the host processor in the memory system. Also, when the specifications of the memory device are changed, the memory system can control the memory device with the changed specifications by modifying the microcode. 
         [0039]      FIG. 2  is a diagram illustrating a microcode, stored for example in internal memory of the Ch. A control sequencer  32 , according to an illustrative embodiment of the invention. 
         [0040]    Referring to  FIGS. 1 and 2 , a microcode according to the depicted embodiment may be configured to include 128 bits, for example. More particularly, the microcode includes a combination of a first microcode Code # 1 , a second microcode Code # 2 , a third microcode Code # 3 , and a fourth microcode Code # 4 . 
         [0041]    In the example depicted in  FIG. 2 , the 0 th  through 7 th  bits of the first microcode Code # 1  contain interrupt information about multiple memories in the first flash memory  31 . The 8 th  bit of the first microcode Code # 1  represents operation done information of the first device DMA  34 . The 24 th  and 25 th  bits of the first microcode Code # 1  represent access size information of the system bus  60 . The 28 th  bit of the first microcode Code # 1  represents a wait-for-event operation, the 29 th  bit of the first microcode Code # 1  represents a read &amp; verify operation, the 30 th  bit of the first microcode Code # 1  represents a write operation, and the 31 st  bit of the first microcode Code # 1  represents a read operation. 
         [0042]    Also, in the depicted example, the second microcode Code # 2  contains address information of the system bus, the third microcode Code # 3  contains write data or read &amp; verify data, and the fourth microcode Code # 4  contains read &amp; verify mask data. 
         [0043]    The Ch. A and Ch. B control sequencers  32  and  42  use the microcodes to control read operations, write operations, read &amp; verify operations, and wait-for-event operations with respect to the first and second flash memories  31  and  41  of the first and second memory devices  30  and  40 , respectively. 
         [0044]      FIG. 3  is a diagram illustrating a sequencer control register in the Ch. A control sequencer  32  illustrated in  FIG. 1 , according to an illustrative embodiment of the invention. 
         [0045]    Referring to  FIGS. 1 and 3 , the sequencer control register in the Ch. A control sequencer  32  according to the depicted embodiment includes a start address register, an end address register, a command register, and a status register, indicated in the left-most column. The start address register stores a sequencer start address. The end address register stores a sequencer end address. The command register stores a sequencer done clear SDC, sequencer error clear SEC, and sequencer run SR indicators or commands. The status register stores sequencer done SD, sequencer busy SB, sequencer error SE, and sequencer current address offset SCAO indicators or commands. 
         [0046]    The sequencer internal memory according to the present embodiment may include a dual-port static random access memory (SRAM), for example. 
         [0047]    The sequencer control registers of the top control sequencer  20  and the Ch. B control sequencer  42  are configured in substantially the same manner as the sequencer control register of the Ch. A control sequencer  32 , shown in  FIG. 3 . Accordingly, additional description of these sequencer control registers will not be repeated for conciseness. 
         [0048]      FIG. 4  is a flow diagram illustrating operation of the top control sequencer  20  of  FIG. 1 , according to an illustrative embodiment of the invention.  FIG. 5  is a flow diagram illustrating operation of the Ch. A control sequencer  32  during the operation of the top control sequencer  20  illustrated in  FIG. 4 , according to an illustrative embodiment of the invention. 
         [0049]    Referring to  FIGS. 1 through 5 , a method of driving the memory system  100 , according to an illustrative embodiment of the invention is as follows. 
         [0050]    In step  441  of  FIG. 4 , the host processor  10  generates microcodes. In step  442 , the DMA  50  transfers the generated microcodes to the top control sequencer  20  and the Ch. A and Ch. B control sequencers  32  and  42 . 
         [0051]    In step  443 , the top control sequencer  20  sets a top-level sequencer control register. That is, the top control sequencer  20  sets the microcode received from the DMA  50  in a start address register, an end address register, a command register, and a status register of the top-level sequencer control register. In step  444 , the top control sequencer  20  inputs a start address of the microcode to a current address of the top-level sequencer control register. 
         [0052]    In step  445 , the top control sequencer  20  performs a process for executing the microcode recorded at the current address of the top-level sequencer control register. That is, the top control sequencer  20  uses the microcode to control the Ch. A and Ch. B control sequencers  32  and  42 . Each of the first and second memory devices  30  and  40  occupies the system bus  60  under the control of the top control sequencer  20 . 
         [0053]    The process indicated by step  445  is set forth in detail in  FIG. 5 . Notably,  FIG. 5  is directed to operations of the Ch. A control sequencer  32 , for purposes of explanation. The Ch. A and Ch. B control sequencers  32  and  42  operate independently in the respective memory devices. However, it is understood that operations of the Ch. B control sequencer  42  are similar to the operations of the Ch. A control sequencer  32 , and thus a detailed description only of the Ch. A control sequencer  32  operations will be provided for conciseness. 
         [0054]    In step  451  of  FIG. 5 , the Ch. A control sequencer  32  sets the microcode received from the DMA  50  in a start address register, an end address register, a command register, and a status register of a Ch. A sequencer control register. In step  452 , the Ch. A control sequencer  32  inputs a start address of the microcode to a current address of the Ch. A sequencer control register. In step  453 , the Ch. A control sequencer  32  executes the microcode recorded at the current address of the Ch. A sequencer control register. 
         [0055]    In step  454 , the Ch. A control sequencer  32  determines whether the current address of the Ch. A sequencer control register is the end address of the microcode. When the current address of the Ch. A sequencer control register is the end address of the microcode, the Ch. A control sequencer  32  generates an interrupt signal in step  456 . On the other hand, when the current address of the Ch. A sequencer control register is not the end address of the microcode, the Ch. A control sequencer  32  increases the current address of the Ch. A sequencer control register in step  455  and returns to step  453 . 
         [0056]    If an error occurs in any one of Ch. A control sequencers, the Ch. A control sequencer  32  reports the error and identifies the status registers of the channel control sequencers, in step  457 . 
         [0057]    The Ch. A and Ch. B control sequencers  32  and  42  operate in parallel. Upon completion of the operations of the Ch. A and Ch. B control sequencers  32  and  42 , the process returns to  FIG. 4 . It is determined at step  446  whether the current address of the top-level sequencer control register is the end address of the microcode. When the current address of the top-level sequencer control register is the end address of the microcode, the top control sequencer  20  generates an interrupt signal in step  448 . On the other hand, when the current address of the top-level sequencer control register is not the end address of the microcode, the top control sequencer  20  increases the current address of the top-level sequencer control register in step  447  and returns to step  445 . 
         [0058]    If an error occurs, the top control sequencer  20  reports the error and identifies the status register of the top control sequencer, in step  449 . 
         [0059]      FIG. 6  is a block diagram of a memory system, according to another illustrative embodiment of the present invention. 
         [0060]    Referring to  FIG. 6 , a memory system  200  includes a host processor  110 , a top control sequencer  120 , first through fourth memory devices  130  through  160 , a DMA  170 , and a system bus  180 . 
         [0061]    The first memory device  130  includes a first NAND flash memory  131 , a Ch. A control sequencer  132 , a first interface  133 , a first device DMA  134 , and a first error correction (ECC) block  135 . The second memory device  140  includes a second NAND flash memory  141 , a Ch. B control sequencer  142 , a second interface  143 , a second device DMA  144 , and a second ECC block  145 . The third memory device  150  includes a third NAND flash memory  151 , a Ch. C control sequencer  152 , a third interface  153 , a third device DMA  154 , and a third ECC block  155 . The fourth memory device  160  includes a fourth NAND flash memory  161 , a Ch. D control sequencer  162 , a fourth interface  163 , a fourth device DMA  164 , and a fourth ECC block  165 . 
         [0062]    Microcodes generated by the host processor  110  control memories included in the first through fourth memory devices  130  through  160  equipped in the memory system  200 . The DMA  170  transfers the microcodes, which have been generated by the host processor  110 , through the system bus  180  to the top control sequencer  120  and the Ch. A through Ch. D control sequencers  132 ,  142 ,  152  and  162  of the first through fourth memory devices  130 ,  140 ,  150  and  160 , respectively. The microcodes transferred by the DMA  170  are stored in sequencer internal memories (not shown) of the Ch. A through Ch. D control sequencers  132 ,  142 ,  152  and  162 . 
         [0063]    The Ch. A control sequencer  132  of the first memory device  130  executes the microcode transferred by the DMA  170 . In response to the executed microcode of the Ch. A control sequencer  132 , the first device DMA  134  corrects an error in data of the first NAND flash memory  131  by the first ECC block  135  and transfers the resulting data through the first interface  133  to the host processor  110 . 
         [0064]    Operations of the respective control sequencers of the second through fourth memory devices  140 ,  150  and  160  are similar to the operation of the Ch. A control sequencer  132  of the first memory device  130 . Therefore, detailed descriptions will not be repeated for conciseness. 
         [0065]    As described above, the memory system, according to embodiments of the present invention, uses microcodes to control memory devices equipped therein, thus making it possible to reduce the load of a host processor in the memory system. Also, when specifications of the memory device are changed, the memory system can control the memory device with the changed specifications by modifying the microcodes. It is thus possible, for example, to reduce the load of the host processor in the memory system. 
         [0066]    While the present invention has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.