Abstract:
An apparatus and method is disclosed for providing control of current consumption of a power amplifier. The power amplifier comprises an output stage for amplifying a RF signal, and the output stage is operably coupled to an output load. The power amplifier further comprises a bias circuit operably coupled to the output stage, wherein the bias circuit is capable of applying a bias voltage to the output stage. The power amplifier still further comprises a limit circuit operably coupled to the bias circuit for detecting an increase in the current of the output stage under an output load mismatch and in response, decreasing the bias voltage applied to the output stage.

Description:
TECHNICAL FIELD OF THE INVENTION 
   The present invention relates generally to radio frequency (RF) power amplifiers and more specifically, to a current limiting circuit for controlling current consumption of a RF power amplifier. 
   BACKGROUND OF THE INVENTION 
   Radio frequency (RF) power amplifiers are often used in portable battery operated wireless devices, such as cellular telephones. Extending the battery life is a key concern for users and manufacturers of these battery operated wireless devices. One of the key factors in determining the battery life of the battery operated wireless device is the power consumption of the RF power amplifiers. The RF power amplifiers are designed to operate into an optimal load impedance and are typically coupled to an antenna of the battery operated wireless device. 
   However, under an antenna mismatch condition, such as for example, when the antenna of the battery operated wireless device approaches objects (e.g. metal structures, human contact, or the like), the load impedance of the RF power amplifier changes and the RF power amplifier draws excess current. In some cases, the current can exceed more than two times the current drawn under an optimal load impedance. When the RF power amplifier draws excess current, the battery life of the battery operated wireless device is reduced. In addition, the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) linearity and distortion limits are often exceeded when the RF power amplifier draws excess current. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed to be characteristic of embodiments of the invention are set forth in the appended claims. However, embodiments of the invention will best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings, wherein embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. 
       FIG. 1  illustrates a high-level block diagram of a wireless device according to an exemplary embodiment of the present invention; 
       FIG. 2  illustrates a schematic diagram of a current mirror bias circuit according to one embodiment of the present invention; 
       FIG. 3  illustrates a schematic diagram of a current limit circuit according to one embodiment of the present invention; and 
       FIG. 4  illustrates a schematic diagram of a current limit circuit according to another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Reference will now be made to the following detailed description of the exemplary embodiments of the present invention. Those skilled in the art will recognize that embodiments of the present invention provide many inventive concepts and novel features that are merely illustrative and not to be construed as restrictive. Accordingly, the specific embodiments discussed herein are given by way of example and do not limit the scope of the embodiments of the present invention. In addition, those skilled in the art will understand that for purposes of explanation, numerous specific details are set forth, though embodiments of the invention can be practiced without these specific details, and that certain features have been omitted so as to more clearly illustrate embodiments of the invention. 
     FIG. 1  illustrates a high-level block diagram of a wireless device  100  according to an exemplary embodiment of the present invention. In one embodiment, wireless device  100  comprises an antenna  102 , a duplexer  104 , a transmitter  106 , a receiver  108 , TX/RX circuitry  110 , a speaker/microphone  112 , a main processor  114 , a display/keypad  116 , a memory  118 , and a battery  120 . Wireless device  100  may be any wireless device, including, but not limited to, conventional cellular telephones, paging devices, personal digital assistant devices, text-messaging devices, portable computers, or any other like device capable of wireless communication. 
   As will be explained below in greater detail with respect to  FIGS. 2-4 , transmitter  106  comprises radio frequency (RF) power amplifier circuitry including bias circuitry, one or more RF power amplifier stages, and other like circuitry. In one embodiment of the present invention, the RF power amplifier circuitry of transmitter  106  is formed on a Gallium Arsenide (GaAs) substrate. However, other semiconductor materials (e.g., silicon, indium phosphide, gallium nitride) may be used. In addition, for purposes of illustration and ease of explanation, embodiments of the present invention are described in terms of bipolar junction transistor (BJT) technology (e.g., heterojunction bipolar transistors (HBTs)). However, embodiments of the invention are not limited to BJT technology. 
   TX/RX circuitry  110  receives from antenna  102  an incoming signal transmitted by for example, a communication system or a wireless network provider, through duplexer  104  and receiver  108 . TX/RX circuitry  110  processes and sends the incoming signal to the speaker (i.e., voice data) or to main processor  114  (e.g., web browsing) for further processing. Likewise TX/RX circuitry  110  receives analog or digital voice data from the microphone or other outgoing data (e.g., web data, e-mail) from main processor  114 . TX/RX circuitry  110  transmits an RF signal that is transmitted through transmitter  106  via antenna  102 . 
   Main processor  114  executes a basic operating system program stored in memory  118  in order to control the overall operation of wireless device  100 . For example, main processor  114  controls the reception of signals and the transmission of signals by TX/RX circuitry  110 , receiver  108 , and transmitter  106 . Main processor  114  is capable of executing other processes and programs resident in memory  118  and may move data into or out of memory  118 , as required by an executing process. 
   Main processor  114  is also coupled to display/keypad  116 . The user of wireless device  100  uses the keypad to enter data into wireless device  100 . The display may be a liquid crystal display capable of rendering text and/or at least various graphics; alternate embodiments may use other types of displays. Battery  120  is operably coupled with the electrical components of wireless device  100 , in accordance with known electrical principles. 
   Those skilled in the art will recognize that wireless device  100  is given by way of example and that for simplicity and clarity, only so much of the construction and operation of wireless device  100  as is necessary for an understanding of the present invention is shown and described. In addition, or as an alternative, although an exemplary wireless device  100  is shown and described, the present invention contemplates any suitable component or combination of components performing any suitable tasks in association with wireless device  100 , according to particular needs. Moreover, it is understood that wireless device  100  should not be construed to limit the types of devices in which embodiments of the present invention may be implemented. 
   In accordance with the principles of embodiments of the present invention, the RF power amplifier circuitry of transmitter  106  of wireless device  100  provides for detecting and limiting the current for an output load mismatch of the RF power amplifier, as described below in greater detail with respect to  FIGS. 2-4 . 
     FIG. 2  illustrates a schematic diagram of a current mirror bias circuit  200  according to one embodiment of the present invention. Current mirror bias circuit  200  comprises a source regulated voltage Vreg, bias circuit  202 , output stage  204 , and a battery voltage Vbatt. Bias Circuit  202  comprises a transistor Q 1 , resistors R 1  and R 2 , and diodes D 1  and D 2 . Output stage  204  comprises a transistor Q 2  and a resistor R 3 . For simplicity and clarity, only a single transistor Q 2  and a single resistor R 3  of output stage  204  are shown and described. Although output stage  204  is shown and described as having a single transistor Q 2  and a single resistor R 3 , any number of transistors or resistors may be used. 
   In one embodiment of the present invention, transmitter  106  of wireless device  100  of  FIG. 1  comprises RF power amplifier circuitry including current mirror bias circuit  200 . In addition or as an alternative, transistor Q 2  of output stage  204  is a final amplification stage of transmitter  106  and may experience an output load mismatch of antenna  102  of wireless device  100 . 
   In another embodiment of the present invention, transistor Q 1  is an emitter-follower transistor, wherein the voltage at the collector of transistor Q 1  is set with resistor R 2  and is the emitter-follower voltage Vef. In addition, the current through transistor Q 1  is the emitter-follower current Ief. In an alternative embodiment of the present invention, a capacitor (not shown) may be combined with resistor R 2  for decoupling transistor Q 1 . Although transistor Q 1  is shown and described as an emitter-follower transistor, the present invention contemplates any suitable transistor or combination of transistors performing the same or substantially similar function as the emitter-follower transistor. As will be explained below in greater detail with respect to  FIGS. 3 and 4 , the emitter-follower voltage Vef of transistor Q 1 , is capable of being used as a trigger voltage relative to the collector current Icc of the output stage  204  (i.e. transistor Q 2 ). 
   In still another embodiment of the present invention, transistor Q 1  of bias circuit  202  provides the base current for transistor Q 2  of output stage  204 . When transistor Q 2  of output stage  204  is biased, the collector current Icc of output stage  204  is approximately proportional to the current Ief of transistor Q 1 , via beta (Icc=Ief*beta). In addition, or as an alternative, by maintaining a tight tolerance on the source regulated voltage Vreg, such as for example within +/−100 mV, the emitter-follower voltage Vef (Vreg−[Ief*R 2 ]) is known for any collector current Icc of output stage  204 . 
     FIG. 3  illustrates a schematic diagram of a current limit circuit  300  according to one embodiment of the present invention. Current limit circuit  300  comprises source regulated voltage Vreg, bias circuit  202 , a limit circuit  302 , output stage  204 , and battery voltage Vbatt. As indicated above with respect to  FIG. 2 , bias circuit  202  comprises transistor Q 1 , resistors R 1  and R 2 , and diodes D 1  and D 2 . Also, as indicated above with respect to  FIG. 2 , output stage  204  comprises transistor Q 2  and resistor R 3 . Limit circuit  302  comprises transistors Q 3  and Q 4 , a plurality of resistors R 4 -R 8 , and a capacitor C 1 . 
   The emitter voltage of transistor Q 3 , voltage V 1 , may be set with resistors R 6  and R 7  of limit circuit  302 , which provide an adequate collector to emitter voltage of transistor Q 1  of bias circuit  202 . In addition, as discussed above, the relationship between the collector current Icc of transistor Q 2  of output stage  204  and the emitter-follower current Ief of bias circuit  202  is related by beta of transistor Q 1 . Therefore, the trigger voltage for limit circuit  302  is V 1 +VbeQ 3  and may be adjusted or set by resistors R 2 , R 6 , and R 7 . 
   In one embodiment of the present invention, transmitter  106  of wireless device  100  of  FIG. 1  comprises RF power amplifier circuitry including current limit circuit  300 . In addition or as an alternative, transistor Q 2  of output stage  204  is a final amplification stage of transmitter  106  of wireless device  100  and may experience an output load mismatch of antenna  102  of wireless device  100 . 
   To further explain the operation of current limit circuit  300 , an example is now given. In the following example, wireless device  100  experiences an antenna mismatch condition, such as, for example, when antenna  102  comes in close proximity with objects, for example, metal structures, human contact, or the like. Although a load mismatch of transistor Q 2  of output stage  204  is described as a mismatch generated from an antenna mismatch condition, the present invention contemplates any suitable mismatch condition. For example, a load mismatch condition may be any mismatch condition that causes the collector current Icc to increase in transistor Q 2  of output stage  204 , thereby increasing the power consumption and decreasing the battery life or exceeding the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) limits of wireless device  100 . In addition, or as an alternative, a load mismatch condition may be any mismatch to the optimal load impedance presented to transistor Q 2  of output stage  204  that causes the collector current Icc to increase in transistor Q 2  of output stage  204 , thereby increasing the power consumption and decreasing the battery life or exceeding the ACPR and EVM limits of wireless device  100 . 
   In another embodiment of the present invention, during a load mismatch condition of output stage  204 , the collector current Icc of transistor Q 2  increases, which in turn decreases the emitter-follower voltage Vef of transistor Q 1 . When the emitter-follower voltage Vef of transistor Q 1  decreases below a predetermined trigger voltage, limit circuit  302  detects the increase in the collector current Icc of transistor Q 2  and closes the loop back to the emitter base voltage Veb of transistor Q 1 . Transistor Q 4  of limit circuit  302  “pulls” current Ipull 1  through resistor R 1  of bias circuit  202 , thereby decreasing the emitter base voltage Veb of transistor Q 1 , which in turn limits the emitter-follower current Ief through resistor R 2 . 
   Since the emitter-follower current Ief is limited, the emitter-follower voltage Vef of transistor Q 1  is prevented from going more negative and is limited relative to the voltage V 1  of limit circuit  302 . As mentioned above, the emitter-follower current Ief through resistor R 2  of bias circuit  202  is equivalent to the base current for transistor Q 2  of output stage  204 . Therefore, limiting the emitter-follower current Ief also limits the base current of transistor Q 2  and effectively limits the collector current Icc of output stage  204 . Resistor R 4  and capacitor C 1  control the loop stability of limit circuit  302  and in particular transistor Q 3 . In addition, resistor R 8  may be used to control the gain of limit circuit  302 . 
     FIG. 4  illustrates a schematic diagram of a current limit circuit  400  according to another embodiment of the present invention. Current limit circuit  400  comprises source regulated voltage Vreg, bias circuit  202 , a bias circuit  402 , a limit circuit  406 , output stage  204 , a driver RF power amplifier stage  404 , and battery voltage Vbatt. As indicated above with respect to  FIG. 2 , bias circuit  202  comprises a transistor Q 1 , resistors R 1  and R 2 , and diodes D 1  and D 2 . Also, as indicated above with respect to  FIG. 2 , output RF power amplifier stage  204  comprises a transistor Q 2  and a resistor R 3 . Bias circuit  402  comprises a transistor Q 6 , resistors R 9  and R 10 , and diodes D 3  and D 4 . Bias circuit  402  operates substantially similar to bias circuit  202 , as described above with respect to  FIGS. 2 and 3 , except bias circuit  402  controls the bias of transistor Q 7  of driver RF power amplifier stage  404 . 
   Driver RF power amplifier stage  404  comprises a transistor Q 7  and a resistor R 12 . Although driver RF power amplifier stage  204  is shown and described as having a single transistor Q 7  and a single resistor R 12 , any number of transistors or resistors may be used. Limit circuit  406  comprises transistors Q 3 -Q 5 , a plurality of resistors R 4 -R 8  and R 11 , and a capacitor C 1 . 
   As discussed above, the emitter voltage of transistor Q 3 , voltage V 1 , may be set with resistors R 6  and R 7  of limit circuit  302 , which provides an adequate collector to the emitter voltage of transistor Q 1  of bias circuit  202 . In addition, as discussed above, the relationship between the collector current Icc of transistor Q 2  of output stage  204  and the emitter-follower current Ief of bias circuit  202  is related by beta of transistor Q 1 . Therefore, the trigger voltage for limit circuit  406  is V 1 +VbeQ 3  and in addition may be adjusted or set by resistors R 2 , R 6 , and R 7 . 
   In an embodiment of the present invention, transmitter  106  of wireless device  100  of  FIG. 1  comprises RF power amplifier circuitry including current limit circuit  400 . In addition or as an alternative, transistor Q 7  of driver RF power amplifier stage  404  is a driver amplification stage, and transistor Q 2  of output stage  204  is a final amplification stage of transmitter  106  of wireless device  100 . Output stage  204 , which is driven by driver RF power amplifier stage  404 , may experience an output load mismatch due to any change in the optimal load impedance associated with transmitter  106  of wireless device  100 . 
   As an example only and not by way of limitation, when wireless device  100  experiences a load mismatch condition, such as for example, due to a mismatch of the optimal load impedance presented to transistor Q 2  of output stage  204 , the collector current Icc of output stage  204  increases, and the emitter-follower voltages Vef and Vef 2  of transistors Q 1  and Q 6 , decrease respectively. When the emitter-follower voltage Vef of transistor Q 1  decreases below a predetermined trigger voltage, limit circuit  406  detects the increase in the collector current Icc of transistor Q 2  and closes the loop back to the emitter base voltages Veb and Veb 2  of transistors Q 1  and Q 6 , respectively. 
   Transistors Q 4  and Q 5  of limit circuit  406  “pulls” current through resistors R 1  and R 10  of bias circuits  202  and  402 , thereby decreasing the emitter base voltage Veb and Veb 2  of transistors Q 1  and Q 6 , which in turn limits the emitter-follower current Ief through resistor R 2  and the emitter-follower current Ief 2  through resistor R 9 , respectively. Since the emitter-follower current Ief and Ief 2  is limited, the emitter-follower voltage Vef and Vef 2  of transistors Q 1  and Q 6  are prevented from going more negative and are limited relative to the voltage V 1  of limit circuit  406 . 
   As mentioned above, the emitter-follower current Ief through resistor R 2  of bias circuit  202  is equivalent to the base current for transistor Q 2  of output stage  204 . Therefore, limiting the emitter-follower current Ief also limits the base current of transistor Q 2  and effectively limits the collector current Icc of output stage  204 . Likewise, the emitter-follower current Ief 2  through resistor R 9  of bias circuit  402  is equivalent to the base current for transistor Q 7  of driver RF power amplifier stage  404 . Therefore, limiting the emitter-follower current Ief 2  also limits the base current of transistor Q 7  and effectively limits the collector current Icc of driver RF power amplifier stage  404 . Resistor R 4  and capacitor C 1  control the loop stability of limit circuit  406  and in particular transistor Q 3 . In addition, resistors R 8  and R 11  may be used to control the gain of limit circuit  406 . 
   In another embodiment of the present invention, when current circuit  406  detects the increase in the collector current Icc of transistor Q 2 , transistor Q 5  of limit circuit  406  provides a first feedback path to output stage  204  and a second feedback path back to the preceding gain stage, to reduce the gain and drive of, for example, driver RF power amplifier stage  404 . In addition or as an alternative, the reduction of drive from driver RF power amplifier stage  404  provides for an additional level of control to limit the base current of transistor Q 2  and, therefore, the collector current Icc of output stage  204 . As a result, the power consumption is reduced, the battery life is increased, and the ACPR and EVM performance is maintained within the limits of wireless device  100 . 
   Reference in the foregoing specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. 
   While the exemplary embodiments of the present invention have been shown and described, it will be understood that various changes and modifications to the foregoing embodiments may become apparent to those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, the invention is not limited to the embodiments disclosed, but rather by the appended claims and their equivalents.