Abstract:
A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

Description:
TECHNICAL FIELD  
       [0001]     The present invention relates generally to FET and MOSFET transistors, and more particularly the invention relates to field effect transistors having channel regions extending vertically from a supporting substrate between horizontally disposed source and drain regions.  
       BACKGROUND ART  
       [0002]     Metal-oxide-semiconductor field effect transistor (MOSFET) technology is a dominant electronic device technology in use today. Performance enhancement between generations of devices is generally achieved by reducing an overall size of the device, resulting in an enhancement in device speed. This size reduction is generally referred to as device scaling. As MOSFETs are scaled to channel lengths below about 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade an ability of the gate to control whether the device is on or off. The degradation in control ability phenomenon is called a short-channel effect (SCE). Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (usually, but not limited to, silicon dioxide or sapphire) below an active region of the device, unlike conventional bulk MOSFETs, which are formed directly on silicon substrates, and hence have silicon below all active regions. SOI is generally considered advantageous as it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. Other techniques, such as separation by implantation of oxygen (SIMOX) functions similarly to SOI. The reduction in coupling in SOI and SIMOX is often achieved by ensuring that all the silicon in the MOSFET channel region can be either inverted or depleted by the gate (called a fully depleted MOSFET). As device size is scaled, however, ensuring a fully depleted channel region becomes increasingly difficult, since the distance between the source and drain is reduced. The reduced distance results in an increased interaction with the channel thus reducing gate control and increasing short channel effects.  
         [0003]     A double-gate MOSFET structure places a second gate in the device, such that there is a gate on either side of the channel. The double- gate allows gate control of the channel from both sides, reducing SCE. Additionally, when the device is turned on using both gates, two conduction (i.e., inversion) layers are formed, allowing for better channel control. An extension of the double-gate concept is a surround-gate or wraparound-gate concept, where the gate is placed such that it completely or almost-completely surrounds the channel, providing improved gate control. These surround-gate and wraparound-gate concepts are also formed on SOI or SIMOX and are referred to as FinFET devices due to the silicon-etched fin produced above the oxide/insulator level.  
         [0004]     Such a FinFET device is presented in U.S. Pat. No. 6,413,802, entitled “FinFET Transistor Structures Having a Double Gate Channel Extending Vertically from a Substrate and Methods of Manufacture,” issued to Hu et al.  FIG. 1  illustrates a FinFET transistor  100  in accordance with Hu et al. The FinFET transistor  100  is fabricated on an insulative layer  101  (e.g., SIMOX) and includes a silicon drain island  103  and a silicon source island  105  connected by a silicon fin or channel  107 . The drain island  10 , source island  105 , and channel  107  are each covered by a dielectric layer  109 , and a gate  111  extends across the channel  107  and is isolated from the channel  107  by a gate oxide (not shown explicitly) and the dielectric layer  109 . Inversion layers are formed on either side of the channel  107 . However, the FinFET transistor  100  still relies on photolithography for minimum feature sizes (e.g., a width of the channel  107  and the gate  111 ).  
         [0005]     There is a need in the integrated circuit art for obtaining increasingly smaller devices without sacrificing device performance. The small device size requires small device regions, precise and accurate alignment between regions, and minimization of parasitic resistances and capacitances. Device size can be reduced by putting more reliance on fine line lithography, but as discussed below, it becomes impractical or impossible to continue to reduce feature size and achieve the required greater increase in alignment accuracy. As lithography is pushed to a limit, yield and production throughput decrease.  
         [0006]     Four governing performance parameters of a photolithographic system are limit-of-resolution, L r , level-to-level alignment accuracy, depth-of-focus, and throughput. For purposes of this discussion, limit-of-resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.  
         [0007]     Typical photolithographic techniques are limited by physical constraints of a photolithographic system involving actinic radiation wavelength, λ, and geometrical configurations of projection system optics. According to Rayleigh&#39;s criterion,  
         L   r     =       0.61   ⁢   λ     NA         
 
 where NA is the numerical aperture of the optical system and is defined as NA =n sin α, where n is the index of refraction of a medium which the radiation traverses (usually air for this application, so n ≅1) and α is a half-angle of the divergence of the actinic radiation. For example, using deep ultraviolet illumination (DUV) with λ=193 nm, and NA =0.7, the lower limit of resolution is 168 nanometers (1680 Å). Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks. 
 
         [0008]     Along with the limit-of-resolution, the second parameter, level-to-level alignment accuracy becomes more critical as feature sizes on photomasks decrease and a number of total photomasks increases. For example, if photomask alignment by itself causes a reduction in device yield to 95% per layer, then 25 layers of photomask translates to a total device yield of 0.95 25  =0.28 or 28% yield (assuming independent errors). Therefore, a more complicated mask, such a phase-shifted mask is not only more expensive but device yield can suffer dramatically.  
         [0009]     Further, although the numerical aperture of the photolithographic system may be increased to lower the limit-of-resolution, the third parameter, depth-of-focus, will suffer as a result. Depth-of-focus is inversely proportional to NA 2 . Therefore, as NA increases, limit-of-resolution decreases but depth-of-focus decreases more rapidly. The reduced depth-of-focus makes accurate focusing more difficult especially on non-planar features such as “Manhattan Geometries” becoming increasingly popular in advanced semiconductor devices.  
         [0010]     Therefore, what is needed is a method of forming a FinFET device with minimum design geometries substantially smaller than achievable with photolithography. Further, the FinFET device must be fabricated by a process that is reproducible and fully adaptable to high-volume semiconductor fabrication processes.  
       SUMMARY  
       [0011]     An SOI transistor is fabricated by a highly modified FinFET technology. The FinFET implementation disclosed utilizes design rules far smaller than may be achieved through conventional lithography by fabricating nitride spacers to define device geometries on underlying semiconducting layers. Lateral device geometries relate to a thickness, rather than a width, of a deposited dielectric layer.  
         [0012]     In an exemplary embodiment, a method for forming a highly modified FinFET transistor includes providing a substrate having a base, an insulative layer, and a semiconducting layer and forming a pedestal region from the semiconducting layer. The pedestal region is surrounded with a first dielectric layer where an uppermost surface of the first dielectric layer is substantially coplanar with an uppermost surface of the pedestal region. A second dielectric material is then formed over a first uppermost portion of the pedestal region leaving an exposed uppermost portion of the pedestal region not covered by the second dielectric material. A third dielectric material is formed conformally over the second dielectric material and the exposed portion of the pedestal region. Horizontal regions of the third dielectric material are etched, leaving a first dielectric spacer where the first dielectric spacer overlies a protected portion of the pedestal region. Substantially all portions of the second dielectric material are then removed followed by removing substantially all portions of the pedestal region that are not laterally in close proximity to or underlying the protected portion, thereby forming a fin. The fin is doped with a dopant having a first type of majority carrier and the doped fin thus forms a channel region of the transistor. Transistor gate, drain, and source are then formed in association with the channel region to complete the device.  
         [0013]     In another exemplary embodiment, a highly modified FinFET transistor includes a fin fabricated from a first portion of a first semiconducting layer where the semiconducting layer overlies an insulating layer (e.g., SOI or SIMOX). A minimum lateral dimension of the fin is related to a thickness of a dielectric formed over the fin and used to form a dielectric spacer rather than relying on a limit of resolution of a particular photolithographic tool. A gate region comprised of a second semiconducting material overlies the fin, the fin being doped with a majority carrier of a first type. A drain region is formed on a second portion of the semiconducting material adjacent to the fin, the drain region being located on a first side of the gate region, the drain region being doped with a majority carrier of a second type. A source region is formed on a second portion of the semiconducting material adjacent to the fin, the source region being distal to the drain region and located on a second side of the gate region, the source region being doped with the majority carrier of the second type. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a perspective view of a FinFET device of the prior art.  
         [0015]      FIGS. 2A-2L  show various stages in an exemplary process flow for producing a self-aligned nanometer-level transistor. 
     
    
     DETAILED DESCRIPTION  
       [0016]     With reference to  FIG. 2A , a substrate  201 A has a insulative layer  201 B, and an unetched semiconductor layer  201 C 1 . In a specific exemplary embodiment the substrate  201 A, the insulative layer  201 B, and the (unetched) semiconductor layer  201 C 1  is a commonly available combination material—a silicon-on-insulator (SOI) wafer. Another combination material incorporating the aforementioned three layers is a wafer produced as a separation by implantation of oxygen (SIMOX). However, a skilled artisan will recognize that other appropriate materials for the substrate  201 A or the (unetched) semiconductor layer  201 C 1  materials include, for example, elemental semiconductors such as germanium, compound semiconductors such as group III-V, and II-VI materials, and semiconducting alloys. Additionally, the substrate  201 A may be comprised of a non-semiconducting material such as, for example, a photomask blank or reticle. The term “substrate,” as used herein, may thus be interpreted to be either a base, such as the substrate  201 A, or a combination material including a base, an insulative layer, and a semiconductor layer.  
         [0017]     The etched semiconductor layer  201 C is patterned and etched to produce the pedestal shape shown in  FIG. 2A  by techniques known to a person of skill in the art. For example, after appropriate masking, if the (unetched) semiconductor layer  201 C 1  is comprised of silicon, silicon may be etched with, for example, dry-etch techniques. Once the etched semiconductor layer  201 C 1  has been formed, a fill oxide  203 , a pad oxide  205 A, and a first nitride layer  207  A are added to and around the etched semiconductor layer  203 C 1 . The fill oxide  203  may be, for example, a high-density plasma (HDP) generated silicon dioxide film or an oxide produced by various other chemical vapor deposition (CVD) techniques. The pad oxide  205 A may be, for example, thermally grown or produced by CVD techniques. The nitride layer  207 A may also be produced by CVD techniques comprising silicon nitride deposition techniques. In a specific exemplary embodiment, the pad oxide  205 A is 50 Å-200 Å in thickness, the first nitride layer  207 A is 500 Å-1500 Å in thickness, and a total height of the fill oxide  203  is dependent on a thickness of the (unetched) semiconductor layer  201 C 2 . The nitride layer  207 A will be used as “Hard” mask. If the starting material used is SOI, the height of the etched semiconductor layer  203 C 1  is about 0.20 μm-1.0 μm. Although exact fabrication procedures and sequences for producing the fill oxide  203 , the pad oxide  205 A, or the first nitride layer  207 A are not given herein, such fabrication procedures are readily known to a person of ordinary skill in the art.  
         [0018]     With reference to  FIG. 2B , a first mask layer  209  is deposited and patterned, partially overlapping an uppermost section of the first nitride layer  207 A. The first mask layer  209  may be, for example, tetra-ethoxysilane (TEOS) deposited to a thickness of about 1000 Å-3000 Å. A second nitride layer  211 A ( FIG. 2C ) is then conformally deposited over the first mask layer  209 . A thickness, t s , of the second nitride layer  211 A is typically less than 2000 Å. The thickness, t s , defines a thickness of an eventual semiconductor fin produced (discussed infra). Consequently, an actual thickness, t s , of the second nitride layer  211 A is less important than the fabrication techniques described herein so long as the thickness, t s , is chosen to closely match an expected thickness of the fin produced.  
         [0019]     A dry-etch (e.g., a reactive-ion etch (RIE)) optimized to remove primarily horizontal portions of the second nitride layer  211 A produces a nitride spacer  211 B ( FIG. 2D ). The first mask layer  209  is then removed ( FIG. 2E ) by etching in accordance with methods known in the semiconductor arts. For example, depending upon a chemical composition of a given layer, etching may be accomplished through various wet etch (e.g., in hydrofluoric acid, such as contained in a standard buffered oxide etch, or orthophosphoric acid) or dry-etch techniques (e.g., RIE).  
         [0020]      FIG. 2F  provides a multi-view indication of a relationship between the nitride spacer  211 B and other features in the fabrication process such as the first nitride layer  207 A. The plan view of  FIG. 2F  shows that the nitride spacer  211 B is actually a square ring that once surrounded the now-etched first mask layer  209 . Section A-A of  FIG. 2F  indicates only that portion of the nitride spacer  211 B that will be used to form the etched semiconductor fin (described infra). An area underlying the nitride layer  207 A will eventually become the active area of the transistor. Section B-B indicates portions of the nitride spacer  211 B lying outside of the active area, the active area being confined primarily to an area within the fill oxide  203 .  
         [0021]     With reference to  FIG. 2G , a photoresist mask layer  213  is applied over the fill oxide  203 , the first nitride layer  207 A, and the nitride spacer  211 B . The photoresist mask layer  213  is then patterned forming an open channel over portions of both the fill oxide  203  and the active area. The open channel area allows an etchant to remove underlying layers of material in the active area (Section C-C,  FIG. 2G ). A highly selective dry etch (e.g., RIE) may be used to remove the underlying layers within the channel. The nitride spacer  211 B serves as a hard mask to the underlying etched semiconductor layer  201 C 1  thus allowing an etched semiconductor fin (“fin”)  201 C 2  to be formed (Section A-A). Portions of the etched semiconductor layer  201 C 1  remain in the active area bounded by the fill oxide  203 . These portions will later form source and drain regions, discussed infra. Notice that an original surface height of the fill oxide  203  may also be lowered due to aggressive etching required to clear the underlying layers down to an uppermost portion of the insulative layer  201 B. The insulative layer  201 B acts as an etch-stop; thus, timing issues are eliminated.  
         [0022]     In addition to selectively etching and forming the fin  201 C 2  through dry-etch techniques, a skilled artisan will recognize that other etch techniques may be employed as well. In  FIG. 2H , the photoresist mask layer  213  ( FIG. 2G ) has been stripped. The nitride spacer  211 B and the etched first nitride layer  207 B have also been removed with, for example, a high-selectivity etchant (e.g., wet-etched). The high-selectivity etchant may be optimized to remove silicon nitride while having little if any effect on silicon or silicon dioxide. A cross-sectional view of the fin  201 C 2  is presented in Section A-A while Section B-B indicates a transverse slice through the fin  201 C 2  and a relationship of the fin to remaining portions of the etched semiconductor layer  201 C 1  which will become source and drain regions of a FET transistor.  
         [0023]     With reference to  FIG. 2I , the etched pad oxide 205B has been stripped from the fin  201 C 2  and a sacrificial oxide  215  has been formed over the fin  201 C 2 . If the fin  201 C 2  is comprised of any material subject to oxidation (e.g., silicon), the sacrificial oxide  215  may be thermally grown. This oxidation repairs any surface damage of the fin  201 C 2  after, for example, a dry-etch step. An oxide spacer layer  217 A is then conformally formed (e.g., deposited) over the fin  201 C 2  and surrounding areas. The plan view of  FIG. 2I  provides an illustration of how the conformally deposited oxide spacer layer  217 A produces open areas on either side of the fin  201 C 2 . Additionally, the oxide spacer  217 A surrounds the fin  201 C 2  (as indicated in Sections A-A and C-C). Relative thicknesses t s , and t 2  of various parts of the film stack are chosen such that a thickness of t s , is greater than a thickness of t 2 . ( FIG. 2I  should be viewed in a relative and not an absolute sense. Therefore, as is the case with all patent figures,  FIG. 2I  is not necessarily to scale. Therefore, it is to be understood that t 1 , is thicker than t 2 .  
         [0024]     In  FIG. 2J , the oxide spacer layer  217 A is etched anisotropically primarily etching the oxide spacer layer  217 A from sidewalls of the fin  201 C 2 , leaving etched oxide spacers  217 B of sides of the active area. Lateral dimensions in two directions on a fabricated device may be made extremely small through a use of spacers as described herein. This two-dimensional size reduction is due both to a small size of the nitride spacer  211 B ( FIG. 2G ) as well as a minimum width between the oxide spacers  217 B. Consequently, the fin  201 C 2  can theoretically possess lateral dimensions of 30 Å in each direction (i.e., x-y) or less.  
         [0025]     A preoxidation clean is performed to fully clean sidewalls of the fin  201 C 2  prior to forming a gate oxide (not shown) over the fin  201 C 2 . A dopant may be added to the fin  201 C 2  as well, forming a channel region of the FinFET transistor. A polysilicon layer  219  is then conformally applied ( FIG. 2K ). A planarization step is performed, planarizing a top portion of the polysilicon layer  219  to be substantially coplanar with uppermost portions of the fill oxide  203  and the etched first nitride layer  207 B. The planarization may be accomplished by, for example, a chemical mechanical planarization (CMP) system and process, using the uppermost portion of the etched first nitride layer  207 B as an etch stop.  
         [0026]     With reference to  FIG. 2L , an etching process (either dry-etch or wet-etch) is used to remove the remaining portions of the etched first nitride layer  207 B and the etched pad oxide layer  205 B remaining above each portion of the etched semiconductor layer  201 C 1  in the active area (i.e., the area bounded laterally by the fill oxide  203 . Standard transistor fabrication techniques are then employed to produce final features required for the FinFET transistor device, such as doping regions of the etched semiconductor layer  201 C 1  thus producing source and drain regions as indicated.  
         [0027]     In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that although specific layers are called out, such as oxide and nitride, other films (e.g., other dielectric films) with similar etch characteristics (e.g., high etch-selectivity differences) could be readily employed as well. Further, the exemplary embodiments called out specific techniques and specific processes for making a FinFET transistor. Similar techniques may be employed to produce other device types as well or a series of mixed device types. As defined and fabricated herein, adjacent devices require no additional barrier layers to isolate the devices (such as, for example, shallow trench isolation (STI) regions) since the fill oxide layer  203  surrounding each device may be employed as a barrier layer. Therefore, the specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.