Abstract:
A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

Description:
BACKGROUND  
       [0001]     The invention relates to basic input output systems and computer reset methods, in particular, to a rapid reset method that only resets the Central Processing Unit.  
         [0002]     Central Processing Units (CPU) often need to reset. For example, when a frequency ratio is changed, or when the power state is restored from a suspend mode to a normal mode, a CPU reset is required.  
         [0003]      FIG. 1  shows a conventional computer system architecture and signal flows thereof. The computer system  100  comprises a processor  102 , a Northbridge  104 , a Southbridge  106 , and a Read Only Memory (ROM) device  108 . The bus for the Northbridge  104  and Southbridge  106 , can be Peripheral Connection Interface (PCI), or specific standards such as VIA® V-Link or Intel® ICH. The Northbridge  104  couples to the processor  102  via Front Side Bus (FSB), to memory devices (not shown) via a memory bus, and to graphic units (not shown) via Accelerated Graphic Ports (AGP) Conventionally, when the processor  102  requires a reset, the Northbridge  104  cannot actively perform CPU reset. Conversely, the Southbridge  106  must deliver a system reset signal PCI_RST#, to completely reset the computer system, thereby triggering the Northbridge  104  to deliver the CPU reset signal CPU_RST# to the processor  102 . As shown in  FIG. 1 , the system reset signal PCI_RST# can be activated by a trigger  110 , or by Basic Input Output System (BIOS) programmed in the computer system  100 . The system reset signal PCI_RST# is delivered to units coupling to the PCI bus, and to the Northbridge  104  via the V-Link bus. When the Northbridge  104  receives the system reset signal PCI_RST#, corresponding reset signals RST# are individually generated by the Northbridge  104 , and delivered to memory devices and graphic units respectively. Simultaneously, a CPU reset signal CPU_RST# is generated and delivered to the processor  102  via the Front Side Bus (FSB). Therefore the only way to reset the processor  102 , is to completely reset the computer system  100 .  
         [0004]     In this method, however, the Northbridge  104  and Southbridge  106  are also reset, and data stored in the registers of the Northbridge  104  are lost, which is undesirable. Unrecoverable problems may occur when the computer system  100  returns from a power saving mode. Thus an initialization procedure is required to help the computer system  100  return to normal operation, increasing implementation complexity and cost.  
       SUMMARY  
       [0005]     An embodiment of the invention provides a reset method for use in a computer system comprising a Southbridge, a Northbridge and a processor. The system reset method comprises the following steps. First, a trigger signal is provided. A CPU reset signal is delivered by the Southbridge to the Northbridge after receiving the trigger signal, and is relayed to the processor. Thereafter, the processor is reset when receiving the CPU reset signal.  
         [0006]     The Southbridge comprises a plurality of sideband pins coupling to the processor to provide startup options. The processor is reset in a mode relative to the startup options determining the frequency ratio of the processor. The trigger signal is generated by a Basic Input Output System (BIOS).  
         [0007]     The reset method further comprises backing up the processor register data before the Northbridge delivers the CPU reset signal to the processor, and restoring the registers after the processor is reset.  
         [0008]     Another embodiment of the invention provides the described computer system, performing the described method. A further embodiment provides the described BIOS, processing the described method on the computer described system. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:  
         [0010]      FIG. 1  shows a conventional computer system and signal flows therein;  
         [0011]      FIG. 2  shows an embodiment of a computer system and signal flows therein; and  
         [0012]      FIG. 3  is a flowchart of an embodiment of the reset method. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]      FIG. 2  shows an embodiment of a computer system  200  and signal flows therein. The computer system  200  comprises a processor  102 , a Northbridge  104 , a Southbridge  106  and a ROM device  108 . Additionally, the computer system  200  is capable of receiving a CPU reset trigger  202 , for directly resetting the processor  102  without affecting other units therein. The sideband pins  204 , conforming to earlier processor specifications, are capable of providing specific startup options such as frequency ratio. When the Southbridge  106  receives the CPU reset trigger  202 , a signal CPU_RST# is delivered directly to the Northbridge  104  via the V-Link bus. When the Northbridge  104  receives the signal CPU_RST#, relay it to the processor  102  via the Front Side Bus (FSB), thereby the processor  102  is reset. During reset of processor  102 , the potentials on the sideband pins  204 , provided by the Southbridge  106 , are referenced as startup options for the processor  102 . For example, the number of sideband pins  204  may be four, each indicating a bit  0  or  1 , providing the frequency ratio of the processor  102  with 16 variations, thus the processor  102  can read the bits when reset and operate on the frequency accordingly. In another case, the Northbridge  104  also provides some startup options such as Hyper-Threading enablement to the processor  102  during reset. The reset procedure only resets the processor  102 , and does not affect other units of the computer system  200 , therefore no additional initialization procedures are required for the Northbridge  104 , and data in the registers is not lost.  
         [0014]     Similar to trigger  110 , the CPU reset trigger  202  can be triggered externally, or generated by the program in the system. For example, when the BIOS adjusts the frequency ratio, and when the computer system is returning from a power saving mode to normal mode, the CPU reset trigger  202  is generated.  
         [0015]     In another case, before the Northbridge  104  relays the CPU reset signal CPU_RST# to the processor  102 , data in the registers of processor  102  can be backed up in the memory devices. When the processor  102  reset is complete, the data are restored to the registers thereto.  
         [0016]      FIG. 3  is a flowchart of an embodiment of the reset method. First, in step  302 , a trigger signal is provided on the Southbridge  106 . The trigger signal only resets the processor, not the entire computer system. In step  304 , the Southbridge  106  delivers a CPU reset signal to the Northbridge  104  when receiving the trigger signal. The communication of the Southbridge  106  and Northbridge  104  is performed using a specific protocol capable of distinguishing the difference between the CPU reset signal and the system reset signal, thus the processor  102  can be individually reset. In step  306 , the Northbridge  104  receives and relays the CPU reset signal to the processor  102 . Alternatively, the Northbridge  104  backs up the processor register data in the processor  102  to the memory devices before relaying the CPU reset signal, and then delivers the CPU reset signal to reset the processor  102 . In step  308 , the processor  102  is reset upon receiving the CPU reset signal. For some earlier processor  102  types, a plurality of sideband pins  204  coupling between the Southbridge  106  and the processor  102  are supported, and some specific startup options are provided by the Southbridge  106  to the processor  102  via the sideband pins  204 . The processor  102  operates in a mode corresponding to the startup options provided after reset. For example, if the sideband pins  204  are used to determine frequency ratio, the processor  102  operates at a corresponding frequency accordingly. Additionally, a plurality of native pins coupling between the Northbridge  104  and processor  102 , also provide some startup options based on the processor implementation guide, such as Hyper-Threading enablement. In step  310 , if present, the memory devices restore the backed up register data to the processor  102 , thus the computer system can return to the previous working state.  
         [0017]     In summary, the invention simplifies the CPU reset procedure, avoids unnecessary system re-initialization and data loss, satisfies specific requirements such as rapid resetting and frequency ratio adjustment.  
         [0018]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.