Abstract:
A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

Description:
PRIORITY CLAIM 
       [0001]    This application claims priority to provisional application Ser. No. 62/088,912, filed Dec. 8, 2014, which is entirely incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    This disclosure relates to signal transmission. This disclosure also relates to long-distance, high-speed data and clock transmission. 
       BACKGROUND 
       [0003]    Rapid advances in electronics and communication technologies, driven by immense customer demand, have resulted in the widespread adoption of a wide array of sophisticated electronic devices. These devices often rely on high speed processing circuitry that implements complex functionality. In many cases, the circuitry employs high speed signaling over long distances. Improvements in the communication pathways for such signaling will improve the performance and functionality of these devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  shows an example transmission line with a non-linear impedance for far end termination. 
           [0005]      FIG. 2  shows examples of signal response in the transmission line. 
           [0006]      FIG. 3  is an example of a non-linear impedance. 
           [0007]      FIG. 4  shows an example of undershoot performance for the transmission line. 
           [0008]      FIG. 5  shows an example of overshoot performance for the transmission line. 
           [0009]      FIG. 6  shows an example implementation of a non-linear resistor with biasing circuitry. 
           [0010]      FIG. 7  shows connections between circuits, the connections terminated by non-linear impedances. 
           [0011]      FIG. 8  shows a circuit design process. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]      FIG. 1  shows an example transmission line  100  with a non-linear impedance for far end termination. More particularly, the transmission line  100  includes a signal path  102  that provides a signal propagation medium  104  along which signals travel. At the end of the signal path  102  is a termination point  106 . A non-linear impedance  108 , Z, is connected at the termination point. 
         [0013]    For the purposes of explanation below,  FIG. 1  also shows a driver circuit  110 . The driver circuit  110  drives signals onto the transmission line  100 . In  FIG. 1 , the driver circuit  110  is modeled as a voltage source  112  in series with an impedance  114 , R out . Note that R out  is often difficult to control accurately, and non-linear termination will facilitate better performance for the transmission line  100 . 
         [0014]    The signal path  102  may be differential, as shown, or single ended. The signal path is characterized by an impedance, Z 0 . Signal reflections at the termination point  106  may occur when Z 0  is not equal to Z. A measure of the mismatch between Z 0  and Z is the reflection coefficient parameter, denoted by gamma: 
         [0000]    
       
         
           
             Γ 
             = 
             
               
                 Z 
                 - 
                 
                   Z 
                   0 
                 
               
               
                 Z 
                 + 
                 
                   Z 
                   0 
                 
               
             
           
         
       
     
         [0015]    The signal propagation medium  104  may be any electrical conductor. As examples, the signal propagation medium  104  may be metal or polysilicon lines within an integrated circuit, traces between modules carried in a Multiple-Chip-Module (MCM), traces on a circuit board that carry signals between sets of circuitry on the circuit board, wire cables such as coaxial cables, or other propagation mediums. In some cases, the non-linear impedance  108  may be included when the wavelength of the signals on the signal path  102  is comparable to the length of the signal path  102 . Said another way, the wavelength of a signal is the propagation speed (e.g., the speed of light) divided by the signal frequency. When the physical length of a signal path becomes comparable to wavelength (e.g., more than one tenth of a wavelength), then non-linear termination may be included to help prevent undesired signal reflections. The non-linear impedance  108  may be included when it is desired to manage signal reflections that are expected to be significant arising from an impedance mismatched termination point  106 . In some systems, the length may be on the order of several millimeters, although there is no restriction on when the non-linear impedance  108  may be included. 
         [0016]    The termination point  106  may represent any endpoint for the signal path  102  or selected location along the signal path  102 . As an example, the termination point may be at or adjacent to the input of a processing circuit that processes signals sent by the driver circuit  110 . 
         [0017]      FIG. 2  shows examples of signal response  200  in the transmission line  100 . In  FIG. 2 , v+ represents the pulse travelling in the positive direction down the signal path  102  toward the termination point  106 , and v− represents the reflected pulse, with the total voltage, v=v++v−. In example  202 , R out &gt;Z 0 , while in example  204 , R out &lt;Z 0 . 
         [0018]    For the example  202 , R out &gt;Z 0  causes a voltage step  206  that is less than half of the voltage swing. The voltage at the far end should settle to the full voltage swing, v. A v− larger than v+ is therefore desired to reach the full voltage swing, v. This, in turn, means: 
         [0000]      Γ&gt;1
 
         [0000]      Z&lt;0 
         [0019]    That is, for the example  202 , the non-linear impedance  108  presents a negative impedance. 
         [0020]    For the example  204 , R out &lt;Z 0  causes a voltage step  208  that is greater than half of the voltage swing. The voltage at the far end should settle to the full voltage swing, v. A v− smaller than v+ is therefore desired to reach the full voltage swing, v. This, in turn, means: 
         [0000]      F&lt;1 
         [0000]      Z&gt;0 
         [0021]    That is, for the example  202 , the non-linear impedance  108  presents a positive impedance. Expressed another way, the non-linear impedance  108  is a voltage dependent impedance. 
         [0022]      FIG. 3  shows an example implementation  300  for the non-linear impedance  108 . In this example, the non-linear impedance includes a first inverter  302  connected back-to-back with a second inverter  304 . The first inverter  302  and second inverter  304  are not used as digital switches, but in an analog manner as voltage controlled resistors.  FIG. 3  shows the voltage and current conventions used for the discussion of the impedance of this configuration, in connection with the voltage and current waveform  306 . 
         [0023]    Note that the non-linear impedance presents a negative impedance in regions  308  and  309  (i.e., v/i&lt;0) in response to a first range of input voltage  310 , e.g., |v|&lt;|vdd| where vdd is the power supply voltage to the transistors in the first and second inverters  302  and  304 . In region  309 , for instance, v is positive, and the first inverter  302  tries to drive its output low, thereby sinking current (and i is negative given the current convention), while in region  308 , v is negative and the inverter  304  tries to drive its output low, thereby sinking current (and i is positive given the current convention). 
         [0024]    The non-linear impedance presents a positive impedance  312  (i.e., v/i&gt;0) in response to a second range of input voltage  314  that is different than the first range of input voltage  310 , e.g., |v|&gt;|vdd|. As shown in  FIG. 3 , the non-linear impedance is a voltage dependent impedance, with current changing depending on the applied voltage. 
         [0025]      FIG. 4  shows an example of undershoot performance  400  for the transmission line. The voltage curve  402  shows performance without termination of the signal path  102 . The voltage curve  404  shows performance with termination of the signal path  102  by the non-linear impedance shown in  FIG. 3 . Note that with termination, the voltage curve rises much more quickly to the desired high voltage  406 , and also falls more quickly to the desired low voltage  408 . 
         [0026]      FIG. 5  shows an example of overshoot performance  500  for the transmission line. The dashed voltage curve  502  shows performance without termination of the signal path  102 . The solid voltage curve  504  shows performance with termination of the signal path  102  by the non-linear impedance shown in  FIG. 3 . Note that with termination, the voltage curve  504  has less overshoot, and settles to the final high voltage  506  and the final low voltage  508  more quickly than without termination. 
         [0027]      FIG. 6  shows an example implementation of a non-linear resistor with biasing circuitry  600 . There is a positive-side bias circuit  602  and a negative-side bias circuit  604 . Each bias circuit includes a reference voltage input, e.g., the positive-side reference voltage Vrefp  606  and the negative side reference voltage Vrefn  608 . The reference voltages may be set to one-half of vdd, for instance, with the individual transistor matched in width/length or wide/length ratio. Each bias circuit also includes a calibrated output impedance, e.g., the positive-side calibrated impedance  610  and the negative-side calibrated impedance  612 , connected to the non-linear impedance. 
         [0028]    The positive-side bias circuit  602  is connected to a positive side transistor  614  in the first inverter  616  and to a positive side transistor  618  in the second inverter  620 . The first inverter  616  is connected back-to-back with the second inverter  620 . The negative-side bias circuit  604  is connected to a negative-side transistor  622  in the first inverter  616  and to a negative-side transistor  624  in the second inverter  620 . 
         [0029]    As noted above, the signal path  102  may be a differential signal path. The non-linear impedance  108  may then be connected across the differential signal path. More specifically, with reference to the example in  FIG. 6 , the non-linear impedance  300  is connected across the differential signal path S+ and S−, which may be a differential clock line, data line, control line, or any other type of communication path.  FIG. 6  shows the first input, P, of the inverter  616  connected to the first path S+ and the second input, N, of the inverter  620  connected to the second path S−. 
         [0030]    The reference voltage  606  is mirrored at the negative-side calibrated impedance  612 , causing a known fixed current to flow through the negative-side calibrated impedance  612 . The reference voltage  608  is mirrored at the positive-side calibrated impedance  610 , causing a known fixed current to flow through the positive-side calibrated impedance  610 . The outputs  626 ,  628  of the operational amplifiers  630 ,  632  adjust to control their respective current source transistors  634 ,  636  (which are matched to the inverter transistors), and thereby account for any process, voltage, or temperature (PVT) variation, in the process of generating the known fixed currents. The transistor  634  is part of a stacked pair of transistors  634 ,  635 , and the transistor  636  is part of the stacked pair of transistors  636 ,  637 . In the positive side bias circuit  602 , the current through the stacked transistors  634 ,  635  is fixed to Vrefp divided by the negative-side calibrated impedance  612 , and the voltage across the stacked transistors  635 ,  635  is fixed to vdd−Vrefp. Accordingly, the effective impedance of the stacked transistors  634 ,  635  is fixed and has no PVT variation, a characteristic copied to the first inverter  616  and the second inverter  620 . 
         [0031]      FIG. 7  shows connections between modules  700 , the connections terminated by non-linear impedances. In the example in  FIG. 7 , a multi-chip module (MCM)  702  includes individual modules  704 ,  706 , and  708 . The MCM  702  may be provided, for instance, on a single common carrier  710 . 
         [0032]    The module  704  communicates with the module  706  over an inter-module signal path  712 . The signal path is terminated with a non-linear resistor (NLR)  714 . The NLR  714  may be the back-to-back inverter configuration discussed above. As another example, the module  708  includes circuitry  716  and  718  that communicate over an inter-circuitry signal path  720 . The inter-circuitry signal path  720  is terminated with a NLR  722 . The NLR  722  may be the back-to-back inverter configuration discussed above. As a further example, the NLR-terminated inter-MCM signal path  724  connects the module  706  and the module  726 . As additional examples, NLRs may terminate signal paths between circuit boards or discrete systems. 
         [0033]      FIG. 8  shows a circuit design process  800 . The process  800  may be implemented in a circuit design tool (e.g., in software) stored in a memory and executed by a processor in a circuit design hardware system, for instance. The process  800  includes identifying a signal path in a circuit layout for which to control signal quality (e.g., to reduce reflections) ( 802 ). The signal path includes a signal propagation medium along which signals travel. The process  800  also identifies a termination point along the signal propagation medium ( 804 ), e.g., at the end of the signal propagation medium. 
         [0034]    The process  800  determines whether to place a non-linear impedance at the termination point ( 806 ). For instance, the process  800  may determine whether sufficient layout space exists to place the impedance, whether impedance mismatch at the termination point is calculated to exceed a placement threshold, or may make the determination based on other criteria. If the impedance will be placed, then the process  800  places the impedance in the circuit layout ( 808 ). As noted above, the impedance may present a negative impedance in response to a first range of input voltage and present a positive impedance in response to a second range of input voltage that is different than the first range of input voltage. The impedance may be a first inverter connected back-to-back with a second inverter. 
         [0035]    Further, the process  800  may determine whether to place bias circuit(s) in the layout ( 810 ), such as bias circuits  602  and  604 . The bias circuits may include a reference voltage input and a calibrated output impedance connected to the non-linear impedance. More particularly, the bias circuits may include a positive-side bias circuit comprising a positive-side reference voltage input and a positive-side calibrated output impedance connected to the non-linear impedance, as well as a negative-side bias circuit comprising a negative-side reference voltage input and a negative-side calibrated output impedance connected to the non-linear impedance. 
         [0036]    The circuit design hardware system may be implemented in many different ways and in many different combinations of hardware and software. For example, all or parts of the implementations may be circuitry that includes an instruction processor, such as a Central Processing Unit (CPU), microcontroller, or a microprocessor; an Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or Field Programmable Gate Array (FPGA); or circuitry that includes discrete logic or other circuit components, including analog circuit components, digital circuit components or both; or any combination thereof. The circuitry may include discrete interconnected hardware components and/or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a Multiple Chip Module (MCM) of multiple integrated circuit dies in a common package, as examples. 
         [0037]    The circuitry may further include or access instructions for execution by the circuitry. The instructions may be stored in a tangible storage medium that is other than a transitory signal, such as a flash memory, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM); or on a magnetic or optical disc, such as a Compact Disc Read Only Memory (CDROM), Hard Disk Drive (HDD), or other magnetic or optical disk; or in or on another machine-readable medium. A product, such as a computer program product, may include a storage medium and instructions stored in or on the medium, and the instructions when executed by the circuitry in a device may cause the device to implement any of the processing described above or illustrated in the drawings. 
         [0038]    The implementations may be distributed as circuitry among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways, including as data structures such as linked lists, hash tables, arrays, records, objects, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library, such as a shared library (e.g., a Dynamic Link Library (DLL)). The DLL, for example, may store instructions that perform any of the processing described above or illustrated in the drawings, when executed by the circuitry. 
         [0039]    Various implementations have been specifically described. However, many other implementations are also possible.