Abstract:
A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/811,487, filed on Apr. 12, 2013, the entirety of which is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a semiconductor device, and in particular relates to a chip package and fabrication method thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    The chip packaging process is an important process when fabricating an electronic product. Chip packages not only provide chips with protection from environmental contaminants, but also provide an interface for connection between electronic elements in the chips and electronic elements outside of the chip package. 
         [0006]    Due to reductions in the size of electronic products, forming chip packages with more functions and smaller sizes has become an important issue. However, chip packages with more functions and smaller sizes have high-density circuits, which results in a large chip warpage and can lead to some of the solder balls on the chip not being able to bond to a packaging substrate. Therefore, the durability of such chip packages is low, and the performance of the chips is impacted. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    Embodiments of the invention provide a chip package, including: a packaging substrate; a chip; and solder balls disposed between the packaging substrate and the chip so as to bond the chip onto the packaging substrate, wherein the solder balls have a first size and a second size that is different from the first size. 
         [0008]    Embodiments of the invention provide a manufacturing method of a chip package, including: forming a plurality of chips on a wafer; measuring distribution of a circuit of the chips on the wafer; disposing a plurality of solder balls on the chips on the wafer, wherein the solder balls have a first size and a second size, and the solder balls of the first size and the solder balls of the second size are arranged according to the measurement result; bonding the wafer onto a packaging substrate; and dicing the wafer to form a plurality of chip packages. 
         [0009]    Embodiments of the invention provide a manufacturing method of a chip package, including: forming a plurality of chips on a wafer; measuring warpage of the chips on the wafer; dicing the wafer into a plurality of separated chips; disposing a plurality of solder balls on the separated chips, wherein the solder balls have a first size and a second size, and the solder balls of the first size and the solder balls of the second size are arranged according to the measurement result of the warpage; and bonding the separated chips onto corresponding packaging substrates. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIGS. 1A-1E  are cross-sectional views of a wafer-level packaging process of a chip package according to an embodiment of the invention; 
           [0013]      FIG. 2  is a bottom view of chips after being disposed with the solder balls of FIG.  1 C; 
           [0014]      FIG. 3  is a cross-sectional view of a wafer-level packaging process of a chip package according to another embodiment of the invention; and 
           [0015]      FIGS. 4A-4B  are cross-sectional views of a chip-level packaging process of a chip package according to one embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0017]    It should be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, descriptions of a first layer “on,” “overlying,” (and like descriptions) a second layer, include embodiments where the first and second layers are in direct contact and those where one or more layers are interposing the first and second layers. 
         [0018]    A chip package according to an embodiment of the present invention may be used to package a proximity sensor, but the application is not limited thereto. The wafer scale packaging process mentioned above mainly means that after the packaging process is accomplished during the wafer stage, the wafer with chips is cut to independent packages. However, in a specific embodiment, separated chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer scale packaging process. In addition, the above mentioned wafer scale packaging process may also be adapted to form chip packages of multi-layer integrated circuit devices by stacking a plurality of wafers having integrated circuits. In one embodiment, the diced package is a chip scale package (CSP). The size of the chip scale package may be only slightly larger than the size of the packaged chip. For example, the size of the chip package is not larger than 120% of the size of the packaged chip. 
         [0019]      FIGS. 1A-1E  are cross-sectional views of a wafer-level packaging process of a chip package according to an embodiment of the invention. As shown in  FIG. 1A , a semiconductor substrate  100  is provided. The semiconductor substrate  100  has a surface  100   a . The semiconductor substrate  100  is, for example, a semiconductor wafer. Therefore, the symbol  100  may represent a semiconductor wafer. The suitable semiconductor wafer may include a silicon wafer, a silicon-germanium wafer, a gallium arsenide wafer, or the like. 
         [0020]    The semiconductor substrate  100  has chips  102 . In the embodiments of the present invention, the chips  102  may include active or passive elements, or electronic components with digital or analog circuits, such as opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting the physical quantity variation of heat, light, or pressure. Particularly, a wafer scale package (WSP) process may be applied to package semiconductor chips such as image sensor devices, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, pressure sensors, ink printer heads, or power MOSFET modules. In the present embodiment, the chips  102  may be manufactured by any suitable process, such as a wafer-level CMOS process. 
         [0021]    Since each of the chips  102  has function circuits, each of the chips  102  has a warpage according to the circuit design. For example, the warpage includes an upward warpage of the chip edge, a downward warpage of the chip edge or other irregular warpage. In general, for dispersing the stress resulted from the warpage of the chips  102 , the semiconductor substrate  100  has a warpage shape corresponding to the chips  102 . In some embodiments, the chips  102  of the semiconductor substrate  100  are chips with the same function or the same design. Therefore, in top view, each of the chips  102  of the semiconductor substrate  100  is a repeating unit, and the chips  102  are arranged in the semiconductor substrate  100  continuously. That is, as shown in  FIG. 1A , the semiconductor substrate  100  with the chips  102  has a surface  100   a  with a substantial wavy shape. It should be noted that  FIG. 1A  only shows an embodiment of a downward warpage of the chip edge. However, persons skilled in the art may conjecture that the surface of the semiconductor substrate  100  has a wavy shape when the edges of the chips  102  warp upwardly or irregularly. Furthermore, in one embodiment, a space (not shown) is between the chips  102  to be used as a scribing line SC. 
         [0022]    Thereafter, as shown in  FIG. 1B , it shows a measurement  101  of circuit distributions on the surface  100   a  of each of the chips  102 . In one embodiment, the measurement  101  may be performed by using a surface scattering instrument or by other measuring methods. It should be noted that the warpage shape and the warpage degree of each of the separated chips  102  formed from dicing the semiconductor substrate  100  is able to be calculated by the measurement of circuit distributions on the surface  100   a  of each of the chips  102 . 
         [0023]    Then, referring to  FIG. 1C , according to the calculation result mentioned above, the solder balls  104  are disposed on each of the chips  102  of the semiconductor substrate  100 . In one embodiment, the solder balls  104  may at least have a first size and a second size that is different from the first size. The solder balls  104  may have various sizes according to requirements. For example, the solder balls  104  may have a third size different from the first size and the second size or have more sizes. In one embodiment, the sizes of the solder balls  104   a  of the first size and the solder balls  104   b  of the second size have a positive relationship or a negative relationship to the warpage degree and the warpage direction of the chips. Alternatively, the solder balls  104  may at least have a first height and a second height that is different from the first height and other heights. For illustration purposes, the different heights are referred as different sizes in the following description. The solder balls  104  may include eutectic solder balls, lead-free solder balls or combinations thereof. For example, in some embodiments, according to the calculation results, the solder balls  104   a  and  104   b  are disposed on portions of the chips  102  with a low degree of warpage and portions of the chips  102  with a high degree of warpage, respectively, and vice versa. Therefore, there are the solder balls  104   a  of the first size and the solder balls  104   b  of the second size on each of the chips  102 . In some embodiments, there are the solder balls  104   c  with the third size or the solder balls of other size on the chips  102 . The number of the solder balls of different sizes may be varied according to the chip warpage degree or the area of the chip, and may be adjusted according to demand. 
         [0024]    In some embodiments, the spacing d1 between the adjacent solder balls  104   a  of the first size is different from the spacing d2 between the adjacent solder balls  104   b  of the second size. For example, referring to  FIG. 2 ,  FIG. 2  is a bottom view of the chips  102  after being disposed with the solder balls  104  (as shown in  FIG. 1C ). As shown in  FIG. 2 , the spacing d1 between the adjacent solder balls  104   a  of the first size is different from the spacing (not shown) between the solder balls  104   a  and the solder balls  104   b  of the second size. According to the above descriptions, it is known that the spacings mentioned above are determined according to the warpage degree and the shape of the chips  102  after dicing the semiconductor substrate  100 . 
         [0025]    For example,  FIG. 1C  shows the embodiment in which the chip edges warp downwardly. The solder balls  104   a  of the first size may be disposed adjacent to the center of each of the chips  102 . The solder balls  104   b  of the second size may be disposed adjacent to the edge of each of the chips  102 . The solder balls  104   c  with the third size may be disposed mostly adjacent to the edge of each of the chips  102 . In the present embodiment, the first size is larger than the second size, and the second size is larger than the third size. 
         [0026]    As shown in  FIG. 2 , the solder balls  104   b  of the second size and the solder balls  104   c  with the third size are disposed adjacent to the corners of the chips  102 . Alternatively, in other embodiments, the solder balls  104   b  of the second size and the solder balls  104   c  with the third size are arranged in one row or multiple rows concentrically surrounding the solder balls  104   a  (not shown) disposed adjacent to the center of each of the chips  102 . 
         [0027]    In the present embodiment, the solder balls  104   a  of the first size have the main functions of support and signal transmission. The solder balls  104   b  of the second size, the solder balls  104   c  with the third size and the solder balls of other sizes may also have the functions of support and electronic signal transmission. Alternatively, in other embodiments, the solder balls  104   b  of the second size, the solder balls  104   c  with the third size and the solder balls of other sizes may have the functions of support, stress compensation or heat conduction and are not connected with functional circuits of the chips  102 . 
         [0028]    Then, referring to  FIG. 1D , the semiconductor substrate  100  is disposed on the packaging substrate  120  via the solder balls  104   a , and the semiconductor substrate  100  and the packaging substrate  120  are diced into separated chip packages  140  along the scribing lines SC on the semiconductor substrate  100 . The packaging substrate  120  is, for example, a printed circuit board, a silicon substrate with a function of electrical connection, three dimensional (3D) packaging substrate, etc. After the dicing process, the separated chips  102  may warp due to the distribution of the functional circuits of the chips  102 . Therefore, the solder balls  104   a ,  104   b  and  104   c  may be in close contact with the packaging substrate  120 . 
         [0029]    Thereafter, referring to  FIG. 1E , a reflow process is performed to the solder balls  104   a ,  104   b  and  104   c , such that the solder balls  104   a ,  104   b  and  104   c  are deformed into solder balls  104   a ′,  104   b ′ and  104   c ′ by gravity, and therefore the solder balls  104   a ′,  104   b ′ and  104   c ′ are in close contact with the chips  102  and the packaging substrates  120 . For example, since the solder balls  104   a ′ adjacent to the center of the chip  102  bear the main weight of the chip  102 , the solder balls  104   a ′ are wider and shorter than the unreflowed solder balls  104   a . Since the spacing between the chip  102  and the packaging substrate  120  becomes large, the solder balls  104   b ′ and  104   c ′ adjacent to the edge of the chip  102  are taller and more slender than the unreflowed solder balls  104   b  and  104   c.    
         [0030]    Therefore, the warpage of the chip  102  may be compensated by adjusting the size and the disposed position of the deformed solder balls  104   a ′,  104   b ′ and  104   c ′ and the spacing between the solder balls  104   a ′,  104   b ′ and  104   c ′. The solder balls  104   a ′,  104   b ′ and  104   c ′ may be the same height. Furthermore, the solder balls  104   a ′ are wider than the solder balls  104   b ′, and the solder balls  104   b ′ are wider than the solder balls  104   c ′. Therefore, the issue of warpage of the chip  102  may be reduced or eliminated, and the possibility of breaking the chip  102  is reduced. That is, the surface of the chip  102  is a substantially flat surface. 
         [0031]    Therefore, the manufacturing method of the embodiment of  FIGS. 1A-1E  may improve the yield, and the durability and the performance of the chip packages  140  formed by the manufacturing method are significantly improved. 
         [0032]      FIG. 3  shows chip packages  340  formed by the manufacturing method of the embodiment of  FIGS. 1A-1E . However, the edge of the chip  102  of the chip package  340  bears the main weight of the chip. In the present embodiment and the embodiment mentioned above, same reference numbers are used to designate same or similar elements. Therefore, the materials and the manufacturing methods of the elements with the same reference numbers are provided by referring to the relative description of the embodiment of  FIGS. 1A-1E . 
         [0033]    In the present embodiment, the solder balls  304   a ′ of the first size may be disposed adjacent to the centers of the chips  102 . The solder balls  304   b ′ of the second size may be disposed adjacent to the edges of the chips  102 . The solder balls  304   c ′ with the third size may be disposed mostly adjacent to the edge of each of the chips  102 . The same as the embodiment mentioned above, the solder balls  304   b ′ of the second size and the solder balls  304   c ′ with the third size may be disposed adjacent to the corners of the chips  102 . Alternatively, in other embodiments, the solder balls  304   b ′ of the second size and the solder balls  304   c ′ with the third size are arranged in one row or multiple rows concentrically surrounding the solder balls  304   a ′ (not shown) disposed adjacent to the center of each of the chips  102 . In the present embodiments, the solder balls  304   a ′,  304   b ′ and  304   c ′ may have the same height. The widths of the solder balls  304   a ′ are less than the widths of the solder balls  304   b ′, and the widths of the solder balls  304   b ′ are less than the widths of the solder balls  304   c′.    
         [0034]    Therefore, the warpage of the chip  102  may be compensated by adjusting the size and the disposed position of the deformed solder balls  304   a ′,  304   b ′ and  304   c ′ and the spacing between the solder balls  304   a ′,  304   b ′ and  304   c ′. Therefore, the issue of warpage of the chip  102  may be reduced or eliminated, and the possibility of breaking the chip  102  is reduced. That is, the surface of the chip  102  is a substantially flat surface. In the present embodiment, the solder balls  304   a ′ of the first size have the main functions of support and signal transmission. The solder balls  304   b ′ of the second size, the solder balls  304   c ′ with the third size and the solder balls of other sizes may also have the functions of support and electronic signal transmission. Alternatively, in other embodiments, the solder balls  304   b ′ of the second size, the solder balls  304   c ′ with the third size and the solder balls of other sizes may have the functions of support, stress compensation or heat conduction and are not connected with functional circuits of the chips  102 . 
         [0035]      FIGS. 4A-4B  are cross-sectional views of a chip-level packaging process of a chip package according to one embodiment of the invention. In the present embodiment and the embodiment mentioned above, same reference numbers are used to designate same or similar elements. Therefore, the materials and the manufacturing methods of the elements with the same reference numbers are provided by referring to the relative description of the embodiment of  FIGS. 1A-1E . 
         [0036]    As shown in  FIG. 4A , the solder balls  104  are disposed on each of the separated chips  102  according to the calculation result. In one embodiment, the solder balls  104  may at least have a first size and a second size that is different from the first size. In one embodiment, the sizes of the solder balls  104   a  of the first size and the solder balls  104   b  of the second size have a positive relationship or a negative relationship to the warpage degree and the warpage direction of the chips. Alternatively, the solder balls  104  may have various sizes according to requirements. For example, the solder balls  104  may further have a third size or more sizes. For example, in some embodiments, according to the calculation results, the solder balls  104   a  and  104   b  with different sizes are disposed on portions of the chips  102  with a low degree of warpage and portions of the chips  102  with a high degree of warpage, respectively, and vice versa. Therefore, there are the solder balls  104   a  of the first size and the solder balls  104   b  of the second size on each of the chips  102 . In some embodiments, there are the solder balls  104   c  with the third size or the solder balls of other size on the chips  102 . The number of the solder balls with different sizes may be varied according to the chip warpage degree or the area of the chip, and may be adjusted according to demand. 
         [0037]    In some embodiments, the spacing d1 between the adjacent solder balls  104   a  of the first size is different from the spacing d2 between the adjacent solder balls  104   b  of the second size. The spacings mentioned above are determined according to the warpage degree and the shape of the chips  102  after dicing the semiconductor substrate  100 . 
         [0038]    Then, referring to  FIG. 4B , the separated chips  102  are bonded onto the corresponding packaging substrate  120  respectively so as to form multiple chip packages  440 . Furthermore, a reflow process is performed to the solder balls  104   a ,  104   b  and  104   c , such that the solder balls  104   a ,  104   b  and  104   c  are deformed into solder balls  104   a ′,  104   b ′ and  104   c ′ by gravity, and therefore the solder balls  104   a ′,  104   b ′ and  104   c ′ are in close contact with the chips  102  and the packaging substrates  120 . For example, since the solder balls  104   a ′ adjacent to the center of the chip  102  bear the main weight of the chip  102 , the solder balls  104   a ′ are wider and shorter than the unreflowed solder balls  104   a . Since the spacing between the chip  102  and the packaging substrate  120  becomes large, the solder balls  104   b ′ and  104   c ′ adjacent to the edge of the chip  102  are taller and more slender than the unreflowed solder balls  104   b  and  104   c . For example, the solder balls  104   a ′ are shorter than the solder balls  104   b ′, and the solder balls  104   b ′ are shorter than the solder balls  104   c ′. The solder balls  104   a ′ are wider than the solder balls  104   b ′, and the solder balls  104   b ′ are wider than the solder balls  104   c′.    
         [0039]    Therefore, the warpage of the chip  102  may be compensated by adjusting the size and the disposed position of the deformed solder balls  104   a ′,  104   b ′ and  104   c ′ and the spacing between the solder balls  104   a ′,  104   b ′ and  104   c ′. For example, the solder balls  104   a ′,  104   b ′ and  104   c ′ may have the same height. The solder balls  104   a ′ are wider than the solder balls  104   b ′, and the solder balls  104   b ′ are wider than the solder balls  104   c ′. Therefore, the issue of warpage of the chip  102  may be reduced or eliminated, and the possibility of breaking the chip  102  is reduced. That is, the surface of the chip  102  is a substantially flat surface. Therefore, the manufacturing method of the embodiment of  FIGS. 1A-1E  may improve the yield, and the durability and the performance of the chip packages  440  formed by the manufacturing method are significantly improved. 
         [0040]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.