Abstract:
A method for fabricating a magnetic tunnel junction (MTJ) is disclosed. The process involves annealing a stack that includes a tunnel barrier layer and cooling the stack under vacuum immediately after annealing. At least one overlayer is deposited on the tunnel barrier layer to form the MTJ.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Patent Application No. 61/840,905 entitled “MAGNETIC TUNNEL JUNCTION (MTJ) WITH A MAGNESIUM OXIDE TUNNEL BARRIER,” filed on Jun. 28, 2013 for Minglang Yan, et al. which is incorporated herein by reference. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates one embodiment of the present method for fabricating MTJs. 
       FIG. 2  is a graph illustrating how reduced temperatures affect the magnetoresistance ratios (MR ratios) of various magnetic devices. 
       FIG. 3  is a graph of waiting time versus TMR ratio. 
       FIG. 4  is a graph comparing MR ratios obtained from various magnetic devices compared to MR ratios obtained from conventionally processed MTJs. 
    
    
     DETAILED DESCRIPTION 
       FIG. 1  summarizes the new process. The process begins by forming a partial stack  50  comprising conventional layers, such as a bottom shield  105  and tunnel barrier layer  113 . Intermediate structure  50  is formed in a manner that is well known in the art, and comprises a bottom shield  105  on which is deposited a seed layer  107 . In one embodiment, a seed layer  107  is deposited on a bottom shield  105 . Seed layer  107  may comprise a multilayer of CoFeB/NiFe/Ru. Upon seed layer  107  is deposited an antiferromagnetic layer  109 , such as IrMn. In this embodiment, synthetic antiferromagnetic (SAF) layers  111  are provided on antiferromagnetic layer  109 . In other embodiments SAF layers  111  are omitted. In this embodiment, a tunnel barrier layer  113  of MgO is formed on the SAF layers to complete intermediate structure  50 . In several embodiments, tunnel barrier layer  113  has a thickness of about four to seven angstroms. Subsequent treatment of the intermediate structure  50  will be described in more detail in association with  FIG. 1 . 
     The magnetic tunnel junction (MTJ) device is manufactured in a vacuum processing system that contains multiple chambers. The system can be a cluster tool that includes multiple deposition chambers, as well as chambers for heating, etching and holding. In one embodiment, the vacuum processing system is maintained at a base pressure of between 5×10 −9  to 7×10 −19  Torr, while the wafers are transported between chambers during processing. However, during deposition, the vacuum system has a higher pressure of between 0.5 mTorr-10 mTorr. In certain embodiments, the wafers are not subjected to a magnetic field during formation of the MTJ. 
     After tunnel barrier layer  113  is formed, a wafer containing multiple intermediate structures  50  is loaded into a heating chamber (not shown) to be annealed. In some embodiments, annealing may occur at a temperature between 100-250° C. in a vacuum system. In other embodiments, the wafer may be annealed at a temperature between 155-200° C. The annealing time may vary depending on the design requirements. In one embodiment, annealing takes place for a period ranging from 5 to 15 minutes. In other embodiments, tunnel barrier layer  113  is annealed from 15-30 minutes. Yet in other embodiments, the anneal time of the wafer can last for up to one hour. 
     After the wafer has been annealed, it is transferred to a holding chamber (not shown) via block  70  where it will be subject to cooling. The terms cool, cooled and cooling are used herein to refer to a natural reduction in temperature, as opposed to forced cooling. In some embodiments cooling is used in this disclosure to mean placing a wafer in a holding chamber for a predetermined waiting period. The holding chamber is kept at an ambient temperature ranging from 24 to 30° C. The wafer may be left in the holding chamber to cool down for anywhere from 5-35 minutes. Once the wafer has been in the holding chamber for the desired time period, it will have reached a temperature between 24-190° C. When the wafer has cooled after the predetermined time period, the wafer is then moved to a deposition chamber where several overlayers are deposited. In one embodiment, a free layer  115  is deposited on the intermediate structures. Suitable free layers may include a multi-layer comprising Co Fe, NiFe and CoFeB. At the time of deposition, free layer  115  is amorphous. 
     After free layer  115  is deposited, a capping layer  117  such as a layer of Ta/Ru may be provided on the wafer. Next, a top shield  119  is placed on the capping layer  117  to complete the MTJ structure. In certain embodiments, top shield  119  and bottom shield  105  may comprise a NiFe layer. The wafer containing the MTJ  100  may then be annealed at a temperature ranging from 260-300° C. 
     In certain embodiments, MTJs formed using the methods disclosed herein exhibited increased magnetoresistance ratios (MR ratios) without increasing the thickness of the MgO layer  113 .  FIG. 2  is a graph of the MR ratio versus RA (resistance-area product) for two different wafers. Curve  22  corresponds to a wafer processed with one of the novel methods of the present disclosure, in which a wafer is maintained in a holding chamber of a vacuum processing system for 30 minutes after annealing tunnel barrier layer  113 . Curve  24  represents devices processed in accordance with embodiments that omitted cooling. 
     Curve  24  of  FIG. 2  illustrates that as the RA increased, the MR ratio also increased for a prior process where cooling was not used. However, by introducing a 30-minute waiting time, during which stack  50  is allowed to cool to a temperature between 24-190° C., higher MR ratios may be obtained in certain embodiments of the disclosure.  FIG. 2 , illustrates results achieved in some embodiments where magnetic devices demonstrated MR Ratios greater than or equal to 110 times the resistance-area product of the MTJ. For RA (resistance-area product) values between 0.55 and 0.85 Ωμm 2 , some MTJs were produced having MR ratios between 60% and 90%. 
       FIG. 3  illustrates the MR ratios obtained for magnetic devices processed in accordance with another embodiment of the disclosure, where the RA is maintained at approximately 0.54 Ωμm 2 . In  FIG. 3 , the MR ratio of devices fabricated with different waiting periods in the holding chamber were measured. In some embodiments, as the waiting times increased, the magnetic devices demonstrated increased MR ratios, approaching saturation at around a 25 minute waiting time. 
     The introduction of a waiting period after annealing the tunnel barrier layer also benefited devices that were annealed over a broad temperature range.  FIG. 4  is a graph of MR ratio versus RA at different annealing temperatures. The MR ratios of magnetic devices manufactured with three different processes were measured and plotted in  FIG. 4 . Two MTJs were fabricated in accordance with embodiments of the novel process of the disclosure, while the third MTJ was fabricated with a prior process that omitted cooling. In one embodiment of the disclosure, wafers annealed at 155° C. and then cooled for 30 minutes experienced a steady increase in MR ratios. In other embodiments, enhanced MR ratios were observed for wafers manufactured with RAs as low as 0.50 Ωμm 2 . The MTJs having the higher MR ratios correspond to stacks  50  that were annealed at temperatures ranging from 155° C. to 200° C., and then placed in a holding chamber for a period of 30 minutes. By contrast, MTJs with tunnel barrier layers that were annealed at a fixed temperature, without being cooled at ambient temperature, displayed lower MR ratios. 
     By contrast, MTJs with tunnel barriers that were annealed at a fixed temperature, without being cooled at ambient temperature, displayed lower MR ratios. Thus,  FIG. 4  illustrates improved MR ratios for magnetic devices fabricated in accordance with several embodiments of the disclosure. Consequently, for a given RA, the MR ratio is shown to vary based on the temperature at which the tunnel barrier layer is annealed. 
     After top shield  119  has been deposited on capping layer  117 , stack  100  may then be annealed at a temperature ranging from 260-300° C. This second annealing changes the free layer from an amorphous state to a crystallized state. 
     With area densities of TMR heads gradually increasing, a read head that reduces junction resistance or resistance-area product (RA), while maintaining relatively high MR ratios is desirable in order to increase the reading data rate and decrease noise levels. The novel process described in the Detailed Description above, can provide a method for attaining higher MR ratios at lower junction resistance or resistance areas (RA) without having to increase the junction barrier thickness. 
     The above detailed description is provided to enable any person skilled in the art to practice the various embodiments described herein. While several embodiments have been described, it should be understood that these are for illustration purposes only and should not be taken as limiting the scope of the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art. Thus, many changes and modifications may be made to the embodiments, by one having ordinary skill in the art, without departing from the spirit and scope of the invention.