Abstract:
A step-up rectifier circuit includes first and second input terminals for applying AC outputs of opposite polarities, a third input terminal connected between the first and second input terminals, a plurality of rectifier elements connected between the third input terminal and a first output terminal, a plurality of output capacitors connected parallel to the rectifier elements, a second output terminal connected to a node between said output capacitors, a plurality of first capacitors connected between nodes between those of said rectifying elements located between the first output terminal and the second output terminal and a plurality of second capacitors connected between nodes between those of the rectifying elements which are between the second output terminal and the third input terminal, wherein the ratio between the capacitance of the first capacitors and the second capacitors is defined such that the ratio between the output voltages at individual output terminals can be made constant, regardless of whether they are loaded or unloaded.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a step-up rectifier circuit and, as disclosed herein, to a step-up rectifier circuit which multiplies the input voltage and can generate different output voltages and currents at a plurality of output terminals, by using a plurality of diodes and a plurality of capacitors. 
     DESCRIPTION OF THE PRIOR ART 
     As is well-known in the art, a step-up rectifier circuit constructed with a plurality of diodes and capacitors usually has a high internal impedance. As a result, the step-up rectifier circuit has the defect that the output voltage varies widely with changes in load. When an output voltage is provided from an intermediate portion of the rectifier circuit, it has a very strong influence upon the voltage at another output terminal, so that it is difficult to keep the ratio of two voltages at a constant regardless of the load condition. As a result, it is impossible for the step-up rectifier circuit to stabilize individual output voltages when the rectifier circuit is made to generate multiple outputs. 
     SUMMARY OF THE INVENTION 
     An object of this invention is, therefore, to provide a step-up rectifier circuit in which the ratio between the output voltages at individual output terminals can be made constant, regardless of the load conditions, and which can readily generate sufficiently stabilized output voltages at the individual output terminals. 
     Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned from the practice of the invention. The objects and advantages may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims. 
     In order to achieve the objects of the present invention as embodied and broadly described herein, a step-up rectifier circuit is provided for multiplying the input voltage applied to said rectifier circuit, comprising first and second input terminals for supplying AC inputs of opposite polarities, a third input terminal connected between said first and second input terminals, rectifier means provided with a plurality of rectifying elements connected in series with said third input terminal and aligned in the same direction of rectification, a plurality of series-connected output capacitors having one end connected to said third input terminal and connected in parallel to said plurality of rectifying elements, a first output terminal connected to the other end of said series-connected output capacitors, a second output terminal connected to a node between said output capacitors, a plurality of first capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said first output terminal and said second output terminal, and a plurality of second capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said second output terminal and said third input terminal, wherein the ratio between the total capacitance C A  of said first capacitors and the total capacitance C B  of said second capacitors is defined by the following equation: ##EQU1## in which I 1  designates the current flowing through the first output terminal, I 2  designates the sum of the currents flowing through said first output terminal and said second output terminal, n 1  designates one half of the number of said first capacitors, and n 2  designates one half of the number of said second capacitors. 
     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of one embodiment of the step-up rectifier circuit constructed according to the present invention; 
     FIG. 2 is a circuit diagram used to explain the operation of the embodiment of the present invention; 
     FIG. 3 is a circuit diagram of another embodiment of the step-up rectifier circuit constructed according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be described in connection with two embodiments thereof, and with reference to the accompanying drawings. 
     In FIG. 1, AC power supply A is connected to the primary winding n 1  of a transformer T. The secondary winding n 2  of this transformer T is provided with a middle tap m. Two terminals a, b of the secondary winding n 2  and the middle tap m of the transformer provide first to third input terminals, so that AC inputs of opposite polarities are supplied to the two terminals a,b of the secondary winding n 2 . The tap m, acting as the third input terminal, is grounded. A plurality of diodes D 1  to D 15  are connected in series between the tap m and a first output terminal P 1  so that their rectification directions are identical. More specifically, the anode of diode D 1  is connected to the tap m, and the cathode of diode D 15  is connected to the first output terminal P 1 . 
     A plurality of capacitors C 1  to C 5  are connected between one side a of the secondary winding n 2  of the transformer T acting as the first input terminal and predetermined nodes of the diodes D 1  to D 15 . More specifically, the capacitors C 1  and C 2  are connected in series between one side a of the secondary winding n 2  and the node j between diodes D 5  and D 6  ; and a node between the capacitors C 1  and C 2  is connected to the node f between diodes D 2   and D 3 . The capacitors C 3 , C 4  and C 5  are connected in series between one side a of the secondary winding n 2  and the node x between diodes D 14  and D 15 . The node between capacitors C 3  and C 4  is connected to the node n between diodes D 8  and D 9 , and the node between capacitors C 4  and C 5  is connected to the node u between diodes D 11  and D 12 . 
     Five output capacitors C 6  to C 10  are connected between the anode of diode D 1  and the cathode of diode D 15 . As shown, the node between capacitors C 6  and C 7  is connected to the node g between diodes D 3  and D 4 , and the node between capacitors C 7  and C 8  is connected to the node k between diodes D 6  and D 7 . The node between capacitors C 8  and C 9  is connected to the node s between diodes D 9  and D 10 , and the node between capacitors C 9  and C 10  is connected to the node v between diodes D 12  and D 13 . 
     A plurality of capacitors C 11  to C 15  are connected between the other side b of the secondary winding n 2  of the transformer T, which acts as a second input terminal, and predetermined nodes between diodes D 1  to D 15 . More specifically, capacitors C 11  and C 12  are connected in series between the other side b of the secondary winding n 2  and the node h between diodes D 4  and D 5 . The node between these capacitors C 11  and C 12  is connected to the node e between diodes D 1  and D 2 . The capacitors C 13 , C 14  and C 15  are connected in series between the other side b of the secondary winding n 2  and the node w between diodes D 13  and D 14 . Of these, the node between capacitors C 13  and C 14  is connected to the node l between diodes D 7  and D 8 , and the node between capacitors C 14  and C 15  is connected to the node t between diodes D 10  and D 11 . 
     To provide a general explanation, the following designations are made for the construction described above. The current output from the first output terminal P 1  is designated by i 1  (A); the current output from a node P 2  (which will be referred to as the &#34;second output terminal P 2  &#34;) between capacitors C 7  and C 8  is designated by i 2  (A); the number of circuit steps between the grounded portion and the second output terminal P 2  (i.e., the number of capacitors connected between the nodes between rectifying elements located between the tap m and the second output terminal P 2  and the first input terminal a or the second input terminal b) is designated by N 2 , wherein N 2  =2 in FIG. 1; the number of steps between the output terminal P 2  and the output terminal P 1  (i.e., the number of capacitors connected in series between the nodes between the rectifying elements located between the output terminal P 2  and P 1  and the first or second input terminal) is designated by N 1  , wherein N 1  =3 in FIG. 1; the voltage between the grounded portion and the output terminal P 2  is designated by E 2  (V); the voltage between the output terminal P 2  and the output terminal P 1  is designated by E 1  (V); the secondary voltage of the transformer T is designated by E 0  (V); and the frequency of the power supply is designated by F(=1/T) (HZ). The capacitances of the capacitors C 1 , C 2 , C 6 , C 7 , C 11  and C 12 , constituting the circuit from the grounded portion to the output terminal P 2 , are designated by C B  (F), and the capacitances of the capacitors C 3  to C 5 , C 8  to C 10  and C 13  to C 15 , constituting the circuit from the output terminal P 2  to the output terminal P 1 , are designated by C A  (F). 
     If this circuit is operated with a full output but zero current, i.e., under no load, the voltages E 1  and E 2  are expressed by the following equations: 
     
         E.sub.1 =2N.sub.1 E.sub.0                                  (1) 
    
     
         E.sub.2 =2N.sub.2 E.sub.0                                  (2) 
    
     Before the steps of deducing the above equation are explained, the operation of the circuit described above will be described in the following. 
     First, the other side b of its secondary winding n 2  is at a voltage of -E 0  /2 with respect to ground potential. In this case, diode D 1  is turned on so that capacitor C 11  is charged to a voltage E 0  /2, in the direction such that its node e becomes positive, by a current which flows through node m, diode D 1 , node e, capacitor C 11  and the output terminal b. Next, the one side a of the secondary winding n 2  is at a voltage of -E 0  /2 with respect to ground potential. In this case, diode D 2  is turned on so that capacitor C 1  is charged to a voltage 3/2E 0  which is the sum of the output voltage E 0  of the secondary winding and the charged voltage E 0  /2, in the direction such that node f becomes positive, by a current which flows through the output terminal b, capacitor C 11 , node e, diode D 2 , node f, capacitor C 1  and terminal a. 
     Next, the output terminal b of the secondary winding is at a voltage of -E 0  /2. In this case, diode D 3  is turned on so that capacitor C 6  is charged to a voltage of 2E 0  which is the sum of the output voltage E 0  /2 between the terminal a and node m of secondary winding and the charged 3/2E 0  of capacitor C 1 , in the direction such that node g becomes positive, by a current which flows through the output terminal a, capacitor C 1 , node f, diode D 3 , capacitor C 6  and node m. At the same time when the diode D 3  is turned on, the diode D 4  is turned on so that capacitor C 12  is charged to a voltage of 2E 0  which is the sum of the output voltage E 0  of the secondary winding, the charged 3/2E 0  of capacitor C 1  and the charged -E 0  /2 (a charge direction which is the reverse of that at the capacitor C 12 ) of capacitor C 11 , in the direction such that node h becomes positive, by a current which flows through node m, terminal a, capacitor C 1 , diode D 3 , diode D 4 , capacitor C 12 , capacitor C 11  and the terminal b. 
     Next, the output terminal b of the secondary winding is at a voltage of E 0  /2. In this case, the diode D 5  is turned on so that capacitor C 2  is charged to a voltage of 2E 0  which is the sum of the output voltage E 0  of the secondary winding, the charged voltage E 0  /2 of capacitor C 11 , the charged voltage of 2E 0  of capacitor C 12  and the charged voltage -3/2E 0  of capacitor C 1 , in the direction such that node j is positive, by a current which flows through the secondary winding n 2 , capacitor C 11 , capacitor C 12 , diode D 5 , capacitor C 2 , and capacitor C 1 . Next, the output terminal a of the secondary winding is at a voltage of E 0  /2. In this case, the diode D 6  is turned on so that capacitor C 7  is charged to a voltage of 2E 0  which is the sum of the output voltage E 0  /2 between the terminal a and node m of secondary winding n 2 , the charged voltage 3/2E 0  of capacitor C 1 , the charged voltage 2E 0  of capacitor C 2  and the charged voltage -2E 0  of capacitor C 6 , in the direction such that node k becomes positive, by a current which flows through terminal a, capacitor C 1 , capacitor C 2 , diode D 6 , capacitor C 7 , capacitor C 6  and node m. 
     At the same time the diode D 7  is turned on so that capacitor C 13  is charged to a voltage of 9/2E 0  which is the sum of the output voltage E 0  of secondary winding n 2 , the charge voltages 3/2E 0  of capacitor C 1  and the charged voltage 2E 0  of capacitor C 2 , in the direction such that node l becomes positive, by a current which flows through the secondary winding n 2 , capacitors C 1 , C 2 , diode D 6 , D 7 , and capacitor C 13 . 
     Next, the terminal b of the secondary winding n 2  is at a voltage of E 0  /2. In this case, diode D 8  is turned on so that capacitor C 3  is charged to a voltage of 11/2E 0  which is the sum of the output voltage E 0  of the secondary winding n 2  and the charged voltage 9/2E 0  of capacitor C 13 , in the direction such that node n becomes positive, by a current which flows through the secondary winding n 2 , capacitor C 13 , diode D 8  and capacitor C 3 . Next, the terminal a of the secondary winding is at a voltage of E 0  /2. In this case, diode D 9  is turned on so that capacitor C 8  is charged to a voltage of 2E 0  which is the sum of the output voltage E 0  /2 between the terminal a and node m, the charged voltage 11/2E 0  of capacitor C 3  and the charged voltage -2E 0 , -2E 0  of capacitor C 7  and C 6 , respectively, in the direction such that node s becomes positive, by a current which flows through node m, terminal a, capacitor C 3 , diode D 9  and capacitors C 8 , C 7 , C 6 . 
     At the same time, diode D 10  is turned on. In this case, capacitor C 14  is charged to a voltage of 2E 0  which is the sum of the output voltage E 0  of the secondary winding n 2  the charged voltage 11/2E 0  of capacitor C 3  and the charged voltage -9/2E 0  of capacitor C 13 , in the direction so that node t becomes positive, by a current which flows through the secondary winding n 2 , capacitor C 3 , diodes D 9 , D 10 , and capacitors C 14 , C 13 . 
     Next, the terminal b of the secondary winding n 2  is at a voltage E 0  /2. In this case, the diode D 11  is turned on so that a capacitor C 4  is charged to a voltage of 2E 0  which is the sum of the voltage E 0  of the secondary winding n 2 , charged voltages 9/2E 0 , 2E 0  of capacitors C 13 , C 14 , and the charged voltages -11/2E 0  of capacitor C 3 , in the direction such that node u becomes positive, by a current which flows through the secondary winding n 2 , capacitors C 13 , C 14 , diode D 11 , and capacitors C 4 , C 3 . 
     Next, the terminal a is positive. In this case, diode D 12  and diode D 13  are turned on. As a result, capacitor C 9  is charged to a voltage 2E 0  which is the sum of the output voltage E 0  /2 between the terminal a and node m, the charged voltages 11/2E 0 , 2E 0  of capacitors C 3 , C 4  and the charged voltages -2E 0 , -2E 0 , -2E 0  of capacitors C 8 , C 7 , C 6 , in the direction such that node v becomes positive, by a current which flows through node m, terminal a, capacitors C 3 , C 4 , diode D 12 , capacitors C 9 , C 8 , C 7 , C 6 . At the same time, capacitor C 15  is charged to a voltage 2E 0  which is the sum of the voltage E 0  of the secondary winding n 2 , the charged voltages 11/2E 0 , 2E 0  of capacitors C 3 , C 4  and the charged voltages -2E 0 , -9E 0  of capacitor C 14 , C 13 , in the direction such that node w is positive, by a current which flows through the secondary windings n 2 , capacitors C 3 , C 4 , diodes D 12 , D 13  and capacitors C 15 , C 14 , C 13 . 
     Next, the terminal b of the secondary winding is positive. In this case, diode D 14  is turned on so that a capacitor C 5  is charged to a voltage 2E 0  which is the sum of the output voltage E 0  of the secondary winding n 2 , the charged voltage 9/2E 0 , 2E 0 , 2E 0  of capacitors C 13 , C 14 , C 15  and the charged voltage -2E 0 , -11/2E 0  of capacitors C 4 , C 3 , in the direction such that node x is positive, by a current which flows through the secondary winding n 2 , capacitors C 13 , C 14 , C 15 , diode D 14  and capacitors C 5 , C 4 , C 3 . Next, the terminal a is positive. In this case, the diode D 15  is turned on so that capacitor C 10  is charged to a voltage 2E 0  which is the sum of the output voltage E 0  /2 between terminal a and node m, the charged voltages 11/2E 0 , 2E 0 , 2E 0  of capacitors C 3 , C 4 , C 5  and the charged voltages -2E 0 ,-2E 0 , -2E 0 , -2E 0  of capacitors C 9 , C 8 , C 7 , C 6 , in the direction such that the output terminal is positive, by a current which flows through node m, terminal a, capacitors C 3 , C 4 , C 5 , diode D 15  and capacitors C 10 , C 9 , C 8 , C 7 , C 6 . 
     As described above, each of the output capacitors C 6  to C 10  is charged to voltage 2E 0  which is twice the output voltage E 0  of the secondary winding n 2 . The voltages E 1  and E 2  are obtained by summing the voltages on the capacitors C 6  and C 7  for voltage E 2 , and capacitors C 8  to C 10  for voltage E 1 . Thus, the voltages obtained are as expressed in equations (1) and (2) above. 
     The equations (1) and (2) are formed under no load. When load current flows from the output terminals P 2  and P 1 , a voltage drop E d  is established, which will now be considered with reference to FIG. 2. 
     In FIG. 2, the mean value of the load current flowing during one period, T (=1/f) is designated by I (A), and the voltage drop which occurs during one period in an output capacitor of a capacity C (F) is designated by e 0  (V). The capacitances of the individual capacitors are assumed to be equal. 
     The following conditions (a) to (c) hold for FIG. 2: 
     (a) A load current flows through the output capacitors C 11 , C 12  and C 13  connected in series, so that each output capacitor produces an equal voltage drop e 0  of predetermined value. 
     (b) The voltage drops during one period generated in capacitors C 11 , C 12  and C 13  at the instant within that period at which a point a becomes positive are supplied by capacitors C 21 , C 22  and C 23  (i.e., they are charged to compensate for discharges due to the current flows). 
     (c) The voltage drops during one period, generated in capacitors C 21 , C 22  and C 23  at the instant within that period at which a point b becomes positive are supplied by capacitors C 31 , C 32  and C 33 . 
     As a result, the voltage drops in the individual capacitors during one period are as follows: 
     C 11 , C 12  and C 13  : e 0 , 
     C 21  : e 0  (i.e., the voltage drop due to the supply of C 11 ). 
     C 31  : e 0  (i.e., the voltage drop due to the supply of C 21 ) 
     C 22  : 2e 0 , (i.e., the voltage drop due to the supply of C 12  and C 31 ) 
     C 32  : 2e 0 , (i.e., the voltage drop due to the supply of C 22 ) 
     C 23  : 3e 0 , (i.e. the voltage drop due to the supply of C 13  and C 32 ), and 
     C 33  : 3e 0 , (i.e. the voltage drop due to the supply of C 23 ). 
     The total voltage drops are the sums of the voltage drops in the individual capacitors and are as follows: 
     C 33  : 3e 0 , C 23  : 6e 0 , C 32  : 8e 0 , C 22  : 10e 0 , C 31  : 11e 0 , and C 21  : 12e 0 . 
     The output capacitor C 11  is supplied by the capacitor C 21  so that its voltage drop after the current supply is 12e 0 . 
     Similarly output capacitors C 12  and C 13  have voltage drops of 10e 0  and 6e 0 , respectively. 
     The values of the voltage drops in the output capacitors C 11 , C 12  and C 13  can be broken down as follows: 
     C 11  : (2×3+2×2+2×1)e 0 , 
     C 12  : (2×3+2×2)e 0 , and 
     C 13  : (2×3)e 0 . 
     In the above three equations, the underlined numerals 3 correspond to the number of capacitors C 21 , C 22  and C 23 , or C 31 , C 32  and C 33  connected between point a or b and nodes between rectifying elements. Therefore, if the number of capacitors connected between point a or b and nodes between rectifying elements is generally designated by n, the voltage drops in the voltage capacitors can be expressed by the following equations: 
     
         C.sub.11 :{2n+2×(n-1)+2×(n-2)}e.sub.0          (a), 
    
     
         C.sub.12 :{2n+2×(n-1)}e.sub.0                        (b), and 
    
     
         C.sub.13 : 2n e.sub.0                                      (c). 
    
     The total voltage drop resulting from the flow of the load current is the sum of the voltage drops in the individual capacitors. Generally speaking, therefore, the total voltage drop E d  is expressed by the following equation when there are three output capacitors: 
     
         E.sub.d ={2n×3+2(n-1)(3-1)+2(n-2)(3-2)}e.sub.0, 
    
     wherein 
     the underlined numerals 3 designate the number of output capacitors. 
     If the number of capacitors connected between point a or b and nodes between rectifying elements is designated by n, the total voltage drop in the output capacitors is expressed by the following equation when the voltage drops expressed by Equations (a), (b) and (c) are extended to the case of a number n of output capacitors: 
     
         E.sub.d ={2n.sup.2 +2(n-1).sup.2 +2(n-2).sup.2 +2(n-3).sup.2 . . . }e.sub.0. 
    
     This equation can be rewritten in the following form: ##EQU2## 
     In above equation (3), 
     
         e.sub.0 =Q/c=IT/c=1/C.sub.f 
    
     As a result, the voltage drop E d , when the load voltage is applied at the output, is expressed by the following equation: 
     
         E.sub.d =(2/3n.sup.3 +n.sup.2 +1/3n)I/C.sub.f              (4), 
    
     wherein: 
     n: number of steps in step-up rectifier circuit, 
     I: load current (A), 
     C: capacitance of capacitors (F), and 
     f: frequency of input power supply (Hz). 
     Therefore, the voltage drop E 1d  in the voltage E 1  is expressed by the following equation: 
     
         E.sub.1d =(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.Af (5), 
    
     wherein 
     I 1  =i 1 . 
     On the other hand, the voltage drop E 2d  in the voltage E 2  is expressed by the following equation, because the voltage drop due to the current i 1  is added to the voltage drop due to the current i 2  : 
     
         E.sub.2d =(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.Bf (6), 
    
     wherein 
     I 2  =i 1  +i 2 . 
     From the above, if the voltage at output terminal P 2  (FIG. 1) under load is designated by E 2 , and if the voltage from output terminal P 2  to output terminal P 1  is designated E 1 , voltages E 1  and E 2  are expressed by the following equations: 
     
         E.sub.1 =2n.sub.1 E.sub.0 -(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.Af                             (7), 
    
     and 
     
         E.sub.2 =2n.sub.2 E.sub.0 -(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.Bf                             (8). 
    
     If the secondary voltage E 0  of the transformer T is charged to E 0 .spsb.&#39; to compensate for the voltage drop in voltage E 1 , the following relationship is obtained from Equations (1) and (7): 
     
         2N.sub.1 E.sub.0 =2N.sub.1 E.sub.0.spsb.&#39; -(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.Af 
    
     
         E.sub.0.spsb.&#39; =E.sub.0 +1/2N.sub.1 ×(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)1/C.sub.Af                    (9) 
    
     When the secondary voltage of the transformer T is designated by E 0 .spsb.&#39;  (V), the following equation can be deduced from equations (2) and (8), if the voltage E 2  at output terminal P 2  returns to a non-loaded voltage: 
     
         2N.sub.2 E.sub.0 =2N.sub.2 E.sub.0.spsb.&#39; -(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.Bf             (10) 
    
     The following equation can be deduced from Equation (9) and (10): 
     
         n.sub.2 /n.sub.1 ×(2/3n.sub.1.spsb.3 +n.sub.1.spsb.2 +1/3n.sub.1)I.sub.1 /C.sub.A -(2/3n.sub.2.spsb.3 +n.sub.2.spsb.2 +1/3n.sub.2)I.sub.2 /C.sub.B =0                           (11) 
    
     Equation (11) can be rewritten in the following form: ##EQU3## 
     From the above, it can be understood that the voltage at the output terminal P 2  can be stabilized if the ratio of the total capacitances of the capacitors used satisfied equation (12), and if stabilization is conducted by the voltage at the terminal P 1 . 
     According to the embodiment thus far described, the capacitances of the capacitors constituting the step-up rectifier circuit are set according to both the magnitudes of output currents relating to the capacitors on the basis of equation (12), and the number of voltage-multiplication steps in the sections relating to those currents. As a result, if the voltage at the terminal side, i.e., output terminal P 1 , is stabilized; the voltage at the middle point, i.e., output terminal P 2 , can be stabilized so that a plurality of output voltages can be stabilized. 
     Another embodiment of the present invention will be described in FIG. 3, where components identical to those in FIG. 1 are indicated by the same reference characters. 
     As shown in FIG. 3, one terminal of each of capacitors C 1  and C 2  is connected to the node between diodes D 2  and D 3  and the node between diodes D 5  and D 6 , respectively, and the other terminals thereof are connected to terminal a of the secondary winding n 2  of the transformer T. One terminal of each of capacitors C 11  and C 12  is connected to the node between diodes D 1  and D 2  and the node between diodes D 4  and D 5 , respectively, and the other terminals thereof are connected to the other terminal b of the secondary winding n 2  of the transformer T. An output which has a voltage to ground of E 3  (V) and a current i 3  (A) is obtained from a node P 3  (which will be referred to as the &#34;output terminal P 3  &#34;) between capacitors C 6  and C 7 . The remainder of the circuit of FIG. 3 is constructed in the same manner as the corresponding components shown in FIG. 1. 
     With this structure the output terminals P 1  and P 2  can be handled in exactly the same way as in the foregoing embodiment, and similar operations may be conducted for output terminals P 2  and P 3  by substituting the relationships of I 1  =i 1  +i 2  and I 2  =i 1  +i 2  +i 3 . Effects similar to those of the foregoing embodiment can be obtained by these substitutions. 
     By using this concept, moreover, the individual output voltages from a circuit with three or more output terminals can be stabilized. 
     In the embodiments thus far described, the description has concerned the case in which the secondary winding of a transformer provided with a tap is used as first to third input terminals to which an AC voltage is applied. The present invention can also be exemplified by a structure in which the first to third input terminals are connected to an AC power supply directly, i.e., not through a transformer.