Abstract:
Provided is a battery device for controlling charge/discharge of a secondary battery by a single bidirectionally conductive field effect transistor, a charge/discharge control circuit with which a leakage current of the bidirectionally conductive field effect transistor is reduced to perform stable operation. The charge/discharge control circuit includes: a switch circuit for controlling a gate of the bidirectionally conductive field effect transistor based on an output of a control circuit for controlling the charge/discharge of the secondary battery; and two MOS transistors for preventing back-flow of a charge current and a discharge current. The first MOS transistor has a drain and a back gate which are connected to each other, and a source connected to a drain of the bidirectionally conductive field effect transistor. The second MOS transistor has a drain and a back gate which are connected to each other, and a source connected to a source of the bidirectionally conductive field effect transistor.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2010-201124 filed on Sep. 8, 2010, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a charge/discharge control circuit for detecting a voltage and an abnormality of a secondary battery and to a battery device including the charge/discharge control circuit, and more particularly, to a charge/discharge control circuit capable of control by a single charge/discharge control MOSFET and to a battery device including the charge/discharge control circuit. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 5  illustrates a circuit diagram of a battery device including a conventional charge/discharge control circuit. In the battery device including the conventional charge/discharge control circuit, an enhancement mode N-channel MOSFET  306  capable of bidirectional energization/interruption is connected in series to a negative terminal of a secondary battery  101 . A charge circuit or a load is connected to terminals  120  and  121 , and a charge/discharge current is supplied or discharged to or from the secondary battery  101  via the terminals  120  and  121 . A control circuit  102  detects a voltage of the secondary battery  101  and a voltage of the enhancement mode N-channel MOSFET  306 , and controls ON/OFF of switches  301 ,  304 , and  305  based on the detected values. When a potential of a gate terminal of the enhancement mode N-channel MOSFET  306  is equal to or higher than a positive threshold voltage, the enhancement mode N-channel MOSFET  306  provides bidirectional energization between the drain terminal and the source terminal thereof. When the potential of the gate terminal is lower than the threshold voltage, the enhancement mode N-channel MOSFET  306  enters the OFF state between the drain terminal and the source terminal. 
         [0006]    A charge-inhibited state is described. When a charger is connected between the terminals  120  and  121 , a voltage Vds between the drain terminal and the source terminal of the enhancement mode N-channel MOSFET  306  has a positive value. The control circuit  102  detects that the voltage Vds is positive, and turns ON the switch  301  and OFF the switches  305  and  304 . Accordingly, the gate terminal of the enhancement mode N-channel MOSFET  306  has a voltage higher than that of the source terminal thereof by the voltage of the secondary battery  101 , with the result that the enhancement mode N-channel MOSFET  306  enters the energized state. 
         [0007]    When the secondary battery  101  is charged and the battery voltage reaches a set upper limit value, the control circuit  102  turns OFF the switch  301  and ON the switches  305  and  304 . Then, the gate terminal of the enhancement mode N-channel MOSFET  306  has the same potential as that of the source terminal thereof, with the result that the enhancement mode N-channel MOSFET  306  enters the OFF state. As a result, the charge current is interrupted to prevent overcharge of the secondary battery  101 . Further, at this time, a diode  302  is reverse-biased to prevent the current from flowing through the switch  304  and the switch  305 . 
         [0008]    When the charge current is interrupted, no voltage drop by internal resistance occurs and the voltage of the secondary battery  101  reduces. In order to prevent the re-start of charge in response to the voltage reduction, after the charge is inhibited, the charge-inhibited state is maintained until the secondary battery  101  is discharged to some extent to have a voltage that is equal to or lower than a set value. Under the charge-inhibited state, if a load is connected between the terminals  120  and  121 , the voltage Vds is switched from positive to negative. The control circuit  102  is thus configured to control the switches  301 ,  304 , and  305  so that the secondary battery  101  may be discharged when the voltage Vds is negative and that the charge current may be interrupted when the voltage Vds is positive. 
         [0009]    In the above description, the switches  304  and  305  are both turned ON at the time of the stop of charge. However, the charge can be stopped similarly even if the switch  304  is turned OFF. The first reason is that the switch  305  is ON regardless of ON/OFF of the switch  304 , and hence the gate terminal of the enhancement mode N-channel MOSFET  306  has the same potential as that of the source terminal thereof and the enhancement mode N-channel MOSFET  306  thus enters the OFF state. The second reason is that the diode  302  also interrupts the current flowing through the switches  304  and  305 . 
         [0010]    Note that, the switches  304  and  305  are both OFF at the time of the charge described above and at the time of the discharge to be described later. Accordingly, if the switches  304  and  305  are both turned ON at the time of the stop of charge and the switches  304  and  305  are both turned ON also at the time of the stop of discharge as described later, the two switches are turned ON or OFF simultaneously all the time. It is therefore not necessary to control the switches  304  and  305  independently, which can simplify the configuration of the control circuit  102 . 
         [0011]    Next, a discharge-inhibited state is described. When a load is connected between the terminals  120  and  121 , the voltage Vds between the drain terminal and the source terminal of the enhancement mode N-channel MOSFET  306  has a negative value. The control circuit  102  detects that the voltage Vds is negative, and turns ON the switch  301  and OFF the switches  304  and  305 . Accordingly, the gate terminal of the enhancement mode N-channel MOSFET  306  has a voltage higher than that of the drain terminal thereof by the voltage of the secondary battery  101 , with the result that the enhancement mode N-channel MOSFET  306  enters the energized state. 
         [0012]    When the discharge of the secondary battery  101  progresses and the battery voltage reaches a set lower limit value, the control circuit  102  turns OFF the switch  301  and ON the switches  304  and  305 . Then, the gate terminal of the enhancement mode N-channel MOSFET  306  has the same potential as that of the drain terminal thereof, with the result that the enhancement mode N-channel MOSFET  306  enters the OFF state. As a result, the discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Further, at this time, a diode  303  is reverse-biased to prevent the current from flowing through the switch  304  and the switch  305 . 
         [0013]    When the discharge current is interrupted, no voltage drop by internal resistance occurs and the voltage of the secondary battery  101  increases. In order to prevent the re-start of discharge in response to the voltage increase, after the discharge is inhibited, the discharge-inhibited state is maintained until the secondary battery  101  is charged to some extent to have a voltage that is equal to or higher than a set value. Under the discharge-inhibited state, if the charge circuit is connected between the terminals  120  and  121 , the voltage Vds is switched from negative to positive. The control circuit  102  is thus configured to control the switches  301 ,  304 , and  305  so that the secondary battery  101  may be charged when the voltage Vds is positive and that the discharge current may be interrupted when the voltage Vds is negative. 
         [0014]    In the above description, the switches  304  and  305  are both turned ON at the time of the stop of discharge. However, the discharge can be stopped similarly even if the switch  305  is turned OFF. The first reason is that the switch  304  is ON regardless of ON/OFF of the switch  305 , and hence the gate terminal of the enhancement mode N-channel MOSFET  306  has the same potential as that of the drain terminal thereof and the enhancement mode N-channel MOSFET  306  thus enters the OFF state. The second reason is that the diode  303  also interrupts the current flowing through the switches  305  and  304 . 
         [0015]    Note that, if the switches  304  and  305  are both turned ON at the time of the stop of discharge, as described above, the two switches are turned ON or OFF simultaneously all the time. It is therefore not necessary to control the switches  304  and  305  independently, which can simplify the configuration of the control circuit  102 . 
         [0016]    The enhancement mode N-channel MOSFET  306  has built-in diodes  321  and  322  formed therein. However, the diodes  321  and  322  are connected in series in opposite directions and hence are not electrically connected to each other, which has no influence on the protection operation described above. 
         [0017]    The enhancement mode N-channel MOSFET  306  may be of either a lateral structure or a vertical structure. In the case of the lateral structure, it is easy to form the enhancement mode N-channel MOSFET  306  and the control circuit  102  as a single IC. Therefore, the reduction in size and cost can be achieved because the overcharge/overdischarge protection circuit, which has heretofore been formed by a single IC and two switches, can be formed by a single IC. On the other hand, in the case of the vertical structure, the reduction in loss can be achieved as compared to the lateral structure (see, for example, Japanese Patent Application Laid-open No. 2000-102182 (FIG. 9)). 
         [0018]    The conventional technology, however, has a problem that the gate voltage of the enhancement mode N-channel MOSFET  306  can be reduced to no more than the source or drain voltage plus VF (about 0.6 V), and hence a leakage current is large when the enhancement mode N-channel MOSFET  306  is OFF. Further, the back gate of the enhancement mode N-channel MOSFET  306  becomes a floating state, leading to another problem of unstable operation of the battery device including the charge/discharge control circuit. 
       SUMMARY OF THE INVENTION 
       [0019]    The present invention has been made in order to solve the above-mentioned problems, and provides a charge/discharge control circuit capable of stable operation by reducing a leakage current flowing when the charge/discharge control circuit is OFF, and also provides a battery device including the charge/discharge control circuit. 
         [0020]    In order to solve the conventional problems, a battery device including a charge/discharge control circuit according to the present invention has the following configuration. 
         [0021]    The present invention provides a charge/discharge control circuit for controlling charge/discharge of a secondary battery by a single bidirectionally conductive field effect transistor, the charge/discharge control circuit including: a control circuit connected to both ends of the secondary battery, for monitoring a voltage of the secondary battery; a switch circuit including a first terminal and a second terminal, for controlling a gate of the bidirectionally conductive field effect transistor based on an output of the control circuit; a first transistor including a drain connected to a drain of the bidirectionally conductive field effect transistor, and a source and a back gate which are connected to the first terminal of the switch circuit; and a second transistor including a drain connected to a source of the bidirectionally conductive field effect transistor, and a source and a back gate which are connected to the first terminal of the switch circuit. 
         [0022]    According to the battery device including the charge/discharge control circuit of the present invention, the leakage current can be reduced by controlling the gate of the bidirectionally conductive field effect transistor to a source voltage or a drain voltage thereof. Besides, the present invention provides the effect that the bidirectionally conductive field effect transistor can be operated stably by controlling the back gate of the bidirectionally conductive field effect transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    In the accompanying drawings: 
           [0024]      FIG. 1  is a circuit diagram of a battery device including a charge/discharge control circuit according to a first embodiment of the present invention; 
           [0025]      FIG. 2  is a circuit diagram of a battery device including a charge/discharge control circuit according to a second embodiment of the present invention; 
           [0026]      FIG. 3  is a circuit diagram of a battery device including a charge/discharge control circuit according to a third embodiment of the present invention; 
           [0027]      FIG. 4  is a circuit diagram of a battery device including a charge/discharge control circuit according to a fourth embodiment of the present invention; 
           [0028]      FIG. 5  is a circuit diagram of a battery device including a conventional charge/discharge control circuit; 
           [0029]      FIG. 6  is a circuit diagram of a battery device including a charge/discharge control circuit according to a fifth embodiment of the present invention; and 
           [0030]      FIG. 7  is a circuit diagram of a battery device including a charge/discharge control circuit according to a sixth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0031]    Referring to the accompanying drawings, embodiments of the present invention are described below. 
       First Embodiment 
       [0032]      FIG. 1  is a circuit diagram of a battery device including a charge/discharge control circuit  151  according to a first embodiment of the present invention. 
         [0033]    The battery device including the charge/discharge control circuit  151  of this embodiment includes a secondary battery  101 , a control circuit  102 , an N-channel bidirectionally conductive field effect transistor  114 , external terminals  120  and  121  between which a charger  132  or a load  131  is to be connected, a PMOS transistor  110 , and NMOS transistors  111 ,  161 , and  162 . The PMOS transistor  110 , the NMOS transistor  111 , a terminal  124  (second terminal), and a terminal  125  (first terminal) together form a switch circuit  152 . 
         [0034]    The secondary battery  101  has both ends connected to a positive power supply terminal  122  and a negative power supply terminal  123 , respectively. The control circuit  102  is connected to the positive power supply terminal  122  as positive power supply and to the terminal  125  as negative power supply. The control circuit  102  has an output terminal  126  connected to a gate of the PMOS transistor  110  and a gate of the NMOS transistor  111 , an output terminal  127  connected to a gate of the NMOS transistor  162 , and an output terminal  128  connected to a gate of the NMOS transistor  161 . The PMOS transistor  110  has a source connected to the positive power supply terminal  122  and the external terminal  120  via the terminal  124 , and a drain connected to a drain of the NMOS transistor  111 . The NMOS transistor  111  has a source and a back gate which are connected to a source and a back gate of the NMOS transistor  161  and a source and a back gate of the NMOS transistor  162  via the terminal  125 . The NMOS transistor  111  has the drain also connected to a gate of the N-channel bidirectionally conductive field effect transistor  114 . The NMOS transistor  161  has a drain connected to the negative power supply terminal  123 . The NMOS transistor  162  has a drain connected to the external terminal  121 . The N-channel bidirectionally conductive field effect transistor  114  has a drain connected to the negative power supply terminal  123 , a source connected to the external terminal  121 , and a back gate connected to the terminal  125 . 
         [0035]    Next, an operation of the battery device including the charge/discharge control circuit  151  according to this embodiment is described. 
         [0036]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  is in a chargeable/dischargeable state, the output terminal  126  of the control circuit  102  outputs Low and the output terminals  127  and  128  thereof output High. Then, the PMOS transistor  110  is turned ON, the NMOS transistor  111  is turned OFF, the NMOS transistor  161  is turned ON, and the NMOS transistor  162  is turned ON. Then, the gate electrode of the N-channel bidirectionally conductive field effect transistor  114  is connected to the positive power supply terminal  122 , and the N-channel bidirectionally conductive field effect transistor  114  enters an ON state. This way, charge/discharge is performed. Here, the respective outputs of the control circuit  102  may be such that: the output terminals  126  and  128  output Low while the output terminal  127  outputs High; the output terminals  126  and  127  output Low while the output terminal  128  outputs High; or the output terminals  126 ,  127 , and  128  output Low. The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence a lower one of the voltage at the negative power supply terminal  123  and the voltage at the external terminal  121  can be output as Low. 
         [0037]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a charge-inhibited state, the output terminals  126  and  127  of the control circuit  102  output High and the output terminal  128  thereof outputs Low. Then, the PMOS transistor  110  is turned OFF, the NMOS transistor  111  is turned ON, the NMOS transistor  161  is turned OFF, and the NMOS transistor  162  is turned ON. Then, the gate of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  via the NMOS transistor  162 , the terminal  125 , and the NMOS transistor  111 . The N-channel bidirectionally conductive field effect transistor  114  then enters the OFF state. This way, a charge current is interrupted to prevent overcharge of the secondary battery  101 . Here, a parasitic diode  171  is reverse-biased to prevent the current from flowing from the negative power supply terminal  123  to the external terminal  121 . The gate voltage of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  to be reduced to the source voltage of the N-channel bidirectionally conductive field effect transistor  114 , to thereby reduce a leakage current. The back gate terminal of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  via the terminal  125  and the NMOS transistor  162  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  151 . The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the external terminal  121  can be output as Low. 
         [0038]    When the load  131  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a discharge-inhibited state, the output terminals  126  and  128  of the control circuit  102  output High and the output terminal  127  thereof outputs Low. Then, the PMOS transistor  110  is turned OFF, the NMOS transistor  111  is turned ON, the NMOS transistor  161  is turned ON, and the NMOS transistor  162  is turned OFF. Then, the gate of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  via the NMOS transistor  161 , the terminal  125 , and the NMOS transistor  111 . The N-channel bidirectionally conductive field effect transistor  114  then enters the OFF state. This way, a discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Here, a parasitic diode  172  is reverse-biased to prevent the current from flowing from the external terminal  121  to the negative power supply terminal  123 . The gate voltage of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  to be reduced to the drain voltage of the N-channel bidirectionally conductive field effect transistor  114 , to thereby reduce the leakage current. The back gate terminal of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  via the terminal  125  and the NMOS transistor  161  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  151 . The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the negative power supply terminal  123  can be output as Low. 
         [0039]    Note that, the N-channel bidirectionally conductive field effect transistor  114  may be externally connected to the charge/discharge control circuit  151 . 
         [0040]    As described above, according to the battery device including the charge/discharge control circuit  151  of this embodiment, the leakage current flowing through the N-channel bidirectionally conductive field effect transistor  114  can be reduced in either case where the secondary battery  101  has entered the charge-inhibited state or the discharge-inhibited state. In addition, by connecting the back gate of the N-channel bidirectionally conductive field effect transistor  114  to the external terminal  121  or the negative power supply terminal  123 , the charge/discharge control circuit  151  can be operated stably. 
       Second Embodiment 
       [0041]      FIG. 2  is a circuit diagram of a battery device including a charge/discharge control circuit  251  according to a second embodiment of the present invention. 
         [0042]    The battery device including the charge/discharge control circuit  251  of the second embodiment includes a secondary battery  101 , a control circuit  102 , a P-channel bidirectionally conductive field effect transistor  214 , external terminals  120  and  121  between which a charger  132  or a load  131  is to be connected, PMOS transistors  210 ,  261 , and  262 , and an NMOS transistor  211 . The PMOS transistor  210 , the NMOS transistor  211 , a terminal  124  (second terminal), and a terminal  125  (first terminal) together form a switch circuit  252 . 
         [0043]    The secondary battery  101  has both ends connected to a positive power supply terminal  122  and a negative power supply terminal  123 , respectively. The control circuit  102  is connected to the terminal  125  as positive power supply and to the negative power supply terminal  123  as negative power supply. The control circuit  102  has an output terminal  126  connected to a gate of the PMOS transistor  210  and a gate of the NMOS transistor  211 , an output terminal  127  connected to a gate of the PMOS transistor  262 , and an output terminal  128  connected to a gate of the PMOS transistor  261 . The PMOS transistor  210  has a source and a back gate which are connected to a source and a back gate of the PMOS transistor  261  and a source and a back gate of the PMOS transistor  262  via the terminal  125 . The PMOS transistor  210  has a drain connected to a drain of the NMOS transistor  211 . The NMOS transistor  211  has a source connected to the negative power supply terminal  123  and the external terminal  121  via the terminal  124 . The NMOS transistor  211  has the drain also connected to a gate of the P-channel bidirectionally conductive field effect transistor  214 . The PMOS transistor  261  has a drain connected to the positive power supply terminal  122 . The PMOS transistor  262  has a drain connected to the external terminal  120 . The P-channel bidirectionally conductive field effect transistor  214  has a drain connected to the positive power supply terminal  122 , a source connected to the external terminal  120 , and a back gate connected to the terminal  125 . 
         [0044]    Next, an operation of the battery device including the charge/discharge control circuit  251  according to the second embodiment is described. 
         [0045]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  is in a chargeable/dischargeable state, the output terminal  126  of the control circuit  102  outputs High and the output terminals  127  and  128  thereof output Low. Then, the PMOS transistor  210  is turned OFF, the NMOS transistor  211  is turned ON, the PMOS transistor  261  is turned ON, and the PMOS transistor  262  is turned ON. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the negative power supply terminal  123 , and the P-channel bidirectionally conductive field effect transistor  214  enters an ON state. This way, charge/discharge is performed. Here, the respective outputs of the control circuit  102  may be such that: the output terminals  126  and  128  output High while the output terminal  127  outputs Low; the output terminals  126  and  127  output High while the output terminal  128  outputs Low; or the output terminals  126 ,  127 , and  128  output High. The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence a higher one of the voltage at the positive power supply terminal  122  and the voltage at the external terminal  120  can be output as High. 
         [0046]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a charge-inhibited state, the output terminals  126  and  127  of the control circuit  102  output Low and the output terminal  128  thereof outputs High. Then, the PMOS transistor  210  is turned ON, the NMOS transistor  211  is turned OFF, the PMOS transistor  261  is turned OFF, and the PMOS transistor  262  is turned ON. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  via the PMOS transistor  262 , the terminal  125 , and the PMOS transistor  210 . The P-channel bidirectionally conductive field effect transistor  214  then enters the OFF state. This way, a charge current is interrupted to prevent overcharge of the secondary battery  101 . Here, a parasitic diode  271  is reverse-biased to prevent the current from flowing from the external terminal  120  to the positive power supply terminal  122 . The gate voltage of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  to be increased to the source voltage of the P-channel bidirectionally conductive field effect transistor  214 , to thereby reduce a leakage current. The back gate terminal of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  via the terminal  125  and the PMOS transistor  262  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  251 . The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the external terminal  120  can be output as High. 
         [0047]    When the load  131  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a discharge-inhibited state, the output terminals  126  and  128  of the control circuit  102  output Low and the output terminal  127  thereof outputs High. Then, the PMOS transistor  210  is turned ON, the NMOS transistor  211  is turned OFF, the PMOS transistor  261  is turned ON, and the PMOS transistor  262  is turned OFF. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  via the PMOS transistor  261 , the terminal  125 , and the PMOS transistor  210 . The P-channel bidirectionally conductive field effect transistor  214  then enters the OFF state. This way, a discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Here, a parasitic diode  272  is reverse-biased to prevent the current from flowing from the positive power supply terminal  122  to the external terminal  120 . The gate voltage of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  to be increased to the source voltage of the P-channel bidirectionally conductive field effect transistor  214 , to thereby reduce a leakage current. The back gate terminal of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  via the terminal  125  and the PMOS transistor  261  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  251 . The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the positive power supply terminal  122  can be output as High. 
         [0048]    Note that, the P-channel bidirectionally conductive field effect transistor  214  may be externally connected to the charge/discharge control circuit  251 . 
         [0049]    As described above, according to the battery device including the charge/discharge control circuit  251  of the second embodiment, the leakage current flowing through the P-channel bidirectionally conductive field effect transistor  214  can be reduced in either case where the secondary battery  101  has entered the charge-inhibited state or the discharge-inhibited state. In addition, by connecting the back gate of the P-channel bidirectionally conductive field effect transistor  214  to the external terminal  120  or the positive power supply terminal  122 , the charge/discharge control circuit  251  can be operated stably. 
       Third Embodiment 
       [0050]      FIG. 3  is a circuit diagram of a battery device including a charge/discharge control circuit  351  according to a third embodiment of the present invention. 
         [0051]      FIG. 3  is different from  FIG. 1  in that the terminal  125  and the back gate of the N-channel bidirectionally conductive field effect transistor  114  are disconnected from each other. 
         [0052]    Next, an operation of the battery device including the charge/discharge control circuit  351  according to the third embodiment is described. 
         [0053]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  is in a chargeable/dischargeable state, the output terminal  126  of the control circuit  102  outputs Low and the output terminals  127  and  128  thereof output High. Then, the PMOS transistor  110  is turned ON, the NMOS transistor  111  is turned OFF, the NMOS transistor  161  is turned ON, and the NMOS transistor  162  is turned ON. Then, the gate electrode of the N-channel bidirectionally conductive field effect transistor  114  is connected to the positive power supply terminal  122 , and the N-channel bidirectionally conductive field effect transistor  114  enters an ON state. This way, charge/discharge is performed. The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence a lower one of the voltage at the negative power supply terminal  123  and the voltage at the external terminal  121  can be output as Low. Here, the respective outputs of the control circuit  102  may be such that: the output terminals  126  and  128  output Low while the output terminal  127  outputs High; or the output terminals  126  and  127  output Low while the output terminal  128  outputs High. 
         [0054]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a charge-inhibited state, the output terminals  126  and  127  of the control circuit  102  output High and the output terminal  128  thereof outputs Low. Then, the PMOS transistor  110  is turned OFF, the NMOS transistor  111  is turned ON, the NMOS transistor  161  is turned OFF, and the NMOS transistor  162  is turned ON. Then, the gate electrode of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  via the NMOS transistor  162 , the terminal  125 , and the NMOS transistor  111 . The N-channel bidirectionally conductive field effect transistor  114  then enters the OFF state. This way, a charge current is interrupted to prevent overcharge of the secondary battery  101 . Here, the parasitic diode  171  is reverse-biased to prevent the current from flowing from the negative power supply terminal  123  to the external terminal  121 . The gate voltage of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  to be reduced to the source voltage of the N-channel bidirectionally conductive field effect transistor  114 , to thereby reduce a leakage current. The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the external terminal  121  can be output as Low. 
         [0055]    When the load  131  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a discharge-inhibited state, the output terminals  126  and  128  of the control circuit  102  output High and the output terminal  127  thereof outputs Low. Then, the PMOS transistor  110  is turned OFF, the NMOS transistor  111  is turned ON, the NMOS transistor  161  is turned ON, and the NMOS transistor  162  is turned OFF. Then, the gate electrode of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  via the NMOS transistor  161 , the terminal  125 , and the NMOS transistor  111 . The N-channel bidirectionally conductive field effect transistor  114  then enters the OFF state. This way, a discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Here, the parasitic diode  172  is reverse-biased to prevent the current from flowing from the external terminal  121  to the negative power supply terminal  123 . The gate voltage of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  to be reduced to the drain voltage of the N-channel bidirectionally conductive field effect transistor  114 , to thereby reduce a leakage current. The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the negative power supply terminal  123  can be output as Low. 
         [0056]    Note that, the N-channel bidirectionally conductive field effect transistor  114  may be externally connected to the charge/discharge control circuit  351 . 
         [0057]    As described above, according to the battery device including the charge/discharge control circuit  351  of the third embodiment, the leakage current flowing through the N-channel bidirectionally conductive field effect transistor  114  can be reduced in either case where the secondary battery  101  has entered the charge-inhibited state or the discharge-inhibited state. 
       Fourth Embodiment 
       [0058]      FIG. 4  is a circuit diagram of a battery device including a charge/discharge control circuit  451  according to a fourth embodiment of the present invention. 
         [0059]      FIG. 4  is different from  FIG. 2  in that the terminal  125  and the back gate of the P-channel bidirectionally conductive field effect transistor  214  are disconnected from each other. 
         [0060]    Next, an operation of the battery device including the charge/discharge control circuit  451  according to the fourth embodiment is described. 
         [0061]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  is in a chargeable/dischargeable state, the output terminal  126  of the control circuit  102  outputs High and the output terminals  127  and  128  thereof output Low. Then, the PMOS transistor  210  is turned OFF, the NMOS transistor  211  is turned ON, the PMOS transistor  261  is turned ON, and the PMOS transistor  262  is turned ON. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the negative power supply terminal  123 , and the P-channel bidirectionally conductive field effect transistor  214  enters an ON state. This way, charge/discharge is performed. The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence a higher one of the voltage at the positive power supply terminal  122  and the voltage at the external terminal  120  can be output as High. Here, the respective outputs of the control circuit  102  may be such that: the output terminals  126  and  128  output High while the output terminal  127  outputs Low; or the output terminals  126  and  127  output High while the output terminal  128  outputs Low. 
         [0062]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a charge-inhibited state, the output terminals  126  and  127  of the control circuit  102  output Low and the output terminal  128  thereof outputs High. Then, the PMOS transistor  210  is turned ON, the NMOS transistor  211  is turned OFF, the PMOS transistor  261  is turned OFF, and the PMOS transistor  262  is turned ON. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  via the PMOS transistor  262 , the terminal  125 , and the PMOS transistor  210 . The P-channel bidirectionally conductive field effect transistor  214  then enters the OFF state. This way, a charge current is interrupted to prevent overcharge of the secondary battery  101 . Here, the parasitic diode  271  is reverse-biased to prevent the current from flowing from the external terminal  120  to the positive power supply terminal  122 . The gate voltage of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  to be increased to the source voltage of the P-channel bidirectionally conductive field effect transistor  214 , to thereby reduce a leakage current. The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the external terminal  120  can be output as High. 
         [0063]    When the load  131  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a discharge-inhibited state, the output terminals  126  and  128  of the control circuit  102  output Low and the output terminal  127  thereof outputs High. Then, the PMOS transistor  210  is turned ON, the NMOS transistor  211  is turned OFF, the PMOS transistor  261  is turned ON, and the PMOS transistor  262  is turned OFF. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  via the PMOS transistor  261 , the terminal  125 , and the PMOS transistor  210 . The P-channel bidirectionally conductive field effect transistor  214  then enters the OFF state. This way, a discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Here, the parasitic diode  272  is reverse-biased to prevent the current from flowing from the positive power supply terminal  122  to the external terminal  120 . The gate voltage of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  to be increased to the source voltage of the P-channel bidirectionally conductive field effect transistor  214 , to thereby reduce a leakage current. The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the positive power supply terminal  122  can be output as High. 
         [0064]    Note that, the P-channel bidirectionally conductive field effect transistor  214  may be externally connected to the charge/discharge control circuit  451 . 
         [0065]    As described above, according to the battery device including the charge/discharge control circuit  451  of the fourth embodiment, the leakage current flowing through the P-channel bidirectionally conductive field effect transistor  214  can be reduced in either case where the secondary battery  101  has entered the charge-inhibited state or the discharge-inhibited state. 
       Fifth Embodiment 
       [0066]      FIG. 6  is a circuit diagram of a battery device including a charge/discharge control circuit  651  according to a fifth embodiment of the present invention. 
         [0067]      FIG. 6  is different from  FIG. 1  in that Schottky barrier diodes  601  and  602  are added. The Schottky barrier diode  601  has an anode connected to the source of the NMOS transistor  161  and a cathode connected to the drain of the NMOS transistor  161 . The Schottky barrier diode  602  has an anode connected to the source of the NMOS transistor  162  and a cathode connected to the drain of the NMOS transistor  162 . 
         [0068]    Next, an operation of the battery device including the charge/discharge control circuit  651  according to the fifth embodiment is described. 
         [0069]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  is in a chargeable/dischargeable state, the output terminal  126  of the control circuit  102  outputs Low and the output terminals  127  and  128  thereof output High. Then, the PMOS transistor  110  is turned ON, the NMOS transistor  111  is turned OFF, the NMOS transistor  161  is turned ON, and the NMOS transistor  162  is turned ON. Then, the gate electrode of the N-channel bidirectionally conductive field effect transistor  114  is connected to the positive power supply terminal  122 , and the N-channel bidirectionally conductive field effect transistor  114  enters an ON state. This way, charge/discharge is performed. Here, the respective outputs of the control circuit  102  may be such that: the output terminals  126  and  128  output Low while the output terminal  127  outputs High; the output terminals  126  and  127  output Low while the output terminal  128  outputs High; or the output terminals  126 ,  127 , and  128  output Low. The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence a lower one of the voltage at the negative power supply terminal  123  and the voltage at the external terminal  121  can be output as Low. 
         [0070]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a charge-inhibited state, the output terminals  126  and  127  of the control circuit  102  output High and the output terminal  128  thereof outputs Low. Then, the PMOS transistor  110  is turned OFF, the NMOS transistor  111  is turned ON, the NMOS transistor  161  is turned OFF, and the NMOS transistor  162  is turned ON. Then, the gate of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  via the NMOS transistor  162 , the terminal  125 , and the NMOS transistor  111 . The N-channel bidirectionally conductive field effect transistor  114  then enters the OFF state. This way, a charge current is interrupted to prevent overcharge of the secondary battery  101 . Here, the parasitic diode  171  is reverse-biased to prevent the current from flowing from the negative power supply terminal  123  to the external terminal  121 . The gate voltage of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  to be reduced to the source voltage of the N-channel bidirectionally conductive field effect transistor  114 , to thereby reduce a leakage current. The back gate terminal of the N-channel bidirectionally conductive field effect transistor  114  is connected to the external terminal  121  via the terminal  125  and the NMOS transistor  162  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  651 . The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the external terminal  121  can be output as Low. The Schottky barrier diode  602  can prevent the terminal  125  from becoming a floating state even if the NMOS transistor  161  and the NMOS transistor  162  are instantaneously turned OFF when the NMOS transistor  162  is changed from OFF to ON. 
         [0071]    When the load  131  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a discharge-inhibited state, the output terminals  126  and  128  of the control circuit  102  output High and the output terminal  127  thereof outputs Low. Then, the PMOS transistor  110  is turned OFF, the NMOS transistor  111  is turned ON, the NMOS transistor  161  is turned ON, and the NMOS transistor  162  is turned OFF. Then, the gate of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  via the NMOS transistor  161 , the terminal  125 , and the NMOS transistor  111 . The N-channel bidirectionally conductive field effect transistor  114  then enters the OFF state. This way, a discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Here, the parasitic diode  172  is reverse-biased to prevent the current from flowing from the external terminal  121  to the negative power supply terminal  123 . The gate voltage of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  to be reduced to the drain voltage of the N-channel bidirectionally conductive field effect transistor  114 , to thereby reduce a leakage current. The back gate terminal of the N-channel bidirectionally conductive field effect transistor  114  is connected to the negative power supply terminal  123  via the terminal  125  and the NMOS transistor  161  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  651 . The negative power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the positive power supply terminal  123  can be output as Low. The Schottky barrier diode  601  can prevent the terminal  125  from becoming a floating state even if the NMOS transistor  161  and the NMOS transistor  162  are instantaneously turned OFF when the NMOS transistor  161  is changed from OFF to ON. 
         [0072]    As described above, according to the battery device including the charge/discharge control circuit  651  of the fifth embodiment, the leakage current flowing through the N-channel bidirectionally conductive field effect transistor  114  can be reduced in either case where the secondary battery  101  has entered the charge-inhibited state or the discharge-inhibited state. In addition, by connecting the back gate of the N-channel bidirectionally conductive field effect transistor  114  to the external terminal  121  or the negative power supply terminal  123 , the charge/discharge control circuit  651  can be operated stably. 
         [0073]    Note that, the N-channel bidirectionally conductive field effect transistor  114  may be externally connected to the charge/discharge control circuit  651 . Further, the leakage current can be reduced also in a configuration in which the back gate of the N-channel bidirectionally conductive field effect transistor  114  is not connected to the terminal  125 . 
       Sixth Embodiment 
       [0074]      FIG. 7  is a circuit diagram of a battery device including a charge/discharge control circuit  751  according to a sixth embodiment of the present invention. 
         [0075]      FIG. 7  is different from  FIG. 2  in that Schottky barrier diodes  701  and  702  are added. The Schottky barrier diode  701  has an anode connected to the source of the PMOS transistor  261  and a cathode connected to the drain of the PMOS transistor  261 . The Schottky barrier diode  702  has an anode connected to the source of the PMOS transistor  262  and a cathode connected to the drain of the PMOS transistor  262 . 
         [0076]    Next, an operation of the battery device including the charge/discharge control circuit  751  according to the sixth embodiment is described. 
         [0077]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  is in a chargeable/dischargeable state, the output terminal  126  of the control circuit  102  outputs High and the output terminals  127  and  128  thereof output Low. Then, the PMOS transistor  210  is turned OFF, the NMOS transistor  211  is turned ON, the PMOS transistor  261  is turned ON, and the PMOS transistor  262  is turned ON. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the negative power supply terminal  123 , and the P-channel bidirectionally conductive field effect transistor  214  enters an ON state. This way, charge/discharge is performed. Here, the respective outputs of the control circuit  102  may be such that: the output terminals  126  and  128  output High while the output terminal  127  outputs Low; the output terminals  126  and  127  output High while the output terminal  128  outputs Low; or the output terminals  126 ,  127 , and  128  output High. The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence a higher one of the voltage at the positive power supply terminal  122  and the voltage at the external terminal  120  can be output as High. 
         [0078]    When the charger  132  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a charge-inhibited state, the output terminals  126  and  127  of the control circuit  102  output Low and the output terminal  128  thereof outputs High. Then, the PMOS transistor  210  is turned ON, the NMOS transistor  211  is turned OFF, the PMOS transistor  261  is turned OFF, and the PMOS transistor  262  is turned ON. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  via the PMOS transistor  262 , the terminal  125 , and the PMOS transistor  210 . The P-channel bidirectionally conductive field effect transistor  214  then enters the OFF state. This way, a charge current is interrupted to prevent overcharge of the secondary battery  101 . Here, the parasitic diode  271  is reverse-biased to prevent the current from flowing from the external terminal  120  to the positive power supply terminal  122 . The gate voltage of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  to be increased to the source voltage of the P-channel bidirectionally conductive field effect transistor  214 , to thereby reduce a leakage current. The back gate terminal of the P-channel bidirectionally conductive field effect transistor  214  is connected to the external terminal  120  via the terminal  125  and the PMOS transistor  262  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  751 . The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the external terminal  120  can be output as High. The Schottky barrier diode  702  can prevent the terminal  125  from becoming a floating state even if the PMOS transistor  261  and the PMOS transistor  262  are instantaneously turned OFF when the PMOS transistor  262  is changed from OFF to ON. 
         [0079]    When the load  131  is connected between the external terminals  120  and  121  and the control circuit  102  detects that the secondary battery  101  has entered a discharge-inhibited state, the output terminals  126  and  128  of the control circuit  102  output Low and the output terminal  127  thereof outputs High. Then, the PMOS transistor  210  is turned ON, the NMOS transistor  211  is turned OFF, the PMOS transistor  261  is turned ON, and the PMOS transistor  262  is turned OFF. Then, the gate electrode of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  via the PMOS transistor  261 , the terminal  125 , and the PMOS transistor  210 . The P-channel bidirectionally conductive field effect transistor  214  then enters the OFF state. This way, a discharge current is interrupted to prevent overdischarge of the secondary battery  101 . Here, the parasitic diode  272  is reverse-biased to prevent the current from flowing from the positive power supply terminal  122  to the external terminal  120 . The gate voltage of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  to be increased to the source voltage of the P-channel bidirectionally conductive field effect transistor  214 , to thereby reduce a leakage current. The back gate terminal of the P-channel bidirectionally conductive field effect transistor  214  is connected to the positive power supply terminal  122  via the terminal  125  and the PMOS transistor  261  and hence does not become a floating state, which enables more stable operation of the charge/discharge control circuit  751 . The positive power supply of the control circuit  102  is connected to the terminal  125 , and hence the voltage at the positive power supply terminal  122  can be output as High. The Schottky barrier diode  701  can prevent the terminal  125  from becoming a floating state even if the PMOS transistor  261  and the PMOS transistor  262  are instantaneously turned OFF when the PMOS transistor  261  is changed from OFF to ON. 
         [0080]    As described above, according to the battery device including the charge/discharge control circuit  751  of the sixth embodiment, the leakage current flowing through the P-channel bidirectionally conductive field effect transistor  214  can be reduced in either case where the secondary battery  101  has entered the charge-inhibited state or the discharge-inhibited state. In addition, by connecting the back gate of the P-channel bidirectionally conductive field effect transistor  214  to the external terminal  120  or the positive power supply terminal  122 , the charge/discharge control circuit  751  can be operated stably. 
         [0081]    Note that, the P-channel bidirectionally conductive field effect transistor  214  may be externally connected to the charge/discharge control circuit  751 . Further, the leakage current can be reduced also in a configuration in which the back gate of the P-channel bidirectionally conductive field effect transistor  214  is not connected to the terminal  125 .