Abstract:
A method of manufacturing an integrated circuit having metal programmable logic cells. Metal programmable logic cells include transistors which, by varying routing of conductors in the metalization of the integrated circuit, may be connected in or disconnected from a logic path extending between the input and output of the cell. Transistors which are deselected by not being connected in the logic path are also decoupled from the supply rails. Generally speaking, deselected transistors can not be scan tested without substantial additional circuitry, as they do not form part of the logic path between the cell input and output to which the scan test circuitry is normally coupled. Decoupling transistors which are not in the logic path ensures that “stuck on” faults, in which transistors are stuck in a conductive state, do not allow current to flow between the supply rails through these faulty transistors, thus avoiding hot spots and reliability problems. By preventing damage even in the event of a “stuck on” fault, the need for extra test circuitry is avoided.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention is in the field of integrated circuits, and solves a problem related to reliability of integrated circuits having metal programmable logic. 
     2. Description of the Prior Art 
     Integrated circuits (“ICs”) typically have a substrate, an active region on the substrate containing a large plurality of circuit elements such a transistors, resistors, capacitors etc., and a region adjacent the active region which has a plurality of conductor layers and insulating layers interspersed between the conductor layers. The conductor layers each include a large number of conductor tracks which are used to provide power to the circuit elements, as well as for signal routing between the elements. 
     During design and testing of an integrated circuit, or even after an IC has been in production, it is often necessary or desirable to revise the circuit operation to remove faults or to otherwise improve circuit operation. At the most severe end of the spectrum of revisions, the changes may require modifications to the masks which define the content and arrangement of circuit elements on the substrate. More frequently, however, the designer has anticipated potential problems and has included sufficient circuit elements on the integrated circuit to fix the problem. For example, the designers may include a selection of buffer circuit elements to remove timing problems in the signal routing. It is then a matter of modifying the conductor routing so as to decouple and/or couple certain of the circuit elements so as to implement the fix. 
     Additionally, many chip designs incorporate an identification (“ID”) module which is readable by software. The purpose of the module ID is to allow software to identify the hardware and, based on the ID, configure the chip and the corresponding software. As the industry moves to systems on a chip design, where proven circuit modules are “plugged into” the IC, it will be desirable for each circuit module to have a corresponding module ID. 
     When making a circuit fix/enhancement to a particular module, it will typically be desirable to change the output of the module ID circuit, so that software will read a different ID code reflecting the change. One way to implement a module ID is with metal programmable logic. Metal programmable logic includes a region on an IC in which a plurality of logic gates are formed. The logic function implemented by these gates is selected by controlling how the gates are interconnected with conductors in the conductors layers. Changing the module ID is but one of many uses for metal programmable logic. 
     Integrated circuits typically contain built-in circuitry which allows the integrated circuit to be thoroughly tested. One well-known technique is boundary scan testing in which a chain of registers and flip-flops are included on the IC. Boundary scan circuits allow digital inputs to be applied to individual circuits while allowing monitoring of the output of a circuit in response to the known input. When the output is not as expected, the circuit then has a fault. 
     SUMMARY OF THE INVENTION 
     A problem with metal selectable logic that was recognized by the present inventors is that “deselected” transistors, i.e. transistors of a logic cell provided on the IC substrate but which are decoupled from the logic path of the cell by removing conductors which would otherwise couple these transistors to other transistors in the logic path, are not scan testable with typical scan test circuits. This is because scan test circuits are commonly coupled to the input and output of a cell. Thus, if the logic configuration is changed for example by coupling the output to a different node in the cell, thereby removing one or more transistors from the logic path between the cell input and the cell output, scan test data input to the cell input and read from the cell output will no longer be influenced by deselected transistors. If one of these deselected transistors has a fault, it will not be observed by the scan test. However, deselected transistors usually form a gate coupled between power supply rails of the logic cell. A failure mode is for deselected transistors to form an unwanted current path between the power supply rails which causes hot spots that can lead to premature failure of neighboring gates and malfunctioning of the integrated circuit. This normally occurs with “stuck on” faults in which a transistor is stuck in a conductive state. 
     Accordingly, it would be desirable to provide an IC with metal programmable logic in which the potential for damage to selected gates from non-selected gates is substantially reduced. 
     Generally, metal programmable logic cells are switchable between two or more logic configurations. Consequently, it would be possible to provide extra circuitry in the scan test circuit to test deselected gates. However, this is not desirable as it would add complexity, consume additional die area, and generally increase the cost of the integrated circuit. 
     Accordingly, it would be desirable to increase the confidence in the integrity of integrated circuits having metal programmable logic cells with deselected transistors without providing additional circuitry to actually scan test deselected gates. 
     Generally speaking, the invention is a method of improving the reliability of an integrated circuit having a metal-programmable logic cell in which the logic cell can be selected during manufacturing to have one of a first logic configuration and a second logic configuration by selection of conductor routing paths to select and deselect transistors for inclusion in a logic path of the cell. At least one transistor is deselected from the logic path of the cell by placing conductor routings so that the at least one transistor is functionally decoupled from the logic path of the cell. The deselected transistor is also decoupled from power supply rails of the cell so that no conductive path extends through the deselected transistor between the cell power supply rails. 
     When changing from one logic configuration to another, instead of merely changing conductor routing so as to deselect one or more transistors as in known methods, the present method goes further and makes additional conductor routing changes to provide an open circuit in the path of the main current channel of the deselected transistors. In this way, if a deselected transistor were to have a “stuck on” fault in which it remained conductive despite its control terminal being decoupled from other, selected transistors in the logic path, there will be no conductive path through the deselected transistor(s) between the cell power supply rails. In this way, hot spots and the reliability problems to the integrated circuit which this entails are avoided. 
     The method does not alter the fact that in the completed integrated circuit with a typical scan test circuit the deselected transistor(s) are not scan testable. Rather, the method removes a major source of reliability problems posed by “stuck on” fault conditions. Thus, the method provides an integrated circuit with deselected transistors with enhanced reliability. This alleviates the need to provide additional, area consuming elements in the scan test circuitry to test for “stuck on” faults, since even if a deselected transistor were to have such a fault, the reliability problem posed by this fault in prior art circuits has been removed by the method according to this invention. 
     The invention also relates to an integrated circuit manufactured according to the above method in which deselected transistors in a metal programmable logic cell have conductor routings with an open circuit so that no current path extends through the deselected transistors between the supply rails. 
     According to another aspect of the invention, an integrated circuit has an ID module comprising a metal programmable logic cell with deselected transistors electrically decoupled from the supply rails. 
     These and other objects, features and advantages of the invention will become apparent from the following detailed description and the drawings, both of which are illustrative and not limiting. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 diagrammatically illustrates an integrated circuit with a number of circuit modules and corresponding ID modules; 
     FIG. 2 illustrates cells of an exemplary identification module according to the invention; 
     FIGS.  3 ( a ), ( b ) are circuit diagrams of a register having two inverters in series; 
     FIGS.  4 ( a ), ( b ) illustrate cell layouts corresponding to the registers of FIGS.  3 ( a ),  3 ( b ); 
     FIG.  5 ( a ) is a circuit diagram of a register having a non-selected gate according to one aspect of the invention; 
     FIG.  5 ( b ) is a circuit diagram of a register having a non-selected gate according to another embodiment of the invention; 
     FIGS.  6 (A)- 6 ( b ) are exemplary cell layouts corresponding to FIGS.  5 ( a ),  5 ( b ); 
     FIGS.  7 ( a );  7 ( b ) are circuit diagrams of an AND gate and a NAND gate according to the invention; 
     FIGS.  8 ( a );  8 ( b ) are cell layouts corresponding to the circuits of FIGS.  7 ( a );  7 ( b ); and 
     FIG. 9 diagrammatically illustrates an IC with a scan test circuit coupled to the cell input and cell output of a cell. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates an IC  100  having a plurality of circuit modules  101 ,  103 ,  105 . Each of the circuit modules has a corresponding module ID circuit  101 A,  103 A,  105 A. A circuit  107  provides a logic signal to each of the module ID circuits. The module ID circuits are coupled to an output pin of the IC so that the output of each module ID circuit can be read by an external device. 
     FIG. 2 is a circuit diagram of an exemplary ID circuit  101 A having a plurality of cells ( 200   1 - 200   n ) Each cell includes an input ( 205   1 - 205   n ), a first circuit element ( 201   1 - 200   n ), a second circuit element ( 203   1 - 203   n ) and an output ( 207   1 - 207   n ) Each of the circuit elements is a logic gate in the form of an inverter. The cells are arranged in parallel to provide an identification code at the outputs  207  in response to a common logic signal applied to all of the cells at the inputs  205 . For example, if n=5 and a logic “0” is applied to each of the inputs  205 , the ID code output will be (0 0 0 0 0) since each cell is shown configured simply as a buffer. To change the code, one or more of the cells are configured to bypass one of the inverters. FIG. 2 shows the cell  200   1  optionally being configured to bypass the first inverter  201   1 , as represented by the dashed bridging conductor  209   1 . Alternatively, a bridging conductor could bypass the second inverter, such as illustrated with dashed conductor  209   5  for the cell  200   5 . If the first and fifth cells were so modified and the input kept the same, the output would then be (1 0 0 0 1). Generally, more cells would be included in each ID module, such as 32 to form a 32 bit ID. 
     While FIG. 1 shows each circuit module having a respective ID module for each circuit module, this is for a system on a chip implementation. ICs for other applications could have only some of the circuit modules with ID module&#39;s, or only one ID module for the IC. 
     As is well known in the art, generally, individual circuit elements are formed on top of a substrate of the integrated circuit. Connections to the individual transistors, resistors, capacitors to provide a source of potential as well as for signal routing are accomplished with conductor tracks arranged in a plurality of layers. The conductor tracks are typically of a metal, such as an alloy of aluminum or copper. The conductor layers are separated by an electrically insulating layer, such as silicon dioxide as one of many examples. 
     FIG.  3 ( a ) is a circuit diagram of an exemplary cell  200   1  having a first inverter INV 1  and a second inverter INV 2 . The inverters includes first and second CMOS transistors of opposite conductivity type having their main current channels coupled between first and second supply rails Vdd and Vss. The inverter INV 1  has a PMOS transistor T 1  with a source S 1  coupled to the first rail Vss, a drain D 1  coupled to the drain D 2  of an NMOS transistor T 2 , which has its source S 2  coupled to the second supply rail Vss. The input IN of the cell is coupled to the input IN 1  of the first inverter and to the gates G 1  and G 2  of the first and second transistors T 1 , T 2 . The output of the first inverter OUT 1  is coupled to the input IN 2  of the second inverter. The second inverter includes third and fourth transistors coupled between the supply rails in an identical manner as the first inverter. When the cell input IN is logic high, the output OUT 1  of the first inverter is logic low, with transistor T 1  being off (non-conductive) and transistor T 2  being on (conductive). The output OUT 1  is thus coupled to Vss and is logic low. With input IN 2  being logic low, the transistor T 4  is off while the transistor T 3  is conductive and couples the output OUT 2  to the first rail Vdd. Thus, the output OUT 2  of the second inverter and of the cell (OUT)is logic high. When used as a cell for a module ID circuit, the cell input will typically be the same for all sales, so the output of the cell is changed by rearranging how a respective conductor track is coupled to the cell. To change the cell output, an output conductor would be coupled to the output OUT 1  of the first inverter, with the output OUT 1  also being disconnected from the input IN 2  of the second inverter. This configuration is illustrated in FIG.  3 ( b ). Thus, by selective conductor routing of an output conductor to either of the outputs OUT 1  or OUT 2 , the logic function of the cell is effectively programmed during manufacture. 
     FIG.  4 ( a ) illustrates a CMOS layout for the cell of FIG.  3 ( a ). The respective drain and source regions are labeled for each transistor, with the labels corresponding to those of FIG.  3 ( a ). However, instead of each transistor having a separate gate, the first and second transistors have a common gate CG 1  and the third and fourth transistors have a common gate CG 2 . The supply rails Vdd and Vss are formed by conductors  301 ,  303 , in a first metal layer above the transistors, and are coupled to their respective sources by vias “V” which extend between the sources and rails in a conventional manner. The cell input IN is formed by a conductor  305  which is coupled to a gate contact GC 1  connected to the common gate GC 1 . A conductor  307  connects the drains D 1 , D 2  together and a conductor  308  connects the conductor  307  to the gate contact GC 2 , connected to the common gate CG 2 . A conductor  309  couples the drains of the third and fourth transistors to each other and forms the output OUT of the cell. FIG.  4 ( b ) is identical to FIG.  4 ( a ), with the exception that there is no conductor  309  connecting the output OUT 1  of the first inverter to the input INV 2  of the second inverter formed by gate contact GC 2 . 
     If the cell is to function as a buffer, the output OUT 2  of the cell would be used by contacting an output conductor to conductor  309 . Conversely, if the cell is to function as an inverter, an output conductor would be connected to the conductor  307  which forms the output OUT 1  of the first inverter. The contact would be made for example from an output conductor in a higher metal layer connected with a via to the desired conductor  307 ,  308 ,  309 . 
     A problem arises when the output OUT 2  is not used, in that the functioning of the second set of transistors T 3 , T 4  is not scan testable. The logic path extends from the input IN 1  to the output OUT 1 . The transistors T 3 , T 4  still have there drains D 3 , D 4  coupled to each other so that a conductive path extends between the supply rails Vss, Vdd. If either of these devices has a fault, it cannot be detected because they are no longer part of the scan chain. A fault has consequences for the circuit, typically with respect to reliability. For example, if the transistor T 3  leaks current, it can cause hot spots, which over time can cause surrounding transistors which are part of the logic circuit to fail. 
     FIG.  5 ( a ) shows a circuit diagram according to a first embodiment of the invention which avoids the above-mentioned failure scenario while still providing the same logic function. The change from the known configuration is that the cell input IN is connected to the input IN 2 , which couples the cell input directly to the input of the second inverter INV 2 . Additionally, the drains D 1 , D 2  of the transistors T 1 , T 2  are not connected and do not form a path between the two supply rails. Thus, a “stuck on” fault in either of the transistors T 1 , T 2  would not allow a current to flow between the two supply rails. The reliability of these devices T 1 , T 2  is thus not a significant issue, and the need for testing is alleviated. The corresponding layout is shown in FIG.  6 ( a ) in which a conductor  311  connects the gate contact GC 1  to the gate contact GC 2 , and no conductor connects the drains D 1 , D 2  of the transistors T 1 , T 2 . 
     FIG.  5 ( b ) shows another embodiment in which the inverting output is tapped at the output OUT 1 . However, drains D 3 , D 4  of the third and fourth conductors are disconnected so that no conductive path is possible between the rails. As with FIG.  5 ( a ), the cell functions as an inverter, but the risk of damage due to a “stuck on” fault is avoided. FIG.  6 ( b ) shows the corresponding layout for FIG.  5 ( b ). 
     FIGS.  7 ( a );  7 ( b ) illustrate another type of metal programmable logic cell according to the invention, in this case an AND gate  300  in FIG.  7 ( a ) which can be converted to a NAND gate  350  by appropriate metal selection. AND gate  300  includes an inverter formed by the PMOS transistor T 15  and NMOS transistor T 16  whose drains are coupled together by a conductor  401  and whose gates are coupled together by a conductor  403 . AND gate  300  further includes PMOS transistors T 11 , T 12  having drains commonly connected to (i) the gates of transistors T 15 , T 16  at conductor  403  and (ii) to the drain of a transistor T 13  whose source is coupled to the drain of a transistor T 14 . A first input IN 1  of the AND gate  300  is coupled to the gates of the transistors T 12 , T 13  and a second input IN 2  is coupled to the gates of the transistors T 11  and T 14 . 
     The operation of AND gates and NAND gates are well known, and accordingly will not be discussed in detail. Essentially, the AND gate  300  is converted to a NAND gate  350  by coupling the output (out) of the cell so as to bypass the inverter formed by the transistors T 15 , T 16 . As shown in FIG.  7 ( b ), the output of the cell is coupled at the input of the inverter at line  403 , and effectively at node  405 . In the prior art, the line  401  of the AND gate would not be removed as illustrated by dashed line  4011  in FIG.  7 ( b ). However, with line  401 ′ still connecting the drains of the non-selected inverter drain transistors T 15 , T 16 , there would still be a path between the supply rails Vdd and Vss. If a “stuck on” condition existed, this would pose the same reliability issues as discussed with respect to the inverter of cell  201  above. Thus, in the cell according to the invention, when making a metal change to connect the output at the line  403  instead of at the line  401 , the line  401  is also removed. In this way, the potential problem from a “stuck on” condition is avoided. 
     FIGS.  8 ( a ) and  8 ( b ) illustrate the cell layouts corresponding to the AND and NAND gates of FIGS.  7 ( a ), ( b ). Portions of the layout corresponding to the conductors and transistors of FIGS.  7 ( a ),  7 ( b ), bear the same reference numerals. For brevity, only those portions of the layout relevant to the present invention will be discussed. In FIG.  8 ( a ), a conductor  401  and vias  401   a,    401   b  are shown which connect the drains D 15 , D 16  of the inverter transistors T 15 , T 16 . The output of the AND gate  300  is formed by the conductor  401 . To convert the AND gate to a NAND gate  350 , a mask change is made in the metal layers of the IC in the portion defining the relevant cell, in this case AND gate  300 . In this case, the relevant mask(s) defining the vias and metal layers are changed such that the conductor  401  is removed. It should be evident that the vias  401 ( a );  401 ( b ) could also be removed as they are no longer used, but this would merely entail an unnecessary mask revision. In addition, the mask(s) are modified to add a conductor  409  and a via  409   a,  so that the output of the cell is now coupled to the commonly connected drains D 11 , D 12 , D 13  corresponding to node  305  in FIG.  7 ( b ). 
     FIG. 9 illustrates a scan test circuit  500  coupled to the cell input and cell output of an exemplary cell  300 / 350 . The scan test circuit feeds test data via line  501  to the cell input IN and reads output data of the cell from the cell output OUT via line  503 . In the case of the cell being in the AND configuration, all transistors will be in the scan path. This is evident from FIG.  7 ( a ) in which the cell output OUT is connected to line  401 . When configured as a NAND gate  350 , however, the transistors T 15 /T 16  will not be in the scan path and “stuck on” faults in these two transistors will not be detected. This is evident from FIG.  7 ( b ) since the cell output OUT is connected to line  403 . However, by reason of the drains of T 15 /T 16 , even if a stuck on condition exists, there is no current path between the supply rails, so hot spots and the ensuing failures caused thereby will not occur. 
     The structure and method described above are not limited to the use of module ID circuits, but in any metal programmable logic circuit. 
     It is understood in the art that routing software is used to layout the conductor tracks in the various conductor layers. Furthermore, software is used to generate masks for the mask sets which are used in manufacturing an IC. Changes in conductor routing for a logic cell will therefore be initially selected with software tools, which will then be reflected in a modified mask or masks which controls the formation/location of conductor paths. 
     The technology by which the invention is made is not important and any of the standard bipolar, CMOS or BiCMOS processes can be used. 
     Although preferred embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims. For example, it will be clear from the foregoing that the open circuit placed in the path between the supply rails for deselected transistors may be placed in any convenient location. 
     The many features and advantages of the invention are apparent from the detailed specification and it is intended by the appended claims to cover all such features and advantages which fall within the true spirit and scope of the invention. Since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.