Abstract:
An ESD protection circuit protects circuitry internal to an integrated circuit from ESD damage to electrostatic discharge voltages occurring at one or more of the inputs of the integrated circuit while maintaining substantially zero effective capacitance at the inputs. The ESD protection circuit includes a pair of diodes of opposite conductivity coupled between at least one of the inputs of the integrated circuit and an internal node thereof for providing current paths to the operating supply rails when ESD voltages occurring at the input forward bias the diodes. A unity gain amplifier provides feedback between the input and the internal circuit node to maintain a zero voltage difference therebetween whereby the effective capacitance seen at the input is reduced to substantially zero.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates generally to electrostatic discharge (ESD) circuits and, more particularly, to an ESD protection circuit and method for use with integrated circuits having input pads without significantly increasing the parasitic capacitance at the input pads.  
         BACKGROUND OF THE INVENTION  
         [0002]    Integrated circuits (IC) normally require ESD protection. ESD protection is conventionally provided at bond pads and/or input/output pads of the IC. In this manner ESD protection is provided to internal circuitry of the IC, such as transistors etc., from ESD spike voltages that exceed the rating of the active devices of the IC. Typically, electrostatic discharge voltage spikes occur at the input pads during handling of the IC.  
           [0003]    The prior art is replete with myriad of ESD integrated protection circuits. Typical ESD protection circuits divert ESD generated voltages occurring at input pads to the power rails of the IC circuits employing such protection. The input pads, for example, are clamped to approximately V DD  or V SS  (the operating voltages applied to the IC) by using ESD protection diodes depending on the polarity of the ESD voltages. Thus, for instance, in response to an ESD voltage established at an input pad of a first polarity (positive) exceeding the forward breakdown voltage of one of the ESD protection diode, current flow is oriented from the pad via the ESD protection diode to the high potential power rail(V DD ). Likewise, if the ESD voltage established at the input pad is of a second polarity and exceeds the forward breakdown voltage of the second ESD protection diode, current flow is oriented from ground (V SS ) via the second ESD protection diode to the pad. Hence, both positive and negative ESD occurrences are clamped to the power rails by the aforementioned action of the ESDP diodes. Similarly, the output pads are also protected from ESD spike voltages by a like pair of diodes.  
           [0004]    Most, if not all, conventional ESD protection circuits typically produce significantly large input capacitance at the input/output pads of the integrated circuit. The increased capacitance is due to the relatively large conductive elements such as the metal pads or conductive patterns associated with the integrated circuit as well as resistors, and the base-emitter junctions of the ESDP diodes of the protection circuit. In some applications, this increased capacitance at the input pads of the integrated ESD protection circuit cannot be tolerated. For example, the integrated circuit employing a conventional ESD protection may be used to probe the output of a pressure sensor. Typically, such pressure sensors provide a small delta output voltage. In order to detect the output of the sensor, the capacitance at the input of the probing device must be as small of value as possible.  
           [0005]    Hence, a need exists to provide an integrated ESD protection circuit in which the capacitance thereof is reduced to a minimum value.  
         SUMMARY OF THE INVENTION  
         [0006]    In accordance with an aspect of the present invention, there is provided an electrostatic discharge (ESD) protection circuit for protecting circuitry internal to an integrated circuit from ESD damage due to ESD voltage that may occur at the input of the integrated circuit while minimizing any effective input capacitance appearing at the input. The ESD protection circuit includes at least one pair of opposite conductivity type diodes coupled between the input and an internal circuit node which provide current paths between the input and the power rails of the integrated when forward bias by ESD voltages. A unity gain amplifier provides feedback to maintain a zero voltage difference between the input and the internal circuit node thereby reducing the effective capacitance to substantially zero.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 is a circuit schematic diagram of the ESD protection circuit of the present invention;  
         [0008]    [0008]FIG. 2 is a simple illustration of an integrated circuit utilizing the ESD protection circuit of FIG. 1;  
         [0009]    [0009]FIG. 3 is a simplified cross sectional view (not to scale) of portion of an integrated circuit illustrating a portion of the circuit shown in FIG. 1; and  
         [0010]    [0010]FIG. 4 is a schematic diagram of another embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0011]    Turning to FIG. 1, there is shown ESD protection circuit  10  of the present invention. ESD protection circuit  10  may be incorporated as part of a conventional integrated circuit (IC) that also includes an analog signal processor as part thereof. ESD protection circuit  10  is shown coupled to input pad  12 , which may also be an input of the IC. Pad  12  is coupled to core output  14  of circuit  10  via metal conductive element  16 , polyresistor rp 1  and metal conductive element  18 . Core output  14  generally would be coupled to internal circuitry of the IC as understood. First and second ESD protection diodes Q 1  and Q 2  are provided as in a conventional ESD protection circuit. Q 1  comprises a PNP transistor having its emitter electrode coupled to input  12 , its base electrode coupled to metal conductive element  20 , and its collector electrode coupled to ground rail  22  to which is supplied V SS . Similarly, Q 2  comprises an NPN transistor having its emitter electrode coupled to metal conductive element  16  and its base electrode coupled to metal conductive element  20 . The collector electrode of Q 2  is coupled to positive rail  24  to which is supplied V DD . The base electrodes of Q 1  and Q 2  are coupled to interconnection of the anode and cathode of diodes D 1  and D 2  respectively. The cathode of D 1  is returned to positive rail  24  while the anode of D 2  is coupled to negative or ground rail  22 .  
         [0012]    In operation, as an ESD voltage at input  12  exceeds V DD , the base-emitter junction of Q 1  is forward biased and current flows through Q 1  via D 1  to the positive rail  24 . Likewise, a positive ESD voltage appearing at rail  22  will cause current flow via D 2  and the base-emitter of Q 2  to input pad  12  once the base-emitter junction is forward biased thereby. Hence, both input  12  and output  14  are substantially clamped to either the positive or negative power rail voltages depending on the polarity of the ESD occurrence.  
         [0013]    Similarly, core output  14  is clamped to the positive and negative rails responsive to positive and negative ESD voltages that may occur on metal conductive elements  18  and  26  respectively as the base-emitter junctions of Q 3  and Q 4  are forward biased. Thus, a positive ESD voltage appearing on metal conductive element  18  causes a current flow via Q 3  and D 3  to rail  24  while negative ESD spike voltages produce current flow from negative rail  22  via D 4  and Q 4  to metal conductive element  18 .  
         [0014]    ESD protection circuit  10  includes unity gain amplifier A 1  having an input coupled to output  14  while its output is coupled to conductive elements  26  and  20 . A second poly-resistor rp 2  is coupled between metal conductive elements  20  and  26 . Typically, the resistances of rp 1  and rp 2  are small (150 ohms or less).  
         [0015]    The effect of metal conductive elements  16 - 26 , resistors rp 1 , rp 2 , and the relatively large base-emitter junctions of Q 1 -Q 4  is to generally increase the parasitic capacitance seen between metal conductive elements  16 , 18  and  20 , 26  due to the structure of the integrated circuit as will be discussed later in more detail. This increased capacitance is undesirable as it can prevent detection of small voltages applied to input  12 . However, unity gain amplifier A 1  of the present invention minimizes this unwanted parasitic capacitance by maintaining a zero voltage difference between the metal conductive elements as will be further explained.  
         [0016]    Referring to FIG. 2, integrated circuit  30  is shown in simplified form. IC incorporates ESD protection circuit  10  of the present invention. Integrated circuit  30  includes at least one input  32  coupled to the input  12  of circuit  10  the output  14  of which may be coupled via rp 1  to an analog signal processor shown at  34 . A probe, for example, may be attached at input  32  to detect small voltage differences (such as from a pressure sensor). The voltage differences are processed by signal processor  34  to provide desired information that is the displayed by output display unit  36 .  
         [0017]    Turning now to FIG. 3 there is shown a simplified, partial cross sectional view of monolithic integrated circuit (IC)  40  useful for describing the structure of diode-connected transistors Q 1  and Q 2  of FIG. 1. IC  40  is conventional in structure and includes P-type substrate  42 . Isolated N-well  44  is constructed by providing a layer of N-type epitaxial semiconductor material on substrate  42  and diffusing isolation ring  46  through the N-type layer into P substrate  42 . Q 1  is then constructed by diffusing P-type base regions  48  and  50 , as well as N-type emitter region  52  into isolated N-well  44 . The P+-type collector region  54  of Q 1  may be formed in isolation ring  46 . Similarly, using known and conventional photolithographic techniques, isolated P-well  56  is constructed by providing a P-type layer of semiconductor material on P substrate  42 . Next, a buried layer  58  of N-type semiconductor material is formed into both P substrate  42  and the P-well. Isolated P-well  56  is completed by diffusing N-type isolation ring  60  through the P-type layer into buried layer  58 . Q 2  is formed by diffusing base regions  62  and  64 , as well as emitter region  66 , into isolated P-well  56 . Metal conductive elements  16  and  18  (FIG. 1) are formed by selectively patterning metalization layers  68  and  70 , the latter of which makes contact to output  14 . Poly-resistor rp 1  is grown and contacts layers  68  and  70 . Similarly, base regions  50  and  62  of Q 1  and Q 2  are connected by metalization layer  72 . It is understood that Q 3  and Q 4 , as well as rp 2 , are likewise constructed as aforementioned.  
         [0018]    As described above, the selective patterned metalization layers as well as the two poly-resistors, which overlay the isolated wells, form one plate of a capacitor at input  12 . Isolated wells  44  and  56  create the second plate of the aforementioned capacitor. However, since amplifier A 1  provides unity gain feedback across the two plates of the capacitor, a zero voltage is maintained thereacross. Thus, the effective capacitance is substantially zero.  
         [0019]    Referring now to FIG. 4 there is described additional ESD protection circuit  80 . Circuit  80  functions similar to circuit  10  described above utilizing NMOS transistors instead of bipolar transistors. Circuit  80  includes input  82  which may also be an input/output pad of a monolithic integrated circuit. Input  82  is coupled via resistor r 1  (a poly-resistor, for example) to output  84 . Output  84  is coupled to internal IC circuitry (not shown) as already described above. A n-channel MOSFET device Q 1  is coupled between input  82  and common terminal  86  via its source and drain main electrodes while the gate control electrode thereof is connected to its source electrode. A second n-channel MOSFET device Q 2  is coupled between common terminal  86  and terminal  88  to which ground reference is applied. Hence, the drain and source main electrodes of Q 2  are connected to common terminal  86  and terminal  88  while the gate control electrode thereof is connected to its source electrode. Because Q 1  and Q 2  are formed in a P-type substrate, such as shown in FIG. 3, a parasitic P/N junction exists between the substrate and the drain electrodes thereof. Consequently, a high positive ESD voltage occurring at input  82  with respect to ground reference will produce current flow through Q 1  and Q 2 . The high voltage causes Q 2  to operate in a reverse breakdown or snap back mode, as understood, to thereby clamp the input to essentially the voltage developed across Q 2  in the snap back mode of operation. Similarly, a high negative ESD voltage occurring at input  82  with respect to ground reference causes current flow from ground reference to input  82  via Q 2  and Q 1 . Q 1  will operate in a reverse breakdown or snap back mode to clamp input 82  thereat as previously described.  
         [0020]    Common terminal  86  is shown coupled via resistor r 2  (which may be a poly-resistor) to additional common terminal  90 . A pair of NMOSFET devices Q 3  and Q 4 , which have their respective main electrodes coupled in series to one another are shown serially coupled between output  84  and terminal  88 . The gate electrodes of each of these two NMOSFET devices are connected to their respective source electrodes. Additional common terminal  90  also forms the interconnection between the drain electrodes of Q 3  and Q 4 . Unity gain amplifier A 1  has an input coupled to output  84  and an output coupled to additional common terminal  90  in the same way as illustrated in FIG. 1.  
         [0021]    Q 3  and Q 4  function in a like manner as described previously with respect to Q 1  and Q 2  of protection circuit  90 . Thus, output  84  will be clamped to the respective snap back voltages of either Q 3  and Q 4  responsive to ESD voltages exceeding the respective break down voltage of the two devices.  
         [0022]    Hence, what has been described above is a novel and inventive ESD protection circuit for protecting internal integrated circuitry from ESD damage. The ESD protection circuit uses feedback to reduce or severely limit the parasitic capacitance formed at the input thereof due to the structure of the integrated circuit in which the protection circuit is formed. As an example, the ESD protection circuit may be incorporated with a signal processor integrated circuit for measuring small input voltages applied to the input of the integrated circuit. Various changes may be made in the function and arrangement described in connection with the exemplary embodiments without departing from the spirit and scope of the invention as set forth in the appended claims.