Abstract:
A process and structure for fabricating a non-volatile memory cell through the formation of a source and drain region and a charge trapping layer located therebetween is presented. E-fields for generating trapped charges are formed through using poly-edge discharge techniques wherein the gate structures of the memory cells are laterally separated from the vertical region of the source and drain regions. The gate structure forms a laterally directed e-field through the charge trapping layer to one of the source and drain regions which enables the charge to be trapped and retained in an area that is lateral to the source and drain regions. Lateral separation of the gate from the source and drain regions is maintained through the use of spacers which may take the form of insulated polysilicon structures or in an alternate embodiment may take the form of insulating spacers located on the sidewalls of the gate structure.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. The Field of the Invention  
           [0002]    The present invention relates generally to semiconductor memory devices and more particularly to programmable memory devices.  
           [0003]    2. The Background of the Invention  
           [0004]    Non-volatile memory storage devices have become very ubiquitous in modern electronic applications. Non-volatile memories include read only memory (ROM) and various programmable and erasable variations therefrom, including programmable read only memory (PROM), erasable and electrically erasable programmable read only memory and other higher speed derivations therefrom. Another type of memory device includes a flash EPROM which has the capability of electrically erasing, programming, and reading a memory cell within the memory device.  
           [0005]    A memory cell formed within a traditional flash EPROM has been traditionally formed using floating gate transistors, in which the data is stored in a cell by charging or discharging the floating gate. The floating gate has traditionally been comprised of conductive materials such as polysilicon which is insulated from the channel located between the drain and source of the transistor by a thin layer of insulative oxide or other insulating material. Under this traditional floating gate approach, data is stored in the memory cell by charging or discharging the floating gate. The floating gate is charged by applying a large positive voltage between the gate and the source or drain. Such an approach relies on the electron tunneling mechanism for storing the charge in the gate.  
           [0006]    Alternatively, potentials such as electrical voltages may be applied to induce high energy electrons in the channel of a cell which are injected across the insulator of the floating gate. Such an alternative approach employs an avalanche mechanism for storing the charge within the floating gate. The voltage on the control gate or word line when divided by the coupling ratio of the memory cell results in a first voltage between the control gate and floating gate and a second voltage between the floating gate and the source or drain. An exemplary calculation of a 50% coupling ratio implies that half of the voltage applied to the control gate appears across the oxide between the floating gate and the source or drain. Such a voltage between the floating gate and the source or drain causes electrons to tunnel or to be injected into the floating gate through the thin insulator. When the floating gate is charged, the threshold voltage for causing the memory cell to conduct is increased above the voltage applied to the word line during a read operation. Thus, when the charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interrupted as a binary 1 or a 0, depending on the polarity of the sensing circuit.  
           [0007]    In order to establish the opposite memory state, the floating gate is discharged through a typical tunneling process between the floating gate and the source or drain of the transistor, or between the floating gate and the substrate. That is to say, the floating gate may be discharged through the source by establishing a large positive voltage from the source to the gate while the drain is left at a floating potential. The high voltages used to charge and discharge a floating gate place significant design restrictions on flash memory devices, particularly as the cell dimensions and process specifications are reduced in size. Thus, the coupling ratio for the memory cells becomes a critical design parameter.  
           [0008]    Memory cell designs, other thin those employing a floating gate, have been proposed. For example, ONO EPROM memory cells employ a trapping dielectric architecture as depicted in FIG. 1. The memory cell  10  includes a P-type silicon substrate  12  with an N+ drain  14  and an N+ source  16  implanted therein. In place of a traditional gate oxide, a non-conducting composite comprised of an oxide layer  28 , a nitride layer  18 , and another oxide layer  20 , separate the polysilicon gate  22  from the channel  24 . Oxide layer  28 , nitride layer  18 , and oxide layer  20  combine to form the ONO layer  26 . It should be further pointed out that ONO layer  26  intentionally extends beyond the length of channel  24  out into the regions overlapping drain  14  and source  16 . Such an overlap enables the trapping of the charge during the programming process as described below.  
           [0009]    ONO memory cell  10  is programmed or written to by applying voltages to drain  14  and gate  22  while simultaneously grounding source  16 . By way of example, a 10 volt potential may be applied to gate  22  with a 9 volt potential applied to drain  14 . Such voltages generate electrical fields causing an inversion in channel  24  from source  16  to drain  14 . Such a difference in potential in the presence of the electrical field causes electrons to migrate from source  16  and begin accelerating toward drain  14 . In the migration toward drain  14  they gain energy and eventually gain sufficient energy to pass through oxide layer  20  and become trapped in nitride layer  18 . The probability of such electrons traversing oxide layer  20  is maximized when there energy is also which occurs in a concentrated region nearest drain  14 . Such high energy electrons, also known as hot electrons, become trapped in nitride layer  18  and remain concentrated or stored therein. Because nitride layer  18  is largely nonconductive, the electrons in nitride layer  18  do not spread throughout nitride layer  18  and remain in the localized trapping region near drain  14 . It should be recalled that this is in contrast to memory cells implemented using floating gate technology wherein the retained charge is not locally trapped but rather distributed evenly across the entire gate region. Because of this distribution, the threshold for the entire gate increases as more charge is retained by the gate.  
           [0010]    In contrast, for memory cells implemented according to FIG. 1 using a nitride layer or other similar low or nonconductive materials, the gate threshold voltage is altered only in the localized charge-trapping region. In both the floating gate or conductive gate implementation as well as in the low or nonconductive gate memory cell designs, an increase in the gate threshold voltage causes the current flowing through the channel to decrease. Such a reduction increases the programming time necessary for injecting an identifiable charge into the charge trapping region. In a ONO memory cell design, the programming time is reduced due to the localized charge trapping that is possible in a conductive floating gate memory cell implementation.  
           [0011]    While the overlapping of the ONO composite  26  into the drain  14  and source  16  regions results in the creation of an e-field in the overlapping regions that enables charge trapping as described above, it would be desirable to provide a memory cell architecture that reduces the program and erase voltages and current necessary for trapping charge that is retainable and readable as a logic level.  
         BRIEF SUMMARY OF THE INVENTION  
         [0012]    A non-volatile memory cell is presented that incorporates a phenomenon known as poly-edge discharge which creates an enhanced e-field which is very beneficial for the trapping of charges in a memory device. In one embodiment of the present invention, a non-volatile memory cell is comprised of source and drain regions formed within a semiconductor substrate. The source and drain regions are separated with an ONO charge trapping layer located at least partially between the source and drain regions.  
           [0013]    In a direction generally laterally from the source and drain planar regions, a gate is formed that has an edge or point from which the e-field is generated. The gate is generally in a location lateral from the source and drain regions such that any charge to be trapped is done so in a region lateral as opposed to vertically above a source or drain region. In one embodiment, the gate structure is maintained or formed lateral to the source and drain regions through the use of a spacer which may typically be comprised of insulative materials such as an oxide or a silicon nitride material that is insulated from the gate. In one embodiment the spacer is comprised of polysilicon material which is surrounded by insulative oxide.  
           [0014]    In another embodiment, the charge trapping layer is formed between the drain and source regions and may even extend over the source and drain regions with the gate being located, preferably central between the source and drain regions. In order to ensure that the gate does not overlap the source and drain regions, nonconductive or insulative spacers are formed on the sidewall of the gate such that the gate does not extend through the entire length of the channel region between the source and drain regions. Such insulative sidewall spacers induces the lateral e-field through the charge trapping layer such that the charge may be trapped in a region that is lateral to the source and drain areas.  
           [0015]    These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    In order that the manner in which the above-recited and other advantages and features of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:  
         [0017]    [0017]FIG. 1 illustrates a sectional view of a memory cell of the prior art utilizing ONO trapping material that extends over into the source and drain regions of the memory cell;  
         [0018]    FIGS.  2 A- 2 G illustrate the fabrication and structure of a memory cell having storage regions within the ONO layer that are adjacent to the source and drain regions that utilize poly-edge discharge techniques, in accordance with a preferred embodiment of the present invention;  
         [0019]    [0019]FIG. 3 depicts an alternate embodiment of a memory cell having a plurality of storage regions over a single channel area, in accordance with the present invention; and  
         [0020]    [0020]FIG. 4 depicts an alternate embodiment also employing poly-edge discharge for trapping charge in a charge trapping layer region adjacent to, rather than vertically over, the source and drain regions of the memory cell, in accordance with an alternate embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]    [0021]FIG. 2 depicts the fabrication of a memory cell structure, in accordance with a preferred embodiment of the present invention. In FIG. 2A, a semiconductor substrate  100  is prepared by forming a doped P-well  102  in semiconductor substrate  100 . A dielectric composite or trapping region is thereafter developed which consists of a three-layer stack of dielectrics (ONO)  104  consisting of a bottom layer of silicon dioxide  94 , a middle layer of silicon nitride (Si 3 N 4 )  96 , and a top layer of silicon dioxide  98 . The outside layers in ONO  104  may either be thermally grown or in the case of the silicon nitride, it may be deposited as a film. While the thicknesses of each component of ONO layer  104  may be varied depending upon the specific process employed, acceptable values for the top layer of oxide  98  may include 90 Å, with the nitride layer  96  assuming a thickness of approximately 20 Å, and the lower level oxide  94  assuming a thickness of approximately 70 Å.  
         [0022]    It should be recalled that the nitride layer  96  within ONO  104  is a nonconductor and forms the memory retention layer which functions to trap electrons or charge as they become injected therein. As a nonconductor, the nitride layer retains the trapped charge in the localized area and does not distribute it evenly throughout as is the case in floating gate technology.  
         [0023]    In FIG. 2B, photoresist  106  is applied using a traditional photo etching process wherein photoresist  106  is applied as a mask for etching ONO layer  104  for the formation of buried drain/source. The photoresist  106  is removed to facilitate diffusion processes for fabricating the source and drain regions of the memory cell. The fabrication of a source  110  and a drain  112 , using an N+ implant, defines the boundaries of the memory cell, in accordance with the preferred embodiment of the present invention.  
         [0024]    [0024]FIG. 2C depicts the further processing of source  110  and drain  112  through the application of a buried drain oxide  114  about the diffusion areas. FIG. 2D depicts the application of a polysilicon layer  116  with a follow-up nitride layer  118  about the entire memory cell region. Polysilicon layer  116  provides lateral spaces between the forthcoming gate and the drain or source. Through etching processes as seen in FIG. 2E, portions of polysilicon layer  116  and nitride layer  118  remain and straddle portions of either source  110  or drain  112  and a portion of the ONO layer  104 . As shown in FIG. 2F, oxide layers  120  are grown about the sides of polysilicon  116  and nitride  118  to provide appropriate insulation. In FIG. 2G of the present embodiment, an additional polysilicon layer  122  is deposited about the entire upper surface of the overall structure. This layer, gate polysilicon  122 , provides the word line for an array of memory cell devices.  
         [0025]    It should be recalled that prior art memory devices have employed a ONO layer which extends significantly over the drain or source regions of a memory cell architecture. As such, the charge defining the logical state to be stored is trapped in the nitride layer of the ONO structure at a position within the nitride layer that is located on top of the drain or source region due to the location of the gate in relationship to the drain or source device. Because of the overlapping relationship with the ONO layer and the drain and gate configuration, an e-field was generated which was spread about the entire surface area that is common with the ONO layer and the drain or source region. As such, the intensity of the e-fields is directly proportional to such a common area between the gate and the drain or source regions. The e-field created between the regions which passes through the ONO layer causes the migration and trapping of charge within the nitride inner layer.  
         [0026]    As shown in FIG. 2G, and in accordance with the present invention, the ONO layer  104  does not substantially overlap the source or drain regions of the semiconductor device. Additionally, the gate region of the structure, or in other words, gate polysilicon layer  122  is spaced about the drain and source regions so as to create an e-field path between the gate and the source or drain that does not involve a directly vertically overlapping arrangement. For example, as seen in FIG. 2G, the first polysilicon layer  116  provides a spacing arrangement for gate polysilicon  122 , to be spaced a notable distance from the source or drain regions. For example, drain  112 , as depicted in FIG. 2G, is spaced a physical distance  124  from gate polysilicon  122  due to the spacing functionality of polysilicon  116 . This spacing distance  124  is traversed by ONO  104  between gate polysilicon  122  at a point  126  and drain  112 . As such, the presence of a voltage differential between gate polysilicon  122  and drain  112  as separated by polysilicon  116  induces the trapping of electrons or holes within the nitride layer of ONO layer  104  between gate polysilicon  122  at a point  126  and drain  112 . In a practical application of the present invention, polysilicon layer  116  may extend the length of drain  112  and be perpendicular to wordline gate polysilicon  122 . Furthermore, polysilicon layer  116  may be coupled to drain  112  such that they may be biased similarly to drain  112  or, alternatively, polysilicon layer  116  may be coupled to a different potential for programming, erasing or reading.  
         [0027]    It should be further evidenced that the generation of an e-field between gate polysilicon  122  and drain  112  occurs between a point  126  on gate polysilicon  122  and drain  112 . The point or corner  126  on the gate  122  region induces a high e-field between the gate polysilicon  122  and drain  112 . Such a phenomenon is termed herein “poly-edge discharge.” Such an intense e-field due to the poly-edge discharge effect results in a more easily generated and trapped charge within the nitride layer of ONO layer  104  between gate polysilicon  122  at point  126  and drain  112 . Therefore, such an increase in the e-field results in the ability to reduce the program and erasure voltages and current associated with the use of poly-edge discharge techniques. Such an improvement also facilitates an increased coupling ratio of up to 100% over traditional flash memory cells. Such a technique also positively impacts the program and erasure speeds due to the localization of the high V t  region.  
         [0028]    By way of example, the memory cell as depicted in FIG. 2G, may be programmed by placing drain  112  and polysilicon  116  at a potential of between 3 to 5 volts. The word line or gate polysilicon  122  is placed at a potential of between 0 and −5 volts. Such potentials allow for the injection of electrons from point  126  of gate polysilicon  122  into the nitride layer of ONO layer  104 .  
         [0029]    In order to erase the exemplary cell of FIG. 2G, the word line or gate polysilicon  122  is placed at a potential of between 3 to 5 volts with the P-well or the bulk region being placed at a potential of between 0 and −5 volts with all other contacts floating. The exemplary memory cell of the present invention may be read by placing drain  112  and polysilicon  116  at a potential of between 3 to 5 volts with the word line or gate polysilicon  122  being placed at a potential of between 3 to 5 volts with source  110  placed at 0 volts.  
         [0030]    [0030]FIG. 3 illustrates an alternate embodiment exhibiting a two cell per channel structure, in accordance with an alternate embodiment of the present invention. In this embodiment, polysilicon  116  is duplicated in polysilicon  216  that facilitates increased densities through the placement of an additional point  226  on gate polysilicon  122 .  
         [0031]    [0031]FIG. 4 depicts an alternate embodiment of the memory cell of the present invention. In the present embodiment, a substrate  150  having a P-well  102  configuration is generated wherein a source  152  and a drain  154  are defused therein. Thereafter, on the top of substrate  150 , an ONO layer  156  is deposited which is comprised, as described above, of an oxide/nitride/oxide composite capable of trapping or storing charge within the nitride layer.  
         [0032]    A polysilicon gate  162  is formed upon ONO layer  156 . Polysilicon or gate  162  is formed so as to be within the distance between source  152  and drain  154 . As the present embodiment also employs poly-edge discharge techniques for enhancing the e-field for the storage of charges within the nitride layer, the polysilicon or gate  162  is spaced from the edges of the source and drain regions through the use of spacers  158  and  160  located on the edges or sidewalls  159 ,  161  of gate  162 . Spacers  158 ,  160  provide lateral narrowing of polysilicon gate  162  such that the charge traverses laterally or sideways between a gate and either a source or drain. The formation of non-conducting spacers  158  and  160  allow the formation of a storage region within the nitride layer as defined by storage regions  164  and  166  to be located substantially away from any vertical overlap areas of source  152  or drain  154 .  
         [0033]    Furthermore, consistent with the benefits of poly-edge discharge techniques, the program and erase voltages including the current for performing such functions may be reduced due to the enhanced e-field associated with the edges  168 ,  170  of gate  162  that most closely correspond to the respective sources and drains. Therefore, the storage of charge that facilitates the functionality of memory cell  140  is stored within the trapping or nitride layer of ONO  156  that is located in a region predominately lateral to rather than vertically above the source or drain regions. The present embodiment further facilitates the advantages of enhancing or improving the program and erase speeds because of the localized high V t  region as well as the improved coupling ratio, up to 100%, over traditional flash memory cells.  
         [0034]    The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.