Abstract:
The present invention is an exposure information setting circuit for use in photographic cameras which calculates the required exposure time in response to input signals indicative of APEX indices and produces a signal indicative of the exposure time. The circuit is constituted mainly by an integrated circuit which takes advantage of the fact that although the absolute values of electrical characteristics of the circuit elements may fluctuate, particular ratios of such values can be maintained in a predetermined ratio with good precision. This maintenance of the particular ratios can be achieved without requiring any supplementary voltage sources or/and adjustment resistors, whereby large-scale production of the exposure information setting circuit at low cost is possible.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a circuit for use in photographic cameras, and more particularly, to an exposure information setting circuit which produces a signal indicative of shutter speed upon receipt of signal indicative of the brightness of the object to be photographed. 
     In photography it is necessary to set the camera at the proper shutter speed and F number or aperture setting with respect to a preselected ASA or DIN number. These three factors, i.e., shutter speed, F number and ASA number are determined by the brightness of the object to be photographed. Since each factor is variable, it is photographer&#39;s choice to set these three factors to his taste. If, however, two of the factors are fixed, the remaining factor will be determined by the brightness of the object. In an automatic exposure control system for use in single-lens reflex camera employing through the lens (TTL) system, there have been employed an exposure information setting circuits which operate to calculate a suitable exposure time Tv in accordance with the so-called APEX system given by the following equation. 
     
         Tv=Bv-(Av-Sv)=Bv+Sv-Av                                     (1) 
    
     wherein Bv is the given value of objective brightness, i.e., the brightness of the scene to be photographed, Sv is the film sensitivity value and Av is the aperture value. These values Bv, Sv and Av are referred to as APEX indices hereinbelow. 
     In FIG. 1, there is shown an exposure information setting circuit which includes a photodiode PD 2  and diode D 1   connected in series across a first power source E 1 . When the photodiode PD 2  receives light from the object to be photographed, a voltage signal V B  which is related to the exponential value of the brightness is produced across the diode D 1 . Here, the voltage signal V B  is identical with the APEX index Bv of brightness value given in the equation (1). The principle circuit further includes potentiometers PM 3  and PM 4  which are parallel to one another and are connected to a second power source E 2 . A sliding arm or wiper W 3  of the potentiometer PM 3  slides along the potentiometer to be set in a position corresponding to film sensitivity and is connected to junction P 2  between photodiode PD 2  and diode D 1 . A wiper W 4  of the potentiometer PM 4  slides along the potentiometer to be set in a position corresponding to aperture value and is connected to an output terminal P 4 . In this circuit the voltage drop V S  between the wiper W 3   and a junction P 3  of potentiometers PM 3  and PM 4  is identical with the APEX index Sv of film sensitivity value and the voltage drop V A  between the wiper W 4 , and the junction P 3  is identical with the APEX index Av of aperture value. 
     According to the circuit described above, the voltage V T  which appears across ground line P 1  and output terminal P 4  can be given as; 
     
         V.sub.T =V.sub.B +V.sub.S -V.sub.A                         ( 2) 
    
     in other words, the circuit performs a calculation corresponding to the solution of the above described equation (1) showing APEX system. 
     Identical results can be obtained in the case where the output P 4  of the circuit shown in FIG. 1 is taken in reference to a junction P 3  &#39; of the negative terminal of the power source E 2  and potentiometers PM 3  and PM 4 . In this case, the voltage drop V S  &#39; between the wiper W 3  and the junction P 3  &#39; corresponds to the APEX index Sv of film sensitivity value, while the voltage drop V A  &#39; between the wiper W 4  and the junction P 3  &#39; corresponds to the APEX index Av of aperture value, thus, the output V T  of the circuit can be given as; 
     
         V.sub.T =V.sub.B -V.sub.S &#39;+V.sub.A &#39;                      (3) 
    
     the circuit of FIG. 1 employs two power sources E 1  and E 2 . However, it is undesirable for the camera to have power sources occupy much space in the limited space available in the camera. Accordingly, there has been proposed a circuit which has the same function as that described above while employing only one power source. One example of such a circuit is shown in FIG. 2 in which the input voltage V B  produced across the diode D 1  is supplied to a noninverting input of an operational amplifier A 1 . The output terminal of the operational amplifier A 1  is connected to one junction P 7  of potentiometers PM 5  and PM 6  which are connected in parallel with each other. The other junction P 8  of the potentiometers PM 5  and PM 6  is connected to ground through series connection of a transistor Q 12  and an adjusting resistor R 11 . The transistor Q 12  has its collector connected to the junction P 8  and its emitter connected to the adjusting resistor R 11 . The base of the transistor Q 12  is connected to a transistor Q 11  at its collector. The transistor Q 11  has its base and emitter connected to each other to function as a diode, has the emitter connected to ground and has the collector connected to the positive side of a power source such as E 1  through a suitable resistor R 10 . These transistors Q 11  and Q 12  and adjusting resistor R 11  are connected to form a known type of constant current generator. The wiper W 5  of the potentiometer PM 5 , provided for establishing voltage signal V S  indicative of the APEX index Sv of film sensitivity value, is connected to the inverting input of the operational amplifier A 1  to form a negative feedback circuit, so that the voltage drop appearing between the input terminals P 5  and P 6  is approximately maintained at 0 (volt). Accordingly, the signal appearing at the wiper W 5  is approximately equal to the signal appearing at the noninverting input P 5 , that is, the signal V B . The wiper W 6  of the potentiometer PM 6 , provided for establishing voltage signal V A  indicative of the APEX index Av of aperture value, is connected to an output terminal P 9 . As a result, the voltage between the ground and the output terminal P 9  is (V B  +V S  -V A ) which is equal to the above mentioned value of output V T  indicative of exposure time. Thus, by the employment of the operational amplifier A 1  and transistors Q 11  and Q 12 , the circuit of FIG. 2 permits calculation of exposure time without requiring a supplementary power source, such as power source E 2 . Further information for this type of circuit shown in FIG. 2 is described in detail in U.S. Pat. No. 2,936,842 of Nanba et al or U.S. Pat. No. 3,977,011 of Matsuda. 
     However, according to this type of circuit as described above, it is inevitable to provide the adjusting resistor R 11  for the reasons described hereinbelow. 
     In an operational circuit such as shown in FIG. 2 or the circuit of FIG. 1, presuming an ambient temperature of 25° C., the value of the voltage change which corresponds to a 1-step change of the APEX index value is required to be 18 mv. This value is determined in reference to the current-voltage characteristics of the semiconductor employed as a logarithmic conversion element. In a diode, for example, a two-fold change in current therethrough normally corresponds to a change of 18 mv across the terminals thereof, and in a transistor a two-fold change in collector current corresponds to an 18 mv change in base-emitter voltage. Thus, in FIG. 1, when there is a two-fold change in the amount of light incident on photodiode PD 2 , i.e., when there is a 1-step change of APEX index value, there is a two-fold change in photocurrent, and hence an 18 mv change in voltage V B  across the terminals of diode D 1 . The potentiometer circuit in the right-hand portion of FIG. 1 or FIG. 2 is required to accurately respond to input signals and accurately produce output signals that change 18 mv for each 1-step change in APEX value. 
     These requirements can be met in closely controlled manufacturing conditions. However, at present, such requirements can not be met in large-scale production. In other words, if it were possible to easily obtain, in large quantity, transistors Q 11  or Q 12  in which the requisite value of collector current could be obtained without need of adjustment, or if it were possible to easily obtain potentiometers having required resistance characteristic curves, there would be no problems. In large-scale production ensuring accuracy of values of circuit components beyond a certain point is considered too costly, and it is a current practice to tolerate a variation of 20% above or below the designed values of the characteristics of components. In the circuit of FIG. 2, therefore, in order to accurately obtain a signal voltage of 18 mv corresponding to a 1-step change in exposure time information, it is necessary to adjust the current which flows in potentiometers PM 5  and PM 6 . To achieve this, it is necessary to add adjusting resistor R 11  to the exposure control circuit, which for the most part is constituted as an integrated circuit module. Because of this necessary addition of an extra resistor there is the disadvantage that extra work for positioning wiring, and adjustment is necessary, and hence the cost of production of the exposure control circuits is increased. 
     OBJECT OF THE INVENTION 
     It is an primary object of the present invention to provide an exposure information setting circuit which requires only one power source without requiring the use of supplementary adjusting resistors. 
     It is another object of the present invention to provide an exposure information setting circuit of the above described type which can be provided substantially in the form of an integrated circuit module. 
     SUMMARY OF THE INVENTION 
     In order to accomplish these and other objects, the present invention makes use of the fact that, although variations in conditions during large-scale production of integrated circuits make it practically impossible to guarantee maintenance of values of electrical characteristics of circuit elements within close tolerances in all circuits, it is possible to accurately maintain particular ratios between values of electrical characteristics of circuit elements in a whole series of circuits, since in any one circuit the absolute values of electrical characteristics of the circuit elements are all affected in more or less the same way by a variation in production conditions. In the circuit of the invention accurate production of requisite output signals depends merely on maintenance of ratios of characteristic values of circuit elements, and there is no need for costly control to achieve precise characteristic values, or for provision of supplementary adjustment means. 
    
    
     These and other object and features of the present invention will become apparent from the following descriptions taken in conjunction with preferred embodiments thereof with reference to the accompanying drawings, in which; 
     FIGS. 1 and 2 are drawings referred to in the foregoing description, FIG. 1 being a principle circuit for the exposure information setting circuit and FIG. 2 being one example of conventional type of exposure information setting circuit; 
     FIG. 3 is a circuit diagram of one embodiment of the present invention; 
     FIG. 4 is one embodiment of a shutter mechanism operation circuit to be coupled with the circuit of FIG. 3; 
     FIGS. 5, 6, 7 and 8 are circuit diagrams of various modifications of the portion of the circuit of FIG. 3 to be formed in an integrated circuit; and 
     FIG. 9 is a modification of a potentiometer portion to be employed in the circuit of FIG. 8. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Before the description of the present invention proceeds, it should be noted that like parts are designated by like reference numerals throughout the accompanying drawings. 
     Referring to FIG. 3, the exposure information setting circuit of the present invention comprises a voltage setting circuit A including resistors R 7  and R 8  and transistor Q 6  connected in series and coupled to a power source F including a battery E 3  and a switch SW connected in series. In the voltage setting circuit A, the transistor Q 6  has its collector connected to the resistor R 8  and its emitter connected the negative terminal of the battery E 3 , which is grounded. The base of the transistor Q 6  is connected to the junction of resistors R 7  and R 8  so that the transistor Q 6  is excited to generate a constant voltage between the collector and emitter thereof. 
     Coupled to the voltage setting circuit A is an exposure information developing circuit B including a capacitor C 2 . One end of capacitor C 2  is connected to the voltage setting circuit A at the junction of resistor R 8  and the transistor Q 6  via terminal P 01  and the other end is grounded. Connected to the terminal P 01  is the cathode of the photodiode PD 1 , while the anode thereof is connected to the collector of a transistor Q 7  via terminal P 02 . The emitter of the transistor Q 7  is connected to the ground and base thereof is connected to wiper W 1  of potentiometer PM 1 . The potentiometer PM 1  is connected in parallel with another potentiometer PM 2  and also in parallel with resistor R 6  which is described later. The wiper W 2  of the potentiometer PM 2  is connected to the output terminal To of the exposure information setting circuit. 
     Coupled to the exposure information developing circuit B is an amplifier C including a field effect transistor (referred to as FET hereinbelow) Q 8  having the gate thereof connected to the terminal P 02 . The source of the FET Q 8  is connected to the positive side of the battery E 3  through a suitable resistor R 9  and the drain of the FET Q 8  is connected, through a transistor Q 9  serving as a diode, to the ground. The source of the FET Q 8  is also connected to the base of transistor Q 10 . The emitter of transistor Q 10  is connected to the positive side of the battery E 3  and the collector of transistor Q 10  is connected to the positive side of the potentiometer PM 1 . 
     When the switch SW is closed, voltage at the terminal P 01  rises in accordance with the characteristic curve determined essentially by the time constant of capacitor C 2  and resistors R 7  and R 8 . As a result of the rise in voltage at the terminal P 01  and the incidence of light on photodiode PD 1 , the voltage at the terminal P 02  similarly rises. When the voltage at the terminal P 02  reaches a predetermined level suitable for stable circuit operation, the charge stored by the photodiode PD 1  acting as a capacitor is rapidly discharged through transistor Q 7 . Note that when stable circuit operation conditions are reached, the voltage level at the terminal P 01  is set to be generally equal to or slightly greater than that at the terminal P 02 . In this manner, photocurrent proportional to the brightness of light incident on photodiode PD 1  is obtained. Also note that the capacitor C 2  is provided for reducing the time the circuit is in the transient state and for rapidly achieving the stable circuit operation conditions when the power is first supplied, upon turning on of switch SW. More specifically, by the provision of the time constant circuit consisting essentially of capacitor C 2  and the resistors R 7  and R 8 , stable circuit operation conditions are achieved about 10 msec after closure of the power source circuit E. Without provision of capacitor C 2 , it would take several seconds to achieve circuit stablity. 
     In the event that the incident light should increase to rise the gate voltage of the FET Q 8 , the voltage at the drain thereof decreases, and in turn, the voltage at the collector of the transistor Q 10  increases. Since, as described later, a constant current flows in potentiometer PM 1 , rise of collector voltage of transistor Q 10  is transmitted to the base of the transistor Q 7 . Therefore, the collector voltage of the transistor Q 7  is decreased. Consequently, the gate voltage of the FET Q 8  is maintained at a predetermined value, regardless of fluctuation of gate voltage thereof, by a network of negative feedback circuit as described above formed in the amplifier C. In other words, the voltage drop across the photodiode PD 1  is maintained at a predetermined value in accordance with the changes in the amount of light incident on photodiode PD 1 , so that good response of the photodiode is ensured. 
     The potentiometers PM 1  and PM 2  described as connected in parallel with each other, are in turn connected in parallel with the resistor R 6  through terminals P 10  and P 11 . The wiper W 1  of the potentiometer PM 1  is previously adjusted to produce, between the wiper W 1  and the terminal P 10 , a voltage signal V S  indicative of the film sensitivity value while the wiper W 2  of the potentiometer PM 2  is previously adjusted to produce, between the wiper W 2  and the terminal P 10 , a voltage signal V A  indicative of the aperture value. Since the wiper W 1  is connected to the base of the transistor Q 7  producing a voltage signal V B  indicative of the brightness, the output terminal To produces the exposure information signal V T . 
     Still referring to FIG. 3, the description is now directed to a constant current generator D. The constant current generator D comprises transistors Q 1 , Q 2 , Q 3  and Q 4  and resistors R 1 , R 2 , R 3  and R 4 . The transistors Q 1  and Q 2  have their bases connected to each other and their emitters connected to each other through the resistor R 1 . The emitter of the transistor Q 2  is further connected to ground through the resistor R 4 . On the other hand, the transistors Q 3  and Q 4  have their bases connected to each other and their emitters connected to each other through the resistors R 2  and R 3  connected in series. The junction between the resistors R 2  and R 3  is connected to the positive side of the battery E 3 . The collectors of the transistors Q 1  and Q 3  are connected to each other and the collectors of the transistors Q 2  and Q 4  are also connected together. Furthermore, the transistor Q 2  has its base and collector connected together and the transistor Q 3  has its base and collector connected to each other. The constant current generator D as described above is coupled with a voltage setting circuit E in a manner described hereinbelow. The base of the transistor Q 1  is further connected to the base of transistor Q 5 , namely output transistor Q 5 . The emitter of output transistor Q 5  is connected to ground through resistor R 5  and the collector of transistor Q 5  is connected to resistor R 6 . 
     It should also be noted that the electrical elements in the constant current generator D and the voltage setting circuit E, i.e., the transistors Q 1  to Q 5  and resistors R 1  to R 5  are provided as an integrated circuit on a semiconductor chip and that the transistors Q 1 , Q 2  and Q 5  are NPN type transistors and transistors Q 3  and Q 4  are PNP type transistors. The value of resistance offered by the resistor R 6  is suitably smaller than, e.g., 1/10 to 1/5, that of the lumped resistance of potentiometers PM 1  and PM 2 . 
     Generally, during the production of large numbers of semiconductor integrated circuits, the base-emitter voltage characteristics and the resistance values of resistors vary considerably from circuit to circuit depending on the diffusion conditions, etc. Therefore, it is difficult to precisely achieve the required values in every circuit. However, since the area of any element on an integrated circuit chip is determined by a mask, it is possible to maintain good precision in the specific ratios of resistances of resistors or of transistor emitter areas, etc. The invention makes use of this characteristic of integrated circuits to provide a circuit in which the voltage across particular resistors is held close to required values, and accurately varying output signals are produced despite the fact that the electrical values of circuit elements may vary from the design values which are considered ideal with respect to the resistance values of potentiometers PM 1  and PM 2 . 
     In regard to the constant current generator D which is formed by a semiconductor integrated circuit, the emitter region areas of the transistors Q 3  and Q 4  are defined as respectively S 3  and S 4  and resistance values of the resistors R 2  and R 3  are defined as respectively R 2  and R 3 . Unless the value of various electrical elements such as resistors and capacitors is defined as represented by particular characters, the values of respective elements are represented by the respective reference characters hereinbelow. In the step of forming the semiconductor integrated circuit, the transistors Q 3  and Q 4  and the resistors R 2  and R 3  are designed to satisfy the relation given by the following equation. 
     
         S.sub.3 /S.sub.4 =R.sub.3 /R.sub.2                         (4) 
    
     this relation results in a voltage between the base and emitter of the transistor Q 3  equal to that of the transistor Q 4 . The ratio of collector currents I 1  and I 2  of the transistors Q 3  and Q 4 , respectively, is proportional to the ratio of areas in the emitter regions thereof. Accordingly, from the equation (4), the following equation is obtained. 
     
         I.sub.1 /I.sub.2 =S.sub.3 /S.sub.4                         (5) 
    
     it should be noted that, in the constant current generator described above, the resistors R 2 , R 3  and R 4  are not strictly necessary, but are merely provided to control the current flowing through the constant current generator. Generally, in a transistor where the base current is constant, the collector current varies in accordance with the change of collector-emitter voltage. For example, in the circuit of FIG. 3, if the voltage of the battery E 3  rises, the voltage between the collector and the base of transistor Q 4  will increase, thus increasing the collector current I 2  of transistor Q 4 . At the same time, this increase in the collector current I 2  produces a voltage increase across the resistor R 3 , and accordingly, the base-emitter voltage of the transistor Q 4  increases. As a result, because of this negative feedback effect, collector current I 2  is maintained at a constant value. In other words, the resistor R 3  is provided for establishing a self-biasing circuit while the resistor R 2  is provided for equalizing the base-emitter voltage of the transistor Q 3  with that of the transistor Q 4 . The resistor R 4  is also basically unnecessary, but is provided to prevent excessive rise of the base voltage of transistors Q 1  and Q 2 . 
     Considering now particularly the transistors Q 1  and Q 2 , since the bases of the transistors Q 1  and Q 2  are connected to each other, the relation among the transistors Q 1  and Q 2  and the resistor R 1  can be represented as follows; 
     
         V.sub.BE1 +I.sub.1 R.sub.1 =V.sub.BE2                      (6) 
    
     wherein V BE1  and V BE2  are base-emitter voltage of the transistors Q 1  and Q 2  respectively. According to the characteristics of the transistor, these voltages V BE1  and V BE2  can be expressed by the following equations; ##EQU1## wherein K is Boltzmann&#39;s constant, T is absolute temperature, q is electron charge and I S1  and I S2  are respectively the reverse saturation currents of the transistors Q 1  and Q 2 . By applying the equations (7) and (8) to the equation (6), the following equation is obtained; ##EQU2## The equation (9) can be further modified to obtain the following equation; ##EQU3## wherein V R1  is equal to I 1  ·R 1 . Since the reverse saturation currents I S1  and I S2  are proportional to the respective emitter region areas S 1  and S 2  of transistors Q 1  and Q 2 , and the collector currents I 1  and I 2  are proportional to the respective emitter region areas S 3  and S 4  of the transistors Q 3  and Q 4  from the equation (5), the equation (10) can be further modified to obtain the following equation; ##EQU4## 
     As is apparent from the equation (11), the voltage appearing across the resistor R 1  is determined by the ratios of the emitter region areas of transistors Q 1 , Q 2 , Q 3  and Q 4 . Also, since V R1  =I 1  R 1 , the values of the currents I 2  and I 1  are determined by the resistance value presented by the resistor R 1 . From the relation V R1  =I 1  R 1  and I 1  /I 2  =S 3  /S 4 , the voltage V R4  appearing across the resistor R 4  can be expressed as follows; ##EQU5## From the equation (12), it is understood that the voltage V R4  is determined by the ratio of resistance value of R 1  and R 4 . 
     The description hereinbelow is now particularly directed to the output transistor Q 5  and the resistor R 5  connected to the emitter thereof. 
     According to the characteristics of the transistor, the relation between the collector current I 5 , which is approximately equal to the emitter current, of the transistor Q 5  and the base-emitter voltage V BE5  of the transistor Q 5  can be expressed in the following equations; 
     
         V.sub.BE5 =KT/q·ln I.sub.5 /I.sub.S5              (13) 
    
     wherein I S5  is a reverse saturation current of the transistor Q 5 . Since the base of the transistor Q 5  is in common with the base of the transistor Q 2 , following equation is obtained; 
     
         V.sub.BE5 +I.sub.5 R.sub.5 =V.sub.BE2 +I.sub.3 R.sub.4     (14) 
    
     by applying equations (8) and (13) to the equation (14), following equation is obtained; ##EQU6## wherein V R5  =I 5  R 5  and V R4  =I 3  R 4 . Since the reverse saturation currents I S5  and I S2  are proportional to the respective emitter region areas S 5  and S 2  of the transistors Q 5  and Q 2 , it is understood from equation (15) that the voltage V R5  across the resistor R 5  is determined once the ratios of emitter region areas and collector currents of transistor Q 5  to those of transistor Q 2  are specified. 
     By way of example, consider the case in which the dimensions of the output transistor Q 5  are made equal to those of the transistor Q 2  and the collector current I 5  is made equal to the collector current I 2 . In this case, if the voltage V R5  across the resistor R 5  is set to be equal to the voltage V R4 , in other words, if the relation; 
     
         I.sub.2 R.sub.5 =I.sub.3 R.sub.4                           (16) 
    
     is satisfied, then the respective base-emitter voltages V BE5  and the V BE2  of transistors Q 5  and Q 2  become equal, and collector currents I 5  and I 2  of these transistors also become equal. The equation (16) can be rearranged as in a following equation; ##EQU7## From the equation (17), it is understood that the ratio of resistance R 5  to that of R 4  required to satisfy equation (16) is determined solely by the ratio of emitter area of transistor Q 3  to that of the transistor Q 4 . Therefore, since it is possible to design the resistor R 5  to satisfy ratio requirements of equation (17), it is possible to make the voltage V R5  across the resistor R 5  equal to the voltage V R4  across the resistor R 4 , and it is also possible to make the collector current I 5  equal to the collector current I 2 . 
     Next, the voltage V R6  across the resistor R 6  connected to the collector of the transistor Q 5  is taken into consideration, provided that the presence of the potentiometers PM 1  and PM 2  of FIG. 3 is disregarded for the moment and that the collector current I 5  of the transistor Q 5  is assumed to be simply flowing through the resistor R 6 , so as to simplify the description hereinbelow. When the collector currents I 5  and I 2  are made equal in the manner described above, voltage V R6  can be expressed as follows; 
     
         V.sub.R6 =I.sub.2 R.sub.6                                  (18) 
    
     since I 2  =S 4  /S 3  ·V R1  /R 1 , the equation (18) can be expressed as follows; 
     
         V.sub.R6 =S.sub.4 /S.sub.3 ·R.sub.6 /R.sub.1 ·V.sub.R1 (19) 
    
     furthermore, since V R1  =KT/q·ln S 1  /S 2  ·S 4  /S 3 , the equation (19) can be expressed as follows; ##EQU8## As is apparent from the equation (20), the voltage V R6  across the resistor R 6  is determined by the ratio of resistance R 6  to R 1 , and it is understood that the voltage V R6  is proportional to the absolute temperature T. 
     Now, consider the case in which the potentiometers PM 1  and PM 2  are connected in parallel with the resistor R 6  through the terminals P 10  and P 11 , as shown in FIG. 3. Assume that the potentiometers PM 1  and PM 2  are each required to specify information in 10 steps. In this case, at 25° C., the voltage required to be produced across the terminals P 10  and P 11  is 18 mv×10=180 mv. Also, by way of example, note that the potentiometers PM 1  and PM 2  are designed to have a parallelly connected combined resistance value of 10 times the value of the resistor R 6 . However, the actually achieved resistance in the integrated circuit obtained through known manufacturing steps has a variation, for example, in the range of ±30%, with respect to the designed value. Similarly, the potentiometers PM 1  and PM 2  have a certain degree of variation. The resistor R 6 , in the instance shown in FIG. 3, has a variation of ±30% while the potentiometers PM 1  and PM 2  have variations of ±20%. When the potentiometers PM 1  and PM 2  are not connected to the terminals P 10  and P 11 , the required voltage across the resistor R 6 , that, is between the terminals P 10  and P 11  is 198 mv, since the resistance value of the parallel connection of potentiometers PM 1  and PM 2  and the resistor R 6  equals R 6  /1.1, while R 6  /1.1×I 5  =180 mv, thus R 6  ×I 5  =198 mv. 
     With resistor R 6  having a variation of ±30% and potentiometers PM 1  and PM 2  having a variation of ±20%, one of the worst cases in the combination occurs when the resistor R 6  is varied 30% above the designed value while the potentiometers are varied 20% below the designed value. Accordingly, the resistance value of the resistor R 6  can be represented as 1.3R 6 , while the resistance value of the parallelly connected potentiometers PM 1  and PM 2  can be represented as 8R 6 . In spite of this variation in the resistor R 6 , the collector current of the transistor Q 5  is maintained at a predetermined value for the reasons described above. In the above described worst case, the voltage V 180  appearing between the terminals P 10  and P 11  is calculated as follows ##EQU9## 
     In other words, the value of voltage actually produced is 170 mv instead of the value of 180 mv supposed to be produced. As 18 mv corresponds to 1-step of potentiometer setting, this output voltage constitutes an error of (180-170)/18=0.56 of a step. 
     The situation in which this an error would result in any apparent effect in the output of the information setting circuit would be in the case where a low-speed film (e.g. ASA 6) is employed and the wiper W 1  is moved towards the upper terminal end P 10  of the potentiometer PM 1  while the camera shutter aperture is set at a minimum or close to a minimum value such as F32 and the wiper W 2  is moved to the lower terminal P 11  end of the potentiometer PM 2 . However, deliberate selection of such a combination of settings occurs only in the work of a specialist and application of such a combination in an automatic exposure control circuit is not in fact employed. In normal practical photography, such settings do not occur, and even if they did the effect of a 0.56 step error would not be unduly great, when compared with the photographic effect achieved by properly selecting such a combination of settings. For other potentiometer settings, a 0.56 step error is well within accepted limits of precision. Thus, the exposure information setting circuit of the present invention provides a circuit which, although it can be manufactured on a mass-production basis, does not require provision of a supplementary adjustment means in order to accurately calculate exposure information, so that the work steps and requirements for skilled work are reduced and the cost of production is lowered accordingly. 
     However, in the case where it is desired to completely eliminate this error as described above, an adjusting variable resistor (not shown) can be inserted between the terminals P 10  and P 11 , or between the lower end terminal of the potentiometer PM 2  and the terminal P 11  so as to adjust the voltage drop between the terminals P 10  and P 11  to substantially equal to a predetermined value, i.e., 180 mv. 
     Note that the base-emitter voltage V BE7  of the transistor Q 7  corresponding to the brightness signal of the object is proportional to the absolute temperature, since 
     
         V.sub.BE7 =KT/q·ln I.sub.7 /I.sub.S7              (21) 
    
     wherein I 7  is a photocurrent and I S7  is a reverse saturation current of the transistor Q 7 . It is, therefore, necessary to have the voltage obtained from the potentiometers PM 1  and PM 2  proportional to the absolute temperature. However, as is apparent from the equation (20), the voltage across the resistor R 6  is proportional to the absolute temperature. Accordingly, in the case where the resistance value of the resistor R 6  is comparatively large with respect to the combined resistance value of the potentiometers PM 1  and PM 2 , the voltage obtained between the terminals P 10  and P 11  will become substantially proportional to the absolute temperature when the resistor R 6  is connected in parallel to the potentiometers PM 1  and PM 2 . Thus, there will be an accurate computation of signal indicative of the exposure time by the circuit as a whole. 
     The output voltage signal V T  indicative of the exposure time is supplied to a shutter mechanism operating circuit of any known type such as one shown in FIG. 4. 
     Referring to FIG. 4, the shutter mechanism operating circuit G comprises a memory switch Sm and a memory capacitor Cm connected in series. The switch Sm has one end connected to the input terminal Ti which is further connected to the output terminal To of the exposure information setting circuit and the other end thereof connected to the capacitor Cm which is in turn connected to the ground. Thus the capacitor Cm memorizes the value of the output voltage signal V T  when the switch Sm is closed. This memorized signal, i.e., the signal V T , is integrated in an intergration circuit comprising a switch S 2 , a transistor Q 13  and a capacitor C 1  connected in series, and a switch S 1  connected in parallel with the capacitor C 1 . The memorized signal V T  is applied to the base of the transistor Q 13  for generating a current I m  determined by the signal V T  and this current I m  charges the capacitor C 2 . The charged voltage is applied to a holding circuit comprising a switching circuit SC and an electromagnet Mg connected in series. When the capacitor C.sub. 2 is suitably charged up to a predetermined level, the voltage across capacitor C 1  turns the switching circuit SC off, thus de-energizing the electromagnet Mg and automatically closing the window of the exposure system in the camera. It should be noted that the window is opened at the moment when the shutter of the camera is released. 
     The foregoing description is particularly directed to a case where the integrated circuit including constant current generator D and the voltage setting circuit E is formed to have the transistors Q 2  and Q 5  constructed with exactly the same features and arranged to produce the same collector currents I 2  and I 5 . The description hereinbelow is given to the general case where the characteristics as well as the collector currents I 2  and I 5  of the transistors Q 2  and Q 5  are different from each other. 
     From the equation (15), the relation between the voltages V R5  and V R4  can be expressed as follows; ##EQU10## From the equation (22), the current I 5  is expressed as follows; ##EQU11## While, on the other hand, from the equation (5), ##EQU12## therefore ##EQU13## Furthermore, since V R5  =I 5  R 5 , the equation (25) can be expressed as; ##EQU14## Accordingly, from the equation (26), it is possible to construct a desirable output transistor Q 5  and also a desirable resistor R 5 . 
     In the similar manner, since ##EQU15## From the equation (27), it is possible to construct a desirable resistor R 6  which produces a predetermined voltage V R6  thereacross. 
     In the case where the resistance values R 4  and V R6  are zero, the voltage R 4  is expressed as; ##EQU16## 
     Referring to FIG. 5 there is shown a constant current generator D&#39; and a voltage setting circuit E&#39; which are modifications of the same shown in FIG. 3. In the circuit of FIG. 5, the resistors R 4  and R 5  are eliminated to show the resistance values thereacross are substantially zero. 
     Referring to FIG. 6, there is shown a voltage setting circuit E&#34; which is another modification of the voltage setting circuit E. The voltage setting circuit E&#34; comprises an output transistor Q 14  having the base thereof connected to the base of the transistor Q 3 . The emitter of transistor Q 14  connected to a resistor R 11  and further to a positive side of the battery E 3 . The collector of the transistor Q 14  is connected to resistor R 12  which is connected, in parallel with the potentiometers PM 1  and PM 2  through a pair of terminals P 10  and P 11 . It is to be noted that the transistor Q 14  and the resistors R 11  and R 12  in the voltage setting circuit E&#34; are formed in the integrated circuit together with the constant current generator D. The voltage setting circuit E&#34; in this modification shows that the output transistor employed therein is not necessarily biased by the base of the transistors Q 1  or Q 2 , but it is possible to have the output transistor biased by the base of the transistors Q 3  and Q 4 . 
     Referring to FIG. 7, there is shown a voltage setting circuit E&#34;&#39; which is yet another modification of the voltage setting circuit E shown in FIG. 3. The voltage setting circuit E&#34;&#39; comprises the transistor Q 5  having the base thereof connected to the base of the transistor Q 1 , and a pair of transistors Q 15  and Q 16  having the bases thereof connected to each other. The transistor Q 15  has its collector connected to the collector of the transistor Q 5  and the emitter thereof connected to the emitter of the transistor Q 16  and further to the positive side of the battery E 3 . The transistor Q 16 , namely the output transistor, has its base and collector connected to each other. A resistor R 12  is connected to the collector of the transistor Q 16  and also connected in parallel with the potentiometers PM 1  and PM 2 . Note that the transistors Q 5 , Q 15  and Q 16  and the resistor R 12  in the voltage setting circuit E&#34;&#39; are formed in the integrated circuit together with the constant current generator D. 
     According to the voltage setting circuit E&#34;&#39; of FIG. 7, the base-emitter voltage V BE5  of the transistor Q 5  is determined by the base-emitter voltage V BE2  of the transistor Q 2 . The current I 5  relating to the base-emitter voltage V BE5  is thus determined, and in turn, the base-emitter voltage V BE15  of the transistor Q 15  is determined by the current I 5 . Similarly, the base-emitter voltage V BE16  of the transistor Q 16  is determined by the base-emitter voltage V BE15 , so that the current I 16  relating to the base-emitter voltage V BE16  is thus determined. Therefore, a predetermined voltage is produced across the resistor R 12 . The voltage setting circuit E&#34;&#39; in this modification shows that the output transistor in the voltage setting circuit can be indirectly biased by the output of the constant current generator D. 
     Referring to FIG. 8, there is shown a constant current generator D&#34; which is another modification of the constant current generator D shown in FIG. 3. The constant current generator D&#34; has a resistor R 13  connected between the collectors of the transistors Q 2  and Q 4 . The opposite ends of the resistor R 13  are provided with terminals P 12  and P 13 , respectively, for connecting a potentiometer PM 7  therebetween. Note that the resistor R 13  is formed in the integrated circuit together with the other electric elements in the current generator D&#34; such as transistors Q 1 , Q 2 , Q 3  and Q 4  and resistors R 1 , R 2  and R 3 , however, the potentiometer PM 7  is provided externally to the integrated circuit. Wiper W 7  of the potentiometer PM 7  is connected to the output terminal Te which is further connected to a circuit such as shown in FIG. 4. The wiper W 7  is mechanically coupled to a shutter speed setting dial provided in the camera so as to permit manual setting of the exposure time. In this circuit, the output signal produced from the wiper W 7  is equal to V BE2  +Vt&#39;, in which Vt&#39; is a voltage drop between the wiper W 7  and the terminal P 13 . Since the characteristics in the integrated circuit comprising transistors Q 1  to Q 4 , and resistors R 1  to R 3  and R 13 , can be controlled to generate a constant current across the resistor R 13 , the required output voltage signal indicative of the exposure time can be accurately achieved regardless of departure of the electrical characteristics of potentiometer PM 7  from the design values. 
     Referring to FIG. 9, there is shown a resistor R 13  &#39; which is a modification of the resistor R 13  of FIG. 8. The resistor R 13  &#39; in this modification is divided into a plurality of sections, ten sections in this instance, and is provided with taps 1a to 9a between the neighboring sections. These taps are selectively connected with the output terminal Te for producing the output voltage signal indicative of the exposure time. With the circuit shown in FIG. 9, it is necessary to provide the external potentiometer PM 7  as described above. 
     According to the exposure information setting circuit of the present invention, there is no need to provide any variable adjusting resistors to adjust the voltage to be provided across the potentiometers as indicated by the reference characters PM 1  and PM 2 , so that the cost of production of the exposure information setting circuit of the present invention is low compared with the conventional circuit, yet maintains the required accuracy. 
     Note that the integrated circuit provided in the information setting circuit of the present invention is not limited to that shown in FIG. 3 or in FIGS. 5 to 9, but, for example, may be the constant current generator constituted by the transistors Q 11  and Q 12  and resistors R 10  and R 11 , as shown in FIG. 2, in which the resistor R 11  is fixed. In this case, a resistor corresponding to the resistor R 6  of FIG. 3 is connected to the collector of the transistor Q 12 . Since required ratios of the transistor areas and resistance of the resistors can be precisely achieved, an accurate output can be achieved by the reasons given above in reference to the circuit of FIG. 3. In a circuit thus employing the transistors Q 11  and Q 12  and resistors R 10  and R 11 , however, it is necessary to provide an additional circuit for maintaining the power supply voltage at a constant value, since according to the equations given above, the factors of the power supply remain in the equations. 
     Although the present invention has been fully described by way of examples with reference to the attached drawings, that various changes and modifications are apparent to those skilled in the art. Therefore, unless such changes and modifications depart from the scope of the present invention, they should be construed as included therein.