Abstract:
A photoelectric conversion apparatus includes a plurality of buffer devices which each receive a sensor signal via a first switching device and receive a predetermined voltage via a second switching device. A plurality of output lines are respectively connected to corresponding buffer devices, and a plurality of charge storage devices are respectively connected to corresponding output lines. Resetting devices are connected to input and output sides of each charge storage device.

Description:
This application is a division of application Ser. No. 07/868,773 filed Apr. 15, 1992, now abandoned, which is a divisional of Ser. No. 07/508,893, now U.S. Pat. No. 5,162,912. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a photoelectric conversion apparatus and, more particularly, to a photoelectric conversion apparatus for removing noise included in a signal photoelectrically converted by a photoelectric conversion element. 
     2. Related Background Art 
     In a conventional photoelectric conversion apparatus, when a signal photoelectrically converted by a photoelectric conversion element is to be read out, an unnecessary component such as a dark signal or a drive noise from the photoelectric conversion element is often included in and output together with the readout signal. The dark signal is a dark current of a photosensor, and the drive noise is noise generated when the photosensor is driven to read out a signal. 
     In order to remove these noise components from a photoelectric conversion element, the assignee of the present invention proposed a photoelectric conversion apparatus having the following arrangement in Japanese Patent Application No. 62-279390. 
     FIG. 1 is a partial circuit diagram showing an arrangement of the above photoelectric conversion apparatus. 
     Referring to FIG. 1, noise from a photoelectric conversion element is stored in a capacitor C 1  via a MOS transistor Qh 1 , and a signal from the photoelectric conversion element is stored in a capacitor C 2  via a MOS transistor Qh 2 . 
     The stored noise and signal are sequentially transferred, via a buffer amplifier Qh 5  and a MOS transistor Qh 9 , to an output signal line AL by MOS transistors Qh 3  and Qh 4  controlled by pulses φ A  and φ B , respectively. Thereafter, the noise is removed from the signal. Since a signal and noise are passed through the same amplifier Qh 5  to remove the noise such as fixed pattern noise from the signal, noise from the photoelectric conversion element and offset noise generated by the amplifier can be simultaneously removed. 
     The assignee of the present invention also proposed a photoelectric conversion apparatus having the following arrangement in Japanese Patent Application No. 63-72112. 
     FIG. 2 is a partial circuit diagram showing an arrangement of the above photoelectric conversion apparatus. 
     First, as shown in FIG. 2, MOS transistors Qh and Qhr are turned on, one terminal of a capacitor C 1  is grounded, and a MOS transistor Q VC  is turned off, thereby floating the emitter of a photoelectric conversion element S. As a result, noise from the photoelectric conversion element is stored in the capacitor C 1  and a capacitor C V . Assume that a potential obtained in this state is Vn. A signal is stored in the base of the photoelectric conversion element S, and a pulse φ VC  during a storage period is raised to clear the capacitor C V . At this time, the potential changes from Vn to GND. If the transistors Qh and Qhr are kept OFF, the potential at the output side of the capacitor C 1  is -Vn. 
     The signal from the photoelectric conversion element S is transferred to and stored in the capacitor C V . At this time, the potential rises from GND by Vs. Meanwhile, the potential at the output side of the capacitor C 1  rises from -Vn by Vs. 
     By turning on the transistor Qh, a signal from which noise components are removed can be output. 
     Of the above two photoelectric conversion apparatuses, however, the former photoelectric conversion apparatus must comprise a high-precision and high-speed clamp circuit and a sample-and-hold circuit as external circuits in order to remove noise from the photoelectric conversion element and offset noise from a point sequential signal. In addition, it is difficult to apply an IC arrangement to the entire apparatus. Furthermore, in order to incorporate these circuits in a single chip, positive and negative pulses must be used for the clamp or the sample-and-hold circuit. 
     In the latter photoelectric conversion apparatus, when an output signal is passed through the buffer amplifier, offset noise generated by the amplifier is superposed on the signal. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a noise correction circuit, a photoelectric conversion apparatus, and a subtractor suitable for an IC arrangement, which can remove both noise from a photoelectric conversion element and offset noise from a buffer amplifier. 
     A photoelectric conversion apparatus according to an embodiment of the present invention, comprises: a photoelectric conversion element; first storage means for storing a signal from the photoelectric conversion element; second storage means for storing noise from the photoelectric conversion element; buffer means for buffering output signals from the first and second storage means; capacitor means connected to the buffer means; and resetting means connected to both sides of the capacitor means. 
     According to the above embodiment, the output side of the capacitor means is reset to be a predetermined potential (in this case, GND) by the resetting means provided at the output side of the capacitor means, and noise from the photoelectric conversion element is transferred from the second storage means to the capacitor means via the buffer means (in this case, a potential is Vn). 
     After the output side of the capacitor means is floated, the input side of the capacitor is reset to be a predetermined potential (in this case, GND) by the resetting means provided at the input side of the capacitor means. At this time, the potential at the input side of the capacitor means changes from Vn to GND, and that at the output side of the capacitor means changes from GND to -Vn. 
     A signal from the photoelectric conversion element is transferred from the first storage means to the capacitor means via the buffer means (in this case, a potential is Vs). At this time, the potential at the input side of the capacitor means changes from GND to Vs, and that at the output side of the capacitor means rises by Vs from -Vn to Vs-Vn. 
     In this manner, noise from the photoelectric conversion element can be removed. At the same time, noise from the buffer means can be removed since a subtraction is performed after both the noise components from the signal and the photoelectric conversion element are passed through the same buffer means. 
     A noise correction circuit according to an embodiment of the present invention, comprises: buffer means for receiving a signal via first switching means and receiving a predetermined voltage via second switching means; charge storage means connected to an output side of the buffer means; and resetting means connected to input and output sides of the charge storage means. 
     A photoelectric conversion apparatus according to an embodiment of the present invention, comprises: a plurality of buffer means each for receiving a sensor signal via first switching means and receiving a predetermined voltage via second switching means; a plurality of output lines each connected to a corresponding one of the buffer means; a plurality of charge storage means each connected to a corresponding one of the output lines; and resetting means connected to input and output sides of each of the charge storage means. 
     The noise correction circuit according to the embodiment having the above arrangement removes noise of the buffer means by the following operation. 
     The output side of the charge storage means connected in series with the buffer means is set at a predetermined potential (V GN ) by the resetting means, and the second switching means is turned on to store an electrical charge via the buffer means, thereby setting a potential at the input side of the charge storage means to be a potential (V B  +V N ) obtained by adding a noise component (V N ) of the buffer means to a predetermined potential (V B ). Note that the input side of the charge storage means may be set at a predetermined potential (V I ) beforehand to obtain a potential of V B  +V N  +V I . In this embodiment, however, V I  is set as V I  =0. 
     The output side of the charge storage means is then opened and floated, and the first switching means is turned on to apply a signal voltage (V S  +V N ) obtained by adding the noise component (V N ) of the buffer means to a signal voltage V S  to the input side of the charge storage means. At this time, a potential variation at the input side of the charge storage means is represented by (V S  +V N )-(V B  +V N )=V S  -V B  (note that V S  -V B  &gt;0). Meanwhile, the potential at the output side of the charge storage means rises by V S  -V B  to be V GN  +V S  -V B  in accordance with the variation at the input side. In this manner, the noise component V N  generated by the buffer means is removed. 
     The photoelectric conversion apparatus of the present invention obtains a sensor signal from which noise generated by the buffer means is removed by using the above noise correction circuit. 
     A subtractor according to an embodiment of the present invention, comprises: first switching means connected to a first signal source; second switching means connected to a second signal source; and capacitor means commonly connected to output sides of the first and second switching means, wherein a signal of one of the first and second signal sources is output to the capacitor means, and then a signal from the other signal source is output to the capacitor means, thereby extracting a difference signal of the signals from the first and second signal sources from an output side of the capacitor means. 
     In the subtractor having the above arrangement, the first switching means connected to the first signal source is used to output a signal from the first signal source to the capacitor means (in this case, a potential of the capacitor means is V1), and a reference potential at the output side of the capacitor means is set to be, e.g., GND. 
     Thereafter, the second switching means connected to the second signal source is used to output a signal from the second signal source to the capacitor means (in this case, the potential of the capacitor means is V2). As a result, a potential variation at the input side of the capacitor means becomes V2-V1. Meanwhile, the potential at the output side of the capacitor means varies from the reference potential to V2-V1. That is, a difference signal representing a difference between the signals from the first and second signal sources can be output from the output side of the capacitor means. 
     The other objects and features of the present invention will become apparent from the following description in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a partial circuit diagram showing an arrangement of a photoelectric conversion apparatus disclosed in Japanese Patent Application No. 62-279390; 
     FIG. 2 is a partial circuit diagram showing an arrangement of a photoelectric conversion apparatus disclosed in Japanese Patent Application No. 63-72112; 
     FIG. 3 is a schematic circuit diagram showing an arrangement of a photoelectric conversion apparatus of the present invention; 
     FIG. 4 is a timing chart for explaining an operation of the photoelectric conversion apparatus shown in FIG. 3; 
     FIG. 5 is a partial circuit diagram showing a photoelectric conversion apparatus of the present invention including a removing circuit for a pulse leakage component; 
     FIG. 6 is a schematic block diagram showing an arrangement of an image reader; 
     FIG. 7 is a circuit diagram showing an embodiment of a noise correction circuit used in the photoelectric conversion apparatus of the present invention; 
     FIG. 8 is a timing chart for explaining an operation of the noise correction circuit shown in FIG. 7; 
     FIG. 9 is a circuit diagram for explaining a basic arrangement of a subtractor of the present invention; 
     FIG. 10 is a timing chart for explaining an operation of the subtractor shown in FIG. 9; 
     FIG. 11 is a circuit diagram of a photoelectric conversion apparatus showing an embodiment of the subtractor of the present invention; 
     FIG. 12 is a timing chart for explaining the embodiment of the subtractor shown in FIG. 11; 
     FIG. 13 is a circuit diagram of a photoelectric conversion apparatus showing another embodiment of the subtractor of the present invention; and 
     FIG. 14 is a timing chart for explaining the embodiment of the subtractor shown in FIG. 13. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of a photoelectric conversion apparatus according to the present invention will be described in detail below with reference to the accompanying drawings. 
     FIG. 3 is a schematic circuit diagram showing an embodiment of a photoelectric conversion apparatus according to the present invention. 
     As shown in FIG. 3, a photoelectric conversion element S is connected to a capacitor C N  via a transistor T 1  and is connected to a capacitor C S  via a MOS transistor T 2 . The capacitors C N  and C S  are connected to a buffer amplifier Tr 2  and a MOS transistor T BC  controlled by a pulse φ BC  via MOS transistors T H1  and T H2  controlled by a shift register. The shift register is controlled by pulses φ HS , φ H1 , and φ H2 . 
     An output from the buffer amplifier Tr 2  is transferred to an output signal line SL. Note that the output signal line SL has a parasitic capacitance C H . A portion A at the output signal line SL side is reset by a MOS transistor T HBC  controlled by a pulse φ BC . 
     The output signal line SL is connected to a MOS transistor T SH  controlled by a pulse φ H2  and a MOS transistor T HC1  controlled by a pulse φ HC1  via a coupling capacitor C C . The MOS transistor T HC1  resets a portion B at the output side of the coupling capacitor C C . The MOS transistor T SH  is further connected to a capacitor C S  and a MOS transistor T HC2 . The MOS transistor T HC2  resets a portion C at the output side of the MOS transistor T SH . 
     An operation of the photoelectric conversion apparatus having the above operation will be described below with reference to FIG. 4. 
     FIG. 4 is a timing chart for explaining the operation of the above photoelectric conversion apparatus. 
     Noise from the photoelectric conversion element S is stored in the capacitor C N  via the MOS transistor T 1  under the control of a pulse φ T1 . A signal from the photoelectric conversion element S is stored in the capacitor C S  via the MOS transistor T 2  under the control of a pulse φ T2 . 
     When the pulse φ H1  goes to high level, the MOS transistor T H1  is turned on, and the noise stored in the capacitor C N  is stored in the coupling capacitor C C  via the MOS transistor T H1  and the buffer amplifier Tr 2 . Since the pulse φ HC1  is at high level and the MOS transistor T HC1  is kept ON, a potential of the portion B at the output side of the coupling capacitor C C  is kept at GND. Therefore, while a potential V 2  of the portion B is at GND, a noise voltage of +Vn 1  is stored as a potential V 1  of the portion A of the output signal line SL. 
     The pulse φ HC1  is switched to low level, and the MOS transistor T HC1  is turned off, thereby floating the portion B. In addition, the pulse φ BC  is switched to high level, and the MOS transistor T HBC  is turned on, thereby decreasing the potential of the portion A from the noise voltage of +Vn 1  to GND. At this time, a noise voltage of -Vn 1  having a polarity opposite to that of the noise voltage of +Vn 1  appears as the potential V 2  of the portion B. 
     The pulse φ BC  is switched to low level, and the MOS transistor T HBC  is turned off. Thereafter, by switching the pulse φ H2  to high level, the MOS transistor T H2  is turned on, and the signal stored in the capacitor C S  is transferred to the coupling capacitor C C  via the MOS transistor T H2  and the buffer amplifier Tr 2 . 
     At this time, the potential of the portion A rises from GND to a signal voltage of Vs 1 . In accordance with the potential rise in the portion A, the potential of the portion B rises by the potential Vs 1  from a noise voltage of -Vn 1  to a potential of Vs 1  -Vn 1 , i.e., a potential including only signal components obtained by canceling noise voltage components. That is, the sensor noise and the buffer amplifier noise are cancelled. 
     Since the sample-and-hold MOS transistor T SH  is turned on when the voltage Vs 1  -Vn 1  appears in the portion B, a voltage V 3  appears in the portion C. By sampling and holding, a signal having a high duty ratio and free from noise components can be obtained. 
     FIG. 5 is a partial circuit diagram showing a photoelectric conversion apparatus according to the present invention including a pulse leakage component removing circuit. 
     Referring to FIG. 5, when a MOS transistor or the like is pulse-driven, a pulse leakage component is generated due to capacitance division of a pulse caused by the gate capacitance or an overlap capacitance between the source (drain) and the gate of the MOS transistor and a signal line capacitance. The pulse leakage component is also generated by a parasitic capacitance between pulse wiring and a signal line. As shown in FIG. 5, such a leakage component can be removed by arranging a circuit having the same arrangement as that of a signal reading circuit in parallel with the signal reading circuit to perform differential processing. 
     A practical arrangement of an image reader to which the present invention is applied will be described below. 
     FIG. 6 is a schematic block diagram showing the arrangement of the image reader. 
     Referring to FIG. 6, an original 501 is mechanically moved relative to a reading unit 505 in a direction indicated by an arrow Y. Image reading is performed by scanning in a direction indicated by an arrow X by an image sensor 504 as a photoelectric conversion apparatus of the present invention. 
     Light from a light source 502 is reflected by the original 501, and the reflected light forms an image on the image sensor 504 through an imaging optical system 503. The image sensor 504 stores carriers corresponding to the intensity of the incident light and outputs the carriers as a photoelectrically converted image signal. 
     This image signal is digital-converted by an A/D converter 506 and fetched as image data in an internal memory of an image processing unit 507. The fetched data is subjected to, e.g., shading correction and color correction and transmitted to a personal computer 508, a printer, or the like. 
     When image signal transfer of X-direction scanning is finished in this manner, the original 501 is moved relatively in the Y direction, and the above operation is repeatedly performed, thereby converting the total image of the original 501 into an electrical signal and extracting the signal as image information. 
     In the above embodiment, the present invention is applied to an image reader using a line sensor. The present invention, however, can be applied to not only a line sensor but also, e.g., an area sensor. 
     As has been described above in detail, according to the photoelectric conversion apparatus, noise included in a signal from a photoelectric conversion element and offset noise generated by a buffer amplifier in a read system can be removed in a single chip. 
     In addition, by noise removal of a coupling capacitance system provided at the output side of the buffer amplifier, a bipolar transistor portion is included between the photoelectric conversion element and the buffer amplifier. Therefore, even if a bias voltage is applied, the bias voltage can be cancelled. 
     Furthermore, since a sample-and-hold circuit is included, only a sensor signal having a high S/N ratio can be output. 
     An embodiment of a noise correction circuit according to the present invention will be described in detail below with reference to the accompanying drawings. 
     Although an application of the noise correction circuit of the present invention is not limited to a photoelectric conversion apparatus, a photoelectric conversion apparatus will be exemplified as a suitable application. 
     FIG. 7 is a circuit diagram showing an arrangement of the noise correction circuit used in the photoelectric conversion apparatus of the present invention. 
     FIG. 7 shows an arrangement of a circuit for reading out a sensor signal from a photoelectric conversion unit having m pixels via a buffer amplifier as a buffer means. 
     Referring to FIG. 7, output lines L 1 , L 2 , and L 3  are connected to buffer amplifiers B 11  to B 1n , B 21  to B 2n , and B 31  to B 3n , respectively, each corresponding to m/3 pixels. Transistors M 11  to M 1n  (n=m/3) are connected to the input sides of the buffer amplifiers B 11  to B 1n  which are connected to the output line L 1 , respectively. Transistors M 21  to M 2n  (n=m/3) are connected to the input sides of the buffer amplifiers B 21  to B 2n  which are connected to the output line L 2 , respectively. Transistors M 31  to M 3n  (n=m/3) are connected to the input sides of the buffer amplifiers B 31  to B 3n  which are connected to the output line L 3 , respectively. 
     The transistors M 11  to M 1n , M 21  to M 2n , and M 31  to M 3n  are ON/OFF-controlled by pulses φ 11  to φ 1n , φ 21  to φ 2n , and φ 31  and φ 3n , respectively. 
     Sensor signals V s1  to V sm  of the respective signals are selected by the pulses φ 11  to φ 1n , φ 21  to φ 2n , and φ 31  to φ 3n  and output to the output lines L 1  to L 3  via the transistors M 11  to M 1n , M 21  to M 2n , and M 31  to M 3n  and the buffer amplifiers B 11  to B 1n , B 21  to B 2n , and B 31  to B 3n  which are connected to these transistors. 
     Transistors N 11  to N 1n  are connected to the input sides of the buffer amplifiers B 11  to B 1n , respectively, transistors N 21  to N 2n  are connected to the input sides of the buffer amplifiers B 21  to B 2n , respectively, and transistors N 31  to N 3n  are connected to the input sides of the buffer amplifiers B 31  to B 3n , respectively. The transistors N 11  to N 1n , N 21  to N 2n , and N 31  to N 3n  are ON/OFF-controlled by pulses φ 30  to φ 3n-1 , φ 11  to φ 1n , and φ 21  to φ 2n , respectively. A reference voltage V B  can be applied to the input sides of the buffer amplifiers B 21  to B 2n  via the transistors N 11  to N 1n , N 21  to N 2n , and N 31  to N 3n , respectively. 
     Capacitors C N1 , C N2 , and C N3  are connected in series with the output stages of the output lines L 1 , L 2 , and L 3 , respectively, and the input sides of the capacitors C N1 , C N2 , and C N3  are connected to reset power sources via transistors, M R1 , M R2 , and M R3 , respectively, so that a reset voltage V GN  can be applied thereto. The transistors M R1 , M R2 , and M R3  are ON/OFF-controlled by output read pulses φ 2 , φ 3 , and φ 1 , respectively. 
     The output sides of the capacitors C N1 , C N2 , and C N3  are connected to a sample-and-hold circuit (S/H circuit) via transistors M T1 , M T2 , and M T3 , respectively. The transistors M T1 , M T2 , and M T3  are controlled by the output read pulses φ 1 , φ 2 , and φ 3 , respectively, and the signal charges stored in the capacitors C N1 , C N2 , and C N3  are read out to the S/H circuit under the control of the output read pulses φ 1 , φ 2 , and φ 3 , respectively. 
     The output sides of the capacitors C N1 , C N2 , and C N3  are connected to reset power sources via transistors M C1 , M C2 , and M C3 , respectively, so that the reset voltage V GN  can be applied thereto. The transistors M C1 , M C2 , and M C3  are ON/OFF-controlled by the output read pulses φ 3 , φ 1 , and φ 2 , respectively. 
     The output sides of the transistors M T1 , M T2 , and M T3  are connected to reset power sources via transistors M F1 , M F2 , and M F3 , respectively, so that the reset voltage V GN  can be applied thereto. The transistors M F1 , M F2 , and M F3  are ON/OFF-controlled by the output read pulses φ 2 , φ 3 , and φ 1 , respectively. 
     An operation of the noise correction circuit having the above arrangement will be described below. 
     FIG. 8 is a timing chart for explaining an operation of the noise correction circuit. 
     As has been described above with reference to FIG. 7, the pulses φ 1 , φ 2 , and φ 3  ON/OFF-control the transistors M T1 , M T2 , and M T3  to select the output lines L 1 , L 2 , and L 3 , respectively, and ON/OFF-control the transistors M R1  to M R3 , M C1  to M C3 , and M F1  to M F3  to reset the output lines L 1 , L 2 , and L 3 , respectively. Pulses φ 11 , φ 21 , φ 31 , and φ 30  are the pulses output from a scanning circuit in synchronism with the pulses φ 1 , φ 2 , and φ 3 , and only one of them is output during one sensor operation cycle. 
     With reference to a timing chart shown in FIG. 8, a noise correction read operation of an input signal V S1  to the output line L 1  will be described below. First, the transistor N 11  is turned on by the pulse φ 30  to input a predetermined voltage V B  to the buffer amplifier B 11 . A the same time, the transistor M C1  is turned on by the pulse φ 3  to set the output side of the capacitor C N1  at a fixed voltage V GN . Assuming that a signal including a noise component output via the buffer amplifier B 11  is V B  +V N , the capacitor C N1  holds a potential of V B  +V N . When the transistor M 11  is turned on by the pulse φ 11  to input the sensor signal V S1  to the buffer amplifier B 11 , a noise component at the same level as that obtained when the predetermined voltage V B  is input via the buffer amplifier B 11  is generated as V S1  +V N . At the same time this signal V S1  +V N  is output from the buffer amplifier B 11 , the transistor M C1  is turned off by the pulse φ 3  to float the capacitor C N1 . At this time, a signal change in the capacitor C N1  is as follows. That is, at the beginning, a potential V B  +V N  is held at the input side of the capacitor C N1 , while the potential V GN  is held at its output side. When the signal of V S1  +V N  is applied, a potential change at the input side of the capacitor C N1  is V S1  -V B , while the potential at its output side changes by V S1  -V B  to be V S1  -V B  +V GN , thereby removing the noise component V N  generated by the buffer amplifier B 11 . Since the transistor M T1  is kept ON by the pulse φ 1 , the signal having the potential V S1  -V B  +V GN  is input to the S/H circuit. Thereafter, the transistors M R1  and M F1  are turned on by the pulse φ 2 , and the potentials of the respective wiring portions are reset to prepare for the next signal reading. 
     The above series of operations are similarly performed for the output lines L 2  and L 3 . As is apparent from the timing chart in FIG. 8, the output signals are supplied to the S/H circuit in the order of the pulses φ 1 , φ 2 , and φ 3  and extracted as continuous signals. In this embodiment, an output line is divided into three or more lines, and scanning pulses and output read pulses of the respective lines are efficiently combined. Therefore, a noise correction operation can be performed by using the same number of pulses as that used in a circuit not having a noise correction circuit, and the signal processing can be efficiently performed within a short time period. 
     Note that in the above embodiment, the potential V B  is preferably set to be a value at which the same noise as that generated when the signal is input to a buffer amplifier is generated by the buffer amplifier. In the above embodiment, however, the potential V B  may be a potential at the same level as a dark signal level of the sensor. 
     As has been described above in detail, according to the noise correction circuit of the present invention, noise generated by the buffer means can be removed by a simple circuit arrangement. 
     A photoelectric conversion apparatus using the present invention can prevent gain reduction in an output unit and improve a read time efficiency by using the above noise correction circuit. 
     An embodiment of a subtractor according to the present invention will be described in detail below with reference to the accompanying drawings. 
     FIG. 9 is a circuit diagram for explaining a basic arrangement of the subtractor of the present invention. 
     Referring to FIG. 9, this subtractor comprises a connection terminal S 1  connectable to a first signal source, a MOS transistor M 1  for ON/OFF-controlling a signal from the first signal source by using a clock φ A , a connection terminal S 2  connectable to a second signal source, and a MOS transistor M 2  for ON/OFF-controlling a signal from the second signal source by using a clock φ B . 
     The MOS transistors M 1  and M 2  are commonly connected at a node P 1 , and then to a capacitor C. The capacitor C is connected to an output amplifier A 1 . A terminal of the capacitor C at the node P side is connected to a MOS transistor M 4  which is ON/OFF-controlled by a clock φ C  so that a charge stored in the wiring and the capacitor can be reset. A terminal of the capacitor C at the output amplifier A side is connected at a node P 2  to a MOS transistor M 3  which is ON/OFF-controlled by the clock φ A  so that a reference potential (V R ) can be applied thereto. 
     An operation of the subtractor having the above arrangement will be described below. 
     FIG. 10 is a timing chart for explaining the operation of the above circuit. 
     Referring to FIG. 10, when the pulse φ A  rises at a timing t0 turn on the MOS transistors M 1  and M 3 , the signal voltage V 1  from the first signal source is read out to the node P 1  and at the same time the node P 2  is reset to the reference potential (V R ), 
     When the clock φ A  falls at a timing t1 to turn off the MOS transistors M 1  and M 3 , the node P 2  is set in a high-impedance state. 
     When the clock φ B  rises at a timing t2 to turn on the MOS transistor M 2 , the signal voltage V 2  (in this case, V 2  &gt;V 1 ) from the second signal source is read out to the node P 1 . 
     At this time, the potential at the node P 1  rises from V 1  to V 2 , and the potential at the node P 2  rises from the reference potential V R  by (V 2  -V 1 ) due to the capacitor C provided between the contacts P 1  and P 2 . Therefore, the amplifier A 1  outputs a signal corresponding to the difference signal (V 2  -V 1 ) 
     When the clock φ B  falls at a timing t3 to turn off the MOS transistor V 2  and the clock φ C  rises at a timing t4 to turn on the MOS transistor M 4 , charges stored in the wiring and the capacitor at the node P 1  side are reset to prepare for the next signal reading. 
     As an embodiment of the subtractor of the present invention, an embodiment in which the present invention is applied to a photoelectric conversion apparatus will be described below. 
     FIG. 11 is a circuit diagram showing an arrangement of a photoelectric conversion apparatus using the subtractor of the present invention. 
     As shown in FIG. 11, MOS transistors M 11  to M 1n  are connected to the bases of sensor transistors Q 1  to Q n , respectively, and a voltage V BB  is applied thereto under ON/OFF control of a pulse φ BR . The emitters of the sensor transistors Q 1  to Q n  are connected to MOS transistors M 21  to M 2n , respectively, and are further connected to capacitors C P1  to C Pn  and capacitors C D1  to C Dn  via MOS transistors M 31  to M 3n  and MOS transistors M 41  to M 4n , respectively. 
     The MOS transistors M21 to M2n are ON/OFF-controlled by a pulse φ VRS  so that a voltage V VR , can be applied to the emitters of the sensor transistors Q 1  to Q n  respectively. The MOS transistors M 31  to M 3n  are ON/OFF-controlled by a pulse φ TP , and the MOS transistors M 41  to M 4n  are ON/OFF, controlled by a pulse φ TD . The capacitors C P1  to C Pn  and the capacitors C D1  to C Dn  are connected to MOS transistors M 51  to M 5n  and MOS transistors M 61  to M 6n  via buffers B 11  to B 1n  and buffers B 21  to B 2n , respectively. The gates of the MOS transistors M 51  and M 61 , M 52  and M 62 , . . . , M 5n  and M 6n  are commonly connected and sequentially scanned by a shift register. By sequentially controlling the shift register, the signals stored in the capacitors C P1  and C D1 , C P2  and C D2 , . . . , C Pn  and C Dn  are transferred onto horizontal transfer lines l 1  and l 2 . 
     The horizontal transfer lines l 1  and l 2  are connected to a subtractor unit X. Note that the subtractor unit X is equivalent to the subtractor described above except that the reference potential V R  is GND in the unit X. In the subtractor unit X, the same reference symbols as in the above subtractor denote the same parts and a detailed description thereof will be omitted. 
     FIG. 12 is a timing chart for explaining an operation of the above circuit. 
     At a timing t1, a clock φ TP  rises to turn on the MOS transistors M 31  to M 3n , and storage end timing signals (including fixed pattern noise) are simultaneously transferred to the temporary storage capacitors CP1 to CPn for all the pixels. 
     When the clock φ TP  falls to turn off the MOS transistors M 31  to M 3n  at a timing t2 and a clock φ BR  falls to turn on the transistors M 11  to M 1n  at a timing t3, the base potentials of the sensor transistors Q 1  to Q n  are reset to be V BB  for all the pixels (this is called a perfect reset operation). 
     When the clock φ BR  rises to turn off the transistors M 11  to M 1n  at a timing t4 and a clock φ VRS  rises to turn on the transistors M 21  to M 2n  at a timing t5, the emitter potentials of the sensor transistors Q 1  to Q n  are reset to be V VR  (this is called a transition reset operation). 
     From a timing t6 to a timing t7 during this transition reset operation, a clock φ TD  rises to turn on the transistors M 41  to M 4n , and the potential at the end of the transition reset operation, i.e., the potential at the start of the storage operation is transferred to the capacitors C D1  to C Dn . 
     Storage of new signals into the sensor transistors Q 1  to Q n  is started at the timing t7, and the storage end timing signals (including the fixed pattern noise) transferred to the capacitors C P1  to C Pn  and C D1  to C Dn  and storage operation start timing outputs are sequentially output via the buffers B 11  and B 1n , the MOS transistors M 51  to M 5n , the horizontal transfer line l 2 , the buffers B 21  to B 2n , the MOS transistors M61 to M6n, and the horizontal transfer line l 1 , respectively. 
     An output operation of the storage end timing signal (including the fixed pattern noise) and the storage start timing output is performed as follows. That is, the shift register applies a clock φ 1  to the MOS transistors M 51  and M 61 , and carriers of the capacitors C P1  and C D1  are read out onto the horizontal transfer lines l 2  and l 1  via the buffers B 11  and B 21 , respectively. By using the subtractor of the present invention described above, a differential signal obtained by subtracting a dark output from an optical signal is extracted. 
     Since the clock φ A  is at high level during the first half of the readout operation, i.e., between timings t8 to t9, the MOS transistors M 1  and M 3  are in an ON state. Therefore, the potentials at the nodes P 1  and P 2  are GND which is an output level upon storage start. 
     Since the clock φ B  is at high level during the second half of the readout operation, i.e., between timings t9 to t10, the MOS transistor M 2  is in an ON state, and the potential at the node P 1  changes from V N  to V S+N  (storage end timing signal level). At this time, since the node P 2  is in a floating state, the potential at the node P 2  rises from the GND level by the potential rise (V S  ), and this level is finally output. Thereafter, at a timing t10, the clock φ 1  from the shift register goes to low level and the clock φ C  rises. In the first half (timings t10 to t11) of the clock φ C , the clock φ A  goes to high level to turn on the transistors M 1  and M 3 , and the nodes P 1  and P 2  and the horizontal transfer line l 1  are reset. In the second half (timings tll to t12) of the clock φ C , the clock φ B  goes to high level to turn on the transistor M 2 , and the horizontal transfer line l 2  is reset. 
     The above series of read operations are sequentially performed to output an optical signal for each pixel. In this case, even if the storage start timing output level varies for each pixel, only the storage end timing signal level not including the fixed pattern noise is output to the output terminal. Therefore, optical information having a high S/N ratio can be obtained. 
     FIG. 13 is a circuit diagram showing an arrangement of another photoelectric conversion apparatus using the subtractor of the present invention. 
     FIG. 14 is a timing chart for explaining the basic arrangement of the subtractor. 
     As shown in FIG. 13, this embodiment is a photoelectric conversion apparatus of a 4-line read system in which outputs from pixels are divided into upper and lower stages, each of which is further divided into upper and lower stages. 
     A sensor unit and a subtractor unit of each line of four horizontal transfer lines are equivalent to those of the first embodiment, and detailed arrangements and operations thereof will be omitted. 
     As shown in FIGS. 13 and 14, clocks φ C1 , φ C2 , φ C3 , and φ C4  are sequentially scanned to output a storage start timing output and a storage end timing signal to horizontal transfer lines l la  and l 2a , l 1b  and l 2b , and l 2c , and l 1d  and l 2d , respectively. 
     Subtractor units X a  to X d  correspond to the subtractor unit X in the above embodiment shown in FIG. 11 except that no amplifier is included in these units. MOS transistors M 1a  to M 4a , M 1b  to M 4b , M 1c  to M 4c , and M 1d  to M 4d  correspond to the transistors M 1  to M 4 , respectively, and capacitors C 1  to C 4  correspond to the capacitor C. Outputs from nodes Q 1  to Q 4  of the subtractor units X a  to X d  are connected to MOS transistors M 5a  to M 5d  which are ON/OFF-controlled by the clocks φ C3 , φ C4 , φ C2 , and φ C1 , respectively. The MOS transistors M 5a  and M 5b  are commonly connected via an amplifier A 2  to a MOS transistor M 6  which is ON/OFF-controlled by a clock φ A0 . The MOS transistors M 5c  and M 5d  are commonly connected via an amplifier A 3  to a MOS transistor M 7  which is ON/OFF-controlled by a clock φ B0 . 
     The MOS transistors M 6  and M 7  are commonly connected to a capacitor C S  and an amplifier A 4 . 
     The nodes Q 1 , Q 2 , Q 3l  , and Q 4  shown in FIG. 13 have potentials Q 1 , Q 2 , Q 3 , and Q 4  shown in FIG. 14, respectively, and the amplifier A4 outputs V out . 
     In the embodiment shown in FIG. 11, an optical signal is output during a 1/4 period of the clock φ 1 . In this embodiment shown in FIG. 13, however, the horizontal signal line is divided into four parts, and the phases of the four parts are offset by 90° C. Therefore, an optical signal continuously appears at the output terminal. In addition, a sample-and-hold function is provided by the capacitor C S . 
     The above photoelectric conversion apparatus can be applied to the image reader as shown in FIG. 6. 
     As has been described in detail above, according to the subtractor of the present invention, a circuit can be easily integrated since a circuit member such as a differential amplifier which is difficult to be integrated need not be used. Therefore, a compact apparatus can be manufactured at low cost.