Abstract:
In a method of estimating a bit rate (f 1 ) of a digital signal conveyed through a SONET network between an originating node and a terminating node, the digital signal received by the originating node is processed to determine a result of a first function of the signal bit rate (f 1 ) and a respective Tx local reference frequency (f 2 ) of the originating node. A result of a second function of the Tx local reference frequency (f 2 ) and a respective Rx local reference frequency (f 3 ) of the terminating node is calculated. Finally, a result of a third function of the respective first and second function results is calculated, to derive an estimate of the signal bit rate (f 4 ) relative to the Rx local reference frequency (f 3 ).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This is the first application filed for the present invention.  
       MICROFICHE APPENDIX  
       [0002]     Not Applicable.  
       TECHNICAL FIELD  
       [0003]     This invention relates to communications networks, and in particular to a method for digitally processing SONET pointers.  
       BACKGROUND OF THE INVENTION  
       [0004]     Within the modern network space, the Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) protocol is becoming increasingly popular as a mechanism for data transport. In this respect, SDH is the European equivalent of the SONET transmission standard. Accordingly, all references in this application to SONET should be understood to also refer to SDH.  
         [0005]     A significant amount of SONET/SDH infrastructure has been installed, particularly within the network core. This SONET infrastructure is used to transport asynchronous subscriber signal traffic having differing formats, such as Asynchronous Transfer Mode (ATM), Internet Protocol (IP), etc. In order to facilitate this functionality, various known methods are provided for mapping the asynchronous subscriber traffic into Synchronous Transfer Signal (STS/STM) frames for transport across the SONET infrastructure, and then extracting the subscriber traffic out of the STS to recover the original subscriber signal format.  
         [0006]      FIG. 1   a  is a block diagram schematically illustrating principal operations of a conventional transmitting node  2  of an optical communications system. As shown in  FIG. 1   a,  asynchronous subscriber traffic within multiple tributaries  4  is received by the node  2  and buffered in an elastic store  6 . The traffic may comprise any arbitrary mix of signals, including DS-1, DS-3 and E1 traffic. Traffic within each tributary  4  is normally buffered in a respective First-In-First-Out (FIFO) buffer  8 . The timing of this buffering operation is controlled by a data clock signal  10  having a frequency f 1  generated by a tributary clock recovery circuit  12 . A synchronizing framer  14  reads data from each FIFO  8 , and maps the read data into corresponding tributaries of a number of SONET Synchronous Payload Envelopes (SPEs)  16 , using a known format such as those defined in the SONET standard. Each SPE  16  is then passed to a channel transmitter (Tx)  18 , which inserts the SPEs into an STS frame, and then modulates the STS frame onto an optical channel carrier  20  for transmission through the optical network. A Tx local clock  22 , which is synchronous with a SONET Primary Reference  24 , generates a respective TX local clock signal  26  having a frequency f 2 , which is used to control operation of the synchronizing framer  14  and channel Tx  18 .  
         [0007]     As is known in the art, the number and size of the SPEs  16  are selected based on the channel line rate. For example, for a channel line rate of 10 Gb/s, the synchronizing framer  14  may map subscriber traffic into a set of four STS-48 envelopes. Other combinations may equally be used, such as, for example, eight STS-12 envelopes.  
         [0008]     Normally, a respective buffer fill signal  28  is generated for each tributary FIFO  8 , and used to control the insertion of stuffing bits into the corresponding SPE tributary.  
         [0009]     As shown in  FIG. 1   b,  at the terminating node  30 , the incoming STS  20  is decoded by a channel receiver (Rx)  32  and processed by a pointer processor  34  to demap each SPE tributary from the STS  20 . Thus, stuffing bits are stripped out of each tributary, and the remaining subscriber data stored in a respective tributary FIFO  36  of an elastic store  38 . An Rx local clock signal  40 , having a frequency f 3  which is preferably referenced to the SONET Primary Reference  24 , is supplied to a desynchronizer Phase locked Loop (PLL)  42 . A buffer fill signal  44  generated by the tributary FIFO  36  is used to steer the Phase locked Loop (PLL)  42 , so that the PLL output constitutes a recovered data clock signal  46  having a frequency f 4  which approximates the data rate of the subscriber traffic. As a result, by reading data from the tributary FIFO  36  at a timing of the recovered data clock  46 , a desynchronizer framer  48  can generate a recovered subscriber signal  50  in which the original timing is closely approximated.  
         [0010]     For cases in which the channel line rate is equal to or greater than the subscriber data rate (i.e. for f 1 ≦f 2 ), the introduction of idle packets to replace “missing” subscriber traffic enables the synchronizing and desynchronizing framers  14  and  48  to compensate any differences between the tributary data rate and the channel rate. However, this mapping technique suffers a limitation in that the fill signal  44  of the Rx tributary FIFO buffer  3   b  tends to vary in a step-wise manner as idle packets are inserted and striped from SPE tributaries. This causes timing jitter in the recovered subscriber signal  50 .  
         [0011]     In most situations, the amount of timing jitter introduced by mapping and demapping asynchronous client signal traffic to and from STS frames does not create any difficulties. However, if the timing of the subscriber signal is critical, such as an HDTV signal or a subscriber-originated SONET signal (e.g. for SONET over SONET applications) the introduced timing jitter can noticeably degrade the quality of the subscriber&#39;s signal. Accordingly, there is interest in methods that enable subscriber traffic to be transparently mapped on to SONET STS signals. An important aspect for transparency is to preserve the original timing information of the subscriber signal.  
         [0012]     Applicant&#39;s co-pending U.S. patent application Ser. No. 09/972,686 (Roberts et al.), entitled Method and Apparatus for Digital Data Synchronization, which was filed on Oct. 9, 2001, teaches a method of rate adapting an asynchronous subscriber signal on to SONET STS frames without incurring waiting time jitter, by measuring the phase and frequency of the (asynchronous) subscriber signal and encoding this information into the frame overhead. Thus, as shown in  FIG. 2   a,  a multi-bit digital timing estimate (F) is calculated (at 52) to indicate the difference between the tributary data rate f 1 , and the Tx local clock frequency f 2 . In the embodiment of  FIG. 2   a,  the timing estimate F is computed as a ratio between f 1  and f 2 . In other embodiments, the timing estimate F may be computed as a phase difference between the subscriber data signal and Tx local clock signal, calculated at the time that a corresponding client data block is mapped into the SPE. In either case, the timing estimate F is supplied to the synchronizing framer  14  and used in place of the tributary fill  28  to control the insertion of stuff bytes into the SPE tributary. The timing estimate F is also inserted into the SPE tributary and conveyed with the subscriber data to the terminating node  30 .  
         [0013]     As shown in  FIG. 2   b,  at the terminating node  30 , the pointer processor  34  demaps each SPE tributary, and extracts the timing estimate F. The timing estimate F extracted from the SPE tributary is used in place of the elastic store fill signal  44  to steer the desynchronizer Phase locked Loop (PLL)  54 . Consequently, the PLL output constitutes a recovered data clock signal  56  having a frequency f 4  which more closely approximates the original frequency f 1  of the subscriber traffic. As a result, by reading subscriber data from the tributary FIFO  36  at a timing of the recovered data clock  56 , the desynchronizer framer  48  can generate a recovered subscriber signal  50  in which the original timing is substantially restored.  
         [0014]     An important attribute of U.S. patent application Ser. No. 09/972,686 is that the timing estimate F enables the transparent transport of the subscriber&#39;s original phase variations over a reasonable bandwidth (e.g. 100 Hz-1 KHz). Traditionally, waiting time jitter is reduced by narrowing the bandwidth of the desynchronizer PLL  42  (see  FIG. 1   b ). However, very narrow filtering at the desynchronizer PLL  42  has the effect of attenuating the subscriber signal&#39;s phase variations and hence looses some transparency of the subscriber timing characteristics. U.S. patent application Ser. No. 09/972,686 overcomes this limitation by the accurate measurement of subscriber phase/frequency at the synchronizer  2 . This information is encoded within the STS frame (in the form of timing estimate F) and used to steer the desynchronizer PLL  54 , which substantially eliminates waiting time jitter.  
         [0015]     Another important attribute of U.S. patent application Ser. No. 09/972,686 is that, unlike conventional systems, an elastic store fill signals  28  and  44  are not used to control insertion of stuff bytes at either the transmitting or receiving nodes  2 ,  30 . This avoids problems due to the fill signals  22  and  44  containing clock noise, cross-talk from other signals, and data patterning. Instead of the elastic store fill signals  22  and  44 , U.S. patent application Ser. No. 09/972,686 uses the timing estimate F as an accurate measurement of the subscriber phase/frequency to drive stuffing at the transmitting node  2  and generation of the recovered data clock signal  56  at the receiving node  30 .  
         [0016]     A limitation of U.S. patent application Ser. No. 09/972,686 is that subscriber signal phase and frequency information (F) is measured with respect to the Tx local clock signal  26  ( FIG. 2   a ) at the originating node  2 , whereas the recovered data clock signal  56  generated by the desynchronizer PLL  54  is based on the Rx local clock signal  40  at the terminating node  30 . Ideally, both of the Tx and Rx clock signals  26  and  40  are derived from the same SONET primary reference  24 , and thus will be synchronous. However, the originating and terminating nodes  2  and  30  may well be situated in different SONET islands, with the result that there may be a frequency difference (Δf) between the Tx and Rx local clock signals  26  and  40 . Any such frequency difference means that the recovered data clock frequency f 4  will not precisely match the original subscriber data frequency f 1 , and thus accurate recovery of the original timing of the subscriber signal may not be possible.  
         [0017]     The SONET standard provides a method for frequency aligning an incoming SONET signal at a SONET network element using the payload pointers (e.g. the H 1 , and H 2  bytes) within the Transport Overhead (TOH). These pointers provide a positive or negative word stuff of size 8*N bits for an STS-N signal. For a positive stuff, the start position of data in the Synchronous Payload envelope (SPE) is advanced by 8*N bits, and for a negative stuff, the start position is pushed back by 8*N bits. In principle, the positive and or negative stuff indications that arrive at the terminating SONET node provides a measure of the relative frequency difference between the originating and terminating nodes.  
         [0018]     However, a pointer change (i.e. a positive or negative stuff indication) is typically generated when, at an elastic store between the synchronous write and read clocks, the elastic store fill exceeds a predetermined threshold. These pointer changes represent large phase changes in the subscriber data (equivalent to 8*N bits) and occur at a worst case nominal stuffing ratio of zero (see D. L. Duttweiler, “Waiting Time Jitter” Bell System Technical Journal, vol. 51, pp 165-207, January, 1972), which means they can induce a large jitter/wander penalty on the data payload arriving at the terminating node  30 . As well, these pointer changes may have been generated by clock noise or cross-talk, due to the fact that they are driven by an elastic store fill signal.  
         [0019]     Various methods have been proposed for reducing the jitter/wander penalty imposed by pointer changes. For example, a common method is to simply allow the large phase step due to the pointer change to occur in the Rx elastic store  38 , and filter this phase step directly into the desynchronizer PLL  42  using, for example, a low-pass filter  58  ( FIG. 1   b ). This method directly couples the pointer filtering with the desynchronizer function, which means that the pointer and desynchronizer functions cannot be optimized independently.  
         [0020]     The publication “Analysis of Techniques for the Reduction of Jitter Caused by SONET Pointer Adjustments”, Kusyk et al., IEEE Transaction on communications, Vol. 42, pp 2036-2050, describes a “pointer leaking” method in which, when a pointer is received, bits corresponding to the pointer are leaked from a first elastic store to a second elastic store (not shown) in order to reduce the slope of the phase change. The second elastic store fill drives the desynchronizer PLL  42 , via a low pass filter  58  in a conventional manner.  
         [0021]     The publication “Waiting Time Jitter Reduction by Synchronizer Stuff Threshold Modulation”, W. D. Grover et al., Proceedings of IEEE GLOBECOM &#39;87, vol. 1, pp 514-518, describes a threshold modulation method, which involves encoding word stuffing at the synchronizer such that a traditional desynchronizer can largely filter the frequency of the word stuffs. Again this method uses the elastic store fill  44  to drive the desynchronizer PLL  42 , which again implies that the pointer and desynchronizer functions cannot be optimized independently.  
         [0022]     As described above, prior art techniques focus on the problem of reducing the jitter imposed on the subscriber signal by pointer changes through the network. Hence the prior art does not address the problem of how to jointly optimize pointer filtering with transparent synchronizer/desynchronizer operation. Nor does the prior art address the question of how to process pointer filters for SONET over SONET applications.  
         [0023]     Accordingly, a method and apparatus capable of accurately estimating the bit rate of subscriber traffic conveyed through a synchronous network between different SONET islands remains highly desirable.  
       SUMMARY OF THE INVENTION  
       [0024]     An object of the present invention is to provide a method and apparatus for accurately estimating the bit rate of subscriber traffic conveyed through a synchronous network between different SONET islands.  
         [0025]     Accordingly, an aspect of the present invention provides a method of estimating a bit rate (f 1 ) of a digital signal conveyed through a SONET network between an originating node and a terminating node. The digital signal received by the originating node is processed to determine a result of a first function of the signal bit rate (f 1 ) and a respective Tx local reference frequency (f 2 ) of the originating node. A result of a second function of the Tx local reference frequency (f 2 ) and a respective Rx local reference frequency (f 3 ) of the terminating node is calculated. Finally, a result of a third function of the respective first and second function results is calculated, to derive an estimate of the signal bit rate (f 4 ) relative to the Rx local reference frequency (f 3 ).  
         [0026]     A further aspect of the present invention provides a method of estimating a relationship between a Tx local reference frequency (f 2 ) of an originating node and an Rx local reference frequency (f 3 ) of a terminating node of a SONET network. An STS/STM signal is conveyed through the network between the originating node, and received at the and terminating node. Each successive payload pointer of the received STS/STM signal is processed to generate a corresponding pointer parameter. The pointer parameters are filtered to derive an estimate of the relationship between the Tx local reference frequency (f 2 ) and the Rx local reference frequency (f 3 ).  
         [0027]     A still further aspect of the present invention provides A method of desynchronizing asynchronous subscriber traffic conveyed through a synchronous network. An STS/STM signal encapsulating the subscriber traffic is received at a terminating node of the network. The STS signal includes a timing estimate (F) indicative of a frequency difference between a data rate (f 1 ) of the subscriber traffic and a Tx local reference frequency (f 2 ) of an originating node of the network. The encapsulated subscriber traffic is buffered within an elastic store. Each successive payload pointer of the received STS/STM signal is processed to generate a corresponding pointer parameter. These pointer parameters are digitally filtered to derive an estimated relationship (Δf) between the Tx local reference frequency (f 2 ) and an Rx local reference frequency (f 3 ) of the terminating node. The local reference frequency (f 3 ) is then adjusted using the timing estimate (F) and the estimated relationship (Δf), to generate a recovered clock signal having a frequency (f 4 ) that substantially equals the data rate (f 1 ) of the subscriber traffic. Finally, the buffered asynchronous subscriber traffic is read at a timing of the recovered clock signal.  
         [0028]     An important application for transparent signal transport is SONET over SONET, in which a SONET signal is encapsulated transparently over another SONET signal. For example, the emerging G. Modem standard (G.709 standard) utilizes an STS-192 signal, which is encapsulated within ODU-2 (G.709 standard), which, in turn, is encapsulated within an STS-204 for transport across SONET infrastructure. In this scenario, any pointer changes in the STS-204 line overhead must be filtered in order to desynchronize the STS-192 embedded in the ODU-2, and preserve the original STS-192 phase and timing. The present invention enables this operation, even across differing SONET islands. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     Further features and advantages of the present invention will become apparent from the following detailed description, taken in combination with the appended drawings, in which:  
         [0030]      FIGS. 1   a  and  1   b  are block diagrams schematically illustrating conventional originating and terminating nodes, respectively, of an optical communications network;  
         [0031]      FIGS. 2   a  and  2   b  are block diagrams schematically illustrating originating and terminating nodes, respectively, known from U.S. patent application Ser. No. 09/972,686;  
         [0032]      FIG. 3  is a block diagram schematically illustrating principal elements of a pointer filter in accordance with the present invention;  
         [0033]      FIG. 4  is a state diagram schematically illustrating operating modes of the state machine of the embodiment of  FIG. 3 ;  
         [0034]      FIG. 5  is a block diagram schematically illustrating a terminating node employing a pointer filter in accordance with the embodiment of  FIG. 3  used to steer a phase locked loop; and  
         [0035]      FIG. 6  is a block diagram schematically illustrating the terminating node of  FIG. 2   b  employing a pointer filter in accordance with the embodiment of  FIG. 3 . 
     
    
       [0036]     It will be noted that throughout the appended drawings, like features are identified by like reference numerals.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0037]     The present invention provides a method an apparatus for accurately estimating the bit rate of subscriber traffic received through a synchronous network having two or more SONET islands. Embodiments of the invention are described below with reference to  FIGS. 3-5 .  
         [0038]     In general, the present invention operates by filtering pointer parameters to estimate a relationship between the Tx reference frequency (f 2 ) at an originating node and the Rx reference frequency (f 3 ) at the terminating node. This relationship can then be used for various purposes, such as, for example, estimating the bit rate of subscriber traffic relative to the Rx reference frequency (f 3 ). Pointer parameters may take any of a variety of forms, such as, for example, payload pointer changes, or pointer rates. As may be appreciated, the relationship between the Tx reference frequency (f 2 ) and the Rx reference frequency (f 3 ) may be represented in various ways, depending on how the information is to be used. Exemplary formulations include: a frequency difference (Δf) between the Tx and Rx clock frequencies; a phase difference (ΔP); a ratio  
       (     e   .   g   .           ⁢                 f2   f3         or                 f3   f2     )                 
 
 between the Tx and Rx clock frequencies; or any other suitable function of the Tx and Rx reference frequencies, such as  
         (     1   -     f2   f3       )     .       
 
 For ease of description, the relationship between the Tx and Rx local reference frequencies will be generically referred to herein as the frequency difference (Δf), it being understood that any of the above formulations may equally be used, and may in fact be preferable, in certain circumstances. 
 
         [0041]     As shown in  FIG. 3 , the present invention can be implemented using a pointer filter  60  coupled to receive payload pointer changes from the pointer processor  34  of the terminating node  30 . The pointer filter  60  processes the payload pointer changes to generate a multi-bit estimate of the frequency difference (Δf) between the Tx and Rx local clock signals. Operation of the pointer filter  60  to calculate the frequency difference (Δf) between the Tx and Rx local clock signals is described below.  
         [0042]     As is known in the art, the Synchronous Payload Envelope (SPE) is permitted to float within the STS frame. The starting position of the SPE within the STS frame payload capacity is denoted by a payload pointer located in the H 1  and H 2  bytes of the line overhead (LOH). As the frame traverses the network, differences between the frame rate and the SPE rate (for example, due to a SONET reference frequency difference between SONET islands) will result in periodic changes in the payload pointer values. The presence of a pointer change can be identified by the value of the “New Data Flag” (NDF) located in bits  1 - 4  of the payload pointer. The sign of the change is indicated by inversion of either bits  7 ,  9 ,  11 ,  13  and  15  (the I-bits of the payload pointer) in the case of a positive change, or bits  8 ,  10 ,  12 ,  14  and  16  (the D-bits of the payload pointer) in the case of a negative change. According to the SONET standard, payload pointer changes are implemented by incrementing the value of the payload pointer by one. Thus the rate of pointer changes (relative to the payload pointer frequency within the STS signal), and the stuff word size, provides a direct measure of the difference between the STS frame rate and the SPE rate, and thus the difference (Δf) between the Tx and Rx reference frequencies (f 2  and f 3 ).  
         [0043]     As each STS frame arrives at the terminating node  30 , the pointer processor  34  operates to examine the payload pointers within the TOH and forward corresponding pointer change information to the pointer filter  60 . In the illustrated embodiment, if the NDF value indicates no change in the payload pointer, then the pointer processor  34  sends a “Zero” indication to the pointer filter  60 . On the other hand, if the NDF value indicates that the payload pointer has changed, then pointer processor  34  determines the sign of the change (e.g. positive or negative) and sends a corresponding indication to the pointer filter  60 . This means that the pointer filter  60  will receive a respective pointer change indication (e.g. positive, negative or zero) for each payload pointer received by the pointer processor  34 .  
         [0044]     As shown in  FIG. 3 , the pointer filter  60  generally comprises a digital phase locked loop (DPLL)  62  controlled by a state machine  64 , and a digital divider  66 . The output of the digital divider  66  is a multi-bit low noise estimate of the frequency difference (Δf).  
         [0045]     The DPLL  62  is formed by a digital ADDER  68 , a phase error calculator  70 , and a digital filter block  72  controlled by the state machine  64 . The digital ADDER  68  operates to add the pointer change indications received from the pointer processor  34  to the negative of the digital filter output. The resulting digital signal is supplied to the phase error calculator  70 , which computes an estimate of the phase error (PE) of the SPE using, for example, an operator of the form  
         1     1   -     z     -   1           ,       
 
 where z represents the current output value of the digital ADDER  68 . 
 
         [0047]     The phase error estimate (PE) is supplied to the state machine  64  and the digital filter  72 . The state machine  64  uses the phase error estimate PE for managing state transitions, as will be described below. The digital filter  72  operates to filter the phase error estimate (PE) using, for example, an operator of the form:  
           2     -   g       ⁢     (     1   +     2     -   n       +       (       2     -   n       -   1     )     ⁢     z     -   1           )         1   -     z     -   1             
 
 where z is the current phase error estimate (PE), and (n) and (g) are parameters supplied by the state machine  64 . As may be appreciated, the parameters n and g determine the filter characteristic, and thereby the effective bandwidth of the DPLL  62 . Thus the state machine  64  can operate to select wide or narrow bandwidth operating modes of the DPLL  62 , as required, by selecting appropriate values for the parameters n and g. If desired, the required parameter values (for both wide and narrow bandwidth operating modes) can be predetermined and stored in a memory (not shown) for use during run-time of the state machine  64 . 
 
         [0049]     The output of the digital filter  72  is a multi-bit error value that is directly proportional to the rate of “slippage” of the SPE within the STS frame as it traverses the optical network, measured in bits-per-pointer (or, equivalently, bits-per-tributary). This error value can be normalized (at 66) to a low noise estimate of the frequency difference (Δf) by dividing the error value by the tributary length (in bits).  
         [0050]     As may be appreciated, in order to properly account for frequency differences between SONET islands, the DPLL  62  must be able to acquire the SPE frequency within a comparatively wide pull-in range (e.g., on the order of about 10 Hz). However, once the SPE frequency has been acquired, the DPLL  62  must be able to maintain phase lock within a range of about 0.0025 Hz, in order to satisfy standard MTIE ANSI specifications for normal operation.  
         [0051]     In general, the state machine  64  operates to select the appropriate DPLL bandwidth based on the phase error estimate (PE) and a frequency estimate (FE) derived from the pointer changes received from the pointer processor  34 . The frequency estimate (FE) may be calculated (at 74) using an equation of the form  
         FE   =       sign   ·   L     Count       ,       
 
 where: “Sign” is the sign of the pointer change (e.g. positive or negative); L is the stuff word size (in bits); and “Count” is an integer count of received payload pointers between successive pointer changes. Thus the frequency estimate (FE) provides an estimate of the relative difference between the STS frame rates at the originating and terminating nodes, measured in bits-per-pointer (or, equivalently, bits-per-SPE tributary). This frequency estimate (FE) is sufficiently accurate to permit the DPLL  62  (operating in the narrow bandwidth mode) to acquire phase lock within the size of a conventional elastic store FIFO  36 . If desired, the frequency estimate (FE) can be recalculated for each successive payload pointer, which means that the value will be updated for eachtributary. Jitter in the frequency estimate (FE) value can be reduced by using an average count value calculated over a desired number of successive pointer changes. 
 
         [0053]     As shown in  FIG. 4 , the state machine  64  transitions between a wide bandwidth state  76  and a narrow bandwidth state  78 , depending on the value of the phase error estimate (PE), and a timer value C. A timer  80  ( FIG. 3 ) is used to ensure that the state machine  64  remains in one state for a predetermined minimum period of time (such as, for example, Co=20 seconds) before transitioning to the other state. This is advantageous in that it prevents erroneous operation of the state machine  64  rapidly oscillating between states.  
         [0054]     During initialization (e.g. during system start-up), the state machine  64  enters the Wide bandwidth state  78  in order to acquire the SPE frequency and pull the phase error estimate (PE) close to zero. While the phase error estimate (PE) is equal to or greater than a predetermined threshold (such as, for example, the stuff word size L) the state machine  64  remains in the Wide bandwidth state  78 . Within the Wide bandwidth state  78 , the state machine  64  selects appropriate “wide bandwidth” parameter values n and g, and supplies these values to the digital filter  72  of the DPLL  62 , to yield a DPLL bandwidth of, for example, about 10 Hz. Under these conditions, the impulse response of the DPLL  62  satisfies the short term MTIE specification for phase transients, while the jitter performance meets the network limit requirements.  
         [0055]     When the phase error estimate (PE) drops below the predetermined threshold (e.g. the stuff word size L), the state machine  64  transitions to the narrow bandwidth state  78 . If the current timer value C is greater than the predetermined limit Co (e.g. 20 seconds), the timer  80  is reset to C=0. In addition, the input state is set to zero, and the feedback state is set to the frequency estimate (FE).  
         [0056]     Within the narrow bandwidth state  78 , the state machine  64  selects appropriate “narrow bandwidth” parameter values n and g, and supplies these values to the digital filter  728  of the DPLL  62 , to yield a DPLL bandwidth of, for example, about 0.0025 Hz. With this arrangement, the impulse response of the DPLL  62  meets the short term MTEI ANSI specification for normal operation. As long as the phase error estimate (PE) remains below the threshold, the state machine  64  will remain in the narrow bandwidth state  78 . If the phase error estimate (PE) rises above the threshold, which may, for example, occur during a change in the SONET Primary Reference frequency, the state machine will return to the wide bandwidth state  76  in order to reacquire the SPE rate.  
         [0057]     An advantageous feature of the present invention is that pointer changes are digitally processed independently of the desynchronizer circuit (formed by the pointer processor  34 , elastic store  38 , desynchronizer PLL  54  and desynchronizer framer  48 ). Digitally processing the pointer changes independently of the subscriber data enables this separation. A benefit of this separation is that it enables independent optimization of pointer and data desynchronization functions. This attribute is significant since the performance requirements for the pointer changes and data desynchronization are typically different, and the nature of degradations are unique. An additional benefit of the present invention is that, because pointer changes are digitally filtered directly, the data elastic store fill signal with its associated hazards of clock noise, cross-talk, and data patterning is avoided.  
         [0058]     The solution of the present invention also enables the important advantage that two different bandwidths for pointer change processing and data synchronization can be maintained simultaneously. Thus, for example, bandwidths of less than 100 mHz can be maintained in the pointer filter DPLL  62  to meet the stringent SONET standards (e.g. for SONET over SONET applications), while the desynchronizer PLL  54  bandwidth can be very wide to facilitate transparency.  
         [0059]     As discussed in detail above, pointers of a received STS signal are processed to generate a multibit estimate of the frequency difference (Δf) between the respective local clocks at the originating and terminating nodes of a SONET path. This information can be used in various ways, including (without limitation): 
        the frequency difference (Δf) can be provided to a network management system (not shown) and used for monitoring network clock synchronization quality. For example. the frequency difference (Δf) can be compared to a predetermined threshold, and an alarm raised if the threshold is exceeded;     the frequency difference (Δf) can be used in combination with the frequency estimate (FE) and estimated phase error (PE) to enable intelligent handling of payload pointers by the pointer processor. For example, pointer arrival events can be classified (e.g. as being due to the frequency difference Δf or burst effects such as SONET primary reference changes etc.) and handled by different digital signal processing methods based on the classification result; and     the frequency difference (Δf) can be used to adjust the Rx local reference frequency f 3 , and thereby improve network transparency.        
 
         [0063]     In the embodiment of  FIG. 5 , the frequency difference (Δf) is used to steer a PLL  80  to generate an adjusted clock signal  82  having a frequency f 5  which closely approximates the Tx local clock frequency f 1 . If desired, the PLL  80  could be cascaded with the desynchronizer PLL  54  of the prior art transparent desynchroniser illustrated in  FIG. 2   b.  With this arrangement, the frequency f 4  of the recovered clock signal  56  generated by the desynchronizer PLL  54  would approximate the frequency f 1  of the subscriber traffic, to an arbitrary degree of accuracy. A limitation of this approach is that two cascaded Phase Locked Loop circuits are required, which increases the risk of noise in the frequency f 4  of the recovered clock signal  56 . Alternatively, the frequency difference (Δf) can be combined with the subscriber signal timing value (F) to generate a frequency offset value (FO), which is then used to steer a single desynchronizer PLL  54 . Such an embodiment is described below with reference to  FIG. 6 .  
         [0064]     As shown in  FIG. 6 , a terminating node  30   a  in accordance with the present invention operates in a manner that is generally similar to that described above with reference to  FIG. 2   b.  Thus, the pointer processor  34  demaps each SPE tributary from a received STS  20 , and extracts the timing estimate F. However, the pointer processor  34  also extracts pointer changes, which are filtered by the pointer filter  60  in the manner described above with reference to  FIGS. 3 and 4 . In the illustrated embodiment, the frequency difference (Δf) generated by the pointer filter  60  is used as a “scaling factor” for the timing estimate F, to thereby yield a frequency offset value (FO) which accounts for both the frequency difference between the original subscriber data signal frequency f 1  and the Tx reference frequency f 2 , and between the Tx reference frequency f 2  and the Rx reference frequency f 3 . Accordingly, the difference estimate (Δf) and the timing estimate F are supplied to a digital combiner  84 , which calculates the frequency offset FO.  
         [0065]     As shown in  FIG. 6 , the digital combiner  84  comprises a multiplier  86 , which normalizes the difference estimate (Δf) to the timing estimate F, and a digital ADDER  88  which then adds the normalized difference estimate to the timing estimate F, to yield the frequency offset (FO).  
         [0066]     The frequency offset (FO) is then used to steer the desynchronizer Phase locked Loop (PLL)  54 , so that the PLL output constitutes a recovered clock signal  56  having a frequency f 4  which approximates the original frequency f 1  of the subscriber traffic to an arbitrary degree of accuracy. As a result, by reading subscriber data from the tributary FIFO  36  at a timing of the recovered clock  56 , the desynchronizer framer  48  can generate a recovered subscriber signal  50  in which the original timing is restored, again, to an arbitrary degree of accuracy.  
         [0067]     In the foregoing description, the DPLL  62  is controlled by a state machine  64  to switch between wide and narrow band operation, based on an estimated phase error of the SPE within the received STS frame. As mentioned above, the bandwidth of the DPLL  62  is controlled via the filter characteristic of the digital filter  72 . Accordingly, while a dual bandwidth DPLL is described, those of ordinary skill in the art will appreciate that any desired number of different bandwidths may be implemented, by suitably controlling the digital filter  72 .  
         [0068]     The embodiment(s) of the invention described above is(are) intended to be exemplary only. The scope of the invention is therefore intended to be limited solely by the scope of the appended claims.