Abstract:
The invention provides a NANO-ampere operable differential circuit by means of a few additional components. The multi-input differential circuit consists of more than three input elements that are connected to the same tail node, and an adaptive bias current control circuit. Applications of this multi-input differential circuit, which are, for instance comparators and voltage followers, do have a very low operation current at a normal operation mode. The proposed differential circuit is applicable for all kinds of analog complex circuits to attain nano-power operation.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to an over-three multi-input differential amplifier with adaptively controlled biasing.  
           [0002]    1. Description of the Related Art  
           [0003]    Not only handy equipment but also every kind of electric equipment incorporates a voltage comparator circuit or differential amplifier applied for low voltage detection or battery charge-discharge control or signal buffering. It is assumed that a few billion of such equipments are in use worldwide. If one comparator circuit draws 10 μA for example, the total idling current is multiplied by 10 billion sets and 10,000 ampere is given. If an operation voltage is assumed at 5 volt, the total power consumption reaches 50 KILO-watt what is equivalent to one power plant capacity. The present invention will reduce current consumption of a voltage comparator and differential amplifier drastically to contribute to energy saving on a global scale.  
           [0004]    2. Description of the Prior Art  
           [0005]    [0005]FIG. 18 shows a conventional prior differential circuit diagram applied for voltage comparator circuit. A differential circuit is composed of MP 1 , MP 2 , MP 3 , MN 2  and MN 3 ; a buffer circuit is composed of MP 5  and MN 5 . A current source Ib and a N-FET MNB form a bias current generator. A reference voltage is fed to the Vref input terminal of the voltage comparator circuit. FIG. 19 shows simulated operation waveforms of the prior differential circuits in FIG. 18. When the input signal p is lower or higher than the reference input Vref sufficiently, the differential circuit and the buffer circuit draw constant idling current. The relationship between the idling current and rise-fall time or transition time of the output can be derived from the charge equation Q=CV roughly. As shown in FIG. 18, Id stands for the drain current of MP 2 ; Vg for the voltage transition at OUTX; dT 1  for the transition time of Vg; Ig for the charge or discharge current of Cg during dT 1 , then equation (1) is given as,  
             Ig*dT 1 =Cg*Vg   (1)  
           [0006]    Since Ig is a breeding current of Id, the value is supposed as ⅕ to {fraction (1/20)} generally. Letting the breeding factor K,  
           
         Ig=Id/K  
       
           [0007]    Only a part of dT 1  contributes to the delay time of output OUTX, it is assumed that around 80% of dT 1  occupies the delay time by evaluation from the relation between the threshold voltage and supply voltage.  
             T 1=0.8* dT 1=0.8 *K* ( Cg*Vg )/ Id   (1)  
           [0008]    “dT 2 ” stands for the transition time of OUTX; Ic for idling current of MP 5 ; all of Id flows into CL when MN 5  is off state, then following equation is derived.  
             dT 2=( CL*Vdd )/ Ic    
           [0009]    The delay time T 2  is measured at the half position of supply voltage, then  
             T 2=0.5 *dT 2  
           [0010]    Letting a required delay specification be Tos,  
             Tos&lt;T 1 +T 2  
             Id&gt; 0.8 *K*Cg*Vg/T 1  (2)  
             Ic&gt; 0.5 *CL*Vdd/T 2  (3)  
           [0011]    At the rise transition the load capacitor CL is charged from MN 5  and the idling current of MP 5  does not contribute to transition time. Then the delay at the rise transition equals with sum of dT 1  and dT 3 . Since the gate of MN 5  is biased forward sufficiently at the rising transition of OUTX usually, the delay dT 3  is fairly smaller than dT 1 . However when the idling current Id is set to very little level, it should be noted that the total delay time becomes very large number.  
           [0012]    The idling current of whole circuit Ii is given as,  
             Ii= 2 *Id+Ic    
           [0013]    The drain current “Id” is multiplied with 2 because Id is the idling current of one side of differential circuit.  
           [0014]    For example, T 1 &lt;20 μS, T 2 &lt;5 μS, Cg=0.1 pF, CL=50 pF, Vg=2V, Vdd=3V, K=20,  
           [0015]    Ii&gt;19.8 μA  
           [0016]    In case of, T 1 &lt;5 μS and T 2 &lt;2 μS  
           [0017]    Ii&gt;61.5 μA  
           [0018]    In this way, the minimum idling current can be evaluated by a required specification for output delay time.  
           [0019]    [0019]FIG. 19 shows simulated waveforms of the circuit in FIG. 18 when the input p is raised slowly from ground level to VDD level and then falls to ground level again. Even though the transition is very slow as few hundreds hours in an actual voltage detector application, the simulation time scale is accelerated for easy observation. “co” indicates the output waveform of prior comparator circuit when the bias current is designed to meet the required delay time less than 24 μS. “qo” indicates the output waveforms of prior circuit shown in FIG. 18 in which the bias current is limited below 200 nA. The delay time at rise or fall transition is 59 μS, 728 μS respectively, those delay time are fairly large and not suitable for general applications.  
           [0020]    A voltage follower circuit is also popular application of a differential amplifier and useful for measurement circuit condition of a differential amplifier. FIG. 20 shows a voltage follower circuit diagram modified from the connection in FIG. 18. The configuration of differential circuit part is same as the circuit in FIG. 18; the output is connected with the m input to form a voltage follower amplifier with unity gain. The output waveform follows identically with the p input signal ideally. FIG. 21 is a simulated waveform diagram of the circuit in FIG. 20. A denoted “co” shows a waveform of the output when a sufficient idling current is supplied, measured to be 11.6 μA shown as “vvdco”. The denoted “qo” shows a waveform when the idling current is limited to low level such as 588 nA. The waveform of “co” follows with the p input signal roughly and the delay time is 27 μS. However “qo” has big delay 335 μS and dull transition waveform. A voltage follower application also sacrifices operation speed unless enough idling current is supplied to the differential circuit that is backed by previous equation (2) and (3).  
           [0021]    In the prior art, the idling current cannot be reduced from the certain limitation decided by a required transition delay time of the output. If it is set to lower current than the limitation, the transition delay time becomes very large and that will result in application problems. The order of microampere looks like negligible small in the aspect of total system current consumption, however the accumulated amount becomes huge value because multi-billion of equipments are in work on the global scale. It should be noted that reducing the idling current of a voltage comparator and differential amplifier incorporated in all of electric equipments is a significant subject for global energy saving.  
         SUMMARY OF THE INVENTION  
         [0022]    As described previously, it is impossible to reduce the idling current by means of prior circuit and design methodology such as the circuits in FIG. 18. The presented invention provides a means composing of small count of transistors and a design methodology proofed sufficiently by a formula well correlated with measured results.  
           [0023]    To solve the above problems, a new circuit configuration and a new design theory is proposed, in which the idling current can be designed on the order of NANO-ampere when the inputs are far away from a detective reference level, and only at the detection transition the operation current becomes required level to attain a specified transition delay time. It is well known that output transition time of the voltage comparator circuit relates to operation current. Therefore it is presumable that boosted operation current only at the detection transition will realize low power and high-speed circuit, however no prior proposal attains the goal with less transistor count and simple design theory. The invention presented that a new means and a method realize the current boost only at the output transition, by a combination of cascaded transistor architecture and conventional differential circuits of which transistor pairs are designed under a new theory. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    [0024]FIG. 1 is a circuit diagram showing an embodiment of the present invention.  
         [0025]    [0025]FIG. 2 is a transfer characteristic of circuit shown in FIG. 1 indicating an optimum operating condition claimed.  
         [0026]    [0026]FIG. 3 is a transfer characteristic of circuit shown in FIG. 1 indicating an improper operating.  
         [0027]    [0027]FIG. 4 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0028]    [0028]FIG. 5 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 4.  
         [0029]    [0029]FIG. 6 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0030]    [0030]FIG. 7 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 6.  
         [0031]    [0031]FIG. 8 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0032]    [0032]FIG. 9 is a transfer characteristic of circuit shown in FIG. 8.  
         [0033]    [0033]FIG. 10 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 8.  
         [0034]    [0034]FIG. 11 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0035]    [0035]FIG. 12 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 11.  
         [0036]    [0036]FIG. 13 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0037]    [0037]FIG. 14 is a transfer characteristic of circuit shown in FIG. 13.  
         [0038]    [0038]FIG. 15 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 13.  
         [0039]    [0039]FIG. 16 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0040]    [0040]FIG. 17 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application.  
         [0041]    [0041]FIG. 18 is a conventional differential amplifier for voltage comparator application.  
         [0042]    [0042]FIG. 19 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 18.  
         [0043]    [0043]FIG. 20 is a conventional differential amplifier for voltage follower application.  
         [0044]    [0044]FIG. 21 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 20.  
         [0045]    [0045]FIG. 22 is a circuit diagram showing an embodiment of the present invention as a voltage follower application.  
         [0046]    [0046]FIG. 23 is a transfer characteristic of circuit shown in FIG. 22.  
         [0047]    [0047]FIG. 24 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 23.  
         [0048]    [0048]FIG. 25 is a circuit diagram showing an embodiment of the present invention as a voltage follower application.  
         [0049]    [0049]FIG. 26 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 25.  
         [0050]    [0050]FIG. 27 is a circuit diagram showing an embodiment of the present invention as a voltage follower application.  
         [0051]    [0051]FIG. 28 is a simulation waveform diagram showing voltages and currents of respective node the circuit shown in FIG. 27.  
         [0052]    [0052]FIG. 29 is a circuit diagram showing an embodiment of the present invention as a voltage follower application.  
         [0053]    [0053]FIG. 30 is a circuit diagram showing an embodiment of the present invention as a voltage comparator application. 
     
    
     DETAILED DESCRIPTION  
       [0054]    [0054]FIG. 1 is a circuit diagram showing an embodiment of the present invention corresponding to the claim-1. M 3 , M 4 , M 5  and M 8  are N-FET. M 5  forms a bias current control circuit and is connected to three of input means M 3 , M 4 , M 8 . P-FET M 1 , M 2 , and M 7  are three load means and connected to the said input means. Each load means forms a current mirror coupled with P-FET M 11  in the bias current generation circuit and is controlled under constant current as soon as possible. Therefore it is regarded as a current source and works as a high impedance load device in an amplifier.  
         [0055]    Each of M 1  and M 3 , M 2  and M 4 , M 7  and M 8  constitutes an amplifier. Three amplifiers are connected to the bias current control circuit M 5  through a common node called tail node. An inverting threshold of each amplifier can be calculated from a well-known source-drain current equation of FET roughly. Focusing on the amplifier composed of M 1  and M 3 .  
         [0056]    Id stands for drain current of M 3 ,  
           Id= 0.5 *Gm ( Vg−Vtn )( Vg−Vtn )(1+Lamda *Vds )  (5)  
         [0057]    Where Gm is the conductance of M 3 , Vtn is the threshold voltage, Vg is the input voltage, Lamda is the channel length modulation factor, and Vds is the source drain voltage.  
         [0058]    Being assumed that the inverting threshold of amplifier VT is defined as the source drain voltage of M 1  and M 3  is identical each other,  
           VT={SQR ( Id/ 0.5* Gm )+ Vtn}/SQR (1+Lamda *Vds )+ Vs   (6)  
           Vds =( Vdd−Vs )/2  
           Gm =(½)* u*Cox* ( W/L )  
         [0059]    Where Vs is the voltage level at the tail node, μ is the mobility of carrier; Cox is the gate oxide capacitance per unit area. Equation (6) indicates that the inverting threshold depends upon Gm namely FET size (W/L) since other parameter is constant value. Id flows both of M 1  and M 3 , the size ratio between M 1  and M 3  decide the inverting threshold. It is not contradict against well-known formula. Thus the inverting threshold of assumed single amplifier is simply expressed. In case of two input differential circuit, the inverting threshold can be also expressed by similar prior formula. However a more-than three multi-input differential amplifier does not have such an established design theory or methodology. The reason why is no inevitable market needs for a more-than three multi-input differential amplifier so far. The presented patent has discovered the validity of the multi-input amplifier in adaptive biasing circuit application and thereby the examples of embodiment describe the qualitative analysis and show the variety of applications.  
         [0060]    Embodyment  
         [0061]    In FIG. 1, the bias current control circuit M 5  has important roll. It is not restricted one component; more parts form it as described later. The present invention disclose that three amplifiers act each other in the range of the size of M 5  or the mirror current of bias current control circuit and a boundary condition is discovered successfully.  
         [0062]    Hereinafter, a total sum of FET means a summing size of FETs connected in parallel way.  
         [0063]    And a theoretical mirror current means a mirrored current under no obstacle to mirror operation. Usually the mirror current is proportional to transistor size.  
         [0064]    In the figure when the size of M 5  is larger than the sum of FET size M 1 , M 2  and M 7  or the theoretical mirror current of the bias current control circuit is larger than the total sum of mirror current of M 1 , M 2  and M 7 , the circuit in FIG. 1 is not functional. The tail node is shorted to ground level; the three amplifiers have no interaction each other.  
         [0065]    When the theoretical mirror current of the bias current control circuit is smaller than total sum of mirror current of M 1 , M 2  and M 7 , three amplifiers begin interaction each other. Since the total sum of mirror current of M 1 , M 2  and M 7  is limited under the mirror current primarily to be flowed, borrowing and lending of current among three amplifiers is caused to generate large voltage swing at output node. A large voltage swing at the output node is generated by borrowed or lent current change because the operation point of each three input-FET is just located on the threshold edge and even small drain current modulation produces large drain voltage deflection.  
         [0066]    [0066]FIG. 2 is a transfer characteristic of the circuit shown in FIG. 1 indicating an optimum operating condition. As shown in FIG. 1 the input of M 3  is connected to the input signal Vp, and a reference voltage is fed to the input of M 4  and M 8 . Due to three inputs, there are many combinations of input connection; a simple connection for transfer curve is adopted for easy understanding. In FIG. 2 the outputs Vo 1  and Vo 2  are offset from the reference input Vm 1.5V. The output Vo 1  changes from low to high at Vp=1.43V. It is called as theoretical offset, −70 mV in this case. The theoretical offset is not caused from a production deviation but designed intentionally. The output Vo 2  has +50 mV theoretical offset  
         [0067]    The characteristic like shown in FIG. 2 are produced by following method.  
         [0068]    The size of load FET M 1 , M 2 , M 7  or the size of input FET M 4 , M 3 , M 8  must meet with the below conditions,  
         [0069]    Vp=Vm, Vm=1.5V, Id 1 &lt;&lt;Id 3  and Id 2 &lt;&lt;Id 3 ,  
         [0070]    And Id 3 =17 nA, and VT 3 =1.5V and Equation (6).  
         [0071]    Where Id 1 , Id 2 , Id 3  is the drain current of M 4 , M 3 , M 8  respectively. VT 3  is inverting threshold of the output Vo 3 . The reason why being put Id 3 =17 nA is that the current source in the bias current generator is 20 nA and M 7  is mirrored with ration of 1 to 0.85.  
         [0072]    In case of FIG. 2, the size (W/L) of M 1 , M 2 , M 7 , M 5  is given as 1.1, 1.1, 0.85, and 2.5 respectively.  
         [0073]    When the size of M 5  is smaller than the sum of FET size M 2  and M 7  or the theoretical mirror current of the bias current controller is smaller than sum of mirror current of M 2  and M 7 , the circuit in FIG. 1 begins a misconduct operation. Decreasing the size of M 5 , the potential of tail node or M 4  source node goes up and it results in degradation of input voltage range of M 4 . In the end, M 4  cannot draw an enough current from M 2  to output a low level. As shown in FIG. 3, the denoted vo 1  is floated over the low level, which is reached by the denoted vo 2  or vo 3 . Therefore one of boundary condition is that the theoretical mirror current of the bias current control circuit is smaller than the total sum of mirror current of M 1 , M 2  and M 7 . And the other side is that the theoretical mirror current of the bias current controller is lager than the sum of mirror current of two load FET of three load FET, excluding largest one in the size. Even though it is called “boundary”, it is not digital condition since the drain current of FET is not discontinuous even around the threshold voltage.  
         [0074]    [0074]FIG. 4 is a circuit diagram showing a second embodiment of the present invention corresponding to the claim-1 and 2. It is applied as a voltage comparator of which bias current is controlled or increased adaptively. P-channel FET M 1 , M 2 , M 7  and N-channel FET M 3 , M 4 , M 5 , M 8  and M 6  have same connections as FIG. 1. Two N-channel FET M 9  and M 10  compose a current conversion circuit are connected to the output vo 1  having minus offset and the output vo 2  having plus offset. Both of vo 1  and vo 2  is at high state, the current conversion circuit flows a current through the bias current generation circuit and then increase a current in the bias current control circuit M 5  by positive feedback. N-FET M 13  and P-FET M 12  compose an output buffer that is connected to the output vo 3  having no offset.  
         [0075]    [0075]FIG. 5 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 4 as a voltage comparator.  
         [0076]    In the figure, a time scale is plotted on the horizontal axis and the number at pointing line indicates voltage or current. In case shown FIG. 5, VDD=3V, CL=50 pF, a constant voltage as VDD/ 2  is fed to the m input as a reference input and at the p input terminal a slowly changing triangular signal is fed. The voltage waveform of the output terminal Vo 1 , Vo 2 , Vo 3  and Vout are shown by “vo 1 ”, “vo 2 ”, “vo 3 ” and “vout” respectively, the current waveform of the voltage supply Vdd and the FET M 5  are shown by “vdd” and “m 5 ”.  
         [0077]    The p input is approaching to the reference voltage, both of the output vo 1  and vo 2  turn to high level so that M 9  and M 10  turn on to flow a current and the bias current control circuit increases current from 41 nA to 984 nA and then the whole circuit become activated. With the exception of this activated status, the whole circuit is operated under very low current consumption, and the supply current vdd is measured to be 177 nA or 61 nA. The output delay time is 41 μS at the fall transition, 21 μS at the rise transition that is fairy improved from the prior example 728 μS at fall and 59 μS at rise.  
         [0078]    A reference U.S. Pat. No. 4,690,391 has proposed similar circuit configuration as the present invention in FIG. 1 or FIG. 4. However, it is obvious that the referenced circuit has different operation mechanism and function. Because all of its output have theoretical zero offset, and the important relationship between a bias current and total sum of mirror current is not disclosed, and moreover the propose circuit concept never intend to apply for adaptive control by positive feed back current. Even though the present invention has similar circuit configuration as the referenced USP, it must be stressed that its essence, effectiveness, and claims are quite different.  
         [0079]    [0079]FIG. 6 is a circuit diagram showing a third embodiment of the present invention applied for a bipolar process or a silicon germanium process, corresponding to the claim-1 same as FIG. 4. PNP transistors Q 1 , Q 2 , Q 7  and NPN transistors Q 3 , Q 4 , Q 5 , Q 8  compose a three input differential amplifier. PNP transistor Q 9 , Q 10  and resistor R 3  compose a current conversion circuit. PNP transistor Q 11 , NPN transistor Q 6  and a current source I 1  form a bias current generator. A very high resistor or a transistor connected with fixed base potential can replace the current source I 1 . A bias current control circuit comprises of transistor Q 5  as the simplest case.  
         [0080]    The output vo 1  having minus offset and the output vo 2  having plus offset are over the forward potential Vbe, the current conversion circuit draws a current through the bias current generation circuit and then increase a current in the bias current control circuit Q 5  by the positive feedback. NPN transistor Q 13  and PNP transistor Q 12  compose an output buffer that is connected to the output vo 3  having no offset.  
         [0081]    [0081]FIG. 7 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 6 as a voltage comparator. In the figure, a time scale is plotted on the horizontal axis and the number at pointing line indicates voltage or current In case shown FIG. 6, Vcc=3V, CL=50 pF, a constant voltage Vcc/ 2  is fed to the m input as a reference voltage and at the p input terminal a slowly changing triangular signal is supplied. The voltage waveform of the output terminal Vo 1 , Vo 2 , Vo 3  and Vout are shown by “vo 1 ”, “vo 2 ”, “vo 3 ” and “vout” respectively, the current waveform of the voltage supply Vcc and the transistor Q 5  are shown by “vdd” and “q 5 ”.  
         [0082]    The p input is approaching to the reference voltage, both of vo 1  and vo 2  turn to lower level so that Q 9  and Q 10  turn on to flow a current and the voltage supply current increase from 580 nA to 22 μA.  
         [0083]    [0083]FIG. 8 is a circuit diagram showing a forth embodiment of the present invention corresponding to the claim-1. P-FETs are M 1 , M 2 , M 7 , M 12 , M 14 , and M 15 . N-FETs are M 3 , M 4 , M 5 , M 8 , M 6 , M 10  and M 13 . Four input means M 3 , M 4 , M 8  and M 16  are connected to a bias current control circuit composed of M 5 .  
         [0084]    Each of M 1 , M 7  and M 15  forms a current mirror coupled with P-FET M 2  and is controlled under constant current as soon as possible. Therefore it is regarded as a current source and works as a high impedance load device in an amplifier. A source of current mirror M 2  has diode connection then the drain output give a just small voltage swing, however a large voltage swing will appear at the output of M 1 , M 7  and M 15  when a current balance between a load device and a input device is collapsed.  
         [0085]    The FET M 1 , M 2 , M 7  and M 15  are four load means and connected to the said four input means respectively. Each of M 1  and M 3 , M 2  and M 4 , M 7  and M 8 , M 15  and M 16  composes an amplifier. All of four amplifiers are connected to the common “tail node”.  
         [0086]    An inverting threshold of each amplifier can be calculated from the size ratio of the input device and load device according to previous equation (6).  
         [0087]    The circuit in FIG. 8 has no boundary condition for M 5  likewise the differential circuit in FIG. 1 or FIG. 4 since the mirror current of load device is generated separately from bias current generation circuit.  
         [0088]    [0088]FIG. 9 is a simulated transfer characteristic of the circuit shown in FIG. 8.  
         [0089]    A reference voltage Vm=1.5V is fed to the input m of M 4 . The size of M 1  is smaller than that of M 2  to give a minus theoretical offset on the output Vo 1 . While M 7  is enlarged than that of M 2  to have plus offset for the output Vo 2 . The output Vo 3  has zero offset by making M 15  same size as M 2 . A current conversion circuit consists of two different types of FET P-channel M 10  and N-channel M 14 . The current conversion circuit draws a current during vo 1 =low and vo 2 =high and feed back to the bias current control circuit to increase the bias current.  
         [0090]    [0090]FIG. 10 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 8 as a voltage comparator.  
         [0091]    In the figure, a time scale is plotted on the horizontal axis and the number at pointing line indicates voltage or current. In case shown FIG. 10, VDD=3V, CL=50 pF, a constant voltage as VDD/ 2  is fed to the m input as a reference voltage and at the p input terminal a slowly changing triangular signal is fed. The voltage waveform of the output terminal Vo 1 , Vo 2 , Vo 3  and Vout are shown by “vo 1 ”, “vo 2 ”, “vo 3 ” and “vout” respectively, the current waveform of the voltage supply Vdd and the FET M 5  are shown by “vdd” and “m 5 ”.  
         [0092]    The p input is approaching to the reference voltage, the output vo 1  goes down to low level and the output vo 2  keeps high level so that M 14  and M 10  turn on to flow a current and the bias current control circuit increase the bias current from 49 nA to 1.75 μA and then the whole circuit become activated. In the outside of activated status, the whole circuit is operated under very low current consumption, and the supply current vdd is measured to be 107 nA or 69 nA.  
         [0093]    The output delay time is 27 μS at the fall transition, 9 μS at the rise transition that is fairy improved from the prior example.  
         [0094]    A reference U.S. Pat. No. 5,381,054 has proposed similar circuit configuration as the present invention in FIG. 8. However, it is obvious again that the referenced circuit has different operation mechanism and function. Because its application is limited for a switches and resistive network in the claims, and as a tacit understanding all of its output have theoretical zero offset, and then the circuit cannot be applied for adaptive control by positive feed back current. Namely the present invention has similar circuit configuration as the referenced USP, it must be stressed again that its essence, effectiveness, and claims are quit different.  
         [0095]    [0095]FIG. 11 is a circuit diagram showing a fifth embodiment of the present invention applied for a bipolar process or silicon germanium process, corresponding to the claim-1.  
         [0096]    PNP transistors are Q 1 , Q 2 , Q 7 , Q 12 , Q 14 , and Q 15 . NPN transistors are Q 3 , Q 4 , Q 5 , Q 8 , Q 6 , Q 10  and Q 13 . Four input devices Q 3 , Q 4 , Q 8  and Q 15  are connected to a bias current control circuit composed of Q 5 . Q 1 , Q 2 , Q 7  and Q 15  are four load devices and connected to the said four input device respectively. Each of Q 1  and Q 3 , Q 2  and Q 4 , Q 7  and Q 8 , Q 15  and Q 16  composes an amplifier. All of four amplifiers are connected to a common “tail node”.  
         [0097]    A current conversion circuit consists of different type transistors P-channel Q 10  and N-channel Q 14 . The current conversion circuit draws a current during vo 1 =low and vo 2 =high and feed back to the bias current control circuit to increase the bias current.  
         [0098]    NPN transistor Q 13  and PNP transistor Q 12  compose an output buffer that is connected to vo 3  having no offset.  
         [0099]    [0099]FIG. 12 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 11 as a voltage comparator.  
         [0100]    The p input is approaching to the reference voltage, both of the output Vo 1  and the output vo 2  turn to lower level so that Q 9  and Q 10  turn on to flow a current and the voltage supply current increase from 823 nA to 8 μA.  
         [0101]    [0101]FIG. 13 is a circuit diagram showing a sixth embodiment of the present invention corresponding to the claim-1. P-FETs are M 1 , M 2 , M 7 , M 12 , M 19 , and M 20 . N-FETs are M 3 , M 4 , M 5 , M 8 , M 6  and M 13 . Three input means M 3 , M 4  and M 8  are connected to a bias current control circuit composed of M 5 . M 1 , M 2  and M 7  are three load means and connected to the said three input device respectively. Each of M 1  and M 3 , M 2  and M 4 , M 7  and M 8  composes an amplifier. All of three amplifiers are connected to a common tail node.  
         [0102]    In this embodiment, a theoretical offset is not designed by a size ratio between a load device and input device, but generated by positive feedback loop through a current conversion circuit. An output of M 2  vo 1  is connected to the gate of M 19 ; an output of M 7  vo 2  is connected to the gate of M 20 . When the p input is equal to the reference input m, a current flow of M 19  and M 20  became peak, and therefore a feedback loop makes adaptive positive feedback operation just around the reference voltage. If the size of M 1  and M 3  is identical, the output vo 3  has zero offset, accordingly the bias current is increased just around the inverting threshold of vo 3 .  
         [0103]    [0103]FIG. 14 is a simulated transfer characteristic of the circuit shown in FIG. 13.  
         [0104]    In the figure, a voltage scale of the p input is plotted on the horizontal axis and the vertical axis shows voltage and current scale. In the case shown in FIG. 14, VDD=3V, CL=50 pF, a constant voltage as VDD/ 2  is fed to the m input.  
         [0105]    The voltage curve of the output terminal Vo 1 , Vo 2  and Vout are shown by “vo 1 ”, “vo 2 ” and “vout” respectively, the current characteristic curve of the FET M 5  is shown by “m 5 ”. The voltage characteristic curve of vo 3  is omitted for easy observation. As shown in the figure, vo 1  has plus offset about 100 mV, vo 2  has minus offset −100 mV. The direction of offset is different from other embodiment case. The current of the bias current control circuit M 5  swells between 1.4V and 1.6V. As shown in the figure, the current characteristic curve is symmetrical with respect to the reference voltage. This symmetry is attained by adjusted FET size of M 20 . The size of M 20  is much larger than that of M 19  to cancel a degradation of Gm caused by the back gate effect of M 20 . When the size of M 19  and M 20  is identical, the current characteristic curve is not symmetrical.  
         [0106]    [0106]FIG. 15 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 13 as a voltage comparator.  
         [0107]    In the figure, a time scale is plotted on the horizontal axis and the number at pointing line indicates voltage or current. In case shown in the figure, VDD=3V, CL=50 pF, a constant voltage as VDD/ 2  is fed to the m input and at the p input terminal a slowly changing triangular signal is fed.  
         [0108]    The voltage waveform of the output terminal Vo 1 , Vo 2 , Vo 3  and Vout are shown by “vo 1 ”, “vo 2 ”, “vo 3 ” and “vout” respectively, the current waveform of the voltage supply Vdd and the FET M 5  are shown by “vdd” and “m 5 ”.  
         [0109]    The p input is approaching to the reference voltage, the output vo 1  and the output vo 2  drift to lower level so that M 19  and M 20  increase the current and the bias current control circuit M 5  increases current from 23 nA to 288 nA and then the whole circuit become activated. In the outside of activated status, the whole circuit is operated under very low current consumption, and the supply current vdd is measured to be 44 nA or 81 nA.  
         [0110]    [0110]FIG. 16 is a circuit diagram showing a seventh embodiment of the present invention applied for a bipolar process or silicon germanium process, corresponding to the claim-1. A circuit configuration is analogical with the circuit in FIG. 13.  
         [0111]    PNP transistors are Q 1 , Q 2 , Q 7 , Q 12 , Q 19 , and Q 20 . NPN transistors are Q 3 , Q 4 , Q 5 , Q 8 , Q 6  and Q 13 . Three input means Q 3 , Q 4  and Q 8  are connected to a bias current control circuit composed of QM 5 . Q 1 , Q 2  and Q 7  are three load means and connected to the said three input means respectively. Each of Q 1  and Q 3 , Q 2  and Q 4 , Q 7  and Q 8  composes an amplifier. All of three amplifiers are connected to a common tail node.  
         [0112]    [0112]FIG. 17 is a circuit diagram showing an eighth embodiment of the present invention corresponding to the claim-1. P-FETs are M 1 , M 2 , M 7 , M 9  and M 12 . N-FETs are M 3 , M 4 , M 5 , M 8 , M 6  M 10  and M 13 . Three input devices M 3 , M 4  and M 8  are connected to a bias current control circuit composed of M 5 . M 1 , M 2  and M 7  are three load devices and connected to the said three input device respectively. Each of M 1  and M 3 , M 2  and M 4 , M 7  and M 8  composes an amplifier. All of three amplifiers are connected to a common tail node.  
         [0113]    Previously mentioned embodiments are voltage comparators. Present invention is useful for a voltage follower circuit too. FIG. 22 is a circuit diagram showing a ninth embodiment of the present invention corresponding to the claim-1 and 2. It is applied as a voltage follower of which bias current is controlled or increased adaptively. P-FET M 1 , M 2 , M 7 , M 12  and N-FET M 3 , M 4 , M 5 , M 8 , M 13  and M 6  have same connections as FIG. 4 excepting gate connection of M 4 . Major difference is a current conversion circuit. Two P-FET M 19  and M 20  compose a current conversion circuit are connected to the output Vo 1  having minus offset and the output Vo 2  having plus offset. Since two FET M 19  and M 20  is in parallel connection. N-FET M 13  and P-FET M 12  compose an output buffer that is connected to the output Vo 3  having no offset.  
         [0114]    [0114]FIG. 23 is a simulated transfer characteristic of the circuit shown in FIG. 22.  
         [0115]    In the figure, a voltage scale of the p input is plotted on the horizontal axis and the vertical axis shows voltage and current scale under the conditions as VDD=3V. CL=50 pF, a constant voltage as reference VDD/ 2  is fed to them input that is different connection from voltage follower operation.  
         [0116]    The voltage curve of the output terminal Vo 1 , Vo 2  and Vout are shown by “vo 1 ”, “vo 2 ” and “vout” respectively, the current characteristic curve of the voltage supply vdd and the FET M 5  is shown by “vdd” and “m 5 ” respectively. As shown in the figure, vo 1  has minus offset about −20 mV, vo 2  has plus offset about 40 mV. The current of the bias current control circuit M 5  is dented in the vicinity of the reference voltage. It means that the bias current turns to minimum when voltage of the output Vout is equal to the p input signal in the voltage follower application. While the bias current is boosted when the output Vout does not follow the p-input signal. Call as balance pocket for the dented current area. The balance pocket is an equal state between the p input and the output Vout, which does not require big power consumption to keep the same. The width of balance pocket is varying from a few uV to few hundred mV depending upon applications. If the width of balance pocket is zero, a voltage follower circuit becomes unstable due to critical response for very small disturbance. In other word, the balance pocket created from the offset of vo 1  and vo 2  produces a delay time in the feed back loop to make the positive feed back stable. Either of vo 1  or vo 2  turns to low state, the current conversion circuit flows a current through the bias current generation circuit and then increases a current in the bias current controller M 5  by positive feedback. In FIG. 23, the bias current of M 5  increases from 55 nA in the vicinity of reference voltage to 3.7 μA. In the application such as a voltage follower or an error sense amplifier, the output is approximately equal to input during balanced state. It is well known that a little power consumption can keep the balanced state. The present invention realizes very low power in balanced state by the innovation of multi-input differential amplifier with intentional offset control.  
         [0117]    [0117]FIG. 24 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 22 as a voltage follower. In the figure, a time scale is plotted on the horizontal axis and the number at pointing line indicates voltage or current. In case shown, VDD=3V, CL=50 pF, a pulse signal transiting between 1.2V and 2.2V is fed to the p input. The voltage waveform of the output terminal Vo 1 , Vo 2 , Vo 3  and Vout are shown by “vo 1 ”, “vo 2  ”, “vo 3 ” and “vout” respectively, the current waveform of the voltage supply Vdd and the FET M 5  are shown by “vdd” and “m 5 ”.  
         [0118]    The whole circuit is operated under very low current consumption, and the supply current vdd is measured to be 206 nA at balanced state 7,7_A at transition. The output delay time is 48 μS at rise transition, 12 μS at fall transition that is fairy improved from the prior example 335 μS at fall transition under 588 nA idling current.  
         [0119]    [0119]FIG. 25 is a circuit diagram showing a tenth embodiment of the present invention corresponding to the claim-1. It is applied as a voltage follower of which bias current is controlled or increased adaptively in the same way as FIG. 22. P-FET M 1 , M 2 , M 7 , M 11 , M 12  and N-FET M 3 , M 4 , M 5 , M 8 , M 13  and M 6  have same connections as FIG. 22 excepting gate connection of M 4 . A current conversion circuit is consists of P-FET M 19 , M 20  and N-FET M 17  which is connected to the output Vo 1  having minus offset and the output Vo 2  having plus offset. N-FET M 13 , M 14  and P-FET M 12  compose an output buffer that is connected to the output Vo 3  having zero offset. The gate of M 14  is connected to the output of M 17  in the current conversion circuit.  
         [0120]    [0120]FIG. 26 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 25 as a voltage follower. When the p input goes to high level, the output Vo 1  transits to low side and M 19  is biased forward to turn on and increase a current of the bias current control circuit. After rise-transition of the p input, the output Vout becomes same voltage as the p input and the idling current drops in a very little current state. When the p input goes to low level, the output vo 2  transits to low side and M 20  and M 17  pass a current to turn on M 14  and pull down the Vout until same level as the p input. In the figure the supply current vdd at balanced state is just 293 nA, and the delay time is 26 μS at rise transition and 20 μS at fall transition.  
         [0121]    Thus not only simple parallel connection but also more complex combination is effective for a current conversion circuit.  
         [0122]    [0122]FIG. 27 is a circuit diagram showing an eleventh embodiment of the present invention corresponding to the claim-1. P-FET M 19  and N-FET M 20 , M 17 , M 18  compose a current conversion circuit. A bias current control circuit consists of N-FET M 24  and M 5 . An output buffer has additional N-FET M 14  of which gate is connected to the current conversion circuit. A part of four input differential amplifier is same as the circuit in FIG. 8 and the transfer characteristic is similar to the diagram in FIG. 9. FIG. 28 is a simulated waveform diagram showing voltages and currents in respect to the circuit in FIG. 27 as a voltage follower.  
         [0123]    When the p input and vout are identical in voltage, the output vo 1  is low and the vo 2  is high level since M 19  and M 20  is off no current flows in the current conversion circuit. In FIG. 28 the current of supply current vdd is shown to be 199 nA or 194 nA. At the fall timing of the p input, the output vo 1  goes to high level to turn M 20  on and then M 17  and M 14  draw current to pull down the Vout until same level as the p input.  
         [0124]    As shown in the figure FET M 14  draws a peak current 6.5 μA and 1.7 nA at the steady state. At the rising edge of the p input, the output vo 2  goes to low level to turn M 19  on and then M 18  and M 24  draw mirrored current to increase the bias current of the differential circuit as a result the output of M 15  and the output vout M 12  response are accelerated. In the figure the current of M 24  peaks at 693 nA. Due to a overshoot of the output vout M 14  draws current at the same rising edge to pull back the overshoot.  
         [0125]    [0125]FIG. 29 is a voltage follower circuit diagram showing a twelfth embodiment of the present invention. An output buffer consists of N-FET M 11 , M 13 , P-FET M 10  and M 12 . P-FET M 19  and N-FET M 20 , M 9  compose a current conversion circuit. M 9  is inserted so as to decrease the bias current at the balance status between the input and the output.  
         [0126]    [0126]FIG. 30 is a circuit diagram shows an embodiment of the present invention. It is a modification from the circuit in FIG. 13. The circuit in FIG. 13 is P-FET input differential amplifier; FIG. 29 shows a N-FET input equivalent. Other embodiments also have such an equivalent conversion that is easily derivable although every one is not shown in figure. “FET” means not only MOS type but also junction type, TFT and, GaAs. Every kind of FET is applicable for the present invention.  
         [0127]    For example a plus offset or a minus offset can be omitted for low-voltage detector application because a input does not pass away from a reference input.  
         [0128]    And even though the claime-3 also is not shown, for instance, an output buffer can be deleted when a load is small and drivable from the output of differential amplifier.  
         [0129]    Thus the differential amplifier comprising more than 3 amplifiers connected with common tail node and having various offsets is more excellent than every prior art in respect to number of element, design flexibility of offset, power saving and stability by balancing pocket and the usefulness of present invention is proven.