Abstract:
System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to Advanced Process Control (“APC”) as applied to semiconductor fabrication and, more particularly, to system and method for implementing a wafer acceptance test (“WAT”) APC with routing model. 
         [0002]    APC has become an essential component in semiconductor fabrication facilities (“fabs”) for enabling continued improvement of device yield and reliability at a reduced cost. Significant elements of APC include integrated metrology, fault detection and classification, and run-to-run control. APC aids in reducing process variation as well as production costs. A key requirement for effective APC is that metrology tools are available to measure key parameters within an acceptable time frame. Additionally, methods must be provided for analyzing and interpreting measurement data. In practice, APC requires rich in-line measurements because the manufacturing processes are usually subjected to disturbance and drift caused by a variety of sources. 
         [0003]    Similarly, wafer-level testing plays a crucial role in IC fabrication, particularly as the cost for post production processes increases. A defective wafer is identified by the processing and disposed of before it undergoes post-processing. A wafer acceptance test (“WAT”) includes numerous testing items and is a vital part of the IC fabrication process. In a conventional foundry, WAT is performed as defined by a predetermined WAT model that specifies a number of test sites for wafers of a particular size. As advances have been made in IC fabrication, more specific testing has been required to determine product quality. 
       SUMMARY 
       [0004]    System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling a tuning process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
           [0006]      FIG. 1  is a block diagram illustrating a lifecycle of a lot of semiconductor wafers during a fabrication process in accordance with the prior art. 
           [0007]      FIG. 2  is a block diagram illustrating a lifecycle of a lot of semiconductor wafers during a fabrication process in accordance with one embodiment. 
           [0008]      FIG. 3  is a more detailed block diagram illustrating a lifecycle of a lot of semiconductor wafers during the fabrication process shown in  FIG. 2 . 
           [0009]      FIGS. 4A-4B  illustrate a lot sampling process of the fabrication process of  FIG. 3 . 
           [0010]      FIGS. 5A-5B  illustrate a wafer sampling process of the of the fabrication process of  FIG. 3 . 
           [0011]      FIGS. 6A-6B  illustrate a WAT prediction process of the of the fabrication process of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    The present disclosure relates generally to APC as applied to semiconductor fabrication and, more particularly, to system and method for implementing a wafer acceptance test (“WAT”) APC with routing model. 
         [0013]    It is understood, however, that specific embodiments are provided as examples to teach the broader inventive concept, and one of ordinary skill in the art can easily apply the teachings of the present disclosure to other methods and systems. Also, it is understood that the methods and systems discussed in the present disclosure include some conventional structures and/or steps. Since these structures and steps are well known in the art, they will only be discussed in a general level of detail. Furthermore, reference numbers are repeated throughout the drawings for the sake of convenience and example, and such repetition does not indicate any required combination of features or steps throughout the drawings. 
         [0014]      FIG. 1  illustrates a lifecycle of a lot of semiconductor wafers during a fabrication process in accordance with prior art. The process starts in a step  100 . In step  102 , a key process, which may comprise, for example, a photolithography process, an etching process, a deposition process, a chemical mechanical processing (“CMP”) process, a coating process, a developing process, a thermal treatment process, or some other process, is performed on the wafers using appropriate process tools and/or computing devices, which may comprise processing, control, storage, display and/or input/output capabilities, as well as other equipment as necessary and appropriate to perform the respective functions thereof. In step  104 , key in-line measurements on a sample (i.e., one or two wafers) of the wafer lot. It will be recognized that the measurements taken in step  104  are related to features created by the key process performed in step  102 . For example, if the key process performed in step  102  is an etching process, then one of the key in-line measurements taken in step  104  may be a trench depth measurement. The key in-line measurements taken in step  104  are used to tune a process APC  106 , which controls operation of the key process performed in step  102 . In view of the fact that methods tuning an APC and using the APC to control a related process are well known to those having ordinary skill in the art, specific methods of accomplishing these tasks will not be discussed herein. It will be recognized that, while only one of each of the key process step  102 , key inline measurements step  104 , and process APC  106  are shown, multiple process steps and related measurement steps and APCs will likely be implemented during “front end” processing  110  of the wafers. During “back end” processing  112 , in step  114 , inter-metal (“IM”) WAT is performed. Subsequently, and typically several weeks later, in step  116 , final WAT is performed and each wafer that passes the final WAT undergoes post processing and is shipped out in step  118 . Results of the final WAT step  116  are fed back to a WAT APC  120 , which provides control signals to a tuning process step  122  and/or controller parameters about device electronic properties of a process APC  106 . The tuning process step tunes the electrical properties of the subsequent wafers, for example, by performing an appropriate implant process to correct electrical properties of the wafer. 
         [0015]      FIG. 2  illustrates a lifecycle of a lot of semiconductor wafers during a fabrication process in accordance with a novel embodiment described herein. Similar to the process shown in  FIG. 1 , the process in  FIG. 2  starts in a step  200 . In step  202 , a key process, which may comprise, for example, a photolithography process, an etching process, a deposition process, a chemical mechanical processing (“CMP”) process, a coating process, a developing process, a thermal treatment process, or some other process, is performed on the wafers. In step  204 , key in-line measurements on a sample (i.e., one or two wafers) of the wafer lot. It will be recognized that the measurements taken in step  204  are related to features created by the key process performed in step  202 . For example, if the key process performed in step  202  is an etching process, then one of the key in-line measurements taken in step  204  may be a trench depth measurement. The key in-line measurements taken in step  204  are used to tune a process APC  206 , which controls operation of the key process performed in step  202 . In view of the fact that methods tuning an APC and using the APC to control a related process are well known to those having ordinary skill in the art, specific methods of accomplishing these tasks will not be discussed herein. It will be recognized that, while only one of each of the key process step  202 , key inline measurements step  204 , and process APC  206  are shown, multiple process steps and related measurement steps and APCs will likely be implemented during “front end” processing  210  of the wafers. 
         [0016]    During “back end” processing  212 , in step  214 , inter-metal (“IM”) WAT is performed. Subsequently, and typically several weeks later, in step  216 , final WAT is performed and each wafer that passes the final WAT undergoes post processing and is shipped out in step  218 . In accordance with features of one embodiment, as will be described in detail in connection with  FIG. 3  et seq., rather than feeding the results of the final WAT step  216  back to the WAT APC  220  for use in tuning a tuning process  222  and/or a process APC  206 , the results of the IM WAT step  214 , which are available much sooner than the final WAT results, are used for this purpose. 
         [0017]    Referring now to  FIG. 3 , in accordance with features of embodiments described herein, results of the IM WAT step  214  are fed back to the WAT APC  220  via a lot sampling process  300 , a wafer sampling process  302 , and a WAT prediction process  304 , each of which will be described in greater detail with reference to  FIGS. 4A-4B ,  5 A- 5 B, and  6 A- 6 B, respectively. 
         [0018]    In particular,  FIG. 4A  is a flowchart of a method of performing the lot sampling process  300  ( FIG. 3 ). In particular, the process  300  is used to select one or more lots for sampling in accordance with one embodiment. Referring to  FIG. 4B , the process  300  employs a first table  400  comprising a chamber-lot matrix with processed lot count to prioritize lots for optimizing chamber coverage and a second table  402  comprising chamber-lot matrix with sampled lot count to prioritize lots for optimizing sampling rate balance. In the first table  400 , lots are prioritized according to a sum of chamber total moves for the most representative stages, or process steps. It will be recognized that each stage may be implemented by one of multiple process tools. In the second table  402 , lots are prioritized to achieve a chamber sampling rate balance. 
         [0019]    Returning to  FIG. 4A , in step  420 , weekly move lots that have passed a contact_photo process step but that have not passed an M 2 _CMP process step are collected and in step  422 , the table  400  ( FIG. 4B ) is generated. In particular, each column of a first group of columns A, collectively designated in  FIG. 4B  by a reference numeral  404 , represents a move lot, with each column being identified by a corresponding the lot number (i.e., L 1 -L 15 ). The lots represented in the first group of columns A  404  are divided into two suffix groups  406 A,  406 B, although a greater number of suffix groups may be used. Each row in the table  400  corresponds to a tool for performing each of N stages. For example, as illustrated in the table  400 , three tools (Tool- 1 , Tool- 2 , and Tool- 3 ) are employed in stage  1 ; five tools (Tool- 4  through Tool- 8 ) are employed to perform stage  2 , and so on. 
         [0020]    A weekly total lot count for each tool is respectively entered in a column B, as designated by a reference numeral  408 , for the tool. In particular, the weekly total lot count is the sum of all of the lots represented in the group of columns A  404  processed by the particular tool. For example, three lots (L 1 , L 5 , L 9 , and L 14 ) were processed by Tool- 1 , so the entry in the column B  408  for Tool- 1  is 4. A total number of lots from the previous week for each tool not covered that week is entered in a column C, as designated by a reference numeral  410 . For example, Tool- 1  was not covered in the previous week and the lot count for Tool- 1  for that week was 3. A column D, as designated by a reference numeral  411  indicates whether the corresponding tool has been sampled, with a 0 indicating the tool has not been sampled and a 1 indicating that it has. A final row  412  indicates a cycle- 1  score for the corresponding lot. The cycle- 1  score for each lot is calculated by scoring each tool N using the following equation: 
         [0000]      Tool Score N   =A   N *( B   N   +C   N )*(1 −D   N ) 
         [0000]    and then summing all of the tool scores for the lot. For example, using lot L 1 , the tool score for Tool- 1  is 1*(4+3)*(1−0) or 7; the tool score for Tool- 4  is 1*(2+1)*(1−0) or 3; the tool score for Tool-N is 1*(6+4)*(1−0) or 10. It will be noted that the tool scores for the remaining tools will be 0, as A=0 for each of those tools. Therefore, the cycle- 1  score for lot L 1  is the sum of the tool scores; i.e., 7+3+10 or 20. Once the tool scores have been calculated for each of the lots, in step  424 , a lot with the highest cycle- 1  score is selected. It will be noted that if two or more lots have the same cycle- 1  score, the lot processed earlier will be selected. From the table  400 , the lot L 4  is selected. In step  426 , a determination is made whether 100% tool coverage has been achieved. If not, execution proceeds to step  428  in which a determination is made whether an over-sampling quota has been met. If not, execution returns to step  422  and the first table is updated to remove the selected lot (in this case, lot L 4 ) and the value in column D  411  for each of the tools used to process lot L 4  (Tool- 2 , Tool- 5 , and Tool-N) will be set to 1 to indicate that the tool has been sampled. It should be noted that each time the step  422  is executed, a lot in the next suffix group should be selected to balance the sampling rate for all groups. This loop continues until there is either 100% tool coverage in step  426  or the over-sampling quota is met in step  428 . Once the over-sampling quota is met in step  428 , in step  430 , the weekly total lot count for all tools that were not covered is saved for inclusion in the first table for the following week. 
         [0021]    If in step  426 , 100% tool coverage has been achieved (as indicated by all of the values in column D  411  being set to 1), in step  432 , the second table  402  is generated. The second table  402  is identical to the most recently updated version of the first table  400 , except that (1) the entry in column D  411  for each of the tools is 1 instead of 0; and (2) instead of including a cycle- 1  score for each lot L 1 -L 15 , the table  402  includes a cycle- 2  score for each of the lots in a row  414 . The cycle- 2  score for each lot is calculated by scoring each tool N using the following equation: 
         [0000]      Tool Score N   =A   N   *D   N /( B   N   +C   N ) 
         [0000]    and then summing all of the tool scores for the lot. For example, using lot L 1 , the tool score for Tool- 1  is 1*1/(4+3) or 0.143; the tool score for Tool- 4  is 1*1/(2+1) or 0.333; the tool score for Tool-N is 1*1/(6+4) or 0.1. It will be noted that the tool scores for the remaining tools will be 0, as A=0 for each of those tools. Therefore, the cycle- 2  score for lot L 1  is the sum of the tool scores; i.e., 0.143+0.333+0.1 or 0.576. Once the tool scores have been calculated for each of the lots in step  432  and the second table  402  has been generated, the lot with the lowest cycle- 2  score is selected in step  434 . It will be noted that if two or more lots have the same cycle- 2  score, the lot processed earlier will be selected. 
         [0022]    In step  436 , a determination whether the over-sampling quota has been met. If not, execution returns to step  432  and the table  402  is updated by removing the selected lot. This loop is repeated until the over-sampling quota is met in step  436 . It should be noted that each time the step  432  is executed, a lot in the next suffix group should be selected to balance the sampling rate for all groups. Upon completion of steps  430  or  436 , execution proceeds to step  438 , in which the lots selected in steps  424  and  434  are used for wafer sampling and WAT prediction as described hereinbelow. It will be noted that in an optional step  440 , a GUI may be provided for enabling a user to define suffix groups and sampling rates, including over-sampling quotas, for the lots for use in connection with the generation and updating of the tables  400 ,  402 , in steps  422 ,  432 , respectively. 
         [0023]      FIGS. 5A and 5B  illustrate the wafer sampling process  302  of the process of  FIG. 3 . It will be recognized that the process is performed for each of the lots selected in the process illustrated in  FIGS. 4A-4B . Referring first to  FIG. 5A , in block  500 , the final WAT data for one of the selected lots is accumulated and then divided into groups of three wafers each, as represented by blocks  502 ( 1 )- 502 (N). Next, a lot mean error (“Lot_Mean_Error”) is calculated for each of the groups  502 ( 1 )- 502 (N), as represented by blocks  504 ( 1 )- 504 (N), using an equation  550  shown in  FIG. 5B . Additionally, standard error values (“STD_Error”) are calculated for each of the groups  502 ( 1 )- 502 (N), as represented by blocks  506 ( 1 )- 506 (N), using an equation  552  shown in  FIG. 5B . Next, an index (Index x ) is calculated for each of the groups using an equation  554  shown in  FIG. 5B  and the groups are ranked by index, as represented in  FIG. 5A  by blocks  508 ( 1 )- 508 (N). In the equation  554 , w 1 -w 4  represent weights selected based on past experience. A x  represents a PMOS mean error for the group, A a  represents the lot mean error, and A s  represents the standard error. B x  represents a PMOS standard error for the group, B a  represents the lot mean error, and B s  represents the standard error. C x  represents an NMOS mean error for the group, C a  represents the lot mean error, and C s  represents the standard error. Finally, D x  represents an NMOS standard error for the group, C a  represents the lot mean error, and D s  represents the standard error. 
         [0024]    ** FIG. 5B  illustrates a table  560 , which includes mean error, standard error, and index data for three months (May, June, and July) for each of three wafer groups ([ 6 ] [ 13 ] [ 18 ], [ 6 ] [ 11 ] [ 22 ], and [ 6 ] [ 7 ] [ 23 ]). In step  510  ( FIG. 5A ), a robust sampling slot selection is performed. Generally, this consists of selecting the wafer group with the highest index as the sample wafer group for use in performing the WAT prediction process described below. Although a new group may be picked each month based on the preceding month&#39;s data, it is anticipated that, so long as a group&#39;s index remains sufficiently high, the group will be maintained as the sample wafer group. 
         [0025]      FIGS. 6A-6B  illustrate the WAT prediction process  304 . It will be recognized that, while final WAT is performed for all wafers of a lot, IM WAT is performed for only a sample number of such wafers; therefore, the WAT prediction process  304  models final WAT for all wafers of the lot based on the IM WAT data for the sample wafers of the lot based on routing of the wafers. Referring to  FIG. 6A , each of grids  600 ( 1 )- 600 (N) represents one of N wafer processing stages. Referring for the sake of example to the grid  600 (N) point a represents sample IM WAT data for a sample wafer a for the stage N. Similarly, points b and c each represent sample IM WAT data for sample wafers b and c, respectively, for the stage N. It will be recognized that, although not shown, a data point a exists on each of the grids  600 ( 1 )- 600 (N- 1 ) representing respective sample IM WAT data for wafer  1  for each of those stages, respectively. The same is true for IM WAT data for wafers b and c. Using wafer a as an example, a line  602 ( a ) thorough the points a on all of the grids  600 ( 1 )- 600 (N) represents a tool trajectory for the wafer a. Similarly, lines  602 ( b ),  602 ( c ), through the points b and c, respectively, on all of the grids  600 ( 1 )- 600 (N) represent tool trajectories of the wafers b and c. It will be recognized that two wafers that have identical tool trajectories should have identical properties/IM WAT data. A point x on the grid  600 (N) represents an unknown data value that must be predicted from the data for wafers a, b, and c. 
         [0026]    Referring now to  FIG. 6B , the data illustrated in  FIG. 6A  is evaluated as follows. In a step  620 , a distance z between x and each of a, b, and c, respectively, at each stage is calculated using the equation  620 . For example, using the data for wafer a as an example, in the equation  620 , for each stage that the trajectory of point x intersects with that of wafer a, the value of Φ at that stage will be true, otherwise, the value of Φ at that stage will be false. Accordingly, z x,a  represents the number of stages at which the trajectories of x and a intersect. Next, an equation  622  is applied to determine a weight ω x,i  for each wafer. In particular, the value for z x,a  determined using the equation  620  is divided by the number of stages to normalize the value. Next, an equation  624  is used to determine WAT data for wafer x. Finally, a known bias is applied to the estimated WAT data for x determined in step  622  to more closely approximate the actual final WAT data for the wafer. The adjusted WAT data may then be used by the WAT APC  220  in the same manner as the final WAT data is used by the WAT APC  120  in the prior art embodiment illustrated in  FIG. 1 . 
         [0027]    Although only a few exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. 
         [0028]    It is understood that various different combinations of the above-listed embodiments and steps can be used in various sequences or in parallel, and there is no particular step that is critical or required. Moreover, each of the processes depicted in the drawings can be implemented on multiple devices, including computing devices, and implementation of multiple ones of the depicted modules may be combined into a single device, including a computing device. Furthermore, features illustrated and discussed above with respect to some embodiments can be combined with features illustrated and discussed above with respect to other embodiments. Accordingly, all such modifications are intended to be included within the scope of this invention.