Abstract:
Frequency translation and applications of same are described herein, including frequency synthesizers that employ universal frequency translation technology. The universal frequency translation technology includes a device for switching, a device for storing, and an energy transfer signal for controlling the switching device. The energy transfer signal may include pulses having apertures sufficiently wide to effect substantial energy transfer.

Description:
The present application is a continuation-in-part of the following pending U.S. applications, which are incorporated herein by reference in their entireties: 
     “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998 now U.S. Pat. No. 6,061,551; 
     “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/376,359, filed Aug. 18, 1999, now U.S. Pat. No. 6,266,518, which itself is a continuation of U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, now U.S. Pat. No. 6,061,551; 
     “Matched Filter Characterization and Implementation of Universal Frequency Translation Method and Apparatus,” Ser. No. 09/521,879, filed Mar. 9, 2000, which itself is a continuation-in-part of U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals Including Resonant Structures for Enhanced Energy Transfer,” Ser. No. 09/293,342, filed Apr. 16, 1999, which itself is a continuation-in-part of U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, now U.S. Pat. No. 6,061,551; and 
     “Method and System for Down-Converting an Electromagnetic Signal, Transforms for Same, and Aperture Relationships,” Ser. No. 09/550,644, filed Apr. 14, 2000, which is a continuation-in-part of U.S. patent application entitled “Matched Filter Characterization and Implementation of Universal Frequency Translation Method and Apparatus,” Ser. No. 09/521,879, filed Mar. 9, 2000, which itself is a continuation-in-part of U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals Including Resonant Structures for Enhanced Energy Transfer,” Ser. No. 09/293,342, filed Apr. 16, 1999, which itself is a continuation-in-part of U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, now U.S. Pat. No. 6,061,551. 
    
    
     CROSS-REFERENCE TO OTHER APPLICATIONS 
     The following applications of common assignee are related to the present application, and are herein incorporated by reference in their entireties: 
     “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, now U.S. Pat. No. 6,061,551. 
     “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998, now U.S. Pat. No. 6,091,940. 
     “Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed Oct. 21, 1998, now U.S. Pat. No. 6,061,555. 
     “Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998, now U.S. Pat. No. 6,049,706. 
     “Applications of Universal Frequency Translation,” Ser. No. 09/261,129, filed Mar. 3, 1999, now U.S. Pat. No. 6,370,371. 
     “Method and System for Down-Converting Electromagnetic Signals Having Optimized Switch Structures,” Ser. No. 09/293,095, filed Apr. 16, 1999, now allowed. 
     “Method and System for Down-Converting Electromagnetic Signals Including Resonant Structures for Enhanced Energy Transfer,” Ser. No. 09/293,342, filed Apr. 16, 1999. 
     “Method and System for Frequency Up-Conversion with a Variety of Transmitter Configurations,” Ser. No. 09/293,580, filed Apr. 16, 1999, now allowed. 
     “Integrated Frequency Translation and Selectivity with a Variety of Filter Embodiments,” Ser. No. 09/293,283, filed Apr. 16, 1999. 
     “Matched Filter Characterization and Implementation of Universal Frequency Translation Method and Apparatus,” Ser. No. 09/521,879, filed Mar. 9, 2000. 
     “Method, System, and Apparatus for Balanced Frequency Up-Conversion of a Baseband Signal,” Ser. No. 09/525,615, filed Mar. 14, 2000. 
     “DC Offset, Re-radiation, and I/Q Solutions using Universal Frequency Translation Technology,” Ser. No. 09/526,041, filed Mar. 14, 2000. 
     “Method and System for Down-converting an Electromagnetic Signal, and Transforms for Same, and Aperture Relationships,” Ser. No. 09/550,644, filed Apr. 4, 2000. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is generally related to frequency translation, and applications of same. More particularly, the present invention relates to a frequency synthesizer and applications of the same. Particularly, it is directed to a system and method for providing an output signal at a precise frequency or set of frequencies. As an example, a set of frequencies centered 30 KHz apart may be generated for use in cellular communications implementations. 
     2. Related Art 
     Conventional frequency synthesizers require precise frequency sources at or near the frequency of interest. These precise frequency sources are often very expensive. The present invention permits the use of a very stable frequency source centered at any frequency, thereby permitting the use of a lower cost frequency source. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to frequency translation, and applications of same. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same. 
     The invention may include one or more receivers, transmitters, and transceivers. According to embodiments of the invention, at least some of these receivers, transmitters, and transceivers are implemented using universal frequency translation (UFT) modules. The UFT modules perform frequency translation operations. Embodiments of the present invention incorporating various applications of the UFT module are described below. 
     Implementations of the invention exhibit multiple advantages by using UFT modules. These advantages include, but are not limited to, lower power consumption, longer power source life, fewer parts, lower cost, less tuning, and more effective signal transmission and reception. The present invention can receive and transmit signals across a broad frequency range. The structure and operation of embodiments of the UFT module, and various applications thereof are described in detail in the following sections. 
     Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     The present invention is described with reference to the accompanying drawings, wherein: 
     FIG. 1A is a block diagram of a universal frequency translation (UFT) module according to an embodiment of the invention; 
     FIG. 1B is a more detailed diagram of a UFT module according to an embodiment of the invention; 
     FIG. 1C illustrates a UFT module used in a universal frequency down-conversion (UFD) module according to an embodiment of the invention; 
     FIG. 1D illustrates a UFT module used in a universal frequency up-conversion (UFU) module according to an embodiment of the invention; 
     FIG. 2 is a block diagram of a UFT module according to an alternative embodiment of the invention; 
     FIG. 3 is a block diagram of a UFU module according to an embodiment of the invention; 
     FIG. 4 is a more detailed diagram of a UFU module according to an embodiment of the invention; 
     FIG. 5 is a block diagram of a UFU module according to an alternative embodiment of the invention; 
     FIGS. 6A-6I illustrate exemplary waveforms used to describe the operation of the UFU module; 
     FIG. 7 illustrates a UFT module used in a receiver according to an embodiment of the invention; 
     FIG. 8 illustrates a UFT module used in a transmitter according to an embodiment of the invention; 
     FIG. 9 illustrates an environment comprising a transmitter and a receiver, each of which may be implemented using a UFT module of the invention; 
     FIG. 10 illustrates a transceiver according to an embodiment of the invention; 
     FIG. 11 illustrates a transceiver according to an alternative embodiment of the invention; 
     FIG. 12 illustrates an environment comprising a transmitter and a receiver, each of which may be implemented using enhanced signal reception (ESR) components of the invention; 
     FIG. 13 illustrates a UFT module used in a unified down-conversion and filtering (UDF) module according to an embodiment of the invention; 
     FIG. 14 illustrates an exemplary receiver implemented using a UDF module according to an embodiment of the invention; 
     FIGS. 15A-15F illustrate exemplary applications of the UDF module according to embodiments of the invention; 
     FIG. 16 illustrates an environment comprising a transmitter and a receiver, each of which may be implemented using enhanced signal reception (ESR) components of the invention, wherein the receiver may be further implemented using one or more UFD modules of the invention; 
     FIG. 17 illustrates a UDF module according to an embodiment of the invention; 
     FIG. 18 is a table of exemplary values at nodes in the UDF module of FIG. 17; 
     FIG. 19 is a detailed diagram of an exemplary UDF module according to an embodiment of the invention; 
     FIGS.  20 A and  20 A- 1  are exemplary aliasing modules according to embodiments of the invention; 
     FIGS. 20B-20F are exemplary waveforms used to describe the operation of the aliasing modules of FIGS.  20 A and  20 A- 1 ; 
     FIG. 21 illustrates an enhanced signal reception system according to an embodiment of the invention; 
     FIGS. 22A-22F are exemplary waveforms used to describe the system of FIG. 21; 
     FIG. 23A illustrates an exemplary transmitter in an enhanced signal reception system according to an embodiment of the invention; 
     FIGS. 23B and 23C are exemplary waveforms used to further describe the enhanced signal reception system according to an embodiment of the invention; 
     FIG. 23D illustrates another exemplary transmitter in an enhanced signal reception system according to an embodiment of the invention; 
     FIGS. 23E and 23F are exemplary waveforms used to further describe the enhanced signal reception system according to an embodiment of the invention; 
     FIG. 24A illustrates an exemplary receiver in an enhanced signal reception system according to an embodiment of the invention; 
     FIGS. 24B-24J are exemplary waveforms used to further describe the enhanced signal reception system according to an embodiment of the invention; 
     FIG. 25 illustrates a system diagram of a frequency synthesizer according to the present invention; 
     FIG. 26 illustrates a first exemplary implementation of a generalized frequency translation device; 
     FIG. 27 illustrates a second exemplary implementation of a generalized frequency translation device; 
     FIG. 28 illustrates a third exemplary implementation of a generalized frequency translation device; 
     FIG. 29 illustrates an exemplary frequency spectrum of the output of the signal generator; 
     FIG. 30 illustrates an exemplary frequency spectra of the output of the first generalized frequency translation device; 
     FIG. 31 illustrates an exemplary frequency spectrum of the output of the first filter; 
     FIG. 32 illustrates an exemplary frequency spectra of the output of the second generalized frequency translation device, in the implementation wherein f 2 &lt;f 1 ; 
     FIG. 33 illustrates an exemplary frequency spectra of the output of the second generalized frequency translation device, in the implementation wherein f 2 &gt;f 1 ; 
     FIG. 34 illustrates an exemplary frequency spectrum of the output of the second filter, in the implementation wherein f 2 &gt;f 1 ; 
     FIG. 35 illustrates an exemplary flowchart of a first embodiment of the invention; 
     FIG. 36 illustrates an exemplary flowchart of an alternate embodiment of the present invention; 
     FIG. 37 illustrates an exemplary frequency spectra of the output of the first generalized frequency translation device in an alternate embodiment of the present invention; 
     FIG. 38 illustrates an exemplary frequency spectra of the output of the second generalized frequency translation device in an alternate embodiment of the present invention; 
     FIGS. 39-42 illustrate exemplary implementations of a switch module according to embodiments of the invention; 
     FIGS. 43A-B illustrate exemplary aperture generators; 
     FIGS. 44-45 illustrate exemplary aperture generators; 
     FIG. 46 illustrates an oscillator according to an embodiment of the present invention; 
     FIG. 47 illustrates an energy transfer system with an optional energy transfer signal module according to an embodiment of the invention; 
     FIG. 48 illustrates an aliasing module with input and output impedance match according to an embodiment of the invention; 
     FIG. 49A illustrates an exemplary pulse generator; 
     FIGS. 49B and C illustrate exemplary waveforms related to the pulse generator of FIG. 49A; 
     FIG. 50 illustrates an exemplary energy transfer module with a switch module and a reactive storage module according to an embodiment of the invention; 
     FIGS. 51A-B illustrate exemplary energy transfer systems according to embodiments of the invention; 
     FIG. 52A illustrates an exemplary energy transfer signal module according to an embodiment of the present invention; 
     FIG. 52B illustrates a flowchart of state machine operation according to an embodiment of the present invention; 
     FIG. 52C is an exemplary energy transfer signal module; 
     FIG. 53 is a schematic diagram of a circuit to down-convert a 915 MHz signal to a 5 MHz signal using a 101.1 MHz clock according to an embodiment of the present invention; 
     FIG. 54 shows exemplary simulation waveforms for the circuit of FIG. 53 according to embodiments of the present invention; 
     FIG. 55 is a schematic diagram of a circuit to down-convert a 915 MHz signal to a 5 MHz signal using a 101 MHz clock according to an embodiment of the present invention; 
     FIG. 56 shows exemplary simulation waveforms for the circuit of FIG. 55 according to embodiments of the present invention; 
     FIG. 57 is a schematic diagram of a circuit to down-convert a 915 MHz signal to a 5 MHz signal using a 101.1 MHz clock according to an embodiment of the present invention; 
     FIG. 58 shows exemplary simulation waveforms for the circuit of FIG. 57 according to an embodiment of the present invention; 
     FIG. 59 shows a schematic of the circuit in FIG. 53 connected to an FSK source that alternates between 913 and 917 MHz at a baud rate of 500 Kbaud according to an embodiment of the present invention; 
     FIG. 60A illustrates an exemplary energy transfer system according to an embodiment of the invention; 
     FIGS. 60B-C illustrate exemplary timing diagrams for the exemplary system of FIG. 60A; 
     FIG. 61 illustrates an exemplary bypass network according to an embodiment of the invention; 
     FIG. 62 illustrates an exemplary bypass network according to an embodiment of the invention. 
     FIG. 63 illustrates an exemplary embodiment of the invention; 
     FIG. 64A illustrates an exemplary real time aperture control circuit according to an embodiment of the invention; 
     FIG. 64B illustrates a timing diagram of an exemplary clock signal for real time aperture control, according to an embodiment of the invention; 
     FIG. 64C illustrates a timing diagram of an exemplary optional enable signal for real time aperture control, according to an embodiment of the invention; 
     FIG. 64D illustrates a timing diagram of an inverted clock signal for real time aperture control, according to an embodiment of the invention; 
     FIG. 64E illustrates a timing diagram of an exemplary delayed clock signal for real time aperture control, according to an embodiment of the invention; 
     FIG. 64F illustrates a timing diagram of an exemplary energy transfer including pulses having apertures that are controlled in real time, according to an embodiment of the invention; 
     FIG. 65 illustrates an exemplary embodiment of the invention; 
     FIG. 66 illustrates an exemplary embodiment of the invention; 
     FIG. 67 illustrates an exemplary embodiment of the invention; 
     FIG. 68 illustrates an exemplary embodiment of the invention; 
     FIG. 69A is a timing diagram for the exemplary embodiment of FIG. 65; 
     FIG. 69B is a timing diagram for the exemplary embodiment of FIG. 66; 
     FIG. 70A is a timing diagram for the exemplary embodiment of FIG. 67; 
     FIG. 70B is a timing diagram for the exemplary embodiment of FIG. 68; 
     FIG. 71A illustrates and exemplary embodiment of the invention; 
     FIG. 71B illustrates exemplary equations for determining charge transfer, in accordance with the present invention; 
     FIG. 71C illustrates relationships between capacitor charging and aperture, in accordance with an embodiment of the present invention; 
     FIG. 71D illustrates relationships between capacitor charging and aperture, in accordance with an embodiment of the present invention; 
     FIG. 71E illustrates power-charge relationship equations, in accordance with an embodiment of the present invention; 
     FIG. 71F illustrates insertion loss equations, in accordance with an embodiment of the present invention; and 
     FIG. 72 shows an original FSK waveform and a down-converted waveform. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Table of Contents 
     1. Universal Frequency Translation 
     2. Frequency Down-conversion 
     2.1 Optional Energy Transfer Signal Module 
     2.2 Smoothing the Down-converted Signal 
     2.3 Impedance Matching 
     2.4 Tanks and Resonant Structures 
     2.5 Charge and Power Transfer Concepts 
     2.6 Optimizing and Adjusting the Non-negligible Aperture Width/Duration 
     2.6.1 Varying Input and Output Impedances 
     2.6.2 Real Time Aperture Control 
     2.7 Adding a Bypass Network 
     2.8 Modifying the Energy Transfer Signal Using Feedback 
     2.9 Other Implementations 
     2.10 Exemplary Energy Transfer Down-converters 
     3. Frequency Up-conversion 
     4. Enhanced Signal Reception 
     5. Unified Down-Conversion and Filtering 
     6. Exemplary Application Embodiments of the Invention 
     7. Specific Implementation Application 
     7.1 System of Operation 
     7.2 Method of Operation 
     8. Other Exemplary Applications 
     9. Conclusions 
     1. Universal Frequency Translation 
     The present invention is related to frequency translation, and applications of same. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same. 
     FIG. 1A illustrates a universal frequency translation (UFT) module  102  according to embodiments of the invention. (The UFT module is also sometimes called a universal frequency translator, or a universal translator.) 
     As indicated by the example of FIG. 1A, some embodiments of UFT module  102  include three ports (nodes), designated in FIG. 1A as Port  1 , Port  2 , and Port  3 . Other UFT embodiments include other than three ports. 
     Generally, UFT module  102  (perhaps in combination with other components) operates to generate an output signal from an input signal, where the frequency of the output signal differs from the frequency of the input signal. In other words, UFT module  102  (and perhaps other components) operates to generate the output signal from the input signal by translating the frequency (and perhaps other characteristics) of the input signal to the frequency (and perhaps other characteristics) of the output signal. 
     An exemplary embodiment of UFT module  103  is generally illustrated in FIG.  1 B. Generally, UFT module  103  includes a switch  106  controlled by a control signal  108 . Switch  106  is said to be a controlled switch. 
     As noted above, some UFT embodiments include other than three ports. For example, and without limitation, FIG. 2 illustrates an exemplary UFT module  202 . Exemplary UFT module  202  includes a diode  204  having two ports, designated as Port  1  and Port  2 / 3 . This embodiment does not include a third port, as indicated by the dotted line around the “Port  3 ” label. 
     The UFT module is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications. 
     For example, a UFT module  115  can be used in a universal frequency down-conversion (UFD) module  114 , an example of which is shown in FIG.  1 C. In this capacity, UFT module  115  frequency down-converts an input signal to an output signal. 
     As another example, as shown in FIG. 1D, a UFT module  117  can be used in a universal frequency up-conversion (UFU) module  116 . In this capacity, UFT module  117  frequency up-converts an input signal to an output signal. 
     These and other applications of the UFT module are described below. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. In some applications, the UFT module is a required component. In other applications, the UFT module is an optional component. 
     2. Frequency Down-conversion 
     The present invention is directed to systems and methods of universal frequency down-conversion, and applications of same. 
     In particular, the following discussion describes down-converting using a Universal Frequency Translation Module. The down-conversion of an EM signal by aliasing the EM signal at an aliasing rate is fully described in U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference. A relevant portion of the above mentioned patent application is summarized below to describe down-converting an input signal to produce a down-converted signal that exists at a lower frequency or a baseband signal. 
     FIG. 20A illustrates an aliasing module  2000  for down-conversion using a universal frequency translation (UFT) module  2002  which down-converts an EM input signal  2004 . In particular embodiments, aliasing module  2000  includes a switch  2008  and a capacitor  2010 . The electronic alignment of the circuit components is flexible. That is, in one implementation, switch  2008  is in series with input signal  2004  and capacitor  2010  is shunted to ground (although it may be other than ground in configurations such as differential mode). In a second implementation (see FIG.  20 A- 1 ), capacitor  2010  is in series with input signal  2004  and switch  2008  is shunted to ground (although it may be other than ground in configurations such as differential mode). Aliasing module  2000  with UFT module  2002  can be easily tailored to down-convert a wide variety of electromagnetic signals using aliasing frequencies that are well below the frequencies of EM input signal  2004 . 
     In one implementation, aliasing module  2000  down-converts input signal  2004  to an intermediate frequency (IF) signal. In another implementation, aliasing module  2000  down-converts input signal  2004  to a demodulated baseband signal. In yet another implementation, input signal  2004  is a frequency modulated (FM) signal, and aliasing module  2000  down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal. Each of the above implementations is described below. 
     In an embodiment, control signal  2006  includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of input signal  2004 . In this embodiment, control signal  2006  is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of input signal  2004 . Preferably, the frequency of control signal  2006  is much less than input signal  2004 . 
     A train of pulses  2018  as shown in FIG. 20D controls switch  2008  to alias input signal  2004  with control signal  2006  to generate a down-converted output signal  2012 . More specifically, in an embodiment, switch  2008  closes on a first edge of each pulse  2020  of FIG.  20 D and opens on a second edge of each pulse. When switch  2008  is closed, input signal  2004  is coupled to capacitor  2010 , and charge is transferred from input signal  2004  to capacitor  2010 . The charge stored during successive pulses forms a down-converted output signal  2012 . 
     Exemplary waveforms are shown in FIGS. 20B-20F. 
     FIG. 20B illustrates an analog amplitude modulated (AM) carrier signal  2014  that is an example of input signal  2004 . For illustrative purposes, in FIG. 20C, an analog AM carrier signal portion  2016  illustrates a portion of analog AM carrier signal  2014  on an expanded time scale. Analog AM carrier signal portion  2016  illustrates analog AM carrier signal  2014  from time t 0  to time t 1 . 
     FIG. 20D illustrates an exemplary aliasing signal  2018  that is an example of control signal  2006 . Aliasing signal  2018  is on approximately the same time scale as analog AM carrier signal portion  2016 . In the example shown in FIG. 20D, aliasing signal  2018  includes a train of pulses  2020  having negligible apertures that tend towards zero (the invention is not limited to this embodiment, as discussed below). The pulse aperture may also be referred to as the pulse width as will be understood by those skilled in the art(s). Pulses  2020  repeat at an aliasing rate, or pulse repetition rate of aliasing signal  2018 . The aliasing rate is determined as described below, and further described in U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” application Ser. No. 09/176,022, Filed Oct. 21, 1998, and is incorporated herein by reference in its entirety. 
     As noted above, train of pulses  2020  (i.e., control signal  2006 ) control switch  2008  to alias analog AM carrier signal  2016  (i.e., input signal  2004 ) at the aliasing rate of aliasing signal  2018 . Specifically, in this embodiment, switch  2008  closes on a first edge of each pulse and opens on a second edge of each pulse. When switch  2008  is closed, input signal  2004  is coupled to capacitor  2010 , and charge is transferred from input signal  2004  to capacitor  2010 . The charge transferred during a pulse is referred to herein as an under-sample. Exemplary under-samples  2022  form down-converted signal portion  2024  (FIG. 20E) that corresponds to analog AM carrier signal portion  2016  (FIG. 20C) and train of pulses  2020  (FIG.  20 D). The charge stored during successive under-samples of AM carrier signal  2014  form down-converted signal  2024  (FIG. 20E) that is an example of down-converted output signal  2012  (FIG.  20 A). In FIG. 20F, a demodulated baseband signal  2026  represents demodulated baseband signal  2024  after filtering on a compressed time scale. As illustrated, down-converted signal  2026  has substantially the same “amplitude envelope” as AM carrier signal  2014 . Therefore, FIGS. 20B-20F illustrate down-conversion of AM carrier signal  2014 . 
     The waveforms shown in FIGS. 20B-20F are discussed herein for illustrative purposes only, and are not limiting. Additional exemplary time domain and frequency domain drawings, and exemplary methods and systems of the invention relating thereto, are disclosed in U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” application Ser. No. 09/176,022, Filed Oct. 21, 1998, and is incorporated herein by reference in its entirety. 
     The aliasing rate of control signal  2006  determines whether input signal  2004  is down-converted to an IF signal, down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or an AM signal. Generally, relationships between input signal  2004 , the aliasing rate of control signal  2006 , and down-converted output signal  2012  are illustrated below: 
     
       
         (Freq. of input signal 2004)= n· (Freq. of control signal 2006)±(Freq. of down-converted output signal 2012) 
       
     
     For the examples contained herein, only the “+” condition will be discussed. The value of n represents a harmonic or sub-harmonic of input signal  2004  (e.g., n=0.5, 1, 2, 3, . . . ). 
     When the aliasing rate of control signal  2006  is off-set from the frequency of input signal  2004 , or off-set from a harmonic or sub-harmonic thereof, input signal  2004  is down-converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of input signal  2004 . As a result, the under-samples form a lower frequency oscillating pattern. If input signal  2004  includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal. For example, to down-convert a 901 MHz input signal to a 1 MHz IF signal, the frequency of control signal  2006  would be calculated as follows:                  (       Freq   input     -     Freq   IF       )     /   n     =     Freq   control                     (       901                 MHz     -     1                 MHz       )     /   n     =     900   /   n                                  
     For n=0.5, 1, 2, 3, 4, etc., the frequency of control signal  2006  would be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc. 
     Exemplary time domain and frequency domain drawings, illustrating down-conversion of analog and digital AM, PM and FM signals to IF signals, and exemplary methods and systems thereof, are disclosed in U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” U.S. patent application Ser. No. 09/176,022, Filed Oct. 21, 1998, and is incorporated herein by reference in its entirety. 
     Alternatively, when the aliasing rate of control signal  2006  is substantially equal to the frequency of input signal  2004 , or substantially equal to a harmonic or sub-harmonic thereof, input signal  2004  is directly down-converted to a demodulated baseband signal. This is because, without modulation, the under-sampling pulses occur at the same point of subsequent cycles of input signal  2004 . As a result, the under-samples form a constant output baseband signal. If input signal  2004  includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal. For example, to directly down-convert a 900 MHz input signal to a demodulated baseband signal (i.e., zero IF), the frequency of control signal  2006  would be calculated as follows:                  (       Freq   input     -     Freq   IF       )     /   n     =     Freq   control                     (       900                 MHz     -     0                 MHz       )     /   n     =     900                   MHz   /   n                                    
     For n=0.5, 1, 2, 3, 4, etc., the frequency of control signal  2006  should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc. 
     Exemplary time domain and frequency domain drawings, illustrating direct down-conversion of analog and digital AM and PM signals to demodulated baseband signals, and exemplary methods and systems thereof, are disclosed in the U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” U.S. patent application Ser. No. 09/176,022, Filed Oct. 21, 1998, and is incorporated herein by reference in its entirety. 
     Alternatively, to down-convert an input FM signal to a non-FM signal, a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF). As an example, to down-convert a frequency shift keying (FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (a subset of PM), the mid-point between a lower frequency F 1  and an upper frequency F 2  (that is, [(F 1 +F 2 )+2]) of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F 1  equal to 899 MHz and F 2  equal to 901 MHz, to a PSK signal, the aliasing rate of control signal  2006  would be calculated as follows:                Frequency                 of                 the                 input     =       (       F   1     +     F   2       )     ÷   2                 =       (       899                 MHz     +     901                 MHz       )     ÷   2                 =     900                 MHz                                  
     Frequency of the down-converted signal=0 (i.e., baseband)                  (       Freq   input     -     Freq   IF       )     /   n     =     Freq   control                     (       900                 MHz     -     0                 MHz       )     /   n     =     900                   MHz   /   n                                    
     For n=0.5, 1, 2, 3, etc., the frequency of control signal  2006  should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc. The frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F 1  and the upper frequency F 2 . 
     As another example, to down-convert a FSK signal to an amplitude shift keying (ASK) signal (a subset of AM), either the lower frequency F 1  or the upper frequency F 2  of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F 1  equal to 900 MHz and F 2  equal to 901 MHz, to an ASK signal, the aliasing rate of control signal  2006  should be substantially equal to: 
     
       
         
           
             
               
                 
                   
                     
                       
                         ( 
                         
                           
                             900 
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     For the former case of 900 MHz/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of control signal  2006  should be substantially equal to 1.8 GHz, 900 MHz, 450 MHz, 300 MHz, 225 MHz, etc. For the latter case of 901 MHz/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of control signal  2006  should be substantially equal to 1.802 GHz, 901 MHz, 450.5 MHz, 300.333 MHz, 225.25 MHz, etc. The frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F 1  and the upper frequency F 2  (i.e., 1 MHz). 
     Exemplary time domain and frequency domain drawings, illustrating down-conversion of FM signals to non-FM signals, and exemplary methods and systems thereof, are disclosed in the U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” U.S. patent application Ser. No. 09/176,022, Filed Oct. 21, 1998, and is incorporated herein by reference in its entirety. 
     In an embodiment, the pulses of control signal  2006  have negligible apertures that tend towards zero. This makes UFT module  2002  a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired. 
     In another embodiment, the pulses of control signal  2006  have non-negligible apertures that tend away from zero. This makes UFT module  2002  a lower input impedance device. This allows the lower input impedance of UFT module  2002  to be substantially matched with a source impedance of input signal  2004 . This also improves the energy transfer from input signal  2004  to down-converted output signal  2012 , and hence the efficiency and signal to noise (s/n) ratio of UFT module  2002 . In this embodiment, control signal  2006  has an aliasing frequency selected as described above, an aliasing period, “T,” that is the inverse of the aliasing frequency, and each of the non-negligible apertures of the pulses of control signal  2006  are said to have an aliasing pulse width, “PW A .” The output of UFT module  2002  is stored in capacitor  2010 . 
     In order to effectively transfer energy from input signal  2004  to down-converted output signal  2012 , the size of capacitor  2010  is selected based on the ratio of “PW A ” to “T” and must be matched with the other circuit elements. Preferably, the capacitor will be “large,” as will be understood by one skilled in the relevant art(s). When the size of the capacitor is properly selected for the open-switch and closed-switch impedances and for a specific “PW A ” to “T” ratio, the capacitor will charge quickly when switch  2008  of UFT  2002  is closed, and will discharge slowly when switch  2008  is open. The difference in the charging and discharging rates is due to the switching of impedances in and out of the circuit. That is, when switch  2008  is closed, the closed-switch impedance can be said to be R C , and when switch  2008  is open, the open-switch impedance can be said to be R O . 
     The voltage on capacitor  2010  during charging (i.e., when switch  2008  is closed) can be represented by the equation (assuming there is no charge on the capacitor at t=0) 
     
       
           V   cap/charging   =V   input ·(1− e   −[t/(Rc·C)] ) 
       
     
     and the voltage on capacitor  2010  during discharge (i.e., when switch  2008  is open) can be seen by the equation (assuming the capacitor is fully charged at t=0) 
     
       
         
           V 
           cap/discharging 
           =V 
           full 
           ·e 
           −[t/(Ro·C)] 
         
       
     
     It should be noted that for the capacitor to charge quickly and discharge slowly, the discharging time constant, R O ·C, must be greater than the charging time constant, R C ·C. 
     Capacitor  2010  can be characterized as having a first charged state corresponding to the charge on capacitor  2010  at the end of each pulse of control signal  2006  (i.e., at the end of the charging cycle); a second charged state corresponding to the charge on capacitor  2010  at the beginning of the next pulse in control signal  2006  (i.e., at the end of the discharge cycle); and a discharge rate which is the rate at which the first charged state changes to the second charged state and is a function of the size of capacitor  2010 . The ratio of the second charged state to the first charged state is the charged ratio, and to effect large energy transfer, the capacitance should be chosen so that the charged ratio is substantially equal to or greater than 0.10. In an alternate embodiment, the capacitor fully discharges while switch  2008  is closed. The discussion herein is provided for illustrative purposes only, and is not meant to be limiting. In another embodiment, the capacitor is replaced by another storage device, such as, and without limitation, an inductor. 
     Exemplary systems and methods for generating and optimizing control signal  2006 , and for otherwise improving energy transfer and s/n ratio, are disclosed in the U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” U.S. patent application Ser. No. 09/176,022, Filed Oct. 21, 1998, and is incorporated herein by reference in its entirety. 
     2.1. Optional Energy Transfer Signal Module 
     FIG. 47 illustrates an energy transfer system  4701  that includes an optional energy transfer signal module  4702 , which can perform any of a variety of functions or combinations of functions including, but not limited to, generating an energy transfer signal  4106 . 
     In an embodiment, optional energy transfer signal module  4702  includes an aperture generator, an example of which is illustrated in FIG. 44 as an aperture generator  4420 . Aperture generator  4420  generates non-negligible aperture pulses  4326  from an input signal  4324 . Input signal  4324  can be any type of periodic signal, including, but not limited to, a sinusoid, a square wave, a saw-tooth wave, etc. Systems for generating input signal  4324  are described below. 
     The width or aperture of pulses  4326  is determined by delay through branch  4322  of aperture generator  4420 . Generally, as the desired pulse width increases, the difficulty in meeting the requirements of aperture generator  4420  decrease. In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components used in exemplary aperture generator  4420  do not require as fast reaction times as those that are required in an under-sampling system operating with the same EM input frequency. 
     The exemplary logic and implementation shown in aperture generator  4420  are provided for illustrative purposes only, and are not limiting. The actual logic employed can take many forms. Exemplary aperture generator  4420  includes an optional inverter  4428 , which is shown for polarity consistency with other examples provided herein. 
     An exemplary implementation of aperture generator  4420  is illustrated in FIG.  45 . Additional examples of aperture generation logic are provided in FIGS. 43A and 43B. FIG. 43A illustrates a rising edge pulse generator  4340 , which generates pulses  4326  on rising edges of input signal  4324 . FIG. 43B illustrates a falling edge pulse generator  4350 , which generates pulses  4326  on falling edges of input signal  4324 . 
     In an embodiment, input signal  4324  is generated externally of energy transfer signal module  4702 , as illustrated in FIG.  47 . Alternatively, input signal  4724  is generated internally by energy transfer signal module  4702 . Input signal  4324  can be generated by an oscillator, as illustrated in FIG. 46 by an oscillator  4630 . Oscillator  4630  can be internal to the energy transfer signal module  4702  or external to the energy transfer signal module  4702 . Oscillator  4630  can be external to energy transfer system  4701 . The output of oscillator  4630  may be any periodic waveform. 
     The type of down-conversion performed by energy transfer system  4701  depends upon the aliasing rate of energy transfer signal  4106 , which is determined by the frequency of pulses  4326 . The frequency of pulses  4326  is determined by the frequency of input signal  4324 . 
     For example, when the frequency of input signal  4324  is substantially equal to a harmonic or a sub-harmonic of EM signal  3904 , EM signal  3904  is directly down-converted to baseband (e.g. when the EM signal is an AM signal or a PM signal), or converted from FM to a non-FM signal. When the frequency of input signal  4324  is substantially equal to a harmonic or a sub-harmonic of a difference frequency, EM signal  3904  is down-converted to an intermediate signal. 
     The optional energy transfer signal module  4702  can be implemented in hardware, software, firmware, or any combination thereof. 
     2.2 Smoothing the Down-Converted Signal 
     Referring back to FIG. 20A, down-converted output signal  2012  may be smoothed by filtering as desired. 
     2.3 Impedance Matching 
     Energy transfer module  2000  has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., UFT  2002 ), and (2) the impedance of the storage module (e.g., capacitor  2010 ), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies). 
     Starting with an aperture width of approximately ½the period of the EM signal being down-converted as a preferred embodiment, this aperture width (e.g. the “closed time”) can be decreased. As the aperture width is decreased, the characteristic impedance at the input and the output of the energy transfer module increases. Alternatively, as the aperture width increases from ½ the period of the EM signal being down-converted, the impedance of the energy transfer module decreases. 
     One of the steps in determining the characteristic input impedance of the energy transfer module could be to measure its value. In an embodiment, the energy transfer module&#39;s characteristic input impedance is 300 ohms. An impedance matching circuit can be used to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module&#39;s impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below. 
     Referring to FIG. 48, a specific embodiment using an RF signal as an input, assuming that impedance  4812  is a relatively low impedance of approximately 50 Ohms, for example, and input impedance  4816  is approximately 300 Ohms, an initial configuration for input impedance match module  4806  can include an inductor  5006  and a capacitor  5008 , configured as shown in FIG.  50 . The configuration of inductor  5006  and capacitor  5008  is a possible configuration when going from a low impedance to a high impedance. Inductor  5006  and capacitor  5008  constitute an L match, the calculation of the values which is well known to those skilled in the relevant arts. 
     The output characteristic impedance can be impedance matched to take into consideration the desired output frequencies. One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1 MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms). An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components. 
     In an embodiment, the energy transfer module&#39;s characteristic output impedance is 2K ohms. An impedance matching circuit can be used to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below. 
     When matching from a high impedance to a low impedance, a capacitor  5014  and an inductor  5016  can be configured as shown in FIG.  50 . Capacitor  5014  and inductor  5016  constitute an L match, the calculation of the component values being well known to those skilled in the relevant arts. 
     The configuration of input impedance match module  4806  and the output impedance match module  4808  are considered to be initial starting points for impedance matching, in accordance with the present invention. In some situations, the initial designs may be suitable without further optimization. In other situations, the initial designs can be optimized in accordance with other various design criteria and considerations. 
     As other optional optimizing structures and/or components are used, their affect on the characteristic impedance of the energy transfer module should be taken into account in the match along with their own original criteria. 
     2.4 Tanks and Resonant Structures 
     Resonant tank and other resonant structures can be used to further optimize the energy transfer characteristics of the invention. For example, resonant structures, resonant about the input frequency, can be used to store energy from the input signal when the switch is open, a period during which one may conclude that the architecture would otherwise be limited in its maximum possible efficiency. Resonant tank and other resonant structures can include, but are not limited to, surface acoustic wave (SAW) filters, dielectric resonators, diplexers, capacitors, inductors, etc. 
     An exemplary embodiment is shown in FIG.  60 A. Two additional embodiments are shown in FIG.  55  and FIG.  63 . Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention. These implementations take advantage of properties of series and parallel (tank) resonant circuits. 
     FIG. 60A illustrates parallel tank circuits in a differential implementation. A first parallel resonant or tank circuit consists of a capacitor  6038  and an inductor  6020  (tank 1 ). A second tank circuit consists of a capacitor  6034  and an inductor  6036  (tank 2 ). 
     As is apparent to one skilled in the relevant art(s), parallel tank circuits provide: 
     low impedance to frequencies below resonance; 
     low impedance to frequencies above resonance; and 
     high impedance to frequencies at and near resonance. 
     In the illustrated example of FIG. 60A, the first and second tank circuits resonate at approximately 920 MHz. At and near resonance, the impedance of these circuits is relatively high. Therefore, in the circuit configuration shown in FIG. 60A, both tank circuits appear as relatively high impedance to the input frequency of 950 MHz, while simultaneously appearing as relatively low impedance to frequencies in the desired output range of 50 MHz. 
     An energy transfer signal  6042  controls a switch  6014 . When energy transfer signal  6042  controls switch  6014  to open and close, high frequency signal components are not allowed to pass through tank 1  or tank 2 . However, the lower signal components (50MHz in this embodiment) generated by the system are allowed to pass through tank 1  and tank 2  with little attenuation. The effect of tank 1  and tank 2  is to further separate the input and output signals from the same node thereby producing a more stable input and output impedance. Capacitors  6018  and  6040  act to store the 50 MHz output signal energy between energy transfer pulses. 
     Further energy transfer optimization is provided by placing an inductor  6010  in series with a storage capacitor  6012  as shown. In the illustrated example, the series resonant frequency of this circuit arrangement is approximately 1 GHz. This circuit increases the energy transfer characteristic of the system. The ratio of the impedance of inductor  6010  and the impedance of storage capacitor  6012  is preferably kept relatively small so that the majority of the energy available will be transferred to storage capacitor  6012  during operation. Exemplary output signals A and B are illustrated in FIGS. 60B and 60C, respectively. 
     In FIG. 60A, circuit components  6004  and  6006  form an input impedance match. Circuit components  6032  and  6030  form an output impedance match into a 50 ohm resistor  6028 . Circuit components  6022  and  6024  form a second output impedance match into a 50 ohm resistor  6026 . Capacitors  6008  and  6012  act as storage capacitors for the embodiment. Voltage source  6046  and resistor  6002  generate a 950 MHz signal with a 50 ohm output impedance, which are used as the input to the circuit. Circuit element  6016  includes a 150 MHz oscillator and a pulse generator, which are used to generate energy transfer signal  6042 . 
     FIG. 55 illustrates a shunt tank circuit  5510  in a single-ended to-single-ended system  5512 . Similarly, FIG. 63 illustrates a shunt tank circuit  6310  in a system  6312 . Tank circuits  5510  and  6310  lower driving source impedance, which improves transient response. Tank circuits  5510  and  6310  are able store the energy from the input signal and provide a low driving source impedance to transfer that energy throughout the aperture of the closed switch. The transient nature of the switch aperture can be viewed as having a response that, in addition to including the input frequency, has large component frequencies above the input frequency, (i.e. higher frequencies than the input frequency are also able to effectively pass through the aperture). Resonant circuits or structures, for example, resonant tanks  5510  or  6310 , can take advantage of this by being able to transfer energy throughout the switch&#39;s transient frequency response (i.e. the capacitor in the resonant tank appears as a low driving source impedance during the transient period of the aperture). 
     The exemplary tank and resonant structures described above are for illustrative purposes and are not limiting. Alternate configurations can be used. The various resonant tanks and structures discussed can be combined or used independently as is now apparent. 
     2.5 Charge and Power Transfer Concepts 
     Concepts of charge transfer are now described with reference to FIGS. 71A-F. FIG. 71A illustrates a circuit  7102 , including a switch S and a capacitor  7106  having a capacitance C. The switch S is controlled by a control signal  7108 , which includes pulses  7110  having apertures T. 
     In FIG. 71B, Equation  2  illustrates that the charge q on a capacitor having a capacitance C, such as capacitor  7106 , is proportional to the voltage V across the capacitor, where: 
     q=Charge in Coulombs 
     C=Capacitance in Farads 
     V=Voltage in Volts 
     A=Input Signal Amplitude 
     Where the voltage V is represented by Equation 3, Equation 2 can be rewritten as Equation 4. The change in charge Δq over time t is illustrated as in Equation 5 as Δq(t), which can be rewritten as Equation 6. Using the sum-to-product trigonometric identity of Equation 7, Equation 6 can be rewritten as Equation 8, which can be rewritten as Equation 9. 
     Note that the sin term in Equation 3 is a function of the aperture T only. Thus, Δq(t) is at a maximum when T is equal to an odd multiple of π(i.e., π, 3π, 5π, . . . ). Therefore, capacitor  7106  experiences the greatest change in charge when the aperture T has a value of π or a time interval representative of 180 degrees of the input sinusoid. Conversely, when T is equal to 2π, 4π, 6π, . . . , minimal charge is transferred. 
     Equations 10, 11, and 12 solve for q(t) by integrating Equation 2, allowing the charge on capacitor  7106  with respect to time to be graphed on the same axis as the input sinusoid sin(t), as illustrated in the graph of FIG. 71 C. As the aperture T decreases in value or tends toward an impulse, the phase between the charge on the capacitor C or q(t) and sin(t) tend toward zero. This is illustrated in the graph of FIG. 71D, which indicates that the maximum impulse charge transfer occurs near the input voltage maxima. As this graph indicates, considerably less charge is transferred as the value of T decreases. 
     Power/charge relationships are illustrated in Equations 13-18 of FIG. 71E, where it is shown that power is proportional to charge, and transferred charge is inversely proportional to insertion loss. 
     Concepts of insertion loss are illustrated in FIG.  71 F. Generally, the noise figure of a lossy passive device is numerically equal to the device insertion loss. Alternatively, the noise figure for any device cannot be less that its insertion loss. Insertion loss can be expressed by Equation 19 or 20. 
     From the above discussion, it is observed that as the aperture T increases, more charge is transferred from the input to capacitor  7106 , which increases power transfer from the input to the output. It has been observed that it is not necessary to accurately reproduce the input voltage at the output because relative modulated amplitude and phase information is retained in the transferred power. 
     2.6 Optimizing and Adjusting the Non-Negligible Aperture Width/Duration 
     2.6.1 Varying Input and Output Impedances 
     In an embodiment of the invention, the energy transfer signal (i.e., control signal  2006  in FIG.  20 A), is used to vary the input impedance seen by EM Signal  2004  and to vary the output impedance driving a load. An example of this embodiment is described below using a gated transfer module  5101  shown in FIG.  51 A. The method described below is not limited to the gated transfer module  5101 . 
     In FIG. 51A, when switch  5106  is closed, the impedance looking into circuit  5102  is substantially the impedance of a storage module, illustrated here as a storage capacitance  5108 , in parallel with the impedance of a load  5112 . When switch  5106  is open, the impedance at point  5114  approaches infinity. It follows that the average impedance at point  5114  can be varied from the impedance of the storage module illustrated in parallel with the load  5112 , to the highest obtainable impedance when switch  5106  is open, by varying the ratio of the time that switch  5106  is open to the time that switch  5106  is closed. Switch  5106  is controlled by an energy transfer signal  5110 . Thus the impedance at point  5114  can be varied by controlling the aperture width of the energy transfer signal in conjunction with the aliasing rate. 
     An exemplary method of altering energy transfer signal  5106  of FIG. 51A is now described with reference to FIG. 49A, where a circuit  4902  receives an input oscillating signal  4906  and outputs a pulse train shown as a doubler output signal  4904 . Circuit  4902  can be used to generate energy transfer signal  5106 . An example of waveforms of doubler output signal  4904  are shown on FIG.  49 C. 
     It can be shown that by varying the delay of the signal propagated by an inverter  4908 , the width of the pulses in doubler output signal  4904  can be varied. Increasing the delay of the signal propagated by inverter  4908 , increases the width of the pulses. The signal propagated by inverter  4908  can be delayed by introducing a R/C low pass network in the output of inverter  4908 . Other means of altering the delay of the signal propagated by inverter  4908  will be well known to those skilled in the art. 
     2.6.2 Real Time Aperture Control 
     In an embodiment, the aperture width/duration is adjusted in real time. For example, referring to the timing diagrams in FIGS. 64B-F, a clock signal  6414  (FIG. 64B) is used to generate an energy transfer signal  6416  (FIG.  64 F), which includes energy transfer pluses  6418 , having variable apertures  6420 . In an embodiment, the clock signal  6414  is inverted as illustrated by inverted clock signal  6422  (FIG.  64 D). The clock signal  6414  is also delayed, as illustrated by delayed clock signal  6424  (FIG.  64 E). The inverted clock signal  6414  and the delayed clock signal  6424  are then ANDed together, generating an energy transfer signal  6416 , which is active—energy transfer pulses  6418 —when delayed clock signal  6424  and inverted clock signal  6422  are both active. The amount of delay imparted to delayed clock signal  6424  substantially determines the width or duration of apertures  6420 . By varying the delay in real time, the apertures are adjusted in real time. 
     In an alternative implementation, inverted clock signal  6422  is delayed relative to original clock signal  6414 , and then ANDed with original clock signal  6414 . Alternatively, original clock signal  6414  is delayed then inverted, and the result ANDed with original clock signal  6414 . 
     FIG. 64A illustrates an exemplary real time aperture control system  6402  that can be used to adjust apertures in real time. The exemplary real time aperture control system  6402  includes an RC circuit  6404 , which includes a voltage variable capacitor  6412  and a resistor  6426 . The real time aperture control system  6402  also includes an inverter  6406  and an AND gate  6408 . The AND gate  6408  optionally includes an enable input  6410  for enabling/disabling the AND gate  6408  and RC circuit  6404 . The real time aperture control system  6402  optionally includes an amplifier  6428 . 
     Operation of the real time aperture control circuit is described with reference to the timing diagrams of FIGS. 64B-F. The real time control system  6402  receives input clock signal  6414 , which is provided to both inverter  6406  and to RC circuit  6404 . Inverter  6406  outputs inverted clock signal  6422  and presents it to AND gate  6408 . RC circuit  6404  delays clock signal  6414  and outputs delayed clock signal  6424 . The delay is determined primarily by the capacitance of voltage variable capacitor  6412 . Generally, as the capacitance decreases, the delay decreases. 
     Delayed clock signal  6424  is optionally amplified by optional amplifier  6428 , before being presented to AND gate  6408 . Amplification is desired, for example, where the RC constant of RC circuit  6404  attenuates the signal below the threshold of AND gate  6408 . 
     AND gate  6408  ANDs delayed clock signal  6424 , inverted clock signal  6422 , and optional Enable signal  6410 , to generate energy transfer signal  6416 . Apertures  6420  are adjusted in real time by varying the voltage to voltage variable capacitor  6412 . 
     In an embodiment, apertures  6420  are controlled to optimize power transfer. For example, in an embodiment, apertures  6420  are controlled to maximize power transfer. Alternatively, apertures  6420  are controlled for variable gain control (e.g. automatic gain control—AGC). In this embodiment, power transfer is reduced by reducing apertures  6420 . 
     As can now be readily seen from this disclosure, many of the aperture circuits presented, and others, can be modified as in circuits illustrated in FIGS. 46H-K. Modification or selection of the aperture can be done at the design level to remain a fixed value in the circuit, or in an alternative embodiment, may be dynamically adjusted to compensate for, or address, various design goals such as receiving RF signals with enhanced efficiency that are in distinctively different bands of operation, e.g. RF signals at 900 MHz and 1.8 GHz. 
     2.7 Adding a Bypass Network 
     In an embodiment of the invention, a bypass network is added to improve the efficiency of the energy transfer module. Such a bypass network can be viewed as a means of synthetic aperture widening. Components for a bypass network are selected so that the bypass network appears substantially lower impedance to transients of the switch module (i.e., frequencies greater than the received EM signal) and appears as a moderate to high impedance to the input EM signal (e.g., greater that 100 Ohms at the RF frequency). 
     The time that the input signal is now connected to the opposite side of the switch module is lengthened due to the shaping caused by this network, which in simple realizations may be a capacitor or series resonant inductor-capacitor. A network that is series resonant above the input frequency would be a typical implementation. This shaping improves the conversion efficiency of an input signal that would otherwise, if one considered the aperture of the energy transfer signal only, be relatively low in frequency to be optimal. 
     For example, referring to FIG. 61 a bypass network  6102  (shown in this instance as capacitor  6112 ), is shown bypassing switch module  6104 . In this embodiment the bypass network increases the efficiency of the energy transfer module when, for example, less than optimal aperture widths were chosen for a given input frequency on the energy transfer signal  6106 . Bypass network  6102  could be of different configurations than shown in FIG  61 . Such an alternate is illustrated in FIG.  57 . Similarly, FIG. 62 illustrates another exemplary bypass network  6202 , including a capacitor  6204 . 
     The following discussion will demonstrate the effects of a minimized aperture and the benefit provided by a bypassing network. Beginning with an initial circuit having a 550 ps aperture in FIG. 65, its output is seen to be 2.8 mVpp applied to a 50 ohm load in FIG.  69 A. Changing the aperture to 270 ps as shown in FIG. 66 results in a diminished output of 2.5 Vpp applied to a 50 ohm load as shown in FIG.  69 B. To compensate for this loss, a bypass network may be added, a specific implementation is provided in FIG.  67 . The result of this addition is that 3.2 Vpp can now be applied to the 50 ohm load as shown in FIG.  70 A. The circuit with the bypass network in FIG. 67 also had three values adjusted in the surrounding circuit to compensate for the impedance changes introduced by the bypass network and narrowed aperture. FIG. 68 verifies that those changes added to the circuit, but without the bypass network, did not themselves bring about the increased efficiency demonstrated by the embodiment in FIG. 67 with the bypass network. FIG. 70B shows the result of using the circuit in FIG. 68 in which only 1.88 Vpp was able to be applied to a 50 ohm load. 
     2.8 Modifying the Energy Transfer Signal Using Feedback 
     FIG. 47 shows an embodiment of a system  4701  which uses down-converted Signal  4708 B as feedback  4706  to control various characteristics of energy transfer module  4704  to modify down-converted signal  4708 B. 
     Generally, the amplitude of down-converted signal  4708 B varies as a function of the frequency and phase differences between EM signal  3904  and energy transfer signal  4106 . In an embodiment, down-converted signal  4708 B is used as feedback  4706  to control the frequency and phase relationship between EM signal  3904  and energy transfer signal  4106 . This can be accomplished using the exemplary logic in FIG.  52 A. The exemplary circuit in FIG. 52A can be included in energy transfer signal module  4702 . Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention. In this embodiment a state-machine is used as an example. 
     In the example of FIG. 52A, a state machine  5204  reads an analog to digital converter, A/D  5202 , and controls a digital to analog converter, DAC  5206 . In an embodiment, state machine  5204  includes 2 memory locations, Previous and Current, to store and recall the results of reading A/D  5202 . In an embodiment, state machine  5204  uses at least one memory flag. 
     DAC  5206  controls an input to a voltage controlled oscillator, VCO  5208 . VCO  5208  controls a frequency input of a pulse generator  5210 , which, in an embodiment, is substantially similar to the pulse generator shown in FIG.  44 . Pulse generator  5210  generates energy transfer signal  4106 . 
     In an embodiment, state machine  5204  operates in accordance with a state machine flowchart  5219  in FIG.  52 B. The result of this operation is to modify the frequency and phase relationship between energy transfer signal  4106  and EM signal  3904 , to substantially maintain the amplitude of down-converted signal  4708 B at an optimum level. 
     The amplitude of down-converted signal  4708 B can be made to vary with the amplitude of energy transfer signal  4106 . In an embodiment where switch module  6502  is a FET as shown in FIG. 38, wherein gate  3918  receives energy transfer signal  4106 , the amplitude of energy transfer signal  4106  can determine the “on” resistance of the FET, which affects the amplitude of down-converted signal  4708 B. Energy transfer signal module  4702 , as shown in FIG. 52C, can be an analog circuit that enables an automatic gain control function. Alternate implementations will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Alternate implementations fall within the scope and spirit of the present invention. 
     2.9 Other Implementations 
     The implementations described above are provided for purposes of illustration. These implementations are not intended to limit the invention. Alternate implementations, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate implementations fall within the scope and spirit of the present invention. 
     2.10 Exemplary Energy Transfer Down-Converters 
     Exemplary implementations are described below for illustrative purposes. The invention is not limited to these examples. 
     FIG. 53 is a schematic diagram of an exemplary circuit to down convert a 915 MHz signal to a 5 MHz signal using a 101.1 MHz clock. 
     FIG. 54 shows exemplary simulation waveforms for the circuit of figure  53 . Waveform  5302  is the input to the circuit showing the distortions caused by the switch closure. Waveform  5304  is the unfiltered output at the storage unit. Waveform  5306  is the impedance matched output of the down-converter on a different time scale. 
     FIG. 55 is a schematic diagram of an exemplary circuit to down-convert a 915 MHz signal to a 5 MHz signal using a 101.1 MHz clock. The circuit has additional tank circuitry to improve conversion efficiency. 
     FIG. 56 shows exemplary simulation waveforms for the circuit of figure  55 . Waveform  5502  is the input to the circuit showing the distortions caused by the switch closure. Waveform  5504  is the unfiltered output at the storage unit. Waveform  5506  is the output of the down-converter after the impedance match circuit. 
     FIG. 57 is a schematic diagram of an exemplary circuit to down-convert a 915 MHz signal to a 5 MHz signal using a 101.1 MHz clock. The circuit has switch bypass circuitry to improve conversion efficiency. 
     FIG. 58 shows exemplary simulation waveforms for the circuit of FIG.  57 . Waveform  5702  is the input to the circuit showing the distortions caused by the switch closure. Waveform  5704  is the unfiltered output at the storage unit. Waveform  5706  is the output of the down-converter after the impedance match circuit. 
     FIG. 59 shows a schematic of the exemplary circuit in FIG. 53 connected to an FSK source that alternates between 913 and 917 MHz, at a baud rate of 500 Kbaud. FIG. 72 shows the original FSK waveform  5902  and down-converted waveform  5904  at the output of the load impedance match circuit. 
     3. Frequency Up-Conversion 
     The present invention is directed to systems and methods of frequency up-conversion, and applications of same. 
     An exemplary frequency up-conversion system  300  is illustrated in FIG.  3 . Frequency up-conversion system  300  is now described. 
     An input signal  302  (designated as “Control Signal” in FIG. 3) is accepted by a switch module  304 . For purposes of example only, assume that input signal  302  is an FM input signal  606 , an example of which is shown in FIG.  6 C. FM input signal  606  may have been generated by modulating information signal  602  onto oscillating signal  604  (FIGS.  6 A and  6 B). It should be understood that the invention is not limited to this embodiment. Information signal  602  can be analog, digital, or any combination thereof, and any modulation scheme can be used. 
     The output of switch module  304  is a harmonically rich signal  306 , shown for example in FIG. 6D as a harmonically rich signal  608 . Harmonically rich signal  608  has a continuous and periodic waveform. 
     FIG. 6E is an expanded view of two sections of harmonically rich signal  608 , section  610  and section  612 . Harmonically rich signal  608  may be a rectangular wave, such as a square wave or a pulse (although, the invention is not limited to this embodiment). For ease of discussion, the term “rectangular waveform” is used to refer to waveforms that are substantially rectangular. In a similar manner, the term “square wave” refers to those waveforms that are substantially square and it is not the intent of the present invention that a perfect square wave be generated or needed. 
     Harmonically rich signal  608  is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of harmonically rich signal  608 . These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is referred to as the first harmonic. FIG.  6 F and FIG. 6G show separately the sinusoidal components making up the first, third, and fifth harmonics of section  610  and section  612 . (Note that in theory there may be an infinite number of harmonics; in this example, because harmonically rich signal  608  is shown as a square wave, there are only odd harmonics). Three harmonics are shown simultaneously (but not summed) in FIG.  6 H. 
     The relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal  306  and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal  306 . According to an embodiment of the invention, input signal  606  may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission). 
     A filter  308  filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal  310 , shown for example as a filtered output signal  614  in FIG.  6 I. 
     FIG. 4 illustrates an exemplary universal frequency up-conversion (UFU) module  401 . UFU module  401  includes an exemplary switch module  304 , which comprises a bias signal  402 , a resistor (or impedance)  404 , a universal frequency translator (UFT)  450 , and a ground  408 . UFT  450  includes a switch  406 . Input signal  302  (designated as “Control Signal” in FIG. 4) controls switch  406  in UFT  450 , and causes it to close and open. Harmonically rich signal  306  is generated at a node  405  located between resistor (or impedance)  404  and switch  406 . 
     Also in FIG. 4, it can be seen that an exemplary filter  308  is comprised of a capacitor  410  and an inductor  412  shunted to a ground  414 . The filter is designed to filter out the undesired harmonics of harmonically rich signal  306 . 
     The invention is not limited to the UFU embodiment shown in FIG.  4 . 
     For example, in an alternate embodiment shown in FIG. 5, an unshaped input signal  501  is routed to a pulse shaping module  502 . Pulse shaping module  502  modifies unshaped input signal  501  to generate a (modified) input signal  302  (designated as the “Control Signal” in FIG.  5 ). Input signal  302  is routed to switch module  304 , which operates in the manner described above. Also, filter  308  of FIG. 5 operates in the manner described above. 
     The purpose of pulse shaping module  502  is to define the pulse width of input signal  302 . Recall that input signal  302  controls the opening and closing of switch  406  in switch module  304 . During such operation, the pulse width of input signal  302  establishes the pulse width of harmonically rich signal  306 . As stated above, the relative amplitudes of the harmonics of harmonically rich signal  306  are a function of at least the pulse width of harmonically rich signal  306 . As such, the pulse width of input signal  302  contributes to setting the relative amplitudes of the harmonics of harmonically rich signal  306 . 
     Further details of up-conversion as described in this section are presented in U.S. application “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998, incorporated herein by reference in its entirety. 
     4. Enhanced Signal Reception 
     The present invention is directed to systems and methods of enhanced signal reception (ESR), and applications of same. 
     Referring to FIG. 21, transmitter  2104  accepts a modulating baseband signal  2102  and generates (transmitted) redundant spectra  2106   a-n,  which are sent over a communications medium  2108 . Receiver  2112  recovers a demodulated baseband signal  2114  from (received) redundant spectra  2110   a-n.  Demodulated baseband signal  2114  is representative of modulating baseband signal  2102 , where the level of similarity between modulating baseband signal  2114  and modulating baseband signal  2102  is application dependent. 
     Modulating baseband signal  2102  is preferably any information signal desired for transmission and/or reception. An exemplary modulating baseband signal  2202  is illustrated in FIG. 22A, and has an associated modulating baseband spectrum  2204  and image spectrum  2203  that are illustrated in FIG.  22 B. Modulating baseband signal  2202  is illustrated as an analog signal in FIG. 22 a,  but could also be a digital signal, or combination thereof. Modulating baseband signal  2202  could be a voltage (or current) characterization of any number of real world occurrences, including for example and without limitation, the voltage (or current) representation for a voice signal. 
     Each transmitted redundant spectrum  2106   a-n  contains the necessary information to substantially reconstruct modulating baseband signal  2102 . In other words, each redundant spectrum  2106   a-n  contains the necessary amplitude, phase, and frequency information to reconstruct modulating baseband signal  2102 . 
     FIG. 22C illustrates exemplary transmitted redundant spectra  2206   b-d.  Transmitted redundant spectra  2206   b-d  are illustrated to contain three redundant spectra for illustration purposes only. Any number of redundant spectra could be generated and transmitted as will be explained in following discussions. 
     Transmitted redundant spectra  2206   b-d  are centered at f 1 , with a frequency spacing f 2  between adjacent spectra. Frequencies f 1  and f 2  are dynamically adjustable in real-time as will be shown below. FIG. 22D illustrates an alternate embodiment, where redundant spectra  2208   c,d  are centered on unmodulated oscillating signal  2209  at f 1 (Hz). Oscillating signal  2209  may be suppressed if desired using, for example, phasing techniques or filtering techniques. Transmitted redundant spectra are preferably above baseband frequencies as is represented by break  2205  in the frequency axis of FIGS. 22C and 22D. 
     Received redundant spectra  2110   a-n  are substantially similar to transmitted redundant spectra  2106   a-n,  except for the changes introduced by communications medium  2108 . Such changes can include but are not limited to signal attenuation, and signal interference. FIG. 22E illustrates exemplary received redundant spectra  2210   b-d.  Received redundant spectra  2210   b-d  are substantially similar to transmitted redundant spectra  2206   b-d,  except that redundant spectrum  2210   c  includes an undesired jamming signal spectrum  2211  in order to illustrate some advantages of the present invention. Jamming signal spectrum  2211  is a frequency spectrum associated with a jamming signal. For purposes of this invention, a “jamming signal” refers to any unwanted signal, regardless of origin, that may interfere with the proper reception and reconstruction of an intended signal. Furthermore, the jamming signal is not limited to tones as depicted by spectrum  2211 , and can have any spectral shape, as will be understood by those skilled in the art(s). 
     As stated above, demodulated baseband signal  2114  is extracted from one or more of received redundant spectra  2210   b-d.  FIG. 22F illustrates exemplary demodulated baseband signal  2212  that is, in this example, substantially similar to modulating baseband signal  2202  (FIG.  22 A); where in practice, the degree of similarity is application dependent. 
     An advantage of the present invention should now be apparent. The recovery of modulating baseband signal  2202  can be accomplished by receiver  2112  in spite of the fact that high strength jamming signal(s) (e.g. jamming signal spectrum  2211 ) exist on the communications medium. The intended baseband signal can be recovered because multiple redundant spectra are transmitted, where each redundant spectrum carries the necessary information to reconstruct the baseband signal. At the destination, the redundant spectra are isolated from each other so that the baseband signal can be recovered even if one or more of the redundant spectra are corrupted by a jamming signal. 
     Transmitter  2104  will now be explored in greater detail. FIG. 23A illustrates transmitter  2301 , which is one embodiment of transmitter  2104  that generates redundant spectra configured similar to redundant spectra  2206   b-d.  Transmitter  2301  includes generator  2303 , optional spectrum processing module  2304 , and optional medium interface module  2320 . Generator  2303  includes: first oscillator  2302 , second oscillator  2309 , first stage modulator  2306 , and second stage modulator  2310 . 
     Transmitter  2301  operates as follows. First oscillator  2302  and second oscillator  2309  generate a first oscillating signal  2305  and second oscillating signal  2312 , respectively. First stage modulator  2306  modulates first oscillating signal  2305  with modulating baseband signal  2202 , resulting in modulated signal  2308 . First stage modulator  2306  may implement any type of modulation including but not limited to: amplitude modulation, frequency modulation, phase modulation, combinations thereof, or any other type of modulation. Second stage modulator  2310  modulates modulated signal  2308  with second oscillating signal  2312 , resulting in multiple redundant spectra  2206   a-n  shown in FIG.  23 B. Second stage modulator  2310  is preferably a phase modulator, or a frequency modulator, although other types of modulation may be implemented including but not limited to amplitude modulation. Each redundant spectrum  2206   a-n  contains the necessary amplitude, phase, and frequency information to substantially reconstruct modulating baseband signal  2202 . 
     Redundant spectra  2206   a-n  are substantially centered around f 1 , which is the characteristic frequency of first oscillating signal  2305 . Also, each redundant spectrum  2206   a-n  (except for  2206   c ) is offset from f 1  by approximately a multiple of f 2  (Hz), where f 2  is the frequency of second oscillating signal  2312 . Thus, each redundant spectrum  2206   a-n  is offset from an adjacent redundant spectrum by f 2  (Hz). This allows the spacing between adjacent redundant spectra to be adjusted (or tuned) by changing f 2  that is associated with second oscillator  2309 . Adjusting the spacing between adjacent redundant spectra allows for dynamic real-time tuning of the bandwidth occupied by redundant spectra  2206   a-n.    
     In one embodiment, the number of redundant spectra  2206   a-n  generated by transmitter  2301  is arbitrary and may be unlimited as indicated by the “a-n” designation for redundant spectra  2206   a-n.  However, a typical communications medium will have a physical and/or administrative limitations (i.e. FCC regulations) that restrict the number of redundant spectra that can be practically transmitted over the communications medium. Also, there may be other reasons to limit the number of redundant spectra transmitted. Therefore, preferably, transmitter  2301  will include an optional spectrum processing module  2304  to process redundant spectra  2206   a-n  prior to transmission over communications medium  2108 . 
     In one embodiment, spectrum processing module  2304  includes a filter with a passband  2207  (FIG. 23C) to select redundant spectra  2206   b-d  for transmission. This will substantially limit the frequency bandwidth occupied by the redundant spectra to passband  2207 . In one embodiment, spectrum processing module  2304  also up converts redundant spectra and/or amplifies redundant spectra prior to transmission over communications medium  2108 . Finally, medium interface module  2320  transmits redundant spectra over communications medium  2108 . In one embodiment, communications medium  2108  is an over-the-air link and medium interface module  2320  is an antenna. Other embodiments for communications medium  2108  and medium interface module  2320  will be understood based on the teachings contained herein. 
     FIG. 23D illustrates transmitter  2321 , which is one embodiment of transmitter  2104  that generates redundant spectra configured similar to redundant spectra  2208   c-d  and unmodulated spectrum  2209 . Transmitter  2321  includes generator  2311 , spectrum processing module  2304 , and (optional) medium interface module  2320 . Generator  2311  includes: first oscillator  2302 , second oscillator  2309 , first stage modulator  2306 , and second stage modulator  2310 . 
     As shown in FIG. 23D, many of the components in transmitter  2321  are similar to those in transmitter  2301 . However, in this embodiment, modulating baseband signal  2202  modulates second oscillating signal  2312 . Transmitter  2321  operates as follows. First stage modulator  2306  modulates second oscillating signal  2312  with modulating baseband signal  2202 , resulting in modulated signal  2322 . As described earlier, first stage modulator  2306  can effect any type of modulation including but not limited to: amplitude modulation frequency modulation, combinations thereof, or any other type of modulation. Second stage modulator  2310  modulates first oscillating signal  2304  with modulated signal  2322 , resulting in redundant spectra  2208   a-n , as shown in FIG.  23 E. Second stage modulator  2310  is preferably a phase or frequency modulator, although other modulators could used including but not limited to an amplitude modulator. 
     Redundant spectra  2208   a-n  are centered on unmodulated spectrum  2209  (at f 1  Hz), and adjacent spectra are separated by f 2  Hz. The number of redundant spectra  2208   a-n  generated by generator  2311  is arbitrary and unlimited, similar to spectra  2206   a-n  discussed above. Therefore, optional spectrum processing module  2304  may also include a filter with passband  2325  to select, for example, spectra  2208   c,d  for transmission over communications medium  2108 . In addition, optional spectrum processing module  2304  may also include a filter (such as a bandstop filter) to attenuate unmodulated spectrum  2209 . Alternatively, unmodulated spectrum  2209  maybe attenuated by using phasing techniques during redundant spectrum generation. Finally, (optional) medium interface module  2320  transmits redundant spectra  2208   c,d  over communications medium  2108 . 
     Receiver  2112  will now be explored in greater detail to illustrate recovery of a demodulated baseband signal from received redundant spectra. FIG. 24A illustrates receiver  2430 , which is one embodiment of receiver  2112 . Receiver  2430  includes optional medium interface module  2402 , down-converter  2404 , spectrum isolation module  2408 , and data extraction module  2414 . Spectrum isolation module  2408  includes filters  2410   a-c.  Data extraction module  2414  includes demodulators  2416   a-c,  error check modules  2420   a-c,  and arbitration module  2424 . Receiver  2430  will be discussed in relation to the signal diagrams in FIGS. 24B-24J. 
     In one embodiment, optional medium interface module  2402  receives redundant spectra  2210   b-d  (FIG. 22E, and FIG.  24 B). Each redundant spectrum  2210   b-d  includes the necessary amplitude, phase, and frequency information to substantially reconstruct the modulating baseband signal used to generated the redundant spectra. However, in the present example, spectrum  2210   c  also contains jamming signal  2211 , which may interfere with the recovery of a baseband signal from spectrum  2210   c.  Down-converter  2404  down-converts received redundant spectra  2210   b-d  to lower intermediate frequencies, resulting in redundant spectra  2406   a-c  (FIG.  24 C). Jamming signal  2211  is also down-converted to jamming signal  2407 , as it is contained within redundant spectrum  2406   b.  Spectrum isolation module  2408  includes filters  2410   a-c  that isolate redundant spectra  2406   a-c  from each other (FIGS. 24D-24F, respectively). Demodulators  2416   a-c  independently demodulate spectra  2406   a-c,  resulting in demodulated baseband signals  2418   a-c,  respectively (FIGS.  24 G- 24 I). Error check modules  2420   a-c  analyze demodulate baseband signal  2418   a-c  to detect any errors. In one embodiment, each error check module  2420   a-c  sets an error flag  2422   a-c  whenever an error is detected in a demodulated baseband signal. Arbitration module  2424  accepts the demodulated baseband signals and associated error flags, and selects a substantially error-free demodulated baseband signal (FIG.  24 J). In one embodiment, the substantially error-free demodulated baseband signal will be substantially similar to the modulating baseband signal used to generate the received redundant spectra, where the degree of similarity is application dependent. 
     Referring to FIGS. 24G-I, arbitration module  2424  will select either demodulated baseband signal  2418   a  or  2418   c,  because error check module  2420   b  will set error flag  2422   b  that is associated with demodulated baseband signal  2418   b.    
     The error detection schemes implemented by the error detection modules include but are not limited to: cyclic redundancy check (CRC) and parity check for digital signals, and various error detections schemes for analog signal. 
     Further details of enhanced signal reception as described in this section are presented in U.S. application “Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed Oct. 21, 1998, incorporated herein by reference in its entirety. 
     5. Unified Down-Conversion and Filtering 
     The present invention is directed to systems and methods of unified down-conversion and filtering (UDF), and applications of same. 
     In particular, the present invention includes a unified down-converting and filtering (UDF) module that performs frequency selectivity and frequency translation in a unified (i.e., integrated) manner. By operating in this manner, the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment). The invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies. 
     FIG. 17 is a conceptual block diagram of a UDF module  1702  according to an embodiment of the present invention. UDF module  1702  performs at least frequency translation and frequency selectivity. 
     The effect achieved by UDF module  1702  is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, UDF module  1702  effectively performs input filtering. 
     According to embodiments of the present invention, such input filtering involves a relatively narrow bandwidth. For example, such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values. 
     In embodiments of the invention, input signals  1704  received by UDF module  1702  are at radio frequencies. UDF module  1702  effectively operates to input filter these RF input signals  1704 . Specifically, in these embodiments, UDF module  1702  effectively performs input, channel select filtering of RF input signal  1704 . Accordingly, the invention achieves high selectivity at high frequencies. 
     UDF module  1702  effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof. 
     Conceptually, UDF module  1702  includes a frequency translator  1708 . Frequency translator  1708  conceptually represents that portion of UDF module  1702  that performs frequency translation (down conversion). 
     UDF module  1702  also conceptually includes an apparent input filter  1706  (also sometimes called an input filtering emulator). Conceptually, apparent input filter  1706  represents that portion of UDF module  1702  that performs input filtering. 
     In practice, the input filtering operation performed by UDF module  1702  is integrated with the frequency translation operation. The input filtering operation can be viewed as being performed concurrently with the frequency translation operation. This is a reason why input filter  1706  is herein referred to as an “apparent” input filter  1706 . 
     UDF module  1702  of the present invention includes a number of advantages. For example, high selectivity at high frequencies is realizable using UDF module  1702 . This feature of the invention is evident by the high Q factors that are attainable. For example, and without limitation, UDF module  1702  can be designed with a filter center frequency f C  on the order of 900 MHz, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000 (Q is equal to the center frequency divided by the bandwidth). 
     It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as discussed herein is not applicable. 
     The invention exhibits additional advantages. For example, the filtering center frequency f C  of UDF module  1702  can be electrically adjusted, either statically or dynamically. 
     Also, UDF module  1702  can be designed to amplify input signals. 
     Further, UDF module  1702  can be implemented without large resistors, capacitors, or inductors. Also, UDF module  1702  does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of UDF module  1702  is friendly to integrated circuit design techniques and processes. 
     The features and advantages exhibited by UDF module  1702  are achieved at least in part by adopting a new technological paradigm with respect to frequency selectivity and translation. Specifically, according to the present invention, UDF module  1702  performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa. 
     According to embodiments of the present invention, the UDF module generates an output signal from an input signal using samples/instances of the input signal and samples/instances of the output signal. 
     More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken. 
     As described further below, the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (IF) or baseband. 
     Next, the input sample is held (that is, delayed). 
     Then, one or more delayed input samples (some of which may have been scaled) are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal. 
     Thus, according to a preferred embodiment of the invention, the output signal is generated from prior samples/instances of the input signal and/or the output signal. (It is noted that, in some embodiments of the invention, current samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal.). By operating in this manner, the UDF module preferably performs input filtering and frequency down-conversion in a unified manner. 
     FIG. 19 illustrates an exemplary implementation of a unified down-converting and filtering (UDF) module  1922 . UDF module  1922  performs the frequency translation operation and the frequency selectivity operation in an integrated, unified manner as described above, and as further described below. 
     In the example of FIG. 19, the frequency selectivity operation performed by UDF module  1922  comprises a band-pass filtering operation according to EQ. 1, below, which is an exemplary representation of a band-pass filtering transfer function. 
     
       
           VO=α   1   z   −1   VI−β   1   z   −1   VO−β   0   z   −2   VO   EQ.1 
       
     
     It should be noted, however, that the invention is not limited to band-pass filtering. Instead, the invention effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof. As will be appreciated, there are many representations of any given filter type. The invention is applicable to these filter representations. Thus, EQ.1 is referred to herein for illustrative purposes only, and is not limiting. 
     UDF module  1922  includes a down-convert and delay module  1924 , first and second delay modules  1928  and  1930 , first and second scaling modules  1932  and  1934 , an output sample and hold module  1936 , and an (optional) output smoothing module  1938 . Other embodiments of the UDF module will have these components in different configurations, and/or a subset of these components, and/or additional components. For example, and without limitation, in the configuration shown in FIG. 19, output smoothing module  1938  is optional. 
     As further described below, in the example of FIG. 19, down-convert and delay module  1924  and first and second delay modules  1928  and  1930  include switches that are controlled by a clock having two phases, φ 1  and φ 2 . φ 1  and φ 2  preferably have the same frequency, and are non-overlapping (alternatively, a plurality such as two clock signals having these characteristics could be used). As used herein, the term “non-overlapping” is defined as two or more signals where only one of the signals is active at any given time. In some embodiments, signals are “active” when they are high. In other embodiments, signals are active when they are low. 
     Preferably, each of these switches closes on a rising edge of φ 1  or φ 2 , and opens on the next corresponding falling edge of φ 1  or φ 2 . However, the invention is not limited to this example. As will be apparent to persons skilled in the relevant art(s), other clock conventions can be used to control the switches. 
     In the example of FIG. 19, it is assumed that α 1  is equal to one. Thus, the output of down-convert and delay module  1924  is not scaled. As evident from the embodiments described above, however, the invention is not limited to this example. 
     Exemplary UDF module  1922  has a filter center frequency of 900.2 MHz and a filter bandwidth of 570 KHz. The pass band of the UDF module  1922  is on the order of 899.915 MHz to 900.485 MHz. The Q factor of UDF module  1922  is approximately  1879  (i.e., 900.2 MHz divided by 570 KHz). 
     The operation of UDF module  1922  shall now be described with reference to a Table  1802  (FIG. 18) that indicates exemplary values at nodes in UDF module  1922  at a number of consecutive time increments. It is assumed in Table  1802  that UDF module  1922  begins operating at time t−1. As indicated below, UDF module  1922  reaches steady state a few time units after operation begins. The number of time units necessary for a given UDF module to reach steady state depends on the configuration of the UDF module, and will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. 
     At the rising edge of φ 1  at time t−1, a switch  1950  in down-convert and delay module  1924  closes. This allows a capacitor  1952  to charge to the current value of an input signal, VI t−1 , such that node  1902  is at VI t−1 . This is indicated by cell  1804  in FIG.  18 . In effect, the combination of switch  1950  and capacitor  1952  in down-convert and delay module  1924  operates to translate the frequency of the input signal VI to a desired lower frequency, such as IF or baseband. Thus, the value stored in capacitor  1952  represents an instance of a down-converted image of the input signal VI. 
     The manner in which down-convert and delay module  1924  performs frequency down-conversion is further described elsewhere in this application, and is additionally described in U.S. application “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, which is herein incorporated by reference in its entirety. 
     Also at the rising edge of φ 1  at time t−1, a switch  1958  in first delay module  1928  closes, allowing a capacitor  1960  to charge to VO t−1 , such that node  1906  is at VO t−1 . This is indicated by cell  1806  in Table  1802 . (In practice, VO t−1  is undefined at this point. However, for ease of understanding, VO t−1  shall continue to be used for purposes of explanation.) 
     Also at the rising edge of φ 1  at time t−1, a switch  1966  in second delay module  1930  closes, allowing a capacitor  1968  to charge to a value stored in a capacitor  1964 . At this time, however, the value in capacitor  1964  is undefined, so the value in capacitor  1968  is undefined. This is indicated by cell  1807  in table  1802 . 
     At the rising edge of φ 2  at time t−1, a switch  1954  in down-convert and delay module  1924  closes, allowing a capacitor  1956  to charge to the level of capacitor  1952 . Accordingly, capacitor  1956  charges to VI t−1 , such that node  1904  is at VI t−1 . This is indicated by cell  1810  in Table  1802 . 
     UDF module  1922  may optionally include a unity gain module  1990 A between capacitors  1952  and  1956 . Unity gain module  1990 A operates as a current source to enable capacitor  1956  to charge without draining the charge from capacitor  1952 . For a similar reason, UDF module  1922  may include other unity gain modules  1990 B- 1990 G. It should be understood that, for many embodiments and applications of the invention, unity gain modules  1990 A- 1990 G are optional. The structure and operation of unity gain modules  1990  will be apparent to persons skilled in the relevant art(s). 
     Also at the rising edge of φ 2  at time t−1, a switch  1962  in first delay module  1928  closes, allowing a capacitor  1964  to charge to the level of capacitor  1960 . Accordingly, capacitor  1964  charges to VO t−1 , such that node  1908  is at VO t−1 . This is indicated by cell  1814  in Table  1802 . 
     Also at the rising edge of φ 2  at time t−1, a switch  1970  in second delay module  1930  closes, allowing a capacitor  1972  to charge to a value stored in a capacitor  1968 . At this time, however, the value in capacitor  1968  is undefined, so the value in capacitor  1972  is undefined. This is indicated by cell  1815  in table  1802 . 
     At time t, at the rising edge of φ 1 , switch  1950  in down-convert and delay module  1924  closes. This allows capacitor  1952  to charge to VI t , such that node  1902  is at VI t . This is indicated in cell  1816  of Table  1802 . 
     Also at the rising edge of φ 1  at time t, switch  1958  in first delay module  1928  closes, thereby allowing capacitor  1960  to charge to VO t . Accordingly, node  1906  is at VO t . This is indicated in cell  1820  in Table  1802 . 
     Further at the rising edge of φ 1  at time t, switch  1966  in second delay module  1930  closes, allowing a capacitor  1968  to charge to the level of capacitor  1964 . Therefore, capacitor  1968  charges to VO t−1 , such that node  1910  is at VO t−1 . This is indicated by cell  1824  in Table  1802 . 
     At the rising edge of φ 2  at time t, switch  1954  in down-convert and delay module  1924  closes, allowing capacitor  1956  to charge to the level of capacitor  1952 . Accordingly, capacitor  1956  charges to VI t , such that node  1904  is at VI t . This is indicated by cell  1828  in Table  1802 . 
     Also at the rising edge of φ 2  at time t, switch  1962  in first delay module  1928  closes, allowing capacitor  1964  to charge to the level in capacitor  1960 . Therefore, capacitor  1964  charges to VO t , such that node  1908  is at VO t . This is indicated by cell  1832  in Table  1802 . 
     Further at the rising edge of φ 2  at time t, switch  1970  in second delay module  1930  closes, allowing capacitor  1972  in second delay module  1930  to charge to the level of capacitor  1968  in second delay module  1930 . Therefore, capacitor  1972  charges to VO t−1 , such that node  1912  is at VO t−1 . This is indicated in cell  1836  of FIG.  18 . 
     At time t+1, at the rising edge of φ 1 , switch  1950  in down-convert and delay module  1924  closes, allowing capacitor  1952  to charge to VI t+1 . Therefore, node  1902  is at VI t+1 , as indicated by cell  1838  of Table  1802 . 
     Also at the rising edge of φ 1  at time t+1, switch  1958  in first delay module  1928  closes, allowing capacitor  1960  to charge to VO t+1 . Accordingly, node  1906  is at VO t+1 , as indicated by cell  1842  in Table  1802 . 
     Further at the rising edge of φ 1  at time t+1, switch  1966  in second delay module  1930  closes, allowing capacitor  1968  to charge to the level of capacitor  1964 . Accordingly, capacitor  1968  charges to VO t , as indicated by cell  1846  of Table  1802 . 
     In the example of FIG. 19, first scaling module  1932  scales the value at node  1908  (i.e., the output of first delay module  1928 ) by a scaling factor of −0. 1. Accordingly, the value present at node  1914  at time t+1 is −0.1*VO t . Similarly, second scaling module  1934  scales the value present at node  1912  (i.e., the output of second scaling module  1930 ) by a scaling factor of −0.8. Accordingly, the value present at node  1916  is −0.8*VO t−1  at time t+1. 
     At time t+1, the values at the inputs of summer  1926  are: VI t  at node  1904 , −0.1*VO t  at node  1914 , and −0.8*VO t−1  at node  1916  (in the example of FIG. 19, the values at nodes  1914  and  1916  are summed by a second summer  1925 , and this sum is presented to summer  1926 ). Accordingly, at time t+1, the summer generates a signal equal to VI t −0.1*VO t −0.8*VO t−1 . 
     At the rising edge of φ 1  at time t+1, a switch  1991  in the output sample and hold module  1936  closes, thereby allowing a capacitor  1992  to charge to VO t+1 . Accordingly, capacitor  1992  charges to VO t+1 , which is equal to the sum generated by summer  1926 . As just noted, this value is equal to: VI t −0.1*VO t −0.8*VO t−1 . This is indicated in cell  1850  of Table  1802 . This value is presented to optional output smoothing module  1938 , which smooths the signal to thereby generate the instance of the output signal VO t+1 . It is apparent from inspection that this value of VO t+1  is consistent with the band pass filter transfer function of EQ. 1. 
     Further details of unified down-conversion and filtering as described in this section are presented in U.S. application “Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998, incorporated herein by reference in its entirety. 
     6. Exemplary Application Embodiments of the Invention 
     As noted above, the UFT module of the present invention is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications. 
     Exemplary applications of the UFT module were described above. In particular, frequency down-conversion, frequency up-conversion, enhanced signal reception, and unified down-conversion and filtering applications of the UFT module were summarized above, and are further described below. These applications of the UFT module are discussed herein for illustrative purposes. The invention is not limited to these exemplary applications. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s), based on the teachings contained herein. 
     For example, the present invention can be used in applications that involve frequency down-conversion. This is shown in FIG. 1C, for example, where an exemplary UFT module  115  is used in a down-conversion module  114 . In this capacity, UFT module  115  frequency down-converts an input signal to an output signal. This is also shown in FIG. 7, for example, where an exemplary UFT module  706  is part of a down-conversion module  704 , which is part of a receiver  702 . 
     The present invention can be used in applications that involve frequency up-conversion. This is shown in FIG. 1D, for example, where an exemplary UFT module  117  is used in a frequency up-conversion module  116 . In this capacity, UFT module  117  frequency up-converts an input signal to an output signal. This is also shown in FIG. 8, for example, where an exemplary UFT module  806  is part of up-conversion module  804 , which is part of a transmitter  802 . 
     The present invention can be used in environments having one or more transmitters  902  and one or more receivers  906 , as illustrated in FIG.  9 . In such environments, one or more transmitters  902  may be implemented using a UFT module, as shown for example in FIG.  8 . Also, one or more receivers  906  may be implemented using a UFT module, as shown for example in FIG.  7 . 
     The invention can be used to implement a transceiver. An exemplary transceiver  1002  is illustrated in FIG.  10 . Transceiver  1002  includes a transmitter  1004  and a receiver  1008 . Either transmitter  1004  or receiver  1008  can be implemented using a UFT module. Alternatively, transmitter  1004  can be implemented using a UFT module  1006 , and receiver  1008  can be implemented using a UFT module  1010 . This embodiment is shown in FIG.  10 . 
     Another transceiver embodiment according to the invention is shown in FIG.  11 . In this transceiver  1102 , transmitter  1104  and receiver  1108  are implemented using a single UFT module  1106 . In other words, transmitter  1104  and receiver  1108  share a UFT module  1106 . 
     As described elsewhere in this application, the invention is directed to methods and systems for enhanced signal reception (ESR). Various ESR embodiments include an ESR module (transmit)  1204  in a transmitter  1202 , and an ESR module (receive)  1212  in a receiver  1210 . An exemplary ESR embodiment configured in this manner is illustrated in FIG.  12 . 
     ESR module (transmit)  1204  includes a frequency up-conversion module  1206 . Some embodiments of frequency up-conversion module  1206  may be implemented using a UFT module, such as that shown in FIG.  1 D. 
     ESR module (receive)  1212  includes a frequency down-conversion module  1214 . Some embodiments of frequency down-conversion module  1214  may be implemented using a UFT module, such as that shown in FIG.  1 C. 
     As described elsewhere in this application, the invention is directed to methods and systems for unified down-conversion and filtering (UDF). An exemplary unified down-conversion and filtering module  1302  is illustrated in FIG.  13 . Unified down-conversion and filtering module  1302  includes a frequency down-conversion module  1304  and a filtering module  1306 . According to the invention, frequency down-conversion module  1304  and filtering module  1306  are implemented using a UFT module  1308 , as indicated in FIG.  13 . 
     Unified down-conversion and filtering according to the invention is useful in applications involving filtering and/or frequency down-conversion. This is depicted, for example, in FIGS. 15A-15F. FIGS. 15A-15C indicate that unified down-conversion and filtering according to the invention is useful in applications where filtering precedes, follows, or both precedes and follows frequency down-conversion. FIG. 15D indicates that a unified down-conversion and filtering module  1524  according to the invention can be used as a filter  1522  (i.e., where the extent of frequency down-conversion by the down-converter in unified down-conversion and filtering module  1524  is minimized). FIG. 15E indicates that a unified down-conversion and filtering module  1528  according to the invention can be used as a down-converter  1526  (i.e., where the filter in unified down-conversion and filtering module  1528  passes substantially all frequencies). FIG. 15F illustrates that unified down-conversion and filtering module  1532  can be used as an amplifier. It is noted that one or more UDF modules can be used in applications that involve at least one or more of filtering, frequency translation, and amplification. 
     For example, receivers, which typically perform filtering, down-conversion, and filtering operations, can be implemented using one or more unified down-conversion and filtering modules. This is illustrated, for example, in FIG.  14 . 
     The methods and systems of unified down-conversion and filtering of the invention have many other applications. For example, as discussed herein, the enhanced signal reception (ESR) module (receive) operates to down-convert a signal containing a plurality of spectra. The ESR module (receive) also operates to isolate the spectra in the down-converted signal, where such isolation is implemented via filtering in some embodiments. According to embodiments of the invention, the ESR module (receive) is implemented using one or more unified down-conversion and filtering (UDF) modules. This is illustrated, for example, in FIG.  16 . In the example of FIG. 16, one or more of UDF modules  1610 ,  1612 ,  1614  operates to down-convert a received signal. UDF modules  1610 ,  1612 ,  1614  also operate to filter the down-converted signal so as to isolate the spectrum or spectra contained therein. As noted above, UDF modules  1610 ,  1612 ,  1614  are implemented using the universal frequency translation (UFT) modules of the invention. 
     The invention is not limited to the applications of the UFT module described above. For example, and without limitation, subsets of the applications (methods and/or structures) described herein (and others that would be apparent to persons skilled in the relevant art(s) based on the herein teachings) can be associated to form useful combinations. 
     For example, transmitters and receivers are two applications of the UFT module. FIG. 10 illustrates a transceiver  1002  that is formed by combining these two applications of the UFT module, i.e., by combining a transmitter  1004  with a receiver  1008 . 
     Also, ESR (enhanced signal reception) and unified down-conversion and filtering are two other applications of the UFT module. FIG. 16 illustrates an example where ESR and unified down-conversion and filtering are combined to form a modified enhanced signal reception system. 
     The invention is not limited to the exemplary applications of the UFT module discussed herein. Also, the invention is not limited to the exemplary combinations of applications of the UFT module discussed herein. These examples were provided for illustrative purposes only, and are not limiting. Other applications and combinations of such applications will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such applications and combinations include, for example and without limitation, applications/combinations comprising and/or involving one or more of: (1) frequency translation; (2) frequency down-conversion; (3) frequency up-conversion; (4) receiving; (5) transmitting; (6) filtering; and/or (7) signal transmission and reception in environments containing potentially jamming signals. 
     Additional exemplary applications are described below. 
     7. Specific Implementation Application 
     The present implementation of the invention is directed to a frequency synthesizer and applications of the same. Particularly, it is directed to a system and method for providing an output signal at a precise frequency or set of frequencies. As an example, a set of frequencies centered 30 KHz apart may be generated for use in cellular communications implementations. 
     7.1 System of Operation 
     Looking to FIG. 25, the first embodiment of the present implementation of the present invention is displayed. In this embodiment, a signal generator  2502  generates a signal  2512 . Signal  2512  may be a tone having a frequency f 0 , but the invention is not limited to this example. Signal  2512  is input to a first generalized frequency translation device  2504 . First generalized frequency translation device  2504  also accepts a control signal  2514  having a frequency f 1 . The output of first generalized frequency translation device  2504  is an output  2516  having a plurality of spectra having frequencies that may be represented by (f 0 +n·f 1 ), where “n” is any integer. Output  2516  is routed to a filter  2506  where undesired frequencies are filtered, resulting in a first filtered output  2518 . First filtered output  2518  is preferably comprised of a single frequency, for example, and not meant to be limiting, (f 0 +2·f 1 ). 
     First filtered output signal  2518  is routed to a second generalized frequency translation device  2508 . Second generalized frequency translation device  2508  also accepts a second control signal  2520  having a frequency f 2 . The output of second generalized frequency translation device  2508  is an output  2522  having a plurality of spectra having frequencies that may be represented by the expression (f 0 +n·f 1 ±m·f 2 ), where “n” is an integer that is determined by filter  2506 , and “m” is any integer. Output  2522  is routed to a filter where undesired frequencies are eliminated, resulting in a desired output  2524 . 
     In an exemplary implementation, filter  2510  is a selectable filter, and can select one or more of the spectra of output  2522 . As an example, filter  2510  may, at one point, select a signal having a frequency of (f 0 +2·f 1 +3·f 2 ) and then subsequently select a signal having a frequency of (f 0 +2f 1 −2f 2 ). In another example, filter  2510  is fixed, and selects only a single output frequency. In yet another example, filter  2510  selects a range of frequencies simultaneously. These examples are provided for purposes of illustration only, and are not meant to be limiting. 
     FIG. 26 illustrates a first example of generalized frequency translation devices  2504 / 2508 . In this example, signal  2512 /first filtered output signal  2518  is routed to an impedance module  2604 . Impedance module  2604  may be a resistor, and inductor, a capacitor, or any combination thereof, although the invention is not limited to these examples. The output of impedance module  2604  is gated by a switch  2602  at a rate that is a function of control signals  2514 / 2520  which have been routed through a control signal shaping module  2606 . It is noted that control signal shaping module  2606  is optional. The gating thereby creates outputs  2516 / 2522 . 
     FIG. 27 illustrates a second example of generalized frequency translation devices  2504 / 2508 . In this example, signal  2512 /first filtered output signal  2518  is routed to a switch  2702 . Switch  2702  may be a semiconductor device, such as a field effect transistor, although the invention is not limited to this embodiment. Switch  2702  is controlled by control signals  2514 / 2520  which have been routed through a control signal shaping module  2704 . It is noted that control signal shaping module  2704  is optional. The output of switch  2702  is connected through a capacitor  2706  to a ground  2707 . Also present at the output of switch  2702  is outputs  2516 / 2522 . 
     FIG. 28 illustrates a third example of generalized frequency translation devices  2504 / 2508 . In this example, signal  2512 /first filtered output signal  2518  is routed to a capacitor  2804 . The size of capacitor is selected to optimize energy transfer. In an example, capacitor  2804  is large, although the invention is not limited to this example. The output of capacitor  2804  is gated by a switch  2802  at a rate that is a function of control signals  2514 / 2520  which have been routed through a control signal shaping module  2806 . It is noted that control signal shaping module  2806  is optional. The gating thereby creates outputs  2516 / 2522 . 
     FIG. 29 illustrates the positive portion of a spectrum  2900  of signal  2512  at a frequency f 0 . 
     FIG. 30 illustrates a spectra  3000  that results from first generalized frequency translation device  2502 . The spectrum  2902  is displayed at f 0 , while the remaining spectra  3002  through  3008  are at frequencies (f 0 +f 1 ) through (f 0 +4·f 1 ). These frequencies are provided for purposes of illustration only, and in fact the spectra continue through (f 0 +n·f 1 ), where “n” is any integer. Note that each spectrum is located at a frequency distance of f 1  from adjacent spectra. 
     FIG. 31 illustrates a spectrum  3100  of first filtered output signal  2518 . For purposes of example only, first filtered output signal  2518  is shown at a frequency of (f 0 +2·f 1 ). First filtered output signal  2518  may be at any frequency (f 0 +n·f 1 ), where “n” is any integer. 
     FIG. 32 illustrates a spectra  3200  that results from second generalized frequency translation device  2508 . FIG. 32 is for the example wherein f 2  is less than f 1 . The spectrum  3004  is displayed at (f 0 +2f 1 ), while the remaining spectra  3202  through  3220  are at frequencies (f 0   +2·f   1 −5·f 2 ) through (f 0 +2f 1 +5·f 2 ). These frequencies are provided for purposes of illustration only, and in fact the spectra continue between (f 0 +2f 1 −m·f 2 ) through (f 0 +2·f 1 +m·f 2 ), where “m” is any integer. Note that each spectrum is located at a frequency distance of f 2  from adjacent spectra. 
     FIG. 33 illustrates a spectra  3200  that results from second generalized frequency translation device  2508 . FIG. 33 is for the example wherein f 2  is less than f 1 . The spectrum  3004  is displayed at (f 0 +2f 1 ), while the remaining spectra  3202  through  3220  are at frequencies (f 0   +2·f   1 −5·f 2 ) through (f 0 +2f 1 +5·f 2 ). These frequencies are provided for purposes of illustration only, and in fact the spectra continue between (f 0 +2f 1 −m·f 2 ) through (f 0 +2·f 1 +m·f 2 ), where “m” is any integer. Note that each spectrum is located at a frequency distance of f 2  from adjacent spectra. 
     FIG. 34 illustrates a frequency spectrum  3400  of the output of filter  2510  for the example wherein f 2  is larger than f 1 . As an example, and not meant to be limiting, desired output  2524  is illustrated as a signal having a frequency (f 0 +2·f 1 −3f 2 ). In one embodiment, filter  2510  is fixed, and desired output  2524  is illustrated by spectrum  3306 . In an alternate embodiment, desired output  2524  may be illustrated first by spectrum  3306 , then by spectrum  3312 , then by spectrum  3302 , and so on. In this embodiment, filter  2510  is not fixed, and may select different spectra at different times. In yet another embodiment, filter  2510  passes more than one spectrum at a time, so that, for example, spectra  3302 ,  3304 , and  3306  are all present simultaneously at desired output  2524 . These examples are provided for illustrative purposes only, and are not meant to be limiting. 
     In an alternate embodiment of the present invention, signal generator  2502  of FIG. 25 is replaced by a direct current signal source. In the representative spectral diagrams, signal  2512  would then have f 0  equal to zero. However, as shown in FIG. 37, each spectrum of output  2516  would still be located at a frequency distance of f 1  from adjacent spectra, and, as shown in FIG. 38, each spectrum of output  2522  would still be located at a frequency distance of f 2  from adjacent spectra. 
     7.2 Method of Operation 
     A flowchart  3500  of FIG. 35 illustrates the steps of a first embodiment of the present invention, and is described below with reference to the elements of FIG.  25 . In step  3502 , signal  2512  having a frequency f 0  is generated. In step  3504 , signal  2512  is gated at a rate that is a function of the frequency of control signal  2514  having a frequency f 1 . This results in signal  2516  that is filtered in step  3506 . In step  3508 , filtered signal  2518  is then gated at a rate that is a function of the frequency of second control signal  2520  having a frequency f 2 . The output  2522  is then filtered in step  3510 , thereby creating a desired output signal  2524 . 
     A flowchart  3600  of FIG. 36 illustrates the steps of an alternate embodiment of the present invention, and is described below with reference to the elements of FIG.  25 . In step  3602 , direct current signal  2512  is gated at a rate that is a function of the frequency of control signal  2514  having a frequency f 1 . This results in signal  2516  that is filtered in step  3604 . In step  3606 , filtered signal  2518  is then gated at a rate that is a function of the frequency of second control signal  2520  having a frequency f 2 . The output  2522  is then filtered in step  3608 , thereby creating a desired output signal  2524 . 
     The above methods are provided for illustrative purposes only, and one skilled in the relevant arts would appreciate, based on the teachings contained herein that other methods could be employed and still be within the spirit and scope of the invention. 
     8. Other Exemplary Applications 
     The application embodiments described above are provided for purposes of illustration. These applications and embodiments are not intended to limit the invention. Alternate and additional applications and embodiments, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, such alternate and additional applications and embodiments include combinations of those described above. Such combinations will be apparent to persons skilled in the relevant art(s) based on the herein teachings. 
     9. Conclusions 
     Exemplary implementations of the systems and components of the invention have been described herein. As noted elsewhere, these exemplary implementations have been described for illustrative purposes only, and are not limiting. Other implementation embodiments are possible and covered by the invention, such as but not limited to software and software/hardware implementations of the systems and components of the invention. Such implementation embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. 
     While various application embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.