Abstract:
A high-speed serial ATA physical layer includes a serial ATA control circuit. A serial ATA multiplexer outputs one of a plurality of serial ATA signals that is selected by the serial ATA control circuit. A serial ATA analog front end provides a first gain and pre-emphasis to the selected one of the plurality of serial ATA signals. The pre-emphasis alters a transmission characteristic of the selected one of the plurality of serial ATA signals.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/277,449 filed on Oct. 22, 2002. The disclosure of the above application is incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to serial ATA communications channels, and more particularly to a programmable pre-emphasis circuit for a serial ATA communications channel. 
   BACKGROUND OF THE INVENTION 
   A host and a device typically transmit and receive data to and from each other. For example in a personal computer environment, a disk drive controller (host) is often connected to a disk drive (device). Referring now to  FIG. 1A , a host  10  includes a receiver  12  and a transmitter  14 . A device  16  includes a receiver  18  and a transmitter  20 . The transmitter  14  of the host  10  transmits host data  22  to the receiver  18  of the device  16 . The transmitter  20  of the device  16  transmits device data  24  to the receiver  12  of the host  10 . In the personal computer environment the host  10  can be a disk controller  10 - 1  and the device  16  can be a disk drive  16 - 1  as shown in  FIG. 1B . Still other hosts and devices can be employed. 
   The host and the device are connected using a Serial Advanced Technology Attachment (SATA) standard, which is generally identified at  26 . The SATA standard is a simplified packet switching network between a host and a device. SATA typically employs balanced voltage (differential) amplifiers and two pairs of wires that connect transmitters and receivers of the host  10  and the device  16  in a manner similar to 100BASE-TX Ethernet. The SATA standard is disclosed in “Serial ATA: High Speed Serialized AT Attachment”, Serial ATA Organization, Revision 1.0, 29, Aug. 2001, and its Supplements and Errata, which are hereby incorporated by reference. 
   Referring now to  FIG. 1C , a typical physical layer (PHY)  28  of the host  10  and/or the device  16  is shown generally at  29 . An analog front end  30  provides an interface to the data transmission lines. The analog front end  30  includes differential drivers and receivers and/or out-of-band signaling circuits. A PHY control circuit  31  controls the functionality of the PHY  28 . Fixed pattern source and detect circuits  32  and  33 , respectively, are optional circuits that provide ALIGN primitives. The fixed pattern detect circuit  33  generates a COMMA signal when a K28.5 character is detected in the received data. 
   DataIn[0:n] and an output of the fixed pattern source  32  are input to a multiplexer  34 . The PHY control circuit  31  controls the multiplexer  34 . DataIn[0:n] includes data sent from the link layer to the PHY  28  for serialization and transmission. A data extraction circuit  35  separates the clock (RecClk clock signal) and data received by the receivers in the analog front end  30 . The TxClk output from the control circuit  31  regulates the frequency of the serial stream. DataOut[0:n], which is passed to the link layer, includes data that is received and deserialized by the PHY  28 . The SYSCLK signal is a reference clock signal that is used to establish the transmitter interface speed. Other control inputs and outputs generally identified by MISC in  FIG. 1C  are specified in the SATA standard. 
   Referring now to  FIG. 2 , the transmitter  14  of the host  10  or the transmitter  20  of the device  16  is shown. Differential data (D( 0 ) +  and D( 0 ) − ) to be transmitted is received by differential inputs of a differential driving device  40 . The differential driving device  40  creates a differential voltage (V +  and V − ) by driving differential outputs (i 0   +  and i 0   − ) through loads  42  and  44 . A communications channel  46  transmits the differential voltage to the receiver  18  of the device  16  or to the receiver  12  of the host  10 . The transmission characteristics of the communications channel  46  may attenuate or otherwise alter the signal that is received by the receiver at the opposite end of the communications channel  46 , which may increase bit error rates. 
   Referring now to  FIG. 3 , the differential output voltage in an ideal communications channel  46  is shown. In  FIG. 4 , the differential output voltage of a band-limiting communications channel is shown, which is a typical characteristic of the communications channel  46 . The transition from 0 to 1 to 0 creates an “eye”-shaped waveform that is generally identified at  48  in  FIGS. 4 and 5 . As the band-limiting transmission characteristic increases, the “eye” closes as shown by arrows  49 , which makes the 0-1-0 transition more difficult to detect. 
   SUMMARY OF THE INVENTION 
   A high-speed serial ATA physical layer according to the present invention transmits data over a communications medium using a serial ATA protocol. A serial ATA control circuit controls operation of the serial ATA physical layer. A serial ATA multiplexer outputs a serial ATA signal and has a plurality of input lines for receiving input data and a control input that communicates with the serial ATA control circuit. A serial ATA analog front end includes a first differential driver that communicates with the serial ATA multiplexer and provides a first gain to the serial ATA signal and a serial ATA pre-emphasis circuit that provides pre-emphasis to the serial ATA signal to alter a transmission characteristic of the serial ATA signal. 
   In other features, the serial ATA physical layer is implemented in a serial ATA device or a serial ATA host. The first differential driver generates a first amplified signal. The pre-emphasis circuit includes a first delay element that delays the first amplified signal to generate a first delayed signal, a second driver that amplifies the first delayed signal using a second gain to generate a second amplified signal, and a first summing circuit that adds the first amplified signal and the second amplified signal to generate a sum. 
   In yet other features, the pre-emphasis circuit further includes a second delay element that delays the second amplified signal to generate a second delayed signal. A third driver amplifies the second delayed signal using a third gain to generate a third amplified signal. The summing circuit adds the third amplified signal to the sum. 
   In still other features, the pre-emphasis circuit further includes a third delay element that delays the third amplified signal to generate a third delayed signal. A fourth driver amplifies the third delayed signal using a fourth gain to generate a fourth amplified signal. The summing circuit adds the fourth amplified signal to the sum. 
   In other features, the first, second and third delay elements provide at least one of unit delays and partial unit delays. The multiplexer receives L input lines at x frequency and outputs the first serial ATA signal at L*x frequency. L*x is greater than 1.4 GHz. 
   In other features, the first differential driver includes a gain control circuit that controls the first gain. n differential amplifiers have differential inputs that communicate with first and second inputs, differential outputs that communicate with first and second outputs, and enable inputs that communicate with the gain control circuit. The gain control circuit selectively enables the n differential amplifiers to adjust the first gain. 
   The second differential driver includes a pre-emphasis gain control circuit that controls the second gain. m differential amplifiers have differential inputs that communicate with first and second inputs, differential outputs that communicate with first and second outputs, and enable inputs that communicate with the pre-emphasis gain control circuit. The pre-emphasis gain control circuit selectively enables the m differential amplifiers to adjust the second gain. 
   In still other features, the communications channel has a band-limiting transmission characteristic. The pre-emphasis circuit compensates for the band-limiting transmission characteristic. The pre-emphasis circuit adjusts delays of the first and second delay elements and the first and second gains based on a selected communication channel medium. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1A  is a functional block diagram of a host and a device with a connection based on the SATA standard according to the prior art; 
       FIG. 1B  is a functional block diagram of a disk controller (host) and a disk drive (device) with a connection based on the SATA standard according to the prior art; 
       FIG. 1C  is a functional block diagram of a serial ATA physical layer according to the prior art; 
       FIG. 2  is a functional block diagram of a differential driving device for the transmitter of the host and/or the device according to the prior art; 
       FIG. 3  illustrates a differential voltage waveform at the receiver end of an ideal communications channel; 
       FIG. 4  illustrates a differential voltage waveform at the receiver end of a band-limited communications channel; 
       FIG. 5  illustrates a closing “eye”-shaped waveform as the band limiting characteristics of a communications channel increase; 
       FIG. 6  is a functional block diagram of a transmitter with programmable pre-emphasis according to the present invention for a serial ATA channel; 
       FIG. 7  illustrates a transmission characteristic of a band-limited channel before pre-emphasis, an exemplary pre-emphasis transmission characteristic, and a transmission characteristic after pre-emphasis; 
       FIG. 8  is a functional block diagram of the transmitter of  FIG. 6  in further detail; 
       FIGS. 9A-9C  are waveforms for multi-clocking; 
       FIG. 10  is a functional block diagram of exemplary driving devices with programmable gain; and 
       FIG. 11  is a functional block diagram of one of the driving devices of  FIG. 10 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
   Referring now to  FIG. 6 , a transmitter  100  with programmable pre-emphasis according to the present invention for a serial ATA channel is shown. Data is received by a multiplexer  104  on L lines each at x MHz. For example, current serial ATA standards specify L=10 and x=150 MHz, although other numbers of input lines and higher or lower data rates are contemplated. The multiplexer  104  outputs data at L*x MHz. The transmitter  100  provides programmable pre-emphasis based on transmission characteristics of the communications channel  46  to reduce receiver error rates. For example, the transmitter  100  may provide pre-emphasis to offset band-limiting characteristics of the communications channel  46 . Because the pre-emphasis is programmable, the transmitter  100  can be readily adapted to the particular transmission characteristics of other communications channels  46 . 
   Referring now to  FIG. 7 , a transmission characteristic of a band-limited channel before pre-emphasis is shown generally at  120 . A pre-emphasis transmission characteristic is shown at  124 . The resulting or combined signal is shown at  128 . As a result of the pre-emphasis in this example, the eye-shaped waveform  48  in  FIG. 5  is opened, which improves data error rates of the receiver at the opposite end of the communications channel  46 . As can be appreciated, the transmission characteristic and the pre-emphasis will vary for other types of communications channels  46 . 
   Referring now to  FIG. 8 , the transmitter  100  includes driving devices  130 - 1 ,  130 - 2 ,  130 - 3 ,  130 - 4 , . . . , and  130 - n , delay elements  134 - 1 ,  134 - 2 ,  134 - 3 , . . . , and  134 - n , summing circuits  138 - 1 ,  138 - 2 ,  138 - 3 , . . . , and  138 - n , and a pre-emphasis gain control circuit  140 . The data output by the multiplexer  104  is input to the driving device  130 - 1 , which provides a first gain a 0 , and to a delay chain including the delay elements  134 - 1 ,  134 - 2 , . . . , and  134 - n.    
   An output of the delay element  134 - 1  is input to the driving device  130 - 2 , which provides a second gain a 1 . The output of the delay element  134 - 1  is also output to the delay element  134 - 2 . An output of the delay element  134 - 2  is input to the driving device  130 - 3 , which provides a third gain a 2 . The output of the delay element  134 - 2  is also input to the delay element  134 - 3 . An output of the delay element  134 - 3  is input to the driving device  130 - 4 , which provides a fourth gain a 3 . The output of the delay element  134 - 3  is also input to the delay element  134 - n . An output of the delay element  134 - n  is input to the driving device  130 - n , which provides a gain a n . 
   Outputs of the driving device  130 - n  and the driving device  130 - 4  are input to the summer  138 - 4 . Outputs of the driving device  130 - 3  and the summer  138 - 4  are input to the summer  138 - 3 . Outputs of the driving device  130 - 2  and the summer  138 - 3  are input to the summer  138 - 2 . Outputs of the driving device  130 - 1  and the summer  138 - 2  are input to the summer  138 - 1 . An output of the summer  138 - 1  is transmitted over the communications channel  46  to the receiver at the opposite end of the communications channel  46 . While two-input summing circuits  134 - 1 ,  134 - 2 ,  134 - 3 , . . . , and  134 - n  are shown, summing circuits with three or more inputs can also be used to reduce the number of summing circuits  134 . 
   While the circuit shown in  FIG. 8  includes a primary stage  142  and three or more pre-emphasis stages  144 - 1 ,  144 - 2 ,  144 - 3  . . . , and  144 - n  (generally identified  144 ), the transmitter  100  can include the primary stage  142  and one or more pre-emphasis stages  144 . The number of pre-emphasis stages  144  that are used for a particular design will depend on the accuracy of the impulse response that is desired and the desired cost of the circuit. Increasing the number of pre-emphasis stages  133  generally increases the cost of the transmitter  100 . 
   The transmitter  100  that is shown in  FIG. 8  implements the transfer function set forth below:
 
Output= a   0   +a   1   z   −1   +a   2   z   −2   + . . . a   n   z   −n  
 
While the foregoing example illustrates terms with unit delay elements, fractional delay elements can also be used. Referring now to  FIGS. 9A-9C , using multi-clocking, the terms can be delayed for partial periods, such as T/2, T/3, . . . , or T/N. An example with three pre-emphasis terms and partial periods is as follows:
 
Output= a   0   +a   1   z   −1/2   +a   2   z   −1   +a   3   z   −3/2  
 
In addition, the pre-emphasis stages  144  can be limited to odd delays, even delays or any other combination using additional delay elements. For example,
 
Output= a   0   +a   1   z   −1   +a   3   z   −3   +a   5   z   −5  
 
The gains a 0 , a 1 , a 2 , . . . , and a n  can be positive, zero or negative, and not limited to integer values. Still other variations will be apparent to skilled artisans.
 
   Referring now to  FIGS. 10 and 11 , an exemplary transmitter  100  is shown and includes main and pre-emphasis stages  142  and  144 , respectively. Data D( 0 ) is input to a main driving device  164 - 1  which provides the first gain a 0 . Delayed data D( 1 ), D( 2 ), . . . , and D(n) are input to driving devices  204 - 2 ,  204 - 3 , . . . ,  204 - n , respectively, having the gains a 1 , a 2 , . . . , and a n , respectively. The pre-emphasis gain control circuit  140  adjusts the gain of the data D( 0 ) and the delayed data D( 1 ), D( 2 ), . . . and D(n) to provide a desired transmission characteristic. The desired transmission characteristics of various different media can be determined in advanced and stored in the pre-emphasis gain control circuit  140 . Dip adjusts and/or software adjusts can be used to select the gain settings and delays for the particular medium being used. 
   Referring now to  FIG. 11 , one of the driving devices  204  is illustrated in further detail. Each driving device  164  includes one or more differential amplifiers  220 - 1 ,  220 - 2 ,  220 - 3 , . . . ,  220 - m  having inputs coupled to input lines IN +  and IN −  and outputs coupled to output lines OUT and OUT. The driving devices  204  of the transmitter  100  may have different numbers of differential amplifiers  220  as needed. The pre-emphasis gain control circuit  210  increases or decreases gain by enabling or disabling one or more differential amplifiers  220 . 
   By providing programmable pre-emphasis, the transmitter  100  works with media having different transmission characteristics. With pre-emphasis, the transmitter provides compensation for degradation that occurs during transmission over the communications channel to reduce receiver error rates. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.