Abstract:
A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a process wherein a first insulator is deposited on an active area. A first metal level is deposited and defined, with a first mask, to form a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield. A second insulator is deposited, and via openings therein are defined, with a second mask. An overlying second metal level is deposited and defined, with a third mask, to form two connection areas covering the via openings on each side of the first and second pixels. The second and third masks are identical for the first and second pixels.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. application Pat. No. 14/642,100 filed Mar. 9, 2015, which claims the priority benefit of French Application for Patent No 1453318, filed on Apr. 14, 2014, the disclosures of which are hereby incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to a method for simultaneously manufacturing a first pixel and a second pixel respectively shielded on a first side and on a second side. 
       BACKGROUND 
       [0003]    In a pixel array, a pixel comprises, in a semiconductor substrate, a main region corresponding to a photodiode and various regions corresponding to transistor drains/sources. The case where each pixel is associated with an interconnection network comprising two metal levels is considered herein. 
         [0004]      FIG. 1  shows an example of a pixel read circuit. Circuit  100  comprises a photodiode  103  coupled to a read node INT via a transfer transistor  105 , for example, a MOS transistor, capable of receiving on its gate a transfer voltage TG. A power supply voltage VRT is coupled to node INT via a transistor  107  capable of receiving a reset voltage RST on its gate. A transistor  109  has its drain coupled to power supply voltage VRT, its gate coupled to node INT, and its source coupled to an output node V X  via a read transistor  111  capable of receiving a read voltage RD on its gate. The reference voltage of circuit  100  is ground VSS. 
         [0005]    In certain pixel arrays, it is provided to insert self-focusing pixels. A self-focusing pixel is a pixel intended to receive only light arriving under a given incidence. Based on pixels receiving light under different incidences, a focus determination can be performed. Self-focusing pixels comprise shields covering substantially complementary portions of the photodiodes of these pixels, for example, a right-hand portion and a left-hand portion. A self-focusing pixel shielded on the left-hand side (called left-hand pixel hereafter) and a self-focusing pixel shielded on the right-hand side (hereafter, the right-hand pixel) are here distinguished. 
         [0006]    The manufacturing of similar pixel arrays comprising “normal” pixels and self-focusing pixels is here considered, the self-focusing pixels being located in determined and identical cells in each array. However, in practice, according to the specific processing unit adopted by a user, the user desires for the left-hand and right-hand pixels to be distributed differently inside of the determined cells which are assigned thereto. 
       SUMMARY 
       [0007]    It is desired to simultaneously manufacture a left-hand and a right-hand pixel while providing the smallest possible number of different masks to decrease the manufacturing costs of a plurality of similar pixel arrays, comprising self-focusing pixels with different distributions. 
         [0008]    Thus, an embodiment provides a method of simultaneously manufacturing a first pixel and a second pixel respectively shielded on a first side and on a second side, comprising the steps of: 
         [0009]    a) depositing a first insulator on an active area; 
         [0010]    b) depositing a first metal level and defining therein, with a first mask, a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield, the outer limit of the shield and the line being at equal distance from the center of each pixel, the screen and the line being symmetrical for the first and second pixels; 
         [0011]    c) depositing a second insulator and defining therein, with a second mask, openings for vias crossing the first insulator all the way to the shield and to the line; and 
         [0012]    d) depositing a second metal level and defining therein, with a third mask, two connection areas covering the via openings on each side of the first and second pixels, where each of the second and third masks is identical for the first and second pixels. 
         [0013]    According to an embodiment, the first insulator comprises a first insulating layer covered with a second insulating layer, and the second insulator comprises a third insulating layer covered with a fourth insulating layer, this method comprising the steps of: 
         [0014]    e) etching, with a fourth mask, between steps b) and c), the second insulating layer between the shield and the line; and 
         [0015]    f) etching, with a fifth mask, after step d), the fourth insulating layer between connection areas, where the fifth mask is identical for the first and second pixels. 
         [0016]    According to an embodiment, additional lines are formed between the shield and an outer limit of the first and second pixels, and between the line opposite to the shield and another outer limit of the first and second pixels. 
         [0017]    Another embodiment provides an array of photodiodes comprising first and second pixels respectively shielded on a first side and on a second side, wherein the first pixel comprises on the first side, in a first metal level, a first shield substantially covering half of the pixel, and a first line between an outer limit of the first shield and a corresponding outer limit of the pixel and, in a second metal level, a first connection area connected by first and second vias to the first line and to the outer limit of the first shield; and, on the second side, in the first metal level a second line in an area corresponding to a portion of the surface area occupied by a second shield in the second pixel and, in the second metal level, a second connection area adjacent to the other outer limit of the pixel and connected by third vias to the second line; the second pixel comprises a first line, first and second connection area, and first, second, and third vias at the same locations as in the first pixel; and on the first side, in the first metal level, a third line in contact with fourth vias located at the same locations as the second vias and, on the second side, a second shield having its outer limit in contact with fifth vias located at the same locations as the third vias. 
         [0018]    According to an embodiment, the first pixel comprises additional lines between the first line and the first shield, and between the second line and the outer limit of the pixel; and the second pixel comprises additional lines between the second line and the third line, and between the second shield and the outer limit of the pixel. 
         [0019]    In an embodiment, a photo-sensitive circuit comprises: a first pixel and a second pixel, each of the first and second pixels including a first side and a second side; a first metal level over the first and second pixels, said first metal level including: a first shield on the first side of the first pixel; a first line on the first side of the first pixel between an outer limit of the first shield and a corresponding outer limit of the first pixel; a second line on the second side of the first pixel; a second shield on the second side of the second pixel; a third line on the first side of the second pixel; and a fourth line on the first side of the second pixel between an outer limit of the third line and a corresponding outer limit of the second pixel; a second metal level over the first metal level, said second metal level including: a first connection area on the first side of the first pixel adjacent to the outer limit of the first pixel and connected by first and second vias to the first line and the first shield, respectively; a second connection area on the second side of the first pixel adjacent to an opposite outer limit of the first pixel and connected by a third via to the second line; a third connection area on the first side of the second pixel adjacent to the outer limit of the second pixel and connected by a fourth and fifth vias to the third and fourth lines, respectively; a fourth connection area on the second side of the second pixel adjacent to an opposite outer limit of the second pixel and connected by a sixth via to the second shield. 
         [0020]    In an embodiment, a photo-sensitive circuit comprises: first and second pixels, each of the first and second pixels including a first side and a second side; wherein the first pixel comprises: on the first side, in a first metal level, a first shield and a first line between an outer limit of the first shield and a corresponding outer limit of the first pixel and, in a second metal level, a first connection area connected by first and second vias to the first line and to the first shield, respectively; and on the second side, in the first metal level, a second line in the second pixel and, in the second metal level, a second connection area adjacent to an opposite outer limit of the first pixel and connected by a third via to the second line; and wherein the second pixel comprises: on the first side, in the first metal level, a third line and a fourth line between an outer limit of the third line and a corresponding outer limit of the second pixel and, in the second metal level, a third connection area connected by fourth and fifth vias to the third and fourth lines, respectively; and on the second side, in the first metal level, a second shield and, in the second metal level, a fourth connection area adjacent to an opposite outer limit of the second pixel and connected by a sixth via to the second shield. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, wherein: 
           [0022]      FIG. 1 , previously described, shows an example of a pixel read circuit; 
           [0023]      FIGS. 2A and 2B  are top views showing a left-hand pixel and a right-hand pixel; 
           [0024]      FIGS. 3A and 3B  are cross-section views along plane AA of  FIGS. 2A and 2B ; 
           [0025]      FIGS. 4A to 8A and 4B to 8B  are cross-section views along plane AA of  FIGS. 2A and 2B , showing successive steps of an example of simultaneous manufacturing of left-hand and right-hand pixels; 
           [0026]      FIGS. 9A and 9B  are top views showing an embodiment of a left-hand pixel and of a right-hand pixel; 
           [0027]      FIGS. 10A and 10B  are cross-section views along plane AA of  FIGS. 9A and 9B ; and 
           [0028]      FIGS. 11A to 15A and 11B to 15B  are cross-section views along plane AA of  FIGS. 9A and 9B , showing successive steps of a mode of simultaneous manufacturing of left-hand and right-hand pixels. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    For clarity, the same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. 
         [0030]      FIGS. 2A and 2B  are top views showing a left-hand pixel  200  and a right-hand pixel  250 .  FIGS. 3A and 3B  are cross-section views along plane AA of  FIGS. 2A and 2B . The elements specific to a left-hand pixel are marked with an index L and the elements specific to a right-hand pixel are marked with an index R. 
         [0031]    Each pixel comprises a first metal level  301  covering two insulating layers  303  and  305  coating a photodiode  103 . A second metal level  307  is separated from first metal level  301  by two insulating layers  309  and  311 . 
         [0032]    In first metal level  301  are particularly formed a shield S (respectively S L  and S R ) and lines towards voltages and nodes VSS, V X , VRT, and INT of read circuit  100  of  FIG. 1 . Second metal level  307  particularly has a connection area C (respectively C L  and C R ) formed therein. Connection area C L  is connected on the one hand to line VSS by vias  313  and on the other hand to shield S L  by vias  315 . Connection area C R  is connected on the one hand to shield S R  by vias  317  and on the other hand to line VSS of an adjacent pixel to the right of the right-hand pixel by vias  319 . Lines VSS, V X , VRT, and INT of pixels  200  and  250  and have the same topology. 
         [0033]    Line VSS is located on the left-hand side of the pixel and line V X  is located next to line VSS. Line INT is located to the right of the pixel and line VRT is located to the left of line INT. In the case of the left-hand pixel, shield S L  is located to the right of line V X . In the case of the right-hand pixel, shield S R  is located to the left of line VRT. Lines VSS, V X , VRT, and INT cross each pixel to be connected to the other elements (not shown herein) of circuit  100  of  FIG. 1 . 
         [0034]      FIGS. 4A to 8A and 4B to 8B  are cross-section views along plane AA of  FIGS. 2A and 2B , showing successive steps of an example of manufacturing of a left-hand pixel  200  and of a right-hand pixel  250 . 
         [0035]    At the step illustrated in  FIGS. 4A and 4B , first metal level  301  is deposited on insulating layers  303  and  305  coating photodiode  103 . In first metal level  301  are formed, according to the pattern of a first mask, shields S (respectively S L  and S R ) and lines VSS, V X , VRT, and INT. The shields cover substantially complementary portions of the photodiodes of pixels  200  and  250 . 
         [0036]    At the step illustrated in  FIGS. 5A and 5B , insulating layer  305  is removed, according to the pattern of a second mask, between shield S L  and line VRT of the left-hand pixel, and between shield S R  and line V X  of the right-hand pixel. 
         [0037]    At the step illustrated in  FIGS. 6A and 6B , insulating layers  309  and  311  are deposited and vias  313 ,  315 ,  317 , and  319  are defined according to the pattern of a third mask. 
         [0038]    At the step illustrated in  FIGS. 7A and 7B , second metal level  307  is deposited. In second metal level  307 , connection area C L  is formed so that it is in contact with vias  313  and  315 , and connection area C R  is formed so that it is in contact with vias  317  and  319 . The connection areas are formed according to the pattern of a fourth mask. 
         [0039]    At the step illustrated in  FIGS. 8A and 8B , insulating layer  311  is removed, according to the pattern of a fifth mask, between connection area C (respectively C L  and C R ) and the pixel edge. 
         [0040]    It should be noted that the patterns of the five above-mentioned masks have different topologies for the left-hand and right-hand pixels. 
         [0041]    As a result of the foregoing, to manufacture a first and a second pixel arrays comprising left-hand  200  and right-hand  250  pixels distributed differently in determined cells, a component manufacturer should design and manufacture five specific masks for each array, which is expensive. 
         [0042]      FIGS. 9A and 9B  are top views showing an embodiment of a left-hand pixel  400  and of a right-hand pixel  450 .  FIGS. 10A and 10B  are cross-section views along plane AA of  FIGS. 9A and 9B . The elements specific to a left-hand pixel are marked with an index L and the elements specific to a right-hand pixel are marked with an index R. 
         [0043]    Each pixel comprises a first metal level  401  covering two insulating layers  403  and  405  coating a photodiode  103 . A second metal level  407  is separated from first metal level  401  by two insulating layers  409  and  411 . 
         [0044]    In first metal level  401  are particularly formed shields S (respectively S L  and S R ) and lines towards voltages and nodes VSS, V X , VRT, and INT of read circuit  100  of  FIG. 1 . Shields S and lines VSS, V X , VRT, INT have the same topology as in the case of  FIGS. 2A, 2B and 3A, 3B . These elements will thus not be described again. 
         [0045]    Further, first metal level  401  comprises lines D (respectively D L  and D R ). Line D L  is located to the left of line VRT while line D R  is located to the right of line V X . Line D L  is formed on a surface of the left-hand pixel corresponding to a portion of the surface occupied by shield S R  in the right-hand pixel. Line D R  is formed on a surface of the right-hand pixel corresponding to a portion of the surface occupied by shield S L  in the left-hand pixel. The provision of lines D L  and D R  enables, as will be seen hereafter, to define vias at the same locations in the left-hand and right-hand pixels. 
         [0046]    In second metal level  407  are formed connection areas C 1   L  and C 2   R  respectively corresponding to connection areas C L  and C R  of  FIGS. 2A, 3A and 2B, 3B . These elements will thus not be described again. 
         [0047]    Further, in second metal level  407  are formed a connection area C 2   L  in the left-hand pixel and a connection area C 1   R  in the right-hand pixel. Connection area C 2   L  has the same topology as connection area C 2   R  and connection area C 1   R  has the same topology as connection area C 1   L . 
         [0048]    Connection areas C 1   L  and C 2   R  are connected to the first metal level by vias  413   L ,  415   L ,  417   R  and  419   R  corresponding to vias  313 ,  315 ,  317 , and  319  defined in left-hand  200  and right-hand  250  pixels of  FIGS. 2A, 3A and 2B, 3B . The connections between connection areas C 1   L , C 2   R  and the first metal level will not be described again. 
         [0049]    Further, connection areas C 2   L  and C 1   R  are connected to the first metal level, on the one hand, by vias  417   L ,  419   L , and on the other hand by vias  413   R  and  415   R . Vias  417   L  and  419   L  connect connection area C 2   L , respectively, to line D L  and to line VSS of the adjacent pixel to the right of the left-hand pixel. Vias  417   L  and  419   L  connect connection area C 1   R , respectively, to line VSS and to line D R . Vias  417   L  and  419   L  are defined at the same locations in the left-hand pixel as vias  417   R  and  419   R  in the right-hand pixel. Vias  413   R  and  415   R  are defined at the same locations in the right-hand pixel as vias  413   L  and  415   L  in the left-hand pixel. 
         [0050]      FIGS. 11A to 15A and 11B to 15B  are cross-section views along plane AA of  FIGS. 9A and 9B , showing successive steps of a mode of simultaneous manufacturing of left-hand  400  and right-hand  450  pixels. 
         [0051]    At the step illustrated in  FIGS. 11A and 11B , first metal level  401  has been deposited on insulating layers  403  and  405  coating photodiode  103 . In first metal level  401  are formed, according to the pattern of a first mask, shields S (respectively S L  and S R ) and lines D (respectively, DL and DR) VSS, V X , VRT, and INT. Shields S L  and S R  cover substantially complementary portions of the photodiodes of pixels  400  and  450 . 
         [0052]    At the step illustrated in  FIGS. 12A and 12B , insulating layer  405  is removed, according to the pattern of a second mask, between shield S L  and line DL of the left-hand pixel, and between shield S R  and line DR of the right-hand pixel. 
         [0053]    At the step illustrated in  FIGS. 13A and 13B , insulating layers  409  and  411  are deposited and vias  413 ,  415 ,  417 , and  419  are defined according to the pattern of a third mask. Vias  413   L  and  413   R  are in contact with lines VSS. Vias  415   L  and  415   R  are in contact, respectively, with shield S L  and line D R . Vias  417   L  and  417   R  are in contact, respectively, with line D L  and shield S R . Vias  419   L  and  419   R  are in contact with lines VSS of the adjacent pixels to the right of the left-hand and right-hand pixels. 
         [0054]    At the step illustrated in  FIGS. 14A and 14B , second metal level  407  is deposited. In second metal level  407 , according to a pattern of a fourth mask, connection areas C 1   L  and C 1   R  are formed in such a way that they are in contact with vias  413  and  415 , and connection areas C 2   L  and C 2   R  are formed in such a way that they are in contact with vias  417  and  419 . 
         [0055]    At the step illustrated in  FIGS. 15A and 15B , insulating layer  411  is removed between shields C 1  and C 2  according to the pattern of a fifth mask. 
         [0056]    It should be noted that the patterns of the first and second above-mentioned masks have different topologies for the left-hand and right-hand pixels while the patterns of the third, fourth, and fifth above-mentioned masks have the same topology for the left-hand and right-hand pixels. Thus, to pass from a first pixel array to a second pixel array comprising a different distribution of left-hand  400  and right-hand  450  pixels inside of determined cells, the component manufacturer only has to design and manufacture two specific masks (and not five as in the case of the example of  FIGS. 2A to 8B ). 
         [0057]    It has been considered herein that insulating layers  405  and  411  have refraction indexes different from the refraction indexes of insulating layers  403  and  409 . To avoid optical losses, it has thus been provided herein to remove layers  405  and  411  above the active area of the photodiodes. If such a removal is not desired to be performed (for example, in the case where insulating layers  403 ,  405 ,  409 , and  411  have close refraction indexes), the method of  FIGS. 2A and 8B  will require three specific masks, while the method of  FIGS. 9A to 15B  will require a single specific mask. 
         [0058]    Hereafter, dimensions taken along the horizontal axis of  FIGS. 9A and 9B  will be called “lengths”, and dimensions taken along the vertical axis of  FIGS. 9A and 9B  will be called “widths”. 
         [0059]    As a numerical example, the length of the photodiode of a pixel is in the range from 2 to 6 μm, for example, 4.1 μm. The length of connection area C 1  is in the range from 500 and 800 nm, for example, 700 nm. The length of connection area C 2  is in the range from 500 and 800 nm, for example, 600 nm. The length of a shield corresponds to half the length between areas C 1  and C 2 , in the present case, 1.4 μm. The width of a pixel is in the range from 2 to 6 μm, for example, 4.1 μm. The width of a photodiode of a pixel is in the range from 2 and 3.2 μm, for example, 2.4 μm, for a pixel having a 4.1 μm side length. 
         [0060]    Specific embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. 
         [0061]    In particular, although self-focusing pixels respectively shielded to the right and to the left have been described herein, other configurations with complementary shields may be provided, for example, self-focusing pixels respectively shielded on the top and at the bottom. 
         [0062]    Further, it has been indicated at various steps of the previous description that layer  305  is selectively etched over layer  303 . This may result from the fact that the layers are made of different materials, for example, made of silicon nitride and of silicon oxide. It may also be provided for the two layers to be of same nature, for example, made of silicon nitride, and for an etch stop layer to be provided therebetween. The same observation applies to layers  403  and  405 . 
         [0063]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.