Abstract:
An active matrix display device comprises a substrate having an insulating surface, a plurality of pixel electrodes arranged in a matrix form over the substrate, and a plurality of switching elements operationally connected to the pixel electrodes. Each of the switching elements further comprise a thin film transistor. The display device further includes a display medium comprising an emissive material that is capable of electrically changing luminous strength disposed at each of the pixel electrodes, and a driver circuit that includes a plurality of thin film transistors for driving the plurality of switching elements. Each of the plurality of thin film transistors comprise a crystallized semiconductor layer, a gate insulating film adjacent to the crystallized semiconductor layer and a gate electrode adjacent to the gate insulating film.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a shift register circuit constructed by thin film transistor (TFTs), in particular, a redundancy shift register circuit. 
         [0002]    A shift register circuit in which TFTs are used is utilized in a driver circuit of an image sensor or a liquid crystal display (LCD) device, in particular, recently, in a driver circuit of an active matrix type display device. 
         [0003]    In an active matrix type display device, each pixel is arranged in a cross section portion of an active matrix circuit and connected with a switching element, and image information is controlled by on/off of the switching element. As a display media of such display device, a liquid crystal, plasma, an object (state) capable of electrically changing an optical characteristic (reflectance, refractive index, transmimissivity, emission (luminous) strength) or the like are used. As a switching element, in particular, a three terminal element, that is, a field effect transistor having a gate, a source and a drain is used. 
         [0004]    In a matrix circuit, a signal line (a gate line) which is arranged in parallel to a line is connected with gate electrodes of transistors with respect to the line, and a signal line (a source line) which is arranged in parallel to a column is connected with source (or drain) electrodes of the transistors with respect to the column. A circuit for driving the gate line is referred to as a gate driver circuit, and a circuit for driving the source line is referred to as a source driver circuit. 
         [0005]    Since the gate driver circuit generates a vertical line scan timing signal with respect to an active matrix type display device, a shift register includes serial-connected registers (in a single line) corresponding to the number of gate lines with a vertical direction. As a result, switching of thin film transistors (TFTs) in an active matrix type display device is performed by the gate driver circuit. 
         [0006]    Since the source driver circuit generates a horizontal line image signal of image data to be displayed on an active matrix type display device, a shift register includes serial-connected registers (in a single line) corresponding to the number of source lines with a horizontal direction. Also, by a latch pulse synchronous with a horizontal scan signal, an analog switch is turned on or off. As a result, a current is supplied from the source driver circuit to TFTs in an active matrix type display device, to control alignment of a liquid crystal cell. 
         [0007]    Referring to  FIG. 5 , a common active matrix type display device will be described. 
         [0008]    A horizontal line scan timing signal is generated by a shift register  51 . Analog switches  53  and  54  are turned on and then a video signal is stored in analog memories  55  and  56  in response to the horizontal line scan timing signal. Image data corresponding to the video signal stored in the analog memories  55  and  56  is stored in analog memories  59  and  60  through analog switches  57  and  58  turned on by timing of a latch pulse. The image data is supplied from the analog buffers  59  and  60  to source lines of TFTs  63  and  64  through analog buffers  61  and  62  in an active matrix circuit  70  of an active matrix type liquid crystal display device in timing of the latch pulse. 
         [0009]    On the other hand, a vertical line scan timing signal is generated by a shift register  52  and then supplied to gate lines of the TFTs  63  and  64  in the active matrix circuit  70  of the active matrix type liquid crystal display device. Therefore, the image data (voltage) supplied to the source lines is applied to liquid crystals  65  and  66 , to determine alignment of the liquid crystals  65  and  66  connected with drain lines of the TFTs  63  and  64 . The active matrix type liquid crystal display device is operated by the above operation. 
         [0010]    Generally, a shift register includes a circuit as shown in  FIGS. 6A and 6B , in particular, a D-type flip-flop.  FIG. 6A  shows a D-type flip-flop constructed using analog switches, and  FIG. 6B  shows a D-type flip-flop constructed using clocked invertors. These operation will be described below. 
         [0011]    In  FIG. 6A , when an operation clock CK is a high level (H) and an input signal DATA is a high level (H), a complementary type transmission gate a- 1  is turned on and then the input signal DATA is input to a complementary type invertor circuit a- 2 . Therefore, an output of the complementary type invertor circuit a- 2  becomes a low level (L). In this state, complementary type transmission gates a- 4  and a- 5  are in a turn off state. 
         [0012]    When the operation clock CK is changed to a low level (L) while the input signal DATA is a high level (H), the complementary transmission gate a- 1  becomes a turn off state, the complementary type transmission gates a- 4  and a- 5  become a turn on state. Therefore, an output of the complementary invertor circuit a- 2  is held to a low level (L). 
         [0013]    Also, since the complementary type transmission gate a- 5  becomes a turn on state, an output of an complementary type invertor circuit a- 6  becomes a high level (H). In this state, a complementary type transmission gate a- 8  becomes a turn off state. 
         [0014]    When the operation clock CK is changed to a high level (H) again, the complementary transmission gate a- 5  becomes a turn off state and the complementary type transmission gate a- 8  becomes a turn on state, so that a previous signal level is held. Therefore, an output of the complementary type invertor circuit a- 6  can be held to an input signal DATA having a high level (H) in synchronous with an operation clock CK. 
         [0015]    As a result, a D-type flip-flop can be constructed using transmission gates. Also, when an input signal DATA is a low level (L), the above described operation is performed. 
         [0016]    In  FIG. 6B , when the operation clock CK is a high level (H) and the input signal DATA is a high level (H), an output of a complementary clocked invertor circuit b- 1  becomes a low level (L) and then an output of the complementary invertor circuit b- 2  becomes a high level (H). In this state, complementary clocked invertor circuits b- 3  and b- 4  are in a turn off state. 
         [0017]    When the operation clock CK is changed to a low level (L) while the input signal DATA is a high level (H), the complementary clocked invertor circuits b- 3  and b- 4  are turned on, so that an output of the complementary type invertor circuit b- 2  is held to a high level (H). An output of the complementary invertor circuit b- 5  becomes a high level (H). In this state, the complementary clocked invertor circuit b- 6  is a turn off state. 
         [0018]    When the operation clock CK is changed to a high level again, the complementary type clocked invertor circuit becomes a turn off state, and the complementary type clocked invertor circuit becomes a turn on state. Therefore, an output of the complementary type invertor circuit can be held to an input signal DATA having a high level (H) in synchronous with an operation clock CK. 
         [0019]    As a result, a D-type flip-flop is constructed by clocked invertors. Also, when an input signal DATA is a low level (L), the above described operation is performed. 
         [0020]    In a shift register circuit used in gate and source driving circuits of a common active matrix type display device, as shown in  FIGS. 2A and 2B , registers having the same number as the number of gate lines (or source lines) are connected in serial. In a gate driver circuit as shown in  FIG. 2A , outputs of registers SR, (i=1 to n) in a shift register circuit  120  are connected to gate lines  123  and  124  through invertor type buffer circuits  121  and  122 . In a source driver circuit as shown in  FIG. 2B , outputs of registers SR i  (i=1 to N) in a shift register circuit  125  are connected to control terminals of sampling transmission gates  128  and  129  through invertor type buffer circuits  126  and  127 . 
         [0021]    If at least one register has defect in the shift register circuit having serial-connected registers, image data and scan timing signals output from the defect register and later connected register are abnormal, an accuracy image cannot be obtained. This problem is due to a yield of a shift register. 
       SUMMARY OF THE INVENTION 
       [0022]    The object of the present invention is to solve the above problems. 
         [0023]    One exemplary embodiment of the present invention includes an active matrix display device having a substrate having an insulating surface, a pixel portion comprising a pixel having a switching TFT over the substrate and a display element over the substrate, electrically connected to the switching TFT, and a driver circuit comprising a shift register comprising an inverter circuit having an input terminal, a first TFT over the substrate, a second TFT over the substrate, a third TFT over the substrate, a fourth TFT over the substrate, and an output terminal, wherein a first terminal of the first TFT is electrically connected to the input terminal, wherein a second terminal of the first TFT is electrically connected to a first terminal of the second TFT, and to a gate terminal of the third TFT, wherein a first terminal of the third TFT is electrically connected to a first power source, wherein a second terminal of the third TFT is electrically connected to a second power source, via a first resistance element, wherein a first terminal of the fourth TFT is electrically connected to the first power source, wherein a second terminal of the fourth TFT is electrically connected to the second power source, via a second resistance element, wherein a second terminal of the second TFT is electrically connected to the second terminal of the fourth TFT, wherein the output terminal is electrically connected to the second terminal of the third TFT, and to a gate terminal of the fourth TFT, wherein a clock signal is inputted to a gate terminal of the first TFT, wherein an inverted clock signal is inputted to a gate terminal of the second TFT, and wherein each of the switching TFT, the first TFT, the second TFT, the third TFT and the fourth TFT comprises an active layer having a channel forming region comprising an impurity element having a same conductivity type. 
         [0024]    On exemplary embodiment of the present invention includes an active matrix display device having a substrate having an insulating surface, a pixel portion comprising a pixel having a switching TFT over the substrate and a display element over the substrate, electrically connected to the switching TFT, and a driver circuit comprising a shift register comprising an inverter circuit having an input terminal, a first TFT over the substrate, a second TFT over the substrate, a third TFT over the substrate, a fourth TFT over the substrate, a fifth TFT over the substrate, a sixth TFT over the substrate, and an output terminal, wherein a first terminal of the first TFT is electrically connected to the input terminal, wherein a second terminal of the first TFT is electrically connected to a first terminal of the second TFT, and to a gate terminal of the third TFT, wherein a first terminal of the third TFT is electrically connected to a first power source, wherein a second terminal of the third TFT is electrically connected to a second power source, and to a first terminal of the fifth TFT, wherein a second terminal of the fifth TFT is electrically connected to a gate terminal of the fifth TFT, and to a second power source, wherein a first terminal of the fourth TFT is electrically connected to the first power source, wherein a second terminal of the fourth TFT is electrically connected to the second power source, and to a first terminal of the sixth TFT, wherein a second terminal of the sixth TFT is electrically connected to a gate terminal of the sixth TFT, and to the second power source, wherein a second terminal of the second TFT is electrically connected to the second terminal of the fourth TFT, wherein the output terminal is electrically connected to the second terminal of the third TFT, and to a gate terminal of the fourth TFT, wherein a clock signal is inputted to a gate terminal of the first TFT, wherein an inverted clock signal is inputted to a gate terminal of the second TFT, and wherein each of the switching TFT, the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT and the sixth TFT comprises an active layer having a channel forming region comprising an impurity element having a same conductivity type. 
         [0025]    On exemplary embodiment of the present invention includes an active matrix display device having a substrate having an insulating surface, a pixel portion comprising a pixel having a switching TFT over the substrate and a display element over the substrate, electrically connected to the switching TFT, and a driver circuit comprising a shift register comprising an inverter circuit having an input terminal, a first TFT over the substrate, a second TFT over the substrate, a third TFT over the substrate, a fourth TFT over the substrate, a fifth TFT over the substrate, a sixth TFT over the substrate, and an output terminal, wherein a first terminal of the first TFT is electrically connected to the input terminal, wherein a gate terminal of the second TFT is electrically connected to a second terminal of the first TFT, wherein a first terminal of the second TFT is electrically connected to a first power source, wherein a first terminal of the fourth TFT is electrically connected to a second terminal of the second TFT, to a first terminal of the third TFT, and to a second power source via a first capacitor, wherein a first terminal of the fifth TFT is electrically connected to the first power source, wherein a gate terminal of the fifth TFT is electrically connected to a second terminal of the fourth TFT, and the second power source via a second capacitor, wherein a first terminal of the sixth TFT is electrically connected to a second terminal of the fifth TFT, wherein the output terminal is electrically connected to the second terminal of the sixth TFT, and to a second terminal of the third TFT, wherein a clock signal is inputted to a gate terminal of the first TFT, and to a gate terminal of the third TFT, wherein an inverted clock signal is inputted to a gate terminal of the fourth TFT, and to a gate terminal of the sixth TFT, and wherein each of the switching TFT, the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT and the sixth TFT comprises an active layer having a channel forming region comprising an impurity element having a same conductivity type. 
         [0026]    According to the above embodiments, the active layer includes crystallized silicon, wherein at least one of the first, second, third, fourth, fifth, and sixth TFTs has at least one lightly doped region formed by ion doping using the gate electrode of the corresponding TFT as a mask. 
         [0027]    According to the above embodiments, the display element includes an emissive material or a liquid crystal material. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]      FIG. 1  shows a redundancy shift register circuit in a driving circuit of an active matrix type display device according to an embodiment of the present invention; 
           [0029]      FIGS. 2A and 2B  show a shift register circuit in a driving circuit of a common active matrix type display device, respectively; 
           [0030]      FIG. 3  shows a shift register circuit of an embodiment; 
           [0031]      FIG. 4  shows a shift register selecting switch of the embodiment; 
           [0032]      FIG. 5  shows a schematic view of a common active matrix type display device; 
           [0033]      FIGS. 6A and 6B  show a common register, respectively. 
           [0034]      FIGS. 7A and 7B  show a priority encoder circuit and a multiplexer circuit, respectively. 
           [0035]      FIGS. 8A to 8C  show a bias circuit, respectively. 
           [0036]      FIGS. 9A to 9C  show a register constructed by p-channel transistors; 
           [0037]    FIGS.  10 A to  1 OF show a method for forming complementary invertor circuit; 
           [0038]      FIGS. 11A and 11B  show a shift register selecting circuit of the embodiment; 
           [0039]      FIG. 12  shows a truth table of a priority encoder circuit; and 
           [0040]      FIG. 13  shows a shift register selecting switch of another embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0041]    As shown in  FIG. 1 , a shift register circuit  104  includes at least one register group  103  and a register selecting switch  102 . The register group  103  includes register lines  101   a,    101   b,  and  101   n  having a plurality of serial-connected registers SRAi, SRBi, . . . , and SRZi (i=1 to n), respectively. The register line selecting switch  103  selects one of the register lines. 
         [0042]    In this structure, one register line is used as a main register line, and the other register lines are used as a subregister line. When a plurality of register groups are arranged in a shift register circuit, the register groups are connected with each other in serial, to use as a shift register constructing gate and source driver circuits. Defect detection terminals  105   a,    105   b,  . . . ,  105   n  are arranged with the register lines in the register group, respectively, so that whether or not each register line operates normally is detected. An output of a last register of each shift register line is connected with the register line selecting switch  103 . 
         [0043]    The register line selecting switch  103  has at least one bias circuit (as described later). A voltage is always applied to the bias circuit, switching operation by the bias circuit is performed by providing one bias. 
         [0044]    When one of the register lines is selected by the register line selecting switch  103 , register column selecting switches  106   a,    106   b,  . . . ,  106   n  selects registers included in the selected one of the register lines, respectively. The number of register column selecting switches coincides with the number of registers included in each register line. Each register column selecting switch selects one of a plurality of input signals as an output signal. A signal for selecting the output signal is generated by using an output signal of the bias circuit. 
         [0045]    When defect is detected by examining a main register line using a defect detection terminal, one of subregister lines is examined by another defect detection terminal. When defect is not detected, the register line selecting switch  102  selects the one of the subregister lines. Simultaneously, the register column selecting switches select the registers of the selected subregister lines. 
         [0046]    As a result, redundancy is performed for register lines in a register group, so that a yield for a whole shift register circuit can be improved. 
         [0047]    A thin film device (such as a complementary invertor circuit) used in the present invention will be described below. 
         [0048]    A silicon oxide film having a thickness of 1000 to 3000 Å is formed as a base oxide film on a glass substrate (a low alkaline glass such as Corning 7059 or a quartz glass) by sputtering in an atmosphere containing oxygen. To improve productivity, a film to be deposited by decomposing a tetra-ethyl-ortho-silicate (TEOS) in plasma chemical vapor deposition (CVD) may be used. 
         [0049]    An amorphous silicon film having a thickness of 300 to 5000 Å, preferably 500 to 1000 Å is deposited by plasma CVD and low pressure CVD (LPCVD) and then placed in a reducing atmosphere at 550 to 600° C. for 4 to 48 hours to crystallize it. After this process, crystallinity may be increased (improved) by laser irradiation. The crystallized silicon film is patterned to form island regions  1  and  2 . Further, a silicon oxide film  3  having a thickness of 700 to 1500 Å is formed on the island regions  1  and  2  by sputtering. 
         [0050]    An aluminum (containing Si of 1 weight % or Sc (scandium) of 0.1 to 0.3 weight %) film having a thickness of 1000 Å to 3 μm is formed by electron beam evaporation or sputtering. A photoresist (for example, a product of Tokyo Ohka Co. Ltd. OFPR800/30cp) is formed by spin coating. When an aluminum oxide film having a thickness of 100 to 1000 Å is formed on a surface thereof by anodization after formation of the photoresist, adhesion to the photoresist is high. Also, by suppressing a leak current from a photoresist, it is effective on formation of a porous anodic oxide in only side surface in a later anodization process. The photoresist and the aluminum film are patterned and etched to form gate electrodes  4  and  5  and mask films  6  and  7 . ( FIG. 10A ) 
         [0051]    The formed substrate is anodized by supplying a current in an electrolytic solution, to form an anodic oxide having a thickness of 3000 to 6000 Å, for example, 5000 Å. The anodization is performed using an acid solution containing citric acid, nitric acid, phosphoric acid, chromic acid, sulfuric acid, oxalic acid or the like of 3 to 20% by applying a voltage of 10 to 30 V to a gate electrode at a constant current. In the embodiment, the anodization is performed in an oxalic acid solution (30° C.) at 10 V for 20 to 40 minutes. A thickness of an anodic oxide is adjusted by an anodization time. ( FIG. 10B ) 
         [0052]    After that, the mask films are removed, and then a current is supplied to the gate electrodes in an electrolytic solution (ethylene glycol solution containing tartaric acid, boric acid, nitric acid of 3 to 10%) again. In order to obtain a superior oxide film, it is preferred that a temperature of the solution is about 10° C. and lower than a room temperature. As a result, barrier type anodic oxides  10  and  11  are formed in upper and side surfaces of the gate electrodes. Thicknesses of the anodic oxides  10  and  11  are proportional to an applied voltage. For example, when an applied voltage is 150 V, an anodic oxide having a thickness of 2000 Å is formed. Thicknesses of the anodic oxides  10  and  11  are determined by a necessary offset size. Although an anodic oxide having a thickness of 3000 Å or more is formed by applying 250 V or higher, since this influences TFT characteristics, it is desired that an anodic oxide having a thickness of 3000 Å or less is formed. In the embodiment, a voltage is increased until 80 to 150 V and selected by necessary thicknesses of the anodic oxides  10  and  11 . 
         [0053]    In this state, although a barrier type anodic oxide is formed by a later process, the barrier type anodic oxides  10  and  11  are formed between the porous anodic oxides  8  and  9  and the gate electrodes  4  and  5  without forming barrier type anodic oxides outside porous anodic oxides. 
         [0054]    An insulating film  3  is etched by dry etching or wet etching. A depth of etching is arbitrary. Etching may be performed until an active layer formed under the insulating film  3  is exposed. Etching may be stopped on halfway. However, it is desired to etch the insulating film  3  until an active layer is exposed, in mass productivity, yield and uniformity. In this state, insulating films  12  and  13  covered with the anodic oxides  8  and  9  and the gate electrodes  4  and  5  remain as a gate insulating film. ( FIG. 10C ) 
         [0055]    After that, the anodic oxides  8  and  9  are removed. It is preferred that a solution containing phosphoric acid, for example, a mixture acid containing phosphoric acid, acetic acid and nitric acid is used as an etchant. In using an etchant containing phosphoric acid, an etching rate of a porous anodic oxide is ten times or more as large as that of a barrier type anodic oxide. Therefore, since barrier type anodic oxides  10  and  11  are not etched substantially by the etchant containing phosphoric acid, the gate electrodes can be protected from etching. 
         [0056]    In such structure, a source and a drain are formed by implanting N-type or P-type impurity ion into an active layer. In a state wherein a left TFT region is covered with a mask  14 , a phosphorus ion is irradiated (introduced) by ion doping at a relatively low speed (an accelerating voltage of 5 to 30 kV, 20 kV in the embodiment). A doping gas is phosphine (PH 3 ). A dose is 5×10 14  to 5×10 15  cm −2 . In this process, since a phosphorus ion cannot be transmitted through the insulating film  13 , it is implanted into only region in which a surface is exposed, so that a drain  15  and a source  16  of an N-channel type TFT are formed. ( FIG. 10D ) 
         [0057]    Also, a phosphorus ion is irradiated by ion doping at a relatively high speed (an accelerating voltage of 60 to 120 kV, 90 kV in the embodiment). A dose is 1×10 13  to 5×10 14  cm −2 . In this process, a phosphorus ion is transmitted through the insulating film  13  and reaches a region formed under the film  13 . However, since a dose is small, N-type regions  17  and  18  each having a low concentration are formed. ( FIG. 10E ) 
         [0058]    After phosphorus doping, the mask is removed. Then, using the N-channel type TFT as a mask, as described above, a source  19 , a drain  20  and a P-type regions  21  and  22  each having a low concentration in a P-channel type TFT. A KrF excimer laser (wavelength of 248 nm and pulse width of 20 ns) is irradiated to activate an impurity ion introduced into an active layer. 
         [0059]    A silicon oxide film having a thickness of 3000 to 6000 Å is formed as an interlayer insulator  23  on a whole surface by CVD. Also, contact holes are formed in a source and a drain of a TFT and then aluminum wiring-electrodes  24  to  26  are formed. Further, hydrogen annealing is performed at 200 to 400° C. As a result, a complementary invertor circuit using TFTs is completed. ( FIG. 10F ) 
         [0060]    A shift register in the embodiment is formed in a basis of the above complementary invertor circuit. A shift register used in a driver circuit of an active matrix type display device and an active matrix circuit having pixel TFTs are formed on the same substrate. 
         [0061]    Referring with  FIG. 3 , an embodiment of the present invention will be described. 
         [0062]    In the embodiment, one main register line and one subregister line are used in each register group, and three registers are included in each register line. Also, the number of register groups is a positive integer and a multiple of three, for example. 
         [0063]    As shown in  FIG. 3 , a shift register circuit  135  includes register groups  130   a,  . . . ,  130   b.  The register group  130   a  includes a main register line  131   a  having registers SRN 1 , SRM 2  and SRM 3  and a subregister line  131   b  having registers SRS 1 , SRS 2  and SRS 3 . The register group  130   b  includes a main register line  131   c  having registers SRM N-2 , SRM N-1  and SRM N  and a subregister line  131   d  having registers SRS N-2 , SRS N-1  and SRS N . 
         [0064]    Register line selecting switches  133   a  and  133   b  are arranged to select the register lines in each register group. Defect detection terminals  134   a  and  134   b  are arranged to detect outputs of last registers of the register lines, so that whether or not each register line includes defect is detected. 
         [0065]    Register column selecting switches  132   a  to  132   f  are arranged to select registers included in the selected register lines in each register group. 
         [0066]    First, the main register line is examined by using the defect detection terminal in each register group. If the line is normal, the register line selecting switch is connected with the main register line. On the other hand, if the main register line has defect, the register line selecting switch is connected with the subregister line. 
         [0067]    A conventional shift register circuit is compared with a shift register circuit according to the present invention. 
         [0068]    In a conventional shift register circuit as shown in  FIG. 2 , when a defective rate per register is f n (0&lt;f n &lt;1) and the number of registers to be serial-connected is N (a positive integer and a multiple of three), a probability An which a conventional shift register circuit as shown in  FIG. 2  is operated normally is obtained by the following equation, 
         [0000]        An =(1− f   n ) N .
 
         [0069]    In a shift register circuit of the present invention, the same defective rate per register f n (0&lt;f n &lt;1) is used. Also, the number of registers when all registers of each register group in one line are connected in serial is used as N (a positive integer and a multiple of three). Further, each register line includes three registers. 
         [0070]    In this state, a probability Bn which one register group is not operated normally is obtained by the following equation, 
         [0000]        Bn={ 1−(1− f   n ) 3 } 2 .
 
         [0071]    Therefore, since the number of register groups is N/3, a probability Cn which a whole shift register circuit is operated normally is obtained by the following equation, 
         [0000]    
       
         
           
             
               
                 
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         [0072]    If F n =1−f n  and r=N/3 (r is a positive integer), 
         [0073]    An=F n   3r , and 
         [0074]    Cn=F n   3r  (2−F n   3 ) r . 
         [0075]    In this state, from 0&lt;f n &lt;1, 
         [0076]    0&lt;(1−f n )=F n &lt;1, and 
         [0077]    0&lt;F n   3 &lt;1. 
         [0078]    Therefore, 
         [0079]    1&lt;(2−F n   3 )&lt;2, and 
         [0080]    1&lt;(2−F n   3 &lt;2 r . 
         [0081]    From the above relationship, 
         [0082]    Cn−An=F n   3r {(2−F n   3 ) r −1}&gt;0. 
         [0083]    As a result, An&lt;Cn. 
         [0084]    When the number of registers included in a source driver circuit is  480  and a defective rate of register is 0.001, a probability An′ which a conventional source driver circuit is operated normally is 
         [0000]        An′ =(1−0.001) 480 =0.619.
 
         [0085]    On the other hand, a probability Cn′ which a redundancy source driver circuit according to the present invention is operated normally is 
         [0000]        Cn′=[ 1−{1−(1−0.001) 3 } 2 ] 480/3 =0.999.
 
         [0086]    Therefore, it is confirmed that An′&lt;Cn′. 
         [0087]    As described above, redundancy of a register line increases a probability which a shift register is operated normally. If a defective rate per register is the same, this relationship is always obtained without depending on the number of registers included in one register line, the number of register lines and the number of register groups. 
         [0088]    Structures of a register line selecting switch will be described below using  FIGS. 11A and 11B . 
         [0089]    The register line selecting switch includes bias circuit  90   a  to  90   g,  a priority encoder circuit  81  and a multiplexer circuit  82 . 
         [0090]    Output terminals of register lines  80   a  to  80   h  are connected with input terminals (X) of the multiplexer  82 . The bias circuits are arranged in correspondent to register lines each having an output terminal, and the output terminals are connected with input terminals (X) of the priority encoder circuit  81 . 
         [0091]    When outputs of the bias circuits are held, the priority encoder circuit  81  converts a bit position of L of bit string to be input into binary data and then outputs the binary data (bit string) form output terminals (Y) to input signal selecting terminals (S) of the multiplexer circuit  82  and input signal selecting terminals (S) of a multiplexer circuit  83  used as a register column selecting switch through invertor circuits. 
         [0092]    As described above, one of the register lines is selected using a register line selecting switch constructed by a combination of the priority encoder circuit  81 , the multiplexer circuit  82  and the bias circuits  90   a  to  90   g.    
         [0093]      FIG. 7A  shows an equivalent circuit of a 8 bit priority encoder circuit, and  FIG. 7B  shows an equivalent circuit of a 8 bit input multiplexer circuit. Also,  FIG. 12  shows a truth table of the priority encoder circuit of  FIG. 7A . 
         [0094]      FIG. 4  shows a case wherein two register lines  140   a  and  140   b  are used in one register group. Since the number of register lines is 2, it is not necessary to use a priority encoder circuit as described above. Therefore, outputs of all register lines  140   a  and  140   b  are connected with input terminals (X) of a multiplexer circuit  141  for register line selection. An output terminal of a bias circuit  144  is connected with an input signal selecting terminal (S) of the multiplexer circuit  141 . Defect detection terminals  143   a  and  143   b  are used to detect a register line having defect. 
         [0095]    When one of register line is normal, a low level (L) bias is supplied to the bias circuit  144  corresponding to the one of the register lines. Therefore, since a level of the input signal selecting terminal (S) of the multiplexer circuit  141  is determined, the multiplexer circuit  141  selects a normal register line, to use an output of a last register of the selected register line as an output of a register group having the selected register line. 
         [0096]    A structure of a register column selecting switch will be described below using  FIG. 4 . 
         [0097]    Register column selecting switches includes multiplexer circuits  142   a,  . . . , and  142   b,  respectively. Outputs of the registers SR 1  (SR n ) constructing each column are connected with input terminals (X) of the multiplexer circuits  142   a  ( 142   b ) for register column selection. To select a register in a column, an output of the bias circuit  144  is connected with input signal selecting terminals (s) of the multiplexer circuits  142   a  and  142   b.    
         [0098]    As described above, a register column selecting switch is constructed by a combination of the bias circuit  144  and the multiplexer circuits  142   a  and  142   b.    
         [0099]    A structure of a bias circuit will be described using  FIGS. 8A to 8C . 
         [0100]    In a bias circuit as shown in  FIG. 8A , a pull-up resistor is connected with a pull-down resistor in serial, and an output terminal and a cutting portion are provided between these resistors. A resistance value ratio between the pull-up resistor and the pull-down resistor is 100:1, and may be set in a range which a voltage level detected on the output terminal becomes a low level (L). 
         [0101]    A bias circuit corresponding to a normal register line holds a low level (L), and bias circuits corresponding to register lines other than the normal register line holds a high level (H) by cutting a cutting portion of the bias circuit using a laser to obtain a pull-up state. As a result, an input signal of the multiplexer circuit can be selected. 
         [0102]    In a bias circuit as shown in  FIG. 8B , an analog switch using an N-type TFT is used. As described above, a bias circuit corresponding to a normal register line holds a low level (L), and bias circuits corresponding to register lines other than the normal register line holds a high level (H) by cutting a cutting portion of the bias circuit using a laser to obtain a pull-up state. As a result, an input signal of the multiplexer circuit can be selected. 
         [0103]      FIG. 8C  shows cutting of a cutting portion of a bias circuit. The cutting portion may be cut by applying a high voltage to two foot prints. 
         [0104]    As shown in  FIGS. 11A and 11B , in a case wherein the number of register lines is n (n&gt;2), outputs of last registers of all register lines  80   a  to  80   n  are connect with input terminals (X) of a multiplexer circuit  82  for register line selection. Also, bias circuits  90   a  to  90   g  each having output terminals are arranged in correspondence to the register lines, and the output terminals of the bias circuits  90   a  to  90   g  are connected with input terminals (X) of the priority encoder circuit  81 . The output terminals of the priority encoder circuit  81  is connected with input signal selection terminals of the multiplexer circuit  82  through invertor circuits. 
         [0105]    When a normal register line is detected, an output of a bias circuit corresponding to the register line is held to a low level (L). An output of a bias circuit corresponding to the register line is held to a low level (L). Also, an output of a bias circuit corresponding to the register line other than the normal register line is held to a high level (H). As described above, outputs of the priority encoder circuit  81  are determined by holding output levels of the output terminals of the bias circuits. Therefore, since levels of input signal selection terminals of the multiplexer circuit  82  are determined, the multiplexer circuit  82  selects a normal register line, so that an output of a last register of the selected register line is input to an input terminal of an OR circuit  84 . An output of the OR circuit  84  is used as an input of next register group in a case wherein a plurality of register groups are arranged in a shift register circuit. 
         [0106]    A register column is defined at a column direction of registers of register lines. Multiplexer circuits for register column selection are arranged for each register column. The number of the multiplexer circuits for register column selection coincide with the number of registers of one register line. 
         [0107]    When a normal register line is selected in one register group, an output of the priority encoder circuit  81  is input to input signal selection terminals (S) of a multiplexer circuit  83  for register column selection through invertor circuits. Therefore, registers included in the selected register line are selected in a column direction, so that sample timing signals can be output to source lines of an active matrix type display device. 
         [0108]      FIG. 13  shows a case wherein two register lines  140   a  and  140   b  are used in one register group and a shift register circuit has only one register group. As shown in  FIG. 13 , a multiplexer circuit for register line selection can be omitted in comparison with  FIG. 4 . 
         [0109]    As described above, a normal register line is selected in each register group, and a shift register circuit is constructed by connecting with each register group each other. 
         [0110]    In the above embodiment, although a complementary type is used, a circuit using an N-channel type or a P-channel type may be constructed. In this state, since only one impurity doping process is performed, the number of forming processes can be decreased. 
         [0111]      FIGS. 9A to 9C  show shift register circuit constructed by only P-channel type.  FIG. 9A  shows an invertor circuit constructed using P-channel transistors and resistors. In  FIG. 9A , the invertor circuit includes an input terminal IT, a first thin film transistor (TFT)  1 , a second TFT  2 , a third TFT  3 , a fourth TFT  4 , and an output terminal OT. Here, a first terminal  1 T 1  of the first TFT  1  is electrically connected to the input terminal IT, and a second terminal  1 T 2  of the first TFT  1  is electrically connected to a first terminal  2 T 1  of the second TFT  2  and to a gate terminal  3 GT of the third TFT  3 . A first terminal  3 T 1  of the third TFT  3  is electrically connected to a first power source VDD, and a second terminal  3 T 2  of the third TFT  3  is electrically connected to a second power source GND via a first resistance element R 1 . A first terminal  4 T 1  of the fourth TFT  4  is electrically connected to the first power source VDD, and a second terminal  4 T 2  of the fourth TFT  4  is electrically connected to the second power source GND via a second resistance element R 2 . A second terminal  2 T 2  of the second TFT  2  is electrically connected to the second terminal  4 T 2  of the fourth TFT  4 , and the output terminal OT is electrically connected to the second terminal  3 T 2  of the third TFT  3  and to a gate terminal  4 GT of the fourth TFT  4 . In  FIG. 9A , a clock signal CK is inputted to a gate terminal  1 GT of the first TFT  1 , and an inverted clock signal  CK  is inputted to a gate terminal  2 GT of the second TFT  2 . In addition, each of the first, second, third, and fourth TFTs  1 ,  2 ,  3 , and  4  includes an active layer having a channel forming region comprising an impurity element have a same conductivity type, wherein the active layer comprises crystallized silicon. At least one of the first, second, third, and fourth TFTs  1 ,  2 ,  3 , and  4  has at least one lightly doped region formed using the gate electrode of the corresponding TFT as a mask. 
         [0112]      FIG. 9B  shows an invertor circuit constructed using P-channel transistors. In  FIG. 9B , the invertor circuit includes an input terminal IT, a first thin film transistor (TFT)  1 , a second TFT  2 , a third TFT  3 , a fourth TFT  4 , a fifth TFT  5 , a sixth TFT  6 , and an output terminal OT. Here, a first terminal  1 T 1  of the first TFT  1  is electrically connected to the input terminal IT, and a second terminal  1 T 2  of the first TFT  1  is electrically connected to a first terminal  2 T 1  of the second TFT  1  and to a gate terminal  3 GT of the third TFT  3 . A first terminal  3 T 1  of the third TFT  3  is electrically connected to a first power source VDD, and a second terminal  3 T 2  of the third TFT  3  is electrically connected to a second power source GDN and to a first terminal  5 T 1  of the fifth TFT  5 . A second terminal  5 T 2  of the fifth TFT  5  is electrically connected to a gate terminal  5 GT of the fifth TFT  5  and to a second power source GND. A first terminal  4 T 1  of the fourth TFT  4  is electrically connected to the first power source VDD, and a second terminal  4 T 2  of the fourth TFT  4  is electrically connected to the second power source GND and to a first terminal  6 T 1  of the sixth TFT  6 . A second terminal  6 T 2  of the sixth TFT  6  is electrically connected to a gate terminal  6 GT of the sixth TFT  6  and to the second power source GND. A second terminal  2 T 2  of the second TFT  2  is electrically connected to the second terminal  4 T 2  of the fourth TFT  4 , wherein the output terminal OT is electrically connected to the second terminal  3 T 2  of the third TFT  3  and to a gate terminal  4 GT of the fourth TFT  4 . In  FIG. 9B , a clock signal CK is inputted to a gate terminal  1 GT of the first TFT  1 , and an inverted clock signal  CK is inputted to a gate terminal  2 GT of the second TFT  2 . In addition, each of the first, second, third, fourth, fifth, and sixth TFTs  1 ,  2 ,  3 ,  4 ,  5 , and  6  includes an active layer having a channel forming region comprising an impurity element have a same conductivity type, wherein the active layer comprises crystallized silicon. At least one of the first, second, third, fourth, fifth, and sixth TFTs  1 ,  2 ,  3 ,  4 ,  5 , and  6  has at least one lightly doped region formed using the gate electrode of the corresponding TFT as a mask. 
         [0113]      FIG. 9C  shows a dynamic type shift register. In  FIG. 9C , the shift register includes an input terminal IT, a first thin film transistor (TFT)  1 , a second TFT  2 , a third TFT  3 , a fourth TFT  4 , a fifth TFT  5 , a sixth TFT  6 , and an output terminal OT. Here, a first terminal  1 T 1  of the first TFT  1  is electrically connected to the input terminal IT, and a gate terminal  2 GT of the second TFT  2  is electrically connected to a second terminal  1 T 2  of the first TFT  1 . A first terminal  2 T 1  of the second TFT  2  is electrically connected to a first power source VDD, and a first terminal  4 T 1  of the fourth TFT  4  is electrically connected to a second terminal  2 T 2  of the second TFT, to a first terminal  3 T 1  of the third TFT  3 , and to a second power source GND via a first capacitor C 1 . A first terminal  5 T 1  of the fifth TFT  5  is electrically connected to the first power source VDD, and a gate terminal  5 GT of the fifth TFT  5  is electrically connected to a second terminal  4 T 2  of the fourth TFT  4  and the second power source GND via a second capacitor C 2 . A first terminal  6 T 1  of the sixth TFT  6  is electrically connected to a second terminal  5 T 2  of the fifth TFT  5 , and the output terminal OT is electrically connected to the second terminal  6 T 2  of the sixth TFT  6  and to a second terminal  3 T 2  of the third TFT  3 . In  FIG. 9C , a clock signal CK is inputted to a gate terminal  1 GT of the first TFT  1  and to a gate terminal  3 GT of the third TFT  3 , and an inverted clock signal  CK  is inputted to a gate terminal  4 GT of the fourth TFT  4  and to a gate terminal  6 GT of the sixth TFT  6 . In addition, each of the first, second, third, fourth, fifth, and sixth TFTs  1 ,  2 ,  3 ,  4 ,  5 , and  6  includes an active layer having a channel forming region comprising an impurity element have a same conductivity type, wherein the active layer comprises crystallized silicon. At least one of the first, second, third, fourth, fifth, and sixth TFTs  1 ,  2 ,  3 ,  4 ,  5 , and  6  has at least one lightly doped region formed using the gate electrode of the corresponding TFT as a mask. 
         [0114]    A multiplexer circuit, a priority encoder circuit and like can be constructed using P-channel transistors and resistors. 
         [0115]    In the embodiment, although only P-channel type transistor is used, a N-channel type transistor can be used. 
         [0116]    According to the present invention, a defective rate of one register is constant and redundancy shift register circuit is used, so that a yield of a whole shift register circuit can be increased and reliability of a shift register circuit can be improved.