Abstract:
Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The. write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell.

Description:
REFERENCE TO PRIORITY APPLICATION 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0069002, filed Jul. 16, 2010, the entirety of which is hereby incorporated herein by reference. 
       BACKGROUND 
       [0002]    Semiconductor memory device are typically classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. 
         [0003]    Volatile memory devices include static random access memories (SRAMs) and dynamic random access memories (DRAMs), which are roughly categorized according to data storage schemes. That is, an SRAM stores data by using a latch while a DRAM stores data by using a capacitor. Especially, an SRAM is mainly used as a cache memory because its peripheral circuit is simple in configuration and its speed is high in spite of lower memory capacity resulting from lower integration density than a DRAM. 
         [0004]    The miniaturization of semiconductor devices is accelerating with the recent advance in semiconductor manufacturing processes, which involves increase in distribution of basic process characteristics of the semiconductor devices. For example, in an SRAM, miniaturization of semiconductor devices involves increase in distribution of characteristics required for design such as a write margin and a sense margin. As semiconductor manufacturing processes become finer, the increased distribution leads to difficulty in development of SRAMs and reduction in stability of memory cells. As a result, yield is reduced. 
       SUMMARY OF THE INVENTION 
       [0005]    Integrated circuit memory devices according to embodiments of the invention include a memory cell configured to receive a power supply signal (e.g., Vc) and a write assist circuit. This write assist circuit is configured to reduce a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. According to some additional embodiments of the invention, the memory device may also include at least one bit line electrically coupled to the memory cell and a read assist circuit. This read assist circuit may be configured to partially discharge the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell. 
         [0006]    According to additional embodiments of the invention, the write assist circuit is further configured to raise the power supply signal from the second voltage level to the first voltage level upon completion of the operation to write data into the memory cell. In addition, the read assist circuit, which may be responsive to a read assist control signal, may be configured to partially discharge the at least one bit line in response to a transition of the read assist control signal between unequal logic states (e.g., from logic 1→0). 
         [0007]    According to still further embodiments of the invention, the memory cell is a static random access memory (SRAM) cell containing a pair of PMOS pull-up transistors. The source terminals of the pair of PMOS transistors are configured to receive the power supply signal. This SRAM cell is responsive to a word line signal that is active during the operation to write data into the memory cell. The write assist circuit is also configured to hold the magnitude of the power supply signal at the second voltage level when the word line signal is active during the operation to write data into the memory cell. 
         [0008]    According to still further embodiments of the invention, a method of operating a static random access memory (SRAM) cell includes writing data into the SRAM cell by driving a word line of the SRAM cell with an active word line signal concurrently with reducing a voltage of a power supply signal received by the SRAM cell. In addition, to prepare for a reading operation, a pair of differential bit lines coupled to the SRAM cell may be precharged to equivalent precharged voltage levels. Thereafter, data may be read from the SRAM cell by partially discharging the precharged pair of differential bit lines in advance of driving the word line of the SRAM cell with the active word line signal. This reading operation may also include driving the word line of the SRAM cell with the active word line signal concurrently with sensing and amplifying a differential voltage established across the pair of differential bit lines using, for example, a sense amplifier. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The inventive concept will become more apparent in view of the attached drawings and accompanying detailed description. The embodiments depicted therein are provided by way of example, not by way of limitation, wherein like reference numerals refer to the same or similar elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating aspects of the inventive concept. 
           [0010]      FIG. 1  is a circuit diagram of a power supply circuit according to an example embodiment of the inventive concept. 
           [0011]      FIG. 2  is a timing diagram illustrating the operation of the power supply circuit shown in  FIG. 1 . 
           [0012]      FIG. 3  is a circuit diagram of a static random access memory device including a write assist circuit according to an example embodiment of the inventive concept. 
           [0013]      FIG. 4  is a timing diagram illustrating the operation of the write assist circuit shown in  FIG. 3 . 
           [0014]      FIG. 5  is a circuit diagram of a static random access memory device including a read assist circuit according to another example embodiment of the inventive concept. 
           [0015]      FIG. 6  is a timing diagram illustrating the operation of the read assist circuit shown in  FIG. 5 . 
           [0016]      FIG. 7  is a block diagram of a static random access memory device including a read assist circuit and a write assist circuit according to an example embodiment of the inventive concept. 
           [0017]      FIG. 8  is a block diagram of a user device including a static random access memory device according to an example embodiment of the inventive concept. 
           [0018]      FIG. 9  is a block diagram of a computer system including a static random access memory device according to an example embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0019]    The advantages and features of the inventive concept and methods of achieving them will be apparent from the following exemplary embodiments that will be described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concept and let those skilled in the art know the category of the inventive concept. In the drawings, embodiments of the inventive concept are not limited to the specific examples provided herein and may be exaggerated for clarity. Furthermore, the same reference numerals denote the same elements throughout the specification. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0020]      FIG. 1  is a circuit diagram of a power supply circuit  100  according to an example embodiment of the inventive concept. As illustrated, the power supply circuit  100  includes a first PMOS transistor P 1  and a second PMOS transistor P 2 . The first PMOS transistor P 1  is coupled between a voltage input terminal to which an input voltage V IN  is applied and a voltage output terminal to which an output voltage V OUT  is output. The second PMOS transistor P 2  is coupled between a control signal input terminal to which a control signal CTRL is applied and the voltage output terminal from which an output voltage V OUT  is output. A ground voltage (or another appropriate reference voltage) may be applied to a gate of each of the first and second PMOS transistors P 1  and P 2 . If necessary, the gates of the first and second PMOS transistors P 1  and P 2  may be connected to each other and a ground voltage (or another appropriate reference voltage) may be applied to the connected gates. 
         [0021]    The power supply circuit  100  according to an example embodiment of the inventive concept includes a multi-purpose PMOS driver. That is, the second PMOS transistor P 2  functions as the multi-purpose PMOS driver. The second PMOS transistor P 2  may function as either one of a discharger and a precharger according to the control signal CTRL applied to the control signal input terminal. For example, the second PMOS transistor P 2  may function as a discharger when a control signal CTRL of logic ‘low’ level is applied. Meanwhile, the second PMOS transistor P 2  may act as a precharger when a control signal CTRL of logic ‘high’ level is applied. 
         [0022]    The output voltage V OUT  output from the voltage output terminal of the power supply circuit  100  is controlled according to an operation scheme of the second PMOS transistor P 2 . For example, as describe above, the second PMOS transistor P 2  may function as a discharger when the control signal CTRL of logic ‘low’ level is applied to the control signal input terminal. In this case, the output voltage V OUT  output from the output terminal of the power supply circuit  100  may be output after being reduced by a predetermined voltage by the second PMOS transistor P 2 . On the other hand, as described above, the second PMOS transistor P 2  may function as a precharger when the control signal CTRL of logic ‘high’ level is applied to the control signal input terminal. In this case, the output voltage V OUT  output from the output terminal of the power supply circuit  100  may be generated by not only an input voltage V IN  transferred through the first PMOS transistor P 1  but also a control signal CTRL transferred through the second PMOS transistor P 2 . 
         [0023]      FIG. 2  is a timing diagram illustrating the operation of the power supply circuit  100  shown in  FIG. 1 . The operation of the power supply circuit  100  will be described in further detail below with reference to  FIGS. 1 and 2 . The power supply circuit  100  according to embodiments of the inventive concept includes a first PMOS transistor P 1  and a second PMOS transistor P 2 . Since a ground voltage is applied to a gate of each of the first and second PMOS transistors P 1  and P 2 , the first and second PMOS transistors P 1  and P 2  may be in a turn-on state. Thus, an output voltage V OUT  output from an output terminal of the power supply circuit  100  is controlled according to an input voltage V IN  input to a voltage input terminal and a control signal CTRL applied to a control signal input terminal. Hereinafter, the operation of the power supply circuit  100  will be described under the assumption that the input voltage V IN  input to the voltage input terminal of the power supply circuit  100  is maintained at a constant voltage level. 
         [0024]    Since the input voltage V IN  of the power supply circuit  100  is maintained at a constant voltage value, the output voltage V OUT  of the power supply circuit  100  is controlled according to the control signal CTRL. As shown at a period “t 1 ” in  FIG. 2 , the input voltage V IN  of the power supply voltage  100  is output to the voltage output terminal through the first PMOS transistor P 1  when the control signal CTRL of logic ‘low’ level is applied to the control signal input terminal. However, the input voltage V IN  of the power supply voltage  100  may be output after being reduced by a predetermined voltage level ΔV. The predetermined voltage level ΔV may be determined according to current driving characteristics (and threshold voltage) of the second PMOS transistor P 2 . Thus, the second PMOS transistor P 2  functions as a discharger configured to reduce the output voltage V OUT  of the power supply circuit  100  by the predetermined voltage level ΔV. 
         [0025]    Meanwhile, as shown at a period “t 2 ” in  FIG. 2 , the output voltage V OUT  of the power supply voltage  100  is also generated by the input voltage V IN  transferred through the first PMOS transistor P 1  when the control signal CTRL of a ‘high’ level is applied. In addition, the output voltage V OUT  of the power supply voltage  100  is also generated by the control signal CTRL transferred through the second PMOS transistor P 2  when the control signal CTRL of logic ‘high’ level is applied. That is, the output voltage V OUT  of the power supply voltage  100  is generated by a voltage V 1  transferred through the first PMOS transistor P 1  and a voltage V 2  transferred through the second PMOS transistor P 2 . Thus, the second PMOS transistor P 2  functions as a sub-precharger to stabilize the output voltage V OUT  of the power supply voltage  100 . 
         [0026]    Because the second PMOS transistor P 2  may function as a sub-precharger, the output voltage V OUT  may be stably output even if current driving capability of the first PMOS transistor P 1  decreases. This means that a size of the first PMOS transistor P 1  may decrease. That is, the size of the first PMOS transistor P 1  may decrease because the second PMOS transistor P 2  may function as a sub-precharger. 
         [0027]    As set forth above, the second PMOS transistor P 2  functions as either one of a discharger and a precharger according to the control signal CTRL applied to the control signal input terminal. Therefore, the second PMOS transistor P 2  functions as a multi-purpose PMOS transistor having two purposes of a discharger and a precharger. The output voltage V OUT  output from the voltage output terminal of the power supply circuit  100  is controlled according to an operation scheme of the second PMOS transistor P 2 . 
         [0028]    According to embodiments of the inventive concept, a ground voltage is commonly applied to a gate of each of the first and second PMOS transistors P 1  and P 2  of the power supply circuit  100 . Moreover, the second PMOS transistor P 2  functions as either one of a discharger and a precharger according to a control signal applied to a control signal input terminal. However, it will be understood that an output voltage V OUT  output from a voltage output terminal may be controlled according to a gate voltage applied to a gate of each of the first and second PMOS transistors P 1  and P 2  and a control signal applied to a control signal input terminal of the second PMOS transistor P 2 . 
         [0029]      FIG. 3  is a circuit diagram of a static random access memory device  200  including a write assist circuit according to an example embodiment of the inventive concept. Referring to  FIG. 3 , the static random access memory device  200  includes a write assist (WASS) circuit  210 , a WASS control signal generating circuit  220 , a precharge circuit  230 , a control logic  240 , and a memory cell  250 . The static random access memory device  200  stores data by using a latch-type memory cell  250  including six transistors. That is, the memory cell  250  may be a full-CMOS type SRAM cell including two pull-up transistors PU and PUB, two pull-down transistors PD and PDB, and two pass transistors PG and PGB. However, it will be understood that the memory cell  250  is not limited to a latch-type memory cell  250  including six transistors. For example, the memory cell  250  may be a high load resistor (LHR) type memory cell or a thin film transistor (TFT) type memory cell according to elements constituting pull-up transistors. 
         [0030]    The memory cell  250  is connected to a wordline WL and a bitline pair (BL and BLB) that is a data input/output path. The memory cell  250  includes a first pass transistor PG, a second pass transistor PGB, and a latch circuit  255 . A gate of the first pass transistor PG is connected to the wordline WL and a first terminal thereof is connected to a bitline BL. The first pass transistor PG connects a bitline BL and a first data storage node Q to each other when the wordline WL is activated to a logic ‘high’ level. A gate of the second pass transistor PGB is connected to the wordline WL and a first terminal thereof is connected to the bitline BLB. The second pass transistor PGB connects the bitline BLB and a second data storage node QB to each other when the wordline WL is activated to a logic ‘high’ level. The latch circuit  255  is coupled between the first pass transistor PG and the second pass transistor PGB and stores data. 
         [0031]    The latch circuit  255  storing data includes a first pull-up transistor PU, a second pull-up transistor PUB, a first pull-down transistor PD, and a second pull-down transistor PDB. A first terminal of the first pull-up transistor PU is applied with a power supply voltage V C  of a memory cell and a second terminal thereof is connected to a second terminal of the first pass transistor PG. A first terminal of the first pull-down transistor PD is connected to a second terminal of the first pass transistor PG and a second terminal thereof is applied with a ground voltage. The first pull-up transistor PU and the first pull-down transistor PD are each controlled by a signal of the second data storage node QB to supply the power supply voltage V C  or the ground voltage to the first data storage node Q. A first terminal of the second pull-up transistor PUB is applied with a power supply voltage V C  of a memory cell and a second terminal thereof is connected to a second terminal of the second pass transistor PGB. A first terminal of the second pull-down transistor PGB is connected to a second terminal of the second pass transistor PGB and a second terminal thereof is applied with a ground voltage. The second pull-up transistor PUB and the second pull-down transistor PDB are each controlled by a signal of the first data storage node Q to supply the power supply voltage or the ground voltage Vc to the second data storage node QB. 
         [0032]    The amount of current flowing through the first and second pull-up transistors PU and PUB is necessarily reduced to improve a write margin of the memory cell  250 . The amount of current flowing through the first and second pull-up transistors PU and PUB is controlled by a power supply voltage level V C  of a memory cell. That is, according to the embodiment of the inventive concept, the power supply voltage level V C  of a memory cell is controlled by the write assist circuit  210  such that the memory cell  250  operates stably during a write operation. For example, the write assist circuit  210  may lower the power supply voltage level V C  of a memory cell. The precharge circuit  230  precharges a power supply voltage supply terminal of the memory cell  250 . The precharge circuit  230  includes a first PMOS transistor WAP 1 , which is coupled between a power supply voltage (V DD ) input terminal and a power supply voltage (V C ) supply terminal of a memory cell. A gate of the first PMOS transistor WAP 1  is applied with a ground voltage. The write assist circuit  210  includes a second PMOS transistor WAP 2 , which is coupled between the power supply voltage (V C ) supply terminal of a memory cell and a write assist control signal (WASS_E) input terminal. Similar to the first PMOS transistor WAP 1 , a gate of the second PMOS transistor WAP 2  is applied with a ground voltage. The second PMOS transistor WAP 2  may function as either one of a discharger and a precharger according to the control signal WASS_E applied to a write assist control signal (WASS_E) input terminal. For example, the second PMOS transistor WAP 2  may function as a discharger when the control signal WASS_E of logic ‘low’ level is applied. Meanwhile, the second PMOS transistor WAP 2  may function as a precharger when the control signal WAS S_E of logic ‘high’ level is applied. This operation of the second PMOS transistor WAP 2  will be described below in detail with reference to  FIG. 4 . 
         [0033]      FIG. 4  is a timing diagram illustrating the operation of the write assist circuit shown in  FIG. 3 . Referring to  FIGS. 3 and 4 , the first and second PMOS transistors WAP 1  and WAP 2  are in a turn-on state because their gates are each applied with a ground voltage. Thus, the power supply voltage V C  of the memory cell  250  is controlled according to a power supply voltage V DD  input to a power supply voltage (V DD ) input terminal of the precharge circuit  230  and a write assist control signal WASS_E input to a write assist control signal (WASS_E) input terminal of the write assist circuit  210 . Hereinafter, the operation of the write assist circuit  210  will be described below under the assumption that the power supply voltage V DD  is maintained at a constant voltage level. 
         [0034]    The power supply voltage V C  of the memory cell  250  is controlled according to the write assist control signal WASS_E because the power supply voltage V DD  input to the power supply voltage (V DD ) input terminal of the precharge circuit  230  is maintained at a constant voltage level. For a write operation period in which a wordline WL is activated to a logic ‘high’ level, the power supply voltage supply terminal of the memory cell  250  is precharged to the power supply voltage V DD  by the first PMOS transistor WAP 1 . At the same time, the control logic  240  activates the write assist control signal WASS_E. When the write assist control signal WASS_E is activated (e.g., the write assist control signal WASS_E of logic ‘low’ level is applied to the write assist control signal), the second PMOS transistor WAP 2  functions as a discharger. A part of the current flowing through the first PMOS transistor WAP 1  flows through the second PMOS transistor WAP 2  remaining in a turn-on state after being divided. Thus, the power supply voltage V C  decreases by a predetermined voltage level ΔV W  due to the second PMOS transistor WAP 2 . 
         [0035]    The decreased amount ΔV W  of the power supply voltage V C  of a memory cell may be determined according to current driving capability of the first and second PMOS transistors WAP 1  and WAP 2 . For example, assuming that the current driving capability of the first PMOS transistors WAP 1  is constant, the decreased amount ΔV W  of the power supply voltage V C  of a memory cell may increase as the current driving capability of the second PMOS transistor WAP 2  becomes greater (e.g., the second PMOS transistor WAP 2  increases in width and decreases in length). 
         [0036]    According to the embodiment of the inventive concept, the second PMOS transistor WAP 2  controls a power supply voltage level V C  of a memory cell to be lower than a power supply voltage level V DD  during a write operation. Thus, the static random access memory device  200  according to the embodiment of the inventive concept may lower the power supply voltage level V C  of a memory cell by using the second PMOS transistor WAP 2  in spite of the use of a single power supply. Since the amount of current flowing through the first and second pull-up transistors PU and PUB decreases according to the lowered power supply voltage level V C  of a memory cell, a write margin of the memory cell may be improved. 
         [0037]    For a period in which the write assist circuit  210  is inactivated (e.g., write operation and a standby operation), the control logic  240  inactivates the write assist control signal WASS_E. When the write assist control signal WASS_E is inactivated (e.g., a write assist control signal WASS_E of logic ‘high’ level is applied to a write assist control signal input terminal), the second PMOS transistor WAP 2  functions as a precharger. The power supply voltage supply terminal of the memory cell  250  is precharged by a voltage V WAP1  generated by current flowing through the first PMOS transistor WAP 1  and a voltage V WAP2  generated by current flowing through the second PMOS transistor WAP 2 . That is, the internal voltage level V C  of the memory cell  250  is maintained at the power supply voltage level V DD  by the first and second PMOS transistors WAP 1  and WAP 2 . 
         [0038]    Since the second PMOS transistor WAP 2  functions as a sub-precharger, the power supply voltage level V C  of the memory cell  250  is stably maintained at the power supply voltage level V DD . That is, the power supply voltage level V C  of the memory cell  250  may be stably maintained by the second PMOS transistor WAP 2  even if the current driving capability of the first PMOS transistor WAP decreases. As the second PMOS transistor WAP is used, the size of the first PMOS transistor WAP 1  may decrease. For the brevity of description, the memory cell  250  and the write assist circuit  210  connected to one bitline pair have been exemplarily described in  FIG. 3 . However, the static random access memory device  200  shown in  FIG. 3  may include a plurality of memory cells connected to a plurality of bitline pairs. Moreover, a write assist circuit may be configured at the respective bitline pairs. The bitline pairs are controlled by a column address for selecting a memory cell. For example, a memory cell to read data during a read operation or a memory cell in which data is to be stored is controlled by a corresponding bitline according to the column address. In addition, as set forth above, the assist circuit is activated during a write operation and inactivated during a read operation and a standby operation. 
         [0039]    Accordingly, the control logic  240  applies a write operation signal WR and a write assist operation signal WASS to the WASS control signal generating circuit  220  to activate a write assist circuit only during a write operation. In addition, a bitline selection signal BL_SEL depending on a column address is applied to the WASS control signal generating circuit  220  to activate only a write assist circuit connected to a selected memory cell where a write operation is performed. 
         [0040]    When the write operation signal WR, the write assist operation signal WASS, and the bitline selection signal BL_SEL are activated, the WASS control signal generating circuit  220  outputs the write assist control signal WASS_E to operate the corresponding write assist circuit. As a result, during a write operation, only the assist circuit connected to a memory cell where the write operation is performed is activated while a write assist circuit connected to an unselected memory cell is inactivated. 
         [0041]      FIG. 5  is a circuit diagram of a static random access memory device  300  including a read assist circuit according to another example embodiment of the inventive concept. As illustrated, the static random access memory device  300  includes a read assist circuit  310 , a bitline precharge circuit  330 , and a memory cell  350 . The configuration and operation of the memory cell  350  are identical to those described in  FIG. 3  and will not be described in further detail. The bitline precharge circuit  330  includes a first PMOS transistor RPP 1 , a second PMOS transistor RPP 2 , and a third PMOS transistor RPP 3 . The bitline precharge circuit  330  is coupled between a bitline pair (BL and BLB) and a power supply voltage V DD  input terminal to which a power supply voltage V DD  is applied. That is, a precharge control signal PCH is applied to a gate terminal of each of the first and second PMOS transistors RPP 1  and RPP 2 . A first terminal of the first PMOS transistor RPP 1  is applied with the power supply voltage (V DD ) and a second terminal thereof is connected to the bitline BLB. The precharge control signal PCH is applied to a gate of the third PMOS transistor RPP 3 . A first terminal of the third PMOS transistor RPP 3  is connected to the bitline BL and a second terminal thereof is connected to the bitline BLB. 
         [0042]    The first PMOS transistor RPP 1  precharges the bitline BL to a predetermined voltage level (e.g., power supply voltage level V DD ) in response to the precharge control signal PCH. The second PMOS transistor RPP 2  precharges the bitline BLB to a predetermined voltage level (e.g., power supply voltage level V DD ) in response to the precharge control signal PCH. The third PMOS transistor RPP 3  connects the bitline BL and the bitline BLB to each other in response to the precharge control signal PCH. That is, the third PMOS transistor RPP 3  makes the bitline BL and the bitline BLB maintained at the same voltage level when it is turned on by the precharge control signal PCH. 
         [0043]    The read assist circuit  310  includes a first PMOS transistor RAP 1  and a second PMOS transistor RAP 2 . A control signal PCH is applied to a gate of each of the first and second PMOS transistors RAP 1  and RAP 2 . A first terminal of the first PMOS transistor RAP 1  is connected to a second terminal of the first PMOS transistor RPP 1  and the bitline BL. A first terminal of the second PMOS transistor RAP 2  is connected to a second terminal of the second PMOS transistor RPP 2  of the bitline precharge circuit  330  and the bitline BLB. A read assist control signal RASS_E is applied to the second terminal of each of the first and second PMOS transistors RAP 1  and RAP 2 . 
         [0044]    The amount of current flowing through the first pass transistor PG and the second pass transistor PGB is necessarily reduced to improve a read margin of the memory cell  350 . The amount of current flowing through the first pass transistor PG may be controlled by the level of a precharge voltage to precharge the bitline BLB. That is, when the precharge voltage level at which the bitline BL and the bitline BLB are precharged decreases, the amount of current flowing through the first pass transistor PG and the second pass transistor PGB may also decrease. 
         [0045]    According to the embodiment of the inventive concept, during a read operation in which data is read from the memory cell  350 , the precharge voltage levels of the bitline BL and the bitline BL are controlled by the read assist circuit  310  to stably operate the memory cell  350 . For example, the read assist circuit  310  may decrease the precharge voltage levels of the bitline BL and the bitline BLB. 
         [0046]    The first and second PMOS transistors RAP 1  and RAP 2  of the read assist circuit  310  may function as either one of a discharger and a precharger according to the control signal RASS_E applied to a read assist control signal (RASS_E) input terminal. For example, the first and second PMOS transistors RAP 1  and RAP 2  may function as a discharger when the control signal RASS_E of logic ‘low’ level is applied. Meanwhile, the first and second PMOS transistors RAP 1  and RAP 2  may function as a precharger when the control signal RASS_E of logic ‘high’ level is applied. This operation of the first second PMOS transistors RAP 1  and RAP 2  will be described below in detail with reference to  FIG. 6 . 
         [0047]      FIG. 6  is a timing diagram illustrating the operation of the read assist circuit  310  shown in  FIG. 5 . Referring to  FIGS. 5 and 6 , during a read operation, a control logic (not shown) of the static random access memory device  300  activates the precharge control signal for a precharge period of the bitline pair (BL and BLB). When the precharge control signal PCH is activated (e.g., the precharge signal PCH of logic ‘low’ level is applied to a signal input terminal, all the transistors RPP 1 ˜RPP 3  of the bitline precharge circuit  330  and all the transistors RAP 1  and RAP 2  of the write assist circuit  310  are turned on. The control logic (not shown) inactivates the read assist control signal RASS_E for the precharge period of the bitline pair (BL and BLB). The read assist control signal RASS_E may be an inverted version of a read control signal generated by the control logic (not shown) during a read operation. When the read assist control signal RASS_E is inactivated (e.g., the read assist control signal RASS_E of logic ‘high’ level is applied to a read assist control signal input terminal), the first and second PMOS transistors RAP 1  and RAP 2  of the read assist circuit  310  function as a precharger. 
         [0048]    The bitline BL is precharged by a voltage V RPP1  generated by current flowing through the first PMOS transistor RPP 1  of the bitline precharge circuit  330  and a voltage V RAP1  generated by current flowing through the first PMOS transistor RAP 1  of the read assist circuit  310 . The bitline BLB is precharged by a voltage generated by current flowing through the second PMOS transistor RPP 2  of the bitline precharge circuit  330  and a voltage generated by current flowing through the second PMOS transistor RAP 2  of the read assist circuit  310 . 
         [0049]    Since the bitline BL and the bitline BLB are identical in precharge voltage level, the voltage V RPP1  generated by current flowing through the first PMOS transistor RPP 1  of the bitline precharge circuit  330  may be identical to the voltage generated by current flowing through the second PMOS transistor RPP 2  of the bitline precharge circuit  330 . In addition, the voltage V RAP1  generated by current flowing through the first PMOS transistor RAP 1  of the read assist circuit  310  may be identical to the voltage generated by current flowing through the second PMOS transistor RAP 2  of the read assist circuit  310 . Therefore, for the brevity of description, the operation of the first PMOS transistor RPP 1  of the bitline precharge circuit  330  and the operation of the first PMOS transistor RAP 1  of the read assist circuit  310  will be described hereinafter. 
         [0050]    Since The first PMOS transistor RAP 1  of the read assist circuit  310  function as a sub-precharger, a bitline voltage level V BL  is stably maintained. That is, the bitline voltage V BL  may be stably maintained by the first PMOS transistor RAP 1  of the read assist circuit  310  even if the current driving capability of the first PMOS transistor RPP 1  of the bitline precharge circuit  330  decreases. Thus, the dimension of the first PMOS transistor RPP 1  of the bitline precharge circuit  330  may be reduced by the first PMOS transistor RAP 1  of the read assist circuit  310 . 
         [0051]    The control logic (not shown) of the static random access memory device  300  performs an operation of decreasing a bitline voltage before activating a wordline WL to read data of the memory cell  350 . Since the precharge control signal PCH is activated in advance, the first PMOS transistor RPP 1  of the bitline precharge circuit  330  and the first PMOS transistor RAP 1  of the read assist circuit  310  may be in a turn-on state. Thus, a precharge voltage level V BL  of the bitline BL is controlled according to the power supply voltage V DD  input to the power supply voltage (V DD ) input terminal of the bitline precharge circuit  330  and the read assist control signal WASS_E applied to the read assist control signal (WASS_E) input terminal of the read assist circuit  310 . Hereinafter, the operation of the read assist circuit  310  will be described under the assumption that the power supply voltage V DD  is maintained at a constant voltage level. 
         [0052]    Since the power supply voltage V DD  input to the power supply voltage (V DD ) input terminal of the bitline precharge circuit  330  is maintained at a constant voltage level, the precharge voltage level V BL  of the bitline BL is controlled according to the read assist control signal RASS_E. When the read assist control signal RASS_E is activated (e.g., the read assist control signal RASS_E of logic ‘low’ level is applied to the read assist control signal input terminal), the first PMOS transistor RAP 1  of the read assist circuit  310  functions as a discharger. A part of the current flowing through the first PMOS transistor RPP 1  of the bitline precharge circuit  330  flows through the first PMOS transistor RAP 1  of the read assist circuit  310  remaining in a turn-on state after being divided. Thus, the bitline voltage level V BL  decreases by a predetermined voltage level ΔV R  due to the first PMOS transistor RAP 1  of the read assist circuit  310 . 
         [0053]    The decreased amount ΔV R  of the bitline voltage level V BL  may be determined by the current driving capability of the first PMOS transistor RPP 1  of the bitline precharge circuit  330  and the first PMOS transistor RAP 1  of the read assist circuit  310 . For example, assuming that the current driving capability of the first PMOS transistor RPP 1  of the bitline precharge circuit  330  is constant, the decreased amount ΔV R  of the bitline voltage level V BL  may increase as the current driving capability of the first PMOS transistor RAP 1  of the read assist circuit  310  becomes greater (e.g., the first PMOS transistor RAP 1  increases in width and decreases in length). 
         [0054]    According to the embodiment of the inventive concept, during a read operation, the read assist circuit  310  controls the precharge circuit  330  to lower the precharge voltage precharging the bitline pair (BL and BLB). Thus, the static random access memory device  300  according to the embodiment of the inventive concept may decrease a precharge voltage of a bitline by using the first and second PMOS transistors RAP 1  and RAP 2  in spite of the use of a single power. Since the amount of current flowing through the first and second pass transistors PG and PGB decreases according to the decreased precharge voltage of a bitline, a read margin of the memory cell  350  may be improved. 
         [0055]    For a period in which the read assist circuit  310  is inactivated (e.g., a write operation and a standby operation), the control logic (not shown) of the static random access memory device  300  inactivates the read assist control circuit RASS_E. When the read assist control signal RASS_E is inactivated (e.g., the read assist control signal RASS_E of logic ‘high’ level is applied to the read assist control signal input terminal), the first and second PMOS transistors RAP 1  and RAP 2  of the read assist circuit  310  operates the same as for a precharge period a read operation. That is, for the period in which the read assist circuit  310  is inactivated (e.g., a write operation or a standby operation), the first and second PMOS transistors RAP 1  and RAP 2  of the read assist circuit  310  function as a precharger. 
         [0056]      FIG. 7  is a block diagram of a static random access memory device  400  including a read assist circuit and a write assist circuit according to an example embodiment of the inventive concept. As illustrated, the static random access memory device  400  includes a control logic  410 , a row decoder  420 , a column decoder  425 , a sense amplifier and write driver  430 , a memory cell array  450 , a write assist circuit  460 , a bitline precharge circuit  470 , and read assist circuit  480 . The control logic  410  controls an overall operation of the static random access memory device  400  in response to control signals /CS, /OE, and /WE and an address ADD of an external device (e.g., a host, a memory controller or a memory interface). For example, the control logic  410  controls read and write operations of the static random access memory device  400 . Moreover, the control logic  410  controls the write assist circuit  460  to be activated during the write operation. In addition, the control logic  410  controls the read assist circuit  480  to be activated during the read operation. 
         [0057]    The row decoder  420  selects one of a plurality of wordlines WL 0 ˜WLm in response to a row address. The column decoder  425  selects one of a plurality of bitline pairs BL 0 ˜BLn and BLB 0 ˜BLBn in response to a column address. The sense amplifier and write driver  430  outputs and receives data through a data input/output buffer (not shown). The sense amplifier  430  amplifies a difference in voltage between bitlines connected to a selected one of a plurality of memory cells to read data stored in the selected memory cell. The read data is output to an external entity of the static random access memory device  400  through the data input/output buffer. The write driver  430  programs data input to the selected memory cell through the data input/output buffer. Such as operation of the sense amplifier and write driver  430  is performed according to the control of the control logic  410 . 
         [0058]    The memory cell array  450  includes a plurality of cells for storing data. The memory cells are connected to each of the wordlines WL 0 ˜WLm and are each coupled between the bitlines BL 0 ˜BLn and the bitlines BLB 0 ˜BLBn. During a write operation, the write assist circuit  460  is activated according to a control signal WASS_E of the control logic  410  to decrease a power supply voltage level of a memory cell. During the write operation, the read assist circuit  480  is inactivated according to the control signal WASS_E of the control logic  410  to stably precharge a selected bitline pair. Meanwhile, during a write operation, the write assist circuit  460  is inactivated according to the control signal WASS_E of the control logic  410  to stably precharge an internal voltage level of a memory cell. During the write operation, the read assist circuit is activated according to the control signal WASS_E of the control logic  410  to decrease a precharge voltage precharging a bitline pair. Although not shown in the figure, it will be understood that the write assist circuit  460  and the read assist circuit  480  is connected to the respective bitlines pairs BL 0 ˜BLn and BLB 0 ˜BLBn. 
         [0059]      FIG. 8  is a block diagram of a user device  2000  including a static random access memory device according to an example embodiment of the inventive concept. As illustrated, the user device  2000  includes a memory controller  2200  and a nonvolatile memory device. The user device  2000  includes a plurality of nonvolatile memory devices  2900 . The memory controller  2200  is connected to a host  2100  and the nonvolatile memory devices  2900 . The memory controller  2200  is configured to access the nonvolatile memory devices  2900  in response to a request from the host  2100 . For example, the memory controller  2200  is configured to control read, write, and erase operations of the nonvolatile memory devices  2900 . The memory controller  2200  is configured to provide an interface between the nonvolatile memory devices  2900  and the host  2100 . The memory controller  2200  is configured to drive a firmware for controlling the nonvolatile memory devices  2900 . 
         [0060]    The memory controller  2200  includes well-known elements such as a random access memory (RAM), a central processing unit (CPU), a host interface, an error connection code block (ECC), and a memory interface. The CPU  2400  may include a random access memory device  2450  according an embodiment of the inventive concept. The RAM  2600  may be used as a working memory of the CPU  2400 . The static random access memory device  2450  may be used as a cache memory of the CPU  2400 . The CPU  2400  controls an overall operation of the memory controller  2200 . The host interface  2300  may include a protocol for data exchange between the host  2100  and the memory controller  2200 . For example, the memory controller  2200  may be configured to communicate with an external entity (e.g., host) through one of various types of protocols such as USB(Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnection) protocol, PCI-E (PCI-Express) protocol, ATA (Advanced Technology Attachment) protocol, SATA (Serial ATA) protocol, SCSI (Small Computer Small Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, and IDE (Integrated Drive Electronics) protocol. 
         [0061]    An error correction code block (ECC)  2700  may be configured to detect an error of data read from the nonvolatile memory devices  2900  and correct the detected error. The ECC  2700  may be provided as an element of the memory controller  2200 . Alternatively, the ECC  2700  may be provided as an element of each of the nonvolatile memory devices  2900 . The memory interface  2500  may provide interfacing between the nonvolatile memory devices  2900  and the memory controller  2200 . 
         [0062]    It will be understood that elements of the memory controller  2200  are not limited to the foregoing elements. For example, the memory controller  2200  may further include a read only memory (ROM) storing code data required for an initial booting operation and data for interfacing with the host  2100 . 
         [0063]    The memory controller  2200  and the nonvolatile memory devices  2900  may be integrated into one semiconductor device to constitute a memory card. For example, the memory controller  2200  and the nonvolatile memory devices  2900  may be integrated into one semiconductor device to constitute a personal computer memory card international association (PCMCIA) card, a compact flash (CF) card, a smart media card, a memory stick, a multimedia card (e.g., MMC, RS-MMC, and MMC-micro), a secure digital (SD) card (e.g., SD, Mini-SD, Micro-SD, and SDHC) or a universal flash storage (UFS). 
         [0064]    As another example, the memory controller  2200  and the nonvolatile memory devices  2900  may be applied to solid state drives (SSDs), computers, portable computers, laptop computers, ultra mobile personal computers (UMPCs), net-books, personal digital assistants (PDAs), web tablets, wireless phones, mobile phones, smart phones, digital cameras, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, devices capable of transmitting/receiving information in wireless environments, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, one of various components constituting a computing system, radio frequency identification (RFID) devices or embedded systems. 
         [0065]    The CPU  2400  of the user device  2000  may include a static random access memory device  2450  according to the embodiment of the inventive concept shown in  FIG. 7 . In the static random access memory device  2450 , during a write operation, a power supply terminal of a memory cell may be discharged by a write assist circuit and a bitline may be precharged by a read assist. Thus, a write margin of the memory cell may be improved. During a read operation, the power supply terminal of the memory cell may be precharged by the write assist circuit and a selected bitline may be discharged by the read assist circuit. Thus, a read margin of the memory cell may be improved. 
         [0066]      FIG. 9  is a block diagram of a computer system  3000  including a static random access memory device according to an example embodiment of the inventive concept. As illustrated, the computer system  3000  includes a network adapter  3100  electrically connected to a system bus  3700 , a central processing unit (CPU)  3200 , a data storage device  3300 , a random access memory (RAM)  3400 , a read only memory (ROM), and a user interface  3600 . The CPU includes a static random access memory device  3250  according to an embodiment of the inventive concept. 
         [0067]    The network adapter  3100  provides interfacing between the computer system  3000  and external networks. The CPU  3200  performs overall operation processing for driving an operating system (OS) or application programs that are resident on the RAM  3400 . The CPU  3200  may use the static random access memory device  3250  as a cache memory to perform the operation processing. The static random access memory device  3250  may stably control a memory cell array voltage and a bitline voltage through write and read assist circuits. Thus, the static random access memory device  3250  may stably perform write and read operations. 
         [0068]    The data storage device  3300  stores overall data required in the computer system  3000 . For example, an operating system (OS) for driving the computing system  3000 , application programs, various types of program modules, program data, and user data are stored in the computer system  3000 . The RAM  3400  may be used as a working memory of a computer system  3000 . Not only the operating system (OS), the application programs, the various types of program modules read from the data storage device  3300  but also program data consumed to drive programs is loaded into the RAM  3400  at the time of booting. A basic input/output system (BIOS) activated before driving the operating system (OS) at the time of booting is stored in the ROM  3500 . Information exchange between the computer system  3000  and a user is conducted through the user interface  3600 . Besides, the computer system  3000  may further include a battery or a modem. Although not shown in the figure, it will be understood that a computer system according to the inventive concept may be further provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and so forth. 
         [0069]    While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.