Abstract:
A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for forming an embedded circuit. In particular, the present invention relates to a method for forming an embedded circuit by using a dummy layer. The dummy layer is not only resistant to the acidic or alkaline conditions or organic solvents, but also does not interfere with the formation of the seed layer. The method of the present invention is advantageous in mass production and in circuit board structure. 
     2. Description of the Prior Art 
     A circuit board is an essential element in an electronic device. The function of the circuit boards is to define the pre-determined circuit patterns on a solid surface. Along with the trend of miniaturization of the electronic devices, the line width and the line space of the conductive wires on the circuit boards are becoming narrower and narrower. The embedded circuit structure draws more and more attention than ever in order to pursue a thinner product, to meet the demands of finer wires and to overcome the drawbacks of the etching procedure and reliability. Because in the embedded circuit structure the wire pattern is embedded in the substrate, the thickness of the wires seems to be omitted, thereby further reducing the thickness of the products after packaging. 
     With the development of shrinking dimensions of the electronic devices, the circuit board is usually disposed in a limited space. Currently, there are several methods available to form the circuit boards to meet the demand. The first one is to transfer-print patterned wires into a dielectric layer. Another one is to pattern the substrate by means of a laser fashion to define an intaglio structure. Then a conductive material is used to fill the recess formed on the substrate to obtain an embedded circuit structure. 
     For the current solution, it is produced by direct circuit design. For example, a laser is used to pattern a substrate. Then a conductive material is used to fill the recess formed on the substrate to obtain an embedded circuit structure.  FIGS. 1-5  illustrates a conventional method to form an embedded circuit. Please refer to  FIG. 1 , first a substrate  101  is provided. The substrate  101  includes a dielectric layer  110 , an inner layer  111  and an interconnecting circuit  112 . The interconnecting circuit  112  is disposed on the inner layer  111  and the dielectric layer  110  covers the interconnecting circuit  112  and the inner layer  111  at the same time. In addition, the dielectric layer  110  also includes a via column  113  which is electrically connected to the interconnecting circuit  112 . 
     Second, as shown in  FIG. 2 , a mask layer  114  is used to completely cover the dielectric layer  110  and the via column  113 . The mask layer  114  is required to have many features to facilitate the following steps. The features of the mask layer  114  will be described in the following paragraphs. 
     First, as shown in  FIG. 3 , a laser is used to pattern the mask layer  114 . The laser may be used to define the pattern and the location of the needed circuits. For example, trenches  115  of different width are formed after the laser patterns the mask layer  114 . Some of the trenches  115  may expose the via column  113 . 
     Then, as shown in  FIG. 4 , a desmear step is carried out. Because there may be some remaining residues  116  after the laser patterns the mask layer  114  and the remaining residues  116  degrade the quality of the following electrical connection, a pre-treatment step is carried out to remove the remaining possible residues  116  after the laser patterns the mask layer  114  to facilitate the later formation of the electrical connection. There may be an organic solvent or an oxidizing agent used in the pre-treatment step so the mask layer  114  must be resist to the corrosion of the organic solvent or the oxidizing agent. In addition, a base or an acid may also be used in the pre-treatment step, so the mask layer  114  must also be resistant to the corrosion of the acid or the base. 
     Next, as shown in  FIG. 5 , a seed layer  117  is formed. The resultant seed layer  117  may induce and facilitate the formation of the later formed copper circuit (not shown) in the trench  115 . Because the copper circuit (not shown) is required solely and exclusively to form in the trench  115 , the seed layer  117  accordingly has to be selectively and specifically formed in the trench  115  without covering the mask layer  114 . By the difference between the mask layer  114  and the dielectric layer  110 , the seed layer  117  is required to solely and exclusively form on the exposed dielectric layer  110  rather than on the mask layer  114 . 
     In the light of the above, the mask layer  114  not only must be resistant to the corrosion of the organic solvent or the oxidizing agent, but also be resistant to the corrosion of the acid or the base and impossible for the formation of the seed layer  117  so the seed layer  117  is selectively and specifically formed in the trench  115 . The development of the materials for the mask layer  114  becomes very difficult due to the various requirements of the mask layer  114 . 
     Further, in order to avoid the mask layer  114  falling off due to the attack of the chemical agents in the desmear step, weaker chemical agents are used. However, when the chemical agents are weaker, it is more likely to have remaining residues and the reliability of the products is more likely to be compromised. Circuits of bad quality are not welcome. 
     Given the above, a novel method for forming an embedded circuit is still needed to provide a reliable circuit board product. 
     SUMMARY OF THE INVENTION 
     The present invention therefore proposes a method for forming an embedded circuit, to provide a circuit board of good and reliable quality. In the method of the present invention, a dummy layer is used to form the embedded fine circuit. Such dummy layer is not only resistant to the acidic or alkaline conditions or organic solvents, but also does not interfere with the formation of the seed layer. The method of the present invention is advantageous in mass production and in circuit board structure. 
     The present invention therefore in a first aspect proposes a method for forming an embedded circuit. First, a substrate is provided. The substrate includes a dielectric layer. Second, the dielectric layer is entirely covered with a dummy layer. Next, the dummy layer is patterned and simultaneously a trench is formed in the dielectric layer. Then, a seed layer is formed to entirely cover the dummy layer and the trench. Later, the dummy layer and the seed layer covering the dummy layer are removed but part of the seed layer remains in the trench. Afterwards, the trench is filled with a metal layer to form an embedded circuit which is embedded in the dielectric layer. 
     In one embodiment of the present invention, the substrate includes an inner layer, an inner circuit and the dielectric layer. The inner circuit is disposed on the inner layer and the dielectric layer simultaneously covers the inner layer and the inner circuit. 
     In another embodiment of the present invention, the dummy layer is not a photoresist so the dummy layer includes no photo-sensitive material. 
     In another embodiment of the present invention, at least one of a physical manner and a chemical manner may be used to remove the dummy layer. 
     In another embodiment of the present invention, the seed layer disposed in the trench substantially remains intact when the dummy layer is removed. 
     In another embodiment of the present invention, the embedded circuit has a line width less than 30 μm. 
     In another embodiment of the present invention, the embedded circuit has a line pitch less than 30 μm. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1-5  illustrates a conventional method to form an embedded circuit. 
         FIGS. 6-13  illustrate a method for forming an embedded circuit of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention therefore provides a method for forming an embedded circuit, to provide a circuit board of good and reliable quality. In the method of the present invention, a dummy layer is used to form the embedded fine circuit. Such dummy layer is not only photo-sensitive material free, it is also resistant to the acidic or alkaline conditions or organic solvents and does not interfere with the formation of the seed layer. The method of the present invention is advantageous in mass production and in circuit board structure. 
       FIGS. 6-12  illustrate a method for forming an embedded circuit of the present invention. As shown in  FIG. 6 , first a substrate  101  is provided. The substrate  101  includes at least a dielectric layer  110 . Please refer to  FIG. 1 , in another embodiment of the present invention, the substrate  101  may include a dielectric layer  110 , an inner layer  111 , and an interconnecting circuit  112 . The dielectric layer  110  and the inner layer  111  may respectively be an insulating material. The interconnecting circuit  112  is disposed on the inner layer  111  and usually includes a metal, such as copper (Cu). The dielectric layer  110  simultaneously covers the inner layer  111  and the interconnecting circuit  112 . In addition, optionally the dielectric layer  110  may further include a via column  113  which is formed by forming a via hole penetrating the dielectric layer  110  and exposing the interconnecting circuit  112  then filled with a metal which is electrically connected to the interconnecting circuit  112 , as shown in  FIG. 1 . The via column  113  includes the via hole and the metal. 
     Second, as shown in  FIG. 7 , a dummy layer  118  is used to completely cover the dielectric layer  110  and the via column  113 . The dummy layer  118  generally includes a thermo-polymeric material and may be a polymer material of oligomers. The dummy layer  118  may have various monomers before curing and the oligomerization may be enhanced by a baking step. The dummy layer  118  may have various polymeric groups, such as an epoxy group with (artificially) modified rubber, an acrylic group, an imide group or an amide group . . . etc., after the polymerization reaction. In addition, there may be some optional additives, such as a defoamer, or a wetting agent. Accordingly, the dummy layer  118  is a co-polymer of low polymerization degree after the polymerization reaction. For example, the dummy layer  118  may undergo a baking step of 70° C.-120° C. for around 30 minutes for curing, so that the dummy layer  118  may have a resultant thickness of around 0.5 μm-30 μm. Please note that the curing step of the dummy layer  118  does not involve a photo-initiative reaction. 
     Next, as shown in  FIG. 8 , the dummy layer  118  may be patterned by a laser. The laser may also remove some of the dielectric layer  110  to simultaneously form a trench  115  in the dielectric layer  110 . An UV laser or an excimer may be used to define the locations or the patterns of the needed circuit. For example, various trenches  115  of different widths are formed after the dummy layer  118  is patterned by a laser. The trenches  115  may have suitable widths or pitches. For example, the trenches  115  per se may have a line width less than 30 μm. Besides, the trenches  115  per se may also have a pitch less than 30 μm. Some of the trenches  115  may even expose the via columns  113 . The dummy layer  118  is not patterned by an optical image transfer process so the dummy layer  118  is actually not a photoresist. 
     Then, as shown in  FIG. 9 , a desmear step may be carried out. Because there may be some residues  116  which remain on the inner wall of the trenches  115  and degrade the quality of the electrical connection in the following step, a desmear step is carried out to remove the possible residues  116  which remain on the inner wall of the trenches  115  after the dummy layer  118  is patterned by the laser to facilitate the later formation of the electrical connection. The desmear step may involve a plasma treatment, an organic solvent treatment such as alcohols, ethers, DMSO, DMF . . . etc. to render the patterned dummy layer  118  swelled, or an oxidizing agent, such as aqueous sulfuric acid/hydrogen peroxide, and MnO4 −  . . . etc. so the patterned dummy layer  118  is resistant to the corrosion of an organic solvent or an oxidizing agent. Besides, the desmear step may also involve an acid, such as sulfuric acid, or a weak base, so the patterned dummy layer  118  is resistant to the corrosion of an acid or a weak base as well. 
     Next, as shown in  FIG. 10 , a seed layer  117  is formed. The resultant seed layer  117  may induce and facilitate the formation of the later formed copper circuit (not shown) in the trench  115 . Because of the special properties of the dummy layer  118  of the present invention, the seed layer  117  is allowed to form in the trench  115 , or the seed layer  117  may also cover the surface of part of the dielectric layer  110  which is exposed by the trench  115  and covers the dummy layer  118 . For example, the surface of part of the dielectric layer  110  exposed by the trench  115  is soaked in a solution containing at least a noble metal such as Pt, Pd, Au or Rh, so that the resultant seed layer  117  is able to completely cover the trench  115  and the surface of part of the dielectric layer  110  exposed by the trench  115 . Of course, the resultant seed layer  117  may also selectively cover the trench  115  and the surface of part of the dielectric layer  110  exposed by the trench  115 . 
     Later, as shown in  FIG. 11 , the dummy layer  118  is completely removed. Because there is some of the seed layer  117  covering the dummy layer  118 , such seed layer  117  which covers the dummy layer is also removed when the dummy layer  118  is completely removed. For example, the dummy layer  118  may be removed chemically or physically. 
     The dummy layer  118  may be removed by an alkaline solution chemically. The alkaline solution may contain a strong inorganic base, such as sodium hydroxide. The alkaline solution may have a pH value greater than 11, preferably between pH 11-pH 13. The physical way may play a dominant part or an auxiliary part to remove the dummy layer  118 . For example, the physical way may be brushing, polishing, plasma treating or ultra-sonic treating. In a better embodiment, the dummy layer  118  is completely removed without damaging the quality of the seed layer  117  in the trench  115 . 
     Afterwards, as shown in  FIG. 12 , a metal layer  119  layer of a sufficient thickness is formed in the trench  115  by electroless-plating so that the metal layer  119  becomes an embedded circuit  120  embedded in the dielectric layer  110 . Please refer to  FIG. 13 , the metal layer  119  which is embedded in the dielectric layer  110  may have various embodiments. For example, the top of the metal layer  119  is slightly lower than the top of the dielectric layer  110 , or the top of the metal layer  119  is roughly as high as the top of the dielectric layer  110 , or the top of the metal layer  119  is slightly higher than the top of the dielectric layer  110 . 
     The metal layer  119  is usually a layer of copper made by a way of chemical deposition reaction rather than by a way of electroplated deposition reaction. Optionally, a pre-electroless plating step may be carried out to form a pre-layer of a thickness about 2 μm, to facilitate the formation of the embedded circuit  120  to form a layer of chemical deposited copper of a thickness around 5-30 μm. After the previous step, an embedded circuit  120  embedded in the dielectric layer  110  is obtained. The embedded circuit  120  includes a layer of metal  119  chemically made of chemical deposited copper which is disposed in the trench  115  and on the seed layer  117 . 
     Preferably, the desmear step may also render the exposed part of the trench  115 , i.e. the surface of the dielectric layer  110 , to have a suitable roughness. For example, the roughness Ra may be 0.5 μm-5.0 μm. Please refer to JIS B 0601 of the latest edition for the definitions and the details of the roughness Ra. Or, the desmear step may render the final chemically made metal layer  119  to have a peel stress greater than 0.5 kg/cm. 
     The present invention produces an embedded circuit by a dummy layer. Such dummy layer is not only resistant to the acidic or alkaline conditions or organic solvents, but also does not interfere with the formation of the seed layer. The method of the present invention is advantageous in mass production and in circuit board structure. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.