Abstract:
A method for transmitting signals along an interconnect in a VLSI system comprising receivers is disclosed. The VLSI based systems operate in the high Giga hertz range. The signals are transmitted along the interconnect as a localized wave packet i.e. as a pulse. The interconnect may be either electrically linear or nonlinear in nature.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority under 35 U.S.C §119(e) of U.S. Provisional application 60/675,090 filed Apr. 27, 2005, the entire contents of which are hereby incorporated by reference. 
    
    
     GOVERNMENT SPONSORSHIP STATEMENT 
     This invention was made with Government support from the Defense Advanced Research Projects Agency (DARPA) under grant number F30602-01-2-0552 and the National Science Foundation (NSF) under grant number 9985062. The Government has certain rights in the invention. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Systems and methods for on-chip interconnect are disclosed. More specifically, systems and methods are described for transmission of signals as localized wave packets that propagate along the interconnect lines to trigger the receivers. In addition, the present invention enables time division multiplexing of signals on a single interconnect. 
     2. Description of the Background Art 
     On-Chip global interconnect is among the top challenges in integrated circuit technology scaling due to the rapidly increasing operation frequencies and the growing chip size. With clock frequencies in multi gigahertz range, inductance, capacitance and other frequency dependant factors have to be taken into consideration. For high frequency range, frequency related dispersions and skin effect are other concerns while designing interconnects. Other global interconnects, such as data bus and control lines, face similar complications. 
     In interconnect design, the general practice in transmitting signals is to control the voltage level of the entire interconnect line and connected receivers. As a result, the long line and all the receivers are very heavy loads to the drivers. Repeaters are thus needed to overcome the propagation delay. This however adds more chip area and increases the power consumption of the system. 
     SUMMARY OF THE INVENTION 
     A method for transmitting signals along an interconnect in a VLSI system comprising receivers is disclosed. The VLSI based systems operate in the high Giga hertz range. The signal is transmitted along the interconnect as a localized wave packet i.e. as a pulse. The interconnect may be either electrically linear or nonlinear in nature. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1(   a ) depicts a general pulsed wave interconnect circuit logic as disclosed herein. 
         FIG. 1(   b ) shows an equivalent circuit of the logic in  FIG. 1(   a ). 
         FIG. 1(   c ) shows a conventional circuit with repeaters inserted. The line is uniformly divided into “n” sections. Each driver is ‘h’ times of the minimum size inverter. 
         FIG. 2  shows waveforms from SPICE simulations: 
         FIG. 2(   a ). Dotted line: input signal; dashed line: output signal from the circuit in  FIG. 1(   a ). Solid line: output of the circuit in  FIG. 1(   b ). 
         FIG. 2(   b ). Two pulses sharing one interconnect. Dotted line: input signal to the inverter  2  in  FIG. 1(   a ). Dashed line: output signal from the receiver in  FIG. 1(   a ). Inter symbol interferences exist, but reach steady state after several periods. 
         FIG. 3(   a ) Non Linear Transmission Line (NLTL) with nonlinear capacitors. 
         FIG. 3(   b ) Simplified equivalent circuits which are conventionally used for soliton studies. 
         FIG. 4  represents Pulse-shaped soliton generated using models of  FIG. 3(   a ) with 100 lumped RLC elements for each stage: Dashed line: input; solid line: output. 
         FIG. 5(   a ) Pulse amplitude attenuation during propagation through the NLTL. Dashed line: input; solid lines: outputs at different stages. 
         FIG. 5(   b ) Pulse compression for amplitude amplification. The line parameters are similar to the line in  FIG. 4 . The symbols are similar to those in  FIG. 5(   a ). 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Overview 
     Methods and systems for realizing on-chip interconnect are disclosed. In typical VLSI based systems, a new interconnect scheme can be realized when the clock frequency (f clock ) is pushed into the high-gigahertz range. In such systems, a localized wave packet i.e. a pulse with a width of only a small fraction of the global clock signal (T c ) is required to trigger a receiver. The pulse is also spatially short in comparison with the chip size in the conventional technologies. If such a pulse is used as a signal carrier, the long interconnect would electrically isolate the driver from the receiver. Such a practice of charging up the entire line and the receivers, results in waste of energy and resources in high-speed VLSI systems. Therefore in such systems, only a short pulse with duration of a small fraction of T c  is necessary and sufficient for signal transmission and for triggering the receiver. 
     This approach is annotated as Pulsed Wave Interconnect wherein only a small part of the interconnect line is charged for signal transmission. In one embodiment, the same interconnect line is shared by several consecutive time division multiplexed pulses to boost the bit-rate capacity of the interconnect lines. 
     In another embodiment, where the attenuation of the pulses is very high, a non-linear transmission line is used to counter waveform distortion and amplitude loss. The pulse propagation along these interconnects results in the pulse being propagated as solitons. 
     The aspects involved in realizing a Pulsed Wave Interconnect are now described in greater detail. 
     An Exemplary System 
     Although not required, the systems and methods for realizing pulsed wave interconnect are described in the general context of logic circuitry and active and passive electronic elements. While the systems and methods are described in the foregoing context, acts and operations described hereinafter may also be implemented as hardware. 
       FIG. 1(   a ) depicts an exemplary pulsed wave circuit  100  through the use of logic circuits in one implementation. An equivalent circuit of FIG. ( 1   a ) is depicted in  FIG. 1(   b ). The pulsed wave circuit as depicted in  FIG. 1(   a ) consists of invertors  102 - 1 ,  102 - 2 ,  102 - 3  and  102 - 4 . 
     It would be appreciated that all the components of the pulsed wave circuit are connected to each other through an interconnect. Another embodiment the system includes one or more receivers, with the receivers being identical or non-identical or a combination thereof. In such systems, a pulse with a width of only a small fraction of the global clock signal (T c ) would be necessary and sufficient to trigger the receiver. The pulse is also spatially short in comparison with the chip size known in conventional technologies. When such a pulse is used as a signal carrier, the long interconnect would electrically isolate the driver from the receiver. It also results in the system consuming lesser amount of energy as compared to existing interconnect methodologies.  FIG. 1(   c ) shows a conventional circuit with repeaters, wherein the interconnect is uniformly divided into “n” sections. Each driver is ‘h’ times of the minimum size inverter. The detailed analysis of the energy consumption of the two systems is provided in the section titled “E NERGY  C ONSUMPTION  I N  P ULSED  W AVE  I NTERCONNECT  S YSTEMS ”. 
     In case of severe signal dispersion and attenuation, non-linearity can be introduced to counter wave form distortion and amplitude loss. In another embodiment, this is achieved by using a Non-Linear Transmission Line (NLTL). The pulse propagation along such interconnects results in the pulse being propagated as a soliton. A soliton is a self-reinforcing solitary wave caused by nonlinear effects in the medium through which it propagates. Solitons are found in many physical phenomena. They arise as the solutions of a widespread class of weakly nonlinear partial differential equations describing physical systems. An NLTL is a type of transmission line which is periodically loaded with nonlinear energy storage elements in stages. In one implementation the NLTL uses nonlinear capacitors. The analysis of the transmission of a pulse over a non-linear interconnect is described in the section titled “N ONLINEAR  T RANSMISSION  L INE  (NLTL) D ESIGN ”. 
     In accordance with the invention, a small portion of the entire line would be charged. Smaller line capacitances and the voltage doubling property of the receiver gate capacitances help reduce energy consumption. It is also evident from the invention that an NLTL may also be used to overcome pulse broadening and attenuation caused by dispersion and frequency-dependant losses. 
     Energy Consumption in Pulsed Wave Interconnect Systems 
       FIG. 1(   a ) illustrates an arrangement of the proposed pulsed wave interconnect for signal transmission which can be represented by a line with R, L, C, G as its resistance, inductance, capacitance and conductance per unit length respectively. To simplify the analysis in this section, a linear, non-dispersive line is assumed with DC attenuations. The input pulse duration is of the order of T c  and much longer than the fan-out-of-4 (FO4) T FO4 . A sub-circuit is used to generate a short pulse with a duration determined by the propagation delay of inverter  102 - 1 . Inverter  102 - 2  then generates a short electrical pulse through charging up the interconnect line. If the round-trip time-of-flight of the line is longer than the pulse duration T p , the receiver inverter is electrically isolated from the driver. The load of the pull-up pMOS transistor is equivalent to an infinitely long transmission line, which can be represented as a grounded load with an impedance equal to the line characteristic impedance Z s  given by: 
     
       
         
           
             Zs 
             = 
             
               
                 
                   ( 
                   
                     R 
                     + 
                     
                       jω 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         L 
                         / 
                         G 
                       
                     
                     + 
                     
                       jω 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       C 
                     
                   
                   ) 
                 
               
               ⁢ 
               
                 
 
               
               ⁢ 
               
                   
               
               = 
               
                 Zo 
                 ⁢ 
                 
                   
                     ( 
                     
                       1 
                       + 
                       
                         
                           ( 
                           
                             
                               R 
                               / 
                               jω 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             L 
                           
                           ) 
                         
                         / 
                         
                           ( 
                           
                             1 
                             + 
                             
                               ( 
                               
                                 
                                   G 
                                   / 
                                   jω 
                                 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 C 
                               
                               ) 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
             
           
         
       
     
     where Zo is the lossless characteristic impedance of the line and is given as Zo=√{square root over (L/C)} 
     The pMOS transistor (inverter  2 )  104  as indicated in  FIG. 1(   b ) is assumed to be operating in the linear region. The expression for the voltage wave front V(x) traveling down the lossy infinite line is given by: 
     
       
         
           
             
               V 
               ⁡ 
               
                 ( 
                 x 
                 ) 
               
             
             = 
             
               
                 V 
                 dd 
               
               ⁢ 
               
                 
                   Z 
                   0 
                 
                 
                   
                     Z 
                     0 
                   
                   + 
                   
                     R 
                     tr 
                   
                 
               
               ⁢ 
               
                 ⅇ 
                 
                   
                     - 
                     Rx 
                   
                   / 
                   
                     ( 
                     
                       2 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         Z 
                         0 
                       
                     
                     ) 
                   
                 
               
             
           
         
       
     
     where V dd  is the power source voltage; R tr  is the equivalent source resistance; and Rx is the line characteristic impedance at point x. 
     It is known in the art that the significant frequency given by: 
     
       
         
           
             f 
             = 
             
               0.34 
               
                 t 
                 r 
               
             
           
         
       
     
     where t r  is the signal rise time. 
     The above equation provides a very good representative frequency of a trapezoidal pulse for approximating its high-frequency electrical behavior. 
     The pulsed wave interconnect method requires a pulse at the end of the interconnect line with amplitude given by: 
     
       
         
           
             
               V 
               ⁡ 
               
                 ( 
                 l 
                 ) 
               
             
             = 
             
               
                 
                   
                     
                       V 
                       dd 
                     
                     ⁢ 
                     
                       Z 
                       0 
                     
                   
                   
                     
                       Z 
                       0 
                     
                     + 
                     
                       R 
                       tr 
                     
                   
                 
                 ⁢ 
                 
                   ⅇ 
                   
                     
                       
                         - 
                         Rl 
                       
                       / 
                       2 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       Z 
                       0 
                     
                   
                 
               
               &gt; 
               
                 
                   V 
                   M 
                 
                 2 
               
             
           
         
       
     
     Wherein V(l)=V(x) for x=l. 
     The pulse takes a length L p  along the interconnect line where L p  is given as:
 
 L   p   =T   p ×ν p  
 
     where ν p  is the signal transmission speed determined by the speed of light in the dielectric medium. 
     The interconnect capacitance, which is effectively charged up to generate a certain voltage across the length of the interconnect is given by C p . In one cycle of charging and discharging, the energy consumption related to C p  is given by the equation: 
     
       
         
           
             
               E 
               pl 
             
             = 
             
               
                 
                   
                     C 
                     p 
                   
                   ⁡ 
                   
                     ( 
                     
                       
                         Z 
                         0 
                       
                       
                         
                           Z 
                           0 
                         
                         + 
                         
                           R 
                           tr 
                         
                       
                     
                     ) 
                   
                 
                 2 
               
               ⁢ 
               
                 
                   V 
                   dd 
                   2 
                 
                 . 
               
             
           
         
       
     
     The energy consumed by charging and discharging the capacitors of the drivers and the receivers in one cycle can be approximated by the following expression.
 
 E   pdr   =C   pdr   V   dd   2  
 
     where C pdr  is the sum of all the input and output capacitances in  FIG. 1(   a ). It should be noted that the sub-script p denotes the variables in the Pulsed Wave Interconnect systems, 
     The system and methods use lesser amount of energy and space as compared to conventional repeater insertion methods. A conventional repeater insertion circuit is indicated in  FIG. 1(   c ). In this system, the energy consumption by the whole line whose capacitance is C l  is represented as:
 
 E   1   =C   1   V   dd   2  
 
     The energy consumption of the systems using repeaters is represented by
 
 E   rdr   =C   rdr   V   dd   2  
 
     Where C rdr  is the sum of all input and output capacitances of the repeaters. 
     It should be noted that the sub-script r denotes the systems using repeater insertion. 
     The total energy consumed in the pulsed wave interconnect and repeater insertion methods are given by: 
     
       
         
           
             
               
                 
                   
                     E 
                     p 
                   
                   = 
                   
                     
                       E 
                       pl 
                     
                     + 
                     
                       E 
                       sdr 
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         
                           
                             
                               C 
                               p 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   Z 
                                   0 
                                 
                                 
                                   
                                     Z 
                                     0 
                                   
                                   + 
                                   
                                     R 
                                     tr 
                                   
                                 
                               
                               ) 
                             
                           
                           2 
                         
                         + 
                         
                           C 
                           sdr 
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       V 
                       dd 
                       2 
                     
                   
                 
               
             
             
               
                 
                   
                     E 
                     repeater 
                   
                   = 
                   
                     
                       
                         E 
                         l 
                       
                       + 
                       
                         E 
                         rdr 
                       
                     
                     = 
                     
                       
                         ( 
                         
                           
                             C 
                             l 
                           
                           + 
                           
                             C 
                             rdr 
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         
                           V 
                           dd 
                           2 
                         
                         . 
                       
                     
                   
                 
               
             
           
         
       
     
     The circuits were simulated on SPICE and the results obtained are tabulated in Table I. Table I lists the energy consumption, propagation delay and layout area for driving a line of length 10 cm with Zo=75 Ω, L=500 nH/m, C=89 pF/m, and R=1500 Ω/m using  FIGS. 1(   a ) and ( c ). 
     
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 ENERGY CONSUMPTION, AREA AND THE PROPOGATION 
               
               
                 DELAY FOR THE INTERCONNECT IN FIG. 1. 
               
             
          
           
               
                   
                 Energy 
                 Delay 
                 I max   
                   
               
             
          
           
               
                   
                 Calcula- 
                 Simu- 
                 Simu- 
                 Simu- 
                 Area 1   
               
               
                   
                 tions 
                 lated 2   
                 lated 2   
                 lated 2   
                 Simu- 
               
               
                   
                 (pJ) 
                 (pJ) 
                 (ps) 
                 (mA) 
                 lated 2   
               
               
                   
               
             
          
           
               
                 Pulsed 
                 ~11.4 
                 13.4 
                 ~840 
                 ~15 
                 ~316 
               
               
                 Wave 
                   
                   
                   
                   
                   
               
               
                 Interconnect 
                   
                   
                   
                   
                   
               
               
                 Repeater 
                 ~23 
                 32 
                 840 
                 ~14 
                 ~500 
               
               
                 Insertion 
               
               
                   
               
               
                   1 Areas are in minimum size inverter 
               
               
                   2 Simulated indicates results from the SPICE simulations 
               
             
          
         
       
     
     Table I indicates that the pulsed wave interconnect, as in one of the embodiments, is superior to the repeater insertion method on energy consumption (saves more than 50%) and layout area (saves about 30%) when the signal propagation delays are about the same. Pulsed wave interconnect uses about the same peak current as the repeater insertion method. In the simulation, the last inverters in both circuits are chosen to be the same so that they will have identical driving ability to the following stages. The requirement for the input signal is also set approximately the same to make the comparison fair. 
     In one implementation the pulsed wave of ˜200 ps duration, which is about 3 times of t FO4  and 3 cm long on the line, has an amplitude of about 1.22 V at the driver end under V dd  equal to 1.8 V. 
       FIG. 2(   b ) shows another embodiment in which the same line can be shared by two short pulses simultaneously with minimal inter symbol interference. The above embodiments show that pulsed wave interconnect can be used for wafer-scale integration or packaging interconnect to save energy and area. 
     Nonlinear Transmission Line (NLTL) Design 
     An NLTL is a type of transmission line which is periodically loaded with nonlinear energy storage elements in stages. In one implementation, the NLTL uses nonlinear capacitors  302 - 1  to  302 - n . Such a circuit  300 - 1  and the corresponding equivalent circuit  300 - 2  are shown in  FIG. 3 . 
       FIG. 4  shows the pulse-shaped soliton  404  generated by the input signal  402  and transmitted with hundred lumped RLC elements for each stage in another embodiment. 
       FIG. 5(   a ) shows a pulsed wave  504  generated by the input signal  502  and propagating through the NLTL, without pulse compression. As shown in  FIG. 5(   a ), the soliton amplitude will gradually diminish because of the losses from the resistances in the interconnect. Pulse compression can be used to compensate for the amplitude loss. In one embodiment, pulse compression shown in  FIG. 5(   b ), is obtained by tapering the non-linear energy storage elements. The tapering is applied at each stage along the length of the interconnect. The non-linear capacitance is given by the following equation:
 
 C   n,c ( V )= k   n   C   d0 /(1 +V/V   cc )
 
     where k is the tapering factor, for the stage n. The choice of the value of the tapering factor k is dependent on the expected pulse width, amplitude and the number of stages. It may be noted that the pulse amplitude attenuation in  5 ( b ) is far less than in  FIG. 5(   a ). 
     The pulse amplitude attenuation of the pulse  506 , along NLTL which is tapered is dramatically reduced. In the case of the last pulse in  FIG. 5(   b ), the pulse amplitude is about two times that of the last pulse in  FIG. 5(   a ). In one implementation of the tapered NLTL, the capacitors used have a tapering factor of 0.95. 
     CONCLUSION 
     In accordance with the method disclosed, a small portion of the entire line would be charged. Smaller line capacitances and voltage doubling property of the receiver gate capacitances help reduce energy consumption. It is also evident that an NLTL may be used to overcome pulse broadening and attenuation caused by dispersion and frequency-dependant losses. 
     Although the foregoing description has been shown and described with reference to particular embodiments and applications thereof, it may be appreciated that the embodiments and implementations have been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the particular embodiments and implementations disclosed. It will be apparent to those ordinarily skilled in the art that a number of changes, modifications, variations or alterations to the systems and methods as described herein may be made, none of which depart from the spirit or scope of the invention.