Abstract:
A low power charge pump system having a plurality of charge pump cells. Each cell is a three transistor device that operates to transfer voltage from an input node to an output node of the cell when the input voltage is substantially greater than the output voltage and to block when the output voltage is substantially greater than the input voltage. Each cell has a pump capacitor is connected between a clock and its output, the odd-numbered cells having a first clock connected to their pump capacitors and the even-numbered cells having a second clock connected to their pump capacitors. During a first phase of either the first or second clock, the cell operates to transfer a voltage on its input node to its output node and during a second phase, the cell operates to boost its output voltage by a predetermined amount.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. application titled “LOW POWER CHARGE PUMP METHOD AND APPARATUS”, Ser. No. 10/294,042, filed Nov. 12, 2002, which is a continuation-in-part of Ser. No. 09/967,189, filed Sep. 27, 2001, now U.S. Pat. No. 6,559,681, issued May 6, 2003, titled “RESONANT LOGIC AND THE IMPLEMENTATION OF LOW POWER DIGITAL INTEGRATED CIRCUITS”, which patent is hereby incorporated by reference into the present application. 

   FIELD OF THE INVENTION 
   This invention relates generally to charge pumps, and in particular, to low power charge pumps using resonant power circuitry. 
   DESCRIPTION OF THE RELATED ART 
   Charge pumps are commonly used to generate or boost a voltage beyond the range of the power supply in the system. These devices are often used in flash memory or EEPROM.  FIG. 1  shows a prior art charge pump  10  employing diodes  12 ,  14 ,  16  and two clocks CLK 1   20 , CLK 2   22 . Included in the charge pump are a number of stages  32 ,  34 ,  36  each of which includes a diode  12 ,  14 ,  16  (or diode connected transistor), which is used as the charge transfer device, and a capacitor  24 ,  26 ,  28  which is used as charge holding device. One side of the diode in each stage is connected to an input voltage and the other side is connected to the capacitor of the stage. The other side of the capacitor  24 ,  26 ,  28  is connected to a clock input  20 ,  22 . The input of the diode in the first stage is connected to the power supply, Vdd, that is to be boosted. The output of the diode  16  in the last stage is the boosted voltage, which may be connected to a storage capacitor  40  via a diode  18 . Preferably, the clock inputs to adjacent stages are non-overlapping to prevent charge from moving backward and decreasing efficiency. 
   In operation, while the clock  20  to the capacitor  24  of the first stage  32  is low, charge is transferred through the first stage diode  12  from the power supply Vdd to the first stage capacitor  24 . Thus, the capacitor  24  is charged so as to have a voltage, Vdd−Vf, across it, where Vdd is the supply voltage and Vf is the voltage drop across the diode  12 . While the first stage capacitor  24  is charging to Vdd−Vf, the next succeeding stage  34  has its clock  22  in its high state to prevent the charging of the first stage  32  from leaking into the second stage capacitor  26 , because the second stage diode  14  is back-biased. 
   When the clock  20  to the first stage  32  changes to its high state and the second stage clock  22  changes to its low state, the voltage on the first stage capacitor  24  is now, (Vdd−Vf)+Vdd and the second stage capacitor  26  is now charged to (Vdd−Vf)+Vdd . When the second stage clock  22  changes to Vdd, the voltage on the second stage capacitor  26  becomes Vout=(Vdd−Vf)2+Vdd. Every succeeding stage adds a new voltage of Vdd−Vf to the preceding stage voltage. Thus, after N stages the final voltage Vout=(Vdd−Vf)·N+Vdd. As is apparent from the formula, to obtain a specified increase in voltage, an additional number of stages may need to be employed to overcome the Vf loss at each stage than if there were no Vf loss at each stage. For example, if Vf is 0.5 volt, after two stages an entire volt is lost that otherwise could have been generated. This requires an additional stage of boost to recover the one volt loss. Therefore, the above described circuitry is inefficient. 
   To improve the efficiency of the above circuitry, the circuitry of  FIG. 2A  may be used. The circuitry  50  of  FIG. 2A  shows a charge pump in which the Vf drop of the charge transfer device is substantially reduced. Two stages  52 ,  54  of the charge pump are shown in the figure. Stage  52  includes three transistors M 2   56 , M 1   58 , M 3   60 , two capacitors C 1   68 , C 2   70  and two clock inputs CLK 1   76 , CLK 2 _a  78 . Stage  54  includes three transistors M 1   62 , M 2   64 , M 3   66 , two capacitors C 1   72  and C 2   74  and two clock inputs CLK 2   80 , CLK 1 _a  82 . Stage  54  has an input node  84  and an output node  86 . A first transistor M 1  of each stage is the charge transfer device, the second transistor M 2  is configured for Vt cancellation and the third transistor M 3  is used for initialization. A first capacitor C 1  is the charge-pump holding capacitor. A second capacitor C 2  is a Vt cancellation capacitor for use in conjunction with the second transistor M 2 . 
   The channel of the first transistor M 1  of each stage connects between the input node and the output node of the stage, the output node being the node at which the boosted voltage is present. The gate of the first transistor M 1  connects to one side of the second capacitor C 2  and a “transfer clock,” CLK 1 _a or CLK 2 _a, connects to the other side of the second capacitor C 2 . The channel of the second transistor M 2  of each stage connects between the gate of the first transistor M 1  and the input node of the stage. The gate of the second transistor M 2  connects to one side of the first capacitor C 1  and a “boost clock,” CLK 1  or CLK 2 , connects to the other side of the first capacitor C 1 . The gate of the second transistor M 2  also connects to the output node of each stage. 
   The third transistor M 3  of each stage is diode-connected, having its channel between the supply voltage Vdd and the output node of each stage and is present to maintain the voltage at the output of each stage at least the supply voltage Vdd. Preferably, the four clocks, CLK 1 , CLK 2 _a, CLK 2 , and CLK 1 _a have the relationship shown in  FIG. 2B , i.e., CLK 1  and CLK 2  are inversions of each other, CLK 1 _a is in-phase with CLK 1  but has a smaller duty cycle and CLK 2 _a is in-phase with CLK 2  but has a smaller duty cycle. Clocks CLK 1 _a and CLK 2 _a operate to turn on the pass transistor devices M 1  of each stage, and clocks CLK 1  and CLK 2  operate to boost the voltage at the output of the stage. 
   When the CLK 2 _a  78  is high, voltage (in this case Vdd) on the input node  84  is transferred to the output node  86  of the stage  52  via the channel of transistor M 1   58 , because the channel of transistor M 1   58  is conductive due to the change in CLK 2 _a  78  propagating through capacitor C 2   70 . When the CLK 1   76  transitions high, transistor M 2   56  turns on, transferring input voltage Vdd to the gate of transistor M 1   58  and boosting, via capacitor C 1   68 , the output node of the stage to approximately 2Vdd. A short time after CLK 1  transitions high, CLK 1  a turns on and transfers the 2Vdd voltage to the output of the second stage. Next, when CLK 2  transitions high, the output of the second stage is boosted to 3Vdd. A short time after CLK 2  transitions high, CLK 2 _a turns on and the cycle begins anew. 
   The clocks, CLK 2  and CLK 1 _a, of the second stage must operate out-of-phase from the clocks, CLK 1  and CLK 2 _a, of the first stage, as shown in  FIG. 2B , such that the output node of the first stage is boosted prior to the output node the second stage being boosted. Otherwise, the output nodes of two adjacent stages would be connected at the same time, thus defeating the second of the two adjacent stages. Instead, by inversely phasing the clocks between stages, every other stage is a boosting stage. 
   The result of this implementation is that each stage increases the voltage by an amount approximately equal to Vdd. However, although the circuit of  FIG. 2  substantially removes the Vt drop from each stage, four clocks are required between two stages for the circuit of  FIG. 2  to work. These clocks, as explained above, must have precise timing relationships to guarantee that the transistors of each stage are not on at the same time, and that the boost time in the previous stage, is properly overlapped with the transfer time, by the adjacent succeeding stage. Furthermore, the four clocks of the circuit of  FIG. 2 , have high power consumption and the sizes of the pass transistors  58 ,  62  and the pump capacitors  68 ,  72  are large, thus requiring large amounts of die area. 
   It is apparent from the above, that there is a need for an improved charge pump circuit that does not have a significant voltage loss at each stage and has low power consumption. There is also a need for a further improved charge pump that does not require four precisely-timed clocks to operate and does not require large capacitors and transistors. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention is directed towards such a need. A device in accordance with the present invention includes a charge pump system having a first charge pump means and a second charge pump means. The first means includes an input and an output node and is configured to transmit a voltage on the input node to the output node during a first phase of a first clock, and to add a first predetermined voltage to the voltage on the output node, during a second phase of a first clock. The second means includes an input and an output node and is configured to transmit a voltage on the input node to the output node during a first phase of the second clock, and to add a second predetermined voltage to an output node, during a second phase of a second clock. The first phase of the first clock is aligned with the second phase of the second clock and the second phase of the first clock is aligned with the first phase of the second clock, such that the voltage at the output of the second means is substantially near the sum of the first predetermined and second predetermined voltages. 
   More particularly and in accordance with the present invention, a charge pump cell includes a pass transistor, a biasing transistor and a blocking transistor. The pass transistor its channel connected between an input node and an output node of the charge pump cell. The biasing transistor has its channel connected between the gate of the pass transistor and a biasing node and the blocking transistor has its channel connected between the gate of the pass transistor and the output node of the cell. The gate of the blocking transistor is connected to the gate of the biasing transistor and the input node of the cell. When a voltage at the input node of the cell is greater than a voltage at the output node and a voltage on the biasing node is at least a threshold voltage below the voltage at the input node, the pass transistor passes current from the input node to the output node, and when the voltage at the output node is greater than the voltage at the input node, the pass transistor is non-conductive. 
   One advantage of the present invention is that, in one embodiment, only two clocks are needed to control the charge pump stage while the stage provides a doubling of the input voltage without the loss of a threshold drop. 
   Another advantage in the above embodiment is that the two clocks provide the power to operate the charge pump circuitry. No connection of the charge pump stage to the power supply is made. 
   Yet another advantage of the above embodiment is that low power is achieved by providing the clocks that power the charge pump stage from clock circuitry that recycles the clock energy. 
   Another advantage of the present invention is that, in another embodiment, lower power operation is obtained by providing the clocks from a pair of clock circuitry blocks. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
       FIG. 1  shows a prior art charge pump employing diodes and two clocks; 
       FIG. 2A  shows a prior art charge pump employing transistors and four clocks; 
       FIG. 2B  shows a timing diagram of the operation of the charge pump of  FIG. 2A ; 
       FIG. 3  shows a charge pump cell of the present invention; 
       FIG. 4  shows a charge pump system employing the cells of the present invention; 
       FIG. 5  shows clock circuitry  140  for use with the charge pump of FIG.  3  and charge pump system of  FIG. 4 ; 
       FIG. 6  shows a preferred embodiment of the clock circuitry of  FIG. 5 ; and 
       FIG. 7  is a block diagram of the precharge and discharge paths. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3  shows a charge-pump cell  98  of the present invention. This charge pump cell  98  has the property that it passes current from input to output depending on the relative magnitudes of the input and output voltages, with very little voltage drop across the cell  98 , thus approximating an ideal voltage-controlled switch. 
   The cell  98  includes two PMOS transistors P 1 , P 2  and one NMOS  104  transistor N 1 . The first PMOS transistor P 1   100  acts as a pass transistor and the second PMOS transistor P 2   102  is connected to prevent conduction from the output back to the input. The NMOS transistor is connected to properly bias the gate of the pass transistor P 1  when current flows from input to output. More particularly, the first PMOS transistor P 1  has a channel connected between the input and the output nodes of the cell. The second PMOS transistor P 2  has a channel connected between the output node of the cell and the gate of the first PMOS transistor. The NMOS transistor has a channel connected between the gate of the first PMOS transistor and the NSS node. Both the gate of the second PMOS transistor P 2  and the gate of the NMOS transistor N 1  are connected to the input node of the cell. 
   There are two conditions to consider in the operation of the cell. A first condition occurs when the voltage on the input node of the cell is substantially greater than the voltage on the output node of the cell. A second condition is when the voltage on output node of the cell is substantially greater than the voltage on the input node. 
   When the first condition is present, the pass transistor P 1  and the NMOS transistor N 1  are both on, and the P 2  transistor is off. The NMOS transistor is on because it is assumed that there is a positive voltage between the gate and NSS node of the transistor when the first condition is present. Positive gate drive on the NMOS transistor is guaranteed by the connections made to the NSS node when a plurality of cells are joined as described below. Because the NMOS transistor N 1  is on, the pass transistor P 1  is also on, because there is a positive voltage between the input node of the cell and the gate of the pass transistor. Thus, the pass transistor conducts from the input node to the output node of the cell, with a very small voltage drop. Also, transistor P 2  is off when the NMOS transistor is on, because both sides of the channel of transistor P 2  are at a lower voltage than the gate of transistor P 2 . With the pass transistor on, the output node eventually rises to the voltage level of the input node. When this occurs, condition one is no longer present, and the cell is at the verge of the second condition. 
   When the second condition is present, both the pass transistor P 1  and the NMOS transistor N 1  are off, and the second PMOS transistor P 2  is on. The NMOS transistor N 1  is off because the voltage on the NSS node is no longer at least a threshold voltage below the voltage on gate of the N 1  transistor. Transistor P 2  is on because the output voltage of the cell is greater than the input voltage of the cell, thus providing a positive voltage between one side of the channel (connected to the output node) and the gate of transistor P 2 . Pass transistor P 1  is off because transistor P 2  is on preventing the gate from falling at least a threshold voltage below either side of the channel of transistor P 1 . Thus, in the second condition, the cell is non-conducting. The cell, therefore, operates as a voltage-controlled switch with little or no voltage drop when on. 
     FIG. 4  shows a charge pump system employing the cells of the present invention. It is important to note the connections made to the NSS node. In particular, each NSS node is connected to the input node of the preceding cell, except for cell  1 , which has its NSS node connected to the output node of cell  1 . Thus, the NSS of cell  2  is connected to the input node of cell  1 , the NSS of cell  3  is connected to the input node of cell  2 . These connections guarantee that the voltage on the NSS node of a cell is always less than the gate of the NMOS transistor in the cell when the cell should be conducting. Also, the output node of each cell is connected via a capacitor to either a first clock CLK 1  or a second clock CLK 2 , in alternating fashion and the input of the first cell is connected to Vdd. The first and second clocks are non-overlapping clocks similar to CLK 1  and CLK 1  a of  FIG. 2 , and each has a high voltage level that is very close to Vdd and a low voltage that is very close to VSS. 
   The charge pump system of  FIG. 4  operates as follows. While the first clock CLK 1  is low, cell  1  conducts because the first condition is true for cell  1   98   a . This causes the voltage on the output node of the cell to become close to Vdd. When the first clock CLK 1  transitions high, cell  1  blocks, because the second condition is now true for the cell, and a charge close to 2Vdd is now present on the output of cell  1 . When the first clock CLK  1  is high, the second clock CLK 2  is low, so now cell  2  is conducting and a voltage 2Vdd is transferred to the output of cell  2 . When CLK  1  transitions low, the second clock CLK 2  become high and now the output of cell  2  has 3Vdd. 
   It is now easy to see that when CLK  1  is low, every other cell, beginning with cell  1 , is conducting while the intervening cells are blocking. When CLK  1  is high the situation reverses. The result is that, after at least as many clocks cycles as there are cells, the output of each cell is boosted by an additional voltage Vdd. Thus, the output of the last cell is very close to Ncell·Vdd, where Ncell is the number of cells. 
     FIG. 5  shows clock circuitry  140  for use with the charge pump of FIG.  3  and charge pump system of FIG.  4 . Clock circuitry  140  and threshold detection circuitry  142  are used to provide the non-overlapping first and second clocks CLK 1  CLK 2 . The clock circuitry  140  includes energy storage circuitry  144 , control circuitry  146 , initialization circuitry  148  and adaptive circuitry  150 . The energy storage circuitry  144 , after initialization, provides an oscillating power source on node X 2  at a frequency determined by the either the control circuitry  146  or the adaptive circuitry  150 , one of which receives a reference clock  152  having a known frequency. The adaptive circuitry  150  maintains the amplitude of the oscillations, by transferring energy from the power supply (+Voltage Rail, −Voltage Rail) to the energy storage circuitry  144  to make up for dissipative losses in the clock circuitry and the circuitry that operates from the energy provided by the clocks. 
   An embodiment of the clock circuitry  140  is shown in FIG.  6 . The initialization circuitry  264  connects to the energy storage circuitry  262  to initialize oscillations in the energy storage circuitry  262 . The control circuitry  260 , which includes a phase detector  256  and a tuning circuit  258 , connects to the output node X 2  of the energy storage circuitry  262  and to a reference clock  274  to control the frequency of the oscillations in the energy storage circuitry  262 . The adaptive circuitry  266  also connects to the output X 2  of the energy storage circuitry  262  along with the effective circuit model of the logic circuitry  268 . The effective circuit model may include discharge path  160  and precharge path  162  of FIG.  7 . Paths of any circuitry are modeled as an equivalent series RC circuit, with the equivalent Reff representing the dissipative portion of such circuitry and Ceff representing the capacitive portion of such circuitry including load capacitance. 
   In the energy storage circuitry  262 , there are two capacitors Co′  252   a  and C 1   252   b , where C 1  is much smaller than Co′. The junction I between the two provides a point of control for the initialization circuitry  264 . 
   The initialization circuitry  264  includes an inverter circuit  254  that is connected to the output of the energy storage circuitry  262  and the junction I of the C 1   252   b  and Co′  252   a  capacitances. A reset line  202  controls whether the inverter  254  has a high-impedance output or a low impedance output, which is the inversion of the input. When the reset line  202  is active, the inverter  254  is in the low impedance output state, which causes the energy storage circuit  262  to oscillate. When the reset line  202  is deactivated, the inverter  254  changes to a high-impedance output and the resonant circuit continues to oscillate on its own with a frequency that is controlled by C 1 , Co′, Ceff and the output, Cx, of the tuning circuit. 
   As mentioned above, the control circuitry  260  includes a phase detector  256  and a tuning circuit  258  that together cause the frequency of the energy storage circuitry oscillations to be equal to the reference clock  274 . Phase detector  256  receives the reference clock  274  and the output X 2  of the energy storage circuitry  262 , compares the two to control the tuning circuit  258  that modifies the frequency of the energy storage circuitry  262  to be the same as frequency of the reference clock  274 . 
   Adaptive circuitry  266  is also connected to the output X 2  of the energy storage circuitry  262  to replenish energy that is dissipated in the logic circuitry  268 , modeled as an effective resistance Reff and effective capacitance Ceff. 
   In operation, the energy storage circuitry  262  begins oscillating at its natural resonant frequency after the deactivation of the reset line  202 . The natural resonant frequency is related inversely to the square root of the product of L and the value of (Co′∥C 1 ∥Ceff), where ‘x∥y’ is defined as the quantity xy/(x+y). If C 1 ′ is much smaller than the other capacitances, then it is the capacitance that influences the natural resonant frequency the most (because (Co′∥C 1 ∥ Ceff) is approximately equal to C 1 ′). Once started, the energy storage circuitry is then locked to the reference clock input by the phase detector  256  and tuning circuit  258 . The phase detector  256  detects a phase difference between the energy storage circuitry frequency and the reference clock and converts this difference into a signal Z that controls the tuning circuit  258 . The tuning circuit  258  then alters the oscillation frequency of the energy storage circuitry  262  by adding either inductance or capacitance into the energy storage circuitry  262  so as to drive the phase difference towards zero. If the amplitude of the oscillations of the energy storage circuit begin to diminish in amplitude, then adaptive circuitry  266  is activated to provide a synchronous energy boost to the oscillations, thereby restoring the amplitude. 
   The clock circuitry  140  uses very little power because power provided by the clock circuitry to circuitry external to it is returned back to the clock circuitry to once again be supplied by the clock circuitry. In other words, a substantial portion of the energy that the clock circuitry provides is recycled back to the clock circuitry. This means that the power supply need only supply the dissipative losses of the clock circuitry and the external circuitry. 
   Clock circuitry  140  can also be used to reduce the power dissipated by the charge pump circuit  50  of FIG.  2 . The circuit  50  is modified to receive the four clocks from two clock circuitry blocks  140 . One clock circuitry block provides CLK 1  and CLK 1 _a, and the other clock circuitry block provides CLK 2  and CLK 2 _a. Threshold detection circuitry, connected to the clock circuitry, determines the phases and degree of overlap of the four clocks. 
   Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.