Abstract:
An image sensor includes (a) a plurality of pixels, wherein each pixel comprises:(i) at least one photosensor; (ii) at least one transfer gate connecting the photosensor to a floating diffusion; (iii) an output transistor connected to the floating diffusion; (iv) a first reset transistor connected between the floating diffusion and a summing node; (v) a second reset transistor connected to the summing node; and (b) a first summing transistor connecting together the summing nodes of two or more pixels.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to electronic image sensors for use in digital cameras and other types of imaging devices, and more particularly to charge domain summing of photogenerated charge. 
       BACKGROUND OF THE INVENTION 
       [0002]      FIG. 1  shows the schematic of a prior art array of pixels  210 . Each pixel  210  has one photodiode  205 . Charge collected by the photodiode  205  is transferred to a floating diffusion  204  by the transistor  203 . Transistor  203  transfers charge to the floating diffusion  204  when the control gate signal of the transfer gate is activated. All the transfer gate control gates of transistors  203  are connected together within each row of pixels  210 . Transistor  202  buffers the voltage between the floating diffusion  204  and the output column signal wire. Some variations of the pixel  210  will have a row select transistor (not shown) between the transistor  202  and the column output wire. A row select transistor may also be placed between transistor  202  and the power supply (or some other voltage source) wire. A reset transistor  200  is used to reset the floating diffusion  204  to the power supply voltage. All of the reset transistor  200  gates are connected together within each row of pixels  210 . 
         [0003]    Summing together photogenerated charge between pixels can change the resolution of the pixel array. Activating transistors  206  that connect adjacent floating diffusions  204  across a row sums together the charge stored on the floating diffusions  204 . Activating the vertical summing transistors  207  sums the charge along the columns. 
         [0004]    The summing of charge is desirable when the pixel array needs to be read out at a higher frame rate for video applications. It also effectively creates a larger pixel for better light sensitivity. U.S. Pat. No. 7,071,980 and U.S. Patent Application US2006/0274176 are examples of pixel summing using circuits similar to  FIG. 1 . This method of charge summing is not optimum because the summing transistors  206  and  207  are connected directly to the floating diffusions  204 . These extra transistors add capacitance to the floating diffusions  204 . The voltage change, V, on the floating diffusion  204  is given by the equation V=Q/C where Q is the amount of charge, and C is the floating diffusion  204  capacitance. The increased capacitance C of the floating diffusion  204  caused by the summing transistors  206  and  207  causes a smaller voltage change, V. A smaller voltage change means is will be harder to detect small amounts of photogenerated charge than if there were no summing transistors present. 
         [0005]    U.S. Pat. Nos. 6,452,153 and 6,878,918 avoid the problem of summing transistors that causes increased floating diffusion capacitance.  FIG. 2  shows a schematic demonstrating the prior art. 
         [0006]    Each pixel  310  has one photodiode  305 . Charge collected by the photodiode  305  is transferred to a floating diffusion  304  by the transistor  303 . Transistor  303  transfers charge to the floating diffusion  304  when the transfer gate control gate signal is activated. All the transfer gate control gates of transistors  303  are connected together within each row of pixels  310 . Transistor  302  buffers the voltage between the floating diffusion  304  and the output column signal wire. Some variations of the pixel  310  will have a row select transistor (not shown) between the transistor  302  and the column output wire. A row select transistor may also be placed between transistor  302  and the power supply wire (or some other voltage source). Reset transistor  300  is used to reset the floating diffusion  304  to the power supply voltage. All of the reset transistor  300  gates are connected together within each row of pixels  310 . 
         [0007]    There are horizontal summing transistors  306  and vertical summing transistors  307  that when activated, cause charge to be shared between the photodiodes  305 . Because the summing transistors  306  and  307  are connected to the photodiodes  205  and not the floating diffusions  304 , the floating diffusion  304  capacitances are not increased. 
         [0008]    This disadvantage of this approach to charge summing is that it is very difficult to transfer all charge out of the photodiodes when the summing transistors are turned on. Incomplete charge transfer results in poor signal linearity response and image defects. 
         [0009]    U.S. Pat. No. 6,914,227 solves the previously mentioned problems by inserting a second amplifier into each pixel to isolate summing transistors from the floating diffusions. However, the extra amplifier adds extra noise to the signal. 
         [0010]    The present invention discovered that it is desirable to sum together photogenerated charges in a pixel with the minimum possible floating diffusion capacitance and minimum possible amplifier signal noise. The present invention described herein will also address the deficiencies of the prior art. 
       SUMMARY OF THE INVENTION 
       [0011]    According to one aspect of the present invention, the invention resides in an image sensor comprising: (a) a plurality of pixels, wherein each pixel comprises: (i) at least one photosensor; (ii) at least one transfer gate connecting the photosensor to a floating diffusion; (iii) an output transistor connected to the floating diffusion; (iv) a first reset transistor connected between the floating diffusion and a summing node; (v) a second reset transistor connected to the summing node; and (b) a first summing transistor connecting together the summing nodes of two or more pixels. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The above and other objects, features, and advantages of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical features that are common to the figures, and wherein: 
           [0013]      FIG. 1  is prior art image sensor showing charge summing by placing summing transistors between floating diffusions; 
           [0014]      FIG. 2 . is prior art image sensor showing charge summing by placing summing transistors between photodiodes; 
           [0015]      FIG. 3 . is the preferred embodiment of the present invention showing summing transistors between summing nodes isolated from the floating diffusion; 
           [0016]      FIGS. 4   a  and  4   b  are alternative embodiments of the present invention; 
           [0017]      FIG. 5  is a top view of the image sensor array of the present invention; and 
           [0018]      FIG. 6  is an imaging system of the present invention containing the image sensor array of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]      FIG. 3  shows a schematic of the preferred embodiment of the invention. Each pixel  110  has one photodiode  105 . Charge collected by the photodiode  105  is transferred to a floating diffusion  104  by the transistor  103 . Although only one photodiode  105  and transfer transistor  103  are shown, the principle of operation of the present invention is not altered by adding additional transfer transistors and photodiodes to the pixel that share a common floating diffusion  104 . Transistor  103  transfers charge to the floating diffusion  104  when the transfer gate control gate signal is activated. All the transfer gate control gates of transistors  103  are connected together within each row of pixels  110 . Transistor  102  buffers the voltage between the floating diffusion  104  and the output column signal wire. Some variations of the pixel  110  will have a row select transistor (described later in reference to  FIG. 4   a ) between the transistor  102  and the column output wire. A row select transistor (described in reference to  FIG. 4   b ) may also be placed between transistor  102  and the power supply wire. There are two reset transistors  100  and  101  to reset the floating diffusion  104  to the power supply voltage. The floating diffusion  104  is reset when both RG 1  and RG 2  signals are activated at the same time. All of the reset transistor  100  gates are connected together within each row of pixels  110 . All of the reset transistor  101  gates are connected together within each row of pixels  110 . 
         [0020]    There are horizontal summing transistors  106  that connect the summing nodes  108  of each pixel along a row. There are also vertical summing transistors  107  that connect the summing nodes  108  of each pixel along a column. It is noted that the summing nodes  108  are isolated from the floating diffusions  104  by transistor  101 . The summing transistors  106  and  107  do not increase the floating diffusion  104  capacitance. Therefore the present invention will have better low signal response than the prior art. 
         [0021]    To sum together two pixels, signal HB 1  on transistor  106  would be activated at the same time as signal RG 2  on transistor  101 . When those transistors are activated at the same time, the floating diffusions will sum (share) charge. For full resolution read out the summing transistors and reset transistors  101  would not be activated. With this circuit, the floating diffusion has two transistor drains and one transistor gate capacitance, the minimum capacitance possible. This minimum capacitance provides for the largest possible voltage change on the floating diffusion  104  for a given amount of charge. The prior art has more than two drains connected to a floating diffusion, and as a result, more capacitance. 
         [0022]    If the photodiode  105  has more photogenerated charge than what will fit onto the floating diffusion, then the first reset transistor  101  can be activated while summing transistors  106  and  107  are not activated. That will increase the floating diffusion  104  capacitance so it can hold more charge. 
         [0023]    The summing transistors  106  and  107  do not have to be connected to adjacent pixels. In the case of a color image sensor, the summing transistors  106  and  107  may skip across pixels for purposes of connecting together pixels of the same color. The summing transistors  106  and  107  may be activated in a pattern to sum any arbitrary number of pixels together to form an image sensor of arbitrary resolution. All summing transistors  106  and  107  may even be activated simultaneously to sample every pixel in the imager simultaneously for purposes of rapid exposure metering in a camera. Summing transistors  106  and  107  can also be activated in conjunction with transistors  101  to increase the floating diffusion capacitance even more without summing charge. This would be done if the pixel is very large and the photodiode  105  hold large amounts of charge. 
         [0024]      FIG. 4   a  and  FIG. 4   b  show alternative embodiments of the present invention with the addition of a row select transistor  112 . These embodiments are the same as  FIG. 3  except for the addition of the row select transistor. In  FIG. 4   b  the row select transistor  112  is placed between the output transistor  102  and the power supply wire. In  FIG. 4   a  the row select transistor  112  is placed between the output transistor  102  and the output wire. The pixel summing operation is identical to what was described for  FIG. 3 . 
         [0025]    Referring to  FIG. 5 , there is shown the image sensor array  400  of the present invention having a pixel array  405  that includes the plurality of pixels  110 . Each pixel  110  includes the components as described in  FIG. 3  or alternatively as described in  FIGS. 4   a  and  4   b . The image sensor array  400  includes a substrate  410  in which the pixels  110  are disposed. 
         [0026]    Referring to  FIG. 6 , there is shown a block diagram of an imaging system that can be used with the image sensor  1212  of present the invention. Imaging system  1200  includes digital camera phone  1202  and computing device  1204 . Digital camera phone  1202  is an example of an image capture device that can use an image sensor incorporating the present invention. Other types of image capture devices can also be used with the present invention, such as, for example, digital still cameras and digital video camcorders. 
         [0027]    Digital camera phone  1202  is a portable, handheld, battery-operated device in an embodiment in accordance with the invention. Digital camera phone  1202  produces digital images that are stored in memory  1206 , which can be, for example, an internal Flash EPROM memory or a removable memory card. Other types of digital image storage media, such as magnetic hard drives, magnetic tape, or optical disks, can alternatively be used to implement memory  1206 . 
         [0028]    Digital camera phone  1202  uses lens  1208  to focus light from a scene (not shown) onto image sensor array  300  of image sensor  1212 . Image sensor array  300  provides color image information using the Bayer color filter pattern in an embodiment in accordance with the invention. Image sensor array  300  is controlled by timing generator  1214 , which also controls flash  1216  in order to illuminate the scene when the ambient illumination is low. 
         [0029]    The analog output signals output from the image sensor array  300  are amplified and converted to digital data by analog-to-digital (A/D) converter circuit  1218 . The digital data are stored in buffer memory  1220  and subsequently processed by digital processor  1222 . Digital processor  1222  is controlled by the firmware stored in firmware memory  1224 , which can be flash EPROM memory. Digital processor  1222  includes real-time clock  1226 , which keeps the date and time even when digital camera phone  1202  and digital processor  1222  are in a low power state. The processed digital image files are stored in memory  1206 . Memory  1206  can also store other types of data, such as, for example, music files (e.g. MP3 files), ring tones, phone numbers, calendars, and to-do lists. 
         [0030]    In one embodiment in accordance with the invention, digital camera phone  1202  captures still images. Digital processor  1222  performs color interpolation followed by color and tone correction, in order to produce rendered sRGB image data. The rendered sRGB image data are then compressed and stored as an image file in memory  1206 . By way of example only, the image data can be compressed pursuant to the JPEG format, which uses the known “Exif” image format. This format includes an Exif application segment that stores particular image metadata using various TIFF tags. Separate TIFF tags can be used, for example, to store the date and time the picture was captured, the lens f/number and other camera settings, and to store image captions. 
         [0031]    Digital processor  1222  produces different image sizes that are selected by the user in an embodiment in accordance with the invention. One such size is the low-resolution “thumbnail” size image. Generating thumbnail-size images is described in commonly assigned U.S. Pat. No. 5,164,831, entitled “Electronic Still Camera Providing Multi-Format Storage of Full and Reduced Resolution Images” to Kuchta, et al. The thumbnail image is stored in RAM memory  1228  and supplied to display  1230 , which can be, for example, an active matrix LCD or organic light emitting diode (OLED). Generating thumbnail size images allows the captured images to be reviewed quickly on color display  1230 . 
         [0032]    In another embodiment in accordance with the invention, digital camera phone  1202  also produces and stores video clips. A video clip is produced by summing multiple pixels of image sensor array  1210  together (e.g. summing pixels of the same color within each 4 column×4 row area of the image sensor array  1210 ) to create a lower resolution video image frame. The video image frames are read from image sensor array  1210  at regular intervals, for example, using a 15 frame per second readout rate. 
         [0033]    Audio codec  1232  is connected to digital processor  1222  and receives an audio signal from microphone (Mic)  1234 . Audio codec  1232  also provides an audio signal to speaker  1236 . These components are used both for telephone conversations and to record and playback an audio track, along with a video sequence or still image. 
         [0034]    Speaker  1236  is also used to inform the user of an incoming phone call in an embodiment in accordance with the invention. This can be done using a standard ring tone stored in firmware memory  1224 , or by using a custom ring-tone downloaded from mobile phone network  1238  and stored in memory  1206 . In addition, a vibration device (not shown) can be used to provide a silent (e.g. non-audible) notification of an incoming phone call. 
         [0035]    Digital processor  1222  is connected to wireless modem  1240 , which enables digital camera phone  1202  to transmit and receive information via radio frequency (RF) channel  1242 . Wireless modem  1240  communicates with mobile phone network  1238  using another RF link (not shown), such as a 3GSM network. Mobile phone network  1238  communicates with photo service provider  1244 , which stores digital images uploaded from digital camera phone  1202 . Other devices, including computing device  1204 , access these images via the Internet  1246 . Mobile phone network  1238  also connects to a standard telephone network (not shown) in order to provide normal telephone service in an embodiment in accordance with the invention. 
         [0036]    A graphical user interface (not shown) is displayed on display  1230  and controlled by user controls  1248 . User controls  1248  include dedicated push buttons (e.g. a telephone keypad) to dial a phone number, a control to set the mode (e.g. “phone” mode, “calendar” mode” “camera” mode), a joystick controller that includes 4-way control (up, down, left, right) and a push-button center “OK” or “select” switch, in embodiments in accordance with the invention. 
         [0037]    Dock  1250  recharges the batteries (not shown) in digital camera phone  1202 . Dock  1250  connects digital camera phone  1202  to computing device  1204  via dock interface  1252 . Dock interface  1252  is implemented as wired interface, such as a USB interface, in an embodiment in accordance with the invention. Alternatively, in other embodiments in accordance with the invention, dock interface  1252  is implemented as a wireless interface, such as a Bluetooth or an IEEE 802.11b wireless interface. Dock interface  1252  is used to download images from memory  1206  to computing device  1204 . Dock interface  1252  is also used to transfer calendar information from computing device  1204  to memory  1206  in digital camera phone  1202 . 
         [0038]    The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. 
       PARTS LIST 
       [0000]    
       
           100  reset transistor 
           101  reset transistor 
           102  transistor 
           103  transistor 
           104  floating diffusion 
           105  photodiode 
           106  summing transistor 
           107  summing transistor 
           108  summing nodes 
           110  pixel 
           112  row select transistor 
           200  reset transistor 
           202  transistor 
           203  transistor 
           204  floating diffusion 
           205  photodiode 
           206  summing transistor 
           207  summing transistor 
           210  pixel 
           300  reset transistor 
           302  transistor 
           303  transistor 
           304  floating diffusion 
           305  photodiode 
           306  summing transistors 
           307  summing transistors 
           310  pixel 
           400  image sensor array 
           405  pixel array 
           410  substrate 
           1200  imaging system 
           1202  digital camera phone 
           1204  computing device 
           1206  memory 
           1208  lens 
           1212  image sensor 
           1214  timing generator 
           1216  flash 
           1218  A/D converter circuit 
           1220  buffer memory 
           1222  digital processor 
           1224  firmware memory 
           1226  clock 
           1228  RAM memory 
           1230  color display 
           1232  audio codec 
           1234  microphone 
           1236  speaker 
           1238  mobile phone network 
           1240  wireless modem 
           1242  RF Channel 
           1244  photo service provider 
           1246  Internet 
           1248  user controls 
           1250  dock 
           1252  dock interface