Abstract:
The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a process for manufacturing a semiconductor device comprising an empty trench structure, and a semiconductor device obtained with said process. 
         [0003]    2. Description of the Related Art 
         [0004]    In the present context, the term “empty trench” refers to the fact that the trench (or some other cavity of any shape) is not filled, irrespective of the conditions of pressure existing inside the trench itself. 
         [0005]    In semiconductors devices it is at times required to provide an empty trench. For example, empty-channel transistor devices are under study (also called “microminiature vacuum tubes” or “vacuum microelectronic devices”—VMDs) present in which is a very deep trench closed at the top by a layer of metal, for example aluminum, which operates as ion-emitter element. 
         [0006]    An example of an embodiment of an empty trench microelectronic device and its manufacturing method are described, for example, in U.S. Patent Publication No. 2014/0353576 in the name of the present applicant, as described hereinafter. 
         [0007]    With reference to  FIG. 1 , an empty trench device  1  comprises a substrate  2  of heavily doped semiconductor material, such as silicon, a stack  3  of layers  4 - 6 , which extends above the substrate  1 , a trench or hole  10 , which extends throughout the thickness of the stack  3 , as far as the substrate  1 , and a cathode metal region  11 , which extends above the stack  3  and closes the trench  10  at the top. The trench  10  is here in a condition of negative pressure, and is thus defined as “vacuum hole”. 
         [0008]    The stack  3  of layers here comprises a first insulating layer  4  on the substrate  2 , a semiconductor layer  5 , made, for example, of polycrystalline silicon, and a second insulating layer  6 , on the semiconductor layer  5 . 
         [0009]    A contact structure  12  is formed above the cathode metal region  11 , and an anode metal layer  13  extends underneath the substrate  2 . 
         [0010]    A passivation layer  15 , of silicon nitride, coats the side walls of the trench  10 . 
         [0011]    The device  1  is obtained as follows: the layers  4 - 6  are deposited in sequence on the substrate  2 ; then, using a resist mask, the layers  4 - 6  are chemically etched in sequence in different apparatuses and using appropriate etching solutions. Next, the passivation layer  15  is deposited, in a highly conformable way, and is then removed from the bottom of the trench  10  and from the external part of the trench  10 , above the second insulating layer  6 . Then a metal layer, made for example of aluminum, that closes the trench  10  at the top and forms the cathode metal region  11  is deposited in a non-conformable way and shaped lithographically. 
         [0012]    In the practical manufacture of the device, there have been noted difficulties in deposition of the metal layer that is to form the cathode metal region  11 . In fact, even using non-conformable material and deposition techniques, it is not always possible to guarantee that the metal does not penetrate extensively within the trench  10 . Furthermore, the presence of metal particles inside the trench is disadvantageous given that any possible metal traces in the trench  10  may give rise to leakage that cannot be easily distinguished from emissions of the cathode metal region, resulting in an improper operation of the device. 
         [0013]    It is thus desirable for the metal layer (which constitutes the cathode region) to extend above the trench and not penetrate therein. 
         [0014]    This requirement, also in common with other empty trench semiconductor products, is not easy to meet, given the absence of a stop structure, also taking into account the conditions of negative pressure present in certain applications. 
       BRIEF SUMMARY 
       [0015]    One or more embodiments of the present provides a process and a device that may overcome one or more of the drawbacks of the known art. 
         [0016]    According to the present disclosure, a process for manufacturing a semiconductor device comprising an empty trench structure, and a semiconductor device obtained with said process are provided, as defined in claims  1  and  12 , respectively. 
         [0017]    In one embodiment, in order to prevent penetration of metal material into the trench, during at least part of etching thereof, the products of reaction of a polymeric type, instead of being removed with the subsequent processes of resist removal, are left, as deposited, on the walls of the trench. In this way, on these, a passivation layer is formed, which, in the proximity of the open end or mouth of the trench, forms a sort of narrowing that restricts the area of the mouth itself. By modulating appropriately the etching conditions, said narrowing forms a “collar” element that prevents penetration of the metal material, for example aluminum, into the trench during the subsequent step of deposition of the cathode layer. In addition, the collar forms a sort of “mold”, which gives rise to a tip shape of the cathode region, which optimizes the performance of the finished device. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0018]    For a better understanding of the present disclosure, a preferred embodiment thereof is now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
           [0019]      FIG. 1  is a cross-section through a vacuum microelectronic device (VMD); 
           [0020]      FIGS. 2-6  show cross-sections through a wafer of semiconductor material in successive steps of manufacturing of a vacuum microelectronic device, according to one embodiment of the present process; and 
           [0021]      FIG. 7  is a cross-sectional view through an embodiment of the present microelectronic device. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    An embodiment of the present process for manufacturing the above device is described hereinafter, with reference to  FIGS. 2-7 . 
         [0023]    In particular, the process described regards manufacture of an empty trench microelectronic semiconductor device, such as a diode, a triode, a tetrode, a pentode or some other device having a similar basic structure. 
         [0024]    Initially ( FIG. 2 ), on a substrate  31 , of heavily doped semiconductor material, such as monocrystalline silicon, a stack  32  of layers is formed. The ensemble constituted by the substrate  31  and the stack  32  forms a body  30 , for example a wafer. 
         [0025]    The substrate  31  is typically of an N type, for example doped with phosphorus, and has a resistivity of approximately 4 mΩ·cm. 
         [0026]    The stack  32  here comprises a first insulating layer  33 , a conductive layer  34 , and a second insulating layer  35 . 
         [0027]    For example, the first insulating layer  33  is made of tetraethylorthosilicate (TEOS) formed by chemical vapor deposition (CVD) with a thickness of, for example, approximately 1 μm. 
         [0028]    The conductive layer  34  is, for example, made of semiconductor material such as polycrystalline silicon of an N type, doped with phosphorus and having a thickness of approximately 0.5 μm. The conductive layer  34  is, for example, deposited via low-temperature chemical vapor deposition (LTCVD) and may have a resistivity comprised between 10 and 100 mΩ·cm. The conductive layer  34  is generally defined after it has been deposited for forming a control grid, in a way not shown. 
         [0029]    The second insulating layer  35  is, for example, made of TEOS, which is also deposited via CVD and may have a thickness of approximately 0.5 μm, in such a way that the stack  32  has an overall thickness of approximately 2 μm. 
         [0030]    As shown in  FIG. 3 , on the stack  32  a masking layer  36  is laid, of a thickness of approximately 0.5 μm. For example, the masking layer  36  is made of AlSiCu. 
         [0031]    As shown in  FIG. 4 , the masking layer  36  is shaped photolithographically, for forming a hard mask  40 , of metal material, having an opening  38  of a shape and width corresponding to the ones desired for the trench to be obtained. For example, the trench  41  may have a circular shape having a width of approximately 0.6 μm. 
         [0032]    Using the hard mask  40 , a trench etch is carried out, with selective removal of the stack  32 . In particular, a reactive ion etch (RIE) is carried out, of a type generally used for dry etching of oxides. In particular, here, the trench etch uses an etching chemistry rich in CF 4  and with low selectivity in regard to silicon, which is the same for all the layers  33 - 35  of the stack  32 . According to one embodiment, initially etching of the second insulating layer  35  and of the conductive layer  34  is carried out, then a washing treatment in amine solvent is performed, using spray equipment, and finally etching of the first insulating layer  33  is carried out, using the same etching solution as previously and the same machine. 
         [0033]    For example, for the etch, the machine MXP+ manufactured by Applied Materials, Inc., may be used at a low pressure (for example, comprised between 10 −2  and 1 Torr, in particular approximately 0.2 Torr), with application of a magnetic field of 10 Gauss and using a gas of CF 4 , Ar, CH F 3 , and O 2 . According to an embodiment of the present process, for the etching step, a flow of CF 4  is used that is greater than, for example three times, that of CH F 3 . In particular, the flow of CF 4  may be comprised between 40 and 50 sccm, and the flow of CHF 3  may be comprised between 10 and 20 sccm. During the plasma-etching reaction, as is known, polymeric by-products are produced, with a base of C and F, the majority of which is generally expelled and removed the structures being defined, by an appropriate choice of the pressure and of the flow of the etching gases. 
         [0034]    In the process described, instead, the parameters are studied so that said by-products, during the expulsion process, deposit with a particular pattern on the walls of the structure just defined. In fact, with the values of flow indicated, as the trench  41  is formed, on the walls of this residue deposits, thus forming a passivation layer  42 . 
         [0035]    According to one embodiment, the etching step is divided into two parts. Initially, an etch of the second insulating layer  35  and of the conductive layer  34  is carried out, also referred to hereinafter as “pre-etch”. Then a washing treatment in amine solvent is carried out, using spray equipment, and finally the first insulating layer  33  is etched, using the same previous etching solution and the same machine, in particular the solution and the machine indicated above. 
         [0036]    Consequently, in this case, the by-products accumulating on the walls during the first etching step are removed by washing, and the passivation layer  42  is only formed during the second etching step, after washing. Other etching/washing steps or a single etch are, however, possible, as will be clear to a person skilled in the art, on the basis of the desired geometries, the used machines, and possibly on the basis of trials. In case of multiple etches, use of the same etching conditions in the various steps simplifies the operations and reduces the manufacturing costs. 
         [0037]    As shown in  FIG. 5 , the passivation layer  42  that forms does not have a uniform thickness, but thickens in proximity of an open end or the mouth of the trench  41 , where it forms a sort of restriction or collar element  45  having a profile that is bulging or approximately shaped as a toroid quarter in the top part, facing the outside of the trench  41 . For example, in tests carried out by the present applicant, the passivation layer  42  has a thickness ranging between 0.05 μm and 0.2 μm, and the collar element  45  has a thickness of approximately 0.25 μm. 
         [0038]    Etching is carried out for a fixed time, for example 200 s, removing the entire thickness of the stack  32 , with a possible minor etching of the substrate  31  (not shown). 
         [0039]    Performing an etch using just a chemistry, with the hard mask  40  of metal material, enables the profile of the trench  41  to be particularly smooth and uniform, without significant steps at the interface between the layers  33 - 35 , thus facilitating formation of the passivation layer  42  and coating, by the latter, of the wall of the trench  41 , in particular in the area of the conductive layer  34 . 
         [0040]    As shown in  FIG. 6 , a cathode layer  46  is deposited. For example, an aluminum layer with a thickness of approximately 3 μm is laid with a non-uniform deposition technique, typically sputtering at a low temperature, less than 300° C. By virtue of the shape of the collar  45 , the cathode layer  46  cannot penetrate into the trench  41  and has a tip-shaped or cusp-shaped portion  47  in proximity of the mouth of the trench  41 . 
         [0041]    When it is desired to form a device wherein the trench is in a negative pressure or vacuum condition, deposition of the cathode layer  46  may be carried out in a high-vacuum environment, for example between 10 −7  and 10 −8  Torr. 
         [0042]    Finally as shown in  FIG. 7 , the cathode layer  46  is defined, in a not shown manner. In a known way, a cathode contact  48  (and possibly grid contacts, not shown, for contacting the conductive layer  34 ) is formed above the cathode layer  46 , and an anode contact  49  is formed under the substrate  49 . An empty trench device  50  is thus obtained. Then, the usual passivation steps follow. 
         [0043]    The described process and the finished device thereby obtained have numerous advantages. 
         [0044]    In fact, due to the presence of the restriction element or collar  45 , the trench device  50  does not have any metal intrusions inside the trench  41 . Moreover, the cathode layer  46  has a tip-shaped portion  47  having an optimal shape for emission of charges during operation of the device. 
         [0045]    The wall of the trench  41  is particularly uniform and without steps, ensuring passivation of the conductive layer  34  and thus electrical insulation thereof, which is necessary for proper operation of the device as integrated microminiature vacuum tube. 
         [0046]    Finally, it is clear that modifications and variations may be made to the process and the device described and illustrated herein, without thereby departing from the scope of the present disclosure. 
         [0047]    For instance, even though the described example refers to formation of a trench in a stack of layers, the same approach can be adopted for forming openings and cavities in even single layers. 
         [0048]    Moreover the trench may have any shape. 
         [0049]    As indicated, the number of etching steps may vary according to the specific conditions. In case of successive etches followed by washing, the etching steps may be carried out with different parameters. In particular, in the first etching step or steps, the parameters may be standard, with automatic removal of the by-products, if so desired. 
         [0050]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.