Abstract:
A method and apparatus for detecting imaging measuring points which have a defined signal progression for testing an integrated circuit and wherein the signals at the measuring points have a defined signal progression and wherein a secondary particle signal is generated using a scanning particle microscope and which makes it possible to quickly locate a measuring point in an integrated circuit at which a defined signal is present or, respectively, assuming there are faults in the electronic modules to identify whether a defined signal has potentially failed and wherein the measured secondary particle signal is compared to the anticipated signal. The comparison can occur using a correlation method and the correlation can be accomplished with the assistance of an electronic correlator or also with the assistance of the particle beam itself. When the particle beam itself is used, the particle beam is modulated with the anticipated signal progression and the resulting secondary particle signal is integrated.

Description:
This is a division of application Ser. No. 760,574, filed July 30, 1985, now U.S. Pat. No. 4,771,235. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates in general to method and apparatus for detecting and imaging one or more measuring points which have a defined signal progression, as for example, in an integrated circuit. 
     2. Description of the Prior Art 
     When testing integrated circuits to locate faculty circuits it is desired to compare the characteristic of the integrated circuit to the rated characteristic so as to locate faults in the circuit. For this purpose, a check must be performed to see whether specific signal progressions are present at one or more measuring points within the integrated circuit. 
     There are five methods for making checks that have been disclosed by the prior art. The method of the so-called &#34;voltage coding&#34; is described in &#34;Scanning Electron Microscopy&#34; 1975 part I, Processing of the Eighth Annual Scanning Electron Microscope Symposium, Chicago, IIT Research Institute, Pages 465-471. The &#34;voltage coding&#34; method forms the dynamic voltage distribution of an integrated circuit on a video monitor. The &#34;voltage coding&#34; method enables a chronological allocation of the logic states of the various components and is therefore particularly suited for a fast function check of integrated circuits. The most serious disadvantage of this method is that it has a low upper limit frequency. 
     U.S. Pat. No. 4,223,220 disclosed the so-called &#34;logic state mapping&#34;. In such &#34;logic state mapping&#34; method, the dynamic voltage distribution is imaged with the assistance of a stroboscope effect. This &#34;logic state mapping&#34; method supplies a chronological resolution which is higher by orders of magnitude as compared to the &#34;voltage coding&#34; method given the same voltage resolution. The &#34;logic state mapping&#34; method also simplifies recording since the imaging of the dynamic voltage distribution can be photographed directly from the photo picture screen of a scanning electron microscope. In the &#34;voltage coding&#34; method by contrast a recording is only possible with a tape storage or with photos of a video monitor. 
     A third method which is disclosed in Feuerbaum, Electron Beam Testing Methods and Applications, Scanning, Vol. 5, 1983 pages 14-24 which is referred to as a &#34;waveform&#34; measurement, it is possible to measure the chronological signal progression as a measuring point. By means of employing a sampling method, this method makes it possible to also record extremely fast signal progressions with high chronological resolution. However, the measurement is extremely lengthy requiring several minutes and is relatively complicated. 
     It is also known with the assistance of two further methods to locate the measuring points which carry the periodic signals of specific frequencies. In the first of these methods, described in J. P. Collin in Proceedings of Jornees d&#39;Electronique 1983, &#34;Testing Complex Integrated Circuits: A Challenge&#34;, edited by the Swiss Federal Institute of Technology, Lausanne, Switzerland, Pages 283-298, Title: &#34;Une Alternative Economique au Contraste Potentiel Stroboscopique: Le Traitement du Signal d&#39;Electrons Secondaires d&#39;un Microscope a Balayage&#34;, the location of defined frequencies at a measuring point is executed upon employment of a &#34;lock-in&#34; amplifier. A signal having the sought-for frequency is thereby filtered out from a voltage contrast signal acquired at a measuring point inside an integrated circuit and is filtered out with the assistance of the &#34;lock-in&#34; amplifier and the intensity of this signal is then imaged as a brightness modulation. This method, however, is extremely slow and has a very low upper limit frequency. 
     When the last of the above described methods is combined with a stroboscopic imaging method, then the bandwidth limitation can be overcome. This modified method is disclosed in H. D. Brust, F. Fox, E. Wolfgang, Frequency Mapping and Frequency Tracing: Two Novel Electron Beam Testing Methods, Vortrag auf der Microcircuit Engineering Konferenz in Berlin, September, 1984 and is referred to as &#34;frequency mapping&#34; method. The &#34;frequency mapping&#34; method similar to the method of J. P. Collin will only allow a check to be performed as to whether a signal having a defined frequency occurs at a measuring point. It provides no information as to what the actual signal progression looks like. 
     The described methods disclosed by the prior art are difficult to implement and only allow the checking of a very few or of even a single interconnection and are greatly limited in terms of their working frequency range and, thus, checking of integrated circuits is frequently not possible under normal operating conditions. Also, the methods known in the prior art are very slow and presume that the comparison of the measured and anticipated signal progression is manually undertaken or, respectively, that given signals having the same basic frequency require that an independent decision be made as to whether the anticipated signal progression is in fact present. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to describe a method and apparatus for testing integrated circuits which allows testing to be quickly performed and to check whether a defined anticipated signal progression occurs at a measuring point inside of an integrated circuit or when faulty electronic components occur to identify whether a defined signal progression can occur. 
     The object of the invention is achieved in that the signal or respectively the progression is measured at the investigated measuring point. For example, with one of the known methods of electron beam testing and is compared to the anticipated signal or, respectively, to the progression thereof. The comparison can particularly occur by means of a correlation method. The development and advantages of the invention will be further understood when considering the specification and the drawings. 
     As compared to the methods of the prior art, the method of the invention is significantly faster and allows an automatic search for a defined prescribed or measured signal progression. Also, the method can be employed up to extremely high working frequencies. A method and apparatus of the invention thus allows a fast and large area implementation of a function check or respectively error search inside an integrated circuit even under normally operating conditions. 
     Other objects, features and advantages of the invention will be readily apparent from the following description of certain preferred embodiments thereof taken in conjunction with the accompanying drawings although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure and in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating the invention; and 
     FIG. 2 is a block diagram illustrating a modification of the invention, 
     FIG. 3 illustrates a modified form of the invention; and 
     FIG. 4 illustrates a further modification of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 1 and 2 illustrate common elements which are identified with the same reference characters. Although the following exemplary embodiments refer to an electron microscope, the invention should be understood can be used with ions or other particles instead of electrons both as primary particles as well as secondary particles. Also digital signal progressions are always utilized in the following exemplary embodiments. Also, method and apparatus for the invention can be used to check a measuring point as to the existence of a defined analog signal progression as long as a suitable correlator is utilized. 
     FIG. 1 illustrates an apparatus of the invention for detecting and/or imaging a measuring point or an interconnect which has a defined signal progression. In both FIGS. 1 and 2, a scanning electron microscope can be employed and such microscope may be such as known, for example, from U.S. Pat Nos. 4,220,853, 4,220,854 or 4,277,679 for a quantitative voltage measurement and for a qualitative voltage measurement U.S. Pat. No. 4,223,220. In the apparatus of FIGS. 1 and 2, the integrated circuit IC can be replaced by any arbitrary specimen which comprises at least one measuring point which may possibly have a defined signal progression. Primary electrons PE are emitted from the electron source EG and impinge upon a measuring point or an interconnection within an integrated circuit IC and trigger secondary electrons SE. Such secondary electrons SE pass to and are detected by a detector DT. Due to the potential contrast occurring at the surface of the integrated circuit, the number of secondary electrons SE which are detected by the detector DT depends on the voltage of the integrated circuit IC at the measuring location. Depending on the secondary electron current which impinges on the detector DT, a secondary electron signal is generated by the detector DT. The output of the detector DT is supplied to a photomultiplier PM where it is amplified. The secondary electron signal which has been amplified in the photomultiplier is supplied to a pre-amplifier PA where it is further amplified and is then supplied to a circuit SV in which it is subjected to a suitable signal processing for enhancing the signal to noise ratio (for example an optimum filter) and is converted into an exclusively digital signal DSE. Such digital secondary electron signal indicates the voltage of the integrated circuit at the measuring location and is then supplied to the digital correlator KOR. 
     The illustrated internal structure of the correlator KOR is largely based on the structure of the correlator TDC model 1023J of the TRW Corporation. Other correlators can also be used in the invention. First, the anticipated reference signal RS which is to be checked to see whether it appears at the measuring location is read into the shift register SR2. The clock signal required for this position is supplied by the clock generator TG with the switch S1 being in position c. After the read in of the reference signal RS, the switch S1 is moved to switch position b and as a consequence the shift register SR2 with this reference signal RS is separated from the output of the clock generator TG. The content of the shift register SR2 remains unaltered during the execution of the check. 
     During the measurement, the secondary electron signal DSE is continuously sensed with the frequency f1 and is read into the shift register SR1. The clock signal CLK1 having the frequency f1 should therefore bye synchronous with the operating frequency of the integrated circuit. It can, for example, for acquired by means of frequency division or multiplication using a frequency divider or multiplier FP which receives the clock frequency ft of the integrated circuit IC. Since the integrated circuit IC is driven by the controller CON with a clock frequency having the frequency of ft this frequency is readily accessible and can be supplied from the controller CON to the frequency divider or multiplier FP as illustrated in FIG. 1. Fundamentally, however, any signal synchronous with the signal next to the measuring point is suitable as a clock signal CLK1 for the shift register SR1. The frequency f1 must be selected such that an adequately large time interval of the signal progression at the measuring point can be stored in the shift register SR1 and this must be at least as large as the time interval occupied by the anticipated signal progression. Using the coicidence elements EXNOR, the memory contents of the shift registers SR1 and SR2 are checked for coincidence. The number of coinciding memory locations of the shift register SR1 and SR2 is identified with the use of the summation circuit SUM and the output of such circuit is a binary number. Such binary numbers can be subsequently converted into an analog signal AS using the digital to analog converter DAW or, alternatively, can be compared to a comparison number VZ using a digital comparator KOM. When the number of coincidences is greater than VZ, then the digital output DS of the comparator KOM changes to logic 1 otherwise it is logic 0. 
     When thus a bit sequence corresponding to the reference signal RS read into the comparison shift register SR2 appears at any time in the sensed secondary electron signal DSE, then the summation circuit indicates maximum coincidence and the output DS is changed to logic 1 and the analog output AS assumes its maximum output voltage value. Since the measured secondary electron signal DSE can easily deviate from the signal at the measuring point due to noise or due to other disruptions under given conditions it may be desirable to assume that the desired reference signal RS is present although there is no complete coincidence and there is nonetheless a high grade coincidence between the reference signal RS and the measured signal DSE. The corresponding threshold, in other words, the number of coincidences which is required so as to interpret the measured signal as the sought for bit sequence can be set by adjusting the comparison number VZ. 
     In the described apparatus of FIG. 1 a check is performed to see whether the prescribed signal progression RS appears at the measuring location. In addition, insofar as a periodic signal is anticipated at the measuring location, a check can also be performed in a further development of the invention to see whether the anticipated signal RS appears at the measuring location at a defined fixed phase. Such apparatus is also shown in FIG. 1. For this purpose, the shift register SR2 is electrically connected to the reference signal RS by closing the switch S2 to form a ring shift register and is also clocked with the signal CLK1 with the switch S1 being in switch position a. The phase at which the check is to be formed to see whether the anticipated reference signal is next to the measuring location can be shifted by changing the delay time of delay element DL. Otherwise the measuring device operates in the same fashion as described previously. 
     For a large area check of an integrated circuit IC, the electron beam PE is scanned across the specimen surface of the integrated circuit. The scanning must thereby occur so slowly that a check can be performed at every measuring location at a time in which the anticipated signal can appear - that is, for example, one period given periodic signals-or, on the other hand, the check must be periodically undertaken. The output signals AS and DS then indicate whether the signal progression occurs at all or, respectively, whether it occurs in proper phase at the location which is hit by the electron beam. When the signals AS or DS are recorded depending on the measuring location using a suitable recording method as, for example, by reading it into a computer or by storing on a magnetic tape, then an image of the surface structures of the specimen integrated circuit which carry the sought-for signal progression (at all or in phase). A simple recording possibility comprises employing the signal DS for the brightness modulation of the picture tube of a scanning electron microscope. In this instance, all interconnections which carry the sought-for signal will be brightly presently. For better orientation in the two dimensional image of a specimen, it can be advantageous to add the secondary electron topography signal or some other topography signal to the output signal AS or DS in attenuated form. The method and apparatus for obtaining a topography signal is well known and is discussed in text books describing scanning electron microscopes. 
     When in the arrangement of FIG. 1, a plurality of correlators are connected in parallel then the presence of a plurality of different signal progressions can be simultaneously checked for one measuring location. For this case, the various output signals must be recorded in parallel depending on the measuring location for the large area checking of an integrated circuit IC. For this purpose, for instance, the picture tube of the scanning electron microscope can be replaced by a color picture tube and every correlator output and, thus, every reference signal progression can have a different color allocated to it. 
     The above-described measuring apparatus and techniques are not well suited for the investigation of analog signals, since the interrelationship between the voltage at the measuring location and secondary electron current is non-linear due to the voltage contrast. For the investigation of analog signal progressions, it is desirable to replace the voltage contrast by the linear energy shift of the secondary electrons SE. Using a spectrometer SP as described, for example, in U.S. Pat. No. 4,292,519, this energy shift can be converted into a corresponding secondary electron current. The secondary electron current obtained in this manner can then be further processed in the same fashion as described above. Also, a spectrometer reduces the disturbing influence due to local fields on the specimen and is also advantageous for the investigation of digital signal progression. 
     The limiting frequency of the measuring installation illustrated in FIG. 1 is essentially determined by the detector DT and generally lies in the range of 1 through 5 MHz. So as to be able to use the method of the invention at higher frequencies, the correlation can be undertaken before the detector DT. FIG. 2 illustrates such an apparatus. Here the correlation is undertaken by the electron beam itself. For this purpose, the electron beam PE is intensity modulated with the use of a beam modulating system BBS as disclosed, for example, in U.S. Pat. No. 4,169,229. The sought-for bit sequence RS sensed with the frequency f2 synchronous with the operating frequency of the integrated circuit IC is read into the shift register SR before the beginning of the measurement with the switch S in position a. During the measurement, the content of the shift register SR is cyclically shifted by the clock signal CLK2 which has a frequency f2. The output signal of the shift register is amplified by an amplifier AMP and then controls the beam modulating system BBS. When the signal progression at the beam modulating system is defined as g(t), then the intensity of the primary electron beam PE varies proportionally to g(t). The signal h(t) is next to the measuring location on the integrated circuit IC. The secondary electron current is therefore proportional to g(t) * h(t). The secondary electron current is detected by the detector DT and is amplified in the photomultiplier PM and in the pre-amplifier PA. The output signal of the pre-amplifier PA is then integrated by the integrator INT. The output signal of the integrator is proportional to ∫g(t)*h(t)*dt. Since g(t) and h(t) are both digital signals they can only assume the values of 0 or 1. When both signals coincide in the integration span in the low or respectively high values in the bit sequence and in the phase of appearance, then the value of the integral becomes maximum. The output signal of the integrator INT is thus a measure of the coincidence of the signal at the measuring location and of the reference signal RS. The integration time of the integrator must therefore be at least as great as the duration of the signal progression which is under consideration. 
     When a large area of the integrated circuit IC is to be checked, then the scanning of the specimen surface by the electron beam must occur so slowly that the beam dwells at every measuring point at least for the integration time or, on the other hand, the check must be periodically undertaken. The analog output signal AS of the integrator INT can then be recorded and, for example, be displayed on a picture screen as a component of the scanning electron microscope utilized for the apparatus of FIG. 2. For contrast enhancement, the signal AS can also be applied to the input of a comparator CM which also receives an input from a variable response threshold TH which can be set to various levels. The comparator CM converts the analog signal AS into a digital signal DS which can also control the brightness of picture tube. With such measuring installation, the employment of a spectrometer can also be advantageous for the reasons mentioned above. Under certain conditions an integrator can be omitted because for higher frequencies the detector DT and for low frequencies the picture tube of the scanning electron microscope have an integrading effect when a suitable selection of the scan speed is made. 
     In the arrangement described up to this point, the apparatus of FIG. 2 checks to see whether a defined signal progression occurs in proper phase at the measuring point under investigation. The phase at which this is investigated can be shifted by modifying the delay time of the delay element DL. The upper limit frequency of the measuring installation is defined by the beam modulating system BBS which is utilized. Beam modulating systems which operate up to the GHz range, are presently available. Such apparatus and method of the invention can therefore be utilized for inspecting integrated circuits under real operating conditions. 
     It is also possible with the arrangement of FIG. 2 to execute checks to see whether a defined signal progression is present at the measuring location independently of the phase. For this purpose, the delay element DL which must now be electronically controlled is driven by a generator GDL having a frequency f3. A delay line comprising a plurality of taps which may be a so-called &#34;tapped delay line&#34; can, for instance, be employed as the delay element DL. The output of this delay line is connected to the shift register SR through a multiplexer controlled by an analog to digital converter. When 2*Dt is the total delay of the delay element VZ, then the clock signal CLK2 is delayed Dt*(1+cos(2πf3)). The primary electron current is thus proportional to g(t+Dt*(1+cos(2πf3))). 
     When the integration time of the integrator INT is significantly shorter than the period of duration 1/2πf3 during which the primary electron current is modulated, then the output signal of the integrator INT periodically fluctuates at the frequency f3 when the reference bit sequence and the signal adjacent to the measuring location coincide. When there are only a few coincidences, then the integrator output supplies a nearly time-independent mean signal value. The amplitude of the signal fluctuation at the frequency f3 at the integrator output is therefore a measure of the coincidence of the two bit sequences. For measuring the coincidence, the signal components of the frequency f3 at the output of the integrator are filtered with the assistance of a bandpass filter BP which has a center frequency of f3 and then the amplitude is determined using an amplitude demodulator AMD which may be an envelope demodulator, for example. The analog output signal AS1 of the amplitude demodulator indicates the degree of coincidence of the two bit sequences. The signal AS1 can also be converted using a comparator CM1 with the variable threshold TH1 into a digital signal DS1 for contrast enhancement. Both signals just like the signals AS and DS can be recorded and displayed. When the integration time of the integrator INT is longer than the period duration 1/2πf3, then the signals AS and DS are direct measure for the coincidence of the signal at the measuring location and of the reference bit sequence. In this case, however, the signal to noise ratio is significantly poorer. For the reasons mentioned above, the employment of a spectrometer SP can also be advantageously utilized with the method and apparatus of FIG. 2. 
     According to a further development of the invention rather than modulating the primary electron beam PE, the secondary electron current beam SE can be modulated with a reference bit sequence RS in contrast to the measuring installations described above. An retarding field spectrometer as disclosed in U.S. Pat. No. 4,292,519 can serve as the modulator when the retarding field of the spectrometer is controlled by the reference bit sequence. Otherwise such measuring installation corresponds to that shown in FIG. 2. The advantage of this method is that no beam modulating system BBS is required. However, the obtainable limit frequency is also lower because of the relatively high capacitance of a spectrometer. A detector which has its extraction voltage controlled by the reference bit sequence can also serve for the modulation of the secondary electron beam. 
     According to a further development of the invention, the secondary electron signal is modulated with the reference bit sequence instead of the primary electron beam and it may be modulated for instance using a gate circuit. 
     In a manner similar to that described with reference to FIG. 1, it may also be advantageous in the circuits described above to add the secondary electron topography signal or some other topography signal to the respective output signal so as to improve the orientation in the two dimensional imaging of a specimen. 
     In the apparatus and method of the invention, the sought-for reference signal RS definitely need not only be acquired in a theoretical manner from simulation. It can also be measured with one of the known methods of electron beam testing at a measuring point inside the integrated circuit IC and can then be read into the shift register SR2 or the shift register SR illustrated in FIG. 2. 
     Also, the secondary electron signal at the measuring location need not necessarily occur due to voltage contrast. Any other influence of the secondary electron current by the signal at the measuring location is suitable for this purpose. An example of such alternative is the influence of the secondary electrons by magnetic fields (magnetic contrast). This, for example, can be utilized when magnetic bubble memories are used as the specimen integrated circuit IC. 
     FIG. 3 illustrates a modified form of the invention wherein the output of the amplifier AMP which receives the output of the shift register SR is applied adjacent the integrated circuit IC. The other structure of FIG. 3 is similar to that shown in FIG. 2. 
     FIG. 4 illustrates a modified form of the invention wherein the output of the amplifier AMP is supplied to a gate Gate rather than to the modulating system illustrated in FIG. 2. The other components of FIG. 4 are the same as in FIG. 2. 
     Although the invention has been described with respect to preferred embodiments, it is not to be so limited as changes and modifications can be made which are within the full intended scope of the invention as defined by the appended claims.