Abstract:
A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to U.S. Provisional Application No. 60/799,349, filed on May 11, 2006, which is incorporated by reference in its entirety herein. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    The Institute of Electrical and Electronics Engineers (IEEE) inter alia sets the standards for communication devices interchanging information using the Ethernet protocol in order to enable for example different manufacturers to produce devices complying with the same specifications and thus being compatible to each other. For example 10 BT is a well known Ethernet standard protocol for transmitting digital information at a transmission speed of 10 Mbit/s. 
         [0003]    The IEEE 802.3 standard defines the requirements for transmitting information using the 10 BT protocol on unshielded twisted pair (UTP) lines, wherein numerous details are specified in the sections of the standard. For example section 14.3 of IEEE 802.3 “MAU electrical specifications” specifies a differential output voltage between 2.2 Volts and 2.8 Volts on a load of 100 Ω. Wherein for a load with varying impedance in the range of 86.8 Ω to 1155 Ω it is specified that the transmitter has to provide an output impedance in a range of approximately 80 Ω to 1220 Ω. 
         [0004]    As a widely spread supply voltage for integrated circuits (ICs) is 3.3 Volts active impedance line drivers are also implemented using operational amplifiers operated at this nominal voltage, wherein the supply voltage often is allowed to vary by 10%. Accordingly a nominal supply voltage of 3.3 Volts can drop to 3.0 Volts. Regarding the requirements of the IEEE 802.3 standard for 10 BT protocol such a voltage drop is considerable in view of maintaining the required output voltage swing and output impedance of the line driver. In particular the design of the output stage of a 10 BT line driver becomes difficult, because the output stage of the line driver controls the output voltage and output impedance of the driver. Accordingly the design of an active output impedance line driver for transmitting symbols using the 10 BT protocol gravitates around trading output swing for control of the output impedance, with the intention to keep the transistors in the amplifier&#39;s output stage out of linear operation, because a linear operation of the transistors can cause gain drop or even instability of the amplifier and thus of the entire circuit. That is, in order to maintain the transistors operate in a non-linear region, their source-drain voltage must be large enough. Hence when designing an output stage of a 10 BT line driver operated at a supply voltage of 3.3 Volts with an admissible variation of ±10% care must be taken to provide for a large enough source-drain voltage of the output stage transistors. 
         [0005]    A conventional solution of a 10 BT line driver is shown in  FIG. 1 . The topology of circuit  100 , i.e. the arrangement of elements, is symmetrical to dotted line  101  or the common mode voltage supply V CM . Accordingly for an element in the upper half of the drawing, i.e. any element above dotted line  101  having an even reference numeral there is a corresponding element having an uneven reference number (increased by 1). The operation of the two identical circuit portions is also very similar, wherein the circuit portion shown above dotted line  101  processes the positive signal portion output at terminal V OP  and the circuit portion below dotted line  101  processes the negative signal portion of the output signal V OUT , and wherein the positive and negative portions of the output signal are symmetrical with reference to a common mode voltage. 
         [0006]    Circuit  100  takes a voltage V IN  as input signal representing the symbol to be transmitted and processed to be output as output voltage V OUT , which can be coupled to a transmission line represented as an ohmic resistor R CABLE . 
         [0007]    The circuit comprises single ended operational amplifiers  110 ,  111  each coupled with its positive input terminal via resistor R 3   120 ,  121  to a common mode voltage supply V CM . Input signal V IN  is fed into the negative input terminals of amplifiers  110 ,  111  via resistors R 1   130 ,  131 . A negative feedback loop around each amplifier comprises resistor R 2  and optional capacitor C FB    150 ,  151  and a positive feedback loop comprises resistors R 4   160 ,  161  and optional capacitors  170 ,  171  and termination resistors R T    180 ,  181 . 
         [0008]    In case that circuit  100  is operated at a supply voltage of 3.3 Volts, which can drop to 3.0 Volts, and the output swing reaches close to its maximum, i.e. close to the supply voltage, then the value of termination resistor R T , which is used to control the output impedance of the line driver, decreases considerably making the positive feedback loop almost as strong as the negative feedback loop, which can lead to an instable operation of the circuit. 
         [0009]    The risk of instable operation of the amplifiers is reduced by introducing the capacitors C FB    150 ,  151  into the feedback loops as shown, but which does not guarantee proper operation in all situations. Thus a supply voltage much higher than the required output swing of V OUT  usually is used, for example a supply voltage of 5 Volts. 
         [0010]    Thus there is a need for a 10 BT line driver operable at a voltage of 3.3 Volts, which also accurately operates in case the supply voltage drops to 3.0 Volts, and which accurately generates a 10 BT signal within the IEEE 802.3 specifications in these operating conditions. 
       SUMMARY OF THE INVENTION 
       [0011]    The invention relates to an integrated circuit including an active output impedance line driver circuit comprising a differential amplifier, the negative input terminal coupled via an input resistor to an input terminal, the positive output terminal providing an output signal, and wherein at least a feedback resistor forms a negative feedback path, and wherein the positive feedback path is shorted and coupled by an adjustable termination resistor to the residual in- and output terminal of the line driver and a common mode voltage source 
         [0012]    Furthermore a method is disclosed for operating an integrated circuit comprising an active output, impedance line driver for producing an output signal from an input signal, wherein the amplitude of the input signal is decreased in case the supply voltage of the active output impedance line driver drops. 
     
     
       DESCRIPTION OF THE FIGURES 
         [0013]      FIG. 1  depicts a schematic of a conventional 10 BT line driver 
           [0014]      FIG. 2  depicts a schematic overview of a 10 BT line driver circuit 
           [0015]      FIG. 3  depicts a schematic circuit for generating reference signal 
           [0016]      FIG. 4  depicts a schematic circuit of a 10 BT active output impedance line driver 
           [0017]      FIG. 5  depicts a circuit of a 10 BT active output impedance line driver comprising two identical, mirrored circuit portions 
           [0018]      FIG. 6  depicts an embodiment of a differential amplifier 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known processes and steps have not been described in detail in order not to unnecessarily obscure the present invention. 
         [0020]      FIG. 2  illustrates a block diagram of the invention. The blocks illustrated herein will be explained in detail hereinafter. The elements used in these blocks for example can be integrated in an integrated circuit (IC) and can be fabricated for example in 90 nm CMOS technology. 
         [0021]    In circuit  200  it is assumed that digital symbols  210  are generated by some upstream circuit not shown here. The digital symbols are provided to a digital-to-analog converter (DAC)  220 , which also is coupled to a clock signal, and which converts the digital symbols  210  into an analog output signal  230 . Analog signal  230  is fed into a 10 BT line driver  240 , which produces a 10 BT signal  250  as defined in the IEEE802.3 standard. The 10 BT signal then may be coupled to connection pads  260  of a chip comprising the 10 BT line driver. Connection pads  260  may be coupled to a transmission line to transmit signal  250  to a remote transceiver. 
         [0022]    The output signal  230  of DAC  220  may be either an analog current-mode signal, in which the information is coded in the current or a voltage-mode signal, wherein the information is coded in the voltage of the signal. In case signal  230  is voltage coded it may be coupled directly to the 10 BT line driver, because it requires a voltage as input signal as described below. 
         [0023]    However, in case signal  230  is a current-mode signal it is to be converted to voltage-mode signal by a conventional transimpedance current-to-voltage converter before being coupled to the 10 BT line driver, which in the here described embodiment requires a voltage as input signal. In its simplest implementation the current-to-voltage converter for example may comprise an operational amplifier having an ohmic resistor in its negative feedback path, wherein the value of the resistor defines the range of the output voltage. While the positive input of the amplifier is coupled to ground, the input current is provided to the inverting input of the amplifier. The output voltage is then produced at the amplifiers output, which may be coupled to the input of the 10 BT line driver  240 . 
         [0024]    The 10 BT line driver is further coupled to a calibration circuit  290 , which provides a digital calibration word for calibrating the value of a termination resistor comprised in the line driver as explained in detail hereinafter. 
         [0025]    Furthermore it is assumed that at least the DAC  220  and the 10 BT line driver are supplied by the same supply voltage  270 , which in the described embodiment is VDD=3.3 Volts nominal. As mentioned above this supply voltage may for any reason drop to 3.0 Volts, such that DAC  220  and 10 BT line driver are coupled to the same reduced supply voltage. A drop of the supply voltage VDD thus impacts DAC  220  and line driver  240  as well. 
         [0026]    As shown in the drawing DAC  120  furthermore is coupled to circuit  280 , which is coupled to the supply voltage VDD  270 . Circuit  280  generates a signal, which serves as a reference signal in DAC  120  controlling the maximum amplitude of the output signal, such that the output amplitude of the DAC drops by half the voltage drop of the supply voltage. That is, if the supply voltage drops by 0.3 Volts from 3.3 Volts to 3.0 Volts, which is around 9.1%, then the output amplitude of the DAC drops proportionally, i.e. in this case for example by 4.55%. 
         [0027]    An exemplary embodiment of a circuit  280  may have a topology as depicted in  FIG. 3 . A first voltage-to-current converter  310  is coupled to a bandgap reference voltage V BG  as input voltage and a polysilicon resistor R Poly    320  and outputs a current of V BG /R POLY , wherein the bandgap voltage is the most supply- and process-independent signal that can be generated inside integrated circuits (ICs). A second voltage to current converter  330  is coupled to the supply voltage V DD  as its input voltage and to a polysilicon resistor  340  and correspondingly outputs a current of V DD /R POLY . The output currents of the current-to-voltage converters are summed on a third polysilicon resistor  350 , wherein all resistors  320  and  340  and  350  match in their resistivity values. In this way a voltage of V REF =αV BG +βV DD , wherein α and β depend on the value of the resistors, is produced at resistor  350 , which servers as reference input voltage of the DAC. 
         [0028]      FIG. 4  depicts a circuit  400  of an exemplary implementation of an active output impedance line driver, which can be used as 10 BT line driver  240  in  FIG. 2 . Circuit  400  comprises a digital-to-analog converter  410  which receives digital symbols D IN  and the reference voltage V REF  and outputs a voltage signal V SIG , wherein V SIG  is proportional to the digital input signal D IN  and the reference voltage V REF . As described with reference to  FIG. 3  V REF  is generated as a combination of a supply-dependent current and a supply-independent current it can be made to vary in any ratio with the supply voltage. Accordingly the output voltage signal of DAC  410  decreases proportionally if the supply voltage drops and increases proportionally if the supply voltage exceeds its nominal value. 
         [0029]    V SIG  is fed into the circuit, which comprises an input resistor R VI    420  coupled to the input signal V SIG  and to the negative input terminal of differential amplifier  430 . Differential amplifier  430  comprises in its negative feedback loop a feedback resistor R FB    440  parallel to a feedback capacitor C FB    450 . The value of input resistor R VI  is chosen as a scaled down value of the feedback resistor, because the line driver is designed to have a gain larger than 1, thus acting as an amplifier. 
         [0030]    The positive feedback path is shorted and coupled via adjustable or calibrated termination resistor R T    460  to a direct current voltage source V CM , which defines the common mode voltage of the output signal V OUT . 
         [0031]    The IEEE standard requires a differential output amplitude of the line driver circuit between 2.2 Volts and 2.8 Volts with nominal 2.5 Volts on a cable impedance R CABLE    470  of 100 Ω. As  FIG. 4  depicts half of the circuit the value of the cable is half of the specification, i.e. 50 Ω. In this embodiment the nominal supply voltage of the circuit shall be 3.3 Volts, so the DAC can easily generate a 0.5 Volt full scale output. To reach the required voltage swing the line driver must have a gain of 2.5 times. Since the line driver output gets divided over the cable impedance and the output impedance of driver circuit  400  equally, the 2.5 times gain is implemented by making 1+R FB /R VI =5, which results in R FB =4·R VI . The value of the input resistor is chosen to be much higher, i.e. for example 10 times higher, than the resistance of the cable in order to achieve a high input impedance of the line driver, such that the line driver has the characteristic of a high input impedance and a matching output impedance, as illustrated below. Convenient values for the resistors may be for example R VI =1 kΩ and R FB =4 kΩ. R T  is calculated from the output impedance equation, 
         [0000]    
       
         
           
             ROUT 
             ≈ 
             
               RT 
                
               
                 
                   RVI 
                   + 
                   RFB 
                 
                 RVI 
               
             
           
         
       
     
         [0000]    as 50 Ω/5=10 Ω. If it is assumed that amplifier  430  has its negative output current scaled 10 times smaller that its positive output current, such that the value of R T  scales 10 times higher to 100 Ω. 
         [0032]    The amplitude of the output signal Vout is given as 
         [0000]    
       
         
           
             VOUT 
             ≈ 
             
               
                 VSIG 
                  
                 
                   ( 
                   
                     1 
                     + 
                     
                       RFB 
                       RVI 
                     
                   
                   ) 
                 
               
                
               
                 RCABLE 
                 
                   RCABLE 
                   + 
                   RT 
                 
               
             
           
         
       
     
         [0033]    As 3.3 Volts is a widespread supply voltage for integrated circuits circuit  400  is designed to be supplied with this voltage. Accordingly amplifiers  420 ,  421  are supplied with 3.3 Volts, which can drop to 3.0 Volts as mentioned above. Consequently the circuit should be able to properly operate at a voltage of 3.0 Volts. That is, the specifications relating to the amplitude of the output signal amplitude and to the output impedance of the line driver should be met also when operating the circuit with 3.0 Volts. 
         [0034]    According to the above given equation the amplitude of the output signal V OUT  depends on the impedance R CABLE  of the transmission line, i.e. the cable, and the termination resistor R T . As R T  is produced as an on-chip resistor it may have a production spread of ±15% from its nominal value. So for achieving a tighter control over V OUT  the termination resistor R T  is made adjustable, such that it may not vary by more than 2% from its nominal value. 
         [0035]    The calibration of termination resistor R T  can be done in a number of conventional ways. For example switches can be inserted between different gaps of the resistor and the common mode voltage source V CM , wherein the switches increase or reduce the resistivity value of R T . The switches itself show very low resistance in their on state and very little signal dependency since they are coupled to a DC biased node, namely V CM , such that the switches itself have a negligible overall impact on the circuit. The setting of these switches can be done at the time when the circuit is powered on. A separate circuit, which is not shown in the drawings, determines the setting of the switches by comparing one of a plurality of termination resistors R T  included in one chip to a reference resistor. The determined setting can be for example a binary word, which can be spread on the chip to a plurality of termination resistors comprised in one chip. The determination of the settings may be performed for one termination resistor and spread over the chip to all termination resistors, because it is known from experience that all termination resistors comprised in one chip and thus originating from one wafer show very similar values. In this way, i.e. by determining the switch settings for one termination resistor and spreading these values to all termination resistors of the chip the resistivity value of each termination resistor can be adjusted to a deviation of less than 2%. 
         [0036]    More care must be taken to maintain proper voltage conditions for the operation of amplifier  420  respectively. So in case the supply voltage drops to 3.0 Volts the swing of output signal V OUT  still should be in the range defined by the IEEE 802.3 standard, while at the same time there should be enough voltage difference between the supply voltage of the amplifiers, which will be 3.0 Volts, and the maximum amplitude of output signal V OUT  to enable a sufficient source drain voltage for operating an output stage transistor in amplifier  420 . 
         [0037]    As shown above in the equation V OUT  directly depends on the amplitude of the input voltage V SIG . Accordingly the input voltage V SIG , which is output from DAC  120  as shown in  FIG. 2 , is controlled so that it also drops in case the supply voltage drops to effectuate a reduced output signal V OUT . 
         [0038]    For example assuming the DAC reference signal to be 50% supply-independent and 50% supply-dependent, a closed-loop line driver gain of 2.5 and normal conditions, i.e. when the supply voltage has its nominal value of 3.3 Volts, the input signal Vsig may have an amplitude of 1 Volt and the output signal V OUT  may have an amplitude of 2.5 Volts such that there is a difference of 0.8 Volts between the output signal amplitude and the supply voltage of the amplifier  420 . 
         [0039]    In case the supply voltage increases for example to 3.6 Volts, then the input signal V SIG  increases to an amplitude of 1.05 Volts and the output signal V OUT  may have a value of 2.625 Volts, which is still in the specified IEEE standard limits. The difference between the supply voltage and the output signal V OUT  is thus 0.975 Volts. 
         [0040]    In case the supply voltage decreases to a value of 3.0 Volts, a reduced input voltage V SIG  of 0.95 Volts is fed into circuit  400 , which effectuates a drop of the amplitude of the output signal, i.e. the voltage of the 10 BT Ethernet signal, to 2.375 Volts, which is still in the allowed range. The difference between the supply and the output voltage in this case is 0.625 Volts. 
         [0041]    Conventional differential amplifiers in many embodiments comprise two transistors in their output stage, which are coupled with their source—drain path between the supply and the output voltage. For enabling a proper operation of these transistors the source—drain voltage of these transistors must be large enough, i.e. at least 0.2 Volts for each transistor. As these voltages add for the two exemplary transistors in the output stage of the exemplary differential amplifier, there should be at least a voltage of 0.4 Volts between the supply and the maximum output voltage of the differential amplifier. 
         [0042]    As shown above this minimum voltage between supply and maximum output voltage of a conventional differential amplifier is exceeded in each of the operating conditions, i.e. in particular the supply voltage drops from 3.3 Volts to 3.0 Volts. Accordingly circuit  400  allows the proper operation of the comprised differential amplifiers while preserving operating conditions for the transistors making the output stage. 
         [0043]    In this way  FIG. 4  discloses a circuit of an active output impedance line driver comprising a differential amplifier, the negative input terminal coupled via an input resistor to an input terminal, the positive output terminal providing an output signal, and wherein at least a feedback resistor forms a negative feedback path, and wherein the positive feedback path is shorted and coupled by an adjustable termination resistor to the residual in- and output terminal of the line driver and a common mode voltage source. 
         [0044]      FIG. 5  depicts a circuit  500  of an exemplary implementation of an active output impedance line driver, wherein the circuit comprises two circuit portions of identical topology, such that the drawing shows one circuit portion above and the other circuit portion below mirror line  501 . As the input signal V SIG  and also the output signal V OUT  are differential signals one circuit portion processes the positive and one signal portion processes the negative signal portion of the output signal V OUT , such that for example the positive output signal portion of V OUT  is output at pad V OP  and the negative output signal portion is output at pad V ON . 
         [0045]    In the following description of  FIG. 5  even reference numerals refer to the circuit portion processing above mirror line  501  whereas uneven reference numbers denote elements below the mirror line. 
         [0046]    The topology of each circuit portion is similar to the circuit as depicted in  FIG. 4 . Accordingly each circuit portion comprises an input resistor R VI    510 ,  511  coupled to the input signal V SIG  and to the negative input terminal of a differential amplifier  520 ,  521 . Amplifiers  520 ,  521  comprise in their respective negative feedback loops a feedback resistor R FB    530 ,  531  parallel to a feedback capacitor C FB    540 ,  541 . The positive output terminals of amplifiers  520 ,  521  each form an output terminal of the driver, so that the output signal is provided between the positive output terminals of the differential amplifiers  520  and  521 . The positive feedback paths of each amplifier is shorted to the negative input and coupled via an adjustable termination resistor R T    550  and  551  to a direct current common mode voltage source V CM    560 . 
         [0047]    As described above the calibration of termination resistors R T  can be done in a number of conventional ways, in which the value of each resistor is adjusted by providing an electrical signal to these, such that the resistors can be adjusted when the circuit or the integrated circuit comprising the line driver is powered up. 
         [0048]    Example values for the passive elements in the circuit can be chosen as in  FIG. 4  and the resulting output impedance of this pseudo-differential circuit is twice the output impedance of the single ended circuit as depicted in  FIG. 4 . 
         [0049]      FIG. 6  depicts an exemplifying embodiment of a differential amplifier  600 , which can be amplifier  430  of  FIG. 4 . The negative and positive input terminals of the amplifier  600  are labeled V IN  and V IP  and the negative and positive output terminals are labeled V ON  and V OP  respectively. 
         [0050]    Amplifier  600  comprises a first input stage IS 1   610  and a second input stage IS 2   620 , which are directly coupled to a first and a second output stage OSN and OSP  630 ,  640  and to the dual class-AB biasing mesh  650 . A common mode loop uses four replica transistors  660  to get the sum of all currents in the two output stages, which drives a current-input, voltage-output common-mode feedback loop (CMFB) generating a biasing voltage for one of the input stages. This makes the sum of biasing currents in the PMOS side of the two output stages equal the sum of the biasing currents in the NMOS side, so that no offset current is drawn from the load. 
         [0051]    The topology of the differential amplifier is thus designed for power efficiency since no intermediate stages between the input and output stages are used. Also the output stages, which draw a large current at 2.5 Volts peak output on 100 Ω loads, are biased in class-AB so that the power consumption is reduced when the output voltage is near a zero-crossing. Furthermore the negative output stage OSN can be designed as a scaled version of the positive output stage OSP to reduce power consumption, which effectuates the design of the termination resistor R T .