Abstract:
Disclosed is a liquid crystal display using a swing common electrode voltage and a drive method thereof. The liquid crystal display comprises a timing controller for outputting data driver drive signals and gate driver drive signals, and outputting a first signal according to externally-received signals; a data driver which outputs data drive voltages for driving a polarity of liquid crystal capacitors; a gate driver which outputs gate drive voltages; a drive voltage generator for receiving the first signal and either increasing or decreasing a voltage level of the first signal, and outputting at least two different common electrode voltages that undergo swinging by synchronizing to a predetermined period with respect to the gate drive voltages; and an LCD panel including switching elements, the liquid crystal capacitors and storage capacitors. The drive method comprises the steps of receiving image signals from an external image signal source, and supplying the image signals to the data lines; supplying scanning signals sequentially to the gate lines; checking pixel voltage variations; outputting a common electrode voltage ending at positive during a gate “on” time to the LCD panel, and outputting a common electrode voltage that repeatedly swings from negative to positive during a gate “off” time if the pixel voltage has varied from negative to positive; and outputting a common electrode voltage ending at positive during a gate “on” time to the LCD panel, and outputting a common electrode voltage that repeatedly swings from positive to negative during a gate “off” time to the LCD panel if the pixel voltage is varied from positive to negative.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    (a) Field of the Invention  
           [0002]    The present invention relates to a liquid crystal display and a drive method thereof. More particularly, the present invention relates to a liquid crystal display and a drive method thereof in which swinging of a common electrode voltage is performed by synchronizing the voltage with a gate pulse, thereby generating an overshoot to improve a response speed of liquid crystal material.  
           [0003]    (b) Description of the Related Art  
           [0004]    In recent times, there has been an ever-increasing need for lighter and thinner displays. Accordingly, the liquid crystal display (LCD) is replacing the CRT in many applications such as in television and as displays for personal computers.  
           [0005]    LCDs include first and second substrates provided substantially in parallel with a predetermined gap therebetween, and liquid crystal material is sandwiched between the two opposing substrates. A voltage is applied to the liquid crystal material, which has a dielectric anisotropy, to form an electric field between the substrates. By varying the strength of the electric field, the alignment of liquid crystal molecules of the liquid crystal material is controlled to thereby control the transmittance of incident light. Although there are different types of LCDs, the most common type is the thin film transistor (TFT) LCD.  
           [0006]    [0006]FIG. 1 shows a pixel equivalent circuit of a conventional TFT-LCD. With reference to the drawing, a pixel of the TFT-LCD includes a TFT switching element in which a source terminal and a gate terminal are respectively connected to a data line and a gate line; a liquid crystal capacitor Clc and a storage capacitor Cst, each connected to a drain terminal of the TFT switching element; a parasitic capacitor Cgd provided between the gate terminal and the drain terminal; a parasitic capacitor Cds connected between the drain terminal and the source terminal; and an overlap capacitor (Cover) provided between the data line and a pixel electrode Vp.  
           [0007]    The method of driving the liquid crystal material between the pixel electrode Vp, which is provided on a TFT substrate, and a common electrode Vcom, which is provided on a color filter substrate, will now be described.  
           [0008]    First, if a positive pulse is applied through the gate line, the TFT switching element turns on. At this time, a signal voltage applied to a source electrode of the TFT switching element through a signal line is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the drain terminal. The signal voltage, which is applied together with a gate pulse, is continuously maintained even when a gate voltage is turned off and applied to the liquid crystal capacitor Clc. However, because of the parasitic capacitor Cgd between the gate terminal and the drain terminal, a pixel voltage undergoes a voltage level shift by a certain amount of voltage.  
           [0009]    The biggest limitation in the TFT-LCD that is structured and operating as described above is its response speed. Matsushida Company improves a capacitive coupled driving (CCD) mechanism in order to increase the response speed of the TFT-LCD.  
           [0010]    [0010]FIG. 2 shows a chart for describing the effects of CCD. A direction applied to a pixel for controlling overshooting and undershooting is determined by the liquid crystal property of low anisotropy. If a pulse is applied to a common electrode COM, an amount that undergoes capacitive coupling increases in the pulse direction of a low anisotropic state of the liquid crystal material. If a pulse in which the voltage is first increased then decreased is applied in the case where the direction applied to the common electrode COM inverts from positive (+) to negative (−), or if a pulse in which the voltage is increased then decreased is applied in the case where the direction applied to the common electrode inverts from negative (−) to positive (+), conversion from a high gray level to a low gray level occurs for a normal white mode. However, if conversion from the low gray level to the high gray level occurs, undershooting and overshooting of the voltage result such that the liquid crystal material rotates more quickly.  
           [0011]    [0011]FIG. 3 shows a pixel equivalent circuit of a TFT-LCD using a previous gate disclosed by Matsushita Company, and FIG. 4 shows charts used to describe the increase in response speed for the TFT-LCD of FIG. 3.  
           [0012]    With reference to the drawings, one end of a storage capacitor Cst is connected to a drain, and its other end is connected to a previous gate. During operation, a gate pulse is applied such that an average voltage Vp applied to the pixel results as shown in Equation 1.  
           [0013]    [Equation 1] 
             Vp=±Vs+[Cst/ ( Cst+Cgd+Clc ) ]ΔVg   
           [0014]    where Vs is a voltage applied to a source terminal, Cst is a capacitance of the storage capacitor Cst, Cgd is a parasitic capacitance between a gate terminal and a drain terminal, Clc is a capacitance of a liquid crystal capacitor, and ΔVg is a difference between a previous gate voltage and a present gate voltage.  
           [0015]    However, the use of the previous gate in the TFT-LCD disclosed by Matsushida Company increases the gate load and can only be applied to line inversion driving. It also generates crosstalk and flicker to thereby make large-scale high resolution difficult. Also, a conventional gate tap IC is not able to be used in the Matsushida TFT-LCD. Further, if the gate voltage excessively increases when turned off in this prior TFT-LCD, an off current increases such that there is a limit to the degree at which a value of the gate can be changed.  
           [0016]    As described above, in the TFT-LCD disclosed by Matsushita Company, although the use of a previous gate signal and the drive method of applying a gate signal in two steps significantly improves response speed, there are limits to the application to a large-scale high resolution LCD when considering the use of a previous gate, and line inversion.  
         SUMMARY OF THE INVENTION  
         [0017]    The present invention has been made in an effort to solve the above problems.  
           [0018]    It is an object of the present invention to provide a liquid crystal display and a drive method thereof that uses a dot inversion structure without modification, and a common electrode voltage is synchronized with a gate pulse to swing the common electrode voltage to generate an overshoot, thereby increasing a response speed of liquid crystal material.  
           [0019]    To achieve the above object, the present invention provides a liquid crystal display using a swing common electrode voltage and a drive method thereof. The liquid crystal display comprises a timing controller for outputting data driver drive signals and gate driver drive signals, and outputting a first signal, which determines a period and an amplitude, according to externally-received signals including a vertical synchronization signal, a horizontal synchronization signal, and a main clock signal; a data driver which, according to the data driver drive signals, outputs data drive voltages for driving a polarity of liquid crystal capacitors; a gate driver which, according to the gate driver drive signals, outputs gate drive voltages; a drive voltage generator for receiving the first signal and either increasing or decreasing a voltage level of the first signal, and outputting at least two different common electrode voltages that undergo swinging by synchronizing to a predetermined period with respect to the gate drive voltages; and an LCD panel including (a) switching elements formed in regions defined by the crossing of gate lines and data lines and connected to the gate lines and the data lines, (b) the liquid crystal capacitors for transmitting a light according to an “on” operation of the switching element and in accordance to a pixel voltage that is in proportion to the swing common electrode voltages and the data drive voltages, and (c) storage capacitors for accumulating the data drive voltages when the switching element is on and applying the stored voltages to the liquid crystal capacitor when the switching element is off, the LCD panel being driven according to the data drive voltages and the gate drive voltages.  
           [0020]    According to a feature of the present invention, each of the common electrode voltages output from the drive voltage generator ends at negative at a gate “on” time when the pixel voltage changes from negative to positive, ends at positive at a gate “on” time when the pixel voltage changes from positive to negative, and undergoes swinging of positive and negative after the gate is closed.  
           [0021]    According to another feature of the present invention, the LCD panel further comprises a plurality of gate lines arranged horizontally, and a plurality of common electrode lines arranged between the gate lines, wherein a first terminal of the switching elements is connected to the gate lines and a second terminal of the switching elements is connected to the data lines; one end of the storage capacitors connected to a third terminal of the switching elements; and in the case where the liquid crystal capacitors are positioned at odd lines and odd columns, and at even lines and even columns within regions formed by the gate lines and the data lines, one end is connected to the third terminal of the switching elements and other ends are connected to the common electrode lines positioned at upper ends of the gate lines, and when the liquid crystal capacitors are positioned at odd lines and even columns, and at even lines and odd columns, one end is connected to the third terminal of the switching elements and other ends are connected to the common electrode lines adjacent to the gate lines positioned at the lower ends of the gate lines.  
           [0022]    According to yet another feature of the present invention, the LCD panel comprises odd common electrode lines arranged horizontally; odd gate lines arranged adjacent to the odd common electrode lines; even common electrode lines arranged horizontally; even gate lines arranged adjacent to the even common electrode lines; odd data lines arranged vertically and even data lines arranged horizontally; a first storage capacitor for connecting the odd common electrode lines (or the even common electrode lines) to the odd gate lines (or the even gate lines) in regions divided by the odd data lines and the even data lines; and a second storage capacitor for connecting the even common electrode lines (or the odd common electrode lines) to the odd gate lines (or the even gate lines) in regions divided by the even data lines and the odd data lines.  
           [0023]    According to still yet another feature of the present invention, the LCD panel comprises common electrode lines arranged horizontally between gate lines; a first pixel formed in a region formed by odd gate lines and even gate lines, and by odd data lines and even data lines, one end of the first pixel being connected to the odd gate lines and its other end being connected to the common electrode lines; a second pixel formed in a region formed by the odd gate lines and the even gate lines, and by the odd data lines and the even data lines, one end of the second pixel being connected to the even gate lines; a third pixel formed in a region formed by the odd gate lines and the even gate lines, and by the even data lines and the odd data lines, one end of the third pixel being connected to the odd gate lines; and a fourth pixel formed in a region formed by the odd gate lines and the even gate lines, and by the even data lines and the odd data lines, one end of the fourth pixel being connected to the common electrode lines and its other end being connected to the even gate lines.  
           [0024]    According to still yet another feature of the present invention, the minimum two types of common electrode voltages supplied by the drive voltage generator are applied at leftward, rightward, or both ends of the common electrode lines.  
           [0025]    According to still yet another feature of the present invention, a dot inversion drive method is used to drive the LCD panel.  
           [0026]    According to still yet another feature of the present invention, the common electrode lines are arranged in an independent wiring configuration.  
           [0027]    In another aspect, the present invention provides a liquid crystal display comprising an LCD panel, the LCD panel including (a) switching elements formed in regions defined by the crossing of gate lines and data lines and connected to the gate lines and the data lines, (b) liquid crystal capacitors for transmitting a light according to an “on” operation of the switching element and in accordance to a pixel voltage that is in proportion to swing common electrode voltages and data drive voltages, and (c) storage capacitors for accumulating the data drive voltages when the switching element is on and applying the stored voltages to the liquid crystal capacitors when the switching element is off, wherein a record signal voltage corresponding to display data is applied sequentially to each pixel to display an image of each frame, and wherein during driving of the pixels, each of the common electrode voltages output from the drive voltage generator ends at negative at a gate “on” time when the pixel voltage changes from negative to positive, ends at positive at a gate “on” time when the pixel voltage changes from positive to negative, and undergoes swinging of positive and negative after the gate is closed.  
           [0028]    According to still yet another feature of the present invention, a swing width of the common electrode voltages is between 12 and 25 volts.  
           [0029]    In another aspect, the present invention provides a drive method for a liquid crystal display, the liquid crystal display comprising an LCD panel, which includes (a) switching elements formed in regions defined by the crossing of gate lines and data lines and connected to the gate lines and the data lines, (b) liquid crystal capacitors for transmitting a light according to an “on” operation of the switching element and in accordance to a pixel voltage that is in proportion to swing common electrode voltages and data drive voltages, and (c) storage capacitors for accumulating the data drive voltages when the switching element is on and applying the stored voltages to the liquid crystal capacitors when the switching element is off, the drive method comprising the steps of (a) receiving image signals from an external image signal source, and supplying the image signals to the data lines; (b) supplying scanning signals sequentially to the gate lines to control gate on/off operations of the switching element; (c) checking pixel voltage variations occurring according to the gate on/off operations of the switching elements; (d) outputting a common electrode voltage ending at positive during a gate “on” time to the LCD panel, and outputting a common electrode voltage that repeatedly swings from negative to positive during a gate “off” time if, in step (c), it is determined that the pixel voltage has varied from negative to positive; and (e) outputting a common electrode voltage ending at positive during a gate “on” time to the LCD panel, and outputting a common electrode voltage that repeatedly swings from positive to negative during a gate “off” time to the LCD panel if, in step (c), it is determined that the pixel voltage has varied from positive to negative.  
           [0030]    According to a feature of the drive method of the present invention, a swing width of the common electrode voltage is between 12 and 25 volts.  
           [0031]    According to another feature of the drive method of the present invention, the LCD panel is driven by a dot inversion method.  
           [0032]    According to yet another feature of the drive method of the present invention, the LCD panel comprises a plurality of gate lines arranged horizontally; a plurality of data lines arranged vertically; a plurality of common electrode lines arranged between the gate lines, that is, arranged at an upper end of a first gate line and a lower end of a last gate line; a plurality of switching elements, a first terminal connected to the gate lines and a second terminal connected to the data lines; storage capacitors, one end of each connected to a third terminal of the switching elements; and liquid crystal capacitors in which, when positioned at odd lines and odd columns, and at even lines and even columns within regions formed by the gate lines and the data lines, one end is connected to the third terminal of the switching elements and other ends are connected to the common electrode lines positioned at upper ends of the gate lines, and in which, when positioned at odd lines and even columns, and at even lines and odd columns, one end is connected to the third terminal of the switching elements and other ends are connected to the common electrode lines adjacent to the gate lines positioned at the lower ends of the gate lines.  
           [0033]    According to still yet another feature of the drive method of the present invention, the LCD panel comprises odd common electrode lines arranged horizontally; odd gate lines arranged adjacent to the odd common electrode lines; even common electrode lines arranged horizontally; even gate lines arranged adjacent to the even common electrode lines; odd data lines arranged vertically and even data lines arranged horizontally; a first storage capacitor for connecting the odd common electrode lines (or the even common electrode lines) to the odd gate lines (or the even gate lines) in regions divided by the odd data lines and the even data lines; and a second storage capacitor for connecting the even common electrode lines (or the odd common electrode lines) to the odd gate lines (or the even gate lines) in regions divided by the even data lines and the odd data lines.  
           [0034]    According to still yet another feature of the drive method of the present invention, the LCD panel comprises common electrode lines arranged horizontally between gate lines; a first pixel formed in a region formed by odd gate lines and even gate lines, and by odd data lines and even data lines, one end of the first pixel being connected to the odd gate lines and its other end being connected to the common electrode lines; a second pixel formed in a region formed by the odd gate lines and the even gate lines, and by the odd data lines and the even data lines, one end of the second pixel being connected to the even gate lines; a third pixel formed in a region formed by the odd gate lines and the even gate lines, and by the even data lines and the odd data lines, one end of the third pixel being connected to the odd gate lines; and a fourth pixel formed in a region formed by the odd gate lines and the even gate lines, and by the even data lines and the odd data lines, one end of the fourth pixel being connected to the common electrode lines and its other end being connected to the even gate lines. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0035]    The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of the invention:  
         [0036]    [0036]FIG. 1 is a pixel equivalent circuit of a conventional TFT-LCD;  
         [0037]    [0037]FIG. 2 is a chart for describing the effects of CCD;  
         [0038]    [0038]FIG. 3 is a pixel equivalent circuit of a TFT-LCD using a previous gate disclosed by Matsushita Company;  
         [0039]    [0039]FIG. 4 shows charts used to describe the increase in response speed for the TFT-LCD of FIG. 3;  
         [0040]    [0040]FIG. 5 shows waveform diagrams for illustrating variations in a pixel voltage occurring as a result of a periodic swing common electrode voltage according to a first preferred embodiment of the present invention;  
         [0041]    [0041]FIG. 6 is a graph showing changes in transmissivity and voltage according to an increase in a common electrode voltage swing width according to a first preferred embodiment of the present invention;  
         [0042]    [0042]FIG. 7 is a graph showing a relation between a resistor array and a VT curve in a drive PCB according to a first preferred embodiment of the present invention;  
         [0043]    [0043]FIG. 8 shows waveform diagrams for illustrating variations in a pixel voltage occurring as a result of a periodic swing common electrode voltage according to a second preferred embodiment of the present invention;  
         [0044]    [0044]FIG. 9 is a graph showing changes in transmissivity and voltage according to an increase in a common electrode voltage swing width according to a second preferred embodiment of the present invention;  
         [0045]    [0045]FIG. 10 is a schematic view of an LCD using a reverse mode swing common electrode voltage according to a second preferred embodiment of the present invention;  
         [0046]    [0046]FIG. 11 is a schematic view of an equivalent circuit of the LCD of FIG. 10;  
         [0047]    [0047]FIG. 12 is a schematic view used to describe a single common line wiring structure in dot inversion according to a second preferred embodiment of the present invention; and  
         [0048]    [0048]FIG. 13 is a schematic view used to describe a divided pixel structure in dot inversion according to a second preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0049]    Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.  
         [0050]    [0050]FIG. 5 shows waveform diagrams for illustrating variations in a pixel voltage occurring as a result of a periodic swing common electrode voltage according to a first preferred embodiment of the present invention.  
         [0051]    With reference to the drawing, by swinging a common electrode voltage, swinging of voltages applied to a pixel is performed. An average voltage Vp applied to a pixel is as shown in Equation 2.  
         [0052]    [Equation 2] 
           Vp=±Vs+{Cst/[ 2( Cst+Cgd+Clc )]}ΔVcom 
         [0053]    where Vs is a voltage applied to a source terminal, Cst is a capacitance of a storage capacitor, Cgd is a parasitic capacitance between a gate terminal and a drain terminal, Clc is a capacitance of a liquid crystal capacitor, and ΔVcom is a swing width of a voltage applied to a common electrode line.  
         [0054]    In Equation 2, since a voltage additionally applied to a common electrode is proportional to Cst/(Cst+Clc), when a gray level varies by memory effects resulting from the liquid crystal capacitor Clc, overshooting occurs such that a response speed of liquid crystal material increases. In order to increase the response speed of the liquid crystal material, that is, in order to apply the above method of generating overshoot to improve response speed, the following three conditions must be satisfied.  
         [0055]    (i) When the pixel voltage changes from negative (−) to positive (+), the common electrode voltage ends at negative (−) at a gate “on” time.  
         [0056]    (ii) When the pixel voltage changes from positive (+) to negative (−), the common electrode voltage ends at positive (+) at a gate “on” time.  
         [0057]    (iii) After the gate is closed, swinging of positive (+) and negative (−) is repeatedly performed.  
         [0058]    The degree of overshoot generated as a result of the liquid crystal capacitor Clc is determined as follows.  
         [0059]    If each capacitance of the liquid crystal capacitor Clc is designated as Clc 1  and Clc 2 , when changing to a second gray state from a first gray state, a difference in values of the second term on the right side of Equation 2 results in a value corresponding to overshoot as shown in Equation 3.  
                     V   overshoot     =       [         Cst   /   2          (     Cst   +     Clc                 1       )       -       Cst   /   2          (     Cst   +     Clc                 2       )         ]        Δ                 Vcom                 =       [     Δ                 Vcom                   Cst        (       Clc                 2     -     Clc                 1       )         ]     /     [     2        (     Cst   +     Clc                 1       )          (     Cst   +     Clc                 2       )       ]                     [     Equation                 3     ]                               
 
         [0060]    The amount of overshoot is a deciding factor in determining increases in response speed. Although variations in capacitance can be realized through design, the degree of such variations is limited by panel characteristics. Accordingly, to increase the amount of overshoot, the swing width ΔVcom of the common electrode voltage must be increased. However, when Vs in Equation 2 is 0, since the second term on the right side of the equation must be less than a critical voltage Vth of liquid crystals, the swing width ΔVcom of the common electrode voltage is limited. In particular, in a dot inversion drive method, when 0V is applied to the pixel, a voltage induced because of a swing of an independent common electrode voltage must be less than the critical voltage Vth of liquid crystals as follows. 
           Cst/[ 2( Cst+Cgd+Clc )]ΔVcom&lt;Vth 
         [0061]    From this inequality, it follows that the condition of ΔVcom&lt;[2Vth(Cst+Cgd +Clc)]/Cst must be satisfied. Hence, the amount of overshoot in Equation 3 is limited. For example, if Clc 2 =Cst and Clc 1 =0.5Cst, it is possible to ignore Cgd, and if Vth=1.6V, a maximum overshoot value of 0.4V results in Equation 3.  
         [0062]    Since this is a value that moves between 1 gray level and 64 gray levels, when moving between gray levels starting from a low gray level, the amount of overshoot is reduced. Also, with this value, it is not possible to reduce the response speed to under 16 msec over the entire range of gray levels. As a result, in order to realize a high-speed response using a swing multi common capacity, the overshoot of Equation 3 must be increased more.  
         [0063]    Reasons for the limitations in the swing width ΔVcom of the common electrode voltage in Equation 3 will be described with reference to FIG. 6. FIG. 6 is a graph showing changes in transmissivity and voltage according to increases in the common electrode voltage swing width.  
         [0064]    As shown in the drawing, a normal VT curve results when swinging of a voltage of a storage common electrode is not performed, while the VT curve is moved to the left according to increases in the swing width ΔVcom of the common electrode voltage. This is a result of an additional voltage at Vs through a common swing (in addition to the voltage applied in Equation 2).  
         [0065]    Accordingly, even with the application of an identical voltage, if the swing width ΔVcom of the common electrode voltage is large, the effective voltage applied to the pixel is increased such that the VT curve is shifted to the left in FIG. 6, in accordance with increases in the swing width ΔVcom of the common electrode voltage. In FIG. 6, ΔV is less than roughly 5V in a vertical alignment mode. If ΔV exceeds this level, a black value is unable to be obtained.  
         [0066]    [0066]FIG. 7 is a graph showing a relation between a resistor array and a VT curve in a drive PCB according to a first preferred embodiment of the present invention.  
         [0067]    In the uppermost row of the graph (row  1 ), there is shown a resistor array for gray level expression in a control PCB. Negative (−) side VT curves and positive (+) side VT curves are shown in rows  2  through  4 . Rows  2 ,  3  and  4  appear in this order under row  1 . In normal drive of row  2  of FIG. 7, a left curve is a negative (−) side VT curve and a right curve is a positive (+) side VT curve. The drawn curves are drive voltages.  
         [0068]    Row  3  of FIG. 7 shows a VT curve in the case where the swing width ΔV of the common electrode voltage Vcom is approximately 5V. As described above with reference to FIG. 6, this is the voltage used in conventional methods to obtain the largest overshoot. Here, black portions meet at a central area. However, in row  4  of FIG. 7, the VT curves cross. If the voltage is applied with this structure, the swing width ΔV of the common electrode voltage Vcom can be increased.  
         [0069]    In the above method of the first preferred embodiment of driving the high voltage swing common electrode voltage, since there is a limit to the degree to which swinging of the common electrode voltage Vcom can be performed, the level of overshoot is small such that only minimal improvements in response speed are obtained. A method of improving increases to response speed (up to 4×), even with a swing width that is smaller than that realized in the first embodiment, will now be described.  
         [0070]    [0070]FIG. 8 shows waveform diagrams for illustrating variations in a pixel voltage occurring as a result of a periodic swing common electrode voltage according to a second preferred embodiment of the present invention.  
         [0071]    With reference to FIG. 8, voltages applied to one pixel swing a common electrode voltage such that the voltages applied to the pixel undergo swinging. At this time, an average voltage Vp applied to a pixel is as shown in Equation 2.  
         [0072]    In Equation 2, since the voltage additionally applied to the common electrode is proportional to Cst/(Cst+Clc), when a gray level varies by memory effects resulting from the liquid crystal capacitor Clc, overshooting occurs such that the response speed of liquid crystal material increases. In order to increase the response speed of the liquid crystal material, that is, in order to apply the above method of generating overshoot to improve response speed, the following three conditions must be satisfied. In this case, a faster response speed than the first embodiment is realized.  
         [0073]    (i) When the pixel voltage changes from negative (−) to positive (+), the common electrode voltage ends at negative (+) at a gate “on” time.  
         [0074]    (ii) When the pixel voltage changes from positive (+) to negative (−), the common electrode voltage ends at positive (−) at a gate “on” time.  
         [0075]    (iii) After the gate is closed, swinging of positive (+) and negative (−) is repeatedly performed.  
         [0076]    With reference to FIGS. 5 and 8, in the first and second preferred embodiments, the common electrode voltages undergo swinging and are inverted.  
         [0077]    [0077]FIG. 9 is a graph showing changes in transmissivity and voltage according to an increase in a common electrode voltage swing width according to the second preferred embodiment of the present invention. In FIG. 9, a VT curve undergoes a shift as a result of the shift in the common electrode voltage.  
         [0078]    With reference to the drawing, if a positive (+) voltage is applied when a data voltage is applied, a negative (−) voltage is applied to the pixel. However, if a negative (−) voltage is applied when the data voltage is applied, a positive (+) voltage is applied to the pixel. Further, switching from a normally black mode to a normally white mode occurs.  
         [0079]    To obtain such effects, the swing width ΔVcom of the common electrode voltage, which is applied to a common electrode of an independent wiring structure and to a common electrode line, must be between 12V and 25V, and preferably 18V. An internal structure of an LCD panel and a pixel structure to realize an increase in the swing width of the common electrode voltage to 18V or higher will now be described. In particular, an example of dividing the common electrode line into three types to drive the same will be described.  
         [0080]    [0080]FIG. 10 shows a schematic view of an LCD using a reverse mode swing common electrode voltage according to a second preferred embodiment of the present invention.  
         [0081]    As shown in the drawing, the LCD includes a timing controller  100 , a data driver  200 , a gate driver  300 , a drive voltage generator  400 , and an LCD panel  500 . The timing controller  100  outputs data drive driving signals (LOAD, Hstart, R, G, B) and gate driver drive signals (Gate Clk, Vstart) to the data driver  200  and the gate driver  300 , respectively. Also, the timing controller  100  outputs a first signal, which determines a period and an amplitude of a common electrode voltage Vcom, to the drive voltage generator  400  according to signals received externally, which include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock signal MCLK.  
         [0082]    The data driver  200 , based on the data driver drive signals (LOAD, Hstart, R, G, B), outputs data drive voltages (D 1 , D 2 , . . . Dm), which drive a polarity of a liquid crystal capacitor Clc, to a plurality of data lines. Here, the data lines are arranged in a vertical direction (in the drawing) of the LCD panel  500 . The gate driver  300 , based on the gate driver drive signals (Gate Clk, Vstart) supplied from the timing controller  100  and Von and Voff supplied from the drive voltage generator  400 , outputs gate drive voltages (G 1 , G 2 , . . . Gn) to a plurality of gate lines. Here, the gate lines are arranged in a horizontal direction (in the drawing) of the LCD panel  500 .  
         [0083]    The drive voltage generator  400  receives the first signal, which determines the period and amplitude of the common electrode voltage Vcom as described above, and either increases or decreases a voltage level of the first signal. Also, the drive voltage generator  400  outputs the common electrode voltage Vcom to the LCD panel  500 . In the present invention, there are first, second and third common electrode voltages Vcom 1 , Vcom 2  and Vcom 3 , and the first, second and third common electrode voltages Vcom 1 , Vcom 2  and Vcom 3  swing by synchronizing to a predetermined period with respect to the gate drive voltages (G 1 , G 2 , . . . Gn).  
         [0084]    The LCD panel  500  includes the plurality of gate lines for transmitting scanning signals; the plurality of data lines, which cross the gate lines and transmit image signals; switching elements (TFTs), which are formed in regions defined by the crossing of the gate lines and the data lines and are connected to the same; the liquid crystal capacitor Clc for transmitting a light provided by a back light (not shown) according to an “on” operation of the switching element, the light being in proportion to the data drive voltages (D 1 , D 2 , . . . Dm); and a storage capacitor Cst for accumulating the data drive voltages (D 1 , D 2 , . . . Dm) when the switching element is on, and applying the stored voltages to the liquid crystal capacitor Clc when the switching element is off.  
         [0085]    In operation, the LCD panel  500  displays the image signals supplied from the data driver  200  based on the first, second and third common electrode voltages Vcom 1 , Vcom 2  and Vcom 3 . Common electrode lines are arranged on the LCD panel  500  such that they receive one of the three common electrode voltages Vcom 1 , Vcom 2  and Vcom 3  from the drive voltage generator  400 . That is, a first common electrode line receives the first common electrode voltage Vcom 1 , a second common electrode line receives the second common electrode voltage Vcom 2 , a third common electrode line receives the third common electrode voltage Vcom 3 , and a fourth common electrode line receives the first common electrode voltage Vcom 1 . Although the second preferred embodiment was described with three common electrode voltages, it is also possible to use different numbers of common electrode voltages such as two or four.  
         [0086]    [0086]FIG. 11 shows a schematic view of an equivalent circuit of the LCD of FIG. 10.  
         [0087]    As shown in the drawing, the gate lines, which are arranged horizontally (in the drawing), are connected to a single common electrode line. Also, a single common electrode line is arranged between the gate lines. There are three common electrode lines, which apply the first, second and third common electrode voltages Vcom 1 , Vcom 2  and Vcom 3 . The first common electrode voltage Vcom 1  is applied to the liquid crystal capacitor on the first line, the second common electrode voltage Vcom 2  is applied to the liquid crystal capacitor on the second line, and the third common electrode voltage Vcom 3  is applied to the liquid crystal capacitor on the third line.  
         [0088]    Further, a first terminal of the switching elements is connected to the gate lines, a second terminal of the switching elements is connected to the data lines, a third terminal of the switching elements is connected to one end of the liquid crystal capacitors, which are connected to one end of the storage capacitors. Connections of the other ends of the liquid crystal capacitors are as follows. The other ends belonging to the liquid crystal capacitors positioned at odd lines and odd columns are connected to the common electrode lines, which are positioned at upper ends of the gate lines to which the switching elements are connected; and the other ends belonging to the liquid crystal capacitors and positioned at even lines and even columns are connected to lower ends of the gate lines to which the switching elements are connected. The other ends of the liquid crystal capacitors can also be connected in the opposite manner.  
         [0089]    Only one example of the application of the three common electrode voltages Vcom 1 , Vcom 2  and Vcom 3  through the plurality of common electrode lines, which are arranged with and between the gate lines and bundled in three portions in a left portion of the LCD panel, has been described. However, it is possible for the common electrode lines to be arranged and bundled at a right portion of the LCD panel. Further, it is also possible for the common electrode lines to be arranged and bundled on both left and right portions of the LCD panel.  
         [0090]    In the second preferred embodiment of the present invention as described above, the common electrode voltage output by the drive voltage generator  400  is applied to the common electrode lines formed horizontally on the LCD panel  500  to generate an overshoot. Accordingly, a response speed of the LCD is improved.  
         [0091]    [0091]FIG. 12 is a schematic view used to describe a single common line wiring structure in dot inversion according to the second preferred embodiment of the present invention.  
         [0092]    Common electrode lines are laid out horizontally (in the drawing). Odd gate lines (G 1 , G 3 , . . . ) are formed adjacent to odd common electrode lines and therefore are laid out horizontally, and even gate lines (G 2 , G 4  . . . ) are formed adjacent to even common electrode lines and therefore are laid out horizontally. Data lines (D 1 , D 2 , D 3 , D 4  . . . ) are provided vertically (in the drawing).  
         [0093]    Further, first storage capacitors connect the odd common electrode lines to the odd gate lines (G 1 , G 3  . . . ) in regions divided by the odd data lines (D 1 , D 3 , . . . ) and the even data lines (D 2 , D 4 , . . . ). The first storage capacitors also connect the even common electrode lines to the even gate lines (G 2 , G 4 , . . . ) in regions divided by the odd data lines (D 1 , D 3 , . . . ) and the even data lines (D 2 , D 4  . . . ). Second storage capacitors connect the even common electrode lines to the odd gate lines (G 1 , G 3 , . . . ) in regions divided by the even data lines (D 2 , D 4 , . . . ) and the odd data lines (D 1 , D 3 , . . . ). The second storage capacitors also connect the even common electrode lines to the even gate lines (G 2 , G 4 , . . . ) in regions divided by the even data lines (D 2 , D 4 , . . . ) and the odd data lines (D 1 , D 3 , . . . ).  
         [0094]    Various common electrode voltages—first, second and third common electrode voltages Vcom 1 , Vcom 2  and Vcom 3  in the present invention—are applied to the common electrode lines of the LCD panel of the above. That is, the first common electrode voltage Vcom 1  is applied to a first common electrode line, the second common electrode voltage Vcom 2  is applied to a second common electrode line, the third common electrode voltage Vcom 3  is applied to a third common electrode line, and the first common electrode voltage Vcom 1  is also applied to a fourth common electrode line.  
         [0095]    [0095]FIG. 13 shows a schematic view used to describe a divided pixel structure in dot inversion according to the second preferred embodiment of the present invention.  
         [0096]    As shown in the drawing, common electrode lines are arranged horizontally (in the drawing) between gate lines. A first pixel is formed in a region formed by odd gate lines (G 1 , G 3 , . . . ) and even gate lines (G 2 , G 4 , . . . ), and by odd data lines (D 1 , D 3 , . . . ) and even data lines (D 2 , D 4 , . . . ). One end of the first pixel is connected to the odd gate lines (G 1 , G 3 , . . . ), and its other end is connected to the common electrode lines. A second pixel is formed in a region formed by the odd gate lines (G 1 , G 3 , . . . ) and the even gate lines (G 2 , G 4 , . . . ), and by the odd data lines (D 1 , D 3 , . . . ) and the even data lines (D 2 , D 4 , . . . ). One end of the second pixel is connected to the even gate lines (G 2 , G 4  . . . ). A third pixel is formed in a region formed by the odd gate lines (G 1 , G 3 , . . . ) and the even gate lines (G 2 , G 4 , . . . ), and by the even data lines (D 2 , D 4 , . . . ) and the odd data lines (D 1 , D 3 , . . . ). One end of the third pixel is connected to the odd gate lines (G 1 , G 3  . . . ). A fourth pixel is formed in a region formed by the odd gate lines (G 1 , G 3 , . . . ) and the even gate lines (G 2 , G 4 , . . . ), and by the even data lines (D 2 , D 4 , . . . ) and the odd data lines (D 1 , D 3 , . . . ). One end of the fourth pixel is connected to the common electrode lines and its other end is connected to the even gate lines (G 2 , G 4 , . . . ).  
         [0097]    Various common electrode voltages—first, second and third common electrode voltages Vcom 1 , Vcom 2  and Vcom 3  in the present invention—are applied to the common electrode lines of the LCD panel of the above. That is, the first common electrode voltage Vcom 1  is applied to a first common electrode line, the second common electrode voltage Vcom 2  is applied to a second common electrode line, the third common electrode voltage Vcom 3  is applied to a third common electrode line, and the first common electrode voltage Vcom 1  is also applied to a fourth common electrode line.  
         [0098]    To operate the above LCD using a dot inversion drive method, pixels are divided on both sides of the gate lines. Here, separation between the gate lines and the common electrode lines reduces defects caused by a line short.  
         [0099]    In the embodiments as described above, the common electrode lines are arranged between the horizontally provided gate lines enhancing the response speed of liquid crystals. However, it is also possible, if necessary to reduce an aperture ratio, to arrange the common electrode lines between the vertically provided data lines.  
         [0100]    In the first embodiment of the present invention described above, when driving the common electrode voltage, because of the limit to the swing width to which swinging of the common electrode voltage must be performed, overshoot is small. Accordingly, only minor response speed improvements are realized. However, in the second preferred embodiment of the present invention, a swing width of at least four times greater than that obtained in the first embodiment is realized, thereby greatly improving the response speed of liquid crystals. Further, in the second embodiment, an enhanced response speed is achieved with the application of a dot inversion structure without modification.  
         [0101]    Although preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concepts herein taught that may appear to those skilled in the present art will still fall within the spirit and scope of the present invention, as defined in the appended claims.