Abstract:
A charge coupled device has a transfer electrode portion having a first gate electrode, a second gate electrode having an end portion partially overlapping an end portion of the first gate electrode, and a third gate electrode having one end portion partially overlapping the other end portion of the first gate electrode. The charge coupled device also has a charge transfer portion located in a semiconductor substrate under the first, second and third gate electrodes, which includes a first potential area formed in the semiconductor substrate under the second gate electrode and a second potential area formed in the semiconductor substrate under the third gate electrode. The charge coupled device further has a clock portion which includes a first clock terminal connected to the first and third gate electrodes, and a second clock terminal connected to the second gate electrode. This charge coupled device may prevent unnecessary local potential barriers or wells produced by a misalignment, and thus may provide increased charge transfer efficiency.

Description:
RELATED APPLICATIONS 
     This application is a continuation-in-part of prior application Ser. No. 08/772,183, filed Dec. 19, 1996, now U.S. Pat. No. 5,986,295, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to semiconductor devices and manufacturing methods therefor, and more particularly, to charge coupled devices which enable charge transfer and manufacturing methods therefor. 
     BACKGROUND OF THE INVENTION 
     Charge coupled devices are dynamic charge transfer devices which transfer charge via a predetermined path according to clock pulses applied to a gate electrode. A charge coupled device may be constituted of metal oxide semiconductor (MOS) transistors which are connected in series to one another via their gates. 
     Charge coupled devices are widely used as imaging devices, whereby the charge coupled device is combined in parallel to a group of photo-diodes to form a device capable of sensing optical signals. Charge coupled devices are also used in various analog and digital signal processing applications. 
     Early charge coupled devices, such as the one suggested by Bell and Smith in 1969, comprised an insulation layer and gate electrodes arranged to constitute a MOS capacitor on a semiconductor substrate. However, the simple planar arrangement of the gate electrodes on this device made it difficult to control the shapes of the potential wells under the gate electrodes. Therefore, devices have been suggested in which the gate electrodes are isolated from one another while being partially overlapped with each other. Of these devices, the structure which has gained the widest acceptance has a plurality of gate electrodes formed on a semiconductor substrate with insulation layers formed therebetween, and charge transfer areas formed under the gate electrodes. 
     Charge-coupled devices are divided into a pseudo 2-phase charge coupled device, 3-phase charge coupled devices, and 4-phase charge coupled devices according to their driving method, and the structural configurations of the charge coupled devices are modified in accordance with their driving methods. The pseudo 2-phase charge coupled device uses simple driving pulses, despite its low capacity of charge transfer as compared with other configurations, thus it is widely used as a horizontal charge transfer device of a charge coupled device-type image device requiring high speed operation. 
     FIG. 1 is a sectional view of a conventional pseudo 2-phase charge coupled device. In FIG. 1, reference numeral  10  denotes a semiconductor substrate, reference numeral  12  denotes a buried channel for a buried charge coupled device, and reference numeral  20  denotes an interlayer insulation layer. As illustrated in FIG. 1, such a conventional charge coupled device has first gate electrodes  16  spaced from one another by a predetermined distance, second gate electrodes  18  positioned between the first gate electrodes  16 , and potential areas  14  formed under the second gate electrodes  18 . A first clock terminal φ1 is connected to a first gate electrode  16  and a second gate electrode  18  to form a unit transfer group, and a second clock terminal φ2 is connected to a first gate electrode  16  and a second gate electrode  18  to form another unit transfer group. Mutually opposite clock signals are applied to the first and second clock terminals φ1 and φ2. 
     The potential areas  14  are formed by ion implantation using the first gate electrodes  16  as a mask, and thus potential areas  14  are aligned with the first gate electrodes  16 . These potential areas  14  form potential wells in a charge transferring direction. 
     The migration of charge of the charge coupled device of FIG. 1 is illustrated in the potential distribution diagram of FIG.  2 . Referring to FIG. 2, charge stored in a potential well in the left side of the figure migrates to the right when a clock pulse is applied to the first and second clock terminals φ1 and φ2. The arrow in FIG. 2 indicates the direction of charge transfer. 
     In many applications, such as high speed horizontal charge coupled devices of a charge coupled device-type image device, it is desirable to form as many transfer groups as possible in an area of a given unit length. However, as the pseudo 2-phase charge coupled device of FIG. 1 applies a single clock pulse to two gate electrodes, limitations in the resolution achievable during photolithography place a limit on the minimum length of the charge transfer groups. Such limits emerge as a serious problem in applications requiring a large number of charge transfer groups per unit area. 
     To avoid the above-mentioned problem, a device has been suggested in which a single gate electrode is used as a unit transfer group by forming a potential area below only half the area of each gate electrode. Such a device is illustrated in FIG.  3 . 
     The charge coupled device depicted in FIG. 3 is identical to the charge coupled device depicted in FIG. 1 in terms of the arrangement of the first and second gate electrodes  16  and  18 . However, a potential area is  15  formed under each of the first and second gate electrodes  16  and  18 , and each of the clock terminals φ1 and φ2 are connected to only a single gate electrode. Through these modifications, the size of the area reserved for the charge coupled device of FIG. 3 can be reduced to at least half of the area of the charge coupled device of FIG.  1 . Thus, if the sizes of horizontal charge transfer devices of a charge coupled device-type image device are comparable, the device of FIG. 3 can include twice as many charge transfer groups as the device of FIG.  1 . 
     In fabricating the charge coupled device of FIG. 3, the potential area  15 , may be formed via ion implantation after an ion implantation mask is formed using photolithography. However, when such a method is used, it may be difficult to align each potential area  15  with each of the gate electrodes  16  and  18 . Thus, in the charge coupled devices of FIG. 3, there is a likelihood that an unnecessary local potential barrier or well is created due to the misalignment of a potential area and a gate electrode at a gate electrode boundary, thereby lowering charge transfer efficiency. 
     U.S. Pat. No. 4,097,885 discloses another charge coupled device having a gate structure that utilizes three depositions of electrically conductive material to form electrodes. This patent indicates that via such a technique a two-phase charge coupled device may be fabricated that occupies less wafer surface area and operates at faster speeds than conventional charge coupled devices. 
     SUMMARY OF THE INVENTION 
     In light of the aforementioned limitations with conventional charge coupled devices, it is an object of the present invention to provide a charge coupled device which provides higher charge transfer efficiency. 
     It is a second object of the present invention to provide a charge coupled device where the area occupied by a unit transfer group is reduced. 
     Yet another object of the present invention is to provide a method for manufacturing such a charge coupled device. 
     The above-stated objectives are provided by a charge coupled device which includes a transfer electrode portion having a first gate electrode, a second gate electrode which has an end portion that partially overlaps an end portion of the first gate electrode, and a third gate electrode which has one end portion partially overlapping the other end portion of the first gate electrode and the other end portion thereof partially overlapping the other end portion of the second gate electrode. This charge coupled device further includes a charge transfer portion located in a semiconductor substrate under the first, second and third gate electrodes. The charge transfer portion has a first potential area partially formed in the semiconductor substrate under the second gate electrode and a second potential area formed in the semiconductor substrate under the third gate electrode. This charge coupled device also includes a clock portion comprising a first clock terminal that is simultaneously connected to both the first and third gate electrodes, and a second clock terminal that is connected to the second gate electrode. 
     In one embodiment of the present invention, the length of the second gate electrode is equal to the sum of the lengths of the first and third gate electrodes. In another embodiment of the present invention, the size of the first potential area is the same as that of the second potential area. In still another embodiment of the present invention, an end portion of the first potential area is aligned with an end portion of the first gate electrode, and the end portions of the second potential area are aligned with end portions of the first and second gate electrodes. 
     In another aspect of the present invention, there is provided a method for manufacturing a charge coupled device comprising the steps of: (a) forming a first gate electrode on a gate insulation layer formed on a region of semiconductor material; (b) coating an exposed surface of the first gate electrode with a first insulation layer; (c) forming a photoresist pattern on the first insulation layer and the gate insulation layer, wherein the photoresist layer is patterned so as to expose portions of the first insulation layer and the first gate insulation layer adjacent the first insulation layer; (d) forming a first potential area by implanting impurity ions, using the photoresist pattern and the first gate electrode as an ion implantation mask; (e) forming a second gate electrode wherein an end portion thereof partially overlaps an end portion of the first gate electrode; (f) forming a second insulation layer on exposed surfaces of the second gate electrode; (g) forming a second potential area in the semiconductor substrate by implanting impurity ions, using the first and second gate electrodes as an ion implantation mask; (h) forming a third gate electrode wherein an end portion thereof overlaps an end portion of the first gate electrode opposite the second gate electrode and an end portion thereof overlaps an end portion of the second gate electrode opposite the first gate electrode. Additionally, a buried channel layer may be formed near the surface of the semiconductor substrate, and the first and third gate electrodes may be connected to a first clock terminal, and the third gate electrode may be connected to a second clock terminal. 
     Therefore, according to the charge coupled devices and manufacturing methods of the present invention, the area occupied by a unit transfer group can be reduced and a potential area is formed to be aligned with a gate electrode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
     FIG. 1 is a sectional view of a conventional charge coupled device; 
     FIG. 2 is a potential distribution view illustrating the migration of charge of the charge coupled device shown in FIG. 1; 
     FIG. 3 is a sectional view of another conventional charge coupled device; 
     FIG. 4 is a sectional view of a charge coupled device according to the present invention; and 
     FIGS. 5A to  5 G are sectional views of the steps for manufacturing a charge coupled device according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those of skill in the art. 
     FIG. 4 illustrates a preferred embodiment of a charge coupled device according to the present invention. As shown in FIG. 4, the charge coupled device has a transfer electrode portion, a charge transfer portion, and a clock portion. 
     The transfer electrode portion has a plurality of first gate electrodes  36 , a plurality of second gate electrodes  46  and a plurality of third gate electrodes  54 . As illustrated in FIG. 4, the second gate electrodes  46  each have an end portion which partially overlaps one end portion of its adjacent first gate electrode  36 . Similarly, one end portion of each of the third gate electrodes  54  partially overlaps the other end portion of each first gate electrode  36 , and the other end portion of each of the third gate electrodes  54  partially overlaps the other end portion of its adjacent second gate electrode  46 . 
     As is also illustrated in FIG. 4, the charge transfer portion of the charge coupled device has a plurality of first potential areas  44  which are formed in the semiconductor substrate underlying the second gate electrodes  46 , and a plurality of second potential areas  52  which are formed in the semiconductor substrate underlying the third gate electrodes  54 . 
     The clock portion of the charge coupled device illustrated in FIG. 4 comprises a plurality of first clock terminals φ1 and a plurality of second clock terminals φ2. Each of the first clock terminals φ1 are simultaneously connected to adjacent first and third gate electrodes  36  and  54 , and each of the second clock terminals φ2 are connected to a corresponding second gate electrode  46 . 
     As illustrated in FIG. 4, the length of each second gate electrode  46  is equal to the sum of the lengths of the first and third gate electrodes  36  and  54 . The configuration and size of each first potential area  44  preferably matches the configuration and size of each second potential area  52 . These first and second potential areas  44  and  52  form a potential well in a charge transferring direction, and mutually opposite clock signals are applied to the first and second clock terminals φ1 and φ2. 
     In a preferred embodiment of the present invention, an end portion of each first potential area  44  is aligned with an end portion of each first gate electrode  36 . In this embodiment, the end portions of the second potential areas  52  are aligned with the other end portion of the respective first gate electrodes  36  and one of the end portions of the respective second gate electrodes  46 . Thus, according to the charge coupled device of the present invention, reduction of charge efficiency due to the formation of an unnecessary local potential barrier or well is prevented as the potential areas are aligned with the gate electrodes. 
     The portions of FIG. 4 which were not described will be described with reference to FIGS. 5B through 5G. 
     FIGS. 5A through 5G illustrate methods of forming charge coupled devices according to the present invention. FIG. 5A illustrates the step of forming a buried channel layer  32  in a semiconductor substrate  30 . As shown in FIG. 5A, the buried channel layer  32  may be formed by implanting N-type ions into the overall surface of a P-type semiconductor substrate  30 , as is well understood by those of skill in the art. As will also be understood by those of skill in the art, the buried channel layer  32  is formed as a path for the migration of charge. A charge coupled device having the buried channel layer  32  near the surface of the semiconductor substrate  30 , as shown in FIG. 5A, is referred to as a buried charge coupled device (BCCD), whereas a charge coupled device having no buried channel layer is referred to as a surface charge coupled device (SCCD). Thus, although FIG. 5A depicts a charge coupled device having a buried channel layer  32 , the scope of the present invention is not limited to BCCD devices and related methods of manufacture, but instead is as is set forth in the claims appended hereto. 
     FIG. 5B illustrates a method according to the present invention for forming the first gate electrodes  36 , wherein a gate insulation layer  34  is formed by growing, for example, silicon dioxide, over the surface of buried channel layer  32 . A first conductive material layer (not shown) of, for example, polysilicon, is then formed atop the surface of gate insulation layer  34 . The first gate electrodes  36  may then be formed to be spaced from each other by a predetermined distance by selectively removing the conductive materials layer via photolithography. 
     FIG. 5C illustrates a method according to the present invention for forming the first gate insulation layers  38 . Such first gate insulation layers  38  may be formed of silicon dioxide by exposing the surfaces of the first gate electrodes  36  to oxygen atmosphere. As illustrated in FIG. 5C, the first insulation layers  38  may entirely cover the respective first gate electrodes  36 . 
     FIG. 5D illustrates a method according to the present invention for forming the first potential areas  44 . As illustrated in the figure, photoresist patterns  40  may be formed by selectively applying and developing a photoresist film atop the device while leaving exposed a portion of the respective first gate electrodes  36  and areas for forming second gate electrodes. First potential areas  44  may then be formed in a portion of an area reserved for the second gate electrodes by implanting impurity ions  42 , using the photoresist patterns  40  as an ion implantation mask. In the illustrated embodiment, the impurity ions  42  are P-type ions, as the buried channel layer  32  shown in FIG. 5D is N-type. 
     In the embodiment of the present invention illustrated in FIG. 5D, the photoresist patterns  40  are formed to expose the right end portions of the first gate electrodes  36  and the left portions of the areas in which the second gate electrodes will be formed. In this manner, the first potential areas  44  may be formed so that their left end portions are aligned with the first gate electrodes  36 , and their right end portions are aligned with the photoresist patterns  40 . 
     FIG. 5E illustrates a method according to the present invention for forming the second gate electrodes  46 . As shown in the figure, the photoresist patterns  40  of FIG. 5D are removed, and a second conductive material layer (not shown) of, for example, polysilicon, may then be formed atop the device. Second gate electrodes  46  may then be formed by patterning the second conductive material layer in a manner similar to that described above with respect to formation of first gate electrodes  36 . Thereafter, second insulation layers  48  may be formed atop the second gate electrodes  46 . As will be understood by those of skill in the art, the second insulation layers  48  may be formed in the same manner as is described above with respect to the first insulation layers  38 . 
     In a preferred embodiment of the present invention, the second gate electrodes  46  are formed so that their left end portions partially overlap the right end portions of the first gate electrodes  36 , and their right end portions are positioned near the third gate electrode areas. 
     FIG. 5F illustrates a method according to the present invention for forming the second potential areas  52 . As illustrated in FIG. 5F, the second potential areas  52  may be formed on the semiconductor substrate in the area reserved for the third gate electrodes  54  (described below) by implanting, for example, P-type impurity ions  50  atop the semiconductor substrate  30  having the first and second gate electrodes  36  and  46  formed therein. In this embodiment, the second potential areas  52  preferably are identical to the first potential areas  44  in terms of shape, size, and concentration of impurity ions. Moreover, preferably the second potential areas  52  are formed so that their right end portions are aligned with the left end portions of the respective first gate electrodes  36 , and their left end portions are aligned with the right end portions of the respective second gate electrodes  46 . 
     FIG. 5G illustrates a method according to the present invention for forming the third gate electrodes  54 , wherein a third conductive material layer (not shown) is formed by depositing, for example, polysilicon atop the surface of the device. Third gate electrodes  54  may then be formed in their desired locations by patterning the third conductive material layer. A third insulation layer (not shown) may then be formed atop the third gate electrodes  54  in a manner similar to that described above for the first and second insulation layers  38  and  48  of FIG. 5E, and then an insulation layer  60  may be formed over the surface of the resultant structure. As illustrated in FIG. 5G, in a preferred embodiment of the present invention, the third gate electrodes  54  are formed so that their right end portions partially overlap the left end portions of the first gate electrodes  36 , while their left end portions partially overlap the right end portions of the second gate electrodes  46 . 
     As is also illustrated in FIG. 5G, the first and third gate electrodes  36  and  54  may be connected to the first clock terminal φ1 to form a unit transfer group, and the second gate electrode  46  may be connected to the second clock terminal φ2, to form another unit transfer group. In this manner, charge accumulated in the buried channel layer  32  under the gate electrodes  36 ,  46 , and  54  may be transferred in a predetermined direction according to clock pulses applied to the first and second clock terminals φ1 and φ2. 
     Note that while a preferred embodiment using electrons as a charge carrier has been described herein (for example, the first conductive type and the second conductive type were defined as P and N, respectively), those of skill in the art will understand that impurity ions of the conductive type opposite to that described should be used when holes are used as a charge carrier. Moreover, those of skill in the art will also understand that the gate insulation layer formation steps and the impurity-ion implantation steps for forming potential areas described herein may be reversed, if necessary, with the same effects. 
     Therefore, according to the charge coupled device and manufacturing method therefor described herein, the area occupied by a unit transfer group can be reduced and a potential area can be accurately aligned with a gate electrode. Consequently, an unnecessary local potential barrier or well produced by a misalignment can be prevented, thereby increasing charge transfer efficiency. 
     The present invention is not limited to the above embodiment, and it is clearly understood that many variations are possible within the scope and spirit of the present invention by those of skill in the art.