Abstract:
A delay compensation circuit compensates a signal delay between a signal driver and receiver when transmitting a digital signal through a transmission line. The circuit includes an inverter connected in parallel with the transmission line for inverting the digital signal, and pull-down device connected in parallel with the inverter for compensating a fall time of the digital signal according to an output of the inverter.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a circuit for compensating delay time of the digital signals transmitted through a transmission line between a signal driver and a receiver, and in particular, to such circuit connectable in parallel with the transmission line in order to reduce the delay time by advantageously modifying the edges of the signals. 
     Generally, a long transmission line between the signal driver and receiver develops resistive and capacitive impedance that deimpedes the output signal of a driver transmitted to a receiver, thus resulting in a flattened waveform of the signal with increased falling or rising times. Also, the resistive and capacitive impedance causes undesirable power consumption. 
     FIG. 1 shows a conventional circuit for solving the problem of increased resistive and capacitive impedance in a transmission line. A repeater RP is added between the signal driver 10 and receiver 20. 
     The repeater RP provided before receiver 20 corrects the distortion of the signal waveform caused by the resistance and capacitance of the transmission line, and reduces the time required for the rising or falling edge of the signal. The repeater generally includes a plurality of inverters connected in multiple stages. The number of the inverters should be even so that the phase of the input signal is the same as that of the output signal. Hence, a minimum of two inverters is necessary to cause delay of the signal. As a result, the repeater provides the correction of the signal waveform, but does not compensate the delay time of the signal. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a circuit for compensating delay time of a signal through a transmission line caused by the resistance and capacitance thereof. 
     It is another object of the present invention to provide a circuit for reducing the rise and fall times of the signal on the transmission line. 
     A delay compensation circuit according to the present invention is connected before a receiver on a transmission line and in parallel to the transmission line, so that the transmission line is supplied with a negative power source (V SS ) for promptly bypassing the positive charges existing in the transmission line as soon as the falling edge of the transmitted signal is generated, thus minimizing the fall time without delaying the transmitted signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Reference is now made by example in conjunction with the accompanying drawings, in which: 
     FIG. 1 shows a conventional circuit diagram for a delay compensation circuit; 
     FIG. 2 shows an operational timing diagram of FIG. 1; 
     FIG. 3 is a circuit diagram for a delay compensation circuit in accordance with a preferred embodiment of the present invention; and 
     FIG. 4 is an operational timing diagram for the delay compensation circuit of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 3, the delay compensation circuit is connected in parallel with a transmission line &#34;L&#34; between a driver 10 and receiver 20. The delay compensation circuit includes a sensor 30 for sensing the falling edge of a signal on the transmission line &#34;L&#34;, four transistors 40, 50, 60, 70, and a delay circuit comprising two inverters 80 and 90. The gates and drains of the transistors 50 and 60 are interconnected with one another. The connecting point &#34;B&#34; between the gates of the transistors 50 and 60 is connected to an output terminal of the sensor 30. The connecting point &#34;A&#34; between the transmission line &#34;L&#34; and the sensor 30 is connected to an input terminal of the delay circuit. The source and drain of the transistor 40 are respectively connected to a negative power source &#34;V SS  &#34; and the source of transistor 50. The gate of the transistor 40 is connected to an output terminal of the delay circuit. The source and drain of the transistor 70 are respectively connected to a positive power source &#34;V DD  &#34; and the source of the transistor 60. The gate of transistor 70 is connected to the output of the delay device. 
     The transistors 50 and 60 have the same construction and function as an inverter. The trip point of the sensor 30 is positioned at three quarters or more of an interval from a logic &#34;low&#34; to a logic &#34;high&#34; of an input logic signal. 
     For example, when a logic signal &#34;a&#34; as shown in FIG. 4 is transmitted through the transmission line &#34;L&#34;, the sensor 30 senses the falling edge of the signal at time P 1  shown in &#34;a&#39;&#34;, and supplies the signal as shown by &#34;b&#34; to the point &#34;B&#34;. In this case, the n-type transistor 50 is turned on, whereas the p-type transistor 60 is turned off. Meanwhile, the delay circuit delays the signal introduced into the point &#34;A&#34;. The delay of the signal is accomplished by the inverters 80 and 90, and thus the signal appears at the output of the delay circuit after a predetermined time. Consequently, the output of the delay circuit maintains the previous &#34;high&#34; state during the voltage of the point &#34;A&#34; falling into &#34;low&#34; state. 
     The gates of the transistors 40 and 70 are connected to the output of the delay circuit, thus maintaining &#34;high&#34; voltage during the falling edge interval when the voltage of the point &#34;A&#34; is in transition from &#34;high&#34; level to &#34;low&#34; level. Of course, the n-type transistor 40 is turned on. 
     Thus, when the sensor 30 senses the falling edge of the transmitted signal &#34;a&#34; at time &#34;P 1  &#34; of &#34;a,&#34; as shown in FIG. 4, the transistors 40 and 50 are turned on so that the negative power source V SS  is connected therethrough with the point &#34;A&#34; at time &#34;P 2  &#34; in &#34;a&#39;&#34; of FIG. 4, thus preventing any positive charging of point &#34;A&#34;. Hence, the voltage of the point &#34;A&#34; is dropped at time &#34;P 3  &#34; to the negative voltage level of V SS . 
     In this case, if the inventive circuit is not used, the voltage of the point &#34;A&#34; is gradually dropped to V SS  at time &#34;P 4  &#34; as shown by in FIG. 4. However, the inventive circuit decreases the fall time of the logic signal by a time P 4  minus P 3 . 
     According to experiments, if V CC  =4V, V SS  =0V, the temperature is 83° C., and the capacitance of the transmission line is 6pF, the signal delay through the transmission line in the inventive circuit is compared with that in the conventional circuit as shown in the table 1. In this case, a reference &#34;D 2V  &#34; shows a delay time of the transmission signal &#34;a&#34; on transmission line &#34;L&#34; until fall by up to &#34;2V&#34;, and a reference &#34;D 1V  &#34; shows another delay time until fall by up to &#34;1V&#34; from the reference &#34;D 2V  &#34;. Namely, the inventive circuit reduces the signal delay over 70 percent. Particularly, the inventive circuit is not connected in series but parallel with the transmission line &#34;L&#34;, so that the gate delay is eliminated, which is not achieved with the conventional circuit. 
     
                       TABLE 1______________________________________Condition             D.sub.2V                         D.sub.1V______________________________________Installing the Inventive Circuit                 1.6 ns  0.6 nsUninstalling the Inventive Circuit                 1.6 ns  2.0 ns______________________________________ 
    
     Thus, the inventive circuit substantially eliminates the a distortion of the signal or delay time of the signal caused by the resistance and capacitance inherent in the transmission line. 
     The descriptions that have been made heretofore with reference to the attached drawings define a preferred embodiment which is intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.