Abstract:
The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The disclosure of Japanese Patent Application No. 2011-48854 filed on Mar. 7, 2011 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    The present invention relates to a semiconductor device and, more particularly, relates to a semiconductor device having a variable resistance circuit. 
         [0003]    A related-art semiconductor device has a variable resistance circuit (terminating resistance element) including a first resistance element and a first transistor coupled in parallel, a replica circuit including a second resistance element and a second transistor coupled in parallel, a constant current source for passing constant current to the replica circuit, and an operational amplifier controlling gate voltage of the first and second transistors so that voltage across the terminals of the replica circuit becomes predetermined voltage. In the semiconductor device, even in the case where the resistance value of the resistance element fluctuates due to fluctuations in manufacture process and temperature, the resistance value of the variable resistance circuit can be set to a predetermined value (refer to, for example, patent literature 1). 
       [Related-Art Literature] 
       [0000]    
       
         [Patent Literature] 
         [Patent Literature 1] 
         Japanese Unexamined Patent Publication No. 2007-288737 
       
     
       SUMMARY 
       [0007]    However, in a related-art semiconductor device, an adjustable range of a resistance value of a variable resistance circuit is small. Consequently, in the case where the resistance value of the resistance element largely fluctuates due to fluctuations in the manufacture process and temperature, a problem occurs such that the resistance value of the variable resistance circuit cannot be set to a predetermined value. 
         [0008]    A main object of the present invention is therefore to provide a semiconductor device in which an adjustable range of the resistance value of a variable resistance circuit is large. 
         [0009]    A semiconductor device according to the present invention has a variable resistance circuit, first to M-th replica circuits (where M is an integer of 2 or larger), and operational amplifiers each provided in correspondence with each of the replica circuits. Each of the variable resistance circuit and the first to M-th replica circuits includes first to M-th resistance elements coupled in series between a first voltage line and a predetermined node, and first to M-th transistors provided in correspondence with the first to M-th resistance elements, respectively, and each coupled between the first voltage line and an electrode on the predetermined node side of a corresponding resistance element. Each of the first to M-th replica circuits further includes a constant current source coupled between the predetermined node and a second voltage line and passing predetermined constant current. Each of (m+1)th to M-th transistors of the m-th replica circuit (where m is any integer from 1 to M−1) is fixed in a non-conductive state. Gates of a plurality of k-th transistors which are not fixed in the non-conductive state out of k-th transistors (where k is any integer from 1 to M) of M+1 pieces included in the variable resistance circuit and the first to M-th replica circuits are coupled to one another. The operational amplifier controls the gate voltage of the k-th transistor of a corresponding to k-th replica circuit so that voltage of the predetermined node of the corresponding k-th replica circuit becomes predetermined reference voltage. 
         [0010]    In the semiconductor device according to the present invention, the variable resistance circuit is formed by M sets of resistance elements and transistors, and the gate voltage of M pieces of transistors is controlled by M sets of replica circuits and operational amplifiers. Consequently, the adjustable range of the resistance value of the variable resistance circuit can be made wider than that in the related-art technique. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram illustrating the configuration of a semiconductor device according to a first embodiment of the present invention. 
           [0012]      FIG. 2  is a diagram illustrating the operation of the semiconductor device shown in  FIG. 1 . 
           [0013]      FIG. 3  is another diagram illustrating the operation of the semiconductor device shown in  FIG. 1 . 
           [0014]      FIG. 4  is a diagram illustrating temperature dependency of gate voltage shown in  FIG. 1 . 
           [0015]      FIG. 5  is another diagram illustrating the temperature dependency of the gate voltage shown in  FIG. 1 . 
           [0016]      FIG. 6  is a circuit diagram showing a comparative example of the first embodiment. 
           [0017]      FIG. 7  is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention. 
           [0018]      FIG. 8  is a diagram of the operation of the semiconductor device illustrated in  FIG. 7 . 
           [0019]      FIG. 9  is a circuit diagram illustrating a comparative example of the second embodiment. 
           [0020]      FIG. 10  is a circuit diagram showing a configuration of a semiconductor device according to a third embodiment of the invention. 
           [0021]      FIG. 11  is a diagram showing the operation of the semiconductor device illustrated in  FIG. 10 . 
           [0022]      FIG. 12  is another diagram showing the operation of the semiconductor device illustrated in  FIG. 10 . 
           [0023]      FIG. 13  is a diagram illustrating the temperature dependency of the gate voltage shown in  FIG. 10 . 
           [0024]      FIG. 14  is a circuit diagram illustrating a configuration of a semiconductor device according to a fourth embodiment of the invention. 
           [0025]      FIG. 15  is a diagram illustrating the operation of the semiconductor device shown in  FIG. 14 . 
           [0026]      FIG. 16  is a circuit diagram illustrating a configuration of a semiconductor device according to a fifth embodiment of the invention. 
           [0027]      FIG. 17  is a circuit diagram illustrating a configuration of a semiconductor device according to a sixth embodiment of the invention. 
           [0028]      FIG. 18  is a diagram illustrating the operation of the semiconductor device shown in  FIG. 17 . 
           [0029]      FIG. 19  is another diagram illustrating the operation of the semiconductor device shown in  FIG. 17 . 
           [0030]      FIG. 20  is a block diagram illustrating the layout of a semiconductor device according to a seventh embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
     First Embodiment 
       [0031]    A semiconductor device according to a first embodiment of the present invention has, as illustrated in  FIG. 1 , a control voltage generation circuit VCG, replica circuits RP 1  to RP 3 , an output buffer DOB, and an output terminal TO. The output buffer DOB is configured as a full-speed driver circuit of a USB (Universe Serial Bus) and includes resistance elements RA 1  to RA 4  and RB 1  to RB 3 , P-channel MOS transistors P 1  to P 4 , N-channel MOS transistors Q 1  to Q 4 , and a driver DR. 
         [0032]    The resistance elements RA 1  to RA 3 , the P-channel MOS transistor P 4 , and the resistance element RA 4  are coupled in series between a line of power supply voltage VDD and the output terminal TO. The sources of the P-channel MOS transistors P 1  to P 3  receive the power supply voltage VDD, and the drains are coupled to electrodes on the lower voltage side (the output terminal TO side) of the resistance elements RA 1  to RA 4 . 
         [0033]    The resistance elements RB 1  to RB 3  and the N-channel MOS transistor Q 4  are coupled in series between the line of the ground voltage VSS and the drain of the P-channel MOS transistor P 4 . The sources of the N-channel MOS transistors Q 1  to Q 3  receive the ground voltage VSS, and the drains are coupled to electrodes on the higher voltage side (the output terminal TO side) of the resistance elements RB 1  to RB 3 . The gates of the transistors P 4  and Q 4  are coupled to each other. The driver DR transmits an internal data signal φD to the gates of the transistors P 4  and Q 4 . 
         [0034]    Each of the replica circuits RP 1  to RP 3  is a replica of the output buffer DOB and includes the resistance elements RA 1  to RA 4  and RB 1  to RB 4 , the P-channel MOS transistors P 1  to P 4 , the N-channel MOS transistors Q 1  to Q 4 , and the constant current sources CA and CB. The resistance elements RA 1  to RA 4  and RB 1  to RB 3  of the replica circuits RP 1  to RP 3  have the same resistance values as those of the resistance elements RA 1  to RA 4  and RB 1  to RB 3  of the output buffer DOB, respectively. The resistance element RB 4  in each of the replica circuits RP 1  to RP 3  has the same resistance value as that of the resistance element RA 4  of the output buffer DOB. 
         [0035]    The P-channel MOS transistors P 1  to P 4  and the N-channel MOS transistors Q 1  to Q 4  in each of the replica circuits RP 1  to RP 3  have the same sizes (current drive capability) as those of the P-channel MOS transistors P 1  to P 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB. 
         [0036]    When the P-channel MOS transistor P 4  is turned on, the constant current source CA in each of the replica circuits RP 1  to RP 3  passes current having the same value as that of current which flows from the output buffer DOB to the outside via the output terminal TO. When the N-channel MOS transistor Q 4  of the output buffer DOB is turned on, The constant current source CB in each of the replica circuits RP 1  to RP 3  passes current having the same value as that of current which flows from the outside to the output buffer DOB via the output terminal TO. 
         [0037]    In each of the replica circuits RP 1  to RP 3 , the resistance elements RA 1  to RA 3 , the P-channel MOS transistor P 4 , the resistance element RA 4 , and the constant current source CA are coupled in series between the line of the power supply voltage VDD and the line of the ground voltage VSS. The sources of the P-channel MOS transistors P 1  to P 3  receive the power supply voltage VDD, and the drains are coupled to electrodes on the lower voltage side (the ground voltage VSS side) of the resistance elements RA 1  to RA 4 . The gate of the P-channel MOS transistor P 4  receives the ground voltage VSS. The P-channel MOS transistor P 4  operates as a resistance element. 
         [0038]    The resistance elements RB 1  to RB 3 , the N-channel MOS transistor Q 4 , the resistance element RB 4 , and the constant current source CB are coupled in series between the line of the ground voltage VSS and the line of the power supply voltage VDD. The sources of the N-channel MOS transistors Q 1  to Q 3  receive the ground voltage VSS, and the drains are coupled to electrodes on the higher voltage side (the power supply voltage VDD side) of the resistance elements RB 1  to RB 3 . The gate of the N-channel MOS transistor Q 4  receives the power supply voltage VDD. The N-channel MOS transistor Q 4  operates as a resistance element. 
         [0039]    Voltages VFP 1  to VFP 3  between the resistance elements RA 4  in the replica circuits RP 1  to RP 3  and the constant current sources CA are fed back to the control voltage generation circuit VCG. Voltages VFN 1  to VFN 3  between the resistance elements RB 4  in the replica circuits RP 1  to RP 3  and the constant current sources CB are fed back to the control voltage generation circuit VCG. 
         [0040]    The control voltage generation circuit VCG includes operational amplifiers AP 1  to AP 3  and AN 1  to AN 3 . The inversion input terminals (− terminals) of the operational amplifiers AP 1  to AP 3  receive a reference voltage VRP and non-inversion input terminals (+ terminals) receive the output voltages VFP 1  to VFP 3  of the replica circuits RP 1  to RP 3 . 
         [0041]    The output terminal of the operational amplifier AP 1  is coupled to the gates of the P-channel MOS transistors P 1  in the replica circuits RP 1  to RP 3  and the output buffer DOB. The operational amplifier AP 1  controls the gate voltage VP 1  of the P-channel MOS transistors P 1  in the replica circuits RP 1  to RP 3  and the output buffer DOB so that the output voltage VFP 1  of the replica circuit RP 1  matches the reference voltage VRP. 
         [0042]    The output terminal of the operational amplifier AP 2  is coupled to the gates of the P-channel MOS transistors P 2  in the replica circuits RP 2  and RP 3  and the output buffer DOB. The operational amplifier AP 2  controls the gate voltage VP 2  of the P-channel MOS transistors P 2  in the replica circuits RP 2  and RP 3  and the output buffer DOB so that the output voltage VFP 2  of the replica circuit RP 2  matches the reference voltage VRP. The P-channel MOS transistor P 2  in the replica circuit RP 1  receives the power supply voltage VDD by its gate and is fixed in the non-conductive state. 
         [0043]    The output terminal of the operational amplifier AP 3  is coupled to the gates of the P-channel MOS transistors P 3  in the replica circuit RP 3  and the output buffer DOB. The operational amplifier AP 3  controls the gate voltage VP 3  of the P-channel MOS transistors P 3  in the replica circuit RP 3  and the output buffer DOB so that the output voltage VFP 3  of the replica circuit RP 3  matches the reference voltage VRP. The P-channel MOS transistor P 3  in each of the replica circuits RP 1  and RP 2  receives the power supply voltage VDD by its gate and is fixed in the non-conductive state. 
         [0044]    The inversion input terminals (− terminals) of the operational amplifiers AN 1  to AN 3  receive a reference voltage VRN and non-inversion input terminals (+ terminals) receive the output voltages VFN 1  to VFN 3  of the replica circuits RP 1  to RP 3 . 
         [0045]    The output terminal of the operational amplifier AN 1  is coupled to the gates of the N-channel MOS transistors Q 1  in the replica circuits RP 1  to RP 3  and the output buffer DOB. The operational amplifier AN 1  controls the gate voltage VN 1  of the N-channel MOS transistors Q 1  in the replica circuits RP 1  to RP 3  and the output buffer DOB so that the output voltage VFN 1  of the replica circuit RP 1  matches the reference voltage VRN. 
         [0046]    The output terminal of the operational amplifier AN 2  is coupled to the gates of the N-channel MOS transistors Q 2  in the replica circuits RP 2  and RP 3  and the output buffer DOB. The operational amplifier AN 2  controls the gate voltage VN 2  of the N-channel MOS transistors Q 2  in the replica circuits RP 2  and RP 3  and the output buffer DOB so that the output voltage VFN 2  of the replica circuit RP 2  matches the reference voltage VRN. The N-channel MOS transistor Q 2  in the replica circuit RP 1  receives the ground voltage VSS by its gate and is fixed in the non-conductive state. 
         [0047]    The output terminal of the operational amplifier AN 3  is coupled to the gates of the N-channel MOS transistors P 3  in the replica circuit RP 3  and the output buffer DOB. The operational amplifier AN 3  controls the gate voltage VN 3  of the N-channel MOS transistors Q 3  in the replica circuit RP 3  and the output buffer DOB so that the output voltage VFP 3  of the replica circuit RP 3  matches the reference voltage VRN. The N-channel MOS transistor Q 3  in each of the replica circuits RP 1  and RP 2  receives the ground voltage VSS by its gate and is fixed in the non-conductive state. 
         [0048]    Next, the operation of the semiconductor device will be described. The operational amplifiers AP 1  to AP 3  control the gate voltages VP 1  to VP 3  of the P-channel MOS transistors P 1  to P 3  so that the output voltages VFP 1  to VFP 3  of the replica circuits RP 1  to RP 3  become equal to the reference voltage VRP in accordance with the value of combined resistance of the resistance elements RA 1  to RA 3  and the P-channel MOS transistor P 4 . 
         [0049]    If the output voltage VFP 1  of the replica circuit RP 1  becomes equal to the reference voltage VRP, the resistance characteristic determined by (VDD−VRP)/ICA is obtained by the gate voltage VP 1 . ICA denotes the current value of the constant current source CA. Since the output voltages VFP 2  and VFP 3  of the replica circuits RP 2  and RP 3  are also controlled to be equal to the reference voltage VRP by the gate voltage VP 1 , the gate voltages VP 2  and VP 3  become the highest voltage (power supply voltage VDD) and function to turn off the P-channel MOS transistors P 2  and P 3 . 
         [0050]    On the other hand, when the output voltage VFP 1  of the replica circuit RP 1  does not become equal to the reference voltage VRP, the gate voltage VP 1  becomes the lowest voltage (ground voltage VSS), and the drain current of the P-channel MOS transistor P 1  is maximized. Further, if the output voltage VFP 2  of the replica circuit RP 2  does not become equal to the reference voltage VRP, the gate voltage VP 2  becomes the lowest voltage, and the drain current of the P-channel MOS transistor P 2  is also maximized. In this state, for example, if the output voltage VFP 3  of the replica circuit RP 3  does not become equal to the reference voltage VRP, the resistance characteristic determined by (VDD−VRP)/ICA is obtained by the gate voltage VP 3 . 
         [0051]    Since the gate voltages VP 1  to VP 3  also control the P-channel MOS transistors VP 1  to VP 3  of the output buffer DOB, an output impedance Zp at the time when the output buffer DOB outputs the “H” level is adjusted to have the resistance characteristic determined by (VDD−VRP)/ICA. 
         [0052]    Concretely, as illustrated in the upper row in  FIG. 2 , when the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, all of the output voltages VFP 1  to VFP 3  of the replica circuits RP 1  to RP 3  become equal to the reference voltage VRP. 
         [0053]    The gate voltage VP 1  becomes intermediate voltage, and both of the gate voltages VP 2  and VP 3  become the highest voltage. As a result, the drain current of the P-channel MOS transistor P 1  is adjusted to a proper value, the P-channel MOS transistors P 2  and P 3  are turned off, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0054]    As illustrated in the intermediate row in  FIG. 2 , when the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance elements RA 3  and RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, the output voltage VFP 1  of the replica circuit RP 1  becomes lower than the reference voltage VRP, and both of the output voltages VFP 2  and VFP 3  of the replica circuits RP 2  and RP 3  become equal to the reference voltage VRP. 
         [0055]    The gate voltage VP 1  becomes the lowest voltage, the gate voltage VP 2  becomes the intermediate voltage, and the gate voltage VP 3  becomes the highest voltage. As a result, the P-channel MOS transistor P 1  is turned on, the drain current of the P-channel MOS transistor P 2  is adjusted to a proper value, the P-channel MOS transistor P 3  is turned off, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0056]    As illustrated in the lower row in  FIG. 2 , when the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance element RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, both of the output voltages VFP 1  and VFP 2  of the replica circuits RP 1  and RP 2  become lower than the reference voltage VRP, and the output voltage VFP 3  of the replica circuit RP 3  becomes equal to the reference voltage VRP. 
         [0057]    Both of the gate voltages VP 1  and VP 2  become the lowest voltage, and the gate voltage VP 3  becomes the intermediate voltage. As a result, the P-channel MOS transistors P 1  and P 2  are turned on, the drain current of the P-channel MOS transistor P 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0058]    Similarly, the operational amplifiers AN 1  to AN 3  control the gate voltages VN 1  to VN 3  of the N-channel MOS transistors Q 1  to Q 3  so that the output voltages VFN 1  to VFN 3  of the replica circuits RP 1  to RP 3  become equal to the reference voltage VRN in accordance with the combined resistance value of the resistance elements RB 1  to RB 3  and the N-channel MOS transistor Q 4 . 
         [0059]    If the output voltage VFN 1  of the replica circuit RP 1  becomes equal to the reference voltage VRN, the resistance characteristic determined by (VRN−VSS)/ICB is obtained by the gate voltage VN 1 . ICB denotes the current value of the constant current source CB. Since the output voltages VFN 2  and VFN 3  of the replica circuits RP 2  and RP 3  are also controlled to be equal to the reference voltage VRN by the gate voltage VN 1 , the gate voltages VN 2  and VN 3  become the lowest voltage and function to turn off the N-channel MOS transistors Q 2  and Q 3 . 
         [0060]    On the other hand, when the output voltage VFN 1  of the replica circuit RP 1  does not become equal to the reference voltage VR, the gate voltage VN 1  becomes the highest voltage, and the drain current of the N-channel MOS transistor Q 1  is maximized. Further, if the output voltage VFN 2  of the replica circuit RP 2  does not become equal to the reference voltage VRN, the gate voltage VN 2  becomes the highest voltage, and the drain current of the N-channel MOS transistor Q 2  becomes also the highest. In this state, for example, if the output voltage VFN 3  of the replica circuit RP 3  becomes equal to the reference voltage VRN, the resistance characteristic determined by (VRN−VSS)/ICB is obtained by the gate voltage VN 3 . 
         [0061]    Since the gate voltages VN 1  to VN 3  also control the N-channel MOS transistors Q 1  to Q 3  of the output buffer DOB, an output impedance Zn at the time when the output buffer DOB outputs the “L” level is adjusted to have the resistance characteristic determined by (VRN−VSS)/ICB. 
         [0062]    Concretely, as illustrated in the upper row in  FIG. 3 , when the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, all of the output voltages VFN 1  to VFN 3  of the replica circuits RP 1  to RP 3  become equal to the reference voltage VRN. 
         [0063]    The gate voltage VN 1  becomes intermediate voltage, and both of the gate voltages VN 2  and VN 3  become the lowest voltage. As a result, the drain current of the N-channel MOS transistor Q 1  is adjusted to a proper value, the N-channel MOS transistors Q 2  and Q 3  are turned off, and the combined resistance value of the resistance elements RB 1  to RB 3  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. The resistance value of the resistance element RB 4  and that of the resistance element RA 4  are equal to each other. 
         [0064]    As illustrated in the intermediate row in  FIG. 3 , when the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the output voltage VFN 1  of the replica circuit RP 1  becomes higher than the reference voltage VRN, and both of the output voltages VFN 2  and VFN 3  of the replica circuits RP 2  and RP 3  become equal to the reference voltage VRN. 
         [0065]    The gate voltage VN 1  becomes the highest voltage, the gate voltage VN 2  becomes the intermediate voltage, and the gate voltage VN 3  becomes the lowest voltage. As a result, the N-channel MOS transistor Q 1  is turned on, the drain current of the N-channel MOS transistor Q 2  is adjusted to a proper value, the N-channel MOS transistor Q 3  is turned off, and the combined resistance value of the resistance elements RB 1  to RB 3  and RA 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0066]    As illustrated in the lower row in  FIG. 3 , when the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance element RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, both of the output voltages VFN 1  and VFN 2  of the replica circuits RP 1  and RP 2  become higher than the reference voltage VRN, and the output voltage VFN 3  of the replica circuit RP 3  becomes equal to the reference voltage VRN. 
         [0067]    Both of the gate voltages VN 1  and VN 2  become the highest voltage, and the gate voltage VN 3  becomes the intermediate voltage. As a result, the N-channel MOS transistors Q 1  and Q 2  are turned on, the drain current of the N-channel MOS transistor Q 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RB 1  to RB 3  and RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0068]    In the case where an internal data signal φD is at the “H” level, the P-channel MOS transistor P 4  is turned off, the N-channel MOS transistor Q 4  is turned on, the output terminal TO becomes the “L” level, and the data signal DO becomes the “L” level. 
         [0069]    In the case where the internal data signal φD is at the “L” level, the N-channel MOS transistor Q 4  is turned off, the P-channel MOS transistor P 4  is turned on, the output terminal TO becomes the “H” level, and the data signal DO becomes the “H” level. 
         [0070]      FIG. 4  is a diagram illustrating a result of simulation of changes in the gate voltages VP 1  to VP 3  and VN 1  to VN 3  accompanying temperature changes of the semiconductor device. In  FIG. 4 , the gate voltage VP 1  is set to the lowest voltage, the gate voltage VN 1  is set to the highest voltage, both of the transistors P 1  and Q 1  are turned on, the gate voltage VP 3  is set to the highest voltage, the gate voltage VN 3  is set to the lowest voltage, both of the transistors P 3  and Q 3  are turned on, each of the gate voltages VP 2  and VN 2  is set to the intermediate voltage, and the drain current of each of the transistors P 2  and Q 2  is adjusted. As the temperature rises, the gate voltage VP 2  decreases and the gate voltage VN 2  increases so that the output impedances Zp and Zn become constant. 
         [0071]      FIG. 5  is a diagram illustrating a result of another simulation of changes in the gate voltages VP 1  to VP 3  and VN 1  to VN 3  accompanying temperature changes of the semiconductor device. In  FIG. 5 , in a low-temperature region, the gate voltages VP 2  and VP 3  are set to the highest voltage, both of the transistors P 1  and P 3  are turned off, both of the gate voltages VN 2  and VN 3  are set to the lowest voltage, both of the transistors Q 2  and Q 3  are turned off, each of the gate voltages VP 1  and VN 1  is set to the intermediate voltage, and the drain current of each of the transistors P 1  and Q 1  is adjusted. In the low-temperature region, as the temperature rises, the gate voltage VP 1  decreases and the gate voltage VN 1  increases so that the output impedances Zp and Zn become constant. 
         [0072]    In a high-temperature region, the gate voltage VP 1  is set to the lowest voltage, the gate voltage VN 1  is set to the highest voltage, both of the transistors P 1  and Q 1  are turned on, the gate voltage VP 3  is set to the highest voltage, the gate voltage VN 3  is set to the lowest voltage, both of the transistors P 3  and Q 3  are turned off, each of the gate voltages VP 2  and VN 2  is set to the intermediate voltage, and the drain current of each of the transistors P 2  and Q 2  is adjusted. In the high-temperature region, as the temperature rises, the gate voltage VP 2  decreases and the gate voltage VN 2  increases so that the output impedances Zp and Zn become constant. 
         [0073]      FIG. 6  is a circuit diagram showing a configuration of a semiconductor device as a comparative example of the first embodiment and is compared to  FIG. 1 . In  FIG. 6 , the semiconductor device is different from the semiconductor device of  FIG. 1  with respect to the points that the operational amplifiers AP 2 , AP 3 , AN 2 , and AN 3  in the control voltage generation circuit VCG are not provided, the transistors P 2 , P 3 , Q 2 , and Q 3  and the resistance elements RA 2 , RA 3 , RB 2 , and RB 3  in the replica circuit RP 1  are not provided, the replica circuits RP 2  and RP 3  are not provided, and the transistors P 2 , P 3 , Q 2 , and Q 3  and the resistance elements RA 2 , RA 3 , RB 2 , and RB 3  in the output buffer DOB are not provided. 
         [0074]    In the comparative example, in the case where the resistance value of the resistance element RA 1  changes beyond a range in which the resistance value can be adjusted by the drain current of the P-channel MOS transistor P 1 , the output impedance of the output buffer DOB cannot be adjusted to a predetermined value (for example, 40.5 to 49.0 ΩQ). In the case where the resistance value of the resistance element RB 1  changes beyond a range in which the resistance value can be adjusted by the drain current of the N-channel MOS transistor Q 1 , the output impedance Zn of the output buffer DOB cannot be adjusted to a predetermined value. 
         [0075]    On the other hand, in the first embodiment, the plurality of P-channel MOS transistors P 1  to P 3  are provided. Consequently, even in the case where the sum of the resistance values of the resistance elements RA 1  to RA 4  fluctuates beyond the range in which the resistance value can be adjusted by the drain current of one P-channel MOS transistor P, the output impedance Zp can be adjusted to a predetermined value. Since the plurality of N-channel MOS transistors Q 1  to Q 3  are provided, even in the case where the sum of the resistance values of the resistance elements RB 1  to RB 4  (RB 1  to RB 3  and RA 4 ) fluctuates beyond the range in which the resistance value can be adjusted by the drain current of one N-channel MOS transistor Q, the output impedance Zn can be adjusted to a predetermined value. 
         [0076]    In the first embodiment, three sets of transistors P(Q) and the resistance elements RA (RB) are provided and three sets of replica circuits RP and three sets of operational amplifiers AP (AN) are provided. However, the invention is not limited to the embodiment. Obviously, four sets or more (or two sets) of transistors P (Q) and resistance elements RA (RB) may be provided, and four sets or more (or two sets) of replica circuits RP and four sets or more (or two sets) of operational amplifiers AP (AN) may be provided. 
       Second Embodiment 
       [0077]    A semiconductor device according to a second embodiment of the present invention has, as shown in  FIG. 7 , a control voltage generation circuit VCG  10 , replica circuits RP 11  to RP 13 , an output buffer DOB  10 , and an output terminal TO. The output buffer DOB  10  is configured as a high-speed driver circuit of a USB and includes resistance elements RB 1  to RB 4 , N-channel MOS transistors Q 1  to Q 5 , a constant current source CB, and a driver DR. 
         [0078]    The constant current source CB and the N-channel MOS transistor Q 5  are coupled in series between the line of the power supply voltage VDD and the output terminal TO. The gate of the N-channel MOS transistor Q 5  receives the internal data signal φD. The resistance elements RB 1  to RB 3 , the N-channel MOS transistor Q 4 , and the resistance element RB 4  are coupled in series between the line of the ground voltage VSS and the output terminal TO. The sources of the N-channel MOS transistors Q 1  to Q 3  receive the ground voltage VSS, and the drains are coupled to electrodes on the higher voltage side (the output terminal TO side) of the resistance elements RB 1  to RB 3 . The driver DB supplies a signal of the “H” level to the gate of the transistor Q 4  to turn on the transistor Q 4 . 
         [0079]    The control voltage generation circuit VCG 10  is obtained by eliminating the operational amplifiers AP 1  to AP 3  in the control voltage generation circuit VCG in  FIG. 1 . The replica circuits RP 11  to RP 13  are obtained by eliminating the resistance elements RA 1  to RA 4 , the P-channel MOS transistors P 1  to P 4 , and the constant current source CA in the replica circuits RP 1  to RP 3  in  FIG. 1 . 
         [0080]    Next, the operation of the semiconductor device will be described. The operational amplifiers AN 1  to AN 3  control the gate voltages VN 1  to VN 3  of the N-channel MOS transistors Q 1  to Q 3  so that the output voltages VFN 1  to VFN 3  of the replica circuits RP 11  to RP 13  become equal to the reference voltage VRN in accordance with the value of combined resistance of the resistance elements RB 1  to RB 3  and the N-channel MOS transistor Q 4 . 
         [0081]    If the output voltage VFN 1  of the replica circuit RP 11  becomes equal to the reference voltage VRP, the resistance characteristic determined by (VRN−VSS)/ICB is obtained by the gate voltage VN 1 . ICB denotes the current value of the constant current source CB. Since the output voltages VFN 2  and VFN 3  of the replica circuits RP 12  and RP 13  are also controlled to be equal to the reference voltage VRN by the gate voltage VN 1 , the gate voltages VN 2  and VN 3  become the lowest voltage and function to turn off the N-channel MOS transistors Q 2  and Q 3 . 
         [0082]    On the other hand, if the output voltage VFN 1  of the replica circuit RP 11  does not become equal to the reference voltage VRN, the gate voltage VN 1  becomes the highest voltage, and the drain current of the N-channel MOS transistor Q 1  is set to the highest voltage. Further, if the output voltage VFN 2  of the replica circuit RP 12  does not become equal to the reference voltage VRN, the gate voltage VN 2  becomes the highest voltage, and the drain current of the N-channel MOS transistor Q 2  also becomes the largest. In this state, for example, if the output voltage VFN 3  of the replica circuit RP 13  does not become equal to the reference voltage VRN, the resistance characteristic determined by (VRN−VSS)/ICB is obtained by the gate voltage VN 3 . 
         [0083]    Since the gate voltages VN 1  to VN 3  also control the N-channel MOS transistors Q 1  to Q 3  of the output buffer DOB  10 , the output impedance Zn at the time when the output buffer DOB outputs the “L” level is adjusted to have the resistance characteristic determined by (VRN−VSS)/ICB. 
         [0084]    In the case where the internal data signal φD is at the “H” level, the N-channel MOS transistor P 5  is turned on, the output terminal TO becomes the “H” level, and the data signal DO becomes the “H” level. In the case where the internal data signal φD is at the “L” level, the N-channel MOS transistor Q 5  is turned off, the output terminal TO becomes the “L” level, and the data signal DO becomes the “L” level. 
         [0085]    Concretely, as illustrated in the upper row in  FIG. 8 , when the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, all of the output voltages VFN 1  to VFN 3  of the replica circuits RP 11  to RP 13  become equal to the reference voltage VRN. 
         [0086]    The gate voltage VN 1  becomes intermediate voltage, and both of the gate voltages VN 2  and VN 3  become the lowest voltage. As a result, the drain current of the N-channel MOS transistor Q 1  is adjusted to a proper value, the N-channel MOS transistors Q 2  and Q 3  are turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB 10  is adjusted to a predetermined value. 
         [0087]    As illustrated in the intermediate row in  FIG. 8 , when the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the output voltage VFN 1  of the replica circuit RP 11  becomes higher than the reference voltage VRN, and both of the output voltages VFN 2  and VFN 3  of the replica circuits RP 12  and RP 13  become equal to the reference voltage VRN. 
         [0088]    The gate voltage VN 1  becomes the highest voltage, the gate voltage VN 2  becomes the intermediate voltage, and the gate voltage VN 3  becomes the lowest voltage. As a result, the N-channel MOS transistor Q 1  is turned on, the drain current of the N-channel MOS transistor Q 2  is adjusted to a proper value, the N-channel MOS transistor Q 3  is turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB 10  is adjusted to a predetermined value. 
         [0089]    As illustrated in the lower row in  FIG. 8 , when the combined resistance value of the resistance elements RB 2  and RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance element RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, both of the output voltages VFN 1  and VFN 2  of the replica circuits RP 11  and RP 12  become higher than the reference voltage VRN, and the output voltage VFN 3  of the replica circuit RP 13  becomes equal to the reference voltage VRN. 
         [0090]    Both of the gate voltages VN 1  and VN 2  become the highest voltage, and the gate voltage VN 3  becomes the intermediate voltage. As a result, the N-channel MOS transistors Q 1  and Q 2  are turned on, the drain current of the N-channel MOS transistor Q 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB 10  is adjusted to a predetermined value. 
         [0091]      FIG. 9  is a circuit diagram illustrating a configuration of a semiconductor device as a comparative example of the second embodiment and is a diagram which is compared to  FIG. 7 . The semiconductor device of  FIG. 9  is different from that of  FIG. 7  with respect to the points that the operational amplifiers AN 2  and AN 3  in the control voltage generation circuit VCG 10  are not provided, the transistors Q 2  and Q 3  and the resistance elements RB 2  and RB 3  in the replica circuit RP 11  are not provided, the replica circuits RP 12  and RP 13  are not provided, and the transistors Q 2  and Q 3  and the resistive elements RB 2  and RB 3  in the output buffer DOB 10  are not provided. 
         [0092]    In the comparative example, in the case where the resistance value of the resistance element RB 1  changes beyond a range in which the resistance value can be adjusted by the drain current of the N-channel MOS transistor Q 1 , the output impedance Zn of the output buffer DOB cannot be adjusted to a predetermined value. 
         [0093]    On the other hand, in the second embodiment, the plurality of N-channel MOS transistors Q 1  to Q 3  are provided. Consequently, even in the case where the sum of the resistance values of the resistance elements RB 1  to RB 4  (RB 1  to RB 3 , RA 4 ) fluctuates beyond the range in which the resistance value can be adjusted by the drain current of one N-channel MOS transistor Q, the output impedance Zn can be adjusted to a predetermined value. 
         [0094]    In the second embodiment, three sets of transistors Q and the resistance elements RB are provided and three sets of replica circuits RP and three sets of operational amplifiers AN are provided. However, the invention is not limited to the embodiment. Obviously, four sets or more (or two sets) of transistors Q and resistance elements RB may be provided, and four sets or more (or two sets) of replica circuits RP and four sets or more (or two sets) of operational amplifiers AN may be provided. 
       Third Embodiment 
       [0095]      FIG. 10  is a circuit diagram showing a main part of a semiconductor device according to a third embodiment of the invention and is compared to  FIG. 1 . The semiconductor device of  FIG. 10  is different from the semiconductor device of  FIG. 1  with respect to the points that an N-channel MOS transistor QS and a P-channel MOS transistor PS are added to the replica circuit RP 1 , and inverters IP and IN, an N-channel MOS transistor QS, and a P-channel MOS transistor PS are added to each of the replica circuits RP 2  and RP 3 . 
         [0096]    The drain of the N-channel MOS transistor QS is coupled to an electrode on the low voltage side (the ground voltage VSS side) of the resistance element RA 4 , and the source is coupled to the line of the ground voltage VSS via the constant current source CA. The source of the P-channel MOS transistor PS is coupled to the line of the power supply voltage VDD via the constant current source CB, and the drain is coupled to the electrode on the high voltage side (the power supply voltage VDD side) of the resistance element RB 4 . 
         [0097]    In the replica circuit RP 1 , the power supply voltage VSS is applied to the gate of the transistor QS, the ground voltage VSS is applied to the gate of the transistor PS, and both of the transistors QS and PS are fixed in the on state. 
         [0098]    In the replica circuit RP 2 , the input node of the inverter IP receives the gate voltage VP 1 , and an output signal of the inverter IP is supplied to the gate of the N-channel MOS transistor QS. In the case where the gate voltage VP 1  is lower than a threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “H” level, and the N-channel MOS transistor QS is turned on. In the case where the gate voltage VP 1  is higher than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “L” level, and the N-channel MOS transistor QS is turned off. 
         [0099]    The input node of the inverter IN receives the gate voltage VN 1 , and an output signal of the inverter IN is supplied to the gate of the P-channel MOS transistor PS. In the case where the gate voltage VN 1  is lower than a threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “H” level, and the P-channel MOS transistor PS is turned off. In the case where the gate voltage VN 1  is higher than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. 
         [0100]    In the replica circuit RP 3 , the input node of the inverter IP receives the gate voltage VP 2 , and an output signal of the inverter IP is supplied to the gate of the N-channel MOS transistor QS. In the case where the gate voltage VP 2  is lower than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “H” level, and the N-channel MOS transistor QS is turned on. In the case where the gate voltage VP 2  is higher than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “L” level, and the N-channel MOS transistor QS is turned off. 
         [0101]    The input node of the inverter IN receives the gate voltage VN 2 , and an output signal of the inverter IN is supplied to the gate of the P-channel MOS transistor PS. In the case where the gate voltage VN 2  is lower than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “H” level, and the P-channel MOS transistor PS is turned off. In the case where the gate voltage VN 2  is higher than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. 
         [0102]    Next, the operation of the semiconductor device will be described. In the case where the output voltage VFP 1  of the replica circuit RP 1  becomes equal to the reference voltage VRP, the inverter IP of the replica circuit RP 2  detects that the gate voltage VP 1  is not the lowest voltage, and the N-channel MOS transistor QS of the replica circuit RP 2  is turned off to interrupt the current of the constant current source CA. 
         [0103]    When the current of the constant current source CA is interrupted, the output voltage VFP 2  of the replica circuit RP 2  becomes the power supply voltage VDD, and the gate voltage VP 2  becomes the highest voltage. As a result, the inverter IP of the replica circuit RP 3  turns off the N-channel MOS transistor QS to interrupt the current of the constant current source CA. When the current of the constant current source CA is interrupted, the output voltage VFP 3  of the replica circuit RP 3  becomes the power supply voltage VDD, and the gate voltage VP 3  becomes the highest voltage. 
         [0104]    Concretely, as illustrated in the upper row in  FIG. 11 , when the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, the output voltage VFP 1  of the replica circuit RP 1  becomes equal to the reference voltage VRP. The gate voltage VP 1  becomes the intermediate voltage, and both of the gate voltages VP 2  and VP 3  become the highest voltage. 
         [0105]    As a result, in each of the replica circuits RP 2  and RP 3 , the output signal of the inverter IP becomes the “L” level, the N-channel MOS transistor QS is turned off, and the output voltages VFP 2  and VFP 3  of the replica circuits RP 2  and RP 3  become the power supply voltage VDD. 
         [0106]    The drain current of the P-channel MOS transistor P 1  is adjusted to a proper value, the P-channel MOS transistors P 2  and P 3  are turned off, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0107]    As illustrated in the intermediate row in  FIG. 11 , when the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance elements RA 3  and RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, the output voltage VFP 1  of the replica circuit RP 1  becomes lower than the reference voltage VRP, and the output voltage VFP 2  of the replica circuit RP 2  becomes equal to the reference voltage VRP. The gate voltage VP 1  becomes the lowest voltage, the gate voltage VP 2  becomes the intermediate voltage, and the gate voltage VP 3  becomes the highest voltage. 
         [0108]    As a result, in the replica circuit RP 2 , an output signal of the inverter IP becomes the “H” level, and the N-channel MOS transistor QS is turned on. In the replica circuit RP 3 , an output signal of the inverter IP becomes the “L” level, the N-channel MOS transistor QS is turned off, and the output voltage VFP 3  of the replica circuit RP 3  becomes the power supply voltage VDD. 
         [0109]    The P-channel MOS transistor P 1  is turned on, the drain current of the P-channel MOS transistor P 2  is adjusted to a proper value, the P-channel MOS transistor P 3  is turned off, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0110]    As illustrated in the lower row in  FIG. 11 , when the combined resistance value of the resistance elements RA 3  and RA 4  and the P-channel MOS transistor P 4  is lower than a predetermined value and the combined resistance value of the resistance element RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, both of the output voltages VFP 1  and VFP 2  of the replica circuits RP 1  and RP 2  become lower than the reference voltage VRP, and the output voltage VFP 3  of the replica circuit RP 3  becomes equal to the reference voltage VRP. 
         [0111]    Both of the gate voltages VP 1  and VP 2  become the lowest voltage, and the gate voltage VP 3  becomes the intermediate voltage. As a result, in each of the replica circuits RP 2  and RP 3 , an output signal of the inverter IP becomes the “H” level, and the N-channel MOS transistor QS is turned on. 
         [0112]    The P-channel MOS transistors P 1  and P 2  are turned on, the drain current of the P-channel MOS transistor P 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  in the output buffer DOB is adjusted to a predetermined value. 
         [0113]    Similarly, in the case where the output voltage VFN 1  of the replica circuit RP 1  becomes equal to the reference voltage VRN, the inverter IN of the replica circuit RP 2  detects that the gate voltage VN 1  is not the highest voltage, and the P-channel MOS transistor PS of the replica circuit RP 2  is turned off to interrupt the current of the constant current source CB. 
         [0114]    When the current of the constant current source CB is interrupted, the output voltage VFN 2  of the replica circuit RP 2  becomes the ground voltage VSS, and the gate voltage VN 2  becomes the lowest voltage. As a result, the inverter IN of the replica circuit RP 3  turns off the P-channel MOS transistor PS to interrupt the current of the constant current source CB. When the current of the constant current source CB is interrupted, the output voltage VFN 3  of the replica circuit RP 3  becomes the ground voltage VSS, and the gate voltage VN 3  becomes the lowest voltage. 
         [0115]    Concretely, as illustrated in the upper row in  FIG. 12 , when the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the output voltage VFN 1  of the replica circuit RP 1  becomes equal to the reference voltage VRN. The gate voltage VN 1  becomes the intermediate voltage, and both of the gate voltages VN 2  and VN 3  become the lowest voltage. 
         [0116]    As a result, in each of the replica circuits RP 2  and RP 3 , the output signal of the inverter IN becomes the “H” level, the P-channel MOS transistor PS is turned off, and the output voltages VFN 2  and VFN 3  of the replica circuits RP 2  and RP 3  become the ground voltage VSS. 
         [0117]    The drain current of the N-channel MOS transistor Q 1  is adjusted to a proper value, the N-channel MOS transistors Q 2  and Q 3  are turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0118]    As illustrated in the intermediate row in  FIG. 12 , when the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the output voltage VFN 1  of the replica circuit RP 1  becomes higher than the reference voltage VRN, and the output voltage VFN 2  of the replica circuit RP 2  becomes equal to the reference voltage VRN. The gate voltage VN 1  becomes the highest voltage, the gate voltage VN 2  becomes the intermediate voltage, and the gate voltage VN 3  becomes the lowest voltage. 
         [0119]    In the replica circuit RP 2 , an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. In the replica circuit RP 3 , an output signal of the inverter IN becomes the “H” level, the P-channel MOS transistor PS is turned off, and the output voltage VFN 3  of the replica circuit RP 3  becomes the ground voltage VSS. 
         [0120]    The N-channel MOS transistor Q 1  is turned on, the drain current of the N-channel MOS transistor Q 2  is adjusted to a proper value, the N-channel MOS transistor Q 3  is turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0121]    As illustrated in the lower row in  FIG. 12 , when the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance element RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, both of the output voltages VFN 1  and VFN 2  of the replica circuits RP 1  and RP 2  become higher than the reference voltage VRP, and the output voltage VFN 3  of the replica circuit RP 3  becomes equal to the reference voltage VRP. 
         [0122]    Both of the gate voltages VN 1  and VN 2  become the highest voltage, and the gate voltage VN 3  becomes the intermediate voltage. As a result, in each of the replica circuits RP 2  and RP 3 , an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. 
         [0123]    The N-channel MOS transistors Q 1  and Q 2  are turned on, the drain current of the N-channel MOS transistor Q 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0124]      FIG. 13  is a diagram illustrating a result of simulation of changes in the gate voltages VP 1  to VP 3  and VN 1  to VN 3  accompanying temperature changes of the semiconductor device. In  FIG. 13 , in a low-temperature region, both of the gate voltages VP 2  and VP 3  are set to the power supply voltage VDD, both of the transistors P 2  and P 3  are turned off, both of the gate voltages VN 2  and VN 3  are set to the ground voltage VSS, both of the transistors Q 2  and Q 3  are turned off, each of the gate voltages VP 1  and VN 1  is set to the intermediate voltage, and the drain current of each of the transistors P 1  and Q 1  is adjusted. In the low-temperature region, as the temperature rises, the gate voltage VP 1  decreases and the gate voltage VN 1  increases so that the output impedances Zp and Zn become constant. 
         [0125]    When the temperature further rises and the gate voltage VN 1  becomes higher than the threshold voltage VTHN of the inverter IN, the P-channel MOS transistor PS of the replica circuit RP 2  is turned on, and the gate voltage VN 2  is increased from the ground voltage VSS to the intermediate voltage. 
         [0126]    When the temperature further rises and the gate voltage VP 1  becomes lower than the threshold voltage VTHP of the inverter IP, the N-channel MOS transistor QS of the replica circuit RP 2  is turned on, and the gate voltage VP 2  is decreased from the power supply voltage VDD to the intermediate voltage. 
         [0127]    In a high-temperature region, the gate voltage VP 1  is set to the lowest voltage, the gate voltage VN 1  is set to the highest voltage, both of the transistors P 1  and Q 1  are turned on, the gate voltage VP 3  is set to the power supply voltage VDD, the gate voltage VN 3  is set to the ground voltage VSS, both of the transistors P 3  and Q 3  are turned off, each of the gate voltages VP 2  and VN 2  is set to the intermediate voltage, and the drain current of each of the transistors P 2  and Q 2  is adjusted. In the high-temperature region, as the temperature rises, the gate voltage VP 2  decreases and the gate voltage VN 2  increases so that the output impedances Zp and Zn become constant. 
         [0128]    In the third embodiment, the effect similar to that of the first embodiment is obtained. In addition, since through current of the replica circuit RP which does not exert an influence on the adjustment of the output impedances Zp and Zn can be interrupted, power consumption is smaller than that of the first embodiment. 
       Fourth Embodiment 
       [0129]      FIG. 14  is a circuit diagram showing a main part of a semiconductor device according to a fourth embodiment of the invention and is compared to  FIG. 7 . The semiconductor device of  FIG. 14  is different from the semiconductor device of  FIG. 7  with respect to the points that a P-channel MOS transistor PS is added to the replica circuit RP 11 , and the inverter IN and the P-channel MOS transistor PS are added to each of the replica circuits RP 12  and RP 13 . 
         [0130]    The source of the P-channel MOS transistor PS is coupled to the line of the power supply voltage VDD via the constant current source CB. The drain of the P-channel MOS transistor PS is coupled to the electrode on the high voltage side (the power supply voltage VDD side) of the resistance element RB 4 . In the replica circuit RP 11 , the power supply voltage VSS is applied to the gate of the transistor PS, and the transistor PS is fixed in the on state. 
         [0131]    In the replica circuit RP 12 , the input node of the inverter IN receives the gate voltage VN 1 , and an output signal of the inverter IN is supplied to the gate of the P-channel MOS transistor PS. In the case where the gate voltage VN 1  is lower than a threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “H” level, and the P-channel MOS transistor PS is turned off. In the case where the gate voltage VN 1  is higher than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. 
         [0132]    In the replica circuit RP 13 , the input node of the inverter IN receives the gate voltage VN 2 , and an output signal of the inverter IN is supplied to the gate of the P-channel MOS transistor PS. In the case where the gate voltage VN 2  is lower than a threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “H” level, and the P-channel MOS transistor PS is turned off. In the case where the gate voltage VN 2  is higher than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. 
         [0133]    Next, the operation of the semiconductor device will be described. In the case where the output voltage VFN 1  of the replica circuit RP 11  becomes equal to the reference voltage VRN, the inverter IN of the replica circuit RP 12  detects that the gate voltage VN 1  is not the highest voltage, and the P-channel MOS transistor PS of the replica circuit RP 12  is turned off to interrupt the current of the constant current source CB. 
         [0134]    When the current of the constant current source CB is interrupted, the output voltage VFN 2  of the replica circuit RP 12  becomes the ground voltage VSS, and the gate voltage VN 2  becomes the lowest voltage. As a result, the inverter IN of the replica circuit RP 13  turns off the P-channel MOS transistor PS to interrupt the current of the constant current source CB. When the current of the constant current source CB is interrupted, the output voltage VFN 3  of the replica circuit RP 13  becomes the ground voltage VSS, and the gate voltage VN 3  becomes the lowest voltage. 
         [0135]    Concretely, as illustrated in the upper row in  FIG. 15 , when the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the output voltage VFN 1  of the replica circuit RP 11  becomes equal to the reference voltage VRN. The gate voltage VN 1  becomes the intermediate voltage, and both of the gate voltages VN 2  and VN 3  become the lowest voltage. 
         [0136]    As a result, in each of the replica circuits RP 12  and RP 13 , the output signal of the inverter IN becomes the “H” level, the P-channel MOS transistor PS is turned off, and the output voltages VFN 2  and VFN 3  of the replica circuits RP 2  and RP 3  become the ground voltage VSS. 
         [0137]    The drain current of the N-channel MOS transistor Q 1  is adjusted to a proper value, the N-channel MOS transistors Q 2  and Q 3  are turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0138]    As illustrated in the intermediate row in  FIG. 15 , when the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the output voltage VFN 1  of the replica circuit RP 11  becomes higher than the reference voltage VRN, and the output voltage VFN 2  of the replica circuit RP 12  becomes equal to the reference voltage VRN. The gate voltage VN 1  becomes the highest voltage, the gate voltage VN 2  becomes the intermediate voltage, and the gate voltage VN 3  becomes the lowest voltage. 
         [0139]    As a result, in the replica circuit RP 12 , an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. In the replica circuit RP 13 , an output signal of the inverter IN becomes the “H” level, the P-channel MOS transistor PS is turned off, and the output voltage VFN 3  of the replica circuit RP 13  becomes the ground voltage VSS. 
         [0140]    The N-channel MOS transistor Q 1  is turned on, the drain current of the N-channel MOS transistor Q 2  is adjusted to a proper value, the N-channel MOS transistor Q 3  is turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0141]    As illustrated in the lower row in  FIG. 15 , when the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance element RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, both of the output voltages VFN 1  and VFN 2  of the replica circuits RP 11  and RP 12  become higher than the reference voltage VRN, and the output voltage VFN 3  of the replica circuit RP 13  becomes equal to the reference voltage VRN. 
         [0142]    Both of the gate voltages VN 1  and VN 2  become the highest voltage, and the gate voltage VN 3  becomes the intermediate voltage. As a result, in each of the replica circuits RP 12  and RP 13 , an output signal of the inverter IN becomes the “L” level, and the P-channel MOS transistor PS is turned on. 
         [0143]    The N-channel MOS transistors Q 1  and Q 2  are turned on, the drain current of the N-channel MOS transistor Q 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RB 1  to RB 4  and the P-channel MOS transistors Q 1  to Q 4  in the output buffer DOB is adjusted to a predetermined value. 
         [0144]    In the fourth embodiment, the effect similar to that of the second embodiment is obtained. In addition, since through current of the replica circuit RP which does not exert an influence on the adjustment of the output impedances Zp and Zn can be interrupted, power consumption is smaller than that of the second embodiment. 
       Fifth Embodiment 
       [0145]      FIG. 16  is a circuit diagram showing a main part of a semiconductor device according to a fifth embodiment of the invention and is compared to  FIG. 1 . The semiconductor device of  FIG. 16  is different from the semiconductor device of  FIG. 1  with respect to the points that the N-channel MOS transistors QS 1  to QS 3  and the P-channel MOS transistors PS 1  to PS 3  are added to the control voltage generation circuit VCG, and the inverters IP 1 , IP 2 , IN 1 , and IN 2  are added to each of the replica circuits RP 2  and RP 3 . 
         [0146]    The drains of the N-channel MOS transistors QS 1  to QS 3  are coupled to the negative-side power supply nodes of the operational amplifiers AP 1  to AP 3 , and the sources receive the ground voltage VSS. The gate of the N-channel MOS transistor QS 1  receives the power supply voltage VDD and is fixed in the on state. The sources of the P-channel MOS transistors PS 1  to PS 3  receive the power supply voltage VDD, and the drains are coupled to the power supply nodes on the positive side of the operational amplifiers AN 1  to AN 3 . The P-channel MOS transistor PS 1  receives the ground voltage VSS by its gate and is fixed in the on state. 
         [0147]    In the replica circuit RP 12 , the input node of the inverter IP 1  receives the gate voltage VP 1 , and an output signal of the inverter IP 1  is supplied to the gate of the P-channel MOS transistor P 4  via the inverter IP 2 . An output signal of the inverter IP 1  is supplied to the gate of the N-channel MOS transistor QS 2 . 
         [0148]    In the case where the gate voltage VP 1  is lower than the threshold voltage VTHP of the inverter IP 1 , an output signal of the inverter IP 1  becomes the “H” level, an output signal of the inverter IP 2  becomes the “L” level, and both of the transistors QS 2  and P 4  are turned on. In the case where the gate voltage VP 1  is higher than the threshold voltage VTHP of the inverter IP 1 , an output signal of the inverter IP 1  becomes the “L” level, and an output signal of the inverter IP 2  becomes the “H” level, and both of the transistors QS 2  and P 4  are turned off. 
         [0149]    In the replica circuit RP 2 , the input node of the inverter IN 1  receives the gate voltage VN 1 , and an output signal of the inverter IN 1  is supplied to the gate of the N-channel MOS transistor Q 4  via the inverter IN 2 . An output signal of the inverter IN 1  is supplied to the gate of the P-channel MOS transistor PS 2 . 
         [0150]    In the case where the gate voltage VN 1  is lower than the threshold voltage VTHN of the inverter IN 1 , an output signal of the inverter IN 1  becomes the “H” level, an output signal of the inverter IN 2  becomes the “L” level, and both of the transistors PS 2  and Q 4  are turned off. In the case where the gate voltage VN 1  is higher than the threshold voltage VTHN of the inverter IN 1 , an output signal of the inverter IN 1  becomes the “L” level, an output signal of the inverter IN 2  becomes the “H” level, and both of the transistors PS 2  and Q 4  are turned on. 
         [0151]    In the replica circuit RP 3 , the input node of the inverter IP 1  receives the gate voltage VP 2 , and an output signal of the inverter IP 1  is supplied to the gate of the P-channel MOS transistor P 4  via the inverter IP 2 . An output signal of the inverter IP 1  is supplied to the gate of the N-channel MOS transistor QS 3 . 
         [0152]    In the case where the gate voltage VP 2  is lower than the threshold voltage VTHP of the inverter IP 1 , an output signal of the inverter IP 1  becomes the “H” level, an output signal of the inverter IP 2  becomes the “L” level, and both of the transistors QS 3  and P 4  are turned on. In the case where the gate voltage VP 2  is higher than the threshold voltage VTHP of the inverter IP 1 , an output signal of the inverter IP 1  becomes the “L” level, an output signal of the inverter IP 2  becomes the “H” level, and both of the transistors QS 3  and P 4  are turned off. 
         [0153]    In the replica circuit RP 3 , the input node of the inverter IN 1  receives the gate voltage VN 2 , and an output signal of the inverter IN 2  is supplied to the gate of the N-channel MOS transistor Q 4  via the inverter IN 2 . An output signal of the inverter IN 1  is supplied to the gate of the P-channel MOS transistor PS 3 . 
         [0154]    In the case where the gate voltage VN 2  is lower than the threshold voltage VTHN of the inverter IN 1 , an output signal of the inverter IN 1  becomes the “H” level, an output signal of the inverter IN 2  becomes the “L” level, and both of the transistors PS 3  and Q 4  are turned off. In the case where the gate voltage VN 2  is higher than the threshold voltage VTHN of the inverter IN 1 , an output signal of the inverter IN 1  becomes the “L” level, an output signal of the inverter IN 2  becomes the “H” level, and both of the transistors PS 3  and Q 4  are turned on. 
         [0155]    Next, the operation of the semiconductor device will be described. In the case where the output voltage VFP 1  of the replica circuit RP 1  becomes equal to the reference voltage VRP, the inverter IP 1  of the replica circuit RP 2  detects that the gate voltage VP 1  is not the lowest voltage, and turns off the transistors P 4  and QS 2 . As a result, the current of the constant current source CA is interrupted, application of the ground voltage VSS to the negative-side power supply node of the operational amplifier AP 2  is stopped, and the gate voltage VP 2  as the output voltage of the operational amplifier AP 2  becomes the highest voltage. When the gate voltage VP 2  becomes the highest voltage, the inverter IP 1  of the replica circuit RP 3  turns off the transistors P 4  and QS 3 . As a result, the current of the constant current source CA is interrupted, application of the ground voltage VSS to the negative-side power supply node of the operational amplifier AP 3  is stopped, and the gate voltage VP 3  as the output voltage of the operational amplifier AP 3  becomes the highest voltage. 
         [0156]    Similarly, in the case where the output voltage VFN 1  of the replica circuit RP 1  becomes equal to the reference voltage VRP, the inverter IN 1  of the replica circuit RP 2  detects that the gate voltage VN 1  is not the highest voltage, and turns off the transistors Q 4  and PS 2 . As a result, the current of the constant current source CB is interrupted, application of the power supply voltage VDD to the positive-side power supply node of the operational amplifier AN 2  is stopped, and the gate voltage VN 2  as the output voltage of the operational amplifier AN 2  becomes the lowest voltage. When the gate voltage VN 2  becomes the lowest voltage, the inverter IN 1  of the replica circuit RP 3  turns off the transistors Q 4  and PS 3 . As a result, the current of the constant current source CB is interrupted, application of the power supply voltage VDD to the positive-side power supply node of the operational amplifier AN 3  is stopped, and the gate voltage VN 3  as the output voltage of the operational amplifier AN 3  becomes the lowest voltage. The other operation is similar to that of the third embodiment, and its description will not be repeated. 
         [0157]    In the fifth embodiment, the effect similar to that of the first embodiment is obtained. In addition, since through current of the replica circuit RP and through current of the operational amplifiers AP and AN, which does not exert an influence on the adjustment of the output impedances Zp and Zn can be interrupted at the same time, power consumption can be further reduced as compared with that of the third embodiment. 
       Sixth Embodiment 
       [0158]      FIG. 17  is a circuit diagram showing a main part of a semiconductor device according to a sixth embodiment of the invention and is compared to  FIG. 1 . The semiconductor device of  FIG. 17  is different from the semiconductor device of  FIG. 1  with respect to the point that the inverters IP and IN are added to each of the replica circuits RP 1  and RP 2 . 
         [0159]    In the replica circuit RP 1 , the input node of the inverter IP receives the gate voltage VP 2 , and an output signal of the inverter IP is supplied to the gate of the P-channel MOS transistor P 4 . In the case where the gate voltage VP 2  is lower than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “H” level, and the P-channel MOS transistor P 4  is turned off. In the case where the gate voltage VP 2  is higher than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “L” level, and the P-channel MOS transistor P 4  is turned on. 
         [0160]    The input node of the inverter IN receives the gate voltage VN 2 , and an output signal of the inverter IN is supplied to the gate of the N-channel MOS transistor Q 4 . In the case where the gate voltage VN 2  is lower than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “H” level, and the N-channel MOS transistor Q 4  is turned on. In the case where the gate voltage VN 2  is higher than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “L” level, and the N-channel MOS transistor Q 4  is turned off. 
         [0161]    In the replica circuit RP 2 , the input node of the inverter IP receives the gate voltage VP 3 , and an output signal of the inverter IP is supplied to the gate of the P-channel MOS transistor P 4 . In the case where the gate voltage VP 3  is lower than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “H” level, and the P-channel MOS transistor P 4  is turned off. In the case where the gate voltage VP 3  is higher than the threshold voltage VTHP of the inverter IP, an output signal of the inverter IP becomes the “L” level, and the P-channel MOS transistor P 4  is turned on. 
         [0162]    The input node of the inverter IN receives the gate voltage VN 3 , and an output signal of the inverter IN is supplied to the gate of the N-channel MOS transistor Q 4 . In the case where the gate voltage VN 3  is lower than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “H” level, and the N-channel MOS transistor Q 4  is turned on. In the case where the gate voltage VN 3  is higher than the threshold voltage VTHN of the inverter IN, an output signal of the inverter IN becomes the “L” level, and the N-channel MOS transistor Q 4  is turned off. 
         [0163]    Next, the operation of the semiconductor device will be described. In the case where the replica circuit RP 3  becomes equal to the reference voltage VRP, the inverter IP of the replica circuit RP 2  detects that the gate voltage VP 3  is not the highest voltage, and turns off the P-channel MOS transistor P 4  in the replica circuit RP 2  to interrupt the constant current source CA. 
         [0164]    When the current of the constant current source CA is interrupted, the output voltage VFP 2  of the replica circuit RP 2  becomes the ground voltage VSS, so that the gate voltage VP 2  also becomes the lowest voltage. As a result, the inverter IP of the replica circuit RP 1  turns off the P-channel MOS transistor P 4  to interrupt the current of the constant current source CA. When the current of the constant current source CA is interrupted, the output voltage VFP 1  of the replica circuit RP 1  becomes the ground voltage VSS, so that the gate voltage VP 1  also becomes the lowest voltage. 
         [0165]    Concretely, as illustrated in the upper row in  FIG. 11 , when the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, the gate voltage VP 1  becomes the intermediate voltage, and both of the gate voltages VP 2  and VP 3  become the highest voltage. As a result, in each of the replica circuits RP 1  and RP 2 , the output signal of the inverter IP becomes the “L” level, the P-channel MOS transistor P 4  is turned on, and the output voltages VFP 1  to VFP 3  of the replica circuits RP 1  to RP 3  become the reference voltage VRP. 
         [0166]    The drain current of the P-channel MOS transistor P 1  is adjusted to a proper value, the P-channel MOS transistors P 2  and P 3  are turned off, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0167]    As illustrated in the intermediate row in  FIG. 18 , when the combined resistance value of the resistance elements RA 2  to RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance elements RA 3  and RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, the gate voltage VP 1  becomes the lowest voltage, the gate voltage VP 2  becomes the intermediate voltage, and the gate voltage VP 3  becomes the highest voltage. As a result, in the replica circuit RP 1 , an output signal of the inverter IP becomes the “H” level, the P-channel MOS transistor P 4  is turned off, and the output voltage VFP 1  becomes the ground voltage VSS. In the replica circuit RP 2 , an output signal of the inverter IP becomes the “L” level, the P-channel MOS transistor P 4  is turned on, and the output voltage VFP 2  of the replica circuit RP 2  becomes equal to the reference voltage VRP. Since the P-channel MOS transistor P 4  is on in the replica circuit RP 3 , the output voltage VFP 3  of the replica circuit RP 3  becomes equal to the reference voltage VRP. 
         [0168]    The P-channel MOS transistor P 1  is turned on, the drain current of the P-channel MOS transistor P 2  is adjusted to a proper value, the P-channel MOS transistor P 3  is turned off, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0169]    As illustrated in the lower row in  FIG. 18 , when the combined resistance value of the resistance elements RA 3  and RA 4  and the P-channel MOS transistor P 4  is higher than a predetermined value and the combined resistance value of the resistance element RA 4  and the P-channel MOS transistor P 4  is lower than the predetermined value, both of the gate voltages VP 1  and VP 2  become lowest voltage, and the gate voltage VP 3  becomes the intermediate voltage. As a result, in each of the replica circuits RP 1  and RP 2 , an output signal of the inverter IP becomes the “H” level, the P-channel MOS transistor P 4  is turned off, and the output voltages VFP 1  and VFP 2  become the ground voltage. In the replica circuit RP 3 , since the P-channel MOS transistor P 4  is on, the output voltage VFP 3  of the replica circuit RP 3  becomes equal to the reference voltage VRP. 
         [0170]    The P-channel MOS transistors P 1  and P 2  are turned on, the drain current of the P-channel MOS transistor P 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RA 1  to RA 4  and the P-channel MOS transistors P 1  to P 4  in the output buffer DOB is adjusted to a predetermined value. 
         [0171]    Similarly, in the case where the output voltage VFN 3  of the replica circuit RP 3  becomes equal to the reference voltage VRN, the inverter IN of the replica circuit RP 2  detects that the gate voltage VN 3  is not the lowest voltage, and the N-channel MOS transistor Q 4  is turned off to interrupt the current of the constant current source CB. When the current of the constant current source CB is interrupted, the output voltage VN 2  also becomes the highest voltage. As a result, the inverter IN of the replica circuit RP 1  turns off the N-channel MOS transistor Q 4  to interrupt the current of the constant current source CB. When the current of the constant current source CB is interrupted, the output voltage VFN 1  of the replica circuit RP 1  becomes the power supply voltage VDD, and the gate voltage VN 1  also becomes the highest voltage. 
         [0172]    Concretely, as illustrated in the upper row in  FIG. 19 , when the combined resistance value of the resistance elements RB 1  to RAB and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the gate voltage VN 1  becomes the intermediate voltage, and both of the gate voltages VN 2  and VN 3  become the lowest voltage. As a result, in each of the replica circuits RP 1  and RP 2 , the output signal of the inverter IN becomes the “H” level, the N-channel MOS transistor Q 4  is turned on, and the output voltages VFN 1  to VFN 3  of the replica circuits RP 1  to RP 3  become the reference voltage VRN. 
         [0173]    The drain current of the N-channel MOS transistor Q 1  is adjusted to a proper value, the N-channel MOS transistors Q 2  and Q 3  are turned off, and the combined resistance value of the resistance elements RB 1  to RAB and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0174]    As illustrated in the intermediate row in  FIG. 19 , when the combined resistance value of the resistance elements RB 2  to RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, the gate voltage VN 1  becomes the highest voltage, the gate voltage VN 2  becomes the intermediate voltage, and the gate voltage VN 3  becomes the lowest voltage. As a result, in the replica circuit RP 1 , an output signal of the inverter IP becomes the “L” level, the N-channel MOS transistor Q 4  is turned off, and the output voltage VFN 1  becomes the power supply voltage VDD. 
         [0175]    In the replica circuit RP 2 , the output signal of the inverter IP becomes the “H” level, the N-channel MOS transistor Q 4  is turned on, and the output voltage VFN 2  of the replica circuit RP 2  becomes equal to the reference voltage VRN. In the replica circuit RP 3 , the N-channel MOS transistor Q 4  is on, so that the output voltage VFN 3  of the replica circuit RP 3  becomes equal to the reference voltage VRN. 
         [0176]    The N-channel MOS transistor Q 1  is turned on, the drain current of the N-channel MOS transistor Q 2  is adjusted to a proper value, the N-channel MOS transistor Q 3  is turned off, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  in the output buffer DOB is adjusted to a predetermined value. 
         [0177]    As illustrated in the lower row in  FIG. 19 , when the combined resistance value of the resistance elements RB 3  and RB 4  and the N-channel MOS transistor Q 4  is higher than a predetermined value and the combined resistance value of the resistance element RB 4  and the N-channel MOS transistor Q 4  is lower than the predetermined value, both of the output voltages VN 1  and VN 2  become the highest voltage, and the gate voltage VN 3  becomes the intermediate voltage. As a result, in each of the replica circuits RP 1  and RP 2 , an output signal of the inverter IP becomes the “L” level, the N-channel MOS transistor Q 4  is turned off, and the output voltages VFN 1  and VFN 2  become the power supply voltage VDD. In the replica circuit RP 3 , since the N-channel MOS transistor Q 4  is on, the output voltage VFN 3  of the replica circuit RP 3  becomes equal to the reference voltage VRN. 
         [0178]    The N-channel MOS transistors Q 1  and Q 2  are turned on, the drain current of the N-channel MOS transistor Q 3  is adjusted to a proper value, and the combined resistance value of the resistance elements RB 1  to RB 4  and the N-channel MOS transistors Q 1  to Q 4  of the output buffer DOB is adjusted to a predetermined value. 
         [0179]    In the sixth embodiment, the effect similar to that of the first embodiment is obtained. In addition, since through current of the replica circuit RP which does not exert an influence on the adjustment of the output impedances Zp and Zn can be interrupted, power consumption can be further reduced as compared with that of the first embodiment. 
       Seventh Embodiment 
       [0180]      FIG. 20  is a block diagram showing a  1   a  semiconductor device according to a seventh embodiment of the invention. In  FIG. 20 , the semiconductor device is used in, for example, a port part of a personal computer and has the semiconductor substrate  10 . Along one side of the semiconductor substrate  10 , seven pads PD 1  to PD 7  are disposed in one line in the vertical direction of the diagram at predetermined intervals. A first port is formed by the pads PD 1  to PD 3 , and a second port is formed by the pads PD 5  to PD 7 . To the first port or the second port, for example, a mouse is coupled. The pads PD 1  and PD 2  are used to input/output complementary signals V+ and V−. The pads PD 5  and PD 6  are used to input/output the complementary signals V+ and V−. To each of the pads PD 3 , PD 4 , and PD 7 , the power supply voltage VDD is output. 
         [0181]    The pads PD 1  to PD 7  are provided in the regions of ESD (Electro-Static Discharge) protection circuits  11  to  17 , respectively. The ESD protection circuits  11  to  17  protect internal circuits by discharging static electricity generated in the pads PD to PD 7  to the line (not-shown) of the ground voltage VSS. 
         [0182]    An output buffer  21  and an input buffer  31  are disposed in order in a region on the right side in the diagram of the ESD protection circuit  11 , and an output buffer  22  and an input buffer  32  are disposed in order in a region on the right side in the diagram of the ESD protection circuit  12 . An output buffer  25  and an input buffer  34  are disposed in order in a region on the right side in the diagram of the ESD protection circuit  15 , and an output buffer  26  and an input buffer  35  are disposed in order in a region on the right side in the diagram of the ESD protection circuit  16 . 
         [0183]    Each of the output buffers  21 ,  22 ,  25 , and  26  includes the full-speed output buffer DOB shown in  FIG. 1  and the high-speed output buffer DOB 0  shown in  FIG. 7 . The output buffer  21  outputs the signal V+ to the pad PD 1  in response to an internal signal φV+. The output buffer  22  outputs the signal V− to the pad PD 2  in response to an internal signal φV−. The output buffer  25  outputs the signal V+ to the pad PD 5  in response to the internal signal φV+. The output buffer  26  outputs the signal V− to the pad PD 6  in response to the internal signal φV−. 
         [0184]    Each of the input buffers  31 ,  32 ,  34 , and  35  includes the full-speed input buffer and the high-speed input buffer. The input buffer  31  generates the internal signal φV+ in response to an external signal V+ supplied to the pad PD 1 . The input buffer  32  generates the internal signal φV− in response to an external signal V− supplied to the pad PD 2 . The input buffer  34  generates the internal signal φV+ in response to the external signal V+ supplied to the pad PD 5 . The input buffer  35  generates the internal signal φV− in response to the external signal V− supplied to the pad PD 6 . 
         [0185]    A power supply detection circuit (VBUS)  23  and a control voltage generation circuit+replica circuit  33  are disposed in order in a region on the right side in the diagram of the ESD protection circuit  13 , and a PLL (Phase Locked Loop) circuit  24  is disposed in a region on the right side in the diagram of the ESD protection circuit  14 . A power supply detection circuit (VBUS)  27  is disposed in a region on the right side in the diagram of the ESD protection circuit  17 . 
         [0186]    The power supply detection circuit  23  generates a power supply detection signal in response to output of the power supply voltage VDD to the pad PD 3  in the first port. The power supply detection circuit  27  generates a power supply detection signal in response to output of the power supply voltage VDD to the pad PD 7  in the second port. 
         [0187]    The control voltage generation circuit+replica circuit  33  includes the control voltage generation circuit VCG and the replica circuits RP 1  to RP 3  illustrated in  FIG. 1  and supplies the gate voltages VP 1  to VP 3  and VN 1  to VN 3  to the full-speed output buffers DOB in the output buffers  21 ,  22 ,  25 , and  26 . The PLL circuit  24  generates an internal clock signal synchronized with an external clock signal. 
         [0188]    In the seventh embodiment, one control voltage generation circuit 30  replica circuit  33  is provided for the plurality of output buffers  21 ,  22 ,  25 , and  26 , so that layout area can be reduced. 
         [0189]    It should be understood that the embodiments disclosed herein are illustrative and not restrictive in all of aspects. The scope of the present invention is defined by the scope of claims rather than by the above description, and all changes in the claims or equivalents are intended to be included.