Abstract:
A high-speed Fibre Channel switch element in a Fibre Channel network is provided. The Fibre Channel switch element includes, a rate select module that allows a port in the Fibre Channel switch element to operate at a rate equal to and/or higher than 10 gigabits per second (“G”). The port may operate at 20G, 40G or at a rate greater than 40G. Also, a cut status is provided for cut-through routing between ports operating at different speed. Plural transmit and receive lines are used for port operation at a rate equal to or higher than 10G.

Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to Fibre Channel networks, and more particularly to a Fibre Channel switch element that can operate at a high speed.  
         [0003]     2. Background of the Invention  
         [0004]     Fibre Channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre Channel provides an input/output interface to meet the requirements of both Channel and network users.  
         [0005]     Fibre Channel supports three different topologies: point-to-point, arbitrated loop and Fibre Channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The Fibre Channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The Fibre Channel fabric topology allows several media types to be interconnected.  
         [0006]     In Fibre Channel, a path is established between two nodes where the path&#39;s primary task is to transport data from one point to another at high speed with low latency, performing only simple error detection in hardware.  
         [0007]     Fibre Channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or “F_port”. Fabric elements include the intelligence to handle routing, error detection, recovery, and similar management functions.  
         [0008]     A Fibre Channel switch is a multi-port device where each port manages a simple point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and automatically routes it to another port. Multiple calls or data transfers happen concurrently through the multi-port Fibre Channel switch.  
         [0009]     Fibre Channel switches use memory buffers to hold frames received and sent across a network. Associated with these buffers are credits, which are the number of frames that a buffer can hold per fabric port.  
         [0010]     Current Fibre Channel standards define switch port/link operations to occur at 1 gigabit per second (“G”), 2 G, 4 G and 10 G. However, as bandwidth increases a need for 20 G, 40 G or higher port/link operation will occur. Conventional standards and Fibre Channel switches do not provide Fibre Channel switches that can operate at such high speeds.  
         [0011]     Therefore, there is a need for a Fibre Channel switch whose ports can be selected to operate at high speeds, for example, at 10 G, 20 G or 40 G.  
       SUMMARY OF THE PRESENT INVENTION  
       [0012]     In one aspect of the present invention, a high-speed Fibre Channel switch element is provided. The Fibre Channel switch element includes, a rate select module that allows a port in the Fibre Channel switch element to operate at a rate equal to and/or higher than 10 gigabits per second (“G”). The port may operate at 20 G, 40 G or at a rate greater than 40 G.  
         [0013]     Also, a cut status is provided for cut-through routing between ports operating at different speed. Plural transmit and receive lines are used for port operation at a rate equal to or higher than 10 G.  
         [0014]     In another aspect of the present invention, a Fibre Channel network is provided. The network includes a Fibre Channel switch element including a rate select module that allows a port in the Fibre Channel switch element to operate at a rate equal to and/or higher than 10 G, as described above.  
         [0015]     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:  
         [0017]      FIG. 1A  shows an example of a Fibre Channel network;  
         [0018]      FIG. 1B  shows an example of a Fibre Channel switch element, according to one aspect of the present invention;  
         [0019]      FIG. 1C  shows a block diagram of a 20-channel switch chassis, according to one aspect of the present invention;  
         [0020]      FIG. 1D  shows a block diagram of a Fibre Channel switch element with sixteen GL_Ports and four XG ports, according to one aspect of the present invention;  
         [0021]      FIG. 2  shows a block diagram of a Fibre Channel switch with a rate select module, according to one aspect of the present invention; and  
         [0022]      FIG. 3  shows a table for cut-through routing, according to one aspect of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]     Definitions:  
         [0024]     The following definitions are provided as they are typically (but not exclusively) used in the Fibre Channel environment, implementing the various adaptive aspects of the present invention.  
         [0025]     “E_Port”: A fabric expansion port that attaches to another Interconnect port to create an Inter-Switch Link.  
         [0026]     “F_Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports.  
         [0027]     “Fibre Channel ANSI Standard”: The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others.  
         [0028]     “Fabric”: The structure or organization of a group of switches, target and host devices (NL_Port, N_ports etc.).  
         [0029]     “N-Port”: A direct fabric attached port, for example, a disk drive or a HBA.  
         [0030]     “NL_Port”: A L_Port that can perform the function of a N_Port.  
         [0031]     “Port”: A general reference to N. Sub.—Port or F.Sub.—Port.  
         [0032]     “Switch”: A fabric element conforming to the Fibre Channel Switch standards.  
         [0033]     To facilitate an understanding of the preferred embodiment, the general architecture and operation of a Fibre Channel switch system/element will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture.  
         [0034]     Fibre Channel System  
         [0035]      FIG. 1A  is a block diagram of a Fibre Channel system  100  implementing the methods and systems in accordance with the adaptive aspects of the present invention. System  100  includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device, e.g. server  103 , disk array  105  and storage device  104 . Fabric ports are located in fabric devices such as switch  101  and  102 . Arbitrated loop  106  may be operationally coupled to switch  101  using arbitrated loop ports (FL_Ports).  
         [0036]     The devices of  FIG. 1A  are operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. between server  103  and storage  104 . A packet-switched path may be established using multiple links, e.g. an N_Port in server  103  may establish a path with disk array  105  through switch  102 .  
         [0037]     Switch Element  
         [0038]      FIG. 1B  is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.  FIG. 1B  provides the general architecture of a 20-channel switch chassis using the 20-port fabric element. Fabric element includes ASIC 20 with non-blocking Fibre Channel class 2 (connectionless, acknowledged) and class 3 (connectionless, unacknowledged) service between any ports. It is noteworthy that ASIC 20 may also be designed for class 1 (connection-oriented) service, within the scope and operation of the present invention as described herein.  
         [0039]     The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. Although  FIG. 1B  shows 20 ports, the present invention is not limited to any particular number of ports.  
         [0040]     ASIC 20 has 20 ports numbered in  FIG. 1B  as GL 0  through GL 19 . These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below.  
         [0041]     For illustration purposes only, all GL ports are drawn on the same side of ASIC 20 in  FIG. 1B . However, the ports may be located on both sides of ASIC 20 as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC.  
         [0042]     Each port GL 0 -GL 19  has transmit and receive connections to switch crossbar  50 . One connection is through receive buffer  52 , which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmit buffer  54 .  
         [0043]     Switch crossbar  50  includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only, switch crossbar  50  is shown as a single crossbar. Switch crossbar  50  is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external to ASIC 20.  
         [0044]     In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/output processor (“IOP”). IOP  66  is shown in  FIG. 1C  as a part of a switch chassis utilizing one or more of ASIC 20. As seen in  FIG. 1B , bi-directional connection to IOP  66  is routed through port  67 , which connects internally to a control bus  60 . Transmit buffer  56 , receive buffer  58 , control register  62  and Status register  64  connect to bus  60 . Transmit buffer  56  and receive buffer  58  connect the internal connectionless switch crossbar  50  to IOP  66  so that it can source or sink frames.  
         [0045]     Control register  62  receives and holds control information from IOP  66 , so that IOP  66  can change characteristics or operating configuration of ASIC 20 by placing certain control words in register  62 . IOP  66  can read status of ASIC 20 by monitoring various codes that are placed in status register  64  by monitoring circuits (not shown).  
         [0046]      FIG. 1C  shows a 20-channel switch chassis S 2  using ASIC 20 and IOP  66 . S 2  will also include other elements, for example, a power supply (not shown). The 20 GL_Ports correspond to channel C 0 -C 19 . Each GL_Port has a serial/deserializer (SERDES) designated as S 0 -S 19 . Ideally, the SERDES functions are implemented on ASIC 20 for efficiency, but may alternatively be external to each GL_Port. The SERDES converts parallel data into a serial data stream for transmission and converts received serial data into parallel data. The 8 bit to 10 bit encoding enables the SERDES to generate a clock signal from the received data stream.  
         [0047]     Each GL_Port may have an optical-electric converter, designated as OE 0 -OE 19  connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C 0 -C 19 . It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters.  
         [0048]      FIG. 1D  shows a block diagram of ASIC 20 with sixteen GL ports and four high-speed port control modules designated as XG 0 -XG 3  (for example, 10 G, 20 G or 40 G). ASIC 20 include a control port  62 A that is coupled to IOP  66  through a PCI connection  66 A.  
         [0049]     Details of how switch  20  is operated is provided in U.S. patent application Ser. No. 10/894,587, filed on Jul. 20, 2004, the disclosure of which is incorporated herein by reference in its entirety.  
         [0050]      FIG. 2  shows another block diagram of switch element  20 , according to one aspect of the present invention. Switch element  20  has receive and transmit pipelines  202 A that operate in the manner described in the aforementioned patent application using plural data buffers  203 .  
         [0051]     A rate select module  202  is provided that selects a particular speed for a port based on a select speed signal  201  that is generated from the common port  62 A. Firmware for switch element  20  may be used to generate signal  201 . Module  202  provides the appropriate clock and configuration signals for a 10 G, 20 G, 40 G or port/link operation at any rate.  
         [0052]     A port can negotiate with another port to operate at 10 G/20 G/40 G or any other rate. A port may operate at 10 G, 20 G, 40 G, 10 G and 20 G, 20 G and 40 G or any other combination. The negotiation process may be similar to that described in the FC-FS Fibre Channel standard. The ‘RF” primitive may be used to replace the “NOS” primitive, as discussed in FC-FS.  
         [0053]     SERDES  204 ,  205 ,  206  and  207  converts parallel 10 bit characters into a serial stream on the transmit side (i.e. data to the network) and converts data received by switch element  20  into 10-bit characters. SERDES  204 - 207  recover clock information from data that is received by a port.  
         [0054]     In one aspect of the present invention, for a 20 G operation, 4 serial streams (i.e., four transmit and four receive lanes) (as shown in  FIG. 2  with SERDES  204 - 207 ) at 6.375 G may be used. Each lane encodes/decodes a byte of data using 8 B/10 B code. The 20 G ports may be connected through passive copper, actively driven copper or optical at the same or different wavelengths (one wavelength for each lane) paths (not shown).  
         [0055]     For a 40 G operation, 4 serial streams each at 12.75 G may be used. Each lane encodes/decodes a byte of data using 8 B/10 B code. The four lanes are synchronized and aligned, as described in the aforementioned patent application.  
         [0056]     It is noteworthy that the invention is not limited to any particular number of serial streams; for example, a single stream may be used to operate a port at 20 G/40 G or any other rate. Also, the serial streams may operate at the same optical wavelength or different wavelengths; one for each serial stream.  
         [0057]     SERDES  204 - 207  clock rates are manipulated to facilitate higher speed operation. Currently the XAUI interface (incorporated herein by reference in its entirety) supports 10 G operation using four transmit and four receive lanes; each lane encoding data with an 8 B/10 B code for differential serial transmission and operating at 3.1875 GigaBaud. To operate at higher speeds, a full rate will be at 12.75 GigaBaud, half rate will be at 6.375 GigaBaud. The full rate, half and quarter rates are selected by module  202 , based on signal  201 .  
         [0058]     Cut-Through Routing at Higher Speeds:  
         [0059]     “Cut” bits are a status signal sent from receive to transmit buffers to keep the transmit buffer running as quickly as possible by either guaranteeing that the transmit port either does not run out of data or by allowing the transmit port to re-arbitrate its tags to select a frame source that has the “cut” bit set. The use of cut bits at lower rates (i.e., 1 G, 2 G, 4 G and 10 G) is described in the aforementioned patent application. The Cut Bits may be expanded to include 20 G, 40 G or higher transfer rates.  
         [0060]     To reduce latency, a frame is released from a receive buffer, after a certain threshold value is reached. However, if the receive buffer slots become almost full with other frames, then new incoming frames wait for the end of frame (“EOF”). This reduces contention time on shared resources that may occur if the receive buffer is tied up for “cut” through routing.  
         [0061]     There are different conditions on cut status depending on what kind of port the Receive Buffer resides in (for example, 10 G/20 G/40 G or any other speed). The selection of cut status also depends on the type of port the Transmit Port resides in. Table I in  FIG. 3 , shows how some cut through frame length calculations are performed depending upon port transfer rates.  
         [0062]     In one aspect of the present invention, a port can be configured to operate at different rates. High bandwidth operation is permitted for better performance.  
         [0063]     Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.