Abstract:
A semiconductor memory test device is capable of reducing the test time and increasing test reliability by applying an effective stress in a burn-in level or a wafer level. The semiconductor memory test device controls a sense amplifier using an additional sense amplifier driving signal when a 2rb pattern stress is applied. Therefore, the semiconductor memory test device applies a uniform stress by applying the constant supply voltage to a cell corresponding to the entire wordlines.

Description:
BACKGROUND 
   1. Technical Field 
   The present invention relates to a semiconductor memory test device and, more particularly, to a semiconductor memory test device in which uniform stress can be applied at a constant voltage to cells corresponding to entire wordlines. 
   2. Description of the Prior Art 
   The  2 rb pattern stress represents a mode in which each of a pair of wordlines is alternately driven in a burn-in test. For example, wordlines WL 0 -WL 7  can be classified into a unit pair of the wordlines (WL 0 , WL 1 ), (WL 2 , WL 3 ), (WL 4 , WL 5 ) and (WL 6 , WL 7 ), respectively. An enable state of this unit pair will be below explained. First, the wordlines (WL 2 , WL 3 ) and (WL 6 , WL 7 ) are disabled when the wordlines (WL 0 , WL 1 ) and (WL 4 , WL 5 ) are enabled, and the wordlines (WL 0 , WL 1 ) and (WL 4 , WL 5 ) are disabled when the wordlines (WL 2 , WL 3 ) and (WL 6 , WL 7 ) are enabled. 
     FIG. 1  is a block diagram of a conventional burn-in stress apparatus. A main wordline (mwl) is connected to a sub X-decoder  10  and the sub X-decoder  10  is also connected to a plurality of sub-wordlines wl 0 -wl 7 . A sub-hole  40  outputs eight wordline driver driving select signals (px&lt; 0 : 7 &gt;) to the sub X-decoder  10 . A test mode decoder  20  decodes an input signal to produce an even wordline driving signal (even), an odd wordline driving signal (odd), the entire wordline driving signal (all), wordline driving signals ( 2 rbe — with sa and  2 rbo — with sa) and a normal sense amplifier enable signal (nsae) to a sense amplifier control unit  30 . The sense amplifier control unit  30  outputs an inverted wordline driver driving select signal (pxz&lt; 0 : 7 &gt;), an inverted bit line equalizer signal (bleqz), a sense amplifier pull-up driving signal (rto) and an inverted sense amplifier pull-down driving signal (sz) to the sub-hole  40 , depending on each of the signals received from the test mode decoder  20 . A plurality of sense amplifiers  50  each sense and amplify data applied to bit lines bl, bl depending on a bit line equalizer signal (bleq), an inverted sense amplifier pull-up driving signal (rtoz) and a sense amplifier pull-down driving signal(s) from the sub-hole  40 . 
     FIG. 2  is a detailed circuit diagram of the sense amplifier control unit in  FIG. 1 . An X-decoder  31  decodes an even wordline driving signal (even), an odd wordline driving signal (odd), the entire wordline driving signal (all) and a wordline driving signals ( 2 rbe — with sa and  2 rbo — with sa), which are received from the test mode decoder  20 , to produce an inverted wordline driver driving select signal (pxz&lt; 0 : 7 &gt;) to the sub-hole  40 . Also, a sense amplifier driving unit  32  outputs an inverted bit line equalizer signal (bleqz), a sense amplifier pull-up driving signal (rto), and an inverted sense amplifier pull-down driving signal (sz), for controlling the sense amplifier  50 , to the sub-hole  40 , depending on the wordline driving signals ( 2 rbe — with sa and  2 rbo — with sa) and the normal sense amplifier enable signal (nsae). 
     FIG. 3  is a detailed circuit diagram of the sense amplifier-driving unit  32  in  FIG. 2 . The sense amplifier driving unit  32  includes a NOR gate NOR 1  for NORing the wordline driving signals ( 2 rbe — with sa and  2 rbo — with sa), and an inverter IV 1  for inverting the normal sense amplifier enable signal (nsae). A NAND gate ND 1  NANDs the output signals of the NOR gate NOR 1  and the inverter IV 1  and outputs a sense amplifier driving signal (sae). Inverters IV 2  and IV 3  delay the sense amplifier driving signal (sae), and then the inverter IV 3  output an inverted bit line equalizer signal (bleqz). Inverters IV 4  and IV 5  delay the sense amplifier driving signal (sae), and then the inverter IV 5  outputs a sense amplifier pull-up driving signal (rto). An inverter IV 6  inverts the sense amplifier driving signal (sae) to produce an inverted sense amplifier pull-down driving signal (sz). 
   An operating procedure of the conventional burn-in stress apparatus having this structure is described below with reference to  FIGS. 4–7 . 
   In a process of manufacturing a general dynamic random access memory (DRAM), a method by which an artificial stress is applied between cell-to-cell, line-to-line and node-to-node at a high temperature burn-in mode in order to verify reliability and secure the quality is usually employed. One of the artificial stresses used is a  2 rb pattern stress. 
     FIGS. 4–7  illustrate a process of applying stress in this  2 rb pattern stress method, which includes enabling the wordlines WL by two and driving the sense amplifier so that HIGH or LOW signals are applied to corresponding cells and stress is applied between neighboring nodes. 
     FIG. 4  shows a case in which the even wordline-driving signal (even) is enabled and the sense amplifier driving signal (sae) is not outputted from the sense amplifier-driving unit  32 . If the sense amplifier driving signal (sae) is disabled, the sense amplifier pull-up driving signal (rto) becomes HIGH, the inverted sense amplifier pull-down driving signal (sz) becomes LOW, and the bit line precharge signal (blp) and the bit line equalizer signal (bleq) become HIGH. At this time, the even (0, 2, 4, 6) wordlines WL 0 , WL 2 , WL 4  and WL 6  are selected and the bit line precharge voltage (Vblp) becomes LOW. 
     FIG. 5  shows a case in which the odd wordline-driving signal (odd) is enabled and the sense amplifier driving signal (sac) is not outputted from the sense amplifier-driving unit  32 . In this case, the odd (1, 3, 5, 7) wordlines WL 1 , W 13 , WL 5  and WL 7  are selected and the bit line precharge voltage (Vblp) becomes HIGH. 
     FIG. 6  shows a case in which the wordline driving signal ( 2 rbe) is enabled and the sense amplifier driving signal (sac) is outputted from the sense amplifier-driving unit  32 . Also, the  2 rbe wordlines WL 0 , WL 1 , WL 4  and WL 5  are enabled by the wordline driving signal ( 2 rbe). At this time, if the sense amplifier driving signal (sac) is enabled to HIGH, the sense amplifier is driven to write HIGH and LOW into the bit lines bl, /bl, respectively, corresponding to the  2 rbe wordlines WL 0 , WL 1 , WL 4  and WL 5  and a stress is applied to corresponding nodes via the bit lines bl, /bl for a predetermined time. 
     FIG. 7  shows a case in which the wordline driving signal ( 2 rbo) is enabled and the sense amplifier driving signal (sac) is outputted from the sense amplifier-driving unit  32 . Also, the  2 rbo wordlines WL 2 , WL 3 , WL 6  and WL 7  are enabled by the wordline driving signal ( 2 rbo). At this time, if the sense amplifier driving signal (sac) is enabled to HIGH, the sense amplifier is driven to write HIGH and LOW into the bit lines bl, /bl, respectively, corresponding to the  2 rbo wordlines WL 2 , WL 3 , WL 6  and WL 7  and apply a stress to corresponding nodes via the bit lines bl, /bl for a predetermined time. An operating timing of the conventional burn-in stress apparatus is shown in  FIG. 8 . 
   However, this type of a conventional burn-in stress apparatus applies a stress to cell-to-cell, storage node contact (snc)-to-snc and snc-to-cell, while selectively enabling the wordlines corresponding to the wordline driving signals ( 2 rbe and  2 rbo). 
   At this time, the conventional burn-in stress apparatus enables the wordlines WL by dividing it into two units using the wordline driving signals ( 2 rbe and  2 rbo) and drives the sense amplifier. Therefore, there is a problem that the test time increases and a portion of the device is partially over-stressed and another portion of the device is relatively under-stressed. 
   SUMMARY 
   The disclosed apparatus may include a test mode decoder for decoding an inputted address signal and outputting a wordline driving signal and a sense amplifier driving signal. The disclosed apparatus may also include a driving unit for controlling said sense amplifier depending on said sense amplifier driving signal and being enable all the wordlines when said sense amplifier is enabled. 
   In another embodiment, the disclosed device may include a test mode decoder for decoding inputted address signals and outputting wordline driving signal and a sense amplifier driving signal; a sense amplifier control unit for decoding the wordline driving signal, outputting a wordline driver driving select signal, and enabling all the wordlines when said sense amplifier is enabled depending on said sense amplifier driving signal and a sub-hole for inverting the wordline driver driving select signal and the sense amplifier control signal. The device may also include a sub X-decoder for enabling a selected wordline depending on the wordline driver driving select signal and a sense amplifier enabled depending on the sense amplifier control signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram illustrating a conventional burn-in stress apparatus; 
       FIG. 2  is a detailed circuit diagram illustrating a sense amplifier control unit in  FIG. 1 ; 
       FIG. 3  is a detailed circuit diagram illustrating a sense amplifier-driving unit in  FIG. 2 ; 
       FIGS. 4–7  are circuit diagrams explaining a wordline driving mode in a conventional burn-in stress apparatus; 
       FIG. 8  is a timing diagram illustrating a conventional operating pattern; 
       FIG. 9  is a block diagram illustrating a semiconductor memory test device; 
       FIG. 10  is a detailed circuit diagram illustrating a test mode decoder in  FIG. 9 ; 
       FIG. 11  is a detailed circuit diagram illustrating a sense amplifier control unit in  FIG. 9 ; 
       FIG. 12  a detailed circuit diagram illustrating a sense amplifier-driving unit in  FIG. 11 ; 
       FIGS. 13–15  are circuit diagrams explaining a wordline driving mode; and 
       FIG. 16  is a timing diagram illustrating an operating pattern of the semiconductor memory test device. 
   

   DETAILED DESCRIPTION 
   The disclosed apparatus is described in detail with reference to accompanying drawings, in which like reference numerals are used to identify the same or similar parts. 
     FIG. 9  is a block diagram illustrating a semiconductor memory test device. The semiconductor memory test device includes a sub X-decoder  100 , a test mode decoder  200 , a sense amplifier control unit  300 , a sub-hole  400  and a sense amplifier  500 . 
   A main wordline mwl is connected to the sub X-decoder  100 . The sub X-decoder  100  is connected to a plurality of sub-wordlines wl 0 -wl 7 . The sub-hole  400  outputs eight wordline driver driving select signals (px&lt; 0 : 7 &gt;) to the sub X-decoder  100 . The test mode decoder  200  decodes an inputted signal, and then outputs an even wordline driving signal (even), an odd wordline driving signal (odd), the entire wordline driving signal (all), wordline driving signals ( 2 rbe and  2 rbo), a sense amplifier driving signal (tsae), and a normal sense amplifier enable signal (nsae) to the sense amplifier control unit  300 . The sense amplifier control unit  300  outputs an inverted wordline driver driving select signal (pxz&lt; 0 : 7 &gt;), an inverted bit line equalizer signal (bleqz), a sense amplifier pull-up driving signal (rto) and an inverted sense amplifier pull-down driving signal (sz) to the sub-hole  400 , depending on each of the output signals of the test mode decoder  200 . The plurality of the sense amplifiers  500  senses data applied to the bit line bl,/bl depending on a bit line equalizer signal (bleq), an inverted sense amplifier pull-up driving signal (rtoz) and the sense amplifier pull-down driving signals. 
     FIG. 10  is a detailed circuit diagram illustrating the test mode decoder  200  of  FIG. 9 . The test mode decoder  200  includes a signal generating unit  201 , an address control unit  202  and a decoder  203 . 
   The signal generating unit  201  delays an address signals (aw&lt; 8 &gt;) for a given period of time to produce a pulse generating signal (vcmdp). The address control unit  202  receives address signals (awb&lt; 9 &gt;, awb&lt; 11 &gt;and awb&lt; 12 &gt;), and outputs address signals (awd&lt; 9 &gt;, awd&lt; 11 &gt;and awd&lt; 12 &gt;). The decoder  203  decodes the address signals (awbd&lt; 9 &gt;, awd&lt; 9 &gt;, awbd&lt; 11 &gt;, awd&lt; 11 &gt;, awbd&lt; 12 &gt;and awd&lt; 12 &gt;) and the pulse generating signal (vcmdp) to produce the even wordline driving signal (even), the odd wordline driving signal (odd), the entire wordline driving signal (all), wordline driving signals ( 2 rbe,  2 rbo) every two, and the sense amplifier driving signal (tsae). The address signals (awb&lt; 8 &gt;-awb&lt; 12 &gt;) is an externally inputted address signals, and may be internally generated signals in the other embodiment. 
   The signal generating unit  201  includes inverters IV 7 –IV 12  for delaying an inputted address signal (aw&lt; 8 &gt;), inverters IV 13 –IV 17  for inverting/delaying the output of the inverter IV  12 , a NAND gate ND 2  for performing a NAND logic function on the output of the inverter IV 12  and the output of the inverter IV 17 , and a NAND gate ND 3  for NANDing the output of the NAND gate ND 2  and an inputted power-up signal (pwrup) and outputting a pulse generating signal (vcmdp). 
   Also, the address control unit  202  includes inverters IV 18 –IV 20  for inverting/delaying the address signal (awb&lt; 9 &gt;) to produce the address signal (awd&lt; 9 &gt;), inverters IV 24 –IV 26  for inverting/delaying the address signal (awb&lt; 11 &gt;) to produce the address signal (awd&lt; 9 &gt;), and inverters IV 27 –IV 29  for inverting/delaying the address signal (awb&lt; 12 &gt;) to produce an address signal (awd&lt; 12 &gt;). 
   Further, the decoder  203  includes NAND gates ND 4 –ND 11  for NANDing the address signals (awbd&lt; 9 &gt;, awd&lt; 9 &gt;, awbd&lt; 11 &gt;, awd&lt; 11 &gt;, awbd&lt; 12 &gt;and awd&lt; 12 &gt;), inverters IV 30 –IV 37  for inverting the outputs of the NAND gates ND 4 –ND 11 , respectively, NAND gates ND 12 –ND 19  for NANDing the outputs of the inverters IV 30 –IV 37  and the pulse generating signal (vcmdp), respectively, latches R 1 –R 7  for latching the outputs of the NAND gates ND 12 –ND 19  and the power-up signal (pwrup), respectively, and inverters IV 38 –IV 51  for delaying the outputs of the latches R 1 – 4 R 7  to produce the even wordline driving signal (even), the odd wordline driving signal (odd), the whole wordline driving signal (all), the wordline driving signals ( 2 rbe,  2 rbo), and the sense amplifier driving signal (tsae). 
     FIG. 11  is a detailed circuit diagram illustrating the sense amplifier control unit  300  of  FIG. 9 . The X-decoder  301  decodes the even wordline driving signal (even), the odd wordline driving signal (odd), the whole wordline driving signal (all) and the wordline driving signals ( 2 rbe and  2 rbo) and outputs the inverted wordline driver driving select signal (pxz&lt; 0 : 7 &gt;) to the sub-hole  400 . Also, the sense amplifier driving unit  302  outputs the inverted bit line equalizer signal (bleqz), the sense amplifier pull-up driving signal (rto) and the inverted sense amplifier pull-down driving signal (sz), for controlling the sense amplifier  500 , to the sub-hole  400 , depending on the wordline driving signals ( 2 rbe and  2 rbo), the normal sense amplifier enable signal (nsae) and the sense amplifier driving signal (tsae). 
     FIG. 12  a detailed circuit diagram of the sense amplifier-driving unit  302  of  FIG. 11 . The sense amplifier driving unit  302  includes a first signal generating unit  303  and a second signal generating unit  304 . The first signal generating unit  303  includes an inverter IV 52  for inverting the sense amplifier driving signal (tsae), an inverter IV 53  for inverting the normal sense amplifier enable signal (nsae), and a NAND gate ND 20  for NANDing the sense amplifier driving signal (tsae) and the normal sense amplifier enable signal nsae inverted through the inverter IV 52  and the inverter IV 53  to produce the sense amplifier driving signal (sae). Also, the second signal generating unit  304  includes a NOR gate NOR 2  for NORing the wordline driving signals ( 2 rbe and  2 rbo), an inverter IV 54  for inverting the output of the NOR gate NOR 2 , a NOR gate NOR 3  for NORing the output signal of the inverter IV 54  and the sense amplifier driving signal (sae), and an inverter IV 55  for inverting the output of the NOR gate NOR 3  to produce the inverted bit line equalizer signal (bleqz). Also, the sense amplifier driving unit  302  further includes inverters IV 56  and IV 57  for delaying the sense amplifier driving signal (sae) to produce the sense amplifier pull-up driving signal (rto), and an inverter IV 58  for inverting the sense amplifier driving signal (sae) to produce the sense amplifier pull-down driving signal (sz). 
   The operation of the semiconductor memory test device having this structure is described with reference to  FIGS. 13–15 . 
   First, when the sense amplifier driving signal (sae) is disabled, the sense amplifier pull-up driving signal (rto) becomes HIGH, the inverted sense amplifier pull-down driving signal (sz) becomes LOW, and the bit line precharge signal (blp) and the bit line equalizer signal (bleq) become HIGH. At this time, the even (0, 2, 4, 6) wordlines WL 0 , WL 2 , WL 4  and WL 6  are selected and the bit line precharge voltage (Vblp) becomes LOW. 
   Next, after the odd wordlines WL 0 , WL 2 , WL 4  and WL 6  are disabled, the odd (1, 3, 5, 7) wordlines WL 1 , W 13 , WL 5  and WL 7  are selected and the bit line precharge voltage (Vblp) becomes HIGH. 
   As shown in  FIG. 13 , if the wordline driving signal ( 2 rbe) is enabled, the bit lines bl,/bl become a high potential (cvdd) and a low potential (vss) by charge distribution, respectively. At this time, the sense amplifier  500  is not driven. The sense amplifier  500  is only driven when the sense amplifier driving signal (sae) is enabled. 
   As shown in  FIG. 14 , if an additional sense amplifier driving signal (sae) is applied when the charge distribution of the bit lines bl,/bl is completed, the sense amplifier is enabled. Also, if the wordlines corresponding to the wordline driving signal ( 2 rbe) are enabled, HIGH and LOW are applied to the bit lines bl,/bl of corresponding cell, respectively. At this time, HIGH and LOW are uniformly sequentially applied to the bit line B and the bit line bar /B by charge distribution. 
   Then, as shown in  FIG. 15 , when sense amplifier is enabled, the wordlines WL 2 , WL 3 , WL 6  and WL 7  corresponding to the wordline driving signal  2 rbo are enabled. At this time, the wordline driving signals ( 2 rbe and  2 rbo) are selected and data applied to the bit lines b,/b by the same sense amplifier are sensed, where in the data of a cell corresponding to the wordline driving signal ( 2 rbo) is adversely written. Therefore, the data of a cell corresponding to the wordline driving signal ( 2 rbe) and the data of a cell corresponding to the wordline driving signal ( 2 rbo) do not collide. 
   An operating timing diagram of the disclosed semiconductor memory test device is shown in  FIG. 16 . 
   It should be noted that the above method is only one embodiment and the sequence in which the even wordlines and the odd wordlines are enabled or the sequence in which the wordline driving signals ( 2 rbe and  2 rbo) are enabled could be changed. 
   As mentioned above, the disclosed apparatus is advantageous in it can reduce the test time by controlling the bias of the entire cells using only the potential of the bit line at the sense amplifier and a stress application time. Further, the disclosed apparatus may reduce a region that is partially over-stressed or relatively under-stressed by uniformly applying a stress when a semiconductor memory is tested. 
   The disclosed device provides a semiconductor memory test device in which a constant supply voltage is applied to cells and snc corresponding to the entire wordlines to consistently apply a uniform stress to them. This technique stresses devices in the way a sense amplifier is controlled depending on an additional sense amplifier driving signal to enable all the wordlines and the sense amplifier drives bit lines bl, /bl with HIGH and LOW, respectively, when a  2 rb pattern stress is applied. 
   Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all embodiments of the teachings of the invention fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.