Abstract:
Disclosed are a capacitor for semiconductor capable of increasing storage capacitance as well as preventing leakage current and a method of manufacturing the same. According to the present invention. A lower electrode is formed on a semiconductor substrate. The surface of the lower electrode is surface-treated so as to prevent a natural oxide layer from generating on the surface thereof. A (TaO) 1−x (TiO)N layer as a dielectric is deposited on the upper part of the lower electrode. Afterwards, to crystallize the (TaO) 1−x (TiO)N layer, a thermal-treatment is performed. Next, an upper electrode is formed on the upper part of the (TaO) 1−x (TiO)N layer.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device capable of increasing the storage capacitance as well as preventing leakage current and a method of manufacturing the same.  
         BACKGROUND OF THE INVENTION  
         [0002]    As the number of memory cells composing DRAM semiconductor device has been recently increased, occupancy area of each memory cell is gradually decreased. Meanwhile, capacitors formed in the respective memory cells require a sufficient capacitance for precise reading out of storage data. Accordingly, the current DRAM semiconductor device requires memory cells in which capacitors having larger capacitance as well as occupying small area are formed. The capacitance of a capacitor can be increased by using an insulator having high dielectric constant as a dielectric layer, or by enlarging the surface area of a lower electrode. In a highly integrated DRAM semiconductor device, a Ta 2 O 5  layer having a higher dielectric constant than that of the nitride-oxide(NO) is now used as a dielectric, thereby forming a lower electrode of a 3-Dimentional structure.  
           [0003]    [0003]FIG. 1 is a cross-sectional view showing a capacitor for a conventional semiconductor memory device. Referring to FIG. 1, a gate electrode  13  including a gate insulating layer  12  at a lower portion thereof is formed according to a known technique on the upper part of a semiconductor substrate  10  which a field oxide layer  11  is formed at a selected portion thereof. A junction region  14  is formed on the semiconductor substrate  10  at both sides of the gate electrode  13 , thereby forming an MOS transistor. A first interlayer insulating layer  16  and a second interlayer insulating layer  18  are formed on the upper part of the semiconductor substrate  10  which the MOS transistor is formed therein. A storage node contact hole h is formed inside the first and the second interlayer insulating layers  16 , 18  so that the junction region  14  is exposed. A cylinder type lower electrode  20  is formed according to a known method, inside the storage node contact hole h so as to be in contact with the exposed junction region  14 . A HSG(hemi-spherical grain) layer  21  is formed on a surface of a lower electrode  20  to increase the surface area of the lower electrode  20  more. A tantalum oxide layer  23  is formed on the surface of the HSG layer  21 . Afterwards, the Ta 2 O 5  layer  23  is deposited on the upper part of the lower electrode  20  including the HSG layer  21  by using an organic metal precursor such as Ta(OC 2 H 5 ) 5 . Afterwards, the Ta 2   0   5  layer  23  is thermal-treated at a selected temperature so as to crystallize. An upper electrode  25  is formed of a polysilicon layer or a metal layer doped on the upper part of the Ta 2 O 5 , layer  23 .  
           [0004]    However, a difference in the composition rate of Ta and O is generated since the Ta 2 O 5  layer  23  generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms are generated in a thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated.  
           [0005]    Now, a process for oxidizing the Ta 2 O 5  layer has been additionally performed to remove the substitutional Ta atoms therein. However, when performing this oxidizing process, an oxide reaction of the Ta 2 O 5  layer with the upper and the lower electrodes actively progresses. As a result, an oxide layer having a low dielectric constant is formed on the interface between the Ta 2 O 5  layer and the lower electrode or the upper electrode, thereby deteriorating the homogeneity of the interface and increasing the thickness of an effective oxide layer as well as manufacturing process steps.  
           [0006]    Moreover, since the Ta 2 O 5  layer is formed by a reaction between an organic tantalum precursor containing carbon components and oxygen, reaction impurities such as carbon atoms (C), carbon compounds(CH 4 , C 2 H 4 ), and H 2 O remain therein after the deposition process. These reaction by-products cause leakage current and deteriorate the dielectric strength of the Ta 2 O 5  layer.  
           [0007]    To remove these reaction by-products, the Ta 2 O 5  layer has been conventionally deposited more than  2  layers, at least. And, after each deposition step, a plasma treatment or UV-O 3  process has been additionally performed to remove reaction by-products inside the Ta 2 O 5  layer. However, the above method has a demerit of increase in the number of the processes.  
         SUMMARY OF THE INVENTION  
         [0008]    Accordingly, it is one object of the present invention to provide a capacitor for a semiconductor memory device with a dielectric layer having low leakage current and high dielectric constant.  
           [0009]    Furthermore, the other object of the present invention is to provide a method of manufacturing a capacitor for a semiconductor memory device capable of simplifying manufacturing process thereof.  
           [0010]    To achieve the foregoing objectives, a capacitor for a semiconductor memory device of the present invention according to one aspect includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper part of the dielectric layer, wherein the dielectric layer is a (TaO) 1−x (TiO)N layer.  
           [0011]    Further, the present invention according to another aspect provides a method of manufacturing a capacitor of a semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; depositing a (TaO) 1−x (TiO)N layer as a dielectric layer on the upper part of the lower electrode; and forming an upper electrode on the upper part of the (TaO) 1−x (TiO)N layer.  
           [0012]    And, the present invention according to still another aspect provides a method of manufacturing a capacitor of a semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; surfacetreating to prevent a natural oxide layer from generating on the surface of the lower electrode; depositing the (TaO) 1−x (TiO)N layer as a dielectric on the upper part of the lower electrode; diffusing and simultaneously crystallizing impurities inside the (TaO) 1−x (TiO)N layer; and forming an upper electrode on the upper part of the (TaO) 1−x (TiO)N layer, wherein the (TaO) 1−x (TiO)N layer is formed by a surface chemical reaction of Ta chemical, Ti chemical vapor, NH 3  gas and O 2  gas in an LPCVD chamber maintaining a temperature of 300 to 600° C. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 is a cross-sectional view of a conventional capacitor for a semiconductor memory device.  
         [0014]    [0014]FIGS. 2A to  2 D are cross-sectional views of respective processes for describing the method of manufacturing a capacitor for a semiconductor device according to the embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]    Referring to FIG. 2A, a field oxide layer  31  is formed according to a known method at a selected portion of a semiconductor substrate  30  having a selected conductivity. A gate electrode  33  having a gate insulating layer  32  at a lower portion thereof is formed at a selected portion on the upper part of the semiconductor substrate  30 , and a spacer  34  is formed according to a known method at both side-walls of the gate electrode  33 . A junction region  35  is formed at both sides of the semiconductor substrate  30  on the gate electrode  33 , thereby forming an MOS transistor. A first interlayer insulating layer  36  and a second interlayer insulating layer  38  are formed on the semiconductor substrate  30  which the MOS transistor is formed therein. Afterward, the second and the first interlayer insulating layers  38 ,  36  are patterned so that a portion of the junction region  35  is exposed, thereby forming a storage node contact hole H. A lower electrode  40  of cylinder type or stack type is formed to be in contact with the exposed junction region  35 . An HSG layer  41  for enlarging the surface area of the lower electrode  40  is formed according to a known method on the surface of the lower electrode  40 .  
         [0016]    Afterward, to restrain the generation of a low dielectric natural oxide layer at an interface of the lower electrode  40  having the HSG layer  41  and a dielectric layer to be formed later(not shown), the lower electrode  40  having the HSG layer  41  and the second interlayer insulating layer  38  are surface-treated. Herein, the surface-treatment can be performed in various methods. As one among the methods, a thermal treatment is performed in situ by using plasma in a low pressure chemical vapor deposition(LPCVD) chamber under NH 3  gas or N 2 /H 2  gas atmosphere at temperature of 300˜600° C. Further, as another method, the RTN is performed at temperature of 500˜1000° C. under NH 3  gas atmosphere, or a furnace treatment is performed under the same conditions as above. As an additional method, the surface of the lower electrode  40  is cleaned by HF vapor, HF solution or compounds containing HF. At this time, before or after the cleaning step, an extra interface-treating step can be performed by NH 4   0 H solution or H 2 SO 4  solution. In addition to the interface-treating step, also a thermal process can be performed under N 2 O or O 2  gas atmosphere, thereby improving the structural defects as well as the structural heterogeneity due to the dangle bonds on the lower electrode surface. As a result, generation of the natural oxide layer is restrained. Herein, when the thermal process, the RTN or the furnace treatment using plasma under NH 3  gas atmosphere is performed, a silicon nitride layer  42  is naturally formed on the upper parts of the lower electrode  40  having the HSG layer  41  and the second interlayer insulating layer  38 . In addition, when the silicon nitride layer is not formed naturally by the surface treatment, a silicon nitride layer  42  for restraint of the natural oxide layer is artificially deposited on the upper parts of the lower electrode  40  having the HSG layer  41  and the second interlayer insulating layer  38 .  
         [0017]    Referring to FIG. 2B, as a dielectric, a (TaO) 1−x (TiO)N layer  43  (0.01≦×≦0.09) is formed on the upper part of the silicon nitride layer  42  and in an LPCVD chamber maintaining a temperature of 300 to 600° C. by a chemical reaction of Ta chemical vapor, Ti chemical vapor, NH 3  gas and O 2  gas. Herein, Ta chemical vapor is obtained by quantifying a precursor such as Ta(OC 2 H 5 ) 5 (tantalum ethylate), Ta(N(CH 3 ) 2 ) 5 (penta-dimethyl-amino-tantalum) and then evaporating in an evaporation tube maintaining a temperature of 140 to 220° C. and Ti chemical vapor is obtained by quantifying a precursor such as Ti[OCH(CH 3 ) 2 ] 4 (tantalum isopropylate), TiCl 4 , TDMAT(tetrakis-dimethylamido-Ti), TDEAT(tetrakis-diethlamido-Ti) and evaporating in an evaporation tube maintaining a temperature of 200 to 300° C. At this time, Ta chemical vapor and Ti chemical vapor are supplied so that mole ratio of Ti/Ta is 0.01 to 1 and NH 3  gas and O 2  gas are respectively supplied in the range of 10 to 1000 sccm. When forming the (TaO) 1−x (TiO)N layer  43 , a gas phase reaction inside the chamber is restrained to a maximum extent while a chemical reaction is generated only on a wafer surface. In addition, the (TaO) 1−x (TiO)N layer  43  is formed to the thickness of approximately 80 to 150 Å.  
         [0018]    Afterward, as shown in FIG. 2C, to crystallize the (TaO) 1−x (TiO)N layer  43  in an amorphous state and to outward-diffuse reaction by-products therein, the (TaO) 1−x (TiO)N layer  43  is annealed by the RTP or a furnace at a temperature of 550˜950° C. under a N 2 O(O 2  or N 2 ) gas atmosphere for 30 seconds to 30 minutes. As a result, the (TaO) 1−x (TiO)N layer  43  in the amorphous state is converted into a crystalline (TaO) 1−x (TiO)N layer  43   a , thereby improving dielectric constant and outward-diffusing the remaining reaction by-products therein. Therefore, the source of leakage current is removed.  
         [0019]    Then, as shown in FIG. 2D, an upper electrode  45  is formed on the upper part of the crystallized (TaO) 1−x (TiO)N layer  43   a . Herein, the upper electrode  45  can be made of a doped polysilicon layer or a metal layer. When the metal layer is used for the upper electrode  45 , one among TiN, TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2 , and Pt is selected. When the metal layer can be formed according to a method among LPCVD, PECVD and RF magnetic sputtering methods.  
         [0020]    As discussed above in detail, the followings are effects of using the (TaO) 1−x (TiO)N layer as a dielectric.  
         [0021]    First, the (TaO) 1−x (TiO)N layer has high dielectric constant of more than  40 , and can be applied to a capacitor of a large capacitance. And, the (TaO) 1−x (TiO)N layer is covalent-bonded to TiO 2  having a grid structure of structurally-stable tetragonal system, thereby obtaining excellent mechanical and electric strengths as well as a stable structure.  
         [0022]    Consequently, the (TaO) 1−x (TiO)N layer has an excellent tolerance against external impacts and very low leakage current.  
         [0023]    Furthermore, since the (TaO) 1−x (TiO)N layer has more stable stoichiometry than that of the Ta 2 O 5  layer, an extra low temperature oxidizing process for stabilizing the stoichiometry is not required. Consequently, process steps can be reduced.  
         [0024]    Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of the present invention.