Abstract:
A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

Description:
TECHNICAL FIELD  
       [0001]     This invention relates to amplifier circuits, and, more particularly, to a switched capacitor amplifier circuit that provides higher open-loop gain and improved closed-loop gain accuracy.  
       BACKGROUND OF THE INVENTION  
       [0002]     Switched capacitor amplifiers are compatible with CMOS technology and consequently are therefore frequently used as analog building blocks in CMOS circuits. In general, the design methodology in CMOS amplifiers assumes the use of infinite gain and infinite bandwidth operational amplifiers. However, CMOS amplifiers have a relatively low gain because of the low gain inherent in CMOS devices. The maximum gain of a CMOS switched amplifier, i.e., open circuit gain, is approximately 25, and may be as low as 10. The low gain of CMOS switched amplifiers introduce finite gain error when the gain of the amplifier is assumed to be the ratio of the capacitance of an input capacitance to the capacitance of a feedback capacitor.  
         [0003]      FIG. 1  shows a switched capacitor amplifier  100  having an input capacitor  104  having a capacitance of Cin connected to an inverting input  116  of an operational amplifier  112 , which is assumed to have infinite gain. The amplifier  100  also includes a feedback capacitor  108  having a capacitance of Cfb coupled in series with an NMOS switching transistor  110  between an output  124  of the amplifier  112  and the inverting input  116 . The feedback capacitor  108  forms a closed loop via the transistor  110  to provide feedback from an output terminal  124  of the operational amplifier  112  to the inverting input terminal  116 . A non-inverting input  120  of the operational amplifier is connected to the ground. As a matter of convention, it should be understood that the terms “non-inverting input” terminal and “inverting input” terminal are used with respect to their relationship to a particular output terminal. An amplifier could alternatively be considered to have an “inverting output” terminal and a “non-inverting output” terminal, as one skilled in the art will appreciate. For example, rather than refer to an amplifier as having an inverting input terminal and an output terminal, one could refer to the same amplifier as having an input terminal and an inverting output terminal.  
         [0004]     Another switched NMOS transistor  126  is connected between the input capacitor  104  and an input voltage source  128 . The gates of the transistors  110 ,  126  both receive a Q 1  switching signal so they are both ON at the same time. When the transistors  110 ,  126  are turned ON, the input voltage source  128  is applied to the input capacitor  104 . As a result, the input capacitor  104  is charged since the input terminal  116  is a virtual ground because of the feedback through the capacitor  108 . The capacitor  108  is also charged for that same reason. The capacitor  108  is charged to a voltage Vout that is equal to the product of the voltage −Vin and ratio of the capacitance of the input capacitor  104  to the capacitance of the feedback capacitor  108 .  
         [0005]     A switched NMOS transistor  136  is connected between the input capacitor  104  and the ground, another NMOS transistor  138  is connected between the feedback capacitor  108  and ground, and another NMOS transistor  140  is connected between the output terminal  124  and the inverting input  116 . When the transistors  136 ,  138 ,  140  are ON responsive to a high Q 2  signal applied to their gates, the capacitors  104 ,  108  are discharged to the ground, and the output terminal  124  is reset to zero volts.  
         [0006]     In operation, the Q 1  and Q 2  signals are alternately driven to a high logic level. Therefore, the transistors  110 ,  126  are operated in a complementary manner with the transistors  136 ,  138 ,  140  thereby causing the capacitors  104 ,  108  to be alternately charged and discharged. Periodically discharging the capacitors  104 ,  108  prevents offsets that would otherwise be present at the output terminal  124  of the amplifier  100 .  
         [0007]     In the discussion of the amplifier  100  shown in  FIG. 1 , it was assumed that the open-loop gain of the operational amplifier  112  was infinite. However, a typical CMOS differential amplifier does not have an open-loop gain that even approaches infinity. With an operation amplifier  112  having a more limited open-loop gain, the approximate closed loop gain of the operational amplifier is given by the following equation: 
 
Vout/Vin=− Av /[((1 +Cfb *( Av+ 1))/ Cin )]  (1) 
 
 where Av is the open-loop gain of the operational amplifier. 
 
 If Av is very large, equation (1) can be approximated as follows: 
 
Vo/Vin=− Cin/Cfb   (2) 
 
         [0008]     Thus, as explained above with respect to the amplifier  112  used in the amplifier  100  of  FIG. 1 , if the open-loop gain Av is very large, the closed-loop gain of the amplifier is approximately equal to the ratio of the capacitance Cin of the input capacitor  104  to the capacitance Cfb of the feedback capacitor  108 . However, since CMOS amplifiers invariably do not have high open-loop gain, equation (2) does not provide an accurate result.  
         [0009]     Suppose for example, Av=100 and Cin/Cfb=10. If Av is very large, equation (2) can be used, and Vo/Vin=−10. However, if Av is 10, then, equation (1) provides Vo/Vin =−9. The simplified formula, i.e., equation (2), based on the ratio of the capacitances predicts a gain of 10, but the actual gain from a more accurate analysis using equation (1) predicts a gain of 9. The error, which is the difference in gain, is caused by the low open-loop gain of the CMOS amplifier. If the open-loop gain of the CMOS amplifier could be increased, the error could be eliminated, and the closed-loop gain of the amplifier would be simply the ratio of the input capacitance Cin to the feedback capacitance Cfb given by equation (2). Since the capacitance of capacitors can be controlled fairly precisely during manufacture, the gain of a switched capacitance amplifier could then be precisely controlled.  
         [0010]     Another technique for dealing with the relatively low open-loop gain of CMOS amplifiers is to factor the open-loop gain of the CMOS amplifier into the closed-loop gain using equation (1) to provide the desired level of gain. However, it is fairly impractical to fabricate a CMOS amplifier with a precisely controlled open-loop gain since the gain can vary with process variations. The open-loop gain of a CMOS amplifier can also change with temperature or supply voltage variations. Without a stable value for the open-loop gain of a CMOS amplifier, it is not possibly to use equation (1) to calculate a precise closed-loop gain for a switched capacitor amplifier.  
         [0011]     There are also other approaches that can be used for attempting to provide switched capacitance CMOS amplifiers with stable gain characteristics. However, all of these approaches impose limitations or costs on switched capacitance CMOS amplifiers using these approaches. For example, some approaches result in the use of greatly increased surface area on a die, and other approaches provided somewhat limited performance.  
         [0012]     Accordingly, there is a need for a CMOS amplifier circuit having very high open-loop gain so that the closed-loop gain of a switched capacitor amplifier can be precisely controlled and does not vary with process, supply voltage and temperature variations.  
       SUMMARY OF THE INVENTION  
       [0013]     An amplifier circuit includes a first stage amplifier having an input terminal and an output terminal. The first stage amplifier is configured to operate with positive feedback and therefore has a very high gain. The amplifier circuit also includes a second stage amplifier having an input terminal and an output terminal. The input terminal of the second stage amplifier is coupled to the output terminal of the first stage amplifier. The first stage amplifier and the second stage amplifier together forming an inverting amplifier between the output terminal of the second stage amplifier and the input terminal of the first stage amplifier. The second stage amplifier may have a relatively small amount of gain compared to the gain of the first stage amplifier. A first feedback capacitor is connected between the output terminal of the second stage amplifier and the input terminal of the first stage amplifier. The first feedback capacitor provides negative feedback from the output terminal of the second stage amplifier to the input terminal of the first stage amplifier. The positive feedback of the first stage amplifier may be provided by a capacitor connected between a non-inverting output of the first stage amplifier and the input of the first stage amplifier. Positive feedback may also be provided by connecting a transistor in parallel with an input transistor having a gate that is coupled to the input terminal of the first stage amplifier. The gate of the transistor is then coupled to a non-inverting output terminal of the first stage amplifier. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a schematic diagram of one example of a conventional switched capacitor amplifier.  
         [0015]      FIG. 2  is a schematic diagram of a CMOS switched capacitor amplifier according to one example of the invention.  
         [0016]      FIG. 3A  is a schematic diagram of a CMOS amplifier that can be used in the switched capacitor amplifier of  FIG. 2  or in some other example of the invention.  
         [0017]      FIG. 3B  is a schematic diagram of an equivalent circuit for the CMOS amplifier of  FIG. 3A .  
         [0018]      FIG. 4  is a schematic diagram of another example of a CMOS amplifier that can be used in the switched capacitor amplifier of  FIG. 2  or in some other example of the invention.  
         [0019]      FIG. 5  is a schematic diagram of another example of a CMOS amplifier that can be used in the switched capacitor amplifier of  FIG. 2  or in some other example of the invention.  
         [0020]      FIG. 6  is a schematic diagram of a CMOS switched capacitor amplifier according to another example of the invention.  
     
    
     DETAILED DESCRIPTION  
       [0021]     A switched capacitance CMOS amplifier  200  according to one example of the invention is shown in  FIG. 2 . The amplifier  200  uses a first CMOS amplifier  210 , a second CMOS amplifier  220 , and the same components that were used externally to the amplifiers  210 ,  220  that were used externally of the amplifier  112  in the amplifier  100  shown in  FIG. 1 . In addition, the first CMOS amplifier  210  includes a capacitor  224  having a capacitance of Cc connected between its output  230  and a non-inverting input  234 . An inverting input of the  236  of the amplifier  210  is connected to ground. In operation, the capacitor  224  provides the amplifier  210  with positive feedback, thereby greatly increasing its gain.  
         [0022]     The output  230  of the first CMOS amplifier  210  is connected to an inverting input  240  of the second CMOS amplifier  220 . A non-inverting input  242  of the amplifier  220  is connected to ground. The amplifier  220 , like typical CMOS amplifiers, has a relatively low gain. However, because of the very high gain of the first amplifier  210 , the gain of the two amplifiers  210 ,  220  together is very large. The amplifiers  210 ,  220  can be considered to be a single amplifier having a very large open-loop gain as in the amplifier  100  shown in  FIG. 1 . The amplifier  200  therefore operates in the same manner as explained above for the amplifier  100 , and its closed-loop gain is therefore given by equation (2) as simply −Cin/Cfb, where Cin is the capacitance of the input capacitor  104  and Cfb is the capacitance of the feedback capacitor  108 . As previously explained, it is possible to fabricate the capacitors  104 ,  108  with fairly precise capacitances. Furthermore, the capacitances of these capacitors do not change appreciably with process, supply voltage and temperature variations. As a result, the amplifier  200  has precise, very stable gain characteristics.  
         [0023]     A CMOS amplifier  250  with positive feedback according to one example of the invention is shown in  FIG. 3A . The amplifier includes a pair of differential NMOS input transistors  254 ,  256 , a current sink NMOS transistor  258 , and a pair of PMOS load transistors  261 ,  262  coupled to each other to act as a current mirror. The transistors  254 - 262  are coupled to each other in a conventional manner, and such amplifiers are in common use. The gate of the input transistor  254  serves as a non-inverting input terminal  260  to which an input voltage Vin is coupled through an input capacitor  264  having a capacitance of Cin. (The NMOS switching transistors shown in  FIGS. 1 and 2  have been omitted from  FIG. 3A  in the interest of clarity). The gate of the input transistor  256  serves as an inverting input terminal  266 , which is connected to ground. The transistors  254 ,  260  form a first current path, and the transistors  256 ,  262  form a second current path. The current mirror formed by the transistors  260 ,  262  ensures that the currents through the first and second current paths are equal to each other. The drain of the input transistor  256  serves as an output terminal  268  for the amplifier  250 . A feedback capacitor  270  having a capacitance of Cc is connected between the output terminal  268  and the non-inverting input terminal  260 . The feedback capacitor  270  provides positive feedback to greatly increase the gain of the amplifier  250 .  
         [0024]     An equivalent circuit for the CMOS amplifier  250  of  FIG. 3A  is shown in  FIG. 3B . The voltage between the input terminals  260 ,  266  is labeled Vx, and the voltage at the output terminal  268  is Vo. The input transistor  256  is modeled by a current source  274  providing a current having a magnitude of gm*Vx, where gm is the transconductance of the amplifier  250 . The transistor  262  is modeled by a load resistor  276  having a resistance R L . A second current source  278  provides a relatively small current that can be ignored for the present analysis.  
         [0025]     Without the presence of the feedback capacitor  270 , the voltage Vx would be equal to the input voltage Vin. The voltage Vo would therefore be the product of the current gm*Vin and the resistance R L  of the load resistor  276 , i.e., Vin*gm*R L . The gain of the amplifier  250 , VoNin, would therefore be simply gm*R L .  
         [0026]     With the feedback capacitor  270 , the gain of the amplifier  250  is given by the equation: 
 
Vo/Vin=( gm*R   L   *Cin )/[ Cin−Cc ( gm*R   L −1)]  (3) 
 
         [0027]     It can be seen from Equation 3 that the gain VoNin can become very large if the denominator Cin−Cc(gm*R L −1) becomes very small by making Cin only slightly larger than Cc(gm*R L −1). However, the amplifier  250  is conditionally stable and will not oscillate as long as the value of Cin−Cc(gm*R L −1) does not become too large. Nevertheless, gains of 100 or more are easily achievable.  
         [0028]     An alternative example of a CMOS amplifier  280  that can be used in the switched capacitor amplifier of  FIG. 2  or in some other example of the invention is shown in  FIG. 4 . The amplifier  280  can be thought of as the compliment to the amplifier  250  shown in  FIG. 3A  in that it uses NMOS load transistors  282 ,  284  instead of the PMOS load transistors  261 ,  262  used in the amplifier  250 , and it uses PMOS input transistors  286 ,  288  and a PMOS current source transistor  290  instead of the NMOS input transistors  254 ,  256  and NMOS current sink transistor  258 , respectively, used in the amplifier  250 . However, the amplifier  280  operates in substantially the same manner as the amplifier  250 , and it uses the same input capacitor  264  and the same feedback capacitor  270 .  
         [0029]     Still another example of a CMOS amplifier  300  that can be used in the switched capacitor amplifier of  FIG. 2  or in some other example of the invention is shown in  FIG. 5 . Like the amplifier  250  shown in  FIG. 3A , the amplifier  300  uses a pair of PMOS load transistors  304 ,  306  connected to each other as current mirrors. The amplifier  300  also uses a pair of NMOS input transistors  310 ,  312  and an NMOS current sink transistor  316 . However, unlike the amplifier  250 , in which the output terminal  268  is taken from the drain of the transistor  312 , an output terminal  318  is taken from the drain of the transistor  310 . As a result, the gate of the transistor  310  constitutes an inverting input rather than a non-inverting input as in the amplifier  250  of  FIG. 3A . In the amplifier  300  of  FIG. 5 , positive feedback is provided by connecting an NMOS transistor  320  in parallel with the inverting input transistor  310 . The transistor  320  preferably has a small channel width in comparison to the channel width of the transistor  310 . The gate of the transistor  320  is driven by the drain of the input transistor  312 .  
         [0030]     In operation, an increase in the magnitude Vin of the input voltage decreases the impedance of the input transistor  310 , thereby decreasing the voltage at the drain of the transistor  310 . Consequently, the magnitude Vo of the output voltage decreases. The decreased impedance of the input transistor  310  also causes more current to flow through the first current path formed by the transistors  304 ,  310 . However, because of the current mirror, the current flowing through the second current path formed by the transistors  306 ,  312  must decrease. The impedance of the transistor  306  is essentially constant. As a result, the decreased current flowing through the second current path increases the voltage at the drain of the non-inverting input transistor  312 , which is coupled to the gate of the transistor  320 . The impedance of the transistor  320  then decreases to further decrease the impedance across the input transistor  310 , which further decreases the magnitude Vo of the output voltage. Consequently, the transistor  320  provides the amplifier  300  with positive feedback.  
         [0031]     A specific example of a switched capacitor CMOS amplifier  340  is shown in  FIG. 6 . The amplifier  340  uses as its first amplifying stage the positive feedback CMOS amplifier  250  shown in  FIG. 3A . The amplifier  250  functions in the same manner as previously explained. Therefore, the components have been provided with the same reference numerals, and, in the interest of brevity, an explanation of their function and operation will not be repeated.  
         [0032]     The amplifier  340  includes as its second amplifying stage a unity gain inverting amplifier  344  formed by a PMOS input transistor  348  connected in series with a diode-connected NMOS transistor  350 . The non-inverting output terminal  268  of the amplifier  250  is connected to the gate of the transistor  348 , and an output terminal  354  is taken at the drain of the transistor  348 . As in the other examples, an input capacitor  360  having a capacitance of Cin is connected to the gate of the transistor  254 , and a feedback capacitor  364  having a capacitance of Cfb is connected between the output terminal  354  and the non-inverting input terminal  260 . Insofar as the amplifier  344  is an inverting amplifier, the capacitor  364  provides negative feedback. The gain of the amplifier  250  is given by equation (3) and, since the gain of the amplifier  344  is simply −1, the open-loop gain of the amplifier is given by the equation: 
 
Vo/Vin=−( gm*R   L   *Cin )/[ Cin−Cc ( gm*R   L −1)]  (4) 
 
         [0033]     As previously explained with reference to  FIG. 3A , the gain of the amplifier  250  can be made very large, thereby making the open-loop gain of the amplifier  340  very large. Consequently, the closed-loop gain of the amplifier  340  is essentially equal to Cin/Cc, where Cin is the capacitance of the input capacitor  360  and Cc is the capacitance of the feedback capacitor  364 . The closed-loop gain of the amplifier  340  is therefore substantially insensitive to process, supply voltage and temperature variations.  
         [0034]     In addition to the first stage amplifier  250 , the unity gain inverting amplifier  344 , the input capacitor  360 , and the feedback capacitor  364 , the switched capacitor CMOS amplifier  340  shown in  FIG. 6  uses the same components that were used externally of the amplifier  112  in the amplifier  100  shown in  FIG. 1 . These components operate in the same manner responsive to the Q 1  and Q 2  signals to periodically charge and discharge the input capacitor  360  and the feedback capacitor  364 . However, these components have been omitted from  FIG. 6  in the interest of clarity.  
         [0035]     Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. For example, the amplifier  340  of  FIG. 6  uses the unity gain inverting amplifier  344  as the second amplifying stage of the amplifier  340  because the non-inverting positive feedback amplifier  250  is used as the first amplifying stage of the amplifier  340 . However, if the inverting positive feedback amplifier  300  shown in  FIG. 5  was used as the first amplifying stage of the amplifier  340 , a non-inverting amplifier would be used as the second amplifying stage of the amplifier  340 . Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.