Abstract:
Equipment and methods are disclosed for testing inductively loaded telephone lines for loading irregularities. In brief, immittance magnitude measurements are used to determine the approximate frequencies of the poles and zeros of such a line and then a lossless ladder network comprising series inductors and shunt capacitors is synthesized wherein the pole and zero frequencies of the network are substantially equal to those previously determined. The network inductor values relate to the line loading inductor values while the network capacitor values relate to the distances between the loading inductors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the testing of inductively loaded transmission lines to identify incorrect loading on such lines. 
     2. Description of the Prior Art 
     Insertion of load coils at regular intervals greatly improves the voice-transmitting properties of long twisted-pair cables. The most common loading arrangement in telephone systems places 88 millihenry load coils every 6,000 feet on loops longer than 18,000 feet. Using this arrangement as a basis, there are over five million loaded telephone loops and at least several million loaded trunk facilities in the continental United States. 
     Faulty loading caused by missing or excessive load coils, incorrect spacing of coils, or damaged coils can cause voice transmission to be poorer than if the loop were correctly loaded and in some cases poorer than if the loop were not loaded. The prior art discloses test equipment for identifying such faulty loading. A typical piece of prior art test equipment includes a cathode ray tube for displaying a pattern representing, as a function of frequency, the impedance characteristic of a line under test. At the same time, the tube displays a second pattern which represents, as a function of frequency, the impedance characteristic of a lattice network. This network is made up by the test equipment operator from a kit to cause the second pattern to approximate that of the line under test. When a good match between the two patterns is achieved, then the configuration and values of the network elements are indicative of the composition of the line under test. 
     Although the above-described equipment has been used successfully, it has been found that producing a reasonable match of patterns is time consuming and somewhat of an art. Equipment which produces rapid results with relatively inexperienced operators would permit better overall telephone service. 
     Apparatus and methods which permit incorrect line loading to be identified by relatively inexperienced operators are disclosed in U.S. patent application Ser. No. 787,847, filed on even date herewith by J. T. Peoples. In accordance with the disclosure in that application, phase differentials as a function of frequency of the input immittance of a line under test are produced. The frequencies at which local maximum and minimum values occur in the differentials are detected and a ladder network comprising series connected inductors and shunt connected capacitors is then synthesized wherein the pole and zero frequencies of the network approximate in value those previously detected. The values of the inductors and capacitors of the synthesized network represent the values of the loading inductors and the line spacing between the inductors, respectively. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to reduce the skill and time required to identify the parameters of an inductively loaded transmission line. 
     In accordance with the present invention, the magnitude as a function of frequency of the input immittance of a transmission line is obtained and utilized to approximate the frequencies of the poles and zeros of the immittance. A lossless ladder network comprising series inductors and shunt capacitors is then synthesized with the pole and zero frequencies of the network being substantially equal to those produced with respect to the input immittance of the line. The network inductors are viewed as corresponding to the line inductors while the network capacitors are viewed as related to line spacings between line inductors. 
     Embodiments of the invention include structure which rapidly approximates the line immittance poles and zeros and, furthermore, rapidly synthesizes a ladder network with the resulting capacitor and inductor values being produced on a read-out device. This structure may be readily adapted to give a read-out in the form of line spacings instead of capacitor values by inputting data relative to the capacitance characteristic of the line under test. As a consequence, embodiments of the invention may be utilized by relatively unskilled personnel to quickly obtain data on a loaded line. 
     The data produced by practicing the invention relates to the line under test in an approximate manner because the frequencies produced are only approximations of the true pole and zero frequencies. However, the data is always sufficiently close to identify correctly loaded lines and, furthermore, sufficiently close to identify most types of problems in incorrectly loaded lines. There are cases, however, where incorrectly loaded lines will have zero and pole frequencies so related with respect to one another that an incorrect diagnosis will result. Fortunately, such cases seldom occur and the invention may therefore be advantageously employed. 
     As stated above and discussed in detail hereinafter, the present invention acquires pole and zero frequency information by utilizing input immittance magnitude information. Structure for acquiring frequency information by this approach is less complicated than the structure required for acquiring similar information by the differential phase approach taught by J. T. Peoples in the above referenced patent application. However, the more complex structure of Peoples is useful for diagnosing longer lines and in general a greater percentage of cases than can be diagnosed by the use of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a block diagram of one embodiment of the invention; 
     FIGS. 2 through 4 disclose structure that may be used in the embodiment of FIG. 1; 
     FIG. 5 is a schematic drawing of a first Cauer network; and 
     FIG. 6 shows a line circuit synthesized in accordance with the invention. 
    
    
     DETAILED DESCRIPTION 
     The embodiment of the invention disclosed in FIG. 1 comprises an apparatus 101 for determining the frequencies for system maximum and minimum immittances, a microprocessor 102 connected to apparatus 101 and a read-out device 103 connected to microprocessor 102. 
     Apparatus 101 has an input port for connection to the tip and ring leads of a telephone line 12 which is to be tested. Apparatus 101 has a further input port for securing a START input from microprocessor 102 and three output ports for indicating the time occurrences of peaks and valleys in the measured immittances, the frequencies at which these peaks and valleys occur and, finally, the termination of the operation of apparatus 101. 
     Apparatus 101 of FIG. 1 may take the form of that disclosed in R. S. Hoppough&#39;s copending application, Ser. No. 787,849, filed on even date herewith and reproduced in FIG. 2 hereof. The apparatus depicted by FIG. 2 comprises apparatus 11 connected to telephone line 12 to produce, as a function of frequency, an output directly related to the absolute magnitude of admittance of line 12. This output in turn is applied to a peak and valley detector 13. Finally, a frequency identifying circuit 14 is connected between apparatus 11 and detector 13, to produce indications of the frequencies at which the peaks and valleys occur. 
     Apparatus 11 comprises an admittance measuring apparatus 15 which may take the form of the structure disclosed in R. S. Hoppough&#39;s copending application Ser. No. 700,333, filed on June 28, 1976 now U.S. Pat. No. 4,028,507, and reproduced in FIG. 3 hereof. When using such structure, apparatus 15 receives the output of a variable frequency oscillator 16 and forces the input terminals of line 12 to these output levels. Furthermore, the output of apparatus 15 is related to the current flowing in line 12 as a result of the voltages forced onto line 12. This output is applied to a conventional detector 17 which produces a dc output related to the value of its input. 
     Peak and valley detector 13 may take the form of the structure disclosed in R. S. Hoppough&#39;s copending application Ser. No. 787,848, filed on even date herewith and reproduced in FIG. 4 hereof. That structure comprises an operational amplifier with a bidirectional nonlinear feedback circuit and a capacitor between its inverting input and ground. The nonlinear feedback circuit is nonconductive until voltages of either polarity thereacross exceed a threshold level. The capacitor is charged and discharged by feedback path current whose polarity and magnitude are dictated by the slope of a signal applied to the noninverting input terminal of the operational amplifier. The feedback path current results in a voltage being developed across the feedback path. This voltage is amplified and clipped so as to shift between two levels depending on the polarity of the current, which as mentioned earlier, is dictated by the slope of the signal applied to the operational amplifier noninverting input terminal. When, therefore, an input signal of variable amplitude is applied to the noninverting input terminal, an output signal is produced which shifts between two levels in response to each reversal in the slope of the input signal. The transition between these two levels is extracted by a high-pass filter to indicate peaks and valleys in the input signal. 
     Frequency identifying circuit 14 comprises a wave squarer 18 which produces square waves in response to the sinusoidal output of oscillator 16. The output from wave squarer 18 is applied to both an inverter 19 and an AND gate 20. The output from a clock 21 is also applied to AND gate 20. Positive outputs from wave squarer 18 enable AND gate 20 so that pulse outputs from clock 21 are passed to and counted in a counter 22. The negative output of squarer 18 is inverted by inverter 19 and applied to counter 22 to reset it. The maximum count produced each time by counter 22 is therefore representative of the period of the positive output of squarer 18, which of course is inversely related to the immediate frequency of oscillator 16. A gate 23 is connected to both detector 13 and counter 22 and passes the output of counter 22 when peaks and valleys are detected by detector 13. Outputs thus produced represent the frequencies at which the maximum and minimum values of admittance occur for line 12. 
     When using apparatus 15 of FIG. 3, and detector 13 of FIG. 4, detector 13 produces negative pulses for peaks (local maximum values) and positive pulses for valleys (local minimum values) in the output of detector 17. Gate 23 may then comprise a pair of gates connected in parallel to counter 22 and responsive to the negative and positive pulses, respectively. One of the gates therefore produces frequency information for peaks while the other produces such information for valleys. (As appreciated by those skilled in the art, other configurations may be employed to correlate peak and valley pulses and the output of counter 22.) Peak-produced frequency information is related to the &#34;zeros&#34; of line 12 while valley-produced frequency information is related to the &#34;poles&#34; of line 12. (The opposite relationship exists when using impedance measuring apparatus.) Peak and valley frequency information is of course produced in an alternating order as there must always be a valley between a pair of peaks and a peak between a pair of valleys. 
     Referring back to FIG. 1, microprocessor 102 receives counter output information relating to frequencies and also peak and valley occurrence information for labeling the counter output as either a peak or valley frequency. This procedure is repeated each time a peak or valley is detected. When the frequency sweep is completed, a signal on the READY lead signals microprocessor 102 that the data collecting process is completed and that the process of synthesizing a first Cauer network may begin. These two processes are discussed in detail in the following sections (a) and (b): 
     (a) Numerical Format of the Peak and Valley Frequencies 
     After the frequency sweep is completed, microprocessor 102 has stored in its read/write memory a string of data words, one for each peak or valley. In one embodiment in which an 8080 type of microprocessor is used, each data word contains a 14-bit binary count representing the number of clock cycles (from clock 21) in a half cycle of variable frequency oscillator (VCO) 16 output. With a 4 MHz clock, the maximum and minimum VCO frequencies give the counts shown in Table 1. From the table, it can be seen that when the lower-order bit is omitted, the remaining 13 bits give an adequate representation of the frequencies of interest with a quantizing error of 16 Hz at the 4,000-Hz limit, or a 0.4% error. 
     
                       TABLE 1.______________________________________ COUNTER OUTPUT FOR VCO FREQUENCIES.f(clock) = 4 MHz, Count = f(clock)/2×f(VCO)VCO        Count        CountFrequency (Hz)      (Decimal)    (14-bit binary)______________________________________200        10,000       11 0111 0001 00003,985      502          00 0001 1111 01104,000      500          00 0001 1111 0100______________________________________ 
    
     From the preceding paragraph, it can be seen that the frequencies are obtained by dividing the 14-bit count into another binary constant representing clock frequency. In practice, this calculation and subsequent calculations are made by first converting the numbers to a 32-bit floating point representation having a 24-bit mantissa and an 8-bit exponent. This precision is not needed to calculate peak or valley frequencies, but is necessary for the numerical network synthesis procedure described below. 
     (b) Synthesizing the LC Ladder Network 
     The desired LC ladder network has the form shown in FIG. 5, which is the classical first Cauer ladder network (see, for example, &#34;Introduction to Modern Network Synthesis,&#34; by M. E. Van Valkenburg, J. Wiley &amp; Sons 1960, pages 128-131) having an input impedance ##EQU1## where: n is the number of load coils, 
     s is the imaginary operator j times the radian frequency, 
     k is a scale factor, and 
     z 1  through z n  and p 1  through p n  are the zero and pole frequencies in radians per second. 
     An actual telephone loop cannot, of course, be represented exactly by a lumped, lossless network function of this form, but this simplified model is adequate for locating most loading irregularities. 
     Multiplying the roots in (1) to form polynominals in s, and then inverting gives ##EQU2## 
     A first-Cauer synthesis of the ladder network of FIG. 5 from equation (2) is straightforward, and is explained in the above-cited text. As an example and to demonstrate the operation of microprocessor 102, synthesis of a two load coil example is carried out below using normalized variables, denoted by an underbar, and using frequency in Hertz. The numerical results labeled C 0 ,C 1 ,L 1 , etc. refer directly to the element values in FIG. 5. ##EQU3## 
     One additional piece of data is required to determine element values; that is, to denormalize. A number 88 procedures are possible; one that has been used successfully is to assume that the first load coil is exactly what it should be, as, for example, 88 millihenries. This assumption is a good one for two reasons. First, the load coils are within a few millihenries of their assumed values if they are present, and, secondly, using this known fact avoids having to take additional data such as measuring the magnitude of admittance at a frequency that is not a pole or zero. The latter procedure is to be avoided if at all possible since no magnitude measuring circuits are required otherwise. 
     Denormalization of the element values in the above example by assuming the first load coil is exactly 88 mH is carried out below: 
     
         ______________________________________Normalized                Denormalized______________________________________ ##STR1##                 L.sub.1 =88.0 mH ##STR2##                 L.sub.2 =88.0 mH ##STR3##                 C.sub.0 = 3.026 K feet ##STR4##                 C.sub.1 = 5.979 K feet ##STR5##                 C.sub.2 = 6.003 K feet______________________________________ 
    
     The synthesized network is shown in FIG. 6. Note that a two load coil LC ladder is obtained with cable lengths of 3.026, 5.979, and 6.003 K feet. The conversion from microfarads to kilofeet of cable was accomplished by assuming a cable capacitance of 0.01572 μF per K feet (0.083 μF per mile). 
     In the disclosed embodiment, a microprocessor is disclosed for synthesizing the ladder network. It should be understood that embodiments of the invention are not restricted to the use of microprocessors but instead can be constructed utilizing any apparatus which can perform the synthesizing function.