Abstract:
The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path. Then, the synchronizing signal detection circuit acquires detection positions of synchronizing pulses of the synchronizing signals of every path, selects a synchronizing signal of every path at which a difference in time between each of the detection positions of every path and the predicted detection position is minimal, and sets the selected synchronizing signal as an output synchronizing signal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a synchronizing signal detection circuit which detects a corresponding synchronizing signal from a video signal including synchronizing signals. 
         [0002]    A patent document 1 (Japanese Unexamined Patent Publication No. 2001-275014) has disclosed a video signal processing device which, even though a pedestal level of an analog video signal inputted thereto varies, outputs a digital video signal whose pedestal level is always controlled to a preset black level. Using such a device makes it possible to avoid abnormalities in the hue of a reproduced image. 
         [0003]    Meanwhile, a synchronization failure or error such as video blurring caused by an inability to accurately detect a synchronizing signal contained in a video signal due to the influence of high-frequency noise or the like becomes a problem as well as a problem associated with an abnormality in brightness such as a hue abnormality that causes an abnormality in video reproduction. 
         [0004]      FIG. 1  shows a synchronizing signal detection circuit for a conventional video signal. In the figure, an input video signal S 10  inputted from a video signal input terminal  10  is inputted to an IIR filter unit  11 . The IIR filter unit  11  outputs a video signal S 11  obtained by eliminating high-frequency noise components from the input video signal S 10 . The video signal S 11  is inputted to a synchronizing signal extraction unit  21 , which detects a synchronizing signal contained in the video signal S 11  and outputs it as a synchronizing signal S 21 . 
         [0005]    However, error detection of a synchronizing signal still occurs depending on such related arts. Since the difference in level between effective data and a synchronizing signal is large where, for example, the end of an effective data period of a video signal is terminated at high-brightness data, the synchronizing signal is rounded in its waveform and erroneously detected depending on the effective data when it is caused to pass through an IIR filter. The error detection of the synchronizing signal leads to synchronization errors and becomes the cause of occurrence of video blurring. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention has been made in view of the following problems. It is therefore an object of the present invention to provide a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. 
         [0007]    According to one aspect of the present invention, for attaining the above object, there is provided a synchronizing signal detection circuit which generates an output synchronizing signal, based on a synchronizing pulse detected from an input video signal, comprising detection position predicting means for predicting a detection position of the synchronizing pulse every synchronization cycle peculiar to the input video signal, unnecessary signal eliminating means for supplying the input video signal to a plurality of unnecessary signal eliminating paths in common thereby to eliminate unnecessary signals according to characteristics of the paths every path, thereby obtaining video signals of every path, detection position detecting means for extracting synchronizing signals of every path from the video signals and detecting detection positions of synchronizing pulses of the synchronizing signals, respectively, and output synchronizing signal selecting means for selecting a synchronizing signal of every path at which a difference in time between each of the detection positions of the synchronizing pulses obtained every path and the detection position predicted by the detection position predicting means is minimal and setting the selected synchronizing signal as the output synchronizing signal. 
         [0008]    According to the synchronizing signal detection circuit related to the present invention, there is provided such a configuration that a path for eliminating unnecessary signals according to the state of an input video signal is automatically selected. It is thus possible to detect a synchronizing signal stably. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: 
           [0010]      FIG. 1  is a block diagram showing a conventional synchronizing signal detection circuit; 
           [0011]      FIG. 2  shows a first preferred embodiment and is a block diagram illustrating a configuration of a synchronizing signal detection circuit according to the present invention; 
           [0012]      FIG. 3  is a diagram for describing the manner in which the optimum synchronizing signal is selected in the synchronizing signal detection circuit; 
           [0013]      FIG. 4  shows a second preferred embodiment and is a block diagram illustrating a configuration of a synchronizing signal detection circuit according to the present invention; and 
           [0014]      FIG. 5  is a diagram for describing control operations of a line memory by a memory controller in a video signal processing device. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0015]    Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
       First Preferred Embodiment 
       [0016]      FIG. 2  shows a first preferred embodiment and illustrates a configuration of a synchronizing signal detection circuit according to the present invention. The synchronizing signal detection circuit  1  includes an IIR filter unit  11 , an FIR filter unit  12 , a pedestal level cut unit  13 , an IIR filter unit  14 , a synchronizing signal extraction unit  21 , a predicted detection position counter  31  and an optimum selection unit  41 . 
         [0017]    An input video signal S 10  inputted to the synchronizing signal detection circuit  1  is captured by a video signal input terminal  10 . The video signal input terminal  10  is connected to the IIR filter unit  11 , the FIR filter unit  12  and the pedestal level cut unit  13  and inputs the input video signal S 10  to them in common. The IIR filter unit  11  is provided with an IIR (Infinite Impulse Response) filter. The IIR filter unit  11  outputs a video signal S 11  obtained by performing a predetermined filtering process on the input video signal S 10  thereby to remove or eliminate unnecessary signals such as high-frequency noise components and inputs the same to the synchronizing signal extraction unit  21 . The FIR filter unit  12  is provided with an FIR (Finite Impulse Response) filter. The FIR filter unit  12  outputs a video signal S 12  obtained by performing a predetermined filtering process on the input video signal S 10  thereby to eliminate unnecessary signals such as high-frequency noise components and inputs the same to the synchronizing signal extraction unit  21 . The pedestal level cut unit  13  performs a process for cutting data at which a signal level is greater than or equal to a predetermined pedestal level, on the input video signal S 10  and inputs the so-obtained video signal to the IIR filter unit  14 . The IIR filter unit  14  is provided with an IIR filter. The IIR filter unit  14  outputs a video signal S 13  obtained by performing a predetermined filtering process on the signal inputted from the pedestal level cut unit  13  thereby to eliminate unnecessary signals such as high-frequency noise components and inputs the same to the synchronizing signal extraction unit  21 . 
         [0018]    The synchronizing signal extraction unit  21  extracts synchronizing signals S 21  through S 23  relative to the respective video signals S 11  through S 13  set on a path-by-path basis and inputs detection position signals S 21  through S 23  each indicative of a detected position of a synchronizing pulse on a time base to the optimum selection unit  41 . The synchronizing signals S 21  through S 23  of every path and the detection position signals S 24  through S 26  of every path respectively correspond to one another in a one-to-one relationship. For example, the synchronizing signal S 21  is outputted from the video signal S 11  inputted to the IIR filter unit  11 , and the detection position signal S 24  indicative of the detection position at the synchronizing signal S 21  is outputted. 
         [0019]    The optimum selection unit  41  selects the optimum synchronizing signal out of the synchronizing signals S 21  through S 23 , based on a predicted detection position signal S 31  to be described later and outputs it to the outside as an output synchronizing signal S 41  via a synchronizing signal output terminal  100 . The optimum selection unit  41  inputs a detection position signal S 42  indicative of a detection position of a synchronizing pulse of the output synchronizing signal S 41  to the predicted detection position counter  31 . The predicted detection position counter  31  counts up only a predetermined horizontal synchronizing cycle with the detection position signal S 42  supplied from the optimum selection unit  41  as the reference to predict the position of the next synchronizing signal and inputs the so-obtained predicted position to the optimum selection unit  41  as the predicted detection position signal S 31 . 
         [0020]      FIG. 3  describes the manner in which the optimum synchronizing signal is selected in the synchronizing signal detection circuit. In the present figure, the horizontal axis indicates a time base, and two synchronizing signals # 1  and # 2  are shown by way of example. For example, the synchronizing signal # 1  corresponds to the synchronizing signal S 21  outputted from the IIR filter (refer to  FIG. 2 ), and the synchronizing signal # 2  corresponds to the synchronizing signal S 22  (refer to  FIG. 2 ) outputted from the FIR filter. 
         [0021]    As shown in the figure, the detected or detection positions of two synchronizing signals # 1  and # 2  are determined depending on detection position signals. A predicted detection position defined based on a predicted detection position signal (S 41 ) is compared with these detection positions, whereby differences in time between the two, i.e., the amounts of displacements (S 44 ) are obtained respectively. The synchronizing signal smallest in displacement between the so-obtained amounts of displacements is selected. In the illustrated example, the synchronizing signal # 1  is selected. 
         [0022]    In the first preferred embodiment referred to above, there is provided such a configuration that a path for eliminating unnecessary signals according to the state of the input video signal is selected automatically. It is thus possible to reduce error detection of each synchronizing signal. 
         [0023]    Incidentally, although the three unnecessary signal eliminating paths have been used in the first preferred embodiment, no limitation is imposed on the present invention. 2 through N (where N: positive number) unnecessary signal eliminating paths may be prepared. While the effect of the invention that reduces error detection even by the provision of the two paths is obtained, such a configuration that the optimum one of, preferably, three or more paths is selected produces more effects. It is considered that a path for the FIR filter is effective where its signal is relatively close to a standard signal, whereas a path for the IIR filter is effective at a video signal on which a large quantity of noise are overlaid in a poor electric wave state and at a weak electric field. A path that cuts a pedestal level or more is effective in reducing the amount of bluntness of the input video signal, which is caused by filtering. 
       Second Preferred Embodiment 
       [0024]      FIG. 4  shows a second preferred embodiment and illustrates a video signal processing device including a synchronizing signal detection circuit according to the present invention. The video signal processing device  300  basically includes a synchronizing signal detection circuit  1  having a configuration basically similar to one described in the first preferred embodiment and further includes a selector  51 , a memory controller  61  and a line memory  71 . Parts different from the first preferred embodiment will be explained below. 
         [0025]    A synchronizing signal extraction unit  21  detects synchronizing signals S 21 , S 22  and S 23  and, at the same time, outputs video signals S 21 ′, S 22 ′ and S 23 ′ corresponding to the respective synchronizing signals to the selector  51 . An optimum selection unit  41  selects the optimum one out of the synchronizing signals S 21  through S 23 , based on a predicted detection position signal S 31  and outputs the same to the outside as an output synchronizing signal S 41  via a synchronizing signal output terminal  100 . At this time, the optimum selection unit  41  inputs a select signal S 43  for selecting any of the video signals S 21 ′, S 22 ′ and S 23 ′ to the selector  51  and generates the amount of displacement S 44  indicative of a difference in time between the output synchronizing signal S 41  and the predicted detection position signal S 31 , followed by input to the memory controller  51 . 
         [0026]    The selector  51  inputs a video signal corresponding to the contents of the select signal S 43  to the line memory  71  as a video signal S 51 . Incidentally, the video signal selected out of the video signals S 21 ′, S 22 ′ or S 23 ′ is normally of a video signal corresponding to the synchronizing signal selected as the output synchronizing signal S 41 . Since, however, a pedestallevel-cut video signal does not contain effective data, other video signals are selected. 
         [0027]    The line memory  71  is of a memory which stores the input vided signal S 51  therein by an FIFO system. The line memory  71  reads the video signal S 51  in accordance with a read control signal S 61  outputted from the memory controller  61  and outputs the same to the outside as a video signal S 71  via a video signal output terminal  200 . 
         [0028]    The memory controller  61  generates the read control signal S 61  for giving the starting position of effective data to be read of the video signal S 51  stored in the line memory  71 . The memory controller  61  corrects the amount of difference between the predicted detection position (S 31 ) supplied from the predicted detection position counter  31  and the starting position of the effective data, based on the amount of displacement S 44  outputted from the optimum selection unit  41 . 
         [0029]      FIG. 5  explains control operations of the line memory by the memory controller. In the present figure, the horizontal axis indicates a time base. Different operations are performed depending on the positive and negative of the amount of displacement (S 44 ). 
         [0030]    As shown in  FIG. 5(   a ), a synchronizing signal based on a predicted detection position (S 31 ) is delayed by an amount equivalent to the amount of displacement (S 44 ) where the detected position of output synchronizing signal (S 41 ) exists anterior to the predicted detection position (S 31 ). As shown in  FIG. 5(   b ), the amount of difference between a synchronizing signal based on a predicted detection position (S 31 ) and a read control signal is increased by an amount equivalent to the amount of displacement (S 44 ) where the detected position of selected synchronizing signal exists posterior to a predicted detection position (S 31 ). 
         [0031]    In the second preferred embodiment referred to above, a difference is determined by performing a comparison between a detected position of synchronizing pulse and a predicted detection position, and the amount of difference between a video signal and a synchronizing signal is corrected, thereby to perform a phase correction with respect to the video signal. It is thus possible to reduce image jitters every horizontal synchronizing period and thereby prevent image blurring. 
         [0032]    While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention is to be determined solely by the following claims. 
       DRAWINGS 
       [0033]    
       FIG. 1 
       
         
           
               21  . . . SYNCHRONIZING SIGNAL DETECTION UNIT 
           
         
       
     
         [0035]    
       FIG. 2 
       
         
           
               1  . . . SYNCHRONIZING SIGNAL DETECTION CIRCUIT,  13  . . . PEDESTAL LEVEL CUT UNIT,  21  . . . SYNCHRONIZING SIGNAL EXTRACTION UNIT,  31  . . . PREDICTED DETECTION POSITION COUNTER,  41  . . . OPTIMUM SELECTION UNIT 
           
         
       
     
         [0037]    
       FIG. 3 
       
         
           
             SYNCHRONIZING SIGNAL # 1 , SYNCHRONIZING SIGNAL # 2  AMOUNT OF DISPLACEMENT TIME 
             DETECTION POSITION OF SYNCHRONIZING SIGNAL # 1 ,
           DETECTION POSITION OF SYNCHRONIZING SIGNAL # 2     
         
             PREDICTED DETECTION POSITION 
           
         
       
     
         [0042]    
       FIG. 4 
       
         
           
               1  . . . SYNCHRONIZING SIGNAL DETECTION CIRCUIT,  13  . . . PEDESTAL LEVEL CUT UNIT,  21  . . . SYNCHRONIZING SIGNAL EXTRACTION UNIT,  31  . . . PREDICTED DETECTION POSITION COUNTER,  51  . . . SELECTOR,  61  . . . MEMORY CONTROLLER,  71  . . . LINE MEMORY 
           
         
       
     
         [0044]    
       FIG. 5 
       
         
           
             (a) WHERE SELECTED SYNCHRONIZING SIGNAL EXISTS ANTERIOR TO PREDICTED DETECTION POSITION 
             SYNCHRONIZING SIGNAL 
           
         
       
     
         [0047]    AMOUNT OF DISPLACEMENT DELAY
       (b) WHERE SELECTED SYNCHRONIZING SIGNAL EXISTS POSTERIOR TO PREDICTED DETECTION POSITION   SYNCHRONIZING SIGNAL   DIFFERENCE VALUE   READ CONTROL SIGNAL AMOUNT OF DISPLACEMENT DELAY