Abstract:
A plurality of one-port split lookup tables having alternately stored therein correction data corresponding to input data is provided as a lookup table that has stored therein the correction data corresponding to the input data at predetermined intervals relevant to predetermined higher-order bits. An address generating unit generates addresses for a plurality of the corresponding split lookup tables from the input data. An interpolation arithmetic unit executes interpolation arithmetic with the use of lower-order bits of the input data for readout data read from two lookup tables.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The entire disclosure of Japanese Patent Application No. 2007-265570 filed on Oct. 11, 2007 including specification, claims, drawings, and abstract is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a correction arithmetic circuit that utilizes a lookup table having stored therein correction data corresponding to input data at predetermined intervals relevant to predetermined higher-order bits. 
         [0004]    2. Description of the Related Art 
         [0005]    Conventionally, the gamma correction is executed based on gamma curves when video signals are displayed. The correction using gamma curves utilizes a lookup table. When a lookup table is utilized, a required memory capacity becomes very large if all the correction data corresponding to input data are stored. Therefore, the lookup table has stored therein the correction data for the input data at predetermined intervals. Although the correction data may be read and output if the correction data for the input are saved, the data must be saved and interpolation arithmetic must be executed to acquire video data after the gamma correction if the data are not stored. 
         [0006]    Therefore, two adjacent correction data must be output for one item of input data from the lookup table. As a result, two addresses are generated and adjacent correction data are output for one item of input data. For example, it is assumed that input data have eight bits and that correction data corresponding to the high five bits of the input data are stored in the lookup table. In this case, two addresses are generated, which are an address  1  corresponding to the high five bits of the input data and an address  2  corresponding to a value of the high five bits +1, and correction data of these two addresses are output from the lookup table. 
         [0007]    Therefore, a two-port memory is utilized as the lookup table to acquire two output data by concurrently specifying two addresses. 
         [0008]    Related arts include Japanese Patent Application Laid-Open Publication No. 2005-323137. 
         [0009]    However, since a two-port memory needs a circuit for concurrent access, it is problematic that an area of the lookup table is increased. 
       SUMMARY OF THE INVENTION 
       [0010]    The present invention comprises a lookup table that has stored therein correction data corresponding to input data at predetermined intervals relevant to predetermined higher-order bits, the lookup table having a plurality of one-port split lookup tables having alternately stored therein the correction data corresponding to the input data, an address generating unit that generates addresses for a plurality of the corresponding split lookup tables from the input data, and an interpolation arithmetic unit that executes interpolation arithmetic with the use of lower-order bits of the input data for readout data read from the plurality of the split lookup tables through the generated addresses. 
         [0011]    According to the present invention, since one-port lookup tables are used, an efficient correction arithmetic circuit may be acquired with a smaller area as a whole. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  depicts an overall configuration of a system; 
           [0013]      FIG. 2  depicts a configuration of a gamma correction circuit; 
           [0014]      FIG. 3  depicts contents of a lookup table; 
           [0015]      FIG. 4  depicts an exemplary configuration of another gamma correction circuit; and 
           [0016]      FIG. 5  depicts contents of a lookup table. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0017]    An exemplary embodiment of the present invention will hereinafter be described with reference to the drawings. 
         [0018]      FIG. 1  depicts an overall configuration of a system. An antenna receives television broadcasting, and a tuner  10  receives and processes received electric waves to acquire analogue video signals. An A/D converter  12  converts the analogue video signals into digital video data, which are supplied to a digital video conversion circuit  14 . The digital video conversion circuit  14  executes a process for conversion into data to be supplied to a display panel as well as various processes for contrast, brightness, color balance, etc. 
         [0019]    The output of the digital video conversion circuit  14  is supplied to a gamma correction circuit  16 . The gamma correction circuit  16  performs gamma correction for the supplied video data such that the display on the display panel is recognized as correct gradation by a viewer. The output of the gamma correction circuit  16  is supplied to and displayed by a display panel  18 . 
         [0020]      FIG. 2  depicts a configuration of the gamma correction circuit  16 . Video data (input data) are the output of the digital video conversion circuit  14  and are supplied to an address generating unit  20 . The address generating unit  20  generates two address data (address  1  and address  2 ) based on the input data. The addresses  1  and  2  are supplied to a lookup table. A lookup table  22  includes split lookup tables, which are a first LUT  22   a  and a second LUT  22   b,  and the address  1  and the address  2  are supplied to the first LUT  22   a  and the second LUT  22   b,  respectively. The outputs from the first and second LUTs  22   a  and  22   b  are supplied as two correction data to an interpolation arithmetic unit  24 . 
         [0021]    The input data are also supplied to an interpolation coefficient generating unit  26 . The interpolation coefficient generating unit  26  generates an interpolation coefficient from a value of lower-order bits of the input data and supplies the interpolation coefficient to the interpolation arithmetic unit  24 . The interpolation arithmetic unit  24  executes the interpolation arithmetic based on the two correction data supplied from the lookup table  22  and the interpolation coefficient supplied from the interpolation coefficient generating unit  26  to output interpolated data. 
         [0022]      FIG. 3  depicts the correction data stored in the lookup table  22 . If the input data are eight-bit data, the correction data corresponding to the high-five-bit data are stored in the lookup table  22 . In this example, correction data r 1 , r 2 , r 3 , . . . r 63  corresponding to  0 ,  4 ,  8 ,  12 , . . .  252  of the input data are stored in the lookup table  22 . The even-numbered correction data r 0 , r 2 , . . . corresponding to  0 ,  8 , . . . indicated by  in  FIG. 3  are stored in the first LUT  22   a,  and the odd-numbered correction data r 1 , r 3 , . . . corresponding to  4 ,  12 , . . . indicated by ◯ in  FIG. 3  are stored in the second LUT  22   b.  That is, r 0 , r 2 , r 4 , . . . r 62  are stored in addresses  0 ,  1 ,  2 , . . .  31  of the first LUT  22   a,  and r 1 , r 3 , r 5 , . . . r 63  are stored in addresses  0 ,  1 ,  2 , . . .  31  of the second LUT  22   b.    
         [0023]    The interpolation arithmetic requires two correction data corresponding to two data sandwiching the input data. Therefore, the address generating unit  20  generates the addresses  1  and  2  for the input data as follows. 
         [0024]    (i) If the bit [ 2 ] of the input data is zero, the address 1=the high five bits of the input and the address  2  =the high five bits of the input are defined. 
         [0025]    (ii) If the bit [ 2 ] of the input data is one, the address  2 =the high five bits of the input and the address  1 =the high five bits of the input +1 are defined. 
         [0026]    When such addresses are generated, for example, if the input data are “11”, the input is “00001011”. Therefore, since bit[ 2 ]=0, the address  1 =1 (correction data  1 =r 2 ) and the address  2 =1 (correction data  2 =r 3 ) are defined. In the case of “14”, the input is “00001110”. Therefore, since bit[ 2 ]=1, the address  1 =2 (correction data  1 =r 4 ) and the address  2 =1 (correction data  2 =r 3 ) are defined. 
         [0027]    As above, although the addresses of the first and second LUTs  22   a  and  22   b  are specified by the higher-order bits, the lower-order bit value is used to control whether both addresses are made identical or shifted by one to generate two readout addresses. 
         [0028]    The interpolation coefficient generating unit  26  generates an interpolation coefficient depending on a value of the low three bits. For example, the value may be obtained by dividing a value of the low three bits by “111” or may be approximated through a quadratic curve. The interpolation arithmetic unit  24  divides a difference between two correction data by the interpolation coefficient from the interpolation coefficient generating unit  26  to acquire and output the interpolated data. 
         [0029]    According to the present embodiment, two one-port LUTs  22   a,    22   b  are used. The one-port memory has one port and enables efficient wiring, etc., and providing two one-port memories can make the area smaller. The one-port memories are widely used general-purpose memories, efficiently designed in many cases, and inexpensive. 
         [0030]    The two LUTs  22   a  and  22   b  may efficiently be accessed by only generating addresses in the address generating unit  20  as above. 
         [0031]    Three or more one-port LUTs  22  may also preferably be provided.  FIG. 4  depicts an example of providing four one-port LUT (first to fourth LUTs)  22   a  to  22   d.  In this example, the address generating unit  20  generates addresses of the first to fourth LUTs  22   a  to  22   d  depending on one item of input data. As a result, four gamma-converted correction data close to the one item of input data are acquired from the outputs of the first to fourth LUTs  22   a  to  22   d.  Although linear interpolation is basically performed in the case of interpolation based on two items of data for one input, second-order interpolation is enabled if four items of data exist. For example, if input data are eight-bit and correction data are input every four bits of the input data, the correction data are stored in the first to fourth LUTs  22   a  to  22   d  every four bits of the input data as shown in  FIG. 5 . Therefore, as shown in Table 1 below, corresponding correction data are respectively stored at addresses  0  to  15  determined by the high four bits as shown in Table 1. 
         [0000]    
       
         
               
             
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 The address generating unit 20 generates the following 
               
               
                 addresses in accordance with Table 1. 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                   When a bit [3:2] of the input (which means three bits - 
               
               
                   
                 two bits, assuming that LSB is zero bit) is zero: 
               
               
                   
                   the address of the first LUT 22a = the high four bits 
               
               
                   
                 of the input; 
               
               
                   
                   the address of the second LUT 22b = the high four bits 
               
               
                   
                 of the input; 
               
               
                   
                   the address of the third LUT 22c = the high four bits 
               
               
                   
                 of the input; and 
               
               
                   
                   the address of the fourth LUT 22d = the high four bits 
               
               
                   
                 of the input. 
               
               
                   
                   When a bit [3:2] of the input is one: 
               
               
                   
                   the address of the first LUT 22a = the high four bits 
               
               
                   
                 of the input +1; 
               
               
                   
                   the address of the second LUT 22b = the high four bits 
               
               
                   
                 of the input; 
               
               
                   
                   the address of the third LUT 22c = the high four bits 
               
               
                   
                 of the input; and 
               
               
                   
                   the address of the fourth LUT 22d = the high four bits 
               
               
                   
                 of the input. 
               
               
                   
                   When a bit [3:2] of the input is two: 
               
               
                   
                   the address of the first LUT 22a = the high four bits 
               
               
                   
                 of the input +1; 
               
               
                   
                   the address of the second LUT 22b = the high four bits 
               
               
                   
                 of the input +1; 
               
               
                   
                   the address of the third LUT 22c = the high four bits 
               
               
                   
                 of the input; and 
               
               
                   
                   the address of the fourth LUT 22d = the high four bits 
               
               
                   
                 of the input. 
               
               
                   
                   When a bit [3:2] of the input is three: 
               
               
                   
                   the address of the first LUT 22a = the high four bits 
               
               
                   
                 of the input +1; 
               
               
                   
                   the address of the second LUT 22b = the high four bits 
               
               
                   
                 of the input +1; 
               
               
                   
                   the address of the third LUT 22c = the high four bits 
               
               
                   
                 of the input +1; and 
               
               
                   
                   the address of the fourth LUT 22d = the high four bits 
               
               
                   
                 of the input. 
               
               
                   
                   
               
             
          
         
       
     
         [0032]    The four correction data corresponding to the input data are generated from the first to fourth LUTs  22   a  to  22   d  as a result of the above address generation and are supplied to the gamma interpolation arithmetic unit  24 . Therefore, the gamma interpolation arithmetic unit  24  may perform the interpolation arithmetic with the use of four correction data. If one item of correction data corresponds to the eight-bit input data, only the corresponding data maybe output. Although it is preferable to perform interpolation from four correction data corresponding to two preceding data and two subsequent data adjacent to the input data, the numbers of the preceding and subsequent data may not be the same. 
         [0033]    By changing the readout address depending on a value of the low four bits, i.e., [3-2] bits even if values of the high four bits are the same, four correction data centering on the input data may always be acquired and used to enable the interpolation arithmetic.