Abstract:
An apparatus includes an electrostatic discharge (ESD) protection device configured to protect a circuit from ESD conditions. The protection device includes an emitter region having a first diffusion polarity; a collector region laterally spaced apart from the emitter region, and having the first diffusion polarity; and a barrier region interposed laterally between the emitter region and the collector region while contacting the emitter region. The barrier region has a second diffusion polarity opposite from the first diffusion polarity. The device can further include a base region having the second diffusion polarity, and laterally surrounding and underlying the emitter region and the barrier region. The barrier region can have a higher dopant concentration than the base region, and block a lateral current flow between the collector and emitter regions, thus forming a vertical ESD device having enhanced ESD performance.

Description:
BACKGROUND 
       [0001]    1. Field 
         [0002]    Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to electrostatic discharge protection. 
         [0003]    2. Description of the Related Technology 
         [0004]    Certain electronic circuits can be exposed to overvoltage or undervoltage conditions. The overvoltage or undervoltage conditions can include, for example, electro static discharge (ESD) events arising from the abrupt release of charge from an object or person to an electronic system. 
         [0005]    Such overvoltage or undervoltage conditions can damage electronic circuits or adversely affect the operations of the circuits. Various protection circuits have been developed to provide protection over electronic circuits from overvoltage or undervoltage conditions. 
       SUMMARY 
       [0006]    In one embodiment, an apparatus includes an electrostatic discharge (ESD) protection device configured to protect a circuit from overvoltage and/or undervoltage conditions. The protection device comprises: an emitter region having a first diffusion polarity; and a collector region laterally spaced apart from the emitter region. The collector region has the first diffusion polarity. The protection device further includes a barrier region interposed laterally between the emitter region and the collector region. The barrier region laterally contacts at least a portion of the emitter region, and has a second diffusion polarity opposite from the first diffusion polarity. The protection device also includes a base region having the second diffusion polarity. The base region laterally surrounds and underlies the emitter region and the barrier region, wherein the barrier region has a higher dopant concentration than the base region. 
         [0007]    In another embodiment, an electronic device comprises an internal circuit electrically coupled to a first power supply rail, a second power supply rail, an input node, and an output node; and a bipolar device electrically coupled to one or more of the first power supply rail, the second power supply rail, the input node, or the output node. The bipolar device comprises: an emitter region having a first diffusion polarity; a collector region laterally spaced apart from the emitter region, the collector region having the first diffusion polarity; and a barrier region interposed laterally between the emitter region and the collector region such that the barrier region blocks a lateral current flow from the collector region to the emitter region during an electrostatic discharge (ESD) event, the barrier region having a second diffusion polarity opposite from the first diffusion polarity. 
         [0008]    In yet another embodiment, a method comprises forming a bipolar protection device comprising: an emitter region having a first diffusion polarity; a collector region laterally spaced apart from the emitter region, the collector region having the first diffusion polarity; a barrier region interposed laterally between the emitter region and the collector region, the barrier region laterally contacting at least a portion of the emitter region, the barrier region having a second diffusion polarity opposite from the first diffusion polarity; and a base region having the second diffusion polarity, the base region laterally surrounding and underlying the emitter region and the barrier region, wherein the barrier region has a higher dopant concentration than the base region. The method also includes forming an internal circuit electrically coupled to the protection device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1A  is a schematic block diagram of an electronic system including an internal circuit and ESD protection circuits according to one embodiment. 
           [0010]      FIG. 1B  is a schematic block diagram of an electronic system including an internal circuit, ESD protection circuits, and ESD diodes according to another embodiment. 
           [0011]      FIG. 1C  is a schematic block diagram of an electronic system including an internal circuit and ESD protection circuits according to yet another embodiment. 
           [0012]      FIG. 2  is a circuit diagram of an ESD protection circuit according to one embodiment. 
           [0013]      FIG. 3  is a graph illustrating a relationship between output current and input voltage of an example ESD protection device. 
           [0014]      FIG. 4A  is a schematic top plan view of a bipolar ESD protection device according to one embodiment. 
           [0015]      FIG. 4B  is a cross-section of the device of  FIG. 4A , taken along the line  4 B- 4 B. 
           [0016]      FIG. 5A  is a schematic top plan view of a bipolar ESD protection device according to another embodiment. 
           [0017]      FIG. 5B  is a cross-section of the device of  FIG. 5A , taken along the line  5 B- 5 B. 
           [0018]      FIG. 5C  is a schematic partial top plan view of a bipolar ESD protection device according to another embodiment. 
           [0019]      FIG. 5D  is a partial cross-section of the device of  FIG. 5C , taken along the line  5 D- 5 D. 
           [0020]      FIG. 6A  is a graph illustrating a leakage current and a relationship between output current and input voltage of the device of  FIG. 4A . 
           [0021]      FIG. 6B  is a graph illustrating a leakage current and a relationship between output current and input voltage of the device of  FIG. 5A . 
           [0022]      FIG. 7A  is a schematic top plan view of a bipolar ESD protection device having a collector ring according to another embodiment. 
           [0023]      FIG. 7B  is a cross-section of the device of  FIG. 7A , taken along the line  7 B- 7 B. 
           [0024]      FIG. 8A  is a schematic top plan view of a bi-directional bipolar ESD protection device according to yet another embodiment. 
           [0025]      FIG. 8B  is a cross-section of the device of  FIG. 8A , taken along the line  8 B- 8 B. 
           [0026]      FIG. 9  is a schematic top plan view of a bipolar ESD protection device according to yet another embodiment. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0027]    The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals indicate identical or functionally similar elements. 
         [0028]    Terms such as above, below, over and so on as used herein refer to a device orientated as shown in the figures and should be construed accordingly. It should also be appreciated that because regions within a semiconductor device (such as a transistor) are defined by doping different parts of a semiconductor material with differing impurities or differing concentrations of impurities, discrete physical boundaries between different regions may not actually exist in the completed device but instead regions may transition from one to another. Some boundaries as shown in the accompanying figures are of this type and are illustrated as abrupt structures merely for the assistance of the reader. In the embodiments described below, p-type regions can include a p-type semiconductor material, such as boron, as a dopant. Further, n-type regions can include an n-type semiconductor material, such as phosphorous, as a dopant. A skilled artisan will appreciate various concentrations of dopants in regions described below. 
         [0000]    Electronic Devices with Electrostatic Discharge Protection 
         [0029]    Referring to  FIG. 1A , an electronic device including an internal circuit and protection circuits according to one embodiment will be described below. The illustrated electronic device  100 A includes a first power supply rail  101 , a second power supply rail  102 , an internal circuit  103 , first to fifth protection circuits  110 - 150 , and first to fourth nodes  161 - 164 . The third node  163  can also be referred to as an “input node.” The fourth node  164  can also be referred to as an “output node.” 
         [0030]    In one embodiment, the protections circuits  110 - 150  are integrated with the internal circuit  103  in a common semiconductor substrate for system-on-a-chip applications. In other embodiments, one or more of the protections circuits  110 - 150  can be placed in a stand-alone IC, in a common package for system-on-a-package applications, and electrically coupled to the internal circuit  103 . 
         [0031]    The first power supply rail  101  is electrically coupled to a first voltage source Vcc, and the second power supply rail  102  is electrically coupled to a second voltage source Vee. In one embodiment, the first voltage source Vcc can provide a voltage between about 2.7 V and about 36 V, for example, about 36 V. The second voltage source Vee provides a voltage between about −18 V and about 0 V, for example, about −18 V or about 0 V. In some embodiments, the first voltage source Vcc and the second voltage source Vee can provide voltages of about 33 V (±10%) and about 0 V (±10%), respectively, for unipolar operation. In other embodiments, the first voltage source Vcc and the second voltage source Vee can provide voltages of about +16.5 V (±10%) and −16.5 V (±10%), respectively, for bipolar operation. 
         [0032]    The internal circuit  103  is electrically coupled to the first and second power supply rails  101 ,  102  at the first and second nodes  161 ,  162 , respectively, to receive power. The internal circuit  103  can include one or more integrated circuits (ICs) having any configurations and functions, which need electrostatic discharge protection. The internal circuit  103  can include an input  103   a  electrically coupled to the third node  163 , and an output  103   b  electrically coupled to the fourth node  164 . In some embodiments, the electronic device can also include a resistor between the third node  163  and the input  103   a,  and/or between the fourth node  164  and the output  103   b  to reduce a current flow to the internal circuit  103  during an ESD event. The internal circuit  103  can receive an input voltage signal V IN  at the input  103   a,  and output an output voltage signal V OUT  at the output  103   b.    
         [0033]    In the illustrated embodiment, the first protection circuit  110  has a first terminal electrically coupled to the third node  163 , and a second terminal electrically coupled to the second node  162 . The first protection circuit  110  can serve to protect the third node  163  coupled to the input  103   a  of the internal circuit  103  from an ESD event occurring between the first node  163  and the second power supply rail  102  (or some other node or pad coupled to the internal circuit  103 ), which has a voltage exceeding that of the first power supply rail  101  and/or an ESD event having a voltage much below the second power supply rail  102 . 
         [0034]    The second protection circuit  120  has a first terminal electrically coupled to the first node  161 , and a second terminal electrically coupled to the second node  162 . The second protection circuit  120  can serve to protect the internal circuit  103  from an ESD event occurring between the first and second power supply rail  101 ,  102 . 
         [0035]    The third protection circuit  130  has a first terminal electrically coupled to the fourth node  164 , and a second terminal electrically coupled to the second node  162 . The third protection circuit  130  can serve to protect the fourth node  164  coupled to the output  103   b  of the internal circuit  103  from an ESD event occurring between the fourth node  164  and the second power supply rail  102  (or some other node or pad coupled to the internal circuit  103 ), which has a voltage exceeding that of the first power supply rail  101  and/or an ESD event having a voltage much below the second power supply rail  102 . 
         [0036]    The fourth protection circuit  140  has a first terminal electrically coupled to the first node  161 , and a second terminal electrically coupled to the third node  163 . The fourth protection circuit  140  can serve to protect the third node  163  from an ESD event occurring between the first node  163  and the first power supply rail  101  (or some other node or pad coupled to the internal circuit  103 ), which has a voltage exceeding that of the first power supply rail  101  and/or an ESD event having a voltage much below the second power supply rail  102 . 
         [0037]    The fifth protection circuit  150  has a first terminal electrically coupled to the first node  161 , and a second terminal electrically coupled to the fourth node  164 . The fifth protection circuit  150  can serve to protect the fourth node  164  from an ESD event occurring between the fourth node  164  and the first power supply rail  101  (or some other node or pad coupled to the internal circuit  103 ), which has a voltage exceeding that of the first power supply rail  101  and/or an ESD event having a voltage much below the second power supply rail  102 . 
         [0038]    Referring to  FIG. 1B , an electronic device including an internal circuit and protection circuits according to another embodiment will be described below. The illustrated electronic device  100 B includes a first power supply rail  101 , a second power supply rail  102 , an internal circuit  103 , first to third protection circuits  110 - 130 , first and second voltage clamp diodes  170   a,    170   b,  and first to fourth nodes  161 - 164 . The details of the components of the electronic device  100 B can be as described above in connection with those of the device  100 A of  FIG. 1A  except that the device  100 B includes the first and second voltage clamp diodes  170   a,    170   b  for the fourth and fifth protection circuits  140 ,  150 , respectively, of the device  100 A of  FIG. 1A . In the context of this document, the term “voltage clamp diode” may also be referred to as an “ESD diode.” 
         [0039]    The first voltage clamp diode  170   a  can have a cathode electrically coupled to the first node  161 , and an anode electrically coupled to the third node  163 . The second voltage clamp diode  170   b  can have a cathode electrically coupled to the first node  161 , and an anode electrically coupled to the fourth node  164 . The voltage clamp diodes  170   a,    170   b  can serve to protect the third node  163  and the fourth node  164  of the internal circuit  103  from an ESD event having a voltage exceeding that of the first power supply rail  101  and/or an ESD event having a voltage much below the second power supply rail  101 , but with a weaker ESD protection than the protection circuits  140  and  150  of  FIG. 1 , which will be described later in connection with  FIG. 2 . In other embodiments, the first voltage clamp diode  170   a  can be coupled in series with one or more additional voltage clamp diodes between the first and third nodes  161 ,  163 . Similarly, the second voltage clamp diode  170   b  can be coupled in series with one or more additional voltage clamp diodes between the first and fourth nodes  161 ,  164 . 
         [0040]    Referring to  FIG. 1C , an electronic device including an internal circuit and protection circuits according to another embodiment will be described below. The illustrated electronic device  100 C includes a first power supply rail  101 , a second power supply rail  102 , an internal circuit  103 , first to third protection circuits  110 - 130 , and first to fourth nodes  161 - 164 . The details of the components of the electronic device  100 B can be as described above in connection with those of the device  100 A of  FIG. 1A  except that the device  100 C does not include the fourth and fifth protection circuits  140 ,  150  of the device  100 A of  FIG. 1A . By having no protection circuit between the first power supply rail  101  and the third node  163  or between the first power supply rail  101  and the fourth node  164 , the input voltage V IN  or output voltage V OUT  can exceed the voltage of the first power supply rail  101 , which can be required in some applications. In an ESD event between the third node  163  and the second power supply rail  102 , a current can flow through the first protection circuit  110  to the second power supply rail  102 , and then through the second protection circuit  120  to the first power supply rail  101 . In yet another embodiment, the electronic device  100 C of  FIG. 1C  can include a protection circuit either between the first power supply rail  101  and the third node  163  or between the first power supply rail  101  and the fourth node  164 . 
       ESD Protection Circuits 
       [0041]    Referring to  FIG. 2 , an ESD protection circuit according to one embodiment will be described below. The illustrated protection circuit  210  includes a bipolar protection device PD and a diode D coupled in parallel between a first node N 1  and a second node N 2 . The protection circuit  210  can form a part or the whole of any of the protection circuits  110 - 150  of the electronic devices  100 A- 100 C of  FIGS. 1A-1C . 
         [0042]    The bipolar protection device PD can have a first terminal T 1  electrically coupled to the first node N 1 , and a second terminal T 2  electrically coupled to the second node N 2 . The diode D can have an anode electrically coupled to the second node N 2 , and a cathode electrically coupled to the first node N 1 . 
         [0043]    The protection device PD can serve to provide protection over an internal circuit when an overvoltage event occurs. In the context of this document, the protection device PD can also be referred to as a “snapback device.” The diode D can serve to provide protection over the internal circuit when an undervoltage event occurs. 
         [0044]    The protection device PD can have operating characteristics, for example, as shown in  FIG. 3 . Ideally, the protection device PD does not pass any current until a trigger voltage V T  is reached. The trigger voltage V T  should be less than a breakdown voltage V B  for an internal circuit being protected. Once the trigger voltage V T  is reached, the protection device PD starts conducting a current, and the voltage across the protection device PD falls back to a holding voltage V H  which is lower than the trigger voltage V T . From the holding voltage V H , ideally a current flow would increase without an increase in the voltage across the protection device PD. Practically, however, due to resistance within the protection device PD, the voltage can increase slightly as the current flow increases in the region  30 . 
         [0045]    The holding voltage V H  should be above the power supply rail voltage (for example, Vcc in  FIGS. 1A-1C ) by, for example, at least about 4 or 5 V, (alternatively, about 10% higher than the power supply rail voltage) in order to accommodate temperature and process variations. Otherwise, once the protection device PD is switched on, it would not switch off. Once the voltage across the protection device PD decreases below the holding voltage V H , the protection device PD can turn off by itself, thereby returning to a high impedance state. 
         [0046]    In one embodiment (for example, in the device of  FIG. 1A ), the first supply voltage can be about 36 V, and the holding voltage V H  of one or more of the protection circuits  110 - 150  can be, for example, about 40V. The breakdown voltage V B  can be, for example, about 69 V. A skilled artisan will appreciate that the characteristic of the protection device PD can vary widely, depending on the configuration and need of the internal circuit  103 . 
         [0000]    ESD Protection Device with Improved ESD Rating 
         [0047]    In one embodiment, an ESD protection device can include a structure similar to a bipolar device, such as a bipolar transistor. Such an ESD protection device can include an emitter region, a base region, a collector region, and a barrier region interposed laterally between the emitter region and the collector region. The barrier region can be doped with the same type of dopant as the base region while having a higher concentration than the base region. The barrier region blocks a current from flowing laterally from the collector region to the emitter region during an ESD event. 
         [0048]    In the ESD protection device, a base-collector breakdown occurrence during an ESD event results in a vertical current flow through the device. In such an instance, a snapback mechanism can be triggered so as to limit the voltage developed in the protection device. A current resulting from the snapback mechanism can be spread over a large junction area between the emitter region and the base region, thereby increasing the ESD rating of the device. Further, the trigger voltage of the device is tunable by simple spacing variations. 
         [0049]    In another embodiment, a collector ring diffusion can be added without affecting the trigger mechanism or the high current carrying capability of the device in snapback. Such a collector ring permits a lower breakdown voltage, a lower trigger voltage, and a less leakage current than without it. 
         [0050]    Generally, the ESD rating of a protection device is inversely proportional to the holding voltage of the protection device. Thus, if the holding voltage is too high, the ESD rating of the device can be too low. However, it is desirable to provide a protection device having a holding voltage higher than the maximum operating voltage of a power supply so that the protection device can turn off at a voltage below the power supply voltage. Further, it is desirable to provide a protection device, of which the trigger voltage can be easily adjusted during fabrication. 
         [0051]    Referring to  FIGS. 4A and 4B , one embodiment of a bipolar protection device will be described below.  FIG. 4A  is a schematic top plan view of the protection device, and  FIG. 4B  is a cross-section of the protection device, taken along the line  4 B- 4 B. The illustrated protection device  400  can form, for example, the protection device PD of  FIG. 2 . 
         [0052]    The protection device  400  shown in  FIGS. 4A and 4B  can be a silicon-on-insulator (SOI) isolated well device. As such, the protection device  400  sits in its own “island” of semiconductor material, which is formed in a well of insulation and is insulated from the devices outside the well on the same monolithic integrated circuit. In this embodiment, a handle wafer  401  acts as a carrier substrate and has a buried oxide layer  402  formed of silicon dioxide on the wafer  401 . 
         [0053]    Trench side walls  403   a - 403   d  are also formed (typically of silicon dioxide) so as to isolate the island of silicon forming the protection device  400  in a well formed by the layer  402  and the side walls  403   a - 403   d.  The process for forming the layer  402  and the side walls  403   a - 403   d  can be a conventional fabrication process. In other arrangements, the well of semiconductor material can be junction isolated. Such a well can be referred to as a well of isolation or insulation. The protection device  400  can include an N buried layer  410 , an N epitaxial layer  420 , an N plug  430 , an N+ emitter region  440 , a P base region  450 , an N+ collector region  460 , an emitter contact  471 , a collector contact  473 , and an insulating layer  480 . In one embodiment, the components of the protection device  400  can be formed by a bipolar process or a BiCMOS process. While illustrated in the context of n-type dopants, the principles and advantages described are applicable to p-type dopants in all the embodiments described in connection with  FIGS. 4A ,  4 B,  5 A- 5 D,  7 A,  7 B,  8 A,  8 B, and  9 . 
         [0054]    The N buried layer  410  is formed on the buried oxide layer  402 , and includes n-type dopants. The N epitaxial layer  420  is a layer epitaxially grown on the N buried layer  410 . The N plug  430  is formed on the N buried layer  410  and is adjacent to the N epitaxial layer  420  such that the N plug  430  is surrounded and contacted by the side walls  403   a,    403   c,    403   d  and the N epitaxial layer  420 . 
         [0055]    The emitter region  440  contains an n-type dopant, forming an n+ region, and is formed in a shallow trench shape. The emitter region  440  can also be referred to as a “first n-region” in the illustrated embodiment. The emitter region  440  has side surfaces and a bottom surface contacting the base region  450  while having a top surface exposed above through an opening in the insulating layer  480 . The emitter contact  471  is formed on at least a portion of the top surface of the emitter region  440 . The emitter contact  471  can serve as the second terminal T 2  of the protection device PD of  FIG. 2 . 
         [0056]    The base region  450  contains a p-type dopant, and is formed in a trench shape. The base region  450  can also be referred to as a “first p-region” in the illustrated embodiment. The base region  450  has outer side surfaces  451  and a bottom surface  452  that contact the N epitaxial layer  420 . The base region  450  also has inner side surfaces  453  and a first top surface  454  that contact the emitter region  440 . The base region  450  further includes a second top surface  455  on which the insulating layer  480  is formed. The base region  450  is floating with no electrical or conductive contact coupled thereto. 
         [0057]    The collector region  460  contains an n-type dopant, and is formed in a trench shape in a top portion of the N plug  430 . The collector region  460  can also be referred to as a “second n-region” in the illustrated embodiment. The collector region  460  has side surfaces and a bottom surface contacting the N plug  430  while having a top surface exposed above through an opening in the insulating layer  480 . The collector contact  473  is formed on at least a portion of the top surface of the collector region  460 . The collector contact  473  can serve as the first terminal T 1  of the protection device PD of  FIG. 2 . 
         [0058]    During operation, when a voltage difference between the emitter contact  471  and the collector contact  473  (the voltage at the emitter contact  471  is lower than the voltage at the collector contact  473 ) reaches a trigger voltage V T1 , a current flows from the collector region  460  to the emitter region  440  through the N plug  430 , the N epitaxial layer  420 , and the P base region  450  in sequence. The current flows through side surfaces of the emitter region  440  and the P base region  450 , which have a smaller area than the bottom surfaces of the regions  440 ,  450 . Thus, the protection device  400  has a relatively small current carrying capability. The arrows shown in  FIG. 4B  represent an electron flow when the current flows. 
         [0059]    The protection device  400  can have operating characteristics as shown in  FIG. 6A . In the illustrated comparative example, the trigger voltage V T1a  of the protection device  400  is about 70 V while the holding voltage V H1a  of the protection device is about 40 V. When the voltage across the protection device  400  reaches the holding voltage V H1a , a current flow can increase while the voltage across the protection device  400  decreases in a region  610   a.    FIG. 6A  also shows that there is a high leakage current in a region  620   a  above about 0.7 A when a pulsed voltage signal is applied to the protection device  400 . This shows that the protection device  400  is subjected to a leakage damage mechanism at or above 0.7 A, and has a relatively small ESD capability. Typically, it is desirable that an ESD device has substantially no leakage current at or below about 1.3 A. 
         [0060]    Referring to  FIGS. 5A and 5B , a bipolar protection device according to another embodiment will be described below.  FIG. 5A  is a schematic top plan view of the protection device, and  FIG. 5B  is a cross-section of the protection device, taken along the line  5 B- 5 B. The illustrated protection device  500  can form, for example, the protection device PD of  FIG. 2 . 
         [0061]    The protection device  500  shown in  FIGS. 5A and 5B  can be a silicon-on-insulator (SOI) isolated well device. As such, the protection device  500  sits in its own “island” of semiconductor material, which is formed in a well of insulation and is insulated from devices outside the well on the same monolithic integrated circuit. In the illustrated embodiment, a handle wafer  501  acts as a carrier substrate and has a buried oxide layer  502  formed of silicon dioxide on the handle wafer  501 . 
         [0062]    The protection device  500  can also include trench side walls  503   a - 503   d,  an N buried layer  510 , an N epitaxial layer  520 , an N plug  530 , an N+ emitter region  540 , a P+ region  545 , a P base region  550 , an N+ collector region  560 , an emitter/base contact  571 , a collector contact  573 , and an insulating layer  580 . Details of the components of the protection device  500  can be as described above with respect to those of the protection device  400  of  FIGS. 4A and 4B  except for the N+ emitter region  540 , the P+ region  545 , the emitter/base contact  571 . 
         [0063]    In one embodiment, the components of the protection device  500  can be formed by a bipolar process or a BiCMOS process simultaneously with other bipolar devices on, for example, a monolithic substrate. In another embodiment, the protection device  500  can be formed as a separate device that is not integrated with the internal circuit  103  that is to be protected. 
         [0064]    The emitter region  540  contains an n-type dopant, forming an n+ region, and is formed in a shallow trench shape. The emitter region  540  can also be referred to as a “first n-region” in the illustrated embodiment. The emitter region  540  has a first side surface  541   a  contacting the P+ region  545 . The emitter region  540  also includes second side surfaces  541   b  and a bottom surface  541   c  contacting the base region  550  while having a top surface exposed above through an opening in the insulating layer  580 . The emitter region  540  has a generally rectangular shape when viewed from above. A portion of the emitter/base contact  571  is formed on at least a portion of the top surface of the emitter region  540 . The emitter/base contact  571  can serve as the second terminal T 2  of the protection device PD of  FIG. 2 . The emitter region  540  can have a lateral dimension or width W E  which extends parallel to the side walls  503   c,    503   d,  as denoted in  FIG. 5A . 
         [0065]    The P+ region  545  contains a p-type dopant, forming a p+ region, and is formed in a shallow trench shape. In the context of this document, the P+ regions  545  can also be referred to as a “barrier region,” “P+ barrier region,” “current barrier region,” “blocking region,” or “current blocking region.” The P+ region  545  has a first side surface  546   a  contacting the first side surface  541   a  of the emitter region  540 . The P+ region  545  also includes second side surfaces  546   b  and a bottom surface  546   c  contacting the P base region  550  while having a top surface exposed above through the opening in the insulating layer  580 . The P+ region  545  has a generally rectangular shape when viewed from above. Another portion of the emitter/base contact  571  is formed on at least a portion of the top surface of the P+ region  545 , shorting the emitter region  540  and the P+ region  545  to each other. In one embodiment, a first distance D 1  between the P+ region  545  and the N+ collector region  560  can be between about 10 μm and 100 μm. In another embodiment, an array of separate emitter/base contacts can be formed in place of the single emitter/base contact  571  of  FIG. 5A . Each of such separate emitter/base contacts can be formed on portions of the emitter region  540  and the P+ region  545 , thereby shorting the emitter region  540  and the P+ region  545 . 
         [0066]    The P+ region  545  can have a lateral dimension or width W P  which extends parallel to the side walls  503   c,    503   d,  as denoted in  FIG. 5A . In one embodiment, the width W P  can be substantially the same as the width W E  of the emitter region  540 . In other embodiments, the width W P  can be about 5% to about 100% of the width W E  of the emitter region  540 . The width W P  can be optionally between about 10% and 70%, or between about 20% and 50%. In one embodiment, the width W P  of the P+ region  545  can be at least about 0.5 μm. A skilled artisan will appreciate that the widths W E  and W P  can vary widely, depending on the configuration of the ESD device. 
         [0067]    The base region  550  contains a p-type dopant in a concentration lower than that of the P+ region  545 , thereby forming a p-region, and is formed in a trench shape. The base region  550  can also be referred to as a “first p-region” in the illustrated embodiment. The base region  550  has outer side surfaces  551  and a bottom surface  552  that contact the N epitaxial layer  520 . The base region  550  also has inner side surfaces  553  and a first top surface  554  that contact the emitter region  540  and the P+ region  545 . The base region  550  further includes a second top surface  555  on which a portion of the insulating layer  580  is formed. The base region  550  can be electrically coupled to the emitter/base contact  571  through the P+ region  545 . 
         [0068]    During operation, when a voltage difference between the emitter contact  571  and the collector contact  573  (the voltage at the emitter/base contact  571  is lower than the voltage at the collector contact  573 ) reaches a trigger voltage V T1b , a current (positive for holes, and negative for electrons) flows from the collector region  560  to the emitter region  540  through the N plug  530 , the N buried layer  510 , the N epitaxial layer  520 , and the P base region  550  in sequence. The arrows shown in  FIG. 5B  represent an electron flow corresponding to the current flow (electrons are negatively charged). 
         [0069]    Further details of the operation of the protection device  500  are as follows. When a positive ESD event occurs to the protection device  500  (for example, a voltage greater than the trigger voltage V T1b  is applied between the collector contact  573  and the emitter/base contact  571 ), a series of breakdown mechanisms occur in the device  500 , which enhance the current sinking capability of the device  500  and limit the voltage that is developed to sink a large amount of transient current. During such a positive ESD event, one mechanism that is triggered is simple impact ionization between the P base region  550  and the collector region  560 . 
         [0070]    During this initial breakdown, a hole current flows from the breakdown site to the P base region  550 , and electrons flow from the same breakdown site through the collector region  560  to the collector contact  573 . The emitter region  540  is defined to be in the path of the hole current travelling through the P base region  550 . 
         [0071]    This pinching of the base region  550  in the current path causes a resistive drop to build up in the base region  550 , leads to a forward biasing of the emitter region  540  and the switching on of the protection device  500  in a form of a vertical bipolar device. The foregoing describes a second mechanism that occurs during the ESD event. 
         [0072]    After the vertical bipolar device switches on, the device  500  can sink more current because of the high gain of the vertical bipolar device. Using an emitter-base resistance rather than a floating base device (such as in the protection device  400  of  FIGS. 4A and 4B ) results in lower passive power dissipation for a protection circuit, which can be desirable for input pin protection in high performance, low input current analog applications. 
         [0073]    As the ESD event becomes severe, the current, which is now flowing by bipolar action from the emitter region  540  to the collector region  560 , attains a sufficiently high density such that a Kirk event is triggered in the N epitaxial layer  520 . A “Kirk” event refers to an event that occurs at high current densities of a current passing through the base-collection region of a bipolar transistor, and causes a dramatic increase in the transit time of the bipolar transistor. The Kirk event allows the voltage to collapse as large ESD events are dealt with, thus preventing an internal circuit from being exposed to large voltages during the event, which would otherwise damage the internal circuit. 
         [0074]    During this Kirk breakdown mechanism, the spacing of the emitter region  540  from the N plug region  530  can establish the ESD rating of the protection device  500 . In one embodiment, the spacing between the emitter region  540  and the N plug region  530  can be greater than a vertical distance between the P base  550  and the N buried layer  510 , which prevents a localized bipolar action in the lateral direction at the side of the emitter region (as in the protection device  400  of  FIGS. 4A and 4B ). 
         [0075]    By directing the current flow through the bottom surface of the emitter region  540 , the P+ region  545  keeps the localized current densities high, and prevents damage that can result from localized heating at a much higher voltage than it otherwise would. Thus, the configuration of the protection device  500  can provide a high ESD rated device. 
         [0076]    The protection device  500  can have operating characteristics as shown in  FIG. 6B . In the illustrated embodiment, the trigger voltage V T1b  of the protection device  500  is about 100 V while the holding voltage V H1b  of the protection device is above 36 V. When the voltage across the protection device reaches the holding voltage V H1b , the current flow increases with a substantially less change to the voltage across the protection device  500  (see the region  610   b  in  FIG. 6B ) than the change of the voltage in the region  610   a  of  FIG. 6A .  FIG. 6B  also shows that there is a leakage current in a region  620   a  above about 3 A when a pulsed signal is applied to the protection device  500 . Thus, the protection device  500  can operate without breakdown at or below 3 A, and has substantially greater ESD capability than the device  400  (see  FIG. 6A ). 
         [0077]    As described above in connection with  FIG. 3 , from the holding voltage V H , ideally a current flow can increase without increasing the voltage across the protection device PD. Thus, the protection device  500  of  FIGS. 5A and 5B  has more ideal characteristics than those of the protection device  400  of  FIGS. 4A and 4B . Further, as the protection device  500  can take more current than the protection device  400  (as shown in  FIGS. 6A and 6B ), the protection device  500  has greater ESD protection over an internal circuit than the protection device  400 . 
         [0078]    Further, Applicants recognized that the trigger voltage V T1b  of the protection device  500  can be adjusted by configuring a second distance D 2  between the P base  550  and the N plug region  530 . For example, the trigger voltage V T1b  of the protection device  500  can be increased by increasing the second distance D 2 . In one embodiment, the second distance D 2  between the P base  550  and N plug region  530  can be between about 10 μm and about 20 μm, for example, about 15 μm. The trigger voltage V T1b  of the protection device  500  can also be adjusted by adjusting a vertical distance between the N+ emitter  540  and the N buried layer  510 , which may require a change to the manufacturing process. Further, the ESD performance of the device  500  can be enhanced by increasing the horizontal area of the emitter region  540 , for example, by increasing the length L E  of the emitter region  540  ( FIG. 5A ). The length L E  is a dimension perpendicular to the width W E . 
         [0079]    Applicants also recognized that the holding voltage V H1b  of the protection device  500  can be adjusted by changing the concentration of p-type dopant in the P+ region  545 . For example, the holding voltage V H1b  of the protection device  500  can be increased by increasing the concentration of p-type dopant in the P+ region  545 . 
         [0080]    Referring to  FIGS. 5C and 5D , in another embodiment, the base/emitter contact  571  of  FIGS. 5A and 5B  can be replaced with an emitter contact  571 ′ which resides only on the emitter region  540 , but not on the P+ region  545 . Other details of the device can be as described above in connection with  FIGS. 5A and 5B . In another embodiment, an array of separate emitter contacts can be formed in place of the single emitter contact  571 ′ of  FIG. 5A . 
         [0000]    ESD Protection Device with a Collector Ring 
         [0081]    Referring to  FIGS. 7A and 7B , a bipolar ESD protection device according to another embodiment will be described below.  FIG. 7A  is a schematic top plan view of the protection device, and  FIG. 7B  is a cross-section of the protection device, taken along the line  7 B- 7 B. The illustrated protection device  700  can form, for example, the protection device PD of  FIG. 2 . 
         [0082]    The protection device  700  shown in  FIGS. 7A and 7B  can be a silicon-on-insulator (SOI) isolated well device formed in a handle wafer  501 . The protection device  700  can also include a buried oxide layer  502 , first to fourth side walls  503   a - 503   d,  an N buried layer  510 , an N epitaxial layer  520 , an N plug  530 , an N+ emitter region  540 , a P+ region  545 , a P base region  550 , an N+ collector ring  760 , an emitter/base contact  571 , a collector contact  573 , and an insulating layer  580 . Details of the components of the protection device  700  can be as described above with respect to those of the protection device  500  of  FIGS. 5A and 5B  except for the collector ring  760 . In one embodiment, the components of the protection device  700  can be formed by a bipolar process or a BiCMOS process. 
         [0083]    The collector ring  760  contains an n-type dopant, forming an n+ region, and is formed in a generally rectangular ring shape when viewed from above the device  700 , as shown in  FIG. 7A . It will be understood that edges of a generally rectangular shape can become rounded during processing. In one embodiment, the collector ring  760  is heavily doped with an n-type dopant. The collector ring  760  can have first to fourth portions  760   a - 760   d  that can together laterally surround a portion of the N plug  530 , a substantial portion of the N epitaxial layer  520 , the emitter region  540 , the P+ region  545 , and the P base region  550 . 
         [0084]    When viewed from above the device  700 , the first side wall  503   a  is on the left, and extends vertically in  FIG. 7A ; the second side wall  503   b  is on the right, and extends vertically in  FIG. 7A ; the third side wall  503   c  is on the top, and extends horizontally in  FIG. 7A ; and the fourth side wall  503   d  is on the bottom, and extends horizontally in  FIG. 7A . 
         [0085]    When viewed from above, the first portion  760   a  is formed in the middle of the N plug  530 , and extends in parallel to the first side wall  503   a  with its opposing end portions having gaps with the third and fourth side walls  503   c,    503   d.  The second portion  760   b  is formed in the N epitaxial layer  520  proximate to the second side wall  503   b,  and extends in parallel to the second side wall  503   b  while having a gap with the second side wall  503   b  and the P base region  550 . 
         [0086]    The second portion  760   b  can have a first spacing S 1  (alternatively, a gap or distance) with the opposing edge of the emitter region  540 , and a second spacing S 2  with the opposing edge of the P base region  550 , as shown in  FIGS. 7A and 7B . A third spacing which is equal to S 1 -S 2  is denoted as S 3  in  FIG. 7B . In one embodiment, the second spacing S 2  can be between about 1 μm and about 4 μm, for example, about 2 μm. The third spacing S 3  can be between about 1 μm and about 7 μm, for example, about 2 μm. 
         [0087]    The third portion  760   c  is formed in a portion of the N plug  530  and a portion of the N epitaxial layer  520  proximate to the third side wall  503   c,  and extends in parallel to the third side wall  503   c  while having a gap with the third side wall  503   c  and the P base region  550 . The fourth portion  760   d  is formed in a portion of the N plug  530  and a portion of the N epitaxial layer  520  proximate to the fourth side wall  503   d,  and extends in parallel to the fourth side wall  503   d  while having a gap with the fourth side wall  503   d  and the P base region  550 . 
         [0088]    As shown in  FIG. 7B , the first and second portions  760   a,    760   b  of the collector ring  760  are formed in a shallow trench shape, and the third and fourth portions  760   c,    760   d  of the collector ring  760  have substantially the same depth as the first and second portions  760   a,    760   b.  The first to fourth portions  760   a - 760   d  can have widths W 1 -W 4 , respectively, that can vary widely, depending on the design of the device  700  while the first portion  760   a  can have the greatest width. 
         [0089]    The collector ring  760 , by having the second portion  760   b  close to the emitter region  540 , can facilitate triggering the initial breakdown. Further, by reducing the spacing S 1  between the second portion  760   b  and the emitter region  540 , the initial breakdown can be triggered at a lower voltage. During the initial breakdown, a current can flow from the second portion  760   b  to the emitter region  540 . Once the initial breakdown is completed (when a forward bias voltage drop is established between the base and emitter regions  550 ,  540 ), the device  700  operates as a vertical device similar to that shown in  FIG. 5B . In addition, the trigger voltage of the device  700  can be easily tuned by selecting the spacing between the second portion  760   b  and the emitter region  540 . In one embodiment, the trigger voltage of the device  700  can be decreased by reducing the second spacing S 2 . In another embodiment, the trigger voltage of the device  700  can be decreased by reducing the third spacing S 3 , to an extent that a vertical current flow from the emitter region  540  is not interfered with. Other details of the operation of the protection device  700  can be as described above with respect to  FIGS. 5A and 5B . The device  700  can have a lower trigger voltage than that of the device  500  of  FIGS. 5A and 5B . 
       Bidirectional ESD Protection Device 
       [0090]    Referring to  FIGS. 8A and 8B , a bi-directional bipolar ESD protection device according to another embodiment will be described below.  FIG. 8A  is a schematic top plan view of the protection device, and  FIG. 8B  is a cross-section of the protection device, taken along the line  8 B- 8 B. 
         [0091]    The protection device  800  shown in  FIGS. 8A and 8B  can be a silicon-on-insulator (SOI) isolated well device formed a handle wafer  801 . The protection device  800  can include a buried oxide layer  802 , and side walls  803 . The protection device  800  includes a first portion  800   a  and a second portion  800   b  within a space enclosed by the buried oxide layer  802  and the side walls  803 . 
         [0092]    The protection device  800  can also include an N buried layer  810 , an N epitaxial layer  820 , an N plug  830 , first and second N+ emitter regions  840   a,    840   b,  first and second P+ regions  845   a,    845   b,  first and second P base regions  850   a,    850   b,  a collector region  860 , first and second emitter/base contacts  871   a,    871   b,  a collector contact  873 , and an insulating layer  880 . The components of the device can be arranged symmetrically with respect to the N plug  830 , and the collector region  860 . 
         [0093]    The first portion  800   a  can include the left portions of the N buried layer  810  and the N epitaxial layer  820 , the N plug  830 , the first N+ emitter region  840   a,  the first P+ region  845   a,  the first P base region  850   a,  the collector region  860 , the first emitter/base contact  871   a,  the collector contact  873 , and the left portion of the insulating layer  880 . The second portion  800   b  can include the right portions of the N buried layer  810  and the N epitaxial layer  820 , the N plug  830 , the second N+ emitter region  840   b,  the second P+ region  845   b,  the second P base region  850   b,  the collector region  860 , the second emitter/base contact  871   b,  the collector contact  873 , and the right portion of the insulating layer  880 . Other details of the components of the first and second portions  800   a,    800   b  can be as described above with respect to those of the protection device  500  of  FIGS. 5A and 5B . 
         [0094]    In one embodiment, the illustrated protection device  800  can form, for example, at least part or the whole of the first and fourth protection circuits  110 ,  140  of  FIG. 1A  or the third and fifth protection circuits  130 ,  150  of  FIG. 1A . In such an embodiment, the collector contact  873  can be electrically coupled to an input or output node  163 ,  164 . The first emitter/base contact  871   a  can be electrically coupled to the first power supply rail  101 , and the second emitter/base contact  871   b  can be electrically coupled to the second power supply rail  102 . 
         [0095]    During operation, the first and second portions  800   a,    800   b  can operate at different triggering conditions. For example, the first portion  800   a  can protect an internal device from an overvoltage condition while the second portion  800   b  can protect the internal device from an undervoltage condition, or vice versa, by turning on either of the first or second portion  800   a,    800   b.  Other details of the operation of each portion  800   a,    800   b  of the protection device  800  can be as described above with respect to  FIGS. 5A and 5B . 
         [0096]    In another embodiment, the first and second portions  800   a,    800   b  can have different dimensions and/or concentrations in the P+ regions  845   a,    845   b  such that the portions  800   a,    800   b  have different triggering voltages and/or holding voltage. In yet another embodiment, one or more of the first and second portions  800   a,    800   b  can include a collector ring, as described above in connection with  FIGS. 7A and 7B . 
         [0000]    ESD Protection Device with an External Resistor 
         [0097]    Referring to  FIG. 9 , a bipolar ESD protection device according to yet another embodiment will be described below. The illustrated protection device  900  can form, for example, the protection device PD of  FIG. 2 . 
         [0098]    The protection device  900  can include a silicon-on-insulator (SOI) isolated well device  900   a  formed in a handle wafer  501 . The SOI isolated well device  900   a  can include a buried oxide layer (not shown in  FIG. 9 , but see the buried oxide layer  502  in  FIG. 5B ), side walls  503 , an N buried layer (not shown in  FIG. 9 , but see the N buried layer  510  in  FIG. 5B ), an N epitaxial layer  520 , an N plug  530 , an N+ emitter region  540 , a P+ region  545 , a P base region  550 , an N+ collector region  560 , a first (or emitter) contact  971   a,  a second (or base) contact  971   b,  a collector contact  573 , and an insulating layer (not shown in  FIG. 9 , but see  580  in  FIG. 5B ). The protection device  900  can further include a resistor  990 , a first interconnect  980   a,  and a second interconnect  980   b.  Details of the components of the protection device  900  can be as described above with respect to those of the protection device  500  of  FIGS. 5A and 5B  except for the first and second contacts  971   a,    971   b,  the resistor  990 , the first interconnect  980   a,  and the second interconnect  980   b.  In one embodiment, the components of the protection device  900  can be formed by a bipolar process or a BiCMOS process. 
         [0099]    Unlike the emitter/base contact  571  of  FIG. 5A , the first and second contacts  971   a,    971   b  are separate, and contacted by the emitter region  540  and the P+ region  545 , respectively. The resistor  990  can be formed outside the SOI isolated well device  900   a.  One end of the resistor  990  is electrically coupled to the first contact  971   a  via the first interconnect  980   a,  and the other end of the resistor  990  is electrically coupled to the second contact  971   b  via the second interconnect  980   b.  The first contact  971   a  can be electrically coupled to a node of an internal circuit, for example, the second node N 2  of  FIG. 2 . The resistor  990  may be in a form of thin film resistor. 
         [0100]    The resistor  990  can serve as a switch to flow small currents therethrough. By having the resistor  990 , a relatively large breakdown current (and consequently collector voltage) is not required to switch on the SOI-isolated well device  900   a,  and snapback. Thus, the protection device  900  can be held near the breakdown voltage of the collector to the emitter with the base shorted to the emitter (in the device shown in  FIGS. 5A and 5B ), and can have a lower trigger voltage than that of the device  500  of  FIGS. 5A and 5B . 
         [0101]    In another embodiment, the protection device can include a collector ring as described above in connection with  FIGS. 7A and 7B . In yet another embodiment, the protection device  900  can be implemented as a bi-directional device, as described above in connection with  FIGS. 8A and 8B . 
       Applications 
       [0102]    Thus, a skilled artisan will appreciate that the configurations and principles of the embodiments can be adapted for any devices that can be protected from over- or under-voltage conditions by the ESD protection devices described above. The ESD protection devices employing the above described configurations can be implemented into various electronic devices or integrated circuits. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipments, etc. Examples of the electronic devices can also include circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, a mobile phone, cellular base stations, a telephone, a television, a computer monitor, a computer, a hand-held computer, a netbook, a tablet computer, a digital book, a personal digital assistant (PDA), a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, a DVR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device can include unfinished products. 
         [0103]    The foregoing description and claims may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected). 
         [0104]    Although this invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above can be combined to provide further embodiments. In addition, certain features shown in the context of one embodiment can be incorporated into other embodiments as well. Accordingly, the scope of the present invention is defined only by reference to the appended claims.