Abstract:
A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Description:
FIELD OF THE INVENTION 
     The present invention is in the field of integrated circuitry as it applies to computerized semiconductor devices and pertains more particularly to methods and apparatus for achieving a symmetric signal propagation delay from input to output in a current mode logic circuit. 
     BACKGROUND OF THE INVENTION 
     A logic gate is an elementary building block of a digital circuit. There are several different types of logic gates. The most basic of these are AND, OR, XOR, NOT, NAND, NOR, and XNOR. Generally speaking, a logic gate is defined by a specific truth table that describes required input condition to produce a specific output condition. Most logic gates have multiple inputs and one output. Of course, every terminal in a logic gate assumes a binary condition either 0 or 1 at any given moment in time during operation. These binary conditions are defined by voltage levels applied to the circuit. For example, a low voltage produces a binary 0 and high voltage produces a binary 1. In most logic ICs there is a definitive on and off state and, therefore, a charge storage time to contend with before terminals change state. 
     A relative recent development in digital logic is known as emitter-coupled-logic (ECL), also known as current-mode-logic (CML). CML is based on the use of a multi-input differential amplifier to amplify and combine the digital signals, and emitter followers to adjust the DC voltage levels. As a result, none of the transistors in the gate ever enter saturation, nor do they ever get turned off completely. The transistors remain entirely within their active operating regions at all times. As a result, the transistors have a much smaller charge storage time to contend with, and can change states much more rapidly. Also the difference between the voltages used to represent the binary values is smaller requiring less charge transfer to change states. Thus, the main advantage of this type of logic gate is extremely high speed. 
     One issue that one must contend with in a CML multi-input logic gate is that there is an unequal propagation state of individual signal inputs to individual signal outputs through a given array of transistors within a circuit. For example, if one input A/{overscore (A)} is changed, the latency to the output of the circuit it will experience will be La. If B/{overscore (B)} is then changed, the latency to output it will experience will be Lb where La≠Lb. This phenomenon is troublesome in various applications such as in phase detection circuits used in phase-locked-loop (PLL) synthesizing. It is well known that a phase detector must quantify phase error of an input signal against a timed reference signal. Latency non-equivalence in propagation from input gates to output of the circuit causes an error in the quantification of phase error. 
     What is clearly needed is a symmetrical transistor structure within a circuit that equalizes latency within a circuit in terms of signal propagation from multiple inputs to output of the circuit. 
     SUMMARY OF THE INVENTION 
     In a preferred embodiment of the present invention, a multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure. 
     In a preferred embodiment, the gate is implemented in current-mode-logic (CML). In one embodiment, the symmetrical structure is an AND structure. In one embodiment, the symmetrical structure is a NAND structure. In one aspect, there are two separate input voltage ranges applied to the gate, the voltage ranges defined as one higher voltage range and one lower voltage range. In this aspect, an even division of the number of signal input leads connected to inputs on the symmetrical structure are operated at the higher voltage range. The remaining number of signal input leads connected to inputs on the symmetrical structure are operated at the lower voltage range. 
     In another aspect of the present invention, a method for producing an equal signal-propagation latency from any input on multiple input, multilevel logic gate to any output on the gate is provided. The method includes the steps of (a) duplicating the asymmetric structure of the standard logic gate once for each possible combination of inputs, (b) providing each input simultaneously on all input ranges, (c) connecting each input to a asymmetric structure so that all variations of connecting the inputs to the structure are represented, and (d) connecting the output leads of the asymmetric structures together so that the asymmetric structures balance one another and provide a combined structure that is symmetric overall. 
     In one aspect of the method, the logic gate is a current-mode-logic (CML) gate. Also in one aspect in step (d), the symmetric structure is an AND structure. In another aspect in step (d), the symmetric structure is a NAND structure. In a preferred application in step (b) there are two separate input voltage ranges applied to the gate, the voltage ranges defined as one higher voltage range and one lower voltage range. 
     In preferred aspects in step (c), an even division of the number of signal input leads connected to inputs on the symmetrical structure are operated at the higher voltage range, and wherein the remaining number of signal input leads connected to inputs on the symmetrical structure are operated at the lower voltage range. In all aspects in step (d), the output of the symmetrical structure is a weighted sum of the outputs of the asymmetrical structures of step (a). 
     Now, for the first time, a symmetrical transistor structure is provided within a circuit that equalizes latency within the circuit in terms of signal propagation from multiple inputs to output of the circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     FIG. 1A is a simple schematic diagram of a portion of a symmetrical logic gate  100  according to an embodiment of the present invention. 
     FIG. 1B is a simple schematic diagram of the remaining portion of the logic gate of FIG.  1 A. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As was previously described in the background section, equivalence in latency from any input to any output in a CML circuit is highly desired for many types of task performance circuits such as a phase detection circuit, for example. Accordingly, is an object of the present invention to provide a symmetrical transistor structure within a CML circuit that will guarantee equivalence in latency for signal propagation within the circuit. 
     FIG. 1A is a simple schematic diagram of a portion of a symmetrical logic gate  100  according to an embodiment of the present invention. CML logic gate  100  is, in this example, an AND gate. Signal inputs for gate  100  are represented at left in universal schematic symbols. These are signal inputs A and {overscore (A)}, inputs B and {overscore (B)}, inputs A 2  and {overscore (A 2 )}, and inputs B 2  and {overscore (B 2 )}. It is known in the art that the bar represents the opposite binary value from the value designated by an input without a bar. Hereinafter in this specification, the signal input pairs will simply be described as input pairs A, B, A 2 , and B 2  with the understanding that the opposite value is represented by a bar over the symbols. It is also noted herein that input pairs A and A 2  represent the same signal and that input pairs B and B 2  represent the same signal. 
     Gate  100  operates at two voltage levels or stages. Signal pairs A and B operate at the higher voltage range while signal pairs A 2  and B 2  operate at the lower voltage range. It will be appreciated by one with skill in the art of CML logic gates that the voltage difference between the higher and lower voltage levels within a voltage range is considerably smaller than in other types of logic gates. Also, the voltage range between high and low for a single signal pair is also considerably smaller than in other types of logic gates wherein a definite on and off state exists in terms of transistor terminal state. 
     FIG. 1B is a simple schematic diagram of the remaining portion of the logic gate  100  of FIG.  1 A. Referring now to FIG. 1B, signal outputs of gate  100  are illustrated as output Q and {overscore (Q)}. Referring now to both FIGS. 1A and 1B, general construction of gate  100  includes a voltage line represented by the schematic symbol vdd extending the entire length of schematic gate  100 . Similarly, a ground line is illustrated along the entire length of schematic gate  100  and labeled with the schematic symbol gnd. Current sources I 32 , I 33 , I 55  and I 51  in FIG. 1A, I 88 , I 66 , I 71 , I 82 , I 58 , and I 76  in FIG. 1B control the currents in each logic structure. In this example, each structure has a resistive load, these resistors are labeled R 2 , R 1 , R 4 , R 5 , R 6 , and R 3  in FIG. 1A, and R 23 , R 24 , R 9 , R 8 , R 16 , R 14 , R 17  and R 18  in FIG.  1 B. 
     Referring now back to FIG. 1A, a symmetrical construction is implemented in this example regarding the first eight transistors represented in gate  100 , namely transistors M 15 , M 14 , M 37 , M 36 , M 19 , M 30 , M 38 , and M 35 . When any input signal voltage is high (1) a transistor is considered on and therefore allowing current to flow between its drain and source as part of a path from vdd to gnd. When an input signal voltage is low, a transistor is considered off breaking the current flow through that transistor. 
     The symmetrical transistor architecture described above is illustrated as enclosed in a dotted rectangle labeled with the element number  103 . The symmetry represented in this architecture is achieved by taking 2 conventional AND structures and connecting their outputs together as described in the method above. In this way the asymmetry of a conventional AND structure is avoided. 
     Each signal input to gate  100  is connected to an input on each structure or transistor pair. For example, input pair A in the highest voltage range of CML gate  100  is connected to inputs of transistors M 15  and M 14  while input pair B in the highest voltage range of CML  100  is connected to inputs of transistors M 37  and M 36 . Pairs A and B enjoy an equal latency from input to output because they are connected to the same input of their respective structures. It is noted herein however that in a prior art circuit, signal pairs A 2  and B 2  represented in the lower voltage range of gate  100  would have a greater latency than pairs A and B because of the necessity of traveling through additional transistors to reach the output. However, in this symmetrical structure the transistor output configuration of input pairs A, B and A 2 , B 2  are constructed such that A and B are mirror images of each other and similarly A 2  and B 2  are mirror images thereby eliminating any un-equivalence in terms of latency of signal propagation from any input to structure  103  to the output of the structure. 
     The transistor structure within box  103  functions to perform the logical operation of an AND gate. Any one input signal into structure  103  enjoys an equal propagation through the structure compared with any other input into structure  103 . The construction method for producing an equal signal-propagation architecture includes duplicating the asymmetric structure of the standard logic gate once for each possible combination of inputs and providing each input simultaneously on all available input ranges. Then each input to a asymmetric structure is connected such that all variations of connecting the inputs to the structure are represented. Finally, all of the output leads of the asymmetric structures are connected together so that the asymmetric structures balance one another and provide a combined structure ( 103 ) that is symmetric overall. 
     The weightings and delays are inherent in the asymmetrical structures before their outputs are connected. Providing each input simultaneously on all available input ranges and connecting each input to the asymmetrical structures so that all possible variations of input connection are represented ensures that all possible weightings and delays are applied to all inputs so that when the outputs of the asymmetric structures are summed by the overall-symmetric structure, the delay from each input to the output is determined by the same weighted sum. 
     An integrated and fixed delay structure is provided by an illustrated array of conventional delay buffers illustrated as transistor pairs M 53 , M 54 ; M 62 , and M 63  of FIG. 1A, and transistor pairs M 89 , M 87 ; M 65 , and M 64  in FIG.  1 B. Referring now to FIG. 1B, signal edge sharpeners are provided for cleaning up the signal output. These cross-coupled structures are identified and labeled as transistor pairs M 80 , M 81 , and M 74 , M 75 . 
     Assuming, for example, that gate  100  is a phase detection circuit used in PLL synthesizing, then there would be no error in quantification of phase error. The accuracy of phase detection with no signal-propagation latency un-equivalencies is greatly improved and can be represented as a straight line on an X, Y line graph. 
     It will be apparent to one with skill in the art of CML logic that the method of the present invention may be expanded to include a wide variety of logic gates where latency un-equivalence in signal propagation poses a problem in task performance. 
     The method and apparatus of the present invention is not limited to the specific embodiments described and can be utilized in existing applications not described or in new applications made possible as a result of the invention. Therefore, the method and apparatus of the present invention should be afforded the broadest possible scope under examination. The spirit and scope of the present invention is limited only by the claims that follow.