Abstract:
A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present invention is a continuation application which claims priority under 35 U.S.C. 120 from Ser. No. 11/799,467 filed on Apr. 30, 2007 entitled “Semiconductor Package Having Dimpled Plate Interconnections” which is in turn a continuation-in-part application of Ser. No. 11/226,913 filed on Sep. 13, 2005 entitled “Semiconductor Package Having Plate Interconnections”, the entire specifications of which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention generally relates to a semiconductor package and more particularly to a semiconductor package having a bridged plate connecting a power semiconductor device source metalized contact and a leadframe source lead. 
         [0003]    Semiconductor devices are conventionally connected to leadframe leads using either plate interconnections or wire bonding. For example, U.S. Pat. No. 5,821,611 discloses a semiconductor device which comprises a first lead having a tip formed with an island, a semiconductor chip unit mounted on the island of the first lead by means of a solder layer and having a plurality of electrode bumps projecting away from the island, and a plurality of additional leads each of which has a tip electrically connected to the electrode bumps via respective solder deposits. The additional leads include at least second and third leads. The leads are alloyed to the electrode bumps in a heating furnace and the solder bumps may spread during heating and create undesirable shapes. 
         [0004]    U.S. Pat. No. 6,040,626 discloses a semiconductor package which employs a mixed connection between a MOSFET top surface comprising a low resistance plate portion for connecting to a source and a wire bond for connecting to a gate. Wire bonding may introduce short circuits in the device due to device dielectric layer damage during the wire bonding process. 
         [0005]    A semiconductor package with directly connected leads is disclosed in U.S. Pat. No. 6,249,041. A semiconductor device includes a semiconductor chip with contact areas on the top or bottom surface. A first lead assembly, formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to one of the contact areas of the semiconductor chip. The first lead assembly also has at least one lead connected to and extending from the lead assembly contact. A second lead assembly, also formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to another one of the contact areas of the semiconductor chip. The second lead assembly also has at least one lead connected to and extending from the lead assembly contact. An encapsulant encloses the semiconductor chip, the lead assembly contact of the first lead assembly and the lead assembly contact of the second lead assembly. The semiconductor device has low electrical and thermal resistance contributions from the package due to the direct connection of the lead assemblies to the chip. The lead assembly contact areas are held in contact with lead contact areas on the semiconductor chip by an electrically conductive adhesive layer. The electrically conductive adhesive layer may be a silver-filled epoxy or polyimide paste or solder bumps. The adhesive layer may be cured in a curing oven, if necessary. The adhesive layer does not include soft solder or solder paste. 
         [0006]    Another semiconductor package with directly connected leads is disclosed in U.S. Pat. No. 6,479,888. A MOSFET comprises a plurality of inner leads electrically connected to a surface electrode of a semiconductor pellet having a field effect transistor on a principal surface thereof. The inner leads are mechanically and electrically connected to the principal surface by a gate connecting portion and source connecting portions constituted by bumps. 
         [0007]    A common problem encountered in the use of patterned plate or clip interconnections is that the plates or clips may float during solder reflow and result in a misaligned interconnection. In some cases, the misalignment results in a short circuit between the source and gate contact areas resulting in low assembly yields. Furthermore, it is difficult to control the required solder volume to prevent this problem. 
         [0008]    Another problem resulting from the use of patterned plate or clip interconnections is the thermal expansion mismatch between the silicon of the semiconductor device and the metal of the patterned plate or clip. The larger the contact area of the patterned plate or clip, the higher the stress induced by the mismatch, which often results in die cracking. To reduce the stress, a smaller plate or clip may be used. However, the smaller contact area may result in higher resistance. 
         [0009]    There is therefore a need in the art for a semiconductor package that includes a semiconductor power device connected to leadframe source and gate leadframe contact areas by means of patterned plates that overcomes the problems of the prior art. There is also a need for a patterned plate interconnection that does not float during solder reflow and ensures precise clip placement and location assurance. There is also a need for a semiconductor package having device metallized areas for restricting the flow of solder during the soldering process. There is also a need for a metalized area formed of Ni/Au. There is also a need for a semiconductor package process that increases throughput and provides easier assembly process control. There is also a need for a semiconductor package method that provides a soft attachment process of the patterned plates onto the semiconductor power device. There is also a need for a semiconductor package having an exposed source plate. There is also a need for a semiconductor package having reduced electrical resistance. There is a further need for a semiconductor package having improved thermal dissipation properties. There is also a need for a semiconductor package having improved mechanical properties. 
       SUMMARY OF THE INVENTION 
       [0010]    The present invention overcomes the limitations of the prior art by providing a semiconductor device package having plate connections between leadframe source and gate contact areas and a power semiconductor power device source and gate metalized areas. The plate connections include dimples positioned to correspond to the source and gate metalized areas. A portion of the source plate may be exposed to allow for improved thermal dissipation. 
         [0011]    In accordance with another aspect of the invention, a semiconductor package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, the dimples being positioned for contact with the metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, the dimple being positioned for contact with the metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads. 
         [0012]    In accordance with yet another aspect of the invention, a semiconductor package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of Ni/Au metalized source areas and a Ni/Au metalized gate area, a patterned source connection having a plurality of dimples formed thereon, the plurality of dimples coupling the source lead to the semiconductor die metalized source areas in corresponding relationship therewith, the patterned source connection being soldered to the semiconductor die metalized source areas, a patterned gate connection having a dimpled formed thereon, the dimple coupling the gate lead to the semiconductor die metalized gate area in corresponding relationship therewith, the patterned gate connection being soldered to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads. 
         [0013]    There has been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof that follows may be better understood, and in order that the present contribution to the art may be better appreciated. There are, of course, additional features of the invention that will be described below and which will form the subject matter of the claims appended herein. 
         [0014]    In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of design and to the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein, as well as the abstract, are for the purpose of description and should not be regarded as limiting. 
         [0015]    As such, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the designing of other methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent methods and systems insofar as they do not depart from the spirit and scope of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is schematic representation of a semiconductor package in accordance with the invention; 
           [0017]      FIG. 2  is a cross sectional view of the semiconductor package of  FIG. 1  taken along line  2 - 2  in accordance with the invention; 
           [0018]      FIG. 3  is a cross sectional view of the semiconductor package of  FIG. 1  taken along line  3 - 3  in accordance with the invention; 
           [0019]      FIG. 3A  is a schematic representation of a patterned gate connection disposed over a metalized gate area in accordance with the invention; 
           [0020]      FIG. 3B  is a schematic representation of a gate lock in accordance with the invention; 
           [0021]      FIG. 3C  is a schematic representation of the semiconductor package of  FIG. 1  showing an alternative metalized gate area in accordance with the invention; 
           [0022]      FIG. 4  is a view in partial section of the semiconductor package of  FIG. 1  in accordance with the invention; 
           [0023]      FIG. 5  is another view in partial section of the semiconductor package of  FIG. 1  in accordance with the invention; 
           [0024]      FIG. 6  is a schematic representation of an alternative embodiment of the semiconductor package in accordance with the invention; 
           [0025]      FIG. 7  is a cross sectional view of the semiconductor package of  FIG. 6  taken along line A-A in accordance with the invention; 
           [0026]      FIG. 8  is a cross sectional view of the semiconductor package of  FIG. 6  taken along line B-B in accordance with the invention; 
           [0027]      FIG. 9  is a view in partial section of the semiconductor package of  FIG. 6  in accordance with the invention; 
           [0028]      FIG. 10  is a schematic representation of an alternative embodiment of the semiconductor package in accordance with the invention; 
           [0029]      FIG. 11  is a cross sectional view of the semiconductor package of  FIG. 10  taken along line A-A in accordance with the invention; 
           [0030]      FIG. 12  is a cross sectional view of the semiconductor package of  FIG. 10  taken along line B-B in accordance with the invention; 
           [0031]      FIG. 13  is a schematic representation of an embodiment of the semiconductor package having dimpled plate interconnections in accordance with the invention; 
           [0032]      FIG. 14  is a cross sectional view of a dimpled source plate of the semiconductor package of  FIG. 13 ; 
           [0033]      FIG. 15  is a cross sectional view of a dimpled gate plate of the semiconductor package of  FIG. 13 ; 
           [0034]      FIG. 16  is a schematic representation of a semiconductor die in accordance with the invention; 
           [0035]      FIG. 17  is a schematic representation of an alternative embodiment of the semiconductor package having dimpled plate interconnections in accordance with the invention; 
           [0036]      FIG. 18  is a cross sectional view of a dimpled source plate of the semiconductor package of  FIG. 17 ; and 
           [0037]      FIG. 19  is a cross sectional view of a dimpled gate plate of the semiconductor package of  FIG. 17 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0038]    The following detailed description is of the best modes of carrying out the invention. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention, since the scope of the invention is best defined by the appended claims. 
         [0039]    The present invention generally provides a semiconductor device package having plate connections between leadframe source and gate contact areas and power semiconductor power device metalized source and gate areas. The metalized source and gate areas are preferably Ni/Au plated or sputtered surfaces. The metalized source and gate areas provide for improved bonding of the plate connections and reduction of overbonding which often introduces short circuit problems due to dielectric layer damage during wire bonding processes. The metalized source and gate areas further eliminate the need for solder bumps and epoxy adhesive layers as soft solder and solder paste may be used to connect the plates to the metalized source and gate areas. 
         [0040]    In a first aspect of the invention and with reference to  FIGS. 1-5 , a semiconductor package generally designated  100  may include a leadframe  105  having a drain contact portion  107 , a source contact portion  110  and a gate contact portion  115 . A power semiconductor die  120  may have a metalized drain area (not shown) coupled to the drain contact portion  107  by solder reflow. 
         [0041]    Semiconductor source and gate metalized areas may be formed by Ni/Au plating or sputtering. With reference to  FIG. 3A , a gate metalized area  160  may be of circular configuration. It has been discovered by the inventors that circular metalized area  160  advantageously restricts the flow of soft solder and solder paste to the confines of the circular metalized area  160  during solder reflow, thereby reducing the incidence of undesirable shapes and short circuits. 
         [0042]    A patterned source plate  125  may include an exteriorly exposed portion  127  and an internal portion  130 . Interior portion  130  may be coupled to source contact portion  110 . Exteriorly exposed portion  127  may be exposed outside of an encapsulant  135 . Patterned source plate  125  may be coupled to the metalized source area by solder reflow using soft solder or solder paste. Metalized source area may cover a substantial portion of a top surface of the die  120  for improved heat dissipation and decreased resistance and inductance. 
         [0043]    A patterned gate plate  137  may connect the metalized gate area  160  to the leadframe gate contact area  115 . The patterned gate plate  137  may include a hole  165  formed at an end  167  thereof. A locking ball  155  may be formed during solder reflow to provide mechanical stability to the patterned gate plate  137  ( FIG. 3B ). In one aspect of the invention, soft solder may be disposed in the hole  165  and allowed to flow through the hole  165  to the metalized gate area  160  during solder reflow. Metalized gate area  160  may provide a bonding surface for the solder which limits the flow of solder to the circular area. 
         [0044]    With reference to  FIG. 3C , an alternative metalized gate area  170  is shown including a cross-shaped area. 
         [0045]    In accordance with another aspect of the invention, and as shown in  FIGS. 6-9 , a semiconductor package generally designated  600  may include a leadframe  605  having a drain contact portion  607 , a source contact portion  610  and a gate contact portion  615 . A power semiconductor die  620  may have a metalized drain area (not shown) coupled to the drain contact portion  607  by solder reflow. 
         [0046]    Semiconductor source and gate metalized areas may be formed by Ni/Au plating or sputtering. A patterned source plate  625  may include an exteriorly exposed portion  627  and an internal portion  630 . Exteriorly exposed portion  627  may be exposed outside of an encapsulant  635 . Patterned source plate  625  may be coupled to the metalized source area by solder reflow using soft solder or solder paste. 
         [0047]    A patterned gate plate  637  may connect the metalized gate area  640  to the leadframe gate contact area. The patterned gate plate  637  may be connected to the metalized gate area  640  by solder reflow to provide mechanical stability to the patterned gate plate  637 . 
         [0048]    In another aspect of the invention and with reference to  FIGS. 10-12 , a semiconductor package generally designated  1000  may include a leadframe  1005  having a drain contact portion  1007 , a source contact portion  1010  and a gate contact portion  1015 . A power semiconductor die  1020  may have a metalized drain area (not shown) coupled to the drain contact portion  1007  by solder reflow. 
         [0049]    Semiconductor source and gate metalized areas may be formed by Ni/Au plating or sputtering. A patterned source plate  1025  may include an exteriorly exposed portion  1027  and an internal portion  1030 . Exteriorly exposed portion  1027  may be exposed outside of an encapsulant  1035 . Patterned source plate  1025  may be coupled to the metalized source area by solder reflow using soft solder or solder paste. 
         [0050]    A patterned gate plate  1037  may connect the metalized gate area  1040  to the leadframe gate contact area. Patterned gate plate  1037  may include a hook portion  1039  for connection to the metalized gate area  1040 . The patterned gate plate  1037  may be connected to the metalized gate area  1040  by solder reflow to provide mechanical stability to the patterned gate plate  1037 . 
         [0051]    The present invention advantageously employs Ni/Au device patterned source, drain and gate metalized areas. Ni/Au provides for improved connection between the patterned source plates and patterned gate plates and allows for a simplified process of source, drain and gate metallization in one Ni/Au process to thereby improve process throughput. 
         [0052]    The Ni/Au process provides for a Ni layer on the metal areas and a Au layer to protect the Ni layer. As Ni does not diffuse into the Al metal area, an inter-metallic layer comprised of Ni/Al provides for a high density layer to which the patterned source and gate connections may be soldered. 
         [0053]    In another aspect of the invention, and with reference to  FIG. 13 ,  FIG. 14 ,  FIG. 15 , and  FIG. 16 , a source plate  1300  includes a plurality of dimples  1310  formed thereon. The dimples  1310  are concave with respect to a top surface  1320  of the source plate  1300  and have bottom surfaces  1315  extending beyond a plane of a bottom surface  1330  thereof. A gate plate  1350  includes a dimple  1360  that is concave with respect to a top surface  1370  of the gate plate  1350  and has a through hole  1365  having an opening  1367  that extends beyond a plane of a bottom surface  1380  thereof. 
         [0054]    Source plate dimples  1310  and the gate plate dimple  1360  are positioned and stamped or punched on the source plate  1300  and the gate plate  1350  so as to align with source metalized areas  1620  and gate metalized area  1630  of semiconductor die  1600  during solder reflow. It has been found that the source plate  1300  is not prone to floating due to the number of distinct source plate dimples  1310  contacting the source metalized areas  1630 . Furthermore, the metalized areas advantageously restrict the flow of soft solder and solder paste to the confines of the metalized areas during solder reflow, thereby reducing the incidence of undesirable shapes and short circuits. The through hole  1367  the gate dimple  1360  allows for the formation of locking balls formed during solder reflow to provide mechanical stability to the gate plate  1350 . 
         [0055]    In another aspect of the invention, and with reference to  FIG. 17 ,  FIG. 18 , and  FIG. 19  a source plate  1700  includes a plurality of dimples  1710  formed thereon. The dimples  1710  are concave with respect to a top surface  1715  of the source plate  1700  and include a through hole  1720  having an opening  1725  formed beyond a plane of a bottom surface  1730  thereof. A gate plate  1750  includes a dimple  1760  that is concave with respect to a top surface  1755  of the gate plate  1750  and includes a through hole  1770  having an opening  1775  formed beyond a plane of a bottom surface  1780  thereof. 
         [0056]    As in the embodiment shown in  FIGS. 13-16 , the source dimples  1710  and the gate dimple  1760  are positioned and stamped or punched on the source plate  1700  and the gate plate  1750  so as to align with source metalized areas  1620  and gate metalized area  1630  of semiconductor die  1600  during solder reflow. The through holes  1720  of the source dimples  1710  and the through hole  1770  of the gate dimple  1760  allow for the formation of locking balls formed during solder reflow to provide mechanical stability to the source and gate plates  1700  and  1750  respectively. Soft solder may be disposed in the source dimples  1710  and the gate dimple  1760  and allowed to flow through the through holes  1720  and  1770  to the metalized source areas  1620  and metalized gate area  1630  respectively during solder reflow. Metalized source areas  1620  and metalized gate area  1630  may provide bonding surfaces for the solder which limits the flow of solder to the metalized areas. 
         [0057]    The present invention advantageously provides for patterned source and gate plate connections having dimples positioned to correspond to source and gate metalized areas. The dimpled source and gate plates ensure that the source and gate plates do not float during solder reflow to thereby ensure precise clip placement and location assurance. 
         [0058]    It should be understood, of course, that the foregoing relates to preferred embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.