Abstract:
In the structure of convention logic/flash memory, this invention provides a novel process to generate some dent, which is used for isolating in following self-alignment silicide process, in some specific location in the substrate, so there will not be short among those produced silicide. Also, during the following of the installation process of borderless contact, this present invention avoids the problem caused by mis-aligned borderless contact. Moreover, the present invention will improve the integration of Very Large Scale Integration (VLSI) structure and no extra special mask layer is needed in the process by using the present invention.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to semiconductor manufacturing in general, and more specifically to a method for providing an improvement of an isolation in a non-volatile memory.  
         BACKGROUND OF THE INVENTION  
         [0002]    Non-volatile memory, which includes Mask Read-only memory(Mask ROM), Programmable Read-only memory(PROM), Erasable Programmable Read-only memory(EPROM), Electrically Erasable Programmable Read-only memory(EEPROM), and Flash memory, can keep its stored information although the electricity supply has been removed, so the Non-volatile memory is used in extensive field in the semiconductor industry. And they are another class of memories that are developed to prevent programmed data from being lost. Typically, the manufacturer or user can program their non-volatile memory based on requirements, and the programmed data can be stored for a long time interval.  
           [0003]    Within the decades, due to the fast growth rate of the IT market, portable computer and the electronic communication industry become the main driving force for the technology of semiconductor VLSI design, so it causes a great demand on low power consume, high density and re-programmable non-volatile memory. These programmable and erasable memories are able to store application programs and working systems, and they become the essential devices in the semiconductor industry.  
           [0004]    When demands rise for more memory function, the requirement of the integration level of a semiconductor is also getting higher. A higher integration level usually represents a requirement of a memory with bigger storage capacity. When there is a novel flash memory developed with the merit of multi-programmable and multi-erasable, the flash memory soon becomes one of the fastest growing new generation memories.  
           [0005]    As FIG. 1 illustrates, it expresses the arrangement of a conventional memory structure, which is a typical Twin Cell flame structure. According to the common-use design rule for preventing in case of misalign of contact  5  manufacturing situation, there have prepared a margin  6  in the surrounding region of contact prepared position during the design stage. If in case of mis-align happens and a contact is not built in the anticipated position, the contact can just be located in these margin  6  regions. Since one of the functions of the margin  6  is isolated, the margin can be a “safety region” for avoiding the electrical short, so, the mis-aligned contact  5  in the margin  6  region does not conduct with nearby device. Due to this characteristic of avoiding short, the entire circuit can have better performance and the saving of margin region is another merit because it can have a better integration in a semiconductor.  
           [0006]    In the process of multi-layer semiconductor circuit, the integration of a semiconductor device increases for a more powerful and better performance device, thus the resistance in drain and in source also increases. When the resistance achieves the equality of the resistance in the semiconductor device channel, the process of self-aligned silicide is usually applied for reducing the sheet resistance of drain and source and assuring the competition of Shallow Junction between the metal and Metal-Oxide-Semiconductor device. Simply speaking, after Titanium sputtering on the surface within this process, Titanium and Silicide react together to form a good conductor by rapid thermal treatment. Some extra Titanium that does not react with silicide is removed by wet etching from the surface. In an ideal situation, TiSi 2  is formed and resided on the surface of drain, source and gate only. In a Twin Cell frame structure such as in FIG. 1, the next close nearby TiSi 2  formed on a memory cell that may interfere and short each other because there is no efficient isolation among them, and it damages a semiconductor&#39;s performance.  
           [0007]    Therefore, it is necessary to have a new manufacturing method for isolation of non-volatile memory which avoids the short among TiSi 2  in semiconductors, and enforces its efficiency within the same or higher level integration.  
         SUMMARY OF THE INVENTION  
         [0008]    In accordance with the preferred embodiment of the present invention, the process of manufacturing method of non-volatile memory design is forwarded by an improvement of design rule. When the error of a mis-aligned situation of misplaced contact exists, the problem of short among TiSi 2  is solved.  
           [0009]    It is therefore an objective of the present invention to provide a manufacturing method, in which the space in the design rule of non-volatile memory is saved. Because mis-align does not cause any negative effect such as a short by using the present invention, it is not necessary to prepare the surrounding margin region. By reducing the margin occupied region, it can increase the integration of a semiconductor device.  
           [0010]    It is therefore another objective of the present invention to provide a method, in which for the defect of the application of multi-layer integration circuit to be improved by preventing the short circuit among the gate, drain and source, and different transistors.  
           [0011]    It is therefore an another objective of the present invention to provide a method, in which there is no extra mask necessary in the process, so no extra procedure or cost is needed.  
           [0012]    In accordance with the foregoing and other objective of the present invention, a manufacturing method is for novel isolation for non-volatile memory. The method comprises providing a substrate, wherein the substrate having a plurality of Shallow Trench Isolation (STI) layers and the STI layers are used for defining at least a local interconnected region and an active area.  
           [0013]    Next, a tunnel oxide is doped on the substrate and then, a polysilicon layer and a silicon nitride layer are deposited thereon respectively. The silicon nitride layer is above the polysilicon layer.  
           [0014]    Next, after locating the active area of the MOS, Buried Drain and Large Angle Tile Drain are driven in the substrate by Ion Implantation process. Then, a High-Density Plasma (HDP) layer is deposited whereon. Then, a portion of HDP layer is removed to expose the upper edge of the silicon nitride. During the process of removing the silicon nitride by etching, whereon HDP layer is also being removed.  
           [0015]    Next, a second polysilicon layer is formed and etched on the first polysilicon layer and HDP oxide layer. Then, a dielectric material(ONO) layer, a third polysilicon layer and a hard mask layer are formed sequentially. Next, the hard mask is patterned, and the third polysilicon layer, ONO layer and other polysilicon layer are etched through the patterned hard mask layer.  
           [0016]    Following is another etching process through the pattern of HDP oxide to polysilicon material to define recessed areas. Then, etching to the oxide material and depositing a dielectric material layer in the recess and on the surface of the substrate. Next, the dielectric material layer is overetched to obtain a spacer which extends from the recessed area to the hard mask layer.  
           [0017]    After the spacer is formed, the following can be a typical application process in multi-layer semiconductor, such as borderless contact and Salicide process. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0019]    [0019]FIG. 1 shows a cross-sectional view of a semiconductor structure which illustrates the contact location as practiced in prior art;  
         [0020]    [0020]FIG. 2 shows a cross-sectional view of a semiconductor structure which illustrates the steps of forming trenchs in substrate of this present invention;  
         [0021]    [0021]FIG. 3 shows a cross-sectional view of a semiconductor structure which illustrates removing portions of the second silicon nitride layer and HDP oxide layer by CMP of this present invention;  
         [0022]    [0022]FIG. 4 shows a cross-sectional view of a semiconductor structure which illustrates the steps after removing the silicon nitride layer and depositing and etching the second polysilicon layer of this present invention;  
         [0023]    [0023]FIG. 5A shows a cross-sectional view of a semiconductor structure which illustrates the steps of which after patterning hard mask layer in the SAMOS process, etching the third polysilicon layer, ONO layer, the second polysilicon layer and the first polysilicon layer of the present invention;  
         [0024]    [0024]FIG. 5B shows a cross-sectional view of a semiconductor structure which illustrates the steps of forming recesses by etching substrate masked by HDP oxide layer of the present invention.  
         [0025]    [0025]FIG. 6 shows a top view of a semiconductor structure, which illustrates the steps of depositing the third polysilicon, layer and hard mask layer;  
         [0026]    [0026]FIG. 7 shows a cross-sectional view of a semiconductor structure, which illustrates the structure of the BB cross-section of FIG. 6.  
         [0027]    [0027]FIG. 8 shows a 3D graph of semiconductor structure which illustrate the spacer structure formed by anisotropic etching.  
         [0028]    [0028]FIG. 9A shows another directional view of the BB cross-sectional area structure in FIG. 6 that illustrates the structure by the X-axis; and  
         [0029]    [0029]FIG. 9B shows another directional view of the DD cross-sectional area structure in FIG. 6 that illustrates the structure by the Y-axis.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0030]    The invention provides a novel method, in which the isolation of semiconductor devices is manufactured in an integral process. The method is compatible with the LOGIC self-aligned Silicide. This is the invention provides a self-aligned MOS (SAMOS) process for a logic technology to forming isolation which can replace the margin of the surrounding area of contact for preventing the circuit short in case of contact mis-alignment.  
         [0031]    From FIG. 2 to FIG. 9 shows the practice of the present invention in the non-volatile flash memory as the embodiment of twin-cell flame memory. Please referring to the FIG. 2, a single crystallized polysilicon with &lt;100&gt; crystallized plane semiconductor substrate  10  is isolated by traditional process. In the preferred embodiment, forming a 3500-4100 angstrom deepness Shallow Trench Isolation (STI)  11  on the substrate to avoid the disruption from different cells in the active area. Silicon nitride layer or Pad Oxide layer can be used for the mask during the anisotropic etching in this STI process to form the trenches. Then, Si2 is deposited in these trenches and finally silicon nitride is removed to create the isolation function among different transistors.  
         [0032]    After this fundamental isolation structure is completed, first oxide layer  12 , for example a Tunnel Oxide Layer(Tox)  12 , is generated on the substrate  10  by thermal oxidation at between 750° C. and 1000° C., and the thickness of the Tox is between 50 and 300 angstrom. This Tox can be used for a channel stop.  
         [0033]    After forming the Tox  12 , first polysilicon layer  13  is covered whereon by, for example conventional CVD process or doping process. The thickness of the first polysilicon layer is from 500 angstrom to 1000 angstrom. Because this polysilicon layer does not contact with any other conductor, this polysilicon layer is called “floating gate.” One of the most significant functions of polysilicon is storing electric charge. Generally speaking, more electric charge makes better performance of a flash memory.  
         [0034]    Then, first silicon nitride layer  14  is deposited by, for example, CVD on the first polysilicon layer. Due to the advantage of non-infiltration of silicon nitride, silicon nitride can be used as a passivation. The thickness of the first silicon nitride layer  14  is about 1000 to 2000 angstrom.  
         [0035]    Subsequent to the formation of the first oxide layer  12 , the first polysilicon layer  13  and the first silicon nitride layer  14 , several active areas are defined by conventional anisotropic etching to obtain the structure as shown in the upper portion of FIG. 1.  
         [0036]    After etching, the floating gate is used for mask to implant to form Drain/Source. In the preferred embodiment, N++ is implanted into the substrate 10  to form Buried Drain (BD)  15  and Large Angle Tile Drain (LATID)  16  for preventing short channel effect, as shown in the shadow area in FIG. 2. The BD is ion implanted with energy of about 40 KeV to 80 KeV, and dose of about 1E15 ions/cm 2  to 5E15 ions/cm 2 ; the LATID is ion implanted with energy of about 40 KeV to 100 KeV, and dose of about 5E12 ions/cm 2  to 1E14 ions/cm 2 .  
         [0037]    [0037]FIG. 3 represents the next step of process after FIG. 2. After formation of implanting Drain/Source, second oxide layer  17  is formed over it. For example, the second oxide layer  17  can be made by HDPCVD to a thickness of about 1500 to 3500 angstrom. Then, a portion of deposited oxide  17  is removed to get a thickness of about 300 to 1550 angstrom by the method of conventional wet etching for exposing the upper edge of the first silicon nitride layer  14 .  
         [0038]    Following the removal of oxide, another second silicon nitride layer is deposited over the top to a thickness of about 150 to 600 angstrom as a cap layer  18 , which contacts to the exposed first silicon nitride layer  14  edge. The next is removing the highest protruding portion of the structure by such as CMP process. The removing section includes silicon nitride in the top and portion of HDP layer for a deepness of about 300 to 1500 angstrom. After removal, the structure is illustrated in FIG. 3 where portion of HDP oxide layer  17 A is exposed after upper second silicon nitride cap layer is removed, and then the HDP oxide layer  17 A on BD and LATID is protected by the first silicon nitride layer  14  and second silicon nitride  18 .  
         [0039]    Referring to FIG. 4, the structure shows the result that second polysilicon layer  18  and the residual HDP oxide layer  17 A are deposited, patterned, and etched after removing all silicon nitride components. As referred to FIG. 3, after the residual HDP oxide layer  17 A is removed from the first silicon nitride layer  14 , the first silicon nitride layer  14  and the second silicon nitride layer  18  are removed simultaneously by such as dry etching process. Then, the second polysilicon layer  19 , for increasing the thickness of polysilicon and the electrical capacity, is deposited to a thickness of about 300 to 1000 angstrom over the residual the first polysilicon layer  13  and HDP oxide layer  17 . Here the second polysilicon layer is not necessary, but it accommodates more electrical charge to have better performance in flash memory.  
         [0040]    Due to the combination between deposited second polysilicon layer  19  and original first polysilicon layer  13 , it becomes a combined polysilicon layer where the interface between two polysilicon layers do not exist anymore. After that, the combined polysilicon is proceeded by the steps of patterning and etching to remove the polysilicon material which is on the STI  11  and HDP oxide layer  17 , and it defines the structure as showed in FIG. 4. During the patterning in the photolithography process, it has defined the size of every section.  
         [0041]    After formation of the structure as FIG. 4 shows, a dielectric material layer  20  such as SiO 2 /Si 3 N 4 /SiO 2 (ONO), third polysilicon layer  21 , and a hard mask layer  22 , such as WSi 2  or Oxide are deposited respectively over it. ONO layer is used for insulation and can be replaced by other materials with the same function such as SiN/SiO 2 . The formation of ONO can be proceeded by the Ion Implantation process to the surface of the combined polysilicon. In the preferred embodiment, N 2  and NO 2  can be used for controlling the growth of oxide to determine the thickness of the first Oxide layer of ONO. Furthermore, the third polysilicon layer  21  and hard mask layer  22  can be formed to a thickness of about 700 to 2000 angstrom and to a thickness of about 1000 to 30000 angstrom respectively by CVD. Besides, another mask layer, such as dark anti-reflection coating (DARC), can be used over the hard mask layer  22  for achieving better effect in the following process of etching and photolithography.  
         [0042]    After defining the region structure of memory by patterning the hard mask layer  22 , in the embodiment of the present invention is forming the Self-Align Metal Oxide semiconductor (SAMOS) by etching. Patterned hard mask in accordance with the present invention is shown in FIG. 5A. The third polysilicon layer  21 , dielectric material layer/ONO  20 , the second polysilicon layer  19  and the first polysilicon layer  13  are removed respectively by dry etching until the Tox  12  is exposed on the surface of the HDP layer  17  and substrate  10 .  
         [0043]    Then, referring to FIG. 5A, the dent shape of twin cell structure is defined through the pattern of HDP oxide layer  17  and hard mask layer  22 . Thereby etching to silicone material, for example using CF 4  as the etchant, through Tox  12  to form to a dent  24 , the deepness from 500 to 1500 angstrom, over the substrate  10 . This dent structure  24  is used for isolation and it plays a significant rule in the present invention.  
         [0044]    In the present invention, after the SAMOS etching process, it further includes the removal of HDP oxide layer  17 . Oxide layer is anitosopic dry etched in the protection of hard mask layer  22  since exchanging another etchant, and it removes the residual HDP oxide layer  17 A, referring to FIG. 5A, FIG. 5B and FIG. 6, there are 3D-drawings and top view, they respectively show the sectional schematic representation of section AA and section BB. Due to the hard mask layer  22  in section AA, the structure under the hard mask layer  22  is not etched to form the transistor illustrated in FIG. 7. Because without the protection from hard mask layer in section BB, the third polysilicon layer  21 , dielectric material layer/ONO  20 , and the combined polysilicon layer are etched respectively, and then, taking HDP oxide layer  17  as the mask, substrate  10  is etched to form a dent structure  24 . In one of the embodiment of the present invention, after dent  24  is formed, the HDP oxide layer  17  will be removed.  
         [0045]    Subsequent to forming self-align dent  24  and etching remains HDP oxide layer  17 , the formation of spacer  25  is proceeded. Typically a dielectric material layer  28  is deposited to a thickness of about 3500 to 5000 angstrom nitride by LPCVD. The deposited material is not only filled into the dent  24 , but also over the surface of substrate  10 , STI  11  and hard mask layer  22 . Then the second dielectric material layer  28  is anitosopic etched back to formed spacer  25  and the dent  24  is filled up of dielectric material  28  as showed in FIG. 8.  
         [0046]    In another embodiment of the present invention, the second oxide layer(HDP) is not removed right after the dent  24  is formed. After that, the spacer  25  is proceeded as above description, depositing a second dielectric material layer  28  first, then etching back. In the process of etching back, not only a portion of the second dielectric material layer  28  is removed, but the residual second oxide layer  17  is also removed.  
         [0047]    A top plan view of a portion of a memory cell in accordance with the present invention is shown in FIG. 6, where twin cell memory structure is formed in an active area by hard mask  22 . For the application of the present invention for flash memory, STI  11  is used for separating memory region. In the present invention, the dent structure  24  can also be used for isolation between memories.  
         [0048]    After the SAMOS process, a typical process of Self-Aligned Silicide/Salicide can be continued. For example, a metal layer (not shown), such as Titanium, is formed by conventional method, and then proceeded as thermal treatment to react with silicon on transistor to generate TiSi 2 .  
         [0049]    The formation structure among cells is shown in FIG. 9A and FIG. 9B. FIG. 9A shows the sectional view of the BB section along the X-axis as in FIG. 6 and FIG. 9B shows the sectional view of the DD section along the Y-axis as in FIG. 6. Arrows mean the corresponding parts between FIG. 9A and FIG. 9B. These demonstrate one of the merit of the present invention: the dent  24  can be used for the isolation region for TiSi 2  in the Salicide process, so it can not be short among cells.  
         [0050]    In another embodiment of the present invention, the borderless contact process is proceeded after MOS transistor is finished. For example, the process can include: a thin silicon nitride is formed on the original Si 3 N 4 , and another dielectric material (nitride oxide) is formed whereon Then, the location on the dielectric material for contact is etched for forming a contact. During the etching, because silicon nitride has higher selectivity then silicon oxide, so the etching stops when it hits the silicon oxide layer. Then another etchant is used to remove nitride silicide to form contact. Another merit of the present invention is replacing margin structure, which is surrounding contact, by the formation of the dent as isolation. As referring the BB section and the DD section in FIG. 6, FIG. 9A and FIG. 9B, despite mis-alignment in contact  27 , the defect of short does not happen. Furthermore, once the margin region has disappeared in the memory design rule, it can increase the integration of the semiconductor.  
         [0051]    As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated by the present invention rather than limitation of the present invention. It is intended to cover various modifications and similar arrangements, such as adding another persist mask layer over the hard mask layer  22  to prevent over-etching, included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.