Abstract:
A motherboard includes a host chip, switch chip, and a number of components having different inter integrated circuit ( 12 C) interfaces. The switch chip couples to the host chip through a first  12 C bus. The components having different  12 C interfaces can couple to the switch chip through different  12 C buses.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to a motherboard with multiple interfaces. 
       BACKGROUND 
       [0002]    An inter integrated circuit (I2C) interface, including a clock signal pin and a data signal pin, can be used to performing communication between different components. The different components may include various interfaces, such as an open-drain interface and/or a push-pull interface. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
           [0004]      FIG. 1  is a circuit diagram of a first embodiment of a motherboard of the present disclosure. 
           [0005]      FIG. 2  is a circuit diagram of a second embodiment of the motherboard of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0006]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
         [0007]    Several definitions that apply throughout this disclosure will now be presented. 
         [0008]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently coupled or releasably coupled. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0009]    The present disclosure is described in relation to a motherboard having different type inter integrated circuit (I2C) interfaces. 
         [0010]      FIG. 1  illustrates a first embodiment of a motherboard  10  of the present disclosure. The motherboard  10  can comprise a interface circuit  109 . The interface circuit  109  can comprise a switch chip  102  being capable of communicating a host chip through a first bus  113 , a first device  104  coupled to the switch chip  102  through a second bus  115 , and a second device  106  coupled to the switch chip  102  through a third bus  117 . In one embodiment, the first bus  113 , the second bus  115 , and the third bus  117  can be an I2C bus, each of which can comprise a clock signal line and a data signal line. In one embodiment, the first device  104  can be a display chip with an open-drain I2C interface, the second device  106  can be a power chip with a push-pull I2C interface. In one embodiment, the host chip can be a southbridge chip  100 . In other embodiments, the host chip can be a integrated baseboard management controller (IBMC) chip, or other chips with I2C function. 
         [0011]    In one embodiment, the southbridge chip  100  can comprise a first clock pin SCL and a first data pin SDA. A second clock pin SDL 1  of the switch chip  102  can couple to the first clock pin SCL through the first bus  113 . A second data pin SDA 1  of the switch chip  102  can couple to the first data pin SDA of the southbridge chip  100  through the first bus  113 . The first clock pin SCL of the southbridge chip  100  can couple to a power terminal VCC through a resistor R 1 , the first data pin SDA can couple to the power terminal VCC through a resistor R 2 . 
         [0012]    The switch chip  102  can further comprise a third clock pin SC 0 , a third data pin SD 0 , a fourth clock pin SC 1 , a fourth data pin SD 1 , a power pin VDD, and a ground pin VSS. The third clock pin SC 0  can couple to the power terminal VCC through a resistor R 3 , and the third data pin SD 0  can couple to the power terminal VCC through a resistor R 4 . The fourth clock pin SC 1  can couple to a power terminal VPP through a resistor R 5 , and the fourth data pin SD 1  of the switch chip  102  can couple to the power terminal VPP through a resistor R 6 . In one embodiment, the voltage of the power terminal VCC is 3.3 voltages, the voltage of the power terminal VPP is 5 voltages. The first device  104  and the second device  106  can communicate with the southbridge chip  100  through an I2C protocol. 
         [0013]      FIG. 2  illustrates a second embodiment of the motherboard  10  of the present disclosure. As comparing to the first embodiment of the motherboard  10 , the second motherboard  10  can further comprise a sensor  101  and a memory  103 . The sensor  101  and the memory  103  are both coupled to the first bus  113 , to communicate with the southbridge chip  100 . The southbridge chip  100  can obtain temperature of the motherboard  10  through the sensor  101 , and obtain configuration information of the memory  103  through the first bus  113 . In one embodiment, the sensor  101  and the memory  103  are both having the open-drain interfaces. 
         [0014]    In one embodiment, the switch chip  102  can control the communication between the first device  104  and the southbridge chip  100 , and control the communication between the second device  106  and the southbridge chip  100 , thereby making the devices with different I2C interfaces being capable of communicate with the host device through the first bus  113 . 
         [0015]    While the disclosure has been described by way of example and in terms of a preferred embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.