Abstract:
An improved relaxation oscillator circuit is provided using conventional CMOS device shunted with a current source ( 101  and  103 ) at each load of two cross-coupled gain stages. The improved oscillator uses a clamp voltage reference ( 134 ), to control the voltage swing across the charging/discharging capacitor ( 118 ). The improvements provide improved speed to power ratio, increased frequency tuning range, and less process and temperature variation effects. A transistor ( 130 ) and current source ( 138 ) replicate output transistors ( 110, 114 ) and current sources ( 101, 103 ). An amplifier ( 132 ) receives a clamp voltage reference ( 134 ) and current from the transistor ( 130 ) and current source ( 138 ) and functions to provide necessary drive currents to the gates of transistors ( 110, 114 ) which drive the outputs (VOR, VOL)

Description:
CLAIM OF PRIORITY  
       [0001]    This application claims priority from provisional application entitled “A CMOS Relaxation Oscillator Circuit with Improved Speed and Reduced Process/Temperature Variations”, Application No. 60/341,481, filed Dec. 14, 2001. 
     
    
     
       BACKGROUND  
         [0002]    1. Technical Field  
           [0003]    This invention relates to CMOS relaxation oscillator circuits. More particularly, this invention relates to high speed CMOS relaxation oscillator circuits with reduced dependence on process and temperature variations.  
           [0004]    2. Background  
           [0005]    Oscillators are widely used throughout the microelectronics industry to provide a steady and stable periodic output waveform. For example, a typical oscillator could be used to generate the clock signals for digital applications. Another application where oscillator circuits are used is in the generation of an amplitude modulated carrier signal or a frequency modulated carrier signal for the transmission of data.  
           [0006]    Oscillator circuits are generally broken down into two subclasses: tuned oscillators and relaxation oscillators.  
           [0007]    Tuned oscillators have the advantage of high frequency stability, high frequency capability and higher spectral purity than relaxation oscillators. Tuned oscillators, however, require expensive and bulky components, such as inductors and crystals. Furthermore, these components are difficult to integrate into monolithic circuits. Additionally, tuned oscillators suffer from a narrow frequency band of operation.  
           [0008]    Relaxation oscillators, however, have some unique advantages when used in integrated circuit design. For instance, relaxation oscillators do not require inductors or crystals. Thus, the relaxation oscillator can be easily incorporated into monolithic circuits. Additionally, the operative frequency band of a relaxation oscillator circuit is proportional to a charging current and inversely proportional to a voltage level across an energy storage device (e.g. capacitor) and the energy storage capacity of the energy storage device. The frequency of the relaxation oscillator circuit can easily be set using a single external component (e.g. a resistor) and can be varied linearly over a wide frequency band. A relaxation oscillator circuit, however, suffers from relatively poor frequency stability, particularly for high-speed operation. Furthermore, the relaxation oscillator circuit has a poor spectral purity characteristic. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    Further details of the present invention are explained with the help of the attached drawings.  
         [0010]    [0010]FIG. 1 depicts a relaxation oscillator circuit found in the prior art.  
         [0011]    [0011]FIG. 2 depicts the voltage waveforms within the prior art relaxation oscillator circuit during the transitions between the two stable states.  
         [0012]    [0012]FIG. 3 depicts an improved relaxation oscillator circuit with improved speed and reduced dependency on process and temperature variations.  
         [0013]    [0013]FIG. 4 depicts the voltage waveforms within the improved relaxation oscillator circuit depicted in FIG. 3.  
     
    
     DETAILED DESCRIPTION  
       [0014]    [0014]FIG. 1 depicts a relaxation oscillator circuit found in the prior art. The circuit is biased with a first voltage source  199  at a voltage potential of VSUP, and a second voltage source  198  at a voltage potential of VSUP 2 . The first voltage source  199  has a higher voltage potential than the voltage potential of the second voltage source  198  (VSUP&gt;VSUP 2 ). The value of VSUP 2  can be zero volts. Connected between the first voltage source  199  and the second voltage source  198  is a right side of the relaxation oscillator circuit and a left side of the relaxation oscillator circuit.  
         [0015]    The right side of the relaxation oscillator circuit includes a current source  101  connected in parallel with a diode connected transistor  110 . Thus, a drain and a gate of the transistor  110  are connected together as well as being connected with the first voltage source  199 . A first terminal of the current source  101  is connected to the first voltage source  199 . The current source  101  is connected in such a manner as to source current in a direction that is generally from the first voltage source  199  and towards the second voltage source  198 . A source of the transistor  110 , a second terminal of the current source  101 , a drain of a transistor  112 , and the gate of a transistor  116  are connected together to form a first node, VOR. A source of the transistor  112  is connected with a first terminal of a capacitor  118  and a first terminal of a current sink  105  to form a second node, VSR. The second terminal of the current sink  105  is connected with the second voltage source  198 , such that current flows into the second voltage source,  198 .  
         [0016]    The left side of the relaxation oscillator circuit essentially mirrors the right side of the relaxation oscillator circuit. Thus, the left side of the relaxation oscillator circuit includes a current source  103  connected in parallel with a diode connected transistor  114 . Thus, a drain and a gate of the transistor  114  are connected together as well as being connected with the first voltage source  199 . Additionally, the gate of the transistor  114  is connected with the gate of the transistor  110 . A first terminal of the current source  103  is connected with the first voltage source  199 . The current source  103  is connected in such a manner as to supply current in a direction that is generally from the first voltage source  199  towards the second voltage source  198 . A source of the transistor  114 , a second terminal of the current source  103 , a drain of a transistor  116 , and a gate of the transistor  112  are connected together to form a third node, VOL. A source of the transistor  116  is connected with a second terminal of the capacitor  118  and a first terminal of a current sink  107  to form a fourth node, VSL. A second terminal of the current sink  107  is connected with the second voltage source  198 , such that current flows into the second voltage source  198 .  
         [0017]    The current sink  105  and the current sink  107  sinks current from a first gain stage that includes the transistor  112  and a second gain stage that includes the transistor  116 . Additionally, the current sink  105  is typically set to sink the same amount of current as the current sink  107  and has a current value of ISINK.  
         [0018]    The current source  101  and the current source  103  are non-ideal. Thus, they both have a zero amp output current when the voltage across their terminals is zero. If the voltage across their terminals is not zero, then the value of the current can be any arbitrary number from zero amps to two times ISINK. Typically, the current provided by the current source  101  is equal to the current provided by the current source  103  and has a current value of ISOURCE. Furthermore, ISINK is typically equal to ISOURCE.  
         [0019]    For simplicity, the ratio of the transistor width to the transistor length is balanced along the different stages of the relaxation oscillator circuit. Thus, the width-to-length (W/L) of the transistor  110  is approximately equal to the W/L of the transistor  114 . Likewise, the W/L of the transistor  112  is approximately equal to the W/L of the transistor  116 . Thus, W/L( 112 )=W/L( 116 ) and W/L( 110 )=W/L( 114 ). Consequentially, the gate to source voltage, VGS, drop across the transistor  110  when it is on is equal to the VGS drop of the transistor  114  when it is on. The VGS associated with the transistor  110  or the transistor  114  is referred to as VGS 1 . Furthermore, the VGS drop across the transistor  112  when it is on is equal to the VGS drop of the transistor  116  when it is on. The VGS associated with the transistor  112  or the transistor  116  is referred to as VGS 2 .  
         [0020]    In operation, the cross-coupling between the transistor  112  and the transistor  116  by the capacitor  118  creates a positive feedback around the loop of the two gain stages. Thus, the relaxation oscillator circuit will oscillate and the voltage amplitude of an output signal on the output nodes, VOL and VOR, will grow until the output signal is clipped. At any one time, it can be assumed that either the transistor  112  or the transistor  116  will be active, but not both. Thus, the capacitor  118  is alternatively charged with equal but opposite currents. One current that charges the capacitor  118  originates from the transistor  112  when it is active and another current originates from the transistor  116  when it is active. The source of the charging current for the capacitor  118  alternates in half cycles of the relaxation oscillator circuit operation.  
         [0021]    During one half cycle of the relaxation oscillator circuit operation, the transistor  116  is supposed to be off and the transistor  112  is on. Meanwhile, the voltage at the third node, VOL, is equal to the voltage potential of the first voltage source  199 , or [VOL=VSUP]. The first node, VOR, however, is clamped to a voltage potential equal to the first voltage source 199 , less VGS 1 , the gate to source voltage drop across the transistor  110 , or [VOR=VSUP−VGS 1 ]. The source current of the transistor 110  is equal to the sum of the current sink  105  and the current sink  107  less the current source  101 , or [2*ISINK−ISOURCE=ISINK]. The transistor  112  is conducting a current equal to the sum of the current sink  105  and the current sink  107  or [2*ISINK]. The voltage at the second node, VSR, is clamped to the voltage at the third node, VOL, less VGS 2 , the gate to source voltage of the transistor  112  or [VSR=VOL−VGS 2 =VSUP−VGS 2 ]. It can be assumed that at the beginning of the half cycle, the voltage at the fourth node, VSL, is equal to the voltage at the node of VSR. Since the transistor  116  is off and the transistor  112  is on with a current of 2*ISINK, there is a current of ISINK flowing from the node VSR to the node VSL. The charging current through the capacitor  118  will cause the voltage level at the node, VSL, to ramp down with a constant slew rate of ISINK/C 1 , where C 1  is the capacitance value of the capacitor  118 . When this voltage ramps to [VSUP−VGS 1 −VGS 2 ], the transistor  116  is turned on like a switch. At this point, the positive feedback around the loop of the two stages will force the transistor  112  to be off like a switch. The output voltage at the third node, VOL, will be pulled down to VSUP−VGS 1  and the output voltage of the first node, VOR, is regenerattively pulled up to VSUP. The voltage at the node VSL is restored to be [VSUP−VGS 2 ]. As a result, the circuit has now changed its state and the capacitor  118  discharges in the opposite direction with a constant current equal to ISINK. The circuit maintains this state until the voltage level at the source of the transistor  112  ramps downward to [VSUP−VGS 1 −VGS 2 ], causing the transistor  112  to turn on and switch the circuit to its prior state, whereby the cycle repeats itself.  
         [0022]    [0022]FIG. 2 depicts the voltage waveforms within the prior art relaxation oscillator circuit during transitions between two stable states. The voltage level at the source of the off-transistor (transistor  116  or  112 , which is off) is linearly ramping in a negative direction with a slew rate of ISINK/C 1 , for a total voltage swing of (VSUP−VGS 2 )−(VSUP−VGS 1 −VGS 2 )=VGS 1  during each half-cycle. Recall that VGS 1  is the gate to source voltage across either transistor  110  or transistor  114 , whichever is on. Each half-cycle of oscillation is equal to the time T/2 for the voltage across capacitor  118  to ramp down by an amount equal to VGS 1 . Thus, T/2=C 1 *VGS 1 /ISINK. The total period of oscillation is T and the frequency of oscillation can be expressed as [F=1/T=ISINK/(2*C 1 *VGS 1 )]. Thus, the frequency is proportional to the charging current of ISINK, and is inversely proportional to the value of the timing of capacitor  118  and VGS 1 , which is the voltage across the diode connected transistors, transistor  110  and transistor  114  when they are on with a source current of ISOURCE=ISINK, and the voltage swing across the capacitor  118 .  
         [0023]    By neglecting the body effect of the transistors for simplicity, VGS 1  can be expressed as VGS 1 =Vt 0 +((2* ISINK/k)^ ½). In this equation, Vt 0  is the threshold voltage and k is the device transconductance of either transistor  110  or transistor  114 , depending on which transistor is conducting. Both Vt 0  and k are determined by the process used for the design of the relaxation oscillator circuit. The frequency dependence on VGS 1  prevents the use of ISINK to compensate for process and temperature variations. Thus, the frequency will be unstable over process and temperature. Additionally, VGS 1  has a minimum value of Vt 0  when ISINK is zero. Consequentially, a certain amount of current, ISINK, is required for a minimum operating frequency. Moreover, VGS 1  increases linearly in proportion to the square root of ISINK. This relationship between VGS 1  and ISINK forces the oscillator to need more charging current for higher speed operation due to the increased signal swing.  
         [0024]    [0024]FIG. 3 depicts modifications to the circuit of FIG. 1 to create an improved relaxation oscillator circuit with improved speed and reduced dependency on process variations and temperature. Components carried over from FIG. 1 to FIG. 3 are similarly labeled for convenience. In FIG. 3, the transistor  110  and the transistor  114  are no longer diode connected. Thus, the gate of these two transistors are not connected with the voltage source  199 . Rather, the gate of transistor  110  is connected with the gate of transistor  114 , the gate of an additional transistor  130  and the output of an amplifier  132 . In addition to the previously identified connections to the voltage source  199 , the drain of the transistor  130 , a first terminal of a current source  138 , and a first terminal of voltage source  134  are connected to the voltage source  199 . A second terminal of current source  138  is connected with the source of the transistor  130 , an inverting input to the amplifier  132 , and a first terminal of a current sink  136 . A second terminal of voltage source  134  is connected to a non-inverting input to amplifier  132 . Lastly, a second terminal of current sink  136  is connected to the voltage source  198 .  
         [0025]    The reference voltage source  134 , the amplifier  132  together with the transistor  130 , the current source  138  and the current sink  136  provide proper biasing for the gates of the transistor  114  and the transistor  110 . The current source  138  has the same properties as the current source  103  and the current source  101 . Thus, the current source  138  is non-ideal and requires a voltage across its terminals for it to generate a current. Also, current source  138  provides the same current as the current source  103  and the current source  101 , that being ISOURCE. The current sink  136  provides a current equal to two times ISINK or [2*ISINK]. The voltage source  134  has a voltage value of VCLMP. Lastly, the W/L ratio of the transistor  130  is equal to W/L ratio of the transistor  114  and the transistor  110 , [W/L( 130 )=W/L( 114 )=W/L( 110 )].  
         [0026]    The relaxation oscillator circuit of FIG. 3 performs similarly to the relaxation oscillator circuit of FIG. 1, with a few exceptions. For instance, the value of voltage source  134 , VCLMP, now controls the voltage at the node VOR to be VSUP−VCLMP when transistor  112  is on (same for the voltage at the node VOL when transistor  116  is on), rather than the gate-to-source voltage drop of the transistor  110  setting the voltage at the node VOR to be VSUP−VGS 1  (same for the node VOL). As the circuit settles, the voltage difference between the non-inverting and the inverting terminals of the amplifier  132  seek equilibrium. Thus, the voltage at the source of the transistor  130  settles to a value equal to VSUP−VCLMP. The voltage on the gate and source of transistor  114  and transistor  110  (when they are on) mirror the voltage values on the gate and source of the transistor  130 , to make VOR=VSUP−VCLMP and VOL=VSUP−VCLMP.  
         [0027]    While the transistors shown in FIG. 3 are NMOS transistors, these transistors can be replaced with PMOS transistors. Thus, a drain-source current path is formed in the transistors. Current in the drain-source path is controlled at a transistor control input (e.g. transistor gate). Furthermore, the transistors shown in FIG. 3 can be BJT transistors, either npn BJTs or pnp BJTs. If BJTs are used, then a collector-emitter path is formed. Current in the collector-emitter path is set using a transistor control input (e.g. transistor base). Collectively, a transistor can be described as comprising a first terminal coupled with a second terminal and a control terminal coupled between the first terminal and the second terminal.  
         [0028]    [0028]FIG. 4 depicts the voltage waveforms within the improved relaxation oscillator circuit depicted in FIG. 3. In operation, the voltage at the first node, VOR, varies between VSUP and (VSUP−VCLMP); the voltage at the second node, VSR, varies between (VSUP−VGS 2 ) and (VSUP−VCLMP−VGS 2 ); the voltage at the third node, VOL, varies between VSUP and (VSUP−VCLMP); and, the voltage at the fourth node, VSL, varies between (VSUP−VGS 2 ) and (VSUP−VCLMP−VGS 2 ). Furthermore, the voltage at node VSR and the node VSL continue to ramp down with a slew rate of ISINK/C 1 , where C 1  is the value of capacitor  118 . From these voltage characteristics of the relaxation oscillator circuit in FIG. 3, it can be seen that the voltage source  134  with a value of VCLMP can be used to control the voltage variation on node VOR and node VOL. Also, each half-cycle of oscillation is equal to the time T/2 for the voltage across capacitor  118  to ramp down by a voltage equal to VCLMP, or T/2=C 1 *VCLMP/ISINK. Thus, the total period of oscillation is T and the frequency of oscillation can be expressed as F=1/f=ISINK/(2*C 1 *VCLMP). Hence, the frequency is proportional to the charging current of ISINK, and inversely proportional to the value of the timing capacitor  118  and the voltage swing across the capacitor, VCLMP.  
         [0029]    The value of VCLMP can be designed to be less than the threshold voltage, Vt 0 , therefore less than the VGS 1  of the relaxation oscillator circuit depicted in FIG. 1 for any charging current ISINK. Thus, the improved relaxation oscillator circuit of FIG. 3 will have a higher speed than the relaxation oscillator circuit of FIG. 1 for the same charging current ISINK and the same timing capacitor  118 . Another way to describe the improvement is to say that for the same speed and capacitor, the improved relaxation oscillator circuit of FIG. 3 consumes less current than the relaxation oscillator circuit of FIG. 1. The amplifier  132  can also be designed to have a higher supply voltage than the voltage source  199 , or VSUP. Hence, the amplifier output can exceed the voltage source  199 ; and, the gate voltage of the transistor  110 , the transistor  114  and the transistor  130  can also be higher than the value of the voltage source  199 , or VSUP.  
         [0030]    In addition to the above-described improvements, the value of VCLMP is independent of the value of ISINK. Hence, the frequency increases linearly with ISINK in the relaxation oscillator circuit of FIG. 3 rather than increasing with the square root of ISINK as the relaxation oscillator circuit of FIG. 1 behaves. Consequentially, the frequency tuning range of the relaxation oscillator circuit of FIG. 3 is improved over the prior art.  
         [0031]    The value of VCLMP allows a frequency to be stable irrespective of process and temperature variations. Thus, voltage source  134  can be a neighboring circuit on an integrated circuit that includes the relaxation oscillator circuit of FIG. 3. Additionally, the value of VCLMP can be set such that it is proportional to a reference voltage (Vref) on an integrated circuit that includes the relaxation oscillator circuit of FIG. 3. For instance, VCLMP can be proportional to a bandgap voltage. Furthermore, VCLMP can equal k times Vref, where k is constant. Moreover, ISINK can be obtained from the reference voltage, Vref, and a precision resistor such as an off-chip resistor, Rext. Thus, ISINK=Vref/Rext. If such a configuration is used, then the frequency would be equal to, F=1/(2*k*C 1 *Rext). Thus, the frequency can be inversely proportional to the value of an on-chip capacitor  118  and an off-chip resistor, Rext. The reference voltage, Vref, is no longer part of the frequency expression. Since an off-chip resistor can be more resistant to process and temperature variations, the improved relaxation oscillator circuit of FIG. 3 will have better process and temperature independence over the relaxation oscillator circuit of FIG. 1.