Abstract:
A voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat.

Description:
RELATED APPLICATION  
         [0001]    This application claims the benefit of Korean Patent Application No. 2001-46567, filed Aug. 1, 2001, the disclosure of which is hereby incorporated herein by reference.  
         FIELD OF THE INVENTION  
         [0002]    The present invention relates generally to integrated circuit devices and methods of operating same and, more particularly, to integrated circuit memory devices and methods of operating same.  
         BACKGROUND OF THE INVENTION  
         [0003]    A conventional integrated circuit memory device may include a high voltage generating circuit for generating a voltage higher than a power voltage. Devices using a battery as a power source may include a high voltage generating circuit for generating a voltage higher than a battery power voltage. A high voltage generating circuit of an integrated circuit memory device may generate a high voltage target of about 4 volts when an external power voltage is in a predetermined range, such as, for example, about 2.2 volts to about 2.8 volts.  
           [0004]    As a level of a power voltage of a system incorporating an integrated circuit memory device is decreased, however, a level of an external power voltage applied to the integrated circuit memory device may also decrease. Accordingly, when an external power voltage less than, for example, about 2.2 volts is applied, the integrated circuit memory device&#39;s high voltage generating circuit may not be able to generate a target voltage of about 4 volts.  
           [0005]    In more detail, the integrated circuit memory device&#39;s high voltage generating circuit may use a step-up capacitor having a specific side based on the assumption that an external power voltage is in a predetermined range. When an external power voltage falls below the expected voltage range, the high voltage generating circuit may generate a target voltage of about 4 volts by increasing the capacitance of the step-up capacitor. Unfortunately, increasing the size of the step-up capacitor may increase the layout area needed to accommodate the high voltage generating circuit.  
           [0006]    A conventional high voltage generating circuit  100  will now be described with reference to FIG. 1. Signals and the media carrying those signals may be referred to by the same names. Referring now to FIG. 1, the conventional high voltage generating circuit  100  comprises first and second delay circuits  10  and  12 , first and second level shifters  14  and  16 , NOR gates NOR 1  and NOR 2 , a NAND gate NA 1 , inverters I 1  through I 8 , NMOS transistors NC 1  through NC 5 , and NMOS transistors N 1  through N 7 .  
           [0007]    An external power voltage VEXT is applied to the first and the second delay circuits  10  and  12 , the NOR gates NOR 1  and NOR 2 , the NAND gate NA 1 , and the inverters I 3  through I 6 . A high voltage VPP is applied to the inverters I 1 , I 2 , I 7 , and I 8 , and the first and second level shifters  14  and  16 .  
           [0008]    The first and the second delay circuits  10  and  12 , the NOR gates NOR 1  and NOR 2 , the first and the second level shifters  14  and  16 , the NAND gate NA 1 , the inverters I 1  through I 8 , the NMOS capacitors NC 1  and NC 2 , and the NMOS transistors N 1  and N 2  comprise a circuit that generates control signals for controlling a voltage step-up operation of the high voltage generating circuit. The NMOS transistors N 3 , N 4 , and N 6  comprise a circuit that pre-charges signals n 8 , n 10 , and n 13  during a pre-charge operation. The NMOS capacitor NC 3  and the NMOS transistor N 5  comprise a first step-up circuit that steps-up the signal n 10 , which corresponds to a step-up node, during an active operation. The NMOS capacitor NC 4  comprises a second step-up circuit that steps-up the signal n 10  node during an active operation. The NMOS capacitor NC 5  comprises a step-up circuit that steps-up the signal n 13  during an active operation. The NMOS transistor N 7  comprises a high voltage transmission circuit that transmits the signal n 10  at the step-up node to a high voltage generation terminal during an active operation.  
           [0009]    The first delay circuit  10  delays a pulse signal EN by a first delay time d 1  to generate a signal n 1 . The second delay circuit  12  delays an output signal of the first delay circuit  10  by a second delay time d 2  to generate a signal n 2 . The NOR gate NOR 1  NORs the pulse signal EN and the signal n 1  to generate a signal n 3 . The NOR gate NOR 2  NORs the signals n 2  and n 3 . The NAND gate NA 1  and the inverter I 6  AND the signals n 2  and n 3 . The first and the second level shifters  14  and  16  level-shift levels of the output signals of the NOR gate NOR 2  and the inverter I 6 , respectively. The inverter I 1  inverts an output signal of the first level shifter  14  to generate a signal n 4 . The inverter I 2  inverts an output signal of the inverter I 1 . The NMOS capacitor NC 1  pre-charges a signal n 5  to a level of the external power voltage VEXT in response to an output signal of the inverter I 2 . The NMOS transistor N 1  generates a signal n 5  at the external power voltage level VEXT in response to the signal n 4 . The inverter I 3  inverts the signal n 3  to generate a signal n 7 . The NMOS transistor N 2  generates a signal n 6  at the external power voltage level VEXT. The NMOS capacitor NC 2  pre-charges the signal n 6  to the external power voltage VEXT level in response to the signal n 3 . The NMOS transistor N 3  generates a signal n 8  at the external power voltage level VEXT in response to the signal n 3 . The NMOS capacitor NC 3  steps up the signal n 8  in response to the signal n 7 . The NMOS transistor N 5  facilitates charge sharing between nodes n 8  and n 10  to step up the signal n 10  in response to the signal n 5 . The NMOS transistor N 4  generates the signal n 10  at the external power voltage level VEXT in response to the signal n 6 . The inverters I 4  and I 5  delay the signal n 2  to generate a signal n 9 . The NMOS capacitor NC 4  steps up the signal n 10  in response to the signal n 9 . The inverter I 7  inverts an output signal of the second level shifter  16  to generate a signal n 11 . The inverter I 8  inverts the signal n 11  to generate a signal n 12 . The NMOS transistor N 6  generates the signal n 13  at the external power voltage level VEXT in response to the signal n 11 . The NMOS capacitor NC 5  steps up the signal n 13  in response to the signal n 12 . The NMOS transistor N 7  facilitates charge sharing between the node n 10  and the high voltage generation terminal in response to the signal n 13 .  
           [0010]    [0010]FIG. 2 is a waveform diagram that illustrates operations of the conventional high voltage generating circuit  100  of FIG. 1. During a time period t 1 , the external power voltage VEXT is applied and the pulse signal EN is at a common or ground voltage level VSS. The first delay circuit  10  delays the pulse signal EN by a first delay time d 1  to generate a signal n 1  at the ground voltage level VSS. The second delay circuit  12  delays the signal n 1  by a second delay time d 2  to generate a signal n 2  at the ground voltage level VSS. The NOR gate NOR 1  NORs the pulse signal EN and the signal n 2  to generate a signal n 3  at the external power voltage level VEXT. The NOR gate NOR 2 , the first level shifter  14 , and the inverter I 1  receive the signals n 2  and n 3  to generate the signal n 4  at the high voltage level VPP. The NMOS transistor N 1  pre-charges the signal n 5  to the external power voltage level VEXT in response to the signal n 4 . The inverter I 3  inverts the signal n 3 , which is at the external power voltage level VEXT, to generate the signal n 7  at the ground voltage level VSS. The NMOS transistor N 2  pre-charges the signal n 6  to the external power voltage level VEXT. The NMOS capacitor NC 2  steps up the signal n 6  to a voltage of 2VEXT when the signal n 3  is driven to the external power voltage level VEXT. The NMOS transistors N 3  and N 4  pre-charge the signals n 8  and n 10  to the external power voltage level VEXT, respectively, when their gate terminals are driven to a voltage level of 2VEXT. The inverters I 4  and I 5  generate the signal n 9  at the ground voltage level VSS in response to the signal n 2 . The NAND gate NA 1 , the inverter I 6 , the second level shifter  16 , and the inverter I 7  generate the signal n 11  at the high voltage level VPP in response to the signals n 1  and n 2 . The inverter I 8  generates the signal n 12  at the ground voltage level VSS in response to the signal n 11 . The NMOS transistor N 6  pre-charges the signal n 13  to the external power voltage level VEXT in response to the signal n 11 .  
           [0011]    During a time period t 2  that the pulse signal EN transitions from the ground voltage level VSS to the external power voltage level VEXT, the first delay circuit  10  delays the pulse signal EN by the first delay time d 1  to generate the signal n 1  at the external power voltage level VEXT. The second delay circuit  12  delays the signal n 1  by the second delay time d 2  to generate the signal n 2  at the external power voltage VEXT level. The NOR gate NOR 1  NORs the signals n 1  and n 2  to generate the signal n 3  at the ground voltage level VSS. The NOR gate NOR 2 , the first level shifter  14 , and the inverter I 1  generate the signal n 4  at the ground voltage level VSS in response to the signal n 3 . The inverter I 2  inverts the signal n 4  to generate a signal at the high voltage level VPP. The NMOS capacitor NC 1  steps up the signal n 5  to a voltage of “VEXT+VPP” in response to the signal at the output of the inverter I 2 . The NMOS capacitor NC 3  steps up the signal n 8  to a voltage of 2VEXT in response to the signal n 7  being driven to the external power voltage level VEXT. The inverters I 4  and I 5  generate the signal n 9  at the ground voltage level VSS in response to the signal n 2 . The NAND gate NA 1 , the inverter I 6 , the second level shifter  16 , and the inverter I 7  generate the signal n 11  at the high voltage level VPP in response to the signals n 1  and n 2 . The NMOS transistor N 6  is turned on and drives the signal n 13  to the external power voltage level VEXT in response to the signal n 11 . The inverter I 8  inverts the signal n 11  to generate the signal n 12  at the ground voltage level VSS.  
           [0012]    Because the NMOS transistors N 4  and N 7  are turned off and the NMOS transistor N 5  is turned on during the time period t 2 , charge is shared between the nodes n 8  and n 10 . As a result, the signal n 8  is driven to a voltage 1.5VEXT and the signal n 10  is driven a level of 1.5VEXT. Thus, a first step-up operation is performed on the signal n 10 .  
           [0013]    During a time period t 3 , the signal n 4  is transitions to the high voltage level VPP, the signal n 5  transitions to the external power voltage level VEXT, the signal n 9  transitions to the external power voltage level VEXT, and the signal n 13  transitions to a voltage level of “VEXT+VPP”. The signals n 6  and n 7  are at the external power voltage level VEXT. As a result, the NMOS capacitor NC 4  steps up the signal n 10  to a voltage level of 2.5VEXT in response to the signal n 9 . At this moment, the NMOS transistors N 4  and N 5  are turned off, and the NMOS transistor N 7  is turned on, so that charge sharing is performed between the node n 10  and the high voltage generating terminal, which results in the signal n 10  transitioning from the voltage 2.5VEXT to the high voltage level VPP. The signal n 8  maintains a voltage level of 1.5VEXT.  
           [0014]    After the time period t 3 , operations of the time periods t 1  through t 3  described above may be repeatedly performed to generate the high voltage VPP. In summary, the conventional high voltage generating circuit  100  steps up the node n 8  from a voltage VEXT to a voltage 2VEXT and the node n 5  from a voltage VEXT to a voltage “VEXT+VPP” during the second time interval t 2  to turn on the NMOS transistor N 5 , to allow charge sharing between the nodes n 10  and n 8 . This charge sharing operation steps up the voltage level at the node n 10  to 1.5VEXT.  
           [0015]    Thereafter, the node n 9  transitions from the ground voltage level VSS to the external power voltage level VEXT to step up the voltage at the node n 10  to 2.5VEXT using the NMOS capacitor NC 4 . Also, the node n 13  is driven from the external power voltage level VEXT to a voltage of “VEXT+VPP,” which turns the NMOS transistor N 7  on to allow charge sharing between the node n 10  and the high voltage generating terminal VPP. The amount of charge transferred may be given by “NC 4 ×(2.5VEXT−VPP).” After a second step-up operation is performed at the node n 10 , a voltage of the node n 13  falls to the external power voltage level VEXT, which turns the NMOS transistor N 7  off. The NMOS transistors N 3  and N 4  again precharge the signals n 8  and n 10  to the external power voltage level VEXT, respectively, when their gate terminals are driven to a voltage level of 2VEXT.  
           [0016]    Typically, the sizes of the step-up capacitors NC 3  and NC 4  are set based on an assumption that the external power voltage VEXT is in a predetermined range. When the external power voltage VEXT is below the expected voltage range, then the conventional high voltage generating circuit can generate a high voltage target by increasing the capacitances of the step-up capacitors NC 3  and NC 4 . Unfortunately, increasing the size of one or both of the step-up capacitor may increase the layout area needed to accommodate the high voltage generating circuit  100 .  
         SUMMARY OF THE INVENTION  
         [0017]    According to some embodiments of the present invention, a voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat. Advantageously, by sharing charge between the first node and the second node to increase the potential of the second node, the second node may be driven to a relatively high voltage, i.e., the fourth voltage described above, without the need to increase a size of a capacitor that may be used to drive the second node.  
           [0018]    In other embodiments of the present invention, a capacitor may be used to drive the second node to the fourth voltage and/or a capacitor may be sued to drive the first node to the sixth voltage.  
           [0019]    In still other embodiments of the present invention, charge may be shared between the first node and the second node to increase the potential at the second node from the first voltage to the second voltage by generating a first control signal and closing a switch between the first node and the second node responsive to the first control signal.  
           [0020]    In still further embodiments of the present invention, charge may be shared between the first node and the second node so that the first and second nodes reach the common fifth voltage by generating a second control signal and closing the switch between the first node and the second node responsive to the second control signal.  
           [0021]    Although embodiments of the present invention have been described above primarily with respect to method embodiments, voltage generation circuit embodiments are also provided. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which:  
         [0023]    [0023]FIG. 1 is a block diagram that illustrates a conventional voltage generation circuit;  
         [0024]    [0024]FIG. 2 is a timing diagram that illustrates waveforms of signals of the conventional voltage generation circuit of FIG. 1;  
         [0025]    [0025]FIG. 3 is a block diagram that illustrates a voltage generation circuit in accordance with some embodiments of the present invention;  
         [0026]    [0026]FIG. 4 is a timing diagram that illustrates waveforms of signals of the voltage generation circuit of FIG. 3 in accordance with some embodiments of the present invention; and  
         [0027]    [0027]FIG. 5 is a graph of step-up charge quantity versus external power voltage for the voltage generation circuit of FIG. 3 and the conventional voltage generation circuit of FIG. 1.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0028]    While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like numbers refer to like elements throughout the description of the figures. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Signals and the media carrying those signals may be referred to by the same names.  
         [0029]    [0029]FIG. 3 is a circuit diagram that illustrates a high voltage generating circuit  200  in accordance with some embodiments of the present invention. The high voltage generating circuit  200  comprises third, fourth, and fifth delay circuits  20 ,  22 , and  24 , a first pulse generating circuit  26 , which comprises an inverter I 10  and a NAND gate NA 3 , a second pulse generating circuit  28 , which comprises an inverter I 9  and a NAND gate NA 2 , NAND gates NA 1  through NA 4 , a NOR gate NOR 3 , first and second level shifters  14  and  16 , inverters I 1  through I 8 , NMOS transistors N 1 , N 2 , N 3 ′, and N 4  through N 7 , and NMOS capacitors NC 1  through NC 5 .  
         [0030]    An external power voltage VEXT is applied to the third, fourth and fifth delay circuits  20 ,  22  and  24 , NAND gates NA 1  through NA 4 , NOR gate NOR 3 , and inverters I 3  through I 6 , I 9  and I 10 . A high voltage VPP is applied to the inverters I 1 , I 2 , I 7 , and I 8 , and the first and second level shifters  14  and  16 .  
         [0031]    The third, fourth, and the fifth delay circuits  20 ,  22  and  24 , the first pulse generating circuit  26 , the second pulse generating circuit  28 , the NAND gates NA 1  and NA 4 , the NOR gate NOR 3 , the first and the second level shifters  14  and  16 , and the inverters I 1  through I 8  comprise a control signal generating circuit to control voltage step-up operations of the high voltage generating circuit  200 . The NMOS capacitor NC 1  and the NMOS transistor N 1  comprise a circuit to step up and pre-charge the signal n 5 . The NMOS capacitor NC 2  and the NMOS transistor N 2  comprise a circuit to step up and pre-charge the signal n 6 . The NMOS capacitor NC 3  comprises a circuit to step up the signal n 8 . The NMOS capacitor NC 4  comprises a circuit to step up the signal n 10 .  
         [0032]    The NMOS capacitor NC 5  and the NMOS transistor N 6  configure a circuit to step up and pre-charge the signal n 13 . The NMOS transistors N 3 ′ and N 4  comprise a circuit to pre-charge the signals n 8  and n 10 , respectively. The NMOS transistor N 5  is configured to transmit charge between the nodes n 8  and n 10 . The NMOS transistor N 7  is configured to transmit charge between node n 10  and a high voltage generating terminal.  
         [0033]    Exemplary operations of the high voltage generating circuit  200 , in accordance with some embodiments of the present invention, are described hereafter. The third delay circuit  20  delays the enable pulse signal EN by a third delay time d 3  to generate a signal n 14 . The fourth delay circuit  22  delays an output signal of the third delay circuit  20  by a fourth delay time d 4  to generate a signal n 15 . The fifth delay circuit  24  delays an output signal of the fourth delay circuit  22  by a fifth delay time d 5  to generate a signal n 16 . The first pulse signal generating circuit  26  generates a signal n 18  by NANDing the signal n 16  and an inverted version of the signal n 14 . The second pulse signal generating circuit  28  generates the signal n 17  by NANDing the signal EN and an inverted version of the signal n 16 . The NAND gate NA 4  generates a signal n 19  by NANDing the signals n 17  and n 18 . The NOR gate NOR 3  generates a signal n 20  by NORing the signals EN and n 16 . The NAND gate NA 1  and the inverter I 6  AND the signals EN and n 16 . The first level shifter  14  shifts a level of the signal n 19 . The second level shifter  16  shifts a level of an output signal of the inverter I 6 . The inverter I 1  inverts an output signal of the first level shifter  14  to generate a signal n 4 . The inverter I 2  inverts the signal n 4 . The NMOS transistor N 1  pre-charges the signal n 5  to the external power voltage level VEXT in response to the signal n 4 . The NMOS capacitor NC 1  steps up the signal n 5  to a voltage “VEXT+VPP” in response to an output signal of the inverter I 2 . The NMOS transistor N 2  pre-charges the signal n 6  to the external power voltage level VEXT. The NMOS capacitor NC 2  steps up the node n 6  to a voltage 2VEXT in response to the signal n 20 . The NMOS transistor N 4  pre-charges the node n 10 , which corresponds to a step up node, in response to the signal n 6 . The inverter I 3  inverts the signal n 17 . The NMOS transistor N 3 ′ pre-charges the signal n 8  to the external power voltage level VEXT in response to the signal n 13 . The NMOS capacitor NC 3  steps up the node n 8  to the voltage 2VEXT in response to the signal n 7 . The NMOS transistor N 5  facilitates charge sharing between nodes n 8  and n 10  to step up the signal n 10  in response to the signal n 5 . The inverters I 4  and I 5  generate the signal n 9  by delaying and buffering the signal n 16 . The NMOS capacitor NC 4  steps up the signal n 10  in response to the signal n 9 . The inverter I 7  inverts an output signal of the second level shifter  16  to generate the signal n 11 . The inverter I 8  inverts the signal n 11  to generate the signal n 12 . The NMOS transistor N 6  pre-charges the signal n 13  to the external power voltage level VEXT in response to the signal n 11 . The NMOS capacitor NC 5  steps up the signal n 13  to a voltage “VEXT+VPP” in response to the signal n 12 . The NMOS transistor N 7  facilitates charge sharing between the node n 10  and the high voltage generation terminal in response to the signal n 13 .  
         [0034]    [0034]FIG. 4 is a waveform diagram that illustrates exemplary operations of the high voltage generating circuit  200  of FIG. 3 in accordance with some embodiments of the present invention. Wave forms of FIG. 4 represent signals n 1  through n 20  of the high voltage generating circuit of FIG. 1, which are generated after step-up operation have been performed multiple times.  
         [0035]    During a time period T 1 , the pulse signal EN is applied at a common or ground voltage level VSS. The signals n 14 , n 15 , n 16 , n 19 , n 7 , and n 9  are driven to the ground voltage VSS, and the signals n 17 , n 18 , n 20 , and n 10  are driven to the external power voltage VEXT. The signals n 4  and n 11  are at the high voltage VPP, and the signal n 6  is at the voltage 2VEXT. The signals n 5  and n 13  are pre-charged to the external power voltage level VEXT, and the signal n 8  is pre-charged to a voltage “VEXT+Va” where Va=(VPP−VEXT)/2.  
         [0036]    During a time period T 2  that the pulse signal EN transitions from the ground voltage level VSS to external power voltage level VEXT, the signals n 14 , n 15  and n 16  are delayed by delay times d 1 , d 2  and d 3  and then transition from the ground voltage level VSS to the external power voltage level VEXT, respectively. The signals n 17 , n 20 , n 4 , n 6 , n 9 , and n 12  transition to the ground voltage level VSS, the signals n 18 , n 19 , n 6 , and n 7  transition to the external power voltage level VEXT, and the signal n 11  remains at the high voltage level VPP. The signal n 5  transitions to a voltage of “VEXT+VPP,” and the signal  13  remains at the external power voltage level VEXT. As a result, node n 8  is stepped up to a voltage of “2VEXT+Va” in response to the signal n 7 . At this moment, the NMOS transistors N 4  and N 7  are turned off and the NMOS transistor N 5  is turned on to allow charge sharing between the nodes n 8  and n 10 . Due to the charge sharing, the signal n 8  is stepped down from a voltage of “2VEXT+Va” to a voltage of “1.5VEXT+(Va/2),” and the signal n 10  is stepped up from a voltage of VEXT to a voltage of “1.5VEXT+(Va/2).” 
         [0037]    During a time period T 3 , the signals n 14 , n 15 , n 16 , n 18 , and n 6  remain at the external power voltage level VEXT, and the signal n 20  remains at the ground voltage level VSS. The signal n 11  transitions from the high voltage level VPP to the ground voltage level VSS. The signal n 17  transitions from the ground voltage level VSS to the external power voltage level VEXT, the signal n 19  is transited from the external power voltage level VEXT to the ground voltage level VSS, and the signals n 4  and n 12  transition from the ground voltage level VSS to the high voltage level VPP. The signal n 5  transitions from the voltage level “VEXT+VPP” to the external power voltage level VEXT, the signal n 9  transitions from ground voltage level VSS to the external power voltage level VEXT, and the signal n 13  transitions from the external power voltage level VEXT to a voltage of “VEXT+VPP.” Hence, the signal n 8  transitions to the external power voltage level VEXT, and the NMOS capacitor NC 4  steps up the signal n 10  to a voltage of “2.5VEXT+(Va/2)” in response to the signal n 9 . At this moment, the NMOS transistors N 4  and N 5  are turned off and the NMOS transistor N 7  is turned on to allow charge sharing between the node n 10  and the high voltage generating terminal. The signal n 10  drops from a voltage level of “2.5VEXT+(Va/2)” to the high voltage level VPP. A total charge quantity transferred to the high voltage generating terminal through the NMOS transistor N 7  may be represented by “NC 4 ×(2.25VEXT−0.75VPP).” 
         [0038]    During a time period T 4 , the signal n 14  transitions to the ground voltage level VSS, the signals n 15 , n 16 , n 17 , and n 9  remain at the external power voltage level VEXT, and the signals n 20  and n 7  remain at the ground voltage level VSS. The signal n 18  transitions from the external power voltage level VEXT to the ground voltage level VSS, and the signal n 19  transitions from the ground voltage level VSS to the external power voltage level VEXT.  
         [0039]    The signals n 4  and n 12  transition from the high voltage level VPP to the ground voltage level VSS, the signal n 1  transitions from the ground voltage level VSS to the high voltage level VPP, the signal n 13  transitions from the external power voltage level VEXT to a voltage of “VEXT+VPP,” and the signal n 5  transitions from the external power voltage level VEXT to a voltage of “VEXT+VPP.” Hence, the NMOS transistors N 4  and N 7  are turned off and the NMOS transistor N 5  is turned on to allow charge sharing between the nodes n 8  and n 10 . The signal n 8  increases from the external power voltage level VEXT to a voltage of “VEXT+Va” and the signal n 10  decreases from the high voltage level VPP to a voltage of “VEXT+Va.” 
         [0040]    The high voltage generating circuit  200  of FIG. 3 generates a high voltage VPP by repeatedly performing operations of the time periods T 1  through T 4 , which are described above. A total charge quantity transferred to the high voltage generating terminal through the NMOS transistor N 7  by the high voltage generating circuit  200  of FIG. 3 is “NC 4 ×(2.25VEXT−0.75VPP),” and a total charge quantity transferred to the high voltage generating terminal through the NMOS transistor N 7  by the conventional high voltage  100  generating circuit is “NC 4 ×(2.5VEXT−VPP).” Thus, the high voltage generating circuit  200 , in accordance with some embodiments of the present invention, can transmit a charge quantity more than the conventional high voltage generating circuit  100  of FIG. 1. If the external power voltage VEXT is 2 volts and a target high voltage VPP is 4 volts, then the conventional high voltage generating circuit  100  of FIG. 1 can transmit a total charge quantity of 1.0×NC 4  to the high voltage generating terminal, whereas the high voltage generating circuit  200  of FIG. 3 can transmit a total charge quantity of 1.5×NC 4 .  
         [0041]    That is, the high voltage generating circuit  200  increases a voltage level of the signal n 8  such that the NMOS transistor N 5  is turned on and the NMOS transistors N 4  and N 7  are turned off to allow charge sharing between the nodes n 8  and n 10  during the time period T 4 , thereby improving a step-up ability. As a result, when the signal n 10  is first stepped up during the time period T 1 , a step-up voltage level can be increased. Advantageously, the high voltage generating circuit  200  may increase a step-up ability, not by increasing a step-up ability of the step-up transistors NC 3  and NC 4 , but by generate additional control signals through an additional delay circuit and additional logic circuitry.  
         [0042]    [0042]FIG. 5 is a graph of step-up charge quantity versus external power voltage VEXT for the high voltage generating circuit  200  of FIG. 3 and the conventional high voltage generating circuit  100  of FIG. 1. The values denoted by “X” correspond to the high voltage generating circuit  200  of FIG. 3 and the values denoted by “Y” correspond to the conventional high voltage generating circuit  100  of FIG. 1. As can be seen in FIG. 5, when the external power voltage VEXT is less than 1.9 volts, the step-up charge quantity generated by the high voltage generating circuit  200  is approximately twice that of the conventional high voltage generating circuit  100 . When the external power voltage VEXT exceeds 1.9 volts, the step-up charge quantity generated by the high voltage generating circuit  200  exceeds that of the conventional high voltage generating circuit  100 .  
         [0043]    Advantageously, high voltage generating circuits, in accordance with some embodiments of the present invention, may improve step-up ability without increasing a size of the step-up capacitor, which may obviate a need to increase layout area size.  
         [0044]    In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.