Abstract:
A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure generally relates to embedded Dynamic Random Access Memory (eDRAM). More specifically, the present disclosure relates to improved eDRAM devices and processes for fabricating improved eDRAM devices. 
       BACKGROUND 
       [0002]    Dynamic Random Access Memory (DRAM) is a type of Random Access Memory (RAM) that stores data bits in capacitors in an integrated circuit. It is generally implemented on a package separate from the package of its accompanying processor. By comparison, cache memory within a Central Processing Unit (CPU) is conventionally implemented using Static Random Access Memory (SRAM). 
         [0003]    However, recent advances have brought embedded DRAM (eDRAM) to market. Embedded DRAM is usually integrated on the same die or in the same package as its accompanying processor. Advantages of some eDRAM devices include higher operation speeds than external DRAM and higher bit storage device density than is available in SRAM. 
         [0004]      FIG. 1  is an example of a prior art processor device  100 , which has a memory portion  101  and a logic portion  102 . The memory portion  101  is an eDRAM portion that includes many capacitors used as storage devices. For ease of illustration, only one such storage device, capacitor  103 , is shown. The logic portion  102  includes many logic circuits, which are also not shown for ease of illustration. On a substrate  104  are gates  110   a ,  110   b ,  110   c  and contacts  111   a ,  111   b ,  111   c . The processor  100  includes two metal layers, M1  106  and M2  105 . The M2 metal layer  105  is coupled to the M1 metal layer  106  through vias  113   a ,  113   b . The M1 metal layer  106  is coupled to the contacts  111   b ,  111   c  through the contacts  112   a ,  112   b.    
         [0005]    As shown in  FIG. 1 , the M1 metal layer  106  is fabricated to be above the storage device  103 . (As used herein, relational terms, such as “above” and below” are used with respect to the substrate  104 , such that, e.g., the gates  110   a ,  110   b ,  110   c  are below the M1 metal layer  106 , and the M1 metal layer  106  is above storage device  103 ). In some prior art devices, the distance from the M1 metal layer  106  to the substrate  104  is on the order of ten-thousand Angstroms. For very high density eDRAM devices, the space between the M1 metal layer  106  and the gates  110 , a ,  110   b ,  110   c  is so large that M1-to-gate parasitic capacitance is high enough to result in noticeable speed degradation of the processor  100 . The parasitic capacitance further increases as the space between the structures  120  and  130  decreases due to scaling. Thus, the tall contact  113   a ,  112   a ,  111   b  becomes more problematic as the technology continues to scale. 
       BRIEF SUMMARY 
       [0006]    Various embodiments of the present invention include improved eDRAM devices and techniques to fabricate improved eDRAM devices. According to one embodiment, a process for manufacturing an eDRAM device includes fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area. 
         [0007]    In another embodiment, an integrated circuit includes a DRAM portion and a logic portion. Semiconductor structures are fabricated upon a substrate within the DRAM portion and the logic portion. A first conductive layer is disposed above the semiconductor structures in the DRAM portion and the logic portion. A storage device is disposed above at least some of the semiconductor structures in the DRAM portion. The first conductive layer is not located above the storage device. 
         [0008]    In yet another embodiment, an integrated circuit includes a DRAM portion and a logic portion, as well as means for contacting gates within the DRAM portion and the logic portion. The contact means is fabricated upon a substrate. The integrated circuit also has a first conductive layer disposed above the contact means in the DRAM portion and the logic portion, and means for storing data disposed above at least some of the contact means in the DRAM portion. The first conductive layer is not located above the data storage means. 
         [0009]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    For a more complete understanding of the present invention, reference is now made to the following description taken in conjunction with the accompanying drawings. 
           [0011]      FIG. 1  is an illustration of an example prior art processor device. 
           [0012]      FIG. 2  shows an exemplary wireless communication system  200  in which an embodiment of the disclosure may be advantageously employed. 
           [0013]      FIG. 3  is a cut-away view of an exemplary processor adapted according to one embodiment of the invention. 
           [0014]      FIGS. 4-10  illustrate an example process flow for fabricating the processor of  FIG. 3  according to one embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]      FIG. 2  shows an exemplary wireless communication system  200  in which an embodiment of the disclosure may be advantageously employed. For purposes of illustration,  FIG. 2  shows three remote units  220 ,  230 , and  240  and two base stations  250  and  260 . It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units  220 ,  230 , and  240  include improved eDRAM components  225 A,  225 B, and  225 C, respectively, which include embodiments of the invention as discussed further below.  FIG. 2  shows forward link signals  280  from the base stations  250  and  260  and the remote units  220 ,  230 , and  240  and reverse link signals  290  from the remote units  220 ,  230 , and  240  to base stations  250  and  260 . 
         [0016]    In  FIG. 2 , remote unit  220  is shown as a mobile telephone, remote unit  230  is shown as a portable computer, and remote unit  240  is shown as a computer in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, media players, such as music players, video players, game consoles, and entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. Although  FIG. 2  illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Various embodiments may be suitably employed in any device which includes eDRAM. 
         [0017]      FIG. 3  is a cut-away view of an exemplary processor  300  adapted according to one embodiment of the invention. In its various embodiments, the processor  300  can be any type of processor, such as an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a general purpose processor, and the like. The processor  300  includes the DRAM portion  301  and the logic portion  302  on the same die, where the logic portion  302  includes the logic circuitry, and the DRAM portion  301  includes on-die information storage. The DRAM portion  301  is in communication with the logic portion  302  so that the logic portion  302  can read to and write from the DRAM portion  301 . 
         [0018]    The processor  300  includes a variety of semiconductor structures disposed on the substrate  310 . The semiconductor structures include word lines  303   a ,  303   b ,  303   c ,  303   d ,  303   e , gates  304   a ,  304   b ,  304   c ,  304   d ,  304   e , gate contacts  305   a ,  305   b ,  305   c ,  305   d ,  305   e , storage node contacts  306   a ,  306   b , a bitline contact  307 , and a logic contact  308 . The bitline contact  307  is part of a two-step contact that also includes a metal 1 (M1) stud  311   a  and another bitline contact  317 , both of which are described in more detail below. 
         [0019]    The M1 stud  311   a  is one part of the M1 conductive layer, as is the M1 portion  311   b . The M1 conductive layer acts as the interconnect line for processor  300 . In the embodiment of  FIG. 3 , the M1 layer is fabricated before storage devices  312  and  313  are fabricated, and the M1 layer is not placed above storage devices  312  and  313 . 
         [0020]    The embodiment of  FIG. 3  stands in contrast to the prior art embodiment of  FIG. 1 , which places the M1 layer  106  above the storage device  103 . Whereas the distance from the M1 layer  106  of  FIG. 1  to the substrate  104  may be in the range of ten-thousand Angstroms, the M1 layer of  FIG. 3  can be in the range of three-thousand Angstroms from the substrate  310  (though various embodiments of the invention are not limited to any particular distance between the M1 layer and the substrate). The embodiment of  FIG. 3  includes less parasitic capacitance between the M1 layer and the gates  304   a ,  304   b ,  304   c ,  304   d ,  304   e  and between and among the various M1 portions (e.g., M1 portion  311   a ,  311   b , and other M1 portions not shown) than does the embodiment of  FIG. 1 , because of the shorter distance from the M1 layer to the substrate  310 . 
         [0021]    The processor  300  includes storage components  312  and  313 , which in this example, are metal-insulator-metal (MIM) capacitors. The storage devices  312  and  313  are in communication with the storage node contacts  306   a ,  306   b , and the M1 stud  311   a  is in contact with the bitline contact  307 . In this example, the M1 stud  311   a  and the storage devices  312  and  313  are fabricated directly above the contacts  306   a ,  306   b , and  307 , and the M1 stud  311   a  and the storage devices  312  and  313  are fabricated at substantially the same level. 
         [0022]    The processor  300  employs a metal 2 (M2) conductive layer  320  as a bitline in this example. The M2 layer  320  is in communication with the contact  305   b  through a bitline contact  317 . In another embodiment, the M1 conductive layer operates as the bitline. 
         [0023]    In many embodiments, the bitline contact  317  (as well as the other contacts  306   a ,  306   b ,  307 , and  308 ) is constructed as a via. The embodiment of  FIG. 3  uses a two-step contact between the M2 metal layer and the substrate, which has one fewer step than do the three-step contacts used by the embodiment of  FIG. 1  between the M2 metal layer  105  and the substrate. Accordingly, the embodiment of  FIG. 3  can increase efficiency by using one fewer via mask. 
         [0024]      FIGS. 4-10  illustrate an example process flow for fabricating the processor  300  according to one embodiment of the invention.  FIG. 4A  shows a process  400 , which includes Chemical Mechanical Polishing (CMP) and oxide deposition. After the M1 layer is deposited and after an M1 pattern lithograph/oxide etch, it undergoes CMP for purposes of planarization. After CMP, the M1 layer and an oxide layer  415  conform to a plane  420 . The processor  300  employs a portion of the M1 layer for the stud  311   a , and a top-down view of the M1 stud  311   a  and bitline contact  307  is shown in  FIG. 4B . Oxide deposition is then performed to create the oxide layer  410 . 
         [0025]      FIG. 5  shows the process  500 . The process  500  includes an oxide etch in the oxide layers  410  and  415  to create recesses in which the storage devices  312  and  313  will be formed. The oxide etching removes the oxide down to the contacts  306   a ,  306   b , and bitline contact  307 . 
         [0026]      FIG. 6  shows the process  600 . The process  600  includes deposition of a conductive material  610 , e.g., a metal, for the storage devices  312  and  313 . After the conductive material  610  is deposited, another CMP process is performed to planarize the conductive material  610  at the top of the oxide layer  410 . 
         [0027]      FIG. 7  shows the process  700 . The process  700  includes depositing an insulator  715 , e.g., a high K oxide, upon the conductive material  610 . Then, process  700  deposits a conductive plate  710 , e.g., a metal, on the insulator  715 . The conductive plate  710  is etched after patterning by lithograph. 
         [0028]      FIG. 8  shows the process  800 . The process  800  includes depositing an oxide layer  810  on the storage devices  312  and  313  and on the oxide layer  410 . 
         [0029]      FIG. 9  shows the process  900 , which includes etching oxide layers  810  and  410  down to the M1 layer, including the M1 stud  311   a  and the M1 portion  311   b . The etch is in preparation of enabling communication with the M1 layer, by for example, vias. 
         [0030]      FIG. 10  shows the process  1000 , which includes fabricating the contacts  317  and  1017  as vias in the etched recesses from process  900 . The contacts  317  and  1017  provide a communication path from the M2 conductive layer to the contacts  305   b ,  305   d  in the substrate  310 . The contact area of the M1 contact stud  311   a  is larger than the contact areas of the bitline contacts  307  and  317  (as shown in  FIG. 4A ), thereby providing for convenient alignment during processes  400 ,  900 , and  1000 . In another embodiment, the M1 contact stud  311   a  is not fabricated. In this embodiment, the bitline contact  317  is directly on the bitline contact  307 . In either embodiment, the M2 conductive layer is then deposited, as shown in  FIG. 3 . 
         [0031]    While  FIGS. 4-10  show one example method for fabricating a processor according to one embodiment, other embodiments may use other methods. Specifically, other embodiments may add, omit, rearrange, or modify one or more of the processes  400 - 1000  while fabricating the M1 conductive layer before fabricating one or more storage components. Additionally, various embodiments include implementing the processor in a system such as a computer, phone, game console, or the like. 
         [0032]    Various embodiments include advantages over prior art embodiments. For instance, the embodiment of  FIG. 3  includes less parasitic capacitance, and thus greater speed, than the embodiment of  FIG. 1  (assuming the density of contacts is similar in the embodiments of  FIG. 1  and  FIG. 3 ). Furthermore, the M1 stud  311   a  of  FIG. 3  can be somewhat wider than the studs  107   a ,  107   b  of  FIG. 1 , thereby increasing yield by ameliorating alignment issues. Additionally, the embodiment of  FIG. 3  replaces the three-step contacts of  FIG. 1  with two-step contacts, thereby eliminating one via mask. 
         [0033]    Although specific circuitry has been set forth, it will be appreciated by those skilled in the art that not all of the disclosed circuitry is required to practice the invention. Moreover, certain well known circuits have not been described, to maintain focus on the invention. 
         [0034]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.