Abstract:
An organic thin film transistor substrate and a method of manufacturing the organic thin film transistor substrate capable of preventing overflow of an organic semiconductor layer. An organic thin film transistor substrate comprises a gate line formed on the substrate, a data line intersecting the gate line, a thin film transistor connected to the gate line and the data line and including an organic semiconductor layer, a pixel electrode connected to the thin film transistor, an organic protective layer protecting the thin film transistor, a first bank-insulating layer providing filling areas in the organic gate insulating layer and the organic semiconductor layer, and a second bank-insulating layer providing the filling area of the organic semiconductor layer together with the first bank-insulating layer and formed on a source electrode and a drain electrode of the thin film transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority of Korean Patent Application No. 2006-71235 filed on Jul. 28, 2006 and all the benefits accruing therefrom under 35 U.S.C. §119, the contents of which are herein incorporated by reference in their entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to organic thin film transistor substrates and, more particularly, to a method of manufacturing the organic thin film transistor substrate that prevents overflow of the organic semiconductor layer. 
         [0004]    2. Description of the Related Art 
         [0005]    In general, liquid crystal displays (“LCDs”) display an image in such a way that each of the liquid crystal cells varies its light transmittance responsive to video signals. Each liquid crystal cell includes a thin film transistor (“TFT”) used as a switching element for supplying video signals. An active layer of the TFT uses an amorphous silicon layer or a poly silicon layer. Since the amorphous silicon or poly silicon active layer is patterned by a thin film deposition (coating) process, a photolithography process, and an etching process, the manufacturing process is complex and costly. Recently, research and development have been actively conducted using a printing process to form an organic TFT substrate having an organic semiconductor layer. The organic semiconductor layer of the organic TFT substrate is formed by an ink-jet printing method within a hole provided in a bank-insulating layer. However, ink over spray may cause the organic semiconductor layer to overflow out of the hole and penetrate into a pixel electrode. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    The present invention provides an organic TFT substrate and a method of manufacturing the TFT substrate capable of preventing overflow of the organic semiconductor layer. 
         [0007]    In an exemplary embodiment of the present invention, the organic thin film transistor substrate comprises a gate line formed on the substrate, a data line intersecting the gate line, a thin film transistor connected to the gate line and the data line and including an organic semiconductor layer, a pixel electrode connected to the thin film transistor, a first bank-insulating layer providing filling areas in the organic gate insulating layer and the organic semiconductor layer, and a second bank-insulating layer providing the filling area in the organic semiconductor layer together with the first bank-insulating layer and formed on a source electrode and a drain electrode of the thin film transistor. 
         [0008]    In some embodiments, an organic protective layer protecting the thin film transistor is included. 
         [0009]    In some embodiments, the gate insulating layer is formed of an organic material. 
         [0010]    In some embodiments, a first embodiment of each of the source and drain electrodes comprises a first conductive layer which is a transparent conductive layer, and at least one second conductive layer formed on the first conductive layer, except for an area overlapping a gate electrode of the thin film transistor. 
         [0011]    In some embodiments, a second embodiment of each of the source and drain electrodes is formed of a first conductive layer which is a transparent conductive layer. 
         [0012]    In some embodiments, the data line is formed by extending the first conductive layer of the source electrode, and the pixel electrode is formed by extending the first conductive layer of the drain electrode. 
         [0013]    In some embodiments, the data line is formed by depositing the first and second conductive layers, and the pixel electrode is formed by extending the first conductive layer of the drain electrode. 
         [0014]    In some embodiments, the second bank-insulating layer is formed on the second conductive layer to have the same width as the width of the second conductive layer on the second conductive layer, or to be wider than the width of the second conductive layer. 
         [0015]    In some embodiments, the second bank-insulating layer is formed of a photosensitive layer. 
         [0016]    In some embodiments, the first bank-insulating layer comprises a first sub-bank-insulating layer which provides a first dot hole exposing the gate electrode so that the organic gate insulating layer can be filled, and a second sub-bank-insulating layer connected to the first dot hole and providing a second dot hole wider than the first dot hole so that the organic semiconductor layer and the organic protective layer can be filled. 
         [0017]    In an exemplary embodiment of the present invention, a method of manufacturing an organic thin film transistor substrate comprises forming a gate line and a gate electrode connected to the gate line on the substrate, forming a first bank-insulating layer exposing the gate electrode, forming a gate insulating layer to be filled within the first bank-insulating layer, forming a data line intersecting the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a pixel electrode connected to the drain electrode, and forming a second bank-insulating layer formed on the source electrode, the drain electrode, and the data line, and forming an organic semiconductor layer comprising a channel between the source electrode and the drain electrode within an area provided in the first bank-insulating layer and the second bank-insulating layer. 
         [0018]    In some embodiments, forming an organic protective layer to cover the organic semiconductor layer is included. 
         [0019]    In some embodiments, the forming of the data line, the source electrode, the drain electrode, the pixel electrode, and the second bank-insulating layer comprises sequentially forming on a substrate, on which the organic gate insulating layer is formed, a first conductive layer and at least one second conductive layer, forming a second bank-insulating layer having a stepped structure on the second conductive layer, forming a source/drain metal pattern including the data line, the source electrode, and the drain electrode, and the pixel electrode on the first bank-insulating layer by patterning the first and second conductive layers using the second bank-insulating layer as a mask, exposing the second conductive layer of the pixel electrode and the second conductive layer of each of the source and drain electrodes in a channel area by ashing the second bank-insulating layer, and removing the second conductive layer exposed. 
         [0020]    In some embodiments, the first conductive layer is formed of a transparent conductive layer. 
         [0021]    In some embodiments, the second conductive layer is formed of an opaque metal. 
         [0022]    In some embodiments, the second bank-insulating layer is formed on the second conductive layer to have the same width as the width of the second conductive layer or to be wider than the width of the second conductive layer. In some embodiments, the second bank-insulating layer is formed of a photosensitive layer. 
         [0023]    In some embodiments, the forming of the first bank-insulating layer comprises forming a first sub-bank-insulating layer which prepares a first dot hole exposing the gate electrode so that the organic gate insulating layer is filled, and forming a second sub-bank-insulating layer which is connected to the first dot hole and a second dot hole wider than the first dot hole so that the organic semiconductor layer and the organic protective layer are filled. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The above and other features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with accompany drawings, in which: 
           [0025]      FIG. 1  is a plan view showing an organic TFT substrate in accordance with an exemplary embodiment of the present invention; 
           [0026]      FIG. 2  is a cross-sectional view taken along line I-I′ of the organic TFT substrate shown in  FIG. 1 ; 
           [0027]      FIGS. 3A and 3B  are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a gate metal pattern shown in  FIGS. 1 and 2 ; 
           [0028]      FIGS. 4A and 4B  are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a first bank-insulating layer and an organic gate insulating layer shown in  FIGS. 1 and 2 ; 
           [0029]      FIGS. 5A to 5C  are cross-sectional views illustrating a method of manufacturing the first bank-insulating layer and the organic gate insulating layer shown in  FIG. 4B ; 
           [0030]      FIGS. 6A and 6B  are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a source/drain metal pattern, a pixel electrode, an organic semiconductor layer, a second bank-insulating layer, and an organic protective layer shown in  FIGS. 1 and 2 ; and 
           [0031]      FIGS. 7A to 7E  are cross-sectional views illustrating a method of manufacturing the source/drain metal pattern, the pixel electrode, the organic semiconductor layer, the second bank-insulating layer, and the organic protective layer shown in  FIG. 6B . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0032]    Exemplary embodiments of the present invention are described with reference to the accompanying drawings in detail. The same reference numbers will be used throughout the drawings to refer to the same or like parts. Detailed descriptions of well-known functions and structures incorporated herein may be omitted to avoid obscuring the subject matter of the present invention. 
         [0033]      FIG. 1  is a plan view showing an organic TFT substrate in accordance with an exemplary embodiment of the present invention and  FIG. 2  is a cross-sectional view taken along line I-I′ of the organic TFT substrate shown in  FIG. 1 . 
         [0034]    An organic TFT substrate shown in  FIGS. 1 and 2  comprises a gate line  102  and a data line  104  formed to intersect each other with a first bank-insulating layer  118  interposed therebetween on a lower substrate  101 , a TFT  130  formed in an intersecting area of the gate and data lines  102  and  104 , and a pixel electrode  122  formed in a sub-pixel area provided by the intersecting structure of the gate and data lines  102  and  104  and connected to the TFT  130 . 
         [0035]    The gate line  102  supplies a scan signal from a gate driver (not shown) and the data line  104  supplies a pixel signal from a data driver (not shown). 
         [0036]    The data line  104  is formed in a single layer or multi-layer structure including a transparent conductive layer on the first bank-insulating layer  118 . For example, the data line  104  is formed in a double layer structure having a first conductive layer  105  using a transparent conductive layer and a second conductive layer  107  using an opaque metal. The first conductive layer  105  uses ITO (Indium Tin Oxide), TO (Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), etc. The second conductive layer  107  is formed in a single layer structure composed of a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), Cu alloy, Mo alloy, and Al alloy or in a multi-layer structure using these metals, such as Mo/Al/Mo. 
         [0037]    The TFT  130  causes a pixel signal, which is supplied to the data line  104  responsive to a scan signal supplied to the gate line  102 , to be charged and stored in the pixel electrode  122 . The TFT  130  comprises a gate electrode  106  connected to the gate line  102 , a source electrode  108  connected to the data line  104 , a drain electrode  110  facing the source electrode  108  and connected to the pixel electrode  122 . An organic semiconductor layer  114  overlaps the gate electrode  106  with an organic gate insulating layer  112  interposed therebetween to form a channel between the source electrode  108  and the drain electrode  110 . 
         [0038]    The gate electrode  106  is exposed by a first dot hole  124 A which is prepared in a first sub-bank-insulating layer  118 A. The source and drain electrodes  108  and  110  include a first and second conductive layers  105 ,  107  overlapping the gate electrode  106 . The source and drain electrodes  108  and  110  are formed having a stepwise shape along a stepped structure prepared in the first bank-insulating layer  118  and the gate insulating layer  112 . As a result, the channel width between the source and drain electrodes  108  and  110  is increased, thereby improving the current property of the organic TFT  130 . 
         [0039]    The organic semiconductor layer  114  is formed on the organic gate insulating layer  112  in an area prepared in the first and second bank-insulating layers  118  and  116  so as to contact with the source and drain electrodes  108 ,  110  each formed of the first conductive layer  105  in the channel area. 
         [0040]    The organic semiconductor layer  114  is formed of an organic semiconductor material, for example, pentacene, tetracene, anthracene, naphthalene, α-6T, α-4T, perylene and derivative thereof, rubrene and derivative thereof, coronene and derivative thereof, perylene tetracarboxylic diimide and derivative thereof, perylene tetracarboxylic dianhydride and derivative thereof, phthalocyanine and derivative thereof, naphthalene tetracarboxylic diimide and derivative thereof, naphthalene tetracarboxylic dianhydride and derivative thereof, conjugated polymer derivative containing a substituted or non-substituted thiophene, conjugated polymer derivative containing a substituted fluorine, etc. 
         [0041]    The organic semiconductor layer  114  provides ohmic-contact with the source and drain electrodes  108  and  110  by a self-assembled monolayer (SAM) treatment process. More specifically, a difference of work functions between each of the source and drain electrodes  108  and  110  and the organic semiconductor layer  114  is reduced by the SAM treatment process. Accordingly, a hole injection into the organic semiconductor layer  114  from the source and drain electrodes  108  and  110  is easily implemented and a contact resistance between each of the source and drain electrodes  108  and  100  and the organic semiconductor layer  114  is also reduced. 
         [0042]    The TFT  130  is protected by an organic protective layer  120 . The organic protective layer  120  is formed within a second dot hole  124 B provided in second sub-bank-insulating layer  118 B and in the second bank-insulating layer  116 . 
         [0043]    The first bank-insulating layer  118  is stepwise formed to prepare the first and second dot holes  124 A and  124 B exposing the gate electrode  106 . In other words, the first bank-insulating layer  118  comprises the first sub-bank-insulating layer  118 A formed to provide the first dot hole  124 A on the lower substrate  101 , and the second sub-bank-insulating layer  118 B formed to be thicker than the first sub-bank-insulating layer  118 A and to provide the second dot hole  124 B. The area exposed by the first dot hole  124 A has a hydrophilic property with the organic gate insulating layer  112 , and the remaining area has a hydrophobic property with the organic gate insulating layer  112 . The area exposed by the second dot hole  124 B has a hydrophilic property with the organic semiconductor layer  114  and the organic protective layer  120 , and the remaining area has a hydrophobic property with the organic semiconductor layer  114  and the organic protective layer  120 . The second dot hole  124 B is connected to the first dot hole  124 A and has a wider width than the first dot hole  124 A. 
         [0044]    The second bank-insulating layer  116  is formed of a photosensitive organic layer and used as a mask pattern when the data line  104 , the source electrode  108 , and the drain electrode  110  are formed. The second bank-insulating layer  116  is formed to be wider than the width of the second conductive layer  107  on the second conductive layer  107  of each of the data line  104  and the source and drain electrodes  108  and  110 . The second bank-insulating layer  116  prevents the organic semiconductor layer  114  formed by an ink-jet printing method from penetrating into the pixel electrode  122 . The channel area exposed by the second bank-insulating layer  116  has a hydrophilic property with the organic semiconductor layer  114  and the remaining area has a hydrophobic property with the organic semiconductor layer  114 . 
         [0045]    The pixel electrode  122  is formed on the second sub-bank-insulating layer  118 B by extending the first conductive layer  105 , which is the transparent conductive layer of the drain electrode  110 . 
         [0046]    Upon receiving video signals through the TFT  130 , the pixel electrode  122  forms an electric field with the common electrode. The liquid crystal molecules aligned between the TFT substrate and the color filter substrate are rotated by dielectric anisotropy, thereby varying the transmittance of light through the pixel area and implementing a gray scale. 
         [0047]    While the source and drain electrodes  108  and  110  have been described as having been formed by depositing the first and second conductive layers  105  and  107  along with the data line  104 , the source and drain electrodes  108  and  110  may be formed only of the first conductive layer  105  being a transparent conductive layer. In this case, a mask pattern of the second bank-insulating layer  116  used similar to that used to pattern the source and drain electrodes  108 ,  110 , and the data line  104 . 
         [0048]      FIGS. 3A and 3B  are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a gate metal pattern of the TFT substrate in accordance with the present invention. 
         [0049]    As shown in  FIGS. 3A and 3B , a gate metal pattern including the gate line  102  and the gate electrode  106  is formed by a first mask process on the lower substrate  101 . 
         [0050]    More specifically, a gate metal layer is deposited on the lower substrate  101 , and then the gate metal layer is patterned by a photolithography process and an etching process to form the gate metal pattern including the gate line  102  and the gate electrode  106 . Herein, the gate metal layer is formed of a single layer composed of a metal such as Mo, titanium (Ti), Cu, aluminum neodymium (AINd), Al, Cr, Mo alloy, Cu alloy, and Al alloy or at least a double-stacked layer having these metals. 
         [0051]      FIGS. 4A and 4B  are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing the first bank-insulating layer  118  and the organic gate insulating layer  112 . 
         [0052]    As shown in  FIGS. 4A and 4B , the first bank-insulating layer  118  including first and second sub-bank-insulating layers  118 A and  118 B is formed on the lower substrate  101 . The organic gate insulating layer  112  is formed within the first dot hole  124 A provided in the first bank-insulating layer  118 , as will now be described in detail with reference to  FIGS. 5A to 5C . 
         [0053]    As shown in  FIG. 5A , a photosensitive organic insulating material  119  is deposited on the entire surface of the lower substrate  101  by a spinless or spin coating method. Then, a slit mask  140  is aligned on the lower substrate  101 . The slit mask  140  comprises a blocking area S 11  in which a blocking layer  144  is formed on a quartz substrate  142 , a slit area S 12  in which slits  146  are formed on the quartz substrate  142 , and a transmitting area S 13  in which only the quartz substrate  142  exists. As shown in  FIG. 5B , blocking area S 11  blocks ultraviolet rays in the exposing process. After a developing process, the second sub-bank-insulating layer  118 B is formed on the lower substrate  101  of an area that corresponds to the blocking area S 11 . The slit area S 12  diffracts ultraviolet rays in the exposing process. After the developing process, the first sub-bank-insulating layer  118 A is formed to be thinner than the thickness of the second sub-bank-insulating layer  118 B on the lower substrate  101  of an area that corresponds to the slit area S 12 . The second dot hole  124 B is formed, as shown in  FIG. 5B . The transmitting area S 13  transmits all of the ultraviolet rays in the exposing process and, after the developing process, the first dot hole  124 A connected to the second dot hole  124 B is formed on the lower substrate  101 . Then, as shown in  FIG. 5C , an organic insulation solution is sprayed into the first dot hole  124 A using an ink-jet printing apparatus and cured, thereby forming the organic gate insulating layer  112  filled the first dot hole  124 A. The organic gate insulating layer  112  is formed to be thinner than the depth of the first dot hole  124 A. The organic gate insulating layer  112  uses polyvinyl pyrrolidone (PVP), polymethlymethacrylate (PMMA), benzocyclobutene (BCB), polyimide, polyvinylphenol, parylene, etc. 
         [0054]    In some embodiments, before spraying the organic insulation solution, the lower substrate  101 , on which the first bank-insulating layer  118  is formed, may undergo surface treatment. The area exposed by the first dot hole  124 A through the surface treatment process has a hydrophilic property with the organic insulation solution, and the remaining area has a hydrophobic property with the organic insulation solution. Then, when the organic insulation solution is sprayed on the lower substrate  101 , the organic insulation solution is concentrated on the area exposed by the first dot hole  124 A having a hydrophilic property with the organic insulation solution to form the organic gate insulating layer  112 . Accordingly, overflow of the organic gate insulating layer  112  may be prevented. 
         [0055]    Alternatively, the first bank-insulating layer  118  may be formed of a material having a hydrophobic property with the organic insulation solution. For example, the first bank-insulating layer  118  may be formed of an insulating material having a fluorine group. When the organic insulation solution is sprayed on the lower substrate  101  on which the first bank-insulating layer  118  is formed, the organic insulation solution is concentrated on the area exposed by the first dot hole  124 A to form the organic gate insulating layer  112 . 
         [0056]      FIGS. 6A and 6B  are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a source/drain metal pattern, the pixel electrode  122 , the second bank-insulating layer  116 , the organic semiconductor layer  114 , and the organic protective layer  120  among a method of manufacturing the TFT substrate in accordance with the present invention. 
         [0057]    As shown in  FIGS. 6A and 6B , the source/drain metal pattern including the data line  104 , the source electrode  108 , and the drain electrode  110 , the pixel electrode  122 , and the second bank-insulating layer  116  are formed on the lower substrate  101  on which the organic gate insulating layer  112  is formed, and then the organic semiconductor layer  114  and the organic protective layer  120  are sequentially formed. In this regard, it will now be described in detail with reference to  FIGS. 7A to 7E . 
         [0058]    As shown in  FIG. 7A , the first and second conductive layers  105  and  107  are deposited by a deposition method such as a sputtering method on the lower substrate  101  on which the organic gate insulating layer  112  is formed. The first conductive layer  105  is formed of a transparent conductive material, such as ITO, TO, IZO, and ITZO, and the second conductive layer  107  is formed of a single layer composed of a metal such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, and Al alloy, or at least a double-stacked layer having these metals. 
         [0059]    Then, a photosensitive organic layer  115  such as photoresist or photo-acryl resin is formed on the second conductive layer  107 . Next, the photosensitive organic layer  115  is exposed and developed by a photolithography process using a transreflective mask or a slit mask  150 , thereby forming the second bank-insulating layer  116  having a stepped structure, as shown in  FIG. 7B . 
         [0060]    More specifically, the slit mask  150  comprises a blocking area S 21  in which a blocking layer  154  is formed on a quartz substrate  152 , a slit area S 22  in which slits  156  are formed on the quartz substrate  152 , and a transmitting area S 23  in which only the quartz substrate  152  exists. The blocking area S 21  is positioned in an area in which the source electrode, the drain electrode, and the data line are to be formed. The blocking area S 21  blocks ultraviolet rays in an exposing process, and after a developing process, the second bank-insulating layer  116  having a first thickness h 1  is formed, as shown in  FIG. 7B . The slit area S 22  is formed in an area in which the source and drain electrodes corresponding to a channel area and the pixel electrode are to be formed. The slit area S 22  diffracts ultraviolet rays in the exposing process, and then after a developing process, the second bank-insulating layer  116  having a second thickness h 2  thinner than the first thickness h 1  is formed, as shown in  FIG. 7B . The transmitting area S 23  transmits all of ultraviolet rays, and then after the developing process, the photosensitive organic layer  115  is removed, as shown in  FIG. 7B . 
         [0061]    The first and second conductive layers  105  and  107  are patterned by an etching process using the second bank-insulating layer  116  as a mask, thereby forming the source/drain metal pattern of a multi-layer structure including the data line  104 , the source electrode  108 , and the drain electrode  110 , and the pixel electrode  122 , as shown in  FIG. 7B . 
         [0062]    Thereafter, as shown in  FIG. 7C , the thickness of the second bank-insulating layer  116  with the first thickness h 1  becomes thin by an ashing process using O 2  plasma, and the second bank-insulating layer  116  with the second thickness h 2  is removed. The second conductive layer  107  formed on the pixel electrode  122  and the second conductive layer  107  of the source and drain electrodes  108  and  110  corresponding to the channel area are removed by the etching process using as a mask the second bank-insulating layer  116  ashed. At this time, the second conductive layer  107  of the source and drain electrodes  108  and  110  is formed to have the same width as the width of the second bank-insulating layer  116  or overly etched to have the width narrower than the width of the second bank-insulating layer  116 . 
         [0063]    Thereafter, an organic semiconductor solution of a liquid state is sprayed into the second dot hole  124 B defined by the second bank-insulating layer  116  and the second sub-bank-insulating layer  118 B by using an ink-jet printing method. Then, the organic semiconductor solution is cured, and the organic semiconductor layer  114  of a solid state is formed, as shown in  FIG. 7D . 
         [0064]    In some embodiments, before spraying the organic semiconductor solution, the lower substrate  101  on which the source/drain metal pattern, the pixel electrode  122 , and the second bank-insulating layer  116  are formed may undergo surface treatment. An area exposed through the second dot hole  124 B defined by the second bank-insulating layer  116  and the second sub-bank-insulating layer  118 B has a hydrophilic property with the organic semiconductor solution and a remaining area has a hydrophobic property with the organic semiconductor solution by the surface treatment process. Then, when the organic semiconductor solution is sprayed on the lower substrate  101 , it is concentrated on the gate insulating layer  112  having a hydrophilic property with the organic semiconductor solution of a liquid state and an exposed portion of the first conductive layer  105  of the source and drain electrodes  108 ,  110 , thereby forming the organic semiconductor layer  114 . As a result, overflow of the organic semiconductor layer  114  is prevented. 
         [0065]    Alternatively, when the first bank-insulating layer  118  is formed of a material having a hydrophobic property with the organic semiconductor solution, the organic semiconductor solution is concentrated on the gate insulating layer  112 , thereby preventing overflow of the organic semiconductor layer  114 . 
         [0066]    After the organic semiconductor layer  114  is formed, it is treated by a SAM process. Accordingly, the organic semiconductor layer  114  provides ohmic-contact with the source and drain electrodes  108  and  110 . 
         [0067]    Thereafter, an organic protective solution such as polyvinyl alcohol (PVA) is sprayed by an ink-jet printing method into the second dot hole  124 B prepared by the second sub-bank-insulating layer  118 B and the second bank-insulating layer  116 , and then the organic protective solution is cured, thereby forming the organic protective layer  120  within an area provided in the second bank-insulating layer  116 , as shown in  FIG. 7E . 
         [0068]    In some embodiments, before spraying the organic protective solution, the lower substrate  101 , on which the organic semiconductor layer  114  is formed, may undergo surface treatment. An area exposed by the second bank-insulating layer  116  has a hydrophilic property with the organic protective solution and a remaining area has a hydrophobic property with the organic protective solution by the surface treatment process. Then, when the organic protective solution is sprayed on the lower substrate  101 , the organic protective solution is concentrated on an area having the hydrophilic property with the organic protective solution to form the organic protective layer  120 . 
         [0069]    As described above, the organic TFT substrate and a method of manufacturing the organic TFT substrate according to the present invention forms the second bank-insulating layer on the second conductive layer of each of the source and drain electrodes. The second bank-insulating layer may prevent the organic semiconductor layer interposed between the source and drain electrodes from penetrating into the pixel electrode. 
         [0070]    While this invention has been described in connection with what is presently considered practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.