Abstract:
The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The field of invention relates to detecting misaligned electrical masks in the semiconductor manufacturing process. In particular, the field of invention relates to measuring alignment, rotation, and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation in devices defined by the mask layers. 
         [0003]    2. Description of the Related Art 
         [0004]    Semiconductor manufacturers produce a number of types of computer chips, including dynamic random access memory chips (DRAMs), microprocessors, application specific integrated circuits (ASICs), and digital signal processors, for example. Although the process for manufacturing these computer chips, also referred to as integrated circuits (IC), may vary depending on the type of chip, all include some fundamental manufacturing process steps such as deposition, photolithography, etching, ion implantation, polishing, cleaning, and drying, for example. 
         [0005]    Often, throughout the semiconductor manufacturing process, repeated use is made of masks for creating multiple layers of circuit patterns on a chip. In particular, the process includes creating multiple layers (hereinafter “level”) by transferring a pattern from a mask to a light sensitive material, known in the art as a photoresist, on a substrate. In high yield semiconductor manufacturing processes it is especially crucial that the various mask levels that are transferred onto the photoresist be within specification such that it is aligned, without rotation, and without bias (i.e., oversized or undersized). 
         [0006]    Typically, alignment is performed using physical techniques such as optical structures that are read by persons or read by pattern recognition software and tools using misalignment verniers, “box inside a box” optical reflection techniques or other manual comparative assessments. Although some masking levels result in structures that are still visible during the subsequent processing steps, many mask levels do not leave any visible physical structure behind. The most common of these are ion implant mask levels. Ion implantation is a materials engineering process whereby ions of a material can be implanted into the silicon wafer to change the physical properties of the silicon wafer. Often, for the ion implant mask levels, a layer of photoresist is applied, light is exposed through the mask, and subsequently developed to open the desired images. Next, this masked wafer is ion implanted, wherein the photoresist is used to control the areas where ions are implanted before the photoresist is chemically stripped away. Thus, the alignment of the ion implant mask is crucial in determining the areas that are implanted with ions, but difficult to determine through traditional techniques. 
         [0007]    Current alignment measurement techniques suffer from several limitations. First, measurement of the alignment, rotation and bias of the mask often has to be done with the photoresist still in place since after the photoresist is removed there is no optically or electrically visible evidence remaining of the ion implant. Second, alternatives to physical alignment techniques, such as electrical alignment techniques fail to apply to lightly doped implants such as threshold tailoring implants, for example. Thus, there exists a need to measure the ion implant mask alignment, rotation, and bias of these masks after the wafers are fully processed and that apply to lightly doped implants. 
       SUMMARY 
       [0008]    The present invention provides an apparatus and method for detecting ion implant mask misalignment, rotation and bias in a semiconductor manufacturing process. In one embodiment, the apparatus comprises at least two field effect transistor (FET) pairs. The apparatus further includes an ion implanted area in each FET included in the at least two FET pairs. The apparatus also includes at least one inspection unit configured to measure the threshold voltage of each FET included in the at least two FET pairs. 
         [0009]    In one embodiment, at least one inspection unit is further configured to compare the measured threshold voltage of each FET included in at least two FET pairs against a known reference threshold voltage. In one instance, at least one inspection unit is configured to provide an indication of an undersized mask bias error when the measured threshold voltage of each FET included in at least two FET pairs is smaller than the known reference threshold voltage. In a similar manner, at least one inspection unit is configured to provide an indication of an oversized mask bias error when the measured threshold voltage of each FET included in at least two FET pairs is larger than the known reference threshold voltage 
         [0010]    In another embodiment of the present invention, the inspection unit is configured to compare the measured threshold voltage of each FET from at least two FET pairs against each other. In one embodiment, the inspection unit is configured to provide an indication of a vertical mask alignment error when at least one FET pair is vertically aligned, and when the measured threshold voltage of at least two of the FETs within the aligned FET pair is different. Similarly, the inspection unit may also be configured to provide an indication of a horizontal mask alignment error when at least one FET pair is horizontally aligned, and when the measured threshold voltage of at least two of the FETs within the aligned FET pair is different. 
         [0011]    In yet another embodiment of the present invention, an inspection unit is positioned at each corner of a mask reticle, wherein each of the inspection units is configured to measure mask alignment errors. In one embodiment, the apparatus analyzes the direction of alignment errors provided by at least one inspection unit in order to determine a mask rotation error, and the direction of the mask rotation. 
         [0012]    The present invention also provides a method for detecting ion implant mask misalignment, rotation and bias errors in semiconductor fabrication, wherein the method includes the step of positioning at least one mask alignment, rotation and bias measurement (MARB) unit having at least two field effect transistor (FET) pairs during semiconductor manufacturing such that a gate region within each FET receives ion dopants from an ion implant process. The method further includes the step of measuring, via an inspection unit within the MARB, threshold voltages of each FET included in the at least two FET pairs. 
         [0013]    One skilled in the art will appreciate that many variations are possible within the scope of the claims. Thus, while the disclosure is particularly shown and described above, it will be understood by those skilled in the art that these and other changes in form and details may be made therein without departing from the spirit and scope of the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. 
           [0015]    It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
           [0016]      FIG. 1  (Prior Art) illustrates a known photolithography technique for creating multiple layers of circuit patterns on a chip. 
           [0017]      FIG. 2  (Prior Art) illustrates a view of a silicon wafer undergoing ion implantation as known in the art. 
           [0018]      FIG. 3A-3B  illustrates a general and detailed view of a mask alignment, rotation and bias measurement unit. 
           [0019]      FIGS. 4A-4D  illustrate examples of the mask alignment, rotation and bias measurement unit illustrated in  FIG. 3  with varied misaligned and biased mask overlays. 
           [0020]      FIGS. 5A-5F  illustrate cross-section views of a FET in the MRB measurement unit described in  FIGS. 3A-3B . 
           [0021]      FIGS. 6A-6B  illustrate an overhead view of a mask reticle designed to work in conjunction with the mask alignment, rotation and bias measurement unit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]      FIG. 1  (Prior Art) illustrates a known photolithography technique for creating multiple layers of circuit patterns on a chip. In particular,  FIG. 1  shows a photoresist coated substrate  110 . The photoresist coated substrate  110  is exposed to a UV light  102  shown through a reticle  106  with a mask pattern  104 . The mask pattern  104  is larger than the final pattern projected on substrate  110  and is reduced by a reduction lens  108  before exposing the photoresist coated substrate  110 . 
         [0023]      FIG. 2  (Prior Art) illustrates a view of a silicon wafer undergoing a light threshold voltage tailor implant as known in the art.  FIG. 2  shows the different layers of the circuit including a lightly doped P-silicon wafer  218 , and a photoresist region  206  formed on the wafer. Lightly doped P-silicon wafer  218  is implanted with dopants via an ion implantation doping process  202 . As shown, photoresist  206  prevents ion implantation of those regions of lightly doped P-silicon wafer  218  covered by the photoresist. In those regions of lightly doped P-silicon wafer  218  not covered by the photoresist, a lightly doped ion implant area  212  is created. 
         [0024]      FIG. 3A  illustrates a general view of one embodiment of a mask alignment, rotation and bias measurement (MARB) unit  300  coupled to a parametric test unit (PTU)  390 .  FIG. 3B  illustrates a detailed embodiment of the MARB measurement unit  300 . The embodiment includes two sets of paired field effect transistors (FET) including a first pair to measure vertical (up/down) alignment ( 350  and  370 ) and a second pair to measure horizontal (left/right) alignment ( 340  and  360 ). In alternate embodiments, additional FETs make be positioned around the periphery of the mask without departing from the scope and spirit of the present invention. 
         [0025]    MARB measurement unit  300  is positioned such that the area exposed during the ion implant process overlaps a portion of gate region  308  of each FET instance. In particular, the MARB measurement unit  300  is overlaid with an ion implant mask  320  that opens an image that, once developed, exposes the sections of each FET within the ion implant mask  320 . The exposed sections, including an interior source/drain region  310  of each FET and the gate region  308  as previously noted, receive ion dopants that impact the operation of each FET instance. Specifically, the ion dopants in the gate region  300  alter the threshold voltage of the FET. Differing ion dopants may be employed in accordance with the present invention with may either raise or lower the threshold voltage of the gate regions within each FET. For the purposes of illustration, the embodiment described herein utilizes a light P dopant for the ion implant process which effectively raises the threshold voltage of the FET. The PTU  390  coupled to the MARB measurement unit  300  compares the threshold voltage results across the FET instances with threshold voltage results of a perfectly aligned ion implant process. Based on the variations in threshold voltages across FET instances the PTU  390  is configured to determine misalignment and bias. 
         [0026]      FIGS. 4A-4D  illustrate examples of the mask alignment, rotation and bias measurement unit illustrated in  FIG. 3  with varied misaligned and biased mask overlays.  FIG. 4A  shows a horizontally misaligned mask. In this instance, mask  404 A is shifted horizontally to the left, such that gate region  308 C in gate  310 C receives a relatively higher amount of ion dopants than the perfectly aligned gate  360  shown in  FIG. 5B , since only a small portion of the mask covers gate region  308 C during the implant process. In contrast, gate region  308 A in gate  310 A receives a relatively lower amount of ion dopants, since gate region  308 A is mostly masked from receiving ion dopants during the implant process (i.e., only a very small region at the leftmost edge of gate  308 A is unmasked and will receive ion dopants. The increased amount of ion dopants received in gate region  308 C relative to the perfectly aligned gate  310  in  FIG. 3B  raises the voltage threshold of gate  310 C relative to the voltage threshold of a normally aligned gate, and the decreased amount of ion dopants received in gate region  308 A relative to the perfectly aligned gate  310  in  FIG. 3B  lowers the voltage threshold of gate  310 A. This is an indication to PTU  390  that the mask is misaligned to the left. By way of contrast, vertically aligned gate regions  308 B and  308 D receive an equivalent amount of ion dopants, since in both instances mask  404 A bisects the gate regions. Thus, the vertical mask alignment is perfect, in this instance. As long as the mask (either aligned or misaligned) remains positioned somewhere within the gate regions  308 A and  308 C, the degree of misalignment can be directly determined by the corresponding voltage threshold change in the gate, as compared to the voltage threshold of the perfectly aligned gate of  FIG. 3B . 
         [0027]      FIG. 4B  shows a vertically misaligned mask. In this instance, mask  404 B is shifted vertically downward, such that gate region  308 B in gate  310 B receives a relatively higher amount of ion dopants compared to the normally aligned gate  350  shown in  FIG. 3B , since only a small portion of the mask covers gate region  308 B during the implant process. In contrast, gate region  308 D in gate  310 D receives a relatively lower amount of ion dopants, since gate region  308 D is almost completely masked from receiving ion dopants during the implant process. The increased amount of ion dopants received in gate region  308 B relative to the perfectly aligned gate  310  in  FIG. 3B  raises the voltage threshold of gate  310 B, and the decreased amount of ion dopants received in gate region  308 D relative to the perfectly aligned gate  310  in  FIG. 3B  lowers the voltage threshold of gate  310 D. This is an indication to PTU  390  that the mask is misaligned vertically downward. By way of contrast, horizontally aligned gate regions  308 A and  308 C receive an equivalent amount of ion dopants, since in both instances mask  404 A bisects the gate regions. Thus, the horizontal mask alignment is perfect, in this instance. As long as the mask (either aligned or misaligned) remains positioned somewhere within the gate regions  308 B and  308 D, the degree of misalignment can be directly determined by the corresponding voltage threshold change in the gate, as compared to the voltage threshold of the perfectly aligned gate of  FIG. 3B . 
         [0028]      FIG. 4C  shows a biased mask, wherein the mask is undersized. As a result, all gate regions,  308 A- 308 D, receive an increased amount of ion dopants and consequently the threshold voltage across all gates is increased. PTU  390  is configured to interpret the increased voltage across all gates as compared to a known reference voltage as an indication of an undersized mask. In one embodiment, the known reference voltage may be predefined. In another embodiment, the known reference voltage is measured from a reference FET (i.e., a FET positioned in an area of the semiconductor where no mask bias error can come into play). 
         [0029]      FIG. 4D  shows a biased mask, wherein the mask is oversized. As a result, all gate regions,  308 A- 308 D, receive a decreased amount of ion dopants and consequently the threshold voltage across all gates is decreased. PTU  390  is configured to interpret the decreased voltage across all gates as compared to a known reference voltage as an indication of an oversized mask. In one embodiment, the known reference voltage may be predefined. In another embodiment, the known reference voltage is measured from a reference FET (i.e., a FET positioned in an area of the semiconductor where no mask bias error can come into play). 
         [0030]      FIGS. 5A-5F  illustrate cross-section views of a FET in the MRB measurement unit described in  FIGS. 3A-3B . In particular,  FIG. 5A  shows a P-silicon wafer  510  having a plurality of recessed shallow trench isolation (STI) regions  520 . STI regions  520  provide gate isolation between FETs. The P-silicon wafer  510  is covered with a photoresist  506 , effectively creating an ion implant mask region. Photoresist can be created by either a positive or negative mask process. Within the P-silicon wafer  510 , a future source, drain and body area  540  is defined between the STI regions  520 , and a future gate electrode and gate dielectric region  550  is defined on top of the future source, drain and body area  540 . Thus a portion of the future source, drain and body area  540  and a portion of the future gate electrode and gate dielectric area  550  will be exposed to a subsequent ion implant process, further described in  FIG. 5B . 
         [0031]      FIG. 5B  shows an ion implant process step, wherein a VT tailor implant of light P dopants are dispersed on the top surface of the photoresist  506 , and the non-photoresist covered portions of the P-silicon wafer  510 . The photoresist  506  will prevent the light implant of P dopants from reaching covered portions of the P-silicon wafer  510 , whereas the light dopants will be implanted in areas of the silicon wafer  510  not covered by the photoresist, creating a modified P-area  570 . A portion of the area within the future source, drain and body area  540  is masked from the light implant of P dopants, leaving an unmodified P-area  571 . 
         [0032]    In  FIG. 5C  a FET gate  585  is formed over a portion of the modified P-area  570  and the unmodified P-area  571 , the FET gate  585  comprising a gate dielectric region  556  and a gate electrode  558 .  FIG. 5C  is illustrative of a gate formed over a perfectly aligned modified P-area  570 . In this embodiment, approximately half of the area under the gate  585  is modified P-area  570 , and approximately half of the area under the gate  585  is unmodified P-area  571 . 
         [0033]      FIG. 5D  illustrates an N+ implant process step  582  performed over the perfectly aligned FET of  FIG. 5C . In the example, N+ regions  586 A and  586 B are created on the P-silicon wafer  510  directly adjacent to the gate area  585 . Gate  558  serves as a mask to that the N+ implant does not affect the remaining modified P-area  570 . 
         [0034]      FIG. 5E  illustrates an ion implant step similar to that shown in  FIG. 5B , however in this figure, the ion implant mask used in an earlier step is misaligned (e.g., the etched away photoresist areas  506  defining the ion implant mask are shifted to the right, when compared with the photoresist areas shown previously in  FIG. 5B ). This is indicated by a misalignment indicator  588 . As a result, a larger unmodified P-area  571  (i.e. an area that did not receive the light P dopant during the VT tailor ion implant) exists under the gate  585  next to the modified P-area  570 . Thus, the voltage threshold of the gate  585  is reduced. 
         [0035]      FIG. 5F  illustrates a section of the PTU  390  connected to the FET in the MRB measurement unit. The PTU  390 , using contacts  598  placed on the gate, source, and drain of the FET, measures threshold voltage to determine misalignment and bias. 
         [0036]      FIGS. 6A-6B  illustrate overhead views of a mask reticle  106 A with an ion implant mask  606 A- 606 D at each corner of the mask reticle  106 A. The ion implant mask  606 A opens an image at each corner of the mask reticle that, once developed, exposes the interior sections of each MARB measurement unit  300  instance. If the mask reticle  106 A is rotated out of position, as shown in  FIG. 6B , each ion implant mask  606 A shifts, leaving sections unexposed that should be exposed or vice versa. The shift results in a variation in gate threshold voltage across all MARB measurement unit instances, indicating a particular type of rotation. For example, if PTU  390  identifies that ion implant masks  606 A and  606 C are misaligned upward and  606 B and  606 D are misaligned downward, PTU  390  flags the mask reticle as having undergone a counter-clockwise rotation.