Abstract:
An optical receiver implemented with two electronic dispersion compensators (EDC) is disclosed. The optical receiver selects one of the EDC in an ordinary operation. Once there shaped signal compensated by the selected EDC is degraded due to irregular conditions of the optical transmission line, the optical transmitter and so on, the optical receiver reconfigures the tap coefficients of the unselected EDC and switches to the newly configured EDC after setting the tap coefficients for the new condition of the transmission line and the transmitter.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an optical receiver and a method to control the optical receiver. 
         [0003]    2. Related Prior Arts 
         [0004]    An electrically compensating method for the dispersion attributed to a multimode fiber has been developed. The method is called as the electrical dispersion compensator (hereafter denoted as EDC). A Japanese patent application published as JP-H08-163027A has disclosed one of circuits applicable to the EDC. The circuit disclosed therein is a type of optical signal processor and includes a plurality of delay units that sequentially delays a signal converted from the received optical signal and outputs thus delayed signals in parallel, a plurality of multipliers each coupled with one of delay units and multiplying the delayed signal by a coefficient unique to the delay unit, an adder that sums up respective outputs of the multiplier, and an arithmetic unit to evaluate the coefficients, which is one type of, what is called, transversal filter. 
         [0005]    Optimum multiplied coefficients set in the multipliers strongly depend on the optical transmission line. The aged deterioration, the tensile stress or the bent status of the fiber, and so on, affects the optimum multiplied coefficients. Thus, the EDC is necessary to evaluate the optimum coefficients by the arithmetic unit. However, depending on the conditions of the transmission line, the arithmetic unit is occasionally unable to evaluate the optimum multiplied coefficients, which results in a drastic increase of the bit error rate. 
         [0006]    Even in such a case that the arithmetic unit could not reach the optimum coefficients, the transversal filter sometimes gives the optimum set of multiplied coefficients by resetting whole coefficients. However, the resetting the filter means that, the optical receiver implementing this filter is unavoidable to be temporarily ceased. Thus, an aspect of the present invention is to provide an optical receiver with a function to adjust or to reset the multiplied coefficients of the transversal filter without suspending the optical receiver. 
       SUMMARY OF THE INVENTION 
       [0007]    One aspect of the present application relates to a configuration of an optical receiver implementing at least two EDCs. The optical receiver further includes a front end receiver, a selector and a controller. The front end receiver converts an input optical signal into a corresponding electrical signal and transmits this electrical signal to the EDCs. The selector selects one of outputs of the EDCs. The controller decides which outputs of the EDCs should be selected by the selector. The at least two EDCs may provide the same configuration to each other. 
         [0008]    According to the optical receiver of the present application, when a difference between an analog signal reshaped from the converted electronic signal and a digital signal discriminated from the reshaped analog signal exceeds a preset level, the controller may command the selector to select another EDC after the other EDC reconfigures a set of tap coefficients. 
         [0009]    The optical receiver of the present application may further provide a clock data recovery (CDR) that receives an output of the selector, that is, the output of the currently selected EDC. In the S present invention, the selector may select the other EDC in synchronous with the clock data contained in the output of the currently selected EDC. 
         [0010]    Another aspect of the present application relates to a method to control an optical receiver implementing at least two EDCs. The method includes steps of: (1) watching a difference between an analog output of the currently selected EDC, which is reshaped from an output of a front end receiver, and a digital output discriminated from the analog output of the EDC, and (2) selecting another EDC, when the watched difference of the currently selected EDC exceeds a preset level, after the other EDC reconfigures a set of tap coefficients of the transversal filter. 
         [0011]    The method may further include a step to revise the preset level to a difference between the analog data and the digital data of the other EDC when the other EDC reconfigures the set of tap coefficients, or to a new level greater by a preset increment than the difference of the other EDC whose set of the tap coefficient is configured. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]      FIG. 1  is a block diagram of an optical receiver according to an embodiment of the present invention; 
           [0013]      FIG. 2  is a block diagram of an electronic dispersion compensator implemented within the optical receiver of the present invention; and 
           [0014]      FIG. 3  is a flow chart to switch between two electronic dispersion compensators. 
       
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0015]    Next, preferred embodiments of the present invention will be described as referring to accompanying drawings. In the description of the drawings, the same numerals or the same symbols will refer to the same elements without overlapping explanations as possible. 
         [0016]      FIG. 1  is a block diagram of an optical receiver according to an embodiment of the invention. The optical receiver  1  comprises a front end receiver  2 , a first EDC  4   a , a second EDC  4   b , a selector  6 , a clock data recovery (hereafter denoted as CDR)  8 , and a controller  10 . The front end receiver  2  receives an optical signal transmitted in an optical fiber F and converts this optical signal into an electrical signal. This electrical signal is commonly provided with the first and second EDCs,  4   a  and  4   b . The front end receiver  2  also provides a status signal K 1  to the controller  10 . The status signal K 1  decides whether the front end receiver  2  receives no or substantially no optical signal, and this status is often called as “Loss Of Signal (LOS)” state. 
         [0017]    The first and second EDCs,  4   a  and  4   b , are disposed between the front end receiver  2  and the selector  6 , that is, each input of the EDC,  4   a  or  4   b , receives the output of the front end receiver  2 , while, the output thereof is coupled with the input of the selector  6 . Each EDC,  4   a  or  4   b , provides a transversal filter able to reduce the influence of the dispersion due to the optical F by adjusting the multiplied coefficients of the filter. This dispersion is reflected in the optical signal received by the front end receiver  2 . 
         [0018]    The first EDC  4   a  reshapes the electrical signal coming from the front end receiver  2 , and outputs this reshaped signal to the selector  6 . Thus, the EDC  4   a  is a type of the electronic dispersion correction circuit. The first EDC  4   a  also outputs a first differential signal K 2  to the controller  10 . This differential signal K 2  corresponds to a difference between the reshaped signal in an analog form and a digital signal converted from this reshaped signal. The differential signal K 2  is used to adjust the multiplied coefficients. The arithmetic unit included in the transversal filter may reduce the difference between the analog signal and the digital signal above described. 
         [0019]    The multiplied coefficient is often called as the tap coefficient of the transversal filter and, as illustrated in  FIG. 2 , includes a plurality of forward coefficients, c 0  to c m , and a plurality of feedback coefficients, d 0  to d m . The differential signal K 2  is a difference of the output of the EDC  4   a . When the EDC receives the first reset K 3  from the controller  10 , the EDC resets all tap coefficients, namely, the EDC sets all coefficients to be zero. Negating the reset K 3 , the EDC begins to adjust the tap coefficients. 
         [0020]    The second EDC  4   b  has the same configuration with that of the first EDC  4   a . The second EDC  4   b  generates the second difference K 4  to the controller  10 . This second difference K 4  is also used to adjust the tap coefficients in the second EDC  4   b . When the second EDC  4   b  receives the reset K 5  from the controller  10 , the second EDC  4   b  sets all tap coefficients to be zero, and begins the adjustment of the tap coefficients in synchronizing with the release of the reset K 5 . 
         [0021]    The selector  6  selects one of the outputs from the first EDC  4   a  and from the second EDC  4   b  by the command K 6  provided from the controller  10 ; and sends this selected output to the CDR  8 . The selector  6  also receives the clock K 7  recovered in the CDR  8 . Thus, the selector  6  may select one of the outputs in synchronizing with the clock K 7 . 
         [0022]    The CDR  8 , when it receives one of the outputs of the EDCs,  4   a  or  4   b , selected by the selector  6 , and recovers the clock contained in the output above mentioned. 
         [0023]    The controller  10  provides a central processing unit, which is often called as CPU, a ROM, a RAM, and so on. The CPU controls two EDCs,  4   a  and  4   b , and the selector  6  by executing programs stored in the ROM or the RAM according to the flow chart shown in  FIG. 3 . The controller decides which outputs of the first EDC  4   a  or that of the second EDC  4   b  should be coupled with the CDR  8 , and sends the command K 6  based on this decision to the selector K 6 . 
         [0024]    For instance, in a case where the first EDC  4   a  couples with the CDR  6 , at the same time the second EDC  4   b  is in the reset mode, and the first difference K 2  of the first EDC  4   a  becomes greater than a preset level K 8 , the controller releases the second reset K 5  to the second EDC  4   b , which starts the adjustment of the tap coefficients in the second EDC  4   b  such that the second difference K 4  becomes less than the preset level K 8 . After the second difference K 4  converges in a level less than the preset level K 8 , the controller sends a command K 6  to the selector  6  so as to select the output of the second EDC  4   b  to couple with the CDR  8 . The preset level K 8  may be held in the ROM or the RAM. 
         [0025]      FIG. 2  is a block diagram of the EDC,  4   a  or  4   b , according to the present invention. In the present invention, the first and second EDCs,  4   a  and  4   b , have the same configuration to each other. The EDC  4   a  includes the transversal filter  40  and an adjustor  48 . The transversal filter  40  is configured with a feed forward equalizer (hereafter denoted as FFE)  41 , a decision feedback equalizer (hereafter denoted as DFE)  42 , an adder section  44 , and a discriminator  46 . The transversal filter  40  receives an electrical output of the front end receiver  2 , reshapes this output and sends the reshaped output to the selector  6 . 
         [0026]    The FFE  41  includes a plurality of delay units, T C1  to T Cm , where m is an integer greater than unity, and a plurality of multipliers, C 0  to C m . These delay units and the multipliers constitute taps, P C0  to P Cm , of the FFE  41 . The DFE  42  includes a plurality of delay units, T D0  to T Dn , where n is an integer greater than unity, and a plurality of multipliers, D 0  to D n . These delay units and the multipliers constitute taps, P D0  to P Dn , of the DFE. 
         [0027]    The first tap P C0  includes only the first multiplier C 0 , while, other taps, P C1  to P Cm , and taps, P D0  to P Dn , in the DFE include both the delay unit and the multiplier. The delay unit T Ck  delays an signal coming from the upstream delay unit T C(k−1)  by one bit and outputs this delayed signal to both the downstream delay unit T C(k+1)  and the multiplier C k . While, the delay unit T Dj  in the DFE delays a signal coming from the upstream delay unit T D(j−1)  by one bit and outputs this delayed signal to both the downstream delay unit T D(j+1)  and the corresponding multiplier D j . 
         [0028]    The first multiplier, C 0 , multiplies the signal from the front end receiver  2  by the tap coefficient c 0  and outputs the product to the adder  44 . The subsequent multiplier, C k , multiplies the signal output from the delay unit T ck  by the tap coefficient c k , and sends the product to the adder  44 . 
         [0029]    The adder  44  sums up the products each sent from the multipliers, C 0  to C m , and also sums up the products sent from the other set of multipliers, D 0  to D n , in the DFE  42 . The adder  44  outputs thus summed up products to the selector  6 . 
         [0030]    The discriminator  46  decides the level of the output of the adder  44 , that is, the discriminator  46  judges whether the output of the adder  44  is in the level “1” or in the level “0” digitally, and sends the discriminated result to the first delay unit T D0  in the DFE  42 . The difference between the input of the discriminator  46  and the output thereof corresponds to the difference signal K 2 , which is K 4  for the second EDC  4   b . Thus, the difference signal, K 2  or K 4 , is a difference between the reshaped analog signal and its digitally converted signal. Accordingly, the difference signal, K 2  or K 4 , becomes an index how close the reshaped analog signal to the digital signal to be recovered. This difference signal, K 2  or K 4 , is sent to the adjustor  48  and also to the controller  10 . 
         [0031]    The adjustor  48  adjusts the tap coefficients, c 0  to c m  in the FFE  41  and d 0  to d n  in the DFE  42  such that the difference signal K 2  becomes less than a preset level. When an adequate level of difference signal K 2  is obtained, the adjustor  48  fixes the whole tap coefficients. The multipliers, C 0  to C m  in the FFE  41  and D 0  to D n  in the DFE, multiply respective delayed signals by thus fixed tap coefficients, c 0  to c m  and d 0  to d n . Accordingly, the transversal filter  40  may reshape the output of the front end receiver  2  adequately and electrically reduce the influence of the dispersion of the fiber. 
         [0032]    The adjustor  48  may reset the whole tap coefficients, c 0  to c m  and d 0  to d n , namely, set to zero, in synchronous with the assertion of the reset command K 3  from the controller  10 . Negating the command K 3 , which means that the reset is released, the adjustor  48  begins to adjust the tap coefficients. 
         [0033]    Next, an operation of the optical receiver will be described as referring to  FIG. 3 . An exemplary case is assumed, where the front end receiver  2  outputs no substantial signal to two EDCs,  4   a  and  4   b , due to some failures of the optical transmitter or the optical transmission line. In this case, the front end receiver  2  outputs a status signal K 1  (Loss-Of-Signal: LOS) to the controller  10 , and the controller  10  resets two adjustors  48  in respective EDCs,  4   a  and  4   b , by asserting the commands K 3  and K 5 , at step S 01 . The controller subsequently watches whether the status signal LOS (K 1 ) is reset or not, that is, whether the front end receiver  2  outputs a substantial signal to both EDCs,  4   a  and  4   b , at step S 02 . Once resetting the status signal LOS (K 1 ), the procedure advances step S 03 . 
         [0034]    The controller  10  negates one of resets, K 3  or K 5 , in step S 03 . It is assumed for the explanation sake that the first reset K 3  to the first EDC  4   a  is negated. The tap adjustor  48  in the first EDC  4   a , responding to the negation of the reset K 3 , begins to adjust the tap coefficients, c 0  to c m  and d 0  to d n , based on the first difference K 2 . Subsequently, the controller  10  watches whether the first difference K 2  becomes less than the preset level K 8  at step S 04 . 
         [0035]    When the first difference K 2  becomes less than the preset level K 8 , in which the tap adjustor  48  in the first EDC  4   a  fixes the whole tap coefficients, c 0  to c m  and d 0  to d n , the controller  10  changes the preset level K 8 , which is the subject of the comparison between the analog and the digital signals, to the first difference K 2  or a difference greater than the first difference by a preset increment, and stores thus revised preset level in the RAM. Concurrently with the saving of the new preset level, the controller  10  sends the command K 6  (Select) to the selector  6  such that the selector  6  selects the output from the first EDC  4   a , at step S 05 . During the steps S 03  to S 05 , the controller continues to assert the second reset K 5  to the second EDC  4   b.    
         [0036]    The controller also continues to watch the status signal LOS (K 1 ) at step S 07 . Once deciding the status signal LOS (K 1 ) is asserted, the optical receiver  1  iterates the operation from step S 01 . During the status signal LOS (K 1 ) is negated, the controller  10  continuously watches the first difference K 2  and decides whether the first difference K 2  exceeds the preset level K 8  or not, which was set at step S 05 , at step S 08 . During the first difference K 2  is less than the preset level K 8 , the controller  10  iterates the watching of the status signal LOS (K 1 ) and the first difference K 2 . 
         [0037]    When the first difference K 2  exceeds the present level K 8 , the controller  10  releases the second reset K 5  for the second EDC  4   b  at step S 09 . The tap adjustor  48  in the second EDC  4   b , responding to the negation of the second reset K 5 , begins to adjust the tap coefficients by using the second difference K 4 . The controller  10  watches whether the second difference K 4  becomes less than the preset level K 8 , at step S 10 . 
         [0038]    After the convergence of the second difference K 4 , the tap adjustor  48  in the second EDC  4   b  fixes the whole tap coefficients thereof, c 0  to c m  and d 0  to d n , while, the controller  10  changes the preset level K 8  to the current second difference K 4 , or a value greater than the second difference K 4  by the preset increment and saves this revised preset level K 8  in the RAM. Concurrently with the saving of the revised preset level K 8 , the controller  10  commands the selector  6  so as to select the output of the second EDC  4   b  by sending the signal K 6  at step  11  and resets the first EDC  4   a  by sending the first reset K 3  at step  12 . 
         [0039]    After switching the input of the CDR  8 , the controller  10  continues to watch the signal status LOS (K 1 ) and the second difference K 4  at step  13 . When the status LOS (K 1 ) is asserted, the procedure jumps to step S 01 . When the status LOS (K 1 ) is negated but the second difference K 4  exceeds the preset level K 8 , the procedure jumps to step S 03 . 
         [0040]    Thus, the optical receiver according to the described embodiment implements two EDCs,  4   a  and  4   b . When the first EDC  4   a  is selected so as to be coupled with the CDR  8  and the first difference K 2  thereof exceeds the preset level K 8 , the optical receiver  1  may adjust the tap coefficients in the second EDC  4   b  as keeping the output of the first EDC  4   a  to be coupled with the CDR  8 . After the adjustment of the tap coefficients in the second EDC  4   b  is completed, the optical receiver  1  may switch the output of the second EDC  4   b  to be coupled with the CDR  8 . Accordingly, the optical receiver  1  may readjust the tap coefficients of the EDC without interrupting the normal operation of the optical receiver. Moreover, the selector  6  receives the clock from the CDR  8 , the switching between two outputs of the two EDCs may be synchronized with the clock, which may release the optical receiver  1  from interposing a dead time for the switching. 
         [0041]    While the preferred embodiments of the present invention have been described in detail above, many changes to these embodiments may be made without departing from the true scope and teachings of the present invention. For instance, the embodiments above described concentrates on a case where two EDCs,  4   a  and  4   b , provide the same configuration to each other. However, the EDCs may have different arrangements. Moreover, the optical receiver may implement three or more EDCs to show the function described above. The present invention, therefore, is limited only as claimed below and the equivalents thereof.