Abstract:
We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

Description:
REFERENCE TO RELATED PATENT APPLICATIONS  
       [0001]     This application claims the priority from Korean Patent Application No. 2004-33380 filed on May 12, 2004, which we incorporate by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an integrated circuit, and more particularly to an internal signal replication device and method.  
         [0004]     2. Description of the Related Art  
         [0005]     To precisely generate clock signals, integrated circuits include duty cycle compensation circuits to compensate for duty cycle variances of an externally provided clock signal. A typical integrated circuit with a duty cycle compensation circuit will now be described with reference to  FIG. 1 .  FIG. 1  is a block diagram of an integrated circuit  100  with a duty cycle compensation circuit  110 . The duty cycle compensation circuit  110  includes a DLL  111  to generate N delayed versions of an externally generated clock signal ECLK and a phase mixer  112  to generate a replica clock signal CLK_R according to the N delayed clock signals. A data output unit  120  receives cell data from a memory cell array (not shown) and transmits the cell data DQ responsive to the replica clock signal CLK_R. Integrated circuit  100  may be a memory as disclosed in Korean patent laid-open publication No. 2003-88232.  
         [0006]     The relationship among the external clock signal ECLK, the replica clock signal CLK_R, and the memory cell data DQ is illustrated in  FIG. 2 .  FIG. 2  is a timing diagram illustrating the operation of integrated circuit  100  shown in  FIG. 1 . Referring to  FIG. 2 , the integrated circuit  100  receives external clock signal ECLK and generates the replica clock signal CLK_R from the external clock signal ECLK. Since the integrated circuit  100  compensates for the duty cycle of the external clock signal ECLK when generating the replica clock signal CLK_R, there is a delay or latency between the reception of the external clock signal ECLK and the generation of the replica clock signal CLK_R. The integrated circuit  100  transmits the cell data DQ responsive to the replica clock signal CLK_R.  
         [0007]     Testing the internal signals of integrated circuit  100 , e.g., the delayed clock signals generated by the DLL  111  or signals for controlling the operation of memory cell array (not shown), remains difficult. For instance, to measure the internal signals the package containing the integrated circuit  100  must be decapped and probed using a probe tip or measured using electron beam (E-beam) probing with an oscilloscope. This testing process is not only inconvenient and complicated, but the results are potentially inaccurate since the internal signals are measured in a substantially different environment. In other words, decapping the package containing the integrated circuit  100  exposes the circuit to external noise, and thus internal signals are likely to be inaccurately measured.  
       SUMMARY OF THE INVENTION  
       [0008]     We describe a circuit including a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.  
         [0009]     We also describe a method including selecting one of a plurality of clock signals, and replicating the selected clock signal from a reference clock signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The features and advantages of the present invention will become more apparent with the detailed description of the exemplary embodiments with reference to the attached drawings.  
         [0011]      FIG. 1  is a block diagram of an integrated circuit with a conventional duty cycle compensation circuit.  
         [0012]      FIG. 2  is a timing diagram illustrating the operation of integrated circuit shown in  FIG. 1 .  
         [0013]      FIG. 3  is a block diagram of an integrated circuit with a duty cycle compensation circuit according to an embodiment of the present invention.  
         [0014]      FIGS. 4-6  are timing diagrams illustrating the operation of the integrated circuit shown in  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]      FIG. 3  is a block diagram of an integrated circuit  300  with a duty cycle compensation circuit  320  according to an embodiment of the present invention. Referring to  FIG. 3 , the integrated circuit  300  includes a memory cell array  310 , a duty cycle compensation circuit  320 , a data output unit  330 , and a clock signal selector  340 . The integrated circuit  300  may be a memory such as a Rambus Dynamic Random Access Memory (RDRAM) and Double Data Rate (DDR). Although  FIG. 3  illustrates the integrated circuit  300  as a memory with the memory cell array  310 , the present invention is not so limited and may be an apparatus that processes a video/audio signal, a transceiver for communications, or include a functional unit that provides data to data output unit  330  responsive to control signals.  
         [0016]     The memory cell array  310  writes data to or reads data from the memory cells (not shown), responsive to input control signals such as a Row Action Signal (RAS), a Column Action Signal (CAS), or a precharge control signal. A person of skill in the art knows well use of the RAS, the CAS, and the precharge control signal when accessing memory.  
         [0017]     In a normal operation mode, the duty cycle compensation circuit  320  generates a replica clock signal CLK_R by compensating for the duty cycle or duty factor of an external clock signal ECLK. The duty factor represents a percentage of a clock period, typically 50%, which is logically high. To guarantee the normal operation of the system, the duty cycle compensation circuit  320  generates the replica clock signal CLK_R with a constant duty factor. The memory cell array  310  provides cell data to the data output unit  330 , where the data output unit  330  latches the cell data in response to the replica clock signal CLK_R. The latched cell data DQ may be provided to an external DQ pin via a DQ pad (not shown).  
         [0018]     In a test operation mode, the clock signal selector  340  selects one of the internal clock signals INTCLK 1 -INTCLKN responsive to a Mode Register Set (MRS) code. The internal clock signals INTCLK 1 -INTCLKN may be generated internally to integrated circuit  300 . The clock signal selector  340  may include a MRS register (not shown) to store the MRS code. A person of skill in the art knows well the use of MRS codes to test memory devices.  
         [0019]     The duty cycle compensation circuit  320  generates the replica clock signal CLK_R by compensating for the duty factor of the selected internal clock signal in response to the external clock signal ECLK and the selected internal clock signal. In other words, the external clock signal ECLK is a reference clock signal used by duty cycle compensation circuit  320  to generate a replica of the selected internal clock signal. The data output unit  330  outputs data DQ responsive to the replica clock signal CLK_R. The memory cell array  310  may be controlled by the internal clock signals INTCLK 1 -INTCLKN.  
         [0020]     The duty cycle compensation circuit  320  includes a delay locked loop (DLL)  321  and a phase mixer  322 . The DLL  321  generates a plurality of delay signals with different phases by delaying the external clock signal ECLK responsive to the difference in phase between the replica clock signal CLK_R and the selected internal clock signal. The phase mixer  322  mixes the phases of the delay signals and generates the replica clock signal CLK_R by correcting the duty factor of the external clock signal ECLK. In other words, the phase mixer  322  generates the replica clock signal CLK_R with a duty factor of 50% in-phase with the selected internal clock signal.  
         [0021]     The DLL  321  includes a plurality of delay cells  323 , a delay compensator  324 , a phase detector  325 , and a controller  326 . Each delay cell  323  generates a delay signal in response to a current control signal from the controller  326 . The delay compensator  324  delays the replica clock signal CLK_R by a time delay TD corresponding to the time required for the cell data DQ to propagate through the data output unit  330  once latched responsive to the replica clock signal CLK_R. The phase detector  325  detects the difference in phase between the delayed replica clock signal CLK_R and the selected internal clock signal. The controller  326  generates the current control signal proportional to the difference in phase detected by the phase detector  325  and provides the current control signal to the plurality of delay cells  323 . In the normal operation mode, the clock signal selector  340  selects the external clock signal ECLK and the phase detector  325  detects the difference in phase between the delayed replica clock signal CLK_R and the external clock signal ECLK. Although  FIG. 3  shows the DLL  321  including a delay compensator  324  to delay the replica clock signal CLK_R as it is feedback into DLL 321 , in some embodiments it may be advantageous to omit the delay compensator  324 .  
         [0022]     The operation of the integrated circuit  300  will now be described in detail with reference to  FIGS. 4-6 .  FIG. 4  is a timing diagram illustrating the operation of integrated circuit  300  in the normal operation mode. Referring to  FIG. 4 , in the normal operation mode, the integrated circuit  300  generates the replica clock signal CLK_R in-phase with the external clock signal ECLK, and thus the cell data DQ is synchronized with the external clock signal ECLK. The data output unit  330  provides the data DQ at time T 3  after the external clock signal ECLK is activated. The external clock signal ECLK and the cell data DQ may be measured using a tester such as oscilloscope.  FIG. 4  shows the timing of the internal clock signals INTCLK 1  and INTCLK 2 , where the two internal clock signals INTCLK 1  and INTCLK 2  are activated at times T 1  and T 2  after the external clock signal ECLK is activated, respectively.  
         [0023]      FIGS. 5 and 6  are timing diagrams illustrating the operation of integrated circuit  300  in the test operation mode. Referring to  FIG. 5 , in a test operational mode, the clock signal selector  340  selects internal clock signal INTCLK 1  using the MRS code as described above, and the duty cycle compensation circuit  320  generates the replica clock signal CLK_R in-phase with the selected internal clock signal INTCLK 1  at time T 4  after activation of the external clock signal ECLK. The data output unit  330  outputs cell data DQ synchronized with the replica clock signal CLK_R and the selected internal clock signal INTCLK 1 . Thus, the cell data DQ and the external clock signal ECLK may be measured using a tester such as oscilloscope to determine the time T 4 , or the phase of the selected internal clock signal INTCLK 1  relative to the external clock signal ECLK.  
         [0024]     Referring to  FIG. 6 , in a test operational mode, the clock signal selector  340  selects internal clock signal INTCLK 2  using the MRS code as described above, and the duty cycle compensation circuit  320  generates the replica clock signal CLK_R in-phase with the selected internal clock signal INTCLK 2  at time T 5  after activation of the external clock signal ECLK. The data output unit  330  provides cell data DQ that is synchronized with the replica clock signal CLK_R and the selected internal clock signal INTCLK 2 . Thus, the cell data DQ and the external clock ECLK may be measured using a tester such as oscilloscope to determine the time T 5 , or the phase of the selected internal clock signal INTCLK 2  relative to the external clock signal ECLK.  
         [0025]     The times T 4  and T 5  may be compared to determine a margin between the corresponding internal clock signals, where the margin may be used to determine whether the internal clock signals are timed properly. For instance, when the margin between internal clock signals is improper, accesses to memory cell array  310  may not occur correctly. Accordingly, the design of the integrated circuit  300  may be altered or the integrated circuit  300  may be determined to be defective responsive to the margin. Although  FIGS. 5 and 6  show cell data DQ provided at times T 4  and T 5 , respectively, the integrated circuit  300  may provide cell data DQ according to any of the internal clock signals INTCLK 1 -INTCLKN. Thus, the timing of the internal clock signals INTCLK 1 -INTCLKN generated in the integrated circuit  300  may be determined without decapping the package. Furthermore, since each internal clock signal timing is measured in the same environment as normal operation of the integrated circuit  300 , the testing is hardly affected by noise, and precise and reliable results may be acquired.  
         [0026]     While embodiments of the present invention have been particularly shown, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the claimed invention.