Abstract:
An electronic driver circuit for comnmunicating a logic value along a conductor ( 12 ) from one part of a system ( 10 ) to another ( 14 ) by representing each of two logic values by one of two logic levels (V DD , V ss ).A capacitor (C R1 ) reduces ground and power reference differences between a chip containing the driver and the board on which it is mounted. The capacitor also provides power and ground decoupling. According to another aspect, a controlled slew rate ramp initiates an incident or outbound wave or turn-on and circuits are described for this. The time taken to complete the controlled slew rate ramp can be adjusted. The arrangements allow reduced power consumption, whilst at the same time producing desirable signal characteristics.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates to electronic circuits. In particular this invention relates to improving the performance of a type of electronic driver circuit the operation of which is intended to reduce power consumption. This invention relates to achieving low power consumption in such driver circuits, whilst at the same time producing desirable signal characteristics.  
       BACKGRUND TO THE INVENTION  
       [0002]     For many years conventional driver circuits have existed which communicate a logic value from one part of a system to another by representing each of two logic values respectively by one of two voltage levels. For example  FIG. 1   a  shows a conventional CMOS inverting driver  10  formed as part of an IC. Output driver  10  generates an inverted driver output voltage VDO in response to a driver input voltage signal VL. Driver  10  is connected through electrical conductor  12  printed wiring board (PWB) to load circuitry  14 . Specifically, electrical conductor  12  converts driver output voltage VDO into conductor output voltage VBO that drives a group of one or more digital ICs  16  in load  14 .  
         [0003]     Driver  10  is formed with N-channel insulated gate field effect transistor (‘FET’) QA and P-channel insulated gate FET QB whose gate electrodes receive driver input voltage VI. The sources of FET QA and QB respectively are connected to a source of low supply voltage VSS, typically ground reference (0 volts) and a source high supply voltage VDD. The QA and QB drains are connected together to provide driver output voltage VDO. N-channel FET QA is turned on by raising input voltage VI to suitably high level. On the other hand FET QB is turned on by reducing input voltage VI to a suitably low level.  
         [0004]     Accordingly, only one of FETs QA and QB is conductive during steady state operation. If input VI is high, FET QA is turned on to pull driver output voltage VDO to a low value close to VSS. Conversely, output voltage VDO is at a high value close to VDD when input voltage VI is low and causes FET QB to be turned on. The “on” resistance of each of FET QA and QB is normally quite low. Consequently output signal VDO makes a rapid transition from VSS to VDD in response to a rapid transition of input signal VI from high to low. Likewise output signal VDO makes a rapid transition from VDD to VSS in response to a rapid transition of input signal VI from low to high. During a transition there is a typically a brief period when both FETs QA and QB are conductive.  
         [0005]     PWB electrical conductor  12 , commonly referred to as an interconnect, consists of copper track and a ground plane at the VSS potential. The steps shown in the line passing through conductor  12  in  FIG. 1   a  qualitatively represent the changes in direction that conductor  12  makes on the PWB. The ground plane is represented by the block slanted shading.  
         [0006]     Since  FIG. 1   b  is a simplified electrical model, it does not show the parasitic lead inductances which typically exist when driver  10  is formed as part of an integrated circuit which is contained within an in integrated circuit package which is in turn mounted on a PWB. These parasitic inductances must be accounted for in the design of driver  10  if an undesirable effect known as ground/power bounce is to be avoided.  
         [0007]     Interconnect  12  in  FIG. 1   a  or  1   b  having distributed inductance and capacitance is alternatively known as a transmission line having characteristic impedance Z 0 . As is well known in the art, RON in  FIG. 1   b  is ideally chosen to match Z 0  so that a half amplitude outward bound wave is launched initially which doubles its amplitude on reaching load  14  and reflects back towards driver  10  as a fill amplitude wave. In the absence of RON or if RON is too small, the reflected wave is of an amplitude exceeding the level of VDD and causing signal integrity problems.  
         [0008]     In his previous application (PCT/GB96/02199, U.S. Pat. No. 6,201,420B1, EP0848868 etc), applicant describes a method by which, rather than generating a half amplitude outward bound wave by effectively by dropping voltage through a resistance RON, an equivalent wave can be launched by connecting signal VDO via a low “ON” resistance switch or transistor to an intermediate voltage VHH generated from an additional voltage supply or simply from a reservoir capacitor. The method has the advantage that less power is dissipated and the power consumption can be reduced by up to 75%. The technique is equally applicable to situations in which load capacitance CL is much larger than distributed capacitance CB in which case CL and LB act more like a sinusoidally LC resonant system than a transmission line. For ease of reference a driver employing the method will be referred to as a resonant line driver.  
         [0009]      FIGS. 2   a  and  2   b  show how the resonant line driver can equivalently replace conventional line driver of  FIG. 1   a  and  1   b.    
         [0010]      FIG. 2   b  for example shows a CMOS implementation of a resonant line driver. Q 1  and Q 3  can connect the driver output VDO to low and high voltage sources VSS and VDD respectively as in a conventional driver. Particular to the resonant line driver, Q 2  can connect driver output VDO also to an intermediate voltage source VHH during transitions. Gate electrodes (and therefore switching of Q 1 , Q 2  &amp; Q 3 ) are controlled by control circuit  20  via signals VC 1 , VC 2  &amp; VC 3  respectively. Since Q 1  and Q 3  are N channel MOSFET (NMOS) transistors, they provide a conductive path when VC 1  and VC 3  respective are at a high voltage level. Since Q 2  is a P channel MOSFETs (PMOS) transistor it provides a conductive path when VC 2  respective is at a low voltage level.  
         [0011]      FIG. 3  shows that intermediate voltage supply VHH can be supplied by a reservoir capacitor CR.  
         [0012]      FIG. 4  shows waveforms representative of the operation of the circuit shown in  FIG. 2   b  when CL is much larger than CB and CL and LB act more like a sinusoidally LC resonant system than a transmission line. Initially only Q 1  is “ON” and VDO is at a low level. Then in response to a change of level of the input signal VI at time t 1  Q 1  is switched “OFF” while Q 2  is switched “ON” driving VDO near to the level of VHH. Current builds sinusoidally to a maximum and then falls back to zero whilst at the same time the voltage seen at the load VBO swings sinusoidally to the level of VDD at which point control circuit  20  switches Q 2  “OFF” and switches Q 3  “ON” to complete the transition. As shown in  FIG. 4 , the circuit operates in a similar manner to produce the opposite polarity transition  
         [0013]      FIG. 5  shows waveforms resulting from the equivalent sequence of events when CL is smaller than or of a similar value to CB, in which case the transmission line character of CB and LB is more clearly evident. In response to a change of level of the input signal VI at time t 1 , Q 1  is switched “OFF” while Q 2  is switched “ON” driving VDO near to the level of VHH. An outward bound (or incident) wave of voltage amplitude equivalent to VHH travels along the transmission line. When it reaches the load, and since the load is reasonably small and cannot provide a significant path for the current in the incident wave, a reflected wave results tending to cancel the current of the incident wave. This reflected wave is also of amplitude equivalent to VHH but adds to the incident wave to give a voltage level at the load equal to VDD. The reflected wave travels back toward driver  18  until the whole length of the transmission line is at the level of VDD by time t 2 , being the time when the reflected wave actually reaches the driver  18 , at which point control circuit  20  switches Q 2  “OFF” and switches Q 3  “ON” to complete the transition. Control circuit  20  can be designed in a variety of ways to control the timing of this to coincide with the return of the reflected wave. The timing for the current transition of VDO can be determined by observing and storing some characteristic of a previous transition to make adjustments to some circuit capable of storing and reproducing timed sequences, for example a digitally controlled delay line controlled by a digital counter.  
         [0014]     Resonant Line Drivers have the potential to both reduce power consumption and produce well conditioned signal without ringing and overshoot. Unfortunately though, when certain unavoidable characteristics of typical physical implementations are taken into account, whilst low power consumption can be achieved, signal conditioning may be poor.  
         [0015]      FIG. 6  shows the circuit of  FIG. 3  but modified to make it more representative of a real physical implementation. Quite typically driver  18  is formed on silicon chip which is in turn contained in a chip package in turn mounted onto PWB  12 . Often, though not necessarily, reservoir capacitor CR may be contained within the chip or chip package.  FIG. 3  shows driver  18 , PWB  12  and load  14  all sharing a common voltage reference level VSS. In an actual physical implementation this is often not the case since as shown in  FIG. 6 , ground voltage levels for driver  18 , PWB  12  and load  14  (VSSD, VSSB and VSSL respectively) and power voltage levels for driver  18 , PWB  12  and load  14  (VDDD, VDDB and VDDL respectively) are connected via parasitic package lead inductances LPL 1 , LPL 2 , LPL 3 , and LPL 4  as shown. Also, in an actual physical implementation, the parasitic capacitances of the interconnect and load often occur not only between signal VSS but also between signal VDD as shown.  
         [0016]     Turning to  FIG. 7 , Q 2  of driver  18  in  FIG. 2   b  is typically relatively large and consequently has a very low “ON” compared to, for example, QA or QB in the conventional driver of  FIG. 1   a , so the waveform produced by driver  18  as shown in  FIG. 7  is very abrupt, causing VDO to go from the level of VSS to nearly the level of VHH in a relatively short space of time at about time t 1 . At the same time the current flowing from driver  18  into the interconnect increases very rapidly giving a very high rate of change of current (or di/dt). Since the change in current causes an equal and opposite change in current in the return path via LPL 1  &amp; LPL 2 , these parasitic inductances respond to such a rapid change in current by allowing an appreciable voltage difference to occur between VSSD &amp; VSSB and between VDDD &amp; VDDB as shown in  FIG. 7  which shows the levels of VSSB and VDDB referred to VSSD and VDDD as reference.  
         [0017]     In an actual application driver  18  would normally be part of an IC not only driving output signals but also receiving input signals. Unfortunately, since the input signals have considerable capacitance coupling with VSSB and VDDB, their levels tend to be determined in reference to VSSB and VDDB so that for example an input signal which is nominally at a low level will present to its receiver on the aforementioned IC, a voltage spike very similar to that shown for VSSB in  FIG. 7  at time t 1 . This causes the possibility of the input signal being temporarily interpreted as being at a high level. As can be seen in  FIG. 7 , since all the change in output current from driver  18  in  FIG. 6  is supplied from VSSD either via reservoir capacitor CR &amp; Q 2  in  FIG. 2   b  or through Q 1  in  FIG. 2   b , the most extreme disturbance is to the level of VSSB in relation to VSSD at time t 1 , t 3  &amp; t 4 . (At time t 2  the change in current is supplied in part by VDDD via Q 3  in  FIG. 2   b  so the disturbance is less serious.) Therefore a signal which inputs to the aforementioned IC and because of its particular physical routing being coupled mainly to VSSB may suffer serious disturbance as received by a receiver circuit in the IC.  
       SUMMARY OF THE INVENTION  
       [0018]     It is the aim of the present invention to provide improvements to resonant line drivers to allow their operation with low signal disturbance and better signal integrity whist still allowing the benefits of reduced power consumption. These improvements may be used either in combination or individually to provide a greater or less degree of benefit.  
         [0019]     In accordance with a first aspect of the invention, an electronic driver circuit is provided for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load where the circuit and conductor output signals respectively making corresponding circuit and conductor output transitions approximately between a pair of output voltage levels between which there is an intermediate voltage level. Inductance and capacitance of the conductor and the load produce resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at approximately the intermediate voltage level for a non-zero intermediate-level holding period during the corresponding circuit output transition. The circuit includes at least a first capacitor element between the intermediate voltage level and each of the first and second voltage levels and at least a second capacitor element (preferably equal to the first capacitor element, e.g. a) between the intermediate voltage level and the second voltage level.  
         [0020]     The first and second capacitor elements may form a split-reservoir capacitor.  
         [0021]     A package lead inductance may exist between the electrical conductor and a source of each of the pair of output voltage levels. In this case the first and second capacitor elements are preferably such that a change in circuit output voltage causes return current flowing back into the driver to be split approximately equally between the package lead inductances. The first and second capacitor elements may provide decoupling capacitance between the output voltage levels.  
         [0022]     In accordance with a second aspect of the invention, an electronic driver circuit is provided for generating a circuit output signal providable to an electrical conductor that furnishes a conductor-output signal providable to a load. The circuit and conductor output signals respectively make corresponding circuit and conductor output transitions approximately between a pair of output voltage levels between which there is an intermediate voltage level. Inductance and capacitance of the conductor and the load produce resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at approximately the intermediate voltage level for a non-zero intermediate-level holding period during the corresponding circuit output transition. The circuit comprising a ramp control circuit for controlling partial circuit output transitions between at least one of the pair of output voltage levels and the intermediate level to provide a substantially non-zero transition time for a partial circuit output transition.  
         [0023]     The partial circuit output transition is preferably controlled to be slow relative to other switching events in the circuit.  
         [0024]     A pull-up transistor and a pull-down transistor may be provided for pulling the circuit output up to a first of the two output voltage levels and down to a second of the two output voltage levels, in which case the partial circuit output transition is controlled to be slower than the switching of the pull-up and pull-down transistors.  
         [0025]     An intermediate level driving transistor can be provided, which, in switching-on drives the circuit output up to the intermediate voltage level and in switching-off permits the circuit output to be driven up to a first of the two output voltage levels. In this case the partial circuit output transition is controlled to be slower than the switching-off of the intermediate level driving transistor.  
         [0026]     The partial circuit output transition time is preferably adjustable, for example it is controllable as a function of the time taken for the conductor output signal to largely complete a conductor output transition.  
         [0027]     The control circuitry may comprise time-comparison circuitry for comparing the circuit output signal and the second control signal to determine whether the circuit output signal completes a circuit output transition before the second control signal completes the corresponding control transition and adjustment circuitry for adjusting the partial circuit transition time depending on the comparison.  
         [0028]     Alternatively the comparator circuit preferably compares a level of the partial circuit output transition with a reference voltage that is approximately midway between the intermediate voltage level and an output voltage level to which the output is transitioning at a time approximately midway between a start of the partial circuit output transition and an expected completion of the partial circuit output transition.  
         [0029]     Preferably, reference ramp circuitry may be provided for generating a reference ramp, together with comparator circuitry coupled to the reference ramp circuitry for comparing a partial circuit output transition with the reference ramp.  
         [0030]     The time taken for a partial circuit transition is preferably controlled as a function of characteristics (e.g. characteristics determined from relative timing of two signals) of at least one previous circuit output transition.  
         [0031]     Preferably the ramp control circuit controls a partial circuit output transition as a function of a current stored control value stored as a result of a previous partial circuit output transition.  
         [0032]     In accordance with a third aspect of the invention, an electronic driver circuit is provided for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load. The circuit and conductor output signals respectively make corresponding circuit and conductor output transitions approximately between a first voltage, a second voltage and an intermediate voltage between the first and second voltages. In this aspect, the circuit comprises: a first transistor having (a) a first flow electrode coupled to a source of the first voltage, (b) a second flow electrode coupled to an output node from which a circuit output signal is provided, and (c) a control electrode responsive to a first control signal for controlling current flow between the first transistor&#39;s flow electrodes; a second transistor having (a) a first flow electrode coupled to a source of the second voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to a second control signal for controlling current flow between the second transistor&#39;s flow electrodes; and a third transistor having (a) a first flow electrode coupled to a source of the intermediate voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to a third control signal for controlling current flow between the third transistor&#39;s flow electrodes. Fourth and fifth transistors are connected between the control electrode of the third transistor and the sources of the first and second voltage levels respectively. Control circuitry selectively discharges the control electrode of the third transistor to the first and second voltage levels respectively through the fourth and fifth transistors such that the control electrode makes partial transitions between the first and second voltage levels. The output signal makes rising and falling circuit output transitions approximately between the first and second voltages controlled by the first, second and third control signals, and the circuit output signal stays approximately at the intermediate voltage for a non-zero intermediate-level holding period during each circuit output transition.  
         [0033]     The features of the first, second and third aspects of the invention and their various preferred features may be combined in any combination.  
         [0034]     In accordance with the first aspect of the invention, the split reservoir (or other) capacitor reduces ground and power reference differences (known as ground and power bounce) between a chip containing a resonant driver and the PWB on which it is mounted. The split reservoir capacitor also provides power and ground decoupling. In its second aspect the invention provides for a controlled slew rate ramp initiating an incident or outbound wave or turn-on and circuit methods for this. In a further aspect, the invention provides for the time taken to complete the controlled slew rate ramp to be adjusted approximately proportionately in time with the intermediate voltage holding period of the resonant driver.  
         [0035]     The controlled slew rate ramp methods can not only further reduce ground and power bounce but also reduce unnecessary high frequency components in the signal seen at the load which can cause other signal integrity and radio frequency interference issues. A further aspect of the current invention lies in matching the “ON” resistance of the driver pull-up and pull-down transistors (for example Q 3  and Q 1  in  FIG. 2   b ) approximately to the characteristic impedance interconnect  12 . A still further aspect of the invention relates to means for determining a feedback control signal to adjust the internal delay of a resonant line driver.  
         [0036]     A number of preferred embodiments will now be described by way of example only, with reference to the drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0037]     FIGS.  1  to  3  represent prior art resonant line driver circuits.  
         [0038]      FIGS. 4 and 5  are timing diagrams illustrating the operation of the circuit of  FIG. 2   b  for different values of CL.  
         [0039]      FIG. 6  represents a resonant line driver similar to that of  FIG. 3  in a typical physical environment.  
         [0040]      FIG. 7  is a timing diagram for the circuit of  FIG. 6 .  
         [0041]      FIG. 8  represents a resonant line driver in accordance with a first embodiment of the invention.  
         [0042]     FIGS.  9  to  11  are timing diagrams illustrating the operation of the circuit of  FIG. 8 .  
         [0043]      FIG. 12  represents a resonant line driver in accordance with a second embodiment of the invention.  
         [0044]      FIG. 13  is a timing diagram illustrating the operation of the circuit of  FIG. 12 .  
         [0045]      FIG. 14  represents a resonant line driver in accordance with a third embodiment of the invention.  
         [0046]      FIGS. 15 and 16  are timing diagrams illustrating the operation of the circuit of  FIG. 14 .  
         [0047]      FIG. 17  is a diagram of a control circuit suitable for use in the circuit of  FIG. 12  or  FIG. 14  or other embodiments.  
         [0048]      FIG. 18  illustrates a prior art control circuit.  
         [0049]      FIG. 19  is a timing diagram for explanation of the operation of a resonant line driver in accordance with the second aspect of the invention.  
         [0050]      FIG. 20  illustrates a control circuit suitable for use in accordance with the second aspect of the invention.  
         [0051]      FIG. 21  expands upon  FIG. 19 .  
         [0052]      FIG. 22  illustrates a control circuit alternative to that of  FIG. 20 .  
         [0053]      FIG. 23  represents a resonant line driver in accordance with a further embodiment.  
         [0054]      FIG. 24  is a timing diagram for the circuit of  FIG. 23 .  
         [0055]      FIG. 25  illustrates in greater detail a comparator suitable for use in the circuit shown in  FIG. 23 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0056]     Turning to  FIG. 8 , it shows a circuit similar to that in  FIG. 6  but instead of the reservoir capacitance being supplied entirely between the VSSD and VHHD circuit nodes, the reservoir capacitor is split into two capacitances CR 1  and CR 2 . CR 1  provides capacitance between VSSD and VHHD while CR 2  provides capacitance between VDDD and VHHD. Since each of CR 1  and CR 2  provides reservoir capacitance in parallel, each of CR 1  &amp; CR 2  can be made half the numerical size of CR in  FIG. 6  to provide the same effective reservoir capacitance. But by using a split reservoir capacitor driver  19  in  FIG. 8  is made more symmetrical so when a change in voltage of driver output signal VDO causes current to flow into or out of interconnect  12 , a return current flows back into driver  19  split equally between package lead inductances LPL 1  &amp; LPL 2 .  
         [0057]      FIG. 9  shows waveforms that occur in relation to the circuit of  FIG. 8 . Comparing  FIG. 7  with  FIG. 9 , whereas at time t 1  in  FIG. 7  since in  FIG. 6  all return current flows through LPL 2  giving a large offset between VSSB and VSSD, at time t 1  in  FIG. 9  both VSSB and VDDB are offset approximately equally from VSSD and VDDD respectively but by a smaller amount since in the circuit of  FIG. 8  any return current is split equally between package lead inductances LPL 1  an LPL 2 . As a further benefit, the series combination of LPL 1  and LPL 2  provides a very useful degree of decoupling capacitance between VSSD and VDDD. For example, at time t 2  in  FIG. 9  some current is supplied from node VDDD to the driver output node via, for example MOSFET Q 3  in  FIG. 2   b . The decoupling capacitance provided by the series combination of CR 1  and CR 2  can provide the necessary current which would othervise need to be drawn externally through LPL 1  causing further ground bounce.  
         [0058]     Turning to  FIG. 10 , a second element of the current invention provides for a controlled slew rate ramp when at time t 1 , driver output signal is driven from the level of VSSD to VHHD. The positive going ramp takes output signal VDO smoothly at a controlled rate from the level of VSSD at time t 1  nearly to the level of VHHD at time t 1   a  and a negative going ramp takes output signal VDO smoothly at a controlled rate from the level of VDDD at time t 3  nearly to the level of VHHD at time t 3   a.    
         [0059]     Preferably the ramp is generated by a circuit of low output impedance so that the amplitude and duration of the ramp is largely unaffected by the degree of loading on output signal VDO. A controlled ramp considerably reduces the rate of change of current output from the driver and therefore the rate of change of return current through for example LPL 1  and LPL 2  and results in considerable reduction of power and ground bounce, as shown in  FIG. 10  and yet adds only a small delay to the overall transit of the signal from source to load.  
         [0060]     When the load approximates a transmission line the ramp commencing at time t 1  in  FIG. 10  travels along the transmission line and reflects back toward the driver reaching it at time t 2 . At this point control circuit  20  disconnects output VDO from VHHD and connects it to VDDD via pull-up transistor for example Q 3  in  FIG. 2   b . If Q 3  is sized such that its “ON” resistance is matched to the characteristic impedance of the transmission line then the driver output voltage VDO smoothly approaches the level of VDDD without overshoot or undershoot to complete the transition. A similar sequence commences at time t 3  in the opposite polarity transition and likewise Q 1  in  FIG. 2   b  can be sized such that its “ON” resistance is matched to the characteristic impedance of the transmission line.  
         [0061]     A disadvantage of the controlled ramp method is that a reduced portion of total charge for the transition is supplied from the reservoir capacitor. For example in  FIG. 10  the shade areas under the IHH and IDD curves show the relative proportions of charge deliver from the VHHD node (i.e. reservoir capacitor) and VDDD power supply node. As can be seen in  FIG. 10 , about 75% of the charge is provided by the reservoir capacitor, the remaining 25% coming from the VDDD power supply. Also indicated in  FIG. 10  (dotted lines) is that if the controlled ramp rate is made still slower the portion of charge supplied from the reservoir capacitor could drop still further to about 50%. Therefore the use of a controlled ramp leads to a slightly higher power consumption, though still much lower than a conventional driver but improves signal integrity and ground/power bounce. The timing requirements for signal integrity versus those for low power consumption and speed are therefore somewhat in opposition. Achieving a compromise between the requirements is the aim of a further element of the current invention.  
         [0062]     Looking again  FIG. 10 , if the ramp rate were approximately halved such that its duration is from t 1  to t 2  then as discussed above, the power consumption would increase so that a driver employing such a ramp rate might be unsuitable. On the other hand, if the same driver were driving an interconnect of about twice the length (and therefore delay), such a ramp time would again have low power consumption compared with a conventional driver as well as delivering good signal integrity as show in  FIG. 11 , whilst a ramp of the original speed (t 1  to t 1   a ) would bring only marginal further improvement in power consumption and speed and yet greatly increase the contribution of the driver to ground/power bounce. At the same time the signal would contain an excess of high frequency harmonics adding unnecessarily to radio frequency emission. If therefore the ramp circuit is made controllable (i.e. capable of delivering ramp times of variable duration within a range, and if the ramp time is controlled by the same circuit control mechanism used in control circuit  20  to adjust the intermediate level holding period of the resonant line driver, then the driver can operate over a range of load conditions (i.e. can drive load with varying transmission line delay or LC resonant frequency) and still produce waveforms which represent close to an optimum chosen compromise between, on the one hand power consumption and speed and on the other hand signal integrity.  
         [0063]      FIG. 12  shows a resonant line driver  118  comprising a first embodiment of a ramp control circuit  118 . Comparing it with the circuit in  FIG. 2   b , NMOS transistor Q 2  has been replaced by a pair of transistors Q 2 N (an NMOS device) and Q 2 P (a PMOS device) with their respective channels connected in parallel. At the beginning of a transition of output signal VDO the gate of Q 2 N is charged (positively) by a flow of current from current mirror Q 21 /Q 20  when Q 22  switches “ON”, and at the same Q 24  is turned “OFF” whilst the gate of Q 2 P is charge (negatively) by a flow of current from current mirror Q 31 /Q 30  when Q 32  switches “ON” and at the same Q 34  is turned “OFF”.  
         [0064]     In a LOW to HIGH transition, for example that commencing at time t 1  in  FIG. 13 , PMOS transistor Q 2 P is initially not conducting even after its gate electrode begins to fall because its channel cannot switch “ON” until the gate electrode become more negative than VHH. NMOS device Q 2 N on the other hand becomes conductive as soon as its gate electrode becomes more positive than VDO by at least the threshold voltage of Q 2 N. It will be seen that Q 2 N is therefore initially in a source follower configuration. During the ramp time signal, VDO is pulled gradually higher by a very low impedance, since a source follower configuration gives a very low output resistance. Q 2 P does eventually switch “ON” after the ramp is substantially complete and helps to attain a low overall “ON” resistance for Q 2 N and Q 2 P in parallel combination. At time t 2  both Q 2 N and Q 2 P are rapidly switched “OFF”, while pull-up transistor Q 3  is switched “ON”. In a HIGH to LOW transition, beginning at time t 3 , it is Q 2 P which switches “ON” first in source follower mode and Q 2 N which switches “ON” later so that the same pattern of operation occurs as described in relation the LOW to HIGH transition. Varying the value of current reference IREF allows variable ramp rates to be generated.  
         [0065]     A disadvantage of the circuit of  FIG. 12  is that, since CMOS P-channel devices are generally much less space efficient than N-channel devices, the circuit represents an increase in silicon area for the same value of “ON” resistance when compared to the circuit in  FIG. 2   b .  FIG. 14  shows a resonant line driver comprising an alternative ramp control circuit  119  using a single NMOS device Q 2  in place of the parallel combination of Q 2 N and Q 2 P in  FIG. 12 . Clearly for LOW-HIGH transitions Q 2  can again be driven in a source follower mode to generate a variable ramp. In  FIG. 14 , the gate of Q 2  is again charged during LOW-HIGH ramp when Q 22  switches “ON” current mirror Q 21 /Q 20  and at the same Q 24  is turned “OFF”. The reference current for mirror Q 21 /Q 20  comes in turn from current mirror Q 30 /Q 31 , which is in turn controlled by current reference IREFOUT. For HIGH-LOW transitions, Q 2  cannot be used as a source follower but is effectively configured as a common source switch which would normally switch “ON” very abruptly when the gate became more positive than VHH by an amount equal to the threshold voltage of Q 2 . However if a feedback capacitor CFB is place between output signal VDO and the input to mirror Q 41 /Q 40 , then the ramp rate generates a rate dependent current feedback which subtracts from reference current IREFOUT. Thus the circuit uses negative feedback to control the ramp rate to depend on the reference current input, since if the ramp is too slow the gate voltage will build at the input to mirror Q 41 /Q 40  tending to correct the rate to that desired. In effect therefore the ramp again has a low output impedance. As shown in  FIG. 15 , for HIGH-LOW transitions the gate of Q 2  is charged on a steadily increasing ramp whilst for HIGH-LOW transitions the gate voltage rises quite quickly at first and then slowly during an active period whilst the ramp rate is controlled. Thus capacitor CFB can be described as checking the rate of rise of the current to the control electrode of transistor Q 2  when the circuit output signal falls from VDD to VSS.  
         [0066]     A drawback with the circuit of  FIG. 14  is that on HIGH-LOW transitions there is an appreciable delay from beginning to charge the gate of Q 2  to the point where Q 2  first becomes conductive until driver output VDO begins to move. As shown in  FIG. 16 . however, during the period when VDO is high, it is not necessary to discharge the gate of Q 2  to the level of VSSD in order to switch Q 2  “OFF”. If the gate is discharged only to VHHD as shown in  FIG. 16 , Q 2  will still be switched “OFF” but can be switched “ON” again much more quickly at the start of the next HIGH-LOW transition. This can be achieved by replacing Q 24  in  FIG. 14  with two transistors, one discharging the gate of Q 2  to VSSD and the other discharging the gate of Q 2  to VHHD under control of suitably provisioned control signals VD 2 S and VD 2 H shown in  FIG. 16 . Alternatively the gate of Q 2  can be first discharged to VSSD and then pre-charged to the level of VHHD only before HIGH-LOW-transitions.  
         [0067]     An advantage of such a modified form of the circuit of  FIG. 14  can be seen by comparing  FIG. 16  for such a modified circuit with  FIG. 15  for the circuit as shown. The peak voltage stress between the gate and channel of switch Q 2  is approximately halved. E.g., after a low/high transition, all that is required to switch Q 2  off is to return the gate electrode to VHH. This reduces power consumption and allows a thinner oxide layer to be used in the manufacture of the MOSFET channel of Q 2 . Note that this advantage is independent of the particular rise time control scheme or timing of control for the partial output transitions. Note also that it is described in the context of a circuit comprising exclusively N-channel technology, but is equally applicable to P-channel technology or a mixture of N and P-channels. By way of example, the same principal could be applied to the circuit of  FIG. 12 , with suitable modifications.  
         [0068]      FIG. 17  shows a block diagram of a control circuit  120  in which the same current reference controls both the intermediate level holding period of a resonant line driver via controllable delay D 1  and provides current IREFOUT to a ramp circuit (for example in driver  119  of  FIG. 14 ) so that the ramp period tracks the intermediate level holding period for chosen optimum over a range of timing conditions. As described above, IREFOUT can be adjusted according to some characteristic of a previous transition as described in the prior art.  
         [0069]     For example,  FIG. 18  shows a control circuit described in U.S. Pat. No. 6,201,420, in which the duration of the intermediate level holding period is set by the value of an up/down counter  32 , in turn controlled by a comparator circuit  30  which compares the timing of circuit output signal VDO with control signal VC 2  to produce feedback signal RP. However, comparator  30  is designed to compare the relative timing of two fast transitioning signals and may be unreliable or inaccurate for use in a resonant line driver using a controlled ramp as described previously. A further aspect of the current invention therefore provides a means of adjusting the intermediate level holding for resonant line drivers using a controlled ramp.  
         [0070]      FIG. 19 , for clarity, shows only the low-to-high transition of a resonant line driver using a controlled ramp. It shows an initial ramp beginning at time t 1  followed by an intermediate level holding period after which the reflection of the initial ramp at time t 1  (let it be called “initial reflection”) arrives at approximately time t 3 . Time t 3  is the time of the transitioning of control signals VC 3  and VE 2 N as determined by the control circuitry. An element of the current invention is the positioning of an optimum timing for the transitioning of control signals VC 3  and VE 2 N at t 3  such that it coincides as nearly as possible with initial reflection. When this optimum timing is achieved, output signal VDO rises with approximately the same slope starting from time t 3  as it does during the initial ramp starting at time t 1 . This optimum timing is depicted by voltage waveform VDOO in  FIG. 19 . When initial reflection arrives in early, in advance of time t 3 , signal VDO rises more quickly than the initial ramp beginning at time t 1  as indicated by waveform VDOE. Conversely, when initial reflection arrives late in relation to time t 3 , signal VDO rises with a slope similar to the initial ramp at time t 1  but commencing some time after time t 3  as depicted by waveform VDOL.  
         [0071]     Turning to  FIG. 20 , this shows control circuit  128  comprising timing circuit and control loop for use in a resonant line driver using a controlled ramp, whilst  FIG. 21  depicts waveforms which occur in relation to the operation of control circuit  128 .  
         [0072]     Control circuit  128  contains latching comparator circuit  132  which has level sensitive inputs receiving signals VDO and VREF and furnishes digital output signal U/D to an N-bit up/down counter  130  in response to clock signal input VIDD. Signal U/D is set to a logic “high” on the rising edge of VIDD if at that time signal VDO has a higher voltage than signal VREF or to a logic “low” on the rising edge of VIDD if at that time signal VDO has a lower voltage than signal VREF. Signal U/D controls the N-bit up/down counter  130  such that if signal U/D is at a logic “high” during the logic “high” to logic “low” transition of input signal VI then the counter value increments. Conversely if signal U/D is at a logic “low” during the logic “high” to logic “low” transition of input signal VI then the counter value decrements. Counter  130  in turns controls digitally controlled delay circuit  134  such that input signal VI is delayed in time by an amount dependent upon the current value stored by counter  130 .  
         [0073]     Signal VID, the delayed version of signal VI, is output from delay circuit  134  and in turn initiates the transitioning of output signals VE 2 N, VC 3  and VC 1  at time t 3  in  FIG. 21 . Current controlled delay circuit  136  further delays signal VID to produce signal VIDD which transitions at time t 4  in  FIG. 21 . Signal VIDD in turn is the clocking signal for latching comparator  132 . Delay circuit  136  is controlled by an output of current source  126  which supplies current IREF such that the greater the value of IREF the shorter the delay produced by delay circuit  136 . Current source  126  furnishes a second equal or proportional current to output IREFOUT which in turn can control the rise time of the ramp beginning at time t 1  in  FIG. 21 . When optimum timing is achieved, output signal VDO rises with approximately the same slope starting from time t 3  as it does during the initial ramp starting at time t 1 , as depicted by waveform VDDO.  
         [0074]     Delay circuit  136  is arranged to produce a delay always equal to approximately one half of the duration of the ramp commencing at time t 1  in  FIG. 21 . Input signal VREF on the other hand has a potential approximately midway between the potential of VHHD and VDDD as shown in the figure. When optimum timing is achieved, waveform VDOO results such that its potential approximately equals VREF at time t 4  producing an indeterminate output U/D from latching comparator  132 .  
         [0075]     On the other hand, if optimum timing has not been achieved, either waveform VDOE or waveform VDOL will result, and latching comparator  132  will drive its output signal, U/D to a logic “high” or logic “low” respectively. Since signal U/D controls the timing of signal VID and hence the positions of time t 3  in  FIG. 21  via counter  130  and delay circuit  134  in  FIG. 20 , the overall operation of the circuit is such that output signals VE 2 N, VC 3  and VC 1  are controlled to occur at or near an optimum time. Those skilled in the art will recognize that latching comparator  132 , up/down counter  130  and digitally controlled delay  134  together comprise elements of a control loop or more specifically a delay locked loop when used as the control circuit in a resonant line driver.  
         [0076]     Turning to  FIG. 22 , it shows control circuit  138  which is similar to control circuit  128  in  FIG. 20  but differs in that digitally controlled delay  134  in of control circuit  128  is replaced by current controlled delay  135  in control circuit  138 . Furthermore delay  135  is controlled by a current supplied from digitally controlled current source  140  in place of fixed current source  126  in control circuit  128 . Digitally controlled current source  140  supplies several equal or proportional output currents whose magnitudes are controlled as some function of the n-bit binary control input supplied by up/down counter  130  in control circuit  138 , but typically the output currents of current source  140  are substantially proportional or inversely proportional to the binary value control input supplied by counter  130 . Since counter  130  in control circuit  138  controls current source  140  which in turn controls delay  135  and via current controlled delay  136  enables latching comparator  132 , these again comprise elements of a delay locked loop.  
         [0077]     An advantage of control circuit  138  when compared with control circuit  128  is that control circuit  138  can supply additional control currents IREFOUT and IREFOUT 1  which are proportional to the control input current to current controlled delay  135 . As described in relation to control circuit  120  in  FIG. 17 , IREFOUT in  FIG. 22  can be used to control the rise time of a ramp circuit allowing the ramp period to track the intermediate level holding period in a resonant line driver. The further usefulness of IREFOUT 1  is described later. As described in relation to control circuit  128  in  FIG. 20 , control circuit  138  likewise contains current controlled delay  136 , the purpose of which is to provide clock signal VIDD to latching comparator circuit  132  such that signal VDO is compared at time t 3  to reference voltage VREF as shown in  FIG. 21 . Voltage VREF and time t 3  typically have their intersection as shown in  FIG. 21  coinciding with waveform VDOO so that waveform VDOE can be discriminated from waveform VDOL to produce loop feedback signal U/D.  
         [0078]     A particular difficulty when physically implementing control circuits  128  or  138  may be in designing latching comparator  132  to work at sufficiently high speed and providing it with reference and clocking inputs of sufficient precision. For example, whilst in  FIG. 21  voltage levels VHHD and VDDD are shown as time invariant, in a physical implementation both VDDD and VHHD are subject to change, particularly the level of VHHD when it is supplied from a reservoir capacitor. Therefore the choice of appropriate level for VREF in relation to the current and immediately prior levels of VHHD and VDDD and circuitry required to furnish signal VREF may become quite complex issues. Likewise, the timing of signal VIDD in control circuits  128  or  138  needs to be accurate and repeatable to a degree which may prove hard to achieve. Furthermore, latching comparator  132  in control circuits  128  or  138  notionally compares the voltage of signal VDO to the voltage of signal VREF at a single instant on the rising-edge of clocking signal VIDD. In reality though, due to the finite speed of circuit elements internal to latching comparator  132 , that comparator will tend to compare the values of inputs signal VDO and VREF averaged throughout the time duration of a sampling window, approximately (though not precisely) coinciding with the rising edge of clocking input signal VIDD.  
         [0079]     All of these uncertainties may combine to make circuit design difficult and circuit operation erratic. In accordance with a further embodiment of the current invention improved means are provided for furnishing loop feedback signal U/D in control circuit  128  and  138 . This is achieved in part by redefining the inputs to latching comparator  132  to demand less precision and in part by providing an internal circuit for latching comparator  132  which is novel and particular to the application and further relaxes the timing accuracy demanded of clocking signal VIDD.  
         [0080]      FIG. 23  shows an alternative resonant line driver comprising a control circuit  138 , a ramp circuit  119  similar to that shown in  FIG. 14 , output MOSFET&#39;s Q 1 , Q 2  and Q 3  and additional circuitry comprising N-channel MOSFET Q 2 R and capacitor CRAMP. Capacitor CRAMP furnishes a signal VREFRAMP which functions as described below. The source and drain terminals of N-Channel MOSFET Q 2 R are connected to signals VHHD and VREFRAMP respectively.  
         [0081]     Referring to  FIG. 24 , reference current output IRFEOUT 1  from control circuit  138  initially charges capacitor CRAMP high to the voltage level of VDD. When signal VC 2  rises initiating a low to high transition at time t 1  and further rises above the level of VHHD time tA, N-Channel MOSFET Q 2 R turns “ON”, discharging capacitor CRAMP and signal REFRAMP to the level of VHHD. Then at time immediately prior to time t 3 , signal VC 2  falls. Prior to the falling edge of signal VC 2 , output signal VDO is strongly held at a level close to the level of VHHD because large N-channel MOSFET Q 2  is “ON” The falling edge of VC 2  is what initiates the ramp beginning at time t 3  of signal VDO when N-channel MOSFET Q 2  turns “OFF”.  
         [0082]     Waveform VREFRAMP has a slope between time t 3  and t 5  that is arranged to be substantially the same as waveform VDDO in  FIG. 21 . By using waveform VREFRAMP in place of signal VREF, output signal VDO can be compared with VREFRAMP at any time between times t 3  and t 5  and the same result can be obtained, thus considerably relaxing the timing requirements for signal VIDD in part of  FIG. 23 .  
         [0083]     It is a considerable benefit of the current invention and in particular the circuit shown in  FIG. 23  that at substantially the same time (t 3  in  FIG. 24 ) that N-channel MOSFET Q 2 N turns “OFF” initiating the ramp of VDO, N-channel MOSFET Q 2 R also turns “OFF” allowing IREFOUT 1  to begin charging capacitor CRAMP. The close timing coincidence of these two events at time t 3  is very precise because both MOSFET Q 2  and Q 2 R can be N-channel devices formed on the same substrate sharing a common gate signal VC 2  and a common source signal VHHD. Furthermore, the slope of signal VREFRAMP between time t 3  and t 5  is proportional to the reference current IREFOUT 1 , which is in turn proportional to the reference current IREFOUT, which (through ramp circuit  119 ) substantially determines the slope of the VDO ramp beginning at time t 1 . Therefore the slope of signal VREFRAMP between times t 3  and t 5  can be arranged to be always substantially the same as the slope of the ramp of output signal VDO beginning at time t 1 , and when signals VDO and VREFRAMP are compared at any time between t 3  and t 5  by latching comparator  132  ( FIG. 23 ) then a loop feedback signal U/D can be furnished, which very accurately discriminates waveform VDOE of output signal VDO from waveform VDOL of output signal VDO. Thus up/down counter  130  and digitally controlled current source  140  allow current controlled delay  135  in control circuit  138  (all shown in  FIG. 22 ) to be adjusted very close to an optimum value.  
         [0084]     Instead of comparing the voltage level of output signal VDO to the voltage level of signal VREFRAMP at some a single time between time t 3  and t 5  in  FIG. 24 , still further accuracy may be obtained if the difference voltage between the two signals is time integrated between times t 3  and t 5  using what (for ease of reference) will be called an integrating latching comparator. Such a comparator has inherent advantages in terms of accuracy and noise immunity. However when implemented in a resonant line driver operating at high speed there may be difficulties in furnishing to an integrating latching comparator a signal or combination of signals that accurately delimits the desired period of integration. A further embodiment of the current invention employs an integrating latching comparator circuit which largely overcomes this issue.  
         [0085]     Turning to  FIG. 25 , this figure shows an integrating latching comparator  150  with comparator inputs VREFRAM and VDO and furnishing comparator outputs Q and QN. Integrating latching comparator  150  also accepts a reference current MREF and latching control signals VE 2 N, EXTENT and EXTENT 13 NOT where suitable. Example timing of for these control signals is shown in the lower part of  FIG. 24 .  
         [0086]     The input stage of integrating latching comparator  150  comprises capacitors CCOMP 1  and CCOMP 2 , current bias generating N-channel MOSFETS Q 102  and Q 103 , shorting N-channel MOSFET Q 104  and differential input N-channel MOSFETs Q 105  and Q 106 . Output nodes Q and QN are rapidly shorted, upon VE 2 N going to a low level shortly before time t 1  in  FIG. 24 , and are driven to the voltage level of VDDD by P-channel MOSFETs Q 111 , Q 109  and Q 110 . Initially N-channel MOSFETs Q 105  and Q 106  act as source followers with bias current supplies by N-channel MOSFETs Q 102  and Q 103  and therefore capacitors CCOMP 1  and CCOMP 2  track the voltage levels of input signals VREFRAMP and VDO shifted lower by the gate-source bias voltage of Q 105  and Q 106 . Then, when signal EXTENT goes to a high level, N-channel MOSFET Q 104  is switched “ON” and shorts source terminals of N-channel MOSFETs Q 105  and Q 106  so that they now function as a differential pair with bias current again supplied by N-channel MOSFETs Q 102  and Q 103 . The output current of the differential pair flows to output nodes Q and QN so that when, shortly before time t 3  in  FIG. 24 , VE 2 N goes to a high level and Q 109 , Q 110  and Q 111  are switched “OFF”, this output current begins charging output nodes Q and QN and associated capacitance (provided mainly by the gate capacitance of P-channel MOSFETs Q 107  and Q 108  and N-channel MOSFETs Q 112  and Q 113 ). The current source formed by Q 102  and Q 103  is arranged to supply only a modest amount of current so that even if VE 2 N happens relatively far in advance of time t 3 , output nodes Q and QN remain quite near to the level of VDDD and thus the relative timing of VE 2 N is non-critical in relation to time t 3  save that it should go to a low level in advance of time t 3 . Now when input signals VREFRAMP and VDO begin their respective ramps at or near time t 3 , being connected to the gate terminals of N-channel MOSFETs Q 105  and Q 106 , the respective source terminals Q 105  and Q 106  shorted by Q 104  also begin to rise in voltage and to charge capacitors CCOMP 1  and CCOMP 2 .  
         [0087]     Note that when Q 114  is closed for regeneration, Q 104  is closed and serves to separate the differential pair of Q 105  and Q 106  at that time.  
         [0088]     The integrating latching comparator  150  has a positive input VDO which receives the partial output transition, and a negative input VREFRAMP which receives a signal corresponding to (i.e. representative of) a reference ramp. The integrating latching comparator accumulates charge on the comparator output nodes (Q and QN) only during a time when either of the two input signals is rising. It provides an average comparison over the whole ramping period, i.e. over the time of the partial output transition.  
         [0089]     A positive feedback regeneration circuit comprising the transistors Q 107  to Q 114  receives charge at the comparator output nodes Q and QN via the differential input transistor pair. The regeneration circuit takes a small difference on nodes Q and QN, and, when EXTENTNOT causes Q 114  to conduct, it amplifies this small difference to a full rail voltage.  
         [0090]     Capacitors CCOMP 1  and CCOMP 2  are sized such that charging them requires quite a large current in relation to the modest bias current supplied by Q 102  and Q 103  so that the total bias current through the differential pair formed by Q 105  and Q 106  becomes quite large, but only while input signals VDO and VREFRAMP continue to rise. The circuit therefore embodies an inherent feature which tends to integrate the difference voltage between inputs VREFRAMP and VDO only during their respective ramp period between time t 3  and t 5  in  FIG. 24 . This feature further relaxes the timing precision required of control input signals to integrating latching comparator  150 . By time t 5  in  FIG. 24 , the difference voltage between inputs VREFRAMP and VDO will have been time integrated by charge accumulation to produce a small difference in the voltage levels of output nodes Q and QN. Finally this voltage is amplified to a full rail voltage when signal EXTENT 13 NOT goes to a high level after time t 5  in  FIG. 24 , since the current flowing through N-channel MOSFET Q 114  strongly biases cross coupled N-channel MOSFET pair Q 112  and Q 113 , which regenerate any pre-existing voltage difference at output nodes Q &amp; QN by positive feedback assisted by a similar mechanism applying to cross coupled P-channel MOSFET pair Q 107  and Q 108 .  
         [0091]     Again the timing of the rising edge of control signal EXTENT 13 NOT is non-critical in relation to time t 5  in  FIG. 24 , save that it should occur after time t 5 . The final state of output signals Q &amp; QN will be such that one is at the level of VDDD and the other at the level of VSSD depending on the time integrated difference voltage between input signals VREFRAMP and VDO between time t 3  and t 5  in  FIG. 24 . Integrating latching comparator  150  along with suitable circuitry to furnish control signals EXTENT and EXTENT 13 NOT could therefore replace latching comparator  132  in control circuit  138  of  FIG. 23  with one of its output signal Q or QN chosen for appropriate logic polarity furnishing loop feedback signal U/D in  FIG. 23 .