Abstract:
Embodiments of electronic module metallization systems and apparatus and methods for forming same are described generally herein. Other embodiments may be described and claimed.

Description:
[0001]    The present application claims the benefit of priority under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 61/481,160, filed Apr. 30, 2011, entitled “Electronic Module Metalization System, Apparatus, and Methods of Forming Same”; and the disclosure of U.S. Provisional Application No. 61/481,160 is hereby incorporated by reference herein as if set forth in full. 
     
    
     TECHNICAL FIELD 
       [0002]    Various embodiments described herein relate generally to electronic modules metallization systems and apparatus and methods for forming same. 
       BACKGROUND 
       [0003]    It may be desirable to limit the long term effect of electromigration and reduce the parasitic capacitance of electronic modules. The present invention provides a system, method, and apparatus for same. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a block diagram of a signal processing system according to various embodiments. 
           [0005]      FIG. 2A  is a block diagram of a semiconductor circuit or module according to various embodiments. 
           [0006]      FIG. 2B  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern according to various embodiments. 
           [0007]      FIG. 2C  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0008]      FIG. 2D  is a block diagram of a semiconductor circuit with multiple cells or channels with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0009]      FIG. 3A  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern according to various embodiments. 
           [0010]      FIG. 3B  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0011]      FIG. 4A  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern according to various embodiments. 
           [0012]      FIG. 4B  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0013]      FIG. 5A  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern according to various embodiments. 
           [0014]      FIG. 5B  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0015]      FIG. 6A  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern according to various embodiments. 
           [0016]      FIG. 6B  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0017]      FIG. 7A  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern according to various embodiments. 
           [0018]      FIG. 7B  is a block diagram of a semiconductor circuit or module with a first metallization, finger, or electrode pattern and additional metallization, finger, or electrode pattern according to various embodiments. 
           [0019]      FIG. 8  is a flow diagram illustrating several methods according to various embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]      FIG. 1  is a block diagram of a signal processing system  10  according to various embodiments. As shown in  FIG. 1 , the system  10  includes resistors  16 A,  16 B, and  16 C, a frequency signal generator module  30 , and a controllable module  40 . The frequency signal generator module  30  may generate signals  20 B including various frequencies from audio to radio frequency (RF). A control or bias signal  20 A may be coupled to the controllable module  40  via the resistor  16 A. The controllable module  40  may process the signal  20 B based on the signal  20 A. The module  40  processed signal  20 C may be read across resistor  16 C. 
         [0021]    In an embodiment, the controllable module  40  may include one or more controllable elements or modules such as an n-type complementary metal-oxide-semiconductor N-CMOS transistor  42  or other electronic modules including a semiconductor transistor  42 .  FIG. 2A  is a block diagram of a semiconductor circuit or module  50  according to various embodiments. In an embodiment the module  50  may be any electronic circuit including a semiconductor. The module  50  may be a transistor such as an NMOS or a PMOS transistor. 
         [0022]    In an embodiment the transistor or module  50  may include a first submodule, cell, or channel  52 A, a third submodule, cell, or channel  56 A, and a second submodule, cell, or channel  54 A. In a NMOS transistor the first submodule may represent a source channel or cell  52 A and may include a p-type silicon well in a silicon substrate, an n-type silicon channel, and a top insulator such as silicon dioxide. The second submodule may represent a drain channel or cell  54 A and may include an n-type silicon channel in the p-type silicon well in the silicon substrate and a top insulator such as silicon dioxide. The third submodule may represent a gate channel or cell  56 A and may include an n-channel in the p-type silicon well in the silicon substrate, a top insulator, and a metal track (metallization), finger, or electrode electrically coupled to the third submodule or gate channel or cell. 
         [0023]    Similarly in a PMOS transistor the first submodule may represent a source channel or cell  52 A and may include an n-type silicon well in a silicon substrate, a p-type silicon channel, and a top insulator such as silicon dioxide. The second submodule may represent a drain channel or cell  54 A and may include a p-type silicon channel in the n-type silicon well in the silicon substrate and a top insulator such as silicon dioxide. The third submodule may represent a gate channel or cell  56 A and may include a p-channel in the n-type silicon well in the silicon substrate, a top insulator, and a metal track (metallization), electrode, or finger electrically coupled to the third submodule or gate channel or cell. The transistor or module  50  is shown from a top level. Other semiconductor configurations may be employed according to the present invention. 
         [0024]    In a transistor or module  50 , a metal track or metallization may be applied to a channel or cell  52 A,  56 A,  54 A to provide an electrically conducting coupling or electrode for the transistor segment, channel or cell such as the n-type or p-type channel (for NMOS or PMOS, respectively). Similarly, another metal track, metallization or finger may be applied to another transistor segment, channel or cell  52 A,  54 A,  56 A such as the n-type or p-type channel (for NMOS or PMOS, respectively) to form an electrode for the channel or cell. In an embodiment the channel, cell, or section  54 A may represent a second submodule, channel, or cell (drain in an embodiment) and the channel, cell, or section  52 A may represent a first submodule, channel, or cell (source in an embodiment)for a MOS transistor or module  50 . 
         [0025]    Electromigration in the submodules  52 A,  54 A,  56 A (source, drain, and gate in an embodiment) in the respective metallizations, fingers or metal tracks ( 58 A,  58 B, and  56 A in  FIG. 2B  for example) may affect the resistance or conductance of the submodules  52 A,  54 A,  56 A. The submodules  52 A,  54 A,  56 A (source, drain, and gate in an embodiment) respective metallizations, fingers or metal tracks ( 58 A,  58 B, an  56 A in  FIG. 2B  for example) configuration or geometry may create parasitic capacitances in the respective transistor or module  50 .  FIG. 2B  is a block diagram of the semiconductor transistor or module  50  with a metallization, fingers, or tracks  58 A,  58 B for the first submodule, channel, cell (or source)  52 A and the second submodule, channel, cell (or drain  54 A) according to various embodiments. As shown in  FIG. 2B  metallization, finger, electrode, or track  58 A may include a wide, proximal narrow, distal section  65 A and a narrower, distal section  63 A of metal or alloy applied to the channel or cell  52 A. The metallization, finger, or track  58 A may be comprised of any conducting metal or alloy including aluminum. 
         [0026]    The first submodule, channel, or cell  52 A (source in an embodiment) metallization, finger, electrode, or track  58 A may include a plurality of contact pads  62 A coupling the metallization, finger, or track  58 A, sections  63 A,  65 A to the first submodule, channel, cell  52 A or source in an embodiment semiconductor channel (n-type or p-type) or other section, segment, or layer. The metallization  58 A sections  63 A,  65 A may be contiguous metal or alloy. In an embodiment, the electrical current at the metallization, track, or finger&#39;s  58 A wide, proximal section  65 A may be greater at its base and lower at its distal section  63 A. The wider proximal section  65 A of the finger or track  58 A may reduce the effect of electromigration in an embodiment. 
         [0027]    The second submodule, channel, cell (or drain)  58 B metallization, finger, electrode, or track metallization, finger, electrode, or track  58 B may also include two sections: a distal narrow, section  63 B and a wide proximal section  65 B with a plurality of contact pads  62 B. In an embodiment the electrical current at the metallization, track, or finger&#39;s  58 B wide, proximal section  65 B may be greater at its base and lower at its distal section  63 B. The wider proximal section  65 B of the finger or track  58 B may reduce the effect of electromigration in an embodiment. Further the parasitic capacitance of the module  50  may be reduced due to the narrow, distal sections  63 A,  63 B of the tracks or fingers  58 A,  58 B of the channels or submodules  52 A,  54 A being adjacent the wider sections  65 A,  65 B of the channels or fingers  58 A,  58 B, i.e., the respective geometries of the fingers or channels  58 A,  58 B where the higher electrical currents of the respective channels  58 A,  58 B are at opposite ends from each other. In an embodiment the tracks, or metallizations or electrodes  58 A,  58 B may extend substantially along the length of their respective submodule  52 A,  54 A semiconductor material. In the transistor or module  50  the first submodule, channel, or cell  52 A (source) metallization, finger, electrode, or track  58 A may be configured to be coupled to a circuit at an end opposite where the second submodule, channel, or cell  54 A (drain) metallization, finger, electrode, or track  58 B is coupled to a circuit. In an embodiment, the metallizations, electrodes or tracks  58 A,  58 B are wider  65 A,  65 B at their respective bases or proximal to the circuit coupling sections and may become narrower  63 A,  63 B at their distal sections. 
         [0028]    Accordingly in an embodiment, the first submodule, channel, or cell  52 A (source) metallization, electrode, or track  58 A distal end  63 A may have greater physical separation from the more active (electrically when operating) second submodule, channel, or cell  54 A (drain) metallization, track, or electrode&#39;s  58 B proximal section  65 B. Similarly, the second submodule, channel, or cell  54 A (drain) metallization, electrode, or track&#39;s  58 B distal end  63 B metallization, track, or electrode may also have greater physical separation from the more active (electrically when operating) first submodule, channel, or cell  52 A (source) metallization, track, or electrode&#39;s  58 A proximal section  65 A. 
         [0029]    As noted the metallizations, tracks, fingers, or electrodes  58 A,  58 B pattern or geometry may help reduce parasitic capacitance of the respective transistor or module  50  formed by the submodules, channels, or cells  52 A,  54 A,  56 A (source, drain, gate in an embodiment).  FIG. 2C  is a block diagram of the semiconductor transistor or module  50  with a first metallization, finger, electrode, or track  58 A,  58 B and a second, additional metallization, track, or electrode  58 C,  58 D formed over the first metallizations, fingers, electrodes, or tracks  58 A,  58 B (of the submodules, channels, or cells  52 A,  54 A according to various embodiments. 
         [0030]    As shown in  FIG. 2C  the first submodule, channel, or cell  52 A (source in an embodiment) may include a first metallization, finger, electrode, or track  58 A and an additional, overlaid metallization, finger, electrode, or track  58 C and the second submodule, channel, or cell  54 A (drain in an embodiment) may include a first metallization, finger, electrode, or track  58 B and an additional, overlaid metallization, finger, electrode, or track  58 D. Similar to the first or lower metallizations, fingers, electrodes, or tracks  58 A,  58 B, the additional, upper metallization, finger, electrode, or track  58 C,  58 D may include a narrow, distal section  63 C,  63 D and wide, proximal section  65 C,  65 D of metal or alloy. The additional, upper metallizations, fingers, electrodes, or tracks  58 C,  58 D may be comprised of any conducting metal or alloy including aluminum where the metallizations, fingers, electrodes, or tracks  58 C,  58 D overlay the first metallizations, fingers, electrodes, or tracks  58 A,  58 B, respectively. submodule, channel, or cell (source in an embodiment) The first submodule, channel, or cell  52 A (source in an embodiment) additional, upper metallization, finger, electrode, or track  58 C may also include a plurality of contact pads or vias  62 C coupling the additional, upper metallization, finger, electrode, or track  58 C, sections  63 C,  65 C to the first submodule, channel, or cell  52 A (source in an embodiment) semiconductor channels (n-type or p-type) or other layer. The metallization, finger, electrode, or track  58 C sections  63 C,  65 C may be contiguous metal or alloy. The second submodule, channel, or cell (drain in an embodiment)  58 B additional metallization, finger, electrode, or track  58 D may also include two sections: an extended narrow, distal section  63 D and a wide, proximal section  65 D with a plurality of contact pads or vias  62 D. 
         [0031]    In metallizations, fingers, electrodes, or tracks  58 C,  58 D the metallization, finger, electrode, or track  58 C,  58 D extends along a shorter length of the respective first submodule, channel, or cell (source in an embodiment) 52 A or second submodule, channel, or cell (drain in an embodiment)  54 A semiconductor material than the first metallization, finger, electrode, or track  58 A,  58 B. In an embodiment the second metallization, finger, electrode, or track  58 C,  58 D wide, proximal section  65 C,  65 D may be wider than the first metallization, finger, electrode, or track  58 A,  58 B wide, proximal section  65 A,  65 B. 
         [0032]    Similarly, the second metallization, finger, electrode, or track  58 C,  58 D narrow, distal section  63 C,  63 D may be wider than the first metallization, finger, electrode, or track  58 A,  58 B narrow, distal section  63 A,  63 B. The combination of the first and second metallizations, fingers, electrodes, or tracks  58 A,  58 C for first submodule, channel, or cell  52 A (source in an embodiment) may have greater physical separation from the second submodule, channel, or cell (drain in an embodiment)  54 A metallization, finger, electrode, or track  58 B,  58 D proximal sections  65 B,  65 D. Similarly, the combination of the first and second metallizations, fingers, electrodes, or tracks  58 B,  58 D for the second submodule, channel, or cell  54 A (drain in an embodiment) may have greater physical separation from the first submodule, channel, or cell (source in an embodiment)  52 A metallizations, fingers, electrodes, or tracks  58 A,  58 C proximal sections  65 A,  65 C. 
         [0033]    The combined metallizations  58 A and  58 C,  58 B and  58 D patterns or geometry may help reduce the effects of electromigration in the metallizations  58 A to  58 D. The metallizations  58 A and  58 C,  58 B and  58 D patterns or geometry may also reduce the parasitic capacitance of the respective transistor or module  50  formed by the first submodule, channel, or cell (source in an embodiment)  52 A, the second submodule, channel, or cell (drain in an embodiment) MA, and the third submodule, channel, or cell (gate in an embodiment)  56 A.  FIG. 2D  is a block diagram of a semiconductor circuit  60  with multiple modules  50 A,  50 B with a first metallization pattern  58 A,  58 B and an additional metallization pattern  58 C,  58 D,  58 E,  58 F according to various embodiments. In an embodiment the circuit  60  may be a CMOS transistor comprised of two modules  50 A,  50 B. Modules  50 A,  50 B are similar to the module  50  shown in  FIGS. 2A-2C  but are coupled together by the common third submodule, cell, or channel (gate in an embodiment)  56 B. 
         [0034]    The module  50 B first submodule, channel, or cell (source in an embodiment)  52 B metallizations, fingers, or electrodes  58 E are physically further from both the adjacent second submodule, channel, or cell (drain in an embodiment)  54 B metallizations, fingers, or electrodes  58 F (narrow, distal section  63 B) and the module  50 A second submodule, channel, or cell (drain in an embodiment)  54 A metallizations, fingers, or electrode  58 B,  58 D narrow section. In an embodiment the effect of electromigration of the metallizations, fingers, electrodes, or tracks  58 A,  58 B,  58 C,  58 D,  58 E, and  58 F may be reduced due to larger combined metallization cross-sectional areas. Parasitic capacitance for the CMOS transistor  60  may also be reduced due to the geometry of the metallizations, fingers, or electrodes  58 A,  58 B,  58 C,  58 D,  58 E, and  58 F. 
         [0035]    Other metallization configurations that may reduce the effect of electromigration and potential parasitic capacitance are shown in  FIGS. 3A to 7B . A transistor  70  with a first, lower and a second, upper metallization, finger, or electrode  75 A,  75 B,  75 C,  75 D is shown in  FIGS. 3A-3B . As shown in  FIG. 3A , the first, lower metallization  75 A may extend along a substantial section of submodule, channel, or cell (source in an embodiment) length and include a plurality of contact pads or vias  62 A coupling the metallization, finger, electrode, or track  75 A to submodule, channel, or cell (source in an embodiment) semiconductor channel (n-type or p-type) or other section, segment, or layer. 
         [0036]    The other first, lower metallization  75 B may extend along a substantial section of second submodule, channel, or cell (drain in an embodiment)  54 A length and include a plurality of contact pads or vias  62 B coupling the metallization, finger, electrode, or track  75 B to second submodule, channel, or cell (drain in an embodiment)  54 A semiconductor channel (n-type or p-type) or other section, segment, or layer. As shown in  FIG. 3B  the submodule, channel, or cell (source in an embodiment)  52 A may include a second, upper metallization  75 C overlapping the first, lower metallization  75 A for at least half the length of the first metallization  75 A. Similarly, second submodule, channel, or cell (drain in an embodiment)  54 A may include a second, upper metallization  75 D overlapping the first metallization  75 B for at least half the length of the first metallization  75 B. 
         [0037]    The additional metallizations, fingers, or electrodes  75 C and  75 D may also include a plurality of contact pads or vias  62 C,  62 D coupling the metallization, finger, electrode, or track  75 C,  75 D to the first submodule, channel, or cell (source in an embodiment)  52 A, second submodule, channel, or cell (drain in an embodiment)  54 A semiconductor channel (n-type or p-type) or other section, segment, or layer. The additional metallizations  75 C,  75 D shorter length (less than the length of the first metallizations  75 A,  75 B) may help reduce parasitic capacitance between adjacent metallizations  75 A,  75 B,  56 A,  75 C, and  75 D. The combination of the first, lower metallizations  75 A,  75 B and the second, upper metallizations  75 C,  75 D may help reduce the effects of electromigration. 
         [0038]      FIGS. 4A and 4B  are block diagrams of a semiconductor circuit or module  80  with a first, lower metallization, finger, or electrode  85 A,  85 B and a second, upper metallization, finger, or electrode  85 C,  85 D according to various embodiments. As shown in  FIG. 4A , the first, lower metallization  85 A may extend along a substantial section of submodule, channel, or cell (source in an embodiment)  52 A length and include a plurality of contact pads or vias  62 A coupling the metallization, finger, electrode, or track  85 A to submodule, channel, or cell (source in an embodiment)  52 A semiconductor channel (n-type or p-type) or other section, segment, or layer. 
         [0039]    Similarly, the other first, lower metallization  85 B may extend along a substantial section of second submodule, channel, or cell (drain in an embodiment)  54 A length and include a plurality of contact pads or vias  62 B coupling the metallization, finger, electrode, or track  85 B to second submodule, channel, or cell (drain in an embodiment)  54 A semiconductor channel (n-type or p-type) or other section, segment, or layer. As shown in  FIG. 4B  the submodule, channel, or cell (source in an embodiment)  52 A may include a second, upper metallization  85 C overlapping the first, lower metallization  85 A for less than half the length of the first metallization  85 A. 
         [0040]    Similarly, second submodule, channel, or cell (drain in an embodiment)  54 A may include a second, upper metallization  85 D overlapping the first, lower metallization  85 B for less than half the length of the first, lower metallization  85 B. The additional metallizations  85 C and  85 D may also include a plurality of contact pads or vias  62 C,  62 D coupling the second, upper metallization, finger, electrode, or track  85 C,  85 D to the first submodule, channel, or cell (source in an embodiment)  52 A, second submodule, channel, or cell (drain in an embodiment)  54 A semiconductor channel (n-type or p-type) or other section, segment, or layer. The second, upper metallizations  85 C,  85 D shorter length (less than half the length of the first, lower metallizations  85 A,  85 B) may reduce parasitic capacitance between adjacent metallizations  85 A,  85 B,  56 A,  85 C, and  85 D. The combination of the first, lower metallizations  85 A,  85 B and the second, upper metallizations  85 C,  85 D may help reduce the effects of electromigration. 
         [0041]      FIGS. 5A and 5B  are block diagrams of a semiconductor circuit or module  90  with a first, lower metallization or finger  98 A,  98 B and a second, upper metallization or finger  98 C,  98 D according to various embodiments. The first, lower metallizations or fingers  98 A,  98 B are similar to metallizations or fingers  58 A,  58 B shown in  FIG. 2B  with the addition of a third wide, proximal section  97 A,  97 B. In an embodiment the transistor  90  may only include the first metallizations  98 A,  98 B shown in  FIG. 5A . The transistor  90  may include the first  98 A,  98 B and a second, upper metallization  98 C,  98 D as shown in  FIGS. 5B . 
         [0042]    As shown in  FIG. 5A , the first metallizations  98 A,  98 B may extend along a substantial section of submodule, channel, or cell  52 A,  54 A length and include three sections ( 97 A,  95 A,  93 A), ( 97 B,  95 B,  93 B), each more distal section more narrow in width than the previous section. As shown in  FIG. 5B  the submodule, channel, or cell  52 A,  54 A (source, drain in an embodiment) may include a second, upper metallization  98 C,  98 D overlapping the first, lower metallization  98 A,  98 B for less than the length of the first, lower metallization  98 A,  98 B. The second, upper metallization  98 C,  98 D may include a first wide, proximal section  97 C,  97 D and a narrower, more distal section  95 C,  95 D. 
         [0043]    The second, upper metallizations  98 C and  98 D may also include a plurality of contact pads or vias  62 C,  62 D coupling the second, upper metallization, finger, electrode, or track  95 C,  95 D to the submodule, channel, or cell  52 A,  54 A (source, drain in an embodiment) semiconductor channel (n-type or p-type) or other section, segment, or layer. The second, upper metallizations  98 C,  98 D shorter length (less than the length of the first, lower metallizations  98 A,  98 B) may reduce parasitic capacitance between adjacent metallizations  98 A,  98 B,  56 A,  98 C, and  98 D. The combination of the first, lower metallizations  98 A,  98 B and the second, upper metallizations  98 C,  98 D may help reduce the effects of electromigration. 
         [0044]      FIGS. 6A and 6B  are block diagrams of a semiconductor circuit or module  110  with a first, lower metallization or finger  113 A,  113 B and a second metallization or finger  113 C,  113 D according to various embodiments. In an embodiment the submodule, channel, or cell  112 A,  112 B (source, drain in an embodiment) cross sectional shape may be tapered from a proximal to distal end with the submodule, channel, or cell  112 A,  112 B proximal end opposite the other of submodule, channel, or cell  112 A,  112 B proximal end distal end. The submodule, channel, or cell  112 A,  112 B (source, drain in an embodiment) geometry may reduce the effect of electromigration and reduce parasitic capacitance between the submodules, channels, or cells (source, drain in an embodiment)  112 A,  112 B. 
         [0045]    In an embodiment the semiconductor, module, or transistor  110  may only include first metallizations  113 A,  113 B as shown in  FIG. 6A . The metallizations, fingers, or electrodes  113 A and  113 B may continuously taper from its proximal end to its distal end similar to the respective first submodule, channel, or cell  112 A,  112 B. The transistor  110  may include also include a second, upper metallization  113 C,  113 D as shown in  FIG. 6B . As shown in  FIG. 6A , the first, lower metallization  113 A,  113 B may extend along a substantial section of the submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B length and include a plurality of contact pads  114 A,  114 B coupling the metallization, finger, electrode, or track  113 A,  113 B to the submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B semiconductor channel (n-type or p-type) or other section, segment, or layer. In an embodiment the contact pads  114 A,  114 B may also be tapered in shape similar to the metallizations, fingers, electrodes, or tracks  113 A,  113 B and the submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B. 
         [0046]    As shown in  FIG. 6B  a submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B may also include a second, upper metallization  113 C,  113 D overlapping a section of a first, lower metallization  113 A,  113 B for less than the length of the first, lower metallization  113 A,  113 B. The second, upper metallization  113 C,  113 D may be tapered similar to the first, lower metallization  113 A,  113 B. The second, upper metallizations  113 C,  113 D may also include a plurality of contact pads or vias  114 C,  114 D coupling the metallization, finger, electrode, or track  113 C,  113 D to a submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B semiconductor channel (n-type or p-type) or other section, segment, or layer. 
         [0047]    In an embodiment the contact pads  114 C,  114 D may be tapered in shape similar to the metallizations, fingers, electrodes, or tracks  113 C,  113 D, and the submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B. The second, upper metallizations&#39;  113 C,  113 D shorter length (less than the length of the first, lower metallizations  113 A,  113 B) and the submodule, channel, or cell (source, drain in an embodiment)  112 A,  112 B geometry may reduce parasitic capacitance between adjacent metallizations  113 A,  113 B,  116 A,  113 C, and  113 D. The combination of the first, lower metallizations  113 A,  113 B and the second, upper metallizations  113 C,  113 D may help reduce the effects of electromigration due the additional metallization at the channels  112 A,  112 B proximal end where the current density may be greater. 
         [0048]      FIGS. 7A and 7B  are block diagrams of a semiconductor circuit or module  130  with first, lower metallizations or fingers  133 A,  133 B and second, upper metallizations or fingers  133 C,  133 D according to various embodiments. In an embodiment a submodule, channel, or cell (source, drain in an embodiment)  132 A,  132 B cross sectional shape may be rectangular from a proximal end to a distal end. In an embodiment the transistor  130  may only include first metallizations  133 A,  133 B shown in  FIG. 7A . The metallization or fingers  133 A and  133 B may have a continuous taper from their proximal end to their distal end. The transistor  130  may include also second, upper metallizations or fingers  133 C,  133 D as shown in  FIG. 7B . 
         [0049]    As shown in  FIG. 7A , the first, lower metallizations or fingers  133 A,  133 B may extend along a substantial section of a submodule, channel, or cell (source, drain in an embodiment)  132 A,  132 B length and include a plurality of contact pads  134 A,  134 B coupling the metallizations, fingers, electrodes, or tracks  133 A,  133 B to a submodule, channel, or cell (source, drain in an embodiment)  132 A,  132 B semiconductor channel (n-type or p-type) or other section, segment, or layer. In an embodiment the contact pads  134 A,  134 B may be tapered in shape similar to the metallizations, fingers, electrodes, or tracks  133 A,  133 B. 
         [0050]    As shown in  FIG. 7B  a submodule, channel, or cell (source, drain in an embodiment)  132 A,  132 B may also include second, upper metallizations or fingers  133 C,  133 D overlapping a section of the first, lower metallizations or fingers  133 A,  133 B for less than the length of the first metallizations or fingers  133 A,  133 B. The second, upper metallizations  133 C,  133 D may be tapered similar to the first, lower metallizations  133 A,  133 B. The second, upper metallizations  133 C,  133 D may include a plurality of contact pads or vias  134 C,  134 D coupling the metallization, finger, electrode, or track  133 C,  133 D to the submodule, channel, or cell (source, drain in an embodiment)  132 A,  132 B semiconductor channel (n-type or p-type) or other section, segment, or layer. In an embodiment the contact pads  134 C,  134 D may be tapered in shape similar to the metallizations, fingers, electrodes, or tracks  133 C,  133 D. The second, upper metallizations  133 C,  133 D shorter length (less than the length of the first metallizations  133 A,  133 B) and the metallizations  133 A,  133 B,  133 C,  133 D tapered geometry may reduce parasitic capacitance between adjacent metallizations  133 A,  133 B,  136 A,  133 C, and  133 D. The combination of the first, lower metallizations  133 A,  133 B and the second, upper metallizations  133 C,  133 D may help reduce the effects of electromigration due the additional metallization at the channels  132 A,  132 B proximal ends where the current density may be greater. 
         [0051]      FIG. 8  is a flow diagram illustrating several methods  150  according to various embodiments. The method  150  may be employed to apply one or more metallizations  58 A-D,  75 A-B,  85 A-D,  98 A-D,  113 A-D,  133 A-D to one or more submodules  52 A-B,  54 A-B,  112 A-B,  132 A-B of a transistor or module  50 ,  60 ,  70 ,  80 ,  90 ,  110 , or  130 . The method  150  may apply a first metallizations layer  58 A-B,  75 A-B,  85 A-B,  98 A-B,  113 A-B,  133 A-B to a first submodule  52 A-B,  54 A-B,  112 A-B,  132 A-B including contact pads  62 A-D,  114 A-D,  134 A-D such as shown in  FIGS. 2B to 7B  (activity  152 A). The method  150  may apply a first, lower metallization, finger, or electrode  58 A-B,  75 A-B,  85 A-B,  98 A-B,  113 A-B,  133 A-B to a second submodule  52 A-B,  54 A-B,  112 A-B,  132 A-B including contact pads  62 A-D,  114 A-D,  134 A-D such as shown in  FIGS. 2B to 7B  (activity  152 B). 
         [0052]    The method  150  may apply a second or additional, upper metallizations, fingers, electrodes, or tracks  58 C-D,  75 C-D,  85 C-D,  113 C-D,  133 C-D to a submodule  52 A-B,  54 A-B,  112 A-B,  132 A-B including contact pads  62 A-D,  114 A-D,  134 A-D such as shown in  FIGS. 2B to 7B  (activity  156 A) when the module  50  submodule, channel, or cell includes multiple metallizations (activity  154 A). The method  150  may apply a second or additional, upper metallization layers  58 C-D,  75 C-B,  85 C-D,  113 C-D,  133 C-D to another submodule  52 A-B,  54 A-B,  98 A-D,  56 A-B,  112 A-B,  132 A-B including contact pads  62 A-D,  114 A-D,  134 A-D D such as shown in  FIGS. 2B to 7B  (activity  156 B) when the module  50  another submodule, channel, or cell includes multiple metallizations (activity  154 B). 
         [0053]    In an embodiment the metallizations, fingers, electrodes, or tracks  58 A-D,  75 A-B,  85 A-D,  98 A-D,  113 A-D,  133 A-D may have a width from 0.2 microns to 2.0 microns and vary about 1.0 microns from proximal to distal end in another embodiment. The submodules, channels, or cells (source or drain in an embodiment)  52 A-B,  54 A-B,  112 A-B,  132 A-B may have a width from 0.2 microns to 2.0 microns and vary about 1.0 microns from proximal to distal end in another embodiment. The contact pads  62 A-D,  114 A-D,  134 A-D may have a width from 0.1 microns to 1.5 microns and vary about 0.4 microns from proximal to distal end in another embodiment. 
         [0054]    The accompanying drawings that form a part hereof show, by way of illustration and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived there-from, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. 
         [0055]    Such embodiments of the inventive subject matter may be referred to herein individually or collectively by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept, if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. 
         [0056]    The Abstract of the Disclosure set forth below is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.