Abstract:
An apparatus comprising a pullup circuit, a pulldown circuit, and a control circuit. The pullup circuit may be configured to receive a first and second control signal. The pulldown circuit may be configured to receive a third and fourth control signal. The control circuit may be configured to generate the first, second, third and fourth control signals. The control circuit may comprise (i) a first and second control device coupled between the first and second control signals and a supply and (ii) a third and fourth control device coupled between the third and fourth control signals and the supply.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for current sources generally and, more particularly, to a method and/or architecture matching PMOS and NMOS current sources in charge pumps used in PLLs. 
     BACKGROUND OF THE INVENTION 
     Several conventional methods have been implemented to provide current matching between pullup and pulldown sections in charge pump phase lock loop (PLL) circuits. However, most conventional methods have improper matching and a higher output compliance requirement for good matching. 
     Referring to FIGS.  1 ( a-c ), conventional methods for current generation are shown. FIG. 1 a  illustrates a circuit  10 , FIG. 1 b  illustrates a circuit  20  and FIG. 1 c  illustrates a circuit  30 . Current matching simulation plots of the circuits  10 ,  20  and  30  are shown in FIGS.  2 ( a-c ), respectively. 
     The circuits  10  and  20  are cascode structures that do not provide accurate matching between NMOS and PMOS stacks. In particular, the resistance of the NMOS and PMOS devices that are closest to the supply voltage do not track each other due to differences between NMOS and PMOS devices when they enter saturation. Increasing current through the cascode stage or providing very large size discrimination may obtain better matching. However, the circuits  10  and  20  provide a current source with very low output compliance, particularly if only the NMOS or PMOS source is of interest. 
     A cascoded output stage provides a large output impedance, which is a general prerequisite for any current reference. One method of generating the cascode voltages PCAS and NCAS and the bias voltages PBIAS and NBIAS is by size discrimination or current discrimination in the two stages. The size discrimination generates unequal bias voltages PBIAS and NBIAS that drive a cascode output stage. 
     Ideally a constant current (or a multiple) flows through the two stages that generate the bias voltages PBIAS and NBIAS and the cascode voltage PCASC and NCASC. However, a mismatch occurs between the NMOS and PMOS stacks that mirror the cascode and bias voltages. The mismatch can be traced to the devices closest to the supply voltage. The mismatch occurs since the NMOS and PMOS devices can enter saturation at different drain to source voltages (i.e., Vdsnmos does not equal Vdspmos). Therefore, a different output resistance curve is traced by the two references, as shown in FIGS. 2 a  and  2   b.    
     The circuits  10  and  20  provide an output compliance range in the region of around 200 mV from either supply voltage. The devices closest to supply voltage operate on the edge of their linear limit (i.e., just as they enter saturation) before the negative feedback blocks any further increase in the drain to source voltage Vds. However, different resistance values for the NMOS and PMOS devices may result. Prior solutions have increased the size discrimination or current discrimination or both in the cascode and bias generation legs and obtained reasonable matching. However, such solutions are not best suited with respect to die area and current consumption constraints. 
     The circuit  30  requires a compliance voltage of a threshold voltage Vtn or (Vcc−Vtp) at the output before a high impedance output is delivered. The circuit  30  eliminates the mismatch associated with the circuits  10  and  20  by operating the devices closest to the supply voltage with a drain to source voltage Vds that is equal to at least a threshold voltage Vt. As Vds&gt;=Vt, the devices are pulled well into the saturation regions to provide matching between NMOS and PMOS output references. However, a disadvantage of the circuit  30  is that the minimum output compliance voltage is equal to one threshold voltage Vt from the supply voltage. Thus, the output compliance voltage is Vtn&gt;Vcompliance&lt;(Vcc−Vtp). 
     Generally, charge pumps should have a high output impedance in order to maintain a constant current across a range of control voltages used in frequency synthesis. Therefore, single MOS devices biased with a constant gate voltage are unsuitable due to channel length modulation which causes large mismatches between NMOS and PMOS currents. Such current mismatches can cause different phase offsets at different synthesized frequencies. A cascode device structure is usually a good choice to maintain constant current over a wide range of output voltages. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a pullup circuit, a pulldown circuit, and a control circuit. The pullup circuit may be configured to receive a first and second control signal. The pulldown circuit may be configured to receive a third and fourth control signal. The control circuit may be configured to generate the first, second, third and fourth control signals. The control circuit may comprise (i) a first and second control device coupled between the first and second control signals and a supply and (ii) a third and fourth control device coupled between the third and fourth control signals and the supply. 
     The objects, features and advantages of the present invention include providing a method and/or architecture for improved current matching in charge pumps that may be used in PLLs that may (i) improve current matching in NMOS and PMOS output stages, (ii) improve a specification margin for static phase offset in single ended charge pump implementations, (iii) have a lower output compliance compared to an otherwise equivalent-performing scheme, (iv) have matching between P and N stacks, (vi) provide less than 1% mismatch within the operating range, (vi) allow tracking between reference and mirror devices and/or (vii) allow compliance limits on an output voltage that are less than Vtn or (Vcc−Vtp). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIGS.  1 ( a-c ) are diagrams of conventional current matching circuits; 
     FIGS.  2 ( a-c ) are simulation graphs illustrating results of the conventional circuits for current matching; 
     FIG. 3 is a block diagram illustrating a context for implementing the present invention; 
     FIG. 4 is a diagram of a preferred embodiment of the present invention; and 
     FIG. 5 is a simulation plot illustrating an operation of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a block diagram of a circuit  50  illustrating a preferred embodiment of the present invention implemented in the context of a phase lock loop circuit is shown. The circuit  50  generally comprises a phase frequency detector (PFD)  52 , a charge pump  54 , and a voltage controlled oscillator (VCO)  56 . A capacitor C 1 , a capacitor C 2  and a resistor R may be used to filter the signal (e.g., CTRL) presented to the VCO  56  by the charge pump  54 . The present invention may be implemented within the charge pump  54 . 
     Phase lock loop circuits (PLLs) may be designed to meet skew specifications between an input reference clock signal (e.g., REF) and a generated feedback clock signal (e.g., V). Ideally, a zero skew is desired in order to meet a similar setup and hold timing requirement either with or without a PLL. However, a static phase offset between the reference clock signal REF and the feedback clock signal V may result from (i) mismatches in the PFD  52  and (ii) current mismatches coupled with transient response differences between NMOS and PMOS devices within the charge pump  54 . The present invention may reduce the mismatch between PMOS and NMOS currents in the charge pump  54 . 
     Referring to FIG. 4, a schematic diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises a pullup block (or circuit)  102 , a pulldown block (or circuit)  104 , and a control block (or circuit)  106 . The circuit  102  may be implemented as a pullup stack. The circuit  102  generally pulls the signal CRTL towards a power supply voltage in response to a bias signal or voltage (e.g., PBIAS) and a cascode signal or voltage (e.g., PCASC). The circuit  104  may be implemented as a pulldown stack. The circuit  104  generally pulls the signal CRTL towards a power supply ground in response to a bias signal or voltage (e.g., NBIAS) and a cascode signal or voltage (e.g., NCASC). A current (e.g., I) generally flows between the circuits  102  and  104  through a connection to a pad  113 . The circuit  106  may be configured to generate the signals PBIAS, PCASC, NBIAS, and NCASC. 
     The pullup circuit  102  generally comprises a transistor  110  and a transistor  112 . The transistors  110  and  112  may be implemented as one or more PMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. A gate of the transistor  110  generally receives the bias signal PBIAS. A source of the transistor  110  may be connected to the supply voltage. A drain of the transistor  110  may be connected to a source of the transistor  112 . A gate of the transistor  112  generally receives the cascode signal PCASC. A drain of the transistor  112  may be connected to the pad  113 . 
     The pulldown circuit  104  generally comprises a transistor  114  and a transistor  116 . The transistors  114  and  116  may be implemented as one or more NMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. A drain of the transistor  114  may be connected to the pad  113 . A gate of the transistor  114  generally receives the cascode signal NCASC. A source of the transistor  114  may be connected to a drain of the transistor  116 . A gate of the transistor  116  generally receives the bias signal NBIAS. A source of the transistor  116  may be connected to the voltage supply ground. 
     The control circuit  106  generally comprises a control circuit  120  and a control circuit  122 . The control circuit  120  generally controls the pullup circuit  102  by generating the signals PBIAS and PCASC. The control circuit  122  generally controls the pulldown circuit  104  by generating the signals NCASC and NBIAS. The control circuit  120  generally comprises a transistor M 1 , a transistor M 2 , and a transistor M 2 C. The transistors M 1 , M 2 , and M 2 C may be implemented as one or more PMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. The transistor M 1  generally creates a current path  142  to ground. A source of the transistor M 1  may be connected to the supply voltage. A drain and a gate of the transistor M 1  may be connected to a first terminal of a current source  142 . A second terminal of the current source  142  may be connected to a power supply ground. The signal PBIAS may be presented at the gate of the transistor M 1 . 
     The transistors M 2 C and M 2  generally create a current path  144  to ground. A source of the transistor M 2 C may be connected to the supply voltage. A gate of the transistor M 2 C may receive the signal PBIAS. A drain of the transistor M 2 C may be connected to a source of the transistor M 2 . A gate and a drain of the transistor M 2  may be connected to a first terminal of a current source  144 . A second terminal of the current source  144  may be connect to the power supply ground. The signal PCASC may be presented at the gate of the transistor M 2 . 
     The control circuit  122  generally comprises a transistor M 3 , a transistor M 3 C and a transistor M 4 . The transistors M 3 , M 3 C, and M 4  may be implemented as one or more NMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. The transistor M 3  may also be configured as a diode. The transistor M 4  generally creates a current path  146  from a supply voltage. A source of the transistor M 4  may be connected to the voltage supply ground. A drain and a gate of the transistor M 4  may be connected to a first terminal of a current source  146 . A second terminal of the current source  146  may be connected to a power supply voltage. The signal NBIAS may be presented at the gate of the transistor M 4 . 
     The transistors M 3  and M 3 C generally create a current path  148  from a supply voltage. A source of the transistor M 3 C may be connected to the power supply ground. A gate of the transistor M 3 C may receive the signal NBIAS. A drain of the transistor M 3 C may be connected to a source of the transistor M 3 . A gate and a drain of the transistor M 3  may be connected to a first terminal of a current source  148 . A second terminal of the current source  148  may be connect to the power supply voltage. The signal PCASC may be presented at the gate of the transistor M 3 . 
     The transistors M 1 , M 2 , M 2 C, M 3 , M 3 C, and M 4  may have a channel width to length ratio (e.g., W/L) that may be four times the W/L of the transistors  110 ,  112 ,  114 , and  116 . The current paths  142 ,  144 ,  146 , and  148  may pass, in one example, four times as much current as flows between the circuits  102  and  104 . 
     The circuit  100  may be implemented with compliance less than a threshold voltage Vt from the supply rail and may provide matching similar to the circuit  30  of FIG.  1 C. When considering the pulldown section  114  of the circuit  100  of FIG. 4, the signal NBIAS may be generated using conventional methods. By mirroring the signal NBIAS onto the cascode device M 3 C (which has a current that is generally sourced by the transistor M 3 ) matching similar to the circuit  30  can be obtained, but without the associated drawbacks (e.g., threshold voltage constraints, etc.). The transistor M 3 C does not develop a full voltage threshold Vtn of the drain to source voltage Vds to saturate. The transistor M 3 C requires less than a threshold voltage Vtn to saturate. As the saturation voltage Vdsat (which is generally less than the threshold voltage Vtn) is mirrored on the output stack of circuit  104 , the compliance requirements on node  113  are reduced. Furthermore, the compliance of the pullup stack  102  is also reduced. Since the transistors M 2 C and M 3 C are pulled away from soft saturation transistors  116  and  110 , the transistors  110  and  112  generally mirror the same effect and track with less mismatch. 
     Referring to FIG. 5, a simulation plot illustrating example waveforms of the present invention is shown. Resistance curves traced by the NMOS and PMOS output stages illustrate the current matching that the present invention may provide. 
     The circuit  100  may improve the matching between PMOS and NMOS current sources used in charge pump PLLS. Accurate matching is generally desired in order to reduce the static phase offset of the PLL generated clock. The circuit  100  may improve the compliance range, since the minimum compliance required is generally less than a threshold voltage Vt from the supply voltage. In particular, the circuit  100  may be useful in low voltage environments (e.g., supply voltages of 2.7 v, 1.8 v, or even lower). The devices of the control circuit  106  generally need not have a threshold voltage Vt equal to a drain to source voltage Vds to enter saturation. A value less than a threshold voltage Vt may cause saturation. The biasing allows a compliance less than the threshold voltage Vt from either power supply. 
     The circuit  100  provides improved matching in the NMOS and PMOS output stages ( 102  and  104 ) that ultimately improves margin to the specification of static phase offset in single ended charge pump implementations. 
     The circuit  100  may provide lower output compliance compared to an equivalent-performing scheme. The circuit  100  may also provide accurate matching between PMOS and NMOS stacks. Additionally, the circuit  100  may also provide less than 1% mismatch within the operating range. The circuit  100  may also provide accurate tracking between the reference device and mirror. The circuit  100  may also provide less than Vtn or (Vcc−Vtp) compliance limits on output voltage. The circuit  100  may also provide a current reference scheme suited for charge pump PLLs. The circuit  100  may also provide a constant current source with relatively low output compliance. 
     The present invention may have particular value based on design requirements. In particular, if low voltage operability and matching are desired, the present invention may be useful. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.