Abstract:
In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to semiconductor device structures and processes for fabricating high-voltage transistors. 
       BACKGROUND 
       [0002]    High-voltage, field-effect transistors (HVFETs) are well known in the semiconductor arts. Many HVFETs employ a device structure that includes an extended drain region that supports or blocks the applied high-voltage (e.g., several hundred volts) when the device is in the “off” state. In a conventional vertical HVFET structure, a mesa or pillar of semiconductor material forms the extended drain or drift region for current flow in the on-state. A trench gate structure is formed near the top of the substrate, adjacent the sidewall regions of the mesa where a body region is disposed above the extended drain region. Application of an appropriate voltage potential to the gate causes a conductive channel to be formed along the vertical sidewall portion of the body region such that current may flow vertically through the semiconductor material, i.e., from a top surface of the substrate where the source region is disposed, down to the bottom of the substrate where the drain region is located. 
         [0003]    In a traditional layout, a vertical HVFET consists of long continuous silicon pillar structure that extends across the semiconductor die, with the pillar structure being repeated in a direction perpendicular to the pillar length. One problem that arises with this layout, however, is that it tends to produce large warping of the silicon wafer during high temperature processing steps. In many processes, the warping is permanent and large enough to prevent the wafer from tool handling during subsequent processing steps. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0004]    The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only. 
           [0005]      FIG. 1  illustrates an example cross-sectional side view of a vertical HVFET structure. 
           [0006]      FIG. 2A  illustrates an example layout of the vertical HVFET structure shown in  FIG. 1 . 
           [0007]      FIG. 2B  is an expanded view of one portion of the example layout shown in  FIG. 2A . 
           [0008]      FIG. 3A  illustrates another example layout of the vertical HVFET structure shown in  FIG. 1 . 
           [0009]      FIG. 3B  is an expanded view of one portion of the example layout shown in  FIG. 3A . 
           [0010]      FIG. 4A  illustrates yet another example layout of the vertical HVFET structure shown in  FIG. 1 . 
           [0011]      FIG. 4B  is an expanded view of one portion of the example layout shown in  FIG. 4A . 
           [0012]      FIG. 5  illustrates an example layout of a wafer with die-to-die checkerboarding of HVFETs. 
           [0013]      FIG. 6  illustrates an example layout of a wafer with die-to-die checkerboarding of segmented HVFETs. 
           [0014]      FIG. 7  illustrates an example layout of a rectangular die with checkerboarded blocks of HVFET segments. 
           [0015]      FIG. 8  illustrates an example gate metal routing layout for the die shown in  FIG. 7 . 
           [0016]      FIG. 9  illustrates an example gate and source metal routing layout for the die shown in  FIG. 7 . 
           [0017]      FIG. 10  illustrates an expanded portion of the example layout shown in  FIG. 9 . 
       
    
    
     DETAILED DESCRIPTION  
       [0018]    In the following description specific details are set forth, such as material types, dimensions, structural features, processing steps, etc., in order to provide a thorough understanding of the present invention. However, persons having ordinary skill in the relevant arts will appreciate that these specific details may not be needed to practice the present invention. It should also be understood that the elements in the figures are representational, and are not drawn to scale in the interest of clarity. 
         [0019]      FIG. 1  illustrates an example cross-sectional side view of a vertical HVFET  10  having a structure that includes an extended drain region  12  of N-type silicon formed on an N+ doped silicon substrate  11 . Substrate  11  is heavily doped to minimize its resistance to current flowing through to the drain electrode, which is located on the bottom of the substrate in the completed device. In one embodiment, extended drain region  12  is part of an epitaxial layer that extends from substrate  11  to a top surface of the silicon wafer. A P-type body region  13  and N+ doped source regions  14   a  &amp;  14   b  laterally separated by a P-type region  16 , are formed near a top surface of the epitaxial layer. As can be seen, P-type body region  13  is disposed above and vertically separates extended drain region  12  from N+ source regions  14   a  &amp;  14   b  and P-type region  16 . 
         [0020]    In one embodiment, the doping concentration of the portion of epitaxial layer which comprises extended drain region  12  is linearly graded to produce an extended drain region that exhibits a substantially uniform electric-field distribution. Linear grading may stop at some point below the top surface of the epitaxial layer  12 . 
         [0021]    Extended drain region  12 , body region  13 , source regions  14   a  &amp;  14   b  and P-type region  16  collectively comprise a mesa or pillar  17  (both terms are used synonymously in the present application) of silicon material in the example vertical transistor of  FIG. 1 . Vertical trenches formed on opposite sides of pillar  17  are filled with a layer of dielectric material (e.g., oxide) that makes up dielectric region  15 . The height and width of pillar  17 , as well as the spacing between adjacent vertical trenches may be determined by the breakdown voltage requirements of the device. In various embodiments, mesa  17  has a vertical height (thickness) in a range of about 30 μm to 120 μm thick. For example, a HVFET formed on a die approximately 1 mm×1 mm in size may have a pillar  17  with a vertical thickness of about 60 μm. By way of further example, a transistor structure formed on a die of about 2 mm-4 mm on each side may have a pillar structure of approximately 30 μm thick. In certain embodiments, the lateral width of pillar  17  is as narrow as can be reliably manufactured (e.g., about 0.4 μm to 0.8 μm wide) in order to achieve a very high breakdown voltage (e.g., 600-800V). 
         [0022]    In another embodiment, instead of arranging P-type region  16  between N+ source regions  14   a  &amp;  14   b  across the lateral width of pillar  17  (as shown in  FIG. 1 ), N+ source regions and P-type regions may be alternately formed at the top of pillar  17  across the lateral length of pillar  17 . In other words, a given cross-sectional view such as that shown in  FIG. 1  would have either an N+ source region  14 , or a P-type region  16 , that extends across the full lateral width of pillar  17 , depending upon where the cross-section is taken. In such an embodiment, each N+ source region  14  is adjoined on both sides (along the lateral length of the pillar) by P-type regions  16 . Similarly, each P-type region  16  is adjoined on both sides (along the lateral length of the pillar) by N+ source regions  14 . 
         [0023]    Dielectric regions  15   a  &amp;  15   b  may comprise silicon dioxide, silicon nitride, or other suitable dielectric materials. Dielectric regions  15  may be formed using a variety of well-known methods, including thermal growth and chemical vapor deposition. Disposed within each of the dielectric layers  15 , and fully insulated from substrate  11  and pillar  17 , is a field plate  19 . The conductive material used to from field plates  19  may comprise a heavily doped polysilicon, a metal (or metal alloys), a silicide, or other suitable materials. In the completed device structure, field plates  19   a  &amp;  19   b  normally function as capacitive plates that may be used to deplete the extended drain region of charge when the HVFET is in the off state (i.e., when the drain is raised to a high voltage potential). In one embodiment, the lateral thickness of oxide region  15  that separates each field plate  19  from the sidewall of pillar  17  is approximately 4 μm. 
         [0024]    The trench gate structure of vertical HVFET transistor  80  comprises gate members  18   a  &amp;  18   b,  each respectively disposed in oxide regions  15   a  &amp;  15   b  on opposite sides of pillar  17  between field plates  19   a  &amp;  19   b  and body region  13 . A high-quality, thin (e.g., ˜500Å) gate oxide layer separates gate members  18  from the sidewalls of pillar  17  adjacent body region  13 . Gate members  18  may comprise polysilicon, or some other suitable material. In one embodiment, each gate member  18  has a lateral width of approximately 1.5 μm and a depth of about 3.5 μm. 
         [0025]    Practitioners in the art will appreciate that N+ source regions  14  and P-type body region  13  near the top of pillar  17  may each be formed using ordinary deposition, diffusion, and/or implantation processing techniques. After formation of the N+ source region  38 , HVFET  10  may be completed by forming source, drain, gate, and field plate electrodes that electrically connect to the respective regions/materials of the device using conventional fabrication methods (not shown in the figures for clarity reasons). 
         [0026]      FIG. 2A  illustrates an example layout of the vertical HVFET structure shown in  FIG. 1 . The top view of  FIG. 2A  shows a single, discrete HVFET comprising an upper transistor section  30   a  and a lower transistor section  30   b  on a semiconductor die  21 . The two sections are separated by a dummy silicon pillar  32 . Each section  30  comprises a plurality of “racetrack” shaped transistor structures or segments, each transistor segment comprises an elongated ring or oval that includes a silicon pillar  17  surrounded on opposite sides by dielectric regions  15   a  &amp;  15   b.  Pillar  17 , itself, extends laterally in the x and y directions to form a continuous, elongated, racetrack-shaped ring or oval. Disposed within dielectric regions  15   a  &amp;  15   b  are respective gate members  18   a  &amp;  18   b  and field plates  19   a  &amp;  19   b.  Field plate  19   a  comprises a single elongated member that terminates on either end in a rounded fingertip area. Field plate  19   b,  on the other hand, comprises an enlarged ring or oval that encircles pillar  17 . Field plates  19   b  of adjacent racetrack structures are shown merged such that they share a common member on a side. By way of reference, the cross-sectional view of  FIG. 1  may be taken through cut lines A-A′ of the example layout of  FIG. 2A . 
         [0027]    It should be understood that in the example of  FIG. 2A , each of the racetrack transistor segments has a width (i.e., pitch) in the y-direction of approximately 13 μm, a length in the x-direction in a range of about 400 μm to 1000 μm, with a pillar height of about 60 μm. In other words, the length to width ratio of the individual racetrack transistor segments comprising sections  30   a  &amp;  30   b  is in a range of about 30 up to 80. In one embodiment, the length of each racetrack shaped segment is at least 20 times greater than its pitch or width. 
         [0028]    Practitioners in the art will appreciate that in the completed device structure, patterned metal layers are used to interconnect each of the silicon pillars  17  of the individual transistor segments. That is, in a practical embodiment, all of the source regions, gate members, and field plates are respectively wired together to corresponding electrodes on the die. In the embodiment shown, the transistor segments in each section  30  are arranged in a side-by-side relationship in the y-direction substantially across a width of die  21 . Similarly, in the x-direction the additive length of the transistor segments of sections  30   a  &amp;  30   b  extend substantially over the length of die  21 . In the example layout of  FIG. 2A  the width of dielectric regions  15  separating the silicon pillars, as well as the width of the field plates, is substantially uniform across semiconductor die  21 . Laying out the transistor segments with uniform widths and separation distances prevents the formation of voids or holes following the processing steps used to conformably deposit the layers that comprise dielectric regions  15  and field plates  19 . 
         [0029]      FIG. 2B  is an expanded view of one portion of the example layout shown in  FIG. 2A . For purposes of clarity, only pillars  17  and dielectric regions  15   b  of each of the transistor segments is represented. Dummy silicon pillar  32  is shown separating the rounded end areas of dielectric regions  15   b  of respective transistor segment sections  30   a  &amp;  30   b.  In other words, the deep vertical trenches that are etched in the semiconductor substrate to define pillars  17  also define dummy silicon pillar  32 . In one embodiment, dummy silicon pillar  32  is made to have a width in the x-direction (i.e., that separates the transistor segment sections) that is as small as can be reliably manufactured. 
         [0030]    The purpose of segmenting the single die HVFET into sections separated by dummy silicon pillar  32  is to introduce lengthwise (x-direction) stress-relief in the elongated racetrack shaped transistor segments. Segmenting or breaking the transistor device structures into two or more sections relieves mechanical stress across the length of the die. This stress is induced by the oxide regions flanking the pillars and normally concentrates at the rounded ends of each racetrack segment. Relieving mechanical stress by segmenting the transistor device structures into two or more sections thus prevents undesirable warping of the silicon pillars and damage (e.g., dislocations) to the silicon caused by stress. 
         [0031]    It is appreciated that a tradeoff exists between the stress relief provided by a highly segmented layout and loss of conduction area. More segmentation results in greater stress relief, but at the expense of conduction area. In general, the greater the vertical height of the pillars and the larger the semiconductor die, the greater the number of transistor sections or segments that will be required. In one embodiment, for a 2 mm×2 mm die with 60 μm high pillars, adequate stress relief is provided in a HVFET with an on-resistance of about 1 ohm utilizing a layout comprising four racetrack transistor sections separated by dummy silicon pillars, each having a pitch (y-direction) of about 13 μm and a length (x-direction) of about 450 μm. 
         [0032]    In another embodiment, instead of a dummy pillar of silicon to separate pairs of racetrack transistor segments, each pair being located in a different section, a dummy pillar comprising a different material may be utilized. The material used for the dummy pillar should have a thermal coefficient of expansion close to that of silicon, or sufficiently different from that of the dielectric region so as to relieve the lengthwise stress induced by the dielectric regions flanking the silicon pillars. 
         [0033]      FIG. 3A  illustrates another example layout of the vertical HVFET structure shown in  FIG. 1 .  FIG. 3B  is an expanded view of one portion of the example layout shown in  FIG. 3A , just showing pillars  17 , oxide region  15   b , and an optional dummy silicon pillar  33 . Similar to the embodiment of  FIGS. 2A &amp; 2B ,  FIGS. 3A &amp; 3B  show a single, discrete HVFET comprising an upper transistor section  30   a  and a lower transistor section  30   b  on a semiconductor die  21 . But in the example of  FIGS. 3A &amp; 3B , the deep vertical trenches filled with oxide regions  15   b  and field plates  19   b  of transistor sections  30   a  and  30   b  overlap, or are merged, leaving small, diamond-shaped dummy silicon pillars  33  between the segmented transistor sections. In this embodiment, a single dummy pillar is centrally located between the four rounded ends of adjacent pairs of transistor segments over the two sections. In the example shown, for every N (where N is an integer greater than 1) racetrack segments or structures in a section  30  of the transistor comprising die  21 , there are a total of N−1 dummy pillars  33 . 
         [0034]      FIG. 4A  illustrates yet another example layout of the vertical HVFET structure shown in  FIG. 1 .  FIG. 4B  is an expanded view of one portion of the example layout shown in  FIG. 4A . Pillars  17  and oxide region  15   b  are just shown for clarity reasons in the expanded view of  FIG. 4B . In this example, the transistor segments comprising the HVFET of semiconductor die  21  are alternately shifted by half of the length of each racetrack segment, resulting in racetrack transistor segments that are alternately associated with upper transistor section  40   a  and lower transistor section  40   b . In other words, each of the transistor segments of a row of section  40   a  is separated by a pair of the transistor segments of section  40   b , the pair being arranged in an end-to-end relationship in the x-direction. 
         [0035]    It is appreciated that the alternate shifting of the segments may be any fraction of the segment length. In other words, shifting of the segments is not limited to 50% or half the length. Various embodiments may comprise segments alternately shifted by any percentage or fraction ranging from greater than 0% to less than 100% of the length of the transistor segments. 
         [0036]    In the example of  FIGS. 4A &amp; 4B , the dielectric regions  15   b  of alternating ones of the transistor segments in respective sections  40   a  &amp;  40   b  are merged. In the specific embodiment shown, the rounded ends of the transistor segments associated with different adjacent sections overlap or are merged such that field plates  19   b  of the adjacent sections are merged at the ends (in the x-direction). Also, the extended straight side portions of field plates  19   b  of alternating transistor segments of different sections are merged along a substantial length of each segment. It is appreciated that regions  15   b  and  19   b  may be merged with or without a dummy pillar (or isolated dummy silicon pillars) between the respective sections. 
         [0037]      FIG. 5  illustrates an example layout of a wafer  50  with die-to-die checkerboarding of HVFETs  10   a - 10   d  on semiconductor die  21   a - 21   d , respectively. Each of HVFETs  10  comprises a plurality of racetrack-shaped transistor segments such as that shown in  FIG. 1 , arranged side-by-side along their width into a substantially square block. In this example, HVFETs  10   a - 10   d  each comprises transistor segments having a length that extends substantially across the length of the respective die  21   a - 21   d . In one embodiment, the width of each segment is about 13 μm, with the length ranging from about 500 μm to 2000 μm. Other embodiments may have lengths greater than 2000 μm. The block or stacked arrangement of segments also extends substantially across the width of each die. (Note that the bordered square of each die  21  represents the edge of the scribe area between adjacent semiconductor die.) Although  FIG. 5  shows two rows and two columns of HVFETs  10  it is appreciated that the die-to-die checkerboarding arrangement shown may be repeated across the entire wafer substrate. 
         [0038]    In the example of  FIG. 5  adjacent die in a row or a column are oriented such that the length of the transistor segments in one die extends in one direction, with the length of the transistor segments in an adjacent die extending in a second orthogonal direction. For instance, HVFET  10   a  is shown with the length of its transistor segments oriented in the x-direction, whereas adjacent HVFETs  10   b  &amp;  10   c  By orthogonally alternating the orientation of the transistor segments in each individual die  21  across wafer  50  (i.e., checkerboarding) mechanical stress generated by the long dielectric regions is distributed in two orthogonal directions, thus reducing warping of wafer  50 . 
         [0039]      FIG. 6  illustrates another example layout of a wafer with die-to-die checkerboarding of segmented HVFETs. The example of  FIG. 6  utilizes the same approach as in  FIG. 5  of alternating the orientation of the transistor structures die-to-die; however, in the embodiment of  FIG. 6 , the HVFET structures are segmented into multiple (e.g., two) sections. For instance, each HVFET that extends substantially across the length and width of a semiconductor die  21  is segmented into two sections  30   a  &amp;  30   b  separated by a dummy pillar  32 . 
         [0040]    Each of the semiconductor die  21  shown in  FIG. 6  has a layout that is the same as that shown in  FIG. 2A  for a substantially square die. Similar to the example shown in  FIG. 5 , adjacent die have transistor segments that are orthogonally alternating across wafer  50 . That is, the transistor segments in sections  30   a  &amp;  30   b  of die  21   a  and  21   d  have a length oriented in the x-direction, whereas the transistor segments in sections  30   a  &amp;  30   b  of die  21   b  and  21   c  have a length oriented in the y-direction. 
         [0041]    It is appreciated that the HVFET of each die  21  may be formed with multiple transistor sections, e.g., greater than 2, each separated by one or more dummy pillars. Furthermore, any of the single die layouts with multiple transistor sections shown in the examples of  FIGS. 2A-4B  may be utilized in each of the die  21  shown in  FIG. 6 , with the orientation of the segments alternating die-to-die across wafer  50 . 
         [0042]      FIG. 7  illustrates an example rectangular layout of a die  25  with checkerboarded blocks of racetrack-shaped HVFET segments stacked in a side-by-side arrangement of substantially square blocks or sections  36 . Adjacent sections in a row or a column are oriented such that the length of the transistor segments in one section extends in one direction, with the length of the transistor segments in the other adjacent section extending in a second orthogonal direction. For example, each of the rows and columns of die  25  include transistor sections  36   a  oriented with the elongated transistor segments aligned in the x-direction and alternate transistor sections  36   b  oriented with the elongated transistor segments aligned in the y-direction. The spaces between sections  36   a  and  36   b  comprise dummy silicon pillars; that is, the silicon that forms the dummy pillars is not an active transistor region. 
         [0043]    In the embodiment shown, die  25  comprises three rows and four columns of transistor sections  36 . The checkerboarded layout approach shown in the example of  FIG. 7  may be used to produce a single, discrete HVFET on a die of virtually any (within practical limits) rectilinear-shape. 
         [0044]      FIG. 8  illustrates an example gate metal routing layout for the die shown in  FIG. 7 . The gate metal routing scheme of  FIG. 8  is fabricated using a single metal layer process with both source and gate metal disposed on the same planar level. The example shown includes horizontal gate metal bus lines  41   a - 41   d  that run between each row of the checkerboarded blocks of racetrack-shaped HVFET segments. For example, gate metal bus lines  41   a  &amp;  41   b  are shown extending horizontally along the top and bottom of the first (upper) row of checkerboarded sections  36  of  FIG. 7 . (It is appreciated that gate metal bus line  41   b  may be twice as wide as bus line  41   a  due to the face that bus line  41   b  provides a shared conduction path to the polysilicon gate members of both the first and second rows of checkerboarded sections.) 
         [0045]    Within each row, the sections  36  that have the length of their transistor segments aligned in the x-direction have half of the polysilicon gate members coupled to the top bus line, and a second half of the polysilicon gate members coupled to the bottom bus line. For instance, the upper left-hand block or section  36  in  FIG. 8  is shown having the polysilicon gate members represented by lines  44   a  connected to gate metal bus line  41   b  via contacts  45   a , whereas the polysilicon gate members represented by lines  44   b  in the same section are connected to gate metal bus line  41   a  via contacts  45   b . Note that each line  44   a  or  44   b  actually represents the two gate members  18   a  &amp;  18   b  (see  FIG. 1 ) of a single racetrack-shaped HVFET segment. Thus, lines  44   a  represent the gate members of the two left-most HVFET segments, and lines  44   b  represent the gate members of the two right-most HVFET segments, in the same section. Note further that each gate member is connected to a bus line (top or bottom) at one end only. 
         [0046]    The gate metal routing pattern shown in  FIG. 8  also includes vertical gate metal stub lines  42  that extend approximately half-way across each row of checkerboarded blocks. Within each section in which the length of the HVFET segments is aligned in the y-direction, half of the polysilicon gate members are coupled to one stub line, and the other half of the polysilicon gate members are coupled to another stub line. For example, the second section (from the left) in the upper row of  FIG. 8  shows a bottom half of the gate members (represented by lines  44   c ) connected to left-sided gate metal stub line  42   a  via contacts  45   c , with a top half of the gate members (represented by lines  44   d ) connected to right-sided gate metal stub line  42   b  via contacts  45   d . Similarly, the fourth section (right-hand most) in the upper row of  FIG. 8  shows a bottom half of the gate members connected to gate metal stub line  42   c  and a top half of the gate members connected to gate metal stub line  42   d . Note that each gate member of the horizontally-aligned segments is connected to a stub line (left or right side) at one end only. 
         [0047]    The reason why gate metal stub lines  42  extend only half-way across those sections having their segments aligned in the y-direction (i.e., horizontally) is to allow the source metal bus lines to extend across each row and contact the source regions of each transistor segment. This is illustrated by the example of  FIG. 9 , which shows a die  25  having individual source bus lines  61  that extend continuously across each row of transistor sections  36  between top and bottom gate metal traces  51 . (Metal traces  51  represent the merged metal bus lines  41  and stub lines  42  associated with each row.) For example, source bus lines  61   a  runs continuously across the upper row of sections on die  25  to contact each of the source regions  14  at the top of silicon pillars  17  for each HVFET segment in the row. In so doing, source bus lines  61   a  “snakes” between and around stub lines  42 , as well as between bus lines  41 , all of which are patterned on the same single layer of metal. 
         [0048]    Practitioners in the art will appreciate that by extending stub lines  42  approximately half-way across each row, the current handling capability of each source bus line  61  is maximized (i.e., minimum notching of lines  61 ). To put it differently, extending stub lines  42  vertically (in the x-direction) a distance other than half-way across each row would unnecessarily constrain or pinch current flow across source bus lines  61  due to the notching of lines  61  around stub lines  42 . Likewise, it should be understood that by connecting half of the gate members in a section to one gate metal bus (or stub) line, and the other half to another gate metal bus (or stub) line, electro-migration and resistance problems are minimized. 
         [0049]      FIG. 10  illustrates an expanded portion of the example layout shown in  FIG. 9  that shows one possible scheme for connecting gate metal trace  51  with gate members  18   a  &amp;  18   b . In this example, via contacts  55   a  &amp;  55   b  are shown connecting trace  51  with the rounded fingertip portion of gate members  18   a  &amp;  18   b , respectively. The source region at the top of pillar  17  located between gate members  18   a  &amp;  18   b  is shown connected to source metal bus  61  via contacts  75 . (It is appreciated that only two contacts  75  are shown for clarity reasons.) In an alternative embodiment, rather than contacting the rounded fingertip portion of gate members, gate metal trace  51  may connect along the straight, linear portion of gate members  18   a  &amp;  18   b  near the rounded fingertip portion. (Note that the field plates are not shown in the example of  FIG. 10  for clarity reasons.) 
         [0050]    Although the above embodiments have been described in conjunction with a specific device types, those of ordinary skill in the arts will appreciate that numerous modifications and alterations are well within the scope of the present invention. For instance, although HVFETs have been described, the methods, layouts and structures shown are equally applicable to other structures and device types, including Schottky, diode, IGBT and bipolar structures. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.