Abstract:
In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from European patent application No. 05425406.5, filed Jun. 6, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     An embodiment of the present invention relates to a process for manufacturing a high-quality wafer of semiconductor-on-insulator material (SOI—Silicon On Insulator).  
       BACKGROUND  
       [0003]     From commonly assigned patent application No. EP-A-1 324 382, which is incorporated by reference, a process is known for the manufacturing of SOI wafers by annealing and oxidation of buried channels. Said process is described briefly with reference to  FIGS. 1-5 .  
         [0004]     In an initial step ( FIG. 1 ), deep trenches  3  are formed in a silicon wafer  1  comprising a substrate  2 , by means of an anisotropic etching through an appropriately shaped resist mask  4 . In particular, the deep trenches  3  have a substantially rectilinear shape, extend parallel to one another, and are separated by silicon walls  5 .  
         [0005]     Next ( FIG. 2 ), the resist mask  4  is removed and, via an epitaxial growth, a surface layer  6  of silicon is formed, closing at the top the deep trenches  3  to form a plurality of buried channels  7 . Before the deep trenches  3  are closed at the top, a growth of silicon also occurs within them, causing a reduction in their dimensions. At the end of the epitaxial growth, the buried channels  7  consequently have an oval cross section elongated in a direction perpendicular to the surface of the wafer  1 .  
         [0006]     Then ( FIG. 3 ), a thermal annealing is performed, which causes a migration of part of the silicon atoms of the walls  5  surrounding the buried channels  7 , which move to a lower energy state. At the end of the annealing step, the buried channels  7  assume an approximately circular cross section, and the walls  5  thin out.  
         [0007]     Next ( FIG. 4 ), the wafer  1  is etched from the front to form a connection trench  8 , having a depth and a size such as to reach all the buried channels  7 . In particular, the connection trench  8  extends along a closed line delimiting an active area  9  of the surface layer  6 , wherein integrated components are subsequently formed (active area of the SOI wafer). Oxygen is then supplied through the connection trench  8  during a step of thermal oxidation so as to oxidize completely the walls  5  and the portions of silicon that surround the buried channels  7 , and partially the internal walls of the connection trench  8  and the buried channels  7 . An insulating region  10  is thus formed, which electrically separates the active area  9  from the substrate  2  and forms the buried-oxide layer of the SOI wafer ( FIG. 5 ). Finally, a layer of TEOS (TetraEthylOrthoSilicate) oxide can be deposited on the wafer  1  so as to fill the connection trench  8  and the buried channels  7  and form, with the insulating region  10 , a single insulating structure.  
         [0008]     The above process involves considerably lower costs as compared to traditional type processes. Furthermore, it has the advantages of enabling almost complete elimination of low-frequency parasitics, which are responsible for approximately 90% of the active silicon layer failures, and substrate gettering, thus ensuring a good quality of gate oxides (for CMOS or DMOS devices).  
         [0009]     However, said process may also have some drawbacks.  
         [0010]     In the first place, SOI wafers thus formed may have a higher thermal resistance (R th ) than SOI wafers formed with traditional type manufacturing processes: for example, it may be shown that the DC thermal resistance of a power LDMOS integrated in the SOI wafer active area undergoes an increase of approximately 25% as compared to the thermal resistance of a power LDMOS integrated in a traditional type SOI wafer. This is principally due to the presence, within the buried-oxide layer, of empty areas or voids set at regular intervals apart and not filled with dielectric material. In particular, empty areas can also remain even if filling with TEOS has been performed.  
         [0011]     The buried-oxide layer moreover has undulations ( FIG. 5 ) at the interface with the silicon, which may further reduce the quality of the SOI wafer as far as electrical characteristics are concerned.  
         [0012]     Furthermore, the thickness of the buried-oxide layer formed through said process may be excessively high for normal (i.e., non-power) applications.  
         [0013]     To reduce some of said problems, and in particular to eliminate the empty areas within the buried-oxide layer, it has been proposed to prolong the step of oxidation (pronounced oxidation) and to use shallower trenches. Furthermore, it has been proposed to act on the ratio width/depth of the trenches to reduce both the thickness of the buried-oxide layer and the undulations at the interface with the silicon. Said solutions have, however, proven not altogether satisfactory both because they may not provide a total reduction of the empty areas within the buried-oxide layer, and because the pronounced oxidation may cause stress in the adjacent silicon regions, which can lead to crystallographic defects (in the form of dislocations).  
       SUMMARY  
       [0014]     An embodiment of the present invention is a process for manufacturing SOI wafers that overcomes the aforesaid disadvantages and problems and, in particular, that forms high-quality SOI wafers.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     For a better understanding of the present invention, embodiments thereof are now described purely by way of non-limiting example and with reference to the attached drawings.  
         [0016]      FIGS. 1-3  are cross-sectional views of a wafer of semiconductor material in successive steps of a manufacturing process of a SOI wafer of a known type.  
         [0017]      FIG. 4  is a top plan view of the wafer of  FIG. 3 , in a subsequent step of the manufacturing process.  
         [0018]      FIG. 5  is a cross-sectional view of the wafer of  FIG. 4  taken along the line V-V.  
         [0019]      FIG. 6  is a top plan view of a wafer of semiconductor material in an initial step of a manufacturing process of a SOI wafer according to a first embodiment of the present invention.  
         [0020]      FIG. 7  is a cross-sectional view at an enlarged scale of details of  FIG. 6 , taken along the line VII-VII.  
         [0021]      FIGS. 8-10  are cross-sectional views of the wafer of semiconductor material of  FIG. 6  in subsequent steps of the manufacturing process according to the first embodiment of the invention.  
         [0022]      FIG. 11  is a top plan view of the wafer of  FIG. 10 .  
         [0023]      FIGS. 12 and 13  show an enlargement of a portion of a buried cavity of the wafer of  FIG. 11  during an oxidation step.  
         [0024]      FIG. 14  is a cross-sectional view of the wafer of  FIG. 11 , taken along the line XIV-XIV, in a final step of the manufacturing process according to the first embodiment of the invention.  
         [0025]      FIG. 15  is a cross-sectional view of a wafer of semiconductor material in a step of a manufacturing process of a SOI wafer in accordance with a second embodiment of the invention.  
         [0026]      FIG. 16  is a top plan view of the wafer of  FIG. 15 , in a subsequent step of the manufacturing process according to the second embodiment of the invention.  
         [0027]      FIGS. 17 and 18  are cross-sectional views of the wafer of  FIG. 16 , taken along the line XVII-XVII, in successive steps of the manufacturing process according to the second embodiment of the invention.  
         [0028]      FIGS. 19-21  show different structures of an etching mask which can be used in the manufacturing process according to an embodiment of the invention.  
         [0029]      FIG. 22  is a view similar to that of  FIG. 11 , according to a variation of the first embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0030]     Embodiments of a process for manufacturing a SOI wafer are now described. Said process is based, in part, upon the process described in commonly assigned European patent application No. 04 425 197.3, which was filed on Mar. 19, 2004 and which is incorporated by reference.  
         [0031]      FIG. 6  (not in scale, like all the following figures) shows a wafer  20  of semiconductor material, for example monocrystalline silicon, comprising a substrate  21 , for instance of an N type.  
         [0032]     In an initial step of the manufacturing process according to an embodiment of the invention, a resist layer is deposited on a top surface  20   a  of the wafer  20 , and the resist layer is defined so as to form a mask  22  (see also the cross section of  FIG. 7 ). In detail, the mask  22  has a lattice-shaped structure  22   a , extending on an approximately square area (as may be seen in the enlarged detail of  FIG. 6 ) and defining a plurality of openings  23 , also having an approximately square shape. For example, the distance t between opposite sides of the openings  23  may be 0.5 μm, and the distance d between facing sides of adjacent openings  23  may also be 0.5 μm.  
         [0033]     Using the mask  22  ( FIG. 8 ), an anisotropic etching of the wafer  20  is then performed, following upon which deep trenches  24  are formed at the openings  23 . The deep trenches  24  have, for example, a depth of 2 to 2.5 μm, and are separated from one another by walls  25  of semiconductor material, which form together a single separation structure, having a cross section corresponding to that of the structure  22   a.    
         [0034]     Subsequently, the mask  22  is removed, and an epitaxial growth is performed in a deoxidizing environment (typically, in an atmosphere with a high concentration of hydrogen, for example with trichlorosilane-SiHCl 3 ). Subsequently ( FIG. 9 ), an epitaxial layer  26 , for instance of an N type, grows in a controlled way on top of the walls  25  and closes the deep trenches  24  at the top, entrapping the gas therein. A step of thermal annealing is then performed, for example in a hydrogen atmosphere for 30 minutes at 1190° C., or, alternatively, in a nitrogen atmosphere for 13 hours. In particular, the annealing step causes a migration of the silicon atoms, which tend to migrate into positions of lower energy. Consequently, and also thanks to the relatively small thickness of the walls  25 , the silicon atoms migrate completely from the walls  25 , and the deep trenches  24  merge together, forming a single buried cavity  27 , which is uniform and entirely contained within the substrate  21 . For example, the buried cavity  27  has a square cross section with a side of 500 μm and has a thickness of 0.5 μm. A relatively thin layer of semiconductor material (for instance, having a thickness of approximately 1 μm) remains on top of the buried cavity  27 , said thin layer being constituted in part by epitaxially grown silicon atoms and in part by migrated silicon atoms. The thin layer forms a membrane surface region  28 , which is suspended in a flexible way above the buried cavity  27 .  
         [0035]     According to a first embodiment of the present invention ( FIG. 10 ), an etching is performed starting from the top surface  20   a  of the wafer  20  through an appropriate masking so as to form access trenches  30 , which extend through the surface region  28  and reach the buried cavity  27 . In particular (see also  FIG. 11 ), two access trenches  30  are formed having, for instance, an elongated rectilinear shape and extending parallel to one another, next to, and for the entire length of, two opposite sides of the surface region  28 .  
         [0036]     Next, a step of thermal oxidation of the internal walls of the buried cavity  27  is performed by supplying oxygen through the access trenches  30  (for example, at a temperature of 1150 to 1200° C. for 5 to 10 hours). Advantageously, in a way not shown, the masking used for the etching can be maintained in this step to protect the top surface  20   a  of the wafer  20  from oxidation. In detail, in an initial step of the oxidation process, as shown in  FIG. 12 , the oxygen atoms react with the silicon atoms at the internal walls of the buried cavity  27 , forming a top layer  32  and a bottom layer  33  of silicon oxide, separated by a gap  34 . In particular, the top layer  32  grows from silicon atoms of the surface region  28 , whilst the bottom layer  33  grows from silicon atoms of the substrate  21 . Subsequently, the oxygen atoms diffuse through the top and bottom layers  32 ,  33  (as highlighted by the arrows in  FIG. 12 ) to react at the interface with the silicon, increasing the thickness of the top and bottom layers  32 ,  33  and thus reducing the gap  34 . In a final stage of the oxidation process ( FIG. 13 ), the top layer  32  and the bottom layer  33  come into contact with one another, and complete closing of the gap  34  occurs. When the top layer  32  and the bottom layer  33  come into contact, oxygen atoms are still diffusing towards the interface with the silicon (as highlighted by the arrows). The further supply of oxide that follows thereon, although limited, determines a pressure in the interface region between the top layer  32  and the bottom layer  33 , causing the bonding between the two layers. In particular, it is reasonable to suppose that silicon-bridge bonds (Si—O—Si) are created in a way similar to what occurs, for instance, in the case of bonding between two oxidized wafers.  
         [0037]     Consequently ( FIG. 14 ), at the end of oxidation, a flat, compact and uniform buried-oxide layer  35  is formed within the buried cavity  27 , separating the surface region  28  (i.e., the active region of the SOI wafer), from the substrate  21 , in this way determining the classic SOI structure. Furthermore, also the access trenches  30  come to be filled with oxide, thus laterally constituting insulating regions  36  for the active region of the SOI wafer. The resulting thickness of the buried-oxide layer  35  is principally a function of the dimensions (depth and width) of the deep trenches  24  and of the walls  25 . In particular, with the described process it is possible to obtain a buried-oxide layer  35  having a minimum thickness of approximately 1 μm.  
         [0038]     Subsequently, within the surface region  28  (in a known manner which is not illustrated) active or passive components, sensors, or other micro-electromechanical structures are integrated, which can, for instance, be electrically insulated from one another by further trenches having a depth such as to reach the buried-oxide layer  35 .  
         [0039]     A second embodiment of the present invention again envisages the formation of the surface region  28 , suspended above the buried cavity  27  to form a flexible membrane, with the difference that, in this case, the buried-oxide layer  35  is formed with recessed-LOCOS processes.  
         [0040]     In detail, following upon the formation of the surface region  28  and of the buried cavity  27  (as shown in  FIG. 9 ), a pad-oxide layer  37  is formed on the top surface  20   a  of the wafer  20 , and on the latter a sacrificial layer  38  of silicon nitride. Then a resist layer is deposited, which is appropriately defined so as to form an etching mask  39  ( FIG. 15 ).  
         [0041]     Subsequently ( FIGS. 16 and 17 ), through the etching mask  39 , the sacrificial layer  38 , the pad-oxide layer  37 , and part of the surface region  28  and of the substrate  21  are etched, in sequence. So, a plurality of recesses  40  are opened at the periphery of the surface region  28 , each of which extends in part through the surface region  28  and in part through the substrate  21  and has a depth such as to reach the buried cavity  27 . In detail, the recesses  40  are aligned at regular intervals along the sides of the surface region  28 . Connection bridges  41  of semiconductor material are provided between adjacent recesses  40 ; the connection bridges  41  connect the surface region  28  to the substrate  21 , supporting the surface region  28  over the buried cavity  27  during the etching step.  
         [0042]     Next, the recesses  40  are thermally oxidized (recessed-LOCOS process), which leads to the formation of an oxide region, selectively in the areas not covered by the sacrificial layer  38  (for example, oxidation is performed at a temperature of 1100° C. for 3 to 4 hours). In particular, the oxide region has a first portion that fills the inside of the buried cavity  27  uniformly to form the buried-oxide layer  35 , and a second portion that fills the recesses  40  to form the insulating region  36 . In particular, the insulating region  36  also engulfs the connection bridges  41 , which are completely oxidized given their relatively small dimensions, thus completely surrounding and insulating the surface region  28 .  
         [0043]     Then, the sacrificial layer  38  is removed to obtain the structure of  FIG. 18 , where the classic SOI structure is again recognizable. In particular, recessed-LOCOS type oxidation often allows a good surface planarity of the final structure to be achieved.  
         [0044]     The above described process embodiments has numerous advantages.  
         [0045]     In fact, they often allow high-quality SOI wafers to be obtained with low production costs, in so far as they envisages the use of standard techniques normally used in the semiconductor industry.  
         [0046]     In particular, a compact (i.e., without any empty regions) and flat (i.e., without any undulations) buried-oxide layer can be formed. In particular, the surface region  28  has an almost planar bottom surface in contact with the buried-oxide layer  35 . The SOI wafers thus obtained may also keep the advantage linked to the elimination of low-frequency parasitics.  
         [0047]     In addition, it is possible to achieve a particularly small thickness of the buried-oxide layer, such that said SOI wafers can be advantageously used for the integration of non-power components.  
         [0048]     Furthermore, the first embodiment described (thermal oxidation through trenches) can be advantageously applied also in BCD (Bipolar CMOS DMOS) power technologies, wherein a larger thickness of the surface region  28  (in the order of some ten microns) is envisaged, whilst the second embodiment described (recessed-LOCOS oxidation) is particularly advantageous in VLSI (Very Large-Scale Integration) technologies, wherein a smaller thickness of the surface region  28  is envisaged (smaller than a micron).  
         [0049]     Finally, it is clear that modifications and variations can be made to what is described and illustrated herein, without thereby departing from the scope of the present invention.  
         [0050]     In particular, the structure of the mask  22  and the shape of the walls  25  and of the deep trenches  24  can vary with respect to what is illustrated.  
         [0051]     For instance,  FIG. 19 , the mask  22  can have a structure  22   a  shaped like a grid, and define openings  23  having a strip-like shape and extending parallel to one another, separated by walls  25  also shaped like strips.  
         [0052]     Alternatively, the mask  22  can have a complementary structure with respect to what is illustrated in  FIG. 6 . In particular ( FIGS. 20-21 ), the mask  22  can comprise a plurality of portions  22   b  of a polygonal shape (for instance, square or hexagonal), regularly arranged to define a lattice-shaped opening  23  (square or honeycomb-shaped).  
         [0053]     More in general, the walls  25  can be relatively thin structures enabling complete migration of the silicon atoms during the annealing step, which leads to the formation of the buried cavity  27 .  
         [0054]     The masks  22  with lattice-shaped structure are in any case often the best in terms of crystallographic quality of the silicon surface region  28 , and hence more advantageous to use in the described manufacturing process.  
         [0055]     In addition, the geometrical shape of the surface region  28  can be different; for instance, it may be circular or generically polygonal.  
         [0056]     The thickness of the buried-oxide layer  35  can be further reduced to increase the compatibility with integration techniques of the VLSI type. For this purpose, it is possible to scale down even further the dimensions of the mask  22  and in particular to reduce the size of the openings  23 . This can be achieved by resorting to higher-performance lithographies, or else to the so-called “self-assembled polymer” technique. As described in detail in “Process integration of self-assembled polymer templates into silicon nanofabrication”, K. W. Guarini, et al., J. Vac. Sci. Technol. B 20(6), November/December 2002, which is incorporated by reference, it is possible to obtain the mask  22  starting from a self-assembled polymer film. The blocks of polymers, in fact, organize themselves spontaneously in a lattice of hexagonal pores, having diameters of up to 20 nm and centre-to-centre spacings of up to 42 nm. Said lattice can be deposited on top of the surface  20   a  of the wafer  20  and used as mask  22  to obtain deep trenches  24  and walls  25  of extremely small dimensions (in the order of a few tens of nanometers). The thickness reduction of the buried-oxide layer  35  allows, among other things, a better thermal dissipation towards the substrate  21  to be achieved.  
         [0057]     Furthermore ( FIG. 22 ), according to a variation of the first embodiment, a single access trench  30  is formed next to one of the sides of the surface region  28 . Also in this case, it is possible to envisage oxidation of the buried cavity  27  to form the buried-oxide layer  35 . Again, the components that will be integrated in the surface region  28  may have to be electrically insulated in an appropriate way, for instance via the formation of further trenches, of a depth such as to reach the buried-oxide layer  35 .  
         [0058]     In particular, simultaneously with the formation of the access trench  30  it is possible to provide, aligned along the remaining sides of the surface region  28 , a plurality of recesses  40  alternating with connection bridges  41  (in a way similar to what has been described with reference to  FIG. 16 ) so as to provide, with the subsequent oxidation, a complete insulation of the surface region  28  with respect to the substrate  21 .  
         [0059]     Moreover, an SOI wafer formed as described above may be scribed into dies, from which integrated circuits (ICs) may be formed. And such an IC may be incorporated into an electronic system such as a computer system.  
         [0060]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.