Abstract:
A digital control system for an internal combustion engine uses a two stage register. The register is used to store digital data representative of sensed engine operating conditions and to feed such data to a programmable digital computer for processing. Processing time is improved by reading only one register containing the most significant data bits of the stored data for engine parameters having a relatively narrow dynamic range and reading both registers, containing all data bits of the stored data for engine parameters having a relatively large dynamic range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a digital control system for an internal combustion engine, and more particularly to an improvement in the method and apparatus of storing and processing digital output data from an analogue to digital convertor for optimal use by a processor of the control system. 
     2. Description of the Prior Art 
     It is known to utilize a digital control system for an internal combustion engine. The digital control system generally employs sensors which provide analogue output signals indicative of engine operating conditions such as air flow rate, engine coolant temperature, power source voltage, and others. In such a control system, an analogue to digital convertor (A/D convertor) transforms the analogue signals indicative of engine operating conditions into the corresponding digial signals, and a microprocessor receives the digital signals to determine the amount of fuel to be injected into the engine and the ignition timing to control the engine in response to the engine operating conditions. 
     The desired degree of accuracy in the transforming process of the A/D convertor depends on the kind of analogue input data. The data indicative of the air flow rate, for example, having a relatively great dynamic range needs an accuracy higher than that of the data having a relatively small dynamic range, such as data indicative of engine coolant temperature or the power source voltage. However all such data are commonly transformed into a fixed-bit, e.g., 10-bit, digital signals for simplifying the making of the system and especially the A/D convertor. These 10-bit signals are stored in a two-stage register each stage having one byte. Such a conventional system has a characteristic that data must be read out from both the register stages, necessitating two reading operations even when low accuracy is all that is required e.g. 8-bits, as will be described hereinafter. Such operation makes the calculation process complicated and the operation time undesirably long. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a digital control system for an internal combustion engine powering a vehicle or other device, wherein multi-level accuracy may be provided for input data to the conrtrol system. 
     Another object of the present invention is to provide a method and apparatus for use in a device, such as a vehicle engine, which has a programmable digital computer control system for controlling the device in response to sensed input signals which are indicative of device operating parameters. The method and apparatus permits optimal use of the digital computer in receiving and processing digital input signals which are fed to the digital computer from analogue sensors via an A/D convertor and a two-stage storage register. Either one or both stages of the two-stage storage register may selectively be used as required by the degree of accuracy and dynamic range of the sensed input parameter and the requirements of the subsequent calculation or processing by the digital computer. 
     According to the present invention, a digital control system for an internal combustion engine, includes first and second sensors for detecting first and second engine operating conditions as first and second analogue signals respectively. The first analogue signal has a dynamic range less than that of the second. A multiplexer is connected to the first and second sensors for selecting either first or second analogue signals. An analogue to digital convertor is connected to the multiplexer for transforming the selected analogue signal into a corresponding digital signal with a first number of bits. A first register is connected to the analogue to digital convertor for storing a second preset number of sequentially ordered bits of the digital signal starting with the most significant bit. The second preset number is less than the first preset number. A second register is connected to the analogue to digital convertor for storing the remaining bits of the digital signal. A control unit is connected to the multiplexer for controlling the selection of the first and second analogue signals. The control unit is also connected to the first and second registers for reading out only the second preset number of bits of the digital signal stored in the first register when the control unit controls the multiplexer to select the second analogue signal and reading out all the bits of the digital signal stored in the first and second registers when the control unit controls the multiplexer to select the first analogue signal. The control unit controls the engine in response to the first and second engine operating conditions. 
    
    
     The above and other objects, features and advantages of the present invention will be apparent from the following description of a preferred embodiment thereof, taken in conjunction with the drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of circuit contained within a digital control system for an internal combustion engine of the prior art; 
     FIG. 2 is a schematic diagram of circuit constituting a digital control system for an internal combustion engine of the present invention; 
     FIG. 3 is a schematic diagram of circuit including a multiplexer, an A/D convertor, and a register of FIG. 2; and 
     FIG. 4 is a flowchart of the program stored in the ROM of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The pertinent portion of the aforementioned conventional control system for an internal combustion engine is illustrated in FIG. 1, wherein a multiplexer 10 selects and feeds one of the three kinds of analogue input data Da 1 , Da 2 , and Da 3  indicative of engine operating conditions to an analogue to digital convertor (A/D converter) 12, which transforms the selected data into the corresponding parallel 10-bit digital form. The A/D convertor 12 is connected to a register 14 for feeding the digital data to the register 14. The register 14 includes high and low byte storage locations 14H and 14L to store the 10-bit digital data. In FIG. 1, the output connections of the A/D convertor 12 to the register 14 are explicitly shown for output bits B1, B2 and B9, B10. For simplicity of illustration, the remaining connections are only generally indicated by a line 16 indicative of the remaining lines associated with the remaining bit positions B3-B8. 
     In operation of the circuit of FIG. 1, the convertor 12 feeds the digital output data in the form of &#34;1001100110&#34;, for example, to the register 14. The eight least significant bits of the data, &#34;01100110&#34;, are stored in the low byte storage location 14L in the order from the least to the most significant bits (from right to left in FIG. 1). The two most significant bits, &#34;10&#34;, are stored in the high byte storage location 14H in the order from the least to the most significant bit (right to left). It is a characteristic of such conventional systems that data must be read out from both the high and low byte storage locations 14H and 14L, necessitating two reading operations even when low accuracy is all that is required e.g. 8-bits. Such operations makes the calculation process complicated and the operation time undesirably long. 
     Referring now to FIG. 2, there is shown a digital computer control system for an internal combustion engine according to an embodiment of the present invention, wherein sensors 30, 32, 34. 36, and 38 are provided for detecting engine operating conditions including the power source voltage. The sensor 30 is attached to an air intake duct and produces a voltage signal as an analogue input data Da 1  having a magnitude which depends on the flow rate of intake air. The sensor 32 is attached to an engine block and produces a voltage signal as an analogue input data Da 2  having a magnitude which depends on the temperature of engine coolant. The sensor 34 detects the voltage of the power source as an analogue input data Da 3 . In this case, the sensor 34 merely consists of lines which are connected to the power source (not shown) to transmit the voltage thereof. The sensor 36 is associated with an engine crankshaft (not shown) and produces a pulse signal Db 1  upon rotation of the engine crankshaft at each preset rotational-angle thereof. The sensor 38 is associated with an engine throttle valve (not shown) and produces an on-off signal Db 2  which depends on whether or not the throttle valve is fully closed. The sensed analogue input data signals Da 1 , Da 2 , and Da 3  and signals Db 1  and Db 2  are fed to an input/output circuit (I/O circuit) 40 through filters 42, 44, 46, 48, and 50 respectively. These filters eliminate noise from the respective signals Da 1 , Da 2 , Da 3 , Db 1 , and Db 2 . 
     The I/O circuit 40 is connected to a central processor unit (CPU) 52 and a memory unit 54 by means of a bus 56. The I/O circuit 40, the CPU 52, and the memory unit 54 constitute a microcomputer control unit for the engine. The I/O circuit 40 is also connected to an electrically-driven fuel injector 58, an engine ignition unit 60, and a fuel pump 62 through amplifiers 64, 66, and 68 respectively. The CPU 52 and the memory unit 54 are interconnected by the bus 56. The bus 56 contains a data bus 56a, an address bus 56b, and a control bus 56c which perform delivery and receipt of data, address, and control information respectively among the I/O circuit 40, the CPU 52, and the memory unit 54. In accordance with a program stored in the memory unit 54, the CPU 52 and the memory unit 54 determine the desired amount of fuel injected into the engine and the desired ignition timing by calculation or table look up using the sensed signals Da 1 , Da 2 , Da 3 , and Db 1  fed through the I/O circuit 40. The I/O circuit 40 produces control signals Dc 1  and Dc 2  in response to the desired values of the amount of fuel injected and the ignition timing fed from the CPU 52 and the memory unit 54, and supplies the control signals Dc 1  and Dc 2  to the fuel injector 58 and the engine ignition unit 60 via the amplifiers 64 and 66 respectively in a conventional way. Thus, the digital computer unit controls the amount the fuel injected and the ignition timing in response to the engine operating conditions. In fact, the control signal Dc 1  takes the form of a pulse train which is synchronous with the engine crankshaft rotation, and the CPU 52 and the memory unit 54 determine the pulse width of the control signal Dc 1  which corresponds to a period during which the fuel injector 58 is open to inject fuel, and thus to control the amount of fuel injected. Since the fuel injector 58 has a response time for opening which depends on the power source voltage applied thereacross, the pulse width of the control signal Dc 1  is corrected by the CPU 52 and the memory unit 54 in response to the power source voltage. The pulse width of the control signal Dc 1  is also corrected by the CPU 52 and the memory unit 54 in response to the engine coolant temperature to obtain optimum engine operation under all temperature regions of engine coolant. Meanwhile, the control signal Dc 2  takes the form of a pulse train which determines the ignition timing and the dwell time of current conduction in the primary ignition coil (not shown) of the ignition unit 60. The CPU 52 and the memory unit 54 determine the pulse generating time of the control signal Dc 2  for the ignition timing control. Various algorithms may be utilized for determining such timing, and, for example, such timing may be determined in response to the engine speed (RPM) and the pulse width of the control signal Dc 1 . The CPU 52 also determines the pulse width of the control signal Dc 2  for the dwell time control, for example, in response to the power source voltage for the purpose of correction. 
     The I/O circuit 40 includes a multiplexer 70, an analogue to digital convertor (A/D convertor) 72, a register 74, a pulse input circuit 76, a pulse output circuit 78, and a discrete input/output circuit 80. The multiplexer 70 is connected to the filters 42, 44, and 46 for receiving the analogue input data signals Da 1 , Da 2 , and Da 3  from the air flow sensor 30, the engine coolant temperature sensor 32, and the power source voltage sensor 34. The multiplexer 70 selects one of the analogue input data signals Da 1 , Da 2 , and Da 3  according to a command from the CPU 52. The command takes the form of control signals transmitted along the control bus 56c to the select terminals of multiplexer 70 via selection lines 70a and 70b. The A/D convertor 72 is connected to the multiplexer 70 for receiving the selected analogue input data signal from the multiplexer 70. The A/D converter 72 transforms the selected analogue signal into the corresponding digital data signals. The register 74 is connected to the A/D convertor 72 for receiving the digital output data signals from the A/D convertor 72. The register 74 stores the digital output data signals according to a command from the CPU 52. The command takes the form of control signals S 1  and S 2  transmitted along the control bus 56c to the strobe terminals of register 74 via strobe lines 74a and 74b respectively. The register 74 is connected to the data bus 56a for transmitting the stored data signal to the memory unit 54. 
     The pulse input circuit 76 is connected to the filter 48 for receiving the pulse signal Db 1  from the crank angle sensor 36. The pulse input circuit 76 consists of a pulse shaping circuit which transforms the pulse signal Db 1  into a corresponding rectangular pulse signal. The pulse input circuit 76 is connected to the data bus 56a for feeding the rectangular pulse signal to the CPU 52 and the memory unit 54 to determine engine rotational speed (RPM). The pulse output circuit 78 is connected to the bus 56 for producing and outputting the control signals Dc 1  and Dc 2  which are responsive to the desired values of the amount of fuel injected and the ignition timing respectively. The pulse output circuit 78 is also connected to the pulse input circuit 76 for receiving the crank angle pulse signal as a reference of ignition timing control. The discrete input/output circuit 80 is connected to the filter 50 for receiving the sensed signal Db 2  representative of the fully-closed position of throttle valve or the engine idling condition. The discrete input/output circuit 80 is connected to the fuel pump 62 via the amplifier 68 for feeding a control signal Dc 3  to the fuel pump 62. The discrete input/output circuit 80 controls the fuel pump 62 in response to the sensed signal Db 2  and, for example, reduces the rotational speed of fuel pump 62 to decrease a running noise of fuel pump 62 when the engine is under idling condition where the engine needs to be supplied with a relatively small amount of fuel injected. 
     As shown in FIG. 3, the A/D converter 72 has 10 output bits B1 to B10 and thus transforms the analogue signal selected by the multiplexer 70 into the corresponding parallel 10-bit digital data signals, for example &#34;1001100110&#34;. The register 74 consists of high and low byte storage locations 74H and 74L of the parallel-in parallel-out type having the respective strobe terminals connected to the strobe lines 74a and 74b respectively (see FIG. 2). The output bits B10 to B3, the eight most significant output bits of A/D convertor 72 are connected to the high byte storage location 74H in the order from the most to least significant bits (from left to right in FIG. 3). The output bits B2 and B1, the two least significant output bits of A/D convertor 72 are connected to the low byte storage location 74L in the order from the most significant bit to least significant bit (left to right). In FIG. 3, the output connections of the A/D converter 72 are explicitly shown for the output bits B1, B2 and B9, B10. For simplicity of illustration, the remaining connections are only generally indicated by a line 82 indicative of the remaining lines associated with the remaining bit positions B3-B8. Thus, the eight most significant bits of the signal converted by the A/D convertor 72, for example &#34;10011001&#34;, are stored in the high byte storage location 74H in the order from the most to least significant bit positions thereof, as shown in FIG. 3. The remaining two least significant bits of the converted signal, for example &#34;10&#34;, are stored in the low byte storage location 74L. 
     The memory unit 54 consists of a read only memory (ROM) 54A and a random access memory (RAM) 54B. The ROM 54A stores the program for controlling the I/O circuit 40, the CPU 52, and the memory unit 54 to determine the amount of fuel injected and the ignition timing. According to the program written in the ROM 54A, the I/O circuit 40, the CPU, and the memory unit 54 are controlled in a sequence as shown by the flowchart of FIG. 4. In a first block 100, the desired values of the amount of fuel injected, namely the pulse width of the control signal Dc 1 , and the ignition timing are determined by use of the signals Da 1 , Da 2 , Da 3 , and Db 1  indicative of the engine operating conditions. The control signals Dc 1  and Dc 2  are produced in response to the determined values of the pulse width and the ignition timing and outputted from the pulse output circuit 78 to the fuel injector 58 and the engine ignition unit 60 via the amplifiers 64, 66 respectively. In fact, the engine speed (RPM) is, firstly, determined by use of the signal Db 1  fed via the pulse input circuit 76 in a conventional way. Secondly, the pulse width of the control signal Dc 1  may be calculated, for example, by use of the following equation. Pw=K 1  ·Q/N+K 2 , where Pw is pulse width; Q is flow rate of intake air; N is engine speed; K 1  is constant depending on engine coolant temperature for temperature correction; and K 2  is constant depending on power source voltage for voltage correction. Thirdly, the desired ignition timing is determined in response to the engine speed and the pulse width in a conventional way by looking up a table which holds a set of desired ignition timings as a function of engine speed and pulse width in the ROM 54A. Fourthly, the desired dwell time for ignition is determined in response to the power source voltage. Finally, the determined values of the pulse width, the ignition timing, and ignition dwell time are fed to the pulse output circuit 78 to produce the control signals Dc 1  and Dc 2  . The specific algorithms utilized in the block 100 are not germane to the present invention. Many different algorithms may be employed such as shown in U.S. Pat. Nos. 4,199,812, 3,696,614. 
     In a second block 102, the control signal for selecting the analogue data signal Da 1  is transmitted to the select terminals of multiplexer 70 along the control bus 56c and the selection lines 70a and 70b. Then, the data signal Da 1  is selected among the analogue data signals Da 1 , Da 2 , and Da 3  by the multiplexer 70 and is fed to the A/D convertor 72 to be transformed into the corresponding 10-bit digital form. The digital data signals from the A/D converter 72 are stored in the register 74 (both high and low byte storage locations 74A and 74B respectively). In a third block 104, the control signal S 1  is transmitted along the control bus 56c and the strobe line 74a to the strobe terminal of the high byte storage location 74H of the register 74. In response to this control signal S 1 , the eight most significant bits of the data corresponding to the analogue signal Da 1  are read out from the high byte storage location 74H and transmitted along the data bus 56a to the RAM 56B to be again stored. In a fourth block 106, the control signal S 2  is transmitted along the control bus 56c and the strobe line 74b to the strobe terminal of the low byte storage location 74L of the register 74. Then, the remaining two least significant bits of the data corresponding to the analogue signal Da 1  are read out and transmitted along the data bus 56a to the RAM 54B to be stored. Thus, the 10-bit digital data corresponding to the signal Da 1  are entirely read out and stored in the RAM 54B. In a fifth block 108, the control signal for selecting the analogue data signal Da 2  is transmitted to the select terminals of multiplexer 70 along the control bus 56c and the selection lines 70a and 70b. Then, the analogue data signal Da 2  is selected among the analogue data signals Da 1 , Da 2 , Da 3  and is fed to the A/D convertor 72 to be transformed into the corresponding 10-bit digital data signal. Again the digital data signals from the A/D convertor 72 are stored in the high and low byte storage locations 74H and 74L as shown in FIG. 3. In a sixth block 110, the control signal S 1  is transmitted along the control bus 56c and the strobe line 74a to the strobe terminal of high byte storage location 74H of register 74. Then, the eight most significant bits of the digital data corresponding to the analogue signal Da 2  are read out and transmitted to the RAM 54B to be again stored. The control signal S 2  for the low byte storage location 74L of register 74 is not generated in this block 110, and therefore the two least significant bits of the digital data are eliminated. In a seventh block 112, the control signal for selecting the analogue data signal Da 3  is transmitted along the control bus 56c and the section lines 70a and 70b to the select terminals of multiplexer 70. Then, the analogue data signal Da 3  is selected among the analogue data signals Da 1 , Da 2 , Da 3  and is fed to the A/D convertor 70 to be transformed into the corresponding 10-bit digital data signals. The digital data signals from the A/D convertor 72 are stored in the high and low byte storage locations 74H and 74L. In a eighth block 114, the control signal S 1  is transmitted along the control bus 56c and the strobe line 74a to the strobe terminal of high byte storage location 74H of register 74. Then, the eight most significant bits of the digital data corresponding the analogue signal Da 3  are read out and transmitted to the RAM 54B to be again stored. The control signal S 2  for the low byte storage location 74L of register 74 is not generated in this block 114, and therefore the two least significant bits of the digital data are eliminated. The processes in the blocks 100 to 114 are performed repeatedly in that order, so that the process in the block 100 is started after the process in the block 114 is finished. The digital data signals, corresponding to the analogue signals Da 1 , Da 2 , and Da 3 , stored in the RAM 54B are again read out to determine the desired values of the pulse width of the control signal Dc 1  and the ignition timing in the block 100. 
     Since the analogue data signal Da 1  indicative of the air flow rate has a relatively large dynamic range, the signal Da 1  needs to be transformed into relatively high bit-number, for example 10, digital form and then processed with the same bit-number maintained to avoid impairment of accuracy. On the other hand, since the analogue data signals Da 2  and Da 3  indicative of the engine coolant temperature and the power source voltage respectively have respective relatively small dynamic ranges, it is sufficient for the signals Da 2  and Da 3  to be transformed into relatively low bit-number, for example 8, digital form and then processed with the same bit-number maintained to avoid impairment of accuracy. In fact, after transformation into the corresponding 10-bit digital forms, the digital data corresponding to the analogue signal Da 1  are processed with the bit-number, 10, maintained while the digital data corresponding to the analogue signals Da 2  and Da 3  are processed as 8 bit data after reduction from 10 to 8 in bit-number. Therefore, the accuracies of analogue signals Da 1 , Da 2 , and Da 3  are maintained at acceptable levels during process to determine the amount of fuel injected and the ignition timing. Meanwhile, the digital data corresponding to the analogue signals Da 2  or Da 3  are read out by only a one step operation in the blocks 110 or 114, so that the calculation process can be simple and the operation time can be short as compared to the prior art system of FIG. 1. 
     It should be understood that further modifications and variations may be made in the present invention without departing from the spirit and scope of the present invention as set forth in the appended claims. For example, the sensor 32 or 34 may be designed so as to detect another engine operating condition, such as temperature of engine intake air, temperature of engine exhaust, or air excessive percentage of intake air-fuel mixture, and the control system may be designed so as to control the engine in response to the foregoing detected and other engine operating condition.