Abstract:
A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the step of providing a semiconductor wafer including a dielectric layer formed on the wafer. The dielectric layer has vias formed therein. The wafer is placed in a deposition chamber wherein the wafer has a first temperature achieved without preheating. A metal is deposited on the wafer which fills the vias wherein the metal depositing is initiated at a substantially same time as heating the wafer from the first temperature.

Description:
BACKGROUND  
         [0001]    1. Technical Field  
           [0002]    This disclosure relates to semiconductor fabrication and more particularly, to a deposition process for forming metal lines which improves reliability and electrical performance.  
           [0003]    2. Description of the Related Art  
           [0004]    Semiconductor devices, such as semiconductor memories, processors, application specific integrated circuits and the like, include layers of conductive lines used to interconnect components on the devices. Conductive or metal lines are often formed on upper levels of a semiconductor device. These metal lines are typically connected by contacts through vias to underlying devices or other metal lines.  
           [0005]    In a conventional method, an Aluminum (Al) metal line deposition includes a two step process. This process is characterized by a cold-hot process. This process is extremely slow having a throughput of only about 22 wafers per hour for a two physical vapor deposition Al chamber mainframe. The process includes two depositions (cold and hot). The first (cold) deposition suffers from the disadvantage of running unchucked. This means that there is no possibility to check whether the wafer is sitting correctly on a chuck which secures the wafer in a processing chamber. If the wafer is not placed correctly on the chuck, the chuck could get deposited on and ruined. This is disadvantageous since an electrostatic chuck can cost about $80,000.  
           [0006]    Another problem with the conventional method is the heat up time needed in between the two Al depositions. After the cold Al deposition, the wafer is heated. During that time, a thin Al 3 O 2  layer may be formed on the previously deposited Al. This decreases via filling properties.  
           [0007]    The cold-hot process sequence may be employed as a so-called sprint approach. This means that a via has to get filled and concurrently a planar Al film has to get deposited. The planar Al film is then etched for structuring metal lines.  
           [0008]    The requirements for the Al deposition include the following:  
           [0009]    1. vias formed in a dielectric (oxide) layer which are typically tapered must get filled reliably;  
           [0010]    2. a planar (low topography) Al film must be formed on top of the dielectric layer; and  
           [0011]    3. a temperature budget for semiconductor processing must be maintained (i.e., little or no influence on sub lying metal lines). To achieve this, the two step Al deposition process was developed. The two step process begins with a cold step which uses high sputter power and runs at low temperatures. This ensures that the vias are getting filled (i.e., small Al grains and no overhangs at the top edge of the vias), and that no voids are formed. Before the second (hot) Al deposition step starts, the wafer temperature gets increased up to 350° C. This second Al deposition process runs at low power to ensure that the Al film gets planarized during deposition. This Al deposition sequence is not a reflow process. Reflow processes typically run at much higher temperatures and were developed for filling more aggressive (higher aspect ratio) via structures. The hot Al deposition process deposition therefore has to fulfill different requirements and is optimized for tapered via fill and planar Al deposition on top of a dielectric layer, as described.  
           [0012]    As mentioned above, the conventional two-step deposition process is very slow (e.g., a 192 second process time, and 11/22 wafers/hour for a one/two chamber system). Due to the relatively long Al deposition time of 192 seconds, a small amount of TiAl 3  forms which increases contact resistance and decreases the electromigration lifetime.  
           [0013]    Therefore, a need exists for a deposition process which increases throughput without sacrificing performance and reliability.  
         SUMMARY OF THE INVENTION  
         [0014]    A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the step of providing a semiconductor wafer including a dielectric layer formed on the wafer. The dielectric layer has vias formed therein. The wafer is placed in a deposition chamber wherein the wafer has a first temperature achieved without preheating. A metal is deposited on the wafer which fills the vias wherein the metal depositing is initiated at a substantially same time as heating the wafer from the first temperature.  
           [0015]    Another method for depositing metal lines for semiconductor devices includes the steps of providing a semiconductor wafer including a dielectric layer formed on the wafer, the dielectric layer having vias formed therein, placing the wafer in a deposition chamber by securing the wafer to a thermal surface by employing chucks which ensure a position of the wafer, the wafer being at a first temperature achieved without preheating. The step of simultaneously depositing a metal on the wafer while heating the wafer above the first temperature wherein the metal depositing is initiated at a substantially same time as the heating of the wafer is also included. The chucks may include electrostatic chucks.  
           [0016]    In alternate methods, the metal may include Aluminum, Tungsten, Gold and/or Copper. The step of determining a position of the wafer at the substantially same time as the depositing may be included. The step of placing the wafer in a deposition chamber may include the step of securing the wafer with chucks prior to initiating the depositing step. The step of placing the wafer in a deposition chamber may include the step of placing the wafer on a thermal surface for heating. The substantially same time preferably includes a window of less than 15 seconds between heating the wafer and depositing the metal. The method may include the step of etching the metal on a surface of the wafer to form metal lines. The first temperature may be between about room temperature to about 150 degrees Celsius.  
           [0017]    These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0018]    This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:  
         [0019]    [0019]FIG. 1 is a flow diagram showing a method for forming metal lines and contacts in accordance with the present invention;  
         [0020]    [0020]FIG. 2 is a schematic diagram showing a processing chamber for use in accordance with the present invention;  
         [0021]    [0021]FIG. 3 is a partial cross-sectional view of a wafer showing vias formed in a dielectric layer for deposition of a metal in accordance with the present invention;  
         [0022]    [0022]FIG. 4 is a partial cross-sectional view of the wafer of FIG. 3 showing the vias filled with a metal deposited in a single deposition process in accordance with the present invention; and  
         [0023]    [0023]FIG. 5 is a partial cross-sectional view of the wafer of FIG. 4 showing the metal patterned on a top surface of the wafer in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0024]    The present invention provides an improved metal deposition process for semiconductor devices. The present invention reduces preheat time for a semiconductor wafer prior to depositing metal thereon. In this way, the wafer has metal which is initially deposited on a relatively cold surface. This provides a smaller grain size and better nucleation. The reduced or eliminated preheat step further provides better metal coverage, for example, in via holes, since nucleation is improved. Since the metal coverage is improved, improvements in electrical characteristics and reliability are also achieved.  
         [0025]    The time for the preheat step for a semiconductor wafer is typically used to determine proper positioning of the wafer. However, by chucking the wafer prior to depositing metal thereon, wafer position may be determined without expending a lot of time prior to initiating the deposition process. The present invention is preferably employed using a one step deposition process as described, in a commonly assigned disclosure, U.S. application Ser. No. (TBD) (Attorney Docket Number: 98E9170), entitled IMPROVED METAL LINE DEPOSITION PROCESS, filed concurrently herewith, and incorporated herein by reference. The present invention may also be employed with conventional cold-hot deposition processes. The present invention provides many advantages over the prior art. Some of these advantages include the following:  
         [0026]    1) High throughput (shorter process times, which result in a higher throughput); and  
         [0027]    2) Wafer detection is provided since the wafer is chucked before the deposition begins.  
         [0028]    These benefits are accompanied with improved electrical results, such as reduced contact resistance and even improved reliability results.  
         [0029]    Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 1, an illustrative method for forming metal lines in accordance with the present invention is shown. In block  10 , a processing chamber is provided. As shown in FIG. 2, a processing chamber  100  may be a standard processing chamber such as an Endura 5500 model available commercially from Applied Materials, Inc. or an INOVA available commercially from Novellus, Inc. Other models may be employed as well. Chamber  100  includes a thermal surface  102  employed to alter the temperature of a wafer  104  installed thereon. Thermal surface  102  may include a chuck  106  for securing wafer  104  thereon. Chuck  106  may include an electrostatic chuck (ESC) or a clamp.  
         [0030]    Chuck  106  preferably works in conjunction with a positioning system  108 . Positioning system  108  provides information about the position of wafer  104 . Chamber  100  includes other components employed for physical vapor deposition processes, for example gas supplies and valves, temperature and pressure controls and instruments, process timing devices, etc. In one embodiment, thermal surface  102  includes a temperature controller  110  which permits a thermal gradient of thermal surface to be programmed or set in accordance with a desired thermal profile. For example, in one embodiment, thermal surface  102  is maintained at a constant temperature (e.g., about 350 degrees Celsius). In another embodiment, thermal surface  102  is programmed to increase its temperature over a given period of time at a given gradient. For example, the gradient could be a linear gradient, an exponential gradient or any other relationship which can be programmed into temperature controller  110 .  
         [0031]    In block  12  of FIG. 1, a wafer to be processed is chucked (in chucks  106 , see FIG. 2) in preparation for processing. In a preferred embodiment, the chucks include electrostatic chucks, or other types of chucks which can provide a nearly immediate determination of the wafer position. In this way, a determination of the correct position of the wafer in the chamber may be made without expending a significant amount of time. Preferably the determination is made in less than 15 seconds after placement in the chamber in contact with a thermal surface, and more preferably between about 0 to about 5 seconds. Block  12  is preferably performed simultaneously with blocks  14  and  16 . It is noted that the present invention is preferably employed in a single processing chamber so that handling the wafer is reduced.  
         [0032]    In block  14 , the wafer is brought into contact with a thermal surface or the thermal surface is activated to begin heating the wafer, i.e., heating is initiated. The wafer at the start is preferably at about room temperature to about 150 degrees Celsius, preferably closer to room temperature. In block  16 , deposition of the metal is begun immediately upon the initiation of heating the wafer, that is, upon contact (or activation) with the heating surface. In a preferred embodiment, deposition begins from between about 0 to about 15 seconds after the initial heating is begun, and preferably closer to 0 seconds. These times and temperatures may be adjusted according to the deposition process and metal to be deposited, the wafer used and the design of the semiconductor device.  
         [0033]    In the prior art, the wafer would go unchucked during an initial cold deposition. However, as described for the present invention, the wafer is chucked from the onset obviating the concern of damaging the chucks due to deposition of sputtered metal. The depositing step and the initiation of heating are preferably performed simultaneously.  
         [0034]    In block  16 , a physical vapor deposition (PVD) process is initiated. In a preferred embodiment, the PVD process includes sputtering in a one step method as described in Application Serial No. (TBD) (Attorney Docket Number: 98E9170), entitled IMPROVED METAL LINE DEPOSITION PROCESS, previously incorporated by reference. The PVD process may include the deposition of metals, such as Aluminum (Al), Tungsten (W), Copper (Cu), Gold (Au), or other metals. For simplicity, the present invention will illustratively be described for depositing Al metal lines on a semiconductor wafer.  
         [0035]    Advantageously in accordance with the present invention, a seed layer deposition (small grain size, good nucleation) begins to form instantly as deposition begins. As the wafer begins to heat up (in accordance with a constant heating temperature of thermal surface or by a temperature gradient on thermal surface) and eventually reaches a set point (or target) temperature, for example, about 350 degrees Celsius, deposition of the metal continues forming contacts and a metal layer on top of a dielectric layer. Preferably, the contacts and metal lines are formed concurrently. As the temperature, increases warmer metal continues to be deposited on top of the smaller grain-sized metal deposited earlier. The warmer metal deposition advantageously provides improved planarization properties.  
         [0036]    In block  18 , the later (warmer) deposited metal can be planarized and etched to form metal lines on the surface of the dielectric layer, and contacts are formed in vias in or through the dielectric layer. A conventional two step deposition process can also benefit from the methods of the present invention.  
         [0037]    For a one step Al deposition process, the deposition process needs between about 70 seconds to about 110 seconds in deposition time to form metal lines and contacts concurrently. This is a significant reduction over the conventional deposition process which requires over 190 seconds to complete. Further, with the reduction or elimination in preheat time, an additional 10 to 25 seconds per wafer may be achieved. With the reduced processing times throughput is accordingly increased.  
         [0038]    Referring to FIG. 3, a semiconductor wafer  201  is shown for processing in accordance with a one step metal deposition process. Wafer  201  may include a semiconductor memory chip, such as a dynamic random access memory (DRAM), static random access memory (SRAM), a read only memory (ROM), embedded DRAM/SRAM, or the like. Wafer  201  may also include a processor chip, or an application specific integrated circuit (ASIC) chip, etc. A target layer  200  may include a conductive component or underlying metal line or layer. Alternately, Target layer  200  may include a target conductor  203 , such as a substrate, for example, a semiconductor substrate, having diffusion regions formed therein or a conductive layer or conductive line formed thereon. A dielectric layer  202  is formed on target layer  200 . Dielectric layer  202  may include an oxide, a nitride, an organic layer, such as a resist or polyamide, or other suitable dielectric materials. Dielectric layer  202  is patterned to form trenches  204 . Trenches  204  may include contact holes or vias  206  and/or conductive line openings. Other structures may be formed in accordance with the present invention. For example, conductive lines may be formed in trenches in dielectric layer  202 . In a preferred method vias  206  are formed in trenches  204  while metal lines are formed on the surface of dielectric layer  202 . Vias  206  expose portions of the underlying conductive materials of target layer  200 .  
         [0039]    Referring to FIG. 4, wafer  201  is placed in a PVD chamber in accordance with the present invention. A position of the wafer is assessed, if needed. Preferably, the wafer position is ensured upon placement in the processing chamber, for example, by employing electrostatic chucks. A metal  210  is deposited in vias  206  and on dielectric layer  202  by preferably employing a one step process. A metal liner  207  may be deposited prior to metal  210  deposition. For example, liner  207  may include Ti/TiN, Ta, W or other materials. Deposition is begun as early as possible upon mounting wafer  201  on a thermal surface in the chamber. Wafer  201  is gradually heated from a “cold” temperature to a “hot” temperature during the deposition process. In accordance with one aspect of the present invention, the temperature of thermal surface  102  (FIG. 2) is adjusted (e.g., by changing the temperature of the thermal surface) to achieve optimal results for the given deposition process. During the heating process, metal  210  is deposited in trenches  204  (which may include vias  206  or other structures). Metal  210  is continuously deposited until open trenches  204  are filled and metal  210  covers top surfaces of dielectric layer  202 .  
         [0040]    Referring to FIG. 5, metal  210  formed on the top surfaces of dielectric layer  202  is etched to form metal lines  214 . A planarization process may be employed prior to etching to provide a better metal surface for later processing. Contacts  212  and metal lines  214  are now provided in accordance with the present invention.  
         [0041]    In accordance with the present invention, contact resistances for structures formed in FIG. 5 provided about a 10% improvement over the prior art. Further, chain currents provided about a 5% improvement over the prior art.  
         [0042]    Having described preferred embodiments for heat-up time reduction before metal deposition (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.