Abstract:
A repair circuit having a repair controller which is capable of reducing unnecessary current dissipation by interrupting a control operation to redundant cells that are unused for replacement of defective cells is presented. The repair circuit includes a repair controller and a repair signal generator. The repair controller is configured to generate a first drive voltage, a second drive voltage and a repair control signal depending on whether or not a defective cell exists. The repair signal generator driven by the first and second drive voltages in which the repair signal generator is configured to generate a repair signal, for repairing the defective cell, in response to receiving the repair control signal and an external address.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2009-0070760, filed on Jul. 31, 2009, in the Korean Intellectual Property Office, which is incorporated by reference in its entirety as set forth in full. 
       BACKGROUND 
       [0002]    An embodiment of the present invention relates to a repair circuit including a repair controller for reducing current dissipation. 
         [0003]    Semiconductor memories are additionally equipped with spare memory cells (hereinafter referred to as “redundancy cells” or “redundant cells”) for replacing defective memory cells, which are incapable of operating in normal conditions due to defects in memory cell arrays, for the purpose of enhancing product yields thereof. Establishing the number of the redundant cells highly affects yields of semiconductor memories. For instance, a semiconductor memory chip having redundant cells larger than defective cells is disadvantageous to integration density because the redundant cells necessarily cause the chip size to increase. To the contrary, semiconductor memory chips having redundant cells smaller than defective cells are abolished as inferior products, which degrade the product yield. Therefore, evaluating the number of redundant cells in a reasonable degree is important in designing a semiconductor memory. 
         [0004]    In a semiconductor memory having a sufficient number of redundant cells, the redundant cells are partly unused for replacing defective cells. Although that, since the redundant cells unused for replacing defective cells are put into a control operation of repair, there would be unnecessary current dissipation. Such current dissipation induces power noise to cause malfunctions in the semiconductor memory. 
       SUMMARY 
       [0005]    There is provided a repair circuit having a repair controller capable of reducing unnecessary current dissipation by interrupting a control operation to redundant cells that are unused for replacing defective cells. 
         [0006]    In accordance with an aspect of the present invention, there is provided a repair controller comprising a fuse coupled between a first node and a second node from which a voltage control signal is output; a voltage driver configured to actuate a drive voltage in response to the voltage control signal; and a control signal generator configured to latch a signal of the second node in response to the drive voltage and configured to generate a repair control signal to control a repair operation for a defective cell. 
         [0007]    In accordance with an another aspect of the present invention, there is provided a repair circuit comprising a repair controller configured to generate a first drive voltage, a second drive voltage and a repair control signal depending on whether a defective cell occurs; and a repair signal generator driven by the first and second drive voltages and configured to generate a repair signal, which is used in repairing the defective cell, in response to receiving the repair control signal and a row address. 
         [0008]    A further understanding of the nature and advantages of the present invention herein may be realized by reference to the remaining portions of the specification and the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0010]      FIG. 1  is a block diagram illustrating a functional configuration of a repair circuit according to an embodiment of the present invention; 
           [0011]      FIG. 2  is a circuit diagram illustrating the repair controller included in the repair circuit shown in  FIG. 1 ; 
           [0012]      FIG. 3  is a circuit diagram illustrating the first compared signal generator included in the repair circuit shown in  FIG. 1 ; and 
           [0013]      FIG. 4  is a circuit diagram illustrating the compared signal detector included in the repair circuit shown in  FIG. 1 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0014]    Hereinafter, various exemplary embodiments will now be described more fully with reference to the accompanying drawings in which some exemplary embodiments are shown. However, specific structural and functional details disclosed herein are merely representative for purposes of describing exemplary embodiments of the present invention. Like numbers refer to like elements throughout the description of the drawings. 
         [0015]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. 
         [0016]    Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Also will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
         [0017]    In order to more specifically describe exemplary embodiments, various aspects will be hereinafter described in detail with reference to the attached drawings. 
         [0018]      FIG. 1  illustrates a functional block configuration of a repair circuit according to an embodiment of the present invention. Referring to  FIG. 1 , the repair circuit may be comprised of a repair controller  1  and a repair signal generator  2 . The repair signal generator  2  may be composed of a compared signal generator  3  and a compared signal detector  4 . The compared signal generator  3  is exemplarily formed of first through eleventh compared signal generation units  3 &lt;1:11&gt;. 
         [0019]    Referring to  FIG. 2 , the repair controller  1  may be composed of a voltage driver  10 , a fuse F 10  and a control signal generator  11 . 
         [0020]    The voltage driver  10  is exemplarily formed of P-type metal-oxide-semiconductor (PMOS) transistors P 10  and P 11 . The PMOS transistor P 10  is coupled between a terminal of an internal voltage V PERI  and a node nd 10  from which a first drive voltage V PL  is output, and functions as pull-up element to pull up a voltage level of the node nd 10  in response to a power-up signal PWRUP. The PMOS transistor P 11  is coupled between the internal voltage terminal V PERI  and a node nd 12  from which a second drive voltage V DR  is output, and functions as a pull-up element that pulls up a voltage level of the node nd 12  in response to a voltage control signal DRV. The power-up signal PWRUP rises up along a level of the power voltage during a period when the power voltage is supplied into a semiconductor memory apparatus and an initial operation begins (hereinafter, referred to as a “power-up period”) and goes down to a low level state after the power-up period terminates. 
         [0021]    The fuse F 10  is coupled between the node nd 10  and the node nd 11  from which the voltage control signal DRV is output. Cutting off the fuse F 10  depends on whether there is a defective cell in a memory cell array that has been completed in fabrication. In this embodiment, the fuse F 10  is designed to be cut off when there is a defective cell corresponding thereto. 
         [0022]    The control signal generator  11  may be formed of an N-type metal-oxide-semiconductor (NMOS) transistor N 10  and a latch circuit  110 . The NMOS transistor N 10  is coupled between the node nd 10  and the node nd 11  and functions as a switch element that turns on in response to the power-up signal PWRUP. The latch circuit  110  generates a repair control signal FET by buffering a signal of the node nd 11  in supply with the second drive voltage V DR  and holds the signal of the node nd 11 . The latch circuit  110  is exemplarily formed of an inverter IV 10  and an NMOS transistor N 11 . The inverter IV 10  functions as a buffer to output the repair control signal FET to a node nd 13  by inversely buffering the signal of the node nd 11 . The NMOS transistor N 11  functions as a pull-down element that pulls down a voltage level of the node nd 11  in response to a signal of the node nd 13 . The repair control signal FET is activated to a high level state for controlling a repair operation when there is a defective cell in the memory cell array. 
         [0023]    With this configuration, the repair controller  1  supplies the first drive voltage V PL , which is driven in a high level state by the internal voltage V PERI , when the PMOS transistor P 10  is turned on after the power-up period terminates. During this, the repair controller  1  operates to control activations of the second drive voltage V DR  and the repair control signal FET depending on whether there is a defective cell, which will be described in detail hereinafter. 
         [0024]    First, in case that there is a defective cell, the fuse F 10  is cut off (or blown out) to hold the node nd 11  on a low level state that is set in the power-up period. Then, the second drive voltage V DR  rises up to a high level state through the PMOS transistor P 11  that is turned on. The inverter IV 10  generates the repair control signal FET in a low level state by supply of the second drive voltage V DR . 
         [0025]    In the other case, when there is no defective cell, the fuse F 10  is not cut off to drive the voltage control signal DRV up to a high level state. The voltage control signal DRV of a high level state stops driving the PMOS transistor P 11  and the inverter IV 10 , so the second drive voltage V DR  and the repair control signal FET are generated in low level states. 
         [0026]    Now referring to  FIG. 3 , the first compared signal generation unit  3 &lt;1&gt;, representatively, may be composed of a selection signal generator  30  and a selective transmitter  31 . 
         [0027]    The selection signal generator  30  may be formed of a fuse F 30 , an NMOS transistor N 30  and a buffer circuit  300 . The fuse F 30  is coupled between a node nd 30  into which the first drive voltage V PS  is supplied, and a node nd 31 . The NMOS transistor N 30  is coupled between the node nd 31  and a terminal of the ground voltage Vss and functions as a pull-down element that pulls down a voltage level of the node nd 31  in response to the power-up signal PWRUP. The buffer circuit  300  is driven by the second drive voltage V DR  and outputs a first selection signal SEL&lt;1&gt; to a node nd 32  by buffering a signal of the node nd 31 . The buffer circuit  300  is exemplarily formed of an inverter IV 30  and an NMOS transistor N 31 . The inverter IV 30  is driven to output the first selection signal SEL&lt;1&gt; by inversely buffering the signal of the node nd 31  when the second drive voltage V DR  is input thereto in the state of a high level. The NMOS transistor N 31  functions as a pull-down element for pulling down a voltage level of the node nd 31 . The fuse F 30  is cut off depending on a first row address signal RXA&lt;1&gt; that corresponds to a defective cell. In this embodiment, the connection through the fuse F 30  is sustained when the first row address signal RXA&lt;1&gt; corresponding to the defective cell is set on a high level state. The fuse F 30  is cut off when the first row address signal RXA&lt;1&gt; corresponding to the defective cell is set on a low level state. Thus, the selection signal generator  30  output the first selection signal SEL&lt;1&gt; in a low level state when the first row address signal RXA&lt;1&gt; corresponding to the defective cell is set on a high level state. But, when the first row address signal RXA&lt;1&gt; corresponding to the defective cell is set on a low level state, then the selection signal generator  30  outputs the first selection signal SEL&lt;1&gt; in a high level state. 
         [0028]    The selective transmitter  31  is exemplarily formed of a gate ND 30 , an inverter IV 31  and an inverter IV 32 . The gate ND 30  receives the first row address signal RXA&lt;1&gt; and the repair control signal FET. The gate ND 30  is driven by the second drive voltage V DR  that is on a high level state. The gate ND 30  functions as a buffer to process the first row address signal RXA&lt;1&gt; in response to the repair control signal FET. The inverter IV 31  is driven by the second drive voltage V DR  of a high level state such that the inverter IV 31  functions as a transmission element for inversely buffering the first row address signal RXA&lt;1&gt; in response to the first selection signal SEL&lt;1&gt;. The inverter IV 31  transfers the inverted first row address signal RXA&lt;1&gt; as a first compared signal MAT&lt;1&gt;. The inverter IV 32  is driven by the second drive voltage V DR  of a high level state and functions as a transmission element for inversely buffering an output signal of the gate ND 30  in response to the first selection signal SEL&lt;1&gt;. The inverter IV 32  transfers the inverted output signal of the gate ND 30  as the first compared signal MAT&lt;1&gt;. With this configuration, the selective transmitter  31  generates the compared signal MAT&lt;1&gt; in a high level state when the first row address signal RXA&lt;1&gt; is conditioned in a level state corresponding to a defective cell. Otherwise, the compared signal MAT&lt;1&gt; is generated in a low level state from the selective transmitter  31  when the first row address signal RXA&lt;1&gt; is out of a logical level corresponding to a defective cell. 
         [0029]    The second through eleventh compared signal generation units  3 &lt;2:11&gt; included in the compared signal generator  3  are substantially similar to the first compared signal generation unit  3 &lt;1&gt;, except that the second through eleventh row address signals RXA&lt;2:11&gt; are input respectively thereto instead of inputting the first row address signal RXA&lt;1&gt; and except that the second through eleventh compared signals MAT&lt;2:11&gt; are input respectively thereto instead of inputting the first compared signal MAT&lt;1&gt;. Thus, the second through eleventh compared signal generation units  3 &lt;2:11&gt; will not be further detailed later. 
         [0030]    With this configuration, when there is an input of the first through eleventh row address signals RXA&lt;1:11&gt; that corresponds to a defective cell, then the compared signal generator  3  generates the first through eleventh compared signals MAT&lt;1:11&gt; that are all activated on high level states. In further detail, the first through eleventh compared signal generation units  3 &lt;1:11&gt; include fuses, respectively, which are cut off depending on a result of testing defective cells. For instance, when a row address of a defective cell is ‘10001000111’, the fuses belonging to the first through third compared signal generation units  3 &lt;1:3&gt;, the seventh compared signal generation unit  3 &lt;7&gt; and the eleventh compared signal generation unit  3 &lt;11&gt; are kept connected while the fuses corresponding to the fourth through sixth compared signal generation units  3 &lt;4:6&gt; and the eighth through tenth compared signal generation units  3 &lt;8:10&gt; are cut off. Therefore, the first through third compared signal generation units  3 &lt;1:3&gt;, the seventh compared signal generation unit  3 &lt;7&gt; and the eleventh compared signal generation unit  3 &lt;11&gt; generate the first through third compared signals MAT&lt;1:3&gt;, the seventh compared signal MAT&lt;7&gt; and the eleventh compared signal MAT&lt;11&gt; in the same levels with the row address signals RXA&lt;1:3&gt;, RXA&lt;7&gt; and RXA&lt;11&gt;, respectively. In contrast, the fourth through sixth compared signal generation units  3 &lt;4:6&gt; and the eighth through tenth compared signal generation units  3 &lt;8:10&gt; respectively generate the fourth through sixth compared signals MAT&lt;4:6&gt; and the eighth through tens compared signals MAT&lt;8:10&gt; in inverted levels of the row address signals RXA&lt;4:6&gt; and RXA&lt;8:10&gt; input thereto. 
         [0031]    Referring to  FIG. 4 , the compared signal detector  4  may be composed of a logical element  40 , a logical element  41 , a logical element  42  and a gate ND 43 . The logical element  40  outputs a signal S 40  by conducting an AND operation with the first through fourth compared signals MAT&lt;1:4&gt;. The logical element  41  outputs a signal S 41  by conducting an AND operation with the fifth through eighth compared signals MAT&lt;5:8&gt;. The logical element  42  outputs a signal S 42  by conducting an AND operation with the ninth through eleventh compared signals MAT&lt;9:11&gt;. The gate ND 43  outputs a repair signal /HIT from the signals S 40 , S 41  and S 42 . With this configuration, the compared signal detector  4  generates the repair signal /HIT by detecting voltage levels of the first through eleventh compared signals MAT&lt;1:11&gt; in response to the repair control signal FET. The repair signal /HIT is activated in a low level state for replacing a defective cell with a redundant cell. The repair signal /HIT is generated in a high level state from the compared signal detector  4  when the repair control signal FET is set on a low level state. To the contrary, the repair signal /HIT is generated in a low level state from the compared signal detector  4  when the repair control signal FET and the first and eleventh compared signals MAT&lt;1:11&gt; are all set on high level states. 
         [0032]    Now hereinafter will be described an operation of the repair circuit in conjunction with  FIGS. 1 through 4 . 
         [0033]    First, corresponding to the case that there is a defective cell in the memory cell array, the fuse F 10  included in the repair controller  1  is preliminarily set in the cutoff state and the fuses belonging respectively to the first through eleventh compared signal generation units  3 &lt;1:11&gt; are also preliminarily set to be each controllable (to be cut off or not) by the row address signals RXA&lt;1:11&gt;. In the repair circuit, during the power-up period, a signal of the node nd 11  is initialized at a low level state by the NMOS transistor N 10  that is turned on in response to the power-up signal PWRUP of a high level state. After the power-up period, the PMOS transistor P 10  turned on in response to the power-up signal PWRUP of the high level state operate to supply the first drive voltage V PL , which is activated in a high level state, into the node nd 10 . As the fuse F 10  has been already set in the cutoff state, the signal of the node nd 11  is substantially maintained on the low level state that has been initialized during the power-up period. Thus, the PMOS transistor P 11  is turned on in response to the voltage control signal DRV of a low level state which is output from the node nd 11  and then the second drive voltage V DR  is supplied into the node nd 12  in a high level state. Accordingly, the latch circuit  110  of the control signal generator  11  is driven by a supply of the second drive voltage V DR  at a high level state and the latch circuit  110  generates the repair control signal FET that is activated in a high level state. Also the compared signal generator  3  is driven by a supply with the second drive voltage V DR  and generates the first through eleventh compared signals MAT&lt;1:11&gt; that are all activated in high level states when there is an input of the first through eleventh row address signals RXA&lt;1:11&gt; corresponding to a defective cell. During this, the compared signal detector  4  generates the repair signal /HIT in response to receiving the repair control signal FET at a high level state and the first through eleventh compared signals MAT&lt;1:11&gt; at high level states, and then the defective cell is replaced with a redundant cell in response to the repair signal /HIT at the low level state. 
         [0034]    On the other hand, corresponding to the situation where there is no defective cell in the memory cell array, the fuse F 10  of the repair controller  1  is preliminarily set to be in connection. Under this condition of the repair circuit, a signal of the node nd 11  is initialized at a low level state by the NMOS transistor N 10  in response to the power-up signal PWRUP that is set at a high level state. After the power-up period, the repair controller  1  supplies the first drive voltage V PL  at a high level state into the node nd 10  through the PMOS transistor P 10 , which is turned on, in response to the power-up signal PWRUP at a low level state. During this, as the fuse F 11  is set to be in connection, the node nd 11  is driven up to a high level state. Thus, the voltage control signal DRV of a high level state output from the node nd 11  turns the PMOS transistor P 11  on to interrupt power to the second drive voltage V DR , so that the second drive voltage V DR  drops to a low level state. As the second drive voltage V DR  goes down to the low level state, driving the buffer circuit  110  of the control signal generator  11  is stopped and then the repair control signal FET is generated at a low level state. Further, the compared signal generator  3  is not further driven to disable the generation of the first through eleventh compared signals MAT&lt;1:11&gt;. During this, as the compared signal detector  4  generates the repair signal /HIT at a high level state in response to the repair control signal FET at a low level state, the repair operation for replacing a defective cell is disabled. 
         [0035]    As aforementioned, the repair circuit according to this exemplary embodiment is able to interrupt the second drive voltage V DR  at a high level state to the control signal generator  11  and the compared signal generator  3 , by using the voltage control signal DRV at a high level state that is output from the node nd 12  coupled with the fuse F 10 , by setting the fuse F 10  in connection when there is no defective cell in the memory cell array. Thus, the control signal generator  11  and the compared signal generator  3  actuated by the second drive voltage V DR  of the high level state are stopped to be driven when a defective cell does not occur. As a result, the repair circuit according to exemplary embodiments is effective in reducing unnecessary current dissipation because a control operation to redundant cell, which is unused for replacing a defective cell, is disabled by interrupting the supply of the drive voltage for driving the control operation of the redundant cell. 
         [0036]    The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in exemplary embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims.