Abstract:
A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the memory space to different memory ranks. First, the distributive rule of the data is defined. Next, the data is distributed to the memory ranks that the data belongs to according to the rule. Then, the data is physically accessed in one of the memory ranks.

Description:
RELATED APPLICATIONS  
       [0001]     The present application is based on, and claims priority from, Taiwan Application Serial Number 93133093, filed on Oct. 29, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety.  
       BACKGROUND  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to a method for accessing a memory system. More particularly, the present invention relates to an access method used to enhance the throughput by interleaving a multi-rank memory system.  
         [0004]     2. Description of Related Art  
         [0005]     Generally, data access systems nowadays include a memory unit, and some of the memory units are designed as multi-rank for expanding the memory space in the future. These memory ranks share the same single system bus.  
         [0006]     A memory page is a basic unit of a memory access. A memory page should be activated before reading operation, and then a reading command is asserted to the memory after passing some clock cycles. After the memory received the command, the memory waits for a span of time then the desired data can be accessed, where the span of time is so-called latency. It spends many clock cycles between activating a memory page and accessing the data. If the next desired data is in the same memory page with the present accessed data, time of activating memory page can be saved; furthermore, the pipeline schedule can be fully utilized for enhancing the efficiency of the system bus. In contrast, if the next desired data is not in the same memory page with the present accessed data, the activated memory page should be firstly pre-charged and then the another memory page allocating to the next desired data is activated. After spending lots of clock cycles for asserting the accessing command and after waiting for the latency, then the data is ready to be accessed. However, the data bus is idle during those clock cycles and latency, as a result, the data access system is inefficient.  
         [0007]      FIG. 1  shows the condition described above. The access cycle  102  is total clock duration for accessing the first data. As shown in  FIG. 1 , when accessing a first data, the system spends two clock cycles for activating a page, and spends three clock cycles and two clock cycles respectively for waiting latency and accessing the data after asserting a data accessing command. Assuming the following second data which needs to be accessed after the first data is in the different memory page with the first data, the memory page allocating to the first data is pre-charged and the another memory page allocating to the second data is activated. Similarly, an access cycle  104  identical with the access cycle  102  is spent for accessing the second data. In this example, the system spends total nine clock cycles for accessing the second data, and most of the time is spent on the activating and pre-charging.  
       SUMMARY  
       [0008]     The present invention provides a memory interleaving method in a memory unit with multi-rank.  
         [0009]     The present invention provides a data accessing method for enhancing data accessing efficiency.  
         [0010]     The present invention provides a data accessing method used in a memory unit of a general data access system. In the invention, a continuous data with a continuous logical address is configured to different memory ranks.  
         [0011]     A memory space configuring method in the present invention includes: dividing a data to a plurality of blocks, each block has corresponding logical address. Then, configuring the blocks in turn to each of the memory ranks, wherein the continuous blocks with continuous logical addresses are configured to the different memory ranks The following description of an embodiment comprises a method for forming an interleaving control code and distributing the continuous data. Both the distribution and the size of distributed data block have many variations, so they can be adjusted to adapt to the practical requirements and are not to be limited by the embodiment. After the processes for decoding the interleaving control code and the logical address code, a physical location can be obtained and then the desired data can be accessed.  
         [0012]     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:  
         [0014]      FIG. 1  is a timing diagram showing the clock cycles spent for accessing memory by a conventional method;  
         [0015]      FIG. 2  is a block diagram of a data access system;  
         [0016]      FIG. 3A  is a distribution diagram of the memory blocks according to an embodiment of the present invention;  
         [0017]      FIG. 3B  is a distribution diagram of the memory blocks according to an embodiment of the present invention; and  
         [0018]      FIG. 4  is a flow chart of the method in accordance with an embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0020]     In accordance with the conventional data storing method, the continuous data (e.g. program codes of the same application program) are generally stored into a continuous memory location. That is to say, even if the memory unit comprises many memory ranks, these continuous data may very likely be stored into the same memory rank. Thus, an accessible data quantity in a continuous access operation is limited by the size of the memory page in a memory rank. If a desired data quantity in the access operation is exceeding the memory page size, the utility rate of the data bus will be widely degraded due to the frequently pre-charging of the old memory page and activating the new memory page.  
         [0021]      FIG. 2  shows a block diagram of a data access system, wherein a central processing unit  202  sends a request to a memory control unit  206  via a system bus  204  for data accessing. After the memory control unit receives the request, the data will be readout from or written into a physical location of a memory unit  208  according to a logical address signal transmitted from the central processing unit  202 . Therefore, the memory control unit  206  is able to map a logical address to a physical address of the memory.  
         [0022]     This embodiment assumes that a memory system formed by the memory control unit  206  and the memory unit  208  is a Synchronous DRAM (SDRAM) module or a Double Data Rate (DDR) SDRAM module. A memory rank of a SDRAM module is formed by a plurality of memory banks, and each memory bank can activate one memory page at one time. Size of one memory page may be 4 KB to 32 KB depending on the characteristic of the memory unit. If a memory rank has four memory banks and size of a memory page is 32 KB, there is 128 KB data that can be simultaneously activated at most. That is to say, if two memory ranks can be access at one time, there has 256 KB data that can be simultaneously activated, and so on.  
         [0023]     This embodiment assumes that the memory unit  208  has four memory ranks namely memory rank  212 - 218 .  
         [0024]     Assuming the memory size of the memory rank  212  is 256 MB, the memory rank  214  is blank, and the memory size of both the memory rank  216  and memory rank  218  are 128 MB. That is to say, the total memory size of the memory unit  208  for data accessing is 512 MB. Therefore, the system uses 29 bits {A 28 ,A 27 , . . . ,A 1 ,A 0 } for addressing the logical address.  
         [0025]     In general, the memory addresses are assigned by a linear distribution in the conventional memory address mapping method. In this embodiment, memory space of memory rank  212  is addressed from logical address 0 MB to logical address 256 MB; memory space of memory rank  216  is address from logical address 256 MB to logical address 384 MB; and memory space of memory rank  212  is addressed from logical address 384 MB to logical address 512 MB  
         [0026]     Assuming bits {A 28 , A 27 } of logical address can be used to determine which one of memory rank is mapped. If a data which bits {A 28 , A 27 } of logical address is {0, 0} or {0, 1}, thus, the data is mapped to the memory rank  212 . If a data which bits {A 28 , A 27 } of logical address is {1, 0}, thus, the data is mapped to the memory rank  216 . And if a data which bits {A 28 , A 27 } of logical address is {1, 1}, thus the data is mapped to the memory rank  218 . Besides, bits {A 26 , A 25 , . . . ,A 1 ,A 0 } of logical address is used to determine the physical location of the mapped memory rank.  
         [0027]     For example, an application program needs to occupy 64 MB memory space herein, thus a continuous logical address will be allocated for the application program. At that time, if the logical address of the application program is directly mapped to a physical address, the 64 MB application program will very likely be stored into one of memory rank  212 , memory rank  216  or memory rank  218 . Thus, only 128 KB of memory pages is activated by the application program at one time, and then the access efficiency of the memory unit is degraded.  
         [0028]     In the present invention, the application program with 64 MB memory size is divided and respectively allocated to the memory rank  212 , memory rank  216  and memory rank  218 , therefore size of memory page accessing at one time is increase.  
         [0029]     In this embodiment, the data is equally allocated to the memory rank  212 , memory rank  216  and memory rank  218 ; therefore, at least two bits of logical address is used to being as an interleaving control code for determining the objective memory rank between the three memory ranks  212 ,  216  and  218 .  
         [0030]     The bits {A 18 , A 17 } of logical address of each data is regarded as the interleaving control code herein. Nevertheless, an interleaving control code may be formed by any bits of the logical address in practice, and it is not limited by this embodiment. This embodiment assumes that if a data with bits {A 18 ,A 17 } equals to {0,0} or {0,1} is mapped to the memory rank  212 ; if a data with bits {A 18 ,A 17 } equals to {1,0} is mapped to the memory rank  216 ; and if a data with bits {A 18 ,A 17 } equals to {1,1} is mapped to the memory rank  218 .  
         [0031]      FIG. 3A  shows a memory space configuration method of the present invention. A 512 MB memory space  302  is divided 4096 blocks, wherein each block is 128 KB (assuming that there are four memory banks in per memory rank, and each of the memory banks is able to activate a memory page of 32 KB at one time.) The block  0001  to the block  0004  are allocates to memory rank  212 , memory rank  216 , memory rank  212  and memory rank  218  in turn. Also, the rest blocks are sequentially allocated to each memory banks in the same manner. Consequently, the continuous data block with continuous logical address will not be allocated to identical memory rank.  
         [0032]     After determining the objective memory rank, physical address of the data in the objective memory rank can be figured out by decoding the logical address of the data. Because the bits {A 18 , A 17 } are used as the interleaving control code, in the embodiment, using higher order bits such as bits {A 28 ,A 27 } to replace the bits {A 18 ,A 17 }. That is to say, the physical address of the data in the objective memory rank to can be obtained by decoding logical address {A 25 ,A 24 , . . . ,A 19 ,A 28 ,A 27 , A 16 , . . . ,A 1 ,A 0 }. Finally, the data can be accessed at the physical address in the objective memory rank.  
         [0033]      FIG. 3B  shows another embodiment according to the present invention. The only difference between the examples shown in  FIG. 3A  and  FIG. 3B  is that the memory size of the memory rank  212  is  128 MB and the memory size of the memory rank  214  is also 128 MB.  
         [0034]     In this embodiment, logical address 0M to 256 MB of the memory space  304  is shared by the memory rank  212  and memory rank  214  forming a memory group X; and logical address 256M to 512 MB of the memory space  304  is shared by the memory rank  216  and memory rank  218  forming a memory group Y.  
         [0035]     Assuming bit {A 17 } of the logical address is selected to be the interleaving control code of the memory group X. That is, if a data with bit {A 17 } equals to {0} will be mapped to the memory rank  212 ; and if a data with bit {Al  7 } equals to { 1  } will be mapped to the memory rank  214 . Assuming bit {A 18 } of the logical address is selected to be the interleaving control code of the memory group Y. If a data with bit {A 18 } equals to {0} will be mapped to the memory rank  216 ; and if a data with bit {A 18 } equals to {1} will be mapped to the memory rank  218 . Thus, the configuration of the memory space  304  with 512 MB is shown in  FIG. 3B .  
         [0036]     In which, blocks  0001  to  2048  are equally configured to the memory rank  212  and memory rank  214  in turn at first, and then blocks  2049  to  3072  are equally configured to the memory rank  216  and memory rank  218  in turn. Assuming memory size of each block  0001  to the block  2048  is 128 KB, and the memory size of each block  2049  to the block  3072  is 256 KB. Finally, the substitutive logical address can be formed by respectively replacing bit {A 17 } in the memory group X and bit {A 18 } in the memory group Y with bit {A 28 } to obtain the physical address.  
         [0037]     According to the foregoing description, the numbers of the interleaving level and grouping of the present invention can be programable.  
         [0038]      FIG. 4  shows a flow chart of the method in accordance with the present invention. In step  402 , objective memory rank of a data is defined by a logical address with a plurality of bits, wherein the number of bits of the logical address is determined by the memory size. In step  404 , the data is divided to a plurality of blocks, and each block has a corresponding logical address. In step  406 , a part of bits of the logical address are regarded as interleaving control code, and all the blocks are distributed to each memory rank according to their interleaving control codes respectively. The bit numbers of the interleaving control code is according to block size. In step  408 , the interleaving control code is replaced by the higher order bits in the logical address. In step  410 , a physical address of the block in the memory rank can be obtained by decoding the replaced logical address.  
         [0039]     In the present invention, bits of interleaving control code can be random selected and is not limited to the adjacent bits.  
         [0040]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.