Abstract:
A technique for operating a source follower buffer circuit, such as employed in a charge domain pipeline, to eliminate floating diffusion signal charge contamination from downstream circuits. The method and apparatus places an output of the circuit in a known state immediately prior to charge transfer into a floating diffusion, and again in known state immediately prior to charge transfer out of the floating diffusion.

Description:
RELATED APPLICATION(S) 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/005,773, filed on Dec. 7, 2007. The entire teachings of the above application(s) are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    In charge domain pipeline circuits, such as used in Analog to Digital Converters (ADCs) and other applications, signal charge is transferred from a sending capacitive net to a pre-charged receiving capacitive net using a charge transfer device. These capacitive nets are typically implemented as floating diffusions. Transfer of a signal charge into a capacitive net causes the voltage on the capacitive net to drop from a pre-charged voltage by an amount proportional to the amount of charge. 
         [0003]    In order to measure the size of the signal charge, as needed for the purpose of comparing it to another charge packet on an opposing floating diffusion of a differential design, it is necessary to either amplify or buffer the change in voltage. This is normally done by connecting the Floating Diffusion (FD) to the gate of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which acts as an input device to a buffer circuit. 
         [0004]    After the change in voltage has been measured, the received charge packet is sent to the next receiving floating diffusion in the pipeline. This charge packet should be completely transferred without losing any charge to the gate of the buffer/amplifier input device. Unfortunately, this is difficult due to the charging of the parasitic capacitance of these input devices with some of the signal charge. Opposite sides of these parasitic capacitors are connected to internal nets of the amplifier/buffer circuitry and, thus the amount of coupling from these nets back onto the floating diffusion is un-deterministic. 
       SUMMARY OF THE INVENTION 
       [0005]    In a preferred embodiment, a charge packet present in a floating diffusion charge pipeline is sensed by a Source Follower Buffer (SFB) circuit. The SFB circuit is placed in a known state just prior to charge transfer onto a floating diffusion and is returned a known state just prior to transfer of a charge off of the floating diffusion. 
         [0006]    The known state in the SFB circuit may be imposed by using a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) controlled by a clock signal. In one embodiment, the clock signal is arrange to hold the output of the SFB circuit in a known high state prior to charge transfer onto the floating diffusion, released while charge is transferred onto the floating diffusion, and then held in a high state again prior to and during charge transfer off of the floating diffusion. Such an arrangement not only provides the desired states for the MOSFET, but also places it in a deep depletion mode to minimize its capacitance contribution to the net. 
         [0007]    In still further alternate embodiments, a current source may improve current flow while the MOSFET is pulling the output of the SFB circuit to the known state. 
         [0008]    By holding the floating diffusion in an initial state during a pre-charge mode (e.g., just after pre-charge and prior to charge transfer), releasing it during a charge transfer in mode, but then returning it to the same initial state prior to charge transfer out of the floating diffusion, one can reduce and/or eliminate the influence of follow on circuits on the amount of charge transferred out of the floating diffusion. 
         [0009]    Furthermore, by providing a switch coupled to the current source, one can reduce the total power consumption as well. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0010]    The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention. 
           [0011]      FIG. 1  is a high level block diagram of a charge pipeline circuit. 
           [0012]      FIG. 2  is a circuit diagram of a Source Follower Buffer (SFB) circuit. 
           [0013]      FIGS. 3 and 4  are timing diagrams for the circuit of  FIG. 2 . 
           [0014]      FIG. 5  is a block diagram of a digital radio receiver that may utilize the SFB circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    A description of example embodiments of the invention follows. 
         [0016]      FIG. 1  is a high level block diagram of a charge pipeline circuit. The specific circuit shown is an Analog to Digital converter (ADC) function comprised of a number of stages  10 - 1 ,  10 - 2 , . . . An example stage  10 - 1  consists of a floating diffusion represented by capacitor  100  (Cfd), a charge transfer input circuit  102 , a floating diffusion (FD) pre-charge circuit  103 , and a charge output circuit  114 . In operation, the pre-charge circuit  103  sets an initial state (voltage) for diffusion  100 . An input signal charge (QT) is then fed to the floating diffusion  100  by input circuit  102 . A clock signal generator  12  provides the various signals necessary to operate the stages  10  such as an input transfer signal (TR) that controls input circuit  102 , a pre-charge signal (PRE) that controls precharge  103 , and other signals. 
         [0017]    Introduction of this charge to the floating diffusion causes the voltage thereon to change. In order to implement an application circuit such as an analog to digital converter, the amount of voltage on the floating diffusion  100  must be measured and compared to one or more reference voltages. For this purpose, a buffer circuit  104  such as may be a Source Follower Buffer (SFB) senses charge on floating diffusion  100  and feeds it to an ADC stage  108 . The n-bit ADC stage  108  may be composed of a 1 bit, 1½ bit, 2 bits or more providing a number of output bits,  2   n . ADC stage  108  typically consists of a number of reference voltages and comparators to provide demultiplexed output bits. For example, if the ADC stage  108  is a 2-bit converter, then there are 4 outputs. A parasitic capacitance represented by Ccouple  110  feeds change back from ADC  108  to SFB  104 . 
         [0018]    The 2 n  outputs from ADC stage  108  are then fed to corresponding ones of charge redistribution capacitors  112 - 1 ,  112 - 2   n  (Cqr 1 , . . . Cqr 2   n ). These capacitors collectively provide an amount of charge to be reintroduced to the pipeline, which is then fed to the input of the differential amplifier  114 , producing the output charge from stage  10 - 1 . 
         [0019]      FIG. 2  shows the Source Follower Buffer (SFB) circuit  104  and its interaction with elements of the stage  10 - 1  in more detail. Carried forward from  FIG. 1  are the capacitance  100  representing floating diffusion  120  (FD) with an input charge provided by input current source I QT . Output amplifier  114  is generally represented as providing the output charge Q T  to the next floating diffusion in the floating diffusion network. The pre-charge amplifier provided by M PRE  provides pre-charging of the floating diffusion  120 . 
         [0020]    The source follower buffer (SFB) circuit  104  is shown to more particularly include an N-channel device (M SF ), a load represented by current source  142  (i load ), and P-channel device (M CTRL ). The P channel device is controlled by the LOOK signal which is generated by the clock signal generator previously referenced. 
         [0021]    Here, Cdg  146  and Cgs  148  parasitics are also shown. The Cgs parasitic capacitances include both channel and overlap capacitance. An additional capacitor  110  (Ccouple), represents coupling from follow on circuitry. Such coupling circuitry may, for example, be a cross-coupled latch that can kick back and contaminate the signal charge on the floating diffusion  120  (FD). 
         [0022]    Referring to the timing diagram of  FIG. 3 , the floating diffusion voltage (Vfd) sequence is as follows: 
         [0023]    by t 1 , the pre-charge FET  103  (MPRE) pulls the FD  120  to Vdd; 
         [0024]    at t 2 , the pre-charge FET  103  (MPRE) turns off resulting in a positive going feedthrough; 
         [0025]    during i QT , a signal charge packet (e.g. Qt) is transferred onto the FD  120  causing its voltage to drop by an amount proportional to the size of the packet; 
         [0026]    by t 3 , charge transfer is complete; 
         [0027]    at t 4 , a voltage disturbance on the other side of Ccouple  110  has coupled back onto the FD; and 
         [0028]    at t 5 , the signal charge is transferred out of the FD  120  using the QT block  114  which extracts charge by bringing Vfd to a fixed Vfdss level. 
         [0029]    The dashed horizontal line  330  in  FIG. 3  shows how Vfd would behave with the SFB  104  removed; the other trace  340  shows the effect of SFB  104 . The difference between these two traces illustrate the effects of the parasitic capacitors of the SFB  104 . The change (delta Vfd) is due the load capacitance presented to the FD  120  by the buffer  104 . The longer time constant “droop” after the signal charge has been dumped onto the FD  120  is due to the slow settling of the SFB  104  output coupling back to the FD  120  through Cgs  148 . The output of the SFB, Vfdbuf, is seen to follow the FD  120  with a limited bandwidth. 
         [0030]    Interferer noise, Vnoise, also couples onto Vfd through Ccouple  110  and Cgs  148 . If the effect of Vnoise has not settled adequately before charge transfer off of the FD  120 , an error in the amount of signal charge transferred results. 
         [0031]    In a preferred embodiments, the invention controls the output of the SFB  104  by putting it in a known state at two points in time; just prior to charge transfer onto the FD  120  and just prior to charge transfer off of the FD  120 . By holding the FD  120  in an initial state during pre-charge, just after pre-charge and prior to charge transfer, and then returning it to that same initial state prior to transfer of charge out of FD  120  eliminates the influence of follow-on circuit net voltage changes on the amount of charge transferred from the FD  120 . 
         [0032]    With reference to  FIG. 4  and the implementation illustrated in  FIG. 2 , the P-channel device Mctrl is clocked by LOOK so that the output of the SFB  104  is held high prior to charge transfer onto the FD  120 , released while charge is transferred onto the FD  120 , and then held high again prior and during charge transfer off of the FD  120 . This has the added benefit that the Msf  140  inversion channel is eliminated, reducing the capacitance of the floating diffusion, reducing kTC noise. 
         [0033]    In preferred embodiments, the current source  142  load is controlled with the switch  148  in synchronization with Mctrl. By also switching off the current source  142  in this state, one can reduce overall power consumption. The current source  142  may be implemented as an active current source or also may be a resistor. 
         [0034]    The LOOK signal bus controls the operation of the source follower buffer circuit. In particular, the LOOK signal ensure that the output of the SFB  104  is held until a point in time, t a , that occurs between times t 1  and t 2 . It is then released the floating diffusion until time, t b , that occurs between times t 4  and t 5  when the output of the SFB  104  will again return to a known state. 
         [0035]    One particular use of the SFB  104  is to implement a digital radio receiver as generally shown in  FIG. 5 . A radio frequency (RF) signal is fed to a radio frequency RF amplifier  504 . In a wireless application, the RF signal may be received from an antenna  502 ; in other applications it may be received via a wire. The amplified RF signal is then fed to an RF translator  506  to down-convert the amplified RF signal to an intermediate frequency (IF). After the RF translator  506  (which may be optional) the ADC  510  is then used to digitize the RF input into digital samples for subsequent processing. A digital local oscillator  511  may operate digital mixers  512 -i and  512 -q to provide for in phase and quadrature samples thereof. A digital low pass filter  520  limits the frequency content of resulting signal to the desired bandwidth. A demodulator  530  then recovers the original modulated signal from the same using. One or more of the operations of the digital local oscillator  511 , mixers  512 , low pass filter  520  and/or demodulator  530  may be implemented in a digital signal processor  550 . The recovered signal may then be further processed converted back to an analog baseband signal or the like, depending on the specific end application of the digital receiver. 
         [0036]    While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.