Abstract:
Increasing the number of MOSFET gate bump contacts makes MOSFET gate contacts more durable and reliable. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads overlying the source pad metallization reduces the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. The result is a reliable, durable MOSFET gate contact.

Description:
FIELD OF INVENTION 
     This invention relates to semiconductor fabrication, and more specifically to power MOSFET contact fabrication. 
     Definitions 
     BCB: benzocyclobutene, an insulating polymer widely used as a photosensitive patterning material and insulator. 
     RDSon: the on-state drain-to-source resistance in a MOSFET. 
     UBM: under-bump metal, the conductive metal used to connect a source or gate contact to an external circuit via a surface solder bump. 
     DISCUSSION OF PRIOR ART 
     MOSFET die layouts are designed to maximize the source contact area for optimum RDSon performance. This approach leaves just enough area for the gate pad to establish one wirebonding connection or bump connection. With the increasing trend toward wireless packaging via wafer bumping and flipchip technologies, a single gate bump contact serves the purpose. A disadvantage of single gate bump contact designs is that mechanical and thermal stress experienced by this single gate bump contact can cause disconnection. Inherent in multilayer metal stack technology, as commonly used in MOSFET contact areas, is the frequent problem of delamination of such metallization from its underlying dielectric layer due to differences between the coefficients of thermal expansion of the metallization and the dielectric when the stack is subjected to thermal stress. Such delamination of the metallization renders the parent device inoperable and unusable. Increasing the gate contact area in an attempt to guarantee robustness does not help, since the resulting contact still constitutes only a single connection. 
     SUMMARY 
     By increasing the number of MOSFET gate pads, the invention makes MOSFET gate connections more durable and reliable. The invention extends under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads not overlying the gate pad metallization, thereby minimizing the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. The gate pads use source pad space adjacent to the original gate contact. The invention&#39;s use of more than one gate pad further reduces such failure risks. The result is a reliable, durable MOSFET gate contact compatible with current assembly methods. 
    
    
     DESCRIPTION OF DRAWINGS 
     FIG. 1 shows a cross section of the invention&#39;s gate bump and source bump structure. 
     FIG. 2 shows a cutaway view of the invention&#39;s gate bump structure. 
     FIG. 3 shows a plan view of the invention&#39;s gate and source bump layout. 
     FIG. 4 shows a plan view of an alternate first embodiment of the invention&#39;s gate and source bump layout. 
     FIG. 5 shows a plan view of another alternate first embodiment of the invention&#39;s gate and source bump layout. 
     FIG. 6 shows a cross section of a second embodiment of the invention&#39;s gate bump and source bump structure. 
     FIG. 7 shows a cutaway view of the second embodiment of the invention&#39;s gate bump structure. 
     FIGS. 8-25 show the fabrication steps for the invention. 
     FIGS. 26-34 show alternate fabrication steps for the second embodiment of the invention. 
    
    
     A legend for all figures is shown on the drawing sheet with FIG.  26 . 
     DETAILED DESCRIPTION OF INVENTION 
     This invention details a practical approach of creating more gate contacts on a MOSFET die. The invention&#39;s approach resembles the redistribution or routing techniques used in ball grid array (BGA) chips, in which the contact opening of a pad is relocated to another position in substrate layout design. The present invention creates dual or multiple gate pads for a single gate contact. For bumped gate pads, the stress is therefore distributed among the pads, so that the stress experienced by one connection is equal to the total stress divided by the number of connections (i.e., for a dual connection, stress is divided by 2; for a triple connection, stress is divided by 3). The strength of the entire gate connection is multiplied twice if it uses a dual gate contact, or three times if it uses a triple gate contact. This approach sharply reduces the mechanical stress introduced during assembly processing. 
     In a first embodiment, the invention adds one or more gate bump contacts by reallocating source bump contact locations to use as gate bump contacts. The added gate bump contacts provide both multiple electrical gate connections and multiple gate lead frame support points, at the cost of the loss of a few source bump contacts. 
     See FIG. 1, which shows a gate bump  10  and additional gate bumps  11 ,  12  connecting a gate contact  51  with package control gate connection  5 , via gate bump contacts  54 ,  54   a . FIG. 1 also shows one of a number of source bumps  13 , connecting a source metallization  60 , source contact  61 , and source under bump metal  63 ,  63   a  with package source connection  6 , via source bump contacts  64 . The invention fabricates gate bump  10  directly over gate metallization  50 , gate contact  51 , and gate under bump metal  53 ,  53   a , to make external gate bump contact  54  with package control gate connection  5 . The invention also extends under bump metal  52  laterally over source metallization  60 , source passivation layer  65 , and insulating layer  40  to connect gate contact  51  to additional gate bump contacts  11  and  12 , and thus to additional gate bump contacts  54   a  over source metallization  60 . Added gate bumps  11  and  12  furnish added mechanical support for the package control gate connections, thereby reducing the stress per gate contact and the consequent risk of gate contact failure. 
     A cutaway view of the first embodiment of the invention appears in FIG.  2 . This figure shows, from the bottom up, wafer  7 , gate metallization  50 , gate passivation layer  55 , gate contact  51 , first insulating layer  40 , gate under bump metal  52 , second insulating layer  90  (in dotted form, to show underlying layers), gate under bump metal  53 , gate bumps  10  and  11 , gate bump contacts  54  and  54   a , and package control gate connection  5 . In this figure the extension of first insulating layer  40  over source passivation layer  65  insulates gate bump  11  from source metallization  60 . 
     FIG. 3 shows a plan view of the invention&#39;s gate bump contacts. For clarity of essentials, the insulating layers are not shown in this view. Gate contact  51  connects to gate bump contact  54  for gate bump  10  and gate bump contacts  54   a  for gate bumps  11 ,  12  via under bump metal  52 ,  53 , to make contact with package control gate connection  5 . FIG. 4 shows a plan view of an alternate first embodiment of the invention using gate bumps  10   a  and  10   b  in addition to gate bumps  10 ,  11  and  12 , to provide gate contact support in two dimensions. FIG. Y 1   d  shows a plan view of another alternate first embodiment of the invention using gate bumps  10 ,  10   a ,  11 ,  11   a  to provide gate contact support in two dimensions. 
     In a second embodiment, the invention eliminates the multilayer metal from atop the gate contact by laterally offsetting the gate bump contact and multi-metal layers from the gate contact region. This embodiment avoids multi-metal stacking on top of the gate metallization. 
     See FIG. 6, which shows two gate bumps  11 ,  12  connecting a gate contact  51  with package control gate connection  5 , via gate bump contacts  54   a . As in FIG. 1, FIG. 6 also shows one of a number of source bumps  13 , connecting a source metallization  60 , source contact  61 , and source under bump metal  63  with package source connection  6 , via source bump contacts  64 . The invention fabricates gate under bump metal  52  directly over gate metallization  50  and gate contact  51 , and extends under bump metal  52  laterally over source metallization  60 , source passivation layer  65 , and insulating layer  40  to connect gate contact  51  to gate bump contacts  11  and  12 , and thus to gate bump contacts  54   a  over source metallization  60 . Gate bumps  11  and  12  furnish added mechanical support for the package control gate connections, thereby reducing the stress per gate contact and the consequent risk of gate contact failure. Since no gate bump is fabricated directly over multiple metal layers  50 ,  51 ,  52 , and  53  in this embodiment, the risk of delamination of the metallization due to thermal and mechanical stresses in package assembly and operation is minimized. 
     A cutaway view of the second embodiment of the invention appears in FIG.  7 . This figure shows, from the bottom up, wafer  7 , gate metallization  50 , gate passivation layer  55 , gate contact  51 , first insulating layer  40 , gate under bump metal  52 , second insulating layer  90  (in dotted form, to show underlying layers), gate under bump metal  53 , gate bump  11 , gate bump contact  54   a , and package control gate connection  5 . In this figure the extension of first insulating layer  40  over source passivation layer  65  insulates gate bump  11  from source metallization  60 , and there is no gate bump directly over gate contact  51 . Additional gate bumps  54   a  are not shown in this figure, but are present in the invention in alternate embodiments as indicated in FIGS. 3,  4 , and  5 . 
     The invention&#39;s fabrication process is as follows. See FIG. 8. A semiconductor wafer  7  has gate metallization  50  and source metallization  60 , silicon oxide or silicon nitride gate passivation layer  55  and source passivation layer  65 , and gate and source contact passivation openings  56  and  66  respectively already in place. The wafer is cleaned. A first BCB layer  40  is coated and baked on the wafer as shown in FIG.  9 . The BCB is exposed to define the exposed gate contact  51  and source contacts  61 , and then developed (FIG. 10) to expose contacts  51  and  61 . BCB is left in place over additional gate bump areas  59  above source A 1  metallization  60 , to insulate the eventual gate bumps from the source metallization. TiCu  42 , serving as a layer of under bump metal, is then sputtered onto gate contact  51  and source contacts  61  for metallization (FIG.  11 ). TiCu  42  deposited over additional gate bump areas  59  does not contact source Al metallization  60  in areas  59 , and will serve as a gate contact lead for the gate support bumps used to support the gate lead frame contacts physically. A first photoresist coating  80  is added (FIG.  12 ), UV-exposed and developed to protect bump and lead areas  59 ,  69  where TiCu is to be retained (FIG.  13 ). The unprotected Cu and TiCu are etched in areas  89  (FIG.  14 ), and photoresist  80  is stripped off (FIG.  15 ), exposing gate under bump metal  52  and source under bump metal  62 . A second BCB layer  90  is coated and baked on the wafer (FIG.  16 ). This concludes the stages of fabrication common to both the first and second embodiments. 
     For the invention&#39;s first embodiment, second BCB layer  90  is exposed and developed (FIG. 17) to define each gate bump termination, or pad opening,  96  and each source bump termination, or pad opening,  98 . In the first embodiment, a pad opening  96  is fabricated directly over gate contact  51 . Cu is sputtered onto the wafer surface to provide a conductive layer  43  (FIG.  18 ). A second photoresist coating  100  is added onto the sputtered Cu  43  (FIG.  19 ), and is UV-exposed and developed (FIG. 20) to expose gate bump areas  59  and source bump areas  69  of Cu where gate solder bumps and source solder bumps respectively will eventually be placed. Cu  53   a ,  63   a  is plated onto exposed Cu areas  59 ,  69  respectively (FIG. 21) to raise the level of Cu to ensure that enough bulk copper interconnect is retained during subsequent processing and soldering where part of the copper is consumed in the formation of Cu—Sn intermetallics. Gate solder bumps  101  and source solder bumps  121  are plated onto Cu  53   a  and  63   a  respectively (FIG.  22 ), with photoresist  100  supporting the edges of the bumps around each Cu area. Photoresist  100  is stripped (FIG.  23 ), exposing sputtered Cu layer  43 , and sputtered Cu layer  43  is etched (FIG. 24) to define the conductive gate metal  53  and conductive source metal  63  and expose the second BCB layer  90 . The plated solder is reflowed (FIG. 25) to form the final gate solder bumps  101  and source solder bumps  121 . 
     For the invention&#39;s second embodiment, second BCB layer  90  is exposed and developed (FIG. 26) to define each gate bump termnination, or pad opening,  96  and each source bump termination, or pad opening,  98 . In the second embodiment, no gate bump termination is fabricated over gate contact  51 . More than one gate bump termination may be fabricated over the source metallization area as desired. Cu is sputtered onto the wafer surface to provide a conductive layer  43  (FIG.  27 ). A second photoresist coating  100  is added onto the sputtered Cu  43  (FIG.  28 ), and is UV-exposed and developed (FIG. 29) to expose gate bump areas  59  and source bump areas  69  of Cu where gate solder bumps and source solder bumps respectively will eventually be placed. Cu  53   a ,  63   a  is plated onto exposed Cu areas  59 ,  69  respectively (FIG. 30) ensure that there is enough bulk copper interconnect material to survive subsequent processing and soldering that consumes copper to form Cu—Sn intermetallics. Gate solder bumps  101  and source solder bumps  121  are plated onto Cu  53   a  and  63   a  respectively (FIG.  31 ), with photoresist  100  supporting the edges of the bumps around each Cu area. Photoresist  100  is stripped (FIG.  32 ), exposing sputtered Cu layer  43 , and sputtered Cu layer  43  is etched (FIG. 33) to define the conductive gate metal  53  and conductive source metal  63  and expose the second BCB layer  90 . The plated solder is reflowed (FIG. 34) to form the final gate solder bumps  101  and source solder bumps  121 . 
     Conclusion, Ramifications, and Scope of Invention 
     From the above descriptions, figures and narratives, the invention=s advantages in providing reliable, durable, and economical MOSFET gate contacts should be clear. 
     Although the description, operation and illustrative material above contain many specificities, these specificities should not be construed as limiting the scope of the invention but as merely providing illustrations and examples of some of the preferred embodiments of this invention. 
     Thus the scope of the invention should be determined by the appended claims and their legal equivalents, rather than by the examples given above.