Abstract:
A sense amplifier for reading a memory cell, comprising: a read node linked to the memory cell, an active stage connected to the read node and comprising means for supplying a read current on the read node, and a data output linked to a node of the active stage where an electrical voltage representative of the state of conductivity of the memory cell appears. The sense amplifier comprises means for adjusting a voltage appearing on the read node at a value inferior to a value of threshold voltage linked to the manufacturing technique of the sense amplifier. Application in particular to the reading of non-volatile memories of the type EEPROM, FLASH and PCM.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation-in-part of International Patent Application No. PCT/FR2006/001686, filed Jul. 11, 2006, now pending, which application is incorporated herein by reference in its entirety. 
         [0002]    This application claims the benefit under 35 U.S.C. § 119(a) of French Patent Application No. 05 07592, filed Jul. 18, 2005, from which priority was claimed in the International Patent Application No. PCT/FR2006/001686, and which is also incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The present invention relates to a memory cell sense amplifier. 
         [0005]    2. Description of the Related Art 
         [0006]    The present invention more particularly relates to a sense amplifier comprising a read node directly or indirectly linked to a memory cell, an active stage connected to the read node and comprising means for supplying a read current to the read node, and a data output linked to the output of a comparator which compares to a reference voltage the voltage present on a node of the active stage, this voltage being representative of the state of conductivity of the memory cell. 
         [0007]    The present invention particularly, but not exclusively applies to non-volatile memories, like EEPROM and FLASH EEPROM memories, and more particularly to PCM memories (phase change memory). In these memories, each memory cell can take two distinct states, i.e., an erased state and a programmed state. In phase change memories, each memory cell comprises an alloy able for example to take a crystalline state and an amorphous state, passing from one to the other being made by cycles for heating/cooling the alloy, in particular according to the duration of the cycle for cooling or heating. 
         [0008]    Classically, a sense amplifier is used to detect the programmed or erased state of a memory cell of a non-volatile memory, by comparing the value of a current flowing through the memory cell to a reference current. The fact that the memory cell is programmed or erased is rendered indeed by a determined state of conductivity of the memory cell, and corresponds by convention to a determined value of the datum stored by the memory cell, for example 1 for the programmed state and 0 for the erased state. 
         [0009]      FIG. 1  schematically shows a standard architecture of a sense amplifier SA 1  of a non-volatile memory. On this figure and in the description of the present invention, the transistors of the PMOS type are indicated by references beginning with “TP” and the NMOS transistors are indicated by references beginning with “TN”. The sense amplifier SA 1  comprises a control stage CST 1 , a read stage RST 1  comprising a read node Sin, and an output stage OST comprising a data output Sout, these stages being electrically powered by a voltage Vcc. 
         [0010]    The control stage CST 1  comprises transistors TP 1  and TP 2  mounted in series with parallel-connected transistors TN 2  and TN 1 . The transistor TP 1  receives on its source terminal the voltage Vcc, and on its gate terminal a reference voltage Vrefp. The drain terminal of the transistor TP 1  is connected to the source terminal of the transistor TP 2 . A control signal EN 1  is applied to the control gate of the transistors TP 2  and TN 2 . The drain terminal of the transistor TP 2  is connected to the drain terminals of the transistors TN 1  and TN 2  which source terminals are put to the ground. The gate terminal of the transistor TN 1  is connected to the read node Sin. 
         [0011]    The read stage RST 1  comprises two transistors TP 3  and TN 3  mounted in series. The transistor TP 3  receives the voltage Vcc on its source terminal and the voltage Vrefp on its gate terminal. The drain terminal of the transistor TP 3  and the drain terminal of the transistor TN 3  are connected to a node N 1  which is connected to the input of the output stage OST. 
         [0012]    The source terminal of the transistor TN 3  is connected to the read node Sin, on which a voltage Vs called “read voltage” appears. The gate terminal of the transistor TN 3  is connected to a node CH which receives a voltage V(CH) taken from the drain terminal of the transistor TP 2  of the control stage CST 1 . The read stage further comprises a precharge transistor TN 4  mounted in parallel with the transistor TP 3  and which drain terminal receives the voltage Vcc. The gate and the source terminals of the transistor TN 4  are respectively connected to the data output Sout of the sense amplifier SA 1 , and to the node N 1 . 
         [0013]    The output stage OST comprises a comparator CP comprising a positive output receiving the voltage Vrefp and a negative input receiving a voltage V(N 1 ) present on the node N 1 . The output of the comparator which forms the data output Sout of the sense amplifier, is in addition connected to the gate terminal of the transistor TN 4 . 
         [0014]    On  FIG. 1 , the read node Sin is linked to a non-volatile memory cell MC(i,j,k) of a memory array MA (only one memory cell is shown for the sake of simplicity), for example by means of a word column k selection transistor TS(k) and of a bit line BL(j,k). The transistors TS(k) are driven by a column selection signal SEL(k) from a column decoder (not shown). As an example application, the memory cell belongs to an EEPROM memory, and thus comprises a floating gate transistor which source terminal is linked to the ground and which gate terminal receives a read voltage Vr during a read phase. The threshold voltage of the floating gate transistor depends on its programmed or erased state and the read voltage Vr is chosen between the threshold voltage at the programmed state and the threshold voltage at the erased state. Thus, when the read voltage Vr is applied, the floating gate transistor is highly conducting if it is in the programmed state (low threshold voltage), or conversely little conducting, or even blocked if it is in the erased state (high threshold voltage). 
         [0015]    The sense amplifier is inactive when the signal EN 1  is 1 (=Vcc) and the voltage Vrefp is equal to Vcc. The transistor TN 2  is then conducting. The transistor TP 2  is blocked, and the drain terminal of the transistor TN 1  is linked to the ground. Therefore, there is no current flowing through the control stage CST 1 . The transistors TP 1  and TP 3  are blocked and there is no current flowing through the read stage RST 1 . 
         [0016]    The reading of a memory cell MC(i,j,k) is preceded by a phase of address decoding, performed by the column decoder, making it possible to link the bit line BL(j,k) of the memory cell to the read node Sin of the sense amplifier. 
         [0017]    The reading of the memory cell comprises a phase of precharging the bit line BL(j,k), and a phase of reading the datum memorized in the memory cell. The read voltage Vr is applied from the precharge phase to the gate terminal of the floating gate transistor of the memory cell to be read. The sense amplifier SA 1  is first activated by bringing the voltage Vrefp to the value Vcc−Vtp, where Vtp is the threshold voltage of the PMOS transistors. The transistors TP 1  and TP 3  then operate as current generators and respectively supply currents Ib and Ir in their respective stages. 
         [0018]    The precharge phase is started by setting the signal EN 1  to 0. The transistor TN 2  blocks and the transistor TP 2  becomes conducting. The voltage V(CH) on the node CH which is applied to the gate terminal of the transistor TN 3  increases and the latter becomes conducting. The transistors TP 3  and TN 4  are also conducting (the voltage V(Sout) at the data output Sout is at the high level), and a precharge current is supplied to the read node Sin. The transistor TN 4  is used to accelerate the precharge phase and consequently, to diminish the global read time, by supplying a current Ifb which adds to the current Ir supplied by the transistor TP 3 . The precharge current, equal to Ir+Ifb, is used to charge stray capacitances located in the bit line BL(j,k) and to rapidly bring the read voltage Vs to a determined value which is substantially equal to the threshold voltage Vtn of the NMOS transistors. In addition, the limitation of the voltage Vs, performed by the transistor TN 3  allows the floating gate transistor of the memory cell to be protected against a phenomenon called “drain stress”, which is rendered by an involuntary injection of charges into the floating gate causing a parasitic programming of the memory cell. 
         [0019]    When the determined value of the read voltage Vs is reached, the transistor TN 1  becomes conducting. The voltage V(CH) on the node CH decreases and stabilizes at a value such that, on the one hand, the currents in the transistors TP 1  and TN 1  are identical, and on the other hand, the current supplied by the transistor TN 3  to the read node corresponds to the current Ic imposed by the memory cell currently being read. 
         [0020]    At the end of the precharge phase, the voltage V(N 1 ) on the node N 1  is near the voltage Vrefp. There are two possible situations: either the memory cell is programmed and a 1 must be read by the sense amplifier, or the memory cell is erased and 0 must be read. If a 1 must be read, the cell current Ic is superior to the reference current Ir. The voltage V(N 1 ) on the node N 1  remains slightly inferior to the voltage Vrefp. The signal supplied by the comparator CP on the data output Sout of the sense amplifier remains at a level of voltage high enough to maintain the transistor TN 4  in the conducting state. The transistor TN 4  then supplies a current equal to the difference Ic−Ir between the current Ic imposed by the memory cell and the reference current Ir supplied by the transistor TP 3 . 
         [0021]    If a 0 must be read, the current Ic in the memory cell to be read is lower than the reference current Ir. In that case, the voltage V(N 1 ) on the node N 1  increases to a level higher than the voltage Vrefp. The signal on the data output Sout then goes to the low state. 
         [0022]    It turns out that this type of detection circuit has a limitation due to the fact that the voltage Vs on the read node Sin, which corresponds to the voltage of the bit line BL(j,k), must be forced to a value slightly superior to the threshold voltage Vtn (typically ranging from 0.8 V to 1 V), because of a slight over-voltage required by the transistor TN 1  to supply the current Ib. However, in certain applications, the bit line must be biased to a level lower than this threshold voltage to reduce the constraints caused by the current Ic flowing through the memory cell, which could damage data integrity. 
         [0023]    In particular, in PCM memories, the current Ic flowing through a memory cell during a read phase should be limited so as to reduce the heating of the memory cell, and thus avoid undesirable thermal effects that may particularly cause the recrystallization of the phase change material from its amorphous state, and thus a corruption of memorized data. 
         [0024]    To reduce the read voltage Vs applied to the read node, the threshold voltage Vtn may be reduced. However, this voltage constitutes a technological parameter of the NMOS transistors of the sense amplifier. In fact, this parameter is linked to the manufacturing technique used to make the amplifier, and is substantially invariant for a given manufacturing technique. 
       BRIEF SUMMARY OF THE INVENTION 
       [0025]    One embodiment of the present invention provides a sense amplifier used to control the voltage applied to the bit line without being limited by the threshold voltage Vtn. 
         [0026]    One embodiment of the present invention is a sense amplifier for reading a memory cell, made with MOS transistors having a threshold voltage forming a technological parameter of the sense amplifier, and comprising: 
         [0027]    a read node linked to the memory cell, 
         [0028]    an active stage connected to the read node and comprising means for supplying a read current on the read node, and 
         [0029]    a data output linked to a node of the active stage where an electric voltage appears, which is representative of the state of conductivity of the memory cell. 
         [0030]    The sense amplifier also comprises means for maintaining a voltage appearing on the read node at a value inferior to the threshold voltage. 
         [0031]    According to one embodiment of the invention, the means for maintaining the voltage of the read node at a value inferior to the threshold comprise: 
         [0032]    a first transistor and a second transistor arranged in series in the active stage, the second transistor being linked to the read node, and 
         [0033]    means for applying to the gate terminals of the first and second transistors gate voltages having a controlled potential difference one relative to the other. 
         [0034]    According to one embodiment of the invention, the sense amplifier comprises a control stage biased by a bias current and arranged for applying to the gate terminals of the first and the second transistors gate voltages having a potential difference, one relative to the other, which is determined by a current flowing through a resistance. 
         [0035]    According to one embodiment of the invention, the sense amplifier comprises means for generating the bias current flowing through the resistance, independently from a current flowing through the active stage. 
         [0036]    According to one embodiment of the invention, the means for generating the bias current flowing through the charge comprise a resistor through which the bias current is generated, the voltage Vs applied to the read node complying with the following relationship: 
         [0000]      Vs=Vtn 
         [0000]    where Vtn is the threshold voltage, R 1  is the impedance value of an impedance and R 11  is the value of the resistor of the current generation means. 
         [0037]    According to one embodiment of the invention, the sense amplifier comprises means for limiting the voltage drop in the resistance during a phase of precharging the read node. 
         [0038]    According to one embodiment of the invention, the means for limiting the voltage drop in the resistance comprise a transistor mounted in parallel with the resistance, controlled by the voltage on the read node. 
         [0039]    According to one embodiment of the invention, the resistance comprises at least one element of the group comprising a resistor and a MOS transistor. 
         [0040]    According to one embodiment of the invention, the sense amplifier comprises means for discharging a connection node between the first and the second transistors, and thus avoiding a blocking situation. 
         [0041]    According to one embodiment of the invention, the means for discharging the connection node between the first and the second transistors, comprise a transistor connected between the node and the ground. 
         [0042]    According to one embodiment of the invention, the sense amplifier comprises means for attenuating oscillations appearing in the node. 
         [0043]    According to one embodiment of the invention, the active stage comprises a first current generator linked to the read node through the first and the second transistors, and the control stage comprises a second current generator supplying the bias current flowing through the charge. 
         [0044]    According to one embodiment of the invention, the sense amplifier comprises means for activating the sense amplifier before a phase for precharging the read node. 
         [0045]    According to one embodiment of the invention, the means for activating the sense amplifier before a phase of precharging the read node comprise means for disconnecting the sense amplifier from the read node during the activation of the sense amplifier. 
         [0046]    One embodiment of the invention is a non-volatile memory comprising at least one memory cell. The memory comprises at least one sense amplifier as defined above, for reading the memory cell. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) 
         [0047]    These and other advantages and features of the present invention will be presented in greater detail in the following description of the invention given in relation with, but not limited to the following figures: 
           [0048]      FIG. 1  previously described is the electrical diagram of a standard sense amplifier of a memory cell; 
           [0049]      FIGS. 2 to 6  are electrical diagrams of various embodiments of sense amplifiers of a memory cell, according to the present invention; 
           [0050]      FIG. 7  shows a circuit for generating a control voltage applied to the circuit shown in  FIG. 6 ; and 
           [0051]      FIGS. 8A and 8B  show the aspect of some voltages appearing in the sense amplifier of  FIGS. 2 and 6 , respectively. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0052]      FIG. 2  shows a sense amplifier SA 2  comprising a read stage RST 2  derived from the one of the sense amplifier SA 1  described with reference to  FIG. 1 , and an output stage OST identical to the one of the sense amplifier SA 1 . The elements previously described with reference to  FIG. 1  are indicated with the same references. 
         [0053]    The read stage RST 2  is connected to a read node SIN, and to an input node N 1  of the output stage OST which comprises a data output Sout, these stages being electrically powered by a voltage Vcc. 
         [0054]    As in  FIG. 1 , the read node Sin is linked to a memory cell through a selection transistor controlled by a column decoder, and a bit line (not shown). The memory cell receives a read voltage Vr comprised between a threshold voltage in the programmed state of the memory cell and a threshold voltage in the erased state. The output Sout supplies a signal at high or low level according to the state of conductivity of the memory cell, that is approximately and respectively the voltage Vcc or the ground potential, because they are not pure logic potentials. The output signal is then converted in “pure” CMOS logic levels by an inverter (not shown). 
         [0055]    The read stage RST 2  comprises, like the read stage RST 1 , transistors TP 3  and TN 3  mounted in series, and a transistor TN 4  mounted in parallel with the transistor TP 3 . The voltage Vcc is applied to the drain terminal of the transistor TN 4  and the source terminal of the transistor TP 3  which gate terminal receives the voltage Vrefp. The drain terminals of the transistors TP 3  and TN 3 , and the source terminal of the transistor TN 4  are connected to the input node N 1  of the output stage OST. 
         [0056]    The read stage RST 2  further comprises a transistor TN 5  mounted in series between the transistor TN 3  and the read node Sin, to achieve with the transistor TN 3  a cascode arrangement. The gate terminal of the transistor TN 3  is controlled by a fixed voltage Vref 1 . The source terminal of the transistor TN 3  is connected to the drain terminal of the transistor TN 5  which source terminal is connected to the read node Sin and which gate terminal receives a control voltage EN 2 . The control voltage EN 2  is chosen such that the transistor TN 5  operates like a switch to disconnect the read node Sin of the selection transistor TS(k) ( FIG. 1 ) before the column selection. 
         [0057]    The voltage Vs at the read node Sin is equal to Vref 1 −VTn. It is therefore directly controlled by the voltage Vref 1 , and can thus be lower than the threshold voltage Vtn, if the voltage Vref 1  is fixed at a value inferior to  2 VTn. The transistor TN 5  therefore allows the read voltage Vs to be reduced beyond the limit imposed by the threshold voltage Vtn of the NMOS transistors, determined by the manufacturing technique used. 
         [0058]      FIG. 3  shows another advantageous embodiment of a sense amplifier according to the invention. The elements previously described with reference to  FIGS. 1 and 2  are indicated by the same references. 
         [0059]    The sense amplifier SA 3  shown in  FIG. 3  comprises a control stage CST 3 , a read stage RST 3  and an output stage OST. The output stage is identical to the output stage shown in  FIG. 1  previously described. 
         [0060]    The sense amplifier SA 3  is controlled by an activation signal EN 3 , and comprises a read node Sin for linking the bit line of the memory cell to be read (not shown), and a data output Sout supplying a signal at high or low level according to the state of conductivity of the memory cell. 
         [0061]    The read stage RST 3  comprises the same components, substantially arranged in the same way as in the stage RST 2  previously described. 
         [0062]    The read stage RST 3  comprises a transistor TN 5  arranged in series between the source terminal of the transistor TN 3  (node N 2 ) and the read node Sin. The drain and the source terminals of the transistor TN 5  are respectively connected to the node N 2  and the read node Sin. 
         [0063]    In addition, the gate terminals of the transistors TN 3  and TN 5  are respectively connected to nodes CH and CL of the control stage CST 3 . 
         [0064]    Like the stage CST 1  previously described with reference to  FIG. 1 , the control stage CST 3  comprises transistors TP 1  and TP 2  mounted in series with parallel-connected TN 1  and TN 2 . Thus, the transistor TP 1  receives the voltage Vcc on its source terminal and the voltage Vrefp on its gate terminal. The drain terminal of the transistor TP 1  is connected to the source terminal of the transistor TP 2 . The transistors TP 2  and TN 2  receive an activation signal EN 3  on their gate terminals. The gate terminal of the transistor TN 1  is connected to the node N 2 . 
         [0065]    Advantageously, a resistor R 1  is arranged in series between the drain terminal of the transistor TP 2  (node CH) and the drain terminal of the transistor TN 1  (node CL). The difference of potential between the nodes CH and CL is thus equal to the voltage drop between the terminals of the resistor R 1 . 
         [0066]    The transistors TN 3  and TN 5  of the read stage RST 3  form a cascode arrangement wherein the transistor TN 5  is controlled by a gate voltage equal to the voltage V(CL) on the node CL, which is inferior to the voltage V(CH) on the node CH applied to the gate terminal of the transistor TN 3 . 
         [0067]    The sense amplifier SA 3  is activated by bringing the voltage Vrefp to a value equal to Vcc−Vtp (where Vtp is the threshold voltage of a PMOS transistor), and the precharge phase starts by setting the signal EN 3  to 0. The transistors TP 1  and TP 3  operate like current generators and respectively supply the currents Ib and Ir in their respective stages. As a result, the transistor TN 2  blocks and the transistor TP 2  becomes conducting. The voltage V(CH) at the node CH increases and the transistor TN 3  becomes conducting. 
         [0068]    The transistor TN 4  supplies the main part of the precharge current Ifb (assumed to be high compared to Ir) to the read node Sin. When the read voltage Vs reaches a determined value, the transistor TN 1  becomes conducting. The voltage on the gate terminal of the transistor TN 3  stabilizes. The currents in the transistors TP 1  and TN 1  are identical. 
         [0069]    The operation of the sense amplifier SA 3  is substantially identical to the one of the amplifier SA 1  described with reference to  FIG. 1 . However, the operating point of this circuit is such that the voltage on the source terminal of the transistor TN 3 , which controls the transistor TN 1 , forces it to supply a current equal to the current Ib controlled by the transistor TP 1 . This current flowing through the resistor R 1 , the voltage V(CL) at the node CL can be determined in the following way: 
         [0000]        V ( CL )= V (CH)− Ib×R 1=2  Vtn−Ib×R 1   (1) 
         [0070]    It results that the read voltage Vs at the read node Sin complies with the following relationship: 
         [0000]        Vs=V ( CL )− Vtn=Vtn−Ib×R 1   (2) 
         [0071]    The read voltage Vs is thus reduced compared to the threshold voltage Vtn by a value equal to Ib×R 1 . This reduction can thus be easily controlled by setting either the value of the current Ib, or the value of the resistor R 1 . 
         [0072]    The combination of the control stage CST 3  wherein the resistor R 1  has been added, and the addition of the transistor TN 5  in the read stage RST 3  thus allows the read voltage Vs to be reduced beyond the limit imposed by the threshold voltage Vtn of the NMOS transistors of the sense amplifier. 
         [0073]    Compared to the sense amplifier SA 2 , the voltage Vs at the read node Sin in the sense amplifier SA 3  is less linked to the current Ic, and the precharge phase of the bit line is less long. 
         [0074]      FIG. 4  shows a sense amplifier SA 4  according to another embodiment of the invention. The sense amplifier SA 4  comprises read stages RST 4  and output stages OST identical to those of the sense amplifier SA 3 , and a control stage CST 4  comprising all the components of the control stage CST 3 , substantially arranged in the same way. The control stage CST 4  further comprises an additional transistor TN 6  which gate terminal is controlled by a reference voltage Vrefn equal to Vtn. The source terminal of the transistor TN 6  is put to the ground, and its drain terminal is connected to the connection node N 2  of the transistors TN 3 , TN 5  and TN 1 . 
         [0075]    The transistor TN 6  behaves like a current source, calling to its drain terminal a leakage current Ilk. The effect of this current which adds to the current Ic can be easily compensated by increasing by the same value the current Ir flowing through the transistor TP 2 . 
         [0076]    This arrangement makes it possible to avoid an overshoot wherein the node N 2  cannot discharge. 
         [0077]      FIG. 5  shows a sense amplifier SA 5  according to another embodiment of the invention. The sense amplifier SA 5  comprises a control stage CST 5 , a read stage RST 5  and an output stage OST, the latter being identical to the one of the amplifier described with reference to  FIG. 1 . The stages CST 5  and RST 5  comprise all the components of the stages CST 4  and RST 4  of the sense amplifier SA 4 , substantially arranged in the same way. The control stage CST 5  further comprises an additional transistor TP 4  mounted in parallel with the resistor R 1 . The gate terminal of the transistor TP 4  is connected to the read node Sin, and is linked to the ground through a transistor TN 7 . The gate terminal of the transistor TN 7  is controlled by a signal EN 1 , and the drain and the source terminals of this transistor are respectively connected to the read node Sin and to the ground. 
         [0078]    The read stage RST 5  further comprises a capacitor C and an additional transistor TN 8 . The capacitor C is mounted between the node N 2  and the gate terminal of the transistor TN 5  to suppress or attenuate undesired current oscillations. The drain and the source terminals of the transistor TN 8  are respectively connected to the source terminal of the transistor TN 5  (node N 3 ) and to the read node Sin. The gate terminal of the transistor TN 8  is controlled by the signal EN 1  through an inverter INV, so that when the transistor TN 7  is conducting, the transistor TN 8  is blocked, and vice versa. 
         [0079]    By maintaining the signal EN 1  to 1 before the column of the memory array is selected, the transistor TN 8  is blocked and insulates the read node Sin. The column selection transistor TS(k) ( FIG. 1 ) is thus isolated from the rest of the sense amplifier SA 5 , which allows it to be set into its state of operation before the selection of the column of the memory array. When the sense amplifier SA 5  is thus disconnected from the column selection transistor by the transistor TN 8 , the transistor TN 7  is conducting and puts the read node Sin to the ground. 
         [0080]    The sense amplifier SA 5  is therefore activated before an operation of reading a memory cell by setting the signal EN 3  to 0 and the signal EN 1  to 1. In these conditions, no current Ic can flow through the read node Sin, and the voltages internal to the sense amplifier have the following values: 
         [0000]        V (N2)= Vtn  (voltage on the node N 2 ) 
         [0000]        V (N3)= Vtn−Ib×R 1 (voltage on the node N 3 ) 
         [0000]        Vs= 0 
         [0000]        V (N1)= Vcc  (voltage on the node N 1 ) 
         [0000]        V ( Sout )=0 (voltage on the data output Sout) 
         [0081]    As soon as the signal EN 1  goes to 0, a high current flows through the transistors TN 3 , TN 5  and TN 8 , this current being necessary for charging the capacitance of the bit line and the column decoder. The voltage of the nodes N 1 , N 2  and N 3  then rapidly drops. It results that the output signal Sout goes to 1, which renders conducting the transistor TN 4  which supplies the current Ifb necessary for the precharge, and which cannot be supplied by the transistor TP 3  alone. The drop of the voltage V(N 2 ) of the node N 2  triggers the reaction of the feedback circuit which increases the voltage V(CH) at the node CH. The transistor TP 4  which is then conducting, limits the voltage drop in the resistor R 1  during this phase, and thus accelerates the control of the transistor TN 5 , and therefore the charge of the bit line. 
         [0082]    When the read node Sin is charged at the required value, the sense amplifier SA 5  has reached its operating point. The increase of the read voltage Vs which is followed by the drop of the voltage CH, reduces the drain-source voltage of the transistor TP 4  to a value such that the current that flows through it is negligible in relation to the current flowing through the resistor R 1 . The effect of the transistor TP 4  therefore disappears during the reading of the datum. 
         [0083]      FIG. 6  shows a sense amplifier SA 6  according to another embodiment of the invention. The sense amplifier SA 6  comprises a control stage CST 6 , a read stage RST 6  and an output stage OST. These stages are identical to those of the sense amplifier SA 5 , except that in the control stage CST 6 , the gate terminal of the transistor TP 1  is controlled by a voltage Vb distinct from the voltage Vrefp. This arrangement renders the current Ib independent from the current Ir, which allows the voltage drop in the resistor R 1  to be better controlled. 
         [0084]      FIG. 7  shows an electrical circuit VG allowing the voltage Vb to be generated. This circuit comprises a first branch comprising two transistors TP 11  and TP 12  mounted in series. The transistor TP 11  receives the voltage Vcc on its source terminal and the control voltage Vrefp on its gate terminal. The drain terminal of the transistor TP 12  is connected to the drain terminals of two transistors TN 11  and TN 12  mounted in parallel and which source terminals are put to the ground. The gate terminals of the transistors TP 12  and TN 11  are controlled by a signal EN 4 . The circuit VG comprises a second branch comprising a transistor TP 13  mounted in series with a transistor TN 13 . The source terminal of the transistor TP 13  receives the voltage Vcc. The source terminal of the transistor TN 13  is connected to the gate terminal of the transistor TN 12  and is linked to the ground through a resistor R 11 . The gate terminal of the transistor TN 13  is connected to the drain terminal of the transistor TP 12 . The second branch further comprises a transistor TP 14  which source terminal receives the voltage Vcc, which gate terminal is controlled by the signal EN 4  inverted by an inverter INV 11 , and which drain terminal which supplies the voltage Vb is connected to the gate terminal of the transistor TP 13  and to the drain terminals of the transistors TP 13  and TN 13 . 
         [0085]    The circuit VG is activated by setting the signal EN 4  to 0. The signal Vrefp being equal to Vcc−Vtp, the transistors TP 11  and TP 12 , and the transistors TP 13  and TN 13  become conducting, whereas the transistors TN 11  and TP 14  are blocked. The circuit stabilizes at a state of operation such that the voltage Vd at the source terminal of the transistor TN 13  and at the gate terminal of the transistor TN 12  is equal to Vtn. It results that the current Ib flowing through the transistor TN 13  and the resistor R 11  is equal to Vtn/R 11 . With reference to the equation (2), it can be deduced that: 
         [0000]        Vs=Vtn−Ib×R 1= Vtn  (1 −R 1 /R 11)   (3) 
         [0086]    Thanks to these arrangements, the read voltage Vs applied to the bit line BL(j,k) can be easily set by adjusting the ratio R 1 /R 11 . 
         [0087]      FIGS. 8A and 8B  show time variations of voltages respectively present in the amplifiers SA 2  and SA 6 , in the case where the current Ir is lower than the current Ic.  FIG. 8A  shows variations of the voltages Vs, EN 2 , Vref 1 , V(N 1 ) and of the voltage V(Sout) at the data output Sout of the sense amplifier.  FIG. 8B  shows variations of the voltages Vs, EN 2 , V(N 1 ) and V(Sout), and the voltages V(CH) and V(CL) on the nodes CH and CL, respectively. 
         [0088]    In  FIG. 8A , it can be observed that the duration of the charge of the bit line, corresponding to the duration during which the output voltage V(Sout) goes from 5 V to 0 V, is about 80 ns. In  FIG. 8B , this duration is about 40 ns. 
         [0089]    It results from the comparison of these two figures that the feedback circuit of the sense amplifier SA 6  significantly reduces the duration of charge of the bit line, in relation to the solution consisting in biasing the gate terminal of the transistor TN 3  by the fixed voltage Vref 1 . 
         [0090]    It will be clear to those skilled in the art that the present invention is susceptible of various embodiments and applications. In particular, the resistor R 1  of the control stage CST 3 , CST 4 , CST 5  or CST 6  can be replaced by an active component like a transistor which gate terminal is linked to the ground.