Abstract:
The present invention discloses a CNFET double-edge pulse JKL flip-flop, comprising a double-edge pulse signal generator, 31 CNFET tubes, 6 NTI gate circuits having the same circuit structure, 6 PTI gate circuits having the same circuit structure as well as the 1 st  and 2 nd  two-value inverters having the same circuit structure; it features in correct logic functions as well as high-speed and low power consumption.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefit of China application serial no. 201610388691.6, filed on Jun. 3, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
       FIELD OF THE INVENTION 
       [0002]    The present invention is related to a JKL flip-flop, in particular to a CNFET double-edge pulse JKL flip-flop. 
       BACKGROUND ART 
       [0003]    Three-value JKL flip-flop is provided with diversified function, and it is of high significance to design a CNFET double-edge pulse JKL flip-flop featuring in high speed and low power consumption. 
       SUMMARY OF THE INVENTION 
       [0004]    The technical issue to be settled by the present invention is to provide a CNFET double-edge pulse JKL flip-flop featuring in high speed and low power consumption. 
         [0005]    Technical solutions used by the present invention to settle aforesaid technical issue are stated as follows: A CNFET double-edge pulse JKL flip-flop, comprising a double-edge pulse signal generator, the 1 st , 2 nd , 3 rd , 4 th , 5 th , 6 th , 7 th , 8 th , 9 th , 10 th , 11 th , 12 th , 13 th , 14 th , 15 th , 16 th , 17 th , 18 th , 19 th , 20 th , 21 st , 22 nd , 23 rd , 24 th , 25 th , 26 th , 27 th , 28 th , 29 th , 30 th  and 31 st  CNFET tubes, 6 NTI gate circuits of the same circuit structure, 6 PTI gate circuits of the same circuit structure, the 1 st  and 2 nd  three-value inverters of the same circuit structure; the 6 NTI gate circuits comprise the 1 st , 2 nd , 3 rd , 4 th , 5 th  and 6 th  NTI gate circuits; the 6 PTI gate circuits comprise the 1 st , 2 nd , 3 rd , 4 th , 5 th  and 6 th  PTI gate circuits; The 1 st , 11 th , 21 st  and 26 th  CNFET tubes belong to P CNFET tubes; the 2 nd , 3 rd , 4 th , 5 th , 6 th , 7 th , 8 th , 9 th , 10 th , 12 th , 13rd, 14 th , 15 th , 16 th , 17 th , 18 th , 19 th , 20 th , 22 nd , 23 rd , 24 th , 25 th , 27 th , 28 th , 29 th ,  30   th  and 31 st  CNFET tubes belong to N CNFET tubes; source of the 1st, 11th and 21st CNFET tubes is to be accessed to the 1st supply voltage; source of the 26th CNFET tube is accessed to the 2nd supply voltage; the 2nd supply voltage is equivalent to half of the 1st supply voltage; grid of the 1st, 4th, 14th and 21st CNFET tubes is connected to that of the 25th CNFET tube, and the connecting terminal is connected to the output terminal of the said double-edge pulse signal generator; drain of the 1st, 2nd, 5th and 9th CNFET tubes is connected to that of the 11th CNFET tube; source of the 2nd CNFET tube is connected to the drain of 3rd CNFET tubes; the source of the 3rd and 8th CNFET tubes and drain of the 4th CNFET tube are connected to the source of the 10th CNFET tube; source of the 4th CNFET tube is grounded; source of the 5th CNFET tube is connected to the drain of the 6th CNFET tube; source of the 6th CNFET tube is connected to the drain of the 7th CNFET tube; source of the 7th CNFET tube is connected to the drain of the 8th CNFET tube; source of the 9th CNFET tube is connected to the drain of the 10th CNFET tube; drain of the 11th, 12th, 15th, 18th and 26th CNFET tubes is connected to the input terminal of the 1st three-value inverter; source of the 12th CNFET tube is connected to the drain of the 13rd CNFET tube; the source of the 13rd CNFET tubes, the drain of 14 th  CNFET tubes and the source of 17th CNFET tubes are connected to the source of the 20th CNFET tube; source of the 15th CNFET tube is connected to the drain of the 16th CNFET tube; source of the 16th CNFET tube is connected to the drain of the 17th CNFET tube; source of the 18th CNFET tube is connected to the drain of the 19th CNFET tube; source of the 19th CNFET tube is connected to the drain of the 20th CNFET tube; source of the 14th CNFET tube is grounded; drain of the 21st CNFET tube, grid of the 26th CNFET, drain of the 22nd CNFET tube and drain of the 27th CNFET tube are connected to the drain of the 30th CNFET tube; source of the 22nd CNFET tube is connected to the drain of the 23rd CNFET tube; source of the 23rd CNFET tube is connected to the drain of the 24th CNFET tube; source of the 24th CNFET tube, drain of the 25th CNFET tube and source of the 29th CNFET tube is connected to the source of 31st CNFET tube; source of the 25th CNFET tube is grounded; source of the 27th CNFET tube is connected to the drain of the 28th CNFET tube; source of the 28th CNFET tube is connected to the drain of the 29th CNFET tube; source of the 30th CNFET tube is connected to the drain of the 31st CNFET tube; grid of the 2nd CNFET tube, input terminal of the 3rd NTI gate circuit and grid of the 22nd CNFET tube are connected to the input terminal of the 5th PTI gate circuit, and the connecting terminal is the end J of the said JKL flip-flop; grid of the 5th CNFET tube, input terminal of the 1st PTI gate circuit and grid of the 15th CNFET tube are connected to the input terminal of the 6th NTI gate circuit, and the connecting terminal is end K of the said JKL flip-flop; input terminal of the 2 nd  NTI gate circuit, input terminal of the 4 th  PTI gate circuit and grid of the 18 th  CNFET tube are connected to the grid of the 30 th  CNFET, and the connecting terminal is end L of the said JKL flip-flop; input terminal of the 1 st  NTI circuit, input terminal of the 2 nd  PTI gate circuit, grid of the 8 th  CNFET tube grid of the 9 th  CNFET tube, input terminal of the 4 th  NTI circuit, input terminal of the 3 rd  PTI gate circuit, grid of the 17 th  CNFET tube, grid of the 20 th  CNFET tube, input terminal of the 5 th  NTI gate circuit, input terminal of the 6 th  PTI gate circuit, grid of the 29 th  CNFET tube and grid of the 31 st  CNFET tube are connected to the output terminal of the 2 nd  three-value inverter, and the connecting terminal is the output terminal of the said JKL flip-flop; output terminal of the 1 st  NTI gate circuit is connected to the grid of the 3 rd  CNFET tube; output terminal of the 2nd NTI gate circuit is connected to the grid of the 10th CNFET tube; output terminal of the 1st PTI gate circuit is connected to the grid of the 6th CNFET tube; output terminal of the 2nd PTI gate circuit is connected to the grid of the 7th CNFET tube; output terminal of the 3rd NTI gate circuit is connected to the grid of the 12th CNFET tube; output terminal of the 4th NTI gate circuit is connected to the grid of the 13th CNFET tube; output terminal of the 3rd PTI gate circuit is connected to the grid of the 16th CNFET tube; output terminal of the 4th PTI gate circuit is connected to the grid of the 19th CNFET tube; output terminal of the 5th PTI gate circuit is connected to the grid of the 23rd CNFET tube; output terminal of the 5th NTI gate circuit is connected to the grid of the 24th CNFET tube; output terminal of the 6th PTI gate circuit is connected to the grid of the 28th CNFET tube; output terminal of the 6th NTI gate circuit is connected to the grid of the 27th CNFET tube; output terminal of the 1st three-value inverter is connected to the input terminal of the 2nd three-value inverter. 
         [0006]    The said NTI gate circuit comprises the 32nd and 33 rd  CNFET tubes; the 30 th  CNFET tube belongs to P CNFET tube; the 33 rd  CNFET tube belongs to N CNFET tube; source of the 32 nd  CNFET tube is accessed to the 1 st  supply voltage; grid of the 32 nd  CNFET tube is connected to the grid of the 33 rd  CNFET tube, and its connecting terminal is the input terminal of the said NTI gate circuit; drain of the 32 nd  CNFET tube is connected to the drain of the 33 rd  CNFET tube, and its connecting terminal is the output terminal of the said NTI gate circuit; source of the 33 rd  CNFET tube is grounded. 
         [0007]    The said PTI gate circuit comprises the 34 th  and 35 th  CNFET tubes; the 34 th  CNFET tube belongs to P CNFET tube; the 35 t h CNFET tube belongs to N CNFET tube; source of the 34 th  CNFET tube is accessed to the 1 st  supply voltage; grid of the 34 th  CNFET tube is connected to the grid of the 35 th  CNFET tube, and its connecting terminal is the input terminal of the said PTI gate circuit; drain of the 34 th  CNFET tube is connected to the drain of the 35 th  CNFET tube, and its connecting terminal is the output terminal of the said PTI gate circuit; source of the 35 th  CNFET tube is grounded. 
         [0008]    The 1 st  three-value inverter comprises the 36 th , 37 th , 38 th , 39 th , 40 th  and 41 st  CNFET tubes; the 36 th , 37 th  and 38 th  CNFET tubes belong to P CNFET tubes; the 39 th , 40 th  and 41 st  CNFET tubes belong to N CNFET tubes; source of the 36 th  and 37 th  CNFET tubes is accessed to the 1 st  supply voltage; source of the 36 th , 37 th  and 40 th  CNFET tubes is connected to the source of the 41 st  CNFET tube, and its connecting terminal is the input terminal of the 1 st  three-value inverter; drain of the 36 th  CNFET tube is connected to the drain of the 38 th  CNFET tube; source of the 38 th  CNFET tube, grid of the the 38 th  CNFET tube, grid of the 39 th  CNFET tube, drain of the 39 th  CNFET tube and drain of the 37 th  CNFET tube are connected to the drain of the 41 st  CNFET tube, and their connecting terminals are the output terminal of the 1 st  three-value inverter; source of the 39 th  CNFET tube is connected to the drain of the 40 th  CNFET tube; source of the 40 th  and 41 st  CNFET tubes is grounded. 
         [0009]    The double-edge pulse signal generator comprises the 1 st , 2 nd , 3 rd , 4 th  and 5 th  two value inverters, the 42 nd , 43 rd , 44 th  and 45 th  CNFET tubes; the 42 nd  and 43 rd  CNFET tubes belong to P CNFET tubes; the 44 th  and 45 th  CNFET tubes belong to N CNFET tubes; input terminal of the 1 st  two-value inverter, grid of the 43 rd  CNFET tube and source of the 44 th  CNFET tube and are connected to the grid of 45 th  CNFET tube, and their connecting terminals constitute input terminal of the said double-edge pulse signal generator; output terminal of the 1 st  two-value inverter is connected to the input terminal of the 2 nd  two-value inverter; output terminal of the 2 nd  two-value inverter is connected to the input terminal of the 3 rd  two-value inverter; output terminal of the 3 rd  two-value inverter, grid of the 42 nd  CNFET tube and grid of the 44 th  CNFET tube are connected to the source of the 45 th  CNFET tube; source of the 42 nd  CNFET tube is accessed to the 1 st  supply voltage; drain of the 42 nd  CNFET tube is connected to the source of the 43 rd  CNFET tube; drain of the 43 rd , 44 th  and 45 th  CNFET tubes is connected to the input terminal of the 4 th  two-value inverter; output terminal of the 4 th  two-value inverter is connected to the input terminal of the 5 th  two-value inverter; output terminal of the 5 th  two-value inverter is the output terminal of the said double-edge pulse signal generator. 
         [0010]    As compared with prior art, the present invention has the following features: It makes use of clock signal accessed to the double-edge pulse signal generator clk to control the connection of JKL flip-flop; it further makes use of node Y connecting drain of the 1 st , 2 nd , 5 th  and 9 th  CNFET tubes and grid of the 11 th  CNFET tube and node Z connecting drain of the 21 st  CNFET tube, grid of the 26 th  CNFET tube, and drain of the 22 nd , 27 th  and 30 th  CNFET tubes to control jumping of JKL flip-flop among “0”, “1” and “2”; this aims to reduce the power consumption while improving working efficiency of JKL flip-flop. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0011]      FIG. 1  is the circuit diagram of the prevent invention; 
           [0012]      FIG. 2 ( a )  is the circuit diagram for NTI gate circuit of the present invention; 
           [0013]      FIG. 2 ( b )  is the graphical diagram for NTI gate circuit of the present invention; 
           [0014]      FIG. 2 ( c )  is the circuit diagram for PTI gate circuit of the present invention; 
           [0015]      FIG. 2 ( d )  is the graphical diagram for PTI gate circuit of the present invention; 
           [0016]      FIG. 3 ( a )  is the circuit diagram for the 1 st  three-value inverter of the present invention; 
           [0017]      FIG. 3 ( b )  is the graphical diagram for the 1 st  three-value inverter of the present invention; 
           [0018]      FIG. 4  is the circuit diagram for the double-edge pulse signal generator of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0019]    The present invention is further described as follows in combination with drawings and embodiments. 
       Embodiment 
       [0020]    A CNFET double-edge pulse JKL flip-flop as shown in  FIG. 1 , comprising a double-edge pulse signal generator  1 , a 1 st  CNFET tube N 1 , a 2 nd  CNFET tube N 2 , the 3 rd  CNFET tube N 3 , the 4 th  CNFET tube N 4 , the 5 th  CNFET tube N 5 , the 6 th  CNFET tube N 6 , the 7 th  CNFET tube N 7 , the 8 th  CNFET tube N 8 , the 9 th  CNFET tube N 9 , the 10 th  CNFET tube N 10 , the 11 th  CNFET tube N 11 , the 12 th  CNFET tube N 12 , the 13rd CNFET tube N 13 , the 14 th  CNFET tube N 14 , the 15 th  NFET tube N 15 , the 16 th  CNFET tube N 16 , the 17 th  CNFET tube N 17 , the 18 th  CNFET tube N 18 , the 19 th  CNFET tube N 19 , the 20 th  CNFET tube N 20 , the 21 st  CNFET tube N 21 , the 22 nd  CNFET tube N 22 , the 23 rd  CNFET tube N 23 , the 24 th  CNFET tube N 24 , the 25 th  CNFET tube N 25 , the 26 th  CNFET tube N 26 , the 27 th  CNFET tube N 27 , the 28 th  CNFET tube  28 , 29 th  CNFET tube N 29 , the 30 th  CNFET tube N 30 , the 31 st  CNFET tube N 31 , 6 NTI gate circuits of the same circuit structure, 6 PTI gate circuits of the same circuit structure, the 1 st  three-value inverter F 1  and the 2 nd  three-value inverter F 2  of the same circuit structure; 6 NTI gate circuits comprise the 1 st  gate circuit T 1 , the 2 nd  NTI gate circuit T 2 , the 3 rd  NTI gate circuit T 3 , the 4 th  NTI gate circuit T 4 , the 5 th  NTI gate circuit T 5  and the 6 th  NTI gate circuit T 6 ; 6 PTI gate circuits comprise the 1 st  PTI gate circuit P 1 , the 2 nd  PTI gate circuit P 2 , the 3 rd  PTI gate circuit P 3 , the 4 th  PTI gate circuit P 4 , the 5 th  PTI gate circuit P 5  and the 6 th  PTI gate circuit P 6 ; the 1 st  CNFET tube N 1 , the 11 th  CNFET tube N 11 , the 21 st  CNFET tube N 21  and the 26 th  CNFET tube N 26  belong to P CNFET tubes; the 2 nd  CNFET tube N 2 , the 3 rd  CNFET tube N 3 , the 4 th  CNFET tube N 4 , the 5 th  CNFET tube N 5 , the 6 th  CNFET tube N 6 , the 7 th  CNFET tube N 7 , the 8 th  CNFET tube N 8 , the 9 th  CNFET tube N 9 , the 10 th  CNFET tube N 10 , the 12 th  CNFET tube N 12 , the 13rd CNFET tube N 13 , the 14 th  CNFET tube N 14 , the 15 th  CNFET tube N 15 , the 16 th  CNFET tube N 16 , the 17 th  CNFET tube N 17 , the 18 th  CNFET tube N 18 , the 19 th  CNFET tube N 19 , the 20 th  CNFET tube N 20 , the 22 nd  CNFET tube N 22 , the 23 rd  CNFET tube N 23 , the 24 th  CNFET tube N 24 , the 25 th  CNFET tube N 25 , the 27 CNFET tube N 27 , the 28 th  CNFET tube N 28 , the 29 th  CNFET tube N 29 , the 30 th  CNFET tube N 30  and the 31 st  CNFET tube N 31  belong to N CNFET tubes; source of the 1 st  CNFET tube N 1 , the 11 th  tube N 11  and the 21 st  CNFET tube N 21  is accessed to the 1 st  supply voltage; source of the 26 th  CNFET tube N 26  is accessed to the 2 nd  supply voltage; the 2 nd  supply voltage is equivalent to half of the 1 st  supply voltage; grid of the 1 st  CNFET tube N 1 , the 4 th  CNFET tube N 4 , the 14 th  CNFET tube N 14  and the 21 st  CNFET tube N 21  is connected to that of the 25 th  CNFET tube, and the connecting terminal is connected to the output terminal of the said double-edge pulse signal generator  1 ; drain of the 1 st  CNFET tube N 1 , the 2 nd  CNFET tube N 2 , the 5 th  CNFET tube N 5  and the 9 th  CNFET tube N 9  is connected to grid of the 11 th  CNFET tube N 11 ; source of the 2 nd  CNFET tube N 2  is connected to the drain of the 3rd CNFET tube N 3 ; source of the 3 rd  CNFET tube N 3  and the 8 th  CNFET tube N 8  and drain of the 4 th  CNFET tube N 4  are connected to the source of 10 th  CNFET tube N 10 ; source of the 4 th  CNFET tube N 4  is grounded; source of the 5 th  CNFET tube N 5  is connected to the drain of the 6 th  CNFET tube N 6 ; source of the 6 th  CNFET tube N 6  is connected to the drain of the 7 th  CNFET tube N 7 ; source of the 7 th  CNFET tube N 7  is connected to the drain of the 8 th  CNFET tube N 8 ; source of the 9 th  CNFET tube N 9  is connected to the drain of the 10 th  CNFET tube N 10 ; drain of the 11 th  CNFET tube N 11 , the 12 th  CNFET tube N 12 , the 15 th  CNFET tube N 15 , the 18 th  CNFET tube N 18  and the 26 th  CNFET tube N 26  is connected to the input terminal of the 1 st  three-value inverter F 1 ; source of the 12 th  CNFET tube N 12  is connected to the drain of the 13rd CNFET tube N 13 ; source of the 13rd CNFET tube N 13 , drain of the 14 th  CNFET tube N 14  and source of the 17 th  CNFET tube N 17  are connected to the source of the 20 th  CNFET tube N 20 ; source of the 15 th  CNFET tube N 15  is connected to the drain of the 16 th  CNFET tube N 16 ; source of the 16 th  CNFET tube N 16  is connected to the drain of the 17 th  CNFET tube N 17 ; source of the 18 th  CNFET tube N 18  is connected to the drain of the 19 th  CNFET tube N 19 ; source of the 19 th  CNFET tube N 19  is connected to the drain of the 20 th  CNFET tube N 20 ; source of the 14 th  CNFET tube N 14  is grounded; drain of the 21 st  CNFET tube N 21 , grid of the 26 th  CNFET tube N 26 , drain of the 22 nd  CNFET tube N 22  and drain of the 27 th  CNFET tube N 27  are connected to the drain of the 30 th  CNFET tube N 30 ; source of the 22 nd  CNFET tube N 22  is connected to the drain of the 23 rd  CNFET tube N 23 ; source of the 23 rd  CNFET tube N 23  is connected to the drain of the 24 th  CNFET tube N 24 ; source of the 24 th  CNFET tube N 24 , drain of the 25 th  CNFET tube N 25  and source of the 29 th  CNFET tube N 29  are connected to the source of 31 st  CNFET tube N 31 ; source of the 25 th  CNFET tube N 25  is grounded; source of the 27 th  CNFET tube N 27  is connected to the drain of the 28 th  CNFET tube N 28 ; source of the 28 th  CNFET tube N 28  is connected to the drain of the 29 th  CNFET tube N 29 ; source of the 30 th  CNFET tube N 30  is connected to the drain of the 31 st  CNFET tube N 31 ; grid of the 2 nd  CNFET tube N 2 , input terminal of the 3 rd  NTI gate circuit T 3  and grid of the 22 nd  CNFET tube N 22  are connected to the input terminal of the 5 th  PTI gate circuit P 5 , and the connecting terminal is the terminal J of the said JKL flip-flop; grid of the 5 th  CNFET tube N 5 , input terminal of the 1 st  PTI gate circuit P 1  and grid of the 15 th  CNFET tube N 15  are connected to the input terminal of the 6 th  NTI gate circuit T 6 , and the connecting terminal is terminal K of JKL flip-flop; input terminal of the 2 nd  NTI gate circuit T 2 , input terminal of the 4 th  PTI gate circuit P 4  and grid of the 18 th  CNFET tube N 18  are connected to the grid of the 30 th  CNFET tube N 30 , and the connecting terminal is terminal L of JKL flip-flop; input terminal of the 1 st  NTI gate circuit T 1 , input terminal of the 2 nd  PTI gate circuit P 2 , grid of the 8 th  CNFET tube N 8 , grid of the 9 th  CNFET tube N 9 , input terminal of the 4 th  NTI gate circuit T 4 , input terminal of the 3 rd  PTI gate circuit P 3 , grid of the 17 th  CNFET tube N 17 , grid of the 20 th  CNFET tube N 20 , input terminal of the 5 th  NTI gate circuit  15 , input terminal of the 6 th  PTI gate circuit P 6 , grid of the 29 th  CNFET tube N 29  and grid of the 31 st  CNFET tube N 31  are connected to the output terminal of the 2 nd  three-value inverter F 2 , and the connecting terminal is the output terminal of JKL flip-flop; output terminal of the 1 st  NTI gate circuit T 1  is connected to the grid of the 3 rd  CNFET tube N 3 ; output terminal of the 2 nd  NTI gate circuit T 2  is connected to the grid of the 10 th  CNFET tube N 10 ; output terminal of the 1 st  PTI gate circuit P 1  is connected to the grid of the 6 th  CNFET tube N 6 ; output terminal of the 2 nd  PTI gate circuit P 2  is connected to the grid of the 7 th  CNFET tube N 7 ; output terminal of the 3 rd  NTI gate circuit is connected to the grid of the 12 th  CNFET tube N 12 ; output terminal of the 4 th  NTI gate circuit T 4  is connected to the grid of the 13 th  CNFET N 13 ; output terminal of the 3 rd  PTI gate circuit P 3  is connected to the grid of the 16 th  CNFET tube N 16 ; output terminal of the 4 th  PTI gate circuit P 4  is connected to the grid of the 19 th  CNFET tube N 19 ; output terminal of the 5 th  PTI gate circuit P 5  is connected to the grid of the 23 rd  CNFET tube N 23 ; output terminal of the 5 th  NTI gate circuit P 5  is connected to the grid of the 24 th  CNFET tube N 24 ; output terminal of the 6 th  PTI gate circuit is connected to the grid of the 28 th  CNFET tube N 28 ; output terminal of the 6 th  NTI gate circuit T 6  is connected to the grid of the 27 th  CNFET tube N 27 ; output terminal of the 1 st  three-value inverter F 1  is connected to the input terminal of the 2 nd  three-value inverter F 2 . 
         [0021]    As shown in  FIGS. 2 ( a ) and ( b ) , NTI gate circuit in this embodiment comprises the said 32 nd  CNFET tube N 32  and the 33 rd  CNFET tube N 33 ; the 32 nd  CNFET tube N 32  belongs to P CNFET tube; the 33 rd  CNFET tube N 33  belongs to N CNFET tube; source of the 32 nd  CNFET tube N 32  is accessed to the 1 st  supply voltage; grid of the 32 nd  CNFET tube N 32  is connected to the grid of the 33 rd  CNFET tube N 33 , and the connecting terminal is the input terminal of the NTI gate circuit; drain of the 32 nd  CNFET tube N 32  is connected to the drain of the 33 rd  CNFET tube N 33 , and the connecting terminal is the output terminal of NTI gate circuit; source of the 33 rd  CNFET tube N 33  is grounded. 
         [0022]    As shown in  FIGS. 2 ( c ) and ( d ) , PTI gate circuit in this embodiment comprises the 34 th  CNFET tube N 34  and the 35 th  CNFET tube N 35 ; the 34 th  CNFET tube N 34  belongs to P CNFET tube; the 35 th  CNFET tube N 35  belongs to N CNFET tube; source of the 34 th  CNFET tube N 34  is accessed to the 1 st  supply voltage; grid of the 34 th  CNFET tube N 34  is connected to the grid of the 35 th  CNFET tube N 35 , and the connecting terminal is the input terminal of PTI gate circuit; drain of the 34 th  CNFET tube N 34  is connected to the drain of the 35 th  CNFET tube N 35 , and the connecting terminal is the output terminal of PTI gate circuit; source of the 35 th  CNFET tube N 35  is grounded. 
         [0023]    As shown in  FIGS. 3 ( a ) and ( b ) , the 1 st three-value inverter F 1  in this embodiment comprises the 36 th  CNFET tube N 36 , the 37 th  CNFET tube N 37 , the 38 th  CNFET tube N 38 , the 39 th  CNFET tube N 39 , the 40 th  CNFET tube N 40  and the 41 st  CNFET tube N 41 ; the 36 th  CNFET tube N 36 , the37 th  CNFET tube N 37  and the 38 th  CNFET tube N 38  belong to P CNFET tubes; the 329 th  CNFET tube N 39 , the 40 th  CNFET tube N 40  and the 41 st  CNFET tube N 41  belong to N CNFET tubes; source of the 36 th  CNFET tube N 36  and the 37 th  CNFET tube N 37  is accessed to the 1 st  supply voltage; grid of the 36 th  CNFET tube N 36 , the 37 th  CNFET tube N 37 , the 40 th  CNFET tube N 40  and the 41 st  CNFET tube N 41  is connected, and the connecting terminal is the input terminal of the 1 st  three-value inverter F 1 ; drain of the 36 th  CNFET tube N 36  is connected to the grid of the 38 th  CNFET tube N 38 ; source of the 38 th  CNFET tube N 38 , grid of the 38 th  CNFET tube N 38 , grid of the 39 th  CNFET tube N 39 , drain of the 39 th  CNFET tube N 39  and drain of the 37 th  CNFET tube N 37  are connected to the drain of the 41 st  CNFET tube N 41 , and the connecting terminal is the output terminal of the 1 st  three-value inverter F 1 ; source of the 39 th  CNFET tube N 39  is connected to the drain of the 40 th  CNFET tube N 40 ; source of the 40 th  CNFET tube N 40  and the 41 st  CNFET tube N 41  is grounded. 
         [0024]    As shown in  FIG. 4 , the double-edge pulse signal generator  1  in this embodiment comprises the 1 st  two-value inverter G 1 , the 2 nd  two-value inverter G 2 , the 3 rd  two-value inverter G 3 , the 4 th  two-value inverter G 4 , the 5 th  two-value inverter G 5 , the 42 nd  CNFET tube N 42 , the 43 rd  CNFET tube N 43 , the 44 th  CNFET tube N 44  and the 45 th  CNFET tube N 45 ; the 42 nd  CNFET tube N 42  and the 43 rd  CNFET tube N 43  belong to P CNFET tubes; the 44 th  CNFET tube N 44  and the 35 th  CNFET tube N 45  belong to N CNFET tubes; input terminal of the 1 st  two-value inverter G 1 , grid of the 43 rd  CNFET tube N 43  and source of the 44 th  CNFET tube N 44  are connected to the grid of the the 45 th  CNFET tube N 45 , and the connecting terminal is the input terminal of the double-edge pulse signal generator  1 ; output terminal of the 1 st  two-value inverter G 1  is connected to the input terminal of the 2 nd  two-value inverter G 2 ; output terminal of the 2 nd  two-value inverter G 2  is connected to the input terminal of the 3 rd  two-value inverter G 3 ; output terminal of the 3 rd  two-value inverter G 3 , grid of the 42 nd  CNFET tube N 43  and grid of the 44 th  CNFET tube N 44  are connected to the source of the 45 th  CNFET tube N 45 ; source of the 42 nd  CNFET tube N 42  is accessed to the 1 st  supply voltage; drain of the 42 nd  CNFET tube N 42  is connected to the source of the 43 rd  CNFET tube N 43 ; drain of the 43 rd  CNFET tube N 43 , drain of the 44 th  CNFET tube N 44  and drain of the 45 th  CNFET tube N 45  are connected to the input terminal of the 4 th  two-value inverter G 4 ; output terminal of the 4 th  two-value inverter G 4  is connected to the input terminal of the 5 th  two-value inverter G 5 ; output terminal of the 5 th  two-value inverter G 5  is the output terminal of the double-edge pulse signal generator  1 . 
         [0025]    In this embodiment, the 1 st  supply voltage is 0.9V, and the 2 nd  supply voltage is 0.45V. 
         [0026]    In aforesaid embodiments, caliber (diameter) of each CNFET tube is as shown in figures; caliber unit D is nm.