Abstract:
A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the fabrication and structure of integrated circuit and, more particularly, to the fabrication and structure of the integrated circuit with an electrostatic discharge (ESD) device. 
       BACKGROUND OF THE INVENTION 
       [0002]    To safeguard circuits in an integrated circuit chip from electrostatic discharge, a device is included in the integrated circuit chip for protection during an electrostatic discharge event. Such protection can prevent damage from high voltage or current transients. Metal oxide semiconductors field effect transistors (MOSFETs) are particularly vulnerable to electrostatic discharge because an electrostatic discharge event can damage the gates of the MOSFETs, especially those with thin gate oxides. 
         [0003]    The trend in semiconductor manufacture continues to be the reduction of the size of the overall I/O area on an integrated circuit and to enable a larger number of I/O pins on an integrated circuit chip. Unfortunately, the largest percent of the I/O area is used by the electrostatic protection devices. Accordingly, to increase the number of I/Os on the overall integrated circuit, the size of the ESD protection devices and, hence, the I/O area of the ESD devices must be reduced without affecting the protection of the non-ESD devices. 
         [0004]    ESD NMOSFETs are commonly used as ESD protection devices. The required characteristics of the NMOSFET based protection devices are: low trigger voltage (Vt1), high failure current (It2) and low on-resistance (Ron). In order to reduce the size of the ESD protection device and still meet the ESD protection requirements, the failure current of the ESD NMOSFET needs to be increased and the on-resistance needs to be decreased compared with prior art devices. This, in turn, would enable a reduction in the device width and, therefore, a reduction in the area of the ESD device. Substrate triggering techniques are commonly used to reduce the trigger voltage, increase the failure current and lower the on-resistance. 
         [0005]    A basic prior art device for electrostatic discharge (ESD) protection is shown in  FIG. 1  and is a n-channel MOSFET between the input pad and the substrate and closely coupled to ground. To enhance the protection capability of this prior art device, a further prior art technique employs a lateral NPN transistor integral within a n-channel MOSFET. This ESD device is used to shunt to ground a large transient by turning on the lateral NPN when the event occurs. Another prior art technique also uses a lateral NPN transistor but it is coupled to the input element and operates to activate when the input element voltage exceeds threshold, the threshold being greater than or equal to the ordinary operating voltage of the circuitry coupled to the input element. However, none of these prior art structures will provide sufficient ESD protection when the area of the protection device is reduced in size, such as by as much as about 20 percent. 
       SUMMARY OF THE INVENTION 
       [0006]    Accordingly, the primary object of the present invention is to provide and fabricate a MOSFET integrated circuit with an ESD protection device of reduced area but with increased I/O pins and at least equal in protection ability to ESD devices of a larger scale. 
         [0007]    A further object of the present invention is to provide and fabricate an ESD MOSFET with the required characteristic of a lower trigger voltage (Vt1) with a modified substrate triggering techniques to achieve this characteristic. 
         [0008]    An additional object of the present invention is to provide and fabricate an ESD MOSFET with the required characteristic of a higher failure current (It2) with a modified substrate triggering techniques to achieve this characteristic. 
         [0009]    Another object of the present invention is to provide and fabricate an ESD MOSFET with the required characteristic of a low on-resistance (Ron) with modified substrate triggering techniques to achieve this characteristic. 
         [0010]    These and other objects and features of the present invention are accomplished by a method of fabricating, and the resulting structure, a protection device comprising integrating a lateral bipolar with a MOSFET and within a triple well including an isolated well for performing the substrate triggering. The MOSFET can be either a n-channel or a p-channel with the lateral bipolar being of opposite polarity. Preferably, the lateral bipolar is formed with diodes at its I/O and/or its VDDs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    These and further features of the present invention will be apparent with reference to the following description of the present invention along with the following  FIGS. 1-8 : 
           [0012]      FIG. 1  (PRIOR ART) is a circuit schematic of a conventional ESD NMOSFET with a grounded gate. 
           [0013]      FIG. 2  is a circuit schematic of the preferred embodiment of the present invention with a lateral p-n-p integrated into an ESD NMOSFET and with the emitter of the p-n-p tied to the I/O pad. 
           [0014]      FIG. 3  is a cross-sectional view of the preferred embodiment of the present invention with an isolated P-well as part of a NMOSFET. 
           [0015]      FIG. 4  is a cross-sectional view of a modification of the preferred embodiment of the present invention with additional diodes in series with the emitter-base diodes of the lateral p-n-p. 
           [0016]      FIG. 5  is a cross-sectional view of a further modification of the preferred embodiment of the present invention with diodes at each of the VDDs. 
           [0017]      FIG. 6  is a cross-sectional view of an alternative embodiment of the present invention with an isolated N-well as part of a PMOSFET. 
           [0018]      FIG. 7  is a cross-sectional view of a modification of the alternative embodiment of the present invention with additional diodes in series with the emitter-base diodes of the lateral n-p-n. 
           [0019]      FIG. 8  is a cross-sectional view of a further modification of the alternative embodiment of the present invention with a diode at the VDD. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    As shown by the schematic of  FIG. 1  (PRIOR ART), a NMOSFET  10  is connected to an I/O pad  11  and comprises a source  12 , drain  13  and gate  14 . In operation, during a positive mode discharge on the I/O pad  11  with respect to ground  15 , the N+ drain  13 /P-well junction breaks down and results in an avalanche of carriers in the form of generated holes. The holes are collected by the substrate and raise the substrate potential, which results in substrate current and in forward biasing the N+ source/P-well junction. A parasitic lateral n-p-n turns on and safely discharges the ESD current to ground  15 . 
         [0021]    In accordance with the present invention, the conventional MOSFET, herein a NMOSFET  10   a  in the preferred embodiment, is modified to provide an improved ESD protection device. A lateral bipolar, herein a p-n-p device  16 , is fabricated and made integral with the NMOSFET  10   a , as shown by the schematic of  FIG. 2 , and comprises an emitter  18 , a collector  20 , and a base  17 . The emitter  18  of the lateral p-n-p  16  is connected to the I/O pad  11   a  and the base  20  of the p-n-p  16  is connected to VDD. The collector  18  of the p-n-p is connected to the isolated P-well. The resistance of the isolated P-well, which is connected to ground, is represented by the resistor  19 . During an ESD event, the lateral p-n-p  16  injects holes into the isolated P-well, raising the isolated P-well potential. Thus, the P-well current (I-sub) which, is necessary to turn-on the parasitic lateral n-p-n, comes from two sources: 1) avalanche generation near N+ drain  13   a /p-well junction, and 2) lateral p-n-p collector  20  current. For the ESD structure of the present invention, smaller drain voltage is required to turn-on the parasitic lateral n-p-n. Therefore, the ESD NMOSFET trigger voltage (Vt1) and holding voltage are reduced. By this reduction, the scale or area of the ESD protection device can be made smaller. In addition, there is an increase in the failure current and a reduction in the on-resistance of the ESD device. This reduction in trigger voltage (Vt1), the increase in failure current and the reduction in on-resistance permit the scaling down of the width and area of the ESD protection device and allow for an increased number of I/O pins in the ESD protection device and the functional circuits without reducing the protection capability of the ESD device. 
         [0022]    Turning now to  FIG. 3 , which is a cross-section of the ESD protection device of the present invention, there is shown a substrate  21  with an uniform N-band  22  therein. Above the N-band, a herein isolated P-Well  23 , contains the herein NMOSFET  10   a  and is formed with a source  12   a , a drain  13   a  and a gate  14   a . In the present instance, on both sides of the isolated P-Well are N-Wells  24  and  24 ′, which are physically the same Well. Deposed therein and integral with the NMOSFET  10   a , are lateral bipolars, herein p-n-p  16  and  16 ′ to achieve an apparent triple Well structure. N-Well  24  with lateral p-n-p  16  comprises the elements of a base  17 , a emitter  18  and a collector  20  with a collector contact, while N-Well  24 ′ with lateral p-n-p  16 ′ comprises the elements of a base  17 ′, a emitter  18 ′ and a collector  20 ′ with a collector contact. The contacts of the collectors  20  and  20 ′ also serve as the isolated P-Well contact to the NMOSFET. These elements of the lateral n-p-n  16  and  16 ′ are separated and isolated from each other and the MOSFET  10   a  in the substrate by the N-Band  22  and recessed trenches  25  containing an insulating material, such as silicon oxide. The emitters  18  and  18 ′ of the lateral p-n-p  16  and  16 ′ are connected to the I/O pad  11   a , each preferably through diodes  26  and  26 ′, and along with the drain  13   a  of the MOSFET, which herein has low leakage. Ground  15   a  is connected to the collector  20  and  20 ′ of the lateral p-n-p and the source  12   a  and gate  14   a  of the MOSFET, whereas VDD is connected to the bases  17  and  17 ′. During normal operation of the integrated circuit, the bases  17  and  17 ′ are connected to VDD causing the emitter-base diodes  26  and  26 ′ to be preferably reversed biased. Although the diodes are not required, their purpose is to establish the voltage on the pad  11   a  higher than the VDD voltage and adjust current injected by p-n-p bipolar transistor. 
         [0023]    A modification of the preferred embodiment of the present invention is shown in  FIG. 4  where additional emitter-base diodes  27  and  27 ′ are disposed in series with the emitter-base diodes  26  and  26 ′. Although only two diodes are added in series in  FIG. 4 , more diodes could be added in series if desired. 
         [0024]    A further modification of the preferred embodiment of the present invention is shown in  FIG. 5  where diodes  28  and  28 ′ are added to the collectors  17  and  17 ′, respectively, at VDD. These diodes can be partially or totally in place of or in addition to the diodes  26 ,  26 ′  27  and  27 ′ of  FIG. 4 . 
         [0025]    In operation, during a positive mode ESD event on the I/O pad  11   a , the n+ drain  13   a /isolated P-Well  23  junction breaks down and results in an avalanche generation of carriers. The generated holes are collected in the isolated P-Well and this raises the overall isolated P-Well potential. The resulting isolated P-Well current causes a local isolated P-Well potential increase and in forward biasing the n+ source  12   a /isolated P-Well  23 . With these conditions, the parasitic lateral n-p-n turns on and safely discharges ESD current to ground  15   a . Thus, unique to the present invention, the isolated P-Well current (Isub) necessary to turn-on the parasitic lateral n-p-n is provided by two sources; namely, 1) avalanche generation near n+ drain  13   a /P-Well junction  23 , and 2) lateral p-n-p collector  20  and  20 ′ current. Accordingly, for the same MOSFET structure as the prior art, a smaller drain  13   a  voltage is now required to turn on the parasitic lateral n-p-n. Because of this, the ESD MOSFET trigger voltage (Vt1) and holding voltage can be reduced which, in turn, permits a smaller dimension integrated circuit with increased I/O pins with similar ESD protection as the prior art of a larger dimension integrated circuit with fewer I/O pins. A large failure current is achieved with this reduced ESD device area. The trigger voltage (Vt1) is smaller than the Vt1 of any NFET and/or PFET drivers and the gate oxide breakdown voltage of any receivers. 
         [0026]    During a negative mode ESD event on the I/O pad  11   a , the N+/isolated P-Well diode which is intrinsic to an NMOSFET turns on and discharges the ESD current safely to ground. The N+/isolated P-Well  23  comprises the cathode formed in the drain  13   a  junction and the anode contact which is formed by the isolated P-Well  23 . 
         [0027]    In accordance with another aspect of the present invention, an alternative embodiment is disclosed and shown in  FIGS. 6-8 . In  FIG. 6 , which is a cross-section of the alternative ESD protection device of the present invention, there is shown a substrate  41  with N-bands  42  therein and separated by a N-Well  43 , which contains herein PMOSFET  40  and is formed with a source  40   a , a drain  40   b  and a gate  40   c  which is connected to VDD, preferably through a diode  52 . Above the N-bands  42 , which are connected and are a single band, are formed isolated P-Wells  44 , which again are connected and are physically the same well. Deposed therein and integral with the PMOSFET  40 , are lateral bipolars, herein n-p-n  45  and  45 ′ to achieve an apparent triple Well structure. Isolated P-Well  44  with lateral n-p-n  45  comprise the elements of a base  45   a , an emitter  45   b  and a collector  45   c  with a collector contact (not shown), while isolated P-Well  44 ′ with lateral n-p-n  45 ′ comprises the elements of a base  45   a ′, an emitter  45   b ′ and a collector  45   c ′ with a collector contact. The contacts of the collectors  45   c  and  45 ′ also serve as the isolated N-Well contact to the PMOSFET  40 . These elements of the lateral n-p-n  44  and  44 ′ are separated and isolated from each other and the PMOSFET  40  in the substrate by the N-Band  42  and recessed trenches  46  containing an insulating material, such as silicon oxide. The emitters  45   b  and  45   b ′ of the lateral p-n-p  45  and  45 ′ are connected to the I/O pad  47 , each preferably through diodes  48  and  48 ′, and along with the drain  40   b  of the PMOSFET, which herein has low leakage. Ground  49  is connected to the base  45   a  and  45   a ′ of the lateral p-n-p and to the PMOSFET, whereas VDD is connected to the emitters  45   b  and  45   b ′. The resistance of the isolated P-well, which is connected to ground, is represented by the resistor  50 . Adjacent the outer sides of the P-Wells  44  and  44 ′, N-Wells  51  and  51 ′ are formed and connected to VDD to isolate the P-Wells  44  and  44 ′ in the substrate  41 , along with the N-Bands  42  and  42 ′ and the N-Well  43 . During normal operation of the integrated circuit, the bases  45   a  and  45   a ′ are connected to ground causing the emitter-base diodes  48  and  48 ′ to be preferably reversed biased. Although the diodes are not required, their purpose is to establish the voltage on the pad  47  lower than the ground voltage and/or to adjust current injected by n-p-n bipolar transistors. 
         [0028]    In operation, during a negative mode ESD event on the I/O pad  47 , the p+ drain  40   c /N-Well  43  junction breaks down and results in an avalanche generation of carriers. The generated electrons are collected in the N-Well and this raises the overall N-Well potential. The resulting N-Well current causes a local N-Well potential to decrease and results in forward biasing the n+ source  40   a /isolated N-Well  43 . With these conditions, the parasitic lateral p-n-p turns on and safely discharges ESD current to VDD. Thus, unique to the present invention, the N-Well current (Isub) necessary to turn-on the parasitic lateral p-n-p is provided by two sources; namely, 1) avalanche generation near p+ drain  40   b /N-Well junction  43 , and 2) lateral n-p-n collector  45  and  45 ′ current. Accordingly, for a MOSFET structure as the prior art, a smaller drain  40   b  voltage is now required to turn on the parasitic lateral p-n-p. Because of this, the ESD MOSFET trigger voltage (Vt1) and holding voltage can be reduced which, in turn, permits a smaller dimension integrated circuit with increased I/O pins with similar ESD protection as the prior art of a larger dimension integrated circuit with fewer I/O pins. A large failure current is achieved with this reduced ESD device area. The trigger voltage (Vt1) is smaller than the Vt1 of any NFET and/or PFET drivers and the gate oxide breakdown voltage of any receivers. 
         [0029]    During a positive mode ESD event on the I/O pad  47 , the P+/N-Well diode which is intrinsic to an PMOSFET turns on and discharges the ESD current safely to VDD. The P+/isolated N-Well  43  comprise the anode formed in the drain  40   b  junction and the cathode contact which is formed by the N-Well  45   c.    
         [0030]    Although the invention has been shown and described with respect to certain embodiments, equivalent alterations and modifications will occur to those skilled in the art upon reading and understanding this specification and drawings. In doing so, those skilled in the art should realize that such alterations and modifications are within the spirit and scope of the present invention as set forth in the appended claims and equivalents thereon. Those skilled in the art also will understand that the semiconductor structure described by the present inventive technique will be part of a larger semiconductor device incorporating a plurality of semiconductor devices. For example, the semiconductor structure could be part of a p-channel or n-channel MOSFET integrated circuit, or part of a CMOS which incorporates both p-channel and n-channel MOSFET integrated circuits.