Abstract:
There is disclosed a TAB style BGA type semiconductor device. This semiconductor device comprises a semiconductor chip on which an integrated circuit is formed, and a polyimide tape which has a conductive pattern and which is allowed to adhere to the semiconductor chip. The conductive pattern includes a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to the outside electrode, and an electrically floating island-like portion in addition to a wiring portion for connecting the bonding portion and the pad portion.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-351902, filed Dec. 10, 1999, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates to semiconductor devices, and more particularly to a TAB type ball grid array semiconductor device.  
           [0003]    [0003]FIG. 1A is a plan view showing a conventional TAB type, FIG. 1B is a sectional view taken along the line  1 B- 1 B of FIG. 1A. FIG. 1C is a sectional view taken along the line  1 C- 1 C of FIG. 1A.  
           [0004]    As shown in FIGS. 1A through 1C, a Cu pattern  2  comprising copper (Cu) is formed on the surface of a polyimide tape (an insulating base)  1 . The Cu pattern  2  is formed by allowing, for example, a copper foil to adhere to the polyimide tape  1 , for example, with an adhesive agent and etching the Cu foil by using as a mask a resist layer having a pattern corresponding to, for example, the Cu pattern  2 . On the surface of the polyimide tape  1 , a solder resist layer  3  is formed, and this solder resist layer  3  is covered at least except for a wire bonding portion  2 WB, and a ball pad portion  2 BP.  
           [0005]    On the rear surface of the polyimide tape  1 , an adhesive agent layer  4  is formed. A protection tape  5  is allowed to adhere to the adhesive agent layer  4 .  
           [0006]    A semiconductor chip  6  is mounted on the TAB tape and is allowed to adhere to the TAB tape via the adhesive agent layer  4 .  
           [0007]    In allowing the semiconductor chip  6  to adhere to the TAB tape, as shown in FIG. 2A, the semiconductor chip  6  is picked up from the wafer-chip tray of the mounting device, and the semiconductor chip  6  is placed on a lower mold  22  of a pressurizing device.  
           [0008]    Next, as shown in FIG. 2B, after the position of the TAB tape having the protection tape  5  peeled off and the position the semiconductor chip  6  is corrected, an upper mold  23  is allowed to come down so that the chip  6  is bonded onto the TAB tape.  
           [0009]    However, with the conventional TAB tape, as shown in FIGS. 1B, 1C or FIG. 2B, an uneven configuration is generated on the surface where the Cu pattern  2  is formed with the presence and absence of the Cu pattern  2 . A concave portion  20  is a portion where no Cu pattern  2  is formed. A convex portion  21  is a portion where the Cu pattern  2  is formed.  
           [0010]    Therefore, when the chip  6  is heat pressurized to the TAB tape, the pressure is concentrated on the convex portion  21  as shown in FIG. 2C with the result that the pressure is applied to the concave portion  22  with greater difficulty. A difference in this pressure distribution generates a difference in the adherence force between the TAB tape and the chip  6  which will lead to the peeling off of the TAB tape from the chip  6  later.  
           [0011]    Furthermore, with the conventional TAB tape, as shown in FIG. 3A and FIG. 3B, there arises an intersection angle θ between the solder resist layer  3  and the wire bonding portion  2 WB is less than 90 degrees.  
           [0012]    Consequently, when the solder resist is printed on the TAB tape, a disuniformity is generated in the flow of the paste-like solder resist in the Cu pattern  2  particularly in the vicinity of the wire bonding portion  2 WB, so that bubbles  24  are easily involved in the solder resist layer  3 .  
           [0013]    When bubbles are generated in the solder resist layer  3 , and between the solder resist layer  3  and the polyimide tape  1 . Water infiltrates into the bubbles from the outside so that the Cu pattern  2  is eroded with the lapse of time.  
         BRIEF SUMMARY OF THE INVENTION  
         [0014]    The present invention has been made in view of the above circumstances. A first object of the invention is to provide a semiconductor device having a reduced difference in adherence force between an insulating base and a chip, and a stable adherence.  
           [0015]    Furthermore, a second object of the invention is to provide a semiconductor device which suppresses the generation of bubbles and which has a high reliability against the erosion of a conductive pattern.  
           [0016]    In order to attain the first object of the invention, according to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip having a pad; an insulating base which adheres to the semiconductor chip; a conductive pattern formed on the insulating base, the conductive pattern including a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to an outside electrode, and a wiring portion connecting the bonding portion and the pad portion; and an electrically floating island-like portion formed on the insulating base.  
           [0017]    According to the semiconductor device having the above structure, the uneven configuration can be alleviated which results from the presence and absence of the conductive layer by providing the electrically floating island-like portion on the insulating base. Consequently, the difference in the pressure distribution can be alleviated as compared with the conventional example, so that a difference in the adherence force between the insulating base and the chip can be reduced. Consequently, a semiconductor device having a stable adherence force can be obtained.  
           [0018]    In order to attain a first object of the invention, according to a second aspect of the invention, there is provided a semiconductor device comprising: a semiconductor chip having a pad; an insulating base which adheres to the semiconductor chip; and a conductive pattern formed on the insulating base, the conductive pattern including a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to an outside electrode, and a wiring portion connecting the bonding portion and the pad portion and having a tend portion with a different width.  
           [0019]    According to the semiconductor device having the above structure, the uneven configuration resulting from the presence and absence of the conductive pattern can be alleviated by providing the extended portion mutually different width on the wiring portion of the conductive pattern. Consequently, in the same manner as the first aspect of the invention, the difference in the pressure distribution can be alleviated as compared with the conventional example with the result that the adherence force between the tape and the chip can be reduced. Thus, the semiconductor device having a stable adherence can be obtained.  
           [0020]    In order to attain the second object, according to a third aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; an insulating base which adheres onto the semiconductor chip; a conductive pattern formed on the insulating base, the conductive pattern including a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to an outside electrode, and a wiring portion connecting the bonding portion and the pad portion; and a covering layer which covers the conductive pattern formed on the insulating base at least except for the bonding portion and the pad portion; wherein an intersection angle between the edge of the covering layer and the bonding portion is 90 degrees or more.  
           [0021]    According to the semiconductor device having the above structure, the covering layer less involves bubbles on the conductive pattern particularly in the vicinity of the bonding portion at the time of forming the covering layer by setting an intersection angle between the covering layer and the terminal portion to 90 degrees or more. Consequently, a semiconductor device which suppresses the generation of bubbles and which has a high reliability against the corrosion of the conductive pattern can be obtained.  
           [0022]    Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.  
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0023]    The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.  
         [0024]    [0024]FIG. 1A is a plan view showing a conventional TAB tape.  
         [0025]    [0025]FIG. 1B is a sectional view taken along the line  1 B- 1 B of FIG. 1A.  
         [0026]    [0026]FIG. 1C is a sectional view taken along the line  1 C- 1 C of FIG. 1A.  
         [0027]    [0027]FIGS. 2A, 2B and  2 C are sectional views showing a heat pressurizing step respectively.  
         [0028]    [0028]FIG. 3A is a plan view showing a conventional TAB tape.  
         [0029]    [0029]FIG. 3B is a sectional view taken along the line  3 B- 3 B of FIG. 3A.  
         [0030]    [0030]FIG. 4A is a plan view showing a semiconductor device according to a first embodiment of the present invention.  
         [0031]    [0031]FIG. 4B is a sectional view taken along the line  4 B- 4   b  of FIG. 4A.  
         [0032]    [0032]FIG. 4C is a sectional view showing the state after the completion of the device.  
         [0033]    [0033]FIGS. 5A, 5B,  5 C and  5 D are sectional views showing a method for manufacturing the semiconductor device according to the present invention respectively.  
         [0034]    [0034]FIG. 6A is a plan view showing a first basic pattern of the TAB tape provided in the semiconductor device according to the present invention.  
         [0035]    [0035]FIG. 6B is a sectional view taken along the line  6 B- 6 B of FIG. 6A.  
         [0036]    [0036]FIG. 6C is a sectional view taken along the line  6 C- 6 C of FIG. 5A.  
         [0037]    [0037]FIGS. 7A, 7B and  7 C are sectional views showing the heat pressurizing step respectively.  
         [0038]    [0038]FIGS. 8A, 8B,  8 C and  8 D are plan views showing basic patterns of an island-like portion respectively.  
         [0039]    [0039]FIG. 9A is a plan view showing a second basic pattern of the TAB tape provided in the semiconductor device according to the present invention.  
         [0040]    [0040]FIG. 9B is a sectional view taken along the line  9 B- 9 B of FIG. 9A.  
         [0041]    [0041]FIG. 9C is a sectional view taken along the line  9 C- 9 C of FIG. 9A.  
         [0042]    [0042]FIGS. 10A, 10B, and  10 C are sectional views showing the heat pressurizing step respectively.  
         [0043]    [0043]FIGS. 11A, 11B,  11 C and  11 D are plan views showing basic patterns of an expanded portion respectively.  
         [0044]    [0044]FIG. 12A is a plan view showing a third basic pattern of the TAB tape provided in the semiconductor device according to the present invention.  
         [0045]    [0045]FIG. 12B is a sectional view taken along the line  12 B- 12 B of FIG. 12A.  
         [0046]    [0046]FIGS. 13A and 13B are plan views showing a printing step respectively.  
         [0047]    [0047]FIGS. 14A and 14 b  are plan views showing basic patterns of a bonding portion respectively.  
         [0048]    [0048]FIG. 15 is a plan view showing a semiconductor device according to a reference example of the present invention.  
         [0049]    [0049]FIG. 16 is a plan view showing a semiconductor device according to a second embodiment of the present invention.  
         [0050]    [0050]FIG. 17 is a plan view showing a semiconductor device according to a third embodiment of the present invention.  
         [0051]    [0051]FIG. 18 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention.  
         [0052]    [0052]FIG. 19 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.  
         [0053]    [0053]FIG. 20 is a plan view showing a semiconductor device according to the present invention.  
         [0054]    [0054]FIG. 21 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0055]    Hereinafter, embodiments of the present invention will be explained by referring to the drawings. In the explanation, common portions are denoted by common reference numerals over all the drawings.  
         [0056]    (First Embodiment)  
         [0057]    [0057]FIG. 4A is a plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 4B is a sectional view taken along the line  4 B- 4 B of FIG. 4A.  
         [0058]    As shown in FIGS. 4A and 4B, a Cu pattern (a conductive pattern)  2  comprising copper (Cu) is formed on the surface of a polyimide (an insulating base)  1 . The Cu pattern  2  includes a wire bonding portion  2 WB, a ball pad portion  2 BP, and a wiring portion  2 WB. The ball pad portion  2 BP is arranged in a matrix-like configuration on a pad area  12  set approximately in the center of the polyimide tape  1 . The wiring portion  2 WR connects the wire bonding portion  2 WB and the ball pad portion  2 BP.  
         [0059]    On the main surface of the polyimide tape  1 , a solder resist layer (covering layer)  3  is formed. The solder resist layer  3  covers the Cu pattern  2  at least except for the wire bonding portion  2 WB, and the ball pad portion  2 BP. The polyimide tape  1  has an open hole  8  to which a pad  7  of a semiconductor chip  6  is exposed. The wire bonding portion  2 WB is connected to the pad  7  which is exposed to the hole  8  via a bonding wire  9  comprising, for example, gold (Au).  
         [0060]    On the rear surface of the polyimide tape  1 , an adhesive layer  4  is formed, and the polyimide tape  1  is connected to the semiconductor chip  6  via the adhesive layer  4 . An example of the adhesive agent of the layer  4  is an acryl-epoxy resin adhesive. In addition, a silicone resin adhesive or the like can be used.  
         [0061]    [0061]FIG. 4C is a sectional view showing a state after the completion of the semiconductor device.  
         [0062]    On the open hole  8 , a shield resin  10  is formed for shielding the bonding wire  9  and the pad  7  from the outside. Furthermore, on the ball pad portion  2 BP, for example, a solder bump (also referred to as a solder ball)  11  comprising solder is formed. The solder bump  11  constitutes an outside electrode of the semiconductor chip  6 . An example of the thickness of the polyimide tape  1  in this state is about 0.075 mm± 0.008 mm. An example of thickness of the adhesive agent layer  4  is 0.05 mm±0.01 mm. An example of the thickness of the chip  6  is 0.38 mm±0.02 mm.  
         [0063]    Furthermore, a solder bump  11 ′ formed on the peripheral area  13  on the outside of the pad area  12  is referred to as an option ball, and has a function of heightening the mechanical strength of the TAB type ball grid array semiconductor device.  
         [0064]    The solder bump (the option ball)  11 ′ is formed on the option pad portion  2 BP′, and the option pad portion  2 BP′ is formed on the peripheral area  13 .  
         [0065]    [0065]FIGS. 5A, 5B,  5 C and  5 D are sectional views showing a method for manufacturing the semiconductor device according to the present invention.  
         [0066]    In the beginning, as shown in FIG. 5A, there is prepared the polyimide tape  1  on which the Cu pattern  2  is formed.  
         [0067]    Next, as shown in FIG. 5B, a screen  51  having a window  50  corresponding to the solder resist layer formation pattern is allowed to come close to the Cu pattern  2 . Next, a squeegee  52  is allowed to move in a direction shown by an arrow so that a paste-like solder resist  53  is printed on the tape  1  via the screen  51  thereby forming the solder resist layer  3 . As a consequence, the TAB tape is completed.  
         [0068]    Next, as shown in FIG. 5C, the semiconductor chip  6  is placed on a lower mold  22 . Next, after the position of the TAB tape having the protection tape  5  peeled off and the position of the chip  6  are corrected, an upper mold  23  is allowed to come down so that the TAB tape is heat pressurized to the chip  6 . As a consequence, the chip  6  is adhered to the TAB tape.  
         [0069]    Next, as shown in FIG. 5D, the wire bonding portion  2 WB of the Cu pattern  2  is connected to the pad  7  of the chip  6  with the bonding wire  9 . Next, the bonding wire  9  and the pad  7  are shielded with resin  10 , and a solder bump  11  is formed on the ball pad portion  2 BP with the result that the semiconductor device according to the present invention is completed.  
         [0070]    The semiconductor device according to the first embodiment of the semiconductor device includes mainly three elements.  
         [0071]    The elements will be explained in order hereinafter.  
         [0072]    (First element)  
         [0073]    [0073]FIG. 6A is a plan view showing a first basic pattern of the TAB tape provided in the semiconductor device according to the present invention. FIG. 6B is a sectional view taken along the line  6 B- 6 B of FIG. 6A. FIG. 6C is a sectional view taken along the line  6 C- 6 C of FIG. 6A.  
         [0074]    The Cu pattern  2  in the first embodiment has, as shown in FIGS. 6A through 6C, an electrically floating island-like portion  2 IL in addition to the wire bonding portion  2 WB, the ball pad portion  2 BP, the wiring portion  2 WR. The island-like portion  2 IL is arranged between the wiring portions  2 WR or ball pad portions  2 BP.  
         [0075]    The Cu pattern  2  has the island-like portion  2 IL so that the area of a convex portion  21  increases and the uneven configuration resulting from the presence and the absence of the Cu pattern  2  can be alleviated. As a consequence, at the time of the heat pressurizing step shown in FIGS. 7A through 7C, a difference in the pressure distribution applied to the chip  6  can be alleviated as compared, for example, with the conventional example shown in FIG. 2C. As a consequence, the adherence force between the TAB tape and the chip  6  can be made small with the result that a semiconductor device having a stable adherence can be obtained.  
         [0076]    It is preferable that a region for arranging the island-like portion  2 IL is arranged along the peripheral area  13  at least outside of the pad area  12 , namely along the peripheral portion of the chip  6 .  
         [0077]    In the peripheral portion of the chip  6 , an adherence with the TAB tape is heightened by arranging the island-like portion  2 IL in the peripheral area  13  in this manner, a stronger pressure endurance can be obtained against the separation.  
         [0078]    [0078]FIGS. 8A, 8B,  8 C and  8 D are plan views showing basic patterns of the island-like portion respectively.  
         [0079]    By the way, when the Cu pattern  2  has an island-like portion  2 IL, it is feared that the parasitic capacity of the wiring portion  2 WR increases, and the electric characteristic of the wiring portion  2 WR, particularly, the RCL characteristic is affected.  
         [0080]    This influence can be minimized by changing the design of the island-like portion  2 IL into a stripe pattern shown in FIG. 8B, a checker pattern shown in FIG. 8C and a lattice-like (matrix-like) pattern shown in FIG. 8D, instead of a planer pattern shown in FIG. 8A. For example, patterns shown in FIGS. 8B through 8D have a gap therebetween. For the portion of this gap, for example, the parasitic capacity of the wiring portion  2 WR can be reduced so that the electric characteristic of the wiring portion  2 WR, particularly, the influence upon the RCL characteristic can be minimized. Furthermore, by changing the design of the island-like portion  2 IL, the electric characteristic of the wiring portion  2 WR can be adjusted.  
         [0081]    (Second element)  
         [0082]    [0082]FIG. 9A is a plan view showing a second basic pattern of the TAB tape provided in the semiconductor device according to the present invention. FIG. 9B is a sectional view taken along the line  9 B- 9 B of FIG. 9A. FIG. 9C is a sectional view taken along the line  9 C- 9 C of FIG. 9A.  
         [0083]    The Cu pattern  2  in the first embodiment has, as shown in FIGS. 9A through 9C, has a tend portion  2 WRW having a widened width at least on a portion of the wiring portion  2 WR. The tend portion  2 WRW reduces a gap D between the wiring portions  2 WRW and the ball pad portions  2 BP.  
         [0084]    The Cu pattern  2  has a tend portion  2 WRW so that the area of the convex portion  21  can be increased in the same manner as the case in which the island-like portion  2 IL is provided. Consequently, at the time of heat pressurizing step shown in FIGS. 10A through 10C, a difference in the pressure distribution applied to the chip  6  can be alleviated as compared with conventional example shown in FIG. 2C. Consequently, a difference in the adherence between the TAB tape and the chip  6  can be made small with the result that a semiconductor device having a stable adherence can be obtained.  
         [0085]    Preferably, a portion for providing the tend portion  2 WRW is arranged at least along an outside peripheral area  13  of a pad area  12 , namely along the peripheral portion of the chip  6 .  
         [0086]    Furthermore, the tend portion  2 WRW can be obtained by expanding, for example, the width of the wiring portion  2 WR with the result that there is an advantage that the tend portion  2 WRW can be easily provided on a portion where the island-like portion  2 IL can be provided with difficulty, and the wiring density is high.  
         [0087]    In the case where the expanded portion  2 WRW is provided on a portion where the wiring density is dense, a large tend portion  2 WRW is required, and the capacity of the wiring portion  2 WR largely increases.  
         [0088]    The island-like portion  2 IL and the tend portion  2 WRW may be respectively provided appropriately in consideration of the electric characteristic of the semiconductor device. One example of an appropriate arrangement is such that, as shown in FIG. 4A, the island-like portion  2 IL is provided in the peripheral portion  13  where the wiring density is relatively rough, and the tend portion  2 WRW is provided on a pad area  12  where the wiring density is relatively dense.  
         [0089]    [0089]FIGS. 11A, 11B,  11 C and  11 D are plan views showing basic patterns of the expanded portion respectively.  
         [0090]    The configuration of the basic patterns of the tend portion  2 WRW is, as shown in FIG. 11A, a fin-like configuration which projects either to one side or both sides of the wiring portion  2 WRW, or the fin-like configuration which is expanded of the wiring portion. The expanded portion  2 WRW having a fin-like configuration is provided on route of the wiring portion  2 WR so as to reduce a gap D between adjacent wiring portion  2 WR as shown in FIG. 11A. Otherwise, as shown in FIG. 11B, the fin-like configuration is provided so as to extend between separate Cu patterns  2  so that a gap between the ball pad portions of these separate Cu pattern  2  is reduced. Otherwise, as shown in FIG. 11C, the fin-like expanded portion  2 WRW is provided so as to reduce the gap between the wiring portions  2 WR. Furthermore, the fin-like tend portion  2 WRW may be provided at the end of the wiring portion  2 WR as shown in FIG. 11D.  
         [0091]    As the hardness of such tend portion  2 WRW and the Cu pattern  2  including the island-like portion  2 IL, Vickers hardness of 170 HV is preferable. Setting the hardness to such level is based on the viewpoint of suppressing the collapse of the Cu pattern  2 .  
         [0092]    Besides, one example of the tend portion  2 WRW according to the present invention, and the wiring density in the case where the Cu pattern  2  including the island-like portion  2 IL is provided is Cu pattern area/tape area=68.5%. The conventional wiring density is Cu pattern area/tape area=45.7%. From this viewpoint, when the wiring density (Cu pattern area/tape area) exceeds the wiring density=45.7%, the adherence is heightened as compared with the conventional device.  
         [0093]    (Third element)  
         [0094]    [0094]FIG. 12A is a plan view showing a third basic pattern of the TAB tape provided in the semiconductor device according to the present invention. FIG. 12B is a sectional view taken along the line  12 B- 12 B of FIG. 12A.  
         [0095]    With respect to the Cu pattern  2  according to the first embodiment, as shown in FIGS. 12A and 12B, an intersection angle θ between the wire bonding portion  2 WB and an edge of the solder resist layer  3  is maintained at 90 degrees or more. The bubbles are hardly involved at the time of printing in the Cu pattern  2  in the vicinity of the wire bonding portion  2 WB as compared with the conventional example in which a portion is generated which has an intersection angle of 90 degrees or less shown in FIG. 3A by maintaining the intersection angle θ of 90 degrees. As a result of the fact that the bubbles are involved with difficulty, the bubbles are generated with difficulty in the solder resist layer  3  and between the solder resist layer  3  and the polyimide tape  1  so that the situation of the corrosion of the Cu pattern  2  is suppressed with the lapse of time. As a consequence, a semiconductor device having a high reliability against the erosion of the conductive pattern can be obtained.  
         [0096]    [0096]FIGS. 13A and 13B are plan views showing an example of a step of printing a solder resist onto the tape  1  having the above Cu pattern  2 .  
         [0097]    As shown in FIG. 13A, a screen  51  having a window  50  corresponding to the solder resist layer formation pattern is allowed to come close to the Cu pattern  2 .  
         [0098]    Next, as shown in FIG. 13B, the squeegee  52  is moved along the direction of an arrow in FIG. 13B. Specifically, the squeegee  52  is moved from the wire bonding portion  2 WB to the wiring port ion  2 WR, with the result that the paste-like solder resist layer  53  is printed on the tape  1  via the window  50  of the screen  51 . As a consequence, the solder resist layer  3  is formed where bubbles are generated with difficulty.  
         [0099]    [0099]FIGS. 14A and 14B are plan views showing the basic patterns of the bonding portion respectively.  
         [0100]    The Cu pattern  2  shown in FIG. 14A is a case in which the intersection angle θ is maintained at 90 degrees. The Cu pattern  2  shown in FIG. 14B is a case in which intersection angle θ is maintained at 90 degrees or more. In the case where the intersection angle θ is maintained at 90 degrees or more, the configuration of the wire bonding portion  2 WB may be formed in a tapered configuration toward the end.  
         [0101]    Next, another embodiment of the present invention will be explained.  
         [0102]    (Second Embodiment)  
         [0103]    [0103]FIG. 15 is a plan view showing a semiconductor device according to a reference example of the present invention. FIG. 16 is a plan view showing a semiconductor device according to a second embodiment of the present invention.  
         [0104]    As shown in FIG. 16, the semiconductor device according to the second embodiment is an example in which an island-like portion  2 IL is further provided on the Cu pattern  2  in the reference example shown in FIG. 15. The island-like portion  2 IL of the embodiment is provided outside of the pad area  12 , namely, in the peripheral area  13 .  
         [0105]    Incidentally, the second embodiment is an example in which the option pad  2 BP′ shown in the first embodiment is not provided.  
         [0106]    (Third Embodiment)  
         [0107]    [0107]FIG. 17 is a plan view showing a semiconductor device according to a third embodiment of the present invention.  
         [0108]    As shown in FIG. 17, the semiconductor device according to the third embodiment is an example in which the tend area  2 WRW is further provided outside of the pad area  12 , namely, on the Cu pattern  2  of the reference example. The tend portion  2 WRW of the embodiment is provided outside of the pad area  12 , namely the peripheral area  13 .  
         [0109]    (Fourth Embodiment)  
         [0110]    [0110]FIG. 18 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention.  
         [0111]    As shown in FIG. 18, the semiconductor device according to the fourth embodiment of the present invention is an example in which the island-like portion  2 IL and the tend portion  2 WRW are further provided respectively on the Cu pattern  2  of the reference example shown in FIG. 15. The island-like portion  2 IL and the tend portion  2 WRW are provided respectively on the outside of the pad area  12 , namely in the peripheral area  13 .  
         [0112]    (Fifth Embodiment)  
         [0113]    [0113]FIG. 19 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.  
         [0114]    As shown in FIG. 19, the semiconductor device according to the fifth embodiment of the present invention is an example in which the tend portion  2 WRW is provided on the Cu pattern  2  of the reference example shown in FIG. 15. And, at the same time, the tend portion  2 WRW is provided in the pad area  12 , and the peripheral area  13  respectively. In particular, in the fifth embodiment, the expanded portion  2 WRW is provided over the while pad area  12  and the peripheral area  13 .  
         [0115]    (Sixth Embodiment)  
         [0116]    [0116]FIG. 20 is a plan view showing a semiconductor device according to the present invention. FIG. 21 is a plan view showing the semiconductor device according to the sixth embodiment of the present invention. Incidentally, FIGS. 20 and 21 are plan views showing the semiconductor device as seen from the side of the chip  6  not from the side of the tape  1 .  
         [0117]    As shown in FIG. 20, when the semiconductor devices according to the first to the fifth embodiments are observed from the side of the chip  6 , the shield resin  10  is present only on the periphery of the open hole  8  of the tape  1 .  
         [0118]    In the sixth embodiment, as shown in FIG. 21, the shielded resin  10  is allowed to present on the whole periphery of the chip  6  so that the adherence of the chip  6  and the tape  1  can be further stabilized.  
         [0119]    In the above description, the present invention has been explained with respect to the first to the sixth embodiments of the present invention. The present invention is not restricted thereto, and the invention can be modified in various ways within the scope of not departing from the gist of the invention.  
         [0120]    For example, as a conductive pattern  2 , copper (Cu) is given, copper can be replaced with copper alloy or other conductive material. Furthermore, in the case where copper is replaced with copper alloy or other conductive material, preferably, the hardness may be at least 170 HV or more.  
         [0121]    Furthermore, as a pad arrangement of the semiconductor chip, an example is shown wherein the pad is arranged on the periphery of the chip, and on the center of the chip. The pad arrangement is provided either on the periphery of the chip or in the center of thee chip.  
         [0122]    Furthermore, as a semiconductor product formed in the semiconductor chip, products which requires a compact package such as a SRAM, FLAS, H-EEPROM, DRAM, mixedly mounted DRAM, CPU or the like are particularly preferable.  
         [0123]    Furthermore, the first to the sixth embodiments can be practiced as a single entity. However, the embodiments can be practiced by a combination of the embodiments in various manners.  
         [0124]    As has been described above, according to the present invention, a semiconductor device can be provided which has a reduced difference in adherence force between the tape and the chip, and which has a stable adherence.  
         [0125]    Furthermore, a semiconductor device can be provided which suppresses the generation of bubbles and which has a high reliability against the erosion of the conductive pattern.  
         [0126]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.