Abstract:
A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure includes a plurality of lines, which extend along the second orientation, and a plurality of conductive pads that are respectively disposed on the lines. The conductive pads are distributed along the first orientation and staggered along the second orientation. Each line can shift away from the adjacent conductive pad on the first orientation. Thus, the LCD chip has a better conductivity and a thinner dimension under the precision of the conventional machines.

Description:
This application claims the benefits of the priority based on Taiwan Patent Application No. 096112142 filed on Apr. 4, 2007; the disclosure of which is incorporated by reference herein in its entirety. 
     CROSS-REFERENCES TO RELATED APPLICATIONS 
     Not Applicable 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a layout structure for chip coupling, and more particularly to a layout structure that can ensure an electrical connection with a chip and thereby reduce the chip size, under the precision of the conventional machine. 
     2. Descriptions of the Related Art 
     Liquid crystal displays (LCDs) have replaced conventional displays and become mainstream products due to their low power consumption, light weight, low radiation and portability. In addition to key parts, such as a backlight module, liquid crystals and a color filter, an integrated circuit (IC) chip and a layout structure of the display panel are provided for converting external signals into control signals to control the luminance of each pixel. 
     In a conventional LCD  10 , as depicted in  FIG. 1 , a layout structure  13  is formed on a glass substrate  11 . An IC chip  15  is disposed at the lowermost edge of the glass substrate  11  to electrically connect with the layout structure  13  and connect to a flexible printed circuit (FPC)  17  on the other side. During operation, external signals are transferred through the FPC  17  to the IC chip  15  and are converted into control signals to control the luminance of each pixel through the layout structure  13 . 
     The most common conventional technology used for bonding the IC chip  15  to the glass substrate  11  is the chip on glass (COG) technology. By the COG technology, the IC chip  15  with bumps is directly bonded onto the layout structure  13  of the glass substrate  11 .  FIGS. 2A and 2B  illustrate two partially enlarged schematic views of the layout structure  13  disposed on the glass substrate  11  and connected with the IC chip  15 . The layout structure  13  comprises a plurality of lines  131  and a plurality of conductive pads  133  corresponding to the bumps on the IC chip  15 . When the IC chip  15  is overlaid onto the layout structure  13 , the bumps of the IC chip  15  will be correspondingly bonded with the conductive pads  133  of the layout structure  13  to establish an electrical conduction state therebetween through the conductive particles. 
     However, there are still issues with the aforesaid structure. Still referring to  FIGS. 2A and 2B , a conventional conductive pad layout design for dual-line routing is depicted in  FIG. 2A , while a conventional conductive pad layout design for triple-line routing is depicted in  FIG. 2B . Typically, in conventional technology, the conductive pads  133  are approximately the same in size as the bumps of the IC chip  15  so that the bumps can come into contact exactly with the conductive pads  133  after the bonding process. However, if the preciseness of the machine is not enough, the bumps may shift from the desired position. Such a shift will lead to a reduced contact area between the bumps and the conductive pads  133 , thus, making the electrical conductivity therebetween inadequate. Furthermore, such bumps may come into contact with adjacent lines  131 , eventually leading to short-circuits or product failures. 
     Consequently, in conventional technology, an adequate spacing is maintained between the conductive pads  133  and their adjacent lines  131  to prevent the bumps from coming into contact with the adjacent lines  131  due to the IC chip  15  shift during the bonding process. During the manufacturing process, a finer spacing between the individual lines  131  or between the individual conductive pads  133  is preferred to reduce the size of the final product. However, if there is a shift during the chip bonding process, then a large spacing between the conductive pads  133  and the adjacent lines  131  would be preferred. Thus, these two objectives contradict each other, making it difficult for the designers to account for both situations. In addition, the spacing maintained between the conductive pads  133  and the lines  131  is estimated according to the machine precision, the inaccuracy of the feed materials or the process stability criteria evaluated by the manufacturers. Thus, the machine precision, the inaccuracy of the feed materials or the process stability criteria evaluated by the manufacturers will also affect the IC chip  15  design dimensions. 
     In the conventional process, the IC chip  15  has to be made with excessive footprints, which causes the display area to shrink correspondingly, due to the limitations of the stability and manufacturing capability of the bonding machine. As a result, the IC chip  15  is undesirable for the miniaturization of the LCD products. On the contrary, if a smaller IC chip  15  is desired for the LCD, a bonding machine of higher precision will become a necessity, which will increase the manufacturing cost of the LCD. 
     Given the above, a novel layout structure that meets the manufacturing process criteria under the precision of conventional bonding machines needs to be developed in this field. 
     SUMMARY OF THE INVENTION 
     One objective of this invention is to provide a layout structure for chip coupling. The lines in the layout structure are distributed non-linearly; that is, the lines can shift in accordance with the adjacent conductive pads. In this way, the safety margin can be improved to tolerate the chip shift due to limited precision of the bonding machine. In addition, the chip bonding process can satisfy the process criteria using the existing bonding machine. Furthermore, the short circuits that arise from the contact between the bumps of the IC chip and the lines are prevented. 
     Another objective of this invention is to provide a layout structure for chip coupling. Since the lines are able to shift, the layout structure allows a further enlargement of the conductive pads. As a result, the electrical conduction between the bumps of the IC chip and the conductive pads can be ensured during the chip bonding process to maintain an effective electrical conductivity therebetween. The minimum compression area can also be more effectively utilized. In this way, the bonding area can be enlarged without having to design larger bumps. 
     Yet a further objective of this invention is to provide a layout structure for chip coupling. Since the bumps shrink in size and the aspect ratio thereof is adjustable, the footprint of the IC chip is reduced, and therefore, the chip is miniaturized. Accordingly, a wafer of the same size can yield more chips than before, thus, further lowering the manufacturing costs. 
     To achieve the aforementioned objectives, the present invention discloses a layout structure disposed on the substrate of a liquid crystal display (LCD) for chip coupling. The first and second orientations that are substantially perpendicular to each other can be defined on the substrate. The layout structure comprises a plurality of lines that are substantially parallel to each other and extend along the second orientation. There is also a plurality of conductive pads respectively disposed on the lines. The adjacent conductive pads are distributed in sequence along the first orientation and staggered along the second orientation. Each line has a shifting portion that departs from the adjacent conductive pad on the first orientation. The shifting portion of the lines comprises a main section that is disposed substantially parallel to the second orientation and the two connecting sections connecting the two ends of the main section respectively. There is an included angle substantially greater than 90 degrees that is formed between the main section and the connecting sections. 
     The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic view of a conventional liquid crystal display; 
         FIG. 2A  is a schematic view of a layout structure in a conventional dual-line routing design; 
         FIG. 2B  is a schematic view of a layout structure in a conventional triple-line routing design; 
         FIG. 3  is a schematic view of a preferred embodiment of the present invention; and 
         FIG. 4  is a schematic view of another preferred embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       FIG. 3  illustrates a layout structure  20  that is disposed on the substrate of a liquid crystal display (LCD) for chip coupling. For illustration convenience, the first orientation X and second orientation Y that are substantially perpendicular to each other can be defined in the substrate. The layout structure  20  of the present invention has at least one unit  30  comprising a plurality of lines and conductive pads. In this embodiment, the conductive pads and bumps on the IC chip are approximately of the same area and can be electrically connected together once they are bonded together. 
     In particular, the plurality of lines comprise of a first line  41 , a second line  42  and a third line  43 , all substantially parallel to each other and extending along the second orientation Y. The plurality of conductive pads comprise of a first conductive pad  51 , a second conductive pad  52  and a third conductive pad  53  that are disposed on the first line  41 , the second line  42  and the third line  43 , respectively. With respect to the distribution of the conductive pads, the first conductive pad  51 , the second conductive pad  52  and the third conductive pad  53  are distributed in sequence along the first orientation X and staggered along the second orientation Y to form a conductive pad layout design for triple-line routing, as illustrated in  FIG. 3 . 
     The first conductive pad  51  will be used as an example to describe the bonding between the conductive pads and lines. The first conductive pad  51  has two connecting ends  54   a ,  54   b  that are independently disposed on both sides along the second orientation Y and are staggered along the first orientation X to connect with the line  41  respectively. Other conductive pads and lines of the present invention are similar and will not be described herein. 
     In the preferred embodiments of the present invention, each line has a shifting portion and is able to shift from the adjacent conductive pad along the first orientation X. As illustrated in  FIG. 3 , the first line  41 , the second line  42  and the third line  43  respectively have a first shifting portion  61 , a second shifting portion  62  and a third shifting portion  63  departing from the adjacent conductive pads along the first orientation X. 
     For example, the first shifting portion  61  comprises a main section  611  substantially disposed parallel to the second orientation Y, and two connecting sections  612 ,  613  respectively connecting with the two ends of the main section  611 . More specifically, an included angle θ greater than 90 degrees can be formed between the main section  611  and the connecting sections  612 ,  613 . In the preferred embodiments, the included angle θ ranges from 90 to 180 degrees. In other words, in unit  30 , the first line  41  has a first shifting portion  61  departing from the adjacent second conductive pad  52 , the second line  42  has second shifting portions  62  departing from both the adjacent first conductive pad  51  and the third conductive pad  53 , and the third line  43  has a third shifting portion  63  departing from the adjacent second conductive pad  52 . 
     It should be noted that, as shown in  FIG. 3 , the pad layout design of the triple-line routing features two adjacent conductive pads for each line, one on each side. Certainly, each line has two shifting portions that respectively depart from the two adjacent conductive pads along the first orientation X. 
     In this embodiment, the line shifts allow the spacing between the lines and their adjacent conductive pads to be substantially enlarged, and thus, there is a higher tolerance when the chip shifts due to the imprecision of the machine. 
     In this embodiment, the adjacent lines that are substantially parallel to each other define a first interval D 1  therebetween. Each of the conductive pads and the shifting portions of their adjacent lines define a second interval D 2  therebetween. Likewise, the adjacent shifting portions define a third interval D 3  therebetween, and the adjacent conductive pads define a fourth interval D 4  therebetween along the second orientation Y. For example, in the preferred embodiments, the first interval D 1  is about 16 μm, the second interval D 2  is about 13 μm, the third interval D 3  is about 4 μm, and the fourth interval D 4  is about 40 μm. In other words, the proportion of the second interval D 2  to the first interval D 1  is about 1.3, the proportion of the third interval D 3  to the first interval D 1  is about 0.4, and the proportion of the fourth interval D 4  to the second interval D 2  is about 3. 
     In addition, each of the conductive pads can be defined with a transverse dimension L 1  along the first orientation X and a lengthwise dimension L 2  along the second orientation Y. For example, in the preferred embodiments, the transverse dimension L 1  is about 19 μm, and the lengthwise dimension L 2  is about 126 μm. In other words, the proportion of the lengthwise dimension L 2  to the transverse dimension L 1  is about 6.63. 
     Another preferred embodiment of the present invention is shown in  FIG. 4 . The main structure of this embodiment is similar to the aforesaid embodiment and will not be further described. In this embodiment, the conductive pads can be appropriately enlarged so that even if the bumps slightly shift during the chip bonding process due to the imprecision of the machine, an effective conduction can still be established between the bumps and the conductive pads. Furthermore, since the conductive pads have a larger area than that of the bumps, there is no need to design large bumps to ensure an electrical conduction in the conventional technologies. Moreover, the dimensions of the IC chip along the second orientation Y can be reduced through a flexible design of the bump size, such as adjusting the length and transverse of the bumps. 
     In this embodiment, the first interval D 1  is still about 10 μm, the second interval D 2  is about 5 μm, the third interval D 3  is about 5 μm, and the fourth interval D 4  is about 20 μm. In other words, the proportion of the second interval D 2  to the first interval D 1  is about 0.5, the proportion of the third interval D 3  to the first interval D 1  is about 0.5, and the proportion of the fourth interval D 4  to the second interval D 2  is about 4. 
     In addition, in the preferred embodiments, the transverse dimension L 1  is about 34 μm, and the lengthwise dimension L 2  is about 98 μm. In other words, the proportion of the lengthwise dimension L 2  to the transverse dimension L 1  is about 2.88. It should be noted that these dimension values are intended only to illustrate and not to limit the present invention. 
     It is apparent from the above disclosure that the present invention exhibits a higher tolerance towards the imprecision of the machine during the chip bonding process due to the lines ability to shift. In addition, the bumps are less likely to come into contact with the other lines. Furthermore, the line shifting ability can enlarge the area of the conductive pads. As a result, the bumps can be adjusted simultaneously to reduce the size of the IC chip and therefore lower the manufacturing costs. 
     The above disclosure is related to the detailed technical contents and inventive features thereof. People skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.