Abstract:
A common Baker Clamp includes diodes having predetermined reverse-recovery times for responding to a signal having a high frequency on the order of 100 kHz. A pair of anti-parallel diodes coupled between an input terminal and a first output terminal are each characterized by a reverse-recovery time on the order of 2μs. A third diode is coupled between the input terminal and a second output terminal and is characterized by a reverse-recovery time on the order of 200 ns.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a circuit for improving the switching time of a power transistor, and in particular, to a circuit for maintaining a switching transistor in a quasi-saturation condition. 
     2. Description of the Prior Art 
     In commonly used switching circuits such as inverters, when two or more power transistors are utilized, there is a potential condition of &#34;simultaneous conduction&#34;, wherein two power transistors are simultaneously in the &#34;ON&#34; state causing a direct short across the power line. This simultaneous conduction phenomenon is due to the storage time (t s ) of the power transistor. Storage time is the delay between the time a &#34;turn-off&#34; signal is applied to the transistor and the time that the transistor actually begins to turn off. Because this storage time is variable, even among transistors of the same type, it is usually difficult to ensure that a two-transistor circuit, which is supposed to switch alternately, will actually prevent conditions of simultaneous conduction, i.e., one transistor is turning &#34;ON&#34; while the other is still partially &#34;ON&#34;. 
     One solution to the problem is to reduce the value of t s  to virtually zero by preventing saturation in the power transistor. A circuit commonly known as a Baker Clamp has been used for such a purpose. However, such circuits discussed in the literature do not specify key component characteristics (performance parameters). For example, it is not clear which of the diodes utilized in the Baker Clamp should be fast and which of them can be slow, especially in high-frequency operation. Nor is it clear that particular benefits are derived from specifying such characteristics. In addition, the stray inductance caused by the wires of the Baker Clamp coupled to the power transistor degrade the maximal recovery time (t r ) and turn-off time (t f ) in the power transistor. 
     SUMMARY OF THE INVENTION 
     An inverter circuit having an input and two outputs for switching a transistor in response to a high-frequency signal comprises first and second diode means coupled in anti-parallel between the input terminal and an output terminal. A third diode is coupled between the input terminal and the other output terminal. The first and second diode means are each characterized by a reverse-recovery time on the order of 2μs and the third diode means is characterized by a reverse-recovery time on the order of 200 ns in order that the circuit will best respond to the high-frequency signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a schematic of a circuit according to the teachings of the present invention. 
     FIG. 2 shows a preferred embodiment of the circuit of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows an inverter circuit 10 within the dashed lines 11 according to the teachings of the present invention. The inverter circuit 10 operates in the Class D (switching) mode, is capable of operating in the 20 KHz to 100 KHz range of input signal frequencies, and can switch currents of 50 to 60 amperes at 300 volts. The circuit 10 includes an input terminal 31 and output terminals 32 and 33. In FIG. 1, a transistor 40, for example, of the type D60T includes a collector 41 coupled to the output terminal 32, a base 43 coupled to the output terminal 33, and an emitter 45 coupled to ground. A transformer 47 is included for coupling a signal from a signal source 49 to the circuit input 31 and thereby providing a base current for the transistor 40. The base current can be provided by, for example, a circuit including Ferranti ZN1066 switching regulator control and drive circuit. The oscillator for the ZN1066, that is the signal source 49, is adjustable and is capable of driving 120 mA. 
     The circuit 10 includes a diode means D 1  for providing a voltage drop to raise the transistor 40 out of saturation. Commonly, the diode means D 1 , includes two or more series-coupled diodes. However, a trade off in performance is required in determining the number of diodes for diode means D 1 . Typically, the more diodes in series, the lower the storage time and the faster the switching time, but the greater the power dissipation. On the other hand, fewer diodes in series result in a comparatively higher storage time and, thereby, a slower switching time. It is preferred that each diode in the diode means D 1  have a reverse-recovery time t rr  on the order of 2 μs in order that the circuit 10 will best respond to the higher frequencies from the signal source 49 on the order of 100 kHz contemplated in the teachings of the present invention. 
     The circuit 10 also includes a diode means D 2  coupled in anti-parallel to the diode means D 1  for providing a path for turn-off current. The diode means D 1  and D 2  are coupled together such that the anode of the diode means D 1  and the cathode of the diode means D 2  are coupled to a node 21 and such that the anode of the diode means D 2  and the cathode of the diode means D 1  are coupled to a node 23. It is preferred that the diode means D 2  have a reverse-recovery time on the order of 2 μs in order that the circuit 10 will best respond to the higher frequencies from the signal source 49 on the order of 100 kHz contemplated in the teachings of the present invention. The reverse-recovery time of both the diode means D 1  and D 2  may not be much slower than 2 μs without deteriorating the performance of the circuit 10 at the contemplated frequencies. The reverse-recovery time of both the diode means D 1  and D 2  may be faster than 2 μs. However, according to the teachings of the present invention, the reverse-recovery time of the diode means D 1  and D 2  may be relatively slow, and the efficient operation of the circuit 10 at the frequencies contemplated does not require a reverse-recovery time any faster than 2 μs for the diode means D 1  and D 2 . Moreover, the use of a diode having a reverse-recovery time faster than 2 μs may unnecessarily increase the total cost of the circuit 10. 
     A diode means D 3  is coupled between the node 21 and the output terminal 32 such that the cathode is coupled to the terminal 32 and the anode is coupled to the node 21. It is preferred that the diode means D 3  have a reverse-recovery time on the order of 200 ns in order that the circuit 10 will best respond to the higher frequencies from the signal source 49 on the order of 100 kHz contemplated in the teachings of the present invention. 
     A preferred embodiment of the invention is shown in FIG. 2. Similar reference characters are used to designate like elements as described in FIG. 1. FIG. 2 shows a non-conductive substrate material 60, for example berylia or alumina, on which is eteched a pattern of metal deposits and strips for connecting the circuit elements shown in FIG. 1. A preferred metal for connecting the circuit elements is copper. Generally, the copper connections in FIG. 2 can be formed by placing a silk screen or photo-resist screen on a copper-clad surface of a printed circuit board and etching out the unwanted copper thereby leaving the copper circuit pattern as shown in FIG. 2. Diodes D 1  through D 3  can be, for example, diode chips placed on appropriate pads and soldered in order to connect the bottom side of the chips to the copper circuit pattern. Interconnecting wiring can be ultrasonically bonded or soldered in order to connect the top side of the chips to the copper circuit pattern. For example, diode chips D 1  and D 3  are soldered on the bottom (cathode) side at node 23; the top anode side of each diode chip D 1  and D 3  is wired to the node 21. The diode chip D 2  is soldered on the bottom (cathode) side at node 21 and the top (anode) side thereof is wired to the node 23. Similar to diode chips D 1 , D 2 , and D 3 , capacitor C 1  can be a capacitor chip placed on an appropriate pad and connected in a manner similar to that for diodes D 1  -D 3 . For example, capacitor chip C 1  is soldered on one (bottom) side on a pad connected to node 23; the other (top) side of the capacitor chip C 1  is wired to a pad connected to the terminal 31. As shown in FIG. 2, the capacitance C 1  can be variably increased by adding an external capacitor C 2  in parallel with the capacitor C 1 . In order to connect the capacitor C 2  in parallel with the capacitor C 1  copper pads 51 and 52 are formed on or near an edge 62 of the substrate 50, between which copper pads 51 and 52 is coupled the capacitor C 2 . The copper pads 51 and 52 are coupled to copper pads 53 and 54, respectively, by wiring connections 55 and 56, respectively. 
     The resistor R 1  of FIG. 2 is a thick-film resistor which can be formed by depositing a thick-film resistor paste between the nodes 32 and 21 and then trimming the paste to provide the desired resistivity. The capacitor C 1  can be a capacitor chip which can be soldered on in much the same manner as the diodes D 1  and D 4  are soldered on.