Abstract:
An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to Analog-to-Digital Converters (ADC), and more particularly to a dual-use comparator for a multi-stage ADC. 
       BACKGROUND OF THE INVENTION 
       [0002]    Many types of Analog-to-Digital Converters (ADC&#39;s) have been used for a wide variety of applications. Flash ADC&#39;s compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC&#39;s use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC&#39;S, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline. 
         [0003]    Algorithmic, re-circulating, or recycling ADC&#39;s use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage. 
         [0004]      FIG. 1  shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR  302  receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR  302  may first be 0.5, then 0.25, then 0.32, then 0.28, then 0.30, then 0.31, then 0.315, then 0.313, then 0.312, when comparing to a VIN of 0.312 volts. SAR  302  outputs the current register value to digital-to-analog converter (DAC)  300 , which receives a reference voltage VREF and converts the register value to an analog voltage VA. 
         [0005]    The input analog voltage VIN is applied to sample-and-hold circuit  304 , which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit  304  is applied to the inverting input of comparator  306 . The converted analog voltage VA is applied to the non-inverting input of comparator  306 . 
         [0006]    Comparator  306  compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR  302  is too high. The register value in SAR  302  can then be reduced. 
         [0007]    When the converted analog voltage VA is below the sampled input voltage, comparator  306  generates a low output to SAR  302 . The register value in SAR  302  is too low. The register value in SAR  302  can then be increased for the next cycle. 
         [0008]    The register value from SAR  302  is a binary value of N bits, with D(N−1) being the most-significant-bit (MSB) and D 0  being the least-significant-bit (LSB). SAR  302  can first set the MSB D(N−1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N−2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR  302  to control sequencing. 
         [0009]    Comparator  306  can be replaced with a series of pre-amplifier stages and a final latch.  FIG. 2A  is a response graph of pre-amplifier and latch stages. The pre-amplifier stages have a negative response shown by curve  312 , while the final latch has a positive response as shown by curve  310 . For low voltages, curve  312  is above and to the left curve  310 , indicating that the pre-amplifiers require less time to achieve the same VOUT voltage than the latch. However, for higher VOUT voltages, curve  310  is above curve  312 , indicating that for larger values of VOUT, the latch can achieve these larger voltage outputs much faster than the pre-amplifiers. 
         [0010]      FIG. 2B  shows a series of pre-amplifiers and a final latch. Pre-amplifier stages  320 ,  322 ,  324 ,  326 ,  328  are amplifiers that boost the voltage difference between VIN and VA. Especially near the end of comparison when the LSB is being set, the difference between VIN and VA can be quite small. This voltage difference is gradually increased by the pre-amplifier stages until the final stage. Latch stage  330  latches this voltage difference to generate the compare signal that is fed back to SAR  302 . Thus stages  320 - 330  replace comparator  306  of  FIG. 1 . 
         [0011]    By combining a series of pre-amplifier stages with the positive response of the final latch, a fast response time can be achieved. The pre-amplifier stages can gradually amplify and enlarge the voltage difference between VIN and VA until the amplified voltage difference is large enough to drive the final latch. The delay time can be minimized by using low-gain, wide bandwidth pre-amplifiers. 
         [0012]      FIG. 3  shows a prior-art auto-zeroing amplifier stage for an ADC. Small mismatches or other offset voltages in a comparator circuit can be larger than the voltage difference being compared. These offsets can be stored in the comparator during an auto-zeroing period and then cancelled during an amplifying period. 
         [0013]    During the zeroing period, clock φ 1  is active, closing switches  338 ,  346 ,  348 , but φ 2  is inactive, leaving switches  342 ,  344  open. The input voltages VIN+, VIN− are disconnected. Switch  346  equalizes the two inputs that receive VIN+, VIN− to the same voltage. Switch  338  connects the output of op amp  336  to its inverting input, providing a unity gain configuration. Offset voltage VOS  350  is a parasitic offset voltage rather than a voltage source such as a battery. When switch  338  is closed, and op amp  336  is in the unity gain configuration, VOS applied to the input of op amp  336  is driven to the output VOUT. Switch  348  also closes during φ 1 , driving the other end of VOS  350  to ground. Capacitor  340  isolates the negative terminal of VOS from the inputs. VOS is fed back from VOUT through switches  338 ,  348  to the other plate of capacitor  340 , so VOS is effectively stored on capacitor  340  during the zeroing period. 
         [0014]    During the amplifying period, φ 1  is inactive and φ 2  is active. Switches  338 ,  346 ,  348  open while switches  342 ,  344  close to connect VIN+, VIN− to the inputs of op amp  336 . Capacitor  340  stored negative VOS during the zeroing period, so the VOS on capacitor  340  cancels VOS  350 . The offset is canceled. VIN+ minus VOS plus VOS, or just VIN+, is applied to the non-inverting input of op amp  336 . VIN− is applied to the inverting input of op amp  336 , so op amp  336  amplifies the voltage difference VIN+, VIN− to generate VOUT. 
         [0015]    A series of such stages can be cascaded together in a prior-art ADC. Offsets can be stored in each stage, and a final latch stage can stored the final amplified result. VIN+ to the first stage can be VA and VIN− can be VIN of  FIG. 1 . 
         [0016]    Auto-zeroing requires a high-gain amplifier, yet a low-gain pre-amplifier was needed for high speed, such as shown in  FIG. 2 . This contradiction between high-gain and low-gain requirements makes design of such ADC&#39;s problematic. ADC&#39;s may have the desired gain, but may operate slowly or with fewer bits of precision. Tradeoffs may reduce the performance, either of speed or of precision, of the resulting ADC. 
         [0017]    In critical comparisons, such as with many digital bits of precision, the voltage applied to the comparator is small enough such that all the outputs may end up in the linear input range; thus the time taken for each output to reach the linear input region is much greater. The overdrive recovery delay is roughly four times the delay of any one amplifier. The overdrive recovery delay is the time from when the input is first applied to the first preamplifier stage to the time when the output of the last preamplifier returns from saturation to linear operation. This increased overdrive recovery delay is undesirable. Extra amplifiers may be used to compensate, but these extra amplifiers increase cost and are also undesirable. 
         [0018]    What is desired is a comparator stage for an ADC that can operate as both a low-gain preamplifier and a high-gain op amp. A stage that can provide unity-gain negative-feedback offset cancellation and low-gain pre-amplification is desired. A dual-use stage in an ADC is desirable. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  shows a Successive-Approximation-Register ADC. 
           [0020]      FIG. 2A  is a response graph of pre-amplifier and latch stages. 
           [0021]      FIG. 2B  shows a series of pre-amplifiers and a final latch. 
           [0022]      FIG. 3  shows a prior-art auto-zeroing amplifier stage for an ADC. 
           [0023]      FIG. 4  is a diagram of a dual-input differential amplifier comparator stage in an ADC. 
           [0024]      FIG. 5  is a schematic of a comparing and auto-zeroing stage in an ADC. 
           [0025]      FIG. 6  is a schematic of an alternate embodiment of a comparing and auto-zeroing stage in an ADC. 
           [0026]      FIG. 7  is a schematic of a final latch. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    The present invention relates to an improvement in comparators for ADC&#39;s. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
         [0028]      FIG. 4  is a diagram of a comparator stage in an ADC. While the prior art of  FIG. 3  places the capacitor in series between input VIN+ and the op amp, the inventors provide a direct path to the input of an op amp, and place capacitor  360  across a second pair of inputs to dual-input differential amplifier  370 . 
         [0029]    While a standard op amp has one pair of differential inputs, dual-input differential amplifier  370  has two pairs of differential inputs. Input voltage VIN+ passes through switch  362  to the primary non-inverting (+) input to dual-input differential amplifier  370 , while input voltage VIN− passes through switch  364  to the primary inverting (−) input to dual-input differential amplifier  370 . Switches  362 ,  364  close during phase φ 2  to connect inputs VIN+, VIN− to dual-input differential amplifier  370 , but are open during φ 1 , when switch  366  closes to equalize the primary differential inputs to dual-input differential amplifier  370 , and switch  368  closes to ground these primary inputs. 
         [0030]    Offset capacitor  360  is coupled across the secondary differential inputs to dual-input differential amplifier  370 . Feedback switches  356 ,  358  close during φ 1  to connect stage outputs VOUT+, VOUT− to the terminals of offset capacitor  360  and to the secondary inputs of dual-input differential amplifier  370 . Any offsets in the stage are fed back and stored on offset capacitor  360  during φ 1 . 
         [0031]    In an ADC, there may be several stages such as that shown in  FIG. 4  that are cascaded together. Each stage&#39;s VIN+, VIN− can be driven by VOUT+, VOUT− from the prior stage. The first stage can have VIN+ connected to the ADC input analog voltage, while VIN− is connected to VA from DAC  300  of  FIG. 1 . The last stage can drive a latch that drives a compare signal back to SAR  302 . 
         [0032]    During the auto-zeroing phase, φ 1  is active and φ 2  is inactive. Input switches  362 ,  364  are open, isolating dual-input differential amplifier  370  from stage inputs VIN+, VIN−. Switches  366 ,  368  close, grounding both primary differential inputs to dual-input differential amplifier  370 . Feedback switches  356 ,  358  close, connecting stage outputs VOUT+, VOUT− to the secondary differential inputs of dual-input differential amplifier  370 . Thus dual-input differential amplifier  370  is connected in a unity-gain configuration of the secondary inputs, while the primary inputs are grounded. Dual-input differential amplifier  370  operates as a high gain op amp. Any offsets in the stage are fed back through feedback switches  356 ,  358  and stored on offset capacitor  360 . 
         [0033]    During the amplifying phase, φ 1  is inactive but φ 2  is active. Input switches  362 ,  364  are closed, connecting from stage inputs VIN+, VIN− to the primary differential inputs of dual-input differential amplifier  370 . Switches  366 ,  368  are open, and feedback switches  356 ,  358  are open. The differential signal on VIN+, VIN− is amplified to generate VOUT+, VOUT−. 
         [0034]    Dual-input differential amplifier  370  operates as a high-speed, low-gain amplifier during amplifying phase φ 2 , but operates as a unity-gain op amp during auto-zeroing phase φ 1 . 
         [0035]      FIG. 5  is a schematic of a comparing and auto-zeroing stage in an ADC. The schematic of  FIG. 5  is functionally equivalent to  FIG. 4 , with some differences. For example, stage inputs VIN+, VIN− are applied directly to the gates of p-channel primary differential transistors  22 ,  24  rather than through input switches  362 ,  364 . P-channel primary differential transistors  22 ,  24  switch current to VOUT+, VOUT− from current source  26  during amplifying phase φ 2 . Thus VIN+, VIN− are quickly amplified during φ 2 . 
         [0036]    Feedback from the VOUT+, VOUT− outputs pass through feedback switches  10 ,  12  during φ 1  to the gates of p-channel secondary differential transistors  42 ,  44 , which switch current from current source  46  during auto-zeroing phase φ 1 . Closing feedback switches  10 ,  12  causes the dual-input differential amplifier to operate as a unity gain amplifier. 
         [0037]    In the unity gain configuration, any offsets are fed back through feedback switches  10 ,  12  and stored on offset capacitor  40  which has its terminals connected to the gates of p-channel secondary differential transistors  42 ,  44 . 
         [0038]    The currents through p-channel primary differential transistors  22 ,  24  and p-channel secondary differential transistors  42 ,  44  are sunk through resistors  36 ,  38  and n-channel sink transistors  32 ,  34 , which are connected between VOUT+, VOUT− and ground. The gates of n-channel sink transistors  32 ,  34  are driven with an adjustable bias voltage. 
         [0039]    During auto-zeroing phase φ 1 , switches  52 ,  54  close and switches  56 ,  58  are open. A bias voltage VB is generated by current source  16  providing a current through resistor  14  and n-channel bias transistor  18 , which has its gate and drain connected together as bias voltage VB. The bias voltage applied to the gates of n-channel sink transistors  32 ,  34  causes them to operate in the linear region to provide a high gain, but low current and thus a lower speed of operation. With feedback switches  10 ,  12  closed, the dual-input differential amplifier operates as a unity-gain op amp during auto-zeroing phase φ 1 . 
         [0040]    During amplifying phase φ 2  switches  52 ,  54  are open but switches  56 ,  58  close. Switches  56 ,  58  drive the power-supply voltage VDD to the gates of n-channel sink transistors  32 ,  34 , Applying VDD to the gates of n-channel sink transistors  32 ,  34  provides the maximum current drive. The high current provides a faster speed of operation, although the gain is low. Thus the dual-input differential amplifier operates as a high-speed, low-gain amplifier during amplifying phase φ 2 . 
         [0041]    Resistors  36 ,  38  provide a voltage drop as the sink current flows through them to n-channel sink transistors  32 ,  34 . This voltage drop increases the voltage levels of VOUT+, VOUT− and can provide a well-defined gain. In some embodiments, resistors  36 ,  38  may be deleted, or may be parasitic drain resistances. 
         [0042]      FIG. 6  is a schematic of an alternate embodiment of a comparing and auto-zeroing stage in an ADC. The schematic of  FIG. 6  is functionally equivalent to  FIG. 4 , with some differences. For example, stage inputs VIN+, VIN− are applied directly to the gates of p-channel primary differential transistors  22 ,  24  rather than through input switches  362 ,  364 . P-channel primary differential transistors  22 ,  24  switch current to VOUT+, VOUT− from current source  26  during amplifying phase φ 2 . Thus VIN+, VIN− are quickly amplified during φ 2 . 
         [0043]    Feedback from the VOUT+, VOUT− outputs pass through feedback switches  10 ,  12  during φ 1  to the gates of p-channel secondary differential transistors  42 ,  44 , which switch current from current source  46  during auto-zeroing phase φ 1 . Closing feedback switches  10 ,  12  causes the dual-input differential amplifier to operate as a unity gain amplifier. 
         [0044]    In the unity gain configuration, any offsets are fed back through feedback switches  10 ,  12  and stored on offset capacitor  40  which has its terminals connected to the gates of p-channel secondary differential transistors  42 ,  44 . 
         [0045]    The currents through p-channel primary differential transistors  22 ,  24  and p-channel secondary differential transistors  42 ,  44  are sunk through n-channel sink transistors  32 ,  34 , which are connected between VOUT+, VOUT− and ground. The gates of n-channel sink transistors  32 ,  34  are driven with an adjustable bias voltage. 
         [0046]    During auto-zeroing phase φ 1 , switches  52 ,  54  close and switches  56 ,  58  are open. A bias voltage VB is generated by current source  16  providing a current through resistor  14  and n-channel bias transistor  18 , which has its gate and drain connected together as bias voltage VB. The bias voltage applied to the gates of n-channel sink transistors  32 ,  34  causes them to operate in the linear region to provide a high gain, but low current and thus a lower speed of operation. With feedback switches  10 ,  12  closed, the dual-input differential amplifier operates as a unity-gain op amp during auto-zeroing phase φ 1 . 
         [0047]    During amplifying phase φ 2  switches  52 ,  54  are open but switches  56 ,  58  close. The gates and drains of p-channel primary differential transistors  22 ,  24  are shorted together by switches  56 ,  58 , causing n-channel sink transistors  32 ,  34  to operate as a resistor with a resistance of 1/gm. The high current provides a faster speed of operation, although the gain is low. Thus the dual-input differential amplifier operates as a high-speed, low-gain amplifier during amplifying phase φ 2 . 
         [0048]      FIG. 7  is a schematic of a final latch. An ADC may have several stages, such as  8  stages of  FIG. 6  cascaded together, with a final latch stage that drives the compare output back to SAR  302  of  FIG. 1 . Rather than sample and hold the input analog voltage, as shown in  FIG. 1 , the result of comparing the input analog voltage to the DAC voltage VA is stored in the final latch. 
         [0049]    In the final latch, the output from the last stage, VOUT+, VOUT−, is applied to the gates of p-channel differential latch transistors  64 ,  62 , which switch current sourced by p-channel current source transistor  60  which receives a bias voltage VBIASP on its gate. The current switched by p-channel differential latch transistors  62 ,  64  toggles the bistable sink, which has n-channel latch transistors  66 ,  68  with their gates cross-coupled to their drain. 
         [0050]    The latched value on n-channel latch transistors  66 ,  68  is output from their drains. The drain of n-channel latch transistor  66  and the gate of n-channel latch transistor  68  is applied to the gates of n-channel transistors  72 ,  74 , and to the drain of n-channel transistor  74 . Transistors  70 ,  72  have their drains connected together, and the gate and drain of p-channel transistor  70  are connected together and to the gate of p-channel transistor  80  to source output current to the latched output VOUT, which can be the compare output that is fed back to SAR  302  of  FIG. 1 . 
         [0051]    The drain of n-channel latch transistor  68  and the gate of n-channel latch transistor  66  are applied to the gates of n-channel transistors  76 ,  78 , and to the drain of n-channel transistor  76 . Transistors  80 ,  78  have their drains connected together as the latched compare output VOUT. 
         [0052]    During auto-zeroing phase φ 1 , VOUT+, VOUT− from the last stage are driven to a mid-point voltage by the unity gain configuration. Since VOUT+, VOUT− are driven to the same voltage during auto-zeroing, the latch is ready to be tipped to one state or the other during amplifying period φ 2 . 
         [0053]    Simulations for a 0.35 um process show that an  8 -stage comparator can convert an input of ±30 uV in 230 ns when there is no offset. When an offset of 2 mV is added to each stage, the 8-stage comparator can convert an input of ±30 uV with a delay of 280 ns. 
       Alternate Embodiments  
       [0054]    Several other embodiments are contemplated by the inventors. For example a bipolar junction transistor (BJT) or diode may replace transistors  32 ,  34 . The number of bits in the register value in SAR  302  can be adjusted to achieve the desired accuracy. For example, when N is 16 bits and VREF is 2 volts, the LSB represents  30  micro-volts, which is the precision of the ADC. A different number of bits could be substituted for a different precision, and the number of bits could be fixed or could be variable. 
         [0055]    Rather than use p-channel differential transistors, the circuit can be inverted or reversed and n-channel differential transistors substituted, and other p-channel transistors swapped to n-channel transistors, supply rails reversed, etc. Inversions may be added by swapping inverting and non-inverting inputs as desired, but do not change the overall function and thus may be considered equivalents. 
         [0056]    The resistance values of select and other resistors may vary in different patterns. Capacitors and other filter elements may be added. Switches could be n-channel transistors, p-channel transistors, or transmission gates with parallel n-channel and p-channel transistors. 
         [0057]    Additional components may be added at various nodes, such as resistors, capacitors, inductors, transistors, etc., and parasitic components may also be present. Enabling and disabling the circuit could be accomplished with additional transistors or in other ways. Pass-gate transistors or transmission gates could be added for isolation. 
         [0058]    Inversions may be added, or extra buffering. The final sizes of transistors and capacitors may be selected after circuit simulation or field testing. Metal-mask options or other programmable components may be used to select the final capacitor, resistor, or transistor sizes. 
         [0059]    While comparison to a single analog voltage has been described, a differential analog voltage could also be compared. The differential input voltage could be latched and then the latched single-ended voltage compared to the DAC voltage. Differential analog voltages could also be compared using a differential amplifier with a defined gain at the input. While an operational amplifier (op amp) has been described, other kinds of comparators could be used, such as non-amplifying compare buffers. 
         [0060]    While positive currents have been described, currents may be negative or positive, as electrons or holes may be considered the carrier in some cases. Source and sink currents may be interchangeable terms when referring to carriers of opposite polarity. Currents may flow in the reverse direction. 
         [0061]    Rather than have equalizing switch  366 , two grounding switches ( FIG. 4   368  and a second grounding switch on the + input to  370 ) could be used on the true and complement inputs lines of the primary pair of inputs to dual-input differential amplifier  370 . Rather than grounding, the switches could connect to another fixed voltage, such as VDD or VDD/2. 
         [0062]    Current sources  26 ,  46  may be p-channel transistors with gates connected to a fixed bias voltage. The fixed bias voltage may be switched to VDD to power down the dual-input differential amplifier. 
         [0063]    The circuit designer may choose resistors, capacitors, transistors, and other components to have a ratio that produces the desired reference voltages. While Complementary-Metal-Oxide-Semiconductor (CMOS) transistors have been described, other transistor technologies and variations may be substituted, and materials other than silicon may be used, such as Galium-Arsinide (GaAs) and other variations. 
         [0064]    The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant. 
         [0065]    Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result. 
         [0066]    Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line. 
         [0067]    The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.