Abstract:
In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line without increasing the layout area to improve the reading speed of the memory. Moreover, two adjacent banks of the memory share common bit lines or virtual ground lines, whereby reducing the contact density and height of the memory.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention is related generally to a read only memory (ROM) and more particularly to a flat cell ROM structure for high-speed applications.  
       BACKGROUND OF THE INVENTION  
       [0002]     Speeding up is always one of the attempts in the ROM design. For a high-speed memory, the main bottleneck in design is the low speed on the word line owing to the large resistance and parasitic capacitance inherent in a polysilicon word line, and there have been proposed two solutions for improving thereto. The first one is to separate a word line into several segments along the length thereof, and provide for each segment of the word line with an individual word line driver, so as to have a higher operating speed of the memory. In other words, the memory is separated into several small ones in this solution. For more illustrative, FIG.  1  is a schematic diagram of this solution, in which  FIG. 1A  is a simplified diagram of showing several word lines  10  and word line drivers  12  for driving the word lines  10  in a memory before the word line  10  is separated into multiple segments, and  FIG. 1B  is a simplified diagram of showing each of the word lines  10  in  FIG. 1A  having been separated into two segments  102  and  104 . In  FIG. 1A , each word line  10  has a length of L, and each word line  10  is driven by a word line driver  12 . After separated into two segments  102  and  104  along the length L, each word line  10  is provided with two drivers  12  for the segments  102  and  104 , respectively. For each segment  102  or  104  of a word line  10 , the resistance and parasitic capacitance thereof are only half as large as that of the original one, and therefore the operating speed thereto is improved. However, this solution requires a large number of additional word line drivers  12 , thereby dramatically increasing the circuit area of the memory.  
         [0003]     The other solution for speeding up a memory is to connect a word line with a metal line in parallel along the direction of the word line to reduce the RC delay thereof, and this metal line is referred to as a word line strap. The word line strap technique will not requests much more additional layout area, but is only available for those processes of two or more metal layers, due to the requirement of looser contacts in an array for the contacts to be slightly shifted in their locations so as to insert local metal word lines in the direction along the bit lines of the memory to connect the respective word lines in each memory banks. For more illustrative to the use of the word line strap,  FIG. 2  shows a schematic diagram of a simplified memory  20 , in which each of two memory banks Bank 0  and Bank 1  includes a word line WL 0 , and each of the word lines WL 0  is connected with a word line strap  204  or  206  in parallel by its side to reduce the resistance thereof. In the memory  20 , the bit lines BL 0  and BL 1 , virtual ground lines VG 0  and VG 1 , and local word line LWL 0  are formed from a first metal layer and perpendicular to the word lines WL 0  in the banks Bank 0  and Bank 1 , and the word line straps  204  and  206 , and global word line GWL 0  are formed from a second metal layer, in which the local word line LWL 0  connects the word line straps  204  and  206  to the global word line GWL 0  through contacts  208 ,  210 , and  212 , respectively, and the dash line  202  indicates the word line signal path.  
         [0004]      FIG. 3  provides a circuit diagram of a conventional flat cell ROM to show why the word line strap technique is not available for flat cell ROMs. In a memory  30 , a memory array  32  includes several transistors  322  serving as memory cells arranged in a manner that the gates of the transistors  322  on the same row are connected to a common word line among WL 0 -WLN, and the sources/drains of the transistors  322  on the same column are connected to a common bit line BL or virtual ground line VG, and select lines SL 0  and SL 1  to select the bit line BL and virtual ground line VG.  FIG. 4  shows a layout of the circuit  30  shown in  FIG. 3 , in which Bank 0 , Bank 1 , and Bank 2  represent different memory banks. In the memory bank Bank 1 , each bit line BL and each virtual ground line VG are connected to a respective bit signal line  36  and a respective virtual ground signal line  38  through a respective contact  34 . It is shown in  FIG. 4  that there is no enough space between the adjacent contacts  34  allowed the contacts  34  to be slightly shifted in their locations and therefore, inserting any local word line between the bit signal line  36  and virtual ground signal line  38  will push the adjacent structures away from the original locations in the X-direction and enlarge the layout area.  
         [0005]     Therefore, it is desired a flat cell ROM available for the word line strap technique to be applied without an enlarged layout area.  
       SUMMARY OF THE INVENTION  
       [0006]     One object of the present invention is to provide a flat cell ROM structure available for the word line strap technique to be applied thereto.  
         [0007]     Another object of the present invention is to provide a flat cell ROM using common contacts for bit lines and virtual ground lines.  
         [0008]     In a flat cell read only memory including a plurality of memory banks, according to the present invention, each of the memory banks comprises a memory array, and a plurality of word lines as well as a plurality of bit lines and virtual ground lines perpendicular thereto connected to the memory array for selecting a specific memory cell therefrom, in which any two adjacent bit lines are connected to the memory array through a first switch and a second switch, respectively, and connected to a bit signal line through a first common contact, each of the virtual ground lines is connected to the memory array through a third switch and a fourth switch, any two adjacent virtual ground lines are connected to a virtual ground signal line through a second common contact, and the first and second contacts are shared by adjacent memory banks of the memory. Further, the first and third switches are switched by a first select line, and the second and fourth switches are switched by a second select line.  
         [0009]     With the first contact shared by two bits line and the second contact shared by two virtual ground lines, the contacts in a memory of the present invention are allowed to be slightly adjusted in their locations to insert a local word line for speeding up the operation of the memory without increasing the layout area. Moreover, in a memory of the present invention, with the first and second contacts shared by adjacent banks, the contact density is reduced, and the height of the memory is reduced accordingly. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0010]     These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:  
         [0011]      FIG. 1A  is a simplified diagram of several word lines and word line drivers in a conventional memory;  
         [0012]      FIG. 1B  is a simplified diagram of several word lines having separated segments and word line drivers in a conventional memory;  
         [0013]      FIG. 2  shows a schematic diagram of a simplified conventional memory using the word line strap technique;  
         [0014]     FIG. 3  shows a circuit diagram of a conventional flat cell ROM;  
         [0015]      FIG. 4  shows a layout of the memory circuit shown in  FIG. 3 ;  
         [0016]      FIG. 5  shows a circuit diagram of a flat cell ROM according to the present invention;  
         [0017]      FIG. 6  shows a layout of the memory circuit shown in  FIG. 5 ;  
         [0018]      FIG. 7  shows a practical layout of the memory shown in  FIG. 3 ;  
         [0019]      FIG. 8  shows a practical layout of the memory shown in  FIG. 5 ; and  
         [0020]      FIG. 9  shows two memory banks of the memories shown in  FIGS. 3 and 5 , respectively. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]      FIG. 5  shows a circuit diagram of a flat cell ROM  40  according to the present invention. In a memory bank  42  of the ROM  40 , a memory array includes several transistors  482  serving as memory cells arranged in a manner that the gates of the transistors  482  on the same row are connected to a common word line among WL 0 -WLN, and the sources/drains of the transistor  482  on the same column are connected to one of bit lines BL 0 -BL 7  or virtual ground lines VG 0 -VG 8 , respectively. The bit lines BL 0  and BL 1  are bonded together to a common bit line CBL 0 , and capable of being connected to the memory array  48  through transistors MB 0  and MB 1 , respectively. The bit lines BL 2  and BL 3  are bonded together to a common bit line CBL 1 , and capable of being connected to the memory array  48  through transistors MB 2  and MB 3 , respectively. The bit lines BL 4  and BL 5  are bonded together to a common bit line CBL 2 , and capable of being connected to the memory array  48  through transistors MB 4  and MB 5 , respectively. The bit lines BL 6  and BL 7  are bonded together to a common bit line CBL 3 , and capable of being connected to the memory array  48  through transistors MB 6  and MB 7 , respectively. The virtual ground lines VG 0  and VG 1  are bonded together to a common virtual ground line CVG 0 , the virtual ground line VG 0  is capable of being connected to the memory array  48  through a transistor MV 0 , and the virtual ground line VG 1  is capable of being connected to the memory array  48  through transistors MV 1  and MV 2 . The virtual ground lines VG 2  and VG 3  are bonded together to a common virtual ground line CVG 1 , the virtual ground line VG 2  is capable of being connected to the memory array  48  through transistors MV 3  and MV 4 , respectively, and the virtual ground line VG 1  is capable of being connected to the memory array  48  through transistors MV 5  and MV 6 , respectively. The virtual ground lines VG 4  and VG 5  are bonded together to a common virtual ground line CVG 2 , the virtual ground line VG 4  is capable of being connected to the memory array  48  through transistors MV 7  and MV 8 , respectively, and the virtual ground line VG 5  is capable of being connected to the memory array  48  through transistors MV 9  and MV 10 , respectively. The virtual ground lines VG 6  and VG 7  are bonded together to a common virtual ground line CVG 3 , the virtual ground line VG 6  is capable of being connected to the memory array  48  through transistors MV 11  and MV 12 , respectively, and the virtual ground line VG 7  is capable of being connected to the memory array  48  through transistors MV 13  and MV 14 , respectively. The transistors MB 1 , MB 3 , MB 5 , MB 7 , MV 0 , MV 2 , MV 4 , MV 6 , MV 8 , MV 10 , MV 12 , MV 14 , and MV 16  are under the control of a select line SL 0 , and the transistors MB 0 , MB 2 , MB 4 , MB 6 , MV 1 , MV 3 , MV 5 , MV 7 , MV 9 , MV 11 , MV 13 , and MV 15  are under the control of a select line SL 0 B.  
         [0022]     Referring to  FIG. 5 , in the flat cell ROM  40 , memory banks  42  and  44  share the common bit lines CBL 0 -CBL 3 , and memory banks  42  and  46  share the common virtual ground lines CVG 0 -CVG 4 . In this embodiment, moreover, the bit lines BL 0 -BL 7  and virtual ground lines VG 0 -VG 8  are arranged at the top side and bottom side of the memory array  48 , respectively, and therefore the cell current path is an I-type path. While in the conventional ROM  30  shown in  FIG. 3 , the cell current path is a U-type path, owing to the staggered arrangement of the bit lines BL and virtual ground lines VG. It is known to those skilled ones in the art that, under a same bias, an I-type cell current path has a larger cell current than a U-type cell current path does. As a result, a greater design margin is obtained, and the reading speed is higher.  
         [0023]      FIG. 6  shows a layout of part of the circuit  40  shown in  FIG. 5 , from which is pictured that two adjacent bit lines, for example BL 2  and BL 3 , share a common contact  58  to connect to a bit signal line  50 , and two adjacent virtual ground lines, for example VG 2  and VG 3 , share a common contact  60  to connect to a virtual ground signal line  52 , resulting in less contacts. Therefore, there is a larger space present between two adjacent contacts for the contacts to be adjusted in their locations, so as to easily insert a local word line  54  between a bit signal line  50  and a virtual ground signal line  52  to connect to the word line WL 0  through a contact  56 . Furthermore, the memory banks  42  and  44  have their bit lines to share the contact  58  therebetween, and the memory banks  42  and  46  have their virtual ground lines to share the contact  60  therebetween, thereby reducing the contact density and the height of the memory.  
         [0024]      FIG. 7  is a practical layout of the conventional memory  30 , and  FIG. 8  shows a practical layout of the memory  40  according to the present invention, from which it is shown that the contact density between adjacent banks in the memory  40  is much lower than that in the conventional memory  30 . For comparison,  FIG. 9  shows a layout of one memory bank in the memory  40  according to the present invention and a layout of one memory bank in the conventional memory  30  to put together, with the former on the left and the latter on the right, and the heights of them besides. The memory bank of the present invention has a height of 28.15 μm, which is 0.25 μm or approximately 0.88% less than the height of 28.4 μm for the conventional memory bank.  
         [0025]     While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set fourth in the appended claims.