Abstract:
A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.

Description:
FIELD OF THE INVENTION 
     The present invention relates to driver protection circuits that prevent short circuits and high currents that could potentially damage the driver. The present invention also relates to methods for protecting the circuits that drive capacitive loads. 
     BACKGROUND OF INVENTION 
     Capacitive loads are often found in the form of piezoelectric actuators, such as piezoelectric speakers or motors for driving mechanical components. Typically, the capacitive loads are relatively small, e.g., on the order of 2 nF. Thus, driver circuits for driving capacitive loads are often designed without taking into account the possibility that the drivers may be connected to loads that are of greater capacitance than the drivers can handle. As the load capacitance increases, so does the power required to drive the capacitance. If the power exceeds the current handling capabilities of the driver, damage may occur. 
       FIG. 1  shows an example of a conventional H-bridge driver  10  formed using CMOS elements. Each terminal of a capacitive load  20  is connected to a respective resistor  5 , which receives an input signal from a source-drain connection of a PFET-NFET transistor pair. Alternatively, the capacitor terminals may be connected directly to the source-drain connection without intervening resistors. One transistor pair consists of a PFET  12  and an NFET  16 . Another pair consists of a PFET  14  and an NFET  18 . The PFETs  12 / 14  operate as pull-up devices and are connected to a power supply signal Vdd. The NFETs operate as pull-down devices and are connected to a ground signal Vss. Depending on the gate inputs supplied to the transistors  12 / 14 / 16 / 18 , the load  20  may be driven in any number of ways. For example, the PFET  12  may be switched on in combination with the NFET  16 , e.g., by first turning the PFET  12  on to develop a voltage (e.g., Vdd) at a source-drain connection Vout_ 1 , then turning PFET  12  off while turning NFET  16  on to provide a current path to Vss. Alternatively, the PFET  14  may be switched on in combination with the NFET  18 , e.g., by turning the PFET  14  on, then off while turning NFET  18  on. In either of these configurations, current is supplied across the terminals of the load  20 . If the capacitance of the load  20  is too large, the current may exceed the handling capabilities of the driver  10 , and cause permanent damage to one or more of the transistors  12 / 14 / 16 / 18 . 
     In addition to high capacitance, another problem to which the present invention is directed is short circuits. In  FIG. 1 , if the PFET  12  and the NFET  18  are switched on while the terminals of the capacitor are shorted, this leads to a dangerous condition in which Vdd is essentially connected directly to Vss through low ohmic drivers. Consequently, a large current develops through the transistors  12 / 18  which, as pointed out above, can lead to permanent damage. Thus, there is a need in the art for techniques that prevent damage to drivers, and in particular, damage arising from attempts to drive high capacitive loads. 
       FIG. 2  shows a plot of the output current of the driver  10  of  FIG. 1  versus time. A curve  23  may correspond to a hypothetical current measured through either of the two source-drain connections labeled Vout_ 1  and Vout_ 2  in  FIG. 1 . A curve  21  may correspond to a hypothetical short circuit condition in which the current at the source-drain connection rapidly rises to a maximum and then remains constant. Curve  23  may be related to capacitor charge in that the current rapidly rises as the load  20  is charged, then saturates before slowly decreasing (corresponding to a transition from transistor saturation to triode region operation when the capacitor voltage is charged to a nearly Vdd-level voltage, as measured at Vout_ 1  or Vout_ 2 ). 
     As evident from the curves  21  and  23 , the current goes high and saturates in both cases, so that it is not possible to distinguish the short circuit condition simply by detecting a high current. However, as explained below, selection of appropriate threshold detection levels in combination with detection timing allows for proper short circuit detection. 
     Additionally, the rate at which the current in curve  23  decays is a function of capacitor size and of the total series resistance connected to the capacitor (e.g., FET resistances plus any additional series resistances). If the load  20  is relatively small, then the current should decay quickly. Thus, as explained in connection with the exemplary embodiments of the present invention, current and/or voltage at the output, e.g., the source-drain connection Vout_ 1 , can be used to detect capacitor size. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a conventional H-bridge driver. 
         FIG. 2  is a diagram illustrating an output current of the driver of  FIG. 1  as a function of time. 
         FIG. 3  is a block diagram illustrating a system for driver protection according to an embodiment of the present invention. 
         FIG. 4  is a block diagram illustrating components of a detection circuit according to an embodiment of the present invention. 
         FIG. 5  is diagram illustrating an example of a detection circuit connected to a driver according to an embodiment of the present invention. 
         FIG. 6  is a diagram illustrating exemplary detection principles of the present invention as applied to output voltage versus time. 
         FIG. 7  is a diagram illustrating additional exemplary detection principles of the present invention as applied to output voltage versus time. 
         FIG. 8  is a flow chart illustrating a first detection method according to an embodiment of the present invention. 
         FIG. 9  is a flow chart illustrating a second detection method according to an embodiment of the present invention. 
         FIG. 10  is a flow chart illustrating a third detection method according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention provide methods for enhanced driver protection. The methods may involve comparing an output signal of a driver circuit that drives a capacitive load to a reference voltage, then sampling a result of the comparison at a predetermined time after the output signal is asserted. The reference voltage may be associated with an error condition such as a high capacitive load or a short circuit. The methods may also involve generating an error signal when the sampled result indicates that the output signal is below the reference voltage. By detecting the error condition at an appropriate time using the voltage comparison, the methods of the present invention provide for a more robust protection of the driver circuit compared to conventional protection schemes. 
       FIG. 3  shows an exemplary system  100  according to the present invention. The system  100  includes a capacitive load (e.g., the load  20 ), a driver  30 , a detector  40  and a controller  50 . 
     The driver  30  may be any driver of a capacitive load, such as the driver  10  previously described. The driver  30  may produce the output signal over Vout_ 1  in response to some input, e.g., from the controller  50 , to drive the load  20 . Although the driver  30  is a CMOS circuit, other types of circuit technologies may be used to form suitable drivers. For example, in an alternative embodiment, the driver  30  may include bi-polar junction transistors (BJTs), in which case the output voltage/current can be measured as a function of a signal across the base and emitter terminals of a BJT. 
     Referring to  FIG. 4 , the detector  40  is shown to include a comparator  52 , a latch  54  and a timer unit  56 . The comparator  52  may receive the signal Vout as an input along with a reference signal Vref. In an exemplary embodiment, Vout is connected to Vout_ 1  of  FIG. 3 . The comparator  52  may compare Vout to Vref and generate a digital output, e.g., a “1” if Vout is greater than Vref and a “0” if Vout is not greater than Vref. In alternative embodiments, the comparator  52  may generate an analog output. However, for ease of implementation, it is preferred that the output is digital. Vref may be a selectable reference voltage corresponding to Vthres_ 1  and/or Vthres_ 2  (described below in connection with  FIG. 6 ). For example, Vref may be set to Vthres_ 1  at T 1 , then changed to Vthres_ 2  at T 2 . Alternatively, a separate comparator may be provided so that Vref can be fixed at either Vthres_ 1  or Vthres_ 2 . 
     The latch  54  may receive the digital output of the comparator  52  and latch the digital output at times determined by the timer unit  56 . The latch  54  may be any device capable of storing an input signal in response to a control signal. The latch  54  may pass the digital output to the controller  50 . In one embodiment, the latch  54  may be a flip-flop that receives the control signal as an enable input so that the digital output is latched each time the control signal is asserted. 
     The timer unit  56  may generate the control signal as a delayed response to an assertion of Vout by the driver  30 , e.g., in response to the assertion of a gate input that causes the driver  30  to produce Vout. The control signal can be output any number of times in response to each assertion of Vout. In one embodiment, each assertion results in the control signal being output at a predetermined time corresponding to a delay equal to T 1 . In another embodiment, each assertion results in the control signal being output at T 1 , then output again at T 2 . The number and timing of each control signal output by the timer unit  56  depends on the requirements of a particular detection scheme which, as discussed below, can vary. The delay value(s) can be stored in the timer unit using any form of data storage, e.g., a temporary register. 
     The controller  50  may provide an input signal to the driver  30 . The controller  50  may also modify the input signal when the detector  40  indicates the presence of an error condition. For example, the controller  50  may simply refrain from asserting the input signal to the driver  30  (thereby preventing generation of Vout) whenever the error condition is detected. 
     Although the exemplary embodiments of the present invention are described with respect to a Vout connected to the source-drain connection Vout_ 1 , it will be understood that the present invention may also be implemented at other output nodes, e.g., the source-drain connection of the transistors  14 / 18  (Vout_ 2 ). This may be done in combination with, or as an alternative to, detection at Vout_ 1 , so that both sides of the driver  10  are monitored during the respective on times of Vout_ 1  and Vout_ 2 . For example, in an alternative embodiment, instead of feeding only Vout_ 1  into the comparator  52 , Vout_ 1  and Vout_ 2  may be fed into the comparator  52  at different times using pass gates, the timing of which may be controlled by the timer unit  56 . In yet another embodiment, the comparator  52  and the latch  54  may be duplicated to provide a parallel path for Vout_ 2 , so that Vout_ 1  and Vout_ 2  are simultaneously compared to Vref and latched. 
       FIG. 5  shows a system  150  according to an embodiment of the present invention, in which the detector  40  is connected to the driver  10  shown in  FIG. 1 . For illustrative purposes, only the PFET  12  and the NFET  16  are shown. Instead of connecting the comparator  52  directly to Vout as shown in  FIG. 4 , a resistor divider comprising series resistors  32  and  34  may be used to lower Vout before input into the comparator  52 . Additionally, a second resistor divider comprising series resistors  36  and  38  may be used to lower Vdd before input into the comparator  52 . The resistance values of the resistors  32 / 34 / 36 / 38  may be selected to provide voltage levels appropriate for use with the comparator  52 . 
     The resistor  38  may be a variable resistor set to a value that causes Vref to equal Vthres_ 1  or Vthres_ 2 . In this manner, the comparator  52  can be configured to compare Vout (or, in the example of  FIG. 5 , a signal derived from Vout) to Vthres_ 1  or Vthres_ 2 . 
       FIG. 6  shows a plot of the output voltage at the source-drain connection Vout_ 1  when the PFET  12  is turned on. A substantially constant voltage level  31  corresponds to a voltage at the source terminal of the PFETs  12 / 14 . The voltage  31  may be equal to Vdd or, alternatively, may be a boosted voltage greater than Vdd. A curve  33  corresponds to a voltage characteristic of a small capacitor, while a curve  35  corresponds to a voltage characteristic of a large capacitor. A curve  37  corresponds to a voltage level associated with a short circuit, i.e., a short to Vss. The curves shown in  FIG. 6  may be equally representative of the output voltage at Vout_ 2  when the PFET  14  is turned on. 
     As shown in  FIG. 6 , the small capacitor reaches a saturation voltage faster than the large capacitor. This can be used as a basis for distinguishing small capacitances from large capacitances. For example, a threshold voltage detection may be performed at a time in which the small capacitor is expected to be at or near saturation (T 1 ), but the large capacitor has not yet reached saturation. Additionally, a threshold voltage detection may be performed at a time in which both the small capacitor and the large capacitor are expected to be at or near saturation (T 2 ), making it possible to detect whether there is a short circuit, since the short circuit voltage is substantially lower than the saturation voltage of either capacitor. 
     Also shown in  FIG. 6  are threshold voltages Vthres_ 1  and Vthres_ 2 , which may be selected in combination with detection times, e.g., T 1  and T 2 , to define an exact set of conditions that must be met in order to determine that neither a short circuit nor an excessively large capacitance is present. Vthres_ 1  may correspond to a voltage level less than the saturation voltage of the small capacitance, yet greater than the expected voltage of the large capacitor at T 1 . Thus, if a voltage detected at T 1  exceeds Vthres_ 1 , this indicates that the capacitor is a small capacitor. However, if the detected voltage does not exceed Vthres_ 1 , then either the capacitor is large or there exists a short circuit. 
     Vthres_ 2  may correspond to a voltage level less than the saturation voltages of the large capacitor and the small capacitor, yet greater than the short circuit voltage. Thus, if a voltage detected at T 2  exceeds Vthres_ 2 , this indicates that the capacitor is either a small capacitor or a large capacitor. However, if the detected voltage does not exceed Vthres_ 2 , then there exists a short circuit. 
       FIG. 7  shows a plot of the output voltage at the source-drain connection Vout_ 1  when the NFET  16  is turned on. The substantially constant voltage level  31 , as discussed above in connection with  FIG. 6 , may correspond to Vdd or a boosted supply voltage. A curve  43  corresponds to a voltage characteristic of a small capacitor, while a curve  45  corresponds to a voltage characteristic of a large capacitor. A curve  47  corresponds to a voltage level associated with a short circuit, i.e., a short to Vdd. The curves shown in  FIG. 7  may be equally representative of the output voltage at Vout_ 2  when the NFET  18  is turned on. 
     Also shown in  FIG. 7  are threshold voltages Vthres_ 3  and Vthres_ 4 , which may be selected in combination with detection times, e.g., T 4  and T 5 , to define an exact set of conditions that must be met in order to determine that neither a short circuit nor an excessively large capacitance is present. Vthres_ 3  may correspond to a voltage level greater than the saturation voltage of the small capacitance, yet smaller than the expected voltage of the large capacitor at T 4 . Thus, if a voltage detected at T 4  is less than Vthres_ 3 , this indicates that the capacitor is a small capacitor. However, if the detected voltage exceeds Vthres_ 3 , then either the capacitor is large or there exists a short circuit. 
     Vthres_ 4  may correspond to a voltage level greater than the saturation voltages of the large capacitor and the small capacitor, yet less than the short circuit voltage. Thus, if a voltage detected at T 5  is less than Vthres_ 4 , this indicates that the capacitor is either a small capacitor or a large capacitor. However, if the detected voltage exceeds Vthres_ 4 , then there exists a short circuit. 
     Exemplary detection methods will now be described in connection with  FIGS. 8 to 10 . The detection methods may be implemented using the systems and devices previously described, and may be performed at any time. For example, it is possible to perform any of the methods during a testing phase of device manufacture, in order to detect large capacitances or short circuits prior to device packaging. In a preferred embodiment, at least one of the methods is performed on a continuous basis while the driver  30  is in operation. Accordingly, the timer unit  56  can be implemented as a digital clock that is enabled or reset whenever there is a new assertion of Vout. 
       FIG. 8  shows an exemplary method  200 . In step  210 , Vref is set. Vref may correspond to either Vthres_ 1 , or Vthres_ 2 , depending on the detection requirements of a user. For example, if the user is interested in detecting both large capacitances and short circuits, Vref can be set to Vthres_ 1 . However, if the user is only concerned with short circuits, Vref can be set to Vthres_ 2 . 
     In step  212 , the sampling rate may be set. The sampling rate may correspond to a delay value programmed into the timer unit  56 . The delay value may cause sampling to occur in sync with an activation of the transistors. For example, if Vthres_ 1  or Vthres_ 2  are used, then the sampling may occur when PFET  12  or  14  is turned on. 
     In step  214 , the output of the comparator  52  may be sampled by the latch  54  after a delay equal to the sampling rate. 
     In step  216 , the method  200  may determine, based on the comparator output, whether Vout is greater than Vref. This determination may be performed anytime after the latching in step  214 . In one embodiment, the controller  50  may be configured to periodically poll the latch  54  to perform the determination. If Vout exceeds Vref, then there is no error condition and the method  200  returns to  214 . However if Vout does not exceed Vref, then an error condition is present and an error procedure is executed in  218 . 
     The error procedure in  218  may include preventing the driver  30  from driving the load  20 . Additionally, an error indicator may be provided to the user in the form of a visual display, an audio alarm, an error log, etc. 
       FIG. 9  shows an exemplary method  300 , which differs from the method  200  in that a plurality of threshold voltages are set, instead of setting a single Vref ( 310 ). In step  312 , the sampling rate may be set in a manner similar to that of step  212  in  FIG. 8 . 
     In step  314 , the output of one or more comparators is sampled. In one embodiment, a separate comparator may be provided for each threshold voltage, e.g., one for Vthres_ 1  and one for Vthres_ 2 . Each comparator can be operated in parallel. In another embodiment, a single comparator, e.g., the comparator  52  may, at different times, compare Vout to a respective threshold voltage, then output each comparison to a separate latch. For example, the timer unit  56  may control the resistor  38  so that Vref varies between Vthres_ 1  and Vthres_ 2 . The timer unit  56  may also cause the separate latches to latch the output of the comparator  56  in conjunction with the varying of Vref, e.g., after appropriate delays. 
     In step  316 , the method  300  may determine, based on the comparator output, whether Vout exceeds a first threshold, e.g., Vthres_ 1 . If Vout exceeds Vthres_ 1 , then there is no error and the method  300  returns to step  314 . 
     If Vout does not exceed Vthres_ 1 , then the method  300  proceeds to  316 , where it may be determined whether Vout exceeds Vthres_ 2 . If Vout exceeds Vthres_ 2 , then a large capacitance is detected, but there is no short circuit. If Vout does not exceed Vthres_ 2 , then there is a short circuit. In either case, an error procedure is performed in  320 . The error procedure may be similar to that of step  218  in  FIG. 8 . Additionally, the error condition may be handled in different ways depending on the nature of the error. For example, short circuits may require immediate shut-down, whereas large capacitances may involve gradual shut-down or drive operation using a nominal output voltage that won&#39;t damage any circuit components. 
       FIG. 10  shows an exemplary method  400 , in which a single Vref value, e.g., Vthres_ 1 , is set in step  410 . In  412 , a plurality of sampling rates may be set in order to perform at least two comparisons at different times. 
     In  414 , the output of a comparator, e.g., the comparator  52 , may be sampled in accordance with the earliest of the sampling rates, e.g., T 1 . 
     In  416 , the method  400  may determine whether Vout exceeds Vref. If Vout exceeds Vref, then there is no error and the method  400  returns to step  414 . However, if Vout does not exceed Vref, then the method  400  proceeds to step  418 , where the comparator output may be re-sampled in accordance with the next earliest sampling rate, e.g., T 2 . 
     In  420 , the method  400  may again determine whether Vout exceeds Vref. If Vout exceeds Vref, then a large capacitance is detected. However, if Vout does not exceed Vref, then a short circuit is detected. In either case, an error procedure may be performed in  422 , in a manner similar to that of step  320  in  FIG. 9 . 
     As illustrated in the exemplary embodiments above, the present invention enables various error conditions to be detected through careful selection of signal threshold and timing parameters. Using at least one threshold-timing parameter pair (e.g., Vthres_ 1  and T 1 ), it is possible to distinguish normal operation from, for example, a short circuit or a high capacitive load. 
     The exemplary systems and methods above were discussed in connection with voltage detection during PFET activiation, i.e., when either PFET  12  or  14  is turned on. However, systems and methods may also be implemented in connection with NFET activation, i.e., when either NFET  16  or  18  is turned on. For example, Vref may correspond to Vthres_ 3  or Vthres_ 4 , and analogous comparisons of Vout to Vref may be performed to determine whether a large capacitance, a smaller capacitance, or a short circuit is occurring. For example, after setting the appropriate threshold (e.g., Vref or either of the first and the second thresholds in  FIG. 9 ) to Vthres_ 3  or Vthresh_ 4 , the comparisons at each of steps  216 ,  316 ,  318 ,  416  and  420  may be substituted with a comparison that determines whether Vout is less than the threshold. It may be advantageous to combine PFET-based detection with complementary NFET-based detection, because although both types of detection can be used to determine whether a large capacitance or a small capacitance exists, PFET-based detection may enable detection of shorts to Vss, whereas NFET-based detection may enable detection of shorts to Vdd. Thus, in one alternative embodiment, the system  100  may perform sampling and detection for PFET activation as well as NFET activation. Additionally, detection of large and small capacitances need only be performed for one of the types of activation, since PFET-based detection and NFET-based detection are equally capable of detecting these conditions. 
     Although the exemplary methods described above utilize voltage detection, it will be understood that the present invention may also be implemented using current detection, since voltage and current are essentially governed by the relationship P=VI, where P is power, V is voltage and I is current. Accordingly, in alternative embodiments, current values may be substituted for Vref, Vthres_ 1 , Vthres_ 2 , Vthres_ 3  or Vthres_ 4 .