Abstract:
A charge-pump circuit for charge-share suppression. A first switching element is coupled between a first connecting node and an output terminal. A first load receives a current from a first current source and outputs an output voltage at the output terminal when the first switching element is in “On” state. A status of a second switching element is controlled by the input signal and opposite to the status of the first switching elements A second current source is coupled to the second switching element through a second connecting node. A second load receives the output voltage when the second switching element is in “On” state. A first feedback circuit maintains a constant relation between the output voltage and a voltage of the first node. A second feedback circuit maintains a constant relation between the output voltage and a voltage of the second node.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to a charge-pump circuit for the PLL (Phase Lock Loop), and more particularly to a feedback charge-share suppressing charge-pump circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    When generating required system clocks, it is necessary to input referenced clocks in phase lock loops (PLL) or clock synthesizers. FIG. 1 is a block diagram illustrating a conventional phase lock loop system. The phase lock loop system  100  comprises a phase frequency detector  102 , a charge-pump circuit  104 , a voltage-controlled oscillator  106 , a divider  108  and a loop filter  110 . The phase lock loop system  100  receives a referenced clock F in . The charge-pump circuit  104  drives the voltage-controlled oscillator  106  to generate a required clock F out  at a signal generated by the phase frequency detector  102 . The required clock F out  is fed back to the phase frequency detector  102  through the divider  108 . The loop filter  110  is coupled to an output terminal of the charge-pump circuit  104 . A detailed diagram of the conventional charge-pump circuit  104  and loop filter  110  is shown in FIG. 2 a.    
           [0005]    [0005]FIG. 2 a  is a circuit diagram illustrating a conventional charge-pump circuit and loop filter as shown in FIG. 1. As shown in FIG. 2 a,  the charge-pump circuit  104  comprises current sources  202  and  204 , switches  206  and  208 , and a capacitor  210 . The loop filter  110  is composed of a capacitor  212 . The loop filter  110  is coupled to an output terminal of the charge-pump circuit  104 . When the switch  206  is in “On” state, the loop filter  110  is charged by the current sources  202 . When the switch  208  is in “On” state, the loop filter  110  supplies the stored power to the switch  208  and the current source  204 . A charge-share problem occurs in the charge-pump circuit  104 . FIG. 2 b  is a diagram illustrating the charge-share problem in the charge-pump circuit shown in FIG. 2 a.  The X axis is time, in units of seconds (s). The Y axis is the output voltage Vc, in units of volts (V). Line  22  shows a normal voltage curve. Dotted line  24  shows a curve of the voltage affected by the charge-share problem when the switch  206  changes from “Off” state to “On” state. Because of the charge-share problem, the signal driving the controlled oscillator  106  is incorrect. Thus, the phase lock loop system cannot generate the required clock.  
           [0006]    To preventing the charge-share problem, Ian A. Young, Jeffrey K. Greason, and Keng L. Wang provide a charge-pump circuit for charge-share suppression with an operational amplifier (referring “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE J. Solid State Circuits, vol. 27, pp. 1599-1607 November 1992). FIG. 3 is a circuit diagram illustrating the conventional charge-pump circuit for charge-share suppression with the operational amplifier OP 1 . As shown, when the switches S 1  and S 4  are in “Off” state and the switches S 2  and S 3  are in “On” state, through the operational amplifier OP 1 , the voltage on the node N 1  is equal to V c . When the switches S 2  and S 3  is in “Off” state and the switches S 1  and S 4  is in “On” state, through the operational amplifier OP 1 , the voltage on the node N 2  is equal to V c . Thus, the charge-share problem does not occur. The disadvantage of this circuit is that the operational amplifier must work in the wide range of the input frequency and respond quickly to all input frequencies. The result of the charge-share suppression in this circuit completely depends upon the operational capacity of the operational amplifier. A fine design of the operational amplifier is preferred to the result of the charge-share suppression. It is difficult to design such an operational amplifier. Thus, the design of the charge-pump circuit becomes more complex.  
           [0007]    To overcome the above problem, Hee-Tae Ahn and David J. Allstet provide a charge-pump circuit for charge-share suppression with transistors (referring to Hee-Tae Ahn and David J. Allstet “A Low-Jitter 1.9 V CMOS PLL for UltraSPARC Microprocessor Applications, ” IEEE J. Solid-State Circuits, vol. 35, pp. 450-454 March 2000). FIG. 4 is a circuit diagram illustrating the conventional charge-pump circuit for charge-share suppression with the transistors Q 1  and Q 2 . As shown in FIG. 4, when the switch S 1  is in “Off” state and the switch S 2  is in “On” state, a difference in voltage between a source and a gate of the transistor Q 1  is V Q1 . Thus, the voltage on the node N 1  is equal to V c +V Q1 . If the voltage depleted in an impedance of the switch Si in “On” state is V Q1 , the charge-share problem does not occur. When the switch S 2  is in “Off” state and the switch S 1  is in “On” state, a voltage between a source and a gate of the transistor Q 2  is V Q2 . Thus, the voltage on the node N 2  is equal to V c +V Q2 . If the voltage depleted in an impedance of the switch S 2  in “On” state is V Q2 , the charge-share problem does not occur. Therefore, his circuit has many problems. When the switch is in “On” state, there are two current paths, and it is difficult to detect the current through the switch. Thus, the impedance of the switch in “On” state is difficult to determine, to resolve the charge-share problem. Also, when the current through the switch is small, the impedance of the switch in “On” state must be large. However, in the design of the switch, the impedance of the switch in “On” state must be small. The large impedance of the switch in “On” state cannot be implemented in practical circuit. Finally, the large impedance of the switch in “On” state can be influenced by different procedures and environments. Thus, the design the charge-pump circuit becomes more complex.  
         SUMMARY OF THE INVENTION  
         [0008]    An object of the present invention is to provide a charge-pump circuit for charge-share suppression without adding operational amplifiers to decrease the difficulty of design for the charge-pump circuit.  
           [0009]    Another object of the present invention is to provide a charge-pump circuit for charge-share suppression with a feedback path to resolve the problems in the conventional charge-pump circuit shown in FIG. 4.  
           [0010]    Accordingly, the present invention provides a charge-pump circuit for charge-share suppression comprising a first current source, a first switching element, a first load, a second switching element, a second current source, a second load, a first feedback circuit and a second feedback circuit. The first current source receives a voltage from a voltage generator and provides a current output. The first switching element is coupled between a first connecting node and an output terminal. The first switching element is controlled by an input signal. The first load is coupled between the first switching element and the output terminal. The first load receives the current and outputs an output voltage at the output terminal when the first switching element is in “On” state. The second switching element is controlled by the input signal and opposite to the first switching element. The second current source is coupled between the second switching element and ground and is coupled to the second switching element through a second connecting node. The second load is coupled between the second switching element and the output terminal. The second load receives the output voltage when the second switching element is in “On” state. The first feedback circuit maintains a constant relation between the output voltage and a voltage of the first node, and is not influenced by the status of the first and second switching elements. The second feedback circuit maintains a constant relation between the output voltage and a voltage of the second node, and is not influenced by the status of the first and second switching elements. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0011]    For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which:  
         [0012]    [0012]FIG. 1 is a block diagram illustrating a conventional phase lock loop system;  
         [0013]    [0013]FIG. 2 a  is a circuit diagram illustrating the conventional charge-pump circuit and the loop filter shown in FIG. 1;  
         [0014]    [0014]FIG. 2 b  is a diagram illustrating the charge-share problem occurring in the charge-pump circuit shown in FIG. 2 a;    
         [0015]    [0015]FIG. 3 is a circuit diagram illustrating a conventional charge-pump circuit for charge-share suppression with an operational amplifier;  
         [0016]    [0016]FIG. 4 is a circuit diagram illustrating a conventional charge-pump circuit for charge-share suppression with transistors;  
         [0017]    [0017]FIG. 5 a  is a circuit diagram illustrating a charge-pump circuit for charge-share suppression according to the embodiment of the invention;  
         [0018]    [0018]FIG. 5 b  is a circuit diagram illustrating the charge-pump circuit for charge-share when the switches S 1  and S 4  shown in FIG. 5 a  are in “On” state;  
         [0019]    [0019]FIG. 5 c  is a circuit diagram illustrating the charge-pump circuit for charge-share when the switches S 2  and S 3  shown in FIG. 5 a  are in “On” state;  
         [0020]    [0020]FIG. 6 is a block diagram illustrating a phase lock loop system comprising the charge-pump circuit for charge-share shown in FIG. 5 a;    
         [0021]    [0021]FIG. 7 a - 7   h  are schematic diagrams illustrating simulation results of two conventional charge-pump circuits and the charge-pump circuit of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]    [0022]FIG. 5 a  is a circuit diagram illustrating a charge-pump circuit for charge-share suppression according to the embodiment of the invention. As shown in FIG. 5 a,  the charge-pump circuit for charge-share suppression comprises current sources  502  and  504 , switch S 1 -S 4 , and groups of transistors  510 ,  520 ,  530 , and  540 . A voltage V dd  generated from a voltage generator is input to the current source  502 . A current I 1  is generated from the current source  502 . The current source  504  is coupled between the switch S 2  and ground. The impedance of the switch S 1  in “On” state is the same as that of the switch S 3  in “On” state. Therefore, in the embodiment, the switch S 1  is the same as the switch S 3 . The impedance of the switch S 2  in “On” state is the same as that of the switch S 4  in “On” state. Therefore, in the embodiment, the switch S 2  is the same as the switch S 4 .  
         [0023]    The switches S 1 -S 4  are co-controlled by an input signal (such as the control signal generated by the phase frequency detector shown in FIG. 1). The switch S 2  is opposite to the switch S 1 , such that when the switch S 1  is in “On” state, the switch S 2  is in “Off” state. The switch S 3  is opposite to the switch S 1 , such that when the switch S 1  is in “On” state, the switch S 3  is in “Off” state. The switch S 4  is the same as the switch S 1 , such that when the switch S 1  is in “On” state, the switch S 4  is also in “On” state.  
         [0024]    The group of transistors  510  comprises transistors Q 1a  and Q 1b . The group of transistors  520  comprises transistors Q 2a  and Q 2b . The group of transistors  530  comprises transistors Q 3a  and Q 3b . The group of transistors  540  comprises transistors Q 4a  and Q 4b . The group of transistors  510  is coupled to the switch S 1 . When the switch S 1  in “On” state, the current generated from the current source  502  and the bias voltage V b  is input to the group of transistors  510 . The group of transistors  510  generates an output voltage V c  at an output terminal N 5 . The group of transistors  520  is coupled to the switch S 2 . When the switch S 2  is “On”, the output voltage V c  and the bias voltage V b  are input to the group of transistors  520 . The group of transistors  530  is coupled between the switch S 3  and the output terminal N 5 . When the switches S 2  and S 3  are “On”, the output voltage V c  and the bias voltage V b  are input to the group of transistors  530 . The components of the group of transistors  530  are the same as the group of transistors  510 . Therefore, the transistor Q 1a  is the same as the transistor Q 3a  and the transistor Q 1b  is the same as the transistor Q 3b . The group of transistors  540  is coupled between the switch S 4  and the output terminal N 5 . When the switches S 1  and S 4  are “On, the output voltage V c  and the bias voltage V b  are input to the group of transistors  540 . The components of the group of transistors  540  is the same as the components of the group of transistors  520 . Therefore, the transistor Q 2a  is the same as the transistor Q 4a  and the transistor Q 2b  is the same as the transistor Q 4b .  
         [0025]    For a better understanding of the embodiment, reference is made to a detailed description to be read in conjunction with FIG. 5 b  and FIG. 5 c.    
         [0026]    [0026]FIG. 5 b  is a circuit diagram illustrating the charge-pump circuit for charge-share when the switches S 1  and S 4  shown in FIG. 5 a  are in “On” state. As shown in FIG. 5 b,  when the switch S 4  is in “On” state, the output voltage V c  on the node N 5  is increased because the switch S 1  is in “On” state. The voltage depleted in impedance R 2  of the switch S 4  in “On” state is V S4 . A difference in voltage between a source and a gate of the transistor Q 4b  of the group of transistors  540  is V 540 . Therefore, the voltage on the node N 2  is V c −V S4 −V 540 . At this time, if the switch S 2  changes from “Off” state to “On” state, the switch S 4  will change from “On” state to “Off” state. The voltage on the node N 2  is V c −V S4 −V 540 . Because the switch S 2  is the same as the switch S 4 , the voltage depleted in impedance R 2  of the switch S 2  in “On” state, i.e. V S2 , is equal to the voltage V S4 . The voltage on the node N 4  is V c −V 540 . Because the transistor Q 2b  is the same as the transistor Q 4b  and the transistor Q 2a  is the same as the transistor Q 4a , the difference in voltage between a source and a gate of the transistor Q 2b  of the group of transistors  520 , i.e. V 520 , is equal to the voltage V 540 . Thus, the voltage on the node N 5  is still V c . The charge-share problem does not occur.  
         [0027]    [0027]FIG. 5 c  is a circuit diagram illustrating the charge-pump circuit for charge-share when the switches S 2  and S 3  shown in FIG. 5 a  are in “On” state. As shown in FIG. 5 c,  when the switch S 3  is in “On” state, the output voltage V c  on the node N 5  is decreased because the switch S 2  is in “On” state. The voltage depleted in impedance R 1  of the switch S 3  in “On” state is V S3 . A difference in voltage between a source and a gate of the transistor Q 3b  of the group of transistors  530  is V 530 . Therefore, the voltage on the node N 1  is V c +V S3 +V 530 . At this time, if the switch S 1  changes from “Off” state to “On” state, the switch S 3  will change from “On” state to “Off” state. The voltage on the node N 1  is V c +V S3 +V 530 . Because the switch S 1  is the same as the switch S 3 , the voltage depleted in impedance R 1  of the switch S 1  in “On” state, i.e. V S1 , is equal to the voltage V S3 . The voltage on the node N 3  is V c +V 530 . Because the transistor Q 1b  is the same as the transistor Q 3b  and the transistor Q 1a  is the same as the transistor Q 3a , the difference in voltage between a source and a gate of the transistor Q 1b  of the group of transistors  510 , i.e. V 510 , is equal to the voltage V 530 . Thus, the voltage on the node N 5  is still V c . The charge-share problem does not occur.  
         [0028]    In the embodiment of the present invention, the groups of transistors  510 ,  520 ,  530 , and  540 , separately comprising a pair of transistors, are regarded as loads. In anther embodiment of the present invention, the groups of transistors, separately comprising one transistor, can be regarded as loads. If the groups of transistors separately comprising one transistor are used, however, the work range of the charge-pump circuit will be limited i.e. when the output voltage is close to V dd  or 0, the charge-pump circuit cannot work. Therefore, in the preferred embodiment of the invention, the groups of transistors separately comprising a pair of transistors are regarded as loads. The output impedance of the current source is increased and the work range of the charge-pump circuit is not changed.  
         [0029]    [0029]FIG. 6 is a block diagram illustrating a phase lock loop system comprising the charge-pump circuit for charge-share shown in FIG. 5 a.  The phase lock loop system  600  comprises a phase frequency detector  602 , a charge-pump circuit  500 , a loop filter  604 , a voltage-controlled oscillator  606  and a divider  608 . The phase frequency detector  602  receives a referenced clock F in . A controlling signal S I  is generated by the phase frequency detector  602 .  
         [0030]    The charge-pump circuit  500  is coupled to the phase frequency detector  602 . The circuit diagram of the charge-pump circuit  500  refers to FIG. 5 a.  The controlling signal S I  is input to the charge-pump circuit  500  to control the switches S 1 ˜S 4 . The output voltage V c  is output from the charge-pump circuit  500 . The loop filter  604  is coupled to an output terminal of the charge-pump circuit  500 . When the switch S 1  is in “On” state, the loop filter  604  is charged by the output voltage V c . When the switch S 2  is in “On” state, the loop filter  604  supplies the stored power to the group of transistors  520 .  
         [0031]    The voltage-controlled oscillator  606  is coupled to the charge-pump circuit  500 . The voltage-controlled oscillator  606  is controlled by the output voltage V c  and generates a required clock F out  output. The required clock F out  is fed to the divider  608 . The divider  608  generates a feedback frequency F feb . The feedback frequency F feb  is fed back to the phase frequency detector  602 .  
         [0032]    [0032]FIG. 7 a˜   7   h  are schematic diagrams illustrating simulation results of two conventional charge-pump circuits (shown in FIG. 3 and FIG. 4) and the charge-pump circuit of the present invention (shown in FIG. 5). The X axis is time, in units of seconds (s). The Y axis is the output voltage Vc, in units of volts (V).  
         [0033]    [0033]FIG. 7 a  shows the three kinds of charge-pump circuits can work between a high voltage (about 2.5 V) and a low voltage (close to 0 V) when the output voltage is increased due to charging. FIG. 7 b  illustrates simulation results of three kinds of charge-pump circuits when the output voltage of FIG. 7 a  is at the low voltage. FIG. 7 c  illustrates simulation results of three kinds of charge-pump circuits when the output voltage of FIG. 7 a  is one middle voltage. FIG. 7 d  illustrates simulation results of three kinds of charge-pump circuits when the output voltage of FIG. 7 a  is at the high voltage. Comparison between FIG. 7 b ˜ 7   d,  the charge-share problem does not occur in the charge-pump circuit of the present invention. When the output voltage of the conventional charge-pump circuit shown in FIG. 3 is close to high voltage, the charge-share problem occurs. However, the result of the charge-share suppression in the circuit of FIG. 3 completely depends upon the operational capacity of the operational amplifier. A fine design of the operational amplifier is preferred to the result of the charge-share suppression.  
         [0034]    [0034]FIG. 7 e  shows the three kinds of charge-pump circuits between a high voltage (about    2 . 5   V) and a low voltage (close to 0 V) when the output voltage is decreased because of discharge. FIG. 7 f  illustrates simulation results of three kinds of charge-pump circuits when the output voltage of FIG. 7 a  is at the high voltage. FIG. 7 g  illustrates simulation results of three kinds of charge-pump circuits when the output voltage of FIG. 7 a  is at one middle voltage. FIG. 7 h  illustrates simulation results of three kinds of charge-pump circuits when the output voltage of FIG. 7 a  is at the low voltage. Comparing FIG. 7 f ˜ 7   h,  the charge-share problem occurs in the conventional charge-pump circuit shown in FIG. 4. When the output voltage of the conventional charge-pump circuit shown in FIG. 3 is close to the high voltage, the charge-share problem occurs. The charge-share problem only occurs in the charge-pump circuit of the present invention, when the output voltage is close to the low voltage (below 100 mV) The problem of the charge-pump circuit is eliminated.  
         [0035]    The present invention provides a charge-pump circuit for charge-share suppression without adding operational amplifiers, which decrease the difficulty of designing the charge-pump circuit, and with a feedback path to resolve the problems of influence on components by different procedures and environments.  
         [0036]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.