Abstract:
A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage. 3)

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention refers to a circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor. 
     Moreover, the present invention refers to a method for reducing the threshold voltage of the transistor connected as a diode. 
     2. Discussion of the Related Art 
     The trend in transistor design is toward devices that work with lower and lower supply voltages. 
     One of the significant design limitations is that related to the threshold voltage of the MOS transistors. The threshold voltage of a transistor depends on the minimum voltage achieved with the kind of process used. 
     In particular, the threshold voltage of the transistors connected as a diode, used widely in integrated circuits, represent a significant limit for the circuits such as current mirrors, sense amplifiers, and charge pumps. 
     At the decreasing of the supply voltage a lot of the classic structures of such kind, that use transistors connected as a diode, cannot work in a proper way any more. 
     SUMMARY OF THE INVENTION 
     The aim of the present invention is to reduce the threshold voltage of transistors connected as a diode. 
     The basic idea to reach such aim is to reduce the threshold voltage of a transistor applying a voltage generator in series to the control terminal of said transistor in a way that the difference of the transistor threshold voltage and of the voltage generator is smaller than the threshold voltage of the transistor. 
     From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an opportune delta of voltage. 
     According to a first aspect, the present invention is directed to a circuit design comprising a transistor having a control terminal, a first terminal connected to a first potential, a second terminal connected to a second potential, a voltage generator able to provide a prefixed value of voltage having a third terminal and a fourth terminal, said third terminal is connected to said control terminal and said fourth terminal is connected to said first terminal. 
     According to a second aspect, the present invention is directed to a method for reducing the threshold voltage of a transistor connected as a diode having a gate terminal to which it is associated a threshold voltage that provides the application of a voltage in series to the gate terminal of said transistor. 
     Achieving a circuit design able to reduce, to a predetermined value, the threshold voltage of the equivalent transistor connected as a diode, and in an embodiment of the present invention equal to the difference of the threshold voltage of the transistors used in the circuit design, has great advantage in all circuits in which a lower voltage threshold with respect to the one offered by conventional building processes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and the advantages of the present invention will be made evident by the a following detailed description of its preferred embodiment, illustrated as a non-limiting example in the annexed drawings, wherein: 
     FIG. 1 shows a MOS transistor of p type connected as a diode according to the known art; 
     FIG. 2 shows a MOS transistor of n type connected as a diode according to the known art; 
     FIG. 3 shows a circuit design comprising a MOS transistor of p type according to a first embodiment of the present invention; 
     FIG. 4 shows a circuit design comprising a MOS transistor of n type according to a second embodiment of the present invention; 
     FIG. 5 shows a circuit design comprising a MOS transistor of p type according to a third embodiment of the present invention; 
     FIG. 6 shows a circuit design comprising a MOS transistor of n-type according to a fourth embodiment of the present invention; 
     FIG. 7 shows a circuit design comprising a MOS transistor of p-type according to a fifth embodiment of the present invention; and 
     FIG. 8 shows a circuit design comprising a MOS transistor of n-type according to a sixth embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 1, a pMOS transistor  100  is connected as a diode. It has a gate terminal  102  connected to a drain terminal  103  and to an external terminal  105  to which a voltage VB is applied. The transistor  100  has also a source terminal  101  connected to an external terminal  104  to which is applied a voltage VDD. For the working of the circuit the voltage VB must be lesser than voltage VDD less the threshold voltage of the transistor  100 . The voltages VB and VDD can be also any internal voltage of the device. 
     In FIG. 2 a nMOS transistor is connected as a diode. It has a gate terminal  202  connected to a drain terminal  201  and to an external terminal  204  to which a voltage VAA is applied. The transistor  200  has also a source terminal  203  connected to an external terminal  205  to which a voltage VBB is applied. For the working of the circuit, the voltage VAA must be greater than voltage VBB less the threshold voltage of the transistor  200 . The voltages VAA and VBB can be also any internal voltage of the device. 
     In these two configurations, at the two external terminals of the transistors  100  and  200 , the behavior is equal to that of two diodes having a threshold voltage equal to the transistors themselves. Clearly, under said voltage threshold the devices are turned off. 
     For example, the transistor  100 , having a threshold voltage VT 1 , stays in conduction if 
     
       
         
           VB&lt;VDD−VT 
           1 
         
       
     
     In an analogous way, the transistor  200 , being VAA and VBB the generic voltages applied respectively on the drain and on the source, is in conduction if 
     
       
         
           VBB&lt;VAA−VT 
         
       
     
     In FIG. 3 an embodiment of the present invention is shown. 
     A pMOS transistor  300  having a source  302  connected to an external terminal  308  to which a voltage VDD is applied, a drain  304  connected to an external terminal  309  to which a voltage VB is applied, and a gate  303  connected to the drain terminal  307  and the gate  306  of another pMOS transistor  301 . The source terminal  305 , of the transistor  301 , is connected to the drain terminal  304  of the transistor  300 . The gate  303  is also connected to a current generator  310  terminal, the other terminal of the current generator  310  is connected to the external terminal  311  connected to the voltage VNN (in the figure it is connected to the ground terminal). 
     In practice the circuit design of FIG. 3, makes provision for a first transistor  300  having a second transistor  301 , connected as diode, placed between the gate  303  (cathode of the diode) and the drain  304  (anode of the diode) of the first transistor  300  and a current generator having a terminal connected to the two gates  303  and  306  of the two transistors  300  and  301 . The equivalent diode is that seen from the external terminals  308  and  309 . 
     By means of using a process which makes provision for the possibility to build transistors having different thresholds (for example at low voltage and at high voltage) it is possible to achieve an equivalent transistor connected as a diode with a threshold equal to the difference of the thresholds of the used transistors. 
     The transistor  300  has associated a threshold VT 2  and the transistor  301  has associated a threshold VT 1 . The threshold voltage VT 2 , in absolute value, is greater than the threshold voltage VT 1 . With the circuit disposal shown in FIG. 3 an equivalent transistor connected as a diode having a threshold voltage equal to VT 2 −VT 1  is obtained. 
     When the potential VB applied to the terminal  309  increases, the potential VA of the gate terminal  303  also increases and it is equal to VB−VT 1 , that is 
     
       
         
           VA =VB−VT 
           1 
         
       
     
     The transistor  300  stays in conduction until 
     
       
           VDD−VA−VT   2 &gt;0 
       
     
     which becomes 
     
       
           VDD −( VB−VT   1 )− VT   2 &gt;0 
       
     
     from which 
     
       
           VB&lt;VDD −( VT   2   −VT   1 ) 
       
     
     which compared with the equivalent relation relevant to the transistor  100 , and that is 
     
       
         
           VB&lt;VDD−VT 
           1 
         
       
     
     to note as in the case of FIG. 3 it is obtained an equivalent transistor with lower threshold and equal to the difference of the threshold voltage of the two transistors. 
     Therefore choosing appropriately the threshold voltages of the two transistors it is possible to obtain a threshold voltage value predetermined and included between 0 and the maximum threshold obtainable with the used process. 
     The transistor  300  stays in saturation as long as the current generator  310  is dimensioned as to maintain the transistor  301  in conduction, satisfying the saturation condition of the transistor  300  which is 
     
       
         
           VB−VA&lt;VT 
           2 
         
       
     
     where VB−VA is almost equal to a VT 1  if the current generator  310  is appropriately dimensioned, therefore seen that 
     
       
         
           VT 
           2 
           &gt;VT 
           1 
         
       
     
     the above written saturation condition is surely satisfied. 
     The current generator  310 , connected to the VNN potential, supplies a current of the appropriate sign, to bias the transistor  301 , so that it could be correctly in conduction. 
     Such a circuit design is also applicable to MOS transistors of n type, as it can be seen in the FIG.  4 . 
     A nMOS transistor  400  having a drain  402  connected to an external terminal  408  to which a voltage VA is applied, a source  404  connected to an external terminal  409  connected to a VBB potential (in the figure connected to the ground terminal), and a gate  403  connected to the gate terminal  406  and of drain  405  of an other transistor nMOS  401 . The source terminal  407  of the transistor  401  is connected to a drain terminal  402  of the transistor  400 . The gate  406  is also connected to a current generator terminal  410 , the other terminal of the current generator  410  is connected to an external terminal  411  to which a voltage VPP is applied (with VPP&gt;VA). 
     The transistor  400  has associated a threshold VT 2  and the transistor  401  has associated a threshold VT 1 . The threshold voltage VT 2  is bigger than the threshold voltage VT  1 . Called VAA the voltage on the gate  403 , the transistor  400  is in conduction if it is satisfied the following relation 
     
       
         
           VAA &gt;VT 
           2 
         
       
     
     which becomes 
     
       
         
           VT 
           1 
           +VA &gt;VT 
           2 
         
       
     
     from which 
     
       
         
           VA&gt;VT 
           2 
           −VT 
           1 
         
       
     
     Note that fixed the generic voltage VA on the external terminal  408 , the equivalent diode (between the terminals  408  and  409 ) is in conduction until, being VBB the generic voltage on the terminal  409 , is 
     
       
           VBB&lt;VA −( VT   2   −VT   1 ) 
       
     
     The current generator  410 , connected to the VPP potential, supplies a current of the opportune sign, to bias the transistor  401 , so that it can be correctly in conduction. 
     Besides the transistor  400  works in a saturation zone being verified the condition 
     
       
           VDS&lt;VGS−VT 2 
       
     
     which becomes 
     
       
         
           VA&gt;VT 
           1 
           +VA−VT 
           2 
         
       
     
     which is always verified if VT 2 &gt;VT 1 . 
     If VT 1  is very close to VT 2  the working point of the transistor  400  will be on the border between the saturation region and the triode region. 
     In the practical application of the configuration of the FIG. 3, the equivalent transistor connected as a diode, having a lower threshold voltage, is that seen on the external terminals  308  and  309 , biased so as to have the potential applied to the node  309  greater than the potential applied to the node  309 . 
     In alternative to the transistor pMOS  301 , connected as a diode and represented in the FIG. 5 by a block  500  connected to the terminals  304  and  303 , it is possible to use a nMOS transistor connected as a diode (gate and drain connected to the terminal  304  and source connected to the terminal  303 ), or however a diode having its anode connected to the terminal  304  and its cathode connected to the terminal  303 . Besides, it is possible to use a resistance of the appropriate value, always applied between the nodes  304  and  303 . The value of the resistance and of the current generator  310  must be determined so as to make fall the voltage value (VT 1 ) on the resistance which will be subtracted from the transistor  300  voltage threshold. 
     In the practical application of the configuration of FIG. 4, the transistor equivalent connected as a diode, having a lower threshold voltage is that seen from the external terminals  408  and  409 , biased so as to have the potential applied to the node  408  greater than the potential applied to the node  409 . 
     In alternative to the nMOS transistor  401 , connected as a diode represented in FIG. 6 by a block  600  connected to the terminals  402  and  403 , it is possible to use a pMOS transistor connected as a diode (gate and drain connected to the terminal  402  and source connected to the terminal  403 ), or however a diode having its anode connected to the terminal  403  and its cathode connected to the terminal  402 . Besides, it is possible to use a resistance of the appropriate value, always applied between the nodes  403  and  402 . The value of the resistance and of the current generator  410  must be determined so as to make fall the voltage value (VT 1 ) on the resistance which will be subtracted from the value of the transistor  400  voltage threshold. 
     The circuit design of the transistor connected as a diode, here described in different embodiments, is equivalent to that of the FIGS. 7 and 8, in which a voltage generator, respectively  700  and  800 , is connected in series to the transistor gate terminals  300  and  400  so as (voltage of opposite sign of that of the threshold voltage) that the total voltage applied to the control terminal (gate) is lower than the threshold voltage of the transistor itself. That is the voltage generator operates at a level translation between the gate control voltage and the voltage directly applied to the gate. 
     The voltage generator, referring to the FIGS. 5 and 6, includes respectively the block  500  and the  600  and the current generator  310  and  410 . 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.