Abstract:
A multiphase DC-to-DC converter includes at least two phase circuits each having upper and lower power switches and a front-end inductor that is operative for forming a resonant tank circuit with the phase circuits to ensure zero voltage switching and minimizing power losses.

Description:
RELATED INVENTION 
   The present invention claims benefit under 35 U.S.C. §119(e) to U.S. Provisional Patent Application Ser. No. 60/538,091, filed 21 Jan. 2004, which is incorporated by reference herein. 

   FIELD OF THE INVENTION 
   The present invention relates to the field of electronic circuits, and more particularly, to DC-to-DC converters and switch mode power supplies for example, Buck converters. 
   BACKGROUND OF THE INVENTION 
   DC-to-DC converters typically are designed as switching regulated power supplies, also known as switch-mode power supplies. Some DC-to-DC converters raise voltage from a lower input voltage (step-up converters), and others lower voltage from a higher input voltage (step-down converters). One type of step-down switch mode power supply is known as a Buck converter. These devices resemble linear power supplies in some respects, but in other ways are much different. A switching power supply typically includes an energy-storage inductor, and sometimes a non-linear regulator network. This type of power supply may incorporate a regulation system in which a control element, for example, a power MOSFET switch, is switched on and off rapidly. Controlling on/off pulses may be produced by an oscillator/error amplifier/pulse-width modulator network as a controller. Thus, in a more common variety of switching regulator, the transistor switch, for example, the MOSFET, is a control element. 
   During an ON cycle, energy may be pumped into an inductor and stored in a magnetic field. When the control element is turned OFF, the energy stored in the inductor is directed into a filter and load. Various sampling circuits may sample the output voltage and feed a sample to an input of an error amplifier as part of a controller. The sample voltage may be compared with a reference voltage and an error amplifier may increase its output control voltage, which may be sent to a pulse-width modulator. The pulse-width modulator may produce a modified ON/OFF signal, for example, a square wave whose ON and OFF times are determined by the input error voltage. 
   More specific examples of DC-to-DC converters as switch mode power supplies are disclosed in commonly assigned, published U.S. patent application nos. 2003/0038614 and 2004/0070382, which are incorporated by reference herein. As noted before, a Buck converter is a specific type of step-down, DC-to-DC converter. 
   To power various microprocessors, and more particularly the next generation microprocessors, which may require a voltage of about one volt at up to 1,000 amps, the number of phases in a multiphase Buck converter has been increasing, sometimes requiring as many as eight phases. The optimum number of phases may be determined by the output current, system efficiency, transient requirements, thermal management, cost of capacitors, MOSFET performance, size restrictions, and overall system costs. A controller for Buck converters may be complicated and typically is designed as a multiphase pulse-width modulation (PWM) control integrated circuit with companion gate drivers, e.g., the HIP6301, HIP6601B, HIP6602B, HIP6603B, or HIP6604B with external MOSFETs, for example, as manufactured by the assignee of the present invention, Intersil Americas Inc. 
   Multiphase power conversion is an improvement over earlier single phase converter configurations and is used to satisfy the increasing current demands of modern microprocessors. Multiphase converters distribute the power and load current, which results in smaller and lower cost transistors with fewer input and output capacitors. This occurs because of higher effective conversion frequency with higher frequency ripple current and phase interleaving. Each phase circuit typically includes a lower MOSFET and an upper MOSFET as power switches. The requirement for decreasing the size of the converter along with the requirement for higher power densities requires an increase in the switching frequency used in the power converter. The use of a high switching frequency in these multiphase DC-to-DC converters, and especially Buck converters, however, may lead to switching losses, stresses on the power component, and EMI generation. 
   SUMMARY OF THE INVENTION 
   Accordingly, it is an advantage of the present invention that a multiphase converter with zero voltage switching is provided. 
   The present invention is advantageous and improves the efficiency of a switch mode power supply DC-to-DC converter because it is operable for zero voltage switching and may be used for non-isolated high input/low voltage output voltage converters, such as a Buck converter. The present invention uses a resonant tank circuit for a multiphase topology. The Vout/Vin DC transfer function depends on a number of phases, N. With the present invention, it is possible to achieve higher than normal output ripple cancellation than with existing Buck topologies. 
   In the present invention, the duty cycle is no longer a function of only the ON time but it is a function of the ON time and the number of phases N. The present invention detects the zero crossing, for example, using a PWM controller or other Buck controller. In the present invention, it is possible to create a zero voltage across the upper MOSFET before the power switches are turned ON or OFF. A resonant tank is created that achieves zero voltage across the power switches before they are turned ON or OFF as part of the improved topology. The front-end inductor creates a desired resonant tank circuit. 
   Typically a power switch has an inherent parasitic capacitance as part of a resonant tank. If the inherent parasitic capacitance is too small, it is possible to add a capacitor. A diode may also be added if the intrinsic diode capability of a power switch is insufficient. 
   In accordance with the present invention, the inductor at the front end does not allow the current to increase until a power switch is fully ON. There is no overlapping of current until the power switch turns ON. As to the inductor, its transition is smoother and the diode is slowly turning OFF instead of switching. Thus, it may be seen that when there is zero current across the upper power switches, there is zero voltage across the lower power switches. The inductor resonates with any capacitors of the upper power switches. Because of the resonant tank circuit, the ON time is nominally fixed, but may vary in response to the controller. A total period for each phase is changing and time is variable, notably because the ON time is variable by the controller. The present invention is also operable because there is a time period when all lower power switches are ON, and that time period is taken advantage of because of the resonance. 
   In accordance with the present invention, a multiphase DC-to-DC converter includes at least two phase circuits, each having upper and lower power switches and a front end inductor operative for forming a resonant tank circuit with the phase circuits to ensure zero voltage switching and minimizing power losses. The converter includes a controller operative with the phase circuit for detecting a zero volt crossing. The controller could be a PWM controller or other Buck controller. The resonant tank circuit is created to achieve zero voltage across the power switches, which typically are formed as field effect transistors. The converter could include a feedback signal processing circuit operative with each phase circuit and an output capacitor operative with the voltage output from the phase circuits. A capacitor may be operative with at least each upper power switch and lower power switch. A diode may also be operative with the upper power switch and lower power switch. These capacitors and diodes may be added if the intrinsic capacitance or diode function of the power switch is not enough to form the resonant tank circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the present invention will become apparent from the detailed description of the invention which follows, when considered in light of the accompanying drawings in which: 
       FIG. 1  depicts a schematic diagram of a multiphase switch mode power supply showing a front-end inductor forming a single resonant tank for a multiphase topology of the present invention. 
       FIG. 2  depicts a timing diagram for N phases in accordance with the present invention. 
       FIG. 3  depicts a graph showing Vout/Vin as a function of theta, θ, and the number of phases, N. 
       FIG. 4  depicts a graph showing Vout/Vin as a more detailed function of theta, θ, and the number of phases, N. 
       FIG. 5  depicts a schematic diagram illustrating an example of a circuit function relative to Mode 1 for the multiphase DC-to-DC converter of the present invention. 
       FIG. 6  depicts another schematic diagram similar to that of  FIG. 5 , but showing a Mode 2 operation. 
       FIG. 7  depicts a graph showing time relative to VSW and VSW_Vin and phases  1 ,  2 , . . . , N. 
       FIG. 8  depicts a graph showing simulation results for three phases that all switch at zero voltage. 
       FIG. 9  depicts a schematic diagram showing a two-phase circuit similar to that shown in  FIG. 1 , but showing greater details of functional components. 
       FIG. 9A  depicts an equivalent circuit of  FIG. 9 , showing currents IO 1  and IO 2  in respective phase structures (circuits). 
       FIG. 10  depicts an equivalent circuit of the present invention showing its function prior to Mode 1. 
       FIG. 11  depicts an equivalent circuit of the present invention showing its function at Mode 1. 
       FIG. 12A  is an equivalent circuit of the present invention showing its function at Mode 2. 
       FIG. 12B  depicts formulas governing the operation of the circuit shown in  FIG. 12A . 
       FIG. 13A  depicts an equivalent circuit of the present invention showing its function at Mode 3. 
       FIG. 13B  depicts formulas governing the operation of the circuit shown in  FIG. 13A . 
       FIG. 14  depicts a graph of a state plane diagram in accordance with the present invention. 
       FIG. 15  depicts an example of an equivalent circuit similar to the circuit depicted in  FIG. 10  and showing functional operation prior to mode  1 . 
       FIG. 16  depicts an example of an equivalent circuit similar to the circuit depicted in  FIG. 11  and showing functional operation at mode  1 . 
       FIG. 17  depicts an example of an equivalent circuit similar to the circuit depicted in  FIG. 12A  and showing functional operation at mode  2 . 
       FIG. 18  depicts an example of an equivalent circuit similar to the circuit depicted in  FIG. 13A  and showing functional operation prior to mode  3 . 
       FIG. 19  depicts a graph showing the conservation of energy relative to time in accordance with the present invention. 
       FIG. 20  depicts a three-dimensional graph showing duty versus the number of phases, N, and the ON time. 
       FIG. 21  depicts a graph showing results of a SPICE test. 
       FIG. 22  depicts a schematic diagram showing an example of a SPICE model set-up that may be used for modeling the present invention. 
       FIG. 23  depicts a graph showing a state plane, full load diagram. 
       FIG. 24  depicts a graph showing a no load state diagram. 
       FIG. 25  depicts graphs comparing efficiencies of hard and the soft switching of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in alternative embodiments. 
   The present invention improves the overall efficiency of a DC-to-DC converter system because zero voltage switching may be used for non-isolated high input voltage, and low output voltage power converters, for example, “Buck converters.” 
   There exists a need for decreasing the size of power converter, along with the need for higher power densities. This need implies an increase of switching frequency used in the power converters. The use of high switching frequency, however, leads to switching losses, imparted stresses on the power components, and EMI generation. To overcome this disadvantage, soft switching zero voltage switching is used in the present invention. 
     FIG. 1  depicts a fragmentary, block diagram of a portion of the multiphase “Buck” converter  30  as a DC-to-DC converter that includes an output inductor  32  coupled between the load for Vout and a node where the high and low side power switches (MOSFETs)  34  and  36  are connected together. High and low side power switches  34  and  36  are also termed upper and lower power switches, respectively. Different phase circuits  40 ,  40   a , . . . ,  40 N are cascaded and terminate at phase N as illustrated, to form phase circuits  40 ,  40   a , . . . ,  40 N. Phase circuits  40 ,  40   a , . . . ,  40 N include appropriate inputs and outputs  42  and  44 . Pulse-width modulation (PWM) drivers  50  are operative with power switches  34  and  36  and may each include a feedback signal processing circuit  52 . Capacitors  54  and  55  may be placed in parallel with the power switches  34  and  36  as illustrated, including an output capacitor  56  connected in parallel across the load. Power switches  34  and  36  may have intrinsic capacitance, and capacitors  54  and/or  55  may not be required. 
   In accordance with the present invention, to have zero volt switching, an input inductor  60  is placed in front of switching circuits  40 ,  40   a , . . . ,  40 N, as illustrated, and receives input voltage from an input voltage source  61 . The control scheme is also changed to detect zero voltage, as will be discussed hereinafter. Input inductor  60  resonates with capacitors  54  of upper power switches  34  in each of the N phases. 
     FIG. 9  depicts a schematic diagram similar to that of  FIG. 1 , but showing in greater detail first and second phase structures on circuits  40  and  40   a , which are cascaded. Also, each of power switches  34 ,  34   a ,  36 , and  36   a  is a power MOSFET, which includes a diode. These diodes  62 ,  62   a ,  63 , and  63   a  are labeled D 1  in first phase circuit  40  and D 2  in second phase circuit  40   a , and given the designations “up” for upper power switches  34  and  36 , or “low” for lower power switches  34   a  and  36   a . Diodes  62  and  63  could be body diodes. Power switches  34 ,  34   a ,  36 , and  36   a , realized as MOSFETs, would have some intrinsic diode capability, but additional diodes  62  and  63  may be added as necessary for achieving desired inductance as discussed hereinafter. 
     FIG. 9   a  depicts an equivalent circuit structure to that of  FIG. 9 , but without the output and showing currents Io 1  and Io 2  in the respective phase circuits  40  and  40   a . Upper and lower switches  34 ,  34   a ,  36 , and  36   a  are given the designations “up” and “low,” with first phase circuit switches  34  and  36  designated S 1 _up and S 1 _low, respectively, and second phase circuit switches  34   a  and  36   a  designated S 2 _up and S 2 _low, respectively. In a similar manner, upper and lower capacitors  54 ,  54   a ,  55 , and  55   a  are designated Cr 1 _up, Cr 2 _up, Cr 1 _low, and Cr 2 _low, respectively, and upper and lower diodes  62 ,  62   a ,  63 , and  63   a  are designated D 1 _up, D 2 _up, D 1 _low, and D 2 _low, respectively. 
     FIG. 2  depicts a timing diagram of the present invention using input inductor  60  for N phases with ON time and OFF time shown relative to the number of phases. The total time within a duty cycle is equal to the number of phases N times the ON time, ton, plus the number of phases N times the OFF time, toff. 
     FIG. 3  depicts a graph wherein the vertical axis shows Vout over Vin, and the horizontal axis shows the number of phases on the right and theta, θ, the ON time ton divided by the Off time toff, on the left. Thus,  FIG. 3  shows that the voltage OUT Vout divided by the voltage IN Vin is a function of theta θ and the number of phases N. 
     FIG. 4  depicts in greater detail Vout over Vin as a function of theta θ and the number of phases N. 
     FIG. 5  depicts a conceptual schematic diagram demonstrating the function of input inductor  60  of  FIG. 1  in mode  1  with upper capacitor  54  and showing a flow of current Io.  FIG. 6  depicts a similar conceptual schematic diagram demonstrating a mode  2  operation.  FIG. 7  depicts a graph showing zero volt switch points (ZVS) as predetermined times, and the various switching voltage VSW points and upper_drive switching relative to different phases.  FIG. 8  depicts the simulation results for three phases, all shown switching at zero voltage. 
   With reference again to  FIGS. 1 through 9   a , assume that there are N phases, such as shown in  FIG. 1 , and that input inductor  60  is large enough so that input voltage source  61  appears as a constant current source. At a time t=0, the cycle starts. Upper power switch  34  of phase  1  is ON, and lower power switch  36  is OFF. Coincidentally, for the (N-1) other phases, upper powers switches  34   a , . . . ,  34 N are off, and lower power switches  36   a , . . . ,  36 N are ON. The operation will differ depending on the modes and the time, t. 
   With mode  1 , at t=t on , the phase  1  upper power switch  34  will be turned OFF, and body diode  63  of lower power switch  36  will be turned on. As a result, lower power switch  36  of phase  1  would be turned on at zero voltage. After that time, all lower power switches  36 ,  36   a , . . . ,  36 N of the N phases would be ON and upper power switches  32 ,  34   a , . . . ,  34 N would be OFF. 
   At mode  2 , the N capacitors  54 ,  54   a , . . . ,  54 N will start resonating with input inductor  60 , and the resonant time is toff, when input switching voltage VSW_Vin and switching voltage VSW are equal phase  2  may be turned on at zero voltage. The cycle continues for all N phases. When upper power switches  34 ,  34   a , . . . ,  34 N are OFF and all lower power switches  36 ,  36   a , . . . ,  36 N are ON, the next mode of operation may start. 
     FIGS. 5 and 6  depict functional circuit representations of a single phase circuit  40 ,  40   a , or  40 N.  FIG. 8  depicts a simulation graph of the three phases. As may be seen from the simulation graph, the three phases shown all switch at zero voltage. The steady state analysis of converter  30  shows that: 
                   Vout   Vin     =     1       N   ×   θ     +   N               (   1   )               
where θ=ton/toff, for example, as shown in  FIG. 3 , for a higher input voltage Vin and lower output voltage Vout. It is possible to use more phases to achieve a practical duty cycle without the requirement for the down stage. A two-phase (or stage) converter  30  is shown in  FIG. 9 , and an equivalent circuit of two-phase converter  30  is shown in  FIG. 9A . Two phase structures  40  and  40   a  are shown with the addition of diodes  62  (D 1 _up) and  63  (D 1 _low) and diodes  62   a  (D 2 _up) and  63   a  (D 2 _low) for each power switching phase structure  40  and  40   a , respectively, in parallel with capacitors  54  (Cr 1 _up),  56  (Cr 1 _low),  54   a  (Cr 2 _up), and  56   a  (Cr 2 _low), respectively, and in parallel with power switches  34  (S 1 _up),  36  (S 1 _low),  34   a  (S 2 _up), and  36   a  (S 2 _low), respectively. For phase structure  40 , Cr 1 _up capacitor  54  is in parallel with D 1 _up diode  62 . For phase structure  40   a , Cr 2 _up capacitor  54   a  is in parallel with D 2 _up diode  62   a . Upper and lower switches  34  and  36  or  34   a  and  36   a  are illustrated in each phase structure  40  and  40   a , respectively. Functional operation of the circuit prior to Mode 1, when t&lt;t 0 , is shown in  FIG. 10 .
 
   At t 0 , as shown in  FIG. 11 , s 1 _up switch  34  is turned on for Mode 1 with the following initial condition: 
                     i   lr     ⁡     (   0   )       =     I   ro             (   2   )                   V   Cr1_up     ⁡     (   0   )       =   0           (   3   )                   i   lr     ⁡     (   t   )       =         Vin   L     ⁢           ⁢   t     +     I   ro               (   4   )               
At t 2 , the inductor current reaches the output current (Mode 2), which is reflected in the functional drawing of  FIG. 12A . This condition may be explained by the formula shown in  FIG. 12B . At Mode 3, both switches  34  and  36  are ON, as best shown in the functional circuit diagram of  FIG. 13A , with the initial condition explained by the formula shown in  FIG. 13B .
 
   A state plane diagram is shown in  FIG. 14 . This diagram shows the various centers of operation for Mode 2 and Mode 3. 
   The present invention allows zero voltage switching. Referring again to  FIGS. 1 and 9 , an example of a two-stage converter  30  ( FIG. 1 ) with zero voltage switching and the function of converter  30  may be expressed as: 
   
     
       
         
           
             
               
                 
                   I 
                   o1 
                 
                 = 
                 
                   
                     I 
                     o2 
                   
                   = 
                   
                     Io 
                     2 
                   
                 
               
             
             
               
                 ( 
                 5 
                 ) 
               
             
           
           
             
               
                 VD1_low 
                 = 
                 
                   VD2_low 
                   = 
                   0 
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
           
             
               
                 Cr1_up 
                 = 
                 
                   Cr2_up 
                   = 
                   Cr 
                 
               
             
             
               
                 ( 
                 7 
                 ) 
               
             
           
         
       
     
   
   When the mode of operation is t&lt;t 0 =0, the mode of operation may be expressed as a circuit function depicted in  FIG. 15 . The voltage across upper switch  34  of phase  1  (S 1 _up) is zero. This may be expressed as: switch  34  (S 1 _up) OFF; switch  34   a  (S 2 _up) OFF; switch  36  (S 1 _low) ON; switch  36   a  (S 2 _low) ON; diode  63  (D 1 _low) OFF; and diode  63   a  (D 2 _low) OFF. 
   Mode 1 of operation, when 0&lt;t&lt;t 1 , is depicted in  FIG. 16 . This may be expressed as: switch  34  (S 1 _up) ON; switch  36  (S 1 _low) OFF; switch  34   a  (S 2 _up) OFF; switch  26   a  (S 2 _low) ON; diode  63  (D 1 _low) ON; and Diode  63   a  (D 2 _Low) OFF. For purposes of this example: 
                 Z   =         L   r       C   r                 (   8   )                 ω   o     =     1         L   r     ⁢     C   r                   (   9   )                   i   r     ⁡     (   0   )       =     I   r1             (   10   )               
where the normalized value for V is:
 
                 V   =     V     V   in               (   11   )               
and for i(t) is:
 
                   i   ⁡     (   t   )       =         i   ⁡     (   t   )       ⁢           ⁢   Z       V   in               (   12   )               
This results in:
 
   
     
       
         
           
             
               
                 
                   
                     i 
                     r 
                   
                   ⁡ 
                   
                     ( 
                     t 
                     ) 
                   
                 
                 = 
                 
                   
                     
                       
                         V 
                         in 
                       
                       ⁢ 
                       T 
                     
                     
                       L 
                       r 
                     
                   
                   + 
                   
                     I 
                     r1 
                   
                 
               
             
             
               
                 ( 
                 13 
                 ) 
               
             
           
           
             
               
                 
                   
                     i 
                     lrn 
                   
                   ⁡ 
                   
                     ( 
                     t 
                     ) 
                   
                 
                 = 
                 
                   
                     
                       ω 
                       o 
                     
                     ⁢ 
                     t 
                   
                   + 
                   
                     I 
                     r1n 
                   
                 
               
             
             
               
                 ( 
                 14 
                 ) 
               
             
           
         
       
     
   
   Mode 2 of operation, when t 1 &lt;t&lt;t 2 , is depicted in  FIG. 17 . This may be expressed as: switch  34  (S 1 _up) ON; switch  36  (S 1 _low) OFF; switch  34   a  (S 2 _up) OFF; switch  36   a  (S 2 _low) ON; diode  63  (D 1 _low) OFF; and diode  63   a  (D 2 _Low) OFF. At an initial condition: 
                           i   r     ⁡     (     t   1     )       =     Io   2                 V   cr     ⁡     (   t1   )       =   0                 (   15   )               
At a normalized solution:
 
   
     
       
         
           
             
               
                 
                   
                     V 
                     in 
                   
                   - 
                   
                     
                       L 
                       r 
                     
                     ⁢ 
                     
                       
                         ∂ 
                         
                           
                             i 
                             r 
                           
                           ⁡ 
                           
                             ( 
                             t 
                             ) 
                           
                         
                       
                       
                         ∂ 
                         t 
                       
                     
                   
                   - 
                   
                     
                       V 
                       Cr 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 = 
                 0 
               
             
             
               
                 ( 
                 16 
                 ) 
               
             
           
           
             
               
                 
                   
                     V 
                     crn 
                   
                   ⁡ 
                   
                     ( 
                     t 
                     ) 
                   
                 
                 = 
                 
                   1 
                   - 
                   
                     cos 
                     ⁡ 
                     
                       ( 
                       
                         
                           ω 
                           o 
                         
                         ⁢ 
                         t 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 17 
                 ) 
               
             
           
           
             
               
                 
                   
                     
                       i 
                       r 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                   - 
                   
                     
                       C 
                       r 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       
                         ∂ 
                         
                           
                             V 
                             Cr 
                           
                           ⁡ 
                           
                             ( 
                             t 
                             ) 
                           
                         
                       
                       
                         ∂ 
                         t 
                       
                     
                   
                   - 
                   
                     
                       I 
                       o 
                     
                     2 
                   
                 
                 = 
                 0 
               
             
             
               
                 ( 
                 18 
                 ) 
               
             
           
           
             
               
                 
                   
                     i 
                     rn 
                   
                   ⁡ 
                   
                     ( 
                     t 
                     ) 
                   
                 
                 = 
                 
                   
                     sin 
                     ⁡ 
                     
                       ( 
                       
                         
                           ω 
                           o 
                         
                         ⁢ 
                         t 
                       
                       ) 
                     
                   
                   + 
                   
                     
                       I 
                       on 
                     
                     2 
                   
                 
               
             
             
               
                 ( 
                 19 
                 ) 
               
             
           
         
       
     
   
   Mode 3 of operation, when t 2 &lt;t&lt;t 3 , is depicted in  FIG. 18 . This may be expressed as: switch  34  (S 1 _up) OFF; switch  36  (S 1 _low) OFF; switch  34   a  (S 2 _up) OFF; switch  36   a  (S 2 _low) ON; diode  63  (D 1 _low) OFF; and diode  63   a  (D 2 _low) OFF. The initial condition is:
 
 i   r ( t   2 )= I   r2   (20)
 
 V   Cr ( t 2)= Vm   (21)
 
The normalized solution is:
 
   
     
       
         
           
             
               
                 
                   
                     V 
                     in 
                   
                   - 
                   
                     
                       L 
                       r 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       
                         ∂ 
                         
                           
                             i 
                             r 
                           
                           ⁡ 
                           
                             ( 
                             t 
                             ) 
                           
                         
                       
                       
                         ∂ 
                         t 
                       
                     
                   
                   - 
                   
                     
                       V 
                       Cr 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                 
                 = 
                 0 
               
             
             
               
                 ( 
                 22 
                 ) 
               
             
           
           
             
               
                 
                   
                     
                       i 
                       r 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                   - 
                   
                     
                       C 
                       r 
                     
                     ⁢ 
                     
                       
                         ∂ 
                         
                           
                             V 
                             Cr 
                           
                           ⁡ 
                           
                             ( 
                             t 
                             ) 
                           
                         
                       
                       
                         ∂ 
                         t 
                       
                     
                   
                   - 
                   
                     
                       I 
                       o 
                     
                     2 
                   
                 
                 = 
                 0 
               
             
             
               
                 ( 
                 23 
                 ) 
               
             
           
           
             
               
                 
                   
                     V 
                     crn 
                   
                   ⁡ 
                   
                     ( 
                     t 
                     ) 
                   
                 
                 = 
                 
                   1 
                   + 
                   
                     
                       sin 
                       ( 
                       
                         
                           
                             ω 
                             o 
                           
                           
                             2 
                           
                         
                         ⁢ 
                         t 
                       
                       ) 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       ( 
                       
                         Vmn 
                         - 
                         1 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 24 
                 ) 
               
             
           
           
             
               
                 
                   
                     i 
                     rn 
                   
                   ⁡ 
                   
                     ( 
                     t 
                     ) 
                   
                 
                 = 
                 
                   
                     
                       2 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       sin 
                       ( 
                       
                         
                           
                             ω 
                             o 
                           
                           
                             2 
                           
                         
                         ⁢ 
                         t 
                       
                       ) 
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         - 
                         Vmn 
                       
                       ) 
                     
                   
                   + 
                   
                     
                       cos 
                       ( 
                       
                         
                           
                             ω 
                             o 
                           
                           
                             2 
                           
                         
                         ⁢ 
                         t 
                       
                       ) 
                     
                     ⁢ 
                     
                       I 
                       r2n 
                     
                   
                 
               
             
             
               
                 ( 
                 25 
                 ) 
               
             
           
         
       
     
   
   The state plane diagram for this type of function is depicted in  FIG. 14 . Points are shown for the center of operation of Mode 2, a graph for Mode 2 during ON time, the center of operation for Mode 3, a graph when tie is OFF, and a point for Mode 1 during inductor  60  charge. Analytical solutions are: 
   
     
       
         
           
             
               
                 
                   I 
                   r1n 
                 
                 = 
                 
                   
                     
                       2 
                     
                     ⁢ 
                     
                       ( 
                       
                         
                           cos 
                           ⁡ 
                           
                             ( 
                             
                               
                                 ω 
                                 0 
                               
                               ⁢ 
                               ton 
                             
                             ) 
                           
                         
                         - 
                         
                           cos 
                           ⁡ 
                           
                             ( 
                             
                               
                                 1 
                                 2 
                               
                               ⁢ 
                               
                                 ω 
                                 0 
                               
                               ⁢ 
                               
                                 2 
                               
                               ⁢ 
                               toff 
                             
                             ) 
                           
                         
                       
                       ) 
                     
                   
                   
                     sin 
                     ⁡ 
                     
                       ( 
                       
                         
                           1 
                           2 
                         
                         ⁢ 
                         
                           ω 
                           0 
                         
                         ⁢ 
                         
                           2 
                         
                         ⁢ 
                         toff 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 26 
                 ) 
               
             
           
           
             
               
                 
                   I 
                   rn2 
                 
                 ⁢ 
                 
                   
                     
                       ( 
                       
                         
                           
                             cos 
                             ⁡ 
                             
                               ( 
                               
                                 
                                   1 
                                   2 
                                 
                                 ⁢ 
                                 
                                   ω 
                                   0 
                                 
                                 ⁢ 
                                 
                                   2 
                                 
                                 ⁢ 
                                 toff 
                               
                               ) 
                             
                           
                           ⁢ 
                           
                             cos 
                             ⁡ 
                             
                               ( 
                               
                                 
                                   ω 
                                   0 
                                 
                                 ⁢ 
                                 ton 
                               
                               ) 
                             
                           
                         
                         - 
                         1 
                       
                       ) 
                     
                     ⁢ 
                     
                       2 
                     
                   
                   
                     sin 
                     ⁡ 
                     
                       ( 
                       
                         
                           1 
                           2 
                         
                         ⁢ 
                         
                           ω 
                           0 
                         
                         ⁢ 
                         
                           2 
                         
                         ⁢ 
                         toff 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 27 
                 ) 
               
             
           
           
             
               
                 
                   V 
                   mn 
                 
                 = 
                 
                   1 
                   - 
                   
                     cos 
                     ⁡ 
                     
                       ( 
                       
                         
                           ω 
                           0 
                         
                         ⁢ 
                         ton 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 28 
                 ) 
               
             
           
           
             
               
                 
                   I 
                   on 
                 
                 = 
                 
                   2 
                   ⁢ 
                   
                     
                       
                         
                           - 
                           
                             sin 
                             ⁡ 
                             
                               ( 
                               
                                 
                                   ω 
                                   0 
                                 
                                 ⁢ 
                                 ton 
                               
                               ) 
                             
                           
                         
                         ⁢ 
                         
                           sin 
                           ⁡ 
                           
                             ( 
                             
                               
                                 1 
                                 2 
                               
                               ⁢ 
                               
                                 ω 
                                 0 
                               
                               ⁢ 
                               
                                 2 
                               
                               ⁢ 
                               toff 
                             
                             ) 
                           
                         
                       
                       - 
                       
                         2 
                       
                       + 
                       
                         
                           2 
                         
                         ⁢ 
                         
                           cos 
                           ⁡ 
                           
                             ( 
                             
                               
                                 1 
                                 2 
                               
                               ⁢ 
                               
                                 ω 
                                 0 
                               
                               ⁢ 
                               
                                 2 
                               
                               ⁢ 
                               toff 
                             
                             ) 
                           
                         
                         ⁢ 
                         
                           cos 
                           ⁡ 
                           
                             ( 
                             
                               
                                 ω 
                                 0 
                               
                               ⁢ 
                               ton 
                             
                             ) 
                           
                         
                       
                     
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         
                           
                             1 
                             2 
                           
                           ⁢ 
                           
                             ω 
                             0 
                           
                           ⁢ 
                           
                             2 
                           
                           ⁢ 
                           toff 
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 29 
                 ) 
               
             
           
           
             
               
                 
                   T 
                   s 
                 
                 = 
                 
                   
                     2 
                     ⁢ 
                     ton 
                   
                   + 
                   
                     2 
                     ⁢ 
                     toff 
                   
                   + 
                   
                     
                       
                         I 
                         on 
                       
                       - 
                       
                         I 
                         r1n 
                       
                     
                     
                       ω 
                       0 
                     
                   
                 
               
             
             
               
                 ( 
                 30 
                 ) 
               
             
           
         
       
     
   
   Simplified equations for the circuit functions may be expressed as using:
 
θ=ω o toff  (31)
 
β=ω o ton  (32)
 
                   I   r1n     =         2     ⁢     (       cos   ⁡     (   β   )       -     cos   ⁡     (     θ     2       )         )         sin   ⁡     (     θ     2       )                 (   33   )                 I   r2n     =         2     ⁢     (         cos   ⁡     (     θ     2       )       ⁢     cos   ⁡     (   β   )         -   1     )         sin   ⁡     (     θ     2       )                 (   34   )                 I   on     =       2   ⁢         2   ⁢     (         cos   ⁡     (     θ     2       )       ⁢     cos   ⁡     (   β   )         -   1     )           sin   ⁡     (     θ     2       )           -     2   ⁢     sin   ⁡     (   β   )                   (   35   )                 V   mn =1−cos (β)  (36)   Tsω   o =2β+2 θ+I   on   −I   r1n   (37) 
   The circuit functions with conservation of energy are expressed as: 
                   P   in_n     =       2   Ts     ⁢     (         ∫   0   o     ⁢         i   rn     ⁡     (   t   )       ⁢     ∂   t         =         ∫   0   1     ⁢         i   rn     ⁡     (   t   )       ⁢     ∂   t         ⁢           +       ∫   0   Ts     ⁢         i   rn     ⁡     (   t   )       ⁢     ∂   t             )               (   38   )               P Out     —     n =I on D  (39) 
Where D is:
 
                     V   o       V   in       ⇔     Duty   ⁢           ⁢   Cycle             (   40   )               
Using the conservation of energy, it is possible to obtain D as a function of β and θ:
   D=f (β, θ)  (41) 
   A graphical example of this conservation of energy is depicted in  FIG. 19 , where L r =10 nH, C r =10 nF, N=2, and toff=90 nS. 
   Generalized solutions for the duty, ON time, and number of phases N are depicted in  FIG. 20 . This three-dimensional graph shows duty on the vertical axis y and the number of phases N and ON time on the lower axes x and Z. The SPICE (Simulation Program With Integrated Circuit Emphasis) result is depicted in  FIG. 21 . This graph shows ON time on the horizontal axis and voltage on the vertical axis. The V-switch, gate drive, and next phase gate drive are shown. 
   A SPICE model set-up circuit is depicted in  FIG. 22 . The SPICE model set-up shows various integrated circuits as U51 and U50 operative with various components and IC&#39;s. The SPICE model, of course, is a computerized modeling technique for the design of integrated circuits. By entering details of the circuit using the SPICE model as illustrated, it is possible to check for frequency and phase response of the circuit and check the circuit response over a set period of time as a transient analysis as compared to an AC analysis. There are also different analyses to check effects of temperature variations and noise. By using the SPICE model as shown in  FIG. 22 , the design was tested “on paper” and then prototyped. 
   A graph showing a state plane full load is depicted in  FIG. 23 . This graph shows modes 1, 2 and 3. A no load state diagram is depicted in  FIG. 24 .  FIG. 25  depicts an efficiency comparison between hard and soft switching. 
   Many modifications and other embodiments of the invention will be apparent to those of ordinary skill in the art and having the benefit of the teachings presented herein. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications thereto and alternative embodiments are intended to be included within the scope of the appended claims.