Abstract:
The two output currents (INP, IN) which are produced by a current source digital/analog converter (DAC) are supplied to the two halves of a symmetrical transimpedance amplifier. The input current (INP, IN) is supplied to a first stage, which is formed by a first transistor (N 2 ), and a potential at the output of the first stage is supplied to a second stage, which is formed by a second transistor (N 3 ), and the output voltage (VOUT, VOUTP) is formed by a potential at the output of the second stage. The output of the second stage is coupled to the output of the first stage through a Miller capacitor (Cm). The output of the transimpedance amplifier is coupled to its input by means of a connecting line which contains a feedback resistor (Rf).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation of co-pending International Application No. PCT/DE2004/000187 filed Feb. 4, 2004, which designates the United States of America, and claims priority to German application number 103 009 877.1 filed Mar. 6, 2003, the contents of which are hereby incorporated by reference in their entirety. 
     
    
     TECHNICAL FIELD  
       [0002]     The present invention relates to a transimpedance amplifier for production of an output voltage from an input current, with the input current being formed in particular by the output current from a digital/analog converter (DAC).  
       BACKGROUND  
       [0003]     In wire-free baseband applications such as UMTS, WLAN as well as digital television and Bluetooth, digital data is converted to analog signals by means of a digital/analog converter (DAC). The analog signals are then up-mixed to the carrier frequency, are post-filtered and are emitted by means of the power amplifier via the antenna to the air interface. In the baseband applications that have been mentioned, broadband modulation methods such as OFDM, DSSS or other broadband modulation methods are used. These modulation methods make better use of the channel bandwidth and thus achieve higher data rates. The linearity, the phase response and attenuation response of the DAC output are subject to stringent requirements resulting from the broadband modulation methods.  
         [0004]      FIG. 1  shows a 9-bit current source DAC with 512 individual current sources. Each current source has a switch, which receives a binary signal from a decoder. This signal determines whether a current source is connected to the node Vout,p or to the node Vout,n. If the digital word is altered by an LSB (Least Significant Bit), a current source is switched from Vout,p to Vout,n. Depending on the bit number, the DAC is fully segmented or partially segmented. If the digital word (000000000) is applied to the DAC,  512  current sources are connected to Vout,n, and no current sources are connected to Vout,p. The digital word (111111111) is applied when fully driven, with all of the current sources being connected to Vout,p and none to Vout,n. As can be seen from  FIG. 1 , the output currents are converted across the resistors to a differential output voltage Voutdiff=Vout,p−Vout,n.  
         [0005]     Various circuit arrangements by means of which the two DAC output currents can be converted to a differential output voltage are known from the prior art. The simplest option is to convert the output currents from the DAC directly to two output voltages across the two resistors illustrated in  FIG. 1 . This solution is highly linear and does not produce any additional harmonics. The phase and attenuation response are influenced only by that pole which is produced across the resistors with the load capacitances. Another known circuit arrangement amplifies the difference voltage across the DAC output resistors using an inverting differential amplifier circuit. It has been found that these known circuit arrangements do not satisfactorily ensure one major aim, specifically the maintenance of the phase and attenuation profile. For this purpose, it is necessary for the converter to have a high gain/bandwidth product, and for no additional poles and null points to be introduced into the current/voltage transfer function during conversion of the DAC output current to the output voltage. The known circuits arrangements do not have these characteristics to an adequate extent.  
       SUMMARY  
       [0006]     Accordingly, one object of the present invention is to specify an apparatus by means of which an input current can be converted to an output voltage with little power consumption, a high gain/bandwidth product and without the introduction of additional poles and null points into the current/voltage transfer function. In particular, the apparatus should be suitable for conversion of the two output currents from a digital/analog current source converter to two output voltages.  
         [0007]     The apparatus according to the invention comprises a transimpedance amplifier to which the output current from a digital/analog converter (DAC) can be supplied as the input current, and which produces an output voltage in response to this. The transimpedance amplifier can be designed such that it can be supplied with two input currents, which are the two output currents of a DAC, and such that it produces two output voltages in response to this.  
         [0008]     The transimpedance amplifier according to the invention has a first stage for production of a first voltage signal from the input current that is supplied. The transimpedance amplifier according to the invention also has a second stage for production of a second voltage signal from the first voltage signal. A capacitor for frequency compensation is coupled between the output of the first stage and the output of the second stage. A feedback resistor is connected between the input and the output of the transimpedance amplifier.  
         [0009]     As will be explained in further detail below, the transimpedance amplifier according to the invention is based on a Miller operational amplifier as known from the prior art. In an operational amplifier such as this, any deterioration in the frequency response caused by parasitic capacitances (Miller effect) is compensated for (frequency compensation) by connection of a Miller capacitor between the output of a first amplification stage, and the output of a second amplification stage. In the case of a fully differential embodiment of the transimpedance amplifier according to the invention, a Miller operational amplifier such as this is modified in such a way that the difference pair of the input transistors is removed, and the DAC output currents are fed in at the same point at which the difference pair has fed in the currents. Feeding the DAC output currents in directly means that the output signal is no longer distorted, since this overcomes the current limiting of the difference pair that occurs as a result of the current source in the Miller operational amplifier. For this reason, the transimpedance amplifier circuit according to the invention also has no inherent limiting of the rate of rise of the output voltage (slew rate), which causes output signal distortion.  
         [0010]     One preferred embodiment of the transimpedance amplifier according to the invention is of a fully differential design and has two mutually symmetrical amplifier circuits, to which two input currents can be supplied and which produce a first and a second output voltage. A transimpedance amplifier such as this can be supplied with the two output currents from a current source digital/analog converter.  
         [0011]     According to a further embodiment of the transimpedance amplifier according to the invention, the first stage has a first transistor, with the input current being supplied to the input connection of the first transistor, and with the potential of the output connection of the first transistor forming the first voltage signal.  
         [0012]     According to a further embodiment of the transimpedance amplifier according to the invention, the second stage has a second transistor, with the first voltage signal being supplied to the control connection of the second transistor, and with the potential at an output connection of the second transistor forming the second voltage signal. The output voltage is formed from the second voltage signal, or is derived from it.  
         [0013]     According to a further embodiment, a first current source which, in particular, is formed by a transistor is arranged between a first node, at which the input current is injected into the first stage, and a first reference ground potential.  
         [0014]     According to a further embodiment, a second current source which, in particular, is formed by two series-connected transistors, is arranged between a further node, at which the capacitor is connected to the output of the first stage, and a second reference ground potential.  
         [0015]     The first current source preferably has a relatively low output impedance, and the second current source has a relatively high output impedance.  
         [0016]     According to a further embodiment, an additional resistor can also be connected in series with the Miller capacitor. Furthermore, a further Miller capacitor can also be connected between a node, which is located between the current source transistors, and the output of the transimpedance amplifier.  
         [0017]     The invention likewise relates to an apparatus for production of an analog voltage signal from a digital input signal, with the apparatus having a transimpedance amplifier according to the invention and a current source digital/analog converter, whose output current is supplied to the transimpedance amplifier.  
         [0018]     This apparatus is preferably designed such that the digital/analog converter produces two output currents and, as already mentioned above, the transimpedance amplifier is designed as a fully differential circuit, to two inputs of which the two output currents from the DAC are supplied and which produces two output voltages in response to this.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The invention will be explained in detail in the following text with reference to the drawings, in which:  
         [0020]      FIG. 1  shows a 9-bit current source DAC according to the prior art;  
         [0021]      FIG. 2  shows a Miller operational amplifier according to the prior art;  
         [0022]      FIG. 3  shows a first embodiment of a transimpedance amplifier according to the invention;  
         [0023]      FIG. 4  shows one half of the circuit illustrated in  FIG. 3 , without a feedback resistor;  
         [0024]      FIG. 5  shows a Bode plot for one embodiment of a transimpedance amplifier according to the invention;  
         [0025]      FIG. 6  shows a second embodiment of a transimpedance amplifier according to the invention; and  
         [0026]      FIG. 7  shows a third embodiment of a transimpedance amplifier according to the invention.  
     
    
     DETAILED DESCRIPTION  
       [0027]      FIG. 2  shows a conventional Miller operational amplifier according to the prior art. The operational amplifier is supplied with two input voltages VINP and VINN, and converts these to two output voltages VOUTN and VOUTP. The two input voltages VINP and VINN are in each case applied to the control electrode (gate) of transistors in a differential amplifier input stage. The transistors are supplied with the current from a current source Io. The rest of the description refers to  FIG. 3 .  
         [0028]      FIG. 3  shows a first embodiment of a transimpedance amplifier according to the invention. One major change from the operational amplifier shown in  FIG. 2  is that the difference pair of the input amplifier stage is removed, and input currents are fed in at the same point at which the difference pair has fed in the currents Ip and In. In the illustrated case, the two output currents from a current source DAC are used as the input currents INP and IN, as has been explained in the introduction with reference to  FIG. 1 . The circuit is designed to be symmetrical, so that the input currents INP and IN are supplied to two identical amplifier circuits. Since the DAC output currents are fed in directly, with the transimpedance amplifier according to the invention, the output signal is no longer distorted, since the current limiting of the difference pair has been eliminated by the current source Io. The transimpedance amplifier according to the invention thus has no inherent limiting of the rate of rise of the output voltage (slew rate), which distorts the output signal.  
         [0029]     The input currents are in each case supplied to one input connection of a first transistor N 2  which, in its circuitry, acts as a cascode transistor. The potential at the output connection of the first transistor N 2  is applied to the control electrode of a second transistor N 3 , which is connected between the two supply voltages VSS and VDD. The potential which is formed at the electrode connection of the second transistor N 3  on the side of the supply voltage VDD forms the output voltage of the transimpedance amplifier.  
         [0030]     In the case of the transimpedance amplifier according to the invention as shown in  FIG. 3 , as well as in the case of the Miller operational amplifier as shown in  FIG. 2 , a so-called Miller capacitance Cm is connected between the output of the first stage, that is to say at the output of the first transistor N 2 , and the output of the second stage, in the present case, that is to say the output of the transimpedance amplifier, for frequency compensation reasons.  
         [0031]     A further major modification in comparison to the Miller operational amplifier shown in  FIG. 2  is that a feedback resistor Rf is connected between the input and the output of the transimpedance amplifier. A connecting line between the output connections and the input connections (which carry the input currents INP and IN) is thus in each case connected to a feedback resistor Rf in each of the two symmetrical branches of the embodiment shown in  FIG. 3 .  
         [0032]     The transimpedance amplifier shown in  FIG. 3  has no common-mode control. The output common-mode level is set by the voltage across the cascode transistor N 2  and by the steady-state equalization current which flows through the feedback resistor Rf. The voltage across the feedback resistor Rf is constant only when all of the currents which set the operating points of the transistors in the transimpedance amplifier and the DAC output currents are proportional to the bandgap voltage, and are reciprocally proportional to the feedback resistance. The transistors P 1  and P 2  form a relatively high output impedance current source. The transistor N 1  is a reduced output impedance current source. The cascode transistor N 2  guarantees that the summation point is exactly 200 mV above the supply potential VSS. The equalization current mentioned above through the feedback resistor Rf is set by the current source P 1 /P 2  and by the current source formed by the transistor N 1 . If the currents between P 1 /P 2  and N 1  are not the same, then ΔI flows through the feedback resistor Rf. This effect allows the common-mode level to be set.  
         [0033]     The characteristics of the new Miller frequency compensation for the transimpedance amplifier according to the invention will be explained in more detail with reference to  FIG. 4 . The illustrated circuit is one of the two halves of the symmetrical transimpedance amplifier circuit without a feedback resistor, as shown in  FIG. 3 . The Miller capacitor Cm in this illustration is formed by the capacitor C 3 . A load which is connected to the output of the transimpedance amplifier and is represented by a load capacitor CL and a load resistor RL connected in parallel with it is also taken into account.  
         [0034]     If a small-signal analysis is carried out using the Y matrix method on the circuit shown in  FIG. 4 , then the loop gain A*β, which governs the stability, is defined by an equation with two null points and four poles.  
         A   ⁢           ⁢   β     =           y   21     ⁢     y   21           y   11     ⁢     y   22         =         gm   N2     ⁢       gm   N3     ⁡     (     1   +     s   /     z   1         )       ⁢     (     1   -     s   /     z   2         )           gds   N2     ⁢       g   L     ⁡     (     1   +     s   /     p   1         )       ⁢     (     1   +     s   /     p   2         )     ⁢     (     1   +     s   /     p   3         )     ⁢     (     1   +     s   /     p   4         )               
 
         [0035]     The equations for the two null points:  
               z   1     =       gds   N2       C   3                     z   2     =       gm   N3       C   3                 
 
         [0036]     The equations for the four poles:  
               p   1     =       gds   N2         R   f     ⁢     gm   N2     ⁢     C   3                       p   2     =         g   L     ⁢     gds   N2           gm   N2     ⁢     C   3                       p   3     =       gm   N3           C   L     ⁡     (     1   +       C   2       C   3         )       +     C   2                       p   4     =       gm   N2       C   1                   GBW   =     1       R   f     ⁢     C   3                   
 
                               TABLE 1                                   Components   Parameter 1   Parameter 2                           NMOS transistor N1   gds N1  = 1.35 mS               NMOS transistor N2   gds N2  = 450 μs   gm N2  = 18.3 mS           NMOS transistor N3   gds N3  = 2.5 mS   gm N3  = 65 mS           PMOS transistor P1   gds P1  = 180 μS           PMOS transistor P2   gds P2  = 150 μS   gm P2  = 13 mS           PMOS transistor P3   gds P3  = 165 μS           Capacitance C1   C 1  = 2 pF           Capacitance C2   C 2  = 400 fF           Capacitance C3   C 3  = 10 pF           Capacitance CL   C L  = 20 pF           Resistor Rf   R f  = 600 Ω           Resistor RL   R L  = 1 kΩ                      
 
         [0037]     The poles and null points illustrated in Table 2 are obtained from the small-signal parameters listed in Table 1.  
                   TABLE 2                           Null points                     z   1     =         450   ⁢           ⁢   μS       10   ⁢           ⁢   pF       =     45   ⁢           ⁢     Mrad   /   s                           z   1     =         65   ⁢           ⁢   mS       10   ⁢           ⁢   pF       =     6.5   ⁢           ⁢     Grad   /   s                             Poles                 p   1     =         450   ⁢           ⁢   μS       600   ⁢           ⁢     Ω   ·   18.3     ⁢           ⁢     mS   ·   10     ⁢           ⁢   pF       =     4.1   ⁢           ⁢     Mrad   /   s                           p   2     =         450   ⁢           ⁢     μS   ·   5.16     ⁢           ⁢   mS       18.3   ⁢           ⁢     mS   ·   10     ⁢           ⁢   pF       =     25   ⁢           ⁢     Mrad   /   s                                       p   3     =         65   ⁢           ⁢   mS       20   ⁢           ⁢   pF       =     3.35   ⁢           ⁢     Grad   /   s                           p   4     =         18.3   ⁢           ⁢   mS       2   ⁢           ⁢   pF       =     9.15   ⁢           ⁢     Grad   /   s                             Gain/bandwidth product               GBW   =       1     600   ⁢           ⁢     Ω   ·   2     ⁢           ⁢   pF       =     166   ⁢           ⁢     Mrad   /   s                                
 
         [0038]      FIG. 5  shows the Bode plot for the embodiment of a transimpedance amplifier according to the invention as described in Tables 1 and 2. As can be seen from the plot, the amplifier has a phase margin of  670 . If the null point Z 2  is compensated for by a resistor in series with the Miller capacitor, this results in a phase margin of  700 .  
         [0039]      FIG. 6  illustrates a second embodiment of a transimpedance amplifier according to the invention. In this circuit, not only is an additional resistor Rm connected in series with the Miller capacitor Cm 1 , but an additional Miller capacitor Cm 2  is also connected between the output of the transimpedance amplifier and a node which is located between the current source transistors P 1  and P 2 .  
         [0040]     The frequency compensation for the transimpedance amplifier according to the invention is similar to the frequency compensation for a two-stage Miller amplifier. The null point z 2  and the dominant pole p 2  and the non-dominant pole p 3  are equivalent to the poles and null points in the Miller amplifier. The transimpedance amplifier also has the pole p 1  and the null point z 1  in the frequency domain before the gain/bandwidth product GBW. The pole p 1  occurs before the null point z 1  by the factor R f *gm N2 . It is necessary to ensure that the frequency of the null point z 1  is four to five times less than the gain/bandwidth product GBW. This is achieved by choosing gds N2  to be four to five times less than 1/R f . The gain/bandwidth product GBW is governed by the Miller capacitor C 3  and by the feedback resistor R f . The circuit also has a second non-dominant pole p 4 , which should be higher than p 3  by the factor 2.  
         [0041]     A third embodiment of a transimpedance amplifier according to the invention is illustrated in  FIG. 7 . In this circuit, in addition to the embodiment shown in  FIG. 6 , a further capacitor Cf is also connected in parallel with the feedback resistor Rf. In the case of the embodiments shown in  FIG. 3  and  FIG. 4 , it is possible to provide in a manner such as this for a further capacitor Cf to be connected in parallel with each of the feedback resistors Rf.