Abstract:
An approach for calibrating a signal reconstruction system. A signal may be input to a low-pass filter. An output of the filter may be converted to a digital signal which goes to a processor which outputs a reconstruction of the signal to the filter. The reconstruction may be based on an expression that maintains the accuracy of the reconstruction. The expression may include information about samples of the input signal and a low value of the reconstruction. The expression may permit initial calibration and then maintenance of the calibration. The calibration may include compensating for inexpensive components of the filter which have values significantly different than indicated values and/or have large drifts over temperature changes.

Description:
[0001]    This application is a continuation-in-part of U.S. patent application Ser. No. 12/034,986, filed Feb. 21, 2008. U.S. patent application Ser. No. 12/034,986, filed Feb. 21, 2008, is hereby incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    The invention pertains to signal processing, and particularly to reconstructive signal processing. 
       SUMMARY 
       [0003]    The invention is a self-calibrating system for reconstructing high-frequency signals put through a low-pass filter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0004]      FIG. 1  is a block diagram of a signal reader system; 
           [0005]      FIG. 2  is a schematic diagram of a low-pass filter in the system; 
           [0006]      FIG. 3  is a graph of a response of the low-pass filter plus a reconstruction filter; 
           [0007]      FIG. 4  is a graph showing a closer view of a portion of the graph in  FIG. 3 ; 
           [0008]      FIG. 5  is a graph of an input and output signals of the low-pass filter; 
           [0009]      FIG. 6  is a graph of the low-pass filter output signal and a reconstructed input signal of the filter; 
           [0010]      FIG. 7  is a graph of input and output signals of the low-pass filter for a very low frequency wave followed by a higher frequency; 
           [0011]      FIG. 8  is a graph the low-pass filter output signal and a reconstructed input signal to the filter for the very low frequency wave followed by a higher frequency; 
           [0012]      FIG. 9  is a graph showing a reconstruction of a worst-case scenario of a low-pass filter input having sinusoidal noise at a certain frequency in transitions between high and low, and showing the filter output; 
           [0013]      FIG. 10  is a graph showing the low-pass filter output in the graph of  FIG. 9  decimated by a certain factor, and showing a reconstruction of the filter input along with low and high thresholds; 
           [0014]      FIG. 11  is a graph showing a reconstruction of a worst-case scenario of a low-pass filter input having white noise in transitions between high and low, and showing the filter output; 
           [0015]      FIG. 12  is a graph showing the low-pass filter output in the graph of  FIG. 11  decimated by a certain factor, and showing a reconstruction of the filter input along with low and high thresholds; 
           [0016]      FIG. 13  is a diagram of an apparatus of the present system; and 
           [0017]      FIG. 14  is a diagram of the waveforms illustrating the present system. 
       
    
    
     DESCRIPTION 
       [0018]    The present invention is a self-tuning system for reading high-frequency pulses through a low-pass filter. It may include an approach for using an analog input from which a pulse count may be obtained indirectly. The input signal to a low-pass filter of the approach cannot realistically be used for the count in absence of additional hardware to pick up the signal. Additional hardware means undesired expense. In the approach, pulse counting of the input may be achieved without adding any hardware specific to counting, like a second path for the input signal, which could be a high frequency path around the filter. In the approach, the input signal may be reconstructed after the filter. This approach appears to work even if there is a resistor-capacitor (RC) filter in the analog input hardware that severely attenuates frequencies in the range of which pulses are to be counted. The approach may essentially include reading high frequency pulses coming through a strong low-pass filter. 
         [0019]    Pulse counting hardware may be different from analog input hardware partially because the bandwidth needed for pulse counting appears to be in conflict with the low-pass filtering requirements of an analog input. 
         [0020]    At a highest level, the approach may operate by nearly exactly reconstructing the original signal being input to the RC filter. This approach may appear workable in a manner contrary to normal intuition. Further, it may be done more simply than intuition would suggest. The approach may be done without accumulating any state information except for a previous sample value. This may eliminate the possibility of long term round off, drift, or instability. It also means that the approach may work accurately at arbitrarily low frequencies. 
         [0021]    Other approaches may include specific inputs that count pulses, but are not capable of doing any analog-to-digital conversion, and do not share terminals with analog input hardware. This generally adds costs to the product because more hardware appears to be required. 
         [0022]    Still other approaches may include sharing the same input terminals between an analog input and pulse-counting input, but ultimately have the signal go through two different paths. This appears to be basically the same as having dedicated pulse-counting hardware, except that the terminals are shared with analog input hardware. Once again, these approaches may involve added costs for the pulse counting capability. 
         [0023]    The pulse counting approach may include an input block for providing biasing and filtering. The counting approach may be shown with an example which involves re-engineering a pulse counting algorithm using a low-pass RC filter on the input. 
         [0024]    It may be noted that by doing a computation on the differences between consecutive A/D readings, pulses through an RC filter could be counted. But there may be some difficulties with using a fixed threshold; however, it appears that some sort of relatively simple incremental state-maintaining algorithm might accomplish the task of counting pulses. Whatever algorithm is to be used, it should be simple, run at about 640 Hz, and do computations for up to three channels for certain product needs, but there may be more or less channels. 
         [0025]    One may consider the following example, in which a 100 Hz square wave is presented at the input immediately following the tail end of a very long square wave. If one were to set a fixed threshold at 512 Hz, the system would miss the first two pulses following the long pulse. However, this could possibly be alleviated by having a moving threshold. For instance, the threshold may simply be the output of a low-pass IIR (infinite impulse response) filter with a lower frequency than the RC filter itself (but not so low that the threshold would fail to keep up with the special case shown herein). However, if the threshold reacts fast enough for such case, one&#39;s intuition may indicate that it would not function properly over the other extreme case of a ten minute long square wave (i.e., it would tend to follow such a long square wave too closely). 
         [0026]    Ultimately, one thing that may indicate having the wrong solution is a situation where the input is a ten minute line sine wave. Then the slowly-moving-threshold approach would appear to simply follow the sine wave and not provide a useful threshold point at all. One might argue that responding to a sine wave is not needed, but one may have to admit that certain designs do respond to a sine wave. 
         [0027]    A goal is to cancel out the effects of the RC filter. If one designed a system that accomplished a cancellation of such effects, it might be unstable (which is often a concern with IIR filters) or require too much computation if done at 640 Hz. However, it may be noted that not only can such design be safely done with integer-only math; it may be implemented without any feedback (meaning that it would not get out of sync or become unstable). The only state variable in this designed system would be a previous A/D reading. 
         [0028]    The design of the system may begin with a characterization the low-pass RC filter as an IIR filter in order to get its constants. A form of a single-pole IIR filter may be: 
         [0000]        y   n   =a   0   x   n   +b   1   y   n-1 .  (1) 
         [0000]    The constants for this equation may be computed as: 
         [0000]      b 1 =e −2πf     C     /f     s    and 
         [0000]        a   0 =1 −b   1    
         [0000]    where f c  is a −3 dB point of the RC filter and f s  a sample rate of the analog-to-digital converter. The RC filter of the input block  12  may have a −3 dB point of 1/(2*π*R*C)=1/(2*π*34000*0.00000047)≈10 Hz. Thus, for a sample rate of 640 Hz, 
         [0000]      b 1 =e −2π(10/640) =0.9064905 and 
         [0000]      a 0 =0.0935095. 
         [0029]    By solving the equation (1) for x n , one may get 
         [0000]        x   n =(1 /a   0 ) y   n −( b   1   /a   0 ) y   n-1 =10.694 y   n −9.694 y-1 . 
         [0000]    It may be noted that the computation of x n  seems to just depend on two consecutive A/D readings. Since there appears to be no possibility of accumulated errors, the following equation is nearly as good. 
         [0000]        x   n =11 y   n −10 y   n-1   (2) 
         [0000]    A critical thing here is that the two constants are different from each other by virtually exactly one (in this instance, 11−10=1). Since the x n  is a reconstruction of the original waveform, ranging from 0 to 1023 (in a 10-bit A/D case); an absolute threshold (e.g., around 512) for the 10-bit A/D may be used. It may be noted that the x n  resulting from equation (2) is specific to the parameters of the filter and the sample rate. The 640 Hz sampling rate, which can be optional, may be regarded as integral to the 50/60 Hz of common power lines, and thus helpful in rejecting 50/60 Hz noise at the input side of the A/D converter. 
         [0030]    The low-pass filter may be a multiple-pole filter and a corresponding characterization may be provided and implemented in a similar manner as the characterization provided herein for the single-pole low-pass filter. 
         [0031]      FIG. 1  is a block diagram of the system  10  applicable to pulse counting. A signal or pulse source  11  may provide an output to an RC filter  12 . An output of filter may go to an input of an analog-to-digital (A/D) converter (ADC)  13 . ADC  13  may provide an output to an algorithmic processor  14 . The signal may be processed according to the algorithm described herein (i.e., equation (1)). Also, the algorithm may be adapted for compensating temperature drifts of filter  12 . 
         [0032]    Processor  14  may be used for reconstructing an input signal to filter  12 . ADC  13  and processor  14  may be regarded together as a signal reconstructor. The output of processor  14  may go to a signal thresholder  15 . The thresholder  15  may condition signals from the processor  14  into digitally-formed or pulse-like shaped signals. From thresholder  15 , the output signals may be provided to a signal reader  16  having a counter for counting pulses. For certain kinds of signals, processor  14  might be directly connected to the signal reader  16 . 
         [0033]      FIG. 2  shows the low-pass RC filter  12  having an output connected to the input of ADC  13 . An input signal may be provided by a signal or pulse source  11  to filter  12  at a common connection of resistors  21  and  22 . Resistor  21  may have a value of about 10K ohms and resistor  22  may have a value of about 100K ohms. The other ends of resistors  21  and  22  may be connected to a power source  24  and a capacitor  23 , respectfully. Capacitor  23  may have a value of about 0.47 microfarads. The indicated values of the resistors and capacitor are examples but could be other values. The output of filter  12  may be at the common connection of resistor  22  and capacitor  23  which may go to the input of the ADC  13 . A reference voltage of the various components of system  10  may be a ground  24 . 
         [0034]    The frequency response of the RC filter  12  plus the response of reconstruction filter (using 10 and 11 as constants—equation (2)) in the processor  14  is shown as curve  32  in the graph of  FIG. 3 . In the range from 0 to 100 Hz, the overall reconstructed response  32  may appear very nearly ideal, as shown in  FIG. 4 .  FIG. 4  may effectively be a zoomed-in version of the graph in  FIG. 3 , from zero to 120 Hz. Plot  31  may be a response of just the RC filter  12 . The graphs of  FIGS. 3 and 4  show plots in terms of dB (−6 dB=0.5) versus frequency. 
         [0035]    Relative to the 640 Hz sampling scenario, one concern may be that there is a high response around 920 Hz, with the overall attenuation being only about 13 dB. 920 Hz may be aliased to 280 Hz. The next such high response point may be near 1575 Hz, at about 17 dB attenuation. 1575 Hz may alias to 295 Hz. Both of these aliased frequencies appear outside the 0 to 100 Hz range. Such high-frequency noise could occur due to contact bouncing, making this a legitimate concern. 
         [0036]    The situation might be improved with a 100 Hz low pass filter after the reconstruction filter, but a single-pole low pass filter seems not strong enough (in that 100 Hz appears too close to the middle of the 640 Hz spectrum). A higher order filter could be probably too CPU intensive to implement at such a high rate. 
         [0037]    A solution may be to set hysteresis or threshold points at ¾-full-scale and ¼-full-scale, so that a full-amplitude signal with 13 dB of attenuation (i.e., about one quarter amplitude) gets rejected. 
         [0038]    Test or simulation results may be noted. An input test using random noise may be done to see if the reconstruction IIR filter is unstable in the face of noise. Such test was done before it was realized that the filter appeared not to be an IIR filter, but rather an FIR (finite impulse response) filter of a length  2 , and thus would not become unstable. A distinguishing aspect of the FIR filter may be a lack of x n-1  in equation (1).  FIG. 5  is a graph of the test on a basis of 10-bit counts versus sample number. Line  35  is a plot of the raw input to an RC filter  12  and line  36  represents an output of the RC filter (an A/D  13  input).  FIG. 6  is a graph which shows a reconstructed filter input in terms of 10-bit counts versus sample number. A line  37 , representing a reconstruction of the original input, may be generated directly from an RC filter  12  output (an A/D or ADC  13  input) signal represented by line  36  in the graph. 
         [0039]      FIG. 7  is a graph where a very low frequency wave is followed by 100 Hz. Line  38  represents a raw input and line  39  represents an RC filter  12  output (an A/D input).  FIG. 8  is a graph that shows a reconstruction of the raw input in  FIG. 7 . Line  41  in  FIG. 8  represents the reconstruction of the original waveform and line  39  represents the RC filter output (A/D input). One may note that the reconstructed signal  41  appears attenuated a little bit, which is probably due to a rounding off of the filter constants. 
         [0040]    Noise rejection may be noted. The graph of  FIG. 9  shows an attempt to reconstruct the worst-case scenario of having virtually an exact 930 Hz of sinusoidal noise in the transitions from high to low. This simulation may be done at 10.240 KHz so that the effects of the RC filter  12  can be replicated appropriately. The graph of  FIG. 9  shows 10-bit counts versus sample number with sample frequency at 10.240 KHz. The noise may be simulated at 10.240 KHz. The raw data input is represented by line  43  and the RC filter  12  output is represented by line  44  in the graph of  FIG. 9 . The RC output in the graph of  FIG. 9  may be decimated by a factor of 16, leading to line  45  representing the RC output (A/D input) in the graph of  FIG. 10 . The graph of  FIG. 10  shows 10-bit counts versus sample number with a sample frequency of 640 Hz. The decimation factor x16 may simulate the 640 Hz sampling with its aliasing implications. In this case, the 930 Hz sine wave may be aliased down to 290 Hz. One may note how the line  45  (RC output) in the graph of  FIG. 10  hardly shows the input noise, yet the reconstruction filter (i.e., algorithmic processing of processor  14 ) produces a reconstruction, as indicated by line  46 , of the original wave having a 290 Hz signal near samples  8  to  10 , and also near samples  28  to  31 . This appears to be because of the “hump” in the frequency response near 930 Hz. As expected, however, this signal may be attenuated enough so that it does not go outside the ¼ and ¾ thresholds, as shown by lines  47  and  48 , respectively. Thus, this signal or noise may be rejected by a threshold/hysteresis algorithm of thresholder  15 . 
         [0041]    Another realistic simulation may be provided in a graph of  FIG. 11 . The graph of  FIG. 11  shows 10-bit counts versus sample number with a sampling frequency at 10.240 KHz. The noise may be simulated at 10.240 KHz. Line  51  represents the raw input and line  52  represents the output of RC filter  12 . White noise may appear in the transitions. This graph appears to show performance better than the 930 Hz case because the white noise has a more spread out spectrum. The input may be reconstructed in a graph of  FIG. 12 . The graph of  FIG. 12  shows 10-bit counts versus sample number with a sampling frequency at 640 Hz. Line  53  represents the RC filter  12  output (ADC  13  input) and line  54  represents a reconstruction of the original waveform of the filter  12  input. Lines  55  and  56  represent upper and lower thresholds, respectively. There may, under certain circumstances and design, instead be just one threshold. 
         [0042]    With regards to the signal reading system  10  noted in  FIG. 1 , another approach indicated herein is a way to use the system for even higher frequency signals, under certain conditions. The approach may account for circuit component tolerances and temperature drift. The apparatus of  FIGS. 1 and 2  may be applicable; but with some hardware and software algorithmic changes, it may result in a system  20 . The approach of present system  20  may be applicable to the signal reconstruction algorithm noted herein. 
         [0043]    System  20  may be used relative to digital serial communications, particularly to Alerton™ Microset™ communications. With such communications, some features of a waveform input to the present system may have higher frequencies than the underlying sample rate, thus resulting in a need for filter components having values with little variation from the indicated values, and having insignificant changes due to environmental conditions. 
         [0044]    With system  20 , a high frequency waveform may be reconstructed from a low-pass RC filter output sufficient enough for Microset™ communications. Because cost is a factor, a desired high performance approach using inexpensive components may require compensation since such components may have values with large variation from the indicated values, and/or significant changes due to environmental conditions such as temperature drift. 
         [0045]    The signal reconstruction may be based on the following formula. 
         [0000]        x   n =(1 /a   0 ) y   n −( b   1   /a   0 ) y   n-1 , 
         [0000]    where 
         [0046]    b 1 =e (−2πf     C     /f     s     ) =e (−1/RCf     s     ) , 
         [0047]    f c =−3 dB point of RC filter=1/(2πRC), 
         [0048]    f s =sample frequency, and 
         [0049]    a 0 =1−b 1 . 
         [0050]    The constants a 0  and b 1  may be dependent on the values of R and C, i.e., the resistance and capacitance of the RC filter components. As to an inexpensive capacitor, the tolerance of the capacitor&#39;s nominal value might not be very stringent in that it may vary plus or minus 20 percent of its indicated value. The nominal value may also drift an extra 5 percent or so, one way or the other, with temperature change. System  20  may indicate how correct values of constants b 1  and a 0  (based on exact values of R and C) may be directly determined by monitoring a known signal. 
         [0051]      FIG. 13  is a diagram of system  20  using the present approach. A microset  81  may have a two-way connection on line  72  to a circuit  71 . For a period of time sufficient for calibration, a “1” signal may be output to circuit  71  from a TX/power control  73 . Communications may in general proceed with TX/power control  73  along with a signal or signals for calibration. 
         [0052]    Control  73  may output a signal to a base of a PNP transistor  74  to cause the raw line data  61  ( FIG. 14 ) to go to zero for about 2 milliseconds. Transistor  74  may have an emitter connected to a terminal  78 , having a positive voltage such as 5 volts, and have a collector connected to line  72  and to one end of a resistor  75 . The other end of resistor  75  may be connected to a ground  24 . Resistor  75  may be about 4.7K ohms or another effective value. Line  72  may be connected to an input of RC filter  12 . The output of filter  12  may go to an input of A/D converter  13 . The output of the A/D converter  13  may go to a processor  76  with a signal reconstruction algorithm. Processor  76  may be regarded to as an algorithmic processor. An output  77  from processor  76  may provide a reconstruction signal  79 . 
         [0053]    Signal  79  may or may not go to the thresholder  15  of  FIG. 1 . Thresholder  15  may have one threshold level  69  ( FIG. 14 ) with no hysteresis, rather than more than one threshold level as otherwise may be indicated herein. If the thresholder is used, then an output of thresholder  15  may go the signal reader  16  of  FIG. 1 . 
         [0054]    The calibration algorithm may be noted in the following. Calibration may involve a known waveform  62  made from a “raw line data” or waveform  61 , as shown in a diagram of amplitude versus time of  FIG. 14 . Waveform  62  may be an output from the low-pass RC filter  12  having waveform  61  as an input to filter  12 . There may be two A/D samples  63  and  64  of waveform  62 . Diamonds  65  and squares  66  and  67  are the points of the reconstruction signal  79  from output  77  of processor  76 . A square  66  is a low point of the reconstructed signal  79  and should be zero when the value of b 1  is appropriate. The host may contrive to put the second sample  64  at the end of the low-going pulse  68 . Squares  66  and  67  may be regarded as a reconstruction output x n  which should be at zero. The diagram also shows a threshold level  69 . 
         [0055]    In the case of the microset communications, there may be a scenario where a host sends a “1” to the microset  81 . After sending a “1”, the host may drop the TX/power for 2 milliseconds, thus causing the raw line data  61  to go from a logic “one” to zero volts for about 2 milliseconds, which should be long enough to include two 640 Hz samples, the samples being about 0.001563 second apart. At 0.001563 second and 0.003125 second, the two samples  63  and  64  would occur when the raw line data  61  is at zero volts. Samples  63  and  64  may be designated as y n-1  and y n , respectively. Since it is evident that the raw line data  61  makes no immediate excursion away from 0 volts between samples  63  and  64  (i.e., which effectively indicates a perfect 0 volt DC with no higher frequency components) and that the samples correspond to a zero original waveform, then it would be expected that the reconstruction output x n  be equal to zero. Thus, the following may be computed. 
         [0000]        x   n =(1 /a   0 ) y   n −( b   1   /a   0 ) y   n-1 , 
         [0000]    and since x n =0 may be given, then 
         [0000]        b   1   =y   n   /y   n-1 . 
         [0000]    The computation may virtually give an exact value of b 1  corresponding to the component values of R and C at the time the samples y n-1  and y n  are taken. Furthermore, it may be possible to reduce the number of division operations, thus reducing CPU time in some architectures. To achieve this, the formula herein for b 1  is done only once at the first time a “1” is sent to circuit  71 , which generally occurs at a start or power-up of system  20 . From that point on, such as square  67  and other low points of the reconstruction  79  beyond square  66 , which may be regarded as x n , the value b 1  may incrementally be maintained to account for temperature drift and/or other factors. The algorithm for incrementally maintaining b 1  (and thus also a 0 ) is indicated in the following. Every time a host sends a “1”, the data may be sampled as indicated herein, and the system may compute 
         [0000]        x   n =(1 /a   0 ) y   n −( b   1   /a   0 ) y   n-1 , 
         [0000]    using the current values of b 1  and a 0 . 
         [0056]    If x n &gt;0, then b 1  is too small; so then it should be increased by a small amount. On the other hand, if x n &lt;0, then b 1 , is too large, so then it should be reduced by a small amount. In practice, increasing or decreasing the value “by a small amount” may be interpreted as increasing or decreasing it by 1 percent or so. It may be noted that both the direct and incremental approaches, whenever b 1  is changed, a 0  is implicitly changed since a 0 =1−b 1 . A goal of the calibration approach is to ensure that the reconstruction  79  of system  20  is effectively accurate. The calibration and/or maintenance of the calibration may occur automatically in system  20 . 
         [0057]    To recap, the present approach for calibration of the reconstruction system  20  may include inputting a first signal to a low-pass filter, taking at least two samples of an output from the low-pass filter  12 , inputting the output of the low-pass filter to analog to digital converter  13 , and inputting an output of the analog to digital converter to processor  76 . The processor may output a reconstruction of the first signal  61 , which is calibrated according to an expression. 
         [0058]    The first signal  61  may have a logic one and zero, in that order. The logic zero  68  may be during a first period of time and the at least two samples  63 ,  64  may be taken during the first period of time. 
         [0059]    The expression may include x n =(1/a 0 )y n −(b 1 /a 0 )y n-1 , where y n-1 =a magnitude of one sample of the at least two samples, y n =a magnitude of another and subsequent sample of the at least two samples, y n-1 ≧y n , and x n =a low value of a reconstruction of the first signal, during the first period of time. The low-pass filter  12  may include a resistance and a capacitance where R=ohms of the resistance and C=microfarads of the capacitance. Also, f s =frequency of the samples, b 1 =e (−1/RCf     s     ) , and a 0 =1−b 1 . 
         [0060]    It may be noted that if the raw data line  61  makes no excursion away from the logic zero between the at least two samples  63 ,  64 , then the x n  should be about zero. Thus, b 1 =y n /y n-1 , if x n  is zero. 
         [0061]    A second signal, which may be like the first signal, may be input to the low-pass filter  12  and x n  may be measured. If x n  is greater than zero, then b 1  may be increased by a small amount. If x n  is less than zero, then b 1  may be decreased by a small amount. The term b 1  may be increased or decreased until x n  equals approximately zero. A “small amount” means about one percent of a given amount being changed. 
         [0062]    The expression x n =(1/a 0 )y n −(b 1 /a 0 )y n-1 , may be implemented once at the first time that a logic one of the first signal is inputted to the low-pass filter  12 . At subsequent times that a logic one is inputted to the low-pass filter, then b 1  may be incremented one way or the other to maintain x n  equal to about zero. The processor  76  may output a sufficiently accurate reconstruction  79  by automatically adjusting b 1  to maintain x n  at about 0. The first time that the logic one is input to the low pass filter may generally occur during a start or power-up of system  20  which may include the low-pass filter  12 , analog-to-digital converter  13  and processor  76 . 
         [0063]    In the present specification, some of the matter may be of a hypothetical or prophetic nature although stated in another manner or tense. 
         [0064]    Although the invention has been described with respect to at least one illustrative example, many variations and modifications will become apparent to those skilled in the art upon reading the present specification. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.