Abstract:
Method and system for application specific integrated circuit (ASIC) simulation, wherein the ASIC includes plural logical elements is provided. The method includes, monitoring transitions at an output of a logic element of the ASIC; checking if the transition is to an unknown value (X); verifying if the unknown value is based on a design error; forcing the output of the logic element to a known value if the unknown is an unwanted condition; propagating the known value to logic elements in the ASIC; and releasing the known value after a next command.

Description:
BACKGROUND 
   1. Field of the Invention 
   This invention relates in general to the field of application specific integrated circuits (“ASICs”), and more specifically, to simulation and debugging techniques used to filter unknown values. 
   2. Background of the Invention 
   Application Specific Integrated Circuits (“ASICs”) are commonly used in various computing functions. Typically, while an ASIC is being designed and before a foundry fabricates it, the ASIC is verified and tested in a simulation environment. After fabrication, the ASIC is tested to perform in real life situations using lab equipment. 
   ASICs are first designed in a hardware description language (“HDL”) and then synthesized to logical components, like registers flip-flops, AND gates, and OR gates. 
   Flip-flops are logical sequential elements that store logical digital values, for example, 1 and 0. Inputs to a conventional flip-flop are clock, data and a write enable signals. The clock signal oscillates at a regular interval; data is sampled at the transition of the clock signal and at the assertion of write enable signal. The output of a typical flip-flop is either 1 or 0. 
   Simulations are typically run using simulators to verify the functionality of an ASIC design. Simulation includes monitoring, forcing, checking and releasing actions using simulator language constructs. 
   The simulator has the ability to create a logical X (unknown logic level) when inputs to a component (for example, a flip-flop) violate set-up or hold time requirements for the component. These set-up and hold times are often specified to the simulator. 
   When a simulation fails, different debugging techniques are used to debug the failure mechanisms. One technique is to propagate the X value from a logic element (for example, a flip-flop) to the rest of the ASIC logic elements. This technique works well if the generated X value is based on a true error. However, not all X values are based on true errors. For example, X values originate from a register that is constructed from bits in different clock domains. If the register is not synchronized to both clock domains, then the simulator due to timing violations originates an X value. Such X values are not design related and are propagated to the rest of the design, resulting in an early termination of the simulation process. This is undesirable because it impedes the overall simulation process. 
   Therefore, what is needed is a method and system to filter localized unwanted X&#39;s from the rest of the design, while preserving the global checks that the simulator performs to create X&#39;s for legitimate timing violations that should be propagated through the design. 
   SUMMARY OF THE INVENTION 
   A method for ASIC simulation is provided. The method includes, monitoring transitions at an output of a logic element of the ASIC; checking if the transition is to an unknown value (X); verifying if the unknown value is an unwanted condition; forcing the output of the logic element to a known value if the transition is an unwanted condition; propagating the known value to logic elements in the ASIC; and releasing the known value after a next command. 
   In another aspect, an ASIC simulation system is provided. The simulation system includes a computing system with a processor coupled to an application specific integrated circuit (“ASIC”) simulator, wherein the computing system includes a processor for executing code for monitoring transitions at an output of a logic element of the ASIC; checking if the transition is to an unknown value (X); verifying if the unknown value is an unwanted condition; forcing the output of the logic element to a known value if the transition is an unwanted condition; propagating the known value to logic elements in the ASIC; and releasing the known value after a next command. 
   This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
       FIG. 1A  shows a block diagram of a simulation environment for an ASIC; 
       FIG. 1B  shows a block diagram of a computing system used for performing the simulation; 
       FIG. 1C  is an example showing the undesirable propagation of unknown values (X&#39;s); 
       FIG. 2  shows a flow diagram for debugging ASIC simulations by selectively propagating X&#39;s, according to one aspect of the present invention; and 
       FIG. 3  illustrates filtering localized X&#39;s, according to one aspect of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In one aspect of the present invention, a logic element&#39;s (for example, a flip-flop) out-put is monitored to see if it has been set to an unknown value (X). The process verifies if the X value is based on a true design error and if it is not based on a true design error, then the X value is forced to a known value (for example, 1 or 0). The process continues to monitor future writes to the logic element and when a new write enable signal is received, the forced value is disabled. 
   To facilitate an understanding of the preferred embodiment, the general architecture and operation of a simulation system will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture. 
   Simulation Environment 
     FIG. 1A  shows a top-level block diagram of a system  60  for testing ASICs, according to one aspect of the present invention. 
   System  60  includes the ASIC simulator  40 , which can be a standard hardware description language simulator. Simulator  40  interfaces with a host bus interface functional module (also referred to as “HIBFM”)  50 . HIBFM  50  can be configured to receive any stimulus from computing system  10 . 
   Host system/computing system  10  uses a host computer emulation (“HCE”) program (or module)  20  that interfaces with a driver  30  that interfaces with HIBFM  50 . There are standard emulation programs, for example, VMware available from VMWare Corp. and VirtualPC available from Microsoft® Corporation, used to emulate real hardware to software. Software executing in the HCE  20  environment believes that it is interfacing with hardware components, while in fact it is interfacing with software that behaves like hardware. HCE  20  interfaces with HIBFM  201  via driver  30 , using for example, a TCP/IP link  50 A. 
   Before describing the adaptive aspect of the present invention, the following describes the overall architecture of computing system  10 , with respect to  FIG. 1B . As shown in  FIG. 1B , system  10  includes a central processing unit “CPU”  10 A for executing computer-executable process steps and interfaces with a computer bus  10 H. Also shown in  FIG. 1B  are a network interface  10 B, a display device interface  10 C, interface for various other devices (for example, a mouse, keyboard and others)  10 F and storage media (for example, hard drive, CD-ROM, CD-R/W, flash memory, tape drive and others)  10 G. 
   Storage media  10 G stores operating system program files, application program files, and other files. Some of these files are stored on using an installation program. For example, CPU  10 A executes computer-executable process steps of an installation program so that CPU  10 A can properly execute the application program. 
   A random access main memory (“RAM”)  10 E also interfaces to computer bus  10 H to provide CPU  10 A with access to memory storage. When executing stored computer-executable process steps from storage media  10 G, CPU  10 A stores and executes the process steps out of RAM  10 E. 
   Read only memory (“ROM”)  10 D is provided to store invariant instruction sequences such as start-up instruction sequences or basic input/output operating system (BIOS) sequences. 
   Network Interface  10 B allows computing system  10  to connect (for example, using TCP/IP link  50 A,  FIG. 1A ) with other systems via a network. 
   It is noteworthy that the foregoing systems are merely to illustrate the adaptive aspects of the resent invention. The architecture and block diagrams may have fewer or more components to execute the process steps described below. 
   Undesirable X&#39;s Propagation 
   Before describing the adaptive aspects of the present invention, the undesirable propagation of X&#39;s is described with respect to  FIG. 1C . 
   After simulation is started, logic values are propagated throughout the ASIC design. Flip-flop  102  samples input data  101  at the transition of the input clock  104  and at the assertion of the input write enable  103 . 
   If the output  105  of the flip-flop transitions to an X, it gets propagated to the inputs of all the logical components that the output is connected. In the example shown in  FIG. 1C , the output of the flip-flop is connected to one of the inputs of logical component  106 . The other input to this logical component is a logical 1. Since one of the inputs to this logical block is an unknown value X, the output  107  is also an unknown value X. This propagation continues to the rest of the outputs (i.e.  109  and  111 ) of the logical components  108  and  110  respectively. This abruptly ends the simulation process. If the X is based on an unwanted condition and not an ASIC design error, then the simulation disruption is not necessary. 
   Process Flow Diagram 
     FIG. 2  shows a flow diagram for debugging ASIC simulations by selectively propagating X&#39;s, according to one aspect of the present invention. 
   The process begins in step S 201 , when the simulation for the ASIC is started using a simulator tool (for example, as shown in  FIG. 1A  and mentioned above). In step S 202 , state transitions are monitored at the output of a logical element (for example, a flip-flop  102 ). The process monitors the initial non-X values at a flip-flop, the most recent non-X value and the X values. 
   If the transition of an output is to an X, then in step S 203 , the source of the X value is checked/validated. This is to ascertain if the X value is based on a design error or if the X value creates an unwanted condition. If the source of the X is determined to be a real condition (for example, based on a design error), then the X value is propagated to the rest of the design (i.e. other elements of the ASIC) in step S 204 . Simulation ends in step S 210  when a fault is encountered (or generated due to the propagation of X&#39;s) in step S 209 . 
   If X is determined to be an unwanted condition (based on the source verification in step S 203 ) then in step S 205 , the output of the logic element is forced to a known logic value, for example, 0 or 1. It is noteworthy that the forced value is based on the last non-X value that was written to a flip-flop (or any other logic) that is tracked in step S 202 . According to the present invention, this action suppresses the propagation of the unwanted X values to the rest of the design. 
   In Step S 206 , the output of the logic element is released from the forced condition after a write enable signal (for example,  103 ) is de-asserted at the input of the logic element. 
   In step S 207 , the known logic value is propagated to the rest of the design and simulation progresses to step S 208  without terminating. Thereafter, simulation ends in step S 210 . 
   It is noteworthy that multiple logic segments (for example, multiple flip-flops) can exhibit unwanted conditions based on the X values. Hence, each piece of logic is handled separately, i.e., initial non-X value (during logic initialization) and the last non-X value before the X value is received are tracked. The X value conditions are validated as described above and for unwanted conditions an output value is forced (instead of propagating the X value throughout the design). 
     FIG. 3  illustrates filtering of localized X&#39;s using the foregoing method of the present invention. The logic element used to illustrate the adaptive aspects of the present invention is a flip-flop (similar to  FIG. 1C ). Flip-Flop  102  samples input data and the transitions at the output are monitored (as shown in step S 202 ). If the transition is to an unknown value X, and the source of the X is found to be an unwanted condition, then the output  105  is forced to a known logic value, in this example, to logic high or 1. This known logical value (1) then propagates to outputs  107 ,  109 ,  111  of the rest of the logical components  108 ,  110 . This allows the simulation to continue without unnecessary disruption. 
   According to one aspect of the present invention, forcing the output of the flip-flop suppresses the propagation of unknown value. Hence, simulation runs efficiently to the desired end point without being terminated abruptly. 
   Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.