Abstract:
A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention generally relates to a method for fabricating a semiconductor device and more particularly to a method of bevel trimming a three dimensional (3D) semiconductor device. 
     2. Description of the Related Art 
     Since the invention of integrated circuit, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For most part, this improvement in integration density has come from repeated reductions in minimum feature sizes, which allows more components to be integrated into a given area. 
     These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in two dimensional (2D) integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. 
     An additional limit comes from the significant increase in the number and the length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increases. Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical formation of a 3D IC, wafer thinning is an important process.  FIG. 1A-FIG .  1 B show one issue generated from the wafer thinning process when fabricating a three dimensional semiconductor device. Referring to  FIG. 1A , a wafer  102  which has curve-shaped edges is provided. A device structure  104  comprising stack layers (not shown) is formed on the wafer  102  for forming integrated circuits. Next, referring to  FIG. 1B , the wafer  102  is thinned by grinding. Due to the curve-shaped edges, the wafer  102  has a sharp edge  106  after thinning. The wafer with a sharp edge is likely to crack along defects. Further, it is dangerous to carry the wafer  102  with the sharp edge. 
     BRIEF SUMMARY OF INVENTION 
     A method of bevel trimming a 3D semiconductor device is disclosed, comprising, providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias. 
     A method of bevel trimming a 3D semiconductor device is disclosed, comprising, providing a wafer with stack layers thereon and through substrate vias (TSV) therein to constitute a 3D semiconductor device, wherein an edge of the wafer is curved, performing a bevel trimming step to the curved edge of the wafer for obtaining a planar edge, and thinning the substrate to expose the through substrate vias, wherein the planar edge of the substrate is perpendicular to a surface of the substrate. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein, 
         FIGS. 1A-1B  show one issue generated when thinning a wafer when fabricating a three dimensional semiconductor device. 
         FIGS. 2A-2C  show a method of avoiding a sharp edge of a wafer during thinning known by the inventor. 
         FIGS. 3A-3D  show a method of bevel trimming a 3D semiconductor device for eliminating the issue of sharp edges of a wafer of an embodiment of the invention. 
         FIGS. 4A-4C  show enlarged views to more clearly illustrate formation of stack layers of a device structure. 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     It is understood that specific embodiments are provided as examples to teach the broader inventive concept, and one of ordinary skill in the art can easily apply the teaching of the present disclosure to other methods or apparatus. The following discussion is only used to illustrate the invention, not limit the invention. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration. 
     A method of avoiding forming a sharp edge during thinning of a wafer known by the inventor is illustrated in accordance with  FIG. 2A-FIG .  2 C. First, referring to FIG.  2 A, a wafer  202  which has a curved edge is provided. A device structure  204  comprising stack layers is formed on the wafer  202  for forming integrated circuits. Referring to  FIG. 2B , the wafer  202  is cut at an edge to form an L shaped opening  206 . Thereafter, the wafer  202  is thinned by grinding and due to the L shaped opening  206  at the edge, the thinned wafer  202  can have a planar edge  208  to eliminate the issues from sharp edges, as shown in  FIG. 3C . However, cutting the wafer  202  at edges may generate defects and particles in the wafer  202  and another issue may be generated due to the defects and particles. 
     A method of bevel trimming a three dimensional (3D) semiconductor device for eliminating the issue of a sharp edge of a wafer of an embodiment of the invention is illustrated in accordance with  FIG. 3A-FIG .  3 D. First, referring to  FIG. 3A , a substrate  302  which has an edge  308 , a front surface  306  and a back surface  304  is provided. In an embodiment of the invention, the substrate  302  is a wafer and the edge  308  of the wafer  302  is curve shaped. The substrate  302  comprises semiconductor wafers such as silicon, gallium arsenide, a rock crystal wafer, sapphire, glass, and the like. In a preferred embodiment of the invention, the substrate  302  is formed of silicon. Referring to  FIG. 3B , through substrate vias  312  (TSV) are formed in the substrate  302  and a device structure  310  comprising stack layers are formed on the substrate  302 . Formations of the device structure  310  comprising stack layers and the through substrate vias  312  are more clearly illustrated in accordance with  FIG. 4A-FIG .  4 C. Referring to  FIG. 4A , holes  401  (only one hole is shown for simplicity) are formed in the substrate  302 . In an embodiment of the invention, the method for forming the holes  401  comprises performing a lithography process and an etching process in sequence. Subsequently, referring to  FIG. 4B , a conductive layer  405  is formed on the substrate  402  and fills the holes  401 . The material of the conductive layer  405  may be cupper, tungsten, titanium or other high conductivity materials. The method for forming the conductive layer can be plasma vapor deposition (PVD) or chemical vapor deposition (CVD). Next, referring to  FIG. 4C , the conductive layer  405  outside of the holes  401  is removed, so that the conductive layer  405  is left in the holes  401  for forming through substrate vias  304 . 
     Next, semiconductor processes are performed on the substrate  402  at the front side  404  to form stack layers of the device structure  310 . For example, a semiconductor device  414 , a dielectric layer  416 , an interconnect  419 , a pad  422  and a passivation layer  424  are formed on the substrate  402  at the front side  404 . The semiconductor device  414  may be an MOS transistor. More specifically, the semiconductor device  414  may include a gate dielectric layer  410  and a gate electrode  412  sequentially formed on the substrate  402 , and may include source/drain regions  408  deployed in the substrate  402  at both sides of the gate electrode  412 . The interconnect  419  includes conductive lines  420  and plugs  418  deployed in different layers, respectively. The materials of the semiconductor device  414 , the dielectric layer, the interconnect  419 , the pad  422  and the passivation layer  424 , and the respective forming methods thereof are known by one of ordinary skill in the art, and thus, the details thereof are not described herein. It is noted that through substrate vias (TSV) can electrically connect to the semiconductor device  414  by the conductive lines  420  and the plugs  418  of the interconnect  419 , and the pad  422  can connect outside. 
     Referring back to  FIG. 3C , a bevel trimming process is performed to the edges  308  of the substrate  302 . In an embodiment of the invention, the bevel trimming process is a vertical grinding process (bevel polishing), so that the edge  308  of the substrate  302  is modified from a curved shape to a planar shape and the planar edge  308  is preferably perpendicular to the front surface  306  and the back surface  304  of the substrate  302 , as shown in  FIG. 3C . It is noted that a time control of the bevel trimming process is required to prevent the bevel trimming process from affecting the device structure  310 . 
     Referring to  FIG. 3D , the substrate  302  is thinned by, for example grinding, at the back surface  304  till exposing the through substrate vias  312  (TSV). Since the edges  308  of the substrate  302  are treated to have a planar surface in the step of  FIG. 3C , the substrate  302  can have a planar edge after thinning and the issue of the sharp edge of the substrate  302  can be eliminated. Thereafter, the substrate  302  can further be treated with a post cleaning process for insuring that the substrate  302  treated with the bevel trimming process is clean. 
     The substrate treated with the bevel trimming process before wafer thinning has advantages as follows. First, a sharp shape at edges after thinning is prevented, so that. A cracking issue due to sharp edges of the thinned wafer can be eliminated. Second, a substrate treated with the bevel trimming process is more flexible than cutting edges of the wafer which forms L shaped openings. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. It is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.