Abstract:
In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of pending U.S. application Ser. No. 14/173,976, filed on Feb. 6, 2014, which is a divisional of pending U.S. application Ser. No. 13/721,983, filed on Dec. 20, 2012, which claims the benefit of U.S. Provisional Application No. 61/677,835, filed on Jul. 31, 2012, the entireties of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor package and a method for fabricating a base for a semiconductor package, and in particular, to a base for a high density semiconductor package. 
         [0004]    2. Description of the Related Art 
         [0005]    In order to ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are desired to be small in size, to support multi-pin connection, to support high speeds, and to support high functionality. The demand for increasing Input-Output (I/O) pin counts and high-performance ICs has led to the development of flip chip packages. 
         [0006]    Flip-chip technology uses bumps on a chip to interconnect to a package substrate. The flip-chip is bonded face down to the package substrate through the shortest path. The technology used can be applied not only to a single-chip package, but also to higher or integrated levels of packaging in which the packages are larger and packaged with more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, can achieve a high density interconnection with devices and a very low inductance interconnection with packaging. However, this requires printed circuit board (PCB) fabricators to minimize line widths and space or to develop direct chip attach (DCA) semiconductors. Accordingly, the increased amount of input/output connections of a multi-functional flip-chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference for RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products. 
         [0007]    Thus, a novel high-density flip chip package and a printed circuit board for a high-density flip chip package are desirable. 
       BRIEF SUMMARY OF INVENTION 
       [0008]    A semiconductor package and a method for fabricating a base for a semiconductor package are provided. An exemplary embodiment of a semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. 
         [0009]    Another exemplary embodiment of a semiconductor package includes a conductive trace, having a bottom surface and at least a portion of a sidewall connected to a base. A semiconductor device is mounted on the conductive trace via a conductive structure. 
         [0010]    An exemplary embodiment of a method for fabricating a base for a semiconductor package includes providing a carrier with conductive seed layers on a top surface and a bottom surface of the carrier. First conductive traces are respectively formed on the top surface and the bottom surface of the carrier, connecting to the conductive seed layers. A first base material layer and a second base material layer are respectively laminated on the top surface and the bottom surface of the carrier, covering the first conductive traces. Second conductive traces are respectively formed on first surfaces of the first base material layer and the second base material layer, wherein the first surfaces of the first base material layer and the second base material layer are respectively away from the top surface and the bottom surface of the carrier. The first base material layer with the first and second conductive traces thereon and the second base material layer with the first and second conductive traces thereon are separated from the carrier to form a first base and a second base. 
         [0011]    Another exemplary embodiment of a method for fabricating a semiconductor package includes providing a base, forming a conductive trace on the base, further forming an additional insulation material on the base, and further defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace. 
         [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0013]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0014]      FIGS. 1 to 4  show cross sections of various exemplary embodiments of a semiconductor package of the invention. 
           [0015]      FIGS. 5   a  to  5   e  are cross sections showing one exemplary embodiment of a method for fabricating a base for a semiconductor package of the invention. 
           [0016]      FIGS. 6   a  to  6   e  are cross sections showing another exemplary embodiment of a method for fabricating a semiconductor package of the invention. 
       
    
    
     DETAILED DESCRIPTION OF INVENTION 
       [0017]    The following description is a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts. 
         [0018]    The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice of the invention. 
         [0019]      FIGS. 1 to 4  show cross sections of various exemplary embodiments of a semiconductor package of the invention. In this embodiment, the semiconductor package can be a flip chip package using conductive structures, for example, copper pillar bumps, connecting a semiconductor device to a base. . Alternatively, the semiconductor package can be a package using wire bonding technology to connect a semiconductor device to a base.  FIG. 1  shows a partial cross section of one exemplary embodiment of a semiconductor package  500   a  of the invention. Please refer to  FIG. 1 , wherein the semiconductor package  500   a  comprises a base  200  having a device attach surface  214 . In one embodiment, the base  200 , for example, a print circuit board (PCB), may be formed of polypropylene (PP). It should be also noted that the base  200  can be a single layer or a multilayer structure. A plurality of conductive traces  202   a  is embedded in the base  200 . In one embodiment, the conductive traces  202   a  may comprise signal trace segments or ground trace segments, which are used for input/output (I/O) connections of a semiconductor device  300  mounted directly onto the base  200 . Therefore, each of the conductive traces  202   a  has a portion serving as a pad region of the base  200 . In this embodiment, the conductive traces  202   a  are designed to have a width which is larger than 5 μm. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than 5 μm if required. 
         [0020]    A semiconductor device  300  is mounted on the device attach surface  214  of the base  200  with an active surface of the semiconductor device  300  facing the base  200  by a bonding process. In one embodiment, the semiconductor device  300  may comprise a die, a passive component, a package or a wafer level package. In this embodiment, the semiconductor device  300  is a flip chip package. A circuitry of the semiconductor device  300  is disposed on the active surface, and metal pads  304  are disposed on a top of the circuitry. The circuitry of the semiconductor device  300  is interconnected to the circuitry of the base  200  via a plurality of conductive structures  222  disposed on the active surface of the semiconductor device  300 . However, it should be noted that the conductive structures  222  shown in  FIG. 1  is only an example and is not a limitation to the present invention. 
         [0021]    As shown in  FIG. 1 , the semiconductor device  300  may include a body  301 , metal pads  304  overlying the semiconductor body  301 , and an insulation layer  302  covering the metal pads  304 . In this embodiment, the semiconductor body  301  may include but is not limited to a semiconductor substrate, circuit elements fabricated on the main surface of the semiconductor substrate, inter-layer dielectric (ILD) layers and an interconnection structure. In one embodiment, the interconnection structure may comprise a plurality of metal layers, a plurality of dielectric layers alternatively laminated with the metal layers and a plurality of vias formed through the dielectric layers on the semiconductor substrate. The metal pads  304  comprise the topmost metal layer of the metal layers of the interconnection structure. In one embodiment, the insulation layer  302  may be a single layer structure or a multilayer structure, and the insulation layer  302  may comprise but is not limited to silicon nitride, silicon oxide, silicon oxynitride, polyimide or any combination thereof. Also, the the insulation layer  302  may have functions of stress buffering and insulation. In one embodiment, the metal pad  304  may comprise but is not limited to aluminum, copper or alloys thereof. A plurality of openings can be formed in the insulation layer  302 . Each of the openings exposes at least a portion of one of the metal pads  304 . 
         [0022]    As shown in  FIG. 1 , the conductive structure  222  may comprise a conductive bump structure such as a copper bump or a solder bump structure, a conductive wire structure, or a conductive paste structure. In this embodiment, the conductive structure  222  may be a copper bump structure composed of a metal stack comprising a UBM (under bump metallurgy) layer  306 , a copper layer  216  such as a plated copper layer, a conductive buffer layer  218 , and a solder cap  220 . In one embodiment, the UBM layer  306  can be formed on the exposed metal pads  304  within the openings by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process. The anisotropic etching process is performed after forming conductive pillars. The UBM layer  306  may also extend onto a top surface of the insulation layer  302 . In this embodiment, the UBM layer  306  may comprise titanium, copper or a combination thereof. A copper layer  216  such as an electroplated copper layer can be formed on the UBM layer  306 . The opening can be filled with the copper layer  216  and the UBM layer  306 , and the copper layer  216  and the UBM layer  306  within the opening may form an integral plug of the conductive structure  222 . A formation position of the copper layer  216  is defined by a dry film photoresist or liquid photoresist patterns (not shown). 
         [0023]    A solder cap  220  can be formed on the copper layer  216  by electroplating a solder with a patterned photoresist layer or by a screen printing process and a subsequent solder re-flow process. A conductive buffer layer  218  formed of Ni may be formed between the copper layer  216  and the solder cap  220  by an electroplating method. The conductive buffer layer  218  may serve as a seed layer, adhesion layer and barrier layer for the solder cap  220  formed thereon. In this embodiment, the conductive structure  222 , such as a conductive pillar structure, is used as a solder joint for the metal pad  304 , which transmits input/output (I/O), ground or power signals of the semiconductor device  300  formed thereon. Therefore, the copper layer  216  of the conductive structure  222  may help to increase the mechanical strength of the bump structure. In one embodiment, an underfill material or the underfill  230  can be introduced into the gap between the semiconductor device  300  and the base  200 . In one embodiment, the underfill  230  may comprises a capillary underfill (CUF), molded underfill (MUF) or a combination thereof. 
         [0024]    In one embodiment, the conductive traces may have a top surface disposed above, below or aligned to a surface of the base to improve routing ability for high-density semiconductor packages. As shown in  FIG. 1 , the conductive traces  202   a  have top surfaces  212   a  disposed below a device attach surface  214  of the base  200 . That is to say, a bottom surface  206   a  and at least a portion of a sidewall  204   a  of the conductive trace  202   a  are designed to be connected to the base  200 . In this embodiment, the solder cap  220  of the conductive structure  222  is disposed to contact with a portion of the base  200  and to connect to a top surface  212   a  of the conductive trace  202   a  only. Due to the top surfaces of the conductive traces being recessed from the device attach surface  214  of the base  200 , the bump-to-trace space is increased and the problem of bump-to-trace bridging can be effectively avoided. 
         [0025]      FIG. 2  shows a partial cross section of another exemplary embodiment of a semiconductor package  500   b  of the invention. Elements of the embodiments that are the same or similar as those previously described with reference to  FIG. 1 , are hereinafter not repeated for brevity. In this embodiment, conductive traces  202   b  of the semiconductor package  500   b  embedded in the base  200  may have a top surface  212   b  designed to be aligned to a device attach surface  214  of the base  200  to improve routing ability for high-density semiconductor packages. That is to say, a bottom surface  206   b  and a sidewall  204   b  of the conductive trace  202   b  are designed to be fully connected to the base  200 . Therefore, the solder cap  220  of the conductive structure  222  is disposed on the device attach surface  214  of the base  200 , contacting the top surface  212   b  of the conductive trace  202   b  only. 
         [0026]      FIG. 3  shows a partial cross section of yet another exemplary embodiment of a semiconductor package  500   c  of the invention. Elements of the embodiments that are the same or similar as those previously described with reference to  FIGS. 1 and 2 , are hereinafter not repeated for brevity. In this embodiment, conductive traces  202   c  of the semiconductor package  500   c  embedded in the base  200  may have a top surface  212   c  designed above a device attach surface  214  of the base  200  to improve routing ability for high-density semiconductor packages. That is to say, a bottom surface  206   c  and only a portion of a sidewall  204   c  of the conductive trace  202   c  are designed to be connected to the base  200 . Therefore, the solder cap  220  of the conductive structure  222  is disposed on the device attach surface  214  of the base  200 , wrapping a top surface  212   c  and only a portion of the sidewall  204   c  of the conductive trace  202   c.    
         [0027]      FIG. 4  shows a partial cross section of still another exemplary embodiment of a semiconductor package  500   d  of the invention. Elements of the embodiments that are the same or similar as those previously described with reference to  FIGS. 1-3 , are hereinafter not repeated for brevity. In one embodiment, the base may comprise a single layer structure as shown in  FIGS. 1-3 . Alternatively, the base may comprise a multilayer structure. In this embodiment, conductive traces  202   d  of the semiconductor package  500   d  embedded in the base portion  200   a  may have a top surface  212   d  designed to be aligned to a surface  214  of the base portion  200   a  to improve routing ability for high-density semiconductor packages. That is to say, a bottom surface  206   d  and a sidewall  204   d  of the conductive trace  202   d  are designed to be connected to the base portion  200   a.  Also, an insulation layer  208  having openings  210  is disposed on the base portion  200   a.  The insulation layer  208  is disposed above the device attach surface  214  of the conductive trace  202   d.  In this embodiment, the base portion  200   a  and the insulation layer  208  collectively serve as a multilayer base. As shown in  FIG. 4 , the conductive traces  202   d  are exposed within the openings  210 . Therefore, the solder cap  220  of the conductive structure  222  is formed through a portion of the insulation layer  208 , contacting a top surface  212   d  of the conductive trace  202   d  only. It should be noted that it is not necessary for the insulation layer  208  to align with the sidewall  204   d  of the conductive traces  202   d.  Instead, it can be designed to be distanced outward or inward from the sidewall  204   d  of the conductive traces  202   d  as shown in  FIG. 4 . 
         [0028]      FIGS. 5   a  to  5   d  are cross sections showing one exemplary embodiment of a method for fabricating two bases  200   c  and  200   d  for a semiconductor package of the invention. In this embodiment, the method for fabricating bases for a semiconductor package is also called a double-sided base fabricating process. Elements of the embodiments that are the same or similar as those previously described with reference to  FIGS. 1-4 , are hereinafter not repeated for brevity. As shown in  FIG. 5   a,  a carrier  400  with conductive seed layers  402   a  and  402   b  on a top surface  401  and a bottom surface  403  is provided. In one embodiment, the carrier  400  may comprise FR4 glass epoxy or stainless steel. Also, the conductive seed layers  402   a  and  402   b  are used as seed layers for subsequently formed interconnection conductive traces of bases on the top surface  401  and the bottom surface  403  of the carrier  400 . In one embodiment, the conductive seed layers  402   a  and  402   b  may comprise copper. 
         [0029]    Next, as shown in  FIG. 5   b,  first conductive traces  404   a  and  404   b  are respectively formed on the top surface  401  and the bottom surface  403  of the carrier  400 . Bottom portions of the first conductive traces  404   a  and  404   b  connect to top portions of the conductive seed layers  402   a  and  402   b.  In one embodiment, the first conductive traces  404   a  and  404   b  may be formed by a plating process and an anisotropic etching process. The plating process and the anisotropic etching process are simultaneously performed on the top surface  401  and the bottom surface  403  of the carrier  400 . In one embodiment, the plating process may comprise an electrical plating process. In one embodiment, the first conductive traces  404   a  and  404   b  may comprise copper. In one embodiment, the first conductive traces  404   a  and  404   b  are designed to have a width which is larger than 5 μm. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than 5 μm if required. In this embodiment, the anisotropic etching process may precisely control the width of the first conductive traces  404   a  and  404   b.    
         [0030]    Next, as shown in  FIG. 5   c,  a laminating process is performed to respectively dispose a first base material layer  406   a  and a second base material layer  406   b  on the top surface  401  and the bottom surface  403  of the carrier  400 , wherein the first base material layer  406   a  and a second base material layer  406   b  respectively cover the first conductive traces  404   a  and  404   b.  In this embodiment, the laminating process of the first base material layer  406   a  and the second base material layer  406   b  is simultaneously performed on the on the top surface  401  and the bottom surface  403  of the carrier  400 . In one embodiment, the first base material layer  406   a  and the second base material layer  406   b  may comprise polypropylene (PP). 
         [0031]    Next, please refer to  FIG. 5   c  again, wherein a drilling process is performed to form openings (not shown) through the first base material layer  406   a  and the second base material layer  406   b  to define the formation positions of subsequently formed vias  408   a  and  408   b.  In one embodiment, the drilling process may comprise a laser drilling process, an etching drilling process or a mechanical drilling process. Next, a plating process is performed to fill a conductive material into the openings to form vias  408   a  and  408   b  for interconnecting the first conductive traces  404   a  and  404   b  to subsequent second conductive traces  410   a  and  410   b.  In this embodiment, the drilling process and the plating process are simultaneously performed on the first base material layer  406   a  and the second base material layer  406   b,  respectively. 
         [0032]    Next, please refer to  FIG. 5   c  again, wherein a plurality of second conductive traces  410   a  and  410   b  are respectively formed on a first surface  412  of the first base material layer  406   a  and a first surface  414  of the second base material layer  406   b.  As shown in  FIG. 5   c,  the first surface  412  of the first base material layer  406   a  and the first surface  414  of the second base material layer  406   b  are respectively away from the top surface  401  and the bottom surface  403  of the carrier  400 . The second conductive traces  410   a  and  410   b  are formed by a plating process and an anisotropic etching process. The plating process and the anisotropic etching process are simultaneously performed on the first surface  412  of the first base material layer  406   a  and the first surface  414  of the second base material layer  406   b.  In one embodiment, the plating process may comprise an electrical plating process. In one embodiment, the second conductive traces  410   a  and  410   b  may comprise copper. In one embodiment, the second conductive traces  410   a  and  410   b  are designed to have a width which is larger than 5 μm. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than 5 μm if required. In this embodiment, the anisotropic etching process may precisely control the width of the second conductive traces  410   a  and  410   b.    
         [0033]    Next, as shown in  FIG. 5   d,  the first base material layer  406   a  with the first and second conductive traces  404   a  and  410   a  thereon and the second base material layer  406   b  with the first and second conductive traces  404   b  and  410   b  thereon are respectively separated from the top surface  401  and the bottom surface  403  of the carrier  400  to form a first base  200   c  and a second base  200   d  which are separated from each other. Next, as shown in  FIG. 5   d  again, the conductive seed layers  402   a  and  402   b  are removed from the first base  200   c  and the second base  200   d,  respectively. 
         [0034]    As shown in  FIGS. 5   d  and  5   e,  the first conductive traces  404   a  and  404   b  are aligned to second surfaces  416  and  418  of the of the first and second bases  200   c  and  200   d,  which are respectively opposite to the first surfaces  412  and  414 . In this embodiment, the first base  200   c  and the second base  200   d  are simultaneously fabricated on opposite surfaces (the top surface  401  and the bottom surface  403 ) by the double-sided base fabricating process. 
         [0035]    Alternatively, two passivation or insulation layers (not shown) having openings may be optionally formed respectively on a second surface  416  of the first base  200   c  and the second surface  418  of the second base  200   d  after the separation of the first base  200   c  and the second base  200   d  as shown in  FIGS. 5   d  and  5   e.  In this embodiment, the first conductive traces  404   a  and  404   b  of the first and second bases  200   c  and  200   d  are exposed within the opening. Positions of the insulation layer with openings and the first conductive traces  404   a/   404   b  as shown in  FIG. 5   d/   5   e  can be similar to the insulation layer  208  with openings  210  and the conductive traces  202   d  as shown in  FIG. 4 . Also, in this embodiment, the first base  200   a/ second base  200   b  and the insulation layer thereon collectively serve as a multilayer base. 
         [0036]      FIGS. 6   a  to  6   e  are cross sections showing another exemplary embodiment of a method for making a semiconductor package of the invention. Also,  FIG. 6   e  shows a cross section of another exemplary embodiment of a semiconductor package  500   e  of the invention. Elements of the embodiments that are the same or similar as those previously described with reference to  FIGS. 1-4  and  5   a - 5   e,  are hereinafter not repeated for brevity. Alternatively, the base may have a multilayer structure. As shown in  FIG. 6   a,  a base  450  with a top surface  451  is provided. Next, as shown in  FIG. 6   b,  at least one conductive trace  454  is formed on the top surface  451  of the base  450 . In one embodiment, the conductive trace  454  may be formed by a plating process and an anisotropic etching process. In one embodiment, the plating process may comprise an electrical plating process. In one embodiment, the conductive trace  454  may comprise copper. In one embodiment, the conductive trace  454  is designed to have a width which is larger than 5 μm. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than 5 μm if required. In this embodiment, the anisotropic etching process may precisely control the width of the conductive trace  454 . 
         [0037]    Next, as shown in  FIG. 6   c,  a laminating process is performed to respectively dispose an additional insulation material  456  on the top surface  451  of the base  450 . Also, the additional insulation material  456  covers a top surface  460  and sidewalls  462  of the conductive trace  454 . 
         [0038]    Next, please refer to  FIG. 6   d,  wherein a drilling process is performed to form at least one opening  458  through the additional insulation material  456  to define formation of a position of a subsequently formed conductive structure, for example, a copper bump structure or a solder bump structure. In one embodiment, the drilling process may comprise a laser drilling process, an etching drilling process or a mechanical drilling process. In this embodiment, the top surface  460  of the conductive trace  454  is exposed within the opening  458  of the additional insulation material  456 . 
         [0039]    Next, as shown in  FIG. 6   e,  a bonding process is performed to mount a semiconductor device  300  on the base  450  through the conductive structure  222 . Elements of the semiconductor device  300  and the conductive structure  222  that are the same or similar as those previously described with reference to  FIGS. 1-4 , are hereinafter not repeated for brevity. After the bonding process, the conductive structures  222  are disposed through the opening  458  of the additional insulation material  456 , contacting to the top surface  460  of the conductive trace  454  only. Next, an underfill material or the underfill  230  can be introduced into the gap between the semiconductor device  300  and the additional insulation material  456 . In one embodiment, the underfill  230  may comprises a capillary underfill (CUF), molded underfill (MUF) or a combination thereof. Finally, the base  450 , the additional insulation material  456 , the semiconductor device  300 , the conductive trace  454 , and the conductive structure  222  collectively form a semiconductor package  500   e.    
         [0040]    Exemplary embodiments provide a semiconductor package. The semiconductor package is designed to comprise conductive trace embedded in a base, for example, a print circuit board (PCB). The conductive traces may have a top surface disposed above, below or aligned to a surface of the base to improve routing ability for high-density semiconductor packages. Also, the conductive traces are designed to have a width which is larger than 5 μm. Further, the base may comprise a single layer structure or a multilayer structure. Exemplary embodiments also provide a method for fabricating a base for a semiconductor package. In one embodiment, the method can fabricate two bases on two sides of a carrier simultaneously. Also, the conductive traces may be embedded in the base. Further, the conductive trace may be formed by a plating process and an anisotropic etching process, and the anisotropic etching process may precisely control the width of the conductive trace. Alternatively, the method can fabricate a base comprising a single layer structure or a multilayer structure to improve design capability. 
         [0041]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.