Abstract:
A method for reducing a supply voltage drop in a digital circuit block, where the digital circuit block includes a first conducting segment coupled to a first supply voltage, a second conducting segment coupled to a second supply voltage, and a digital logic coupled between the first conducting segment and the second conducting segment, the method including: constructing a third conducting segment connected to the first conducting segment and not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer; and constructing a fourth conducting segment electrically connected to the second conducting segment and not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at a second conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.

Description:
BACKGROUND  
       [0001]    The present invention is related to supplying a supply voltage to a digital circuit, and more particularly, to a layout architecture for reducing leakage current of the supply voltage path of the supply voltage of the digital circuit and a method thereof. 
         [0002]    In the field of digital circuit design, one of the most efficient ways to arrange each of the digital cells within a digital circuit is to perform an automatic placement and routing (APR) process upon the functional digital cells after the digital circuit is designed. Normally, the APR process is performed by software tools. Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a prior art digital circuit  10  after performing the APR process. The digital circuit  10  comprises a plurality of functional digital cells  11   a ˜ 11   d,  a power rail  12 , and a ground rail  13 , in which the power rail  12  is coupled to a supply voltage VDD to supply power to each of the functional digital cells  11   a ˜ 11   d,  and the ground rail  13  provides a ground voltage GND for the functional digital cells  11   a ˜ 11   d.  However, the APR process may generate a gap between some of the two functional digital cells, such as the gap  14  between the functional digital cells  11   b  and  11   c,  when optimizing the whole digital circuit  10 . If this happens, the gap  14  will be filled up by a filler capacitor  15  in order to stabilize the supply voltage VDD for the functional digital cells  11   b  and  11   c.  However, since the filler capacitor  15  is implemented by a CMOS (Complementary Metal Oxide Semiconductor) transistor, and the electric charge of the filler capacitor is accumulated on the gate terminal and the substrate of the CMOS transistor, the electric charge may leak from the gate terminal to the substrate of the CMOS transistor. Therefore, a significant leakage current may be induced if the digital circuit  10  includes a large number of filler capacitors. Accordingly, to reduce the leakage current problem of the digital circuit  10  is becoming one of the most urgent problems in the field of digital circuit design. 
       SUMMARY OF THE INVENTION  
       [0003]    One of the objectives of the present invention is provide a layout architecture for reducing leakage current of the supply voltage path of a supply voltage of a digital circuit and a method thereof. 
         [0004]    According to an embodiment of the present invention, a method for reducing a supply voltage drop in a digital circuit block is provided, wherein the digital circuit block comprises a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment. The method comprises the following steps: constructing a third conducting segment having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer, and an dielectric layer is between the first conducting layer and a second conducting layer; and constructing a fourth conducting segment having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the second conducting layer, whereby a first capacitive element is formed between the first portion and the second portion. 
         [0005]    According to a second embodiment of the present invention, a method for reducing a supply voltage drop in a digital circuit block is provided, wherein the digital circuit block comprises a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the method comprising the following steps: constructing a third conducting segment having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a conducting layer; and constructing a fourth conducting segment having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the conducting layer, whereby a capacitive element is formed between the first portion and the second portion. 
         [0006]    According to a third embodiment of the present invention, a layout architecture for reducing a supply voltage drop in a digital circuit block is provided, wherein the digital circuit block comprises a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the layout architecture comprises a third conducting segment and a fourth conducting segment. The third conducting segment has a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer, and an dielectric layer is between the first conducting layer and a second conducting layer; and the fourth conducting segment has a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the second conducting layer, whereby a first capacitive element is formed between the first portion and the second portion. 
         [0007]    According to a fourth embodiment of the present invention, a layout architecture for reducing a supply voltage drop in a digital circuit block is provided, wherein the digital circuit block comprises a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, and the layout comprises a third conducting segment and a fourth conducting segment. The third conducting segment has a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a conducting layer. The fourth conducting segment has a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the conducting layer, and whereby a capacitive element is formed between the first portion and the second portion. 
         [0008]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a diagram illustrating a prior art digital circuit after performing an APR process. 
           [0010]      FIG. 2  is a top view diagram illustrating a layout architecture for reducing a supply voltage drop in a digital circuit block according to an embodiment of the present invention. 
           [0011]      FIG. 3  is a space diagram illustrating the layout architecture of the digital circuit block as shown in  FIG. 2 . 
           [0012]      FIG. 4  is a diagram illustrating a side view diagram of a Metal-dielectric-metal capacitor of the digital circuit block as shown in  FIG. 2 . 
           [0013]      FIG. 5  is a flowchart illustrating a method for reducing a supply voltage drop in the digital circuit block of the embodiment as shown in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION  
       [0014]    Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0015]    Please refer to  FIG. 2  in conjunction with  FIG. 3 .  FIG. 2  is a top view diagram illustrating a layout architecture  202  for reducing a supply voltage drop in a digital circuit block  200  according to an embodiment of the present invention, wherein the digital circuit block  200  comprises a first conducting path  2022  having a first end coupled to a first supply voltage, such as Vdd, a second conducting path  2024  having a first end coupled to a second supply voltage, such as ground voltage Vgnd, and a digital logic  2026  coupled between a second end of the first conducting path  2022  and a second end of the second conducting path  2024 .  FIG. 3  is a space diagram illustrating the layout architecture  202  of the digital circuit block  200  as shown in  FIG. 2 . Please note that, according to the embodiment of the present invention, the layout architecture  202  provides a capacitance block between the first conducting path  2022  and the second conducting path  2024  in order to reduce the supply voltage Vdd IR drop (e.g., dynamic voltage drop) to the digital logic  2026 . The layout architecture  202  comprises conducting segments  202   a,    202   b,    202   c,    202   d,    202   e,    202   f,  vias  202   g,    202   h,    202   i,    202   j,  and a metal-dielectric-metal capacitor  202   k.  The conducting segments  202   a,    202   b  have a first end electrically connected to the first conducting path  2022  and a second end not electrically connected to the second conducting path  2024 , and the conducting segments  202   c,    202   d  have a first end electrically connected to the second conducting path  2024  and a second end not electrically connected to the first conducting path  2022 . 
         [0016]    According to the embodiment of the present invention, the conducting segment  202   e  coupled to the conducting segments  202   a  and  202   b  through the vias  202   g  and  202   i  respectively, and the conducting segment  202   f  coupled to the conducting segments  202   c  and  202   d  through the vias  202   h  and  202   j  respectively. Furthermore, the metal-dielectric-metal capacitor  202   k  is constructed under the region between the conducting segments  202   a  and  202   c.  Therefore, in this embodiment, the first conducting path  2022 , the second conducting path  2024 , the conducting segments  202   a,    202   b,    202   c,    202   d  are located at the same conducting layer L 6 , such as the top conducting layer (e.g., layer  6 ) of a semiconductor process; and the conducting segments  202   e,    202   f  are located at the other conducting layer L 5 , such as layer  5  of the semiconductor process, as shown in  FIG. 3 . In other words, the layer L 6  is adjacent to the layer L 5 . However, the two conducting layers could also not adjacent to each other. In other words, those skilled in this art are readily to understand that the metal-dielectric-metal capacitor  202   k  could be implemented between any two conducting layers. Furthermore, a dielectric layer L IN  may be between the conducting layer L 6  and the conducting layer L 5 , in which the dielectric layer L IN  can be implemented by an oxide layer. Please note that, the layout architecture  202  is just an example of the embodiment of the digital circuit block  200 , and is not meant to be a limitation of the present invention. In other words, the number of the conducting segments, vias, and metal-dielectric-metal capacitors and the arrangement between the conducting segments, vias, and metal-dielectric-metal capacitors can be adjusted according to practical conditions, such as the area required by the layout architecture  202 , of the implementation of the digital circuit block  200 . 
         [0017]    Please refer to  FIG. 2  again. Since the conducting segments  202   b,    202   d  are located at the conducting layer L 6 , and the conducting segments  202   e,    202   f  are located at the conducting layer L 5 , a capacitor C 1  may be formed between the overlapped region of the conducting segments  202   d  and  202   e,  which is an oblique line portion  202   d ′; and a capacitor C 2  may be formed between the overlapped region of the conducting segments  202   b  and  202   f,  which is the oblique line portion  202   b ′. Furthermore, since the conducting segments  202   b  and  202   d  do not electrically contact with each other, a capacitor C 3  may be formed between the conducting segments  202   b  and  202   d.  Similarly, a capacitor C 4  may be formed between the conducting segments  202   e  and  202   f.    
         [0018]    Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating a side view diagram of the metal-dielectric-metal capacitor  202   k  of the digital circuit block  200  along line I-I′ as shown in  FIG. 2 . Please note that, the via  202   h  and the capacitor C 2  is omitted in the side view diagram of  FIG. 4  for the purpose of illustration, and the vias  202   h ′ and  202   i  illustrated in dotted line represents that the vias  202   h ′ and  202   i  are in the background from the line I-I′ and the via  202   g ′ is in the foreground from the line I-I′. The metal-dielectric-metal capacitor  202   k  comprises the conducting segment  202   a,  the conducting segment  202   c,  a top plate  402 , a bottom plate  404 , and a dielectric plate  406 , in which the dielectric plate  406  can be implemented by an oxide layer. In addition, the conducting segment  202   a  is electrically connected with the top plate  402  through the via  202   g ′, and the conducting segment  202   c  is electrically connected with the bottom plate  404  through the via  202   h ′. Please note that, in order to illustrate the placement of the metal-dielectric-metal capacitor  202   k  more clearly,  FIG. 4  further shows up the conducting segment  202   b,  the via  202   i,  and the conducting segment  202   e  of the layout architecture  202 . Furthermore, an insulating layer may be constructed between the bottom plate  404  and the conducting segment  202   e  in the dielectric layer L IN . Therefore, according to the embodiment of the present invention, the metal-dielectric-metal capacitor  202   k  provides another capacitive element between the first conducting path  2022  and the second conducting path  2024 . Please note that, those skilled in this art will readily understand that the metal-dielectric-metal capacitor can be implemented between any two conducting layers, such as the conducting layer L 6  and L 5  of the above-mentioned embodiment, and can be rearranged into any appropriate shape depending on the configuration between the first conducting path  2022  and the second conducting path  2024 . Besides, it is not necessary for the two conducting layers to be adjacent to each other. Since the metal-dielectric-metal capacitor is well-known to those skilled in this art, a detailed description is omitted here for brevity. 
         [0019]    Accordingly, when the digital logic  2026  loads the current from the supply voltage Vdd at the first conducting path  2022 , the energy that is stored in the capacitors C 1 , C 2 , C 3 , and C 4  can provide the required current to the digital logic  2026  instantaneously. Therefore, the supply voltage Vdd IR drop (e.g., dynamic voltage drop) of the digital logic  2026  can be minimized. Furthermore, since the capacitors C 1 , C 2 , C 3 , and C 4  store the energy (i.e., electric charge) in the region of the conducting layer of the semiconductor architecture, but do not utilize the substrate of the semiconductor architecture to store the energy as in the prior art, the leakage current of the layout architecture  202  of the digital circuit block  200  is much smaller than the prior art current. 
         [0020]    Please refer to  FIG. 5 .  FIG. 5  is a flowchart illustrating a method  500  for reducing the supply voltage drop in the digital circuit block  202  of the embodiment as shown in  FIG. 2 . Provided that substantially the same result is achieved, the steps of the flowchart shown in  FIG. 5  need not be in the exact order shown, need not be contiguous, that is, other steps can be intermediate, and need not be executed completely. The method  500  comprises: 
         [0021]    Step  502 : performing a supply voltage path routing, such as an auto placement and routing (APR) process upon the digital logic  2026  to generate the first conducting path  2022  and the second conducting path  2024 ; 
         [0022]    Step  504 : determining a region between the first conducting path  2022  and the second conducting path  2024  for the layout architecture  202 ; 
         [0023]    Step  506 : constructing the conducting segment  202   a,    202   b  having the first end electrically connected to the first conducting path  2022  and a second end not electrically connected to the second conducting path  2024 , wherein the conducting segment  202   a,    202   b  are located in layer L 6 ; 
         [0024]    Step  508 : constructing the conducting segment  202   c,    202   d  having a first end electrically connected to the second conducting path  2024  and a second end not electrically connected to the first conducting path  2022 , wherein the conducting segment  202   c,    202   d  are located in layer L 6 ; 
         [0025]    Step  510 : constructing the conducting segment  202   e,    202   f  in the layer L 5 ; 
         [0026]    Step  512 : utilizing the vias  202   h  and  202   j  to couple the conducting segments  202   c  and  202   d  to the conducting segment  202 f respectively, and utilizing the vias  202   g  and  202   i  to couple the conducting segments  202   a  and  202   b  to the conducting segment  202   e  respectively; and 
         [0027]    Step  514 : constructing the metal-dielectric-metal capacitor  202   k  under the region between the conducting segments  202   a  and  202   c.    
         [0028]    The first conducting path  2022  may be coupled to the supply voltage Vdd and the second conducting path  2024  may be coupled to the ground voltage Vgnd (Step  502 ). After the APR process, one of the embodiments of the present invention may have filler capacitor cells between the region of the first conducting path  2022  and the second conducting path  2024 , and it may be necessary for the method  500  to remove the filler capacitor cells first. Then, the region between the first conducting path  2022  and the second conducting path  2024  can be utilized for constructing the layout architecture  202  (Step  504 ). Please note that, this is just an optional step of the embodiment, and not a limitation of the present invention. In other words, the APR process may automatically provide the regions for the layout architecture  202  after performing the APR process upon the digital circuit block  200 . 
         [0029]    Please refer to  FIG. 2  and  FIG. 3 . In step  506 ˜ 512 , the capacitor C 1  is formed between the overlapped region of the conducting segments  202   d  and  202   e,  which is formed by a portion  202   d ′; and the capacitor C 2  is formed between the overlapped region of the conducting segments  202   b  and  202   f,  which is formed by a portion  202   b ′. Furthermore, the capacitor C 3  is formed between the conducting segments  202   b  and  202   d.  Similarly, the capacitor C 4  is formed between the conducting segments  202   e  and  202   f.  In step  514 , the metal-dielectric-metal capacitor  202   k  is constructed under the region between the conducting segments  202   a  and  202   c,  and comprises the conducting segment  202   a,  the conducting segment  202   c,  a top plate  402 , a bottom plate  404 , and a dielectric plate  406  as shown in  FIG. 4 . In addition, the method  500  utilizes the via  202   g ′ to electrically connect the conducting segment  202   a  with the top plate  402 , and utilizes the via  202   h ′ to electrically connect the conducting segment  202   c  with the bottom plate  404 . Therefore, the metal-dielectric-metal capacitor  202   k  provides another capacitive element between the first conducting path  2022  and the second conducting path  2024 . Those skilled in this art will readily understand that the metal-dielectric-metal capacitor can be implemented between any two conducting layers, such as the conducting layer L 6  and L 5  in the above-mentioned embodiment, and can be rearranged into any appropriate shape depending on the configuration between the first conducting path  2022  and the second conducting path  2024 . Besides, it is not necessary for the two conducting layers to be adjacent to each other. Since the Metal-dielectric-metal capacitor is well-known to those skilled in this art, a detailed description is omitted here for brevity. 
         [0030]    Please note that the layout architecture  202  generated under the method  500  is just an example of the present invention, and not a limitation of the present invention. In other words, the number of the conducting segments, vias, and metal-dielectric-metal capacitors and the arrangement between the conducting segments, vias, and metal-dielectric-metal capacitors can be adjusted according to practical conditions, such as the area available for the layout architecture  202 , of the implementation of the digital circuit block  202 . 
         [0031]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.