Abstract:
A circuit having a plurality of circuit blocks formed on a semiconductor substrate is disclosed. The circuit blocks are stitched together by appropriately connecting input and output lines of the plurality of circuit blocks. The circuit also includes connecting circuits coupled to the plurality of circuit blocks. The connecting circuits provide low voltage drop across boundaries where the plurality of circuit blocks are stitched together.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 60/123,582, filed on Mar. 10, 1999. 
    
    
     BACKGROUND 
     This disclosure relates to integrated circuit fabrication. 
     As integrated circuit (IC) fabrication technique advances, semiconductor manufacturers continue to develop techniques to construct integrated circuits with structures having dimensions in the sub-micron range on a semiconductor substrate. Improvements in photolithographic processing techniques have substantially contributed to the miniaturization of active semiconductor devices to dimensions below a single micron. The fabrication of these semiconductor devices often involves the transfer of circuit patterns from a photolithographic mask or reticle onto a photoresist layer. The process uses an imaging lens apparatus. 
     The reticle is often itself constructed from a substrate of silicon dioxide. The reticle can be patterned with areas of differing transmissivity thereon. The patterned areas of the reticle represent either the positive or negative images of an integrated circuit structure. After being properly positioned and aligned over the semiconductor wafer, the reticle is subjected to electromagnetic radiation. The radiation passes through transparent portions of the reticle, striking portions of the photoresist layer on the wafer. The resist coating is developed and etched so as to impart a positive or negative image of the reticle pattern onto the photoresist layer remaining on the wafer. 
     Conventional photolithographic methods of fabricating integrated circuits on a substrate often involve stepping a reticle and imaging apparatus across a photoresist coated wafer. The methods also involve repeatedly transferring the reticle image pattern to adjacent areas on the wafer. Each of the individual areas on the wafer containing the circuitry image is termed a die. The wafer is cut or otherwise segmented at the end of the fabrication process so that the dice are separated from one another for subsequent packaging as individual integrated circuit chips. 
     As integrated circuits become increasingly complex, however, the integrated circuit structures within an individual die have become significantly smaller and denser. Larger reticles are often required to transfer larger and more complex circuit images to substrate fields of increased dimensions. Because of inherent image resolution limitations associated with conventional photolithographic processes, imaging and alignment errors are often introduced when fine line structures having sub-micron dimensions are produced on relatively large reticles. Further, steppers used in photolithographic process also set the limit on the size of the printed circuit. 
     SUMMARY 
     The inherent limitations associated with producing relatively large reticles having structures with sub-micron dimensions have motivated development of different types of integrated circuits (IC) with larger fields. One type of circuit includes a plurality of circuit blocks formed on a semiconductor substrate. The circuit blocks are stitched together by appropriately connecting input and output lines of the plurality of circuit blocks. The circuit also includes connecting circuits coupled to the plurality of circuit blocks. The connecting circuits provide low voltage drop across boundaries where the plurality of circuit blocks are stitched together. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Different aspects of the disclosure will be described in reference to the accompanying drawings wherein: 
     FIG.1 shows a substrate having a composite field fabricated using stitching technique in accordance with one aspect of the present invention; 
     FIG. 2 shows sub-fields on a reticle corresponding to each function block; 
     FIG. 3 is a schematic diagram of a row select circuit in accordance with one aspect of the present invention; and 
     FIG. 4 is a schematic diagram of a shift register in accordance with one aspect of the present invention. 
    
    
     DETAILED DESCRIPTION 
     The inherent limitations associated with producing relatively large reticles having structures with sub-micron dimensions have motivated development of new methods of fabricating integrated circuits (IC) with larger fields. One such photocomposition method, known as “stitching,” is directed to producing larger reticle fields by sub-dividing the circuitry pattern. The sub-field patterns are then stitched or recomposed to form a large composite circuit field thereon. 
     As illustrated in FIG. 1 of the drawings, a substrate having a field  100  is shown as a composite field fabricated using the stitching technique. Often, a field  100  is image patterns of an integrated circuit structure. In the illustrated embodiment, the field  100  is a representation of the image patterns of a large image sensor having a large pixel sensor array  102 - 116 . The large image sensors are well suited for stitching because many parts of the sensors are duplicative. 
     The substrate circuit is constructed by first photolithographically patterning smaller sub-fields  120 ,  130 ,  140 ,  150 , with each sub-field bearing a portion of the image pattern of the integrated circuit structure. The sub-fields  120 ,  130 ,  140 ,  150  are then stitched together along stitching boundaries  124 ,  134 ,  144 ,  152 ,  160 ,  170 ,  180  to form the composite field  100 . The image patterns of sub-fields  120 ,  130 ,  140 ,  150  substantially adjoin each other with a high accuracy in order to avoid any alignment errors that otherwise occur with respect to the millions of fine line interconnections necessary to “re-connect” adjacent sub-fields along the stitching boundaries  124 ,  134 ,  144 ,  152 ,  160 ,  170 ,  180 . Each of the sub-fields  120 ,  130 ,  140 ,  150  contains one or more functional blocks, which together form a complex integrated system. 
     For some embodiments of the large image sensors, there are areas near the stitching boundaries  124 ,  134 ,  144 ,  152 ,  160 ,  170 ,  180  where there are no pixel coverage. To minimize the area with no pixel coverage, a shift register for the row select and reset select circuit have been incorporated into the middle of the pixel array. The circuit field  100  of the large image sensor includes a pixel sensor array  102 - 116 , pixel signal routing areas  122 ,  132 ,  136 ,  142 ,  146 , a row logic  134 ,  144 , a column logic  154 , and a readout logic  156 . 
     Individual sets of reticles are initially patterned with images representative of the circuitry structures comprising each of the function blocks  102 - 116 ,  122 - 124 ,  132 - 136 ,  142 - 146 ,  152 - 156 . Each function block is preferably defined within a single field on the reticle  200  as shown in FIG.  2 . For example, the field  1  corresponds to the function blocks  106 - 112  while the field  3  corresponds to the function blocks  102 ,  104 . The image patterns comprising each of the fields on the reticle  200  corresponding to the function blocks  102 - 116 ,  122 - 124 ,  132 - 136 ,  142 - 146 ,  152 - 156  are then transferred to the substrate. Upon completion of the initial transfer of function block image patterns from the individual fields to the substrate, each of the function block patterns on the field  100  can be considered to be electrically independent with respect to all other function blocks. Considering, for example, function blocks  102 - 116 , a plurality of row and column pixel currents flow through the lines and preferably terminate at predetermined locations along the perimeters of the blocks  102 - 116 . To minimize the voltage drops across the areas between the blocks  102 - 116 , the areas  124 ,  134 ,  144 ,  152  have been designed with stitching circuits, such as row and column select circuits having shift registers. These circuits are designed with minimal power dissipation. 
     FIGS. 3 and 4 illustrate the row select circuit  300  and the shift register  400  in accordance with one aspect of the present invention. To minimize the logic, the shift register  400  shown in FIG. 4 can implement the column select logic as well. The row select circuit  300  selects the row  302  indicated by the input  304  at the edge of the clock signal  306 . The input  304  can be reset with a reset signal  308 . The selected row  302  can be reset with an Srst signal  310 . The global reset signal  312 , Grst, resets the entire array. 
     The shift register  400  receives a clock signal and sends the signal to the gate terminals of the transistors Q 1 , Q 2 , and Q 4 . The input signal drives the gate terminal of the transistor Q 3 . The transistor Q 3 , in conjunction with the transistor Q 4 , drives the node  402  either to high (V DD ) or low voltage (V SS ), depending on the voltage level of the input signal. The node  402  can be pulled up through the transistors Q 10  and Q 11 . The pull-up is triggered by the clock signal using the transistors Q 9 , Q 12 , and Q 13 . The node  402  can be pulled down through the transistors Q 3  and Q 4 . The pull-down is triggered by the inverse clock signal using the transistors Q 5  and Q 6 . The transistor Q 5  drives the output. The transistors Q 14  to Q 19  drive the inverse output. The shift register  400  can be reset by a reset signal through the transistor Q 7 . 
     With the stitched circuit of the present invention, resolution can be increased without reducing the field size or increasing the lens size. An area larger than the maximum reticle size can be formed by appropriately stitching the blocks with row and column select circuits and shift registers in accordance with some aspects of the present invention. The resultant area has increased the resolution producible with lens without increasing the lens size or decreasing the field size. 
     Accordingly, the complexity and functionality of each function block may be dramatically increased, resulting in large part from the ability to utilize a maximum available reticle field area for the integrated circuitry defining each function block. 
     Above described aspects and embodiments are for illustrative purposes only. Other embodiments and variations are possible. For example, the concept of connecting the seams with select circuits and shift registers can be used in circuits other than the image sensors, such as any integrated circuits having large duplicative areas. 
     All these are intended to be encompassed by the following claims.