Abstract:
A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Description:
[0001]    This application claims the benefit of U.S. Provisional Patent Application Ser. No. 62/351,746, filed Jun. 17, 2016, entitled “Self Aligned Contact and Manufacturing Method Thereof,” which application is incorporated herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    Metal-oxide-semiconductor field-effect transistors (FETs or MOSFETs) are widely used in integrated circuits (ICs). To increase the density of MOSFETs in ICs, physical dimensions such as gate length LG of MOSFETs are aggressively reduced. MOSFETs with short LG may suffer from undesirable short-channel effects (SCEs), such as high off-state leakage current and high drain-induced barrier lowering. 
         [0003]    To suppress SCEs in transistors having short gate lengths LG, the multiple-gate field-effect transistor (MuGFET) architecture may be employed. A MuGFET has better electrostatic control of the channel potential by the gate electrode, as compared to a planar device structure. MuGFETs include examples such as the double-gate transistor and tri-gate or triple-gate transistor. A double-gate transistor is also known as a double-gate FinFET. A tri-gate transistor may be referred to as tri-gate FinFET, or simply FinFET. Double-gate or tri-gate devices employ a channel that resembles a fin. The on-state or saturation drive current IDsat flows in a fin to achieve high current density per footprint or layout area. 
         [0004]    Other MuGFETs include pi-gate, omega-gate, surround-gate (SG) or gate-all-around (GAA) structure, where the electrostatic gate control is further improved. The SG transistor has a channel that is similar to a nanowire, where the nanowire may be oriented horizontally or vertically. For a horizontal nanowire transistor, several horizontally-oriented nanowire channels may be vertically stacked. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
           [0006]      FIGS. 1A-13D  illustrate various intermediate process steps in a fabrication process in accordance with some embodiments. 
           [0007]      FIGS. 14A-17B  illustrate various profiles that may be used in combination with other disclosed embodiments. 
           [0008]      FIGS. 18A-28D  illustrate various intermediate process steps in a fabrication process in accordance with some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    It is understood that this disclosure provides many embodiments or examples for implementing this invention. Specific examples are described below, and are not intended to be limiting. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
         [0010]    Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
         [0011]    Disclosed embodiments relate to a method of forming a contact for multiple-gate field-effect transistors, including a method of forming self-align contacts, and reducing fringing capacitance between the gate and the contact for such devices with metal gate electrodes. The embodiments such as those disclosed herein are generally applicable to double-gate or triple-gate FinFETs, surround-gate or gate-all-around transistors and/or nanowire transistors. 
         [0012]    As discussed in greater detail below, embodiments are disclosed that provide a process flow to integrate metal gate electrode and self-aligned contact for multiple-gate field-effect transistors or MuGFETs (double-gate, triple-gate FinFETs, and horizontal gate-all-around transistors), but may be applied to other structures as well. Disclosed embodiments may provide reduced fringing capacitance between the metal gate and the contact for multiple-gate field-effect transistors or MuGFETs (double-gate, triple-gate FinFETs, and horizontal gate-all-around transistors). 
         [0013]    For purposes of illustration, the Figures and the following discussion refer to one fin and three gates. It is noted, however, that in other embodiments more fins may be used and fewer or greater gates may be used. Furthermore, other structures may be used. For example, epitaxial regions of adjacent fins may be joined to form a single larger source/drain region. 
         [0014]      FIGS. 1A-13C  are cross-sectional views and perspective views of intermediate stages in the manufacturing of a FinFET and the respective contacts in accordance with some embodiments. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In  FIGS. 1A-13C , the “A” figures (e.g.,  FIGS. 1A, 2A , etc.) illustrate a perspective view, the “B” figures (e.g.,  FIGS. 1B, 2B , etc.) illustrate a cross-sectional view along the Y-cut line illustrated in the respective “A” figure, and the “C” figures (e.g.,  FIGS. 1C, 2C , etc.) illustrate a cross-sectional view along the X-cut line illustrated in the respective “A” figure. 
         [0015]    Referring first to  FIGS. 1A-1C , there is shown a substrate  102  having one or more fins, with one fin  104  being illustrated. It is understood that one fin is illustrated for purposes of illustration, but other embodiments may include any number of fins. The substrate  102  may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET. 
         [0016]    In some embodiments, the substrate  102  may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide InmGal-mAs, indium arsenide, indium phosphide, indium antimonide. gallium arsenic phosphide, or gallium indium phosphide), or the like. Further, the substrate  102  may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure. 
         [0017]    The fin  104  may be formed using, for example, a patterning process to form trenches  108  such that the fin  104  is formed between adjacent fins. In some embodiments, photolithography techniques are utilized to pattern a masking layer (not shown). Generally, a photoresist material (not shown) is deposited over the masking layer. The photoresist material is irradiated (exposed) to energy, e.g. light, through a patterned reticle in order to induce a reaction in those portions of the photoresist material exposed to the energy. The photoresist material is developed to remove a portion of the photoresist material, wherein the remaining photoresist material protects the underlying material from subsequent processing steps, such as etching. As discussed in greater detail below, the fin  104  will be used to form a MuGFET. An example of the crystal orientation of a channel sidewall surface may be, for example, ( 110 ) and a channel top surface may be (001). The channel sidewall surface may be of other crystal orientations, such as (551). The channel sidewall and the channel top surface may have other crystal orientations. 
         [0018]    Isolation regions, such as Shallow Trench Isolations (STI)  106 , are formed along sidewalls of the fin  104  in the trenches  108 . Prior to forming the STIs  106 , one or more liners (collectively referred to as a liner  110 ) are formed over the substrate  102  and sidewalls of the fins  104 . In some embodiments, the liner  110  has a single layer structure with a thickness between about 10 Å and about 50 Å. In other embodiments, the liner  110  has a bilayer structure comprising a first liner sub-layer and a second liner sub-layer. In some embodiments, the first liner sub-layer comprises silicon oxide and has a thickness between about 5 Å and about 20 Å, and the second liner sub-layer comprises silicon nitride and has a thickness between about 5 Å and about 30  521  . The liner  110  may be deposited through one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process may be utilized. In some embodiments, the trenches  108  have a depth from a top of the fin  104  from about 500 Å to about 3000 Å. Other materials, dimensions, and/or processes may be used. 
         [0019]    The STIs  106  may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the STIs  106  are formed through a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the STIs  106  extending over the top surfaces of the fins  104 , and portions of the liner  110  over the top surfaces of the fins  104  are removed using, for example, an etch process, chemical mechanical polishing (CMP), or the like. 
         [0020]    In some embodiments, the STI  106  and the liner  110  are recessed to expose sidewalls of the fins  104  as illustrated in  FIGS. 1A-1C . In some embodiments, the STI  106  and the liner  110  are recessed using one or more selective etch processes utilizing the fins  104  as an etch mask. For example, the STI  106  and the liner  110  are recessed using a single etch processes. In alternative embodiments, the STI  106  and the liner  110  are recessed using a multiple etch processes. For example, the STI  106  is recessed using a first etch process utilizing the fins  104  and the liner  110  as an etch mask, and subsequently, the liner  110  is recessed using a second etch process. In embodiments in which the STI  106  comprise silicon oxide, the etch process may be, for example, a dry etch, a chemical etch, or a wet cleaning process. For example, the chemical etch may employ fluorine-containing chemical such as dilute hydrofluoric (dHF) acid. After the fin formation process, the fin height H fin  may be 30 nm or higher, such as 50 nm or higher. It is understood that the fin height may be modified by subsequent processing. Other materials, processes, and dimensions may be used. 
         [0021]      FIGS. 1A-1C  further illustrate a dummy gate dielectric  112  and a dummy gate electrode  114  formed over the exposed fin  104  in accordance with some embodiments. The dummy gate dielectric  112  and the dummy gate electrode  114  will be subsequently used to define and form the source/drain regions. In some embodiments, the dummy gate dielectric  112  and the dummy gate electrode  114  are formed by depositing and patterning a dummy gate dielectric layer (not shown) formed over the exposed fins  104  and a dummy gate electrode layer (not shown) over the dummy gate dielectric layer. The dummy gate dielectric layer may be formed by thermal oxidation, CVD, sputtering, or any other methods known and used in the art for forming a dummy gate dielectric layer. In some embodiments, the dummy gate dielectric layer may be formed of a same material as the STIs  106 . In other embodiments, the dummy gate dielectric  112  may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, SiCN, SiON, Si 3 N 4 , and SiN x H y , low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. In some embodiments, the dummy gate dielectric layer includes dielectric materials having a high dielectric constant (k value), for example, greater than 3.9. The materials may include metal oxides such as HfO 2 , HfZrO x , HfSiO x , HifiO x , HfAlO x , the like, or combinations and multi-layers thereof. 
         [0022]    Subsequently, the dummy gate electrode layer is formed over the dummy gate dielectric layer. In some embodiments, the dummy gate electrode layer is a conductive material and may be selected from a group comprising amorphous silicon, poly silicon, amorphous germanium, poly germanium, amorphous silicon-germanium, poly silicon-germanium, metallic nitrides, metallic silicides, metallic oxides, and metals. In an embodiment, the dummy gate electrode layer may be deposited by PVD, CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. Other materials, conductive and non-conductive, may be used. The top surface of the dummy gate electrode layer usually has a non-planar top surface and may be planarized after it is deposited. 
         [0023]    A hardmask, such as a dummy gate mask  117  formed, may be formed over the dummy gate electrode layer to aid in the patterning. The dummy gate mask  117  comprises one or more masking layers and will be used to pattern the dummy gate dielectric layer and the dummy gate electrode layer to form the dummy gate dielectric  112  and the dummy gate electrode  114  as illustrated in  FIGS. 1A-1C . The dummy gate mask  117  may comprise one or more patterning layers. In some embodiments, the dummy gate mask  117  may be formed of SiO 2 , SiCN, SiON, Si 3 N 4 , Al 2 O 3 , SiN x H y , or other suitable materials. 
         [0024]    In some embodiments, the dummy gate mask  117  comprises a first hardmask layer and a second hardmask layer. The first hardmask layer may be an oxide layer (e.g., silicon oxide) and the second hardmask layer may be a nitride (e.g., silicon nitride). The first hardmask layer and the second hardmask layer may be deposited through a process such as CVD, or a spin-on-glass process, although any acceptable process may be utilized. The first hardmask layer may have a thickness from about 10 Å to about 250 Å and the second hardmask layer may have a thickness from about 150 Å to about 850 Å. The dummy gate electrode  114  and the dummy gate dielectric  112  collectively form a dummy gate stack  116 . 
         [0025]    Sidewall spacers  118  are formed along sidewalls of the dummy gate stack  116  in accordance with some embodiments. The sidewall spacers  118  may be formed by depositing and patterning a spacer layer (not shown) over the dummy gate stack  116 , the fin  104 , and the STIs  106 . In some embodiments, spacer layer is formed of silicon nitride, and may have a single-layer structure. In alternative embodiments, the spacer layer may have a composite structure including a plurality of layers. For example, the spacer layer may include a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. Other materials, such as SiO 2 , SiCN, SiON, Si 3 N 4 , SiN x H y , SiOCN, other low k material, or combinations thereof, may also be used. 
         [0026]    The spacer layer may be patterned to form sidewall spacers  118  using, for example, an anisotropic etch process to remove the spacer layer over horizontal portions of the device and along sidewalls of the dummy gate stack  116 . Due to the difference in the thicknesses of the spacer layer over horizontal portions of the device and along sidewalls of the fin  104 , the spacer layer remains along sidewalls of the dummy gate stacks  116  while the fins  104  are exposed in the source/drain regions as illustrated in  FIGS. 1A-1C . 
         [0027]    It is noted that the figures illustrate three gate electrodes for illustrative purposes. The gate electrode in the middle may represent an active gate electrode while the gate electrodes on either side are dummy gate electrodes (e.g., non-active) used for patterning purposes in some embodiments. In other embodiments, all of the gate electrodes may be active gate electrodes. 
         [0028]      FIGS. 1A-1C  further illustrate a first source/drain region  120  and a second source/drain region  122  formed on exposed portions of the fins  104  along opposing sides of the dummy gate stack  116  in accordance with some embodiments. In some embodiments, the fins  104  may be recessed and the first source/drain region  120  and the second source/drain region  122  are epitaxially formed on the exposed portion of the recessed fin. The use of epitaxial grown materials in the source/drain regions allows for the source/drain regions to exert stress in the channel region  124 . The materials used for the first source/drain region  120  and the second source/drain region  122  may be varied for the n-type and p-type FinFETs, such that one type of material is used for the n-type FinFETs to exert a tensile stress in the channel region and another type of material for the p-type FinFETs to exert a compressive stress. For example, SiP or SiC may be used to form n-type FinFETs, and SiGe or Ge may be used to form p-type FinFETs. Other materials may be used. 
         [0029]    In embodiments in which different materials are utilized for the n-type devices and the p-type devices, it may be desirable to mask one (e.g., the n-type fins) while forming the epitaxial material on the other (e.g., the p-type fins), and repeating the process for the other. The first source/drain regions  120  and the second source/drain regions  122  may be doped either through an implanting process to implant appropriate dopants, or by in-situ doping as the material is grown. For example, for a p-channel MuGFET where the channel may be Si or Si 1-x Ge x , the doped epitaxial film may be boron-doped Si 1-y Ge y , where y is equal to or larger than x to induce longitudinal compressive strain in the channel for hole mobility enhancement. For an n-channel MuGFET where the channel may be Si, the doped epitaxial film may be, for example, phosphorus-doped silicon (Si:P) or silicon-carbon (Si 1-z C z :P). In the case where the channel is a compound semiconductor such as In m Ga 1-m As, the doped epitaxial film may be, for example, In n Ga 1-n As, where n is smaller than or equal to m. 
         [0030]    Referring now to  FIGS. 2A-2C , a liner dielectric film  230  is deposited on top of the first source/drain region  120 , the second source/drain region  122 , the sidewalls spacers  118 , and the dummy gate stack  116 . As will be described in greater detail below, a filler material will be formed over the liner dielectric film  230 , which will be subsequently patterned. The liner dielectric film  230  acts as an etch stop during the patterning of the filler material. In some embodiments, the liner dielectric film  230  comprises SiO 2 , SiCN, SiON, Si 3 N 4 , and SiN x H y , but other suitable dielectric materials may be used. The liner may further comprise a plurality of layers that comprises combinations of the above mentioned materials. The liner dielectric film  230  may be deposited through one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. 
         [0031]    In some embodiments, the liner dielectric film  230  has a thickness t 1  of 5 nm or less, such as 3 nm or less. Other thicknesses may be used. 
         [0032]      FIGS. 3A-3C  illustrate formation of a sacrificial inter-gate film  332  formed over the liner dielectric film  230  in accordance with some embodiments. In some embodiments, the sacrificial inter-gate film  332  comprises Si, Ge, SiGe, SiO 2 , SiCN, SiON, SiO x C y , SiO x H y , SiN x H y , or other suitable semiconductor or dielectric materials. In some embodiments, the sacrificial inter-gate film  332  is formed through a process such as CVD, FCVD, or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the liner dielectric film  230  and the sacrificial inter-gate film  332  extending over the top of the fins  104  are removed using, for example, an etch process, CMP, or the like. 
         [0033]    As noted above and explained in greater detail below, the sacrificial inter-gate film  332  will be subsequently removed from between the dummy gate stacks  116 , and during the removal process, the underlying liner dielectric film  230  acts as an etch stop and protects the underlying structures. As such, it may be desirable to select materials for the liner dielectric film  230  and the sacrificial inter-gate film  332  having a high etch selectivity such that the etch rate for the sacrificial inter-gate film  332  is greater than the etch rate for the liner dielectric film  230  for a selected etch process. 
         [0034]    Referring now to  FIGS. 4A-4C , the sacrificial inter-gate film  332  is recessed and an inter-gate mask  434  is formed in the recesses, in accordance with some embodiments. The inter-gate mask  434  prevents or reduces the loss of sacrificial inter-gate film  332  during the removal of dummy gate electrode  114  and dummy gate dielectric  112  in subsequent processes. In embodiments in which the dummy gate mask  117  comprises silicon nitride and the sacrificial inter-gate film  332  comprises silicon oxide, the sacrificial inter-gate film  332  may be recessed using an isotropic dry or wet etch process, such as wet etch using a dilute hydrofluoric acid. 
         [0035]    In some embodiments, the inter-gate mask  434  is formed of SiO 2 , SiCN, SiON, Si 3 N 4 , Al 2 O 3 , La 2 O 3 , SiN x H y , or the like using a CVD method, which may be Plasma Enhance CVD (PECVD), Molecular Layer Deposition (MLD), combinations thereof, or other applicable methods. A planarization process, such as a CMP process, may be performed to expose the dummy gate mask  117  (see  FIGS. 3A-3C ). In some embodiments, the planarization process may continue to remove the dummy gate mask  117  and to expose the dummy gate electrode  114  as illustrated in  FIGS. 4A-4C . 
         [0036]      FIGS. 5A-5C  illustrate removal of the dummy gate electrode  114  and the dummy gate dielectric  112  in accordance with some embodiments. With the inter-gate mask  434  protecting the sacrificial inter-gate film  332 , the dummy gate stack  116  is removed. The removal process may comprise one or more etch processes. For example in embodiments in which the inter-gate mask  434  comprises silicon nitride and the dummy gate electrode  114  comprises polysilicon and the dummy gate dielectric  112  comprises silicon oxide, the removal process may comprise selectively etching using either dry or wet etching. In the case dry etching is used, the process gas may include CF 4 , CHF 3 , NF 3 , SF 6 , Br 2 , HBr, Ck 2 , or combinations thereof. Diluting gases such as N 2 , O 2 , or Ar may optionally be used. In the case wet etching is used, the chemicals may include NH 4 OH:H 2 O 2 :H 2 O (APM), NH 2 OH, KOH, HNO 3 :NH 4 F:H 2 O, and/or the like. The dummy gate dielectric  112  may be removed using a wet etch process, such as a diluted HF acid, may be used. Other processes and materials may be used. 
         [0037]      FIGS. 6A-6C  illustrate formation of a gate dielectric layer  642  is formed over a channel region  124  of the fin  104  in accordance with some embodiments. In an embodiment, the gate dielectric layer  642  includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than 3.9). For example, the one or more gate dielectric layers may include one or more layers of a metal oxide or a silicate of Hf, Al, Zr, combinations thereof, and multi-layers thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloyed oxides, and combinations thereof. Exemplary materials include MgO x , BaTi x O y , BaSr x TiO z , PbTi x O y , PbZr x TiO z , SiCN, SiON, Si 3 N 4 , Al 2 O 3 , La 2 O 3 , Ta 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , HfSiON, YGe x O y , YSi x O y  and LaAlO 3 , and the like. The formation methods of gate dielectric layer  642  include molecular-beam deposition (MBD), ALD, PVD, and the like. In an embodiment, the gate dielectric layer  642  may have a thickness of about 3 Å to about 30 Å. 
         [0038]    In some embodiments, an interfacial layer (not shown) may be formed over the channel region  124  prior to forming the gate dielectric layer  642 , and the gate dielectric layer  642  is formed over the interfacial layer. The interfacial layer helps buffer the subsequently formed high-k dielectric layer from the underlying semiconductor material. In some embodiments, the interfacial layer is a chemical silicon oxide, which may be formed of chemical reactions. For example, a chemical oxide may be formed using deionized water+ozone (DIO 3 ), NH 4 OH+H 2 O 2 +H 2 O (APM), or other methods. Other embodiments may utilize a different material or processes for the interfacial layer. In an embodiment, the interfacial layer  640  may have a thickness of about 3 Å to about 7 Å. 
         [0039]      FIGS. 6A-6C  further illustrate a gate electrode  644  formed over the gate dielectric layer  642 . The gate electrode  644  may be a metal selected from a group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. In some embodiments, the gate electrode  644  comprises a metal selected from a group of TiN, WN, TaN, and Ru. Metal alloys such as Ti—Al, Ru—Ta, Ru—Zr, Pt—Ti, Co—Ni and Ni—Ta may be used and/or metal nitrides such as WN x , TiN x , MoN x , TaN x , and TaSi x N y  may be used. In some embodiments, the gate electrode  644  has a thickness in the range of about 5 nm to about 100 nm. The gate electrode  644  may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof. A planarization process, such as a CMP, may be performed to remove excess materials. 
         [0040]    Referring now to  FIGS. 7A-7C , there is illustrated the recessing of the gate electrode  644  and formation of a gate electrode mask  746  over remaining portions of the gate electrode  644  in accordance with some embodiments. In some embodiments in which the inter-gate mask  434  comprises silicon nitride, the gate electrode may be recessed using, for example, dry etch process using Cl 2 /O 2 /BCl 3 , at a temperature range of 24° C. to 150° C., and at an operation pressure of below 1 torr. 
         [0041]    After recessing the gate electrode  644 , the gate electrode mask  746  may be formed in the recess to protect the gate electrode  644  during subsequent processes. In some embodiments, the gate electrode mask  746  comprises SiO 2 , SiCN, SiON, Si 3 N 4 , Al 2 O 3 , La 2 O 3 , SiN x H y , a combination thereof, or the like, but other suitable dielectric film may be used. The gate electrode mask  746  may be formed using, for example, CVD, PVD, spin-on, or the like. Other suitable process steps may be used. 
         [0042]    A planarization process, such as a CMP, may be performed to remove excess materials. Furthermore, the planarization process may continue to remove the inter-gate mask  434  as illustrated in  FIGS. 7A-7C . 
         [0043]      FIGS. 8A-8C  illustrate removal of the sacrificial inter-gate film  332  in accordance with some embodiments. As discussed in greater detail below, the sacrificial inter-gate film  332  will be replaced with another material (e.g., the sacrificial film  950 ) having a higher etch rate selectivity to the materials of the other structures, such as the silicon oxide, silicon nitride, etc. of the gate electrode mask  746 , the liner dielectric film  230 , and the sidewall spacers  118 , allowing for a more controlled contact formation. 
         [0044]    In embodiments in which the sacrificial inter-gate film  332  is formed of silicon oxide and the gate electrode mask  746  is formed of silicon nitride, the sacrificial inter-gate film  332  may be removed using an isotropic dry or wet etch process. For example, a dry etch process using a process gas of C 4 F 6  or fluorine-based gas, or combinations thereof, and a carrier gas such as N 2 , O 2 , or Ar, may be used. In the case wet etching is used, the etchants may include dilute HF, and/or the like. As illustrated in  FIGS. 8A-8C , after removal of the sacrificial inter-gate film  332 , the liner dielectric film  230  is exposed. 
         [0045]      FIGS. 9A-9C  illustrate formation of a sacrificial film  950  in the recesses formed by the removal of the sacrificial inter-gate film  332  (see  FIGS. 8A-8C ) in accordance with some embodiments. In some embodiments the sacrificial film  950  comprises polysilicon, though other materials such as SiO 2 , SiCN, SiON, Si 3 N 4 , SiN x H y , Si, Ge, SiGe, SiGeC, GeSn or III-V materials, other suitable semiconductor or dielectric film, or the like may be used. In some embodiments, the deposition temperature of the sacrificial film  950  is kept below 600° C., such as below 500° C., or below 400° C., in order to reduce or minimize the thermal impact on the threshold voltage of the metal-gate/high-k dielectric stack previously formed. The sacrificial film  950  may also have good gap-fill capability. For example, in an embodiment, a width of the opening w c  is less than 20 nm, such as less than 10 nm, or such as less than 7 nm. 
         [0046]    For example, in some embodiments the sacrificial film  950  is Si, Ge, SiGe, SiGeC, formed by a CVD process. For example, the Si deposition process may use precursors such as silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ) or other higher-order silanes. The CVD process temperature is generally dependent on the precursor used. For growth using silane or disilane, the growth temperature may be about 300° C. or higher. For growth using higher-order silanes, temperatures lower than 300° C. may be used. For the other example of Ge growth, the precursor can be germane (GeH 4 ), digermane (Ge 2 H 6 ), trigermane (Ge 3 H 8 ), tetragermane (Ge 4 H 10 ), or other higher-order germanes. The growth temperature may be from about 250° C. to about 650° C. The range of operation pressure may be from 10 Torr to 760 Torr. 
         [0047]    As explained in greater detail below, portions of the sacrificial film  950  will be selectively removed, and as such, it may be desirable to select a material for the sacrificial film  950  that has a high etch rate selectivity compared to the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746 . For example, in embodiments in which the sacrificial film  950  is formed of polysilicon and the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746  are formed of silicon nitride or silicon oxide, an etching process may be used such that the sacrificial film  950  is etched at a much higher rate than the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746   
         [0048]      FIGS. 10A-10C  illustrate the resulting structure after patterning the sacrificial film  950  in accordance with some embodiments. As will be explained below the remaining material of the sacrificial film  950  will be replaced in subsequent steps with a conductive material to form contacts to the source drain regions. In some embodiments, photolithography techniques are utilized to pattern the sacrificial film  950 . Generally, a photoresist material (not shown) is deposited over the sacrificial film  950 . The photoresist material is irradiated (exposed) to energy and developed such that the portions of the photoresist over regions of the sacrificial film  950  at which contacts to the source/drain regions are desired remain. The protected portions of the sacrificial film  950  represent the locations of contacts to the source/drain regions. In some embodiments, a length of the contact l c  is below 40 nm, such as below 20 nm. As illustrated in  FIGS. 10A-10C , portions of the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746  may be removed during the etch process. 
         [0049]    The removal of the sacrificial film  950  may be done so that the etch rate of the sacrificial film is larger than the etch rate of exposed materials, e.g. liner, spacers, gate mask, and isolation dielectric film. Etch selectivities S l , S s , S gm , and S id  may be the ratios of the etch rate of the sacrificial film to that of liner dielectric film  230 , the sidewall spacers  118 , gate electrode mask  746 , and STI  106 , respectively. S l , S s , S gm , and S id  may each be higher than 3, and in some embodiments be higher than 10, such as higher than 20. During the etching of the sacrificial film  950 , the liner dielectric film  230  along a top of the source/drain may be removed as the sacrificial film below the source/drain top is being etched. In some embodiments S l  be at least approximately H fin /t l . In some embodiments, H fin  is 60 nm and t l  is 3 nm, and S l  may be at least 20. 
         [0050]    For example, in some embodiments the sacrificial film  950  is formed of polysilicon and the liner dielectric film  230 , sidewall spacers  118 , and the gate electrode mask  746  are formed of silicon nitride. In such an embodiment, a contact isolation etch process using dry etching may be used to avoid laterally overetching that may be exhibited by some wet etch behavior. The process gas may include HBr/N 2 /O 2 , or Cl 2 /SF 6  at a temperature of less than 200° C. (e.g., less than 100° C.), an RF power of less than 3 kW (e.g., less than 600 W), and at a pressure of less than 10 torr (e.g., less than 3 torr). 
         [0051]    As another example, in some embodiments the sacrificial film  950  is formed of SiOC formed by spin-on coating, and the liner dielectric film  230 , sidewall spacers  118 , and the gate electrode mask  746  are formed of silicon nitride. In these embodiments, an anisotropic etch process may be used to remove this sacrificial film  950  in the contact isolation regions. The process gas may include N 2  and H 2 , or SO 2  and O 2 , at a temperature of less than 200° C. (e.g., 20-100° C.), an RF power of greater than 100 W (e.g., greater than 300 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). 
         [0052]    As yet another example, in some embodiments the sacrificial film  950  is formed of silicon oxide formed by flowable CVD, and the liner dielectric film  230 , sidewall spacers  118 , and the gate electrode mask  746  are formed of silicon nitride. The removal of the sacrificial film  950  may be performed using a plasma etch process the process gas may include C 4 F 6  or a fluorine-based gas, at a temperature of less than 200° C. (e.g., less than 150° C.), an RF power of greater than 50 W (e.g., greater than 100 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). 
         [0053]    As yet another example, in some embodiments the sacrificial film  950  is formed of germanium, and the liner dielectric film  230 , sidewall spacers  118 , and the gate electrode mask  746  are formed of silicon nitride. In these embodiments, a plasma etch process may be used to remove  950  by anisotropic etch. The process gas may include CF 4  chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like, or HBr, Cl 2  or other halogen gases, at a temperature of less than 200° C. (e.g., less than 60° C.), an RF power of greater than 2,000 kW (e.g., from about 50 W to about 300 W), and at a pressure of less than 10 torr (e.g., less than 500 mtorr). 
         [0054]    Referring now to  FIGS. 11A-11C , an interlayer dielectric (ILD)  1150  is formed in accordance with an embodiment. The ILD  1150  may comprise a single layer or multiple layers. For example, in some embodiments an ILD liner  1152  is deposited on top of the first source/drain region  120 , the second source/drain region  122 , the sidewalls spacers  118 , and the dummy gate stack  116 , and an ILD filler material  1154  is deposited over the ILD liner  1152 . (The ILD liner  1152  and the ILD filler material  1154  are collectively referred to as the ILD  1150 .) In some embodiments, the ILD liner  1152  comprises SiO 2 , SiCN, SiON, Si 3 N 4 , and SiN x H y , but other suitable dielectric materials may be used. The ILD liner  1152  may further comprise a plurality of layers that comprise combinations of the above mentioned materials. The ILD liner  1152  may be deposited through one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. 
         [0055]    In some embodiments, the ILD filler material  1154  comprises SiO 2 , SiCN, SiOC, SiON, Si 3 N 4 , and SiN x H y , but other suitable dielectric film may be used. The isolation dielectric may be cured or treated after deposition. For example, the curing may involve irradiation with ultra-violet radiation, and the treatment may involve annealing in N 2 , O 2 , or H 2 O ambient at temperatures ranging above 200° C. After the curing or treatment, the isolation dielectric may have a relative permittivity of less than 6, such as less than 5, and such as less than 4. For example, the isolation dielectric may be SiO 2  formed by CVD, PECVD or ALD deposition process, FCVD, or a spin-on-glass process. A planarization process, such as a CMP process, may be performed to remove excess materials and to expose the sacrificial film  950 . 
         [0056]      FIGS. 12A-12C  illustrate the removal of the sacrificial film  950  (see  FIGS. 11A-11C ) in accordance with some embodiments. As discussed in greater detail below, the sacrificial film  950  is replaced with a conductive material which will form the contacts to the source/drain regions. In some embodiments, the sacrificial film  950  may be removed using a selective etch process. As such, it may be desirable to select materials for the sacrificial film  950 , the ILD  1150 , the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746  such that a high etch rate selectivity exists between the material of the sacrificial film  950  and the materials of the ILD  1150 , the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746 . 
         [0057]    For example, in some embodiments the sacrificial film  950  is formed of polysilicon and the ILD liner  1152 , the ILD filler material  1154 , the liner dielectric film  230 , the sidewall spacers  118 , and the gate electrode mask  746  is formed of silicon nitride and/or silicon oxide. In these embodiments, a ratio of an etch rate of the polysilicon to an etch rate of the silicon nitride and the silicon oxide may be about 30 to about 50 using an isotropic etch process. In the case plasma etching is used, the process gas may include Cl 2 /NF 3 /He or SF6 or NF3 or CF4 or other suitable halogens based etch gas at a temperature of less than 200° C. (e.g., less than 100° C.), an RF power of less than 3 kW (e.g., less than 600 W), and at a pressure of less than 10 torr (e.g., less than 3 torr). In some embodiments, the wet etch process is used to remove the sacrificial film  950 . The etch material of wet etch process can be NH 4 OH or TMAH or other material can remove Si film. As another example, a dry chemical etch process may be performed using fluorine-based gas/NH 3  at a temperature of less than 200° C. (e.g., less than 100° C.). 
         [0058]    As another example, in some embodiments the sacrificial film  950  is formed of SiOC formed by spin-on coating, the ILD filler material  1154  is SiO 2  formed by flowable CVD, the ILD liner  1152  may be an ALD silicon nitride, and the gate electrode mask  746  may be silicon nitride. In these embodiments, a ratio of an etch rate of the SiOC to an etch rate of the silicon nitride and the silicon oxide may be greater than 50 using a plasma etch process wherein the process gas may include N 2  and H 2 , or SO 2  and O 2 , at a temperature of less than 200° C. (e.g., 20-100° C.), an RF power of greater than 100 W (e.g., greater than 300 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). 
         [0059]    As yet another example, in some embodiments the sacrificial film  950  is formed of silicon oxide formed by flowable CVD, the ILD filler material  1154  is SiO 2  formed by flowable CVD , the ILD liner  1152  may be an silicon nitride, and the gate electrode mask  746  may be silicon nitride. The removal of the sacrificial film  950  may be performed using a plasma etch process the process gas may include C 4 F 6  or a fluorine-based gas, at a temperature of less than 200° C. (e.g., less than 150° C.), an RF power of greater than 50 W (e.g., greater than 100 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). 
         [0060]    As yet another example, in some embodiments the sacrificial film  950  is formed of germanium, the ILD filler material  1154  is SiO 2 , the ILD liner  1152  may be an ALD silicon nitride, and the gate electrode mask  746  may be silicon nitride. In these embodiments, a ratio of an etch rate of the germanium to an etch rate of the silicon nitride and the silicon oxide may be greater than 15 using a plasma etch process wherein the process gas may include CF 4  chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like, or HBr, Cl 2  or other halogen gases, at a temperature of less than 200° C. (e.g., less than 60° C.), an RF power of greater than 2,000 kW (e.g., from about 50 W to about 300 W), and at a pressure of less than 10 torr (e.g., less than 500 mtorr). 
         [0061]    After removing the sacrificial film  950 , exposed portions of the liner dielectric film  230  may be removed to expose the underlying first source/drain region  120  and the second source/drain region  122 . In embodiments in which the liner dielectric film  230  is formed of silicon nitride, the ILD liner  1152  is formed of silicon nitride and the ILD filler material  1154  is formed of silicon oxide, the liner dielectric film  230  may be removed using a dry etch process with a fluorine-based etching gas. Due to the difference in materials, the liner dielectric film  230  may be removed without removing or limiting the removal of the ILD liner  1152  and the ILD filler material  1154 . 
         [0062]    As illustrated above, the use of the sacrificial film  950 , and the selection of a material capable of being selectively etched with a high-etch rate selectivity as compared to other materials, contact openings may be formed using a self-aligned process. As such, embodiments such as those disclosed herein allow formation of smaller contact areas as devices are scaled down further to meet market demands with less risk of mis-alignment, which may cause shorting and device failure issues. Additionally, the full space between the sidewall spacers can be used thereby allowing for larger contact areas, which may lower contact resistance and provide increased device performance. 
         [0063]    Referring now to  FIGS. 13A-13D , there is shown formation of contacts  1358  in accordance with some embodiments, wherein  FIG. 13  D illustrates an enlarged view of a portion of  FIG. 13B . The contacts  1358  may comprise a single layer or a multi-layer structure. For example, in some embodiments the contacts  1358  comprise a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a contact filler formed over the contact liner in the openings. The contact liner may include Ti, TiN, Ta, TaN, or the like formed by ALD, CVD, or the like. The contact filler may be formed by depositing a conductive material, such as one or more layers of Ni, Ta, TaN, W, Co, Ti, TiN, Al, Cu, Au, alloys thereof, combinations thereof, or the like, but other suitable metal may be used. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the ILD filler material  1154 . 
         [0064]    As illustrated in  FIG. 13D , the contacts  1358  may exhibit a tapered contact sidewall profile and the angle between the top contact plane and contact sidewall is larger than 90°. As illustrated in  FIG. 13D , a width of the contacts  1358  along a top of the contacts  1358  C w1  is less than a width of the contacts  1358  along a bottom of the contacts  1358  C w2 . 
         [0065]      FIGS. 14A-15B  illustrate different etch profiles that may be obtained in a contact isolation region during removal of the sacrificial film  950  in accordance with some embodiments. The process illustrated in  FIGS. 14A-15B  assume processes discussed above with reference to  FIGS. 1A-10C  are performed prior, and processes discussed above with reference to  FIGS. 11A-13  are performed after the processes discussed below with reference to  FIGS. 14A-15B . Accordingly, after performing processes discussed above with reference to  FIGS. 1A-10C , an additional etch process may be performed to laterally widen an upper portion of the opening above the contact isolation region while portions of the sacrificial film  950  over the source/drain regions are protected as discussed above with reference to  FIGS. 10A-10C . As illustrated in  FIG. 14A-14B , the second etch may laterally remove upper portions of the sidewall spacers  118  and portions of the remaining gate electrode mask  746 , thereby creating a funnel-shaped opening profile. The funnel-shaped opening profile allows part of the sidewall spacers  118  and the gate electrode mask  746  to be replaced with a lower dielectric constant material, thereby reducing the fringing capacitance between the gate electrode  644  and the contact  1358  and improving device performance. 
         [0066]    In some embodiments in which the sidewall spacers  118  and the gate electrode mask  746  are formed of silicon nitride, a lateral dry etch plasma process using a process gas of CF 4  chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like), at a temperature of less than 250° C. (e.g., less than 150° C.), an RF power of greater than 3 kW (e.g., less than 2 kW), and at a pressure of less than 5 torr (e.g., less than 2.5 torr) may be performed. In some embodiments, the height (H A ) and width (W A ) are greater than 4 nm and greater than 2 nm, respectively. 
         [0067]    Thereafter, processes such as those discussed above with reference to  FIGS. 11A-11C  may be performed to fill the funnel-shaped opening with the ILD material (e.g., the ILD liner  1152  and the ILD filler material  1154 ), thereby resulting in the structure illustrated in  FIGS. 15A-15B . Processes such as those discussed above with reference to  FIGS. 11A-13D  may be performed to complete formation of the contacts. 
         [0068]      FIGS. 16A-17B  illustrate different etch profiles that may be obtained in the contact regions during removal of the sacrificial film  950  in the contact regions in accordance with some embodiments. As discussed above,  FIGS. 14A-15B  illustrate different profiles that may be obtained for the openings in which the ILD  1150  is formed.  FIGS. 16A-17B  illustrates that similar etch profiles may be used for forming the openings in which the contacts  1358  will be formed. 
         [0069]    The processes illustrated in  FIGS. 16A-17B  assume processes discussed above with reference to  FIGS. 1A-1C  through the process of removing the sacrificial film  950  as discussed in reference to  FIGS. 12A-12C , are performed prior to the processes illustrated in  FIGS. 16A-17B , wherein an additional etch process may be performed to laterally widen an upper portion of the opening above the contact region of the source/drain regions. As illustrated in  FIG. 16A-16B , the second etch may laterally remove upper portions of sidewall spacers  118  and portions of the gate electrode mask  746 , thereby creating a funnel-shaped opening profile as shown in  FIGS. 16A-16B . The ILD liner  1152  may be removed from over the source/drain regions as discussed above with reference to  FIGS. 12-12C . 
         [0070]    In some embodiments in which the ILD liner  1152  and the gate electrode mask  746  are formed of silicon nitride, a lateral dry etch plasma process using a process gas of CF 4  chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like), at a temperature of less than 250° C. (e.g., less than 150° C.), an RF power of greater than 3 kW (e.g., less than 2 kW), and at a pressure of less than 5 torr (e.g., less than 2.5 torr) may be used. In some embodiments, the height (H B ) and width (W B ) may be less than 7 nm and less than 3 nm, respectively. In some embodiments, H B  and W B  may be greater than H A  and W A  respectively. The funnel-shaped opening may then be filled with a conductive material as discussed above with reference to  FIGS. 13A-13D , thereby resulting in a contact as illustrated in  FIGS. 17A-17B . 
         [0071]    Other processes may be performed. For example, in some embodiments a metal silicide may be formed over the first source/drain regions  930  and the second source/drain regions  932 . In some embodiments a metal silicide formation process is performed after the inter-gate film film removal process discussed above with reference to  FIGS. 8A-8C , or after the contact hole formation discussed above with reference to  FIGS. 12A-12C . The metal silicide formation process may form a metal silicide on top of the doped source/drain region to reduce R c  between the doped source/drain regions and the contact metal formed thereafter. The metal silicide formation process includes a metal film deposition on top of the source/drain region, a thermal treatment to form a metal silicide at the interface between the source/drain region and an etching process to remove the excess unreacted metal. The metal silicide comprises TiSi x , NiSi x , CoSi x , NiCoSi x , and TaSi x , but other suitable silicide materials may be used. In some embodiments, the silicide formation may be performed ILD removal. 
         [0072]    It is noted that other embodiments may utilize various other steps or ordering of the steps. For example,  FIGS. 18-28  illustrate various cross-sectional views and perspective views of intermediate stages in the manufacturing of a FinFET in accordance with some embodiments. In  FIGS. 18A-28C , the “A” figures (e.g.,  FIGS. 18A, 19A , etc.) illustrate a perspective view, the “B” figures (e.g.,  FIGS. 18B, 19B , etc.) illustrate a cross-sectional view along the Y-cut line illustrated in the respective “A” figure, and the “C” figures (e.g.,  FIGS. 18C, 19C , etc.) illustrate a cross-sectional view along the X-cut line illustrated in the respective “A” figure. 
         [0073]    As discussed above with reference to  FIGS. 1-15 , a sacrificial inter-gate film film  332  was temporarily deposited as illustrated in  FIGS. 3A-3C , and then removed as illustrated in  FIGS. 8A-8C  and replaced with a sacrificial film  950  as illustrated in  FIGS. 9A-9C . In the embodiments illustrated in  FIGS. 18-28 , the sacrificial inter-gate  332  is omitted. Rather, as discussed in greater detail below, the sacrificial film  950  is formed earlier in the process. Greater detail of the process is discussed in the following paragraphs with reference to  FIGS. 18-28 , wherein like reference numerals refer to like elements. 
         [0074]    Referring first to  FIGS. 18A-19C , processes and materials similar to those discussed above with reference to  FIGS. 1A-2C  are illustrated, wherein like reference numerals refer to like elements, and will not be repeated. 
         [0075]    Referring now to  FIGS. 20A-20C , the sacrificial film  950  is formed, using for example, materials and processes similar to those discussed above with reference to  FIGS. 9A-9C . 
         [0076]      FIGS. 21A-21C  illustrates a recessing of the sacrificial film  950  in accordance with some embodiments. As discussed in greater detail below, the sacrificial film  950  is recessed and a mask is formed over the recessed sacrificial film  950  to protect the sacrificial film  950  during subsequent processing. In some embodiments, the sacrificial film  950  is recessed from 100 Å to about 600 Å in order to provide a sufficient thickness for the subsequently formed mask layer. 
         [0077]    In embodiments in which the sacrificial film  950  is formed of polysilicon and the dummy gate mask  116 , the liner dielectric film  230  and the sidewall spacers  118  are formed of silicon nitride/silicon oxide, the sacrificial film  950  may be recessed using a timed etch, using for example plasma etching with a process gas may of NF 3 , HBr/N 2 /O 2 , or Cl 2 /NF 3 /He, at a temperature of less than 200° C. (e.g., less than 100° C.), an RF power of less than 3 kW (e.g., less than 600 W), and at a pressure of less than 10 torr (e.g., less than 3 torr). 
         [0078]    As another example, in some embodiments the sacrificial film  950  is formed of SiOC formed by spin-on coating, and the dummy gate mask  116 , the liner dielectric film  230  and the sidewall spacers  118  are formed of silicon nitride/silicon oxide, the sacrificial film  950  may be recessed using a timed etch, using for example plasma etching with a process gas including N 2  and H 2 , or SO 2  and O 2 , at a temperature of less than 200° C. (e.g., 20-100° C.), an RF power of greater than 100 W (e.g., greater than 300 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). 
         [0079]    As yet another example, in some embodiments the sacrificial film  950  is formed of silicon oxide formed by flowable CVD, and the dummy gate mask  116 , the liner dielectric film  230  and the sidewall spacers  118  are formed of silicon nitride, the sacrificial film  950  may be recessed using a timed etch, using for example a plasma etch process with a process gas including C 4 F 6  or a fluorine-based gas, at a temperature of less than 200° C. (e.g., less than 150° C.), an RF power of greater than 50 W (e.g., greater than 100 W), and at a pressure of less than 3 torr (e.g., less than 200 mtorr). 
         [0080]    As yet another example, in some embodiments the sacrificial film  950  is formed of germanium , and the dummy gate mask  116 , the liner dielectric film  230  and the sidewall spacers  118  are formed of silicon nitride/silicon oxide, the sacrificial film  950  may be recessed using a timed etch, using for example a plasma etch process with a process gas including CF4 chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like, or HBr, Cl 2  or other halogen gases, at a temperature of less than 200° C. (e.g., less than 60° C.), an RF power of greater than 2,000 kW (e.g., from about 50 W to about 300 W), and at a pressure of less than 10 torr (e.g., less than 500 mtorr). 
         [0081]    A planarization process, such as a CMP process, may be performed to expose the dummy gate mask  117  (see  FIGS. 19A-19C ). In some embodiments, the planarization process may continue to remove the dummy gate mask  117  and to expose the dummy gate electrode  114  as illustrated in  FIGS. 21A-21C . 
         [0082]    Thereafter, processing similar to that discussed above with reference to  FIGS. 5A-7C  may be performed as illustrated in  FIGS. 22A-24C , respectively. Similar processes and materials may be used as described above and will not be repeated. 
         [0083]    Referring now to  FIGS. 25A-25C , the sacrificial film  950  is patterned in accordance with some embodiments. The sacrificial film  950  may be patterned as discussed above with reference to  FIGS. 10A-10C  and will not be repeated. It is noted that in embodiments such as these, the processes discussed above with reference to  FIGS. 3 and 8  (forming and then removing the sacrificial inter-gate film  332  to form the sacrificial film  950 ) may be omitted. 
         [0084]    Thereafter, processes illustrated in  FIGS. 26A-28D  may be performed. The processes may be similar to those discussed above with reference to  FIGS. 11A-13D , respectively, and will not be repeated. 
         [0085]    Processes discussed above with reference to  FIGS. 14A-15B  to form a funnel-shaped opening in the contact isolation region and/or with reference to  FIGS. 16A-17B  to form a funnel-shaped opening in the contact region may be incorporated into the process discussed above with reference to  FIGS. 18A-28C . For example, after performing processes discussed above with reference to  FIGS. 18A-25C , the processes discussed above with reference to  FIGS. 14A-15B  may be performed. Accordingly, after performing processes discussed above with reference to  FIGS. 18A-25C , an additional etch process may be performed to laterally widen an upper portion of the opening above the contact isolation region while portions of the sacrificial film  950  over the source/drain regions are protected as discussed above with reference to  FIGS. 25A-25C . As illustrated in  FIG. 14A-14B , the second etch may laterally remove upper portions of the sidewall spacers  118  and portions of the remaining gate electrode mask  746 , thereby creating a funnel-shaped opening profile. The funnel-shaped opening profile allows part of the sidewall spacers  118  and the gate electrode mask  746  to be replaced with a lower dielectric constant material, thereby reducing the fringing capacitance between the gate electrode  644  and the contact  1358  and improving device performance. 
         [0086]    In some embodiments in which the sidewall spacers  118  and the gate electrode mask  746  are formed of silicon nitride, a lateral dry etch plasma process using a process gas of CF 4  chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like), at a temperature of less than 250° C. (e.g., less than 150° C.), an RF power of greater than 3 kW (e.g., less than 2 kW), and at a pressure of less than 5 torr (e.g., less than 2.5 torr) may be performed. In some embodiments, the height (H A ) and width (W A ) are greater than 4 nm and greater than 2 nm, respectively. 
         [0087]    Thereafter, processes such as those discussed above with reference to  FIGS. 26A-26C  may be performed to fill the funnel-shaped opening with the ILD material (e.g., the ILD liner  1152  and the ILD filler material  1154 ), thereby resulting in the structure illustrated in  FIGS. 15A-15B . Processes such as those discussed above with reference to  FIGS. 26A-28D  may be performed to complete formation of the contacts. 
         [0088]    The processes discussed above with reference to  FIGS. 16A-17B  may also be incorporated into the process discussed above with reference to  FIGS. 18A-28C  to form a funnel-shaped contact. For example, after performing processes discussed above with reference to  FIGS. 18A-27C , but prior to removing the liner dielectric film  230 , an additional etch process may be performed to laterally widen an upper portion of the opening above the contact region of the source/drain regions. As illustrated in  FIG. 16A-16B , the second etch may laterally remove upper portions of sidewall spacers  118  and portions of the gate electrode mask  746 , thereby creating a funnel-shaped opening profile as shown in  FIGS. 16A-16B . The ILD liner  1152  may be removed from over the source/drain regions as discussed above with reference to  FIGS. 27A-27C . 
         [0089]    In some embodiments in which the ILD liner  1152  and the gate electrode mask  746  are formed of silicon nitride, a lateral dry etch plasma process using a process gas of CF 4  chemistry (e.g., CF 2 Cl 2 , CF 3 Br, or the like), at a temperature of less than 250° C. (e.g., less than 150° C.), an RF power of greater than 3 kW (e.g., less than 2 kW), and at a pressure of less than 5 torr (e.g., less than 2.5 torr) may be used. In some embodiments, the height (H B ) and width (W B ) may be less than 7 nm and less than 3 nm, respectively. In some embodiments, H B  and W B  may be greater than H A  and W A  respectively. The funnel-shaped opening may then be filled with a conductive material as discussed above with reference to  FIGS. 28A-28D , thereby resulting in a contact as illustrated in  FIGS. 17A-17B . 
         [0090]    Other processes may be performed. For example, in some embodiments a metal silicide may be formed over the first source/drain regions  930  and the second source/drain regions  932 . In some embodiments a metal silicide formation process is performed after the inter-gate film removal process discussed above with reference to  FIGS. 8A-8C , or after the contact hole formation discussed above with reference to  FIGS. 12A-12C . The metal silicide formation process may form a metal silicide on top of the doped source/drain region to reduce R c  between the doped source/drain regions and the contact metal formed thereafter. The metal silicide formation process includes a metal film deposition on top of the source/drain region, a thermal treatment to form a metal silicide at the interface between the source/drain region and an etching process to remove the excess unreacted metal. The metal silicide comprises TiSi x , NiSi x , CoSi x , NiCoSi x , and TaSi x , but other suitable silicide materials may be used. In some embodiments, the silicide formation may be performed ILD removal. 
         [0091]    In an embodiment, a method of forming a semiconductor device is provided. The method includes forming a sacrificial film over a source/drain region of a fin and an isolation region adjacent the fin, removing a first portion of the sacrificial film over the isolation region to form a first recess, a second portion of the sacrificial film over the source/drain region remaining, and forming a dielectric layer in the first recess. The method further includes removing the second portion of the sacrificial film to form a second recess and forming a conductive layer in the second recess. 
         [0092]    In another embodiment, a method of forming a semiconductor device is provided. The method includes forming a first gate electrode and a second gate electrode over a semiconductor structure, forming a first sacrificial film between the first gate electrode and the second gate electrode, and patterning the first sacrificial film such that a remaining portion of the first sacrificial film remains over the semiconductor structure and such that first recesses are formed between the first gate electrode and the second gate electrode on opposing sides of the remaining portion of the first sacrificial film. The method further includes forming an interlayer dielectric (ILD) in the first recesses, removing the remaining portion of the first sacrificial film to form a second recess, and forming a conductive feature in the second recess. 
         [0093]    In another embodiment, a semiconductor device is provided. The semiconductor device includes a gate electrode over a semiconductor structure, the semiconductor structure having a first source/drain region, a second source/drain region, and a channel region interposed between the first source/drain region and the second source/drain region, the gate electrode being over the channel region, a gate mask over the gate electrode, and a sidewall spacer along a sidewall of the gate electrode and the gate mask, wherein an upper surface of the sidewall spacer is recessed from an upper surface of the gate mask. The semiconductor device further includes a contact adjacent the sidewall spacer, the contact electrically coupled to the first source/drain region, wherein the contact contacts a sidewall of an upper portion of the gate mask. 
         [0094]    The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.