Abstract:
A chip which utilizes a silicon controlled rectifier (SCR) for ESD protection prevents a latchup condition from occurring when the SCR misfires and turns on during normal operation by utilizing a fuse in series with the SCR. The fuse allows the SCR to perform normally during an ESD event, but blows if the SCR misfires and attempts to pull a pin voltage down to the holding voltage.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to silicon controller rectifiers (SCRs) and, more particularly, to an SCR with a fuse that prevents latchup. 
   2. Description of the Related Art 
   A silicon controlled rectifier (SCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a trigger voltage. However, when the voltage across the first and second nodes rises to be equal to or greater than the trigger voltage, the SCR snaps back. 
   When the SCR snaps back, the SCR allows a large current to flow between the first and second nodes at a much lower voltage as long as a minimum current or a minimum voltage, known as a holding current or a holding voltage, is maintained. If the current flowing between the first and second nodes falls below the holding current, or the voltage across the first and second nodes falls below the holding voltage, the SCR again provides an open circuit between the first and second nodes. 
   As a result of these characteristics, SCRs are used with electronic circuits to protect the electronic circuits from an electro-static discharge (ESD) pulse when an ESD pulse is unintentionally applied to the pins of a chip that houses the electronic circuits. An ESD pulse can be unintentionally generated when a chip is handled prior to being attached to a printed circuit board. 
   When an ESD pulse is generated, a very high potential is momentarily placed on a pin while the chip is otherwise powered off. If another pin is grounded, a very large current can flow from the high potential pin through circuitry in the chip to the grounded pin. If the pins are not ESD protected, the current can destroy the circuitry in the chip. 
     FIG. 1  shows a schematic diagram that illustrates a portion of a conventional chip  100 . As shown in  FIG. 1 , chip  100  includes a first pin  110  and a second pin  112 . In addition, chip  100  includes an electronic circuit  114  and an SCR  116  that are both connected to first pin  110  and second pin  112 . 
   Thus, during normal operation, SCR  116  provides an open circuit between first pin  110  and second pin  112 . However, when first pin  110  receives a voltage spike that equals or exceeds the trigger voltage of SCR  116 , such as when an ungrounded human-body contact occurs, SCR  116  provides a low-resistance current path from first pin  110  to second pin  112 , thereby protecting electric circuit  114  from damage. 
   An SCR ideally operates within an ESD protection window that has a maximum voltage that is defined by the destructive breakdown level of the devices that are electrically connected to a pin, and a minimum voltage that is defined by any DC bias voltage that is present on the pin during normal operation. The trigger voltage of the SCR is then set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window. 
   It is often difficult to fabricate an SCR that has a holding voltage which is greater than the DC bias voltage that is placed on the pin during normal operation. As a result, many SCRs are fabricated with a holding voltage that is less than the DC bias voltage. However, when the holding voltage is less than the DC bias voltage, the chip is subject to a condition known as latchup. 
   Latchup occurs when the SCR misfires and turns on during normal operation. When the holding voltage is less than the DC bias voltage, and the SCR turns on and remains turned on during normal operation, the SCR pulls the voltage on the pin down to the holding voltage which, in turn, effectively disables the entire operation of the circuitry with the chip. 
   For example, if an SCR has a holding voltage of 1.0V and the chip places a DC bias voltage of 1.8V on a pin during normal operation, then the SCR pulls the voltage on the pin down to 1.0V when the SCR misfires and turns on during normal operation. In addition, since the DC bias voltage of 1.8V is greater than the holding voltage of 1.0V, the DC bias voltage ensures that once the SCR misfires and turns on, the SCR remains turned on until power is removed from the chip. Thus, unless the circuitry on the chip can operate with 1.0V, the circuitry is disabled. 
   In addition, if the SCR sinks a large current while latched up, the large current can lead to excessive heating that can burn out the circuitry on the chip. As a result, there is a need for an approach that prevents an SCR from latching up when the SCR, which has a holding voltage less than the DC bias voltage, misfires and turns on during normal operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram illustrating a portion of a conventional chip  100 . 
       FIG. 2  is a schematic diagram illustrating an example of a portion of a chip  200  in accordance with the present invention. 
       FIG. 3  is a plan view illustrating an example of a portion of an interconnect structure  300  in accordance with the present invention. 
       FIG. 4  is a plan view illustrating an example of a portion of an interconnect structure  400  in accordance with the present invention. 
       FIG. 5  is a plan view illustrating an example of a portion of an interconnect structure  500  in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  shows a schematic diagram that illustrates an example of a portion of a chip  200  in accordance with the present invention. As described in greater detail below, the chip of the present invention utilizes a fuse in series with an SCR to prevent latchup from occurring when the SCR misfires and turns on during normal operation. 
   As shown in the  FIG. 2  example, chip  200  includes a first pin  210 , a second pin  212 , and an electronic circuit  214  that is connected to both first pin  210  and second pin  212 . In addition, chip  200  includes a silicon controller rectifier (SCR)  216  that lies between first pin  210  and second pin  212 . 
   In accordance with the present invention, chip  200  also includes a fuse  220  that is connected in series with SCR  216  between first pin  210  and second pin  212  so that a voltage applied across the first and second pins  210  and  212  is applied across SCR  216  and fuse  220 . For example, if 1.8V is applied to first pin  210  and ground is applied to second pin  212 , then 1.8V is also applied across SCR  216  and fuse  220 . In addition, although fuse  220  is shown connected to first pin  210  and SCR  216 , with SCR  216  connected to second pin  212 , SCR  216  can alternately be connected to first pin  210  and fuse  220 , with fuse  220  connected to second pin  212 . 
   During normal operation, SCR  216  provides an open circuit between first pin  210  and second pin  212 . However, when first pin  210  receives a voltage spike that equals or exceeds the trigger voltage of SCR  216 , SCR  216  and fuse  220  provide a low-resistance current path from first pin  210  to second pin  212 , thereby protecting electronic circuit  214  from damage. 
   In accordance with the present invention, if SCR  216  misfires and turns on during normal operation, a misfire current flows from first pin  210  to second pin  212  through SCR  216  and fuse  220 . The misfire current flowing through fuse  220 , however, heats up and blows fuse  220 . When fuse  220  is blown, the blown fuse forms an open circuit that prevents the misfire current from continuing to flow through SCR  216 . As a result, fuse  220  prevents SCR  216  from pulling the voltage on first pin  210  down to the holding voltage, and from a thermal overrun which can destroy chip  200 . 
   Fuse  220  satisfies the 2500V human body model (HBM) and the 250V machine model (MM), while also burning out and blowing in response to the misfire current because an ESD pulse is short when compared to the time required to blow fuse  220 . In other words, fuse  220  does not blow in response to a 4A ESD pulse, but does blow in response to a 50 mA misfire current, because the 4A ESD pulse is present for a much shorter time than the 50 mA misfire current is present. 
   In addition, the misfire current takes a relatively short period of time to blow fuse  220  such that the devices in electronic circuit  214  that receive the DC bias voltage from pin  210  only experience a momentary glitch in the power. This momentary glitch, in turn, is insufficient to alter the normal operation of the devices in electronic circuit  214  connected to first pin  210 . 
   Fuse  220  can be implemented in a number of different ways. For example, fuse  220  can be formed as a conductive line that has a necked down section.  FIG. 3  shows a plan view that illustrates an example of a portion of an interconnect structure  300  in accordance with the present invention. 
   As shown in  FIG. 3 , interconnect structure  300  includes a region of isolation material  310 , a first conductive section  312 , a second conductive section  314 , and a third conductive section  316  that lies between and contacts the first and second conductive sections  312  and  314 . The first, second, and third conductive sections  312 ,  314 , and  316  contact and lie on isolation region  310 . 
   In addition, first conductive section  312  has a first width W 1 , second conductive section  314  has a second width W 2  that is substantially equal to the first width W 1 , and third conductive section  316  has a third width W 3  that is less than the first and second widths W 1  and W 2 . The first, second, and third widths W 1 , W 2 , and W 3  are measured parallel to each other. 
   The width W 3  of third conductive section  316  can be formed to be, for example, 5 μM to 10 μM, depending on the magnitude of the misfire current and the maximum glitch in the DC bias voltage that can be tolerated by the devices in electronic circuit  214 . Third conductive section  316  has the same thickness as the first and second conductive sections  312  and  314 , and can have a number of different lengths L, such as 20 μM, since the width W 3  of third conductive section  316  defines the time required to vaporize a portion of third conductive region  316  and form an open circuit. For example, a third conductive section  316  which is 5 μM wide can vaporize a portion of third conductive section  316  to form an open circuit in response to a 50 mA misfire current in a very short period of time. 
   In the  FIG. 3  example, third conductive section  316  can be a necked down portion of a metal trace or a polysilicon strip. Examples of polysilicon-based fuse structures are described in U.S. Pat. No. 6,166,421 to Kalnitsky et al., issued on Dec. 26, 2000, and U.S. patent application Ser. No. 11/312,215, filed on Dec. 19, 2005, which are hereby incorporated by reference. 
   As further shown in  FIG. 3 , interconnect structure  300  includes a fourth conductive section  320  that lies on isolation region  310 , and a fifth conductive section  322  that lies on isolation region  310 . Fourth conductive section  320 , which is connected to first conductive section  312 , has a fourth width W 4  that is greater than the first width W 1 . Similarly, fifth conductive section  322 , which is connected to second conductive section  314 , has a fifth width W 5  that is greater than the second width W 2 . 
   Interconnect structure  300  also includes a first vertical conductive segment  330  that contacts a center region of the fourth conductive section  320 , and a second vertical conductive segment  332  that contacts a center region of the fifth conductive section  322 . The first and second vertical conductive segments  330  and  332  can be implemented as contacts and/or vias. 
   Alternately, rather than having fourth and fifth conductive sections that are wider than the first and second conductive sections, the contacts and/or vias can be connected to the first and second regions.  FIG. 4  shows a plan view that illustrates an example of a portion of an interconnect structure  400  in accordance with the present invention. 
   As shown in  FIG. 4 , interconnect structure  400  includes a region of isolation material  410 , a first conductive section  412 , a second conductive section  414 , and a third conductive section  416  that lies between and contacts the first and second conductive sections  412  and  414 . The first, second, and third conductive sections  412 ,  414 , and  416  contact and lie on isolation region  410 . 
   In addition, first conductive section  412  has a first width W 1 , second conductive section  414  has a second width W 2  substantially equal to the first width W 1 , and third conductive section  416  has a third width W 3  that is less than the first and second widths W 1  and W 2 . The first, second, and third widths W 1 , W 2 , and W 3  are measured parallel to each other. Further, third conductive section  416  has the same thickness as the first and second conductive sections  412  and  414 , and can have a number of different lengths. 
   As further shown in  FIG. 4 , interconnect structure  400  includes a first vertical conductive segment  420  that contacts a center region of the first conductive section  412 , and a second vertical conductive segment  422  that contacts a center region of the second conductive section  414 . The first and second vertical conductive segments  420  and  422  can be implemented as contacts and/or vias. Thus, the first and second vertical conductive segments  420  and  422  can be formed on the first and second conductive sections  412  and  414 . 
   In addition to a necked down region of a conductive line, fuse  220  can also be implemented as a thinner contact/via structure.  FIG. 5  shows a plan view that illustrates an example of a portion of an interconnect structure  500  in accordance with the present invention. As shown in  FIG. 5 , interconnect structure  400  includes a region of isolation material  510 , a first conductive section  512 , a second conductive section  514 , and a third conductive section  516  that lies between and contacts the first and second conductive sections  512  and  514 . The first, second, and third conductive sections  452 ,  514 , and  516  contact and lie on isolation region  510 . 
   As further shown in  FIG. 5 , interconnect structure  500  includes a first vertical conductive segment  520  that contacts a center region of the first conductive section  512 , and a second vertical conductive segment  522  that contacts a center region of the second conductive section  514 . The first and second vertical conductive segments  520  and  522  can be implemented as contacts and/or vias. 
   In addition, first conductive section  512  has a first width W 1 , second conductive section  514  has a second width W 2  substantially equal to the first width W 1 , and third conductive section  516  has a third width W 3  that is less than the first and second widths W 1  and W 2 . The first, second, and third widths W 1 , W 2 , and W 3  are measured parallel to each other. 
   Further, first vertical conductive segment  520  has a fourth width W 4 , and second vertical conductive segment  520  has a fifth width W 5  that is less than the fourth width W 4 . The fourth and fifth widths W 4  and W 5  are measured parallel to the first, second, and third widths W 1 , W 2 , and W 3 . Alternately, second vertical conductive segment  522  can have a width W 5  substantially equal to the fourth width W 4 , but a dimension D, measured normal to the fourth width W 4  along a length L of the third conductive section  516 , which is less than the fourth width W 4 . A thinner contact/via structure functions in the same way as a necked down portion of a conductive line, remaining intact in response to an ESD pulse and blowing in response to a misfire current. 
   Returning to  FIG. 2 , once fuse  220  has been blown, a current path from first pin  210  to second pin  212  through SCR  216  is permanently removed. However, once chip  200  has been attached to a printed circuit board, there is no longer any need for ESD protection. This is because all of the chips on the printed circuit board are protected by bypass capacitors that can absorb an ESD pulse. 
   Thus, chip  200  is operated by applying a DC bias voltage to pin  210 . All of the DC bias voltage is placed across SCR  216  and fuse  220 , which are connected in series. The DC bias voltage is substantially constant, and not ever intentionally raised to a level that is sufficient to turn on SCR  216 . If SCR  216  misfires and turns on during normal operation, fuse  220  blows quickly such that electronic circuit  214  experiences only a momentary glitch in the power. 
   It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.