Abstract:
For a digital communications receiver, a clock and data signal recovery circuit and method use an all digital delay locked loop timed by an on-chip transmit clock signal. The digital delay locked loop includes a phase detector and loop filter. The phase detector determines, for each data signal rising or falling edge, if the current delay of a reference clock signal leads or lags the data signal edge. The loop filter examines the stream of such lead/lag indications, performs a nonlinear filtering process thereon, and in response increases or decreases the clock signal phase appropriately.

Description:
BACKGROUND 
     1. Field of the Invention 
     This invention relates to digital communications and more specifically to clock and data signal recovery for digital communications. 
     2. Description of the Prior Art 
     As is well known in the field of digital (e.g., computer data) communications, two fundamental processes are carried out at the receiver end of a communications system to convert an analog signal transmitted along a communications channel to a digital signal. These processes are (1) analog amplitude domain processing which typically includes signal equalization and slicing in order to produce a discrete level, analog transition time signal; (2) analog transition time processing which typically includes clock signal and data signal recovery to produce a discrete level, discrete time signal; see “A 30-MHz Hybrid Analogy Digital Clock Recovery Circuit in 2-μmCMOS,” Kim et al.,  IEEE Journal of Solid - State Circuits , SC-25, December 1990, PP. 1385-1394. This disclosure is directed to the latter process. 
     Note that a discrete level/analog transition time signal has only two voltage levels but can transition between those levels at any time. A discrete level/discrete time signal again has only two voltage levels but can transition between those two levels only at multiples of a time period. 
     Data recovery is usually achieved by sampling a discrete level/analog-transition-time signal at a rate determined by a recovered clock (timing) signal. There is typically no independent timing signal per se; instead the “clock signal” is inherent in the timing of the data signal pulses. The recovered clock signal therefore is a timing signal generated synchronous to the rate at which the original data pulses were transmitted from the receiver. 
     See FIG. 1 showing a conventional digital communications system including, at the receiver end, a D-type flip flop circuit  14 , to the D terminal of which a data signal is coupled via line  10 . The clock input terminal of flip flop  14  is connected via input line  16  to a transmitter (Tx) clock signal. The output signal from flip flop  14  at its Q terminal is coupled via analog processor  20  to a communications channel  22 , for instance a twisted cable pair, coaxial cable etc. Channel  22  may also be for instance an optical fiber link, telephone line, microwave transmission system, etc. (In the optical fiber situation, the analog processor  20  is replaced by an optical transmitter.) 
     At the distal end of the communications channel  22  the receiver is located which includes an analog processing circuit  26 , as described above including both equalization and slicer functions. The output signal from analog processing circuit  26  is connected to the input terminal of a clock recovery circuit  30 , the output terminal of which is connected to the clock input terminal of a D type flip flop  32  which performs the data recovery function. Line  36  connects the output terminal of the analog processing circuit  26  to the D input terminal of the data recovery flip flop  32 . The recovered data signal is output on the output (Q) terminal of the flip flop  32 . 
     FIG. 2 relates to FIG. 1 by showing at each of the designated nodes A, B, C, D, E, F, G in FIG. 1, the associated waveform. Node A carries the digital clock signal; node B carries the digital data signal, each pulse of which defines a high and a low state. Node C carries the analog counterpart of the node B signal. Node D carries the received analog signal as distorted by channel  22 . Node E carries the processed received analog signal, including some errors at the transition times (arrows). Node F carries the recovered clock signal and node G the recovered digital data signal. 
     FIG. 3 shows detail of the clock recovery circuit  30  of FIG. 1, illustrating one technique for clock/data recovery which recovers the clock signal using an analog phase-locked loop (PLL) that is locked to the discrete-level/analog-transition-time signal, hereinafter referred to as the analog-transition signal. This recovered clock signal is applied to a flip flop  32  to sample the analog-transition signal. The output of flip flop  32  at node G is the discrete level, discrete time signal hereinafter referred to as a digital signal. 
     The clock recovery circuit  30  includes a phase detector  40  which generates up or down pulses whose durations are proportional to the phase error between the recovered clock signal and the signal at node E. The output of the phase detector  40  is coupled to a charge pump  44  which in turn is connected via analog filters  46  and  48  to the input terminal of a voltage controlled oscillator (VCO)  54 . The output signal from the VCO  54  is fed back to the other terminal of the conventional phase detector  40 , thus forming the conventional analog phase locked loop. The nodes E, F, A in FIG. 3 correspond to the similar nodes in FIG.  1 . 
     The analog PLL, while common, suffers the same disadvantages as most analog circuits, namely: being difficult to manufacture because of process variations, sensitive to system noise, and sensitive to temperature and power supply drift. 
     SUMMARY 
     In accordance with this invention, clock and data signal recovery is performed, in one embodiment, without using an analog PLL, and wherein all digital processing is performed at for instance one half the data rate. This is done by providing a digital delay locked loop based on e.g., an off chip reference clock signal. A phase detector, phase pump, and a loop filter are in the delay locked loop, where the phase detector determines for each data pulse&#39;s rising (or falling) edge, if the current delay (phase) of the reference clock signal is leading or lagging the data signal edge. The loop filter determines from the stream of lead/lag indicators, by a non-linear digital filtering process, whether it should increase or decrease the delay. The phase pump “holds,” or stores the current reference clock signal phase, until the next update by the loop filter. This advantageously eliminates the VCO from the loop, allows use of digital signal processing, and provides better performance. 
     In one embodiment the non-linear loop filter is a digital signal processing apparatus and drives a phase pump which in turn outputs a signal to a selector which selects from amongst a number (e.g. 32) of various phases of a clock signal. The phase is selected in response to whether a lead or lag adjustment is necessary. This leading or lagging new clock signal is then fed back to the phase detector and also is used as the clock signal to clock the data recovery circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art phase detector. 
     FIG. 2 shows waveforms associated with various nodes of the circuit of FIG.  1 . 
     FIG. 3 shows the clock and data recovery circuits of FIG. 1 in additional detail. 
     FIG. 4 shows a clock and data recovery circuit in accordance with this invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 4 shows relevant portions of a receiver for a digital communication system in accordance with this invention. Other conventional portions of the receiver are not shown. For instance, where this receiver is used in a Fast Ethernet environment, the conventional higher layers of circuitry that interface to e.g. a computer that uses the received data signal are not shown. The receiver in FIG. 4 is intended to replace elements  30  and  32  in a system as in FIG.  1  and hence only represents the analog transition time processing portion, i.e., the clock and data recovery portion of the receiver. 
     In FIG. 4, as in FIG. 1, line  60  is coupled to the output terminal of an equalizer/slicer circuit  26 , which may be conventional. 
     The incoming data signal on line  60  is therefore coupled to one (clock) input terminal of a lead/lag detector  62 , the other input terminal of which is coupled to the output terminal  88  of multiplexer  70  and to the clock terminal of the data recovery flip flop  90 . Lead/lag detector  62  is e.g. a D type flip flop connected as shown. In this case the clock input terminal is connected to receive the “data” input while the D input terminal is connected to receive the “clock” input signal, so this flip flop  62  is connected in the reverse to the usual flip flop connections. This is because the data signal is being used to sample the clock signal to determine if it (the clock) is currently leading or lagging. The output (Q) terminal of the detector  62  is connected to the input terminal of a non-linear digital signal processing element  64  which is part of the loop filter referred to above, further functionality of which is explained below. 
     The output terminal of the non-linear DSP element  64  is connected to the input terminal of a phase pump  68 . The phase pump  68  is a digital circuit that essentially increases or decreases its output signal (according to its input signal) and holds its output signal. In this case the phase pump input signal is the amount of lead or lag as determined by 64 elements and its output goes to selector  70 . So as long as the output signal of element  64  is zero, the output signal of phase pump  68  will be held e.g. for 32 data edges. 
     The output port of phase pump  68  is an N bit digital bus coupled to the N control terminals of a selector (multiplexer)  70 . The various signal input terminals of multiplexer  70  are coupled to receive various clock signals f 1 , f 2 , f 3 , f 2N . In one example N equals 5, and so there are 32 such clock signals. The frequency of each clock signal f 1 , f 2  etc. is the same: however they are each slightly out of phase with one another, i.e. each is a successively delayed version of the clock signal. In one embodiment these clock signals are generated by applying a single clock signal from source  76  to the input terminal of a set of serially connected delay elements  78 ,  80 , . . .  82 . Hence in this case there are  31  such delay elements providing 32 signals f 1 , f 2 , . . . f 32 . The delay provided by each delay element is equivalent to that of ½ N  times the minimum expected time between successive data signal edges (data signal period). Hence in one example if the period between successive data signal edges is no less than 8 nanoseconds and there are 31 delay elements, each delay element gives 0.25 nanoseconds of delay. 
     The source  76  of the clock signals in FIG. 4 is here designated as being a transmission (Tx) clock, because in one embodiment the source  76  is an on-chip “transmission clock” signal which is part of a transmitter. (It is to be understood that the FIG. 4 circuit, while it is a receiver, in this embodiment is on the same integrated circuit with an associated transmitter which has its own clock signal source.) Generally such an “on-chip” transmission clock signal is known to be within a very small tolerance, in terms of frequency, of the received signal&#39;s clock signal. Hence this is a convenient source of a clock signal which is close to that of the received clock signal which is to be recovered. Of course, other sources for the reference clock signal(s) may be used instead. 
     Hence the output signal from the selector (multiplexer)  70  is the selected clock signal which is used to clock the data recovery circuit  90 , which is similar to the data recovery circuit  32  in FIG. 1, and also used as a second input signal to the lead/lag detector  62 . Hence the elements  62 ,  64 ,  68 ,  70  with feedback line  88  form a digital delay locked loop. Note that only one phase of the reference clock  76  is needed at any given time. 
     It is to be appreciated that in one embodiment this is essentially a digital device embodied in digital logic circuitry rather than by analog elements. As seen, no conventional analog filtering components are needed. Instead, filtering is provided by the non-linear digital signal processing element  64 . In one embodiment this is an all digital device, i.e. having no resistors or capacitors. Hence the present digital delay locked loop is all digital. 
     The non-linear digital signal processing element  64  in one embodiment is all digital “hardware” (logic circuitry). However this is not limiting and in other embodiments this and other elements in accordance with this invention may be for instance in the form of code (software) to be executed by a general purpose processor or by a dedicated digital signal processor. 
     The non-linear digital signal processing element  64  determines if the previously chosen clock signal, supplied on the D terminal of lead/lag detector  62  is arriving, in terms of time, before (leading) or after (lagging) the data edge provided on line  60 . Element  64  in one embodiment counts a consecutive number of such lead/lag comparisons, e.g. 16. Clearly if the last 16 comparisons include a preponderance of data pulse edges leading the clock signal, it is desirable to advance the clock signal; if the data edges are lagging the clock signal, it is desirable to retard the clock signal. Hence in the code POS-CNT (positive count) refers to the number of data pulse rising edges counted. One embodiment counts both the rising and falling edge of each data pulse. One accumulates e.g. 16 such counts. In one embodiment if more than half these 16 counts indicate the existence of a lead, then one wants to delay the clock signal; if less than half of them indicate a lead, one wants to advance the clock signal. In one embodiment the advance at each instance is only one increment, where the increment is the difference between for instance signals f 1  and f 2  or f 2  and f 3  etc. Hence in this relatively simple version the advance (or retardation) at each decision time, e.g. 16 data edges, is only one phase (one delay period  78 ,  80 ,  82 , etc.). In another version, the amount of delay or advance is made variable by using a more sophisticated non-linear DSP process in element  64 . 
     Hence the output signal from the non-linear DSP element  64  is in one embodiment merely a 0 or 1, where 1 indicates advancing the clock phase by one delay and 0 indicates retarding the clock phase by one delay. The phase pump  68  then translates this value into the desired selection from amongst f 1 , f 2 , f 3 , etc. since the phase pump  68  keeps track of the previously selected clock signal f 1 , f 2 , etc. 
     Hence by use of such an apparatus and the accompanying method, one dynamically alters the phase of the recovered clock signal using the all-digital delay locked loop. 
     This disclosure includes copyrightable material. The copyright owner gives permission for facsimile reproduction of material in Patent Office files but reserves all other copyright rights whatsoever. 
     This disclosure is illustrative and not limiting; further modifications will be apparent to one skilled in the art in the light of this disclosure and are intended to fall within the scope of the appended claims.