Abstract:
A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

Description:
BACKGROUND 
     This disclosure relates to high voltage clamps for integrated circuits. The need for protection against electrostatic discharge (ESD) exists, for example, in applications including programming pads. Such applications may involve One Time Programmable (OTP) memories used in RFID, video game consoles, mobile phones, and the like. 
     Design of high voltage tolerant ESD clamps using nominal devices can be quite challenging. During programming mode, the use of simple ESD clamps using nominal devices often present reliability issues such as gate oxide stress, drain/well voltage overstress, etc. A commonly used technique to overcome such problems is by stacking nmos FETs in a clamping device. An example of such technique is disclosed in U.S. Pat. No. 7,203,045. Multilevel stacking of nmos elements, however, reduces clamping efficiency with each added level. Reliability concerns exist with respect to drain junction voltages and gate oxide breakdown, as well as the possibility of leakage currents during normal functioning modes. 
     A high voltage tolerant clamp is needed that uses nominal devices, yet avoids reliability stress that can occur due to a high voltage application. Such clamp should be optimized to reduce area and current leakage. 
     DISCLOSURE 
     The needs described above are fulfilled, at least in part, by a pmos nmos series clamp based circuit connected between a voltage source terminal, such as an integrated circuit pad, and ground. The inverter based circuit contains both nmos and pmos devices connected in series. A trigger unit connected between the voltage source and ground includes a plurality of output terminals coupled to the inverter based circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices. 
     The trigger unit may include a resistive-capacitive timing circuit. First and second circuit branches may have capacitive and resistive elements connected between the voltage source terminal and ground. Junctions between a capacitive element and a resistive element in each circuit branch may be connected to respective inputs of the nmos and pmos devices. An ESD voltage event is detected by the trigger unit and, in response thereto, the series connected nmos and pmos devices are activated. Application of clamping signals to the nmos and pmos devices is applied by the resistive-capacitive timing circuitry. A plurality of capacitive elements may be provided in each circuit branch, the extent of delay being dependent thereon. 
     The trigger circuit, upon sensing termination of the ESD voltage occurrence, deactivates the series connected nmos and pmos devices, to restore normal functionality to the circuit application. Such deactivation may be delayed by latching the clamping signals. For this purpose, the first and second latch circuits may include respective back-to-back inverters. 
     The trigger unit alternatively may include a resistor divider circuit. A plurality of PGATE FETs and a plurality of NGATE FETs may be connected between the voltage source terminal and ground. Gates of these devices are connected to respective resistive elements of the resistor divider circuit. A double guard ring may be formed for adjacent series connected like FET elements. 
     Additional advantages of the present disclosure will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       Various exemplary embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which: 
         FIG. 1  is a block diagram of a PMOS/NMOS power clamp of the present disclosure; 
         FIG. 2  is a circuit diagram of one implementation for the power clamp of  FIG. 1 ; 
         FIG. 3  is a circuit diagram of another implementation for the power clamp of  FIG. 1 ; and 
         FIG. 4  is an exemplary circuit diagram modification for the implementation of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     A PMOS/NMOS power clamp of the present disclosure is depicted in block diagram form in  FIG. 1 . P-Clamp  10  and N-Clamp  12  are ESD clamping devices connected in series between a voltage source pad  14  and ground. During normal pad operation, such as OTP memory programming, the gate of N-Clamp  12  is driven to a logic low and the gate of P-Clamp  10  is driven to a logic high. As both devices are driven off, there will be no oxide stress, no oxide/junction stress, and no leakage current. After an ESD event is detected by the trigger unit, clamping devices  10  and  12  will be driven on by clamping signals generated by trigger unit  16  to sink the current to ground. A logic low signal will be applied to P-Clamp  10  and a logic high signal will be applied to N-Clamp  12 . 
     Buffering by the trigger unit is desirable to stabilize the clamping signals to avoid any mis-triggering of the clamping devices. One implementation for providing appropriate buffering is exemplified by the circuit diagram of  FIG. 2 . P-Clamp  10  and N-Clamp  12  are under control of separate buffering and RC timer circuit branches. Capacitors are realized using a plurality of nmos devices (MNC 1 , MNC 2  . . . MNCn) and a plurality of pmos devices (MPC 1 , MPC 2  . . . PMCn) to avoid any voltage over stress issue for the gate dielectrics. Capacitors MPC 1 , MPC 2 , MPCn, and resistor R 1 , connected in series between terminal  14  and ground, form an N-RC timer. Similarly, capacitors MNC 1 , MNC 2  . . . MNCn, and resistor R 2 , connected in series between terminal  14  and ground, form an P-RC timer. Node  20 , the resistor capacitor junction, is connected to the gate of N-Clamp  12 . Node  22 , the resistor capacitor junction, is connected to the gate of the P-Clamp  10 . 
     During normal operation, or programming mode, all capacitor elements are fully charged. Node  20 , connected to the NGATE of MN 1   12  will be at a logic low, and node  22 , connected the PGATE of MP 1   10 , will be at a logic high. This will keep both MP 1  and MN 1  transistors off. The gate, source and bulk of PMOS MP 1  will be at a logic high, while the gate, source and bulk of NMOS MN 1  will be at a logic low. Node np  24  will be left floating. This will avoid any possible over stress on the devices. During an ESD event, capacitors will be electrically shorted. This will drive node  20  to a logic high, and node  22  to a logic low. This will keep both clamping devices MP 1  and MN 1  on during the ESD event. 
     An alternative implementation is exemplified by the resistor divider based circuit shown in  FIG. 3 . P-Clamps MP 1  and MP 2  and N-Clamps MN 1  and MN 2  are connected between in series between voltage source pad  14  and ground. A plurality of four resistor elements R 3  is connected between pad  14  and ground. Node  30 , the junction between R 5  and R 6 , is connected to the gate of MN 1 . Node  32 , the junction between R 3  and R 4 , is connected to the gate of MP 1 . Resistor R 7  is connected between pad and the gate of MP 2 . Resistor R 8  is connected between the gate of MN 2  and ground. Resistors R 3 -R 6  may be of substantially equal value, for example, 2.0 Meg. Resistors R 7  and R 8  may be of substantially equal lesser value, for example, 50K. Bulk resistance SBLK may be about 1.5 um, and on the order of a few Ohms. 
     The illustrated circuit of  FIG. 3  provides a double guard ring around the pmos and nmos elements. The circuit is formed in a relatively reduced area of the integrated circuit. In operation, the circuit will perform in accordance with the description of  FIG. 1 . During normal pad operation, the gates of MN 1  and MN 2  are driven to a logic low and the gates of MP 1  and MP 2  are driven to a logic high. As these devices are driven off, there will be no oxide stress, no oxide/junction stress, and no leakage current. An ESD event is detected from the high voltage applied to pad  14 , to drive clamping devices MN 1 , MN 2 , MP 1  and MP 2 , to sink the current to ground. Logic low signals will be applied to the gates of MP 1  and MP 2  and logic high signals will be applied to the gates of MN 1  and MN 2 . 
     The circuit shown in  FIG. 4  exemplifies a modification for the circuit of  FIG. 2 . As in the circuit of  FIG. 1 , MP 1  and MN 1  are connected in series between voltage pad  14  and ground. Capacitor MPC and resistor R 1  are connected in a series circuit branch between pad  14  and ground. Node  22 , the junction between MPC and R 1 , is coupled to the gate of MP 1  via latch  40 . Latch  40  includes back-to-back inverters. MP 1  and MN 1  are connected in series between voltage pad  14  and ground. Capacitor MNC and resistor R 2  are connected in a series circuit branch between pad  14  and ground. Node  20 , the junction between MNC and R 12  is coupled to the gate of MN 1  via latch  42 . Latch  42  includes back-to-back inverters. Each of the circuit branches corresponds to a respective circuit branch of the diagram of  FIG. 2 . Latches  41  and  42  form weak buffers that delay switching off the clamping devices MP 1  and MN 1  following an ESD event. 
     In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein. For example, the latch circuits illustrated in  FIG. 4  may be utilized in conjunction with the resistor divider circuit of  FIG. 3 . The relative values of the elements described with respect to  FIG. 3  are merely exemplary and may be adjusted in accordance with expected application.