Abstract:
A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region the n+ heavily doped region and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide is heavily doped than the front region thereof.

Description:
This application is a Division of application U.S. Ser. No. 10/425,951, entitled “TRENCH POWER MOSFET IN SILICON CARBIDE AND METHOD OF MAKING THE SAME” and filed on Apr. 30, 2003, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a semiconductor device, specifically, to a novel termination structure for trench MOS devices so as to prevent leakage current. 
     BACKGROUND OF THE INVENTION 
     Currently, in the power transistors with breakdown voltage over 1000V market is mostly occupied by silicon base insulated gate bipolar transistor (IGBT). However, owing to the bipolar carriers characteristic of IGBT devices, the devices will suffer problems of the lifetime of the minority while turning the device off. Consequently, if it could not to add lifetime killers in the manufacture process, the system should have to tolerate the power consumption and time waste while turning off IGBT devices. 
     By contrast, silicon base metal oxide semiconductor field transistor features with mono-carrier species, as a result, it provides faster switch speed and less extra power consumption than those bipolar IGBTs. This is because the silicon carbide having large energy band gap of about 3.26 eV, high critical breakdown electric field intensity and high conductivity (4.9 W/cm-k) and is envisioned as an excellent material for power transistor. The power transistor based on silicon carbide can come up to a benchmark of 1000V breakdown voltage without suffering any difficulty. The breakage voltage can even come up to 5 kV if the epi-layer thickness is appropriately adjusted. 
     Thus, it is prone to develop silicon carbide base power transistor replaced for silicon IGBT. According to the estimation in theory, under a condition of the same breakdown voltage, the power transistor formed of silicon carbide has a Ron, sp (sheet resistance for transistor operates at a liner region) of Id vs Vd only about 1/200 to 1/400 of conventional power transistor. 
     For the purpose of acquiring a normal-off device, most of the conventional silicon carbide MOSFETs are operated in an inversion channel type. An example is U.S. Pat. No. 5,506,421, issued to Palmour, with a title of “Power MOSFET in Silicon Carbide.” Please refer to  FIG. 1A  that illustrates a cross-sectional view of the silicon carbide MOSFET with an inversion channel. In this figure, a drain region consisting of a silicon carbide substrate  10  has n-type impurities in heavily doped and a drift layer  12  has lightly doped n-type impurities. A layer over the drift layer  12  is a p-type epi-layer  14 . The p-type epi-layer  14  comprises trenches  27  formed therein and having trench bottoms thereof come down into the drift layer  12 . An oxide layer formed on the bottoms and sidewalls of the trenches and extended to the upper surface of the p-type epi-layer  14 . Poly gates with contacts  30  thereof are then formed on the gate oxide layer  31 . Moreover, the source contacts  22  are formed over both he p-type epi-layer  14  and n+ doped regions  18  where the n+ doped regions  18  are formed on the two sides of each trench  27  so as to keep the source contacts  22  remain at the same voltage level. In the figure, the termination region  35  and oxide layer  36  formed thereover are shown. The deficiency of about the forgoing MOSFET is with a large R ON ,sp, the specific on-resistance in the linear operating region of the transistor while turning on. 
     To reduce the R ON ,sp, the MOSFET of accumulation channel type may provide a good solution. The accumulation channel make channel of the electron migration from inducing an inversion channel, where the channel is near the surface of the silicon carbide substrate turn into the interior bulk region of the silicon carbide substrate. Increasing the electron mobility and reduce the R ON ,sp, of the device are thus anticipated. 
     An example of accumulation channel type silicon carbide MOSFET is U.S. Pat. No. 6,281,521 with a title “Silicon Carbide Horizontal Channel Buffered Gate Semiconductor Devices” issued to Singh. The device structure of the patent proposed is shown in  FIG. 1C , which is a planar device. The feature of the device is no gate oxide layer but a p-type gate layer  16  lie in between the gate contact layer  20  and the drift layer  12 . The drift layer  12  is formed on the silicon carbide substrate  10 . While exerting a bias voltage to the gate contact  20 , an accumulation channel is formed on the upper portion of the drift layer  15 . As the gate voltage is grounded, the channel presents pinch-off in between the p+ base region  14  and the gate layer.  16 . 
     To make the transistor becoming a normally off (i.e. no gate bias voltage, no current flow occurs), the doping concentration in the drift layer  12 , the p+ base region  14  and the gate layer  16  have to appropriately restricted, and so does the spacing in between the p+ base layer  14  and the gate layer  16 . In the situation, the channel region  15  is completely depleted. 
     The proposed Singh&#39;s patent had reached the aim of decreasing Ron,sp. However, the area occupied for a planar MOSFET is larger than for a typical trench MOSFET. 
     The motivation of the present invention is thus to propose a trench MOSFET of accumulation channel type so as to increase the electron mobility and thus reduce the Ron,sp. 
     SUMMARY OF THE INVENTION 
     The present invention discloses a structure of an accumulation channel type trench MOSFET in silicon carbide (SiC) and a method of making the same. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region, the n+ heavily doped region, and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. 
     Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide substrate is more heavily doped than the front region thereof. 
     The method comprises: at first, an n-type heavily doped silicon carbide substrate having an n-type drift layer formed thereon is provided. Then, a first photoresist pattern having openings to define p-base regions is formed. Thereafter, a first ion implant is carried out to form the p-base regions in the drift layer. After removing the first photoresist pattern, a second ion implant is carried out to form an n-type heavily doped layer in the drift layer and extended to an outer surface of the drift layer. Next, a trench is formed in the drift layer and in between the p-base regions through lithography and an etching process. The trench is separated from the p-base regions by an accumulation channel width. Subsequently, a gate oxide layer over all surfaces is performed. A polycrystalline silicon layer is then refilled the trench and formed on all surface of the SiC substrate. The polycrystalline silicon layer is then patterned to form a trench polygates. Afterward, a second photoresist pattern is formed to define p-type heavily doped regions. A third ion implant is then conducted to form p-type heavily doped regions which are extended to the surface of the drift layer and is abutting remnant n-type heavily doped layer and over the p-base region. The second photoresist pattern is then stripped. Next, an insulating layer over all exposed surface is formed. Then a patterning step is done to define a capping layer over the trench polygate and a portion of n-type heavily doped layer and to define a poly-gate contact. A thermal anneal to activate all ions doped is then performed. Thereafter, a first metal layer atop front surface of the silicon carbide substrate is formed. The first metal layer is then patterned to form a source contact metal layer and a trench polygate contact metal layer. All layers formed on a rear surface of the silicon carbide substrate are removed. Finally, a second metal layer on the rear surface is formed and functions as a drain electrode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
         FIG. 1A  is a cross-sectional view of a conventional trench MOSFET, which is an inversion type MOSFET. 
         FIG. 1B  is a cross-sectional view of a conventional planar MOSFET, which is an accumulation type MOSFET. 
         FIG. 2A  is a cross-sectional view of forming p-base regions in the drift layer formed by selecting implant in accordance with the present invention. 
         FIG. 2B  is a cross-sectional view of forming an n-type heavily doped layer in the drift layer by blanket implant in accordance with the present invention. 
         FIG. 2C  is a cross-sectional view of forming a trench in the drift layer by selected etching in accordance with the present invention. 
         FIG. 2D  is a cross-sectional view of refilling the trench with a polysilicon layer in accordance with the present invention. 
         FIG. 2E  is a cross-sectional view of defining the trench gate in accordance with the present invention. 
         FIG. 2F  is a cross-sectional view of forming a thin poly-oxide layer by thermal oxidation in accordance with the present invention. 
         FIG. 2G  is a cross-sectional view of forming an insulating layer capping the trench gate and a portion of n-type heavily doped layer in accordance with the present invention. 
         FIG. 2H  is a cross-sectional view of forming a source contact metal layer and poly contact metal layer and drain contact metal layer in accordance with the present invention. 
         FIG. 2I  is a schematic topographic diagram of trench MOSFET in accordance with the present invention. 
         FIG. 3  shows a simulation result of Id-Vd relationship diagram in accordance with the trench MOSFET proposed by the present invention. 
         FIG. 4  shows a simulation result of blocking performance of the trench MOSFET of the present invention. 
         FIG. 5  shows a comparison for breakdown voltages, Ron,sp of the device, and the invention with devices proposed by other countries&#39; researching laboratories. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The method of forming trench metal oxide transistor according to the present invention is shown in cross-sectional views from  FIG. 2A  to  FIG. 2H . 
     Referring to  FIG. 2A , an n-type impurity doped silicon carbide substrate  100 A having an impurity doped silicon carbide epi-layer  100 B formed thereon is prepared. The epi-layer  100 B functions as drift layer  100 B. A photoresist pattern  102  is then formed on the epi-layer  100 B to define p-base regions  105 . Thereafter, a first ion implant is carried out to implant p-type ions into epi-layer  100   b  so as to form p-base regions  105 , using the photoresist pattern  102  as a mask. The p-type ions can be selected from aluminum or BF 2     +    ions. The p-base regions  105  are between about 0.8 to 5.0 μm in depth. In general, the diffusion length of the impurities in silicon substrate is much shorter than in silicon substrate during ion activation process. Therefore, the p-base region  180  is formed by multiple implants with different implant energies so as to uniform distribution the impurities. 
     Turning to  FIG. 2B , after stripping photoresist pattern  102 , a second and blanket ion implantation implants the epi-layer  100   b  with n-type ions to form an n+ heavily doped layer  108 . The n+ heavily doped layer  108  has a much shallower junction than p-base regions  105 . 
     Referring to  FIG. 2C , a hard mask layer formed of metal or oxide  110  is formed on the epi-layer  100 B through a lithographic and an etch step. The hard mask layer  110  is to defined trenches  120 . The silicon carbide epi-layer  100 B is then patterned to form trenches  120  using the hard mask  110  as an etch mask. The trenches  120  have a bottom depth value about the same as the bottom of the p-base regions  105 . Worthy to note, the trenches  120  are spaced from the p-base regions  105  by spacing with a width value W. The spacing in between the p-base regions  105  and trenches  120  functions as an accumulation channel. 
     Please refer to  FIG. 2D , after the hard mask or the photoresist pattern  110  removal, a gate oxide layer  130  is formed on a bottom and sidewalls of each trench  120  and extended to all surfaces of the epi-layer  100 B. The gate oxide layer  130  is a HTO layer formed by thermal deposition or a thermal oxide layer formed by thermal oxidation or a poly-oxide layer by polysilicon deposition and re-oxidation. Preferably, the gate oxide layer  130  is between about 50–200 nm. Afterward, a polycrystalline silicon layer  140  is deposited on all surfaces and filled in the trenches  120  by low-pressure chemical vapor deposition (LPCVD) in the meanwhile. The polycrystalline silicon layer  140  is doped through an in-situ doped process or by POCL3 diffusion after deposition. 
     Referring to  FIG. 2E , the polycrystalline silicon layer  140  is then patterned to form trench polygates  140 A using a lithographic step and an etch process. The trench polygates  140 A have a width W 1  larger than the trench width W 1  for a purpose of easier to form trench gate contact. 
     Referring to  FIG. 2F , a thermal oxidation process is then conducted to form an oxide layer on and enclosed the trench polygates  140 A. Certainly, a thinner oxide layer is formed on the surface of silicon carbide substrate  100  to increase the thickness of the gate oxide layer  130 . 
       FIG. 2G  illustrates a cross-sectional view. A photoresist pattern  165  is formed on the resulted surface to define p+ heavily doped regions  170 . A third ion implantation is then carried out to implant p-type ions into n+ heavily doped layer  108  so as to form p+ heavily doped regions  170  using the photoresist pattern  165  as a mask. Certainly, the dosage of the third ion implant is much heavier than the second ion implant dosage. For example, the dosage for p+ heavily doped regions  170  may be double than that of prior implant for n+ heavily doped layer  108  since it requires an electrical compensation with the n+ ions. Moreover, the p+ heavily doped regions  170 , n+ heavily doped layer (herein it become regions  108 ). And the p-base regions  105  are abutting each other so that if a voltage exerted on the source contact, the three regions are at the same voltage level. 
     Please refer to  FIG. 2H , the photoresist pattern  165  is removed. Then a dielectric layer  180  having a thickness of about 0.3–1.0 μm is formed over all surfaces. Afterward, a conventional deposition, lithography and etch steps and photoresist pattern stripping are successively followed to form an insulating layer capping the trench polygates and a portion of n+ heavily doped region  180  and form a polygates contact where the polygates contact is near the termination region by patterning the dielectric layer  180 . The dielectric layer  180  may be a TEOS layer or other oxide layer. 
     Thereafter a thermal process is carried out at a temperature of about 1400–1600° C. for a half hour to 2 hours to activate the conductive impurities. A metal layer is then deposited on the front surface of epi-layer  100 B by sputtering. A patterning process by using a lithography and an etch process are then done to form a source contact metal layer  200  on the p+ heavily doped regions  170 , n+ heavily doped regions  108  and the insulating layer  180  and form a polygates gate contact metal layer  210  to contact polygates contact. 
     Still referring to  FIG. 2H , before forming a drain metal layer, the layers formed over a rear surface of the silicon carbide  100 A are removed firstly. For example the removal may be done by using CMP (chemical/mechanical polishing) until the surface of the silicon carbide substrate  100 B is exposed or even more thinning the silicon carbide substrate. Finally, a second metal layer  220  on the rear surface is deposited. The second metal layer is functioned as a drain electrode  220 . 
     The schematic topographic diagram of the devices according the present invention is shown in  FIG. 2I . 
     The aforementioned device according to the present invention is an accumulation channel type MOSFET. The accumulation channel is abutting the sidewall of the trench polygate. Generally, the device with accumulation channel belongs to a normally-on type. That is a current flow will be found if there is a positive voltage drop in between the drain electrode and the source electrode even the gate voltage is zero. The device desired as depicted before aims at a normally-off device. Since silicon carbide has a larger energy band gap than silicon, the depleted region of device made of the silicon carbide is thus much larger than that of silicon. And thus easier to make the accumulation channel completely depleted while the gate voltage is grounded electrically. According to a preferred embodiment, a ratio of concentration in the p-base region  105  over the n-drift epi-layer  100 B is controlled at a range between about 10 15 :10 12  to 10 18 :10 15  and the accumulation channel is about 0.1–0.8 μm. 
     The electrons flow in accumulation channel will attract more and more electron if the gate voltage is positive and has a positive voltage difference between drain electrode and source electrode. Since electrons are majority while they move in the accumulation channel, as a result, the electron mobility decrease is thus alleviated due to less collision. In the situation of high electron mobility, low Ron,sp is thus anticipated. 
       FIG. 3  to  FIG. 5  show electrical performance simulation results of the device according to the present invention. The simulation proceeding is in accordance with the following conditions: the trench width and depth, are both 2 μm, the ratio of impurity concentration in p-base over in n-drift layer is 10 18  cm −3 :10 15  cm −3 . The accumulation channel width is 0.3–0.5 μm and the source voltage VSS=0V. 
       FIG. 3  shows relation curve of drain current versus drain voltage (Id-Vd). The result shows Ron,sp=11 mΩ-cm 2  as VG=VD=10V. 
       FIG. 4  shows simulation results of blocking performance of the device. The curves  410 ,  420 , and  430  are respectively, of electron impact ionization integral versus Vd, hole impact Ionization integral versus Vd, and leakage current during reverse bias. The VG (gate voltage)=VSS=0. The figure shows electron impact ionization drastically increase as Vd=2,100V and reaches an ultimate value ionization integral=1 while Vd=2,200V. It represents the breakdown voltage of the device is 2,200V. On the contrary, the hole impact ionization drastically increase at Vd=1,800V. However, the curve  430  almost attaches to the horizontal axis. It indicates almost free of leakage current until reaching breakdown voltage, Vd=2,200 V. 
       FIG. 5  shows a comparison for breakdown voltage and Ron,sp of the device the invention proposed with devices proposed by researching laboratories of other countries. Although the breakdown voltage of the device, the invention proposed is lower than that of KEPC proposed (2200V vs. 6000V), however, among all of the devices, the invention provides lowest Ron,sp. It implies that the heat generated of the device is lowest and thus it provide most stable electron mobility while comparing with the others. In views of the characteristic of silicon carbide, and for Ron,sp=10 −2  Ω-cm 2  is concerned, the device of the present invention proposed is the one whose voltage is the most approaching the theories. In fact, 2,200 V breakdown voltage is enough to satisfy most of applications. 
     The benefits of this invention are as follows: 
     The device provides high breakdown voltage and lower Ron,sp and thus electron mobility performance can keep above a mean level. 
     The leakage current problem is not occurred although it is an accumulation channel type. And the device is a normally-off device too. 
     As is understood by a person skilled in the art, the foregoing preferred embodiment of the present o invention is an illustration of the present invention rather than limiting thereon. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.