Abstract:
The present invention relates to a tester for testing a semiconductor IC circuit having multiple pins, comprising a timing signal generator, a test signal generator for outputting a test signal to an input pin of a semiconductor IC circuit.  
     The tester in the prior art has the drawbacks that the size of the circuit of the tester increases according to the number of input/output pins of a semiconductor IC circuit, because the timing signal generator, the test signal generator, etc have to be prepared for each of the input pins of a semiconductor IC circuit. As a result, the production cost of a tester increases, according to the number of the input pins of a semiconductor IC circuit.  
     A tester is proposed, in which the timing signal generating means can supply timing signals to all the test signal generating means or to one or some of the test signal generating means.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a tester for testing a semiconductor IC circuit having multiple pins.  
           [0003]    2. Description of the prior art  
           [0004]    [0004]FIG. 2 is a block diagram of a tester for testing a semiconductor IC circuit having multiple pins, in the prior art. A timing signal generator  1  generates a test period signal, which commands to generate a test pattern. The timing signal generator  1  generates also six timing signals TS 1 -TS 6 .  
           [0005]    When a pattern address controller  2  receives the test period signals from the timing signal generator  1 , the pattern address controller  2  outputs a reading-out address, which is used when a test pattern is read out. When a pattern memory  3  receives the reading-out address from the pattern address controller  2 , it outputs a test pattern having a leading address corresponding to the received reading-out address. When a formatter  4  receives the timing signals from the timing signal generator  1 , it generates a test signal on the basis of the test pattern supplied from the pattern memory  3 , according to the timing signals. A pin electronic circuit  5  amplifies and processes the test signal generated by the formatter  4  and outputs the test signal to an input pin of a semiconductor IC circuit. A controller  6  controls the timing of the generation of the test period signal in the timing signal generator  1 , and the selection of the timing signals to be used in the formatter  4 .  
           [0006]    The function of the tester for testing a semiconductor IC circuit having multiple pins in the prior art is explained below.  
           [0007]    A great many of test patterns are stored in the pattern memory  3  of a tester, and the timing signal generator  1  can output many sort of timing signals, so that the tester can estimate the functions of many sort of LSIs, for example, MPU or ASIC, namely the tester is assured to be a general purpose tester for testing a semiconductor IC circuit having multiple pins Recently, semiconductor IC circuits tend to have multiple pins, because the structure and function of ICs become more and more complex. As a result, a tester for testing such a semiconductor IC circuit must have a circuit shown in FIG. 2 in a form of a hard ware circuit for each of the input/output pins of a semiconductor IC circuit. The hard ware circuit of FIG. 2 is shown as a circuit for sending test signals to a pin  1  of a semiconductor IC circuit. Of course, a circuit having a structure same as FIG. 2 is prepared for each of the pins of a semiconductor IC circuit.  
           [0008]    When the hardware circuit estimates a semiconductor IC circuit, at first, the timing signal generator  1  generates, under the control of the control device  6 , a test period signal to send to the pattern address controller  2 . The test period signal commands to generate a test pattern. At the same time, the timing signal generator  1  outputs six timing signals TS 1 -TS 6  to the formatter  4 .  
           [0009]    The pattern address controller  2  has a counter for counting the number of receiving times of the test period signal from the timing signal generator  1 . And when the pattern address controller  2  receives the test period signal from the timing signal generator  1 , the pattern address controller  2  is triggered to output the counted value of the counter as a reading-out address, which is used when a test pattern is read out.  
           [0010]    When the pattern memory  3  receives the reading-out address from the pattern address controller  2 , it outputs a test pattern having a leading address identical to the reading-out address. For example, when the pattern address controller  2  receives an address “11000” as a reading-out address, the test pattern stored at the address “ 11000 ” is outputted. In general, a test pattern is a signal pattern comprised of an appropriately combined “1” and “0”.  
           [0011]    When the formatter  4  receives six timing signals TS 1 -TS 6  from the timing signal generator  1 , it selects timing signals, under the control of the control device  6 , so as to generate a test signal on the basis of the test pattern sent form the pattern memory  3 , according to the selected timing signals. For example, when the logical value of the test pattern is “1”, a test signal at HIGH level is outputted, and when the logical value of the test pattern is “0”, a test signal at LOW level is outputted, as shown in FIG. 3. The standing-up edge and the standing-down edge of each pulse constituting the test signal are controlled by the selected timing signals.  
           [0012]    The pin electronic circuit  5  amplifies and processes the test signal generated by the formatter  4  and outputs the signal to an input pin of a semiconductor IC circuit.  
           [0013]    The tester in the prior art can generate test signals having a complex wave form, using all the timing signals TS 1 -TS 6 . However, such a tester has drawbacks that it is necessary to prepare a timing signal generator, etc, for each of the input/output pins of a semiconductor IC circuit. Therefore, the size of the circuit of the tester increases according to the number of the input/output pins of a semiconductor IC circuit, hence, the price of a tester for testing a semiconductor IC circuit having multiple pins increases accordingly.  
           [0014]    Japanese patent application JP j-150005-A discloses a tester for testing a semiconductor IC circuit having multiple pins, in which timing signals generated by a timing signal generator are only used by a formatter for a pin  1  and another formatter for a pin  2 . This tester has the drawback that when all the timing signals are supplied to the formatter for a pin  1 , the other formatter for a pin  2  can not receive any timing signal and can not provide any test signal to the pin  2 .  
         SUMMARY OF THE INVENTION  
         [0015]    An object of the present invention is to eliminate these problems of the testers for testing a semiconductor IC circuit having multiple pins as in the prior art.  
           [0016]    Another object of the present invention is to provide a tester for common use, which can be fabricated cheaply, by suppressing the augmentation of the size of the tester circuit for testing a semiconductor IC circuit having multiple pins, which may increase according to the number of the pins of a semiconductor IC circuit.  
           [0017]    The object of the present invention is attained by a tester for testing a semiconductor IC circuit having multiple pins according to claim  1 .  
           [0018]    More precisely, the object is attained by a tester having a timing signal generating means, which can send timing signals to one of the test signal generating means and to more than one test signal generating means.  
           [0019]    The timing signal generating means can be controlled to send timing signals to all of the test signal generating means or to send to at least one of the test signal generating means.  
           [0020]    In an embodiment of the tester for testing a semiconductor IC circuit having multiple pins according to the present invention, the timing signal generating means supplies the timing signals to at least one of the test signal generating means.  
           [0021]    In an embodiment of the tester according to the present invention, the timing signal generating means supplies the timing signal to one of the test signal generating means, and the test signal generating means generates a test signal, using all the timing signal outputted from the timing signal generating means.  
           [0022]    In an embodiment of the tester according to the present invention, the timing signal generating means supplies the timing signals to both the test signal generating means, and the test signal generating means generate a test signal, using all the timing signal outputted from the timing signal generating means, so that identical wave form test signals are generated for two input pins of a semiconductor IC circuit.  
           [0023]    In an embodiment of the tester according to the present invention, the timing signal generating means supplies the timing signal to both the test signal generating means, and the test signal generating means generate a test signal, using different set of the timing signals outputted from the timing signal generating means, so that different wave form test signals are generated for two input pins of a semiconductor IC circuit.  
           [0024]    In an embodiment of the tester according to the present invention, the pattern generating means are comprised of a plurality of memories, and when the timing signal generating means output timing signals to one of the test signal generating means, the memories are used as one sequential memory, and when the timing signal generating means output timing signals to both of the test signal generating means, the memories are used as two separated memories.  
           [0025]    In an embodiment of the tester according to the present invention, delay circuits are inserted in the timing signal transmission lines connecting the timing signal generating means and one of the test signal generating means. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    [0026]FIG. 1 is a block diagram of a tester for testing a semiconductor IC circuit having multiple pins according to the embodiment  1  of the present invention.  
         [0027]    [0027]FIG. 2 is a block diagram of a tester for testing a semiconductor IC circuit having multiple pins in the prior art.  
         [0028]    [0028]FIG. 3 shows how a test signal is generated. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
     Embodiment 1  
       [0029]    The tester for testing a semiconductor IC circuit having multiple pins according to the embodiment 1 is explained below, referring to FIG. 1.  
         [0030]    A timing signal generator  11  (a component of timing signal generating means) generates a test period signal and six timing signals TS 1 -TS 6 . The test period signal commands to generate a test pattern. A first timing selector  12   a  (a component of timing signal generating means) sends timing signals TS 1 -TS 3  to at least one of first and second formatters  22 ,  23 . A second timing selector,  12   b  (a component of timing signal generating means) sends timing signals TS 4 -TS 6  to at least one of the formatters  22 ,  23 . A distributor  13  distributes the test period signal to first and second pattern address controllers  15 ,  16 . A delay circuit  14  is inserted in a line connecting between the distributor  13  and the second pattern address controller  16 .  
         [0031]    When the first and second pattern address controller  15 , 16  (a component of pattern generating means) receive the test period signal from the timing signal generator  11  through the distributor  13 , the first and second pattern address controller  15 , 16  output a reading-out address, which is used when a test pattern is read out. A pattern memory selector  17  outputs the reading-out address sent from the first pattern address controller  15  to either of first and second pattern memories  18  or  19 . When the first pattern memory  18  (a component of pattern generating means) receives the reading-out address from the pattern memory selector  17 , it outputs a test pattern which has a leading address identical to the received reading-out address. When the second pattern memory  19  (a component of pattern generating means) receives the reading-out address fray either of the second pattern address controller  16  or the pattern memory selector  17 , it outputs a test pattern which has a leading address at the received reading-out address.  
         [0032]    A first test pattern selector  20  receives a test pattern either from the pattern memory  18  or a second test pattern selector  21  and outputs it to the first formatter  22 . The second pattern selector  21  receives the test pattern from the pattern memory  19  and outputs it either of the first test pattern selector  20  or a second formatter  23 . When the first formatter  22  (first test signal generating means) receives the timing signals generated in the timing signal generator  11 , it generates a test signal on the basis of the test pattern sent from the first pattern selector  20 , according to the timing signals. When the second formatter  23  (second test signal generating means) receives the timing signals generated in the timing signal generator  11 , it generates a test signal on the basis of the test pattern sent from the second pattern selector  21 , according to the timing signals.  
         [0033]    A first pin electronic circuit  24  (a component of first test signal generating means) outputs the test signal generated in the first formatter  22  to a pin  1  (an input pin) of a semiconductor IC circuit, after amplifying and processing it. A second pin electronic circuit  25  (a component of second test signal generating means) outputs the test signal generated in the second formatter  23  to a pin  2  (another input pin) of a semiconductor IC circuit, after amplifying and processing it. Delay circuits  26  are inserted in lines connecting the timing signal generator  11  and the second formatter  23  through the first and second timing selectors.  
         [0034]    The function of the tester for testing a semiconductor IC circuit having multiple pins according to this embodiment is explained below.  
         [0035]    The tester can generate test signal in three modes:  
       Mode 1  
       [0036]    Test signal is outputted only to a pin  1  of a semiconductor IC circuit, and no test signal is sent to a pin  2  of the semiconductor. The first formatter  22  uses all the timing signals TS 1 -TS 6  to generate a test signal;  
       Mode 2  
       [0037]    Same test signals are outputted to pins  1 ,  2  of a semiconductor IC circuit. The first and second formatter  22 ,  23  use commonly all the timing signals, TS 1 -TS 6  to generate a test signal;  
       Mode 3  
       [0038]    Different test signals are outputted to pins  1 ,  2  of a semiconductor IC circuit. The first and second formatter  22 ,  23  use different timing signals to generate different test signals.  
       Mode 1  
       [0039]    The timing signal generator  11  generates a test period signal under instruction of a controller  27  and outputs it to the distributor  13 . The period signal commands to generate a test pattern. The distributor  13  distributes the test period signal to the first and second pattern address controllers  15 ,  16 . The delay circuit  14  is inserted in the signal transmitting line so that the test period signals sent from the distributor  13  reach to the first and second pattern address controllers  15 ,  16  at a same time.  
         [0040]    The timing generator  11  outputs timing signals TS 1 -TS 3  to the first timing selector  12   a,  at the same time it outputs timing signals TS 4 -TS 6  to the second timing selector  12   b.  The first and second timing selectors  12   a,    12   b  output all the timing signals TS 1 -TS 6  only to the first formatter  22 , and no timing signal is sent to the second formatter  23 .  
         [0041]    When the first pattern address controller  15  receives the test period signal from the distributor  13 , the first pattern address controller  1  is triggered by the signal to output a reading-out address, which is used when a test pattern is read out. The first address controller counts the receiving times of the test period signal from the timing signal generator  11 , and outputs; the counted value as a reading-out signal.  
         [0042]    In mode  1 , the second pattern address controller  16  does not output any reading-out signal, because the controller  27  does not instruct the second pattern address controller  16  to output it. Even if the second pattern address controller  16  outputs an address, the second pattern memory  19  ignores signals from the second pattern address controller  16 , in the mode 1.  
         [0043]    When the first selector  17  receives the reading-out signal from the pattern address controller  15 , it compares the reading-out signal and the leading address of the second pattern memory  19  under the control of the controller  27 . When the reading-out address is smaller than the leading address, the reading address is outputted to the first pattern memory  18 . When the reading-out address is larger than the leading address, the reading address is outputted to the second pattern memory  19 .  
         [0044]    When the first and second pattern memories receive the reading-out address from the pattern memory selector  17 , they output a test pattern which has a leading address identical to the reading-out address. For example, when the reading-out address is “1000”, a test pattern stored at the address “ 1000 ” is outputted. By the way, a test pattern is a signal pattern comprised of an appropriately coined “1” and “0”.  
         [0045]    In mode 1, the second test pattern selector  21  outputs the test pattern outputted from the second pattern memory  19  to the first test pattern selector  20 , and the first test pattern selector  20  outputs the test pattern received from either of the first pattern memory  18  or the second test pattern selector  21  to the first formatter  22 . No test pattern is outputted to the second formatter  23 .  
         [0046]    The first formatter  22  receives six timing signals TS 1 -TS 6  from the timing signal generator  11  through the first and second timing selectors  12   a,    12   b.  And the first formatter  22  selects timing signals from the timing signals, under the control of the controller  27 , so as to generate a test signal on the basis of the test pattern sent from the first pattern selector  20 , according to the selected timing signals.  
         [0047]    As shown in FIG. 3, when the logical value of the test pattern is “1”, a test signal of “H” state is outputted. And when the logical value of the test pattern is “0”, a test signal of “L” state is outputted. The standing-up edge and the standing-down edge of the pulse signal, which constitute the test signal, are controlled according to the selected timing signals.  
         [0048]    The pin electronic circuit  24  amplifies and processes the test signal so as to output it to a pin  1  of a semiconductor IC circuit.  
         [0049]    In mode 1, no test signal cannot be outputted to a pin  2  of the semiconductor IC circuit. However, all the timing signal TS 1 -TS 6  can be used for generating a test signal so that rather complex wave form test signal can be generated, if it is necessary.  
       Mode 2  
       [0050]    The timing signal generator  11  generates a test period signal under instruction of a controller  27  and outputs it to the distributor  13 . The test period signal commands to generate a test pattern. The distributor  13  distributes the test period signal to the first and second pattern address controllers  15 ,  16 . The timing signal generator  11  outputs timing signals TS 1 -TS 3  to the first timing selector  12   a , at the same time it outputs timing signals TS 4 -TS 6  to the second timing selector  12   b . Differently from the mode  1 , the first timing selector  12   a  outputs the timing signal TS 1 -TS 3  to both the first and second formatters  22 ,  23 . Also the second timing selector  12   b  outputs the timing signal TS 4 -TS 6  to both the first and second formatters  22 ,  23 .  
         [0051]    If the lengths of the transmission lines connecting the first and second timing selectors  12   a ,  12   b  and the first formatter  22  are different from that of connecting the first and second timing selectors  12   a ,  12   b  and the second formatter  23  are different, the arrival timings of the timing signals to the first and second formatters do not coincide to each other. Delay circuits  26  are inserted in the transmission lines connecting the first and second timing selectors  12   a ,  12   b  and the second formatter  23  for compensating the difference of the arrival timings of the timing signals.  
         [0052]    When the first and second pattern address controllers  15 ,  16  receive the test period signal from the distributor  13 , they are triggered to output a reading-out address, which is used when a test pattern is read out, to the pattern memory selector  17  and the second pattern memory  19 , respectively. When the pattern memory selector  17  receives the reading-out address from the first pattern address controller  15 , it outputs the reading-out address to the first pattern memory  18 , under the control of the controller  27 .  
         [0053]    When the first and second pattern memories  18 ,  19  receive a reading-out address from either of the pattern memory selector  17  or the second pattern address controller  16 , they output a test pattern having a leading address identical to the received reading-out address.  
         [0054]    In mode  2 , the first test pattern selector  20  outputs the test pattern supplied from the first pattern memory  18  to the first formatter  22 , and the second test pattern selector  21  outputs the test pattern supplied from the second pattern memory  19  to the second formatter  23 .  
         [0055]    The first and second formatters  22 ,  23  receive six timing signals TS 1 -TS 6  from the timing signal generator  11  through the first and second timing selectors  12   a,    12   b.  And the first and second formatters  22 ,  23  select timing signals from the received timing signals, under the control of the controller  27 , so as to generate a test signal on the basis of the test pattern sent from either of the first and second pattern selectors  20 ,  21  according to the selected timing signals.  
         [0056]    When the first formatter  22  generates the test signal, the pin electronic circuit  24  amplifies and processes the test signal to output it to a pin  1  of a semiconductor IC circuit. When the second formatter  23  generates the test signal, the pin electronic circuit  25  amplifies and processes the test signal to output it to a pin  2  of a semiconductor IC circuit.  
         [0057]    In mode  2 , only an identical signal can be outputted to the pins  1  and  2 . However, it is possible to output timing signals for two pins  1 ,  2  without using two timing generators  11 . The test signals for two pins  1 ,  2  can be generated using all the timing signals TS 1 -TS 6 .  
       Mode 3  
       [0058]    The timing signal generator  11  generates a test period signal under instruction of a controller  27  and outputs it to the distributor  13 . The period signal commands to generate a test pattern. The distributor  13  distributes the test period signal to the first and second pattern address controllers  15 ,  16 . The timing signal generator  11  outputs timing signals TS 1 -TS 3  to the first timing selector  12   a,  in the same time it outputs timing signals TS 4 -TS 6  to the second timing selector  12   b.  Differently from the modes  1 ,  2 , the first timing selector  12   a  outputs the timing signal TS 1 -TS 3  to the first formatter  22 . And the second timing selector  12   b  outputs the timing signal TS-TS 6  to the second formatter  23 .  
         [0059]    When the first and second pattern address controllers  15 ,  16  receive the test period signal from the distributor  13 , it outputs a reading-out address, which is used when a test pattern is read out. When the pattern memory selector  17  receives the reading-out address from the first pattern address controller  15 , it outputs the reading-out address to the first pattern memory  18 , under the control of the controller  27 .  
         [0060]    When the first and second pattern memories  18 ,  19  receive a reading-out address from either of the pattern memory selector  17  or the second pattern address controller  16 , they output a test pattern having a leading address identical to the reading-out address.  
         [0061]    In mode 3, the first test pattern selector  20  outputs the test pattern supplied. From the first pattern memory  18  to the first formatter  22 , and the second test pattern selector  21  outputs the test pattern supplied from the second pattern memory  19  to the second formatter  23 .  
         [0062]    When the first formatter  22  receives three timing signals TS 1 -TS 3  from the timing signal generator  11  through the first timing selector  12   a , the first formatter  22  selects timing signals from the received timing signals, under the control of the controller  27 , so as to generate a test signal on the basis of the test pattern sent from the first pattern selector  20  according to the selected timing signals.  
         [0063]    When the second formatter  22  receives three timing signals TS 4 -TS 6  from the timing signal generator  11  through the second timing selector  12   b , the second formatter  23  selects timing signals from the received timing signals, under the control of the controller  27 , so as to generate a test signal on the basis of the test pattern sent from the second pattern selector  21  according to the selected timing signals.  
         [0064]    When the first formatter  22  generates the test signal, the first pin electronic circuit  24  amplifies and processes the test signal to output it to a pin  1  of a semiconductor IC circuit. When the second formatter  23  generates the test signal, the second pin electronic circuit  25  amplifies and processes the test signal to output it to a pin  2  of a semiconductor IC circuit.  
         [0065]    In mode  3 , it is impossible to use all the timing signals TS 1 -TS 6  in generating a test signal, namely a test signal is generated using the timing signals TS 1 -TS 3  or the timing signals TS 4 -TS 6 . However, it is possible to output different wave form timing signals for outputting to pins  1 ,  2 , without using two set of timing generators  11 .  
         [0066]    As explained, according to the tester for testing a semiconductor IC circuit having multiple pins of the embodiment 1, the timing signal generator  11  is commonly used by the first and second formatter  22 ,  23 , and the timing signal generator can supply timing signals to both of or either of the first and second formatters  22 ,  23 . Thus, it is possible to provide cheaply a tester for common use, by suppressing the augmentation of the size of the tester circuit, which may increase according to the number of the pins of a semiconductor IC circuit.  
         [0067]    Furthermore, the first and second memories  18 ,  19  can be effectively used, because they can be used as one sequential memory, when the first and second timing selectors  12   a ,  12   b  output timing signals to one of the first and second formatter  22 ,  23 , and they can be used as two separated memories, when the first and second timing selectors  12   a ,  12   b  output timing signals to both of the first and second formatters  22 ,  23 .  
       Embodiment 2  
       [0068]    The tester for testing a semiconductor IC circuit having multiple pins according to the embodiment 1 is a tester, which generates test signals for two input pins of a semiconductor IC circuit. However, the scope of the present invention is not limited to such a tester. The tester for testing a semiconductor IC circuit having multiple pins according to the present invention can be constructed so as to output test signals for more than two input pins of a semiconductor circuit.  
         [0069]    For example, a tester for testing a semiconductor IC circuit having multiple pins, which generates test signals for three input pins of a semiconductor IC circuit, has a third pattern address controller, a third pattern memory, a third formatter, a third pin electronic circuit and necessary delay circuits in addition to the components shown in FIG. 2. But it is necessary only one timing signal generator  11 .  
       Embodiment 3  
       [0070]    The tester for testing a semiconductor IC circuit having multiple pins according to the embodiment  1  is a tester, in which the first timing selector  12   a  outputs the timing signals TS 1 -TS 3  to the first formatter  22 , and the second timing selector  12   b  outputs the timing signals TS 4 -TS 6  to the second formatter  23 . However, the scope of the present invention is not limited to such a tester. For example, it is possible that the first timing selector  12   a  outputs the timing signals TS 1 -TS 2  to the first formatter  22 , and the second timing selector  12   b  outputs the timing signals TS 3 -TS 6  to the second formatter  23 . Of course, further another combination of the timing signals is possible.  
         [0071]    The tester for testing a semiconductor IC circuit having multiple pins according to the embodiment 1 is a tester, in which the timing signal generator  11  generates six timing signals TS 1 -TS 6 . However, the scope of the present invention is not limited to such a tester. For example, it is possible that the timing signal generator  11  generates seven or more than seven timing signals.  
         [0072]    In the explanations of the embodiments of the present invention, the input pins of a semiconductor IC circuit were supposed to be pins  1 ,  2 . These pins are no more than examples of pins. Of course, the other pins can be input pins of the semiconductor IC circuit.