Abstract:
A multi-slope analog-to-digital converter avoids the dielectric absorption problem by providing a predetermined number of risings and fallings of the output of an integrator integrating an input analog signal during a first predetermined period of time, each falling corresponding to the simultaneous integration of a first reference signal during the first integration period. Subsequently the first reference signal is integrated for a time period to assure that the output signal of the integrator has a predetermined polarity, prior to completing the measurement of the input analog signal during further integration periods. Variations in the number of switching delays, and variations depending upon the direction with which the output of the integrator approaches a reference level, may thus be avoided.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a multi-slope integrating analog-to-digital converter which integrates input analog signals during a first integration period, during which a first reference signal of opposite polarity to the input signal is integrated repeatedly together with the input analog signal so as to cause a predetermined number of cycles of rising and falling at the integrator output, after which a second reference signal and a third reference signal are integrated during respective second and third integration periods, to obtain a digital signal corresponding to an input analog signal by measuring the time intervals of the first reference signal being integrated and the second and third integration periods. 
     A dual-slope type integrating analog-to-digital converter is well known in the art. In such an analog-to-digital converter, an input signal is provided to an integrator and is integrated during the first integration period T 1 , resulting in a rising slope being output from the integrator as shown in FIG. 1. At the end of the first integration period T 1 , a reference signal of opposite polarity to the input signal is provided to the integrator so as to cause a falling slope at the integrator output. As illustrated in FIG. 1, a second integration period T x  begins at a time when the reference signal integration starts, and ends at the time when the integrated signal reaches a predetermined voltage level, for example, the voltage level at the beginning of the integration, which is typically provided to be ground potential. 
     When the input analog signal is small, the integrated output at the end of the first integration period T 1  is small because the first integration period is fixed, and thus the second integration period T x  becomes short as shown by the broken line in FIG. 1. In other words, the second integration period T x  depends on the voltage level of the input analog signal. The second integration period T x  is measured for example by a counter, and accordingly the measured digital data corresponds to the value of the input analog signal. 
     A prior art triple-slope analog-to-digital converter is described in U.S. Pat. No. 3,577,140, in which an input signal to be measured is integrated for a fixed period, and then the integrated value is down-counted to a predetermined level while applying a reference signal, followed by completing the down-counting into a less significant digit while applying a smaller reference signal. U.S. Pat. No. 4,354,176 describes an analog-to-digital converter that for instance avoids inaccuracies due to reaching said predetermined level during the middle of a clock pulse. 
     In such known analog-to-digital converters, a voltage supplied across an integrating capacitor increases when the input analog voltage increases, resulting in the so-called dielectric absorption problem. The dielectric absorption problem concerns a degrading of the linearity of the voltage charged in the integrating capacitor when a high voltage is supplied to the integrator. Thus analog to digital conversion with high accuracy is difficult with this prior art. 
     For solving this problem, a multi-slope integrating analog-to-digital converter is known, for instance as described at page 9 of the Hewlett-Packard Journal of February 1977. FIG. 2A is a block diagram of such a prior art example of a multi-slope analog to digital converter, and FIG. 2B is a voltage-time diagram of the multi-slope analog-to-digital converter of FIG. 2A. According to this multi-slope analog-to-digital converter, within the first integration period T 1  a first reference signal, of opposite polarity to the input analog signal and of greater absolute value than the maximum input analog signal to be measured, is applied to the integrator 14 each time the integrator signal reaches a predetermined voltage V 1 . The comparator 24T in FIG. 2A is used for sensing the integrated signal crossing the voltage level V 1 . 
     Thus the output from the integrator 14 begins to fall as in FIG. 2B and, after the fixed time interval T 3 , the first reference signal is stopped from supplying the integrator 14 in order to integrate the input signal alone. The integrated signal again begins to rise and, when it reaches the predetermined voltage V 1  again, the first reference signal is again integrated together with the input signal during the subsequent fixed period T 3 . 
     This process is repeated during the first integration period T 1 , and, after the first integration period T 1 , the second reference signal I 2 , of opposite polarity from the integrated signal at the end of the first integration period T 1 , is provided to the integrator 14 so that the second integration T x  begins. The second integration period T x  ends when the integrated signal crosses the predetermined voltage level in the same way as the dual-slope analog-to-digital converter. For the T x  and the T 3  periods, digital signals are obtained for providing a digital value corresponding to the input analog signal. 
     According to this prior art multi-slope integrating analog-to-digital converter, since the integrating capacitor is not supplied with a voltage higher than V 1 , the linearity error originating from the dielectric absorption problem does not occur. However, when the input analog signal is small, the number of times the fixed integration period T 3  occurs within the first integration period is reduced, as shown by the broken line in FIG. 2B. Because the slope of the integrated output is lower, it takes a longer time to get to the voltage V 1 , and conversely, when the input analog signal is increased, the number of times of the period T 3  occurs is also increased. Therefore, according to the voltage level of the input analog signal, there is a variation in the number of times the integration period T 3  occurs, that is, during which both the input signal and the first reference signal are integrated. 
     The first reference signal I 1  is provided to the integrator 14 through a switch 17 as illustrated in FIG. 2A, and the switch 17 has a delay time when it is closed or opened by a control signal, and thus an error caused by these delay times is included in the time period T 3 . It is possible to compensate for this error if it is always the same. However, the error varies in accordance with the level of the input analog signal, since the number of times the switching operation occurs depends on the voltage level of the input signals. Accordingly, compensation for the error caused by this switching delay time is not feasible in this prior art multi-slope integrating analog-to-digital converter. This error is especially damaging in high speed analog-to-digital conversion. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a multi-slope, integrating, analog-to-digital converter which is capable of compensating for errors caused by the delay time of a switch by making constant the number of times the output of an integrator rises and falls within the first integration period. 
     It is another object of the present invention to provide a multi-slope analog-to-digital converter which is capable of converting an input analog signal to a corresponding digital signal with high speed. 
     It is a further object of the present invention to provide a multi-slope, integrating, analog-to-digital converter which is capable of improved resolution by employing a third integration. 
     It is another object of the present invention to provide a multi-slope analog-to-digital converter which is capable of high accuracy by sensing a threshold level of the integrated signal with the integrated signal approaching the threshold level from the same direction and with the same slope regardless of the polarity of the voltage of the input analog signal. 
     According to the present invention, the number of times an integration period occurs during which both the input signal and the reference signal are simultaneously integrated is fixed, that is, the number of times the output of the integrator rises and falls during the first integration period is always the same. More specifically, the switching operation, by which the reference signal is provided to the integrator while the input analog signal is being integrated, is performed a fixed number of times. Since the error caused by the switching time may therefore be made constant, it is possible to compensate for this error. 
     As mentioned before, the error caused by the switching time is especially harmful in high speed analog-to-digital conversion, and thus the cancellation of the error makes it possible for a multi-slope analog-to-digital converter to operate at high speed. 
     In this invention a third integration may also be employed for increasing resolution. During the third integration a reference signal of less magnitude than the other reference signal is integrated so as to generate a gentle slope at the integrator output so that the integration time is increased, thereby increasing resolution. Since the third integration is operated for a lower bit digital signal, it is possible to operate this multi-slope analog-to-digital converter without sacrificing conversion speed. 
     Further, in the present invention, an error caused by the comparator which detects the ending time of each integration period may be eliminated for increasing conversion accuracy. In an actual comparator circuit the detecting speed is different between the case in which the integrated signal to be detected is changing from a higher voltage than the reference level toward a lower voltage, as compared to changing from a lower voltage than the reference level toward a higher voltage. In this invention, after the first integration period, a reference signal is provided to the integrator to make the output from the integrator go to a specific predetermined polarity regardless of the polarity or magnitude of the input analog signal. Accordingly, the integrated signal after the first integration period may be used to approach the reference signal level from a predetermined direction, for all input signals at all times, and thus error caused by differences in sensing speed of the comparator may be eliminated and accuracy increased. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a voltage-time diagram of a dual-slope analog-to-digital converter. 
     FIG. 2A is a block diagram of one example of a prior art multi-slope analog-to-digital converter. 
     FIG. 2B is a voltage-time diagram of the prior art multi-slope analog-to-digital converter of FIG. 2A. 
     FIG. 3 is a block diagram of a multi-slope, integrating analog-to-digital converter in accordance with a preferred embodiment of the present invention. 
     FIG. 4 shows waveforms A to L illustrating the operation of the multi-slope, integration, analog-to-digital converter of FIG. 3. 
     FIG. 5 is a suitable gate signal generator circuit used in the embodiment of FIG. 3. 
     FIG. 6 shows suitable reference current source circuits and switching circuits which may be used in the embodiment of FIG. 3. 
     FIG. 7 is an example of a counter circuit suitable to be employed in the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 shows a preferred embodiment of the present invention. An input analog voltage V x  at the input terminal 11 is converted to a corresponding analog current by a voltage-to-current converter 12. The converted analog current is provided to an integrator 14 through a switch 13 which is controlled by a signal from a switch drive circuit 44. The integrator 14 is comprised, for example, of an operational amplifier 15 and an integrating capacitor 16 which is connected between the output and the inverting input of the operational amplifier 15. 
     Each current source 21, 22, 23 generates a corresponding reference current I 1 , I 2 , I 3  and provides the reference current to the integrator 14. The output of the integration is compared with a predetermined reference level such as ground potential by the comparator 24. The output of the comparator 24 is connected to a gate signal generator 25 which generates gate signals at terminals 26, 27, 28. The gate signals from terminals 26, 27, 28 respectively control the switches 17, 18, 19 through a switch drive circuit 29. 
     The gate signals are also provided to the NAND gate 32 via an OR gate 31, to control the NAND gate 32 to selectively gate clock signals from a clock signal generator 33. The gated clock signals are provided from the NAND gate 32 to a counter 34 wherein the clock signals (inverted in this case) are counted for measuring integration times. 
     The counted data is provided to a data bus 37 via a buffer 35 and is stored in a random-access memory 38 under the control of a central processor unit CPU 36. The CPU 36 works according to a program stored in a read-only memory 39 and, as a result of the program, address data is provided to an address decoder 42 through an address bus 41. The CPU 36 controls the operation in this embodiment and calculates a digital signal from the data stored in the random access memory 38. The decoded data from the address decoder 42 is provided to a control signal generator 43, whereby control signals such as a reset signal, period signals, etc. are generated. 
     The waveforms A to L of FIG. 4 illustrate the operation of the embodiment shown in FIG. 3. In this embodiment several integration periods are employed. The first integration time period T 1  may be fixed, and the integrated value is shown by the solid line of waveform A. Various ones of the time periods, reference currents and reference levels may be adjusted in a predetermined manner depending on the magnitude and polarity of the input analog signals. 
     The clock signals P 1 , P 2 , P 3  generated by the clock signal generator 33 are illustrated by waveforms C, D and E respectively. The gate signals at terminal 26, 27, 28 of the gate signal generator 25 are shown by waveforms I, J and K respectively. Further, the control signals generated by the control signal generator 43 are illustrated by waveforms F, G and H respectively. 
     At the beginning of the analog-to-digital conversion, the switch 13 is closed so that the input analog voltage is applied to the integrator 14 after being converted to a corresponding current by the voltage-to-current converter 12. The input analog signal and the reference signals supplied to the integrator 14 may be in the form of current, not voltage, so as to suppress errors caused by internal resistance of the switches 13, 17, 18, 19. 
     The input analog signal thus provided is integrated by the integrator 14 all the time during the first integration period T 1 . An output from the integrator 14 begins to rise linearly at time t 0  as shown by waveform A of FIG. 4. 
     At time t 1  the switch 17 is closed by the gate signal shown by waveform I, so as to provide the first reference current I 1  from the current source 21 to the integrator 14. The gate signal of waveform I is changed to high level by the falling edge of the clock signal P 3  of waveform E. While the gate signal of waveform I, that is, the gate signal from the terminal 26 of the gate signal generator 25, is at a high level, both the input analog signal and the first reference current I 1  are integrated. The first reference current I 1  is provided to be sufficiently large in magnitude as compared with the maximum input signal to be dealt with, in this embodiment, so that the integration signal begins to fall at time t 1 . 
     When the integrated signal reaches the reference level within the time interval T 3  of the clock signal P 2  shown by waveform D of FIG. 4, the comparator 24 changes its state from high level to low level at time t 2 , and by the first falling edge of the clock signal P 1  immediately after t 2 , that is at time t 3 , the gate signal of waveform I is changed to low level and thus the switch 17 is opened. If the integrated signal still remains above the reference level at the end of each interval T 3 , as shown in the case of the dashed line of waveform A, the comparator keeps its high level until the clock signal P 2  of waveform D changes its state and the switch is opened by the falling edge of the clock signal P 2 , that is, in synchronism with the end of the interval T 3 . 
     In either case the output from the integrator 14 is increased after opening the switch 17 and attains a higher voltage than the reference level. 
     Further in this embodiment, at times t 5  and t 9  the switch 17 is closed again so that both the input signal and the first reference current I 1  are simultaneously integrated, and thus the integrated output signal starts to fall again each time. When the comparator 24 changes its state within the period T 3  of the clock signal P 2 , for instance at time t 6  or t 10 , the switch 17 is opened in synchronism with the falling edge of the clock signal P 1  immeditely following t 6  or t 10  by the gate signal of waveform I of FIG. 4. Again, if the comparator 24 remains in its high state at the end of the period T 3  as shown by the broken line of waveform A, the switch 17 is opened in synchronism with the end of the period T 3 , that is at time t 8  or t 12 . At time t 12  the period signal T 1  from the control signal generator 43 is changed to low state as shown by waveform F in FIG. 4, and the switch 13 is opened and thus the first integration period T 1  comes to an end. 
     Since the number of times that the rising and falling of the output of the integrator 14 occurs during the first integration period T 1  is determined by the clock signal P 2 , and not by the level of the input analog signal, this number of times is always the same regardless of the input signal. Thus the error caused by the switching time of the switch 17 is fixed and can be eliminated. 
     The gate signal at the terminal 26 of the gate signal generator, shown by waveform I in FIG. 4, is also provided to the NAND gate 32 through the OR gate 31 to open the NAND gate 32 during its high level. Thus the clock signal P 1  from the clock signal generator 33 is provided to the counter 34, whereby the clock signals are counted. The counter 34 is initially reset by the reset signal from the control signal generator 34 at the beginning of the analog-to-digital conversion, as shown by waveform L of FIG. 4. During the occurrence of the high level of the gate signal from the terminal 26, the counter 34 counts the number of pulses of the clock pulse P 1  supplied during each of the periods T x1  (which begins at t 1  and ends at T 3 ), T x2  (which begins at t 5  and ends at t 7 ) and T x3  (which begins at t 9  and ends at t 11 ). 
     The conversion operation after the first integration period T 1  is as follows. After the first integration period T 1 , the period signals shown in FIG. 4 by waveforms G and H are supplied to the gate signal generator 25 from the control signal generator 43 control. During the period T 5  of the period signal shown in FIG. 4 by waveform G both the switch 13 and the switch 17 are opened so that no signal is applied to the generator. The reason for providing the period T 5  in this embodiment is to obtain enough time for opening the switch 17 as in the case of the integrated signal shown with the broken line of waveform A of FIG. 4, so that the number of times of the switching operation of the switch 17 is made equal for all input signals. 
     In synchronism with the end of the period T 5 , the period T 6  starts as shown by waveform H, and, by the rising edge of the period signal T 6 , the gate signal of waveform I is changed to high level. Accordingly, the switch 17 is closed again so as to supply the reference current I 1  from the current source 21 to the integrator 14 during the period T 6 . 
     As mentioned before, the polarity of the slope of the integrated output signal during the second and third integration periods T x4  and T x5  may be fixed for eliminating the error caused by the detection speed of the comparator 24. Thus the period of time T 6  is suitably selected to allow the integrated output signal to assure a specific polarity, in this embodiment a negative voltage, at the beginning of the second integration period T x4  regardless of the value of the input analog signal. Thus, during the period T 6  the output from the integrator 14 falls to a negative value as shown by the solid line of waveform A in FIG. 4, and during the period T 6  the clock signal P 1  is provided to the counter 34. The total count of time in the counter 34 then corresponds to the time period T x1  +T x2  +T x3  +T 6 , and this data is stored in the random access memory 38 during the period T 7 . 
     After the period T 6 , the counter 34 is reset by the reset signal generated by the control signal generator 43. By the falling edge of the period signal T 7  the gate signal at terminal 27 of the gate signal generator 25 changes to high level as shown by waveforms J in FIG. 4, and thus the switch 18 is closed so as to provide the second reference current I 2  from the current source 22 to the integrator 14. As a result, the second integration T x4  begins and, since the reference current I 2  is provided with opposite polarity than that of the reference current I 1 , the output from the integrator 14 starts to rise at time t 14  as shown by the solid line of waveform A in FIG. 4. 
     The gate signal from the terminal 27 of the gate signal generator 25 is also supplied to the NAND gate 32 via the OR gate 31, so that the counter 34 counts the clock signals P 1  during the second integration period Tx 4 . When the integration signal crosses the reference level at time t 15  the comparator 24 is changed to high level, and by the falling edge of the clock signal P 1  immediately following t 15 , that is at time t 16 , the gate signal from the terminal 27 is changed to low level so that the switch 18 is opened and the NAND gate 32 is closed. The data counted by the counter 34, corresponding to the second integration period T x4  (which begins at t 14  and ends at t 16 ), is stored in the random access memory 38 and after that the counter 34 is reset by the reset signal as shown by waveform L in FIG. 4. 
     In this embodiment the third integration may be employed so as to acquire higher resolution. In the third integration the third reference current I 3  which has less magnitude than the second reference current I 2  is supplied to the integrator 14 so as to make less steep the slope of the output of the integrator 14, and thus the number of clock pluses counted by the counter 34 during the time period T x5  is increased. At time t 17 , with the falling edge of the clock signal P 1 , the gate signal generated at the terminal 28 of the gate signal generator 25 is changed to high level so as to close the switch 19 and to open the NAND gate 32. Therefore the third reference current I 3  is provided to the integrator 14 from the current source 23 and the third integration period T x5  begins as shown by the solid line of waveform A of FIG. 4. 
     When the integrated signal reaches the reference level at time t 18 , the comparator 24 changes its state from high level to low level. By the falling slope at t 19  of the clock signal P 1  immediately after t 18 , the gate signal at terminal 28 is changed to low level as in waveform K of FIG. 4. During the third integration period T x5  (which begins at t 17  and ends at t 18 ) the clock signals P 1  are counted by the counter 34 and the counted data is stored in the random access memory 38. 
     For obtaining the relationship between the input analog signal and the stored data in the random access memory 38, a description is now made in terms of the charges stored in the capacitor 16 of the integrator 14, wherein: 
     Q 1  is a charge caused by the input analog signal during the first integration period T 1  ; 
     Q x1 , Q x2 , Q x3  are the opposite polarity charges, that is, the discharges caused by the first reference current I 1  during the periods T x1 , T x2 , T x3  respectively; 
     Q 6  is the discharge caused by the first reference current I 1  during the period T 6  ; 
     Q 5  is also a discharge value brought about by the third reference current I 3  during the third integration period T x5  ; and 
     Q x4  is the charge caused by the second reference current I 2  during the second integration period T x4 . 
     At the end of the third integration period T x5 , since the output voltage from the integrator 14 is zero, the charge stored in the integrating capacitor 16 is also zero. Thus the following relation exists among the charges and discharges indicated above. 
     
         Q.sub.1 +Q.sub.x4 =Q.sub.x1 +Q.sub.x2 +Q.sub.x3 +Q.sub.6 +Q.sub.x5 (1) 
    
     In one embodiment of the present invention the reference currents may be selected as follows. The magnitude of a reference current I r  may be supplied as I 1  =I r , the reference current I 2  may be set to I r  /10 and the reference current I 3  may be set to I r  /1000. Since the charge Q is the product of current I and time T, that is Q=IT, equation (1) may then be used to derive a value for the input analog signal, wherein I i  is the corresponding input current: ##EQU1## Since the magnitudes of the reference current I r  and the first integration period T 1  are known, and since the periods of time T x1 , T x2 , T x3 , T 6 , T x4 , T x5  are measured by the counter 34 and stored in the random access memory 38, the analog-to-digital conversion is accomplished according to the equation (2) as calculated by the CPU 36. 
     The gate signal generator 25 may be constituted as illustrated in FIG. 5. The clock signals P 1 , P 2 , P 3  shown by waveforms C, D, E in FIG. 4 are supplied at terminals 45, 46, 47, waveform B in FIG. 4 is provided to the terminal 48. Also, the period signals T 1 , T 5 , T 7 , T 6  generated by the control signal generator 43 as indicated by waveforms F, G, H are supplied at terminals 49, 51, 52. The output signal from the comparator 24 at terminal 48 is provided to the J inputs of the JK flip-flops 53, 54, 57 and to the K input of the JK flip-flop 55, and thru the respective illustrated inverters to the K inputs of the JK flip-flops 53, 54, 57 and to the J input of the JK flip-flop 55. 
     The clock signal P 1  at terminal 45 is provided to an AND gate 56 and also to clock terminals CK of the JK flip-flops 54, 55, 58. The period signal T 1  is supplied from the terminal 49 to the other input of the AND gate 56, and the output signal from the AND gate 56 is given to the clock terminal CK of the JK flip-flop 53. The Q output of the flip-flop 53 is input to the AND gate 59 whose other input is provided with the clock signal P 3  from the terminal 47. The output of the AND gate 59 is connected to the clock terminal of the flip-flop 57 whose clear terminal is supplied with the clock signal P 2  from the terminal 46. 
     At time t 0 , since both the output from the comparator 24 and the period signal T 1  are changed to high level, the AND gate 56 is opened so as to provide the clock signals P 1  to the flip-flop 53, and thus the output Q of the flip-flop 53 goes to high level. The flip-flop 57 is at low level because of the low level of the clock signal P 2  supplied at the clear terminal. 
     At time t 1  the clock signal P 2  goes to high level and the clock signal P 3  is applied to the flip-flop 57 through the AND gate 59, and, by the falling edge of the clock pulse P 3 , the flip-flop 57 is changed to high level since both the J and K terminals are at high level. When the output from the comparator 24 is changed to low level at time t 2 , the Q output of the flip-flop 53 is changed to low level by the falling edge of the clock signal P 1  at time t 3 , as illustrated by waveforms A, B and C in FIG. 4. Thus the output of the AND gate 59 becomes low level and the flip-flop 57 goes to low level because of the low level of the signal from the comparator 24. The Q output from the flip-flop 57 is provided at terminal 26 through an OR gate 61 whose other input is supplied with the period signal T 6  from the terminal 52. 
     As has been described above, the gate signal of waveform I in FIG. 4 is obtained at the terminal 26. The period signals T 1 , T 5 , T 6  and T 7  are provided to a NOR gate 62 whose output is connected to the clear terminal of the flip-flop 55 so that during each period T 1 , T 5 , T 6 , T 7 , that is during the time interval t 0  to t 14 , the output Q of the flip-flop 55 is at low level. At the end of the period T 7 , the signal at the clear terminal goes to high level and, by the falling edge of the clock signal P 1 , the flip-flop 55 goes to high level because the inverted signal of the output from the comparator 24 is supplied at the input. When the signal from the comparator 24 rises as illustrated by waveform B in FIG. 4 at time t 15 , the flip-flop 55 is changed to low level by the falling edge of the first clock signal P 1  immediately after t 15 . Thus the gate signal of waveform J in FIG. 4 is generated at the terminal 27. 
     The output signal from the flip-flop 55 is also applied to a NOR gate 63 whose other input is the inverted output of the NOR gate 62. Accordingly, after the end of all the periods T 1 , T 5 , T 6 , T 7 , and T x4  the J input of the flip-flop 58 is provided with high level signal from the NOR gate 63 through a delay circuit 64. Since the Q output signal from the flip-flop 58 is at low level and is provided to the clear terminal of the flip-flop 54, the output of the flip-flop 54 is at low level. At time t 16  the falling edge of the gate signal of waveform J of FIG. 4 is provided to the flip-flop 58 with a slight delay caused by the delay circuit 64, and thus the output of the flip-flop 58 is changed to high level by the clock signal P 1  with delay from the time t 16 . 
     Thus the Q output of the flip-flop 54 is changed to high level at time t 17 , since a high level signal from the comparator 24 is provided at both J and K inputs. When the comparator 24 is turned to low level at time t 18 , the flip-flop 54 is changed to low level by the falling edge of the first clock signal P 1  immediately after t 18 . Accordingly, the gate signal shown by waveform K in FIG. 4 is generated at the terminal 28. 
     FIG. 6 is a circuit diagram showing an example of the current sources 21, 22, 23 and of the voltage-to-current converter 12. In this embodiment an input analog voltage of either positive or negative polarity is converted to a corresponding current of a single polarity. For example, an input analog voltage in the range from +15 to -15 V may be converted to a current in the range from 0 to -6 mA, so as to simplify the circuit of the analog-to-digital converter. Although a voltage-to-current converter which generates currents of both polarities can be used in the present invention, the circuit would become complicated because of the necessity of additional reference currents and also of a polarity detection circuit. 
     In FIG. 6, the switch 13 includes two FETs 13 a , 13 b  which are controlled together by the signals from the switch drive circuit 44. The FET 13 b  is OFF and 13 a  is ON during the first integration period T 1 , so that the output of the voltage to the current converter 12 is connected to the integrator 14. Before the period T 1 , the FET 13 b  is turned ON so that the output current from the converter 12 is provided to ground. 
     The current source 21 includes the operational amplifier 67, a FET 68 and a resistor 66, as illustrated in FIG. 6. The reference current I 1  is acquired by converting a positive reference voltage of +9 V, for example, supplied at terminal 65, to a corresponding current. 
     The switch 17 includes a FET 17 a  and a FET 17 b , and is controlled by the gate signal from the terminal 26 of the gate signal generator 24 in the same way as the switch 13. That is, while the gate signal at the terminal 26 is at high level, the FET 17 a  is closed and FET 17 b  is open so as to provide the reference current I 1  to the integrator 14, and otherwise the FET 17 b  is closed and FET 17 a  is opened so as to short the reference current I 1  to ground. 
     The current source 22 includes an operational amplifier 72, a FET 73 and a resistor 71. A negative reference voltage -9 V, for example, supplied at terminal 69, is converted to the reference current I 2 . The resistor 71 is ten times larger than the resistor 66 to provide the reference current I 2  with one tenth the value of the reference current I 1 . 
     The switch 18 includes a FET 18 a  and a FET 18 b , and it works in the same way as the switches 13 and 17. 
     The switch 19 and the current source 23 include common components in this embodiment. A reference voltage, for example +9 V, applied at terminal 74, is converted to the reference current I 3  by the FET 75 and resistors 76, 77. The FET 75 is controlled to close or open by the gate signal provided from the terminal 28 of the gate signal generator 25. If the reference current I 3  is to be 1/1000th of the reference current I 1 , the resistor 77 is selected to be 1000 times larger than resistor 66. 
     When decade up-down counters as illustrated in FIG. 7 are used as the counter 34 of the preferred embodiment of FIG. 3, the random access memory 38 and the calculation of equation (2) by the CPU can be omitted. In FIG. 7 the counter 34 is a five digit counter comprised of the five decade up-down counters 34 1  to 34 5 . The gate signals generated at the terminals 26, 27, 28 of the gate signal generator 25, shown by waveforms I, J, K in FIG. 4, are provided to the NAND GATES 83, 82, 81 respectively. The clock signal P 1  is also supplied to each NAND gate 83, 82, 81 so that the clock signal P 1  is gated by the gate signals supplied from the terminals 26, 27, 28. The gated clock signal from the NAND gate 81 is supplied to the up-count terminal of the counter of the least significant digit 34 1 . The gated clock signal P 1  from the NAND gate 82 is provided to the down-count terminal of the counter 34 3 . The clock signal P 1  from the NAND gate 83 is provided to the up-count terminal of the counter 34 4 . At the end of the third integration period T x5 , the counted data in the counter 34 is latched by register 84. 
     Many variations and extensions of the present invention would be obvious to a skilled worker in the art in light of the present disclosure.