Abstract:
A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to NOR flash memory devices and programming methods for such devices.  
         [0003]     A claim of priority is made to Korean Patent Application No. 2005-68561 filed on Jul. 27, 2005, the subject matter of which is hereby incorporated by reference in its entirety.  
         [0004]     2. Description of Related Art  
         [0005]     Semiconductor memory devices generally store and read data, and may be classified as random access memories (RAMs) and read only memories (ROMs). RAMs are volatile memory devices that lose their stored data when power is interrupted. ROMs are non-volatile memory devices that continuously hold stored data even when power is interrupted. RAMs include dynamic RAM (DRAM) and static RAM (SRAM). ROMs include programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory.  
         [0006]     Flash memories may be classified into two types, NAND and NOR, in accordance with the logical configuration of their constituent memory cells. NOR flash memory devices are characterized by high speed programming and read operations and are commonly used to store application code. As such, NOR flash memory is commonly used in potable host devices such as mobile phones.  
         [0007]     In common conventional form, a flash memory cell is connected between a bitline and a source line and to a wordline. Multiple flash memory cells may be connected to one wordline. Depending on a voltage applied to a given wordline, the connected flash memory cells may be sensed as ON-cell or OFF-cell. The term, “ON-cell” designates a flash memory cell that is turned ON when its corresponding wordline receives a voltage higher than its threshold voltage. In this condition, the flash memory cell allows current to flow. The term “OFF-cell” designates a flash memory cell that is turned OFF when its corresponding wordline receives a voltage lower than its threshold voltage. In this condition, the flash memory cell does not allow current to flow above some incident level.  
         [0008]     Conventional NOR flash memory generally requires that a program verification operation be carried out following a program operation. The program verification operation functionally verifies whether or not the threshold voltage of a flash memory cell has reached a desired level. In addition, the program verification operation determines whether or not the program operation has been successful by applying a program verification voltage to the wordline and sensing current flow (or not) from the flash memory cell.  
         [0009]     The conventional program verification operation is simultaneously performed across a plurality (or block) of memory cells, (e.g., 128 memory cells). However, within a block of programmed memory cells, some memory cells require program verification and some do not. For example, a memory cell may not require program verification if it is in a state lower than another defined state for programmed memory cells, or if the memory cell is a program-passed memory cell.  
         [0010]     If a great many memory cells require program verification, a large amount of current flows in relation to these memory cells. In such cases, the voltage applied to the various connected source lines will increase, and threshold voltages for memory cells within the block of memory cells undergoing program verification may be inadvertently interpreted in an erroneous manner.  
         [0011]     For example, if one assumes the use of memory cells having four programmable states, (“11”, “10”, “01”, and “00”), some memory cells may exist in the “11” state and others in the “01” state within the context of a program verification operation. A large amount of current flowing as a result of the presence of memory cells in the “11” state may increase the voltage apparent on source lines associated with the memory cells in the “01” state, for example.  
       SUMMARY OF THE INVENTION  
       [0012]     Embodiments of the invention provide a NOR flash memory device and a related programming method adapted to prevent the inadvertent elevation of a wordline voltage during a program verification operation, and the resulting negative effects.  
         [0013]     Thus, in one embodiment, a programming method for a NOR flash memory device comprises; programming data in a memory cell, and during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programming data.  
         [0014]     In a related aspect, controlling the supply of current from the sense amplifier to the memory cell is performed only if a program verification operation is indicated for the memory cell. In another aspect, the supply of current from the sense amplifier to the memory cell is cut off if a program verification operation is not indicated for the memory cell.  
         [0015]     The method may further comprise disabling the sense amplifier before performing the program verification operation, and then enabling the sense amplifier during the program verification operation, if a program verification operation is indicated for the memory cell.  
         [0016]     Alternatively, the method may further comprise enabling the sense amplifier before performing the program verification operation, and then disabling the sense amplifier the program verification operation, if a program verification operation is not indicated for the memory cell.  
         [0017]     In another embodiment, the invention provides a programming method for a NOR flash memory device that comprises; programming data in a plurality of memory cells, disabling a plurality of sense amplifiers so as not to supply current to the plurality of memory cells, enabling one of the plurality of sense amplifiers in relation to the value of the programmed data, and performing a program verification operation using the enabled sense amplifier.  
         [0018]     In yet another embodiment, the invention provides a programming method of a NOR flash memory device that comprises; programming data in a plurality of memory cells, enabling a plurality of sense amplifiers so as to supply a current to the plurality of memory cells, disabling one of the plurality of sense amplifiers in relation to the value of the programmed data, and performing a program verification operation using sense amplifiers from the plurality of sense amplifiers other than the disabled one.  
         [0019]     In yet another embodiment, the invention provides a NOR flash memory device that comprises; a memory cell adapted to store programmed data, a data buffer adapted to store the programmed data, and a sense amplifier adapted to sense a state of the memory cell by supplying current to the memory cell, wherein the sense amplifier is further adapted to control the current supplied to the memory cell in accordance with the value of the programmed data during a program verification operation. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The invention is described below in relation to several embodiments illustrated in the accompanying drawings. Throughout the drawings like reference numbers indicate like exemplary elements, components, or steps. In the drawings:  
         [0021]      FIG. 1  is a graph of the distribution profiles of threshold voltages;  
         [0022]      FIG. 2  is a block diagram of a NOR flash memory device according to the present invention;  
         [0023]      FIG. 3  is a block diagram of a NOR flash memory device performing a program verification operation according to an embodiment of the present invention;  
         [0024]      FIG. 4  is a circuit diagram showing an amplifier of  FIG. 3 ;  
         [0025]      FIG. 5  is a circuit diagram showing a latch circuit of  FIG. 3 ;  
         [0026]      FIG. 6  is an exemplary circuit diagram showing an inverter of the latch circuit of  FIG. 5 ;  
         [0027]      FIG. 7  is a timing diagram illustrating an operation of the NOR flash memory device of  FIG. 3 ;  
         [0028]      FIG. 8  is a flowchart illustrating a programming method of a NOR flash memory device according to a first embodiment of the present invention; and  
         [0029]      FIG. 9  is a flowchart illustrating a programming method of a NOR flash memory device according to a second embodiment of the present invention. 
     
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0030]     Exemplary embodiments of the invention are described below with reference to the corresponding drawings. These embodiments are presented as teaching examples. The actual scope of the invention is defined by the claims that follow.  
         [0031]      FIG. 1  is a graph showing a distribution profile for memory cell threshold voltages. An exemplary NOR flash memory device adapted to store multi_bit data is assumed for purposes of this explanation. Various program states for the exemplary NOR flash memory device correspond to the distribution of threshold voltages shown in  FIG. 1 .  
         [0032]     Referring to  FIG. 1 , a memory cell may be placed into one of four states: “11”, “10”, “01”, and “00” using an appropriate threshold voltage. The “11” state in the illustrated example corresponds to an erased memory cell and has the lowest threshold voltage. The “10” state requires a higher threshold voltage than the “11” state. Similarly, the “01” state requires a higher threshold voltage than the “10” state, and the “00” state requires the highest threshold voltage.  
         [0033]     Consistent with conventional practice, a program verification operation functionally verifies whether or not a desired threshold voltage has been programmed with respect to a particular memory cell in view of its intended data state. In one approach, the program verification operation makes this determination by sensing a particular current (hereinafter, referred to as a “cell current”) flowing the memory cell. If the cell current is less than a reference current, the memory cell is identified as “program pass”. In contrast, if the cell current is greater than the reference current, the memory cell is identified as “program fail”. If the memory cell is identified as “program fail”, a program operation must be repeated until the correct threshold voltage for the memory cell is achieved.  
         [0034]     Referring to  FIG. 1 , a verification voltage V 10  is a voltage indicating that the threshold voltage for a programmed memory cell is sufficiently high to properly correspond to the “10” state. Thus, if a memory cell intended to be placed into the “10” state has a threshold voltage less than verification voltage V 10 , the memory cell is identified as “program fail”. However, once the memory cell is identified as “program pass”, (i.e., properly placed in the “10” state), it is inhibited from being reprogrammed during a subsequent program operation. Similarly, a verification voltage V 01  is a voltage indicating that the threshold voltage for a programmed memory cell is sufficiently high to properly correspond to the “01” state (e.g., a voltage greater than that associated with the “10” state), and a verification voltage V 00  is a voltage indicating that the threshold voltage for a programmed memory cell is sufficiently high to properly correspond to the “00” state (e.g., a voltage greater than that associated with the “01” state). These verification voltages may be identified as part of a program operation in relation to a selected wordline.  
         [0035]      FIG. 2  is a block diagram of an exemplary NOR flash memory device well adapted to the benefits of the invention. The NOR flash memory device of  FIG. 2  generally comprises; a memory cell array  10 , a bitline selection circuit  20 , a row decoder  30 , a column decoder  40 , a data input/output circuit  50 , and a controller  140 . For purposes of this explanation, the operation and interoperation of memory cell array  10 , bitline selection circuit  20 , row decoder  30 , and column decoder  40  are assumed to be conventional and a detailed description thereof will not be presented here.  
         [0036]     Referring to  FIG. 2 , data input/output circuit  50  comprises a sense amplifier  100 , a data buffer  130 , and a write driver  150 . During a program operation, data input to data buffer  130  is programmed to a memory cell selected by write driver  150 . During a program verifying operation, the data programmed to the memory cell is output by sense amplifier  100  and data buffer  130 . The operation of data input/output circuit  50  is controlled by controller  140 .  
         [0037]     Referring still to  FIG. 2 , sense amplifier  100  comprises an amplifier  11  and a latch circuit  12 . Amplifier  11  senses and amplifies cell current flowing from the selected memory cell by supplying current to it. During a program verification operation, latch circuit  12  controls current being supplied from amplifier  11  to the memory cell in response to an output signal received from data buffer  130 . An exemplary sense amplifier  100  will be described in some additional detail below.  
         [0038]     During a program verification operation, the illustrated NOR flash memory device controls current being supplied from sense amplifier  100  to the memory cell according to data stored in the data buffer  130 . In other words, if data programmed in the memory cell requires program verification, current is supplied from sense amplifier  100  to the memory cell. If the data programmed in the memory cell does not require program verification, current from sense amplifier  100  is cut off.  
         [0039]      FIG. 3  shows a block diagram of an exemplary NOR flash memory device performing a program verification operation. The illustrated example is drawn to a program verification operation being conducted in relation to the “01” state. Thus, the “01” program verification operation will be carried out after programming “01” data to a selected memory cell (e.g., MC 4  and MC 6 ).  
         [0040]     Referring to the specific example illustrated in  FIG. 3 , the fourth and sixth memory cells (MC 4  and MC 6 ) are memory cells programmed with “01” data (i.e., placed in the “01” state), while the remaining memory cells (MC 1  through MC 3 , MC 5 , MC 7 , and MC 8 ) are assumed to maintain an erase state, (i.e., remain in the “11” state). During the “01” program verification operation, corresponding fourth and sixth amplifier circuits (AMP 4  and AMP 6 ) are enabled, but the remaining of amplifiers (AMP 1  through AMP 3 , AMP 5 , AMP 7  and AMP 8 ) are disabled.  
         [0041]     Referring again to  FIG. 3 , the NOR flash memory device comprises sense amplifier  100  connected between the memory cells and data buffer  130 . Sense amplifier  100  comprises amplifier circuits AMP 1  through AMP 8 , and corresponding latch circuits Latch  1  through Latch  8 . Each combination of sense amplifier and latch circuit is assumed to have the same construction and operation for purposes of this explanation. Thus, a first amplifier circuit  110  (e.g. AMP  1 ) and a first latch circuit  120  (e.g., Latch  1 ) will be described as indicative of the group.  
         [0042]     Memory cell MC 1  is connected between a bitline BL 1  and a source line SL 1 , and is controlled by a wordline voltage (V WL ). Memory cell MC 1  is in an erase state, that is, the “11” state. During the “01” program operation, verification voltage V 01  is supplied to the wordline. As shown in  FIG. 1 , verification voltage V 01  is greater than the threshold voltage of memory cell MC 1  in the “11” state. Accordingly, memory cell MC 1  is turned ON during the “01” verification operation. When the memory cell MC 1  is turned ON, the voltage level apparent on source line SL 1  increases. As such, during the “01” verification operation, the voltage apparent on the respective source lines (SL 4  and SL 6 ) connected to the fourth and sixth memory cells (MC 4  and MC 6 ) will also be increased. If these increased source line voltages are not corrected, the program verification results for the fourth and sixth memory cells (MC 4  and MC 6 ) may be different from the intended program state(s). Namely, the fourth and sixth memory cells (MC 4  and MC 6 ) may be identified as “program pass” before actually reaching a threshold voltage consistent with the “01” state.  
         [0043]     Referring still to  FIG. 3 , sense amplifier  110  supplies current to memory cell MC 1  via bitline BL 1  and senses the state of memory cell MC 1 . Sense amplifier  110  then senses the state of memory cell MC 1  and supplies an output signal (SO 1 ) to latch circuit  120 .  
         [0044]     Latch circuit  120  receives the output signal (SOl) from sense amplifier  110  and an output signal (DL 1 ) from data buffer  130  during the program verification operation, and provides an enable signal (EN 1 ) to sense amplifier  110 . Latch circuit  120  provides the enable signal (EN 1 ) to sense amplifier  110  to control the current being supplied to memory cell MC 1  during the program verification operation.  
         [0045]     Data buffer  130  receives the data (DIN 1  through DIN 8 ) to be programmed to memory cells MC 1  through MC 8  during a program operation. Data buffer  131  provides the output signal (DL 1 ) to latch circuit  120  when data stored in memory cell MC 1  during a program operation requires program verification. Latch circuit  120  provides the enable signal (EN 1 ) to amplifier circuit  110  in response to the output signal (DL 1 ) supplied from data buffer  131 .  
         [0046]     However, during a program verification operation the NOR flash memory device of  FIG. 3 , selectively enables only the fourth and sixth amplifier circuits (AMP 4  and AMP 6 ) connected respectively to the fourth and sixth memory cells (MC 4  and MC 6 ), thereby avoiding the program verification error associated with conventional NOR flash memory devices.  
         [0047]      FIG. 4  is a circuit diagram showing an exemplary amplifier circuit adapted for use as amplifier circuit  110  of  FIG. 3 .  FIGS. 5 and 6  are circuit diagrams showing respective, exemplary latch circuits adapted for use as any one of Latch 1  through Latch 8  of  FIG. 3 . The operation of these exemplary circuits will be described with reference to  FIG. 7 .  
         [0048]     Reference is made to  FIG. 7  with the assumption of a NOR flash memory device comprising amplifier circuit  110  connected between memory cell MC 1  and latch circuit  120 , and adapted to receive a bitline precharge signal (BLPRE) and a bitline discharge signal (BLDIS) from controller  140 . Amplifier circuit  110  is further assumed to comprise a precharge circuit  111 , a discharge circuit  112 , and an amplifier  113 .  
         [0049]     With reference to  FIG. 4 , precharge circuit  111  is connected so as to provide a power voltage (Vcc) to the bit line BL 1  in response to the enable signal (EN 1 ) from latch circuit  120  and bitline precharge signal (BLPRE) from controller  140 . In the illustrated example, precharge circuit  111  comprises a PMOS transistor P 11  and a NAND gate G 11 . NAND gate Gl 1  receives the bitline precharge signal (BLPRE) and the enable signal (EN 1 ), and provides a precharge signal (PRE 1 ) to the gate of PMOS transistor P 11 .  
         [0050]     Discharge circuit  112  is connected between the bitline BL 1  and ground. Discharge circuit  112  discharges charges from the first bit line BL 1  to ground in response to the bitline discharge signal (BLDIS) from controller  140 . In the illustrated example, discharge circuit  112  comprises an NMOS transistor N 11 .  
         [0051]     Amplifier  113  compares cell current received from memory cell MC 1  with a reference current (Vref) in order to sense the state of memory cell MC 1 . The reference voltage (Vref) may be supplied from a reference voltage generator (not shown). In one embodiment, amplifier  113  generates a reference current in response to the received reference voltage.  
         [0052]     The exemplary latch circuit  120  shown in  FIG. 5  comprises a latch  123 , a reset circuit  125 , and a set circuit  126 . Latch  123  may be formed from two inverters  121  and  122  connected between a first node (node 1 ) and a second node (node  2 ). The enable signal (EN 1 ) is generated from the second node (node 2 ) and provided to precharge circuit  111 . (See, e.g.,  FIG. 4 ). Inverter  122  is controlled by a reset signal (RST 1 ) received from reset circuit  125  and a set signal (SET 1 ) received from set circuit  126 . The construction and operation of an exemplary inverter  122  will be described hereafter with reference to  FIG. 6 .  
         [0053]     Reset circuit  125  is connected between the first node (node 1 ) and the ground. Reset circuit  125  resets the first node (node 1 ) in response to a latch signal (DLLAT) received from controller  140 , see  FIG. 4 , and the output signal (DL 1 ) received from data buffer  131 , see  FIG. 3 . In one embodiment, reset circuit  125  comprises an NMOS transistor N 41  and an AND gate G 41 . The AND gate G 41  receives the latch signal (DLLAT) and the output signal (DL 1 ) and generates the reset signal (RST 1 ). The reset signal (RST 1 ) is provided to the gate of NMOS transistor N 41 .  
         [0054]     Set circuit  126  is connected between a power terminal and the first node (node 1 ). Set circuit  126  provides power voltage (Vcc) to the first node (node 1 ) in response to a latch signal (SOLAT) received from controller  140  and an output signal from amplifier  110 . In one embodiment, set circuit  126  comprises a NAND gate G 42  and PMOS transistor P 41 . The NAND gate G 42  receives the latch signal (SOLAT) and the output signal (SO 1 ) to generate a set signal (SET 1 ). The set signal (SET 1 ) is provided to the gate of PMOS transistor P 41 .  
         [0055]      FIG. 6  is a circuit diagram showing an exemplary inverter  122  adapted for use in the latch shown in  FIG. 5 . In the illustrated example, inverter  122  comprises two NMOS transistors, N 51  and N 52 , and two PMOS transistors, P 51  and P 52 . The NMOS transistor N 51  is controlled by the set signal (SET 1 ), and the PMOS transistor P 51  is controlled by the reset signal (RST 1 ).  
         [0056]     When the set signal (SET 1 ) is logically low in the illustrated example, the NMOS transistor N 51  is turned OFF. By so doing, the discharge of a voltage apparent at the first node (node 1 ) may be prevented when the PMOS transistor P 41  is turned ON. When the reset signal (RST 1 ) is logically high, the PMOS transistor P 51  is tuned OFF. By so doing, the voltage apparent at first node (node 1 ) may be kept below a desired threshold when the NMOS transistor N 41  is turned ON.  
         [0057]      FIG. 7  is a timing diagram illustrating the operation of the NOR flash memory device shown in  FIG. 3 . The operation of the NOR flash memory device will be described referring to  FIGS. 3 through 7 .  
         [0058]     In the event that the bitline discharge signal (BLDIS) is provided to the amplifier circuits AMP 1  through AMP 8 , the bit lines BL 1  though BL 8  are discharged to a ground. With discharged bit lines BL 1  through BL 5 , an initial sensing operation is performed. After the initial sensing operation is performed, output signals SO 1  through S 08  from the amplifier circuits AMP 1  though AMP 8  are set to logical high. The reason for doing this is that if the sensing operation is performed under the condition that the bit line is discharged, the memory cell is sensed as “ON-cell”.  
         [0059]     If the latch signal (SOLAT) is activated under the condition that the output signals SO 1  through S 08  of the amplifier circuits AMP 1  through AMP 8  are high, the set signal (SET 1 ) is low. See,  FIG. 5 . The reason for this is that both inputs (SOLAT and SO) of the NAND gate G 42  are high. If the set signal (SET 1 ) is low, the first node (node 1 ) and second node (node 2 ) are both low. In this case, since enable signals EN 1  through EN 8  are low, all amplifier circuits AMP 1  though AMP 8  become disabled. The reason for this is that if the enable signals EN 1  though EN 8  are low, the precharge signals PRE 1  though PRE 8  are high.  
         [0060]     Next, output signals DL 1  though DL 8  are generated in accordance with the intended data values to be stored. If data programmed to the memory cell needs a program verification, a high output signal is generated. In the illustrated example, output signals DL 4  and DL 6  become high, and the remaining output signals DL 1  though DL 3 , DL 7 , and DL 8  are low.  
         [0061]     Subsequently, the latch signal (DLLAT) is applied to the latch circuits Latch  1  though Latch  8 . At this time, the enable signals EN 4  and EN 6  are activated. If the enable signals EN 4  and EN 6  are activated, the precharge signals PRE 4  and PRE 6  become low, and the rest of precharge signals PRE 1  though PRE 8 , PRE 5 , PRE 7 , and PRE 8  are high. Accordingly, a program verification operation is performed with respect to only the fourth and sixth memory cells MC 4  and MC 6 .  
         [0062]      FIG. 8  is a flowchart illustrating an exemplary programming method for a NOR flash memory device according to one embodiment of the invention. According to this method, a program operation is performed (S 110 ), and then a program verification operation is performed.  
         [0063]     Before performing the program verification operation, all sense amplifiers are disabled (S 120 ). The NOR flash memory device performs an initial sensing operation while the bit line is discharged so as to disable all sense amplifiers.  
         [0064]     Subsequently, the sense amplifiers are selectively enabled depending on program data stored in the data buffer (S 130 ). In case that the stored program data needs a program verification, a high output signal DLi is generated. The latch circuit provides an enable signal ENi to the amplifier circuit in response to the high output signal received from the data buffer. The amplifier circuit performs a program verification operation in response to the enable signal (S 140 ).  
         [0065]      FIG. 9  is a flowchart illustrating an exemplary programming method for a NOR flash memory device according to another embodiment of the invention. In accordance with the programming method, a program operation is performed (S 210 ), and then a program verification operation is performed.  
         [0066]     Before performing a program verification operation, all sense amplifiers are enabled (S 220 ). In order to enable all sense amplifiers, the NOR flash memory device performs an initial sensing operation while a bit line is precharged.  
         [0067]     Next, the sense amplifiers are selectively disabled depending on program data stored in the data buffer (S 230 ). If the program data stored in the data buffer does not need a program verification, the data buffer generates a high output signal DLi. The latch circuit provides a disable signal DISi to the amplifier circuit in response to the high output signal received from the data buffer. If the disable signal is applied to the amplifier circuit, the sense amplifier does not perform a program verification operation.  
         [0068]     Next, the NOR flash memory device performs a program verification operation by the sense amplifier being in an enable state (S 240 ).  
         [0069]     According to the NOR flash memory device and a programming method thereof, a program verification operation is accomplished by sense amplifiers that are selectively enabled. In addition, the sense amplifiers requiring a program verification are selectively enabled. Accordingly, it is possible to avoid a program verification error caused by an elevated voltage on a source line during a program verification operation, and correct program verification results may be obtained.  
         [0070]     The foregoing embodiments are merely teaching examples. Those of ordinary skill in the art will understand that various changes in form and detail may be made to the exemplary embodiments without departing from the scope of the present invention as defined by the following claims.