Abstract:
A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 2006-126443, filed on Dec. 12, 2006, the entirety of which is incorporated herein by reference as if set forth in its entirety. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to semiconductor memory devices and, more particularly, to flash memory devices and memory systems that include flash memory devices. 
       BACKGROUND 
       [0003]      FIG. 1  is a diagram illustrating the pin configuration of a standard 48-pin TSOP1 circuit that may be used in a general NAND flash memory device. As shown in  FIG. 1 , the standard 48-pin TSOP1 includes a plurality of control pins such as /WE, ALE, CLE, /CE, /RE, and R/BB, power pins Vcc and Vss, and input/output pins I/O 0 ˜I/O 7 . As is well known, data that is to he programmed into the flash memory device is input through the input/output pins I/O 0 ˜I/O 7  in synchronization with a transition (e.g. a rising edge or a falling edge) of a control signal /WE. Data that is to be read from the flash memory device is output through the input/output pins I/O 0 ˜I/O 7  in synchronization with a transition of the control signal /RE. 
         [0004]    The quantity of data that is input into or output from a NAND flash memory device may increase in proportion to the capacity of the NAND flash memory device. Accordingly, as the capacity of NAND flash memory devices increases, all else being equal, the time required to transfer data between the NAND flash memory device and a flash controller may increase. For example, the time required to transfer data between a flash controller and a NAND flash memory device having a 1 kilobyte page size will be twice the time required to transfer data between a flash controller and a NAND flash memory device having a 512-byte page size. Accordingly, as the capacity of NAND flush memory devices has increased, efforts have been made to reduce the data transmission time between the NAND flash memory device and the flash controller. 
         [0005]    U.S. Patent Publication No. 2006-0023499 entitled “NON-VOLATILE MEMORY DEVICE FOR PERFORMING DDR OPERATION IN DATA OUTPUTTING PROCESS AND DATA OUTPUTTING METHOD OF THE SAME CAPABLE OF OUTPUTTING DATA AT FALLING EDGE AS WELL AS RISING EDGE OF READ CONTROL SIGNAL”, which claims priority from Korean Patent No. 10-0546418, describes one such effort at reducing the data transmission time. In particular, the above-referenced documents describe data transmission techniques in which data is transferred in synchronization with both the rising and falling edges of the control signal /RE. Both the above-referenced U.S. patent publication and the Korean patent from which it claims priority are incorporated herein by reference as if set forth in their entireties. 
         [0006]    According to the above-referenced documents, data read out through a page buffer circuit of a non-volatile memory device is output externally in synchronization with the rising and falling edges of a clock signal (e.g., S_REB) that oscillates in a half cycle of the signal /RE. Such a data output scheme enables data to be rapidly output from the NAND flash memory device to, for example, a flash controller. However, using the signal /RE to generate a clock signal may cause problems. 
         [0007]    In particular, as shown in  FIG. 1 , in the standard 48-pin TSOP1 chip, the signal /RE is supplied through a control pin that is on one side of the chip and data is input and output through the input/output pins I/O 0 ˜I/O 7  that are on the other side of the chip. As shown in  FIG. 2 , the signal /RE that is input to the chip is converted into the clock signal S_REB by a clock generator  10  (the clock generator  10  corresponds to the frequency controller  553  of the forgoing disclosure). The clock signal S_REB is applied to a data buffer circuit  20  that is adjacent to the input/output pins I/O 0 ˜I/O 7 . The data buffer circuit  20  outputs-data in synchronization with the rising and falling edges of the clock signal S_REB. As shown in  FIG. 2 , the signal /RE is transferred to the data buffer circuit  20 , which is on the right side of the chip, from a pin on the left-side of the chip. With this configuration, it may be difficult to maintain a duty ratio of the signal /RE (from which the clock signal S_REB is generated) at a fixed value (e.g., 50%). As a result, setup/hold margins may be different between data output in synchronization with a rising edge of the clock signal S_REB and data output in synchronization with a falling edge of the clock signal S_REB. Thus, it may be difficult to practically implement a NAND flash memory device with a double data rate (DDR) function using the control signal /RE. 
       SUMMARY 
       [0008]    Pursuant to embodiments of the present invention, NAND and other types of flash memory devices that may have improved data transmission speed arc provided, as are memory systems that include such flash memory device. These flash memory devices may also reduced numbers of pins. 
         [0009]    Pursuant to some embodiments of the present invention, the flash memory device may include a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode and a plurality of data input/output pads. A data input/output buffer circuit is also provided, and may be electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit may be configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode. 
         [0010]    In some embodiments, the input for receiving the signal designating the writing operating mode may be an input for a write-enable signal. In such embodiments, the device may further include an input for a read-enable signal, and the data input/output buffer circuit may also be configured to receive data from the memory cell array and output the data through the input/output pads in synchronization with the clock signal that is applied to the clock signal input in response to activation of the read-enable signal. Moreover, in some of these embodiments, the data input/output buffer circuit may be configured to input and output data in synchronization with both rising and falling edges of the clock signal. 
         [0011]    In other embodiments, the input for receiving the signal designating the writing operating mode may be an input for a mode selection signal that indicates one of a reading or writing operating mode. In such embodiments, the data input/output buffer circuit may be further configured to receive data from the memory cell array and output the data through the input/output pads in synchronization with the clock signal that is applied to the clock signal input in response to the mode selection signal designating the reading operating mode. Moreover, in some of these embodiments, the data input/output buffer circuit may be configured to input and output data in synchronization with both rising and falling edges of the clock signal. 
         [0012]    In some embodiments, the clock signal input comprises a clock signal input pad, and this clock signal input pad may be disposed between respective ones of the plurality of data input/output pads. Moreover, the device may further include a first row of pins on a first side of the device and a second row of pins on a second side of the device. In these embodiments, a pin connected to the clock signal input pad and a plurality of pins that are connected to respective ones of the plurality of data input/output pads may each be part of the second row of pins, and the pin connected to the clock signal input pad may be disposed between some of the plurality of pins that are connected to respective ones of the plurality of data input/output pads. 
         [0013]    In sonic embodiments, the data input/output buffer circuit may receive an address and a command in synchronization with a rising or falling edge of the clock signal. In other embodiments, the data input/output buffer circuit may receives addresses in synchronization with both rising and falling edges of the clock signal. Moreover, the device may also include an input for receiving a data rate selection signal that selects one of single and double data rate modes. In such embodiments, when a data rate selection signal indicates the single data rate mode, the data input/output buffer circuit inputs and outputs data in synchronization with a rising or falling edge of the clock signal, and when the data rate selection signal indicates the double data rate mode, the data input/output buffer circuit inputs and outputs data in synchronization with both rising and falling edges of the clock signal. In still other embodiments, the device may also include a mode-register set circuit that is configured to store a data rate selection command that selects one of single and double data rate modes. 
         [0014]    Pursuant to still further embodiments of the present invention, methods of operating a flash memory device that includes a memory cell array and a data input/output buffer circuit that is configured to receive a clock signal at a first input, a signal designating a writing operating mode at a second input, and data that is to be written to the memory cell array at a plurality of data input/output pads arc provided. Pursuant to these methods, data that is to be written to the memory cell array at the plurality of data input/output pads is received in synchronization with the clock signal in response to activation of the signal designating a writing operating mode. In some embodiments of these methods, the signal designating the writing operating mode comprises one of a write-enable signal or a mode selection signal. Moreover, the method may further include receiving data from the memory cell array and outputting the received data through the plurality of data input/output pads in synchronization with the clock signal in response to activation of a signal designating a reading operating mode. The signal designating the reading operating mode may be one of a read-enable signal or a mode selection signal. Additionally, the data may be received in synchronization with both rising and falling edges of the clock signal. The first input may be a first pin that is electrically connected to a clock signal input pad, and this first pin may be disposed between a plurality of pins that are electrically connected to respective ones or the plurality of data input/output pads. 
         [0015]    A further understanding of the nature and advantages of the present invention herein may be realized by reference to the remaining portions of the specification and the attached figures. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0016]    Non-limiting and non-exhaustive embodiments of the present invention will be described with reference to the following figures. In the figures: 
           [0017]      FIG. 1  is a diagram illustrating a pin configuration of a standard 48-pin TSOP1 in a general NAND flash memory device; 
           [0018]      FIG. 2  is a block diagram of the NAND flash memory device shown in  FIG. 1 ; 
           [0019]      FIG. 3  is a block diagram of a flash memory system according to first embodiments of the present invention: 
           [0020]      FIG. 4  is a block diagram schematically illustrating the NAND flash memory device shown in  FIG. 3 ; 
           [0021]      FIGS. 5 and 6  are timing diagrams of reading and writing operations performed by the NAND flash memory device shown in  FIG. 4 ; 
           [0022]      FIG. 7  is a block diagram of a flash memory system according to second embodiments of the present invention; 
           [0023]      FIG. 8  is a block diagram schematically illustrating the NAND flash memory device shown in  FIG. 7 ; 
           [0024]      FIGS. 9 and 10  are timing diagrams of reading and writing operations performed by the NAND flash memory device shown in  FIG. 8 ; 
           [0025]      FIG. 11  is a block diagram of a memory system according to third embodiments of the present invention; 
           [0026]      FIG. 12  is a timing diagram illustrating operation of the NAND flash memory device shown in  FIG. 11 ; 
           [0027]      FIG. 13  is a block diagram illustrating another embodiment of the memory system shown in  FIG. 11 ; 
           [0028]      FIG. 14  is a block diagram of a memory system according to fourth embodiments of the present invention; 
           [0029]      FIG. 15  is a timing diagram illustrating operation of the NAND flash memory device shown in  FIGS. 14 ; and 
           [0030]      FIG. 16  is a block diagram illustrating another embodiment of the memory system shown in  FIG. 14 . 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    Certain embodiments of the present invention will be described below, involving a flash memory device as an example in illustrating certain structural and operational features of the invention. The present invention may, however, be embodied in many different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout the accompanying figures. 
         [0032]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms arc only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second clement could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0033]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (i.e., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.). 
         [0034]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0035]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0036]      FIG. 3  is a block diagram of a flash memory system  1000  according to first embodiments of the present invention. As-shown-in  FIG. 3 , the flash memory system  1000  may include a flash controller  1100  and a NAND flash memory device  1200 . The NAND flash memory device  1200  may be configured to conduct reading/writing operations under the control of the flash controller  1100 . The NAND flash memory device  1200  receives addresses, commands, and data in synchronization with transitions of a clock signal CLK instead of a control signal /WE (i.e., write-enable signal) or a control signal /RE (i.e., read-enable signal). In embodiments of the present invention, the signals /WE and /RE may be used as flag signals to indicate operation modes. For instance, the signal /WE is used as a flag signal for a writing mode, while the signal /RE is used as a flash signal for a reading mode. The NAND flash memory device  1200  according to embodiments of the present invention may be configured to receive and output data in synchronization with rising and falling edges of the clock signal CLK. Addresses or commands may also be input to the NAND flash memory device  1200  in synchronization with rising and falling edges of the clock signal CLK. The flash controller  1100  is likewise configured to receive data from the NAND flash memory device  1200  in synchronization with rising and falling edges of the clock signal CLK. 
         [0037]    In this embodiment, the NAND flash memory device  1200  may communicate with the flash controller  1100  in accordance with an interface protocol for a standard NAND flash memory device. 
         [0038]      FIG. 4  is a block diagram schematically illustrating structural features of the NAND flash memory device shown in  FIG. 3 .  FIGS. 5 and 6  are timing diagrams illustrating the timing of reading and writing operations performed by the NAND flash memory device  1200  of  FIG. 4 . Other configurations of the NAND flash memory device  1200  may be arranged in a typical structure as well known by those skilled in this art. 
         [0039]    As shown in  FIG. 4 , the clock signal CLK provided from the flash controller  1100  is applied to an input/output buffer circuit  1220  by way of pad/pin (i.e., a pad and/or pin or other input terminal) that is adjacent to the input/output pads/pins I/O 0 ˜I/O 7 : The pad/pin to which the clock signal CLK is input may, for example, be one of the non-bonded pads/pins (e.g., 25˜28, 33˜35, 38˜40, or 45˜48) when a 48-pin TSOP1 is used. The pad/pin supplied with the clock signal CLK may be assigned to a non-bonded pad/pin that is located very close to the input/output pins I/O 0 ˜I/O 7 . As such, the transmission path of the clock signal CLK to the data input/output buffer circuit  1220  is short, and thus the duty ratio of the clock signal CLK applied to the data input/output buffer circuit  1220  can generally be maintained at a predetermined value (e.g., 50%). When this is the case, the setup/hold margins between data output in synchronization with a rising edge of the clock signal CLK and data output in synchronization with a falling edge of the clock signal CLK may be approximately the same. Consequently, a NAND flash memory device with a double data rate (DDR) function may be provided using the clock signal CLK. 
         [0040]    Referring still to  FIG. 4 , the signals /RE and /WE, as flag signals for indicating operation modes, arc transferred to the data input/output buffer circuit  1220  by way of their corresponding pads. For example, the signal /RE may be transferred to the data input/output buffer circuit  1220  as the flag signal F_DOUT which indicates the reading operation mode. As shown in  FIG. 5 , the data input/output buffer circuit  1220  outputs data from memory core  1240  (i.e., a memory cell array of the device) in synchronization with rising and falling edges of the clock signal CLK during the active period of the flag signal F_DOUT. The signal /WE may similarly be transferred to the data input/output buffer circuit  1220  as the flag signal F_DIN for indicating the writing operation mode. As shown in  FIG. 6 , the data input/output buffer circuit  1220  receives data from an external source in synchronization with rising and falling edges of the clock signal CLK during the active period of the flag signal F_DIN, and outputs the input data to the memory core  1240 . 
         [0041]      FIG. 7  is a block diagram of a flash memory system according to second embodiments of the present invention. As shown in  FIG. 7 , the flash memory system  2000  according to the second embodiments of the present invention includes a flash controller  2100  and a NAND flash memory device  2200 . The NAND flash memory device  2200  may be configured to conduct reading/writing operations under the control of the flash controller  2100 . The NAND flash memory device  2200  receives addresses, commands, and data in synchronization with transitions of a clock signal CLK, as is the case with respect to the NAND flash memory device  1200  shown in  FIG. 3 . Thus, the NAND flash memory device  2200  may be configured to receive and output data in synchronization with rising and falling edges of the clock signal CLK. Addresses or commands may also be input to the NAND flash memory device  2200  in synchronization with rising and falling edges of the clock signal CLK. The flash controller  2100  is configured to receive data from the NAND flash memory device  2200  in synchronization with rising and falling edges of the clock signal CLK. 
         [0042]    In the NAND flash memory device  2200 , a mode selection signal M_SEL may be used as a flag signal for indicating the operation mode instead of the signals /WE and /RE. For instance, the writing operation mode may be enabled when the mode selection signal M_SEL is set to a low level, and the reading operation mode may be enabled when the mode selection signal M_SEL is set to a high level. 
         [0043]    In this embodiment, the NAND flash memory device  2200  may communicate with the flash controller  2100  in accordance with an interface protocol for a standard NAND flash memory device. 
         [0044]      FIG. 8  is a block diagram schematically illustrating structural features of the NAND flash memory device shown in  FIG. 7 .  FIGS. 9 and 10  are timing diagrams illustrating the timing of writing and reading operations by the NAND flash memory device shown in  FIG. 8 . Other configurations of the NAND flash memory device  2200  may be arranged in a typical structure as well known by those skilled in this art. 
         [0045]    As shown in  FIG. 8 , the clock signal CLK provided from the flash controller  2100  is applied to an input/output buffer circuit  2220  by way of pad/pin that is adjacent to input/output pads/pins I/O 0 ˜I/O 7 . The clock signal CLK may be input to, for example, one of the non-bonded pads/pins (e.g., 25˜28, 33˜35, 38˜40, or 45˜48). The pad/pin supplied with the clock signal CLK may be assigned to a non-bonded pad/pin that is located close to the input/output pins I/O 0 ˜I/O 7 . As in the first embodiments of the present invention discussed above, this arrangement of pads/pins facilitates maintaining setup/hold margins on the same level between data output in synchronization with a rising edge of the clock signal CLK and data output in synchronization with a falling edge of the clock signal CLK. 
         [0046]    Referring still to  FIG. 8 , the signal M_SEL, as a flag signal for indicating the operation mode, is transferred to the data input/output buffer circuit  2220  by way of its corresponding pad. For example, if the signal M_SEL that is transferred to the data input/output buffer circuit  2220  has a low level it operates as a flag signal for indicating the writing operation mode, and thus the writing operation begins. Then, the data input/output buffer circuit  2220 , as shown in  FIG. 9 , receives data from an external source in synchronization with rising and falling edges of the clock signal CLK during an active period of the flag signal M_SEL, and outputs the input data to a memory core  2240  (see  FIG. 8 ). On the other hand, if the signal M_SEL that is transferred to the data input/output buffer circuit  2220  has a high level it operates as a flag signal for indicating the reading operation mode, and thus the reading operation begins. Then, the data input/output buffer circuit  2220 , as shown in  FIG. 10 , outputs data from the memory core  2240  in synchronization with rising and falling edges of the clock signal CLK during an active period of the flag signal M_SEL. 
         [0047]      FIG. 11  is a block diagram of a memory system according to third embodiments of the present invention, and  FIG. 12  is a timing diagram illustrating operation of the NAND flash memory device of  FIG. 11 . 
         [0048]    Referring to  FIG. 11 , the memory system  3000  according to the third embodiments of the present invention may include a flash controller  3100  and a NAND flash memory device  3200 . The NAND flash memory device  3200  is similar to the NAND flash memory device  2200  of  FIG. 8 , but is operable in a single data rate (SDR) mode in which data is input/output in synchronization with a rising or falling edge of the clock signal CLK, as well as operable in a double data rate (DDR) mode in which data is input/output in synchronization with both rising and falling edges of the clock signal CLK. These modes may be alternatively enabled by the selection signal SDR/DDR. If the selection signal SDR/DDR indicates the SDR mode, as shown in  FIG. 12 , the NAND flash memory device  3200  receives addresses, commands, and data in synchronization with the rising or falling edges of the clock signal CLK (the rising edge is depicted in  FIG. 12 ). If the selection signal SDR/DDR indicates the DDR mode, as shown in  FIG. 12 , the NAND flash memory device  3200  receives addresses, commands, and data in synchronization with both the rising and failing edges of the clock signal CLK. 
         [0049]    An alternative implementation of the memory system  3000  of  FIG. 11  is depicted in  FIG. 13 . As shown in  FIG. 13 , in this alternative embodiment, the NAND flash memory device is implemented using the signals /RE and /WE (instead of the signal M_SEL) as flag signals for indicating the operation mode. 
         [0050]      FIG. 14  is a block diagram of a memory system according to fourth embodiments of the present invention, and  FIG. 15  is a timing diagram showing operation of the NAND flash memory device of  FIG. 14 . 
         [0051]    Referring  FIG. 14 , the memory system  4000  according to fourth embodiments of the present invention may include a flash controller  4100  and a NAND flash memory device  4200 . The NAND flash memory device  4200  is similar to the NAND flash memory device  2200  of  FIG. 8 , but is different in that it is operable in either the SDR or DDR mode. The mode selected may be alternatively enabled by setting a mode-register set circuit  4220 . In aiming an operation from the SDR mode to the DDR mode, as shown in  FIG. 15 , the mode-register set circuit  4220  is conditioned with a command in correspondence with the DDR mode. Once the mode-register set circuit  4220  is commanded for the DDR mode, the NAND flash memory device  4200  interfaces with the flash controller  4100  in the DDR mode. For instance, if the mode-register set circuit  4220  is conditioned with a command in correspondence with the DDR mode, as shown in  FIG. 15 , the NAND flash memory device  4200  receives addresses, commands, and data in synchronization with both rising and falling edges of the clock signal CLK. 
         [0052]    An alternative implementation of the NAND flash memory device  4200  of  FIG. 14  is depicted in  FIG. 16 . As shown in  FIG. 16 , in this alternative embodiment, the NAND flash memory device  4200 ′ is implemented using the signals /RE and /WE (instead of the signal M_SEL) as flag signals for indicating the operation mode. 
         [0053]    As described above, pursuant to embodiments of the present invention, NAND flash memory devices having a DDR function may be provided using the clock signal CLK instead of the signals IRE and /WE. 
         [0054]    The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.