Abstract:
Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

Description:
This application is a division of application Ser. No. 564,642 filed Dec. 22, 1983, now U.S. Pat. No. 4,595,875. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to circuitry for the detection of shorts or leaky junctions in programmable read only memories (PROMs). 
     2. Description of the Prior Art 
     A programmable read only memory (PROM) is a memory in which information is permanently stored in each memory cell of the memory by a programming process. The programming process is performed by the user after fabrication is complete, in contrast to the programming of ROMS by the manufacturer during the fabrication process. 
     A short or a leaky junction in a PROM cannot be detected by existing design by the manufacturer prior to shipment. Such a short or leaky junction may cause underprogramming, i.e., one or more memory cells may fail to program when the user attempts to program the PROM. Such a short or leaky junction may also cause overprogramming, i.e., when a programming current is applied to a selected memory cell, one or more different cells may be unintentionally programmed. Because the programmming of such PROMS is generally performed by the end user, the manufacturer may become aware of low yields only when the PROM&#39;s are rejected by the user. 
     FIG. 1 illustrates a typical prior art PROM in which the memory includes a rectangular array x ij  of NPN transistors and associated fuses f ij  connected between word lines W j  and bit lines B i  for i=1, . . . ,N; j=1, . . . M. Prior to programming, each memory cell which includes the transistor x ij  and its associated fuse f ij  stores a logical 0, i.e., the fuse f ij  is not open. A leaky base emitter junction of an NPN transistor or a short between a bit line and a word line may result in a fuse which fails to open when a programming current is attempted to be applied to the fuse. A typical titanium-tungsten (TiW) fuse used in many PROMS requires approximately 3 volts across the fuse in order to produce the approximately 50 milliampere (mA) current required to open the fuse. During normal operation (i.e., reading) of the PROMs the maximum supply voltage, (Vcc), is approximately 5.5 volts, and there is not enough voltage across the fuse to cause the 50 mA of current required to open the fuse. 
     Accordingly, one of the steps of the programming procedure is to raise the supply voltage Vcc to approximately 12 volts, well above the levels used during reading the PROM. A memory cell to be programmed containing the array transistor x ij  is selected by selecting the word line W j  and the bit line B i . The selected word line and thus the base of the selected transistor x ij  is at approximately 8 volts, a voltage level determined by internal clamping circuitry (not shown). The remaining deselected word lines are at approximately 1 volt. The base emitter voltage, V BE , of the selected array transistor x ij  at a base emitter current of 50 mA is approximately 1.5 volts. So, the emitter of the array transistor x ij , which is connected to one end of its associated fuse f ij , is at a voltage of approximately 8 volts-1.5 volts=6.5 volts. The programming circuit (not shown) holds the voltage on the selected bit line B i  on the other end of the fuse f ij  at approximately 1.5 volts if the fuse is to open to store a logical one. Therefore, the voltage across the fuse f ij  is approximately 6.5 volts-1.5 volts=5.0 volts which will cause a current greater than 50 mA which will cause the fuse to open, thereby storing a logical one. 
     Conversely, if the fuse f ij  is not to be opened and the cell is to store a logical zero, the bit line B i  is held to approximately 7 volts, so that the voltage drop across the fuse f ij  is insufficient to cause a current which will cause the fuse to open. 
     The array transistor x ij  provides to its associated fuse f ij  a programming current of 50 mA by amplifying the base current supplied to it through transistor x j  (the &#34;word driver&#34;). If an emitter-base (EB) junction of an array transistor x ij  to be programmed is shorted or has a sufficiently large leakage current, or if there is a short between its word line W j  and its bit line B i , the drive current supplied by word driver x j  is not sufficient to provide enough current to cause the fuse to open. 
     On the other hand, a short between the base of an array transistor and its associated bit line may cause unintentional programming of another cell on the same bit line. For example, suppose there is a short between the base of transistor X IM  (Shown in FIG. 1) and bit line B 1 . If word line W 1  is then brought high with the intent of programming transistor x N1 , fuse f 11  may unintentionally be opened by current flowing along the following path: from word line W 1 , through the base emitter junction of transistor x 11 , through fuse f 11  to bit line B 1 , from bit line B 1  through the short between bit line B 1  and the base of transistor x IM , to decode diode D m  *, and from decode diode D m  * through buffer transistor F 1  to ground. This will cause the undesired programming (opening) of fuse f 11 . 
     Prior art PROMs do not contain circuitry to detect the existence of these shorts and therefore since PROMs are typically programmed by the user, defective unprogrammed units may be shipped to the user. This problem does not arise for read-only-memories (ROMs) since these are typically programmed by a mask pattern as a part of the manufacturing process and hence can be tested by the manufacturer prior to shipment. 
     SUMMARY 
     This invention includes fault detection circuitry incorporated into a programmable read only memory so that a selected positive voltage can be applied across each memory cell to allow the detection, prior to programming, of shorts between bit lines and word lines and shorts or leaks in a memory cell. By measuring the current flowing into the bit lines, shorts or leaky junctions within memory cells can be detected in unprogrammed devices prior to shipment by the manufacturer. The fault detection circuitry is isolated from the memory during normal operation of the memory, thereby having no adverse effect on the operation of the device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art memory array using NPN transistors. 
     FIG. 2 shows one embodiment of the short detecting circuitry of this invention in a memory array. 
     FIG. 3 shows the current-voltage (I-V) characteristic curve of the circuit shown in FIG. 2 with no shorts or leakage. 
     FIG. 4 shows the I-V characteristic curve of the circuit shown in FIG. 2 with massive emitter-base (EB) leakage. 
     FIG. 5 shows the I-V characteristic curve of the circuit shown in FIG. 2 with an emitter-base short or a short between a word line and a bit line. 
    
    
     DETAILED DESCRIPTION 
     The following description refers to a memory array including NPN transistors and associated addressing circuitry. It will become readily apparent to those of ordinary skill in the art in light of the teachings of this invention that many other embodiments are possible and the following description is intended to be exemplary and not limiting. 
     FIG. 2 shows a memory array of NPN transistors x ij , i=1, . . . , N, j=1, . . . , M with the emitter of x ij  connected to the bit line B i  through the fuse f ij  for i=1,. . . N; j=1, . . . M and the base of x ij  connected to the word line W j  for i=1, . . . N; j=1, . . . M. 
     The fuses f ij  used in the memory array may be of any convenient type. For example, titanium-tungsten, nickelchromium, doped polycrystalline silicon, metal alloyed polycrystalline silicon, semiconductor junction fuses, and the like, are used in various embodiments. 
     Each bit line B i  is connected to the emitter of a diode connected transistor D i  having an emitter TE i , a collector TC i , and a base TB i  whose collector TC i  and base TB i  are connected to a common terminal T for receiving a test voltage and whose emitter TE i  is connected to the collector of a y-decode transistor Yi, for i=1, . . . N. 
     Each word line W j  is connected to the emitter of an x-decode transistor x j , having an emitter Ex j , a collector Cx j , and a base Bx j  for j=1, . . . , M, and to the anode of decode diode D j  *, for j=1, . . . , M, the cathode of said decode diode being connected to the collector of an output transistor F 1  of an input buffer, the emitter of said output transistor F 1  being connected to ground, and the base of said output transistor F 1  being connected to the remainder of the input buffer circuitry (not shown). 
     A constant current source CS j  is connected across the collector-base junction of each transistor x j  to provide base drive to each transistor x j  for j=1, . . . M. 
     Each base Bx j  is connected to the anode of diode D&#39; j  whose cathode is connected to the cathode of D j  * for j=1, . . . , M. A clamp transistor C i  has its emitter connected to an associated bit line B i  for i=1, . . . N. 
     In one embodiment, a 10K resistor R is connected in series between the terminal T for receiving a test voltage and the anode of diode PD1 whose cathode is connected to the anode of diode PD2 whose cathode is connected to ground. The magnitude of the resistance of the resistor R is selected to appropriately limit the current flowing through diodes PD1 and PD2. 
     In another embodiment, the cathode of diode PD2 is connected to a means S for receiving a second voltage other than ground. 
     In another embodiment, the resistor R alone is connected between the terminal T and a terminal S for receiving a reference voltage. 
     Testing for shorts or leakage in the memory array A shown in FIG. 2 is performed in the following manner. 
     First, the clamp transistors C i  for i=1, . . . N are turned off by raising the voltage on the base of the PNP transistors C i  above the voltage required to turn the transistor on; 
     Next, the NPN Y-decode transistors Y i  for i=1, . . . , N, are turned off by pulling their bases below the voltage required to turn the transistors on, thus preventing any of the bit lines B l  through B N  from being selected; 
     Then, the X-decode is disabled by pulling the voltage on all of the word lines down through the decode diodes D j  * for j=1, . . . , M and the output transistor F 1  of an input buffer (not shown). 
     Next, a test voltage is applied to the terminal T, and 
     Finally, the current flowing into the terminal T is measured and the current flowing from terminal T through the PROM array is calculated. 
     To perform the test for the embodiment shown in FIG. 2, a positive 3 volts is applied by voltage source VS to the terminal T. The presence or absence of a short in one of the transistors x ij  or between a word line and a bit line is determined by the amount of current flowing into the terminal T. 
     For a good memory with no shorts or leakage, current will flow from the terminal only through the 10 K resistor R, and through the diodes PD1 and PD2 to ground. Assuming a 0.8 voltage drop across each of forward biased diodes PD1 and PD2, the value of the current going into the terminal measured at 3 V is: ##EQU1## 
     The I-V characteristic curve for the circuit of FIG. 2 which has no shorts or leakage is shown in FIG. 3, and has a slope equal to the reciprocal of the value of resistor R. Current begins to flow into the terminal T when the voltage applied to T is approximately 1.6 volts, which is the minimum voltage required to turn on the diodes PD 1  and PD 2 . 
     If there is emitter-base (EB) leakage in any transistor x ij  in the array but no EB short nor metal short in the array, current will flow also from terminal T through diode D i , through the EB leak in x ij , through decode diode D j  * and finally through input buffer Fl to ground. The amount of leakage current flowing into the terminal T depends on how many array transistors leak and how much each leaks. A typical I-V characteristic curve for the circuit shown in FIG. 2 which has EB leakage in one or more array transistors x ij  but no EB shorts or metal shorts in the array is shown in FIG. 4. It is similar to FIG. 3, except that the current flowing into terminal T is higher than it should be for a good memory, and the slope of the curve is no longer equal to the reciprocal of the value of resistor R. The slope is equal to (1/R) +(1/R 1 ) where R 1  is the effective resistance of the parallel current path from the terminal T through the leak or leaks to buffer transistor F 1  to ground. Again current begins to flow when the voltage applied to T is approximately 1.6 volts, the minimum voltage required to turn on diode D i  and decode diode D j  * and provide the saturation voltage of transistor F 1  or alternatively the minimum voltage required to turn on diodes PD 1  and PD 2 . This sort of leakage may have an effect on the programming yield and T AA  (address access time). 
     If an EB short or bit line to word line short occurs in the array shown in FIG. 2, current from the terminal T will flow through at least one forward biased diode D i  through the short or shorts, through at least one decode diode D j  * and through input buffer transistor F 1  to ground. The I-V characteristic for the circuit of FIG. 2 in which there is an EB short in an array transistor or a short between a word line and a bit line is shown in FIG. 5. Of importance, the current will be much higher than in either of the two previous cases. This occurs because there is a low resistance path from the terminal T through the short or shorts, and then through F 1  to ground. Again, the slope of the curve is given by 1/R+1/R 1  where R 1  is the effective resistance of the low resistance path. 
     Devices with EB shorts and/or a short between a word line and a bit line will be rejected during the testing phase of production. 
     Devices having excessive EB leakage will also be rejected. Limits for allowable leakage depend on the size of the device, and there will, of course, always be nominal leakage in the PROM array. The ultimate test for allowable leakage is whether the device is programable, which may be established by testing. In a typical PROM containing an array of NPN transistors, a workable first approximation may be to reject dice with leakage of 5 times nominal leakage. 
     It will be clear to one of ordinary skill in the art that various substitutions and modifications may be made in the testing circuitry described herein without departing from the spirit and scope of the invention. In particular, one may modify the circuitry so that memory cells on selected word lines or selected bit lines are tested or so that selected memory cells are tested individually.