Abstract:
A digital data processing system minimizes overall power consumption in a system having embedding large capacity RAMs. Power consumption is reduced by establishing sufficient set-up times when driving plural RAM blocks that have been held in a standby state. A RAM access controller is interposed between an oscillator and the RAM blocks, and controls a master clock generated from the oscillator to secure setup times of the RAM blocks.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention generally relates to digital data processing systems and, more particularly, to digital data processing systems employing a plurality of RAM (Random Access Memory) blocks. 
     2. Description of Related Art 
     Data processing systems usually have storage components such as RAMs (dynamic RAMs (DRAMs) or static RAMs (SRAMs)). The RAMs are installed in a circuit board together with a microprocessor (or a microcontroller) in a digital data processing system. A large capacity RAM is divided into plural blocks of uniform memory capacities for operating at a high clock frequency. 
     Such systems having plural RAM blocks have been employed with an operational mechanism for operating at a high clock frequency in which RAM blocks in a standby state as well as RAM blocks in an operating state are put into a conductive state, to secure the minimum setup times necessary to make the standby RAM blocks operable in an operating state. As a result, there has been unnecessary power consumption in the system due to current through the standby RAM blocks. The rate of power consumption increases as the memory capacity of the RAM is increased. 
     Another conventional way to reduce unnecessary power consumption is to force RAM blocks that are not going to be used in an operation into a standby state. Therefore, setup times are required to operate newly selected RAM blocks in order to switch a memory access routine from the conductive RAM blocks in an operating state to the RAM blocks in a standby state. Securing the setup times is accomplished by controlling an operation speed of a microprocessor for a period of time when a signal for selecting a RAM block is active. Thus, a frequency-divided signal of a master clock provided from an oscillator is applied to the microprocessor. Consequently, the overall speed of a digital data processing system is degraded so that an operation speed of the microprocessor declines when a memory access routine switches from the RAM blocks in an operating state to the RAM blocks in a standby state. 
     SUMMARY OF THE INVENTION 
     To solve the above and other related problems of the prior art, there is provided a digital data processing system having plural RAM blocks. The digital data processing system according to the invention reduces overall power consumption as well as enhances operational efficiency without unnecessary power consumption. 
     According to an aspect of the present invention, there is provided a digital data processing system that comprises an oscillator, a plurality of memory blocks, a processor, and an access controller. The oscillator generates a clock signal with a predetermined frequency. The processor conducts access operations for the memory blocks in response to the clock signal. The access controller inhibits an access operation for a selected one of the plurality of memory blocks when the selected one of the plurality of memory blocks is being setup by the processor. 
     The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein: 
     FIG. 1 is a block diagram of a digital data processing system, according to an illustrative embodiment of the present invention; 
     FIG. 2 is a circuit diagram of a RAM access controller shown in FIG. 1, according to an illustrative embodiment of the present invention; and 
     FIG. 3 is a timing diagram showing an operation of the RAM access controller of FIG. 2, according to an illustrative embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     It should be understood that the description of the preferred embodiment is merely illustrative and that it should not be taken in a limiting sense. In the following detailed description, several specific details are set forth to provide a thorough understanding of the present invention. 
     Referring to FIG. 1, a digital data processing system of the invention includes an oscillator  10 , a microprocessor  20 , a RAM access controller  30 , and a RAM Device  40  that includes a plurality of RAM blocks RB 1 ˜RBn. The oscillator  10  generates a master clock MCLK 0  having a predetermined cycle period. The RAM blocks RB 1 ˜RBn temporarily store and output data through write and read operations, being controlled by command signals provided from the microprocessor  20 . The RAM blocks RB 1 ˜RBn are synchronously activated in response to an access clock MCLK 1 . In driving the RAM blocks RB 1 ˜RBn, only one of the RAM blocks is put into an active state by a RAM block selection signal RBS supplied through an external pin. Thus, the RAM blocks RB 1 ˜RBn are divided into a RAM block that is conductive and other RAM blocks that are in a standby state. For example, if the first RAM block RB 1  is in an active state, other RAM blocks RB 2 ˜RBn are held in a standby state. The microprocessor  20  provides various control signals, here a reset signal RSB and the RAM block selection signal RBS, to the peripheral circuit blocks in response to the master clock MCLK 0 . 
     As used herein, the phrase “standby state” refers to the time period when an enable signal is being applied to a RAM block (with power being consumed by the RAM block), and data is still not applied to an output buffer. Moreover, as used herein, the phrase “active state” refers to the time period when an enable signal is not applied to a RAM block (and power is not being consumed by the RAM block), and a setup time is required in accordance with a selection signal supplied to the RAM block (that is in the standby state). The RAM block selection signal RBS acts as an enable signal for the RAM blocks RBP-RBn. 
     After being reset at an initial time in response to the reset signal RSB, the RAM access controller  30  generates the access clock MCLK 1  in response to the RAM block selection signal RBS at every rising edge of the master clock MCLK 0  provided from the oscillator  10 . The RAM access controller  30 , as well as supplying the access clock MCLK 1  to a selected RAM block, also applies the wait signal WT to the microprocessor  20  to suspend an access from the microprocessor  20  while a RAM block being accessed is in a setup period. 
     Referring to FIG. 2, the RAM access controller  30  includes a data storage circuit  32  made of a D-flip/flop, a first logic circuit  34  made of an exclusive-OR gate, a data latch circuit  36 , an inverter  37 , and a second logic circuit  38  made of an AND gate. 
     The data storage circuit  32 , after being reset at an initial state by the reset signal RSB, stores the RAM block selection signal RBS supplied through an input terminal D at every rising edge of the master cock MCLK 0  and then generates an N 1  signal shown in FIG.  3 . 
     The first logic circuit  34  generates the wait signal WT shown in FIG. 3 in response to the RAM block selection signal RBS and an output signal provided from the data storage circuit  32 . The inverter  37  converts a phase of the master clock MCLK 0  into its reverse phase. 
     The data latch circuit  36 , after being reset by the reset signal RSB at an initial state, holds the wait signal WT applied through an input terminal D for a low-level term of the master clock MCLK 0  and generates a clock-masking signal MEB shown in FIG.  3 . The second logic circuit  38  generates the access clock MCLK 1  signal (shown in FIG. 3) which activates the RAM blocks RB 1 ˜RBn, in response to the clock-masking signal MEB and the master clock MCLK 0 . 
     Referring to the timing diagram of FIG. 3, first, the RAM access controller  30  is initiated by the reset signal RSB to set output terminals Qs of the data storage circuit  32  and the data latch circuit  36 . Next, at a time t1, the RAM block selection signal RBS transitions to a low level to select one of the RAM blocks RB 1 ˜RBn. 
     The data storage circuit  32  receives data at every rising edge of the master clock MCLK 0 . That is, the rising edges  1 ,  3 ,  5 , and  7  of the master clock MCLK 0  control the data storage circuit  32  to store the RAM block selection signal RBS and generate the output signal N 1 . The RAM block selection signal RBS is held in the data storage circuit  32  during a cycle period from a rising edge to the next rising edge of the master clock MCLK 0 . 
     As the RAM block selection signal RBS is at a high level at the rising edge  1 , the data storage circuit  32  stores the high-level RAM block selection signal RBS until the rising edge  3  and then generates the output signal N 1  at a high-level. As the RAM block selection signal RBS is at a high level at the rising edge  3 , the data storage circuit  32  stores the high-level RAM block selection signal RBS and generates the output signal N 1  at a high level until the rising edge  5 . However, as the RAM block selection signal RBS transitions to a low level after the rising edge  3 , the data storage circuit  32  stores the low-level RAM block selection signal RBS until the rising edge  5 , so that at the rising edge  5  the data storage circuit  32  generates the output signal N 1  at a low level. As the RAM block selection signal RBS maintains a low level still at the rising edge  7 , the data storage circuit  32  stores the low-level RAM block selection signal RBS and continuously generates a low-level output signal N 1 . As shown in FIG. 3, the data storage circuit  32  generates the output signal N 1  that is delayed from the RAM block selection signal RBS by one cycle of the master clock MCLK 0 . 
     The first logic circuit  34  performs an exclusive-OR operation. The exclusive-OR gate outputs a high-level of the wait signal WT only when the RAM block selection signal RBS and the output signal N 1  are at a high level and a low level, or at a low level and a high level, respectively. Thus, the wait signal WT is established in a low level except when either the block selection signal RBS or the output signal N 1  is a low level (or a high level). 
     The data latch circuit  36  receives the wait signal WT during a low level of the master clock MCLK 0 , which is substantially an active state because it is applied through the inverter  37 , and holds the low level therein during a high level of the master clock MCLK 0 . That is, the wait signal WT is input to the data latch circuit  36  during a low-level time period before the rising edge  1  and stored therein as a low level during a high-level time period from the rising edge  1  to a falling edge  2 . Consequently, the data latch circuit  36  receives the wait signal WT at a low level during a time period from the falling edge  2  to the rising edge  3  and then stores the low-level wait signal during a high-level time period from the rising edge  3  to a falling edge  4 . The data latch circuit  36  receives the wait signal WT at a high level during a time period from the falling edge  4  to the rising edge  5  and then stores the high-level wait signal during a high-level time period from the rising edge  5  to a falling edge  6 . Consequently, the data latch circuit  36  receives the wait signal WT at a low level during a time period from the falling edge  6  to the rising edge  7  and then stores the low-level wait signal during a high-level time period from the rising edge  7  to a falling edge  8 . It can be seen that, in FIG. 3, the data latch circuit  36  generates the wait signal WT through the output terminal Q, with a low level until the falling edge  4 , a high level between the falling edge  4  and the rising edge  5 , and a low level after the rising edge  5 . The clock-masking signal MEB maintains a low level from the falling edges  4  to  6 , and a high level during other time periods. 
     The second logic circuit  38  performs an AND operation. The AND gate generates a high level signal only when all input signals are high levels. Therefore, the access clock MCLK 1  output from the second logic circuit  38  maintains a low level between the rising edge  5  and the falling edge  6 , and is figured the same logic value as that of the master clock MCLK 0  until the MEB and MCLK 0  signals go low during the same time period. 
     The access clock MCLK 1  generated from the RAM access controller  30  in response to the RAM block selection signal RBS and the master clock MCLK 0  is activated in accordance with one cycle of the master clock MCLK 0  after the RAM block selection signal RBS transitions to a low level at the time t1. The clock-masking signal MEB is active for a time period between the falling edges  4  and  6 . 
     Returning to FIG. 1, the access clock MCLK 1  generated from the RAM access controller  30  is applied to an alternative one of the RAM blocks RB 1 ˜RBn, which is selected by the RAM block selection signal RBS. Assuming that the RAM block selection signal RBS is applied to the RAM block RB 2  in the state that the RAM block RB 1  is active while the other RAM blocks RB 2 ˜RBn are inactive, the access clock MCLK 1  and not the master clock MCLK 0  is applied to the RAM block RB 2  so as to secure a setup time to prepare an active operation of the RAM block RB 2 . 
     As seen from the aforementioned procedures and constructions, as the present invention places all of the RAM blocks except those that are active in a standby state and employs the access clock MCLK 1  to activate the standby RAM blocks, the present invention reduces overall power consumption and secures a setup time for driving the standby RAM blocks when an access routine by the microprocessor switches the standby RAM blocks to active RAM blocks. While the access clock MCLK 1  is later than the master clock MCLK 0  in activating the next RAM block that transitions to an active state from a standby state, speed degradation will not occur because of the number of RAM blocks being held in a standby state. 
     As a result, regarding the conventional techniques wherein a number of RAM blocks including an active RAM block are forced to be in an active state and wherein RAM blocks other than the RAM blocks that are forced into an active state are situated in a standby state, an additional frequency division process needs to obtain a stable setup time for a RAM block to be accessed therein. Advantageously, the present invention provides a low power digital data processing system having a great storage capacity of RAMs. 
     Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims. For instance, the invention would be advantageous to a digital data processing system including other kinds of storage device such as ROM (Read-Only Memory), as well as the aforementioned system with the RAMs.