Abstract:
A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor device comprising an epitaxial layer. More particularly, the present invention relates to a multi-layered structure including an epitaxial layer, to a semiconductor device comprising the same, and to a method of fabricating the semiconductor device.  
         [0003]     2. Description of the Related Art  
         [0004]     Recently, the use tensile-strained silicon as a channel layer has been researched as a way to improve carrier mobility in a field effect transistor (hereinafter, referred to as a FET).  
         [0005]     In general, the tensile-strained silicon channel layer is produced by forming an Si 1-x Ge x  virtual substrate on a silicon substrate, annealing the resultant structure to relax the structure, and forming a silicon channel layer on the relaxed Si 1-x Ge x  virtual substrate. As a result, the tensile-strained silicon channel layer can be obtained by using the tensile strain in silicon caused by a lattice mismatch between the relaxed Si 1-x Ge x  virtual substrate and the silicon channel layer.  
         [0006]     In forming the Si 1-x Ge x  virtual substrate on the silicon substrate, dislocations thread within the Si 1-x Ge x  virtual substrate when the strain caused by the lattice mismatch with the silicon substrate is relaxed. The threads of the dislocations in the virtual substrate accumulate at the top portion of the virtual substrate, and propagate into the silicon channel, thereby causing carrier scattering to occur in the channel. Carrier scattering prevents the FET from providing high carrier mobility.  
         [0007]     An attempt to reduce the dislocation defect density of the epitaxial layer is described in U.S. Pat. No. 5,659,187. The patent discloses that an epitaxial layer, used as a virtual substrate, and having a composition graded by 0.025 to 2% per 1,000 Å in its direction of thickness, has a reduced dislocation defect density.  
         [0008]     Meanwhile, in order to form a tensile-strained silicon channel layer that provides sufficient carrier mobility at the top of an Si 1-x Ge x  virtual substrate, the value of X at the top surface of the Si 1-x Ge x  virtual substrate must be 0.2 or more. And preferably, the value of X at the bottom surface of the Si 1-x Ge x  virtual substrate contiguous to (i.e., interfacing with) the silicon substrate is 0.  
         [0009]     Therefore, in a case in which an Si 1-x Ge x  layer is used as the virtual substrate, and the composition of the Si 1-x Ge x  was graded by 2% per 1,000 Å as described in the above-mentioned patent, the Si 1-x Ge x  virtual substrate would have to be at least 1 μm thick if the value of X were to be 0 at the bottom surface and 0.2 or more at the top surface. Such a thick epitaxial layer presents problems in implementing a subsequent photolithography process.  
         [0010]     Another attempt to reduce the dislocation defect density, proposes a chemical mechanical polishing (CMP) process to eliminate the threads of the dislocations accumulating at the top portion of the epitaxial layer.  
         [0011]     Nonetheless, despite the use of the above-described methods, the dislocation defect density of an Si 1-x Ge x  virtual substrate remains high—on the order of 10 6 /cm 2 .  
       SUMMARY OF THE INVENTION  
       [0012]     An object of the present invention is to solve the above-described problems and limitations of the prior art.  
         [0013]     Thus, it is one object of the present invention to provide a multi-layered structure comprising an epitaxial layer that is relatively thin and yet has a low dislocation defect density.  
         [0014]     It is thus another object of the present invention to provide a semiconductor device having a multi-layered structure comprising an epitaxial layer and having high carrier mobility.  
         [0015]     According to one aspect of the present invention, the invention provides a multi-layered structure comprising a substrate, and a heteroepitaxial layer disposed on the substrate. The heteroepitaxial layer consists of a main epitaxial layer having a lattice constant different from that of the substrate, and at least one intermediate epitaxial layer sandwiched within the main epitaxial layer. The intermediate epitaxial layer has a lattice constant different from portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. Also, the intermediate epitaxial layer has a thickness smaller than that of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer.  
         [0016]     The main epitaxial layer may have a graded composition from its bottom surface to its top surface or the main epitaxial layer may have a uniform composition throughout its entirety.  
         [0017]     Preferably, the main epitaxial layer is composed of Si 1-x Ge x  (0&lt;X&lt;1). In this case, the substrate is composed of monocrystalline silicon, and the value of X may be 0 at the bottom surface of the main epitaxial layer. The value of X may also thus increase in a graduated manner to the top surface of the main epitaxial layer or the value of X may be constant throughout the main epitaxial layer.  
         [0018]     The intermediate epitaxial layer may have a uniform composition throughout. The intermediate epitaxial layer may be formed of Si, SiC, or SiGeC. Preferably, the sum of the thicknesses of the at least one intermediate epitaxial layer is ½ or less of the net thickness of the main epitaxial layer.  
         [0019]     According to another aspect of the present invention, the invention provides a semiconductor device comprising a strained channel layer, and wherein the heteroepitaxial layer is interposed between the substrate and the channel layer. The channel layer may be a tensile-strained layer. Also, the channel layer may be composed of Si or SiC.  
         [0020]     As was mentioned above, the composition of the main epitaxial layer may be graded from the bottom surface to the top surface of the layer. In this case, the semiconductor device preferably further comprises a uniform epitaxial layer interposed between the heteroepitaxial layer and the channel layer. The composition of the uniform epitaxial layer is the same as that at the top surface of the heteroepitaxial layer.  
         [0021]     According to still another aspect of the present invention, the invention provides a method of fabricating the semiconductor device including steps of providing a substrate, forming the heteroepitaxial layer on the substrate whereby the intermediate epitaxial layer will absorb the strain in the heteroepitaxial layer, annealing the heteroepitaxial layer, and forming the channel layer on the annealed heteroepitaxial layer.  
         [0022]     The substrate on which the heteroepitaxial layer is formed may be polished using a chemical mechanical polishing (CMP) process, before the channel layer is formed.  
         [0023]     Also, the heteroepitaxial layer may be formed by ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), low pressure chemical vapor deposition (LPCVD), or molecular beam epitaxy (MBE).  
         [0024]     Also, in the case mentioned above in which the heteroepitaxial layer has a graded composition, a uniform epitaxial layer may be formed on the heteroepitaxial layer before the channel layer is formed, wherein the composition of the uniform epitaxial layer is the same as that of the top portion of the heteroepitaxial layer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]     The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0026]      FIGS. 1A and 1B  are sectional views of a substrate, illustrating a method of fabricating a semiconductor device according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0027]     The preferred embodiments of the present invention will be described in detail hereinafter with reference to  FIGS. 1A and 1B .  
         [0028]     Referring first to  FIG. 1A , a heteroepitaxial layer is formed on a substrate  100 . The substrate  100  may be made of monocrystalline silicon. The heteroepitaxial layer comprises a main epitaxial layer  200  and at least one intermediate epitaxial layer  300  sandwiched within the main epitaxial layer  200 . The heteroepitaxial layer having the intermediate epitaxial layer  300  may be formed by ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), low pressure chemical vapor deposition (LPCVD), or molecular beam epitaxy (MBE). Subsequently, the heteroepitaxial layer comprising the at least one intermediate epitaxial layer  300  is annealed. Preferably, the annealing process is performed for at least one hour at 950° C.  
         [0029]     The main epitaxial layer  200  is formed of a material having a lattice constant different from that of the substrate  100 . Generally, an epitaxial layer is strained by a lattice mismatch with an underlying substrate, and dislocations occur in the epitaxial layer when the strain is relaxed by the annealing process. However, according to the present invention, dislocations can be prevented from occurring in the main epitaxial layer  200  by forming the intermediate epitaxial layer  300  therein. Here, the intermediate epitaxial layer  300  must have a lattice constant different from that of the portions of the main epitaxial layer  200  contiguous to the intermediate epitaxial layer  300 .  
         [0030]     Assuming that the thicknesses of the main epitaxial layer  200  and the intermediate epitaxial layer  300  are small, the magnitudes of the strain in the main epitaxial layer  200  and the intermediate epitaxial layer  300  are identical. In addition, the orientation of the strain in the main epitaxial layer  200  is different from that in the intermediate epitaxial layer  300  because the lattice constants of the main epitaxial layer  200  and the intermediate epitaxial layer  300  are mismatched. That is, the main epitaxial layer  200  and intermediate epitaxial layer  300  are strained in tension and compression, or in compression and tension, respectively, and the levels of the strain are identical. This condition can be represented by the following mathematical expression: 
 
Be 1   2 h 1 =Be 2   2 h 2  
 
 wherein B=2G(1+n)/(1−n), G=shear modulus, n=Poisson&#39;s ratio, e=lattice mismatch, and h=layer thickness. 
 
         [0031]     Referring to the mathematical expression, the larger the net thickness (h 2 ) of the main epitaxial layer  200  becomes, the greater is the strain applied to the intermediate epitaxial layer  300 . Accordingly, when the thickness of the main epitaxial layer  200  is sufficiently large relative to the thickness of the intermediate epitaxial layer  300 , the intermediate epitaxial layer  300  absorbs almost all of the strain in the heteroepitaxial layer. Accordingly, the thickness of the intermediate epitaxial layer  300  must be small compared to the net thickness of the main epitaxial layer  200 . Preferably, the thickness of the intermediate epitaxial layer  300  is ½ of that of the main epitaxial layer  200 . And, it follows that when more than one intermediate epitaxial layer  300  is present in the heteroepitaxial layer, the sum of the thicknesses of the intermediate epitaxial layers  300  is preferably ½ of the net thickness of the main epitaxial layer  200 .  
         [0032]     The annealing process relaxes the strain at the interface between the intermediate epitaxial layer  300  and the main epitaxial layer  200 . The relieving of strain due to the annealing process causes dislocations to occur in the intermediate epitaxial layer  300  that has absorbed almost all of the strain from the main epitaxial layer  200 . However, the dislocations are suppressed in the main epitaxial layer  200  in which the strain has been relieved by the intermediate epitaxial layer  300 . Accordingly, the main epitaxial layer  200  has a low number of dislocations, i.e., a low dislocation defect density.  
         [0033]     The main epitaxial layer  200  may have a graded composition from the bottom surface  200   a,  contiguous to the substrate  100 , to the top surface  200   b  thereof, which is to say from the bottom surface to the top surface of the heteroepitaxial layer. Alternatively, the main epitaxial layer  200  may have a uniform composition from the bottom surface  200   a  to the top surface  200   b.    
         [0034]     The main epitaxial layer  200  may be formed of Si 1-x Ge x  (0&lt;X&lt;1).  
         [0035]     In the case in which the substrate  100  is a monocrystalline silicon substrate and the main epitaxial layer  200  has a graded composition, it is possible for the value of X to be 0 at the bottom surface  200   a  of the heteroepitaxial layer. Preferably, the value of X is 0.2 or more at the top surface  200   b.  Generally, the dislocation density of the graded main epitaxial layer  200  can be minimized solely by fabricating the main epitaxial layer  200  such that the value of X varies by 0.02 or less per 1,000 Å in the direction of thickness of the heteroepitaxial layer. However, as described above, according to the present invention, dislocations in the main epitaxial layer  200  can be suppressed by forming the intermediate epitaxial layer  300  in the main epitaxial layer  200 . Accordingly, the value of X in a main epitaxial layer formed of Si 1-x Ge x  can vary by 0.02 or more per 1,000 Å in the direction of thickness of the heteroepitaxial layer. Consequently, when the value of X is 0.2 at the top surface  200   b  of the heteroepitaxial layer, the thickness of the main epitaxial layer  200  can be 1 μm or less and still have a low dislocation defect density.  
         [0036]     Alternatively, the value of X in the composition Si 1-x Ge x  of the main epitaxial layer  200  may be constant from the bottom surface  200   a  of the main epitaxial layer to the top surface  200   b.  In this case, the value of X may be 0.2 or more. In general, in the case of an epitaxial layer having a uniform composition, the layer is formed thick enough to limit the ability of dislocations to propagate all the way to the top surface of the epitaxial layer. However, according to the present invention as described above, the heteroepitaxial layer can be relatively thin without incurring dislocations because of the forming of the intermediate epitaxial layer  300  prior to the annealing process. Such a relatively thin (hetero)epitaxial layer facilitates a subsequent photolithography process.  
         [0037]     The intermediate epitaxial layer  300  may have a uniform composition. Preferably, the intermediate epitaxial layer  300  is formed of Si, SiC, or SiGeC.  
         [0038]     Referring to  FIG. 1B , preferably, the substrate  100  on which the heteroepitaxial layer is formed is polished using a chemical mechanical polishing (hereinafter, referred to as CMP) process. As described above, although it is unlikely that a significant number of dislocation defects will be present at the top surface  200   b  of the heteroepitaxial layer, the CMP process will nonetheless eliminate any dislocation defects that have been incurred at the top surface  200   b.    
         [0039]     Subsequently, a uniform epitaxial layer  400  (an epitaxial layer having a uniform composition) may be formed on the polished heteroepitaxial layer. The uniform epitaxial layer  400  may be omitted in the case in which the main epitaxial layer  200  has a uniform composition. The uniform epitaxial layer  400  has the same composition as that of the heteroepitaxial layer at the top surface  200   b,  i.e., at the surface at which the uniform epitaxial layer  400  interfaces with the heteroepitaxial layer.  
         [0040]     A channel layer is formed on the uniform epitaxial layer  400 . The channel layer is formed of a material having a lattice constant different from that of the uniform epitaxial layer  400 , i.e. different from that at the top surface  200   b  of the heteroepitaxial layer. Alternatively, the channel layer is formed directly on the heteroepitaxial layer in the above-described case in which the uniform epitaxial layer  400  is omitted. In this latter case, the channel layer is formed of a material having a lattice constant different from that of the heteroepitaxial layer. For example, the channel layer may be formed of Si or SiC.  
         [0041]     As a result, the channel layer is formed as a strained channel layer  500  due to a lattice mismatch with the uniform epitaxial layer  400  or the heteroepitaxial layer. When the lattice constant of the channel layer is smaller than that of the uniform epitaxial layer  400  or the heteroepitaxial layer, the strained channel layer  500  is strained in tension, i.e., is a tensile-strained channel layer  500 . In the case in which the channel layer  500  is formed of Si and the uniform epitaxial layer  400  or the heteroepitaxial layer  200  is formed of Si 1-x Ge x  (0&lt;X&lt;1), the value of X is preferably 0.2 or more. This is because proper carrier mobility is obtained in the channel layer  500  when X has a value of 0.2 or more in this case.  
         [0042]     Meanwhile, few dislocation defects propagate into the channel layer  500  because of the low dislocation defect density of the main epitaxial layer  200  and the lack of dislocation defects incurred at the top surface  200   b  of the heteroepitaxial layer  200 . Accordingly, carrier scattering is reduced and therefore, carrier mobility in the channel layer is high.  
         [0043]     According to the present invention as described above, a thin epitaxial layer having a low dislocation defect density can be provided by forming the epitaxial layer as heteroepitaxial layer consisting of a main epitaxial layer and an intermediate epitaxial layer having a thickness less than that of the main epitaxial layer. Also, the present invention provides a semiconductor device having high carrier mobility.  
         [0044]     Although the present invention have been described above in detail with respect to the preferred embodiments thereof, those skilled in the art will appreciate that various modifications and/or additions can be made to the preferred embodiments without departing from the true scope and spirit of the invention as defined by the appended claims.