Abstract:
An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention pertains in general to a bipolar junction transistor and, more particularly, to a high-gain pnp bipolar junction transistor in a CMOS circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    Bipolar junction transistors (“BJTs”) are important in a number of applications in a CMOS device, which, by definition, includes at least one p-channel and one n-channel metal-oxide semiconductor field-effect transistor (“MOSFET”). BJTs generally exhibit higher gain, higher frequency performance and lower noise compared to MOSFETs. The gain (β) of a BJT is defined as the ratio of collector current Ic over base current I B , and is inversely proportional to well-depth and well concentration. As a result, BJTs often exhibit lower than preferred gain when incorporated in a conventional CMOS circuit because of deep well-depth and high well concentration.  
         SUMMARY OF THE INVENTION  
         [0005]    Accordingly, the present invention is directed to a high-gain pnp BJT in a CMOS device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.  
           [0006]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawing.  
           [0007]    To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit device that includes a semiconductor substrate, a first n-well in the substrate, a first p-well contiguous with the first n-well in the substrate, and a second n-well contiguous with the first p-well. The second n-well includes a second p-well having a first n-type region and a second n-type region, wherein the first and the second n-type regions respectively define emitter and collector regions of a first BJT, a first p-type region spaced apart from the second n-type region, wherein the first p-type region and the second p-well respectively define emitter and collector regions of a second BJT, and a third n-type region spaced apart from the first p-type region.  
           [0008]    In one aspect of the invention, the first n-type region is a collector of a composite pnp BJT.  
           [0009]    In another aspect of the invention, the second p-well and the first p-type region comprise emitter of a composite pnp BJT.  
           [0010]    In yet another aspect of the invention, the third n-type region is a base of a  
           [0011]    In still another aspect of the invention, the second p-well comprises an npn BJT.  
           [0012]    In another aspect of the invention, the second p-well, the first p-type region, and the third n-type region comprise a pnp BJT.  
           [0013]    Also in accordance with the invention, there is provided an integrated circuit device that includes a semiconductor substrate, an NMOS formed in the substrate, a PMOS contiguous with the NMOS and formed in the substrate, and a composite pnp bipolar junction transistor contiguous with the NMOS and formed in the substrate, wherein the composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having first and second spaced-apart n-type regions, and a lateral pnp bipolar junction transistor including the second spaced-apart n-type region, a first p-type spaced-apart region and a third n-type region, wherein the first p-type spaced-apart region and the third n-type region are separated by a shallow trench isolation.  
           [0014]    In one aspect of the invention, a gain of the composite pnp bipolar junction transistor equals gain of the lateral npn bipolar junction transistor multiplied by a gain of the lateral pnp bipolar junction transistor.  
           [0015]    Further in accordance with the present invention, there is provided an integrated circuit device that includes a semiconductor substrate, an NMOS formed in the substrate, a PMOS contiguous with the NMOS and formed in the substrate, and a composite pnp bipolar junction transistor contiguous with the NMOS and formed in the substrate, wherein the composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, and wherein a current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.  
           [0016]    Additionally in accordance with the present invention, there is provided a method for forming a composite pnp BJT in a CMOS device having a substrate including an n-well region. The method includes providing a first photoresist over the substrate, patterning and defining the photoresist to expose a portion above the n-well region, implanting the n-well region with a dopant to form a shallow p-well region, and removing the photoresist. The method also includes the steps of implanting a first dose of dopant to form lightly-doped n-type spaced-apart regions, implanting a second dose of dopant to form a lightly-doped p-type spaced-apart region, forming a gate structure including a gate and gate oxide, implanting a third dose of dopant into the lightly-doped spaced-apart n-type regions to form heavily-doped n-type regions wherein the third dose of dopant is more concentrated than the first dose of dopant, and implanting a fourth dose of dopant into the lightly-doped spaced-apart p-type region to form a heavily-doped p-type regions wherein the fourth dose of dopant has a higher concentration than the second dose of dopant.  
           [0017]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the objects, advantages, and principles of the invention.  
         [0019]    In the drawings:  
         [0020]    [0020]FIG. 1 shows a cross-sectional view of a CMOS device having a composite pnp bipolar junction transistor constructed in accordance with the present invention;  
         [0021]    [0021]FIG. 2 shows a top view of a layout of a portion of a composite pnp bipolar junction transistor constructed in accordance with the present invention;  
         [0022]    [0022]FIG. 3 shows an equivalent circuit of a composite pnp bipolar junction transistor of the present invention; and  
         [0023]    FIGS.  4 A- 4 H show a sequence of cross-sectional views illustrating a method for forming a CMOS device having a composite pnp bipolar junction transistor according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    In accordance with the present invention, a high-gain composite pnp BJT is provided in a CMOS device. The composite pnp BJT is comprised of a lateral pnp BJT and a lateral npn BJT, wherein the base of the lateral npn BJT is a shallow p-well. The gain of the composite pnp BJT is the product of the gain of the lateral npn BJT multiplied by the gain of the lateral pnp BJT, and is not influenced by the depth of the shallow p-well.  
         [0025]    An embodiment of the present invention is shown in FIG. 1, which shows a cross-sectional view of a twin-well CMOS device  2  with a composite pnp BJT. Although only one composite pnp BJT is shown, one of ordinary skill in the art will now understand that more than one such composite pnp BJT may be implemented in a CMOS device.  
         [0026]    Referring to FIG. 1, CMOS device  2  includes a p-type semiconductor substrate  4 , an n-well region  6  that contains a p-type MOS (“PMOS”), a contiguous p-well region  8  that contains an n-type MOS (“NMOS”), and an n-well region  28  contiguous with p-well region  8 . N-well region  28  contains a composite pnp BJT.  
         [0027]    N-well region  6  includes spaced-apart p-type regions  20  and  22  that respectively serve as drain and source regions for the PMOS. N-well region  6  includes a channel region (not numbered) between spaced-apart regions  20  and  22 , and shallow trench isolation (“STI”) structures  14 - 2  and  14 - 3  contiguous with spaced-apart regions  20  and  22 , respectively. Each STI  14  (i.e.,  14 - 2 ,  14 - 3 , etc.) may be composed of a suitable dielectric material such as silicon-dioxide. Region  20  includes a lightly-doped region  20 - 1  and a heavily-doped region  20 - 2  and region  22  likewise includes a lightly-doped region  22 - 1  and a heavily-doped region  22 - 2 . The PMOS also includes a gate structure including a gate  24  and gate insulator  26  positioned over the channel region.  
         [0028]    Contiguous with the PMOS is an NMOS that includes P-well region  8 , which includes spaced-apart n-type regions  10  and  12  that respectively serve as drain and source regions for the NMOS. Region  10  includes a lightly-doped region  10 - 1  and a heavily-doped region  10 - 2  and region  12  includes a lightly-doped region  12 - 1  and a heavily-doped region  12 - 2 . P-well region  8  also includes a channel region (not numbered) between spaced-apart regions  10  and  12 , and STIs  14 - 1  and  14 - 2  contiguous with spaced-apart regions  10  and  12 , respectively. The NMOS also includes a gate structure including a gate  16  and gate insulator  18  positioned above the channel region.  
         [0029]    Contiguous with the NMOS is a high-gain composite pnp BJT. The composite BJT includes N-well region  28 , a lateral pnp BJT, and a lateral npn BJT. Specifically, n-well region  28  includes a shallow p-well region  30 , a p-type region  32 , an n-type region  34 , and STIs  14 - 4  and  14 - 5 .  
         [0030]    Shallow p-well region  30  includes spaced-apart n-type regions  40  and  42  that respectively serve as emitter and collector regions of the lateral npn BJT. Region  40  includes two lightly-doped regions  40 - 1  and a heavily-doped region  40 - 2  and region  42  includes a lightly-doped region  42 - 1  and a heavily-doped region  42 - 2 . Shallow p-well region  30  further includes a channel region (not numbered) between spaced-apart regions  40  and  42 . Region  42  is contiguous with STI  14 - 4 . A gate structure including a gate  36  and gate insulator  38  is positioned over the channel region to complete the lateral npn BJT.  
         [0031]    The lateral pnp BJT includes spaced-apart regions  32  and  40 , and a channel region there between (not numbered). Region  32  is contiguous with STI  14 - 5 . Region  32  includes a lightly-doped region  32 - 1  and a heavily-doped region  32 - 2 . Region  40  includes a lightly-doped region  40 - 1  and a heavily-doped region  40 - 2 . A gate structure including a gate  44  and gate insulator  46  is positioned over the channel region to complete the lateral pnp BJT of the present invention.  
         [0032]    [0032]FIG. 2 shows the top view of the layout of a part of a composite pnp BJT of the present invention. Referring to FIG. 2, n-well region  28  includes implanted spaced-apart regions  32  and  34 , and implanted spaced-apart n-type regions  40  and  42 . Gate  36  is disposed over the channel region between spaced-apart n-type regions  40  and  42  and gate  44  is disposed over the channel region between n-type region  40  and p-type region  32 .  
         [0033]    In operation, the lateral pnp BJT and the lateral npn BJT combine to form the composite high-gain pnp BJT, wherein spaced-apart region  42  acts as the collector, spaced-apart region  34  acts as the base, and spaced-apart regions  32  and  40 , in combination, act as the emitter of the composite pnp BJT. An equivalent circuit of the composite pnp BJT is shown in FIG. 3. The arrows in FIG. 3 indicate the direction of current flow for I B , I C  and I E , representing the base, collector, and emitter current, respectively.  
         [0034]    The lateral pnp BJT exhibits a gain of β 1  and the lateral npn BJT exhibits a gain of β 2 . The gain of the composite pnp BJT exhibits a gain β equal to the product of β 1  multiplied by β 2 . In addition, gain β is not sensitive to the depth of shallow p-well  30 , and may be controlled by the lengths of the gates  36  and  44 .  
         [0035]    A method in accordance with the present invention is explained with reference to FIGS.  4 A- 4 H. Referring to FIG. 4A, n-well region  6 , p-well region  8 , n-well region  28  and STIs  14 - 1 ,  14 - 2 ,  14 - 3 ,  14 - 4  and  14 - 5  are formed in silicon substrate  4  with a conventional CMOS manufacturing process. For example, n-well regions  6  and  28  may be formed by implanting phosphorus P at a dose of approximately 10 11  to 10 13  per cm 2  at an energy of approximately between 80 KeV to 200 KeV. P-well region  8  may be formed by implanting boron B or BF 2  at a dose of approximately 10 11  to 10 13  per cm 2  at an energy of approximately between 80 KeV to 200 KeV.  
         [0036]    Referring to FIG. 4B, a first photoresist  50  is disposed over substrate  4  and patterned to remove a portion where shallow p-well  30  is to be formed. With photoresist  50  as a mask, a step of ion implantation is performed. Specifically, substrate  4  is doped with BF 2  at a dose of approximately 10 11  to 5×10 13  per cm 2  at a relatively low energy of approximately between 60 KeV to 120 KeV to form shallow p-well  30 . The BF 2  ion implantation step preferably takes place after the formation of the STIs to limit dopant diffusion. In a preferred embodiment, shallow p-well  30  extends approximately between 0.1 micron and 0.3 microns underneath STI 14 - 4 . Photoresist  50  is then removed.  
         [0037]    [0037]FIG. 4C shows the formation of the gates of the PMOS, NMOS, npn BJT and pnp BJT. Conventional steps may be employed to form the gates as shown in FIG. 1. Specifically, a layer of gate oxide (not numbered) is grown at a temperature between approximately 700° C. and approximately 900° C. A polysilicon layer is deposited over the gate oxide layer. A photoresist is the deposited over the polysilicon layer, patterned to form open areas. The stacked structure of the polysilicon and gate oxide layers is then etched. After the photoresist is removed, gates  36 ,  44 ,  16  and  24  and the gate oxide disposed directly beneath the gates remain. In a preferred embodiment, the overlap between gate  44  and shallow p-well  30  is approximately between 0.1 micron and 1.0 microns.  
         [0038]    Lightly-doped regions  32 - 1 ,  22 - 1  and  20 - 1  of p-type regions  32 ,  22  and  20 , respectively, are then formed. Referring to FIG. 4D, a second photoresist  52  is deposited over substrate  4  and patterned to form open areas directly above regions  32 ,  22  and  20 . With photoresist  52  as a mask, a second step of ion implantation is performed. Regions  32 ,  22  and  20  are doped with B or BF 2  at a dose of approximately 10 12  to 10 14  per cm 2  at an energy of approximately between 20 KeV to 60 KeV.  
         [0039]    After photoresist  52  is removed, the n-type lightly doped regions are then formed. Referring to FIG. 4E, a third photoresist  54  is disposed over substrate  4  and patterned to form open areas as shown. With photoresist  54  as a mask, a third step of ion implantation is performed. The exposed areas of substrate  4  are doped with phosphorus P or arsenic As at a dose of approximately 10 12  to 2×10 14  per cm 2  at an energy of approximately between 20 KeV to 80 KeV, forming n-type region  34 - 1  and n-type lightly doped regions  42 - 1 ,  40 - 1 ,  10 - 1 ,  12 - 1  and  34 - 1  of spaced-apart regions  42 ,  40 ,  10  and  12 , respectively. Photoresist  54  is then removed.  
         [0040]    Conventional steps may be used to form spacer oxides  38 - 1 ,  46 - 4 ,  18 - 1  and  26 - 1  surrounding gates  36 ,  44 ,  16  and  24 , respectively, as shown in FIG. 4F. In a preferred embodiment, spacer oxides  38 - 1 ,  46 - 1 ,  18 - 1  and  26 - 1  are composed of undoped tetraethyl orthosilicate (“TEOS”), and the width of the spacer oxides is between approximately 0.05 microns and 0.3 microns.  
         [0041]    Heavily doped p-type regions  32 - 2 ,  20 - 2  and  22 - 2  of regions  32 ,  20  and  29 , respectively, are formed next. Referring to FIG. 4G, a fourth photoresist  56  is deposited over substrate  4  and patterned to form open areas above regions  32 ,  20  and  22 . With photoresist  56  and spacer oxides  46 - 1  and  26 - 1  as a mask, a fourth ion implantation step is performed. Regions  32 ,  22  and  20  are doped with B or BF, at a dose of approximately 5×10 14  to 5×10 15  per cm 2  at an energy of approximately between 20 KeV to 80 KeV, thereby forming heavily doped regions  32 - 2 ,  22 - 2  and  20 - 2 . As a result, spaced-apart region  32  includes lightly-doped region  32 - 1  and heavily-doped region  32 - 2 ; spaced-apart region  20  includes lightly-doped region  20 - 1  and heavily-doped region  20 - 2 ; and spaced-apart region  22  includes lightly-doped region  22 - 1  and heavily-doped region  22 - 2 . Photoresist  56  is then removed.  
         [0042]    Heavily doped n-type regions  42 - 2 ,  40 - 2 ,  10 - 2  and  12 - 2  of regions  42 ,  40 ,  10  and  12 , and region  34  are formed. Referring to FIG. 4H, a fifth photoresist  58  is deposited over substrate  4  and patterned to form open areas above regions  40 ,  42 ,  34 ,  10  and  12 . With photoresist  58  and spacer oxides  38 - 1 ,  46 - 1  and  18 - 1  as a mask, a fifth ion implantation step is performed. Regions  40 ,  42 ,  34 ,  10  and  12  are doped with As at a dose of approximately 5×10 14  to 5×10 15  per cm 2  at an energy of approximately between 20 KeV to 100 KeV, thereby forming heavily doped regions  40 - 2 ,  42 - 2 ,  10 - 2  and  12 - 2 , and region  34 . As a result, spaced-apart region  40  includes lightly-doped region  40 - 1  and heavily-doped region  40 - 2 ; spaced-apart region  42  includes lightly-doped region  42 - 1  and heavily-doped region  42 - 2 ; spaced-apart region  10  includes lightly-doped region  10 - 1  and heavily-doped region  10 - 2 ; and spaced-apart region  12  includes lightly-doped region  12 - 1  and heavily-doped region  12 - 2 . Photoresist  58  is then removed.  
         [0043]    The method of the present invention continues with known steps of forming inter-layer dielectrics, forming contacts and metalization.  
         [0044]    It will also be apparent to those skilled in the art that various modifications and variations can be made in the disclosed product without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.