Abstract:
A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of electronic devices and, more particularly, to semiconductor devices and related methods. 
     JOINT RESEARCH AGREEMENT 
     The claimed configurations set forth herein were made as a result of activities undertaken within the scope of a joint research agreement. The parties to the joint research agreement are (1) STMicroelectronics, Inc., and (2) International Business Machines Corporation. 
     BACKGROUND OF THE INVENTION 
     Fin-based field effect transistors (FINFETs) are vertical transistor devices in which a semiconductor fin is located on a substrate and is used to define the channel region of the device. The gate structure overlies the fin in the channel area, and in some configurations multiple fins may be used to provide a multi-gate transistor architecture. The multiple gates may be controlled by a single gate electrode, where the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. 
     With ever-increasing device integration densities, (e.g., 10 nm and beyond), various challenges may arise with respect to FINFET semiconductor devices. For example, with increasing densities, the distances between adjacent devices becomes smaller, making the chances for inadvertent shorting between them greater. As such, further enhancements in semiconductor devices may be desirable in some applications, such as next generation FINFET devices with relatively small dimensions, for example. 
     SUMMARY OF THE INVENTION 
     A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric material in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins. 
     More particularly, selectively removing the at least one intermediate semiconductor fin may include selectively removing a group of adjacent intermediate semiconductor fins, and the at least one isolation pillar may include a group of spaced-apart isolation pillars. Furthermore, the method may also include selectively removing portions of the first dielectric material to widen the at least one trench after selectively removing the at least one intermediate semiconductor fin. The method may further include removing upper portions of the regions of the first dielectric material so that the semiconductor fins and the at least one isolation pillar extend above the regions of the first dielectric material. 
     By way of example, the first dielectric material may comprise silicon dioxide, and the second dielectric material may comprise aluminum oxide. The method may also include forming a gate overlying the semiconductor fins and the at least one isolation pillar. Moreover, a pair of source and drain regions may be formed on opposing ends of at least one semiconductor fin. 
     In addition, selectively removing the at least one intermediate semiconductor fin may include forming a mask layer above the semiconductor fins and exposing the at least one intermediate semiconductor fin, and removing the at least one semiconductor fin through the mask layer. By way of example, the plurality of semiconductor fins may comprise silicon, and the substrate may comprise a semiconductor substrate. 
     A related semiconductor device may include a substrate, a plurality of laterally spaced-apart semiconductor fins above the substrate, and a first dielectric material between the laterally spaced-apart semiconductor fins. Further, at least one isolation pillar may be between the laterally spaced-apart semiconductor fins, the at least one isolation pillar comprising a second dielectric material different than the first dielectric material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a top view of a semiconductor FINFET device in accordance with an example embodiment including isolation pillars between adjacent transistors. 
         FIGS. 2-15  are a series of cross-sectional views taken along line A-A of  FIG. 1  and illustrating a method of making the semiconductor FINFET device shown therein. 
         FIGS. 16-19  are a series of cross-sectional views, also taken along line A-A of  FIG. 1 , and illustrating another approach for making the semiconductor FINFET device. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similarly elements in different embodiments. 
     By way of background, FINFET devices may provide desired short channel control to enable technology scaling down to 10 nm nodes and beyond. A source/drain in-situ doped epitaxial merge process may be used to connect the fins outside of the gate for lowering the source/drain spreading resistance, and to provide a relatively flat topography for source/drain contact landings, as will be appreciated by those skilled in the art. One potential drawback of this lateral epitaxial growth in complementary devices is that in the boundary region between N-type and P-type transistors, relaxed or wider spacing may otherwise be required to keep epitaxial growth from shorting fins from the N-type and P-type transistors together. More particularly, due to the loading effects, the fins tend to experience more epitaxial growth, which may make it challenging to achieve desired growth in the source/drain regions without inter-fin growth that results in shorting. However, increasing the spacing between N-type and P-type devices reduces the amount of available surface area or “real estate”, and accordingly restricts chip area scaling, especially in ultra-dense SRAM arrays, for example. 
     One approach to providing adequate isolation between fins of adjacent N-type and P-type transistors, without an excessive loss of surface area from spacing the transistors too far apart, is to grow raised shallow trench isolation (STI) regions between adjacent transistors to help prevent shorts between these adjacent devices. However, it may be difficult to accurately control the positioning of the raised STI regions due to lithography alignment capabilities. More particularly, at smaller processing nodes, it may be challenging to precisely align the lithography/photoresist to pattern an STI region precisely between adjacent N-type and P-type devices. For example, if the STI pillar gets too close to a fin this may undesirably increase the “on” resistance for that particular device. Moreover, if the STI pillar is in contact with a fin, this may damage the fin and potentially lead to device failure. 
     Generally speaking, a self-aligned “dummy fin” approach is set forth herein to help prevent epitaxial lateral growth in the N/P transistor boundary regions, to thereby help enable further chip area scaling to lower processing nodes. It should be noted, however, that the techniques set forth herein are not reserved for isolating N and P-type (i.e., complementary) devices, but may also be used for isolating devices of a same conductivity type, for example. 
     Referring initially to  FIGS. 1-2 , a semiconductor FINFET device  30  and associated method for making the semiconductor device are first described. On a semiconductor substrate  31  (e.g., silicon), a hard mask  32  (e.g., silicon nitride, SiN) is formed. A fin patterning/etching step may then be performed, as seen in  FIG. 3 , to define a plurality of semiconductor fins  33  and residual nitride portions  34 , as will be appreciated by those skilled in the art. An oxide  35  (e.g., SiO 2 ) may then be filled over and between the fins  33 /residual nitride portions  34 , and planarized (e.g., by chemical mechanical polishing, CMP) at the upper surfaces of the residual nitride portions, as seen in  FIG. 4 . 
     A photomask  36  may then be formed ( FIG. 5 ) covering the fins  33  and corresponding residual nitride portions  34  that are to remain, and exposing those that are to be removed via photolithography patterning. As shown in this example, the openings in the photomask  36  are not precisely aligned with the fins  33 /residual nitride portions  34  that are to be etched away. This may otherwise present a problem if one were attempting to selectively replace certain fins  33  with a raised STI region at this point, as the relatively imprecise alignment of the photomask  36  opening may result in the STI region being in contact with (or almost in contact with) adjacent fins, leading to the problems discussed above. 
     Yet, in accordance with the present approach, the exposed residual nitride portions  34  may be etched away, as shown in  FIG. 6 . By way of example, this may be done using an isotropic etching process, such as a Frontier dry etch process from AMAT. This may be followed by stripping or removal of the photomask  36  ( FIG. 7 ), and then selective etching of the exposed fins  33  using adjacent portions of the oxide  35  and the remaining residual nitride portions  34  as a hard mask ( FIG. 8 ). The etch may extend partially into the silicon substrate  31 , as shown in the illustrated example. Thus, despite the potential misalignment or inaccuracy of the photomask  36  deposition, a very precise removal of the desired fins  33  may still be achieved through the two-part removal of the given residual nitride portions  34  and the underlying fins. 
     Referring to  FIG. 9 , an isotropic lateral etch of the oxide  35  may then be performed to widen the trenches where the exposed semiconductor fins  33  were removed. By way of example, a target width of the lateral etch may be slightly more than half of a fin-to-fin spacing  37 , which may be in a range of about 10 nm to 20 nm, for example, although other spacings may be used in different embodiments. Where multiple contiguous fins are removed, this creates a wider gap or trench compared to a single fin removal, as seen in  FIG. 9 . An epitaxial protection layer  40  (e.g., Al 2 O 3 ) may then be deposited or formed over the upper surfaces of the oxide  35 , residual nitride portions  34 , and the substrate  31  where exposed by the above-noted etching, as shown in  FIG. 10 . Other suitable materials may also be used for the protection layer  40 , as will be appreciated by those skilled in the art. For example, such materials may include oxides which are different than the oxide  35  (i.e., different than SiO 2  in the present example), as this will allow selective removal of the oxide  35  to expose portions of the protection layer  40 , as will be discussed further below. 
     Another oxide  41  (e.g., SiO 2 ) may then be formed or filled over the protection layer  40 , followed by oxide planarization and non-selective CMP processing to expose the residual nitride hard mask portions  34 , as shown in  FIGS. 11 and 12 . The residual nitride hard mask portions  34  may then be removed to expose the underlying fins  33 , followed by CMP processing which stops at the upper surfaces of the exposed fins, as seen in  FIGS. 13 and 14 . Further etching back of the oxide  35  exposes upper portions of the fins  33 , as well as the protective layer portions  40 , as seen in  FIG. 15 . In this way, the exposed protective layer portions  40  serve as “dummy” dielectric fins which help prevent lateral epitaxial shorts between adjacent devices, as will be appreciated by those skilled in the art. In the final device  30  shown in  FIG. 1 , source and drain regions  50 ,  51  are provided for each respective device, as well as a gate line  52  which extends across the fins  33  and “dummy” dielectric fins  40 . 
     In accordance with another embodiment, the oxide  40 ′ (e.g., Al 2 O 3 ) may be etched back ( FIG. 16 ) prior to removal of the residual nitride portions  34 ′ ( FIG. 17 ). CMP processing of the oxide  35 ′, which stops at the fins  33 ′, may then be performed ( FIG. 17 ). The oxide  35 ′ is etched back to reveal or expose upper portions of the fins  33 ′ and “dummy” oxide fins  40 ′, as seen in  FIG. 19 . 
     While the above-noted embodiments are described with a silicon substrate and fins, it will be appreciated that other suitable semiconductor materials may also be used. By way of example, such materials may include SiGe, Ge, III-V materials, etc. Moreover, in some embodiments, the fins  33 ,  33 ′ may be formed into nanowire fins, such as by the approach described in U.S. patent application Ser. No. 14/182,601 filed Feb. 18, 2014, which is assigned to the present Applicant and is hereby incorporated herein in its entirety by reference. 
     Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.