Abstract:
A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to clock signal generating circuits, and more particularly to a clock signal generator circuit which generates from an input clock signal having an input frequency and input duty cycle, an output clock signal having an output frequency which is a predetermined multiple of the input frequency and an output duty cycle which is a fifty percent duty cycle irrespective of the input duty cycle. 
     Frequency multiplying of clock signals is employed in computer systems for a number of reasons. For example, an accelerated clock signal may be necessary to adequately operate or receive asynchronous input from a storage device, such as a read only memory or ROM, which requires quick read and write speeds. Similarly, a frequency multiplier may be necessary to update data at a time other than the leading edge of an input clock signal pulse. 
     For instance, random access memory (RAM) cells often require precharging before and recharging after each read and write operation during a single clock cycle. In this example, a clock signal having double the frequency of the input clock signal is useful for initiating the precharge, read, recharge and write operations. In such an application, preferably the generated double frequency clock signal is characterized by rising edges simultaneous with the rising and falling edges of the input clock signal, and by falling edges simultaneous with the mid-points of each half-cycle of the input clock signal. A fifty percent duty cycle will ensure such an output signal. 
     According to the background art, frequency doubling with a fifty percent duty cycle output can be achieved by employing a plurality of cascaded inverters forming a tapped delay line. Such prior art design required the total amount of delay achieved by such delay lines to be predetermined according to the input frequency. The output of the delay line was connected to one input of an EXCLUSIVE OR gate. The input clock signal was applied to the input of the tapped delay line and to the second input of the EXCLUSIVE OR gate. By accurately specifying the delay generated by the cascaded inverters, the signal applied to the first EXCLUSIVE OR gate input is delayed from the input clock signal by one quarter cycle, causing the EXCLUSIVE OR gate to generate the appropriate double frequency output clock signal, as described above. The duty cycle of the double frequency signal output from the EXCLUSIVE OR gate is monitored by a control circuit using a counter device to increase or decrease the duty cycle as needed to ensure a fifty percent duty cycle for the output signal. Such a prior art apparatus is shown, for example, in U.S. Pat. No. 4,799,022 , entitled &#34;Frequency Doubler with Duty Cycle Monitor Means,&#34; which is incorporated herein by reference. 
     There are numerous disadvantages inherent in such prior art. First, such prior art is not easily adapted to creating an output signal of some frequency other than double the input frequency (e.g., three or four times the input frequency). Second, the prior art requires knowledge of the input frequency before the circuit can properly function, leaving the accuracy of the output signal&#39;s frequency vulnerable to variations in the input frequency. Third, some prior art frequency multipliers are designed such that they remain unpredictably sensitive to minor variations in temperature. If a frequency multiplier is sensitive to minor variations in temperature, the duty cycle of the output signal may vary from a desired setting, such as fifty percent. This can result in erroneous operation of the &#34;precharge, read, recharge and write&#34; procedure discussed above. 
     SUMMARY OF THE INVENTION 
     Accordingly, one object of the present invention is a clock signal generator without such drawbacks of the prior art. 
     To achieve these and other objects, one aspect of the present invention is a clock signal generator which responds to a first rising edge of an input clock signal by creating an output signal with a decreased period and accelerated frequency. The period of the output signal is gradually increased by the expansion, through the opening and closing of a serial array of feedback gates, of an oscillating feedback loop until the output signal frequency matches a desired multiple of the input clock signal frequency. 
     Expansion of the feedback loop depends upon the time elapsed between a first and second rising edge from an input clock signal. The first rising edge of the input clock signal triggers the propagation of a logic signal through a series of delay elements. Propagation of the logic signal through a single delay element triggers a corresponding and predetermined fractional increase in the length of the feedback loop by causing a next feedback gate to become active and a previous feedback gate to deactivate. A second rising edge from the input clock signal halts propagation of the logic signal through the delay elements and locks the feedback loop length at the predetermined fraction of the input clock signal&#39;s period. The frequency of the resulting output signal is a desired multiple of the input signal frequency. This multiple is in direct proportion to the ratio between the delay within each delay element and the delay between adjacent feedback gates. 
     The feedback loop output signal oscillates by negative feedback techniques employing, for example, an inverting logic gate. As a result of such negative feedback techniques, the output signal from the loop has a fifty percent duty cycle regardless of variations in device temperature. The circuit thus ensures a half-wave output signal and a frequency which matches a desired multiple of the input signal frequency. 
     Also according to the present invention is a method for receiving an input clock signal having first and second transition edges defining a period and frequency of the input clock signal, and generating an output clock signal having a fifty percent duty cycle and a frequency proportionally related to the input clock signal frequency. The method comprises the steps of: delaying an input signal through a first plurality of serially connected delay elements, each of the first plurality of delay elements having an input and an output; selectively connecting at least one of the outputs of the first plurality of delay elements to a common node through at least one of a plurality of gating elements, each of the gating elements having an input, an output and a gating control, preferably formed of transistors; forwarding the delayed input signal to the common node; generating a code signal responsive to the period of the input clock signal through a second plurality of serially connected delay elements, each of the second plurality of delay elements respectively connected to a plurality of encoded outputs; generating a decode signal responsive to the code signal, through a plurality of inputs respectively connected to the plurality of encoded outputs and a plurality of decoded outputs respectively connected to the gating controls; selectively activating only a selected one of the plurality of gating controls; inverting the delayed input signal through the inverting element; forwarding the inverted and delayed input signal to the input of the first plurality of delay elements; and providing the output clock signal to an inverting element after the selected one of the plurality of gating controls is activated. 
     Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings. 
    
    
     BREIF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B illustrate, as examples, first and second stages, respectively, of a clock signal generator circuit utilizing; 
     FIG. 2 illustrates, as an example, a schematic diagram of a delay element of the delay cell depicted in FIG. 3; 
     FIG. 3 illustrates, as an example, a schematic diagram of a delay cell of the clock signal generator circuit depicted in FIGS. 1A and 1B; and 
     FIG. 4 illustrates, as an example, timing diagrams for the clock signal generator circuit depicted in FIGS. 1A and 1B. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIGS. 1A and 1B illustrate first and second stages, respectively, of a clock signal generator circuit utilizing aspects of the present invention. In particular, FIG. 1A illustrates a first circuit stage 20, wherein an input clock signal CLK is connected to the clock inputs of D-type flip-flops 12 and 14. Data input D12 of flip-flop 12 receives a high logic signal V dd . Accordingly, upon each rising edge of input clock signal CLK, signal V dd  is &#34;clocked&#34; into an output Q12 of flip-flop 12. 
     The reset inputs of flip-flops 12 and 14 are connected to a power-up reset signal RETN. At power-up, signal RETN is set at logic low and the outputs Q12 and Q14 of flip-flops 12 and 14, respectively, are reset and remain at logic low until the signal RETN is released to logic high. Following stabilization of the input clock signal CLK, external circuitry 15 releases the signal RETN to logic high. A subsequent single rising edge from the signal CLK causes the output Q12 to register a logic high signal and to remain at logic high until the signal RETN returns to logic low. 
     Similarly, because input D14 is connected to output Q12, after a second rising edge is transmitted by signal CLK output Q14 will also be set to logic high. When output Q14 is set to logic high, output Q14 will be set to logic low. Output Q14 is connected to the input of a buffer 18. The buffer 18 produces a signal HOLD1 referred to below with respect to FIG. 2. 
     Output Q12 is connected to node 16 to form a delay element input signal STRTIN1. After signal CLK transmits a single rising edge, signal STRTIN1 is set at logic high until signal RETN returns to logic low. Signal STRTIN1 provides an input to cascoded delay elements 40a to 40zz. 
     In FIG. 2, a delay element 40b of the present invention is shown in detail. Other delay elements 40a and 40c14 40zz are similarly constructed. A series of inverters 42a to 42d are connected end to end between input D40b and a passgate 44. The number of inverters 42a to 42c must be even to ensure the output of the last inverter 42d is the same logic value as the input to the first inverter 42a. Also entering delay element 40b is signal HOLD1 originating from output Q14 of D-type flip flop 14. Signal HOLD1 is connected to a second even numbered series of inverters 46a and 46b. A third signal input to delay element 40b is the output enable signal OE, originating from the output of an inverter 28 which inverts signal RETN to yield the signal OE. The signal OE is received at the gate input of a common NMOS tie-down transistor 50. 
     Delay element 40b functions in one of three modes (initiation mode, delayed pass-through mode or latch mode) depending on the status of the three input signals STRTIN1, HOLD1 and OE. While signal RETN remains at a logic low status, delay element 40b is in initiation mode. Signal OE remains at a logic high status, activating the tie-down transistor 50. Tie-down transistor 50 forwards a logic low signal from its source at node 51 to delay element output Q40b tied to node 53. Thus, during initiation mode all delay element outputs Q40a to Q40zz remain at logic low. 
     After input clock signal CLK has stabilized and power-up reset signal RETN switches to logic high, delay element 40b functions in a second mode, as a delayed pass-through element. After reset signal RETN is released to logic high, signal OE switches to logic low and the tie-down transistor 50 is deactivated, allowing output Q40b to assume whatever signal is passed through the inverters 42a to 42d and the passgate 44. A control input 45 of passgate 44 is connected to the output of the inverter 46b in such a manner that the passgate 44 is active only as long as signal HOLD1 is at a logic high. Signal HOLD1 is set to logic high at circuit initiation and does not change until the second rising edge from clock input signal CLK arrives at flip-flop 14, as explained above in relation to FIG. 1. Thus, after circuit initiation, and until a second rising edge from clock input signal CLK forces a change in signal HOLD1, delay element 40b functions as a simple delayed pass-through element for signal STRTIN1 with a total delay fixed by the number of inverters 42a to 42d placed between input D40b and output Q40b combined with the delay of passgate 44. In a preferred embodiment, there are four inverters 42a to 42d, as shown in FIG. 2. 
     Referring again to FIG. 1A, each delay element input D40 is connected to output Q40 of the previous delay element, originating with signal STRTIN1 at input D40a. Thus, once the logic state of output Q40a changes from logic low to logic high, a logic high signal propagates from one delay element to the next, until such propagation is halted by a change in signal HOLD1. The total period of time from the change in signal STRTIN1 at input D40a to the termination of propagation caused by a switch in the logic level of signal HOLD1 closely approximates the period of input clock signal CLK. Because the propagation process automatically begins and ends in direct response to the input clock signal CLK, prior knowledge of the input signal frequency is not required to properly multiply the frequency as desired. 
     The total delay caused by inverters placed within a single delay element, such as 40b, between an input, such as D40b, and an output, such as Q40b, approximates the margin of error in determining the period of input clock signal CLK. For example, returning to FIG. 2, if each inverter 42a to 42d between input D40b and output Q40b of delay element 40b delays the input signal by 0.15 ns, while the passgate 44 delays the input signal by 0.07 ns, then the maximum possible error for the period of the output frequency is 0.67 ns. 
     Once a second rising edge from input clock signal CLK forces signal HOLD1 to switch to logic low, delay element 40b functions in its third and final mode, as a signal latch, holding output Q40b at its last logic level. When signal HOLD1 is at logic low, the passgate 44 is deactivated and no longer allows signal STRTIN1 to pass through from inverter 42d to output Q40b. Because a passgate 48 is connected to the inverters 46a and 46b in a manner opposite to the connections of the passgate 44 to the same inverters 46a and 46b, the passgates 48 and 44 are never active at the same time. Thus, simultaneous with deactivation of the passgate 44, passgate 48 is activated by a logic low propagating through inverters 46a and 46b and originating from signal HOLD1. 
     The passgate 48 performs a signal latching function in that it&#39;s input is connected to its output via a buffer 52. Because output Q40b is also connected to the output of the passgate 48, the logic level of output Q40b at the time signal HOLD1 switches to logic low remains at that logic level until the circuit is again reset by a reversal in the logic level of signal RETN. If, therefore, a logic high signal has propagated to output Q40b by the time signal HOLD1 switches to logic low, then the logic level of output Q40b will remain at logic high. The function and three functional modes of delay element 40b are identical for delay elements 40a and 40c-40zz. 
     Referring next to FIG. 3, a detailed schematic of delay cell 80b is shown. Delay cell 80b comprises delay element 40b and feedback gate 60b. Delay element 40b and feedback gate 60b function together to lengthen feedback loop 22, shown in FIG. 1A. In a preferred embodiment, the delay established within feedback loop 22 after the second rising edge from signal CLK occurs, will equal one-half the period of the input clock signal CLK. As will be subsequently explained, a feedback loop delay equal to one-half the period of input signal CLK results in an oscillating output signal with a frequency equal to the frequency of the input clock signal CLK. 
     By adjusting the length of feedback loop 22, the delay cells such as 80b in FIG. 1A ensure the intermediate output signal HLFOUT of the first stage 20 is proportional to the input clock signal CLK with a 50% duty cycle. In the preferred embodiment there are twice as many inverters 42a to 42d in each delay element as there are inverters 78b and 79b, shown in FIG.3, in each feedback gate. Thus, the length of feedback loop 22 in a preferred embodiment, once fixed, creates an oscillating signal with the same total period as the period of the input clock signal CLK. If the ratio of inverters 42 to inverters 78 and 79 in an alternative embodiment were six, then the output signal of the first stage 20 would have three times the frequency of input signal CLK. 
     In FIG. 3, feedback gate 60b is comprised of an AND gate 58b, inverters 66b, 70b and 78b, and two passgates 72b and 77b. The feedback gate 60b is controlled by the AND gate 58b. Delay element output Q40b is connected at a node 56 to the inverter 66b and to an input 62b of the AND gate 58b. An AND gate input 64b receives a logic signal from the output of an inverter 66c in the subsequent delay cell (shown in FIG. 1A). The AND gate 58b functions as a comparator, ensuring that the passgate 72b is active only when the logic levels at the inputs 62b and 64b are equivalent--that is, passgate 72b is active only when the logic levels of the outputs Q40b and Q40c are 1 and 0, respectively. When active, the passgate 72b allows the signal at a node 75b along a delay line 76 to pass through to a node 73b on a feedback line 74, thereby closing the feedback loop 22. When deactivated, the passgate 72b ensures the signal at node 75b will propagate further along delay line 76 to the subsequent feedback gate, thereby increasing the total delay of the feedback loop 22. 
     A passgate 77b, located between inverters 78b and 79b on the delay line 76, is connected to V dd  and ground in such a way as to ensure it is always active. The passgate 77b functions as a short-term delay device to compensate for the delay caused by passgate 44 in delay element 40b. In a preferred embodiment shown in FIG. 1A, there is only one passgate 77 for every two passgates 44 of FIG. 2. This two-to-one passgate ratio ensures the total delay ratio between delay elements 40 and feedback gates 60 remains two-to-one. If a higher output frequency multiple were desired, the number of passgates 77 would decrease proportionally. 
     Inverters 78b and 79b are identical to inverters 42a to 42d in delay element 40b. Inverters 78b and 79b provide a desired fraction of the propagation delay caused by delay element 40b. As noted above with respect to inverters 42a to 42d in FIG. 2, the number of inverters 78 and 79 along delay line 76 must be even to ensure the output of each set of inverters equals the input. 
     Referring again to FIG. 1A, feedback loop 22 includes delay line 76 and feedback line 74, and passes through a plurality of feedback gates including 60a to as far as feedback gate 60zz (not shown). Feedback loop 22 feeds from an output node 92 of a NAND gate 90 and feeds to an input node 94. The output node 92 supplies an intermediate output signal to an inverter 98 which, in turn, supplies a signal HLFOUT to the second stage 30 of the multiplier circuit. The signal RETN is received by a node 96. During circuit initiation, when signal RETN is active and at logic low, the output node 92 of NAND gate 90 is fixed at logic high. Thus, signal HLFOUT is fixed at logic low. After signal RETN releases to logic high, NAND gate 90 acts as an inverter and the logic level at the node 94 determines the logic level at the output node 92 of the NAND gate 90. As a high logic level propagates from one delay element to the next, feedback loop 22 and the period of signal HLFOUT grow longer, as explained above with reference to FIG. 3. Because feedback loop 22 is self-oscillating, creating a half-wave output, once the length of feedback loop 22 is fixed signal HLFOUT will have a fifty percent duty cycle until the circuit is reset and feedback loop length adjusts to any changes in the input clock signal CLK. Moreover, the duty cycle of signal HLFOUT will not vary with minor variations in temperature to the multiplier circuit since the half-wave signal is characteristic of an oscillating inverter tied to a delayed feedback loop. 
     The total length and delay of the feedback loop 22 are fixed when signal HOLD1 switches to logic low. The logic level of output Q14 switches simultaneously with the switching of signal HOLD1. Output Q14 sends signal RETN2 to the second stage 30, shown in FIG. 1B, of the multiplier circuit via node 5. Thus, the delay elements of the second stage 30 remain in initiation mode, in a similar manner as explained above with respect to FIG. 2, until the output Q14 switches to logic high and signal HOLD1 fixes the period of signal HLFOUT. 
     Shown in FIG. 1B, the second stage 30 is similar to first stage 20 in all but three important respects. First, in second stage 30 input signals CLK and RETN no longer originate from external circuitry. The signal CLK is replaced by first stage signal HLFOUT via node 7 and the signal RETN is replaced by signal RETN2 via node 5. Second, approximately one-half the number of delay cells used in the previous stage are necessary to ensure the frequency is doubled. Third, and most important, an inverter 34 appears between inverter 98 and the clock input of a flip-flop 114. The inverter 34 is so placed to ensure that flip-flop 114 &#34;clocks&#34; its input signal on a falling edge of second stage clock input signal HLFOUT, instead of on a rising edge, as was the case for flip-flop 14 in first stage 20. This falling edge sensitivity ensures the delay cells of second stage 30 propagate for only one-half the period of signal HLFOUT, according to a method of frequency multiplying known to those skilled in the art. Second stage 30 is incorporated in a preferred embodiment of the present invention to minimize the number of propagating inverters within a single delay element 40, shown in FIG. 1A, and to minimize thereby the margin of error of first stage 20, as explained above. 
     FIG. 4 illustrates the operation of the circuit in FIGS. 1A and 1B. Signal V HLFOUT , measured from the output of inverter 98, is shown as a square wave of decreasing frequency and increasing period. The increase in period occurs from the first moment both V CLK  and V RETN  are high until V CLK  registers a second rising edge. Thus, signal V HLFOUT  illustrates the growth of feedback loop 22 as a logic high signal propagates through delay elements 40a, 40b, etc. until a second rising edge is encountered from signal CLK. 
     In an example of operation, signal V HLFOUT  is initially fixed at logic low within time 82. This fixed low signal is caused by signal RETN, shown in FIG. 1A, which activates a tie-down transistor 52 connected feedback 74. When active, the tie-down transistor 52 pulls feedback line 74 to logic low, until the transistor is deactivated by a change in signal RETN at time t1. 
     The first change in signal V HLFOUT  is induced after the occurrence of a single rising edge on signal V CLK  at time t2 with signal V RETN  at logic high. This clock pulse changes signal V STRTIN1  to a logic high position. Once a logic high signal propagates through a delay element 40a, as explained above with reference to delay element 40b, a feedback gate 60a will activate a single stage of feedback loop 22. As feedback loop 22 grows, the period of signal V HLFOUT  grows accordingly until a second rising edge on signal CLK occurs at time t3, triggering a drop in signal V HOLD1 . The total number of cycles signal V HLFOUT  will go through between the first and second rising edges of signal V CLK  may be far more than illustrated here. All such cycles may not be clearly illustrated within a figure of this scale. Also, while signals V STRTIN1  and V HOLD1  are shown to change only after input clock signal VOL K  reaches a fully high voltage level, such response may occur at a lower level along a rising edge near times t2 or t3, depending upon the response characteristics of flip-flops 12 and 14. 
     It should be reiterated here that the function of multiplying an input clock signal need not be accomplished with a second stage 30 with flip-flops triggered on the rising and falling edges of an input signal. Instead, by increasing the ratio of the number of inverters 42a to 42d in FIG. 2 to the number of inverters 78b and 79b in FIG. 3, the feedback loop 22 can represent a reduced fraction of the period of input signal CLK. This reduced fraction will ensure signal HLFOUT represents a desired frequency multiple of signal CLK with a fifty percent duty cycle. 
     However, as explained above, an increase in the number of inverters 42 will also increase the margin of error. If, for example, eight inverters 42 with a delay of 0.15 ns each are placed within each delay element 0, the total propagation delay within each delay element will be 1.2 ns. If the input signal has a frequency of 50 MHz, or a period of 20 ns, the margin of error would be approximately ±6%, or twice the error margin with only four inverters 42a to 42d, as shown in a preferred embodiment. There exists, therefore, a need to minimize either the number of inverters 42 appearing within each delay element or the delay of each inverter. If faster inverters 42 were used in each delay element 40, second stage 30 would not be necessary. Thus, the preferred embodiment serves to minimize the margin of error encountered in multiplying the frequency of signal CLK, while employing the frequency multiplying apparatus and method described within the scope of the appended claims. 
     FIG. 4 also assists in distinguishing second stage 30 from first stage 20. The key distinction between the two stages can be seen in the time period 88 lapsed between the signal V STRTIN1  and the signal V HOLD1  as compared to the time period 90 lapsed between the signal V STRTIN2  and the signal V HOLD2 . Because signal HLFOUT is inverted before being forwarded to the flip-flop 114 in the second stage 30, the time period 90 between the onset of propagation in the delay elements caused by signal STRTIN2 and the cessation of such propagation caused by signal HOLD2 is one-half the period of signal HLFOUT. 
     The remainder of second stage 30 functions in the same manner as explained above with respect to first stage 20. The resulting output signal DBLOUT represents the input clock signal CLK with a fifty percent duty cycle and a doubled frequency. If desired, succeeding stages could operate in the same manner as the second stage 30 to further increase the final output frequency. 
     Although the various aspects of the present invention have been described with respect to its preferred embodiment, it will be understood that the invention is entitled to full protection within the full scope of the appended claims.