Abstract:
A memory array apparatus with shorter data accessing time is proposed. The memory array apparatus comprises a register administrator and a plurality of data registers between a micro controller and at least one memory array. The data to be accessed are divided into a plurality of data blocks according to a predetermined data unit. The data block is firstly stored in corresponding data register and then read by the main frame or stored into the corresponding memory array. At the same time, the next data block is stored in the corresponding data register through circuit switched by the micro controller. The pending time of the main frame and the data accessing time can be advantageously reduced.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a memory array apparatus, especially to a memory array apparatus with shorter data accessing time to reduce waiting of a main frame, and method for the same. 
     BACKGROUND OF THE INVENTION 
     The flash memory has the advantages of compact size, low power consumption, shock resistance and non-volatility, and is suitable for portable electronic devices such as personal communication apparatus and palm computer. 
     FIG. 1 shows a conventional flash memory array apparatus, which mainly comprises an interface controller  13 , a micro-controller  15 , a data register  17 , a data input/output port  18  and a flash memory array  19 . The interface controller  13  of the flash memory array apparatus is connected to a main frame  10  through a bus  11 . When data is to be stored into the flash memory array  19 , the main frame  10  commands the micro-controller  15  to divide the data to be stored into a plurality of data blocks according to a predetermined data unit such as 512 bytes. Each data block is firstly stored in the data register  17  and then stored into the flash memory array  19  through the data input/output port  18 . On the contrary, the data transmission path is reversed when the data is to be read. 
     However, in above-mentioned flash memory array apparatus, the data transmission speed between the data register  17  and the flash memory array  19  is relatively low. Moreover, the above-mentioned flash memory array apparatus is designed to have single data register  17  and single flash memory array  19 , the main frame  10  requires a waiting time before the data transmission between the data register  17  and the flash memory array  19  is completed. The data accessing speed is not satisfactory. 
     SUMMARY OF THE INVENTION 
     It is the object of the present invention to provide a memory array apparatus with shorter data accessing time to reduce waiting of a main frame, and method for the same. 
     In one aspect of the present invention, the data to be accessed is divided into a plurality of data blocks and a plurality of data registers are used to store temporarily the separate data block. The data accessing time between the memory array and the data register is exploited to the data transmission for the next data block, whereby the waiting time of main frame can be reduced. 
     The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which: 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 shows the block diagram of a conventional flash memory array apparatus. 
     FIG. 2 shows the block diagram of a preferred embodiment of the present invention. 
     FIG. 3 shows the storing flowchart of the preferred embodiment in FIG.  2 . 
     FIG. 4 shows the timing diagram of the preferred embodiment in FIG.  2 . 
     FIG. 5 shows the reading flowchart of the preferred embodiment in FIG.  2 . 
     FIG. 6 shows the block diagram of another preferred embodiment of the present invention. 
     FIG. 7 shows the timing diagram of the preferred embodiment in FIG.  6 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 shows a block diagram of a preferred embodiment of the present invention. The memory array apparatus of the present invention mainly comprises an interface controller  23 , a micro-controller  25 , a register administrator  30 , a first data register  271 , a second data register  272 , a first data I/O port  281 , a second data I/O port  282 , a first memory array  291  and a second memory array  292 . The interface controller  23  is connected to a main frame  20  through a main bus  21  and is also connected to the micro-controller  25 . The register administrator  30  has at least one bus switch  31 , which is connected to the main frame  20  through the main bus and connected to the micro-controller  25 . The bus switch  31  is controlled by the micro-controller  25  to selectively communicate with one of the two data registers  271  and  272 . The data I/O ports  281  and  282  are connected to the data registers  271  and  272 , respectively, and corresponding memory arrays  291  and  292 . 
     FIGS. 3 and 5 show the flowcharts of the present invention. The storing process for main frame  20  to store data into the memory arrays  291  and  292  comprises following steps: 
     Step  301 : The main frame  20  informs the micro-controller  25  of storing operation through the main bus  21  and the interface controller  23 . 
     Step  302 : The bus switch  31  of the register administrator  30  is controlled by the micro-controller  25  and selectively switched to a first circuit  3171  connected with the first data register  271 . 
     Step  303 : The micro-controller  25  divides the data to be stored into a plurality of data blocks with a predetermined data unit. In the present embodiment, the data unit is in terms of logical array block (LAB); with a blocksize 512 bytes. The plurality of data blocks contains a first data block stored temporarily in the first data register  271 . The first data block belongs to an N data block series. The capacity of all data registers is larger than or equal to 512 bytes. Afterward, steps  304  and  314  are simultaneously executed after the temporary storing process. 
     Step  304 : The first data register  271  is controlled by the micro-controller  25  to store the first data block (N data block) into the memory array  291  through the first data I/O port  281 . The memory is characterized by a relative long accessing time. Therefore, the micro-controller  25  executes the step  314  simultaneous with the step  304 . 
     Step  314 : The bus switch  31  of the register administrator  30  is controlled by the micro-controller  25  and selectively switched to a second circuit  3172  connected with the second data register  272 . The second data block (N+1 data block) of the data blocks from the main frame  20  is stored temporarily in the second data register  272 . 
     Step  305 : Whether the data stored in the first data register  271  is completely stored in the memory array  291 ? If true, the steps  306  and  316  are simultaneously executed. 
     Step  306 : Due to the relative long accessing time of the memory, the second data block (N+1 data block) of the data blocks has been stored temporarily in the second data register  272 . At this time, the second data block (N+1 data block) of the data blocks stored temporarily in the second data register  272  is moved to the second memory array  292  through the second data I/O port  282 . 
     Step  316 : Simultaneously with the step  306 , the bus switch  31  is controlled by the micro-controller  25  and again switched to the first circuit  3171  connected with the first data register  271 . The next first data block (N data block) is stored into the first data register  271 . 
     Step  307 : Whether the data stored in the second data register  272  is completely stored in the memory array  292 . The steps  304  to  307  are repeatedly executed until all data are stored into the memory array. 
     FIG. 4 shows the timing diagram of this embodiment. The table contents in row direction represent the data register and the table contents in column direction represent processing period. 
     In first phase, the main frame  20  sends the first data block to the first data register  271 , and the operation is symbolized by H→1B. At this time, the second data register  272  is idle. 
     In second phase, the first data block is moved from the first data register  271  to the memory array  291  and the operation is symbolized by 1B→1M. At this time, the main frame  20  sends the second data block to the second data register  272 , and the operation is symbolized by H→2B. 
     In third phase, the second data block is moved from the second data register  272  to the second memory array  292 , and this operation is symbolized by 2B→2M. At this time, the main frame  20  sends the next first data block to the first data register  271 , and the operation is symbolized by H→1B. 
     In fourth phase, the first data block is moved from the first data register  271  to the first memory array  291  and the operation is symbolized by 1B→1M. At this time, the main frame  20  sends the second data block to the second data register  272 , and the operation is symbolized by H→2B. The operation in this phase is similar to the operation in the second phase. In other word, the operations in the second and third phases are alternatively executed until all data are stored. 
     As can be seen from FIG. 4, the main frame  20  has no idle time in all phase of operation; the efficiency thereof can be fully exploited. 
     FIG. 5 shows the flowchart of reading operation. 
     Step  501 : the main frame  20  informs the micro-controller  25  of reading operation from the first memory array  291  and the second memory array  292 . 
     Step  502 : The first data block is moved from the first memory array  291  to the first data register  271 . 
     Step  503 : The bus switch  31  of the register administrator  30  is controlled by the micro-controller  25  and selectively switched to a first circuit  3171  connected with the first data register  271 . 
     Step  513 : Simultaneously with the step  503 , the second data block is moved from the second memory array  292  to the second data register  272 . Afterward, a step  505  is executed. 
     Step  504 : The main frame  20  reads the first data block stored in the first data register  271  through the first circuit  3171 . 
     Step  505 : Waiting and detecting whether the second data block is completely stored in the second data register  272 . 
     Step  506 : The bus switch  31  of the register administrator  30  is controlled by the micro-controller  25  and selectively switched to a second circuit  3172  connected with the second data register  272 . 
     Step  517 : Simultaneously with the step  507 , the next first data block is moved from the first memory array  291  to the first data register  271 . 
     Step  508 : Waiting and detecting whether the next first data block is completely stored in the first data register  271 . Afterward, steps  503  to  508  are repeatedly executed until all data are read by the main frame  20 . 
     FIG. 6 shows the block diagram of another preferred embodiment of the present invention. The first preferred embodiment of the present invention is exemplified with two data registers  271  and  272 , and two memory arrays  29  land  292 . However, the number of the data registers is not necessarily matched with the number of the memory arrays. In the second preferred embodiment of the present invention, the memory array apparatus has three data registers  271 ,  272  and  273 , which are used with two I/O ports  281  and  282  and two memory arrays  291  and  292 . To schedule the data blocks in the three data registers  271 ,  272  and  273 , the register administrator  30  has a first I/O switch  35  and a second I/O switch  37 . The first I/O switch  35  is connected to the three data registers  271 ,  272  and  273 , and the first I/O port  281 . The second I/O switch  37  is connected to the three data registers  271 ,  272  and  273 , and the second I/O port  282 . The first I/O switch  35  and the second I/O switch  37  are controlled by a switch controller  33  connected to an interface controller  25 . The register administrator  30  further has a bus switch  31  to schedule data transmission path with the first I/O switch  35  and the second I/O switch  37 . 
     FIG. 7 shows the timing diagram of this embodiment. The table contents in row direction represent the data register and the table contents in column direction represent processing phase. 
     In a first phase, the main frame  20  sends the first data block to the first data register  271 , and the operation is symbolized by H→1B. At this time, the second data register  272  and the third data register  273  are idle. 
     In a second phase, the first data block is moved from the first data register  271  to the memory array  291  and the operation is symbolized by 1B→1M. At this time, the main frame  20  sends the second data block to the second data register  272 , and the operation is symbolized by H→2B. At this time, the third data register  273  is still idle. 
     In a third phase, the second data block is moved from the second data register  272  to the second memory array  292 , and this operation is symbolized by 2B→2M. At this time, the main frame  20  sends the third data block to the third data register  273 , and the operation is symbolized by H→3B. At this time, the first data register  271  is idle and this time can be used as writing time of the first memory array  291 . 
     In a fourth phase, the first data block is moved from the third data register  273  to the memory array  291  and the operation is symbolized by 3B→1M. At this time, the main frame  20  sends the first data block to the first data register  271 , and the operation is symbolized by H→1B. At this time, the second data register  272  is idle and this time can be used as writing time of the second memory array  292 . 
     In a fifth phase, the first data block is moved from the first data register  271  to the second memory array  292  and the operation is symbolized by 1B→2M. At this time, the main frame  20  sends the second data block to the second data register  272 , and the operation is symbolized by H→2B. At this time, the third data register  273  is idle and this time can be used as writing time of the first memory array  291 . For the main frame  20  and all data registers, the operations thereof are similar to those in the second phase. 
     In a sixth phase, the operation in this phase is similar to the operation in the third phase. In other word, the operations in the second to fourth phases are sequentially executed until all data are stored. 
     As can be seen from FIG. 7, the main frame  20  has no idle time in all phase of operation even though certain data register is idle in that phase; the efficiency thereof can be fully exploited. 
     Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.