Abstract:
Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to the manufacture of semiconductor devices having interconnects. In particular, the present disclosure relates to profile control and capacitance reduction for semiconductor devices in the 14 nanometer (nm) technology node and beyond. 
       BACKGROUND 
       [0002]    In a semiconductor integrated circuit (IC) fabrication process, the back end of line (BEOL) processing results in interconnects including alternating metal (e.g., copper) and interlayer dielectric (ILD) layers, with vias through the ILD layers connecting the metal layers. With current processes, electrical shorts in interconnects (VxMx) and time dependent dielectric breakdown (TDDB) in conductive vias (Vx) can occur due to charge chamfer angle. Specifically, an interconnect becomes misaligned with the underlying via, causing an overlay, creating a charge chamfer angle. TDDB is the most significant scaling limiter for BEOL and forces manufacturers to use self-aligned double patterning (SADP) lithography. Moreover, another drawback with current processing is ILD damage caused by chemical mechanical polishing (CMP) after metallization and subsequent etch stop layer formation using plasma enhanced chemical vapor deposition (PECVD) to deposit a nitrogen doped carbide (NDC) or silicon carbon nitride (SiCNH or NBlock) diffusion layer. Electron energy loss spectroscopy (EELS) line scan demonstrates that almost 2.5 nanometers (nm) of damage can occur in the ILD after integration which undesirably increases lateral capacitance. 
         [0003]    A need therefore exists for improved methodology and an apparatus that reduces the risk of electrical short and ILD damage during semiconductor manufacturing. 
       SUMMARY 
       [0004]    An aspect of the present disclosure is a method and device for reducing capacitance and improving profile control in semiconductor manufacturing. Another aspect of the present disclosure is to reduce via chamfer and TDDB. 
         [0005]    Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims. 
         [0006]    According to the present disclosure, some technical effects may be achieved in part by a method including: forming metal vias in a first dielectric layer; forming a graded interlayer (ILD over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon (α-SiC:H) film over the metal layer. 
         [0007]    Aspects of the present disclosure include forming the α-SiC:H film by hot wire chemical vapor deposition (HWCVD). Another aspect includes forming the graded ILD with an ultra low-k dielectric (ULK) material. Further aspects include forming the graded ILD with an upper portion more porous than a lower portion. Additional aspects include forming the graded ILD with a third portion lower than and more porous than the lower portion of the graded ILD. Yet further aspects include forming the upper portion of the graded ILD to a thickness of 50 to 70 nm. Other aspects include forming the lower portion of the graded ILD to a thickness of 5 to 15 nm; and forming the third portion of the graded ILD to a thickness of 25 to 35 nm. Still further aspects include planarizing the metal layer by CMP prior to forming the α-SiC:H film. Aspects include forming a second metal layer over the α-SiC:H film. Additional aspects include forming an etch stop layer between the graded ILD and metal vias. Further aspects include forming the α-SiC:H film to a thickness of 10 to 20 nm. 
         [0008]    Another aspect of the present disclosure is a device including: metal vias formed in a first dielectric layer; a graded ILD formed over the metal vias, the graded ILD having upper portion more porous than a lower portion; a metal layer formed in the graded ILD over one of the metal vias; and a α-SiC:H film formed over the metal layer. 
         [0009]    Aspects include the α-SiC:H film being formed by HWCVD. Other aspects include the graded ILD comprises an ULK material. Additional aspect include an etch stop layer being formed between the graded ILD and the metal vias. Still further aspects include a second metal layer being formed over the α-SiC:H film. Another aspect includes the α-SiC:H film having a thickness of 10 to 20 nm. Additional aspects include the graded ILD including a third portion lower than and more porous than the lower portion of the graded ILD. 
         [0010]    Yet another aspect of the present disclosure is a method including forming metal vias in a first dielectric layer; forming a graded ILD over the metal vias, the graded ILD having upper and lower portions that are more porous than a middle portion; forming a metal layer in the graded ILD over one of the metal vias; planarizing the metal layer by CMP; and forming a α-SiC:H film over the metal layer by HWCVD. Aspects include forming the α-SiC:H film to a thickness of 10 to 20 nm. 
         [0011]    Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which: 
           [0013]    EEGs  1  through  3  schematically illustrate a process flow to produce a semiconductor device, in accordance with an exemplary embodiment; and 
           [0014]      FIG. 4  schematically illustrates a semiconductor device, in accordance with an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” 
         [0016]    The present disclosure addresses and solves the current problems of electrical shorts and ILD damage attendant upon forming metal interconnects during semiconductor manufacturing. Methodology in accordance with embodiments of the present disclosure includes forming metal vias in a first dielectric layer; forming a graded ILD over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon (α-SiC:H) film over the metal layer. 
         [0017]    Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
         [0018]    Adverting to  FIG. 1 , vias  101  are formed in a dielectric layer  103 . Vias  101  are filled with a metal (e.g., copper (Cu)) and include a barrier liner  105  formed around side and bottom surfaces of vias  101 . Etch stop layer  107  is deposited over the vias  101  and dielectric layer  103 . Etch stop layer  107  is used to drastically slow the etch rate, providing a stopping point of high accuracy. Etch stop layer  107  can be formed to a thickness of 10 to 20 nm and may be formed of materials such as NDC, NBLOK, silicon carbide (SiC), or boron-doped SiC. 
         [0019]    A graded ULK dielectric layer  109  (rather than the uniform ULK dielectric layer of current processes) is formed over the etch stop layer  107 . The graded ULK dielectric layer  109  includes three regions  109   a ,  109   b , and  109   c . The middle region  109   b  is the densest region. Upper region  109   a  is more porous (i.e., less dense) than the middle region  109   b . Lower region  109   c  is also more porous (i.e., less dense) than middle region  109   b . Upper region  109   a  may be formed to a thickness of 50 to 70 nm. Middle region  109   b  may be formed to thickness of 5 to 15 nm. Lower region  109   c  may be formed to a thickness of 25 to 35 nm. 
         [0020]    The porosity of the regions can be adjusted by adjusting an amount of porogen and a UV curing process. Exemplary materials used for the graded ULK dielectric layer  109  include carbon doped oxide dielectrics comprised of Si, C, O, and H (SiCOH) with a dielectric constant of 2.4 to 2.6. The stack of  FIG. 1  further includes a first metal layer  111  and second metal layer  113  separated by hard mask  115 , which may be formed of titanium nitride (TiN).  FIG. 1  illustrates a stack formation prior to additional lithography processes (not shown for illustrative convenience) performed on the stack. 
         [0021]    As shown in  FIG. 2 , a metal layer  201  is formed in the graded ULK dielectric layer  109  above vias  101 . The metal layer  201  is connected to one of vias  101 . Excess metal produced from the deposition of the metal layer  201  is removed with CMP to planarize an upper surface of the metal layer  201  and the graded ULK dielectric layer  109 . Examples of metals used for the metal layer  201  include copper and barrier metal (tantalum nitride/tantalum (TaN/Ta) or TaN/Ta/cobalt (Co), ruthenium (Ru) or any other metal barrier. 
         [0022]    In  FIG. 2 , the metal layer  201  is aligned over one of the vias  101  and is not shifted or deviated (i.e., no charge chamfer angle is present) in a lateral direction towards an adjacent via  101 . Thus, the lateral capacitance between adjacent vias can be controlled. The graded ULK dielectric layer  109  helps maintain the aligned orientation of the metal layer  201  during processing and prevents any overlay error of the metal layer  201  on the via  101 . No electrical short occurs because no overlay error exists, and the metal layer  201  is properly aligned over the via  101 , as shown on  FIG. 2 . 
         [0023]    Adverting to  FIG. 3 , the etching process can be controlled, and the proper chamfer angle can be maintained with the presence of an α-SiC:H film  301  serving as a barrier layer and formed over the metal layer  201  by HWCVD. The α-SiC:H film  301  may be formed to a thickness of 10 to 20 nm. 
         [0024]    Conventional methods, such as PECVD, deposit a barrier layer such as NDC or NBlock which results in plasma induced damage (PID) of an underlying dielectric layer such as the ILD. With HWCVD, PID can be eliminated, and resistance capacitance (RC) can be reduced up to 6.5%. Further, TDDB performance can be improved, since CMP related damage can be recovered with the α-SiC:H film  301  formed by HWCVD. HWCVD does not involve any ion bombardment or ultraviolet (UV) radiation and, therefore, eliminates the possibility of related atomic rearrangement and defects formed in the graded ULK dielectric layer  109 . HWCVD uses a hot or high temperature filament (tungsten or tantalum) to chemically decompose a source gas to cause a surface to be coated with a thin film containing silicon present in the silane gas source. The temperature of the filament can rage from 1500° to 2100° C. 
         [0025]    As shown in  FIG. 4 , a resulting semiconductor device having multiple metal layers is produced in accordance with the exemplary embodiment. Graded ULK dielectric layers  109  are formed for each the metal layers depicted in this figure. The α-SiC:H film  301  is formed between each pair of the metal layers. Inter capacitance  401  can be optimized with the present methodology which prevents damage to the graded ULK dielectric layers  109  and prevents electrical shorts between adjacent vias  101 . 
         [0026]    The embodiments of the present disclosure can achieve several technical effects, including improved metal wiring resistance (RS) uniformity, decreased electrical shorts in interconnects, and reduced TDDB in a semiconductor device. The present disclosure enjoys industrial applicability in any of various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, particularly for 14 nm technology nodes and beyond. 
         [0027]    In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.