Abstract:
An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2010-0014608, filed on Feb. 18, 2010, the contents of which are hereby incorporated herein by reference in their entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The present invention relates to a clock generating circuit and method, and more particularly, to an internal clock generating circuit and method to generate an internal clock signal with a data signal. 
         [0004]    2. Description of the Related Art 
         [0005]    Most semiconductor chips include an internal clock to generate an internal clock signal. The internal clock signal is used as a reference signal for controlling various internal signals in appropriate timing, so that the data, which is externally supplied, can be processed in appropriate ways. 
         [0006]    Most of conventional internal clock generating circuits include a phase-locked loop 
         [0007]    (PLL) or a delay-locked loop (DLL) to generate the internal clock signal. The conventional internal clock generating circuits receive an external clock signal. And, the external clock signal is locked with the PLL or the DLL to generate the internal clock signal. 
         [0008]    However, in the conventional internal clock generating circuits, an extra signal line is required for receiving the external clock signal. The extra signal line causes the constitution of the internal clock generating circuit to be more complicated. And, in the conventional internal clock generating circuits, an extra locking time is required for locking the extra clock signal. The extra locking time causes the operating speed of the internal clock generating circuit to be declined. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention is directed to an internal clock generating circuit and method to generate an internal clock signal with a data signal without using the external clock signal. 
         [0010]    According to an aspect of the present invention, there is provided a transition detecting block for detecting transitions in a data signal to generate a data transition information signal; and an internal clock generating block for generating and storing a period digital data signal when detecting the unit period of the data signal in a period confirming mode, and generating an internal clock signal based on the data transition information signal in an internal clock generating mode, wherein the internal clock signal repeatedly transitions between HIGH and LOW voltage levels every time a waiting time is passed following a transition in the data signal, and wherein the waiting time is dependent on the period digital data. 
         [0011]    According to the internal clock generating circuit of the present invention, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple circuit structure. And, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. Also, the internal clock signal is generated based on the data signal, so that it is easy to control the set-up and hold for data. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain aspects of the invention. 
           [0013]      FIG. 1  is a drawing of an internal clock generating circuit according to an embodiment of the present invention; 
           [0014]      FIG. 2  is a timing diagram for explaining operation modes of the internal clock generating circuit of the present invention; 
           [0015]      FIG. 3  is a diagram illustrating the transition detecting block of  FIG. 1  in detail; 
           [0016]      FIG. 4  is a diagram illustrating the internal clock pulse generating part of  FIG. 1 ; 
           [0017]      FIG. 5  is a diagram illustrating the half period transition unit of  FIG. 4  in detail; 
           [0018]      FIG. 6  is a diagram illustrating the rising detection group of  FIG. 5  in detail; 
           [0019]      FIG. 7  is a diagram illustrating the falling detection group of  FIG. 5  in detail; 
           [0020]      FIG. 8  is a diagram illustrating the rising-driving group of  FIG. 5  in detail; 
           [0021]      FIG. 9  is a diagram illustrating the falling-driving group of  FIG. 5  in detail; and 
           [0022]      FIG. 10A  and  FIG. 10B  are timing diagrams for the operation of the internal clock generating circuit of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0023]    The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings 
         [0024]    The internal clock generating circuit of the present invention generates an internal clock signal using a data signal. And, the logic state of the data signal at the current unit period can be same as or different from the previous unit period. 
         [0025]    Referring to  FIG. 1 , the internal clock generating circuit of the present invention includes a transition detecting block  100  and an internal clock generating block BGIC. The transition detecting block  100  detects transitions in an input data signal DIN, and generates ‘data transition information’ in the form of one or more data transition information signals indicative of the timing of transitions in the data signal. In this embodiment, a rising transition confirmation signal PCTA_R and a falling transition confirmation signal PCTA_F are data transition information signals carrying the ‘data transition information’. 
         [0026]    The internal clock generating block BGIC alternately operates in a period confirming mode MTDG or an internal clock generating mode MGIC (shown in  FIG. 2 ). The internal clock generating block detects the unit period TCLK (shown in  FIG. 2 ) of the data signal DIN, and generates a period digital data TDIG signal (shown in  FIGS. 8 and 9 ) when operating in the period confirming mode MTDG (shown in  FIG. 2 ). In the period confirming mode MTDG, a mode signal XMOD is in the logic state HIGH or “H”. 
         [0027]    The internal clock generating block BGIC generates an internal clock signal ICLK, which is generated in response to the ‘data transition information’ when operating in the internal clock generating mode MGIC (shown in  FIG. 2 ). The internal clock signal ICLK transitions between LOW and HIGH voltage levels every time a waiting time TW (shown in  FIG. 2 ) has elapsed following a transition of the data signal DIN. Here, the waiting time TW is dependent on the period digital data TDIG. Preferably, the waiting time TW is equal to or approximately equal to half of the unit period TCLK of the data signal DIN. The waiting time may be predetermined, or variable and depending on the period digital data signal TDIG. 
         [0028]      FIG. 3  is a diagram illustrating the transition detecting block  100  of  FIG. 1  in detail. Referring to  FIG. 3 , the transition detecting block  100  includes a rising transition confirmation portion  110  and a falling transition confirmation portion  120 . 
         [0029]    The rising transition confirmation portion  110  generates a rising transition confirmation signal PCTA_R at its output in response to detecting a rising transition in the data signal DIN. That is to say, the rising transition confirmation portion  110  generates a logic LOW pulse or “L” pulse in the PCTA_R signal (i.e., the PCTA_R signal transitions from a HIGH voltage level to a LOW voltage level for a limited period of time equal to the width of the “L” pulse) when the data signal DIN transitions from a logic “L” state to a logic HIGH or “H” state (Refer to t 11  in  FIG. 10A ). The rising transition confirmation portion  110  receives at its input the data signal DIN, the DIN signal being provided at a first input of a NAND gate and at an input to an inverting delay. The output of the inverting delay is provided to the second input node of the NAND gate, and the PCTA_R signal is generated at the output of the NAND gate. 
         [0030]    The falling transition confirmation portion  120  generates a falling transition confirmation signal PCTA_F in response to detecting a falling transition in the data signal DIN. That is to say, the falling transition confirmation portion  120  generates a “L” pulse in the PCTA_F signal when the data signal DIN transitions from a logic “H” state to a logic “L” state. (Refer to t 12  in  FIG. 10A ). The falling transition confirmation portion  120  receives at its input the data signal DIN, inverts the DIN signal, and provides the inverted DIN signal to a first input of a NAND gate and to an input of an inverting delay. The output of the inverting delay is provided to the second input node of the NAND gate, and the PCTA_F signal is generated at the output of the NAND gate. 
         [0031]    Referring again to  FIG. 1 , the internal clock generating block BGIC includes an internal clock pulse generating part  200  and an internal clock transition part  300 . The internal clock pulse generating part  200  generates the period digital data TDIG signal when operating in the period confirming mode MTDG. The internal clock pulse generating part  200  generates a clock transition signal XCKT according to the ‘data transition information’ received from the transition detecting block  100  when the BGIC operates in the internal clock generating mode MGIC. The clock transition signal XCKT undergoes a “L” pulse every time the waiting time TW has elapsed following a transition of the data signal DIN. 
         [0032]      FIG. 4  is a diagram illustrating the internal clock pulse generating part  200  of  FIG. 1  in detail. Referring to  FIG. 4 , the internal clock pulse generating part  200  includes a rising transition responding portion  210 , a falling transition responding portion  220 , a combining transition responding portion  230  and an internal clock transition portion PICT. 
         [0033]    The rising transition responding portion  210  generates a rising transition responding signal PCTB_R in response to the rising transition confirmation signal PCTA_R. The rising transition responding portion  210  generates a “L” pulse in the PCTB_R signal in response to each rising-edge transition in the PCTA_R signal, the rising-edge transitions in the PCTA_R signal corresponding to the lagging edges of the “L” pulses in the rising transition confirmation signal PCTA_R generated by the rising transition confirmation portion  110  (Refer to t 21  in  FIG. 10A ). 
         [0034]    The falling transition responding portion  220  generates a falling transition responding signal PCTB_F in response to the falling transition confirmation signal PCTA_F. The falling transition responding portion  220  generates a “L” pulse in the PCTB_F signal in response to each rising-edge transition in the PCTA_F signal, the rising-edge transitions in the PCTA_F signal corresponding to the lagging edges of the “L” pulses in the falling transition confirmation signal PCTA_F generated by the falling transition confirmation portion  120  (Refer to t 22  in  FIG. 10A ). 
         [0035]    The rising and falling transition responding portions  210  and  220  are each formed of an inverting delay and a NAND gate. The input of each of the portions is provided to a first input of the NAND gate and to the input of the inverting delay, the output of the inverting delay being provided to the second input of the NAND gate. The circuits respectively receive at their inputs the PCTA_R and PCTA_F signals, and produce the PCTB_R and PCTB_F output signals at the output of their respective NAND gates. 
         [0036]    The combining transition responding portion  230  generates a reset signal RST responding to the rising transition responding signal PCTA_R and the falling transition responding signal PCTA_F. The combining transition responding portion  230  is formed of an 
         [0037]    AND gate receiving at its inputs the PCTA_R and PCTA_F signals, and generates at its output the reset signal RST. The reset signal RST undergoes a “L” pulse in response to each leading edge of the pulses in the rising transition responding signal PCTA_R and the falling transition responding signal PCTA_F (Refer to t 23  and t 24  in  FIG. 10A ). 
         [0038]    The internal clock transition portion PICT generates the period digital data TDIG signal when operating in the period confirming mode MTDG. The internal clock transition portion PICT generates the clock transition signal XCKT in response to the rising transition responding signal PCTB_R and the falling transition responding signal PCTB_F when operating in the internal clock generating mode MGIC. The clock transition signal XCKT undergoes a “L” pulse in response to the rising transition responding signal PCTB_R and the falling transition responding signal PCTB_F. Here, the clock transition signal XCKT undergoes a “L” pulse every time the waiting time TW has elapsed following a transition of the data signal DIN. The generation of the pulse in the clock transition signal XCKT is stopped in response to the reset signal RST (i.e., the XCKT is held HIGH when the RST signal is LOW). 
         [0039]    The internal clock transition portion PICT includes a half period transition unit  240  and a clock transition generating unit  250 . 
         [0040]    The half period transition unit  240  generates the period digital data TDIG signal when operating in the period confirming mode MTDG. And, the half period transition unit  240  generates a rising half period signal XHT_R and a falling half period signal XHT_F when operating in the internal clock generating mode MGIC. The rising half period signal XHT_R undergoes a “L” pulse delayed by the waiting time TW following rising transitions in the responding signal PCTB_R (Refer to t 31  in  FIG. 10A ). The rising half period signal XHT_R further undergoes a “L” pulse delayed by the waiting time TW following the generation of a “L” pulse in the falling half period signal XHT_F. However, the generation of the “L” pulse in the rising half period signal XHT_R is stopped when a pulse in the reset signal RST occurs during the waiting time TW (Refer to t 32  in  FIG. 10A ). 
         [0041]    The falling half period signal XHT_F undergoes a “L” pulse delayed by the waiting time TW following falling transitions in the responding signal PCTB_F (Refer to t 33  in  FIG. 10A ). The falling half period signal XHT_F further undergoes a “L” pulse delayed by the waiting time TW following the generation of a “L” pulse in the rising half period signal XHT_R. However, the generation of the “L” pulse in the falling half period signal XHT_F is stopped when a pulse in the reset signal RST occurs during the waiting time TW (Refer to t 32  in  FIG. 10A ). 
         [0042]      FIG. 5  is a diagram illustrating the half period transition unit  240  of  FIG. 4  in detail. Referring to  FIG. 5 , the half period transition unit  240  includes a rising detection group  241 , a rising-driving group  243 , a falling detection group  245 , and a falling-driving group  247 . 
         [0043]    The rising detection group  241  receives the rising transition responding signal PCTB_R, the rising half period signal XHT_R, the reset signal RST, and a falling transition driving signal EN_F, and generates a rising transition driving signal EN_R. The falling transition driving signal EN_F is generated at an output of the falling detection group  245 . The rising transition driving signal EN_R is activated to “H” when a pulse occurs in the rising transition responding signal PCTB_R or the deactivation of a pulse occurs in the falling transition driving signal EN_F during activation (i.e., a HIGH or “H” voltage level) of the reset signal RST (Refer to t 41  and t 42  in  FIG. 10A ). Also, the rising transition driving signal EN_R is deactivated to “L” when a “L” pulse in the reset signal RST or in the rising half period signal XHT_R is generated. (Refer to t 43  and t 44  in  FIG. 10A ) 
         [0044]    The rising-driving group  243  receives the rising transition driving signal EN_R, and generates the rising half period signal XHT_R. The rising half period signal XHT_R undergoes a “L” pulse delayed by the waiting time TW when the rising transition driving signal EN_R is deactivated to “L” (Refer to t 45  in  FIG. 10A ). However, when the rising transition driving signal EN_R is deactivated to “L” during the waiting time TW following the activation of the rising transition driving signal EN_R, the generation of the pulse in the falling half period signal XHT_F is interrupted (Refer to t 46  in  FIG. 10A ). 
         [0045]    The falling detection group  245  receives the falling transition responding signal PCTB_F, the falling half period signal XHT_F, the reset signal RST, and the rising transition driving signal EN_R, and generates the falling transition driving signal EN_R. The falling transition driving signal EN_F is activated to “H” when a pulse occurs in the falling transition responding signal PCTB_F or the deactivation of a pulse occurs in the rising transition driving signal EN_R during activation of the reset signal RST (Refer to t 51  and t 52  in  FIG. 10A ). Also, the falling transition driving signal EN_F is deactivated to “L” when a “L” pulse in the reset signal RST or in the falling half period signal XHT_F is generated. (Refer to t 53  and t 54  in  FIG. 10A ) 
         [0046]    The falling-driving group  247  receives the falling transition driving signal EN_F, and generates the falling half period signal XHT_F. The falling half period signal XHT_F undergoes a “L” pulse delayed by the waiting time TW when the falling transition driving signal EN_F is activated to “H” (Refer to t 55  in  FIG. 10A ). However, when the falling transition driving signal EN_F is deactivated to “L” during the waiting time TW following the activation of the falling transition driving signal EN_F, the generation of the pulse in the falling half period signal XHT_F is interrupted (Refer to t 56  in  FIG. 10A ). 
         [0047]      FIG. 6  is a diagram illustrating the rising detection group  241  of  FIG. 5  in detail. Referring to  FIG. 6 , the rising detection group  241  includes a first rising logic NAND gate  241   a  and a second rising logic NAND gate  241   b.    
         [0048]    The first rising logic NAND gate  241   a  receives the rising transition responding signal PCTB_R, the falling transition driving signal EN_F and a rising out signal n 241 , and generates the rising transition driving signal EN_R at its output. The rising out signal n 241  is generated from the second rising logic NAND gate  241   b . The rising transition driving signal EN_R is activated to “H” when a “L” pulse occurs in the rising transition responding signal PCTB_R or in the falling transition driving signal EN_F. The rising transition driving signal EN_R is deactivated to “L” in response to the activation to “H” of the rising out signal n 241 . 
         [0049]    The second rising logic NAND gate  241   b  receives the reset signal RST, the rising half period signal XHT_R and the rising transition driving signal EN_R at its inputs, and generates the rising out signal n 241  at its output. The rising out signal n 241  is activated to “H” when a “L” pulse occurs in the reset signal RST or in the rising half period signal XHT_R. The rising out signal n 241  is deactivated to “L” in response to the activation to “H” of the rising transition driving signal EN_R. 
         [0050]      FIG. 7  is a diagram illustrating the falling detection group  245  of  FIG. 5  in detail. Referring to  FIG. 7 , the falling detection group  245  includes a first falling logic NAND gate  245   a  and a second falling logic NAND gate  245   b.    
         [0051]    The first falling logic NAND gate  245   a  receives the falling transition responding signal PCTB_F, the rising transition driving signal EN_R and a falling out signal n 245  at its inputs, and generates the falling transition driving signal EN_F at its output. The falling out signal n 245  is generated from the second falling logic NAND gate  245   b.  The falling transition driving signal EN_F is activated to “H” when a “L” pulse occurs in the falling transition responding signal PCTB_F or in the rising transition driving signal EN_R. The falling transition driving signal EN_F is deactivated to “L” in response to the activation to “H” of the falling out signal n 245 . 
         [0052]    The second falling logic NAND gate  245   b  receives the reset signal RST, the falling half period signal XHT_F and the falling transition driving signal EN_F at its inputs, and generates the falling out signal n 245  at its output. The falling out signal n 245  is activated to “H” when a “L” pulse occurs in the reset signal RST or in the falling half period signal XHT_F. The falling out signal n 245  is deactivated to “L” in response to the activation to “H” of the falling transition driving signal EN_F. 
         [0053]      FIG. 8  is a diagram illustrating the rising-driving group  243  of  FIG. 5  in detail. Referring to  FIG. 8 , the rising-driving group  243  includes a frequency divider  243   a,  a multiplexer  243   b,  an oscillator  243   c,  a counter  243   d,  a half period latch  243   e,  and a comparator  243   f.    
         [0054]    The frequency divider  243   a  divides the frequency of the data signal DIN to generate a period extension signal EDN 1 . In this embodiment, the frequency of the period extension signal EDN 1  is half that of the data signal DIN. That is to say, the unit period of the period extension signal EDN 1  is twice as that of the data signal DIN. 
         [0055]    The multiplexer  243   b  selects one of the period extension signal EDN 1  and the rising transition driving signal EN_R according to the mode signal XMOD. The selected one of the period extension signal EDN 1  and the rising transition driving signal EN_R is output from the multiplexer as an enable signal XEN 1 . In this embodiment, the period extension signal EDN 1  is selected when operating in the period confirming mode MTDG. The rising transition driving signal EN_R is selected when operating in the internal clock generating mode MGIC. 
         [0056]    The oscillator  243   c  is enabled in response to the enable signal XEN 1 . In this embodiment, the oscillator  243   c  is enabled when the enable signal XEN 1  is in a logic “H” or HIGH state. The oscillator  243   c  generates an oscillation signal OSC 1  when it is enabled. 
         [0057]    The counter  243   d  is reset in response to the transition to “H” (i.e., a rising transition) in the enable signal XEN 1 . The counter  243   d  counts the number of rising transitions to “H” in the oscillation signal OSC 1  to generate a counting data signal CNT 1 . 
         [0058]    The half period latch  243   e  is reset in response to the rising transition to “H” in the mode signal XMOD. The half period latch  243   e  divides the counting data CNT 1  into halves to generate the period digital data TDIG. For example, if the counting data CNT 1  is equal to 8, then the half period digital latch outputs a data signal TDIG signal equal to 4. Here, the remaining data can be ignored. 
         [0059]    Accordingly, the period digital data TDIG has the same period as the data signal DIN. In particular, in one embodiment, the period digital data TDIG has digital data corresponding to a period of the data signal DIN, such that TDIG is determined as the digital data having the information of the period of the data signal DIN. In another embodiment, the delays in oscillator  243   c  may be selected so as to ensure that TDIG has the same period as the data signal DIN. In the internal clock generating mode MGIC, the comparator  243   f  compares the counting data CNT 1  with the period digital data TDIG to generate a rising half period signal XHT_R. The rising half period signal XHT_R undergoes a “L” pulse when the counting data CNT 1  is equal to the period digital data TDIG. 
         [0060]    As a result, the rising half period signal XHT_R undergoes a “L” pulse when the half period of the data signal DIN is passed following a lagging edge of the rising transition driving signal EN_R. 
         [0061]      FIG. 9  is a diagram illustrating the falling-driving group  247  of  FIG. 5  in detail. Referring to  FIG. 9 , the falling-driving group  247  includes a frequency divider  247   a,  a multiplexer  247   b,  an oscillator  247   c,  a counter  247   d,  a half period latch  247   e,  and a comparator  247   f.    
         [0062]    The frequency divider  247   a  divides the frequency of the data signal DIN to generate a period extension signal EDN 2 . In this embodiment, the frequency of the period extension signal EDN 2  is half that of the data signal DIN. That is to say, the unit period of the period extension signal EDN 2  is twice as that of the data signal DIN. 
         [0063]    The multiplexer  247   b  selects one of the period extension signal EDN 2  and the falling transition driving signal EN_F according to the mode signal XMOD. The selected one of the period extension signal EDN 2  and the falling transition driving signal EN_R is output from the multiplexer as an enable signal XEN 2 . In this embodiment, the period extension signal EDN 2  is selected when operating in the period confirming mode MTDG. The falling transition driving signal EN_F is selected when operating in the internal clock generating mode MGIC. 
         [0064]    The oscillator  247   c  is enabled in response to the enable signal XEN 2 . In this embodiment, the oscillator  247   c  is enabled when the enable signal XEN 2  is in a logic “H” state. The oscillator  247   c  generates an oscillation signal OSC 2  when it is enabled. 
         [0065]    The counter  247   d  is reset in response to the transition to “H in the enable signal XEN 2 . The counter  247   d  counts the number of rising transitions to “H” in the oscillation signal OSC 2  to generate a counting data signal CNT 2 . 
         [0066]    The half period latch  247   e  is reset in response to the rising transition to “H” in the mode signal XMOD. The half period latch  247   e  divides the counting data CNT 2  into halves to generate the period digital data TDIG. Here, the remaining data can be ignored. 
         [0067]    Accordingly, the period digital data TDIG has the same period as the data signal DIN. 
         [0068]    In the internal clock generating mode MGIC, the comparator  247   f  compares the counting data CNT 2  with the period digital data TDIG to generate a falling half period signal 
         [0069]    XHT_F. The falling half period signal XHT_F undergoes a “L” pulse when the counting data CNT 2  is equal to the period digital data TDIG. 
         [0070]    As a result, the falling half period signal XHT_F undergoes a “L” pulse when the half period of the data signal DIN is passed following a lagging edge of the falling transition driving signal EN_F. 
         [0071]    In this embodiment, the constitution of the falling-driving group  247  is the same as that of the rising-driving group  243 . The period digital data in falling-driving group  247  is the same as that in the rising-driving group  243 . Therefore, the period digital data in rising-driving group  243  and the period digital data in falling-driving group  247  are marked with the same reference mark TDIG, for the convenience of explanation, in this specification. 
         [0072]    Referring again to  FIG. 4 , the clock transition generating unit  250  generates the clock transition signal XCKT in response to the rising transition responding signal PCTB_R, the rising half period signal XHT_R, the falling transition responding signal PCTB_F, and the falling half period signal XHT_F. In the embodiment shown in  FIG. 4 , the clock transition generating unit  250  is formed of three logic AND gates, the first AND gate receiving at its inputs the PCTB_R and XHT_R signals, the second AND gate receiving at its inputs the PCTB_F and XHT_F signals, and the third AND gate receiving at its inputs the outputs of the first and second AND gates and producing at its output the XCKT signal. 
         [0073]    Here, the clock transition signal XCKT undergoes a “L” pulse when at least one of the rising transition responding signal PCTB_R, the rising half period signal XHT_R, the falling transition responding signal PCTB_F and the falling half period signal XHT_F undergo a “L” pulse (Refer to  FIG. 10A ). 
         [0074]    Referring again to  FIG. 1 , the internal clock transition part  300  generates the internal clock signal ICLK in response to the clock transition signal XCKT. The logic state of the internal clock signal ICLK is alternatively transited between “H” and “L” at each falling transition (marking the beginning of a “L” pulse) in the clock transition signal XCKT. 
         [0075]    Accordingly, the internal clock signal ICLK transitions between logic states in response to transitions in the data signal. Also, even if transitions in the data signal are not generated for long time, the logic state of the internal clock signal ICLK alternates between “H” and “L” states every time the waiting time TW is elapsed following a transition in the data signal DIN (Refer to  FIG. 10B ). 
         [0076]    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.