Abstract:
In general, in one aspect, the disclosure describes a digital signal equalizer that includes a plurality of multiplexers. The number of multiplexers defines resolution of equalization. The plurality of multiplexers are configured in groups. The number of groups is based on number of taps, and the number of multiplexers associated with a particular group is based on equalization range for the group. The multiplexers in each group select a digital value associated with the cursor or a non-cursor tap associated with the group.

Description:
BACKGROUND 
     Lossy interconnect channels used in wireline communications, such as that between processor and chipsets on a computing platform, attenuate higher frequency components of the data signal and result in degraded link performance. Transmitter equalization improves the worst case receiver eye height by monitoring the data transmitted and to be transmitted and modifying the present data eye height at the transmitter. Typically, an equalizer is used to either boost high frequency gain or reduce low frequency gain in the signal waveform to compensate for the channel response. Transmitter side digital linear equalization may use Multiply-Add-Accumulate (MAC)/Arithmetic Logic Units (ALU) to perform computations used to provide the equalization. Some of the computations performed may be redundant so the equalizers may be power inefficient as a result. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the various embodiments will become apparent from the following detailed description in which: 
         FIG. 1  illustrates a sequence of outputs from a serial link, according to one embodiment; 
         FIG. 2A  illustrates an example functional diagram of a multiplexer based transmitter equalizer, according to one embodiment; 
         FIG. 2B  illustrates example results for various data patterns for an implementation of the equalizer of  FIG. 2A , according to one embodiment; 
         FIG. 3  illustrates an example functional diagram of a multiplexer based transmitter equalizer adapted to a two-way interleaved data stream, according to one embodiment; and 
         FIG. 4  illustrates an example computer system utilizing multiplexer based transmitter equalization, according to one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a sequence of outputs (data stream) from a serial link. The current bit (D 0 ) being transmitted over the serial link is commonly referred to as the “cursor”. Bits previously transmitted (D 1 , D 2 ) are referred to as “post-cursors” and bits to be transmitted (D −1 ) are referred to as “pre-cursors”. In order to provide digital linear equalization of the data being transmitted an equalizer may look at some combination of post-cursor(s) and pre-cursor(s) in addition to the cursor. The number of data bits used as part of the digital linear equalization is known as taps (four taps are illustrated). Each tap may contribute to the digital linear equalization of a data stream. The post cursors may contribute more to the equalization then pre-cursors and the distance away from the cursor may impact the contribution to equalization (e.g., further the tap is away from the cursor the less the contribution). For example, the digital linear equalized signal may be based up to 100% on the cursor D 0  (if 100% equalization is off), up to 50% on the first post-cursor D 1 , and up to 25% on the second post-cursor D 2  and first pre-cursor D -1 . The sum of all the taps should be 100%. 
     If consecutive digital signals being transmitted in the serial link are the same, the analog output signal (current bit amplitude) need not provide an absolute value representative of the digital signal. Rather, the analog output signal can begin to creep toward the value representative of the other digital signal to help the receiver on the other end of the link detect a transition in the data stream. That is, if a digital  0  was transmitted (D 1 ) and is to be transmitted again (D 0 ) the analog output signal need not have an absolute 0 value but can begin to creep toward a 1 value. Likewise, if a digital  1  was transmitted and is to be transmitted again the analog output signal need not have an absolute  1  value but can begin to creep toward a 0 value. Accordingly, in equalization the compliment of the pre and post cursor taps may be utilized to strengthen or weaken the analog output signal transmitted over the serial link. Depending on the platform utilized, the compliments may be utilized for only the first pre and post taps or may be utilized for additional taps. 
       FIG. 2A  illustrates an example functional diagram of a multiplexer based transmitter equalizer  200 . The equalizer  200  may utilize four taps (D 0 , D 1 , D 2 , D −1 ). The equalizer  200  may include multiplexer based equalization  210  and analog current summation digital to analog converter (DAC)  220 . The multiplexer based equalization  210  may include a plurality of multiplexers  230  and a plurality of flip-flops  240 . The number of multiplexers  230  and flip-flops  240  may be based on the resolution of the equalization desired (e.g.,  61  multiplexers  230  and flip-flops  240  may be utilized in one embodiment to provide a 1/61 (0.016) resolution). 
     Each multiplexer  230  may be provided with the cursor tap D 0  as one input and a complement of one of the other taps (1—tap or tapbar) as the second input (1-D −1  or D- −1 bar, 1-D 2  or D 2 bar, 1-D 1  or D 1  bar). According to one embodiment (as illustrated), each multiplexer  230  may receive the cursor tap D 0  as the 0 select. The number of multiplexers  230  associated with each tap may be based on the equalization resolution (total number of multiplexers  230 ) and the possible equalization contribution (range) of each tap. The range for each tap may be based on the location of the tap with respect to the cursor. For example, according to one embodiment thirty-one multiplexers  230  ( 0 - 30 ) may be associated with the first post-cursor tap D 1  and have D 1 bar as the second input, fifteen (or  30 ) multiplexers  230  ( 31 - 45 ) may be associated with the second post-cursor tap D 2  and fifteen ( 46 - 60 ) may be associated with the first pre-cursor tap D −1  (only one of each illustrated). 
     Each of the multiplexers  230  may receive a coefficient to control which input (tap) is selected. For example, if the coefficient for a multiplexer  230  is 0 the multiplexer  230  may select D 0  and if the coefficient is 1 the multiplexer  230  may select the tapbar. According to one embodiment, coefficients C 0  through C 30  may control a respective one of the multiplexers  0 - 30  that propagate either D 0  or D 1 bar to the output, coefficients C 31  through C 45  may control the multiplexers  31 - 45  that select either D 0  or D 2 bar to the output, and coefficients C 46  through C 60  may select either D 0  or D −1 bar to propagate as the output for multiplexers  46 - 60 . 
     According to one embodiment, by setting all coefficients to 0, the cursor tap D 0  may be propagated to the output of all the multiplexers  230  (equalization is turned off). By setting all coefficients to 1, the cursor tap D 0  may not be propagated to any of the outputs of the multiplexers  230 . Accordingly, the cursor tap D 0  may have a range from 0 to 1 at increments according to one embodiment of 1/61 (0.016). The tap D 1 bar may have a range from 0 if all the coefficients C 0 C 30  are 0 to 31/61 (0.508) if all the coefficients C 0 -C 30  are 1. The taps D 2 bar and D −1 bar may have a range from 0 if all the coefficients C 31 -C 45  and C 46 -C 60  respectively are 0 to 15/61 (0.246) if all the coefficients C 31 -C 45  and C 46 -C 60  respectively are 1. 
     The equalization parameters may be set with control bits. For example, 13 control bits may be used, 5 control bits to select the value for tap D 1 bar (how many of the multiplexers  0 - 30  should select tap D bar) and 4 control bits to select the value for taps D 2 bar and D −1 bar respectively. Decoders (not illustrated) may be used to generate the  61  (C 0  through C 60 ) coefficients. A  5 -to- 31  decoder may be used to convert the 5 D 1 bar control bits into the C 0 -C 30  coefficients and the two  4 -to- 15  decoders may be used to convert the 4 D 2 bar and the 4 D −1 bar control bits into the C 31 -C 45  and C 46 -C 60  coefficients respectively. 
     The output of each of the multiplexers  230  may be provided to corresponding flip-flops  240 . The flip flops  240  may utilize the clock to read the data in and out so that all of the data (tap values) output from the multiplexers  230  are aligned. The outputs of the flip flops  240  may be provided to the analog current summation DAC  220 . 
     The analog current summation DAC  220  includes a plurality of DACs  250  aligned with corresponding flip flops  240 . The DACs  250  convert the digital signal received into an analog signal. All the DACs  250  are tied together and to ground through a load resister  260  to sum all the individual analog signals and generate the overall analog signal. 
     The equalization may be defined as ((D 0 coeff*D 0 )+(D 1 coeff*D 1 bar)+(D 2 coeff*D 2 bar)+(D −1 coeff*D −1 bar))/TOTcoeff, where D x coeff is the number of coefficients selected for the X tap, D 0  is the value of the cursor D 0 , D x bar is the inverted value of D x  (1−D x ) for the X tap, and TOTcoef is the total number of coefficients. The equation shows that if the value of the post and pre cursors are the same as the cursor that they will actually shift the result away from the cursor value. 
       FIG. 2B  illustrates example results for various data patterns for an implementation of the equalizer  200  where D 1 coeff=16, D 2 coeff=4, D −1 coeff=4 and D 0 coeff=37(TOTcoeff−D 1 coeff−D 2 coeff−D −1 coeff). As can be seen when the pre or post cursors are the same as the cursor the resulting DAC value shifts away from the cursor value. For example, when the data pattern is 0000 the resulting DAC value is 0.393. The DAC value is the full cursor value when the cursor value is different than all the pre and post cursor values. For example, when the data pattern is 0100 the resulting DAC value is 1. 
     According to one embodiment, the example four tap equalizer  200  may also function as a 2 or 3-tap equalizer by selecting D 0  on all the multiplexers associated with the specific tap or taps. For example, to operate the four tap equalizer  200  as a three tap equalizer (D 0 , D 1 , D 2 ) all the multiplexers  46 - 60  may select tap D 0  as the output (no D −1  selected) by setting all the C 46 -C 60  coefficients as zeros. To operate as a three tap equalizer (D 0 , D 1 , D −1 ) all the multiplexers  31 - 45  may select tap D 0  as the output (no D 2  selected) by having the C 31 -C 45  coefficients all zeros. To operate the four tap equalizer  200  as a two tap equalizer (D 0 , D 1 ) all the multiplexers  31 - 60  may select tap D 0  as the output (no D 2  or D −1  selected) by setting all the C 31 -C 60  coefficients as zeros. As previously noted equalization may be turned off by setting all the C 0 -C 60  coefficients to zeros and therefore selecting tap D 0  (the cursor) as the output of all the multiplexers  230 . 
     The example equalizer  200  illustrated four taps, 1/61 resolution, a range of 0 to 31/61 for first post-cursor tap, and a range of 0 to 15/31 for the second post-cursor tap D 2  and the first pre-cursor tap D −1 . The multiplexer based transmitter equalizer is not intended to be limited by these illustrated examples. Rather, a multiplexer based transmitter equalizer can easily be adapted to different number of taps, tap resolutions and tap ranges without departing from the scope. 
     The example equalizer  200  is illustrated as using differential multiplexers  230  (receiving differential signals and outputting differential signals) but is not limited thereto. Rather, the equalizer  200  may include a separate multiplexer  230  for each end of the differential signal. The output of the multiplexers  230  for each end of the differential signal may be provided to an appropriate flip flop  240 . 
     The example equalizer  200  is illustrated as receiving differential signals but is not limited thereto. Rather, the equalizer  200  could receive a single ended signal for each tap without departing from the scope. The multiplexers  230  could receive a single ended signal for each tap and output the single ended signal selected (or have only a single multiplexer rather that one for each leg of the differential signal). The output could then be split and one of the signals could be inverted in order to provide the flip flops  240  with a differential signal. Providing the flip flops with a differential signal enables the flip flop to control the timing of the equalization. 
     The example equalizer  200  is illustrated as having the multiplexers  230  receive tapbar signals for the first and second post cursors and the pre cursor but is not limited thereto. For example, depending on the platform that equalization is being performed on the 2 nd  post cursor tap may want to push the DAC value closer to the cursor value if the values are the same and away from the cursor if the values are different (opposite of that described above). Accordingly, the second post cursor value provided to the multiplexers  230  associated therewith ( 31 - 45 ) may vary depending on the platform (is platform dependent). According to one embodiment, D 2 bar may be calculated and D 2  and D 2 bar may be provided to a pre-equalization multiplexer (not illustrated) and the output of the pre-equalization multiplexer may be provided to the appropriate equalization multiplexers  230 . The selection of D 2  or D 2 bar may be made with a control bit that is set depending on platform. 
       FIG. 3  illustrates an example functional diagram of a multiplexer based transmitter equalizer  300  adapted to a two-way interleaved data stream. A two-way interleaved data stream is sometimes preferred in order to reduce the speed requirements of digital circuits. The cursor position for odd bits may be considered as D 1  while the cursor position for the even bits may be considered D 0 . The equalizer  300  may include a multiplexer based equalization  310  for the odd bits and a multiplexer based equalization  320  for the even bits. The equalizer  300  may be a four tap implementation. The taps for the multiplexer based equalization  310  may be D 0 , D 1 , D 2 , D 3  while the taps for the multiplexer based equalization  320  may be D −1 , D 0 , D 1 , D 2 . 
     Each multiplexer based equalization  310 ,  320  may include a plurality of multiplexers  330  and a plurality of flip flops  340 . The number of multiplexers  330  and flip-flops  340  may be based on the resolution of the equalization desired (e.g.,  61  multiplexers  330  and flip-flops  340  may be utilized for each equalization  310 ,  320  in one embodiment to provide a 1/61 (0.016) resolution). The number of multiplexers  330  associated with each tap may be based on the equalization resolution (total number of multiplexers  330 ) and the possible equalization contribution (range) of each tap. The range for each tap may be based on the location of the tap with respect to the cursor. 
     For example, according to one embodiment the multiplexer based equalization  310  may include  31  multiplexers  330  ( 0 - 30 ) associated with D 2  and receiving taps D 1  and D 2 bar, 15 multiplexers  330  ( 31 - 45 ) associated with D 3  and receiving taps D 1  and D 3 bar, and 15 multiplexers  330  ( 46 - 60 ) associated with D 0  and receiving taps D 1  and D 0 bar. The multiplexer based equalization  320  may include  31  multiplexers  330  ( 0 - 30 ) associated with D 1  and receiving taps D 0  and D 1 bar, 15 multiplexers  330  ( 31 - 45 ) associated with D 2  and receiving taps D 0  and D 2 bar, and 15 multiplexers  330  ( 46 - 60 ) associated with D −1  and receiving taps D 0  and D −1 bar. The taps provided to the equalizer  300  may be generated from a 1 bit wide even and odd data streams by a preceding block (not illustrated) that delays data so that the four data taps for the even bit are available synchronously with an even phase clock and the four data taps for the odd bit are available synchronously with an odd phase clock. 
     Each of the multiplexers  330  may receive a coefficient to control which input (tap) is selected. For example, coefficients C 0 -C 30 , C 31 -C 45  and C 46 -C 60  may control the output of the multiplexers  0 - 30 ,  31 - 45  and  46 - 60  respectively for both multiplexer based equalizations  310 ,  320 . A coefficient of 0 may select the cursor tap for the respective multiplexer  330  while a coefficient of 1 may select the other input of the multiplexer  330 . For example, for multiplexers  0 - 30  a coefficient of 0 may select D 1  as the output of the multiplexers  330  in multiplexer based equalizations  310  and D 0  as the output of the multiplexer  330  in the multiplexer based equalizations  320  while a coefficient of 1 may select D 2 bar as the output of the multiplexers  330  in multiplexer based equalizations  310  and D 1 bar as the output of the multiplexer  330  in the multiplexer based equalizations  320 . 
     The output of the multiplexers  330  may be provided to the flip flops  340 . The flip flops  340  from the multiplexer based equalizations  310  may operate on a first clock signal (e.g., rising edge of a clock signal) and the flip flops  340  from the multiplexer based equalization  320  may operate on a second clock signal (e.g., falling edge of a clock signal). The output of the flip flops  340  may be split and then one of the signals may be inverted by inverter  350  to provide a differential signal and the differential signal may be provided to a 2 to 1 multiplexer  360  (e.g., a 61 segment 2 to 1 multiplexer according to one embodiment having 61 multiplexers  330  and flip flops  340  for the odd/even equalizations  310 ,  320 ). The multiplexer  360  includes a plurality of multiplexers  370  (only 3 are illustrated) that may receive the output of the corresponding flip flops  340  from the multiplexer based equalizations  310 ,  320 . For example, multiplexer  0   370  may receive the differential signal from flip flop  0   340  for both the odd and even multiplexer based equalizations  310 ,  320 . 
     The multiplexers  370  may multiplex the odd and even differential data streams into a final differential data output stream that flows at twice the speed of the odd and even data streams (e.g., 61 bit wide stream according to one embodiment). The select signal for the multiplexers  370  may basically be a half rate clock. The output of the multiplexer  360  may be a full-rate differential data stream (e.g., 61 bit differential data stream). The full-rate differential data stream may be provided to a pre-driver/driver  380  that converts the full-rate differential data stream into a single analog differential signal. The pre-driver/driver  380  may provide final analog current summation as the current driven into the load resistor (not illustrated) is the summing of the currents from the plurality of segments (e.g., 61). 
     The example equalizer  300  utilized four taps, 1/61 resolution, a range of 0 to 31/61 for first post-cursor tap, and a range of 0 to 15/31 for the second post-cursor tap and the first pre-cursor tap. The multiplexer based transmitter equalizer is not intended to be limited by these illustrated examples. Rather, this multiplexer based transmitter equalizer can easily be adapted to different number of taps, tap resolutions and tap ranges. 
     The example equalizer  300  is illustrated as receiving single ended signals and converting the signals to differential signals after the flip-flops  340  (since the multiplexer  360  controls the timing) but is not limited thereto. Rather, the single ended signals could be converted to differential signals at other locations without departing from the scope. Furthermore, the equalizer  300  is not limited to providing equalization for single ended signals. Rather, the equalizer  300  could receive differential signals for each tap without departing from the scope. 
     The multiplexer based transmitter equalizers  200 ,  300  may take advantage of realistic tap coefficient ranges to reduce the implementation complexity for digital equalization. The multiplexer based transmitter equalizers  200 ,  300  may retain the ability to be configured from 0 to the maximum number of taps for a given implementation. The multiplexer based transmitter equalizers  200 ,  300  may be implemented into a transmitter simply as implementation may only requires the addition of multiplexer elements to the transmitter. In addition, the entire equalization may be done in one stage so that the latency added by the equalizers is minimal. The simple implementation may enable equalization to be performed with low power requirements. The equalizers  200 ,  300  may be utilized in high speed serial input/output (I/O) application to optimize performance without heavy power consumption. 
       FIG. 4  illustrates an example computer system  400  utilizing multiplexer based transmitter equalization. The system includes a processor circuit  410  and a chipset circuit  420  connected with a serial I/O link  430 . The processor circuit  410  includes a transmitter  440  and the chipset circuit includes a receiver  450 . The transmitter  440  includes a multiplexer based equalizer  460  therewithin. 
     Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
     The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.