Abstract:
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

Description:
BACKGROUND 
       [0001]    Memory devices are typically provided as internal, semiconductor, integrated circuits in apparatuses such as computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile (e.g., phase change memory, flash) memory. 
         [0002]    Non-volatile memories are important elements of integrated circuits due to their ability to maintain data absent a power supply. Phase change materials have been investigated for use in non-volatile memory cells. Phase change memory (PCM) elements include phase change materials, such as chalcogenide alloys, that are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state and the resistance states distinguish the logic values of the memory element. Specifically, an amorphous state exhibits a relatively high resistance and a crystalline state exhibits a relatively low resistance. One of different logic levels (e.g., logic 1 or logic 0) can be assigned to each of these states. 
         [0003]    There are general needs to improve PCM devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  illustrates a cross-sectional view of a typical phase change memory stack. 
           [0005]      FIGS. 2-7  illustrate an embodiment of a process flow to fabricate a phase change memory stack having treated sidewalls. 
           [0006]      FIG. 8  illustrates a block diagram of a memory system in accordance with the embodiments of  FIGS. 2-7 . 
           [0007]      FIG. 9  illustrates a plot of adhesion species deposition depth versus pulse voltage. 
           [0008]      FIG. 10  illustrates a plot of adhesion species deposition depth versus implant nominal dose. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    As described subsequently, a method for fabricating a memory stack (e.g., memory device) with treated sidewalls can increase the adhesion of dielectric passivation material to the electrodes. This can reduce inter-diffusion between the electrodes and adjacent materials in the memory stack. 
         [0010]      FIG. 1  illustrates a typical memory cell stack for a PCM. Carbon can be used as top  101 , middle  102 , and bottom  103  electrodes for the memory cell stack. Carbon is chemically inert and does not react easily with the phase change material  110  or the selector device material  111 . This inert chemistry can also lead to poor adhesion of sidewalls to the carbon electrodes. As a result, it can be possible for the sidewall material  120 ,  121  to inter-diffuse  130 ,  131  between the selector device material  111  and the phase change material  110 . This can occur at higher local temperatures during device operation. The inter-diffusion can cause reliability issues, degrade leakage current, and affect threshold voltage stability. 
         [0011]      FIGS. 2-7  illustrate various steps in fabricating a memory stack (e.g., PCM) in addition to treating the sidewalls of the memory stack with an adhesion species. These fabrication steps are for purposes of illustration only as the different elements of the stack can be formed by different processes. 
         [0012]      FIG. 2  illustrates an embodiment of a blanket deposition of the initial memory stack material  200 . The memory stack can include a word line material (e.g., tungsten (W))  201 . A first electrode material  202  (e.g., carbon) can be formed on the word line material  201 . A selector device material  203  may be formed on the first electrode material  202 . 
         [0013]    The selector device material  203  (SD) may include Selenium (Se), Arsenic (As), Germanium (Ge), Tin (Sn), Tellurium (Te), Silicon (Si), Lead (Pb), Carbon (C), or Bismuth (Bi) as well as other materials. Other embodiments can include selector device material  203  comprising one or more of these elements as well as one or more of these elements combined with other elements. 
         [0014]    A second electrode material  204  (e.g., carbon) can be formed on the selector device material  203 . A phase change material  205  can be formed on the second electrode material  204 . 
         [0015]    The phase change material  205  (PM) can include chalcogenide elements such as Germanium (Ge), Antimony (Sb), Tellurium (Te), Indium (In) as well as other chalcogenide elements, combinations of these elements, or combinations of these elements with other elements. The phase change material  205  can additionally include Aluminum (Al), Gallium (Ga), Tin (Sn), Bismuth (Bi), Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd), Copper (Cu), Cobalt (Co), Silver (Ag), or Platinum (Pt) as well as other elements. Additional embodiments can combine these elements with the chalcogenide elements. 
         [0016]    A third electrode material  206  (e.g., carbon) can be formed on the phase change material  205 . Forming the third electrode material  206 , as well as the other materials  201 - 205  of the memory stack, can be done with a blanket deposition method or some other deposition method. 
         [0017]    After the initial memory stack material  200  has been formed, an etch process (e.g., dry etch) can be performed on the stack material  200  to create trenches  301 - 304  as illustrated in  FIG. 3 .  FIG. 3  illustrates that the stack material  200  has been divided by the plurality of trenches  301 - 304  into a plurality of memory stacks  311 - 315 , each stack comprising the architecture illustrated in  FIG. 2 . 
         [0018]    In another embodiment, the stack material  200  can be dry etched patterned in both x and y directions. Thus, subsequent sidewall liners can be added on four sidewalls, as illustrated in  FIG. 7 . 
         [0019]      FIG. 4  illustrates the treatment of the sidewalls of particular ones of the stack  311 - 315  as formed in  FIG. 3 . This treatment enhances the dielectric liner adhesion to the electrode surfaces. In an embodiment, a plasma immersion technique (e.g., plasma doping) can be used to implant an adhesion species in the stack sidewalls and deposit a dielectric liner (e.g., nitride). While  FIG. 4  illustrates the treatment process with regard to only one sidewall of one electrode, the sidewalls of the other electrodes can experience a similar process. 
         [0020]    The sidewall treatment process illustrated in  FIG. 4  includes a step  430  of implanting the sidewall of the carbon electrode(s)  204  with an adhesion species (e.g., boron) using a relatively low energy (e.g., &lt;3 k eV) plasma doping (PLAD) process  400 . This can be accomplished by exposing the sidewall to a diborane gas (B 2 H 6 ) resulting in a B-C layer  410  as a result of the boron terminating unsatisfied atomic bonds of the carbon. 
         [0021]    A subsequent step  431  includes depositing a boron film  411  on the electrode  204 . As a result of the PLAD implant/deposition process  400 , a gradient structure  420  of B-C bonds and the boron film is formed that can be approximately 1-6 nm thick. 
         [0022]    Another step  432  includes implanting a dielectric material (e.g., nitride (N)) into the B-C gradient  420 . For example, a relatively low energy (e.g., 0-2 k eV) NH 3  or N 2 /H 2  PLAD process  401  can implant nitrogen atoms into the boron film  411  to form a BN X  film  412  on the carbon electrode  204  sidewall. The BN X  film  412  can be referred to as the sidewall liners or dielectric liners. 
         [0023]    The process illustrated in  FIG. 4  can result in a dielectric liner  412  that can be a few atomic layers thick. If a thicker BN X  film is desired, the process of  FIG. 4  can be repeated. 
         [0024]    Relatively low energy plasma immersion implant can have advantages if used in this process. For example, conformal doping can be used in the process in order to achieve a tunable implant/deposition operation regime and a shallow profile. The ion bombardment nature of an implant process can enhance an adhesion-friendly species (e.g., boron) by intermixing with the electrode material. For example, the implanted boron can improve adhesion by species intermixing and terminating unsatisfied atomic bonds (e.g., carbon bonds). Other adhesion species besides boron that have similar properties can also be used. This process can be accomplished at approximately room temperature. To form the PCM cells, electrically insulated pillars are formed (e.g., by dry etching) in the bit line direction while the memory stacks are formed in the word line direction. 
         [0025]      FIG. 5  illustrates the stacks  311 - 315  as a result of forming the sidewall liners  500 - 508  on the sidewalls of the stacks  311 - 315  as seen in  FIG. 4 . The process to form the sidewall liners  500 - 508  can use any dielectric material that can be implanted into the adhesive species film  411 . For purposes of illustration, a dielectric material like AlSiO x  can be used. 
         [0026]      FIG. 6  illustrates an embodiment for forming a dielectric fill material  601 - 604  between adjacent memory stacks. The dielectric fill material  601 - 604  can electrically isolate each of the memory stacks. The dielectric fill material  601 - 604  can be the same material as the sidewall liners  500 - 508  or a different dielectric material. 
         [0027]      FIG. 7  illustrates an embodiment for forming additional decks of memory stacks. For example,  FIG. 7  shows two memory stacks  701 ,  702  coupled together at a common bit line  703 . The sidewalls or the sidewall liner treatment described previously with reference to  FIG. 4  and below with reference to  FIG. 8  may be repeated for the memory stacks at each of the decks. Other embodiments can have additional decks of memory stacks  701 ,  702 . This embodiment can be obtained by a patterned dry etch process in both the x-direction and the y-direction and the liner added to the far side sidewall. 
         [0028]    The represented sequence of layers is for purposes of illustration only. Other embodiments can use other sequences. For example, the relative position of the PM and select material (SD) may be exchanged. Also, the relative positions of word line material and bit line material may be changed (e.g., having bit lines at the bottom of the first deck and word lines at the top of the first deck and possibly shared with a second deck stack. 
         [0029]      FIG. 8  illustrates a block diagram of a memory system that include a memory device  801  that can use the memory stacks with treated sidewalls of  FIGS. 2-7 . A controller  800  may be used to control operations of the system. The memory device  801 , coupled to the controller  800 , may include a memory array comprising memory cell stacks as described above with reference to  FIGS. 2-7 . 
         [0030]    The controller  800  may be coupled to the memory device  801  over control, data, and address buses. In another embodiment, the address and data buses may share a common input/output (I/O) bus. The controller  800  can be part of the same integrated circuit as the memory device  801  or as separate integrated circuits. 
         [0031]      FIG. 9  illustrates a plot of adhesion species (e.g., boron) deposition depth (in nanometers) versus pulse voltage. This plot assumes a B 2 H 6 /H 2  PLAD process. The plot shows that the boron deposition layer thickness can be increased at relatively low energy (e.g., &lt;200 eV) and low temperature (e.g., &lt;approximately 390° C.). Implant mode begins to increase at approximately 200V. 
         [0032]      FIG. 10  illustrates a plot of adhesion species (e.g., boron) deposition depth (in nanometers) versus implant nominal dose (in atmospheres/centimeter 2 ). This plot shows that, even for higher energy (e.g., &gt;3 k eV), the implant/deposition intermixing mode can increase the adhesion species deposition thickness with dose. 
         [0033]    As used herein, an apparatus may refer to, for example, circuitry, an integrated circuit die, a memory device, a memory array, or a system including such a circuit, die, device or array. 
       CONCLUSION 
       [0034]    One or more embodiments of the method for memory stack sidewall treatment can result in a memory device with memory stacks having enhanced adhesion to the sidewall liners. For example, an adhesion species (e.g., boron) can intermix with particular materials of the memory stack to create better adhesion and, thus, reduced sidewall material inter-diffusion. The adhesion species can be implanted in the sidewalls using a PLAD implant/deposition process to form a gradient of boron film and an atomic intermixed structure of boron and carbon. A dielectric forming material (e.g., N) can then be implanted into the film to form a BN X  sidewall liner. 
         [0035]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations.