Abstract:
A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a memory circuit which makes up a semiconductor dynamic RAM, more particularly, it relates to a memory circuit which is capable of executing accessing operations at extremely fast speed. 
     2. Description of Related Art 
     FIG. 1 schematically designates the block diagram of a conventional memory array. The reference numeral 1 shown in FIG. 1 designates an N-channel MOS transistor and the reference numeral 3 a sense amplifier. Gate of transistor 1 is connected to a work line WL, whereas source and drain of this transistor 1 are respectively connected to a capacitor 2 and a bit line B. The bit line B, the other bit line B, and a sense amplifier activating signal line SO, are respectively connected to the sense amplifier 3. The reference numerals 4 and 5 respectively designate N-channel MOS transistors each functioning as a transfer gate. Data signal &#34;y&#34; outputted from a conventional column decoder shown in FIG. 2 is inputted to gates of those transistors 4 and 5. The conventional column decoder shown in FIG. 2 incorporates a NAND circuit 23 and a NOT circuit 24 which are connected to each other in series. The NAND circuit 23 receives column address Ai. Source and drain of the N-channel MOS transistor 4 are respectively connected to the bit line B and a write/read signal line I/O. On the other hand, source and drain of the other N-channel MOS transistor 5 are respectively connected to the bit line B and the other write/read signal line I/O. A write buffer 21 and a read pre-amplifier 22 are respectively connected to the write/read signal lines I/O and I/O. 
     Referring now to the waveform chart shown in FIG. 3, functional operation of the conventional memory array incorporating the above structure is described below. The following description specifically refers to the bit-line pre-charging system applying 1/2 Vcc (Vcc: power voltage). 
     Initially, a pair of bit lines B and B are preliminarly charged with 1/2 Vcc. Next, one word line WL is selected by a low address, and then the selected word line WL goes High. As a result, capacitor 2 delivers a data signal to the bit line B, where the data signal contains &#34;HIGH&#34; information. This causes potential of the bit line B to become slightly higher than that of the other bit line B by about 100 mV. Next, the sense amplifier activating signal line SO goes High. This causes the sense amplifier 3 to amplify the potential of the High-level bit line B up to the Vcc potential and the Low-level bit line B down to the GND potential. This completes a refreshing operation f a dynamic RAM. Next, column address Ai turns the data &#34;y&#34; outputted from one column decoder High so that the output data &#34;y&#34; can be delivered to a pair of write/read signal lines I/O and I/O. The delivered data signal is then amplified by the read pre-amplifier 22 before being outputted from the dynamic RAM. On the other hand, data signal &#34;y&#34; outputted from the column decoder goes High, and then, data is written from the write buffer 21. These are the functional operations of the conventional operations of the conventional dynamic RAM for reading and writing data. 
     Since the conventional memory circuit incorporates the structure mentioned above, after completing data amplification by the sense amplifier, data signal is delivered to the write/read signal lines I/O and I/O. Because of this, any conventional dynamic RAM has those bit lines each containing substantial capacity. This in turn obliges the conventional system to take much time to execute amplification, thus eventually resulting in the delayed accessing operation. As a result, there is still substantial restriction to contract the cyclic time of the convention dynamic RAM. 
     To solve this problem, there is an idea to simultaneously activate the column decoder and the word line so that the accessing operation can be accelerated. Nevertheless, if the column decoder and the word line were simultaneously activated, since the bit line B is connected to the write/read signal line I/O containing substantial parasitic capacity, the bit-line capacity easily expands to merely lower the reading voltage. This in turn causes the memory system to easily malfunction itself. In consequence, any of those conventionally available memory systems cannot achieve accelerated accessing operation. 
     SUMMARY OF THE INVENTION 
     The invention fully solves those problems cited above by providing a novel memory circuit incorporating a current-mirror type amplifier which directly amplifies varied potential of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify minimal difference (100 mV) of potential between a pair of bit lines. As a result, the output from the current-mirror type amplifier is delivered to a data reading signal lien. In other words, data is read before the sense amplifier completes amplification of data, thus permitting the memory circuit to very quickly execute accessing operation in an extremely short period of time. 
     The primary object of the invention is to provide a novel memory circuit capable of quickly executing accessing operation at fast speed. 
     Another object of the invention is to provide a novel memory circuit capable of drastically contracting cycle time. 
     A still further object of the invention is to provide a novel memory circuit capable of drastically contracting dimension of the whole circuit by arranging the current-mirror type amplifier to share common load with the read-only signal line. 
     The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 schematically designates the circuit block diagram of a conventional memory array; 
     FIG. 2 schematically designates the block diagram of the column decoder of a conventional memory array; 
     FIG. 3 designates waveforms of a conventional memory array shown in FIG. 1; 
     FIG. 4 schematically designates the circuit block diagram of the memory array according to an embodiment of the invention; 
     FIG. 5 schematically designates the block diagram of the column decoder of the memory array according to an embodiment of the invention; 
     FIG. 6 designates waveforms of the memory array shown in FIG. 4; and 
     FIG. 7 schematically designates the circuit block diagram of the memory array according to another embodiment of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the accompanying drawings, the memory circuit according to an embodiment of the invention is described below. 
     FIG. 4 schematically designates the circuit block diagram of the memory array according to an embodiment of the invention. The reference number 1 shown in FIG. 4 designates an N-channel MOS transistor, whereas the reference numeral 3 designates a sense amplifier, respectively. Gate of this transistor 1 is connected to a word line WL, whereas the source and drain of this transistor 1 are respectively connected to a capacitor 2 and a bit line B. The bit line B, the other bit line B, and a sense amplifier activating signal line SO, are respectively connected the sense amplifier 3. The reference numerals 10 and 11 respectively designates N-channel MOS transistors which function themselves as a transfer gate. Gates of these transistors 10 and 11 respectively receive an output signal &#34;yW&#34; which is activated while the column decoder shown in FIG. 5 is engaged in the writing mode. 
     The column decoder shown in FIG. 5 comprises a NAND circuit 25 receiving column address Ai, a NOT circuit 26 and a NOR circuit 27 which are respectively connected to the output terminal of the NAND circuit 25 in parallel with each other. The other input terminal of the NOR circuit 27 receives an inverting signal &#34;W&#34; available for the writing-mode activating signal. The NOT circuit 26 and the NOR circuit 27 respectively output a signal &#34;yR&#34; which is activated in the course of reading mode and the signal &#34;yW&#34; which is activated in the course of writing mode. 
     The bit line B and a write-only signal line WI are respectively connected to the source and drain of the transistor 10. On the other hand, the other bit line B and the other write-only signal line WI are respectively connected to the source and drain of the transistor 11. A write buffer 21 is connected to the write-only signal lines WI and WI. 
     The reference numeral 100 shown in FIG. 4 designates a current-mirror type amplifier incorporating P-channel MOS transistors 101 and 102 and transistors 103, 104 and 105. Gate of the transistor 105 receives the output signal &#34;yR&#34; from the column decoder shown in FIG. 5, where the output signal &#34;yR&#34; is activated while the reading mode is underway. Gates of those transistors 103 and 104 are respectively connected to the bit line B and the other bit line B. Those transistors 103, 104 and 105 are respectively connected to each other. On the other hand, those transistors 101, 102, 103 and 104, are respectively connected to each other as shown in FIG. 4. Gates of those transistors 101 and 102 are connected to each other. 
     The reference numerals 12 and 13 respectively designate N-channel MOS transistors which function themselves as a transfer gate. Gates of these transistors 12 and 13 respectively receive the output signal &#34;yR&#34; which is activated while the column decoder embodied by the invention is engaged in the reading mode. Source of transistor 12 is connected to those transistors 101 and 103, whereas drain of the transistor 12 is connected to a read-only signal line RO. On the other hand, source of the transistor 13 is connected to those transistors 102 and 104, whereas drain of the transistor 13 is connected to the other read-only signal line RO. A read preamplifier 22 is connected to those read-only signal lines RO and RO. 
     Next, referring now to the waveform chart shown in FIG. 6, functional operation of the memory array featuring the above structure is described below. 
     Like the conventional memory array cited earlier, the memory array embodied by the invention also executes a refreshing operation as soon as the word line WL and the sense amplifier activating signal line SO respectively turn to High. Therefore, description of the refreshing operation is deleted. Functional operation of the memory array of the invention for reading and writing data is described below. 
     When the word line WL goes High, data flows into the bit line B. As a result, potential of a pair of bit lines B and B slightly varies. Simultaneously, the signal &#34;yR&#34; outputted from the column decoder shown in FIG. 5 goes High, thus activating the current-mirror type amplifier 100. In this way, both the word line WL and the current-mirror type amplifier 100 are simultaneously activated. According to the embodiment of the invention, bit-line potential is delivered to the gate of the current-mirror type amplifier 100. This prevents the bit-line capacity from expanding itself, and as a result, both the word line WL and the current-mirror amplifier 100 is routed to the read-only signal lines RO and RO, and then, the data signal is amplified by the read preamplifier 22 before being outputted. In consequence, time needed for executing an accessing operation is significantly shortened. 
     On the other hand, while the writing mode is underway, initially, the word line WL goes High to simultaneously activate the column decoder, and at the same time, the inverting signal &#34;W&#34; available for the writing-mode activating signal goes Low. This in turn causes the column decoder to output a high signal yW, thus permitting the write buffer 21 to write data via the write-only signal lines WI and WI. 
     In this way, the memory array embodied by the invention can more quickly execute the reading and writing operations. In this way, the invention has provided a novel memory circuit capable of very quickly executing the writing and reading operations by sharply contracting the cycle time. 
     According to the composition of the memory circuit embodied by the invention, since the current-mirror type amplifier 100 amplifies the bit line potential, provision of the sense amplifier 3 may be considered unnecessary. Nevertheless, as mentioned earlier, in order to properly amplify memory-cell data before refreshing the memory cell up to the Vcc potential or down to the GND potential, provision of the sense amplifier 100 amplifies the bit-line potential and then delivers the amplified potential to the read-only signal lines RO and RO, it does not feed the amplified potential back to the memory cell. 
     FIG. 7 schematically designates the circuit block diagram of the memory array according to another embodiment of the invention. The preceding embodiment provides a current-mirror type amplifier for a pair of bit lines. Instead, like the other embodiment shown in FIG. 7, a driver unit may discretely be provided for the current-mirror type amplifier 100, and yet, a load-sharing part may also be provided. Concretely, those N-channel MOS transistors 103 through 105 conjunctionally compose the driver unit, whereas those P-channel MOS transistors 110 and 111 conjunctionally compose the load-sharing part. Note that those components shown in FIG. 7 identical to those shown in FIG. 4 are respectively designated by identical reference numerals. Since the memory array shown in FIG. 7 incorporates the load-sharing part, the memory circuit can more compactly be structured than that provided the preceding embodiment. The memory array shown in FIG. 7 executes the writing and reading operations exactly in the same way as was done for the preceding embodiment, and therefore, description of the functional operation of the memory array shown in FIG. 7 is deleted. 
     As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiment is therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within the metes and bounds of the claims, or equivalence of such metes and bounds thereof are therefore intended to be embraced by the claims.