Abstract:
The dynamic range of a charging current in an open-loop LED driver circuit is scaled to provide a charging current within tolerance for the open-loop LED driver. The scaling of the dynamic range of the charging current is performed transparently to the user, such that user selected parameters for the open-loop LED driver remain unchanged during circuit performance.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a system and method for transparent dynamic scaling of a current delivered to a load. More particularly, the load current is delivered by an inductor that is controlled using an open-loop boost circuit topology that is suitable for use in LED driver applications. With the described topology, the value associated with the inductor is relatively small and the boost circuit operates over a wide operating frequency range. 
   BACKGROUND OF THE INVENTION 
   Demand for portable electronic devices is increasing each year. Example portable electronic devices include: laptop computers, personal data assistants (PDAs), cellular telephones, and electronic pagers. Portable electronic devices place high importance on total weight, size, and battery life for the devices. Many portable electronic devices employ rechargeable batteries such as Nickel-Cadmium (NiCad), Nickel-Metal-Hydride (NiMHi), Lithium-Ion (Li-Ion), and Lithium-Polymer based technologies. 
   In many portable power applications, a voltage that exceeds the battery voltage is required to operate certain circuits such as a video display. DC—DC converters are switching-type regulators that can be used to generate higher output voltages from a battery voltage. The output voltage is typically provided to a load circuit by varying the conduction time that is associated with a controlled device. Example controlled devices include transistors, gate-turn-on (GTO devices), thyristors, diodes, as well as others. The frequency, duty cycle, and conduction time of the controlled device is varied to adjust the average output voltage to the load. Typical DC—DC converters are operated with some sort of oscillator circuit that provides a clock signal. The output voltage of the converter is also determined by the oscillation frequency associated with the clock signal. 
   For certain display applications, such as stacked light emitting diodes (LEDs), both designs for boosting current driven to a load are available. However, certain designs may not meet tolerances or other required parameters of operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. 
       FIG. 1  is an illustration of an example open-loop boost circuit; 
       FIG. 2  is an illustration of an example circuit for providing a range selection signal; 
       FIG. 3  is an illustration of an example circuit for using the range selection signal to generate the charge current for the open-loop boost circuit; 
       FIG. 4  is an illustration of an example circuit for changing the capacitance value of C R  shown in  FIG. 1  according to the range selection signal; and 
       FIG. 5  is an illustration of example signal waveforms for the circuits illustrated in  FIGS. 2–4 , arranged in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention. 
   Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means a direct electrical connection between the items connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. 
   Briefly stated, the invention is related to an apparatus, system and method for dynamically scaling the range of a charging current used in providing a current delivered to a load. Current may be delivered to the load using an open-loop boost circuit topology that is suitable for LED driver applications. 
     FIG. 1  is an illustration of an example open-loop boost circuit ( 100 ) that was provided in U.S. patent application Ser. No. 10/720,953 entitled “Open Loop Magnetic Boost LED Driver System and Method” filed Nov. 24, 2003, which is assigned to the assignee of the present patent application and hereby incorporated by reference in its entirety. The open-loop boost circuit ( 100 ) includes: two capacitors (C IN , C OUT ), an inductor (L), a stack circuit (D 1 , D 2 , . . . , D N ), a Schottky-type diode (D S ), a feed-forward circuit (FFCKT), a latch circuit (LATCH), a ramp generator circuit (RAMPGEN), a resistor (R SET ), a comparator (COMP), a reference circuit (REF CKT), a transistor switch circuit (T SW ), a driver circuit (DRV), and a start-up circuit (STARTUP). 
   Capacitor C IN  is coupled between the input voltage (V IN ) and ground. Resistor R SET  is coupled between the RAMPGEN and ground. RAMPGEN is arranged to provide a ramp voltage (V RAMP ) with a known slope when enabled. Ramp voltage V RAMP  corresponds to ground when RAMPGEN is disabled via signal RES. REF CKT is arranged to provide a voltage reference (V REF ). Inductor L is selectively coupled to ground through transistor switch circuit T SW  when transistor switch circuit T SW  is active, and coupled to the stack circuit through Schottky diode D S  when transistor switch circuit T SW  is inactive. The stack circuit is coupled between Schottky diode D S  and ground. Capacitor C OUT  is coupled in parallel with the stack circuit to minimize ripple in the output voltage (V OUT ). Feed-forward circuit FFCKT is arranged to sense the voltage (V SW ) associated with the non-input side of inductor L and provides a signal to an input of latch circuit LATCH. Comparator COMP is arranged to compare ramp voltage V RAMP  to reference voltage V REF  and provide a comparison signal (V COMP ) to another input of latch circuit LATCH. One output of latch circuit LATCH is arranged to provide signal ENR. Another output of latch circuit LATCH is arranged to selectively activate transistor switch circuit T SW  via driver circuit DRV and signal V GATE . Start up circuit START UP is arranged to force signal V GATE  during a start-up sequence (when EN is active) such that inductor L is charged and the latch is initialized to an appropriate condition via comparator COMP and the feed-forward circuit. 
   An example feed-forward circuit includes a capacitor (C FF ) and an inverter circuit (IFF), which are coupled between signal V SW  and an input of the latch circuit. Changes in the signal V SW  are detected by the capacitor and fed to the latch circuit as signal V FF . For example, V FF  corresponds to a low logic level until V SW  drops below a threshold associated with inverter circuit IFF, where V FF  pulses as a high logic pulse. 
   Ramp generator RAMPGEN is illustrated as a current source (CS) that has an output coupled to a capacitor (C R ), and an input that is coupled to resistor RSET. Transistor switching circuit T SW  is configured to short capacitor (C R ) to ground when signal ENR is active such that the ramp is reset to a known value before each ramp cycle begins. Current source CS provides a current (I CHG ) to capacitor C R  such that the capacitor charges at a constant rate. The charging rate is adjusted by changing the magnitude of current I CHG , which is adjusted by resistor R SET . 
   The output current (I OUT ) is adjusted by changing a value associated with resistor R SET , which in turn adjusts the slope of ramp voltage V RAMP . The slope of ramp voltage V RAMP  controls the on-time (T ON ) associated with transistor switch circuit T SW , which in turn controls the charging of inductor L. For example, comparator COMP controls the gate voltage (V GATE ) via driver circuit DRV and latch circuit LATCH such that transistor switching circuit T SW  is disabled when the ramp voltage (V RAMP ) exceeds the reference voltage (V REF ). 
   In order to accommodate a wide range of input voltages, output currents and possible inductance values, the quantity I CHG  as shown in  FIG. 1  may have a very large dynamic range. The equation for I CHG  may be described as:
 
 I   CHG =( V   IN   2   *V   REF   *C   R )/(2 ·L·I   OUT   ·V   OUT )  (1)
 
   With, V REF  and C R  as constant values, I CHG  is proportional to the following variable quantity:
 
 I   CHG   =V   IN   2 /( I   OUT   ·L·V   OUT )  (2)
 
   One way to characterized dynamic range is to calculate the ratio of possible maximum to minimum values. Consider the case where the circuit of  FIG. 1  is designed to support an output current range of 5 mA to 65 mA, an input voltage range of 2.7V to 7.5V, and an inductance range of 1 uH to 10 uH. This makes the maximum of I CHG  divided by the minimum of I CHG , or I CHG     —     MAX/I   CHG     —     MIN , equal to:
 
 I   CHG     —     MAX   /I   CHG     —     MIN =(7.5/2.7) 2 ·(65/5)·(10/1)·(14.2/9.9) or,  (3)
 
 I   CHG     —     MAX   /I   CHG     —     MIN =1439
 
   The result of equation 3 implies that if an open-loop LED driver is designed with the minimum I CHG  to be a modest 4 uA, the maximum current would need to be (1439·4 uA) or 5.8 mA. Not only is 5.8 mA a considerable power drain, it is difficult to implement a circuit that can produce such wide dynamic ranges with high accuracy. Accuracy may be especially important in an open loop architecture, because unlike closed loop drivers where errors in control circuits are attenuated by large loop gains, any inaccuracy in open loop control contributes directly to the output error. 
   The method and architecture provided below in  FIGS. 2–6  reduces the I CHG  dynamic range. Furthermore, the reduction of the dynamic range is made transparent to the user such that an extra range selection input is not needed. 
     FIG. 2  is an illustration of an example circuit for providing a range selection signal in accordance with the present invention. Selection signal circuit  200  is arranged to provide a selection signal (BGR). The selection signal (BGR) is used to select a value for capacitor C R  of the open-loop LED driver circuit of  FIG. 1 , and to select a resistance value (R A ) shown in  FIG. 3  that is used in producing the charge current I CHG . The value of capacitor C R  and resistance R A  are selected to reduce the dynamic range for the charge current (I CHG ). 
   Transistors Q 3  and Q 4  with resistors Ry and Rx are arranged as in a current mirror configuration. Transistors M 2  and M 3  are also arranged in a current mirror configuration. Transistors Q 3 , Q 4 , M 2 , and M 3  therefore have the same current (I RSET  mirrored from transistor M 7 ) flowing through them. Accordingly, I RSET  is also flowing through the external resistor (RSET) that is coupled to the emitter of transistor Q 2  and gate of transistor Q 3 . A capacitor (C X ) is coupled between ground and the connection between the source of transistor M 1  and the collector of transistor Q 1 . The purpose of C X  is to provide frequency compensation for the feedback loop formed by Q 1  and Q 2 . In the embodiment shown, I RSET =V BG /RSET, Where V BG  is a bandgap voltage. The bandgap voltage may be generated according to a bandgap reference circuit or another voltage reference may also be used. 
   Transistors M 3  and M 4  form a current comparator. When I RSET  is higher than a predetermined threshold (e.g., 50 uA), node N 1  approaches a logic low level. Conversely, when I RSET  is lower than the predetermined threshold (e.g., 50 uA), node N 1  approaches a logic high level. Inverters INV 1  and INV 2  provide extra gain to the comparator. In other embodiments, any number of inverters, including none, may be used at the output for the selection signal (BGR). Transistors M 5  and M 6  are included in the embodiment shown to provide a small positive feedback to the comparator (M 3  and M 4 ). The small positive feedback provides hysteresis to reduce runt pulses. 
   When BGR corresponds to a logic high level, a first scaling region is selected, and C R  and R A  are selected to have a first set of values to scale I CHG  to an acceptable level. Correspondingly, when BGR corresponds to a logic low level, a second scaling region is selected, and C R  and R A  are selected to have a second set of values to scale I CHG  to an acceptable level. Adjustment of C R  and R A  based upon the value of BGR is described in greater detail below with respect to  FIGS. 3 and 4 . 
   The dynamic range scaling method of the present invention utilizes the observation that I CHG  is inversely proportional to I RSET  (the current that flows through RSET). In the open loop architecture, RSET is chosen based on most of the dynamic range setting components that are selected for a particular application. These components are: I OUT , L, and V OUT . Accordingly, once an input voltage (V IN ) is also selected, the dynamic range of I CHG  may be scaled based on I RSET . The following equations provide the relationship between RSET, I RSET , and I CHG :
 
 RSET=Eff·Vref 1 ·Vref 2 ·C   R   ·R   A   2 /( I   OUT ·2 ·L·V   OUT )  (4)
 
 I   RSET   =Vref 2/ RSET =2 ·I   OUT   ·L·V   OUT /( Eff·Vref 1· C   R   ·R   A   2 )  (5)
 
 I   CHG =( V   IN   /R   A ) 2   /I   RSET   =V   in   2   ·RSET /( R   A   2   ·Vref 2)  (6)
 
   The value of RSET is a selected value that may be selected by a user according to design tolerances or other parameters. Accordingly, the value of C R ·R A   2  is held constant so that the user does not perceive a change in value for RSET. However, the individual values of C R  and R A  may be changed as long as the product of C R ·R A   2  is held constant. Adjusting the capacitance of C R  and the resistance of R A  depending on the value of I RSET  provides scaling of the dynamic range for the charge current (I CHG ), where the scaling is performed transparent to the user. 
     FIG. 3  is an illustration of an example circuit for using the range selection signal to generate the charge current for the open-loop boost circuit. Resistors R A1 , R A2 , R A3 , and R A4  in series forms resistance circuit R A , and resistors R B1  and R B2  in series forms resistance circuit R A /2. The resistance circuits (R A  and R A /2) are both used in generating the charge current (I CHG ). When BGR corresponds to a logic high level, transistors M 10  and M 11  are both off. With transistor M 10  off, resistance circuit R A  corresponds the series addition of resistors R A1 , R A2 , R A3 , and R A4 . Similarly, with transistor M 11  off, resistance circuit R A /2 corresponds to the series addition of resistors R B1  and R B2 . Correspondingly, when BGR corresponds to a logic low level, transistors M 10  and M 11  are both on. With transistor M 10  on, resistance circuit R A  corresponds the series addition of resistors R A3  and R A4 . Similarly, with transistor M 11  on, resistance circuit R A /2 corresponds to resistor R B1 . 
   Transistors Q 11  and Q 12  are arranged to provide a voltage across resistance circuit R A  to set the collector current (I C1 ) of transistor Q 10  as: I C1 =(V IN −2V BE )/R A . Transistors Q 10  and Q 11  are arranged in a current mirror configuration such that they have substantially the same collector current. Resistance circuit R A /2 is arranged in parallel with transistor Q 11  such that the current through resistor R A /2 corresponds to I RB =2V BE /R A . The resulting collector current through transistor Q 13  corresponds to V IN /R A . 
   Transistors Q 13  and Q 14  with resistors R C  and R D  are arranged in a current mirror configuration such that their collector currents are ratio matched (X·I 1 =I 2 ), where collector current I 1  is given by I 1 =I Q =V IN /R. Transistors Q 15  and Q 17  are arranged to operate as diodes that are biased by current I 2 =X·V IN /R. 
   The current (I RSET ) through the external resistor (RSET) is coupled to the emitter of transistor Q 16  and the base of transistor Q 20 . Since transistor Q 16  has a collector current of I 2  and an emitter current of I RSET , the base current to transistor Q 20  corresponds to (I 2 −I RSET ), resulting in a collector current for transistor Q 20  that is proportional to I 2 2/I RSET . Transistors Q 18  and Q 19  with resistors R E  and R F  are arranged in a current mirror configuration such that their collector currents are ratio matched. The resulting current at the collector of transistor Q 19  corresponds to I CHG =I 2 2/I RSET . Since I 2  is proportional to V IN /R A , then I CHG  is proportional to the ratio: (V IN /R A ) 2 /(R SET ) as described in Equation 6 above. 
     FIG. 4  is an illustration of an example circuit for changing the capacitance value of C R  shown in  FIG. 1  according to the range selection signal, in accordance with the present invention. 
   As previously stated, the product of C R ·R A   2  is held substantially constant such that C R  and R A  may be adjusted to select the dynamic range of the charging current (I RSET ) without being reflected in the expected output of the open-loop LED driver. The resistance of R A  is selected in response to the selection signal (BGR). The capacitance of C R  is also selected in response to the selection signal (BGR) and corresponds to R A . 
   In the embodiment shown, an inverter (INV 4 ) inverts the selection signal to activate and deactivate a transistor (M 30 ). Transistor M 30  acts as a switch, to include or remove capacitor C R1  in parallel with capacitor C R2 . When the selection signal (BGR) corresponds to a low logic level, transistor M 30  is off and the value capacitance circuit C R  in  FIG. 1  corresponds to the value of capacitor C R2 . Similarly, when the selection signal (BGR) corresponds to a high logic level, transistor M 30  is on, and the value capacitance circuit C R  corresponds to the value of capacitors C R1  and C R2  in parallel. 
   In an alternative embodiment, an additional switch circuit responsive to the selection circuit may be included to switch between two or more capacitors rather than accumulating or removing capacitors in parallel. 
     FIG. 5  is an illustration of example signal waveforms for the circuits illustrated in  FIGS. 2–4 , in accordance with the present invention. Illustrated is a plot ( 510 ) of the selection signal (BGR), and a plot ( 520 ) of I CHG  vs. RSET for the corresponding values of BGR, with V IN  set to 3.6V. The x-axis for both plots is the RSET resistance value. RSET ranges from 1 kOhm to 300 kOhm. The y-axis of the first plot ( 510 ) corresponds to the range selection signal (BGR). It switches from logic low to logic high when RSET is at about 22 kOhms. The y-axis of the second plot is I CHG . As indicated in Equation (6), I CHG  is linearly proportional to RSET, and it has a slop of [V IN   2 /(R A   2 ·Vref2)]. In this example, when BGR=0, R A =48 kOhm and the open-loop LED driver is in region 2. When BGR=1, R A =180 kOhm and the open-loop LED driver is in region 1. The different R A  values produce different I CHG  slopes in the two regions, as expected. But the dynamic ranges for the charging current (I CHG ) in both regions are designed to be about equal (e.g., between 10 uA and 100 uA). 
   As an example of the dynamic range scaling provided by the present invention, let:
         C RX ·R AX   2 =C RZ ·R AZ   2 =constant=0.02;   Vref1=Vref2=1.2V; and
           For I RSET &lt;55 uA (region 1):
               R AX =R AZ =180 kOhm, and   C RX =C RZ =0.62 pF.   
               Else (region 2):
               R AX =R AZ =48 kOhm, and   C RX =C RZ =8.68 pF.   
               
               

   Substituting the above values into Equations (5) and (6) above and assuming Eff is unity, the resulting calculations provide
         For region 1:
           I RSET     —     MIN =(2·5 mA·1 uH·9.9V)/(1.2V·0.02)=4.1 uA;   I RSET     —     MAX =55 uA;
               I CHG     —     MIN =(2.7V/180 k) 2 /55 uA=4.1 uA; and   I CHG     —     MAX=( 7.5V/180 k) 2 /4.1 uA=423 uA.   
               
           For region 2:
           I RSET     —     MIN =55 uA;   I RSET     —     MAX =(2·65 mA·10 uH·14.2V)/(1.2V·0.02)=769 uA;
               I CHG     —     MIN =(2.7V/48 k) 2 /769 uA=4.1 uA; and   I CHG     —     MAX =(7.5V/48 k) 2 /55 uA=443 uA.   
               
               

   As a result of the scaling in the above example, the dynamic range of I CHG  in both regions 1 and 2 is reduced by a considerable factor when compared to an un-scaled dynamic range as shown in equation 3. Also because the product C R ·R A   2  is kept relatively constant, the user can choose RSET based on a single formula (e.g., equation 4). Also, even though in the example above, only two dynamic range regions were chosen, the same method may be extended to create more than two dynamic range regions as desired. 
   The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.