Abstract:
A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Korean Patent Application No. 10-2004-0096168, filed on 23 Nov. 2004, the content of which is incorporated by reference in its entirety for all purposes. 
     
    
     BACKGROUND  
       [0002]     1. Technical Field  
         [0003]     This disclosure relates to a method of fabricating semiconductor memory devices, and more particularly, to a method of fabricating static random access memory devices.  
         [0004]     2. Discussion of Related Art  
         [0005]     Generally, static random access memories (SRAMs) have been widely used in a field of middle- or small-sized computers because the memories operate at a high speed despite lower integration compared to dynamic random access memories (DRAMs). A conventional SRAM cell is typically composed of a flip flop circuit that includes two transfer transistors, two driver transistors, and two load elements. Information is represented as a difference in voltage between the input and output terminals of the flip flop, i.e., charges accumulated on a node of the cell. The charges are always supplemented via a PMOS transistor or a load resistor as a load element from power supply voltage (Vcc), and thus, unlike DRAMS, SRAMs need not have a refresh function.  
         [0006]     SRAM memory cells may be further classified as either high-resistance cells that utilize a high resistance load element or as Complementary Metal Oxide Semiconductor (CMOS) cells that utilize a P-channel Metal Oxide Semiconductor (PMOS) transistor as the load element.  
         [0007]     CMOS cells may be further classified as either thin film transistor cells that utilize a thin film transistor as the load element or as complete CMOS cells that utilize a bulk transistor as the load element.  
         [0008]      FIG. 1  is a circuit diagram illustrating a conventional CMOS cell.  
         [0009]     Referring to  FIG. 1 , the CMOS cell  100  is composed of a pair of driver transistors TD 1  and TD 2 , a pair of transfer transistors TA 1  and TA 2 , and a pair of load transistors TL 1  and TL 2 . The driver transistors TD 1  and TD 2  and the transfer transistors TA 1  and TA 2  are N-channel Metal Oxide Semiconductor (NMOS) transistors while the load transistors TL 1  and TL 2  are both PMOS transistors.  
         [0010]     The first driver transistor TD 1  and the first transfer transistor TA 1  are connected in series. A source region of the first driver transistor TD 1  is connected to a ground line Vss and a drain region of the first transfer transistor TA 1  is connected to a first bit line BL.  
         [0011]     Similarly, the second driver transistor TD 2  and the second transfer transistor TA 2  are connected in series. A source region of the second driver transistor TD 2  is connected to the ground line Vss and a drain region of the second transfer transistor TA 2  is connected to a second bit line /BL. The first and second bit lines BL and /BL carry opposite information. That is, if the BL is at logic “1,” /BL is at logic “0.” 
         [0012]     A source region of the first load transistor TL 1  is connected to a power line Vcc. A drain region of the first load transistor is connected to a drain region of the first driver transistor TD 1 . In other words, the drains of the transistors TL 1  and TD 1  share a common first node.  
         [0013]     Similarly, a source region of the second load transistor TL 2  is connected to the power line Vcc and a drain region of the second load transistor is connected to a drain region of the second driver transistor TD 2 . In other words, the drains of the transistors TL 2  and TD 2  share a common second node.  
         [0014]     A gate electrode of the first driver transistor TD 1  and a gate electrode of the first load transistor TL 1  are both connected to the second node. A gate electrode of the second driver transistor TD 2  and a gate electrode of the second load transistor TL 2  are both connected to the first node. In addition, gate electrodes of the first and second transfer transistors TA 1  and TA 2  are connected to a word line WL.  
         [0015]     SRAMs may often be multi-layered to achieve high integration of semiconductor devices.  
         [0016]      FIGS. 2A-2D  are sectional diagrams illustrating a conventional method of fabricating an SRAM.  
         [0017]     Referring to  FIG. 2A , a conductive layer (not shown) is deposited on a semiconductor substrate  1 . A gate line  2  is formed using by performing a photolithographic process on the conductive layer. An insulating sidewall  3  is then formed on a side surface of the gate line  2  using an etch back process.  
         [0018]     A first insulating film  4  is formed on surface of the semiconductor substrate and on the gate line  2 , and then a first interlayer insulating film  5  is formed on the first insulating film  4 . The first insulating film  4  prevents diffusion of impurities in a device, such as an SRAM, and may also be used as an etch stopping layer in an etching process. The first insulating film  4  is composed of SiOn or SiN. The first interlayer insulating film  5  is an interlayer dielectric (ILD) film (oxide film).  
         [0019]     Photoresist is then deposited on the first interlayer insulating film  5 . Using exposing and developing processes, a photoresist pattern PR is formed with a uniform interval.  
         [0020]     As shown in  FIG. 2B , the first interlayer insulating film  5  and the first insulating film  4  are selectively removed using the photoresist pattern PR as a mask.  
         [0021]     As shown in  FIG. 2C , using selective epitaxial growth (SEG), a single crystalline silicon layer  8  is grown in a region  7  defined by the photoresist pattern PR.  
         [0022]     Pre-flow of silane (SiH 4 ) is carried out on the first interlayer insulating film  5  and the single crystalline silicon layer  8 . This prevents a natural oxide film, such as silicon dioxide (SiO 2 ), from forming on the first interlayer insulating film  5  and the single crystalline silicon layer  8 .  
         [0023]     As shown in  FIG. 2D , a process temperature is elevated to a predetermined temperature and then an amorphous silicon layer  9  is deposited on the first interlayer insulating film  5  and the single crystalline silicon layer  8  using a suitable method, e.g., sputtering, plasma enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). The amorphous silicon layer  9  is annealed in order to become crystallized. The single crystalline silicon layer  8  serves as a seed for crystallization of the amorphous silicon layer  9 . The crystallized silicon layer serves as channel silicon.  
         [0024]     Unfortunately, during the annealing of the amorphous silicon layer  9 , a thinning phenomenon may occur such that the resulting crystallized silicon layer has a thinned profile in a region around the single crystalline silicon layer  8 .  
         [0025]      FIG. 3  is a photograph illustrating the thinning phenomenon in which the crystallized silicon layer has a thin profile in a region  11  around a single crystalline silicon layer. This reduction in thickness of the crystallized silicon layer is undesirable because the thinner portion of the silicon layer may be removed during subsequent processes.  
         [0026]     Embodiments of the invention address these and other disadvantages of the conventional art.  
       SUMMARY  
       [0027]     Embodiments of the invention may reduce the occurrence of a thinning phenomenon in a silicon layer by recessing the ILD and depositing an amorphous silicon layer at low temperature. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]      FIG. 1  is a circuit diagram illustrating a conventional CMOS cell.  
         [0029]      FIGS. 2A-2D  are sectional diagrams illustrating a conventional method of fabricating an SRAM.  
         [0030]      FIG. 3  is a photograph illustrating a thinning phenomenon resulting from the conventional method illustrated in  FIGS. 2A-2D .  
         [0031]      FIGS. 4A-4E  are sectional diagrams illustrating a method of fabricating an SRAM according to some embodiments of the invention.  
         [0032]      FIG. 5  is a graph illustrating the reduction in the thinning rate associated with some embodiments of the invention.  
         [0033]      FIG. 6  is a graph illustrating the reduction in the thinning rate that is associated with some other embodiments of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0034]     Preferred embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The invention may, however, also be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as teaching examples of the invention. Like numbers refer to like elements.  
         [0035]     According to embodiments of the invention, a first interlayer insulating film is recessed through etching and then an amorphous silicon layer is deposited on the first interlayer insulating film and a single crystalline silicon layer at low temperature.  
         [0036]      FIGS. 4A-4E  are sectional diagrams illustrating a method of fabricating an SRAM according to some embodiments of the invention.  
         [0037]     A shown in  FIG. 4A , a conductive layer (not shown) is deposited on a semiconductor substrate  101 . A gate line  102  is formed by performing a photolithographic process on the conductive layer. An insulating sidewall  103  is then formed on a side surface of the gate line  102  using an etch back process.  
         [0038]     A first insulating film  104  is formed on a surface of the semiconductor substrate and on the gate line  102 . A first interlayer insulating film  105  is formed on the first insulating film  104 .  
         [0039]     The first insulating film  104  may prevent diffusion of impurities in a device, such as an SRAM, and may also be used as an etching stopping layer in an etching process. The first insulating film  104  may be composed of SiON, SiN, or a similar material. The first interlayer insulating film  105  may be an interlayer dielectric (ILD) film that is composed of an oxide film.  
         [0040]     Photoresist is then deposited on the first interlayer insulating film  105 . Using exposing and developing processes, a photoresist pattern PR is formed with a uniform interval.  
         [0041]     As shown in  FIG. 4B , the first interlayer insulating film  105  is selectively removed using the photoresist pattern PR as a mask, so that a contact is formed.  
         [0042]     As shown in  FIG. 4C , a single crystalline silicon layer  108  is grown in a region  107  defined by the photoresist pattern using selective epitaxial growth (SEG).  
         [0043]     As shown in  FIG. 4D , the first interlayer insulating film  105  surrounding the single crystalline silicon layer  108  is recessed by etching. This process may be referred to as an Inter-Layer Dielectric (ILD) recess process. Next, a pre-flow of silane (SiH 4 ) is carried out on the first interlayer insulating film  105  and the single crystalline silicon layer  108 .  
         [0044]     As shown in  FIG. 4E , an amorphous silicon layer  109  is deposited on the first interlayer insulating film  105  and the single crystalline silicon layer  108  using a suitable method (e.g., a method such as sputtering, PECVD, or LPCVD). Before the amorphous silicon layer  109  is deposited, the process temperature is preferably set to a predetermined temperature. The predetermined temperature preferably ranges from about 450° C. to about 500° C. After the deposition process, the amorphous silicon layer  109  preferably covers a top surface of the single crystalline silicon layer  108  and partially covers the side surfaces of the single crystalline silicon layer.  
         [0045]     An annealing process is then performed on the amorphous silicon layer  109  so that it becomes crystallized. Here, the single crystalline silicon layer  108  serves as a seed for crystallization of the amorphous silicon layer  109 . The crystallized silicon layer  109  serves as channel silicon.  
         [0046]     Depositing and annealing the amorphous silicon layer following the ILD recessing reduces the occurrence of the thinning phenomenon.  
         [0047]      FIG. 5  is a graph illustrating the reduction in the thinning rate associated with some embodiments of the invention. In particular,  FIG. 5  illustrates the reduction in thinning rate that can be achieved using the ILD recess process according to some embodiments of the invention. As shown in  FIG. 5 , the thinning rate for the crystallized silicon layer is about 70% when the conventional process is used. On the other hand, when the ILD recess method according to some embodiments of the invention is used, the thinning rate drops to about 30%. The thinning rate indicates to what extent the thickness of the crystallized silicon layer is reduced in the area around the single crystalline silicon layer. As shown in  FIG. 5 , the ILD recess process according to some embodiments of the invention reduces the thinning rate.  
         [0048]      FIG. 6  is a graph illustrating the reduction in the thinning rate that is associated with some other embodiments of the invention. In particular,  FIG. 6  illustrates the thinning rate of the silicon layer as a function of the deposition temperature of the amorphous silicon layer.  FIG. 6  illustrates that as the deposition temperature for the amorphous silicon layer is reduced, the thinning rate is reduced as well. Thus, according to other embodiments of the invention, it is possible to further reduce the thinning rate by using the ILD recess process described above in conjunction with lowering the deposition temperature of the amorphous silicon layer.  
         [0049]     The invention has been described above using preferred exemplary embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. To the contrary, the scope of the invention is intended to include various modifications and alternative arrangements within the capabilities of persons skilled in the art using presently known or future technologies and equivalents. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.