Abstract:
Several techniques are provided to increase the efficiency and reduce the EMI of produced by a multiphase switching voltage regulator. According to one technique, a multiphase switching voltage regulator is controlled by varying in time the duration and/or position of each switching pulse for each of a plurality of channels of the switching voltage regulator in response to one or more signals representing a state of each of a plurality of channels of the voltage regulator. According to a second technique, a method is provided for controlling a multiphase switching voltage regulator comprising operating each channel of the voltage regulator at a different frequency. The timing of the switching pulses to each channel is scheduled to avoid time-overlap of switching pulses for two or more channels.

Description:
RELATED APPLICATION  
       [0001]     This application claims priority to U.S. Provisional Application No. 60/644,024, filed Jan. 18, 2005, the entirety of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a voltage regulator for a power supply device, and more specifically to an improved low noise voltage regulator using digitally controlled switching techniques.  
         [0003]     Switching voltage regulators are commonly used in power supply devices, such as those used in consumer appliances, e.g., personal computers, electronic appliances, etc.  FIG. 1  generally illustrates the form of a current evolution of a three-phase voltage regulator shown at reference numeral  10  designed for better line and load regulation.  
         [0004]     A three-phase voltage regulator  10  comprises a single pulse width modulation (PWM) control integrated circuit (IC)  20  and three channels  30 ( 1 ),  30 ( 2 ), and  30 ( 3 ). Each channel  30 ( i ) comprises a driver circuit  40 ( i ), a high-side supply transistor  42 ( i ), a low-side sink transistor  44 ( i ) and an energy-storage inductor  46 ( i ). In operation, the PWM control IC turns on each individual transistor in the channels on a synchronized schedule to manage the timing of the storage of energy in the resonant circuit formed by the corresponding inductor in that channel and a common capacitor  48  shared by all of the channels.  
         [0005]     Exemplary waveforms for the three-phase switching voltage regulator system  10  are shown in  FIG. 2  and illustrate the concept of interleaved switching to control the voltage regulator output. The width of each PWMn pulse (PWM 1 , PWM 2 , PWM 3 ) controls the duration of the conduction period for the respective high-side supply transistors  42 ( i ) in the corresponding channel  30 ( i ). When each PWMn pulse is low, the respective low-side sink transistor  44 ( i ) conducts in the corresponding channel  30 ( i ). The driving signal to the low-side sink transistor  44 ( i ) may optionally be derived separately from the driving signal for the high-side source transistor  42 ( i ) so that its timing may be independently adjusted. Using well-known pulse width modulation techniques, the width of each PWMn pulse is adjusted to control the amount of energy stored in the inductor for the associated channel. This in turn controls the transfer of that energy to the common capacitor and, consequently the output voltage of the regulator. The positive series reactance of the separate channel inductors and the negative reactance of the shared capacitor also provide a filtering action that removes switching artifacts from the regulator output, providing a relatively steady, direct-current (DC) voltage.  
         [0006]     The purpose of the low-side transistor  44 ( i ) is to supply current to the corresponding inductor  46 ( i ) from the circuit ground, when the current supplied by the high-side source transistor  44 ( i ) is off. If the low-side transistor current path was not provided, the voltage on the “near side” of the inductor  46 ( i ) would rise until it broke down a path to a current source. This is a result of the fact that the current through an inductor must be continuous, but the voltage across it may change instantaneously.  
         [0007]     The low-side transistor needs to be turned off sufficiently in advance of the high-side transistor being turned off to avoid the voltage breakdown problem. This results in “shoot-through” current from the regulator input voltage to ground through the two transistors, which reduces the regulator&#39;s overall efficiency.  
         [0008]     Several advantages can be realized by increasing the frequency of the driving signal pulses and the number of phases in the voltage regulator. Since the resonant frequency of the separate channel inductors and the common capacitor is given by,  
         f   PWM     =     1     2   ⁢   π   ⁢         L   channel     ⁢     C   common                 
 
 Increasing the pulse frequency allows reduction of the values of the inductors and capacitor to provide equivalent filtering of switching artifacts in the regulator&#39;s output. Use of smaller inductors and capacitors eases physical placement constraints and reduces the total circuit area consumed by inductors and capacitors. 
 
         [0009]     With more phases, less current is required of each channel because the total current is shared across more channels, reducing energy loss and heat generation resulting from both conductor losses in the inductor wiring and flux losses in the inductor&#39;s magnetic core material. Decreasing the current switched at any instant in time also reduces the amount of electromagnetic interference (EMI) that the circuit generates and allows the switching transistors to be air-cooled while mounted in a vertical position to further save circuit board area.  
         [0010]     Operating more phases necessitates reduction of the maximum duty cycle of each individual phase to prevent the time overlap of signals in any two phases which would interrupt the proper scheduling of energy delivery from the separate inductors in each channel to the common capacitor. According to Fourier theory, reducing the duty cycle of a pulse train increases the range of frequencies over which the spectral energy produced by the pulse train is spread. This reduces the amount of spurious energy produced at any single frequency.  
         [0011]     Nevertheless, increasing the pulse frequency and the number of phases places more stringent constraints on the timing of individual PWMn pulses. A common two-phase system operating at 200 KHz requires a PWMn pulse to be generated every 2.5 μs. Controlling pulse width to within 1% to provide the necessary load regulation requires timing control of 25 ns. Likewise, a sixteen-phase system operating at 10 MHz to realize the benefits described above requires timing control of 62.5 ps, which is well beyond the capabilities of today&#39;s digital multiphase switching voltage regulator systems. Even more precise control of separate driving signals to the high-side source transistor and the low-side sink transistor must be maintained to prevent voltage breakdown of the transistors while reducing efficiency losses due to shoot-through current from the regulator input to ground through the two transistors. Moreover, the repeated generation of the energetic PWMn pulses produces EMI at both the fundamental frequency of the pulse generation, the inverse of the repetition rate, and at harmonics of this frequency.  
         [0012]     There is room for significantly improving voltage regulators and more particularly to reducing EMI and enhance performance of a switching voltage regulator. By monitoring the state of the voltages across the high-side and low-side transistors and taking advantage of precise timing capability, it is possible to increase the efficiency of the voltage regulator without exposure to voltage breakdown.  
       SUMMARY OF THE INVENTION  
       [0013]     Briefly, several techniques are provided to increase the efficiency and reduce the EMI produced by a multiphase switching voltage regulator. According to one technique, a multiphase switching voltage regulator is controlled by varying in time the duration and/or position of each switching pulse for each of a plurality of channels of the switching voltage regulator in response to one or more signals representing a state of each of a plurality of channels of the voltage regulator.  
         [0014]     According to another technique, a method is provided for controlling a multiphase switching voltage regulator comprising operating each channel of the voltage regulator at a different frequency. The timing of the switching pulses to each channel is scheduled to avoid time-overlap of switching pulses for two or more channels.  
         [0015]     Other objects and advantages will become more apparent when reference is made to the following description taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a schematic diagram of a prior art three-phase switching voltage regulator.  
         [0017]      FIG. 2  is a timing diagram of the waveforms for an interleaved switching control of a three-phase voltage regulator according to the prior art.  
         [0018]      FIG. 3  is a block diagram of a control circuit for a switching voltage regulator according to a first embodiment of the present invention.  
         [0019]      FIG. 4  is a timing diagram that illustrates a technique for randomly or pseudo-randomly varying the position in time of each switching pulse in a voltage regulator to reduce electromagnetic interference (EMI) according to the first embodiment of the present invention.  
         [0020]      FIG. 5  is a block diagram of a switching voltage regulator system in which each channel is operated at a different frequency according to a second embodiment of the present invention.  
         [0021]      FIG. 6  is a block diagram of a threshold detector circuit in the switching voltage regulator system shown in  FIG. 5 .  
         [0022]      FIG. 7  is a block diagram of a scheduling logic circuit useful in the switching voltage regulator system shown in  FIG. 5  according to an embodiment of the invention.  
         [0023]      FIG. 8  is a block diagram of a scheduling logic circuit useful in the switching voltage regulator system shown in  FIG. 5  according to another embodiment of the invention.  
         [0024]      FIG. 9  is a timing diagram depicting operation of the switching voltage regulator system shown in  FIG. 5 . 
     
    
     DETAILED DESCRIPTION  
       [0025]     Referring first to  FIGS. 3 and 4 , a first embodiment or aspect of the invention is described. According to the first embodiment of the invention, the positions in time of the PWMn pulses to the high-side source transistors  42  and low-side sink transistors  44  in each channel of the voltage regulator are slightly varied to spread electromagnetic interference (EMI) over a wider band of spectrum. Subtle adjustments to the position in time of each PWMn pulse as shown by the dotted black lines in  FIG. 4  are made to reduce the amount of EMI on any given frequency. Rather than varying this adjustment in a periodic way akin to spread-spectrum modulation, the PWM control circuit  20 ′ uses the random or pseudo-random number generator  60  to impose random or pseudo-random adjustment to the position in time and width (duration) of each pulse PWM 1  to PWMn.  FIG. 4  shows the example where n=3, but of course this can be generalized to any one or more phases of a switching voltage regulator. Random or pseudo-random adjustment reduces EMI without simply creating sidebands of energy displaced by the frequency of the spread-spectrum modulation from the PWM generation frequency and its harmonics as would be the case if the positions were varied in a periodic way.  
         [0026]     EMI may be further reduced at any given frequency and better spread across a spectrum by operating each regulator channel at a different frequency. Thus, according to a second embodiment of the invention, the frequency of the pulses for each of the channels is different, and because the pulse frequencies are different the pulses are scheduled so as to avoid overlap in time of the pulses across the channels. The techniques of the first and second embodiments may be combined so as to introduce random or pseudo-random adjustment to the occurrence and width (duration) of the different frequency pulses.  
         [0027]     Adding such capabilities in a PWM control circuit increases the burden of controlling the timing of PWM pulses by another order of magnitude to 6.25 ps and increases the number of individual synthesizers in the PWM control circuit. Implementing these capabilities using analog pulse generators may be cost-prohibitive for certain applications, while using so-called delay-locked loops may not provide the necessary level of timing control.  
         [0028]     A digital arbitrary waveform synthesizer (AWS) may be used in a PWM control circuit to control the position of the pulses in each of the channels to prevent time-overlap, and to generate the pulse positions to prevent overlap in a multi-frequency channel voltage regulator system. An example of an AWS is disclosed in commonly assigned U.S. Pat. Nos. 6,377,094 and 6,664,832, entitled “Arbitrary Waveform Synthesizer Using a Free-Running Oscillator”. The entirety of each of these patents is incorporated herein by reference.  
         [0029]     The different frequencies for the control pulses may be implemented by choosing an inductor value for each channel that corresponds to the frequency at which that channel operates. For example, channel  1  may have an inductor L 1  of a certain value to operate at frequency f 1 , channel  2  may have an inductor L 2  of a certain value to operate at frequency f 2 , and so on. Operating each channel at a different frequency further reduces the amount of EMI at any given frequency. Because the frequency of each channel is different, two or more of the PWM pulses could overlap in time unless properly scheduled not to do so. Logic is provided in the PWM control circuit to provide the precise control of the position in time of each pulse to prevent these overlaps and therefore prevents producing undesirable spikes in the output voltage. Significant improvements in voltage regulation operation can be realized by monitoring the state of each of the voltage regulator channel output signals and adjusting the timings and widths of the PWM pulses to achieve outputs as close as possible to the ideal.  
         [0030]     An example of a 4-phase switching voltage regulator system  200  is shown in  FIG. 5 . As indicated above, each channel operates at a different frequency by using different values of inductors, L 1 , L 2 , L 3  and L 4 . The voltage regulator system  200  monitors the state of each channel or phase as well as the output voltage V OUT . There are many ways to monitor the state of each phase of the voltage regulator. One way is to monitor the signals from the driver circuit  40 ( i ) to the high side transistor  42 ( i ) and the low side transistor  44 ( i ) and the voltage on the near side of the inductor L i  as shown in  FIG. 5 . To this end, control circuitry is provided for each channel “i” including a network  250 ( i ) of threshold detector circuits and scheduling logic component  300 ( i ). The threshold detector network  250 ( i ) for each channel “i” includes threshold detector  100 ( 1 )(i) that monitors the output voltage V OUT , threshold detector  100 ( 2 )(i) that monitors the driver circuit signal to the high side transistor  42 ( i ), threshold detector  100 ( 3 )(i) that monitors the driver circuit signal to the low side transistor  44 ( i ) and threshold detector  100 ( 4 )(i) that monitors the voltage of the near side of inductor Li.  
         [0031]     The outputs of the network of threshold detectors  100 (I)(i),  100 ( 2 )(i),  100 ( 3 )(i) and  100 ( 4 )(i), for i=1 to n, are connected to the corresponding scheduling logic component  300 ( i ). The scheduling logic component  300 ( i ) takes in the channel “i” state information from the threshold detector network  250 ( i ) and generates the driver control signal PWMi, where each pulse train PWMi is at a different frequency. Electrical communication between the scheduling logic components  300 ( i ), shown by dotted line  400  between the scheduling logic components  300 ( i ) is provided so that the scheduling logic components  300 ( i ) output the driver control signal pulses to avoid any overlap in time between two or more pulses in different channels. Moreover, the scheduling logic component  300 ( i ) may introduce slight random or pseudo-random timing adjustments to the pulses as well to achieve the associated benefits described above in conjunction with  FIGS. 3 and 4 .  
         [0032]      FIG. 5  shows two connections between each scheduling logic component  300 ( i ) and the corresponding driver circuit  40 ( i ) in the event that the driver circuit  40 ( i ) is capable of separately controlling the high-side transistor  42 ( i ) and low-side transistor  44 ( i ) to prevent “shoot-through” current. In that case, the scheduling logic  300 ( i ) generates two PWM signals, one for the high-side transistor and one for the low-side transistor.  
         [0033]     Turning to  FIG. 6 , an example of a threshold detector used in the threshold detector networks  250 ( i ) is shown. The threshold detector compares an input analog signal value from the switching voltage regulator to a programmable DC threshold value (V TH ), shown as rheostat  101 , and outputs the time at which the input analog signal value crosses the threshold V TH . The threshold value may be different depending on which analog signal value is being monitored by the threshold detector (output voltage, high side transistor, low side transistor or voltage at inductor).  
         [0034]     The threshold detector comprises an AWS component  105 , a logic circuit  110 , a ring capture circuit  120 , a comparator  130  and a sample/hold amplifier  140 . The AWS  105  comprises a ring oscillator  106 , a ring capture circuit  107 , clock logic  108  and a selector channel circuit  109 . The function of the AWS  105  is to very precisely measure the frequency of the ring oscillator  106  and to supply a timing calibration signal to the logic circuit  110 . The sample/hold amplifier  140  receives as input the analog signal to be monitored and holds a sample value in response to the “sample” signal from the logic circuit  110 . The comparator  130  compares the sample and held signal value with the threshold V TH  and produces a pulse when the signal value crosses the threshold V TH . The ring capture circuit  120  outputs a threshold crossing event signal that represents the time, with respect to the ring oscillator  106  in the AWS  105  that the comparator  130  outputs the pulse associated with the threshold crossing. The logic circuit  110  processes the timing calibration signal from the AWS  105  and the threshold crossing event signal from the ring capture circuit  120  and outputs a very precise threshold crossover time for that analog signal input to the threshold detector. The threshold detector is essentially a one-bit analog-to-digital converter (ADC). The rheostat  101  that supplies a DC threshold value may be replaced with a timed sawtooth ramp to allow for a more general, multi-bit ADC operation.  
         [0035]     The channel state information for each channel “i” of the voltage regulator  200  is represented by the threshold crossover times output by the corresponding network  250 ( i ) of threshold detectors. With knowledge of the times at which the threshold crossings occur, the scheduling logic  300  adjusts the timing and widths of the PWMn pulses in order to optimize the output of the switching regulator system  200 .  
         [0036]     Turning to  FIG. 7 , one form of the scheduling logic component  300 ( i ) for each channel “i” comprises Boolean logic  305 ( i ) configured to output the PWMn pulses, each at a different frequency, and scheduled so as to avoid overlap in time. In addition, the Boolean logic  305 ( i ) may optionally implement the random or pseudo-random number generation to perform the slight adjustment to PWM pulse positions as described above in conjunction with  FIGS. 3 and 4 .  
         [0037]      FIG. 8  illustrates another form of the schedule logic  300 . In this form, the scheduling logic  300  comprises an AWS subsystem  500  and a channel state processing logic circuit  600 . The AWS subsystem  500  comprises a ring oscillator or delay line  510  tapped by waveform generation logic block  520 . The waveform generation logic block  520  comprises an algebra module  522 , and a switching module  524  and an output module  526 . The algebra module  522  is connected to the switching module  524  and output module  526 .  
         [0038]     The ring oscillator or delay line circuit  510  comprises a plurality of delay elements and a plurality of taps disposed between the delay elements, each tap providing a tap transition signal. The algebra module  522  has an algebra data input port, a clock input port that is coupled to a reference clock signal and an algebra data output port. The algebra module  522  generates a first signal at the algebra data output port in response to a second signal received at the algebra data input port, the first signal indicative of a first rising edge of an arbitrary waveform. The switching module  524  has a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the plurality of taps of the delay line circuit  510 , and a switch output port. The switching module  524  provides at the switch output port a selected transition signal corresponding to the tap transition signal provided from one of the plurality of taps selected in response to the first signal received at the switch input port. The output module  526  has a transition signal input port in electrical communication with the switch output port, a window input port in electrical communication with the algebra data output port and a waveform output port in electrical communication with the clock input port of the algebra module. The output module  526  generates the arbitrary waveform at the waveform output port in response to the selected transition signal received at the transition signal input port of the output module and the first signal received at the window input port. Further details for implementation and operation of the blocks of the AWS  500  can be found in the aforementioned commonly assigned patents.  
         [0039]     The channel state information from the threshold detector network  250 ( i ) is supplied to the channel state processing logic circuit  600 . The channel state processing logic circuit  600  converts the threshold crossing time information for each channel of the switching voltage regulator to a control signal that is coupled to the output module  526  to in the waveform generation logic block  520 . The output module  526  responds to the control signal to adjust a duration (width) or timing of its output signal, which corresponds to PWM(i) for channel “i”. In addition, the scheduling logic components for all of the channels are connected to each other so that the channel state processing logic  600  in each scheduling logic component knows the timing considerations of the other channels. Thus, in each scheduling logic component  300 ( i ), the AWS  500  can precisely produce the driver circuit control pulse signal for that channel at a different frequency from the other channels and such that no two driver control signal pulses for different channels overlap in time. Furthermore, if the scheduling logic component  300 ( i ) is to generate two driver circuit control signals, one for the high-side transistor and one for the low-side transistor, the waveform generation logic block  520  would include another switching module and associated output module. One switching module/output module pair is for the driver control signal for the high-side transistor and the other switching module/output module pair is for the driver control signal for the low-side transistor. In addition, the channel state processing logic  600  would generate two control signals, one that is coupled to the output module for the high-side transistor driver control signal and one that is coupled to the output module for the low-side transistor driver control signal.  
         [0040]      FIG. 9  illustrates an example of the driver control pulse signals PWM 0  to PWM 7  for an eight-phase voltage regulator system using the techniques described above in connection with  FIGS. 5-8 . In this example, the frequency of each of the driver control pulse train signals is different and moreover the widths. Moreover, as indicated in the figure for channel  0  and channel  1 , the width of the pulses are adjusted, when and as necessary, to avoid time overlap. In the case where the driver circuits  40 ( i ) are capable of separately controlling their respective high-side and low-side transistors, there would be two such waveforms for driver circuit control signals, one for the high-side transistor and one for the low-side transistor, for each channel.  
         [0041]     The above description is intended by way of example only.