Abstract:
TASI apparatus suitable for use with telephone networks employing interregister multifrequency signalling comprising transmission apparatus at a first end of a transmission trunk link having a first plurality of communication channels, the transmission apparatus including means for detecting signals on a second plurality of telephone communication lines on which signals are present to an available one of the first plurality of communication channels and means for applying a delay to the detected signals, receiving apparatus at a second end of the transmission link including means for assigning each of the first plurality of communication channels carrying signals to a corresponding one of the second plurality of telephone communication lines in accordance with assignment information received from the transmission apparatus, means for communicating messages including assignment information between the transmission apparatus and the receiving apparatus, means for sensing the onset of interregister multifrequency signalling on the second plurality of telephone communication lines, and means for disabling the means for applying a delay to the detected signals in response to the sensed onset of interregister multifrequency signalling.

Description:
FIELD OF THE INVENTION 
     The present invention relates to telecommunications apparatus generally and more particularly to time assignment speech interpolation apparatus 
     BACKGROUND OF THE INVENTION 
     Time Assignment Speech interpolation (TASI) communication systems have been known for approximately twenty years. Their function, stated in general terms, is to exploit the fact that during a normal telephone conversation, information is being transmitted only about 35% of the time. TASI communication systems serve to connect a speaker to a transmission line only during those portions of a conversation when speech is actually present. During the other portions of the conversation, the transmission line is connected to another speaker, currently speaking in another conversation. By using time assignment speech interpolation, a given number of transmission lines, such as 24, can usually carry about 48 simultaneous conversations. 
     A particularly effective TASI system which has met with commercial success is currently manufactured by Electronics Corporation of Israel Ltd. and is described in Published European Patent Application No. 0025465 of Mar. 25, 1981 corresponding to application No. 79301917.5. 
     All known TASI systems, including that manufactured by Electronics Corporation of Israel Ltd. cannot presently be used in telephone networks having fully compelled interregister multifrequency signalling. 
     Interregister multi frequency signalling is known as System R-2 line signalling in the CCITT standards and Socotel in the French system. The R 2 system operation is described in detail in Volume VI.3 of the CCITT standards, Orange Book, Section 2, Recommendations Q 411-Q 416, the contents of which are incorporated herein by reference as background source material. Briefly described, the R 2 system involves an in-band multifrequency code with forward and backward fully compelled signalling, for call set up control signals, i.e. interregister signalling. Line signalling is provided by out of band signalling such as E and M wire signalling and only indicates the change of states from one signalling state to another. For example, the transition from the &#34;idle&#34; state to the &#34;seized&#34; state is indicated by an out of band transition from TONE-OFF on the outgoing line and an unchanged TONE-ON status on the incoming line. 
     A number of functions of time assignment speech interpolation systems, such as the ECI system, are incompatible with interregister multifrequency signalling. The use of an Echo Suppressor during signalling has been found by applicants to at least partially block the interregister signalling due to the simultaneous presence of signals in both directions. Applicants have also been found that the provision of a 6 db attenuation as part of the echo suppression in the receiver interferes with signalling receipt in the R-2 signalling protocol. 
     Applicants have also found that the delay employed in TASI apparatus acts to extend the time-out period assigned to fully compelled interregister multifrequency signalling in the R-2 protocol. 
     SUMMARY OF THE INVENTION 
     The present invention seeks to provide apparatus for use with a TASI system for enabling it to function in a telephone network employing fully compelled interregister multifrequency signalling such as R-2. 
     There is thus provided in accordance with an embodiment of the present invention TASI apparatus suitable for use with telephone networks employing interregister multifrequency signalling comprising: 
     transmission apparatus at a first end of a transmission trunk link having a first plurality of communication channels, the transmission apparatus including apparatus for detecting signals on a second plurality of telephone communication lines and for assigning each telephone communication line on whch signals are present to an available one of the first plurality of communication channels and apparatus for applying a delay to the detected signals; 
     receiving apparatus at a second end of the transmission link including apparatus for assigning each of the first plurality of communication channels carrying signals to a corresponding one of the second plurality of telephone communication lines in accordance with assignment information received from the transmission apparatus, echo suppression apparatus, attenuation apparatus and apparatus for applying a delay to the received signals; 
     apparatus for communicating messages including assignment information between the transmission apparatus and the receiving apparatus; 
     apparatus for sensing the onset of interregister multifrequency signalling on the second plurality of telephone communication lines; and 
     apparatus for disabling at least one of following in response to the sensed onset of interregister multifrequency signalling: the apparatus for applying a delay to the detected signals, the echo suppression apparatus, the attenuation apparatus and the apparatus for applying a delay to the received signals. 
     Further in accordance with an embodiment of the present invention, the apparatus for disabling is operative in response to the sensed onset of interregister multifrequency signalling to disable all of the following apparatus for the duration of the multifrequency signalling: apparatus for applying a delay to the detected signals, the echo suppression apparatus, the attenuation apparatus and the apparatus for applying a delay to the received signals. 
     Additionally in accordance with an embodiment of the present invention there is provided for use with a TASI system including transmission, receiving and communicating apparatus as described hereinabove, apparatus for enabling TASI operation in a network employing interregister multifrequency signalling comprising: 
     apparatus for communicating messages including assignment information between the transmission apparatus and the receiving apparatus; 
     apparatus for sensing the onset of interregister multifrequency signalling on the second plurality of telephone communication lines; and 
     apparatus for disabling at least one or all of the following apparati in response to the sensed onset of interregister multifrequency signalling: apparatus for applying a delay to the detected signals, echo suppression apparatus, attenuation apparatus and apparatus for applying a delay to the received signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more fully understood and appreciated from the following detailed description taken in conjunction with the drawings in which: 
     FIGS. 1a and 1b are block diagram illustrations of time assignment speech interpolation apparatus constructed and operative in accordance with a preferred embodiment of the present invention; 
     FIGS. 2a and 2b are block diagram illustrations of transmit speech flow circuitry forming part of the apparatus of FIGS. 1a and 1b; 
     FIGS. 3a and 3b are block diagram illustrations of receive speech flow circuitry forming part of the circuitry of FIGS. 1a and 1b; 
     FIGS. 4a and 4b are a timing diagram illustrating timing for the receive speech flow circuitry of FIGS. 3a and 3b; 
     FIGS. 5A through 5K are schematic illustration of echo suppression circuitry forming part of the apparatus of FIGS. 1a and 1b; 
     FIGS. 6A through 6M are schematic illustration of transmit speech flow circuitry illustrated in block diagram form in FIGS. 2a and 2b; and 
     FIGS. 7A through 7H are schematic illustration of receive speech flow circuitry illustrated in block diagram form in 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference is now made to FIG. 1 which illustrates TASI circuitry suitable for use in telephone networks having fully compelled interregister multifrequency signalling constructed and operative in accordance with an embodiment of the present invention. The apparatus of FIG. 1 comprises an input circuit 10, which may be similar to the circuitry illustrated in FIG. 2A of the above cited published European Patent Application. Circuit 10 receives inputs from telephone communications lines which are typically dedicated to outgoing calls. The output of circuit 10 is supplied to transmit speech flow circuitry 12, which receives an input from an CPU 14 and provides an output to a transmit audio switch 16. Circuitry 12 will be described in detail hereinafter in connection with FIG. 2. Audio switch 16 receives an input from a message transmit circuit 18, which also receives an input from CPU 14. The output of audio switch 16 is supplied via an output circuit 20 to an available one of the communication channels in accordance with general TASI principles. 
     The output of input circuit 10 is also supplied to speech detector circuitry 17 which receives an input from an echo suppressor 19. Both the echo suppressor and the speech detector interface with the CPU 14. 
     CPU 14 also receives an input from a signal detector 21, which in turn receives an input from the M signalling wire via an input circuit 23. Activity on the M signalling wire indicates initiation of a call. 
     At a remote location, the communication channels are coupled to an input circuit 22, which outputs to a receive speech flow circuit 24 which receives an input from a CPU 15. Receive speech flow circuit 24 will be described in detail hereinafter in connection with FIG. 3. The output of circuit 24 is supplied to a message receiver circuit 26, which outputs to the CPU 15. The output of circuit 24 is also supplied to a receive audio switch 28, which outputs to a -6b attenuation circuit 30. The attenuated signal is supplied via an output circuit 32 to remote telephone communication lines which are typically dedicated to incoming calls. 
     CPU 15 also provides an enable output to attenuation circuit 30. Additionally CPU 15 provides an output to a receive signalling switch 34 which outputs to a signalling output circuit 36. The output of circuit 36 is coupled to the E signalling wire. 
     It is appreciated that the circuitry shown in FIG. 1 on opposite mutually remote sides of a communication trunk containing a plurality of communication channels is identical and symmetric. For that reason, the receive circuitry on the outgoing side of the circuitry will not be described, since it is identical to the receive circuitry described in connection with the incoming side. Correspondingly, the transmit circuitry on the incoming side will not be described since it is identical to the transmit circuitry described in connection with the outgoing side. 
     It is appreciated that although the detailed construction of the various circuits illustrated in block form are not essential for an understanding and full disclosure of the present invention, these circuits are all described in detail and illustrated fully in the aforesaid published European Patent Application, the disclosure of which is incorporated herein by reference as non-essential disclosure. 
     It is noted that although the present invention is being described herein with particular reference to the ECI TASI apparatus as described in the aforesaid published European Patent Application, the invention is not limited to use with TASI apparatus of this design and construction. The generality of the invention is sufficient to enable it to be used with any known type of TASI apparatus, provided that suitable variations are made in the circuitry described herein to adapt it to the particular application. These adaptations are believed to be well within the scope of a person ordinarily skilled in the art in view of the disclosure contained herein and of the published materials available to such a person. 
     In this connection it is noted that other types of TASI may not incorporate a receive delay and may employ echo suppression apparatus which is external to the TASI apparatus. 
     Reference is now made to FIG. 2 which illustrates in detailed block diagram illustration transmit speech flow circuitry 12. The circuitry of FIG. 2 is substantially identical in structure and function to that illustrated in FIG. 10 of the aforesaid European Patent Application and described therein, with the exception of the following portions which will now be described in detail. 
     A 2/1 multiplexer 40 receives a 6 bit CAT 0-CAT 5 input which is the output of a sequence counter. and also receives from the CPU data bus a DB 0=DB 5 address input. Multiplexer 40 is operative to provide a six-bit output to a 48×1 RAM 42 at an A0-A5 input. RAM also receives a delay enable signal from the CPU data bus. RAM 42 provides a transmit delay disable output to the enable input of a 2/1 multiplexer 44. Multiplexer 44 has two nine-bit inputs, one which is permenently set at zero for all bits and the other one which is coupled to the output of a 384 counter 46. 
     RAM 42 is operative to store a delay disable signal from the CPU bus for one or more specific telephone communication lines indicated by an address furnished by multiplexer 40. Each time that the transmit delay memory (125) of the transmit speech flow circuitry is sequenced to the channel or channels for which delay disable is indicated by the presence of a delay disable signal at multiplexer 44, the multiplexer reads into the delay memory all zeros such that the contents of the signal which are read into the delay memory are read into a location in the delay memory which is next immediately read out to latch (131), without being sequenced through 384 stages which produces the delay. It may thus be appreciated that when a delay disable signal is provided by the CPU, signals arriving on a communication line or lines for which delay disable is indicated are read out from the delay memory immediately after being written therein and without the predetermined delay that would otherwise be provided in the absence of such a delay disable signal. 
     Reference is now made to FIG. 3 which illustrates receive speech flow circuitry 24. The circuitry of FIG. 3 is substantially identical in structure and function to that illustrated in FIG. 12 of the aforesaid published European Patent Application and described therein, with the exception of the following portions which will now be described in detail. 
     Logic circuitry 50 receives the CMR 6 and BLRX timing signals respectively from a latch 99 and blank logic circuitry 97 forming part of receive control memory circuitry shown in FIG. 29b of the aforesaid Published European Patent Application 0025465 and provides an inverse receive delay disable signal to a timing selector 52. Timing selector 52 receives two timing signals, t A  which is the normal timing signal for operation of a receive delay memory output latch (171) and t G  which is a special timing signal employed in the presence of interregister multifrequency signalling. Timing selector 52 is operative in response to the signal received from logic circuitry 50 to determine whether to operate latch (171) on the basis of t A  or t G . The output timing signal, in either case, is applied as a latch clock signal to latch (171). Logic circuitry 50 is operative to cause timing selector 52 to apply the t G  timing signal to latch (171) when interregister multifrequency signalling has been indicated for a given channel at a given time. In such a case, the t G  timing is operative to provide an extra clock pulse to latch (171) immediately following read in of information from that channel into the delay memory (157). In such a way, the information from that channel is passed to the latch with substantially no delay. 
     The operation of the t G  timing signal may be appreciated from a consideration of FIG. 4 which includes a delay memory latch clock signal. Normally the clock pulse occurs at time t A  t 8 , but when delay disable is indicated, it is shifted to t G  t 8  so as to follow the delay memory write enable signal which occurs at t C . 
     Reference is now made to FIGS. 5-7 which are schematic illustrations of various parts of the circuitry illustrating the detailed exemplary implementation of the invention in the ECI circuitry which is disclosed and claimed in the aforesaid published European Patent Application. 
     FIG. 5 is a schematic illustration of echo suppression circuitry forming part of the apparatus of FIGS. 1a and 1b. FIG. 6 illustrates the apparatus shown in FIGS. 2a and 2b in schematic form, while FIG. 7 is a schematic illustration of part of the circuitry shown in block diagram form in FIGS. 3a and 3b. 
     A computer listing for the operation of the CPU in the presence of interregister multifrequency signalling is provided hereinbelow: ##SPC1## 
     The operation of the apparatus of the invention whose structure has been described hereinabove will now be described. 
     On the outgoing side, signal detector circuitry 21 is operative to detect a change in the status of the M signalling wire on an outgoing communication line from idle to seized. 
     The status of the E wire on the outgoing side is then checked by the receive signalling switch 34 in order to indicate the status of the M wire on the incoming side. If the M wire on the incoming side remains in the idle state, outgoing the message transmit circuitry 18 transmits an assignment message to the incoming circuitry message receiver 26. The outgoing CPU 14 then decouples the communication line on which the status change from idle to seized from speech detector control and does the same with a selected communication channel. The incoming message transmit circuit 18 transmits an acknowledge message to the outgoing side. 
     The outgoing side receives the acknowledge message at message receiver 26 and in response to CPU command, transmits a delay disable message to the incoming side. CPU 14 at the outgoing side is then operative to disable the transmit delay in circuitry 12, to disable the operation of echo suppressor 19 and to disable the 6 db attenuation circuitry 30. 
     Upon receipt of the delay disable message, the incoming side is operative to disable its receive delay in circuitry 24 and to commence a timing period of between four and eight seconds during which interregister multifrequency signalling takes place. The incoming side then sends an assignment message via its message transmit circuitry 18. The incoming CPU 15 then disables the corresponding communication line and communication channel from speech detector control. 
     Upon receiving the assignment message, the outgoing side sends an acknowledge message via message transmit circuitry 14. The incoming side is operative upon receive of the acknowledge message to send a delay disable message to the outgoing side and then to disable on the incoming side the transmit delay in circuitry 12, the echo suppressor 19 and the 6 db attenuation circuitry. 
     The outgoing side is operative in response to receipt of the delay disable message to disable the receive delay in the receive speech flow circuitry 24 on the outgoing side. The outgoing side CPU 14 then commences a timing period of between four and eight seconds during which interregister multifrequency signalling takes place. Following the commencement of this period, the CPU sends via the message transmit circuitry 18 a communication line idle signalling status message (LSD OFF) to the incoming side. 
     At the end of the timing period at both the incoming and outgoing sides, the transmit and receive delays, the echo suppressor and the -6 db attenuation on both sides are all enabled to permit time assignment speech interpolation of the speech which follows established of a connection. 
     It will be appreciated by persons skilled in the art that the invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined only by the claims which follow: