Abstract:
A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. An apparatus is provided for measuring a peak value of an analog voltage. The apparatus comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that detects a voltage level of the received input voltage, and a digital memory that is connected for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention generally relates to voltage peak measurement apparatus and methods and in particular to such voltage peak measurement techniques that may be used in units or subunits of communication systems such as WLAN (Wireless Local Area Network) systems.  
           [0003]    2. Description of the Related Art  
           [0004]    A wireless local area network is a flexible data communication system implemented as an extension to, or as an alternative for, a wired LAN. Using radio frequency (RF) or infrared technology, WLAN systems transmit and receive data over the air, minimizing the need for wired connections. Thus, WLAN systems combine data connectivity with user mobility. Most WLAN systems use spread spectrum technology, a wide-band radio frequency technique developed for use in reliable and secure communication systems. The spread spectrum technology is designed to trade-off bandwidth efficiency for reliability, integrity and security.  
           [0005]    One element in wireless communication systems are RF transceivers. Today, RF transceivers are often provided as integrated circuits and the realization of RF transceivers in highly integrated circuits may be a requirement for applications such as those in wireless local area networks and in the cellular telephony to achieve a very high dynamic range and a very high frequency on the one hand and a low power consumption and a reduction in the passive components on the other hand.  
           [0006]    [0006]FIG. 1 shows a typical configuration of a conventional voltage peak measurement apparatus that detects peak values of an analog signal (V in ) and outputs digital results corresponding to the detected peak values. The peak measurement configuration of FIG. 1 comprises an analog to digital converter  100 , a reference voltage source  130 , a capacitor  160 , a diode  190  and a reset switch  150  connected to discharge the capacitor  160 .  
           [0007]    The analog to digital converter  100  is a known device that comprises different input terminals  120 ,  140 . A first input terminal is a peak voltage input terminal  140  that is connected to receive the peak voltage (V peak ) of the analog signal (V in ) applied to the input terminals  170 ,  180  of the peak measurement configuration.  
           [0008]    A second input terminal is a reference voltage input terminal  120 . The reference voltage input terminal  120  is connected to a reference voltage source  130  to provide a reference voltage (V ref ). As shown in FIG. 1, the other side of the reference voltage source  130  is connected to a common ground line that is further connected to the input terminal  180 .  
           [0009]    A further input terminal of the conventional analog to digital converter  100  is a clock terminal  110  to receive an external clock signal that may be used to synchronize internal devices of the analog to digital converter  100 .  
           [0010]    As mentioned above, the input terminal  170  of the peak measurement configuration is connected to the peak voltage input terminal  140  of the analog to digital converter  100 . This connection is referred to as an input line hereafter. Between the input line and the common ground line, there are the capacitor  160  and the reset switch  150  connected in parallel thereto.  
           [0011]    The terminal  140  receives a rectified analog voltage signal, and also the capacitor  160  receives the applied rectified analog voltage. The capacitor  160  is charged and holds a voltage corresponding to the currently applied analog voltage. This held voltage is a peak voltage of the applied analog voltage and the analog to digital converter  100  converts the held peak voltage into digital data.  
           [0012]    The peak measurement configuration of FIG. 1 has several disadvantages. In particular, the usage of the capacitor  160  and the reset switch  150  for discharging the capacitor.  160  is disadvantageous. Referring to the signal graphs of FIG. 2, the function of the conventional peak measurement configuration of FIG. 1 will be explained in more detail and the disadvantages will be pointed out. FIG. 2 illustrates an example of an input signal received at the input terminals  170 ,  180  of the peak measurement configuration of FIG. 1. Further, a reset signal is illustrated that indicates when the reset switch  150  of the peak measurement configuration of FIG. 1 discharges the capacitor  160 .  
           [0013]    After the reset switch  150  is turned off, the discharged capacitor  160  is then ready to store a voltage peak of the applied input signal. The signal graphs of FIG. 2 show that the falling edge  230  of the reset signal initiates the charging of the capacitor  160 . The capacitor  160  holds the first voltage peak  240  of the input signal as long as a further, higher voltage peak  250 ,  260  is applied, or until the capacitor  160  is discharged by the reset switch  150 . Thus, the capacitor voltage represents the maximum of the input voltage (V in ) since the last reset, thus the input voltage peak.  
           [0014]    When the capacitor  160  holds a voltage level, the connected analog to digital converter  100  generates a digital output corresponding to the held voltage level.  
           [0015]    It is well known that each capacitor discharges due to leak currents. This process of discharging effects an error  220  that decreases the currently stored peak voltage level  260  over time. The decreased peak voltage level is delivered to the analog to digital converter  100 , and the analog to digital converter  100  generates output data that does not represent the original peak voltage level of the analog voltage applied to the peak measurement configuration of FIG. 1 but the decreased level.  
           [0016]    Assuming the capacitor of FIG. 1 receives a rectified voltage signal that is generated by an input circuit that comprises a diode and a current source for generating a bias current for keeping the diode at a given operating point in forward direction, the current source will effect a further decrease of the stored voltage level of the capacitor  160  in addition to the above-described discharging effect because the current of the current source may speed up the discharging of the capacitor  160 .  
           [0017]    A further disadvantage of the conventional configuration of FIG. 1 is the fact that discharging the capacitor  160  introduces a time dependent error. Therefore, it is necessary to balance between measurement time, discharge of the capacitor  160  and, in case of a rectified signal, the bias current of the diode for rectifying, to minimize operating point dependent errors and to provide the needed signal bandwidth.  
           [0018]    The above-described effects are difficult to balance and decrease the available signal bandwidth. Further, the disadvantages lead to a decreased operating speed of the peak measurement configuration and result in less precision and less accuracy.  
         SUMMARY OF THE INVENTION  
         [0019]    An improved voltage peak measurement apparatus, an integrated circuit chip, a WLAN receiver and an operation method are provided for performing a voltage peak measurement that may allow for high operating speed, high precision and high accuracy.  
           [0020]    In one embodiment, there is provided a voltage peak measurement apparatus for measuring a peak value of an analog voltage. The apparatus comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that is adapted to detect a voltage level of the received input voltage, and a digital memory that is connected to the voltage level detection unit for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. The digital memory is capable of outputting a digital code that corresponds to the stored voltage level.  
           [0021]    In a further embodiment, an integrated circuit chip has circuitry for measuring a peak value of an analog voltage. The integrated circuit chip comprises an analog to digital converter circuit that is connected to receive an input voltage. The analog to digital converter circuit comprises a voltage level detection circuit that is adapted to detect a voltage level of the received input voltage, and a digital memory circuit that is connected to the voltage level detection circuit for receiving and storing the detected voltage level. The digital memory circuit is adapted for updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. The digital memory circuit is capable of outputting a digital code that corresponds to the stored voltage level.  
           [0022]    In another embodiment, there is provided a WLAN receiver that has a voltage peak measurement device for measuring a peak value of an analog voltage. The device comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that is adapted to detect a voltage level of the received input voltage, and a digital memory that is connected to the voltage level detection unit for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updating the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. The digital memory is capable of outputting a digital code that corresponds to the stored voltage level.  
           [0023]    In yet another embodiment, there is provided a method of measuring a peak value of an analog voltage. The method comprises receiving an input voltage in an analog to digital converter, detecting a voltage level of the received input voltage, storing the detected voltage level in a digital memory, and outputting a digital code that corresponds to the stored voltage level. The stored voltage level is updated by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or the stored voltage level is updated by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    The accompanying drawings are incorporated into and form a part of the specification for the purpose of explaining the principles of the invention. The drawings are not to be construed as limiting the invention to only the illustrated and described examples of how the invention can be made and used. Further features and advantages will become apparent from the following, and more particular description of the invention as illustrated in the accompanying drawings, wherein:  
         [0025]    [0025]FIG. 1 shows a typical configuration for measuring voltage peak values;  
         [0026]    [0026]FIG. 2 shows an example of input signals applied to the configuration of FIG. 1;  
         [0027]    [0027]FIG. 3 is a block diagram of a voltage peak measurement apparatus according to an embodiment;  
         [0028]    [0028]FIG. 4 is a block diagram of a voltage peak measurement apparatus according to another embodiment that comprises an input circuit;  
         [0029]    [0029]FIG. 5 shows an example of input signals applied to the voltage peak measurement apparatus of FIG. 4;  
         [0030]    [0030]FIG. 6 is a block diagram similar to that of FIG. 4 with a different input circuit according to a further embodiment;  
         [0031]    [0031]FIG. 7 shows an example of input signals applied to the voltage peak measurement apparatus of FIG. 6; and  
         [0032]    [0032]FIG. 8 is a flow chart illustrating the process of measuring voltage peaks using the apparatus according to one of the embodiments. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0033]    The illustrative embodiments of the present invention will be described with reference to the figure drawings, wherein like elements and structures are indicated with like reference numbers.  
         [0034]    Referring now to the drawings, in particular to FIG. 3, a block diagram of a voltage peak measurement apparatus is depicted for measuring a peak value of an analog voltage (V in ). According to one embodiment, the apparatus comprises an analog to digital converter  300  and an input circuit that is connected to the analog to digital converter to provide the analog voltage (V in ) and a reference voltage (V ref ).  
         [0035]    The analog to digital converter shown in FIG. 3 comprises a voltage level detection unit  305  that is connected to a first input terminal  330  to receive an input voltage. The voltage level detection unit  305  is adapted to detect a voltage level of the received input voltage by comparing the input voltage with predefined reference voltages. As shown in the figure, a second input terminal  335  of the analog to digital converter  300  is connected to a reference voltage source  340  and is further connected to a reference divider  320  for generating the predefined reference voltages based on the input reference voltage (V ref ). The reference divider  320  is arranged to provide the generated reference voltages to the voltage level detection unit  305 .  
         [0036]    The voltage level detection unit  305  in the current embodiment of FIG. 3 comprises a plurality of threshold switches to detect a voltage level of the received input voltage (V in ), wherein the above-mentioned generated reference voltages define the threshold voltages for the threshold switches. The threshold switches detect a voltage level when the received input voltage (V in ) exceeds respective thresholds, and the connected digital memory  310  holds this status. Once the digital memory stores the data indicating that an individual threshold was exceeded, this data is held even if the input voltage drops below the respective threshold.  
         [0037]    The digital memory  310  is adapted for storing a currently detected voltage level and for updating a stored voltage level with the currently detected voltage level. The memory updates the stored voltage level by a currently detected voltage level only if the currently detected voltage level is higher than the stored voltage level, or updates the stored voltage level by a currently detected voltage level only if the currently detected voltage level is lower than the stored voltage level.  
         [0038]    In the present embodiment, the digital memory  310  comprises a plurality of latch flip flop units, wherein each of the latch flip flop units is connected to a threshold switch of the voltage level detection unit  305  to receive a voltage level related bit. This voltage level related bit comprises the information whether the applied input voltage of the analog to digital converter  300  has exceeded the respective threshold, or not.  
         [0039]    The digital memory  310 , and therefore the latch flip flop units, are resettable by a reset signal received at a reset terminal  325 . The latch flip flop units of the digital memory  310  store the above-mentioned voltage level related bits by switching the related latch flip flop units.  
         [0040]    The stored bits in the digital memory form a digital code that represents the currently detected voltage level. This digital code is transferred to a connected decoder unit  315 , and the decoder unit  315  generates digital output data of the voltage peak measurement apparatus.  
         [0041]    In the following, the function of the above-described analog to digital converter  300  will be described in more detail with reference to FIG. 4. It can be seen that the embodiment of FIG. 4 differs from that of FIG. 3 in the input circuit that is connected to the analog to digital converter  300 . The terminal  420  receives an analog voltage, and a diode  410  is provided to rectify the received analog voltage so that negative voltages are cut off. This rectified analog voltage is delivered to the analog to digital converter  300 .  
         [0042]    The input circuit further comprises a current source  400  that is connected to the diode  410  and a ground line of the input circuit. The current source  400  is adapted to generate a forward bias current for keeping the diode  410  at a defined operating point.  
         [0043]    The reference voltage source  340  is connected to the ground line of the input circuit and further to the reference voltage input terminal  335  of the analog to digital converter  300  to deliver a reference voltage to the divider unit  320 . The divider unit  320  is provided for dividing the input reference voltage of the reference voltage source  340  into predefined voltages to provide threshold voltages for the threshold switches in the voltage level detection unit  305 .  
         [0044]    The function of the voltage peak measurement apparatus that uses a rectifier as shown in FIG. 4 will be explained in the following with reference to the illustrated signal graphs of FIG. 5.  
         [0045]    One curve shown in the upper most signal graph is an example of the analog voltage  500  (V in ) that is applied to the input circuit of FIG. 4. Another curve illustrates the rectified voltage  530  V rect ) that is input to the analog to digital converter  300 . Further, a peak voltage curve  510  (V peak ) is shown that indicates the value of the digital output signal of the digital memory  310 . Moreover, a reset signal is depicted as well as the digital representation  540  of the output signal of the digital memory  310  and the data output of the voltage peak measurement apparatus.  
         [0046]    The falling edge  550  of the reset signal terminates the reset state of the digital memory  310  of the analog to digital converter  300 . The voltage level detection unit  305  starts detecting for a first voltage peak level  560  of the rectified analog input signal (V rect ). The first voltage peak level  560  is kept by the digital memory  310  as long as a higher voltage level  570  is detected. Once the level has been updated to the voltage level  570 , this is kept as long as a further, even higher voltage level  520  is detected. This process continues as long as no higher voltage level is detected. The mentioned process continues until a rising edge  580  of the reset signal  500  is received. In another embodiment, the process is independent of the rising edge.  
         [0047]    The digital memory  310  receives the currently detected voltage as a digital code. This digital code is kept by the digital memory if the voltage is higher than the previously stored voltage, and output to the decoder unit  315 . The digital code may be output simultaneously with each update.  
         [0048]    The decoder  315  generates digital data from the received digital code by decoding the code. In an embodiment, the rising edge  580  of the reset signal initiates an outputting of the generated digital data as a digital output signal of the peak value measurement apparatus.  
         [0049]    A further embodiment of the voltage peak measurement apparatus is depicted in FIG. 6. The apparatus of FIG. 6 differs from the above-described embodiment of FIG. 4 in the construction of the input circuit that provides the input voltage to the analog to digital converter  300  and in the realization of the voltage level detection unit  305 .  
         [0050]    The input circuit of the present embodiment of FIG. 6 is an absolute value generator which receives an analog voltage (V in ) at the input terminals  610  of the voltage peak measurement apparatus. The absolute value generator comprises a diode bridge circuit  600  that is connected to an absolute value input terminal  330  of the analog to digital converter  300 .  
         [0051]    The devices used in the voltage level detection unit  305  of the present embodiment may differ from the above embodiments of FIG. 4. The construction of the voltage level detection unit  305  will be discussed in more detail in the following.  
         [0052]    The absolute value input terminal  330  of the analog to digital converter  300  is connected to the voltage level detection unit  305  that comprises a plurality of comparator devices, wherein each of the comparator devices is connected to receive the absolute value input signal (V abs ). Each of the comparator units is further connected to the divider unit  320  to receive an individual divider voltage.  
         [0053]    The output terminals of the comparator units are connected to the digital memory  310  for delivering the comparator results. As described above, the digital memory  310  comprises a reset terminal for receiving a reset signal and the digital memory  310  is connected to the decoder unit  315  for delivering the digital code related to the detected voltage peak level. In another embodiment, the decoder unit  315  generates digital output data to be output when a rising edge is received at the reset terminal  325 .  
         [0054]    It will be referred in the following to the signal graphs of FIG. 7 in order to describe the embodiment of FIG. 6 in more detail. The signals of FIG. 7 differ from those of FIG. 5 mainly in that absolute values  730  (V abs ) are input to the analog to digital converter  300  rather than rectified voltages. That is, the analog to digital converter  300  receives only positive voltages.  
         [0055]    As mentioned above, the voltage level detection unit  305  in the embodiment of FIG. 6 comprises a plurality of comparator units for detecting a voltage peak level of the received input voltage(V abs ), wherein the received input voltage will be compared with the above-mentioned reference voltages that are predefined by the divider unit  320 .  
         [0056]    Each of the comparator units outputs a comparator result that corresponds to one of the predefined reference voltages that are provided by the divider unit  320  and that each represent a bit of the currently detected voltage level. The comparator results are transferred to the digital memory  310  that holds the comparison results as a digital code if the results indicate that a previously stored peak value has been exceeded.  
         [0057]    Simultaneously, the digital memory  310  transmits the corresponding digital code to the decoder unit  315 . This is shown in FIG. 7 where the memory output changes whenever the voltage peak is updated. That is, each new voltage level that is higher than the previously detected voltage level causes a digital output signal to the decoder unit  315 . In the present embodiment, the decoder unit  315  generates then the digital output of the voltage peak measurement apparatus.  
         [0058]    In another embodiment, the analog to digital converter detects for a higher voltage level until the rising edge  780  of the reset signal is received. If the rising edge  780  of the reset signal is received, the decoder unit  315  generates the digital output of the voltage peak measurement apparatus.  
         [0059]    Turning now to FIG. 8, a flow chart of the process of measuring voltage peaks according to an embodiment is depicted. Because of the fact that the above described voltage peak measurement apparatus start measuring the voltage peaks with a falling edge of the reset signal, the reset signal is detected in step  800 .  
         [0060]    If the reset signal has a high level, the digital memory is reset in step  810 . If the reset signal has a falling edge, the voltage peak measurement apparatus is prepared for detecting voltage peaks and receives a signal in step  820 . The voltage level of the received signal is than detected in step  830 . The currently detected voltage level is now compared with a previously stored voltage level in step  840 . If the currently detected voltage level is greater than the previously stored voltage level, the new voltage level is stored in step  850 . That is, the previously stored voltage level is updated by the currently detected voltage level in step  850 . The stored or updated voltage level is than output as a digital code in step  860 . After outputting the digital code in step  860 , the process of measuring the voltage peaks returns to continue detecting.  
         [0061]    However, if the detected voltage level is lower than the previously stored voltage level, the process of measuring the voltage peaks will reiterate starting from step  840 .  
         [0062]    As apparent from the foregoing description, all of the embodiments as described may advantageously provide high accuracy, high precision and increased operating speed, because the usage of the capacitor  160  is avoided. Moreover, this provides the advantage that no time dependent error is introduced that caused in the prior art systems by charging and discharging the capacitor  160 . This facilitates the timing processes since no time delay exist.  
         [0063]    Further, the embodiment may even be used in systems where data acquisition is driven by an asynchronous timing.  
         [0064]    The provided interconnection of the absolute value generator and the analog to digital converter  300  described in the embodiment above may offer additional advantages.  
         [0065]    Storing the voltage peaks by a built-in digital memory  310 , and in particular by means of latch flip flop units, may further provide the advantage that the stored voltage level is kept absolutely stable independently of leak currents or other disturbances. This makes it possible to keep acquisition errors in a reasonable range.  
         [0066]    The arrangements may further have the advantage to provide a higher bandwidth because no charging and discharging of capacitors is required. Moreover, data acquisition may be finished immediately after the respective measurement period. Any power dissipation is reduced as far as possible.  
         [0067]    Moreover the manufacturing may be simplified because the arrangements use a decreased number of component parts. Therefore, the above-described embodiments may, in effect, reduce the production costs.  
         [0068]    While the invention has been described with respect to the physical embodiments constructed in accordance therewith, it will be apparent to those skilled in the art that various modifications, variations and improvements of the present invention may be made in the light of the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. For instance, while the above embodiments have been described as detecting positive voltage peaks, other embodiments may be provided for detecting negative peaks in much the same way as discussed above.  
         [0069]    In addition, those areas in which it is believed that those of ordinary skill in the art are familiar, have not been described herein in order not to unnecessarily obscure the invention described herein. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrative embodiments, but only by the scope of the appended claims.