Abstract:
A high-speed and low-power encoder and an encoding method, wherein the encoder includes a switching unit for receiving a thermal code of a predetermined number of bits received in series, and outputting one bit among the received bits as a most significant bit and the other bits in parallel, and an encoder for dividing the bits received from the switching unit in parallel into groups having a predetermined number of bits, encoding the bits in each group into a predetermined number of bits, selecting one group of encoded bits using bits not used by the groups, and outputting least significant bits together with the most significant bit output from the switching unit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to an encoder, and more particularly, to an encoder which operates at high speed and uses a small amount of power, and an encoding method using the same.  
           [0003]    2. Description of the Related Art  
           [0004]    In conventional flash-type analog-to-digital converters (hereinafter, referred to as ADCs), the outputs of comparators form a thermal code. Here, an encoder converts the thermal code into a binary code or a binary-coded-decimal (BCD) code to perform further processing on the thermal code. The encoder must operate at high speed and provide a high resolution in communications systems where an analog video signal or an analog audio signal is converted into a digital signal. Existing types of encoders include a priority encoder and a memory cell encoder.  
           [0005]    [0005]FIG. 1 is a block diagram of a conventional priority encoder. The priority encoder of FIG. 1 converts 16-bits produced from an analog signal into 4 bits, which correspond to least significant bits (LSBs), and 2 bits, which correspond to most significant bits (MSBs).  
           [0006]    Referring to FIG. 1, a code generator  110  converts an analog signal of 64 levels into a digital signal of 16 bits (b 0 -b 15 ). An LSB encoder  100  is made up of first, second, third, fourth and fifth encoders  111 , 112 , 113 , 114  and  115  and first and second selectors  116  and  117 . That is, the first, second, third and fourth encoders  111 , 112 , 113  and  114  receive b 0  through b 3 , b 4  through b 7 , b 8  through b 11  and b 12  through b 15 , respectively, and encode the received four bits into 3-bits. The fifth encoder  115  receives four bits, one from each of the first, second, third and fourth encoders  111 , 112 ,  113  and  114 , and encodes the four bits into two LSBs b 2  and b 3 . Further, each of the first and second selectors  116  and  117  encodes 4 bits, which are output from each of the first, second, third and fourth encoders  111 ,  112 ,  113  and  114 , into bits b 1  and b 0 , respectively.  
           [0007]    An MSB encoder  122  encodes four MSBs B 0  through B 3  into two MSBs B 0  and B 1 . A corrector  120  corrects six received bits b 0  through b 3  and B 0  and B 1 .  
           [0008]    The priority encoder as shown in FIG. 1 performs all operations using a signal output from an ADC, so that a large capacity buffer is needed, and the critical path becomes long. The large-capacity buffer and the long critical path of the priority encoder of FIG. 1 cause high power consumption and a long delay in the processing of digital signals. Also, the priority encoder as shown in FIG. 1 includes selectors  116  and  117  and has a complicated circuit structure, so that it is disadvantageous in terms of speed and power.  
           [0009]    Memory cell type encoders are also enlarged with an increase in the number of input bits, and a complicated data path causes delay and noise.  
         SUMMARY OF THE INVENTION  
         [0010]    An objective of the present invention is to provide a high-speed encoder in which the current consumption and delay time are reduced by shortening a data path without increasing the area of use.  
           [0011]    Another objective of the present invention is to provide an encoding method for reducing current consumption and delay time by shortening a data path without increasing the area of use.  
           [0012]    To achieve the first objective, the present invention provides a high-speed encoder including: a switching unit for receiving a thermal code of a predetermined number of bits received in series, and outputting one bit among the received bits as a most significant bit and the other bits in parallel; and an encoder for dividing the bits received from the switching unit in parallel into groups having a predetermined number of bits, encoding the bits in each group into a predetermined number of bits, selecting one group of encoded bits using bits not used by the groups, and outputting least significant bits together with the most significant bit output from the switching unit. The encoder includes: a block unit for dividing the received bits into blocks having a predetermined number of bits and encoding the signals in each group into a predetermined number of bits; a selection unit for selecting the encoded bits in one among the blocks by combining bits not used by the blocks among the received bits; and a bit generation unit for generating bits other than the encoded bits selected by the selection unit and the bit generated by the switching unit, by combining the unused bits.  
           [0013]    To achieve the second objective, the present invention provides a method of encoding a thermal code output from an analog-to-digital converter, the method including: dividing received bits into blocks having a predetermined number of bits and encoding the bits in each group into a predetermined number of bits; selecting one among the blocks by combining bits not used by the blocks among the received bits, and generating the encoded bits in the selected block; and generating bits other than the encoded bits generated in the previous step, by combining the unused bits. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The above objectives and advantage of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:  
         [0015]    [0015]FIG. 1 is a block diagram of a typical priority encoder;  
         [0016]    [0016]FIG. 2 is a block diagram of a high-speed encoder according to the present invention;  
         [0017]    [0017]FIG. 3 is a detailed block diagram of the switching unit of FIG. 2;  
         [0018]    [0018]FIG. 4 is a detailed circuit diagram of the latch of FIG. 3; and  
         [0019]    [0019]FIG. 5 is a detailed block diagram of the encoder of FIG. 2. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0020]    Referring to FIG. 2, a high-speed encoder according to the present invention includes a switching unit  210  and an encoder  220 . The switching unit  210  receives a thermal code consisting of a total of 32 bits received in series, and outputs bit  1  as an MSB b 6  and the remaining bits, bit  2  through bit  32 , in parallel. The encoder  220  generates bits b 1  through b 5 , which are least significant bits (LSBs), using bit  2  through bit  32  output from the switching unit  210 .  
         [0021]    Referring to FIG. 3, the switching unit  210  of FIG. 2 is made up of 32 latches  301   a  through  332   a ,  31  multiplexers  302   b  through  332   b , and 6 inverters INV 1  through INV 6 .  
         [0022]    The latches  301   a  through  332   a  receive bits i 1  through i 32  and complementary bits i 1   b  through i 32   b  via two input ports in 1  and in 1   b , respectively, latch the bits i 1  through i 32  and the complementary bits i 1   b  through i 32   b , and output the results of the latching via two output ports data and datab. The multiplexers  302   b  and  332   b  receive control signals c 1  and c 1   b  via input ports in and inb, respectively, from the two output ports data and datab of the first latch  301   a , receive signals via input ports dat and datb from the output ports data and datab of the latches  302   a  through  332   a  in response to the control signals c 1  and c 1  b, and output MUXed data out 2  through out 32 , respectively.  
         [0023]    Referring to FIG. 3, first, the first latch  301  a receives a first bit signal i 1 , and generates the two control signals c 1  and c 1   b  for controlling the multiplexers  302   b  through  332   b  and a MSB bit b 6 . The other latches  302   a  through  332   a  latch the received bits i 2  through i 32 , respectively, and particularly convert a zero return signal into a nonzero return signal in order to save the power for bit switching.  
         [0024]    The multiplexers  302   b  through  332   b  output  32  bits in response to the control signals c 1  and c 1   b  generated by the first latch  301   a . That is, when the bit i 1  received by the first latch  301   a  is high, the multiplexers  302   b  through  332   b  output the signals i 2  through i 32  received by the latches  302   a  through  332   a  without change. Also, when the bit i 1  received by the first latch  301   a  is low, the multiplexers  302   b  through  332   b  output the complementary signals i 2   b  through i 32   b  received by the latches  302   a  through  332   a . The inverters INV 1  through INV 6  buffer the control signals c 1  and c 1   b  to be applied to the selection ports in and inb of the multiplexers  302   b  through  332   b.    
         [0025]    [0025]FIG. 4 is a detailed circuit diagram of the first latch  301  a of FIG. 3. Referring to FIG. 4, the first latch  301   a  includes an input unit  410  and an output unit  420 . The input unit  410  is made up of N-channel MOS transistors N 3 , N 4 , N 5  and N 6 . The N-channel MOS transistor N 3  transfers the output signal of the first inverter INV 1  to a node a in response to the input bit i 1  of the input port  410 . The N-channel MOS transistor N 4  transfers the output signal of the second inverter INV 2  to a node b in response to the input bit i 1  of the input port  410 . The N-channel MOS transistor N 5  transfers the output signal of the second inverter INV 2  to a node b in response to the input bit i 1   b  of the input port  410 . The N-channel MOS transistor N 6  transfers the output signal of the first inverter INV 1  to a node a in response to the input bit i 1   b  of the input port  410 . The output unit  420  is made up of P channel MOS transistors P 0  and P 3  and third and fourth inverters INV 3  and INV 4 . One end of the P channel MOS transistor P 0  is connected to the node a, the other end is connected to the output port datab, and the gate is connected to the output port data. One end of the P channel MOS transistor P 3  is connected to the node b, the other end is connected to the output port data, and the gate is connected to the output port datab. The third inverter INV 3  is connected between the node a and the output port data, and the fourth inverter INV 4  is connected between the node b and the output port datab.  
         [0026]    Referring to FIG. 4, the output unit  420  outputs data for controlling the multiplexers  302   b  through  332   b . That is, when the first bit i 1  received by the output unit  420  is in a high state, the signals i 2  through i 32  are output without change, and when the first bit i 1  received by the output unit  420  is in a low state, the complementary signals i 2   b  through i 32   b  are output.  
         [0027]    [0027]FIG. 5 is a detailed block diagram of the encoder  220  of FIG. 2. Referring to FIG. 5, the encoder  220  includes first, second, third and fourth blocks  510 ,  520 ,  530  and  540 , each for blocking a predetermined number of the input signals i 2  through i 32  and ib 2  through ib 32 , an LSB selector  550  for selecting one among the first, second, third and fourth blocks  510 ,  520 ,  530  and  540 , a switching unit  560  for outputting the outputs of one among the first, second, third and fourth blocks  510 ,  520 ,  530  and  540  in response to a control signal output from the LSB selector  550 , a B 4  generator  570  for generating a bit b 4 , a B 5  generator  580  for generating a bit b 5 , and a D flip flop  590  for latching bits b 1 -b 6  output from the switching unit  560 , the B 4  generator  570 , the B 5  generator  580  and the switching unit  210 .  
         [0028]    The first, second, third and fourth blocks  510 ,  520 ,  530  and  540  receive bit  2  through bit  8  (i 2  through i 8 ), bit  10  through bit  16  (i 10  through i 16 ), bit  18  through bit  24  (i 18  through i 24 ), and bit  26  through bit  32  (i 26  through i 32 ), respectively, and each encode the received bits into 3 bits b 1  through b 3 .  
         [0029]    The switching unit  560  transfers three bits selected from the outputs of the first through fourth blocks  510  through  540  to the D flip flop  590  in response to the control signal of the LSB selector  550 .  
         [0030]    The LSB selector  550  generates the control signal for selecting one among the first, second, third and fourth blocks  510 ,  520 ,  530  and  540  using input signals i 9 , i 17  and i 25  not used by the first through fourth blocks  510  through  540  among the input signals i 2  through i 32 .  
         [0031]    The B 4  generator  570  generates a bit b 4  using the input signals i 9  and i 25  not used by the first through fourth blocks  510  through  540  among the input signals i 2  through i 32 .  
         [0032]    The B 5  generator  580  generates a bit b 5  using the input signals i 17  and i 25  not used by the first through fourth blocks  510  through  540  among the input signals i 2  through i 32 .  
         [0033]    Here, the first through fourth blocks  510  through  540  require the time taken for data to undergo  3  multiplexers, and the LSB selector  550  requires only about the time taken for data to undergo  2  multiplexers. Thus, little delay occurs.  
         [0034]    The D flip flop  590  latches bits b 4  and b 5  output from the B 4  generator  570  and the B 5  generator  580 , bits b 1  through b 3  output from the switching unit  560 , and a bit b 6  output from the switching unit  210 .  
         [0035]    As described above, the high-speed encoder according to the present invention can reduce current consumption and delay time by shortening a data path without increasing the area occupied by the high-speed encoder within a chip. Also, power consumption due to clock switching is reduced by converting a zero return signal into a non-zero return signal using latches.