Abstract:
Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Description:
BACKGROUND 
       [0001]    The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to chip packages and methods of forming a chip package. 
         [0002]    Bipolar junction transistors may be found, among other end uses, in chips for high-frequency and high-power applications. In particular, bipolar junction transistors may find specific end uses in amplifiers for wireless communications systems and mobile devices, switches, and oscillators. Bipolar junction transistors may also be used in high-speed logic circuits. Bipolar junction transistors are three-terminal electronic devices that include an emitter, an intrinsic base, and a collector defined by regions of different semiconductor materials. In the device structure, the intrinsic base is situated between the emitter and collector. An NPN bipolar junction transistor may include n-type semiconductor material regions constituting the emitter and collector, and a region of p-type semiconductor material constituting the intrinsic base. A PNP bipolar junction transistor includes p-type semiconductor material regions constituting the emitter and collector, and a region of n-type semiconductor material constituting the intrinsic base. In operation, the base-emitter junction is forward biased, the base-collector junction is reverse biased, and the collector-emitter current may be controlled by the base-emitter voltage. 
         [0003]    Packaging is one of the final steps in the process of manufacturing chips. In packaging, a fabricated chip is mounted within a protective housing. Packaging must consider heat transfer needs and, in particular, the need to adequately transfer heat out the package. 
         [0004]    Improved chip packages and methods of forming a chip package are needed. 
       SUMMARY 
       [0005]    In an embodiment of the invention, a method is provided for forming a chip package. A chip is formed that includes a device structure with a first emitter finger and a second emitter finger. The first emitter finger and the second emitter finger having at least one parameter. A thermal pathway structure is formed that is configured to influence transport of heat energy emitted from the first emitter finger and the second emitter finger. The at least one parameter for the first emitter finger and the second emitter finger is selected based upon proximity to the thermal pathway structure. 
         [0006]    In an embodiment of the invention, a chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. 
           [0008]      FIG. 1  is a diagrammatic view of a package and a chip in accordance with an embodiment of the invention. 
           [0009]      FIG. 2  is a top view of the device structure located in an area on the chip of  FIG. 1  in accordance with an embodiment of the invention. 
           [0010]      FIG. 2A  is a cross-sectional view taken generally along line  2 A- 2 A in  FIG. 2 . 
           [0011]      FIGS. 3 and 4  are top views of one of the cells of the device structure of  FIGS. 1, 2, 2A  in accordance with alternative embodiments of the invention. 
           [0012]      FIGS. 5 and 6  are top views of device structures similar to  FIG. 2  in accordance with alternative embodiments of the invention. 
           [0013]      FIG. 7  is a diagrammatic view of an exemplary computer system configured to determine the parameterization of the emitter fingers and cells consistent with the embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    With reference to  FIGS. 1, 2, 2A  and in accordance with an embodiment of the invention, a device structure  10  may be located in an area  44  on a chip  76  formed using a substrate  11 . The chip  76  may include heat sinks  46 ,  48 ,  50  and one or more heat sources  52 . The chip  76  may be assembled for use in an end product in chip packaging, which includes a package element  54 . 
         [0015]    In an embodiment, the heat sinks  46 ,  48 ,  50  may comprise through-substrate vias extend through the entire thickness of the substrate  11 . Through-substrate vias may be fabricated by deep reactive ion etching or laser drilling a deep via into the substrate  11 , electrically insulating the deep via with a dielectric material, lining the via with a conductive liner that is a diffusion barrier and/or adhesion promoter, and filling the via with a conductor such as a metal (e.g., copper). After the vias are filled, the substrate  11  may be thinned from its back side by grinding and/or a wet or dry etch to reduce its original thickness and thereby expose the opposite end of each through-substrate via at the depth of the vias. The through-substrate vias provide continuous conductive paths through the substrate  11  for signals, power, and/or ground, as well as paths for thermal conduction. 
         [0016]    In another embodiment, the heat sinks  46 ,  48 ,  50  may comprise conductive pillars. Conductive pillars may be fabricated by electroplating a metal, such as copper, onto a final metal pad in a top level of the interconnect structure of the chip  76 . A plating resist may provide the placement of the conductive pillars relative to the final metal pads. The conductive pillars may be topped by solder caps. The conductive pillars provide continuous conductive paths for signals, power, and/or ground, as well as paths for thermal conduction. 
         [0017]    The heat sources  52  comprise devices on the chip  76  that generate heat when the chip  76  is powered. For example, the heat sources  52  may comprise passive devices in the interconnect structure of the chip  76  or active devices on the substrate  11 . 
         [0018]    The chip packaging, which includes the package element  54 , protects the chip  76  from physical damage and external stresses. In addition, the chip packaging can provide thermal conductance paths to efficiently remove heat generated in the chip  76 , and also provide electrical connections to other components such as printed circuit boards. Materials used for chip packaging typically comprise ceramic or plastic, and form-factors such as ceramic flat packs, dual in-line packages, pin grid arrays, leadless chip carrier packages, etc. 
         [0019]    The emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  of the device structure  10  may be located on the chip  76  at a given distance from the package element  54  of the chip packaging. The package element  54  may be comprised of a thermal insulator characterized by a low thermal conductivity. The package element  54  restricts the transport of heat energy across its boundary in the chip packaging. The package element  54  may comprise, as examples, a glass-reinforced epoxy laminate to which the chip  76  is attached, an underfill material beneath the chip  76  in the package, or a polymer (e.g., an epoxy mold compound) comprising a molded packaging material of the package. 
         [0020]    As best shown in  FIGS. 2, 2A , the substrate  11  may comprise a single-crystal semiconductor material usable to form the devices of an integrated circuit. For simplicity, the device structure  10  does not show some details associated with a typical SiGe HBT or other NPN transistor types. The semiconductor material constituting the substrate  11  may include an epitaxial layer at its top surface, which may contain an amount of an electrically-active dopant that enhances its electrical properties relative to the remainder of the substrate  11 . For example, the substrate  11  may include an epitaxial layer of single crystal silicon that is doped with a concentration of, in a construction for an NPN transistor, an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) in a concentration effective to impart n-type conductivity. 
         [0021]    Shallow trench isolation regions  12  are located in the semiconductor material of the substrate  11 . The shallow trench isolation regions  12  define the bounds of, and furnish electrical isolation for, each emitter finger relative to the adjacent ones through the collector  14 . In certain embodiments, the trench isolation regions  12  may be omitted from internal emitter finger regions to improve thermal dissipation. 
         [0022]    Deep trench isolation regions  13  are located in the semiconductor material of the substrate  11 . The trench isolation regions  13  define the bounds of, and furnish electrical isolation for, the collector  14  and collector contact regions  16 - 19 , which are each comprised of the semiconductor material of the substrate  11  to the adjacent devices. The collector contact regions  16 - 19  are positioned adjacent to the collector  14 , and are laterally separated from the collector  14  by the shallow trench isolation regions  12 . The collector contact regions  16 - 19  are coupled with the collector  14  by portions of the semiconductor material of the substrate  11  positioned beneath the shallow trench isolation regions  12 . Typically, the deep trench isolation regions  13  are 3 um to 6 um deep relative to the top surface of the substrate  11  and are filled with one or more dielectric materials. In certain embodiments, the deep trench isolation regions  13  may be omitted from the collector boundary regions and replaced with shallow trench isolation regions  12  for better thermal dissipation. 
         [0023]    The shallow trench isolation regions  12  may be formed by depositing a hardmask, patterning the hardmask and substrate  11  with lithography and etching processes to define trenches, depositing an electrical insulator to fill the trenches, planarizing the electrical insulator relative to the hardmask using a chemical mechanical polishing (CMP) process, and removing the hardmask. In one embodiment, the shallow trench isolation regions  12  may be comprised of silicon dioxide (SiO 2 ) deposited by chemical vapor phase deposition (CVD). 
         [0024]    The deep trench isolation regions  13  may be formed by depositing a hardmask, patterning with lithography and etching processes to define trenches through the shallow trench region  12  and substrate  11 , depositing an electrical insulator to fill the trenches, planarizing using a chemical mechanical polishing (CMP) process, and removing the hardmask. In one embodiment, the trench isolation regions  13  may be comprised of silicon dioxide (SiO 2 ) deposited by chemical vapor phase deposition (CVD). 
         [0025]    The chip  76  includes a device structure  10  that is formed using the semiconductor material of the substrate  11 . A base layer  20  of the device structure  10  is located on a top surface of the substrate  11 . The base layer  20  may be comprised of a semiconductor material, such as silicon-germanium (SiGe) in an alloy with a content of silicon (Si) ranging from 95 atomic percent to 50 atomic percent and a content of germanium (Ge) ranging from 5 atomic percent to 50 atomic percent. The germanium content of the base layer  20  may be uniform across the thickness of base layer  20 , or graded and/or stepped across the thickness of base layer  20 . If the germanium content is stepped, respective thicknesses of the base layer  20  that are directly adjacent to the substrate  11  and directly adjacent to the subsequently-formed emitter fingers may lack a germanium content and may therefore constitute intrinsic layers comprised entirely of silicon. The base layer  20  may comprise a dopant, such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity to the constituent semiconductor material and, optionally, carbon (C) to suppress the mobility of the p-type dopant. 
         [0026]    The base layer  20  may be formed using a low temperature epitaxial (LTE) growth process, such as vapor phase epitaxy (VPE) conducted at a growth temperature ranging from 400° C. to 850° C. Single crystal semiconductor material (e.g., single crystal silicon and/or single crystal SiGe) is epitaxially grown or deposited by the low temperature epitaxial growth process on the top surface of substrate  11 . The base layer  20  may have an epitaxial relationship with the single crystal semiconductor material of the substrate  11  in which the crystal structure and orientation of the substrate  11  operates as a template to establish the crystal structure and orientation of the base layer  20  during growth. 
         [0027]    An emitter of the device structure  10  is collectively comprised of a plurality of emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  that are located on the top surface  20   a  of the base layer  20 . The emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be comprised of a semiconductor material than differs in composition from the semiconductor material of the base layer  20  and that has an opposite conductivity type from the semiconductor material of the base layer  20 . For example, the composition of the material comprising the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be comprised of silicon and lack germanium that is present in at least a portion of the base layer  20 , and may contain an n-type dopant in a concentration effective to impart n-type conductivity. In a representative embodiment, the semiconductor material comprising the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be n-type polysilicon (i.e., n-type polycrystalline silicon) deposited by chemical vapor deposition. 
         [0028]    To form the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33 , a mask layer may be applied on a top surface of a deposited layer (e.g., n-type polysilicon) and patterned with photolithography. Specifically, a mask layer is applied that includes stripes are covering the deposited layer at the intended location of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  to be subsequently formed. To that end, the mask layer may comprise a light-sensitive material, such as a photoresist, that is applied as a coating by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to pattern an etch mask. An etching process is used, with the mask layer present on the top surface of the deposited layer, to form the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  from the deposited layer at the locations of the stripes in the pattern. The etching process may be conducted in a single etching step or multiple steps, and may rely on one or more etch chemistries. The mask layer may be removed after the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  are formed by the etching process. If comprised of a photoresist, the mask layer may be removed by ashing or solvent stripping, followed by a conventional cleaning process. 
         [0029]    The portions of the base layer  20  covered by the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may define an intrinsic base that forms a junction with the emitter, and that forms another junction with the collector  14 . Portions of the base layer  20  that are not covered by the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be doped (e.g., by ion implantation) to define an extrinsic base with enhanced electrical conductivity after dopant activation. Spacers  15  may be formed on the vertical sidewalls of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  by etching one or more dielectric layers (e.g., silicon dioxide or silicon nitride (Si 3 N 4 )) with an anisotropic etching process. 
         [0030]    The resulting device structure  10  is a bipolar junction transistor that includes multiple emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33 , the collector  14 , and the portion of the base layer  20  (i.e., intrinsic base) that is vertically between the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  and the collector  14 . The emitter fingers  22 - 25  in cell  36 , the emitter fingers  26 - 29  in cell  38 , and the emitter fingers  30 - 33  in cell  40  are connected in parallel at the back-end-of-line wiring levels or levels. The device structure  10  may be characterized as a heterojunction bipolar transistor (HBT) if two or all three of the semiconductor materials comprising the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33 , the collector  14 , and the base layer  20  have different compositions. During the front-end-of-line (FEOL) portion of the fabrication process, the device structure  10  is replicated across at least a portion of the surface area of the substrate  11 . In BiCMOS integrated circuits, complementary metal-oxide-semiconductor (CMOS) transistors may be formed using other regions of the substrate  11 , and may be protected while bipolar junction transistors are formed. As a result, bipolar junction transistors (or HBTs) and CMOS transistors may be available and co-located on the same substrate  11 . 
         [0031]    In an alternative embodiment, the device structure  10  may include only a single cell  38  that includes emitter fingers  26 - 29 . In an alternative embodiment, the device structure  10  may include any number of cells (“N”) or an array containing multiple rows (“M”) each including any number of cells (“N”). 
         [0032]    Standard middle-of-line (MOL) processing and back-end-of-line (BEOL) processing follows, which includes formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled with the device structure  10 , as well as other similar contacts for additional device structures  10  and CMOS transistors that may be included in other circuitry of the chip  76 . Wiring formed by middle-of-line processing and back-end-of-line processing may couple the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in parallel with other circuitry on the chip  76  or off the chip  76 . 
         [0033]    The emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  are arranged lengthwise parallel to each other with emitter fingers  22 - 25  located in a cell  36  at the periphery of the device structure  10 , emitter fingers  30 - 33  located in a cell  40  at the periphery of the device structure  10 , and emitter fingers  26 - 29  centrally located in a cell  38  between the peripheral cells  36 ,  38 . At least one row of base contacts  41  is located between each pair of emitter fingers  22 - 33  and at the peripheral side edges of each of the cells  36 ,  38 ,  40 . In cell  36 , the middle emitter fingers  23 ,  24  are located laterally between the side emitter fingers  22 ,  25 . In cell  38 , the middle emitter fingers  27 ,  28  are located laterally between the side emitter fingers  26 ,  29 . In cell  40 , the middle emitter fingers  31 ,  32  are located laterally between the side emitter fingers  30 ,  33 . Collector contact regions  16  and  19  are located at the side edges of the device structure  10 . Collector contact region  17  is located between cell  36  and cell  38 , and collector contact region  18  is located between cell  38  and cell  40 . 
         [0034]    The emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  are characterized by at least one parameter relating to their size (e.g., width) and/or placement (e.g., spacing). The widths of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be assessed in a direction transverse to the respective lengths (which may be equal), and the emitter-emitter spacings may be assessed in a direction parallel to the widths. As a result, the sum of the widths and spacings of emitter fingers  22 - 25  multiplied by their equal lengths defines the area of cell  36 , the sum of the widths and spacings of emitter fingers  26 - 29  multiplied by their equal lengths defines the area of cell  38 , and the sum of the widths and spacings of emitter fingers  30 - 33  multiplied by their equal lengths defines the area of cell  40 . 
         [0035]    The emitter fingers  22 - 25  may be characterized by respective individual widths W 1 -W 4 , the emitter fingers  26 - 29  may be characterized by respective individual widths W 5 -W 8 , and the emitter fingers  30 - 33  may be characterized by respective individual widths W 9 -W 12 . The emitter fingers  22 - 25  in cell  36  are separated by respective individual emitter-emitter spacings S 1 -S 3 . In particular, emitter finger  22  is separated by spacing S 1  from emitter finger  23 , emitter finger  23  is separated by spacing S 2  from emitter finger  24 , and emitter finger  24  is separated by spacing S 3  from emitter finger  25 . Similarly, the emitter fingers  26 - 29  in cell  38  are separated by respective individual emitter-emitter spacings S 4 -S 6 , and the emitter fingers  30 - 33  in cell  40  are separated by respective individual emitter-emitter spacings S 7 -S 9 . The widths W 1 -W 12  and emitter-emitter spacings S 1 -S 9  are variable quantities that can be individually selected to tune the thermal properties and temperature profile of each of the cells  36 ,  38 ,  40  and the device structure  10  with respect to objects on the substrate  11  that influence the temperature of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33 . The total number of emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  and the number of emitter fingers respectively included in each of the cells  36 ,  38 ,  40  may vary according to the device design. 
         [0036]    The widths and/or spacings of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be selected to lower the temperature profile across the chip package and to provide an improved temperature uniformity profile across the chip package. Width and/or spacing requirements are different considering the presence of a heat sink, such as the heat sinks  46 ,  48 ,  50  or an insulator, such as the package and its package element  54 . 
         [0037]    As best shown in  FIG. 1 , the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  of the device structure  10  are located in the area  44  on the chip  76 . When powered during operation, the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  emit heat energy that is transported away from the area  44  by various thermal pathways comprised of various structures, such as heat sinks, package elements, heat sources, etc. The thermal pathways end at an external surface of the chip package that transfers the heat energy to the environment surrounding the chip package for dissipation. 
         [0038]    The emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  of the device structure  10  may be located on the chip  76  at given distances, d 1 , from heat sinks  46 ,  48 ,  50 . The device structure  10  may be directly connected with one or more of the heat sinks  46 ,  48 ,  50  and, in the representative embodiment, is directly connected with heat sink  46  and heat sink  48 . 
         [0039]    Different cells  36 ,  38 ,  40  of the device structure  10  may be located on the substrate  11  at different distances from each of the heat sinks  46 ,  48 ,  50 . In the representative embodiment, cell  36  is located closer to heat sink  46  than cells  38 ,  40 , cell  40  is located closer to heat sink  48  than cells  36 ,  38 , and cell  38  is located equidistant from heat sink  46  and heat sink  48 . Different cells  36 ,  38 ,  40  and the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in the cells  36 ,  38 ,  40  are located at different distances from other heat sinks, such as heat sink  50 . The differences in the distances may be present with finer granularity than on the coarser-scale level of the cells  36 ,  38 ,  40 . Within cell  36 , the different emitter fingers  22 - 25  and different portions of each of the emitter fingers  22 - 25  may be located at different distances from each of the heat sinks  46 ,  48 ,  50 . Similarly, the emitter fingers  26 - 29  within cell  38  and their different portions may be located at different distances from each of the heat sinks  46 ,  48 ,  50 , and the emitter fingers  31 - 33  within cell  40  and their different portions may be located at different distances from each of the heat sinks  46 ,  48 ,  50 . 
         [0040]    The emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  of the device structure  10  may also be located on the chip  76  at a given distance, d 3 , from the one or more heat sources  52 . Different cells  36 ,  38 ,  40  and the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in the cells  36 ,  38 ,  40  of the device structure  10  may be located on the substrate  11  at different distances, d 3 , from each of the heat sources  52 . In the representative embodiment, cell  36  is located closer to the heat source  52  than cells  38 ,  40 , cell  38  is located closer to heat source  52  than cell  40 , and cell  40  is located at the greatest distance from heat source  52 . The differences in the distances may be present with finer granularity than on the coarser-scale level of the cells  36 ,  38 ,  40 . Within cell  36 , the different emitter fingers  22 - 25  and different portions of each of the emitter fingers  22 - 25  may individually be located at different distances from each of the heat sources  52 . Similarly, the emitter fingers  26 - 29  within cell  38  and their different portions may be located at different distances from each of the heat sources  52 , and the emitter fingers  30 - 33  within cell  40  and their different portions may be located at different distances from each of the heat sources  52 . 
         [0041]    Different cells  36 ,  38 ,  40  and the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in the cells  36 ,  38 ,  40  of the device structure  10  may be located on the substrate  11  at different distances from the package element  54 . In the representative embodiment, cell  36  is located at the greatest distance from package element  54  than cells  38 ,  40 , cell  38  is located closer to package element  54  than cell  36 , and cell  40  is located at the shortest distance from package element  54 . Within cell  36 , the different emitter fingers  22 - 25  and different portions of each of the emitter fingers  22 - 25  may individually be located at different distances, d 2 , from the package element  54 . Similarly, the emitter fingers  26 - 29  within cell  38  and their different portions may be located at different distances from the package element  54 , and the emitter fingers  31 - 33  within cell  40  and their different portions may be located at different distances from the package element  54 . 
         [0042]    The various distances of the different cells  36 ,  38 ,  40  and the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in the cells  36 ,  38 ,  40  from each of the heat sources  52 , the heat sinks  46 ,  48 ,  50 , and/or the package element  54  are such that the widths and/or the spacings can influence the operating temperatures of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33 . The temperature variation for the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  across the device structure  10  in a chip package can be optimized through the selection of dimensions and/or pitches for the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  as part of a thermal management process that reduces the occurrence of areas on the chip  76  with operating temperatures that are greater than the operating temperatures of other areas on the chip  76 . In an embodiment, the widths and/or the spacings of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be selected to reduce the temperature variation within the device structure  10  and the temperature variation across the chip  76  when compared with other areas of heat generation on the chip  76  when packaged and operating. 
         [0043]    During operation, the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  experience a temperature rise arising from power dissipation and Joule heating as electrical current is transferred through them, such as during operation as a power amplifier or a low-noise amplifier. When powered, the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  represent heat sources that emit heat energy. As described by the law of heat conduction (e.g., Fourier&#39;s law), the emitted heat energy from the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  will be transferred through intervening solid material (e.g., through the dielectric material and wiring of the interconnect structure and/or through the substrate  11 ) toward colder bodies, such as the heat sinks  46 . As also described by Fourier&#39;s law, heat energy from other powered objects, such as the heat sources  52 , may heat the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  and/or contribute to increasing the temperature of the solid material conducting the emitted heat energy from the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33 . The thermal barrier provided by the package element  54  may also affect the thermal conduction of heat energy away from the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  by confining the emitted heat energy from the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  so that the temperature of the solid material rises as the heat energy lacks a path for dissipation. 
         [0044]    The design for the device structure  10  may consider thermal insulation from the package element  54 , heat flow from the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  through each of heat sinks  46 ,  48 ,  50 , and the heat energy contributed by the heat sources  52 . Through selection of, among other factors, the widths W 1 -W 12  and emitter-emitter spacings S 1 -S 9  of the emitter fingers  22 - 25  in cell  36 , the emitter fingers  26 - 29  in cell  38 , and the emitter fingers  30 - 33  in cell  40 , the temperature may be more uniform across of the device structure  10 , although the temperature might not be uniform for each of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  or each of the cells  36 ,  38 ,  40 . Emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in cells  36 ,  38 ,  40  close to the package element  54  may have narrower widths and may have larger spacings. Emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in cells  36 ,  38 ,  40  close to heat sinks  46 ,  48 ,  50  may have wider widths and may have smaller spacings. The result of the determination is a device structure  10  having multiple different widths and multiple different emitter-emitter spacings for the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  across the entire device structure  10 . 
         [0045]    With reference to  FIG. 3  in which like reference numerals refer to like features in  FIGS. 1, 2, 2A , a determination of an adjustment to the spacings S 1 -S 9  that takes into account the proximity of the heat sinks  46 ,  48  may be illustrated for the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in cells  36 ,  38 ,  40  of the device structure  10 . Specifically, in view of the greater separation of the heat sinks  46 ,  48  from cell  38  than cells  36 ,  40 , the emitter spacing of the emitter fingers  26 - 29  in cell  38  may be modified relative to the spacings for the emitter fingers  22 - 25  in cell  36  and the spacings for the emitter fingers  26 - 29  in cell  40 . For the representative cell  38 , the spacings are adjusted such that the spacing S 5  between emitter finger  27  and emitter finger  28  is greater than the spacing S 4  between emitter finger  26  and emitter finger  27  and is greater than the spacing S 6  between emitter finger  28  and emitter finger  29 . Due to the increasing value of the spacing S 5 , multiple rows of base contacts  41  can be located between emitter finger  27  and emitter finger  28 . 
         [0046]    This exemplary embodiment reflects that the emitter fingers  27 ,  28  in cell  38  can be fabricated with a spacing S 5  that is greater than the spacings S 1 -S 3  in cell  36  and that is greater than the spacings S 7 -S 9  in cell  40  ( FIG. 2 ). The relative increase in spacing S 5  may reduce the operating temperature of the emitter fingers  26 - 29  in cell  38  in comparison with the emitter fingers  22 - 25  in cell  36  and the emitter fingers  30 - 33  in cell  40 . The temperature reduction may improve temperature uniformity across the device structure  10  because heat energy is dissipated less efficiently from cell  38  to the heat sinks  46 ,  48  due to the greater distance in the path for heat conduction from cell  38  in comparison with cell  36  and cell  40 , which have shorter paths for heat conduction to the heat sinks  46 ,  48 . 
         [0047]    Generally, for the exemplary embodiment of  FIG. 3 , the greater proximity of the heat sinks  46 ,  48  to cell  36  and cell  40  than to cell  38  may result in the need to increase one or more of the spacings S 4 , S 5 , S 6  of the emitter fingers  26 - 29  compared with the spacings S 1 , S 2 , S 3  of the emitter fingers  22 - 25  and/or the spacings S 7 , S 8 , S 9  of the emitter fingers  30 - 33 . In other words, the emitter fingers  26 - 29  may have one or more spacings that are greater than the spacings for the emitter fingers  22 - 25  and/or the spacings for the emitter fingers  30 - 33 . Alternatively, the greater proximity of the heat sinks  46 ,  48  to cell  36  and cell  40  than to cell  38  may result in the need to decrease one or more of the widths W 5 , W 6 , W 7 , W 8  of the emitter fingers  26 - 29  compared with the widths W 1 , W 2 , W 3 , W 4  of the emitter fingers  22 - 25  and/or the widths W 9 , W 10 , W 11 , W 12  of the emitter fingers  30 - 33 . In other words, the emitter fingers  26 - 29  may have one or more widths that are greater than the emitter fingers  22 - 25  and/or emitter fingers  30 - 33 . Eliminating one or the other of the heat sinks  46 ,  48  would change the determination of the spacings and/or widths that take into account the relative proximity to the remaining one of the heat sinks  46 ,  48 . 
         [0048]    With reference to  FIG. 4  in which like reference numerals refer to like features in  FIGS. 1, 2, 2A, 3 , a determination of an adjustment to the widths W 1 -W 12  that takes into account the proximity of the package element  54  may be illustrated for the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  in cells  36 ,  38 ,  40  of the device structure  10 . Specifically, in view of the greater separation of the heat sinks  46 ,  48  from cell  38  than cells  36 ,  40 , the widths of the emitter fingers  26 - 29  in cell  38  may be modified relative to the widths for the emitter fingers  22 - 25  in cell  36  and the widths for the emitter fingers  30 - 33  in cell  40 . For the representative cell  38 , the width W 6  of emitter finger  26  and the width W 7  of emitter finger  27  are adjusted to be less than the width W 5  of emitter finger  25  and the width W 8  of emitter finger  29 . In the representative embodiment, the decrease in the widths W 6 , W 7  relative to widths W 5 , W 8  are used in combination with the increased value of the spacing S 5  relative to spacings S 4 , S 6 . However, in an alternative embodiment, the widths W 6 , W 7  may be decreased relative to widths W 5 , W 8  and the spacings S 4 , S 5 , S 6  may be equal. 
         [0049]    This exemplary embodiment reflects that the emitter fingers  27 ,  28  in cell  38  can be fabricated with widths W 6 , W 7  that are less than the widths W 1 -W 4  of emitter fingers  22 - 25  in cell  36  and the widths W 9 -W 12  of emitter fingers  30 - 33  in cell  40  ( FIG. 2 ). The relative reduction in the widths W 6 , W 7  may reduce the power dissipation and temperature rise in emitter fingers  26 - 29  in cell  38  in comparison with the emitter fingers  22 - 25  in cell  36  and the emitter fingers  30 - 33  in cell  40 . The temperature reduction may improve temperature uniformity across the device structure  10  as cell  38  is further away from heat sinks  46  and  48  compared to cells  36  and  40  resulting in a higher thermal resistance for heat dissipation. 
         [0050]    Combinations of adjustments to the widths W 1 -W 12  and the spacings S 1 -S 9  of the emitter fingers  22 - 25 ,  26 - 29 , and  30 - 33  may be required to account for the presence of both heat sinks and heat-insulating packaging. The simplified situations in  FIGS. 3 and 4  would be combined in some manner by the width/spacing computation to reflect this more complex situation. 
         [0051]    With reference to  FIG. 5  in which like reference numerals refer to like features in  FIGS. 1, 2, 2A, 3 , the spacings S 1 -S 9  may be adjusted within the cells  36 ,  38 ,  40  across the device structure  10  so that each of the cells includes multiple different spacings that are to provide improved temperature uniformity. For the representative cells  36 ,  38 , and  40 , the spacings are adjusted such that the spacing S 5  is greater than the spacings S 1 -S 4  and S 6 -S 9 , and spacings S 3 , S 4 , S 6 , S 7  are greater than the spacings S 1 , S 2 , S 8 , S 9 . The spacings S 1 -S 12  decrease in proportion to the distance d 1  separating the emitter fingers  22 - 33  from the heat sinks  46 ,  48  ( FIG. 1 ). This variation reflects the generalization that emitter fingers closer to a heat sink may have a spacing that is less than the spacing for emitter fingers located at greater distance from the heat sink. 
         [0052]    With reference to  FIG. 6  in which like reference numerals refer to like features in  FIGS. 1, 2, 2A, 3 , the widths W 1 -W 12  may be adjusted within the cells  36 ,  38 ,  40  across the device structure  10  so that each of the cells includes multiple different widths that are to provide may be modified to vary the emitter width. For the representative cells  36 ,  38 ,  40 , the widths are adjusted such that widths W 2 , W 3 , W 6 , W 7 , W 10 , W 11  are less than the widths W 1 , W 4 , W 5 , W 8 , W 9 , W 12 . The widths W 1 -W 4  in cell  36  decrease in proportion to the distance d 1  separating the emitter fingers  22 - 25  from the heat sinks  46 ,  48  ( FIG. 1 ). The widths W 5 -W 8  in cell  38  decrease in proportion to the distance d 1  separating the emitter fingers  26 - 29  from the heat sinks  46 ,  48 . The widths W 9 -W 12  in cell  40  decrease in proportion to the distance d 1  separating the emitter fingers  30 - 33  from the heat sinks  46 ,  48  ( FIG. 1 ). This variation reflects the generalization that emitter fingers within each of the cells  36 ,  38 ,  40  closer to one or the other of the heat sinks  46 ,  48  ( FIG. 1 ) may have a width that is greater than the width for emitter fingers located at greater distance from the heat sink. 
         [0053]    Referring now to  FIG. 7 , a schematic of an exemplary computer system  112  is shown. The computer system  112  may include one or more processors or processing units  116 , a system memory  128 , and a bus  118  that couples various system components including system memory  128  to each processing unit  116 . Bus  118  represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus. 
         [0054]    Computer system  112  typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system  112 , and it includes both volatile and non-volatile media, removable and non-removable media. 
         [0055]    System memory  128  can include computer system readable media in the form of volatile memory, such as random access memory (RAM)  130  and/or cache memory  132 . Computer system  112  may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system  134  can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical media can be provided. In such instances, each can be connected to bus  118  by one or more data media interfaces. As will be further depicted and described below, system memory  128  may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention. 
         [0056]    Program/utility  140 , having a set (at least one) of program modules  142 , may be stored in system memory  128  by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules  142  generally carry out the functions and/or methodologies of embodiments of the invention as described herein. 
         [0057]    Computer system  112  may also communicate with one or more external devices  114  such as a keyboard, a pointing device, a display  124 , etc.; one or more devices that enable a user to interact with computer system  112 ; and/or any devices (e.g., network card, modem, etc.) that enable computer system  112  to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces  122 . Still yet, computer system  112  can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter  120 . As depicted, network adapter  120  communicates with the other components of computer system  112  via bus  118 . It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system  112 . Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc. 
         [0058]    Thermal modeling software may be included among the program modules  142  and may be used by the computer system  112  to evaluate the placement of the emitter fingers. Among the variables that may be computed are the spacing and width of the emitter fingers, as well as the separation between the cells of emitter fingers and different objects that influence the transfer and dissipation of heat energy. As discussed herein, those objects may include heat sources, heat sinks, and thermal insulation that impedes or blocks the transfer of heat energy. The thermal modeling software may rely on numerical methods used in thermal analysis and, in an embodiment, may comprise a finite volume method that is found in computational fluid dynamics (CFD) software. Other varieties of thermal modeling software may rely on boundary element methods, finite difference methods, or finite element methods. One particular variety of CFD thermal analysis software is commercially available from ANSYS. 
         [0059]    The chip package may be approximated in the thermal analysis as a thermal circuit, and the dissipating characteristics of the chip package modeled by a network of heat transfer pathways through which heat energy must flow. Heat energy must be conducted from the chip package through various thermal pathways to reach an outer surface of the package, which is exposed to an ambient air body, and then be dissipated to that ambient air body. Various packaging materials have unique thermal characteristics, such as thermal conductivity. The thermal conductivity of each material in the chip package determines the amount of heat that can be conducted through and away from that material. 
         [0060]    The proximity of the device structure of the chip to heat sinks, package elements, and heat sources can influence the operating temperatures of the different emitter fingers. By considering the proximity of the emitter fingers to heat sinks, package elements, and heat sources, the widths and spacings of the emitter fingers may be optimized such that the area on the chip containing the device structure may not appear as an area of greater heat generation and higher temperature during operation (i.e., a hot spot) in the temperature profile compared with the operating temperature of other areas on the chip. The result is a higher uniformity in the temperature profile across the chip. 
         [0061]    The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0062]    A feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present. 
         [0063]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.