Abstract:
A state machine and its associated method for achieving a faster response time for an interruption of an erase operation is disclosed. In particular, a state machine having a plurality of interconnected execution cycles is disclosed. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles.

Description:
BACKGROUND  
         [0001]    The present invention relates to operations in flash memory devices. More particularly, the present invention relates to a method and apparatus to suspend an operation in a flash memory device.  
           [0002]    Flash memory devices have proven to be important memory elements in the past several years, and industry pundits predict an ever-increasing role for such devices in the future. A great advantage flash memory devices have over typical EPROM&#39;s and EEPROM&#39;s are, respectively, system programmability and lower cost.  
           [0003]    Despite the many advantages of flash memories over other memories, flash memory devices have several opportunities for improvement. For example, flash memories in their typical implementations suffer from the problems of “over erasure” and “wild bits” which result in all bits not behaving exactly alike with respect to their electrical behavior. In fact, many flash memory devices include wide variations of electrical behavior between adjacent bits.  
           [0004]    Designers of flash memory devices have developed very sophisticated schemes in order to resolve the problems related to bits having disparate electrical behavior. For example, a flash memory device during programing or erasing of the memory elements proceeds through a process of interrogating each memory element and evaluating the respective margins after the operation to determine whether it needs to be re-programmed or further erased. The individual treatment of memory elements has caused the logic circuitry associated with flash memories to become very complicated.  
           [0005]    Memory arrays in flash memory devices typically must be programmed before they can be erased in order to avoid erasing bits into a very negative threshold and disturbing data in other bits during reading. Even during the cycle of programming, the device determines if the bits are sufficiently programmed. A unique verification cycle for an erase operation is performed. Some devices tighten the distribution of memory element threshold voltages after the erase operation for better manufacturability. The memory device also often determines, after the erase operation, whether the data in the memory array remains undisturbed. These procedures, as appreciated by those skilled in the art, are very sophisticated.  
           [0006]    In order to perform such a sophisticated operation, an equally sophisticated state machine is often required. Simply put, a state machine can be a controller in a flash memory device or other integrated circuit. The state machine typically includes several steps that must be performed in the erase operation. This operation takes a relatively long period of time for the processors executing the steps, which could be in the order of seconds. Rather than necessarily occupying the processor during this time, a suspend command has been developed to permit the operation to stop itself and allow the processor to read an unaffected block of memory. In prior art flash memories, a suspend command was permitted only during certain predetermined steps in the operation of the state machine. Only certain cycles in the operation could be suspended, which itself proved difficult to implement. For example, if analog voltage generation or discharge was required, a suspended cycle would often prevent a state machine from functioning properly.  
           [0007]    The consequence of a limited number of suspend operations had a deleterious effect on response time. In certain cases, the system was required to wait for up to 100&#39;s of milliseconds to attain a suspendable cycle. Although the prior art suspend system proved to have a better response time than without a suspend command, much room for improvement was left for flash memories to achieve response times in the order of similar devices.  
         SUMMARY OF THE INVENTION  
         [0008]    The present invention relates to a state machine and its associated method for achieving a faster response time for an interruption of an erase operation. In particular, the present invention is directed to a state machine having a plurality of interconnected execution cycles. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 shows a schematic diagram illustrating generally a memory system embodying features of the present invention.  
         [0010]    [0010]FIG. 2 shows a state diagram of a prior art erase operation for use with a state machine.  
         [0011]    [0011]FIG. 3 shows a state diagram embodying features of the present invention and suitable for implementation in the memory system of FIG. 1. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0012]    In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be used and logical, structural, and electrical changes may be made without departing from the scope of the present invention.  
         [0013]    The terms wafer and substrate used in the following description include any semiconductor-based structure having an exposed surface with which to form the integrated circuit structure of the invention. Wafer and substrate are used interchangeably to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and their equivalents.  
         [0014]    [0014]FIG. 1 is a schematic diagram illustrating generally, by way of example, but not by way of limitation, one embodiment of a memory system  100  embodying features of the present invention. Memory system  100  includes memory controller  105  and memory integrated circuit (IC)  110 . Controller  105  includes a microprocessor or any other controller  105  providing interface signals to the memory IC  110 , as described below. Such interface signals include addressing signals, provided at address lines  115 , and data signals, communicated at data lines  120 . Other interface signals provided by controller  105  include write enable (WE*) at node  121 , chip enable (CE*) at node  122 , reset/power-down (RP*) at node  123 , and output enable (OE*) at node  124 , all of which are active low signals. Memory IC  110  provides a status signal (RY/BY*) at node  125  to controller  105  to indicate the status of internal state machine  130 . Memory IC  110  also receives a positive power supply voltage (V CC ) at node  126  (e.g., approximately 3.3 Volts or approximately 5 Volts), a write/erase supply voltage (V PP ) at node  127  (e.g., approximately 5 Volts), and a reference voltage such as substrate ground voltage (V SS ) at node  128  (e.g., approximately 0 Volts).  
         [0015]    In the embodiment of FIG. 1, memory IC  110  includes a memory cell array  135  of floating gate transistor memory cells arranged in 32 memory cell blocks. Each memory cell block in memory cell array  135  contains 64 kilobytes of floating gate transistor memory cells. Data stored in each memory cell block is erased independently, as described below, without disturbing data stored in other memory cell blocks. A command execution logic module  140  receives the above-described interface signals from controller  105 . Command execution logic module  140  controls internal state machine  130 , which provides write and block erase timing sequences to memory cell array  135  through X-interface circuit  145  and Y-interface circuit  150 .  
         [0016]    Y-interface circuit  150  provides access to individual memory cells through data lines in memory cell array  135 . Y-interface circuit  150  includes a Y-decoder circuit, Y-select gates, sense-amplifiers, and write/erase bit compare and verify circuits. X-interface circuit  145  provides access to rows of memory cells through wordlines in memory cell array  135 , which are electrically coupled to control gates (also called select gates) of floating gate transistors in memory cell array  135 . X-interface circuit  145  includes decoding and control circuits for erasing individual blocks of memory cells in memory cell array  135 .  
         [0017]    [0017]FIG. 2 shows a state diagram of a prior art state machine for controlling an erase operation in a flash memory. A similar state machine is described in U.S. Pat. No. 5,619,453, the disclosure of which is hereby incorporated by reference for its description of the state diagram therein. The operation includes a plurality of interconnected execution cycles including incremental cycles and other cycles. The execution cycles of the erase operation are arranged in a plurality of interconnected groups, including a pre-program group  210 , an erase group  212 , and a distribution and adjustment group  214  connected together in the order shown. In order to erase a block of flash memory, a prior art state machine would execute the cycles in the interconnected groups which effectively could take seconds to complete.  
         [0018]    The pre-program group  210  includes a plurality of interconnected execution cycles including incremental cycles and other cycles. As shown in FIG. 2, the pre-program group includes a high voltage state  216  connected to a setup verify state  218 . The setup verify state  218  is connected to a program verify state  220 . If the program verify state  220  determines that the program is not in order, the operation jumps to a high voltage level setup state  222 . The high voltage level setup state  222  is connected back to the high voltage state  216 . If the program verify state  220  determines that the operation is indeed in order, the operation jumps to a program cleanup state  224 . The above described states are designated as other cycles, as opposed to incremental cycles described below.  
         [0019]    The program clean up state  224  jumps to an increment address state  226  when the operation has completed the program for a given address. The increment address state  226  is designated as an incremental cycle because it adjusts a variable, determines if the adjusted variable is a predefined stopping point, and, if so, proceeds with the operation. If not, the incremental cycles sends the operation back into another loop, as appreciated by those skilled in the art. With regard to the increment address state  226 , the operation increases the address variable and compares it to a predetermined maximum address. If the variable is at the maximum address, the operation proceeds to the erase group  212  of cycles. If not, the operation jumps back to the high voltage level setup state  222  and repeats the cycles in the preprogram group.  
         [0020]    The erase group  212  also includes a plurality of cycles including incremental cycles and other cycles. The initial cycle in the erase group  212  is a high voltage level setup state  230  which takes approximately 400 nanoseconds to complete. The high voltage level setup state  230  then jumps to a high voltage state  232  which takes approximately 10 milliseconds to complete. The next cycle is the setup verify state  234 , which takes approximately 5 microseconds to complete. The erase verify state  236  follows the setup verify state  234  and takes approximately 200 nanoseconds to complete. The above described cycles of the erase group  212  are know as other cycles, again as opposed to increment cycles. If the erase verify state  236  determines that the erase operation is complete, the operation jumps to an increment address state  238  which is an increment cycle.  
         [0021]    The increment address state  238  of the erase group  212  is designated as an incremental cycle because, like the increment address state  226  of the pre-program group  210 , it adjusts a variable, determines if the adjusted variable is a predefined stopping point, and, if so, proceeds with the operation. If not, the incremental cycle sends the operation back into another loop. With regard to the increment address state  238  of the erase group  212 , the operation increases the address variable and compares it to a predetermined maximum address. If the variable is at the maximum address, the operation proceeds to distribution and adjustment group  214  of cycles. If not, the operation jumps back to the erase verify state  236 .  
         [0022]    The distribution and adjustment group  214  includes a plurality of other cycles, the group of the present example does not include any incremental cycles. The erase group  212  jumps to the high level setup state  240  of the distribution and adjustment group. The high voltage level setup state  240  takes approximately 400 nanoseconds to complete. The high voltage state  242  follows the high voltage level setup state  240 . The high voltage state  242  takes approximately 100 milliseconds to complete. The setup verify state  244 , which takes approximately 5 microseconds to complete, follows the high voltage state  242 . The erase verify state  246  is the next state in the succession of cycles. The erase verify state  246  takes approximately 200 nanoseconds to complete. When complete, the operation proceeds to erase done  250 .  
         [0023]    A suspend command could come at any moment during the operation of the state machine while performing the operation. In the prior art, however, a suspend command was only acknowledged at the increment cycles  226 ,  238  of the groups. This process of “wait for a suspendable cycle” proved to have deleterious effect on response time. For example, the distribution and adjustment group  214  does not include an increment cycle, and the operation was required to proceed to erase done  250  in order to free the processor. If a suspend command was issued at the beginning of the high voltage level setup state  240  of the distribution and adjustment group  214 , the processor would wait in the 100&#39;s of milliseconds to be acted upon by the state machine.  
         [0024]    [0024]FIG. 3 shows a state machine  130  constructed in accordance with the present invention and suitable for use with memory system  100 . As indicated, the basic operation of the three groups are the same as the prior art machine. Therefore, like cycles and groups of the present state machine are indicated with reference numerals having a prime notation. The present state machine further includes a suspend cycle connected directly to each execution cycle. In the preferred embodiment, a suspend cycle is connected to execution cycles of all three groups  210 ′,  212 ′,  214 ′. Also, as indicated in the preferred embodiment, suspend cycles are connected to both execution cycles and other cycles.  
         [0025]    In the embodiment shown, a suspend cycle is connected directly to each execution cycle of the pre-program group  210 ′. A suspend high voltage state  316  is connect to cycle  216 ′. A suspend setup verify state  318  is connected to cycle  218 ′. A suspend program verify state  320  is connected to cycle  220 ′. A suspend high voltage level setup state  322  is connected to cycle  222 ′. A suspend program cleanup state  324  is connected to cycle  224 ′, which, like the above, constitutes an “other” cycle of the execution cycles in the pre-program group  210 ′. Also, a suspend increment address state  326  is connected to cycle  226 ′, which is an incremental cycle in the pre-program group  210 ′.  
         [0026]    A suspend cycle is connected to each execution cycle of the erase group  212 ′. A suspend high voltage level setup state  330  is connected to cycle  230 ′. A suspend high voltage state  332  is connected to cycle  232 ′. A suspend setup verify state  334  is connected to cycle  234 ′. A suspend erase verify state  336  is connected to cycle  236 ′, which, like the above, constitutes an “other” cycle of the execution cycles in the erase group  212 ′. Also, a suspend increment address state  338  is connected to cycle  238 ′, which is an incremental cycle in the erase group  212 ′.  
         [0027]    Finally, a suspend cycle is connected to each execution cycle of the distribution and adjustment group  214 ′. A suspend high voltage level setup cycle  340  is connected to cycle  240 ′. A suspend high voltage cycle  342  is connected to cycle  242 ′. A suspend setup verify cycle  344  is connected to cycle  244 ′. Also, a suspend erase verify cycle  346  is connected to cycle  246 ′. As described, all of the execution cycles in the distribution and adjustment group  214 ′ include “other” cycles, i.e., the distribution and adjustment group  214 ′ does not include incremental cycles.  
         [0028]    The above described state machine has many advantages. Among these include an operation which is able to suspend itself at any cycle along its loop, thereby permitting faster interrupts. Upon receiving a suspend command from the processor, a signal would go to all timing elements in a state machine, including one shots and timer circuits and timer counters, as understood by those skilled in the art. The effect of which would be to greatly reduce the inherent timing delay. For example, a timer circuit would short circuit across some capacitors or resistors for the timer, bypass any counting mechanism of the timer counter, and modify the one shots to bypass a portion of the respective timing delay.  
         [0029]    It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The invention should, therefore, be determined with reference to the appended claims, along with the full scope to which such claims are entitled.