Abstract:
The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit ( 10 ) comprising at least one input element ( 20 ) is protected by a protective circuit ( 40 ). The protective circuit ( 40 ) is operable to protect the integrated circuit ( 10 ) from damage due to electrostatic discharge and may be coupled to the input element ( 20 ). The protective circuit ( 40 ) comprises a lateral NPN transistor (T 1 ) coupled to the input element ( 20 ) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element ( 20 ). The protective circuit ( 40 ) also may comprise a lateral PNP transistor (T 2 ) coupled to the input element ( 20 ) and to the lateral NPN transistor (T 1 ). The lateral PNP transistor (T 2 ) is operable to aid in raising a potential of the base of the lateral NPN transistor (T 1 ). Alternatively, the protective circuit ( 40 ) also may use a PMOS transistor (P 1 ), or a PMOS transistor (P 1 ) in combination with the lateral NPN transistor (T 1 ), coupled to the input element ( 20 ) and to the lateral NPN transistor (T 1 ). The PMOS transistor (P 1 ) is operable to aid in raising the potential of the base of the lateral NPN transistor (T 1 ).

Description:
CROSS REFERENCE TO PRIOR APPLICATIONS 
   This is a continuation of application Ser. No. 09/546,988 filed Apr. 11, 2000 now U.S. Pat. No. 6,628,493 which claims priority under 35 USC 119(e)(1) of provisional application No. 60/129,466 filed Apr. 15, 1999. 

   TECHNICAL FIELD OF THE INVENTION 
   This invention relates generally to the field of integrated circuits and more particularly to a system and method for electrostatic discharge protection. 
   BACKGROUND OF THE INVENTION 
   Integrated circuits often employ electrostatic discharge protection to prevent damage to electronic devices during an electrostatic discharge event. Such protection may prevent damage from high voltage or current transients, including those that may occur during installation. Metal oxide semiconductor (MOS) integrated circuits are particularly vulnerable to electrostatic discharge because an electrostatic discharge event may melt the silicon or damage gate oxides and/or the short channel devices used in their design. Designing integrated circuits into deep sub-micron scale presents challenges to traditional forms of electrostatic discharge protection. 
   One prior approach used for electrostatic discharge protection employs a lateral NPN transistor formed by an n-channel MOSFET (NMOS) or field oxide device between the input pad and a substrate closely coupled to ground. The device is used to shunt to ground the large transient current caused by an electrostatic discharge event by turning on the lateral NPN when an event occurs. This approach may also utilize a vertical PNP transistor with a collector common to the substrate to trigger forward biasing of the lateral NPN transistor. When placed near the lateral NPN transistor, the vertical PNP transistor may lower the trigger voltage of the lateral NPN by raising the local substrate potential near the base of the lateral NPN transistor. 
   This prior approach may not be particularly effective in deep sub-micron products, such as those utilizing silicided CMOS technology. Silicided CMOS products generally have low substrate resistance and often encounter problems with uniform turn-on, and even failure, of the lateral NPN transistor. This approach may also not be particularly advantageous for mixed signal products, where chip capacitance is normally substantially smaller. In such products, large substrate current injection may be desirable to bias the substrate near the lateral NPN transistor. Larger circuit area, not usually available in modern sub-micron designs, may be used to achieve such current injection. Furthermore, the vertical PNP trigger may become de-biased at these chip capacitances. Therefore, a suitably-sized device resistant to de-biasing is needed to provide relatively uniform current injection into the substrate, to activate the lateral NPN transistor. 
   SUMMARY OF THE INVENTION 
   The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit comprising at least one input element is protected by a protective circuit. The protective circuit is operable to protect the integrated circuit from damage due to electrostatic discharge and may be coupled to the input element. The protective circuit comprises a lateral NPN transistor coupled to the input element and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element. The protective circuit also comprises a lateral PNP transistor coupled to the input element and to the lateral NPN transistor. The lateral PNP transistor is operable to aid in raising a potential of the base of the lateral NPN transistor. Alternatively, the protective circuit also may use a PMOS transistor, or a PMOS transistor in combination with the lateral NPN transistor, coupled to the input element and to the lateral NPN transistor. The PMOS transistor is operable to aid in raising the potential of the base of the lateral NPN transistor. 
   The invention provides several important technical advantages. The invention is particularly advantageous in providing uniform turn on of the lateral NPN transistor. The protection circuit is not subject to de-biasing at smaller chip capacitances. Thus, the invention may be used for integrated circuits utilizing silicided CMOS, mixed signal products, or other deep sub-micron or smaller technologies. The invention may also be used with larger technologies. The disclosed protection circuit does not require a large design area in order to provide electrostatic discharge protection, thus potentially conserving valuable circuit space. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in connection with the accompanying drawings in which: 
       FIG. 1  illustrates a schematic diagram of one embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. 
       FIG. 2   a  illustrates an equivalent circuit cross-section of the embodiment of FIG.  1 . 
       FIG. 2   b  illustrates a circuit cross-section of a second embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. 
       FIG. 2   c  illustrates a circuit cross-section of a third embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. 
       FIG. 3  illustrates a cross-section of a fourth embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. 
       FIG. 4  illustrates a top view of the electrostatic discharge protection circuit of FIG.  3 . 
       FIG. 5  illustrates a top view of a fifth embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention and its advantages are best understood by referring to  FIGS. 1 through 5  of the drawings, like numerals being used for like and corresponding parts of the various drawings. 
     FIG. 1  illustrates a schematic diagram of one embodiment of an electrostatic discharge protection circuit. Integrated circuit  10  comprises an input pad  20 , a protective circuit  40 , and an internal circuit  30 . Protective circuit  40  electrically couples input pad  20  to internal circuit  30  and provides protection to internal circuit  30  from damage that may be caused by transient signals resulting from an electrostatic discharge event. Although input pad  20  serves as an input element in this embodiment, any input element could be used without departing from the invention. Although direct connections are illustrated for various elements, many elements may be coupled through other elements without departing from the scope of the invention. 
   Protective circuit  40  comprises a lateral NPN transistor T 1  and a lateral PNP transistor T 2 , common to a p-type substrate closely coupled to ground. Lateral PNP transistor T 2  serves as a trigger. In this embodiment, lateral NPN transistor T 1  comprises the drain, source and channel region of an NMOS device N 1 , while lateral PNP transistor T 2  comprises the drain, source and channel region of a PMOS device P 1 . Lateral NPN transistor T 1  and lateral PNP transistor T 2  may also be formed using field oxide devices without departing from the scope of the invention. 
   Input pad  20  is coupled to internal circuit  30 , in this case by a direct connection. Input pad  20  may also be coupled to collector  43  of lateral NPN transistor T 1 , and to emitter  44  of lateral PNP transistor T 2 . Emitter  48  of lateral NPN transistor T 1  is coupled to ground. Collector  42  of lateral PNP transistor T 2  couples to base  41  of lateral NPN transistor T 1  at node  100 . Node  100  may be coupled to ground through resistance of the substrate, denoted R sub . Gate  47  of NMOS N 1  couples to ground through gate resistance R gate . This embodiment employs lateral PNP transistor T 2  with both gate  45  of PMOS P 1  and base  46  coupled to a reference voltage, denoted V cc . V cc  may be any reference voltage, such as one power supply voltage used in integrated circuit  10 . The same is true for other references to V cc  herein. Other embodiments for lateral PNP transistor T 2  may be used without departing from the scope of the invention. Lateral PNP transistor T 2  is discussed in further detail in conjunction with  FIG. 2   a.    
   In operation, protective circuit  40  protects internal circuit  30  by shunting from input pad  20  to ground excess current caused by electrostatic discharge events. Protective circuit  40  operates to limit the current provided to and voltages within internal circuit  30  to operable ranges for devices therein, such as MOSFETS. 
   Lateral NPN transistor T 1  operates as a high impedance device until an electrostatic discharge event causes a large current or voltage transient at input pad  20 . A voltage applied to input pad  20  that causes the voltage between drain  43  and the substrate to reach the junction breakdown voltage, V av  activates lateral NPN transistor T 1 . When lateral NPN transistor T 1  is activated, or turned on, by sufficient forward voltage bias V av , current flows through the substrate to ground from collector  43  to emitter  48 , creating a low impedance device. It is desirable to reduce V av , because lateral NPN transistor T 1  operates more efficiently at voltages lower than V av . 
   In this embodiment, NMOS N 1  operates to reduce the avalanche voltage, V av , required to turn on lateral NPN transistor T 1 . Capacitive coupling between input pad  20  and gate  47  of NMOS N 1  also operates to reduce the voltage required, V av , to turn on lateral NPN transistor T 1 . R gate  similarly raises the voltage of gate  47  of NMOS N 1 , thus reducing V av , and providing additional shunt current through NMOS N 1  to ground through source  48  of NMOS N 1 . Reducing avalanche voltage V av  reduces the likelihood that lateral NPN transistor T 1  will fail. Such failure in protective circuit  40  during an electrostatic discharge event could subject internal circuit  30  to potential damage. 
   Lateral PNP transistor T 2  may be used to raise the local potential of the substrate near lateral NPN transistor T 1 , in order to help activate transistor T 1 . In this embodiment, lateral PNP transistor T 2  is used to trigger current injection into the substrate. Lateral PNP transistor T 2  injects current from collector  42  to base  41  of lateral NPN transistor T 1 . This current injection increases the local substrate potential, and thus the voltage of base  41  of lateral NPN transistor T 1 . This current injection thus triggers the activation of transistor T 1  by reducing V av . 
     FIG. 2   a  illustrates an equivalent circuit cross-section of protective circuit  40  of FIG.  1 . Lateral PNP transistor T 2  may be formed by two surface, heavily positively doped (p+) diffusions  201 ,  202  in an n-well  225  which form emitter  44  and collector  42 . The base of lateral PNP transistor T 2  is connected to V cc  using n+ diffusion  204 . In this embodiment, lateral PNP transistor T 2  comprises the drain, source and channel regions of PMOS transistor P 1 , with source  44  at p+ diffusion  201  and drain  42  at p+ diffusion  202 . Lateral PNP transistor T 2  may also be formed by using a field oxide device, rather than PMOS device P 1 , without departing from the scope of the invention. Thus, gate  45  of PMOS P 1  would be replaced by an isolating oxide that would completely separate the two p+ diffusions  201 ,  202 . 
   In this embodiment, emitter  44  couples to input pad  20 . Collector  42  couples to base  41  of lateral NPN transistor T 1  at p+ diffusion  203 . Base  46  of lateral PNP transistor T 2  and gate  45  of PMOS P 1  are coupled to a power supply voltage V cc . A voltage applied across the base—emitter junction exceeding a threshold voltage of transistor T 2  will activate lateral PNP transistor T 2 , and initiate current flow to collector  42 . An embodiment using a PMOS transistor P 1  to form lateral PNP transistor T 2  will also generate PMOS current from source  44  to drain  42 , and may enhance current through collector  42 , and thus to base  41  of lateral NPN transistor T 1 . 
   Lateral PNP transistor T 2  may also be used in other embodiments without departing from the scope of the invention. For example, in another embodiment illustrated in  FIG. 2   b , the source  44  and n-well (also labeled as base  46 ) of PMOS transistor P 1  may be coupled to input pad  20 . The drain  42  may be coupled to the base  41  of lateral NPN transistor T 1 , while the Gate  45  is connected to a reference voltage such as V cc . In such an embodiment, PMOS transistor P 1  injects current into base  41  of lateral NPN transistor T 1 . Here, PMOS transistor P 1 , may trigger activation of lateral NPN transistor T 1  by supplying current to its base region. This embodiment may or may not also employ lateral PNP transistor T 2  to aid in the activation of lateral NPN transistor T 1 . 
   Another embodiment may utilize a plurality of lateral NPN transistor T 2  or PMOS transistors P 1 . In yet another embodiment, as illustrated in  FIG. 2   c , both source  44  and gate  45  of PMOS P 1  may be coupled to input pad  20 . Additional current may also be injected into the substrate by forming a vertical PNP transistor V 1  near lateral NPN transistor T 1 . A vertical PNP transistor may be formed by a lateral p-n diode using the substrate as its collector. The lateral p-n diode is coupled to input pad  20  at a p+ diffusion and to supply voltage V cc  at an n+ diffusion. Other embodiments of vertical PNP transistors may be used without departing from the scope of the invention. 
     FIG. 3  illustrates a cross-section of a fourth embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. Protective circuit  40  comprises lateral PNP transistor T 2 , lateral NPN transistor LT 1 , and substrate bias ring  60 . Substrate bias ring  60  is illustrated and discussed in further detail in conjunction with FIG.  4 . Lateral NPN transistor LT 1  comprises a plurality of lateral NPN transistors T 1   a , T 1   b , . . . , T 1   n  in parallel. 
   Substrate bias ring  60  is coupled to both lateral PNP transistor T 2  and lateral NPN transistor LT 1 . As described in conjunction with  FIGS. 1 and 2 , emitter  44  of lateral PNP transistor T 2  couples to input pad  20 , and base  46  couples to power supply voltage V cc . Collector  42  of lateral PNP transistor T 2  couples to substrate bias ring  60 , at p+ diffusion  320 . 
   Each lateral NPN transistor T 1   a , . . . , T 1   n  may be formed by two surface, heavily negatively doped (n+) diffusions. For example, lateral NPN transistor T 1   a  is formed between n+ diffusions  301 ,  302 . In this embodiment, lateral NPN transistor T 1   a  comprises the drain, source and channel regions of NMOS N 31 , with source  348  at n+ diffusion  301 , and drain  343  at n+ diffusion  302 . Collector  343  of lateral NPN transistor T 1   a  couples to input pad  20 . Emitter  348  couples to ground. Base  341  couples to ground through resistance of the p-type substrate, designated R sub . Collector  42  of lateral PNP transistor T 2  and base  341  of lateral NPN transistor T 1  are coupled to substrate bias ring  60 . Thus, collector  42  of lateral PNP transistor T 2  is coupled to each base of transistors T 1   a , . . . , T 1   n  of lateral NPN transistor LT 1 . Similarly, input pad  20  couples to each collector of transistors T 1   a , . . . , T 1   n  of lateral NPN transistor LT 1 . 
   In operation, lateral PNP transistor T 2  is used, as discussed in conjunction with  FIG. 1 , to raise the local potential of the substrate near lateral NPN transistor LT 1 , in order to activate each transistor of lateral NPN transistor LT 1 . Lateral PNP transistor T 2  is used in this embodiment to trigger current injection into the substrate. 
   Lateral NPN transistor LT 1  allows large sizes for lateral NPN transistor T 1  without constraining area or distance from input pad  20 . Because the plurality of transistors T 1   a , . . . , T 1   n  are connected in parallel, proper operation requires turn-on of all transistors T 1   a , . . . , T 1   n  before excess current causes failure of one transistor, such as T 1   a . Because deep sub-micron technologies are subject to low substrate resistance, it is desirable to ensure a relatively uniform distribution of the voltage around each transistor T 1   a , . . . , T 1   n . Relatively uniform injection can thus be applied through all lateral NPN transistors T 1   a , . . . , T 1   n , by raising the substrate potential locally near lateral NPN transistor LT 1 . Injecting hole current to raise the base voltage of lateral NPN transistor LT 1  turns on each transistor T 1   a , . . . , T 1   n without reaching hard avalanche action in the base-collector junction (or drain-substrate junction of each NMOS). Substrate bias ring  60  provides this advantage in this embodiment. 
   Lateral PNP transistor T 2  injects current from collector  42  to substrate bias ring  60 , which is coupled to each base of lateral NPN transistor LT 1 . Such current injection locally increases the substrate potential near each base of lateral NPN transistor LT 1 . This current injection into substrate bias ring  60  thus triggers the activation of each lateral NPN transistor T 1   a , . . . , T 1   n  by reducing V av . This method avoids a reliance on avalanche breakdown between each NMOS drain and substrate, which may lead one transistor such as T 1   a  to fail. It thus provides more reliable protection from electrostatic discharge events. 
     FIG. 4  illustrates a top view of the fourth embodiment of an electrostatic discharge protection circuit as illustrated in FIG.  3 .  FIG. 4  clarifies one possible placement of substrate bias ring  60  in protective circuit  40 . Protective circuit  40  comprises lateral PNP transistor T 2 , lateral NPN transistor LT 1 , and substrate bias ring  60 , as shown in FIG.  3 . In this embodiment, lateral NPN transistors T 1   a , . . . , T 1   n  comprise the drain, source and channel regions of NMOS N 31 , . . . , N 3   n.    
   Substrate bias ring  60  comprises a p+ diffusion area that surrounds lateral NPN transistor LT 1 . Substrate bias ring  60  may be placed at a distance L from both lateral NPN transistor T 1   a , and from lateral NPN transistor T 1   n . Distance L may be small to enhance the substrate bias effect, because there is no SCR structure formed in this protection scheme. Because it may be advantageous to minimize distance L, protective circuit  40  may be designed compactly. For example, one could place substrate bias ring  60  within five microns of lateral NPN transistor LT 1 . 
     FIG. 5  illustrates a top view of a fifth embodiment of an electrostatic discharge protection circuit utilizing the teachings of the present invention. Protective circuit  500  comprises lateral PNP transistor T 2 , and a plurality of lateral NPN transistors T 5   a , . . . , T 5   n  comprising the source, drain and channel regions of a plurality of NMOS transistors N 51 , . . . , N 5   n . The plurality of lateral NPN transistors T 5   a , . . . , T 5   n  are connected in parallel. Protective circuit  500  also comprises p+ diffusions  5   a , . . . ,  5   n.    
   Each of the p+ diffusions  5   a , . . . ,  5   n  may be coupled to both lateral PNP transistor T 2  and the plurality of NPN transistors T 2   a , . . . , T 2   n . As described in conjunction with  FIGS. 3 and 4 , emitter  44  of lateral PNP transistor T 2  couples to input pad  20 , and base  46  couples to power supply voltage V cc . Collector  42  of lateral PNP transistor T 2  also coupled to each of the p+ diffusions  5   a , . . . ,  5   n.    
   P+ diffusions  5   a , . . . ,  5   n  may be interspersed between each of the plurality of NPN transistors T 2   a , . . . , T 2   n  to raise the local substrate potential near each of the plurality of transistors. 
   As described in conjunction with  FIG. 3 , the source, drain and channel regions of NMOS transistors N 51 , . . . , N 5   n  forms a lateral NPN transistor. For example, a lateral NPN transistor is formed between n+ diffusions  501 ,  502 , with a source at n+ diffusion  301 , and drain at n+ diffusion  302 . A collector for each lateral NPN transistor couples to input pad  20 . An emitter couples to ground. A base couples to ground through resistance of the substrate. Collector  42  of lateral PNP transistor T 2  and the base of each lateral NPN transistor are coupled to each of the p+ diffusions  5   a , . . . ,  5   n . Similarly, input pad  20  couples to the collector of each lateral NPN transistor. 
   In operation, lateral PNP transistor T 2  is used, as discussed in conjunction with  FIG. 3 , to raise the local potential of the substrate near each of the plurality of NMOS transistors N 51 , . . . , N 5   n , in order to activate each lateral NPN transistor. Lateral NPN transistor T 2  is used in this embodiment to trigger current injection into the substrate. In this embodiment, current is injected into each of the p+ diffusions  5   a , . . . ,  5   n  between each NMOS transistors N 51 , . . . , N 5   n , rather than into substrate bias ring  60  as shown in  FIGS. 3 and 4 . 
   Although the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.