Abstract:
A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance C L , thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to electronic circuits, and more specifically to buffer circuits used for driving capacitive loads. 
   2. Description of the Related Art 
   In integrated circuits, CMOS inverters are often used as buffers to drive on-chip and off-chip capacitive loads. Typically, a single-stage buffer comprising one inverter is not sufficient to drive capacitive loads that are excessively large, so a series of gradually scaled-up stages are configured together to create a “super buffer.” While super buffers are effective in driving large capacitive loads, they are relatively complex and consequently they consume a significant amount of chip area. The teachings of Kang, et al., “CMOS Digital Integrated Circuits,” and Rabaey, “Digital Integrated Circuits,” both of which are herein incorporated by reference, discuss the operability of the super buffer design. 
   SUMMARY OF THE INVENTION 
   In one embodiment, the present invention is an apparatus that is or comprises an integrated circuit comprising a buffer having one or more buffer stages connected in series. The at least one buffer stage comprises a stage input node adapted to receive a stage input signal, a stage output node adapted to present a stage output signal, buffer circuitry connected between the stage input node and the stage output node, and at least one inductor connected between the stage output node and a voltage reference node for the buffer stage, such that the at least one inductor is adapted to reduce apparent load capacitance of circuitry connected to the stage output node. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
       FIG. 1  shows a schematic diagram of a single-stage CMOS buffer with active inductors according to one embodiment of the present invention; 
       FIG. 2  shows a schematic diagram of the small-signal model of the buffer of  FIG. 1 ; 
       FIG. 3  shows a graphical representation of the impedance versus frequency characteristics of the CMOS buffer of  FIG. 1 ; and 
       FIG. 4  shows a simplified block diagram of a representation of an apparatus  400  in which buffer  100  may be practiced. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows a schematic diagram of a single-stage CMOS buffer  100  according to one embodiment of the present invention. Buffer  100  receives input signal V IN  and generates inverted output signal V OUT . Output signal V OUT  drives capacitive loads located either on chip or off chip. 
   Buffer  100  has inverter circuitry  102 , first active inductor circuitry  104 , and second active inductor circuitry  106 . Inverter circuitry  102  includes PMOS transistor P 1  and NMOS transistor N 1  and is equivalent to a prior-art CMOS inverter. Active inductor circuitry  104  includes NMOS transistor N 2  and PMOS transistor P 2  which together act as a first inductor. Transistor N 2  of active inductor circuitry  104  operates in the triode region and thus acts as a resistor connected to the gate of transistor P 2 . Active inductor circuitry  106  includes PMOS transistor P 3  and NMOS transistor N 3  which together act as a second inductor. Like transistor N 2 , transistor P 3  also operates in the triode region and acts as a resistor connected to the gate of transistor N 3 . 
     FIG. 2  shows a schematic diagram of a small-signal model  200  of buffer  100 . Small-signal model  200  has input signal V IN  and output signal V OUT , which represent V IN  and V OUT  of  FIG. 1 . Output signal V OUT  drives the on-chip or off-chip capacitive load, which is represented by capacitor C L . 
   The various elements of buffer  100  are represented in small-signal model  200 . In particular, current source  202  represents the current flow through transistor N 1 , which is approximately input voltage V IN  times the transconductance g mN1  of transistor N 1 . Current source  204  represents the current flow through transistor P 1 , which is approximately input voltage V IN  times the transconductance g mP1  of transistor P 1 . Current source  206  represents the current flow through transistor N 3  which is approximately the gate-to-source voltage V gsN3  of transistor N 3  times the transconductance g mN3  of transistor N 3 . Current source  208  represents the current flow through transistor P 2 , which is approximately the gate-to-source voltage V gsP2  of transistor P 2  times the transconductance g mP2  of transistor P 2 . Transconductance g 0  is equal to the total channel transconductance of transistors P 1 , N 1 , P 2 , and N 3 . 
   As shown in  FIG. 1  and as described above, transistors N 2  and P 3  act as resistors and are connected to the gates of transistors P 2  and N 3 , respectively. In small-signal model  200 , resistor R N2  represents the equivalent channel resistance of transistor N 2 . Resistor R N2  is connected in series with capacitor C gsP2 , which is representative of the gate-to-source capacitance of transistor P 2 . Similarly, resistor R P3  is representative of the channel resistance of transistor P 3 . Resistor R P3  is connected in series with capacitor C gsN3 , which is representative of the gate-to-source capacitance of transistor N 3 . 
   Suppose that the properties of transistors N 2  and P 3  are chosen such that the values of R N2 C gsP2  and R P3 C gsN3  are equal and may each be represented by RC gs . Furthermore, suppose that transistors N 1  and P 1  are chosen such that the transconductance g mN1  and the transconductance g mP1  are equal and may each be represented by g m . The Laplace-domain transfer function of the small-signal model may then be characterized by equation (1) as follows: 
   
     
       
         
           
             
               
                 
                   
                     
                       
                         
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   From equation (1), it can be shown that a low frequency zero of the transfer function is generated by active inductor circuitry  104  and also by active inductor circuitry  106 . More specifically, the low frequency zero is generated due to the series connection of the equivalent channel resistance R of transistors N 2  and P 3  to the corresponding gate-to-source capacitance C gs  of transistors P 2  and N 3 . At this low frequency zero, the impedance Z IN  of each branch of active inductor circuitry  104  and  106  is inductive and so active inductor circuitry  104  and  106  each behave as inductors for relatively small signals. This inductance boosts the high frequency components of output signal V OUT , thereby, compensating for the high frequency loss caused by load capacitance C L . Thus the inductance of active inductor circuitry  104  and  106  partially tunes out load capacitance C L . In tuning out load capacitance C L , active inductor circuitry  104  and  106  both reduce the signal propagation delay of inverter  102  and, therefore, improve the charging capability of inverter  102 . 
   Compared to a multiple-stage super buffer designed to drive a given, relatively large capacitive load, the present invention can be used to implement buffer circuitry, capable of driving the same capacitive load and based on the same transistor technology (i.e., the same transistors for N 1  and P 1 ), using fewer stages, including possibly just a single stage. Since the present invention uses fewer stages, it has the additional advantage of consuming less power than the comparable multi-stage super buffer. Moreover, buffer circuitry implemented using the present invention, which has the same number of stages and which is based on the same transistor technology as a prior-art single-stage buffer or prior-art multiple-stage super buffer is capable of 1) driving the same capacitive load as the prior-art single-stage buffer or prior-art multiple-stage super buffer at quicker charging and discharging rates (e.g., smaller signal propagation delay); and 2) driving a larger capacitive load than the prior-art single-stage buffer or prior-art multiple-stage super buffer. 
     FIG. 3  shows a graphical representation of the impedance Z IN  versus frequency characteristics of each inductor  104  and  106 . In addition to zero Z 1 , the transfer function also has two poles P 1  and P 2  that result from the quadratic equation in the denominator. Poles P 1  and P 2  and zero Z 1  are shown in  FIG. 3 . As the frequency increases from zero Z 1  to pole P 1 , the impedance Z IN  also increases. The zero introduced by the active inductors alters the effect of the pole caused by C L  thus extending the −3 dB bandwidth of inverter  102  to a higher frequency. 
   The present invention has been described using active inductors, namely active inductor circuitry  104  and  106 . Compared to on-chip passive spiral inductors, active inductors use only MOS devices so they consume much smaller chip areas. In addition to chip area, on-chip spiral inductors often require excess area around the inductor to prevent interference (e.g., eddy currents) with other structures. Due to the relatively large area consumed by on-chip spiral inductors, the use of active inductors in integrated circuits is preferred over on-chip spiral inductors. Although the use of active inductors is preferred, passive inductors are not precluded from use in this invention. As such, passive inductors may be used in place of active inductors  104  and  106 . 
   Alternative embodiments of the present invention may be envisioned, which have one or more stages. For example, in one implementation, buffer  100  may be the last stage after a series of conventional CMOS logic circuits. Buffer  100  may also be one stage linking two or more conventional CMOS logic circuits. Furthermore, multiple instances of buffer  100  may be linked together to create one multiple-stage buffer. 
   Further embodiments of the present invention may be envisioned, in which buffer  100  is modified to have one inductor only or more than two inductors. 
   Although the present invention has been described as being implemented using silicone CMOS transistor technology, the present invention can also be implemented using other transistor technologies, such as bipolar or other integrated circuit (IC) technologies such as GaAs, InP, GaN, and SiGe IC technologies. 
   It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. For example, PMOS transistors may be interchanged with NMOS transistors and NMOS transistors may be interchanged with PMOS transistors. Furthermore, the present invention may be implemented using buffer circuitry other than the voltage-mode static CMOS inverter  102 , such as voltage-mode dynamic logic circuits, or current-mode logic (CML) circuits. 
   Buffers of the present invention can be implemented in a wide variety of different types of circuitry, any of which require the driving of a capacitive load. Moreover, circuits embodying buffers of the present invention can be implemented in a wide variety of applications, including any suitable consumer product or other suitable apparatus. The number and types of apparatuses in which the buffer of the present invention may be used is immeasurable. 
     FIG. 4  shows a simplified block diagram of a representation of an apparatus  400  in which buffer  100  may be practiced. As shown in  FIG. 4 , in addition to buffer  100 , apparatus  400  comprises at least one of upstream circuitry  402  and downstream circuitry  404 , either of which may be located on chip or off chip. For example, in one possible implementation where apparatus  400  includes microprocessor circuitry including buffer  100 , upstream circuitry  402  may be any circuitry necessary to generate a clock signal. Buffer  100  may then be used to drive the clock signal to on-chip, downstream circuitry  404 , which may include a plurality of on-chip circuits, each performing separate functions. As another example, upstream circuitry  402  and/or downstream circuitry  404  may comprise one or more additional buffer stages  403 ,  405  that are connected to buffer  100 . For instance, as described above, embodiments of the present invention may be envisioned in which buffer  100  is the last stage after a series of conventional CMOS logic circuits  403 . The series of conventional CMOS logic circuits  403  may be embodied in upstream circuitry  402 . In other embodiments, buffer  100  may be one stage linking two or more conventional CMOS logic circuits  403 ,  405 . The two or more conventional CMOS logic circuits  403 ,  405  may be embodied in upstream circuitry  402  and/or downstream circuitry  404 . In yet further embodiments, multiple instances  403 ,  405  of buffer  100  may be linked together to create one multiple-stage buffer. The multiple instances  403 ,  405  of buffer  100  may be embodied in upstream circuitry  402  and/or downstream circuitry  404 . 
   Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. 
   The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
   It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the present invention. 
   Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. 
   Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”