Abstract:
A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.

Description:
BACKGROUND 
       [0001]    The present invention is directed to semiconductor devices and lead frames for semiconductor devices, and more particularly to compact lead frame based semiconductor package. 
         [0002]    Power devices, such as power MOSFETs, require high performance thermal capacity and heat dissipation because they are required to drain unwanted large currents to ground or other rails to protect devices connected thereto from being damaged. On the other hand, the power devices face challenges from structural compactness, which requires them to have a very small footprint and package height. 
         [0003]    It is an object of the present invention to provide a lead frame based, compact, yet thermally efficient semiconductor package. 
       SUMMARY OF THE INVENTION 
       [0004]    This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
         [0005]    In one embodiment, the present invention provides a semiconductor device, comprising a semiconductor die having a first side and an opposite second side, the semiconductor die comprising a first terminal on the first side and at least two second terminals on the second side, and a lead frame. The lead frame comprises first and second base parts that are mutually spaced from each other both electrically and mechanically, wherein the second side of the semiconductor die is mounted to the lead frame such that the at least two second terminals are electrically connected, respectively, to the first and second base parts. The lead frame further comprises first and second protrusions on the first and second base parts that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the semiconductor die. 
         [0006]    In another embodiment, the present invention provides a semiconductor device, comprising a semiconductor die having a first terminal on a first side and at least two second terminals on an opposite second side, and a lead frame having first and second parts. Each of the first and second parts comprises a base and a protrusion. The protrusions are respectively connected to and protrude from first sides of the bases. A height of the protrusions is substantially equal to a thickness of the semiconductor die, such that when the semiconductor die is mounted on the lead frame with the second side of the die facing the bases of the first and second parts of the lead frame, then the first side of the die is co-planar with distal ends of the protrusions. 
         [0007]    The present invention further provides a lead frame for a semiconductor device. The lead frame comprises a first part including a first branch and a second branch, wherein the second branch is connected to and extends from the first branch. The lead frame also includes a second part having a third branch and a fourth branch, wherein the fourth branch is connected to and extends from the third branch. A first connection bar connects the first branch of the first part to the third branch of the second part of a neighboring lead frame when the lead frame is part of a matrix of lead frames. A second connection bar connects the first branch of the first part to the second and fourth branches respectively of the first and second parts of another neighboring lead frame. The second branch of the first part and the fourth branch of the second part extend in the same direction and to the same height. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. The drawings are for facilitating an understanding of the invention and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which like reference numerals have been used to designate like elements, and in which: 
           [0009]      FIG. 1  is a perspective view of a semiconductor device in accordance with an embodiment of the present invention; 
           [0010]      FIG. 2A  is a top plan view of a semiconductor die of the device of  FIG. 1 ; 
           [0011]      FIG. 2B  is side view the semiconductor die of  FIG. 2A ; 
           [0012]      FIG. 2C  is a bottom plan view of the semiconductor die of  FIG. 2A ; 
           [0013]      FIG. 3  is a perspective view of a lead frame of the semiconductor device of  FIG. 1 ; 
           [0014]      FIGS. 4A-4E  are perspective views illustrating steps for assembling the semiconductor device of  FIG. 1 ; 
           [0015]      FIG. 5A  is a perspective view of an obtained semiconductor device after singulation; 
           [0016]      FIG. 5B  is a bottom plan view of the semiconductor device of  FIG. 5A , seeing from the bottom surface; 
           [0017]      FIG. 5C  is a perspective view of an obtained semiconductor device after grinding and singulation; 
           [0018]      FIG. 6A  shows sectional lines on the semiconductor device of  FIG. 1 ; and 
           [0019]      FIGS. 6B-6D  are cross-sectional views of the semiconductor device along respective sectional lines of  FIG. 6A . 
       
    
    
     DETAILED DESCRIPTION 
       [0020]      FIG. 1  is a perspective view of a semiconductor device  30  in accordance with an embodiment. The semiconductor device  30  has a top surface  302  and an opposing bottom surface  304 . On the bottom surface  304 , the semiconductor device  304  includes multiple contacts  306 ,  308 , and  310 . The contacts  306 ,  308 , and  310  are used for electrically connecting the semiconductor device  30  to external circuit components, such as a printed circuit board (PCB). In the embodiment shown, the first contact  306  is exposed only on the bottom surface  304 , while the second and third contacts  308 ,  310  extend from the bottom surface  304  to a lateral side wall  312  of the semiconductor device  30  where they also are exposed. 
         [0021]    The first contact  306  is provided on a conductive surface of a semiconductor die of the semiconductor device  30 , while the second and the third contacts  308 ,  310  are provided by a conductive lead frame to which the die is mounted and electrically connected. In one example embodiment, the semiconductor die is a VDMOS, and the first contact  306  is connected to a drain of the VDMOS, and the second and third contacts  308 ,  310  are respectively connected to a source and a gate of the VDMOS. The semiconductor device  30  may be square or rectangular in shape, with a side length of  0 . 6 mm, and a thickness of  0 . 4 mm. In other embodiments, the semiconductor die can be provided as BJT, thyristor, etc. 
         [0022]    Referring to  FIGS. 2A and 2B , a top plan view and a side view of a semiconductor die  32  of the semiconductor device  30  are illustrated. The semiconductor die  32  is generally rectangular shaped. A major portion on a first surface  322  is provided as a first terminal  324 , and the other portion on the first surface  322  is provided as a second terminal  326 . As discussed below, on an opposite second surface of the semiconductor die  32 , a third terminal is provided. When packaged (see  FIG. 1 ), the first and second terminals  324  and  326  provide the contacts  310  and  308 , while the third terminal provides the contact  306 . The relative proportion of the first terminal  324  and the second terminal  326  is not limited to that illustrated in  FIG. 2A . For example, in another embodiment, the second terminal  326  may have an area equal to or larger than that of the first terminal  324 . To meet the size specification of example semiconductor device  30 , discussed above, a length of the semiconductor die  32  is 0.5 mm, and a width is 0.275 mm. 
         [0023]    In one embodiment, studs  328  are disposed on the first surface  322 . As illustrated in  FIG. 2B , the studs  328  are placed on top of the first surface  322 , and with predetermined heights. In compliance with the device thickness as in  FIG. 1 , the height of the studs  328  can be 30 μm, while the thickness of the semiconductor die  32  can be 145 μm. A left bottom stud serves as the second terminal, while the other studs serve as the first terminal. In the example of a VDMOS, the left bottom stud can be connected to the gate of the VDMOS, while the other studs connected to the source of the VDMOS. It shall be the appreciation of any skilled person that, the studs  328  can have any other suitable arrangements, and can be made of any suitable material, such as Cu. Furthermore, not all the studs are needed to be conductive. As mentioned above, on a second surface  330  of the semiconductor die  32  opposite to the first surface  322 , a third terminal  332  is provided, for example made of CuSn. As previously presented, in the example that the semiconductor die  32  is a VDMOS, the third terminal  332  can be connected to the drain thereof. In other available embodiments, the semiconductor die can be provided as BJT, thyristor, etc. 
         [0024]      FIG. 3  is a perspective view of a unit of a lead frame matrix in accordance with an exemplary embodiment. The lead frame  34  includes a first part  342  and a second part  344 . The first part  342  is distinguished and spaced apart from the second part  344 . Each of the first part  342  and the second part  344  includes a first branch and a second branch. The first branch  346  of the first part  342  is substantially flat. The second branch  348  of the first part  342  is connected to an edge of the first branch  346 , and extends from the first branch  346  to be substantially perpendicular to the first branch  346 . The first branch  350  of the second part  344  is co-planar with the first branch  346  of the first part  342 . The second branch  352  is connected to an edge of the first branch  350  in the same direction as that of the edge of the first branch  346  of the first part  342 . The second branch  352  extends from the first branch  350  to be substantially perpendicular to the first branch  350 . The second branches  348  and  352  protrude from the first branches  346  and  350  in a same direction, and to a similar extent of height. In this way, the second branch  352  of the second part  344  is aligned with the second branch  348  of the first part  342 . Preferably, the second branches  348  and  352  have a same height of extension from the respective co-planar first branches  346  and  350 . 
         [0025]    Each part  342 ,  344  of the lead frame  34  is thereby provided to be including a base (first branch) and a protrusion (second branch) which connects to the base and protrudes from a first side of the base. The base of the first part  342  and the second base  344  are co-planar, collectively for receiving the semiconductor die  32  to be placed on the first side. A first side of the semiconductor die  32  is placed to face the first side of the first part  342  and the second part  344 , while an opposite second side of the semiconductor die  32  is accordant to the ends of the protrusions. 
         [0026]    In assembly, the first part  342  and the second part  344  are respectively used for receiving and connecting to the first terminal  324  and the second terminal  326  of the semiconductor die  32 . In which situation, the space between the first part  342  and the second part  344 , as well as the sizes of the first part  342  and the second part  344 , are adapted to be, in total, substantially similar to the size of the semiconductor die  32 . Specifically, a width d from an edge of the first part  342  to an opposite edge of the second part  344  is generally equal to the width of the semiconductor die. 
         [0027]    With reference to  FIG. 2A  and  FIG. 2B , in assembly, the first surface  322  of the semiconductor die  32  is placed facing the lead frame  34 . The studs  328  of the first terminal  324  are connected to the first part  342 , in particular, to the first branch  346  of the first part  342 . The stud  328  of the second terminal  326  is connected to the second part  344 , in particular, to the first branch  350  of the second part  344 . For providing a corresponding space for receiving the first terminal  324  and the second terminal  326 , the proportion between the first branch  346  of the first part  342  and the first branch  350  of the second part  344  is approximated to that between the first terminal  324  and the second terminal  326  of the semiconductor die  32 . Furthermore, the area of the first branch  346  of the first part  342  is at least as large as the area of the first terminal  324 . Similarly, the area of the first branch  350  of the second part  344  is at least as large as the area of the second terminal  326 . 
         [0028]    It can hereby be understood that, the arrangement of the first branches  346 ,  350  can be adapted to be correspondent to the arrangement of the first terminal  324  and the second terminal  326 . Since the connections to the first and second terminals  324 ,  326  are guided to the second branches  348 ,  352 , the footprint of the final package can be kept uniform for variable forms of semiconductor dies  32  by making necessary adaptions to the lead frame  34 . The embodiment makes it possible to harmonize the compatibility between the package device and the PCB. For example, the PCB, especially the soldering pads for receiving and connecting to the package device, may not be necessarily modified in the situation that the first and second terminals of the semiconductor die are changed. 
         [0029]    The extent that the second branches  348 ,  352  protrude from the first branches  346 ,  350  can be such that, after the semiconductor die  32  is mounted/packaged onto the lead frame  34 , the second surface  330  is generally co-planar with the distal ends of the second branches  348 ,  352 . In such, the third terminal  332  is able to be in the same plane with electrical extensions of the first and second terminals  324 ,  326 . It can be understood that the lead frame  34  may be provided through known arts, like punching, etching, molding, etc. Each of the second branches  348 ,  352  preferably protrudes to have a length which is at least twice the thickness of the corresponding branches  346 ,  350 . In an example that the lead frame  34  is made through etching, normally a piece of material is etched for obtaining first branches  346 ,  350  that are recessed with reference to the second branches  348 ,  352 . The first branches  346 ,  350  are etched to exceed half of the thickness of the piece of material. 
         [0030]    After the semiconductor die  32  and the lead frame  34  are encapsulated and singulated, the third terminal  332  and the distal ends of the protruding second branches  348 ,  352  are exposed for providing a no-lead package device as shown in  FIG. 1 . The third terminal  332  is thereby provided as the first contact  306  of the semiconductor device  30 , the second branches  348  and  352  are provided as the third and second contacts  310  and  308 . Particularly, after the encapsulation, one side of the protrusions of the second branches  348  and  352  are exposed as well. This exposed side, together with the distal end of the second branches  348  and  352 , will be provided as the third and second contacts  310  and  308 , which extends from the bottom surface  304  of the semiconductor device  30  to a side wall  312  thereof. 
         [0031]    Referring still to  FIG. 3 , unlike the proportional arrangement of the first branches  346 ,  350  in correspondence with the first terminal  324  and the second terminal  326 , the second branches  348  and  352  can be configured to mutually have similar sizes, which may save space required for the semiconductor device  30  to provide the second contact  308  and the third contact  310 . The first terminal  324  and the second terminal  326  are electrically introduced along the first part  342  and the second part  344  of the lead frame  34 , to be provided through third contact  310  and the second contact  308  for external links. The reliability of the electrical connection to the semiconductor die  32  can be enhanced. 
         [0032]    According to an exemplary embodiment, active regions of the semiconductor die  32  are located on the side of the first surface  322 , the direct contact between the first surface  322  and the lead frame  34  will be advantageous for effectively dissipating heat generated by the active regions in a quickly and complete manner. This is especially useful for applications in which power peaks are needed to be dissipated. For this the heat capacity as build by the lead frame is of advantage. 
         [0033]    Generally, the semiconductor die  32  generates heat during operation, which will increase the temperature within the semiconductor die  32 . Considering necessary connections that dissipates the generated heat, the temperature within the die is determined by the heat resistance of the total set-up, including the package and the connected PCB. Transient pulse length is in such a range that the heat diffuses a few hundred microns. Such short pulses like ESD produce only local heating near the active junctions. In ESD applications, cooling with dissipating materials outside the package has limited effect. 
         [0034]    The semiconductor die  32  can be placed such that the active part of the die is finally soldered to a board. However, the cooling depends heavily on the board layout and board properties—parameter that depend on technology choices. Consequently, the actual robustness of the die cannot be predicted. 
         [0035]    According to an exemplary embodiment, the semiconductor die  32  is placed with the active side towards the lead frame. The cooling and the robustness are comparably better and more predictable. The robustness of the die in the application becomes independent (or at least less dependent) from the board layout and board properties. In such configuration the active side is adjacent to adequate heat dissipation material, allowing as low as possible heat resistance between the active side and the lead frame. 
         [0036]    It shall also be mentioned that,  FIG. 3  illustrates an exemplary embodiment of the unit of the lead frame with first and second parts  342 ,  344 , but it&#39;s not intended to limit the lead frame. In other embodiments, for connecting and receiving semiconductor dies with other layouts, the lead frame alternatively can have only one part, or more parts. Each part includes first and second branches as those in  FIG. 3 , and allows the active region of the semiconductor die to be placed facing the first branch. 
         [0037]      FIG. 4A  is a perspective view of multiple lead frames provided in a matrix. As known, the lead frame is manufactured through mass production before the semiconductor dies are applied thereon. In the matrix shown in  FIG. 4A , the lead frame units are connected with neighboring lead frame units. The connection between the lead frame units are rigid, so that the first and second parts are with predetermined assembly positions. Since the lead frame as shown in  FIG. 3  includes dis-connected first and second parts, the rigid connection in  FIG. 4A  between each lead frame units can eliminate assembling the first and second parts in place before applying semiconductor dies thereon. 
         [0038]    With reference to  FIG. 3 , the first part  342  of each lead frame unit  34  includes a first connection bar  354  at one side, the first connection bar  354  is used for connecting the first part  342  of the current lead frame unit  34  to the second part of a neighboring lead frame unit. At another side of the first part  342 , second connection bars  356  are provided to connect the first part  342  of the current lead frame unit  34  to respectively the first part and the second part of a neighboring lead frame unit. More specifically, the first and second connection bars  354 ,  356  are provided on the first branch  346  of the first part  342 . The first connection bar  354  connects the first branch  346  of the first part  342  of the current lead frame unit  34  and the first branch  350  of the second part of the neighboring lead frame unit. One of the second connection bars  356  connects the first branch  346  of the first part  342  of the current lead frame unit  34  and the second branch of the first part of another neighboring lead frame unit; while another second connection bar  356  connects the first branch  346  of the first part  342  of the current lead frame unit  34  and the second branch of the second part of the another neighboring lead frame unit. The one of the second connection  356  is connected to a sidewall of the second branch of the second part of the neighboring lead frame unit, which sidewall is the side of the protrusion of the second branch to be exposed after the encapsulation and singulation. 
         [0039]      FIG. 4B  through  FIG. 4E  and  FIGS. 5A-5C  are illustrative views of assemblies during packaging a semiconductor device according to exemplary embodiments. For packaging a semiconductor device, a semiconductor die and a corresponding lead frame are provided. It will be described hereafter with reference to the semiconductor die as shown in  FIG. 2A  through  FIG. 2C , and the lead frame as shown in  FIG. 3  and  FIG. 4A . The semiconductor die is attached to the lead frame through any suitable connection material, for example solder, glue, or adhesive. In particular applications, the connection material can be selected as conductive material, thereby providing electrical connection between the terminals of the device and the respective parts of the lead frame. The semiconductor die can be applied to the lead frame through various techniques, such as die bonding, etc. See  FIG. 4B  and with reference to  FIG. 2A-2C  and  FIG. 3 , the semiconductor die  32  is placed on the lead frame  34  with its first surface  322  facing the lead frame, and terminals  324 ,  326  connected to corresponding part of the lead frame respectively. After all semiconductor dies are placed, the assembly might be necessary to go through a reflow process, for soldering the semiconductor dies and the lead frame. 
         [0040]    The assembly of the semiconductor dies and the lead frame is molded using various applicable molding compounds, e.g. epoxy. The molded assembly is shown in  FIG. 4C . The molding compound may cover the assembly while leaving the second surface  330  and the third terminal  332  of the semiconductor die  32 , and the distal ends of the protrusion of the second branches  348 ,  352  exposed. As described previously, the second surface  330  and the distal ends of the protrusion of the second branches  348 ,  352  are co-planar. 
         [0041]    Referring to  FIG. 4D  and  FIG. 4E , according to an optional embodiment, the molded assembly is grinded in the back in order to minimize the overall thickness of the final semiconductor device. As described above, the molding compound may cover the whole assembly, leaving only the second surface  330  and the distal ends of the protrusions exposed. It is thereby possible to remove the molding compound that covers the back of the assembly, i.e. at its side of the lead frame. It can be seen from  FIG. 4E  and  FIG. 4C  that, after grinding, a back side of the lead frame which is opposite to the side that the second branches  348 ,  352  are protruded is exposed. The grinding of the back side can allow the package size to be more compact because the thickness of the obtained semiconductor device is reduced. Furthermore, since the lead frame is exposed both from the front side at the protrusions and from the back side at the bases of the first part and the second part, the heat generated by the semiconductor die, especially when operating under power pulses where transient voltages where heat generation is ultra-high, can be more efficiently conducted and dissipated. 
         [0042]    Singulation is followed to cut the molded (and optionally back-grinded) assembly into separate semiconductor device packages. Referring to  FIG. 1 , and with reference to  FIG. 4D  and  FIG. 4E , singulation is carried along the sidewall of the second branches facing the neighboring lead frame, and along the lane between neighboring lead frames where first connection bars  354  are located. During singulation, the molding compound between neighboring lead frames are removed, and connection bars  354 ,  356  are cut and removed.  FIG. 5A  is a perspective view of an obtained semiconductor device after singulation, from another aspect apart from that of  FIG. 1 . 
         [0043]      FIG. 5B  is a bottom view of the semiconductor device, seeing from the bottom surface  304  of the semiconductor device  30 . The connection bars  354  and  356  are cut away during singulation, leaving sections thereof exposed on the sidewalls of the semiconductor device  30 . On the top surface  302  of the semiconductor device  30 , the back surface of the base of the lead frame  34  is exposed. In application, when the semiconductor device  30  is mounted to an external circuit, e.g. a PCB, the exposed lead frame will function as additional heat sink for the semiconductor device  30 .  FIG. 5C  is a perspective view of an obtained semiconductor device after grinding and singulation. 
         [0044]    Cross-sectional views of the semiconductor device  30  along the sectional lines as in  FIG. 1  are described below with reference to  FIG. 6A-6D . See  FIG. 6A , second branches  348 ,  352  are shown. In  FIG. 6B , cross-sections of the first branches  346 ,  350 , and the semiconductor die  32  are illustrated.  FIG. 6C  illustrates the cross-sectional view of the first part  342  of the lead frame  34 , and the semiconductor die  32  placing on the lead frame  34 , with first branch  346  and second branch  348  of the first part  342  being depicted as well.  FIG. 6D  shows the cross-sectional view of the first and second branches  350 ,  352  of the second part  344 , the semiconductor die  32 , and the first branch  346  of the first part  342 . 
         [0045]    The semiconductor device and the lead frame allow the semiconductor die to have multiple contacts to be connected, while maintaining a more compact structure with constrained package size and thickness. The terminals at the active region side of the semiconductor die are connected through the lead frame to be co-planar with the terminal at the passive region side, which enables a no-lead package. The exposure of the protrusions on the sidewall of the semiconductor device further allows the semiconductor device to be side wettable during connection with external circuits like a PCB, which can improve the robustness of both mechanical and electrical connections. 
         [0046]    The use of the terms “a” and “an” and “the” and similar referents in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof entitled to. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed. 
         [0047]    Preferred embodiments are described herein, including the best mode known to the inventor for carrying out the claimed subject matter. Of course, variations of those preferred embodiments will become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventor expects skilled artisans to employ such variations as appropriate, and the inventor intends for the claimed subject matter to be practiced otherwise than as specifically described herein. Accordingly, this claimed subject matter includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed unless otherwise indicated herein or otherwise clearly contradicted by context.