Abstract:
An input voltage range may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone (“safe zone”) of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to integrated circuit devices having programmable non-volatile memory, and more particularly, to programmable non-volatile memory capable of temporary and permanent write protection. 
       BACKGROUND 
       [0002]    Integrated circuit devices having non-volatile memory may store operating parameters of the device, operating programs and/or fixed data in the non-volatile memory. The non-volatile memory may be write protected so as to prevent unauthorized and/or inadvertent changes to the contents therein. A number of means are available to write-protect non-volatile memory and are collectively referred to herein as “write-protect fuses.” Two types of write-protect fuses may be implemented with a non-volatile memory, a) a temporary write-protect fuse that allows a user clear function (disable write-protection), and b) a permanent write-protect fuse that permanently places the non-volatile memory in a write-protected mode without the user being able to clear the permanent write-protect. Thus once a device has been programmed and permanently write-protected, the device program cannot be altered thereafter. 
         [0003]    Typically, an integrated circuit device will have a multi-function pin (external connection) that may be utilized for either normal operation of the integrated circuit or programming operations thereto. The multi-function pin may be further characterized as requiring different voltage levels, e.g., use of a higher voltage then the operating voltage to perform a semi-permanent or permanent programming operation. 
         [0004]    According to the JEDEC Solid State Technology Association Specification for Serial Presence Detection (SPD) electrically erasable and programmable read only memory (EEPROM), when attempting to program a temporary write-protect fuse using the SWP (software write protect) command, if a high voltage, VHV, on the A0 address pin of the device is not at a high enough voltage for completing the temporary write-protection (SWP) command, then the device will have its permanent write-protect fuse set, e.g., execute the permanent software write protect (PSWP) command instead. This results in the device being permanently write-protected, and would require the device to be physically replaced if a program change and/or correction had to be implemented thereto. 
         [0005]    Referring to  FIG. 5 , depicted is a table of voltages and logic levels associated with a prior technology external multifunction input-output connection used to perform temporary write-protection (SWP) and permanent software write protect (PSWP) commands. When attempting to program a temporary write protection (fuse) using the SWP command, if the VHV level applied to the A0 input connection is insufficient, the integrated circuit device will inadvertently program the permanent write protection (fuse), i.e., execute the PSWP command instead. This renders the integrated circuit device permanently write protected. 
       SUMMARY 
       [0006]    Therefore, a need exists to prevent an undesired programming operation, e.g., permanent write protect, occurring inadvertently due to marginal voltage tolerances of the various programming functions. According to the teachings of this disclosure, a range, e.g., “window,” may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone (“safe zone”) of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection. 
         [0007]    According to a specific example embodiment of this disclosure, an integrated circuit device having a nonvolatile programmable memory comprises: nonvolatile memory; memory control and programming logic coupled to the nonvolatile memory and adapted for writing data to the nonvolatile memory; at least one multifunction input connection coupled to the memory control and programming logic, wherein the at least one multifunction input is used to enable write protection of the data written to the nonvolatile memory; wherein the write protection comprises permanent write protection when a voltage on the at least one multifunction input is less than a first voltage value, and temporary write protection when the voltage on the at least one multifunction input is greater than a second voltage value, the second voltage value being greater than the first voltage value; and wherein the write protection cannot be enabled when the voltage on the at least one multifunction input is equal to or greater than the first voltage value and less than or equal to the second voltage value. 
         [0008]    According to another specific example embodiment of this disclosure, a method for preventing unintended permanent write-protection of a nonvolatile programmable memory in an integrated circuit device comprises: comparing a voltage on an input of a multifunction input connection of an integrated circuit device to first and second voltage values, wherein the second voltage value is greater than the first voltage value; if the voltage on the input of the multifunction input connection is less than the first voltage value, then allow permanent write protection of a programmable memory in the integrated circuit device; if the voltage on the input of the multifunction input connection is greater than the second voltage value, then allow temporary write protection of the programmable memory in the integrated circuit device; and if the voltage on the input of the multifunction input connection is equal to or greater than the first voltage value and less then or equal to the second voltage, then do not allow write protection of the programmable memory. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein: 
           [0010]      FIG. 1  is a schematic block diagram of an integrated circuit device having at least one external multifunction input-output connection on an integrated circuit package; 
           [0011]      FIG. 2  is a schematic diagram of a logic circuit for implementing a non-operational window for the at least one external multifunction connection, according to a specific example embodiment of this disclosure; 
           [0012]      FIG. 3  are tables of relationships of various voltage level inputs and logic outputs of the circuit shown in  FIG. 2 , according to the teachings of this disclosure; 
           [0013]      FIG. 4  is a table of voltages and logic levels associated with the integrated circuit device of  FIG. 1  and the circuit shown in  FIG. 2 , according to the teachings of this disclosure; and 
           [0014]      FIG. 5  is a table of voltages and logic levels associated with a prior technology external multifunction input-output connection used to perform temporary write-protection (SWP) and permanent software write protect (PSWP) commands. 
       
    
    
       [0015]    While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0016]    Referring now to the drawing, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. 
         [0017]    Referring to  FIG. 1 , depicted is a schematic block diagram of an integrated circuit device having at least one external multifunction input-output connection on an integrated circuit package. The integrated circuit device  102  comprises memory control and programming logic  104 , a nonvolatile memory  106 , and external connections, e.g., connections  114  and  120  et al. At least one of the external connections, e.g., connection  120   c , may be a multifunction input, output or input-output connection. According to the teachings of this disclosure, the at least one multifunction connection may have primary and secondary functions, such as, for example but not limited to, an address selection input(s) (primary); and nonvolatile memory write protection, both temporary and permanent (secondary), e.g., for setting “fuses” for erasable and non-erasable protection of the program contents of the nonvolatile memory  106 . 
         [0018]    The integrated circuit device  102  may further comprises a digital processor  108 , digital circuits  110 , and/or analog circuits  112 . External input and/or output connections  116  and  118  are coupled to the digital circuits  110  and analog circuits  112 , respectively. 
         [0019]    Referring to  FIG. 2 , depicted is a schematic diagram of a logic circuit for implementing a non-operational window for the at least one external multifunction connection, according to a specific example embodiment of this disclosure. The external connections  114 ,  120   a ,  12   b  and  120   c  have a secondary function that may be used in conjunction with programming and write protecting the programmed nonvolatile memory  106 . The combinatorial logic gates  204 - 216  are representative of one specific example embodiment, according to the teachings of this disclosure, and it is contemplated and within the scope of this disclosure that any logic design may be used as would be readily apparent to one having ordinary skill in digital logic design and the benefit of this disclosure. 
         [0020]    Referring to  FIG. 3 , depicted are tables of relationships of various voltage level inputs and logic outputs of the circuit shown in  FIG. 2 , according to the teachings of this disclosure. Disclosed for illustrative purposes are voltage values VIH, min=0.7*Vdd; VIL, max=0.3*Vdd; VIH, max=Vdd+0.5 volts; VHH, min=7 volts; and Vdd is the power source voltage. It is contemplated and within the scope of this disclosure that other voltage values and their relationships may be used and be within the scope and intent of this disclosure. 
         [0021]    In Table 3(a) when the hv_en signal line  222  is at a logic “0,” the out_hv signal line  220  is always at a logic “0” for all voltage values applied to the multifunction A0 input (connection  120   c ). The out_lv signal line  218  follows the in_lv signal line  228  as being at a logic “1” when the voltage on the multifunction A0 input (connection  120   c ) is greater than or equal to VIH, min; and at a logic “0” when the voltage on the multifunction A0 input (connection  120   c ) is less than or equal to VIL, max. 
         [0022]    In Table 3(b) when the hv_en signal line  222  is at a logic “1,” the in_lv signal line  228  is at a logic “1” when the voltage on the multifunction A0 input (connection  120   c ) is greater than or equal to VIH, min; and at a logic “0” when the voltage on the multifunction A0 input (connection  120   c ) is less than or equal to VIL, max. The in_sz (safe zone) signal line  226  will be at a logic “1” when the voltage on the multifunction A0 input (connection  120   c ) is less than VIH, max, and at a logic “0” when the voltage on the multifunction A0 input (connection  120   c ) is greater than or equal to VIH, max. The in_hv signal line  224  will be at a logic “1” when the voltage on the multifunction A0 input (connection  120   c ) is greater than or equal to VHH, min, and at a logic “0” when the voltage on the multifunction A0 input (connection  120   c ) is less than VHH, min. 
         [0023]    The out_lv signal line  218  will be at a logic “0” when the voltage on the multifunction A0 input (connection  120   c ) is less than or equal to VIL, max; or less than VHH, min, and greater than or equal to VIH, max. The out_lv signal line  218  will be at a logic “1” when the voltage on the multifunction A0 input (connection  120   c ) is greater than VHH, min; or less than VIH, max, and greater than or equal to VIH, min. 
         [0024]    The out_hv signal line  220  will be at a logic “1” when the voltage on the multifunction A0 input (connection  120 c) is greater than or equal to VHH, min; and at a logic “0” when the voltage on the multifunction A0 input (connection  120 c) is less than VHH, min. The use of signal lines  222 ,  224 ,  226  and  228  combined with logic gates  204 - 216  create the “safe zone” where any form of write protection is inhibited. The safe zone will be, according to this specific example embodiment, when the voltage on the multifunction A0 input (input  120   c ) is less than VHH, min; but greater than or equal to VIH, max. 
         [0025]    Referring to  FIG. 4 , depicted is a table of voltages and logic levels associated with the integrated circuit device of  FIG. 1  and the circuit shown in  FIG. 2 , according to the teachings of this disclosure. The aforementioned logic of  FIG. 2  thereby creates a safe zone between VHH, min; and VIH, max; in which neither a temporary (SWP) memory write protection or a permanent (PSWP) memory write protection can occur. When the voltage on the multifunction A0 input (connection  120   c ) is greater than VHH, min; a temporary (SWP) memory write protection can occur, and when the voltage on the multifunction A0 input (connection  120   c ) is less than VIH, max; a permanent (PSWP) memory write protection can occur. Thus inadvertent permanent (PSWP) memory write protection cannot accidentally occur, according to the teachings of this disclosure. 
         [0026]    While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.