Abstract:
An improved sense amplifier for accessing data stored in a flash memory or other memory, wherein the improvement consists of adding a variable impedance switch transistor to a conventional sense amplifier having a fixed impedance. The switch transistor has a low impedance for fast settling of charge during the pre-charge state of the flash memory, and has a high impedance during the sensing state of the flash memory for achieving a high gain and thus faster access of stored data than conventional sense amplifiers. The present invention also provides for better matching of sense amplifier transistors, thereby decreasing variations in performance between different transistors.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of amplifiers, and more particularly to an improved sense amplifier for a memory. 
     BACKGROUND OF THE INVENTION 
     Flash memory is a semiconductor type of non-volatile memory that does not lose its stored data when its power is turned off. Flash memory is both electronically programmable and erasable, thereby enabling it to be reprogrammed even after it has been wired into an electronic system. Flash memory is used in numerous applications including storing microprocessor programs that control the operation of electronic devices such as cell phones and pagers. 
     Conventional flash memory is typically comprised of an array of memory cells. Information can be stored in a flash memory cell as a charge on a floating gate of a transistor comprising the cell, or as a charge trapped in a dielectric layer of semiconductor material from which the cell is fabricated. Data stored in a flash memory cell is typically read, i.e., sensed, by increasing the control gate voltage of the memory cell on a common word-line, and then sensing whether current is flowing through the memory cell at the bit-line to which the drain terminal of the memory cell is coupled. The circuit used to sense stored data is called a sense amplifier because it amplifies a small change in the bit-line voltage during the first moments of a read into a full logic voltage swing. 
     Conventional flash memory operates in two stages: a pre-charge stage requiring low impedance so that a previous read can settle quickly and the memory can prepare for the next read, and a sense stage requiring high impedance in order to achieve a high gain during the read in order to access the stored data as quickly as possible. However, conventional sense amplifiers suffer from a significant drawback. Specifically, they typically have a single fixed impedance value unable to provide both the low and high impedance required for optimum performance. 
     A related U.S. patent application for a Switched Resistor for Sensing Low Current was filed by the applicant Malcolm Smith on Sep. 25, 1998 and has been assigned application Ser. No. 09/160,411. 
     SUMMARY 
     An improved sense amplifier for a flash memory having a low impedance state for fast settling of charge in the pre-charge stage of the operation of the flash memory, and a high impedance state for achieving a high gain and thus faster access to stored data during the sense stage operation of the flash memory than conventional sense amplifiers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a conventional sense amplifier circuit. 
     FIG. 2 shows an exemplary embodiment of an improved sense amplifier circuit according to the present invention. 
     FIG. 3 shows a block diagram of a conventional memory circuit in which a plurality of sense amplifier circuits according to the present invention are used. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a prior art sense-amplifier circuit  10  used in a conventional flash memory, wherein an array of memory cells is attached to node SAIN. Transistors M 1 -M 4  comprise a front end of circuit  10  and act as a pre-amplifier for the rest of circuit  10 . Since the present invention incorporates circuit  10 , a detailed review of its operation will aid in understanding the teachings of the present invention. If during the sense stage operation of the flash memory, the memory cell being read is not conducting, then no current flows from the memory cell into circuit  10  through transistor M 2 . Circuit  10  is thus effectively an open circuit such that the nodal voltage at node N 1  is pulled up by transistor M 1  causing both transistors M 1  and M 3  to turn off since they are current mirrors. 
     As the nodal voltage of node N 1  is pulled up, transistor M 5  turns off while transistor M 6 , whose gate is coupled to node N 1 , turns on, thereby pulling the nodal voltage of node N 3  down towards ground. As a result, transistor M 7  turns on and transistor M 8  turns off, thereby pulling the output of circuit  10  higher. 
     By contrast, if during the sense stage operation of the flash memory, the memory cell being read is conducting, then current flows from the memory cell into circuit  10  through transistor M 2 . As a result, the voltage at node SAIN, which is initially high and at the same voltage as V 15 , is pulled down towards ground such that the nodal voltage at node N 1  is also pulled down towards ground causing transistors M 1  and M 3  to both turn on harder. In response, transistor M 4  turns on harder which causes transistor M 2  to turn on harder increasing the pull on transistor M 1  to turn on harder, thereby creating positive feedback around the front end of circuit  10  for turning transistors M 1 -M 4  on harder. As the nodal voltage of node N 1  is pulled down towards ground, transistor M 5  turns on harder and transistor M 6  turns off so that the nodal voltage of node N 3  is pulled up higher away from ground causing transistor M 7  to turn off and transistor M 8  to turn on, thereby pulling the output of circuit  10  low. 
     Circuit  10  suffers from a significant drawback. Specifically, having an impedance of fixed value limits the gain the sense amplifier can achieve and thus the speed at which it attains the threshold voltage required to switch from the pre-charge stage to the sense stage since the switching speed is directly proportional to the gain. The gate of transistor M 1  is diode connected to its drain such that the signal impedance seen looking into node N 1  from transistor M 2  is relatively small because the transconductance, which is the inverse of the impedance, is relatively large compared to the other conductances, e.g., at the drain of transistor M 1 . Consequently, even though the nodal voltage at node N 1  settles quickly to its pre-charged value, the gain of circuit  10  is small and thus circuit  10  switches slowly. 
     FIG. 2 shows an exemplary embodiment of a sense amplifier circuit  20  according to the present invention which overcomes the foregoing drawback by adding a variable resistance switch transistor M 15  to circuit  10 , thereby enabling circuit  20  to have a low impedance in the pre-charge stage and a high impedance in the sense stage. Circuit  20  utilizes the conventional front end of circuit  10  in the pre-charge stage in which it has a low impedance and thus enables quick settling of the memory cell, but it also eliminates the connection between the gate of transistor M 1  to node N 1  in the sense stage, thereby providing the desired high impedance for a quick switching speed. 
     During the pre-charge stage, switch transistor M 15  switches closed to an on state such that the voltage at node prech is pulled down towards ground causing transistor M 15  to turn on more quickly. Consequently, since the gate of transistor M 1  is connected to the drain of transistor M 1 , the impedance seen looking into the drain of transistor M 1  is small, thereby ensuring quick settling of node N 1 . 
     During the sense stage, switch transistor M 15  switches open to an off state such that the voltage at node prech is pulled up from ground causing transistor M 15  to turn off. Consequently, since the gate of transistor M 1  is no longer connected to its drain, the impedance seen looking into the drain of transistor M 1  is large so that the preamplifier gain is large such that the threshold voltage is more quickly attained to switch the circuit more quickly. 
     Transistor M 15  can be any conventional type of transistor having transconductance and conductance. The back end of circuit  20  operates in the same manner as the back end of circuit  10  described above. The addition of switch transistor M 15  without any other performance enhancements enables circuit  20  to access data from a memory cell faster than can circuit  10 . Circuit  20  has several additional benefits compared to circuit  10 . Typically, the only way to improve the speed of conventional sense amplifiers like circuit  10  is to decrease the width of transistors M 1  and M 3  so that their transconductance decreases. However, doing so worsens the match between transistors M 1 , M 3  and M 5 , and thus results in large differences in performance of the various components of circuit  10 . By contrast, adding switch transistor M 15  enables the widths of transistors M 1  and M 3  to be increased so that they match better, thereby improving both pre-charge settling and sense stage switching, while also decreasing variations in performance of the various components of circuit  20 . 
     Conventional memory circuits typically include a plurality of sense amplifiers for reading data from the memory. FIG. 3 shows a block diagram of a conventional memory circuit  30  having a plurality of sense amplifier circuits  20 . Memory circuit  30  is comprised of a memory  32  to which is coupled a row decoder  34  for a plurality of row addresses  1  through n, and a column decoder  36  for a plurality of column addresses  1  through n. Interposed between memory  32  and column decoder  36  is an in/out circuit  38  having a read/write line  40 , a clock line  42 , a plurality of data lines  44 , numbered  1  through n, and a plurality of sense amplifier circuits  20 , numbered  1  through n, for reading data from memory  32 . 
     The present invention may be used in any integrated circuit such as a memory, or any integrated circuit having an embedded memory. The invention may also be used with various types of memory, including but not limited to EPROM, SRAM, DRAM and ROM. 
     Numerous modifications to and alternative embodiments of the present invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. Details of the structure maybe varied substantially without departing from the spirit of the invention and the exclusive use of all the modifications, which come within the scope of the appended claims, is reserved.