Abstract:
Solar cell assemblies and method of making solar cell assemblies. The method, including: fabricating solar cell chips on solar cell wafers; dicing the solar cell wafers into individual solar cell chips; packaging the individual solar cell chips in molded plastic packages to form solar cell chip packages; and mounting on and electrically connecting one or more of the solar cell chip packages to a printed circuit board. The assemblies including a printed circuit board; one or more solar cell chip packages mounted on and electrically connected to the printed circuit board, each of said one or more solar chip packages comprising a solar cell chip and a lead frame encapsulated in a molded plastic body, top surfaces the solar cell chips exposed in top surfaces of the molded plastic bodies.

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This application is a division of application Ser. No. 12/189,960, filed Aug. 12, 2008, now pending, which is hereby incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the field of solar cells; more specifically, it relates to a method of fabricating a solar cell assembly. 
       BACKGROUND OF THE INVENTION 
       [0003]    Solar cells or solar concentrators are semiconductor devices capable of generating electricity using the photovoltaic effect. The relatively high cost of fabricating solar cells and inability to easily configure voltage and current output as well as the difficulty in repairing solar cell arrays has seriously limited the widespread use of solar cells. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
       SUMMARY OF THE INVENTION 
       [0004]    A first aspect of the present invention is a method, comprising: (a) fabricating solar cell chips on solar cell wafers; (b) dicing the solar cell wafers into individual solar cell chips; (c) packaging the individual solar cell chips in molded plastic packages to form solar cell chip packages; and (d) mounting on and electrically connecting one or more of the solar cell chip packages to a printed circuit board. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0006]      FIG. 1  is a cross-sectional drawings illustrating an exemplary solar cell chip according to embodiments of the present invention through line  1 - 1  of  FIGS. 2 and 3 ; 
           [0007]      FIG. 2  is a top view of the solar cell of  FIG. 1 ; 
           [0008]      FIG. 3  is a bottom view of the solar cell of  FIG. 1 ; 
           [0009]      FIG. 4  is a top view of the solar cell chip of  FIGS. 1 ,  2  and  3  in a plastic package; 
           [0010]      FIG. 5A  is a cross-section of the solar cell chip and package of  FIG. 4  through line  5 A- 5 A; 
           [0011]      FIG. 5B  is a cross-section of a first alternative plastic package containing the solar cell chip of  FIGS. 1 ,  2  and  3 ; 
           [0012]      FIG. 5C  is a cross-section of a second alternative plastic package containing the solar cell chip of  FIGS. 1 ,  2  and  3 ; 
           [0013]      FIG. 6A  is a top view of an exemplary printed circuit board for a solar cell chip assembly configured for the solar cell/chip package of  FIGS. 4 and 5A  according to embodiments of the present invention; 
           [0014]      FIG. 6B  is a bottom view of the exemplary printed circuit board of  FIG. 6A ; 
           [0015]      FIG. 7  is a cross-section view the exemplary printed circuit board of  FIGS. 6A and 6B  through line  7 - 7  of  FIGS. 6A and 6B ; 
           [0016]      FIG. 8  is a cross-section view the exemplary printed circuit board of FIGS.  6 A/ 6 B and  7  having the packaged solar cell of  FIGS. 4 and 5A  attached; 
           [0017]      FIG. 9 , is a top view of an exemplary printed circuit board for a multiple solar cell chip packages according to embodiments of the present invention; 
           [0018]      FIG. 10A  is a bottom view of the exemplary printed circuit board of  FIG. 9  for parallel interconnection of solar cell chip packages according to embodiments of the present invention; 
           [0019]      FIG. 10B  is a bottom view of the exemplary printed circuit board of  FIG. 9  for serial interconnection of solar cell chip packages according to embodiments of the present invention; 
           [0020]      FIG. 11  is a cross-section view of an exemplary printed circuit board for a solar cell chip assembly configured for the solar cell/chip package of  FIG. 5B  according to embodiments of the present invention; 
           [0021]      FIG. 12  is a cross-section view of an exemplary printed circuit board for a solar cell chip assembly configured for the solar cell/chip package of  FIG. 5C  according to embodiments of the present invention; 
           [0022]      FIG. 13A  illustrates attaching a contact frame of a solar cell chip to a lead of a package using wire bonding and  FIG. 13B  illustrates attaching a contact frame of a solar cell chip to a lead of a package using lead bonding; 
           [0023]      FIG. 14  is a cross-section view of an exemplary printed circuit board for a cooled solar cell chip assembly configured for the solar cell/chip package of  FIG. 5B  according to embodiments of the present invention; 
           [0024]      FIG. 15  is a top view of multi-solar-chip assembly according to embodiments of the present invention; and 
           [0025]      FIG. 16  is a flowchart illustrating the major steps required to practice the embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]      FIG. 1  is a cross-sectional drawing illustrating an exemplary solar cell chip according to embodiments of the present invention through line  1 - 1  of  FIGS. 2 and 3 . In  FIG. 1 , a solar cell chip  90  includes a silicon substrate  100  having a P-doped region  105  abutting a top surface  110  of the substrate and an N-doped region  115  abutting a bottom surface  120  of the substrate. A top passivation layer  125  is formed on top surface  110  of substrate  100  and an antireflective coating  130  formed on a top surface  135  of top passivation layer  125 . A bottom passivation layer  140  is formed on bottom surface  120  of substrate  100 . A metal silicide contact  150 A is formed through top passivation layer  125  and antireflective coating  130  to electrically contact P-doped region  105 . A metal silicide contact  150 B formed through bottom passivation layer  140  electrically contact P-doped region  115 . A metal contact frame  155  electrically contacts metal silicide contact  150 A and a metal bus bar  160  electrically contacts metal silicide contact  150 B. Solar cell chip  90  includes optional N-doped emitters  165  under metal silicide contact  150  extending through and past N-doped region  115  into substrate  100 . 
         [0027]      FIG. 2  is a top view of the solar cell of  FIG. 1 . In  FIG. 2 , it can be seen that contact frame  155  includes a peripheral region  170  adjacent to a perimeter  175  of solar cell chip  90  and extensions regions  180  extending out from peripheral region  170  toward the interior of the chip. Metal silicide contact  150 A extends under contact frame  155 . In  FIGS. 1 and 2 , contract frame  155  is illustrated as coextensive with silicide layer  150 A. Alternatively, contact frame  155  may overlap silicide layer  150 A. 
         [0028]      FIG. 3  is a bottom view of the solar cell of  FIG. 1 . In  FIG. 3 , bus bar  160  includes a first region  185  parallel to an edge  190  of solar cell chip  90  and finger regions  195  extending across the chip toward a side opposite side  190 . Metal silicide contact  150 B extends under bus bar  160 . In  FIGS. 1 and 3 , bus bar  160  is illustrated as coextensive with silicide layer  150 B. Alternatively, bus bar  160  may overlap silicide layer  150 B. 
         [0029]    Solar cell chip  90  is exemplary and is illustrated so interconnections between solar cell chips and the next level of packaging can be illustrated. The invention should be understood as not being limited to any particular solar cell chip and that other solar cell chips as known in the art may be substituted. 
         [0030]      FIG. 4  is a top view of the solar cell chip of  FIGS. 1 ,  2  and  3  in a plastic package. In  FIG. 4 , solar cell chip  90  is packaged in a molded plastic (or other polymeric material) package to form a solar cell chip package  200 . Package  200  includes first leads  205 A and  205 B connected to contact frame  155  and second leads  210 A and  210 B connected to bus bar  160  (see  FIG. 5A ) encapsulated in a plastic body  215 . Contact frame  155  and antireflective coating  130  are not covered by body  215  but exposed in a top surface of the body. 
         [0031]      FIG. 5A  is a cross-section of the solar cell chip and package of  FIG. 4  through line  5 A- 5 A. In  FIG. 5A , lead  205 B (and  205 A, see  FIG. 4 ) is electrically and physically connected to contact frame  155  by solder interconnects  220 A and lead  210 B (and  210 A, see  FIG. 4 ) are electrically and physically connected to bus bar  160  by solder interconnects  220 B. Other lead connection methods include wire bonding (see  FIG. 15A ) and gold or aluminum bump bonding (see  FIG. 15B ). The processes used to connect leads  205 A and  205 B to contact frame  155  and leads  210 A and  210 B to bus bar  160  may be independently selected from the group consisting of soldering, wire bonding and gold bump bonding (see  FIGS. 13A and 13B  and discussion infra). Package  200  is a surface mount package and leads  205 A,  205 B,  210 A and  210 B extend away from body  215 . 
         [0032]      FIG. 5B  is a cross-section of a first alternative plastic package containing the solar cell chip of  FIGS. 1 ,  2  and  3 . In  FIG. 5B , a package  200 A is similar package  200  of  FIG. 5A , except leads  206 A,  206 B,  211 A and  211 B which respectively replace leads  205 A,  205 B,  210 A and  210 B of  FIG. 5A , extend under body  215 . Package  200 A is often referred to a “J” lead package. Package  200 A may be surface mounted or socket mounted. 
         [0033]      FIG. 5C  is a cross-section of a second alternative plastic package containing the solar cell chip of  FIGS. 1 ,  2  and  3 . In  FIG. 5C , a package  200 B is similar package  200  of  FIG. 5A , except leads  207 A,  207 B,  212 A and  212 B which respectively replace leads  205 A,  205 B,  210 A and  210 B of  FIG. 5A , are pins. Package  200 A may be through via soldered (see  FIG. 12 ) or socket mounted. 
         [0034]    By using integrated circuit industry standard fabrication processes and tools and fabricating solar cell chips in integrated circuit fabrication facilities costs can be reduced. By using integrated circuit industry standard packages and packaging solar cell chips in integrated circuit package facilities costs can be reduced. Interference of solar cell fabrication with integrated circuit chip fabrication and packaging can be reduced to a minimum by assigning low priority to solar cell fabrication in integrated circuit facilities and using otherwise tool idle time. 
         [0035]      FIG. 6A  is a top view,  FIG. 6B  is a bottom view and  FIG. 7  is a cross-section view rough line  7 - 7  of  FIGS. 6A and 6B  of an exemplary printed circuit board for a solar cell chip assembly configured for the solar cell/chip package of  FIGS. 4 and 5A  according to embodiments of the present invention. A printed circuit board (PCB)  225  includes electrically conductive through vias  235  connected to metal pads  240  on top surface  230 A of PCB  225  and metal lands  245  on bottom surface  230 B of PCB  225 . Lands  245  may act as edge connectors to connect package  200  the outside world. Through vias  235  may be plated through vias. Alternatively, for PCB  225  and PCB  225 A,  225 B described infra, lands  245  may also be formed on the top surface of the PCB eliminating the need for through vias. 
         [0036]      FIG. 8  is a cross-section view of the exemplary printed circuit board of FIGS.  6 A/ 6 B and  7  having the packaged solar cell of  FIGS. 4 and 5A  attached. In  FIG. 8  leads  205 B and  210 B (and  205 A and  210 A, see  FIG. 6A ) and are electrically and physically connected to pads  240  by solder joints  247 . 
         [0037]      FIG. 9  is a top view,  FIG. 10A  is a bottom view for parallel interconnection of solar cell chip packages and  FIG. 10B  is a bottom view for serial interconnection of solar cell chip packages of exemplary printed circuit boards for a multiple solar cell chip/package assemblies according to embodiments of the present invention. In  FIG. 9 , a top surface of PCB  225 A or  225 B has sufficient pads  240  and through vias  235  for three packages  200  (dashed lines). In  FIG. 10A , a bottom surface of PCB  225 A has a pair of lands  245 A each interconnecting all the through vias in different rows of through vias  235 . PCB  225 A thus has a voltage output of one solar cell chip but the current capacity of three solar cell chips. In  FIG. 10B , a bottom surface of PCB  225 B has a pair of lands  245 B 1  interconnecting pairs of through vias in different rows of through vias and a pair of lands  245 B 2  interconnecting a pair of vias in respective same rows of through vias  235 . PCB  225 B thus has a voltage output of three solar cell chips but the current capacity of one solar cell chip. 
         [0038]    It should be understood that PCBs may be fabricated having N by M arrays of solar cell chip packages (N and M being integers such that N+M is at least 3 and neither N or M are 0) and wired in parallel and series combinations. At least three solar cell chip packages are required for parallel and series combinations. It should also be understood, that because each solar cell chip package is connected individually to the PCB, individual solar cell chip packages may be removed and replaced. 
         [0039]      FIG. 11  is a cross-section view of an exemplary printed circuit board for a solar cell chip assembly configured for the solar cell/chip package of  FIG. 5B  according to embodiments of the present invention. In  FIG. 11 , a solar cell chip package  200 A is removeably held in a respective socket  250 . While one cell chip package  200 A/socket  250  pairs is illustrated in  FIG. 11 , there may be two or more solar cell chip package  200 A/socket  250  pairs. Socket  250  includes a plastic body  255  and pin clips  260 . Pin clips  260  not only act as spring clip connections for leads  206 B and  211 B (and  206 A and  211 A, not shown) but also pass through vias  265  of PCB  270  and are soldered ( 275 ) to lands  245 X on the bottom surface  280  of the PCB. Lands  245 X wire sockets  250  and therefore solar cell chip packages  200 A in any number of serial and parallel combinations. Because solar cell chip packages  200 A are held in sockets  250 , it is very easy to replace any particular package if it is found to be defective. 
         [0040]      FIG. 12  is a cross-section view of an exemplary printed circuit board for a solar cell chip assembly configured for the solar cell/chip package of  FIG. 5C  according to embodiments of the present invention. In  FIG. 12 , a solar cell chip package  200 B is soldered ( 275 ) to lands  245 X on the bottom surface  280  of PCB  270 . While one cell chip package  200 B is illustrated in  FIG. 11 , there may be two or more solar cell chip packages  200 B. Lands  245 X are configured to wire solar cell chip packages  200 B in any number of serial and parallel combinations. Because solar cell chip packages  200 B are soldered  250 , it is easy to replace any particular package if it is found to be defective. 
         [0041]      FIG. 13A  illustrates attaching a contact frame of a solar cell chip to a lead of a package using wire bonding and  FIG. 13B  illustrates attaching a contact frame of a solar cell chip to a lead of a package using lead bonding. Wire bonding and lead bonding may be applied to any of solar cell chip packages  200 ,  200 A and  200 B discussed supra. In  FIG. 13A , a lead  205 / 206 / 207  is electrically connected to contact frame  155  by a wire bond  285 . In wire bonding, a ball formed on a first end of a wire by melting one end of a gold or aluminum wire and ultrasonically bonding the ball to frame  155  and then ultrasonically forming a wedge bond at a second end of the wire to lead  205 / 206 / 207 . Alternatively, wedge bonds may be formed at both ends of the wire. In  FIG. 13A , a lead  205 / 206 / 207  is electrically connected to contact frame  155  by a bump  290 . In lead bonding, bump  287  (e.g., gold) is formed on lead  205 / 206 / 207  and contact frame  155  is ultrasonically bonded to the bump. 
         [0042]      FIG. 14  is a cross-section view of an exemplary printed circuit board for a cooled solar cell chip assembly configured for the solar cell/chip package of  FIG. 5B  according to embodiments of the present invention. In  FIG. 14 , an assembly  290  includes a solar cell chip package  200 C, a socket  250 A and a PCB  270 A. There may be multiple cell chip package  200 C/socket  250 A sets on PCB  270 A. Solar cell chip package  220 C is similar to solar cell chip package  200 A of  FIG. 11  except a thermally conductive heat spreader  295  is embedded in body  215  and is in contact with substrate  100  of solar cell chip  90 . A surface  300  of heat spreader  295  is exposed in the bottom surface of solar cell chip package  200 C and not covered by body  215 . Socket  250 A is similar to socket  250  of  FIG. 11 , except for an opening under heat spreader  295 . PCB  270 A is similar to PCB  270  of  FIG. 11 , except for an opening under heat spreader  295 . The respective openings in socket  250 A and PCB  270 A allow a cooling device  305  to be inserted through sockets  250 A and PCB  270 A in order to contact surface  300  of heat spreader  295 . Cooling device  305  may include channels for recirculating a gas or liquid coolant or may be a Peltier device. The heat spreader/cold finger concept may be applied to other embodiments of the present invention. For example, solar cell chip package  200  and PCB board of  FIG. 8  and solar cell chip package  200 B and PCB  270  of  FIG. 12  may be configured for a heat spread and cooling device. 
         [0043]      FIG. 15  is a top view of multi-solar-chip assembly according to embodiments of the present invention. In  FIG. 15 , an assembly  320  includes a PCB  325 , an array of solar cell chip packages  330 , optional control integrated circuits (ICs)  335  and optional devices  340  mounted to the PCB. PCB  325  is provided with an edge connection  345 . Electrically conductive lands (not illustrated in  FIG. 15 ) on the top surface, or bottom surface, or interior regions of PCB  325  or combinations thereof interconnect solar cell chip packages  330 , ICs  335  and devices  340  to each other and edge connection  345 . Solar cell packages  330  may be wired in combinations of parallel and series. Devices  340  may be selected from the group consisting of resisters, capacitors, inductors, diodes and transistors. Integrated circuit chips  335  may include voltage regulators or current regulators or both. Integrated circuit chips  335  may include logic circuits, memory circuits, switching circuits to change the wiring of solar cell chip packages  330  in order change the voltage output and/or current capacity of assembly  320 . Solar cell chip packages  330  may consist of any of the solar cell chip package embodiments described supra, including those illustrated in  FIGS. 8 ,  11 ,  12 ,  13 A,  13 B and  14 . 
         [0044]      FIG. 16  is a flowchart illustrating the major steps required to practice the embodiments of the present invention. A wafer is a disc shaped silicon substrate. An integrated circuit chip is defined as a chip having at least one memory, logic or analog circuit comprised of at least one transistor (e.g., field effect transistor or bipolar transistor). In step  400 , scrap wafers which include wafers on which one or fabrication steps used to make integrated circuit chips has been performed or monitor wafers used in monitoring semi-conductor processes in a integrated circuit manufacturing facility are selected. Scrap wafers include wafers which were misprocessed or which failed testing. 
         [0045]    In step  405 , the wafers are reclaimed by grinding top and/or bottom surfaces of the scrap wafers, chemical-mechanical polishing the top and/or bottom surfaces of the scrap wafers, chemically treating (including etching) the top and/or bottom surfaces of the scrap wafers or performing combinations thereof. 
         [0046]    In step  410 , multiple solar cell chips are fabricated using the reclaimed wafers. Fabrication may include processing the reclaimed wafers on one or more tools normally used to fabricate integrated circuit chips. Fabrication may include processing the reclaimed wafers on one or more tools used to fabricate solar cell chips. Fabrication may include processing the reclaimed wafers only on tools normally used to fabricate integrated circuit chips. Fabrication may include processing the reclaimed wafers only on tools used to fabricate solar cell chips. Testing of the solar cell chips while still in wafer form may be performed prior to step  415   
         [0047]    In step  415 , the wafers are diced (singulated) into individual solar cell chips. If testing was performed in step  410 , only tested good solar cell chips proceed to step  420 . The individual solar cell chips range in surface area from about 25 mm 2  to about 400 mm 2 . 
         [0048]    In step  420 , individual solar cell chips are packaged in plastic packages. Packaging the solar cell chips includes, placing the solar cell chip on a lead frame, providing contact wiring between the solar cell chip and leads of the lead frame (e.g., by soldering, wire bonding, or bump bonding), and encapsulating the solar cell chip and lead frame in plastic or other polymeric material. Step  420  may include testing of the completed solar cell chip packages. It should be understood, that in encapsulating solar cell chips the light collecting surface of the solar cell chip is not covered by molding material. 
         [0049]    In step  425 , one or more solar cell chip packages are mounted on a printed circuit board. The mounting of the solar cell chips may be electrically connected in series to increase the voltage output of the completed assembly, in electrically connected in parallel to increase the current capacity of the completed assembly or electrically connected both in series and parallel. Mounting of the solar cell chip packages may be by soldering to pads on the PCB or by removeably inserting the solar cell chip packages into sockets that have been soldered to the PCB. 
         [0050]    A solar cell chip is essentially a light collecting diode. In one example, solar cell chips according to embodiments of the present invention contain only a single light collecting diode. In one example, solar cell chips of the present invention may include two or more light collecting diodes electrically isolated from each other except for series or parallel connections. In one example, solar cell chips according to embodiments of the present invention consist only of combinations of light collecting diodes, wires, passivation layers and antireflective coatings. In one example, solar cell chips according to embodiments of the present invention consist of only combinations of light collecting diodes, wires, passivation layers, antireflective coatings, and electrical isolation structures. 
         [0051]    Thus the embodiments of the present invention provide a solar cell assembly configurable for different voltage/current combinations and relatively easily repairable. 
         [0052]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.