Abstract:
The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock.

Description:
[0001]     This application is a continue-in-part (CIP) application of U.S. application Ser. No. 11/035,086 filed on Jan. 13, 2005 which is abandoned and is claiming the benefit of Taiwan application serial no. 93101101, filed on Jan. 16, 2004. 
     
    
     BACKGROUND OF INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to an apparatus and a method for generating an output clock signal, particularly relates to an apparatus and a method for generating an output clock signal using an internal clock signal.  
         [0004]     2. Description of the Prior Art  
         [0005]     A Serial interface, such as an I 2 C interface, PCI Express, and Universal Serial Bus (USB), is a common interface for data transmission. The I 2 C interface comprises a data line and a clock line. The USB interface comprises two data lines, Data+ and Data−, and two power lines, Vdd and Gnd. These two data lines Data+ and Data− are differential signals.  
         [0006]     Please refer to  FIG. 1A ;  FIG. 1A  shows a block diagram of the structure of a serial data communication using the serial interface. Please refer to  FIG. 1A . The structure of the serial signal communication comprises a master device  110  and a slayer device  120 . The master device  110  and the slayer device  120  are reference to a reference clock. The reference clock can be provided by a precise crystal oscillator  150  or be generated by an external crystal oscillator  130  and input into an internal phase-lock loop (PLL)  140 . Conventionally, because frequency errors of the reference clocks could not be avoided, the reference clocks of the conventional master device  110  and the conventional slayer device  120  could not be exactly the same and synchronized. In the I 2 C interface, the I 2 C interface includes the clock link for transferring the reference clock from the master device  110  to the slave device  120  such that the master device  110  and the slave device  120  can be synchronization. In a USB, the USB signal contains a data signal and a synchronization signal such that the master device and the slave device can be synchronization according to the synchronization signal.  
         [0007]      FIG. 1B  shows the waveform of a USB signal. The USB signal  160  comprises a synchronization signal  170  and a data signal  180 . When the USB receiver, such as the slayer device  120 , receives the synchronization signal  170 , the USB receiver compensates the sampling frequency of the received data signal  180  to avoid errors. In I 2 C, the I 2 C receiver uses the clock signal of the clock line as a reference to determine the sampling frequency of the data signal of the data line.  
         [0008]     The conventional serial interface requires an external crystal oscillator. In additions, the reference clock frequencies of the conventional master device  110  and the slayer device  120  are not exactly the same.  
         [0009]     Therefore, this invention provides a method and apparatus to generate a clock signal, wherein an external crystal oscillator is not required and the frequency of the clock signal is substantially the same as the frequency of the clock signal generated by a remote serial transmitting device.  
         [0010]     Shinmori (U.S. Pat. No. 6,107,846) discloses a frequency multiplication circuit which is able to generate an output signal having a frequency obtained by multiplying an input external clock signal (see lines 1˜3 of ABSTRACT of Shinmori). The frequency of the output signal is multiple times of that of the input external clock signal, and therefore the period of the output signal definitely is NOT the same as the period of the input external clock signal. Moreover, from the FIGS. 2, 4, 6 and 8 of Shinmori (not shown here), it can be seen that the output signal CLK 2  contains uneven duty cycles due to the fact that, the reference clock signal CLK 0  is output as the output signal CLK 2  only when the output terminal Q 2  is at an active level, and a low signal will be output as the output signal CLK 2  when the output terminal Q 2  is at an inactive level. Therefore, part of the duty cycles of the output signal CLK 2  are equal to the duty cycles of reference clock signal CLK 0 , but some others are not. That is, the frequency multiplication circuit disclosed by Shinmori is merely a frequency multiplying circuit that is capable of generating an output signal having a frequency that is N-times as high as the input external clock signal. However, Shinmori does not disclose, teach nor suggest an apparatus to generate a clock signal as which disclosed in the present invention that, wherein the external crystal oscillator is not required and the frequency and duty cycle of the input clock signal is substantially the same as the frequency and duty cycle of the output clock signal generated by the apparatus.  
       SUMMARY OF INVENTION  
       [0011]     It is therefore one of the objectives of the claimed invention to provide an apparatus and method for generating an output clock without an external reference clock.  
         [0012]     According to the invention, the method for generating an output clock comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronization signal; producing a reference signal according to the synchronization signal; measuring the reference clock according to a second reference clock to generate a measured value; and producing the output clock according to the measured value and the second reference clock.  
         [0013]     Preferably, the reference signal is adjusted according to a control signal such that the period of the reference signal is a multiple of that of the synchronization signal or the frequency of the reference signal is a multiple of that of the synchronization signal.  
         [0014]     According to the present invention, an apparatus for generating an output clock comprises: a control logic receiving a transmitted signal having at least one data signal and at least one synchronization signal, and generating a reference signal according to the synchronization signal; a measuring unit for counting the reference signal according to a second reference clock to generate a counter signal; and an output unit for generating the output clock according to the counter signal and the second reference clock.  
         [0015]     Preferably, the first counter can adjust the reference signal according to a control signal such that the period of the reference signal is a multiple of that of the synchronization signal or the frequency of the reference signal is a multiple of that of the synchronization signal.  
         [0016]     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The details of the present invention will be more readily understood from a detailed description of the preferred embodiments taken in conjunction with the following figures.  
         [0018]      FIG. 1A  shows a block diagram of the structure of a serial data communication using the serial interface;  
         [0019]      FIG. 1B  shows a waveform of a USB signal;  
         [0020]      FIG. 2  shows a diagram of an embodiment of a clock generator according to the present invention;  
         [0021]      FIG. 3  shows a flowchart of an embodiment of a method for generating an output clock according to the present invention;  
         [0022]      FIG. 4  shows a block diagram of an embodiment of the control logic  310  shown in  FIG. 2 ; and  
         [0023]      FIG. 5  shows a block diagram of an embodiment of the measuring unit  320  shown in  FIG. 2 . 
     
    
     DETAILED DESCRIPTION  
       [0024]     Please refer to  FIG. 2 .  FIG. 2  shows an embodiment of a clock generator according to the present invention. The clock generator  300  comprises a control logic  310 , a measuring unit  320 , an output unit  340 , and a free-run clock generator  330 . The control logic  310  can receive a transmitting signal and generate a reference signal  360  according to the synchronization signal  350  of the transmitting signal. The ratio of the period of the reference signal  360  to the period of the synchronization signal  350  can be 1 or any other integers. The ratio of the period of the reference signal  360  and the synchronization signal  350  can also be a non-integer value such as 0.5 or 1.5.  
         [0025]     It can be seen in  FIG. 1B  that, the synchronization signal  170  has a fixed period and is followed by data signal  180 , and that such synchronization signal  170  is not easily counted. In order to make a signal that is “countable”, that “countable” signal must NOT contain “data signal”. Please refer to  FIG. 4 , which illustrates a block diagram of an embodiment of the control logic  310  shown in  FIG. 2 . As sown in  FIG. 4 , one example of the control logic  310  comprises an edge detector  311  and a signal generator  312 . By using the edge detector  311  to detect the edges of the waveform of synchronization signal  170 , the starting edge and ending edge of the period of a synchronization signal  170  can be found, and thus, the signal generator  312  will be able to generate the reference signal  360  by simply corresponding to multiples of (or exactly the same as) the period of the synchronization signal  170 , and such reference signal  360  will contain no data signal at all and is thus countable. In this preferred embodiment, the signal generator  312  further includes a counter therein such that the signal generator  312  is able to generate the reference signal  360  having a period that is “M” times of the period of the synchronization signal  170 . Wherein the value “M” can be 1, or other integer, or non-integer. The reason for this invention to make the reference signal  360  having “M” times in period than the synchronization signal  170  is to make the reference signal  360  easier to be counted by the measuring unit  320 .  
         [0026]     Please refer to both  FIG. 2  and  FIG. 5 , an embodiment of the measuring unit  320  comprises a counter  321  and a divider  322 . The free-run clock generator  330  generates a free-run clock  370  which is fed to the counter  321  of measuring unit  320 . The input of reference signal  360  enables (triggers) the operation of the counter  321  in order to count the reference signal  360  by means of the free-run clock  370 . Through counting the reference signal  360  by the counter  321  of the measuring unit  320 , (in other words, through measuring the period of the reference signal  360  according to the period of the free-run clock  370 ), a sub-measured value is obtained. This sub-measured value is then divided by “M” times by the divider  322 , wherein the value “M” is fed from the control signal  390  and is corresponding to the ratio of period between the reference signal  360  and synchronization signal  170  as mentioned in the previous paragraph. After divided by the divider  322 , the measured value  380  “K” is obtained. The measured value  380  “K” can be an integer or a non-integer. The output unit  340  receives the free-run clock  370  and the measured value  380  and generates an output clock  395 . The ratio of the period of the output clock  395  to the period of the free-run clock  370  is equal to the measured value  380  “K”. For example, if the period of the free-run clock  370  is Tx and the measured value  380  is K, thus the period of the output clock  395  is K×Tx. K can be represented as N.f whereas N and f are integers. In an embodiment, the measuring unit  320  can be implemented by a first counter and the measured value is a counter value. In an embodiment, the output unit  340  can be a second counter.  
         [0027]     The following provides a detailed illustration for how does the measuring unit  320  (as shown in  FIG. 2 ) generate a non-integer measured value  380 . In the world of electronic circuitries, the measured value  380  is always presented in binary digit format. For example, for a 4-bit counter, the measured value  380  can be varied from 0 (“0000” in binary format) to 15 (“1111” in binary format). The simplest way to divide the measured value by 2 is to right-shift one bit of its binary number. For example, for a measured value equal to 8 (“1000” in binary format), a value of 4 (“100.0” in binary format) will be easily obtained by shifting the rightmost digit of its binary number to be located at the right side of the decimal point (please note that this is not really to “shift” the signal, but is only shifting the rightmost bit to the right side of the decimal point “.”). Such prior art operation is similar to divide the value 8 by 2 so as to obtain the result of 4.  
         [0028]     Of course, if somebody wants to divide 8 by 4, then he/she only needs to right-shift the binary digits for 2 digits, and then the value 4 (“10.00” in binary format) will be obtained. Moreover, for dividing a measured value 15 (“1111” in binary format) by 2, the result will be 7.5 (“111.1” in binary format, where the rightmost digit “1” located at the right side of decimal point is considered to be equal to 0.5). Therefore, it is obvious that the measuring unit  320  is able to generate a non-integer measured value  380  by means of counter  321  and divider  322 . That is, the measured value  380  “K” can be represented as N.f whereas N and f are integers, and the symbol “.” is a decimal point. The symbol “N.f” means a non-integer value in binary format. As shown in  FIG. 2  and its corresponding description, the reason for the present invention to present the measured value  380  “K” as “N.f” is due to the fact that there is a “ratio” between the period of the reference signal  360  and the synchronization signal  350 . And, if the ratio between reference signal  360  and synchronization signal  350  is 2, then the sub-measured value should be divided by 2 in order to obtain the measured value  380  “K=N.f” (that is, to right-shift one digit of its binary number), etc.  
         [0029]     The frequency of the free-run clock  370  generated by the free-run generator  330  is independent on that of the synchronization signal  350 . Through the mechanism illustrated previously, the output clock  395  generated by the clock generator  300  of the present invention is corresponding to the synchronization signal  350 . The synchronization signal  350  can be the synchronization signal for the USB interface or the clock signal for the I2C interface.  
         [0030]     In another embodiment, the control logic  310  or the measuring unit  320  can receive a control signal  390  and adjust the period of the reference signal  360  according to the control signal  390 . For example, if the value of the control signal  390  is “M”, the measured value  380  should be equal to KIM to match the counting range of the measuring unit  320 . The value “M” of the control signal  390  can be a positive integer or a positive fraction.  
         [0031]     In a preferred embodiment, the output unit  340  includes a storage unit  341  for storing the measured value  380 .  
         [0032]     Please refer to  FIG. 3 ;  FIG. 3  shows a flowchart of generating an output clock of an embodiment of the present invention. The method comprises the step of:  
         [0033]     In step  201 , a reference signal  360  is generated according to a synchronization signal  350 . The ratio of the period of the reference signal  360  to that of the synchronization signal  350  is a positive value, such as 2 or 2.5.  
         [0034]     In step  202 , the reference signal  360  is adjusted according to the control signal  390 . Users can adjust the period of the reference signal  360  by controlling the control signal  390 . Of course, this step  202  can be omitted.  
         [0035]     In step  203 , a counter value K (the measured value  380 ) is obtained by measuring (counting) the reference signal  360  according to the free-run clock  370 . The free-run clock  370  is generated by the free-run clock generator  330 . The counter value K can be a non-integer.  
         [0036]     In step  204 , an output clock  395  is outputted according to the measured value  380  and the free-run clock  370 .  
         [0037]     In other words, the period of the output clock  395  is K times of that of the free-run clock  370  generated by the free-run clock generator  330 . Such that, the period of output clock  395  is substantially the same as the period of the synchronization signal  350 . Moreover, because the output clock  395  is obtained by multiplying the period of the free-run clock  370  which is a continuous clock signal and has substantially uniformed duty cycles, as a result, the output clock  395  is also a continuous clock signal having substantially uniformed duty cycles.  
         [0038]     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.