Abstract:
A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to a structure and the manufacture method of a non-volatile memory (NVM) and, particularly to a structure and the manufacture method of a embedded flash memory with Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structures in memory cells. 
       BACKGROUND OF THE INVENTION 
       [0002]    A non-volatile memory, as one kind of various memories, has the advantage of that the stored data would not disappear after power down, and thus can be deemed as a data storage device such as a hard disk. It is distinguished from mainstream flash by the use of silicon nitride(Si 3 N 4 ) instead of polysilicon for the charge storage material. SONOS promises lower programming voltages and higher program/erase cycle endurance than polysilicon-based flash. 
         [0003]    As shown in  FIG. 1 , a NVM with SONOS memory cells includes a substrate  104  with a surface  116 , which is divided into a memory area  106  having several NVM transistors  126 ; and a logic area  108  having several metal-oxide-semiconductor (MOS) transistors  112  and  114 . One NVM transistor  126  is constructed by an ONO structure  136  and gate  150  The ONO structure  136  includes a tunnel dielectric layer  128 , a plurality of charge trapping layers  130   a  and  130   b,  and a blocking oxide layer  138 , which are stacked together one by one. The MOS transistors  112  and  114  are constructed by the gate oxide layers  140 / 146  and the gates  152 / 154 , respectively. 
         [0004]    In the conventional manufacture process of a non-volatile memory (NVM), the ONO structure  136  is formed before the formation of the gate oxide layer  140 / 146 . Accordingly, the blocking oxide layer  138  might be lost in the following process, which will worsen the thickness control of the blocking oxide layer  138 , and thus negatively influence the stability of the voltage operation. 
         [0005]    Furthermore, since the elements in the memory area  106  and the logic area  108  will be manufactured simultaneously, there might be SiN resided within the ONO structure  136  of the memory area  104  after the etching process of the gate conductive layer of the logic area  108 , which will influence the quality of the product. 
         [0006]    Moreover, in a batch manufacturing process, the nitride of the exposed ONO structure will inhibit the growth of the oxide layer in the logic area  108 , which will also cause thickness control problems. 
         [0007]    Therefore, to solve the above-mentioned problems will be the main object of the invention. 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention provides a method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer. 
         [0009]    When etching the second gate conductive layer, the ONO structure serves as a hard mask of the MOS transistor gate. 
         [0010]    While etching the first gate conductive layer, a portion of the first gate conductive layer which is not used for forming the MOS transistor gate is remained for forming a capacitor structure with the ONO structure. 
         [0011]    While etching the second gate conductive layer, a portion of the second gate conductive layer which is not used for forming the NVM transistor gate is remained for forming a resistor with a desired electrical resistance. 
         [0012]    The present invention further provides non-volatile memory with SONOS memory cells, which includes a substrate, having a surface divided into a memory area and a logic area; a MOS transistor formed within the logic area, which includes a gate oxide layer formed on the surface of the substrate, and a MOS transistor gate formed above the gate oxide layer; and a NVM transistor formed within the memory gate, which includes an ONO structure formed on the substrate, and a NVM transistor gate formed above the ONO structure; wherein the junction of the ONO structure and the substrate is lower than the surface of the substrate. 
         [0013]    The resistances of the MOS transistor gate and the NVM transistor gate are different. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
           [0015]      FIG. 1  is a schematic cross-sectional view of a conventional SONOS memory. 
           [0016]      FIG. 2  is a flow diagram illustrates a SONOS memory manufacturing process in accordance with an embodiment of the present invention. 
           [0017]      FIGS. 3A through 3G  are process cross-sectional views corresponding to the SONOS memory manufacturing process shown in  FIG. 2 . 
           [0018]      FIGS. 4A and 4B  illustrate applications of the second gate conductive layer with adjustable resistance according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0019]    The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
         [0020]    Please refer to  FIG. 3A  together with the step  201  shown in  FIG. 2 , a substrate (or wafer)  304  made of silicon is provided. A surface  316  of the substrate  304  is divided into a memory area  306  and a logic area  308 , and a plurality of isolation structures  302  are formed, by an isolation process such as the shallow trench isolation(STI) or the local oxidation of silicon (LOCOS) process, on the substrate  304  to isolate the elements which will be formed later, including the memory cells, the NVM transistors in the memory area, and the MOS transistors in the logic area  308 , to the other nearby elements on the substrate  304 . A pad oxide layer  309  is further formed on the surface  316  of the substrate  304 . 
         [0021]    Please refer to  FIG. 3B  together with the steps  202  and  203  shown in  FIG. 2 , various wells or doped zones are formed by respective doping processes to the logic area  308  and the memory area  306 , wherein the dopants penetrate through the pad oxide layer  309 , and are doped into the substrate  304 . A doped zone  310  shown in  FIG. 3B  is a deep N-well, while the doped zones  318 / 324  will serve as the channel of the MOS/NVM transistors, respectively. 
         [0022]    It is noticeable that, referring to  FIG. 3C  together with step  204  shown in  FIG. 2 , a first gate oxide layer  340  of the logic gate  308  is deposited before the depositions of the ONO structure in the memory area  306 , which is different from the conventional SONOS memory manufacturing processes. 
         [0023]    After a cleaning process for removing the pad oxide layer  309  of the surface  316 , including which is located within the doped zone  318 , the first gate oxide layer  340  shown in  FIG. 3C  is deposited on the whole surface  316 . The second gate oxide layer  346  shown in  FIG. 3C  is selectively formed in the application of a low voltage MOS to construct the gate oxide structure of a low voltage MOS transistor corresponding to the high voltage MOS transistor with the gate oxide structure constructed by the first gate oxide layer  340 . 
         [0024]    Then, as indicated by the step  205  shown in  FIG. 2 , the first gate conductive layer made by one of conductive materials such as polysilicon is formed on the surface  316  of the substrate  304 , and a MOS transistor gate  352  is formed by executing a photolithography process on the first gate conductive layer  352 . In the embodiment of a high voltage MOS, the gate  354  on the second gate oxide layer  346  is formed at the same time with the MOS transistor gate  352 , so that a low voltage MOS transistor  314  corresponding to a high voltage MOS transistor  312  is made as shown in  FIG. 3D . The ONO structure, as indicated by the step  206  shown in  FIG. 2 , will be constructed after cleaning the undesired portion of the first gate oxide layer  340 . As shown in  FIG. 3E , an ONO structure  336  is formed on the surface  316  of the substrate  304  by stacking the tunnel dielectric layer  328 , the charge trapping layer  330  (ONO, including sub-layers  330   a / 330   b  as shown in  FIG. 3G ), and the blocking oxide layer  338 . The variations and combinations of materials and forming methods for constructing the ONO structure  336  can be achieved by various conventional techniques, so that it will not be described in detail here. When etching a second gate conductive layer  350  as described later, a portion of the deposition layers of the ONO structure  336  (the charge trapping layer  330 ) covers the MOS transistor gate  352  of the MOS transistor  312  and serves as a hard mask. 
         [0025]    According to the step  207  shown in  FIG. 2  and  FIG. 3F , after forming ONO structure  336 , the second gate conductive layer  350  composed by conductive materials such as polysilicon is deposited on the surface  316  of the substrate  304 , and then a NVM transistor gate  350  is formed by executing a photolithography process on the second gate conductive layer  350 . Accordingly, referring to step  208  shown in  FIG. 2 , the main structures of all transistors are constructed, and the remaining portions of NVM can be performed by standard procedures, e.g., steps for forming the lightly doped drains  358 ,  360  and the sidewall spacers  356 , and the other portion of logic circuits (not shown). Finally, the NVM structure as shown in  FIG. 3G  is fabricated or achieved. 
         [0026]    The order of steps for manufacturing the ONO structure  336  and the first gate oxide  340  is different from that of the conventional manufacturing process, which will cause a distinguishable construction feature between the NVM device according to the present invention and the conventional NVM device. Please refer to  FIG. 3G  together with  FIG. 1 , and it will be found that the junction of the ONO structure  336  and the substrate  304  is lower than the surface  316  and slightly sinks into the interior of the substrate  304 . This is because the oxide layer has an intention of diffusing into the interior of a silicon substrate. Therefore, the level of an oxide layer and the silicon substrate will be lower than that of another oxide layer formed earlier. Similarly, the gate oxide layer  140 / 146  shown in  FIG. 1  sink below the surface  116  of the substrate  104  and into the interior portion of the substrate  104  of the same reason. Such structural feature will be an important criteria for distinguishing the NVM devices manufactured according to embodiments of the method of the present invention. 
         [0027]    Since the NVM transistor gate  350  of the NVM transistor  326  and the MOS transistor gate  352  of the MOS transistor  312  are formed by different gate conductive layer fabricating processes, it is then possible to having different electrical resistances between them. Accordingly, the resistance of the second gate conductive layer  350  will not be limited by the resistance of the MOS transistor gate  352 , and will be possible to have a desired value for high voltage applications. Furthermore, various derivative element structures and applications can be done by applying in-situ processes. For example, as shown in  FIG. 4A , while etching the first gate conductive layer  352 , a portion of the first gate conductive layer  352  which is not used for forming the MOS transistor gate  312  is remained for forming a capacitor structure with the ONO structure  336  and the second gate conductive layer  350 . Furthermore, as have been mentioned, the resistance of the second gate conductive layer  350  is adjustable as desired. Accordingly, as shown in  FIG. 4B , while etching the second gate conductive layer  350 , a portion of the second gate conductive layer  350  which is not used for forming the NVM transistor gate  326  is remained for forming a resistor with a desired electrical resistance. Both of the manufacturing processes do not require to increase the number of photomasks. 
         [0028]    To sum up, the present invention changes the manufacturing order of steps of the ONO structure and the gate oxide layer of the MOS transistor, and thus solves or improves the problems caused by the succeeding processes of the ONO structure in a conventional memory manufacturing, which will influence the quality of memory devices. Furthermore, since the gates of the NVM transistor and the MOS transistor are formed by different gate conductive layer processes, it is then possible to having different electrical resistances between them, and various derivative element structures and applications can be done without increasing the number of photomasks. While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.