Abstract:
The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a divisional patent application of U.S. patent application Ser. No. 12/854,564, filed Aug. 11, 2010, which claims the benefit of Japanese Patent Application No. 2009-186518, filed Aug. 11, 2009, Japanese Patent Application No. 2009-297210, filed Dec. 28, 2009, U.S. Provisional Application No. 61/274,164, filed Aug. 12, 2009, and U.S. Provisional Application No. 61/335,026, filed Dec. 29, 2009, the entire disclosures of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present application relates generally to a semiconductor device and method of producing the same. 
         [0004]    2. Description of the Related Art 
         [0005]    Semiconductor devices, particularly integrated circuits using MOS transistors have increasingly been highly integrated. MOS transistors in integrated circuits have been downsized to nano sizes as the integration level is increased. The basic circuit of digital circuits is an inverter circuit. As MOS transistors constituting an inverter circuit are downsized, problems occur such as difficulty in leaking current control, reduced reliability due to hot carrier effect, and difficulty in reducing the area occupied by circuits while assuring the necessary current quantity. In order to resolve these problems, surrounding gate transistors (SGT) have been proposed in which the source, gate, and drain are provided on a substrate in the vertical direction and the gate surrounds an island-shaped semiconductor, and CMOS inverter circuits using SGTs have been proposed (for example, see S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Nobel Circuit Technology with Surrounding Gate Transistors (SGTs) for Ultra High Density DRAMs,” IEEE JSSC, Vol. 30, No. 9, 1995). 
         [0006]    An inverter is constructed using a pMOS transistor and an nMOS transistor. The mobility of holes is half the mobility of electrons. Therefore, the pMOS transistor must have a gate width double the gate width of the nMOS transistor in an inverter circuit. For this reason, a conventional CMOS inverter circuit using SGTs comprises two pMOS SGTs and one nMOS SGT. In other words, a conventional CMOS inverter circuit using SGTs comprises three island-shaped semiconductors. 
       SUMMARY OF THE INVENTION 
       [0007]    The purpose of the present invention is to provide a semiconductor device consisting of CMOS inverter circuits using highly integrated SGTs. 
         [0008]    In order to achieve this object, according to a first aspect of the present invention, there is provided a semiconductor device serving as an inverter, which comprises, a first island-shaped semiconductor layer, a second semiconductor layer, a gate electrode at least a part of which is arranged between the first island-shaped semiconductor layer and the second semiconductor layer, a first gate insulating film at least a part of which is arranged between the first island-shaped semiconductor layer and the gate electrode and is in contact with at least a part of the periphery of the first island-shaped semiconductor layer and a surface of the gate electrode, a second gate insulating film arranged between the second semiconductor layer and gate electrode being in contact with the second semiconductor layer and another surface of the gate electrode, a first first-conductive-type high-concentration semiconductor layer arranged on the top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged on the bottom of the island-shaped semiconductor layer and having a polarity identical to that of the first first-conductive-type high-concentration semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on the top of the second semiconductor layer and having a polarity opposite to that of the first first-conductive-type high-concentration semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged on the bottom of the second semiconductor layer and having a polarity opposite to that of the first first-conductive-type high-concentration semiconductor layer. 
         [0009]    According to a second aspect of the present invention, there is provided a semiconductor device serving as an inverter, which comprises; a first transistor including; a first island-shaped semiconductor layer; a first gate insulating film surrounding the periphery of the first island-shaped semiconductor layer; a gate electrode surrounding the periphery of the first gate insulting film; a first first-conductive-type high-concentration semiconductor layer arranged on the top of the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged on the bottom of the island-shaped semiconductor layer and having a polarity identical to that of the first second-conductive-type high-concentration semiconductor layer, and a second transistor including; the gate electrode; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged on the top of the second semiconductor layer and having a polarity opposite to that of the first second-conductive-type high-concentration semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged on the bottom of the second semiconductor layer and having a polarity opposite to that of the first second-conductive-type high-concentration semiconductor layer. 
         [0010]    With the present invention, it is possible to make the semiconductor device finer by using SGTs that can be highly integrated. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    A more complete understanding of this application can be obtained when the following detailed description is considered in conjunction with the following drawings, in which: 
           [0012]      FIG. 1A  is a plane view of primary elements of a semiconductor device according to a first embodiment of the present invention,  FIG. 1B  is a cross-sectional view at the line X-X′ in  FIG. 1A , and  FIG. 1C  is a cross-sectional view at the line Y-Y′ in  FIG. 1A ; 
           [0013]      FIG. 2A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 2B  is a cross-sectional view at the line X-X′ in  FIG. 2A , and  FIG. 2C  is a cross-sectional view at the line Y-Y′ in  FIG. 2A ; 
           [0014]      FIG. 3A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 3B  is a cross-sectional view at the line X-X′ in  FIG. 3A , and  FIG. 3C  is a cross-sectional view at the line Y-Y′ in  FIG. 3A ; 
           [0015]      FIG. 4A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 4B  is a cross-sectional view at the line X-X′ in  FIG. 4A , and  FIG. 4C  is a cross-sectional view at the line Y-Y′ in  FIG. 4A ; 
           [0016]      FIG. 5A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 5B  is a cross-sectional view at the line X-X′ in  FIG. 5A , and  FIG. 5C  is a cross-sectional view at the line Y-Y′ in  FIG. 5A ; 
           [0017]      FIG. 6A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 6B  is a cross-sectional view at the line X-X′ in  FIG. 6A , and  FIG. 6C  is a cross-sectional view at the line Y-Y′ in  FIG. 6A ; 
           [0018]      FIG. 7A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 7B  is a cross-sectional view at the line X-X′ in  FIG. 7A , and  FIG. 7C  is a cross-sectional view at the line Y-Y′ in  FIG. 7A ; 
           [0019]      FIG. 8A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 8B  is a cross-sectional view at the line X-X′ in  FIG. 8A , and  FIG. 8C  is a cross-sectional view at the line Y-Y′ in  FIG. 8A ; 
           [0020]      FIG. 9A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 9B  is a cross-sectional view at the line X-X′ in  FIG. 9A , and  FIG. 9C  is a cross-sectional view at the line Y-Y′ in  FIG. 9A ; 
           [0021]      FIG. 10A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 10B  is a cross-sectional view at the line X-X′ in  FIG. 10A , and  FIG. 10C  is a cross-sectional view at the line Y-Y′ in  FIG. 10A ; 
           [0022]      FIG. 11A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 11B  is a cross-sectional view at the line X-X′ in  FIG. 11A , and  FIG. 11C  is a cross-sectional view at the line Y-Y′ in  FIG. 11A ; 
           [0023]      FIG. 12A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 12B  is a cross-sectional view at the line X-X′ in  FIG. 12A , and  FIG. 12C  is a cross-sectional view at the line Y-Y′ in  FIG. 12A ; 
           [0024]      FIG. 13A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 13B  is a cross-sectional view at the line X-X′ in  FIG. 13A , and  FIG. 13C  is a cross-sectional view at the line Y-Y′ in  FIG. 13A ; 
           [0025]      FIG. 14A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 14B  is a cross-sectional view at the line X-X′ in  FIG. 14A , and  FIG. 14C  is a cross-sectional view at the line Y-Y′ in  FIG. 14A ; 
           [0026]      FIG. 15A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 15B  is a cross-sectional view at the line X-X′ in  FIG. 15A , and  FIG. 15C  is a cross-sectional view at the line Y-Y′ in  FIG. 15A ; 
           [0027]      FIG. 16A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 16B  is a cross-sectional view at the line X-X′ in  FIG. 16A , and  FIG. 16C  is a cross-sectional view at the line Y-Y′ in  FIG. 16A ; 
           [0028]      FIG. 17A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 17B  is a cross-sectional view at the line X-X′ in  FIG. 17A , and  FIG. 17C  is a cross-sectional view at the line Y-Y′ in  FIG. 17A ; 
           [0029]      FIG. 18A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 18B  is a cross-sectional view at the line X-X′ in  FIG. 18A , and  FIG. 18C  is a cross-sectional view at the line Y-Y′ in  FIG. 18A ; 
           [0030]      FIG. 19A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 19B  is a cross-sectional view at the line X-X′ in  FIG. 19A , and  FIG. 19C  is a cross-sectional view at the line Y-Y′ in  FIG. 19A ; 
           [0031]      FIG. 20A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 20B  is a cross-sectional view at the line X-X′ in  FIG. 20A , and  FIG. 20C  is a cross-sectional view at the line Y-Y′ in  FIG. 20A ; 
           [0032]      FIG. 21A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 21B  is a cross-sectional view at the line X-X′ in  FIG. 21A , and  FIG. 21C  is a cross-sectional view at the line Y-Y′ in  FIG. 21A ; 
           [0033]      FIG. 22A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 22B  is a cross-sectional view at the line X-X′ in  FIG. 22A , and  FIG. 22C  is a cross-sectional view at the line Y-Y′ in  FIG. 22A ; 
           [0034]      FIG. 23A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 23B  is a cross-sectional view at the line X-X′ in  FIG. 23A , and  FIG. 23C  is a cross-sectional view at the line Y-Y′ in  FIG. 23A ; 
           [0035]      FIG. 24A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 24B  is a cross-sectional view at the line X-X′ in  FIG. 24A , and  FIG. 24C  is a cross-sectional view at the line Y-Y′ in  FIG. 24A ; 
           [0036]      FIG. 25A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 25B  is a cross-sectional view at the line X-X′ in  FIG. 25A , and  FIG. 25C  is a cross-sectional view at the line Y-Y′ in  FIG. 25A ; 
           [0037]      FIG. 26A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 26B  is a cross-sectional view at the line X-X′ in  FIG. 26A , and  FIG. 26C  is a cross-sectional view at the line Y-Y′ in  FIG. 26A ; 
           [0038]      FIG. 27A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 27B  is a cross-sectional view at the line X-X′ in  FIG. 27A , and  FIG. 27C  is a cross-sectional view at the line Y-Y′ in  FIG. 27A ; 
           [0039]      FIG. 28A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 28B  is a cross-sectional view at the line X-X′ in  FIG. 28A , and  FIG. 28C  is a cross-sectional view at the line Y-Y′ in  FIG. 28A ; 
           [0040]      FIG. 29A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 29B  is a cross-sectional view at the line X-X′ in  FIG. 29A , and  FIG. 29C  is a cross-sectional view at the line Y-Y′ in  FIG. 29A ; 
           [0041]      FIG. 30A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 30B  is a cross-sectional view at the line X-X′ in  FIG. 30A , and  FIG. 30C  is a cross-sectional view at the line Y-Y′ in  FIG. 30A ; 
           [0042]      FIG. 31A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 31B  is a cross-sectional view at the line X-X′ in  FIG. 31A , and  FIG. 31C  is a cross-sectional view at the line Y-Y′ in  FIG. 31A ; 
           [0043]      FIG. 32A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 32B  is a cross-sectional view at the line X-X′ in  FIG. 32A , and  FIG. 32C  is a cross-sectional view at the line Y-Y′ in  FIG. 32A ; 
           [0044]      FIG. 33A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 33B  is a cross-sectional view at the line X-X′ in  FIG. 33A , and  FIG. 33C  is a cross-sectional view at the line Y-Y′ in  FIG. 33A ; 
           [0045]      FIG. 34A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 34B  is a cross-sectional view at the line X-X′ in  FIG. 34A , and  FIG. 34C  is a cross-sectional view at the line Y-Y′ in  FIG. 34A ; 
           [0046]      FIG. 35A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 35B  is a cross-sectional view at the line X-X′ in  FIG. 35A , and  FIG. 35C  is a cross-sectional view at the line Y-Y′ in  FIG. 35A ; 
           [0047]      FIG. 36A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 36B  is a cross-sectional view at the line X-X′ in  FIG. 36A , and  FIG. 36C  is a cross-sectional view at the line Y-Y′ in  FIG. 36A ; 
           [0048]      FIG. 37A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 37B  is a cross-sectional view at the line X-X′ in  FIG. 37A , and  FIG. 37C  is a cross-sectional view at the line Y-Y′ in  FIG. 37A ; 
           [0049]      FIG. 38A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 38B  is a cross-sectional view at the line X-X′ in  FIG. 38A , and  FIG. 38C  is a cross-sectional view at the line Y-Y′ in  FIG. 38A ; 
           [0050]      FIG. 39A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 39B  is a cross-sectional view at the line X-X′ in  FIG. 39A , and  FIG. 39C  is a cross-sectional view at the line Y-Y′ in  FIG. 39A ; 
           [0051]      FIG. 40A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 40B  is a cross-sectional view at the line X-X′ in  FIG. 40A , and  FIG. 40C  is a cross-sectional view at the line Y-Y′ in  FIG. 40A ; 
           [0052]      FIG. 41A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 41B  is a cross-sectional view at the line X-X′ in  FIG. 41A , and  FIG. 41C  is a cross-sectional view at the line Y-Y′ in  FIG. 41A ; 
           [0053]      FIG. 42A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 42B  is a cross-sectional view at the line X-X′ in  FIG. 42A , and  FIG. 42C  is a cross-sectional view at the line Y-Y′ in  FIG. 42A ; 
           [0054]      FIG. 43A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 43B  is a cross-sectional view at the line X-X′ in  FIG. 43A , and  FIG. 43C  is a cross-sectional view at the line Y-Y′ in  FIG. 43A ; 
           [0055]      FIG. 44A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 44B  is a cross-sectional view at the line X-X′ in  FIG. 44A , and  FIG. 44C  is a cross-sectional view at the line Y-Y′ in  FIG. 44A ; 
           [0056]      FIG. 45A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 45B  is a cross-sectional view at the line X-X′ in  FIG. 45A , and  FIG. 45C  is a cross-sectional view at the line Y-Y′ in  FIG. 45A ; 
           [0057]      FIG. 46A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 46B  is a cross-sectional view at the line X-X′ in  FIG. 46A , and  FIG. 46C  is a cross-sectional view at the line Y-Y′ in  FIG. 46A ; 
           [0058]      FIG. 47A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 47B  is a cross-sectional view at the line X-X′ in  FIG. 47A , and  FIG. 47C  is a cross-sectional view at the line Y-Y′ in  FIG. 47A ; 
           [0059]      FIG. 48A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 48B  is a cross-sectional view at the line X-X′ in  FIG. 48A , and  FIG. 48C  is a cross-sectional view at the line Y-Y′ in  FIG. 48A ; 
           [0060]      FIG. 49A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 49B  is a cross-sectional view at the line X-X′ in  FIG. 49A , and  FIG. 49C  is a cross-sectional view at the line Y-Y′ in  FIG. 49A ; 
           [0061]      FIG. 50A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 50B  is a cross-sectional view at the line X-X′ in  FIG. 50A , and  FIG. 50C  is a cross-sectional view at the line Y-Y′ in  FIG. 50A ; 
           [0062]      FIG. 51A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 51B  is a cross-sectional view at the line X-X′ in  FIG. 51A , and  FIG. 51C  is a cross-sectional view at the line Y-Y′ in  FIG. 51A ; 
           [0063]      FIG. 52A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 52B  is a cross-sectional view at the line X-X′ in  FIG. 52A , and  FIG. 52C  is a cross-sectional view at the line Y-Y′ in  FIG. 52A ; 
           [0064]      FIG. 53A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 53B  is a cross-sectional view at the line X-X′ in  FIG. 53A , and  FIG. 53C  is a cross-sectional view at the line Y-Y′ in  FIG. 53A ; 
           [0065]      FIG. 54A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 54B  is a cross-sectional view at the line X-X′ in  FIG. 54A , and  FIG. 54C  is a cross-sectional view at the line Y-Y′ in  FIG. 54A ; 
           [0066]      FIG. 55A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 55B  is a cross-sectional view at the line X-X′ in  FIG. 55A , and  FIG. 55C  is a cross-sectional view at the line Y-Y′ in  FIG. 55A ; 
           [0067]      FIG. 56A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 56B  is a cross-sectional view at the line X-X′ in  FIG. 56A , and  FIG. 56C  is a cross-sectional view at the line Y-Y′ in  FIG. 56A ; 
           [0068]      FIG. 57A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 57B  is a cross-sectional view at the line X-X′ in  FIG. 57A , and  FIG. 57C  is a cross-sectional view at the line Y-Y′ in  FIG. 57A ; 
           [0069]      FIG. 58A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 58B  is a cross-sectional view at the line X-X′ in  FIG. 58A , and  FIG. 58C  is a cross-sectional view at the line Y-Y′ in  FIG. 58A ; 
           [0070]      FIG. 59A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 59B  is a cross-sectional view at the line X-X′ in  FIG. 59A , and  FIG. 59C  is a cross-sectional view at the line Y-Y′ in  FIG. 59A ; 
           [0071]      FIG. 60A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 60B  is a cross-sectional view at the line X-X′ in  FIG. 60A , and  FIG. 60C  is a cross-sectional view at the line Y-Y′ in  FIG. 60A ; 
           [0072]      FIG. 61A  is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention,  FIG. 61B  is a cross-sectional view at the line X-X′ in  FIG. 61A , and  FIG. 61C  is a cross-sectional view at the line Y-Y′ in  FIG. 61A ; 
           [0073]      FIG. 62A  is a plane view of primary elements of a semiconductor device according to a second embodiment of the present invention,  FIG. 62B  is a cross-sectional view at the line X-X′ in  FIG. 62A , and  FIG. 62C  is a cross-sectional view at the line Y-Y′ in  FIG. 62A ; 
           [0074]      FIG. 63A  is a plane view of primary elements of a semiconductor device according to a third embodiment of the present invention,  FIG. 63B  is a cross-sectional view at the line X-X′ in  FIG. 63A , and  FIG. 63C  is a cross-sectional view at the line Y-Y′ in  FIG. 63A ; 
           [0075]      FIG. 64A  is a plane view of primary elements of a semiconductor device according to a fourth embodiment of the present invention,  FIG. 64B  is a cross-sectional view at the line X-X′ in  FIG. 64A , and  FIG. 64C  is a cross-sectional view at the line Y-Y′ in  FIG. 64A ; 
           [0076]      FIG. 65A  is a plane view of primary elements of a semiconductor device according to a fifth embodiment of the present invention,  FIG. 65B  is a cross-sectional view at the line X-X′ in  FIG. 65A , and  FIG. 65C  is a cross-sectional view at the line Y-Y′ in  FIG. 65A ; and 
           [0077]      FIG. 66A  is a plane view of primary elements of a semiconductor device according to a sixth embodiment of the present invention,  FIG. 66B  is a cross-sectional view at the line X-X′ in  FIG. 66A , and  FIG. 66C  is a cross-sectional view at the line Y-Y′ in  FIG. 66A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1  
       [0078]      FIG. 1A  is a plane view of an inverter consisting of an nMOS transistor and a pMOS transistor according to a first embodiment of the present invention,  FIG. 1B  is a cross-sectional view at the line X-X′ in  FIG. 1A , and  FIG. 1C  is a cross-sectional view at the line Y-Y′ in  FIG. 1A . 
         [0079]    The inverter according to the first embodiment is described below with reference to  FIGS. 1A to 1C . The inverter according to the first embodiment has a pMOS SGT  148  and an nMOS transistor  149 . The nMOS transistor  149  is formed so as to surround the pMOS SGT  148 . 
         [0080]    The pMOS SGT  148  includes an island-shaped silicon layer  105 . A first gate insulating film  124 A is formed so as to surround the periphery of the island-shaped silicon layer  105 . The first gate insulating film  124 A is a high-K film, for example a silicon oxide film, a silicon nitride film, hafnium oxide, hafnium oxynitride, lanthanum oxide or the like. In addition, a gate electrode  125  is formed so as to surround the periphery of the first gate insulating film  124  A. The gate electrode  125  is, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten or the like. In addition, a first p+ type silicon layer  121  is formed on the top of the island-shaped silicon layer  105  and a second p+ type silicon layer  120  is formed on the bottom of the island-shaped silicon layer  105 . In this embodiment, the first p+ type silicon layer  121  serves as the source scattering layer and the second p+ type silicon layer  120  serves as a drain scattering layer. In addition, the island-shaped silicon layer  105  serves as a channel area. In the present embodiment, a channel is formed in the island-shaped silicon layer  105  by a voltage being impressed on the gate electrode  125  during operation. 
         [0081]    The nMOS transistor  149  includes a second silicon layer  103 . The nMOS transistor  149  shares the gate electrode  125  with the pMOS SGT  148 . A second gate insulating film  124 B is formed so as to contact the second silicon layer  103  while surrounding a part of the periphery of the gate electrode  125  of this pMOS transistor. The second gate insulating film  124 B is a high-K film, similar to the first gate insulating film  124 A. In addition, a first n+ type silicon layer  117  is formed on the top of the second silicon layer  103  and a second n+ type silicon layer  118  is formed on the bottom of the second silicon layer  103 . In this embodiment, the first n+ type silicon layer  117  serves as a source scattering layer and the second n+ type silicon layer  118  serves as a drain scattering layer  118 . In addition, the second silicon layer  103  serves as a channel area. In the present embodiment, a channel is formed in the second silicon layer  103  by a voltage being impressed on the gate electrode  125  during operation. 
         [0082]    In addition, the nMOS transistor  149  and the pMOS SGT  148  share the gate electrode  125  and the distance between the two transistors is extremely short due to the nMOS transistor surrounding a part of the periphery of the pMOS SGT  148 . 
         [0083]    In addition, a third p+ type silicon layer  102  is formed on the bottom of the second n+ type silicon layer  118  and the second p+ type silicon layer  120 . 
         [0084]    Furthermore, a first silicon-metal compound layer  133  and a fourth silicon-metal compound layer  134  are formed on a part of the side wall of the second n+ type silicon layer  118  and the third p+ type silicon layer  102 , a second silicon-metal compound layer  132  is formed on the top of the first n+ type silicon layer  117  and a third silicon-metal compound layer  131  is formed on the top of the first p+ type silicon layer. As the metal comprising the silicon-metal compound layers, nickel or cobalt may be used, for example. Through these silicon-metal compound layers, the second n+ type silicon layer  118 , the third p+ type silicon layer  102 , the first n+ type silicon layer  117  and the first p+ type silicon layer are connected to the below-described contacts. Through this, the resistances of the gate, source and drain are reduced. 
         [0085]    A contact  142  is formed so as to connect to the gate electrode  125 , and an input terminal line  144  is formed so as to connect to that contact  142 . In addition, a contact  143  is formed so as to connect to the first silicon-metal compound layer  133  and an output terminal line  145  is formed so as to connect to that contact  143 . A contact  141  is formed so as to connect to the second silicon-metal compound layer  132  and a VSS power line  147  is formed so as to connect to that contact  141 . A contact  140  is formed so as to connect to the third silicon-metal compound layer  131  and a VDD power line  146  is formed so as to connect to that contact  140 . 
         [0086]    In addition, an interlayer film  135  such as an oxide film is formed around the periphery of the pMOS SGT  148  and the nMOS transistor  149 . 
         [0087]    Furthermore, it is preferable for Wp≈2 Wn, where Wn is the length of an arc along which the second semiconductor layer  103  is in contact with a part of the periphery of the second gate insulating film  124  and Wp is the outer peripheral length of the island-shaped semiconductor layer  105 . In this case, it is possible for the gate width of the pMOS transistor  149  to be double the gate width of the nMOS SGT  148 . 
         [0088]    In such a case, it is preferable that Lp≈Ln in which Ln is the channel length of the second silicon layer and Lp is the channel length of the island-shaped silicon layer. 
         [0089]    Through the above, it is possible for the inverter circuit to be composed of only the pMOS SGT  148  and the nMOS transistor  149 . 
         [0090]    Through the above, the inverter circuit is composed of the pMOS SGT  148  and the nMOS transistor  149 . 
         [0091]    Through the above composition, the inverter according to the present invention is composed of SGTs that can be highly integrated. Through this, it is possible to make semiconductor devices finer by using this inverter. 
         [0092]    An exemplary production process for forming the inverter equipped with an SGT according to this embodiment of the present invention will be described hereafter with reference to  FIGS. 2A to 61C . In these figures, the same components are referred to by the same reference numbers. In each figure, part A is a planar view, part B is a cross-sectional view at a line X-X′, and part C is a cross-sectional view at a line Y-Y′. 
         [0093]    Referring to  FIGS. 2A to 2C , a p type or non-doped silicon layer  103  is formed on an oxide film  101  and a dopant such as boron is implanted on the bottom of this silicon layer  103  to form a third p+ type silicon layer  102 . 
         [0094]    Referring to  FIGS. 3A to 3C , a resist  104  for forming an n type silicon layer is formed on the p type or non-doped silicon layer  103 . When a non-doped silicon layer is used as the silicon layer  103 , this step is unnecessary. 
         [0095]    Referring to  FIGS. 4A to 4C , a dopant such as phosphorus is implanted in an area where an nMOS is slated to be formed to form an n type silicon layer  105 . When a non-doped silicon layer is used as the silicon layer  103 , this step is unnecessary. In this case, the silicon layer  105  is not an n type but a non-doped silicon layer. 
         [0096]    Referring to  FIGS. 5A to 5C , the resist  104  is removed and heat treatment is performed. When a non-doped silicon layer is used as the silicon layer  103 , this step is unnecessary. 
         [0097]    Referring to  FIGS. 6A to 6C , an oxide film  106  is deposited on the result of the above steps, and on top of that a nitride film  107  is formed. 
         [0098]    Referring to  FIGS. 7A to 7C , a resist  108  for forming an island-shaped silicon layer  105  is formed on the nitride film  107  above the silicon layer  105 . 
         [0099]    Referring to  FIGS. 8A to 8C , the nitride film  107  and oxide film  106  are etched and the parts not covered by the resist  108  are removed. 
         [0100]    Referring to  FIGS. 9A to 9C , the resist  108  is removed. 
         [0101]    Referring to  FIGS. 10A to 10C , an oxide film  109  is formed on the result of the above steps. 
         [0102]    Referring to  FIGS. 11A to 11C , the oxide film  109  is partially removed through etching and left in a sidewall shape on the side wall of the nitride film  107  and the oxide film  106  to form a nitride film sidewall  109 A. 
         [0103]    Referring to  FIGS. 12A to 12C , a nitride film  110  is formed on the result of the above steps. 
         [0104]    Referring to  FIGS. 13A to 13C , the nitride film  110  is partially removed through etching and left in a sidewall shape on the side wall of the oxide film sidewall  109 A to form a nitride film sidewall  110 A. 
         [0105]    Referring to  FIGS. 14A to 14C , a resist  111  for forming a second silicon layer is formed. 
         [0106]    Referring to  FIGS. 15A to 15C , the nitride film sidewall  110 A is partially removed through etching to form a nitride film hard mask  110 B for forming a second silicon layer. 
         [0107]    Referring to  FIGS. 16A to 16C , the oxide film sidewall  109 A is partially removed through etching. 
         [0108]    Referring to  FIGS. 17A to 17C , the resist  111  is removed. 
         [0109]    Referring to  FIGS. 18A to 18C , a resist  112  for an output terminal  501  (see  FIGS. 1A to 1C ) is formed. 
         [0110]    Referring to  FIGS. 19A to 19C , the silicon layer  103  is partially removed through etching to form an output terminal part  502 . 
         [0111]    Referring to  FIGS. 20A to 20C , the resist  112  is removed. 
         [0112]    Referring to  FIGS. 21A to 21C , the oxide film  109  is removed through etching. 
         [0113]    Referring to  FIGS. 22A to 22C , the silicon layers  103  and  105  are partially removed through etching to form an island-shaped silicon layer  105 A and a second silicon layer  103 A. 
         [0114]    Referring to  FIGS. 23A to 23C , the nitride film  107  and oxide film  106  are removed 
         [0115]    Referring to  FIGS. 24A to 24C , a nitride film  113  is formed on the surface of the result of the above steps. 
         [0116]    Referring to  FIGS. 25A to 25C , the nitride film  113  is partially removed through etching, and nitride film sidewalls  114  and  115  for protecting the channels during later ion implantation are formed on the sidewalls of the second silicon layer  103 A and the island-shaped silicon layer  105 A, respectively. 
         [0117]    Referring to  FIGS. 26A to 26C , a resist  116  for forming an n+ type silicon layer is formed at the periphery of the island-shaped silicon layer  105 A. 
         [0118]    Referring to  FIGS. 27A to 27C , a dopant such as arsenic is implanted on the top and bottom of the second silicon layer  103 A to form a first n+ type silicon layer  117  and a second n+ type silicon layer  118 , respectively. 
         [0119]    Referring to  FIGS. 28A to 28C , the resist  116  is removed. 
         [0120]    Referring to  FIGS. 29A to 29C , a resist  119  for forming a p+ type silicon layer is formed on the result of the above steps except the surroundings of the island-shaped silicon layer  105 A. 
         [0121]    Referring to  FIGS. 30A to 30C , a dopant such as boron is implanted on the top and bottom of the island-shaped silicon layer  105 A to form a first p+ type silicon layer  121  and a second p+ type silicon layer  120 , respectively. 
         [0122]    Referring to  FIGS. 31A to 31C , the resist  119  is removed and heat treatment is performed. 
         [0123]    Referring to  FIGS. 32A to 32C , an oxide film  122  is formed on the result of the above steps, then flattened and etched back to expose the first n+ type silicon layer  117  and first p+ type silicon layer  121 . 
         [0124]    Referring to  FIGS. 33A to 33C , a resist  123  for forming a gate part  503  (see  FIGS. 42A to 42C ) is formed. 
         [0125]    Referring to  FIGS. 34A to 34C , the oxide film  122  of the area where gate part formation is slated is removed through etching. 
         [0126]    Referring to  FIGS. 35A to 35C , the resist  123  is removed. 
         [0127]    Referring to  FIGS. 36A to 36C , the nitride films  114  and  115  are etched and removed from the sidewall surface of the island-shaped silicon layer  105 A and the sidewall surface of the second silicon layer  103 A facing this sidewall surface. 
         [0128]    Referring to  FIGS. 37A to 37C , a high-K film  124  is formed on the surface of the result of the above steps. The high-K film  124  contains at least one of the following substances: silicon oxynitride film, silicon nitride film, hafnium oxide, hafnium oxynitride, and lanthanum oxide. Then, a metal layer  125  is formed. The metal layer  125  contains at least one of the following substances: titanium, titanium nitride, tantalum, tantalum nitride, and tungsten 
         [0129]    Referring to  FIGS. 38A to 38C , a nitride film  126  is formed on the result of the above steps. 
         [0130]    Referring to  FIGS. 39A to 39C , a resist  127  for a gate pad  504  (see  FIGS. 42A to 42C ) is formed. 
         [0131]    Referring to  FIGS. 40A to 40C , the nitride film  126  is partially removed through etching. 
         [0132]    Referring to  FIGS. 41A to 41C , the resist  127  is removed. 
         [0133]    Referring to  FIGS. 42A to 42C , the metal layer  125  is partially removed through etching to form a gate electrode  125 A. 
         [0134]    Referring to  FIGS. 43A to 43C , a nitride film  128  is formed on the result of the above step. 
         [0135]    Referring to  FIGS. 44A to 44C , the nitride film  128  is partially removed through etching to form a nitride film sidewall  128 A. 
         [0136]    Referring to  FIGS. 45A to 45C , the part of the high-K film  124  on the top surface of the above result is removed through etching. The part of the high-K film  124  remaining on the sidewall of the island-shaped silicon layer  105 A is the first gate insulating film  124 A, and the part of the high-K film remaining on the sidewall of the second silicon layer  103 A is the second gate insulating film  124 B. 
         [0137]    Referring to  FIGS. 46A to 46C , a resist  129  for etching the oxide film  122  is formed 
         [0138]    Referring to  FIGS. 47A to 47C , the oxide film  122  is partially removed through dry etching. 
         [0139]    Referring to  FIGS. 48A to 48C , the resist  129  is removed. 
         [0140]    Referring to  FIGS. 49A to 49C , the oxide film  122  is partially removed through wet etching. 
         [0141]    Referring to  FIGS. 50A to 50C , a nitride film  130  is formed on the result of the above steps. 
         [0142]    Referring to  FIGS. 51A to 51C , the nitride film  130  is partially removed through etching to form a nitride film sidewall  130 A. 
         [0143]    Referring to  FIGS. 52A to 52C , the oxide film  122  is partially removed through dry etching. 
         [0144]    Referring to  FIGS. 53A to 53C , the oxide film  122  is wet-etched to expose the nitride film  114 . 
         [0145]    Referring to  FIGS. 54A to 54C , the nitride film sidewall  130 A and part of the nitride film  114  are removed through etching to expose parts of the sidewalls of the second n+ type silicon layer  118  and third p+ type silicon layer  102 . 
         [0146]    Referring to  FIGS. 55A to 55C , a metal film such as nickel and cobalt is deposited on parts of the sidewalls of the second n+ type silicon layer  118  and third p+ type silicon layer  102 , above the first n+ type silicon layer  117 , and above the first p+ type silicon layer  121 , heat treatment is performed, this metal and the silicon with which it is contact are reacted and any unreacted metal film is removed. Through this, a first silicon-metal compound layer  133  and a fourth silicon-metal compound layer  134  are formed on parts of the sidewalls of the second n+ type silicon layer  118  and third p+ type silicon layer  102 , a second silicon-metal compound layer  132  is formed above the first n+ type silicon layer  117 , and a third silicon-metal compound layer  131  is formed above the first p+ type silicon layer  121 . 
         [0147]    Referring to  FIGS. 56A to 56C , an interlayer film  135  composed of an oxide film or the like is formed on the result of the above steps. 
         [0148]    Referring to  FIGS. 57A to 57C , a contact hole  136  is formed above the third silicon-metal compound layer  131 . 
         [0149]    Referring to  FIGS. 58A to 58C , a contact hole  137  is formed above the second silicon-metal compound layer  132  and a contact hole  138  is formed above the gate electrode  125 . 
         [0150]    Referring to  FIGS. 59A to 59C , a contact hole  139  is formed so as to expose the first silicon-metal compound layer  133 . 
         [0151]    Referring to  FIGS. 60A to 60C , a metal film composed of tungsten or the like is deposited in the contact holes  136 ,  137 ,  138  and  139  to form contacts  140 ,  141 ,  142 , and  143 . 
         [0152]    Referring to  FIG. 61A to 61C , an input terminal line  144 , an output terminal line  145 , a VDD power line  146 , and a VSS power line  147  are formed on the result of the above steps. 
         [0153]      FIGS. 62A ,  62 B, and  62 C show the planar and cross-sectional structures of another embodiment of the semiconductor device of the present invention.  FIG. 62A  is a plane view,  FIG. 62B  is a cross-sectional view at the line X-X′, and  FIG. 62C  is a cross-sectional view at the line Y-Y′. 
         [0154]    In this embodiment, the following is formed: a first gate insulating film  270  in contact with at least a part of an island-shaped semiconductor  205 ; a gate electrode  225  having a surface in contact with the first gate insulating film  270 ; a second gate insulating film  271  in contact with another surface of the gate electrode  225 ; a second silicon layer  203  in contact with the second gate insulating film  271 ; a first p+ type silicon layer  221  arranged on the top of the island-shaped silicon layer  205 ; a second p+ type silicon layer  220  arranged on the bottom of the island-shaped silicon layer  205 ; a first n+ type silicon layer  217  arranged on the top of the second silicon layer  203 ; a second n+ type silicon layer  218  arranged on the bottom of the second silicon layer  203 ; a third p+ type silicon layer  202  arranged on the bottom of the second n+ type silicon layer  218  and second p+ type silicon layer  220 ; a first silicon-metal compound layer  233  formed on parts of the sidewalls of the second n+ type silicon layer  218  and third p+ type silicon layer  202 , and a fourth silicon-metal compound layer  234 ; a second silicon-metal compound layer  232  formed on the top of the first n+ type silicon layer  217 ; and a third silicon-metal compound layer  231  formed on the top of the first p+ type silicon layer  221 . 
         [0155]    A contact  242  is so formed as to be connected to the gate electrode  225 . An input terminal line  244  is so formed as to be connected to the contact  242 . 
         [0156]    A contact  243  is so formed as to be connected to the first silicon-metal compound layer  233 . An output terminal line  245  is so formed as to be connected to the contact  243 . 
         [0157]    A contact  241  is so formed as to be connected to the second silicon-metal compound layer  232 . A VSS power line  247  is so formed as to be connected to the contact  241 . 
         [0158]    A contact  240  is so formed as to be connected to the third silicon-metal compound layer  231 . A VDD power line  246  is so formed as to be connected to the contact  240   
         [0159]      FIGS. 63 to 66  show modifications of the semiconductor device of the present invention. Each of  FIGS. 63 to 66  shows planar structures in part A and cross-sectional structures in parts B and C. In each figure, part A is a plane view, part B is a cross-sectional view at a line X-X′, and part C is a cross-sectional view at a line Y-Y′ 
       Modification 1  
       [0160]    In this modification as shown in  FIG. 63A , the second gate insulating film  124 B is arranged between the nMOS transistor  149  and gate electrode  125  in the area where the nMOS transistor  149  having an arc-shaped cross-section surrounds the gate electrode  125 . In this point, the embodiment in  FIG. 63  is different from the embodiment in  FIG. 1 . In this way, the gate insulating film can be minimized insofar as the nMOS transistor does not make contact with the gate electrode. 
       Modification 2  
       [0161]    In the modification, as shown in  FIG. 64A , the nMOS transistor  149  has a rectangular cross-section. Furthermore, the second gate insulating film  124 B is arranged between the nMOS transistor  149  and gate electrode  125  in the area where the nMOS transistor  149  surrounds the gate electrode  125 . In these points, the embodiment in  FIG. 64  is different from the embodiment in  FIG. 1   
       Modification 3  
       [0162]    In this modification, as shown in  FIG. 65A , the pMOS transistor  148  and gate electrode  125  have a square cross-section, not a circular cross-section. Furthermore, the second gate insulating film  124 B is arranged between the nMOS transistor  149  and gate electrode  125  in the area where the nMOS transistor  149  surrounds the gate electrode  125 . In these points, the embodiment in  FIG. 65  is different from the embodiment in  FIG. 1 . Here, the pMOS transistor  148  and gate electrode  125  can have a polygonal cross-section besides the aforementioned square. 
       Modification 4  
       [0163]    In this modification, as shown in  FIG. 66A , the nMOS transistor  149  has a circular cross-section. Furthermore, the second gate insulating film  124 B is arranged between the nMOS transistor  149  and gate electrode  125  in the area where the nMOS transistor  149  surrounds the gate electrode  125 . In these points, the embodiment in  FIG. 66  is different from the embodiment in  FIG. 1 . 
         [0164]    In the above embodiments, an inverter was described as an example of the semiconductor device using SGTs of the present invention, but the present invention is not limited to this and can be applied to other types of semiconductor devices. 
         [0165]    In addition, the shapes of the members are arbitrary, and naturally appropriate variations to the specific structure of parts are possible. 
         [0166]    Having described and illustrated the principles of this application by reference to one (or more) preferred embodiment(s), it should be apparent that the preferred embodiment(s) may be modified in arrangement and detail without departing from the principles disclosed herein and that it is intended that the application be construed as including all such modifications and variations insofar as they come within the spirit and scope of the subject matter disclosed herein.