Abstract:
A method of decoding a digital signal includes processing the digital using a delay operation in accordance with a frequency characteristic of 1+D, where D is an output signal of the delay element. The processed digital signal is then converted to a three level conversion signal (0, positive, negative). The conversion signal is then processed in accordance with a frequency of 1/(1+D) to generate a decoded signal. The conversion signal is also checked to determine if there is a conversion error. If a conversion error is detected, propagation of the error is restricted, such that a correct decoded signal is provided.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method and an apparatus for decoding a digital signal, and, more particularly, to a digital signal recording/reproducing apparatus which performs a decoding process on recorded digital signals and a digital signal transmission apparatus which performs a decoding process on transmitted digital signals. 
     A digital signal recording/reproducing apparatus uses a PR (Partial Response) class IV algorithm that performs NRZI code conversion in order to improve the recording density of magnetic recording media and improve the S/N ratio of decoded digital signals. Because a magnetic recording/reproducing system has a differential characteristic, recording and reproduction of data spreads the signal waveform, which causes an intersymbol interference. The PR system uses the intersymbol interference positively to shape a signal such that the power spectrum of a code is adequate for the transmission characteristic of a transmission line. 
     FIG. 1 is a schematic block diagram of a conventional digital signal recording/reproducing apparatus  100  which uses the PR class IV algorithm. A precoder  1  has a modulo-2 digital adder  2   a  and a 1-bit delay operation element  3   a  and has the characteristic of 1/(1+D). The precoder  1  receives, for example, a digital input signal Din as shown in FIG. 1, and performs a process of 1/(1+D) on the input signal Din to convert the input signal Din to an NRZI code S 1  as shown in FIG.  2 . The polarity of the NRZI code is inverted every time the input signal Din rises from “0” to “1”. The polarity inversion means a transition of a signal value from “1” to “0” or from “0” to “1”. 
     A write buffer  4  whose structure is similar to that of the precoder  1  has the characteristic of 1/(1−D). The write buffer  4  produces an output signal S 2  by giving an intersymbol interference opposite to the one that is given by a recording/reproducing system to the NRZI code S 1  from the precoder  1 . 
     A recording/reproducing system  5  has a write head  6 , a recording medium  7  and a read head  8 . The output signal S 2  of the write buffer  4  is written on the recording medium  7  via the write head  6  and the written signal is read from the recording medium  7  via the read head  8 . 
     The writing operation to the recording medium  7  by the write head  6  has the differential characteristic of (1−D), and the operation of the read head  8  and an equalizer  9  has the differential characteristic of (1+D). Therefore, the recording/reproducing system  5  and the equalizer  9  carry out a process of {(1−D)(1+D)}, thereby accomplishing PR class IV impulse response. 
     The equalizer  9  performs PR equalization on an analog read signal generated by the read head  8 , thereby producing an equalization signal S 3 . The equalization signal S 3  is a multi-value signal as shown in FIG.  2 . 
     A comparator  10  compares the equalization signal S 3  from the equalizer  9  with threshold values A and B (shown in FIG. 2) and produces a decoded signal Dout of “0” or “1” which coincides with the input signal Din. When the level of the equalization signal S 3  is higher than the threshold value A or is lower than the threshold value B, “1” is output otherwise “0” is output. 
     For digital signal recording/reproducing apparatuses which use recording media, such as a floppy disk, that needs swapping, however, the format of signals to be recorded on recording media is specified. Since the specifications states that the input signal Din is recorded on the recording medium using only a write buffer, the digital signal recording/reproducing apparatuses cannot use a precoder. 
     A digital signal recording/reproducing apparatus of a peak detection type which does not use a precoder cannot implement PR-system based recording and reproduction operations using a precoder. As a solution to this shortcoming, Japanese Unexamined Patent Publication Nos. 5-325425, 5-307837, 8-147893 and 8-77712 disclose apparatuses capable of adapting the PR system without having a precoder at the preceding stage of the recording/reproducing system. However, decoding circuits in the apparatuses described in these publications are complicated. 
     By contrast, the recording/reproducing apparatus  100  in FIG. 1 is of a linear type, where the characteristics of the system do not change even if the order of the individual blocks is changed. 
     One possible modification is a recording/reproducing apparatus  110  shown in FIG. 3 which has a precoder equivalent circuit  11  located after the comparator  10 . The write buffer  4 , recording/reproducing system  5  and comparator  10  in FIG. 3 are identical to those in FIG.  1 . 
     The operation of the recording/reproducing apparatus  110  in FIG. 3 will now be discussed referring to the waveform diagram of FIG.  4 . The write buffer  4  receives the input signal Din and provides an output signal S 4  according to the characteristic of (1−D) to the recording/reproducing system  5 . The recording/reproducing system  5  provides its output signal having a characteristic of (1−D)(1+D) to the equalizer  9 , which in turn provides an equalization signal S 5  to the comparator  10 . The comparator  10  performs a comparison operation and provides an output signal S 6  to the precoder equivalent circuit  11 . The precoder equivalent circuit  11  performs an operation of 1/(1+D) on the output signal S 6 , thus generating a decoded signal Dout which is substantially the same as the input signal Din. 
     Even if the input signal Din has been recorded on the recording medium  7  without using a precoder, the signal that is read by the recording/reproducing system  5  can be decoded by the PR system using the PR equalizer  9  and the precoder equivalent circuit  11 . 
     If the operation of the recording/reproducing system  5  or the equalizer  9  in the digital signal recording/reproducing apparatus  110  causes an arbitrary bit b 1  in the equalization signal S 5  to contain noise n 1  which is greater than the threshold value as shown in FIG. 5, however, the comparator  10  performs an operation different from the one illustrated in FIG. 4 so that the bit b 1  of the output signal S 6  is inverted. Then, the feedback loop of the precoder equivalent circuit  11  inverts all the bits in the decoded signal Dout after the bit b 1 , causing an error to propagate endlessly. This type of digital signal recording/reproducing apparatus is therefore not practical. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a digital signal decoding apparatus which performs a decoding operation using a PR system while suppressing propagation of an error without a precoder at the preceding stage of a recording/reproducing system or a transmission system. 
     In a first aspect of the present invention, a method of decoding a digital signal is provided. First, the digital signal is processed using a delay operation element in accordance with a frequency characteristic of 1+D, where D is an output signal of the delay operation element. The processed digital signal is converted to a conversion signal of at least three values having polarities of 0, positive and negative. A decoded signal is generated by processing the conversion signal in accordance with a frequency characteristic of 1/(1+D). Then, it is detected if there is a conversion error in the conversion signal and a correct signal is generated by restricting propagation of the conversion error to the decoded signal when the conversion error is detected. 
     In a second aspect of the present invention, a method of decoding a digital signal is provided. First, a 1/(1−D) process is performed on the digital signal using a delay operation element, where D is an output signal of the delay operation element to generate a write signal. The write signal is written on a recording medium in accordance with a (1−D) characteristic. The write signal written on the recording medium is read in accordance with a (1+D) characteristic and PR equalization is performed on the read signal to generate a PR equalization signal. Then, the PR equalization signal is converted to a 3-value signal of 1, 0 and −1 and a decoded signal is generated by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). A correct decoded signal is generated by restricting propagation of an error to the decoded signal when the output signal of the delay operation element is 1 or −1 and the digital signal is 0, or when a polarity of the output signal of the delay operation element is opposite to a polarity of the digital signal. 
     In a third aspect of the present invention, a method of decoding a digital signal is provided. First, a 1/(1−D) process is performed on the digital signal using a delay operation element, where D is an output signal of the delay operation element to generate a transmission signal. The transmission signal is transmitted using a transmission line having a (1−D) characteristic and PR equalization is performed on the transmission signal in accordance with a (1+D) characteristic to generate a PR equalization signal. Then, the PR equalization signal is converted to a 3-value signal of 1, 0 and −1 and a decoded signal is generated by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). A correct decoded signal is generated by restricting propagation of an error to the decoded signal when the output signal of the delay operation element is 1 or −1 and the digital signal is 0, or when a polarity of the output signal of the delay operation element is opposite to a polarity of the digital signal. 
     In a fourth aspect of the present invention, an apparatus for decoding a digital signal processed in accordance with a frequency characteristic of 1+D is provided. D is an output signal of a first delay operation element. The apparatus includes a comparator to convert the digital signal to a conversion signal of at least three values having polarities of 0, positive and negative. An error-propagation restriction circuit is connected to the comparator to generate a decoded signal by processing the conversion signal in accordance with a frequency characteristic of 1/(1+D). The error-propagation restriction circuit detects if there is a conversion error in the conversion signal, restricts propagation of the conversion error to the decoded signal when detecting the conversion error, and generates a correct decoded signal. 
     In a fifth aspect of the present invention, a digital signal recording/reproducing apparatus is provided. The apparatus includes a write buffer including a first delay operation element to perform a 1/(1−D) process on a digital signal, where D is an output signal of the first delay operation element, and generate a write signal. A recording/reproducing system is connected to the write buffer to write the write signal on a recording medium in accordance with a (1−D) characteristic and read the write signal written on the recording medium in accordance with a (1+D) characteristic. An equalizer is connected to the recording/reproducing system to perform PR equalization on the signal read by the recording/reproducing system and generate a PR equalization signal. A comparator is connected to the equalizer to convert the PR equalization signal to a 3-value signal of 1, 0 and −1. An error-propagation restriction circuit is connected to the comparator and includes a second delay operation element to generate a decoded signal by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). The error-propagation restriction circuit generates a correct decoded signal by restricting propagation of an error to the decoded signal when the output signal of the second delay operation element is positive or negative and the digital signal is 0, or when a polarity of the output signal of the second delay operation element is opposite to a polarity of the digital signal. 
     In a sixth aspect of the present invention, a digital signal transmission apparatus is provided. The apparatus includes a write buffer including a first delay operation element to perform a 1/(1−D) process on a digital signal, where D is an output signal of the first delay operation element, and generate a transmission signal. A transmission line is connected to the write buffer to transmit the transmission signal in accordance with a (1−D) characteristic. An equalizer is connected to the transmission line to perform PR equalization on the transmission signal, transmitted via the transmission line, in accordance with a (1+D) characteristic and generate a PR equalization signal. A comparator is connected to the equalize to convert the PR equalization signal to a 3-value signal of 1, 0 and −1. An error-propagation restriction circuit is connected to the comparator and includes a second delay operation element to generate a decoded signal by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). The error-propagation restriction circuit generates a correct decoded signal by restricting propagation of an error to the decoded signal when the output signal of the second delay operation element is positive or negative and the digital signal is 0, or when a polarity of the output signal of the second delay operation element is opposite to a polarity of the digital signal. 
     Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
     FIG. 1 is a schematic block diagram of a first conventional digital signal recording/reproducing apparatus; 
     FIG. 2 is a waveform diagram illustrating the operation of the digital signal recording/reproducing apparatus of FIG. 1; 
     FIG. 3 is a schematic block diagram of a second conventional digital signal recording/reproducing apparatus; 
     FIG. 4 is a first waveform diagram illustrating the operation of the digital signal recording/reproducing apparatus of FIG. 3; 
     FIG. 5 is a second waveform diagram illustrating the operation of the digital signal recording/reproducing apparatus of FIG. 3; 
     FIG. 6 is a schematic block diagram of a magnetic recording/reproducing apparatus according to a first embodiment of the present invention; 
     FIG. 7 is a schematic block diagram of a comparator of the magnetic recording/reproducing apparatus of FIG. 6; 
     FIG. 8 is a schematic block diagram of an error-propagation restriction circuit of the magnetic recording/reproducing apparatus of FIG. 6; 
     FIG. 9 is a truth table of the error-propagation restriction circuit of FIG. 8; 
     FIG. 10 is an explanatory diagram showing criteria for error determination; 
     FIG. 11 is a waveform diagram illustrating the operation of the magnetic recording/reproducing apparatus of FIG. 6; 
     FIG. 12 is a schematic block diagram of a magnetic recording/reproducing apparatus according to a second embodiment of the present invention; 
     FIG. 13 is a schematic block diagram of an error-propagation restriction circuit of the magnetic recording/reproducing apparatus of FIG. 12; 
     FIG. 14 is a waveform diagram illustrating the operation of the magnetic recording/reproducing apparatus of FIG. 12; 
     FIG. 15 is a schematic block diagram of a digital signal transmission apparatus according to a third embodiment of the present invention; 
     FIG. 16 is a schematic block diagram of a digital signal transmission apparatus according to a fourth embodiment of the present invention; 
     FIG. 17 is a schematic block diagram of a digital signal transmission apparatus according to a fifth embodiment of the present invention; and 
     FIG. 18 is a schematic block diagram of a digital signal transmission apparatus according to a sixth embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the drawings, like numerals are used for like elements throughout. 
     First Embodiment 
     FIG. 6 is a schematic block diagram of a magnetic recording/reproducing apparatus  200  as a digital signal recording/reproducing apparatus according to a first embodiment of the present invention. The structures of a write buffer  4 , a recording/reproducing system  5  and an equalizer  9  and the operations of the components from the write buffer  4  to the equalizer  9  are the same as those of the prior art shown in FIGS. 3 and 4. 
     A comparator  21  receives an equalization signal S 5  from the equalizer  9  and generates a 2-bit output signal X 1  and X 0 . As shown in FIG. 7, the comparator  21  has three registers  22   a  to  22   c,  a comparison circuit  23  and a conversion circuit  24 . 
     The first register  22   a  stores a high-level threshold value A set by an external unit (not shown). The second register  22   b  stores a low-level threshold value B set by the external unit. The third register  22   c  holds the equalization signal S 5  from the equalizer  9 . 
     The comparison circuit  23  compares the equalization signal S 5  from the equalizer  9  stored in the third register  22   c  with the threshold values A and B and provides one of three values “1”, “0” and “−1” to the conversion circuit  24 . Specifically, the comparison circuit  23  outputs “1” when the of the equalization signal S 5  is higher than the threshold value A, outputs “−1” when the level of the equalization signal S 5  is lower than the threshold value B, and outputs “0” when the level of the equalization signal S 5  lies between the threshold values A and B. 
     The conversion circuit  24  converts the 3-value signal, supplied from the comparison circuit  23 , to the 2-bit output signal X 1  and X 0 . The conversion circuit  24  outputs X 1 =0 and X 0 =1 when “1” is output from the comparison circuit  23 , outputs X 1 =0 and X 0 =0 when “0” is output from the comparison circuit  23 , and outputs X 1 =1 and X 0 =1 when “−1” is output from the comparison circuit  23 . 
     FIG. 8 is a schematic block diagram of an error-propagation restriction circuit  25   a.  The output signal X 1  of the comparator  211  is inverted by an inverter circuit  26   a  and the inverted output signal X 1  is supplied to a first input terminal of a NAND gate  27 . The output signal X 0  of the comparator  21  is supplied to a second input terminal of the NAND gate  27 . 
     The output signal of the NAND gate  27  is supplied to a first input terminal of a NOR gate  28   a  whose output signal is supplied to a first input terminal of an OR gate  29 . The OR gate  29  provides an output signal y 0  which is a decoded signal Dout. 
     The output signal y 0  is supplied to a delay operation element  31   b  whose output signal Dy 0  is supplied to a first input terminal of a NOR gate  28   c.  The output signal of the NOR gate  28   c  is supplied to a first input terminal of a NOR gate  28   b  whose output signal is sent to a second input terminal of the NOR gate  28   a.    
     The output signal X 1  of the comparator  21  is supplied to a first input terminal of an AND gate  30  whose output signal y 1  is supplied to a second input terminal of the OR gate  29  and a delay operation element  31   a.  The output signal Dy 1  of the delayloperation element  31   a  is supplied to second input terminals of the NOR gates  28   b  and  28   c  and an inverter circuit  26   b.  The output signal of the inverter circuit  26   b  is supplied to a second input terminal of the AND gate  30 . 
     The logical expression of the error-propagation restriction circuit  25   a  is given by the following equation 1. 
     
       
           y   0 = {overscore (X 1 )}*   X   0 *( {overscore (Dy 1 )}*   {overscore (Dy 0 )}+   Dy   1 )+ X   1 * {overscore (Dy 1 )}   
       
     
     
       
           y   1   =X   1 * {overscore (Dy 1 )}   (1) 
       
     
     FIG. 9 depicts the truth table of the error-propagation restriction circuit  25   a.  The error-propagation restriction circuit  25   a  prevents the propagation of an error in the output signal y 0  caused by noise in the input signals X 1  and X 0  while carrying out a process of 1/(1+D) equivalent to the operation of a precoder. 
     FIG. 10 presents a truth table in a case where the input signals X 1  and X 2 , the output signals y 0  and y 1  and the output signals Dy 0  and Dy 1  of the delay operation elements  31   b  and  31   a  are respectively expressed by an input signal x, an output signal y and an output signal Dy. 
     As apparent from this truth table, the error-propagation restriction circuit  25   a  generates the output signal y that indicates invalidation of the output signal Dy when receiving the input signal x of “0” with the output signal Dy of the delayloperation element being “1” or “−1”. That is, the error-propagation restriction circuit  25   a  generates the output signal y which is acquired by giving a value having the opposite polarity to that of the value of the output signal Dy of the delay operation element to the result of the process of 1/(1+D). 
     When one of the input signal x and the output signal Dy of the delay operation element is “1” and the other is “−1”, the error-propagation restriction circuit  25   a  generates the output signal y that indicates invalidation of the output signal Dy. That is, the error-propagation restriction circuit  25   a  generates the output signal y which is acquired by giving a value having the opposite polarity to that of the value of the output signal Dy of the delay operation element to the result of the process of 1/(1+D). 
     The operation of the error-propagation restriction circuit  25   a  is based on the following principle. With the output signals X 0  and X 1  of the comparator  21  regarded as a 3-value signal (1, 0, −1), “1” indicates the position of the inversion of magnetization from, for example, the S polarity to the N polarity on the recording medium  7 , “−1” indicates the position of the inversion of magnetization from the N polarity to the S polarity, and “0” indicates a position of other than the inversions of magnetization. 
     For a magnetic substance, the inversion of magnetization is no more than the transition from “1” to “−1” or from “−1” to “1”. If it is detected that “0” follows “1” and “1” follows “0”, therefore, it can be considered as an error. Likewise, if it is detected that “0” follows “−1” and “−1” follows “0”, it can also be considered as an error. 
     The error-propagation restriction circuit  25   a  automatically detects such an error and prevents this error from affecting the subsequent bits. 
     The operation of the magnetic recording/reproducing apparatus  200  will be discussed below with reference to FIG.  11 . 
     In FIG. 11, the input signal Din, the output signal S 4  of the write buffer  4  and the equalization signal S 5  are the same as those of the prior art shown in FIG.  5 . 
     The comparator  21  converts the equalization signal S 5  into a 3-value signal and provides an output signal S 7  to the error-propagation restriction circuit  25   a.  It is to be noted that while the output signal S 7  of the comparator  21  is output as a 2-bit digital signal, it is shown as having three values of “1”, “0” and “−1” in FIG. 11 for the sake of convenience. 
     The error-propagation restriction circuit  25   a  performs the process of 1/(1+D) on the output signal S 7  of the comparator  21 , thereby generating an output signal Dout identical to the input signal Din. At this time, if noise n 1  appears in the equalization signal S 5  so that the comparator  21  consecutively outputs three bits of the output signal S 7  of “1” containing error data e, the error-propagation restriction circuit  25   a  outputs error data eDout for three bits, but outputs a correct decoded signal Dout for the subsequent bits. 
     The magnetic recording/reproducing apparatus  200  according to the first embodiment has the following advantages. 
     (1) As the error-propagation restriction circuit  25   a  equivalent to a precoder and having the characteristic of 1/(1+D) is located at the succeeding stage of the comparator  21 , the propagation of an error is suppressed. 
     (2) Even if the comparator  21  outputs error data e originated from noise produced in the recording/reproducing system  5  and the equalizer  9 , the error-propagation restriction circuit  25   a  restricts the output of the error data signal eDout within a predetermined number of bits. 
     (3) The error-propagation restriction circuit  25   a  can be easily constructed using a relatively small number of gate circuits. 
     (4) The recording/reproducing operation is carried out using the PR system without providing a precoder at the preceding stage of the recording/reproducing system  5 . This makes it possible to accomplish recording/reproduction with an excellent S/N ratio using the PR system while maintaining the compatibility of the recording medium  7 . 
     (5) As the number of bits of the error data signal eDout to be output is limited, the error data signal eDout is easily corrected by an error correcting circuit which is connected to the succeeding stage of the error-propagation restriction circuit  25   a.    
     Second Embodiment 
     FIG. 12 is a schematic block diagram of a magnetic recording/reproducing apparatus  210  according to the second embodiment of the present invention. The magnetic recording/reproducing apparatus  210  has an error-propagation restriction circuit  25   b.  The error-propagation restriction circuit  25   b  includes an error detector  32 , a precoder equivalent circuit  33  and an inversion circuit  34 . FIG. 13 is a schematic block diagram of the error-propagation restriction circuit  25   b.    
     The output signal X 1  of the comparator  21  is supplied via an inverter circuit  35   a  to first input terminals of an AND gate  37   a  and NAND gate  36 . The output signal X 0  of the comparator  21  is supplied to a second input terminal of the NAND gate  36  and a first input terminal of an XOR gate  42   a  of the precoder equivalent circuit  33 . 
     The output signal of the AND gate  37   a  is supplied to a first input terminal of an OR gate  38   a  which supplies an error detection signal err as a clock signal C to a clock input terminal of a D type flip-flop circuit (hereinafter referred to as “D-FF”)  41 . 
     The D-FF  41  provides a first input terminal of an XOR gate  42   b  of the inversion circuit  34  with an output signal Herr which is inverted every time the error detection signal err rises. 
     The output signal of the NAND gate  36  is supplied to a first input terminal of an AND gate  37   b  and a first input terminal of a NOR gate  39   a.  The output signal of the AND gate  37   b  is supplied to a second input terminal of the OR gate  38   a.    
     The output signal of the NOR gate  39   a  is supplied to a first input terminal of an OR gate  38   b.  The output signal y 0  of the OR gate  38   b  is supplied to a delay operation element  40   b  whose output signal Dy 0  is supplied to a second input terminal of the XOR gate  42   a,  a first input terminal of a NOR gate  39   c  and a first input terminal of an AND gate  37   c.    
     The input signal X 1  is input to a first input terminal of an AND gate  37   d  whose output signal yl is supplied to a second input terminal of the OR gate  38   b  and a delay operation element  40   a.    
     The output signal Dy 1  of the delay operation element  40   a  is supplied to a second input terminal of the AND gate  37   a,  a second input terminal of the NOR gate  39   b,  a second input terminal of the NOR gate  39   c  and second input terminals of the AND gates  37   c  and  37   d  the last two via an inverter circuit  35   b.  The output signal of the NOR gate  39   c  is input to the second input terminal of the NOR gate  39   b  whose output signal is input to a second input terminal of the NOR gate  39   a.    
     The output signal of the AND gate  37   c  is supplied to a second input terminal of the AND gate  37   b.  The output signal of the XOR gate  42   a  is supplied to a second input terminal of the XOR gate  42   b.    
     The logical expression of the error detector  32  is given by the following equation 2. 
      err={overscore (X 1 )}* Dy   1 + {double overscore (X 1 )}{overscore (*   X   0 )}* {overscore (Dy 1 )}*   Dy   0   
     
       
           y   0 = {overscore (X 1 )}*   X   0 *( {overscore (Dy 1 )}*   {overscore (Dy 0 )}+   Dy   1 )+ X   1 * {overscore (Dy 1 )}   
       
     
     
       
           y   1 = X   1 * {overscore (Dy 1 )}   (2) 
       
     
     The error detector  32 , like the error-propagation restriction circuit  25   a,  operates in accordance with the truth table shown in FIG.  10 . Specifically, when the comparator  21  consecutively outputs three bits or more of “1” or “−1”, the error detector  32  automatically detects an error at the position of the inversion of magnetization and activates the inversion signal Herr. 
     The logical expression of the precoder equivalent circuit  33  is given by the following equation 3. 
     
       
           py=X   0 ⊕ Dy   0   (3) 
       
     
     (wherein ⊕ indicates a logical symbol of XOR) 
     The precoder equivalent circuit  33  produces an output signal py by performing an XOR operation on the input signal X 0  and the output signal Dy 0  of the delay operation element  40   b.    
     The logical expression of the inversion circuit  34  is given by the following equation 4. 
     
       
           y=Herr⊕py   (4) 
       
     
     (wherein ⊕ indicates a logical symbol of XOR) 
     The inversion circuit  34  produces a decoded signal Dout by performing an XOR operation on the inversion signal Herr supplied from the D-FF  41  and the output signal py supplied from the precoder equivalent circuit  33 . The inversion circuit  34  outputs the output signal py of the precoder equivalent circuit  33  as the decoded signal Dout when the output signal Herr of the error detector  32  is low, and outputs an inverted signal of the output signal py of the precoder equivalent circuit  33  as the decoded signal Dout when the output signal Herr is high. 
     The operation of the magnetic recording/reproducing apparatus  210  will now be discussed with reference to FIG.  14 . 
     The write buffer  4  receives the input signal Din and outputs the output signal S 4 . The equalizer  9  receives the output signal S 5  from the recording/reproducing system  5  and provides the equalization signal S 5  to the comparator  21 . The comparator  21  supplies the output signal S 7  to the error-propagation restriction circuit  25   b.    
     The error detector  32  outputs a low detection signal Herr when the output signal S 7  of “1” or “−1” is not output three or more bits in a row from the comparator  21 . The precoder equivalent circuit  33  performs the process of 1/(1+D) on the output signal S 7  of the comparator  21  and provides its output signal py to the inversion circuit  34 . The inversion circuit  34  outputs the output signal py as the decoded signal Dout in response to the low output signal Herr of the error detector  32 . 
     If noise n 1  appears in the output signal S 5  of the equalizer  9  so that the comparator  21  consecutively outputs three bits of the output signal S 7  of “1” containing error data e, the error detector  32  outputs a high detection signal Herr. 
     Although the precoder equivalent circuit  33  outputs the output signal py containing the error data e, the inversion circuit  34  inverts the output signal py of the precoder equivalent circuit  33  in response to the high detection signal Herr and produces the decoded signal Dout. 
     Although the error-propagation restriction circuit  25   b  outputs 3-bit error data eDout containing the error data e from the comparator  21 , it outputs a correct decoded signal Dout thereafter. 
     Third Embodiment 
     FIG. 15 is a schematic block diagram of a digital signal transmission apparatus  220  according to a third embodiment of the present invention. The third embodiment uses the error-propagation restriction circuit  25   a  of the first embodiment in a transmission line  43  having a capacitive coupling characteristic. The write buffer  4 , the equalizer  9  and the comparator  21  are the same as those of the first embodiment. 
     The input signal Din is provided to the write buffer  4  having the 1/(1−D) characteristic. The write buffer  4  converts the input signal Din into an NRZI code which is in turn provided to the transmission line  43 . 
     The transmission line  43  has a differential characteristic expressed by (1−D). The output signal from the transmission line  43  is supplied to the equalizer  9  having the (1+D) characteristic. The comparator  21  converts the equalization signal from the equalizer  9  into a 3-value signal and provides its output signal to the error-propagation restriction circuit  25   a.  The error-propagation restriction circuit  25   a  carries out the same error detection and correction as done in the first embodiment, thereby producing a decoded signal Dout. 
     The third embodiment can transmit and decode signals via the transmission line  43  having the capacitive coupling characteristic using the PR system. 
     Fourth Embodiment 
     FIG. 16 is a schematic block diagram of a digital signal transmission apparatus  230  according to a fourth embodiment of the present invention. The fourth embodiment uses the error-propagation restriction circuit  25   b  of the second embodiment in the transmission line  43 . The write buffer  4 , the equalizer  9  and the comparator  21  are the same as those of the second embodiment. 
     The error-propagation restriction circuit  25   b  carries out the same error detection and correction as done in the second embodiment, thereby producing a decoded signal Dout. The fourth embodiment can transmit and decode signals via the transmission line  43  having the capacitive coupling characteristic using the PR system. 
     Fifth Embodiment 
     FIG. 17 is a schematic block diagram of a digital signal transmission apparatus  240  according to a fifth embodiment of the present invention. The fifth embodiment uses the error-propagation restriction circuit  25   a  of the first embodiment in a transmission line  44  having a transformer coupling characteristic. The write buffer  4 , the equalizer  9  and the comparator  21  are the same as those of the first embodiment. 
     The input signal Din is input to the write buffer  4  having the 1/(1−D) characteristic. The write buffer  4  converts the input signal Din into an NRZI code which is in turn provided to the transmission line  44 . 
     The transmission line  44  has a differential characteristic expressed by (1−D). The output signal from the transmission line  44  is supplied to the equalizer  9  having the (1+D) characteristic. The comparator  21  converts the equalization signal from the equalizer  9  into a 3-value signal and provides its output signal to the error-propagation restriction circuit  25   a.  The error-propagation restriction circuit  25   a  carries out the same error detection and correction as done in the first embodiment, thereby producing a decoded signal Dout. 
     The fifth embodiment can transmit and decode signals via the transmission line  44  having the transformer coupling characteristic using the PR system. 
     Sixth Embodiment 
     FIG. 18 is a schematic block diagram of a digital signal transmission apparatus  250  according to a sixth embodiment of the present invention. The sixth embodiment uses the error-propagation restriction circuit  25   b  of the second embodiment in the transmission line  44 . The write buffer  4 , the equalizer  9  and the comparator  21  are the same as those of the second embodiment. 
     The error-propagation restriction circuit  25   b  carries out the same error detection and correction as done in the second embodiment, thereby producing a decoded signal Dout. The sixth embodiment can transmit and decode signals via the transmission line  44  having the transformer coupling characteristic using the PR system. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.