Abstract:
A serial-connection and parallel-communication fast interface for a PLC host and an expansion device includes a PLC host, at least one expansion device and shared bus comprising address lines, data lines, control lines and I/O addressing lines. The PLC host comprises an initial address output circuit and outputting a clamping value to the expander through an output addressing line. The expansion device includes a microprocessor, a memory unit and a clamping and decoding circuit such that the expansion device can automatically allocate the order thereof and output the clamping value through the addressing line. The expansion device can automatically allow or block the data from the PLC host. Therefore, the problem of overlong communication time for data access, the augmentation of expansion device and order limitation can be saved.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to serial-connection and parallel-communication fast interface for PLC host and expansion device, especially relates to serial-connection and parallel-communication fast interface for PLC host and expansion device, wherein the expansion device can be optionally and flexibly added with unlimited order and the accessing time can be reduced.  
         [0003]     2. Description of Prior Art  
         [0004]     The programmable logic-controller (PLC) is generally connected to external equipments or devices through the external I/O terminals thereof and controls the external equipments or devices by editing a program thereof. However, the prior art PLC has external I/O terminals with predetermined pin counts and expansion device is need to expand analog or digital pin counts when the prior art PLC is to be connected to more external equipments or devices.  
         [0005]     The prior art PLC is generally connected to expansion device through serial-connection-serial-communication or parallel-connection-parallel-communication. For PLC in serial-connection-serial-communication with the expansion device, the PLC is serially connected to a plurality of expansion devices. When the PLC sends a data-accessing signal for a designated expansion device, each of the expansion devices will receive and process the data accessing signal to examine whether it is the designated expansion device. However, the communication time for the PLC to access the expansion device will be excessively long.  
         [0006]      FIGS. 1 and 2  show the schematic diagram for the prior art PLC in parallel-connection-parallel-communication with expansion device. The PLC is connected through a fixed base  1  and a plurality of connectors  11  with decoding function. The connectors  11  are connected to the bus  15  of the fixed base  1  and comprise address lines, data lines and control lines, whereby the PLC host  12  is connected to a plurality of expansion devices  13  and  14  in parallel fashion. The connector  11  provides decoding function to reduce the communication time for the PLC to access the expansion device. However, the connector  11  has decoding function with fixed order and it places limitation on arrangement order of the expansion devices  13  and  14 . The order of the expansion devices  13  and  14  cannot be changed. The fixed base  1  and a plurality of connectors  11  are needed even when the PLC host  12  is connected to one or just a few of expansion devices  13 .  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention is to provide a serial-connection and parallel-communication interface for a PLC host and at least one expansion device. The serial-connection and parallel-communication interface comprises address lines, data lines, control lines and I/O addressing lines of a shared bus connected between the PLC host and the expansion device. The expansion device uses a built-in decoder to automatically allow or prohibit the PLC host for accessing data. The expansion device can be optionally added and the accessing speed can be enhanced.  
         [0008]     Accordingly the serial-connection and parallel-communication interface for a PLC host comprises:  
         [0009]     a PLC host;  
         [0010]     a shared bus comprising address lines, data lines, control lines and I/O addressing lines and built in the PLC host;  
         [0011]     a first microprocessor connected to the address lines, data lines, and control lines of the shared bus; and  
         [0012]     an initial address output circuit connected to the I/O addressing lines for outputting a clamping value to the expansion device;  
         [0013]     a connector unit for connected to the serially connected expansion device;  
         [0014]     an IRQ signal input for receiving the interrupt signal from the expansion device;  
         [0015]     at least one expansion device comprising:  
         [0016]     a microprocessor;  
         [0017]     a memory unit comprising dual-port connector and connected to the address lines, data lines, and control lines of the first microprocessor, and the address lines, data lines, and control lines of the shared bus;  
         [0018]     an input enable level signal connected to the output enable level signal of the PLC host or the expansion device of previous stage;  
         [0019]     an output enable level signal as an input enable level signal of the expansion device of next stage;  
         [0020]     an IRQ signal for sending interrupt signal to the PLC host; and  
         [0021]     a clamping and decoding circuit connected to the output addressing lines to get the clamping value of the expansion device of previous stage and converting the clamping value for sending to the expansion device of next stage through output addressing lines, the clamping and decoding circuit deciding whether the PLC host is connected to the memory unit and the data lines are activated for data accessing according to the clamping value from the input addressing lines.  
         [0022]     The expansion device comprises a first connector and a second connector for connecting to the PLC host and the adjacent expansion device.  
         [0023]     The PLC host and the expansion device are connected in a serial-connection and parallel-communication manner, which is established by address lines, data lines, control lines and I/O addressing lines of a shared bus connected between the PLC host and the expansion device. The expansion device automatically assign the order thereof and automatically allows or prohibits data accessing of the PLC host according to clamping values sent through the I/O addressing lines. 
     
    
     BRIEF DESCRIPTION OF DRAWING  
       [0024]     The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:  
         [0025]      FIG. 1  shows the schematic diagram for the prior art PLC in parallel-connection and parallel-communication with expansion device.  
         [0026]      FIG. 2  shows the circuit diagram for the prior art PLC in parallel-connection and parallel-communication with expansion device.  
         [0027]      FIG. 3  shows a block diagram of the present invention.  
         [0028]      FIG. 4  shows a circuit diagram of the present invention.  
         [0029]      FIG. 5  shows a detailed circuit diagram of the PLC host of the present invention.  
         [0030]      FIG. 6  shows a detailed circuit diagram of the expansion device of the present invention.  
         [0031]      FIG. 7  shows a detailed circuit diagram of the clamping circuit of the present invention.  
         [0032]      FIG. 8  shows a detailed circuit diagram of the decoding circuit of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0033]     With reference to FIGS.  3  to  8 , the present invention provides a fast communication interface for serial-connection-parallel-communication PLC host and expansion devices. The fast communication interface for PLC host and expansion devices comprises a PLC host  2  and at least one expansion device  3  connected with the PLC host  2 . A connector unit  21  outside the PLC host  2  is connected to the expansion device  3 . A first connector  31  and a second connector  32  are provided outside each expansion device  3 . The first connector  31  of an expansion device  3  is connected to the connector unit  21  of the PLC host  2 , or connected to the second connector  32  of a next expansion device  3 . The second connector  32  of an expansion device  3  is connected to the first connector  31  of a next expansion device  3 . Therefore, serial-connection and parallel-communication connection can be established between the PLC host  2  and at least one expansion device  3  with address lines, data lines, control lines I/O addressing lines therebetween.  
         [0034]     The connector unit  21  of the PLC host  2  is one of a female connector unit or a male connector unit. The first connector  31  of the expansion device  3  is one of a male connector or a female connector, which is connectable to the connector unit  21  of the PLC host  2 . The second connector  32  of the expansion device  3  is one of a female connector or a male connector, which is connectable to the first connector  31  of the next expansion device  3 .  
         [0035]     The internal circuit in the PLC host  2  comprises built-in standard shared bus with address lines, data lines, control lines and output addressing lines Q 0 -Q 4 , a microprocessor  22  and an initial address output circuit  23 . The microprocessor  22  is connected to the address lines, data lines, and control lines in the standard shared bus for sending data and control signals. The microprocessor  22  comprises an output enable level signal pin En_out for sending a high-level signal for enabling and an IRQ signal pin. The initial address output circuit  23  has constant output of 0 or other value and sends its output through the output addressing lines Q 0 -Q 4  to the expansion devices  3  for decoding and addressing.  
         [0036]     The expansion device  3  comprises built-in standard shared bus with address lines, data lines, control lines and I/O addressing lines between the first connector  31  and the second connector  32 , a microprocessor  33 , a memory unit  34  connected to the address lines, data lines, control lines of the microprocessor  33 , the address lines, data lines, control lines of the standard shared bus for the first connector  31  and the second connector  32  for processing data accessing of the PLC host  2 , and a clamping and decoding circuit  35  for acquiring input clamping value of the PLC host  2  or previous expansion device  3  through the input addressing lines I 0 -I 4 . The clamping and decoding circuit  35  further receives signals from the address lines A 15 -A 11 , the /CS signal of the control lines of the shared bus and the input enable level signal En_in from the expansion device  3  for activating the data accessing communication with the data bus and converting the clamping value for sending to next expansion device  3  through the output addressing lines Q 0 -Q 4 .  
         [0037]     The expansion device  3  further comprises an IRQ line linked with the IRQ line of other expansion devices  3  and the IRQ line of the PLC host  2  to inform the PLC host  2  and other expansion devices  3  once an interrupt occurs.  
         [0038]     The clamping and decoding circuit  35  comprises a clamping circuit  36  and a decoding circuit  37 . When the output enable level signal En_out from the PLC host  2  or the expansion devices  3  of previous stage is low level, the clamping and decoding circuit  35  does not work. When the output enable level signal En_out from the PLC host  2  or the expansion devices  3  of previous stage is high level, the clamping and decoding circuit  35  automatically allows or prohibits the PLC host  2  to access the memory unit  34  of the expansion device  3 .  
         [0039]     As shown in  FIG. 7 , the clamping circuit  36  comprises a sum circuit  361 , a first logic circuit (NAND gate)  362  and a second logic circuit (AND gate)  363 . The sum circuit  361  receives an output clamping values from the PLC host  2  or an input clamping value converted from the expansion device  3  of previous stage through input addressing lines I 0 -I 4 , the input enable level signal En_in from the PLC host  2 . The input clamping value is incremented by one and converted into an output clamping value for outputting to the expansion device  3  of next stage through the output addressing lines Q 0 -Q 4 . The input addressing signals I 0 -I 4  are processed by the first logic circuit  362  into the input signal for the second logic circuit  363 . The input enable level signal En_in from the PLC host  2  is processed by the second logic circuit  363  into output enable level signal En_out, which is input enable level signal En_in for the expansion device  3  of next stage. When the address lines I 0 -I 4  of the expansion device  3  receives the clamping value of 31 (namely I 0 ˜I 4 =11111) from the output addressing lines Q 0 -Q 4  of the expansion device  3  of previous stage and the input enable level signal En_in is high level, the output enable level signal En_out with low level is output to the expansion device  3  of next stage.  
         [0040]     As shown in  FIG. 8 , the decoding circuit  37  comprises a comparator  371 , a third logic circuit (NOR gate)  372  and a fourth logic circuit (OR gate)  373 . The comparator  371  receives the output clamping value from the PLC host  2  through the input addressing lines I 0 -I 4  or the output clamping value from the expansion device  3  of previous stage in order to compare with the address signals A 15 -A 11  from the address lines of the shared bus. A low level signal is output when the comparison is matched, and a high level signal is output when the comparison is not matched. The low level or the high level signal is used as input signal for the fourth logic circuit (NOR gate)  373 . The other input signal for the fourth logic circuit (NOR gate)  373  is the output of the third logic circuit (NOR gate)  372 , which receives a control signal /CS and an inverted input enable level signal En_in. The fourth logic circuit (NOR gate)  373  outputs a level signal /CS_decoder to determine whether the memory unit  34  is connected to activate the data accessing communication for the data line.  
         [0041]     In the present invention, the PLC host  2  and the plurality of expansion devices  3  are connected in a serial-connection and parallel-communication manner, which is established by address lines, data lines, control lines I/O addressing lines therebetween. When the output enable level signal En_out output by the PLC host  2  is high level, the plurality of expansion devices  3  use the clamping and decoding circuit  35  thereof and the input addressing to automatically assign the order for each of the expansion devices  3 . When PLC host  2  intends to perform data accessing communication to one memory unit  34  of one expansion device  3 , the microprocessor  22  of the PLC host  2  sends a high-level output enable level signal En_out to all expansion devices  3  to activate the clamping and decoding circuits  35 . Therefore, the PLC host  2  can access one memory unit  34  of one expansion device  3 .  
         [0042]     In the present invention, the PLC host  2  and the plurality of expansion devices  3  are connected in a serial-connection and parallel-communication manner, which is established by address lines, data lines, control lines I/O addressing lines therebetween. Therefore, the expansion devices  3  can be optionally added in user&#39;s disposal and the order of the expansion devices  3  has no limited. The accessible expansion devices  3  depend on the amount of the I/O addressing lines. Therefore, the amount of the expansion devices  3  can be adjusted by changing the amount of the I/O addressing lines. In above-mentioned preferred embodiments, the amount of the I/O addressing lines is 5, therefore, the maximal number of the accessible expansion devices is 2 5 =32.  
         [0043]     The clamping and decoding circuits  35  built in the expansion device  3  can automatically assign the order of the expansion devices  3  when the expansion devices  3  are connected together. The clamping and decoding circuit  35  built in the expansion device  3  automatically allows or prohibits the sent or read data of the PLC host  2  according to the clamping values sent from the PLC host or the expansion device  3  of previous stage through the input addressing line I 0 -I 4 . In the present invention, the above function is realized by hardware and the microprocessor of the expansion device  3  does not need modification. The accessing time of the PLC host to the expansion device according to the present invention can be reduced in comparison with the prior art PLC host, which relies on the microprocessor of the expansion device  3 .  
         [0044]     Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.