Abstract:
A regulator for providing a plurality of output voltages is provided. The regulator includes a basic unit and a plurality of replica units. The basic unit amplifies an input voltage to obtain a core voltage according to a first control signal. Each of the replica units outputs one of the output voltages according to the input voltage and one of a plurality of second control signals, wherein at least two of the output voltages have different voltage levels. The first control signal is set according to the second control signals, to make the voltage level of the core voltage substantially equal to or less than a maximum voltage level of the output voltages and substantially equal to or greater than a minimum voltage level of the output voltages.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority of U.S. Provisional Application No. 61/443,567, filed on Feb. 16, 2011, the entirety of which is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention is related to a regulator for providing multiple output voltages, and more particularly to a regulator for providing various output voltages. 
         [0004]    2. Description of the Related Art 
         [0005]    Voltage regulators are used in a variety of systems to provide regulated voltages to circuits in the system. Generally, it is desirable to provide stable regulated voltages under a wide variety of loads, and operating frequencies, etc. In other words, a voltage regulator is designed to provide and maintain a constant voltage in electrical devices, such as a low dropout (LDO) voltage regulator, which is a DC linear voltage regulator which has a very small input-output differential voltage and relatively low output noise. 
         [0006]    A measure of the effectiveness of a voltage regulator is its power supply rejection ratio (PSRR), which measures the amount of noise present on the power supply to the voltage regulator which is transmitted to an output voltage of the voltage regulator. A high PSRR is indicative of a low amount of noise transmission, and a low PSRR is indicative of a high amount of noise transmission. A high PSRR, particularly across a wide range of operating frequencies of devices being supplied by a voltage regulator, is difficult to achieve. 
         [0007]    For example, assume that a crystal oscillator (XO) and a digitally controlled oscillator (DCO) of an all digital phase locked loop (ADPLL) are supplied by one LDO regulator. If the clock signal generated by the XO kicks back to its supply voltage, the clock signal may kick back again to the LDO regulator&#39;s supply voltage. If a high frequency PSRR is not high enough at the frequency offset or frequency range, the kick back noise may affect the supply voltage of the DCO. To prevent the de-sensing or interference problem, high PSRR performance is very important. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    Regulators for providing a plurality of output voltages are provided. An embodiment of a regulator for providing a plurality of output voltages is provided. The regulator comprises a basic unit and a plurality of replica units. The basic unit amplifies an input voltage to obtain a core voltage according to a first control signal. Each of the replica units outputs one of the output voltages according to the input voltage and one of a plurality of second control signals, wherein at least two of the output voltages have different voltage levels. The first control signal is set according to the second control signals, to make the voltage level of the core voltage substantially equal to or less than a maximum voltage level of the output voltages and substantially equal to or greater than a minimum voltage level of the output voltages. 
         [0009]    Furthermore, another embodiment of a regulator for providing a plurality of output voltages is provided. The regulator comprises a core circuit and a plurality of replica units. The core circuit provides a bias voltage according to a first control signal and an input signal, and the core circuit comprises a basic unit. Each of the replica units outputs one of the output voltages, wherein at least two of the output voltages have different voltage levels. Each of the basic unit and the replica units comprises: a first transistor, having a gate for receiving the bias voltage, so that a reference current can flow through the first transistor; and a first resistor connected in cascade to the first transistor, having a resistance. A voltage level of the output voltage is determined according to the reference current and the resistance of the first resistor in each of the replica units. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  shows a regulator according to an embodiment of the invention, wherein the regulator is a multi-output-level source follower typed replica capless LDO voltage regulator; 
           [0013]      FIG. 2A  shows an example illustrating an operation of the control unit of  FIG. 1 ; 
           [0014]      FIG. 2B  shows a table illustrating a relationship between the control signals and the voltage levels in  FIG. 2A ; 
           [0015]      FIG. 3A  shows another example illustrating an operation of the control unit of  FIG. 1 ; 
           [0016]      FIG. 3B  shows a table illustrating a relationship between the control signals and the voltage levels in  FIG. 3A ; 
           [0017]      FIG. 4  shows a regulator according to another embodiment of the invention, wherein the regulator is a multi-output-level source follower typed replica capless LDO voltage regulator; 
           [0018]      FIG. 5  shows a regulator according to another embodiment of the invention, wherein the regulator is a multi-output-level PMOS typed replica capless LDO voltage regulator; and 
           [0019]      FIG. 6  shows a regulator according to another embodiment of the invention, wherein the regulator is a multi-output-level NMOS typed replica capless LDO voltage regulator. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0021]      FIG. 1  shows a regulator  100  according to an embodiment of the invention. The regulator  100  is a multi-output-level source follower typed replica capless low dropout (LDO) voltage regulator, which provides the LDO voltages V out     —     1  to V out     —     N  in the output nodes N out     —     1  to N out     —     N , respectively. The regulator  100  comprises a core circuit  10 , and N replica units  20   —   1  to  20 _N. The core circuit  10  comprises an amplifier  15 , two resistors R 1  an R 2  and a basic unit  30 , wherein the resistor R 2  is a variable resistor. The amplifier  15  has a non-inverting input terminal (+) receiving an input voltage V ref , an inverting input terminal (−) coupled to the resistors R 1  and R 2 , and an output terminal for simultaneously outputting a bias voltage V bias  to the basic unit  30  and the replica units  20 _ 1  to  20 _N. The resistor R 1  is coupled between a ground GND and the inverting input terminal of the amplifier  15 , and the resistor R 2  is coupled between the inverting input terminal of the amplifier  15  and a variable resistor R 3  of the basic unit  30 . In the core circuit  10 , the resistances of the resistors R 2  and R 3  are controlled by a control signal S ari  simultaneously. The basic unit  30  comprises a current source I 1 , two transistors M 1  and M 2 , the resistor R 3  and a current circuit  35 . In the embodiment, the current circuit  35  is a current mirror, and since the current mirror is known in the art, it will not be described in detail herein. The current source I 1  is coupled between a supply voltage VDD and a gate of the transistor M 1 , which provides a fixed bias current I bias1  to the current mirror  35 . The transistor M 1  is coupled between the supply voltage VDD and the resistor R 3 , and the transistor M 2  is coupled between the resistor R 3  and the current mirror  35 . The current mirror  35  is coupled to the current source I 1 , the transistor M 2  and ground GND, which drains a mirror current I mirror1  from the transistor M 2  according to the bias current I bias1 . In  FIG. 1 , the bias voltage V bias  can be given as the following equation: 
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         [0000]    In one embodiment, the control signal S ctrl  controls the resistors R 2  and R 3  to have the same resistances, thus a voltage across the resistor R 2  is equal to a voltage across the resistor R 3  when the currents flow through the resistors R 2  and R 3  are the same, i.e. I b =I mirror1 . If the currents flow through the resistors R 2  and R 3  are different, the control signal S ari  controls the resistance variations of the resistors R 2  and R 3  (e.g. ΔR 2  and ΔR 3 ) to conform to a specific proportion, so as to keep the bias voltage V bias  as a constant voltage. It is to be noted that the transistors M 1  and M 2  are different type of MOS transistors. In the embodiment, the transistor M 1  is an NMOS transistor and the transistor M 2  is a PMOS transistor. In the embodiment, the transistor M 1  is a native device. In other embodiments, the transistor M 1  is an N-type transistor of I/O or core circuit. 
         [0022]    In the core circuit  10 , the basic unit  30  further comprises a switch SW 1  coupled between the supply voltage VDD and the transistor M 1  and a switch SW 2  coupled between the ground GND and the output terminal of the amplifier  15 , wherein the switches SW 1  and SW 2  are controlled, together, by a signal ENA. In the embodiment, the switch SW 1  is a PMOS transistor and the switch SW 2  is an NMOS transistor. Therefore, the switches SW 1  and SW 2  are not turned on at the same time. When the regulator  100  is powered down, the signal ENA controls the switch SW 1  to turn off and the switch SW 2  to turn on, thus, no current I mirror1  is generated. On the contrary, the switch SW 1  is turned on and the switch SW 2  is turned off when the regulator  100  is powered on. In the regulator  100 , the switch SW 1  further provides electrostatic discharge (ESD) protection, and the switch SW 2  and a capacitor C 0  further provide a start-up function to prevent overshoot. Specifically, the switch SW 2  is used to initialize the bias voltage V bias  rising up from zero voltage when the regulator  100  starts up, to avoid overshoot in the LDO voltages V out     —     1  to V out     —     N . 
         [0023]    In  FIG. 1 , the replica unit  20 _ 1  comprises a current source I 2 _ 1 , a switch SW 3 _ 1 , two transistors M 3 _ 1  and M 4 _ 1 , a resistor R 4 _ 1  and a current circuit  25 _ 1 , wherein the current circuit  25 _ 1  is a current mirror. The current source I 2 _ 1  is coupled between the supply voltage VDD and a gate of the transistor M 3 _ 1 , which provides a bias current I bias2     —     1  to the current mirror  25 _ 1 , wherein the bias current I bias2     —     1  matches the bias current I bias1  of the basic unit  30 . The switch SW 3 _ 1  is coupled between the supply voltage VDD and the transistor M 3 _ 1 , and the switch SW 3 _ 1  is controlled by a signal ENA_ 1 . The transistor M 3 _ 1  is coupled between the switch SW 3 _ 1  and an output node N out     —     1 , and the resistor R 4 _ 1  is coupled between the output node N out     —     1  and the transistor M 4 _ 1 , wherein the output node N out     —     1  is used to output an output voltage V out     —     1 . The resistor R 4 _ 1  is a variable resistor controlled by a control signal S gain     —     1 . The transistor M 4 _ 1  is coupled between the resistor R 4 _ 1  and the current mirror  25 _ 1 . The current mirror  25 _ 1  is coupled to the current source I 2 _ 1 , the transistor M 4 _ 1  and ground GND, which drains a mirror current I mirror21  from the transistor M 4 _ 1  according to the bias current I bias2     —     1 . Similarly, the transistors M 3 _ 1  and M 4 _ 1  are different type of MOS transistors, wherein the size of the transistor M 41  matches that of the transistor M 2  of the basic unit  30 . In the embodiment, the transistor M 31  is an NMOS transistor and the transistor M 41  is a PMOS transistor. In the embodiment, the transistor M 31  is a native device. In other embodiments, the transistor M 3 _ 1  is an N-type transistor of I/O or core circuit. Substantially, the replica units  20 _ 1  to  20 _N have the same architecture, except that the switches SW 3 _ 1  to SW 3 _N are respectively controlled by the ENA_ 1  to ENA_N and resistances of the resistors R 4 _ 1  to R 4 _N are respectively controlled by the control signals S gain     —     1  to S gain     —     N . In the regulator  100 , the signal ENA is obtained according to the signals ENA_ 1  to ENA_N, so that the switch SW 1  is turned on when any one of the switches SW 3 _ 1  to SW 3 _N is turned on. Furthermore, the regulator  100  further comprises a low pass filter (LPF)  50  between the gate of the transistor M 2  and the gates of the transistors M 4 _ 1  to M 4 _N, wherein the LPF  50  is used to filter out noise from the bias voltage V bias . In the embodiment, the LPF  300  comprises a resistor R 5  coupled between the gate of the transistor M 2  and the gates of the transistors M 4 , and a capacitor C 1  between the resistor R 5  and the ground GND. It is to be noted that, in the embodiment, the gate voltages of the transistor M 2  and the transistors M 4 _ 1  to M 4 _N and the bias voltage V bias  are assumed to be equal. In the embodiment, the LPF  300  is an example and does not limit the invention. Furthermore, compared with conventional replica LDO regulators, only global matching is needed to be considered for the transistor M 2  and the transistors M 4 _ 1  to M 4 _N and the current source I 1  and the current sources I 2 _ 1  to I 2 _N in the regulator  100  for design and layout. For the current mirrors  25 _ 1  to  25 _N, only local matching needs to be considered, thererby decreasing design and layout complexity. 
         [0024]    In the core circuit  10 , the amplifier  15  and the basic unit  30  form a feedback loop. Firstly, assuming the current I mirror1  initially flowing through the current mirror  35  is zero, then, the gate of the transistor M 1  is pulled to high due to the fact that the bias current I bias1  is applied. Thus, the current I mirror1  flows from the supply voltage VDD to the ground GND through the transistor M 1 , the resistor R 3 , the transistor M 2  and the current mirror  35 , and then the gate of the transistor M 1  is pulled back due to a closed loop being formed. The closed loop stabilizes when the current I mirror1  is equal to the bias current I bias1 , thus the bias voltage V bias  is stably provided to the gates of the transistors M 2  and M 4 . 
         [0025]    In the regulator  100 , when the basic unit  30  and the replica units  20 _ 1  to  20 _N are at stable states, the gate-source voltages of the transistor M 2  and the transistors M 4 _ 1  to M 4 _N are the same due to the fact that the sizes and currents (i.e. the current I mirror1  and the currents I mirror2 1  to I mirror2 N ) of the transistor M 2  and the transistors M 4 _ 1  to M 4 _N are the same and the gates of the transistor M 2  and the transistors M 4 _ 1  to M 4 _N are controlled by the same bias voltage V bias . In one embodiment, by proportionating the sizes of the transistors M 2  and M 4 _ 1  to M 4 _N and the currents of the transistors M 2  and M 4 _ 1  to M 4 _N (i.e. the current sources I 1  and I 2 _ 1  to I 2 _N), the gate-source voltages of the transistor M 2  and the transistors M 4 _ 1  to M 4 _N are the same. Thus, the LDO voltages V out     —     1  to V out     —     N  are determined according to the bias voltage V bias , the gate-source voltages of the transistors M 4 _ 1  to M 4 _N and the voltages across the resistors R 4 _ 1  to R 4 _N in the replica units  20 _ 1  to  20 _N, respectively. Take the replica unit  20 _ 1  as an example. The output voltage V out     —     1  is equal to the sum of the bias voltage V bias , the gate-source voltages of the transistor M 4 _ 1  and the voltage across the resistor R 4 _ 1  in the replica unit  20 _ 1 , as shown in the following equation: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    where I mirror =I mirror2     —     1 =I mirror1  and V gsM2 =V gsM4 . Specifically, the output voltages V out     —     1  to V out     —     N  are determined according to the various resistances of the resistors R 4 _ 1  to R 4 _N in the replica units  20 _ 1  to  20 _N due to the bias voltage V bias , the gate-source voltages of the transistors M 4 _ 1  to M 4 _N and the currents I mirror2     —     1  to I mirror2     —     N  being the same, wherein each resistance of the resistors R 4 _ 1  to R 4 _N in the replica units  20 _ 1  to  20 _N is controlled by an individual control signal (e.g. S gain     —     1 , . . . , or S gain     —     N ). Therefore, by using the control signals S gain     —     1  to S gain     —     N  to adjust the resistances of the resistors R 4 _ 1  to R 4 _N, the regulator  100  can provide the output voltages V out     —     1  to V out     —     N  with various voltage levels in the output nodes N out     —     1  to N out     —     N , respectively. For the replica units  20 _ 1  to  20 _N, the sizes of the switches SW 3 _ 1  to SW 3 _N can be the same or different, which depend on the capability for IR drop. Furthermore, the sizes of the power transistors M 3 _ 1  to M 3 _N can be the same or different, which depend on supplied currents for the replica units  20 _ 1  to  20 _N. Moreover, the sizes of the devices within the replica units  20 _ 1  to  20 _N should be equal or proportional to the sizes of the devices within the basic unit  30 , such that each of the currents I mirror2     —     1  to I mirror2     —     N  matches the current I mirror1 . 
         [0026]    In  FIG. 1 , the bias voltage V bias  is obtained according to a core voltage V core , the gate-source voltage of the transistor M 2  and the voltage across the resistor R 3  in the basic unit  30 , wherein the resistances of the resistors R 2  and R 3  are controlled by the control signal S ctrl  from a control unit  40  that provides the control signal S ctrl  according to the control signals S gain     —     1  to S gain     —     N  to optimize power supply rejection ratio (PSRR) performance for the output voltages V out     —     1  to V out     —     N . Referring to  FIG. 2A  and  FIG. 2B  together,  FIG. 2A  shows an example illustrating an operation of the control unit  40  of  FIG. 1 , and  FIG. 2B  shows a table illustrating a relationship between the control signals and the voltage levels of the core voltage V core  in  FIG. 2A . In  FIG. 2A  and  FIG. 2B , each of the control signals S gain     —     1  to S gain     —     N  is a logic signal, which uses 3 bits to represent an integer value that indicates a gain level corresponding to a ratio of the individual resistor R 4  to the resistor R 3 . The operations of the control unit  40  of  FIGS. 2A and 2B  are used as an example for description, and do not limit the invention. As shown in  FIG. 2A , the control signal S gain     —     1  [3:1] is “010”, the control signal S gain     —     2  [3:1] is “110”, the control signal S gain     —     3  [3:1] is “100”, the control signal S gain     —     (N-2)  [3:1] is “010”, the control signal S gain     —     (N-1)  [3:1] is “101” and the control signal S gain     —     N  [3:1] is “011”, wherein the voltage levels of the control signals S gain     —     1  to S gain     —     N  can be obtained by looking up the table of  FIG. 2B . For example, “010” represents that the replica unit  20 _ 1  can provide the output voltages V out     —     1  with the voltage level of 1.35V in the output node N out     —     1 . After receiving the control signals S gain     —     1  to S gain     —     N , the control unit  40  uses a maximum level detector  42  and a minimum level detector  44  to find out a control signal having a maximum integer value and a control signal having a minimum integer value, respectively, and then use a calculator  46  to average the maximum integer value and the minimum integer value, so as to obtain the control signal S ctrl  with the averaged integer value. As shown in  FIG. 2A , the maximum level detector  42  determines that the control signal S gain     —     2  has the maximum integer value “110”, and the minimum level detector  44  determines that the control signal S gain     —     1  or S gain     —     (N-2)  has the minimum integer value “010”. Next, the calculator  46  sums up the maximum integer value “110” and the minimum integer value “010” to obtain a sum value “1000”, wherein the sum value “1000” is an even binary value. Then, the calculator  46  divides the sum value “1000” by 2 (e.g. shift 1 bit to right) to obtain the control signal S ctrl  with the averaged value “100”. For example, two parts are separated from the sum value “1000”, wherein one part is the more significant three bits “100” and another part is the least significant bit (LSB) “0”. Next, the LSB “0” is extended to three bits “000” by adding “00”. Next, the values “100” and “000” are summed to obtain the averaged value “100”. Thus, the control unit  40  provides the control signal S ctrl  with the averaged value “100” to control the resistances of the resistors R 2  and R 3 , so as to obtain the core voltage V core  with the voltage level of 1.45V. Therefore, the voltage level of the core voltage V core  is equal to an average of the maximum and minimum output voltage levels. It is to be noted that the operation of the control unit  40  is an example and does not limit the invention, and the control unit can be implemented in hardware or software. 
         [0027]      FIG. 3A  shows another example illustrating an operation of the control unit  40  of  FIG. 1  that a sum of the maximum integer value and the minimum integer value can not be divisible by 2, and  FIG. 3B  shows a table illustrating a relationship between the control signals and the voltage levels in  FIG. 3A . In  FIG. 3A , according to the control signals S gain     —     1  to S gain     —     N , the maximum level detector  42  determines that the control signal S gain     —     2  has the maximum integer value “110”, and the minimum level detector  44  determines that the control signal S gain     —     (N-1)  has the minimum integer value “001”. Next, the calculator  46  sums up the maximum integer value “110” and the minimum integer value “001” to obtain a sum value “0111”, wherein the sum value “0111” is an odd binary value. Next, the calculator  46  divides the sum value “0111” by 2 and rounds the divided value to obtain an averaged integer value “100”. For example, two parts are separated from the sum value “0111”, wherein one part is the more significant three bits “011” and another part is the LSB “1”. Next, the LSB “1” is extended to three bits “001” by adding “00”. Next, the values “011” and “001” are summed to obtain the averaged value “100”. Thus, the control unit  40  provides the control signal S ctrl  with the averaged integer value “100” to control the resistances of the resistors R 2  and R 3 , so as to obtain the core voltage V core  with the voltage level of 1.45V. Therefore, the voltage level of the core voltage V core  is equal to a rounding value of an average of the maximum and minimum output voltage levels. 
         [0028]    As described above, the control unit  40  provides the control signal S ctrl  with a specific value to control the resistances of the resistors R 2  and R 3 , such that the core voltage V core  is equal to or close to an average of the output voltage with the maximum voltage level and the output voltage with the minimum voltage level. Thus, a PSRR at a low frequency can be enhanced through the PSRR cancellation mechanism in the regulator  100 . For example, noise from the supply voltage VDD can be divided into a plurality of paths P 1 , P 2 , P 3 , P 4  and P 5  in the regulator  100 . In each of the replica units  20 _ 1  to  20 _N, the path P 1  is from the supply voltage VDD to its output node through the corresponding switch SW 3  and the transistor M 3 , and the path P 2  is from the supply voltage VDD to its output node through the current source  12  and the transistor M 3 . Furthermore, the paths P 3  are from the supply voltage VDD to the output nodes of the replica units  20 _ 1  to  20 _N through the switch SW 1 , the transistor M 1 , the resistor R 2 , the amplifier  15 , LPF  50  and the transistors M 4 _ 1  to M 4 _N of the replica units  20 _ 1  to  20 _N. The path P 4  is from the supply voltage VDD to the output nodes of the replica units  20 _ 1  to  20 _N through the current source I 1 , the transistor M 1 , the resistor R 2 , the amplifier  15 , LPF  50  and the transistors M 4 _ 1  to M 4 _N of the replica units  20 _ 1  to  20 _N. The path P 5  is from the supply voltage VDD to the output nodes of the replica units  20 _ 1  to  20 _N through the amplifier  15 , LPF  50  and the transistors M 4 _ 1  to M 4 _N of the replica units  20 _ 1  to  20 _N. Due to the fact that the amplifier  15  is operated in a negative feedback loop, the noise through the paths P 4  and P 3  is reversed in the output nodes of the replica units  20 _ 1  to  20 _N. Thus, though the voltages in the output nodes of the replica units  20 _ 1  to  20 _N may be different, the noise through the paths P 1  and P 2  can be appropriately cancelled out in the output nodes of the replica units  20 _ 1  to  20 _N due to the resistance of the resistor R 2  in the negative feedback loop of the amplifier  15  being controlled according to the maximum and minimum output voltages. Therefore, a PSRR at a low frequency is enhanced. Furthermore, since the transistors M 3 _ 1  to M 3 _N of the replica units  20 _ 1  to  20 _N are NMOSs, the PSRR of the regulator  100  is close to 1/(gm×ro) at a high frequency, where gm and ro are the transconductance and the output resistance of the each of the transistors M 3 _ 1  to M 3 _N. In addition, reversed isolation from the LDO voltage V out  to the input voltage V ref  is better than the conventional replica LDO regulators, so the non-inverting input terminal of the amplifier  15  can be directly connected to a very sensitive reference point (e.g. a bandgap voltage VBG). 
         [0029]    According to the embodiments, the multi-output-level source follower typed replica capless LDO regulators can provide a high PSRR from several MHz to hundreds of MHz. Furthermore, through the cancellation mechanism, the regulators further improve low frequency PSRR. Therefore, the multi-output-level source follower typed replica capless LDO regulators can provide replicated output voltages to other circuits; especially level shifters, digital circuits, analog circuits, RF circuits and so on. 
         [0030]      FIG. 4  shows a regulator  200  according to another embodiment of the invention, wherein the regulator  200  is a multi-output-level source follower typed replica capless LDO voltage regulator. The regulator  200  comprises a basic unit  60  and a plurality of replica units  70 _ 1  to  70 _N. The basic unit  60  comprises a current source  13 , the transistors M 5  and M 6 , a switch SW 4 , a variable resistor R 3  controlled by the control signal S ctrl  and a current mirror  65 , wherein the current source  13  drains a bias current I bias3  from the current mirror  65  and then the current mirror  65  provides a current I mirror3  according to the bias current I bias3 . The replica units  70 _ 1  to  70 _N have the same circuits, each providing an individual LDO voltage at an individual output node. Take the replica unit  70 _ 1  as an example. The replica unit  70 _ 1  comprises a current source I 4 _ 1 , the transistors M 7 _ 1  and M 8 _ 1 , a switch SW 5 _ 1 , a variable resistor R 4 _ 1  controlled by a control signal S gain     —     1  and a current mirror  75 _ 1 , wherein the current source I 4 _ 1  drains a bias current I bias4     —     1  from the current mirror  75 _ 1  and the current mirror  75 _ 1  provides a current I mirror4     —     1  according to the bias current I bias4     —     1 . In the regulator  200 , the transistor M 5  and the transistors M 7 _ 1  to M 7 _N are PMOS transistors and the transistor M 6  and the transistors M 8 _ 1  to M 8 _N are NMOS transistors. In the embodiment, the transistor M 5  and the transistors M 7 _ 1  to M 7 _N are native devices. In other embodiments, the transistor M 5  and the transistors M 7 _ 1  to M 7 _N are N-type transistors of I/O or core circuit. Similarly, the output voltages V out     —     1  to V out     —     N  in the output nodes N out     —     1  to N out     —     N  are determined according to the resistances of the resistors R 4 _ 1  to R 4 _N in the replica units  70 _ 1  to  70 _N due to the bias voltage V bias , the gate-source voltages of the transistors M 4 _ 1  to M 4 _N and the currents I mirror4     —     1  to I mirror4     —     N  being the same, wherein each of the resistances of the resistors R 4 _ 1  to R 4 _N in the replica units  70 _ 1  to  70 _N is controlled by an individual control signal (e.g. S gain     —     1  to S gain     —     N ). Therefore, by using the control signals S gain     —     1  to S gain     —     N  to adjust the resistances of the resistors R 4 _ 1  to R 4 _N, the regulator  200  can provide the output voltages V out     —     1  to V out     —     N  with various voltage levels in the output nodes N out     —     1  to N out     —     N . In addition, the control unit  40  provides the control signal S ctrl  according to the control signals S gain     —     1  to S gain     —     N  to optimize PSRR performance for the output voltages V out     —     1  to V out     —     N . Moreover, the sizes of the devices within the replica units  70 _ 1  to  70 _N should be equal or proportional to the sizes of the devices within the basic unit  60 , such that each of the currents I mirror4     —     1  to I mirror4     —     N  matches the current I mirror3 . 
         [0031]      FIG. 5  shows a regulator  300  according to another embodiment of the invention. The regulator  300  is a PMOS typed replica capless LDO voltage regulator, which provides the LDO voltages V out     —     1  to V out     —     N  in the output nodes N out     —     1  to N out     —     N , respectively. Compared to the basic unit  30  of the regulator  100  in  FIG. 1 , the transistors M 1  and M 2  of a basic unit  80  are the same type of MOS transistors (i.e. PMOS), and a current circuit  85  of the basic unit  80  is not a current mirror. In the basic unit  80 , the current circuit  85  comprises a transistor M 9  coupled between the current source I 1  and a common node N com1 , and a current source  15  coupled between the common node N com1  and the ground GND. Furthermore, the transistor M 2  is coupled between the resistor R 3  and the common node N com1 . Thus, the current source I 5  drains a current I com1  from the common node N com1  to the ground GND, so that a current I 1  flowing through the transistor M 2  is determined according to the current I com1  and the bias current I bias1  (i.e. I bias1 +I 1 =I com1 ) when the transistor M 9  is controlled by a common voltage V com . Compared to the replica units  20 _ 1  to  20 _N of the regulator  100  in  FIG. 1 , the transistors M 3 _ 1  to M 3 _N and M 4 _ 1  to M 4 _N of the replica units  90 _ 1  to  90 _N are the same type of MOS transistors (i.e. PMOS), and each of the current circuits  95 _ 1  to  95 _N is not a current mirror. The current circuits  95 _ 1  to  95 _N have the same circuits. Take the current circuit  95 _ 1  as an example. In the current circuits  95 , a current source I 6 _ 1  drains a current I com2     —     1  from a common node N com2     —     1  to the ground GND, so that a current I 2     —     1  flowing through the transistor M 4 _ 1  is determined according to the current I com2     —     1  and the bias current I bias2     —     1  (i.e. I bias2 +I 2 =I com2 ) when a transistor M 10 _ 1  is controlled by the common voltage V com . In the regulator  300 , global matching is needed to be considered between the transistor M 2  and the transistors M 4 _ 1  to M 4 _N, between the current source I 1  and the current sources I 2 _ 1  to I 2 _N and between the current source I 5  and the current sources I 6 _ 1  to I 6 _N. Similarly, the output voltages V out     —     1  to V out     —     N  are determined according to the resistances of the resistors R 4 _ 1  to R 4 _N in the replica units  90 _ 1  to  90 _N due to the bias voltage V bias , the gate-source voltages of the transistors M 4 _ 1  to M 4 _N and the currents I 2 _ 1  to I 2 _N being the same, wherein each resistance of the resistors R 4 _ 1  to R 4 _N in the replica units  90 _ 1  to  90 _N is controlled by an individual control signal (e.g. S gain     —     1  to S gain     —     N ), thus the regulator  300  can provide the output voltages V out     —     1  to V out     —     N  with various voltage levels in the output nodes N out     —     1  to N out     —     N . Moreover, the sizes of the devices within the replica units  90 _ 1  to  90 _N should be equal or proportional to the sizes of the devices within the basic unit  80 , such that each of the currents I 2     —     1  to I 2     —     N  matches the current I 1 . 
         [0032]      FIG. 6  shows a regulator  400  according to another embodiment of the invention, wherein the regulator  400  is an NMOS typed replica capless LDO voltage regulator. Similarly, by using the control signals S gain     —     1  to S gain     —     N  to adjust the resistances of the resistors R 4 _ 1  to R 4 _N, the regulator  400  can provide the output voltages V out     —     1  to V out     —     N  with various voltage levels in the output nodes N out     —     1  to N out     —     N . Furthermore, for the regulator  300  of  FIG. 5  and the regulator  400  of  FIG. 6 , the control unit  40  provides the control signal S ctrl  to control the resistances of the resistors R 2  and R 3  according to the control signals S gain     —     1  to S gain     —     N , such that the core voltage V core  is equal to or close to an average of the output voltage with a maximum voltage level and the output voltage with a minimum voltage level. Thus, a PSRR at a low frequency can be enhanced through the PSRR cancellation mechanism, as described above. 
         [0033]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.