Abstract:
A bandgap reference voltage circuit includes a constant-current circuit, a reference voltage output circuit that generates a reference voltage according to the constant current, a power supply voltage detection circuit, and a start-up output circuit. The start-up output circuit supplies a starting potential to a node in the constant-current circuit until the power supply voltage detection circuit detects that the power supply has reached a voltage sufficient for the constant-current circuit to maintain operation. The power supply voltage detection circuit has circuit elements analogous to the circuit elements in the constant-current circuit that determine this voltage, enabling the start-up operation to be carried out and ended reliably. The start-up output circuit preferably includes a low-impedance path from the power supply to a node controlling supply of the starting potential, so that power-supply noise does not trigger unwanted output of the starting potential after the start-up operation has ended.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a circuit for generating a reference voltage, more particularly to a bandgap reference voltage circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    Bandgap reference voltage circuits are widely used because of their ability to generate a reference voltage that does not vary with temperature. FIG. 21 shows a bandgap reference voltage circuit described in, for example, Japanese Unexamined Patent Application Publication No. 11-231948. The circuit includes a reference stage  50  that generates a constant current proportional to a thermal voltage and generates the bandgap reference voltage from the constant current, a pair of start-up circuits  60 A,  60 B that start the reference stage  50  when power is initially applied, and a pair of filters  70 A,  70 B that filter the high power supply Vcc and lower power supply Vss.  
           [0005]    During operation, p-channel transistors P 500 , P 502 , P 508  form a first current mirror stage in the reference stage  50 , p-channel transistors P 505 , P 506 , P 509  form a second cascoded current mirror stage, and n-channel transistors N 500 , N 502  also form a current mirror. All of these transistors operate in their saturation regions, due to the connections of their gate electrodes to nodes  517 ,  518 , and  519 . Resistor R 500  enables the saturation state to be reached at a relatively low power-supply voltage. The current mirrors hold the currents on paths  512 ,  514 ,  516  to constant values determined by the sizes of bipolar transistors Q 500  and Q 502  and the value of resistor R 502 . The value of resistor R 504  and the base-emitter voltage of bipolar transistor Q 504  then establish a reference voltage Vref at node  510 , which is held by capacitor  510  and made available to external circuits (not shown).  
           [0006]    To generate the reference voltage Vref, it is necessary to initiate current flow on paths  512 ,  514 , and  516 , but the reference stage  50  is incapable of doing this by itself. The reason is basically that paths  512 ,  514 , and  516  will not conduct until electrons have been supplied to or removed from the gates of transistors P 500 -P 509 , N 500 , and N 502 , but electrons cannot be supplied and removed via paths  512 ,  514 ,  516  until these paths conduct. This dilemma is overcome by having the first start-up circuit  60 A draw electrons from the gates of transistors N 500  and N 502 , and the second start-up circuit  60 B supply electrons to the gates of transistors P 500 -P 509 . The start-up operation begins and ends as follows.  
           [0007]    When the bandgap reference voltage circuit in FIG. 21 is initially powered up and the high power supply voltage Vcc rises, p-channel transistors P 512  and P 514  promptly turn on and supply Vcc to node  518 , thereby turning on n-channel transistors N 500  and N 502 . Since node  522  is initially at the low power supply voltage Vss, p-channel transistor P 526  and n-channel transistor N 508  turn on, supplying Vss to node  519  and turning on p-channel transistors P 500 , P 502 , and P 508 . Node  517  is also pulled down to the Vss level through resistor R 500 , turning on p-channel transistors P 504 , P 506 , and P 509 . Current can now flow on paths  512 ,  514 , and  516 , and a reference voltage Vref is generated.  
           [0008]    When p-channel transistors P 500 -P 509  turn on, p-channel transistors P 516  and P 518  in start-up circuit  60 A also turn on, thereby supplying current to a disable node  520  and charging a connected capacitor C 502 . When the voltage at disable node  520  reaches such a level that the source-to-gate voltage of transistor P 512  no longer exceeds the threshold voltage, transistor P 512  turns off, ending the pulling up of node  518 .  
           [0009]    Similarly, as Vcc rises, p-channel transistors P 522  and P 524  in the second start-up circuit  60 B turn on, supplying current to another disable node  522  and charging a connected capacitor C 504 , while n-channel transistor N 504  remains off. When the voltage at disable node  522  reaches a predetermined level, p-channel transistor P 526  turns off, n-channel transistor N 506  turns on, and n-channel transistor N 508  turns off, ending the pulling down of node  519 . In addition, capacitor C 506  charges and transistor P 528  turns on, latching node  522  at the Vcc level.  
           [0010]    During subsequent operation, node  518  is clamped at a potential equal to the sum of the base-emitter voltage (Vbe 500 ) of bipolar transistor Q 500  and the threshold voltage (Vtn 500 ) of n-channel transistor N 500 . Transistor P 520  remains turned off if the voltage at disable node  520  is less than the sum of this potential (Vbe 500 +Vtn 500 ) and the threshold voltage (Vtp 520 ) of transistor P 520 . Accordingly, the voltage at the disable node  520  is clamped at approximately Vbe 500 +Vtn 500 +Vtp 520 .  
           [0011]    In this state, since transistors P 516  and P 518  are coupled to the first and second current mirror stages, they operate in their saturation regions, with high impedance. If the high power supply voltage Vcc varies, the variations are conducted to the source of transistor P 512  through transistor P 514 , which remains in the on state, but the variations do not significantly affect disable node  520 , because of the high impedance of transistors P 516  and P 518  and the cushioning effect of capacitor C 502 . As a result, the source-to-gate voltage of transistor P 512  varies and may from time to time exceed the threshold voltage, so that transistor P 512  turns on and supplies extra current to node  518 . This extra current increases the gate-source bias of n-channel transistors N 500  and N 502 , thereby increasing the current flow on paths  514  and  516 , the biasing of p-channel transistors P 500 -P 509 , and the potential of node  510 . If this behavior occurs repeatedly, due to periodic power-supply noise, for example, capacitor C 500  gradually acquires additional charge and the bandgap reference voltage Vref drifts upward. Noise in the low power supply Vss can also cause Vref to drift.  
           [0012]    The low-pass filters  70 A,  70 B in FIG. 21 are intended to solve this problem. By filtering Vcc, filter  70 A reduces variations in the source potential of transistor P 512  and prevents transistor P 512  from turning on in synchronization with periodic noise.  
           [0013]    The startup circuits  60 A,  60 B in FIG. 21 have problems other than noise, however. One problem is that, depending on the temperature characteristics of the circuit elements and the speed at which the high power supply Vcc rises when power is initially applied, the start-up operation (the pulling of nodes  518  and  519  up and down) may end too early or too late. If the start-up operation ends too early, before Vcc reaches the level necessary for constant current flow in the reference stage  50 , the reference stage  50  may fail to start (fail to operate), in which case no bandgap reference voltage is generated. If the start-up operation continues too long after Vcc reaches the necessary level, the bandgap reference voltage may overshoot its intended value, and power is needlessly consumed.  
           [0014]    Another problem is that transistors P 516 , P 518 , and P 520  in start-up circuit  60 A form a path through which unwanted current flows during steady-state operation.  
           [0015]    Furthermore, the filters  70 A,  70 B in FIG. 21 fail to attack the root cause of the rise in the bandgap reference voltage due to power-supply noise, which is that during normal operation, disable node  520  is connected to the high power supply Vcc on a high-impedance path through transistors P 516  and P 518 , and is held at a potential intermediate between the high power supply Vcc and the low power supply Vss, close to the switching point of p-channel transistor P 520 . These factors allow variations in the Vcc level to turn on transistor P 512 , as explained above.  
           [0016]    Since filter  70 A does not filter out low-frequency noise, it cannot completely prevent the periodic turning on of transistor P 512 . The reason is that transistors P 516  and P 518  and capacitor C 502  combine with filter  70 A to form an equivalent low-pass filter having a lower cut-off frequency than that of filter  70 A alone. As a result, low-frequency power-supply noise that reaches the source of transistor P 112  through filter  70 A and transistor P 514  may be cut off and fail to reach the gate of transistor P 512 . The consequent variations in the source-to-gate voltage of transistor P 512  then turn on transistor P 512 , causing a gradual rise in the bandgap reference voltage Vref.  
           [0017]    The bandgap reference voltage circuit shown in FIG. 21 thus lacks inherent immunity from power-supply noise. When power-supply noise with a frequency less than the cutoff frequency (fc) of filter  70 A is present, the bandgap reference voltage may gradually increase, just as if filter  70 A were absent.  
           [0018]    The above problems of the bandgap reference voltage circuit in FIG. 21 arise from the use of the reference stage  50  to control the transistors P 516 , P 518  and P 520  that control the switching of start-up transistor P 512 .  
         SUMMARY OF THE INVENTION  
         [0019]    An object of the present invention is to provide a bandgap reference voltage circuit that starts reliably, operates with reduced power consumption, and is highly immune to power-supply noise.  
           [0020]    The invented bandgap reference voltage circuit includes a constant-current circuit, a reference voltage output circuit, a power supply voltage detection circuit, and a start-up output circuit.  
           [0021]    The constant-current circuit receives a power supply and conducts a constant current proportional to a thermal voltage. The constant-current circuit has a starter node and includes first circuit elements defining a lower limit voltage, which is the lowest voltage of the power supply at which the constant-current circuit can operate.  
           [0022]    The reference voltage output circuit generates a bandgap reference voltage according to the constant current generated by the constant-current circuit.  
           [0023]    The power supply voltage detection circuit receives the power supply, and has second circuit elements similar to the first circuit elements in the constant-current circuit. By using the second circuit elements, the power supply voltage detection circuit detects whether the power supply has reached the lower limit voltage.  
           [0024]    The start-up output circuit starts the constant-current circuit by supplying a starting potential to the starter node, typically pulling the starter node up or down, until the power supply reaches the lower limit voltage. Supply of the starting potential to the starter node then ceases, and the flow of current through the power supply voltage detection circuit is preferably shut off.  
           [0025]    Providing the power supply voltage detection circuit with circuit elements similar to circuit elements in the constant-current circuit enables the power supply voltage detection circuit to detect with high reliability whether or not the power supply has reached the lower limit voltage and end the start-up operation at the proper time.  
           [0026]    The start-up output circuit has a node that controls the supply of the starting potential to the starter node in the constant-current circuit. After the lower limit voltage has been reached, this node is preferably connected by a low-impedance path to the power supply, so that power-supply noise does not trigger the unwanted further supply of the starting potential to the starter node.  
           [0027]    The constant-current circuit may include a negative feedback loop that reduces the dependence of the constant current on the voltage of the power supply. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    In the attached drawings:  
         [0029]    [0029]FIG. 1 is a circuit diagram of a bandgap reference voltage circuit illustrating a first embodiment of the invention;  
         [0030]    [0030]FIG. 2 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the first embodiment;  
         [0031]    [0031]FIG. 3 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the first embodiment;  
         [0032]    [0032]FIG. 4 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the first embodiment;  
         [0033]    [0033]FIG. 5 is a circuit diagram of a bandgap reference voltage circuit illustrating a second embodiment of the invention;  
         [0034]    [0034]FIG. 6 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the second embodiment;  
         [0035]    [0035]FIG. 7 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the second embodiment;  
         [0036]    [0036]FIG. 8 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the second embodiment;  
         [0037]    [0037]FIG. 9 is a circuit diagram of a bandgap reference voltage circuit illustrating a third embodiment of the invention;  
         [0038]    [0038]FIG. 10 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the third embodiment;  
         [0039]    [0039]FIG. 11 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the third embodiment;  
         [0040]    [0040]FIG. 12 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the third embodiment;  
         [0041]    [0041]FIG. 13 is a circuit diagram of a bandgap reference voltage circuit illustrating a fourth embodiment of the invention;  
         [0042]    [0042]FIG. 14 is a circuit diagram of a bandgap reference voltage circuit illustrating a variation of the fourth embodiment;  
         [0043]    [0043]FIG. 15 is a circuit diagram of a bandgap reference voltage circuit illustrating a fifth embodiment of the invention;  
         [0044]    [0044]FIG. 16 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the fifth embodiment;  
         [0045]    [0045]FIG. 17 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the fifth embodiment;  
         [0046]    [0046]FIG. 18 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the fifth embodiment;  
         [0047]    [0047]FIG. 19 is a circuit diagram of a bandgap reference voltage circuit illustrating a sixth embodiment of the invention;  
         [0048]    [0048]FIG. 20 is a circuit diagram of a bandgap reference voltage circuit illustrating a variation of the sixth embodiment; and  
         [0049]    [0049]FIG. 21 is a circuit diagram of a conventional bandgap reference voltage circuit. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0050]    Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.  
       First Embodiment  
       [0051]    [0051]FIG. 1 is a circuit diagram of a bandgap reference voltage circuit illustrating a first embodiment of the invention. This bandgap reference voltage circuit comprises a reference stage  10  and a start-up stage  20 . The reference stage  10  generates a constant current proportional to a thermal voltage, and generates a bandgap reference voltage from the constant current. The start-up stage  20  starts the reference stage  10  when power is initially applied.  
       Structure of the Reference Stage  10   
       [0052]    The reference stage  10  comprises a constant-current circuit  11  and a bandgap reference voltage output circuit  12 . The constant-current circuit  11  generates a constant current I 1  proportional to a thermal voltage. The bandgap reference voltage output circuit  12  generates a bandgap reference voltage Vref from the constant current I 1 .  
         [0053]    The constant-current circuit  11  comprises a first pair of p-channel metal-oxide-semiconductor (MOS) transistors P 100  and P 102 , a second pair of p-channel MOS transistors P 104  and P 106 , and a third pair of n-channel MOS transistors N 100  and N 102 . The sources of transistors P 100  and P 102  are coupled to the high power supply Vcc. The drain of transistor P 100  is coupled to the source of transistor P 104 , and the drain of transistor P 102  is coupled to the source of transistor P 106 . The drain of transistor P 104  is coupled to the drain of transistor N 100  at a starter node  118  to which the common gate of transistors N 100  and N 102  is also coupled. Transistors N 100  and N 102  have identical specifications, that is, identical dimensions and electrical characteristics.  
         [0054]    The constant-current circuit  11  further comprises resistors R 100  and R 102  and pnp bipolar transistors Q 100  and Q 102 . Resistor R 100  is coupled between the drains of transistors P 106  and N 102 . Transistor Q 100  has an emitter coupled to the source of transistor N 100 , a base coupled to the low power supply Vss, and a collector coupled to the substrate. Resistor R 102  is coupled between the source of transistor N 102  and the emitter of transistor Q 102 , which has a base coupled to the low power supply Vss and a collector coupled to the substrate.  
         [0055]    The bandgap reference voltage output circuit  12  comprises p-channel transistors P 108  and P 109 , a resistor R 104 , and a pnp bipolar transistor Q 104 , which are connected in series, and a capacitor C 100 . The source of transistor P 108  is coupled to the high power supply Vcc. The gate of transistor P 108  is coupled to the gate of transistor P 102 , and the gate of transistor P 109  is coupled to the gate of transistor P 106 . Transistor Q 104  has a base coupled to the low power supply Vss, a collector coupled to the substrate, and an emitter coupled through resistor R 104  to the drain of transistor P 109 . An output node  110  is disposed between the drain of transistor P 109  and resistor R 104 . Capacitor C 100  is coupled between the output node  110  and the low power supply Vss.  
         [0056]    In the reference stage  10 , transistors P 100 , P 102 , P 104 , P 106 , P 108 , and P 109  have identical specifications. Transistors P 100 , P 102 , and P 108  form a first current mirror stage, their gates being interconnected at node  119 . Transistors P 104 , P 106 , and P 109  form a second current mirror stage, their gates being interconnected at node  117 . Due to these interconnections, the current on path  112  is mirrored by the currents on parallel paths  114  and  116 . The first and second stages form a cascode current mirror circuit, in which the common gate of transistors P 100 , P 102 , and P 108  is connected to the drain of transistor P 106 , and the common gate of transistors P 104 , P 106 , and P 109  is coupled to the drain of transistor P 106  through resistor R 100 .  
       Structure of the Start-Up Stage  20   
       [0057]    The start-up stage  20  comprises a power supply voltage detection circuit  21  and a start-up output circuit  22 . When power is turned on, as the high power supply voltage Vcc rises, the power supply voltage detection circuit  21  conducts current and thereby generates a signal indicating whether Vcc has reached a predetermined lower limit voltage. Until Vcc reaches this lower limit voltage, the start-up output circuit  22  pulls up node  118  in the constant-current circuit  11 . After Vcc reaches the lower limit voltage, the start-up output circuit  22  stops pulling up node  118  and shuts off the flow of current in the power supply voltage detection circuit  21 .  
         [0058]    The power supply voltage detection circuit  21  comprises p-channel transistors P 110  and P 111 , n-channel transistors N 110  and N 111 , and a pnp bipolar transistor Q 110 . The source of transistor P 110  is coupled to the high power supply Vcc. Transistors P 111 , N 111 , and Q 110  are connected in series with transistor P 110 , the collector of transistor Q 110  being grounded to the substrate. Transistor N 110  is coupled between the low power supply Vss and a node  120 , which is connected to the drain of transistor P 110  and the source of transistor P 111 . The gate of transistor P 111  is coupled to the low power supply Vss. The gate of transistor N 111  is coupled to the high power supply Vcc. The base of transistor Q 110  is coupled to the low power supply Vss.  
         [0059]    The power supply voltage detection circuit  21  also comprises p-channel transistors P 112  and P 113  and a capacitor C 110 . Transistor P 112  has a gate coupled to node  120  and a source coupled to the high power supply Vcc. Transistor P 113  has a gate coupled to the high power supply Vcc, a source coupled to the drain of transistor P 112  at a node  121 , and a drain coupled to the low power supply Vss. Capacitor C 110  is coupled between node  121  and the low power supply Vss. Node  121  functions as the output terminal of the power supply voltage detection circuit  21  and the input terminal of the start-up output circuit  22 .  
         [0060]    Transistors P 111  and P 112 , transistor N 111 , and transistor Q 110  in the power supply voltage detection circuit  21  have the same specifications as transistors P 102  and P 106 , transistor N 102 , and transistor Q 100 , respectively, in the constant-current circuit  11 .  
         [0061]    The start-up output circuit  22  comprises p-channel transistors P 114 , P 115 , and P 116  and n-channel transistors N 112  and N 113 . Transistor P 114  has a gate coupled to node  121  and a source coupled to the high power supply Vcc. Transistor N 112  has a gate coupled to node  121  and a source coupled to the low power supply Vss. Transistor P 115  has a gate coupled to a node  122 , to which the drains of transistors P 114  and N 112  are coupled, and a source coupled to the high power supply Vcc. Transistor N 113  has a gate coupled to node  122  and a source coupled to the low power supply Vss. Transistor P 116  has a control input terminal or gate coupled to node  123 , to which the drains of transistors P 115  and N 113  are coupled, a source coupled to the high power supply Vcc, and a drain coupled to the starter node  118 . Transistor P 116  operates as a start-up switching element that pulls up starter node  118 . The voltage of node  123  is received by the gates of transistors P 110  and N 110  in the power supply voltage detection circuit  21 .  
       Operation of the First Embodiment  
       [0062]    The operation of the bandgap reference voltage circuit of the first embodiment shown in FIG. 1 will next be described. In this and subsequent descriptions, the following abbreviations will be used: Vbe means the base-emitter voltage of a pnp bipolar transistor; VDSsatp means the saturation source-drain voltage of a p-channel transistor; Vtp means the threshold voltage of a p-channel transistor; VDSsatn means the saturation source-drain voltage of an n-channel transistor; Vtn means the threshold voltage of an n-channel transistor. These abbreviations are followed by the corresponding reference numerals. For instance, the base-emitter voltage of pnp bipolar transistor Q 100  is denoted Vbe 100 ; the threshold voltage of p-channel transistor P 100  is denoted Vtp 100 ; the saturation source-drain voltage of n-channel transistor N 100  is denoted VDSsatn 100 ; the threshold voltage of n-channel transistor N 100  is denoted Vtn 100 . A similar notation will be used for resistances (r), e.g., the resistance of resistor R 100  is denoted r 100 .  
       Operation of the Reference Stage  10   
       [0063]    The operation of the reference stage  10  will be described under the assumptions that: the high power supply Vcc has reached a voltage level sufficient for operating the constant-current circuit  11 ; the emitter area ratio (Q 100 :Q 102 ) of transistors Q 100  and Q 102  is 1:N, where N is a positive number; and transistors Q 100  and Q 102  operate at collector current values in the diffusion region. Because the specifications of transistors P 100 , P 102 , P 104 , P 106 , P 108 , and P 109  are the same, and the specifications of transistors N 100  and N 102  are the same, the constant current I 1  generated by the constant-current circuit  11 , flowing through transistors P 100  and P 102 , P 104  and P 106 , and P 108  and P 109 , is expressed as follows.  
           I   1 (1/r 102 )* K *( T/q )* LN ( N )  (1)  
         [0064]    where K is the Boltzmann constant, T is absolute temperature, q is the charge of the electron, and LN(N) is the natural logarithm of the emitter area ratio N of transistors Q 100  and Q 102 . Equation (1) ignores the power-supply dependence of the current I 1 , due to the dependence of the drain currents of p-channel MOS transistors P 100 , P 102 , P 104 , P 106 , P 108 , and P 109  and n-channel MOS transistors N 100  and N 102  on the drain voltage of these transistors (the effective channel-length modulation effect).  
         [0065]    Given that transistor Q 104  in the bandgap reference voltage output circuit  12  operates at a collector current value in the diffusion region, the voltage Vref at the output node  110  of the bandgap reference voltage output circuit  12  is expressed as follows:  
           Vref =Vbe 104 +(r 104 /r 102 )* K *( T/q )* LN ( N )  (2)  
         [0066]    Voltage Vbe 104  has a negative temperature coefficient. If the resistance ratio r 104 /r 102  and the emitter area ratio N between transistors Q 100  and Q 102  are set so as to cancel out this temperature coefficient, the resultant bandgap reference voltage Vref becomes almost insensitive to variations in temperature. Like equation (1), equation (2) ignores the power supply dependence of the current I 1  due to the effective channel-length modulation effect.  
         [0067]    The constant-current circuit  11  can generate a constant current I 1  only when all of its p-channel and n-channel transistors P 100 , P 102 , P 104 , P 106 , N 100 , and N 102  operate in the saturation region. Therefore, the constant-current circuit  11  requires a high power supply voltage Vcc equal to or greater than the higher of the following two voltage levels: the lowest level (VCC 1 ) of Vcc that enables transistors P 100 , P 104 , and N 100  to operate in the saturation region on path  112 ; and the lowest level (VCC 2 ) of Vcc that enables transistors P 102 , P 106 , and N 102  to operate in the saturation region on path  114 .  
         [0068]    Voltage levels VCC 1  and VCC 2  are expressible as follows.  
         VCC 1 =Vbe 100 +VDSsatp 100 +VDSsatp 104 +Vtn 100   (3)  
         VCC 2 =Vbe 102 + I   1 *r 102 +VDSsatn 102 +Vtp 106 +VDSsatp 102 =Vbe 100 +VDSsatn 102 +Vtp 106 +VDSsatp 102   (4)  
         [0069]    Equation (4) assumes that the following two optimum design conditions are satisfied.  
           I   1 *r 100 =VDSsatp 102 =VDSsatp 106   
         Vtp 106 =Vtp 102   
         [0070]    In the first embodiment, it is assumed that VCC 1  is equal to or less than VCC 2 .  
         [0071]    During the period while the high power supply voltage Vcc is ramping up to the VCC 2  level, the start-up stage  20  keeps node  118  pulled up to a voltage level sufficient to turn on transistors N 100  and N 102 . When transistor N 102  turns on, the potentials of nodes  117  and  119  are lowered, enabling the p-channel transistors in the cascode current mirror circuit to turn on. After the high power supply Vcc reaches voltage level VCC 2 , all of the MOS transistors on paths  112  and  114  have saturated, and the constant-current circuit  11  can maintain a constant current flow without the need for further assistance from the start-up stage  20 .  
       Operation of the Start-Up Stage  20   
       [0072]    Before power is initially applied, that is, while the high power supply voltage Vcc is 0 V, transistor P 113  functions as a MOS diode and discharges capacitor C 110 . Accordingly, the voltage at node  121  does not exceed the threshold voltage Vtp 113  of transistor P 113 .  
         [0073]    As the high power supply Vcc rises, transistor P 113  is held in the off state and the voltage level at node  121  remains at its original level, not exceeding the threshold voltage Vtp 113  of transistor P 113 . This threshold voltage Vtp 113  is set below the threshold voltage Vtn 112  of transistor N 112 . As the high power supply Vcc increases, the voltage at the output node  122  of the inverter formed by transistors P 114  and N 112  goes high and increases together with Vcc. The voltage at the output node  123  of the inverter comprising transistors P 115  and N 113  therefore goes low. This low voltage is received at the gate of starter transistor P 116  and the gates of transistors P 110  and N 110  in the power supply voltage detection circuit  21 . Starter transistor P 116  is turned on, pulling up starter node  118 , while transistor N 110  is turned off, and transistor P 110  is turned on.  
         [0074]    The start-up stage  20  is designed so that the sum of the saturation source-drain voltage of transistor N 113  and the threshold voltage of transistor P 110  (VDSsatn 113 +Vtp 110 ) is lower than the sum of the saturation source-drain voltage of transistor P 111 , the saturation source-drain voltage of transistor N 111 , and the base-emitter voltage of transistor Q 110  (VDSsatp 111 +VDSsatn 111 +Vbe 110 ). Transistor P 110  therefore turns on before transistors P 111 , N 111 , and Q 110 . The voltage at node  120 , which is the drain voltage of transistor P 110 , remains approximately equal to the high power supply Vcc from when Vcc exceeds the VDSsatn 113 +Vtp 110  level until Vcc exceeds the VDSsatp 111 +VDSsatn 111 +Vbe 110  level. The potential at the gate of transistor P 112  likewise remains approximately equal to the high power supply Vcc, so transistor P 112  remains off.  
         [0075]    When the high power supply Vcc exceeds the voltage level VDSsatp 111 +VDSsatn 111 +Vbe 110 , transistors P 111 , N 111 , and Q 110  turn on, conducting current from the drain of transistor P 110  and clamping node  120  at an approximately constant voltage (VDSsatp 111 +VDSsatn 111 +Vbe 110 ). A voltage of (Vcc−(VDSsatp 111 +VDSsatn 111 +Vbe 110 )) is applied between the source and gate of transistor P 112 .  
         [0076]    When the high power supply Vcc exceeds the sum of the saturation source-drain voltage of transistor P 111 , the saturation source-drain voltage of transistor N 111 , the base-emitter voltage of transistor Q 110 , and the threshold voltage of transistor P 112  (VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ), transistor P 112  is continuously turned on, conducts current, and starts charging capacitor C 110 . The voltage at node  121  rises in accordance with the time constant determined by the capacitance of capacitor C 110 .  
         [0077]    When the voltage at node  121  reaches the switching threshold of the inverter formed by transistors P 114  and N 112 , node  122  goes low, and the output node  123  of the inverter formed by transistors P 115  and N 113  goes high, completing the output of the single-shot pulse that started when output node  123  went low.  
         [0078]    The low-to-high transition in the voltage level at node  123  turns off starter transistor P 116 , ending the pulling up of starter node  118 . By this time, the voltage at starter node  118  has reached a level exceeding the sum of the source voltage of transistors N 100  and N 102  and their threshold voltage Vtn, so transistors N 100  and N 102  have turned on, the p-channel transistors in the cascode current mirror circuit have also turned on, and saturation current is flowing on paths  112 ,  114 , and  116  in the reference stage  10 .  
         [0079]    If the high power supply Vcc rises slowly, the constant-current circuit  11  may be able to start operating without the need for capacitor C 110 . If Vcc rises rapidly, however, capacitor C 110  is required in order to keep node  123  from going high before the start-up stage  20  can finish pulling up node  118  to the level necessary to start the constant-current circuit  11 . Capacitor C 110  ensures that the constant-current circuit  11  will start up reliably even if the high power supply Vcc reaches the VCC 2  level instantaneously.  
         [0080]    The low-to-high transition at node  123  also turns off transistor P 110  and turns on transistor N 110 , latching node  120  at the low logic level. Transistor P 112  is held in the on state, and node  121  is held at the high logic level.  
         [0081]    In the first embodiment, the lower limit of the high power supply Vcc necessary for operation of the constant-current circuit  11  (the VCC 2  value given in equation (4) as Vbe 100 +VDSsatn 102 +Vtp 106 +VDSsatp 102 ) is defined by transistors P 102 , P 106 , N 102 , and Q 100  in the constant-current circuit  11 . The power supply voltage detection circuit  21  uses corresponding transistors P 111 , P 112 , N 111 , and Q 110  to detect a voltage level (VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ) equal to the lower limit VCC 2 . Until the high power supply Vcc is detected to have reached this level, the start-up output circuit  22  keeps node  118  pulled up to a voltage level sufficient to turn on transistors N 100  and N 102  in the constant-current circuit  11 . When the high power supply Vcc reaches the VCC 2  voltage level (VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ), the pull-up operation is completed, and all current flow in the start-up stage  20  ends.  
         [0082]    For transistors N 100  and N 102  to operate, the voltage at the starter node  118  must be at least Vbe 100 +Vtn 100 . The period needed for starter node  118  to reach this voltage level (Vbe 100 +Vtn 100 ) coincides with the period needed for Vcc to reach the lower limit voltage level VCC 2  (equal to VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ). During this period, starter transistor P 116  keeps starter node  118  pulled up and transistors N 100  and N 102  turned on. After Vcc reaches the VCC 2  level, starter transistor P 116  is turned off and the constant-current circuit  11  maintains node  118  at the necessary level. Therefore, in the first embodiment, the constant-current circuit  11  can start correctly and generate a bandgap reference voltage Vref with high reliability, irrespective of the speed with which the high power supply Vcc rises or the temperature characteristics of the components of the power supply voltage detection circuit.  
         [0083]    The bandgap reference voltage circuit in the first embodiment can generate a bandgap reference voltage Vref reliably if the constant-current circuit  11  is capable of operating alone when the high power supply Vcc is above VCC 2 , that is, if VCC 2  is higher than VCC 1  (if Vbe 100 +VDSsatn 102 +Vtp 106 +VDSsatp 102 &gt;Vbc 100 +VDSsatp 100 +VDSsatp 104 +Vtn 100 ). The first embodiment is accordingly applicable to devices fabricated by a process that makes (2*VDSsatp+Vtn)&lt;(VDSsatn+Vtp+VDSsatp).  
         [0084]    In the bandgap reference voltage circuit of the first embodiment, when the high power supply Vcc reaches the lower limit VCC 2  (=VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ), transistor P 112  turns on, and node  121  goes high. This turns on transistors N 112  and P 115  in the start-up output circuit  22 , clamping node  122  low and node  123  high. Accordingly, transistor N 110  in the power supply voltage detection circuit  21  is turned on, clamping node  120  low. Transistor P 112  is therefore held securely in the on state, and the high power supply Vcc is conducted with low impedance to node  121 . Transistor P 115  is also held securely in the on state, and the high power supply Vcc is conducted with low impedance to node  123 . Nodes  121  and  123  can therefore stay in phase with power-supply noise on the high power supply Vcc.  
         [0085]    Initially, node  121  serves as the control input to the start-up output circuit  22 , and node  123  controls the startup operation of the constant-current circuit  11  performed by the start-up output circuit  22 , by turning starter transistor P 116  on and off. In the steady-state operation after the constant-current circuit  11  has started up, since nodes  121  and  123  stay in phase with power-supply noise, the source and gate voltages of starter transistor P 116  can stay in phase, despite power-supply noise, so that transistor P 116  is not turned on due to power-supply noise after the high power supply Vcc has reached the VCC 2  level. Because the starter transistor  116  is held securely in the off state, the bandgap reference voltage will not gradually rise because of periodic power-supply noise.  
         [0086]    In the bandgap reference voltage circuit of the first embodiment, when the high power supply Vcc reaches the VCC 2  level (=VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ), transistor P 112  is turned on, pulling up node  121  to the high level, thus turning on transistors N 112  and P 115  in the start-up output circuit  22  and clamping node  123  at the high level, so that transistor P 110  in the power supply voltage detection circuit  21  is turned off and held in the off state. Therefore, in the steady-state operation after the constant-current circuit  11  has started up, there is no path on which unwanted current can flow through the start-up stage  20 . As steady-state operation is thus free of unwanted current flow, power consumption is be reduced.  
       First Variation of the First Embodiment  
       [0087]    [0087]FIG. 2 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the first embodiment. In comparison with the circuit in FIG. 1, the reference stage  10  and power supply voltage detection circuit  21  have the same configuration, but the start-up output circuit  22  in the start-up stage  20  has a different configuration.  
         [0088]    The start-up output circuit  22  in FIG. 2 differs from the start-up output circuit  22  in FIG. 1 in that the startup transistor is an n-channel transistor N 114 , instead of a p-channel transistor. Transistor N 114  has a gate coupled to node  122 , a source coupled to the low power supply Vss, and a drain coupled to node  117 , which is now the starter node in the constant-current circuit  11 .  
         [0089]    The start-up stage  20  of the first variation of the first embodiment starts the constant-current circuit  11  by keeping node  117  pulled down substantially from the time when power is initially applied until the high power supply Vcc reaches the VCC 2  level value given by equation (4). This variation, like the first embodiment described above, is applicable if the constant-current circuit  11  can maintain constant-current operation when Vcc is higher than VCC 2 .  
         [0090]    In the first embodiment, the common gate of n-channel transistors N 100  and N 102  in the constant-current circuit  11  is kept pulled up to the level of the high power supply Vcc until the high power supply Vcc reaches the VCC 2  voltage level, so that transistors N 100  and N 102  turn on quickly, enabling the constant-current circuit  11  to start up.  
         [0091]    In the first variation of the first embodiment, the common gate of p-channel transistors P 104  and P 106  is pulled down to the low power supply level Vss, and the common gate of transistors P 100  and P 102  is also pulled down to the Vss level through resistor R 100 . This forces the cascode current mirror circuit comprising p-channel transistors P 100 , P 102 , P 104 , and P 106  to operate in a way that quickly brings node  118  to the level necessary for n-channel transistors N 100  and N 102  to turn on, so that the constant-current circuit  11  can start up. The first variation has substantially the same effects as the first embodiment.  
       Second Variation of the First Embodiment  
       [0092]    [0092]FIG. 3 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the first embodiment. In comparison with the first embodiment shown in FIG. 1, the start-up output circuit  22  in the start-up stage  20  has the same configuration while the reference stage  10  and the power supply voltage detection circuit  21  have different configurations.  
         [0093]    Whereas the constant-current circuit  11  in the first embodiment had p-channel transistors connected in a cascode current mirror configuration, the second variation employs a simpler current mirror configuration. The constant-current circuit  11  in FIG. 3 differs from the constant-current circuit  11  in FIG. 1 in that transistors P 104  and P 106  and resistor R 100  are eliminated. The bandgap reference voltage output circuit  12  in FIG. 3 differs from the bandgap reference voltage output circuit  12  in FIG. 1 in that transistor P 109  is eliminated. The power supply voltage detection circuit  21  in FIG. 3 differs from the power supply voltage detection circuit  21  shown in FIG. 1 in that transistor P 111  is eliminated.  
         [0094]    In the second variation of the first embodiment, the start-up stage  20  keeps the common gate of n-channel transistors N 100  and N 102  in the constant-current circuit  11  pulled up to the high power supply Vcc until the high power supply Vcc reaches the sum of the saturation source-drain voltage of transistor N 111 , the base-emitter voltage of transistor Q 110 , and the threshold voltage of transistor P 112  (VDSsatn 111 +Vbe 110 +Vtp 112 ). The constant-current circuit  11  starts operating when the voltage at the common gate reaches a level sufficient to turn on transistors N 100  and N 102 .  
         [0095]    The second variation of the first embodiment is applicable if the bandgap reference voltage circuit is fabricated by a process such that (VDSsatp+Vtn)&lt;(VDSsatn+Vtp). The constant-current circuit  11  can then maintain constant-current operation if the high power supply Vcc is at least the sum of the saturation source-drain voltage of transistor N 102 , the base-emitter voltage of transistor Q 100 , and the threshold voltage of transistor P 102  (Vbe 100 +VDSsatn 102 +Vtp 102 ). This is lower than the VCC 2  value given by equation (4), making the second variation of the first embodiment useful for low-voltage applications.  
       Third Variation of the First Embodiment  
       [0096]    [0096]FIG. 4 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the first embodiment. The reference stage  10  and the power supply voltage detection circuit  21  of this circuit have the same configuration as in the second variation of the first embodiment, and the start-up output circuit  22  has the same configuration as in the first variation of the first embodiment. The drain of transistor N 114  is coupled to a node  119  which functions as the starter node in the constant-current circuit  11 .  
         [0097]    In the bandgap reference voltage circuit of the third variation of the first embodiment, the common gate of p-channel transistors P 100  and P 102  is kept pulled down until the high power supply Vcc reaches the voltage level VDSsatn 111 +Vbe 110 +Vtp 112 . By this point transistors N 100  and N 102  have turned on and the constant-current circuit  11  can maintain constant-current operation on its own. This third variation has substantially the same effects as the second variation.  
       Second Embodiment  
       [0098]    [0098]FIG. 5 is a circuit diagram of a bandgap reference voltage circuit illustrating a second embodiment of the invention, this embodiment also comprising a reference stage  10  and a start-up stage  20 . The reference stage  10  has the same configuration as in the first embodiment; the start-up stage  20  has a different configuration.  
       Structure of the Start-Up Stage  20   
       [0099]    In the start-up stage  20  shown in FIG. 5, the power supply voltage detection circuit  21  comprises p-channel transistors P 111  and P 112  and n-channel transistor N 110 . The source of transistor N 110  is coupled to the low power supply Vss. Transistors P 111  and P 112  are connected in series between the high power supply Vcc and node  120 , which is coupled to the drain of transistor N 110 . The gates of transistors P 111  and P 112  are coupled to the low power supply Vss.  
         [0100]    The power supply voltage detection circuit  21  in FIG. 5 also comprises n-channel transistors N 111 , N 115 , and N 117 , pnp bipolar transistor Q 110 , and capacitor C 110 . Transistor Q 110  has a collector grounded to the substrate and a base coupled to the low power supply Vss. Transistor N 111  has a source coupled to the emitter of transistor Q 110  and a gate coupled to node  120 . Transistor N 117  has a gate coupled to the low power supply Vss, a source coupled to node  121 , which is coupled to the drain of transistor N 111 , and a drain coupled to the high power supply Vcc. Transistor N 115  is inserted between node  121  and the low power supply Vss. Capacitor C 110  is coupled between the high power supply Vcc and node  121 . Node  121  functions as the output terminal of the power supply voltage detection circuit  21  and the input terminal of the start-up output circuit  22 .  
         [0101]    Transistors P 111  and P 112 , transistor N 111 , and transistor Q 110  in the power supply voltage detection circuit  21  have the same specifications as transistors P 100  and P 104 , transistor N 100 , and transistor Q 100 , respectively, in the constant-current circuit  11 .  
         [0102]    The start-up output circuit  22  in FIG. 5 comprises p-channel transistors P 114 , P 115 , and P 116  and n-channel transistors N 112  and N 113 . Transistor P 114  has a gate coupled to node  121  and a source coupled to the high power supply Vcc. Transistor N 112  has a gate coupled to node  121  and a source coupled to the low power supply Vss. Transistor P 115  has a gate coupled to a node  122  to which the drains of transistors P 114  and N 112  are connected, and a source coupled to the high power supply Vcc. Transistor N 113  has a gate coupled to node  122  and a source coupled to the low power supply Vss. Transistor P 116  has a gate coupled to node  122 , a source coupled to the high power supply Vcc, and a drain coupled to starter node  118 , so that transistor P 116  pulls up starter node  118 . Node  122  is coupled to the gate of transistor N 115  in the power supply voltage detection circuit  21 , while the node  123  to which the drains of transistors P 115  and N 113  are connected is coupled to the gate of transistor N 110  in the power supply voltage detection circuit  21 .  
         [0103]    The start-up output circuit  22  of the second embodiment differs from the start-up output circuit  22  of the first embodiment (see FIG. 1) in the following two regards: the gate of starter transistor P 116  is coupled to node  122  instead of node  123 ; this node  122  is coupled to the power supply voltage detection circuit  21 .  
       Operation of the Second Embodiment  
       [0104]    The operation of the bandgap reference voltage circuit of the second embodiment shown in FIG. 5 will next be described. The reference stage  10  of the second embodiment shown in FIG. 5 operates in the same way as the reference stage  10  of the first embodiment (see FIG. 1).  
         [0105]    In the second embodiment, as in the first embodiment, the start-up stage  20  is needed to bring the voltage at node  118  up to a level sufficient to turn on transistors N 100  and N 102  when power is initially supplied. The start-up stage  20  in the second embodiment keeps node  118  pulled up to this level until the high power supply Vcc reaches the voltage level VCC 1  given in equation (3). The second embodiment is thus applicable when the minimum voltage that enables the constant-current circuit  11  to operate independently is VCC 1 ; that is, when VCC 1  is equal to or greater than the VCC 2  value given by equation (4).  
         [0106]    The operation of the start-up stage  20  in FIG. 5 will now be described. Before power is initially applied, that is, while the high power supply Vcc is 0 V, transistor N 117  functions as a MOS diode and discharges capacitor C 110 . Accordingly, the difference between the voltage at node  121  and the high power supply Vcc does not exceed the threshold voltage Vtn 117  of transistor N 117 .  
         [0107]    The voltage level at node  121  increases as the high power supply Vcc rises. The threshold voltage Vtp 114  of transistor P 114  is set higher than the threshold voltage Vtn 117  of transistor N 117 , so the voltage at the output node  122  of the inverter formed by transistors P 114  and N 112  goes low, and the voltage at the output node  123  of the inverter formed by transistors P 115  and N 113  goes high, rising with the high power supply Vcc. The low voltage at node  122  is received at the gate of transistor N 115  in the start-up output circuit  22 , and keeps transistor N 115  turned off. The voltage at node  122  is also received at the gate of starter transistor P 116 , which is turned on and pulls up starter node  118 .  
         [0108]    When the high power supply Vcc exceeds the sum of the saturation source-drain voltage of transistor P 115  and the threshold voltage of transistor N 110  (VDSsatp 115 +Vtn 110 ), transistor N 110  turns on sufficiently for transistors P 111  and P 112  to operate as a MOS cascode circuit. The current capability of this MOS cascode circuit is set higher than the current capability of transistor N 110 ; specifically, the saturation source-drain voltage VDSsatn 110  of transistor N 110  is set higher than the sum of the saturation source-drain voltage of transistor P 111  and the saturation source-drain voltage of transistor P 112  (VDSsatp 111 +VDSsatp 112 ). The voltage at node  120 , which is the drain voltage of transistor N 110 , is therefore clamped at a voltage level obtained by subtracting the saturation source-drain voltages of transistors P 111  and P 112  from the high power supply voltage (Vcc−(VDSsatp 111 +VDSsatp 112 )). The voltage at node  120  increases as Vcc rises.  
         [0109]    When the high power supply Vcc reaches a level exceeding the sum of the saturation source-drain voltages of transistors P 111  and P 112 , the base-emitter voltage of transistor Q 110 , and the threshold voltage of transistor N 111  (VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 112 ), transistor N 111  turns on, conducts current, and starts charging capacitor C 110 . The voltage at node  121  falls in accordance with the time constant determined by the capacitance of capacitor C 110 .  
         [0110]    When the voltage at node  121  decreases to the switching threshold of the inverter formed by transistors P 114  and N 112 , node  122  goes high, and the output node  123  of the inverter formed by transistors P 115  and N 113  goes low. The output of the single-shot pulse that started when output node  123  went high is completed when output node  123  goes low.  
         [0111]    The low-to-high transition at node  122  turns on transistor N 115 , while the high-to-low transition at node  123  turns off transistor N 110 . Node  120  is now clamped at the high logic level, and transistor N 111  is fully turned on. With transistor N 115  likewise turned on, node  121  is held at the low logic level.  
         [0112]    Even when transistor N 111  is fully turned on, it does not provide a low-impedance path between node  121  and the low power supply Vss, because this path also passes through transistor Q 110 . Once transistor N 115  is turned on, however, the impedance between node  121  and the low power supply Vss becomes adequately low, as the path through transistor N 115  bypasses transistor Q 110 .  
         [0113]    The low-to-high transition in the voltage level at node  122  also turns off starter transistor P 116 , ending the pulling up of starter node  118 . This completes the start-up operation that pulls the voltage at starter node  118  above the sum of the source voltage of transistors N 100  and N 102  and the threshold voltage Vtn as the supply voltage rises.  
         [0114]    In the bandgap reference voltage circuit of the second embodiment, the lower limit of the high power supply Vcc necessary for operation of the constant-current circuit  11  (the VCC 1  value given by equation (3) as Vbe 100 +VDSsatp 100 +VDSsatp 104 +Vtn 100 ) is defined by transistors P 100 , P 104 , N 100 , and Q 100  in the constant-current circuit  11 . The power supply voltage detection circuit  21  uses corresponding transistors P 111 , P 112 , N 111 , and Q 110  to detect a voltage level VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 111 , which is equal to the lower limit VCC 1 . Until the high power supply Vcc reaches the VCC 1  level, the start-up output circuit  22  keeps node  118  pulled up to a voltage level sufficient to turn on transistors N 100  and N 102  in the constant-current circuit  11 . When the high power supply Vcc reaches the VCC 1  voltage level (VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 11 ), the pull-up operation is completed, and all current flow in the start-up stage  20  ends.  
         [0115]    Like the first embodiment, the second embodiment can start the constant-current circuit  11  and generate the bandgap reference voltage Vref with high reliability, irrespective of the speed with which the high power supply Vcc rises or the temperature characteristics of the components of the power supply voltage detection circuit. In addition, after the high power supply Vcc reaches the lower limit value VCC 1 , power consumption is reduced, and increases in the bandgap reference voltage Vref due to power-supply noise are prevented.  
         [0116]    The bandgap reference voltage circuit of the second embodiment can generate a bandgap reference voltage Vref reliably if the lower limit of the high power supply Vcc necessary for operation of the constant-current circuit  11  is VCC 1  (=Vbc 100 +VDSsatp 100 +VDSsatp 104 +Vtn 100 ); that is, if a process is used that makes (2*VDSsatp+Vtn)&gt;(VDSsatn+Vtp+VDSsatp), so that VCC 1  is higher than VCC 2  (=Vbe 100 +VDSsatn 102 +Vtp 106 +VDSsatp 102 ).  
         [0117]    In the bandgap reference voltage circuit of the second embodiment, when the high power supply Vcc reaches the lower limit VCC 1  (=VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 111 ), transistor N 111  turns on, and the potential of node  121  starts to fall. Shortly thereafter, the transistors in the start-up output circuit  22  switch on/off states, node  122  goes high, and transistor N 115  in the power supply voltage detection circuit  21  is held securely in the on state, establishing a low-impedance path between the low power supply Vss and node  121 . Node  121  is thus held at the low logic level and transistor P 114  is held securely in the on state, creating a low-impedance path between the high power supply Vcc and node  122 .  
         [0118]    Node  122 , which controls the pull-up operation of starter node  118  by turning starter transistor P 116  on and off, can therefore stay in phase with electrical noise in the high power supply Vcc. Because the source voltage and gate voltage of starter transistor P 116  are both in phase with the power-supply noise, starter transistor P 116  does not turn on due to power-supply noise after the high power supply Vcc reaches the lower limit level VCC 1 . Because the starter transistor P 116  is held securely in the off state, the bandgap reference voltage will not gradually rise due to periodic power-supply noise.  
         [0119]    In the steady-state operation after the high power supply Vcc has reached VCC 1  (=VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 111 ) and the constant-current circuit  11  has started up, nodes  120  and  122  are high, nodes  121  and  123  are low, and transistors P 111 , P 112 , P 114 , N 111 , N 113 , and N 115  are turned on, but transistors P 115 , P 116 , N 110 , N 112 , and N 117  are securely turned off. Therefore, there is no path on which current can flow through the start-up stage  20 . The steady-state operation is thus free of unwanted current flow, and power consumption is reduced.  
       First Variation of the Second Embodiment  
       [0120]    [0120]FIG. 6 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the second embodiment. In comparison with the circuit in FIG. 5, the reference stage  10  and the power supply voltage detection circuit  21  have the same configuration, but the start-up output circuit  22  in the start-up stage  20  has a different configuration.  
         [0121]    The start-up output circuit  22  in FIG. 6 differs from the start-up output circuit  22  in FIG. 5 in that the startup transistor is an n-channel transistor N 114 , instead of the p-channel transistor. Transistor N 114  has a gate coupled to node  123 , a source coupled to the low power supply Vss, and a drain coupled to node  117 , which is now the starter node in the constant-current circuit  11 .  
         [0122]    The start-up stage  20  of the first variation of the second embodiment starts the constant-current circuit  11  by keeping node  117  pulled down until the high power supply Vcc reaches the VCC 1  level value given by equation (3). This variation, like the second embodiment described above, is applicable if the constant-current circuit  11  can maintain constant-current operation when Vcc is higher than VCC 1 .  
         [0123]    In the second embodiment, the common gate of n-channel transistors N 100  and N 102  in the constant-current circuit  11  is kept pulled up to the level of the high power supply Vcc until the high power supply Vcc reaches the VCC 1  voltage, so that transistors N 100  and N 102  turn on quickly, enabling the constant-current circuit  11  to start up.  
         [0124]    In the first variation of the second embodiment, the common gate of p-channel transistors P 104  and P 106  is pulled down to the low power supply Vss, and the common gate of p-channel transistors P 100  and P 102  is also pulled down to the low power supply Vss through resistor R 100 . This forces the cascode current mirror circuit comprising p-channel transistors P 100 , P 102 , P 104 , and P 106  to operate in a way that quickly brings node  118  to the level necessary for n-channel transistors N 100  and N 102  to turn on, so that the constant-current circuit  11  can start up. The first variation has substantially the same effects as the second embodiment.  
       Second Variation of the Second Embodiment  
       [0125]    [0125]FIG. 7 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the second embodiment. In comparison with the second embodiment shown in FIG. 5, the start-up output circuit  22  in the start-up stage  20  has the same configuration while the reference stage  10  and the power supply voltage detection circuit  21  have different configurations.  
         [0126]    The reference stage  10  in the second variation of the second embodiment has the same circuit topology as in the second variation of the first embodiment (FIG. 3). Compared with FIG. 5, transistors P 104  and P 106  and resistor R 100  are eliminated from the constant-current circuit  11 , transistor P 109  is eliminated from the bandgap reference voltage output circuit  12 , and transistor P 112  is eliminated from the power supply voltage detection circuit  21 .  
         [0127]    In the second variation of the second embodiment, the start-up stage  20  keeps the common gate of n-channel transistors N 100  and N 102  in the constant-current circuit  11  pulled up to the high power supply Vcc until the high power supply Vcc reaches the voltage level VDSsatp 111 +Vbe 110 +Vtn 111 . The constant-current circuit  11  starts operating when the voltage at the common gate reaches a level sufficient to turn on transistors N 100  and N 102 .  
         [0128]    The second variation of the second embodiment is applicable if the bandgap reference voltage circuit is fabricated by a process such that (VDSsatp+Vtn)&gt;(VDSsatn+Vtp) The constant-current circuit  11  can then maintain constant-current operation if the high power supply Vcc is at least Vbe 100 +VDSsatp 100 +Vtn 100 . This is lower than the VCC 1  value given by equation (3), making the second variation of the second embodiment useful for low-voltage applications.  
       Third Variation of the Second Embodiment  
       [0129]    [0129]FIG. 8 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the second embodiment. The reference stage  10  and the power supply voltage detection circuit  21  of this circuit have the same configuration as in the second variation of the second embodiment, and the start-up output circuit  22  has the same configuration as in the first variation of the second embodiment. The drain of transistor N 114  is coupled to a node  119  which functions as the starter node in the constant-current circuit  11 .  
         [0130]    In the bandgap reference voltage circuit of the third variation of the second embodiment, the common gate of p-channel transistors P 100  and P 102  is kept pulled down from when power is initially applied until the high power supply Vcc reaches the voltage level VDSsatp 111 +Vbe 110 +Vtn 111 . By this point transistors N 100  and N 102  have turned on and the constant-current circuit  11  can maintain constant-current operation on its own. This third variation has substantially the same effects as the second variation.  
       Third Embodiment  
       [0131]    [0131]FIG. 9 is a circuit diagram of a bandgap reference voltage circuit illustrating a third embodiment of the invention, this embodiment also comprising a reference stage  10  and a start-up stage  20 . The start-up stage  20  has the same configuration as in the first embodiment, while the reference stage  10  has a different configuration.  
         [0132]    The reference stage  10  comprises a constant-current circuit  11  and a bandgap reference voltage output circuit  12 . The bandgap reference voltage output circuit  12  has the same configuration as in the first embodiment (see FIG. 1), while the constant-current circuit  11  has a different configuration.  
       Structure of the Reference Stage  10   
       [0133]    The constant-current circuit  11  in the third embodiment differs from the constant-current circuit  11  in the preceding embodiments by including a third current path and a negative feedback loop. Specifically, the constant-current circuit  11  in FIG. 9 comprises a first triad of p-channel transistors P 100 , P 101 , and P 102 , a second triad of p-channel transistors P 103 , P 104 , and P 106 , a pair of n-channel transistors N 100  and N 102 , and another n-channel transistor N 104 . The sources of transistors P 100 , P 101 , and P 102 , are coupled to the high power supply Vcc. The drains of transistors P 100 , P 101 , and P 102 , are coupled respectively to the sources of transistors P 104 , P 103 , and P 106 . The drains of transistors P 104  and P 106  are coupled respectively to the drains of transistors N 100  and N 102 . The common gate of transistors N 100  and N 102  is coupled to a node  117  connected to the drains of transistors P 106  and N 102 . The gate of transistor N 104  is coupled to a node  118  connected to the drains of transistors P 104  and N 100 . Transistors N 100 , N 102 , and N 104  have identical specifications.  
         [0134]    The constant-current circuit  11  further comprises resistors R 100  and R 102 , pnp bipolar transistors Q 100 , Q 102 , and Q 106 , and a capacitor C 104  that provides phase compensation for the negative feedback loop, which will be described later. Resistor R 100  is coupled between the drains of transistors P 103  and N 104 . Transistor Q 100  has an emitter coupled to the source of transistor N 100 , a base coupled to the low power supply Vss, and a collector coupled to the substrate. Transistor Q 106  has an emitter coupled to the source of transistor N 104 , a base coupled to the low power supply Vss, and a collector coupled to the substrate. Resistor R 102  is coupled between the source of transistor N 102  and the emitter of transistor Q 102 . Transistor Q 102  has a base coupled to the low power supply Vss and a collector coupled to the substrate. The phase-compensation capacitor C 104  is coupled between node  118  and the low power supply Vss.  
         [0135]    Transistors P 100 , P 101 , P 102 , P 103 , P 104 , P 106 , P 108 , and P 109  in the reference stage  10  have identical specifications. Transistors P 100 , P 101 , P 102 , and P 108  form a first current mirror stage while transistors P 103 , P 104 , P 106 , and P 109  form a second current mirror stage. The first and second stages form a cascode current mirror circuit in which the common gate of transistors P 100 , P 101 , P 102 , and P 108  is coupled to a node  113 , which is coupled to the drain of transistor P 103 , and the common gate of transistors P 103 , P 104 , P 106 , and P 109  is coupled to a node  119 , which is coupled to the drain of transistor N 104  and to the drain of transistor P 103  through resistor R 100 .  
         [0136]    Transistors P 111  and P 112 , transistor N 111 , and transistor Q 110  in the power supply voltage detection circuit  21  in FIG. 9 have the same specifications as transistors P 101  and P 103 , transistor N 104 , and transistor Q 106 , respectively, in the constant-current circuit  11 .  
       Operation of the Third Embodiment  
       [0137]    The operation of the third embodiment will be described under the assumptions that: the high power supply Vcc has reached the voltage level necessary for operation of the constant-current circuit  11 ; the emitter area ratio Q 100 :Q 106 :Q 102  of transistors Q 100 , Q 106 , and Q 102  is 1:1:N, where N is a positive number; and transistors Q 100 , Q 106 , and Q 102  operate at collector current values in the diffusion region. Because the specifications of transistors P 100 , P 101 , P 102 , P 103 , P 104 , P 106 , P 108 , and P 109  are the same, and the specifications of transistors N 100 , N 102 , and N 104  are the same, the constant current I 1  generated by the constant-current circuit  11 , flowing through transistors P 100  and P 102 , P 101  and P 103 , P 104  and P 106 , and P 108  and P 109 , is expressed by the same equation (1) as in the first embodiment, provided the drain voltage dependence of the drain current of each MOS transistor (the effective channel-length modulation effect) is ignored.  
         [0138]    The purpose of the negative feedback loop in the constant-current circuit  11  in the third embodiment is to reduce the drain voltage dependence of transistors N 100  and N 102  on the high power supply Vcc. In the conventional constant-current circuit employed in the preceding embodiments, this dependence can have noticeable effects when Vcc has a high value.  
         [0139]    In the first embodiment (FIG. 1), once the high power supply Vcc had reached the voltage level necessary for operation of the constant-current circuit  11  and the startup operation had ended, the drain voltage of transistor N 100  was determined by the low power supply Vss, being clamped to a virtually constant level (Vbe 100 +Vtn 100 ) equal to the sum of the base-emitter voltage of transistor Q 100  and the threshold voltage of transistor N 100 . The drain voltage of transistor N 102 , however, was determined by the high power supply Vcc, being clamped to another virtually constant level (Vcc−(VDSsatp 102 +Vtp 106 )) obtained by subtracting the sum of the saturation source-drain voltage of transistor P 102  and the threshold voltage of transistor P 106  from the high power supply Vcc.  
         [0140]    The difference between the drain voltages of transistors N 100  and N 102  (the potential difference between nodes  117  and  118 ) could thus be expressed as:  
         ( Vcc −(VDSsatp 102 +Vtp 106 ))−(Vbe 100 +Vtn 100 )  
         [0141]    At the minimum voltage level VCC 2  necessary for operation of the constant-current circuit  11  in the first embodiment, this potential difference was equal to VDSsatn 102 −Vtn 100 . If the high power supply Vcc continued to increase past the VCC 2  level, however, the potential difference would increase further. Due to the effective channel-length modulation effect of transistors N 102  and P 104 , the constant-current circuit  11  would then raise the potential of node  118  and move to an operating point with increased drain current. Therefore, if the high power supply voltage Vcc increased past VCC 2 , the actual constant current I 1  could increase above the I 1  value given by equation (1).  
         [0142]    The negative feedback loop in the third embodiment reduces the potential increase at node  118  arising from the dependence of drain voltages and drain currents on the high power supply Vcc. In the constant-current circuit  11  in FIG. 9, if the potential of node  118  rises because of an increase in the high power supply Vcc, the gate-to-source voltage Vgs 104  of transistor N 104  rises. This increases the drain current Ids 104  of transistor N 104 , decreasing the potentials at the common gates of transistors P 100 , P 101 , P 102 , and P 108  and transistors P 103 , P 104 , P 106 , and P 109 . The drain current Ids 100  of transistor N 100  and the drain current Ids 102  of transistor N 102  then increase by virtually equal amounts. Because resistor R 102  is coupled to the source of transistor N 102 , the voltage increase ΔV 117  at node  117  caused by the increase ΔIds 102  in the drain current Ids 102  of transistor N 102  is expressed as follows.  
         ΔV 117 = SQRT (ΔIds 102 /( k/ 2 *W/L ))+ΔIds 102 *r 102 + K*t/q*LN (ΔIds 102 /( N*Is ))  (5)  
         [0143]    The voltage increase ΔV 118  at node  118  caused by the increase ΔIds 100  in the drain current Ids 100  of transistor N 100  is expressed as follows.  
         ΔV 118 = SQRT (ΔIds 100 /( k/ 2 *W/L ))+ K*t/q*LN (ΔIds 100 / Is )  (6)  
         [0144]    In equations (5) and (6), W/L is the width-to-length ratio of the n-channel transistor, K is the Boltzmann constant, T is absolute temperature, q is the charge of the electron, N is the emitter area ratio between transistors Q 100  and Q 102 , and Is is the base-emitter reverse saturation current of transistor Q 100 . The constant k represents μn*Cox, where μn is the electron mobility and Cox is the capacitance of the gate oxide film of the transistor. SQRT(x) is the square root of x, and LN(x) is the natural logarithm of x.  
         [0145]    The voltage changes expressed by the third term in equation (5) and the second term in equation (6) are logarithmically compressed with respect to the changes in drain current, making the values of these two terms much smaller than the values of the other terms. If those terms are ignored, equations (5) and (6) simplify to:  
         ΔV 117 = SQRT (ΔIds 102 /( k /2 *W/L ))+ΔIds 102 *r 102   (5)′ 
         ΔV 118 = SQRT (ΔIds 100 /( k /2 *W/L ))  (6)′ 
         [0146]    Because the increase ΔIds 100  in the drain current Ids 100  of transistor N 100  is substantially equal to the increase ΔIds 102  in the drain current Ids 102  of transistor N 102 , the ΔV 117  value given by equation (5)′ is greater than the ΔV 118  value given by equation (6)′. In other words, the potential at node  117 , which is the gate potential of transistor N 100 , increases by more than is necessary to enable transistor N 100  to conduct the additional drain current greater ΔIds 100 . Accordingly, the voltage at node  118  decreases.  
         [0147]    Conversely, if the voltage at node  118  decreases below the proper level, then the gate potentials of the p-channel transistors rise, the drain current Ids 100  of transistor N 100  and the drain current Ids 102  of transistor N 102  decrease, and the potential of node  117  decreases, decreasing the gate-to-source voltage of transistor N 100 . This decrease outweighs the decrease ΔIds 100  in the drain current Ids 100  of transistor N 100 . Accordingly, the voltage at node  118  increases.  
         [0148]    A negative feedback loop is thus established that confines the circuit operation range within narrow limits, minimizing the influence of variations in the voltage level of the high power supply Vcc on the voltages at nodes  117  and  118 . The phase-compensation capacitor C 104  prevents the negative feedback loop from becoming a positive feedback loop.  
         [0149]    Given that transistor Q 104  in the bandgap reference voltage output circuit  12  operates at a collector current value in the diffusion region, the voltage Vref at the output node  110  of the bandgap reference voltage output circuit  12  in FIG. 9 is the same as in the first embodiment, as given by equation (2), which ignores the drain voltage dependence of the drain currents of the MOS transistors (the effective channel-length modulation effect).  
         [0150]    The constant-current circuit  11  can generate a constant current only when all of its p-channel and n-channel transistors P 100 , P 101 , P 102 , P 103 , P 104 , P 106 , N 100 , N 102 , and N 104  are operating in the saturation region. If the transistors P 100 , P 104 , and N 100  on path  112  are saturated, then the transistors P 102 , P 106 , and N 102  on path  114  are also saturated. Therefore, the constant-current circuit  11  requires a high power supply voltage Vcc equal to or greater than the higher of the following two voltage levels: the lowest level (VCC 1 ) of Vcc that enables transistors P 100 , P 104 , and N 100  to operate in the saturation region on the series path  112  through transistors P 100 , P 104 , N 100 , and Q 100 ; and the lowest level (VCC 2 ) of Vcc that enables transistors P 101 , P 103 , and N 104  to operate in the saturation region on the series path through transistors P 101 , P 103 , resistor R 100 , and transistors N 104 , and Q 106 .  
         [0151]    Voltage level VCC 1  can be expressed as in equation (3). level VCC 2  can be expressed as follows.  
         VCC 2 =Vbe 106 +VDSsatn 104 +Vtp 103 +VDSsatp 101   (7)  
         [0152]    Equation (7) assumes that the following two optimum design conditions are satisfied.  
         I 1 *r 100 =VDSsatp 101 =VDSsatp 103   
         Vtp 101 =Vtp 103   
         [0153]    In the third embodiment, when power is initially supplied, the start-up stage  20  brings the voltage at node  118  up to a level sufficient to turn on transistor N 104 , so that current can flow on the path through transistors P 101 , P 103 , N 104 , and Q 106  to start the constant-current circuit  11 . The start-up stage  20  in the third embodiment keeps node  118  pulled up to this level until the high power supply Vcc reaches the voltage level VCC 2  given in equation (7). The second embodiment is thus applicable when the minimum voltage that enables the constant-current circuit  11  to operate independently is VCC 2 .  
         [0154]    The start-up stage  20  operates in the same way in the third embodiment as in the first embodiment (see FIG. 1). After the start-up stage  20  starts up the constant-current circuit  11 , the voltage at the starter node  118  changes from the pulled-up level, which is at least the sum of the source voltage of transistor N 104  and the threshold voltage Vtn, to a steady-state voltage and is held steady by the negative feedback loop described above.  
         [0155]    In the bandgap reference voltage circuit of the third embodiment, if the lower limit of the high power supply Vcc necessary for operation of the constant-current circuit  11  is the VCC 2  value (Vbe 106 +VDSsatn 104 +Vtp 103 +VDSsatp 101 ) given by equation (7), the lower limit VCC 2  is defined by transistors P 101 , P 103 , N 104 , and Q 106  in the constant-current circuit  11 . The power supply voltage detection circuit  21  uses corresponding transistors P 111 , P 112 , N 111 , and Q 110  to detect a voltage level VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 , which is equal to the lower limit VCC 2 . Until the high power supply Vcc reaches the VCC 2  level, the start-up output circuit  22  keeps node  118  pulled up to a level sufficient to turn on transistor N 104  in the constant-current circuit  11 . When the high power supply Vcc reaches the VCC 2  level (VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 ), the pull-up operation is completed, and the supply of current from the start-up output circuit  22  ends.  
         [0156]    As in the preceding embodiments, the bandgap reference voltage circuit in the third embodiment can start the constant-current circuit  11  and generate the bandgap reference voltage Vref with high reliability, irrespective of the speed with which the high power supply Vcc rises or the temperature characteristics of the components of the power supply voltage detection circuit, and can reduce power consumption and prevent increases in the bandgap reference voltage Vref after the high power supply Vcc reaches the lower limit value VCC 2 .  
         [0157]    The bandgap reference voltage circuit in the third embodiment can generate a bandgap reference voltage reliably if the constant-current circuit  11  is capable of operating alone when the high power supply Vcc is above the VCC 2  level; that is, if a fabrication process is used that makes (2*VDSsatp+Vtn)&lt;(VDSsatn+Vtp+VDSsatp), so that VCC 2  is higher than VCC 1  (Vbe 106 +VDSsatn 104 +Vtp 103 +VDSsatp 101 &gt;Vbc 100 +VDSsatp 100 +VDSsatp 104 +Vtn 100 ).  
         [0158]    In the bandgap reference voltage circuit of the third embodiment, as in the first embodiment, once the high power supply Vcc reaches VCC 2 , transistor P 115  turns on and a low-impedance path is established between Vcc and node  123 , so that the source and gate potentials of transistor P 116  both remain in phase with power-supply noise, and the bandgap reference voltage will not gradually rise due to such noise. At the same time, transistor P 110  is turned off, leaving no path on which unwanted current can flow through the start-up stage  20 . As steady-state operation is thus free of unwanted current flow, power consumption is reduced.  
         [0159]    The constant-current circuit  11  in the third embodiment also has a negative feedback loop that controls the potential of node  118 . As a result, the-drain voltages of transistors N 100  and N 102  are determined independently of the level of the high power supply Vcc, and variations in difference between the drain voltage of transistor N 100  and the drain voltage of transistor N 102  caused by variations in the voltage level of the high power supply Vcc are reduced. Accordingly, variations in the constant current Ii due to the effective channel-length modulation effect of transistors N 102  and P 104  are reduced. Correct circuit operation can therefore be ensured over a wide range of operating supply voltages, and an accurate bandgap reference voltage can be generated even if the bandgap reference voltage circuit is fabricated by a process that leads to a high effective channel-length modulation effect in p-channel and n-channel transistors.  
       First Variation of the Third Embodiment  
       [0160]    [0160]FIG. 10 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the third embodiment. In comparison with the circuit in FIG. 9, the reference stage  10  and the power supply voltage detection circuit  21  in the start-up stage  20  have the same configuration, while the start-up output circuit  22  has a different configuration.  
         [0161]    The start-up output circuit  22  in FIG. 10 differs from the start-up output circuit  22  in FIG. 9 in that the startup transistor is an n-channel transistor N 114 , instead of a p-channel transistor P 116 . Transistor N 114  has a gate coupled to node  122 , a source coupled to the low power supply Vss, and a drain coupled to node  119 , which is now the starter node in the constant-current circuit  11 .  
         [0162]    The start-up stage  20  of the first variation of the third embodiment starts the constant-current circuit  11  by keeping node  119  pulled down until the high power supply Vcc reaches the VCC 2  level value given by equation (7). This variation, like the first embodiment described above, is applicable if the constant-current circuit  11  can maintain constant-current operation when Vcc is higher than VCC 2 .  
         [0163]    In the third embodiment as described above, the constant-current circuit  11  is started by pulling the gate voltage of n-channel transistor N 104  up to the level of the high power supply Vcc so that transistor N 104  can turn on quickly.  
         [0164]    In the first variation of the third embodiment, the constant-current circuit  11  is started by pulling the common gate of p-channel transistors P 103 , P 104 , and P 106  down to the level of the low power supply Vss. The common gate of transistors P 100 , P 101 , and P 102  is also pulled down to the Vss level through resistor R 100 . This forces the cascode current mirror circuit comprising p-channel transistors P 100 , P 101 , and P 102  and p-channel transistors P 103 , P 104  and P 106  to operate in a way that quickly brings nodes  117  and  118  to the level necessary for n-channel transistors N 100 , N 102 , and N 104  to turn on, so that the constant-current circuit  11  can start up. The first variation has substantially the same effects as the third embodiment.  
       Second Variation of the Third Embodiment  
       [0165]    [0165]FIG. 11 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the third embodiment. In comparison with the third embodiment shown in FIG. 9, the start-up output circuit  22  in the start-up stage  20  has the same configuration, while the reference stage  10  and the power supply voltage detection circuit  21  have different configurations.  
         [0166]    Whereas the constant-current circuit  11  in the third embodiment had p-channel transistors connected in a cascode current mirror configuration, the second variation employs a simpler current mirror configuration. The constant-current circuit  11  in FIG. 11 differs from the constant-current circuit  11  in FIG. 9 in that transistors P 104 , P 106 , and P 103  and resistor R 100  are eliminated. The bandgap reference voltage output circuit  12  in FIG. 11 differs from the bandgap reference voltage output circuit  12  in FIG. 9 in that transistor P 109  is eliminated. The power supply voltage detection circuit  21  in FIG. 11 differs from the power supply voltage detection circuit  21  in FIG. 9 in that transistor P 111  is eliminated.  
         [0167]    In the second variation of the third embodiment, the start-up stage  20  keeps the gate voltage of n-channel transistor N 104  in the constant-current circuit  11  pulled up to the level of the high power supply Vcc until Vcc reaches the sum of the threshold voltage of p-channel transistor P 112 , the saturation source-drain voltage of n-channel transistor N 111 , and the base-emitter voltage of bipolar transistor Q 110  (VDSsatn 111 +Vbe 110 +Vtp 112 ). The constant-current circuit  11  starts up when the gate potential of transistor N 104  reaches a level sufficient for transistor N 104  to turn on.  
         [0168]    The second variation of the third embodiment is applicable if the bandgap reference voltage circuit is fabricated by a process such that (VDSsatp+Vtn)&lt;(VDSsatn+Vtp). The constant-current circuit  11  can then maintain constant-current operation if the high power supply Vcc is at least the sum of the threshold voltage of p-channel transistor P 102 , the saturation source-drain voltage of n-channel transistor N 102 , and the base-emitter voltage of bipolar transistor Q 100  (Vbe 100 +VDSsatn 102 +Vtp 102 ). This is lower than the VCC 2  value given by equation (7), making the second variation of the third embodiment useful for low-voltage applications.  
       Third Variation of the Third Embodiment  
       [0169]    [0169]FIG. 12 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the third embodiment. The reference stage  10  and the power supply voltage detection circuit  21  of this circuit have the same configuration as in the second variation of the third embodiment, and the start-up output circuit  22  has the same configuration as in the first variation of the third embodiment.  
         [0170]    In the start-up stage  20  of the third variation of the third embodiment, the common gate of p-channel transistors P 100 , P 101 , and P 102  is pulled down to the low power supply level Vss until the high power supply Vcc reaches the voltage level VDSsatn 111 +Vbe 110 +Vtp 112 . By this time transistors N 100 , N 102 , and N 104  have turned on and the constant-current circuit  11  can maintain constant-current operation on its own. This third variation has substantially the same effects as the second variation.  
       Fourth Embodiment  
       [0171]    [0171]FIG. 13 is a circuit diagram of a bandgap reference voltage circuit illustrating a fourth embodiment of the invention, comprising a reference stage  10  and a start-up stage  20 . The start-up stage  20  has the same configuration as in the first and third embodiments. The reference stage  10  has a different configuration.  
         [0172]    As in the preceding embodiments, the reference stage  10  of the fourth embodiment comprises a constant-current circuit  11  and a bandgap reference voltage output circuit  12 . The bandgap reference voltage output circuit  12  has the same configuration as in all of the preceding embodiments. The constant-current circuit  11  has a different configuration from the constant-current circuit  11  in any of the preceding embodiments or their variations.  
         [0173]    The constant-current circuit  11  in FIG. 13 comprises seven p-channel transistors P 100 -P 106  and four n-channel transistors N 100 , N 101 , N 102 , and N 104 . The sources of transistors P 100 , P 101 , P 102 , and P 105 , are coupled to the high power supply Vcc. The drains of transistors P 100 , P 101 , and P 102  are coupled respectively to the sources of transistors P 104 , P 103 , and P 106 . The drains of transistors P 104 , P 103 , and P 106  are coupled respectively to the drains of transistors N 100 , N 104 , and N 102 . The drain of transistor P 105  is coupled to the drain of transistor N 101 . The common gate of transistors N 100  and N 102  is coupled to a node  117  connected to the drains of transistors P 106  and N 102 . The gates of transistors N 101  and  104  are coupled to a node  118  connected to the drains of transistors P 104  and N 100 . Transistors N 100 , N 101 , N 102 , and N 104  have identical specifications.  
         [0174]    The constant-current circuit  11  further comprises a resistor R 102 , pnp bipolar transistors Q 100 , Q 102 , Q 106 , and Q 108 , and a capacitor C 104  that provides phase compensation for a feedback loop. Transistor Q 100  has an emitter coupled to the source of transistor N 100 , a base coupled to the low power supply Vss, and a collector coupled to the substrate. Transistor Q 106  has an emitter coupled to the source of transistor N 104 , a base coupled to the low power supply Vss, and a collector coupled to the substrate. Transistor Q 108  has an emitter coupled to the source of transistor N 101 , a base coupled to the low power supply Vss, and a collector coupled to the substrate. Resistor R 102  is coupled between the source of transistor N 102  and the emitter of transistor Q 102 . Transistor Q 102  has a base coupled to the low power supply Vss and a collector coupled to the substrate. The phase-compensation capacitor C 104  for the feedback loop in the constant-current circuit  11  is coupled between node  118  and the low power supply Vss.  
         [0175]    Transistors P 100 , P 102 , P 103 , P 104 , P 106 , P 108 , and P 109  in the reference stage  10  have identical specifications. The common gate of transistors P 100 , P 102 , P 105 , and P 108  is coupled to a node connected to the drain of transistor P 105 . The common gate of transistors P 101 , P 103 , P 104 , P 106 , and P 109  is coupled to a node  119  connected to the drain of transistor P 103 . Transistors P 100 , P 102 , P 105 , and P 108  form a first current mirror stage, while transistors P 104 , P 106 , and P 109  form a second current mirror stage. Transistors P 100 , P 102 , and P 108  in the first stage and transistors P 104 , P 106 , and P 109  in the second stage form a cascode current mirror circuit. Transistor P 105  in the first stage functions as a diode and applies a bias voltage to the common gate of transistors P 100 , P 102 , and P 108 . Transistors P 101  and P 103  in the second stage function as diodes and apply a bias voltage to the common gate of transistors P 104 , P 106 , and P 109 .  
         [0176]    Transistors P 111  and P 112 , transistor N 111 , and transistor Q 110  in the power supply voltage detection circuit  21  in FIG. 13 have the same specifications as transistors P 101  and P 103 , transistor N 104 , and transistor Q 106 , respectively, in the constant-current circuit  11 .  
       Operation of the Fourth Embodiment  
       [0177]    The operation of the bandgap reference voltage circuit of the fourth embodiment shown in FIG. 13 will be described under the assumptions that: the high power supply Vcc has reached the voltage level necessary for operation of the constant-current circuit  11 ; the emitter area ratio Q 100 :Q 108 :Q 106 :Q 102  of transistors Q 100 , Q 108 , Q 106 , and Q 102  is 1:1:1:N, where N is a positive number; and transistors Q 100 , Q 108 , Q 106 , and Q 102  operate at collector current values in the diffusion region. Because the specifications of transistors P 100 , P 102 , P 103 , P 104 , P 105 , P 106 , P 108 , and P 109  are the same, and the specifications of transistors N 100 , N 101 , N 102 , and N 104  are the same, the constant current I 1  generated by the constant-current circuit  11 , flowing through transistors P 100  and P 104 , P 101  and P 103 , P 102  and P 106 , and P 108  and P 109 , is expressed by the same equation (1) as in the first embodiment, provided the drain voltage dependence of the drain current of each MOS transistor (effective channel-length modulation effect) is ignored.  
         [0178]    Like the constant-current circuit  11  in the third embodiment, the constant-current circuit  11  in the fourth embodiment has a negative feedback loop. The constant-current circuit  11  of the fourth embodiment differs from the constant-current circuit  11  in the first embodiment (see FIG. 1) and from the conventional constant-current circuit in that the drain voltage dependence of transistors N 100  and N 102  on the high power supply Vcc is greatly reduced.  
         [0179]    As explained in the third embodiment, if the high power supply Vcc continues to rise after passing the voltage level VCC 2  necessary for operation of the constant-current circuit  11  in the first embodiment, the difference between the drain voltages of transistors N 100  and N 102  also increases, the difference being expressed as:  
         ( Vcc −(VDSsatp 102 +Vtp 106 ))−(Vbe 100 +Vtn 100 )  
         [0180]    As the difference between the drain voltages of transistors N 100  and N 102  increases, due to the effective channel-length modulation effect of transistors N 102  and P 104 , the constant-current circuit  11  raises the voltage at node  118  and moves to an operating point with increased drain current. Therefore, as the high power supply voltage Vcc ramps up, the actual constant current I 1  increases above the I 1  value given by equation (1).  
         [0181]    The constant-current circuit  11  in the fourth embodiment uses a negative feedback loop to minimize the increase in voltage at node  118  arising from the dependence on the high power supply Vcc, as in the third embodiment. In the constant-current circuit  11  in FIG. 13, if the voltage at node  118  increases as the high power supply Vcc increases, the gate-to-source voltage Vgs 104  of transistor N 104  and the gate-to-source voltage Vgs 101  of transistor N 101  rise. This increases the drain current Ids 104  of transistor N 104  and the drain current Ids 101  of transistor N 101 , decreasing the voltages at the common gates of transistors P 100 , P 102 , P 105 , and P 108  and transistors P 103 , P 104 , P 106 , and P 109 . The drain current Ids 100  of transistor N 100  and the drain current Ids 102  of transistor N 102  then increase by virtually equal amounts. Because resistor R 102  is coupled to the source of transistor N 102 , the voltage increase ΔV 117  at node  117  caused by the increase ΔIds 102  in the drain current Ids 102  of transistor N 102  is expressed by equation (5). The voltage increase ΔV 118  at node  118  caused by the increase ΔIds 100  in the drain current Ids 100  of transistor N 100  is expressed by the equation (6). Accordingly, the voltage at node  118  decreases, as explained in the third embodiment. The phase-compensation capacitor C 104  is provided to prevent the negative feedback loop from becoming a positive feedback loop.  
         [0182]    In the third embodiment, the resistance of resistor R 100  was set so that  
         VDSsatp 101 / I   1 =VDSsatp 103 / I   1    
         [0183]    in order to bring the voltage at the common gate of transistors P 104 , P 106 , and P 109  in the second current mirror stage to the voltage level Vcc−(Vtp+VDSsatp), so that the cascode current mirror circuit formed by the first stage comprising transistors P 100 , P 101 , P 102 , and P 108  and the second stage comprising transistors P 103 , P 104 , P 106 , and P 109  in the reference stage  10  can operate at a low voltage.  
         [0184]    In the fourth embodiment, however, the dimensions of transistor P 101  are set so that  
         VDSsatp 101 =VDSsatp 100 =VDSsatp 102   
         [0185]    so that the voltage at the common gate of transistors P 104 , P 106 , and P 109  in the second current mirror stage becomes equal to Vcc−(Vtp+VDSsatp).  
         [0186]    If transistor Q 104  in the bandgap reference voltage output circuit  12  in FIG. 13 operates at a collector current value in the diffusion region, the voltage Vref at the output node  110  of the bandgap reference voltage output circuit  12  is the same as in the first embodiment, as given by equation (2), ignoring the drain voltage dependence of the drain currents of the MOS transistors (effective channel-length modulation effect).  
         [0187]    The constant-current circuit  11  of the fourth embodiment in FIG. 13 can generate a constant current only when all of its p-channel and n-channel transistors P 100 , P 102 , P 103 , P 104 , P 105 , P 106 , N 100 , N 101 , N 102 , and N 104  are operating in the saturation region. Therefore, the constant-current circuit  11  requires a high power supply voltage Vcc equal to or greater than the higher of the following two voltage levels: the lowest level (VCC 1 ) of Vcc that enables transistors P 100 , P 104 , and N 100  to operate in the saturation region on the series path  112  through transistors P 100 , P 104 , N 100 , and Q 100 ; and the lowest level (VCC 2 ) of Vcc that enables transistors P 101 , P 103 , and N 104  to operate in the saturation region on the series path through transistors P 101 , P 103 , N 104 , and Q 106 . The VCC 1  value is expressed by equation (3) while the VCC 2  value is expressed by equation (7).  
         [0188]    In the bandgap reference voltage circuit of the fourth embodiment, as in the preceding embodiments, the start-up stage  20  is needed to bring the voltage at node  118  up to a level sufficient to turn on transistors N 100  and N 102  when power is initially supplied. The start-up stage  20  operates in the same way in the fourth embodiment as in the first embodiment (see FIG. 1). After the start-up stage  20  starts up the constant-current circuit  11 , the voltage at the starter node  118  changes from the pulled-up level, which is at least the sum of the source voltage of transistors N 100  and N 102  and their threshold voltage Vtn, to a steady-state voltage and is held steady by the negative feedback loop.  
         [0189]    If the minimum high power supply voltage Vcc necessary for operation of the constant-current circuit  11  is the VCC 2  value (Vbe 106 +VDSsatn 104 +Vtp 103 +VDSsatp 101 ) given by equation (7), the bandgap reference voltage circuit of the fourth embodiment can start the constant-current circuit  11  and generate the bandgap reference voltage Vref with high reliability, irrespective of the speed with which the high power supply Vcc rises or the temperature characteristics of the components of the power supply voltage detection circuit, and can reduce power consumption and prevent increases in the bandgap reference voltage Vref after the high power supply Vcc reaches the lower limit value VCC 2 . The bandgap reference voltage circuit in the fourth embodiment can generate a bandgap reference voltage reliably if the device is fabricated by a process that makes (2*VDSsatp+Vtn)&lt;(VDSsatn+Vtp+VDSsatp).  
         [0190]    In the bandgap reference voltage circuit of the fourth embodiment, as in the first embodiment, once the high power supply Vcc reaches the lower limit value VCC 2 , a low-impedance path is established between the high power supply Vcc and node  123 , so that the bandgap reference voltage will not gradually rise due to power-supply noise. At the same time, transistor P 110  in the power supply voltage detection circuit  21  is turned off, leaving no path on which unwanted current can flow through the start-up stage  20 . As steady-state operation is thus free of unwanted current flow, power consumption is reduced.  
         [0191]    The constant-current circuit  11  in the fourth embodiment also has a negative feedback loop that controls the potential of node  118 . As a result, variations in the constant current I 1  due to the effective channel-length modulation effect of transistors N 102  and P 104  are minimized. Correct circuit operation can therefore be ensured over a wide range of operating supply voltages, and an accurate bandgap reference voltage can be generated even if the bandgap reference voltage circuit is fabricated by a process that leads to a high effective channel-length modulation effect in p-channel and n-channel transistors.  
         [0192]    In the conventional bandgap reference voltage circuit shown in FIG. 21, the resistance r 100  of resistor R 100  is set to VDSsatp/I 1  in order to bring the voltage at the common gate of the p-channel transistors in the second stage of the cascode current mirror circuit to the voltage level Vcc (Vtp+VDSsatp), so that the cascode current mirror circuit in the reference stage  10  can operate at a low voltage. The bias voltage of the cascode current mirror circuit is determined by a resistor R 100 , but this resistor that may be subject to different fabrication variations from the variations of the p-channel transistors. There is a risk that the resistance r 100  of resistor R 100  may become less than VDSsatp/I 1 , because of a combination of fabrication variations and the operating temperature, in which case the p-channel transistors in the first stage of the cascode current mirror circuit operate in the non-saturation region.  
         [0193]    In the bandgap reference voltage circuit in the fourth embodiment, however, the dimensions of transistor P 101  are set to make  
         VDSsatp 101 =VDSsatp 100 =VDSsatp 102   
         [0194]    in order to bring the voltage at the common gate of transistors P 104 , P 106 , and P 109  in the second current mirror stage to the voltage level Vcc−(Vtp+VDSsatp), so that the cascode current mirror circuit formed by the first stage comprising transistors P 100 , P 101 , P 102 , and P 108  and the second stage comprising transistors P 103 , P 104 , P 106 , and P 109  can operate at a low voltage. Because all of the circuit elements involved in this cascode current mirror are p-channel transistors, their electrical characteristics vary in the same way due to fabrication variations, so the risk of non-saturation operation of the p-channel transistors in the first stage of the cascode current mirror circuit is reduced. More specifically, because the load disposed in the cascode current mirror circuit of the constant-current circuit  11  to enable low-voltage operation is a p-channel MOS transistor load instead of a resistor load, relative variations among the circuit elements can be reduced, ensuring that the p-channel transistors in the first stage operate in the saturation region.  
       Variation of the Fourth Embodiment  
       [0195]    [0195]FIG. 14 is a circuit diagram of a bandgap reference voltage circuit illustrating a variation of the fourth embodiment. In comparison with the circuit in FIG. 13, the reference stage  10  and the power supply voltage detection circuit  21  in the start-up stage  20  have the same configuration, while the start-up output circuit  22  has a different configuration.  
         [0196]    The start-up output circuit  22  in FIG. 14 differs from the start-up output circuit  22  in FIG. 13 in having two n-channel start-up transistors N 114  and N 115 , instead of a single p-channel transistor start-up P 116 . Transistor N 114  has a gate coupled to node  122 , a source coupled to the low power supply Vss, and a drain coupled to node  119 , which is now a starter node in the constant-current circuit  11 . Transistor N 115  has a gate coupled to node  122 , a source coupled to the low power supply Vss, and a drain coupled to a node  115 , which is another starter node in the constant-current circuit  11 .  
         [0197]    In the fourth embodiment, the constant-current circuit  11  is started by pulling the common gate of n-channel transistors N 101  and N 104  up to the level of the high power supply Vcc until Vcc reaches the voltage level VDSsatp 111 +VDSsatn 111 +Vbe 110 +Vtp 112 .  
         [0198]    In the variation of the fourth embodiment, the constant-current circuit  11  is started by pulling the common gate of p-channel transistors P 104  and P 106  down to the level of the low power supply Vss. The common gate of transistors P 100  and P 102  is also pulled down to the Vss level. This forces the cascode current mirror circuit comprising p-channel transistors P 100 , P 102 , P 104 , and P 106  to operate in a way that quickly brings nodes  117  and  118  to the level necessary for n-channel transistors N 100 , N 101 , N 102 , and N 104  to turn on, so that the constant-current circuit  11  can start up. The variation of the fourth embodiment has substantially the same effects as the fourth embodiment itself.  
       Fifth Embodiment  
       [0199]    [0199]FIG. 15 is a circuit diagram of a bandgap reference voltage circuit illustrating a fifth embodiment of the invention, comprising a reference stage  10  that has the same configuration as in the third embodiment, and a start-up stage  20  that has the same configuration as in the second embodiment.  
         [0200]    Transistors P 111  and P 112 , transistor N 111 , and transistor Q 110  in the power supply voltage detection circuit  21  in FIG. 15 have the same specifications as transistors P 100  and P 104 , transistor N 100 , and transistor Q 100 , respectively, in the constant-current circuit  11 .  
         [0201]    The reference stage  10  in the fifth embodiment operates in the same way as the reference stage  10  in the third embodiment (see FIG. 9), employing a negative feedback loop. The start-up stage  20  in the fifth embodiment operates in the same way as in the second embodiment. During power-up, the gate of n-channel transistor N 104  in the constant-current circuit  11  is pulled up to the level of the high power supply Vcc until Vcc reaches the voltage level . VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 111 , which is equal to the VCC 1  value given by equation (3). This pull-up operation turns on transistor N 104 , then transistors P 100 -P 106 , then transistors N 100  and N 102 , thereby starting the constant-current circuit  11 . If the minimum high power supply voltage Vcc necessary for operation of the constant-current circuit  11  is the VCC 1  value, then after the pull-up operation by the start-up stage  20  ends, the constant-current circuit  11  can continue operating on its own. The voltage at the starter node  118  changes from the pulled-up level, which is at least the sum of the source voltage of transistors N 100  and N 102  and their threshold voltage Vtn, to a steady-state voltage, and is held steady by the negative feedback loop.  
         [0202]    In the bandgap reference voltage circuit of the fifth embodiment, the start-up stage  20  has the same effects as in the second embodiment, and the constant-current circuit  11  has the same effects as in the third embodiment.  
       First Variation of the Fifth Embodiment  
       [0203]    [0203]FIG. 16 is a circuit diagram of a bandgap reference voltage circuit illustrating a first variation of the fifth embodiment. In comparison with the circuit in FIG. 15, the reference stage  10  and the power supply voltage detection circuit  21  in the start-up stage  20  have the same configuration, while the start-up output circuit  22  has a different configuration. The start-up output circuit  22  has the same configuration as in the first variation of the second embodiment (see FIG. 6).  
         [0204]    In the fifth embodiment, to start the constant-current circuit  11 , the gate of n-channel transistor N 104  is pulled up to the high power supply Vcc until Vcc reaches the voltage level VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 111 .  
         [0205]    In the first variation of the fifth embodiment, the constant-current circuit  11  is started by pulling the common gate of p-channel transistors P 104  and P 106  down to the low power supply Vss. The common gate of transistors P 100  and P 102  is also pulled down to the low power supply Vss through resistor R 100 . By the time the pull-down operation ends, transistors N 100 , N 102 , and N 104  have turned on and the high power supply Vcc has reached the VCC 1  voltage level necessary for the cascode current mirror circuit comprising p-channel transistors P 100 , P 102 , P 104 , and P 106  to operate correctly. The first variation has substantially the same effects as the fifth embodiment.  
       Second Variation of the Fifth Embodiment  
       [0206]    [0206]FIG. 17 is a circuit diagram of a bandgap reference voltage circuit illustrating a second variation of the fifth embodiment. In comparison with the circuit in FIG. 15, the start-up output circuit  22  in the start-up stage  20  has the same configuration while the reference stage  10  and the power supply voltage detection circuit  21  have different configurations. The reference stage  10  in this second variation has the same configuration as in the second variation of the third embodiment (see FIG. 11), while the power supply voltage detection circuit  21  in this second variation has the same configuration as in the second variation of the second embodiment (see FIG. 7).  
         [0207]    Whereas the constant-current circuit  11  in the fifth embodiment had p-channel transistors connected in a cascode current mirror configuration, the second variation employs a simpler current mirror configuration.  
         [0208]    In the second variation of the third embodiment, during power-up, the start-up stage  20  keeps the gate voltage of n-channel transistor N 104  in the constant-current circuit  11  pulled up to the level of the high power supply Vcc until Vcc reaches the voltage level VDSsatp 111 +Vbe 110 +Vtn 111 . The constant-current circuit  11  starts up when the gate potential of transistor N 104  reaches a level sufficient for transistor N 104  to turn on.  
         [0209]    The second variation of the third embodiment is applicable if the bandgap reference voltage circuit is fabricated by a process such that (VDSsatp+Vtn)&gt;(VDSsatn+Vtp). The constant-current circuit  11  can then maintain constant-current operation if the high power supply Vcc is at least Vbe 100 +VDSsatp 100 +Vtn 100 . This is lower than the VCC 1  value given by equation (3), making the second variation of the third embodiment useful for low-voltage applications.  
       Third Variation of the Fifth Embodiment  
       [0210]    [0210]FIG. 18 is a circuit diagram of a bandgap reference voltage circuit illustrating a third variation of the fifth embodiment. The reference stage  10  and the power supply voltage detection circuit  21  of this circuit have the same configuration as in the second variation of the fifth embodiment, and the start-up output circuit  22  has the same configuration as in the first variation of the fifth embodiment.  
         [0211]    In the start-up stage  20  of the third variation of the fifth embodiment, during power-up, the common gate of p-channel transistors P 100  and P 102  is kept pulled down to the level of the low power supply Vss until the high power supply Vcc reaches the voltage level VDSsatp 111 +Vbe 110 +Vtn 111 . P-channel transistors P 100  and P 102  therefore turn on quickly, enabling the constant-current circuit  11  to start up. This third variation has substantially the same effects as the second variation.  
       Sixth Embodiment  
       [0212]    [0212]FIG. 19 is a circuit diagram of a bandgap reference voltage circuit illustrating a sixth embodiment of the invention, comprising a reference stage  10  that has the same configuration as in the fourth embodiment, and a start-up stage  20  that has the same configuration as in the second embodiment.  
         [0213]    Transistors P 111  and P 112 , transistor N 111 , and transistor Q 110  in the power supply voltage detection circuit  21  in FIG. 19 have the same specifications as transistors P 100  and P 104 , transistor N 100 , and transistor Q 100 , respectively, in the constant-current circuit  11 .  
         [0214]    The reference stage  10  in the sixth embodiment operates in the same way as the reference stage  10  in the fourth embodiment (see FIG. 13), employing a negative feedback loop. The start-up stage  20  in the sixth embodiment operates in the same way as the start-up stage  20  in the second embodiment (see FIG. 5). During power-up, the common gate of n-channel transistors N 101  and N 104  in the constant-current circuit  11  is pulled up to the level of the high power supply Vcc until Vcc reaches the voltage level VDSsatp 111 +VDSsatp 112 +Vbe 110 +Vtn 112 , which is equal to the VCC 1  value given by equation (3). This pull-up operation quickly turns on transistors N 101  and N 104 , enabling the constant-current circuit  11  to start up. If the minimum high power supply voltage Vcc necessary for operation of the constant-current circuit  11  is the VCC 1  value, then after the pull-up operation ends, the constant-current circuit  11  can continue operating on its own. The voltage at the starter node  118  changes from the pulled-up level, which is at least the sum of the source voltages of transistors N 100  and N 102  and the threshold voltage Vtn, to a steady-state voltage and is held steady by the negative feedback loop.  
         [0215]    In the bandgap reference voltage circuit of the sixth embodiment, the start-up stage  20  has the same effects as in the second embodiment, and the constant-current circuit  11  has the same effects as in the fourth embodiment.  
       Variation of the Sixth Embodiment  
       [0216]    [0216]FIG. 20 is a circuit diagram of a bandgap reference voltage circuit illustrating a variation of the sixth embodiment. In comparison with the circuit in FIG. 19, the reference stage  10  and the power supply voltage detection circuit  21  in the start-up stage  20  have the same configuration, while the start-up output circuit  22  has a different configuration. The start-up output circuit  22  has the same configuration as the start-up output circuit  22  in the first variation of the fourth embodiment (see FIG. 14).  
         [0217]    The start-up output circuit  22  in FIG. 20 differs from the start-up output circuit  22  in FIG. 19 in having two n-channel start-up transistors N 114  and N 115 , instead of a single p-channel start-up transistor P 116 . Transistor N 114  has a gate coupled to node  122 , a source coupled to the low power supply Vss, and a drain coupled to node  119 , which is now the starter node in the constant-current circuit  11 . Transistor N 115  has a gate coupled to node  122 , a source coupled to the low power supply Vss, and a drain coupled to a node  115 , which is another starter node in the constant-current circuit  11 .  
         [0218]    In the sixth embodiment, during power-up, the common gate of n-channel transistors N 101  and N 104  in the constant-current circuit  11  is pulled up to the level of the high power supply Vcc until the high power supply Vcc reaches the voltage level VDSsatp 111 +Vbe 110 +Vtn 111 , so that transistors N 101  and N 104  turn on quickly, enabling the constant-current circuit  11  to start up.  
         [0219]    In the variation of the sixth embodiment, during power-up, the common gate of p-channel transistors P 104  and P 106  is pulled down to the level of the low power supply Vss, and the common gate of transistors P 100  and P 102  is also pulled down to the Vss level. As a result, the cascode current mirror circuit comprising p-channel transistors P 100 , P 102 , P 104 , and P 106  operates in a way that quickly turns on n-channel transistors N 100 , N 101 , N 102 , and N 104 , starting up the constant-current circuit  11 . This variation has substantially the same effects as the sixth embodiment.  
         [0220]    In addition to the variations of the embodiments described above, those skilled in the art will recognize that further variations are possible within the scope of the appended claims.