Abstract:
There is provided a semiconductor device. The semiconductor device includes a lower electrode, a contact connected to the lower electrode to have a double trench structure, a phase change material layer accommodated in the double trench to cause a phase change between a crystalline state and an amorphous state in accordance with a change in heat transmitted by the contact, and an upper electrode connected to the phase change material layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device and a method of manufacturing the same. 
         [0003]    2. Description of the Related Art 
         [0004]    A phase change memory is a memory that uses a difference in resistance between materials in accordance with a phase change and is one of next generation memory semiconductors that has the advantage of a flash memory in which stored information is not erased although power is not supplied and the advantage of a dynamic random access memory (DRAM) in which stored data is erased when power is not supplied, however, processing speed is high. 
         [0005]    The phase change memory has an access time at least 1,000 times faster than that of the flash memory that is a representative non-volatile memory and can operate at a low voltage of no more than 2 to 5 V like the DRAM. 
         [0006]    Also, it is possible to read and write data fast in the phase change memory like in a static random access memory (SRAM). Since the phase change memory has a relatively simple cell structure, it is possible to reduce the size of a device to the size of a DRAM device. 
         [0007]    Also, since not a memory device using storage of charges but a difference in resistance between materials in accordance with a phase change is used, it is possible to write down and erase information no less than 10 10  times without being affected by cosmic radiation or electromagnetic wave. 
         [0008]      FIG. 1  is a sectional view illustrating the structure of a conventional phase change memory. 
         [0009]    As illustrated in  FIG. 1 , a phase change memory  10  includes a lower electrode  12 , a contact  14 , a phase change material layer  16 , and an upper electrode  18 . 
         [0010]    The temperature of the phase change material layer  16  is changed by the amount of current that flows in the contact  14 . In accordance with the change in temperature, the alignment of the atoms or molecules of the phase change material layer  16  is changed into an amorphous state having no regularity or a crystalline state having regularity to obtain 1 and 0 through the lower electrode  12  and the upper electrode  18 . The signal is 0 when the alignment is in the crystalline state and is 1 when the alignment is in the amorphous state. Information is processed while repeating the states. 
         [0011]    As illustrated in  FIG. 1 , in the conventional phase change memory  10 , since the contact  14  is connected to the phase change material layer  16  only through the top surface thereof, the heat generated by the contact resistance of the contact  14  is transmitted to the phase change material layer  16  based on the top surface of the contact  14  in the radiation direction (the arrow of  FIG. 1 ). 
         [0012]    Therefore, a program region  15  that functions as a memory is limited to a partial region as illustrated in  FIG. 1 , the amount of generation of heat is determined by the area of the top of the contact, the distribution of heat is not uniform all over the phase change material layer  16 , and heat transmission time is long. 
         [0013]    When heat distribution is not uniform and it takes a long time to transmit heat like the conventional phase change memory  10 , a switching time for which the phase change material layer  16  changes from an amorphous state to a crystalline state or from the crystalline state to the amorphous state increases so that the operation speed of a memory becomes low. 
       SUMMARY OF THE INVENTION 
       [0014]    The present invention has been made to solve the above problem occurring in the prior art, and therefore, it is an object of the present invention to provide a semiconductor device in which the heat generated by contact resistance is uniformly transmitted to a phase change material layer at high speed so that operation speed increases and a method of manufacturing the same. 
         [0015]    It is another object of the present invention to provide a semiconductor device capable of improving the heat transmission efficiency of a contact and a method of manufacturing the same. 
         [0016]    In order to achieve the above objects, a semiconductor device includes a lower electrode, a contact connected to the lower electrode to have a double trench structure, a phase change material layer accommodated in the double trench to cause a phase change between a crystalline state and an amorphous state in accordance with a change in heat transmitted by the contact, and an upper electrode connected to the phase change material layer. 
         [0017]    A method of manufacturing a semiconductor device includes the steps of forming a first protective layer on a lower electrode, selectively etching the first protective layer to form a double trench, applying a contact layer to fill the double trench and polishing the contact layer so that the contact layer is left only in the double trench, partially etching the polished contact layer to form a second trench, applying a phase change material to fill the second trench and polishing the phase change material so that the phase change material is left only in the second trench to form a phase change material layer, and forming an upper metal layer connected to the phase change material. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0018]      FIG. 1  is a sectional view illustrating the structure of a conventional phase change memory; 
           [0019]      FIGS. 2A and 2B  are a sectional view and a plan view illustrating the structure of a phase change memory according to the present invention; 
           [0020]      FIG. 3  is a sectional view illustrating the step of forming a double trench in a lower electrode in processes of manufacturing a phase change memory according to the present invention; 
           [0021]      FIG. 4  is a sectional view illustrating a state where a contact layer fills the double trench in the processes of manufacturing the phase change memory according to the present invention; 
           [0022]      FIG. 5  is a sectional view illustrating the step of forming a second trench in the contact layer in the processes of manufacturing the phase change memory according to the present invention; 
           [0023]      FIG. 6  is a sectional view illustrating a state where a phase change material layer is applied in the processes of manufacturing the phase change memory according to the present invention; 
           [0024]      FIG. 7  is a sectional view illustrating the step of planarizing a phase change material layer so that the phase change material layer is left only in a second trench in the processes of manufacturing the phase change memory according to the present invention; and 
           [0025]      FIG. 8  is a sectional view illustrating the step of applying a second protective layer and of forming a via in the processes of manufacturing the phase change memory according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    Embodiments of the present invention will be described with reference to the attached drawings. 
         [0027]      FIGS. 2A and 2B  are a sectional view and a plan view illustrating the structure of a phase change memory according to the present invention. 
         [0028]    As illustrated in  FIGS. 2A and 2B , a phase change memory  100  according to the present invention includes a lower electrode  120 , a contact  140 , a phase change material layer  160 , a connection via  170 , and an upper electrode  180 . 
         [0029]    The contact  140  is a double trench in which a double step difference is formed in a first protective layer  130  unlike the contact  14  of the conventional phase change memory  10 . Also, the phase change material layer  160  is accommodated in the double trench of the contact  140 . 
         [0030]    That is, the phase change material layer  160  contacts the four side surfaces of the contact as illustrated in the plan view of  FIG. 2B  and contacts the top surface of the contact as illustrated in the sectional view of  FIG. 2A . Therefore, the heat generated by the contact  140  is transmitted to the phase change material layer  160  through the top surface of the contact  140  (refer to the arrow A of  FIG. 2A ) and is transmitted to the phase change material layer  160  through the four side surfaces of the contact  140  (refer to the arrows B, C, D, and E of  FIG. 2B ). As described above, since the heat of the contact  140  is transmitted to the phase change material layer  160  through the five surfaces in the phase change memory  100 , the heat generated due to the contact resistance is uniformly and fast transmitted to the phase change material layer  160 . 
         [0031]    In the phase change memory  100 , the connection via  170  is formed in the second protective layer  160  to connect the phase change material layer  160  and the upper electrode  180  to each other. 
         [0032]    The lower electrode  120  and the upper electrode  180  can be made of an alloy of Ti, Ni, W, Cu, and N and polycrystalline silicon. The first protective layer  130  and a second protective layer  150  are, for example, ZnS—SiO 2 . The contact  140  is formed of an electric conductive material having high heat transmission and no less than a predetermined value of sheet resistance. 
         [0033]    The phase change material  160  is formed of a Chalcogenide material thin film such as Ge—Sb—Te based nucleation dominant material (NDM) (for example, Ge 2 Sb 2 Te 5 ) and Sb 70 Te 30  based fast growth material (FGM). 
         [0034]    For the phase change material layer  160  to store information in an amorphous state, heat is electrically applied or light is radiated to the phase change material layer  160  and the phase change material layer  160  is rapidly cooled. For the phase change material layer  160  to erase the stored information in a crystalline state, heat of temperature slightly higher than crystal temperature must be applied for a predetermined time required for causing a phase change. 
         [0035]    In general, the temperature of the GeSbTe phase change material is about 600° C. when information is stored and is about no less than 179° C. when information is erased. When the phase change material layer  160  is in the crystalline state, electric resistance is small so that current can flow. However, when the phase change material layer  160  is cooled after the heat caused by the contact resistance with respect to the contact  140  is applied, the phase change material layer  160  is in the amorphous state, resistance increases so that current is intercepted. 
         [0036]    The method of manufacturing the phase change memory  100  according to the present invention will be described with reference to  FIGS. 3 to 8 . 
         [0037]    Referring to  FIG. 3 , the first protective layer  130  is applied on the lower electrode  120  to form a double trench  142 . Polycrystalline silicon or metal is applied on a substrate (not shown) by a chemical vapor deposition (CVD) method to form the lower electrode  120 . When the lower electrode  120  is formed by the polycrystalline silicon, an ion implantation process for controlling the electric resistance must be performed. The double trench  142  can be formed by performing a photolithography process twice or a dual damascene process. 
         [0038]    Referring to  FIG. 4 , a contact layer  145  is applied to fill the double trench  142  and is polished so that the contact layer  145  exists only in the double trench  142  and that the top surface of the contact layer  145  coincides with the top surface of the first protective layer  130 . In the polishing process, a chemical mechanical polishing (CMP) method can be used. 
         [0039]    Then, as illustrated in  FIG. 5 , the contact layer is selectively etched by a photolithography process to form a contact layer pattern  145   a  having a second trench  147 . The second trench  147  is positioned in the center of the double trench  142  of the contact. 
         [0040]    Referring to  FIG. 6 , a phase change material  162  is applied to fill the second trench  147  of the contact layer pattern  145   a.  As illustrated in  FIG. 7 , the phase change material  162  is planarized by the CMP process so that the phase change material is left only in the second trench  147  to form the phase change material layer  160 . As illustrated in  FIGS. 6 and 7 , the second trench  147  contacts all of the surfaces of the phase change material layer excluding the surface on which the phase change material layer  160  is connected to the upper electrode or the connection via  170 . 
         [0041]    Then, as illustrated in  FIG. 8 , the second protective layer  150  is applied and a hole is formed to open the phase change material layer  160  so that the hole is filled with electric conductor to form the connection via  170 . Then, when an upper metal layer  180  connected to the phase change material layer  160  is formed through the connection via  170 , the phase change memory  100  illustrated in  FIG. 2A  is completed. 
         [0042]    In the phase change memory according to the present invention, since the phase change material layer contacts the contact on the four side surfaces and contacts the top surface of the contact, the heat generated by the contact is uniformly and fast transmitted to the entire phase change material layer. 
         [0043]    Also, in the phase change memory according to the present invention, heat distribution is uniform and heat is transmitted fast so that the switching time for which the phase change material layer changes from the amorphous state to the crystalline state and from the crystalline state to the amorphous state is reduced and that the operation speed of the memory increases. 
         [0044]    While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.