Abstract:
A power supply consumes mains power and has first outputs which produce an operational voltage for controlling a CPU and a primary link interface. The primary link interface is capable of sending a mains fail message through the primary link using only power from one of the first outputs. The power supply also produces second outputs for powering circuitry not related to the transmission of this power fail message. The power supply detects loss of mains power and signals this by pulling the second outputs to a signal voltage which may be near ground. The equipment powered by this supply detects the second output changing from an operational voltage to a signaling voltage, and sends this information to the CPU, which sends a power fail message across the primary link interface.

Description:
FIELD OF THE INVENTION 
     This invention relates to an apparatus and method for signaling the detection of mains power loss by locally powered equipment which has a communications link established with central equipment having backup battery power. Such detection of loss of mains power is often used to trigger housekeeping operations in a processor, whereby the processor shuts down in an orderly manner after the loss of mains power. This housekeeping may include the transmission of a power fail message to remote equipment prior to the loss of the mains-derived voltage which operates the processor. 
     BACKGROUND OF THE INVENTION 
     Communications equipment is often sensitive to the loss of mains power. In some systems, either a standby source of mains power is provided, or a method of detecting the loss of mains power is employed in conjunction with an energy storage element which provides enough energy for the powered equipment to complete any tasks that must be finished before the energy storage element is depleted. 
     One class of system extensively discussed in the prior art is one which senses a power fail event, and communicates this to a processor or system. U.S. Pat. No. 4,509,201 by Sekigawa et al discloses a voltage monitor coupled to a battery which signals when the battery has reduced operating level, thereby producing a signal to a CPU. U.S. Pat. No. 4,509,874 by Shimamoto et al. includes a variable A/D converter which measures the output voltage of two batteries and an AC/DC converter for use by a CPU. U.S. Pat. No. 5,831,805 by Sekine discloses a power failure detection subsystem for determining the loss of power and sending this information to a CPU. 
     A second class of system uses this loss of power signal to start a process related to saving information from a pre-existing process. U.S. Pat. No. 5,283,792 by Davies et al, U.S. Pat. No. 5,339,446 by Yamasaki et al, and U.S. Pat. No. 5,423,045 by Kannan et al. disclose the storage of CPU data and instructions upon the detection of power failure or imminent loss of power. 
     A third class of system uses a local capacitor to store sufficient charge to enable a system to operate on the content of this charge alone. U.S. Pat. No. 5,553,138 by Heald et al discloses a CPU which derives its power from a telephone hook voltage, and senses when the level of voltage on this storage capacitor is diminished, thereby producing a signal. 
     SUMMARY OF THE INVENTION 
     A power supply furnishes a plurality of voltages used as the power sources for various parts of a communication system. A CPU and a primary physical layer interface are powered using a first output voltage which persists for a holdup time after the loss of mains power. The remaining power supply secondary voltages are used for secondary physical layer interfaces, and other functions not related to the operation of either the primary physical interface, or the operation of the CPU. These secondary voltages have two values: an operating voltage related to the operation of the associated loads, and a signaling voltage for the communication of the detected AC mains power failure. When the power supply detects the loss of mains voltage, one or more of these power supply output secondary voltages is quickly pulled to this signaling voltage after the loss of mains power. A set of comparators examines one or more of the secondary power supply voltages, and these comparators generate an interrupt to the CPU if one or more of the other voltages is near the signaling voltage. In response to this detected signaling voltage, the CPU sends a special “power fail” message across the primary communications link to indicate to the remote device on this link that the provision of mains power has been terminated. In this manner, the remote device can distinguish between the loss of power to the remote device, and the loss of link through a bad interface, or a bad physical link. 
     OBJECTS OF THE INVENTION 
     A first object of the invention is the detection and communication of a mains power failure event in equipment that is powered by a plurality of power supply voltages. A second object of the invention is the use of one or more power supply first output voltages for powering equipment required for sending messages on a primary communications link, and the use of one or more power supply secondary output voltages for both the operation of secondary loads, as well as the signaling of loss of power information. A third object of the invention is the provision of power to a power fail messaging circuit for a holdup time that permits the sending of a power fail message after the detection of loss of power. A fourth object of the invention is the use of series signalers and comparators to send and receive power fail signals. A fifth object of the invention is the use shunt signalers and comparators to send and receive power fail signals. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is the block diagram for a prior art communication system including a power fail signal. 
     FIG. 2 is the block diagram for the present invention comprising a power supply, powered equipment, and communication links to remote equipment. 
     FIG. 3 shows the waveforms for the mains failure signaling circus. 
     FIG. 4 a  is the schematic diagram for a shunt signaler. 
     FIG. 4 b  is the schematic diagram for a series signaler. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a prior art power source  10  having a plurality of output voltages V 1   12   a , V 2   12   b , and V 3   12   c , as well as a common ground  12   g . A power fail signal  14  is also furnished, which is used to indicate the loss of mains power before the actual loss of output voltages occurs. The output voltages  12   a-c  and power fail signal  14  are provided to a communications device  16 , which may have a plurality of communications interfaces such as a DSL (Digital Subscriber Link)  20 , and an FXS (Full Exchange-Subscriber) interface  26  connected to a link  22 . An FXS interface provides the electrical and functional behavior of a central office to a standard telephone, including the application of the ringing voltage of 71V, and the handset voltage of 24V. In a prior art system, when there is loss of mains power, the power fail signal  14  is asserted to the CPU  18 , which may form a “power fail” message and send this over CPU interface  19  to the DSL physical layer controller chip  24 . Thereafter, this “power fail,” message is sent to the device on the remote end of link  20 . The interval between loss of mains power and the sending of this “power fail” message determines the “holdup” time of the AC/DC converter  11 , which is the amount of time the supply must continue delivering a specified voltage after the removal of mains power. During this holdup time, all of the other outputs  12   b  and  12   c  are also furnishing current to their respective load  26 , even though these outputs are not essential to the communication of the power fail message. Also, the communication of a power fail message requires an additional pin and wire to transport this signal  14  from the power supply  10  to the powered equipment  16 . 
     FIG. 2 shows the present invention. A power supply  36  comprises an AC/DC converter  34  which produces a power fail signal  31  and a plurality of output voltages V 1   38   a , V 2   38   b , V 3   38   c , and a common ground  38   g , as before. Any voltage which is not used in the generation or transmission of the “power fail” message over the communication link is passed through signalers  40   b  and  40   c . The signalers are controlled by the power fail signal  31  such that the secondary output voltages V 2 ′  38   b ′ and V 3 ′  38   c ′ are either disconnected from the active outputs  38   b  and  38   c  and discharged to ground, or are referenced to a signaling voltage such as ground. During this time, first output V 1   38   a  maintains its output voltage. The advantage of signaling in this manner is clear to one skilled in the art of the design of switching power supplies. In a switching power supply, the mains voltage is rectified and stored in a central capacitor. The energy stored in a capacitor is ½(CV 2 ), and the rectified mains voltage is in excess of 150V. This is often the highest voltage typically found in the switching power supply, and this capacitor has a greater storage capacity than one placed for example at the output V 1   38   a , where the voltage is typically 3-5V. Prior art systems with a low voltage capacitor on V 1  often place this capacitor in the powered equipment  49 , whereas the optimal location for the high voltage capacitor is in AC/DC converter  34 . The use of a central capacitor combined with a signaler for the outputs  38   b , and  38   c  ′ which isolates these loads has the effect to extending the holdup time of V 1   38   a . This provides a longer holdup time over either the alternative of placing a large capacitor at first output V 1   38   a , or allowing a central capacitor to operate the switching supply which is feeding secondary outputs V 2 ′  38   b ′ and V 3 ′  38   c ′. The first output voltage  38   a  drives a load comprising a CPU  54  and a primary communications interface such as a DSL interface  56 , both of which are powered by the voltage V 1   38   a , and require no other voltage for operation. The primary communication interface is shown as a DSL interface  56  which includes a link  74  to remote equipment  82 , and this primary link is used for the transmission of IP and other protocols transporting data, as well as the transmission of a “power fail” message upon loss of power. The telephone FXS (or FXO) interface  58  consumes secondary voltages V 2 ′  38   b ′ and V 3 ′  38   c ′, which are typically −24VDC for the telephone line bias, and −71 VDC for a ringing voltage, as is well known to one skilled in telephone art. Following a loss of power, secondary voltages V 2   38   b  and V 3   38   c  produce signaling voltages using signalers  40   b  and  40   c  respectively, causing voltages V 2 ′  38   b ′ and V 3 ′  38   c ′ to fall from their operational level to the signaling level. This is detected by comparators  48   a  and  48   b , which provide outputs to OR gate  50 , which asserts output  52  whenever either V 2 ′  38   b ′ or V 3 ′  38   c ′ fall to the signaling level established by threshold level Vref  78 . The assertion of power loss signal  52  causes the CPU  54  to generate a “power fail” message, send this message across link  80  to DSL interface  56 , and out link  74  to the remote equipment  82 . The remote equipment then marks the link end equipment  49  as powered down, rather than failed. The outputs of comparators  48   a  and  48   b  are logic state 0 when V 2 ′ and V 3 ′ are the operational voltage and logic state 1 when V 2 ′ and V 3 ′ are the signaling voltage. 
     FIG. 3 shows the voltages of the block diagram of FIG.  2 . AC Mains voltage  90  is shown at nominal AC line voltage until point  102 , when the AC mains are shown to fail. Until this time, V 1   92 , V 2 ′  94 , V 3 ′  96  corresponding to respective nodes  38   a ,  38   b , and  38   c  of FIG. 2 are all operational voltages of ±5V, −24V, and −71V respectively. At time  98 , the secondary voltages V 2 ′  94  and V 3 ′  96  are isolated by signalers  40   b  and  40   c , and thereafter fall to 0V as shown. The loss of these voltages is sensed by signal  52  of FIG. 2, shown as PWR_FAIL_INT waveform  96 . The power converter continues to deliver first output voltage V 1  during the holdup interval Th  104 , which is a sufficient period of time for the CPU to receive the interrupt signal PWR_FAIL_INT  52  shown as waveform  96 , generate a “power fail” message, transfer it over CPU bus  80 , and send the message through DSL interface  56  through link  74  to remote equipment  82 . The holdup interval Th  104  is chosen to enable this “power fail” message transmission to occur as described above, and a typical value for this holdup interval is 50 ms. 
     FIG. 4 a  shows the signaler  40   b  or  40   c  implemented as a shunt device. Signaler  40   b  is shown as shunt signaler  90  performing as  40   b  or  40   c  of FIG. 2, comprising a low value resistor  92  which does not interfere with the provision of voltage to the secondary loads as was described earlier. When a power fail event occurs, PWR_FAIL signal  31  is asserted as before, causing shunt switch  94  to reference V 2 ′  38   b ′ to ground. The duration of this assertion may be kept to a minimum, thereby reducing the power consumed by shunt switch  94 . 
     FIG. 4 b  shows a series signaler  96  operating as signaler  40   b  or  40   c . The series signaler  96  comprises a series switch  98  which becomes an electrical open upon the assertion of PWR_FAIL input  31 . If required, shunt resistor  100  my be placed in parallel with the load to ensure the secondary output  38   b ′ drops to the signaling level quickly. When PWR_FAIL input  31  is not asserted, switch  98  is closed, and output  38   b ′ is at the operational output voltage. 
     As is clear to one skilled in the art, there are many different ways to practice the invention described in this letters patent. The AC to DC converter  34  may have a plurality of first outputs, or a plurality of secondary outputs, and the present invention only requires only that the first outputs be operational to each element responsible for the generation and transmission of the “mains failure” message for the duration required to form and transmit this message. One or more of the secondary voltage outputs is required to change to a signaling level to communicate the loss of power to the circuitry powered by the first outputs. One or more first voltages may be present, and one or more secondary voltages may be present without loss of generality, and these secondary voltages may power communications links, peripheral equipment, or any other function not related to the transmission of the “mains failure” message. While a level near 0V is shown for the messaging level used by the signalers, any such level which is unique from the operational voltage level could be used without loss of generality. Similarly, the signalers shown in FIGS. 4 a  and  4   b  are shown for example only, and could be made many different ways, as could the detector  46  of FIG.  2 .