Abstract:
In accordance with the present invention, the degree of timing misalignment between the data and clock paths in a RZ (return-to-zero) transmitter can be determined by converting a fraction of the optical output into the electrical domain with an ultra fast non-linear device, thereby squaring the optical peak power to provide a signal for controlling a phase change in the carrier. Using the same invention, the degree of timing misalignment between incoming optical pulses and an electronic signal fed to a modulator for demultiplexing can also be monitored and controlled in an optical time-division demultiplexing (OTDD) receiver.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to synchronization of an optical pulse stream and an electrical signal, such as data in a return-to-zero (RZ) optical transmission system or a simple digital sequence in an optical time-division demultiplexing (OTDD) receiver.  
         BACKGROUND TO THE INVENTION  
         [0002]    The return-to-zero RZ format is generated in two stages as shown in FIG. 1. In one stage, a carrier is generated by a continuous wave (CW) laser  10  and a pulse generator  20 . The carrier consists of a stream of optical pulses shorter than a bit slot and is produced using a clock signal. In another stage, a physical variable is modulated using a data modulator  30  to encode the data on the optical carrier. In all return-to-zero optical transmitters, including optical time domain multiplexing (OTDM) transmitters, the degree of misalignment between the data and clock paths varies with temperature and aging. With increasing bit rates and decreasing bit time slots, the timing variations can severely limit the transmitter performance.  
           [0003]    In an optical time-division demultiplexing (OTDD) receiver, a similar timing problem occurs as shown in FIG. 2. A series of optical pulses (data) at a very high data rate arrives at a receiver  35 . A splitter is used to generate two (or more) copies of the incoming optical pulse stream. Assuming a 1 to 2 splitting, two modulators  40 ,  50 , generating simple 101010 sequences from a clock signal at half the data rate are used to isolate even and odd bits for detection width slower electronics. Again, the electronic signals  80  that feed the modulators must be synchronized with the incoming pulse stream.  
           [0004]    Several prior art techniques have been tried to overcome this problem in RZ transmitters. One approach consists of minimizing the misalignment at the start of life of the transmitter, and permanently fixing the delay between the clock and data paths. This scheme is currently used in submarine RZ optical systems. However, timing budgets indicate that this set-and-forget approach becomes impractical for higher bit rates—for example, in ten gigabits per second RZ transmitters—as timing misalignments due to temperature variations and aging occupy a larger portion of the bit slot, severely degrading the transmitter performance.  
           [0005]    Another approach involves temperature monitoring. In principle, the effects due to temperature variations could be partially compensated by calibrating at start of life the required delay for the operating temperature range, and measuring the temperature during the normal operation. However, this scheme would not provide any compensation for the effects of aging.  
           [0006]    A third scheme involves measuring the average optical power using a photodetector. However, investigations have indicated that this approach cannot provide an accurate measurement of misalignment, especially for non-50% duty cycle data modulation.  
           [0007]    A further proposal is to build into the optical transmitter an on-board receiver. Such a receiver could be built onto the transmitter board to measure the misalignment. While this solution should provide excellent performance, it is not desirable due to its complexity, high cost and high amount of space occupied by the receiver.  
         SUMMARY OF THE INVENTION  
         [0008]    This invention provides means to synchronize the optical pulse stream (clock path) with the electrical data signal (data path). The present invention solves the alignment problem by providing a means to monitor and minimize the degree of misalignment in a control loop architecture.  
           [0009]    In accordance with the present invention, the degree of timing misalignment between the data and clock paths in a RZ (return-to-zero) transmitter or in an OTDD receiver can be determined by converting a fraction of the optical output into the electrical domain with an ultrafast non-linear device, which provides a signal for controlling a phase change in the carrier. While the use of non-linear devices that provide an output proportional to the square of the input will be discussed in this application, other non-linear devices could also be used.  
           [0010]    In a first aspect the present invention provides a method of synchronizing an optical pulse stream with an electrical data gate. This method comprises converting a fraction of said optical pulse stream to an electrical signal, measuring the average peak power of the electrical signal, and adjusting the phase of the optical pulse stream to maximize the average peak power of said electrical signal.  
           [0011]    In a second aspect the present invention provides a system for synchronizing the phase of an optical output pulse stream with a data stream modulating the pulse stream. The system comprises a pulse generator means to generate a pulse, optical modulator means for modulating the output pulse stream with the pulse generator means receiving an optical signal, optical tap means for tapping and diverting a portion of the output pulse stream, transformer means for transforming the portion of the output pulse stream into an electrical signal, power detection means to detect a average power of said electrical signal, phase adjust means for adjusting a phase of said output pulse stream generated by said pulse generator means, and control means for controlling said phase adjust means based on an average peak power detected by said power detection means. The pulse generator means produces the output pulse stream while the optical modulator receives the output pulse stream and the transformer means receives the portion of the pulse stream. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0012]    A better understanding of the invention may be obtained by reading the detailed description of the invention below, in conjunction with the following drawings, in which:  
         [0013]    [0013]FIG. 1 is a block diagram of a return to zero transmitter according to the prior art;  
         [0014]    [0014]FIG. 2 is a block diagram of an optical time division demultiplexing (OTDD) receiver according to the prior art;  
         [0015]    [0015]FIG. 3 illustrates the best case scenario for synchronization between an optical pulse stream and an electrical data gate for long data gate rise and fall times;  
         [0016]    [0016]FIG. 4 illustrates the worst case scenario for synchronization between an optical pulse stream and an electrical data gate for long data gate rise and fall times;  
         [0017]    [0017]FIG. 5 illustrates the best care scenario for synchronization between an optical pulse stream and an electrical data gate for short data gate rise and fall times;  
         [0018]    [0018]FIG. 6 illustrate the worst case scenario for synchronization between an optical pulse stream and an electrical data gate for short data gate rise and fall times;  
         [0019]    [0019]FIG. 7 is a block diagram of the synchronization system according to an embodiment of the invention;  
         [0020]    [0020]FIG. 8 illustrates the relationship between the signals V pulse  and V pulse  as used in an embodiment of the invention;  
         [0021]    [0021]FIG. 9 is a flowchart detailing the steps executed by the microcontroller illustrated in FIG. 7; and  
         [0022]    [0022]FIG. 10 illustrates error signal generation in the presence of dithering as used in one embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0023]    The idea behind the invention can be understood from a limitation of a simple optical average power measurement in the case of a 50% duty cycle and data gates having relatively long rise and fall times. For perfect synchronization between the optical pulse and the electrical data, each bit slot includes one pulse (see FIG. 3). In the worst-case of loss of synchronization, each bit slot is populated by two pulses located at the bit edges (see FIG. 4). Since these pulses overlap with the gate near its 50% value, the average power inside each bit slot is about the same as in the ideal synchronization case, thus failing to give an indicator as to the lack of synchronization. However, peak power is about 50% lower since the number of pulses inside each bit slot is doubled for the worst-case synchronization error.  
         [0024]    Squaring the Optical Power  
         [0025]    A signal proportional to optical peak power can be obtained by squaring the optical power before taking the average. As an example, consider a Gaussian pulse shape given by  
       y   =     A                   exp        (         -   4          ln        (   2   )              (     x   -     x   0       )     2         σ     fw                 h                 m     2       )                               
 
         [0026]    The average optical power is given by  
         y   ave     =       ∫     -   ∞     ∞          A                   exp        (         -   4          ln        (   2   )              (     x   -     x   0       )     2         σ     fw                 h                 m     2       )               x                               
 
         [0027]    The average of the square of the optical power is  
             (     y   2     )     ave     =         ∫     -   ∞     ∞              (     A                   exp        (         -   4          ln        (   2   )              (     x   -     x   0       )     2         σ     fw                 h                 m     2       )         )     2             x         =         ∫     -   ∞     ∞            (       A   2                     exp        (         -   8          ln        (   2   )              (     x   -     x   0       )     2         σ     fw                 h                 m     2       )         )             x            ∫     -   ∞     ∞            exp        (       -   a                     x   2       )               x             =       π   a             ,                         
 
         [0028]    Since  
         [0029]    We can write  
           (     y   2     )     ave     =         A     2              ∫     -   ∞     ∞            (     A                   exp        (         -   4          ln        (   2   )              (     x   -     x   0       )     2         σ     fw                 h                 m     2       )         )             x           =       A     2            y     a                 v                 e                                 
 
         [0030]    Therefore, averaging the square of the optical power gives a signal proportional to the product of the peak optical power (A) and the average optical power (y ave ). In the case where the average optical power can be considered a constant, we obtain the desired linear relationship between square of the optical power and peak optical power. This conclusion is valid for other pulse shapes, but the proportionality factor differs slightly. As an example it is about 0.7 for a Gaussian pulse shape, but it is closer to 0.63 for a hyperbolic secant. The effect of squaring can be seen in FIG. 3. For the sake of simplicity, we assume that  
         [0031]    1) the pulses have an optical peak power of 1 (arbitrary units),  
         [0032]    2) the data gates have no insertion losses at their maximum throughput and  
         [0033]    3) the data sequence is a simple series of 101010 . . .  
         [0034]    In the best-case synchronization, a single pulse is present in the bit slot, and squaring the optical power produces an output of 1 2 =1. For the worst-case synchronization (FIG. 4), two pulses are present in the bit, and squaring the optical power generates an output approximately equal to (½) 2+ ( ½)   2 =0.5, in agreement with the simple peak power prediction.  
         [0035]    Low-pass Filtering  
         [0036]    A limitation of the simple squaring approach can be observed in the case of very short rise and fall times, as shown in FIG. 5. In this case, peak optical power is almost independent of synchronization, as variations in pulse widths balance out the variation in the effective number of pulses per bit slot. Instead of decreasing the peak power of each pulses in the worst-case synchronization (FIG. 6), the gate merely cuts the pulse in two half-pulses, maintaining their peak power. In this case, a perfect squaring scheme would generate an output approximately equal to (½) 2   +( ½)(1) 2 =1 for the worst-case synchronization, the value also predicted for the best-case synchronization.  
         [0037]    This limitation for the very short rise and fall times can be corrected by appropriate low-pass filtering. In the worst-case synchronization (FIG. 6), the generated pulses will have a highly asymmetric shape, indicating a larger energy content in the high frequencies than for the best-case synchronization. Removing the high-frequencies before squaring will lead to a smaller output for the worst-case synchronization case and therefore restores an error signal. Using low-pass filtering for long rise and fall times is also beneficial as it enhances discrimination between best-case and worst-case synchronization.  
         [0038]    High-pass Filtering  
         [0039]    Coupled with low-pass filtering, the simple squaring approach produces strong error signals for data sequences consisting of single 1s. However, for actual data sequences that include long sequences of 1s, the difference in the squaring device output between best-case and worst-case synchronization becomes smaller, since only pulses near the gate ends contribute to the signal. This problem can be solved using a simple high-pass filter that removes the low-frequency content and hence lowers the contribution from the long series of 1s.  
         [0040]    Besides improving the relative signal strength, the high-pass filtering provides a much better accuracy, especially for duty cycles larger than 50%. Without filtering, the squaring approach, which is proportional to the peak power and average power, can be dominated for large duty cycles by the average power variation with synchronization. With high-pass filtering, the peak power component dominates and the squaring approach yields an accurate signal for synchronization.  
         [0041]    Implementing the squaring function could, in principle, be done in the optical domain using a nonlinear waveguide, such as surface-emitting second-harmonic generation waveguides. However, the current low efficiency of these devices would require an optical amplifier for practical applications.  
         [0042]    Squaring the optical output in the electrical domain using a fast photodetector and fast electronics should provide a more accurate error signal, as proper low-pass and high-pass filtering can be implemented between the fast detector and the electrical squaring device. In one aspect, a fast photodetector, such as a PIN photodiode and a trans-impedance amplifier followed by amplification feeds a signal to an electrical power detector such as a microwave diode detector, which behaves according to the square law and, therefore, provides the necessary non-linear function. For low RF powers, coaxial GaAs microwave detectors that have flat frequency responses up to 50 GHz are commercially available. They operate according to a square law for power up to −10 dBm with a sensitivity larger than 0.4 mV/μW. Use of such a device allows optimum alignment to be detected when the electrical power reaches its maximum value. As previously mentioned, electrical filtering between the PIN photodiode and the electrical power detector can be used for enhanced accuracy of the misalignment measurement. Once the degree of misalignment has been measured, it can be minimized by adjusting a variable phase delay block.  
         [0043]    A further enhancement of the approach consists in applying a small dither to the relative phase between the optical pulse stream and the data gates and measuring a signal at the dither frequency using a phase-sensitive lock-in technique. This technique enhances the signal-to-noise ratio by effectively filtering out the noise occurring outside of the dither bandwidth. Without dither, the optimum synchronization occurs at the RF power maximum. In the presence of dither, the error-signal generated corresponds to the derivative of the RF power, which provides the additional benefit of locking to a zero value.  
         [0044]    An embodiment of the invention is illustrated in the block diagram of FIG. 7.  
         [0045]    Optical pulses are generated using a CW (continuous wave) laser source  90  and an optical pulse generator  100 . The pulse generator is clocked by an electrical clock driver  110  whose phase can be adjusted via the electrical phase adjust  120 . The V phase  signal  130  is adjusted continually using a Microcontroller  140  in order that any short term and long term drift between the electrical data and optical pulse stream can be compensated. The Microcontroller writes the V phase  signal  130  into a DAC  150  which feeds the electrical phase adjust  120 . More details on the firmware software are given below. The optical modulator  160  is gated by the electrical data driver signal  170  from the electrical data driver  180  and thereby generates the optical data stream, Data optical    190 . An optical coupler  200  is used to tap off a small portion of the transmit power which is required for the power detection. The optical, tapped transmit signal is transformed back into the electrical domain using a photodetector  210 . In this implementation, a dedicated lowpass filter is not shown since sufficient lowpass filtering is obtained from the photodetector&#39;s inherent lowpass frequency filtering. However, depending upon the frequency response of the photodetector, a dedicated lowpass filter can be utilized if required. The output signal from the photodetector is then highpass filtered using High pass filter  220  and sent to the power detector block  230 , which outputs a raw detected power given by V detect,raw    240 . Appropriate bandpass filtering is performed by the dither bandpass filter  250  in order to filter out noise so as to increase sensitivity at the input to the ADC block  260 . The filtered V detect,raw  signal is termed V detect    270 . The Microcontroller  140  reads in the ADC output and performs its firmware routine in order to optimize the V phase,DC  setting.  
         [0046]    The Microcontroller generates an input signal, V phase    130 , to the electrical Phase Adjust block  120  which is composed of a DC component, V phase,Dc  and an AC component, V dither . The resultant V phase  signal may be considered as the V phase,DC  component effectively being amplitude modulated by the dither signal (ie. V phase =V phase,DC +V dither ) as shown in FIG. 8. The dither signal could be a single tone having a frequency in the kHz to MHz range or a pseudo-random bit stream (PRBS) sequence in the kbit/s to Mbit/s range. The method used by the microcontroller  140  is independent of the frequency or data rate of the dither but its selection should be chosen so as to minimize any negative impact to the overall fiber optic link performance, which will not be discussed within this invention.  
         [0047]    The method to center the optical pulses, Cloch optical    280 , and the electrical gating signal, Data Electrical , is illustrated in flowchart of FIG. 9. The Microcontroller applies an initial V phase  signal to the Electrical Phase Adjust block  120  (step  280 ). The V phase  signal is composed of a DC component and a dither component. After a portion of the main optical transmit signal  190  has been coupled off and converted back into the electrical domain using the photodetector, a power detection is performed on it which yields the receive signal termed V detect,raw . This raw detected signal undergoes appropriate bandpass filtering in order to obtain a signal in the applied dither frequency range. This filtered dither signal is called V detect  and is received by the microcontroller (step  290 ). The microcontroller then multiplies the reference signal, V dither  with the received V detect  signal in order to generate an error signal V error , whose value is given by: 
           V   error   =V   dither   ×V   detect (step  300 ). 
         [0048]    The sign of the error signal, V error , is then used to increment or decrement the level of the V phase,DC  signal so that the phase adjustor can be steered in the direction of optimal optical pulse to electrical data gate alignment. Step  310  is that of determining the sign of the error signal. If the error signal is positive, the V phase,DC  signal is decreased (step  320 ). If the error signal is negative, the V phase,DC  signal is increased (step  330 ). The case outlined in FIG. 9 assumes a power detector of positive polarity. If a power detector of negative polarity were utilized then the decision would be to decrease V phase,DC  instead of increasing it for V error &gt;0. As the method approaches the optimal phase setting, the magnitude of the V error  signal becomes progressively smaller. A point can be reached at which the method will not be able to optimize any further due to other limitations such as receive noise, ADC resolution and phase adjustor precision.  
         [0049]    A specific case of this is shown in FIG. 10. When V phase,DC  is situated to the left of the optimum setting, V phase,DC opt , as is the case for V phase,DC1 , then the generated error signal, V error1 , is greater than zero. This positive V error  causes the Microcontroller to increase V phase,DC , thereby steering the optical pulse phase towards the optimal setting V phase,DCopt . When V phase,DC  is situated to the right of the optimum setting, as is the case for V phase,DC2 , then the generated error signal, V errror2 , is less than zero. This negative V error  value causes the Microcontroller to decreases V phase,DC , thereby again steering the optical phase towards the optimal setting.  
         [0050]    It should be noted that the apparatus and the method described above can be used for applications other than return to zero transmitters. Any applications or devices which require synchronization between an optical pulse stream and an electrical data stream, usually acting as a data gate, can use the above system. One possible application, described in a preceding section, and shown in FIG. 2, is in OTDD receivers. The synchronization between the data modulators and the optical data can be affected and optimized by the above system. In this application, the data modulator (2 modulators in the example illustrated in FIG. 2) can be used to suppress specific bits in the optical data stream.  
         [0051]    Another possible application of the above system involves simply monitoring the peak power of an optical pulse stream in a system where the average power is time independent, such as in amplified optical systems.  
         [0052]    It should be reiterated that, while current technology makes it more desirable to apply the squaring (or other non linear function) to a portion of the pulse stream converted into an electrical signal, the conversion to an electrical signal is not inherently necessary. The portion of the pulse stream diverted from the main stream may have the nonlinear function directly applied to it. The optical output of this nonlinear function can be used for the same ends as the electrical output of the nonlinear function as described above.  
         [0053]    A person understanding the above-described invention may now conceive of alternative designs, using the principles described herein. All such designs which fall within the scope of the claims appended hereto are considered to be part of the present invention.