Abstract:
Conventional multistage amplifiers oftentimes employ trim circuits or highly matched components to combat noise and offset contributions. Having trim circuitry or highly matched components increases the overall size, cost, and power consumption, so it is desirable to have a circuit that reduces any need for better matching components or trim circuitry. Here, a multistage amplifier system is provided that generally accounts for some noise and offset contributions, reducing the need for better matching components and/or trim circuitry.

Description:
TECHNICAL FIELD 
     The invention relates generally to multistage amplifier system and, more particularly, to multistage amplifier system having reduced noise and offset. 
     BACKGROUND 
     Turning to  FIG. 1  of the drawings, a conventional two-stage amplifier system  100  can be seen. System  100  generally comprise a first stage  102  and a second stage  104  (which are each generally inverting amplifiers). As can be seen, resistor networks (resistors R 1 /R 1  and resistors R 3 /R 4 ) are coupled between the negative input terminals and output terminals of operational amplifiers  106  and  108 , respectively, so that stage  102  can receive the input signal VIN and that stage  104  can receive output signal VOUT 1 . Additionally, offset voltage source  110  and  112  provide offset voltages VOS 1  and VOS 2  to operational amplifiers  106  and  108 , respectively. Each of the voltage sources  110  and  112  (which include the internal offsets of amplifiers  106  and  108 ) are also coupled to supply rail  114  (which is generally at ground). 
     Because of the configuration of system  100  offset and noise contributions from voltage source  110  can significantly affect the output signal VOUT 2 . For the amplifier stage  102 , output signal VOUT 1  can be represented as follows: 
                     VOUT   ⁢           ⁢   1     =             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     VIN   -     VOS   ⁢           ⁢   1       )       +     VOS   ⁢           ⁢   1               (   1   )               
Additional, amplifier stage  104 , output signal VOUT 2  can be represented as follows:
 
                     VOUT   ⁢           ⁢   2     =             -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (       VOUT   ⁢           ⁢   1     -     VOS   ⁢           ⁢   2       )       +     VOS   ⁢           ⁢   2               (   2   )               
Now, substituting equation (1) into equation (2), output signal VOUT 2  becomes:
 
                         VOUT   ⁢           ⁢   2     =               -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     VIN   -     VOS   ⁢           ⁢   1       )       +     VOS   ⁢           ⁢   1     -     VOS   ⁢           ⁢   2       )       +     VOS   ⁢           ⁢   2       =           R   ⁢           ⁢     4   ·   R     ⁢           ⁢   2       R   ⁢           ⁢     3   ·   R     ⁢           ⁢   1       ⁢   VIN     +           -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (     (         R   ⁢           ⁢   2       R   ⁢           ⁢   1       +   1     )     )     ⁢   VOS   ⁢           ⁢   1     -     VOS   ⁢           ⁢   2           )     +     VOS   ⁢           ⁢   2             (   3   )               
Equation (3) can also be expressed as a function of offset voltage VOS 1  (where offset voltage VOS 2  is about 0):
 
                     VOUT   ⁢           ⁢   2     =           R   ⁢           ⁢     4   ·   R     ⁢           ⁢   2       R   ⁢           ⁢     3   ·   R     ⁢           ⁢   1       ⁢   VIN     +           -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (         R   ⁢           ⁢   2       R   ⁢           ⁢   1       +   1     )     ⁢   VOS   ⁢           ⁢   1               (   4   )               
When resistor R 1  is coupled to a block capacitor (AC coupled), the input signal VIN is equal to offset voltage VOS 1 , reducing equation (3) as follows:
 
                     VOUT   ⁢           ⁢   2     =               -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (       VOS   ⁢           ⁢   1     -     VOS   ⁢           ⁢   2       )       +     VOS   ⁢           ⁢   2       =         (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2     -         R   ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢   VOS   ⁢           ⁢   1                 (   5   )               
So, it can clearly be see from the DC coupled and AC coupled cases of equations (3) through (5), respectively, that noise and offset contributions in output voltage VOUT 2  from offset voltage VOS 1  can be significant. Thus, system  100  may require the use of trim circuit or better device matching to reduce the noise and offset contributions from offset voltage VOS 1 .
 
     Some other conventional designs are: U.S. Pat. No. 3,899,743; U.S. Pat. No. 5,257,285; U.S. Pat. No. 6,642,783; U.S. Pat. No. 7,132,882; and U.S. Patent Pre-Grant Publ. No. 2006/0279344. 
     SUMMARY 
     A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a first amplifier stage having an input terminal and an output terminal, wherein the first amplifier receives an input signal at its input terminal, and wherein the first amplifier stage includes a first offset voltage source that provide a first offset voltage to the first amplifier stage and that is coupled to a supply rail; and a second amplifier stage having an input terminal and an output terminal, wherein the input terminal of the second amplifier stage is coupled to the output terminal of the first amplifier stage, and wherein the second amplifier offset includes a second offset voltage source that provides a second offset voltage to the second amplifier stage, and wherein the second offset voltage source is coupled to the first amplifier stage so as to substantially reduce noise contribution from the first offset voltage. 
     In accordance with a preferred embodiment of the present invention, the first and second amplifiers stages further comprise a first inverting amplifier and a second inverting amplifier, respectively. 
     In accordance with a preferred embodiment of the present invention, the first inverting amplifier further comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the second offset voltage source is coupled to the first input terminal of the operational amplifier, and wherein the first voltage offset source is coupled to the second input terminal of the operational amplifier; and a resistor network coupled to the input terminal of the first inverting amplifier, the first input terminal of the operational amplifier, and the output terminal of the operational amplifier. 
     In accordance with a preferred embodiment of the present invention, the resistor network further comprises a plurality of resistors coupled in series with one another. 
     In accordance with a preferred embodiment of the present invention, the first input terminal of the operational amplifier is a negative input terminal, and wherein the second input terminal of the operational amplifier is a positive input terminal. 
     In accordance with a preferred embodiment of the present invention, the second inverting amplifier further comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the second voltage offset source is coupled to the second input terminal of the operational amplifier; and a resistor network coupled to the output terminal of the first inverting amplifier, the first input terminal of the operational amplifier, and the output terminal of the operational amplifier. 
     In accordance with a preferred embodiment of the present invention, the first input terminal of the operational amplifier is a negative input terminal, and wherein the second input terminal of the operational amplifier is a positive input terminal. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a first inverting amplifier having: a first resistor that receives an input signal; a first operational amplifier having a positive input terminal, an negative input terminal, and an output terminal, wherein the negative input terminal is coupled to the first resistor; a second resistor that is coupled between the output terminal of the first operational amplifier and the negative input terminal of the first operational amplifier; and a first offset voltage source that is coupled between the positive input terminal of the first operational amplifier and ground; and a second inverting amplifier having: a third resistor that is coupled to the output terminal of the first operational amplifier; a second operational amplifier having a negative input terminal, a positive input terminal, and an output terminal, wherein the negative input terminal of the second operational amplifier is coupled to the third resistor; a fourth resistor that is coupled between the output terminal of the second operational amplifier and the negative input terminal of second operational amplifier; and a second offset voltage source that is coupled between the positive input terminal of the second operational amplifier and the negative input terminal of the first operational amplifier. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is an example of a conventional multistage system; and 
         FIG. 2  is an example of a multistage system in accordance with a preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
     Turning to  FIG. 2  of the drawings, a multistage system  200  in accordance with a preferred embodiment of the present invention can be seen. System  200  generally comprises amplifiers stages  202  and  204  (which are generally inverting amplifiers). When compared to system  100 , system  200  has the same general components. One difference, however, is the coupled to voltage source  112  and the negative input terminal of operational amplifier  106  instead of supply rail  114 . By making this change, the output voltage VOUT 1  is represented as follows: 
                     VOUT   ⁢           ⁢   2     =             -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (       VOUT   ⁢           ⁢   1     -     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )       )       +     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )               (   6   )               
If equation (1) is substituted into equation (6), it becomes:
 
                         VOUT   ⁢           ⁢   2     =               -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     VIN   -     VOS   ⁢           ⁢   1       )       +     VOS   ⁢           ⁢   1     -     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )       )       +     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )       =             -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     VIN   -     VOS   ⁢           ⁢   1       )       -     VOS   ⁢           ⁢   2       )       +     VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2           )     =           R   ⁢           ⁢     4   ·   R     ⁢           ⁢   2       R   ⁢           ⁢     3   ·   R     ⁢           ⁢   1       ⁢   VIN     +           -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (           R   ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢   VOS   ⁢           ⁢   1     -     VOS   ⁢           ⁢   2       )       +     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )               (   7   )               
Equation (7) can also be expressed as a function of offset voltage VOS 1  (where offset voltage VOS 2  is about 0):
 
                     VOUT   ⁢           ⁢   2     =             R   ⁢           ⁢     4   ·   R     ⁢           ⁢   2       R   ⁢           ⁢     3   ·   R     ⁢           ⁢   1       ⁢   VIN     +           -   R     ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (         R   ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢   VOS   ⁢           ⁢   1     )       +     VOS   ⁢           ⁢   1       =           R   ⁢           ⁢     4   ·   R     ⁢           ⁢   2       R   ⁢           ⁢     3   ·   R     ⁢           ⁢   1       ⁢   VIN     +       (     1   -       R   ⁢           ⁢     4   ·   R     ⁢           ⁢   2       R   ⁢           ⁢     3   ·   R     ⁢           ⁢   1         )     ⁢   VOS   ⁢           ⁢   1                 (   8   )               
Additionally, when resistor R 1  is coupled to a block capacitor (AC coupled), the input signal VIN is equal to offset voltage VOS 1 , reducing equation (7) as follows:
 
                     VOUT   ⁢           ⁢   2     =             R   ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢   VOS   ⁢           ⁢   2     +     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )       =         (         R   ⁢           ⁢   4       R   ⁢           ⁢   3       +   1     )     ⁢   VOS   ⁢           ⁢   2     +     VOS   ⁢           ⁢   1                 (   9   )               
As can clearly be seen by comparing equation (5) to equation (9) and equation (4) to equation (8), offset contributions from offset voltage VOS 1  in output signal VOUT 2  can be significantly reduced. Additionally, for noise contributions, the same analysis would apply to a noise analysis, leading a reduced noise in system  200  as compared to system  100 .
 
     As an example, these types of cascaded arrangements are typically used for single ended to differential conversion, where the differential output voltage V OUTDiff  is:
 
 V   OUTDiff   =V OUT1 −V OUT2  (10)
 
One can substitute equation (1) and (2) (for the conventional system  100 ) into equation (10) to arrive at the differential output voltage V OUTDiff , which becomes:
 
                     V   OUTDiff     =         VOUT   ⁢           ⁢   1     -     VOUT   ⁢           ⁢   2       =         VOU   ⁢           ⁢   1     +         R   ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (       VOUT   ⁢           ⁢   1     -     VOS   ⁢           ⁢   2       )       -     VOS   ⁢           ⁢   2       =           (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOUT   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2       =           (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢     (             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     VIN   -     VOS   ⁢           ⁢   1       )       +     VOS   ⁢           ⁢   1       )       -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2       =                 -   R     ⁢           ⁢   2     ⁢               R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VIN     +         R   ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     +       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2       =             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VIN     +       (     1   +       R   ⁢           ⁢   2       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2                         (   11   )               
Alternatively, one can substitute equation (1) and (6) (for the system  200 ) into equation (10) to arrive at the differential output voltage V OUTDiff , which becomes:
 
               V   OUTDiff     =         VOUT   ⁢           ⁢   1     -     VOUT   ⁢           ⁢   2       =         VOUT   ⁢           ⁢   1     +         R   ⁢           ⁢   4       R   ⁢           ⁢   3       ⁢     (       VOUT   ⁢           ⁢   1     -     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )       )       -     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )       =           (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOUT   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )         =           (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢     (             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     VIN   -     VOS   ⁢           ⁢   1       )       +     VOS   ⁢           ⁢   1       )       -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )         =               -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VIN     +       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢     (     1   +       R   ⁢           ⁢   2       R   ⁢           ⁢   1         )     ⁢   VOS   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢     (       VOS   ⁢           ⁢   1     +     VOS   ⁢           ⁢   2       )         =               -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VIN     +         R   ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     +       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2       =             -   R     ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VIN     +         R   ⁢           ⁢   2       R   ⁢           ⁢   1       ⁢     (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   1     -       (     1   +       R   ⁢           ⁢   4       R   ⁢           ⁢   3         )     ⁢   VOS   ⁢           ⁢   2                         
Comparing equations (11) and (12), the input signal VIN and offset voltage VOS 2  contributions are clearly the same for both, whereas the offset voltage VOS 1  contribution is significantly reduced. Additionally, because (in a differential to single ended conversion) the ratio of resistors R 4 /R 3  is generally 1. Equations (11) and (12) can be rewritten as follows (where the input signal VIN and offset voltage VOS 2  contributions have been dropped):
 
                     V   OUTDiff     =       (     2   +     2   ·       R   ⁢           ⁢   2       R   ⁢           ⁢   1           )     ⁢   VOS   ⁢           ⁢   1                     ⁢     (   13   )                   V   OUTDiff     =       2   ·       R   ⁢           ⁢   2       R   ⁢           ⁢   1         ⁢   VOS   ⁢           ⁢   1                     ⁢     (   14   )                 
Clearly, system  200  has superior performance over system  100 .
 
     Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.