Abstract:
In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/315,337 filed on Dec. 9, 2011, which is a divisional of U.S. patent application Ser. No. 12/341,002 filed on Dec. 22, 2008, issued as U.S. Pat. No. 8,097,506 on Jan. 17, 2012. These applications and patent are incorporated herein by reference in their entirety and for any purpose. 
     
    
     BACKGROUND 
       [0002]    This relates generally to microelectronic memories. 
         [0003]    Columns of flash memory cells in memory arrays may be isolated by shallow trench isolations. In the shallow trench isolation process, shallow trenches are formed between the columns using, as a mask, the polysilicon that will form the gate electrode. Ultimately, these trenches are filled with an insulator that isolates one column from its two adjacent neighbors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is an enlarged, cross-sectional view at an early stage of manufacture; 
           [0005]      FIG. 2  is an enlarged, cross-sectional view at a stage subsequent to that shown in  FIG. 1  in accordance with one embodiment; 
           [0006]      FIG. 3  is an enlarged, cross-sectional view at a stage subsequent to that shown in  FIG. 2  in accordance with one embodiment; 
           [0007]      FIG. 4  is an enlarged, cross-sectional view at a stage subsequent to that shown in  FIG. 3  in accordance with one embodiment; 
           [0008]      FIG. 5  is an enlarged, cross-sectional view at a stage subsequent to that in accordance with one embodiment; 
           [0009]      FIG. 6  is an enlarged, cross-sectional view at a subsequent stage; 
           [0010]      FIG. 7  is an enlarged, cross-sectional view at a subsequent stage; and 
           [0011]      FIG. 8  is an enlarged, cross-sectional view at a subsequent stage. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    In accordance with some embodiments, substrate active area corners, adjacent to shallow trench isolations, are made electrically inactive. By making these corners electrically inactive, reliability issues related to the corners may be reduced. For example, active area thinning or thickening, increased electric field in the corner region, or combinations of these may lead to accelerated degradation of the active oxide over these corners. 
         [0013]    In accordance with one embodiment, a self-aligned, shallow trench isolation approach may be utilized. However, other approaches may be utilized as well. In the self-aligned shallow trench isolation approach, part of the floating gate is defined while etching the trench for shallow trench isolation. Then the rest of the floating gate polysilicon is deposited and patterned further on in the process flow using lithographic or damascene techniques. 
         [0014]    Another approach that may be utilized, in accordance with some embodiments, is advanced self-aligned shallow trench isolation where the whole floating gate is defined while etching the trench during shallow trench isolation. Also, a pol-chemical mechanical planarization (poly-CMP) approach may be used. In poly-CMP, the floating gate is built by a damascene process. Then the shallow trench isolation nitride acts as a place holder and the field oxide is used as a stepping layer for damascene process. 
         [0015]    In accordance with some embodiments, spacers are used around gate material that will ultimately form at least part of a gate electrode. The spacers on the gate material form an etching mask to space the resulting, etched shallow trench away from the ultimate gate electrode structure. This spacing forms electrically inactive active area corners at the substrate locations covered the spacers. Those spacers create an electrically inactive ledge region of the substrate active area to either side of the gate electrode. The ledges and the shallow trench isolation are self-aligned to the gate material. 
         [0016]    Referring to  FIG. 1 , a bulk silicon microelectronic substrate  12  may be covered a tunnel dielectric  14 , a lower gate layer  16 , a dielectric layer  18 , and a nitride layer  20  to form the structure  10 . The tunnel dielectric  14  and the dielectric layer  18  may be formed by any suitable insulating material including oxide. The lower gate layer  16  may be doped or undoped polysilicon or other suitable conductive or non-conductive gate forming materials. In another embodiment, the substrate  12  may be formed of epitaxial material. 
         [0017]    As shown in  FIG. 2 , gate structures are then defined and etched to form strips. The individual gates are not separated at this point. In  FIG. 2 , two adjacent columns are shown, but many parallel columns may be provided. Each strip may include a nitride layer  20  over a dielectric layer  18 , a lower gate layer  16 , and a tunnel dielectric  14 , situated on the microelectronic substrate  12 . 
         [0018]    In some embodiments, the layer  16  is the lower part of a two-part floating gate for a flash memory. However, the present invention is not limited to floating gates or two-part gates. 
         [0019]    Referring to  FIG. 3 , spacers  22  have been formed on the lower gate structures of  FIG. 2 . The spacers  22  may be sidewall spacers in one embodiment. However, overhanging spacers, such as an overhanging nitride spacer, may us another embodiment. The spacer  22  material an insulator, such as oxide, for example. In some embodiments, it is advantageous to use, as the spacer  22 , a dielectric other than nitride and material other than the lower gate material; to facilitate subsequent nitride mask removal. 
         [0020]    Spacers  22  may be formed by blanket depositing the spacer material. In one embodiment, this blanket deposited spacer structure is then anisotropically etched to form t spacers  22  shown in  FIG. 3 . 
         [0021]    In some embodiments, unlike conventional sidewall spacers used for spacing source drain implants, the spacers  22  are arranged on the sides of gate structure that will not have a source or drain. That is, the spacers are aligned perpendicular to the direction through the subsequently formed source/drains. 
         [0022]    Then, as shown in  FIG. 4 , the structure shown in  FIG. 3  is used as a mask for shallow trench  24  isolation etching. The resulting shallow trenches  24  separate the strips and, ultimately, separate adjacent columns of cells from one another. The shallow trenches  24  are displaced outwardly of the gate stack by way of the spacers  22 , forming the electrically inactive ledges  25  in the active area  34 . 
         [0023]    Next, a sidewall ion may be performed, followed by gap filling and field ex chemical mechanical planarization to form the field oxide  28 , as shown in  FIG. 5 . In some embodiments, the spacer (no longer shown) is left in place buried within the field oxide  28 . In other embodiments, the spacer  22  is removed prior to gap filling and, in some cases, before sidewall oxidation. The sidewall oxidation oxidizes edges of the trench  24  sidewalls to recover etch damage, to protect the trench  24 , and to round the corners of the active areas  34 . 
         [0024]    An etch process, illustrated in  FIG. 6 , may remove the nitride layer  20 , whose function is completed. A buffer oxide wet etch may be utilized. As a result, the layer  16  may be partially exposed, because the width of the resulting trench  30  may be wider than the width of the layer  16  in some embodiments. The trench  30  width may correspond to the width of the active area  34  defined between adjacent trenches  24 . 
         [0025]    Next, as shown in  FIG. 7 , an upper gate layer  32  may be deposited on the layer  16  and patterned to form a strip extending parallel to the shallow trenches  24 . Note that the upper gate layer  32  extends over the sides of the lower gate layer  16 , forming an overhanging or mushroom shaped gate structure, that may be a floating gate in some embodiments. 
         [0026]    The dielectric  36  under the layer  32  is thicker than the tunnel dielectric  14  under the layer  16  in one embodiment. In some embodiments, the layer  16  may be undoped as deposited and the layer  32  may be doped as deposited. Subsequent thermal treatments may dope the layer  16  via diffusion from the layer  32 . 
         [0027]    Finally, the field oxide  28  may be subjected to recession down to a level slightly below the upper level of the lower gate layer  16 , as shown in  FIG. 8 . This exposes the upper surface of the upper gate layer  32 , but not its lower surface, avoiding etch-related damage to the tunnel electric. 
         [0028]    The rest of the process can proceed conventionally, including formation of interpoly dielectric, control gates, and sources and drains in the column direction (into the page) in the active areas  34 . 
         [0029]    In some embodiments, it is advantageous to form the shallow trenches  24  prior to forming a mushroom shaped floating gate. The techniques described herein are applicable to both NOR and NAND flash memories, as well as other microelectronic memories. 
         [0030]    References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. 
         [0031]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.