Abstract:
A CAM device features matchlines which are coupled in series between a top current source, a bottom current source, and ground. The top current source is configured to supply a first current to the matchline and the bottom current source, while the bottom current source is configured to supply a second current to ground. The magnitude of the first current is limited by the operation of the CAM cells coupled to the matchline, and is duplicated by a current mirror architecture. The mirrored of the first current, known as the sense current, is coupled to a measurement circuit to measure the state of the matchline. This architecture features lower power consumption and faster matchline evaluations.

Description:
FIELD OF INVENTION 
   The present invention relates generally to semiconductor memory devices and, more particularly to power reduction and matchline switching noise suppression in content addressable memory (CAM) devices. 
   BACKGROUND OF THE INVENTION 
   An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM). 
   Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching. 
   In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address. 
   In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing). 
   Once information is stored in a memory location, it is found by comparing every bit in a memory location with corresponding bits in a comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, a local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which desired data is stored or identification of one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back an address if there is a match found in memory. 
     FIG. 1  is a circuit diagram showing a conventional DRAM-based CAM cell  100 , which includes two one-transistor ( 1 T) DRAM cells  110   a  and  110   b , and a four-transistor comparator circuit  120  made up of transistors Q 2  through Q 5 . Although  FIG. 1  illustrates a DRAM-based CAM cell, it should be recognized that CAM devices can also be made using SRAM-based CAM cells. DRAM cells  110   a  and  110   b  are used to store values. Generally, the content of cell  110   a  is the logical NOT of the content of cell  110   b . However, the cells  110   a ,  110   b  may also store the same values, i.e., “0”/“0”, or “1”/“1”, so that the CAM cell is respectively set to “always match” or “always mismatch” states. DRAM cell  110   a  includes transistor Q 1  and a capacitor CA, which combine to form a storage node A that receives a data value from bitline BL 1  at node U during write operations, and applies the stored data value to the gate terminal of transistor Q 2  of comparator circuit  120 . Transistor Q 2  is connected in series with transistor Q 3 , which is controlled by a data signal transmitted on data line D 1 #, between a matchline M and ground potential. It should be noted that in some embodiments transistors Q 2  and Q 4  are coupled to a discharge line instead of being directly coupled to ground. The second DRAM cell  110   b  includes transistor Q 6  and a capacitor CB, which combine to form a storage node B that receives a data value from bitline BL 2  at node V, and applies the stored data value to the gate terminal of transistor Q 4  of comparator circuit  120 . Transistor Q 4  is connected in series with transistor Q 5 , which is controlled by a data signal transmitted on inverted data line D 1 , between the matchline and the ground potential. 
     FIG. 2  is a block diagram of a portion of a CAM device  200  which includes a plurality of CAM cells, such as the CAM cell  100  of  FIG. 1 . For purposes of simplicity, only a portion of the CAM device  200  is illustrated. In particular, some well known components, such as the previously discussed comparand register, control logic, and I/O logic are not illustrated. The device  200  includes two arrays  210   a ,  210   b  of CAM cells  100 . Each array  210   a ,  210   b  includes its own bitlines (e.g., BL 11 –BL 16  for array  210   a , and BL 21 –BL 26  for array  210   b ), wordlines (e.g., WL 11 –WL 12  for array  210   a ), and matchlines (e.g., M 11 –M 12  for array  210   a ). Each wordline WL 11 –WL 12 , WL 21 –WL 22  is coupled to a respective wordline driver  220   a ,  220   b . Similarly, each bitline is also coupled to respective bitline drivers (not illustrated). Each matchline is coupled to each row of CAM cell  100  in the same wordline. The CAM device  200  also includes a plurality of bitline sense amplifiers  230 . Each bitline sense amplifier  230  is coupled to the CAM cells  100  from two different arrays by two separate bitlines (e.g. bitlines BL 11 , BL 21 ). 
   Now referring back to  FIG. 1 , in order perform a write operation upon a CAM cell, the data values (which are complements) to be stored are respectively written to dynamic storage nodes A and B by applying appropriate voltage signals (e.g., Vcc for logical ‘1’ or ground for logical ‘0’) on bitlines BL 11  and BL 12 , and then applying a voltage signal on wordline WL. The voltage on wordline WL turn on transistor Q 1  and Q 6 , thereby passing the voltage signals to dynamic storage nodes A and B. Refresh circuitry (not illustrated), periodically refreshes the charges stored in capacitors CA and CB, so the data does not decay over time. 
   In order to perform a read operation, data stored as a charge level in the capacitors CA, CB of one of the dynamic storage nodes A, B of the CAM cell  100  is sensed using an associated sense amplifier  230  ( FIG. 2 ) which compares the voltage level of a bitline coupled to one of the dynamic storage nodes (known as the active bitline) with the voltage level of a bitline not coupled to any dynamic storage nodes (known as the reference bitline). For example, node A of the CAM cell  100  which appears as the top left CAM cell illustrated in  FIG. 2  can be sensed by first precharging two bitlines. The two bitlines to be precharged would include the bitline BL 11  which will couple the CAM cell  100  to the sense amplifier  230  (i.e., the active bitline), as well as the other bitline BL 21  coupled to the same sense amplifier  230  (i.e., the reference bitline). As illustrated in  FIG. 2 , each sense amplifier has one input coupled to a bitline of array  210   a  and another input coupled to a corresponding bitline of array  210   b . The wordline WL 12  associated with the CAM cell  100  would then be activated by an applied voltage, causing the transistor Q 1  in the CAM cell  100  to conduct and thereby share the charge of capacitor CA with bitline BL 1 . Depending upon the charge level stored in capacitor CA, the voltage level of bitline BL 11  will either remain the same or be lowered. The sense amplifier  230  is then used to detect whether there is a change in potential between BL 11  and BL 21 . The sense amplifier outputs an indication of the state stored at storage node A as a signal indicating any potential difference between bitlines BL 11  and BL 21  on line  235 . 
   In order to perform a match operation, the data stored at nodes A and B are respectively applied to the gate terminals of transistors Q 2  and Q 4  of comparator circuit  120 . Comparator circuit  120  is utilized to perform match (comparison) operations after the matchline M has been precharged by a precharge circuit (not illustrated). For example, when matchline M is precharged, an applied data value and its complement are transmitted on data lines D 1  and D 1 # to the gate terminals of transistor Q 3  and Q 5 , respectively. A no-match condition is detected when matchline M is discharged to ground through the signal path formed by transistors Q 2  and Q 3 , or through the signal path formed by transistors Q 5  and Q 4 . For example, when the stored data value at node A and the applied data value transmitted on data line D 1 # are both logic “1”, then both transistors Q 2  and Q 3  are turned on to discharge matchline M to ground. When a match condition occurs, matchline M remains in its pre-charged state (i.e., no signal path is formed by transistors Q 2  and Q 3 , or transistors Q 5  and Q 6 ). 
   The above described match operation is directed to what happens in a single CAM cell  100 . In a real CAM device, however, the match operation is performed simultaneously on all CAM cells. In contrast, a conventional memory device, such as a DRAM, does not directly support a match function and must therefore be operated in accordance with a search algorithm to sequentially search each memory location for in order to perform the same function. Thus search operations are typically performed much faster by a CAM device. However, CAM devices consume significantly more power and produce significantly more switching noise than a conventional memory device, especially during search operations because CAM cells are accessed simultaneously. Additionally, the current flow through each matchline varies based on how well the CAM cells associated with the matchline match the search expression. This is because each CAM cell which does not match its respective search data will form a pull down path between the matchline and ground, while each CAM cell which matches it respective search data will not form a pull down path between the matchline and ground. In CAM devices each matchline is typically coupled to a large number of CAM cells. The number of pull down paths on a matchline can therefore vary greatly during a search. Thus, the rate which a matchline can be discharged will can also vary greatly. This range in current flow in each matchline, especially when compounded by differences caused by variations in semiconductor process, power supply voltage variations, and temperature variations makes sensing the state of each matchline M a difficult procedure. Accordingly, there is a need for a CAM device architecture having a matchline sensing mechanism which is relatively immune to the number of CAM cells which match on a search operation. 
   SUMMARY OF THE INVENTION 
   Embodiments of the invention are directed to a CAM device architecture where each matchline is coupled in series between a top current source, a bottom current source, and ground. The top current source is responsive to a first bias current (Ibias 1 ) to supply a first bias current (Ibias 1 ) to the matchline and the bottom current source, while the bottom current source is responsive to a second bias current (Ibias 2 ) to drain a second current equal to the second bias current from the matchline to ground. The first bias current is greater in magnitude than the second bias current (Ibias 1 &gt;Ibias 2 ). Although the top current source is configured to supply a first current equal to the first bias current, the magnitude of the first current is limited by the operation of the CAM cells coupled to the matchline as described below. If during a search operation, each of the CAM cells coupled to a mach line matches its respective search data, there would not be any pull downs through the CAM cells from the matchline to ground. Thus, for a successfull match during a search, the first current is limited to magnitude of the second current, and thus the second bias current.) However, if during a search operation at least one of the CAM cells coupled to the matchline mis-matches its respective search data, there would be a pull down through the CAM cell(s) from the matchline to ground. The top current source would then feed and force the first current to both the matchline and the lower current mirror. This higher level of current is ideally the level of the first bias current. Thus, the first current during a non-matched search operation would be equal to the first bias current (Ibias 1 ). Ideally both the top and bottom current source are each part of a current mirror. That is, the top current source is part of a top current mirror and the bottom current source is part of a bottom current mirror. Each current mirror has two “legs.” One leg is coupled in series with the matchline as described above, while another leg is instead coupled to circuitry which measures the mirrored current. The mirrored current is the current which is sensed by the measurement circuit, so it is known as the sense current (Is). Measuring the sense current (Is) produced by a current mirror architecture isolates the first current from the measurement circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings, in which: 
       FIG. 1  is a circuit diagram of a conventional CAM cell; 
       FIG. 2  is a block diagram of a conventional CAM device, illustrating how matchlines are shared across a plurality of CAM cells; 
       FIG. 3  is a block diagram illustrating an embodiment of the invention; 
       FIG. 4  is a circuit diagram of a first embodiment of the invention; 
       FIG. 5  is a circuit diagram of a second embodiment of the invention; 
       FIG. 6 . is a block diagram of a processor based system having a CAM device employing in accordance with the principles of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Now referring to the drawings, where like reference numerals designate like elements, there is shown in  FIG. 3  a block diagram a portion of a CAM device  300  in accordance with the principles of the present invention.  FIG. 3  illustrates a matchline M, which is coupled to a plurality of CAM cells  100  at their respective transistor comparator circuits  120 .  FIG. 3  also includes a top current source  301  and a bottom current source  302 . The matchline M is coupled in series between the top current mirror  301  and the bottom current mirror  302 , along line  303 . An output node  305  is also coupled in series between the top and bottom current mirrors  301 ,  302 , along line  304 . The top current mirror  301  is comprised of a current source  301   a  which is coupled via line  306  to a current mirror  301   b . The bottom current mirror  302  is also comprised of a current source  302   a  which is coupled via line  307  (or lines  307 ′ and  307 ″) to a current mirror  302   b.    
   The top current source  301   a  is responsive to a first bias current (Ibias 1 ) to supply a first current to the matchline M and the bottom current source  302   a  is responsive to a second bias current (Ibias 2 ) to supply a second current equal in magnitude to the second bias current from the matchline M to ground. The top and bottom current sources  301   a ,  302   a  are configured so that the magnitude of the first bias current is greater than the magnitude of the second bias current (Ibias 1 &gt;Ibias 2 ). The top current source  301   a  is configured to supply a first current equal in magnitude to the first bias current (Ibias 1 ), but the magnitude of the first current which flows from the top current source  301   a  is limited by the operation of the CAM cells  100  coupled to the matchline M during a search operation. If during a search operation, each of the CAM cells  100  coupled to the matchline M matches its respective search data, there would not be any pull downs through the circuits  120  of the CAM cells. Thus during a successful match, the matchline M remains isolated from ground and all of the first current output by the top current source  301   a  flows through the bottom current source  302   a . Thus, the first current which flows from the top current source  301   a  during a successful match is equal to the second current, i.e., the first current is equal to the second bias current (I 1 =Ibias 2 ). 
   If during a search operation, at least one of the CAM cells  100  coupled to the matchline M fails to match its respective search data, the circuit(s)  120  of each non-matching CAM cell  100  will pull the matchline to ground. As a result, the first current flows through both the matchline M and the bottom current source  302   a . Ideally, the first bias current level (Ibias 1 ) is chosen to be equal to this current level. Thus, the first current (I 1 ) during a non-successful match will equal to the first bias current (i.e., I 1 =Ibias 1 ). 
   Since the top and bottom current mirrors  301 ,  302  each include respective current mirrors  301   b ,  302   b , the first current flowing out of the top current source  301   a  on line  303  is duplicated on line  304 , as the sensing current (Is). A measuring circuit  305  is coupled to the first and second current mirror. In an exemplary embodiment, the measuring circuit  305  is a pair of inverters  305   a ,  305   b  (See  FIGS. 4–5 ) coupled to line  304  so as to be in series with the top and bottom current mirror  301   b ,  302   b . The function of the second inverter  305   b  is to achieve a desired polarity for output. Thus, the measuring circuit  305  may also be constructed using a single inverter  305   a . The measuring circuit  305  outputs a voltage Vout indicative of the state of the current Is. The use of the measuring circuit  305  on the current mirror of the top and bottom current mirrors isolates the measuring circuit  305  from the matchline. 
     FIGS. 4 and 5  are circuit diagrams illustrating two exemplary embodiments of the top and bottom current sources  301 ,  302 . The two embodiments differ only in their implementation of the bottom current source. Thus, the top current mirror  301 , including the current source  301   a  and the current mirror  301   b , are identical in both  FIGS. 4 and 5 . Additionally, the same sensing circuit  305  are used in both embodiments. 
   Now referring to  FIG. 4 , it can be seen that the first current source  301   a  is comprised of a transistor Q 10  having a first source/drain terminal coupled to a power source having Vcc potential and a second source/drain terminal coupled to a first source/drain terminal of a transistor Q 11 . The second source/drain terminal of transistor Q 11  is coupled the matchline M via line  303 . A first bias circuit  311  includes a transistor Q 12  having one source/drain coupled to a power source having Vcc potential and a second source/drain coupled to a first source/drain of a transistor Q 13 . The second source/drain of transistor Q 13  is coupled to a current source IS 1 . The current source IS 1  is biased to supply a first bias current Ibias 1  to ground, and can be constructed using a conventional bandgap technique to supply a constant current across a range of temperatures. The gate of the Q 12  transistor is coupled to the second source/drain terminal of Q 12 , while the gate of transistor Q 13  is coupled to the gate of transistor Q 11 . 
   The top current mirror  301   b includes a transistor Q 14 , having a first source/drain terminal coupled to a power source having Vcc potential and a gate coupled the gate of transistor Q 10  from the first current source  301   a  via line  306 . The other source/drain terminal of transistor Q 14  is coupled, via line  304 , to the measuring circuit  305 . 
   The measuring circuit  305  is coupled to line  304 , between the top and bottom current mirrors  301   b ,  302   b , and includes two series connected inverters  305   a ,  305   b . The measuring circuit  305  acts as a voltage divider, and the two inverters force the output voltage Vout to be either a logical “0” or “1.” 
   The bottom current source  302   a  includes a transistor Q 20  which has a first source/drain terminal coupled to the matchline via line  302 , and a second source/drain terminal coupled to a first source/drain terminal of a transistor Q 21 . The gate terminal of transistor Q 20  is coupled to a second bias circuit  312  as later described. The second source/drain terminal of transistor Q 21  is coupled to ground. The first source/drain terminal of transistor Q 21  is also coupled to the gate terminal of transistor Q 21 . 
   A second bias circuit  312  includes a Vcc potential coupled to a second current source IS 2 , which is biased to generate a second bias current Ibias 2 . The current source IS 2  can be constructed using a conventional bandgap technique to supply a constant current across a range of temperatures. In the illustrated embodiment, the first bias current Ibias 1  is greater than the second bias current Ibias 2 . The second current source IS 2  is coupled to the first source/drain terminal and the gate terminal of transistor Q 22 . The gate terminal of transistor Q 22  is also coupled to the gate terminal Q 20  of the second current source  302   a . A second source/drain terminal of transistor Q 22  is coupled to the gate and first source/drain terminal Q 23 , while the second source/drain terminal of transistor Q 23  is coupled to ground. The second current mirror  302   b  includes a transistor Q 24  having a first source/drain terminal coupled to the measurement circuit  305  and the second source/drain terminal of transistor Q 14 . The second source/drain terminal of transistor Q 24  is coupled to ground. The gate of transistor Q 24  is coupled to the gate of transistor Q 21  via line  307 . 
   Now referring to  FIG. 5 , it can be seen that this second embodiment differs from the embodiment illustrated in  FIG. 4  only in the lower current source  302   a  and current mirror  302   b . More specifically, in the lower current source  302   a ′, transistor Q 21  no longer has its first source/drain terminal coupled to its gate terminal. Additionally, the lower current mirror  302   b ′ is now coupled to the lower current source  302   a  via two lines  307 ′,  307 ″ instead of a single line  307 . The first line  307 ′ couples the gates of transistors Q 20 , Q 22 , and Q 25 , and is also coupled to the source/drain terminal of transistor Q 22  which is coupled to the second bias current source IS 2 . The second line of  307 ″ couples the gates of transistors Q 21 , Q 23 , and Q 24  and is also coupled to the source/drain of Q 23  which is coupled to a source/drain of transistor Q 22 . 
   In both embodiments, circuit  301   a  is coupled via line  306  to circuit  301   b  and these two circuits are configured to be in a current mirror configuration so that the current Is measured by circuit  305  is the mirrored current of the current flowing from the Vcc power source in circuit  301   a  to line  303  in circuit  301   a . Circuit  311  is configured to bias the output current of circuit  301   a  to a predetermined level equal to Ibias 1 , which in circuit  311  is supplied by current source IS 1 . However, as previously discussed, the actual current output of circuit  301   a  is dependent upon the state of the matchline. 
   In the embodiment shown in  FIG. 4 , circuit  302   a  is configured to output a current equal to Ibias 2  to ground, where Ibias 2  is less than Ibias 1 . Line  307  couples circuit  302   a  to circuit  302   b , and circuits  302   a  and  302   b  are set up in a current mirror configuration so that the same amount of current flows through both circuits  302   a  and  302   b . Circuit  312  is configured to control the output of circuit  302   a , and includes second bias current (Ibias 2 ) current source IS 2 . In the embodiment shown in  FIG. 5 , circuits  302   a ′ and  302   b ′ perform the same function as circuits  302   a  and  302   b , respectively. However, as shown in the figures, circuits  302   a  and  302   b  have been modified to use two lines  307 ′,  307 ″ 0  instead of  307 . 
   Thus, the embodiments show in  FIGS. 4 and 5  both couple the matchline M between two current sources, each implemented within a current mirror. The current which flows out of the top current source is dependent upon the result of a search operation on the matchline, and can be sensed on current mirrors which are not coupled to the matchline. An output circuit preferably includes a pair of inverters to read the current state and output the state as a full range voltage signal. 
   Additionally, in the above embodiments, the matchline M will generally not be precharged to a full Vcc potential since the internal impedance of the upper current source  301   a  will cause a small potential drop. Thus, during evaluation the matchline M will no longer swing from Vcc to near-ground, thereby permitting a savings in power while simultaneously speeding up evaluation time. Additionally, the current in the power rails will be fix, thereby eliminating a source of switching noise. 
     FIG. 6  is an illustration of an exemplary processor based system  600  including a CAM device  300  in accordance with the principles of the present invention. The system  600  includes a central processing unit (CPU)  601 , a main memory  602 , at least one mass storage device  603 , at least peripheral devices  604 – 605  (e.g., keyboard and display), and a CAM subsystem  606 , each coupled to a bus  610 . The CAM subsystem  606  includes a plurality of CAM devices  300  of the present invention. 
   An example of a processor based system  600  may be a network router, in which case peripheral devices  604 – 605  may be network cards attached to different computer networks. The main memory  602  may include a random access memory for storing data, and a read only memory for storing a boot loader, and the mass storage device  603  may store an operating system and application software for the router. The CAM subsystem  606  may be used to store network routing table. 
   While the invention has been described in detail in connection with the exemplary embodiment, it should be understood that the invention is not limited to the above disclosed embodiment. Rather, the invention can be modified to incorporate any number of variations, alternations, substitutions, or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.