Abstract:
An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.

Description:
FIELD OF THE INVENTION 
     The present invention relates to noise suppression circuits generally and, more particularly, to a method and/or apparatus for implementing an AC noise suppression circuit from a bias signal in a high voltage supply/low voltage device. 
     BACKGROUND OF THE INVENTION 
     Conventional circuits for generating BIAS voltages have been used as intermediate voltages in high voltage  10  designs using low voltage devices. The BIAS voltages have been used as a source to control inverter stages in pre-driver circuits. Conventional designs also use BIAS voltages as a gate input to drive devices which interact with an input/output PAD. Such designs often have large capacitive currents and source/sink current, which contributes the AC noise. Decoupling capacitors have been used to discharge this AC noise. Such capacitors consume a large amount of chip area and expand the overall cell area. 
     It would be desirable to implement a circuit and/or method to provide AC noise suppression when generating a bias signal using high voltage supply/low voltage devices. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal. 
     The objects, features and advantages of the present invention include providing a noise suppression circuit that may (i) provide AC noise suppression, (ii) be implemented in a high supply/low voltage device, (iii) reduce chip area and/or (iv) be implemented on an Integrated Circuit (IC). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram of the invention; 
         FIG. 2  is a more detailed diagram of the invention; 
         FIG. 3  is a plot of the peak noise of the bias voltage versus the pad voltage without the circuit  100 ; and 
         FIG. 4  is a plot of the peak noise of the bias voltage versus the pad voltage with the circuit  100 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 1 , a block diagram of a circuit  100  is shown in accordance with an embodiment of the present invention. The circuit is shown in the context of a circuit  50 . The circuit  50  generally comprises the circuit  100 , a block (or circuit)  60 , a block (or circuit)  62  and a block (or circuit)  70 . The circuit  60  may be implemented as a bias circuit. The circuit  62  may be implemented as a voltage divider circuit. The circuit  70  may be implemented as a pad circuit. The pad circuit  70  may be one of a plurality of input/output pads connected between a core of an integrated circuit (IC) and a number of lead frames (not shown). A number of the circuits  100  may be implemented between a number of pads and the core of the integrated circuit. 
     The circuit  62  may be implemented as a transistor MN 1  and a transistor MP 1 . The circuit  100  may be used to generate a voltage (e.g., BIAS). The circuit  100  generally comprises a block (or circuit)  120 , a device C 1 , a device C 2  and a device C 3 . The circuit  120  may be implemented as an inverting amplifier circuit. The device C 1  may be implemented as a capacitor. The device C 2  may also be implemented as a capacitor. The device C 3  may also be implemented as a capacitor. The transistors MN 1  and MP 1  may have gates connected to BIAS_N and BIAS_P, respectively. A connection between the drain of the transistor MN 1  and the source of the transistor MP 1  may be connected to generate the signal BIAS. The signal BIAS_N may be designed to have a voltage BIAS+VT (where VT is a transistor threshold voltage). The signal BIAS_P may be designed to have a voltage BIAS−VT. 
     AC (alternating current) noise on the signal BIAS is generally passed to inverting amplifier circuit  120  through the capacitor C 1 . The inverting amplifier circuit  120  may amplify and/or invert the AC noise. The inverting amplifier  120  may be coupled to gates of the transistor MN 1  and the transistor MP 1  through the capacitor C 2  and the capacitor C 3 , respectively. The signal BIAS_N and the signal BIAS_P will normally shift AC noise on the signal BIAS in opposite directions. Shifting the noise through the inverting amplifier  120  may help to effectively suppress noise. 
     Referring to  FIG. 2 , a more detailed diagram of the circuit  50  is shown. The circuit  100  generally comprises the circuit  120 , a resistor R 1 , the capacitor C 1 , the capacitor C 2 , and the capacitor C 3 . The circuit  120  generally comprises a transistor MP 2  and a transistor MN 2 . The signal BIAS may be presented to the capacitor C 1 . The capacitor C 1  may be used to filter an AC component from the signal BIAS to generate a signal (e.g., VIN). The signal VIN may be presented to the resistor R 1 , and to a gate of the transistor MP 2  and a gate of the transistor MN 2 . A common connection between a drain of the transistor MP 2  and a source of the transistor MN 2  may be connected to a resistor R 1 , the capacitor C 2 , and the capacitor C 3  to generate a signal (e.g., VOUT). The transistor MN 1  may have a source connected to a power supply (e.g., VDDIO). The transistor MP 1  may have a drain connected to VSS. A gate voltage of the transistor MN 1  may be generated as BIAS+VT (e.g., the signal BIAS_N). A gate voltage of the transistor MP 1  may be generated as BIAS−VT (e.g., the signal BIAS_P). The circuit C 2  normally generates the signal BIAS. The signal BIAS_N and the signal BIAS_P are normally generated to be reliable (or consistent) over process voltage and temperature (PVT) variations. 
     The transistors MP 2  and MN 2  may form the inverting amplifier  120 . The amplifier  120  may be DC biased by the resistor R 1 . The input signal VIN and the output signal VOUT may be biased to be at the same DC voltage level. The AC noise on the signal BIAS is generally coupled to the amplifier  120  through the capacitor C 1 . The amplifier  120  will normally amplify the noise on the input signal VIN and provide an amplified inverted output as the signal VOUT. The signal VOUT is generally coupled to the gate of the transistor MN 1  and the gate of the transistor MP 1  through the capacitor C 2  and the capacitor C 3 , respectively. Since the signal VOUT is inverted compared to the signal BIAS, the transistor MN 1  and the transistor MP 1  will normally compensate for AC noise and will restore the DC value of the signal BIAS. 
     Referring to  FIG. 3 , a plot showing peak noise on the signal BIAS without the circuit  100  is shown. Generally, noise is associated with the signal PAD and moves in the direction of the signal PAD. 
     Referring to  FIG. 4 , reduction in peak on the signal BIAS when the circuit  100  is implemented. As shown, the circuit  100  saves at lease 90 mV of peak noise. In general, as the amplification strength of amplifier  100  increases, more peak noise is generally reduced. Additional amplification strength may increase the overall power used by the circuit  100 . The circuit  100  may be designed to balance noise reduction with power consumption. 
     The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. 
     The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.