Abstract:
In a data transmission device and method provided with e.g. duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches are faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of International Application PCT/JP2007/72565 filed on Nov. 27, 2007, the contents of which are herein wholly incorporated by reference. 
     
    
     FIELD 
       [0002]    The present invention relates to a data transmission device for transmitting or relaying data with switches made redundant. 
       BACKGROUND 
       [0003]    Related art examples [1] and [2] of such a data transmission device will be described below by referring to  FIGS. 14 and 15 . 
       Related Art Example [1] 
     (1:1 Redundancy System): FIG.  74   
       [0004]    A data transmission device  1   a  depicted in  FIG. 14A  has adopted a  1 : 1  redundancy system, being composed of e.g. a duplexed switches SW 0  and SW 1  (hereinafter, occasionally represented by a reference character SW), an N number of input interfaces IFi_ 1 -IFi_N (hereinafter, occasionally represented by a reference character IFi) for providing received data DT to either one of the switches SW 0  and SW 1 , output interfaces IFo_ 1 -IFo_N (hereinafter, occasionally represented by a reference character IFo) for outputting the data DT outputted from the switch SW 0  or SW 1  to a latter stage and a controller  10  for controlling the input interface IFi, the switch SW and the output interface IFo. 
         [0005]    In operation, firstly the controller  10  provides to the input interface IFi a selecting instruction INS for instructing to select the switch SW 0  in a working system. 
         [0006]    Taking as an example a case where as depicted the data DT destined for a device at a latter stage (not depicted) of the output interface IFo_ 1  is inputted to the input interface IFi_ 1 , the input interface IFi_ 1  provides the data DT only to the switch SW 0 , which outputs the data DT to the output interface IFo_ 1 . 
         [0007]    On the other hand, when a fault occurs in the switch SW 0  in the working system as depicted in  FIG. 14B , the switch SW 0  transmits a fault notification FL to the controller  10 . The controller  10  provides to the input interface IF_ 1  the selecting instruction INS for instructing to switch over to the switch SW 1  in the working system free from a fault occurrence to output the data DT. 
         [0008]    This enables the data DT to be received at the output interface IFo_ 1  through the switch SW 1 , whereby the data transmission device  1   a  can continue to perform the data transmission. 
       Related Art Example [2] 
     (1+1 Redundancy System): FIG.  15   
       [0009]    A data transmission device  1   b  depicted in  FIG. 15A  has adopted a 1+1 redundancy system, different from the above related art example [1] in that the input interface IFi provides the data DT to the switches SW 0  and SW 1  in parallel, and the output interface IFo selects the data DT outputted from one of the switches SW 0  and SW 1  based on the selecting instruction INS from the controller  10  and discards the data DT outputted from the other one. 
         [0010]    As depicted in  FIG. 15B , when a fault occurs in the switch SW 0  in the working system, the controller  10  having received the fault notification FL from the switch SW 0  provides to the output interface 
         [0000]    IFo_ 1  the selecting instruction INS for instructing to select only the data DT outputted from the switch SW 1 . 
         [0011]    Thus, even upon a fault occurrence in the switch SW, the data transmission device  1   b  can continue to perform the data transmission as with the above related art example [1]. 
         [0012]    There are the following reference examples (1) and (2) in the art: 
       Reference Example (1) 
       [0013]    A communication network system where a frame having stored a sequence number is transmitted/received between wireless terminals and each terminal can recognize that there are two terminals which are a hidden terminal in a positional relationship when the continuity of the sequence number stored in the received frame is missing (See e.g. Japanese Laid-open Patent Publication No. 2004-173146). 
       Reference Example (2) 
       [0014]    A transmission line switching system where a transmission equipment on a transmission line upstream side sends out a monitoring cell into both of a working transmission line and a protection transmission line, a transmission equipment on a downstream side adjusts a transmission delay of both of the transmission lines and the transmission lines are switched over when the transmission delays of both transmission lines are equalized (See e.g. Japanese Laid-open Patent Publication No. 08-186575). 
         [0015]    While the above related art examples [1] and [2] can continue to perform the data transmission when a fault occurs in the switch, the selection/switchover processing is required with the fault occurrence being triggered, so that during the switchover processing a short break can occur, disadvantageously failing to transmit the data. 
       SUMMARY 
       [0016]    [1] According to an aspect of the invention, a data transmission device includes: switches with redundancy, each outputting a frame in its input order; input interfaces, each coupled to each switch, generating frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frames generated to the switches in parallel; and at least one output interface sequentially storing the frames outputted from the switches for every unique information and selecting a first arrived frame among the frames stored with same input order information. 
         [0017]    [2] In the above [1], the output interface may store the frames in association with the switches having outputted the frames, determine that when the frames stored with the same input order information after a first specified time has lapsed from the selecting of the first arrived frame are detected, the switch corresponding to the frames detected is in a congested state and exclude following frames outputted from the switch in the congested state from being selected. 
         [0018]    [3] Also, in the above [2] after the frames outputted from the switch in the congested state are excluded from the selecting and before a second specified time has lapsed from the selecting of the first arrived frame, when the frames outputted from the switch in the congested state and stored with the same input order information are detected, the output interface may determine that the congested state is released and include following frames outputted out of the switch released from the congested state, as frames to be selected again. 
         [0019]    [4] Also, in the above [2], the data transmission device may further include a controller controlling the input interfaces and the output interface, wherein the output interface notifies information of the switch in the congested state to the input interfaces through the controller, thereby stopping the input interfaces from outputting the frames to the switch in the congested state. 
         [0020]    [5] Also, in the above [4] the output interfaces may deem that the congested state is released when a second specified time has lapsed from the notification of the information of switch in the congested state and notify through the controller the information of the switch released from the congested state to the input interfaces, thereby restarting the input interfaces to output the frames to the switch released from the congested state. 
         [0021]    [6] Also, in the above [2], the input interfaces and the output interfaces may be provided in pairs, in which one output interface having first determined the switch in the congested state notifies to one input interface forming a pair with the one output interface the information of the switch in the congested state to stop the one input interface from outputting the frames to the switch in the congested state and generates frames added with the information of the switch in the congested state to be provided to the other switches, thereby allowing the other output interfaces to determine the switch in the congested state and to notify the information of the switch in the congested state to the other input interfaces to stop the other input interfaces from outputting the frames to the switch in the congested state. 
         [0022]    [7] Also, in the above [6], the one output interface may deem that the congested state is released when a second specified time has lapsed from the notification of the information of switch in the congested state and notify the information of the switch released from the congested state to the one input interfaces to restart the one input interface to output the frames to the switch released from the congested state and add the information of the switch released from the congested state to the frames to be provided to each switch in parallel, thereby allowing the other output interfaces to determine the switch released from the congested state and to notify to the other input interfaces the information of the switch released from the congested state, thereby restarting the other input interfaces to output the frames to the switch released from the congested state. 
         [0023]    [8] Also, in the above [1], the input interfaces may classify the data into a plurality of classes based on specified information within the data and generate a frame in which class information, the unique information and the input order information are added to the data per each class, where the switches perform a priority control upon outputting the frames based on the class information and the output interface sequentially stores the frames outputted from the switches per each unique information and class information. 
         [0024]    [9] Also, in the above [1], the input order information may include a sequence number or time stamp. 
         [0025]    [10] Furthermore, in the above [9], if the sequence number is a number circulated within specified numerical values, the output interface may eliminate a frame stored after a first arrived frame by a fixed time which the sequence number can circulate, the frame stored and the first arrived frame have same sequence number. 
         [0026]    Namely, there is a possibility that depending on area size storing the sequence number, the same sequence number is added to different data. Even in this case, for accurately determining the earlier or later arrival of data, the output interface eliminates the stored frame (i.e. frame already determined if it arrived earlier or later) in a fixed time. 
         [0027]    [11] According to a further aspect of the invention, a data transmission method includes: a step of each of switches with redundancy outputting a frame in its input order; a step of input interfaces, each coupled to each switch, generating frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frames generated to the switches in parallel; and a step of at least one output interface sequentially storing the frames outputted from the switches for every unique information and selecting a first arrived frame among the frames stored with same input order information. 
         [0028]    [12] In the above [11] the output interface may store the frames in association with the switches having outputted the frames, determine that when the frames stored with the same input order information after a first specified time has lapsed from the selecting of the first arrived frame are detected, the switch corresponding to the frames detected is in a congested state and exclude following frames outputted from the switch in the congested state from being selected. 
         [0029]    [13] Also in the above [12] after the frames outputted from the switch in the congested state are excluded from the selecting and before a second specified time has lapsed from the selecting of the first arrived frame, when the frames outputted from the switch in the congested state and stored with the same input order information are detected, the output interface may determine that the congested state is released and includes following frames outputted out of the switch released from the congested state, as frames to be selected again. 
         [0030]    [14] Also in the above [12], the data transmission method further includes a step of a controller controlling the input interfaces and the output interface, wherein the output interface notifies information of the switch in the congested state to the input interfaces through the controller, thereby stopping the input interfaces from outputting the frames to the switch in the congested state. 
         [0031]    [15] Also in the above [14], the output interfaces may deem that the congested state is released when a second specified time has lapsed from the notification of the information of switch in the congested state and notify through the controller the information of the switch released from the congested state to the input interfaces, thereby restarting the input interfaces to output the frames to the switch released from the congested state. 
         [0032]    [16] Also in the above [12] the input interfaces and the output interfaces may be provided in pairs, in which one output interface having first determined the switch in the congested state notifies to one input interface forming a pair with the one output interface the information of the switch in the congested state to stop the one input interface from outputting the frames to the switch in the congested state and generates frames added with the information of the switch in the congested state to be provided to the other switches, thereby allowing the other output interfaces to determine the switch in the congested state and to notify the information of the switch in the congested state to the other input interfaces to stop the other input interfaces from outputting the frames to the switch in the congested state. 
         [0033]    [17] Also, in the above [16] the one output interface may deem that the congested state is released when a second specified time has lapsed from the notification of the information of switch in the congested state and notify the information of the switch released from the congested state to the one input interfaces to restart the one input interface to output the frames to the switch released from the congested state and add the information of the switch released from the congested state to the frames to be provided to each switch in parallel, thereby allowing the other output interfaces to determine the switch released from the congested state and to notify to the other input interfaces the information of the switch released from the congested state, thereby restarting the other input interfaces to output the frames to the switch released from the congested state. 
         [0034]    [18] Also, in the above [11] the input interfaces may classify the data into a plurality of classes based on specified information within the data and generate a frame in which class information, the unique information and the input order information are added to the data per each class, where the switches perform a priority control upon outputting the frames based on the class information and the output interface sequentially stores the frames outputted from the switches per each unique information and class information. 
         [0035]    [19] Also, in the above [11], the input order information may include a sequence number or time stamp. 
         [0036]    [20] Furthermore, in the above [19], if the sequence number is a number circulated within specified numerical values, the output interface may eliminate a frame stored after a first arrived frame by a fixed time which the sequence number can circulate, the frame stored and the first arrived frame have same sequence number. 
         [0037]    The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0038]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0039]      FIG. 1  is a block diagram depicting a schematic operation example in a case where no fault occurs in a switch in an embodiment [1] of a data transmission device and method; 
           [0040]      FIG. 2  is a block diagram depicting a schematic operation example in a case where a fault occurs in a switch in an embodiment [1] of a data transmission device and method; 
           [0041]      FIG. 3  is a block diagram depicting an arrangement of an embodiment [1] of a data transmission device and method; 
           [0042]      FIG. 4  is a frame format diagram used in an embodiment [1] of a data transmission device and method; 
           [0043]      FIG. 5  is a block diagram depicting an arrangement of a protection portion used in an embodiment [1] of a data transmission device and method; 
           [0044]      FIGS. 6A and 6B  are charts depicting respective arrangements of a data memory and a protection memory used in an embodiment [1] of a data transmission device and method; 
           [0045]      FIG. 7  is a flow chart depicting an operation of a protection manager used in an embodiment [1] of a data transmission device and method; 
           [0046]      FIG. 8  is a flow chart depicting a record holding time monitoring example in a protection manager used in an embodiment [1] of a data transmission device and method; 
           [0047]      FIG. 9  is a block diagram depicting a congestion information notifying example (1) of an embodiment [1] of a data transmission device and method; 
           [0048]      FIG. 10  is a block diagram depicting a congestion information notifying example (2) of an embodiment [1] of a data transmission device and method; 
           [0049]      FIG. 11  is a block diagram depicting a frame format example used in a congestion information notifying process example (2) of an embodiment [1] of a data transmission device and method; 
           [0050]      FIG. 12  is a block diagram depicting an arrangement of an embodiment [2] of a data transmission device and method; 
           [0051]      FIG. 13  is a diagram depicting a frame format example used in an embodiment [2] of a data transmission device and method; 
           [0052]      FIG. 14  is a block diagram depicting a related art example [1] of a data transmission device; and 
           [0053]      FIG. 15  is a block diagram depicting a related art example [2] of a data transmission device. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0054]    Embodiments [1] and [2] of a data transmission device and method according to the present invention will now be described referring to  FIGS. 1-13 . 
       Embodiment [1] 
     FIGS.  1 - 11   
     Schematic Operation Example 
     FIGS.  1  and  2   
       [0055]      FIG. 1  depicts a schematic operation example in a case where no fault occurs in both of the switches SW 0  and SW 1  within a data transmission device  1  according to an embodiment [1] of the present invention, and  FIG. 2  depicts a schematic operation example in a case where a fault occurs in the switch SW 0 . 
         [0056]    When as depicted by hatching in  FIG. 1 , three data DT 1 -DT 3  destined for a latter stage device (not depicted) of an output interface IFo_ 1  are sequentially inputted to an input interface IFi_ 1 , the input interface IFi_ 1  generates a frame FR 1  in which an IF No. of the output interface IFo_ 1  (ON)=“1”, an IF No. of its own (IN)=“1” and a sequence No. (SN)=“1” are added to the data DT 1  first inputted and provides it to the switches SW 0  and SW 1  in parallel. 
         [0057]    Then, the input interface IFi_ 1  generates frames FR 2  and FR 3  in which to the following data DT 2  and DT 3 , sequence Nos. (SN)=“2” and “3” respectively together with the output IF No. (ON)=“1” and the input IF No. (IN)=“1” are added respectively, and provides them sequentially to the switches SW 0  and SW 1  in parallel. 
         [0058]    Also, an input interface IFi_ 2  having received three data DT 4 -DT 6  destined for the output interface IFo_ 1  generates frames FR 4 -FR 6  in which to the data DT 4 -DT 6 , sequence Nos. (SN)=“1”-“3” together with the output IF No. (ON)=“1” and the input IF No. (IN)=“2” are added respectively, and provides them to the switches SW 0  and SW 1  in parallel. 
         [0059]    The switches SW 0  and SW 1  respectively provide the frames FR 1 -FR 6  in the order of input to the output interface IFo_ 1  corresponding to the output IF No. (ON)=“1”. 
         [0060]    Therefore, the output interface IFo_ 1  receives the frames FR 1 -FR 6  in parallel and in duplicate from the switches SW 0  and SW 1 , where according to the input IF No. (IN), as depicted in  FIG. 1 , the output interface IFo_ 1  stores separately the frames FR 1 -FR 3  generated by the input interface IFi_ 1  and the frames FR 4 -FR 6  generated by the input interface IFi_ 2 . Then, the output interface IFo_ 1  selects the first one circled among the same sequence No. (SN). 
         [0061]    Then, the output interface IFo_ 1  sequentially eliminates the output IF No. (ON), the input No. (IN) and the sequence No. (SN) from the selected frames FR 1 -FR 6  to reproduce the original data DT 1 -DT 6  and multiplexes the reproduced data DT 1 -DT 6  to be outputted to the latter stage. 
         [0062]    On the other hand, when a fault occurs in the switch SW 0  as depicted in  FIG. 2 , the frames FR 1 -FR 6  only from the switch SW 1  are outputted, so that the output interface IFo_ 1  selects all of the frames FR 1 -FR 6  for the switch SW 1  to be transferred in the form of the data DT 1 -DT 6 . 
         [0063]    Hereinafter, a specific arrangement and operation of the data transmission device for realizing the above will be described referring to  FIGS. 3-11 . 
       Arrangement: FIGS. 3-5 
       [0064]    The data transmission device  1  depicted in  FIG. 3  is composed of the duplexed switches SW 0  and SW 1 , an N number of interfaces IF_ 1 -IF_N (hereinafter, occasionally represented by a reference character IF) and a controller  10  for controlling the interface IF and the switch SW. 
         [0065]    The input interface IFi depicted in  FIGS. 1 and 2  corresponds to an input portion  100  of each interface IF and the output interface IFo corresponds to an output portion  200  of each interface IF, where the input portion  100  and the output portion  200  are provided in pairs. 
         [0066]    The input portion  100  is composed of an in-device header assigning portion no which assigns an in-device header HD to inputted data DT to generate a frame FR, and a copying processor  120  which copies the frame FR outputted from the in-device header assigning portion no to be provided to the switches SW 0  and SW 1  in parallel. 
         [0067]    It is to be noted that the above noted in-device header HD is composed of as depicted in  FIG. 4 , an IF No. of an output interface (output portion  200 ) (ON) that is a destination of the frame FR, an IF No. of an input interface (input portion  200  itself) (IN) and a sequence No. (SN) indicating the input order of the data DT, where instead of the sequence No. (SN) a time stamp indicating an input time of the data DT may be used. 
         [0068]    Also the output portion  200  is composed of frame sorting portions  210 _ 1  and  210 _ 2  respectively sorting the frame FR outputted from the switches SW 0  and SW 1  per each input interface (input portion too) according to the above noted input IF No. (IN), an N number of protection portions  220 _ 1 - 220 _N (hereinafter, occasionally represented by a reference numeral  220 ) which determine an earlier or later arrival of the frame FR outputted from the frame sorting portions  210 _ 1  and  210 _ 2  and reproduce the original data DT, and a multiplexer  230  which multiplexes the data DT outputted from the protection portions  220 _ 1 - 220 _N. 
         [0069]    Furthermore the protection portion  220  is composed of, as depicted in  FIG. 5 , an in-device header eliminator  221  which eliminates the in-device header HD from the frame FR outputted from the switches SW 0  and SW 1  (frame sorting portions  210 _ 1  and  210 _ 2 ) to reproduce the original data DT, an address manager  222  which generates a write address WA in response to the data DT outputted from the in-device header eliminator  221  and writes the data DT in the data memory MEM 1 , a sequence No. extraction-switch No. assigning portion  223  which extracts a sequence No. (SN) from the frame FR in parallel with the generation of the write address WA by the address manager  222  and assigns (outputs) a source switch No. (SWN) and a protection manager  224  which writes the write address WA outputted from the address manager  222  as well as the sequence No. (SN) and switch No. (SWN) outputted from the sequence No. extraction-switch No. assigning portion  223  in a protection memory MEM 2 , determines the earlier or later arrival of the frame FR by sequentially referring to the memory MEM 2  and provides a read address RA or cancel address CA through the address manager  222  to the memory MEM 1  to read or cancel the data DT. 
         [0070]    The protection manager  224  monitors a congested state of the switches SW 0  and SW 1  by referring to the memory MEM 2  and notifies the congestion information INFO {switch No. (SWN) and congested state (STS)} to the controller  10  and the input potion  200  within the same interface. 
       Operation Example: FIGS.  1 - 11   
       [0071]    Taking as an example a case where the data DT 1 -DT 3  depicted in  FIG. 1  are inputted to the input portion  100  within the interface IF_ 1  in  FIG. 3 , the in-device assigning portion no provides to the copying processor  120  a frame FR 1  generated by assigning to the data DT 1  the in-device header HD in which the output IF No. (ON)=“1”, the input IF No. (IN)=“1” and the sequence No. (SN)=“1” are set. 
         [0072]    The frame FR 1  is copied by the copying processor  120 , provided to the switches SW 0  and SW 1  in parallel and provided to the output portion  200  in the interface IF_ 1  through the switches SW 0  and SW 1 . 
         [0073]    Similarly, the frame FR 2  (ON=“1”, IN=“1”, SN=“2”), and the frame FR 3  (ON=“1”, IN=“1”, SN=“3”) are also sequentially provided to the output portion  200  in the interface IF_ 1 . 
         [0074]    The frame sorting portions  210 _ 1  and  210 _ 2  in the output portion  200  having received the frames FR 1 -FR 3  outputted from the switches SW 0  and SW 1  respectively provide the frames FR 1 -FR 3  to the protection portion  220 _ 1  according to the input IF No. (IN)=“1” sequentially. 
         [0075]    Now supposing that a frame has been inputted to the protection portion  220 _ 1  in the order of FR 1  (SW 0 ) (meaning the frame FR 1  from the switch SW 0 ; the same applying to the following)-&gt;FR 1  (SW 1 )-&gt;FR 2  (SW 1 )-&gt;FR 2  (SW 0 )-&gt;FR 3  (SW 0 )-&gt;FR 3  (SW 1 ), the in-device header eliminator  221  in the protection portion  220 _ 1  sequentially eliminates the in-device header HD from the frames FR 1 -FR 3  and provides the data to the data memory MEM 1  and the address manager  222  in the order of DT 1 -&gt;DT 1 -&gt;DT 2 -&gt;DT 2 -&gt;DT 3 -&gt;DT 3 . 
         [0076]    The address manager  222  writes the data DT 1 , DT 1 , DT 2 , DT 2 , DT 3 , DT 3  sequentially in addresses A 1 -A 6  of the data memory MEM 1  as depicted in  FIG. 6A  and provides the addresses A 1 -A 6  to the protection manager  224  as the write address WA. 
         [0077]    In parallel with this, the sequence No. extraction-switch No. assigning portion  223  provides the sequence No. (SN) and the switch No. (SWN) to the protection manager  224  in the order of {1,0 (SW 0 )}-&gt;{1,1 (SW 1 )}-&gt;{2,1}-&gt;{2,0}-&gt;{3,0}-&gt;{3,1}. 
         [0078]    The protection manager  224  writes the sequence No. (SN) and the switch No. (SWN) outputted from the sequence No. extraction-switch No. assigning portion  223  as well as the write address WA outputted from the address manager  222  at addresses B 1 -B 6  of the protection memory MEM 2  as depicted in  FIG. 6B . 
         [0079]    Also, the protection manager  224  performs the earlier/later arrival determination processing of the frames FR 1 -FR 3  by referring to the protection memory MEM 2  in asynchronization with the write processing in the protection memory MEM 2 . 
         [0080]    Namely, as depicted in  FIG. 7 , the protection manager  224  performs a periodical read by one record from the protection memory MEM 2  (step S 1 ). 
         [0081]    Then, the protection manager  224  determines the switch selection state managed inside (step S 2 ). In a double switch system (including the initial state) where no congestion occurs in the switches SW 0  and SW 1 , the protection manager  224  checks whether or not the same sequence No. (SN) as the sequence No. of the record read has been already stored in the protection memory MEM 2  (step S 3 ). 
         [0082]    Now supposing that the record of the head address  81  (sequence No. (SN)=“1”, switch No. (SWN)=“0” and write address WA=“A 1 ”) as depicted in  FIG. 6B  has been read, there is found by scan no record having the sequence No. (SN) of “1” before the reading, so that the protection manager  224  determines that the data stored at the address A 1  of the data memory MEM 1  is the first arrived data and executes the data reading to provide the address A 1  as the read address RA to the address manager  222  (step S 4 ). 
         [0083]    Accordingly, the data DT 1  is to be read from the address A 1  of the data memory MEM 1  depicted in  FIG. 6A . 
         [0084]    Then, the protection manager  224  starts up a timer TIM 1  in order to measure a delay of the data DT 1  later arrived (step S 5 ) and sequentially returns to the above step S 1 , where the record of the next address B 2  (sequence No. (SN)=“1”, switch No. (SWN)=“1” and write address (WA)=“A 2 ”) is read out of the protection memory MEM 2 . 
         [0085]    At this time, in the protection memory MEM 2  the record (address B 1 ) having stored therein the sequence No. (SN)=“1” already exists, so that the protection manager  224  determines at the above step S 3  that the data stored at the address A 2  of the data memory MEM 1  is later arrived data and checks whether or not the timer TIM 1  started up at the above step S 5  lapses or is timed out (step S 6 ). 
         [0086]    Now the later arrived data DT 1  succeeds the earlier arrived data DT 1 , so that the timer TIM 1  is not timed out and the protection manager  224  performs data discard processing (data discarding) in which the address A 2  is provided to the address manager  222  as the cancel address CA (step S 7 ). 
         [0087]    Therefore, the data DT 1  stored at the address A 2  of the data memory MEM 1  is not read but is to be discarded. 
         [0088]    The above steps S 1 -S 7  are repeatedly executed, whereby the earlier arrived data DT 2  and DT 3  stored at the addresses A 3  and A 5  of the data memory MEM 1  are read while the later arrived data DT 2  and DT 3  stored at the address A 4  and A 6  are discarded. 
         [0089]    Thus, from the protection portion  220  (i.e. the output portion  200 ) the data DT 1 -DT 3  are to be outputted in this order without duplication. 
         [0090]    On the other hand, when the timer TIM 1  is timed out at the above step S 6 , the protection manager  224  executes the data discarding (step S 8 ) as with the above step S 7  and determines that the switch corresponding to the switch No. (SWN) in the record read is in a congested state, thereby transitioning to a single switch system state where the frame FR outputted from the switch should not be selected (step S 9 ). 
         [0091]    At this time, the protection manager  224  executes notifying the congestion information INFO (hereinafter, referred to as congestion information notifying) of the switch to the input portion  100  within each interface IF as will be described later. 
         [0092]    It is to be noted that in a case where the data DT is a segment of a fixed length inputted at fixed intervals, instead of the above timer TIM the delay may be estimated by counting the record number (i.e. the number of the other data) between the earlier arrived data—the later arrived data. 
         [0093]    Sequentially having read the record from the protection memory MEM 2 , the protection manager  224  checks whether or not the switch No. (SWN) in the record is consistent with a switch in the congested state (step S 10 ). 
         [0094]    When the switch No. (SWN) is not consistent with the switch in the congested state, the protection manager  224  executes the data read processing by using the write address WA in the record read (step S 11 ) and starts up a timer TIM 2  in order to measure the delay of the frame FR outputted from the switch in the congested state and stored with the same sequence No. (SN) (step S 12 ), where this timer TIM 2  may be replaced by one the same one as the above timer TIM 1 . 
         [0095]    When at the above step S 10  the switch No. (SWN) in the record read out of the protection memory MEM 2  is consistent with the switch in the congested state, the protection manager  224  checks whether or not the timer TIM 2  started up at the above step S 12  is timed out (step S 13 ). 
         [0096]    When the timer TIM 2  is already timed out, the protection manager  224  determines that the switch is still in the congested state and executes the data discarding (step S 14 ). 
         [0097]    When the timer TIM 1  is not timed out, the protection manager  224  executes the data discarding (step S 15 ) and determines that the congested state of the switch is released or resolved and transitions to the double-system state again (step S 16 ). 
         [0098]    Also, every time reading of the record from the protection memory MEM 2  at the above step S 1 , the protection manager  224  executes record holding time monitoring depicted in  FIG. 8  (step S 20 ). 
         [0099]    Namely, the protection manager  224  starts up a record holding timer TIM 3  for a record every time the record in the protection memory MEM 2  is used for determining the earlier or later arrival (step S 21 ). 
         [0100]    The protection manager  224  holds the record until the timer TIM 3  is timed out (step S 22 ) and cancels it when the timer TIM 3  is timed out (step S 23 ). 
       Congestion Information Notification Processing Example (1): FIG. 9 
       [0101]    Upon transitioning to the single-system state at step S 9  depicted in  FIG. 7 , the protection manager  224  notifies the congestion information INFO in which the switch No. (SWN) of the switch in the congested state and the congested state STS (congestion occurrence) are set to the copying processor  120  in the interface IF_ 1  and the controller  10  as depicted in  FIG. 9 . 
         [0102]    In response, the copying processor  120  in the interface IF_ 1  stops copying the frame FR and outputting the frame FR to the switch corresponding to the switch No. (SWN) notified. 
         [0103]    The controller  10  transfers the congestion information INFO to each copying processor  120  within the other interfaces IF_ 2 -IF_N, whereby each copying processor  120  within the interfaces IF_ 2 -IF_N stops outputting the frame FR to the switch in the congested state in the same manner as the copying processor  120  within the interface IF_ 1 . 
         [0104]    Then in a specified time interval, the protection manager  224  deems that the congested state of the switch is released, notifying the congestion information INFO in which the switch No. (SWN) and the congested state (STS) (congestion released) are set to the copying processor  120  within the interface IF_ 1  and the controller  10 . 
         [0105]    Thus, each copying processor  120  within the interfaces IF_ 1 -IF_N restarts outputting the frame FR to the switch in the congested state released. 
         [0106]    It is to be noted that as in the following congestion information notifying example (2), the congestion information INFO may be notified without involving the controller  10 . 
       Congestion Information Notification Processing Example (2): FIGS. 10 and 11 
       [0107]    As depicted in  FIG. 10 , the protection manager  224  in the interface IF_ 1  notifies the congestion information INFO to the in-device header assigning portion  100  in the interface IF_ 1 , different from the above processing example (1). 
         [0108]    In response, the in-device header assigning portion  110  generates a frame FRa in which the congestion information INFO is further set in the in-device header HD as depicted in  FIG. 11  and provides it to the copying processor  120 . The copying processor  120  identifies the switch SW 0  uncongested from the congestion information INFO in the frame FRa as depicted in  FIG. 10  and provides as an output the frame FRa. 
         [0109]    Each protection manager  224  in the other interfaces IF_ 2 -IF_N having received the frame FRa from the switch SW 0  notifies the congestion information INFO to each copying processor  120 . 
         [0110]    Thus, each copying processor  120  in the interfaces IF_ 1 -IF_N is stopped to output the frame to the switch SW 1  in the congested state. 
         [0111]    Then in a specified time interval, the protection manager  224  in the interface IF_ 1  deems that the congested state of the switch SW 1  is released in the same manner as the above processing example (1) and notifies the congestion information INFO where the switch No. (SWN (1)) and the congested state (STS) (congestion released) are set to the in-device header assigning portion  110 . 
         [0112]    The in-device header assigning portion no generates the frame FRa in which the congestion information INFO is set and provides it to the copying processor  120 , which further provides the frame FRa to the switches SW 0  and SW 1  in parallel. 
         [0113]    Thus, each copying processor  120  within the other interfaces IF_ 2 -IF_N recognizes that the congested state of the switch SW 1  is released and restarts outputting the frame to the switch SW 1 . 
       Embodiment [2] 
     FIGS.  12  and  13   
       [0114]    The input portion  100  of the data transmission device  1  depicted in  FIG. 12  includes, in addition to the arrangement of the above embodiment [1], an n class classifier  130  for classifying the data DT into an n number of classes (priorities) based on specified information in the data DT inputted, in which there are correspondingly provided an n number of in-device header assigning portions  110 _ 1 - 110 _n and an n number of copying processors  120 _ 1 - 120 _n. Also, the input portion  100  has multiplexers  140 _ 1  and  140 _ 2  which respectively multiplex the frame FR outputted from the copying processor  120 _ 1 - 120 _n to be provided to the switches SW 0  and SW 1 . 
         [0115]    Also in the output portion  200 , there are provided an m (interface number N * class number n) of protection portions  220 _ 1 - 220 _m. 
         [0116]    In operation, the n class classifier  130  provides the data DT to any one of the in-device header assigning portions  110 _ 1 - 110 _n in accordance with e.g. a source address, a destination address (not depicted) or the like in the data DT. 
         [0117]    The in-device header assigning portions  110 _ 1 - 110 _n respectively generate the frame FR in which a class CL preliminarily assigned to itself is set in the in-device header HD as depicted in  FIG. 13 . 
         [0118]    The copying processor  120 _ 1 - 120 _n respectively copy the frame FR outputted from the in-device header assigning portions  110 _ 1 - 110 _n to be provided to the multiplexers  140 _ 1  and  140 _ 2  in parallel. 
         [0119]    Thus, the frame FR outputted from the copying processors  120 _ 1 - 120 _n is multiplexed by the multiplexers  140 _ 1  and  140 _ 2  and then provided to the switches SW 0  and SW 1  respectively. 
         [0120]    The switches SW 0  and SW 1  respectively performs a priority control (such as a control to output the frame FR where a class CL with a higher priority is set in prior to the frame with a lower priority class CL) based on the class CL in the frame FR and provides it to the output portion  200  in the interface corresponding to the output IF No. (ON). 
         [0121]    The frame sorting portions  210 _ 1  and  210 _ 2  within the output portion  200  respectively sort the frame FR per input IF No. (IN) and class CL to be provided to one of the protection portions  220 _ 1  and  220   —   m.    
         [0122]    Thus, in each in the protection portions  220 _ 1 - 220 _m, as with the above embodiment [1], the earlier or later arrival determination processing of data and congested state monitoring processing of switch are to be performed. 
         [0123]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.