Abstract:
A circuit and method for regulating a voltage by means of a switched capacitor circuit including multiple switches and capacitors. The circuit is operable in a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels. In addition, the circuit provides lower output ripple than conventional charge pumps.

Description:
The present invention relates to switching regulator circuits, and more particularly, to circuits and methods for maintaining high efficiency and low noise over broad current ranges in an inductorless, step-down, switching regulator circuit. 
     BACKGROUND OF THE INVENTION 
     There are three important trends affecting the electronics industry: device miniaturization, declining supply voltages, and an increasing use of battery-power. These trends place great demands on power supply circuitry in miniature, battery powered, electronic devices, such as cellular telephones and personal digital assistants (PDA&#39;s). Miniaturization places limits on circuit size; a reduced supply voltage places stringent requirements on reducing supply ripple to provide adequate noise immunity for integrated circuits; and reliance on battery-power drives a need for high efficiency for prolonged battery life. 
     The purpose of a voltage regulator is to provide a predetermined and constant output voltage to a load from a poorly-specified or fluctuating input voltage source. Series regulators and switching regulators are two common types of voltage regulators. Low drop out (“LDO”) series regulators provide good regulation with very low noise, however, the current supply from the regulated output comes directly from the voltage source. Thus, the best efficiency possible from a LDO regulator is the ratio of the output voltage to the supply voltage which drops rapidly for supply voltages much larger than the output voltage. 
     Switching regulators are generally more efficient than series regulators. A switching regulator employs one or more switches (e.g., a power transistor) coupled either in series and/or parallel with the load. A control circuit turns the switches ON and OFF to transmit power to the output in discrete current pulses. An energy storage element, such as an inductor or capacitor, is used to convert the switched current pulses into a steady load current. Because inductors tend to be large components, switched capacitor converters are preferred in miniaturized devices. 
     In a conventional switched capacitor regulator, a capacitor is charged from the input voltage during a first part of a switch cycle and the charge is transferred to the output during a second part of the switch cycle. This cycle by cycle transfer of charge to the output produces ripple on the output. Furthermore, because charge is transferred during only a portion of a switch cycle, the regulator must be designed to supply much more charge per cycle than is typically required at the output. This can result in output ripple becoming unacceptably large under certain conditions. A couple hundred mV of ripple is not uncommon. 
     A feedback loop may be provided to regulate the output voltage by controlling operation of the switches to regulate the rate at which charge is transferred to the output. In a first type of switched capacitor regulator, the duration of a portion of the switching cycle is kept constant while the duration of the remaining portion of the switching cycle is changed. For example, the length of time during which charge is transferred to the output may be kept constant, while the length of time during which the capacitor is charged from the input is varied. This has the side effect of causing the frequency of a switching cycle to vary as a function of the output current. Because output ripple frequency is determined by the switching frequency, it too varies as a function of the output current making filtering the ripple more difficult. 
     In an alternative type of switched capacitor regulator, the duty cycle of a switching cycle is changed without changing the switching frequency. Constant frequency switched capacitor regulators generally provide lower output noise than variable frequency switching regulators by transferring only the amount of current necessary to keep the output in regulation on a cycle by cycle basis. 
     When a constant frequency switched regulator is supplying close to its rated output current, the efficiency of the overall circuit can be high. However, the efficiency is a function of output current and typically decreases at low output current due to the losses associated with operating the switching regulator. These losses include, among others, quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses and the like. 
     It would therefore be desirable to provide DC/DC converter circuitry having high-efficiency. 
     It would also be desirable to provide DC/DC converter circuitry having low output voltage ripple. 
     It would also be desirable to provide DC/DC converter circuitry having an output voltage ripple with a substantially constant frequency. 
     In addition, it would be desirable to maintain high efficiency over broad current ranges, including low output currents, in a switching regulator circuit. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide DC/DC converter circuitry having high-efficiency. 
     It is also an object of the present invention to provide DC/DC converter circuitry having low output voltage ripple. 
     It is also an object of the present invention to provide DC/DC converter circuitry having an output voltage ripple with a substantially constant frequency. 
     In addition, it is an object of the present invention to maintain high efficiency over broad current ranges, including low output currents, in a switching regulator circuit. 
     These and other objects and advantages of the invention are provided by a switched capacitor converter having a number of switches and capacitors. The converter is operable in different modes to provide different step-down conversion ratios. Mode control circuitry selects the step-down conversion ratio to optimize efficiency as input voltage and load conditions vary. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
     FIG. 1 is a simplified block diagram of a switching regulator circuit of the present invention; 
     FIG. 2 is a simplified schematic of the step-down charge pump and current control circuitry of FIG. 1; and 
     FIG. 3 is a simplified schematic of the switch/mode control circuitry of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring first to FIG. 1, circuit  10  accepts an input voltage, V IN , at terminal  12  and provides a regulated DC output voltage, V OUT , at terminal  14  for driving load  16 . For example, load  16  may be cellular telephone circuitry requiring a 1.5 volt regulated supply and V IN  may comprise a 3.6 volt battery. Circuit  10  includes step-down charge pump  18 , mode control circuit  20 , and current control circuitry  22 . In addition, circuit  10  includes resistors  26   a  and  26   b,  voltage reference  27 , and amplifiers  24  and  28  to provide feedback to mode control circuitry  20  and current control circuitry  22   
     To reduce ripple in the output voltage, an output capacitor  15  is often connected to output terminal  14 . Typically, capacitor  15  has a large value to keep output ripple low. Resistor  17  represents the effective series resistance of capacitor  15 . Although not shown in FIG. 1, additional resistors or capacitors may be used to further filter the output voltage and reduce ripple. As is known in the art, the values of these components must be considered when designing a feedback loop for the regulator circuit of FIG.  1 . 
     Typically, a switched capacitor regulator is constructed using an integrated circuit controller with a few external components. The LT1054 Switched Capacitor Voltage Converter with Regulator, sold by Linear Technology Corporation, Milpitas, Calif., is such an integrated circuit controller for a switched capacitor converter and regulator. With the addition of external components, such as capacitors, resistors, diodes, or transistors, the LT1054 may be used to create many different types of voltage converters. For example, the data sheet for the LT1054, which is incorporated herein by this reference, includes sample circuits for voltage doublers, voltage inverters, voltage converters, and a digitally programmable voltage supply. 
     Referring now to FIG. 2, step-down charge pump  18  comprises a number of capacitors and switches coupled between input terminal  12  and output terminal  14 . The switches are operated in a predetermined sequence to transfer charge from a voltage source at input terminal  12  to the capacitors and then from the capacitors to the output at output terminal  14 . In accordance with the principles of the present invention, the switches are operated so as to control the amount of charge transferred from input terminal  12  to output terminal  14  and thereby regulate the output voltage. 
     Exemplary step-down charge pump  18  includes capacitors  30   a  and  30   b  and switches S 1 -S 7 . Preferably, switches S 1 -S 7  are MOSFET transistors although other types of switches may be used. Also shown in FIG. 2 are MOSFETs  40   a  and  40   b  configured as an inverter  41  and MOSFETs  42   a  and  42   b  configured as a current mirror  43 . 
     In accordance with the principles of the present invention, step-down charge pump  18  may be operated in different modes, wherein a mode of operation is selected to improve the efficiency of the switched capacitor regulator. 
     In a first mode of operation, referred to herein as a “1-to-1”mode, switches S 2 -S 7  are kept open, and switch S 1  is closed. A clock signal, CLK, is applied to the gates of MOSFETs  40   a  and  40   b . When the clock signal is HIGH, MOSFET  40   a  is turned OFF and MOSFET  40   b  is turned ON. Transconductance amplifier  45  sinks current from V IN  at input terminal  12  through MOSFETs  42   a  and  40   b . Because MOSFETS  42   a  and  42   b  are configured as current mirror  43 , MOSFET  42   b  conducts a current approximately equal to the current through MOSFET  42   a  multiplied by the current mirror gain factor. This current is supplied via switch S 1  and output terminal  14  to the output, including output capacitor  15  and load  16 . 
     When the clock signal, CLK, is LOW, MOSFET  40   a  turns ON and MOSFET  40   b  turns OFF, causing MOSFETs  42   a  and  42   b  to turn OFF. As a result, no current flows through MOSFET  42   a  or  42   b . Load current is supplied from output capacitor  15 . 
     A voltage divider formed from resistors  46   a  and  46   b  provides a voltage at node  32  proportional to the output voltage V OUT . The output of transconductance amplifier  45  is a function of the difference between the voltage at node  32  and the reference voltage, V REF . When the voltage at node  32  is less than V REF , indicating that the output voltage is low, transconductance amplifier  45  sinks more current from MOSFETS  40   b  and  42   a  when clock signal CLK is LOW. Because of the current mirror configuration of MOSFETS  42   a  and  42   b , MOSFET  42   b  provides increased current to the output, thereby raising the output voltage, V OUT . Conversely, when the voltage at node  32  is higher than V REF , transconductance amplifier  45  sinks less current when the clock signal is LOW and MOSFET  42   b  provides reduced current to the output, thereby lowering V OUT . 
     When regulating, the voltage regulator of the present invention operates so that the average current supplied by current mirror  43  is equal to the average output current. In this mode of operation V OUT  is less than V IN  by the voltage drops across switch S 1  and MOSFET  42   b  due to the output current. The regulator has an effective output impedance given by:                R   out     =     GM   ×   N   ×       R     46      b           R     46      a       +     R     46      b           ×   DC             (   1   )                                
     where: 
     GM is the gain of transconductance amplifier  45 , 
     N is the mirror gain factor for current mirror  43 , 
     R 46   a  and R 46   b  are the values of resistors  46   a  and  46   b , respectively, and 
     DC is the duty cycle of the clock signal. 
     The mode of circuit operation just described is referred to as 1-to-1 mode because the ratio of average input current to average output current is about 1 to 1 when the output voltage is being regulated. In a second mode of operation, step-down charge pump  18  operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (⅔) the average output current. In the 3-to-2 mode, switches S 1 -S 7  are controlled so that switches S 1 , S 3 , and S 6  are ON and switches S 2 , S 4 , and S 7  are OFF when the clock signal (CLK) is LOW. Conversely, switches S 1 , S 3 , and S 6  are OFF and switches S 2 , S 4 , and S 7  are ON when the clock signal is HIGH. Switch S 5  remains OFF. 
     When CLK is HIGH, the current output of amplifier  45  is amplified by current mirror  43  which supplies current to V OUT . Current mirror  43  also supplies current to capacitors  30   a  and  30   b  which are effectively connected in parallel between MOSFET  42   b  and output terminal  14 . When CLK goes LOW, capacitors  30   a  and  30   b  are connected in series between output terminal  14  and ground, and the charge stored on the capacitors is transferred to the output. Because current flows during both halves of a CLK cycle the efficiency of step-down converter  18  is improved. 
     In the 3-to-2 mode of operations, when the output voltage is being regulated, the average current through MOSFET  42   b  equals two-thirds (⅔) the average output current. Because the average input current is less than the average input current in 1-to-1 mode, the efficiency of the regulator is improved when the voltage regulator can be operated in the 3-to-2 mode. Losses in MOSFET  42   b  and switches S 1 -S 7 , and the required load current, determine how low V IN  may be with respect to V OUT  while maintaining adequate voltage regulation in 3-to-2mode. However, when V IN  is greater than about 1.5×V OUT  the circuitry of FIG. 2 may be operated in 3-to-2 mode for improved efficiency. 
     The effective output impedance of switched capacitor step-down charge pump  18  in the 3-to-2 mode of operation is given by:                R   out     =       3   4     ×   GM   ×   N   ×       R     46      b           R     46      a       +     R     46      b                     (   2   )                                
     To achieve a further improvement in efficiency, switched capacitor step-down charge pump  18  may also be operated in a “2-to-1” mode when V IN  is greater than about twice V OUT . In the 2-to-1 mode, switches S 1  and S 5  are ON and switch S 2  is OFF when CLK is LOW, and switches S 1  and S 5  are OFF and switch S 2  is ON when CLK is HIGH. Switches S 3 -S 4 , and S 6 -S 7  are kept off. When CLK is LOW, current flows from V IN  to V OUT  through MOSFET  42   b  and switch S 1 . Current is also provided to charge capacitor  30   a . When CLK goes high, the charge stored on capacitor  30   a  is transferred to V OUT  at output terminal  14 . The effective output impedance of switched capacitor step-down charge pump  18  in the 2-to-1 mode of operation is given by:                R   out     =     GM   ×   N   ×       R     46      b           R     46      a       +     R     46      b                     (   3   )                                
     A regulator according to the principles of the present invention is operable in a plurality of modes, e.g., 1-to-1 mode, 3-to-2 mode, or 2-to-1 mode, to provide improved operating efficiency over a wide range of input voltages. The optimum mode of operation is determined by the ratio of the input and output voltages, e.g., V IN  to V OUT , as well as, by switch losses and the actual output current. In one embodiment of a regulator in accordance with the principles of the present invention, a specific mode of operation may be preselected and fixed by a circuit designer by appropriately biasing configuration pins on a regulator controller integrated circuit. However, in a preferred embodiment of the present invention, the optimum mode of operation is automatically determined by switch/mode control circuitry  20  of FIG.  1 . FIG. 3 is a schematic representation of an illustrative implementation of switch/mode control circuit  20 . 
     Switch/mode control circuitry  20  includes resistors  50   a - 50   c  and comparators  52   a  and  52   b . Resistors  50   a - 50   c  form a voltage divider network that provides voltage signals for determining the most efficient mode of operation of regulator circuit  10 . The voltage signals are provided to inputs of corresponding comparators  52   a  and  52   b . The other input to comparators  52   a  and  52   b  is provided by reference voltage, V REF  in series with an offset voltage  51  (V OFF ) that is proportional to the output current load. Resistors  50   a-c  are chosen so that one or both of comparators  52   a  and  52   b  will be on at the appropriate voltages on input  12 . Specifically, both comparators are off when          V   IN     &lt;       (       V   REF     +     V   OFF       )     ×     (     1   +       R     50      a           R     50      b       +     R     50      c             )                              
     which corresponds to the conditions under which the regulator should be operated in 1-to-1 mode. When          V   IN     ≥       (       V   REF     +     V   OFF       )     ×     (     1   +         R     50      a       +     R     50      b           R     50      c           )                              
     both comparators are on; which corresponds to the conditions in which the regulator should be operated in 2-to-1 mode. For intermediate input voltages, comparator  52   a  is off and comparator  52   b  is on, indicating that a 3-to-2 mode of operation would be most efficient. 
     However, as described previously, the optimal mode of operation is dependent not only on the input and output voltages, but also on voltage drops caused by the on resistance of switches S 1  through S 7  and the average load current. This variation is taken into account by offset voltage  51  (V OFF ) which is a function of the current feedback signal. The function is set to optimize the mode switching point for any given load condition. As the load current increases, the current feedback signal and the offset voltage also increase. This raises the input voltage at which the operational mode of regulator  10  changes from 1-to-1 mode, to 3-to-2 mode, and then to 2-to-1 mode. 
     Exemplary switching logic circuitry  54  combines the mode signals provided by comparators  52   a  and  52   b  with timing signals, CLKA and CLKB, to operate switches S 1 -S 7  according to the proper mode of operation. For example, when comparators  52   a  and  52   b  are both off, switching logic circuitry  54  provides a signal turning switch S 1  ON. This corresponds to the 1-to-1 mode of operation. Otherwise, if one or both of comparators  52   a  and  52   b  are OFF, switch S 1  is driven by the CLKB signal. Switches S 2 -S 7  are controlled by switching logic circuitry  54  in an analogous manner. 
     Non-overlap clock generator  55  produces the clock signals CLKA and CLKB, such that there is a “blanking”period from one signal going low to the other signal going high. A blanking period is desirable to ensure that operation of switches S 1 -S 7  do not result in shorting the switching nodes together, such as the output voltage, V OUT , to ground. There are many means of designing a non-overlap clock generator, such as non-overlap clock generator  55 , to ensure that all switches are turned off prior to turning any switches on, as one skilled in the art would know. Preferably, the CLKA signal is also used as the CLK signal of FIG.  2 . 
     Connected to the reset signal of the non-overlap clock generator  55 , is comparator  56 . When the output of comparator  56  is high, the non-overlap clock generator operates as described previously. When the output of comparator  56  is low, the clock generator is forced into a static state, where the signal CLKA is held low. If signal CLKA is held low, no switching of switches S 1 -S 7  takes place, which stops the charge transferred from the input  12  to the output  14 . By stopping the switching and shutting down portions of the regulator circuit, efficiency at low output currents can be significantly improved. Comparator  56  goes low when the current feedback offset voltage  51  drops below a threshold voltage  57 , signaling a light output load, which disables the switching as described above. As the output load  16  discharges capacitor  15 , the output will drop, and the current feedback voltage will rise eventually causing the output of comparator  56  to return high, enabling the clock circuit  55  and charge transfer. This is similar to the operation of a conventional regulator, but unlike a conventional regulator, the amount charge transferred when coming out of burst mode is set by the threshold of comparator  56 , effectively limiting the amount of charge transferred, which in turn limits the size of the output ripple voltage. Thus, a means for improved efficiency at light loads is achieved without producing excessive output ripple. 
     Additionally there are many means for providing output short circuit or over current protection. One simple means is to limit the amount of current the transconductance amplifier  45  can sink. By limiting of the amount of current sunk by transconductance amplifier  45 , the current out of mirror transistor  42   b  is limited which in turn limits the effective output current. There are many means by which this may be accomplished as one skilled in the art would know. 
     Thus, an inductorless DC/DC regulator circuit and a method for maintaining high efficiency over broad current ranges has been provided. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.