Abstract:
A device suitable for charging a battery includes at least a first and a second transistor. The transistors are connected to an input voltage and have output terminals; the output terminal of the first transistor is connected to the battery. The device comprises a circuit for driving the transistors and the drive circuit comprises a regulator suitable for regulating the current in the battery during the charging phase of the battery. The regulator is suitable for keeping the voltage on the output terminals of the transistors the same during the charging phase of the battery.

Description:
BACKGROUND 
     1. Technical Field 
     The present invention refers to a battery-charging device. 
     2. Description of the Related Art 
     Battery chargers are generally known in the state of the technique, for example cellular telephone batteries, as batteries of the lithium ion type. 
     The charging of these batteries comes about according to a known constant current (CC) and constant voltage (CV) procedure. During the battery charging phase the charger works according to a current regulation procedure, that is a constant current is supplied to the battery. In the meantime the voltage on the battery grows until it reaches its steady state charge value; in proximity of this value, the charge current starts diminishing until it nullifies itself and the charger enters the voltage regulation phase, that is the battery is supplied with a constant voltage. 
     Generally in this procedure high precision of the regulated current as well as the regulated voltage are important. The values generally are 10% for the charge current and 1% for the regulated voltage. In addition, one should make sure that the temperature of the device does not exceed the thermal limits also depending on the charger device used. 
     Among the various types of battery charger devices one that is generally used is shown in  FIG. 1 . 
     The device comprises means CA, D 2  suitable for regulating the current of a battery LOAD, means VA, D 1  suitable for regulating the voltage and means PA, D 3  suitable for regulating the power. 
     The device comprises a couple of PMOS transistors M 1  and M 2  having the source terminal connected to an input voltage Vin; the drain terminal of the transistor M 2  is connected to the battery LOAD having its other terminal connected to ground and the drain terminal of the transistor M 1  is connected to the source terminal of a transistor M 3 . The latter has the drain terminal connected to a resistor R having its other terminal connected to ground. The gate terminal of the transistor M 3  is driven by an operational amplifier  1  having the inverting and non-inverting input terminals connected respectively to the drain terminals of the transistors M 1  and M 2 . 
     A current generator  11  and the cathodes of the diodes D 1 -D 3 , having the anodes connected to the respective operational error amplifiers VA, CA and PA, are connected to the gate terminals of the transistors M 1  and M 2 . The amplifier VA has in input on the inverting terminal a reference voltage Vref and on the non-inverting terminal the voltage Vout at the terminals of the battery LOAD, the amplifier CA has in input on the inverting terminal a reference voltage V 1  and on the non-inverting terminal the voltage Vout and the amplifier PA has in input on the inverting terminal the temperature of the charger device Tdie and on the non-inverting terminal a reference temperature Tref. 
     During the charging phase of the battery LOAD there is the current regulation phase; the control of the PMOS transistors M 1  and M 2  is carried out by the error amplifier CA because the error amplifier VA is unbalanced, the voltage Vout being less than the voltage Vref. When the voltage Vout reaches the voltage Vref, the control of the transistors M 1  and M 2  passes to the amplifier VA that supplies all the current needed to directly bias the diode D 1  while the diode D 2  is cut off. 
     If the temperature of the charger device is higher than the reference temperature Tref, the control passes to the amplifier PA that directly biases the diode D 3 . 
     So that the regulated current on the charge is very precise the voltages between drain and source of the MOS transistors M 1  and M 2  have to be equal to each other. As both the MOS transistors have the same voltage between the gate and source terminals, the charge current is equal to that of reference 
               V   ⁢           ⁢   1     R         
multiplied by the ratio of the areas of the MOS transistors M 1 , M 2 . For this reason the amplifier  1  is introduced to maintain the drain terminals of the transistors M 1  and M 2  at the same potential.
 
     BRIEF SUMMARY 
     One embodiment of the present invention is a battery-charging device that has a simpler circuitry than that of known chargers and that in addition has greater precision. 
     One embodiment of the present invention is a device suitable for charging a battery comprising at least a first and a second transistor, said transistors being connected to an input voltage and having output terminals, the output terminal of said first transistor being connected to said battery. The device includes a drive circuit of said transistors, said drive circuit comprising a regulator suitable for regulating the current in said battery during the charging phase of said battery, the regulator being suitable for keeping the voltage on the output terminals of said transistors the same during the charging phase of said battery. 
     The battery charging device can be produced which has a lower number of components and a lower occupation of area in the chip where the device is integrated. With said device we also have high precision in the phases of regulating the current and the voltage in the battery. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The characteristics and the advantages of the present invention will appear evident from the following detailed description of an embodiment thereof, illustrated as non-limiting example in the enclosed drawings, in which: 
         FIG. 1  shows a battery charger in accordance with the known art; 
         FIG. 2  shows a diagram of a battery charger according to one embodiment the present invention; 
         FIG. 3  shows a circuit implementation of the battery charger of  FIG. 2 ; 
         FIG. 4  shows the diagrams of the time trend of the voltage Vout, of the output current lout and of the temperature Tp in the charging phase of the battery obtained with the device of  FIG. 3  in the case that no regulation of the temperature is carried out; 
         FIG. 5  is an enlargement of a part of the diagram of the time path of the current lout of  FIG. 4 ; 
         FIG. 6  shows the diagrams of the time trend of the voltage Vout, of the output current lout and of the temperature Tp in the charging phase of the battery obtained with the device of  FIG. 3  in the case that regulation of the temperature is carried out. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to  FIG. 2  a diagram of a battery-charging device according to one embodiment of the present invention is shown. The device comprises a couple of PMOS transistors M 10  and M 20  having the source terminal connected to an input voltage Vin. The drain terminal of the transistor M 10  is connected to the battery LOAD having its other terminal connected to ground. The charging device comprises a circuit  100  suitable for driving the gate terminals of the transistors M 10  and M 20 . The drain terminal of the transistor M 20  is also connected to circuit  100 ; more precisely said terminal is connected to the drain terminal of a transistor M 30  being part of a current mirror M 30 -M 31 . Said current mirror is suitable for mirroring on the transistor M 10  the current  130  proportional to the current Iref coming from a homonymous current generator. The latter is controlled by an operational amplifier PA 1  having in input on the inverting terminal the reference voltage Vref 2  and on the non-inverting terminal a voltage V(T) proportional to the temperature of the device; the voltage V(T) is produced by a device  2  that is sensitive to the temperature. When the temperature of the device increases and the voltage V(T) becomes the same as the voltage Vref 2 , the amplifier PA 1  acts commanding a decrease of the current Iref. Consequently the current  130  and the charge current that flows in the transistor M 10  are also decreased. Consequently the power dissipated in the transistor M 10  decreases and this also makes the temperature of the device decrease; the intervention of the amplifier PA 1  occurs until the balance between the temperature of the device and the current in transistor M 10  that produces this temperature is reached. 
     The drain terminals of the transistors M 10  and M 20  are connected to the non-inverting and inverting input terminals of an operational error amplifier CA 1  belonging to the drive circuit  100 . The output of the amplifier CA 1  converges with the output of an operational error amplifier VA 1  on a circuit block CVA whose output signal is suitable for driving the transistors M 10  and M 20 . The amplifier VA 1  has in input on the inverting terminal a reference voltage Vref 1  and on the non-inverting terminal the voltage Vout at the terminals of the battery LOAD. The non-inverting input of the amplifier CA 1  is connected to the terminal being regulated, that is the drain terminal of the transistor M 10 : in this manner the loop constituted by the amplifier CA 1 , by the circuit block CVA and by the transistors M 10  and M 20  being in equilibrium, maintains the voltages on the drain terminals of the transistors M 10  and M 20  at the same value for the whole time in which the voltage Vout grows towards its steady state value Vref, without the need to provide a further amplification stage. The regulated current is thus exactly the same as the reference current Iref multiplied by the ratio of the areas of the MOS transistors M 10  and M 20 . The circuit block CVA is equivalent to an adder node whose output signal coincides with the output signal from the amplifier CA 1  or with the output signal from the amplifier VA 1  when one or the other are active. The amplifier CA 1  has a bias current Ipol controlled by the output signal of the amplifier VA 1 . During the current regulation, the voltage Vout increases until it reaches the reference value Vref 1 . When this comes about, the system gradually reduces the bias current Ipol of the stage CA 1  to zero so that the active regulation loop becomes that of voltage, constituted by the amplifier VA 1 , by the block CVA and by the MOS transistors M 10  and M 20 . 
     A circuit implementation of the device of  FIG. 2  is shown in  FIG. 3 . When the battery LOAD is discharged, the voltage Vout is less than the reference voltage Vref, the amplifier VA 1  is unbalanced and the error amplifier CA 1  is biased by the current Ipol by means of the mirrors formed by the PMOS transistors M 41 -M 42  and by the NMOS transistors M 43 -M 44 . This current is also mirrored in the NMOS transistor M 49 , at the output of the stage CVA, by means of NMOS transistor mirrors M 44 -M 45 , PMOS transistor mirrors M 46 -M 47  and NMOS transistor mirrors M 48 -M 49 . 
     The differential stage of the amplifier CA 1 , constituted by the PMOS transistors M 51 -M 52  whose gate terminals are connected to the drain terminals of the transistors M 20  and M  10 , sees to regulating the charge current in the battery LOAD by means of transistor mirror M 53 -M 54  which, sending the signal to the output stage CVA, generates in the transistor M 55 , by means of the current mirror M 60 -M 55 , a current that balances the current of the transistor M 49 ; in this manner the equilibrium of the currents is obtained. The drain terminal of the transistor M 51  is connected to a transistor M 61  in diode connection, connected in turn to ground. 
     The amplifier VA 1  comprises a differential stage with PMOS transistor M 62 -M 63 ; on the gate terminals of said transistors there are respectively a part of the voltage Vout given by 
               Vout   ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2             
and the reference voltage Vref 1 . The source terminals of the transistors M 62  and M 63  are connected to a generator of the bias current Ipol and the drain terminals are connected respectively to the drain terminals of the transistors M 44  and M 56 .
 
     It should be noted that, in current regulation, the amplifier VA 1  has no effect because of its unbalance that prevents the passage of current in the current mirror formed by the NMOS transistors M 56 -M 57 . 
     The amplifier PA 1  comprises a differential stage with PMOS transistor M 64  and M 65  and a current mirror of NMOS transistor M 66 -M 67 . The source terminals of the transistors M 64  and M 65  are connected to a generator of the bias current Ipol 2  and the drain terminals are connected respectively to the drain terminals of the transistors M 66  and M 67 . The gate terminals of the transistors M 64  and M 65  are connected to a reference voltage Vref 2  and to the voltage V(T) and the drain terminal of the transistor M 64  is connected to the gate terminal of the transistor M 58 . 
     If the temperature of the system is such that the signal V(T)=K×T is less than Vref 2 , the amplifier PA 1  is unbalanced and turns off the transistor M 58 . Thus the reference current Iref is entirely mirrored in the transistor M 20  and, during the entire charging phase of the battery, the regulated current is exactly a multiple of the current Iref, as the amplifier CA 1  sees to equalling the drain-source voltages of the transistors M 10  and M 20 . 
     If the temperature of the system is such that V(T) reaches Vref 2 , the stage PA 1  tends to subtract a part of the current Iref at the mirror M 30 -M 31 . Consequently the charge current is less than its nominal value and it will settle itself at a value that balances the temperature of the device Tj according to the formula:
 
 Tj=Tamb+ ( Vin−Vout )× Iout×θ 
 
where Tamb is the temperature outside the system, lout is the charge current and θ is the thermal resistor of the package of the device.
 
     The temperature loop, being dynamically slow because of the reaction times of the package, has a dominating pole almost at the origin and has no need for compensation. 
     When the voltage Vout reaches the reference voltage Vref 1 , the amplifier VA 1  balances itself and the NMOS mirror transistor M 56 -M 59  tends to subtract the bias current Ipol of the amplifier CA 1  which then turns off. In this manner the stage VA carries out the voltage regulation of the output. 
     The compensation of the regulation loop current/voltage has been carried out by means of a Miller capacitor connected between the gate and the drain terminals of the transistor M 20 . 
       FIG. 4  shows time graphs of the voltage Vout, of the output current lout and of the temperature Tp in the charging phase of the battery, with an input voltage Vin=5V and an external temperature of 25° C. The charge current is programmed at 0.5 A. The maximum junction temperature set by specification is Tj=120° C. In this case it can be seen that the temperature of the system is lower and thus the charge current is equal to that programmed. In voltage regulation the charge current decreases until it annuls itself and the regulated voltage on the battery is 4.1V, as per specification. 
       FIG. 5  shows an enlargement of the charge current of the battery lout during the current regulation. The excellent precision, which is 0.2%, is highlighted. 
       FIG. 6  shows time graphs of the voltage Vout, of the output current lout and of the temperature Tp in the charging phase of the battery when Vin=12V at an external temperature of 25° C. As before, the current is programmed at 0.5 A. In this case the temperature of the device is regulated at 120° C., lowering the charge current to approximately 0.24 A. 
     The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.