Abstract:
A method of manufacturing a thin film transistor includes: forming an amorphous silicon layer and a blocking layer; forming a photoresist layer having first and second photoresist patterns spaced apart from each other on the blocking layer; etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; reflowing the photoresist layer so the first and second photoresist patterns abut each other; forming a capping layer and a metal layer; removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer; etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and removing the first and second blocking patterns.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of application Ser. No. 10/994,265, filed on Nov. 23, 2004, which is a continuation-in-part application of application Ser. No. 10/801,146, filed on Mar. 16, 2004, which is a continuation application of application Ser. No. 10/114,463, filed on Apr. 3, 2002, now issued as U.S. Pat. No. 6,706,573, and claims priority from and the benefit of Korean Patent Application No. 2001-18010, filed on Apr. 4, 2001, which are all hereby incorporated by reference for all purposes as if fully set forth herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a thin film transistor and a method of manufacturing the same, and, more particularly, to a thin film transistor manufactured according to a method that provides high electrified mobility, high reliability and simplified manufacturing. 
     2. Description of Related Art 
     A poly silicon layer is generally used as a semiconductor layer of a thin film transistor (TFT). The poly silicon layer is formed such that an amorphous silicon layer is first deposited on a substrate and crystallized at a predetermined temperature. A method of crystallizing the amorphous silicon layer includes an eximer laser annealing (ELA) technique, a solid phase crystallization (SPC) technique, and a metal induced lateral crystallization (MILC) technique. 
     Of these techniques, the MILC technique is disclosed in U.S. Pat. No. 6,097,037 and has an advantage in that the amorphous silicon layer is crystallized at a relatively low temperature and at a relatively short processing time in comparison with the ELA technique and the SPC technique. 
       FIGS. 1A to 1B  are cross-sectional views illustrating a process of manufacturing the TFT using the MILC technique according to conventional methods. 
     Referring to  FIG. 1A , an amorphous silicon layer  11  is formed such that an amorphous silicon is deposited on an insulating substrate  10  using a low pressure chemical vapor deposition (LPCVD) technique and patterned in the form of an island. 
     A gate insulating layer  12  and a gate electrode  13  are sequentially formed on the amorphous silicon layer  11  while exposing both end portions of the amorphous silicon layer  11 . A high-density impurity is ion-implanted into the exposed end portions of the amorphous silicon layer  11  to form source and drain regions  11 S and  11 D. A non-doped portion of the amorphous silicon layer  11  acts as a channel area  11 C. 
     A photoresist pattern  15  is formed on the amorphous silicon layer  11  and covers the gate insulating layer  12  and the gate electrode  13 . At this juncture, both end portions of the amorphous silicon layer  11  are not covered with the photoresist pattern  15 . Thereafter, a metal layer  14  is deposited over the entire surface of the insulating substrate  10  using a sputtering technique. Preferably, the metal layer  14  is made of Ni, Pd, Ti, Ag, Au, Al, or Sb. 
     Referring now to  FIG. 1B , the photoresist pattern  15  is removed using a lift-off technique, whereupon offset regions  17  are formed. Subsequently, the amorphous silicon layer  11  is crystallized by a furnace to form a poly silicon layer  11   a . At this juncture, a portion of the amorphous silicon layer  11  that directly contacts the metal layer  14  is crystallized by a metal induced crystallization (MIC) technique, and the offset regions  17  and the channel area  11 C are crystallized by the MILC technique. 
     In the conventional method of manufacturing the TFT using the MILC technique, traps are prevented since the boundaries between the MIC and MILC regions are located outside the channel area  11 C, for example, within the source and drain regions  11 S and  11 D. 
     However, the conventional method of manufacturing the TFT using the MILC technique additionally requires a mask process to form the offset regions  17 , thereby lowering productivity and increasing the production costs. 
     Also, since a crystallization is performed using the MILC technique after the gate insulating layer  12  and the gate electrode  13  are formed on the amorphous silicon layer  11 , an interface characteristic between the gate insulating layer  12  and the channel area  11 C deteriorates, and many trap sites are provided, whereby the electric field mobility is lowered. 
     In addition, an MILC front  11 F, including a metal silicide, exists in the channel area  11 C and serves as a defect of the TFT, thereby deteriorating reliability of the TFT. Here, the MILC front  11 F is referred to as that portion where lateral growths meet each other when the amorphous silicon layer  11  is crystallized by the MILC technique. Such an MILC front  11 F contains more metal components than other portions and becomes a defect of the semiconductor layer. 
     In order to locate the MILC front  11 F outside the channel area  11 C, a method is introduced such that the MIC region is non-symmetrically formed centering on the channel area  11 C to perform crystallization. That method is disclosed in IEEE Electron Device Letters, vol. 21, no. 7, July 2000, and is entitled “The Effects of Electrical Stress and Temperature on the Properties of Polycrystalline Silicon Thin Film Transistor Fabricated by Metal Induced Lateral Crystallization.” However, this method has a problem in that crystallization is non-symmetrically performed and thus a processing time for crystallization is increased. 
     SUMMARY OF THE INVENTION 
     To overcome the problems described above, preferred embodiments of the present invention provide a thin film transistor (TFT) having a high electric field mobility, a high productivity, and a high reliability. 
     In order to provide a thin film transistor (TFT) having a high electric field mobility, a high productivity, and a high reliability, preferred embodiments of the present invention provide one or more methods of manufacturing a thin film transistor. In one embodiment, the method may include: a) forming an amorphous silicon layer and a blocking layer on an insulating substrate; b) forming a photoresist layer having first and second photoresist patterns on the blocking layer, the first and second photoresist patterns spaced apart from each other; c) etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; d) reflowing the photoresist layer, so that the first and second photoresist patterns abut on each other so as to entirely cover the first and second blocking patterns; e) forming a capping layer and a metal layer over an entire first surface of the insulating substrate; f) removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; g) crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer into the amorphous silicon layer to form a polysilicon layer; h) etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and i) removing the first and second blocking patterns. 
     The present invention further provides a method of manufacturing a thin film transistor. In one embodiment, such a method may include: a) forming an amorphous silicon layer on an insulating substrate; b) forming a first photoresist layer on the amorphous silicon layer while exposing edge portions of the amorphous silicon layer; c) forming a capping layer and a metal layer over an entire first surface of the insulating substrate; d) removing the first photoresist layer to expose a portion of the amorphous silicon layer under the first photoresist layer; e) crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer into the amorphous silicon layer to form a polysilicon layer; f) a second photoresist layer having first and second photoresist patterns on the polysilicon layer, wherein the first and second photoresist patterns are spaced apart from each other; g) etching the poly silicon layer using the first and second photoresist patterns as a mask to form first and second semiconductor layers; and h) removing the first and second photoresist patterns. 
     The metal layer is preferably made of Ni or Pd and preferably has a thickness of hundreds of Å. In one embodiment, the thickness may be in the range of about 1 Å to about 5000 Å. Preferably, a crystallization of the amorphous silicon layer is performed at a temperature of 400° C. to 600° C. The capping layer is made of SiO2 or SiNx. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which: 
         FIGS. 1A and 1B  are cross-sectional views illustrating a process of manufacturing the thin film transistor (TFT) using an MILC technique according to conventional methods; 
         FIGS. 2A ,  2 B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H, and  2 I (hereinafter,  FIGS. 2A to 2I ) are plan views illustrating a process of manufacturing a TFT according to an embodiment of the present invention; 
         FIGS. 3A ,  3 B,  3 C,  3 D,  3 E,  3 F,  3 G,  3 H, and  3 I (hereinafter,  FIGS. 3A to 3I ) are cross-sectional views taken along line III-III of  FIG. 2I , illustrating a process of manufacturing the TFT according to an embodiment of the present invention; 
         FIGS. 4A ,  4 B,  4 C,  4 D,  4 E,  4 F, and  4 G (hereinafter,  FIGS. 4A to 4G ) are plan views illustrating a TFT according to another embodiment of the present invention; and 
         FIGS. 5A ,  5 B,  5 C,  5 D,  5 E,  5 F, and  5 G (hereinafter,  FIGS. 5A to 5G ) are cross-sectional views taken along line V-V of  FIG. 4G . 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Reference will now be made in detail to preferred embodiments of the present invention, an example of which is illustrated in the accompanying drawings. 
     One method of implementing one or more embodiments of the invention is shown in the plan views of  FIGS. 2A to 2I  and the corresponding cross-sectional side views of  FIGS. 3A to 3I . 
     Referring to  FIGS. 2A and 3A , a buffer layer  21 , an amorphous silicon layer  22  and a blocking layer  23  are sequentially formed on an insulating substrate  20 . The buffer layer  21  is preferably made of an oxide layer and serves to prevent an impurity from being diffused into a semiconductor layer which will be formed in a subsequent process. The blocking layer  23  is preferably made of an oxide layer. 
     There are two methods to form the buffer layer  21 , the amorphous silicon layer  22 , and the blocking layer  23 . A first method is that after the buffer layer  21  is formed on the insulating substrate  20 , the amorphous silicon layer  22  and the blocking layer  23  are deposited using a plasma-enhanced chemical vapor deposition (PECVD) technique. The second method is that the buffer  21 , the amorphous silicon layer  22 , and the blocking layer  23  can be sequentially deposited using the PECVD technique. 
     A photoresist pattern  24  is formed on the blocking layer  23 . The photoresist pattern  24  has the same pattern as a mask to form a dual-channel semiconductor layer which will be formed in a subsequent process. In other words, the photoresist pattern  24  includes first and second photoresist patterns  24 - 1  and  24 - 2 , which are spaced apart from each other as shown in  FIG. 2A . 
     Referring now to  FIGS. 2B and 3B , using the photoresist pattern  24  as a mask, the blocking layer  23  is patterned using a dry-etching technique or an HF etching solution while exposing both end portions of the amorphous silicon layer  22 , so that the blocking layer  23  includes first and second blocking patterns  23 - 1  and  23 - 2 . The first and second blocking patterns  23 - 1  and  23 - 2  are spaced apart from each other. 
     In  FIGS. 2A to 2I  and  3 A to  3 I, reference numerals in parentheses denote parts which are not shown due to a viewing angle. 
     Referring now to  FIGS. 2C and 3C , the photoresist pattern  24  is reflowed to entirely cover the patterned blocking layer  23 . A first reflowed photoresist pattern  24 - 1   a  and a second reflowed photoresist pattern  24 - 2   a  of the reflowed photoresist pattern  24   a  abut on each other, so that a portion of the amorphous silicon layer  22  between the first blocking pattern  23 - 1  and the second blocking pattern  23 - 2  is covered. 
     Referring now to  FIGS. 2D and 3D , a capping layer  25  and a first metal layer  26  are formed over the entire surface of the substrate  20 . The capping layer  25  directly contacts the exposed ends of the amorphous silicon layer  22 . The capping layer  25  controls a diffused metal concentration from the first metal layer  26  to the amorphous silicon layer  22 . The capping layer has a thickness of hundreds of Å and is made of SiO2 or SiNx, but is preferably made of SiO2. 
     The first metal layer  26  preferably has a thickness of hundreds of Å and is preferably made of a material which can react with silicon (Si) to form a silicide such as Ni or Pd. 
     Referring now to  FIGS. 2E and 3E , the first and second reflowed photoresist patterns  24 - 1   a  and  24 - 2   a  are removed to expose the blocking layer  23  and to expose an offset region “dos” of the amorphous silicon layer  22 . Therefore, the capping layer  25  and the first metal layer  26  remain only on both end portions of the amorphous silicon layer  22 . 
     Referring now to  FIGS. 2F and 3F , the amorphous silicon layer  22  is crystallized at a temperature of preferably 400° C. to 600° C. to form a poly silicon layer  22 . At this moment, the first metal layer  26  and both end portions of the amorphous silicon layer  22  that directly contact the capping layer are diffused to the amorphous silicon layer  22  and make seeds. And then, both end portions of the amorphous silicon layer  22  are crystallized by a super grain silicon (SGS), and a non-contact portion of the amorphous silicon layer  22  that does not contact the capping layer  26  is also crystallized by the SGS. The polysilicon layer  22  includes a first and second polysilicon layers  22 - 1  and  22 - 2 , and the polysilicon layer  22   b  includes first and second polysilicon layers  22 - 3  and  22 - 4 . The first polysilicon layers  22 - 1  and  22 - 3 , the second polysilicon layers  22 - 2  and  22 - 4  are all formed by the SGS, and the second polysilicon layers  22 - 2  and  22 - 4  include SGS seeds. Also, a high angle grain boundary  22 - 5  exists between the polysilicon layers  22   a  and  22   b . The capping layer  25  and the first metal layer  26  remaining on the polysilicon  22   a  and  22   b  are removed to expose the second polysilicon layers  22 - 2  and  22 - 4 . The high angle grain boundary  22 - 5  means that grains are grown to meet each other, thereby forming grain boundaries. 
     Referring now to  FIGS. 2G and 3G , using the first blocking pattern  23 - 1  and the second blocking pattern  23 - 2  as a mask, the poly silicon layers  22   a  and  22   b  are etched to form first and second semiconductor layers  30   a  and  30   b . Therefore, the first and second semiconductor layers  30   a  and  30   b  include only the second polysilicon layers regions  22 - 2  and  22 - 4 , respectively. The high-angle grain boundary  22 - 5  is removed while etching the poly silicon layers  22   a  and  22   b . Thereafter, the blocking layer  23  is removed. 
     Referring now to  FIGS. 2H and 3H , a surface treatment process is performed in order to improve a surface characteristic of the semiconductor layers  30   a  and  30   b . The surface treatment process is to remove a natural oxide layer (not shown) or impurities on the semiconductor layers  30   a  and  30   b  and is performed using a dry-etching technique or an HF etching solution of 0.1% to 20%. 
     At this point, in case the blocking layer  23  is made of an oxide layer, the surface treatment process can be performed at the same time as the process of removing the blocking layer  23 . 
     Referring now to  FIGS. 2I and 3I , the TFT having a dual channel is completed using the first and second semiconductor layers  30   a  and  30   b . In greater detail, a gate insulating layer  26  is formed over the entire surface of the substrate  20 . A second metal layer is deposited over the entire surface of the substrate  20  and patterned to form a gate line  27   a  and a gate electrode  27   b . The gate electrode  27   b  extends from the gate line  27   a.    
     Subsequently, using the gate electrode  27   b  as a mask, a p- or an n-type high-density impurity is ion-implanted into the first and second semiconductor layers  30   a  and  30   b  to form first source and drain regions  29   a  and  29   b  and second source and drain regions  29   c  and  29   d , respectively. The non-doped portions of the first and second semiconductor layers  30   a  and  30   b  serve as a channel area. 
     At this point, an offset region or a lightly doped drain (LDD) region can be formed between the source and drain regions and the channel area. The method of forming the offset region or the LDD region is well known. 
     Next, an interlayer insulating layer  31  is formed over the entire surface of the substrate  20 . The interlayer insulating layer  31  includes contact holes  31   a  to  31   d . The contact holes  31   a  and  31   b  are formed at a location corresponding to a portion of the first source region  29   a  and to a portion of the first drain region  29   b , respectively. The contact holes  31   c  and  31   d  are formed at a location corresponding to a portion of the second source region  29   c  and to a portion of the second drain region  29   d , respectively. 
     Thereafter, a third metal layer is deposited on the interlayer insulating layer  31  and patterned to form source and drain electrodes  32   a  and  32   b  and a data line  32   c . The source electrode  32   a  extends from the data line  32   c  and is electrically connected to the first and second source regions  29   a  and  29   c , respectively, through the contact holes  31   a  and  31   c . The drain electrode  32   b  is electrically connected to the first and second drain regions  29   b  and  29   d , respectively, through the contact holes  31   b  and  31   d . Consequently, the TFT according to the present invention is completed. 
     As described herein, the TFT according to an embodiment of the present invention has numerous advantages. Since a mask process to crystallize the amorphous silicon layer is not required, the manufacturing process is simplified, thus leading to a high manufacturing yield. Also, since the high-angle grain boundary is removed, the formation of defects can be prevented, leading to high reliability. 
     One method of forming one of more embodiments of the invention is shown in the plan views of  FIGS. 4A to 4H  and the corresponding cross-sectional side views of  FIGS. 5A to 5H . 
     Referring now to  FIGS. 4A and 5A , a buffer layer  41  and an amorphous silicon layer  42  are sequentially formed on an insulating substrate  40 . The buffer layer  41  is preferably made of an oxide layer and serves to prevent an impurity from being diffused into a semiconductor layer which will be formed in subsequent process. At this point, the buffer layer  41  and the amorphous silicon layer  42  can be formed using the PECVD technique. Thereafter, a photoresist pattern  43  is formed on the amorphous silicon layer  42  while exposing both end portions of the amorphous silicon layer  42 . 
     Referring now to  FIGS. 4B and 5B , a capping layer  44  and a first metal layer  45  is formed over the whole surface of the substrate  40  and covers the photoresist pattern  43 . The capping layer  44  directly contacts the exposed end portions of the amorphous silicon layer  42 . The capping layer  44  controls a diffused metal concentration from the first metal layer  45  to the amorphous silicon layer  42 . The capping layer  44  preferably has a thickness of tens to hundreds of Å and is made of SiO2 or SiNx, preferably made of SiO2. 
     The first metal layer  45  is preferably made of a material which reacts with silicon to form a silicide such as Pd or Ni. The first metal layer  45  preferably has a thickness of 1 Å to 5000 Å and preferably tens to hundreds of Å. 
     Referring now to  FIGS. 4C and 5C , the photoresist pattern  43  is removed to expose a central portion of the amorphous silicon layer  42 . The capping layer  44  remains only on both end portions of the amorphous silicon layer  42 . 
     Referring now to  FIGS. 4D and 5D , the amorphous silicon layer  42  is crystallized at a temperature of preferably 400° C. to 600° C. to form a poly silicon layer  42   a . The exposed portion of the amorphous silicon layer  42  is crystallized by the SGS, and both end portions of the amorphous silicon layer  42  which directly contact the capping layer  44  includes the seeds for the SGS and are crystallized by the SGS. 
     At this juncture, since a contact region between the amorphous silicon layer  42  and the first metal layer  44  is relatively large, a crystallization speed will increase. An MILC front  42 - 3  exists on a central portion of the poly silicon layer  42   a  (i.e., MILC region  42 - 1 ). 
     Referring now to  FIGS. 4E and 5E , the capping layer  44  and the first metal layer  45  remaining on the second polysilicon layers  42 - 2  of the poly silicon layer  42   a  is removed. 
     Referring now to  FIGS. 4F and 5F , a photoresist pattern  46  is formed on the poly silicon layer  42   a . The photo resist pattern  46  includes first and second photoresist patterns  46 - 1  and  46 - 2 . The first and second photoresist patterns  46 - 1  and  46 - 2  are formed on the corresponding first polysilicon layers  42 - 1 , respectively, and are spaced apart from each other, so that the high-angle grain boundary  42 - 3  is exposed. 
     Referring now to  FIGS. 4G and 5G , using the photoresist pattern  46  as a mask, the poly silicon layer  42  is etched to form first and second semiconductor layers  43   a  and  43   b . At the same time, the MILC front  42 - 3  is removed. Therefore, the first and second semiconductor layers  43   a  and  43   b  include only the first polysilicon layers  42 - 1 . Thereafter, the photoresist pattern  46  is removed. 
     Subsequently, a surface treatment process is performed in order to improve a surface characteristic of the semiconductor layers  43   a  and  43   b . The surface treatment process is to remove a natural oxide layer (not shown) or impurities on the semiconductor layers  43   a  and  43   b  and is performed using a dry-etching technique or an HF etching solution of 0.1% to 20%. 
     Thereafter, even though not shown in the drawings, the process of  FIGS. 2I and 3I  is performed to complete the TFT according to another embodiment of the present invention. 
     As described herein, the TFT according to an embodiment of the present invention has numerous advantages. First, since crystallization simultaneously processes from all edge portions of the amorphous silicon layer, the processing time is reduced. Second, since the high angle grain boundary is removed, the formation of defects is prevented, thereby improving reliability. Third, since the amorphous silicon layer is crystallized without an additional mask process, the manufacturing process is simplified, leading to a high manufacturing yield. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.