Abstract:
The reference circuit includes a current mirror for providing first and second current paths for the conduction of respective first and second currents. The current mirror imposes a current level relationship between the first and second currents. A load, preferably resistive, is provided in the first current path for predominantly establishing a predetermined level of the first current. A transistor having a temperature coefficient of a predetermined polarity and a resistor having a temperature coefficient of a complimentary polarity are provided in the second current path for providing temperature compensation. Finally, a load compensation stage is provided in the first and second current paths to provide a thermal compensation feedback path from the transistor and resistor compensation elements to permit stabilization of the first current level with respect to temperature.

Description:
FIELD OF THE INVENTION 
     The present invention is generally related to current and voltage reference circuits employing temperature compensation and, in particular, to a reference circuit having a temperature compensated output characteristic that can be optimized to establish either a constant current or a constant voltage reference level, or both, from source potentials as low as approximately 1.5 volts. 
     BACKGROUND OF THE INVENTION 
     Quite often integrated analog system components must be designed to operate in close conjunction with digital logic. Further, a typical desire is to fabricate related, if not mutually supportive, analog and digital system components on a common die. Close functional integration of analog and digital is naturally desirable for the ability to form high-level functional blocks. In any of these cases, the analog system components are typically required to operate from a common semiconductor, typically digital voltage supply level. This requirement is often a simple expedient arising from the cost effectiveness of using only a single, fixed potential power supply, such as a battery. Therefore, analog system components are often required to operate from power supply differences of between 1.5 and five volts, or more, over the age of a battery without loss of operational accuracy. 
     Typically, the accuracy of an analog system component will depend on the accuracy of its internal current and voltage reference circuits. Conventional current references utilize a Zener diode to accurately establish a reference voltage level. A reference current level can be derived from the reference voltage level through the conventional use of a simple current mirror amplifier circuit. However, the fabrication of an integrated Zener diode having a Zener threshold (V z ) of less than about 6.2 volts is difficult and generally impractical particularly where other integrated devices are to be fabricated on the same substrate. To achieve Zener thresholds of incrementally less than 6.2 volts requires progressively higher doping densities in the fabrication of the diode. Such high doping densities are generally incompatible with the fabrication of other analog and digital components. Therefore, Zener diode based reference circuits are generally not used where the power supply potential difference is less than approximately 7 volts. 
     Band-gap reference circuits provide an alternate approach to obtaining reference current levels from low voltage supplies. Band-gap references generally rely on a difference between the semiconductor band-gaps of active semiconductor devices. However, band-gap references are quite complex to fabricate as compared to Zener references, are quite sensitive to fabrication process variations and require a well-behaved amplifier in the necessary reference level control feedback loop in order to maintain stable operation. Additionally, band-gap references typically require a relatively large integrated device surface area due to their circuit complexity. 
     SUMMARY OF THE INVENTION 
     Therefore, a general purpose of the present invention is to provide temperature compensated voltage and current level reference circuit capable of operating from low supply voltages. 
     This is achieved by the present invention through the provision of a circuit for providing an output reference level that is fixed with respect to temperature. The circuit includes a current mirror for providing first and second current paths for the conduction of respective first and second currents. The current mirror imposes a current level relationship between the first and second currents. A load, preferably resistive, is provided in the first current path for predominantly establishing a predetermined level of the first current. A transistor having a temperature coefficient of a predetermined polarity and a resistor having a temperature coefficient of a complimentary polarity are provided in the second current path for providing temperature compensation. Finally, a load compensation stage is provided in the first and second current paths to provide a thermal compensation feedback path from the transistor and resistor compensation elements to permit stabilization of the first current level with respect to temperature. 
     Thus, an advantage of the present invention is that it is capable of providing a stable current or voltage reference level insensitive to operating environment conditions including temperature and power source potential difference variations. 
     Another advantage of the present invention is that it is capable of stable operation from power source potential differences of down to approximately 1.5 volts while maintaining a high power-supply-rejection-ratio. The present invention is therefore imminently capable of operating in conjunction with conventional integrated digital logic and battery based power supplies. 
     A further advantage of the present invention is that it employs an efficient, low circuit component count design. Therefore, a highly die-area efficient integrated circuit implementation of the present invention can be readily achieved. The use of few, well characterized integrated components directly yields a high degree of operational reliability, low design cost and relatively minimal implementation complexity. 
     Still another advantage of the present invention is that the circuit components, power supply requirements, and design circuit and layout of the present invention are fully compatible with and producible by standard CMOS design and fabrication processes. Through the use of well characterized integrated circuit components, the present invention is generally not sensitive to nominal fabrication process variation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other advantages of the present invention will become apparent and readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawing and wherein: 
     The FIGURE provides a circuit schematic of a preferred integrated circuit embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A circuit diagram of the low voltage, temperature compensated reference circuit, generally indicated by the reference numeral 10 and exemplary of a preferred embodiment of the present invention, is shown in FIG. 1. The reference 10 is shown as including a low voltage capable, temperature compensated reference circuit 12, exemplary power-on bootstrap circuit 14 and exemplary output circuit stage 16. 
     The reference circuit 12 includes a current mirror configured pair of enhancement mode NMOS transistors 18, 20. The gates 22 of the transistors 18, 20 are connected in common to the source 24 of the transistor 18. The drains of the transistors 18, 20 are commonly connected to a negative source potential (-V) via conductor 26. The current relationship between a current I 1  through transistor 18 and I 2  through transistor 20 is defined by Equation 1. 
     
         I.sub.2 =kI.sub.1                                          Eq. 1 
    
     where k is a proportionality constant defined as the ratio of the width to length dimensions of the active channel of transistor 20 with respect to the width to length dimensions of the active channel of transistor 18. 
     A current mirror amplifier, constructed from a pair of enhancement mode PMOS transistors 30, 32 are provided such that the source of transistor 30 is connected in series with the drain 24 of transistor 18 and the source of transistor 32 is connected in series with the drain 28 of transistor 20. The gates 34 of the transistors 30, 32 are connected in common to the source 28 of transistor 32. The drain of transistor 30 is coupled in series through a resistor 36 (R 1 ) to a positive source potential (+V) provided on a conductor 38. An NPN type, diode connected bipolar transistor 40 (Q 1 ) provides a current path for the current I 2  from the conductor 38 through a series connected resistor 42 (R 2 ) to the drain of transistor 32. The loop equation for the uppermost loop of the reference circuit 12 is given by Equation 2. 
     
         I.sub.1 R.sub.1 +V.sub.GS.sbsb.30 =V.sub.be +I.sub.2 R.sub.2 +V.sub.GS.sbsb.32                                         Eq. 2 
    
     Transistors 30 and 32 can be presumed to have essentially identical operating characteristics due to their common design and close integration together on a common substrate. Therefore, Equation 2 essentially reduces to Equation 3. 
     
         I.sub.1 R.sub.1 =V.sub.be +I.sub.2 R.sub.2                 Eq. 3 
    
     By substituting Equation 1 into Equation 3, a relationship defining the reference current I 1  can be provided as in Equation 4. ##EQU1## It should be recognized that the relationship defined by Equation 4 defines a thermally static circuit operation circumstance. However, initial constraints on the selection of the reference current I 1 , and the design of the reference circuit 12 in general, may be deduced from Equations 3 and 5. The static constraints are: first, the product of the reference current I 1  and resistor R 1  36 must be greater than or equal to the base-to-emitter voltage potential difference V be  of the transistor Q 1  40; and second, the effective resistance R eff  must be greater than zero. The minimum operating voltage requirement of about 1.5 volts is reached from an assumption that the voltage drop across resistor R 2  will be about the same as V be . 
     The dynamic thermal performance of the reference circuit 12 may be determined by differentiating Equation 4 with respect to temperature. The resulting relationship is provided as Equation 6. ##EQU2## where TC Vbe  is the temperature coefficient of the transistor Q 1 , TC R1  is the temperature coefficient of the resistor R 1 , TC R2  is the temperature coefficient of the resistor R 2  and TC net  is the net (output) temperature coefficient of the reference circuit 12. 
     For a preferred embodiment of the present invention, the reference current I 1  is desired to be constant over temperature. Therefore, the net temperature coefficient given by Equation 6 should be equal to zero for such an embodiment. Setting TC net  of Equation 6 equal to zero and simplifying yields Equation 7. 
     
         R.sub.1 (TC.sub.R.sbsb.1)=R.sub.eff (TC.sub.V.sbsb.be)+kR.sub.2 (TC.sub.R.sbsb.2)                                         Eq. 7 
    
     Equation 7 and the static relationship defined by Equation 5 as between the resistor values R 1  and R 2  and current amplifier constant k can be solved simultaneously using matrix algebra and then substituting for fthe value R eff  to isolate the relationship of the resistors R 1  and R 2  with respect to the reference current I 1 . The initial matrix equation is given by Equation 8 and the resulting relationships for resistors R 1  and R 2  are given by Equations 9 and 10, respectively. ##EQU3## 
     In accordance with the preferred embodiments of the present invention, the resistors R 1  and R 2  are chosen to have temperature coefficients that are complimentary in sign to that of the diode connected transistor Q 1 . Further, the manner of fabricating the resistors R 1  and R 2  is chosen to permit the selection of a separate temperature coefficient for each of the resistors R 1 , R 2 . Conventionally fabricated transistors, such as diode connected transistor Q 1 , will have a negative temperature coefficient and a modest magnitude. A typical range of temperature coefficients obtainable with conventional fabrication techniques is from about -3,000 ppm/°C. to about -3,500 ppm/°C. The resistors R 1 , R 2  are preferably fabricated to have a positive temperature coefficient. P-type resistors fabricated in an N-type substrate or N-well will have positive temperature coefficients that can range, using conventional fabrication techniques, from about 400 to about 20,000 ppm/°C. By utilizing differing doping densities, the resistors R 1  and R 2  can be readily fabricated to have the distinctly different temperature coefficients desired. Preferably, the temperature coefficient of the resistor R 2  is chosen to be significantly greater than that of R 1  as can be seen to be preferred from Equation 7. At a resistivity of 45 Ohms per square, a typical highly-doped P-type resistor will have a temperature coefficient of about 550 ppm/°C. For a lighter doped P-type resistor providing a resistance value of 2,600 Ohms per square, a temperature coefficient of about 7,000 ppm/°C. can be readily obtained. Thus, for a desired reference current I 1  and the characteristics of the devices produced by the particular conventional fabrication process utilized, Equations 9 and 10 permit the values of the resistors R 1  and R 2  to be selected to ideally achieve a net zero temperature coefficient for the reference circuit 12. 
     An alternate embodiment of the present invention provides for the optimization of the reference circuit 12 to operate as a temperature compensated voltage level reference. This is achieved by selecting the thermal coefficient and values of the transistor Q 1  and resistors R 1  and R 2  such that a temperature invariant voltage level is established at the drain of the transistor 18; effectively the voltage reference output of the reference circuit 12. From Equation 7, the net thermal coefficient contribution of the transistor Q 1  and resistor R 2  are selected to equal zero as shown in Equation 11. 
     
         0=R.sub.eff (TC.sub.V.sbsb.be)+kR.sub.2 (TC.sub.R.sbsb.2)  Eq. 11 
    
     That is, by fixing the voltage at the drain of transistor 32 with respect to the positive source potential over temperature, the voltage appearing at the drain of transistor 18 is fixed with respect to the negative source potential over temperature. Empirically, as the resistive value of the resistor R 1  changes with temperature, the gate-to-source potential difference of transistor 30 will change proportionately, resulting in a constant voltage appearing at the effective output terminal 24 of the reference circuit 12. The relationships between the values and thermal coefficients of the transistor Q 1  and resistor R 1 , R 2  can again be derived from equation 8 by allowing TC R1  to equal zero. The resulting relationships for resistors R 1  and R 2  are defined by Equations 12 and 13, respectively. ##EQU4## 
     The reference circuit 12, in accordance with another preferred embodiment of the present invention, can be optimized for use as both a current and a voltage level reference. For such an embodiment, Equations 12 and 13 are utilized to select the component values and characteristics of the resistors R 1  and R 2  and the transistor Q 1 . Further, the fabrication of the resistor R 1  is preferably such as to independently minimize its temperature coefficient. For this embodiment, the variance in I 1  over temperature is almost entirely attributable to the temperature coefficient of R 1 . Therefore, minimizing the temperature coefficient of R 1  in combination with the selection of Q 1  and R 2  for an output voltage invariant with respect to temperature yields a combined current and voltage reference capability. The fabrication of resistor R 1  with a minimum temperature coefficient is preferably achieved by Silicon-Chrome thin film deposition. 
     Considering the reference circuit 12 again in general terms and with respect to the implementation of its currently preferred best modes, the power bootstrap circuit 14 is provided to initiate proper operation upon application of power. Initially, the gate of the transistor 44, connected to the output terminal 24 of the reference circuit 12, is at or close to the negative source potential. Consequently, transistor 44 is held off. The source of transistor 44 and gate of a current forcing, depletion mode transistor 50 are pulled, by virtue of a resistor 48 (R 3 ), to the positive source potential. The drain 52 of the current forcing transistor 50 is coupled to the positive source conductor 38 while its source 54 is coupled to the drain 24 of transistor 18. The current forcing transistor 50 therefore acts to control a current feed of a start-up current I 1  &#39; to the current mirror 18, 20. As the transistors 18, 20 are thereby forced to switch on, the transistor 44 of the power-on bootstrap circuit is also driven on. Consequently, the current forcing transistor 50 is forced off. Thereafter, the power-on bootstrap circuit 14 effectively ceases to participate in the operation of the reference circuit 12. 
     The output stage 16 is illustrative of two separate, but not mutually exclusive techniques for preparing the output reference level of the reference circuit 12 for subsequent use. Transistors 60 and 66, combine to provide a conventional bipolar current drive and shifted voltage level capability on the output line 64. Transistor 68 provides a simple, conventional current sink capability on the output line 70. 
     EXAMPLE 
     An embodiment of the present invention substantially as shown in the FIGURE has been fabricated on a standard silicon wafer. A conventional fabrication process was utilized to obtain the following selected device specifications: 
     
         ______________________________________R.sub.1  Ohms (calculated)                  10K Ohm  (measured)      9.7K Ohm  TC (measured)   550 ppm/°C.  Resistor Dimensions                  W - 10 μm                  L - 220 μm  Doping Density  1 × 10.sup.19 cm.sup.-3R.sub.2  Ohms (calculated)                  14.4K Ohm  (measured)      14.9K Ohm  TC (measured)   7,000 ppm/°C.  Resistor Dimensions                  W - 10 μm                  L - 55 μm  Doping Density  1 × 10.sup.16 cm.sup.-3Q.sub.1  Type            Bipolar  V.sub.be (calculated)                  0.68 V  (measured)      0.67 V  TC (measured)   3,000 ppm/°C. @ 25° C.Q.sub.2  Type            NMOS  Channel Dimensions                  W - 120 μm                  L - 15 μmQ.sub.3  Type            NMOS  Channel Dimensions                  W - 30 μm                  L - 15 μmQ.sub.4  Type            PMOS  Channel Dimensions                  W - 400 μm                  L - 20 μmQ.sub.5  Type            PMOS  Channel Dimensions                  W - 100 μm                  L - 20 μm______________________________________ 
    
     The operating characteristics of the fabricated embodiment of the invention, upon thermal sensitivity characterization testing, was found to be at or less than 1000 ppm/°C. without trimming of the R 1  and R 2  resistor values over a temperature range of 25° to 125° C. After trimming the resistors R 1 ,R 2 , the thermal sensitivity of the reference was measured at about 100 ppm/°C. over the temperature range of 25° to 125° C. The trimming of the resistors R 1 ,R 2  was accomplished by first determining, by reverse calculation, the required values in view of the tested, untrimmed performance of the fabricated embodiments. The resistors R 1 , R 2  were then trimmed by blowing fusible links, provided as a series conductive taps positioned along the length of the resistor. Consequently, the effective length, and therefore resistivity, of the resistors where adjusted. 
     Thus, a temperature compensated reference circuit capable of being optimized for establishing a constant current or a constant voltage level, or both, and operating at source potential differences of down to about 1.5 volts has been described. 
     Naturally, the detailed illustrative embodiments of the present invention disclosed herein exemplifies the invention and provides the teachings from which many modifications and variations may be made without departing from the present invention in its broader aspects. It is therefore to be understood that, within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described herein.