Abstract:
A circuit to detect predetermined power supply levels so that sufficient power is provided for an integrated circuit to function properly and drive a bus. A first circuit indicates whether a first voltage has reached a first level, a second circuit indicates whether a second voltage has reached a second level, and a third circuit causes the second circuit to operate in a low power mode when the second voltage has reached a predetermined level. The first voltage is provided by an I/O power supply and the second voltage is provided by a core power supply.

Description:
FIELD 
     This invention relates to integrated circuit power up, more particularly, a circuit to detect predetermined power supply levels so that sufficient power is provided for an integrated circuit to function properly and drive a bus, the circuit operating in a low power mode when predetermined power supply levels are detected. 
     BACKGROUND 
     Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer. Typically, if a processor fails, the computer system fails. Processor failure may occur due to, for example, insufficient power being provided by one or more power supplies. That is, the magnitude of supply voltage can be below the minimum nominal operating voltage required by the processor. 
     Processors are presently designed to consume and require minimal power. When the Merced multiprocessor system powers up, voltage is supplied to each of the different integrated circuits on the bus. Since the Merced processor has dual power supplies, a core power supply having 1.1 volts and an input/output (I/O) power supply having 1.5 volts, it is necessary to ensure that both power supplies reach functional levels before enabling any Front Side Bus (FSB) functionality. If the voltage supplied to the Merced integrated circuit is insufficient for the integrated circuit to function properly, the integrated circuit must not drive the FSB because it would prevent other integrated circuits on the system and the system itself from functioning properly. A faulty core power supply could improperly drive the FSB pins, and a faulty I/O power supply could result in faulty integrated circuit behavior regardless of the state of the integrated circuit core. Although voltage sensors exist for detecting sufficient power supplies in the Deschutes phase locked loop (PLL) and in the Merced PLL, their low power modes (IDDQ) can result in sufficient power being incorrectly indicated while the core supply is inadequate. This invention ensures that power supplies, including both the core power supply and the I/O power supply reach sufficient levels before the Merced integrated circuit drives the FSB. The invention teaches disabling FSB pin driving until sufficient core power is detected, the detection provided by a circuit that can be disabled for low power operation when sufficient core power and I/O power is detected, and the circuit designed to meet high volume manufacturing standards. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit schematic functional diagram showing an embodiment of the present invention. 
     FIG. 2 is a circuit schematic showing an embodiment of the present invention. 
     FIG. 3 a  depicts an I/O power supply being ramped-up and the bias of transistor  24  and transistor  42  over time in an embodiment of the present invention. 
     FIG. 3 b  depicts the total power consumption of the circuit over time, the integral of all the currents of the circuit, in an embodiment of the present invention. 
     FIG. 3 c  depicts a power supply level response over time as the core power supply voltage rises and falls at power-up and after power up, in an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments are described with reference to specific configurations. Those skilled in the art will appreciate that various changes and modifications can be made while remaining within the scope of the claims. 
     In accordance with an embodiment of the present invention, a multiprocessor computer system includes two or more processors that communicate with each other, as well as with the rest of the computer system, via I/O signals across a system bus. The computer system includes an I/O power supply that supplies power to each processor of the system . The I/O power supply provides the power used by the processors to drive the I/O signals on a system bus. The computer system additionally includes core power supplies, one for each processor of the multiprocessor system. The core power supplies provide the power used by the processor cores to perform signal processing. 
     FIG. 1 depicts one embodiment of the invention. At power up, core power supply  14  and I/O power supply  1  are initially at ground and inverter output  44   a  indicates that core power supply  14  is insufficient. Core power supply  14  and I/O power supply  2  are filtered using a resistor and a capacitor (RC filter) having different component values. This filtering causes core power supply  14  to lag I/O power supply  2 , when being ramped up from ground, to establish that I/O power supply  2  is sufficient before establishing that core power supply  14  is sufficient. Filtering also helps ensure flat there is no false indication that power is insufficient for the integrated circuit to function properly and drive a bus if either power supply is noisy. As I/O power supply  2  powers up, but before reaching a level sufficient to drive the FSB, transistor  42  is activated by I/O power supply detector  10 , and current travels from the source to the drain of transistor  42 . Being connected to transistor  42 , inverter  44  receives a logic high from the drain of transistor  42  and outputs a logic low which indicates that core power supply  14  is not sufficient to drive the FSB. When I/O power supply  2  reaches a sufficient level to drive the FSB, I/O power supply detector  10  turns off transistor  42  and therefore inverter  44  receives a logic low from the drain of transistor  42 . In one embodiment, I/O power supply detector  10  comprises a chain of diodes connected between I/O power supply and ground. 
     In one embodiment, the power up of core power supply  14  lags the power up of I/O power supply  2  and therefore in one state example, although I/O power supply  2  has reached a sufficient level to drive the FSB, core power supply  14  is not at a sufficient level to drive the FSB. Reference voltage generator  12  is enabled with I/O power supply  2  and is an input into differential amplifier  20 . A second input into differential amplifier  20  is a filtered core power supply voltage  14 . Differential amplifier  20  compares its two inputs and provides a logic low output into the input of inverter  26  if core power supply  14  is sufficient to drive the FSB, and provides a logic high output into the input of inverter  26  if core power supply  14  is insufficient to drive the FSB. 
     When a logic high is provided as an input into inverter  26 , the output of inverter  26  activates transistor  28 , and transistor  32  is set to off. Current from core power supply  14  travels from the source to the drain of transistor  28 , and inputs a logic high into inverter  44 . Inverter  44  then outputs a logic low, indicating core power supply  14  being insufficient to drive the FSB. If a logic low is provided as an input into inverter  26 , the output of inverter  26  activates transistor  32 , and transistor  28  is set to off. Since transistor  34  is activated by I/O power supply detector  10 , the input of inverter  44  is grounded, inverter  44  then outputs a logic high indicating that core power supply  14  being sufficient to drive the FSB. 
     In one embodiment, a feedback is used from inverter  44  output to an input of logic NAND gate  50 . Once inverter  44  outputs a logic high, and low power enable  46  provides a logic high, NAND gate  50  outputs a logic low to the input of inverter  22 . Inverter  22  then outputs a logic high to the gate of transistor  24 , activating transistor  24 . The output of differential amplifier  20  is then grounded through transistor  24  causing the input into inverter  26  to be low and causing the output of inverter  44  to be high, indicating that core power supply  14  is sufficient to drive the FSB. Logic NAND gate  50  outputs a logic low when the output of inverter  44  outputs a logic high and low power enable  46  outputs a logic high. This ensures that sufficient power is detected from both core power supply  14  and I/O power supply  2  before driving the FSB. Additionally, when logic =NAND gate  50  outputs a logic low, reference voltage generator  12  and differential amplifier  20  are disabled. The signal from low power enable  46  is converted to the I/O power supply voltage domain from the core power supply voltage domain using level shifter  48 . The decrease in power consumption in the low power mode is identifiable in FIG. 3 b . All combinatorial logic is enabled by an unfiltered I/O power supply. 
     FIG. 2 is a schematic diagram of an embodiment of the claimed subject matter. I/O power supply  2  is filtered through Filter  3  and which causes the core power supply to lag the I/O power supply  2 . Level shifter  48  converts the low power enable signal  46  from the core power supply voltage domain to the I/O power voltage domain. Logic NAND gate  50  outputs a logic low when the output of inverter  44  is a logic high and the lower power enable output  46  is a logic high. Reference voltage generator  12  and differential amplifier  20  are disabled when logic NAND gate  50  outputs a logic low, If NAND gate  50  outputs a logic low, the logic low is input into inverter  22 , which outputs a logic high to transistor  24 . 
     As I/O power supply  2  powers up, but before reaching a level sufficient to drive the FSB, transistor  42  is activated by I/O power supply detector  10 , and current travels from the source to the drain transistor  42 . Inverter  44  outputs a logic low, indicating that core power supply  14  is insufficient to drive the FSB. In one embodiment, I/O power supply detector  10  comprises chain of diodes  16 . I/O power supply detector  10  may also comprise transistor  17 , in one embodiment of the claimed subject matter. 
     Having disclosed exemplary embodiments, modifications and variations may be made to the disclosed embodiments while remaining within the spirit and scope of the invention as defined by the appended claims.