Abstract:
An autoregressive model simulator is disclosed. The simulator produces time multiplexed samples of a plurality of signals generated from autoregressive coefficients. The order of the autoregressive model is selected by the configuration of identical integrated circuit chips. The autoregressive coefficients for each signal and past samples of the signal are rotated through FIFOs in a manner which enables the simulator to be simply controlled.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to the formation of signals having desired statistical characteristics and more particularly to a design for an integrated circuit chip to produce signals using an autoregressive model. 
     In various situations, it is desirable to produce an electrical signal or set of electrical signals having a particular frequency spectrum. One technique for producing signals with a desired spectrum is to use what is called an autoregressive model. With this technique, the signal is described in terms of autoregressive coefficients. 
     To produce a sample of the desired signal, the autoregressive coefficients are combined in a known fashion. The combination of these coefficients is described by an equation: ##EQU1## where 
     y(N) is the Nth, and current, sample of the generated signal; 
     q is an index of summation; 
     y(N-q) is a sample of the generated signal generated q samples before the current sample (for values of (N-q) less than zero, y(N-q) is defined to be zero); 
     a q  is the qth autoregressive coefficient characterizing the desired signal; 
     b is a constant also determined as part of the calculation of autoregressive coefficients; 
     X(N) is the Nth sample of a function representing zero mean white noise with a unit variance; and 
     M is a constant representing the order of the autoregressive model. 
     The order of the autoregressive model, M, dictates how closely the spectrum of the generated signal approximates the desired spectrum. The higher the value of M, the closer the approximation. It should be noted, however, that the higher the value of M, the more autoregressive coefficients are required to evaluate Eq. 1. Since the signal is generated by some form of electronic circuitry, more coefficients generally require larger or more complicated circuitry. 
     The circuitry used to form the signal is called an &#34;autoregressive model simulator&#34;. It is desirable for an autoregressive model simulator to be easily constructed, regardless of the order of the model. In some applications, it is desirable to generate several signals simultaneously. Thus, it would be desirable to have circuitry that could generate a plurality of signals. 
     SUMMARY OF THE INVENTION 
     With the foregoing background in mind, it is therefore an object of this invention to provide a simple circuit for implementing an autoregressive model simulator. 
     It is also an object of this invention to provide a simple circuit for an autoregressive model simulator capable of generating a plurality of signals. 
     It is yet another object of this invention to provide a design for an integrated circuit chip from which an autoregressive model simulator of any order can be constructed. 
     The foregoing and other objects of this invention are accomplished by an autoregressive model simulator constructed from a plurality of identical circuit elements. Each circuit element comprises a plurality of multipliers. The inputs to the multipliers are coupled to first in first out FIFO memories storing a set of autoregressive coefficients and past samples for each signal to be generated. The outputs of the multipliers are summed by adder elements. The sum is combined in an adder/subtractor with an external input representing a random signal. 
     In operation, the value at the top of each coefficient FIFO is moved to the bottom of the same FIFO after one sample of each output signal is computed. The value at the top of each FIFO storing past samples, except the last, is moved to the bottom of an adjacent FIFO. The simulator is thereby operated to ensure that the coefficients and the corresponding past samples for each signal are simultaneously at the tops of all the FIFOs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     With the foregoing object of the invention in mind, the invention may be better understood by reference to the following detailed description and the accompanying drawings in which: 
     FIG. 1 is a block diagram of a fourth order autoregressive model simulator constructed according to the present invention; 
     FIG. 2 is a circuit diagram, greatly simplified, of the autoregressive model simulator of FIG. 1 constructed from integrated circuits; 
     FIG. 3 is a block diagram of an Integer Computing Element (ICE) integrated circuit used in the circuit of FIG. 2; and 
     FIG. 4A is a block diagram of the computing circuitry of a sixth order autoregressive model simulator constructed with ICE chips according to the present invention; and 
     FIG. 4B is a block diagram of the computing circuitry of an eighth order autoregressive model simulator constructed with ICE chips according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a block diagram of a fourth order autoregressive model simulator. As shown by Eq. 1, the autoregressive model simulator produces samples of a signal y(N) as N takes on values 0, 1, 2, 3 . . . . 
     In many applications, both the amplitude and phase of the signal y(N) are important. Here, y(N) consists of a real part y R  (N) and an imaginary part y I  (N) which together convey phase and amplitude information. Likewise, each autoregressive coefficient a q  has a real part and an imaginary part a qR  and a qI , respectively. X(n) also consists of a real and an imaginary part X R  (N) and X I  (N). Thus, y(N)=y R  (N)+j y I  (N) and a q  =a qR  +j a qI  and X(N)=X R  (N)+j XI(N). Equation 1 might therefore be written to describe the calculation of y R  (N) and y I  (N): ##EQU2## 
     The block diagram of FIG. 1 shows a circuit which implements Eqs. 2a and 2b. Values of bX I  (N) and bX R  (N) are provided as inputs to the circuit. Memories 100 1  . . . 100 4  store the real parts of the autoregressive coefficients, a qR , for q taking on values 1 . . . 4, respectively. Memories 102 1  . . . 102 4  store the imaginary parts of the autoregressive coefficients, a qI , for q taking on values 1 . . . 4, respectively. Memories 104 1  . . . 104 4  store the real part of y(N-q), y R  (N-q), for q taking on values 1 . . . 4, respectively. Memories 106 1  . . . 106 4  store the imaginary part of y(N-q), y I  (N-q) for q taking on values 1 . . . q, respectively. 
     Adder 120 computes the first summation term of Eq. 2a. Multipliers 112 1  . . . 112 4  multiply the values in memories 100 1  . . . 100 4  by the values in memories 104 1  . . . 104 4 , respectively. Thus, each multiplier 112 1  . . . 112 4  computes one term a qR  y R  (N-q) for q taking on values 1 . . . 4. The output of the multipliers 112 1  . . . 112 4  are summed by adder 120. 
     Adder 121 computes the second summation term of Eq. 2a. Multipliers 114 1  . . . 114 4  multiply the values in memories 102 1  . . . 102 4  by the values in memories 106 1  . . . 106 4 , respectively. Thus, each multiplier 114 1  . . . 114 4  computes one term a qI  y I  (N-q) for q taking on values 1 . . . 4. The output of the multipliers 114 1  . . . 114 4  are summed by adder 121. The outputs of adders 120 and 121 are added by adder 122. The output of adder 121 is negated by adder 122 as indicated in Eq. 2a. The term bX R  (N) provided as an input is also added by adder 122. Adder 122 adds all the terms in Eq. 2a. Thus, the output of adder 122 is y R  (N). 
     Adder 123 computes the first summation term of Eq. 2b. Multipliers 116 1  . . . 116 4  multiply the values in memories 102 1  . . . 102 4  by the values in memories 104 1  . . . 104 4 , respectively. The nodes labeled I are connected together, but the connection is not explicitly shown. Thus, each multiplier 116 1  . . . 116 4  computes one term a qI  y R  (N-q) for q taking on values 1 . . . 4. The output of the multipliers 116 1  . . . 116 4  are summed by adder 123. 
     Adder 124 computes the second summation term of Eq. 2b. Multipliers 118 1  . . . 118 4  multiply the values in memories 102 1  . . . 102 4  by the values in memories 106 1  . . . 106 4 , respectively. The points labeled R are connected together, but the connection is not explicitly shown. Thus, each multiplier 118 1  . . . 118 4  computes one term a qR  y I  (N-q) for q taking on values 1 . . . 4. The output of the multipliers 118 1  . . . 118 4  are summed by adder 124. 
     The outputs of adders 123 and 124 are added by adder 125. The term bX I  (N) provided as an input is also added by adder 125. Adder 125 adds all three terms of Eq. 2b. Thus, the output of adder 125 is y I  (N). 
     Eq. 1 describes what is often called an &#34;infinite impulse response&#34; or &#34;recursive&#34; filter. The value of y(N) produced for any value of N depends on the M preceeding values of y(N). In FIG. 1, memories 104 1  . . . 104 4  are interconnected such that the M (here 4) preceding values of y(N) are always stored. As seen in FIG. 1, when a new value of y(N) is produced, the value of Y R  (N) is stored in memory 104 1 , since that value will represent y R  (N-1) when the next value of y R  (N) is computed. The value stored in memory 104 1 , previously representing y R  (N-1) becomes y R  (N-2) and is moved to memory 104 2 . In this way, the values stored in memories 104 2  and 104 3  are &#34;rippled down&#34; each time the value of N increases. Thus, memories 104 1  . . . 104 4  store the appropriate values for y R  (N-1) . . . y R  (N-4). In a similar fashion, memories 106 1  . . . 106 4  store the appropriate values of y I  (N-1) . . . y I  (N-4). 
     An additional feature of the present invention may also be seen by reference to FIG. 1. As previously described, it is desirable for an autoregressive model simulator to produce a plurality of different signals. From Eq. 1, it can be seen that for each signal, a different set of autoregressive coefficients, a 1  . . . a M , a different set of past outputs y(N-1) . . . y(N-M) and a different value of bX(N) is required. The computing circuitry 130 needed to implement Eq. 1 is otherwise the same. 
     The autoregressive model simulator of FIG. 1 is adapted to produce samples of S different signals. Memories 100 1  . . . 100 4  and 102 1  . . . 102 4  each contain S locations for storing S sets of autoregressive coefficients, one set for each signal to be generated. Memories 104 1  . . . 104 4  and 106 1  . . . 106 4  also have S locations for storing S sets of past values of y(N). 
     In operation, computing circuitry 130 is time multiplexed to produce S different signals. For example, in a first time interval, memories 100 1  . . . 100 4  and 102 1  . . . 102 4  are operated to provide the autoregressive coefficients for a first signal. Simultaneously, memories 104 1  . . . 104 4  and 106 1  . . . 106 4  are operated to provide past samples of the first signal. In that first interval, then, the output y(N) is the Nth sample of the first signal. In the next time interval, memories 100 1  . . . 100 4 , 102 1  . . . 1024, 104 1  . . . 104 4 , and 106 1  . . . 106 4  are operated to provide values needed to compute the Nth sample of the second signal. The operation of the memories continues in this fashion for each of the subsequent time intervals until a sample is produced for each of the S signals. The cycle then starts over with each memory operated to produce the next sample of the first signal. 
     Memories 100 1  . . . 100 4 , 102 1  . . . 102 4 , 104 1  . . . 104 4 , and 106 1  . . . 106 4  are here first in first out memories (FIFOs) to simplify the circuitry needed to produce time multiplexed samples of S signals. FIFOs are known in the art to operate such that values stored in memory are read out one at a time in the order they are stored into memory. The next value to be read out is said to be at the &#34;top&#34; of the memory. The value most recently stored in the FIFO is at the &#34;bottom&#34; of the memory. 
     In preparation for operation, the autoregressive coefficients for the first signal are applied on buses 132 and 134 from any known source. The autoregressive coefficients are then stored into memories 100 1  . . . 100 4  and 102 1  . . . 102 4 . The autoregressive coefficients for the remaining S signals are then stored into memories 100 1  . . . 100 4  and 102 1  . . . 102 4  in like fashion. Memories 104 1  . . . 104 4  and 106 1  . . . 106 4  could be loaded with initial values in a like fashion. Here, however, the initial values are all zero, and well known methods may be employed to set all the values stored in a digital memory to zero. 
     In a first time interval, the values of autoregressive coefficients for the first signal are at the tops of memories 100 1  . . . 100 4  and 102 1  . . . 102 4 . These are thus fed to computing circuitry 130 to compute a value of y(N). After a value of y(N) is computed for the first signal, the autoregressive coefficients at the tops of memories 100 1  . . . 100 4  and 102 1  . . . 102 4  are moved to the bottoms of the memories. The autoregressive coefficients for the second signal are thus at the tops of memories 100 1  . . . 100 4  and 102 1  . . . 102 4  to compute a value of y(N) for the second signal during the second interval. 
     When the autoregressive coefficients for the first signals are placed at the bottoms of memories 100 1  . . . 100 4  and 102 1  . . . 102 4 , the past values of y(N) for the first signal are written to the bottoms of memories 104 1  . . . 104 4  and 106 1  . . . 106 4 . After S time intervals, the autoregressive coefficients for the first coefficient will again be at the tops of memories 100 1  . . . 100 4  and 102 1  . . . 102 4 . The past values of y(N) for the first signal will simultaneously be at the tops of memories 104 1  . . . 104 4  and 106 1  . . . 106 4 . 
     In a like manner, the values needed to compute y(N) for the second signal are the tops of memories 100 1  . . . 100 4 , 102 1  . . . 102 4 , 104 1  . . . 104 4  and 106 1  . . . 106 4  during the second interval. These values are applied to computing circuitry 130 to produce a new value of y(N). The appropriate values are then written to the bottoms of the memories so they will next circulate to the tops of the memories in the same time interval. 
     The same pattern is repeated for all of the other S signals. Thus, use of FIFOs for memories as shown provides a simple circuit for producing time multiplexed samples of a plurality of signals. 
     Turning now to FIG. 2, a circuit for implementing the autoregressive model simulator of FIG. 1 using integrated circuit chips is shown. Standard elements of digital circuits such as power connections and control signals are not explicitly shown. However, one of skill in the art will realize that such elements are required. 
     Computing circuit 130 is shown to comprise four identical chips 220A . . . 220D. Here, chips 220A . . . 220D are called Integer Computing Elements (ICE) chips and are explained in more detail below in conjunction with FIG. 3. Suffice it to say here that ICE chips 220A . . . 220D produce the outputs y R  (N) and y I  (N) described above. 
     FIFO 200A is a single integrated circuit chip (IC) containing two FIFO memories configured like memories 100 1  and 100 2  (FIG. 1). FIFO 200B implements memories 100 3  and 100 4  (FIG. 1). FIFO 202A implements memories 102 1  and 102 2  (FIG. 1). FIFO 202B implements memories 102 3  and 102 4  (FIG. 1). FIFO 204A implements memories 104 1  and 104 2  (FIG. 1). FIFO 204B implements memories 104 3  and 104 4  (FIG. 1). FIFO 206A implements memories 106 1  and 106 2  (FIG. 1). FIFO 206B implements memories 106 3  and 106 4 . FIFOs 200A, 200B, 202A, 202B, 204A, 204B, 206A and 206B are each a separate IC such as are known in the art. 
     Multiplexers 222A and 222B are 4:1 multiplexers such as are known in the art. FIFOs 200A, 200B, 202A and 202B have two outputs (here each a digital word of 16 bits) each representing one autoregressive coefficient. As will be explained later, four 16 bit words are read into each ICE chip 220A . . . 220D. However, each ICE chip 220A . . . 220D has only one 16 bit input labeled H. Multiplexer 222A selects one of the four outputs at a time from FIFOs 200A and 200B for application to ICE chips 220A and 220D. Likewise, multiplexer 222A selects one of the four outputs at the time from FIFOs 202A and 202B for application to ICE chips 220B and 220C. 
     The inputs bX R  (N) and bX I  (N) are produced by noise chip 226. Here, noise chip could be one or a collection of chips using known techniques to generate digital samples of zero mean gaussian noise. Noise chip 226 takes as an input a parameter stored in noise variance FIFO 224. Noise variance FIFO 224 operates like one of the memories 100 1  . . . 100 4  (FIG. 1). Noise variance coefficients for each one of the S signals to be generated is stored in noise variance FIFO 224. The noise variance coefficients for each signal reaches the top of noise variance FIFO 224 in the same interval when the autoregressive coefficients for the same 15 signal reach the tops of memories 100 1  . . . 100 4 . Noise chip 226 generates a sample of a random signal with desired variance. Thus, samples of the input bX(N) for the plurality of signals are generated in a time multiplexed order. 
     FIG. 3 shows additional details of an ICE chip 220 representative of one of the ICE chips 220A . . . 220D. FIG. 3 shows a control input is applied to a decoder 300. Each output of decoder 300 is applied as a control signal to one of the elements of ICE chip 220. The control input is generated by a control circuit (not shown) which might contain a read only memory with the control inputs stored sequentially in it. One of skill in the art will recognize the control circuit (not shown) can be constructed in a variety of known ways to operate the ICE chips as described herein. 
     Inputs A, B, C and D are connected, as shown in FIG. 2 to one of the FIFOs 204A, 204B, 206A or 206B. Thus, one of the past values of the output y(N) are applied to inputs to A, B, C and D. That value is stored in one of the registers 304A, 304B, 304C or 304D. 
     As also shown in FIG. 2, the autoregressive coefficients stored in either FIFO 200A, 200B, 202A or 202B are applied to the H input of an ICE chip 220A . . . 220D via multiplexer 222A or 222B. As described above, multiplexers 222A and 222B apply the coefficients to input H sequentially such that each coefficient may be stored in one of the registers 302A . . . 302D. 
     Each of the multipliers 306A . . . 306D has as its inputs one past value of y(N) and one autoregressive coefficient. The outputs of multipliers 306A . . . 306D therefore make up four terms of one of the summations in Eqs. 2a and 2b. The outputs of multipliers 306A and 306B are summed by adder 308A. The outputs of multipliers 306C and 306D are summed by adders 308B. The output of adder 308A is applied to adder 308C. The output of adder 308B is applied as an input to adder 308C. The output of adder 308C represents the sum of all the products produced by multipliers 306A . . . 306D. In FIG. 1, the output of adder 308C corresponds to the output of adder 120, 121, 123 or 124, depending on which of the ICE chips 220A . . . 220D (FIG. 2) is represented by ICE chip 220 (FIG. 3). 
     The output of adder 308C is added to the input labeled E. As shown in FIG. 2, the input E represents the real part of the input bX R  (N), the output of adder 120 (FIG. 1), the imaginary part of the input bX I  (N) or the output of adder 123 (FIG. 1) depending on whether ICE chip 220 is used for ICE chip 220A, 220B, 220C or 220D, respectively. When ICE chip 220 is used for ICE chip 220B, the output of adder 308C must be subtracted from the input E. Adder 308D can be configured by control signal from decoder 300 to subtract. Thus, ICE chip 220 as shown in FIG. 3 is flexible enough to be used for any of the ICE chips 220A . . . 220D of FIG. 2. 
     ICE chip 220 might be used to provide an autoregressive model simulator of an order other than four as shown in FIGS. 1 and 2. FIG. 4a shows how a plurality of ICE chips 220&#39;A . . . 220&#39;F can be connected to make a sixth order autoregressive model simulator. FIG. 4A shows only the computing circuit 130. As previously described, computing circuit 130 is connected to memories storing autoregressive coefficients at the points labeled &#34;coefficient input&#34;. The points labeled R, I and X are connected to like points designated R, I and X. The points labeled R are connected to a memory containing the real parts of the autoregressive coefficients. The points labeled I are connected to a memory containing the imaginary parts of the autoregressive coefficients. The points labeled X are connected to memories storing the real parts of two autoregressive coefficients and the imaginary parts of two autoregressive coefficients. Computing circuit 130 is also connected to memories storing past samples of y R  (N) and y I  (N) at the points indicated. 
     In a similar fashion, FIG. 4B shows ICE chips 220&#34;A . . . 220&#34;H connected to form an eighth order autoregressive model simulator. As shown, computing circuit 130 is connected to memories storing past samples of y R  (N) and y I  (N). Computing circuit 130 is also connected to inputs bX R  (N) and bX I  (N). The circuit 130 is also connected to memories storing autoregressive coefficients. The points labeled R 1  and R 2  are each connected to memories storing one-half of the real parts of the coefficients. The points labeled I 1  and I 2  are each connected to memories storing one half of the imaginary parts of the coefficients. 
     Having described this invention, it will now be apparent to one of skill in the art that various modifications could be made to the disclosed embodiments. The ICE chips might be combined to form autoregressive model simulators of orders other than disclosed. The layouts of the ICE chips might be modified to include other numbers of multipliers and adders. It is felt, therefore, that this invention should not be restricted to the disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims.