Abstract:
The frequency divider for high-frequency clock signal comprises: a shift register ( 8 ) having cells ( 10 - 13 ) for storing each bit of an initial word, said cells being series connected in a loop ( 14 ), and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the high-frequency clock signal, and wherein an output terminal ( 6 ) for outputting a frequency-divided clock signal is connected to the output of one cell of the loop of series-connected cells.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a digital frequency divider circuit comprising an input terminal for receiving a clock signal, whose frequency of which is to be divided and an output terminal for outputting a frequency divided clock signal.  
       BACKGROUND OF THE INVENTION  
       [0002]     Frequency dividers are among the basic circuits of digital technology. Frequency dividers are digital circuits, and the input frequencies are integer multiples of the output frequencies. Such circuits are used for example in radiofrequency technology, where there exists continual demand for the development of circuits with ever higher clock rates or frequencies. In order to realize frequency dividers, usually a plurality of gates are connected in series in a combinatorial part of the divider, so that, for each state change of the input signal, many gates are switched within one clock period.  
         [0003]     The maximum possible input frequency of a frequency divider is thus limited by the sum of the signal propagation times of the series-connected gates.  
         [0004]     US 2003/0007591 discloses a frequency divider that overcomes the above mentioned disadvantage. This frequency divider comprises among other components a state register, a decoder, a loading device and a parallel to serial converter. Some of these components are clocked with a high frequency clock, whereas other components are clocked with a low frequency clock. Due to the use of many components and of two frequency clocks, the frequency divider disclosed in US 2003/0007591 remains quite complicated to manufacture.  
       SUMMARY OF THE INVENTION  
       [0005]     It is accordingly an object of the invention to provide a frequency divider that is able to operate at high frequency and remains quite easy to manufacture.  
         [0006]     With the foregoing and other objects in view there is provided, in accordance with the invention, a frequency divider comprising a shift register having cells for storing each bit of an initial word, said cells being series connected in a loop, and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the received clock signal, and wherein the output terminal is connected to the output of one cell of the loop of series-connected cells.  
         [0007]     In the above frequency divider, the cells of the shift register are connected to each other in order to form a loop, so that bits shifted turn around or rotate. In such a shift register, if the same initial word is repeatedly shifted in synchronism with the received clock signal, the signal observed at one output of one of the cells is periodic and its frequency is a submultiple of the frequency of the received clock signal. It can be noticed that such frequency divider does not comprise any series connected gates. Consequently, high clock rates can be processed. Furthermore, the number of components of this frequency divider is reduced compare to the frequency divider of US 2003/007591. So, this frequency divider is simpler to manufacture.  
         [0008]     The features as defined in claims  2  to  4  have the advantage that the divider ratio of the frequency divider is adjustable.  
         [0009]     The features as defined in claims  5  to  7  have the advantage that the duty cycle of the frequency divider can be selected.  
         [0010]     Other features of the claimed invention are recited in the dependent claims.  
         [0011]     The invention also concerns an electronic device including a frequency divider according to claim  1 .  
         [0012]     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments describes hereinafter. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is a schematic diagram of a first embodiment of a frequency divider according to the invention; and  
         [0014]      FIG. 2  is a schematic diagram of a second embodiment of a frequency divider according to the invention.  
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0015]      FIG. 1  represents a first embodiment of a frequency divider  2 . The frequency divider  2  will be described only for illustrative proposes in the special case where the divider ratio of the frequency divider is equal to four and its duty cycle is equal to 50/50.  
         [0016]     The value x/y for the duty cycle indicates that during x per cents of the time, the output clock signal should be set to a logic one, whereas during the remaining time the output clock signal should be set to a logic zero.  
         [0017]     Frequency divider  2  is used in an electronic device  3  in  FIG. 1  that needs clock frequency division operations to be carried out.  
         [0018]     Frequency divider  2  comprises an input terminal  4  and an output terminal  6 . Terminal  4  is for receiving the clock signal whose frequency is to be divided by the divider ratio. Terminal  6  is for outputting a clock signal whose frequency is equal to the frequency of the received clock signal divided by the divider ratio.  
         [0019]     The frequency divider  2  comprises a shift register  8  having four cells  10  to  13  clocked in synchronism by the same input clock that is the clock received at terminal  4 . In order to do so, the clock input of each cell is directly connected to terminal  4 .  
         [0020]     Here, each cell is a flip-flop or a scannable circuit.  
         [0021]     The output of each flip-flop is directly connected to the input of a following flip-flop except for last flip-flop  13 . The output of flip-flop  13  is connected to the input of first flip-flop  10 . Such a design forms a loop  14  in which flip-flops  10  to  13  are connected in series.  
         [0022]     The first two flip-flops  10  and  11  are connected to a common reset line  18  in order to initialise these two first flip-flops with a logic one at the output. The other two flip-flops  12  and  13  are connected to a reset line  20  in order to initialise these two flip-flops with a logic zero at the output.  
         [0023]     Reset lines  18 ,  20  are connected, for example, to respective and different fixed potentials so that flip-flops  10  and  11  are always initialized with a logic one, whereas flip-flops  12  and  13  are always initialized with a logic zero.  
         [0024]     The way in which frequency divider  2  works will now be explained.  
         [0025]     At initialization, reset lines  18  and  20  write  8  an initial word “1100” in shift register.  
         [0026]     When a rising edge occurs in the received clock signal at terminal  4 , value from the output of each flip-flop is captured on the following flip-flop. Consequently, each bit of the word “1100” is shifted by one position on the left at each rising edge of the received clock signal. This is illustrated in the following table.  
                                   TABLE 1                                           Output       Received   Flip-flop   Flip-flop   Flip-flop   Flip-flop   clock       clock signal   10   11   12   13   signal                   Initial state   1   1   0   0   0       1st rising edge   0   1   1   0   0       2nd rising edge   0   0   1   1   1       3rd rising edge   1   0   0   1   1       4th rising edge   1   1   0   0   0       5th rising edge   0   1   1   0   0                  
 
         [0027]     The first line of Table 1 shows the output values of each flip-flop  10  to  13  in the initial state of shift register  8 . The following lines shows the output value of flip-flops  10  to  13  respectively after the first, second, third, fourth, fifth rising edge of the received clock signal. The last column of Table 1 shows the output value at terminal  6  corresponding to each rising edge.  
         [0028]     As shown, the initial word “1100” is shifted by one position at each rising edge of the received clock signal and the bit output by flip-flop  13  is returned to the input of flip-flop  10 . The value stored in the shift register is periodically repeated every four rising edges of the received clock signal. Therefore, the output clock signal presents only one rising edge every four rising edges of the received clock signal. So the frequency of the output clock signal is four time lower than the frequency of the received clock signal.  
         [0029]     Furthermore it can be noted that the duty cycle of the frequency divider  2  is equal to 50/50 since during one period of the output clock signal, the value of the output clock signal is equal to “1” during 50% of the time and equal to “0” during the remaining time.  
         [0030]     The maximum possible frequency of the received clock signal is only limited in frequency divider  2  by the signal propagation time through one flip-flop. For example, if the signal propagation time of a signal from the input of one flip-flop to the output of the same flip-flop is equal to 1 ns, the maximum possible input frequency is up to 1 GHz.  
         [0031]     Furthermore, the duty cycle of frequency divider  2  can be easily changed by initializing the shift register with a different initial word, like “1000” or “1110”. The initial word should be comprised between 1 and 2 n −2, where n is the number of cells of the shifted register.  
         [0032]     However, in the preferred embodiment, the setting of each flip-flop is not adjustable or programmable in order to ease the test of the frequency divider during the manufacturing process using a test method known as “SCAN test”. For example, the initial setting of each flip-flop is hardwired.  
         [0033]      FIG. 2  illustrates a second embodiment of a frequency divider designated by the general reference  30 . The frequency divider  30  is designed to have an adjustable duty as well as a programmable divider ratio.  
         [0034]     Similarly to frequency divider  2 , frequency divider  30  comprises an input terminal  32  to receive the input clock signal whose frequency is to be divided, and an output terminal  34  for outputting the divided frequency clock signal.  
         [0035]     Frequency divider  30  also comprises a shift register  36  clocked by the input clock signal and a control unit  38  for configuring the shift register  36 .  
         [0036]     As an example, shift register  36  is designed to have a maximum divider ratio equal to eight. Therefore, shift register  36  comprises eight flip-flops  40  to  47  connected in series in a loop  48 . Flip-flops  40  to  43  form a first group of series-connected flip-flops whose outputs are always initialized at a logic one, and flip-flops  44  to  47  form a second group of series-connected flip-flops whose outputs are always initialized at a logic zero.  
         [0037]     In order to initialize the output of the flip-flops of the first group at a logic one, one reset input of each flip-flop is connected to a reset line  50  which is configured to always set up a logic one at initialization of shift register  36 .  
         [0038]     Similarly, the reset input of each flip-flop of the second group is connected to a reset line  52  which is configured to always set up a logic zero in flip-flops  44  to  47  at initialization of shift register  36 .  
         [0039]     Loop  48  of shift register  36  also has only two multiplexers  54  and  56 . Multiplexer  54  is connected between the first and second groups of flip-flops, whereas multiplexer  56  is connected between the second and first groups of flip-flops. More precisely, the output of each flip-flop of the first group is connected to a corresponding input of multiplexer  54  and an output of multiplexer  54  is connected to the first flip-flop of the second group, that is flip-flop  44 .  
         [0040]     The output of each flip-flop of the second group is connected to a corresponding input of multiplexer  56 . An output of multiplexer  56  is connected to the first flip-flop of the first group, that is flip-flop  40 .  
         [0041]     Two control lines  58  and  60  are connected between control unit  38  and multiplexers  54  and  56 , respectively, in order to select which input of a multiplexer should be connected to its output.  
         [0042]     Control unit  38  has two inputs  64  and  66 . Input  64  is provided for receiving the value of the desired duty cycle and input  66  for receiving the value of the desired divider ratio.  
         [0043]     Control unit  38  is designed to configure the shift register  36 , so that the duty cycle and the divider ratio of the frequency divider are equal respectively, to the input desired duty cycle and divider ratio. In order to do so, the control unit  38  has a module  68  to determine the number of flip-flops that should be used in loop  48  to obtain the desired divider ratio and a module  70  to determine which flip-flops of shift register  36  should be used in loop  48  to obtain the desired duty cycle.  
         [0044]     Modules  68  and  70  are realised in a conventional way in order to implement the functionality described below.  
         [0045]     The way in which frequency divider  30  works, will now be explained in the particular situation where the desired duty cycle is equal to 25/75 and the desired divider ratio is equal to four.  
         [0046]     At initialization, module  68  determines that to obtain a divider ratio equal to four, four flip-flops should be used in the loop of shift register  36 , since the number of flip-flops needed is equal to the desired divider ratio.  
         [0047]     Module  70  determines that 25 per cent of the flip-flops to be used should be selected in the first group, whereas the other flip-flops to be used should be selected in the second group. Indeed, the first value of the desired duty cycle, here “25”, fixes the percentage of the flip-flops to be used that should be selected in the first group. In the particular situation described here as an example, this means that one flip-flop should be selected in the first group and three flip-flops should be selected in the second group.  
         [0048]     So, during an initialization step, control unit  38  controls multiplexer  54  in order to connect the output of flip-flop  40  to the input of flip-flops  44 . Control unit  38  also controls multiplexer  56  in order to connect the output of flip-flop  46  to the input of flip-flops  40 .  
         [0049]     After this initialisation step, the loop of shift register  36  only comprises four flip-flops, which are flip-flops  40 ,  44 ,  45  and  46 , and the initial word to be shifted by one position at each rising edge of the input clock signal is equal to “1000”. This initial word corresponds exactly to a duty cycle equal to 25/75.  
         [0050]     Now the frequency divider  30  is ready to work and works exactly as already explained for frequency divider  2 . Therefore, no further explanation will be given.  
         [0051]     In comparison to frequency divider  2 , frequency divider  30  presents the advantages to have adjustable duty cycle ratio and divider ratio. However, the maximum possible input frequency for the input clock signal is slightly lower than the maximum possible input frequency of frequency divider  2 . Indeed, the maximum possible input frequency of frequency divider  30  is determined by the signal propagation time of one flip-flop and one multiplexer.  
         [0052]     Otherwise, frequency divider  30  presents exactly the same advantages as frequency divider  2 . In particular, the initial state of each flip-flop of shift register  36  is always the same, so that frequency divider  30  can easily be tested during the manufacturing process using the SCAN test method.  
         [0053]     Frequency dividers  2  and  30  have been described in the particular situation where the number of cells of frequency dividers  2  and  30  is equal to four and eight, respectively. In another embodiment, depending on the maximum divider ratio to be adjusted, the number of cells can be greater or smaller.  
         [0054]     Frequency dividers  2  and  30  have been described in the particular situation where the cells of the shift register are flip-flops. However, other components selected from sequential logic components can be used to replace the flip-flops. However, care should be taken as to the signal propagation time of these other components that could be used to replace flip-flops.