Abstract:
System and method for capturing and enabling analysis of one or more test data packets from a radio frequency (RF) data packet signal transmitter device under test (DUT). Recently captured data packets from a received RF data packet signal are retained for analysis following confirmation that they contain potentially valid test data packets. Such confirmation is achieved by confirming that a data pattern defined by currently captured data packets differs from a data pattern defined by subsequently received data packets. Following such confirmation, a trigger signal initiates access and/or analysis of the captured data packets.

Description:
BACKGROUND 
       [0001]    The present invention relates to testing a radio frequency (RF) data packet signal transceiver device under test (DUT), and in particular, enabling analysis of previously received and captured test data packets following detected changes in received signal characteristics while the DUT continues to transmit further data packets. 
         [0002]    Many of today&#39;s electronic devices use wireless technologies for both connectivity and communications purposes. Because wireless devices transmit and receive electromagnetic energy, and because two or more wireless devices have the potential of interfering with the operations of one another by virtue of their signal frequencies and power spectral densities, these devices and their wireless technologies must adhere to various wireless technology standard specifications. 
         [0003]    When designing such wireless devices, engineers take extra care to ensure that such devices will meet or exceed each of their included wireless technology prescribed standard-based specifications. Furthermore, when these devices are later being manufactured in quantity, they are tested to ensure that manufacturing defects will not cause improper operation, including their adherence to the included wireless technology standard-based specifications. 
         [0004]    For testing these devices following their manufacture and assembly, current wireless device test systems employ a subsystem for analyzing signals received from each device. Such subsystems typically include at least a RF data packet signal transmitter, such as a vector signal generator (VSG), for providing the source signals to be transmitted to the device under test, and a RF data packet signal receiver, such as a vector signal analyzer (VSA), for receiving and analyzing signals produced by the DUT. The production of test signals by the VSG and signal analysis performed by the VSA are generally programmable so as to allow each to be used for testing a variety of devices for adherence to a variety of wireless technology standards with differing frequency ranges, bandwidths and signal modulation characteristics. 
         [0005]    When testing such devices, triggering is often used to initiate action on a subsequent test event. For example, in advance of a test packet to be sent (e.g., by the DUT to the tester), a trigger would alert the tester to prepare for it. However, this necessarily requires that the tester know ahead in time when to capture one or more portions of a sequence of data packets being transmitted, as well as when to initiate testing (e.g., analysis) of the captured data packets. Further complicating this approach is the tendency for semiconductor integrated circuits (ICs) to intersperse non-deterministic self-calibration in the midst of a sequence of test data packets being sent. Capturing and analyzing such events (e.g., sequences of self-calibration data packets) provides little to no test data of value and is often cause for a test-error report. 
         [0006]    Triggering often occurs in response to changes in one or more signal characteristics, following which action is taken on a following event. This means the device or system under test must know when the correct time is to respond and begin capturing packets. In many chipsets, some level of non-deterministic self-calibration is employed, which may be erroneously seen as an event to which the proper response is to begin capturing packets. Hence, it is necessary to detect these intervals of self-calibration and, once they have been completed, then begin processing (e.g., capturing or counting) packets. 
       SUMMARY 
       [0007]    In accordance with the presently claimed invention, a system and method are provided for capturing and enabling analysis of one or more test data packets from a radio frequency (RF) data packet signal transmitter device under test (DUT). Recently captured data packets from a received RF data packet signal are retained for analysis following confirmation that they contain potentially valid test data packets. Such confirmation is achieved by confirming that 
         [0008]    In accordance with one embodiment of the presently claimed invention, a system for capturing and enabling analysis of a plurality of test data packets from a radio frequency (RF) data packet signal transmitter device under test (DUT), including: 
         [0009]    data packet capture circuitry responsive to reception of a RF data packet signal, which includes at least one data packet sequence with a plurality of first data packets having respective first packet durations mutually separated by respective first inter-packet intervals, by capturing at least one of said plurality of first data packets and asserting a trigger signal when 
         [0010]    said plurality of first data packets includes a repeated first data packet pattern defined by at least said first packet durations and inter-packet intervals, and 
         [0011]    said RF data packet signal further includes, subsequent to said plurality of first data packets, 
         [0012]    a time interval different from said first inter-packet intervals and having no data packet, or 
         [0013]    a plurality of second data packets having respective second packet durations mutually separated by respective second inter-packet intervals, wherein said second packet durations and inter-packet intervals define a second data packet pattern different from said first data packet pattern; and 
         [0014]    data packet analysis circuitry coupled to said data packet capture circuitry and responsive to said asserted trigger signal by analyzing said captured at least one of said plurality of first data packets. 
         [0015]    In accordance with another embodiment of the presently claimed invention, a method for capturing and enabling analysis of a plurality of test data packets from a radio frequency (RF) data packet signal transmitter device under test (DUT), including: 
         [0016]    responding to reception of a RF data packet signal, which includes at least one data packet sequence with a plurality of first data packets having respective first packet durations mutually separated by respective first inter-packet intervals, by capturing at least one of said plurality of first data packets and asserting a trigger signal when 
         [0017]    said plurality of first data packets includes a repeated first data packet pattern defined by at least said first packet durations and inter-packet intervals, and 
         [0018]    said RF data packet signal further includes, subsequent to said plurality of first data packets, 
         [0019]    a time interval different from said first inter-packet intervals and having no data packet, or 
         [0020]    a plurality of second data packets having respective second packet durations mutually separated by respective second inter-packet intervals, wherein said second packet durations and inter-packet intervals define a second data packet pattern different from said first data packet pattern; and 
         [0021]    responding to said asserted trigger signal by analyzing said captured at least one of said plurality of first data packets. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]      FIG. 1  depicts a typical testing environment for a RF data packet signal transceiver. 
           [0023]      FIG. 2  depicts exemplary sequences of sequential data packets transmitted by a DUT for analysis by a tester in accordance with exemplary embodiments of the presently claimed invention. 
           [0024]      FIG. 3  depicts a test flow in accordance with exemplary embodiments of the presently claimed invention. 
           [0025]      FIG. 4  depicts an exemplary embodiment of data packet capture and analysis circuitry for implementation within a tester in accordance with exemplary embodiments of the presently claimed invention. 
           [0026]      FIG. 5  depicts another exemplary embodiment of data packet capture circuitry for implementation within a tester in accordance with exemplary embodiments of the presently claimed invention. 
           [0027]      FIG. 6  depicts another exemplary embodiment of data packet analysis circuitry for implementation within a tester in accordance with exemplary embodiments of the presently claimed invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
         [0029]    Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. Moreover, to the extent that the figures illustrate diagrams of the functional blocks of various embodiments, the functional blocks are not necessarily indicative of the division between hardware circuitry. 
         [0030]    When a DUT is engaged in a TX test with a tester (during which the tester is receiving and capturing data packets from the DUT for analysis), the DUT will send one or a sequence of test packets to the tester. Ordinarily, the tester would need to know when to expect the transmission of packets that are suitable for testing, and a trigger (e.g., from the DUT or another source such as an external controller) would precede the transmission, thus preparing the tester to capture the packet sequence that follows. As discussed in more detail below, in accordance with exemplary embodiments of the presently claimed invention, the trigger follows rather than precedes a packet sequence transmission, and the occurrence of the trigger depends upon the system knowing the characteristics (e.g., pattern(s)) of transmitted data packet signals. A benefit of this approach is avoidance of erroneous detections that can occur at the beginning of a packet sequence, following which subsequent packet capturing and other packet processing becomes offset in time. For example, if a self-calibration procedure is initiated and executed near the beginning of a packet sequence, a non-deterministic number of packets may be transmitted, thereby making it difficult to identify the desired packets to be captured or processed. Alternatively or additionally, the nominal power level of the packet sequence may not have settled, thereby making it difficult to capture desired packets among fluctuating packet power levels. However, in accordance with the presently claimed invention, the end of a packet sequence, which is well defined and not dependent on initial packet sequence conditions, can be advantageously used to trigger packet capturing and processing. 
         [0031]    As discussed in more detail below, in accordance with exemplary embodiments of the presently claimed invention, to enable the tester to avoid capturing non-test-related events, such as self-calibration, and avoid capturing packets with excessively variable power levels, triggering is used to prompt the tester to capture and analyze past events rather than future events. Incoming test packets are captured and retained in memory such that at any moment there will be some number of most recent packets, previously sent and temporarily stored in that memory. The memory serves as a buffer to provide, in effect, a rolling window of a previously sent number of packets determined by the chosen memory capacity. 
         [0032]    Referring to  FIG. 1 , in accordance with exemplary embodiments of the presently claimed invention, the testing environment  10  includes a tester  12  (e.g., including a VSG and VSA, as discussed above), the DUT  14  and a controller  18 , all interconnected substantially as shown. The controller  18  exchanges test commands and data via a control signal interface  19   a  between the controller  18  and DUT  14 , and a control signal interface  19   b  between the controller  18  and tester  12 . The controller  18  can be external to and separate from the tester  12  and DUT  14 , as depicted here, or, alternatively, can be included, in part or in whole, within the tester  12 . 
         [0033]    The test signal interface  16  between the tester  12  and DUT  14  is typically a conductive signal path, such as a RF coaxial cable and connectors  17   a,    17   b,  or, alternatively, a wireless signal path  16  serving as the communication medium between antennas  17   a,    17   b  associated with the tester  12  and DUT  14 . In accordance with well-known principles, this signal path  16  is used to convey data packet signals  13 ,  15  originating from the tester  12  and DUT  14 . 
         [0034]    Referring to  FIG. 2 , during transmit (TX) signal testing of the DUT  14 , multiple sequential data packet sequences  201 ,  202 ,  204 ,  206 ,  207 , . . . are transmitted by the DUT  14  as the TX signal  15  for reception and analysis by the tester  12 . These data packet sequences often include self-calibration sequences  201 ,  206  and test data packet sequences  202 ,  204 ,  207 , and include packets having respective packet durations mutually separated by respective inter-packet intervals  19 . These packet sequences  201 ,  202 ,  204 ,  206 ,  207 , . . . are further mutually separated by inter-sequence intervals  17 ,  203 ,  205 ,  21 ,  208 , . . . . The test data packet sequences  202 ,  204 ,  207  can be at the same frequency (or channel) or at different frequencies. Self-calibration sequences  201 ,  206  can occur following various signal events, including, without limitation, transmission of a predetermined number of TX data packets, changes in TX signal frequency or power, or timed events. 
         [0035]    As depicted here for this exemplary sequence of data packets, somewhere within this series of sequential data packet sequences, self-calibration is initiated, thereby introducing a self-calibration data packet transmission  201 , following which, after an inter-sequence interval  17 , test data packet sequences  202 ,  204  (separated by another inter-sequence interval  203 ) are transmitted. As shown, the self-calibration data packet sequence includes data packet transmissions having varying signal characteristics, such as signal power levels and data rates, and, as understood in the art, not otherwise consistent or associated with data packets expected to be received by the particular DUT  14  for purposes of ensuring accurate data reception. 
         [0036]    As shown, the test data packets within these test data packet sequences  202 ,  204 , following their preceding inter-sequence intervals  17 ,  203  (during which the signal transmitter circuitry is idled, e.g., turned off), initially have varying signal power levels as the newly active signal transmitter circuitry settles, following which the data packet signal levels settle at the intended nominal signal power level. The repeated packet durations and inter-packet intervals of one or both of these test data packet sequences  202 ,  204  together define a data packet pattern. 
         [0037]    Following another inter-sequence time interval  205 , the DUT  14  chipset may initiate and transmit another self-calibration data packet sequence  206 , which includes different packet durations and/or inter-packet intervals, thereby defining another data packet pattern which differs from the pattern defined by the preceding test data packet sequences  202 ,  204 . Further, the self-calibration data packet sequence  206  does not have a repeating pattern of packet durations and inter-packet intervals. This difference between these preceding and subsequent (e.g., adjacent) data packet patterns serves as a triggering event. Accordingly, capture and analysis of one or more of the test data packets of the preceding sequences  202 ,  204  are triggered. 
         [0038]    This self-calibration data packet sequence  206  is followed by another inter-sequence interval  21  prior to the next test data packet sequence  207 . However, Since the self-calibration data packet sequence  206  did not have a repeating pattern of packet durations and inter-packet intervals, the data packet pattern of the next test data packet sequence  207 , is not compared to the self-calibration data packet pattern for purposes of determining whether capture and analysis of any data packets are to be triggered. 
         [0039]    Subsequently, following the next data packet sequence  207 , which does include repeated packet durations and inter-packet intervals, and the subsequent time interval  208 , subsequent data packet patterns are monitored to determine whether and when further triggering events occur, thereby initiating capture and analysis of one or more preceding test data packets of this sequence  207  those that follow. 
         [0040]    Referring to  FIG. 3 , a test flow  40  in accordance with exemplary embodiments of the presently claimed invention proceed as shown. Following detection of initiation of a TX data packet signal  42 , the signal is monitored for detection of a repeated data packet pattern  44 , which can be defined based on various signal characteristics, including (without limitation) data packet durations, inter-packet intervals, or packet power levels. If no repeated data packet pattern is detected  43  (e.g., as discussed above), this monitoring  44  continues until such time as a repeated data packet pattern is detected (or a timeout interval has been exceeded). 
         [0041]    If a repeated data packet pattern is detected  45 , then capturing of the incoming data packets is enabled  46 . As incoming data packets are captured, they continue to be monitored for the repeated data packet pattern  48 . So long as the repeated data packet pattern continues to be detected  47 , this monitoring continues. Come such time as the repeated data packet pattern is no longer detected  49 , a predetermined number N of the most recently captured data packets are identified and conveyed or otherwise made accessible to appropriate resources for analysis  50 . If the test is deemed completed  53 , this test flow is exited. If the test is not deemed completed  51 , this test flow  40  is repeated. 
         [0042]    Hence, analysis of a predetermined number of the most recently captured data packets is ultimately initiated following either one of two events: (1) reception of one or more repeated data packet patterns followed by a time interval different from (e.g., longer than) the preceding inter-packet intervals and during which no data packet is received; or (2) reception of a data packet pattern different from the preceding repeated data packet pattern (e.g., a data packet pattern having one or more of different data packet durations, different inter-packet intervals, or different packet power levels). 
         [0043]    Referring to  FIG. 4 , the circuitry  100  for capturing and analyzing test data packets as discussed above can be co-located within the tester  12 , or, alternatively, can be located in part within the tester  12  and in part elsewhere in accordance with well-known techniques (e.g., with the data packet capture circuitry  102  located within the tester  12  and the analysis circuitry  104  located elsewhere and accessible via network communications). As discussed above, the test data packet sequence  15  is captured within data packet capture circuitry  102 . Following the occurrence of a trigger, as discussed above, the designated data packets  103  are analyzed by the analysis circuitry  104  to produce test results  105 . 
         [0044]    Referring to  FIG. 5 , in accordance with exemplary embodiments, the capture circuitry  102  can be implemented as receive circuitry  122  capable of providing any necessary signal conversion (e.g., signal frequency down conversion, analog-to-digital signal conversion, etc.) of the data packet sequence  15  to provide digital signal data  123   a  for storage in memory circuitry  124 . This digital signal data  123   b  is also monitored by detection circuitry  126  to recognize occurrences of triggering events (as discussed above). Following detection of a triggering event by the detection circuitry  126 , one or more control signals  103   b  are provided to the analysis circuitry  104  ( FIG. 3 ), in response to which the analysis circuitry  104  will access the predetermined number of test data packets  103   a  for analysis. 
         [0045]    Alternatively, the stored data  127   a  is monitored by the detection circuitry  126  to detect occurrences of triggering events (as discussed above). In response to a triggering event, the detection circuitry  126  provides one or more control signals  127   b  to the memory circuitry  124  to provide the predetermined number of data packets  103   a  for processing by the analysis circuitry  104 . Alternatively, the detection circuitry  126  can provide one or more control signals  103   b  to the analysis circuitry  104  indicating that a triggering event has been recognized, in response to which the analysis circuitry  104  can provide one or more control signals  125  to the memory circuitry  124  to access the desired number of test data packets  103   a.    
         [0046]    Referring to  FIG. 6 , in accordance with further exemplary embodiments, the analysis circuitry  104  can be implemented to include memory circuitry  142 , detection circuitry  144  and processing circuitry  146 . The capture circuitry  102  ( FIG. 3 ) can be implemented to provide any necessary conversion of the data packet sequence  15  (e.g., signal frequency down conversion, analog-to-digital signal conversion, etc.) to provide digital signal data  103  for storage in the memory circuitry  142 . This digital data  145   a  is monitored by the detection circuitry  144  to detect occurrences of triggering events (as discussed above). In response to a triggering event, the detection circuitry  144  provides one or more control signals  145   b  to the memory circuitry  142  to provide the predetermined number of data packets  143  for processing by the processing circuitry  146 . Alternatively, the detection circuitry  144  can provide one or more control signals  145   c  to the processing circuitry  146  indicating that a triggering event has been recognized, in response to which the processing circuitry  146  can provide one or more control signals  147  to the memory circuitry  142  to access the desired number of test data packets  143 . 
         [0047]    Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.