Abstract:
An image processing device includes a data zone expansion circuit and an image processing circuit. The data zone expansion circuit receives input data, increases a number of data bits of said input data, and provides data with the increased number of data bits. The image processing circuit performs image processing on said data with the increased number of data bits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an image processor incorporated in a display device such as a flat panel display device or a CRT display device, or connected to a display device. 
     2. Description of the Related Art 
     It has been required to improve image quality by processing digital image signals, in company with increase, in processing speed of an LSI. 
     FIG. 8 is a schematic block diagram showing a prior art image display device. 
     Digital image signals of three primary colors R, G and B are provided to respective image processing circuits  1 OR,  1 OG and  10 B to perform filtering processing such as edge enhancement, and the results thereof are provided through a display control circuit  12  to an LCD panel  14  to display pictures on the panel  14 . The display control circuit  12  includes a multi-port VRAM and a control circuit therefor. 
     However, as shown in FIG. 9, when an edge enhancement processing is followed by clipping in regions where pixels are saturated at the maximum value MAXO or the minimum value no effect of the edge enhancement processing can be achieved. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a image processor capable of effectively performing an image processing such as an edge enhancement processing even in a region of saturated pixel values, with a simple construction. 
     In one aspect of the present invention, there is provided an image processing circuit comprising: a data zone expansion circuit, receiving input data X, expanding a data zone of the input data by linearly converting X to (αX+β), where α and β are given values, providing the data-zone expanded data (αX+β); and an image processing circuit, performing image processing on the data-zone-expanded data (αX+β). 
     In the prior art, when an edge enhancement processing is applied on image data, an image processing effect such as edge enhancement could not be achieved in pixel value 
     saturated regions at the maximum or minimum value. Such an effect can be achieved with this aspect having a simple construction that the data zone expansion circuit is provided at the preceding stage of the image processing circuit, thereby contributing to improvement in image quality. 
     Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram showing an image display device of a first embodiment according to the present invention; 
     FIG. 2 is a block diagram showing an embodiment of the data zone expansion circuit of FIG. 1; 
     FIG. 3 is a block diagram showing an embodiment of the data zone contraction circuit of FIG. 1; 
     FIG. 4 is a graph showing a result of data zone expansion on data of FIG. 9, wherein an abscissa represents a pixel position on a display line and an ordinate represents a pixel value; 
     FIG. 5 is a graph showing a result of an edge enhancement processing on data of FIG. 4; 
     FIG. 6 is a graph showing a result of data zone contraction on data of IG.  5 ; 
     FIG.  7 (A) is a block diagram showing a data zone expansion circuit employed in an image processor of a second embodiment according to the present invention; 
     FIG.  7 (B) is a block diagram showing a data zone contraction circuit employed in this image processor; 
     FIG. 8 is a schematic block diagram showing a prior art image display device; and 
     FIG. 9 is a graph showing an example of image data from which no effect is achieved even after an edge enhancement processing therefor with the display device of FIG.  8 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings, wherein like reference characters designate like or corresponding parts throughout several views, preferred embodiments of the present invention are described below. 
     First Embodiment 
     FIG. 1 is a schematic block diagram showing an image display device of a first embodiment according to the present invention. 
     Digital image signals in three primary colors R, G and B are provided to data zone expansion circuits  16 R,  16 G and  16 B, respectively. 
     The data zone expansion circuit  16 R linearly converts an input signal R in a range of 0 to MAXO to an output signal (αX R+β), in a range of 0 to MAX 1  in order to 
     accommodate the output signal with sufficient upper and lower margins. Herein, MAX 1 &gt;MAXO, and α and β are constants satisfying conditions of α&gt;1 and β≧0. For simplification of a circuit, generally, α=2 n , n is a positive integer and a is 0 or a positive integer. 
     For example, the input signal R is a signal as shown in FIG. 9 having a pixel position on a display line as a time axis, and is converted to a signal shown in FIG.  4 . 
     The minimum value  0  and the maximum value MAXO of the input signal R are converted to β and α X MAXO+β, respectively, and the following relation holds in order to accommodate the output signal with sufficient upper and lower margins. 
     
       
         0&lt;β&lt;α X MAXO+β&lt;MAX   1   
       
     
     That is, the converted minimum value β and the converted maximum value (αX MAXO+β) are within an output data range of 0 to MAX 1 . 
     FIG. 2 shows an embodiment of the data zone expansion circuit  16 R. 
     The data zone expansion circuit  16 R includes an adder  161  and an offset register  161 . 
     Assume that the input signal R has 8 bits R 7  to R 0 . A first data input of the adder  161  is of 9 bits, and the R 7  to RO bits are provided to the higher 8 bits D 8  to D 1  thereof while ‘0’ is provided to the lowest one bit DO. That is, α=2. The second data input of the adder  161  is, for example, of 4 bits, and the output a of the offset register  162  is provided to the second data input. A data output of the adder  161  is of 9 bits and an output of the data zone expansion circuit  16 R is 10 bits having the 9 bits of the output and a carry bit C of the adder  161 . In this case, the output data length of the data zone expansion circuit  16 R is 10 bit for the input 8 bits. 
     This applies to cases of the data zone expansion circuits  16 G and  16 B in a similar manner. 
     Corresponding outputs from the data zone expansion circuits  16 R,  16 G and  16 B are provided to image processing circuits  20 R,  20 G and  20 B, respectively. 
     The image processing circuit  20 R differs from the image processing circuit  1 OR of FIG. 8 in that a word length of a pixel value to be processed is larger than that of the input signal R. In the image processing circuit  20 R, a filtering processing is performed such as edge enhancement or interpolation accompanying zoom in or out of an image. For example, when an edge enhancement processing is performed on image data shown in FIG. 4 by the image processing circuit  20 R, data shown in FIG. 5 is obtained as a result. 
     This applies to cases of the image processing circuits  20 G and  20 B in a similar manner. 
     A display control circuit  12  and an LCD panel  14  have the same constructions as those of FIG.  8 . Therefore, data zone contraction circuits  18 R,  18 G and  18 B are connected between the respective image processing circuits  20 R,  20 G and  20 B and the display control circuit  12 , and perform the inverse of processing of the data zone expansion circuits  16 R,  16 G and  16 B. 
     FIG. 3 shows an embodiment of the data zone contraction circuit  18 R. 
     The data contraction circuit  18 R includes a subtracter  181  and an offset register  182 . 
     An output RI of the image processing circuit  20 R is of 10 bits and provided to a first data input of the subtracter  181 . The second data input of the subtracter  181  is, for example, of 4 bits and the output β of the offset register  182  is provided to the other data input. The carry C of the subtracter  181  is not used as one bit of the output of the data zone contraction circuit  18 R. The output data of the subtracter  181  is of 9 bits D 08  to DOO and the higher 8 bits D 08  to D 01  are of:the output DO=(RI−β)/α of the data zone contraction circuit  18 R. 
     This applies to cases of the data zone contraction circuits  18 G and  18 B in a similar manner. 
     For example, the data of FIG. 5 having a pixel position on a display line as a time axis is provided to the data zone contraction circuit  18 R, and is converted to a signal shown in FIG.  6 . 
     In the prior art, when an edge enhancement processing is performed on image data shown in FIG. 9, no effect of edge enhancement is achieved in saturated regions at the minimum value and the maximum value of pixels, while the effect can be achieved according to the first embodiment, leading to improvement on the image quality. 
     As a result of experiments, in a case where the input signals R, G and B are all of 8 bits and the word length of the output data of the data expansion circuit  16 R is of 10 bits, the above described effect of the edge enhancement is able to be achieved when β=2 for the offset registers  162  and  182 . 
     According to the first embodiment, it has a simple construction in which the data zone expansion circuit  16 R and the data zone contraction circuit  18 R are provided at stages before and after the image processing circuit  20 R, respectively, and the image processing can be performed even in the pixel value saturated regions with improved image quality. 
     Second Embodiment 
     FIG.  7 (A) shows a data zone expansion circuit  16 RA employed in an image processor of a second embodiment according to the present invention. 
     The circuit  16 RA includes a 9 bit up-counter. The output of the data zone expansion circuit  16 RA has a parallel output obtained by providing one pulse of a clock to the clock input CK after a parallel input R 7  to RO is loaded on the counter, and an added lowest bit “0”. The output is 2(R+1)=2R+2 for the input R. That is, α=2 and β=2. 
     FIG.  7 (B) shows a data zone contraction circuit  18 RA employed in the image processor of the second embodiment according to the present invention. 
     The data zone contraction circuit  18 RA includes a 10 bit down-counter. A parallel input RI 9  to RIO is loaded on the counter, 2 pulses of the clock  0  are provided to the clock input CK thereof, and the output of the data zone contraction circuit  18 R is obtained from an intermediate 8 bit parallel output D 08  to D 01  excluding LSB and MSB among 10 bits. The output is (RI−2)/2 for the input RI. That is, α=2 and β=2. 
     The other points are the same as those of the first embodiment. 
     Although preferred embodiments of the present invention has been described, it is to be understood that the invention is not limited thereto and that various changes and modifications may be made without departing from the spirit and scope of the invention. 
     Please note that various other kinds of modifications or alterations can be included in the present invention. 
     For example, there may be adopted a construction in which the data zone contraction circuit is omitted in FIG.  1 . 
     Further, a linear transformation in the data zone contraction circuit is not limited to the inversion of the processing of the data zone expansion circuit. Accordingly, the output word length of the data zone contraction circuit may be different from. the input word length of the data zone expansion circuit. 
     Furthermore, The value of β set in the offset register may be determined according to a lightness or a chroma of image. Fixed values may be provided to the adder  16  and the subtracter  181  without using the offset registers.