Abstract:
In prior arts, additional pulse-width modulators and more costs are needed for increasing the current output. The invention provides a synchronized parallel running power converter. The power converter includes multiple power converters controlled by single-phase or double-phase pulse-width modulators. Each power converter includes a first pulse input port, a second pulse input port and a current output port. Each first pulse input ports are coupled, and each second pulse input ports are coupled also, so that each power converter is controlled by the same pulse signal and provide a same output current to be added as several times of current output.

Description:
This Non-provisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 092124503 filed in Taiwan on Sep. 4, 2003, the entire contents of which are hereby incorporated by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention generally relates to a power converter, and in particular relates to multiple power converters running in parallel and synchronously. 
   2. Related Art 
   In conventional power converters, parallel circuits are used to increase the current output while preventing from power loss and heat generation caused by current increasing on each circuit. 
   As shown in  FIG. 1 , a power converter of prior arts includes a pulse-width modulator  10 , a first transistor TR 1 , a second transistor TR 2  and an inductor L 1 . The drain terminal of the first transistor TR 1  is connected to the power source Vdd. The source terminal of the first transistor TR 1  is connected to the drain terminal of the second transistor TR 2 . The source terminal of the second transistor TR 2  is connected to the ground. The pulse-width modulator  10  provides an oscillating pulse to the gates of the first and second transistors TR 1 , TR 2  via a first resistor R 1  and second resistor R 2 . When the pulse of the pulse-width modulator  10  is at the positive cycle, the first transistor TR 1  is on and the second transistor is off; a current flows through the first transistor TR 1  to the first inductor L 1 , as the illustrated path P 1 , and stored energy in the first inductor L 1 . When the pulse of the pulse-width modulator  10  is at the negative cycle, the first transistor TR 1  is off and the second transistor is on; the first inductor L 1  releases energy through a reversed path P 2 . Therefore, the first inductor L 1  is charged and discharged corresponding to the pulse oscillation, and provides a stable current to a CPU  70 . A capacitor C 1  is connected between the power input and the ground of the CPU  70  for voltage regulation. 
   In the power converter circuit of  FIG. 1 , the inductor L 1  provides a current I to the CPU  70 . If the CPU  70  requires twice of current 2I, then another power converter has to be added in parallel as shown in  FIG. 2 , in which a third transistor TR 3 , a fourth transistor TR 4 , a third resistor R 3 , a fourth resistor R 4  and a second inductor L 2  are linked and function in the same way of  FIG. 1 . The current output of the first inductor L 1  is I 1 . The current output of the second inductor L 2  is I 2 . If I 1 =I 2 =I, then the total current output It=I 1 +I 2 =2I. 
   There is a limitation in the operation of the power converter of  FIG. 2 . That is, the pulse-width modulator  10  and the pulse-width modulator  20  have to work synchronously. Otherwise, the current outputs of the first inductor L 1  and the second inductor L 2  are unbalanced. Then, for a certain load of current It, one of the inductor L 1  and L 2  has to provide a larger current than the original current I that will cause overload of the components. For this problem, an additional current-balancing circuit has to be used for controlling the currents in both paths to the regular range. 
   As described above in  FIG. 1  and  FIG. 2 , for controlling multiple power converters of prior arts, additional pulse-width modulators and current-balancing circuits are required, and the costs are increased accordingly. Therefore, it is a demand to have a simpler structure of power converter that has a lower cost for benefits to customers and the manufacturer. 
   SUMMARY OF THE INVENTION 
   The object of the invention is to provide a synchronized parallel running power converter. The power converter includes pulse-width modulators and power converters without other current-balancing circuit so as to save cost and remain the same electric characteristics of common power converters. 
   In a first embodiment of the invention, a synchronized parallel running power converter includes a first power converter and a second power converter controlled by a single-phase pulse-width modulator. The single-phase pulse-width modulator has a first pulse output port and a second pulse output port for pulse outputs. The first power converter includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the first pulse output port of the single-phase pulse-width modulator. The second pulse input port is coupled to the second pulse output port of the single-phase pulse-width modulator. 
   In a second embodiment of the invention, a synchronized parallel running power converter includes a first power converter, a second power converter, a third power converter and a fourth power converter controlled by a double-phase pulse-width modulator. The double-phase pulse-width modulator has a first pulse output port, a second pulse output port, a third pulse output port and a fourth pulse output port for pulse outputs. The first power converter includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the first pulse output port of the double-phase pulse-width modulator. The second pulse input port is coupled to the second pulse output port of the double-phase pulse-width modulator. The second power converter includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the first pulse output port of the double-phase pulse-width modulator. The second pulse input port is coupled to the second pulse output port of the double-phase pulse-width modulator. The third power converter includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the third pulse output port of the double-phase pulse-width modulator. The second pulse input port is coupled to the fourth pulse output port of the double-phase pulse-width modulator. The fourth power converter includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the third pulse output port of the double-phase pulse-width modulator. The second pulse input port is coupled to the fourth pulse output port of the double-phase pulse-width modulator. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will become more fully understood from the detailed description given hereinbelow. However, this description is for purposes of illustration only, and thus is not limitative of the invention, wherein: 
       FIG. 1  is a circuit diagram of a power converter of prior arts; 
       FIG. 2  is a circuit diagram of a multiple power converter of prior arts; 
       FIG. 3  is a power converter as a first embodiment of the invention; and 
       FIG. 4  is a power converter as a second embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   As shown in  FIG. 3 , a first embodiment of the invention, a synchronized parallel running power converter includes a first power converter  50  and a second power converter  60  controlled by a single-phase pulse-width modulator  30 . The single-phase pulse-width modulator  30  has a first pulse output port and a second pulse output port for pulse outputs. The first power converter  50  includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the first pulse output port of the single-phase pulse-width modulator  30 . The second pulse input port is coupled to the second pulse output port of the single-phase pulse-width modulator  30 . 
   The first power converter  50  at least includes a first transistor TR 1 , a second transistor TR 2  and a first inductor L 1 . The drain terminal of the first transistor TR 1  is connected to the power source Vdd. The source terminal of the first transistor TR 1  is connected to the drain terminal of the second transistor TR 2 . The source terminal of the second transistor TR 2  is connected to the ground. The pulse-width modulator  30  provides an oscillating pulse from the first pulse output port to the gate terminal of the first transistor TR 1  via a first resistor R 1 . The pulse-width modulator  30  provides an oscillating pulse from the second pulse output port to the gate terminal of the second transistor TR 2  via a second resistor R 2 . The first resistor R 1  and the second resistor R 2  are for current limitation in order to protect the transistors TR 1  and TR 2 . The first inductor L 1  is coupled between the source terminal of the first transistor TR 1  and the current output port of the first power converter  50 . The output current I 1  of the first power converter  50  is provided from the current output port. 
   When the pulse of the pulse-width modulator  30  is at the positive cycle, the first transistor TR 1  is on and the second transistor is off; a current flows through the first transistor TR 1  to the first inductor L 1 , as the illustrated path P 1 , and stored energy in the first inductor L 1 . When the pulse of the pulse-width modulator  30  is at the negative cycle, the first transistor TR 1  is off and the second transistor is on; the first inductor L 1  releases energy through a reversed path P 2 . 
   The second power converter  60  at least includes a third transistor TR 3 , a fourth transistor TR 4  and a second inductor L 2 . The drain terminal of the third transistor TR 3  is connected to the power source Vdd. The source terminal of the third transistor TR 3  is connected to the drain terminal of the fourth transistor TR 4 . The source terminal of the fourth transistor TR 4  is connected to the ground. The pulse-width modulator  30  provides an oscillating pulse from the first pulse output port to the gate terminal of the third transistor TR 3  via a third resistor R 3 . The pulse-width modulator  30  provides an oscillating pulse from the fourth pulse output port to the gate terminal of the fourth transistor TR 4  via a fourth resistor R 4 . The third resistor R 3  and the fourth resistor R 4  are for current limitation in order to protect the transistors TR 3  and TR 4 . The third inductor L 3  is coupled between the source terminal of the third transistor TR 3  and the current output port of the second power converter  60 . The output current I 2  of the second power converter  60  is provided from the current output port. 
   When the pulse of the pulse-width modulator  30  is at the positive cycle, the third transistor TR 3  is on and the fourth transistor is off; a current flows through the third transistor TR 3  to the second inductor L 2 , as the illustrated path P 1 , and stored energy in the second inductor L 2 . When the pulse of the pulse-width modulator  30  is at the negative cycle, the third transistor TR 3  is off and the second transistor is on; the second inductor L 2  releases energy through a reversed path P 2 . 
   The first, second, third and fourth transistors TR 1 , TR 2 , TR 3  and TR 4  are metallic oxide semiconductor field effect transistors (MOSFET). 
   In the embodiment of  FIG. 3 , two power converters run in parallel and synchronously so as to solve the problems of prior arts. The first and second inductors L 1  and L 2  store energy in the path P 1 , and release energy in the path P 2 . The invention connects the first pulse input ports of the two power converters  50 ,  60  to the first pulse output port of the single-phase pulse-width modulator  30  so that the first transistor TR 1  of the first power converter  50  and the third transistor TR 3  of the second power converter  60  can on and off synchronously; and the second transistor TR 2  of the first power converter  50  and the fourth transistor TR 4  of the second power converter  60  can on and off synchronously. As a result, the first power converter  50  and the second power converter  60  have a same pulse width and current output, and the total current output It=I 1 +I 2 =2I. 
   From the aforesaid first embodiment, we can see that only a pulse-width modulator is needed for controlling two power converters. In comparison to prior arts, the invention requires only one (half of prior arts) pulse-width modulator to obtain a same current output. 
   As shown in  FIG. 4 , a second embodiment of the invention, a synchronized parallel running power converter includes four power converters  50 ,  60 ,  80  and  90  and a double-phase pulse-width modulator  40 . The double-phase pulse-width modulator  40  has a first pulse output port, a second pulse output port, a third pulse output port and a fourth pulse output port for pulse outputs. The first power converter  50  includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the first pulse output port of the double-phase pulse-width modulator  40 . The second pulse input port is coupled to the second pulse output port of the double-phase pulse-width modulator  40 . The second power converter  60  includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the first pulse output port of the double-phase pulse-width modulator  40 . The second pulse input port is coupled to the second pulse output port of the double-phase pulse-width modulator  40 . 
   The third power converter  80  includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the third pulse output port of the double-phase pulse-width modulator  40 . The second pulse input port is coupled to the fourth pulse output port of the double-phase pulse-width modulator  40 . The fourth power converter  90  includes a first pulse input port, a second pulse input port and a current output port. The first pulse input port is coupled to the third pulse output port of the double-phase pulse-width modulator  40 . The second pulse input port is coupled to the fourth pulse output port of the double-phase pulse-width modulator  40 . 
   The current output ports of the first, second, third and fourth power converters  50 ,  60 ,  80  and  90  are coupled together so that the total output current is It=I 1 +I 2 +I 3 +I 4 . Through the control of the double-phase pulse-width modulator  40 , the currents I 1 , I 2 , I 3  and I 4  are equal and four times of the current is obtained. 
   The compositions of the first power converter  50  and the second power converter  60  are similar to that of the first embodiment. The third power converter  80  includes a fifth transistor TR 5 , a sixth transistor TR 6 , a fifth resister R 5 , a sixth resister R 6  and a third inductor L 3 . The fourth power converter  90  includes a seventh transistor TR 7 , an eighth transistor TR 8 , an seventh resister R 7 , a eighth resister R 8  and a fourth inductor L 4 . The composition and function of the third power converter  80  and the fourth power converter  90  are the same as that of the first embodiment. 
   From the aforesaid second embodiment, we can see that only two pulse-width modulators are needed for controlling four power converters. In comparison to prior arts, the invention requires only one (half of prior arts) pulse-width modulator to obtain a same current output. 
   The power converter of the invention not only saves the quantity of pulse-width modulators and saves the cost, but also balances the currents in the parallel paths. 
   The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.