Abstract:
An amplifier ( 10 ″) has a first amplifier stage ( 14 ) for producing a control current (I X ) in response to an input voltage. A second amplifier stage ( 16 ) has first ( 46 ) and second ( 38 ) transistors. The first transistor ( 46 ) is coupled to receive the control current (I X ) and is operable to produce a control voltage. The second transistor ( 38 ) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element ( 50 ) is coupled to the first transistor ( 46 ) to add a nonlinear function of the control current (I X ) to the control voltage. The nonlinear resistive element ( 50 ) may include a third transistor connected between the first transistor ( 46 ) and a reference potential, operable to receive the control current (I X ) and to generate the nonlinear function thereof.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of Invention  
         [0002]     This invention relates to improvements in electrical circuits, and more particularly to circuits and methods for fast response current limiting.  
         [0003]     2. Relevant Background  
         [0004]     A prior-art two-stage amplifier  10  is shown in  FIG. 1  for driving an output circuit  12 , having a load, R L ,  18  and an nMOS output power transistor, M POWER ,  20 . The circuit  10  may be, for example, an integrated circuit, with the circuit  12  provided either as a part thereof, or externally connected thereto.  
         [0005]     The amplifier  10  has two stages  14  and  16 . The first amplifier stage  14  has two PNP transistors Q 1 ,  22 , and Q 2 ,  24 , which have an emitter area ratio of 1X/NX. The transistors  22  and  24  have respective associated nMOS current mirror transistors M 2 ,  26 , and M 3 ,  28 . The transistors  26  and  28  mirror the current in nMOS transistor M 1 ,  30 , which is connected to current source  32  that provides a current I B  thereto. If the nMOS transistors  26  and  28  are designed to conduct equal currents, an input-referred voltage offset V PTAT  will occur between the PNP transistors  22  and  24  due to their size differences and resulting different current densities therein. Assuming transistors  22  and  24  operate in low-level injection, the magnitude of the voltage offset equals 
 
 V   PTAT   =V   T   ln ( N )  [ 1 ]
        where V T  is the thermal voltage (V T =kT/q, where k is Boltzmann&#39;s constant, T is the absolute temperature, and q is the charge on the electron), and where N is the emitter ratio as described above).        
 
         [0007]     Since the circuit  10  is preferably fabricated as a single integrated circuit, the resistor R Al  across which the input voltage is developed is preferably constructed of aluminum metallization, which has a temperature coefficient of about 3000 ppm/° C. The temperature coefficient of the resistor then matches (at least approximately) the temperature coefficient of the voltage V PTAT . Therefore the current limit I lim  generated by circuit  10  is largely independent of temperature. This current limit equals  
               I     li   ⁢           ⁢   m       =         V   τ     ⁢     ln   ⁡     (   N   )           R   Al               [   2   ]             
 
         [0008]     In response to the input voltage across R Al , the first amplifier stage  14  generates a current I X  that is sunk into MOS transistor M 4  of the second amplifier stage  16 . The magnitude of current I X  equals:  
               I   x     =       I   s     ⁢     exp   (         V   IN     -     V   PTAT         V   τ       )               [   3   ]             
        where I s  is the saturation current of Q 1 , and V IN  equals the differential voltage appearing across resistor R Al . The current I  X  is referred to herein as a “control current”.        
 
         [0010]     The second amplifier stage  16  includes a first nMOS transistor M 4 ,  46 , connected to receive the control current I x , and a second nMOS transistor M 5 ,  38 , connected to a current source  40 , which provides a current I CP .  
         [0011]     The first transistor  46  amplifies the control current I X  to develop a control voltage, which is applied to the gate of the second transistor  38 . The second transistor  38  generates an output current, which, in the embodiment illustrated controls the voltage at the gate of the output power transistor  20 .  
         [0012]     The frequency response of the amplifier of circuit  10  has two important poles. The first is an internal pole caused by capacitance C X  acting against the resistance at node  36 . The second is a gate pole caused by the capacitance C g  acting against the resistance at node  43 . In order to maintain adequate stability, the gain of the circuit must drop below unity before the phase margin drops below about 30°. This requires either that one of the poles be pushed back to a very low frequency (dominant-pole compensation) or that the gain of the circuit be artificially reduced.  
         [0013]     Dominant-pole compensation is greatly complicated by the movement of the gate pole due to variations in effective gate capacitance C g  with load resistance R L . If R L  is shorted, then C g  includes a large contribution from the gate-to-source capacitance C gs  of the output power transistor  20 . Larger values of R L  decrease the contribution of C gs  to C g . Dominant-pole compensation can still be achieved either by adding a large capacitance to node  43 , or by connecting a Miller capacitance around transistor  38 , but both solutions have the undesirable property of slowing the transient response of the amplifier.  
         [0014]     The addition of transistor  46  greatly reduces the resistance at node  36 . This has two beneficial effects. First, it reduces the loop gain, and second, it pushes the internal pole out to a higher frequency, effectively forcing the gate pole to become the dominant pole of the system. The addition of transistor  46  therefore compensates the amplifier without requiring the addition of any extraneous capacitance. The offset introduced by current I X  can be compensated by drawing an equal current from node  45 .  
         [0015]     The circuit of  FIG. 1  responds relatively rapidly to large input signals, such as those generated by hot-shorting the load R L . The current available to slew the gate capacitance is the current in transistor  38 , which equals  
               I   M5     =           (     W   /   L     )     3         (     W   /   L     )     4       ⁢     I   x               [   4   ]             
        where (W/L) 5  and (W/L) 4  are respectively the width to length ratios of the nMOS transistors M 5 ,  38 , and M 4 ,  46 . As equation [3] indicates, this current is exponentially dependent upon the magnitude of the input voltage. This equation does not consider the terminal resistances of transistors  22  and  24 , nor their finite betas. These factors will ultimately limit the current I X , and through it, the response time of circuit  10 .        
 
       SUMMARY OF INVENTION  
       [0017]     In light of the above, the invention, in accordance with a broad aspect thereof, presents an amplifier. The amplifier has a first amplifier stage for producing a control current in response to an input voltage. A second amplifier stage has first and second transistors. The first transistor is coupled to receive the control current and is operable to produce a control voltage. The second transistor is coupled to receive the control voltage and is operable to produce an output current. A nonlinear resistive element is coupled to the first transistor to add a nonlinear function of the control current to the control voltage. In one embodiment, the nonlinear resistive includes a third transistor connected between the first transistor and a reference potential, the third transistor operable to receive the control current and to generate the nonlinear function of the control current.  
         [0018]     In accordance with another broad aspect of the invention, a circuit is presented that has an amplifier for producing a control current in response to an input voltage and a control voltage in response to the control current. A circuit is provided for producing an output current in response to the control voltage. A nonlinear resistive element is also provided for adding voltage that is a nonlinear function of the control current to the control voltage. An output stage is driven in response to the output current.  
         [0019]     In accordance with still another broad aspect of the invention, a method is presented for controlling an output current of a circuit. The method includes producing a control current in response to an input voltage and a control voltage in response to the control current, producing an output current in response to the control voltage, providing a nonlinear resistive element for adding voltage that is a nonlinear function of the control current to the control voltage, and driving an output stage in response to the output current.  
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0020]      FIG. 1  is a two-stage amplifier circuit, according to the prior art.  
         [0021]      FIG. 2  is a two-stage amplifier circuit showing an example of an incorporation therewith of a nonlinear resistive element, according to a preferred embodiment of the invention.  
         [0022]      FIG. 3  is a two-stage amplifier circuit additionally showing circuitry for sinking additional currents, according to another preferred embodiment of the invention.  
         [0023]      FIG. 4  is a two-stage amplifier circuit further showing circuitry for reducing capacitive effects of at least some circuit elements, according to still another preferred embodiment of the invention. 
     
    
       [0024]     In the various figures of the drawing, like reference numerals are used to denote like or similar parts.  
       DETAILED DESCRIPTION  
       [0025]     With reference now additionally to the circuit  10 ′ of  FIG. 2 , a third nMOS transistor M 6 ,  50 , is shown connected between the source of the first nMOS transistor  46  and ground. The third transistor  50  may be an nMOS device, as in the embodiment shown. Those skilled in the art will recognize that the circuit  10 ′ may be constructed with transistors of different types, (i.e., lateral, vertical, bipolar, MOSFET, and on) and conductivities (i.e., PNP, NPN, nMOS, PMOS, and so on), and that other circuit components (not shown) for collateral purposes may also be employed within the circuit  10 ′.  
         [0026]     First transistor  46 , although necessary in order to ensure stability, slows the transient response of circuit  10 ′. The first transistor  46  draws off current that could otherwise transiently charge capacitance  42 . Furthermore, since the current provided by PNP transistor  22  is limited by beta and terminal resistances, the first transistor  46  effectively clamps the voltage swing seen at the node  36 , and thus limits the maximum current that the second transistor  38  can sink. The slower transient performance increases the time required to turn off the output transistor  20  in the event of a severe overcurrent condition, such as a short circuit. However, these and other issues are addressed by the addition of the third transistor  50 .  
         [0027]     The third transistor  50  is sized to provide a much smaller drain-to-source resistance than the first transistor  46  when the circuit  10 ′ operates at or near equilibrium (V IN ≈V PTAT ). In the embodiment shown, this entails sizing the third transistor  50  so that it operates in the triode (or linear) region when the circuit is at or near equilibrium, and further constructing the third transistor  50  to have a much larger width-to-length ratio than the first transistor  46 .  
         [0028]     The drain-to-source resistance of the third transistor  50  will dramatically increase when the current flowing through it exceeds a threshold value. In the embodiment shown, this increase in resistance corresponds to the transition from the triode region to the saturation region. Thus, the third transistor  50  is sized so that this transition occurs only when the circuit is perturbed from its equilibrium condition (V IN &gt;&gt;V PTAT ).  
         [0029]     In or near equilibrium, the drain-to-source resistance of third transistor  50  is much smaller than that of the first transistor  46 . Thus, circuit  10 ′ operates essentially in the manner as the above-described circuit  10 . However, if circuit  10 ′ is perturbed from equilibrium, for example by a short-circuiting of the load resistance R L , then the current I X  will increase to the point that the third transistor  50  enters saturation. At this point, the current flow through the first transistor  46  is effectively choked off by the large drain-to-source resistance of the third transistor  50 . Any increase in current I X  above and beyond that required to saturate the third transistor  50  will then go to charge capacitance  42  and slew node  36 . Furthermore, the voltage of node  36  will no longer be limited by the current that the PNP transistor  22  can deliver. Therefore circuit  10 ′ will slew substantially faster than prior-art circuit  10 .  
         [0030]     When the third transistor  50  saturates, the pole created by parasitic capacitor  42  moves in to lower frequencies. If the circuit were operating at equilibrium, this would erode the phase margin and could potentially cause the circuit to become unstable. However, third transistor  50  only saturates when circuit  10 ′ is far from equilibrium. As the circuit approaches equilibrium, the third transistor  50  drops back into triode mode, and the pole created by parasitic capacitor  42  moves out to higher frequencies. Therefore circuit  10 ′ exhibits stable operation at equilibrium in combination with rapid slewing when far from equilibrium.  
         [0031]     More generally, the third transistor  50  may be viewed as a nonlinear resistive element that adds a nonlinear function of the control current, I X , to the control voltage that is generated by the first transistor  46 . This nonlinear function is only weakly dependent upon the control current up to a certain threshold, beyond which the control voltage increases very rapidly as a function of the control current. This threshold is selected so as to lie well above the control current, I X , expected to flow under equilibrium conditions. It should be understood that the third transistor  50  can be replaced with any circuit element that operates in a manner similar to that described above. This results in the advantages described above, and, more particularly, extends the use of the circuit of  FIG. 1  to enable it to be used with discrete power transistors which operate at much larger voltages.  
         [0032]     It should be emphasized that although the third transistor  50  is shown and described above in the context of a MOS device, and more particularly, and nMOS device, it may be a pMOS device, a bipolar transistor, or other appropriate device. If a bipolar transistor is used for the third transistor  50 , it would be biased such that at or near equilibrium, the transistor would operate in a saturation mode, and away from equilibrium, the transistor would operate in a forward-active mode. The bipolar transistor also can be either a PNP or NPN device, depending upon the particular circuit construction employed.  
         [0033]     It should be noted that the output power transistor  20 , particularly if it is externally provided, should have a low on-resistance in order to prevent excessive conduction losses. However, during a hot-short event, this low on-resistance may allow extremely large currents to flow. The magnitude of these currents, coupled with the large voltages present across the transistor, can produce extreme levels of power dissipation, which in some cases may be in the kilowatt range. In such cases, the output power transistor  20  needs to be turned off very quickly, typically within a microsecond or two, in order to prevent its destruction. Moreover, a large external output power transistor may have a correspondingly large gate capacitance, which makes it even more difficult to turn off quickly. Thus, an amplifier circuit that can sink large currents and slew rapidly is of great practical significance for current limiting applications.  
         [0034]     The addition of the third transistor  50  improves the slew rate response of the circuit  10 ′ and (in most cases) increases the maximum current that the second transistor  38  can sink. However, the benefits of the third transistor  50  are limited by certain practicalities of circuit design, most notably the sizing requirements for transistor  38 .  
         [0035]     If additional sinking current is desired, additional circuitry may be added, as shown in the circuit  10 ″ of  FIG. 3 , to which reference is now additionally made. Circuit  10 ″ includes a booster circuit comprising a fourth nMOS transistor M 7 ,  52 . Although an nMOS device is shown, those skilled in the art will appreciate that other types and conductivities of devices may be used, depending upon the particular construction of the circuit  10 ″. The fourth transistor  52  may be a large device that can sink a correspondingly large current. When circuit  10 ″ operates at or near equilibrium, the voltage developed across third transistor  50  is insufficient to bias the fourth transistor  52  into conduction. Furthermore, the large gate capacitance of the fourth transistor  52  is shunted to ground through the relatively low drain-to-source resistance of the third transistor  50 , effectively suppressing any pole or zero that this gate capacitance might otherwise have generated. Therefore, while at or near equilibrium, circuit  10 ″ acts in much the same way as circuit  10 .  
         [0036]     When the third transistor  50  is biased into saturation, the potential on node  53  rises, turning on the fourth transistor  52 . The fourth transistor  52  provides additional sinking current to help pull the gate of the output power transistor  20  to ground. This action is in addition to the action of the second transistor  38  of the second amplifier stage  16 , which also serves to pull down the gate of the output power transistor  20  to ground.  
         [0037]     In the operation of the circuit  10 ″, when the third transistor  50  saturates, current I X  charges the gate capacitance of the fourth transistor  52 . If the fourth transistor  52  is very large, its gate capacitance may slow the slew of the circuit, thereby slowing the overall response time. In such cases, the circuit embodiment  10 ′″ of  FIG. 4 , to which reference is now additionally made, may be used. In the circuit  10 ′″, the gate of the fourth transistor M 7 ,  52 , is connected to a node V Z ,  59 , between fifth and sixth nMOS transistors M 8 ,  54 , and M 9 ,  56 , connected between the supply voltage  48  and ground. Fourth, fifth, and sixth transistors  52 ,  54  and  56  together form a booster circuit for the circuit embodiment  10 ′″.  
         [0038]     The gate of the fifth transistor  54  is connected to the gate of the first transistor  38  of the second amplifier stage  16 , and the gate of the sixth transistor  56  is connected to the gate of the third transistor  50 . The drain of the fifth transistor  54  is connected to the supply voltage  48 , and the sixth transistor  56  is connected between the source of the fifth transistor  54  and ground. In the embodiment shown, transistors  54  and  56  may be nMOS devices, as shown; however, as above, it will be appreciated by those skilled in the art, other types and conductivities of devices may be used, depending upon the particular construction of the circuit  10 ′″.  
         [0039]     In the circuit  10 ′″, the fifth transistor  54  acts as a source follower, which is biased into conduction by the sixth transistor  56 . The insertion of a source follower provides a much larger current to charge the gate capacitance of the fourth transistor  52 , without greatly increasing the capacitance seen at node  36 . What capacitance is seen at node  36  can be minimized by making the fifth transistor  54  relatively wide and narrow, thus maximizing its transconductance for a given gate capacitance. This is allowable since the fifth transistor  54  does not need to accurately match any other transistor in the circuit.  
         [0040]     Circuits  10 ′,  10 ″ and  10 ′″ represent a progressive development of a single concept. All three circuits contain a nonlinear resistive element ( 50 ) that allows a rapid increase in the control voltage (at node  36 ) when the circuit is driven from equilibrium. All three circuits achieve a faster rate of slew on the inter-stage node (node  36 ) through use of the nonlinear resistive element, and all three achieve higher second-stage sink currents, although they differ in their means towards this end. Circuit  10 ′ relies merely upon a high voltage at node  36  fully enhancing transistor  38 . Circuit  10 ″ supplements transistor  38  with a booster circuit that includes a transistor  52  which conducts only after the nonlinear resistive element has transitioned from its low-resistance region to its high-resistance region. Circuit  10 ′″ uses a booster circuit that includes a source follower stage comprising transistors  54  and  56  to enable a much larger output sink device (transistor  52 ) without excessive increase of the capacitance on node  36 .  
         [0041]     It should be noted that although the circuits of  FIGS. 2, 3 , and  4  are shown in the context of the transconductance and load circuits  14  and  12  of  FIG. 1 , the transconductance and load circuits shown are examples only, and that various other circuits and circuit arrangements may be used in place thereof within the scope of the invention. Moreover, other permutations may be used; as suggested above, for example, the circuits may be easily implemented entirely in bipolar devices or entirely in MOS devices. Another easily implemented permutation may be the inversion of the power supply, wherein a negative power supply may be used referenced to ground or to a positive potential, with appropriate polarity changes of the devices of the circuit.  
         [0042]     Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.