Abstract:
The present invention relates to an apparatus for transmitting and receiving Manchester coded digital data for IEEE 802.3 Ethernet/Cheapernet type local area network. The apparatus mainly comprises, an isolation transformer, a signal converter with one end connected to one side of the isolation transformer, a receiver with its input connected to the other end of the signal converter, a capacitor located in the receiver and a transmitter with its output connected to the other side of the isolation transformer whereby the isolation transformer and the capacitor may isolate the external terminals from the main circuit. Moreover, the receiver and the transmitter can be integrally formed with a controller and thus to reduce the cost.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an apparatus for transmitting and receiving digital data, and more particularly to an apparatus for transmitting and receiving Manchester coded digital data for IEEE 802.3 Ethernet/Cheapernet type local area network. 
     As shown in FIG. 1, conventional transmitting and receiving apparatus in general utilize an isolated power supply 81 and a pulse transformer 82 to isolate both CS and CC terminals from the main circuit. However, the isolated power supply 81 and the pulse transformer 82 are quite bulky and expensive. Also, the total power consumption caused by the isolated power supply 81 is very significant. Moreover, in conventional apparatus, as shown in FIG. 1, a receiver 83 and a transmitter 84 are separated from a controller 85 by the isolated power supply 81 and the pulse transformer 82 such that both the receiver 83 and the transmitter 84 cannot be integrally formed with the controller 85 to produce a single chip. Therefore, the cost thus incurred cannot be reduced. 
     It is, therefore, the object of the present invention to obviate and mitigate the aforesaid drawbacks. 
     SUMMARY OF THE INVENTION 
     It is the object of the present invention to provide an apparatus for transmitting and receiving digital data which comprises an isolation transformer, a signal converter with one end connected to one side of the isolation transformer, a receiver with its input connected to the other end of the signal converter, a capacitor located in the receiver and a transmitter with its output connected to the other side of the isolation transformer whereby the isolation transformer and the capacitor may isolate the external terminals from the main circuit and the receiver together with the transmitter can be integrally formed with a controller to produce a single chip and thus to reduce the cost. 
     It is another object of the present invention to provide an apparatus for transmitting and receiving digital data which substitutes an isolation transformer and a capacitor for the commonly used isolated power supply and pulse transformer which are quite bulky and expensive, so as to lower the production cost. 
     It is a further object of the present invention to provide an apparatus for transmitting and receiving digital data which can reduce the power consumption due to the omission of the commonly used isolated power supply. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram showing a prior art apparatus; 
     FIG. 2-1 and 2-2 are respectively the simplified overall block diagram and detailed overall block diagram illustrating a preferred embodiment of the present invention; 
     FIG. 3-1 and 3-2 are respectively the simplified block diagram and the detailed circuit diagram of a receiver in accordance with the present invention; 
     FIG. 4 is a schematic block diagram showing a first embodiment of a decision block in accordance with the present invention; 
     FIG. 5 is a schematic block diagram showing an alternative embodiment of the decision block as shown in FIG. 4; 
     FIG. 6 is a schematic circuit diagram showing a first embodiment of a transmitter in accordance with the present invention; 
     FIGS. 7 and 7A are schematic circuit diagrams showing a second embodiment of the transmitter as shown in FIG. 6; 
     FIG. 8 is a schematic circuit diagram showing an alternative embodiment of an isolation block as shown in FIG. 3-1; 
     FIG. 9 is a block diagram illustrating an alternative embodiment of a timing circuit as shown in FIG. 3-1; 
     FIG. 10 is a circuit diagram showing an alternative embodiment of a fixed threshold voltage generator as shown in FIG. 3-1; 
     FIG. 11 is a block diagram showing an alternative embodiment of the receiver as shown in FIG. 3-1; 
     FIG. 12 is a schematic circuit diagram showing a third embodiment of the transmitter as shown in FIG. 6; 
     FIG. 13 is a simplified block diagram showing a further embodiment of the receiver as shown in FIG. 3-1; and 
     FIG. 14 is a circuit diagram showing a low pass filter which may be used with the receiver as shown in FIG. 13. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIGS. 2-1 and 2-2, a preferred embodiment of the present invention mainly comprises an isolation transformer 31, a transmitter 32, a receiver 33 and a signal converter 34 wherein the signal converter 34 is connected at one end to a second coil L2 of the isolation transformer 31 and an input of the receiver 33 is connected to the other end of the signal converter 34 while two outputs thereof are respectively connected to terminals DATA and COLLISION both of which are fed to a controller 35. Furthermore, an output of the transmitter 32 is connected to a first coil L1 of the isolation transformer 31 and an input thereof is connected to a terminal TX which serves as an output of the controller 35. The other end of the second coil L2 is connected to a terminal cs. The input of the receiver 33 also is connected to a terminal cc. As shown in FIG. 2-2, in a preferred embodiment, the signal converter 34 may be a diode 2 with its anode connected to the input of the receiver 33 and its cathode connected to said one end of the second coil L2. 
     As shown in FIG. 3-1, the receiver 33 comprises an isolation block 333 which, for example, can be a capacitor. A second output O/P2 of said isolation block 333 is fed into a fixed threshold voltage generator 46. A first and a second outputs O/P1 and O/P2 of the fixed threshold voltage generator 46 are respectively fed into a first and a second inputs I/P1 and I/P2 of a first dynamic threshold voltage generator 47 and a third output O/P3 thereof is fed into a second input I/P2 of a second dynamic threshold voltage generator 48. A first output O/P1 of the isolation block 333 is connected both to a first input I/P1 of a first comparator 42 and to a first input I/P1 of a second comparator 43. The output of the first dynamic threshold voltage generator 47 is fed into a second input I/P2 of the first comparator 42 and the output of the second dynamic threshold voltage generator 48 is fed into a second input I/P2 of the second comparator 43. The output of the first comparator 42 is connected both to a terminal DI of a decision block 49 and to the input of a timing circuit 73 and the output of the second comparator 43 is connected to a terminal CI of the decision block 49. The output of the timing circuit 73 is fed both to a third input I/P3 of the first dynamic threshold voltage generator 47 and to a first input I/P1 of the second dynamic threshold voltage generator 48. The decision block 49 has a DATA output and a COLLISION output. 
     As shown in FIG. 3-2, the fixed threshold voltage generator 46 comprises a first resistor 51 having one end connected to a positive power supply (such as 5 V) and the other end connected to the connection node of a second resistor 52 and a third resistor 53. The other end of the second resistor 52 is connected to the second output O/P2 of the isolation block 333. The third resistor 53 is connected in series with a fourth resistor 54 and a fifth resistor 55. Referring to FIGS. 3-1 and 3-2, the first output O/P1 of the fixed threshold voltage generator 46 is the connection node of the first and second resistors 51 and 52, the second output O/P2 thereof is the connection node of the third and fourth resistors 53 and 54, and the third output O/P3 thereof is the connection node of the fourth and fifth resistors 54 and 55. 
     As shown in FIG. 3-2, the first dynamic threshold voltage generator 47 comprises a first switch S1 having one end connected to the first output O/P1 of the fixed threshold voltage generator 46, and the other end connected to a sixth resistor 61. A second switch S2 has one end connected to the second output O/P2 of the fixed threshold voltage generator 46 and the other end connected to said one end of said sixth resistor 61. The control pins of said switches S1 and S2 are connected to the output of the timing circuit 73 such that the output signal coming from the output of the timing circuit 73 may turn on the first switch S1 and disable the second switch S2, or vice versa. A first capacitor 63 is connected between the other end of said sixth resistor 61 and the ground. The connection node of the sixth resistor 61 and the first capacitor 63 is connected to the second input I/P2 of the first comparator 42. 
     As shown in FIG. 3-2, the second dynamic threshold voltage generator 48 comprises a third switch S3 which is connected between the second input I/P2 of the second comparator 43 and the ground. A second capacitor 64 is connected in parallel with the third switch 53. A seventh resistor 62 is connected between the second input I/P2 of the second comparator 43 and one end of a fourth switch S4. The other end of the fourth switch S4 is connected to the third output O/P3 of the fixed threshold voltage generator 46. The signal coming from the output of the timing circuit 73 is arranged to turn on the third switch S3 and turn off the fourth switch S4, or vice versa. Also, it is noted that the timing circuit 73 can be a one-shot circuit as shown in FIG. 3-2. 
     As shown in FIG. 4, the decision block 49 mainly comprises a first counter 491 and a second counter 492. The first counter 491 has an input ck coming from the terminal DI and an output Q to the terminal DATA while the second counter 492 has an input ck from the terminal CI and an output Q to the terminal COLLISION. A first one-shot means 493 is connected at its input to the input ck of the first counter 491 and at its output to a reset terminal of the first counter 491. Similarly, a second one-shot means 494 is connected at its input to the input ck of the second counter 492 and at its output to a reset terminal of the second counter 492. The DATA inputs of both counters 491 and 492 are tied to a positive power supply (such as 5 V). 
     An alternative embodiment of the decision block 49 is illustrated in FIG. 5. The differences between FIG. 4 and FIG. 5 reside in that a pulse width detector 495 is connected between the input ck of the first counter 491 and a first input I/P1 of a OR gate 496. The output of the second counter 492 is connected to a second input of the OR gate 496. The output of the OR gate 496 is connected to the terminal COLLISION. 
     Referring to FIGS. 2-2 and 6, the transmitter 32 comprises M sets of transistors wherein each set consists of N transistors tr1 to trn. All of the drains of N transistors tr1 to trn are connected to one end of the first coil L1 of the isolation transformer 31. The other end of the first coil L1 is connected to a power supply, such as 5 V as shown in FIG. 2-2. All of the sources of N transistors tr1 to trn are connected to ground. There are M chains of delay elements wherein each chain consists of (N-1) delay elements d1 to dn-1 which are connected in series with each other and cooperate with each set of N transistors tr1 to trn. That is, the input of the first delay element d1 of the first chain comes from the terminal TX and is connected to the gate of the first transistor tr1 of the first set and the outputs of the delay elements d1 to dn-1 of the first chain are sequentially connected to the gates of the transistors tr2 to trn of the first set. Such procedures are repeated until the Mth set of transistors have combined with the Mth chain of delay elements. Also, there are (M-1) delay components d1 to dm-1 which are connected in series to each other such that the input of the first delay component d1 comes from the terminal TX and is connected to the input of the first delay element d1 of the first chain. The outputs of the delay components d1 to dm-1 are sequentially connected to the first inputs of the first delay elments d1 of the second to Mth chains. 
     As shown in FIG. 7, regarding the first set of transistors tr1 to trn and the first chain of delay elements d1 to dn-1, a switch S11 is connected between the gate of the first transistor tr1 and the input of the first delay element d1 while each of the (N-1) switches S12 to S1n is sequentially connected between the gate of each of transistors tr2 to trn and the output of each delay elements do to dn-1. Such procedures will be repeated for the remaining (M-1) sets of transistors and the remaining (M-1) chains of delay elements. Furthermore, as shown in FIG. 7A a Flop-Flop chain consisting of (N-1) Flip-Flops f1 to fn-1 are connected in series with each other to form a shift register. The input of the first Flop-Flop f1 is connected both to terminal TX and to the control pins of the first switches s11 to M1 for M sets of switches. The output of the first Flop-Flop f1 is simultaneously connected to the control pins of the second switches S12 to SM2 for M sets of switches and similar procedures are applied to the remaining Flop-Flops f2 to fn-1 and the corresponding switches S12 to SMN. 
     As shown in FIG. 8, the isolation block 333 connected between the signal converter 34 and the terminal cc comprises a transformer 333&#39; having a third coil L3 and a fourth coil L4 wherein the third coil L3 is connected between the terminal cc and the signal converter 34, and the fourth coil L4 is connected between the input of the fixed threshold voltage generator 46 and the first inputs of both the first and second comparators 42 and 43. An impedance Z is connected between the terminal Cs, and the connection node of the third coil L3 and signal converter 34. 
     As shown in FIG. 9, the timing circuit 73 comprises a Flop-Flop f having the data input connected to a power supply Vcc, the clock input connected to the terminal DI of the decision block 49, and the Q output thereof connected both to the third input of the first dynamic threshold voltage generator 47 and to the first input of the second dynamic threshold voltage generator 48. Referring to FIGS. 3-2 and 10, these resistors R51-R55 as shown in FIG. 3-2 may be replaced by MOS transistors of different sizes M1 to M5 with their gates respectively connected to DC voltages Vg1 to Vg5. 
     Referring to FIGS. 3-1 and 11, the first dynamic threshold voltage generator 47 as shown in FIG. 3-1 can be omitted and alternatively the second input of the first comparator 42 is connected to the second output of the fixed threshold voltage generator 46. 
     Referring to FIG. 2-1, the signal converter 34 can be replaced by a short circuit to be applicable to the non-IEEE 802.3 environment. 
     Referring to FIG. 12, the transmitter 32 further comprises N tri-state output buffers b1 to bn wherein the output of the first buffer b1 is connected to one end of the first coil L1 of said isolation transformer 31 through a first resistor r1 and the other end of the first coil L1 is connected to a power supply Vcc. The output of the second buffer b2 is connected to the output of the first buffer b1 through a second resistor r2. Similar procedures will be continued until the output of the nth buffer bn is connected to the output of the (n-1) th buffer bn-1 through a nth resistor rn. All of the inputs of buffers b1 to bn are commonly connected to the terminal TX while all of the control pins cp of said buffers b1 to bn are respectively connected to the inputs of a strength control block 321. The strength control block 321 has means to monitor the waveform strength across the terminals cc and cs and accordingly adjust the number of active output buffers so as to maintain a constant waveform strength across said terminals cc and cs. 
     Referring to FIGS. 3-1, 13 and 14, a low pass filter block 421 may be inserted between the first output O/P1 of the isolation block 333 and the first input I/P1 of the first comparator 42. The low pass filter block 421 comprises n resistors r1 to rn which are connected in series with each other. There are n capacitors c1 to cn each of which is connected between the ground and the output of each of the corresponding resistors r1 to rn.