Abstract:
The invention includes a semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) alternating first and second layers over the semiconductor wafer substrate, the alternating layers comprising at least one first layer and at least one second layer, the first layer comprising a first material and the second layer comprising a second material, the second material comprising atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium and mixtures thereof.

Description:
RELATED PATENT DATA 
     This patent resulted from a divisional application of U.S. patent application Ser. No. 09/050,218, which was filed on Mar. 27, 1998. 
    
    
     TECHNICAL FIELD 
     The invention pertains to semiconductor processing etch methods, and to semiconductor assemblies comprising indicator atoms. 
     BACKGROUND OF THE INVENTION 
     Semiconductor wafer fabrication processes frequently involve etching to remove a material. For example, semiconductor fabrication processes can include etching through an insulative material to form a contact opening to an electrical node underlying the insulative material. Semiconductive wafer fabrication processes can also include, for example, etching through conductive materials, and/or etching through semiconductive materials. 
     An example prior art etch process is described with reference to FIGS. 1-4. Referring to FIG. 1, a semiconductive wafer fragment  10  comprises a substrate  12  and three electrical components,  14 ,  16  and  18 , overlying substrate  12 . Component  14  can comprise, for example, a substrate diffusion region, and components  16  and  18  can comprise, for example, conductive lines. Substrate  12  can comprise, for example, monocrystalline silicon lightly doped with a background p-type dopant. To aid in interpretation of the claims that follow, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. 
     An electrically insulative material  20  is provided over electrical components  14 ,  16 , and  18 . Insulative material  20  can comprise, for example, borophosphosilicate glass (BPSG). 
     Etch stop caps  22  and  24  are provided over conductive components  16  and  18 , respectively. Etch stops caps  22  and  24  comprise a material which is selectively etchable relative to insulative material  20 . If insulative material  20  comprises BPSG, the etch stop material can comprise, for example, silicon nitride. 
     A patterned photoresist  26  is provided over insulative material  20  and defines a plurality of locations  28  wherein openings are to be etched through insulative material  20 . The openings are intended to expose conductive component  14 , and etch stop caps  22  and  24 . The openings are not intended to extend through caps  22  and  24 . 
     Referring to FIG. 2, an etch is conducted to remove material  20  from locations  28 . If material  20  comprises BPSG, such etch can comprise, for example, a plasma etch utilizing CF 4 /CHF 3 . The etch is intended to be selective for material  20  relative to photoresist  26 , and relative to etch stop caps  22  and  24 . However, even a highly selective etch will remove some of the material of caps  22  and  24 , and some of photoresist  26 , during removal of material  20 . 
     Etch depth is typically estimated from the duration of an etch. Such estimation leaves uncertainty as to when exactly the etch reaches component  14 . Accordingly, the duration of the etch is generally allowed to be somewhat longer than that estimated to be necessary for reaching component  14 , to ensure that component  14  is in fact actually reached. However, detrimental effects can occur if the etch duration is too long. 
     Referring to FIG. 3, wafer fragment  10  is illustrated after too long of an etch duration. Such etch duration has caused an overetch into component  14 , and has undesirably removed photoresist layer  26  (FIG.  2 ). After removal of photoresist layer  26 , portions of layer  20  that were intended to be protected by photoresist layer  26  are undesirably subjected to etching. This results in an undesired reduction in thickness of such portions of layer  20 . Also, the too long duration of the etch has undesirably resulted in etching through layers  22  and  24  to expose components  16  and  18 . 
     It would be desirable to avoid the detrimental effects illustrated in FIG.  3 . Accordingly, it would be desirable to develop new methods for determining etch rate in situ, and for ascertaining when an etch has reached a particular depth within a material. 
     FIG. 4 illustrates a semiconductive wafer  30  which can comprise wafer fragment  10 . Wafer  30  has a center region  32  and an edge region  34 . Typically, an etch process will comprise etching within both of regions  32  and  34 , as well as etching within portions of wafer  30  between regions  32  and  34 . A difficulty occurs in maintaining a uniform etch rate in edge region  34  relative to center region  32 . The uniformity of the etch rate in region  32  relative to that in region  34  is referred to as “center-to-edge uniformity”. 
     Presently, the center-to-edge uniformity of an etch process is estimated prior to the etching process, and then determined from measurements taken after the etching process. Accordingly, there is uncertainty regarding the center-to-edge uniformity during the etch process. To compensate for the uncertainty regarding the center-to-edge uniformity, etch processes are typically conducted for durations longer than what is necessary to reach a desired level within an etched material. Such long etch durations can cause the detrimental effects shown in FIG.  3 . Accordingly, it would be desirable to develop methods for reducing uncertainties regarding center-to-edge uniformity during etch processes. Specifically, it would be desirable to develop methods for ascertaining center-to-edge uniformity during etch processes. 
     SUMMARY OF THE INVENTION 
     In one aspect, the invention encompasses a method of etching. A material is formed over a substrate. The material comprises a lower portion near the substrate and an upper portion above the lower portion. A quantity of detectable atoms is provided within the material. The detectable atoms are provided at a different concentration in the lower portion than in the upper portion. The material is etched and an etching debris is formed. The detectable atoms are detected in the debris. 
     In another aspect, the invention encompasses a method of monitoring center-to-edge uniformity of an etch occurring on a semiconductor wafer assembly. A semiconductor wafer substrate having a center and an edge is provided. A material comprising detectable atoms is formed over the substrate. The material is etched and etching debris is formed. The detectable atoms are detected in the debris. A degree of center-to-edge uniformity of the etching is determined from the detecting. 
     In yet another aspect, the invention comprises a semiconductor wafer assembly comprising a semiconductor wafer substrate and alternating first and second layers over the semiconductor wafer substrate. The alternating layers comprise at least one first layer and at least one second layer. The first layer comprises a first material and the second layer comprising a second material. The second material comprises atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium, and mixtures thereof. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Preferred embodiments of the invention are described below with reference to the following accompanying drawings. 
     FIG. 1 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment at a preliminary step of a prior art fabrication process. 
     FIG. 2 is a view of the FIG. 1 wafer fragment shown at a prior art processing step subsequent to that of FIG.  1 . 
     FIG. 3 is a view of the FIG. 1 wafer fragment shown at a prior art processing step subsequent to that of FIG.  2 . 
     FIG. 4 is a diagrammatic isometric view of a prior art semiconductive wafer. 
     FIG. 5 is a diagrammatic, fragmentary, cross-sectional view of a semiconductor wafer fragment at a preliminary processing step of a method of the present invention. 
     FIG. 6 is a view of the FIG. 5 wafer fragment shown at a processing step subsequent to that of FIG.  5 . 
     FIG. 7 is a diagrammatic sketch of a graph showing intensity of indicator atoms versus time for a process of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). 
     A semiconductor wafer fragment  50  formed according to a method of the present invention is illustrated in FIG.  5 . Wafer fragment  50  comprises a substrate  52  and electrical components  54 ,  56  and  58  formed over and within substrate  52 . Substrate  52  and components  54 ,  56 , and  58  can comprise identical constructions as those of substrate  12 , and components  14 ,  16  and  18  of prior art wafer fragment  10  (FIG.  1 ). 
     Components  56  and  58  are covered by etch stop caps  60  and  62 , which can comprise materials identical to those of caps  22  and  24  of prior art wafer fragment  10  (FIG.  1 ). 
     A stack  68  comprising alternating first and second layers  64  and  66 , respectively, is provided over components  54 ,  56  and  58 . Layers  64  and  66  can define elevationally separated locations within stack  68 . Stack  68  can alternatively be considered as comprising two or more portions, with each portion comprising either a single layer  64  or a single layer  66 , or with each portion comprising a plurality of layers  64  and  66 . 
     First layers  64  can comprise, for example, an insulative material such as BPSG. Second layers  66  comprise detectable atoms that are present to a different concentration than such detectable atoms are present in first layers  64 . In preferred embodiments, the concentration of such detectable atoms in first layer  64  is substantially non-existent (i.e., substantially nil, or not detectable), and the concentration of such atoms in second layers  66  is from about 1 part per million (ppm) to about 0.1% (measured on an atomic basis). The detectable atoms are referred to herein as “indicator atoms”, as they can be used to indicate when a second layer is etched. Preferably, the indicator atoms comprise atoms that are not generally present in semiconductor fabrication processes, such as, for example, atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium, and mixtures thereof. For purposes of interpreting this disclosure and the claims that follow, the term “lanthanides” refers to the fourteen elements following lanthanum in the periodic table, as well as to lanthanum itself. Also, the term “actinides” refers to the fourteen elements following actinium in the periodic table, as well as to actinium itself. 
     In addition to the indicator atoms, second layers  66  can comprise a material identical to that comprised by first layers  64 . Accordingly, if first layers  64  comprise BPSG, second layers  66  can comprise BPSG in combination with indicator atoms. Second layers  66  can comprise identical compositions relative to one another, or can comprise different compositions. For instance, each of layers  66  could comprise different indicator atoms. 
     In an exemplary embodiment, first layers  64  will consist essentially of BPSG and second layers  66  will consist essentially of BPSG and indicator atoms. In such exemplary embodiment, stack  68  is substantially homogenous in chemical composition but for the indicator atoms. Stack  68  is referred to as “substantially” homogenous to indicate minor variations in BPSG deposition can occur within stack  68  even when processing parameters appear identical due to inaccuracies of measurement of the processing parameters. 
     In an example process, second layers  66  comprise BPSG in combination with indicator atoms, and first layers  64  comprise BPSG. First layers  64  can be formed by, for example, chemical vapor deposition. Second layers  66  can also be formed by chemical vapor deposition. The indicator atoms can be provided within second layers  66  by ion implanting, gas phase doping, or by in situ doping of layers  66  with the atoms during the chemical vapor deposition. If the indicator atoms are provided in situ during a chemical vapor deposition process, they can be provided as, for example, bromates, such as, for example, yttrium bromate. If the indicator atoms are implanted into a second layer  66  after chemical vapor deposition, they can be implanted by, for example, sputtering indicator atom ions from a solid comprising the indicator atoms. 
     The second layers  66  will preferably be provided to thickness which is less than are equal to about 10% of the thicknesses of first layers  64 . Preferably, individual layers  66  will be provided to thicknesses of less than or equal to about 100 Angstroms. First layers  64  will preferably be provided to thicknesses of about 4000 Angstroms. 
     The first layers  64  and second layers  66  are alternately formed until a desired thickness stack  68  is formed over components  54 ,  56  and  58 . In the shown embodiment, second layers  66  are approximately equally spaced throughout stack  68 . However, it is to be understood that the invention encompasses alternative embodiments (not shown) wherein second layers  66  are placed at unequal spacings throughout stack  68 . 
     A patterned layer of photoresist  70  is provided over stack  68 . Patterned photoresist layer  70  defines regions  72  wherein openings will be formed to components  54 ,  56  and  58 . 
     Referring to FIG. 6, openings  74 ,  76  and  78  are etched through stack  68 . Preferably, second layers  66  primarily comprise an identical composition to that of first layers  64 , with the indicator atoms being present in second layers  66  to a low enough concentration that they do not substantially alter etching of second layers  66  relative to the etching of first layers  64 . In such preferred embodiment, and if layers  66  and  64  primarily comprise BPSG, an example etch of stack  68  is a conventional BPSG etch, such as, for example, a plasma etch utilizing CF 4 /CHF 3 . 
     During the etch of stack  68 , debris will be formed as etched particles are displaced from stack  68 . Such debris can be monitored by, for example, spectroscopic methods to determine when second layers  66  are being etched. More specifically, the debris can be monitored by, for example, ultraviolet-visible spectroscopy or mass-spectrometry to determine when indicator atoms are present in the debris. Such determination of when indicator atoms are present in the debris can be utilized to determine a rate of an etch process. Specifically, if the depth of indicator atoms is known, etch rate can be determined by dividing the indicator atom depth by the time taken to reach such depth. The time taken to reach an indicator atom depth can be defined as, for example, the time taken until appearance of an indicator atom signal, or the time taken until appearance and extinction of an indicator atom signal. 
     In the shown preferred embodiment, a lowermost portion of stack  68  is a second layer  66 . This enables accurate determination of when an etch process has reached the bottom of stack  68 . For instance, in the shown embodiment, an operator of an etch process will know that there are four layers of second material to be penetrated before reaching substrate  52 . Accordingly, when the operator sees indicator atoms in the etch debris for the fourth time, the operator will know that bottom layer  66  of stack  68  has been reached. The operator can then monitor a concentration of indicator atoms to accurately identify when bottom layer  66  is etched entirely through to expose substrate  52  within opening  74 . Such accurate identification of when substrate  52  is exposed can enable the operator to avoid the overetch of the prior art (FIG. 3) and to thus avoid etching through the caps  60  and  62  provided over components  56  and  58 . Also, by accurately identifying when an etch has reached substrate  52 , the operator can more likely stop the etch process before photoresist layer  70  is undesirably removed. 
     The shown preferred embodiment also has a second layer  66  provided as an uppermost layer of stack  68 . Such uppermost layer can be utilized to warn that photoresist layer  70  has been removed. Specifically, if an operator of an etch process detects a spike of indicator atoms beyond that which would occur from etching openings  74 ,  76  and  78 , the operator will be warned that photoresist layer  70  has been etched through to expose uppermost surface  66  of stack  68 . The warning potential of uppermost surface  66  can be enhanced by forming uppermost surface  66  to comprise indicator atoms different from those comprised by the other second layers  66 . 
     Referring to FIG. 7, a diagrammatic sketch of a graph of indicator atom intensity (“I”) versus time for the etch process of FIGS. 5 and 6 is illustrated. Intensity (“I”) corresponds to the intensity of indicator atoms within debris formed by the etch process. 
     Four peaks,  80 ,  82 ,  84  and  86 , occur as the etch proceeds downwardly through stack  68 . Peak  80  corresponds to indicator atoms released by the etching of the uppermost of second layers  66 , and peaks  82 ,  84  and  86  correspond to indicator atoms released as each of the remaining second layers  66  is etched. An area under each of peaks  80 ,  82 ,  84  and  86  is roughly proportional to the number of openings extending through a given second layer, and the size of such openings. 
     Peaks  84  and  86  are more spread than peaks  80  and  82  due to a loss of center-to-edge uniformity as the duration of the etching process increases. Thus, the indicator atoms are detected for a greater length of time at peaks  80  and  82  than at peaks  84  and  86 . The shape of peaks  80 ,  82 ,  84  and  86  can be compared with standard peak shapes to determine center-to-edge uniformity. The standard peak shapes utilized for comparison with peaks  80 ,  82 ,  84  and  86  can be obtained experimentally, through theoretical calculations, or through a combination of experiment and theoretical calculation. 
     By comparing actual peak shapes to standard peak shapes, an operator of a process of the present invention can estimate the degree of center-to-edge uniformity of an etch process while the etch process is in progress. This can assist the operator in accurately determining how much, if any, overetch should be utilized to compensate for a reduction in center-to-edge uniformity. A method of the present invention can thus assist in avoiding misestimation of center-to-edge uniformity, and in avoiding the prior art excessive overetching that occurred due to such misestimations. 
     In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.