Abstract:
A flat-band voltage reference includes two insulated-gate field-effect transistors, hereinafter IGFETs, which are substantially identical except for their flat-band voltage characteristics and which are biased to carry equal drain currents at equal drain voltages. The resulting difference in potential between the gate contacts of the IGFETs produces a voltage reference which is substantially independent of variances in operating points, supply potentials, and temperature.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     Typical solid-state voltage reference devices generally obtain a reference voltage from a predictable breakdown voltage or from a known forward biased current-voltage relationship of a junction device. Temperature dependence of one device is often compensated by combination with another device also having a temperature dependence. A constant-current source is usually required for the best precision. 
     The invention is a voltage reference comprising a pair of field-effect devices each substantially identical to the other except for its flat-band voltage. Each field-effect device is biased with a substantially identical drain current, thereby producing a reference voltage between their respective gate field plates corresponding to the difference in flat-band voltages of the two field-effect devices. The invention provides an improved voltage reference which is substantially independent of variances in operating points, supply potentials and temperature. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a graph showing typical electrical characteristics of two insulated-gate field-effect transistors differing only in their flat-band voltages and having a constant and identical source-to-drain voltage and a constant and identical source-to-substrate voltage applied to each. 
     FIG. 2 is a diagram of a voltage reference made in accordance with the invention. 
     FIG. 3 is a schematic cross-section of a double insulator IGFET. 
     FIG. 4 is a diagram of a voltage reference made in accordance with the invention including means for electrically injecting charge into the insulator of one of the IGFETs. 
     FIG. 5 is a table of combinations of metals used for the gates of two IGFETs and approximate expected reference voltages resulting therefrom. 
     FIG. 6 is a diagram illustrating the processing steps for fabricating a voltage reference monolithically in accordance with the invention. 
     FIG. 7 is a diagram of another voltage reference made in accordance with the invention. 
     FIG. 8 is a diagram showing a method for combining a plurality of voltage references made in accordance with the invention to achieve larger reference voltages. 
     FIG. 9 shows a preferred voltage reference wherein surface area required for integrated fabrication is minimized. 
     FIG. 10 is a diagram of a preferred embodiment utilizing field-effect capacitors in accordance with the invention. 
     FIG. 11 is a diagram of another preferred embodiment utilizing field-effect capacitors. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, typical electrical characteristics of two IGFETs differing only in their flat-band voltages are shown for a constant drain-to-source voltage V D  and a constant bulk-to-source voltage V B  applied to each. The parallel electrical characteristics A and B depicted in FIG. 1 differ by a substantially constant amount equal to the difference in flat-band voltages. 
     In the preferred embodiment a substrate contact of each IGFET is connected to its respective source contact, although this is not essential to the invention. P-channel IGFETs, for example, operated above turn-on out below pinch-off, are described by the following equation: ##EQU1## where I D  is the drain current, Z is the channel width, L is the channel length, μ p  is the effective mobility of holes in the channel, C o  is the oxide capacitance per unit area, V G  is the gate-to-substrate voltage, V FB  is the flat-band voltage, φ F  is the Fermi potential, ε s  is the semiconductor dielectric constant, q is the magnitude of the electronic charge and N D  is the donor density in the semiconductor. 
     An IGFET operated in the pinch-off condition is also described by Equation (1) wherein the value for V D  is constant and V D  is given by: ##EQU2## 
     For two IGFETs, identical except for their flat-band voltages and biases with equal I D  &#39;s in pinch-off or equal I D  &#39;s and V D  &#39;s below pinch-off, the quantity (V G  - V FB ) is identically equal. A reference voltage can therefor be developed which is: 
     
         V.sub.Ref = ΔV.sub.G = ΔV.sub.FB               Eq. (3) 
    
     where V Ref  is the reference voltage, ΔV G  is the difference in gate voltages and ΔV FB  is the difference in flat-band voltages. This reference voltage is developed whether or not the IGFETs are operated above or below pinch-off. It is also developed when the IGFETs are operated below turn-on so long as identical I D  &#39;s and V D  &#39;s are maintained. 
     Referring to FIG. 2, there is shown a first preferred embodiment made in accordance with the invention. A first n-channel IGFET 5 and a second n-channel IGFET 7 are substantially identical except for different flat-band voltages. A bias supply 1 is connected between source contact 13 and drain contact 17 of IGFET 5 and a bias supply 3 is connected between source contact 15 and drain contact 19 of the IGFET 7. Substrate contacts 21 and 23 of IGFET 5 and IGFET 7, respectively, are attached to potential V B . The potential of gate contact 35 of IGFET 5 and gate contact 37 of IGFET 7 are adjusted by gate biasing means not shown in FIG. 2. The gate biasing means not shown in FIG. 2, the supply source 1 and the supply source 3 are adjusted such that the drain-to-source voltage of IGFET 5 is substantially equal to the drain-to-source voltage of IGFET 7 and such that the drain current of IGFET 5 is substantially equal to the drain current of IGFET 7. A reference voltage, V Ref , is produced by the difference between the potentials of the gate contact 35 of IGFET 5 and the gate contact 37 of IGFET 7. 
     The flat-band voltage is expressed as: ##EQU3## where Φ MS  is the work-function difference between the material used for the gate field plate and the substrate material, Q IS  is the charge per unit area in the interface states, Q.sub. SS is the fixed charge per unit area located at the semiconductor-insulator interface and the integral accounts for charge distributed throughout the insulator. ρ(x) is the charge density in the insulator located at a distance x from the metal and x o  is the thickness of the insulator. Referring to Equation (4) a change in V FB  is obtained either by changing one of the charge components in the insulator (i.e., interface-state density with a resulting change in the interface-state charge, fixed-charge at the semiconductor-insulator interface or charge distributed throughout the insulator or the like or by changing the work-function difference Φ MS . 
     different densities of interface states are obtained by, for example, subjecting one IGFET to a post-metalization anneal and bias cycle (See, for example, B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, &#34;Characteristics of the Surface-State Charge [Q SS  ] of Thermally Oxidized Silicon,&#34; J. Electrochemical Society, Volume 114, pages 266-274, March 1967), or by utilizing a first substrate of a first crystallographic orientation for the first IGFET and a second substrate of a second crystallographic orientation for the second IGFET (See, for example, A. Goetzberger and S. M. Sze, &#34;Metal-Insulator-Semiconductor [MIS] Physics,&#34; Applied Solid State Science, Volume 1, Raymond Wolfe and C. J. Kriessman [Eds.], Academic Press, New York [1969]). These techniques also result in different fixed charge at the two semiconductor-insulator interfaces (See &#34;Characteristics of the Surface-State Charge [Q Ss  ] of Thermally Oxidized Silicon&#34; as cited above). 
     Different densities of charge distributed throughout the insulators are obtained by, for example, exposing one IGFET to energetic particles, as for example, electrons, protons, molecules or atoms, or electromagnetic radiation, as for example, light or gamma rays, so as to ionize traps in the oxide (See &#34;Metal-Insulator-Semiconductor [MIS] Physics&#34; as cited above). Another technique is to introduce ionized atoms or molecules into one gate insulator (See, for example, A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley and Sons, New York [1967]). Still another technique for obtaining different insulator charge is to electrically inject charge carriers into the insulator region as, for example, by applying a large voltage between one of the substrates and its gate field plate. Elevating the insulator temperature is often used to reduce the time necessary for sufficient charge injection. Another technique is to bias one gate field plate at sufficiently high bias so as to drift the ionic or trapped charge in that insulator from its initial distribution. Elevating the insulator temperature reduces the time required for sufficient redistribution. 
     FIG. 3 is a schematic cross-section of a multiple insulator IGFET which is, for example, fabricated using the well-known metal-nitride-oxide-silicon technology wherein a first insulator 72 which is, for example, silicon dioxide, and a second insulator 74 which is, for example, silicon nitride, are placed between the substrate 52 and the gate field plate 64. Insulator 72 is preferably less than 100 Angstroms in thickness and a voltage of several volts or more between the gate field plate 64 and the substrate 52 results in charge carriers tunneling through the first insulator 72 into the second insulator 74 wherein substantially all of the charge is trapped. 
     Referring to FIG. 4, IGFETs 95 and 97 are matched IGFETs which could, for example, have single or multiple insulators. Voltage source 9 is applied to gate field plate 39 by closing switch 11 for transferring charge thereby producing a different V FB  for IGFET 95 from that for IGFET 97. 
     Different Φ MS  &#39;s are obtained by employing different metals for the different gate field plates. Different Φ MS  &#39;s between the two IGFETs are also obtained by combining different semiconductor materials or a semiconductor material and a metal in place of different gate metals. 
     Referring to FIG. 5, there is shown a table of representative combinations of gate metals and a semiconductor and the approximate expected V Ref  &#39;s from experimental data on individual metal-vacuum surfaces. The V Ref  obtained will differ somewhat from these values due to differences associated with fabrication techniques. Two gate field plate materials should preferably be selected which exhibit a low difference in temperature coefficient and adhere well to SiO 2 . 
     At present the use of two different gate field plate materials is the preferred embodiment as a result of long term stability and equal mobility considerations. The preferred embodiment is fabricated using the well-known metal-oxide-semiconductor technology. The matching of the two IGFETs is enhanced by fabricating them in close proximity to each other on the same substrate. The interface states then have substantially the same occupancy and the mobilities are substantially the same in both IGFETs when operated with substantially the same drain current and the same drain voltage. Effects resulting from temperature dependencies of the mobilities, the Fermi potentials, and the semiconductor surface potentials will thereby be minimized. Effects resulting from variations in the supply potential are also minimized. 
     The processing steps for monolithic fabrication of the two IGFETs using two different metals for the two different gate field plates are shown in FIG. 6. 
     Referring to drawing A of FIG. 6, a substrate 102 which is, for example, n-type silicon, is first cleaned and polished. A field oxide 104 is grown, openings 105 in the field oxide 104 are made and p-type dopants are diffused into the substrate 102 to form source contacts 106 and 108 and drain contacts 110 and 112. Referring to drawing B of FIG. 6, the field oxide 104 is removed in the region between the source diffusion 106 and the drain diffusion 110 and in the region between the source diffusion 108 and the drain diffusion 112. Contact openings 118 are also etched at this time. Gate oxides 114 and 116 are than grown. Referring to drawing C of FIG. 6, contact openings 118 are re-opened as shown. Referring to drawing D of FIG. 6, a first metal is deposited over the wafer and removed everywhere except for a first gate field plate 120, the source and drain contacts 106, 108, 110, 112, and any necessary interconnecting metal and bonding pads. Referring to drawing E of FIG. 6, a second metal is then deposited over the wafer and removed everywhere except for a second gate field plate 122 and wherever the first metal remains. Modifications to the above processing steps are also possible. 
     One such modification is to fabricate the two IGFETs either on the same or different substrates using the same processing steps until after the contact openings have been re-opened. The IGFETs are separated and different gate field plate metals and interconnecting metals are deposited on each. 
     V Ref  is temperature dependent only to the extent of any mismatches in the IGFETs and to the extent of the difference in temperature coefficients of their respective resulting work-function differences. 
     Referring to FIG. 7, there is shown another preferred embodiment made in accordance with the invention. A first p-channel IGFET 2 and a second p-channel IGFET 4 are substantially identical except for different flat-band voltages. An amplifier 6 is coupled to drive the gate of IGFET 4. Amplifier 6 has an inverting input connected to the drain contact of IGFET 2 and a resistor 8 and a non-inverting input connected to the drain contact of IGFET 4 and a resistor 10. Amplifier 6 has a large input impedance as compared with the resistances of resistors 8 and 10. A supply voltage is coupled across terminal 12 and ground 14. The gate contact of IGFET 2, resistor 8 and resistor 10 are connected to ground 14. The drain currents and drain voltages of IGFET 2 and IGFET 4 are maintained substantially equal by selecting matching resistances 8 and 10 and the action of amplifier 6 driving the gate field plate of IGFET 4. A reference voltage is obtained across terminals 16 and 14. 
     Referring to FIG. 8, there is shown a combination comprising two of the voltage references depicted in FIG. 7. A plurality of reference may be similarly combined to provide larger reference voltages. 
     Referring to FIG. 9, matched IGFETs 18 and 20 are substituted for the matched resistors 8 and 10 in the embodiment depicted in FIG. 7. This substitution allows conservation of substrate area should large resistance values be required for the resistors R8 and R10. 
     Other V FB  dependent parameters, as for example, the AC (alternating current) conductance and transconductance, of the IGFETs can also be detected and used to adjust the bias conditions such that a reference voltage is obtained. 
     Referring to FIG. 10, a preferred embodiment made in accordance with the invention using field-effect capacitors is shown. 
     The gate field plate-to-substrate voltage for a field-effect capacitor is given by: ##EQU4## where V G  is the gate field plate-to-substrate voltage, Φ s  is the surface potential, Q s  is the charge per unit area in the semiconductor, C o  is the oxide capacitance per unit area and V FB  is the flat-band voltage. Appropriate gate field plate voltages are applied to each of two field-effect capacitors such that the same φ s  is obtained for each field-effect capacitor, thereby resulting in the same Q s  in each field-effect capacitor. Each field-effect capacitor is substantially identical to the other except for flat-band voltages. A reference voltage V Ref  is produced which is given by: 
     
         V.sub.Ref = V.sub.G1 - V.sub.G2 = V.sub.FB1 - v.sub.FB2    Equation (6) 
    
     where V G1  and V G2  are the gate field plate-to-substrate voltages for first and second field-effect capacitors and V FB1  and V FB2  are the respective flat-band voltages for the first and second field-effect capacitors. V G  is varied to obtain matching capacitance and therefor matching φ s . Flat-band voltages are varied as described hereinbefore with respect to field-effect transistors. 
     Referring to FIG. 10, a first field-effect capacitor 202 and a second field-effect capacitor 204 are substantially identical except for different flat-band voltages. An AC (alternating current) voltage source 206 is coupled by coupling capacitors 208 and 209 to gate field plates 210 and 212 of the field-effect capacitors 202 and 204. Substrate contacts 214 and 216 of the field-effect capacitors 202 and 204 are coupled to ground by resistors 218 and 219. Resistors 218 and 219 are of substantially identical resistance and are each respectively coupled to rectifiers and filters 220 and 222 as shown. Outputs 228 and 230 of the rectifiers and filters 220 and 222 are coupled to differential inputs of amplifier 224. The amplifier 224 has an output coupled to the gate field plate 210 of the field-effect capacitor 202. 
     The resistance of resistors 218 and 219 is selected to be less than the magnitude of the reactance of field-effect capacitor 202. Biasing means 226 adjusts the capacitance of field-effect capacitor 204 to a convenient value and biasing means 226 has an impedance of magnitude greater than the magnitude of the reactance of field-effect capacitor 204. The magnitude of reactances of coupling capacitors 208 and 209 are chosen to be less than the magnitude of reactances of field-effect capacitor 202 and 204 at the frequency of AC voltage source 206. 
     Alternating current voltages having values substantially proportional to the capacitances of field-effect capacitors 202 and 204 are developed at substrate contacts 214 and 216. These voltages are converted to direct current voltages by rectifiers and filters 220 and 222 to produce signals at outputs 228 and 230 which drive amplifier 224. Amplifier 224 drives the voltage at the gate field plate 210 of field-effect capacitor 202 until the capacitance of field-effect capacitor 202 is substantially equal to the capacitance of field-effect capacitor 204. The reference voltage V Ref  is developed between gate field plate 210 and gate field plate 212 and is substantially equal to the difference in flat-band voltages of field-effect capacitors 202 and 204. 
     Referring to FIG. 11, there is shown another preferred embodiment made in accordance with the invention. Substantially identical AC current sources 305 and 306 drive substantially identical currents into field-effect capacitors 302 and 304 which are substantially identical except for their flat-band voltages. Rectifying and filtering means 320 and 322 are connected to field-effect capacitors 302 and 304 respectively. 
     A DC voltage is produced at input terminals 328 and 330 of amplifier 324 which forces the output of amplifier 324 to bias field-effect capacitor 302 such that its capacitance is substantially identical to that of field-effect capacitor 304. A reference voltage V Ref  is produced between terminals 350 and 352 which is substantially equal to the difference in the flat-band voltages of field-effect capacitors 302 and 304. Bias source 326 is adjusted to obtain a convenient value of capacitance. 
     Differences in field-effect capacitor flat-band voltages are produced, for example, by techniques disclosed hereinbefore with respect to field-effect transistors. 
     Other V FB  dependent parameters, as for example tunneling currents in thin oxide devices, of field-effect capacitors can also be detected and used to adjust the bias conditions such that a reference voltage is obtained.