Abstract:
In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Description:
FIELD 
       [0001]    This disclosure relates to integrated circuit (IC) packaging. More particularly, this disclosure relates packaging with a reduced vertical profile and an exposed underside surface providing enhanced thermal performance. 
       BACKGROUND 
       [0002]    The electronics industry continues to rely upon advances in semiconductor technologies to realize higher-function devices in more compact areas. For many applications realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult. 
         [0003]    Many varieties of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor field-effect transistors (MOSFET), such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors. Such MOSFET devices include an insulating material between a conductive gate and silicon-like substrate; therefore, these devices are generally referred to as IGFETs (insulated-gate FET). 
         [0004]    Having manufactured a number of electronic devices on a wafer substrate, a particular challenge is to package these devices for their given purpose. As the complexity of portable systems increases, there is a commensurate need to reduce the size of the individual components which make up the system; the system often is laid out on a printed circuit substrate. One way to reduce the size of individual components is through techniques that reduce the size of packages which contain these devices. There is a need for packaging which reduces the amount of printed circuit substrate space consumed. Further, in reducing amount of consumed space, the power-handling capabilities of the package/device assembly must also be enhanced. 
       SUMMARY 
       [0005]    The present disclosure addresses the challenge of making a semiconductor power package with minimal R DSon  with enhanced thermal performance. This is obtained by having the backside of the die exposed in the package. The die backside has a solderable coating. In this way minimal thermal resistance is achieved between the die junction and the printed circuit board to which the packaged device is attached. The Low R DSon  is achieved using a clip bond process to attach leads in direct die contact. Optional multiple wire bonds may be added, as well, for signal pathways not involved with the low R DSon  requirement. 
         [0006]    In an example embodiment, there is a method for packaging an integrated circuit (IC). The method comprises mounting a plurality of active device die, into predetermined positions, onto a temporary carrier. Each said active device die has bond pads; each of said active device die has a solderable conductive surface on its underside; and each of said device has been subjected to back-grinding to a prescribed thickness. Into predetermined positions, onto a temporary carrier, the plurality of active device die are mounted. A solder paste is dispensed onto the bond pads on the plurality active device die. A lead frame is attached to the temporary carrier, the lead frame having an array of device positions which correspond to the predetermined positions of the plurality of active device die, wherein upper lead frame portions contact the solder paste present on the bond pads and lower lead frame portions contact the carrier tape. There is a reflowing of the solder so that a connection is made between the upper lead frame portions and the bond pads of the plurality of active device die. 
         [0007]    In another example embodiment, there is a method for packaging an integrated circuit (IC) device from a semiconductor wafer substrate, the wafer substrate having a top-side surface with a plurality active device die defined thereon, and an under-side surface. The method comprises back-grinding the under-side surface of the wafer substrate to a prescribed thickness; applying a solderable conductive surface to the under-side surface of the wafer substrate. The plurality of active device die are separated out from the semiconductor wafer substrate, each of the active device die having bond pads, the bond pads providing electrical connection to circuit elements in the active device die and the plurality of active device die are mounted into predetermined positions onto a temporary carrier. A solder paste is dispensed onto the bond pads on the plurality active device die. Individual lead frame portions are attached to the temporary carrier and bond pads, wherein upper individual lead frame portions contact the solder paste present on the bond pads and lower individual lead frame portions contact the carrier tape. A reflowing of the solder is performed so that a connection is made between the upper lead frame portions and the bond pads of the plurality of active device die. 
         [0008]    In yet another example embodiment, an integrated circuit (IC) device comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a solderable conductive surface. A first set of lead frame clips, having upper portions and lower portions, are solder-anchored on the upper portions, to a first set of bond pads, and the lower portions are about co-planar with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The IC device is encapsulated in a molding compound leaving the solderable conductive surface and underside surfaces of the first and second sets of the lead frame portions exposed. 
         [0009]    The above summaries of the present invention are not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follow. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which: 
           [0011]      FIGS. 1A-1G  are side-views of device die assembled according to an embodiment of the present disclosure; 
           [0012]      FIGS. 2A-2G  are top-views of the corresponding  FIGS. 1A-1G ; and 
           [0013]      FIGS. 3A-3B  are side-views of a package singulated by sawing; 
           [0014]      FIGS. 4A-4B  are side-views of packaged devices singulated by punching; 
           [0015]      FIG. 5  is a flow diagram of an example process according to the disclosure; and 
           [0016]      FIGS. 6A-6J  depict side-views of device die assembled according to another embodiment of the present disclosure. 
       
    
    
       [0017]    While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0018]    The present disclosure has been found useful in reducing in a FET device, in the “On” state, the drain/source electrical resistance (i.e., R DSon ). It is desirable that the R DSon  be as low as possible so as to reduce the electrical power loss inside the package. These devices may be expected to dissipate about 100 mW to about 5 W, or more. The degree of grinding and the back side metallization affect the R DSon  of the finished device product. In an example process the wafers are ground down to about 200 μm. To further reduce the R DSon , in another example process, the back grind thickness may be reduced down to 50 μm, after this process the back side metallization is applied. This metallization is in the order of a few micro-meters, One or more metallization deposition techniques may be applied or even a combination of them (e.g., an initial sputter layer which is increased in thickness by a plating process). 
         [0019]    In this disclosure the die backside is coated on wafer level with a solderable back side metal (NiAu, Cu, NiAg, etc.) Any solderable finish can be used, as long as the solderabilty is not deteriorated by the processing conditions and allows storage for a sufficient period between package assembly and customer use. It is worth noting that before the solderable coating is applied to the underside surface of of the back-ground wafer, as a first layer, an adhesion layer of titanium (Ti), chromium (Cr), or other suitable material, is often applied. For example, a complete metal stack may include TiNiAg, CrNiAg, TiNiAu, CrNiAu, etc. Often the solderable coating is expressed in terms of the last two or three layers or surfaces. 
         [0020]    In another example process, a heavily doped poly-silicon may be used in addition to a metallization to enhance conductivity and reduce R DSon . However, the process would have to be compatible and not interfere with the operation of the finished device. After the metallization, the wafer is separated into individual dies; the dies are placed on a temporarily carrier (tape) in an array (e,g, a matrix) format with fixed pitch in X and Y direction. 
         [0021]    Next a solder paste is applied on the low-ohmic required bond pad contacts (e.g., by screen printing or dispensing). Next a pre-formed lead frame is fixed to the carrier. In an example process, the pre-formed lead frame will exert some force on the solder paste and device. However, there should be sufficient space between the pre-formed lead frame and solder paste so as to minimize the contact resistance between the lead frame and flowed solder. The preforming is such that the part of the lead frame which forms the lead is attached on the carrier and the upward bent part of the lead frame is contacting the solder paste. After reflow the contact between die and lead frame is made. Optional additional wire bonds can be made. Molding is then done covering the total lead frame. In an alternative embodiment, single devices are individually encapsulated so that leads remain free from molding compound. After the molding process the devices can be marked and singulated as individual products by sawing or by punch singulation. 
         [0022]    Refer to  FIGS. 1A-1G  and  FIGS. 2A-2G .  FIGS. 1A-1G  illustrate in a cross-section side view X-X′ of the corresponding  FIGS. 2A-2G  which are a top view perspective. A carrier tape  120  is mounted into a carrier ring apparatus  110 . At predetermined device die locations  165 , an array of device die  130  are bonded onto the carrier tape  120 . For example, as a two-sided adhesive carrier tape, REVALPHA® tape may be used. REVALPHA is the trademark of the brand of thermal release sheet material for electronic component processing manufactured by Nitto Denko Corporation, Osaka, Japan. At room temperature, the tape adheres securely. With application of heat the tape loses its adhesion. Depending upon a particular process the tape may be selected to release at 90° C., 120° C., 150° C. or 170° C. 
         [0023]    The undersides of device die  130  have been prepared with a solderable conductive coating  135 . In example processes, carrier ring frame sizes may be 50 mm×200 mm or 80 mm×300 mm. 
         [0024]    In an example embodiment, the carrier tape  120  actually also could be mounted on a flat plate supporting the total materials rather than a ring. This supporting plate or ring can be reused in the process so this is to be seen as tooling and not as consumable material. The number of fabricated devices can range from several hundred to even several thousand pieces. Package sizes may range from few millimeters to down to about 0.5 mm×1 mm. 
         [0025]    On selected device die pads  140 , with a screen printing process, a solder paste  145  is dispensed (in this example, device die pad  140   a ). A lead frame  150  has an array of lead frame clips  155  which correspond to the device die positions  175 . The lead frame  150  is mounted onto the carrier tape  120  so that a first lead frame portion  155   a  (of lead frame clip  155 ) at the device die position  175  contacts the bond pad  140   a , now prepared with a solder paste  145  (of the device die  130 ); the second lead frame portion  155   b  of at device die position  175  adheres to the carrier tape  120 . The lead frame device die position  155  has a first bend  165   a  and a second bend  165   b . A solder reflow process mechanically and electrically attaches the first portion (with the solder paste  145 ) of first portion of  155   a  the device die position  155  of lead frame  150  to the device die pad  140   a . The array of device positions  155  are solder-reflow attached for the entire lead frame  150 . An individual device view  200  of  FIG. 1D  shows, in more detail, the assembly. Note that a second lead frame portion at device position  155   b ′ is part of an additional lead frame device position  155 ′ (as shown by the dashed lines). 
         [0026]    Information on solder paste printing and reflow soldering may be found in the publication, “SMT Notes for CHIP-R and MLCC” of Walsin Technology Corporation, Tao Yuan, Taiwan, pp. 21. Additional information may be found in the publication, “Comprehensive User&#39;s Guide: MLP Micro Leadframe Package,” April 2002. Carsem, Inc. pp. 19. Also further information on surface mounting and solder reflow may be found in Application Note, AN10365 Rev. 6, 20 Jul. 2012, “Surface Mount Reflow Soldering,” of NXP Semiconductors, pp. 31. 
         [0027]    In another example embodiment, additional bond pads  140   b  on device die  130  may have wire bonds  160  connected to a second lead frame portion of the device die position  155   b ′ of the lead frame  150 ′. Refer to device view  250  of  FIG. 1E . 
         [0028]    After the lead frame  150  connections and wire bonds  160 , if done, have been defined for the array of device die positions, the device die  130  and lead frame  150  are encapsulated in a molding compound  170 . Encapsulation may be accomplished with a map molding process in which the entire lead frame/device die array is entirely encapsulated in molding compound or encapsulation may be of individual device die  130  with a mold  170 ′ consisting of separate device locations  5 . Refer to  FIGS. 1F-1G  and  FIGS. 2F-2G . 
         [0029]    Refer to  FIGS. 3A-3B  depict packaged devices which have been separated by wafer sawing with a blade  10 . Those devices encapsulated with a map molding process would be sawn apart at their predetermined package boundaries. In the instant disclosure, the sawing or cleaving apart of the device would be in the vicinity mid-way from the edge of the second lead frame portion  155   b  and the second bend  165   b.    
         [0030]    Refer to  FIG. 3B . The finished IC device  300  has a device die  330  in a molding compound  370 . One or more lead frame clips  365  through a solder/bond pad connections  340  electrically connect the device die  330  whose underside has solderable conductive material (back metal)  335  applied thereto. The lead frame clip  355  has an upper portion  355   a  and a lower first portion  355   b ; the lead frame clip  355  has an upper bend  365   a  and a lower bend  365   b . Device  330  has additional bond pads  340   b  to which wires  360  are bonded. The bond wires  360  are bonded to the additional bond pad  340   b  and to a lower second portion  355   b ′ of an additional set of lead frame clips (not illustrated) which had been cut during singulation. The undersides of the lower first portions  355   b  and second lower portions  355   b ′ and the underside side of the device die  330 , which has been coated with a solderable conductive material  335 , are co-planar with one another. The finished IC device  300  has its device die  330  underside  335  and the lower first portion  355   b  and the lower second portion  355   b ′ soldered to corresponding contact regions  320   a ,  320   b , and  320   c , on printed circuit board  310 . 
         [0031]      FIGS. 4A-4B  depict packaged devices which had been separated by punch singulation  5 . Punch singulation is appropriate for those devices encapsulated as individual device die during the molding process. After encapsulation, an apparatus having a plurality of cutting blades would cleave apart the packaged devices at predetermined package boundaries, as done with the saw cut of  FIG. 3A-3B , in the vicinity mid-way from the edge of the second lead frame portion  455   b  and the second bend  465   b . An example technique for punch singulation may be found in U.S. Patent Publication 2012/0184086 A1 (published Jul. 19, 2012) titled, “Punch Singulation System and Method,” of Hae Choon Yang et al, and is incorporated by reference in its entirety. 
         [0032]    As with the packaged device of  FIG. 3B , the finished IC device  400  has a device die  430  in a molding compound  470  (See  FIG. 4B ). One or more lead frame clips  455  through a solder/bond pad connections  440  electrically connect the device die  430  whose underside has solderable conductive material  435  applied thereto. The lead frame clip  455  has an upper portion  455   a  and a lower first portion  455   b ; the lead frame clip  455  has an upper bend  465   a  and a lower bend  465   b . Device  430  has additional bond pads  440   b  to which wires  460  are bonded. The bond wires  460  are bonded to a lower second portion  455   b ′ of a second set of lead frame clips (not illustrated) which had been cut during singulation. The undersides of the lower first portions  455   b  and second lower portions  455   b ′ and the underside side of the device die  430 , which has been coated with a solderable conductive material  435 , are co-planar with one another. The finished IC device  400  has its device die  430  underside and the lower first portion  455   b  and the lower second portion  455   b ′ soldered to corresponding contact regions  420   a ,  420   b , and  420   c , on printed circuit board  410 . 
         [0033]    In an example embodiment according to the present disclosure, an assembly process is shown. Refer. To  FIG. 5 . In a metal ring apparatus or other suitable carrier, carrier tape is mounted and stretched  510 . Device die are bonded to the tape  515 . These device die (at the wafer level) have had a solderable surface applied to the underside. At predetermined pad landings on the device die, a solder paste is applied  520 . The predetermined bond pads upon which solder paste is applied through a screen process. The lead frame is mounted onto the tape and is positioned so that it is contacting those bond pads upon which solder paste has been applied  525 . A reflow process melts the solder and at the bond pads, mechanically and electrically attaches the lead frame with the device die  530 . If required, an additional cleaning may be performed. Refer back to  FIG. 1E . An additional feature of wire bonding additional bond pads may be implemented  535 . In an example package, the wire bond  160  may be attached from additional bond pads  140   b  to the surface of an adjacent second lead frame portion  155   b ′. Having completed the lead frame attach and wire bonding, the device die are encapsulated in a molding compound  540 . In an example process, some molding compounds, may include, but not necessarily limited to, those manufactured by Sumitomo (e.g.: x84194) and Hitachi (e.g.: cel 400 ZHF 40 53 C), etc. After molding is completed, the carrier tape is removed  545 , individual devices may be laser marked for identification purposes. In another example process, removal of the tape occur later in the process; the same tape might even be used for the saw singulation process. Depending upon the molding process, the devices may be singulated either by sawing with a diamond saw of a suitable kerf or cleaved apart via a punch apparatus  550 . Burrs or rough edges on the individual encapsulated devices may be removed by suitable processes. These finished devices are electrically tested (as required), packed and shipped to the end user  555 . 
         [0034]    In another example embodiment, there may be a concern about material consumption in the discarding of scrap pieces of lead frame material after the device die are assembled. After placement of the device die  130  onto the carrier tape  120 , the components of the lead frame  150  may be individual lead frame portions  155  placed on the carrier tape  120  and the upper portion  155   a  of the lead frame portion  150  contacts pre-determined bond pad landings  140  on device die  130 , so as to establish an electrical connection. An example of this technique of using individual lead frame portions may be found in US Patent Application Publication (US2011/0198738 A1 published Aug. 18, 2011) of Peter Wilhelmus Maria Van De Water et al, titled, “Method for Manufacturing a Microelectronic Package Comprising at Least One Microelectronic Device,” and is incorporated by reference in its entirety. 
         [0035]    In another example embodiment  FIGS. 6A-6J  depict the assembly  600  of device die, as has been shown in reference to  FIGS. 1A-1G . However, a temporary support plate  610  has been included to provide a precision surface upon which carrier tape  620  is applied. Device die  630 , having a solderable underside coating  635 , are laid on the support plate-backed carrier tape  620  based on carrier capacity, die size, number of pins to bond or attach to clips, etc. Solder paste is applied to die pads  640 . The lead frame clips  650  are positioned over the die bond pads  640   a  and attached to the carrier tape  620 . With solder reflow, the lead frame portions are electrically connected and mechanically anchored to the device die bond pads  640   a . As required, for other device die bond pads  640   b , bond wires  660  are attached. The assembly  600  undergoes encapsulation  670 . 
         [0036]    As with the afore-mentioned embodiment, the assembly may undergo map molding ( FIGS. 6F-6G ) and be sawed apart with a blade  90  between devices and their separate the lead frame portions, resulting in individual devices  680 . 
         [0037]    In an alternative process, the devices may be individually encapsulated ( FIG. 6H-6J ). The carrier plate  610  is removed. After removal of the carrier plate  610 , the strip is fed into a punch/singulation tool where punch tool  95  and anvil  615 , with slots  97 , cleave apart the device die. As shown in  FIG. 6I , individual devices  685  have been separated by the punching/cleaving process. 
         [0038]    Depending upon the production process, there is a tradeoff in terms of saving materials v. throughput. Individual clip placement provides for material savings and accuracy (i.e., each clip targets a particular die, as it is placed thereon). Using a grid of clips saves time and increases throughput, however the placement accuracy is of tighter tolerances. In an example process, a combination of both techniques provides a reasonable compromise between material consumption and throughput, and placement accuracy. Lead frame strips of clips about 50 mm in width may be placed upon the arrayed device die. 
         [0039]    Various exemplary embodiments are described in reference to specific illustrative examples. The illustrative examples are selected to assist a person of ordinary skill in the art to form a clear understanding of, and to practice the various embodiments. However, the scope of systems, structures and devices that may be constructed to have one or more of the embodiments, and the scope of methods that may be implemented according to one or more of the embodiments, are in no way confined to the specific illustrative examples that have been presented. On the contrary, as will be readily recognized by persons of ordinary skill in the relevant arts based on this description, many other configurations, arrangements, and methods according to the various embodiments may be implemented. 
         [0040]    To the extent positional designations such as top, bottom, upper, lower have been used in describing this disclosure, it will be appreciated that those designations are given with reference to the corresponding drawings, and that if the orientation of the device changes during manufacturing or operation, other positional relationships may apply instead. As described above, those positional relationships are described for clarity, not limitation. 
         [0041]    The present disclosure has been described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto, but rather, is set forth only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, for illustrative purposes, the size of various elements may be exaggerated and not drawn to a particular scale. It is intended that this disclosure encompasses inconsequential variations in the relevant tolerances and properties of components and modes of operation thereof. Imperfect practice of the invention is intended to be covered. 
         [0042]    Where the term “comprising” is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g. “a” “an” or “the”, this includes a plural of that noun unless something otherwise is specifically stated. Hence, the term “comprising” should not be interpreted as being restricted to the items listed thereafter; it does not exclude other elements or steps, and so the scope of the expression “a device comprising items A and B” should not be limited to devices consisting only of components A and B. This expression signifies that, with respect to the present disclosure, the only relevant components of the device are A and B. 
         [0043]    Numerous other embodiments of the disclosure will be apparent to persons skilled in the art without departing from the spirit and scope of the disclosure as defined in the appended claims.