Abstract:
An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present disclosure generally relates to advanced transistor structures for use in analog integrated circuits. 
         [0003]    Description of the Related Art 
         [0004]    Advanced integrated circuits typically feature strained channel devices, silicon-on-insulator (SOI) substrates, FinFET structures, or combinations thereof, in order to continue scaling transistor gate lengths below 20 nm. Such technologies allow the channel length of the transistor to be made smaller while minimizing detrimental consequences such as current leakage and other short channel effects. 
         [0005]    A FinFET is an electronic switching device that features a conduction channel in the form of a semiconducting fin that extends outward from the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance in the “on” state and less current leakage in the “off” state than is possible in a conventional planar device. 
         [0006]    Incorporating strain into the channel of a semiconductor device stretches the crystal lattice, thereby increasing charge carrier mobility in the channel so that the device becomes a more responsive switch. Introducing compressive strain into a PFET transistor tends to increase hole mobility in the channel, resulting in a faster switching response to changes in voltage applied to the transistor gate. Likewise, introducing a tensile strain into an NFET transistor tends to increase electron mobility in the channel, also resulting in a faster switching response. 
         [0007]    There are many ways to introduce strain into the channel region of a FinFET. Techniques for introducing strain typically entail incorporating into the device epitaxial layers of one or more materials having crystal lattice dimensions or geometries that differ slightly from those of the silicon substrate. The epitaxial layers can be made of doped silicon or silicon germanium (SiGe), for example. Such epitaxial layers can be incorporated into source and drain regions, or into the transistor gate that is used to modulate current flow in the channel, or into the channel itself, which is the fin. Alternatively, strain can be induced in the fin from below the device by using various types of SOI substrates. An SOI substrate features a buried insulator, typically a buried oxide layer (BOX) underneath the active area. SOI FinFET devices have been disclosed in patent applications assigned to the present assignee, for example, U.S. patent application Ser. No. 14/231,466, entitled “SOI FinFET Transistor with Strained Channel,” U.S. patent application Ser. No. 14/588,116, entitled “Silicon Germanium-on-insulator FinFET,” and U.S. patent application Ser. No. 14/588,221, entitled “Defect-Free Strain-Relaxed Buffer Layer,” all of which are hereby incorporated by reference in their entireties. 
         [0008]    Short channel transistors in which the source and drain regions are very close together permit high speed switching, but they are generally less reliable and offer less precise control than long channel devices. Generally, it is desirable to have both short channel and long channel devices available on the same chip, e.g., as discussed in U.S. Pat. No. 7,723,192 to Carter et al. While it is relatively straightforward to include both types of devices in a digital integrated circuit, state-of-the-art analog designs pose a particular challenge. In order to prevent electromagnetic interference among the transistors on an analog chip, it is desirable to maintain some distance between neighboring devices. This limits the ability of circuit designers to shrink analog designs with each new technology generation. Prevention of crosstalk is of particular concern in nanoscale technologies, for which typical short channel lengths are now expected to be as low as about 7 nm. 
       BRIEF SUMMARY 
       [0009]    An analog integrated circuit stacks short channel transistors on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and, in particular, the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. For example, one embodiment of a cell may contain two long channel devices and one short channel device, or two short channel devices co-linear with one long channel device. Another embodiment of a cell may contain two long channel and two short channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0010]    In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. 
           [0011]      FIG. 1  is a flow diagram outlining a basic sequence of steps in a method of fabricating an integrated circuit cell that integrates short channel and long channel devices for analog circuit applications. 
           [0012]      FIGS. 2A-2D  show a perspective view and three different cross-sectional views of the integrated circuit cell after forming trenches for the long channel fins. 
           [0013]      FIGS. 3A-3D  show and a perspective view and three different cross-sectional views of the integrated circuit cell following epitaxial growth of the long-channel fins and formation of an insulating layer covering the long channel fins. 
           [0014]      FIGS. 4A-4D  show a perspective view and three different cross-sectional views of the integrated circuit cell after forming a trench for the short channel fin and source and drain region trenches for the long channel devices. 
           [0015]      FIGS. 5A-5D  show a perspective view and three different cross-sectional views of the integrated circuit cell following epitaxial growth and in-situ doping of the long channel source and drain regions. 
           [0016]      FIGS. 6A-6D  show a perspective view and three different cross-sectional views of the integrated circuit cell following epitaxial growth of the short-channel fin. 
           [0017]      FIGS. 7A-7D  show a perspective view and three different cross-sectional views of the integrated circuit cell during formation of source and drain regions for the short channel device. 
           [0018]      FIGS. 8A-8D  show a perspective view and three different cross-sectional views of the integrated circuit cell after forming trenches for the gates. 
           [0019]      FIGS. 9A-9D  show a perspective view and three different cross-sectional views of the integrated circuit cell after formation of the gates. 
           [0020]      FIGS. 10A-10D  show several exemplary cell embodiments that include different configurations and combinations of stacked short channel and long channel devices. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure. 
         [0022]    Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.” 
         [0023]    Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure. 
         [0024]    Reference throughout the specification to integrated circuits is generally intended to include integrated circuit components built on semiconducting substrates, whether or not the components are coupled together into a circuit or able to be interconnected. Throughout the specification, the term “layer” is used in its broadest sense to include a thin film, a cap, or the like and one layer may be composed of multiple sub-layers. 
         [0025]    Reference throughout the specification to conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals, or similar materials include such processes as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. For example, in some circumstances, a description that references CVD may alternatively be done using PVD, or a description that specifies electroplating may alternatively be accomplished using electro-less plating. Furthermore, reference to conventional techniques of thin film formation may include growing a film in-situ. For example, in some embodiments, controlled growth of an oxide to a desired thickness can be achieved by exposing a silicon surface to oxygen gas or to moisture in a heated chamber. 
         [0026]    Reference throughout the specification to conventional photolithography techniques, known in the art of semiconductor fabrication for patterning various thin films, includes a spin-expose-develop process sequence typically followed by an etch process. Alternatively or additionally, photoresist can also be used to pattern a hard mask (e.g., a silicon nitride hard mask), which, in turn, can be used to pattern an underlying film. 
         [0027]    Reference throughout the specification to conventional etching techniques known in the art of semiconductor fabrication for selective removal of polysilicon, silicon nitride, silicon dioxide, metals, photoresist, polyimide, or similar materials includes such processes as wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical-mechanical planarization (CMP) and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. In some instances, two such techniques may be interchangeable. For example, stripping photoresist may entail immersing a sample in a wet chemical bath or, alternatively, spraying wet chemicals directly onto the sample. 
         [0028]    Specific embodiments are described herein with reference to short channel and long channel FinFETs that have been produced; however, the present disclosure and the reference to certain materials, dimensions, and the details and ordering of processing steps are exemplary and should not be limited to those shown. 
         [0029]    Turning now to the figures,  FIG. 1  shows steps in a method of fabricating stacked short and long channel FinFETs for high performance analog integrated circuits, according to one embodiment. Steps in the method  100  are further illustrated by  FIGS. 2A-8D , and described below. In each of the Figures, A is a perspective view of an integrated short and long channel cell at the present step during fabrication, showing, as an example, a single short channel and a pair of long channels, indicating cut lines for various cross-sectional views; B is a cross-sectional view along a cut line through an exemplary long channel; C is a cross-sectional view along a cut line across the pair of exemplary long channels; and D is a cross-sectional view along a cut line through the exemplary short channel. 
         [0030]    At  102 , long channel epitaxial fins of an integrated short and long channel cell  120  are formed on a silicon substrate  122 , according to one embodiment.  FIGS. 2A-2D  show long channel trenches  126  formed by a damascene process in a blanket first insulating layer  124  formed on the silicon substrate  122 . The first insulating layer  124  desirably is a high quality furnace-grown oxide of thickness 80-120 nm such as those typically used to form a buried oxide (BOX) layer. Alternatively, a silicon-on-insulator (SOI) wafer can be used, which is supplied with a BOX layer already formed. SOI wafers are standard starting materials commonly used in the semiconductor industry. 
         [0031]    The long channel trenches  126  formed in the first insulating layer  124  define the dimensions of the long channels such that the long channels will have widths in the range of about 5-20 nm, desirably between 7-10 nm, and a center-to-center separation, or pitch, within the range of about 34-48 nm, desirably about 44 nm. The long channel trenches  126  can be formed by a reactive ion etching (RIE) process that removes selected portions of the first insulating layer  124  and stops on the underlying silicon substrate  122 . 
         [0032]    Epitaxial silicon is then grown in the long channel trenches  126  to form long channel epitaxial fins  128 , shown in  FIGS. 3A-3D . The epitaxial silicon can be lightly doped in-situ to increase mobility of charge carriers that will traverse the long channel epitaxial fins  128  during operation of the integrated short and long channel cell  120 . The long channel epitaxial fins  128  are then planarized using a conventional chemical-mechanical planarization (CMP) process that stops on the first insulating layer  124 . 
         [0033]    Next, a second insulating layer  130  is deposited over the long channel epitaxial fins  128 , as shown in  FIGS. 3A-3D . The second insulating layer  130  is desirably 100-160 nm thick, but otherwise may be similar to the first insulating layer  124 . The second insulating layer  130  will provide vertical separation to electrically isolate the long channel epitaxial fins  128  from short channel epitaxial fins that will be formed subsequently. 
         [0034]    At  104 , a short channel epitaxial fin  138  and long channel source and drain regions  137 ,  139  are formed according to one embodiment, as shown in  FIGS. 4A-4D . The short channel epitaxial fin  138  is formed in an orientation transverse to the long channel epitaxial fins  128  and is separated vertically from the long channel epitaxial fins by the second insulating layer  130 . In one embodiment, the long channel and short channel epitaxial fins  128  and  138 , respectively, are substantially orthogonal to one another as shown in various perspective views of the integrated short channel and long channel cell  120  presented herein. 
         [0035]    First, a via-first dual damascene process is performed to create via openings  132 . The via openings  132  are etched through the second insulating layer  130  and partially into the first insulating layer  124 , as shown in  FIGS. 3A and 3D . A short channel trench  136  is then etched into the second insulating layer  130 , using a RIE process, to define a short channel fin. Like the long channel trenches  126 , the short channel trench  136  desirably has a widths in the range of about 5-20 nm, and more desirably, between 7-10 nm. The depth d of the short channel trench  136  created by the RIE process may be controlled by an advanced process control (APC) scheme so as to result in a short channel fin height h within the range of about 80-120 nm. A thickness t of the second insulating layer  130 , shown in  FIGS. 4B and 4D , remains to provide physical and electrical isolation between the long and short channel epitaxial fins  128  and  138 , respectively, and to protect the long channel epitaxial fins  128  from dishing during downstream processing. The thickness t of the remaining insulating layer is targeted to be within a range of about 30-60 nm. 
         [0036]    Next, the short channel trench  136  is filled with a blocking mask material  135 . The blocking mask material  135  is deposited so as to fill the short channel trench  136  temporarily, and further to seal off the short channel trench  136  by forming a layer on top of the second insulating layer  130 . The blocking mask material  135  therefore covers a portion of the top surface of the cell  120  to define locations of the long channel source and drain regions  137 ,  139 . The blocking mask material  135  is desirably a material other than oxide, such as polysilicon or silicon nitride (SiN) that can later be removed using a chemical process that is highly selective to the surrounding second insulating layer  130 , e.g., oxide. With the blocking mask material  135  in place, single damascene trenches  134  can be opened above the ends of the long channel epitaxial fins  128  as shown in  FIGS. 4A and 4B . Then, epitaxial silicon can be grown in the trenches  134  to form source and drain regions  137  and  139 , respectively, of the long channel transistors. If desired, the source and drain regions  137 ,  139  can be doped in-situ during the epitaxy process. 
         [0037]    Following the long channel source/drain epitaxy process, the blocking mask material  135  is stripped, according to one embodiment as shown in  FIGS. 5A-5D . The blocking mask may be stripped using, for example, a wet etch chemistry that attacks the blocking mask material, having a high selectivity to oxide. For example, if the blocking mask is made of SiN, the wet etch chemistry used to strip the blocking mask may be phosphoric acid. Once the blocking mask is removed from the short channel trench  136 , a through-oxide implant step can be used to dope the underlying long channel epitaxial fins  128  to adjust the threshold voltage of the long channel transistors. The through-oxide implant step drives dopants through the thickness t of the second insulating layer  130  to form an implant-doped region  140  in the epitaxial fins  128 , slightly below the floor of the short channel trench  136 . 
         [0038]    Finally, epitaxial silicon can be grown in the short channel trench  136  to form a short channel epitaxial fin  138  as shown in  FIGS. 6A-6D . The epitaxial silicon fills the short channel trench  136  and is then planarized to stop on the second insulating layer  130 , thus concluding formation of the short channel epitaxial fin  138 . 
         [0039]    At  106 , source and drain regions  137 ,  139  of the long channel transistors can be further doped by implantation, while gate regions are covered by a multi-gate mask  144 , according to one embodiment, as shown in  FIGS. 7A-7D .  FIG. 7A  shows the integrated short and long channel cell  120  in which the multi-gate mask  144  covers long channel gate regions LG 1  and LG 2  and a short channel gate region SG while exposing long channel source and drain regions  137 ,  139 , short channel source region  146 , and short channel drain region  148 . It is noted that, associated with each one of the long channel epitaxial fins is a pair of gates LG 1  and LG 2 . Thus, the long channel transistors are multi-gate devices. The multi-gate mask  144  is desirably a hard mask that includes one or more of polysilicon and SiN. The multi-gate mask  144  may provide contiguous coverage of the gate regions, or the mask coverage may be separated into different rectangular regions for each of the gates. 
         [0040]    With the multi-gate mask  144  in place, the long channel and short channel source and drain regions  146 ,  148  are serially implanted with dopants as shown in  FIGS. 7A, 7B, and 7D ; e.g., boron for a p-type device, or phosphorous and/or arsenic for an n-type device. A first implant photoresist mask (not shown) can be used to cover the short channel source and drain regions  146 ,  148 , while the long channel source and drain regions receive deep implants as shown in  FIG. 7B . Then, the first implant photoresist mask is stripped and replaced with a second implant photoresist mask  142 , shown in  FIGS. 7A-7C , to cover the long channel source and drain regions  137 ,  139  while the short channel source and drain regions  146 ,  148 , receive shallow implants as shown in  FIG. 7D . The long channel source and drain regions  137 ,  139  extend downward through the long channel epitaxial fin  128  into the silicon substrate  122 , while the short channel source and drain regions  146 ,  148  need only extend downward through the short channel epitaxial fin  138  into the first insulating layer  124 . The second implant photoresist mask  142  is then stripped while leaving the multi-gate mask  144  in place. 
         [0041]    At  108 , self-aligned gate recesses are formed according to one embodiment as shown in  FIGS. 8A-8D . A low-temperature TEOS hard mask  154  is initially deposited to cover the entire surface of the integrated short and long channel cell  120 . The TEOS hard mask  154  is then planarized using the multi-gate mask  144  as a CMP stop layer. When the CMP process exposes the surface of the multi-gate mask  144 , the long channel recessed gate regions LG 1  and LG 2  and the short channel recessed gate region SG are formed in a self-aligned manner by etching through the SiN multi-gate mask  144 . Etching the recessed gates can be performed using an RIE chemistry that attacks SiN, the underlying insulating layer, and silicon, with selectivity to the TEOS hard mask  154 . The recessed gates are initially etched to a same depth using advanced process control (APC). 
         [0042]    At  110 , gate recess extensions  168  are formed to wrap around the fin sidewalls, according to one embodiment as shown in  FIGS. 9A-9D . The gate recess extensions  168  can be formed by continuing the etching process using a RIE with an etch chemistry that removes SiO 2  of the first and second insulating layers  124 ,  130 , selective to the epitaxial silicon in the fins  128 ,  138 . While the short channel gate recesses only extend to wrap around three sides of the short channel epitaxial fins  138  as shown in  FIG. 9B , the depths of the recesses for the long channel gates LG 1  and LG 2  are extended downward to wrap around three sides of the long channel epitaxial fins  128  as shown in  FIG. 9C . 
         [0043]    At  112 , a gate dielectric  162 , a metal liner  164 , and a metal gate electrode  166  are formed in each of the gate recesses LG 1 , LG 2 , and SG according to one embodiment, as illustrated in  FIGS. 9A-9D . It is noted that the metal gates of the short channel and the long channel devices are formed in the same layer. The gate dielectric  162  is deposited over the long channel and short channel epitaxial fins  128  and  138 , respectively. The gate dielectric  162  can be a high-k gate dielectric material such as SiO 2 , HfO 2  or the like, materials that are well known in the art. The metal liner  164  includes a work function material, e.g., titanium nitride (TiN) or titanium carbide (TiC). Alternatively, a separate work function material may be formed after the metal liner  164  is in place. The metal liner  164  and the metal gate electrode  166  can be made of materials that are commonly used in metal gate transistors, for example, TiN, and tungsten (W) or alloys containing tungsten, respectively. Once metal has been deposited into the recesses LG 1 , LG 2 , and SG to form the metal gates, the long channel and short channel gates are planarized using a second insulating layer  140  as a stop layer. The finished metal gates of the long channel and short channel devices thus have substantially co-planar top surfaces. 
         [0044]      FIGS. 10B-10D  show designs for integrated short and long channel cells according to various alternative embodiments, as exemplified in cells  170 ,  172 , and  174 , respectively.  FIG. 10D  reproduces the perspective view of the integrated short and long channel cell  120  for reference. In one example, a high density cell  170  features very short and very long channel devices arranged so that three pairs of long channel devices fit in the footprint of each cell  120 , instead of one pair. Thus, the short channels within the high density cell  170  are three times shorter than the short channel within the cell  120 . In other examples, a footprint of the high density cell  170  may be greater than or less than the footprint of the cell  120 . In still other examples, cells  172  and  174  feature different numbers of short channel and long channel devices integrated into the same cell. For example, the cell  172  includes two long channel epitaxial fins  128  and two short channel epitaxial fins  138 . The cell  174  includes two short channel epitaxial fins  138  and one long channel epitaxial fin  128 , in which the gates of the short channel devices are co-linear with the gates of the long channel devices. Other cell configurations are possible in which different numbers or different sizes of long and short channel devices are integrated with one another. 
         [0045]    It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims. 
         [0046]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. 
         [0047]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. 
         [0048]    Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.