Abstract:
A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The sigma-delta analog-to-digital converter includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of its differential input to its differential output, (2) cross-coupling of its differential input to its differential output, and (3) setting of the differential output to a fixed voltage to discharge the parasitic capacitance associated its differential output every clock cycle. This last mode of operation eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation; while a clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation.

Description:
This application claims priority under 35 USC §119(e)(1) of provisional application Serial No. 60/323,774, filed Sep. 19, 2001. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to sigma-delta analog-to-digital converters, and, more particularly, to a sigma-delta analog-to-digital converter having an improved low power multiplexer. 
     BACKGROUND OF THE INVENTION 
     High resolution sigma-delta analog-to-digital converter (ADC) technology has become a key analog circuit technology for digital audio and telecommunications applications. Sigma-delta ADC&#39;s are capable of providing precision greatly in excess of sixteen bits. For low power applications, however, it is desirable to decrease the power consumption for the overall circuit. 
     Many conventional sigma-delta ADCs include one or more sigma-delta integrators, a comparator and a differential reference multiplexer. As is known, the sigma-delta integrators couple to receive inputs from any analog external source needing a conversion from analog to digital. The comparator couples to receive the output of sigma-delta integrator for implementation of the quantization step to generate a differential pair of decision signals. 
     As in most designs, these sigma-delta integrators require a reference voltage to operate. Thus, a reference voltage is generated using an active circuit such as an amplifier. To reduce power consumption, however, it is desirable to eliminate the active circuit. Most known designs replace the active circuit with reference voltage applied across passive filter circuit including a filter capacitor to generate reference multiplexer inputs. The reference multiplexer receives these reference multiplexer inputs along with the decision signals from the comparator. A first set of output signals from the reference multiplexer provide a shadow bit scheme and a second set of reference output signals provide either an inverted or non-inverted differential reference feedback to the sigma-delta integrator depending upon the comparator decision signals. These reference output signals represent the quantized decision of the sigma-delta integrator multiplied by the reference voltage; whereby, the sigma-delta integrator maintains the average value of the feedback to be equal to the reference voltage input. 
     The leads corresponding to the second set of reference output signals, however, each have a parasitic capacitance associated with it that generates noise in the sigma-delta ADC as a result of the reference multiplexer&#39;s dual modes of operation. In particular, in a first mode, the reference inputs directly feed into the reference outputs and, as a result, the reference voltage signal is not inverted, such that the reference voltage outputs remain the same. When the reference multiplexer switches from the first mode to the second mode, however, a first parasitic capacitor charges from the negative reference input to the positive reference input and a second parasitic capacitor discharges from the positive reference input to the negative reference input. 
     The second mode of operation cross couples the reference inputs to be fed into differing reference outputs such that the reference voltage is effectively inverted. As a result, when the reference multiplexer switches from the second mode to the first mode, the first parasitic capacitor discharges from the positive reference input to the negative reference input and the second parasitic capacitor charges from the negative reference input to the positive reference input. 
     Charging either the first or the second parasitic capacitor draws charge off the filter capacitor which reduces the reference input voltage slightly. Due to the random nature of charging and discharging the filter capacitor, low frequency noise results in the reference input voltage signal. This low frequency noise on the filtered reference degrades the SNR performance of the ADC. 
     Due to this degradation in performance, there is a need to decrease, if not eliminate, the noise in the reference voltage input signals in a sigma-delta ADC given the design constraints of low power consumption. 
     SUMMARY OF THE INVENTION 
     To address the above-discussed deficiencies of sigma-delta analog-to-digital converters (ADC), the present invention teaches a low power, sigma-delta ADC having an improved reference multiplexer that eliminates noise in the reference signal. The sigma-delta ADC includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of the differential input to the differential output, (2) cross-coupling of the differential input to the differential output, and (3) setting the differential output to a fixed voltage to discharge the parasitic capacitance in the differential output every clock cycle. This last mode eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation. A clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation that discharges the parasitic capacitance in the differential outputs of the differential multiplexer. 
     Advantages of this design include but are not limited to a low noise, low power sigma-delta ADC. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein: 
     FIG. 1 illustrates a known sigma-delta ADC; 
     FIG. 2 displays the reference voltage input signals ( 1 ) for the known sigma-delta ADC and ( 2 ) for the sigma-delta ADC in accordance with the present invention; 
     FIG. 3 shows a first portion of a known reference multiplexer; 
     FIG. 4 displays a second portion of a known reference multiplexer; 
     FIG. 5 illustrates a graph for several signals of the known reference multiplexer; 
     FIG. 6 displays a first portion of a reference multiplexer in accordance with the present invention; 
     FIG. 7 shows a second portion of a reference multiplexer in accordance with the present invention; and 
     FIG. 8 illustrates a graph for several signals of the reference multiplexer in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention is best understood by comparison with the prior art. Hence, this detailed description begins with a discussion of the known built-in sigma-delta ADC as shown in FIG.  1 . As described sigma-delta ADC shown in FIG. 1 includes one or more sigma-delta integrators  10 , a comparator  16  and a reference multiplexer  20 . Sigma-delta integrators  10  receive inputs from any analog external source needing a conversion from analog to digital. In a particular hearing aid application, the external source may be a microphone preamplifier (not shown). Clocking signals Φ 1  and Φ 2  are complementary clocking signals that do not make signal transitions simultaneously. The output of sigma-delta integrator  10  is fed into comparator  16  to implement the quantization step for generating a differential pair of signals IN p  and IN m  which represent decision signals. These decision signals, IN p  and IN m  are fed into the reference multiplexer  20  along with reference input signals, R pi  and R mi . Sigma-delta integrators  10  require a reference voltage to operate which is generated using an active circuit such as an amplifier used as a buffer. To reduce power consumption, however, it is desirable to eliminate the active circuit and replace it with a passive filter circuit including capacitor  24  and resistor  22  to generate reference multiplexer inputs, R pi  and R mi , where the reference voltage is applied at the reference voltage nodes, V ref   +  and V ref   − . 
     Whenever a bit switches, it draws current out of the power supply, such that the current pulled from the power supply is signal dependent. Thus, if there is imperfect power supply rejection in the analog portion of the block and the same power supply is shared for the logic, unintentional feedback from the output signal may be generated back to the power supply and analog blocks. The first set of output signals, SBIT and BIT, provide shadow bit scheme whereby, if the logical output is a ‘1’, a pulse would be provided on the output BIT and, if the logical output is a ‘0’, a pulse would be provided on the output SBIT. The second set of reference output signals, R p0  and R m0 , provide either an inverted or non-inverted differential reference feedback to the sigma-delta integrator  10  depending upon the comparator  16  decision. Sigma-delta integrator  10  only needs the reference voltage for half time when the integration clock phase Φ 2  is high. Sigma-delta systems include a feedback similar to the reference output signals, R p0  and R m0 , which represent the quantized decision multiplied by the reference voltage. The sigma-delta integrator  10  maintains the average value of the feedback to be equal to the input. 
     The known reference multiplexer  20  includes a first portion  30  as shown in FIG. 3 and a second portion  60  as shown in FIG.  4 . The first portion  30  includes cross coupled NAND gates  32  and  34  coupled to inverters  36 ,  38 ,  40  and  42  to define nodes A, B, C, and D. NAND gates,  44  and  46 , couple to receive the outputs from nodes C and D as well as node N 2 . Through inverters  48  and  50  these NAND gates,  44  and  46 , provide output signals to nodes SBIT and BIT. 
     FIG. 4 represents the second portion  60  of the known reference multiplexer  20 . Reference inputs, R pi  and R mi , couple to transistors  62 ,  64 ,  66 , and  68  to form nodes A, B, C and D. Reference outputs, R p0  and R m0 , couple to reference input signals R pi  and R mi  depending upon which switches are on and off. Using FIG. 5, when input signal IN p  is low and input signal IN m  is high, node A goes from high to low which switches transistor  66  off and node D switches from low to high which switches transistor  64  off. The transition in node D causes node B to switch from low to high and accordingly node C switches from high to low. This arrangement prevents transistors  62  and  66  from being on at the same time as well as transistors  64  and  68  from being on at the same time. The objective is not to short reference inputs, R pi  and R mi , where neither transistors  62  and  66  are on at the same time nor transistors  64  and  68  are on even for a short incidence due to a change in the decision input IN p . The arrangement of cross-coupled NAND gates and inverters which form delays insures that theses switches are not simultaneously on. NAND gate  32  prevents signal B from switching until signal D has switched. NAND gate  34  prevents signal A from switching until signal C has switched. Since transistors,  66  and  68 , are NMOS transistors, when nodes A and B are high, each transistor,  66  and  68 , is on. Accordingly, when nodes A and B are low, each transistor,  66  and  68 , is off. Since transistors,  62  and  64 , are PMOS transistors, when nodes C and D are low, each transistor,  62  and  64 , is on. Accordingly, when nodes C and D are high, each transistor,  66  and  68 , is off. 
     Reference multiplexer  20  has two modes of operation. The first mode includes the reference inputs, R pi  and R mi , directly fed into the parallel reference outputs, R p0  and R m0 . In this mode, the reference voltage signal is not inverted, such that the reference voltage outputs, R p0  and R m0 , remain the same. Specifically, in this first mode, when nodes B and D are high and nodes A and C are low, transistors,  62  and  68 , are on and transistors,  64  and  66 , are off. When reference multiplexer  20  switches from the first mode to the second mode, however, capacitor C p1  charges from reference input R mi  to reference input R pi  and capacitor C p2  discharges from reference input R pi  to reference input R mi . 
     The second mode of operation cross couples the reference inputs, R pi  and R mi , to be fed into differing reference outputs, R m0  and R p0 , such that the reference voltage V ref  is effectively inverted. Specifically, in this second mode, when nodes A and C are high and nodes B and D are low, transistors,  64  and  66 , are on and transistors,  62  and  68 , are off. As a result, when reference multiplexer  20  switches from the second mode to the first mode, capacitor C p1  discharges from reference input R pi  to reference input R mi  and capacitor C p2  charges from reference input R mi  to reference input R pi . 
     Charging the capacitor C p1  or C p2  draws charge off the filter capacitor  24  which reduces its voltage slightly. This second mode of operation is a random event. As explained, due to this random nature of charging and discharging the filter capacitor, noise results in the reference input voltage signal R pi  which is shown as the signal labeled ( 1 ) in the graph of FIG.  2 . This low frequency noise on the filtered reference degrades the SNR performance of the ADC. 
     The sigma-delta ADC having an improved reference multiplexer as shown in FIGS. 6 and 7 in accordance with the present invention which eliminates noise. FIG. 6 illustrates the first sub-circuit portion of the reference multiplexer in accordance with the present invention. Clock signal input Φ 1  is fed into inverter  102  to control when both lines of the multiplexer output, R mo  and R po , are both connected to the minus voltage reference R mi . Input signal IN p  connects to inverter  104 . The output of inverters  102  and  104  couple into NAND gate  110 . The output of inverter  104  feeds into inverter  108  to provide input for NAND gate  112  along with the output of inverter  102 . NAND gate  110  supplies output to a first cross coupled NAND gate pair,  116  and  118 . NAND gate  112  supplies output to a second cross-coupled NAND gate pair,  132  and  134 . These two pairs are to provide the three modes of operation which will be discussed. The first cross coupled pair,  116  and  118 , include inverters  120 ,  122 ,  124 ,  126 , and  128  coupled to form nodes B, D and SBIT. The second cross coupled pair,  132  and  134 , include inverters  136 ,  138 ,  140 ,  142 , and  144  coupled to form nodes A, C and BIT. FIG. 7 displays the second portion of the improved reference multiplexer similar to FIG. 4 as discussed above for the known reference multiplexer  20  and remains virtually the same. 
     In operation, there are three modes of operation. As explained, the clock signal input Φ 1  determines when both lines of the multiplexer output, R mo  and R po , are both connected to the negative voltage reference R mi . In a first mode of operation, when the clock signal input Φ 1  is high, both reference outputs R po  and R mo  are forced to reference input R mi  which discharges the two parasitic capacitors C p1  and C p2 , since transistors  152  and  154  are off and transistors  156  and  158  are on. Thus, in this state both parasitic capacitors C p1  and C p2  are discharged at every cycle. This corresponds to a new decision in the sigma-delta integrator  10  to remove the signal dependence on the drain of charge of the filter capacitor C f . When the clock signal input Φ 1  is low, which is indicative of the sigma-delta integrator  10  needing the reference voltage, either one of the reference outputs R po  and R mo  will make a transition from low to the positive reference voltage R pi  depending on the decision signal IN p . In a second mode of operation where the clock signal input Φ 1  is low and the decision signal IN p  is high, the reference outputs R po  and R mo  directly couple to reference inputs R pi  and R mi , respectively. In this mode, nodes B and D are high and nodes A and C are low, transistors,  152  and  158 , are on and transistors,  154  and  156 , are off. In the third mode of operation, where the clock signal input Φ 1  is low and the decision signal IN p  is low, the reference outputs R po  and R mo  cross couple to reference inputs R mi  and R pi , respectively. In this mode, nodes A and C are high and nodes B and D are low, transistors,  152  and  158 , are off and transistors,  154  and  156 , are on. Thereby, this improved reference multiplexer  100  proves an additional state, the first state, that discharges the parasitic capacitors C p1  and C p2  to eliminate noise while providing a complementary pair of signals that are guaranteed not to be on or off at the same time. 
     The improved first portion of reference multiplexer  100  no longer needs the gating logic of FIG. 3 that is controlled by signal N 2  to correct outputs SBIT and BIT because the behavior of the outputs are appropriate for these two signals SBIT and BIT of multiplexer  100 . 
     In addition, FIG. 2 shows the distinction between the prior art reference output signal, signal ( 1 ), and that of the ADC in accordance with the present invention, signal ( 2 ). The DC voltage difference between signal ( 1 ) and ( 2 ) is a result of the charge being drawn off the filter capacitor  24  for signal ( 1 ) in a data dependent way. For signal ( 2 ), however, charge is drawn off the filter capacitor  24  every clock cycle. Thus, signal ( 2 ) has a lower DC value than signal ( 1 ). 
     FIG. 8 illustrates corresponding transitions in signals Φ 1 , Φ 2 , IN p , R po , and R mo . Clocks Φ 1  and Φ 2  are complements of one another and are never simultaneously high. When clock Φ 2  is high, this is indicative of when the sigma-delta integrator  10  needs the reference voltage. The reference output signals R po  and R mo  that feed back to the sigma-delta integrator  10  are only used during the integration clock phase of signal Φ 2 . Thus, when signal Φ 2  is high, this is when the integrator  10  is using the reference output signals R po  and R mo . 
     The foregoing described sigma-delta ADC&#39;s primary application may be incorporations in any low power application including hearing aid devices. 
     Advantages of this design include but are not limited to a sigma-delta ADC having a high performance, simple, and cost effective design. 
     The reader&#39;s attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. 
     All the features disclosed in this specification (including any accompany claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
     The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.