Abstract:
A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority to U.S. Provisional Application No. 60/720,653, filed Sep. 27, 2005, entitled “Apparatus and Method for Reducing Parasitic Capacitance in a Semiconductor Device,” incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     As wireless devices are becoming increasing faster and smaller, the power consumption, reliability, and performance of a voltage controlled oscillator (VCO) in such devices have become a design focus. A VCO is typically used in modulating and demodulating a radio frequency (RF) signal by mixing the un-modulated or modulated signal with a locally generated oscillating signal. For example, when demodulating a RF signal, it is important to accurately match the VCO&#39;s generated oscillating signal with the RF&#39;s carrier signal. This is especially critical in high frequency application, as phase noise and jitters are more prevalent and detrimental to the performance of the VCO.  
         [0003]     In high frequency application, the accurate generation of a high frequency oscillating signal depends on several factors such as the tunability of the VCO, Q factor, and the parasitic elements of the VCO&#39;s components. The tunability factor of the VCO is determined by the change of frequency generated by the VCO over the change of the input control voltage. Even though a VCO could be optimally designed for a specific high frequency application, manufacturing process tolerances will invariably introduce inaccuracies into the VCO. Thus it is important for a VCO to be tunable. Generally, it is desirable for a VCO to have a wide range of tunable frequency. However, broad tuning capability increases the VCO&#39;s susceptibility to noise and system variations due to the enhanced tuning sensitivity. As a result, it is important to maintain a high Q factor by lowering the parasitic components of the VCO&#39;s circuit. VCO tuning is implemented using a LC tank circuit including one or more inductors and capacitors.  
         [0004]     Phase noise of the VCO can be reduced by maintaining a high Q factor in the LC tank. A high Q in the LC tank not only reduces phase noise but also increases performance and reduces power consumption of the VCO. To maintain a high Q in the LC tank, the parasitic components of the VCO&#39;s circuit must be reduced.  
         [0005]     There are three parasitic components in a semiconductor device. They are resistive, capacitive, and inductive. These parasitic components negatively effect the reliability, performance, and power consumption of the device. In high frequency application, the inductors and capacitors of the VCO are generally integrated into a semiconductor device. Several methods are available to reduce the parasitic components of the device as a whole. For example, in fabricating an inductor, trenches or void space are introduced into a substrate layer directly underneath the inductor. The same method can also be used in fabricating the capacitor.  
         [0006]     Typically, reduction of parasitic components are focused on the inductors and the capacitors. But as a semiconductor device gets progressively smaller it becomes more sensitive to signal propagation delays caused by parasitic resistance and capacitance inherent to the interconnection lines within the device. A wider interconnection line could be used to ease this problem; however, this will increase the parasitic capacitance of the line to the ground. Even though the parasitic capacitance and resistance of an interconnection line may seem small by itself, collectively it could reduce the Q factor of the semiconductor device. Thus to increase the performance of the semiconductor device and to maintain a high Q factor, it is necessary to reduce the parasitic components inherent to the interconnection lines.  
         [0007]     Accordingly, there is a need in the art for a semiconductor device and a method to fabricate such a semiconductor device with reduced parasitic resistance and capacitance.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES  
       [0008]     The present invention is described with reference to the accompanying drawings.  
         [0009]      FIG. 1  illustrates an exemplary schematic of a VCO that may incorporate embodiments of the present invention;  
         [0010]      FIG. 2A  illustrates an interconnection wire in a semiconductor device;  
         [0011]      FIG. 2B  illustrates a conventional method for shielding an interconnection wire;  
         [0012]      FIG. 3  illustrates a shielding method in accordance to the an embodiment of the present invention;  
         [0013]      FIG. 4  illustrates another shielding method that may be used in embodiments of the present invention;  
         [0014]      FIG. 5  illustrates an exemplary integrated circuit layout containing embodiment of the present invention;  
         [0015]      FIG. 6  illustrates a flow diagram for practicing an embodiment of the present invention.  
         [0016]      FIG. 7  illustrates a flow diagram for practicing another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]     This specification discloses one or more embodiments that incorporate the features of this invention. The embodiment(s) described, and references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.  
         [0018]     An embodiment of the present invention is now described. While specific methods and configurations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the art will recognize that other configurations and procedures may be used without departing from the spirit and scope of the invention.  
         [0019]      FIG. 1  illustrates a VCO circuit that may employ embodiments of the present invention. The VCO circuit includes a pair of inductors  102  and  104 , two pairs of capacitor  118 ,  120 ,  122 , and  124  that overall comprises a LC tank. The VCO also comprises a pair of cross-coupled n-channel MOSFET (NMOS)  106  and  108 . Four switches  110 ,  112 ,  114 , and  116  provide frequency tuning by switching in corresponding capacitors  118 ,  120 ,  122 , and  124 , respectively. Even though NMOS devices are shown in  FIG. 1 , other types of devices may be used such as JFET, p-channel MOSFET, or bipolar. In an embodiment, switches  110 - 116  are NMOS. In an alternative embodiment, different devices could be used such as JEFT or PMOS for switches  110 - 116 .  
         [0020]     In an integrated circuit, the VCO circuit of  FIG. 1  may be fabricated on a multi-layer substrate where each of the devices (capacitor, inductor, and switch) are coupled with interconnection wires  130 - 146 . Interconnection wires are metal lines connecting various electronic devices within the integrated circuit. Each of these interconnection wires has its associated parasitic resistance and capacitance that will contribute to the overall parasitic resistance and capacitance of the LC tank. As a result, the Q factor of the VCO degrades due to the increased parasitic components.  
         [0021]      FIG. 2A  is a cross-sectional view of an interconnection wire in a multi-layer substrate of a semiconductor device. The semiconductor device portion  200  comprises a metal element  210 , and substrate layers  212 ,  224 , and  216 . Substrate  212  and  224  may be composed of dielectric material such as organic polyimide, silicon dioxide, or aerogel. Although semiconductor portion  200  shows a metal element  210  embedded between the two substrate layers  212  and  224 , the metal element could also be suspended in one uniform substrate layer. For example, substrate  212  and  224  could be made of the same material having the same dielectric constant. Alternatively, semiconductor device  200  does not include layer  224 . In this way, metal element  210  is exposed to air.  
         [0022]     For modeling purpose,  FIG. 2A  shows a capacitive element C wire    220  and a resistive element R wire    222  associated with the metal element  210 . At a micro level, the metal element (interconnection wire)  210  can be modeled as a narrow plate. For a narrow plate, fringe capacitance is a factor due to the electric field flux lines coming from the side of the plate. Therefore, the total capacitance of a narrow plate is the combination of fringe capacitance and the parallel plate capacitance. The simplified equation for the parasitic capacitance of an interconnection wire is shown below. Where W and H are the  
         c   wire     =         c   pp     +     c   fringe       =         w   ⁢           ⁢     ɛ   di         t   di       +       2   ⁢           ⁢     πɛ   di         log   ⁡     (       t   di     /   H     )                 
 
 width and height of the wire, respectively. E di  is the dielectric constant of the substrate layer  212 . And T di  is the thickness of the substrate layer  212 . 
 
         [0023]      FIG. 2B  illustrates a method to shield to the metal element in an effort reduce cross-talk, substrate noise, and signal propagation delays.  FIG. 2B  shows a metal layer  230  being added and grounded between the dielectric layer  212  and the substrate layer  216 . However, adding a metal layer  230  will increase the parasitic capacitance of the semiconductor device. This is due to the smaller distance between the metal layer  230  and metal element  210 . Substrate layer  216  is typically composed of a P-type substrate. In a silicon based substrate, acceptor dopant (p-type) such as boron could be used to form the P-substrate. Alternatively, in a gallium arsenide based substrate, carbon, beryllium or zinc could be used as the acceptor dopant. Because of the high resistivity, the substrate  216  carries a parasitic resistance element  222  that degrades the overall Q factor of the semiconductor. This associated parasitic resistance of substrate layer  216  can be avoided with the addition of the metal shield layer  230  at the expense of extra parasitic capacitance between metal element  210  and metal layer  230 .  
         [0024]      FIG. 3  illustrates an exemplary semiconductor device  300  in accordance to an embodiment of the present invention. The semiconductor device  300  includes a metal element  310 , substrate layers  312 ,  316 ,  324 , a ground layer  314 , and a low resistive layer  340 . Although semiconductor portion  300  shows a metal element  310  embedded between the two substrate layers  312  and  324 , the metal element could also be suspended in one uniform substrate layer. Substrate layers  312  and  324  may be made of the same dielectric material. In an alternative embodiment, metal element  310  is formed on top of substrate layer  312  and layer  324  is not present.  
         [0025]     In the semiconductor device  300 , a ground layer  314  is formed on the substrate layer  316 . The ground layer  314  is electrically coupled to a ground (not shown). The ground layer  314  includes an opening  326  that extends through the entire ground layer  314 . In an alternative embodiment, the opening  326  only extends through a portion of the ground layer&#39;s  314  thickness. The opening  326  is designed to locate directly underneath the metal element  310 . Alternatively, depending on the relative position of observation, the opening  326  is designed to locate directly above metal element  310 .  
         [0026]     In the opening  326 , a substrate layer  340  is formed. Substrate layer  340  is highly P doped as compared to the P substrate layer  316 . Substrate layer  340  may be formed by masking layer  316  prior to the doping of substrate layer  340 . In an embodiment, substrate layer  340  is formed by heavily doping the substrate layer  316  with an acceptor dopant such as boron. In this way, a P+ type substrate material is formed. In an alternative embodiment, substrate layer  316  can be doped with acceptor dopant such as carbon, beryllium or zinc. As the result of the highly concentrate P doping, substrate layer  340  exhibits a very low resistivity as compared to the resistivity of the substrate layer  316 .  
         [0027]     As shown in  FIG. 3 , the substrate layer  340  is directly beneath metal element  310 . Alternatively, if the semiconductor device  300  is flipped upside down, the substrate layer  340  is directly above the metal element  310 . The relative position of substrate layer  340  and the metal element  310  is not exactly restrictive as long as the modeled parasitic capacitive element  320  appears between the metal element  310  and the substrate layer  340 . For example, the metal element  310  may be skewed or off centered with respect to a perpendicular centerline of the substrate layer  340 .  
         [0028]     In the semiconductor  300 , ground layer  314  is in contact with the substrate layer  340  thereby electrically grounding it. In an alternative embodiment, the ground layer  314  is not in contact with the substrate layer  340 , but the substrate layer  340  is electrically coupled to ground with other means such as a ground wire connecting the two.  
         [0029]     With the presence of the low resistive layer  340 , the parasitic resistance component  322  is smaller as compared to the parasitic resistance component  222 . The resistive component  322  is smaller due in part to the grounding path  330  (low resistive path) formed in the highly p-type doped layer  340 . In this way, the low resistive path to ground helps reduces the parasitic resistance  322 .  
         [0030]      FIG. 4  illustrates an exemplary semiconductor device  400  in accordance to another embodiment of the present invention. The semiconductor device  400  includes a metal element  410 , substrate layers  412 ,  416 ,  424 , a ground layer  414 , and a low resistive layer  440 . Although semiconductor portion  400  shows a metal element  410  embedded between the two substrate layers  412  and  424 , the metal element could also be suspended in one uniform substrate layer. Substrate layers  412  and  424  may be made of the same dielectric material. In an alternative embodiment, metal element  410  is formed on top of substrate layer  412  with no top layer  424 .  
         [0031]     In the semiconductor device  400 , a substrate layer  440  is formed on the substrate layer  416 . Substrate layer  440  is highly P doped as compared to the P substrate layer  416 . As the result of the highly concentrate P doping, substrate layer  440  exhibits a very low resistivity as compared to the resistivity of the substrate layer  416 .  
         [0032]     As shown in  FIG. 4 , the substrate layer  440  is directly beneath metal element  410 . Alternatively, if the semiconductor device  400  is flipped upside down, the substrate layer  440  is directly above the metal element  410 . The relative position of substrate layer  440  and the metal element  410  is not exactly restrictive as long as the modeled parasitic capacitive element  420  appears between the metal element  410  and the substrate layer  440 . For example, the metal element  410  may be skewed or off centered with respect to a perpendicular centerline of the substrate layer  440 .  
         [0033]     In the semiconductor  400 , the substrate layer  440  is electrically coupled to a ground (not shown). As a result, a path to ground  430  is provided through the low resistive layer  440 , thereby lowering the parasitic resistance component  422  of the semiconductor device  400 .  
         [0034]      FIG. 5  depicts a top view of an exemplary circuit layout of a semiconductor device  500  in accordance with an embodiment of the present invention. Semiconductor device  500  includes capacitor bank  510 , buffer  516 , NMOS circuitry  518 , inductors  512  and  514 , interconnection lines  520 , highly P doped (low resistive) layer  522 , and grounding lines  526 .  
         [0035]     In the semiconductor  500 , interconnection lines  520  electrically connect the capacitor bank  510 , inductors  512  and  514 , buffer  516 , and NMOS  518  together. The highly P doped layer  522  lies between the interconnection lines  520  and the base substrate. In this way, the highly P doped layer  340  provides a low resistive barrier between the interconnection line  520  and the substrate layer  416  (see  FIG. 4 ). In an embodiment, the highly P doped layer  340  is intermittently coupled to the grounding lines  526 . In an alternative embodiment, the grounding lines  526  are formed in continuous contact with highly P doped layer  340 .  
         [0036]     Referring to  FIG. 6 , in block  610  a substrate layer is provided. This substrate layer could be a silicon based substrate, gallium arsenide based substrate or any other suitable substrate. In block  620 , a highly P doped region  440  is formed. This P+ doped region  440  is formed on substrate layer  416  or within the substrate layer  416 . The P+ region is highly P doped with dopant as compared to the substrate layer  416 . In block  630 , the P+ region is electrically coupled to ground. This could be accomplished using a grounding layer or through via that is electrically coupled to a ground or with other suitable grounding means.  
         [0037]     In block  640 , an insulating layer  412  is formed on the P+ region. In block  650 , an interconnection line  410  is formed on the insulating layer  412 . The interconnection line  410  is formed such that it is directly above the highly P+ doped region  440 . Alternatively, depending on the relative position of observation, the interconnection line  410  is formed directly below the highly P+ doped region  440 .  
         [0038]     Referring to  FIG. 7 , in block  710  a substrate layer is provided. This substrate layer could be a silicon based substrate, gallium arsenide based substrate or any other suitable substrate. In block  720 , a ground layer  314  is formed on the substrate layer. The ground layer  314  can be made with metal or with any other suitable grounding materials. In block  730 , the ground layer is then electrically coupled to ground. In block  740 , a highly P doped region  340  is formed. This P+ doped region  340  is formed on substrate layer  316  or within the substrate layer  316 . The P+ region  340  is preferably located in an opening of the grounding layer  314 . The P+ region is highly P doped with dopant as compared to the substrate layer  316 .  
         [0039]     In block  750 , the P+ region is electrically coupled to ground. This could be accomplished using a grounding layer or through via that is electrically coupled to a ground or with other suitable grounding means. In block  760 , an insulating layer  312  is formed on P+ region. In block  770 , an interconnection line  310  is formed on the insulating layer  312 . The interconnection line  310  is formed such that it is directly above the highly P+ doped region  340 . Alternatively, depending on the relative position of observation, the interconnection line  310  is formed directly below the highly P+ doped region  340 .  
       CONCLUSION  
       [0040]     While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.