Abstract:
A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to programmable devices, more particularly to a method and apparatus for effectively re-downloading data to a Field Programmable Gate Array (FPGA), which can easily re-configure the FPGA to increase convenience and speed in R&amp;D and upgrade, and further save developing costs. 
   2. Description of the Related Art 
   Field Programmable Gate Arrays (FPGAs) are frequently used in multimedia, workstations, communications, networks and other applications. The appealing characteristics of FPGAs are speeds approaching those of an integrated circuit (IC) and programmability for design simulation and trial-and-error flexibility. 
   FPGAs are essentially configured in SRAM based mode and Anti-fuse-based mode. The SRAM based mode is widely used for IC design mode in the aforementioned applications. 
   The advantages for the SRAM based mode include reprogrammability, low power consumption and in-circuit configurability. However, this mode typically downloads configuration data from a host system such as a computer or workstation using an FPGA interface cable. As such, the performance for such a mode depends on joint download circuits. 
     FIG. 1  is a schematic diagram of an internal circuit of a typical Field Programmable Gate Array (FPGA). As shown in  FIG. 1 , existing download circuits generally use a Non-Volatile Random Access Memory (NVRAM) to store configuration data codes required by design circuit in the FPGA. However, such an application requires a control access circuit  16  with two functions: one for downloading external update configuration data codes to NVRAM  14  (namely Write-to-NVRAM function) and the other for writing configuration data codes in NVRAM  14  to FPGA  12  (namely Write-to-FPGA function). The cited circuits are normally integrated into a printed circuit board (PCB)  10 . Thus, a user can easily change the configuration circuit in FPGA when performing R&amp;D. When initialing mass-production, configuration data codes are directly downloaded without changing PCB circuitry. However, after mass-production is complete, the Write-to-NVRAM function is not needed. Accordingly, the circuit  16  including functions of downloading configuration data codes to NVRAM  14  and reading configuration data codes from NVRAM  14  is set aside, wasting resources. Additionally, in some products separating the two functions, when initialing mass-production, only the Write-to-FPGA function is left with operating codes. As such, the circuit  16  is removed to thus eliminate resource waste. However, as updates required by FPGA must extract NVRAM and then write new configuration data codes by existing burner or other devices, thus causing inconvenience in R&amp;D and difficulty in upgrade. 
   SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide a method for effectively re-downloading data to a Field Programmable Gate Array (FPGA), which easily re-configures the FPGA to increase convenience and speed in R&amp;D and upgrade, thereby further saving development costs. 
   The present invention is generally directed to a method for effectively re-downloading data to a Field Programmable Gate Array (FPGA), which has a feature of repeated on-board data download to FPGA such that convenience in R&amp;D is increased and further product upgrade speed is increased. The method includes using two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit such that according to a detection state output by the detection circuit to the one CPLD implementing Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA. Thus, repeated on-board data download to FPGA is obtained and has re-configuration convenience and performance. 

   
     DESCRIPTION OF THE DRAWINGS 
     The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
       FIG. 1  is a block diagram of a typical Field Programmable Gate Array (FPGA) download circuit; 
       FIG. 2  is a block diagram of an FPGA download system according to the invention; 
       FIG. 3  is an embodiment of a download circuit according to  FIG. 2  of the invention; and 
       FIG. 4  is a schematic diagram of interior circuit of connectors according to  FIG. 3  of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  is a block diagram of a Field Programmable Gate Array (FPGA) download system according to the invention. In  FIG. 2 , the system essentially includes a first download circuit  201  and a second download circuit  202 . The first download circuit  201  transfers information for updating data on the download side and provides a control signal for controlling download procedure. The second download circuit  202  receives the information from the first download circuit  201  and write the information into a Non-Volatile Random Access Memory (NVRAM) (described later). The NVRAM can be a flash memory. After external data is written in the NVRAM to complete configuration data code update, the updated information is then written in a master FPGA  24 . The master FPGA can convert the information (from a host  21  through an interface  23 ) into a format to be accepted and used by a slave FPGA. 
   As shown in  FIG. 2 , if data is downloaded from the host  21 , the data is transferred to the device  202  through a control line  2  and a data bus  1 . When a Write-to-FPGA occurs, the data is transferred in acceptable and usable format from the device  202  to the device  24 . If more FPGAs are connected to the device  24 , the data is sequentially transferred to the FPGAs. When an update or test requirement for the device  24  or  25  content occurs, a first connector  205  is connected to a second connector  217  to transfer the control right from the device  202  to the device  201  through the control line  2 . At this point, an external signal Erase is input through a pin  209  and a control signal is delivered by a host  21  through an interface  23  to, for example, a pin of the device  201  firstly, to erase existing NVRAM content and then pins Din, pc-clk and connectors  205 ,  217  to directly write new data into the NVRAM. The devices  201  and  202  are further described in the following. 
     FIG. 3  shows an embodiment of the devices  201  and  202   1 S of  FIG. 2  according to the invention. In  FIG. 3 , the device  201  essentially includes a first control block and a first connector  205 , and the device  202  essentially includes a second connector  217 , an NVRAM  211  and a second control block  212 . The devices  201  and  202  are two independent units and communicate with each other through the built-in connectors  205  and  217  respectively. 
   As shown in  FIG. 3 , this embodiment adds a detection circuit (described later) and separates FPGA download circuit into the Write-to-NVRAM (first) download circuit  201  and the Write-to-FPGA (second) download circuit  202  for both cost efficiency and design convenience. The control blocks  203  and  212  are implemented by two Complex Programmable Logic Devices (CPLDs), wherein that for the block  203  requires larger capacity than that for the block  212 . The two devices  201  and  202  are connected by the built-in connectors  205  and  217  with n+13 pins, wherein n is bit number of address bus  207  for NVRAM  211  write, and 13 pins respectively represent 8-bit data bus  208 , 4-bit control signal (including a chip enable signal (ce) pin, an output enable signal (oe) pin, a write enable signal pin, and a detection state signal pin  215  for a detection state signal  206  of the detection circuit), and a clock signal pin  204 . The devices  201  and  202  use the corresponding CPLD download pins  214  to enable download action such that the download cable transfers configuration data codes to be written in the NVRAM  211  from the host  21  ( FIG. 2 ) to the device  201  or serially transmits configuration data codes stored in the NVRAM  211  to the FPGAs  24  and  25  ( FIG. 2 ) through initialized block  212 , wherein initialized action for the block  212  (initialized block) is completed by initializing an initialization signal init (through a pin  213 ) from the device  24  to the block  212  and the device  25 . In addition, circuit synchronization in this case is performed by sending a master clock signal CCLK ( FIG. 2 ) from the device  24  to clock pins  204 ,  210  of all devices. The device  212  can access the device  211  through a control pin  219  for receiving control signals from the device  24  to the device  202 . Access action for the NVRAM  211  is performed by a bi-directional bus  218 . Upon the cited separate connectors  205  and  217 , data-readout for the NVRAM  211  can be independently performed. However, data write to the NVRAM  211  is dependent on the pin  215  of the detection circuit to signal the device  212  floating all data and pins as a high impedance state. The detection circuit built in the connectors is further described in the following. 
     FIG. 4  is a schematic diagram of the interior of the separate connectors of  FIG. 3  according to the invention. In  FIG. 4 , the separate connectors include the detection circuit  303 ,  304  respectively implemented on the separate connector in addition to pins of signals CCLK, Data, Addr and Ctrl shown in  FIG. 3  for electrical connection. 
   As shown in  FIG. 4 , the detection circuit includes a grounded shorted-circuit pin  303  implemented on the connector  205  (as a daughter board) side and a detection resistor R with about 10 K Ohm implemented between the pin  215  and an operating voltage VCC on the connector  217  (as a mother board) side. Thus, when the connectors  205  and  217  are disconnected, the pin  215  is in an open state with logic 1 (high potential). In contrast, when the connectors are connected, the pin  215  presents a closed state with logic 0 (low potential) to form a pathway. Accordingly, data flow direction is determined, i.e. The direction flowing from/to the device  21 . Briefly, data is read from the device  211  to the device  24  when the pin  215  outputs high potential and conversely data is written into the device  211 . 
   While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.