Abstract:
The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Description:
CROSS-REFERENCE TO A RELATED APPLICATION 
       [0001]    This application is a Continuation-In-Part (CIP) Application of U.S. patent application Ser. No. 12/572,030 filed on Oct. 1, 2009, the disclosure of which is incorporate herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a test method and a test circuit, and more particularly, to a method for testing a through-silicon-via and the circuit thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    Three-dimensional integrated circuit (3D IC) technology, a promising technology in the field of modern electronics, is a technology in which two or more layers of active electronic components are integrated into a chip. In other words, a 3D IC packages a plurality of ICs into a single chip. Compared with a traditional single IC chip, a 3D IC provides a faster signal transmission rate between ICs, generates less noise, consumes less power, occupies less space and produces better performance. 
         [0006]    Recent research and development in 3D IC technology has emphasized the benefit of increased packing density attainable by stacking a growing number of ICs. In addition, 3D IC technology offers an opportunity to integrate heterogeneous processes in a more efficient manner, improves speed performance with smaller interconnect delays, decreases power consumption with shorter wire lengths and increases data bandwidth by using short vertical links or vertical interconnection between dies known as through-silicon-via (TSV). According to the step of TSV formation in an overall 3D IC manufacturing sequence, we could classify TSV technologies into two main categories, namely, via-first and via-last. One categorization is to separate by the bonding step. The via-first processes form the TSVs on each wafer prior to the bonding step, and the via-last processes form the TSVs after. Compared with other alternatives for linking the plurality of ICs, such as wire bonding and micro-bumping, TSVs achieve higher interconnection density and better performance. 
         [0007]    In spite of the advantages mentioned above, there are some problems associated with 3D IC technology. One of the most important issues is the compound yield loss due to IC stacking. To guarantee the stacking yield, the interconnection must be tested. The current interconnection test proposed for 3D IC is done with two or more dies in a stack, which is good only for TSVs after bonding. Essentially, after two dies are bonded, the TSVs can be connected serially to form a daisy chain in an electric test or connected with flip-flops to form a scan chain in a structure test. There needs high reliability TSV channels for test control or scan path. With the same test circuit in each layer, they can be tested in a complete or partial stack. 
         [0008]    However, there are some limitations in these test schemes. First, they cannot be performed before bonding. A straightforward way for an electric test uses a daisy chain structure of by alternate routes of TSVs on both the front and back sides of the wafer. Apparently, this scheme is suitable only for the wafer acceptance test (WAT), since it is extremely difficult, if not impossible, to dismantle and rework the back metal once the TSV test is done. As a result, the observation of TSV failures at this stage relies solely on a couple of test keys on the scribe line. Second, individual TSVs are indistinguishable in a serial scan chain or a daisy chain, so diagnosis becomes an issue. Probing both ends of a TSV can measure its resistance as the pass/fail criterion, but the area overhead for direct access is high, and thus is limited to a small number of sparse TSVs. Also, in general, for a die before bonding, the TSVs have one end on the backside that is not only floating but also buried deeply in the wafer substrate before thinning. Third, in the case of a via-first process, which intend to provide an interconnection density as high as 10 4 /mm 2 , on-chip TSV monitoring becomes necessary. However, there are not always flip-flops connected to both ends of each TSV. In addition, the TSV failure rate affects the final yield exponentially with the number of dies in a stack. Unfortunately, it remains relatively high (&gt;10 ppm). Without screening out the bad ones, the overall yield of the die stack will be low. 
         [0009]    In view of the above, it is necessary to design a test method, which not only can be performed on TSVs before bonding, but also allows each TSV to be tested individually. 
       SUMMARY OF THE INVENTION 
       [0010]    The TSV test circuit according to one embodiment of the present invention comprises a charge circuit, a discharge circuit and a sense device. The charge circuit is configured to charge at least one TSV. The discharge circuit is configured to discharge the at least one TSV. The sense device is configured to sense the states of the at least one TSV. 
         [0011]    The TSV test circuit according to another embodiment of the present invention comprises a charge circuit, a discharge circuit and a sense device. The charge circuit is configured to charge at least one TSV. The discharge circuit is electrically coupled to the charge circuit and is configured to discharge the at least one TSV. The sense device is electrically coupled to the discharge circuit and is configured to sense the states of the at least one TSV. 
         [0012]    The TSV test circuit according to another embodiment of the present invention comprises a charge circuit, a switch device and a sense device. The charge circuit is configured to charge a TSV to a predetermined voltage level. The switch device is configured to connect the through-silicon-via to another capacitance device. The sense device is configured to compare the voltage level of the through-silicon-via with at least a reference voltage level. 
         [0013]    The method for testing a TSV according to one embodiment of the present invention comprises the steps of: resetting a through-silicon-via under test to a first state; determining that the through-silicon-via under test is faulty if the through-silicon-via enters a second state within a first period of time, wherein the state of the through-silicon-via is determined by sensing technique, and the resetting and sensing are performed at only one end of the through-silicon-via. 
         [0014]    The method for testing a TSV according to another embodiment of the present invention comprises the steps of: resetting a through-silicon-via under test to a first state; determining that the through-silicon-via under test is faulty if the through-silicon-via remains in the first state or enters a second state within a period of time, wherein the state of the through-silicon-via is determined by sensing technique, and the resetting and sensing are performed at only one end of the through-silicon-via. 
         [0015]    The method for testing a TSV according to another embodiment of the present invention comprises the steps of: charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The objectives and advantages of the present invention will become apparent upon reading the following description and upon referring to the accompanying drawings of which: 
           [0017]      FIG. 1  shows a cross-section view of a TSV; 
           [0018]      FIG. 2  shows the flowchart of a method for testing a TSV according to an embodiment of the present invention; 
           [0019]      FIG. 3  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to an embodiment of the present invention; 
           [0020]      FIG. 4  shows the flowchart of a method for testing a TSV according to another embodiment of the present invention; 
           [0021]      FIG. 5  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to another embodiment of the present invention; 
           [0022]      FIG. 6  shows the flowchart of a method for testing a TSV according to another embodiment of the present invention; 
           [0023]      FIG. 7  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to another embodiment of the present invention; 
           [0024]      FIG. 8  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to another embodiment of the present invention; 
           [0025]      FIG. 9  shows a TSV test architecture according to one embodiment of the present invention; 
           [0026]      FIG. 10  shows a TSV test circuit according to one embodiment of the present invention; 
           [0027]      FIG. 11  shows a TSV test circuit according to another embodiment of the present invention; 
           [0028]      FIG. 12  shows a TSV test circuit according to yet another embodiment of the present invention; 
           [0029]      FIG. 13  shows the flowchart of a method for testing a TSV according to another embodiment of the present invention; 
           [0030]      FIG. 14  shows a TSV test architecture according to one embodiment of the present invention; and 
           [0031]      FIG. 15  shows a TSV test architecture according to one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0032]      FIG. 1  shows a cross-section view of a TSV before wafer grinding/thinning on the backend. As shown in  FIG. 1 , the TSV  110  is formed in a substrate  150  and is electrically connected to an NMOS transistor  140  nearby. One end of the TSV  110  is connected to a metal layer  130 , and the other end of the TSV  110  is floating with a surrounding dielectric layer  120  to insulate the TSV  110  from the substrate  150 . It can be derived from  FIG. 1  that since the TSV  110  is surrounded by the dielectric layer  120  within the substrate  150 , the TSV  110  may exhibit a resistance property, a capacitance property or the combined property. It should be noted that a TSV cannot only applied to an NMOS transistor, it can be applied to a PMOS transistor or other active or passive components as well. 
         [0033]    One type of defect of a TSV is a break type defect. A break in the TSV may cause an open failure. With such a failure, the signal does not pass from one end of the TSV to the other end in a specific period of time. The effective capacitance measured from the top end of the TSV is reduced. Another type of defect of a TSV is an impurity defect. The TSV is not uniformly covered by the dielectric layer, which is caused by impurities or dust during the fabrication process. Such failure may lead to a low breakdown voltage or even a possible short between the TSV and the substrate. 
         [0034]    When a TSV exhibits a defect, such as the aforementioned defect cases, the property of the TSV is varied such that the TSV performs abnormally. Therefore, unlike the conventional test schemes wherein both ends of the TSV are accessed, in the embodiments of the present invention, the property variation of the TSV is measured by a sense amplification technique, such as, but not limited to, the sense amplification technique used in a DRAM. 
         [0035]      FIG. 2  shows the flowchart of a method for testing a TSV according to one embodiment of the present invention. In step  201 , a TSV under test is reset to a first state, and step  202  is executed. In this embodiment, if the voltage of the TSV is at a first voltage threshold, such as V dd , the TSV is in the first state. Therefore, in step  201 , the voltage of the TSV is charged to a high voltage level V dd . In step  202 , the state of the TSV is sensed after a period of time, and step  203  is executed. In step  203 , if the TSV enters a second state, the TSV is determined to be faulty. In this embodiment, if the voltage of the TSV is below a second voltage threshold V th     —     H , the TSV is in the second state. 
         [0036]      FIG. 3  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to the method shown in  FIG. 2 . As shown in  FIG. 3 , the transverse axis is the discharge time of the TSV, the longitudinal axis is the voltage of the TSV, and C L  is the minimum capacitance that provides a voltage greater than the threshold voltage V th     —     H  after a period of discharge time T L . If the voltage of the TSV is smaller than V th     —     H  after a period of discharge time T L , the TSV is determined to in the second state, and the TSV is determined to be faulty. In this way, those TSVs with capacitance smaller than C L  are determined to be faulty, wherein the value of C L  can be determined by adjusting the period of discharge time T L  and the threshold voltage V th     —     H . 
         [0037]    It should be noticed that the property of the TSV is not only determined by its capacitance characteristic, but can be determined by other characteristics as well, such as resistance characteristic. The method for testing a TSV of the present invention is not limited to the TSVs exhibiting capacitance characteristic, but can also be applied to those TSVs exhibiting other characteristics as well. 
         [0038]    In some embodiments of the present invention, the state of the TSV under test is determined differently from the method shown in  FIG. 2 . For instance, in some embodiments, if the voltage of the TSV is below a first voltage threshold, the TSV is in the first state, and if the voltage of the TSV is above a second voltage threshold, the TSV is in the second state, wherein the first voltage threshold is smaller than the second voltage threshold. In such cases, the voltage of the TSV is discharged to a low voltage level in step  201 , such as the ground level, and in step  202 , the TSV is charged and sensed after a period of time. In some embodiments, the state of the TSV is determined by its current level rather than its voltage level. 
         [0039]      FIG. 4  shows the flowchart of a method for testing a TSV according to another embodiment of the present invention. In step  401 , a TSV under test is reset to a first state, and step  402  is executed. In this embodiment, if the voltage of the TSV is at a first voltage threshold, such as V dd , the TSV is in the first state. Therefore, in step  401 , the voltage of the TSV is charged to a high voltage level V dd . In step  402 , the state of the TSV is sensed after a period of time, and step  403  is executed. In step  403 , if the TSV remains in the first state or enters a second state, the TSV is determined to be faulty. In this embodiment, if the voltage of the TSV is below the first voltage threshold V dd  and above a second voltage threshold V th     —     L , the TSV is in the second state. 
         [0040]      FIG. 5  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to the method shown in  FIG. 4 . As shown in  FIG. 5 , the transverse axis is the discharge time of the TSV, the longitudinal axis is the voltage of the TSV, and C H  is the maximum capacitance that provides a voltage lower than the threshold voltage V th     —     L  after a period of discharge time T H . If the voltage of the TSV is greater than V th     —     L  after a period of discharge time T H , the TSV is determined to be faulty. In this way, those TSVs with capacitance greater than C H  are determined to be faulty, and the value of C H  can be determined by adjusting the period of discharge time T H  and the threshold voltage V th     —     L . 
         [0041]    In some embodiments of the present invention, the state of the TSV under test is determined differently from the method shown in  FIG. 4 . For instance, in some embodiments, if the voltage of the TSV is below a first voltage threshold, the TSV is in the first state, and if the voltage of the TSV is above the first voltage threshold and below a second voltage threshold, the TSV is in the second state, wherein the first voltage threshold is smaller than the second voltage threshold. In such cases, the voltage of the TSV is discharged to a low voltage level in step  401 , such as the ground level, and in step  402 , the TSV is charged and sensed after a period of time. In some embodiments, the state of the TSV is determined by its current level other than its voltage level. 
         [0042]    The methods shown in  FIGS. 2 and 4  can be integrated into one method.  FIG. 6  shows the flowchart of a method for testing a TSV according to another embodiment of the present invention. In step  601 , a TSV under test reset to a first state, and step  602  is executed. In this embodiment, if the voltage of the TSV is at a first voltage threshold, such as V dd , the TSV is in the first state. In step  602 , the state of the TSV is sensed after a first period of time, and step  603  is executed. In step  603 , it is determined whether the TSV enters a second state. If not, step  604  is executed; otherwise, step  606  is executed. In step  604 , the state of the TSV is sensed after a second period of time, and step  605  is executed. In step  605 , it is determined whether the TSV remains in the first state or enters a third state. If not, step  607  is executed; otherwise, step  606  is executed. In step  606 , the TSV is determined to be faulty. In step  607 , the TSV is determined to be normal. In this embodiment, if the voltage of the TSV is below a second voltage threshold V th     —     H ′, the TSV is in the second state. If the voltage of the TSV is below the first voltage threshold V dd  and above a third voltage threshold V th     —     L ′, the TSV is in the third state, wherein the second voltage threshold is greater than or equal to the third voltage threshold. 
         [0043]      FIG. 7  shows a comparison of the threshold voltage of the TSV sensing and discharge time according to the method shown in  FIG. 6 . As shown in  FIG. 7 , the transverse axis is the discharge time of the TSV, the longitudinal axis is the voltage of the TSV, C L ′ is the minimum capacitance that provides a voltage greater than or equal to the second threshold voltage V th     —     H ′ after a first period of discharge time T L ′, C H ′ is the maximum capacitance that provides a voltage smaller than or equal to the third threshold voltage V th     —     L ′ after a second period of discharge time T H ′, and C′ is the capacitance of a normal TSV. If the voltage of the TSV is smaller than the first threshold voltage V th     —     H ′ after a first period of discharge time T L ′, or the voltage of the TSV is greater than the second threshold voltage V th     —     L ′ after a second period of discharge time T H ′, the TSV is determined to be faulty. In this way, those TSVs with capacitance smaller than C L ′ and those TSVs with capacitance greater than C H ′ are determined to be faulty, wherein the values of C L ′ and C H ′ can be determined by adjusting the period of discharge time T H ′ and T L ′ and the threshold voltage V th     —     L′ and V   th     —     H ′. 
         [0044]    In some embodiments of the present invention, the state of the TSV under test is determined differently from the method shown in  FIG. 6 . For instance, in some embodiments, if the voltage of the TSV is below a first voltage threshold, the TSV is in the first state, and if the voltage of the TSV is above the first voltage threshold and below a second voltage threshold, the TSV is in the second state, if the voltage of the TSV is above the second voltage threshold and below a third voltage threshold, the TSV is in the second state, wherein the first voltage threshold is smaller than the second voltage threshold, and the second voltage threshold is smaller than the third voltage threshold. In such cases, the voltage of the TSV is discharged to a low voltage level in step  601 , such as the ground level, in step  602 , the TSV is charged and sensed after a first period of time, and step  604 , the TSV is charged and sensed after a second period of time. In some embodiments, the state of the TSV is determined by its current level other than its voltage level. 
         [0045]    In the method shown in  FIG. 6 , the logic level of the TSV is determined by sense amplification technique, such as the sense amplification technique used in DRAM circuit. Therefore, two threshold voltages V th     —     H ′ and V th     —     L ′ are utilized, wherein the first voltage level V dd  is greater than the second voltage threshold V th     —     H ′, the second voltage threshold V th     —     H ′ is greater than the third voltage threshold V th     —     L ′, and the third voltage threshold V th     —     L ′ is greater than ground voltage. However, to reduce the area overhead, the determination of the logic level of the TSV can be performed by other techniques, such as utilizing a circuit comprising a cascade of inverters, a tri-state buffer and a pull-down circuit. In such circuit, the second voltage threshold V th     —     H ′ is equal to the third voltage threshold V th     —     L ′ as V th , and the first period of discharge time T L ′ is longer than the second period of discharge time T H ′.  FIG. 8  shows another comparison of the threshold voltage of the TSV sensing and discharge time according to the method shown in  FIG. 6  and the aforementioned circuit. 
         [0046]      FIG. 9  shows a TSV test architecture according to one embodiment of the present invention. As shown in  FIG. 9 , each TSV  110  at one side is connected to a test module  1110  and a normal function logic  1120  through a multiplexer  1130 , while each TSV  110  at the other side are connected to a test module  1111  with a storage circuit  1112  and the normal function logic  1120  through a multiplexer  1130 . During a test mode, a test controller  1160  receives a test commands, and switches each multiplexer  1130  to its corresponding test module  1110  or  1111 , and each TSV  110  is controlled by its corresponding test module  1110  or  1111 . A plurality of test signals are broadcasted from the test controller  1160  to each test module  1110 , and the test results are captured by a plurality of flip-flops  1140  or the storage circuit  1112 . All of the TSVs  110  can be tested in parallel. Preferably, a test result controller  1150  is utilized to collect the data from the flip-flops  1140  and the storage circuit  1112  and output the test output. 
         [0047]      FIG. 10  shows a TSV test circuit according to one embodiment of the present invention. As shown in  FIG. 10 , the TSV test circuit  1200  comprises a sense device  1210 , a discharge circuit  1220  and a charge circuit  1230 . The discharge circuit  1220  is configured to discharge the TSV  110 , and is controlled by the test commands. In some embodiments of the present invention, the discharge circuit  1220  may be used to discharge a plurality of TSVs  110 . The charge circuit  1230  is configured to charge the TSV  110 , and is controlled by the test commands. In some embodiments of the present invention, the charge circuit  1230  may be used to charge a plurality of TSVs  110 . The sense device  1210  is configured to sense the states of the TSV  110  and sends the sense result to a flip-flop  1140 . In some embodiments of the present invention, the sense device  1210  may be used to sense the states of a plurality of TSVs  110 . In some embodiments of the present invention, in order to minimize the area overhead, the charge circuit  1230  may comprise a tri-state buffer to act as a write driver, the discharge circuit  1220  may be implemented by an NMOS transistor, and the sense device  1210  may be implemented by a cascade of two inverters or a sense amplifier. 
         [0048]      FIG. 11  shows a TSV test circuit according to another embodiment of the present invention. As shown in  FIG. 11 , the TSV test circuit  1300  comprises a sense amplifier  1310 , a discharge circuit  1320  and a charge circuit  1330 . The discharge circuit  1320  is electrically coupled to the multiplexer  1130  and is configured to discharge the TSV  110 . The charge circuit  1330  electrically coupled to the discharge circuit  1320  and is configured to charge the TSV  110 . The sense amplifier  1310  is electrically coupled to the charge circuit  1330  and is configured to sense the states of the TSV  110 . 
         [0049]      FIG. 12  shows a TSV test circuit according to another embodiment of the present invention. As shown in  FIG. 12 , the TSV test circuit  1400  comprises a latch circuit  1410  and a discharge circuit  1420 . The discharge circuit  1420  is electrically coupled to the multiplexer  1130  and is configured to discharge the TSV  110 . The latch circuit  1410  is electrically coupled to the latch circuit  1410  and is configured to charge the TSV  110  and sense the states of the TSV  110 . 
         [0050]    Referring to  FIG. 9 , in some embodiments of the present invention, the TSV test procedure can be performed by the normal function logic  1120 , and thus the multiplexers  1110  and other additional test circuits may be omitted. 
         [0051]      FIG. 13  shows the flowchart of a method for testing a TSV according to another embodiment of the present invention. In this method, the capacitance characteristic of a TSV is tested. In step  1301 , a TSV under test is charged to a first predetermined voltage level, a capacitance device is charged to a second predetermined voltage level, and step  1302  is executed. In some embodiments of the present invention, the first predetermined voltage level is higher than second predetermined voltage level. In step  1302 , the TSV is isolated for a fixed amount of time, and step  1303  is executed. In step  1303 , a charge-sharing is performed between the TSV and the capacitance device, and step  1304  is executed. In step  1304 , a sensing amplification operation is preformed to compare the voltage level of the TSV with a first reference voltage, and step  1305  is executed. In step  1305 , another sensing amplification operation is preformed to compare the voltage level of the TSV with a second reference voltage, and step  1306  is executed. In step  1306 , the voltage level of the TSV is checked. If the voltage level of the TSV is lower than the first reference voltage and higher than the second reference voltage, step  1307  is executed; otherwise, step  1308  is executed. In step  1307 , the TSV is determined to be not faulty. In step  1308 , the TSV is determined to be faulty. 
         [0052]      FIG. 14  shows a TSV test architecture  1400  according to another embodiment of the present invention. As shown in  FIG. 14 , one end of each TSV  1402  is connected to the positive input terminal of a sensing device  1410 , which is a sense amplifier, through a switch device  1406 , and the other end of each TSV  1402  is floated. Similarly, one end of each TSV  1404  is connected to the negative input terminal of the sensing device  1410  through a switch device  1408 , and the other end of each TSV  1404  is floated. A charge circuit  1412 , which is a write buffer, is configured to charge the TSVs  1402  through a switch device  1414 , and charge the TSVs  1404  through a switch device  1416 . In addition, each switch device  1406  is connected to another charge circuit  1418  through a switch device  1420 , and each switch device  1408  is connected to the charge circuit  1418  through a switch device  1422 . 
         [0053]      FIG. 15  shows another view of the TSV test architecture  1400 . As shown in  FIG. 15 , the TSVs  1402  are shown on the left side of the sensing device  1410 , and the TSVs  1404  are shown on the right side of the sensing device  1410 . In addition, there is a capacitance device C L1  connected to the positive input terminal of a sensing device  1410 , and there is another capacitance device C L2  connected to the negative input terminal of a sensing device  1410 . 
         [0054]    The following illustrates applying the method shown in  FIG. 13  to the TSV test architecture  1400 , wherein the TSV  1402  indicated by the arrow A 1  is being tested. In step  1301 , both the switch device  1406  connected to the TSV under test  1402  and the switch device  1414  are turned on. Accordingly, the charge circuit  1412  charges the TSV under test  1402  to the first predetermined voltage level, V dd . Next, the switch device  1406  connected to the TSV under test  1402  and the switch device  1414  are turned off. The switch device  1420  is turned on. The charge circuit  1418  then charges the capacitance device C L1  to the second predetermined voltage level, V load . 
         [0055]    In step  1302 , the TSV under test  1402  is isolated for a fixed amount of time such that the voltage level of the TSV under test  1402  is stabilized. In step  1303 , the switch device  1406  connected to the TSV under test  1402  is turned on, and the other switch devices  1406  and the switch devices  1414  and  1420  are turned off. Accordingly, a charge sharing procedure is performed between the TSV under test  1402  and the capacitance device C L1 . In step  1304 , a sensing amplification operation is performed on the TSV under test  1402  and a TSV  1404  or the capacitance device C L2 , wherein either the TSV  1404  or the capacitance device C L2  is charged to the first reference voltage. Accordingly, whether the voltage level of the TSV under test  1402  is lower than the first reference voltage is determined. In step  1305 , another sensing amplification operation is performed on the TSV under test  1402  and a TSV  1404  or the capacitance device C L2 , wherein either the TSV  1404  or the capacitance device C L2  is charged to the second reference voltage. Accordingly, whether the voltage level of the TSV under test  1402  is lower than the second reference voltage is determined. In step  1306 , the voltage level of the TSV under test  1402  is checked. If the voltage level of the TSV under test  1402  is lower than the first reference voltage and higher than the second reference voltage, i.e., if the capacitance characteristic of the TSV under test  1402  is deemed normal, then the TSV under test  1402  is determined to be not faulty. 
         [0056]    In some embodiments of the present invention, the capacitance devices C L1  and C L2  are TSVs. In some embodiments of the present invention, the capacitance devices C L1  and C L2  are the parasitic capacitance of the TSV test architecture  1400 . 
         [0057]    In conclusion, the method for testing a TSV of the present invention exploits the property of TSVs such that the test process can be performed on individual TSVs. Accordingly, the method for testing a TSV of the present invention can be performed on various kinds of TSVs, especially those formed by via-first process that is difficult to test for conventional method. In addition, since the method for testing a TSV of the present invention can be performed by the test circuit, which is on the same IC as that on which the TSV under test is disposed, the method can be performed before the IC on which the TSV is disposed is bonded to another IC. Therefore, the method for testing a TSV of the present invention can be performed before the bonding process, and thus can increase yield significantly and reduce the implementation cost. 
         [0058]    The above-described embodiments of the present invention are intended to be illustrative only. Those skilled in the art may devise numerous alternative embodiments without departing from the scope of the following claims.