Abstract:
A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures as the damage profile can be more easily localized to the depth of the thin metal oxide film.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention generally relates to the wet chemical etching of metal oxides. More particularly, it relates to the patterning of chemically inert and/or high temperature-treated metal oxides for applications such as high-k gate dielectrics in memory and logic devices, tunnel oxides, passivation layers, nano-devices, thin film capacitors, etc.  
         BACKGROUND OF THE INVENTION  
         [0002]    Metal oxides of Zr, Hf, La, Y and Al are being investigated as possible candidates to replace SiO 2  as a gate dielectric in complementary metal-oxide-semiconductor (CMOS) devices, in part because the higher dielectric constant, k, of these oxides allows the dielectric thickness to be scaled to below 1 nm EOT (equivalent oxide thickness). With current process practices, the gate dielectric is deposited at an early stage of processing and is subsequently subjected to thermal treatments at temperatures of 1000° C. or higher, depending on application and device type.  
           [0003]    Metal oxides such as Al 2 O 3  can undergo phase modifications during these thermal treatments that render the material impossible to etch in commonly used wet chemical etching mixtures such as aqueous HF (hydrofluoric acid). However, these metal oxides must be etched if electrical contact is to be made to underlying layers, for example to the source and drain areas of field effect transistor (FET) devices in CMOS circuits. While reactive ion etching (RIE) is a possible alternative to wet chemical etching, it is not preferred in these critical processes due to the danger of overetching into underlying device layers.  
           [0004]    Thicker (10-100 nm) high-k metal oxides are also being investigated as possible candidates to replace SiO 2  as the capacitor dielectric in thin film metal-insulator-metal capacitors (MIMCAPs) to provide a higher capacitance density. In this case, contact openings to the bottom capacitor electrode are typically formed by etching the metal oxide using the pattern of the top electrode as a mask. Again, wet patterning would often be preferred to RIE due to concerns about overetching into the bottom electrode and redeposition of sputtered bottom electrode material (which may cause shorts between the bottom and top electrodes).  
           [0005]    Ion implantation has long been known to increase the etch rate of SiO 2 . This effect is discussed in a recent paper by L. Liu et al (“HF wet etching of oxide after ion implantation,” Proceedings 1996 IEEE Hong Kong Electron Devices Meeting, Jun. 29, 1996), and has provided the basis for several patents on patterning SiO 2  (see for example, K. C. Jain et al., U.S. Pat. No. 4,652,334 issued Mar. 24, 1987 and entitled “Method for Patterning Silicon Dioxide with High Resolution in Three Dimensions”). However, this effect has not been previously exploited for the etching and patterning of chemically inert metal oxide films, a particularly important case, since so many of these films are impossible to etch without ion-induced damage.  
           [0006]    It would thus be highly desirable to provide a system and method for patterning chemically inert and/or high temperature-treated metal oxide films in which selected areas of such films could be made to become susceptible to the conventional wet etch solutions.  
         SUMMARY OF THE INVENTION  
         [0007]    It is an object of the present invention to provide a semiconductor device fabrication system and method for converting high temperature treated high-k metal oxides (gate dielectrics) into etchable materials.  
           [0008]    It is a further object of the present invention to provide a system and method for patterning chemically inert and/or high temperature-treated metal oxide films in which selected areas of such films are converted into materials that can be etched with conventional wet etch solutions.  
           [0009]    The present invention provides a semiconductor device fabrication system and method for patterning chemically inert and/or high temperature treated metal oxide films that would normally be impervious to conventional wet etch solutions such as aqueous HF. Etching is performed in these same conventional wet etch solutions after the metal oxide regions to be etched are modified, i.e., damaged, by ion (or other charged particle) bombardment processes such as ion implantation or plasma treatment, and/or a short Reactive Ion Etching (RIE) process. If preferred, damage may also be effected by energetic neutral particles, for example, by x-rays, or by photons from pulsed or continuous ultraviolet lasers.  
           [0010]    According to the principles of the invention, there is provided a semiconductor device fabrication system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an ion bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. The ion bombardment processes used to effect damage-induced wet etching in metal oxide films include low energy ion bombardment, such as that provided by a plasma treatment, and ion implantation (I/I) techniques such as those conventionally used in the semiconductor industry for semiconductor doping. Advancement over the prior art is in the new application of the “I/I damage plus wet etch” technique to metal oxides (including metal oxides not previously etchable by wet methods), as well as in the extension of I/I damage methods to include lower energy, plasma-based ion bombardment. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures (since the damage profile can be more easily localized to the depth of the thin metal oxide film).  
           [0011]    Advantageously, the system and methods of the present invention may be used to pattern metal oxide hard mask layers which may or may not remain in the final semiconductor device/structure. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description of the invention, as illustrated in the accompanying drawings, in which:  
         [0013]    FIGS.  1 A- 1 D illustrate the steps of the basic method of the invention;  
         [0014]    FIGS.  2 A- 2 E illustrate the steps of a variation of the basic method of the invention;  
         [0015]    FIGS.  3 A- 3 B illustrate the method of the present invention applied to patterning a thin metal oxide gate dielectric layer in a field effect transistor;  
         [0016]    FIGS.  4 A- 4 B illustrate the method of the present invention applied to patterning a thicker metal oxide used as a capacitor dielectric.  
         [0017]    FIGS.  5 - 7  illustrate how annealed metal oxide films are modified by ion implantation in conventional semiconductor materials as demonstrated by results of electrochemical open circuit potential (OCP) measurements.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]    FIGS.  1 A- 1 D illustrate the basic steps of the inventive method. In FIG. 1A, a metal oxide layer  10  on a semiconductor substrate  20  is exposed to ion (or other energetic particle) bombardment  30  through patterned mask  40  to create damaged metal oxide regions  50 , as shown in FIG. 1B. Damaged metal oxide regions  50  are then removed by a selective wet etch to produce the structure of FIG. 1C with patterned metal oxide  10 ′. If desired, patterned mask  40  may be removed before or after removal of damaged metal oxide regions  50  to produce the structure of FIG. 1D.  
         [0019]    It should be noted that the step of forming patterned mask layer  40  may be omitted from the steps of FIGS.  1 A- 1 D if blanket ion (or other energetic particle) bombardment  30  is replaced by a maskless direct write bombardment process which applies the bombardment to selected film regions only. It should also be noted that the step of forming patterned mask layer  40  may be omitted altogether if a blanket metal oxide layer is to be etched. Alternatively, the step of forming patterned mask layer  40  may be performed after blanket damage to the metal oxide layer, if, for example, the damage process produces a desirable effect on the metal oxide that is to remain.  
         [0020]    FIGS.  2 A- 2 E illustrate a variation of method FIGS.  1 A- 1 D. This variation can be used when the depth of the damaged region is thin compared to the thickness of the metal oxide layer being etched. In FIG. 2A, thick metal oxide layer  60  on substrate  20  is exposed to ion (or other energetic particle) bombardment  70  through patterned mask  40 . Damaged metal oxide regions  80  shown in FIG. 2B are removed by a selective wet etch to produce the structure of FIG. 2C. The bombardment/wet etch cycle of FIGS.  2 A- 2 C can be repeated until the desired thinning is achieved, as shown in FIG. 2D. Alternatively, the bombardment/etch cycles can be repeated until entire thickness of the film is etched, as shown in FIG. 2E. Following these steps, patterned mask  40  may be optionally removed.  
         [0021]    If desired, patterns of different etch depths may be formed in the same metal oxide film by using different bombardment conditions (or different numbers of bombardment cycles) for different regions of the film. This might be useful, for example, in making a two-tone phase shift mask for optical lithography applications.  
         [0022]    [0022]FIGS. 3 and 4 show of two examples of electrical devices in which the methods of this invention may be used to pattern a metal oxide layer. FIGS.  3 A- 3 B show FET  90  before (FIG. 3A) and after (FIG. 3B) patterning of metal oxide gate dielectric layer  100 . FET  90  comprises substrate  110 , shallow trench isolation regions  120 , source  150 , drain  160 , conductive gate  130 , and optional sidewall spacers  140 . Metal oxide gate dielectric layer  100  is patterned according to the steps of FIGS.  1 A- 1 C, where gate  130  functions as patterned mask layer  40 , and the ion implantation process used to implant source/drain regions  150 / 160  may also function as ion (or other energetic particle) bombardment  30 .  
         [0023]    FIGS.  4 A- 4 B show a thin film capacitor  200  on substrate  210  before and after patterning of metal oxide layer  220 . Capacitor  200  comprises bottom electrode  230 , metal oxide dielectric layer  220 , top electrode  230 , and optional additional mask layer  240 . Metal oxide gate dielectric layer  220  is patterned according to the steps of FIGS.  1 A- 1 C, where patterned mask layer  40  is replaced by top electrode  230  and optional additional mask layer  240 .  
         [0024]    The ion (or other energetic particle) bombardment of the inventive method may be applied by processes such as ion implantation, plasma treatment, and/or electron beam irradiation. This bombardment does not etch the metal oxide, but rather introduces damage which makes the material susceptible to etching by conventional wet etch solutions. The ion-induced damage may result from any of the following mechanisms: amorphization, other structural changes, insertion of new atoms in the lattice, creation of vacancies, bond breaking/rearrangement, etc. Is should be noted that the bombarding ions from ion implantation processes do not necessarily embed themselves in the metal oxide layer; the damage from ion implantation can also be effected by ions passing through the metal oxide film into the layer below. It should also be noted that the ion (or other energetic particle) bombardment used to make the metal oxide film susceptible to wet etching may also improve the properties of the metal oxide film. For example, exposure to nitrogen-containing plasma or low energy nitrogen ion implantation may damage the film but also provide a beneficial nitridation.  
         [0025]    It should also be noted that the damage induced by ion bombardment can often be reversed by annealing. In these cases, “rework” is possible if the damage was inadvertently applied to the wrong regions of the metal oxide film. Thus, the metal oxide may be subsequently annealed to “erase” the damage (prior to ion bombardment re-expose). Annealing may also be desirable after the damaged metal oxide regions have been wet etched, to repair substrate damage.  
         [0026]    In the preferred embodiment, bombardment conditions are tailored to the thickness and quality of the metal oxide layer, and on the sensitivity of the mask and substrate to collateral damage from the bombardment. Ion implantation species may be selected from any of the elements or molecular ions (e.g., Si, Ge, B, P, Sb, As, O, N, Ar, BF3, etc.). Implantation energies may range from 1 to 100 keV, with a preferred range of 2 keV to 10 keV for films less than 5 nm thick. Implantation doses may range from 1×10 14 /cm 2  to 1×10 6 /cm 2 , with a preferred range of 5×10 14 /cm 2  to 2×10 15 /cm 2  for films less than 5 nm thick. Thicker films require higher energies than the 5 keV-10 keV cited as preferable if multiple bombardment/etch cycles are to be avoided.  
         [0027]    Plasma treatments may be performed in a conventional RIE tool, high density plasma tool, etc., with or without an additional bias voltage applied to the substrate.  
         [0028]    It should be understood that plasma ashers and conventional plasma etching tools may also be used if the tool geometry and plasma parameters (power, working gas pressure, etc.) allow a sufficient self-bias to develop. Ion bombardment may also be performed by ion beam irradiation. Ion or plasma species may be formed by rf, dc, microwave, etc., excitation of working gases including but not limited to: the noble gases, such as He, Ne, Ar, Kr, Xe; diatomic gases such as O 2 , N 2 , H 2 , F 2 , Cl 2 , Br 2 ; triatomic gases such as CO 2 , N 2 O, H 2 O; halogen containing gases such as CF 4 , C x F y , C x Cl y , C x F y Cl z ; hydrogen-containing gases such as C x H y , C x H y X z  and HX where X=halogen, C x H y Si z , where x,y and z are integers ranging from 1 through 10, and, mixtures including any one of these gases. Preferred working gases include O 2  and Ar, since plasma species from these gases do not chemically etch Si (the typical substrate). As would be within the purview of skilled artisans, preferred ion energies and doses depend on the thickness and quality of the metal oxide layer, and on the sensitivity of the mask and substrate to collateral damage from the bombardment. For example, ion energies of plasma species are typically between 50 eV and 1 keV, and ion energies of ion beam species are typically between 0.5 keV and 3 keV. Plasma treatments would thus be preferred when the desired ion energy is lower than values that can be reliably and efficiently provided by ion implantation tools.  
         [0029]    Wet etch solutions to remove the damaged metal oxide regions may be selected from the group of chemistries including aqueous HF, aqueous buffered HF, and solutions containing at least one of the following components: inorganic bases such as sodium hydroxide, potassium hydroxide, and ammonium hydroxide; organic bases such as tetramethyl ammonium hydroxide (TMAH) and choline (2-hydroxyethyltrimethylammonium hydroxide); hydrogen peroxide; organic acids such as acetic acid; HF, sulfuric acid, nitric acid, other mineral acids; ammonium fluoride, other buffering salts; etc.  
         [0030]    It should be noted that the metal oxides to which the system and methods of this invention pertain include not only the pure metal oxides M-O, but also materials comprising at least 95 wt.-% of the following materials or mixtures thereof: metal oxides M-O, metal silicates M-Si—O, metal aluminates M-Al—O, metal oxynitrides M-O—N, metal oxysiliconnitrides M-Si—N—O, and metal oxyaluminitrides M-Al—N—O, where the metal M is selected from the group including Al, Sb, As, Ba, Bi, Ca, Cd, Ce, Cs, Cr, Co, Cu, Dy, Er, Eu, Gd, Ga, Hf, In, Ir, K, La, Pb, Pd, Pr, Pt, Li, Mg, Mn, Hg, Mo, Na, Nd, Ni, Rb, Sc, Se, Sm, Ta, Te, Th, Ti, Tl, Tm, Sn, W, V, Yb, Y, Zn, and Zr, mixtures of metals in this group; and, alloys of metals in this group. Preferable materials include: HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , Y 2 O 3 , and oxynitrides and silicates thereof.  
         [0031]    FIGS.  5 - 7  provide data on the etching of metal oxide films subjected to various annealing and ion implantation treatments. Measurements are results of Electrochemical Depth Profiling-Open Circuit Potential (EDP-OCP) measurements performed in the manner such as described in the reference to H. F. Okom-Schmidt et al., in “The Physics and Chemistry of SiO 2  and the Si—SiO 2  Interface—4, H. Z. Massoud et al., Edt., Proc. Vol. 2000-2, The Electrochemical Society, Pennington, N.J., 2000, or, the reference H. F. Okom-Schmidt, IBM J. Research Develop. 43 351 (1999), the whole contents and disclosure of each of which is incorporated by reference as if fully set forth herein. In the plots of FIGS.  5 - 7 , the Y-axis represents the open circuit potential, Voc (measured in volts) with respect to a standard Ag/AgCl electrode according to the OCP technique versus time in seconds, t(s), on the X-axis.  
         [0032]    The following examples reveal the details of the invention for the exemplary cases of: (1) a Al 2 O 3  metal oxide 8 nm-10 nm thick, bombardment by ion implantation, and wet etching in 100:1 HF; and, (2) a HfO 2  metal oxide 2 nm-5 nm thick, bombarded by an O 2  RIE plasma, with wet etching in 10:1 HF or 50:1 buffered oxide etch (an aqueous mixture of HF and NH 4 F).  
       EXAMPLE 1  
       [0033]    In an example embodiment, 8 to 10 nm-thick films of Al 2 O 3  were deposited on Si wafers coated with an 0.8 nm-thick layer of thermally grown nitrided SiO 2  (denoted as SiO x N y  or SiON). After being subjected to anneals in N 2  at different temperatures, the Al 2 O 3  was tested for the ability to be etched in aqueous HF solutions by OCP. FIG. 5 is a plot  300  of OCP data obtained for 8 nm-thick Al 2 O 3  films in  200 : 1  dilute HF (about 0.25 wt.-% HF). OCP trace  305  is for an unannealed film, and traces  310 ,  320 ,  330 , and  340  are for films annealed at temperatures of 550° C., 650° C.,  750 ° C., and 850° C., respectively. The peaks in traces  305  to  340  indicate the time at which the Al 2 O 3 /SiO x N y  interface is reached, i.e., the time to etch through the Al 2 O 3 . These Al 2 O 3 /SiO x N y  interface peaks move to longer etch times as the anneal temperature increases, indicating that the Al 2 O 3  becomes harder to etch. Etch rates are determined from the initial film thickness and the time it takes for the interface peak to appear. For example, the as-deposited Al 2 O 3  film has an etch rate of 92 A/min (8 nm/25 sec) and the film annealed at 850° C. has an etch rate of 98 A/min (8 nm/49 sec).  
         [0034]    The plot  400  illustrated in FIG. 6 shows the effect of higher anneal temperatures on the etchability of Al 2 O 3  films in 100:1 dilute HF (about 0.5 wt-% HF). OCP traces  345 ,  350  and  360  are for films annealed at temperatures of 850° C., 950° C. and 1000° C., respectively. Trace  345  for the film annealed at 850° C. shows that the Al 2 O 3 /SiO x N y  interface is reached after about 30 sec, indicated as time  365 . However films annealed at 950° C. and 1000° C. become very hard to etch, as indicated by the absence of the characteristic interface peak even after 700 sec of etching, as well as by the lack of an abrupt flattening of the potential to a flat, stable value after a reasonable amount of time. The presence of residual Al 2 O 3  was also indicated by the fact that the sample surface did not become hydrophobic (i.e., show dewetting behavior).  
         [0035]    The plot  600  illustrated in FIG. 7 shows that 10 nm-thick Al 2 O 3  films annealed at 950-1050° C. become etchable in 100:1 dilute HF after exposure to an ion implant treatment. OCP traces  385 ,  390 , and  395  are for films annealed at temperatures of 950° C., 1000° C. and 1050° C., respectively. All three traces show clear endpoints for Al 2 O 3 +SiO x N y  removal, indicated as time  375 , at which point the potential levels off to a relatively flat and stable value. The complete removal of Al 2 O 3  was also indicated by the hydrophobic sample surface, as well as by x-ray photoelectron spectroscopy (XPS), low-energy electron microscopy (LEEM), and atomic force microscopy (AFM) measurements which showed no surface aluminum. The absence of the Al 2 O 3 /SiO x N y  interface peak seen in the FIG. 5 OCP data is attributed to ion-induced damage and/or mixing effects.  
       EXAMPLE 2  
       [0036]    In a second example, 2 nm-5 nm thick HfO 2  films deposited by atomic layer chemical vapor deposition (ALCVD) on Si substrates are subsequently annealed in N 2  at 700° C. for 30 sec. Etch times (as indicated by time to “dewet” or become hydrophobic) were examined as a function of HfO 2  film thickness, the power and time of oxygen plasma treatments, post-oxygen-plasma anneals, and wet etch chemistry.  
         [0037]    Table I compares the dewet times of oxygen-plasma-treated HfO 2  films in 50:1 buffered HF (“buffered oxide etch” or BOE) and 10:1 aqueous HF. The HfO 2  films were 2.9 nm thick in the example. The plasma treatments were performed in a Plasmalab μP-RIE 80 system with 24-cm-diam water-cooled electrode driven by a 13.56 MHz power supply, with the samples placed on a Si susceptor plate separated from the cathode by a second susceptor plate of graphite. The O 2  pressure was 20 mTorr, the flow was 20 sccm (standard cubic centimeters per minute), and the treatment duration was 1 minute. Three powers were compared: 0 W (control sample), 150 W (with a self-bias voltage of −280 Vdc), and 300 W (with a self-bias voltage of −390 Vdc).  
                                     TABLE I                           Dewet times of 2.9 nm thick HfO 2  films after various O 2  plasma       treatments.                Etchant/O 2  Power (W)   0   150   300                       BOE 50:1   &gt;21 min   20-25 sec   20-25 sec           HF 10:1   &gt;10 min   4 sec   4 sec                      
 
         [0038]    It is clear that the plasma treatments are very effective in transforming the HfO 2  into an etchable material, and that etching is fast in both BOE and HF. BOE, unlike aqueous HF, is compatible with many photoresists and for this reason may be preferred over aqueous HF as the wet etchant.  
         [0039]    Table II provides data demonstrating how dewet times for a given plasma exposure vary with HfO 2  film thickness. The data indicates that the damage provided by 150 W treatment is extremely shallow; it is enough to damage 2.9 nm of HfO 2 , but not the entire thickness of 4.6 nm HfO 2  film. It was also found that an 8.7 nm thick layer of SiO 2  layer prevented damage to a 2.2 nm thick HfO 2  underlayer from a 5 min 150 W O 2  plasma treatment, again indicating that plasma damage is extremely shallow. These results suggest that low energy plasma ions may be preferred over the higher energy implanted ions in the case of damage-sensitive substrates.  
                                 TABLE II                           Effect of HfO 2  thickness on dewet times in 10:1 aqueous HF after O 2         plasma treatments of 1 min duration.            HfO 2  thickness/O 2  Power (W)   0   150   300               2.9 nm   &gt;10 min   4 sec   4 sec       4.6 nm   &gt;10 min   &gt;11.5 min   45 sec-4.25 min                  
 
         [0040]    Table III provides data demonstrating how damage induced in 2.9 nm thick HfO 2  films by O 2  plasma treatments may be at least partially annealed out by various thermal treatments in a rapid thermal annealer. Annealing increases the dewet times, and higher power plasma treatments generate more damage, as indicated by the shorter dewet times for a given annealing condition.  
                                 TABLE III                           Effect of post-plasma-treatment anneals on dewet times of 2.9 nm-       thick HfO 2  films in aqueous 10:1 HF.                Anneal/O 2  Power (W)   150   300                       No anneal   4 sec   4 sec           400° C./5 min N 2      15-20 sec   5 sec           700° C./1 min N 2     4-11.5 min   10-15 sec                      
 
         [0041]    While several embodiments of the invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various further modifications are possible without departing from the scope of the invention. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The examples given are intended only to be illustrative rather than exclusive.