Abstract:
A method for displaying grey-scale images at a desired grey scale resolution on a display having a matrix of pixels, comprises the steps of: defining a control matrix having a size smaller than the entire display and equal to the desired grey scale resolution of the display, each position in the control matrix having an address assigned such that unintended artifacts in the display are controlled; horizontally and vertically mapping the control matrix into the display such that each pixel in the matrix of pixels in the display corresponds to an address in a control matrix mapped into the display; comparing control matrix address of each pixel in a frame of an image to be displayed on the display to a range of address values and turning that pixel on if the grey scale value of that pixel is within the range of address values, the range of address values arranged in a circular queue and being equal to the grey scale value of that pixel; and shifting the range of address values in the circular queue for successive frame by an amount equal to the grey scale value of the pixel to be displayed.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to computer displays and to liquid crystal computer displays. More particularly, the present invention relates to methods for providing grey scale up to the visible limit for display on liquid crystal displays. 
     2. The Prior Art 
     Numerous methods are known for producing grey-scale images on digital (i.e., on/off) displays with characteristics similar to super-twisted nematic (STN) liquid crystal displays (LCD). Modulating individual pixels by employing frame-rate-control (FRC) algorithms over time and by spatial dithering appear to be the preferred methods for realizing gray scale on displays with STN LCD and similar characteristics. 
     Prior-art methods producing such grey-scale images do not claim gray scale approaching the visible limit, but are usually limited to 16 gray shades when using FRC alone and to 64 gray shades when FRC and dithering are used in combination. The details of particular methods are not readily available in the literature. 
     These prior-art methods all suffer from one or more shortcomings. The disadvantages of these previous methods may be classified into three main categories: undesirable visual motion artifacts, undesirable visual static artifacts, and reduced gray shade fidelity. 
     Undesirable visual motion artifacts may be perceived as &#34;shimmer,&#34; &#34;crawl,&#34; &#34;ripple,&#34; or &#34;waterfalling.&#34; The terms used to describe these artifacts are descriptive of subjective perception and are not readily quantifiable. All observed implementations of previous methods (particularly FRC-based processes) have specific gray shade values (&#34;sensitive gray shades&#34;) for which one of these artifacts is readily perceivable. 
     These sensitive gray shades will change from one specific STN LCD panel model to another as a result of differences in panel physical characteristics. Because of this variability among different displays, systems employing these displays have to be tuned to achieve the best result given a combination of the gray scale method and the physical display employed. This normally involves changing the specific FRC implementation and may optionally involve remapping from a sensitive gray shade to an adjacent one that is insensitive, i.e., a gray shade which does not have an undesirable visual motion artifact. Remapping sensitive gray shades to avoid undesirable visual motion artifacts also reduces gray shade fidelity and resolution. 
     FRC-based motion artifacts are caused by the cyclic nature of the FRC as applied over a small physical area. For a given frame, the FRC is used to assign a value to a pixel within a grid or matrix. This value is compared to the gray shade to determine if the pixel should be &#34;on&#34; or &#34;off.&#34; If neighboring pixels cycle harmonically in time with respect to each other, the human eye may perceive motion where none is intended. Virtually all visual motion artifacts are undesirable. 
     Undesirable static artifacts may be the result of sacrificing spatial resolution to achieve increased perceived gray shades by employing a spatial dithering process. The most noticeable static artifact in spatially-dithered grey scale images is &#34;graininess.&#34; If a source gray shade cannot be directly represented, the display system may map the gray shade alternately into the two closest gray shades by dithering. The gritty appearance is caused by high frequency transitions between physically adjacent pixels at a physical resolution the eye can distinguish. 
     Reduced gray shade fidelity can be manifested as &#34;contouring&#34;, also known as Mach banding or &#34;cartooning.&#34; For example, contouring causes a smoothly shaded sphere to appear as a series of concentric rings each of a single gray shade. In cartooning, an image has a narrow enough gray shade or color range that images appear to have been drawn with crayons for use in cartoons. Contouring and cartooning are all apparent in processes having a capacity of fewer gray shades than the perceivable visible limit, which is 256 grey shades. 
     BRIEF DESCRIPTION OF THE INVENTION 
     The purpose of the present invention is to provide the capability to display gray scale to the limit of human perception (256 shades) using displays having characteristics of or ones similar to super-twisted nematic (STN) liquid crystal displays (LCD). The present invention may be utilized for monochromatic or color displays. 
     A method is provided according to the present invention for displaying gray scale up to the visible limit (two hundred and fifty-six shades) for displays such as, but not limited to, dual-scan super twisted nematic (DSTN) liquid crystal displays (LCD). The method of the present invention employs a large static matrix of values in concert with a circular queue consumption to distribute energy evenly in both space and time to achieve a large range of gray shades in digital displays with slow rates of response. The grey scale resolution of the method of the present invention depends upon the size of the matrix employed. 
     A first part of the method addresses minimizing visual motion artifacts and equal distribution of energy over the viewing surface. This is accomplished by assigning addresses to a matrix of pixels. According to the first part of the method of the present invention, a matrix is defined wherein each position in the matrix is defined by a different number or &#34;address&#34;. For example, each position in a 16×16 matrix is defined by a different numbered address from 0 to 255. This matrix is repeatedly mapped into the entire pixel matrix of the display in both the horizontal and vertical directions. 
     Static visual artifacts may be minimized by rotating the matrix columns at the beginning of each horizontally adjacent matrix. For example, in 16×16 matrix, the first matrix in a row includes in order columns 0 through 15. In an embodiment where the column offset is 4, the second matrix to its right begins with column 3 and ends with column 2. The third matrix to its right begins with column 7 and ends with column 6. 
     The second part of the process primarily addresses the consumption or use of the pixels within the matrix to realize smooth shading of an individual pixel over time. This is accomplished by using a circular queue. The circular queue causes pixel consumption in sequential matrix address order, and provides that within any given number of frames that pixels are used with an even distribution. Each color primary has an independent circular queue per shade. Circular queues for each shade of each color primary may be in arbitrary alignment with respect to each other in order to achieve optimal visual results. 
     For example, the grey-scale value of a single pixel in a given display image (frame) is compared with the matrix address corresponding to the position of that pixel in the display. The gray-scale value of the pixel and the frame number within a sequence of frames is used to select a range of matrix addresses from a circular queue (the &#34;ON&#34; range). The address of the current pixel is compared to the &#34;ON&#34; range. If the current pixel&#39;s value is within that range, then it is switched &#34;ON&#34; for that frame. The default state for failing this test is &#34;OFF.&#34; 
     This method is duplicated for each color primary. The number of frames in a sequence is equal to the number of matrix addresses. 
     The present invention provides gray shade resolution at the visible limit and therefore does not introduce gray shade infidelities. Dithering is not used, and thus its attendant artifacts do not occur. Motion artifacts are avoided in the present invention by assigning a static value to each pixel within a matrix and by making the matrix physically large enough so that the eye has difficulty perceiving motion. The decision to turn a pixel &#34;on&#34; or &#34;off&#34; is made by comparing the pixel value against a range of values (the &#34;on range&#34;). If the pixel value is within the on range, the pixel is turned &#34;on.&#34; The on range is determined for each gray shade and each frame. Avoidance of motion artifacts is also assisted by the large cycle time of the process. For comparison, FRC-based processes typically run over a sixteen frame cycle, while the method of the present invention uses a two hundred fifty-six frame cycle, thus spreading low frequency events over a long sample interval with a high sample rate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     FIGS. 1a and 1b are examples of two matrices actually used with an embodiment of the present invention. 
     FIG. 2 is a flow diagram illustrating the method for consumption of pixels according to a presently preferred embodiment of the present invention 
     FIG. 3 is a block diagram of a hardware system which may be used to implement the present invention. 
     FIG. 4 is a more detailed block diagram of the pixel matrix address generator of FIG. 3. 
     FIG. 5 is a more detailed block diagram of the matrix addresses block of FIG. 4. 
     FIG. 6 is a more detailed block diagram of the pixel column and pixel row address generator of FIG. 4. 
     FIG. 7 is a more detailed block diagram of the circular queue of FIG. 3. 
     FIG. 8 is a more detailed block diagram of the G,FG unit of FIG. 7. 
     FIG. 9 is a more detailed block diagram of the Rmin Rmax unit of FIG. 7. 
     FIG. 10 is a more detailed block diagram of the data compare unit of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
     For the purposes of the disclosure and claims herein, the term &#34;digital display&#34; refers to a display wherein each pixel may be either &#34;ON&#34; or &#34;OFF&#34;. Examples of such displays include, but are not limited to, dual-scan super twisted nematic (DSTN) liquid crystal displays (LCD) and other displays having similar characteristics. 
     It is not clear that prior-art grey scale display methods utilized the physical characteristic of STN LCD type displays in an advantageous manner. It appears that the prior-art methods used assumed the display&#39;s physical characteristics to be undesirable. The method of the present invention seeks to take advantage of the relatively slow rate of change of STN LCD type displays as a means for assisting in the even distribution of energy for a given gray shade over a large area. 
     The method of the present invention employs a matrix of values and circular queue method of consuming those values. Similar results are believed to be achievable with matrix assignments of values different from the illustrative ones disclosed herein. 
     According to the method of the present invention, both spatial and temporal aspects of the display technology are advantageously utilized to achieve a grey scale resolution which may be four times that of conventional prior art grey scale display systems. The total area of the display is divided into a plurality of matrices. In the illustrative embodiment disclosed herein, each matrix is a 16×16 pixel area of the display. In a method applied to color displays according to the present invention, a separate matrix is defined for each color component of each pixel in the display. According to another aspect of the method of the present invention, the matrix is repeated in the horizontal and vertical directions, but may be altered from repetition to repetition in order to minimize certain artifacts which might otherwise arise as a result of unintended periodicity. 
     A method is provided according to the present invention for displaying gray scale up to the visible limit (two hundred and fifty-six shades). The method of the present invention employs a large static matrix of values in concert with a circular queue consumption to distribute energy evenly in both space and time to achieve a large range of gray shades in digital displays with slow rates of response. The grey scale resolution of the method of the present invention depends upon the size of the matrix employed. 
     A first part of the method addresses minimizing visual motion artifacts and equal distribution of energy over the viewing surface. This is accomplished by assigning addresses to a matrix of pixels. According to the first part of the method of the present invention, a matrix is defined wherein each position in the matrix is defined by a different number or &#34;address&#34;. For example, each position in a 16×16 matrix is defined by a different numbered address from 0 to 255. This matrix is repeatedly mapped into the entire pixel matrix of the display in both the horizontal and vertical directions. Examples of two matrices which have been actually used with an embodiment of the present invention are presented in FIGS. 1a and 1b. 
     In order to avoid motion artifacts, it is preferable according to the present invention to employ several guidelines for assigning address numbers in the control matrix. These guidelines are not strict rules and may be violated in isolated instances without adversely affecting the performance of the present invention. The application of these guidelines may be seen by examining the adjacent values of the matrices of FIGS. 1a and 1b. 
     First, it is preferable to avoid placing two consecutive values next to each other in the horizontal, vertical or diagonal directions. The 8 pixels surrounding an assigned pixel value in the control matrix should not have an consecutive address number. A discreet incidental violation, like once out of a sequence may not cause a problem. 
     Second, placing consecutive number values on the same row, column, or diagonal should be avoided. For example, if the pixel in the upper left corner is assigned a value of 0, and then a pixel is skipped horizontally, the next pixel should not be assigned number 1. 
     Third, the distribution of the values in the matrix should be even from top to bottom and left to right. For example, if a 16×16 matrix is split vertically, where there are 128 values on the left half and 128 values on the right half, out of the 256 possible values (0-255), it is preferred on have approximately even distribution of values of 127 or less on both the right and left halves of the matrix. The same guideline is preferred for distribution of values between the top and bottom halves of the matrix. 
     Those of ordinary skill in the art will appreciate that these guidelines should be applied to adjacent pixels across horizontal and vertical matrix boundaries. 
     Because of the nature of the digital displays such as the STN LCD panel, they tend to exhibit cross talk. When a pixel is turned on or off, the signal sent to that pixel can leak or bleed to adjacent pixels. This may tend to cause annoying static visual artifacts, one of which is manifested as vertical bars of slightly different intensity. This artifact is not noticeable as a phenomenon when the image is a natural image such as a photograph, but when it is an image with highly repetitive content, such as a window background in a computer generated screen, intensity bars or variations in the intensity may appear as vertical bars. 
     Such static visual artifacts may be minimized by rotating the matrix columns at the beginning of each vertically adjacent matrix. For example, where a 16×16 matrix providing for 256 grey shades is used, the matrices in lines 0 through 16 include in order columns 0 through 15. In an embodiment where the column offset value is 4, the matrices in lines 16 through 31 (the second set of matrices from the top) begin with column 3 and end with column 2. The third set of matrices from the top begin with column 7 and end with column 6. While in the above example, the rotation value is 4, the column rotation value may be programmable according to the present invention so that minor adjustments may be made as needed. 
     Persons of ordinary skill in the art will observe that, while for ease of both understanding and implementing the present invention, square matrices are preferred, other matrix configurations may be employed without departing from the spirit of the present invention. Some of such other configurations will be non-optimal, however, due to the difficulty of predicting the behavior of neighboring pixels. 
     The second part of the process primarily addresses the consumption or use of the pixels within the matrix to realize smooth shading of an individual pixel over time. This is accomplished by using a circular queue. The circular queue causes pixel consumption in sequential matrix address order, and provides that within any given number of frames that pixels are used with an even distribution. Each color primary has an independent circular queue per shade. Circular queues for each shade of each color primary may be in arbitrary alignment with respect to each other in order to achieve optimal visual results. 
     The gray-scale value of the pixel and the frame number within a sequence of frames is used to select a range of matrix addresses from a circular queue (the &#34;ON&#34; range). The address of the current pixel is compared to the &#34;ON&#34; range. If the current pixel&#39;s value is within that range, then it is switched &#34;ON&#34; for that frame. If the current pixel&#39;s value is outside of that range, then it is switched &#34;OFF&#34; for that frame. 
     The circular queue is a modulo N list of the control matrix addresses in ascending order, where N is the desired grey scale resolution. The queue recycles back to the beginning when it reaches its end, i.e., in a 256 address matrix having addresses 0-255, the address following 255 is 0. 
     The range of values is changed for each frame. According to a presently preferred embodiment of the invention, the range of values is equal to the grey scale value of the incoming pixels and for each frame its starting point is incremented by that grey scale value. In each frame, the current incoming pixel value is used and is offset by the frame number multiplied by the current incoming pixel value. The total number of frames is equal to the grey scale resolution. For the example of the 16×16 matrix used herein, there are 256 frames, which may be conveniently referred to as F0-F255. In general, the range of values is determined by: 
     
         Rmin.sub.n =FG+Offset                                      [Eq. 1] 
    
     and 
     
         Rmax.sub.n =Rmin.sub.n +(G-1)                              [Eq. 2] 
    
     where Rmin is the lower end of the range in modulo N, Rmax is the upper end of the range in modulo N, G is the grey scale value of the incoming pixel, F is the frame number, and N is the desired grey scale resolution. For G=0, Rmin/Rmax are ignored and zero is output to the display. Offset is used for multicolor displays, as will be disclosed herein. For black and white displays, the value Offset can have any value. 
     As an example of the range value assignment, assume a grey scale resolution of 256 grey shades, and an incoming pixel having a grey scale value of 64 (one-quarter of full scale in a range of 0-255). Table 1 illustrates the range of values in successive ones of the 256 frames. 
     
                       TABLE 1______________________________________Frame Number   Value Range______________________________________F0              0-63F1              64-127F3             128-191F4             192-255______________________________________ 
    
     Those of ordinary skill in the art will recognize that the range of values repeats itself every four frames, or sixty-four times in every 256 frames. Thus, each pixel in the control matrix having a grey scale value of 64 will be turned on for one frame out of every four. 
     As another example, Table 2 illustrates the range of values in successive ones of the 256 frames for a pixel value of 
     
                       TABLE 2______________________________________Frame Number   Value Range______________________________________ F255          2-255F0             0-253F1             254-251.              ..              ..              . F254          4-1 F255          2-255F0             0-253______________________________________ 
    
     In the example of Table 2, those of ordinary skill in the art will recognize that the range of values repeats itself every two hundred and fifty four frames. In general, for any pixel grey shade value &#34;G&#34;, the range of &#34;ON&#34; values will repeat itself G times in 256 frames. Persons of ordinary skill in the art will appreciate that the consumption of the values in time is always very periodic. By choice, a matrix address layout is selected that minimizes or avoids the common motion visual artifacts. 
     Persons of ordinary skill in the art will recognize that the grey scale value of any given pixel in a moving image on the display will likely change from frame to frame. As shown in Eq. 1, the calculation for the starting point of the range of values employs only the current frame number and the grey scale value of the instant incoming pixel. The grey scale value of the incoming pixel at that location in the display in the previous frame is irrelevant. 
     Referring now to FIG. 2, a flow diagram illustrates the pixel consumption method of the present invention. First, at step 10, the grey scale value for the current pixel to be displayed is fetched from an appropriate place in the pixel pipeline. Next, at step 12, the range of values in the current frame for that pixel is calculated at step 12. 
     At step 14, the matrix address of the pixel to be displayed is compared with the range of values for the current frame calculated in the previous step. If the pixel address is in range, that pixel is turned on at step 16. After step 16, or if the matrix address of the pixel to be displayed is not within the range of values, the process proceeds to step 18 where it is determined if the current pixel is the last pixel in the current frame. If not, process control is transferred back to step 10 to process the next pixel. If the current pixel is the last pixel in the current frame process control is transferred to step 20 where the frame number is incremented. Process control is then transferred back to step 10 to process the first pixel in the next frame. 
     In a color digital display, this pixel consumption method described herein is duplicated for each color primary. A problem may be encountered if the range of values in the circular queue is started at the same point for each gray shade for each of the red primaries, the green primaries and the blue primaries. The on points and off points for all the red, green and blue shades will coincide. It is possible that because of the intensity of the red, green, and blue turning off or on at the same time, a more noticeable blink effect would occur. 
     In order to avoid such artifacts, the ranges of values are offset for each color primary in the display, as indicated by the variable &#34;Offset&#34; in Eq. 1. In the above examples, the ranges of values at F0 started at address 0. If the above examples are assumed to relate to a first primary color in a digital display, the F0 starting addresses for the ranges of values for the other two primary colors would be offset. In an actual 256 frame system fabricated according to the present invention, the range of values for F0 of the second and third primary colors are offset equally so that the F0 range of values for the second primary color begins at 85 and the F0 range of values for the third primary color begins at 170. The values 0, 85, and 170 are each spaced apart by approximately one third of the total address value range of 0-255. According to a presently preferred embodiment of the invention, the color starting point offsets may be programmable so that other values may be selected for the offset. 
     For comparison, FRC-based processes typically run over a sixteen frame cycle, while the method of the present invention uses a two hundred fifty-six frame cycle, thus spreading low frequency events over a long sample interval with a high sample rate. 
     The method of the present invention does introduce two different artifacts, referred to herein as &#34;sparkle&#34; and &#34;darkle.&#34; Sparkle may be manifested at very low valued gray shades when physically separated individual pixels cycle partially on and then decay to the off state. The darkle artifact is the opposite of sparkle. Darkle occurs at very high valued gray shades when physically separated individual pixels are allowed to cycle partially off. Sparkle and darkle occur over such small gray scale ranges and at such low thresholds of discrimination that they are preferable artifacts in comparison to all of the artifacts of previous methods. 
     Referring now to FIGS. 3 through 10, a block diagram of a hardware system 30 for implementing the present invention is shown. FIG. 3 is a first portion of the block diagram and shows pixel matrix address generator 32, circular queue 34, and data compare unite 36. The following disclosure assumes a 16 by 16 matrix size. 
     Pixel matrix address generator 32 generates the pixel address PIX --  ADDR which is 8 bits in the presently preferred embodiment of the invention employing a 16×16 matrix. Circular queue 34 generates Rmin and Rmax, the upper and lower bounds of the range of values in the queue for which an individual pixel is to be turned on, as well as G, the grey shade value. Data compare unit 36 evaluates the PIX --  ADDR and the Rmin and Rmax data from circular queue 34 and generates the signal to turn the current pixel on or off in response thereto. There are several inputs to pixel matrix address generator 32 and circular queue 34. 
     CONTROL DATA is an eight-bit bus which inputs RAM data, RAM address, column offset value or color offset value into pixel matrix address generator 32 and to circular queue 34. WRITE --  COL --  SHIFT input is a clock pulse for loading the lower 4-bit CONTROL DATA as a column offset value. WRITE --  ADDR is a clock pulse for loading 8-bit CONTROL DATA as an address of the 256×8-bit RAM of FIG. 5 WRITE --  RAM is a clock pulse for loading CONTROL DATA as data into the 256×8-bit RAM of FIG. 5. LOAD --  RAM selects an address for 256×8-bit RAM. The use of a multipurpose bus like CONTROL DATA and the use of multiple clock signals for capturing data or interest to particular devices on the bus is familiar to those of ordinary skill in the art. 
     HSYNC is an end-of-line signal and goes high after displaying each line of the current frame. VSYNC is an end-of-frame signal presented to pixel matrix address generator 32 and to circular queue 34, and goes high after displaying all lines of one frame. DOTCLOCK is a clock pulse running at the pixel consumption rate presented to pixel matrix address generator 32 and to circular queue 34 for clocking each pixel value. The combination of DOTCLOCK, HSYNC, VSYNC, and WRITE --  COL --  SHIFT are used to set the column and row address of the 16×16 matrix as will be disclosed herein. The matrix element is previously downloaded to the 256×8-bit RAM of FIG. 5 by using CONTROL DATA as address and data inputs. Rmin and Rmax is the result from CIRCULAR QUEUE according the color value of pixel, current frame number and color offset value. 
     RESET resets the frame counter in circular queue 34 to zero and is asserted prior to initial operation of circular queue 34. PIXEL DATA is the 8-bit color value of the current pixel to be displayed. 
     WRTE --  OFFSET is a clock pulse for loading CONTROL DATA as color offset value. PANEL DATA is the output of data compare unit 36 and is either &#34;1&#34; or &#34;0&#34; which is used to turn the panel pixel &#34;on&#34; or &#34;off&#34;. Data compare unit 36 will output &#34;1&#34; if PIX --  ADDR is greater than or equal to Rmin and less than or equal to Rmax in cases where the queue is not looping. In the case where the queue is looping, data compare unit 36 will output &#34;1&#34; if PIX --  ADDR is greater than or equal to Rmin and less than or equal to 255 or if PIX --  ADDR is less than or equal to Rmax and greater than or equal to zero. In the special case where the grey shade value of the pixel is zero, data compare unit 36 will output zero. PIX --  ADDR is one of the elements of 16×16 matrix. 
     FIG. 4 is a more detailed block diagram in which the pixel matrix address generator 32 of FIG. 3 is seen to comprise a pixel column and pixel row address generator 38 and pixel matrix address generator 40. The combination of DOTCLOCK, HSYNC, VSYNC, and WRITE --  COL --  SHIFT inputs to pixel column and pixel row address generator 38 are used to generate the column and row address of the 16×16 matrix as outputs PIX --  COL and PIX --  ROW. The PIX --  COL (column address of 16×16 matrix) and PIX --  ROW (row address of 16×16 matrix) are used as addresses for fetching the matrix element from pixel matrix address generator 40 when LOAD --  RAM is low. When LOAD --  RAM is high CONTROL DATA will be used as data input with WRITE --  RAM high to write a 16×16 matrix element to the 256×8-bit RAM (shown in FIG. 5). 
     FIG. 5 is a more detailed block diagram of the pixel matrix address generator 40 block of FIG. 4. When WRITE --  ADDR is high, the CONTROL DATA input will load 8-bit register 42 with RAM ADDRESS. When LOAD --  RAM is HIGH, the RAM ADDRESS will pass through the A inputs of 2:1 multiplexers 44 and 46 as column and row addresses, respectively, for the 256×8-bit RAM 48. CONTROL DATA input will load to the 256×8-bit RAM location indicated by RAM ADDRESS when WRITE --  RAM is HIGH. When LOAD --  RAM is LOW, the PIX --  COL and PIX --  ROW data will pass through the B inputs of 2:1 multiplexers 44 and 46 and the PIX --  ADDR will be valid. 
     FIG. 6 is a more detailed block diagram of the pixel column and pixel row address generator 38 of FIG. 4. Every 16 lines vertically down the display frame, the column offset value will be added to the previous accumulated column offset value for the next 16 vertical lines. 
     The initial column offset value (COL --  SHIFT) is loaded to 4-bit register 50 by inputting the lower 4 bits of CONTROL DATA when the WRITE --  COL --  SHIFT signal at its clock input goes high. Four-bit counter 52 is clocked by the DOTCLOCK signal and its output, representing the raw column number 0-15, is presented to adder 54 whose function is to add the offset value to it to produce the output PIX --  COL as will be described herein. Four-bit counter 56 is clocked by the HSYNC signal. The CARRY signal of 4-bit counter 64 will indicate that 16 columns have passed and will clock 4-bit register 58 to provide a new offset value to the 4-bit adder 54. 
     Four-bit register 50, 4-bit adder 60, 4-bit register 58, and 4-bit register 62 perform the function of incrementing the column offset every 16 lines of each frame. At the beginning of each line of display pixels, HSYNC resets 4-bit counter 52. At the beginning of each frame, VSYNC resets 4-bit register 58, 4-bit register 62, and 4-bit counter 56 to zero. During the first 16 lines in a frame, the zero-value output of 4-bit register 58 is added to the raw column data from 4-bit counter 52, resulting in no offset. During this time the zero-value output of 4-bit register 62 is presented to 4-bit adder 60, causing its output to equal COL --  SHIFT. 
     After the first 16 lines have been counted, the carry output of 4-bit counter 56 clocks the value COL --  SHIFF into 4-bit register 58. For the next 16 lines, the 4-bit adder 54 will increment the raw column data from 4-bit counter 52 by the quantity COL --  SHIFT. During this time the output of 4-bit register 62, which has now been set to COL --  SHIFT by clocking through inverter 64 for synchronization, is presented to 4-bit adder 60, causing its output to equal a value of twice COL --  SHIFT. 
     After the second 16 lines have been counted, the carry output of 4-bit counter 52 clocks the value of twice COL --  SHIFT into 4-bit register 58. For the next 16 lines, the 4-bit adder 54 will increment the raw column data from 4-bit counter 52 by the quantity equal to twice COL --  SHIFT. During this time the output of 4-bit register 62, which has now been set to twice COL --  SHIFT, is presented to 4-bit adder 60, causing its output to equal a value of three times COL --  SHIFT. 
     From the above disclosure, persons of ordinary skill in the art will observe that, for each group of 16 lines of display following the first group of 16 lines, the PIX --  COL output will be offset by a value of n times COL --  SHIFT, where n is the nth repetition of 16 lines in the frame. 
     After displaying each line, the HSYNC will again go high and reset the 4bit counter 52 to zero for the beginning of the next line. Four-bit counter 56 is clocked by the HSYNC signal to produce the output PIX --  ROW, a value between 0-15. This counter is reset when VSYNC goes HIGH, indicating the end of a frame. 
     FIG. 7 is a more detailed block diagram of the circular queue 34 of FIG. 3. The G,FG unit 70 (G=Gray Shade and FG=Frame Number times Gray Shade) will generate value of gray shade G and value of frame number times gray shade FG. The grey shade is simply the value of the input PIXEL DATA and the value FG is determined from VSYNC as will be more particularly disclosed with reference to FIG. 8 herein. 
     The value of gray shade G and value of frame number times gray shade FG from G,FG unit 70 are presented to Rmin Rmax generator 72. The offset which will be added add to the boundary values (Rmin and Rmax) is loaded from CONTROL DATA when WRITE --  OFFSET goes HIGH. &#34;1&#34; is a constant value which is use for subtracting the value &#34;one&#34; from G (Gray Shade). 
     FIG. 8 is a more detailed block diagram of the G,FG unit 70 of FIG. 7. An 8-bit binary counter 74 will increment F(Frame Number) output by one each time VSYNC goes high, indicating the end of a frame. Counter 74 will roll 255 over to zero. The 8-bit binary counter 74 will be reset to zero when RESET goes high, indicating the start of frame sequence for initial operation. PIXEL DATA (the grey scale value of the current pixel) will be clocked to 8-bit register 76 when DOTCLOCK goes high. The G(Gray Shade) output of register 76 is multiplied by the F(Frame Number) output of 8-bit counter 74 in multiplier 78. The least significant 8-bit output of multiplier 78 is FG(Frame Number times Gray Shade). 
     FIG. 9 is a more detailed block diagram of the Rmin Rmax unit 72 of FIG. 7. Rmin is generated by adding the FG(Frame Number times Gray Shade) value with the color offset in 8-bit adder 80. The color offset is loaded from CONTROL DATA into 8-bit register 82 with WRITE --  OFFSET high. 
     Rmax is generated by adding Rmin with the quantity G(Gray shade) minus one in 8-bit adder 84. The output of 8-bit adder 84 is the least significant 8 bit result. The output of subtractor is least significant 8 bits result with 0 rolling over to 255. The quantity G(Gray shade) minus one is calculated in subtractor 86. 
     FIG. 10 is a more detailed block diagram of the data compare unit 36 of FIG. 3. The output of a first 8-bit comparator 90 is set to one if PIX --  ADDR is greater than or equal to Rmin. The output of second 8-bit comparator 92 is set to one if PIX --  ADDR is less than or equal to Rmax. The output of third comparator 94 is set to zero if Rmax is less than Rmin, a condition which occurs when the circular queue address range loops from 255 to zero. 
     The output of AND gate 96 is set to one if the outputs of both comparators 90 and 92 are set to one, indicating a pixel in the valid address ranges for cases where queue looping is not a consideration. The output of OR gate 98 is set to one if either the output of comparator 90 or 92 is set to one, indicating pixel in the valid address ranges for cases where queue looping is a consideration. 
     If the output of comparator 94 is set to zero, queue looping is not occurring, and thus multiplexer 100 passes the output of AND gate 96. If the output of comparator 94 is set to one, queue looping is occurring, and thus multiplexer 100 passes the output of OR gate 98. 
     In the special case where the grey shade G of the incoming pixel is zero, comparator 102 causes 8-bit wide multiplexer 104 to pass a hardwired zero to its output PANEL DATA. Otherwise, comparator 102 causes multiplexer 104 to pass the output of multiplexer 100 to PANEL DATA. 
     While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.