Abstract:
An improved prefetch program counter (PC) generation circuitry is provided to the prefetch and dispatch unit (PDU) of a pipelined computer system. The prefetch PC generation circuitry factors into consideration the states of dispatched CTIs in various pipeline stages, when generating a new prefetch PC value for instruction prefetching. The dispatched CTI state dependent prefetch PC generation circuitry includes storage circuitry, fetch control circuitry, and fetch PC generation circuitry. Together, the storage circuitry, the fetch control circuitry, and the fetch PC generation circuitry cooperate to prefetch instructions in a CTI state dependent manner, thereby improving the instruction prefetch rate. In one embodiment, two dynamically switchable instruction fetch queues are provided, with one being used as the sequential instruction fetch queue, and the other being used as the target instruction fetch queue.

Description:
This is a continuation of application Ser. No. 08/283,097, filed Jul. 29, 1994, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention: 
     The present invention relates to the field of computer systems. More specifically, the present invention relates to instruction prefetch and dispatch methods and apparatus of computer systems. 
     2. Background Information: 
     Historically, instruction fetch and dispatch units, and execution units of computer systems fetch, decode, and execute instructions sequentially in program order, one instruction at a time. In other words, an instruction fetch and dispatch unit will fetch and decode an instruction, and then wait for the execution unit to complete execution of the instruction before fetching and decoding another instruction. Under this sequential approach, whether a preceding conditional control transfer instruction (CTI) will be taken or not, and if taken, what is the target address, will both be known at the time the next instruction is fetched. Thus, there is no problem with knowing which is the next instruction to be fetched, and where is it located in memory. 
     To improve performance, instruction fetch and dispatch units, and execution units of some computer systems pipeline the fetching, decoding, and execution of instructions. In other words, while a first instruction is being executed, a second instruction is being decoded in preparation for execution, and a third instruction is being fetched for decoding. The instructions will move through the fetch, decode, and execute pipeline stages in an orderly manner. In some computer systems, the basic fetch, decode, and execute pipeline stages are further broken down into sub-stages, thereby allowing even more instructions to be moving through the pipeline at the same time. Under this pipelined approach, whether a preceding conditional control transfer instruction (CTI) will be taken or not, and if taken, what is the target address, will not necessarily be known at the time a subsequent instruction is fetched. In order to keep the pipeline filled, instead of temporarily suspending instruction fetching and decoding when a CTI is encountered, most pipelined computer systems employ some type of prediction algorithms to predict which direction execution control will be transferred, and continue instruction fetching, decoding, and execution along the predicted direction. If the prediction subsequently turns out to be incorrect, the execution results are purged; instruction fetching, decoding, and execution is then redirected to the correct direction. 
     Since instruction fetching involves reading the instructions in from memory, which is a &#34;slow&#34; process, as compare to instruction execution by the execution unit, most instruction fetch and decode units of pipelined computer systems will pre-fetch instructions to ensure adequate supply of instructions are available to keep the pipeline filled. The prefetched instructions are partially or totally purged as appropriate, when incorrect execution control transfer prediction is detected. 
     In recent years, many pipelined computer systems have also gone &#34;superscalar&#34;, i.e. being capable of executing instructions in groups, thereby further improving execution throughput. Thus, it is desirable to have an instruction prefetch and dispatch unit that can keep up with the improved throughput of the execution unit on a &#34;superscalar&#34; computer system, by intelligently looking and prefetching further ahead downstream than its counterpart in a &#34;regular&#34; pipelined computer system. Additionally, this trend of ever increasing execution throughput is further accelerated by continuing increase of processor speeds of the &#34;superscalar&#34; computer systems, thus making the ability of intelligently looking and prefetching far ahead downstream to be even more desirable. 
     As will be disclosed in detail below, the present invention provides a method and apparatus for prefetching instructions that achieves these and other desired results. 
     SUMMARY OF THE INVENTION 
     The desired results are advantageously achieved by providing prefetch program counter (PC) generation circuitry to the prefetch and dispatch unit (PDU) of a computer system, that factors the states of dispatched CTIs in the various pipeline stages into consideration, in generating the prefetch PC value. The prefetch PC generation circuitry comprises storage circuitry, fetch control circuitry, and fetch PC generation circuitry. The storage circuitry stores state control information about the dispatched CTIs in the various pipeline stages. The fetch control circuitry generates control signals to control the fetch PC generation circuitry in view of the state control information stored. The fetch PC generation circuitry generates the fetch PC values under the control of the fetch control circuitry. 
     In one embodiment, the PDU is further provided with two instruction fetch queues, an instruction dispatch queue, and associated queue control and dispatch circuitry. The two instruction queues store the instructions being prefetched based on the prefetch PC value generated by the prefetch PC generation circuitry of the present invention. The instruction dispatch queue selectively receives and stores the instructions being dispatched, from either one of the two instruction fetch queues or the instruction cache bypassing the two instruction fetch queues, under the control of the associated queue control and dispatch circuitry. The associated queue control and dispatch circuitry controls the queues and instruction dispatching, in particular, dynamically designating one of the two instruction fetch queues as the sequential instruction fetch queue, and the other instruction fetch queue as the target instruction fetch queue. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an exemplary pipelined computer system incorporating the teachings of the present invention. 
     FIG. 2 illustrates pipeline stages of the exemplary computer system of FIG. 1. 
     FIG. 3 illustrates the relevant portions of one embodiment of the instruction prefetch and dispatch unit of FIG. 1 in further detail. 
     FIG. 4 illustrates the relevant portions of one embodiment of the prefetch program counter generation circuitry of the present invention. 
     FIG. 5 illustrates the contents of the state storage circuitry of FIG. 4. 
     FIG. 6 illustrates the operation flow of the fetch control circuitry of FIG. 4. 
     FIG. 7 illustrates the relevant portions of one embodiment of the fetch PC generation circuitry of FIG. 4 in further detail. 
    
    
     DETAILED DESCRIPTION 
     In the following description for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well known systems are shown in diagrammatic or block diagram form in order not to obscure the present invention unnecessarily. 
     Referring now to FIG. 1, a block diagram illustrating an exemplary pipelined computer system incorporating the teachings of the present invention is shown. The exemplary computer system 10 includes an instruction prefetch and dispatch unit (PDU) 12 incorporating the teachings of the present invention. Additionally, the exemplary computer system 10 further includes execution units and associated register files 14, an instruction and a data cache 16 and 20, a memory management unit 18, and a bus interface 22. The elements 12-22 are coupled to each other as shown. Cooperatively, instructions are fetched from the instruction cache 16 and system memory (not shown), and dispatched to the execution units 14 for execution. The execution results are stored back into the data cache 20, and if applicable, to the system memory. Except for the teachings of the present invention incorporated in the PDU 12, elements 14-22 are intended to represent a broad category of these elements found in most computer systems. The constitutions and basic functions are well known and will not be otherwise described further. The teachings of the present invention incorporated in the PDU 12 will be described in further detail below with additional references to the remaining figures. 
     Referring now to FIG. 2, a block diagram illustrating the pipeline stages of the exemplary computer systems of FIG. 1 is shown. As illustrated, at any point in time, multiple instructions are being &#34;executed&#34;. The pipeline stages include an instruction fetch stage 13, an instruction decode stage 15, an execute stage 17, and a writeback stage 19. Instructions are fetched and decoded in the fetch and decode stages 13 and 15 respectively. Decoded instructions are executed in the execute stage 17, and the execution results are written back into storage in the writeback stage 19 respectively. The instructions moved through the pipeline sequentially in program order. While the present invention is being described with four pipeline stages, based on the descriptions to follow, it will be appreciated that the present invention may be practiced with less or more pipeline stages. 
     Referring now to FIG. 3, a block diagram illustrating the relevant portions of one embodiment of the PDU 12 of FIG. 1 in further detail is shown. As illustrated, the PDU 12 includes two instruction fetch queues 24a and 24b and an instruction dispatch queue 28. Additionally, the PDU 12 includes queue control circuitry 26 and dispatch control circuitry 30. Furthermore, the PDU 12 includes execution PC generation circuitry 32 and prefetch PC generation circuitry 34. The elements 24a-24b, and 26-34 are coupled to each other, and to the instruction cache 16 and the execution units 14 as shown. 
     The two instruction fetch queues 24a-24b are used to store the instructions fetched from the instruction cache 16. As will be explained in more detail below, at any point in time, one of two instruction fetch queues 24a-24b is used as the sequential instruction fetch queue, whereas the other instruction fetch queue 24a or 24b is used as the target instruction fetch queue. The manner in which the two instruction queues 24a-24b are used is dynamically determined. 
     The instruction dispatch queue 28 is used to store the instructions being dispatched. The instruction dispatch queue 28 receives the instructions being dispatched from the instruction fetch queue 24a or 24b that is being used as the sequential instruction queue. Preferably, the instruction dispatch queue 28 can also receive instructions being dispatched from the instruction cache 16 directly by-passing the instruction fetch queues 24a-24b in the event these queues 24a-24b are empty. 
     The queue control circuitry 26 controls the two instruction fetch queues 24a-24b. In particular, the queue control circuitry 26 maintains the queue head pointers and the queue tail pointers of the two queues 24a-24b indicating where the next instructions to be dispatched are to be retrieved, and where the next instructions fetched are to be stored. 
     The dispatch control circuitry 30 controls dispatching of instructions from the dispatch queue 28. The dispatch control circuitry 30 also provides dispatch control information to the queue control circuitry 26, the execution PC generation circuitry 32, and the prefetch PC generation circuitry 34. In the illustrated embodiment, the dispatch control circuitry 30 dispatches instruction in groups of up to three (3) instructions at a time. However, there will be at most one CTI in a group of dispatched instructions. 
     Additionally, in one embodiment, there are two types of CTIs, non-delayed CTIs and delayed CTIs. A non-delayed control transfer changes control to the instruction at the target address immediately after the CTI is executed, whereas a delayed control transfer changes control to the instruction at the target address after a 1-instruction delay. The instruction after the delayed CTI is executed before the target of the CTI is executed. This instruction is referred to as the affiliated delay instruction (DI) of the delayed CTI. 
     A particular example of a computer system wherein instructions are dispatched in groups, and CTIs include non-delayed as well as delayed CTIs, is the Sparcstation 20, manufactured by Sun Microsystems, Inc., of Mountain View, Calif. 
     The execution PC generation circuitry 32 and the prefetch PC generation circuitry 34 generate the execution PC value and the prefetch PC value for the execution units 14 and for the instruction cache 16 respectively. The execution PC value denotes the address of instruction to be executed, whereas the prefetch PC value denotes the starting address of the next block of instructions to be prefetched. 
     In accordance to the present invention, the prefetch PC generation circuitry 34 generates the prefetch PC value factoring into consideration the states of the dispatched CTIs in the various pipeline stages. The execution PC generation circuitry 32 assists the prefetch PC generation circuitry 34 in doing so by providing also the target addresses of the CTIs in the various pipeline stages, i.e. the target address of the CTI in the decode stage (DEC --  TGT --  PC), the target address of the CTI in the execute stage (EX --  TGT --  PC), and the target address of the CTI in the writeback stage (WB --  TGT --  PC) when control transfer instructions are encountered at the various pipeline stages. 
     The instruction fetch queues 24a-24b, the instruction dispatch queue 28, the associated queue control circuitry 26 and 30, and the execution PC generation circuitry 32 are intended to represent a broad category of these elements found in many instruction fetch and dispatch units of computer systems, including but not limited to the instruction fetching and dispatching elements described in copending U.S. patent application, Ser. No. 07/875,373, entitled &#34;Methods And Apparatus For Grouping Multiple Instructions, Issuing Grouped Instructions Simultaneously, And Executing Grouped Instructions In A Pipelined Processor&#34;, which is hereby fully incorporated by reference. The prefetch PC generation circuitry 34 will be described in more detail below with additional references to the remaining figures. 
     Referring now to FIG. 4, a block diagram illustrating the relevant portions of one embodiment of the prefetch PC generation circuitry 34 of FIG. 3 in further detail is shown. As illustrated, the prefetch PC generation circuitry 34 includes storage circuitry 36, fetch control circuitry 38, and fetch address generation circuitry 40. These elements 34-40 are coupled to each other as shown. The storage circuitry 36 stores state information of the dispatched CTIs provided by the dispatch control circuitry 30. The fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 based on the stored state information of the dispatched CTIs. The fetch address generation circuitry 40 generates the fetch PC value under the control of fetch control circuitry 38, using the target addresses of the CTIs in the various pipeline stages, if provided by the execution PC generation circuitry 32. 
     Having now described the architectural relationship of the key circuitry of the prefetch PC generation circuitry 32 of the present invention, the content of the storage circuitry 36 and the constitution of the fetch address generation circuitry 40 will be described first with references to FIGS. 5 and 6. Then, the control logic of the fetch control circuitry 38 will be described with references to FIG. 7, showing how the contents of the storage circuitry 36 are used to control the operation of the fetch address generation circuitry 40. 
     Referring now to FIG. 5, a diagram illustrating the content of the storage circuitry 36 of FIG. 4 is shown. As described earlier, the storage circuitry 36 stores the state information of the dispatched CTIs in the various pipeline stages. The dispatched CTI state storage circuitry 36 may be designed using a number of well known, preferably high speed, implementations, such as SRAM. In one embodiment, the storage circuitry 36 stores the state information in a single dispatched CTI state table 39, organized as a 3×4 matrix, having 12 bits, B0 through B11. The meanings of B0 and B11 are described below, and their usage will be described later in conjunction with the control logic of the fetch control circuitry 38. 
     B0, when set, indicates that a CTI is in the writeback stage. B11, when set, indicates that the CTI in the writeback stage is a delayed CTI and the affiliated DI is valid. B2, when set, indicates that the CTI in the writeback stage is taken. B3, when set, indicates the target instruction at the address of the CTI in the writeback stage is valid. 
     Similarly, B4, when set, indicates that a CTI is in the execution stage. B5, when set, indicates that the CTI in the execution stage is a delayed CTI, and the affiliated DI is valid. B6, when set, indicates that the CTI in the execution stage is taken. B7, when set, indicates the target instruction at the address of the CTI in the execution stage is valid. 
     Likewise, B8, when set, indicates that a CTI is in the decode stage. B9, when set, indicates that the CTI in the decode stage is a delayed CTI and the affiliated DI is valid. B10, when set, indicates that the target address of the CTI in the decode stage is valid. B11, when set, indicates the target instruction at the address of the CTI in the decode stage is valid. 
     Referring now to FIG. 6, a block diagram illustrating the relevant portions of one embodiment of the fetch address generation circuitry 40 of FIG. 4 in further detail is shown. As described earlier, the fetch address generation circuitry 40 generates the fetch PC value for instruction fetching. The fetch address generation circuitry 40 includes an incrementer 72, two multiplexors 74a-74b, and two latches 76a-76b. Their organization and relationship are described below, and their usage will be described later in conjunction with the control logic of the fetch control circuitry 38. 
     The second latch 76b is used to store the sequential fetch PC value (Saved Fetch --  PC) just issued. The stored Saved Fetch --  PC is used to calculate the potential incremented sequential PC values for the different cases of number of instructions included in the most recent dispatched group. The stored Saved Fetch --  PC may also be selected for reissuance as the new fetch PC. 
     The incrementor 72 is used to generate four potential incremented sequential PC values off the Saved Fetch --  PC value, one of each of the four possibilities of the number of instructions in the most recent dispatched group, i.e. zero, one, two, or three instructions. The first multiplexor 74a is used to select one of the four incremented sequential PC values as the proper incremented sequential PC value (INCR --  PC) for the second multiplexor 74b, under the control of fetch control circuitry 38. The first latch 76a is used to store the INCR --  PC for subsequent reissuance as the saved sequential PC (Saved SEQ --  PC). 
     Lastly, in addition to the Saved Fetch --  PC, the Saved SEQ --  PC, and the INCR --  PC, the second multiplexor 74b further receives the DEC --  TGT --  PC, EX --  TGT --  PC and WB --  TGT --  PC, and preferably a diagnostic or reset program counter value (DIAG/Reset) as inputs. Recall from earlier discussions that DEC --  TGT --  PC, EX --  TGT --  PC and WB --  TGT --  PC are the target addresses of the CTIs in the decode, execute, and writeback stages, provided by the execution PC generation circuitry 34. The second multiplexor 74b generates the next fetch PC value (Fetch --  PC) by selecting one of the received inputs, under the control of the fetch control circuitry 38. 
     Referring now to FIG. 7, a block diagram illustrating the operation flow of the fetch control circuitry 38 of FIG. 4 is shown. All decisions made by the fetch control circuitry 38 described below are made by the fetch control circuitry 38 examining the dispatched CTI state information stored in the storage circuitry 36, and all control signals are generated for the fetch address generation circuitry 40. The fetch control circuitry 38 may be implemented with any number of combinatorial logics well known in the art. 
     As illustrated, in each clock cycle, the fetch control circuitry 38 first determines whether a CTI is in the writeback stage, by examining B0, step 42. If a CTI is in the writeback stage, the fetch control circuitry 38 further determines whether it is a delayed CTI and whether the affiliated DI is valid, by examining B1, step 44. If the CTI is a delayed CTI and the affiliated DI is not valid, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that the affiliated DI is to be fetched, step 45. In other words, the fetch address generation circuitry 40 generates control signals for the two multiplexors 74a-74b in the next fetch address generation circuitry 40 to select +4 and INCR --  PC respectively. 
     On the other hand, if at step 44, the CTI is not a delayed CTI or the affiliated DI is valid, then the fetch control circuitry 38 further determines whether the CTI in the writeback stage is taken, by examining B2, step 46. If the CTI in the writeback stage is taken, then the fetch control circuitry 38 further determines whether the target instruction for the CTI in the writeback stage has been fetched, by examining B3, step 48. If the target instruction for the CTI in the writeback stage has not been fetched, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that the target instruction of the CTI in the writeback stage is to be fetched, block 49. In other words, the fetch address generation circuitry 40 generates control signals for the second multiplexor 74b in the next fetch address generation circuitry 40 to select WB --  TGT --  PC. Since INCR --  PC is not being selected, the control signals for the first multiplexor 74a are irrelevant. 
     If it is determined in step 42 that there is no CTI in the writeback stage, or in step 46 that the CTI in the writeback stage is not taken, or in step 48 that the target instruction for the CTI in the writeback stage is fetched, the fetch control circuitry 38 then determines whether there is a CTI in the execution stage, by examining B4, step 52. If a CTI is in the execution stage, the fetch control circuitry 38 further determines whether the CTI is a delayed CTI and whether its affiliated DI is valid, by examining B5, step 54. If the CTI in the execute stage is a delayed CTI and the affiliated DI is not valid, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that the affiliated DI is to be fetched, block 55. In other words, the fetch address generation circuitry 40 generates control signals for the two multiplexors 74a-74b in the next fetch address generation circuitry 40 to select +4 and INCR --  PC respectively. 
     On the other hand, if at step 54, either the CTI is not a delayed CTI or the affiliated DI is valid, then the fetch control circuitry 38 further determines whether the CTI in the execution stage is taken, step 56. If the CTI in the execution stage is taken, then the fetch control circuitry 38 further determines whether the target instruction for the CTI in the execution stage has been fetched, step 58. If the target instruction for the CTI in the execution stage has not been fetched, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that the target instruction of the CTI in the execution stage is to be fetched, block 59. In other words, the fetch address generation circuitry 40 generates control signals for the second multiplexor 74b in the next fetch address generation circuitry 40 to select EX --  TGT --  PC. 
     If it is determined in step 52 that there is no CTI in the execution stage, or in step 56 that the CTI in the execution stage is not taken, or in step 58 that the target instruction for the CTI in the execution stage is fetched, the fetch control circuitry 38 then determines whether there is a CTI in the decode stage, step 62. If there is no CTI in the decode stage, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that instructions are to be fetched along the sequential stream, step 63. In other words, the fetch address generation circuitry 40 generates control signals for the two multiplexors 74a-74b in the next fetch address generation circuitry 40 to select either +4, +8, +12, or +16 and INCR --  PC respectively, depending on the number of valid instructions that were returned on the previous fetch. 
     If at step 62, a CTI is in the decode stage, the fetch control circuitry 38 further determines whether the CTI is a delayed CTI and whether its affiliated DI is valid, step 64. If the CTI is a delayed CTI and the affiliated DI is not valid, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that the affiliated DI is to be fetched, step 65. In other words, the fetch address generation circuitry 40 generates control signals for the two multiplexors 74a-74b in the next fetch address generation circuitry 40 to select +4 and INCR --  PC respectively. 
     If at step 64, either the CTI is not a delayed CTI or the affiliated DI is valid, then the fetch control circuitry 38 further determines whether the target address of the CTI in the decode stage is valid, step 66. If the target address is not valid, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating no instruction is to be fetched, step 67. In other words, the fetch address generation circuitry 40 generates control signals for the second multiplexor 74b in the next fetch address generation circuitry 40 to select SAVED --  SEQ --  PC. 
     If at step 66, the target address of the CTI in the decode stage is valid, then the fetch control circuitry 38 further determines whether the target instruction for the CTI in the decode stage has been fetched, step 68. If the target instruction for the CTI in the execution stage has not been fetched, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that the target instruction of the CTI in the decode stage is to be fetched, step 69a. In other words, the fetch address generation circuitry 40 generates control signals for the second multiplexor 74b in the next fetch address generation circuitry 40 to select DEC --  TGT --  PC. 
     Otherwise, the fetch control circuitry 38 generates control signals for the fetch address generation circuitry 40 indicating that no instruction is to be fetched, step 69b. In other words, the fetch address generation circuitry 40 generates control signals for the second multiplexor 74b in the next fetch address generation circuitry 40 to select SAVED --  FETCH --  PC. 
     While the present invention has been described in terms of various embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. In particular, while the present invention is being described with an embodiment where the grouping rules guarantee there is at most one CTI per group (thus per pipeline stage), it will be appreciated that the present invention may be practiced with more than one CTI per group provided the storage circuitry 36, the fetch control circuitry 38, and the fetch address generation circuitry 40, are adjusted correspondingly to track and account for the state information of all permutations. Thus, the method and apparatus of the present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting on the present invention.