Abstract:
A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor) with its well grounded. An output NMOS FET (negative MOS FET) and an extra input pulldown NMOS FET are connected in parallel to the input of the converter. The extra input pulldown NMOS FET provides a negative gate voltage at its drain to the output driver PMOS FET gate. The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse and output pulse due to Miller capacitance effect.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention generally relates to level conversion for multiple-supply voltages for very large scale integration systems and, more particularly, to low voltage-level down conversion with very low voltage operation for on-chip test circuitry.  
         [0002]     Prior art voltage level conversion, e.g., for a dual-supply voltage system, is commonly performed through a differential inverter circuit. The output response for such a circuit is generally limited by the driving capability of the output inverter, e.g., a MOSFET (metal-oxide semiconductor field effect transistor) used to drive the load. Achieving low voltage operation by increasing the output driver size to get more current drive typically does not solve the problem due to the fact that upsizing the driver increases the intrinsic and coupling capacitance MOSFET devices typically have considerable coupling capacitance between their gate and drain terminals. The high edge rate of rise (fall) of drain voltage may couple capacitively to the gate of the MOSFET via the Miller capacitance. The coupling can cause the gate voltage of the MOSFET to rise resulting in unintended or deleterious operation of the circuit. Thus, upsizing the driver to get more current drive may in fact lead to a degradation rather than an improvement in level conversion circuit performance.  
         [0003]     For an on-chip test circuit, one objective is to convert an input signal, e.g., a test noise pulse, from a high supply voltage level to a lower supply voltage level. Due to the trade-off between current drive and intrinsic capacitance, however, prior art circuits have not been able to achieve a satisfactorily short rise time of the output signal at the lower supply voltage while producing the current drive required. To illustrate,  FIG. 1  shows transient response for one example of a prior art level converter on graph  100  of voltage, shown in millivolts (m) on the ordinate, against time, shown in nanoseconds (n) on the abscissa. Graph  100  shows output pulse  102  for comparison on the same graph with input pulse  106 . Input pulse  106  is a result of non-inverted input pulse  104 . As can be seen in  FIG. 1 , output pulse  102  has a poor rise time, indicated generally at  108 , so that the output pulse rise time  116  (succinctly, the time for voltage of output pulse  102  to go from 10 % to 90% of the full amplitude voltage level) occupies an unacceptably large portion of the pulse width  110  of input pulse  102 . For example, as shown in  FIG. 1 , the rise time  116  is approximately 1.7 nanoseconds out of the entire pulse width  110  of approximately 2.2 nanoseconds. In addition, the Miller capacitance effect may produce an initial voltage drop  112 , which may also be referred to as coupling effect. Such a voltage drop  112  is the opposite of desired circuit performance for the rising edge  114  (LOW to HIGH transition) of the input pulse  104  and adversely affects the long rise time  116 .  
         [0004]     As can be seen, there is a need for a low voltage level converter that converts an input signal from a high supply voltage level to a lower supply voltage level. There is also a need for a level down converter that overcomes the limitations of Miller capacitance to provide required current drive with significantly improved, i.e., shortened, rise time of the output pulse.  
       SUMMARY OF THE INVENTION  
       [0005]     In one embodiment of the present invention, a low-voltage level converter circuit includes an output driver transistor and a separate input pulldown transistor that provides a pulldown voltage to the gate of the output driver transistor.  
         [0006]     In another embodiment of the present invention, a system includes a low-voltage level converter having an input pulldown negative metal-oxide semiconductor (NMOS) transistor that provides a negative gate voltage to a positive metal-oxide semiconductor (PMOS) output driver transistor having a grounded well.  
         [0007]     In still another embodiment of the present invention, an on-chip test system includes a pulse generator that provides an input pulse signal at a high supply voltage level to a low-voltage level converter. The low-voltage level converter includes an input pulldown transistor that provides a negative gate voltage to an output driver PMOS FET having a grounded well; and an output NMOS FET having a gate connected in parallel with the input pulldown transistor to an input of the low-voltage level converter. The input of the low-voltage level converter receives the input pulse signal from the pulse generator. The drains of both the PMOS FET and the output NMOS FET are both connected to an output of the low-voltage level converter; and a device under test is connected to the output of the low-voltage level converter. The device under test receives an output signal noise pulse at a low supply voltage level.  
         [0008]     In yet another embodiment of the present invention, a VLSI integrated circuit chip includes a low-voltage level converter. The low-voltage level converter includes an output driver PMOS FET with its drain connected to an output of the low-voltage level converter and its well grounded. The low-voltage level converter also includes an output NMOS FET with its drain connected to the output of the low-voltage level converter and its gate connected to the input of the low-voltage level converter; and an input pulldown NMOS FET that provides a negative gate voltage at its drain to the output driver PMOS FET and has its gate connected in parallel with the output NMOS FET to the input of the low-voltage level converter. The input of the low-voltage level converter receives an input pulse signal at a high supply voltage level; and provides an output signal noise pulse at a low supply voltage level.  
         [0009]     In a further embodiment of the present invention, a method of voltage level conversion includes the steps of: (1) connecting a drain of an output driver transistor to an output of a low-voltage level converter; (2) connecting a drain of an output transistor to the output of the low-voltage level converter; (3) connecting a drain of an input pulldown transistor to a gate of the output driver transistor to provide a negative gate voltage to the output driver transistor; and (4) applying an input pulse to a gate of the input pulldown transistor and a gate of the output transistor so that an output signal noise pulse is provided at the output of the low-voltage level converter at a lower voltage than that of the input pulse.  
         [0010]     In a still further embodiment of the present invention, a means for low-voltage level down converting a voltage pulse includes a means for driving a load; and a means for providing a pulldown gate voltage to the means for driving a load. The pulldown gate voltage increases the current drive of the means for driving a load and decreases switching time of the means for driving a load.  
         [0011]     These and other features, aspects and advantages of the present invention will become better understood with reference to the following drawings, description and claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a voltage-time graph of transient response for a prior art level converter circuit;  
         [0013]      FIG. 2  is a system block diagram of an on-chip test system in accordance with one embodiment of the present invention;  
         [0014]      FIG. 3  is a circuit diagram for a low-voltage level converter circuit in accordance with one embodiment of the present invention;  
         [0015]      FIG. 4  is a graph showing simulation results for the converter circuit of  FIG. 3 ;  
         [0016]      FIG. 5  is a graph showing gate and output voltages for the converter circuit of  FIG. 3 ;  
         [0017]      FIG. 6  is a graph showing simulation results under alternative conditions for the converter circuit of  FIG. 3 ; and  
         [0018]      FIG. 7  is a flowchart of a method for low-voltage level conversion in accordance with one embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     The following detailed description is of the best currently contemplated modes of carrying out the invention. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention, since the scope of the invention is best defined by the appended claims.  
         [0020]     Broadly, the present invention provides low-voltage level down conversion with very low voltage operation, which may be especially suited for operation in very large scale integrated (VLSI) circuit chips. One embodiment may provide on-chip test circuitry that can operate at very low voltages, e.g., 300-450 millivolts (mV) with a relatively high transistor threshold voltage (400-500 mV). In one embodiment, the low voltage level converter converts an input signal level from a high supply voltage level to a lower supply voltage level where the lower supply voltage level can be very close to the threshold voltage of the output driver without significant degradation in performance, e.g., increases in rise time of the output pulse or inability to drive the load.  
         [0021]     One embodiment differs, for example, from prior art by using a separate (i.e., not present in the prior art) NMOS (negative metal-oxide semiconductor) input transistor to pull the gate of the output PMOS (positive metal-oxide semiconductor) transistor down (e.g., negative) using the input signal to the transistor. Negative gate voltage may provide more current drive. For example, using normal gate voltage of zero volts, current drive for the output PMOS may be 400 to 500 micro-amps maximum. Using a negative gate voltage may provide more current drive. As a result, negative gate voltage may allow the transistor to switch (e.g., from off to on) much faster. Therefore, the higher switching speed and the additional current drive may improve—decrease—the rise time of the circuit&#39;s output pulse.  
         [0022]     Also novel in addition to the use of the extra input pulldown NMOS transistor is the combination of using the extra input pulldown NMOS transistor that lowers the gate voltage of the output PMOS transistor along with lowering the threshold voltage (e.g., the voltage required to switch the transistor on) of the output PMOS transistor. For example, threshold voltage of the output PMOS transistor may be lowered by connecting the well of the output PMOS transistor to ground. Lowering the threshold voltage of the output PMOS transistor can help the current drive and provide a faster transition (decreased rise time). In one embodiment, the gate of the output PMOS may be pulled down to a negative voltage through the Miller effect between the extra pulldown NMOS transistor and the output PMOS, the circuit being connected so that the Miller effect of both the output PMOS transistor and the extra pulldown NMOS transistor may be in the same direction so that the only coupling effect that affects the output transition may be that of the output NMOS transistor—resulting in a small coupling effect and short rise time. Thus, one embodiment turns Miller effect to advantage in contrast to prior art circuits where Miller effect works only to disadvantage. In summary, an embodiment of the inventive circuit may do two things compared to a conventional inverter circuit: (1) Miller effect coupling of the output to input may be almost eliminated so there may be no negative dip in the output pulse; and (2) the output pulse may have a shorter rise time because the output PMOS transistor may have a much faster switching speed.  
         [0023]     In addition, the converter circuit illustrated, for example, in  FIG. 3  may be unusual and counterintuitive because when input is HIGH there may be a direct current (DC) path between the output PMOS transistor and the output NMOS transistor from supply to ground. It is not usual in CMOS (complementary metal-oxide semiconductor) design to have a direct path between supply and ground. For the applications involving a special circuit used only for testing, however, the test circuits have a short period of operation and are turned off during normal operation of the chip so that the level converter shown in  FIG. 3  may be used for such an application even though the configuration is unconventional.  
         [0024]      FIG. 2  illustrates an exemplary on-chip test system  200  for a VLSI integrated circuit chip  202  in accordance with an embodiment of the present invention. The on-chip test system  200  may be used, for example, to generate a noise pulse to test the noise margin of CMOS circuits on chip  202 . Circuit chip  202  may be a VLSI circuit used for a modem (modulator-demodulator) chip, for example, used to digitally encode and decode wireless signals for a mobile phone. The device under test  204  may be, for example, the entire system embodied by the chip  202 —such as the modem in the case of a modem chip—or may be a subsystem of the chip  202 —such as a modulator in the case of a modem chip. On-chip test system  200  may include a pulse generator  206 , which may generate a square wave pulse input signal  207  applied at the input of low-voltage level converter  208 . Taking the square wave pulse input signal  207  as input, low-voltage level converter  208  may produce a noise pulse  209  as output signal. Low-voltage level converter  208  may convert an input pulse, e.g., square wave pulse input signal  207 , having a nominal level of 1.2 Volts (V), to an output pulse—such as noise pulse  209 —having a nominal level in the range of 300-400 mV and having a short enough rise time to reproduce a substantially square wave output from a square wave input. For example, an output wave form such as that of output pulse  102 , shown in  FIG. 1 , having a long rise time  108  and pronounced coupling effect  112  to the input pulse is not useful as a noise pulse  209  output of low-voltage level converter  208  for testing noise margin of CMOS circuits on chip  202  as practiced using on-chip test system  200 . The noise pulse  209  output of converter  208  may be injected at various points in the circuit of device under test  204  depending on the specific nature and specifications of device  204 . Device  204  may be connected from various points in the circuit of device  204  to monitor and measure various parameters—such as circuit voltages and currents—and depending on the specific nature and specifications of device  204  the measurements may be used to provide a result of the test, indicated, for example, as pass/fail result  210  in  FIG. 2 .  
         [0025]      FIG. 3  shows a low-voltage level converter  208  according to one embodiment. Low-voltage level converter  208  may be implemented using CMOS fabrication techniques on a VLSI chip—such as VLSI integrated circuit chip  202 . Converter  208  may include a “top” output driver transistor  212 , which may be a PMOS field effect transistor (FET) as shown in  FIG. 3 . Converter  208  may also include a “bottom” output transistor  214 , which may be an NMOS FET as shown. Converter  208  may further include an input pulldown transistor  216 , which may be an NMOS FET as shown. Top output driver transistor  212 , bottom output transistor  214 , and input pulldown transistor  216  may be connected as shown in  FIG. 3 .  
         [0026]     Input signal  207  may be fed to converter input  218 . Converter input  218  may be connected (in parallel) both to the gate  226  of input pulldown NMOS transistor  216  and the gate  224  of bottom output NMOS transistor  214 . Both the source  236  of input pulldown NMOS transistor  216  and the source  234  of bottom output NMOS transistor  214  may be connected to ground  250  as shown in  FIG. 3 . Source  232  of top output driver PMOS transistor  212  may be connected to a low-voltage power supply providing supply voltage V dd     —     noise    260 . For example, a high-voltage power supply for chip  202  may nominally provide between about 1.0 to 1.5 V, while the low-voltage power supply for chip  202  may nominally provide between about 300 mV to 500 mV. The drain  242  of top output driver PMOS transistor  212  may be connected to output  220  and the drain  244  of bottom output NMOS transistor  214  also may be connected to output  220 . Output  220  may provide output noise pulse signal  209  to a load—such as device under test  204 .  
         [0027]     The drain  246  of input pulldown NMOS transistor  216  may be connected to the gate  222  top output driver PMOS transistor  212 . In operation of test system  200 , when input pulse  207  goes LOW , the connection of drain  246  to gate  222  may provide a negative voltage at gate  222 , which may, for example, increase the current drive and switching speed of top output driver PMOS transistor  212 . The well  252  of top output driver PMOS transistor  212  may be connected to ground  250 . In operation of test system  200 , the connection of well  252  to ground  250 , for example—in contrast to a more conventional connection of well  252  to the supply voltage V dd     —     noise    260 —may lower the threshold voltage of top output driver PMOS transistor  212  and also increase the current drive and switching speed of top output driver PMOS transistor  212 .  
         [0028]     Top output driver PMOS transistor  212  may have an intrinsic gate-to-drain capacitance Cgdp, which, on account of the well-known Miller effect, may be referred to as Miller capacitance  262 . Likewise, bottom output NMOS transistor  214  may have an intrinsic gate-to-drain capacitance Cgdn, Miller capacitance  264 ; and input pulldown NMOS transistor  216  may have an intrinsic gate-to-drain capacitance Cgdi, Miller capacitance  266 . In operation of test system  200 , the connection of drain  246  to gate  222  may couple the effect of Miller capacitance  266  to the gate  222  of output driver PMOS transistor  212  so that, for example, when input pulse  207  goes LOW, the gate  222  of the output driver PMOS transistor  212  may be pulled down to a negative voltage through the Miller effect (Cgdi  266 ) between the extra input pulldown NMOS transistor  216  and the output driver PMOS transistor  212 . Miller effect of both the output PMOS (Cgdp  262 ) and the extra input pulldown NMOS (Cgdi  266 ) transistors may be in the same direction so that the only Miller effect that affects the output  220  transition may be that of the output NMOS transistor (Cgdn  264 ). Thus, coupling effect (see  FIGS. 4 through 6 ) becomes negligible (e.g., less than about 30 mV compared to prior art coupling effects ranging from about 100 to 200 mV). The transistor  214  may be made small enough so that the coupling capacitance  264  effect on the output is minimal.  
         [0029]      FIG. 4  shows transient response simulation results using a SPICE (Simulation Program with Integrated Circuit Emphasis) model for the converter circuit  208  of  FIG. 3 . Simulation may be performed, for example, using parameters V dd  (high-voltage power supply for chip  202 )=1.08V; V dd     —     noise  (supply voltage  260 )=350 mV, and a load connected at output  220 , specified in terms of load capacitance as C L =8 femtoFarads (fF). Graph  400  shows voltage in millivolts (m) on the ordinate, against time, shown in nanoseconds (n)on the abscissa. Graph  400  shows output pulse  209  for comparison on the same graph with input pulse  207 . Also shown for comparison is non-inverted input pulse  406 ; input pulse  207  may be a result of non-inverted input pulse  406 . Output pulse rise time  416  may be seen to be approximately 350 pico seconds (ps) or about 0.35 nanoseconds. Coupling effect  412  may be seen to be less than approximately 30 millivolts.  
         [0030]      FIG. 5  shows gate and output voltages for a low-voltage level converter  208  such as that illustrated in  FIG. 3 . Graph  500  shows voltage in millivolts (m) on the ordinate, against time, shown in nanoseconds (n) on the abscissa. Graph  500  shows output pulse  209  for comparison on the same graph with the corresponding voltage at gate  222  of top output driver PMOS transistor  212 , referred to as gate voltage  522 .  FIG. 5  shows that the negative gate voltage  522  resulting from Miller effect between the extra pulldown NMOS transistor  216  and the output PMOS driver transistor  212  results in approximately 150 mV. This result may be in a boosted PMOS current drive, for example, achieved by providing the negative gate voltage  522  or by connecting the well of the output driver PMOS transistor  212  to ground  250 , or combination of both. As a result, a significant reduction in rise time  516  (to approximately 350 ps as shown in  FIG. 5 ) of the noise pulse  209  may be achieved. Also, coupling effect  512  may be seen in  FIG. 5  to be less than approximately 30 millivolts.  
         [0031]      FIG. 6  shows transient response simulation results using a SPICE model for the converter circuit  208  of  FIG. 3  using alternative parameters than those used in  FIG. 4 . Simulation may be performed, for example, using parameters V dd  (high-voltage power supply for chip  202 )=1.08V; V dd     —     noise  (supply voltage  260 )=500 mV, and a load connected at output  220 , having load capacitance C L =8 fF. Graph  600  shows voltage in millivolts (m) on the ordinate, against time, shown in nanoseconds (n) on the abscissa. Graph  600  shows output pulse  209  for comparison on the same graph with input pulse  207 . Also shown for comparison is non-inverted input pulse  606 ; input pulse  207  may be a result of non-inverted input pulse  606 . Output pulse rise time  616  may be seen to be approximately 150 picoseconds (ps). Coupling effect  612  may be seen to be negligible relative to the scale of graph  600 , e.g., less than 10 milliVolts.  
         [0032]      FIG. 7  is a flowchart illustrating a method  700  for low-voltage level conversion in accordance with one embodiment of the present invention. Method  700  may include a step  702  of applying an input pulse—such as square wave pulse input signal  207 —from a pulse generator (e.g., pulse generator  206 ) at a high supply voltage level, for example, one that may be nominally between 1.0 to 1.5 V from a multiple-supply voltage system that may also supply a low supply voltage level nominally between 300 to 500 mV. Method  700  may also include connecting an output driver transistor—such as output driver PMOS FET transistor  212 —at step  704 . Step  704  may include, for example, connecting the drain  242  of output driver transistor  212  to output  220  of low-voltage level converter circuit  208 . Step  704  may also include, for example, connecting the well  252  of the output driver transistor  212  to ground  250 . In addition, step  704  may include, for example, connecting the source  232  of the output driver transistor  212  to a low supply voltage level—such as supply voltage V dd     —     noise . 260 .  
         [0033]     Method  700  may also include a step  706  of connecting the drain of an output transistor—such as drain  244  of bottom output NMOS FET transistor  214 —to the output  220  of the low-voltage level converter  208 . Step  708  may include connecting the drain of an extra input pulldown transistor—such as drain  246  of input pulldown NMOS FET transistor  216 —to the gate of the output driver transistor (e.g., gate  222  of output driver PMOS FET transistor  212 ) to provide a negative gate voltage  522  to the output driver PMOS transistor  212 . Method  700  may further include step  710  of applying the input pulse  207  in parallel both to the gate  226  of the input pulldown NMOS transistor  216  and the gate  224  of the output NMOS transistor  214  so that an output signal noise pulse—such as output signal noise pulse  209  having a short rise time and negligible coupling effect as shown, for example, in  FIGS. 4 through 6 —may be provided at the output  220  of the low-voltage level converter  208  at a lower voltage (e.g. low supply voltage level such as supply voltage  260 ) than that of the input pulse (e.g. high supply voltage level V dd , such as nominal 1.2 V). A step  712  of driving a load with the output signal noise pulse  209 , for example, the load being a device under test  204 , may also be included in method  700 .  
         [0034]     It should be understood, of course, that the foregoing relates to exemplary embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.