Abstract:
A system and method for multiplexing an integrated circuit pin include a plurality of registers for storing bit values; a plurality of functions to be multiplexed on receiving the bit values; a decoding logic for decoding the bit values for selecting at least one of the functions; a plurality of pads connected to the plurality of functions and the decoding logic; and external pin/pins acting as inputs/outputs for the selected functionality depending upon the bit values.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to method and apparatus for multiplexing an integrated circuit pin.  
         [0003]     2. Description of the Related Art  
         [0004]     In the field of Application Specific Integrated Circuit (ASIC), there are a number of applications, which are yet to be explored. As a result of this, manufacturers of micro processor/controller have found it necessary to design their chips in a way so as to target more than one application (or customer) with a single die and simultaneously reduce the cost of manufacturing, maximize profit and reduce time to market.  
         [0005]     Conventional IC devices are designed with dedicated pin configuration, i.e. each pin is dedicated to a specific functionality only. This certainly imposes a problem for IC devices having a low pin count.  
         [0006]     U.S. Pat. No. 5,686,844 discloses two embodiments of the same invention that use a memory device to store information to configure the IC device pin. Input/Output logic is also used in both the embodiments in order to transfer data to and from the IC device pin when the IC device pin is configured as a digital I/O pin.  
         [0007]      FIG. 1  shows a system for configuring IC device pins as a block input pin or as a digital I/O pin as described in the above patent. The system  10  may be used for any type of IC device  12  that requires a clock input pin and a digital I/O pin such as a PIC16C5X type micro-controller produced by MICROCHIP TECHNOLOGY, INC.  
         [0008]     The system  10  comprises an IC device pin  14 . A memory system  16  is provided for storing a value to configure the IC device pin  14  as a clock input pin and for storing a value to configure the IC device pin  14  as a digital I/O pin. The memory system  16  is a nonvolatile memory bit. The memory system  16  may also use a volatile memory bit. However, the volatile memory bit must have a set known value upon power up of the system  10 .  
         [0009]     Input/Output (I/O) logic  18  is coupled to an output  16 B of the memory system  16 . The I/O logic  18  is used for writing data out of the IC device pin  14  and for reading data in from the IC device pin  14  when the IC device pin  14  is configured as a digital I/O pin, the data is transferred to and from the I/O logic  18  through a data bus  20  which is directly coupled to the I/O logic  18 .  
         [0010]     Clock logic gate circuitry  22  is coupled to the output  16 B of the memory system  16  and to the IC device pin  14 . The clock logic gate circuitry  22  is used for outputting a clock signal when the IC device pin  14  is configured as a clock input pin. The clock logic circuitry is comprised of an AND gate  22 A having an input coupled to the output  16 B of the memory system  16  and having another input coupled to the IC device pin  14 , and an OR gate  22 B having an input coupled to an output of the AND gate  22 A and another input  23  coupled to other clock sources that may be internal or external to the IC device  12 .  
         [0011]     The memory system  16  receives program data through its input  16 A. The program data will set the IC device pin  14  as a clock input pin or as a digital I/O pin. The program data will either be a high value “1” or a low value “0”. When a “1” is inputted to the memory system  16 , the IC device pin  14  is configured as a clock input pin. The memory system  16  will output a “1” at its output  16 B and the inverter  24  will invert the high signal “1” signal to a low signal “0”. The low signal “0” will in turn disable the I/O logic  18 . With the I/O logic  18  disabled, when the IC device pin  14  goes high, the output of the AND gate  22 A will go high causing the output of the OR gate  22 B to go high. Thus, an external clock signal that is coupled to the IC device pin  14  will be outputted through the OR gate  22 B to components in the IC device  12  that requires a clock signal to operate. Another input  23  to the OR gate  22 B is coupled to other clock source signals. These other clock source signals may be internal or external to the IC device  12 . When the IC device pin  14  is configured as a digital I/O pin, the clock logic gate circuitry  22  may still send out a clock signal. However, the clock signal sent from the OR gate  22 B has to come from the one of the other clock source signals that may be sent through input  24  of the OR gate  22 B. For most IC devices  12  and applications, only one clock source is active.  
         [0012]     When a low value “0” is inputted to the memory system  16 , the IC device pin  14  is configured as a digital I/O pin. The memory system  16  will output a low signal “0” at its output  16 B and the inverter  24  will invert the low signal “0” signal to a high signal “1”. The high signal “1” will enable the I/O logic  18 .  
         [0013]     The US patent as described above explains how to reuse one pin for different functionalities such as reset, clock or general-purpose I/O functionalities. It also describes how to share a single I/O for either reset/clock functionality or general I/O functionality by using a single configuration bit to configure the device into either of the functionalities.  
         [0014]     While this idea is very useful in the sense that same die can be marketed as two devices (with Reset/Clock and with I/O functionality), it cannot be used for a normal package where both reset/clock and general I/O are present on dedicated pins. To fulfill this requirement, a different die is required as said patent uses a single I/O pad for this multiplexing. This amounts to again a new product design &amp; testing cycle.  
         [0015]     Also, when used for Reset functionality, the pad behaves as an input pin only. This limits the application, as the IC device cannot reset external devices.  
         [0016]     Therefore, a need exists to provide a method and system in which the same die can be used for different configurations.  
       BRIEF SUMMARY OF THE INVENTION  
       [0017]     One embodiment of the present invention provides a method and system for multiplexing an integrated circuit pin, which uses the same die with different packaging namely normal pin count and optimized pin count.  
         [0018]     One embodiment provides flexibility to the user as the configuration can also be done with programmable bits, which are accessible through application software.  
         [0019]     One embodiment of the invention configures the device for specific functionality at the output without internally disabling other functionalities.  
         [0020]     One embodiment of the invention uses option/register/mask option bits to allow external pin to switch between two different peripheral functions thus providing better utilization of peripherals and pins in a micro controller.  
         [0021]     One embodiment of the invention reduces the time to market and cost thereby increasing profit.  
         [0022]     One embodiment of the invention provides a system for multiplexing an integrated circuit pin including:  
         [0023]     a plurality of registers for storing bit values;  
         [0024]     a plurality of functions to be multiplexed on receiving the bit values;  
         [0025]     a decoding logic for decoding the bit values for selecting desired functionalities;  
         [0026]     a plurality of pads connected to the plurality of functions and the decoding logic; and  
         [0027]     external pin/pins acting as inputs/outputs for the selected functionality depending upon said bit values.  
         [0028]     The number of the plurality of registers used depends upon the number of functions to be multiplexed.  
         [0029]     The bit values used include hardware or software programmed bits.  
         [0030]     The plurality of functions exclude Vcc and ground pins of the integrated circuit.  
         [0031]     The decoding logic is a combination of logic gates depending upon the number of the functions to enable the pad/pads and functions.  
         [0032]     The external pin/pins selection depends upon optimized pin package or normal pin package.  
         [0033]     The decoding logic to decide external pin/pins to act as inputs/outputs includes:  
         [0034]     a pad containing desired functionality;  
         [0035]     a logic connected to said pad and including few logic gates and registers for performing said desired functions;  
         [0036]     at least two registers connected to said logic to enable/disable said pad; and  
         [0037]     a plurality of logic gates connected to said registers; and  
         [0038]     an AND gate receiving inputs from said registers for providing a signal to said logic to make said external pin/pins to act as inputs/outputs.  
         [0039]     A method for multiplexing an integrated circuit pin includes:  
         [0040]     storing bit values in a plurality of registers;  
         [0041]     multiplexing the plurality of functions on receiving said bit values;  
         [0042]     decoding said bit values for selecting desired functionalities in decoding logic;  
         [0043]     connecting a plurality of pads to said plurality of functions and said decoding logic; and  
         [0044]     deciding external pin/pins to act as inputs/outputs for said selected functionality depending upon said bit values.  
         [0045]     Therefore, at least one embodiment of the invention provides a method and system in which the same die can be used for different configurations. With different bonding, this can be easily achieved on a single die, thus reducing cost of extra design &amp; testing.  
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)  
       [0046]     The invention will now be described with reference to and as illustrated in the accompanying drawings.  
         [0047]      FIG. 1  shows the prior art.  
         [0048]      FIG. 2  shows a block diagram of one embodiment of the instant invention in optimized mode.  
         [0049]      FIG. 3  shows a block diagram of one embodiment of the instant invention in normal mode.  
         [0050]      FIG. 4  shows a truth table that gives several options to use a single die in different configurations using two bits.  
         [0051]      FIG. 5  expands the internal structure of the die for two-bit implementation in accordance with one embodiment of the invention.  
         [0052]      FIG. 6  shows normal pin package of the same die for two-bit implementation in accordance with one embodiment of the invention.  
         [0053]      FIG. 7  shows detailed view of the interface between Reset pad and Reset function block in accordance with one embodiment of the invention.  
         [0054]      FIG. 8  shows detailed view of the interface between general-purpose IO pad and general-purpose functional block in accordance with one embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0055]     In one embodiment of the present invention, in one package one external pin on which two or more functionalities can be multiplexed with the help of n configuration bits and in another package all the functions are available on different external pins. The configuration bits enable or disable the associated pad of the functional circuits instead of the functional circuit itself. So while only one pad is connected to the external pin, the output of any functional circuit can be used inside the chip for internal operation/processing. This invention stresses specifically on the availability of the die for different packages, which saves cost and time for designing different dies for different packages.  
         [0056]      FIG. 2  shows the block diagram of one embodiment of the instant invention in the optimized mode. It comprises registers  25 [ 1 :N], functional block ( 26 ), decoding logic ( 27 ), pads  28 [ 1 :N] and external pin ( 29 ). In this embodiment, a number of functions contained in the functional block ( 26 ) are to be multiplexed together. Depending upon the number of functions to be multiplexed, corresponding numbers of registers  25 [ 1 :N] are configured to store corresponding bits. Thereafter depending upon bit combination, a particular pad is selected from the pads  28 [ 1 :N]. The selected pad is thus enabled to provide output to the external pin ( 29 ). Said decoding of bit combinations is done by the decoding logic ( 27 ), which is a combination of logic gates.  
         [0057]      FIG. 3  shows the block diagram of another embodiment of the instant invention in the normal mode. It comprises-registers  30 [ 1 :N], functional block ( 31 ), decoding logic ( 32 ), pads  33 [ 1 :N] and external pins  34 [ 1 :N]. In this embodiment, n number of functions can be obtained at their corresponding external pins  34 [ 1 :N] using the same die as used in the first embodiment. The numbers of registers  30 [ 1 :N] used to store bits depends upon the number of functions required at the output. The decoding logic is a combination of logic gates that decodes the bit combination. The pads  33 [ 1 :N] are selected by the decoding logic and the corresponding function is transferred to the corresponding external pin  34 [ 1 :N].  
         [0058]     The invention will now be explained with the help of an example employing reset and general-purpose input/output pin to be multiplexed. Three configurations can be obtained for the two functionalities namely, only reset pad is enabled, only general input/output pad is enabled and both the pads are enabled, thereby employing two bits for said three configurations.  
         [0059]      FIG. 4  shows a truth table that gives options to use a single die in said three different configurations using two bits. When BIT 21  and BIT 22  are “00”, it shows the default state of the device at power on, selecting optimized pin package with reset pad enabled while disabling the general-purpose input/output pad at the external pin.  
         [0060]     Similarly when BIT 21  and BIT 22  are “01”, it shows the state of the device after the program execution starts, selecting optimized pin package with reset pad disabled while enabling general-purpose input/output pad. A unique feature is incorporated in the illustrated embodiment of the instant invention, namely if the customer wants to switch from one pin to the other pin once his work is completed, he can change the bit values. For example, after reset if customer desires to use external pin as general purpose IO pin then he should write “01” on BIT 21  and BIT 22 . This would then enable general-purpose IO pad while disabling the reset pad.  
         [0061]     When BIT 21  and BIT 22  contain “10” or “11” then the same die is used in normal pin package. This would enable two external pins i.e. one for reset pad while other for general-purpose input/output pad.  
         [0062]     It is thus clear that when BIT 21  and BIT 22  are “00” or “01” optimized pin package is configured while for other bit combinations normal pin package is configured.  
         [0063]      FIG. 5  shows the internal structure of the die using a common external pin ( 59 ).  
         [0064]     In this figure we are focusing on optimized pin package containing two pads ( 57  &amp;  58 ), one external pin ( 59 ) and associated circuitry containing one reset function block ( 55 ), one General Purpose function block ( 56 ) and two option registers  51 ,  52  that store respective mask option bits. Reset pad ( 57 ) and general purpose input output pad ( 58 ) are double bonded, i.e. bonded to same external pin ( 59 ) of the chip. Internally, reset pad is connected to reset functionality and general-purpose input/output pad is connected to any general-purpose function like Timer, UART, SPI, SCI and the like.  
         [0065]     The respective outputs of the option registers  51 ,  52  are connected to the respective chip selects CS of the two pads via a combinational circuit of an AND gate ( 53 ) and an OR gate ( 54 ) respectively, which means only one pad can be selected at a time and its corresponding function is also selected which is finally connected to the external pin ( 59 ).  
         [0066]     The advantage in doing so is that if some customer does not want to use an external reset pin then he has the flexibility to use that pin as a general purpose IO pin instead of leaving that pin unused and vice-versa in one package. Also the customer can also use both the functions in another package. Thus using the same logic with different packaging provides this functionality, thereby reducing time-to-market. In the former one, in-place of external reset, the user will use an integrated internal reset by POR (Power On Reset) and LVD (Low Voltage Detector) (as described in the latter part of the description) into the micro controller.  
         [0067]     The default state at power-on of the circuit is the reset state as both non-volatile/memory bits are “00” (see  FIG. 4 ) so the bits stored and output by the registers  51  and  52  are “00” which make the signals output by the logic gates  53 ,  54  equal to “0” and “1” respectively thereby selecting the reset pad  57 . When software writes “01” in these registers  53 ,  54  (see  FIG. 4 ) then it makes the output of the AND gate  53  equal to “1” and the output of the OR gate equal to “0” thereby selecting general purpose IO pad  58 . This means that after start-up general-purpose input/output functionality cannot be used and only reset functionality is alive at the external pin while internal processing can still continue.  
         [0068]      FIG. 6  shows normal pin package containing two pads ( 67  &amp;  68 ), two pins ( 69  &amp;  70 ) and associated circuitry containing one reset function block ( 63 ), one general-purpose function block ( 64 ) and two option registers  61 ,  62  that store respective mask option bits. This package is provided for users who want to use both functions simultaneously. After power on, the circuit is in the reset state, which is the default state. After application program execution, the two configuration bits in the registers  61 ,  62  will have either “10” or “11” written (see  FIG. 4 ) on them making the signals output by the logic gates  65 ,  66  equal to “0”, thereby enabling both of the pads.  
         [0069]      FIG. 7  gives the detailed view of an interface  70  between a reset pad  71  and a reset function block  72 . The reset function block  72  includes a Power On Reset block (POR)  73 , a Low Voltage Detector block (LVD)  74 , a Watch Dog Timer (WDG)  75 , and an Illegal Opcode Block (ICODE)  76 . The interface  70  includes bit registers  77 ,  78 , and a few logic gates described below.  
         [0070]     The Power On Reset block (POR)  73  programs the programmable device in the known state during power on to ensure proper functionality. The POR  73  asserts a reset signal por_rst when the supply voltage rises and de-asserts the signal when the supply voltage reaches to a predetermined level.  
         [0071]     The Low Voltage Detector block (LVD)  74  ensures the correct operation of the micro-controller by providing reset signal lvd_rst when the power supply goes below a pre-determined level.  
         [0072]     The Watch Dog Timer (WDG)  75  ensures the correct execution of the application program by refreshing the watchdog timer. If there is any problem during execution then the WDG register does not gets refreshed and after certain time it generates a reset signal.  
         [0073]     The Illegal Opcode Block (ICODE) detects if any illegal opcode is encountered during execution of the application program. If an illegal opcode is encountered, then it generates a reset signal. This is very common in micro-controller applications due to large interferences with external environment.  
         [0074]     The bit registers  77 ,  78  can be programmed through software. The output of these bit registers form different configurations that are used to disable the reset pad  71  from the circuit or to connect the general-purpose IO pad ( FIG. 8 ) or to connect both of the pads. The bits in the bit registers  77 ,  78  can be option bits if it is an EEPROM or FLASH device or it can be a mask option bits for the ROM device.  
         [0075]     Different options provide flexibility to user or IC manufacturer. If these are register bits then the user/customer has the flexibility to use any of the above pads by only programming in the application program. If these are option bits or mask option bits then it provides the flexibility to IC manufacturer to reconfigure an external pin as reset pin or general-purpose IO pin and sell the device accordingly.  
         [0076]     The bit output signals of the bit registers  77 ,  78  are fed as inputs to an AND gate  79 . The output  80  of this gate  79  serves as one input to an AND gate  81  and also as a select signal of a MUX  82 .  
         [0077]     The interface  70  includes a flip-flop  83  with a reset pin connected to an output  84  of the MUX  82 . When the output  84  of the MUX  82  is “0”, it resets the flip-flop  83 , which completes the circuitry of micro-controller thereby, resetting all the peripherals  85 . After reset, when the system clock bit becomes “1” it de-asserts the reset of all the peripherals.  
         [0078]     The reset pad  71  contains a pad  86  connected to the external pin of the chip as shown in  FIGS. 5 and 6 . An external reset (with low reset state), received from the pad  86 , is applied to a filter  87 . The function of the filter  87  is to remove glitches on the reset coming from external sources so as to remove spurious reset or false reset. It has some fixed time window below which it will not detect any change on its input. The output of the filter  87  goes to a Schmitt trigger  88  and the output of this Schmitt trigger goes to the MUX  82  as one of its inputs. Reset pad  71  also contains a pull up PMOS transistor  89  that provides a weak pull up to the reset signal if the reset pin is unused from the external environment to avoid false reset. Also it contains an NMOS pull down transistor  90  of which gate is connected to the output of the AND gate  81  and thus creates the reset loop circuitry.  
         [0079]     Before discussing the reset loop it is pertinent to mention that the interface  70  includes a TEMPO block  91  that provides a fixed temporization delay (or stretches) to the reset signal coming from any of the POR, LVD, WDG, and ICODE blocks so as to provide stabilization to the internal/external oscillator circuitry.  
         [0080]     Reset loop circuitry traverses the path from POR, LVD, WDG, and ICODE through OR gates  92 ,  93 ,  94  to the TEMPO block  91 , AND gate  81 , and the gate of the pull-down transistor  90 .  
         [0081]     The interface  70  also includes inverters  95 ,  96  connected respectively between the POR  73  and the bit registers  77 ,  78 ; OR gates  97 ,  98  connected respectively between the output and data input of the bit registers  77 ,  78 ; and an inverter  99  connected between the TEMPO  91  and the MUX  82 .  
         [0082]      FIG. 8  provides a detailed view of an interface  100  between a general-purpose IO pad  101  and a general-purpose functional block  102 . The interface  100  includes bit registers  103 ,  104  storing configuration bits. The pad  101  contains a pin  105  bonded to the external pin of the chip (as shown in  FIGS. 5 and 6 ), a pull up resistor  106 , a pull down resistor  107 , a limiting resistor  108 , a Schmitt trigger  109 , and a tri-state buffer  110 . The input of Schmitt trigger  109  is received from the pin  105 , which has an enable signal “trigen” coming from the general-purpose functional block  102  via an AND gate  111 , and an output “zout” connected to the general-purpose functional block. The input of the tristate buffer  110  is a “data” signal while it receives an enable signal “en” from the general-purpose functional block  102  via a NAND gate  112  and outputs the data signal to the pin  105 . Other signals “pu” and “pd” are respective outputs of a NAND gate  113  and an AND gate  114  connected to the general-purpose functional block  102 . The gates  111 - 114  each have one input coming from the output  115  of an OR gate  116 . The inputs of the OR gate  116  are signals  117 ,  118  coming from the bit registers  103 ,  104 . The output of the OR gate  116  is used to enable or disable the gates that in turn enable or disable the complete pad  101 .  
         [0083]     The interface  100  also includes inverters  119 , 120  connected respectively between the POR  73  and the bit registers  103 ,  104 ; and OR gates  121 ,  122  connected respectively between the output and data input of the bit registers  103 ,  104 .  
         [0084]     Operation of the Circuit:  
         [0085]     Case 1: With Optimized Pin Package  
         [0086]     Scenario 1: Reset Pad  71  in Picture  
         [0087]     As soon as the chip is powered on, POR  73  generates a reset on signal line “por_rst”. This “por_rst” is connected to the resets of the bit registers  77 ,  78 , so it resets those registers, which is their default state. The outputs of these bit registers  77 ,  78  act as input to the AND gate  79 . The output  80  of the AND gate  79  is connected to the select signal of the MUX  82  and to the input of the AND gate  81 . During reset both of the outputs of the bit registers  77 ,  78  are “0” therefore signal  80  is “0”. The MUX  82  passes the signal coming from the pin  86  of the reset pad  71  to reset the register  83 , which in turn provides a reset to all the peripherals  85 .  
         [0088]     In the default state, the reset pad  71  is in function and at the same time the bit registers  103 ,  104  of  FIG. 8  output “00” which makes signal  115  equal to “0” which disables all the gates at the input of IO pad  101 , thus disables the IO pad from the picture.  
         [0089]     Also, the reset generated by POR  73  during power on travels through the OR gates  92 ,  93 , thereafter through the TEMPO  91  and the AND gate  81  (enabled by signal  80  from the AND gate  79 ) to the gate of the pull down transistor  90  which pulls down the pin  86  thereby providing reset to external peripherals. Similarly it goes through the filter  87 , the Schmitt trigger  88 , the MUX  82 , and the flip-flop  83 , thereby resetting all the peripherals  85  and completing the reset loop.  
         [0090]     Let us now consider the reset being generated by any of the LVD  74 , WDG  75 , or ICODE  76  blocks. The signal so generated travels through one of the OR gates  92 ,  94 , OR gate  93 , and TEMPO  91 , thereafter to the AND gate  81 , transistor  90 , and pin  86  to outside as well as inside the chip through the filter  87 , Schmitt trigger  88 , and MUX  82  to the flip-flop  83 , thereby completing the reset loop.  
         [0091]     Scenario 2: General Purpose IO Pad  101  in Picture  
         [0092]     As soon as the chip is powered on, POR  73  will generate the reset signal “por_rst” which resets the bit registers  77 ,  78  giving “00” from the bit registers, thereby making  80  equal to “0”. Meanwhile reset pad  71  is connected to the external pad, which is the default state. Once the whole VDD power range is achieved after the temporization time and mode setting in the micro-controller, an application program is executed. The bits “01” are written in the bit registers  77 ,  78  respectively after execution of the application program.  
         [0093]     This bestows a value “0” from the bit register  77  and “1” from the bit register  78 , making signal  80  equal to “1” which disables the AND gate  81  and also selects other input at the MUX  82  coming from the TEMPO block  91  through inverter  99 . Due to this, the reset pad  71  is completely cut-off from the circuit. Simultaneously, signal  115  (see  FIG. 8 ) which contains a value “1” is applied to the inputs of AND  111 , NAND  112 , NAND  113 , and AND  114  gates thereby, enabling these gates and connecting the general-purpose function block to the general purpose IO pad  101 .  
         [0094]     Both the configuration bits are write-only so as to avoid any accidental resetting of the bit, which might result in resetting of the device while the application is running.  
         [0095]     Now consider the case when one of LVD  74  (during power down), WDG  75 , or ICODE  76  (illegal opcode) blocks generates a reset. The signal will loop through OR gate  92  or OR gate  94  and OR gate  93 , TEMPO  91 , inverter  99 , and MUX  82  to the flip-flop  83 , which resets all the peripherals. The device will remain operational in this mode until next power down.  
         [0096]     Finally to completely reset the chip and to come back to its default state, another POR reset should come which will reset the complete thing and the device would come to its default state.  
         [0097]     Case 2: With Normal Pin Package ( FIG. 6 )  
         [0098]     The two bit registers  61 ,  62  are programmed with any combination of “10” or “11” that makes each of the signals output by the gates  65 ,  66  equal to “0” thereby enabling both the pads  67 ,  68  connected to the external pins  69 ,  70 . Thus in this package both reset and general-purpose functions are available at the same time.  
         [0099]     The invention is capable of considerable modification, alternation and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts. While the invention is described as having application to micro-controller, it is intended to have application to other integrated circuits, including, but not limited to, any microprocessor.  
         [0100]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheetare incorporated herein by reference, in their entirety.  
         [0101]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.