Abstract:
Provided are a pin module and a universal serial bus (USB) device. The USB device includes: a substrate including a first side and a second side, the second side opposite to the first side; at least one memory chip mounted on the first side of the substrate; at least one controller chip mounted on the first side of the substrate; a plurality of first planar electrodes formed on the second side of the substrate; a plurality of second planar electrodes formed on the second side of the substrate; and a sealing material housing the memory chip, the controller chip, the first planar electrodes, and the second planar electrodes, wherein the sealing material exposes one sides of the first planar electrodes and the second planar electrodes.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     A claim of priority is made to Korean Patent Application No. 10-2010-0008601, filed on Jan. 29, 2010, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     The inventive concept relates to a pin module and a universal serial bus (USB) device, and more particularly, to a pin module providing a USB 3.0 plug for a chip on board (COB) package and a USB device including the same. 
     A USB is an interface standard used for connecting a host such as a computer with peripheral devices such as a mouse, a printer, a modem, or a speaker. Especially, since a USB implementers forum (USB-IF) recently announced USB 3.0 standard specifications, it is expected that a USB device with an improved transfer speed will be realized soon. 
     SUMMARY 
     The inventive concept provides a pin module and a universal serial bus (USB) device having corrosion resistant and mechanically reliable properties. 
     According to an aspect of the inventive concept, there is provided a Universal Serial Bus (USB) device including: a substrate including a first side and a second side, the second side being opposite to the first side; at least one memory chip mounted on the first side of the substrate; at least one controller chip mounted on the first side of the substrate; a plurality of first planar electrodes formed on the second side of the substrate; a plurality of second planar electrodes formed on the second side of the substrate; a sealing material housing the memory chip, the controller chip, the first planar electrodes, and the second planar electrodes; and a pin module providing a plurality of first pins, the first pins being respectively disposed on the second planar electrodes, wherein the sealing material exposes one side of the first planar electrodes and the second planar electrodes. 
     The pin module may comprise a fixing unit for fixing the first pins. 
     The second planar electrodes are electrically connected to a host of the USB device through the first pins. 
     The pin module may provide a space into which the substrate and the sealing material are inserted. 
     The first pins may be formed of a conductive material and the fixing unit may be formed of a nonconductive material. 
     The pin module may further include a plurality of second pins penetrating the fixing unit, the second pins being directly connected to the first pins, respectively. 
     The first pins directly may contact the second planar electrodes, respectively. 
     The first pins may not contact the second planar electrodes when the USB device is not inserted into a host and the first pins may directly contact the second planar electrodes when the USB device is inserted into the host. 
     The first planar electrodes may include: a first USB 2.0 electrode transmitting a VBUS signal; a second USB 2.0 electrode transmitting a D− signal; a third USB 2.0 electrode transmitting a D+ signal; and a fourth USB 2.0 electrode transmitting a GND signal. 
     The second planar electrodes may include: a first USB 3.0 electrode transmitting a StdA_SSRX− signal; a second USB 3.0 electrode transmitting a StdA_SSRX+ signal; a third USB 3.0 electrode transmitting a GND_DRAIN signal; a fourth USB 3.0 electrode transmitting a StdA_SSTX− signal; and a fifth USB 3.0 electrode transmitting a StdA_SSTX+ signal. 
     According to another aspect of the inventive concept, there is provided a USB device including: a package; a first planar electrode disposed on one side of the package and transmitting a VBUS signal; a second planar electrode disposed on the one side of the package and transmitting a D− signal; a third planar electrode disposed on the one side of the package and transmitting a D+ signal; a fourth planar electrode disposed on the one side of the package and transmitting a GND signal; a fifth planar electrode disposed on the one side of the package and transmitting a StdA_SSRX− signal; a sixth planar electrode disposed on the one side of the package and transmitting a StdA_SSRX+ signal; a seventh planar electrode disposed on the one side of the package and transmitting a GND_DRAIN signal; a eighth planar electrode disposed on the one side of the package and transmitting a StdA_SSTX− signal; a ninth planar electrode disposed on the one side of the package and transmitting a StdA_SSTX+ signal; and a pin module providing a plurality of pins, the pins being respectively disposed on the fifth to ninth planar electrodes. 
     The package may include: a substrate including a first side and a second side, the second side being opposite to the first side; at least one memory chip mounted on the first side of the substrate; and at least one controller chip mounted on the first side of the substrate, wherein the first to ninth planar electrodes are formed on the second side of the substrate. 
     The USB device may further include a sealing material housing the memory chip, the controller chip, and the first to ninth planar electrodes, the sealing material exposing one sides of the first to ninth planar electrodes. 
     The fifth to ninth planar electrodes may be electrically connected to a host of the USB device through the pins. 
     The plurality of pins may include: a first pin disposed on the fifth planar electrode and transmitting a StdA_SSRX− signal; a second pin disposed on the sixth planar electrode and transmitting a StdA_SSRX+ signal; a third pin disposed on the seventh planar electrode and transmitting a GND_DRAIN signal; a fourth pin disposed on the eighth planar electrode and transmitting a StdA_SSTX− signal; and a fifth pin disposed on the ninth planar electrode and transmitting a StdA_SSTX+ signal. 
     The pin module may comprise a fixing unit for fixing the pins. 
     The pin module may provide a space into which the substrate and the sealing material are inserted. 
     The first to fifth pins may be formed of a conductive material and the fixing unit may be formed of a nonconductive material. 
     According to another aspect of the inventive concept, there is provided a pin module including: a first pin transmitting a StdA_SSRX− signal; a second pin transmitting a StdA_SSRX+ signal; a third pin transmitting a GND_DRAIN signal; a fourth pin transmitting a StdA_SSTX− signal; a fifth pin transmitting a StdA_SSTX+ signal; a fixing unit fixing the first to fifth pins; and an insertion unit providing a space into which a package is inserted. 
     The first to fifth pins may be formed of a conductive material and the fixing unit may be formed of a nonconductive material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a plan view illustrating a universal serial bus (USB) device before a package and a pin module are combined according to an embodiment of the present inventive concept; 
         FIG. 2  is a plan view illustrating a USB device after a package and a pin module are combined according to an embodiment of the present inventive concept; 
         FIG. 3  is a perspective view illustrating a USB device before a package and a pin module are combined according to an embodiment of the present inventive concept; 
         FIG. 4  is a perspective view illustrating a USB device after a package and a pin module are combined according to an embodiment of the present inventive concept; 
         FIG. 5  is a cross-sectional view illustrating a USB device before a package and a pin module are combined according to an embodiment of the present inventive concept; 
         FIG. 6  is a cross-sectional view illustrating a USB device after a package and a pin module are combined according to an embodiment of the present inventive concept; 
         FIG. 7  is a partial cross-sectional view taken along the line A-A′ of  FIG. 1  and illustrates a wire-bonded chip on board (COB) package according to an embodiment of the present inventive concept; 
         FIG. 8  is a partial cross-sectional view taken along the line A-A′ of  FIG. 1  and illustrates a flip-chip-bonded COB package according to another embodiment of the present inventive concept; 
         FIG. 9  is a partial cross-sectional view taken along the line A-A′ of  FIG. 1  and illustrates a COB package where a memory chip and a controller chip are stacked and mounted on a substrate according to another embodiment of the present inventive concept; 
         FIGS. 10A and 10B  are cross-sectional views when a USB device is combined with a host according to an embodiment of the present inventive concept; 
         FIGS. 11A and 11B  are cross-sectional views when a USB device is combined with a host according to other embodiments based on the technical scope of the inventive concept; 
         FIGS. 12A and 12B  illustrate a USB device in which a package and a pin module are combined through a sliding combination method according to other embodiments based on the technical scope of the inventive concept; 
         FIG. 13  illustrates a USB device in which a package and a pin module are combined through a vertical combination method according to other embodiments based on the technical scope of the inventive concept; and 
         FIGS. 14A and 14B  illustrate a USB device according to other embodiments based on the technical scope of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Exemplary embodiments of the inventive concept will be described below in more detail with reference to the accompanying drawings. 
     The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that those of ordinary skill in the art thoroughly understand this inventive concept. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those of ordinary skill in the art. 
     In the following description, the technical terms are used only for explaining a specific exemplary embodiment while not limiting the inventive concept. The terms of a singular form may include plural forms unless referred to the contrary. The meaning of ‘comprises’ and/or ‘comprising’ specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components. As used herein, the term ‘and/or’ includes any and all combinations of one or more of the associated listed items. 
     Also, though terms like a first and a second are used to describe various members, components, regions, layers, and/or portions in various embodiments of the inventive concept, the members, components, regions, layers, and/or portions are not limited to these terms. These terms are used only to discriminate one region or layer from another region or layer. Therefore, a member, a component, a region, a layer, or a portion referred to as a first member, a first component, a first region, a first layer, or a first portion in an embodiment can be referred to as a second member, a second component, a second region, a second layer, or a second portion in another embodiment. 
     Additionally, the embodiment in the detailed description will be described with cross-sectional views as ideal exemplary views of the inventive concept. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concept are not limited to the specific shape illustrated in the exemplary views, but may include other shapes that may be created according to manufacturing processes. 
       FIGS. 1 through 6  are plan views, perspective views, and cross-sectional views illustrating a universal serial bus (USB) device  100  according to an embodiment of the present inventive concept. In more detail,  FIGS. 1 ,  3 , and  5  are a plan view, a perspective view, and a cross-sectional view of the USB device  100 , respectively, before a package  10  and a pin module  20  are combined.  FIGS. 2 ,  4 , and  6  are a plan view, a perspective view, and a cross-sectional view of the USB device  100 , respectively, after the package  10  and the pin module  20  are combined.  FIGS. 7 through 9  are cross-sectional views taken along the line A-A′ of  FIG. 1 . 
     Referring to  FIGS. 1 through 6 , the USB device  100  includes a package  10 , first to nine planar electrodes  11  to  19 , and a pin module  20  providing first to fifth pins  21  to  25 . This embodiment represents the inventive concept about the USB 3.0 standard and thus includes nine planar electrodes and five pins, but the inventive concept is not limited thereto. That is, as the USB standard changes, more or less than nine planar electrodes and more or less than five pins may be configured. 
     Referring to  FIGS. 7 through 9 , the package  10  may be a chip on board (COB) package where a semiconductor chip is directly mounted on a substrate such as a printed circuit board (PCB). In more detail, the COB package  10  may include a substrate  105 , a memory chip  110 , a controller chip  120 , a passive device  130 , and a sealing material  140 . 
     Although not illustrated in the drawings, the package  10  may be a package where a surface mount device (SMD) with a sealed semiconductor chip (not shown) or a through hole type (THT) device is mounted on a PCB. 
     A substrate  105  may include a first side and a second side opposite to the first side. The memory chip  110 , the controller chip  120 , and the passive device  130  may be mounted on the first side of the substrate  105 . In more detail, as shown in  FIGS. 7 and 8 , the memory chip  110  and the controller chip  120  may be mounted on the substrate  105  by wire bonding or flip-chip bonding. In addition, as shown in  FIG. 9 , the memory chip  110  and the controller chip  120  with a stacked structure may be mounted on the substrate  105 , and a through-silicon-via technique may be used for mutual electrical connections. 
     The sealing material  140  may seal the memory chip  110 , the controller chip  120 , the passive device  130 , and the first to ninth planar electrodes  11  to  19 . The sealing material  140  may include an epoxy molding compound (EMC), underfill, and glop-top. 
     The memory chip  110  may be a flash memory chip and the controller chip  120  may be configured to control the flash memory chip. The passive device  130  may include electronic components (such as a resistor, an inductor, and a capacitor) and a meander metal line (not shown). The first to ninth planar electrodes  11  to  19  may be formed on the second side of the substrate  105 . The sealing material may expose one side of the first to ninth planar electrodes  11  to  19 . 
     Referring to  FIGS. 1 to 6  again, the first to fourth planar electrodes  11  to  14  may transmit signals based on the USB 2.0 standard. In more detail, the first planar electrode  11  is formed on one side of the package  10  and is configured to transmit a VBUS signal of the USB 2.0 standard. The second planar electrode  12  is formed on the one side of the package  10  and is configured to transmit a D− signal of the USB 2.0 standard. The third planar electrode  13  is formed on the one side of the package  10  and is configured to transmit a D+ signal of the USB 2.0 standard. The fourth planar electrode  14  is formed on the one side of the package  10  and is configured to transmit a GND signal of the USB 2.0 standard. 
     The fifth to ninth planar electrodes  15  to  19  may transmit signals based on the USB 3.0 standard. In more detail, the fifth planar electrode  15  is formed on the one side of the package  10  and is configured to transmit a StdA_SSRX− signal of the USB 3.0 standard. The sixth planar electrode  16  is formed on the one side of the package  10  and is configured to transmit a StdA_SSRX+ signal of the USB 3.0 standard. The seventh planar electrode  17  is formed on the one side of the package  10  and is configured to transmit a GND_DRAIN signal of the USB 3.0 standard. The eighth planar electrode  18  is formed on the one side of the package  10  and is configured to transmit a StdA_SSTX− signal of the USB 3.0 standard. The ninth planar electrode  19  is formed on the one side of the package  10  and is configured to transmit a StdA_SSTX+ signal of the USB 3.0 standard. 
     The pin module  20  may include first to fifth pins  21  to  25 , a fixing unit  33 , and an insertion unit  35 . The pin module  20  may be combined with the package  10  such that the USB device  100  including a plug for the USB 3.0 standard may be formed. 
     The fifth to ninth pins  21  to  25  may transmit signals based on the USB 3.0 standard. The first to fifth pins  21  to  25  may be formed of a conductive material. In more detail, the first pin  21  may be configured to transmit a StdA_SSRX− signal of the USB 3.0 standard. The second pin  22  may be configured to transmit a StdA_SSRX+ signal of the USB 3.0 standard. The third pin  23  may be configured to transmit a GND_DRAIN signal of the USB 3.0 standard. The fourth pin  24  may be configured to transmit a StdA_SSTX− signal of the USB 3.0 standard. The fifth pin  25  may be configured to transmit a StdA_SSTX+ signal of the USB 3.0 standard. 
     If the package  10  and the pin module  20  are combined, the first to fifth pins  21  to  25  may be disposed on the fifth to ninth planar electrodes  15  to  19 , respectively. The first to fifth pins  21  to  25  may directly or indirectly contact the fifth to ninth planar electrodes  15  to  19 . That is, the first to fifth pins  21  to  25  may directly contact the fifth to ninth planar electrodes  15  to  19 . That is, regardless of whether the USB device  100  is inserted into a host or not (see  FIGS. 10A and 10B ), if the package  10  and the pin module  20  are combined, the first to fifth pins  21  to  25  may continuously and directly contact the fifth to ninth planar electrodes  15  to  19 . 
     Selectively, the first to fifth pins  21  to  25  may not contact the fifth to ninth planar electrodes  15  to  19  when the USB device  100  is not inserted into the host (see  FIG. 11A ) and may directly contact the fifth to ninth planar electrodes  15  to  19  when the USB device  100  is inserted into the host (see  FIG. 11B ). These will be described in more detail with reference to  FIGS. 10A ,  10 B,  11 A, and  11 B. 
     The fixing unit  33  may fix the first to fifth pins  21  to  25 . The fixing unit  33  may be formed of a non-conductive material. The insertion unit  35  provides a space S in the pin module  20 . A portion or all of the package  10  including the substrate  105  of  FIG. 9  and the sealing material  140  of  FIG. 9  may be inserted into the insertion unit  35  such that the package  10  and the pin module  20  are combined. 
       FIGS. 10A ,  10 B,  11 A, and  11 B are cross-sectional views when the USB device  100  of  FIGS. 1 to 6  is combined with a host. Hereinafter, redundant descriptions will be omitted. 
     Referring to  FIGS. 10A and 10B , when the package  10  and the pin module  20  are combined, the first pin  21  may directly contact the fifth planar electrodes  15 . That is, before the USB device  100  is inserted into the host  200  as shown in  FIG. 10A  and after the USB device  100  is inserted into the host  200  as shown in  FIG. 10B , the first pin  21  may continuously and directly contact the fifth planar electrodes  15 . 
     Referring to  FIG. 11A , when the USB device  100  is not inserted into the host  200 , the first pin  21  may not contact the fifth planar electrode  15 . Referring to  FIG. 11B , when the USB device  100  is inserted into the host  200 , the first pin  21  may directly contact the fifth planar electrode  15 . 
     Although only the contact relationship between the first pin  21  and the fifth planar electrode  15  is illustrated in the drawings, the inventive concept is not limited thereto. That is, the contact relationships between the second to fifth pins  22  to  25  of  FIG. 1  and the sixth to ninth planar electrodes  16  to  19  of  FIG. 1  may be the same as shown in  FIGS. 10 and 11 . 
       FIGS. 12A ,  12 B, and  13  illustrate USB devices according to embodiments based on the technical idea of the inventive concept.  FIGS. 12A ,  12 B, and  13  illustrate USB devices in which the pin module  20  of the USB device of  FIGS. 1 to 6  is partially modified. Hereinafter, redundant descriptions will be omitted. 
     Referring to  FIGS. 12A ,  12 B, and  13 , the entire package  10  is inserted into the insertion unit  35  of the pin module  20 , such that the package  10  and the pin module  20  are combined. For example, as shown in  FIGS. 12A and 12B , the package  10  and the pin module  20  may be combined through a sliding combination method. Additionally, as shown in  FIG. 13 , the package  10  and the pin module  20  may be combined through a vertical combination method. 
       FIGS. 14A and 14B  illustrate a USB device according to embodiments based on the technical idea of the inventive concept.  FIGS. 14A and 14B  illustrate the USB devices in which the USB device  100  of  FIGS. 1 to 6  is partially modified. Hereinafter, overlapping description in two embodiments will be omitted. 
     Referring to  FIGS. 14A and 14B , first to fourth planar electrodes  11  to  14  for transmitting signals based on the USB 2.0 standard may be disposed at a first edge region E 1  on one side of the package  10 . The fifth to ninth planar electrodes  15  to  19  for transmitting signals based on the USB 3.0 standard may be disposed at a second edge region E 2  on one side of the package  10 . The first to fifth pins  21  to  25  may be disposed on the fifth to ninth planar electrodes  15  to  19 , respectively, at the second edge region E 2 . 
     The USB device  100  may further include sixth to tenth pins  26  to  30  that penetrate the fixing unit  33 . The sixth to tenth pins  26  to  30  may be directly connected to the first to fifth pins  21  to  25 , respectively. In order to provide a USB 3.0 plug to be inserted in a host, the sixth to tenth pins  26  to  30  may extend toward the first edge region E 1 . 
     It should be construed that a form of each portion of the accompanying drawings is just an example to clarify the inventive concept. It should be obvious that various forms different from the drawings are possible. Like reference numerals refer to like components. 
     While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.