Abstract:
A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.

Description:
BACKGROUND 
   The present invention claims priority to U.S. Provisional Application No. 61/020,132 filed Jan. 9, 2008. The present invention relates generally to integrated circuit (IC) designs, and more particularly to a voltage-control oscillator circuits with combined MOS/bipolar device for various circuit design applications. 
   A voltage-controlled oscillator (VCO) is an electronic oscillator designed to be controlled in oscillation frequency by a voltage input. The VCO generates a signal varying at two predetermined voltages levels at a frequency controlled by the voltage input. The VCO can be found in various circuits, such as phase-locked loops in communication applications. These phase-locked loops are able to generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs. 
     FIG. 1A  schematically illustrates a conventional Hartley oscillator  100  comprised of a bipolar transistor  102 , a resistor  110 , a capacitor  108  and inductors  104  and  106  for the purposes of explaining the operation of a simple electronic oscillator. The bipolar transistor  102  has a collector connected to an end of the resistor, an emitter connected between the inductors  104  and  106 , and a base connected to an end of the capacitor. The resistor  110  is connected between the collector of the bipolar transistor  102  and the inductor  106  or the capacitor  108 . The inductors  104  and  106  are serially connected, with one end of the inductor chain connected to the base of the bipolar transistor  102  and the capacitor  108 , and another end connected to the resistor  110  and the capacitor  108 . The capacitor  108 , the chain of inductors  104  and  106 , and the resistor  110  are arranged in parallel. 
   In operation, a bias is applied to the base of the bipolar transistor  102  for controlling the amplified current output from the emitter. The amplified current from the emitter is directed back to the base to induce the next cycle of current amplification. The inductors  104  and  106 , the capacitor  108 , and the resistor  110  make up a LCR circuit that provides the bipolar transistor  102  with impedance to adjust the frequency of the current amplification cycles of the bipolar transistor  102 . Changing the impedance results in a change of the oscillation frequency. 
     FIG. 1B  is a schematic diagram illustrating a voltage-controlled oscillator (VCO) commonly used in radio frequency (RF) devices for telecommunication applications. Serially connected inductor  152  and capacitor  164  form a LC oscillator with a NMOS transistor  172  periodically “on” and “off” to control the discharging and charging, respectively, of the capacitor  164 . Symmetrically, serially connected inductor  154  and capacitor  162  form another LC oscillator with a NMOS transistor  174  periodically “on” and “off” to control the discharging and charging, respectively, of the capacitor  162 . A gate of the NMOS transistor  172  is connected to a node B. Voltage at the node B increases as the capacitor  162  is charging up. When the voltage at the node B passes a threshold voltage of the NMOS transistor  172 , the NMOS transistor  172  will be turned “on” and cause the capacitor  164  to discharge. Symmetrically, a gate of the NMOS transistor  174  is connected to a node A. Voltage at the node A increases as the capacitor  164  is charging up. When the voltage at the node A passes a threshold voltage of the NMOS transistor  174 , the NMOS transistor  174  will be turned “on” and cause the capacitor  162  to discharge. In order to control the frequencies of oscillators, a controllable voltage is applied to the capacitors  162  and  164  at a node VTUNE. Capacitances of the capacitors  162  and  164  vary, so are the frequencies, proportionally to the changes of the voltage at the node VTUNE. In fact, the capacitors  162  and  164  with voltage controlled variable capacitance are called varactors. 
   However, varactors are conventionally formed by a vertical structure in a bipolar process while virtually all other devices in a chip are manufactured in a CMOS processes. Separate bipolar process steps add cost and complexity to the CMOS process. As such, what is desired in VCO with simple device structures and a manufacturing process compatible with the common CMOS process. 
   SUMMARY 
   The present invention is directed to a VCO implemented with merged MOS transistor and BJT devices. In one embodiment of the present invention, the VCO comprises a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor, and a second inductor connected to both the collector of the second bipolar transistor and a base of the first bipolar transistor. 
   In another embodiment of the present invention, the VCO comprises a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, a first inductor connected to the source/drain of the first MOS transistor and a gate of the second MOS transistor, and a second inductor connected to the source/drain of the second MOS transistor and a gate of the first MOS transistor. 
   The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A and 1B  schematically illustrate conventional electronic oscillators. 
       FIGS. 2A and 2B  schematically illustrate merged MOS transistor and BJT devices. 
       FIGS. 3A and 3B  schematically illustrates voltage controlled oscillators using the proposed merged MOS transistor and BJT devices in accordance with one embodiment of the present invention. 
       FIGS. 4A and 4B  schematically illustrates voltage controlled oscillators using the proposed merged MOS transistor and BJT devices in accordance with another embodiment of the present invention. 
   

   DESCRIPTION 
   This invention describes voltage controlled oscillators (VCOs) that utilize merged metal-on-silicon (MOS) transistors and bipolar junction transistors (BJT). The following merely illustrates various embodiments of the present invention for purposes of explaining the principles thereof. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of this invention. 
   A published US patent application, No. 2007/0105301, by the same assignee depicts a merged MOS and BJT structure. The contents of the published US patent application are herein incorporated by reference in their entirety. 
     FIG. 2A  is a schematic diagram representing a merged NMOS transistor and a NPN bipolar transistor device  200 . The merged device  200  is comprised of an NMOS transistor  202  and an NPN bipolar transistor  204 . The NMOS transistor  202  has a source/drain terminal sharing a common active area with a collector of the NPN bipolar transistor  204 , and another source/drain terminal sharing a common active area with an emitter of the NPN bipolar transistor  204 . The gate of the NMOS transistor  202  is adapted to be controlled by a control signal. The base of the NPN bipolar transistor  204  is adapted to be biased to increase the current gain between the collector and the emitter. 
   Similarly,  FIG. 2B  is a schematic diagram representing a merged PMOS transistor and a PNP bipolar transistor device  210 . The merged device  210  is comprised of a PMOS transistor  212  and a PNP bipolar transistor  214 . The PMOS transistor  212  has a source/drain terminal sharing a common active area with a collector of the PNP bipolar transistor  214 , and another source/drain terminal sharing a common active area with an emitter of the PNP bipolar transistor  214 . The gate of the PMOS transistor  212  is adapted to be controlled by a control signal. The base of the PNP transistor  214  is adapted to be biased to increase the current gain between the collector and the emitter. As discussed in the published US patent application, No. 2007/0105301, the merged devices  200  and  210  are fully compatible with common CMOS processes. 
     FIG. 3A  schematically illustrates a VCO  300  using the merged MOS and BJT device  200  shown in  FIG. 2A  in accordance with one embodiment of the present invention. The VCO  300  is comprised of the merged MOS and BJT devices  302   a  and  302   b,  inductors  308   a  and  308   b,  and a supply current device  304 . The inductors  308   a  and  308   b  are serially connected between the merged MOS and BJT devices  302   a  and  302   b,  wherein a power supply VDD is connected to the terminal that serially connecting the two inductors  308   a  and  308   b.  The merged MOS and BJT device  302   a  is comprised of an NMOS transistor N 1  and an NPN bipolar transistor B 1 . The NMOS transistor N 1  has a drain sharing a common active area with a collector of the NPN bipolar transistor B 1  at a node  312 , and a source sharing a common active area with an emitter of the NPN bipolar transistor B 1  at a node  314 . The merged MOS and BJT device  302   b  is comprised of an NMOS transistor N 2  and an NPN bipolar transistor B 2 . The NMOS transistor N 2  has a drain sharing a common active area with a collector of the NPN bipolar transistor B 2  at a node  316 , and a source sharing a common active area with an emitter of the NPN bipolar transistor B 2  at the node  314 . The gates of the NMOS transistors N 1  and N 2  are connected together and controlled by a control signal VIN. The base of the bipolar device B 1  is connected to the node  316 , which is further connected to the inductor  308   b,  the collector of the bipolar transistor B 2 , and the drain of the NMOS transistor N 2 . The base of the bipolar transistor B 2  is connected to the node  312 , which is further connected to the inductor  308   a,  the collector of the bipolar transistor B 1 , and the drain of the NMOS transistor N 1 . Capacitance between collector and emitter of the bipolar transistor B 1  serves as a charging and discharging capacitor for the inductor  308   a.  Similarly, capacitance between collector and emitter of the bipolar transistor B 2  serves as a charging and discharging capacitor for the inductor  308   b.  The NMOS transistor  304  limits the current supply to the merged MOS and BJT devices  302   a  and  302   b,  therefore, can control oscillation frequency of the VCO  300 . 
   In operation, as the power supply VDD charging up the capacitances in the bipolar transistors B 1  and B 2 , voltage at the nodes  312  and  316  increase until to a point where the bipolar transistors B 1  and B 2  are turned on. Then the capacitances in the bipolar transistors B 1  and B 2  discharge to a point the bipolar transistors B 1  and B 2  being turned off and start another charging process. The NMOS transistors N 1  and N 2  can control the oscillation through the bipolar transistors B 1  and B 1 , respectively, by shorting the collector and emitter of the same. Either DC of AC signal may be applied at the node VIN. With the combination of the NMOS transistors N 1  and N 2  with the bipolar transistors B 1  and B 2 , the VCO  300  can operate at much higher oscillation frequency level than conventional VCOs. 
     FIG. 3B  schematically illustrates a VCO  320  also using the merged MOS and BJT device  200  shown in  FIG. 2A  in accordance with another embodiment of the present invention. The only different between the VCO  320  and the VCO  300  shown in  FIG. 3A  is that a pair of varactors  326   a  and  326   b  is added to the VCO  320  between the bases of the bipolar transistors B 1  and B 2 , respectively, and a node VTUNE. The VCO  320  resembles the conventional VCO  150  shown in  FIG. 1B , with the merged MOS and BJT devices  302   a  and  302   b  of  FIG. 3B  replacing the NMOS transistors  172  and  174  of  FIG. 1B , respectively. The varactors  326   a  and  326   b  of  FIG. 3B  performs the same charging and discharging functions as the varactors  162  and  164  of  FIG. 1B . A voltage applied at the node VTUNE can further tune the frequency range of the VCO  320 . 
   Alternatively,  FIG. 4A  schematically illustrates a VCO  400  using the merged MOS and BJT device  200  shown in  FIG. 2A  in accordance with yet another embodiment of the present invention. The VCO  400  is comprised of the merged MOS and BJT devices  402   a  and  402   b,  inductors  408   a  and  408   b,  and a supply current device  404 . The inductors  408   a  and  408   b  are serially connected between the merged MOS and BJT devices  402   a  and  402   b,  wherein a power supply VDD is connected to the terminal that serially connecting the two inductors  408   a  and  408   b.  The merged MOS and BJT device  402   a  is comprised of an NMOS transistor N 3  and an NPN bipolar transistor B 3 . The NMOS transistor N 3  has a drain shares a collector of the NPN bipolar transistor B 3  at a node  412 , and a source sharing a common active area with an emitter of the NPN bipolar transistor B 3  at a node  414 . The merged MOS and BJT device  402   b  is comprised of an NMOS transistor N 4  and an NPN bipolar transistor B 4 . The NMOS transistor N 4  has a drain sharing a common active area with a collector of the NPN bipolar transistor B 4  at a node  416 , and a source sharing a common active area with an emitter of the NPN bipolar transistor B 4  at the node  414 . The bases of the bipolar transistors B 3  and B 4  are connected together and controlled by a control signal VIN. The gate of the NMOS transistor N 3  is connected to the node  416 , which is further connected to the inductor  408   b,  the collector of the bipolar transistor B 4 , and the drain of the NMOS transistor N 4 . The gate of the NMOS transistor N 4  is connected to the node  412 , which is further connected to the inductor  408   a,  the collector of the bipolar transistor B 3 , and the drain of the NMOS transistor N 3 . Capacitance between source and drain of the NMOS transistor N 3  serves as a charging and discharging capacitor for the inductor  408   a.  Similarly, capacitance between source and drain of the NMOS transistor N 4  serves as a charging and discharging capacitor for the inductor  408   b.  The NMOS transistor  404  limits the current supply to the merged MOS and BJT devices  402   a  and  402   b,  therefore, can control oscillation frequency of the VCO  400 . 
   In operation, as the power supply VDD charging up the capacitances in the NMOS transistors N 3  and N 4 , voltage at the nodes  412  and  416  increase until to a point where the NMOS transistors N 3  and N 4  are turned on. Then the capacitances in the NMOS transistors N 3  and N 4  discharge to a point the NMOS transistors N 3  and N 4  being turned off and start another charging process. The bipolar transistors B 3  and B 4  can control the oscillation through the NMOS transistors N 3  and N 4 , respectively, by shorting the source and drain of the same. Either DC of AC signal may be applied at the node VIN. With the combination of the bipolar transistors B 3  and B 4  with the NMOS transistors N 3  and N 4 , the VCO  400  can operate at much higher oscillation frequency level than conventional VCOs. 
   Referring to both  FIGS. 3A and 4A , the difference between the VCO  300  and the VCO  400  is that in the VCO  300 , the bipolar transistors B 1  and B 2  are used as the charging and discharging capacitors for producing an oscillation, while in the VCO  400 , the NMOS transistor N 3  and N 4  are used for the charging and discharging capacitors. This demonstrates the versatility of the merged MOS and BJT device. 
     FIG. 4B  schematically illustrates a VCO  420  also using the merged MOS and BJT device  200  shown in  FIG. 2A  in accordance with yet another embodiment of the present invention. The only different between the VCO  420  and the VCO  400  shown in  FIG. 4A  is that a pair of varactors  426   a  and  426   b  is added to the VCO  420  between the gates of the NMOS transistors N 3  and N 4 , respectively, and a node VTUNE. The VCO  420  resembles the conventional VCO  150  shown in  FIG. 1B , with the merged MOS and BJT devices  402   a  and  402   b  of  FIG. 4B  replacing the NMOS transistors  172  and  174  of  FIG. 1B , respectively. The varactors  426   a  and  426   b  of  FIG. 4B  performs the same charging and discharging functions as the varactors  162  and  164  of  FIG. 1B . A voltage applied at the node VTUNE can further tune the frequency range of the VCO  420 . 
   It is noted that although the above embodiments disclose using the merged devices of NMOS transistors and NPN bipolar transistors in the proposed VCOs, other merged devices comprised of PMOS transistors and PNP bipolar transistors, such as the one shown in  FIG. 2B , can also be used for the VCOs. The construction of the VCOs using the merged PMOS and PNP bipolar transistors is similar to those described in  FIGS. 3 and 4 , and is readily appreciated by people skilled in the art in view of the disclosures of the specification without undue experiments. 
   The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
   Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.