Abstract:
A chip structure with solder bumps and the method for producing the same are disclosed. The chip structure with solder bumps includes a chip, a plurality of pads arranged on one surface of the chip, a protection layer formed on the surface of the chip and exposing the pads, a first photo-imaginable dielectric layer covered on the protection layer, a plurality of UBMs arranged on the pads, and extends over the first photo-imaginable dielectric layer respectively, a second photo-imaginable dielectric layer covered on the UBMs and the first photo-imaginable dielectric layer, and a plurality of conductive bumps relative to the pads and disposed on the UBMs respectively. Each UBM has a heat-dissipation portion extending to the edge of the surface of the chip. The second photo-imaginable dielectric layer reveals the heat-dissipation portions respectively. Therefore, effective heat dissipation can be met by the direct reveled heat-dissipation portion or by a further heat-dissipation bump disposed over the heat-dissipation portion.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority benefit of Taiwan Patent Application Serial Number 094139193 filed Nov. 8, 2005, the full disclosure of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a chip structure with solder bumps and the method for producing the same, and more particularly, to a chip structure with solder bumps and the method for producing the same that can improve the heat dissipation of the solder bumps and circuit board and therefore reduce the damage to the chip and circuit board.  
         [0004]     2. Description of the Related Art  
         [0005]     The chip in an Ultra-Chip-Scale Package (UCSP) uses solder balls to electrically connect to a circuit board. The space between the chip and circuit board is not filled with an underfill. The main advantage of such a package is that the induction reactance between the chip and circuit board can be greatly reduced. However, the thermal stress resulted from the difference between the coefficients of thermal expansion of the chip and circuit board acts on the solder balls. This will cause the junctions between the solder balls and chip/circuit board to be broken when the solder balls experience an increase in thermal stress as a result of temperature raise. Therefore, there exists a need to improve the heat dissipation for the UCSP in order to reduce the thermal stress in the solder balls. Referring to  FIG. 1 , it illustrates a conventional chip structure that a solder ball is attached to a chip. A pad  12   a  is disposed on a chip  10   a.  A protection layer  14   a  is formed on the chip  10   a  and exposes the pad  12   a.  An under bump metallurgy (UBM)  16   a  is formed on the pad  12   a.  A solder ball  18   a  is attached to the UBM  16   a.  Referring to FIG  1   a,  it illustrates that the chip structure of  FIG. 1  is attached to a circuit board. The chip  10   a  is attached to a circuit board  20   a  by the solder balls  18   a.  As shown in the figure, the solder ball  18   a ″ closer to the edge of the chip  10   a  than the solder ball  18   a ′ achieves better heat dissipation as a result of good convection. It is to be noted that heat can be generated by the chip  10   a  during its operation other than in the process of soldering. It is possible that the operating heat can be kept in the chip  10   a  and therefore lead to the damage to the chip  10   a.  On the other hand, the operating heat can also give rise to residual stress in the solder balls  18   a  resulted from the difference between the coefficients of thermal expansion of the chip  10   a  and circuit board  20   a  and therefore reduce the reliability of the package.  
         [0006]     In view of the above, there exists a need to improve the heat dissipation for the UCSP.  
       SUMMARY OF THE INVENTION  
       [0007]     It is an object of the present invention to provide a chip structure with solder bumps and the method for producing the same that can increase the efficiency of the heat dissipation for solder balls and circuit board. This will be able to lower the temperature of the circuit board and the chip disposed thereon and therefore avoid damage to the chip.  
         [0008]     It is another object of the present invention to provide a chip structure with solder bumps and the method for producing the same that can reduce the residual stress in the solder balls resulted from the difference between the coefficients of thermal expansion of the chip and circuit board and therefore the reliability of the package can be raised.  
         [0009]     In order to achieve the above objects, the chip structure with solder bumps of the present invention includes a chip, a plurality of pads disposed on one surface of the chip, a protection layer formed on the surface of the chip and exposing the pads, a first photo-imaginable dielectric layer formed on the protection layer, a plurality of under bump metallurgies (UBMs) disposed on the pads, a second photo-imaginable dielectric layer formed on the UBMs and the first photo-imaginable dielectric layer and a plurality of conductive bumps disposed on the UBMs. The first photo-imaginable dielectric layer has a plurality of first openings from which the pads are exposed. Each of the UBMs has a heat-dissipation portion extending to the periphery of the chip. The second photo-imaginable dielectric layer has a plurality of second openings and third openings. The second openings are corresponding to the pads and expose the UBMs. The third openings are arranged on the periphery of the chip and expose the heat-dissipation portions. The conductive bumps are attached to the UBMs through the second openings.  
         [0010]     The method for producing the chip structure with solder bumps according to an embodiment of the present invention includes the steps as follows.  
         [0011]     A wafer is provided. A plurality of pads, a protection layer, a first photo-imaginable dielectric layer are formed in sequence on one surface of the wafer. The protection layer and first photo-imaginable dielectric layer both expose the pads. A plurality of UBMs is disposed on the pads and first photo-imaginable dielectric layer based on a predetermined pattern. Each of the UBMs has a heat-dissipation portion extending to the periphery of the chip. A second photo-imaginable dielectric layer is formed on the first photo-imaginable dielectric layer. The second photo-imaginable dielectric layer includes a plurality of second openings and third openings. The second openings are corresponding to the pads and expose the UBMs. The third openings are arranged on the periphery of the chip and expose the heat-dissipation portions. A plurality of conductive bumps is corresponding to the pads and attached to the UBMs.  
         [0012]     The method for producing the chip structure with solder bumps according to another embodiment of the present invention includes the steps as follows.  
         [0013]     A wafer is provided. A plurality of pads, a protection layer, a first photo-imaginable dielectric layer are formed in sequence on one surface of the wafer. The protection layer and first photo-imaginable dielectric layer both expose the pads. A plurality of UBMs is disposed on the pads and first photo-imaginable dielectric layer based on a predetermined pattern. Each of the UBMs has a heat-dissipation portion extending to the periphery of the chip. A second photo-imaginable dielectric layer is formed on the first photo-imaginable dielectric layer. The second photo-imaginable dielectric layer includes a plurality of second openings and third openings. The second openings are corresponding to the pads and expose the UBMs. The third openings are arranged on the periphery of the chip and expose the heat-dissipation portions. The heat-dissipation bumps are formed on the periphery of the chip and attached to the UBMs.  
         [0014]     The method for producing the chip structure with solder bumps according to a further embodiment of the present invention includes the steps as follows.  
         [0015]     A wafer is provided. A plurality of pads, a protection layer, a first photo-imaginable dielectric layer are formed in sequence on one surface of the wafer. The protection layer and first photo-imaginable dielectric layer both expose the pads. A plurality of UBMs is disposed on the pads and first photo-imaginable dielectric layer based on a predetermined pattern. Each of the UBMs has a heat-dissipation portion extending to the periphery of the chip. A second photo-imaginable dielectric layer is formed on the first photo-imaginable dielectric layer. The second photo-imaginable dielectric layer includes a plurality of second openings and third openings. The second openings are corresponding to the pads and expose the UBMs. The third openings are arranged on the periphery of the chip and expose the heat-dissipation portions. A plurality of auxiliary UBMs are disposed on the periphery of the chip and attached to the UBMs. The heat-dissipation bumps are formed on the UBMs.  
         [0016]     The foregoing, as well as additional objects, features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIG. 1  is a cross-sectional view of a conventional chip structure with solder bumps.  
         [0018]      FIG. 1A  is a cross-sectional view illustrating that the chip structure of  FIG. 1  is attached to a circuit board.  
         [0019]      FIG. 2  is a top view of the chip structure with solder bumps of the present invention.  
         [0020]      FIG. 3A  is an enlarged cross-sectional view of the portion A of  FIG. 2 .  
         [0021]      FIG. 3B  is an enlarged cross-sectional view of the portion B of  FIG. 2 .  
         [0022]      FIG. 4  is a cross-sectional view of the portion A of  FIG. 2  according to the first embodiment of the present invention.  
         [0023]      FIG. 4A  is a cross-sectional view of the portion A of  FIG. 2  according to the second embodiment of the present invention.  
         [0024]      FIG. 4B  is a cross-sectional view of the portion A of  FIG. 2  according to the third embodiment of the present invention.  
         [0025]      FIG. 5  is a cross-sectional view of the portion B of  FIG. 2  according to the first embodiment of the present invention.  
         [0026]      FIG. 5A  is a cross-sectional view of the portion B of  FIG. 2  according to the second embodiment of the present invention.  
         [0027]      FIGS. 6A  to  6 K illustrate the method for producing the chip structure with solder bumps of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0028]     Referring to  FIGS. 2, 3A  and  3 B, the present invention discloses a chip structure with solder bumps. A chip  10  has a surface  11  for attaching to a circuit board  50 . A plurality of heat-dissipation units  20  are formed on the periphery  12  of the surface  11 . The heat-dissipation unit  20  has an arbitrary shape and size. From the heat convection equation, the heat convection rate is known as 
 
 dQ/dt=h*A* ( Th−Tl ), 
 
 where 
 
         [0029]     Q is heat;  
         [0030]     t is time;  
         [0031]     h is average heat-transfer coefficient;  
         [0032]     A is cross-section area; and  
         [0033]     Th−Tl is temperature difference.  
         [0034]     When the heat-dissipation unit  20  is connected to the conductive bump  30 , the heat kept in the conductive bump  30  can be conducted to the periphery  12  of the chip  10  through the heat-dissipation unit  20  to dissipate to the environment. The heat-dissipation units  20  can be only a conductive layer or be the conductive layer attached with the conductive bump  30 . The bumps of the heat-dissipation units  20  can make a change to the thermal field and therefore the heat kept in the conductive bumps  30  can be taken away by the air flow resulted from the change of the thermal field. In addition, the periphery  12  of the chip  10  can further be provided with a plurality of air spoilers  40  that are not connected to the conductive bumps  30 . The air spoiler  40  has the shape of a bump and can also change the thermal field. The heat kept in the conductive bumps  30  can be taken away by the air flow resulted from the change of the thermal field. Therefore, such arrangements can raise the efficiency of heat dissipation by increasing the area for convection.  
         [0035]     Referring to  FIGS. 4, 4   a  and  4   b,  they illustrate the chip with bumps according to the first, second and third embodiments of the present invention respectively. As shown in  FIG. 4 , it illustrates an enlarged cross-sectional view of the portion A of  FIG. 2 . The chip structure includes the chip  10 , a plurality of pads  101  disposed on the surface  11  of the chip  10 , a protection layer  102  formed on the surface  11  and exposing the pads  101 , a first photo-imaginable dielectric layer  103  formed on the protection layer  102 , a plurality of under bump metallurgies (UBMs)  104  disposed on the pads  101 , a second photo-imaginable dielectric layer  105  formed on the first photo-imaginable dielectric layer  103  and the conductive bumps  30  disposed on the UBMs  104 . The first photo-imaginable dielectric layer  103  has a plurality of first openings  1031  from which the pads  101  are exposed. Each of the UBMs  104  has a heat-dissipation portion  1041  extending to the periphery  12  of the chip  10 . The second photo-imaginable dielectric layer  105  has a plurality of second openings  1051  and third openings  1052 . The second openings  1051  are corresponding to the pads  101  and expose the UBMs  104 . The third openings  1052  are arranged on the periphery  12  of the chip  10  and expose the heat-dissipation portions  1041 . The conductive bumps  30  are attached to the UBMs  104  through the second openings  1051 . The conductive bumps  30  can be solder balls. According to the embodiment shown in  FIG. 4 , the heat-dissipation units  20  are formed by arranging the third openings  1052  on the periphery  12  of the chip  10  and exposing the heat-dissipation portions  1041 . This arrangement can achieve the object of raising the efficiency of heat dissipation by conducting the heat from the conductive bumps  30  to the periphery  12  of the chip  10 .  
         [0036]     Referring to  FIG. 4A , the chip  10  further includes a plurality of heat-dissipation bumps  106  disposed in the third openings  1052  and attached to the heat-dissipation portions  1041  as the heat-dissipation units  20 . The arrangement of the heat-dissipation bumps  106  can change the thermal field and therefore the heat is easy to be taken away by the air flow resulted from the change of the thermal field. Referring to  FIG. 4B , the chip  10  still further includes a plurality of auxiliary UBMs  107  disposed between the heat-dissipation bumps  106  and heat-dissipation portions  1041  to help the heat-dissipation bumps  106  to firmly attach to the chip  10 .  
         [0037]     Referring to  FIG. 5 , it illustrates the air spoilers  40  of the chip structure with bumps of the present invention. As shown in  FIG. 5 , it illustrates an enlarged cross-sectional view of the portion B of  FIG. 2 . The chip  100  further includes a plurality of auxiliary heat-dissipation portions  1042  disposed on the periphery  12  and on first photo-imaginable dielectric layer  103 . The auxiliary heat-dissipation portion  1042  electrically isolates from the UBM  104 . The second photo-imaginable dielectric layer  105  has a plurality of fourth openings  1053  arranged on the auxiliary heat-dissipation portions  1042 . According to the embodiment shown in  FIG. 5 , the fourth openings  1053  are arranged on the periphery  12  of the chip  10  and expose the auxiliary heat-dissipation portions  1042 . The exposed auxiliary heat-dissipation portions  1042  can function as the air spoilers  40 . In addition, according to the embodiment shown in  FIG. 5A , the chip structure still further includes a plurality of auxiliary heat-dissipation bumps  108  disposed on the auxiliary heat-dissipation portions  1042  through the fourth openings  1053 . Therefore, the air spoilers  40  are made by the auxiliary heat-dissipation bumps  108  so as to change the thermal field. The heat is easy to be taken away by the air flow resulted from the change of the thermal field. Referring to  FIG. 5A , as shown in the embodiment of  FIG. 4B , it illustrates another aspect of the air spoilers  40 . The chip structure further includes a plurality of auxiliary UBMs  107  disposed between the auxiliary heat-dissipation bumps  108  and auxiliary heat-dissipation portions  1042  to help the auxiliary heat-dissipation bumps  108  to firmly attach to the chip  10 .  
         [0038]     Referring to  FIGS. 6A  to  6 E, they illustrate the method for producing the chip structure with solder bumps of the present invention. The method includes the steps as follows. First, a wafer  10 ′ defining a plurality of chips is provided (step a). A plurality of pads  101 ′ is then formed on one surface  11 ′ of the wafer  10 ′ (step b). A protection layer  102 ′ is formed on the surface  11 ′ of the wafer  10 ′ and exposing the pads  101 ′ (step c). The steps a to c are shown in  FIG. 6A . Referring to  FIG. 6B , a first photo-imaginable dielectric layer  103 ′ is formed on the protection layer  102 ′ that the first photo-imaginable dielectric layer  103 ′ includes a plurality of first openings  1031 ′ from which the pads  101 ′ are exposed (step d). Referring to  FIG. 6C , a plurality of UBMs  104 ′ is formed on the pads  101 ′ and on first photo-imaginable dielectric layer  103 ′ based on a predetermined pattern by sputtering (step e). Each of the UBMs  104 ′ has a heat-dissipation portion  1041 ′ extending to the periphery  12 ′ of each of the chips. The UBMs  104 ′ separate from each other so as to form a plurality of heat-dissipation units  20 ′ corresponding to the pads  101 ′. Referring to  FIG. 6D , in the step e, a plurality of auxiliary heat-dissipation portions  1042 ′ different from the heat-dissipation portions  1041 ′ can be formed on the periphery  12 ′ and on the first photo-imaginable dielectric layer  103 ′ during the period of forming the UBMs  104 ′ by sputtering. The auxiliary heat-dissipation portions  1042 ′ are exposed to the environment and function as the air spoilers  40 ′. The heat-dissipation portions  1041 ′ are connected to the pads  101 ′ and used to dissipate heat to the environment. Referring to  FIG. 6E , a second photo-imaginable dielectric layer  105 ′ is formed on the first photo-imaginable dielectric layer  103 ′ that the second photo-imaginable dielectric layer  105 ′ includes a plurality of second openings  1051 ′ and third openings  1052 ′ (step f). The second openings  1051 ′ are corresponding to the pads  101 ′ and expose the UBMs  104 ′. The third openings  1052 ′ are arranged on the periphery  12 ′ and expose the heat-dissipation portions  1041 ′. The exposed heat-dissipation portions  1041 ′ are the first aspect of the heat-dissipation units  20 ′, as shown in  FIG. 6E . In the step f, a plurality of fourth openings  1053 ′ can be formed to expose auxiliary heat-dissipation portion  1042 ′ during the period of forming the second openings  1051 ′ and third openings  1052 ′ of the second photo-imaginable dielectric layer  105 ′. Referring to  FIG. 6G , a plurality of conductive bumps  30 ′, such as solder balls is disposed on the UBMs  104 ′ (step g). The steps a to g illustrate the method for producing the chip structure with bumps according to the first embodiment of the present invention.  
         [0039]     In addition, the method for producing the chip structure with bumps of the present invention further includes the following step. Solder paste can be applied in the third openings  1052 ′ and on the heat-dissipation portions  1041 ′. After heating, the solder paste has the shape of a bump (step h). The step g can be performed before the step h, and vice versa. The above steps are the second aspect of the method for producing the chip structure of present invention. As shown in  FIG. 6H , the heat-dissipation bumps  106 ′ and the heat-dissipation portions  1041 ′ connecting to the conductive bumps  30 ′ together can form the second aspect of the heat-dissipation units  20 ′. In the step h, solder paste can be simultaneously applied to the auxiliary heat-dissipation portions  1042 ′. As shown in  FIG. 61 , after heating, the solder paste on the auxiliary heat-dissipation portions  1042 ′ forms a plurality of auxiliary heat-dissipation bumps  108 ′. The auxiliary heat-dissipation bumps  108 ′ function as the air spoilers  40 ′.  
         [0040]     Besides, an additional step i can be performed prior to the step h. A plurality of auxiliary UBMs  107 ′ is disposed between the heat-dissipation bumps  106 ′ and the heat-dissipation portions  1041 ′. This step illustrates the method for producing the chip structure according to the third embodiment of the present invention. The auxiliary UBMs  107 ′ are first disposed on the heat-dissipation portions  1041  and are then applied with solder paste. The solder paste is heated to form the heat-dissipation bumps  106 ′. As shown in  FIG. 6J , the heat-dissipation bumps  106 ′, the auxiliary UBMs  107 ′ and the heat-dissipation portions  1041 ′ connecting to the conductive bumps  30 ′ together form the heat-dissipation units  20 ′ of the third aspect. In the step i, the auxiliary UBMs  107 ′ can also be formed under the auxiliary heat-dissipation bumps  108 ′ to help the auxiliary heat-dissipation bumps  108 ′ to firmly attach to the wafer  10 ′. As shown in  FIG. 6K , the auxiliary heat-dissipation bumps  108 ′ function as the air spoilers  40 ′.  
         [0041]     The photo-imaginable dielectric layers  103 ′ and  105 ′ can be made of polyimide (PI) or benzocyclobutene (BCB).  
         [0042]     From the above discussion, the chip structure with solder bumps of the present invention has the advantages as follows: 
        1. Since the heat-dissipation units are connected to the solder balls, the heat kept in the conductive bumps can be conducted to the periphery of the chip through the heat-dissipation units to dissipate to the environment.     2. The heat-dissipation units with the shape of a bump can make a change to the thermal field and therefore the heat is easy to be taken away by the air flow resulted from the change of the thermal field.     3. Since the heat is easy to be taken away, the damage to the chip as a result of high temperature can therefore be avoided.     4. The residual stress in the solder balls resulted from the difference between the coefficients of thermal expansion of the chip and circuit board can be reduced and therefore the reliability of the package can be raised.     5. The air spoilers with the shape of a bump can change the thermal field and therefore the heat is easy to be taken away.        
 
         [0048]     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.