Abstract:
The present invention provides an electronic device and manufacturing method thereof. The interconnecting leads of adjacent fan-out blocks have different heights along boundary area, thereby making the resistance of the adjacent interconnecting leads uniform and ensuring the quality of the electronic device.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an electronic device with uniform-resistance fan-out blocks, and more particularly, to a thin film transistor liquid crystal display (TFT-LCD) panel with uniform-resistance fan-out blocks. 
   2. Description of the Prior Art 
     FIG. 1  shows a substrate  1  of a typical active matrix thin film transistor LCD panel, which generally includes an active area  10 . The active area  10  includes data lines  12  and gate lines  14  which collectively carry signals to control transistor switches (not shown in  FIG. 1 ) so as to drive pixels constructing an image on the display panel. Alternately, data lines  12  and gate lines  14  will be referred to as control lines in this specification. The portion surrounding the active area  10  is the out-lead bonding (OLB) area  16  which contains some bonding areas  20 . Each bonding area  20  includes multiple bonding pads to be coupled with external driving integrating circuits (ICs) or drivers. Moreover, there are many fan-out blocks  15  formed between control lines ( 12 ,  14 ) and the bonding area  20  in the OLB area  16 . Each fan-out block  15  includes multiple interconnecting leads, and each interconnecting lead is electrically connected to a control line ( 12 ,  14 ) at one end and connected to a bonding pad in the bonding pad area  20  at the other end for further connecting to external driving ICs. 
   Usually the pitch between adjacent interconnecting leads at the external driving IC side is far less than that at control line ( 12 ,  14 ) side in a typical fan-out block, and therefore the interconnecting leads of a fan-out block tend to have different lengths. Without special routing, for example, the outmost interconnecting lead will be far longer than the one in the medial portion of a fan-out block. Since the resistance of an interconnecting lead is proportional to its length, interconnecting leads of a fan-out block are prone to have different resistances. Such difference of resistances may impact the time delay and quality of control signals from external driving ICs and may thus downgrade the entire image quality. To resolve such problem, many works have been done for providing interconnecting leads with uniform resistance in a single fan-out block, such as the techniques disclosed in U.S. Pat. Nos. 6,104,465, 5,757,450, 6,683,669 and 6,842,200. Generally, these techniques can improve and achieve uniform resistance, i.e., make the resistance between adjacent interconnecting leads in a fan-out block substantially identical. 
   Although uniform resistance in a single fan-out block can be achieved by the techniques mentioned in above patents, the inventors of the present invention found that the resistances of interconnecting leads among fan-out blocks in the OLB area  16  may have non-negligible differences. Especially when the difference in resistance between the adjacent outmost interconnecting leads of two adjacent fan-out blocks is too large (more than 10Ω, for example), the resulted image quality is liable to be degraded.  FIG. 2  shows adjacent bonding areas ( 20   a,    20   b ) and the corresponding fan-out blocks (A, B). The adjacent region  5  of the two adjacent fan-out blocks (A, B) is highlighted and indicated by a circle. Driving ICs coupled to bonding area  20   a  and  20   b  may be either ICs of different specification or partially connected with some floating pins. In such cases, it is possible that the difference in resistance between adjacent outmost interconnecting leads of the two adjacent fan-out blocks (A, B) is too large to be neglected. In view of foregoing, there is a need to provide an improved fan-out block structure and method to resolve the problem associated with non-uniformity in resistance between adjacent fan-out blocks. 
   SUMMARY OF THE INVENTION 
   In view of the problem of non-uniformity in resistance between adjacent fan-out blocks in conventional LCD panels, one object of the present invention is to provide an electronic device, such as an LCD panel, which has uniform resistance between adjacent interconnecting leads of two adjacent fan-out blocks so as to ensure the image quality thereof. 
   It is another object of the present invention to provide an electronic device, such as an LCD panel, and a manufacturing method therefor such that the adjacent interconnecting leads of two adjacent fan-out blocks have uniform resistance to ensure the operation quality. 
   According to above objects, the present invention provides an electronic device having fan-out blocks with uniform-resistance interconnecting leads and the manufacturing method therefor. The fan-out block includes at least a first routing portion, a second routing portion, and an intermediate portion. Preferably, the intercept lengths of the second routing portions of two adjacent outmost interconnecting leads of adjacent fan-out blocks are different. Thereby, the resistance in adjacent outmost interconnecting leads of adjacent fan-out blocks is made substantially identical. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a substrate of a typical active matrix thin film transistor LCD panel. 
       FIG. 2  shows adjacent bonding areas and the corresponding fan-out blocks, where the adjacent region of the two adjacent fan-out blocks is also highlighted in the figure. 
       FIG. 3  shows an embodiment of the layout of a fan-out block in accordance with the present invention. 
       FIG. 4A  shows adjacent bonding areas and fan-out blocks as well as highlights the adjacent region therebetween. 
       FIG. 4B  shows an enlarged view of the adjacent region highlighted in  FIG. 4A , which adopts the same conventional routing scheme in both adjacent fan-out blocks. 
       FIG. 5  shows an embodiment of adjacent fan-out blocks in an LCD panel in accordance with the present invention. 
       FIG. 6  shows another embodiment of adjacent fan-out blocks in an LCD panel in accordance with the present invention. 
       FIG. 7  shows another embodiment of adjacent fan-out blocks in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Except fan-out blocks, the structure of elements of the LCD panel disclosed in the embodiments of the present invention is identical with that shown in  FIG. 1 . The description about the structure of a general LCD panel shown in  FIG. 1  is thus applicable for the present invention.  FIG. 3  shows an embodiment of the layout of a fan-out block in accordance with the present invention, which includes multiple interconnecting leads L, each interconnecting lead L at least including three portions: the first routing portion R 100  coupled to bonding pads in bonding area  20  ( FIG. 1 ) and electrically connected with external driving IC(s), the second routing portion R 102  connected with data lines  12  or gate lines  14 , and the intermediate portion R 101  locating and connecting between the first routing portion R 100  and the second routing portion R 102 . In contrast with the second routing portion R 102 , the first routing portion R 100  has a smaller pitch between adjacent interconnecting leads. Referring to  FIG. 3 , the distance between point P and Q is referred to as the intercept length or the height of the interconnecting lead L in the second routing portion R 102 , where P is the intersection point between the interconnecting lead L and an imaginary line X which is the intersection line of the second routing portion R 102  and the intermediate portion R 101 , as shown in  FIG. 3 , and Q is an external connecting point lying on the interconnecting lead L. Alternatively, Q can be referred as the intersection point of the interconnecting lead L and an imaginary line Y formed by intersecting the second routing portion R 102  with the active area  10  shown in  FIG. 1 . Variant routing trace style may be employed in the second routing portion R 102  and/or the first routing portion R 100 , such as a straight line, a bow-shaped line, a zigzag line, a serpentine line, or the combination thereof, as long as the effective length and the resulted resistance of interconnecting leads can be increased. Although the interconnecting leads in the intermediate portion R 101  are straight lines in the embodiment, other type of routing trace can be used therefor if necessary. Moreover, interconnecting lead segments in adjacent routing portion (such as R 101  and R 102 ) intersect with each other in an angle other than 180 degree (for example at point P) in the present embodiment. The intersecting angle thereof, however, can be 180 degree, i.e., an interconnecting lead can be a straight line through adjacent routing portion (such as R 101  and R 102 ) without any “turn” at the intersection point. Furthermore, although the interconnecting leads in the second routing portion R 102  are illustrated to be perpendicular to the imaginary line Y formed by points connecting to data lines  12  or gate lines  14  in the present embodiment, they may intersect with each other in an angle of any degree. 
     FIG. 4A  shows adjacent bonding areas and fan-out blocks as well as highlights the adjacent region  4 B therebetween.  FIG. 4B  shows an enlarged view of the adjacent region  4 B which adopts the same conventional routing scheme in both adjacent fan-out blocks. In contrast with the embodiment of fan-out block routing scheme shown in  FIG. 3 , the interconnecting leads are straight lines in the second routing portions of the conventional fan-out blocks shown in  FIG. 4B  and all have the same intercept length h. 
     FIG. 5  shows an embodiment of adjacent fan-out blocks in an LCD panel in accordance with the present invention, which shows the second routing portion and part of the intermediate portion only and omits the first routing portion. In the present invention, the intercept lengths (Ha, Hb) of the second routing portions of two adjacent outmost interconnecting leads of adjacent fan-out blocks are different in a manner that makes the resistance in the adjacent outmost interconnecting leads substantially identical or uniform, or the difference in resistance therebetween is under 10Ω. The method to implement the embodiment is to select a fan-out block (the one at the left side in  FIG. 5 , for example) as the reference fan-out block, then to construct another fan-out block (the one at the right side in  FIG. 5 ) with respect to the reference one. During the process of forming adjacent fan-out blocks, the resistance of the outmost interconnecting lead La in the reference fan-out block should be measured at first. If the adjacent interconnecting lead Lb has a resistance less than that of La, then the intercept length Hb of the interconnecting lead Lb should be lengthened. On the contrary, if the adjacent interconnecting lead Lb has a resistance larger than that of La, then the intercept length Hb of the interconnecting lead Lb should be shortened. After the intercept length Hb is determined, it may subsequently determine the routing style of the fan-out block in a manner such that resistance uniformity or negligible resistance difference between adjacent interconnecting leads in adjacent fan-out blocks is achieved. Besides the difference in resistance between adjacent interconnecting leads is under 10Ω, when the ratio of the maximum resistance to the minimum resistance of all interconnecting leads is under 3, a qualified image quality can be expected. The routing in the second routing portion may be constructed first. When the intercept length Hb can not meet the resistance uniformity perfectly, the routing in the first routing portion can then be constructed. Nevertheless, it is also feasible to first construct the routing in the first routing portion followed by routing in the second routing portion if necessary. Regarding to routing trace style, it is feasible to adopt schemes such as a bow-shaped routing, a zigzag routing, or a serpentine routing. It is also applicable to change the width, thickness, or material of interconnecting leads to increase or decrease the resistance if necessary. Although the present invention is illustrated by embodiments of LCD panels, it is applicable to other electronic devices to attain uniform resistance between adjacent interconnecting leads in adjacent fan-out blocks. 
   The embodiment shown in  FIG. 5  has interconnecting leads with identical intercept lengths within the same fan-out block, in other words, the intercept lengths of interconnecting leads in the reference fan-out block at the left side are all equal to Ha and the intercept lengths of interconnecting leads in the adjacent fan-out block at the right side are all equal to Hb. The intercept lengths of interconnecting leads in the same fan-out block, however, can be different if necessary in the present invention, as illustrated in another embodiment shown in  FIG. 6 . In the embodiment shown in  FIG. 6 , besides following the rule that the intercept length Ha 1  of the outmost interconnecting lead La 1  in the reference fan-out block is different from the intercept length Hb 1  of the outmost interconnecting lead Lb 1  in the adjacent fan-out block, intercept lengths of interconnecting leads in the second routing portion of an individual fan-out block are also different. As can be noted in  FIG. 6 , the imaginary boundary formed by the intersection between routing portions is thus a curve instead of a straight line. Likewise, this embodiment is also embodied in a manner such that the interconnecting leads in adjacent fan-out blocks have uniform resistance to ensure image quality. 
     FIG. 7  shows another embodiment of adjacent fan-out blocks in accordance with the present invention.  FIG. 7  includes two adjacent fan-out blocks FB 1  and FB 2  respectively containing a plurality of interconnecting leads. Each interconnecting lead has a first routing portion R 100 , an intermediate portion R 101 , and a second routing portion R 102 . Each interconnecting lead is connected with a first lead L 110  and a second lead L 120  respectively through the first routing portion R 100  and the second routing portion R 102  thereof. Particularly, the intercept lengths (the distance between P 1  and the connecting second lead L 120 , and the distance between P 2  and the connecting second lead L 120 ) of the second routing portions of two adjacent outmost interconnecting leads of adjacent fan-out blocks FB 1  and FB 2  are different. In an LCD panel, the first leads L 110  with smaller pitches are typically connected to bonding pads which in turn coupled with external driving Ics. One the other hand, the second leads L 120  are connected to gate lines or data lines. 
   Although only preferred embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.