Abstract:
A vertical diode of low capacitance formed in a front surface of a semiconductor substrate, including a first area protruding from the substrate surface including at least one doped semiconductor layer of a conductivity type opposite to that of the substrate, the upper surface of the semiconductor layer supporting a first welding ball. The diode includes a second area including on the substrate a thick conductive track supporting at least two second welding balls, said first and second welding balls defining a plane parallel to the substrate plane.

Description:
RELATED APPLICATIONS 
   This application is a division of prior application Ser. No. 10/489,153, filed on Mar. 10, 2004, entitled LOW-CAPACITANCE VERTICAL DIODE and now issued as U.S. Pat. No. 6,924,546. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention generally relates to the forming of diodes having low capacitance and low series resistance in semiconductor wafers. More specifically, the present invention relates to the forming of diodes having all their contacts on the front surface side in a semiconductor wafer. Such diodes are useful in certain high-frequency (radio-frequency) applications. 
   2. Discussion of the Related Art 
   A method for manufacturing a diode having reduced capacitance is described hereafter in relation with  FIG. 1  in the case of a PIN-type diode. 
   A heavily-doped semiconductor substrate  1 , generally single-crystal silicon, of a first conductivity type, for example, N-type, is used. The method starts with the epitaxial growth, on substrate  1 , of a layer  2  of same conductivity type N as substrate  1 , but more lightly doped. A heavily-doped layer  3  of the opposite conductivity type, for example, P-type, is then formed. To exhibit a reduced capacitance, the diode must have a reduced surface area. The diode surface area is limited by digging a peripheral groove  4 . Groove  4  is dug to at least reach substrate  1 . Groove  4  generally has a depth at least equal to the height of layers  2  and  3 . The entire structure is then coated with an insulating layer  5 , typically silicon oxide. Insulating layer  5  is then opened in the diode region delimited by groove  4 . A conductive material, typically aluminum, is deposited and etched, to form an anode contact  6  with layer  3 . A cathode contact (not shown) is subsequently formed by a metallization on the rear surface of substrate  1 . 
   To obtain a front surface assembly diode, it could be devised to directly form a cathode contact by opening, as illustrated in  FIG. 1 , insulating layer  5  outside of the region delimited by groove  4 , to partially expose layer  3 . Layer  5  would then be used as an implantation mask to form a heavily-doped region  7  of the same conductivity type, N, as substrate  1 . Region  7  would be formed sufficiently deeply to reach substrate  1  and form a cathode contacting area. A cathode contact  8  would then be formed on region  7 , at the front surface, at the same time as anode contact  6 . 
   However, the forming of deep heavily-doped region  7  requires an additional anneal. To obtain a PIN diode of good quality, the transition between substrate  1  and layer  2  and the junction between layers  2  and  3  must be particularly steep. The diffusion anneal would adversely affect the diode characteristics (capacitance, series resistance, breakdown voltage). 
   SUMMARY OF THE INVENTION 
   The present invention aims at providing a vertical diode having reduced or low capacitance to be assembled on the front surface of a semiconductor substrate. 
   The present invention also aims at providing a method for manufacturing such a diode which avoids the above-mentioned disadvantages. 
   To achieve these and other objects, the present invention provides a vertical diode of low or reduced capacitance formed in a front surface of a semiconductor substrate, including a first area protruding from the substrate surface including at least one doped semiconductor layer of a conductivity type opposite to that of the substrate, the upper surface of the semiconductor layer supporting a first welding ball; and a second area including on the substrate a thick conductive track supporting at least two second welding balls, said first and second welding balls defining a plane parallel to the substrate plane. 
   According to an embodiment of the present invention, the second area includes an intermediary semiconductor layer between the substrate and the semiconductor layer. 
   According to an embodiment of the present invention, the welding balls rest on a bonding surface. 
   According to an embodiment of the present invention, the first area includes a metallization between the semiconductor layer and the bonding surface of the first welding ball. 
   The present invention also provides a method for manufacturing a vertical diode having a low or reduced capacitance and formed in a front surface of a semiconductor substrate of a first conductivity type forming a first electrode of the diode, including the steps of forming a semiconductor layer of the second conductivity type; digging, outside of the diode forming region, at least until the substrate is exposed; forming on the substrate a conductive track having a thickness substantially greater than the digging depth; forming a metallization on a portion of the semiconductor layer forming a second electrode of the diode; and simultaneously forming a welding ball on said metallization and at least two welding balls on the track, said welding balls defining a plane parallel to the substrate plane. 
   According to an embodiment of the present invention, the digging step includes removing the multiple-layer formed by the semiconductor layer and the substrate everywhere except on the diode-forming region. 
   According to an embodiment of the present invention, the digging step includes removing the multiple-layer formed by the semiconductor layer and the substrate, on the one hand, at the diode periphery and, on the other hand, at a distant location in which is subsequently formed the conductive track. 
   According to an embodiment of the present invention, the step of forming a semiconductor layer of the second conductivity type is preceded by forming, on the substrate, a semiconductor layer of the first conductivity type more lightly doped than the substrate. 
   According to an embodiment of the present invention, the step of forming the metallization includes opening a window in an insulating structure covering the second electrode and of depositing a conductive material in and around said window. 
   According to an embodiment of the present invention, the step of simultaneous forming of the first and second welding balls includes the steps of opening an insulating structure covering the thick track as well as an insulating structure covering the metallization; depositing and etching a conductive material to form on the metallization a first bonding surface and on the track at least two second bonding surfaces, the first and second bonding surfaces being coplanar; and simultaneously depositing on each of the bonding surfaces a conductive material to form a welding ball. 
   The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates, in a simplified and partial cross-section view, a vertical PIN diode; 
       FIGS. 2A to 2D  illustrate, in a simplified partial cross-section view, different steps of formation of a vertical diode of small capacitance with a front surface assembly according to an embodiment of the present invention; and 
       FIG. 3  is a simplified partial top view of the diode of  FIG. 2D . 
   

   DETAILED DESCRIPTION 
   For clarity, the same elements have been designated with the same references in the different drawings. Further, as usual in the field of semiconductor representation, the various drawings are not to scale. 
   An embodiment of a vertical diode of small capacitance to be assembled by its front surface according to the present invention will be discussed hereafter in relation with  FIGS. 2A to 2D  and  3 . 
   A vertical diode of small capacitance, and thus of small surface area, is desired to be formed in a semiconductor substrate  1 , for example, single-crystal silicon, heavily doped of a first conductivity type, for example, N. It is assumed hereafter, as a non-limiting example, that the diode is of PIN type. 
   As illustrated in  FIG. 2A , a lightly-doped single-crystal silicon layer  2  of the same conductivity type N as substrate  1  is first formed, for example, by epitaxial growth. A heavily-doped P-type single-crystal silicon layer  3  is then formed. The diode surface is defined by digging into the multiple-layer formed of layers  3  and  2  and of substrate  1 . This digging may be performed over a relatively large surface area, as illustrated in FIG.  2 A. 
   Accordingly, a multiple-layer formed of layer  3 , of layer  2 , and of substrate  1  which emerges from the substantially planar surface of substrate  1  has been formed. A vertical PIN diode has thus been delimited, having the remaining portion of layer  3  forming its anode and substrate  1  forming its cathode. The structure is then coated with an insulating layer  15 . 
   As illustrated in  FIG. 2B , layer  15  is selectively opened, to expose a portion of substrate  1 . A conductive material is then deposited and etched to form a thick conductive track  16 . The upper surface of track  16  slightly protrudes from the upper surface of anode  3  of the diode. Then, the structure is coated with an insulating layer  17 . 
   As illustrated in  FIG. 2C , layers  15  and  17  are then selectively opened to partially expose the upper surface of anode  3 . A conductive layer is deposited and etched on anode  3  to form a metallization  18 . The thickness of metallization  18  is such that its upper surface is coplanar to the upper surface of track  16 . Then, the entire structure is covered with an insulating layer  19 . 
   Preferably, as shown, before deposition of insulating layer  19 , layer  17  is selectively opened to expose the upper surface of track  16 . Thus, the insulator thickness covering track  16  is equal to the insulator thickness covering metallization  18 . 
   At the next steps, illustrated in  FIG. 2D , layer  19  is selectively opened to open a window above metallization  18  and windows above track  16 . The dimensions of the windows thus opened are substantially equal. Then, a bonding layer is deposited and etched. Bonding surfaces  20  and  21  are thus formed with, respectively anode  3 - 18  and track  16 . Bonding layers  20  and  21  are substantially coplanar. Finally, the process stops with the forming of welding balls  23  and  24  respectively on bonding surfaces  20  and  21 . Welding balls  23  and  24  have substantially the same dimensions and are made of a material adapted to enabling welding with contact pads of a printed circuit or the like. 
   A diode including a contact  23  of anode  20 - 18 - 3 , to the right of  FIG. 2D  and contacts  24  of cathode  21 - 16 - 1  on a same front surface as anode contact  23 , to the left of  FIG. 2D , has thus been formed. 
   Although a single contact  24  is visible in the cross-section view of  FIG. 2D , in practice, at least two cathode contacts will be formed on track  16 . For example, as illustrated by the top view of  FIG. 3 , track  16  may have a right angle shape and three cathode contacts  24  are formed on this track. 
   Accordingly, as appears from the foregoing description, a vertical diode, the surface area (capacitance) of which can be controlled and reduced or minimized has advantageously been obtained. Further, none of the operations described in relation with  FIGS. 2B to 2D  requires any thermal processing that might adversely affect the diode performance. 
   As a non-limiting example, the natures and dimensions of the different elements of a PIN diode according to an embodiment of the present invention are the following:
         substrate  1 : heavily-doped N-type single-crystal silicon;   layers  2  and  3 : single-crystal silicon obtained by epitaxy, having a total thickness ranging from 6 to 8 μm;   digging of substrate  1  down to depth of, for example, from 7 to 9 μm;   insulating layer  15 : multiple-layer formed of a thermal silicon oxide sub-layer and of an upper sub-layer of a phosphosilicate based glass (PSG);   conductive track  16 : aluminum of a thickness from 8 to 10 μm;   windows of deposition of metallization  18  and/or of formation of bonding surfaces  20  and  21 : 70 μm×70 μm;   anode metallization  18 : aluminum having a thickness on the order of from 1 to 2 μm;   bonding surfaces  20  and  21 : titanium, nickel, and gold alloy (TiNiAu);   welding balls  23  and  24 : alloys such as PbSn, of a diameter from 50 to 100 μm.       

   The natures and dimensions of the different elements described in the preceding example are not limiting. Those skilled in the art will be able to appropriately modify them according to the technological process, for example, according to the dimensions desired for anode and cathode welding balls  23  and  24 . 
   According to an embodiment not shown, in the digging step described in relation with  FIG. 2A , epitaxial layers  3  and  2  and substrate  1  are dug into, on the one hand according to a groove delimiting the diode surface and, on the other hand, at a distant location where the cathode track is desired to be formed. Between this location and the groove, the multiple-layer formed of epitaxial layers  3 ,  2  and of substrate  1  remains in place. 
   Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the present invention is not limited to the forming, previously described as a non-limiting example, of a PIN-type diode, but applies to the forming of any type of vertical diode with contacts on its upper surface. Further, the semiconductor substrate could correspond to the anode, and not to the cathode of the diode. 
   Further, it should be noted that the exact nature of the materials used may be modified in any appropriate manner, provided to keep their insulating or conductive property such as previously described. Thus, “substrate” designates any type of single-crystal semiconductor material. The substrate may be a solid material or a semiconductor layer obtained, for example, by epitaxial growth, at the surface of a massive substrate. It may also be a specifically doped region of such a solid substrate or of such an epitaxial layer. A multiple-layer of the same nature may also be substituted to any conductive or insulating layer. Further, the deposition of any layer may be preceded by the deposition of a bonding and/or etch stop layer. 
   Further, it has previously been assumed that the cathode track would have, in top view, a non-rectilinear shape. However, it may have any shape, even rectilinear, to form two cathode welding balls non-aligned with the anode welding ball. 
   Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.