Abstract:
In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition to facilitate formation of diffusion barriers and seed layers within one chamber, thereby promoting fabrication efficiency and reducing defects.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
   This patent application is a continuation of U.S. application Ser. No. 10/211,855, filed on Aug. 1, 2002, now issued as U.S. Pat. No. 6,756,298; which is a division of U.S. application Ser. No. 09/488,098, filed on Jan. 18, 2000, now issued as U.S. Pat. No. 6,429,120; the specifications of which are hereby incorporated by reference. 

   TECHNICAL FIELD 
   The present invention concerns methods of semiconductor device or integrated circuit manufacturing, particularly methods of forming interconnects from copper and other metals. 
   BACKGROUND OF THE INVENTION 
   Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together with aluminum wires to define a specific electric circuit, such as a computer memory. 
   To form the aluminum wires, fabricators sometimes use a dual-damascene metallization technique, which takes its name from the ancient Damascan metalworking art of inlaying metal in grooves or channels to form ornamental patterns. The dual-damascene technique entails covering the components on a wafer with an insulative layer of silicon dioxide, etching small holes in the insulative layer to expose portions of the components underneath, and subsequently etching shallow trenches from hole to hole to define a wiring pattern. Fabricators then blanket the entire insulative layer with a thin sheet of aluminum and polish off the excess, leaving behind aluminum vias, or contact plugs, in the holes and thin aluminum wires in the trenches. The aluminum wires are typically about one micron thick, or about 100 times thinner than a human hair. 
   In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. See, for example, D. Edelstein et al., Full Copper Wiring in a Sub-0.25 um CMOS ULSI Technology, Technical Digest of 1997 IEDM, p. 773-776, 1997; and S. Venkatesan et al., A High Performance 1.8V, 0.20 um CMOS Technology with Copper Metallization, Technical Digest of 1997 IEDM, p. 769-772, 1997. Moreover, Applied Materials, Inc., a maker of semiconductor fabrication equipment, reports special equipment for fabricating copper-wired integrated circuits. (Applied Materials Announces First Barrier/Seed Layer System for Copper Interconnects, http://www.appliedmaterials.com/newsroom/pr-00103.html, Dec. 2, 1997.) 
   These copper-wired integrated circuits typically follow a variation of the dual-damascene method, which entails forming a copper-diffusion barrier in holes and trenches prior to filling them with copper. The typical copper-diffusion barrier is more than 30-nanometers thick and consists of tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), or tungsten nitride (WN). Filling the barrier-lined holes and trenches with copper generally entails forming a thin copper seed layer on the copper-diffusion barrier and then electroplating copper on the seed layer to finish. 
   The present inventors identified at least two problems with current techniques for making the copper wiring. The first is that typical copper-diffusion barriers add appreciable resistance to the copper wiring, and thus negate some of the advantages of using copper. The second concerns the use of separate wafer-processing chambers to form the copper-diffusion barrier and the copper seed layer. Using two chambers means that wafers are processed in one chamber to form the diffusion barrier and then transported to another chamber to form the seed layer. However, moving wafers from one chamber to another not only slows down fabrication, but also risks the addition of undesirable particles to the wafers, some of which can cause defects in resulting integrated circuits. 
   Accordingly, there is a need for better ways of making copper wiring in integrated circuits. 
   SUMMARY OF THE INVENTION 
   To address these and other needs, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition, two processes which facilitate formation of copper-diffusion barriers and seed layers within the chamber. One of the unique methods of forming barrier and seed layers entails forming a graded composition of tungsten silicide (WSi x ), nitriding the graded composition, and then depositing a copper seed layer on the nitrided composition, all within a single wafer-processing chamber to promote fabrication efficiency and reduce defects. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic side-view of an exemplary wafer-processing chamber  100  in accord with the present invention; 
       FIG. 2  is a cross-sectional view of an exemplary integrated-circuit assembly  210 , including two transistors  214   a  and  214   b  and an insulative layer  216  with via holes  216   a  and  216   b , and a trench  216   c;    
       FIG. 3  is a top view of the  FIG. 2  assembly, showing relative position of trench  216   c  and transistors  214   a  and  214   b;    
       FIG. 4  is a cross-sectional view of the  FIG. 2  assembly after formation of diffusion barrier  218  and a seed layer  220 ; 
       FIG. 5  is a cross-sectional view of the  FIG. 4  assembly after formation of a conductive structure  222  on seed layer  220 ; and 
       FIG. 6  is a block diagram of an exemplary integrated memory circuit which incorporates the present invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following detailed description, which references and incorporates  FIGS. 1-6 , describes and illustrates specific embodiments of the invention. These embodiments, offered not to limit but only to exemplify and teach the concepts of the invention, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art. 
     FIG. 1  shows an exemplary wafer-processing apparatus or system  100  which incorporates teachings of the present invention. In particular, system  100  includes a chamber  102 , a wafer holder  104 , an RF-gas-emission coil  106 , a sputter target  108 , an electron-cylotron-resonance (ECR) source  110 , an isolation valve  112 , gas inlets  114  and  116 , gas (or more generally fluid) sources  118 ,  120 ,  122 ,  124 , and  126 , and mass-flow controllers  119 ,  121 ,  123 ,  125 , and  127 . 
   More particularly, chamber  102  includes respective top and bottom plates  102   a  and  102   b . In the exemplary embodiment, chamber  102  is a cylindrical structure formed of stainless steel or glass. However, other embodiments use different structures and materials. Bottom plate  102   b  includes an opening  102   c  which is coupled to a vacuum pump (not shown). Extending through opening  102   c  is a stem portion  104   a  of wafer holder  104 . 
   Wafer holder  104  also includes a support platform  104   b  which supports one or more wafers or integrated-circuit assemblies  200 . Holder  104  is coupled through opening  102   c  to a power supply (not shown.) In the exemplary embodiment, wafer holder  104 , which is rotatable either manually or automatically, includes internal heating elements (not shown) for heating wafers or assemblies  200  to a desired temperature. In some embodiments, wafer holder  104  is a planetary wafer holder. 
   Above wafer holder  104  is RF-gas-emission coil  106 , which includes one or more turns or loops of electrically conductive tubing. Coil  106 , which is selectively couplable to a power supply (not shown), also includes a number of orifices (not shown) for emitting gas toward sputter target  108  or to a position where sputter target  108  is to be installed. 
   In the exemplary embodiment, the coil turns define a horizontal spiral; however, in other embodiments, the turns define a helical or vertical spiral. Other embodiments use horizontal or vertical spirals with the coils having regular or irregular polygonal forms. The exemplary embodiment constructs coil  106  as two turns of 6.5-millimeter-diameter tubing, with the “diameter” of the turns being greater than the width or diameter of wafer  200 . However, other embodiments tubing with regular or irregular polygonal cross-sections, for example, triangular, square, or elliptical. The exemplary orifices have a common diameter of 50 microns and are spaced about two-to-three centimeters apart along the turns of the coil. The diameter of the entire coil is generally large enough to encircle wafer holder  104 ; however, some embodiments use smaller or larger coils. Also, the exemplary coil  106  consists of the same material as sputter target  108 . 
   Sputter target  108 , which is positioned above coil  106 , is fixed to top plate  102   a  via target holders  108   a  and  108   b . Target  108  consists of a material intended for deposition on wafer  200 . The exemplary embodiment implements target  108  as a slab of copper with a circular or rectangular shape. However, the invention is not limited to any type, form, or shape of target material. In some embodiments, target  108  is coupled to a power supply (not shown), which biases it to a specific voltage level, for example, a positive, negative, or ground voltage. 
   In addition to chamber  102 , wafer holder  104 , RF-gas-emission coil  106 , and sputter target  108 , wafer-processing apparatus  100  also includes ECR source  110 , isolation valve  112 , gas inlets  114  and  116 , gas sources  118 - 126 , and mass-flow controllers  119 - 127 . ECR source  110  is selectively isolatable from the interior of chamber  102  using isolation valve  112 . When isolation value  112  is open, ECR source  110  can inject a high-energy plasma into chamber  102 . Isolation value  112  may assume any suitable manual or motor-actuated form, such as gate valve, butterfly valve, etc. 
   Gas sources  118 - 126  are coupled respectively via mass-flow controllers  119 - 127  to one of gas inlets  114  and  116 . More particularly, sources  118  and  120  are coupled via respective controllers  119  and  121  to inlet  114 . Inlet  114  is coupled to coil  106 . Sources  122 ,  124 , and  126  are coupled via respective controllers  123 ,  125 , and  127  to inlet  116 . 
   The exemplary mass-flow controllers are thermal or pressure based; however, the invention is not limited to any particular number or type of mass-flow controller. Additionally, in the exemplary embodiment, gas source  118  supplies hydrogen (H 2 ) gas; source  120  supplies argon (Ar) gas; source  122  supplies tungsten hexaflouride (WF 6 ) gas; source  124  supplies silane (SiH 4 ) gas; and source  126  supplies nitrogen (N 2 ) gas. However, the invention is not limited to any particular number or set of gas sources. 
   In general operation, apparatus  100  functions, via manual or automatic control, to apply material through physical or chemical vapor deposition onto wafer  200 . During physical vapor deposition (PVD) (more commonly known as sputtering), isolation valve  112  is open, enabling ions from ECR source  110  into the chamber. In turn, these ions dislodge matter from sputter target  108  onto wafer  200 . During chemical vapor deposition, valve  112  is closed and gases from one or more of the gases sources, for example, WF 6  and SiH 4 , are introduced into the chamber to chemically react and deposit a precipitant on wafers  200 . Additionally, to avoid contaminating sputter target  108  during this operation, coil  106  rapidly emits through its orifices a gas, for example hydrogen gas on sputter target  108 . The gas sweeps the surface of sputter target  108 , preventing its contamination during the chemical-vapor deposition (CVD.) As a further or alternative anti-contamination measure, some embodiments bias sputter target  108  to a low voltage. 
   More particularly,  FIGS. 2-5  show several partial cross-sectional views of wafer  200 , which taken collectively and sequentially, illustrate a unique exemplary method of using apparatus  100  to form diffusion-barrier and seed layers, useful in forming copper, silver, or gold interconnects. The method, as shown in  FIG. 2 , begins with a known integrated-circuit assembly or structure  210 , which can be within any integrated circuit, a dynamic-random-access memory, for example. Assembly  210  includes a substrate  212 . 
   The term “substrate,” as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures. 
   Substrate  212  supports a number of integrated elements  214 , for example transistors  214   a  and  214   b . Transistors  214   a  and  214   b  are covered by an insulative layer  216 , which, for example comprises silicon oxide, nitride, oxynitride, and polymeric materials. Layer  216  includes two exemplary via holes  216   a  and  216   b  positioned over respective transistors  214   a  and the via holes.  FIG. 3  shows a top view of the assembly, further illustrating the relative position of the trench and via holes relative the transistors. 
   The exemplary embodiment forms layer  216  using deposition, lithographic, and selective-material-removal techniques, such as reactive-ion etching. In the exemplary embodiment, via holes  216   a  and  216   b  are cylindrical with diameters of about 1000 nanometers and depths of about 500 nanometers. Trench  216   c  is less than 0.50 microns wide and at least one micron deep. The invention, however, is not limited to any particular insulative composition(s) or hole and trench dimensions. 
   Next, as shown in  FIG. 4 , the exemplary method forms a two-to-six-nanometer-thick diffusion barrier  218  over layer  216  within holes  216   a ,  216   b , and trench  216   c , more precisely on the floor and sidewalls of these structures. In the exemplary embodiment, forming the diffusion barrier entails inserting wafer  200  into chamber  102  of apparatus  100  and using the apparatus in a CVD mode to form a graded composition of tungsten silicide (WSi x ), with x varying from 2.0 to 2.5. This entails heating wafer  200  to a temper tungsten hexafluoride, and silane gases into chamber  102  using respective mass-flow controllers  119 ,  123 , and  125 . 
   The exemplary embodiment introduces the hydrogen and tungsten hexaflouride gases about one-to-three seconds before introducing the silane gas and stops introducing the silane gas about one-to-three seconds before stopping introduction of the hydrogen and tungsten hexaflouride. Note that the exemplary embodiment introduces hydrogen through coil  106 , for example at 1000 sccm milligrams per second or cubic centimeters per second, to prevent contamination of sputter target  108 . Exemplary flow rates for the silane and tungsten hexaflouride gases are respectively 1000 sccm and 14 sccm. These flow rates result in a composition of WSi 2.3 , with a growth rate of approximately 50 nanometers per minute. 
   To complete the diffusion barrier, the exemplary method nitrides the graded composition of WSi x , forming WSi x N y . The exemplary nitridation uses apparatus  100  in a PVD mode, following an ECR plasma nitridation procedure. One version of this method is described in A. Hirata et al., WSiN Diffusion Barrier Formed by ECR Plasma Nitridation for Copper Damascene Interconnection, Extended Abstracts of 1998 International Conference on Solid State Devices and Materials, p. 260-261, which is incorporated herein by reference. This entails operating mass-flow controller  121  to introduce argon gas through coil  106  into chamber  102  and thereby excite plasma generated via ECR source  110  and the introduction of nitrogen gas through inlet  116 , using mass-flow controller  127 . In the exemplary embodiment, the WSiN is not a compound-forming barrier, but a stuffed barrier, which prevents diffusion by stuffing nitrogen atoms into diffusion paths, such as interstitial sites, within the tungsten silicide. 
     FIG. 4  shows that after forming diffusion barrier  218 , the exemplary method forms a seed layer  220  of, for example, copper-, silver-, or gold-based material on top of the diffusion barrier. (As used herein, copper-, silver-, or gold-based material includes any material comprising a substantial amount of copper, silver, or gold. For example, materials containing ten or more percent (by weight) of copper, silver, or gold constitute a copper, silver, or gold-based material.) The exemplary method uses a chemical-vapor-deposition, ionized-sputtering, or DC-magnetron self-sputtering technique to form the seed layer within chamber  102 , thereby forming seed layer  220  within chamber  102  avoids the delay and contamination risk of conventional practices which transport the wafer from the chamber used for barrier formation to a separate chamber for seed-layer formation. 
   The exemplary chemical-vapor-deposition technique follows a procedure such as that described in Y. Senzaki, “Chemical Vapor Deposition of Copper Using a New Liquid Precursor with Improved Thermal Stability,” MRS Conference Proceedings of Advanced Metallization and Interconnect Systems for ULSI Applications in 1997, ULSI XIII, P. 451-455, 1998, which is incorporated herein by reference. This procedure yields copper films at a typical deposition rate of 150-170 nanometers per minute at wafer temperatures of 195-225° C. The resistance of these films falls in the range of 2.0 micro-ohm-centimeter after annealing at 400° C. for about five minutes. 
   In the exemplary embodiment, the ionized sputtering technique and DC magnetron sputtering techniques follow procedures similar to those outlined in S. M. Rossnagel et al., Metal Ion Deposition from Ionized Magnetron Sputtering Discharge,” J. Vac. Sci. Technology B, 12(1), p. 449-453, 1994. And Z. J Radzimski et al, “Directional Copper Deposition using D-C Magnetron Self-sputtering,” J. Vac. Sci Technology B 16(3), p. 1102-1106, 1998. Exemplary conditions for the ionized-magnetron sputtering include target power range of 10-30 kilowatts for a 200-300 millimeter diameter wafer (or integrated-circuit assembly), RF coil power of 3-5 kilowatts, negative DC bias of 100-200 volts, sputtering argon gas pressurized at 1-35 millitorrs. Ionized-magnetron sputtering, which provides greater acceleration of the metal deposition material than conventional sputtering, forces the metal to more closely conform to the interior profiles of holes and trenches and thus facilitates formation of a conductive structure with less electrical resistance. 
   After completion of seed layer  220 , the exemplary method removes wafer  200  from chamber  102  and completes filling the holes and trenches with a conductive material, for example, a copper-, silver-, or gold-based material, as indicated in  FIG. 5 . (Some embodiments use a different materials for the seed layer and the subsequent conductive fill material.) The exemplary method completes the filling through electroplating of copper onto the seed layer. Mechanical, chemical, or chemical-mechanical planarization then removes any excess metal, ensuring a substantially planar surface for formation of subsequent metallization levels according to the same or alternative procedures. 
     FIG. 6  shows one example of the unlimited number of applications for the interconnection of the present invention: a generic integrated memory circuit  600 . Circuit  600 , which operates according to well-known and understood principles, is generally coupled to a processor (not shown) to form a computer system. More precisely, circuit  600  includes a memory array  642  which comprises a number of memory cells  643   a - 643   d , a column address decoder  644 , and a row address decoder  645 , bit lines  646   a - b , word lines  647   a - b , and voltage-sense-amplifier circuit  648  coupled to bit lines  646   a - b . 
   In the exemplary embodiment, each of the memory cells, the address decoders, and the amplifier circuit includes one or more copper-, silver, or gold-based conductors according to the present invention. Other embodiments, use conductors of other materials, made in accord with methods of the present invention In addition, connections between the address decoders, the memory array, the amplifier circuit are implemented using similar interconnects. 
   CONCLUSION 
   In furtherance of the art, the inventors have presented an apparatus and a method for making diffusion barriers and seed layers in a single processing chamber. The exemplary apparatus includes a wafer-processing chamber having equipment for chemical-vapor deposition and physical vapor deposition, while the exemplary method uses this chamber in a chemical-vapor-deposition mode to form a diffusion barrier and in a physical-vapor deposition mode to form a seed layer. Forming the diffusion barrier and seed layer in a single chamber not only skips the conventional step of transporting the wafer from one chamber to another to form the seed layer, but also avoids the attendant risk of contamination during transport. 
   The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.