Abstract:
A method and motor controller for sensing motor winding current. An FET drive transistor has its ON resistance periodically increased to about five times the normal ON resistance for short sensing intervals during motor drive. An analog-to-digital converting senses the voltage across this FET during the sensing intervals. The resulting digital signal is used to calculate motor current. The time at high ON resistance is much less than the time at normal. The ON resistance can be changed using two FETs or one FET with gate fingers over differing parts of the channel region.

Description:
CLAIM OF PRIORITY  
       [0001]     This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 60/648,814 filed Jan. 31, 2005. 
     
    
     TECHNICAL FIELD OF THE INVENTION  
       [0002]     The technical field of this invention is motor drive circuits and more particularly motor current sensing.  
       BACKGROUND OF THE INVENTION  
       [0003]     Sensing current across a turned-on FET is a common practice in motor control applications. In the case of small stepper motors, this signal current is about 10 to 40 mA. This current level is too low to effectively sense across the 5 ohms ON resistance typical for an N-channel transistor. Digital current sensing thus typically requires amplification of this small signal before conversion by an analog-to-digital converter (ADC). The operational amplifier required for this amplification introduces additional expense into the motor control circuit.  
       SUMMARY OF THE INVENTION  
       [0004]     This invention operates the N-channel in a novel manner to sense the stepping motor current. Initially, a large portion of the output transistor&#39;s gate is turned OFF. This raises the ON resistance to a minimum of 25 ohms. This increased resistance results in a signal 5 times larger than with a typical 5 ohm ON resistance. The output transistor is driven in this manner for the required settling time of the ADC. The ADC then samples the current. Then the entire output transistor is turned ON resulting in an ON resistance typically 5 ohms. The time for driving the stepper motor on step is 5 to 10 mS. The current measurement requires about 5 μS or less, which is about 0.1% or less of the stepping time. The loss of drive is not noticeable in stepping performance. The signal magnitude required for the current measurement is relative to other measurements taken near the same time. Thus the current measurement is self-calibrating. Variations in the ON resistance do not appreciably affect the calculated results.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     These and other aspects of this invention are illustrated in the drawings, in which:  
         [0006]      FIG. 1  illustrates a prior art current sensing technique applicable to a motor drive via an H bridge circuit;  
         [0007]      FIG. 2  illustrates the sensing intervals of this invention relative to the stepper pulse drive period;  
         [0008]      FIG. 3  illustrates a two FET manner of control of the ON resistance; and  
         [0009]      FIG. 4  illustrates the construction of the system of this invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0010]     This invention raises the ON current of the sensing transistor during short intervals of the stepper motor drive. This greatly increases gain of the sensing circuit. As consequence an operational amplifier is not needed to boost the level of the current signal. The ON current is dynamically changed during the stepper motor drive. By operating mostly at the prior ON resistance, this invention has negligible effect on the stepping operation. This technique is vastly simpler than the prior art operational amplifier and has the same effect as amplification.  
         [0011]      FIG. 1  illustrates a prior art circuit  100  that uses ON current sensing. Load  101  including resistance R, inductance L and back-electromotive force voltage source EMF is in an H bridge configuration between four FET drive transistors. The four FET drive transistors are P-channel FET  102 , N-channel FET  103 , P-channel FET  104  and N-channel FET  105 . These FETs are driven by drive circuit  110  including AND gates  111 ,  112 ,  113  and  114 . In the typical circuit P-channel FET  104  and N-channel FET  105  are semi-statically driven via an enable input and AND gates  113  and  114 . P-channel FET  102  and N-channel FET  103  are typically pulse width modulated (PWM) via a data input.  
         [0012]     In the prior art technique, the current through load  101  is determined by sensing the voltage across N-channel FET  105  at the V sense  terminal while N-channel FET  105  is ON. In the typical case the ON resistance of N-channel FET  105  is 5 ohms. For a typical load current of 10 to 40 mA this yields a sensing voltage at V sense  of 50 to 200 mV. This voltage level is generally too small to be sensed directly by an ADC to generate a digital current signal for a digital microcontroller controlling the motor drive. The typical solution to this problem is to use an operational amplifier to amplify the analog voltage to a level readable by an ADC.  
         [0013]     This invention proposes to momentarily increase the ON resistance of the N-channel FET to a higher value, such as 25 ohm. This change amplifies the voltage at V sense  by a factor of 5 to 250 to 1000 mV. Voltages at this level are suitable for direct sensing by an ADC. This eliminates the need for an operational amplifier.  
         [0014]     This change in ON resistance could have an adverse effect on the motor drive performance. To minimize this problem, the time that the ON resistance remains at the increased level is minimized. This is illustrated in  FIG. 2 . The first curve is the load current during the typical 5 to 10 mS of a stepper pulse. The increased resistance is not need for the entire pulse interval. The increased resistance need only be applied during the sampling/settling period of the ADC. For a typical ADC used for this purpose this period is much shorter than the stepper pulse interval. This period could be in the range of 5 μS or less. The lower curve in  FIG. 2  shows periodic ADC samples. The ON resistance of the N-channel FET is increased to 25 ohms for these sampling periods as illustrated in middle curve of  FIG. 2 . Because the sampling interval is much shorter than the stepper pulse interval, the overall change observed by load  101  is virtually unchanged.  
         [0015]      FIG. 3  illustrates a preferred manner of control of the ON resistance.  FIG. 3  illustrates portions of the H bridge circuit illustrated in  FIG. 1  necessary to understand this invention. N-channel FET  105  is replaced with N-channel FET  301  and N-channel FET  302 . The ON drive signal is initially applied directly to the gate of N-channel FET  301  which turns ON immediately. N-channel FET  301  is constructed with a narrower channel than used for N-channel FET  105 . If the channel width is one fifth as wide, N-channel FET  301  would have an ON resistance of five times as much, such as 25 ohms rather than 5 ohms.  
         [0016]     N-channel FET  302  receives the ON drive signal via a select circuit  310  including P-channel FET  311 , N-channel FET  312 , inverter  313  and N-channel FET  314 . With the select signal OFF, both P-channel FET  311  and N-channel FET  312  are cut off and thus the ON signal does not reach the gate of N-channel FET  302 . In addition, N-channel FET  314  is ON discharging the gate of N-channel FET  302  keeping it OFF. When the select signal is ON, both P-channel FET  311  and N-channel FET  312  are conducting and thus the ON signal is applied to gate of N-channel FET  302 . N-channel FET  314  is OFF and thus does not change the signal at the gate of N-channel FET  302 . Thus the ON and OFF state of N-channel FET  302  is controlled by the select signal. This permits selective actuation of only N-channel FET  301  or of both N-channel FETs  301  and  302 . The channel width of N-channel  302  is selected for an ON resistance of 6.25 ohms. When both N-channel FETs  301  and  302  are ON, the effective resistance is:  
         1       1   25     +     1   6.25         =       1       1   25     +     4   25         =       1     5   25       =       25   5     =   5             
 
 Thus the circuit of  FIG. 3  achieves the previous 5 ohm ON resistance when both N-channel FETs  301  and  302  are ON. The select signal is active only during the measurement interval illustrated in  FIG. 2 . 
 
         [0017]     Gate fingers over the channel of the N-channel FET may be used to provide similar control. A first set of gate fingers over a first portion of the channel are initially activated. Following the ADC interval, a second set of additional gate fingers are also activated. Proper control of the channel width of these two sets of gate fingers permits ON resistance control similar to the two FET technique described above. This technique had almost zero increase in silicon cost. The FETs typically used in these applications include many gate fingers. This invention merely disables some of these existing gate fingers during the sampling interval.  
         [0018]      FIG. 4  illustrates the construction of the system of this invention.  FIG. 1  shows load  101  and FETs  102 ,  103 ,  104 ,  301  and  302  in the H bridge configuration as illustrated in  FIG. 1 . Analog-to-digital converter  410  receives the V sense  signal and generates a digital output. FET drivers  120  controls the ON and OFF operation of these FETs based upon signals received from microcontroller  420 . Microcontroller  420  is a programmable microprocessor or digital signal processor with memory and a program for the desired motor control. Microcontroller  420  calculates motor current by controlling FET drivers  120  to control FETs  301  and  302  as described above while triggering analog-to-digital converter  410  to sample and digitize V sense .