Abstract:
A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output NMOS pass device. The voltage regulator uses an inverting inter-stage variable gain amplifier to adjust its gain in response to a load current passing through the output NMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The inverting inter-stage variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power NMOS device such that as the load current increases, the gain decreases, wherein the unity gain bandwidth associated with the loop formed by a compensation capacitor is kept substantially constant.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates generally to voltage regulators, and more particularly to a Miller compensated NMOS low drop-out (LDO) voltage regulator using an inverting variable gain stage to improve stability and optimize power supply rejection ratio (PSRR).  
           [0003]    2. Description of the Prior Art  
           [0004]    Active compensating capacitive multiplier structures and techniques, e.g. nested Miller compensation, are well known in the art. The specific type of compensating circuit used is dependent upon the particular application. One application of improving phase margin for example, takes advantage of the Miller Effect by adding a Miller compensation capacitance in parallel with an inverting gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert g. Meyer,  Analysis and Design of Analog Integrated Circuits , Third Ed., John Wiley &amp; sons, Inc. N.Y., 1993, Ch. 9, especially pp. 607-623.  
           [0005]    A typical architecture of a Miller compensated NMOS LDO voltage regulator  100  is shown in FIG. 1. The LDO  100  comprises an error amplifier A 1 , an inverting inter-stage gain amplifier A 2 , a low impedance driver BUF, a NMOS power transistor NSW, feedback resistors R 1  and R 2 , and an output filter capacitor C_FILT with equivalent series resistor (ESR) R_ESR. It can be seen that the inverting inter-stage gain amplifier A 2  and the low impedance driver BUF get their supply from a charge pump  102 , that allows the gate of the NMOS power transistor NSW to be pulled up much higher than its drain, thus broadening the input range of the LDO  100 . It can be appreciated that the charge pump  102  is generally shared by multiple NMOS LDO&#39;s.  
           [0006]    Similar to PMOS LDO&#39;s, the ultra-wide range of load current Iout  104  (usually from 10&#39;s μA to 100&#39;s mA) and the large output filter capacitor C —FILT ( 1 μF to 10 μF) also present significant challenges associated with compensation design for NMOS LDO&#39;s. The LDO  100  depicted in FIG. 1, for example, will very likely remain unstable if no special effort is taken to stabilize the Miller compensation loop. An analysis of the LDO  100  demonstrates the inter-stage gain amplifier A 2  serves a critical function to split the poles. Amplifier A 2  is expected to have high enough gain under low current conditions to push the second pole close or beyond unity gain bandwidth of the LDO. This high gain can be problematic however, under high load conditions where the second pole may be pushed up to a few MHz. Since this second pole is also the unity gain bandwidth of the Miller compensation loop itself, this huge bandwidth nearly always guarantees this loop is unstable, given the multiple stages inside the loop which all contribute to phase shift, albeit at a fairly high frequency range. Since the LDO  100  is a 4-pole system, the unity gain bandwidth must be close to or less than the second highest pole, or the system  100  will become unstable.  
           [0007]    In view of the foregoing, a need exists for an LDO amplifier circuit architecture and technique capable of achieving better stability and higher PSRR performance from an internally compensated NMOS low drop-out voltage regulator than that presently achievable using conventional “Miller” or “Pole-splitting” techniques presently known in the art.  
         SUMMARY OF THE INVENTION  
         [0008]    The present invention is directed to a circuit architecture and technique for achieving good phase margin, highly desirable open-loop gain, and high power supply ripple rejection (PSRR) from an internally compensated NMOS low drop-out voltage regulator that is implemented to formulate a modified type of Miller compensation. This good phase margin and high open-loop gain is achieved by using an inverting variable gain stage that ensures the dominant pole is always at the same internal node regardless of load current (no “pole swapping” allowed). The present circuit further provides high PSRR by implementing the inverting variable gain single stage amplifier such that a differential input has one input tied to C c  while the other is at a dc voltage referenced to ground. Properly setting the input reference improves the PSRR.  
           [0009]    A conventional NMOS low drop-out voltage regulator is generally comprised of two gain stages in order to promote simplification of any related compensated closed loop system. The input stage of such a voltage regulator is formulated via a differential amplifier. The output stage comprises a series pass NMOS device. These two stages are generally coupled together via an impedance buffer, typically a source follower, to enable the input stage high impedance output to drive the large gate capacitance of the series pass NMOS device and thereby minimize the effect of an internal pole that would otherwise interfere with loop compensation. Miller capacitor multiplication, or “Pole-splitting”, is generally used by those skilled in the art to internally compensate the voltage regulator for use with ceramic output capacitors where the circuit designer cannot rely on an external compensating zero formed by the ESR associated with an electrolytic capacitor. Generally, the Miller capacitor is tied across an inverting amplifier, a buffer and the NMOS pass device. It should be noted that the Miller capacitor will shunt the input stage amplifier output (also the inverting input of the inverting amplifier) to ground through a filter capacitor at high frequency, thus reducing the sensitivity of the inverting amplifier output to the supply noise; while the second input of the inverting amplifier is most preferably a voltage referenced to ground. This will help the gate of the NMOS pass device better reject supply noise, and hence improve the PSRR. In view of the foregoing, the present invention provides a low drop-out (LDO) architecture that employs an inverting variable gain stage to improve the internal compensation and achieve high PSRR performance from an internally compensated NMOS LDO voltage regulator.  
           [0010]    A preferred embodiment of the present invention comprises a differential amplifier input stage, a variable gain, inversion, single stage differential amplifier second stage, and an output stage comprising a series pass NMOS device. The second and output stages are coupled together via an impedance buffer (e.g., source follower, or unity-gain feedback amplifier) to enable the input stage high impedance output to drive the large gate capacitance of the series pass NMOS device and thereby minimize the effect of an internal pole that would otherwise interfere with loop compensation. The inversion, variable gain differential amplifier stage has one input tied to C c  and the other tied to a dc voltage referenced to ground. The Miller capacitance is then tied across multiple stages, i.e. the variable gain stage, the buffer, and the power NMOS.  
           [0011]    A feature of the present invention is associated with a higher frequency pole at the filter capacitor achieved through partitioning the LDO into a two stage amplifier and using Miller capacitance for the compensation wherein the G m  of the power NMOS is boosted at low load current and cut down at high load current using a wide band inversion, variable gain stage.  
           [0012]    Another feature of the present invention is associated with better PSRR at high frequency by referencing the second input of the variable gain stage to ground thus minimizing the sensitivity of its output to supply noise.  
           [0013]    Yet another feature of the present invention is associated with a flexible internally compensated NMOS low drop-out voltage regulator capable of functioning with a wide range of output capacitors and ESR values.  
           [0014]    Still another feature of the present invention is associated with providing an internally compensated NMOS low drop-out (LDO) voltage regulator having a Miller compensation loop that remains stable over a wide load current range to maintain the stability of the LDO.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    Other aspects, features and attendant advantages of the present invention will be readily appreciated as the invention becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings in which like reference numerals designate like parts throughout the figures thereof and wherein:  
         [0016]    [0016]FIG. 1 illustrates a very well known low drop-out (LDO) voltage regulator using an NMOS pass device;  
         [0017]    [0017]FIG. 2 is a small signal model of the LDO depicted in FIG. 1;  
         [0018]    [0018]FIG. 3 illustrates an NMOS LDO using a load current controlled variable gain stage according to one embodiment of the present invention;  
         [0019]    [0019]FIG. 4 illustrates an NMOS LDO controller according to one embodiment of the present invention using CMOS process;  
         [0020]    [0020]FIG. 5 illustrates a more detailed view of the error amplifier stage and the inversion gain stage of the NMOS LDO controller shown in FIG. 4;  
         [0021]    [0021]FIG. 6 illustrates a more detailed view of the unity-gain buffer portion of the NMOS LDO controller shown in FIG. 4;  
         [0022]    [0022]FIG. 7 is a top level schematic diagram of the NMOS LDO controller shown in FIG. 4;  
         [0023]    [0023]FIG. 8 illustrates an AC response simulation of open loop gain and phase of the NMOS LDO controller shown in FIG. 1 without variable gain amplification under both minimum and maximum load conditions;  
         [0024]    [0024]FIG. 9 illustrates an AC response simulation of open loop gain and phase of the Miller loop portion of the NMOS LDO controller shown in FIG. 1 without variable gain amplification under both minimum and maximum load conditions;  
         [0025]    [0025]FIG. 10 illustrates an AC response simulation of open loop gain and phase of the Miller loop portion of the NMOS LDO controller shown in FIGS.  3 - 7  with variable gain amplification under both minimum and maximum load conditions; and  
         [0026]    [0026]FIG. 11 illustrates an AC response simulation of open loop gain and phase of the NMOS LDO controller shown in FIGS.  3 - 7  with variable gain amplification under both minimum and maximum load conditions. 
     
    
       [0027]    While the above-identified drawing figures set forth alternative embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]    A typical architecture of a Miller compensated NMOS LDO voltage regulator  100  is shown in FIG. 1. The LDO  100  comprises and error amplifier A 1 , an inverting inter-stage gain amplifier A 2 , a low impedance driver BUF, a NMOS power transistor NSW, feedback resistors R 1  and R 2 , and an output filter capacitor C_FILT with equivalent series resistor (ESR) R_ESR. The inverting inter-stage gain amplifier A 2  and the low impedance driver BUF can be seen to be supplied from a single charge pump  102  that allows the gate of the NMOS power transistor NSW to be pulled up much higher than its drain, thus broadening the input range of the NMOS power transistor NSW. Such a charge pump  102  is generally shared by multiple NMOS LDO&#39;s  100 .  
         [0029]    As with PMOS LDO&#39;S, the ultra-wide range of load current Iout  104  (usually from 10&#39;s μA to 100&#39;s mA) and the large output filter capacitor C_FILT (1 μF to 10 μF) also present significant challenges on compensation designs associated with NMOS LDO&#39;s. The LDO  100  depicted in FIG. 1, for example, is very likely still unstable if no special effort is taken to stabilize the Miller compensation loop. A stability analysis of the LDO  100  is now set forth herein below to better demonstrate the stability problems associated with the LDO  100  when subjected to a wide range of load currents.  
         [0030]    [0030]FIG. 2 is a small signal model of the NMOS LDO  100  illustrated in FIG. 1; where resistors Ro 1  and Ro 2  are the output impedances of A 1  and A 2 ; resistor Ro 3  is the total resistive load at the final output; capacitors Cp 1  and Cp 2  are the parasitic capacitance at the outputs of A 1  and A 2 ; resistor Ro_buf is the equivalent output impedance of the driver BUF; capacitor Cg_NSW is the total capacitance at BUF output (mainly the NMOS power transistor NSW gate capacitance); and resistor Ro_NSW is the output impedance of the NMOS power transistor NSW, that is the same as its transconductance gm 3 .  
         [0031]    The foregoing stability analysis is commenced by first deriving the pole and zero positions. An analysis of the driver stage is simplified by considering the driver stage to be an ideal unity gain buffer, where V GATE =V 02 . Further, the load at the output of each stage is summed to Z 01 , Z 02  and Z 03 , where  
           Z   01     =       R   01       1   +       sC   p1          R   01             ,       Z   02     =           R   02       1   +       sC   p2          R   02                         and                   Z   03       =         R   03       1   +       sC   FILT          R   03           .                               
 
         [0032]    Using nodal analysis, the following equations are then obtained:  
                 (       V   03     -     V   01       )     ·   sCp     =         V   01       Z   01       +       g   m1          V   in                 (   1   )                   g   m2     ·     V   01       =     -       V   02       Z   02                 (   2   )                     (       V   02     -     V   03       )     ·     g   m3       -       V   03       Z   03         =       (       V   03     -     V   01       )        sCc             (   3   )                               
 
         [0033]    Similar to the analysis of a Miller compensated two stage amplifier, after reasonable approximations are made, the transfer function appears as:  
                 V   03       V   in       =         g   m1          g   m2          R   01            R   02          (     1   -     sCc       g   m2          R   02          g   m3           )             (     1   +       sCc   ·     g   m2            R   02          R   01         )          (     1   +       sC   FILT         g   m2          R   02          g   m3           )                 (   4   )                               
 
         [0034]    According to equation (4), the dominant pole, second pole and unity gain bandwidth respectively are:  
           f   pd     =     1     2                   π   ·       R   01          (       g   m2          R   02        Cc     )               ;       f   p2     =         g   m2            R   02     ·     g   m3           2                   π   ·     C   FILT             ;                  f   UGB     =       g   m1       2                   π   ·   Cc                                 
 
         [0035]    It can be seen from the above equations, the inter-stage gain amplifier A 2  serves a critical function to split the poles. Especially at low load current conditions where g m3  is minimal, amplifier A 2  is expected to have high enough gain (about 50-60 dB) to push the second pole close or beyond the unity gain bandwidth of the LDO. It can be appreciated that a reasonably high output impedance R 02  is needed to achieve this, for a single stage A 2 . This high gain associated with amplifier A 2  can be problematic at high load conditions however, where the transconductance g m3  is very high (i.e., a few hundred mSiemens), and the second pole is pushed up to a few MHz. As discussed in further detail herein below, the second pole is also the unity gain bandwidth of the Miller compensation loop itself, i.e. the local loop from V 01  to V 03  back to V 01 . This huge bandwidth nearly always guarantees this local loop is unstable, given the multiple stages inside the local loop, which all contribute to phase shift, albeit at a pretty high frequency range. These concepts are better illustrated by deriving the transfer function from V 01  to V 03  in which the frequency response of the driver BUF must be taken into account since the pole at its output will fall into the frequency range of interest. The transfer function of the driver BUF can be assumed to be a BUF  
         (   s   )     =       1     1   +     s   /     p   BUF           .                           
 
         [0036]    Substituting equation (2) into equation (3) and adding a BUF  to the V 02  term produces:  
                   (         -     g   m2            Z   02          V     01      aBUF         -     V   03       )     ·     g   m3       -       V   03       Z   03         =       (       V   03     -     V   01       )     ·   sCc             (   5   )                               
 
         [0037]    Replacing Z 02  with  
           R   02       1   +       sC   p2          R   02           ,                         
 
         [0038]    Z 03  with  
           R   03       1   +       sC   FILT          R   03           ,                         
 
         [0039]    and a BUF  with  
         1     1   +     s   /     p   BUF           ,                         
 
         [0040]    then provides the following transfer function:  
                 V   03       V   01       =         -     g   m2              R   02          (     1   +         sCc        (     1   +       sC   p2          R   02         )            (     1   +     s   /     p   BUF         )         (       g   m2          R   02          g   m3       )         )             (     1   +       s        (       C   FILT     +   Cc     )         g   m3         )          (     1   +       sC   p2          R   02         )          (     1   +     s   /     p   BUF         )                 (   6   )                               
 
         [0041]    Given that the filter capacitor C_FILT is very large, the dominant pole is most likely at the output. The unity gain bandwidth (assuming a single pole roll-off for the moment) is then given by:  
           f     UGB        (   miller   )         =         g   m2            R   02     ·     g   m3           2                   π   ·     C   FILT             ,                         
 
         [0042]    which is also the second pole of the LDO  100 . Since equation (6) shows a 3-pole system, the system will be unstable unless one can make the unity gain bandwidth close to or less than the second highest pole. Given that DRV in LDO  100  is a high impedance node, and G_NSW in LDO  100  is a high capacitance node, a bandwidth of a few MHz will make it extremely difficult, if not impossible, to stabilize this Miller compensation loop. The present inventor recognized the foregoing stability problems and that these stability problems could be solved by making the gain of A 2  variable with load current (i.e., high gain at light load and low gain at high load).  
         [0043]    [0043]FIG. 3 accordingly illustrates an NMOS LDO  200  using a load current controlled variable gain stage  202  according to one embodiment of the present invention. LDO  200  is primarily different from LDO  100  in that the inverting inter-stage gain amplifier A 2  has a variable gain and a current sensing block  204  to adjust the gain of amplifier A 2 . According to one embodiment, the gain is at its maximum when load current is light, and then drops continuously in response to an increasing load current. The decreasing amplifier A 2  gain (g m2 R 02 ) then compensates the increased NMOS power transistor NSW transconductance (g m3 ). The span of the unity gain bandwidth of the Miller capacitor loop over a range of load currents is thus greatly reduced, affording a lesser bandwidth to maintain loop stability with changing load current.  
         [0044]    It can be appreciated that although the current sensing block  204  can be implemented in a number of different ways, a preferred embodiment employs a small diode connected NMOS shunt  302  between the output of A 2  (DRV) and the output of the LDO (VOUT) such as seen in the LDO controller  300  depicted in FIG. 4. This preferred embodiment only requires that the low impedance driver BUF be a real unity gain buffer without level shift, which excludes any type of source followers. This particular diode NMOS embodiment has multiple benefits as discussed further herein below with reference to FIG. 4.  
         [0045]    [0045]FIG. 4 illustrates an NMOS LDO controller  300  according to one embodiment of the present invention using a CMOS process. The current sensing circuit (shunt)  302  can be seen to include a diode NMOS ND 1  in series with a resistor RSS. The shunt  302  is connected between the DRV node and VOUT, which are also the gate and source respectively of the output power transistor NSW. Under a light load, the V gs  of the output power transistor NSW is very small; hence the diode NMOS ND 1  is turned off and amplifier A 2  can have its maximum gain. As the load increases, the V gs  of the output power transistor NSW increases; and the diode NMOS ND 1  gradually turns on to shunt the output of amplifier A 2  thereby reducing its gain. An important benefit provided by this scheme is associated with the shunt path that also lowers the impedance at the DRV node and helps to push out the parasitic pole as the load current increases. The series resistor RSS can have a value appropriately chosen to limit the current through the diode NMOS ND 1  under high loading to ensure a desired minimum gain from the inverting inter-stage gain amplifier A 2 .  
         [0046]    [0046]FIG. 5 illustrates a more detailed view of the error amplifier stage A 1  and the inversion gain stage A 2  of the NMOS LDO controller  300  shown in FIG. 4.  
         [0047]    [0047]FIG. 6 illustrates a more detailed view of the unity-gain buffer portion of the NMOS LDO controller  300  shown in FIG. 4.  
         [0048]    [0048]FIG. 7 is a higher (top) level schematic diagram of the NMOS LDO controller  300  shown in FIG. 4.  
         [0049]    [0049]FIG. 8 illustrates AC response simulation waveforms  400  of open loop gain and phase of the NMOS LDO controller shown in FIG. 1 without variable gain amplification under both minimum and maximum load conditions.  
         [0050]    [0050]FIG. 9 illustrates AC response simulation waveforms  500  of open loop gain and phase of the Miller loop portion of the NMOS LDO controller  100  shown in FIG. 1 without variable gain amplification under both minimum and maximum load conditions. It can be seen that at maximum load (300 mA), the bandwidth of the Miller loop grows to about 2 MHz, depicted as point  502 ; while the phase shift reaches 180 degrees at about 600 kHz, depicted as point  504 . These results indicate an unstable Miller loop that causes the LDO  100  open loop gain to have a peak and corresponding phase jump up as shown in the FIG. 8 waveforms  400 . Although it appears this LDO  100  has a good phase margin, a transient simulation will therefore definitely demonstrate that oscillations can occur, indicating the LDO  100  is undesirably unstable under certain operating conditions.  
         [0051]    [0051]FIG. 10 illustrates AC response simulation waveforms  600  of open loop gain and phase of the Miller loop portion of the NMOS LDO controller shown in FIGS.  3 - 7  with variable gain amplification under both minimum and maximum load conditions.  
         [0052]    [0052]FIG. 11 illustrates AC response simulation waveforms  700  of open loop gain and phase of the NMOS LDO controller shown in FIGS.  3 - 7  with variable gain amplification under both minimum and maximum load conditions. Comparing FIGS. 11 and 8 at maximum load (300 MA), it can be seen the LDO  300  open loop response no longer has the gain peak and phase jump, and hence looks just like a classic two-stage amplifier response. In summary explanation of the above, by making the gain of amplifier A 2  vary with load current, one can maintain a good Miller loop phase margin over a wide load current range, and thereby eliminate one source of instability otherwise associated with a Miller compensated NMOS LDO.  
         [0053]    This invention has been described in considerable detail in order to provide those skilled in the LDO circuit art with the information needed to apply the novel principles and to construct and use such specialized components as are required. In view of the foregoing descriptions, it should be apparent that the present invention represents a significant departure from the prior art in construction and operation. However, while particular embodiments of the present invention have been described herein in detail, it is to be understood that various alterations, modifications and substitutions can be made therein without departing in any way from the spirit and scope of the present invention, as defined in the claims which follow. For example, while the embodiments set forth herein illustrate particular types of transistors, the present invention could just as well be implemented using a variety of transistor types including, but not limited to, e.g. CMOS, BiCMOS, Bipolar and HBT, among others. Further, while particular embodiments of the present invention have been described herein with reference to structures and methods of current and voltage control, the present invention shall be understood to also parallel structures and methods of current and voltage control as defined in the claims.