Abstract:
Objects are to solve inhibition of miniaturization of a memory element and complexity of a manufacturing process thereof and to provide a nonvolatile memory device and a semiconductor device each having the memory device, in which data can be additionally written except at the time of manufacture and in which forgery or the like caused by rewriting of data can be prevented, and a memory device and a semiconductor device that are inexpensive and nonvolatile. The present invention provides a semiconductor device that includes a plurality of memory elements, in each of which a first conductive layer, a second conductive layer disposed beside the first conductive layer, and a mixed film that are disposed over the same insulating film. The mixed film contains an inorganic compound, an organic compound, and a halogen atom and is disposed between the first conductive layer and the second conductive layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to memory devices and semiconductor devices each having circuits that include memory elements and to a method for manufacturing the memory devices. 
         [0003]    A semiconductor device in this specification refers to all types of devices which can function by use of semiconductor characteristics, such as electro-optic devices, semiconductor circuits, and electronic devices. 
         [0004]    2. Description of the Related 
         [0005]    As described in Reference 1 (United States Patent Application Publication No. 2005-0006640), a memory element that uses an organic compound typically has a structure in which two electrodes as two terminals of the memory element are provided above and below an organic compound layer. 
       SUMMARY OF THE INVENTION 
       [0006]    Examples of memory circuits provided in semiconductor devices include dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric random access memories (FeRAMs), mask read only memories (mask ROMs), electrically programmable read only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs), flash memories, and the like. These memory circuits have the following problems. As regards DRAMs and SRAMs that are volatile memory circuits, in which data are erased when power is turned of, it is necessary to write data every time the power is turned on. As regards FeRAMs, although they are nonvolatile memory circuits, the number of manufacturing steps thereof is increased because capacitors each including a ferroelectric layer are used therein. As regards mask ROMs, although they each have a simple structure, it is necessary to write data during manufacturing steps thereof, and data cannot be additionally written. As regards EPROMs, EEPROMs, and flash memories, although they are nonvolatile memory circuits, the number of manufacturing steps thereof is increased because elements each having two gate electrodes are used therein. 
         [0007]    In a typical memory circuit using an organic compound, the organic compound is provided between a pair of upper and lower electrodes to form a memory element. When the electrode is formed over an organic layer, the organic layer is affected depending on the formation temperature of the electrode, and thus there is the limitation on the formation temperature. Because of this limitation of the temperature, there is the limitation on a formation method of an electrode, and a desired electrode cannot be formed. This creates a problem in that miniaturization of an element is inhibited. A problem related to an electrode formed over an organic layer is needed to be solved in terms of inhibition of the element miniaturization. 
         [0008]    Furthermore, in the case of the memory element described in Reference 1 in which a pair of electrodes as two terminals is formed above and below an organic layer, the plurality of steps are needed to form the pair of electrodes because the electrodes are each provided above and below the organic layer. Unfortunately, this makes a manufacturing process complicated. The complicated manufacturing process is a problem that is needed to be solved in terms of manufacturing cost. 
         [0009]    In the case where memory elements are considered to be mounted in portable information terminals or small pieces such as chips, it is preferable to perform writing and reading data to/from the memory element with limited power. It is an object to reduce power consumption that is needed for writing and reading data to/from the memory element. 
         [0010]    In view of the foregoing problems, it is an object of the present invention to solve the inhibition of miniaturization of memory elements and complexity of a manufacturing process. It is another object to provide a nonvolatile memory device in which data can be additionally written except at the time of manufacture and in which forgery or the like caused by rewriting of data can be prevented, and a semiconductor device having the nonvolatile memory device. It is further another object to provide an inexpensive nonvolatile memory device and a semiconductor device having the nonvolatile memory device. 
         [0011]    In view of the above objects, one aspect of the present invention is a memory element in which a first conductive layer, a second conductive layer disposed beside the first conductive layer, and a mixed film of an inorganic compound, an organic compound, and a halogen atom are disposed over the same insulating film. The mixed film is disposed between the First conductive layer and the second conductive layer. The present invention solves at least one of the above objects. 
         [0012]    Specific examples of the inorganic compound include molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and the like. Alternatively, indium oxide, zinc oxide, or tin oxide can be used. However, there is no limitation to the substances described here, and any other substance may be used. 
         [0013]    A hole-transporting material is suitable for use as the organic compound. Examples of such material includes aromatic amine compounds such as 4,4′-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (NPB, 4,4′-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (TPD), 4,4′,4″-tris(N,N-diphenylamino)triphenylamine (TDATA), 4,4′-bis(N-{4-[N′-(3-methylphenyl)-N′-phenylamino]phenyl}-N-phenylamino)biphenyl (DNTPD), and the like. Alternatively, an anthracene derivative such as 9,10-di(phenyl)anthracene can be used. However, there is no limitation to the substances described here, and any other substance may be used. 
         [0014]    Fluorine or chlorine is suitable for use as the halogen atom. However, there is no limitation to the substances described here, and any other substance may be used. 
         [0015]    The inorganic compound and the organic compound are mixed to form a charge-transfer complex, in which the carrier density is increased, and accordingly, the conductivity is improved. The conductivity value is extremely higher than that of an organic semiconductor film. 
         [0016]    By addition of the halogen atom to the mixture of the inorganic compound and the organic compound, the conductivity is significantly increased; and, the mixed film is characterized in that it can be separated easily from the substrate. 
         [0017]    When writing is performed to the memory element with the use of a wireless signal, a semiconductor device of the present invention includes an antenna and a power supply generating circuit in addition to the above structure. 
         [0018]    In the above structure, a voltage is applied between the two terminals in the memory element to pass current through the mixed film, the mixed film is separated from the substrate, and the resistance value between the electrodes is significantly increased, whereby writing is performed to the memory element. Since the first conductive layer and the second conductive layer are formed over the same insulating film, a voltage is applied in a direction parallel to a plane of the insulating film. 
         [0019]    By addition of the halogen atom, adhesion of each of the substrate and the mixed film is reduced, whereby they are separated at a low applied voltage. 
         [0020]    A distance between electrodes of the first conductive layer and the second conductive layer provided on the same plane of the insulating film can be several nm to several hundreds nm depending on processing precision of formation of the electrodes. For example, when the distance between the electrodes is 35 nm or more, the first conductive layer and the second conductive layer may be formed in such a manner that a resist is exposed by EB exposure to form a mask and a conductive film is selectively etched. 
         [0021]    Side surfaces of the first conductive layer and the second conductive layer may be each formed to have a tapered shape. Another aspect disclosed in this specification is a memory device that includes a first conductive layer and a second conductive layer on the same insulating plane and a mixed film between the first conductive layer and the second conductive layer The side surfaces of the first conductive layer and the second conductive layer each have an angle of less than 90° with respect to the insulating plane. When the side surfaces each have a tapered shape, a region between two side surfaces which face each other is enlarged, and many mixed films can be disposed in the region. 
         [0022]    An aspect of the present invention for achieving the above structure is a method for manufacturing a memory device. In the memory device a first conductive layer and a second conductive layer that are disposed with an electrode distance “d” therebetween are formed over an insulating surface, and a mixed film is formed between a side surface of the first conductive layer and a side surface of a second conductive layer which faces the side surface of the first conductive layer. 
         [0023]    When the first conductive layer and the second conductive layer are formed with high alignment accuracy and a small electrode distance “d”, the first conductive layer and the second conductive layer are preferably formed in such a manner that a conductive film is formed over an insulating surface, a mask is formed over the conductive film, and the conductive film is selectively etched using the mask. 
         [0024]    When the electrode distance “d” is several nm, it is preferable that resist masks be formed by a nanoimprint method to form the first conductive layer and the second conductive layer. Further, the pair of electrodes may be formed in such a manner that one wiring is partially removed using laser light irradiation and then cut or separated. 
         [0025]    Furthermore, the first conductive layer and the second conductive layer may be formed by any of an inkjet method, a dispensing method, or the like, which are wet processes. 
         [0026]    Furthermore, in the formation method of the mixed film, after the inorganic compound and the organic compound are formed by a co-evaporation method, the halogen atom is added to the mixed film preferably by an ion implantation method. 
         [0027]    Furthermore, the mixed film may be formed by any of an inkjet method, a dispensing method, or the like, which are wet processes. 
         [0028]    In accordance with the present invention, a manufacturing process of a memory element can be simplified. Thus, a memory device with reduced manufacturing cost can be provided. 
         [0029]    Further, the present invention provides a nonvolatile memory device and a semiconductor device that includes the nonvolatile memory device, in which data can be additionally written except at the time of manufacture and in which forgery or the like caused by rewriting can be prevented. Furthermore, the present invention provides an inexpensive memory device and a semiconductor device that includes the memory device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    In the accompanying drawings: 
           [0031]      FIG. 1A  is a top view of a memory device of the present invention, and  FIG. 1B  is a cross-sectional view thereof; 
           [0032]      FIG. 2A  is a cross-sectional view of a memory device of the present invention, and  FIG. 2B  is a top view thereof; 
           [0033]      FIG. 3A  is a cross-sectional view of a memory device of the present invention, and  FIG. 3B  is a top view thereof; 
           [0034]      FIG. 4A  is a diagram of a memory cell of the present invention, and  FIG. 4B  is a diagram of a writing circuit included therein; 
           [0035]      FIG. 5  is a diagram of a reading circuit included in a memory device of the present invention; 
           [0036]      FIGS. 6A and 6B  are diagrams of equivalent circuits of a semiconductor device of the present invention; 
           [0037]      FIG. 7  is a diagram illustrating an exemplary structure of a semiconductor device of the present invention; 
           [0038]      FIG. 8  is a diagram illustrating a usage of a semiconductor device of the present invention; and 
           [0039]      FIGS. 9A to 9F  are diagrams of electronic devices each of which includes a semiconductor device of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0040]    Embodiment modes of the present invention are described below. 
       Embodiment Mode 1 
       [0041]    In this embodiment mode, an example of a semiconductor device is described.  FIG. 1A  is a top view, and  FIG. 1B  is a cross-sectional view taken along a line A-A′ of  FIG. 1A . 
         [0042]    In  FIG. 1A , three memory elements are shown. Although an example of three memory elements is given here to make description simple, there is no limitation on the number of memory elements, and designers of semiconductor devices may set the number of memory elements, which corresponds to the desired bit number. For example, memory elements may be formed so as to correspond to 8 bits, 16 bits, 32 bits, 64 bits, and the like. As shown in  FIG. 1B , over a substrate  101  having an insulating surface, the memory element includes a first conductive layer  102 , a second conductive layer  103 , and a mixed film  104  disposed therebetween. 
         [0043]    The mixed film  104  has a larger width than an electrode distance “d” and partially overlaps the first conductive layer  102  and the second conductive layer  103 . Further, the shape of a top surface of the mixed film  104  is not limited to that shown in  FIG. 1A . The mixed film is disposed at least between side surfaces of the first conductive layer  102  and the second conductive layer  103  which face each other. 
         [0044]    The mixed film  104  has a pattern shape extending over the three memory elements. Each distance between the adjacent memory elements is preferably wider than the electrode distance “d”. Although the mixed film  104  is extending over the three memory elements, three mixed films  104  may be separately provided for each memory element. 
         [0045]    The mixed film includes an inorganic compound, an organic compound, and a halogen atom. For the inorganic compound used in the mixed film, inorganic oxide can be used. Specifically, transition metal oxide can be used. Alternatively, oxide of metals that belong to Group 4 to Group 8 of the periodic table can be used. Specifically, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, or rhenium oxide is preferably used because of their high electron accepting properties. Alternatively, indium oxide, zinc oxide, or tin oxide can be used. In the case where the mixed film is formed by an evaporation method, use of molybdenum oxide is particularly preferable because of its stability in the atmosphere, a low hygroscopic property, and ease of handling. In particular, it is preferable that molybdenum trioxide be used. 
         [0046]    As the organic compound used in the mixed film, any of a variety of compounds such as aromatic amine compounds, carbazole derivatives, aromatic hydrocarbons, or high molecular compounds (such as oligomers, dendrimers, or polymers) can be used. It is to be noted that, as the organic compound used in the mixed film, a substance having a hole mobility (a hole-transporting material) of greater than or equal to 10 −6  cm 2 /Vs is preferably used. However, any substance other than the above substances may also be used as long as it is a substance in which the hole-transporting property is higher than the electron-transporting property. The organic compounds that can be used for the mixed film are specifically given below. 
         [0047]    Examples of the aromatic amine compounds that can be used in the mixed film include N,N′-bis(4-methylphenyl)(p-tolyl)-N,N′-diphenyl-p-phenylenediamine (DTDPPA), 4,4′-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl (DPAB), 4,4′-bis(N-{4-[N′-(3-methylphenyl)-N′-phenylamino]phenyl}-N-phenylamino)biphenyl (DNTPD), 1,3,5-tris[N-(4-diphenylaminophenyl)-N-phenylamino]benzene (DPA3B), and the like. 
         [0048]    Examples of the carbazole derivatives that can be used in the mixed film include 3-[N-(9-phenylcarbazol-3-yl)-N-phenylamino]- 9 -phenylcarbazole (PCzPCA1), 3,6-bis[N-(9-phenylcarbazol-3-yl)-N-phenylamino]- 9 -phenylcarbazole (PCzPCA2), 3-[N-(1-naphtyl)-N-(9-phenylcarbazol-3-yl)amino]- 9 -phenylcarbazole (PCzPCN1), and the like. 
         [0049]    Moreover, examples of the carbazole derivatives that can be used in the mixed film also include 4,4′-di(N-carbazolyl)biphenyl (CBP), 1,3,5-tris[4-(N-carbazolyl)phenyl]benzene (TCPB), 9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (CzPA), 1,4-bis[4-(N-carbazolyl)phenyl]-2,3,5,6-tetraphenylbenzene, and the like. 
         [0050]    Examples of the aromatic hydrocarbons that can be used in the mixed film include 2-tert-butyl-9,10-di(2-naphthyl)anthracene (t-BuDNA), 2-tert-butyl-9,10-di(1-naphthyl)anthracene, 9,10-bis(3,5-diphenylphenyl)anthracene (DPPA), 2-tert-butyl-9,10-bis(4-phenylphenyl)anthracene (t-BuDBA), 9,10-di(2-naphthyl)anthracene (DNA), 9,10-diphenylanthracene (DPAnth), 2-tert-butylanthracene (t-BuAnth), 9,10-bis(4-methyl-1-naphthyl)anthracene (DMNA), 9,10-bis[2-(1-naphthyl)phenyl]-2-tert-butylanthracene, 9,10-bis[2-(1-naphthyl)phenyl]anthracene, 2,3,6,7-tetramethyl-9,10-di(1-naphthyl)anthracene, 2,3,6,7-tetramethyl-9,10-di(2-naphthyl)anthracene, 9,9′-bianthryl, 10,10′-diphenyl-9,9′-bianthryl, 10,10′-bis(2-phenylphenyl)-9,9′-bianthryl, 10,10′-bis[(2,3,4,5,6-pentaphenyl)phenyl]-9,9′-bianthryl, anthracene, tetracene, rubrene, perylene, 2,5,8,11-tetra(tert-butyl)perylene, and the like. Besides these compounds, pentacene, coronene, or the like can also be used. In particular, use of an aromatic hydrocarbon which has a mobility of greater than or equal to 1×10 −6  cm 2 /Vs and has 14 to 42 carbon atoms is more preferable. 
         [0051]    It is to be noted that the aromatic hydrocarbons which can be used in the mixed film may have a vinyl skeleton. Examples of the aromatic hydrocarbons having a vinyl skeleton include 4,4′-bis(2,2-diphenylvinyl)biphenyl (DPVBi), 9,10-bis[4-(2,2-diphenylvinyl)phenyl]anthracene (DPVPA), and the like. 
         [0052]    Fluorine or chlorine is suitable for use as the halogen atom. However, there is no limitation to the substances described here, and any other substance may be used. 
         [0053]    Each of the first conductive layer  102  and the second conductive layer  103  may be formed using an element selected from Ta, W, Ti, Mo, Al, Cu, Ag, Au, In, and Zn; a single layer of an alloy material or a compound material containing an element given above as its main component; or a stacked layer thereof A semiconductor film typified by a polycrystalline silicon film that is doped with an impurity element such as phosphorus may be used. 
         [0054]    Material and formation steps of the first conductive layer  102  and the second conductive layer  103  may be different from each other In order to reduce the number of manufacturing steps, the first conductive layer  102  and the second conductive layer  103  are preferably formed using the same material. In addition, when the first conductive layer  102  and the second conductive layer  103  are formed using the same material, the alignment can be performed with high precision. 
         [0055]    Further, each of the first conductive layer  102  and the second conductive layer  103  generates heat by application of a voltage. At that time, if the surfaces of the first conductive layer  102  and the second conductive layer  103  are exposed, they can be oxidized and wiring resistance can be increased. Accordingly, a protective film is preferably provided to cover the first conductive layer  102  and the second conductive layer  103 . However, the protective film is not necessarily provided when a material having a certain degree of conductivity, such as Ti or Zn is used as the material of each of the first conductive layer  102  and the second conductive layer  103 . 
         [0056]    Although the shape of a top surface of each of the first conductive layer  102  and the second conductive layer  103  is, but is not particularly limited to, a rectangular in  FIG. 1A , the top surface may be a folded shape or a shape with a sharp projection. Further, in one memory element, a distance between the first conductive layer  102  and the second conductive layer  103  is not necessary to be uniform. Either or both the conductive layers may have a top surface that makes the distance between the first conductive layer  102  and the second conductive layer  103  partially short. In this case, the electrode distance “d” indicates the shortest distance. Since electric field is concentrated in the portion where the distance is partially short, writing data to the memory element can be performed with a lower writing voltage value. 
         [0057]    In the memory element shown in  FIGS. 1A and 1B , a voltage is applied between the pair of electrodes that are provided with the electrode distance “d” therebetween, and thus the mixed film is separated from the substrate to significantly increase the resistance value between the electrodes, whereby writing can be performed. If a voltage is not applied to the memory element, the conductivity can be kept high because of the existence of the mixed film between the pair of electrodes. In such a manner, two values can be stored to the memory element by a drastic change in the electric resistance value of the memory element depending on whether a voltage is applied or not. 
         [0058]    Further, the memory element to which data is once written by application of a voltage between the pair of electrodes does not have an electric resistance value which is a value before application of a voltage. The memory element is nonvolatile. 
       Embodiment Mode 2  
       [0059]    In this embodiment mode, a memory device including a passive-matrix memory element is described. The passive-matrix memory element is provided in the vicinity of an intersection of a bit line and a word line.  FIG. 2B  is a top view, and  FIG. 2A  is a cross-sectional view taken along a line B-B′ of  FIG. 2B . 
         [0060]    In  FIG. 2A , a word line  202  is provided over a substrate that has an insulating surface, and first insulating layers  203   a  and  203   b  are provided above the word line  202 . The first insulating layers  203   a  and  203   b  each have a thickness of 0.8 to 1.5 μm, which is perpendicular to the substrate surface. As the substrate that has an insulating surface, a glass substrate, a quartz substrate, or a plastic substrate is used. As another substrate that can be used, a semiconductor substrate, an SOI substrate, a ceramic substrate, a metal substrate that has an insulating film on its surface, or the like can be used. 
         [0061]    The first insulating layers  203   a  and  203   b  are formed using the same material, in which an opening (a contact hole) reaching the word line  202  is provided. A word line electrode  204  is provided to cover the opening. The word line electrode  204  which is electrically connected to the word line  202  through the opening is provided over the first insulating layers  203   a  and  203   b.  In  FIG. 2A , the word line electrode  204  and a bit line  201  are provided over the same plane, that is, over the first insulating layer  203   a.    
         [0062]    The word line  202  is a control signal line for selecting one row from a memory cell array. The memory cell array includes a plurality of memory cells that are arranged in matrix. Each memory element is arranged in the vicinity of the intersection of the word line  202  and the bit line  201 , and writing and reading data can be performed by application of a voltage of the word line corresponding to an address to which reading and writing is performed. 
         [0063]    The bit line  201  is a signal line for taking out data from the memory cell array. The memory cell that is connected to the word line  202  to which a voltage is applied performs reading data by outputting the data stored to the memory element to the bit line  201 . 
         [0064]    Further, mixed films  205  are provided between the word line electrode  204  and the bit line  201 . The mixed films  205  are separately formed for each memory element arranged in the vicinity of the intersection of the word line  202  and the bit line  201 . 
         [0065]    A side surface of the word line electrode  204  and a side surface of the bit line  201  each have a tapered shape. An electrode distance “d” is a distance between lower ends of the side surfaces that face each other. 
         [0066]    As shown in  FIG. 2A , the mixed film  205  is in contact with one side surface (the side surface having a tapered shape) of the word line electrode  204 . In addition, the mixed film  205  is also in contact with the side surface of the bit line  201 , which faces the side surface of the word line electrode  204  which is in contact with the mixed film  205 . 
         [0067]    In order to reduce the number of steps, the word line electrode  204  and the bit line  201  are preferably formed in the same step. In order to precisely control the distance “d” between the word line electrode  204  and the bit line  201 , the same photomask is preferably used to pattern the word line electrode  204  and the bit line  201  Reduction in the distance “d” between the word line electrode  204  and the bit line  201  makes it possible to write data at a low voltage. That is, it possible to write data with low power consumption. 
         [0068]    The word line  202 , the bit line  201 , and the word line electrode  204  are each formed by an evaporation method, a sputtering method, a CVD method, a printing method, an electrolytic plating method, a nonelectrolytic plating method, a droplet discharge method, or the like. 
         [0069]    Since the mixed film  205  includes an organic compound, in the process, it is useful that the bit line  201  and the word line electrode  204  are formed in advance of the formation of the mixed film  205 . Since the bit line  201  and the word line electrode  204  are formed before the mixed film  205  is formed, there are advantages that a method for forming a wiring that is to be used, particularly the deposition temperature, is not limited, and any of a variety of methods can be used. 
         [0070]    Further, materials of the word line  202 , the bit line  201 , and the word line electrode  204  may be different from each other. A method for forming each of the wiring of the word line  202 , the bit line  201 , and the word line electrode  204  may also be different from each other. 
         [0071]    The bit line  201  and the word line electrode  204  each of which has a side surface with a tapered shape can be formed by adjusting etching conditions in patterning as appropriate. The tapered shape of each of the bit line  201  and the word line electrode  204  is the same when the bit line  201  and the word line electrode  204  are formed in the same step. The tapered shape means that a cross section of the side surface of the electrode inclines. Each side surface of the bit line  201  and the word line electrode  204  preferably has an angle of inclination of greater than or equal to 10° and less than 85°, more preferably, greater than or equal to 60° and less than or equal to 80° to the substrate surface. 
         [0072]    Although  FIG. 2A  shows an example in which the bit line  201  is provided above the word line  202 , there is no particular limitation on the formation order, and the word line may be disposed above the bit line. When the word line is disposed above the bit line, a bit line electrode that is electrically connected to the bit line through the opening in the first insulating layers is formed, and the mixed film is disposed between the bit line electrode and the word line. 
         [0073]    As described above, the passive-matrix memory element is formed by the arrangement of the memory element in the vicinity of the intersection of the bit line and the word line; accordingly, an area that is occupied by the memory element can be reduced. 
         [0074]    This embodiment mode can be freely combined with Embodiment Mode 1. 
       Embodiment Mode 3 
       [0075]    In this embodiment mode, an example of an active-matrix memory device is described.  FIG. 3B  is a top view.  FIG. 3A  is a cross-sectional view taken along a line C-C′ of  FIG. 3B . 
         [0076]    In  FIG. 3A , a first insulating layer  302  is provided over a substrate  301  that has an insulating surface, and a semiconductor layer  303  is provided over the first insulating layer  302 . A second insulating layer  304  is provided over the first insulating layer  302  and the semiconductor layer  303 , and a word line (a gate line)  305  is provided over the second insulating layer  304 . A third insulating layer  306  is provided over the word line (the gate line)  305 , and a fourth insulating layer  307  is provided over the third insulating layer  306 . A bit line  309 , a first electrode  308 , and a common electrode  312  are provided over the fourth insulating layer  307 . Each of the bit line  309 , the first electrode  308 , and the common electrode  312  is formed using the same material. Six openings (contact holes) in total, which are pairs of right and left and reach the semiconductor layer  303 , are provided in the second insulating layer  304 , the third insulating layer  306 , and the fourth insulating layer  307 . The bit line  309  and the first electrode  308  are provided so as to cover the openings. The bit line  309 , the first electrode  308 , and the common electrode  312  are provided over the same layer, that is, over the fourth insulating layer  307 . 
         [0077]    The semiconductor layer  303 , the word line (gate line)  305 , the first electrode  308 , and the bit line  309  are included in a transistor. 
         [0078]    In  FIG. 3A , a mixed film  313  is in contact with side surfaces of the first electrode  308  and the common electrode  312  and a part of top surfaces (an upper end portion) thereof. The width of the mixed film  313  is larger than at least an electrode distance D x . 
         [0079]    Further, in the memory element shown in  FIG. 3A , a protective layer  314  may be provided so as to cover the bit line  309 , the first electrode  308 , the common electrode  312 , and the mixed film  313 . 
         [0080]    In this embodiment mode, the active matrix memory device is formed, and thus the memory elements can be integrated. Further, low power consumption can be achieved by reduction in the electrode distance D x . 
         [0081]    This embodiment mode can be freely combined with Embodiment Mode 1 or Embodiment Mode 2. 
       Embodiment 1 
       [0082]    In this embodiment, a structure of the passive matrix memory device described in Embodiment Mode 2 and a method for writing data therein are described. 
         [0083]    In  FIG. 4A , a word line is Wn (1≦n≦y), and a bit line is Bm (1≦m≦x). 
         [0084]      FIG. 4A  shows a structure of a memory device of the present invention. A memory device  5008  of the present invention has a column decoder  5001 , a row decoder  5002 , a reading circuit  5004 , a writing circuit  5005 , a selector  5003 , and a memory cell array  22 . The memory cell array  22  includes a plurality of memory cells  21 . 
         [0085]    Each memory cell  21  has a memory element  80 . 
         [0086]    In the present invention, as described in Embodiment Mode 2, a bit line (a first conductive layer) and a word line electrode (a second conductive layer) that is connected to a word line are formed over the same plane. The memory element  80  has a word line electrode, a bit line, and a mixed film between the word line electrode and the bit line. 
         [0087]    It is to be noted that a structure of the memory device  5008  described in this embodiment is just an example. An appropriate circuit structure may be used depending on the type of a reading method or a writing method. 
         [0088]    The column decoder  5001  receives an address signal specifying a column of the memory cell array and gives a signal to the selector  5003 . The selector  5003  receives the signal from the column decoder  5001 , selects a bit line of the specified column, and connects the selected bit line to writing circuit  5005  or a reading circuit  5004 . The row decoder  5002  receives an address signal specifying a row of the memory cell array and supplies a predetermined electric potential to a word line of the specified row. Through the above operation, one memory cell  21  in response to the address signal is selected. The reading circuit  5004  reads data of the selected memory cell and amplifies the data to output the amplified data. The writing circuit  5005  generates a voltage that is necessary for writing and applies the voltage to a memory element of the selected memory cell to perform data writing. 
         [0089]      FIG. 4B  shows a structure of the writing circuit  5005  included in the memory device of the present invention. The writing circuit  5005  includes a voltage generating circuit  7001 , a timing control circuit  7002 , switches SW 0  and SW 1 , and an output terminal Pw. In addition, a writing control signal (denoted by WE), a data signal (denoted by DATA), a clock signal (denoted by CLK), and the like are inputted into the writing circuit  5005 . The voltage generating circuit  7001  is formed of a boosting circuit or the like and generates a voltage V 1  that is necessary for writing data, which is outputted from an output terminal Pa. The timing control circuit  7002  generates signals S 0  and S 1  for controlling the switches SW 0  and SW 1 , respectively and outputs the signals S 0  and S 1  from output terminals P 0  and P 1 , respectively. The switch SW 0  controls a connection with the ground voltage, and the SW 1  controls a connection with the output terminal Pa of the voltage generating circuit  7001 . An output voltage Vw from the output terminal Pw of the writing circuit can be switched by these switches. 
         [0090]    Next, a write operation is described, where “0” refers to an initial state in which conductivity of the memory element is not changed, and “1” refers to a state in which the resistance between the electrodes, which changes the conductivity of the memory element, is high First, an input signal WE becomes a high level, the column decoder  5001 , which has received an address signal specifying a column, gives a signal to the selector  5003 , and the selector  5003  connects the bit line of the specified column to the output terminal Pw of the writing circuit. The bit line which is not specified is in a non-connection (referred to as floating) state. Similarly, the row decoder  5002 , which has received an address signal specifying a row, applies a voltage V 2  to the word line of the specified row and the word line that is not specified is placed in a floating state. Through the above operation, one memory element  80  in response to the address signal is selected. 
         [0091]    At the same time, when an input signal DATA receives a high level signal, the timing control circuit  7002  generates signals S 0  (=Low level) and S 1  (=High level), and outputs the signals from the output terminals P 0  and P 1 , respectively. By the above signals, the switch SW 0  is turned off, and the switch SW 1  is turned on, and the writing circuit  5005  outputs the voltage V 1  as the output voltage Vw from the output terminal Pw. 
         [0092]    In the selected memory element, through the above operation, the voltage V 1  is applied to the first conductive layer, and the voltage V 2  is applied to the second conductive film. Then, the mixed film is separated. As a result, conductivity of the memory element is changed and placed in a high resistance state, and “1” is written. The voltage V 1  and V 2  are selected from the range of values of the voltage, where the conductivity of the memory device can be changed by application of the voltage V 1 -V 2  to the memory device. 
         [0093]    When the input signal WE becomes a low level, all the bit lines and all the word lines are each placed in a floating state. By the above operation, writing is stopped. 
         [0094]    Next, writing of “0” is described. When writing of “0” is performed, conductivity of the memory element is not changed, and a voltage is not applied to the memory element. In other words, writing of “0” can be achieved with the initial state retained. First, in a similar manner to that of writing of “1”, when the input signal WE becomes a high level (a high voltage which enables writing), the column decoder  5001  which has received an address signal specifying a column gives a signal to the selector  5003  of the specified column, and the selector  5003  connects the bit line of the specified column to the output terminal Pw of the writing circuit. At this time, the bit line which is not specified is placed in a floating state. Similarly, the row decoder  5002  which has received an address signal specifying a row applies V 2  to the word line of the specified row and the word line which is not specified is placed in a floating state. Through the above operation, one memory element  80  in response to the address signal is selected. 
         [0095]    At the same time, an input signal DATA receives a low level signal, the timing control circuit  7002  generates a control signal S 0  at a high level and a control signal S 1  at a low level and outputs the control signals S 0  and S 1  from the output terminals P 0  and P 1 , respectively. By the control signals, the switch SW 0  comes to be on, and the switch SW 1  comes to be off; accordingly, 0V is outputted as the output voltage Vw from the output terminal Pw. 
         [0096]    In the selected memory element, through the above operation, 0V is applied to the bit line, and V 2  is applied to the word line. The voltage V 2  is selected from the range of values of the voltage, where the conductivity of the memory device is not changed by application of the voltage V 2  to the memory device. The conductivity of the memory element is not changed; thus, an initial state “0” is retained. 
         [0097]    When the input signal WE becomes a low level, all the bit lines and all the word lines are each placed in a floating state. 
         [0098]    In such a manner, writing of “1” or “0” can be performed. 
         [0099]    Next, reading of data is described. 
         [0100]    In  FIG. 5 , reference numeral  14  denotes a word line, and reference numeral  16  denotes a bit line. 
         [0101]    In a similar manner to that of the writing of data, one memory element  18   a  in response to the address signal is selected.  FIG. 5  shows one selected cell  18   a  and non-selected cells  18   b.  A voltage Vs is applied to the word line  14  connected to the selected cell  18   a,  and the other word lines  14 , which are not selected, are placed in a floating state. In addition, a reading circuit is connected to a bit line  16  connected to the selected cell  18   a,  and the other bit lines  16 , which are not selected, are placed in a floating state. The reading circuit determines whether a state of the memory is “1” or “0” in accordance with the current which flows through the selected cell  18   a.    
         [0102]    This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3. 
       Embodiment 2 
       [0103]    In this embodiment, a structure of the active matrix memory device described in Embodiment Mode 3 and a method for writing data therein are described using equivalent circuits shown in  FIGS. 6A and 6B . 
         [0104]    In an example of a structure of a memory device described in this embodiment, a column decoder  801 , a row decoder  802 , a reading circuit  804 , a writing circuit  805 , a selector  803 , and a memory cell array  822  are included. The memory cell array  822  includes bit lines Bm (1≦m≦x), word lines Wn (1≦n≦y), and x×y memory cells  821  at intersections of the bit lines and the word lines. 
         [0105]    The memory cell  821  has a first wiring that forms a bit line B x  (1≦x≦m), a second wiring that forms a word line W y  (1≧y≦n), a transistor  840 , and a memory element  841 . The memory element  841  has a structure in which a mixed film is interposed between a pair of conductive layers that are arranged in parallel, as described in Embodiment Mode 3. 
         [0106]    It is to be noted that a structure of the memory device  816  described in this embodiment is just an example. An appropriate circuit structure may be used depending on the type of a reading method or a writing method. 
         [0107]    The column decoder  801  receives an address signal specifying a column of the memory cell array and gives a signal to the selector  803 . The selector  803  receives the signal from the column decoder  801  and selects a bit line of the specified column. The row decoder  802  receives an address signal specifying a row of the memory cell array and selects a word line of the specified row. Through the above operation, one memory cell  821  in response to the address signal is selected. 
         [0108]    The memory cell  821  includes a transistor  840  and a memory element  841 . In  FIG. 6A , the memory cell  821  is denoted by a rectangle. A word line is connected to a gate electrode of the transistor  840 , a bit line is connected to one high concentration impurity region of the transistor, and a first electrode of the memory element  841  is connected to the other high concentration impurity region of the transistor. Second electrodes of all the memory elements in the memory cell array are electrically connected to each other, and a common voltage is applied to the second electrodes when the memory device operates, in other words, at the time of reading or writing. The reading circuit  804  reads data stored to a memory element and outputs the data by determining a state of the memory element of the selected memory cell. The writing circuit  805  generates a voltage that is necessary for writing data and applies the voltage to a memory element of the selected memory cell to perform data writing. 
         [0109]      FIG. 6B  shows a structure of the writing circuit  805  included in the memory device of the present invention. The writing circuit  805  includes a voltage generating circuit  811 , a timing control circuit  812 , switches SW 0  and SW 1 , and an output terminal Pw. In addition, a writing control signal (denoted by WE), a data signal (denoted by DATA), a clock signal (denoted by CLK), and the like are inputted into the writing circuit  805 . The voltage generating circuit  811  is formed of a boosting circuit or the like and generates the voltage V 1  that is necessary for writing data, which is outputted from an output terminal Pa. The timing control circuit  812  generates signals S 0  and S 1  controlling the switches SW 0  and SW 1 , respectively, and outputs the signals S 0  and S 1  from output terminals P 0  and P 1 , respectively. The switch SW 0  controls a connection with the ground, and the switch SW 1  controls a connection with the output Pa of the voltage generating circuit  811 . The output voltage Vw from the output terminal Pw of the writing circuit can be switched based on whether each of the switches SW 0  and SW 1  is on or off. 
         [0110]    Next, a write operation is described, where “0” refers to an initial state in which conductivity of the memory element is not changed, and “1” refers to a state in which resistance changing the conductivity of the memory element is high. First an input signal WE becomes a high level, the column decoder  801 , which has received an address signal specifying a column, gives a signal to the selector  803 , and the selector  803  electrically connects the bit line of the specified column to the output terminal Pw of the writing circuit. The bit line which is not specified is in a non-connection (referred to as floating) state. The output voltage Vw of the writing circuit is applied to the bit line of the specified column. Similarly, the row decoder  802 , which has received an address signal specifying a row, applies the voltage V 2  to the word line of the specified row and 0V to the word line that is not specified. Through the above operation, one memory element  841  in response to the address signal is selected. The voltage V 2  is selected from the range of value of the voltage, where the transistor  840  can be placed in an on state by application of the voltage V 2  to the gate electrode. 
         [0111]    At the same time, by receiving a data signal (DATA) at a high level, the voltage generating circuit  811  can generate the voltage V 1  and output the voltage V 1  from the output Pa. The timing control circuit  812  can generate signals S 0  at a low level and S 1  at a high level controlling the switches SW 0  and SW 1 , respectively, based on input signals WE, DATA, CLK, power supply potential (VDD), and the like, and output the signals S 0  and S 1  from the outputs P 0  and P 1 , respectively. By the above signals S 0  and S 1 , the switch SW 0  comes to be off, and the switch SW 1  comes to be on. The writing circuit  805  can output the voltage V 1  as the output voltage Vw from the output terminal Pw. 
         [0112]    In the selected memory element, through the above operation, the voltage V 2  is applied to the word line, the voltage V 1  is applied to the bit line, and 0V is applied to the second electrode. Therefore, the voltage V 1  is applied to the memory element. Then, an impurity region of the thin film transistor is made conductive, and the voltage V 1  of the bit line is applied to the memory element. As a result, conductivity of the memory element is changed and placed in a high resistance state, and “1” is written to the memory element. 
         [0113]    When the input signal WE becomes a low level, voltages of all the word lines become 0V and all the bit lines are placed in a floating state. At the same time, the timing control circuit  812  generates signals S 0  and S 1  each at a low level, which are outputted from the output terminals P 0  and P 1 , respectively. The output terminal Pw is placed in a floating state. By the above operation, writing of “1” is terminated. 
         [0114]    Next, writing of “0” is described. When writing of “0” is performed, conductivity of the memory element is not changed, and a voltage is not applied to the memory element. In other words, writing of “0” can be achieved with the initial state retained. First, similarly to writing of “1”, when the input signal WE becomes a high level, the column decoder  801  which has received an address signal specifying a column gives a signal to the selector  803  of the specified column, and the selector  803  connects the bit line of the specified column to the output terminal Pw of the writing circuit  805 . At this time, the bit line which is not specified is placed in a floating state. Similarly, the row decoder  802  which has received an address signal specifying a row applies the voltage V 2  to the word line of the specified row and 0V to the word line which is not specified. Through the above operation, one memory element  841  in response to the address signal is selected. 
         [0115]    At the same time, by receiving the input signal DATA at a low level, the timing control circuit  812  generates control signals S 0  at a high level and S 1  at a low level and outputs the control signals S 0  and S 1  from the outputs P 0  and P 1 , respectively. By the control signals S 0  and S 1 , the switch SW 0  comes to be on and the switch SW 1  comes to be off, and 0V is outputted as the output voltage Vw from the output terminal Pw. 
         [0116]    In the selected memory element, through the above operation, V 2  is applied to the word line, and the transistor is placed in an on state. However, 0V is applied to the first electrode connected to the bit line and the second electrode. As a result, a voltage is not applied to the memory element, and conductivity of the memory element is not changed; thus, an initial state “0” is retained. 
         [0117]    When the input signal WE becomes a low level, all the word lines becomes 0V, and all the bit lines are placed in a floating state. At the same time, the timing control circuit  812  generates signals S 0  and S 1  at a low level, which are outputted from the output terminals P 0  and P 1 , respectively, and the output terminal Pw is placed in a floating state. By the above operation, writing of “0” is terminated. 
         [0118]    As described above, writing of “1” or “0” can be performed. 
         [0119]    In addition, the memory cell array  822  includes a plurality of transistors  840  each of which functions as a switching element and a plurality of memory elements  841  each of which is connected to the transistor  840  over a substrate that has an insulating surface. 
         [0120]    This embodiment can be freely combined with Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4. 
       Embodiment 3 
       [0121]    A structure of a semiconductor device is described with reference to  FIG. 7 . As shown in  FIG. 7 , a semiconductor device  1520  of the present invention has a function of non-contact communication of data and includes a power supply circuit  1511 , a clock generating circuit  1512 , a data demodulation/modulation circuit  1513 , a control circuit  1514  controlling other circuits, an interface circuit  1515 , a memory circuit  1516 , a data bus  1517 , an antenna (an antenna coil)  1518 , a sensor  1523 a, and a sensor circuit  1523   b.    
         [0122]    The power supply circuit  1511  generates a variety of kinds of power supply voltage that is to be supplied to each circuit inside the semiconductor device  1520 , based on an AC signal inputted from the antenna  1518 . The clock generating circuit  1512  generates a variety of kinds of clock signals that are to be supplied to each circuit inside the semiconductor device  1520 , based on the AC signal inputted from the antenna  1518 . The data demodulation/modulation circuit  1513  has a function of demodulating/modulating data for communication with a reader/writer  1519 . The control circuit  1514  has a function of controlling the memory circuit  1516 . The antenna  1518  has a function of transmitting/receiving an electric wave. The reader/writer  1519  communicates with and controls the semiconductor device and controls the processing of data thereof. It is to be noted that the structure of the semiconductor device is not limited to the above structure, and for example, other elements such as a limiter circuit of power supply voltage and hardware dedicated to encryption processing may be added to the semiconductor device. 
         [0123]    The memory circuit  1516  has a memory element in which a mixed film is interposed between a pair of conductive layers, which is described as the memory element in Embodiment Modes 1 to 3. In this memory element, change in electric resistance is generated by electrical action from an external side. It is to be noted that the memory circuit  1516  may include only the memory element in which the mixed film is interposed between a pair of conductive layers or include a memory circuit that has any other structure. The memory circuit having any other structure corresponds to, for example, one or more selected from a DRAM, an SRAM, a FeRAM, a mask ROM, a PROM, an EPROM, an EEPROM, or a flash memory. 
         [0124]    The sensor  1523   a  is formed using a semiconductor element such as a resistor element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermal electromotive force element, a transistor, a thermistor, or a diode. The sensor circuit  1523   b  detects a change in impedance, reactance, inductance, voltage, or current and performs analog/digital conversion (A/D conversion) to output a signal to the control circuit  1514 . 
         [0125]    This embodiment can be freely combined with any one of Embodiment Modes 1 to 3, Embodiment 1 or Embodiment 2. 
       Embodiment 4  
       [0126]    In accordance with the present invention, a semiconductor device functioning as a wireless chip can be formed. Wireless chips have a variety of uses and can be mounted in objects such as bills, coins, securities, bearer bonds, and certificates (e.g., driver&#39;s licenses and resident cards, see  FIG. 9A ); recording media (e.g., DVD software and video tapes, see  FIG. 9B ); containers for wrapping objects (e.g., wrapping paper and bottles, see  FIG. 9C ); vehicles (e.g., bicycles, see  FIG. 9D ); personal belongings (e.g., bags and glasses), food, plants, animals, human bodies, clothes, livingware, and electronic devices; or tags for baggage or packages of products such as electronic devices (see  FIGS. 9E and 9F ). The electronic devices refer to liquid crystal display devices, EL display devices, television units (also simply referred to as TVs, TV receivers, or television receivers), cellular phones, or the like. 
         [0127]    A semiconductor device  9210  of the present invention is fixed to an object by being mounted on a printed board, being attached to a surface, or being incorporated into the object. For example, the semiconductor device is fixed to each object by being incorporated in paper of a book, being an organic resin of a package, or the like. In the semiconductor device  9210  of the present invention, reduction in size, thickness, and weight are achieved, and accordingly, the design of the object itself is not damaged even after the semiconductor device is fixed to the object. Furthermore, a certification function can be given when the semiconductor device  9210  of the present invention is provided in bills, coins, securities, bearer bonds, certificates, or the like. Forgery thereof can be prevented with the use of the certification function. Further, a system such as an inspection system can be made more efficient when the semiconductor device  9210  of the present invention is provided in containers for wrapping objects, recording media, personal belongings, food, clothes, livingware, electronic devices, or the like. 
         [0128]    Next, an example of an electronic device mounted with the semiconductor device of the present invention is described with reference to the drawing. The electronic device illustrated here is a cellular phone, which includes chassises  2700  and  2706 , a panel  2701 , a housing  2702 , a printed wiring board  2703 , operation buttons  2704 , and a battery  2705  (see  FIG. 8 ). The panel  2701  is incorporated in the housing  2702  so as to be detachable, and the housing  2702  is mounted on the printed wiring board  2703 . The shape or size of the housing  2702  is changed as appropriate depending on an electronic device in which the panel  2701  is incorporated. A plurality of semiconductor devices that is packaged are mounted on the printed wiring board  2703 , and the semiconductor device of the present invention can be used as one of such semiconductor devices. Each of the plurality of semiconductor devices mounted on the printed wiring board  2703  has a function of any one of a controller, a central processing unit (CPU), a memory, a power supply circuit, an audio processing circuit, a transmit/receive circuit, or the like. 
         [0129]    The panel  2701  is fixed to the printed wiring board  2703  with a connection film  2708 . The panel  2701 , the housing  2702 , and the printed wiring board  2703  are stored in the chassises  2700  and  2706 , with the operation buttons  2704  and the battery  2705 . A pixel region  2709  included in the panel  2701  is arranged so as to be seen through an aperture provided in the chassis  2700 . 
         [0130]    As described above, the semiconductor device of the present invention has effects of small size, thin shape, and lightweight. Because of these effects, a limited space inside the chassises  2700  and  2706  of the electronic device can be used efficiently. 
         [0131]    In addition, since the semiconductor device of the present invention includes a memory element that has a simple structure in which a mixed film that is changed by external electric action is interposed between a pair of conductive layers, an electronic device that uses an inexpensive semiconductor device can be provided. Further, since the semiconductor device of the present invention can be easily highly integrated, an electronic device that uses a semiconductor device that has a large-capacity memory circuit can be provided. As the memory element included in the semiconductor device of the present invention, the memory element described in any one of Embodiment Modes 1 to 3 can be used. 
         [0132]    Furthermore, data can be written by external electric action in the memory device included in the semiconductor device of the present invention, which is a nonvolatile memory device in which data can be written additionally. With this feature, forgery by rewriting can be prevented, and new data can be additionally written. Therefore, an electronic device that uses a semiconductor device in which a higher function and higher added-value are achieved can be provided. 
         [0133]    It is to be noted that each of the chassises  2700  and  2706  are an example of an appearance shape of a cellular phone. The electronic device of this embodiment can be modified in a variety of ways depending on the function or application thereof. 
         [0134]    This embodiment can be freely combined with any one of Embodiment Modes 1 to 3 and Embodiments 1 to 3. 
         [0135]    This application is based on Japanese Patent Application serial no. 2007-096977 filed with Japan Patent Office on Apr. 3, 2007, the entire contents of which are hereby incorporated by reference.