Abstract:
A method for making an integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The metal layer can provide one or more power planes within the substrate. A laser is used to ablate channels on the surfaces of the outer dielectric layer for the conductive patterns. The conductive patterns are electroplated or paste screen-printed and an etchant-resistive material is applied. Finally, a plating material can be added to exposed surfaces of the conductive patterns. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 10/138,225 entitled “INTEGRATED CIRCUIT SUBSTRATE HAVING LASER-EMBEDDED CONDUCTIVE PATTERNS AND METHOD THEREFOR”, filed on May 1, 2002 now U.S. Pat. No. 6,930,256, and is further related to U.S. patent application Ser. No. 09/931,144 filed Aug. 16, 2001 issued as U.S. Pat. No. 6,784,376, both by the same inventors and assigned to the same assignee. The specifications of the above-referenced patent applications are herein incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having laser-embedded conductive patterns for providing electrical inter-connection within an integrated circuit package. 
     BACKGROUND OF THE INVENTION 
     Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die. 
     The resolution of the printed circuit is often the limiting factor controlling interconnect density. Photo-etch and other processes for developing a printed circuit on a substrate have resolution limitations and associated cost limitations that set the level of interconnect density at a level that is less than desirable for interfacing to present integrated circuit dies that may have hundreds of external connections. 
     As the density of circuit traces interfacing an integrated circuit die are increased, the inter-conductor spacing must typically be decreased. However, reducing inter-conductor spacing has a disadvantage that migration and shorting may occur more frequently for lowered inter-conductor spacings, thus setting another practical limit on the interconnect density. 
     Therefore, it would be desirable to provide a method and substrate having improved interconnect density with a low associated manufacturing cost. It would further be desirable to provide a method and substrate having reduced susceptibility to shorting and migration between conductors. 
     SUMMARY OF THE INVENTION 
     A substrate having laser-embedded conductive patterns and a method for manufacturing generate a circuit pattern within a substrate having circuits embedded beneath the surface of the substrate. An outer dielectric layer is injection molded or laminated over a thin metal layer and channels outlining a desired circuit pattern are cut in the surface of the plastic layer using a laser. Conductive material is then plated or paste screened into the channels. The thin metal layer may be etched, mechanically drilled or punched to provide through holes for vias and to create separate power and ground paths within the metal layer. The process can be extended to multiple layers to create a sandwich structure for multilayer applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a pictorial diagram depicting a cross sectional side view of a metal layer for forming a substrate in accordance with an embodiment of the invention; 
         FIG. 1B  is a pictorial diagram depicting a top view of a metal layer for forming a substrate in accordance with an embodiment of the invention; 
         FIGS. 2A-2D  are pictorial diagrams depicting cross-sectional side views of various stages of preparation of a substrate in accordance with an embodiment of the invention; and 
         FIG. 3  is a pictorial diagram depicting an integrated circuit in accordance with an embodiment of the invention. 
     
    
    
     The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout. 
     DETAILED DESCRIPTION 
     The above-incorporated patent application discloses a process and structure for manufacturing a low-cost substrate having high conductor density and electrical integrity by embedding the conductive patterns beneath the surface of a substrate. The substrate is an embossed substrate requiring tooling to form channels for the conductive patterns. While embossing provides a low cost and high throughput manufacturing process for the substrate base, the tooling must be remanufactured when design changes are made, as it is unique to a particular design. For low volume applications such as prototyping, the cost to tool the embossing process may be prohibitive and in general, the techniques of the present invention will provide a lower cost alternative, except in designs or portions of designs that have large areas that are recessed such as wells for integrated circuit dies. 
     The present invention provides an alternative that does not require custom tooling for producing channels for conductors within a substrate and provides a manufacturing process, that in general, has fewer steps and lower overall cost in producing a substrate. For some embodiments of the present invention, a punching tool is required to make a metal frame, but for other embodiments of the present invention, the metal frame is etched or mechanically drilled and therefore no punching tool is required, reducing the cost of taking a particular design to the manufacturing process. As a result, the present invention provides a low cost alternative to the techniques of the above-incorporated patent application and an alternative with a greatly reduced startup or low-volume production cost. Also, the substrate material is not deformed to generate circuit channels in the techniques of the present invention, providing use of a wider range of materials for the dielectric layer and eliminates any reduction in the mechanical properties of the dielectric that are cause by deformation. A combination of the techniques described in the above-incorporated patent application and the techniques of the present invention may be used to emboss a large area, such as an integrated circuit die well, within the manufacturing process disclosed herein. 
     Referring now to the figures and in particular to  FIG. 1A , a side view of a metal layer  10  for use in preparing a substrate in accordance with an embodiment of the present invention is depicted. Metal layer  10  is used to form a substrate in a novel process that permits embedding circuits beneath the top and/or bottom surface of a substrate and isolating the circuits in channels. Metal layer  10  is generally a copper core that may be etched or die-cut, but other suitable metal layers may be used for form the core of the substrate of the present invention, such as a copper-INVAR-copper laminate. The ratio of copper to Invar can be varied to provide adjustment of the coefficient of thermal expansion (CTE) of the substrate. Holes  11  are generated in metal layer  10  to permit the passage of circuit paths through metal layer  10 , while avoiding electrical contact with metal layer  10 . Referring now to  FIG. 1B , a top view of metal layer  10  is shown. A die aperture  12 , for mounting an integrated circuit die is provided in the central area of metal layer  10 . Isolating cuts  13  separate metal layer  10  into multiple conductive planes, such as power plane  15  and ground plane  14 . A frame (not shown) can be provided around the periphery of metal layer  10  to hold the isolated planes in place until after the manufacture of the substrate. 
     Referring now to  FIG. 2A , the first stage in the preparation of a substrate  20  in accordance with an embodiment of the present invention is depicted. A dielectric outer layer  21  has been added to the top and bottom surface of metal layer  10  and can be provided by injection molding a plastic material around metal layer  10  or by laminating a dielectric such as KAPTON film or PTFE on each side of metal layer  10 . 
     Referring now to  FIG. 2B , the next stage in the preparation of substrate  20  is depicted. Substrate  20  is laser-ablated to form substrate  20 A having an outer dielectric layer  21 A as shown. Substrate  20 A includes channels on both surfaces of the dielectric layer defining channels  23  for conductive paths, blind vias  22  for connection to ground and power planes formed in metal layer  10  and through vias  11 A having a diameter smaller than holes  11  in metal layer  10 , providing an insulating layer around holes  11 . Blind vias  22  show a conical shape, which is preferred for addition of conductive material and can be generated by varying the laser angle or beam diameter as the dielectric material  21  is ablated. 
     Next, referring to  FIG. 2C , the next step in the preparation of substrate  20 A providing a substrate  20 B having conductive circuit paths. Conductive material is added within channels  23 , blind vias  22  and through vias  11 A to provide conductive paths  23 A, conductive blind vias  22 A and conductive through vias  11 B. The conductive material may be a silver or copper paste that is screen printed into channels  23 , blind vias  22  and through vias  11 A, and planarized to remove conductive material on the surface of outer dielectric layer  21 A after printing. Alternatively, an electroplating process (generally copper electroplate) can be used to add conductive material within channels  23 , blind vias  22  and through vias  11 A and a planarization process or chemical etching process can be used to remove excess conductive material on the surface of dielectric layer  21 A. 
     Multiple conductive layers may be generated by repeating the steps above, adding a second outer dielectric layer to the top and/or bottom surface of substrate  20 B to form a multi-layer circuit on one or both sides of substrate  20 B. Further, embossing steps in accordance with the above-incorporated patent application may be used to generate large area recesses in one or both sides of outer dielectric layer  21 A, such as die mounting recesses. 
     Finally, top plating  24  is electroplated on the conductive surfaces deposited within the channels of substrate  20 B to form plated substrate  20 C. Nickel-Gold is generally used to provide a barrier migration layer and to provide electrical contact for wire or chip bonding in subsequent manufacturing steps. In general, silver-nickel is an appropriate electroplating material and if a silver paste was used to form conductive channels  23 A, electroplating may not be needed to provide solderable conductive connections, but may be added to eliminate oxidation. 
     While the figures illustrate conductive circuit channels, the figures are depicting only a portion of the total substrate. Hundreds of circuit channels  23  will generally be used in an integrated circuit design and may be oriented in any direction within the surface of substrate  20 C. The present invention provides a process for forming circuits within channels in a substrate that are below the top surface of the substrate. This an improvement over the present state of the art similar to that provided by above-incorporated patent application in that the prior art generally provides only surface conductors. The channels formed by laser ablation place the conductors below the surface and the conductors are thereby insulated from adjacent conductors by the substrate. The use of laser ablation techniques further provides improvement over the techniques of the above-incorporated patent application. 
     Referring now to  FIG. 3 , an integrated circuit  30  in accordance with an embodiment of the invention is depicted. A die  31  having electrical contacts is attached to substrate  20 C and is electrically connected to conductive channels  23 A by wires  35 . Ball grid array (BGA) connections for the integrated circuit package are provided by solder balls  36  attached to the bottom channels  23 A formed in substrate  20 C. 
     The above description of embodiments of the invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure and fall within the scope of the present invention.