Abstract:
The present invention discloses a liquid crystal display (LCD) Panel, a LCD device, and a gate driving method of LCD panel. The LCD device comprises a LCD panel; the LCD panel comprises multiple gate lines, and a gate drive circuit connected with the gate lines; the gate drive circuit comprises multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; each shift register unit comprises a GOUT(n−1) interface and a GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n−1) output by the GOUT(n−1) interface at one scanning interval. In the present invention, because each shift register unit can scan two gate lines, the RC distortion of the input clock signals is reduced; the signal delay effect is greatly reduced; and the reliability and stability of circuits are increased. Meanwhile, on the premise of guaranteeing circuit drive, the GOA circuit is further simplified, and the space occupied by the circuit is further reduced.

Description:
TECHNICAL FIELD  
       [0001]    The present invention relates to the field of liquid crystal displays (LCDs), and more particularly to a LCD panel, a LCD device, and a gate driving method of LCD panel. 
       BACKGROUND  
       [0002]    It is well-known that the technique of gate on array (GOA)/gate in TFT-LCD panel (GIP) can reduce integrated circuit (IC) cost, reduce the board area around a panel, and reduce the Tact time of MOD Bonding. However, the stability, the reliability, the power consumption, etc. of the complicated GOA circuits of the panel become problems which are difficult to solve for designers. One gate line signal is output by a general GOA circuit through at least one shift register unit. Thus, for n gate lines, more than n+1 shift register units are required to form a completed circuit loop structure. Because external CLK and VGL lines enter the more than n+1 shift register units simultaneously in accordance with requirements, the power consumption and delay of signals become more serious. 
       SUMMARY  
       [0003]    The aim of the present invention is to provide a LCD panel, a LCD device, and a gate driving method of LCD panel capable of reducing the board area around a panel, reducing the Tact time of MOD Bonding, increasing the stability and reliability of the GOA circuits of the panel, and reducing the power consumption and delay of signals. 
         [0004]    The purpose of the present invention is achieved by the following technical schemes. 
         [0005]    A LCD panel comprises multiple gate lines, and a gate drive circuit connected with the gate lines; the gate drive circuit comprises multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; each shift register unit comprises a former signal GOUT(n−1) interface and a latter signal GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n−1) output by the GOUT(n−1) interface at one scanning interval. 
         [0006]    Preferably, the LCD panel also comprises a first switch circuit and a second switch circuit, and GOUT(n−1) interface shares a common interface with the GOUT(n) interface. A common signal output by the common interface is used as GOUT(n−1) or GOUT(n) to be output to the corresponding gate line, and is connected to the other adjacent gate line through the first switch circuit. This is a specific embodiment of the present invention. An output interface is shared by the GOUT(n−1) and the GOUT(n), and the output interval is controlled by the first switch circuit so that the circuit structure is simple. 
         [0007]    Preferably, the common signal output by the common interface is kept for two scanning intervals within one scanning period; and the first switch circuit is kept for one scanning interval. This is a specific control mode of the GOUT(n−1)/GOUT(n) output. Take the common signal as GOUT(n) for example, the GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval. In addition, in the application of a large panel, the problem of undercharge may occur. The GOUT(n) is kept for two scanning intervals within one scanning period, and the gate lines are pre-charged in the former scanning interval, to ensure a pixel to achieve the required potential within defined time. 
         [0008]    Preferably, the LCD panel also comprises a first switch circuit, and the GOUT(n) interface shares a common interface with the GOUT(n−1) interface. The common interface is used as a GOUT(n−1) or GOUT(n) interface to output a signal to the corresponding gate line, and is connected to the other adjacent gate line by the first switch circuit; and the other adjacent gate line is connected to the reference low-level signal of the shift register unit by the second switch circuit. This is the other embodiment of the present invention. The reliability becomes higher because the output interval of the common signal output to the other gate line is controlled by two switch circuits. 
         [0009]    Preferably, the common signal is kept for two scanning intervals within one scanning period. The first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time. This is the other specific control mode of the GOUT(n−1)/GOUT(n) output. Take the common signal as GOUT(n−1) for example, the GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The first switch circuit and the second switch circuit are respectively used for connecting and disconnecting the GOUT(n−1). The GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval. To ensure the reliability of actions, when the first switch circuit is disconnected, the second switch circuit is connected, and the GOUT(n−1) is forcibly kept at a low-level position. 
         [0010]    Preferably, the common signal is output by the common interface through a third switch circuit, and the control ends of the second switch circuit and the third switch circuit are connected to the same control signal. The third switch circuit can ensure that the scanning of the other gate line is in an off state when the current gate line is scanned. Thus, the scanning interval of every two gate lines is guaranteed as one scanning interval, benefitting to keep the scanning consistency of gate lines and improve display quality. 
         [0011]    Preferably, the LCD panel also comprises an intensifier circuit; the intensifier circuit is connected to the other end of the gate line, and is matched with the gate drive circuit to simultaneously drive and scan the same gate line. The intensifier circuit is added, and then the drive capability of each gate line is improved. 
         [0012]    Preferably, the structure of the intensifier circuit at the other end of the gate line is completely the same as that of the gate drive circuit at one end of the gate line. This is one specific embodiment of the intensifier circuit. 
         [0013]    Preferably, the intensifier circuit is a buffer circuit, and the buffer circuit comprises multiple buffer units. Each buffer unit comprises a fourth switch circuit and a fifth switch circuit which are in series connection. The input end of the fourth switch circuit is connected with a gate line corresponding to the common signal, and the output end of the fourth switch circuit is connected with a gate line corresponding to the output end of the first switch circuit, and is connected with a reference low-level signal of the intensifier circuit through the fifth switch circuit. A same control signal is used by the fourth switch circuit and the first switch circuit. A same control signal is used by the fifth switch circuit and the second switch circuit. This is the other specific embodiment of the intensifier circuit so that the circuit has simple structure and low cost. 
         [0014]    A LCD device, wherein the LCD device comprises the aforementioned LCD panel. 
         [0015]    A gate driving method of LCD panel, comprising the following steps: selecting multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; connecting each shift register unit with adjacent two gate lines; and outputting GOUT(n−1) and GOUT(n) between which one scanning interval exists by each shift register unit to its corresponding adjacent two gate lines. 
         [0016]    Preferably, the GOUT(n) is kept for two scanning intervals. The GOUT(n−1) is connected with the GOUT(n) by the first switch circuit, and is connected with the Voff of the shift register unit by the second switch circuit. The first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time. 
         [0017]    In the present invention, each shift register unit can scan two gate lines. N Gate line signals are output by only at least n/2+1 shift register units. The circuit is greatly simplified; the RC distortion of input clock signals is reduced; the signal delay effect is greatly reduced; and the reliability and stability of circuits are increased. Meanwhile, on the premise of guaranteeing circuit drive, the GOA circuit is further simplified, and the space occupied by the circuit is further reduced. 
     
    
     
       BRIEF DESCRIPTION OF FIGURES  
         [0018]      FIG. 1  is a schematic diagram of a LCD panel of the present invention; 
           [0019]      FIG. 2  is a schematic diagram of a principle conception of the present invention; 
           [0020]      FIG. 3  is a functional block diagram of embodiment 1 of the present invention; 
           [0021]      FIG. 4  is a functional block diagram of embodiment 2 of the present invention; 
           [0022]      FIG. 5  is a waveform diagram of the input and output signals of embodiment 2 of the present invention; 
           [0023]      FIG. 6  is a functional block diagram of embodiment 3 of the present invention; 
           [0024]      FIG. 7  is a waveform diagram of the input and output signals of embodiment 3 of the present invention; 
           [0025]      FIG. 8  is a schematic diagram of a LCD panel of embodiment 4 of the present invention; 
           [0026]      FIG. 9  is a principle diagram of embodiment 4 of the present invention; and 
           [0027]      FIG. 10  is a principle diagram of a buffer unit of embodiment 4 of the present invention. 
       
    
    
       [0028]    Wherein:  1 . LCD panel;  2 . gate drive circuit;  21 . shift register unit;  3 . liquid crystal drive IC (COF);  4 . first switch circuit;  5 . second switch circuit;  6 . third switch circuit;  7 . intensifier circuit;  8 . buffer unit;  81 . fourth switch circuit;  82 . fifth switch circuit. 
       DETAILED DESCRIPTION  
       [0029]    The present invention will further be described in detail in accordance with the figures and the preferred embodiments. 
         [0030]    A LCD device comprises a LCD panel. As shown in  FIG. 1  and  FIG. 2 , the LCD panel  1  comprises multiple gate lines and data lines (arranged on the LCD panel  1  and not shown in the figure), a gate drive circuit  2  connected with the gate lines, and liquid crystal drive ICs (COF)  3  connected with the data lines. The gate drive circuit  2  comprises multiple shift register units  21 . Each shift register unit  21  comprises a GOUT(n−1) interface and a GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n−1) output by the GOUT(n−1) interface at one scanning interval. The scanning interval refers to the average scanning time of all gate lines within one scanning period. The invention will further be described in detail in accordance the embodiments. 
       Embodiment 1  
       [0031]    as shown in  FIG. 3 , the GOUT(n−1) interface shares a common interface with the GOUT(n) interface. A common signal output by the common interface is used as GOUT(n−1) or GOUT(n) to be output to the corresponding gate line, and is connected to the other adjacent gate line through a first switch circuit  4 . 
         [0032]    The common signal output by the common interface is kept for two scanning intervals within one scanning period, and the first switch circuit is kept for one scanning interval. Take the common signal as GOUT(n) for example, the GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit  4  should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval. 
         [0033]    An output interface is shared by the GOUT(n) and the GOUT(n−1), and the output interval is controlled by the first switch circuit  4  so that the circuit structure is simple. 
       Embodiment 2  
       [0034]    as shown in  FIG. 4  and  FIG. 5 , a common interface is shared by the GOUT(n−1) interface and the GOUT(n) interface. The common interface is used as a GOUT(n−1) interface or a GOUT(n) interface to output a signal to the corresponding gate line, and is connected to the other adjacent gate line by the first switch circuit  4 ; and the other adjacent gate line is connected to the reference low-level signal Voff of the shift register unit  21  by the second switch circuit  5 . The common signal is kept for two scanning intervals within one scanning period. The first switch circuit  4  and the second switch circuit  5  are alternatively connected, and are connected for one scanning interval each time. Take the common signal as GOUT(n) for example: 
         [0035]    The GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The first switch circuit  4  and the second switch circuit  5  are respectively used for controlling the connection and the disconnection of the GOUT(n−1). The GOUT(n) output is kept for two scanning intervals. The GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit  4  should be connected when a high-level signal is output by the GOUT(n) interface, and is disconnected after being kept for one scanning interval. To ensure the reliability of actions, when the first switch circuit  4  is disconnected, the second switch circuit  5  is connected, and the GOUT(n−1) is forcibly kept at a low-level position. In the application of a large panel, the problem of undercharge may occur. Therefore, corresponding gate lines should be pre-charged to ensure a pixel to achieve the required potential within defined time. The GOUT(n) exceeds the GOUT(n−1) at one scanning interval, and the signal output is kept in one scanning interval when the GOUT(n−1) is output to pre-charge the corresponding gate line. Therefore, the GOUT(n) is kept for two scanning intervals within one scanning period. 
         [0036]    As shown in the functional block diagram of  FIG. 4 : the first switch circuit  4  is a switch tube T 15 , and the second switch circuit  5  is a switch tube T 16 . A chip select (CS) STV is externally provided by the circuit to control clock signals (CLK 1 ,CLK 2 ,CLK 3 ,CLK 4 ), and the reference low-level signal Voff of the shift register unit  21 . The GOUT(n), the STV(n) of the following shift register unit  21  and the GOUT(n−1) are output through the aforementioned function modules. The switch tube T 1  and the switch tube T 15  are pull-up units and output the GOUT(n) and GOUT(n−1), and the switch tube T 4  is a carry unit and outputs STV(n+2). Switch tubes T 2 , T 6 , T 7 , T 8 , T 9  and T 11  are holding units, and hold the Gate out output to the required potential; switch tubes T 3 , T 5 , T 12 , T 13  and T 16  are discharge units, and pull down high potential to low potential; and a switch tube T 14  is a discharge reset unit. 
         [0037]    The current shift register unit  21  accepts the CS STV(n) of the former shift register unit  21 . Only after the STV(n) is accepted, the output of the current shift register unit  21  is controlled. If the current shift register unit  21  is the first shift register unit  21 , its STV(n) comes from an external enable pulse STVP. After the current shift register unit  21  is started, the level switch of the scanning signal GOUT(n) is controlled by CLK 1  and CLK 2 , the GOUT(n−1) level switch is controlled by CLK 3  and CLK 4 , and a reference low level is provided by Voff. Reset provides a reset signal, the high level is effective, and the data of all the shift register units are cleared. After the current shift register unit  21  drives the current gate line, a CS STV(n+2) of the following shift register unit  21  is produced; the following shift register unit  21  responds to CLK 1  to CLK 4  after starting; the GOUT(n+1) is fed back to the former shift register unit  21  when the current gate line is driven; the former shift register unit  21  is cleared and reset; and the former shift register unit  21  does not respond to the clock signals before the next STV(n) is produced. 
         [0038]    This is the other embodiment of the present invention. The reliability becomes higher because the output interval of the common signal output to the other gate line is controlled by two switch circuits. 
       Embodiment 3  
       [0039]    as shown in  FIG. 6 , the common signal is output by the common interface through a third switch circuit  6 ; and the control ends of the second switch circuit  5  and the third switch circuit  6  are connected to the same control signal. The embodiment can be used in the technical schemes of the aforementioned embodiment 1 and embodiment 2. To simplify description, take the application of embodiment 2 as an example to further describe the technical scheme: take the common signal as GOUT(n) for example, the GOUT(n) is output by the common interface through the third switch circuit  6 . The GOUT(n) is kept for two scanning intervals, and the control end of the first switch circuit  4  is connected to the CLK 3 . The control ends of the second switch circuit  5  and the third switch circuit  6  are connected to the CLK 4 , and the first switch circuit  4  and the second switch circuit  5  are alternatively connected, and are connected for one scanning interval each time. The first switch circuit  4  is connected when a high-level signal is output by the GOUT(n) interface. 
         [0040]    As shown in  FIG. 7 , because the control ends of the second switch circuit  5  and the third switch circuit  6  are connected to the CLK 4 , when the GOUT(n−1) is output, the GOUT(n) output is in an off state. When the GOUT(n−1) is disconnected, the third switch circuit  6  is connected, and the GOUT(n) is output. Therefore, the output time of either the GOUT(n−1) or the GOUT(n) is one scanning interval. The equal scanning interval benefits to guarantee display consistency, and the preferable display quality of the LCD panel  1 . 
       Embodiment 4  
       [0041]    to preferably increase the speed of circuit charge and discharge, a design of drive of double sides is used; an intensifier circuit  7  on the left side may be designed with the same circuit structure as that of the gate drive circuit on the right side to improve the circuit drive capability; alternatively, the intensifier circuit  7  on the left side may be only designed into a buffer circuit for charge and discharge to improve the circuit drive capability. As shown in  FIG. 8 , the LCD panel  1  also comprises an intensifier circuit  7 . The intensifier circuit  7  is connected to the other end of the gate line, and is matched with the gate drive circuit  2  to simultaneously drive and scan the same gate line. The embodiment can be used in any one of the technical schemes of the aforementioned embodiment 1 to embodiment 3. To simplify description, take the application of embodiment 2 as an example to further describe the technical scheme: 
         [0042]    The embodiment uses the buffer circuit solution as an example to explain; as shown in  FIG. 9  and  FIG. 10 , the intensifier circuit  7  comprises multiple buffer units  8 . Each buffer unit  8  comprises a fourth switch circuit  81  and a fifth switch circuit  82  which are in series connection. The input end of the fourth switch circuit  81  is connected with a gate line corresponding to the common signal, and the output end of the fourth switch circuit  81  is connected with a gate line corresponding to the output end of the first switch circuit  4 , and is connected with a reference low-level signal VGL of the intensifier circuit  7  through the fifth switch circuit  82 . A same control signal is used by the fourth switch circuit  81  and the first switch circuit  4 , namely the CLK 3 ; and a same control signal is used by the fifth switch circuit  82  and the second switch circuit  5 , namely the CLK 4 . Thus, the intensifier circuit  7  can simultaneously drive the corresponding gate line from the other end when driving the gate line from one end, so that the scanning drive capability of the gate line is enhanced. 
         [0043]    Through the circuit, the left side and the right side of a circuit are simultaneously charged and discharged; the response speed of the circuit is rapidly increased; and the panel image quality uniformity is improved. The conception of the present invention is not limited to the aforementioned embodiments, all the intensifier circuits which are connected to the other end of each gate line, matched with the gate drive circuit, and used for synchronously driving and scanning the same gate line should be considered to belong to the protection scope of the present invention. 
         [0044]    A gate driving method of LCD panel which is used by the aforementioned LCD panel, comprising the following steps: selecting multiple shift register units which are used for shifting signals to sequentially drive all gate lines; connecting each shift register unit with adjacent two gate lines; and outputting GOUT(n−1) and GOUT(n)1 between which one scanning interval exists by each shift register unit to its corresponding adjacent two gate lines. 
         [0045]    Furthermore, the GOUT(n) is kept for two scanning intervals. The GOUT(n−1) is connected with the GOUT(n) by the first switch circuit, and is connected with the reference low-level signal Voff of the shift register unit by the second switch circuit. The first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time. 
         [0046]    The present invention is described in detail in accordance with the above contents with the specific preferred embodiments. However, this invention is not limited to the specific embodiments. For the ordinary technical personnel of the technical field of the present invention, on the premise of keeping the conception of the present invention, the technical personnel can also make simple deductions or replacements, and all of which should be considered to belong to the protection scope of the present invention.