Abstract:
A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.

Description:
RELATED APPLICATION 
       [0001]    This application is related to U.S. patent application Ser. No. 13/776,324 (Attorney docket no. YOR920120143US1), entitled “SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION”, filed Feb. 25, 2013, the disclosure of which is incorporated by reference herein. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to FinFET structures and, more particularly, relates to the formation of an implanted layer adjacent to the gate to seal the gate prior to a subsequent epitaxial silicon step in which raised source/drains are formed in the FinFET structure. 
         [0003]    FinFET devices and FinFET structures are nonplanar devices and structures typically built on a semiconductor on insulator (SOI) substrate. The FinFET devices may comprise a vertical semiconductor fin, rather than a planar semiconductor surface, having a single or double gate wrapped around the fin. In an effort to provide for continued scaling of semiconductor structures to continuously smaller dimensions while maintaining or enhancing semiconductor device performance, the design and fabrication of semiconductor fin devices and semiconductor fin structures has evolved within the semiconductor fabrication art. 
       BRIEF SUMMARY 
       [0004]    The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing a FinFET structure including silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain. 
     
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         [0005]    The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: 
           [0006]      FIGS. 1A to 1H  illustrate a process for forming fins on a semiconductor substrate wherein: 
           [0007]      FIG. 1A  illustrates a starting structure including a semiconductor on insulator (SOI) substrate, an oxide layer, an amorphous silicon layer and a hard mask layer; 
           [0008]      FIG. 1B  illustrates the patterning of the amorphous silicon layer and the hard mask layer; 
           [0009]      FIG. 1C  illustrates the removal of the hard mask layer, leaving only stripes of amorphous silicon; 
           [0010]      FIG. 1D  illustrates the deposition of a conformal layer of nitride; 
           [0011]      FIG. 1E  illustrates the etching of the nitride to form sidewall spacers; 
           [0012]      FIG. 1F  illustrates the etching of the stripes of amorphous silicon to leave only the sidewall spacers; 
           [0013]      FIG. 1G  illustrates the etching of the oxide layer and the silicon layer of the SOI substrate using the sidewall spacers as a mask to result in stripes of oxide on silicon fins; and 
           [0014]      FIG. 1H  illustrates the etching of the sidewall spacers and the oxide stripes to result in silicon fins. 
           [0015]      FIG. 2  is a cross-sectional view of a prior art structure of a FinFET structure comprising a fin and a raised source/drain formed by epitaxial deposition. 
           [0016]      FIG. 3  is a cross-sectional view of the prior art structure of  FIG. 2  wherein epitaxial nodule defects are formed on an upper part of the gate where the spacer and/or hard mask have been pulled back. 
           [0017]      FIGS. 4A to 7A  and  4 B to  7 B illustrate a first exemplary embodiment for forming a FinFET structure having a silicon nitride layer on the gate wherein: 
           [0018]      FIGS. 4A and 4B  illustrate angle implanting nitrogen into the gate; 
           [0019]      FIGS. 5A and 5B  illustrate a silicon nitride layer formed from the nitrogen-containing layer on the sides of the gate; 
           [0020]      FIGS. 6A and 6B  illustrate the formation of a spacer over the silicon nitride layer; and 
           [0021]      FIGS. 7A and 7B  illustrate the formation of a raised source/drain over the fins. 
           [0022]      FIGS. 8A to 11A  and  8 B to  11 B illustrate a second exemplary embodiment for forming a FinFET structure having a silicon nitride layer on the gate wherein: 
           [0023]      FIGS. 8A and 8B  illustrate angle implanting silicon nitride into the gate; 
           [0024]      FIGS. 9A and 9B  illustrate the silicon nitride layer in upper portions of the sides of the gate; 
           [0025]      FIGS. 10A and 10B  illustrate the formation of a spacer over the silicon nitride layer; and 
           [0026]      FIGS. 11A and 11B  illustrate the formation of a raised source/drain over the fins. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    Referring to the Figures in more detail, and particularly referring to  FIG. 2 , there is disclosed a prior art FinFET structure  200  comprising a semiconductor substrate  202 , fins  204 , gate structure  206  and raised source/drain  208  covering the fins  204 . The semiconductor substrate  202  may include a semiconductor base  210  and an oxide layer  212 . The gate structure  206  may include a gate  214 , a hard mask  216  on top of the gate  214 , and spacers  218  on the sides of the gate  214 . The spacers  218  preferably should overlap the hard mask  216  so that there is no gate  214  exposed. 
         [0028]    A difficulty with the structure shown in  FIG. 2  is that there may be some pullback of the spacer  218  and/or hard mask  216  so that part of the gate  214  is exposed. When this occurs, nodules  220  may form where the gate  214  is exposed when the raised source/drain  208  is formed. The raised source/drain  208  is formed by epitaxial deposition of silicon which will grow anywhere that silicon is exposed. Since the pullback of the spacer  218  and/or hard mask  216  may expose part of the gate  214  which is usually polysilicon, epitaxial silicon may grow on the exposed part of the gate  214 , resulting in nodules  220 . Nodules  220  are undesirable since if they grow large enough, they may short the raised source/drain  208  and the gate  214 . 
         [0029]    Ensuring that the sides of the gate  214  are encapsulated so that the gate  214  is never exposed to the epitaxial silicon process is a desirable advantage of the exemplary embodiments. 
         [0030]    Referring now to  FIGS. 1A to 1H , there is illustrated a preferred process for forming a semiconductor substrate having fins for practicing the exemplary embodiments. The preferred process may be referred to as the sidewall image transfer process. 
         [0031]    In  FIG. 1A , the process begins with a semiconductor on insulator (SOI) substrate  102 , also frequently referred to as a silicon on insulator substrate. The SOI substrate  102  may comprise a semiconductor base  104  (usually silicon but may be other semiconductor materials), a dielectric layer  106 , usually an oxide layer (may also be called a buried oxide or BOX layer), and a semiconductor material  108 , which is usually silicon. For the purposes of the present exemplary embodiments, it is preferred that semiconductor material  108  is silicon and will be referred to as such in the discussion that follows. On top of silicon  108  is an oxide layer  110 , followed by an amorphous silicon layer  112  and hard mask layer  114 , usually a nitride. Not shown in  FIG. 1A  are photoresist and other layers which may be used to pattern the hard mask layer  114 . 
         [0032]    Referring now to  FIG. 1B , the hard mask layer  114  has been patterned and etched down through the amorphous silicon layer  112 , stopping on the oxide layer  110 . 
         [0033]    Referring now to  FIG. 1C , the hard mask layer  114  has been conventionally stripped, leaving only stripes of amorphous silicon  112 . Shown in  FIG. 1C  are only the ends of the stripes of amorphous silicon  112  which run perpendicular to the page. 
         [0034]    Thereafter, a conformal layer of nitride  116  is deposited over the stripes of amorphous silicon  112 , as shown in  FIG. 1D . 
         [0035]    The conformal layer of nitride  116  is conventionally etched to form sidewall spacers  118 , as shown in  FIG. 1E , followed by conventionally etching the stripes of amorphous silicon  112  to result in only the spacers  118  left on the surface of oxide layer  110 , as shown in  FIG. 1F . 
         [0036]    Using the spacers  118  as a mask, the substrate is etched to form fins  120  and stripes of oxide  122  on the fins  120  as shown in  FIG. 1G . 
         [0037]    Referring now to  FIG. 1  H, the spacers  118  and stripes of oxide  122  are conventionally etched to result in fins  120  on BOX layer  106 . 
         [0038]    In the description of  FIGS. 4A to 11A  and  4 B to  11 B that follows, the “A” Figure is a plan view of the FinFET structure as it is being processed and the “B” Figure is a cross-sectional view of the “A” Figure in the direction of the arrows B-B. 
         [0039]    Referring now to  FIGS. 4A and 4B , a first exemplary embodiment begins with a FinFET structure  400  comprising a semiconductor substrate  402 , such as an SOI substrate, comprising a semiconductor base layer  404  and an oxide layer  406 . The FinFET structure  400  further comprises a plurality of fins  408  which may have a hard mask layer  410 . The presence of the hard mask layer  410  is preferred for the first exemplary embodiment. While there are only two fins  408  shown in  FIGS. 4A and 4B , it should be understood that there will usually be many more such fins  408  in the FinFET structure  400 . 
         [0040]    Wrapping around the fins  408  is a gate  412  which may have a hard mask layer  414  on top of the gate  412 . For the purpose of illustration and not limitation, the gate  412  wraps around both of the fins  408 . In other exemplary embodiments, the gate  412  may wrap only one fin  408  or more than two fins  408 . For the purpose of illustration and not limitation, the gate  412  may comprise polysilicon. 
         [0041]    The hard mask  410  and hard mask  414  are usually a nitride, such as a silicon nitride for example. In a preferred embodiment, the hard mask  410  is an oxide. 
         [0042]    As best seen in  FIG. 4B , the FinFET structure  400  is exposed to angled implanting  416  of nitrogen which is directed against first surface  418  and second surface  420  of the gate  412 . The angled implanting of nitrogen should be at a low energy, such as 5 KV (kilovolts), so that the nitrogen does not penetrate the hard mask  410  of the fins  408  or the hard mask  414  of the gate  412 . The angle, α, of the angled implanting should be at about 30 degrees with respect to the vertical. This angle of 30 degrees is preferred to avoid shadowing from nearby structures. Since the direction of implanting is parallel to the fins  408 , the vertical surfaces of the fins  408  are substantially unaffected by the angled implanting  416  of the nitrogen. 
         [0043]    The FinFET structure  400  is then annealed at about 600 to 800° C., preferably about 600° C., in a saturated nitrogen ambient for about 10 to 30 minutes to convert the implanted nitrogen layer into a silicon nitride layer. The annealing temperature is kept low enough so that silicon nitride does not form in areas where it is not desired, such as on the sides of the fins  408 . While not wishing to be held to any particular theory, it is believed that the nitrogen implant breaks the silicon bonds in the gate  412  which makes it easier to form the silicon nitride layer during the annealing process. The thickness of the silicon nitride layer is about 1 to 2 nanometers. 
         [0044]    Referring now to  FIGS. 5A and 5B , gate  412  is shown having the silicon nitride layer  422  in first surface  418  and second surface  420 . In the first exemplary embodiment, the silicon nitride layer  422  extends from the hard mask  414  down the entire first surface  418  and second surface  420  to oxide layer  406 . While not shown in  FIGS. 5A and 5B , it is within the scope of the present exemplary embodiments for silicon nitride layer to extend only part way down to oxide layer  406  although such an embodiment may require extra steps to limit coverage of the silicon nitride layer  422 . However, silicon nitride layer  422  must extend to directly contact hard mask  414  to ensure that the gate  412  is not exposed during epitaxial deposition of the raised source/drain. 
         [0045]    Oxide or nitride spacers may be conventionally formed by depositing oxide or nitride and then etching back to form the spacers  424  shown in  FIGS. 6A and 6B . The spacers may be formed by depositing silicon nitride or silicon oxide over the silicon fins  408  and against surfaces  418 ,  420  of the gate  412  and then etching away the excess spacer material to leave spacers  424  against surfaces  418 ,  420  of the gate  412 . The spacers may be formed by, for example, plasma enhanced chemical vapor deposition (PECVD) followed by a subsequent thermal process at 700° C. or more. 
         [0046]    The silicon nitride layer  422  is situated between the gate  412  and the spacer  424  so as to seal the gate  412  on each side in case the spacer  424  and/or hard mask  414  is pulled back during the forming of the spacer  424 . 
         [0047]    The hard mask  410  from the fins  408  may be conventionally stripped by an etch process. In the preferred embodiment where the hard mask  410  is an oxide and the hard mask  414  is a nitride, there is good etch selectivity between the oxide and nitride materials so that the hard mask  410  may be selectively etched without adversely affecting the hard mask  414 . Then in a next process as shown in  FIGS. 7A and 7B , epitaxial silicon is grown on the silicon fins  408  to form a merged source and drain  426 . The epitaxial process to grow the epitaxial silicon may start with a hydrofluoric acid (HF) pre-clean, followed by a hydrogen (H2) anneal to purge out oxygen. The epitaxial silicon is achieved through a silane-based precursor to deposit epitaxial silicon on the silicon fins  408  and then form crystalline bonding. The flat surface shown for merged source and drain  426  may be achieved by an additional silicon etch back process. 
         [0048]    Again, because the gate  412  has been sealed, there is no longer the possibility of forming nodule defects as shown in  FIG. 3 . 
         [0049]    Referring now to  FIGS. 8A and 8B , a second exemplary embodiment begins with a FinFET structure  600  comprising a semiconductor substrate  602 , such as an SOI substrate, comprising a semiconductor base layer  604  and an oxide layer  606 . The FinFET structure  600  further comprises a plurality of fins  608  which may have a hard mask layer  610 . While there are only two fins  608  shown in  FIGS. 8A and 8B , it should be understood that there will usually be many more such fins  608  in the FinFET structure  600 . 
         [0050]    Wrapping around the fins  608  are a plurality of gates  612 ,  614 ,  616  which may have a hard mask layer  618  on top of each of the gates  612 ,  614 ,  616 . For the purpose of illustration and not limitation, the gates  612 ,  614 ,  616  wrap around both of the fins  608 . In other exemplary embodiments, the gates  612 ,  614 ,  616  may wrap around only one fin  608  or more than two fins  608 . For the purpose of illustration and not limitation, the gates  612 ,  614 ,  616  may comprise polysilicon. 
         [0051]    The hard mask  610  and hard mask  618  are usually a nitride, such as a silicon nitride for example. 
         [0052]    While there are a plurality of gates  612 ,  614 ,  616  shown in  FIGS. 8A and 8B , gates  612  and  616  are dummy gates in that their only purpose is to shadow the fins and a portion of the gate  614  during the implantation of the silicon nitride layer. The dummy gates  612 ,  616  may have no electrical function. Gate  614  is a functioning gate. 
         [0053]    As best seen in  FIG. 8B , the FinFET structure  600  is exposed to angled implanting  620  of silicon nitride by a process such as a gas cluster ion beam (GCIB) process. The GCIB process is a commercially available, high energy (about 60 KV) process which uses a highly pressurized reactive gas in which ionization of the reactive clusters occurs and impinges upon a surface to modify the surface upon impact. The dummy gates  612 ,  616  shadow the gate  614  so only a limited portion of first surface  622  and second surface  624  of the gate  614  are exposed to the GCIB process and the formation of the silicon nitride layer. The presence of the hard mask layer  610  is shown in the Figures for this second exemplary embodiment but it may not be necessary because of the presence of the dummy gates  612 ,  616  which shadow the fins  608  and prevent the GCIB process from contacting the fins  608 . 
         [0054]    The silicon nitride implanting is done at an angle, β, and should be at about 45 degrees with respect to the vertical. This angle of 45 degrees is preferred to avoid shadowing from nearby structures. Since the direction of implanting is parallel to the fins  608 , the vertical surfaces of the fins  608  are substantially unaffected by the angled implanting  620  of the silicon nitride. The thickness of the silicon nitride layer is about 1 to 2 nanometers. 
         [0055]    Unlike the first exemplary embodiment, there is no need to anneal the FinFET structure  600  since a silicon nitride layer forms on impact during implantation. 
         [0056]    Referring now to  FIGS. 9A and 9B , gate  614  is shown having the silicon nitride layer  626  in first surface  622  and second surface  624  of gate  614 . The silicon nitride layer  626  is only in the upper portion of the gate  614 . The silicon nitride layer  626  is also in the dummy gates  612 ,  616  but that is not important since dummy gates  612 ,  616  are nonfunctional. Silicon nitride layer  626  is in direct contact with hard mask  618  to ensure that the gate  614  is not exposed during epitaxial deposition of the raised source/drain. 
         [0057]    Oxide or nitride spacers may be conventionally formed by depositing oxide or nitride and then etching back to form the spacers  628  shown in  FIGS. 10A and 10B . The spacers may be formed by depositing silicon nitride or silicon oxide over the silicon fins  608  and against surfaces  622 ,  624  of the gate  614  and then etching away the excess spacer material to leave spacers  628  against surfaces  622 ,  624  of the gate  614 . The spacers may be formed by, for example, plasma enhanced chemical vapor deposition (PECVD) followed by a subsequent thermal process at 700° C. or more. 
         [0058]    The silicon nitride layer  626  is situated between the gate  614  and the spacer  628  so as to seal the gate  614  on each side in case the spacer  628  and/or hard mask  618  is pulled back during the forming of the spacer  628 . 
         [0059]    Spacers  628  may also be present on the dummy gates  612 ,  616  but that is not important since dummy gates  612 ,  616  are nonfunctional. 
         [0060]    The hard mask  610 , if present, on the fins  408  may be conventionally stripped. Then in a next process as shown in  FIGS. 11A and 11B , epitaxial silicon is grown on the silicon fins  608  to form a merged source and drain  630 . The epitaxial process to grow the epitaxial silicon may be the same as for the first exemplary embodiment. 
         [0061]    Again, because the gate  614  has been sealed, there is no longer the possibility of forming nodule defects as shown in  FIG. 3 . 
         [0062]    It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.