Abstract:
A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.

Description:
RELATED APPLICATION 
       [0001]    This application claims the benefit of and priority to U.S. Provisional Application Ser. No. 61/087,109, filed Aug. 7, 2008, the contents of which are incorporated by reference herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    The present disclosure relates to enhanced reliability for semiconductor devices. In particular, it relates to enhanced reliability for semiconductor devices using dielectric encasement. 
       SUMMARY 
       [0003]    The present disclosure relates to a method and device for enhanced reliability for semiconductor devices using dielectric encasement. In one or more embodiments, the method for enhanced reliability for semiconductor devices using dielectric encasement involves applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. 
         [0004]    In one or more embodiments, the layer of the photoimageable permanent dielectric material is a liquid dielectric. In alternative embodiments, the layer of the photoimageable permanent dielectric material is a dry film laminate. In some embodiments, the layer of the photoimageable permanent dielectric material is 1-300 μm (micrometer) thick. A thicker dielectric layer provides additional mechanical strength. 
         [0005]    In some embodiments, the semiconductor device includes a substrate layer comprising silicon (Si). In one or more embodiments, the features of the semiconductor device may include, but are not limited to, solder bond pads, die streets, and test features. In at least one embodiment, the layer of the photoimageable permanent dielectric material overlaps an under bump metallurgy (UBM) by at least 1 micron. 
         [0006]    In one or more embodiments, the method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In at least one embodiment, the solder is at least one solder sphere and/or a solder paste. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal. 
         [0007]    In some embodiments, the method for enhanced reliability for semiconductor devices using dielectric encasement comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device; patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature; dispensing solder, which contains flux, into the permanent dielectric material openings; and heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal. 
         [0008]    In one or more embodiments, the device for enhanced reliability for semiconductor devices using dielectric encasement comprises a substrate layer, at least one input/output (I/O) pad, a passivation layer, at least one under bump metallurgy (UBM), a layer of a photoimageable permanent dielectric material, fluxing material, and at least one solder sphere, which contains no flux. 
         [0009]    In some embodiments, at least one input/output (I/O) pad lies on a top surface of the substrate layer. Also, the passivation layer lies on a top surface of the substrate layer and lies on a portion of the top surface of each input/output (I/O) pad. In addition, at least one under bump metallurgy (UBM) lies on the top surface of each input/output (I/O) pad. The layer of the photoimageable permanent dielectric material lies on a top surface of the substrate layer and on a top surface of at least one under bump metallurgy (UBM), and the layer of the photoimageable permanent dielectric material is patterned to have an opening over each feature. The fluxing material lies inside the permanent dielectric material openings. Additionally, at least one solder sphere, which contains no flux, lies on a top surface of the fluxing material. The semiconductor device is heated to a reflow temperature appropriate for the reflow of at least one solder sphere, thereby causing at least one solder sphere to conform to sidewalls of the permanent dielectric material openings to form a protective seal. 
         [0010]    In one or more embodiments, the device for enhanced reliability for semiconductor devices using dielectric encasement comprises a substrate layer, at least one input/output (I/O) pad, a passivation layer, at least one under bump metallurgy (UBM), a layer of a photoimageable permanent dielectric material, and at least one solder sphere, which contains flux. 
         [0011]    In at least one embodiment, at least one input/output (I/O) pad lies on a top surface of the substrate layer. In addition, the passivation layer lies on a top surface of the substrate layer and lies on a portion of the top surface of each input/output (I/O) pad. Also, at least one under bump metallurgy (UBM) lies on the top surface of each input/output (I/O) pad. Additionally, the layer of the photoimageable permanent dielectric material lies on the top surface of the substrate layer and on a top surface of at least one under bump metallurgy (UBM). The layer of the photoimageable permanent dielectric material is patterned to have an opening over each feature. At least one solder sphere, which contains flux, lies inside the permanent dielectric material openings. The semiconductor device is heated to a reflow temperature appropriate for the reflow of at least one solder sphere, thereby causing at least one solder sphere to conform to sidewalls of the permanent dielectric material openings to form a protective seal. 
     
    
     
       DRAWINGS 
         [0012]    These and other features, aspects, and advantages of the present disclosure will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
           [0013]      FIG. 1  is a cross-sectional drawing of a semiconductor device, in accordance with at least one embodiment of the present disclosure. 
           [0014]      FIG. 2  is a cross-sectional drawing similar to that of  FIG. 1 , but shows the addition of a photoimageable permanent dielectric material applied to a top surface of the semiconductor device, in accordance with at least one embodiment of the present disclosure. 
           [0015]      FIG. 3  is a cross-sectional drawing similar to that of  FIG. 2 , but shows a layer of the photoimageable permanent dielectric material that is patterned to have an opening over a single feature, in accordance with at least one embodiment of the present disclosure. 
           [0016]      FIG. 4  is a cross-sectional drawing similar to that of  FIG. 3 , but shows the addition of fluxing material dispensed into or stencil printed onto the permanent dielectric material opening, in accordance with at least one embodiment of the present disclosure. 
           [0017]      FIG. 5  is a cross-sectional drawing similar to that of  FIG. 4 , but shows the addition of a solder sphere placed onto a top surface of the fluxing material, in accordance with at least one embodiment of the present disclosure. 
           [0018]      FIG. 6  is an illustration of a Scanning Electron Microscope (SEM) image showing the photoimageable permanent dielectric layer after patterning, in accordance with at least one embodiment of the present disclosure. 
           [0019]      FIG. 7  is an illustration of a SEM image showing the final structure of the semiconductor device after reflow, in accordance with at least one embodiment of the present disclosure. 
       
    
    
     DESCRIPTION 
       [0020]    The methods and apparatus disclosed herein provide an operative system for enhanced reliability for semiconductor devices, or wafer level chip scale packages (WLCSP). Specifically, this system employs the use of dielectric encasement to achieve enhanced reliability for a semiconductor device. 
         [0021]    The present disclosure relates to improvements in semiconductor device reliability performance, which is being demanded by original equipment manufacturers such as, but not limited to, cellular phone manufacturers. In particular, current semiconductor device technology is in need of improvements to the reliability of the solder joint connecting the chip to the substrate. 
         [0022]    During the normal cycle of heating and cooling (which causes expansion and contraction, respectively), which occurs during the use of an electronic device, and during periodic accidental dropping by the consumer (which causes mechanical shock) of an electronic device such as, but not limited to, a cellular phone, the solder joint can break. The breaking of the solder joint will cause a disruption in the function of the electronic device. As such, thermal cycle testing and drop testing are a standard part of the reliability qualification for semiconductor device technologies. 
         [0023]    Sealing improvements are needed between the solder and the underlying circuitry/metallization to protect against potential corrosive agents during subsequent processing of the electronic device and/or during the lifetime usage of the electronic device. The system of the present disclosure uses a material or a combination of materials that will not separate from the solder during the cool down phase of the reflow process, thereby creating a seal in the solder joint. 
         [0024]    The process, method, system, apparatus, and structure taught in this present disclosure lead to an increase in reliability of performance of semiconductor devices by minimizing the impact of thermal expansion, contraction, and mechanical shock that an electronic device may experience. In addition, the process, method, system, apparatus, and structure disclosed in the present application will allow for better sealing and protection of the underlying structures against corrosion or contamination, which can lead to premature device failure or malfunction. The process, method, system, apparatus, and structure taught in the present disclosure allow for improvement of semiconductor device mechanical and thermal reliability as well as for improvement of protection of the underlying structures of the device from corrosion. 
         [0025]    Various underfill and repassivation applications have been developed over the years. Wafer level chip scale packaging (WLCSP) repassivation applications disclosed in prior art involve applying a dielectric layer over a patterned under bump metallurgy (UBM) layer. In these applications, since the repassivation layer is applied over the under bump metallurgy (UBM), a sealing feature is created around the edges of the under bump metallurgy (UBM) pad. In addition, in industry, underfills have also been widely used. However, the use of underfills in industry has generally been limited to die level processing methods. Wafer level underfills have been disclosed in prior art. However, wafer level underfill processing and their resultant final structures are easily distinguishable from the process, method, system, apparatus, and structure that are disclosed in the present application. 
         [0026]    The disclosed apparatus, system, method, process, and structure taught in the present application would likely be used by a company utilizing similar WLCSP packaging requiring maximal thermal cycling and mechanical robustness. In particular, these types of companies likely include, but are not limited to, an original equipment manufacturer (OEM) that requires this packaging design criteria and any company involved with manufacturing chip scale packaging (CSP) or any similar type of packaging. One method that can be used to determine if the technology of the present disclosure was utilized in manufacturing a semiconductor device involves deconstructing the device into x-sections, and visually examining the final device structure by using either a high magnification optical microscope or a scanning electron microscope (SEM). However, it should be noted that other various methods may also be employed. 
         [0027]    In the following description, numerous details are set forth in order to provide a more thorough description of the system. It will be apparent, however, to one skilled in the art, that the disclosed system may be practiced without these specific details. In the other instances, well known features have not been described in detail so as not to unnecessarily obscure the system. 
         [0028]      FIGS. 1 through 5  collectively illustrate the steps for creating semiconductor devices with enhanced reliability using dielectric encasement.  FIG. 1  shows an illustration of a semiconductor device  100 , in accordance with at least one embodiment of the present disclosure. In this figure, the semiconductor device  100  is depicted as including a substrate layer  110 , an input/output (I/O) pad  130 , a passivation layer  120 , and an under bump metallurgy (UBM)  140 . In one or more embodiments, various types of semiconductor material may be used for the substrate layer  110  including, but not limited to, silicon (Si). 
         [0029]    In  FIG. 1 , an input/output (I/O) pad  130  lies on a top surface of the substrate layer  110 . In one or more embodiments, at least one input/output (I/O) pad  130  is employed by the disclosed device. Also shown in this figure, a passivation layer  120  lies on the top surface of the substrate layer  110  as well as lies on a portion of the top surface of the input/output (I/O) pad  130 . This figure also shows an under bump metallurgy (UBM)  140  lying on a top surface of the input/output (I/O) pad  130 . In at least one embodiment, the under bump metallurgy (UBM)  140  includes a recess for accepting a solder sphere  510  (See  FIG. 5 ). 
         [0030]      FIG. 2  illustrates the first step  200  for creating a semiconductor device  100  with enhanced reliability using dielectric encasement.  FIG. 2  shows a semiconductor device  100  with the addition of a photoimageable permanent dielectric material  210  applied to the top surface of the semiconductor device  100 . In this figure, a thick blanket coating of photoimageable permanent dielectric material  210  is applied to the top surface of the semiconductor device  100 . This thick blanket coating  210  completely covers the top surface of the under bump metallurgy ( 140 ) as well as the top surface of the passivation layer  120  of the semiconductor device  100 . 
         [0031]    In one or more embodiments, the photoimageable permanent dielectric layer  210  may be either a liquid dielectric or a dry film laminate. In at least one embodiment, the dielectric material in the dielectric layer  210  is photodefineable or laser ablatable. In some embodiments, the photoimageable permanent dielectric layer  210  has a thickness in the range of 1-300 μm (micrometers). A thicker photoimageable permanent dielectric layer  210  provides additional mechanical strength to the semiconductor device  100 . 
         [0032]      FIG. 3  illustrates the second step  300  for creating a semiconductor device  100  with enhanced reliability using dielectric encasement.  FIG. 3  shows a layer of the photoimageable permanent dielectric material  210  that is patterned to have an opening  310  over a single feature of the semiconductor device  100 . In this figure, the single feature is an under bump metallurgy (UBM)  140 . In some embodiments, the photoimageable permanent dielectric layer  210  is patterned such that the photoimageable permanent dielectric material  210  overlaps the under bump metallurgy (UBM)  140  by at least one micron. In alternative embodiments, the photoimageable permanent dielectric layer  210  may be patterned to have an openings  310  over features including, but not limited to, solder bond pads, die streets, and test features. 
         [0033]      FIG. 4  illustrates the third step  400  for generating a semiconductor device  100  with enhanced reliability using dielectric encasement.  FIG. 4  shows the addition of fluxing material  410  dispensed into or stencil printed onto the permanent dielectric material opening  310  of the semiconductor device  100 . This figure illustrates a fluxing material type  410  being dispensed into or stencil printed onto at least one permanent dielectric material opening  310 . 
         [0034]      FIG. 5  depicts the fourth step  500  for manufacturing a semiconductor device  100  with enhanced reliability using dielectric encasement. In particular,  FIG. 5  shows the addition of a solder sphere  510 , which contains no flux, placed onto a top surface of the fluxing material  410 . During this step, spheres of solder  510 , which contain no flux, are dropped or applied onto the fluxing material  410 , which has been dispensed into the permanent dielectric material openings  310  of the semiconductor device  100 . In alternative embodiments, solder paste is employed instead of or in addition to a solder sphere  510 . 
         [0035]    In alternative embodiments, spheres of solder  510  containing flux are employed by the disclosed method and/or device. In these embodiments, no fluxing material  410  is required. As such, for these embodiments, spheres of solder  510  containing flux are dispensed directly into the permanent dielectric material openings  310  of the semiconductor device  100 . 
         [0036]    After the spheres of solder  510  are applied to the semiconductor device  100 , the semiconductor device  100  is heated to a reflow temperature appropriate for the reflow of the solder spheres  510 . During the reflow process, the solder material  510  fills and conforms to the sidewalls of the permanent dielectric openings  310 , thereby forming a protective seal  520  against corrosive agents. 
         [0037]      FIG. 6  contains an illustration of a Scanning Electron Microscope (SEM) image showing the photoimageable permanent dielectric layer  210  after patterning. In this figure, the photoimageable permanent dielectric material  210  is shown to be patterned to have an opening  310  over an under bump metallurgy (UBM)  140 .  FIG. 7  shows an illustration of a SEM image showing the final structure of the semiconductor device  100  after reflow. In particular, this figure shows a semiconductor device  100  having a patterned photoimageable permanent dielectric layer  210  having an opening over an under bump metallurgy (UBM)  140 . Also, in this figure, a solder sphere  510  is shown to be applied to the under bump metallurgy (UBM)  140  of the semiconductor device  100 . The height of the encasement structure can vary, and may be as tall as 75% of the bump diameter. 
         [0038]    In one or more embodiments, the addition of a thicker photoimageable dielectric material layer to the disclosed semiconductor device would enable building the effective polymer layer higher and, thus, allow for a continuous layer of buffer against thermal expansion stress and mechanical shock, as well as allow for protection from corrosive elements. When employing the disclosed method, the thickness of the permanent dielectric material layer is easy to control, and can be altered to be application specific. The height of the effective encasement surrounding the solder sphere is important since prior art on wafer applied underfills has shown that as the underfill height-to-bump ratio is increased, the thermal cycle life is also increased. Prior art has also shown that as the underfill height-to-bump ratio is increased, the resistance to mechanical shock may also be increased. 
         [0039]    In some embodiments, the height of the photoimageable permanent dielectric layer can be tailored to meet the needs of particular designs. In particular, the height of the photoimageable permanent dielectric layer can be tailored according to the types and sizes of the solder spheres being employed by the design. In at least one embodiment, the opening where the solder sphere sits can be completely filled-in or sealed with solder (or some other type of fluxing underfill material) after the reflow process for creating a continuous protective repassivation layer. This wafer level chip scale packaging (WLCSP) encasement approach is versatile, and can be used on standard sputtered metal and electroplated copper (Cu) applications as well as electroless Ni/Au and electroless Ni/Pd/Au under bump metallurgy (UBM) options. Since the disclosed method is a wafer level application, it is an attractive option compared to the current die level underfill method alternatives. 
         [0040]    In alternative embodiments, the photoimageable permanent dielectric material is opened, and a polymer collar fluxing agent is dispensed into the opening. This method produces a modified blanket layer. For these alternative embodiments, the blanket coat material does not necessarily need to be photoimageable. However, the blanket coat material must be able to act as a fluxing agent, and be able to adhere the solder to the under bump metallurgy (UBM). 
         [0041]    Although certain illustrative embodiments and methods have been disclosed herein, it can be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods can be made without departing from the true spirit and scope of the art disclosed. Many other examples of the art disclosed exist, each differing from others in matters of detail only. Accordingly, it is intended that the art disclosed shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.