Abstract:
Disclosed is an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; and N number of switching sections each of which receives N bits of data applied sequentially through one data pin after the write command is activated, wherein each of the switching sections exclusively outputs one bit from among the N bits of data by using an output signal of the decoding section and a signal for determining a burst type.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a data distribution device for a memory device, and more particularly to a data distribution device which determines a scheme for distributing data applied when a write command is activated. 
   2. Description of the Prior Art 
   As generally known in the art, a synchronous memory device (such as a DDR SDRAM, a DDR2 SDRAM, etc.) receives and outputs data in synchronization with a clock signal. For example, in the case of a write operation in the DDR2 SDRAM, a write command and a column address are applied in synchronization with the rising edge of a clock signal, first data and second data are inputted in synchronization with the rising edge and the falling edge of the next clock signal, respectively, and then in a similar way, data as long as a burst length are continuously applied in synchronization with the rising edges and the falling edges of the clock signals consecutively following. Data continuously-applied as described above are inputted through each of data pins. For convenience of description, it is assumed that a memory device discussed in this document has a burst length of ‘4’. 
   Generally, in a write operation, 4-bit data (e.g., din 0 r&lt; 0 &gt;, din 0 f&lt; 0 &gt;, din 1 r&lt; 0 &gt; and din 1 f&lt; 0 &gt;), which have been sequentially (serially) applied through a specific data pin in synchronization with rising and falling edges of clock signals, are stored in four registers in one-to-one correspondence, and then are inputted to four input lines in one-to-one correspondence in synchronization with a clock signal. That is, the four registers function as a serial-to-parallel converter. The data din 0 r&lt; 0 &gt;, din 0 f&lt; 0 &gt;, din 1 r&lt; 0 &gt; and din 1 f&lt; 0 &gt; applied to the four input lines are transferred to four global input/output lines, respectively, and are then stored in a memory cell array. Herein, the data din 0 r&lt; 0 &gt;, din 0 f&lt; 0 &gt;, din 1 r&lt; 0 &gt; and din 1 f&lt; 0 &gt; represent data applied sequentially through a data pin DQ0 in synchronization with rising and falling edges of clock signals. 
   Meanwhile, before the four pieces of data are transferred to the global input/output lines, an operation of determining the sequence and positions for storing the four pieces of data in the memory cell array is performed. In this document, this operation is called ‘data distribution operation’ for convenience of description. Generally, the data distribution operation is determined according to a burst type and a starting column address. Herein, the burst type includes a sequential mode and an interleave mode, which are modes for determining a data application sequence. A starting column address used in this document represents the lowest two bits (A 1  and A 0 ) of a column address, which is also defined in the JEDEC standard. As generally known in the art, the above-mentioned four global input/output lines corresponds to the decoding values 0, 1, 2 and 3 of the starting column address, respectively. Therefore, data are transferred to the four global input/output lines in one-to-one correspondence according to the starting column address and the burst type. 
   Table 1 shows a data access sequence according to burst lengths, starting column addresses and burst types. 
   
     
       
             
             
             
           
             
             
             
             
           
             
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Burst 
               Starting Column 
               Access Sequence 
             
           
        
         
             
               Length 
               Address 
               Sequential Type 
               Interleave Type 
             
             
                 
             
           
        
         
             
               2 
               A0 
                 
                 
                 
                 
             
             
                 
               0 
                 
                 
               0-1 
               0-1 
             
             
                 
               1 
                 
                 
               1-0 
               1-0 
             
             
               4 
               A1 
               A0 
             
             
                 
               0 
               0 
                 
               0-1-2-3 
               0-1-2-3 
             
             
                 
               0 
               1 
                 
               1-2-3-0 
               1-0-3-2 
             
             
                 
               1 
               0 
                 
               2-3-0-1 
               2-3-0-1 
             
             
                 
               1 
               1 
                 
               3-0-1-2 
               3-2-1-0 
             
             
               8 
               A2 
               A1 
               A0 
             
             
                 
               0 
               0 
               0 
               0-1-2-3-4-5-6-7 
               0-1-2-3-4-5-6-7 
             
             
                 
               0 
               0 
               1 
               1-2-3-4-5-6-7-0 
               1-0-3-2-5-4-7-6 
             
             
                 
               0 
               1 
               0 
               2-3-4-5-6-7-0-1 
               2-3-0-1-6-7-4-5 
             
             
                 
               0 
               1 
               1 
               3-4-5-6-7-0-1-2 
               3-2-1-0-7-6-5-4 
             
             
                 
               1 
               0 
               0 
               4-5-6-7-0-1-2-3 
               4-5-6-7-0-1-2-3 
             
             
                 
               1 
               0 
               1 
               5-6-7-0-1-2-3-4 
               5-4-7-6-1-0-3-2 
             
             
                 
               1 
               1 
               0 
               6-7-0-1-2-3-4-5 
               6-7-4-5-2-3-0-1 
             
             
                 
               1 
               1 
               1 
               7-0-1-2-3-4-5-6 
               7-6-5-4-3-2-1-0 
             
             
                 
             
           
        
       
     
   
     FIG. 1  is a block diagram for explaining a conventional data distribution scheme. For reference, a 16-bit control signal ctr 1 &lt; 0 : 15 &gt;, which is applied to each latch section to control an operation of distributing input data, functions to determine a distribution sequence of 4-bit input data according to burst types and starting column addresses. 
   As shown in  FIG. 1 , 4-bit data din 0 r&lt; 0 &gt;, din 0 f&lt; 0 &gt;, din 1 r&lt; 0 &gt; and din 1 f&lt; 0 &gt; inputted sequentially through a data pin DQ0 are applied to a latch section  100 . The latch section  100  transfers the data din 0 r&lt; 0 &gt;, din 0 f&lt; 0 &gt;, din 1 r&lt; 0 &gt; and din 1 f&lt; 0 &gt; to global input/output lines gio_ 0 _ 0 , gio_ 1 _ 0 , gio_ 2 _ 0  and gio_ 3 _ 0  in one-to-one correspondence according to logic levels of the 16-bit control signal ctr 1 &lt; 0 : 15 &gt;. 
   4-bit data din 0 r&lt; 1 &gt;, din 0 f&lt; 1 &gt;, din 1 r&lt; 1 &gt; and din 1 f&lt; 1 &gt; inputted sequentially through a data pin DQ1 are applied to a latch section  101 . The latch section  101  transfers the data din 0 r&lt; 1 &gt;, din 0 f&lt; 1 &gt;, din 1 r&lt; 1 &gt; and din 1 f&lt; 1 &gt; to global input/output lines gio_ 0 _ 1 , gio_ 1 _ 1 , gio_ 2 _ 1  and gio_ 3 _ 1  in one-to-one correspondence according to logic levels of the 16-bit control signal ctr 1 &lt; 0 : 15 &gt;. 
   4-bit data din 0 r&lt; 2 &gt;, din 0 f&lt; 2 &gt;, din 1 r&lt; 2 &gt; and din 1 f&lt; 2 &gt; inputted sequentially through a data pin DQ 2  are applied to a latch section  102 . The latch section  102  transfers the data din 0 r&lt; 2 &gt;, din 0 f&lt; 2 &gt;, din 1 r&lt; 2 &gt; and din 1 f&lt; 2 &gt; to global input/output lines gio_ 0 _ 2 , gio_ 1 _ 2 , gio_ 2 _ 2  and gio_ 3 _ 2  in one-to-one correspondence according to logic levels of the 16-bit control signal ctr 1 &lt; 0 : 15 &gt;. 
   4-bit data din 0 r&lt; 3 &gt;, din 0 f&lt; 3 &gt;, din 1 r&lt; 3 &gt; and din 1 f&lt; 3 &gt; inputted sequentially through a data pin DQ3 are applied to a latch section  103 . The latch section  103  transfers the data din 0 r&lt; 3 &gt;, din 0 f&lt; 3 &gt;, din 1 r&lt; 3 &gt; and din 1 f&lt; 3 &gt; to global input/output lines gio_ 0 _ 3 , gio_ 1 _ 3 , gio_ 2 _ 3  and gio_ 3 _ 3  in one-to-one correspondence according to logic levels of the 16-bit control signal ctr 1 &lt; 0 : 15 &gt;. 
   As shown in  FIG. 1 , according to the conventional data distribution device, each latch section receives a 16-bit control signal through 16 number of control lines in order to perform a distribution operation for 4-bit data applied to each latch section. For this reason, the conventional data distribution device has a problem in that a large layout area is required for disposition of control lines. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a data distribution device for a memory device which can reduce the number of control lines required for a control signal to perform a data distribution operation, thereby reducing the layout area for disposition of the control lines. 
   In order to accomplish this object, there is provided an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; and N number of switching sections each of which receives N bits of data applied sequentially through one data pin after the write command is activated, wherein each of the switching sections exclusively outputs one bit from among the N bits of data by using an output signal of the decoding section and a signal for determining a burst type. 
   Herein, output nodes of the switching sections one-to-one correspond to global input/output lines of the memory device, and a disposition sequence of the N-bit data transferred to the global input/output lines is determined by a combination of the output signal of the decoding section and the signal for determining a burst type. 
   In accordance with another aspect of the present invention, there is provided an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; a plurality of control sections which use an output signal of the decoding section and a signal for determining a burst type as control signals; and a plurality of first switching sections and second switching sections each of which receives N bits of data sequentially applied as long as a burst length through one data pin after the write command is activated, wherein each of the first switching sections exclusively outputs one bit from among the N-bits of data in response to an output signal of the decoding section, and each of the second switching sections exclusively outputs one bit from among the N bits of data in response to output signals of the decoding section and the control section. 
   Herein, output nodes of the first and second switching sections one-to-one correspond to global input/output lines of the memory device, and a disposition sequence of the N-bit data transferred to the global input/output lines is determined by a combination of the output signal of the decoding section and the signal for determining a burst type. In addition, data outputted from the first switching sections are determined by the starting column address, and data outputted from the second switching sections are determined by the starting column address and the burst type. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram for explaining a conventional data distribution scheme; 
       FIG. 2  is a block diagram for explaining a data distribution scheme according to an embodiment of the present invention; 
       FIG. 3  is a block diagram illustrating a configuration of a data distribution section shown in  FIG. 2  according to an embodiment of the present invention; 
       FIG. 4  is a circuit diagram illustrating a control section shown in  FIG. 3 ; 
       FIG. 5A  is a block diagram illustrating a switching section shown in  FIG. 3 ; 
       FIG. 5B  is a circuit diagram illustrating a switch element shown in  FIG. 5A ; and 
       FIG. 6  is a circuit diagram illustrating an amplifier shown in  FIG. 5A . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted. 
     FIG. 2  is a block diagram for explaining a data distribution scheme according to an embodiment of the present invention. For reference, although  FIG. 2  shows a X4 mode as an example, those skilled in the art will appreciate that the concept of the present invention will be identically applied to X8 and X16 modes. 
   Referring to  FIG. 2 , after a data distribution section  200  receives 4-bit data din 0 _q 0 , din 0 _q 1 , din 0 _q 2  and din 0 _q 3  applied through a data pin DQ0, and the data distribution section  200  determines a transmission sequence of the 4-bit data to be transferred in one-to-one correspondence to global input/output lines gio 0 _r 0 , gio 0 _f 0 , gio 0 _r 1  and gio 0 _f 1  according to logic levels of 4-bit control signals dinclk, seq_intb, A 1  and A 0 . 
   After a data distribution section  201  receives 4-bit data din 1 _q 0 , din 1 _q 1 , din 1 _q 2  and din 1 _q 3  applied through a data pin DQ 1 , and the data distribution section  201  determines a transmission sequence of the 4-bit data to be transferred in one-to-one correspondence to global input/output lines gio 1 _r 0 , gio 1 _f 0 , gio 1 _r 1  and gio 1 _f 1  according to logic levels of 4-bit control signals dinclk, seq_intb, A 1  and A 0 . 
   After a data distribution section  202  receives 4-bit data din 2 _q 0 , din 2 _q 1 , din 2 _q 2  and din 2 _q 3  applied through a data pin DQ 2 , and the data distribution section  202  determines a transmission sequence of the 4-bit data to be transferred in one-to-one correspondence to global input/output lines gio 2 _r 0 , gio 2 _f 0 , gio 2 _r 1  and gio 2 _f 1  according to logic levels of 4-bit control signals dinclk, seq_intb, A 1  and A 0 . 
   After a data distribution section  203  receives 4-bit data din 3 _q 0 , din 3 _q 1 , din 3 _q 2  and din 3 _q 3  applied through a data pin DQ 3 , and the data distribution section  203  determines a transmission sequence of the 4-bit data to be transferred in one-to-one correspondence to global input/output lines gio 3 _r 0 , gio 3 _f 0 , gio 3 _r 1  and gio 3 _f 1  according to logic levels of 4-bit control signals dinclk, seq_intb, A 1  and A 0 . 
   Referring to  FIG. 2 , it can be understood that the data distribution device according to the present invention uses only four control signals, thereby having a more efficient layout than the conventional device using a 16-bit control signal. 
   Hereinafter, how to function as a data distribution section using only a 4-bit control signal will be described in detail. 
     FIG. 3  is a block diagram illustrating the detailed configuration of a data distribution section shown in  FIG. 2  according to an embodiment of the present invention. Herein, reference numeral ‘ 300 ’ represents one of data distribution sections shown in  FIG. 2 . For reference, data q 0 , q 1 , q 2  and q 3  in  FIG. 3  correspond to 4-bit data applied to each data distribution section in  FIG. 2 , and global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1  in  FIG. 3  correspond to global input/output lines of each data distribution section in  FIG. 2 . 
   As shown in  FIG. 3 , the data distribution section  300  includes a decoding section  301 , control sections  302  and  303 , and switching sections  304 ,  305 ,  306  and  307 . 
   The decoding section  301  receives a starting column address (A 0 , A 1 ), and outputs first decoding signals a 1 _ 00  and a 0 _ 00 , second decoding signals a 1 _ 01  and a 0 _ 01 , third decoding signals a 1 _ 10  and a 0 _ 10 , and fourth decoding signals a 1 _ 11  and a 0 _ 11 . 
   As shown in this drawing, the logic levels of the first decoding signals a 1 _ 00  and a 0 _ 00  are equal to those of (A 1 , A 0 ), the logic levels of the second decoding signals a 1 _ 01  and a 0 _ 01  are equal to those of (A 1 , /A 0 ), the logic levels of the third decoding signals a 1 _ 10  and a 0 _ 10  are equal to those of (/A 1 , A 0 ), and the logic levels of the fourth decoding signals a 1 _ 11  and a 0 _ 11  are equal to those of (/A 1 , /A 0 ). 
   A burst type determination signal seq_intb and the signal a 0 _ 01 , which are applied to the control section  302 , are used as control signals. When signal a 1 _ 01  is applied through an input node D of the control section  302 , the control section  302  outputs either a signal having a logic level equal to that of the signal a 1 _ 01  or a signal having a logic level opposite to (i.e., a logic level inverted from) that of the signal a 1 _ 01 , through its output node Q, according to logical levels of the control signals a 0 _ 01  and seq_intb. 
   Similarly, a burst type determination seq_intb and a signal a 0 _ 11  applied to the control section  303  are used also as control signals. When signal a 1 _ 11  applied through an input node D of the control section  303 , the control section  303  outputs either a signal having a logic level equal to that of the signal a 1 _ 11  or a signal having a logic level opposite to (i.e., a logic level inverted from) that of the signal a 1 _ 11 , through its output node Q, according to logical levels of the control signals a 0 _ 11  and seq_intb. 
   For reference, the burst type determination signal seq_intb applied to the control sections  302  and  303  is a signal to determine whether the burst type is a sequential type or an interleave type. In this document, a burst type determination signal seq_intb having a high level represents the sequential type, and a burst type determination signal seq_intb having a low level represents the interleave type. As shown in  FIG. 4  which illustrates a detailed configuration of the control section  302  or  303 , a level of a signal outputted from each of the control sections  302  and  303  is determined depending on whether the burst type is the sequential type or the interleave type. 
   Each of the switching sections  304 ,  305 ,  306  and  307  functions as a multiplexer which selects and outputs one of the input data q 0 , q 1 , q 2  and q 3 . Herein, the input data q 0  to q 3  inputted commonly to the switching sections represents 4-bit data inputted sequentially through one data pin. Therefore, in the case of X4 as shown in  FIG. 2 , it should be noted that three circuits equal to that shown in  FIG. 3  are further included. 
   The switching section  304  selects one of the input data q 0  to q 3  and transfers the selected datum to a global input/output line gio_r 0 . In this case, the datum selected and outputted by the switching section  304  is determined by signals a 1 _ 00  and a 0 _ 00 . The switching section  304  operates in synchronization with a clock signal dinclk. The switching sections  305 ,  306  and  307  described later in this document also operate in synchronization with the clock signal dinclk. 
   The switching section  305  selects one of the input data q 0  to q 3  and transfers the selected datum to a global input/output line gio_f 0 . In this case, the datum selected and outputted by the switching section  305  is determined by a signal a 0 _ 01  and an output signal a 1 _ 01 _out of the control section  302 . 
   The switching section  306  selects one of the input data q 0  to q 3  and transfers the selected datum to a global input/output line gio_r 1 . In this case, the datum selected and outputted by the switching section  306  is determined by signals a 1 _ 10  and a 0 _ 10 . 
   The switching section  307  selects one of the input data q 0  to q 3  and transfers the selected datum to a global input/output line gio_f 1 . In this case, the datum selected and outputted by the switching section  307  is determined by a signal a 1 _ 11  and an output signal a 1 _ 11 _out of the control section  303 . 
   The operation of the circuit shown in  FIG. 3  will now be described in detail. 
   According to an embodiment, it is assumed that the input data (q 0 , q 1 , q 2 , q 3 ) are (1, 0, 1, 1), the burst type is the sequential type, and a starting column address (A 1 , A 0 ) is (1,0). 
   In this case, as shown in Table 1, the starting column address (A 1 , A 0 ) has a value of ‘2’, and a data access sequence is a sequence of 2, 3, 0 and 1. Therefore, the switching section  304  selects and outputs ‘q 2 ’, the switching section  305  selects and outputs ‘q 3 ’, the switching section  306  selects and outputs ‘q 0 ’, and the switching section  307  selects and outputs ‘q 1 ’. Accordingly, data q 2 , q 3 , q 0  and q 1  are transferred to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1 , respectively. That is, data applied to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1  are (1,1,1,0), respectively. 
   According to another embodiment, it is assumed that the input data (q 0 ,q 1 ,q 2 ,q 3 ) are (1,0,1,1), the burst type is the interleave type, and a starting column address (A 1 , A 0 ) is (1,0). 
   In this case, as shown in Table 1, a data access sequence is equal to that in the case of the sequential type. Therefore, data q 2 , q 3 , q 0  and q 1  are transferred to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1 , respectively. That is, data applied to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1  are (1,1,1,0), respectively. 
   According to still another embodiment, it is assumed that the input data (q 0 ,q 1 ,q 2 ,q 3 ) are (1,0,0,1), the burst type is the sequential type, and a starting column address (A 1 , A 0 ) is (0,1). In this case, data q 1 , q 2 , q 3  and q 0  are transferred to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1 , respectively. That is, data applied to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1  are (0,0,1,1), respectively. 
   In contrast, when the input data (q 0 ,q 1 ,q 2 ,q 3 ) are (1,0,0,1), the burst type is the interleave type and a starting column address (A 1 , A 0 ) is (0,1), data q 1 , q 0 , q 3  and q 2  are transferred to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1 , respectively. That is, data applied to the global input/output lines gio_r 0 , gio_f 0 , gio_r 1  and gio_f 1  are (0,1,1,0), respectively. 
     FIG. 4  is a circuit diagram illustrating a control section  302  or  303  shown in  FIG. 3 . 
   As shown in  FIG. 4 , the control section outputs either a signal having the logic level equal to that of an input signal (e.g., a 1 _ 01  or a 1 _ 11  in  FIG. 3 ) applied to its input node D or a signal having the inverted logic level of the input signal (e.g., a 1 _ 01  or a 1 _ 11  in  FIG. 3 ) through its output node Q, depending on the logic levels of control signals in 1  and in 2 . The reason will be described with reference to table 1. Referring to Table 1, when a burst length is ‘4’ and a starting column address is ‘0’, data are distributed in a sequence (access sequence) of 0, 1, 2 and 3 regardless of burst types. Also, when a burst length is ‘4’ and a starting column address is ‘2’, the data are distributed in a sequence of 2, 3, 0 and 1 regardless of burst types. 
   However, when a burst length is ‘4’ and a starting column address is ‘1’, the data are distributed in a sequence of 1, 2, 3 and 0 in the case of the sequential type, and the data are distributed in a sequence of 1, 0, 3 and 2 in the case of the interleave type. It can be understood in this case that the data distribution sequence changes depending on the burst types. Similarly, when a burst length is ‘4’ and a starting column address is ‘3’, the data distributed in a sequence of 3, 0, 1 and 2 in the case of the sequential type, and the data are distributed in a sequence of 3, 2, 1 and 0 in the case of the interleave type. That is it can be understood in this case that the data distribution sequence changes depending on the burst types. As described above, the control section is a circuit for compensating a data distribution sequence which changes depending on burst types. For reference, in  FIG. 3 , each of the switching sections  305  and  307  receives an output signal of a corresponding control section  302  or  303 , and selects and outputs one of the data q 0 , q 1 , q 2  and q 3  by using a starting column address. 
     FIG. 5A  is a block diagram illustrating one of the switching sections  304  to  307  shown in  FIG. 3 , and  FIG. 5B  is a circuit diagram illustrating one of switch elements  51 ,  52  and  53  shown in  FIG. 5A . 
   Since the operation of the switching section as shown in  FIG. 5A  is described above, an additional description thereof will be omitted. For reference, a clock signal dinclk applied to the switching section functions to determine a time point at which selected data is transferred to global input/output lines. 
     FIG. 6  is a circuit diagram illustrating an amplifier  54  shown in  FIG. 5A . The amplifier shown in  FIG. 6  is only an example, and those skilled in the art may use various amplification circuits to achieve the same function as that of the amplifier. 
   Also,  FIGS. 4 to 6  show only examples of circuits for achieving the function of the data distribution section shown in  FIG. 3 . Those skilled in the art may use various types of circuits to achieve the same functions as those of circuits shown in  FIGS. 4 to 6 . 
   According to the method described with reference to  FIG. 3  in the present invention, 4-bit data applied sequentially through one data pin are transferred to global input/output lines by using 4 control signals A 1 , A 0 , seq_intb and dinclk. 
   As described above, the present invention discloses a configuration for distributing input data to global input/output lines by using only four control signals A 1 , A 0 , seq_intb and dinclk. 
   According to an embodiment of the present invention, the number of control signals required in a device, which determines a distribution sequence of data inputted through one data pin, is reduced, thereby significantly reducing the layout area for disposition of control lines. 
   Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.