Abstract:
Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface.

Description:
BACKGROUND 
     1. Technical Field 
     The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to structures including a via having a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method. 
     2. Background Art 
     In the integrated circuit (IC) chip fabrication industry, electromigration (EM) induced failure is a major concern for advanced back-end-of-line (BEOL) technology. Early EM induced failure, in particular, significantly reduces the projected current limit of product chip under operating conditions. One type of EM induced failure is referred to as “line-depletion.” As shown in  FIGS. 1A-C , line-depletion EM includes electron current flowing from an upwardly extending via  10  down into a metal wire  12  below. As electron current flows, atoms move causing “slit void” failures  14  ( FIG. 1C ) initiating, for example, at a site  16  ( FIG. 1B ) between via  10  and a liner-less interface  18  between metal wire  12  and a dielectric layer  20  thereabove. It is well known that this slit void may cause very early fails under electromigration conditions during circuit operation, since it does not take much time to form such a small void. The arrows in  FIGS. 1A and 1B  show the direction of EM flux (i.e., the atom flow during electromigration). Typically, slit void failures  14  ( FIG. 1C ) start (or nucleate) at defective sites  16  ( FIG. 1B ) around an interface between via  10  and metal wire  12 , and grow into a bottom  22  of via  10  until it extends over an entire interface and causes an electrical open  24 , as depicted in  FIG. 1C . Slit void failures  14  occur in both structures with (as shown) or without via gouging, i.e., where via  10  extends into metal wire  12 . 
     SUMMARY 
     Structures including a refractory metal collar at a metal wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer, and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface. 
     A first aspect of the disclosure provides a structure comprising: a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. 
     A second aspect of the disclosure provides a method comprising: providing a copper wire in a first dielectric layer; forming a second dielectric layer over the copper wire to form a liner-less interface between the copper wire and the second dielectric layer; forming an opening through the second dielectric layer and into the copper wire; creating an undercut from the opening under the second dielectric layer; forming a refractory metal collar in the undercut; and filling the opening with a metal to form a via. 
     A third aspect of the disclosure provides a structure comprising: a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer, the via including a substantially frusto-conical portion within the copper wire; a first liner about the via, the first liner including a refractory metal; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. 
     The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which: 
         FIGS. 1A-C  show a conventional via and metal wire interface in which electromigration causes a failure. 
         FIG. 2  shows a structure according to embodiments of the disclosure. 
         FIGS. 3-7  show embodiments of a method of forming the structure of  FIG. 2 . 
     
    
    
     It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings. 
     DETAILED DESCRIPTION 
       FIG. 2  shows a structure  100  according to embodiments of the disclosure. Structure  100  includes a via  110  extending upwardly from a metal wire  112 , e.g., copper, through a dielectric layer  120 . In one embodiment, via  110  includes a substantially frusto-conical portion  122  within metal wire  112 . However, the teachings of the invention are not limited to that type of via. Metal wire  112  is positioned within another dielectric layer  124 , and includes a liner  126  between metal wire  112  and dielectric layer  124 . Liner  126  may include any now known or later developed metal diffusion barrier material, for example, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, etc. Note, however, liner  126  separates metal wire  112  and dielectric layer  124  along only a bottom  128  and sides  130  of metal wire  112 . Accordingly, metal wire  112  includes a liner-less interface  118  with dielectric layer  120  thereabove. 
     Dielectric layer  120  includes a barrier layer  132  forming liner-less interface  118  with metal wire  112 , and an interlevel dielectric  134  above barrier layer  132 . Barrier layer  132  may include any now known or later developed dielectric barrier layer such as silicon carbide (SiC), silicon nitride (Si 3 N 4 ) silicon dioxide (SiO 2 ), nitrogen or hydrogen doped silicon carbide (SiC(N,H)), etc. Interlevel dielectric  134  may include any now known or later developed porous or non-porous interlevel dielectric material, such as silicon oxide, silicon nitride, hydrogenated silicon oxycarbide (SiCOH), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK (a polyarylene ether available from Dow Chemical Corporation), JSR (a spin-on silicon-carbon contained polymer material available form JSR Corporation), other low dielectric constant (&lt;3.9) material, or layers thereof. 
     Structure  100  also includes a refractory metal collar  140  extending from a side  142  of via  110  and partially along liner-less interface  118 . In addition, a first liner  144  may be formed about via  110 , first liner  144  including the same refractory metal. In one embodiment, the refractory metal includes ruthenium; however, other refractory metals such as tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh) and platinum (Pt), etc., or mixtures of thereof, may also be employed. Via  110  may also include a second liner  146  about the via, where second liner  146  includes at least one metal diffusion barrier  150  (i.e., liner) and a metal seed layer  152  for seeding for a metal  158  that forms via  110 . In one embodiment, metal  158  includes copper; however, other metals such as copper alloy, aluminum (Al), aluminum alloy, silver (Ag), etc. may be employed. Metal diffusion barrier(s)  150  may include, for example: tantalum/tantalum nitride titanium/titanium nitride, tungsten/tungsten nitride, ruthenium/ruthenium nitride. etc.; and metal seed layer  152  may include copper (Cu) or other alloy materials, where metal  158  is copper, for example: copper, copper aluminum, and other copper alloy such as copper iridium, copper nickel, and/or copper ruthenium. 
     Refractory metal collar  140  and metal wire  112  interface presents a slow electromigration (EM) path in which the EM flux (i.e., the atom flow during electromigration) is forced down, as shown by the arrow, into metal wire  110  instead of concentrating near liner-less interface  118  (as in  FIGS. 1A-B ). In particular, the interface between metal wire  112  (e.g., of copper) and refractory metal collar  140  is very resistant to electromigration-induced voiding, since the adhesion at the interface is greatly enhanced compared to that between metal and dielectric-based barrier layer  132  materials. As a result, the local EM flux at liner-less interface  118  around via  110  is greatly reduced. Also, since refractory metal collar  140  is formed only around via  110 , but not directly under via  110  and metal wire  112  contact, the via contact resistance is not impacted by this feature. Refractory metal collar  140  around via  110  also serves as a redundant conducting path, even if a void forms underneath via  110 , thus preventing structure  100  from being electrically open. 
     Structure  100  also decreases thermal cycle failure. Thermal cycle testing is a required reliability test reflecting the temperature excursion experienced by the product. Due to mismatch in thermal expansion between metal and its surrounding dielectric(s), fatigue or cracks may occur at the via and metal wire interface, causing an electrical open. Refractory metal collar  140  (mechanically much stronger than copper) serves as an anchor to keep via  110  from pulling out of metal wire  110  under stress. 
     Turning to  FIGS. 3-7 , embodiments of a method of forming structure  100  ( FIG. 2 ) will now be described. It is understood that a variety of methods may be employed and that the following is one example. In  FIG. 3 , metal wire  112  is provided in dielectric layer  124  using any now known or later developed techniques. For example, depositing dielectric layer  124  on a substrate (not shown), photolithography include patterning a mask (not shown), etching the mask, etching an opening, depositing liner  126 , depositing a metal (wire  112 ), and chemical mechanical polishing (CMP). As noted above, liner  126  separates metal wire  112  from dielectric layer  124  along only a bottom  128  and sides  130  of metal wire  112 . 
       FIG. 3  also shows forming dielectric layer  120  over metal wire  112  (and dielectric layer  124 ) to form liner-less interface  118  between metal wire  112  and dielectric layer  124 . As noted above, dielectric layer  120  may include a dielectric barrier layer  132  (e.g., of silicon nitride) forming liner-less interface  118  with metal wire  112 , and interlevel dielectric  134  (e.g., SiCOH) above dielectric barrier layer  132 .  FIG. 3  also shows forming an opening  160  through dielectric layer  134  and dielectric barrier layer  132  to metal wire  112 . Although opening  160  is shown as having been formed using a dual damascene process, it is understood that a via opening alone (single damascene process) may be used. Opening  160  may also extend into metal wire  112 , if desired. 
       FIG. 4  shows an optional process of a gaseous sputtering process to extend opening  160  into metal wire  112 . The gas used in the sputtering process may comprise one of argon (Ar), helium (He), neon (Ne), xenon (Xe), nitrogen (N 2 ), hydrogen (H 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ) or mixtures thereof, and preferably comprises Ar. A substantially frusto-conical opening  162  results within metal wire  112 . 
       FIG. 5  shows creating an undercut  164  from opening  160  under dielectric layer  120 , i.e., under dielectric barrier layer  132 . In one embodiment, the undercutting may include performing an isotropic wet/dry etching. 
       FIG. 6  shows forming refractory metal collar  140  in undercut  164  ( FIG. 5 ), e.g., by atomic layer deposition (ALD) and/or chemical vapor deposition (CVD). As noted above, the refractory metal may include titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), rhodium (Rh) and/or platinum (Pt), etc., or mixtures of thereof.  FIG. 6  also shows forming first liner  144  within opening  160  prior to filling opening  160  with a metal ( FIG. 2 ). In this case, first liner  144  may include refractory metal used for refractory metal collar  130 . 
       FIG. 7  shows forming second liner  146  within opening  160  prior to filling opening  160  with a metal. As noted above, second liner  146  may include at least one metal diffusion barrier  150  (i.e., liner) and metal seed layer  152 . As noted above, metal diffusion barrier(s)  150  may include, for example: tantalum/tantalum nitride, titanium/titanium nitride, tungsten/tungsten nitride, ruthenium/ruthenium nitride, etc. As also noted above, where metal  158  ( FIG. 2 ) is copper, metal seed layer  152  may include, for example: copper, copper aluminum, and other copper alloy such as copper iridium, copper nickel, and/or copper ruthenium. 
     Returning to  FIG. 2 , filling opening  160  ( FIG. 7 ) with a metal  158 , e.g., metal such as copper, to form via  110 , along with any necessary planarization finishes structure  100 . It is understood that the teachings of the disclosure may be repeated numerous times within a level of an IC chip and numerous times for different levels of the IC chip. 
     The structures and methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the disclosure as defined by the accompanying claims.