Abstract:
A semiconductor memory device and a column decoder thereof, in which data is masked using column select line signals obtained by the combination of masking signals and a column address to control the column select line signals and reduce the number of data input/output lines and the number of data input/output drivers. The semiconductor memory device includes: a plurality of memory cell arrays including a plurality of memory cells connected between word lines and bit lines; a plurality of switches each having one end connected to that of an adjacent a first memory cell array, and the other end connected to the bit line of a second memory cell array, which turn on in response to column select line signals, with the column select line signals obtained by combination of masking signals, such that data is not written to a column address and the bit line corresponding to the column address; one or more data input/output drivers for bidirectionally driving the data; and data input/output lines for connecting the output of each of the data input/output drivers to the bit lines.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that masks data by controlling a column select line signal in order to deactivate a specific column select line signal when one or more columns are selected, and to a column decoder. 
     2. Description of the Related Art 
     A semiconductor memory performs a writing operation for storing data input from an outside source and a reading operation for retrieving data stored in the memory cell. When performing writing and reading operations, not all the data are written and read. For example, if there is no need to change the data of a specific memory cell at a specific timing, such a cell is masked out during the writing operation to prevent data from being written over. 
     In a conventional semiconductor memory device, when k columns are selected out of n columns and m masking signals of k masking signals M 0  ˜M k-1  are activated, m data input/output drivers of k data input/output data drivers I/O DRV 0  ˜I/O DRV k-1  are disabled, so data is simultaneously written to only (k-m) memory cells. 
     However, in the conventional semiconductor memory devices it is difficult to control the period during which the m data input/output drivers of k data input/output data drivers I/O DRV 0  ˜I/O DRV k-1  are disabled, and it is difficult to control the timing when the data input/output lines connected to the disabled m data input/output drivers are precharged or equalized to a predetermined voltage level. Also, the conventional semiconductor memory device requires k data input/output lines and k data input/output drivers, which increases the chip size. 
     SUMMARY OF THE INVENTION 
     To solve the above identified problems, it is an objective of the present invention to provide a semiconductor memory device that masks data by controlling a column select line signal, in which the device cannot write specific data to specific memory cells by column select line signals obtained by the combination of column addresses and masking signals. 
     It is another objective of the present invention to provide a column decoder of the semiconductor memory device. 
     Accordingly, to achieve the above first objective, there is provided a semiconductor memory device that masks data by controlling column select line signals, comprising a plurality of memory cell arrays including a plurality of memory cells connected between word lines and bit lines, a plurality of switches each connected to the bit line of a first memory cell array at one end and to the bit line of an adjacent second memory cell array at the other end, wherein said switches operate in response to the column select line signals obtained by the combination of masking signals and column addresses such that data is not written to the bit line corresponding to the column address, one or more data input/output drivers for bidirectionally driving the data, and data input/output lines for connecting the output of each of the data input/output drivers to the bit lines. 
     Preferably, if the maximum number of column select line signals to be active simultaneously is k, the number of input/output drivers is equal to or less than k. Here, if a data write command for activating m of the masking signals is given, (k-m) of the column select line signals become active, so that (k-m) switches are turned on, and data in one or more data input/output drivers are simultaneously written to (k-m) memory cells. 
     To achieve the second objective, there is provided a column decoder of a semiconductor memory device, comprising, (1) k pre-decoders that receives a selection signal for selecting one, or less than k, column select line signals to be simultaneously active; (2) masking signals and lower bits of a column address for decoding; (3) the simultaneous enablement of one, or less than k, pre-decoders; (4) a main decoder for receiving the output signals from the pre-decoders and upper bits of the column address for decoding and outputting a plurality of column select line signals, wherein if the selection signal is in a logic state such that k column select line signals become simultaneously active and m of k masking signals become active, (k-m) of the column select line signals become simultaneously active. 
     Preferably, if the selection signal activates one of the column select line signals and k masking signals become inactive, one of the pre-decoders is enabled to output an active signal. 
     The pre-decoders are enabled by an enable clock signal. 
     Each pre-decoder of the present invention comprises a first logic unit that buffers the masking signals regardless of the lower bits of the column address, a second logic unit that detects the lower bits of the column address, and a third logic unit that selects between signal outputs from the first logic unit and the second logic unit, wherein the main decoder is enabled when a signal output from the third logic unit becomes active. 
     According to the present invention, the timing for masking data from a specific memory cell is precisely controlled and the number of data input/output lines and drivers is decreased, thereby reducing chip size. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objectives and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: 
     FIG. 1 schematically shows a semiconductor memory device for masking data by controlling a column select line signal according to the present invention; 
     FIG. 2 shows a column decoder for generating a column select line signal of FIG. 1; 
     FIG. 3 is a diagram showing 8 pre-decoders formed when the lower bits (CAi) of a column address of the column decoder shown in FIG. 2 are 3 bits, CA 0 , CA 1  and CA 2  ; 
     FIGS. 4A and 4B show pre-decoders of FIG. 3; and 
     FIG. 5 shows a circuit for generating first and second control signals PBWD and PBWB of FIGS. 4A and 4B. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. 
     Referring to FIG. 1, a semiconductor memory device 2 includes a first and a second memory cell arrays A 1  and A 2 , a plurality of switches S 0  through S n-1 , first and second data input/output lines I/O line 1  and I/O line 2 , and first and second data input/output drivers I/O DRV 1  and I/O DRV 2 . 
     The first and second memory cell arrays A 1  and A 2  include a plurality of word lines WL, a plurality of bit lines BL 10  through BL 1n-1  and BL 20  through BL 2n-1 , and a plurality of memory cells which are connected to one of word lines WL and each of the bit lines BL 10  through BL 1n-1  and BL 20  through BL 2n-1 . 
     Switches S 0  through S n-1  formed of NMOS transistors N 0  through N n-1 , each receives one of column select line signals CSL 0  through CSL n-1  to select one of the bit lines BL 10  through BL 1n-1  and BL 20  through BL 2n-1  formed in the first and second memory cell arrays A 1  and A 2 . 
     The column select line signals CSL 0  through CSL n-1  are output signals from the column decoder shown in FIG. 2 and connect the bit lines to the data input/output lines I/O line1 and I/O line2, and combine the masking signals that prevent data from being written to the bit lines with a corresponding column address (CA). 
     Each of the NMOS transistors N 0  through N n-1  has a gate respectively receiving the column select line signal CSL 0  through CSL n-1 , a source connected to the respective bit line BL 10  through BL 1n-1  of the first memory cell array A 1 , and a drain connected to the respective bit line BL 20  through BL 2n-1  of the adjacent second memory cell array A 2 . In other words, each of the NMOS transistors N 0  through N n-1  is turned on when the corresponding column select line signal CSL 0  through CSL n-1  is activated. 
     Bit line sense amplifiers (not shown) are formed between each of the bit lines BL 10  through BL 1n-1  and BL 20  through BL 2n-1  and the NMOS transistors N 0  through N n-1 , to sense the data loaded on the bit lines BL 10  through BL 1n-1  and BL 20  through BL 2n-1  and amplify the sensed data. 
     The input/output drivers I/O DRV 1  and I/O DRV 2  drive data and operate bidirectionally, and the input/output lines I/O line 1  and I/O line 2  connect the bit lines to input/output drivers I/O DRV 1  and I/O DRV 2  through the switches. Thus, in a read mode, the data loaded on the bit lines connected to the turned-on switches are transferred to the input/output drivers I/O DRV 1  and I/O DRV 2 . Also, in a write mode, the data from the input/output drivers I/O DRV 1  and I/O DRV 2  are transferred to the bit lines. 
     When one of the word lines WL in the first memory cell array A 1  is activated, a simultaneous writing operation of data to k memory cells in the first memory cell array A 1  will be described. 
     First, when k column select line signals, e.g., 0th through (k-1)th column select line signals CSL 0  through CSL k-1  are activated to high, the 0th through (k-1)th NMOS transistors N 0  through N k-1  are turned on, so that the input data of input/output drivers I/O DRV 1  and I/O DRV 2  are alternately loaded onto the 0th through (k-1)th bit lines BL 10  through BL 1k-1  via input/output lines I/O line 1  and I/O line 2 , and are stored in k cells of the first memory cell array A 1 . 
     In other words, the input data of the first data input/output drive I/O DRV 1  is simultaneously loaded on even-numbered bit lines BL 10 , BL 12 , . . . , BL 1k-2  of the first memory cell array A 1  via the first data input/output line I/O line 1 , and the input data of the second data input/output driver I/O DRV 2  is simultaneously loaded on odd-numbered bit lines BL 11 , BL 13 , . . . , BL 1k-1  of the first memory cell array A 1  via the second data input/output line I/O line 2 . 
     The data is loaded onto only the 0th through (k-1)th bit lines BL 10  through BL 1k-1  of the first memory cell array A 1 , not the 0th through (k-1)th bit lines BL 20  through BL 2k-1  of the second memory cell array A 2  because the sense amplifiers connected to the 0th through (k-1)th bit lines BL 20  through BL 2k-1  are disabled while the sense amplifiers connected to the bit lines BL 10  through BL 1k-1  of the first memory cell array A 1  are enabled. 
     However, if m of the k masking signals included in the 0th through (k-1)th column select line signals CSL 0  through CSL k-1  become active, only (k-m) column select line signals of the 0th through (k-1)th column select line signals CSL 0  through CSL k-1  become active. Thus, m of the 0th through (k-1)th NMOS transistors N 0  through N k-1  are turned off and only (k-m) NMOS transistors are turned on, so that the data input/output drivers I/O DRV, and I/O DRV 2  are simultaneously loaded on (k-m) bit lines of BL 10  through BL 1k-1 , and, and then simultaneously stored in (k-m) cells of the first memory cell array A 1 . 
     This embodiment of the present invention, has two data input/output lines and data input/output drivers respectively. However, the numbers of data input/output lines and drivers may be any numbers equal to or smaller than the maximum number k of column select line signals which become active simultaneously. Also, this embodiment masks data by controlling a column select line signal while writing data. However, the data may also be masked by controlling a data output buffer while reading data. 
     Thus, a semiconductor memory device according to the present invention combines the masking signal with the column select line signal, and enables the switches S 0  through S n-1  using the column select line signal combined with the masking signal, which reduces the number of data input/output lines and data input/output drivers less than the maximum number k of column select line signals that are activated simultaneously, thereby decreasing the chip size. 
     Referring to FIG. 2, a column decoder 31 receives k masking signals M 0  through M k-1 , lower bits (CA i ) of the column addresses, and a selection signal PBW to generate one or more column select lines CSL 0  through CSL n-1 . The column decoder 31 includes k pre-decoders 40, 41, 42, . . . , and a main decoder 61. 
     The selection signal PBW activates one of the column select line signals CSL 0  through CSL n-1  or simultaneously activates k column select line signals. 
     The pre-decoders 40, 41, . . . are enabled by an enable clock signal PCLKD (see FIG. 3). Each decoder receives one of masking signals M 0  through M k-1 , the lower bits of the column address and a selection signal PBW. One, or less than k, pre-decoders are simultaneously enabled according to the combination of the selection signal PBW and the masking signals M 0  through M k-1 . 
     When the numbers of lower bits (CA i ) and upper bits of the column address are equal to i and j respectively, the number (k) of pre-decoders 40, 41, . . . or masking signals M 0  through M k-1  is 2 i , and the number (n) of column select line signals CSL 0  through CSL n-1  is equal to 2 i+j . For example, if the number of lower bits (CA i ) of the column address is 3, the number (k) of the pre-decoders 40, 41, . . . , or masking signals is 8 (=2 3 ). 
     The main decoder 61 receives the upper bits (CA j ) of the column address and the activated signals among signals Z 0 , Z 1 , . . . , Z k-1 , which are outputs from the pre-decoders 40, 41, . . . , to generate k or less than n (=2 i+j )) column select line signals CSL 0  through CSL n-1 . 
     Referring to FIG. 3, 8 pre-decoders 40, 41, . . . , 47 are enabled by an enable clock signal PCLKD. 
     If the selection signal PBW is in a logic state that activities only one of the column select line signals CSL 0  through CSL n-1 , and all of the masking signals M 0  through M 7  are inactive, only one of the pre-decoders 40, 41, . . . , 47 is enabled to activate one of the signals Z 0 , Z 1 , . . . , Z 7  respectively from the pre-decoders 40, 41, . . . , 47. For example, if the three lower bits CA 2  CA 1  CA 0  are input as 000, it enables only the pre-decoder 40 and only the output signal Z 0  of the pre-decoder 40. If CA 2  CA 1  CA 0  are input as 111, it only activates the output signal Z 7  of pre-decoder 47. 
     If the selection signal PBW is in a logic state that simultaneously activates 8 of the column select line signals among CSL 0  through CSL n-1 , and all of the 8 masking signals of M 0  through M 7  are inactive, all the pre-decoders 40, 41, . . . , 47 are enabled to activate the output signals Z 0 , Z 1 , . . . , Z k-1  of the pre-decoders 40, 41, . . . , 47. However, even though the selection signal PBW is in a logic state that simultaneously activates 8 of the column select line signals among CSL 0  through CSL n-1 , only (k-m) units of the pre-decoders 40, 41, . . . , 47 are enabled if m of the 8 masking signals M 0  through M 7  are active. As a result, only (k-m) output signals of Z 0 , Z 1 , . . . , Z k-1  from the pre-decoders 40, 41, . . . , 47 are activated. 
     FIG. 4A shows the pre-decoder 40 and FIG. 4B shows the pre-decoder 47. 
     The pre-decoder 40 includes a first logic unit 91 that buffers the 0th masking signal M 0  regardless of the column address, a second logic unit 92 that combines the first, second and third column address bits CA 0 , CA 1  and CA 2 , and a third logic unit 93 for selecting one of the signals from the first logic unit 91 and the second logic unit 92. 
     If the main decoder 61 (see FIG. 2) connected to the outputs of the pre-decoders 40 through 47 is a low enable circuit, the low signals of Z 0  through Z 7  from the pre-decoders 40 through 47 enable the main decoder 61. The first logic unit 91 includes an inverter 71 that inverts the 0th masking signal M 0  and a first NAND gate 72 that receives the signal output from the inverter 71 and a first control signal PBWD. The second logic unit 92 includes a second NAND gate 73 that receives column address bits CA 0 , CA 1  and CA 2  as all inverted and a third NAND gate 74 that receives the signal from the second NAND gate 73 and a second control signal PBWB. Also, the third logic unit 93 includes a fourth NAND gate 75 that receives the signals from the first and third NAND gates 72 and 74, and the enable clock signal PCLKD, and inverters 76 and 77 for buffering the signal output from the fourth NAND gate 75. 
     The pre-decoder 47 is the same as the pre-decoder 40, except that a second NAND gate 83 receives column address bits CA 0 , CA 1  and CA 2  without inversion. Thus, the second NAND gate 73 of the pre-decoder 40 outputs a logic low signal only when the first, second and third bit CA 0 , CA 1  and CA 2  of the column address are all 0, while the second NAND gate 83 of the column decoder 47 outputs a logic low signal when CA 0 , CA 1  and CA 2  are all 1. 
     Also, other pre-decoders 41 through 46 (see FIG. 3) are the same as the pre-decoders 40 and 47, except that each second NAND gate of the pre-decoders 41 through 46 receives one or more of the inversions of the first, second and third bit, CA 0 , CA 1  and CA 2  of column addresses. 
     Referring to FIG. 5, the selection signal PBW is inverted by an inverter 97 to give the second control signal PBWB, and the second control signal PBWB is inverted by an inverter 98 to give the first control signal PBWD. 
     Referring to FIGS. 4A, 4B and 5, the operation of the pre-decoders will be described. 
     When the selection signal PBW is logic high, the second control signal PBWB becomes logic low, so the third NAND gates 74 and 84 output a logic high signal all the time regardless of the column address bits CA 0 , CA 1  and CA 2 . Thus, the signals Z 0  and Z 7  output from the pre-decoders 40 and 47 are the inversions of the masking signals M 0  and M 7 . For example, if the 0th masking signal M 0  is a logic low and the 7th masking signal M 7  is a logic high while the selection signal PBW is logic high, the output signal Z 0  of the pre-decoder 40 is inactive to logic high and the pre-decoder 47 is active to logic low. 
     Also, when the selection signal PBW is logic low, the first control signal PBWD is logic low, so the second NAND gates 72 and 82 output a logic high signal regardless of the masking signals M 0  and M 7 . Thus, the signals Z 0  and Z 7  from the pre-decoders 40 and 47 have the same logic state as the signals output from the second NAND gates 73 and 83, respectively. For example, when the selection signal PBW is a logic low and the column address bits CA 0 , CA 1  and CA 2  are 111, the second NAND gate 73 of the pre-decoder 40 outputs a logic high signal, and the second NAND gate 83 of the per-decoder 47 outputs a logic low signal, so that the output signal Z 0  of the pre-decoder 40 becomes inactive to logic high, and the output signal Z 7  of the pre-decoder 47 becomes active to logic low. 
     Here, if the upper column address CA j  fed to the main decoder 61 (see FIG. 2) includes 5 bits of CA 3  through CA 7 , the main decoder 61 generates 256 (=2 8 ) column select line signals of CSL 0  through CSL n-1 . 
     In FIG. 2, if the selection signal PBW is logic high and m of the masking signals M 0  through M k-1 , become active to a logic low, only (k-m) of the signals Z 0 , Z 1 , . . . , Z 7  become active to logic low. As a result, the semiconductor memory device as shown in FIG. 1 having the column decoder as shown in FIG. 2 turns on (k-m) NMOS transistors of N 0  through N n-1  when a write command is given, to write data to the (k-m) memory cells. 
     Also, if the selection signal PBW is logic low, one of k pre-decoders 40, 41, . . . , corresponding to the lower bits of the column address, is activated to logic low. Therefore, only one of the n column select line signals CSL 0  through CSL n-1  output from the main decoder 61 becomes active. As a result, in the semiconductor memory device of FIG. 1, only one of the NMOS transistors N 0  through N n-1  is turned on when a data write command is given, to write data to only one memory cell. 
     While the present invention has been illustrated and described with reference to a specific embodiment, further modifications and alterations within the spirit and scope of this invention will occur to those skilled in the art.