Abstract:
A circuit and method for amplifying a differential input signal over a wide dynamic range using multiple signal gains such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the multiple signal gains.

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to differential amplifiers, including instrumentation amplifiers, and in particular, differential amplifiers requiring high signal gain and wide input signal range. 
   2. Description of the Related Art 
   In many applications for differential amplifiers, particularly instrumentation amplifiers, it is often a design requirement to provide multiple gain settings, in one or more of which it is often necessary to provide maximum loop gain to guarantee adequate gain accuracy. One or more of the remaining gain settings may not require the loop gain to be as high, but it may be necessary to accommodate a much wider input signal range than might be available at the higher gain settings. These requirements are generally conflicting and are often resolved only by increasing the complexity of the circuitry. 
   For example, in an amplifier having two gain settings, e.g., 10 and 1,000, the maximum input signal range requirement for the higher gain setting may only be +/−5 millivolts. For the higher gain of 1,000, such a signal range will produce an output signal of +/−5 volts, which may be close to or at the maximum supply voltage VDD of the circuit. However, to maintain a gain accuracy of 0.1% at this higher gain setting, the overall loop gain of the system must be significantly higher, e.g., 1,000,000. 
   For the lower gain of 10, maintaining a gain accuracy of 0.1% would only require a loop gain of 10,000. However, with the input signal range of +/−5 millivolts, the output signal range will only be ±50 millivolts, which is a small portion of the available output signal range. In that case, a wider input signal range, e.g., +/−500 millivolts, may be more desirable. However, such a higher input signal range would be problematic for the higher gain. 
   SUMMARY OF THE INVENTION 
   In accordance with the presently claimed invention, a circuit and method are provided for amplifying a differential input signal over a wide dynamic range using multiple signal gains such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the multiple signal gains. 
   In accordance with one embodiment of the presently claimed invention, a differential amplifier with multiple signal gains for amplifying a differential input signal over a wide dynamic range includes: 
   differential input electrodes to convey a differential input signal; 
   differential output electrodes to convey a differential output signal; 
   first differential amplifier circuitry having a first signal gain and coupled between the differential input and output electrodes to receive at least a first portion of the differential input signal and provide a first portion of the differential output signal; and 
   second differential amplifier circuitry having a second signal gain lower than the first signal gain and coupled between the differential input and output electrodes to receive at least a second portion of the differential input signal and provide a second portion of the differential output signal; 
   wherein, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the first and second signal gains. 
   In accordance with another embodiment of the presently claimed invention, a differential amplifier with multiple signal gains for amplifying a differential input signal over a wide dynamic range includes: 
   first differential amplifier means having a first signal gain for receiving at least a first portion of a differential input signal and providing a first portion of a differential output signal; and 
   second differential amplifier means having a second signal gain lower than the first signal gain for receiving at least a second portion of the differential input signal and providing a second portion of the differential output signal; 
   wherein, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the first and second signal gains. 
   In accordance with still another embodiment of the presently claimed invention, a method for amplifying a differential input signal over a wide dynamic range using multiple signal gains includes: 
   receiving a differential input signal; 
   amplifying at least a first portion of the differential input signal with a first signal gain to provide a first portion of a differential output signal; 
   amplifying at least a second portion of the differential input signal with a second signal gain lower than the first signal gain to provide a second portion of the differential output signal; and 
   combining the first and second portions of the differential output signal to provide the differential output signal such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the first and second signal gains. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a differential amplifier in accordance with one embodiment of the presently claimed invention. 
       FIGS. 2A and 2B  illustrate transconductance curves for the circuit of  FIG. 1 . 
       FIG. 3  is a functional block diagram of a closed-looped system using differential amplifiers in accordance with another embodiment of the presently claimed invention. 
   

   DETAILED DESCRIPTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. 
   As discussed in more detail below, a differential amplifier in accordance with the presently claimed invention uses multiple signal gains to provide a high signal gain for small input differential signals, with a gradual transition to a lower signal gain for larger differential input signals. In accordance with a further embodiment, the signal gains are transconductance gains, with an input differential signal stage having low voltage tolerant metal oxide semiconductor (MOS) input transistors as are typically found in a complementary MOS (CMOS) or bipolar CMOS (BiCMOS) process in a high voltage design such that the input MOS devices are isolated from otherwise destructive higher voltages. Accordingly, such an amplifier in accordance with the presently claimed invention accommodates conflicting requirements of high gain and low signal range for high gain settings, and low gain and high signal range for low gain settings. Additionally, the input MOS field effect transistors (MOSFETs) are implemented in a bootstrapped configuration (further information about which can be found in U.S. Pat. No. 6,914,485, the disclosure of which is incorporated herein by reference). 
   Referring to  FIG. 1 , a differential amplifier  100  in accordance with one embodiment of the presently claimed invention can be implemented substantially as shown. Transistors MP 1  and MP 2  (p-type MOSFETs) receive the positive VINP and negative VINN phases, respectively of the differential input signal at their respective gate electrodes. These transistors MP 1 , MP 2  receive biasing currents I 1 , I 2  from current sources IS 1 , IS 2  and are bootstrapped by transistors QP 1  and QP 2  (PNP bipolar junction transistors) between the power supply terminals VDD, VSS, as shown. These transistors MP 1 , MP 2  provide a high impedance input for receiving the differential input voltage to provide a buffered differential input voltage via source follower action at the base electrodes of transistors QN 1 , QN 2 , QN 3  and QN 4  (NPN bipolar). 
   Transistors QN 1  and QN 2  along with resistors R 2  and R 3 , and current source IS 3  form a low gain differential amplifier circuit. Current source IS 3  provides tail current I 3  for biasing transistors QN 1  and QN 2 , which, in turn, produce the positive IQN 2  and negative IQN 1  portions of the positive IOUTP and negative IOUTN phases, respectively, of the differential output current. The resulting voltage V 3  across current source IS 3  and base currents IQP 1 , IQP 2  of the bootstrapped transistors QP 1 , QP 2  provide biasing for the bootstrapped transistors QP 1 , QP 2 . 
   Transistors QN 3  and QN 4  (NPN bipolars), along with resistors R 4  and R 5 , and current source IS 4  form a high gain differential amplifier circuit. Current source IS 4  provides tail current I 4  for the differential transistor pair QN 3 , QN 4 , which, in turn, provide additional positive IQN 4  and negative IQN 3  portions of the positive IOUTP and negative IOUTN phases, respectively, of the differential output current. 
   Referring to  FIG. 2A , the differing contributions of the low gain (e.g., low transconductance) differential amplifier pair QN 1 , QN 2 , and high gain (e.g., high transconductance) differential amplifier pair QN 3 , QN 4  are shown. As indicated, the output current components IQN 1 , IQN 2  for the low gain differential amplifier pair QN 1 , QN 2  display substantially linear characteristics over a wide range of input signal VIN amplitudes as they traverse between their minimum and maximum possible values based on the available power supply voltage VDD-VSS. Conversely, the output current components IQN 3 , IQN 4  for the high gain differential amplifier pair QN 3 , QN 4  display substantially linear characteristics over a more narrow range of input signal VIN values as they traverse between their minimum and maximum available values. 
   Referring to  FIG. 2B , the output current components IQN 1 , IQN 2 , IQN 3  and IQN 4  combine together at the output electrodes OUTP, OUTN to form the resultant positive IOUTP and negative IOUTN phases of the output signal current. In other words, positive output signal components IQN 2  and IQN 4  sum together to form the positive output signal component IOUTP, and negative output signal components IQN 1  and IQN 3  sum together to form the negative phase IOUTN of the output signal current. While these output current signal phases IOUTP, IOUTN do not display linear characteristics over as wide a range as those of their constituent component currents IQN 1 , IQN 2 , IQN 3 , IQN 4 , they are nonetheless monotonic over a broad range of input signal values as they traverse between their minimum and maximum signal values. However, as discussed in more detail below, such nonlinear characteristics can be compensated at a system level. 
   Hence, as should be recognized from the transconductance curves of  FIGS. 2A and 2B , a differential amplifier in accordance with the presently claimed invention provides two gain regions. A higher gain region provided by transistors QN 3  and QN 4  over a relatively narrow portion of the input signal VINP-VINN range transitions smoothly to a lower gain region provided by transistors QN 1  and QN 2  over a wider portion of the input signal VINP-VINN range. 
   Referring to  FIG. 3 , the circuitry  100  of  FIG. 1  can be incorporated in a closed loop system  300  to provide a linear output voltage VOUT as follows. The circuitry  100  of  FIG. 1  is replicated, with one such circuit  100   a  amplifying the differential input signal VIN as discussed above, while another such circuit  100   b  serves as a feedback amplifier to feed back a voltage divided portion of the output signal VOUT. Their respective positive IOUTPa, IOUTPb and negative IOUTNa, IOUTNb phases of the differential output signal current sum together to provide the currents IRP, IRN through the pullup resistors RP, RN. This produces a differential voltage VI at the input of an operational amplifier Al, the output voltage VOUT of which is divided down and summed it with a reference voltage VREF. This voltage dividing action is performed in a resistor array RA, RB in which the series resistor RA is selectively changed in value by shorting it at various points to the output electrode OUT supplying the output voltage VOUT. The gain of this voltage divider network is (RA+RB)/RB, with the resistance value RA being changed to achieve the desired loop gain. For example, for a loop gain of unity, resistor RA is shorted entirely by connecting electrode G=1 to the output electrode OUT, while the other gain electrodes G=10, G=100, are left open. Similarly, for a loop gain of 10, electrode G=10 is shorted to the output electrode OUT while the remaining gain control electrodes G=1, G=100 are left open. As a result, mutual cancellation of the inherent nonlinear performance characteristics of the amplifiers  100   a,    100   b  occurs. 
   Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.