Abstract:
A multilayered, low temperature co-fired ceramic (LTCC) substrate within which a radio frequency (RF) filter is formed. Portions of a bandpass filter are implemented using electrode patterns on different ceramic tape layers of which selected portions are mutually superimposed, thereby providing self-compensation for changes in mutual coupling (e.g., mutual inductance) caused by small errors in alignment of the ceramic tape layers occurring during manufacturing.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to radio frequency (RF) circuits implemented with multilayered low temperature co-fired ceramic (LTCC) substrates, and in particular, to RF filter circuits within LTCC substrates. 
     2. Description of the Related Art 
     As electronic circuitry has become increasingly sophisticated, many forms of device and circuit scaling have been used to reduce the size and space needed, as well as to provide durability. First, individual devices and other circuit components were mounted on printed circuit boards. As integrated circuits (ICs) became more developed, more devices and components became integrated, thereby allowing the printed circuit boards and other substrates to be further reduced in size. More recently, ICs have developed to the point where virtually entire systems are integrated within one die, or chip. However, one exception to this has been many forms of RF circuits due to the need for various capacitors and inductors which are difficult, if not impossible, to fully integrate within a chip. Accordingly, alternative techniques have been developed to miniaturize and provide durable circuits and subsystems. One technique has been the use of “hybrid” circuits in which ICs are mounted along with other forms of chip components, including chip resistors, inductors and capacitors, on some form of substrate (e.g., alumina ceramic) and then hermetically sealed for protection. Another technique which is seeing increased use is the use of multilayered LTCC substrates on which ICs and other chip components are mounted on the top surface, while passive components, such as inductors and capacitors, are formed among the underlying layers. 
     As is well known, a typical implementation of circuitry using an LTCC substrate includes multiple layers of a ceramic “tape” which are used to provide the base structure, i.e., substrate, within and upon which to form various electronic components and electrical connections. This tape is formed from a powdered ceramic material which is then mixed with a binder material. For example, one commonly used ceramic tape is that available from DuPont under the trade name “Green Tape 951”. Electronic components that can be formed within or among the various LTCC layers include resistors, capacitors and inductors. The electrical connections between each tape layer, similar to those connections formed within various layers within an integrated circuit, are known as “vias” and are formed by apertures lined or filled with a conductive material. 
     As is further well known, such components are formed by establishing (e.g., punching) holes in the tape as appropriate and layering metal, dielectric material and insulating material. Several layers of the tape are generally used to form the ultimate desired circuitry. These tape players are then pressed together and fired in an oven to remove the binder and sinter the ceramic powder. Components which are too large or difficult to include or form within or among the ceramic tape layers, e.g., IC chips, are typically surface-mounted on the top of the hardened substrate. The resulting substrate and components, often less than one inch square, provide a compact and durable packaged circuit. 
     Referring to  FIG. 1 , for example, integrated LTCC modules are frequently used in cellular wireless telephones. As discussed above, each of the multiple layers of ceramic material is printed with metallized circuit patterns that are electrically coupled layer-to-layer by conductive vias (small metallized holes which pass vertically through the ceramic material layers). The individual layers are then assembled, laminated under pressure and co-fired (fired as a unit) to create a monolithic structure. The external contacts may be plated with gold, nickel or tin to protect conductive metal and to facilitate interconnection at the next system level. The end result is a mechanically strong, hermetic, thermally conductive, chemically inert and dimensionally stable ceramic structure. 
     With respect to hermeticity, the internal conductors are protected by the surrounding dense ceramic material. Metal components, such as sealing rings, are brazed to the plated surface of the co-fired ceramic to provide protection of the surface-mounted IC dice. Having the electrical conductors buried within the ceramic structure reduces risks of short circuits due to environmental effects, such as moisture, dirt or other factors. 
     Circuit density is directly proportional to the number of layers. Increased density of the circuitry to be implemented may require the addition of layers to prevent undesirable electrical performance characteristics, such as crosstalk or other forms of electrical signal interference. Further, distributing circuitry on additional layers can help to avoid yield losses caused by very fine signal lines and spacings. 
     Some problems which can arise from such dense packaging, notwithstanding the use of additional layers, can be noise or signal-induced interference caused by close proximities of the various signal and power supply lines and changes in circuit performances due to the slight variations in alignment or registration between the various ceramic layers that can be expected within normal manufacturing tolerances. These issues, among others, are addressed by the presently claimed invention. 
     SUMMARY OF THE INVENTION 
     In accordance with the presently claimed invention, a multilayered, low temperature co-fired ceramic (LTCC) substrate is provided within which a radio frequency (RF) filter is formed. Portions of a bandpass filter are implemented using electrode patterns on different ceramic tape layers of which selected portions are mutually superimposed, thereby providing self-compensation for changes in mutual coupling (e.g., mutual inductance) caused by small errors in alignment of the ceramic tape layers occurring during manufacturing. 
     In accordance with one embodiment of the presently claimed invention, a radio frequency (RF) filter within a multilayered low temperature co-fired ceramic (LTCC) substrate includes multiple ceramic tape layers with respective electrode patterns, and a plurality of conductive vias. A first ceramic tape layer with a first electrode pattern forms a first RF ground plane. A second ceramic tape layer with a second electrode pattern forms a second RF ground plane. A third ceramic tape layer is positioned between the first and second ceramic tape layers with a third electrode pattern of which at least a first portion is generally geometrically serpentine and forms a portion of a first reactance including a first inductance. A fourth ceramic tape layer is positioned between the first and second ceramic tape layers with a fourth electrode pattern of which at least a first portion is generally geometrically serpentine and forms a portion of a second reactance including a second inductance. The plurality of conductive vias couple selected respective portions of the first, second, third and fourth electrode patterns. The third and fourth electrode patterns together form at least a portion of a RF bandpass filter circuit, corresponding sub-portions of the first portions of the third and fourth electrode patterns are mutually superimposed, and the first and second inductances together produce a mutual inductance which remains substantially constant substantially independently of selected variations in the mutual superimposition. 
     In accordance with another embodiment of the presently claimed invention, a radio frequency (RF) filter within a multilayered low temperature co-fired ceramic (LTCC) substrate includes multiple ceramic tape layers with respective electrode patterns, and a plurality of conductive vias. A first ceramic tape layer with a first electrode pattern forms a first RF ground plane. A second ceramic tape layer with a second electrode pattern forms a second RF ground plane. A third ceramic tape layer is positioned between the first and second ceramic tape layers with a third electrode pattern of which at least a first portion is generally geometrically serpentine with major and minor axes and forms a portion of a first reactance including a first inductance. A fourth ceramic tape layer is positioned between the first and second ceramic tape layers with a fourth electrode pattern of which at least a first portion is generally geometrically serpentine with major and minor axes and forms a portion of a second reactance including a second inductance. The plurality of conductive vias couple selected respective portions of the first, second, third and fourth electrode patterns. Selected respective portions of the first, second, third and fourth electrode patterns are mutually coupled by a plurality of conductive vias, and the third and fourth electrode patterns together form at least a portion of a RF bandpass filter circuit. The major axes of the third and fourth electrode patterns are approximately mutually parallel, and corresponding sub-portions of the first portions of the third and fourth electrode patterns are mutually superimposed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective, cross-sectional view of a conventional RF circuit module with an LTCC substrate. 
         FIGS. 2A ,  2 B,  2 C and  2 D together are a circuit schematic diagram of an RF module with an LTCC substrate in accordance with one embodiment of the presently claimed invention. 
         FIG. 3  is a circuit schematic diagram of a multiple pole bandpass filter used in the circuit of  FIGS. 2A ,  2 B,  2 C and  2 D. 
         FIGS. 4A-4H  illustrate the eight conductive electrode patterns of the seven layers of an LTCC substrate used to implement the circuit of  FIGS. 2A-2D . 
         FIG. 5  depicts mutually superimposed rectangular capacitor plates used for the shunt filter capacitors in the LTCC structure of  FIGS. 4A-4H . 
         FIG. 6  depicts the partially mutually superimposed conductors used to implement two of the shunt inductances in the filter circuit in the LTCC structure of  FIGS. 4A-4H . 
         FIG. 7  is a circuit schematic diagram of a series resonant circuit formed by the buried capacitors and associated conductive vias used in the RF module as depicted in FIGS.  4 A- 4 H. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
     Referring to  FIGS. 2A-2D  together, an RF circuit module with an LTCC substrate in accordance with one embodiment of the presently claimed invention includes two surface-mounted IC chips, IC 1 , IC 2  and a number of various surface-mounted or buried passive support components, i.e., resistors, capacitors and inductors, interconnected substantially as shown, and interfaced with external circuitry by way of an array IO 1  of input/output connections. The specific functions and operations performed by the integrated circuits IC 1 , IC 2  will not be described as they are not material to the subject invention. Selected ones of the outlying passive components which are material to the subject invention are discussed in more detail below. 
     Referring to  FIG. 2A , the incoming and outgoing RF signal is conveyed via signal line RFINOUT and passes through a multiple pole bandpass filter F 1  and an RF switch SW 1 . The incoming RF signal passes through the switch SW 1  and is provided to the RF input port of the integrated circuit IC 1  via a coupling capacitor C 5 . The outgoing RF signal is provided by the integrated circuit IC 1  as a balanced signal which passes through a balanced-unbalanced transformer (“balun”) B 1  for conveyance to the output through the switch SW 1  and filter F 1 . 
     In accordance with well known distributed-circuit RF switch techniques, the RF switch SW 1  uses diodes D 1 , D 2  and a quarter-wavelength transmission line LINE_ 1  to provide the appropriate input and output signal paths. 
     Bypass capacitors C 101 , C 102 , C 103 , C 105 , C 106 , C 107  and C 108  provide decoupling for their respective power supply connections, while bypass capacitor C 104  provides decoupling for the DC signal used to control the RF switch SW 1 . 
     Referring to  FIG. 3 , filter F 1  is designed according to conventional bandpass filter design techniques, and includes serially coupled capacitors C 3 , C 4 , C 5 , C 6 , shunt inductors L 1 , L 2 , L 3 , and shunt capacitors C 1 , C 1   t , C 2 , C 2   t , C 7 , C 7   t , all interconnected substantially as shown. Capacitors C 1   t , C 2   t  and C 7   t  are tunable capacitors which are tuned, or trimmed, during manufacture of the RF module. As discussed in more detail below, shunt inductors L 1  and L 3  are in such mutual proximity as to form a mutual inductance M 13  which, in accordance with conventional filter theory and design, is a factor in establishing the frequency filtering characteristics of the filter F 1 , providing additional rejection at frequencies just below the passband due to an additional left side “zero” in the transfer function of the filter F 1 . 
     As will be discussed in more detail below, these capacitors and inductors forming the filter F 1  are themselves formed using various electrode patterns on multiple layers of the underlying LTCC substrate. For example, portions of series capacitors C 3  and C 6  are on layers  3  and  4 , while portions of series capacitors C 4  and C 5  are on layers  2 ,  3  and  4 . Portions of shunt capacitors C 1 , C 2  and C 7  are on layers  1  and  2 . Tunable capacitors C 1   t , C 2   t  and C 7   t  use layers  6  and  7 . Shunt inductors L 1  and L 3  use layers  3  and  4 , respectively, while shunt inductor L 2  uses layers  3  and  4 . 
     Referring to  FIGS. 4A-4H , the seven layers of ceramic material forming the LTCC substrate for the circuit of  FIGS. 2A-2D  use various electrode patterns to form the bandpass filter F 1 , balun B 1  and bypass capacitors C 101 -C 108 . As indicated in  FIGS. 4A-4H , the eight electrode patterns are identified as conductor  7 ,  6 ,  5 ,  4 ,  3 ,  2 ,  1  and  0 , respectively. Accordingly,  FIGS. 4A ,  4 B,  4 C,  4 D,  4 E,  4 F,  4 G and  4 H correspond to electrode patterns  7 ,  6 ,  5 ,  4 ,  3 ,  2 ,  1  and  0 , respectively, with electrode patterns  1  and  0  being on the top and bottom, respectively, of the first layer of ceramic material. 
     Referring to  FIG. 4A , electrode pattern  7  includes conductor area  200   r  which forms an RF ground region. Conductor C 1   ta  forms a series of upper plates for tunable capacitor C 1   t , separated by conductor bridges  11  which can be trimmed by a laser so as to provide the appropriate upper plate area to achieve the desired capacitance for capacitor C 1   t . Similarly, conductor regions C 2   ta  and C 7   ta  provide the upper capacitor plate regions for tunable capacitors C 2   t  and C 7   t , with conductive bridges  12 ,  17  for laser trimming. These capacitor plate regions C 1   ta , C 2   ta , C 7   ta  are connected by respective conductive vias, 1 v, 2 v, 7 v to conductors on layers below so as to place these tunable capacitors C 1   t , C 2   t , C 7   t  in parallel with their respective shunt capacitors C 1 , C 2 , C 7  (FIG.  3 ). 
     Referring to  FIG. 4B , conductor region  300  of electrode pattern  6  provides the lower capacitor plate regions C 1   tb , C 2   tb , C 7   tb  for the tunable capacitors C 1   t , C 2   t , C 7   t . The remaining conductive traces or lines of electrode pattern  6  primarily provide for various power supply and signal connections. 
     Referring to  FIG. 4C , conductor region  201   r  of electrode pattern  5  provides an RF ground region which also serves as a grounded plate for shunt filter capacitors C 1 , C 2  and C 7 . Conductor regions  201   s  provide RF shielding for signals passing through the conductive vias within the bounded interior. 
     Referring to  FIG. 4D , electrode pattern  4  includes conductive traces forming the quarter wavelength (i.e., based upon the wavelength of the nominal (e.g., center) frequency of the bandpass filter F 1 ) transmission line LINE_ 1  separating the diodes D 1 , D 2  in the RF switch SW 1  (FIG.  2 A), and portions B 1   aa , B 1   ab  of the balun B 1 . Additionally, several portions of the bandpass filter components C 3 , C 4 , C 5 , C 6 , L 2 , L 3  are provided, including lump-circuit capacitor plates C 3   a , C 4   a , C 5   a  and C 6   a  for capacitors C 3 , C 4 , C 5  and C 6 , respectively, plus a conductor trace L 2   a  forming a lumped-circuit portion of inductor L 2 . Further, a conductive trace L 3  is provided forming a lumped-circuit implementation of shunt inductor L 3 . 
     Referring to  FIG. 4E , conductor region  202   d  of electrode pattern  3  provides a digital ground region, plus lower capacitor plates C 101   b , C 102   b  for bypass capacitors C 101  and C 102  (discussed in more detail below). Additional conductive traces C 103   b  and C 104   b  provide lower capacitor plates for bypass capacitors C 103  and C 104  (discussed in more detail below). Another conductor region  301  provides lower capacitor plate regions C 105   b , C 106   b , C 107   b  and C 108   b  for bypass capacitors C 105 , C 106 , C 107  and C 108  (discussed in more detail below). Another conductive trace B 1   b  provides the remainder of the balun B 1  with electromagnetic coupling occurring with the conductor regions B 1   aa , B 1   ab  on electrode pattern  4  through the dielectric formed by the ceramic tape layer  4 . 
     Still further conductive regions provide additional capacitor plate regions C 3   b , C 4   b , C 5   b  and C 6   b  for filter capacitors C 3 , C 4 , C 5  and C 6 , respectively. Another conductive trace L 2   b  provides another portion of the shunt inductor L 2  of the filter F 1 , while another conductive trace L 1  forms a lumped-circuit implementation of shunt inductor L 1  for the filter F 1  (FIG.  3 ). 
     It will be understood by one of ordinary skill in the art that inductors L 3  and L 1  are implemented on electrode patterns  4  and  3  ( FIGS. 4D and 4E ) in accordance with well known RF circuit design techniques for transmission lines with the appropriate characteristic impedance at the nominal frequency of the signal(s) of interest. With reference to the circuit schematic of  FIG. 3 , inductors L 3  and L 1  are connected between capacitor plates of series capacitors C 6  and C 3 , respectively, and RF circuit ground potential. The connections to the RF circuit ground regions are provided by conductive vias 203 v and 201 v, respectively, to an RF ground region  203   r  on electrode pattern  1 . As will also be understood, by grounding one end of these conductive traces L 3 , L 1 , and making the physical line lengths of these traces L 3 , L 1  the appropriate fraction of the wavelength of the nominal frequency of the signal of interest, a net shunt inductance appears at capacitor plates C 6   a  and C 3   b.    
     Referring to  FIG. 4F , electrode pattern  2  includes numerous conductive vias, plus three capacitor plates, or electrodes, C 2   a , C 5   c /C 1   a , C 4   c /C 7   a . Capacitor plate C 2   a  is for the remaining shunt filter capacitor C 2  of the filter F 1 . Capacitor plate C 5   c /C 1   a  is a shared capacitor plate for serial coupling capacitor C 5  and shunt capacitor C 1 . By virtue of ceramic tape layer  3  between electrode patterns  2  and  3 , this plate C 5   c /C 1   a  forms part of the capacitance of serial capacitor C 5 . Additionally, this plate C 1   c /C 1   a  forms one of two capacitor plates for shunt capacitor C 1 . Similarly, capacitor plate C 4   c /C 7   a  is a shared capacitor plate for serial coupling capacitor C 4  and shunt capacitor C 7  of the filter F 1 . 
     Referring to  FIG. 4G , conductor region  203   r  of electrode pattern  1  provides an RF ground region, which includes capacitor plate regions C 1   b , C 2   b  and C 7   b  for shunt capacitors C 1 , C 2  and C 7 , respectively, of the filter F 1 . 
     Referring to  FIG. 4H , the input/output (I/O) interface for the RF circuit module is achieved in a conventional manner using a ball grid array (BGA) interface in which conductive balls  400  on the reverse side (e.g., bottom) of the layer  1  ceramic material are connected by conductive vias 400 v to the circuitry within the RF module and are surrounded by a glass insulating material  401 . One of the interior conductors  400 s provides the signal path for the incoming and outgoing RF signal RFINOUT. The space  402  separating this conductor  400   s  from the outside edge of layer  1  is open, i.e., contains no conductive interconnect, so as to provide a clear path to the signal conductor  400   s  when mounting the RF module on a circuit board. 
     Referring back to  FIGS. 4D  (electrode pattern  4 ),  4 E (electrode pattern  3 ),  4 F (electrode pattern  2 ) and  4 G (electrode pattern  1 ), a number of characteristics and features of the implementation of the bandpass filter circuit F 1  will be noted. The two capacitor plates C 3   a , C 3   b  of capacitor C 3  differ in their respective widths and lengths, i.e., along the X and Y axes, as do the capacitor plates C 6   a , C 6   b  of capacitor C 6 . Accordingly, for normal variations in alignment, or registration, between electrode patterns  4  and  3  during the manufacturing process, the upper capacitor plates C 3   a , C 6   a  may shift along the X or Y axes, or both. Accordingly, as a result, while some portion of the upper capacitor plate C 3   a , C 6   a  may shift away from its normal opposition to its counterpart lower capacitor plate C 3   b , C 6   b , such a reduction in capacitor area is added at the other side, thereby resulting in self-compensation for such alignment errors. Similar self-compensation occurs with respect to capacitor C 2  in the event that the upper capacitor plate C 2   a  (electrode pattern  2 ) experiences a nominal amount of shifting in the X or Y direction relative to the lower capacitor plate C 2   b  (electrode pattern  1 ) formed by the RF ground region  203   r.    
     Referring to  FIG. 5 , using capacitor C 6  as an example, it can be seen that with the use of rectangular capacitor plates C 6   a , C 6   b  which are mutually superimposed as depicted in  FIGS. 4D and 4E , normal variations in alignment along the X or Y directions will be self-compensating in that the width and length dimensions of the superimposed regions of the capacitor plates C 6   a , C 6   b  will remain substantially constant. Accordingly, the resulting capacitor plate area will remain substantially constant; therefore the capacitance will remain substantially constant. 
     With respect to shunt filter inductors L 1  and L 3 , it can be seen that the approximately central regions  213 ,  211  of the traces L 3 , L 1  ( FIGS. 4D and 4E ) are substantially mutually superimposed, with the remaining geometrically serpentine portions of the conductors L 3 , L 1  extending in generally diametrically opposing directions. This inverse symmetry advantageously provides self-compensation for the mutual inductance M 13  formed by these inductors L 1 , L 3  for normal variations in alignment of layers  4  and  3  during the manufacturing process. During any such variations, the major axes (along the Y direction) and minor axes (along the X direction) will remain generally parallel. However, the mutual superimposition of the central regions  213 ,  211  of the these conductors L 3 , L 1  will change slightly. However, while such shifting of this mutual superimposition may affect the mutual inductance M 13  due to these superimposed central regions  213 ,  211 , mutual inductance due to the remaining outwardly extending portions of these conductors, L 3 , L 1  will compensate, thereby maintaining a substantially constant mutual inductance M 13 . 
     Referring to  FIG. 6 , this self-compensation can be better visualized. While a normal shift in alignment between electrode patterns  4  and  3  along the X and Y directions can result in a reduced mutual superimposition in region  212 , an increased mutual superimposition occurs in region  214 . Additionally, regions  216  and  218  are now also in closer mutual proximity. Accordingly, overall coupling will remain substantially constant, thereby resulting in substantially constant mutual inductance M 13 . 
     Another feature which will be noted is the symmetry of the filter components with respect to the two traces L 2   a , L 2   b  forming the central shunt inductor L 2  and the traces L 3 , L 1  ( FIGS. 4D and 4E ) responsible for forming the outer shunt inductors L 1 , L 3 . In conformance with the discussion above concerning variations in alignment between electrode patterns  4  and  3 , normal variations in such alignment along the X and Y directions will be self-compensating with respect to mutual coupling among the shunt inductors L 1 , L 2 , L 3  due to this symmetry. For example, as noted above, normal shifts in alignment along the X or Y direction will cause conductors L 2   a  and L 3  to shift with respect to conductors L 2   b  and L 1 . However, with the center shunt inductor L 2  formed by two generally similar and inversely symmetrical conductors positioned near the periphery of the regions in which the outer shunt inductors L 1 , L 3  are formed, any coupling between the center inductor L 2  and its adjacent inductors L 1 , L 3  will remain substantially constant. 
     In other words, notwithstanding any variations and alignment between electrode patterns  4  and  3 , coupling between inductor L 1  and L 2  will be determined primarily by the proximity of conductor L 3  and conductor L 2   a . Since these two conductors L 3 , L 2   a  are on the same substrate layer, any variations in alignment between electrode patterns  4  and  3  will have virtually no effect. Similarly, coupling between inductor L 2  and inductor L 1  will be determined primarily by the proximity of conductor L 2   b  and L 1 . Accordingly, since these two conductors L 2   b , L 1  are on the same substrate layer, variations in alignment between electrode patterns  4  and  3  will have virtually no effect. 
     Referring back to  FIG. 4E , another feature of this RF module concerns the bypass capacitors C 101 -C 108 . These capacitors C 101 -C 108  are implemented as buried capacitors. As discussed above, the bottom capacitor plates C 101   b , C 102   b , C 103   b , C 104   b , C 105   b , C 106   b , C 107   b , C 108   b  are formed as part of the electrode patterns on electrode pattern  3 . On top of such capacitor plate regions, a dielectric paste  500  is formed, e.g., deposited, preferably with a very high dielectric constant (K), i.e., higher than the dielectric constant of the ceramic tape. Then, on top of this dielectric paste  500 , the top capacitor plates C 101   a , C 102   a , C 103   a , C 104   a , C 105   a , C 106   a , C 107   a , C 108   a  are formed according to well known conventional techniques. (Further discussion of these types of capacitors in general can be found in U.S. Pat. No. 6,252,761, the disclosure of which is incorporated herein by reference.) These top capacitor plates C 101   a , C 102   a , C 103   a , C 104   a , C 105   a , C 106   a , C 107   a , C 108   a  are then coupled to their respective power supply terminals in electrode pattern  7  by conductive vias 101 v, 102 v, 103 v, 104 v, 105 v, 106 v, 107 v, 108 v. The lengths of these conductive vias, as well as the lengths of any additional interconnecting lines, are known (based upon the LTCC substrate design parameters); therefore, the inductance of each such conduction path can be determined (e.g., by computation or measurement). 
     Referring to  FIG. 7 , the capacitance for each of these capacitors C 101  C 102 , C 103 , C 104 , C 105 , C 106 , C 107 , C 108  can be selected and designed such that these respective inductances and capacitances, which are in series, will form series resonant circuits at the nominal signal frequency. Hence, in accordance with well known RF principles, such series resonant circuits will provide virtual short circuit connections between the bypass power supply terminals and RF circuit grounds for any signals appearing at such nominal frequency. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.