Abstract:
Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to output buffer circuits. 
     In many systems, especially those requiring high speed data links, a need exists to provide effective interconnection between integrated circuit chips employing CMOS (Complementary Metal Oxide Silicon) technology and chips employing ECL (Emitter Coupled Logic) circuitry. The problem arises because CMOS circuits generally operate with logic swings between 0→5 volts, while ECL chips operate with logic swings between -0.95→-1.7 volts. 
     A traditional method of achieving the appropriate voltage swing is to provide a bipolar buffer circuit in a chip which is external to the CMOS chip (see, e.g., Fairchild F100K ECL Data Book, pp. 3-38 to 3-40 (1986)). It would be more desirable based on performance and cost factors to provide a CMOS output buffer incorporated into the CMOS chip itself for interconnection with an ECL chip. 
     Some suggestions have been made recently to provide a CMOS output buffer circuit. For example, in Meier, &#34;A 2 μm CMOS Digital Adaptive Equalizer Chip . . . , &#34; IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 64-65 and 302-303 (1988), the lower level voltage is established by an external power supply. The upper voltage level is set by an MOS transistor acting as a current source which mirrors the current through a series of transistors in another branch. Thus, only the upper voltage level is controlled by the circuit. 
     It is, therefore, an object of the invention to provide as part of a CMOS integrated circuit chip an output buffer circuit which accurately sets voltage levels for connection with ECL logic chips. 
     SUMMARY OF THE INVENTION 
     These and other objects are achieved in accordance with the invention which is an output buffer circuit. A first MOS transistor is provided in a first branch of the circuit and a second MOS transistor is provided in a second branch of the circuit. A third MOS transistor is also provided in the second branch and adapted to turn on and off the current through the second branch. The two branches are coupled in parallel so that the output voltage of the first branch when current in the second branch is turned off provides one voltage level for an emitter coupled logic circuit connected to the output of the branches, and the output of the two branches when the current in the second branch is turned on provides another voltage level for the emitter coupled logic circuit connected to the output. The transistors are integrated into a single semiconductor chip. A resistor is also provided external to the chip for supplying reference voltages to the output buffer circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other features of the invention are delineated in detail in the following description. In the drawing: 
     FIG. 1 is a schematic block diagram of a circuit incorporating an output buffer in accordance with an embodiment of the invention; 
     FIG. 2 is a schematic circuit diagram of a portion of the circuit of FIG. 1 in accordance with an embodiment of the invention; 
     FIG. 3 is another portion of the circuit of FIG. 1 in accordance with an embodiment of the invention; and 
     FIG. 4 is an illustration of voltage waveforms for operating the circuit of FIG. 3. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates and overall view of a circuit which includes conversion of CMOS voltage levels to ECL voltage levels. A standard bandgap voltage reference circuit, 10, generates a voltage V BG  which is independent of temperature and power supply voltage. The bandgap reference circuit is coupled to a standard voltage mirror circuit, 11, where V BG  is converted to low and high voltages, V OL  and V OH , respectively. Typically, V BG  is approximately V SS  +1.23 volts, while V OL  is approximately V DD  -1.7 volts and V OH  is approximately V DD  -0.95 volts. V SS  is the most negative supply voltage to the CMOS chip (typically -5 volts) and V DD  is the most positive voltage (typically 0 volts). 
     These circuits are fairly standard in the art and are therefore not discussed in detail. 
     The voltages, V OL  and V OH  are coupled to a sampling reference circuit 12 which, together with a reference resistor 13, provide low and high reference voltages, V OLR  and V OHR , respectively, for the output buffer circuit, 14. V OLR  is typically -1.44 volts and V OHR  is typically -1.50 volts. The buffer circuit, 14, receives CMOS voltage levels at its input terminal designated &#34;CMOS In&#34; from the CMOS integrated circuit chip and converts to voltage levels compatible with ECL chips at its output designated &#34;ECL Out.&#34; The signal is sent along a transmission path, 15, to same ECL chip (not shown). 
     FIG. 2 illustrates in some detail the output buffer circuit 14. The low and high reference voltages, V OLR  and V OHR , are coupled to the inputs of separate operational amplifiers, 20 and 21, respectively. These amplifiers include feeback loops to the other input for the purpose of creating unity gain buffers. The outputs of these amplifiers, 20 and 21, are coupled to the gates of separate MOS transistors, M 3  and M 1 , respectively. These transistors have their source regions coupled in common to a node at a potential, V DD , which, as mentioned above, is the upper driving voltage for the CMOS chip. Capacitors C 2  and C 3  which are coupled between the gates of M 3  and M 1  and V DD  serve to filter out ripples due to parasitic capacitances on these transistors. Capacitor C 4  is coupled between the node at V DD  and the source of transistor M 2  thereby providing a shunt for transistor M 1 . 
     Current flow through the branch of the circuit including transistor M 1  is controlled by MOS transistor M 2 . M 2  is turned on or off by a voltage supplied to its gate from the remainder of the CMOS chip (designated CMOS V in ) through a phase splitter 22 which divides the incoming signal into two signals which are 180 degrees out of phase. One of said signals is amplified by a driver stage 23 and the output of that stage is applied to the gate of M 2 . 
     In operation, transistors M 3  and M 1  are operated in their linear region so that their drains essentially function as non-ideal voltage sources with the output voltage at the node labeled &#34;ECL Out&#34; being a strict function of the voltage applied to their gate electrodes and of the value of the load current through the termination resistor (16 of FIG. 1). The lower voltage level for the ECL output (-1.7 volts) is established when only the branch including M 3  is conducting current. When the branch including M 1  is conducting, as a result of turning on transistor M 2 , the voltage at &#34;ECL out&#34; will be the higher level voltage for ECL operation (-0.95 volts). The presence of C 4  in the branch including M 1  decreases the rise time and lowers impedance at the node by passing most of the current through the capacitor during the ramp up of the current. 
     Means are also provided in the circuit to reduce charge buildup on transistor M 2 . These means include an MOS transistor M 4  whose gate is coupled to the same driver stage (23) as transistor M 2 , and an MOS transistor M 5  whose gate is coupled to another driver stage, 24, which in turn is coupled to phase splitter 22 and receives a signal 180 degrees out of phase with that of driver 23. The drain of transistor M 4  is coupled to the drain of transistor M 2  through resistor R 1 , and the source of M 4  is coupled in common with the drain of M 5  to driver stage 24 through capacitor C 5 . Capacitor C 6  provides a shunt across transistor M 5 . 
     In the operation of this portion of the circuit, when the signal from driver stage 23 ramps up, M 4  is made conducting and any charge accumulated on M 2  will be sucked through M 4 , discharging capacitor C 5  into driver stage 24 and out through a V SS  connection (not shown). When the signal from driver 23 ramps down, M 4  is disconnected from M 2  while M 5  is made conducting by the signal from driver 24. This recharges capacitor C 5  so that charge removal can again be effected in the next signal cycle. Capacitor C 6  serves as an additional shunt to accumulated charge on the drain of M 2  when M 4  turns on and M 5  turns off. 
     It will be appreciated that the circuit of FIG. 2 is designed to operate at a high voltage (V DD ) of 0 volts and a low voltage (V SS ) of -5 volts compatible with the rest of the CMOS circuitry on the chip. Also, the high and low voltages generated by the circuit for ECL operation should be within a fairly narrow range. A typical specification is a high voltage level between -0.880 and -1.025 volts, and a low voltage level between -1.620 and -1.810. The circuit of the present invention provides sufficient control so that the voltages fall within these ranges. 
     One example of a circuit for providing stable reference voltages (12 of FIG. 1) is illustrated in FIG. 3. Voltages V OL  and V OH  from the voltage mirror circuit (11 of FIG. 1) are coupled to the inputs of separate operational amplifiers, 30 and 31. The output of amplifier 30 is coupled, through MOS transistors M 8  and M 9 , to the gate of MOS transistor M 7 , while the output of amplifier 31 is coupled to the gate of MOS transistor M 6 . Transistors M 6  and M 7  are in separate branches coupled in parallel between a node at V DD  and a node which is coupled to the reference resistor 13. Current through the branch including M 6  is controlled by transistor M 14  which is coupled to a source of voltage designated as V P4 . The node coupled to reference resistor 13 is also coupled through resistor R 2  to the other inputs of the operational amlifiers, 30 and 31, not coupled to reference voltages V OL  and V OH . Also coupled to the outputs of operational amplifiers 30 and 31 are transistor pairs, M 10 , M 11  and M 12 , M 13 , respectively. The output of these pairs are the reference voltages, V OLR  and V OHR  which are supplied to the output buffer (FIG. 2). 
     The operation of the reference circuit of FIG. 3 can be understood in conjunction with the voltage waveforms shown in FIG. 4. All voltages vary between a high value of 0 volts (V DD ) and a low value of -5 volts (V SS ). A high value of V P4  applied to transistor M 14  renders it nonconductive. This limits current flow between V DD  and V TT  to the branch of the circuit including M 7 . The voltage across the reference resistor 13 will be sensed by the input of the operational amplifier, 30, not coupled to voltage V OL . Applying a high value of V P3  to transistor M 9  and voltage V P3 , which is 180 degrees out of phase, to transistor M 8  connects a negative feedback loop to the operational amplifier 30. This loop includes M 8 , M 9 , M 7  and R 2  in series, and C 9  and resistor 13 in parallel therewith. When equilibrium is reached, therefore, the two inputs will be equal and the output V.sub. LR will be a stable function of the reference voltage V OL  from the voltage mirror (11 of FIG. 1) and the reference resistor (13 of FIG. 1). After equilibrium is reached, a pulse V P1  is applied to transistor M 10  and its opposite V P1  applied to transistor M 11  to connect that portion of the circuit. This establishes V OLR  at its output and also stores the charge generated by that voltage on capacitor C 7 . In the next cycle, V P4  goes low thereby causing M 14  to conduct. At the same time, although V P3  is low, the gate of M 7  is kept at V LR  by the stored charge on capacitor C 9 . This causes conduction through both branches of the circuit, but only the feedback loop to operational amplifier 31 will be activated. This loop includes M 6 , M 14  and R 2  in series, and M 7  and resistor 13 in parallel. The voltage across the resistor, 13, due to the current through both branches is now sensed at the input of amplifier 31 not connected to V OH . When equilibrium is reached, the voltage at both inputs will be equal, and the output voltage V HR  will be a function of this higher reference voltage. A voltage V P2  is applied to M 12  and V P2  applied to M 13  to establish V OHR  at the output and to store charge corresponding to this voltage on capacitor C 8 . 
     Thus, the circuit of FIG. 3 performs alternate sampling of the high and low reference voltages, V OH  and V OL , across the reference resistor 13 by means of feedback loops to the amplifiers 30 and 31. This scheme allows a single reference resistor to be utilized. However, it should be realized that the invention could be used with two reference resistors, if desired, in which case two separate, continuously operating feedback loops would be used. 
     Various additional modifications will become apparent to those skilled in the art. All such variations which basically rely on the teachings through which the invention has advanced the art are properly considered within the scope of the invention.