Abstract:
A DC-DC converter including a Pulse Width Modulation (PWM) controller for converting an input voltage into an output voltage is provided. The PWM controller includes: an error amplifier, receiving a reference voltage and a feedback voltage and provides an error signal; a compensation unit coupled to an output of the error amplifier, compensating the error signal and comprising a first resister and a first capacitor; a ramp generator, generating a ramp signal according to a constant on time PWM signal; a first comparator coupled to the compensation unit and the ramp generator, comparing the compensated error signal with the ramp signal to generate a trigger signal; and a PWM generator coupled to the first comparator, providing the constant on time PWM signal according to the trigger signal, an input voltage of the DC-DC converter and the output voltage of the DC-DC converter.

Description:
[0001]    This application is a Continuation of pending U.S. patent application Ser. No. 12/536,086, filed Aug. 5, 2009, and entitled “DC-DC Converter with a Constant On-Time Pulse Width Modulation Controller”, the entirety of which is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a controller of a DC-DC converter, and more particularly to a DC-DC converter with a constant on time (COT) pulse width modulation (PWM) controller. 
         [0004]    2. Description of the Related Art 
         [0005]    DC-DC converters are widely used for various electronic devices. A constant on-time (COT) voltage regulator is one type of DC-DC converter. In general, a COT voltage regulator may turn on a main switch during a fixed period when a feedback voltage is smaller than a reference voltage, and the COT voltage regulator may adjust a turn off period of the main switch so that a steady output voltage may be provided. An output capacitor with a high equivalent series resistance (ESR) disposed in parallel with a load is necessary for a conventional COT voltage regulator, so that a steady output voltage may be provided. However, although a high ESR may help to provide system stability, for a COT voltage regulator, probability of output ripples increase due to the high ESR, which negatively influence the output voltage and power conversion efficiency of the COT voltage regulator. 
         [0006]    U.S. Pat. No. 6,583,610 discloses a voltage regulator which operates in ripple-mode and comprises a virtual ripple generator. The virtual ripple generator provides a regulator feedback signal that includes a generated ripple component as a composite signal. The composite signal is generated according to an actual output signal and a ripple signal synchronized to switching cycles of the voltage regulator. Thus, the regulation feedback signal reflects the DC value of the output signal and is responsive to transient changes in the output signal level. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    DC-DC converters are provided. An exemplary embodiment of the DC-DC converter for converting an input voltage into an output voltage is provided. The DC-DC converter comprises an input node for receiving the input voltage, an output node for providing the output voltage to a load, an inductor coupled between the output node and a first node, a first transistor coupled between the input node and the first node, a second transistor coupled between the first node and a ground, and a Pulse Width Modulation (PWM) controller. The PWM controller comprises an error amplifier, a first comparator, a PWM generator, and a ramp generator. The error amplifier receives a reference voltage and the output voltage to generate an error signal according to a difference between the reference voltage and the output voltage. The first comparator compares the error signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input voltage and the output voltage. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage. The PWM controller provides the PWM signal to control the first transistor and the second transistor, so as to convert the input voltage into the output voltage. 
         [0008]    Furthermore, another exemplary embodiment of a DC-DC converter for converting an input voltage into an output voltage is provided. The DC-DC converter comprises an input node for receiving the input voltage, an output node for providing the output voltage to a load, an inductor coupled between the output node and a first node, a first transistor coupled between the input node and the first node, a second transistor coupled between the first node and a ground, and a PWM controller. The PWM controller comprises an error amplifier, a sense unit, a compensation unit, a first comparator, a PWM generator, and a ramp generator. The error amplifier receives a reference voltage and the output voltage to generate an error signal according to a difference between the reference voltage and the output voltage. The sense unit senses the inductor to generate a sense current. The compensation unit generates a compensation signal according to the error signal and the sense current. The first comparator compares the compensation signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input voltage and the output voltage. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage. The PWM controller provides the PWM signal to control the first transistor and the second transistor, so as to convert the input voltage into the output voltage. 
         [0009]    Moreover, another exemplary embodiment of a DC-DC converter for converting an input voltage into an output voltage is provided. The DC-DC converter comprises an input node for receiving the input voltage, an output node for providing the output voltage to a load, an inductor coupled between the output node and a first node, a first transistor coupled between the input node and the first node, a second transistor coupled between the first node and a ground, and a PWM controller. The PWM controller comprises an error amplifier, a sense unit, a compensation unit, a first comparator, a PWM generator, and a ramp generator. The error amplifier receives a reference voltage and the output voltage to generate an error signal according to a difference between the reference voltage and the output voltage. The sense unit generates a sense current corresponding to a loading of the load. The compensation unit generates a compensation signal according to the sense current and a ramp signal. The first comparator compares the compensation signal with error signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input voltage and the output voltage. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage. The PWM controller provides the PWM signal to control the first transistor and the second transistor, so as to convert the input voltage into the output voltage. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  shows a DC-DC converter according to an embodiment of the invention; 
           [0013]      FIG. 2  shows a waveform diagram illustrating the relationship between the PWM signal S PWM  and a current I L  flowing through the inductor L of  FIG. 1 ; 
           [0014]      FIG. 3A  shows a PWM generator according to an embodiment of the invention; 
           [0015]      FIG. 3B  shows a waveform diagram of the signals in the PWM generator of  FIG. 3A ; 
           [0016]      FIG. 4A  shows a ramp generator according to an embodiment of the invention; 
           [0017]      FIG. 4B  shows a waveform diagram of the signals in the ramp generator of  FIG. 4A ; 
           [0018]      FIG. 5  shows an example illustrating a waveform diagram of the signals of the DC-DC converter of  FIG. 1 ; 
           [0019]      FIG. 6  shows another example illustrating a waveform diagram of the signals of the DC-DC converter of  FIG. 1 ; 
           [0020]      FIG. 7  shows a DC-DC converter according to another embodiment of the invention. 
           [0021]      FIG. 8  shows a DC-DC converter according to another embodiment of the invention; 
           [0022]      FIG. 9  shows a DC-DC converter according to another embodiment of the invention; and 
           [0023]      FIG. 10  shows a DC-DC converter according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0025]      FIG. 1  shows a DC-DC converter  100  according to an embodiment of the invention. The DC-DC converter  100  converts an input voltage V IN  received from an input node N in  into an output voltage V OUT . The DC-DC converter  100  comprises two transistors MU and ML, an inductor L, a control unit  110  and a PWM controller  120 . The transistor MU is coupled between the input node N in  and a node N 1 , and the transistor ML is coupled between the node N 1  and a ground GND. In this embodiment, the transistors MU and ML are N-type transistors which function as the switches. The control unit  110  receives a pulse width modulation (PWM) signal S PWM  provided by the PWM controller  120  and controls the transistors MU and ML to switch on or off according to the PWM signal S PWM . The inductor L is coupled between the node N 1 , and an output node N out , wherein the output voltage V OUT  is outputted to a load  180  via the output node N out . Furthermore, an output capacitor C 1  with a lower equivalent series resistance (ESR) is coupled between the N out  and the ground GND, and a resistor Resr represents an ESR of the output capacitor C 1 . 
         [0026]    As shown in  FIG. 1 , the PWM controller  120  comprises a ramp generator  130 , a PWM generator  140 , a compensation unit  150 , an error amplifier  160  and a comparator  170 . The error amplifier  160  receives a reference voltage Y REF  and the output voltage V OUT  to generate an error signal V ERR  according to a difference between the reference voltage V REF  and the output voltage V OUT . The compensation unit  150  coupled between an output terminal of the error amplifier  160  and the comparator  170  is used to compensate the error signal V ERR , and the compensation unit  150  comprises a resistor  152  coupled to the output terminal of the error amplifier  160  and a capacitor  154  coupled between the resistor  152  and the ground GND. After the error signal V ERR  is compensated, the comparator  170  compares the error signal V ERR  with a ramp signal S RAMP  provided by the ramp generator  130  to generate a trigger signal S TR . The PWM generator  140  generates the PWM signal S PWM  according to the trigger signal S TR , the input voltage V IN  and the output voltage Y OUT . The ramp generator  130  generates the ramp signal S RAMP  according to the PWM signal S PWM , the input voltage Y IN  and the output voltage Y OUT . 
         [0027]      FIG. 2  shows a waveform diagram illustrating the relationship between the PWM signal S PWM  and a current I L  flowing through the inductor L of  FIG. 1 . Referring to  FIG. 1  and  FIG. 2  together, during a period T on  (i.e. a turn-on time of the PWM signal), the PWM signal S PWM  controls the transistor MU to turn on and controls the transistor ML to turn off. During a period T off  (i.e. a turn-off time of the PWM signal), the PWM signal S PWM  controls the transistor MU to turn off and controls the transistor ML to turn on. As shown in  FIG. 2 , the current I L  has a minimum current value I min  (ex. I min =O) at time t 1 , and then the current I L  starts to increase and reaches a maximum current value I max  at time t 2 , wherein I max =2×I avg  and I avg  represents an average current value of the current I L . Next, the current I L  starts to decrease and reaches the minimum current value I min  at time t 3 . A rising slope SI of the current I L  may be given by the following Equation (1): 
         [0000]    
       
         
           
             
               
                 
                   
                     S 
                      
                     
                         
                     
                      
                     1 
                   
                   = 
                   
                     
                       
                         
                           V 
                           IN 
                         
                         - 
                         
                           V 
                           OUT 
                         
                       
                       L 
                     
                     = 
                     
                       
                         
                           2 
                           × 
                           
                             I 
                             avg 
                           
                         
                         
                           T 
                           on 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    According to the Equation (1), the period T on  may be given by the following Equation (2): 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                     on 
                   
                   = 
                   
                     
                       
                         2 
                         × 
                         
                           I 
                           avg 
                         
                         × 
                         L 
                       
                       
                         
                           V 
                           IN 
                         
                         - 
                         
                           V 
                           OUT 
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    In addition, a falling slope S 2  of the current I L  may be given by the following Equation (3): 
         [0000]    
       
         
           
             
               
                 
                   
                      
                     
                       S 
                        
                       
                           
                       
                        
                       2 
                     
                      
                   
                   = 
                   
                     
                       
                         V 
                         OUT 
                       
                       L 
                     
                     = 
                     
                       
                         
                           2 
                           × 
                           
                             I 
                             avg 
                           
                         
                         
                           T 
                           off 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    According to the Equation (3), the period T off  may be given by the following Equation (4): 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                     off 
                   
                   = 
                   
                     
                       
                         2 
                         × 
                         
                           I 
                           avg 
                         
                         × 
                         L 
                       
                       
                         V 
                         OUT 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Therefore, according to the Equations (2) and (4), a period T and a frequency F SW  of the PWM signal S PWM  may be given by the following Equations (5) and (6), respectively: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       T 
                       = 
                       
                         
                           
                             T 
                             on 
                           
                           + 
                           
                             T 
                             off 
                           
                         
                         = 
                         
                           2 
                           × 
                           
                             I 
                             avg 
                           
                           × 
                           
                             L 
                              
                             
                               ( 
                               
                                 
                                   1 
                                   
                                     
                                       V 
                                       IN 
                                     
                                     - 
                                     
                                       V 
                                       OUT 
                                     
                                   
                                 
                                 + 
                                 
                                   1 
                                   
                                     V 
                                     OUT 
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                     ; 
                   
                    
                   
                     
 
                   
                    
                   and 
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     F 
                     SW 
                   
                   = 
                   
                     
                       1 
                       T 
                     
                     = 
                     
                       
                         1 
                         
                           2 
                           × 
                           
                             I 
                             avg 
                           
                           × 
                           L 
                         
                       
                       × 
                       
                         
                           
                             
                               ( 
                               
                                 
                                   V 
                                   IN 
                                 
                                 - 
                                 
                                   V 
                                   OUT 
                                 
                               
                               ) 
                             
                             × 
                             
                               V 
                               OUT 
                             
                           
                           
                             V 
                             IN 
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0028]    Suppose that the period T on  has a relationship with a ratio of the output voltage V OUT  to the input voltage V IN , i.e. T on =RCK(V OUT /V IN ), wherein the parameters R, C and K are constant. Therefore, the period T on  may be rewritten as the following Equation (7) to obtain the following Equation (8): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         T 
                         on 
                       
                       = 
                       
                         
                           R 
                            
                           
                               
                           
                            
                           C 
                            
                           
                               
                           
                            
                           
                             K 
                              
                             
                               ( 
                               
                                 
                                   V 
                                   OUT 
                                 
                                 
                                   V 
                                   IN 
                                 
                               
                               ) 
                             
                           
                         
                         = 
                         
                           
                             2 
                             × 
                             
                               I 
                               avg 
                             
                             × 
                             L 
                           
                           
                             
                               V 
                               IN 
                             
                             - 
                             
                               V 
                               OUT 
                             
                           
                         
                       
                     
                     ; 
                   
                    
                   
                     
 
                   
                    
                   and 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     2 
                     × 
                     
                       I 
                       avg 
                     
                     × 
                     L 
                   
                   = 
                   
                     R 
                      
                     
                         
                     
                      
                     C 
                      
                     
                         
                     
                      
                     
                       K 
                        
                       
                         ( 
                         
                           
                             V 
                             OUT 
                           
                           
                             V 
                             IN 
                           
                         
                         ) 
                       
                     
                      
                     
                       
                         ( 
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             OUT 
                           
                         
                         ) 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    According to the Equation (8), the period T off  may be rewritten as the following Equation (9): 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                     off 
                   
                   = 
                   
                     
                       
                         2 
                         × 
                         
                           I 
                           avg 
                         
                         × 
                         L 
                       
                       
                         V 
                         OUT 
                       
                     
                     = 
                     
                       R 
                        
                       
                           
                       
                        
                       C 
                        
                       
                           
                       
                        
                       
                         
                           K 
                            
                           
                             ( 
                             
                               
                                 
                                   V 
                                   IN 
                                 
                                 - 
                                 
                                   V 
                                   OUT 
                                 
                               
                               
                                 V 
                                 IN 
                               
                             
                             ) 
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Thus, according to the Equations (7) and (9), the period T of the PWM signal S PWM  may be rewritten as the following Equation (10): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         T 
                         = 
                           
                          
                         
                           Ton 
                           + 
                           Toff 
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             C 
                              
                             
                                 
                             
                              
                             
                               K 
                                
                               
                                 ( 
                                 
                                   
                                     V 
                                     OUT 
                                   
                                   
                                     V 
                                     IN 
                                   
                                 
                                 ) 
                               
                             
                           
                           + 
                           
                             R 
                              
                             
                                 
                             
                              
                             C 
                              
                             
                                 
                             
                              
                             
                               K 
                                
                               
                                 ( 
                                 
                                   
                                     
                                       V 
                                       IN 
                                     
                                     - 
                                     
                                       V 
                                       OUT 
                                     
                                   
                                   
                                     V 
                                     IN 
                                   
                                 
                                 ) 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           R 
                            
                           
                               
                           
                            
                           C 
                            
                           
                               
                           
                            
                           
                             K 
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0029]    Due to the parameters R, C and K being constant, the period T of the PWM signal S PWM  is fixed. 
         [0030]      FIG. 3A  shows a PWM generator  300  according to an embodiment of the invention. The PWM generator  300  comprises an amplifier  310 , a current generating unit  320 , a comparator  330 , a transistor MI, a resistor R RT  and a capacitor C ON . The amplifier  310  has an inverting input terminal coupled to a node N 2 , a non-inverting input terminal for receiving a voltage V 1  and an output terminal coupled to a gate of the transistor M 1 , wherein the voltage V 1  is a voltage in proportion to the input voltage V IN , i.e. VI=KI×V IN . The current generating unit  320  is used as an example for description, and does not limit the invention. For example, the current generating unit  320  may be a current mirror circuit. When the trigger signal S TR  is triggered, a current I 1  provided by the current generating unit  320  may flow through the transistor MI and the resistor R RT , wherein a current value of the current I 1  is determined according to the voltage VI and the resistor R RT , ex. I 1 =VI/R RT =KI×V IN /R RT . Simultaneously, the capacitor C ON  is charged by a current I 2  provided by the current generating unit  320  when the trigger signal S TR  is triggered. In one embodiment, a current value of the current I 2  is equal to that of the current I 1 , ex. I 2 =K 1 ×V IN /R RT . In another embodiment, the current I 2  is a current in proportion to the current I 1 . 
         [0031]      FIG. 3B  shows a waveform diagram of the signals in the PWM generator  300  of  FIG. 3A . Referring to  FIG. 3A  and  FIG. 3B  together, a voltage V c represents a voltage across the capacitor C ON . The comparator  330  is used to compare the voltage V C  with a voltage V 2 , wherein the voltage V 2  is a voltage in proportion to the output voltage V OUT , i.e. V 2 =K 2 ×V OUT . When the voltage V C  is smaller than the voltage V 2 , an active state of the PWM signal S PWM  is asserted, i.e. the period T on . On the contrary, when the voltage V C  is larger than the voltage V 2 , an inactive state of the PWM signal S PWM  is asserted, i.e. the period T off . Therefore, the period T on  and the period T off  may be given by the following Equations (11) and (12), respectively: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         T 
                         on 
                       
                       = 
                       
                         
                           
                             
                               C 
                               ON 
                             
                             
                               I 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                            
                           dV 
                            
                           
                               
                           
                            
                           2 
                         
                         = 
                         
                           
                             R 
                             RT 
                           
                            
                           
                             
                               C 
                               on 
                             
                              
                             
                               ( 
                               
                                 
                                   K 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                                 
                                   K 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                               ) 
                             
                           
                            
                           
                             
                               V 
                               OUT 
                             
                             
                               V 
                               IN 
                             
                           
                         
                       
                     
                     ; 
                   
                    
                   
                     
 
                   
                    
                   and 
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
             
               
                 
                   Toff 
                   = 
                   
                     
                       R 
                       RT 
                     
                      
                     
                       
                         C 
                         on 
                       
                        
                       
                         ( 
                         
                           
                             K 
                              
                             
                                 
                             
                              
                             2 
                           
                           
                             K 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         ) 
                       
                     
                      
                     
                         
                     
                      
                     
                       
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             OUT 
                           
                         
                         
                           V 
                           IN 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Due to the resistor R RT , the capacitor C ON  and the parameters K 1  and K 2  being constant, the period T on  and the period T off  are determined according to the input voltage V IN  and the output voltage V OUT . 
         [0032]      FIG. 4A  shows a ramp generator  400  according to an embodiment of the invention. The ramp generator  400  comprises an amplifier  410 , two transistors M 2  and M 3 , a capacitor C OFF  and a current source  420 . The amplifier  410  has an invelting input terminal coupled to the transistor M 2 , a non-inverting input terminal for receiving a voltage V 3  and an output terminal coupled to the inverting input terminal, wherein the voltage V 3  is a voltage in proportion to a difference between the input voltage V IN  and the output voltage V OUT , i.e. V 3 =K 3 ×K 1 ×(V IN −V OUT ). The transistor M 2  is coupled between the output terminal of the amplifier  410  and a node N 3 , and the transistor M 3  is coupled between the node N 3  and the current source  420 , wherein the ramp signal S RAMP  is a voltage at the node N 3 . The transistors M 2  and M 3  are controlled by the PWM signal S PWM  and a signal SB PWM , respectively, wherein the signal SB PWM  is a reversed signal for the PWM signal S PWM . Therefore, the transistor M 2  is turned on and the transistor M 3  is turned off when an active state of the PWM signal S PWM  is asserted, and the transistor M 2  is turned off and the transistor M 3  is trned on when an inactive state of the PWM signal S PWM  is asserted. 
         [0033]      FIG. 4B  shows a waveform diagram of the signals in the ramp generator  400  of  FIG. 4A . Referring to  FIG. 4A  and  FIG. 4B  together, the ramp signal S RAMP  represents the voltage of the node N 3 , i.e. a voltage across the capacitor C OFF . When an active state of the PWM signal S PWM  is asserted, the transistor M 2  is turned on and the transistor M 3  is turned off, such that the capacitor C OFF  is charged by the amplifier  410  via the transistor M 2 , and then the voltage across the capacitor C OFF  is charged to a voltage level of the voltage V 3 . On the contrary, when an inactive state of the PWM signal S PWM  is asserted, the transistor M 2  is turned off and the transistor M 3  is turned on, such that the capacitor C OFF  is discharged by the current source  420  via the transistor M 3 , and then the voltage across the capacitor C OFF  is decreased until a subsequent active state of the PWM signal S PWM  is asserted. In the embodiment, the current source  420  may sink a current I 3  from the node N 3  to the ground GND to decrease the ramp signal S RAMP , wherein the current I 3  corresponds to the input voltage V IN . The current source  420  is used as an example, and does not limit the invention. In one embodiment, a current value of the current I 3  is equal to that of the current I 1  of the PWM generator  300  in  FIG. 3A , ex. I 3 =KI×V IN /R RT . In another embodiment, the current I 3  is a current in proportion to the current U 1 . Therefore, a voltage variation dV RAMP  of the ramp signal S RAMP  during the period T off  may be given by the following Equation (13): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           dV 
                           RAMP 
                         
                         = 
                           
                          
                         
                           
                             I 
                              
                             
                                 
                             
                              
                             3 
                           
                           
                             
                               C 
                               OFF 
                             
                              
                             dT 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               K 
                                
                               
                                   
                               
                                
                               1 
                               × 
                               
                                 V 
                                 IN 
                               
                             
                             
                               
                                 R 
                                 RT 
                               
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                               V 
                               steady 
                             
                           
                         
                         , 
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0000]    wherein a voltage level V steady  represents an ideal steady voltage level of the error signal V ERR  in  FIG. 1 . Therefore, according to the Equation (13), the voltage level V steady  of the error signal V ERR  may be given by the following Equation (14): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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                           steady 
                         
                         = 
                           
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                         = 
                           
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                            
                           
                             
                               ( 
                               
                                 
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                                   IN 
                                 
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                                   OUT 
                                 
                               
                               ) 
                             
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
         [0000]    By choosing the parameters K 1 , K 2  and K 3  and the capacitors C ON  and C OFF  appropriately, the error signal V ERR  is designed to operate at a direct current (DC) operation voltage level, i.e. the ideal steady voltage level V steady . 
         [0034]    Referring to  FIG. 1 , a fine adjustment of the error signal V ERR  is automatically performed for a feedback loop of the DC-DC converter  100  according to the determined DC operation voltage level of the error signal V ERR , so as to determine a time period that the trigger signal STR is triggered for every period T of the PWM signal S PWM , thus obtaining a pseudo fix frequency PWM controller. 
         [0035]      FIG. 5  shows an example illustrating a waveform diagram of the signals of the DC-DC converter  100  of  FIG. 1 . By using the error amplifier  160  to generate the error signal V ERR  and comparing the error signal V ERR  with the ramp signal S RAMP  to adjust a duty cycle of the PWM signal S PWM , an included angle e between the error signal V ERR  and the ramp signal S RAMP  is large at time t 4  and sufficient to avoid noise interference, thus increasing a signal to noise ratio (SNR) thereof.  FIG. 6  shows another example illustrating a waveform diagram of the signals of the DC-DC converter  100  of  FIG. 1 . Referring to  FIG. 6  and  FIG. 1  together, the period T H  represents that the load  180  has a higher loading, and the period T L  represents that the load  180  has a lower loading. In addition, the load  180  is changed from the lower to higher loading at time t 5  and changed from the higher to lower loading at time t 6 . When the loading of the load  180  is changed, the comparator  170  may immediately adjust the time period that the trigger signal S TR  is triggered by comparing the ramp signal S RAMP  and the error signal V ERR . Therefore, the DC-DC converter  100  may promptly provide the output voltage V OUT  in response to the loading of the load  180 , thereby increasing system stability. 
         [0036]      FIG. 7  shows a DC-DC conve1ter  700  according to another embodiment of the invention. The DC-DC converter  700  is applied to a capacitor C 2  with a smaller or zero ESR. Compared with the PWM controller  120  of  FIG. 1 , a PWM controller  720  of the DCDC converter  700  further comprises a sense unit  730  for sensing a current flowing through the inductor L to generate a sense current I sense  to a compensation unit  710 , wherein the sense current I sense  corresponds to the loading of the load  180 . The compensation unit  710  comprises a resistor  712 , a capacitor  714 , a resistor R comp  coupled between the error amplifier  160  and the comparator  170 , and a current source  716  for sinking a current I 4  from the resistor R comp  to the ground GND. In one embodiment, the current I 4  is a current in proportion to the sense current I sense . The current source  716  is used as an example, and does not limit the invention. In the embodiment, a current value of the current I 4  is equal to that of the sense current I sense . Therefore, a voltage across the resistor R comp  is determined according to the sense current I sense  and a resistance of the resistor R comp . The compensation unit  710  receives the error signal V ERR  and generates a compensation signal V COMP  to the comparator  170  according to the error signal V ERR  and the voltage across the resistor R comp , such that the comparator  170  of the PWM controller  720  may compare the compensation signal V COMP  with the ramp signal S RAMP  provided by the ramp generator  130  to generate the trigger signal S TR . The compensation signal V COMP  comprises a feedback signal from the output voltage V OUT  associated with a feedback signal from the current flowing through the inductor L, thus avoiding harmonic oscillation and assuring that the output voltage V OUT  is stabilized when the capacitor C 2  with a smaller ESR. In addition, by adjusting the resistor R comp  or detecting a gain of the sense current I sense , a gain of a current loop component is adjusted to increase system stability. 
         [0037]      FIG. 8  shows a DC-DC converter  800  according to another embodiment of the invention. Compared with the DC-DC converter  700  of  FIG. 7 , the sense unit  730  of the DC-DC conve1ter  800  is coupled to a node between the transistor MU and the transistor ML, and senses a current flowing through the transistor ML to generate the sense current I sense . Similarly, the sense current I sense  provided by the sense unit  830  corresponds to the loading of the load  180 . 
         [0038]      FIG. 9  shows a DC-DC converter  900  according to another embodiment of the invention. Compared with the DC-DC converter  700  of  FIG. 7 , the DC-DC converter  900  further comprises a resistor R sense  coupled between the transistor ML and the ground GND. Furthermore, the sense unit  730  of the DC-DC converter  900  is coupled to the resistor R sense , and senses a current flowing through the resistor R sense  to generate the sense current I sense . Similarly, the sense current I sense  provided by the sense unit  930  corresponds to the loading of the load  180 . 
         [0039]      FIG. 10  shows a DC-DC converter  1000  according to another embodiment of the invention. In a PWM controller  1020  of the DC-DC converter  1000 , the comparator  170  compares the error signal V ERR  with a compensation signal V comp  provided by a compensation unit  1010  to generate the trigger signal S TR . In the embodiment, the sense unit  730  senses a current flowing through the inductor L to generate the sense current I sense , wherein the sense current I sense  corresponds to the loading of the load  180 . In one embodiment, the sense unit  730  may sense a current flowing through the transistor ML to generate the sense current I sense . In another embodiment, the DC-DC converter  1000  further comprises a resistor coupled between the transistor ML and the ground GND, e.g. the resistor R sense  of  FIG.9 , and the sense unit  730  may sense a current flowing through the resistor to generate the sense current I sense . The compensation unit  1010  comprises the resistor  712 , the capacitor  714 , a resistor R comp  coupled between the sense unit  730  and the ramp generator  130 , and a current source  716  for sinking a current I 4  from the resistor R comp  to the ground GND. Therefore, the compensation unit  1010  generates the compensation signal V COMP  to the comparator  170  according to the sense current I sense , a voltage across the resistor R comp  and the ramp signal S RAMP . Similarly, the compensation signal V COMP  comprises a feedback signal from the output voltage V OUT  associated with a feedback signal from the current flowing through the inductor L, thus avoiding harmonic oscillation and assuring that the output voltage V OUT  is stabilized when the capacitor C 2  with a smaller ESR. In addition, by adjusting the resistor R comp  or detecting a gain of the sense current I sense , a gain of a current loop component is adjusted to increase system stability. 
         [0040]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.