Abstract:
An arrangement for signal processing at the output of a multichannel detector in the spectrally resolved acquisition of time-variable fluorescence phenomena in a microscope, particularly lifetime measurements, is characterized in that an FPGA (free programmable gate array) is arranged downstream of the output of the multichannel detector.

Description:
[0001]    The present application claims priority from PCT Patent Application No. PCT/EP2007/006279 filed on Jul. 16, 2007, which claims priority from German Patent Application No. DE 10 2006 034 905.9 filed on Jul. 28, 2006, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    Short-pulse lasers are used for time-resolved measurement of fluorescence phenomena (energy transfer, FLIM). 
         [0004]    The fluorophore is excited by a strong ultrashort laser pulse and the decay in fluorescence over time is analyzed. 
         [0005]    2. Description of Related Art 
         [0006]    It is known from DE 10033180A1, which makes up part of the present disclosure, to spectrally resolve the fluorescence signal coming from the sample and to record the spectral components with a multichannel detector. In acquiring FLIM information from a multichannel detector, for example, a 32-channel PMT by Hamamatsu, it is important to record the incoming signals simultaneously, accurately with respect to time, and without dead times in the simplest possible manner. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention offers a particularly advantageous approach to this problem. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0008]      FIG. 1  shows a 32-channel PMT according to DE 10008594 A1 which supplies time-dependent intensity and spectrum data; 
           [0009]      FIG. 2  shows the first step of an FPGA determining the number of pulses arriving per channel within a counting period determined by a pixel clock and their distribution over time according to an embodiment of the present invention; 
           [0010]      FIG. 3   a  is a schematic depiction of the timing of the pixel clock PY according to an embodiment of the present invention; 
           [0011]      FIG. 3   b  shows the signal shape over time per PMT channel according to an embodiment of the present invention; and 
           [0012]      FIG. 4  shows how the time evaluation is carried out within the FPGA according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0013]    It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, many other elements which are conventional in this art. Those of ordinary skill in the art will recognize that other elements are desirable for implementing the present invention. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. 
         [0014]    The present invention will now be described in detail on the basis of exemplary embodiments. 
         [0015]      FIG. 1  shows a 32-channel photo multiplier tube (“PMT”) according to DE 10008594 A1 which supplies time-dependent intensity and spectrum data. The PMT is followed by two application specific integrated circuits (“ASICs”) (e.g., by Hamamatsu), each operating 16 channels in photon counting mode. 
         [0016]    Switching thresholds are determined by comparators for noise cancellation, and a pair of differential leads is provided at the output of the ASICs for each PMT channel to prepare digital 1 or 0 data (pulse or no pulse). The number of pulses arriving per channel within a counting period determined by a pixel clock and their distribution over time is now determined. This is carried out, according to the invention, in an FPGA (free programmable gate array). The first step is shown in  FIG. 2 . An asynchronous counter C into which all of the pulses enter is associated with each PMT channel in the FPGA. The pulses per time unit are stored in registers by a counter. Every counting time has a register and the counting time can be stored in memory by this register. This is carried out by means of drawers, as it were (32 gates in the register), and only pertinent data are stored. 
         [0017]    The system-spanning pixel clock PX determines the time at which the actual counter state is temporarily stored and prepared for transfer to memory (PC) via interface (Giga Star). 
         [0018]    After the counters are read out they are erased and the counting process restarts. 
         [0019]      FIG. 3   a  is a schematic depiction of the timing of the pixel clock PY which represents a laser pulse P triggering a sample reaction and the incoming photons as sample reaction per PMT channel. 
         [0020]    Time windows X, X+1, etc. within a counting cycle (time between two laser pulses) is shown in the top portion. Counting registers are provided for the individual time windows. 
         [0021]      FIG. 3   b  shows the signal shape over time per PMT channel that would correspond to the readout of the counting register. For example, the entire spectral region is not taken into consideration. 
         [0022]      FIG. 4  shows how the time evaluation is carried out within the FPGA. For example, the inputs E 1 , E 2  coming from two PMT channels which receive the digitized signals of the ASICs are shown. 
         [0023]    Hardware wiring V of different length or programmable delay channels (shown) ensure that registers R, R 1 , R 2  are each opened at different times X, x+1, X+2t and, therefore, the pulses entering via the inputs E 1 , E 2  reach the register which is uniquely associated with a time which corresponds to a determined delay after a start signal is triggered (excitation pulse P of the laser). With respect to hardware, 64 inputs, for example (bit length for a data board) are taken and the pins are connected to one another from the outside by a lead V of determined length. Only the register with the arriving pulse(s) has a signal 1; the others have 0. The time data are now available. 
         [0024]    The values are transferred to registers as counting values per channel. 
         [0025]    The registers R with the time data contained therein are read out in the timing of the excitation pulses P and the data are transferred to storage and evaluation media (PC) via an interface. 
         [0026]    While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, the preferred embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the inventions as defined in the following claims.