Abstract:
In one aspect, an embodiment of the invention provides a transition from a planar substrate/chip circuit microwave transmission line to waveguide transmission media on the back of the substrate/chip. The transition enables planar waveguide fed MMW ESA architectures to be realized within the tight grid spacing required for emerging MMW ESAs.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the invention  
         [0002]     The field of the invention relates to transmission line waveguide transitions.  
         [0003]     2. Discussion of the Background  
         [0004]     Conventional interconnects for connecting a transmission line to a waveguide, such as, for example, lateral off chip ribbon interconnects, are reflective to millimeter wave (MMW) signals due to large inductance, use precious lateral area, and are fragile and costly. Additionally, they are performance sensitive for practical applications in emerging MMW electronically scanned arrays (ESAs).  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention aims to overcome at least some of the above described and/or other disadvantages of conventional interconnects. In one aspect, an embodiment of the invention provides a transition from a planar substrate/chip circuit microwave transmission line to waveguide transmission media on the back of the substrate/chip. The transition enables planar waveguide fed MMW ESA architectures to be realized within the tight grid spacing required for emerging MMW ESAs.  
         [0006]     A system according to one aspect of the invention the invention provides an apparatus for use in electronic systems such as, for example, radar systems, communication systems and/or other electronic systems. In some embodiments, the apparatus includes, a first substrate; a first transmission line disposed on a top surface of the first substrate; a second substrate; a ground plane disposed between a bottom surface of the first substrate and a top surface of the second substrate; a third substrate having a top surface that faces the bottom surface of the second substrate; a second transmission line, having a first end and a second end, disposed between the bottom surface of the second substrate and the top surface of the third substrate, wherein the second transmission line widens from the first end to the second end; a via in contact with an end of the first transmission line and in contact with the first end of the second transmission line, wherein the via passes through the first substrate, the ground plane and the second substrate; and a window formed in the second end of the second transmission line.  
         [0007]     In some embodiments, the apparatus further includes a window formed in the third substrate, wherein the window formed in the third substrate is directly beneath and aligned with the window formed in the second transmission line. Additionally, in some embodiments, the apparatus further includes a second ground plane attached to the bottom surface of the third substrate, wherein a window is formed in the ground plane and this window is directly beneath and aligned with the window formed in the third substrate.  
         [0008]     The above and other features and advantages of the present invention, as well as the structure and operation of preferred embodiments of the present invention, are described in detail below with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The accompanying drawings, which are incorporated herein and form part of the specification, help illustrate various embodiments of the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use embodiments of the invention. In the drawings, like reference numbers indicate identical or functionally similar elements.  
         [0010]      FIGS. 1-9  illustrate a transmission line to waveguide transition according to some embodiments of the invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0011]      FIG. 1  illustrates a transmission line  102  to waveguide  104  transition. More specifically,  FIG. 1  is a cross-sectional view of a chip  100  and a waveguide  104 , which is connected to the waveguide interface  103  out the bottom of the chip. In the embodiment shown, transmission line  102  is disposed on a surface of a substrate  106  (substrate  106  may be a GaAs substrate or other substrate), a ground plane  108  is disposed directly between the bottom of substrate  106  and a top surface of a substrate  110 , a substrate  112  is connected to the bottom of substrate  110 , and a second ground plane  114  is attached to the bottom of substrate  112 . Substrates  110 ,  112  are preferably made from a dielectric material. For example, Benzocyclobutene (BCB) may be used to form substrates  110 ,  112 .  
         [0012]     As further shown in  FIG. 1 , a conductive pathway (e.g., a plated through hole or other conductive pathway)  120 , which passes through substrates  106  and  110  and ground plane  108 , is electrically connected between and end  180  of transmission line  102  and an end  182  of a transmission line  122 , which is disposed between substrate  110  and substrate  112 . Transmission line  122  may be printed on the bottom of substrate  110  or on the top of substrate  112 .  
         [0013]     A plurality of conductive pathways (or “Vias”)  130 , which pass through substrate  112 , are electrically connected between an end of transmission line  122  and ground plane  114 . Additionally, a plurality of vias  132 , which pass through substrates  110  and  112 , electrically connect ground plane  108  with ground plane  114 .  
         [0014]     As shown in  FIG. 1 , transmission line  122  connects into the broad wall of a fractional height waveguide structure. Ground plane  108  functions as the other broad wall of the waveguide. The vias are used to create the signal interconnect to the top side (a.k.a., “circuit side”) of substrate  106  and to provide the metal walls of the waveguide. Preferably, the transition would be processed with the dielectric layers  110 ,  112  at the wafer level prior to dicing of the wafer. The dotted lines with arrows at the end represent the signal path.  
         [0015]     An advantage of the interconnect design shown in  FIG. 1  is that it does not take up space in a lateral area of the chip, unlike conventional off chip interconnects, which require lateral area. This enables MMW active ESA planar arrays near lambda/2 grid spacing.  
         [0016]     Referring now to  FIG. 2 ,  FIG. 2  shows a top view of substrate  106 . As shown in  FIG. 2 , signal transmission line  102  is disposed on a top surface of substrate  106  and via  120 , which is disposed at end  180  of transmission line  102 , is used to provide a signal path to transmission line  122 .  
         [0017]     Referring now to  FIG. 3 ,  FIG. 3  shows a top view of ground plane  108 . As shown, ground plane  108  is formed from an electrically conducting material. As further shown, via  120  passes through and is isolated from ground plane  108  (i.e., there is an empty space  302  separating via  120  from ground plane  108 .  
         [0018]     Referring now to  FIG. 4 ,  FIG. 4  shows a top view transmission line  122 . As shown in  FIG. 4 , transmission line  122  widens from end  182  to end  184 . The width of the wide end  184  is dependent upon a selected cutoff frequency for the waveguide performance. In one embodiment, if the width of narrow end  182  is X, then the width of end  184  may be about at least 5 times X. For example, in some embodiments, the width of end  182  may be about 0.005 inches and the width of end  184  may range between about 0.05 inches (i.e., 10×) and about 0.2 inches (i.e., 40×). In a preferred embodiment, as shown in  FIG. 4 , line  122  gradually widens from end  182  to end  184 .  
         [0019]     As further shown, a rectangular window  404  is formed in end  184  of transmission line  122  such that end  184  frames window  404 . Further, vias  130 ,  132  surround the periphery of window  404 . Some of the vias (i.e., vias  130 ) extend only downwardly with respect to transmission line  122  to electrically connect end  184  of transmission line  122  to ground plane  114 , whereas other vias (i.e., vias  132 ) extend upwardly and downwardly with respect to transmission line  122  to electrically connect end  184  of transmission line  122  to ground plane  108  and ground plane  114 .  
         [0020]     Referring now to  FIG. 5 ,  FIG. 5  shows a top (or bottom) view of substrate  112 . As shown, a rectangular window  504  is formed in substrate  112 . Window  504  may have the same width and length dimensions of window  404 . Preferably, window  504  is aligned directly underneath window  404 . As further shown, vias  130 ,  132  surround the periphery of window  504 .  
         [0021]     Referring now to  FIG. 6 ,  FIG. 6  shows a top (or bottom) view of substrate ground plane  114 . As shown, a rectangular window  604  is formed in ground plane  114 . Window  604  may have the same width and length dimensions of window  404 . Preferably, window  604  is aligned directly underneath window  504 . As further shown, vias  130 ,  132  surround the periphery of window  604 .  
         [0022]     Referring now to  FIG. 7 ,  FIG. 7  is a perspective, top view of chip  100  according to some embodiments of the invention. To better illustrate the features of the chip, substrate  106  has been made transparent in the drawing. As shown in  FIG. 7 , chip  100  may have multiple signal transmission lines  102 , and, for each transmission line  102 , there may be a transmission line to waveguide transition for interconnecting the transmission line  102  to a waveguide.  
         [0023]     Referring now to  FIG. 8 ,  FIG. 8  is a perspective, bottom view of chip  100 . Again, for the sake of illustration, substrate  112  has been made transparent.  
         [0024]     As further shown in  FIGS. 7 and 8 , substrate  110  may include thermal pads  702 , substrate  112  may include thermal pads  802 , vias  704  may extend from the top of substrate  106  to thermal pads  702 , and vias  804  may extend between thermal pads  702  and  802 .  
         [0025]     Referring now to  FIG. 9 ,  FIG. 9  is a perspective, exploded view of chip  100  and waveguide  104  according to some embodiments.  
         [0026]     While various embodiments/variations of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.