Abstract:
A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Description:
[0001]    The present application is a Continuation Application of U.S. patent application Ser. No. 14/887,662, filed on Oct. 20, 2015, which is a Continuation Application of U.S. patent application Ser. No. 13/901,482, filed on May 23, 2013, now U.S. Pat. No. 9,176,756 B2, issued on Nov. 3, 2015, which is based on and claims priority from Japanese Patent Application No. 2012-132871, filed on Jun. 12, 2012, the entire contents of which are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to a computer system. More particularly, the invention relates to a computer system capable of operating multiple virtual machines. 
         [0003]    A virtual machine allows single hardware to provide multiple computer systems, namely, a highly reliable, real-time computer system such as a control system and a high-performance computer system for audiovisual processing. 
         [0004]    The virtual machine includes virtual components such as a virtual central processing unit (CPU), virtualized physical memory, and a virtual IO device. The virtual machine implements the virtual components by allowing them to be dedicated to or share physical components (physical CPU, physical memory, and physical IO device). 
         [0005]    An abnormal state due to a device (hereinafter referred to as IO) error may occur under an environment that uses the virtual machine. For example, the method proposed in patent document 1 detects the error and prevent an abnormal state from expanding. The method provides an association table to associate IOs used for operating systems (OS&#39;s) and a means to detect IO errors, specifies a virtual machine from the association table corresponding to an error, if any, and stops only the specified virtual machine. 
         [0006]    A multithreaded processor is provided for computer systems such as control systems that require highly real-time capability. The multithreaded processor divides the processor usage time into predetermined time intervals or instructions and performs multiple processes by switching them. Since processes are switched during execution, the multithreaded processor can reliably ensure the time for real-time processing while performing audiovisual multimedia processes. For example, the method proposed in patent document 2 accelerates specific processes. The method uses multiple scheduling registers for a scheduling process of the multithreaded processor and changes ratios of threads available for normal operation and an interrupt process. 
         [0007]    For example, the method proposed in patent document 3 generates an interrupt via a bus bridge if an IO error causes an abnormal state. When an initialization instruction is issued to the OS or a device driver, the software such as the OS or the device driver reinitializes the communication control portion. 
         [0008]    Patent Document 1: Japanese Unexamined Patent Publication No. 2007-323142 
         [0009]    Patent Document 2: Japanese Unexamined Patent Publication No. 2010-86129 
         [0010]    Patent Document 3: Japanese Unexamined Patent Publication No. 2003-330817 
       SUMMARY 
       [0011]    The multithreaded processor as described in patent document 2 makes it easy to simultaneously control OS&#39;s running on multiple virtual machines. However, the following problem occurs when allowing the same hardware to run multiple OS&#39;s each of which is originally designed to run on distinct hardware. 
         [0012]    Suppose a case where an abnormal access from an OS (assumed to be OS-A) on the virtual machine may allow the corresponding IO (IO-A) to cause an error. In such a case, stopping OS-A can prevent an access to IO-A as described in patent document 1. An IO error can be recovered by notifying the error to OS-A as described in patent document 3. If an IO error occurs, however, the error on IO-A may propagate to a bus (bus x) coupled to IO-A. In this case, another OS (assumed to be OS-B) may use the other IO (IO-B) coupled to bus x and may access IO-B because OS-B does not recognize that bus x is faulty. As a result, OS-B may abnormally terminate. 
         [0013]    The present invention has been made to solve the above-mentioned problem. It is an object of the invention to provide a computer system capable of preventing a failure from propagating and recovering from the failure. 
         [0014]    To solve the shove-mentioned problem, the present invention provides a multithreaded processor and an interrupt controller to notify a bus error occurrence. The multithreaded processor includes: a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed; and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different OS&#39;s and include a first virtual CPU that operates a management OS to manage other OS&#39;s. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred. 
         [0015]    The invention can prevent a failure from propagating and recover from the failure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  illustrates a hardware configuration of the computer system according to a first embodiment; 
           [0017]      FIG. 2  illustrates a software configuration of the computer system according to the first embodiment; 
           [0018]      FIG. 3  is a flowchart illustrating a process to start the computer system according to the first embodiment; 
           [0019]      FIG. 4  is a flowchart illustrating a process to recover from an error on a bus  113  according to the first embodiment; 
           [0020]      FIG. 5  illustrates a software configuration of the computer system according to a second embodiment; 
           [0021]      FIG. 6  illustrates an IO-using OS management table; 
           [0022]      FIG. 7  is a flowchart illustrating a process to recover from an error on the bus  113  according to the second embodiment; 
           [0023]      FIG. 8  illustrates a software configuration of the computer system according to a third embodiment; 
           [0024]      FIG. 9  is a flowchart illustrating a process to start the computer system according to the third embodiment; 
           [0025]      FIG. 10  is a flowchart illustrating a process to generate a schedule according to the third embodiment if a bus error interrupt occurs; and 
           [0026]      FIG. 11  is a flowchart illustrating a process to recover from an error on the bus  113  according to the third embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    Embodiments of the present invention will be described with reference to the accompanying drawings. 
       First Embodiment 
     Hardware Configuration 
       [0028]      FIG. 1  illustrates a hardware configuration of the computer system according to the first embodiment. 
         [0029]    As illustrated in  FIG. 1 , the computer system includes a multithreaded processor  100 , an interrupt controller  101 , a main storage (memory)  102 , bus bridges  120 ,  121 , and  122 , IOs  131  through  135 , buses  110  through  113 . 
         [0030]    The multithreaded processor  100  performs multiple virtual CPUs by switching them from one to the others on a time basis. The software configuration to be described later will cover the multithreaded processor  100  in more detail. 
         [0031]    The interrupt controller  101  receives interrupt requests from the IOs  130  through  135 , the bus bridges  120  through  122 , and the main storage  102  and transmits the interrupt requests to the multithreaded processor  100 . The interrupt controller  101  may be included in the multithreaded processor  100 . Each interrupt factor may be given a priority and a VCPU number. 
         [0032]    The main storage  102  uses random access memory (RAM). The main storage  102  stores programs or data used for the multithreaded processor  100 . 
         [0033]    The bus  110  couples the multithreaded processor  100 , the interrupt controller  101 , the main storage  102 , and the bus bridges  120  and  121  with each other. 
         [0034]    The bus  111  couples the bus bridges  120  and  122 , and the IO  130 . 
         [0035]    The bus  112  couples the bus bridge  121 , and IOs  131  and  132 . 
         [0036]    The bus  113  couples the bus bridge  122 , and IOs  133  through  135 . 
         [0037]    The bus bridge  120  intermediates communication between the buses  110  and  111 . The bus bridge  120  detects an error on the bus  111  and notifies the error to the interrupt controller  101  coupled to the bus  110 . 
         [0038]    The bus bridge  121  intermediates communication between the buses  110  and  112 . The bus bridge  121  detects an error on the bus  112  and notifies the error to the interrupt controller  101  coupled to the bus  110 . 
         [0039]    The bus bridge  122  intermediates communication between the buses  111  and  113 . The bus bridge  122  detects an error on the bus  113  and notifies the error to the interrupt controller  101  coupled to the bus  110 . 
         [0040]    The IOs  130  through  135  represent a display, a control network, nonvolatile memory, a touch panel, a hard disk drive (HDD), and an audio device. While the embodiment shows an example of coupling these devices, some of them may be omissible. In addition, some of the other devices such as read only memory (ROM), a floppy disk drive (FDD), a Secure Digital (SD) memory card, a Compact Flash (CF, registered trademark) card, and a communication board (wired or wireless) may be coupled. 
         [0041]    The embodiment assumes that an error  140  occurs on the IO  134  and an error  141  occurs on the bus  113 . 
       Software Configuration 
       [0042]      FIG. 2  illustrates a software configuration of the computer system according to the first embodiment. 
         [0043]    VCPUs  220  through  222  represent virtual CPUs or schematic CPUs depicted as process images periodically performed by the multithreaded processor  100 . 
         [0044]    The multithreaded processor  100  is provided with schedule register A including multiple register groups. 
         [0045]    Schedule register A includes a sequence table and a register group. The sequence table specifies a sequence of virtual CPUs to be performed. The register group stores data used for the virtual CPU to be performed. According to the embodiment, the sequence table is configured to cyclically perform VCPU# 0 , VCPU# 1 , VCPU# 2 , and VCPU# 2  in order. VCPU# 0 , VCPU# 1 , and VCPU# 2  are provided with corresponding register groups. The embodiment describes that the multithreaded processor includes three register groups (VCPU# 0  through # 2 ). However, the multithreaded processor may include two register groups or more. 
         [0046]    A virtual CPU execution portion  201  includes a flag  202  indicating whether to select the schedule register. 
         [0047]    When the flag  202  is set, the virtual CPU execution portion  201  references the sequence table in the schedule register, changes a VCPU to be selected on a specified time or instruction basis, and selects a register group corresponding to the selected VCPU to perform the selected VCPU. 
         [0048]    When the flag  202  is reset, the virtual CPU execution portion  201  selects a register group corresponding to VCPU# 0  to perform VCPU# 0 . 
         [0049]    The interrupt controller  101  includes an interrupt notification portion  251 . 
         [0050]    The interrupt notification portion  251  receives an interrupt request that may be issued from the IOs  130  through  135 , the bus bridges  120  through  122 , or the main storage  102  if they encounter an error. The interrupt notification portion  251  transmits the interrupt request to the multithreaded processor  100 . 
         [0051]    VCPU# 0  operates a management OS  230  that manages the other OS&#39;s. VCPU# 0  performs programs running under the management OS  230  to function as an initialization processing portion  261 , a bus reinitialization portion  245 , an IO reinitialization request portion  244 , and an interrupt destination setup portion  240 . 
         [0052]    The initialization processing portion  261  performs processes for the management OS. 
         [0053]    The interrupt destination setup portion  240  provides settings for interrupts from the interrupt notification portion  251 . 
         [0054]    The IO reinitialization request portion  244  requests device reinitialization portions  241  and  242  to reinitialize related devices. 
         [0055]    VCPU# 1  operates a real-time (RT) OS  231 . VCPU# 1  performs programs running under the RTOS  231  to function as multiple control applications  255  and the device reinitialization portion  241 . 
         [0056]    The control application  255  performs a control function. 
         [0057]    The device reinitialization portion  241  performs processes to reinitialize devices used by VCPU# 1 . 
         [0058]    VCPU# 2  operates an audiovisual processing OS  232 . VCPU# 2  performs programs running under the audiovisual processing OS  232  to function as multiple audiovisual applications  243  and the device reinitialization portion  242 . 
         [0059]    The audiovisual application  243  performs audiovisual processes. 
         [0060]    The device reinitialization portion  242  performs processes to reinitialize IOs used by VCPU# 2 . 
       Operations 
       [0061]    The following describes operations of the computer system according to the first embodiment. 
         [0062]      FIG. 3  is a flowchart illustrating a process to start the computer system according to the first embodiment. VCPU# 0  starts the computer system. 
         [0063]    The initialization processing portion  261  normally initializes management OS  230  (S 300 ). 
         [0064]    The interrupt destination setup portion  240  configures error notification (issued from the bus bridges  120  through  122 ) from the buses  111  through  113  to be notified to the management OS  230  (S 301 ). 
         [0065]    The interrupt destination setup portion  240  configures the flag  202  to be disabled due to a bus error interrupt (S 302 ). 
         [0066]    The management OS then proceeds to normal operation. 
         [0067]      FIG. 4  is a flowchart illustrating a process to recover from an error on a bus  113  according to the first embodiment. 
         [0068]    If an error occurs on the bus  113 , the bus bridge  122  notifies the error occurrence to the interrupt controller  101 . The interrupt controller  101  notifies the multithreaded processor  100  of the interrupt (S 400 ). 
         [0069]    The interrupt notification portion  251  of the interrupt controller  101  disables the flag  202 . The virtual CPU execution portion  201  accordingly changes the operation of sequentially selecting VCPU# 0  through VCPU# 2  using schedule register A to the operation of only VCPU# 0  (S 401 ). At S 401 , VCPU# 1  and VCPU# 2  stop operating. 
         [0070]    The bus reinitialization portion  245  initializes the bus  113  (S 402 ). At S 402 , the error occurred on the bus  113  is removed. 
         [0071]    The IO reinitialization request portion  244  requests the RTOS  231  and the audiovisual processing OS  232  to reinitialize devices (S 403 ). 
         [0072]    The virtual CPU execution portion  201  sets the flag  202  to change the current operation to the operation of sequentially selecting VCPU# 0  through VCPU# 2  using schedule register A (S 404 ). At S 404 , VCPU# 1  and VCPU# 2  restart operating. 
         [0073]    The device reinitialization portion  241  reinitializes devices used by the RTOS  231  (S 405 ). The device reinitialization portion  242  reinitializes devices used by the audiovisual processing OS  232  (S 406 ). As a result, the bus and the devices coupled to the bus are restored to normal states. Thereafter, each OS returns to normal operation. 
       Effect 
       [0074]    According to the embodiment, all OS&#39;s stop when the bus is reinitialized. Therefore, the embodiment can safely remove a bus error. Even if the OS&#39;s do not complete a procedure of making a request to IOs (e.g., wait for DMA completion), requesting the OS&#39;s to reinitialize IOs ensures a repeated request to IOs. The OS can restart safely. 
       Second Embodiment 
     Hardware Configuration 
       [0075]    A hardware configuration of the computer system according to the second embodiment equals the hardware configuration according to the first embodiment and a description is omitted for simplicity. However, the hardware configuration of the computer system according to the second embodiment assumes that IOs (devices) used for the RTOS are coupled to buses other than those used for the remaining IOs (devices). 
       Software Configuration 
       [0076]      FIG. 5  illustrates a software configuration of the computer system according to the second embodiment. 
         [0077]    The software configuration according to the second embodiment differs from the software according to the first embodiment in the following. 
         [0078]    When a bus error occurs, the schedule change portion  547  references the current schedule register based on the IO-using OS management table  600  and changes the VCPU number to VCPU# 0  for operating the OS that uses a device (IO) coupled to the bus subject to the error. 
         [0079]      FIG. 6  illustrates the IO-using OS management table. 
         [0080]    The table shows the relationship in which each IO (column  601 ) is coupled to a coupling bus (column  602 ) and the OS (column  603 ) uses the corresponding IO. According to the embodiment, the table uses a blank cell and a white circle to indicate whether the bus is coupled. The table uses a blank cell and a black circle to indicate whether the IO is used. Alternatively, the table may use numbers (e.g., 0 and 1) for management. 
         [0081]    According to the IO-using OS management table, for example, the IO  130  is coupled to the bus  111  and uses the audiovisual processing OS. The IO  131  is coupled to the bus  112  and uses the RTOS. 
       Operations 
       [0082]    The following describes operations of the computer system according to the second embodiment. 
         [0083]    A procedure to start the computer system according to the second embodiment equals the first embodiment described with reference to  FIG. 3  and a description is omitted for simplicity. 
         [0084]      FIG. 7  is a flowchart illustrating a process to recover from an error on the bus  113  according to the second embodiment. 
         [0085]    If an error occurs on the bus  113 , the bus bridge  122  notifies the interrupt controller  101  of the error occurrence. The interrupt controller  101  notifies the interrupt to the multithreaded processor  100  (S 700 ). 
         [0086]    The interrupt notification portion  251  of the interrupt controller  101  disables the flag  202 . The virtual CPU execution portion  201  accordingly changes the operation of sequentially selecting VCPU# 0  through VCPU# 2  using schedule register A to the operation of only VCPU# 0  (S 701 ). At S 401 , VCPU# 1  and VCPU# 2  stop operating. 
         [0087]    The schedule change portion  547  references the IO-using OS management table  600  and extracts all OS&#39;s (only the audiovisual processing OS  232  in this example) that use IOs (IOs  133  through  135  in this example) coupled to the bus  113 . The schedule change portion  547  rewrites a virtual CPU (one or more of VCPU# 0  through VCPU# 2 ) running under the extracted OS&#39;s to VCPU# 0  in schedule register A (S 702 ). 
         [0088]    The schedule change portion  547  sets the flag  202  to change the current operation to the operation of sequentially selecting VCPUs using schedule register A (S 703 ). At S 703 , VCPU# 1  restarts operating. 
         [0089]    The bus reinitialization portion  245  initializes the bus  113  (S 704 ). At S 704 , the error occurred on the bus  113  is removed. 
         [0090]    The IO reinitialization request portion  244  requests the audiovisual processing OS  232  to reinitialize devices (S 705 ). 
         [0091]    The schedule change portion  547  changes the VCPU (VCPU# 0  from VCPU# 2  in this example) changed in a schedule register at S 702  to the original state (S 706 ). In this example, the schedule change portion  547  returns the changed VCPU# 0  to VCPU# 2 . At S 706 , VCPU# 1  restarts operating. 
         [0092]    The device reinitialization portion  242  reinitializes a device used for the audiovisual processing OS  232 . As a result, the bus and the devices coupled to the bus are restored to normal states. Thereafter, the audiovisual processing OS  232  returns to normal operation. 
       Effect 
       [0093]    As described above, the embodiment reinitializes a bus by stopping all OS&#39;s related to the bus and is therefore capable of safely removing a bus error. In addition, OS&#39;s unrelated to the bus can continue operating. The real-time process can restart earlier than the first embodiment. Even if the OS related to the bus does not complete a procedure of making a request to IOs (e.g., wait for DMA completion), requesting that OS to reinitialize IOs ensures a repeated request to IOs. The OS can restart safely. 
       Third Embodiment 
     Hardware Configuration 
       [0094]    A hardware configuration of the computer system according to the third embodiment equals the hardware configuration according to the first embodiment and a description is omitted for simplicity. However, the hardware configuration of the computer system according to the third embodiment assumes that IOs (devices) used for the RTOS are coupled to buses other than those used for the remaining IOs (devices). 
       Software Configuration 
       [0095]      FIG. 8  illustrates a software configuration of the computer system according to the third embodiment. 
         [0096]    The multithreaded processor  1200  includes schedule registers A, B, and C. 
         [0097]    The schedule registers A, B, and C each include a sequence table and a register group. The sequence table specifies a sequence of virtual CPUs to be performed. The register group stores data used for the virtual CPU to be performed. 
         [0098]    The sequence table of schedule register A is configured to cyclically perform VCPU# 0 , VCPU# 1 , VCPU# 2 , and VCPU# 2  in order. VCPU# 0 , VCPU# 1 , and VCPU# 2  are provided with corresponding register groups. 
         [0099]    The sequence table of schedule register B is configured to cyclically perform VCPU# 0 , VCPU# 1 , VCPU# 0 , and VCPU# 0  in order. VCPU# 0  and VCPU# 1  are provided with corresponding register groups. 
         [0100]    The sequence table of schedule register C is configured to cyclically perform VCPU# 0 , VCPU# 0 , VCPU# 2 , and VCPU# 2  in order. VCPU# 0  and VCPU# 2  are provided with corresponding register groups. 
         [0101]    A schedule generation portion  1248  generates a schedule based on the IO-using OS management table  600  so as not to schedule an OS related to the bus error occurrence. The example enables schedule registers B and C. 
         [0102]    A virtual CPU execution portion  1201  changes schedule registers to be selected in response to an interrupt request from the interrupt controller  101  or a request from the OS (software). 
       Operations 
       [0103]    The following describes operations of the computer system according to the third embodiment. 
         [0104]      FIG. 9  is a flowchart illustrating a process to start the computer system according to the third embodiment. VCPU# 0  starts the computer system. 
         [0105]    The initialization processing portion  261  normally initializes management OS  230  (S 1400 ). 
         [0106]    The schedule generation portion  1248  enables a schedule register used when a bus error interrupt occurs (S 1401 ). 
         [0107]    The interrupt destination setup portion  240  configures error notification (issued from the bus bridges  120  through  122 ) from the buses  111  through  113  to be notified to the management OS  230  (S 1402 ). 
         [0108]    The management OS then proceeds to normal operation. 
         [0109]      FIG. 10  is a flowchart illustrating a process to generate a schedule according to the third embodiment if a bus error interrupt occurs. The following description provides an example and the other different schedule generation algorithms may be available without departing from the spirit and scope of the invention. 
         [0110]    Steps S 1501  through S 1502  are repeated for the number of buses in the bus list (S 1500 ). 
         [0111]    The schedule generation portion  1248  references the IO-using OS management table  600  and specifies an IO coupled to the selected bus. According to the example, the schedule generation portion  1248  specifies the IO  130  and the bus bridge  122  when the bus  111  is selected. The schedule generation portion  1248  specifies an OS using these IOs (S 1501 ). According to the example, the schedule generation portion  1248  specifies only an audiovisual processing OS  1232 . 
         [0112]    The schedule generation portion  1248  generates a schedule in schedule register A as the standard schedule register to change VCPU#X to VCPU# 0 . VCPU#X allows the specified OS to operate and represents one or more of VCPU# 0  through VCPU# 2 . According to the example, VCPU# 2  is changed to VCPU# 0 . The schedule generation portion  1248  adds the schedule to a virtual CPU execution schedule  1510 . 
         [0113]    After S 1500 , the virtual CPU execution schedule  1510  contains as many schedules as the number of buses in the bus list. 
         [0114]    The schedule generation portion  1248  removes duplicate schedules from the virtual CPU execution schedule  1510  (S 1503 ). 
         [0115]    The schedule generation portion  1248  supplies schedules in the virtual CPU execution schedule  1510  to the schedule registers (schedule registers B and C in this example). The schedule generation portion  1248  supplies the schedule registers to the virtual CPU execution portion  201  so that the schedule registers are selected if a bus error occurs (S 1504 ). 
         [0116]      FIG. 11  is a flowchart illustrating a process to recover from an error on the bus  113  according to the third embodiment. 
         [0117]    If an error occurs on the bus  113 , the bus bridge  122  notifies the error occurrence to the interrupt controller  101 . The interrupt controller  101  notifies the interrupt to the multithreaded processor  1200  (S 1600 ). 
         [0118]    The virtual CPU execution portion  1201  selects a schedule register (schedule register B in this example) corresponding to the bus causing the error and changes the execution schedule (S 1601 ). At S 1601 , the audiovisual processing OS  232  stops operating. 
         [0119]    The bus reinitialization portion  245  reinitializes the bus  113  (S 1602 ). S 1602  removes the error occurred on the bus  113 . 
         [0120]    The IO reinitialization request portion  244  requests the audiovisual processing OS  232  to reinitialize devices (S 1603 ). 
         [0121]    The virtual CPU execution portion  201  changes the schedule register to be used to the standard schedule register (schedule register A) and changes the execution schedule (S 1604 ). At S 1604 , the audiovisual processing OS  1232  restarts operating. 
         [0122]    The device reinitialization portion  242  reinitializes devices used for the audiovisual processing OS  232  (S 1605 ) and restores the bus and devices coupled to the bus to normal states. The audiovisual processing OS  232  then returns to normal operation. 
       Effect 
       [0123]    As described above, the embodiment reinitializes a bus while stopping all OS&#39;s related to the bus. A bus error can be removed safely. Even if the OS related to the bus does not complete a procedure of making a request to IOs (e.g., wait for DMA completion), requesting that OS to reinitialize IOs ensures a repeated request to IOs. The OS can restart safely. In addition, OS&#39;s unrelated to the bus can continue operating. The recovery process is available without stopping the real-time process. 
         [0124]    The disclosed embodiments are examples in all aspects and should not be considered restrictive. The scope of the invention is shown in the appended claims, not in the above-mentioned description, and is intended to include meanings equivalent to the claims and all changes in the claims.