Abstract:
A CMOS light sensor and the operation method thereof are disclosed. The CMOS light sensor has a plurality of light sensing lines and a plurality of capacitor lines. Each light sensing line has a plurality of light sensors such that the number of capacitors in each capacitor line is smaller than the number of light sensing cells in each light sensing line. The capacitors are used for holding a portion of the potentials produced by the light sensing cells due to illumination. The method of operating the CMOS light sensor includes transferring the data captured by the light sensing line to the capacitor line and reading out the data according to a pre-defined order so that the leakage of charges from the capacitor is reduced.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority benefit of Taiwan application serial no.91116948, filed on Jul. 30, 2002. 
     BACKGROUND OF INVENTION 
     1. Field of Invention 
     The present invention relates to a CMOS light sensor and the operation method thereof. More particularly, the present invention relates to a CMOS light sensor and operation method that uses segment processing. 
     2. Description of Related Art 
     Most light sensors are classified into two major types, a charge-coupled device (CCD) or a CMOS light sensor. In a conventional CCD sensor, each light sensing line is assigned a group of shift registers for holding the charges produced by the CCD sensing line. In general, the amount of charges produced by the CCD sensor depends on the strength of illumination. Once the charges are fully transferred to the shift registers, the charges are sequentially shifted away from the shift registers to the circuit in the next processing stage. Similarly, as shown in  FIG. 1 , each CMOS light sensor  10  has a plurality of light sensing lines ( 12   a ,  14   a  and  16   a ) and each has a functional element similar to the shift register in the charge couple device. However, instead of shift registers, these functional elements are capacitors. 
     The structure of the CMOS light sensor  10  and the conventional CCD sensor are almost identical except the deployment of a capacitor in the former instead of a shift register. Hence, the method of operating the CMOS light sensor  10  is very similar to the method of operating the CCD sensor. The CMOS sensor  10  is exposed to light so that the sensing cells (such as  120   a ,  122   a ,  140   a ,  142   a ,  160   a  and  162   a ) in the light sensing lines ( 12   a ,  14   a  and  16   a ) generate an amount of electric charges in proportional to the intensity of illumination. Thereafter, various sensor cells (such as  120   a ,  122   a ,  136   a  and  138   a ) within the same light sensing line (such as  12   a ) are sampled individually to reproduce a corresponding electric potential. The capacitors within the aforementioned capacitor line (such as  12   b ) are actually storage device for registering the sampled electric potential. 
     In general, the capacitor line registers the resultant electric potentials produced by the entire light sensing line all at once but the electric potentials within the capacitor line are read out sequentially. Therefore, time to read out all of the potentials within the capacitor line increases with the number of sensor cells in a light sensing line. Since charge leakage occurs on most capacitors, the total number of charges drained away from the capacitor increases with time. If too many charges leak away from the capacitor, the actual stored data (electric potential) may be seriously distorted. 
     SUMMARY OF INVENTION 
     Accordingly, one object of the present invention is to provide a CMOS light sensor and operation method thereof. The CMOS light sensor has a capacitor line with a count of capacitors smaller than the count of light sensing cells in a light sensing line. Hence, all the data produced by the light sensing line can be read out in a few reading operations. Ultimately, data retaining period of data within each capacitor is shortened considerably when compared with a conventional technique. 
     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a CMOS light sensor. The CMOS light sensor has a light sensing line and a capacitor line. The light sensing line has a plurality of light sensing cells. The count of capacitors in the capacitor line is smaller than the count of light sensing cells in the light sensing line. The capacitors along the capacitor line store up a portion of the potentials produced by the light sensing cells along the light sensing line. 
     This invention also provides an alternative CMOS light sensor. The CMOS light sensor has a plurality of light sensing lines and a group of capacitor lines. Each light sensing line has a plurality of light sensing cells and each group of capacitor lines has at least one capacitor line. The count of capacitors in each capacitor line is smaller than the count of light sensing cells in each light sensing line. Furthermore, the potentials produced by the light sensing cells in each light sensing line is transferred in sequence to the capacitor lines in the capacitor line group. 
     This invention also provides a method of operating a CMOS light sensor. A portion of the light sensing cells in the CMOS light sensor is illuminated to produce a corresponding set of electric charges. Thereafter, the set of unprocessed charges produced by the illuminated light sensing cells is converted into a set of corresponding potentials and transferred to the capacitors on a capacitor line. Finally, the potentials stored in the capacitors of the capacitor line are read out. 
     In one embodiment of this invention, the CMOS light sensor has a plurality of capacitor lines. When the stored potentials inside one of the capacitor lines is read, a set of unprocessed charges produced by the illuminated light sensing cells is converted into a set of corresponding potentials and transferred to any of the capacitor lines other than the one involved in the reading operation. The potentials in these other capacitor lines are subsequently read according to a pre-defined sequence. 
     In brief, this invention uses a capacitor line having a count of capacitors smaller than the count of light sensing cells in a light sensing line. Therefore, the time for reading out all the potentials from the capacitors along a capacitor line is shortened. With considerably reduction in reading time, the amount of charges leaking out from each capacitor is minimized and hence the degree of data distortion is reduced considerably. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
         FIG. 1  is a schematic diagram showing the relationship between the light sensing lines and the capacitor lines in a conventional CMOS light sensor; 
         FIG. 2  is a schematic diagram showing the relationship between the light sensing lines and the capacitor lines in a linear CMOS light sensor according to one preferred embodiment of this invention; 
         FIG. 3  is a schematic diagram showing the relationship between the light sensing lines and the capacitor lines in a staggered CMOS light sensor according to a first preferred embodiment of this invention; 
         FIG. 4  is a schematic diagram showing the relationship between the light sensing lines and the capacitor lines in a staggered CMOS light sensor according to a second preferred embodiment of this invention; 
         FIG. 5  is a schematic diagram showing the relationship between the light sensing lines and the capacitor lines in a staggered CMOS light sensor according to a third preferred embodiment of this invention; 
         FIG. 6  is a timing diagram showing the operating sequence of a CMOS light sensor system having a single capacitor line and at least one light sensing line therein according to one preferred embodiment of this invention; 
         FIG. 7A  is a schematic diagram showing a CMOS light sensor system having a multiple of capacitor lines that correspond to a single light sensing line according to one preferred embodiment of this invention; and 
         FIG. 7B  is a timing diagram showing the operating sequence of the CMOS light sensor system in  FIG. 7A . 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
       FIG. 2  is a schematic diagram showing the relationship between the light sensing lines and the capacitor lines in a linear CMOS light sensor according to one preferred embodiment of this invention. As shown in  FIG. 2 , the CMOS light sensor  20  includes three light sensing lines  22   a ,  24   a ,  26   a  for sensing the three primary colors red (R), green (G) and blue (B) respectively. In addition, the CMOS light sensor  20  also includes three capacitor lines  22   b ,  24   b ,  26   b  for holding potentials produced by the respective light sensing lines  22   a ,  24   a  and  26   a . The operational relationship between the three light sensing lines  22   a ,  24   a ,  26   a  and the three corresponding capacitor lines  22   b ,  24   b ,  26   b  are identical. Hence, the operation of only one group of light sensing line and corresponding capacitor line is explained in the following. 
     In this embodiment, the number of capacitors  221   b ˜ 225   b  in the capacitor line  22   b  is set to one third of the number of light sensing cells  221   a ˜ 235   a  along the light sensing line  22   a . Obviously, the ratio of the number of light sensing cells to the number of capacitors can be varied according to actual application. Since the total number of capacitors  221   b ˜ 225   b  in the capacitor line  22   b  is only one third that of the number of light sensing cells  221   a ˜ 235   a , data must be extracted in stages from the light sensing cells  221   a ˜ 235   a . The following is a more detailed description of the operation relationship between the light sensing line  22   a  and the capacitor line  22   b.    
     Since the number of capacitors  221   b ˜ 225   b  is only one third of the amount of the light sensing cells  221   a ˜ 235   a , the potentials produced by the light sensing cells  221   a ˜ 235   a  must be transferred into the capacitor line step by step. Because the potential within the sensing cells  221   a ˜ 235   a  are transferred to the capacitor line  22   b  in three separate steps, sectional illumination of the CMOS light sensor is preferable. In other words, the light sensing cells  221   a ˜ 225   a  are illuminated first followed by the light sensing cells  226   a ˜ 230   a  and then the light sensing cells  231   a ˜ 235   a  or some other arrangements for these three segments of light sensing cells. Obviously, an alternative arrangement such as illuminating the light sensing cells  221   a ˜ 235   a  all at once and shifting the resulting potentials into the capacitor line  22   b  in sequence is also possible. However, this will increase overall leakage of charges from the sensing cells  221   a ˜ 235   a  and lead to a greater data distortion. Whether the CMOS light sensor is illuminated once or in a multiple of exposures, once a set of charges is produced inside the light sensing cells  221   a ˜ 235   a  within the light sensing line  22   a , the set of charges are converted into electric potentials and stored inside the capacitor line  22   b . Thereafter, each potential inside the capacitor line is sequentially read to obtain the required image data. 
       FIGS. 3 ,  4 ,  5  are schematic diagrams showing the relationship between the light sensing lines and the capacitor lines in a staggered CMOS light sensor according to this invention. In  FIGS. 3 and 4 , only one of the three groups (including the capacitor line that corresponds to the light sensing line) of light sensing lines (R, G, B) is shown. Since the remaining two groups of light sensing lines are identical with the one shown in the Figures, their structures are not drawn. In  FIG. 3 , a light sensing line  32   a  is used to capture the intensity of a particular color in the odd pixels of a scan line while another light sensing line  34   a  is used to capture the intensity of the same color in the even pixels of the scan line. The capacitor lines  32   b  and  34   b  are used to hold the potentials after converting the charges that result from the intensity of illumination of the particular color on the light sensing lines  32   a  and  34   a . In  FIG. 4 , both light sensing lines  42  and  44  correspond with one capacitor line  46 . In other words, the capacitor line  46  not only stores the resultant potentials captured by the light sensing line  44 , but also stores the resultant potentials captured by the light sensing line  42  as well. 
     In the embodiment of  FIG. 5 , two capacitor lines  56  and  58  are utilized by light sensing lines  52   r  and  54   r  used for sensing red color, light sensing lines  52   g  and  54   g  used for sensing green color and light sensing lines  52   b  and  54   b  used for sensing blue color. For example, the capacitor line  56  may serve as a storage area for holding the potentials of odd pixels captured by the light sensing lines  52   r ,  52   g  and  52   b  for various colors. Similarly, the capacitor line  58  may serve as a storage area for holding the potentials of even pixels captured by the light sensing lines  54   r ,  54   g  and  54   b  for various colors. If the number of capacitors in the capacitor line  56  is one-third the number of light sensing cells in a single light sensing line ( 52   r ,  52   g  or  52   b ), all the potentials captured by the light sensing lines  52   r ,  52   g  and  52   b  must be read nine readout operations. Under the same token, all the potentials captured by the light sensing lines  54   r ,  54   g  and  54   b  must be read in nine readout operations. Obviously, this is not the only arrangement for the light sensing lines and the capacitor lines. Persons skilled in the art may change the arrangement to produce optimal results. 
     After explaining a few light sensing line capacitor line configurations, methods of operating the CMOS light sensor are described below.  FIG. 6  is a timing diagram showing the operating sequence of a CMOS light sensor system which has a single capacitor line and at least one light sensing line therein. The light sensing line  22   a  and the capacitor line  22   b  shown in  FIG. 2  are used as an example for illustrating the timing diagram in  FIG. 6 . The clocking signal CK_ 1  in  FIG. 6  is a signal for controlling the light sensing line  22   a  and the capacitor line  22   b . When the clocking signal CK_ 1  is at high potential, potentials captured by the light sensing line  22   a  are transferred to the capacitors in the capacitor line  22   b . As the clocking signal CK_ 1  drops to low potential, the potentials stored inside the capacitors are sequentially read out from the capacitor line  22   b . With this type of timing control, potentials resulted from illuminating the light sensing line  22   a  are read out in three separate sessions, namely, session one for reading data  602 , session two for reading data  604  and session three for reading data  606 . Although this is an arrangement capable of saving a few capacitors in a CMOS light sensor, each data reading session must be punctuated by an idling period t 1 . This idling period t 1  is required for transferring the electric potential from the light sensing line  22   a  to the capacitor line  22   b . Obviously, the aforementioned arrangement implies that the entire light sensing line  22   a  is illuminated all at once and then the generated potentials are transferred in separate sessions. If the light sensing line  22   a  is illuminated in several stages, an exposure time period must also be added to the idling time t 1 . 
     To reduce idling time caused by non-successive data transmission, this invention also provides a CMOS light sensor having a plurality of capacitor lines that correspond to a light sensing line.  FIG. 7A  is a schematic diagram showing a CMOS light sensor system having a multiple of capacitor lines that correspond to a single light sensing line according to one preferred embodiment of this invention. Since the light sensing lines and corresponding capacitor lines for each primary color are the same, only a group that includes a light sensing line  70  and a pair of capacitor lines  73  and  75  is illustrated in detail. The potentials gathered by the light sensing line  70  due to illumination are transferred to the capacitor lines  73  and  75 . In this embodiment, the number of capacitors within the capacitor lines  73  and  75  is one-fourth the number of light sensing cells in the light sensing line  70 . However, persons skilled in the art may arrange the relative number of capacitors and light sensing cells in any ratio that can optimize overall performance. 
       FIG. 7B  is a timing diagram showing the operating sequence of the CMOS light sensor system in  FIG. 7A . In  FIG. 7B , a clocking signal CK_ 2  is used for controlling the capacitor line  73  and a portion of the light sensing line  70  and another clocking signal CK_ 3  is used for controlling the capacitor line  75  and another portion of the light sensing line  70 . For example, when the clocking signal CK_ 2  is at high potential, the potentials gathered by the light sensing cells  701 ˜ 705  or  711 ˜ 715  (as shown in  FIG. 7A ) due to exposure are transferred to the capacitor line  73 . When the clocking signal CK_ 2  drops back to low potential, the potential values are sequentially read from the capacitor line  73  via the end-stage circuit  74 . Similarly, when the clocking signal CK_ 3  is at high potential, the potentials gathered by the light sensing cells  706 ˜ 710  or  716 ˜ 720  (as shown in  FIG. 7A ) due to exposure are transferred to the capacitor line  75 . When the clocking signal CK_ 3  drops back to low potential, the potential values are sequentially read from the capacitor line  75  via the end-stage circuit  74 . With this arrangement, as long as a proper data length is selected, the data  760 ,  772 ,  762 ,  774  and  764  are linked together to form a continuous data stream. Ultimately, the type of interruption caused by transferring data using a single capacitor line can be avoided. 
     In summary, this invention provides a means to reduce the time for reading out data stored inside the capacitor line. Hence, the effect charge leakage from the capacitors is greatly minimized. In addition, this invention also provides a structure that uses a plurality of capacitor lines which correspond with a light sensing line and a method of operating this structure. Consequently, very little time is wasted between data transmission and overall operating efficiency of the CMOS light sensor is improved. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.