Abstract:
A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer.

Description:
[0001]    This is a divisional application of U.S. patent application Ser. No. 11/528,877, filed on Sep. 28, 2006, which is herein incorporated by reference in its entirety, and assigned to a common assignee. 
         [0002]    This application is related to U.S. patent application Ser. No. 11/215,276, filed on Aug. 30, 2005 and since issued as U.S. Pat. No. 7,265,404 on Sep. 4, 2007, and herein incorporated, by reference, in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0003]    The invention relates to the general field of magnetic tunnel junctions (MTJs) with particular reference to the bottom electrode located between them and the inter-layer dielectric (ILD) of an integrated circuit. 
       BACKGROUND OF THE INVENTION 
       [0004]    Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with Magnetic Tunnel Junction (MTJ)s, is a major emerging technology, highly competitive with existing semiconductor memories (SRAM, DRAM, Flash etc). The MTJ consists of two ferromagnetic layers separated by a thin dielectric layer. Magnetization of the two ferromagnetic layers can be arranged to be in either parallel (low resistance) or anti-parallel (high resistance) magnetization states, representing “1” and “0” respectively, 
         [0005]    The MTJ memory cells are usually inserted at the back end of a standard CMOS process. The high-speed version of MRAM architecture consists of a cell with an access transistor and a MTJ (1T1MTJ) in the array. The MTJ element is formed on top of the bottom conductor line, which is used to connect the base of the MTJ to the access transistor. Switching of the free layer magnetization in the MTJ device is accomplished by applying currents to orthogonal conductor lines. 
         [0006]    The conductors are arranged in a cross-point architecture that provides the field for selectively switching each bit. One line (bit line) provides the field parallel to the easy axis of the bit, while another line (write word line) provides the perpendicular (hard axis) component of the field. The intersection of the lines generates a peak field that is engineered to be just above the switching threshold of that MTJ. For high performance MTJ devices, the separation between the write word line (bit line) and MTJ free layer is made as small as possible. 
         [0007]    In a read operation, the read word line (RWL) is selected, and the transistor is turned on. This causes the MTJ device to be connected to ground. At this time, a sense current passes through the BL-MTJ-BE and to ground. The resistance of the MTJ device is low when the MTJ is storing a 1 and high when it is storing a 0. 
         [0008]    Referring now to  FIG. 1   a,  shown there is tantalum hard mask  15  which will be used to separate MTJ sheet stack  16  into individual devices, each resting on a bottom electrode that comprises material from layer  17  which rests on SiN ILD  11 . Also seen (though not relevant to the invention) are vias  18 . In  FIG. 1   b,  layer  16  has been patterned into individual MTJ devices  4 , with Ta mask  15  having been partly consumed during the etch operation. In  FIG. 1   c  bottom electrode layer  17  has also been patterned into individual electrodes. However, in the course of making certain that said electrodes are truly electrically isolated one from another, ILD layer has been over etched so that its top surface has been partly eroded, as symbolized by its being shown as a broken line in the figure. 
         [0009]    Reactive ion etching (RIE) has been preferred over IBE (ion beam etching) as the method for etching layer  17 . However, vertical features created by IBE always have an extended slope on the edge, which not only could creates electrical shorting problems but also limits further reduction of line width and make it impossible to make very high density IC device. In general, RIE is considered a better approach to creating well-defined three dimensional micro-features but there are several major problems currently associated with the RIE process:
   (I) The uncontrollable over etch mentioned above is due to the lack of etching selectivity between the bottom electrode and the ILD.  FIG. 2  illustrates the structure of layer  17  in greater detail—immediately on ILD  11  is TaN layer  12  on which is alpha tantalum layer  13 . Layer  14  comprises a second TaN layer.   (2) This etching process always results in a large amount of re-deposition all over the surface of the device due to the non-volatility of the reaction products.   (3) The MTJ will experience two etching processes (first in its own etch and then during the BE etch). This not only affects the MTJ&#39;s overall dimensions, but also results in serious damage to the edge of the MTJ&#39;s tunnel barrier layer.   
 
         [0013]    A routine search of the prior art was performed with the following references of interest being found:
   U.S. Pat. No. 6,974,708 (Horng et al) discloses OSL on top of the bottom electrode.   U.S. Pat. No. 6,703,654 (Horng et al) teaches a NiCr/Ru bottom electrode.   U.S. Pat. No. 6,960,48 (Horng et al) discloses a bottom electrode of /NiCr/Ru/α-Ta.   U.S. Patent Application 2005/0254293 (Horng et al) teaches layers comprising NiCr/Ru/αTa.   U.S. Patent Application 2005/0016957 (Kodaira et al), the Anelva Co., shows dry etching using CH 3 OH.   U.S. Patent Application 2006/0002184 (Hong et al) teaches bottom electrodes of NiCr/Ru/Ta or NiCr/Ru/α-TaN.   
 
       Additional References of Interest Are: 
       [0000]    
       
         1. S. Tehrani et. al. “Magnetoresistive Random Acess Memory using Magnetic tunnel junction” Proceeding of the IEEE. Vol. 91, p 703-712, 2003. 
         2. C. Horng et. al. HTO3-022 “A novel structure/method to fabricate a high performance magnetic tunneling junction MRAM”. Magic touch and NiCr/Ru/alpha-Ta. 
         3. “Nanoscale MRAM elements” (including an extensive review of RIE),—S. J. Peraton and J. R. Childress (IBM and U of F). 
       
     
       SUMMARY OF THE INVENTION 
       [0023]    It has been an object of at least one embodiment of the present invention to provide a process for forming a bottom electrode for an MTJ stack on a silicon nitride substrate in such a way as to minimize any possible surface damage to said substrate. 
         [0024]    A further object of at least one embodiment of the present invention has been that said substrate also serve as an ILD of an associated integrated circuit and that said ILD have a thickness no greater than about 500 Å thereby facilitating it proximity to a word line of said integrated circuit. 
         [0025]    Another object of at least one embodiment of the present invention has been that said bottom electrode have good electrical conductance. 
         [0026]    Still another object of at least one embodiment of the present invention has been that said MTJ stack have vertical, or near vertical, sidewalls and be spaced no more than about 0.3 microns from neighboring MTJ stacks. 
         [0027]    Yet another object of at least one embodiment of the present invention has been that said process not damage the edges of the tunnel barriers of said MTJ stacks. 
         [0028]    These objects have been achieved by including a layer of ruthenium as one of the layers that make up the bottom electrode. The ruthenium serves two purposes. First, it is a good electrical conductor. Second, it responds differently from Ta and TaN to certain etchants that may be used to perform RIE. Specifically, ruthenium etches much more slowly than Ta or TaN when exposed to CF 4  while the reverse is true when CH 3 OH is used. Furthermore, silicon nitride is largely immune to corrosion by CH 3 OH, so removal of a ruthenium layer at, or near, the silicon nitride surface can be safely performed. 
         [0029]    This differential etch behavior allows an included layer of ruthenium to be used as an etch stop layer during the etching of Ta and/or TaN while the latter materials may be used to form a hard mask for etching the ruthenium. 
         [0030]    A problem of the prior art has been the relatively poor adhesion of ruthenium to silicon nitride. This problem has been overcome by inserting a bilayer of NiCr on TaN as the ‘glue’ between the Ru and the SiN. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIGS. 1   a - 1   c  show the prior art process for forming a bottom electrode for an MTJ stack. 
           [0032]      FIG. 2  illustrates the layer structure of an MTJ bottom electrode of the prior art. 
           [0033]      FIG. 3  illustrates the layer structure of an MTJ bottom electrode as used in the first embodiment of the present invention. 
           [0034]      FIG. 4  shows the structure seen in  FIG. 3  after CF 4  etching during which the Ru layer acts as an etch stop. 
           [0035]      FIG. 5  shows the structure seen in  FIG. 4  after CH 3 OH etching to remove Ru with minimum corrosion of the SiN substrate. 
           [0036]      FIG. 6  shows the starting point for the process of the second embodiment of the invention. 
           [0037]      FIG. 7  illustrates a key feature of the second embodiment, namely a protective coating that is partly consumed during etching of the alpha tantalum portion of the bottom electrode, 
           [0038]      FIG. 8  illustrates the patterning of the protective coating prior to etching down to the level of the ruthenium. 
           [0039]      FIGS. 9 and 10  show the final process steps whereby the SiN substrate on which the bottom electrodes lies suffers minimal corrosion after it is exposed and, furthermore, an amount of the protective coating is still present and is thus able to provide permanent protection to the structure. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0040]    The invention discloses a novel bottom conductor layer structure that is smooth, flat, and has low resistance. In the first embodiment, the bottom conductor layer structure is NiCr30/Ru20/α-Ta120/TaN150. In the second embodiment, the bottom conductor layer structure is typically TaN/NiCr3/Ru30/α-Ta120/TaN150. The total thickness of these bottom conductor structures is 300 Å (as in the prior art). RIE of these bottom conductor layers is first achieved using an etchant of the CF 4  type to remove the top TaN/Ta layer, which is followed by an etchant of the CH 3 OH type to etch the ruthenium. 
         [0041]    In MTJ structures, topological roughness of the magnetic layers causes ferromagnetic coupling (Neel coupling) to shift the hysteresis loop. To minimize this inter-layer coupling effect, it is critical to form the MTJ stack on a flat/smooth bottom conductor. An example of a MTJ configuration that results in a high performance MTJ is: 
         [0000]    
       
                 
         
             
             
         
       
     
         [0042]    where S.E.=sputter etch 
         [0043]    It is known that Ta formed on top of Ru grows in its a low resistance alpha-Ta phase. The high performance MTJ is formed on top of NiCr50/Ru100/Ta150 bottom conductor. The disclosed NiCr30/Ru20/Ta100/TaN150 bottom conductor of this invention is very flat and smooth (typically having a roughness value less than about 2 Å). The TaN150 cap is used here to protect Ta from oxidation. For the process to yield a high performance MTJ, this TaN cap is sputter-etched to a 30 Å thickness of the exposed TaN top layer. 
         [0044]    When using a photoresist mask, the etching selectivity for Ta (TaN)/Ru by CF 4 -RIE is around 10. Thus in the process of using RIE to pattern the NiCr30/Ru30/Ta100/TaN150 bottom conductor, the top Ta/TaN is subjected to CF 4  gas chemistry which is largely ineffective at the Ru surface. After photoresist strip, the etchant is then changed to CH 3 OH to etch the remaining Ru/NiCr. Ru etch rate is about same as SiN and NiCr etch rate is about 0.5 of SiN. Since the NiCr/Ru seed layer is much thinner than ILD SiN (50 Å vs 300 Å), even with a 100% over-etch of the Ru30/NiCr30 layers, over-etching into the SiN would amount to less than 50 Å. In contrast, for CF 4 -RIE of the TaN50/Ta100/TaN150 (as used in the prior art), a 100% over-etch would result in the removal of over 300 Å of the SiN ILD. 
         [0045]    For the first embodiment, as an alternative to the use of NiCr as a ‘glue’ layer, a special treatment of the SiN substrate surface may be used instead: 
         [0046]    Sputter-clean SiN/OSL/Ru30/α-Ta120/TaN150 
         [0047]    where OSL stands for oxygen surfactant layer. When OSL is used to treat the SiN surface, SiOxyNitride/RuO is formed at the SiN/Ru interface which then promotes good adhesion. 
         [0048]    We now provide a description of the processes used to manufacture the two embodiments of the invention: 
       1 st  Embodiment 
       [0049]    Referring now to  FIG. 3 , the process starts with sputter cleaning of the surface of substrate layer  11 , followed by depositing thereon layer of NiCr  10  onto which is deposited ruthenium layer  31  to a thickness between about 20 and 30 Angstroms. This is followed by the deposition, to a thickness between about 100 and 200 Angstroms, of alpha tantalum layer  32  (on ruthenium layer  31 ). Next, tantalum nitride layer  12  is deposited on layer of alpha tantalum  32  (to a thickness between about 100 and 150 Angstroms). 
         [0050]    Now follows a critical feature of the invention which is the process used to etch the bottom electrode sheet (layers  12 / 32 / 31 / 11 ) into individual bottom electrodes without, at the same time, significantly penetrating silicon nitride substrate  11 . This is accomplished in two main steps, as follows: 
         [0051]    Referring now to  FIG. 4 , photoresist mask  41 , that defines the required multiple electrode shapes, is formed on the upper surface of layer  12 . Then, a first reactive ion etching step is performed, using as the etchant one of several possible gaseous compounds of carbon and fluorine, such as CF4, CHF 3  etc., with CF 4  being preferred. Etching of all unprotected areas now proceeds at a rate of about 80 nm/min. and layers  12 , and  32  are successively removed (where there is no photoresist). When however, layer  31  of ruthenium becomes exposed, the etch rate falls off substantially—typically by a factor of about one 10 th , at which point reactive ion etching may be terminated “at leisure” with no danger of etching through ruthenium layer  31  and penetrating silicon nitride substrate  11 . The appearance of the structure is now as shown in  FIG. 4  with arrow  42  pointing to the region of separation between two individual bottom electrodes. 
         [0052]    Now moving to  FIG. 5 , all remaining photoresist has been removed. At this point a second reactive ion etching process is initiated. In this case the etchant used is one of several possible gaseous compounds of carbon, oxygen, and hydrogen, such as CH 3 OH, CO+N H 3 , C 2 H 5 OH, etc., with CH 3 OH being preferred. No additional photoresist is required. Instead the previously etched layer  12  acts as a hard mask during the etching of layers  31  and  10 . Etching of all exposed ruthenium surfaces now proceeds at a rate of about 8 nm/min. until silicon nitride layer  11  is exposed, at which point the second reactive ion etching process may be terminated, also “at leisure”, with no danger of penetrating silicon nitride substrate  11  by more than about 60 Angstroms. The appearance of the structure is now as shown in  FIG. 5 . 
       2 nd  Embodiment 
       [0053]    Referring now to  FIG. 6 , the process of the 2 nd  embodiment starts with sputter cleaning of the surface of SiN substrate layer  11  onto which is deposited layer of tantalum nitride  61  to a thickness between about 20 and 30 Angstroms. This is immediately followed by the deposition (onto the top surface of  61 ) of layer  62  of NiCr to a thickness between about 20 and 30 Angstroms. Note that it is critical for the effectiveness of this embodiment that layers  61  and  62  always be used together. The motivation for this is the excellent adhesion of TaN to SiN, the excellent adhesion of NiCr to TaN, and the excellent adhesion of Ru to NiCr. Furthermore, NiCr is an effective seed layer for Ru so it also serves to minimize the resistivity of Ru layer  63 . 
         [0054]    Next, layer  63  of ruthenium is deposited on layer  62  and then alpha tantalum layer  64  is deposited on ruthenium layer  63 . Layers  61 - 64  now constitute a base layer on which MTJ devices can be formed. Seen in  FIG. 6  are pinned layer sub-stack  65 , insulator tunneling layer  66  and free layer/capping layers  67 . The individual MTJ devices are formed by etching layers  65 - 67  (under a tantalum hard mask) by means of CF 4 —CH 3 OH, which etching process stops when alpha tantalum layer  64  is reached. The appearance of the structure after the individual MTJ devices have been formed is as illustrated in  FIG. 6 . 
         [0055]    Referring next to  FIG. 7 , following the formation of the MTJ devices they are coated with conformal continuous layer  71  of a material known to protect the MTJ junction during the bottom electrode etch that follows. Suitable materials for this layer include SiO 2 , SiN, and SiN/SiO 2 , with SiO 2  being preferred. Moving on to  FIG. 8 , once layer  71  is in place, photoresist layer  81  is applied over the entire surface and patterned so as to define the individual bottom electrodes, following which this pattern is transferred to layer  71  by etching its unprotected areas. 
         [0056]    As shown in  FIG. 9 , once all photoresist has been removed layer  71  becomes a hard mask suitable for etching alpha tantalum layer  64 . This is accomplished by means of a first RIE process based on one of several possible gaseous compounds of carbon and fluorine, such as CF 4  and CHF 3 , with CF 4  being preferred. It is important to note that the initial thickness of layer  71  is critical as it should be thin enough to provide good spatial resolution of the etched parts but thick enough so that there is always present a sufficient thickness to protect the areas that underlie it. This minimum remaining thickness should be about 600 Angstroms. 
         [0057]    When layer  63  of ruthenium becomes exposed, the etch rate falls off substantially—typically by a factor of about 10, at which point first reactive ion etching may be terminated “at leisure” with no danger of etching through ruthenium layer  63  and penetrating silicon nitride substrate  11 . The appearance of the structure is now as shown in  FIG. 9  with arrow  92  pointing to the region of separation between two individual bottom electrodes 
         [0058]    The remains of layers  64  and  71  now serve as a hard mask for the removal of unprotected areas of ruthenium layer  63 , as well as layers  62  and  61 , by means of a second RIE process. The etchant used in the second reactive ion etching process is one of several possible gaseous compounds of carbon, oxygen, and hydrogen such as CO+NH 3 , CH 3 OH, and C 2 H 5 OH, with CH 3 OH being preferred. Once all exposed ruthenium has been removed, the etch rate drops by a factor of about ⅔ when silicon nitride substrate  11  becomes exposed, at which point the second reactive ion etching process may be terminated with minimal penetration of the silicon nitride substrate and with a non-zero thickness of conformal continuous layer  91  still present. This remnant of layer  91  can now serve as a protective layer for the structure. 
         [0059]    In summary, the advantages of the invention include: 
         [0060]    (a) It results in a well defined vertical profile for each MTJ 
         [0061]    (b) It avoids re-deposition of etching by-products on the device surface 
         [0062]    (c) It avoids any extensive over etching of the underlying thin SiN ILD. 
         [0063]    (d) it avoids possible exposure of the underlying Cu word line, thereby avoiding Cu corrosion by the etching chemicals 
         [0064]    (e) It provides an easily controlled manufacturing scheme for the bottom electrode layer of an MRAM device. 
         [0065]    (f) It solves the problem of weak adhesion between the BE and ILD 
         [0066]    (g) It provides a BE with good electrical conduction 
         [0067]    (h) It protects the exposed MTJ junction during BE etch.