Abstract:
A method for a graphics chip to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to a predetermined request sequence into a plurality of request groups, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; and using the memory controller to adjust a request sequence corresponding to read requests grouped in each request group for retrieving data stored at different N pages so that a memory device only performs N−1 page switching operations.

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to a method for accessing the data stored in the memory, and more specifically, to a method for accessing the data stored in the system memory by a graphics chip. 
   2. Description of the Prior Art 
   With the development of multimedia technologies, displaying images has become an important application of computers. Graphics cards not only perform 2D image processing but also complex 3D image operations. Please refer to  FIG. 1 .  FIG. 1  is a block diagram of a computer device  10  according to prior art. The computer device  10  comprises a central processing unit  12 , a north bridge circuit  14 , a south bridge circuit  16 , a graphics chip  18 , a graphics memory  20 , a display device  22 , a system memory  24 , and an input device  26 . The central processing unit  12  is used for controlling the computer device  10 . The north bridge circuit  14  is used for arbitrating the signal transmission between the high-speed peripheral devices (e.g. graphics chip  18  and system memory  24 ) and the central processing unit  12 . The south bridge circuit  16  is used for arbitrating the signal transmission of low-speed peripheral devices. (e.g. the entry device  26 ) and accesses the peripheral high-speed devices via the north bridge circuit  14 . The graphics chip  18  is used for displaying data operations and storing the display data via the graphics memory  20 . The graphics chip  18  outputs the display data to the display device  22  to output the image. Additionally, the system memory  24  is used for temporarily storing data and programs of the computer device  10 . For example, the system memory is capable of loading an operating system, a resident program, and operational data and so on. Additionally, the accessing operation of the system memory  24  is controlled by the memory controller  15  in the north bridge circuit  14 . Generally, the graphics chip  18  can use an accelerated graphics port (AGP) interface or a peripheral component interconnect (PCI) to read the operational data stored in the system memory  24 . For example, in a 3D texturing operation, the accelerated graphics port can quickly read data in the system memory  24 . With increasing applications using 3D image operations, the accelerated graphics port is becoming increasingly common in the graphics chip  18  to improve the efficiency of the 3D image operations. 
   Please refer to  FIG. 2 .  FIG. 2  is a schematic diagram of data transmission between a conventional accelerated graphics port and a conventional peripheral component interconnect interface according the prior art. For the peripheral component interconnect interface, when the graphics chip  18  is connected to the peripheral component interconnect interface, the graphics chip  18  outputs a read request A 1  to read the data D 1  stored in the system memory  24  via the peripheral component interconnect interface. The graphics chip  18  occupies the bus of the peripheral component interconnect interface until the system memory  24  finishes fetching the data D 1  and outputting the data D 1  to the graphics chip  18  via the bus, at which time the graphics chip  18  releases the bus and another peripheral component (e.g. the input device  26 ) can use the bus of the peripheral component interconnect interface. This means that after fetching the data D 1 , another peripheral component outputs a read request A 2  to read the data D 2  stored in the system memory  24  via the peripheral component interconnect interface. As shown in  FIG. 2 , L 1  is the time period that the graphics chip  18  outputs the read request A 1  to the peripheral component interconnect interface to receive the data D 1 . In the period L 1 , the bus of the peripheral component interconnect interface is occupied by the graphics chip  18 . Oppositely, the accelerated graphics port interface uses a pipeline to access data. The graphics chip  18  can use the bus of the accelerated graphics port interface to output a read request A 1  reading the data in the system memory  24 . However, before the system memory  24  finishes fetching the data, the graphics chip  18  can output the read request A 2 , A 3 , A 4 , A 5  to read the data D 2 , D 3 , D 4 , D 5  in the system memory  24 . As shown in  FIG. 2 , when the graphics chip  18  outputs the read requests A 1 , A 2 , A 3 , A 4 , A 5 , the system memory  24  will execute the read requests A 1 , A 2 , A 3 , A 4 , A 5  in the pipeline manner and the system memory will transmit the fetched data D 1 , D 2 , D 3 , D 4 , D 5  to the graphics chip  18 . So in the same period, when the graphics chip  18  uses the peripheral component interconnect interface according to the prior art to read the data in the system memory  25 , the reading efficiency is not good due to the idle time (i.e. time L 1 ) of the bus. However, the graphics chip  18  uses the accelerated graphics port interface according to the prior art to improve the efficiency of the data operation. 
   In general, the memory controller  15  is used for controlling the data entry operation and the data reading operation of the system memory  24 . The memory controller uses a queue to store a plurality of read requests. This means that the data in the memory  24  is fetched according to the sequence of the read requests in the queue. Please refer to  FIG. 3 .  FIG. 3  is a time sequence diagram for accessing data from a system memory  24  in  FIG. 1 . The graphics chip  18  continuously outputs the read requests RA 1 , RA 2 , RB 1  to read the corresponding data D 1 , D 2 , D 3  in the system memory  24 . The data D 1  and D 2  are stored in the same row, namely in the same page A. The data D 3  is stored in another row, namely in another page B. The queue of the memory controller  15  stores the read requests RA 1 , RA 2 , RB 1  in order. So the executing sequence of read requests is read request RA 1 , read request RA 2  and read request RB 1 . In the 1T period, the memory controller  15  executes a control request ActA to turn on the page A in the system memory  24 , specifically to turn on all memory units corresponding to the page A to access the data stored in the memory units corresponding to the page A. In the 2T period, the memory controller  15  executes the read request RA 1 . When the data D 1 , D 2  and D 3  are 24 bytes and it takes 3T periods to read the 24 bytes from the system memory  24 , the system memory  24  outputs the corresponding data D 1  between times 4T and 7T. In the 5T period, while the memory controller  15  is executing the read request RA 2 , when the data D 1  is output at time 7T, the system memory  24  fetches the data D 2  from times 7T to 10T according to the burst mode because the page A is active. Because the data D 3  is stored in the page B not in the page A, the page A should be pre-charged and the page B should be activated before the memory controller  15  executes the read request RB 1  to read the data D 3  on the page B, i.e. at time 8T. The memory controller  15  executes the control request PreA to pre-charge the page A, and then executes the control request ActB to activate the page B at time 9T. When the page B of the system memory  24  is activated to access the data, the memory controller  15  executes the read request RB 1  at 10T and the system memory  24  starts to fetch the data D 3  between times 12T and 15T. 
   From the above, the graphics chip  18  can use the pipeline to continuously output a plurality of read requests to the memory controller  15  to read the system memory  24 . However, when the system memory  24  uses two read requests to read the data in different pages, the system memory  24  should pre-charge a page (e.g. PreA) and activate a page (e.g. ActA, ActB). The above-mentioned pre-charge and activate operations make the system memory  24  generate a period of delay time (i.e. the period L shown in  FIG. 3 ) in the data accessing processing. In other words, when the system memory  24  uses a plurality of read requests to read a plurality of data on each page, the memory controller  15  should continuously control the system memory  24  to switch among pages. When the bus of accelerated graphics port interface according to the prior art transmits data to the graphics chip  18 , the efficiency is not high enough because the bus must wait to receive the data from the system memory  24  according to the delay time of the system memory  25 . 
   SUMMARY OF INVENTION 
   It is therefore a primary objective of the claimed invention to provide a method for accessing the data stored in the system memory with a graphics chip. 
   According to the claimed invention, a method for a graphics chip to access data stored in a system memory of a computer device comprises the following steps: (a) setting a block capacity value; (b) dividing a plurality of read requests corresponding to a predetermined request sequence and said block capacity value into a plurality of request, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; (c) reordering the read requests in each of said request groups corresponding to data on the page of said system memory into a second request sequence for each of said request groups; and (d) executing the read requests in each of request group according to said second request sequence of each of said request groups. 
   According to the claimed invention, a method for accessing data that a plurality of read requests are used for accessing data from a system memory according to a predetermined request sequence, the method comprises the following steps: (a) reordering said read requests according to pages in said system memory accessed by said read requests in a second request sequence, wherein said read requests accessed the same page of said system memory are continuously arranged; and (b) executing the read requests according to said second request sequence. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a block diagram of the computer device according to prior art. 
       FIG. 2  is a schematic diagram of data transmission between a conventional accelerated graphics port and a conventional peripheral component interconnect interface of  FIG. 1 . 
       FIG. 3  is a time sequence diagram for accessing data from the system memory of  FIG. 1 . 
       FIG. 4  is a schematic diagram for reordering reading requests according to the method for accessing data of the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 1 ,  FIG. 2 ,  FIG. 3  and  FIG. 4 .  FIG. 4  is a schematic diagram of reordering read requests according to the method for accessing data according to the invention. A queue Q is set in the memory controller  15  for temporarily storing the read requests output by the graphics chip  18 . The memory controller  15  sequentially executes the read requests in the queue Q for reading the data in the system memory  24 . As shown in  FIG. 4 , the graphics chip  18  outputs the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4 , C 4  to read the data in the system memory  25 . The read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4 , C 4  are sequentially recorded in queue entries QE 1 , QE 2 , QE 3 , QE 4 , QE 5 , QE 6 , QE 7 , QE 8 , QE 9 , QE 10 , QE 11 , QE 12  of the queue Q. The read request recorded in the queue entry QE 1  is the last executed read request. The read requests A 1 , A 2  and A 3  read the page A of the system memory  24 . The read requests B 1 , B 2  and B 3  read the page B of the system memory  24 . The read requests C 1 , C 2  and C 3  read the page C of the system memory  24 . In this embodiment, there is a block capacity value set in the memory controller  15  for dividing the un-reordered queue Q. For example, the block capacity value is set as 32*64 bytes (i.e. 32 quadwords). The data quantity of the data read by the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4 , C 4  can be added up from QE 1 . The queue entries QE 1 , QE 2 , QE 3 , QE 4 , QE 5 , QE 6 , QE 7 , QE 8 , QE 9 , QE 10 , QE 11 , QE 12  and the corresponding read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4 , C 4  can be divided into the plurality of request groups according to the block capacity value. For example, the total amount of the data in the system memory  24  read by the read requests A 1 , B 1 , C 1 , A 2 , B 2  and C 2  is less than 32*64 bytes and the total amount of the data in system memory  24  read by the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2  and A 3  is larger than 32*64 bytes. So the queue entries QE 1 , QE 2 , QE 3 , QE 4 , QE 5  and QE 6  and the corresponding read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2  are indicated as a first request group, and the queue entries QE 7 , QE 8 , QE 9 , QE 10 , QE 11  and QE 12  and the corresponding read requests A 3 , B 3 , C 3 , A 4 , B 4 , C 4  are indicated as a second request group. 
   At first, the read requests A 1 , B 1 , C 1 , A 2 , B 2  and C 2  in the first request group should be reordered. The queue entry QE 1  is the beginning of the queue Q and the read request A 1  will not be altered, i.e. in the queue Q the queue entry QE 1  still stores the request A 1 , then searches whether any read request for reading the page A in the system  24  is in the first request group of the queue Q. In this embodiment, the read request A 2  of the queue entry QE 4  is for reading the page A of the system memory  24  after the execution order of the read request A 2  is advanced, i.e. the queue entry QE 2  of a queue Q′ stores the read request A 2 . In the first request group of the queue, the read request B 2  and C 2  stored in the queue entries QE 5  and QE 6  behind the queue entry QE 4  are not used for reading the page A of the system memory  24 . So all read requests A 1  and A 2  in the first request group of the queue Q′ for reading the page A of the system memory  24  are re-sorted. From the above, the read requests B 1 , C 1 , B 2 , C 2  are not re-sorted. However the read request B 1  is stored in the queue entry QE 2  of the queue Q′ and corresponded to the higher execution priority so that the executing turn of the read request B 1  is changed and the read request B 1  is next to the read request A 2 , i.e. in a queue Q″, the queue entry QE 3  is used for storing the read request B 1  and the queue entry QE 3  searches for a read request the same as the read request B 1  that is used for reading the page A of the system memory  24 . In the embodiment, the read request A 2  stored in the queue entry QE 5  of the queue Q′ is also used for reading the page B of the system memory  24 . So the execution order of the read request B 2  is changed to be next to the read request B 1 , i.e. in the queue Q″ the queue entry QE 4  is used for storing the read request B 2 . Because the read request C 2  stored in the queue entry QE 6  in the first request group is not used for reading the page B of the system memory  24 , all read requests B 1  and B 2  are re-sorted. Because the left read requests C 1  and C 2  are not re-sorted and the read request C 1  is stored in the queue entry QE 3  of the queue Q′ and the read request C 1  is corresponded to the higher executing priority, the execution order of the read request C 1  is changed and the read request C 1  is next to the read request B 2 , i.e. the queue entry QE 5  is used for storing the read request C 1  and the queue entry QE 5  searches for the read request that is the same as the read request C 1  for reading the page C of the system memory  24 . In the embodiment, the read request C 2  stored in the queue entry QE 6  of the queue Q′ is also used for reading the page C of the system memory  24  so that the execution turn of the read request C 2  is changed and the read request C 2  is behind and next to the read request C 1 , i.e. the queue entry QE 6  stores the read request C 2 . At this moment, all read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2  are re-sorted, i.e. the queue entries QE 1 , QE 2 , QE 3 , QE 4 , QE 5  and QE 6  store the read requests A 1 , A 2 , B 1 , B 2 , C 1 , C 2  in the queue Q″ corresponding to the queue Q′ that is re-sorted. 
   According to the same operation principle, the read requests A 3 , B 3 , C 3 , A 4 , B 4  and C 4  of the second request group in the queue Q′ are re-sorted. In the queue Q″ the last queue entry QE 6  stores the read request C 3  for reading the page C of the system memory  24 . When the read requests in the second request group of the queue Q′ are re-sorted, whether a read request for reading the page C of the system memory  24  is in the second request group is determined. The read requests A 2  and A 3  stored in the queue entries QE 7  and QE 8  of the queue Q′ are not used for reading the page C of the system memory  24 . However, the read request C 3  stored in the queue entry QE 9  of the queue Q′ is used for reading the page C of the system memory  24 , so the execution order of the read request C 3  is changed to behind and next to the read request C 2 , i.e. the queue entry QE 7  of the queue Q′ stores the read request C 3  and whether the read request for reading the page C is in the second request group is determined. The read request C 2  in the last queue entry QE 6  of the first request group of the queue Q″ and the read request C 3  in the first queue entry QE 7  of the second request group of the queue Q″ are used for reading the page C, and the first request group of the queue Q″ finishes data accessing. Therefore, the second request group of the queue Q″ does not switch pages, improving the efficiency for data accessing. 
   In the embodiment, the read request C 4  stored in the queue entry QE 12  of the queue Q′ is used for reading the page C of the system memory  24 . Thus, the execution turn of the read request C 4  is changed and the read request C 4  is behind and next to the read request C 3 , i.e. the queue entry QE 8  stores the read request C 4 . Because the read request C 4  is stored in the last queue entry QE 12  in the second request group of the queue Q′, all read requests C 3  and C 4  in the second request group of the queue Q′ for reading the page C of the system  24  are resorted. From the above, the read requests A 3 , B 3 , A 4  and B 4  are not re-sorted, but the read request A 3  is stored in the queue entry QE 7  so that the read request A 3  has higher executing priority. Thus, the execution turn of the read request A 3  is changed and the read request A 3  is behind and next to the read request C 4 , i.e. the queue entry QE 9  stores the read request A 3 . Then, whether any read request in the second request group is the same as the read request A 3  that is used for reading the page A of the system memory  24  is determined. 
   In the embodiment, the read request A 4  stored in the queue entry QE 10  of the queue Q′ is used for reading the page A of the system memory  24 . The execution order of the read request A 4  is changed and the read request A 4  is behind and next to the read request A 3 , i.e. the queue entry QE 10  stores the read request A 4 . Because the read request B 4  stored in the queue entry QE 11  behind the queue entry QE 10  in the second request group of the queue Q′ is not used for reading the page A of the system memory  24 , all read requests A 3  and A 4  in the second request group of the queue Q′ for reading the page A of the system  24  are re-sorted. Because the read requests B 3  and B 4  are not re-sorted and the read request B 3  is stored in the queue entry QE 8 , the read request B 3  has a higher execution priority. The execution of the read request B 3  is changed and the read request B 3  is behind and next to the read request A 4 , i.e. the queue entry QE 11  stores the read request B 3 . Then, whether any read request in the second request group is the same as the read request B 3  that is used for reading the page B of the system memory  24  is determined. In the embodiment, the read request B 4  stored in the queue entry QE 11  of the queue Q′ is used for reading the page B of the system memory  24 . Thus, the execution turn of the read request B 4  is changed and the read request B 4  is behind and next to the read request B 3 , i.e. the queue entry QE 12  stores the read request B 4 . At this moment, all read requests A 3 , B 3 , C 3 , A 4 , B 4  and C 4  are re-sorted, i.e. the queue entries QE 7 , QE 8 , QE 9 , QE 10 , QE 11  and QE 12  store the read requests C 3 , C 4 , A 3 , A 4 , B 3  and B 4  in order in the resorted queue Q″. 
   The graphics chip  18  reads the system memory  24  in order via the accelerated graphic port interface, i.e. the graphic chip  18  outputs the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  in order to read the data in the system memory  24 . So the memory controller  15  should transmit the data corresponding to the read request A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  to the graphics chip  18  according the receiving order of the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4 . For example, when the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  respectively read the stored data DATA 1 , DATA 2 , DATA 3 , DATA 4 , DATA 5 , DATA 6 , DATA 7 , DATA 8 , DATA 9 , DATA 10 , DATA 11  and DATA 12 . The order in which the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  are executed can be ignored. The memory controller  15  finally transmits the stored data DATA 1 –DATA 12  to the graphics chip  18  according to the storing order of the stored data DATA 1 –DATA 12 . When the execution order of the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  are changed, the graphics chip  18  waits for the memory controller  15  to return the data. As shown in  FIG. 4 , in the un-sorted queue Q, the read request B 1  is stored in the queue entry QE 2 . The memory controller executes the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  according to the queue Q′. When the read request A 1  has been executed, the read request B 1  will be executed. However, the read request B 1  is stored in the queue entry QE 3  in the resorted queue Q′. When the memory controller  15  executes the read requests A 1 , A 2 , B 1 , B 2 , C 1 , C 2 , C 3 , C 4 , A 3 , A 4 , B 3  and B 4  according to the queue Q′, the read request B 1  will be executed until the read requests A 1  and A 2  are executed, i.e. when the graphics chip  18  receives the data DATA 1  from the memory controller, the graphics chip  18  should wait for the memory controller  15  to execute the read request A 2  to read the stored data DATA 4 . The memory controller  15  will store the DATA 4  in a buffer at first according to the prior art, i.e. the data DATA 4  will not be transmitted to the graphics chip  18  immediately. The memory controller  15  executes the read request B 1  and then transmits the corresponding stored data DATA 2  to the graphics chip  18 . For the read request C 1 , the read request C 1  is stored in the queue entry QE 5  of the queue Q′, i.e. when the graphics chip  18  receives the stored data DATA 2  from the memory controller  15 , the graphics chip  18  should wait for the memory controller  15  to execute the read request B 2  to read the stored data DATA 5 . The memory controller  15  stores the data DATA 5  in the buffer at first, and the data DATA 5  is not transmitted to the graphics chip  18  immediately. The memory controller  15  executes the read request C 1  and transmits the corresponding stored data DATA 3  to the graphics chip  18 . Because the buffer stores the stored data DATA 4  and DATA 5 , the memory controller  15  can read the buffer in order to transmit the stored data DATA 4  and DATA 5  to the graphics chip  18 . 
   Then, the un-sorted queue Q′ is compared with the re-sorted queue Q″ as shown in  FIG. 4 . In the first request group, the read requests B 1  and C 1  are respectively stored in the queue entries QE 2  and QE 3  of the queue Q′. The read requests B 1  and C 1  are respectively stored in the QE 3  and QE 5  of the queue Q″. Because the queue priority of the queue entry QE 3  is lower than the queue priority of the queue entry QE 2  and the queue priority of the queue entry QE 5  is lower than the queue priority of the queue entry QE 3 , the graphics chip  18  must wait for the memory controller  15  to receive the stored data DATA 2  and DATA 3  when the memory controller  15  executes the resorted queue Q″. For avoiding reduced efficiency from the graphics chip  18  waiting for data, the method for accessing data in the invention uses the block capacity to adjust the number of the resorted read requests, i.e. when the block capacity is 32*64 bytes, in the worst case example, the read request A 3  is stored in the queue entry QE 7  in the second request group of the queue Q′ but is stored in the queue entry QE 12  in the second request group of the resorted queue Q″. When the operation time that the system memory  24  switches the pages is not under consideration, the method for accessing data in the invention can make the time that the graphics chip  18  waits for the data to be not larger than the time that the system memory  24  fetches 32*64 bytes of data. In other words, the method for accessing data in the invention can set adaptive block capacity to control the time that the graphics chip  18  waits for the data, i.e. the graphics chip  18  can be adjusted to have the best execution efficiency. Further, the block capacity can be adjusted dynamically according the activity level of the system memory  24 . For example, when the memory is busy, the block capacity can be enlarged to reduce the number of closed pages. On the other hand, the block capacity can be reduced or kept at an original setting. Additionally, although the method for accessing data of the invention makes the graphics chip  18  idle when the graphics chip  18  waits for data, when the read requests in the queue are re-sorted, the operation time that the system memory  24  uses when switching pages can be reduced substantially. For example, when the memory controller  15  executes the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4  and C 4  to read the stored data DATA 1 –DATA 12  of the system memory  24 , the system memory  24  should switch pages 11 times. According to the prior art, the page switch includes turning off a page and turning on another page so that the efficiency at which the system memory  24  accesses data is reduced. In the embodiment, the read requests A 1 , B 1 , C 1 , A 2 , B 2 , C 2 , A 3 , B 3 , C 3 , A 4 , B 4 , C 4  are divided into a first request group and a second request group and the read request are resorted in the request groups to generate a queue Q″. When the memory controller  15  executes the read requests A 1 , A 2 , B 1 , B 2 , C 1 , C 2 , C 3 , C 4 , A 3 , A 4 , B 3  and B 4  according to the queue Q″, the system memory  24  switches pages 4 times so that the efficiency at which the system memory  24  accesses the data can be improved substantially. In a word, although the method for accessing data makes the graphics chip  18  idle while waiting for the data, the method improves the efficiency at which the system memory  24  accesses the data. In other words, improvement of the efficiency that the system memory  24  accesses data can compensate the time that the graphics chip  18  waits for the data. In the embodiment, the sorting method is applied in a display control circuit to read the read requests output from a system memory. However, the method for accessing data can also be applied to other data processing devices (e.g. CPU) to read the data of the system memory to achieve the goal of improving the efficiency of data access. 
   The method for accessing data according to the invention uses a block capacity to divide a plurality of read requests into a plurality of request groups. The block capacity is used for limiting the worst-case time that a graphics chip waits for data. The reduction of efficiency occurring when a plurality of the read requests are re-sorted can be avoided. Additionally, the read requests of the request group are used for reading the N pages of a system memory. When the read requests in the request group of the invention are re-sorted, the system memory switches the pages (N−1) times. The method for accessing data in the invention can improve the execution efficiency at which the graphics chip reads the system memory and further improve the operating efficiency of the graphics chip. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be constructed as limited only by the metes and bounds of the appended claims.