Abstract:
A capacitor-coupling acceleration apparatus is an accelerating circuit capable of being applied to interconnect lines in an integrated circuit in order to reduce delay owing to parasitic resistance and capacitance of the interconnect lines in the integrated circuit. The apparatus can be disposed between the interconnect lines. When a signal transmitted on the interconnect line has a change from a low-level voltage to a high-level voltage, the apparatus detects the voltage level change of the signal and provides a charging loop to charge the interconnect line, thereby accelerating the change from the low-level voltage to the high-level voltage. When a signal on the interconnect line has a change from the high-level voltage to the low-level voltage, the apparatus detects the voltage level change of the signal and provides a discharging loop to discharge the interconnect line, thereby accelerating the change from the high-level voltage to the low-level voltage.

Description:
This application claims the benefit of Taiwan application Serial No. 091106057, filed Mar. 27, 2002. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates in general to a capacitor-coupling device, and more particularly to a capacitor-coupling accelerator for use in an integrated circuit. 
   2. Description of the Related Art 
   In modem integrated circuit design, the delays of interconnect lines in a chip determine the performance of the whole chip. For the progress of the VLSI manufacturing process and the need for system-on-chip (SOC) integration, the gate delays in a chip are reduced when the devices in the chip are scaled down. Unfortunately, interconnect lines are lengthened along with the chip when the chip becomes larger. Besides, interconnect delays are made larger because greater RC effects result from the smaller line width of the interconnect lines and the narrower space between the interconnect lines. The performance of the whole chip would thus be degraded. As a result, the reduction in the interconnect delay is desired to be achieved. 
   The delay of an interconnect line can be reduced by inserting a buffer into the middle of the interconnect line because the delay time is proportional to the square of the interconnect length, as indicated by the relationship: t∝rcl 2 . This approach to reduction of the interconnect delay is illustrated in  FIG. 1 , wherein a buffer is inserted in the middle of the interconnect line. Suppose that the whole interconnect line has a delay time τ 2 mm  when its length is 2 mm originally. The delay time becomes 2×τ 1 mm +τ buffer  when the buffer is inserted into the middle of the interconnect line, where τ 1 mm  is the interconnect delay for one segment of the interconnect line with a length of 1 mm and τ buffer  is the delay of the buffer. The delay time may thus reduced if τ 2 mm &gt;2×τ 1 mm +τ buffer . This approach is commonly used in the industry. The details for the approach is discussed in the literature by Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, and Juho Kim, entitled “Interleaving buffer insertion and transistor sizing into a single optimization”, IEEE Transactions on VLSI systems, vol. 6, no. 4, pp. 625-63, December 1998. 
   The interconnect delay can also be minimized by using a reduced voltage signal (V), as indicated by the equation t=CV/I deduced from Q=CV=It. This approach is disclosed in the literature by H. Zhang, V. Gerorge and J. M. Rabaey, entitled “Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness”, IEEE Transactions on VLSI Systems, vol. 8, no. 3, pp. 264-272, June, 2000. The delay is reduced in this approach by first reducing the amplitude of a signal to be transferred at the sending end and then amplifying the received signal at the receiving end to make this signal have the original amplitude at the sending end. This approach requires a number of control signals or power supplies, thus resulting in difficulties in implementation. Thus, the approach is not suitable for mass production. 
   In addition, the transient sensitivity of the resistive interconnect signals can be accelerated by controlling the output stage according to a fast control signal and a slow control signal that are produced by a Schmitt trigger and a transient sensitive trigger (TST). This approach is disclosed by Tmofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, and Masakazu Yamashina in the literature entitled “Capacitor coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 531-536, April 1996. Unfortunately, this approach has a disadvantage that the speed of discharging and charging processes involved in the output stage is reduced because the loops for discharging and charging are in serial connection with two PMOS and NMOS, respectively. The accelerating effect is thus restricted. 
   As discussed above, the conventional approaches to the reduction of the interconnect delay are difficult to control and have limited performance. Hence, it is desirable to provide an accelerating circuit that is of high performance and readily to be controlled so as to achieve the reduction in interconnect delay as well as to enhance the overall performance of the chip. 
   SUMMARY OF THE INVENTION 
   It is therefore an object of the invention to provide an apparatus for capacitor-coupling acceleration in order to reduce the time delay of the signal transmitted on the interconnect line and accelerate changes of the signal on the interconnect line. 
   The invention achieves the above-identified object by providing an apparatus for capacitor-coupling acceleration. The apparatus can be disposed in an interconnect line so as to reduce its interconnect delay and speed up the level change of a signal transmitted on the interconnect line. The apparatus includes a voltage step-down detecting device, a first capacitor, a discharging device, a voltage step-down charging device, accelerating devices, a voltage step-up detecting device, a second capacitor, a charging device, a voltage step-up discharging device. When the signal on the interconnect line decreases, the voltage step-down detecting device feeds a step-down signal to the first capacitor. The first capacitor passes the step-down signal to the voltage step-down charging device through the capacitor-coupling effect. The voltage step-down charging device then charges the discharging device so that the discharging device discharges the interconnect line, thereby accelerating the decrease of the signal transmitted on the interconnect line. In addition, one accelerating device can be coupled to the voltage step-down charging device and the discharging device to make the transition from high to low more rapid. When the signal on the interconnect line increases, the voltage step-up detecting device feeds a step-up signal to the second capacitor. The second capacitor passes the step-up signal to the voltage step-up discharging device through the capacitor-coupling effect. The voltage step-up discharging device then discharges the charging device so that the charging device charges the interconnect line, thereby accelerating the increase of the signal transmitted on the interconnect line. In addition, another accelerating device can be coupled to the voltage step-up discharging device and the charging device to make the transition from low to high more rapid. 
   Further, a high-threshold triggering device can be coupled to the interconnect line so as to output a control signal, which is a delayed version of the signal on the interconnect line, by delaying the change of the signal on the interconnect line. An inverter can be used for inverting the control signal in order to produce an inverted control signal. The control and the inverted control signal are employed to preset the operation modes for the voltage step-down detecting device, the voltage step-down charging device, the voltage step-up detecting device, the voltage step-up discharging device in order to make them operable for the next change of the signal on the interconnect line. 

   
     Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a buffer inserted into an interconnect line in the middle so as to reduce interconnect delay. 
       FIG. 2  illustrates capacitor coupling. 
       FIG. 3  is a block diagram of a high-threshold capacitor-coupling trigger according to a first embodiment of the invention. 
       FIG. 4A  illustrates the implementation of the capacitor-coupling trigger in  FIG. 3  by using semiconductor devices. 
       FIG. 4B  is a timing diagram illustrating the signals in FIG.  4 A. 
       FIG. 5  is a block diagram of a low-threshold capacitor-coupling trigger according to a second embodiment of the invention. 
       FIG. 6A  illustrates the implementation of the capacitor-coupling trigger in  FIG. 5  by using semiconductor devices. 
       FIG. 6B  is a timing diagram illustrating the signals in FIG.  6 A. 
       FIG. 7  is a block diagram of a capacitor-coupling accelerator according to a third embodiment of the invention. 
       FIG. 8A  illustrates the operation of the capacitor-coupling accelerator in  FIG. 7  in a high steady state. 
       FIG. 8B  illustrates the operation of the capacitor-coupling accelerator in  FIG. 7  in a transition from a high-level voltage to a low-level voltage. 
       FIG. 8C  illustrates the operation of the capacitor-coupling accelerator in  FIG. 7  in a low steady state. 
       FIG. 8D  illustrates the operation of the capacitor-coupling accelerator in  FIG. 7  in a transition from a low-level voltage to a high-level voltage. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Capacitor coupling is employed in the invention to provide triggering devices and accelerating devices that meet the design needs for reduction in the time delay of the signals transmitted on the interconnect lines. The use of capacitor coupling is illustrated in FIG.  2 . As shown in  FIG. 2 , when the input signal V in  changes, the output signal V out  changes with the input signal V in  because of the capacitor-coupling effect. As a result, the voltage change of the output signal V out  relates to that of the input signal V in , and capacitors C 1  and C 2  by: 
         Δ   ⁢           ⁢   Vout     =         C   1         C   1     +     C   2         ⁢   Δ   ⁢           ⁢     Vin   .           
 
If the capacitor C 1  is sufficiently large, the change of V out  will be substantially equal to that of V in , as indicated in the above relationship between V out  and V in . On the basis of this theory, triggering devices and accelerating devices, as well as their application to signal transmission, will be described in the following embodiments.
 
   FIRST EMBODIMENT 
   A high-threshold capacitor-coupling trigger  300  is illustrated in  FIG. 3  according to a first embodiment of the invention in block diagram form. The high-threshold capacitor-coupling trigger (HCCT)  300  includes two capacitors C 1 , C 2 , a voltage step-down detecting device  310 , a voltage step-down charging device  350 , a voltage step-up detecting device  370 , and a voltage step-up discharging device  390 . The high-threshold capacitor-coupling trigger  300  has an output signal at the output terminal OUT and the output signal is a delayed version of an input signal IN. The voltage step-down detecting device  310  is used for detecting a slow decrease in the voltage of an input signal IN and outputting a step-down signal corresponding to and being delayed against the slow decrease during the slow increase. When the input signal IN decreases from a high level to a predetermined value, the voltage step-down detecting device  310  outputs the step-down signal corresponding to the decrease of the input signal IN. The step-down signal, through the coupling effect of the capacitor C 1 , is then passed to the voltage step-down charging device  350 . On receiving the step-down signal, the voltage step-down charging device  350  begins charging the output terminal OUT according to the step-down signal. That is, the step-down transition of the input signal IN from the high level to the predetermined value causes the output signal from the output terminal OUT to rise to a high level. In addition, the voltage step-up detecting device  370  is used for detecting a slow increase in the voltage of the input signal IN and outputting a step-up signal corresponding to and being delayed against the slow increase during the slow increase. When the input signal IN increases from a low level to a predetermined value, the voltage step-up detecting device  370  outputs the step-up signal corresponding to the increase of the input signal IN. The step-up signal, through the coupling effect of the capacitor C 2 , is then passed to the voltage step-up discharging device  390 . On receiving the step-down signal, the voltage step-up discharging device  390  begins discharging the output terminal OUT. That is, the step-up transition of the input signal IN from the low level to the predetermined value causes the output signal from the output terminal OUT to fall to the low level. 
   Signals corresponding to the input signal can be employed for controlling the status of the high-threshold capacitor-coupling trigger  300  because the input signal (V IN ) at the input terminal controls the charging and discharging of the output terminal of the high-threshold capacitor coupling trigger  300 . The voltage step-up discharging device  390  can be made unaffected by the voltage decrease of the input signal V IN  by disabling both the voltage step-up detecting device  370  and the voltage step-up discharging device  390  when the input signal V IN  is in the high level. Likewise, the voltage step-down charging device  350  can be made unaffected by the voltage increase of the input signal IN by enabling both the voltage step-down detecting device  310  and the voltage step-down charging device  350  when the input signal V IN  is in the low level. In addition, the input terminal of an inverter (INV) can be connected to the output terminal OUT of the high-threshold capacitor-coupling trigger  300  so that the output terminal (OUTB) of the inverter changes its voltage level as the output terminal OUT does. In this way, the output signal V OUTB  at the output terminal OUTB can be used to control the status of the high-threshold capacitor-coupling trigger  300 . Further, the status of the high-threshold capacitor-coupling trigger  300  can be controlled by the feedback of the signal similar to the output signal V OUTB , for example, the output signal of a serial connection of two inverters coupled to the input terminal IN. 
   The high-threshold capacitor-coupling trigger  300  can be implemented with semiconductors, for example, as shown in the circuit diagram in FIG.  4 A. The voltage step-down detecting device  310  includes a PMOS P 1  and an NMOS N 2 . The source and the gate of P 1  are coupled to a power terminal and the output terminal OUTB of the inverter INV, respectively. The drain and the gate of N 2  are coupled to the drain of P 1  and the output terminal OUTB of the inverter INV, respectively. In addition, the source of N 2  is used for receiving the input signal at the input terminal IN and the drain of N 2  is used as the output terminal of the voltage step-down detecting device  310 . The voltage step-down charging device  350  includes PMOSs P 3  and P 4 . P 4  is employed to charge the output terminal of the voltage step-down charging device  350  in response to a voltage decrease at the gate of P 4 . The source, the gate, and the drain of P 4  are coupled to a power terminal, the capacitor C 1 , and the output terminal OUTB of the inverter, respectively. The drain of P 4  is used as the output terminal of the voltage step-down charging device  350 . P 3  is used for charging the gate of P 4  according to the output signal from the output terminal OUTB of the inverter INV. The source, the drain, and the gate of P 3  are coupled to the power terminal, the capacitor C 1 , and the output terminal OUTB of the inverter INV, respectively. The voltage step-up detecting device  370  includes an NMOS N 1  and a PMOS P 2 . The source and the gate of N 1  are coupled to a ground terminal and the output terminal OUTB of the inverter INV, respectively. The drain and the gate of P 2  are coupled to the drain of N 1  and the output terminal OUTB of the inverter INV respectively. Moreover, the source of P 2  is used for receiving the input signal at the input terminal IN and the drain of P 2  is used as the output terminal of the voltage step-up detecting device  370 . The voltage step-up discharging device  390  includes NMOSs N 3  and N 4 . N 4  is employed to discharge the output terminal of the voltage step-up discharging device in response to a voltage increase at the gate of N 4 . The source, the gate, and the drain of N 4  are coupled to the ground terminal, the capacitor C 2 , and the input terminal of the inverter INV, respectively, wherein the drain of N 4  is used as the output terminal of the voltage step-up discharging device. N 3  is used for discharging the gate of N 4  according to an output signal outputted from the output terminal OUTB of the inverter INV. The source, the drain, and the gate of N 3  are coupled to the ground terminal, the capacitor C 2 , and the output terminal OUTB of the inverter INV, respectively. 
   Two possible operations of the high-threshold capacitor-coupling trigger shown in  FIG. 4A  are described. In the initial state of the first operation, the input signal V IN  at the input terminal IN, the output voltage V OUT  at the output terminal OUT, and the output signal V OUTB  at the output terminal OUTB are supposed to have a voltage level of VDD, ground, and VDD, respectively. In addition, the input signal V IN  is supposed to decrease from the voltage level of VDD. When V IN  drops to VDD−V t , the voltage at node C begins to fall with V IN . The voltage signal at node C, that is, the output signal of the voltage step-down detecting device  310 , is referred to as a step-down signal. The step-down signal is then coupled to node A by the capacitor coupling effect of the capacitor C 1 . As a result, the voltage at node A also drops with that at node C. When the voltage at node A drops by a value of V t , P 4  is enabled to charge the output terminal OUT. When the voltage at the output terminal OUT reaches the value of VDD, the output signal V OUT  will be zero. In this case, the PMOSs P 1 , P 2 , P 3  are enabled to charge nodes A and C. In the second operation, the input signal V IN  is supposed to rise from zero. When the input signal V IN  increases to the value of V t , the voltage at node D starts to rise with the input signal V IN . The voltage signal at node D, that is, the output signal of the voltage step-up detecting device  370 , is called a step-up signal. The step-up signal is then coupled to node B by the capacitor coupling effect of the capacitor C 2 . Hence, the voltage at node B rises with that at node D. When the voltage at node B drops by a value of V t , N 4  is enabled to discharge the output terminal OUT. When the voltage at the output terminal OUT reaches the value of zero, the output signal V OUTB  will be equal to VDD. In this case, the NMOSs N 1 , N 2 , N 3  are enabled to discharge nodes B and D. The timing diagram corresponding to the above operations on the signals involved in  FIG. 4A  is shown in FIG.  4 B. In  FIG. 4A , Δt 1  indicates the period for the input signal V IN  at the input terminal IN to drop from the high level so as to enable the NMOS N 2 , and Δt 2  indicates the period for the input signal V IN  at the input terminal IN to rise from the low level so as to enable the PMOS P 2 . 
   The circuit shown in  FIG. 4A  can be employed as a delaying buffer because a delay corresponding to the value of V t  is produced by the PMOS P 2  and the NMOS N 2  to make the output signal V OUT  a delayed version of the input siganl V IN . In addition, the delay of the circuit can be adjusted by the desired threshold and the threshold can be determined by controlling the magnitude of the capacitors. 
   SECOND EMBODIMENT 
   A low-threshold capacitor-coupling trigger  500 , as shown in  FIG. 5 , is a block diagram of a second embodiment of the invention, with an input terminal IN and an output terminal OUT. The low-threshold capacitor-coupling trigger  500  can be used as a signal receiver for signals from an interconnect line, for example. The low-threshold capacitor-coupling trigger  500  includes capacitors C 1 , C 2 , accelerating devices  555 ,  595 , a voltage step-down detecting device  510 , a voltage step-down charging device  550 , a voltage step-up detecting device  570 , and a voltage step-up discharging device  590 . The voltage step-down detecting device  510 , coupled to the input terminal IN, is used for detecting a slow voltage decrease of an input signal at the input terminal so as to output a step-down signal corresponding to the input signal. When the input signal drops from a high level, the voltage step-down detecting device  510  outputs the step-down signal according to the decrease of the input signal. The step-down signal, through the capacitor coupling effect of the capacitor C 1 , is then transferred to the voltage step-down charging device  550 . Thus, the voltage step-down charging device  550  is enabled to charge the output terminal OUT. In other words, the voltage at the output terminal OUT rises while the input signal falls from the high level. Particularly, the voltage at the output terminal OUT is rising faster because charging the output terminal OUT with the voltage step-down charging device  550  is accelerated by the starting of the accelerating device  555  when the voltage step-down charging device  550  charges the output terminal OUT. The voltage step-up detecting device  570 , coupled to the input terminal of the low-threshold capacitor-coupling trigger  500 , is used for detecting a slow voltage increase of the input signal so as to output a step-up signal corresponding to the input signal. When the input signal applied to the input terminal IN rises from the low level, the voltage step-up detecting device  570  outputs the step-up signal corresponding to the rise of the input signal. The step-up signal, through the capacitor coupling effect of the capacitor C 2 , is transferred to the voltage step-up discharging device  590  so as to enable the voltage step-up discharging device  590  to discharge the output terminal OUT. In other words, the input signal rises from the low level so that the voltage at the output terminal OUT falls accordingly. Particularly, the voltage at the output terminal OUT is falling faster because discharging the output terminal OUT with the voltage step-up discharging device  590  is accelerated by the starting of the accelerating device  595  when the voltage step-up discharging device  590  discharges the output terminal OUT. 
   Further, the low-threshold capacitor-coupling trigger  500  can be predetermined in different operating states by two control signals CO 1  and CO 2 , for example. The control signal CO 2  is produced by a high-threshold trigger  505  according to the input signal at the input terminal IN. The high-threshold trigger  505  is used for producing the control signal CO 2  which lags behind this input signal, and can be, for example, the high-threshold capacitor-coupling trigger  300  disclosed in the first embodiment or any other device that can achieve this purpose (e.g. Schmitt trigger). Another control signal CO 1  is an inverted version of the control signal CO 2  and can be produced by using an inverter, such as the inverter INV indicated in FIG.  5 . The control signals CO 1  and CO 2  can be used for presetting the operating states of the voltage step-down detecting device  510 , the voltage step-down charging device  550 , the voltage step-up detecting device  570 , and the voltage step-up discharging device  590 . An example of the implementation of FIG.  5  and its operating state predetermination will be provided in the following. 
   As shown in  FIG. 6A , the low-threshold capacitor-coupling trigger  500  in  FIG. 5  is implemented with semiconductors. The voltage step-down detecting device  510  includes PMOSs P 1  and P 2 . The source of P 1  is coupled to a power terminal while the gate of P 1  is used for receiving the inverted control signal CO 1 . The source of P 2  is coupled to the drain of P 1 . The gate and the drain of P 2  are used for receiving the control signal CO 2  and the input signal at the input terminal IN respectively. The source of P 2  (i.e. node C) is used as the output terminal of the voltage step-down detecting device  510 . The voltage step-down charging device  550  includes PMOSs P 3  and P 4 . P 4  is used for charging the output terminal OUT in response to a decrease in the voltage of the gate of P 4 . The source, the gate, and the drain of P 4  are coupled to a power terminal, the capacitor C 1 , and the output terminal OUT, respectively. The source, the drain, and the gate of P 3  are coupled to the power terminal, the capacitor C 1 , the output terminal of the inverter NV, respectively. The PMOS P 3  is used for charging the gate of P 4  according to the inverted control signal CO 1 . The accelerating device  555  is a positive feedback discharging loop for discharging the voltage step-down charging means, and includes NMOSs N 5  and N 6 , for example. The drain and the gate of N 5  are coupled to the gate and the drain of P 4 , respectively. The drain, the source, and the gate of N 6  are coupled to the source of N 5 , the ground terminal, and the input terminal IN respectively. The voltage step-up detecting device  570  includes NMOSs N 1  and N 2 . The source of N 1  is coupled to the ground terminal while the gate of N 1  is used for receiving the inverted control signal CO 1 . The source of N 2  is coupled to the drain of N 1 . The gate of N 2  is used for receiving the control signal CO 2 . The drain of N 2  is used for receiving the input signal at the input terminal IN, and the source of N 2  is used as the output terminal of the voltage step-up detecting device  570 . The voltage step-up discharging device  590  includes NMOSs N 3  and N 4 . N 4  is used for discharging the output terminal OUT in response to a voltage increase of the gate of N 4 . The source, the gate, and the drain of N 4  are coupled to the ground terminal, the capacitor C 2 , and the output terminal OUT respectively. N 3  is used for charging the gate of N 4  according to the inverted control signal. The source, the drain, and the gate of N 3  are coupled to the ground terminal, the capacitor C 2 , the output terminal of the inverter INV, respectively. The accelerating device  595  is a positive feedback charging loop for charging the voltage step-up discharging device, and includes PMOSs P 5  and P 6 , for example. The drain and the gate of P 5  are coupled to the gate and the drain of N 4 , respectively. The drain, the source, and the gate of P 6  are coupled to the source of P 5 , the power terminal, and the input terminal IN respectively. 
   As shown above, the main difference in implementation between the first and the second embodiments is the two positive feedback loops, including the accelerating devices  555  and  595  individually, for accelerating the response speed of the latter. In addition, the voltage step-down detecting devices in  FIGS. 4A and 6A  are different. 
   In the following, two operation modes of the low-threshold capacitor-coupling trigger  500  in  FIG. 6A  are described. In addition, the timing diagram of the signals involved in this circuit can be referred to FIG.  6 B. In the initial state of the first operation, the voltage at the input terminal IN, the voltage of the inverted control signal CO 1 , the voltage at the output terminal OUT, and the voltage of the control signal CO 2  are supposed to be VDD, VDD, ground, and ground respectively. When the input signal at the input terminal IN begins to fall at time t 1  (as indicated in FIG.  6 B), the voltage at node C, that is, the step-down signal, drops as well. By the coupling effect of the capacitor C 1 , the voltage at node A decrease as the voltage at node C does. When the voltage at node A drops by a value of V t , P 4  is enabled to charge the output terminal OUT. When the voltage at the output terminal OUT rises by a value of V t , N 5  is enabled to begin discharging node A through N 6 . In other words, a positive feedback loop is formed with the accelerating device  555 . The charging speed of the output terminal OUT with P 4  is increased after node A is discharged. Thus, the output terminal OUT has a sharp increase in voltage. In addition, the control signal CO 2  lags behind the output signal at the output terminal OUT because of the characteristics of the high-threshold trigger  505 , and then the inverted control signal CO 1  changes to 0 when the control signal CO 2  changes to VDD. When the inverted control signal CO 1  changes to 0, the PMOS P 1 , P 3 , P 6 , and NMOS N 2  are enabled to charge nodes A and C to VDD, as indicated at time t 2  in FIG.  6 B. As a result, preparation for the next signal transition is done. That is, the operating states of the voltage step-down detecting device  510 , the voltage step-down charging device  550 , the voltage step-up detecting device  570 , and the voltage step-up discharging device  590  can be preset by the control signal CO 2  and the inverted control signal CO 1  in order to prepare the low-threshold capacitor-coupling trigger  500  for the next signal level transition. 
   In the second operation, the input signal at the input terminal IN has a transition from 0 to VDD. When the input signal at the input terminal IN begins to rise at time t 3  (as indicated in FIG.  6 B), the voltage at node D, that is, the step-up signal, rises as well. By the coupling effect of the capacitor C 2 , the voltage at node B increases as the voltage at node D does. When the voltage at node B rises by a value of V t , N 4  is enabled to begin to discharge the output terminal OUT. When the voltage at the output terminal OUT drops by a value of V t , P 5  is enabled to begin charging node B through P 6 . In other words, a positive feedback loop is formed with the accelerating device  595 . The discharging speed of the output terminal OUT with N 4  is increased after node B is charged. Thus, the output terminal OUT has a sharp decrease in voltage. In addition, the control signal CO 2  lags behind the output signal at the output terminal OUT because of the characteristics of the high-threshold trigger  505 , and then the inverted control signal CO 1  changes to VDD when the control signal CO 2  changes to 0. When the inverted control signal CO 1  changes to VDD, the NMOS N 1 , N 3 , N 6 , and PMOS P 2  are enabled to discharge nodes B and D to ground, as indicated at time t 4  in FIG.  6 B. As a result, preparation for the next signal transition is done. That is, the operating states of the voltage step-down detecting device  510 , the voltage step-down charging device  550 , the voltage step-up detecting device  570 , and the voltage step-up discharging device  590  can be preset by the control signal CO 2  and the inverted control signal CO 1  for the next signal transition. 
   As compared with the high-threshold capacitor-coupling trigger  300 , the low-threshold capacitor-coupling trigger  500  has a different input stage and two positive feedback loops. In addition, the input stage of the low-threshold capacitor-coupling trigger  500  causes the delay of the signal transition occurred at node C or D to be reduced by a time corresponding to a voltage change of V t . Further, the two positive feedback loops are applied in the low-threshold capacitor-coupling trigger  500  so that the delay of the low-threshold capacitor-coupling trigger  500  can be made quite small if sufficient large values of the capacitors C 1  and C 2  are taken. 
   The low-threshold capacitor-coupling trigger  500  according to the second embodiment has the following advantages:
         1. The threshold can be adjusted to the design needs by changing the values of the capacitors used in the circuit.   2. Short-circuited current is reduced because the PMOS P 4  and NMOS N 4  of the output stage will not be enabled simultaneously and no DC current is produced in the operation of the circuit.   3. The circuit operation is accelerated because the loads at nodes A and C are reduced by separating the input signal at the input terminal from nodes A and C with the capacitors C 1  and C 2 , respectively if the input load is large.   4. No external control signal is needed, thus contributing to the reduction in complexity. The control signals involved in the circuit operation are generated internally.   5. The application of the low-threshold capacitor-coupling accelerator to a receiver connected to a long interconnect line can adjust the input signal to the receiver in low dissipation and at high speed.       

   THIRD EMBODIMENT 
   A capacitor-coupling accelerator is illustrated in  FIG. 7  according to a third embodiment of the invention. The capacitor-coupling accelerator shown in  FIG. 7  is an accelerator based on the circuit configuration of the second embodiment and can be disposed on an interconnect line TL to accelerate the signal transition occurred on the interconnect line TL. The capacitor-coupling accelerator can be designed to be in the middle of the interconnect line TL to accelerate the signal transition occurred on the interconnect line TL. Because some of the circuit components of the capacitor-coupling accelerator in  FIG. 7 , including the capacitors C 1 , C 2 , the accelerating devices  555 ,  595 , the voltage step-down detecting device  510 , the voltage step-down charging device  550 , the voltage step-up detecting device  570 , and the voltage step-up discharging device  590 , are identical to those in the second embodiment, the detailed operations of these components will not be described. Instead, the operation of a discharging device  757  and a charging device  797  will be described since the discharging device  757  and the charging device  797 , for example, NMOS N 8  and PMOS P 8  respectively, belong to the capacitor-coupling accelerator in  FIG. 7 , not to the second embodiment. 
   When the input signal at the input terminal IN decreases from the high level, the voltage at node A falls with that at node C as so to enable the NMOS N 8  to discharge the interconnect line TL. The voltage of the interconnect line TL is then lowered. The signal on the interconnect line TL decreases more rapidly because the positive feedback loop with the accelerating device  555  accelerates the discharging of the interconnect line TL with the NMOS N 8 . Conversely, when the input signal at the input terminal IN increases from the low level, the voltage at node B rises with that at node D as so to enable the PMOS P 8  to charge the interconnect line TL. The voltage of the interconnect line TL is then increased. The signal on the interconnect line TL increases more rapidly because the positive feedback loop with the accelerating device  595  accelerates the charging of the interconnect line TL with the PMOS P 8 . 
   The operations of the capacitor-coupling accelerator are illustrated in  FIGS. 8A  to  8 D according to the third embodiment of the invention, wherein the devices and the interconnect lines that are enabled or transmit signals are drawn in bold.  FIG. 8A  illustrates the capacitor-coupling accelerator operating in a high steady state. Initially, the signal on the interconnect line TL is supposed to be equal to VDD so that the control signal CO 2  is 0 and the inverted control signal CO 1  is VDD.  FIG. 8B  illustrates the capacitor-coupling accelerator when the input signal changes from the high level to the low level. When the signal on the interconnect line TL begins to decrease, the voltage at node C falls as well. The voltage at node A decreases with the voltage at node C by the coupling effect of the capacitor C 1 . When the voltage at node A drops by a value of V t , P 4  is enabled to charge the gate of N 8 . N 5  and N 8  will be enabled when the gate voltage of N 8  increases by a value of V t . In this case, discharging occurs at node A through N 5 , which is a positive feedback process. In addition, discharging occurs on the interconnect line TL through N 8 , accelerating the fall of the signal on the interconnect line TL. When the voltage on the interconnect line TL drops to 0, the control signal CO 2  and the inverted control signal CO 1  become VDD and 0 respectively by the high-threshold trigger  505  and inverter INV. As a result, P 1 , P 3 , N 2 , and N 7  are enabled, the voltages at nodes A and C are pulled high to VDD and the potential of the interconnect line TL is pulled down to 0, as indicated in FIG.  8 C. Further, when the voltage on the interconnect line TL changes from 0 to VDD, the operation of the capacitor-coupling accelerator corresponds to the above with the corresponding components in the lower part of the schematic diagram, as illustrated in FIG.  8 D. 
   The capacitor-coupling accelerator according to the third embodiment has the following advantages:
         1. The output stage will not be enabled at the same time and thus no short-circuited current occurs during the operation of the circuit.   2. The loads at nodes A and C become smaller by physically separating the input signal from nodes A and C with the capacitors C 1  and C 2 , thus accelerating the circuit operation.   3. The accelerator is fully controlled by its control signals. The complexity of the whole chip to which the accelerators are applied will not be increased because no external control signal is needed.   4. Circuit operation is accelerated because the discharging and charging loops of the output stage employ a serially-connected NMOS and a serially-connected PMOS respectively.   5. The accelerator can be applied to bi-directional interconnect lines.       

   In brief, the capacitor-coupling trigger and the capacitor-coupling accelerator disclosed above have the following advantages:
         1. The threshold can be adjusted to the design needs by changing the values of the capacitors used in the circuit.   2. Short-circuited current is reduced because the PMOS P 4  and NMOS N 4  of the output stage will not be enabled simultaneously. In addition, reduced power dissipation is achieved because no DC current is produced during the operation of the circuit.   3. The circuit operation is accelerated because the loads at nodes A and C are reduced by separating the input signal at the input terminal from nodes A and C with the capacitors C 1  and C 2  respectively.   4. No external control signal is needed, thus contributing to the reduction in circuit complexity. The control signals involved in the circuit operation are generated internally.   5. The application of the low-threshold capacitor-coupling accelerator to a receiver connected to a long interconnect line can adjust the input signal to the receiver in low dissipation and at high speed.   6. Circuit operation is accelerated because the discharging and charging loops of the output stage employ a serially-connected NMOS and a serially-connected PMOS respectively.   7. The accelerator can be applied to bi-directional interconnect lines.       

   While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.