Abstract:
A constant-voltage power supply circuit includes a constant-voltage output unit and an output current restriction unit. The constant-voltage output unit includes an output transistor and controls the transistor based on output voltage from the output transistor to maintain the output voltage constant. The output current restriction unit restricts output current of the constant-voltage output unit. When the overcurrent detection unit detects that current flowing through the output transistor that is an overcurrent flowing continuously for a predetermined time, the output current restriction unit executes an output current restriction operation. This configuration prevents the output voltage from decreasing after an overcurrent control operation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This nonprovisional application is a continuation application of and claims the benefit of International Application No. PCT/JP2003/004968, filed Apr. 18, 2003. The disclosure of the prior application is hereby incorporated herein in its entirety by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a constant-voltage power supply circuit, and more particularly, to a constant-voltage power supply circuit provided with an overcurrent protection function. 
     A power supply circuit for supplying a constant-voltage power supply to devices such as a microprocessor unit (MPU) includes an overcurrent protection circuit. The overcurrent protection circuit prevents output of an overcurrent, which is generated when an electrical or mechanical failure occurs in a load. Such a constant-voltage power supply circuit is required to supply stable constant-voltage power while preventing generation of an overcurrent. 
       FIG. 7  is a schematic circuit diagram of a conventional constant-voltage power supply circuit  100 . When an external power supply V 1  goes on, a differential amplifier  1  is activated, and an output voltage of the differential amplifier  1  is applied to the gate of an output transistor T 1 , which is configured by a P-channel MOS (metal oxide semiconductor) transistor. 
     When the output transistor T 1  goes on and an output voltage Vout is output, the output voltage Vout is divided by feedback resistors R 1  and R 2  to generate divided voltage at node N 1 . The divided voltage is applied to a non-inversion input terminal of the differential amplifier  1 . A reference voltage V 2  is applied to an inversion input terminal of the differential amplifier  1 . 
     When the output voltage Vout increases, the potential at the node N 1  also increases. This increases the output voltage of the differential amplifier  1 . As a result, the drain current of the output transistor T 1  decreases and the output voltage Vout decreases. When the output voltage Vout decreases, the potential at the node N 1  also decreases. This decreases the output voltage of the differential amplifier  1 . As a result, the drain current of the output transistor T 1  increases and the output voltage Vout increases. Through such operations, the output voltage Vout converges on a constant voltage that is set based on the reference voltage V 2 . 
     Some of the drain current of the output transistor T 1  is supplied to the collector of an NPN transistor T 2  and the bases of transistors T 2  and T 3  via a resistor R 3 . The transistors T 2  and T 3  execute a current mirror operation. 
     A P-channel MOS transistor T 4 , which is operated based on the output voltage of the differential amplifier  1 , executes a current mirror operation with the output transistor T 1 . The size of the transistor T 4  is smaller than the size of the output transistor T 1 . 
     The drain current of the transistor T 4  is supplied to the collectors of the transistor T 3  and an NPN transistor T 5  and to the bases of the NPN transistor T 5  and an NPN transistor T 6 . The transistors T 5  and T 6  execute a current mirror operation. The collector of the transistor T 6  is connected to a resistor R 4  and to the gate of a transistor T 7 . 
     When the transistor T 6  is turned on and a collector current flows through the transistor T 6 , the gate voltage of the P-channel MOS transistor T 7  is lowered by the resistor R 4 . As a result, drain current flows through the transistor T 7 . This increases the gate voltage of the output transistor T 1 . As a result, the drain current of the output transistor T 1  decreases. 
     In the constant-voltage power supply circuit  100  during normal operation, the operation of the feedback resistors R 1  and R 2  and the differential amplifier  1  keeps the output voltage Vout constant while changing the output current Iout of the output transistor T 1 . In this state, the drain current of the transistor T 4  is entirely absorbed as the collector current of the transistor T 3 . This keeps the transistors T 5 , T 6 , and T 7  off. 
     When the output current Iout increases and reaches a predetermined overcurrent detection value I 1 , the drain current of the transistor T 4  cannot be further absorbed by the transistor T 3 . Thus, the transistors T 5  and T 6  are turned on. This turns on the transistor T 7  and increases the gate voltage of the output transistor T 1 , decrease the output current Iout, and decreases the output voltage Vout. When the output current Vout decreases, the transistors T 2  and T 3  are turned off. Thus, the drain current of the transistor T 4  keeps the transistors T 5 , T 6 , and T 7  on, and the gate voltage of the output transistor T 1  further increases. 
     As shown in  FIG. 8 , the output current Iout gradually decreases after the output current Iout reaches the overcurrent detection value I 1 . This gradually decreases the output voltage Vout. A predetermined restriction current I 2  is continuously output even after the output voltage Vout reaches 0 V. In this way, the output current Iout decreases after reaching the overcurrent detection value I 1 . This control prevents the load from being damaged by an overcurrent. 
     In the constant-voltage power supply circuit  100 , the restriction current I 2  is continuously output even after the output voltage Vout decreases to 0 V. In this state, when the load current decreases, the drain current of the transistor T 1  decreases and the drain current of the transistor T 4  decreases. This decreases the base currents of the transistors T 5  and T 6 . As a result, the drain current of the transistor T 7  decreases and the gate voltage of the output transistor T 7  decreases and the output current Iout increases. This increases the output voltage Vout and increases the base currents of the transistors T 2  and T 3 . Thus, the drain current of the transistor T 4  is absorbed by the transistor T 3 . As a result, the transistors T 5 , T 6 , and T 7  are turned off so that the constant-voltage power supply circuit  100  recovers to a state in which constant voltage Vout can be output. 
     SUMMARY OF THE INVENTION 
     However, in some recent devices, such as an MPU, there may be an instantaneous flow of excessive consumption current. In the constant-voltage power supply circuit  100 , the output voltage Vout decreases immediately when the output current Iout reaches the overcurrent detection value I 1 . This may cause the load circuit, which uses the output voltage Vout as its power supply, to function erroneously or fail to exhibit a predetermined performance. 
     Accordingly, the overcurrent detection value I 1  may be set at a larger value by enlarging the output transistor T 1  to increase the output current Iout and reduce the number of times the output voltage Vout decreases. However, this would increase the amount of heat generation and measures for solving this problem would be required. 
     The present invention provides a constant-voltage power supply circuit that minimizes decrease in output voltage after an overcurrent control operation is performed. 
     One aspect of the present invention is a constant-voltage power supply circuit provided with a constant-voltage output unit, including an output transistor in which output from the output transistor is controlled based on output voltage from the output transistor to maintain the output voltage at a constant voltage. An output current restriction unit restricts output current of the constant-voltage output unit. The output current restriction unit executes an output current restriction operation when current flowing through the output transistor is an overcurrent flowing continuously for a predetermined time. 
     Another aspect of the present invention is a constant-voltage power supply circuit provided with a constant-voltage output unit, including an output transistor in which output from the output transistor is controlled based on output voltage from the output transistor to maintain the output voltage at a constant voltage. An overcurrent detection unit connected to the constant-voltage output unit detects overcurrent flowing through the output transistor and generates a detection signal. An output current restriction unit connected to the overcurrent detection unit restricts output current of the constant-voltage output unit based on the detection signal of the overcurrent detection unit and removes the current restriction on the constant-voltage output unit when generation of the detection signal is stopped. The overcurrent detection unit includes a first control unit for generating the detection signal when the overcurrent flows continuously for a predetermined time or longer. 
     A further aspect of the present invention is a constant-voltage power supply circuit including an output transistor. A constant-voltage control unit is connected to the output transistor in which output from the output transistor is controlled based on output voltage from the output transistor to maintain the output voltage at a constant voltage. A first transistor executes a current mirror operation with the output transistor. A first overcurrent detection unit connected to the first transistor generates an overcurrent detection signal when overcurrent continuously flows through the output transistor for a predetermined time or longer based on output current of the first transistor. A second transistor executes a current mirror operation with the output transistor. A gate potential control unit, which is connected to the output transistor, the second transistor, and the first overcurrent detection unit, controls gate potential of the output transistor in response to the overcurrent detection signal to restrict current flowing through the output transistor. 
     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
         FIG. 1  is a schematic circuit diagram of a constant-voltage power supply circuit according to a first embodiment of the present invention; 
         FIG. 2  is an output voltage-output current graph showing the operation of the constant-voltage power supply circuit of  FIG. 1 ; 
         FIG. 3  is a schematic circuit diagram of a constant-voltage power supply circuit according to a second embodiment of the present invention; 
         FIG. 4  is a schematic circuit diagram of a constant-voltage power supply circuit according to a third embodiment of the present invention; 
         FIG. 5  is a schematic circuit diagram of a constant-voltage power supply circuit according to a fourth embodiment of the present invention; 
         FIG. 6  is a schematic circuit diagram of a constant-voltage power supply circuit according to a fifth embodiment of the present invention; 
         FIG. 7  is a schematic circuit diagram of a constant-voltage power supply circuit in the prior art; and 
         FIG. 8  is an output voltage-output current graph showing the operation of the constant-voltage power supply circuit of  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       FIG. 1  is a schematic circuit diagram of a constant-voltage power supply circuit  200  according to a first embodiment of the present invention. Like or same reference numerals are given to those components that are the same as the corresponding components of the prior art. 
     An output transistor T 1 , which has a source connected to an external power supply V 1  and a drain connected to an output terminal To, is connected to the ground GND via feedback resistors R 1  and R 2 . 
     A node N 1  between the feedback resistor R 1  and the feedback resistor R 2  is connected to a non-inversion input terminal of a differential amplifier  1 . A reference voltage V 2  is supplied to an inversion input terminal of the differential amplifier  1 . Output voltage of the differential amplifier  1  is supplied to the gate of the output transistor T 1 . The output transistor T 1 , the feedback resistors R 1  and R 2 , and the differential amplifier  1  enable an output voltage Vout, which is set based on the reference voltage V 2 , to be output as a constant voltage from the output terminal To during normal operation. 
     A P-channel MOS transistor T 11 , which has a source connected to the external power supply V 1  and a drain connected to the base of an NPN transistor T 12 , is connected to the ground GND via a resistor R 5 . The transistor T 11  has a gate supplied with the output voltage of the differential amplifier  1 . Thus, the transistor T 11  executes a current mirror operation with the output transistor T 1 . The transistor T 11  is smaller than the output transistor T 1  in size. 
     The transistor T 12  has a collector connected to the external power supply V 1  via a resistor R 6  and an emitter connected to the ground GND. Thus, when the drain current of the transistor T 11  increases, the transistor T 12  is turned on and the potential at the collector (node N 2 ) of the transistor T 12  decreases. 
     A P-channel MOS transistor T 13 , which has a source connected to the external power supply V 1  and a drain connected to the base of an NPN transistor T 14 , is connected to the ground GND via a resistor R 7 . The base of the transistor T 14  is connected to the ground GND via an N-channel MOS transistor T 15 . 
     The transistor T 13  has a gate supplied with the output voltage of the differential amplifier  1 . Thus, the transistor T 13  executes a current mirror operation with the output transistor T 1 . The transistor T 13  is smaller in size than the output transistor T 1  and larger in size than the transistor T 11 . The resistors R 5  and R 7  have the same resistance. Thus, the transistor T 13  operates at a higher speed than the transistor T 11 . 
     The transistor T 14 , which has an emitter connected to the ground GND and a collector connected to the drain of a P-channel MOS transistor T 16  and to the gates of the P-channel MOS transistor T 16  and a P-channel MOS transistor T 17 . The transistors T 16  and T 17  have sources connected to the external power supply voltage V 1 . The drain of the transistor T 17  is connected to the gate of the output transistor T 1 . The transistors T 16  and T 17  execute a current mirror operation. 
     When the drain current of the transistor T 13  increases when the transistor T 15  is off, the transistor T 14  is turned on. When the transistor T 14  is turned on, the transistors T 16  and T 17  are turned on. 
     A node N 2  is connected to an input terminal of an inverter circuit  2 . An output signal of the inverter circuit  2  is provided to a first input terminal of an AND circuit  3 , and is also provided to a second input terminal of the AND circuit  3  via a delay circuit  4 . 
     An output signal of the AND circuit  3  is provided to a signal input terminal of a latch circuit  5  as an input signal S. An output signal Q output from an output terminal of the latch circuit  5  is provided to a first input terminal of a NOR circuit  6 . 
     The output voltage Vout is supplied to a comparator  7 . The comparator  7  compares the output voltage Vout with a predetermined threshold voltage. The comparator  7  outputs a high (H) level output signal to an inverter circuit  8  when the output voltage Vout is higher than the threshold value and provides a low (L) level output signal to the inverter circuit  8  when the output voltage Vout is lower than the threshold value. 
     The threshold value used for the comparator  7  is set lower than a normal output voltage Vout and has hysteresis. More specifically, as shown in  FIG. 2 , a threshold value Vth 1 , which is used when the output voltage Vout decreases, and a threshold value Vth 2 , which is used when the output voltage Vout increases and which is larger than the threshold value Vth 1 , are set for the comparator  7 . 
     An output signal of the inverter circuit  8  is provided to a reset terminal of the latch circuit  5 , as a reset signal R, and to a second input terminal of the NOR circuit  6 . The latch circuit  5  latches an H level input signal S and outputs the latched input signal S as the output signal Q. The latch circuit  5  resets the output signal Q to an L level when the reset signal R rises to an H level. 
     An output signal of the NOR circuit  6  is provided to the gate of the transistor T 15 . When the output signal of the NOR circuit  6  rises to an H level, the transistor T 15  is turned on and the drain current of the transistor T 13  is absorbed by the transistor T 15 . Thus, the transistors T 14 , T 16 , and T 17  are turned off in this state. When the output signal of the NOR circuit  6  falls to an L level, the transistor T 15  is turned off. In this state, when the drain current of the transistor T 13  increases, the transistor T 14  is turned on, and the transistors T 16  and T 17  are turned on. 
     The following describes the operation of the constant-voltage power supply circuit  200 . 
     During normal operation, the differential amplifier  1 , the output transistor T 1 , and the feedback resistors R 1  and R 2  generate the output voltage Vout, which is a constant voltage. Thus, the differential amplifier  1 , the output transistor T 1 , and the feedback resistors R 1  and R 2  configure a constant-voltage output unit. The differential amplifier  1  and the feedback resistors R 1  and R 2  configure a constant-voltage control unit. 
     During generation of the constant voltage, the drain current of the transistor T 11  is relatively small and the transistor T 12  is off. Thus, the voltage at the node N 2  is maintained at an H level, and an output signal having an L level is output from the inverter circuit  2 . Accordingly, the output signal of the AND circuit  3  has an L level, and the output signal of the latch circuit  5  also has an L level. Further, the output voltage Vout is higher than the threshold value Vth 1  of the comparator  7 . Thus, the comparator  7  outputs an output signal having an H level, and the inverter circuit  8  outputs an output signal having an L level. In this state, the NOR circuit  6  is provided with input signals having an L level. Thus, the NOR circuit  6  outputs an output signal having an H level, and the transistor T 15  is turned on. The transistors T 14 , T 16 , and T 17  are maintained in an off state. 
     In this state, when a load circuit connected to the output terminal To short-circuits increases the output current Iout of the output transistor T 1 , the drain current of the transistor T 11  also increases. Further, the base potential at the transistor T 12  increases. Then, when the output current Iout exceeds the predetermined overcurrent detection value I 1 , the transistor T 12  is turned on. This decreases the voltage at the node N 2  to an L level and raises the output signal of the inverter circuit  2  to an H level. 
     When the output current Iout exceeds the overcurrent detection value I 1  during a period exceeding a delay time, which is set by the delay circuit  4 , the output signal of the AND circuit  3  rises to an H level and the output signal Q of the latch circuit  5  rises to an H level. Therefore, the output signal of the NOR circuit  6  falls to an L level, and the transistor T 15  is turned off. When the transistor T 15  is turned off, the drain current of the transistor T 13  turns on the transistor T 14 . This turns on the transistors T 16  and T 17 . As a result, the drain current of the transistor T 17  increases the gate potential of the output transistor T 1 . As shown in  FIG. 2 , the output current Iout is instantaneously restricted at the restriction current value I 2 . The latch circuit  5  holds this restricted state (as indicated by the broken line). 
     The transistors T 11  and T 12  and the resistors R 5  and R 6  configure an overcurrent detection unit. The transistors T 13 , T 14 , T 16 , and T 17 , and the resistor R 7  configure an output current restriction unit. 
     The delay time of the delay circuit  4  is set so that it is longer than the period during which a large consumption current flows through a device, which serves as the load, and so that the heat generation amount of the device does not become too large. This setting of the delay time of the delay circuit  4  prevents the device, which serves as the load, from functioning erroneously. 
     When the output current Iout is restricted at the restriction current value I 2 , the output voltage Vout decreases and becomes lower than the threshold value Vth 1  of the comparator  7 . Thus, the output signal of the comparator  7  falls to an L level, and the output signal of the inverter circuit  8  rises to an H level. As a result, the output signal Q of the latch circuit  5  is reset to an L level, and the output signal of the NOR circuit  6  is held at an L level. 
     Subsequently, when the short-circuited state of the load circuit is corrected and the output circuit Iout decreases, the output voltage Vout increases. When the output voltage Vout exceeds the threshold value Vth 2  of the comparator  7 , the output signal of the comparator  7  rises to an H level. Then, the output signal of the inverter circuit  8  falls to an L level, and the output signal of the NOR circuit  6  rises to an H level. Further, the transistor T 15  is turned on, and the transistors T 14 , T 16 , and T 17  are turned off. As a result, the constant-voltage output unit autonomously returns to normal operation and generates the output voltage Vout as a constant voltage. 
     When the output current Iout instantaneously increases during a period that does not exceed the delay time, which is set by the delay circuit  4 , while a constant voltage is being output, the output current Iout, which corresponds to the value of the output voltage Vout (constant voltage value) and the driving capability (i.e., constant voltage) of the output transistor T 1 , may be supplied to the load until it reaches its maximum value. The value of the output voltage Vout is set by the external power supply V 1  and the reference voltage V 2 . The driving capability of the output transistor T 1  is determined by the size of the transistor T 1 . 
     When the constant voltage is being output, if the output current Iout instantaneously increases causing the output current Iout supplied the load to become greater than or equal to the driving capacity of the transistor T 1  and causing the output voltage Vout to become lower than the threshold value Vth 1  of the comparator  7 , the output signal of the comparator  7  falls to an L level. Thus, the output signal of the NOR circuit  6  falls to an L level and the transistors T 14 , T 16 , and T 17  are turned on. This restricts the output current Iout. This operation is executed even when the period during which the output current Iout is greater than or equal to the overcurrent detection value I 1  does not exceed the delay time set by the delay circuit  4 . 
     The following describes the operation of the constant-voltage power supply circuit  200  when the constant-voltage power supply circuit  200  is activated by the external power supply V 1 . When the activation of the external power supply V 1  increases the power supply voltage, the reference voltage V 2  is supplied to the differential amplifier  1  to operate the differential amplifier  1 . In this state, the output voltage Vout is equal to the potential of the ground GND. Thus, the operation of the differential amplifier  1  turns on the output transistor T 1  and increases the output voltage Vout. 
     In this state, the output voltage Vout is still at an L level. Thus, the comparator  7  outputs an output signal having an L level, the NOR circuit  6  outputs an output signal having an L level, and the transistor T 15  is turned off. Further, the inverter circuit  8  outputs an output signal having an H level, and the output signal Q of the latch circuit  5  is reset to an L level. Thus, when the drain current of the output transistor T 1  increases, the transistors T 14 , T 16 , and T 17  are turned on. This restricts the output current Iout. 
     When the output voltage Vout exceeds the threshold value Vth 2  of the comparator  7 , the output signal of the comparator  7  rises to an H level, the input signals of the NOR circuit  6  both fall to an L level, and the output signal of the NOR circuit  6  rises to an H level. Then, the transistor T 15  is turned on and the transistors T 14 , T 16 , and T 17  are turned off. This stops the output current control operation. Then, the operation of the constant-voltage output unit outputs the output voltage Vout, which is a constant voltage. 
     The constant-voltage power supply circuit  200  has the advantages described below. 
     (1) The operation of the output current restriction unit keeps the output current Iout less than or equal to the overcurrent detection value I 1  when the output current Iout exceeds the overcurrent detection value I 1  during a period longer than or equal to the predetermined time, which is set by the delay circuit  4 . 
     (2) When the period during which the output current Iout exceeds the overcurrent detection value I 1  is shorter than the predetermined time set by the delay circuit  4 , the output current Iout is not restricted. This prevents the output voltage Vout from decreasing. Accordingly, a decrease in the output voltage Vout, which would be caused by an instantaneous overcurrent, is prevented without enlarging the output transistor T 1 . 
     (3) When the output current restriction unit restricts the output current Iout and the output voltage Vout decreases, the cause of the overcurrent factor of the output current Iout is eliminated. Thus, when the output voltage Vout increases, the output current restriction unit automatically stops operating, and the output current restriction unit autonomously returns to execute a constant voltage output operation. 
     (4) When the output voltage Vout decreases and becomes less than or equal to the threshold value Vth 1 , which is set in the comparator  7 , the output current restriction unit operates irrespective of the output current Iout. This prevents the output current Iout from being an overcurrent. 
     (5) The output current restriction unit operates when the circuit  200  is powered on. This prevents an overshoot of the output voltage Vout and the output current Iout. 
     (6) During normal constant voltage operation, the transistors T 12 , T 14 , and T 16  are maintained in an off state. This reduces current consumption of the circuit  200 . 
     Second Embodiment 
       FIG. 3  is a schematic circuit diagram of a constant-voltage power supply circuit  300  according to a second embodiment of the present invention. In the second embodiment, the resistor R 6  in the first embodiment is replaced by a current source  9 . The other parts are the same as in the first embodiment. 
     Due to this configuration, the constant-voltage power supply circuit  200  has the same advantages as the first embodiment. 
     Third Embodiment 
       FIG. 4  is a schematic circuit diagram of a constant-voltage power supply circuit  400  according to a third embodiment of the present invention. In the third embodiment, the transistor T 11  in the first embodiment is replaced by a PNP transistor T 18 , and the transistor T 13  in the first embodiment is replaced by a PNP transistor T 19 . 
     Resistors R 8  and R 9  are connected between the external power supply V 1  and the source of the output transistor T 1 . Further, the base of the transistor T 18  is connected to a node between the resistors R 8  and R 9 . The base of the transistor T 19  is connected to a node between the resistor R 9  and the source of the output transistor T 1 . 
     In such a configuration, the collector currents of the transistors T 18  and T 19  increase when the output current Iout increases. Thus, the third embodiment has the same advantages as the first embodiment. 
     The transistors T 18  and T 19  have different base potentials. Thus, even if the transistors T 18  and T 19  are equal in size, the transistors T 18  and T 19  operate in the same manner as the transistors T 11  and T 13  in the first embodiment. More specifically, the base potentials of the transistors T 18  and T 19  are set so that the transistor T 19  operates at a higher speed than the transistor T 18 . Further, the overcurrent detection value I 1  is easily adjusted by adjusting the resistances of the resistors R 8  and R 9 . 
     Fourth Embodiment 
       FIG. 5  is a schematic circuit diagram of a constant-voltage power supply circuit  500  according to a fourth embodiment of the present invention. In the fourth embodiment, the transistors T 12  and T 14  in the first embodiment are replaced by N-channel MOS transistors T 20  and T 21 . 
     In such a configuration, the constant-voltage power supply circuit  500  has the same advantages as the first embodiment. 
     Fifth Embodiment 
       FIG. 6  is a schematic circuit diagram of a constant-voltage power supply circuit  600  according to a fifth embodiment of the present invention. In the fifth embodiment, the structure of the output current control unit in the first embodiment is changed. 
     Specifically, the drain of the transistor T 13  is connected to the collector of the NPN transistor T 22  and to the bases of the NPN transistors T 22  and T 23 . The transistors T 22  and T 23  configure a current mirror circuit. 
     The collector of the transistor T 23  is connected to the external power supply V 1  via the resistor R 10 . The P-channel MOS transistor T 24  has a source connected to the external power supply V 1  and a drain connected to the gate of the output transistor T 1 . The gate of the transistor T 24  is connected to the collector of the transistor T 23 . 
     In such a configuration, the transistors T 22  and T 23  execute a current mirror operation based on the drain current of the transistor T 13  when the transistor T 15  is off. When the drain current of the transistor T 23  increases, the transistor T 24  is turned on. This increases the gate potential at the output transistor T 1 . 
     The constant-voltage power supply circuit  600  has the same advantages as the first embodiment. 
     The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.