Abstract:
A flat panel display device which is capable of preventing in-line shorts by forming as a face plate a common power line impressing an equal power supply to all pixels. The flat panel display includes a power supply layer formed on an insulation substrate and connected with source/drain electrodes through contact holes; and an insulating layer formed with a contact hole to insulate the power supply layer and a thin film transistor, wherein the thin film transistor is formed over the insulating layer and includes the source/drain electrodes.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a divisional application of U.S. application Ser. No. 10/292,627, filed Nov. 13, 2002, now pending, the disclosures of which are incorporated by reference. This application also claims the benefit of Korean Application No. 2001-79579, filed Dec. 14, 2001, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the invention  
         [0003]     The present invention relates to a flat panel display device, and more particularly, to an organic electroluminescent display device which is capable of preventing in-line shorts and dropping of a supply voltage by forming a common power supply layer as a face plate.  
         [0004]     2. Description of Related Art  
         [0005]      FIG. 1A  illustrates the cross-sectional structure of a conventional organic electroluminescent display device.  FIG. 1B  illustrates the plan structure of a conventional organic electroluminescent display device.  FIG. 1A  illustrates the cross-sectional structure for one pixel region  15  as a cross-sectional structure taken along the line I-I of  FIG. 1B .  
         [0006]     Referring to  FIG. 1A , a transparent insulation substrate  10  is divided into a first region  11  in which a pixel electrode is formed and a second region  12  in which a thin film transistor (TFT) and a capacitor are formed. A buffer layer  15  is formed on the insulation substrate  10 , and a thin film transistor and a capacitor are formed in the second region  12  at the upper part of the buffer layer  15 .  
         [0007]     The thin film transistor is formed on the buffer layer  15  and equipped with a semiconductor layer  20  having source/drain regions  21  and  22 , a gate electrode  31  on a gate insulating layer  30  and source/drain electrodes  51  and  52  which are formed on an interlayer insulating layer  40  so as to be respectively connected to the source/drain regions  21  and  22  through contact holes  41  and  42 . The capacitor comprises a first electrode  32  formed on the gate insulating layer  30  and a second electrode  53  formed on the interlayer insulating layer  40  so as to be connected to the source electrode  51 . A part interposed between the first and second electrodes  32  and  53  of the capacitor in the interlayer insulating layer  40  functions as a dielectric layer of the capacitor.  
         [0008]     On the other hand, an organic electroluminescent display device is formed in the first region  11 . The organic electroluminescent display device is equipped with a first pixel electrode  70  which is formed on a passivation layer  60  so as to be connected to the drain electrode  52  through a via hole  61 , an organic electroluminescent EL layer  90  formed on the first pixel electrode  70  in an opening part  81  and a second pixel electrode  95  which is formed on a planarization layer  80  comprising the organic EL layer  90 .  
         [0009]     Referring to  FIG. 1B , the organic electroluminescent display device is equipped with a plurality of signal lines, i.e., gate lines  35  used in selecting pixels, data lines  55  impressing data signals and power supply lines  56  giving a reference voltage required in driving a thin film transistor to drive by impressing an equal common voltage to all pixels.  
         [0010]     Pixels are respectively arranged per each pixel regions limited by the signal lines  35 ,  55  and  56 , wherein each of the pixels comprises a plurality of thin film transistors connected to the signal lines, for example, two transistors, one capacitor and an organic electroluminescent display device.  
         [0011]     In fabricating a conventional organic electroluminescent display device, a first electrode  32  of capacitor and gate lines  35  are formed when forming the gate electrode  31  while a second electrode  53  of the capacitor, data lines  55 , and power supply lines  56  are formed when forming the source/drain electrodes  51 ,  52 , wherein one of the source/drain electrodes, for example, a source electrode  51  and a second electrode  53  of a capacitor are formed by being connected to the power supply lines  56 .  
         [0012]     Since the signal lines should be formed so that each of two signal lines are electrically separated on a layer as described above, there have been problems in that an in-line short ( 59  in  FIG. 1B ) occurs between data lines  55  and power supply lines  56  which are respectively adjacently arranged by conductive particles generated during the processing, and line defects are generated accordingly.  
         [0013]     Furthermore, it is impossible to form a power supply line as a face plate, and the signal lines should be formed by patterning the power supply line in a line shape since each of the different two signal lines must exist on a layer. Accordingly, voltage drops are generated depending on positions to which a common voltage is impressed resulting in voltage non-uniformity, and resistance is increased due to line shape patterning resulting in a drop in voltage.  
         [0014]     On the other hand, there have been problems in that the foregoing in-line shorts and drops in voltage are generated since two signal lines exist on one layer even in the case that the gate lines and power supply lines are formed at the same time while data lines are separately formed.  
       SUMMARY OF THE INVENTION  
       [0015]     Accordingly, it is an object of the present invention to provide a flat panel display device preventing in-line shorts by forming a power supply line as a face plate, and a method of fabricating such a flat panel display device.  
         [0016]     It is another object of the present invention to provide a flat panel display device which is capable of preventing a drop in supply voltage, and a method of fabricating such a flat panel display device.  
         [0017]     Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.  
         [0018]     The foregoing and other objects of the present invention are achieved by providing a flat panel display device comprising: a power supply layer formed on an insulation substrate and connected with source/drain electrodes through contact holes; and an insulating layer formed with a contact hole to insulate the power supply layer and a thin film transistor, wherein the thin film transistor is formed over the insulating layer and includes the source/drain electrodes.  
         [0019]     The foregoing and other objects of the present invention may also be achieved by providing a method of fabricating a flat panel display device comprising: forming a power supply layer on an insulation substrate; forming an insulating layer on the power supply layer; forming a contact hole exposing a portion of the power supply layer by etching the insulating layer; and forming an island shaped conductive pattern connected to the power supply layer through the contact hole. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     These and other objects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:  
         [0021]      FIG. 1A  is a cross-sectional view of a conventional organic electroluminescent display device.  
         [0022]      FIG. 1B  is a plan view of a conventional organic electroluminescent display device.  
         [0023]      FIG. 2A  is a cross-sectional view of an organic electroluminescent display device according to an embodiment of the present invention.  
         [0024]      FIG. 2B  is a plan view of an organic electroluminescent display device according to the embodiment of  FIG. 2A .  
         [0025]      FIG. 3  is a cross-sectional view of an organic electroluminescent display device according to another embodiment of the present invention.  
         [0026]      FIG. 4A  is a drawing illustrating a connection structure between a power supply layer and source/drain electrodes according to the embodiment of  FIG. 2A .  
         [0027]      FIG. 4B  is a drawing illustrating a connection structure between a power supply layer and source/drain electrodes according to another example of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.  
         [0029]      FIG. 2A  illustrates the cross-sectional view of an organic electroluminescent display device according to an embodiment of the present invention, and  FIG. 2B  illustrates the plan structure of an organic electroluminescent display device according to the embodiment of  FIG. 1 , wherein  FIG. 2A , as a sectional structure taken along a line II-II of  FIG. 2B , illustrates the cross-sectional view for one pixel region  104 .  
         [0030]     Referring to  FIG. 2A  and  FIG. 2B , an insulation substrate  100  is provided, which is equipped with a first region  101  in which a pixel electrode is formed and a second region  102  in which a TFT and a capacitor are formed. A face plate type power supply layer  105  is formed by depositing an electrode material having a low resistance on the front surface of an insulation substrate  100 . A buffer layer  115  is formed on the power supply layer  105  formed as a face plate.  
         [0031]     A semiconductor layer  120  is formed on the buffer layer  115  of the second region  102 , a gate insulating layer  125  is formed on the front surface of the substrate comprising the semiconductor layer  120 , and a gate  131  and a first electrode  132  of the capacitor are simultaneously formed on the gate insulating layer  125  at the upper part of the semiconductor layer  120 . Subsequently, source/drain regions  121  and  122  are formed by ion implanting one of n-type or p-type impurities into the semiconductor layer  120 , wherein a part  123  of the semiconductor layer  120  below the gate  131  acts as a channel layer.  
         [0032]     Successively, an interlayer insulating layer  135  is formed on the gate insulating layer  125  comprising the gate  131  and the first electrode  132  of the capacitor. First and second contact holes  136  and  137  respectively exposing the source/drain regions  121  and  122  and a third contact hole  139  exposing a portion of the power supply layer  105  are simultaneously formed by etching the interlayer insulating layer  135 .  
         [0033]     Source/drain electrodes  141  and  142  respectively contacting the source/drain regions  121 ,  122  through the first and second contact holes  136  and  137  and a second electrode  143  of the capacitor connected to one of the source/drain electrodes  141  and  142 , for example, the source electrode  141 , are simultaneously formed by patterning the deposited interlayer insulating layer  135  after depositing source/drain electrode materials on the interlayer insulating layer  135 .  
         [0034]     Therefore, one of the source/drain electrodes, e.g., the source electrode  141 , and the second electrode  143  of the capacitor are connected to the power supply layer  105  of the face plate through the contact hole  139  .  
         [0035]     In one aspect of the present invention, a mask process is not added since a contact hole  139  to connect the power supply layer  105  to one of the source/drain electrodes is formed simultaneously when forming contact holes  136  and  137  for the source/drain electrodes.  
         [0036]      FIG. 4A  illustrates the connection state between a face plate shaped power supply layer and source/drain electrodes according to this embodiment of the present invention. Referring to  FIG. 4A , a power supply layer  105  is formed on the substrate in a face plate shape, a contact hole  139  exposing a portion of the power supply layer  105  is equipped at each pixel region  104 , and an island shaped conductive pattern  145  is connected to the power supply layer  105  through the contact hole  139 .  
         [0037]     As illustrated in  FIG. 2B , a part of the conductive pattern  145  acts as a source electrode  141  connected through the contact hole  139  while a residual part of the conductive pattern  145  acts as a second electrode  143  of the capacitor. That is, although a conventional organic electroluminescent display device has a structure wherein a second electrode  53  of the capacitor and a source electrode  51  are extended from a power supply line  56 , as illustrated in  FIG. 1B , a conductive pattern functioning as a source electrode  141  and a second electrode  143  of the capacitor has an island shape since the power supply layer  105  is formed in a face plate shape in an embodiment of the present invention.  
         [0038]     A passivation layer  150  is formed on an interlayer insulating layer  135 , the source/drain electrodes  141  and  142  and the second electrode  143  of the capacitor, with a via hole  155  exposing a portion of one of the source/drain electrodes  141  and  142 , e.g., the drain electrode  142 .  
         [0039]     Subsequently, a pixel electrode  160 , connected to the exposed drain electrode  142  through the via hole  155 , is formed on the passivation layer  150 , and a planarization layer  170  is deposited on the passivation layer  150  comprising the pixel electrode  160 . An opening part  175  exposing a portion of the pixel electrode  160  is formed by etching the planarization layer  170 . An EL layer  180  is formed in the opening part  175 , and a cathode electrode is formed on the EL layer  180  as a transparent electrode  190 .  
         [0040]     The formation of a power supply layer  105  into a face plate shape does not affect the operation of the device since the organic electroluminescent display device of the present invention is a front light emitting type. Furthermore, a face plate structure can be adopted without affecting the operation of the device when forming the power supply layer  105  as a transparent face plate where the organic electroluminescent display device of the present invention is applied to a back light emitting structure.  
         [0041]     Since a common power line is formed as a face plate in an embodiment of the present invention, as illustrated in  FIG. 2B , not only a drop in supply voltage is minimized, but also non-uniformity of voltage depending on positions to which the voltage is impressed is prevented by impressing a common supply voltage to four directions, as shown by arrows.  
         [0042]     Although it is described above that a technology of the present invention using of a common power line as a face plate is applied to an organic electroluminescent display device, it can also be applied to an active matrix liquid crystal display device. Furthermore, although the present invention illustrates a structure in which a face plate is formed on a substrate at the lower part of a semiconductor layer, a formation position of the face plate can be altered according to the structure of a thin film transistor. Additionally, a part corresponding to a thin film transistor or electrodes in the power supply layer can be patterned so as to remove the effect of backside bias of the thin film transistor, as illustrated in  FIG. 4B .  
         [0043]     In a back light emitting structure, a pixel electrode must be formed in regions other than TFT regions. However, in the case where an electroluminescent display device employs a face plate emitting structure, an opening ratio can be improved since a pixel electrode  360  may be formed over all pixel regions, as shown in  FIG. 3 .  
         [0044]     The forgoing organic electroluminescent display device according to the embodiments of the present invention has merits in that in-line shorts and a drop in voltage are prevented by forming a common power supply layer in a face plate shape, and an additional mask process is not required by simultaneously forming contact holes to connect the common power line, the source/drain electrodes and the capacitor when forming the source/drain contact holes.  
         [0045]     Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.