Abstract:
Symmetrical, direct coupled laser drivers for high frequency applications. The laser drivers are in integrated circuit form and use a minimum of relatively small (low valued) external components for driving a laser diode coupled to the laser driver through transmission lines. An optional amplifier may be used to fix the voltage at an internal node at data frequency spectrum to improve circuit performance. Feedback to a bias input may also be used to fix the voltage at the internal node. Programmability and a burst mode capability may be included.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/352,011 filed Jan. 17, 2012 which claims the benefit of U.S. Provisional Patent Application No. 61/440,539 filed Feb. 8, 2011. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to the field of laser drivers, and more particularly to laser drivers for high frequency applications. 
         [0004]    2. Prior Art 
         [0005]    Laser drivers are well known in the prior art. However, current operating requirements at increased frequencies, lower voltages and higher efficiencies exceed the performance of current designs. Representative prior art laser driver designs may be found in U.S. Pat. Nos. 7,181,100 and 7,457,336, US Published Application Nos. 2009/0268767 and 2009/0201052. Some products currently on the market are described in data sheets MAX3656 and MAX3946 (Maxim Integrated Products, Inc.), ONET4201LD (Texas Instruments) and ADN2526 (Analog Devices). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is simplified circuit diagram of an embodiment of the present invention. 
           [0007]      FIG. 2  is simplified circuit diagram of another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0008]    Referring to  FIG. 1 , a circuit diagram for a preferred embodiment of the present invention may be seen. The circuitry in the rectangular outline labeled “External” is the only external circuitry needed, with the other circuitry shown being within a single integrated circuit. The external circuitry includes the laser diode LD coupled to the integrated circuit terminals OUTA and OUTC through transmission lines TL 1  and TL 2 . An inductor L 1  is connected between integrated circuit terminals VCC and OUTA, and a bypass capacitor is connected between VCC and the circuit ground. An inductor L 2  is connected between the OUTC and the VBIAS terminals, and capacitor C 2  is connected between the VBIAS terminal and the circuit ground. 
         [0009]    The outputs OUTA and OUTC coupled through the transmission lines to the anode and cathode of the laser diode LD, respectively, are connected to the collectors of transistors T 3  and T 2 , respectively. Transistor T 3 , biased by the bias voltage vcb, is a cascode transistor for transistor T 1  of the differential transistor pair T 1  and T 2 , which have their emitters coupled together and to ground through resistor R 3 . The collector of transistor T 3  is coupled to the anode connection of laser diode LD through output terminal OUTA and transmission line TL 1 , and to the VCC terminal of the integrated circuit through resistor R 1  and external inductor L 1 . No cascode transistor is used for transistor T 2  of the differential pair because of the lack of voltage headroom, the headroom for cascode transistor T 3  effectively being provided by the voltage drop across laser diode LD itself. Note that the drive provided by transistors T 1  and T 2  is a symmetrical differential drive for the laser diode LD. 
         [0010]    The inputs to the bases of the differential pair T 1  and T 2  are the differential data inputs mod−′ and mod+′, respectively, which are the outputs of amplifier A 4 . Amplifier A 4  provides a plus and minus differential output having a fixed differential voltage, with voltages set by the programmable I mod level block and with a state responsive to the inputs mod+ and mod−. With this connection, the transistor that is on at any one time (T 1  or T 2 ) will conduct a current equal to its base voltage minus its Vbe, all divided by the R 3 . Thus transistors T 1  and T 2  act as current sources so that rather than being on and off, each act as a current source or is off, responsive to the digital data inputs mod+ and mod−. User programmability of circuits and control loops in general are well known in the art, as is the biasing of a transistor as a current source, and accordingly are not shown in detail herein. As an alternative, the resistor R 3  might be a programmable current source, though there may not be enough voltage headroom for such an embodiment, depending on the voltage VCC of the power source. 
         [0011]    A second differential transistor pair T 5  and T 6  have their emitters connected together and to the circuit ground through resistor R 4 . The collector of transistor T 5  is connected to cascode transistor T 4  having its base and collector connected in common with the base and collector of cascode transistor T 3 , respectively. Transistor T 6  has its collector connected through capacitor C 3  to the VCC terminal of the integrated circuit, and to resistor R 2 . The other end of resistor R 2  is connected to the collector of transistor T 2  and to the cathode of the laser diode LD through integrated circuit terminal OUTC and transmission line TL 2 . The bases of transistors T 5  and T 6  are coupled as burst enable inputs bias−′ and bias+′, respectively, from amplifier A 1  which controls the base voltages of transistors T 5  and T 6  responsive to the signals bias+ and bias−, and at voltage levels set by the Programmable I bias level block. Thus transistors also act as separately user programmable current sources like those of transistors T 1  and T 2  for the digital data inputs mod+ and mod−. In  FIG. 1 , the connections between the integrated circuit and the terminals VCC, OUTA, OUTC and VBIAS are shown as inductors, as the inductance of these connections at the high frequencies at which the present invention operates is meaningful and should be taken into consideration. 
         [0012]    In one embodiment, additional circuitry is added to the input circuitry, namely to override the data inputs mod− high and mod+ low when bias− is high and bias+ is low, independent of any actual data inputs the circuit may receive. This allows multiple laser drivers to share a communication channel in a time division multiplexing scheme where only one transmitter is enabled at any times. Of course the override is immediately released when bias+ goes high and bias− goes low (output burst enabled). As an example, such an override can be implemented various ways using simple logic functions. 
         [0013]    The impedance of the typical laser diode is on the order of 5 to 10 ohms differentially, so there is a substantial impedance mismatch between the transmission lines (25 ohm transmission lines or 50 ohm differentially in one embodiment) coupled to the laser diode LD. However, resistors R 1  and R 2  are chosen to match the transmission lines, and provide the termination for the signal reflected back from the laser diode LD through the transmission lines, resistor R 1  being directly connected to VCC and R 2  being AC coupled to VCC through capacitor C 3  at the frequencies of operation. Thus there is symmetry in the external circuitry as well as in the drive and termination of the 25 ohm transmission lines. 
         [0014]    When the output burst is not enabled (and mod− is held high and mod+ is held low as previously described), there is no current through the laser diode LD as there is no DC connection to its cathode. Thus there is no light emission from the laser diode. The voltage at OUTA is essentially VCC, i.e., the voltage across inductor L 1  is essentially zero because of its low resistance. When the output burst is enabled and mod+ is high for transmitting a “1”, current flows through the laser diode LD, with a primary current path through transistor T 2  and resistor R 3  to the circuit ground, transistor T 2  acting as a current source controlled by the output voltage levels of amplifier A 4 , which in turn provides output voltage levels controlled by the programmable I mod level block). 
         [0015]    When the output burst is enabled and Mod− is high for transmission of a “0”, transistor T 2  will be off. Now the component of the current through the laser diode LD and transistor T 2  is off, so that the only remaining component of current is that though resistor R 2 , transistor T 6  and resistor R 4 . Note that in essence, transistors T 2  and T 1  steer the current component of the current sources of transistors T 2  and T 1  through the laser diode LD through and around the laser diode, respectively. This in turn means that the average current through external inductor L 1  is constant, independent of whether a “1” or a “0” is being transmitted. 
         [0016]    It may be seen from the foregoing that the structure of the laser driver just described and illustrated in  FIG. 1  is a symmetrical, differential direct coupled laser driver structure with burst mode capabilities. Of particular interest is the fact that the data and bias loops are coupled together, the current for the transmission of a “1” being coupled through the bias loop. 
         [0017]    Circuit performance may be optionally improved by actively fixing the voltage of the node VBIAS, at least with respect to high frequency signals (i.e., signals in the data frequency spectrum, as opposed to low frequencies which are frequencies well below the data frequency spectrum). For this purpose, the optional circuit in the box at the left of  FIG. 1  can be added. This circuit is, in essence, an amplifier A(s) with a complex transfer function and with a feedback resistor R 7  as shown in the oval outline in  FIG. 1 . It has an output impedance for the output VBIAS that is very low at the high frequencies, i.e., looks like a voltage source, but which is very high for low frequencies, i.e., looks like a current source. At high frequencies, it can be considered to make capacitor C 3  look very large, thereby improving the termination of the cathode and thus the circuit balance. At low frequencies, the circuit will seek an output VBIAS equal to the average voltage on the node to which it is connected. 
         [0018]    Now referring to the circuit to the left of  FIG. 1  within the outline, transistor T 7  is coupled through resistor R 5  as an emitter follower biased by current source I 1 . The circuit to the left of transistor T 7  is an amplifier responsive at high frequencies to changes in the voltage on the emitter of transistor T 7 , the voltage VBIAS, by feedback through resistor R 7 , to adjust the voltage on the base of transistor T 7  to cancel or greatly reduce such changes. 
         [0019]    In particular, a change in the voltage VBIAS changes the current through transistor T 8 , changing the voltage drop across resistor R 6 , coupling that change through the base emitter voltage of transistor T 9  biased by current source  13  to the base of transistor T 11 . This changes the current through transistor T 11  which causes the voltage drop through resistor R 8  to change, feeding this change back to the base of transistor T 7  to resist the change in VBIAS that initiated the disturbance. 
         [0020]    The bases of transistors T 7  and T 8  are coupled to VCC through resistors R 8  and R 9 , respectively, and to the collectors of differential transistor pair T 11  and T 10 , respectively. The base of transistor T 10  is connected to a reference voltage, with the common emitter connection of transistors T 10  and T 11  being biased by the current through transistor T 12 . The voltage on capacitor C 6  connected to the gate of transistor T 12  integrates the output of the voltage controlled current source  14  (transconductance Gm), which is proportional to the difference in voltages on the collectors of transistors T 7  and T 8 . If at a low frequency (relative to the data frequencies), VBIAS changes, that will cause a current through resistor R 5 , which in turn will cause a change in voltage on capacitor C 4 . That causes a voltage difference across voltage controlled current source  14 , unbalancing the voltage across the voltage controlled current source  14  to charge or discharge capacitor C 6  until the circuit settles at the new value of VBIAS. 
         [0021]    Capacitor C 4  provides a capacitive load on the collector of transistor T 7  at data frequencies to limit the fluctuations of the voltage on the collector of transistor T 7  to avoid saturation of the transistor. Capacitor C 5 , on the other hand, determines the circuit response to frequencies in a mid-frequency range. 
         [0022]    As an alternative to the circuit at the left of  FIG. 1 , the disturbances in VBIAS at data frequencies may be substantially eliminated using the circuit of  FIG. 2 . This circuit, like that of  FIG. 1 , senses any attempted change in VBIAS at data frequencies, but in addition to directly adjusting VBIAS, provides feedback to transistors T 5  and T 6  so that transistor T 6  will also provide (or absorb) the current component that is attempting to vary VBIAS at the data frequencies. The end result is the same as that achieved by the circuit at the left of  FIG. 1 , though the feedback is both directly to VBIAS itself as in the circuit of  FIG. 1 , and indirectly to VBIAS through transistor T 6 . 
         [0023]    Referring again to  FIG. 2 , resistors R 4 , R 5  and R 7 , transistors T 5 , T 6  and T 7 , current source I 1  and signals bias+ and bias− are the same as in  FIG. 1 , the rest of the right side of  FIG. 1  being omitted in  FIG. 2  for clarity, though could be identical to that of  FIG. 1 . In operation, resistor R 7  senses any change in the VBIAS voltage, which change is amplified by amplifier A′(s) and fed back to the base of transistor T 7 . Amplifier A′(s) can have a transfer function f(s) that produces the same VBIAS voltage characteristics (acts like a voltage source at data frequencies and as a current source at low frequencies) as the circuit in the box at the left of  FIG. 1 . Actually taking out amplifiers A 2  and A 3 , the circuit shown in  FIG. 2  may be considered a simplified representation of the corresponding part of the circuit of  FIG. 1 . 
         [0024]    Amplifier A 1  is shown in  FIG. 1 , though with only one programmable input for bias control. In  FIG. 2 , additional inputs are provided for control through amplifiers A 2  and/or A 3 . Normally both path  2  and path  3  would not be used, and without path  2  and path  3 , but only path  1 , one has a simplified version of the respective part of the circuit of  FIG. 1 . Again, paths  1 ,  2  and  3  may be eliminated, though performance is improved and the size of the external components, especially inductor L 2  and capacitor C 2  may be reduced by using at least feedback path  1 , as previously described. Also if path  2  is used (i.e., paths  1  and  2  are used), then capacitor C 4  may be eliminated, or substantially reduced in capacitance. 
         [0025]    The present invention has been disclosed and described with respect to npn transistors, though it should be noted that it can be implemented in other technologies, such as by way of example, using NMOS transistors. In any case, each transistor, regardless of type, may be characterized as having first, second and third terminals wherein the voltage between the first (emitter or source) and second terminals (base or gate) controls the conduction of current between the third (collector or drain) and first (emitter or source) terminals. Also transistors T 3  and T 4  are cascode transistors, and may be eliminated if desired, as long as transistors T 1  and T 5  can handle the higher voltage that they will be subjected to. In that regard, the topology of the invention may be inverted and implemented with transistors of the opposite conductivity type. 
         [0026]    There have been disclosed herein symmetrical, differential direct coupled laser driver structures with burst mode capabilities that operate on low supply voltages with high efficiency. While certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.