Abstract:
A method for measuring frequency includes the steps of obtaining the cycle number of the clock rate of a signal under test based on a reference signal and a clock mask synchronous with the signal under test; obtaining a frequency of the signal under test based on the cycle number; correcting the frequency of the signal under test based on a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the frequency of the signal under test by increasing the quantity of the phase shift signals. The method enhances the accuracy of the obtained frequency of the signal under test, speeds up frequency measurement, and reduces the required circuit areas. A system for measuring frequency is further introduced for use with the method.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 100125217 filed in Taiwan, R.O.C. on Jul. 15, 2011, the entire contents of which are hereby incorporated by reference. 
       FIELD OF TECHNOLOGY 
       [0002]    The present invention relates to methods and systems for measuring frequency, and more particularly, to a method and system for measuring frequency quickly and precisely. 
       BACKGROUND 
       [0003]    The frequency of a clock signal is usually measured with a frequency counter. In general, a gate duration of the frequency counter is set, and the number of the cycles of the clock signal within the gate duration is counted. Eventually, the frequency of the clock signal is calculated, using the quotient of the count value and the gate duration. 
         [0004]    However, the cycle number of a clock signal within a gate duration is seldom an integer, and thus the method is likely to cause an error at the beginning and the end of the gate duration—underestimating or overestimating by a half cycle, for example. In view of this, to measure frequency, it is usually necessary to maximize the gate duration in order to handle as many cycles as possible and thereby reduce errors. However, the aforesaid solution is performed at the cost of a great increase in the testing time and decrease in resolution. 
       SUMMARY 
       [0005]    It is an objective of the present invention to enhance the speed and accuracy of frequency measurement. 
         [0006]    Another objective of the present invention is to provide an automatic program-controlled method and system for measuring frequency. 
         [0007]    In order to achieve the above and other objectives, the present invention provides a method for measuring frequency. The method is applicable to measuring a signal under test. The method comprises the steps of: providing a reference signal; generating a plurality of phase shift signals of a same frequency based on the reference signal, the phase shift signals being spaced apart from each other by a fixed phase; setting a clock mask, the clock mask starting from a first triggering state of the signal under test and ending at another first triggering state of the signal under test; counting a number Nd 1  of second triggering states occurring to the phase shift signals during a period from commencement of the clock mask to occurrence of a first triggering state to the reference signal; counting a number Nb of cycles of the reference signal within a range of the clock mask; counting a number Ni of cycles of the signal under test within a range of the clock mask; counting a number Nd 2  of second triggering states occurring to the phase shift signals during a period from termination of the clock mask to occurrence of a first triggering state to the reference signal; and obtaining the frequency of the signal under test Fi by the equation: Fi={Ni/[Nb+(Nd/M)]}×Fb, wherein a frequency of the reference signal is denoted by Fb and a number of the phase shift signals by M, with Nd=(Nd 1 −Nd 2 ) and M≧2. 
         [0008]    In order to achieve the above and other objectives, the present invention provides a system for measuring frequency. The system is applicable to measuring a signal under test. The system comprises: a signal input end for receiving the signal under test; a count generator connected to the signal input end for receiving the signal under test, adapted for generating a reference signal of a frequency Fb, adapted for generating M phase shift signals which are based on the reference signal, have a same frequency, and are spaced apart from each other by a fixed phase, adapted for generating a clock mask starting from a first triggering state of the signal under test and ending at another first triggering state of the signal under test, adapted for counting a number Nd 1  of second triggering states occurring to the phase shift signals during a period from commencement of the clock mask to occurrence of a first triggering state to the reference signal, adapted for counting a number Nb of instances of occurrence of the first triggering state to the reference signal within a range of the clock mask, adapted for counting a number Ni of instances of occurrence of the first triggering state to the signal under test within a range of the clock mask, adapted for counting a number Nd 2  of second triggering states occurring to the phase shift signals during a period from termination of the clock mask to occurrence of the first triggering state to the reference signal, and adapted for outputting the count values Fb, M, Nb, Ni, Nd 1 , Nd 2 ; and a computing device connected to the count generator for receiving the count values and performing computation to obtain the frequency of the signal under test Fi by the equation: Fi={Ni/[Nb+(Nd/M)]}×Fb, wherein Nd=(Nd 1 −Nd 2 ), where M≧2. 
         [0009]    In an embodiment, the count generator comprises a fundamental frequency generating unit, a frequency multiplying unit, and a programmable gate array. The fundamental frequency generating unit generates a fundamental frequency signal. The frequency multiplying unit is connected to the fundamental frequency generating unit for turning the fundamental frequency signal into the reference signal by frequency multiplication. The programmable gate array is connected to the signal input end for receiving the signal under test and to the frequency multiplying unit for receiving the reference signal, generates the count values M, Nb, Ni, Nd 1 , and Nd 2 , and outputs the count values Fb, M, Nb, Ni, Nd 1 , and Nd 2 . 
         [0010]    In an embodiment, the computing device is one of a control unit and a computer. 
         [0011]    In an embodiment, the first triggering state is one of an upper triggering state and a lower triggering state. 
         [0012]    In an embodiment, the second triggering state is one of an upper triggering state and a lower triggering state. 
         [0013]    In an embodiment, the clock mask comprises the number Ni of cycles of the signal under test, where Ni≧2. 
         [0014]    In an embodiment, four or eight said phase shift signals are generated. 
         [0015]    In an embodiment, the reference signal frequency Fb is directly replaced by a default value. 
         [0016]    Accordingly, the present invention provides a method and system for measuring frequency to eliminate measurement errors by quick and precise multiphase processing, multiply the accuracy of measurement in accordance with the quantity of generated phase shift signals, effectuate fully automatic program-based control by means of synchronous triggering, and reduce the area occupied by a circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    Objectives, features, and advantages of the present invention are hereunder illustrated with specific embodiments in conjunction with the accompanying drawings, in which: 
           [0018]      FIG. 1  is a timing diagram of a method for measuring frequency according to an embodiment of the present invention; 
           [0019]      FIG. 2  is a flow chart of the method for measuring frequency according to an embodiment of the present invention; and 
           [0020]      FIG. 3  is a function block diagram of a system for measuring frequency according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    The steps of a method for measuring frequency of the present invention are described in specific embodiments thereof and are, unless otherwise specified, interchangeable in terms of sequence. Furthermore, the concept of “connection” used in the description of specific embodiments of a system for measuring frequency according to the present invention is not limited to direction connection; instead, connection can also be effectuated by an intervening element. Also, a “first triggering state” and a “second triggering state” used in the description of the method and system for measuring frequency of the present invention comprise one of an upper-edge triggering state and a lower-edge triggering state. The first triggering state and the second triggering state are not mutually exclusive; hence, both the first triggering state and the second triggering state may be upper-edge triggering states or lower-edge triggering states. 
         [0022]    Referring to  FIG. 1 , there is shown a timing diagram of a method for measuring frequency according to an embodiment of the present invention. As shown in  FIG. 1 , this embodiment is exemplified by eight phase shift signals. Persons skilled in the art should be able to understand that, given at least two phase shift signals, the method and system for measuring frequency of the present invention is effective in eliminating measurement errors and thereby enhancing accuracy. 
         [0023]    A method for measuring frequency according to an embodiment of the present invention comprises two frequency measurement methods comprising the steps of: 
         [0024]    As shown in  FIG. 1 , in addition to an incoming signal under test Fi, measurement is preceded by the step of providing a reference signal Fb and the step of generating multilevel phase shift signals Fb-p 1 ˜Fb-p 8  of the same frequency based on the reference signal Fb, wherein the phase shift signals Fb-p 1 ˜Fb-p 8  are spaced apart from each other by a fixed phase. 
         [0025]    The reference signal Fb functions as a fundamental frequency for obtaining the frequency of the signal under test. The phase shift signals are generated from the reference signal Fb. Normally, the phase shift of a signal is effectuated by a digital clock manager (DCM) of a programmable gate array (FPGA). In this embodiment, eight phase shift signals Fb-p 1 ˜Fb-p 8  are processed by two digital clock managers, and the reference signal Fb is decomposed by a digital clock manager to form four phase shift signals. However, persons skilled in the art should be able to understand that a user can still selectively shut down four of the phase shift decomposition processes even with just one digital clock manager. Hence, with only one digital clock manager, it is still possible to decompose the reference signal Fb into two or three phase shift signals. Hence, users can select the quantity of required phase shift signals as needed and as appropriate for operation of a digital clock manager. Regarding the spacing of phase shift signals, a digital clock manager divides 360° into equal phase portions and distributes the equal phase portions among the phase shift signals. For example, the phase equals 360°/(M−1), where M denotes the number of phase shift signals. 
         [0026]    Afterward, a clock mask mk is set. The clock mask mk thus set starts from a first triggering state of the signal under test Fi and ends at another first triggering state of the signal under test Fi. In this embodiment, the first triggering state is exemplified by an upper triggering state. Hence, the clock mask mk can be synchronized with the signal under test Fi and thus is triggered synchronously in an upper triggering state of the signal under test Fi. The clock mask mk maintains a high level unless and until a preset number of the signal under tests Fi are performed. Hence, the clock mask mk ends at another first triggering state of the signal under test Fi. In the embodiment illustrated with  FIG. 1 , the clock mask mk ends at the seventh first triggering state of the signal under test Fi, and thus six cycles of the signal under test Fi have passed, that is, the number Ni of cycles of the signal under test Fi equals 6, or Ni=(the number of instances in which the signal under test Fi enters the first triggering state)−1. The number Ni of cycles of the signal under test Fi must be at least 1 and is preferably at least 2. 
         [0027]    Upon initialization of the clock mask mk, measurement kicks off. Referring to  FIG. 1 , the reference signal Fb does not synchronize with the signal under test Fi; hence, the time actually taken to effect the number Nb of cycles of the reference signal Fb measured does not fall within the range of the clock mask mk, thereby resulting in front-end errors and back-end errors. It is because the number Nb of cycles of the reference signal Fb measured is usually counted according to the number of upper triggering states or lower triggering states. 
         [0028]    Hence, in an embodiment of the present invention, the front-end and back-end errors are eliminated by means of the phase shift signals. 
         [0029]    Regarding the front-end errors, the number Nd 1  of second triggering states (upper or lower triggering states) that occur to the phase shift signals Fb-p 1 ˜Fb-p 8  during the period from the point in time of commencement of the clock mask mk to the point in time when a first triggering state occurs to the reference signal Fb is counted. 
         [0030]    Regarding the back-end errors, the number Nd 2  of second triggering states (upper or lower triggering states) that occur to the phase shift signals Fb-p 1 ˜Fb-p 8  during the period from the point in time of termination of the clock mask mk to the point in time when a first triggering state occurs to the reference signal Fb is counted. 
         [0031]    Counting the second triggering states that occur to the phase shift signals Fb-p 1 ˜Fb-p 8  means that elimination of back-end errors requires selecting the upper triggering state as the second triggering state when elimination of front-end errors requires selecting the upper triggering state as the second triggering state, or means that elimination of back-end errors requires selecting the lower triggering state as the second triggering state when elimination of front-end errors requires selecting the lower triggering state as the second triggering state. As shown in  FIG. 1 , the upper triggering state is selected to be the second triggering state, thereby setting Nd 1  to 3 and Nd 2  to 5. 
         [0032]    Subsequent calculation involves subtracting Nd 2  from Nd 1  to obtain the cycle number that falls within the range of the clock mask mk and needs to be calibrated with a view to eliminating the front-end errors and the back-end errors. 
         [0033]    After the aforesaid parameters have been figured out, the frequency of the signal under test Fi is calculated by equation (1) below: 
         [0000]        Fi={Ni/[Nb+ ( Nd/M )]}× Fb    (1)
 
         [0000]    wherein a calibrated value is denoted by Nd and the number of the phase shift signals by M, with Nd=(Nd 1 −Nd 2 ) and M≧2. In other words, at least two said phase shift signals are generated. 
         [0034]    The method according to an embodiment of the present invention enhances accuracy. The fundamental frequency of the signal under test Fi is determined by equation (2) below: 
         [0000]      ( Ni/Fi )=( Nb/Fb )   (2)
 
         [0000]    wherein equation (2) may also be rewritten as equation (3) below: 
         [0000]        Fi= ( Ni/Nb )× Fb    (3)
 
         [0035]    Equation (3) can be satisfied, provided that the frequency of the reference signal Fb is larger than the frequency of the signal under test Fi. 
         [0036]    Nonetheless, as revealed above, it is impossible for equation (3) to evaluate the frequency of the signal under test Fi accurately without calibrating the front-end and back-end errors. Accurate calculation necessitates restoration of the front-end errors and removal of the back-end errors in order to conform with the range of the clock mask mk completely. Hence, given the result of the calculation of the calibrated value Nd, it is feasible to evaluate the count value to be finally restored or removed. Furthermore, as indicated by equation (1), accuracy of measurement increases with the quantity of the generated phase shift signals by multiplication. Hence, compared with a convention method which is not based on calibration of front-end errors and back-end errors, the method in an embodiment of the present invention increases accuracy by eight times. 
         [0037]    Referring to  FIG. 1  and  FIG. 2 , there is shown in  FIG. 2  a flow chart of the method for measuring frequency according to an embodiment of the present invention. As shown in  FIG. 2 , step S 101  involves providing the signal under test Fi, the reference signal Fb, and a plurality of phase shift signals Fb-p 1 ˜Fb-p 8 ; step S 102  involves starting the clock mask mk synchronized with the signal under test Fi; step S 103  involves obtaining the number Nd 1  of front-end errors; step S 104  involves shutting down the clock mask mk and obtaining the cycle numbers Ni and Nb of the signal under test Fi and the reference signal Fb, respectively; step S 105  involves obtaining the number Nd 2  of back-end errors; and finally step S 106  involves performing calculation by equation (1). 
         [0038]    Referring to  FIG. 3 , there is shown a function block diagram of a system for measuring frequency according to an embodiment of the present invention. As shown in  FIG. 1 , a frequency measuring system  100  comprises a signal input end  110 , a count generator  120 , and a computing device  130 . 
         [0039]    The signal input end  110  receives the signal under test Fi. 
         [0040]    The count generator  120  is connected to the signal input end  110  for receiving the signal under test Fi. The count generator  120  generates the reference signal Fb, M phase shift signals spaced apart from each other by a fixed phase, the clock mask mk, the number Nd 1  of second triggering states that occur to the phase shift signals within the range of front-end errors, the number Nb of first triggering states that occur to the reference signal Fb within the clock mask mk, the number Ni of first triggering states that occur to the signal under test Fi within the clock mask mk, the number Nd 2  of second triggering states that occur to the phase shift signals within the range of back-end errors, and the count values Fb, M, Nb, Ni, Nd 1 , and Nd 2  to be output. 
         [0041]    In an embodiment, the count generator  120  comprises a fundamental frequency generating unit  121 , a frequency multiplying unit  123 , and a programmable gate array  125 . The fundamental frequency generating unit  121  generates a fundamental frequency signal. Normally, a low fundamental frequency is generated by a crystal oscillator to cut costs, and then the fundamental frequency is boosted by the frequency multiplying unit  123  connected to the fundamental frequency generating unit  121  for functioning as the reference signal Fb. Normally, a fundamental frequency is increased to exceed the range of possible frequencies for the signal under test Fi. Hence, the frequency of the reference signal Fb varies from one signal under test to another. The higher the frequency of the reference signal Fb is, the wider is its application. A programmable gate array  125  comprises a digital clock manager for functioning as a phase shift generating circuit, a differential circuit for performing upper or lower differentiation (upper-edge triggering or lower-edge triggering) to count Nd 1  and Nd 2 , and a mask circuit for generating the clock mask mk and counting the signal under test Fi and the reference signal Fb. Accordingly, the programmable gate array  125  generates the count values M, Nb, Ni, Nd 1 , and Nd 2  and outputs the count values Fb, M, Nb, Ni, Nd 1 , and Nd 2 . 
         [0042]    The programmable gate array is a conventional element. The system for measuring frequency according to an embodiment of the present invention achieve the objectives of the present invention by means of logical elements of the system for measuring frequency. The method for measuring frequency according to an embodiment of the present invention reduces the required number of the logical elements, dispenses with a large-sized programmable gate array chip, and thus reduces the circuit-occupied area and downsizes the product. For example, if the computing function of a computing device is also incorporated into the programmable gate array, the required number of the logical elements will be greatly increased, thereby increasing the circuit-occupied area. Due to its structural design, the programmable gate array is of a low computation capacity and operates at a low speed and thus is not suitable for use in computation. Although a special high-priced programmable gate array can perform high-speed computation, it incurs an excessively high cost. 
         [0043]    The computing device  130  is connected to the count generator  120  for receiving the count values and performing computation by equation (1) to obtain the frequency of the signal under test Fi. The computing device  130  is a control unit (MCU) or a computer. If the computing device  130  is a control unit, then the control unit is usually disposed on the same circuit board as the count generator  120  is, such that the frequency measuring system  100  in its entirety is integrated onto a module; however, the computing device  130  can also be an external computer device for processing a computation procedure in whole with data provided by a measuring module. 
         [0044]    To reduce errors further, it is feasible to perform a high-precision measurement process on the generated reference signal Fb beforehand. To preclude any error which might otherwise be produced as a result of a discrepancy between a frequency actually generated by a fundamental frequency generating unit and a frequency multiplier and a given frequency level, it is feasible to measure the reference signal Fb in advance by means of a high-precision frequency counter having a higher resolution than the frequency of the reference signal Fb, and then use the measured reference signal Fb as a default value to be directly stored in the computing device  130 . In doing so, in every instance of measurement, the default value always applies to the frequency of the reference signal Fb, thereby dispensing with the need to use a parameter set forth in the specifications of a fundamental frequency generating unit and a frequency multiplier. 
         [0045]    In conclusion, a method and system for measuring frequency of the present invention eliminate measurement errors by quick and precise multiphase processing and multiply the accuracy of measurement in accordance with the quantity of generated phase shift signals. An embodiment of the present invention achieves eightfold reduction (corresponding to eight phase shift signals) in errors, effectuates fully automatic program-based control by means of synchronous triggering, and reduces the area occupied by a circuit. 
         [0046]    The present invention is disclosed above by preferred embodiments. However, persons skilled in the art should understand that the preferred embodiments are illustrative of the present invention only, but should not be interpreted as restrictive of the scope of the present invention. Hence, all equivalent modifications and replacements made to the aforesaid embodiments should fall within the scope of the present invention. Accordingly, the legal protection for the present invention should be defined by the appended claims.