Abstract:
A power supply for supplying a load capacitor and comprising a parallel resonant circuit having an inductor and a capacitor, a switching network operating at a frequency at or above the resonant frequency and applying alternating current to the resonant circuit and the primary side of a power transformer, a rectifier for rectifying the induced currents on the secondary winding of the transformer, and applying the rectified output to the load capacitor, and a controller for controlling the output of the power supply based on a comparison of the output voltage V out  with a desired (setpoint) voltage V prog . The resonant capacitance may consist of the power transformer winding self-capacitance. The resonant inductance may consist of the primary winding of the power transformer. The controller provides switching signals to operate the power supply at the resonant frequency of the resonant tank circuit during a &#34;rapid rate charging mode&#34; at which a maximum output current I out  is applied to the load. When the controller senses that the output voltage V out  is closely approaching the desired voltage V prog , it gradually increases the switching frequency from the resonant frequency toward a maximum frequency during a &#34;decreasing rate charging mode&#34;. When the controller senses that V out  equals V prog , it maintains the maximum switching frequency to provide a minimum output current I out .

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention concerns a capacitor charging power supply. More particularly, the present invention concerns a method for automatically controlling the output of a high voltage, parallel resonant mode power supply operating at a variable, non-audible frequency at or above its resonant frequency, including &#34;charge&#34; modes of operation and a &#34;hold&#34; mode of operation, and having an exceptionally smooth modal (i.e., charge mode to hold mode) transition, very low output ripple, and inherently stable output control characteristics in all operating modes. The present invention also concerns a device for implementing this method. 
     2. Description of the Prior Art 
     Known resonant power supplies have been used in various topologies for supplying power to various types of loads. A parallel resonant power converter typically has a transistor switching network connected to a resonant tank circuit having an inductor and a capacitor. The transistor switching network chops a DC input voltage thereby providing an alternating (i.e., a quasi-square wave) voltage across the resonant tank circuit and exciting a resonant current. A transformer is typically used to transfer power from the resonant tank circuit to a full bridge rectifier circuit. The rectified voltage is then applied to the load. 
     With such known resonant power supplies, the output voltage can be regulated by varying the switching frequency of the switching network. The output voltage is maximum when the switching frequency of the switching network is at the resonant frequency of the resonant tank circuit (which is ##EQU1## where L RT  is the inductance of the resonant tank circuit and C RT  is the capacitance of the resonant tank circuit) and decreases as the switching frequency of the switching network deviates from the resonant frequency point. 
     Capacitive loads are often used in high voltage applications such as laser pumps, spark gaps, igniter sources and other high voltage pulsed load applications. Capacitor charging power supplies must be &#34;short circuit proof&#34; because an uncharged capacitive load presented to the power supply will initially appear as a short circuit, i.e., it will draw a large current. Thus, in the absence of any control response, the output current must remain at some nominal value when the output of the supply is, or appears to be, shorted. 
     The capacitor charging power supply must also be able to deliver a large amount of energy to the capacitive load to rapidly charge it. Once the capacitive load is adequately charged, the supply must also be able to maintain the charge of the capacitor with a minimum amount of output voltage ripple. Otherwise, excessive output voltage ripple may cause untimely and inappropriate pulsing of the capacitive load due to fluctuations in the voltage across it. For example, if the voltage varies from pulse to pulse, the energy delivered to the load capacitor will vary. This variation is undesirable because it may affect the consistency of a process controlled by the load capacitor. For example, a capacitor may be charged, and then discharged into a laser having an output used to expose semiconductor wafers to create an image of the integrated circuit pattern. Lasers are highly non-linear devices and a small variation in their input voltage may cause a large variation in their output power. Thus, output voltage ripple by the power supply may cause variations in the output power of the laser which in turn may cause undesirable exposure changes. The variation of the output caused by output ripple may also disadvantageously vary the time at which an energy pulse is delivered by the load capacitor. For example, some pulse systems include saturating magnetic components which operate at a fixed V*T (voltage*time) product. Thus, variations of an input voltage of these components may cause time variations in their outputs. This variation, known as &#34;time jitter,&#34; may cause time synchronization problems for example. Lastly, the power supply must be able to smoothly transition from rapidly charging the capacitor to maintaining the charge of the capacitor. 
     Known capacitor charging power supplies have used two modes of operation, though they suffer from some or all of the problems addressed by the present invention. For example, the power supply discussed in U.S. Pat. No. 5,121,314 (hereinafter &#34;the &#39;314 patent&#34;) uses two operating modes in a fixed-frequency, series-resonant, high voltage capacitor charging power supply. The power supply of the &#39;314 patent operates in a first &#34;full charge mode&#34; at a 100% duty cycle with an open control loop to apply maximum power to the capacitive load until the desired voltage is reached, whereupon the duty cycle is reduced abruptly to 13% or less. This abrupt change in the duty cycle precludes a smooth modal transition. Moreover, the abrupt change in the output voltage (approximating a discontinuity) caused by the abrupt change in duty cycle creates a high frequency component which requires a more accurate feedback control. Finally, the device discussed in the &#39;314 patent operates at a fixed switching frequency. Thus, the resolution of the output control is limited by the resolution at which the duty cycle can be changed. 
     In view of the aforementioned problems with known power supplies for supplying capacitive loads, a short circuit proof power supply is needed. The power supply should also be capable of charging a capacitive load at a rapid rate (e.g., since a capacitive load may be discharged at a rate of several KHz, the power supply of the present invention should be able to recharge the capacitive load in a time on the order of a msec, and preferably on the order of tens or hundreds of μsec) to a desired voltage. At the same time, the power supply should avoid undesirable, and potentially load-damaging, overvoltage or overshoot conditions. The power supply should be able to precisely maintain the capacitive load at the desired voltage level with extremely low output ripple (preferably 0.05% or less). The power supply should operate at frequencies above the audible range. The power supply should also responsively adjust to AC or DC input voltage fluctuations such that these fluctuations are not transferred to the load. 
     An object of the present invention is to provide an apparatus, having the above-mentioned desirable properties, for converting a first input DC voltage (300 V DC, for example) to a second output DC voltage (40 KV DC, for example) for charging a load capacitor. 
     SUMMARY OF THE INVENTION 
     The present invention achieves the aforementioned objects by providing a power supply circuit which includes a variable frequency switching network (such as a half-bridge inverter, for example) which is supplied with a DC input voltage. The switching network alternately applies positive and negative voltages (in a quasi-square wave) to a parallel resonant tank circuit and the primary winding of a power transformer. The resonant tank circuit comprises an associated capacitance and an associated inductance. The inductance may include the leakage inductance of the power transformer and the capacitance may include the winding self-capacitance of the power transformer. 
     In a preferred embodiment of the present invention, the switching action causes sine wave quantums of current to flow through the primary winding of the power transformer in alternating directions. The switching advantageously occurs at a non-audible frequency, at or above the resonant frequency of the resonant tank circuit. The exact frequency of operation is determined by a control circuit. The secondary winding of the power transformer is coupled, via a rectifier, to the load capacitor. 
     Using a control circuit, which varies the switching frequency of the switching network based on the output voltage, the load capacitor is charged to the desired voltage level during a &#34;charge&#34; modes (including a &#34;rapid rate charge mode&#34; and a &#34;decreasing rate charge mode&#34;) and this charge voltage level is maintained by the control circuit during a &#34;hold mode&#34;. That is, as the switching frequency of the switching network reaches its maximum level (e.g., 150 KHz), corresponding to the minimum resonant output voltage level, the controller enters a &#34;hold mode&#34; of operation. In the &#34;hold mode&#34;, high frequency, low energy switching bursts are caused to occur in the switching network. As a result, the capacitor charge voltage is maintained with extremely low ripple. The &#34;decreasing rate charge mode&#34; occurs at a time period between the &#34;rapid rate charge mode&#34; and the &#34;hold mode&#34;. During this time period, the switching frequency is increased (continuously and preferably linearly) from f resonant  to f max  (See time t 1  to t 2  in FIG. 3) during which the charging current applied to the output load may be continuously and substantially linearly reduced. 
     A feedforward means for sensing variations in the input DC voltage source may be used to provide these variations to the control circuit. The control circuit can then adjust the operation of the switching network, if necessary, based on the sensed variations in the input DC voltage. 
     In a preferred embodiment of the present invention, the switching network and resonant components together form a half-bridge parallel resonant inverter. The parallel resonant inverter converts the DC input power to an alternating current having an adjustable frequency at or above the resonant frequency. The output of the parallel resonant inverter is rectified and applied to the load capacitor. Rapid charging of the capacitor is accomplished by operating the inverter at a frequency at or near its resonant point (e.g., ≅50 KHz). 
     The present invention solves several problems associated with charging capacitive loads and maintaining that charge; namely the output power applied to the load during the &#34;rapid rate charge mode&#34; is maximized while controlling a smooth linear transition (during the &#34;decreasing rate charge mode&#34;) to the &#34;hold mode&#34;. In addition, the &#34;hold mode&#34; of operation advantageously maintains a constant output voltage while minimizing the output voltage ripple. 
     In instances where the output voltage must be brought to zero, but the switching frequency cannot be brought high enough to effect such an output, the switching network may be shut-off (i.e., disabled) periodically by the control circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a parallel resonant capacitor charging power supply of the present invention. 
     FIG. 2 is a family of characteristic gain curves of a parallel resonant converter at various load impedances. 
     FIG. 3 is timing diagram illustrating the output voltage, output current and switching frequency for a capacitor-loaded, parallel resonant capacitor charging power supply of the present invention. 
     FIG. 4 is a schematic of an alternative controller which may be used with the parallel resonant capacitor charging power supply of the present invention. 
    
    
     DETAILED DESCRIPTION 
     After reading the following detailed description, those skilled in the art will readily appreciate that a capacitor charging power supply of the present invention can be used to supply power to a wide variety of loads, including purely capacitive loads. Furthermore, the parallel resonant mode power supply of the present invention may be used to supply power to other types of passive or active loads. Since, however, the present invention is particularly advantageous for supplying capacitive loads, it will be illustratively discussed in that context. 
     FIG. 1 is a schematic diagram which illustrates the preferred embodiment of the power supply of the present invention. The power supply comprises a parallel resonant converter formed by a half-bridge zero voltage switching (ZVS) network 200 and a resonant tank circuit 300. The resonant tank circuit 300 has a resonant frequency of approximately 50 KHz and the switching network 200 may operate from approximately 50 KHz to approximately 150 KHz. 
     Although a desire to operate the power supply above audible frequencies limits the minimum switching frequency, the minimum switching frequency is further limited by a desire to have a relatively small power supply. Specifically, if the switching frequency is too low, the output transformer 330 would have to be unacceptably large. On the other hand, the maximum switching frequency is limited by the need to minimize switching losses in the switching network 200 and by the need to space the transformer 330 to adequately insulate the output from the rest of the power supply. This is particularly relevant in high voltage power supplies. For example, the power supply of the present invention may have an input voltage of about 300 V DC and an output voltage of about 40,000 V DC. The output voltage must be adequately insulated from the rest of the power supply to prevent arcing, stray capacitances, etc. 
     The output of the resonant inverter 300 is rectified by a full bridge rectifier 400 and presented to the load capacitor C load . A controller 500 compares the actual output voltage (scaled by a factor 1/R) V out  /R with a desired (setpoint) output voltage V prog  /R (also scaled by a factor 1/R) using an error (differential) amplifier 510. The resulting difference signal (the &#34;error signal&#34;) is provided to a timing circuit 530 (which may comprise a voltage controlled oscillator) which adjusts the switching network 200 drive signals φ 1  and φ 2  based on the error signal such that the output voltage V out  is made to approach the programmed (setpoint) voltage V prog . The output voltage V out  and the desired (setpoint) voltage V prog  are scaled by a factor 1/R because otherwise, they would be too large to be easily handled by typical control circuit elements. 
     The drive signals φ 1  and φ 2  of the switching network 200 should be 180° out of phase and should have a duty cycle of less than 50% to prevent the transistors 210 and 220 from conducting (i.e., being closed) simultaneously. 
     An optional device for minimizing the effect of input fluctuations is also shown. Specifically, a summing amplifier 520 adds the first error signal, output from the error amplifier 510, with a feed forward voltage V FF  to provide a compensated error signal to the timing circuit 530. The feed forward voltage V FF  is formed by scaling and offsetting the DC input voltage V in  with the scaling and offsetting device 700. For example, the DC input voltage V in  may be scaled by a factor of 0.1 and offset by subtracting 25 V to provide the feed forward voltage V FF . Thus, in this example, the scaling and offsetting device 700 produces a feed forward voltage V FF  of 0 V from a DC input voltage V in  of 250 V, and produces a feed forward voltage V FF  of 10 V from a DC input voltage of 350 V. Accordingly, in this case, the timing circuit 530 adjusts the switching network drive signals φ 1  and φ 2  based on the compensated error signal provided by the summing amplifier 520. 
     FIG. 4 illustrates an alternative control circuit 600 which may be used instead of the control circuit 500. The output voltage (scaled by a scale factor 1/R) V out  /R and the desired output voltage (also scaled by a factor 1/R) V prog  /R are provided to an error (differential) amplifier 610. If a feedforward detection system is used to minimize the effects of input voltage fluctuations, the output of the error (differential) amplifier 610 and a feed forward voltage V FF  (produced by scaling and offsetting the input DC voltage V IN  as discussed above) are provided to a summing amplifier 620. The output of the summing amplifier 620 is then provided, as a first input, to a voltage controlled oscillator 630. Otherwise, if a feedforward detection system is not used, the output of the error (differential) amplifier 610 is provided, as a first input, to the voltage controlled oscillator 630. A minimum switching frequency value f min  of the switching network 200 (e.g., 50 KHz) is also provided as a second input to the voltage controlled oscillator 630. 
     The output f out  of the voltage controlled oscillator 630 is applied, as a first input, to a comparator 640. A maximum setpoint frequency f max , representing the maximum switching frequency of the switching network 200 (e.g., 150 KHz), is applied, as a second input, to the comparator 640. The output of the comparator 640 is inverted by an inverter 650. Thus, when the output f out  of the voltage controlled oscillator 630 is greater than the maximum switching frequency of the switching network 200, a low signal is output by the inverter 650. 
     The output of the voltage controlled oscillator f out  is also applied to a first AND gate 660 and, via an inverter 680, to a second AND gate 670. The first and second AND gates 660 and 670 are also supplied with the output of the inverter 650. Thus, the switching signal φ 1  is provided by the first AND gate 660 while the switching signal φ 2  is provided by the second AND gate 670. Further, when the output f out  of the voltage controlled oscillator 630 is greater than the maximum switching frequency of the switching network 200, the switching signals φ 1  and φ 2  are disabled by the low signals applied to AND gates 660 and 670, respectively, by the inverter 650. 
     The parallel resonant power supply of FIG. 1 is now explained in detail. A first DC input voltage V in  (300 V DC, for example) is applied across a capacitive voltage divider circuit 100 formed by a first capacitor 110 and a second capacitor 120 connected in series. A junction 130 is defined at a node between the first and second capacitors 110 and 120, respectively. One half of the input voltage V in  is dropped across each of capacitors 110 and 120 such that the junction 130 is at a voltage V in  /2. A half-bridge inverter of the switching network 200 is arranged in parallel with the capacitive divider circuit 100. The half-bridge inverter is formed by first and second Metal Oxide Field Effect Transistors (MOSFETs) 210 and 220, respectively. A first intrinsic anti-parallel diode 211 and a first snubbing capacitor 212 are each connected across the first transistor 210 (i.e., from its source to its drain). Similarly, a second intrinsic anti-parallel diode 221 and a second snubbing capacitor 222 are each connected across the second transistor 220 (i.e., from its source to its drain). 
     The first transistor 210 is controlled by switching waveform φ 1  applied at its gate and output by the timing circuit 530 (or AND gate 660) and the second transistor 220 is controlled by switching waveform φ 2  applied at its gate and output by the timing circuit 530 (or AND gate 670). A junction 230 is defined at a node between the first and second transistors 210 and 220, respectively. The switching network operates in a well known zero voltage switching (ZVS), soft-switching manner to minimize switching losses. 
     A resonant inductor 310 of the resonant tank circuit 300 is coupled between the junction 230 of the switching network 200 and a first end of the primary winding 331 of a transformer 330 of the resonant tank circuit 300. A second end of the primary winding 331 is coupled with the junction 130 of the capacitive divider 100. A resonant capacitor 320 of the resonant tank circuit 300 is connected in parallel with the secondary winding 332 of the transformer 330. The inductance of the transformer 330 constitutes part of the total resonant inductance of the resonant tank circuit 300. The interwinding capacitance of transformer 330 constitutes part of the total resonant capacitance of the resonant tank circuit 300. 
     FIG. 2 is the family of characteristic gain curves of the parallel resonant converter of the present invention. The gain (V out  /V in ) is plotted as a function of the switching frequency of the switching network 200. As the curves show, the gain is maximum at the resonant frequency f resonant  (about 50 KHz) of the resonant tank circuit 300 and declines as the switching frequency of the switching network 200 deviates from the resonant frequency f resonant . Hence, with a fixed input voltage, the output voltage will decrease as the switching frequency f switch  of the switching network 200 increases above the resonant frequency f resonant . The output voltage will also decrease as the switching frequency f switch  of the switching network 200 decreases below the resonant frequency f resonant . However, this characteristic is not exploited because the switching network 200 should operate above audible frequencies and at frequencies permitting the use of a smaller transformer 330 as discussed above. 
     As the output voltage decreases, the amount of energy available to charge the capacitor decreases until the maximum switching frequency f max  (about 150 KHz) of the switching network 200 is reached. Accordingly, as the gain decreases, so does the power applied to the capacitive load C load . A comparison of the curves LR 1  (high impedance load) through LR 4  (low impedance load) in FIG. 2 also illustrates that the lower the impedance of the output load, the higher the peak gain. 
     In a capacitor charging power supply where the initial required output charging current will be maximum, which will be reduced to a minimum to reduce output ripple, the characteristic curve of parallel resonant converters is advantageously utilized. Specifically, the frequency during the &#34;rapid rate charging mode&#34; is at or about the resonant frequency f resonant , the frequency range for the &#34;decreasing rate charge mode&#34; operation of the power supply is between the resonant frequency (f resonant ) and the maximum frequency (f max ), and the frequency for the &#34;hold mode&#34; operation of the power supply is at about the maximum switching frequency f max . If the output desired is such that the necessary switching frequency would exceed the maximum switching frequency f max  (e.g., 150 KHz) of the switching network 200, then the supply will periodically shut-off (i.e., disable) the switches of the switching network 200. This &#34;switch disable&#34; can be achieved, for example, with the comparitor 640 and inverter 650 of FIG. 4, as discussed above. 
     The operation and modes of the parallel resonant power supply are described with reference to FIG. 3 which illustrates the timing relationship between the output voltage V out , the output current I out , and the switching frequency f switch  of the switching network 200 in the present invention. The purpose of the power supply is to cause the output voltage (V out ) across the load to reach a desired level (V prog ) in a minimum amount of time while avoiding an overshoot of the desired level. Thus, at time t(0), the power supply begins to charge the completely discharged load capacitor. This is called the &#34;rapid rate charge mode&#34;. The initial condition of the load capacitor appears to be a short circuit because it draws current. Accordingly, the controller 500 causes the power supply to operate in the &#34;rapid rate charge mode&#34; at the resonant frequency f resonant  of the resonant tank circuit 300 which in this case coincides with the minimum switching frequency f switch  of the switching network 200. Operating the power supply at the resonant frequency f resonant , causes the output current I out  supplied to the load capacitor to be at a maximum I max  (see time period t 0  to t 1 ). At time t(1), V out  closely approaches V prog . The controller 500 can detect this by comparing V out  with a pre-determined threshold percentage (e.g., 95% of V prog . Consequently, the controller 500 adjusts the switching frequency f switch  (i.e., increases the switching frequency f switch  from the resonant frequency f resonant  of the resonant tank circuit 300) to reduce the output current I out  supplied to the load capacitor. This &#34;decreasing rate charge mode&#34; occurs during the time period between t(1) and t(2) while the power supply continues to operate in a charge mode. However, the switching frequency f switch  of the switching network 200 increases as the controller 500 determines that V out  is closely approaching V prog  as described above. Providing the &#34;decreasing rate charge mode&#34; ensures a smooth modal transition between the &#34;charge modes&#34; and the &#34;hold mode&#34;. At time t(2), when the controller 500 determines that V out  has reached V prog , the controller 500 increases the switching frequency f switch  to its maximum f max , causing the output current I out  to decrease to its minimum. At this point, the power supply is in the &#34;hold mode&#34; of operation. If the output voltage I out  at f max  is too large to prevent V out  from exceeding V prog , that is, if the output frequency four of the timer circuit 530 or the voltage controlled oscillator 630 is greater than the maximum switching frequency f max  of the switching network 200, the switches of the switching network 200 may be periodically disabled as discussed above with reference to FIG. 4. At time t 3 , the capacitor is discharged (or pulsed). The discharge is caused by an external factor, such as a controller for a laser, for example. The period from time t 3  to t 4  is a &#34;deadtime&#34; during which all switches are off. 
     As discussed above, some applications may require the load capacitor to be discharged on the order of a few KHz. Thus, the entire time from t 0  to t 4  may need to be on the order of msec or even tens of μsec.