Abstract:
A multi-mode multi-phase inductor-less DC/DC regulator is powered by a voltage source and produces an output to a load. It includes at least two modes of operation, and allows automatic switching among modes. Each mode includes a charging phase and a transfer phase. Mode selection and automatic mode switching determination are achieved by comparing derived voltages from the voltage source with internal voltage references. Mode selection and automatic mode switching actuation are achieved by selectively actuating some or all of no more than eight switching and regulation elements. Charging and transfer phases alternate and phase change is achieved by changing the configurations of some or all of the switching and regulation elements to charge and discharge no more than two external flying capacitors to provide a voltage at the output. This voltage is then fed back to a voltage regulation circuit to produce a regulated output voltage to the load.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     Not Applicable  
       FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Not Applicable  
       SEQUENCE LISTING OR COMPUTER PROGRAM  
       [0003]     Not Applicable  
       BACKGROUND OF THE INVENTION  
       [0004]     1. Field of the Invention  
         [0005]     The present invention relates to inductor-less DC/DC regulators commonly known in the art as charge pumps or switched capacitors, and more particularly, to multi-mode multi-phase inductor-less DC/DC regulators.  
         [0006]     2. Description of Related Art  
         [0007]     An inductor-less DC/DC regulator, commonly known as a charge pump or a switched capacitor in the art, utilizes internal switching elements to switch at least one external capacitor, known in the art as a flying capacitor, between energy storage phase and energy transfer phase to achieve a desired output voltage. If a regulated output voltage is not needed, a charge pump is typically used to generate an output voltage that is higher than the input voltage applied to the circuit. Such an inductor-less DC/DC regulator is typically referred to as an unregulated charge pump in the art. If a regulated output voltage is desired, a charge pump with internal voltage regulation circuitry can generate an output voltage that is lower than the input voltage applied to the circuit. Such an inductor-less DC/DC regulator is typically referred to as a regulated charge pump in the art.  
         [0008]     A charge pump utilizes an internal timing device, known in the art as a clock or an oscillator, to generate a signal with alternating low high and logic low levels at a fixed frequency, known in the art as a clock signal. A pair of logic high and logic low is known in the art as a clock cycle, and the time duration of such a clock cycle, known in the art as period, is the inverse of the clock frequency. For example, if the frequency of a clock is 1,000,000 Hz, then the period of the clock cycle is 1/1,000,000 s, or 10 −6  s, or 1 μs.  
         [0009]     The fundamental operation of an unregulated charge pump is that, during the logic high phase of a clock cycle, the internal switching elements are positioned as such to allow the flying capacitor or flying capacitors to be charged by an external DC voltage, such as a battery, for the entire duration of the logic high phase of the clock cycle. This phase is referred to as the charging phase. During the logic low phase of the clock cycle, the internal switching elements are positioned as such to allow the fly capacitor or flying capacitors to transfer the charges accumulated during the charging phase to an external load for the entire duration of the logic low phase. This phase is referred to as the transfer phase.  
         [0010]     The unregulated charge pumps are not desirable in electronic and electrical devices and instruments that require constant DC input voltage to operate. The regulated charge pumps are desirable for these electronic and electrical devices and instruments. The fundamental operation of a regulated charge pump that regulates output voltage is that, during the logic high phase of a clock cycle, the internal switching elements are positioned as such to allow the flying capacitor or flying capacitors to be charged by an external DC voltage, such as a battery. The duration of the actual charging is determined by the output voltage of charge pump. If a predetermined fraction of the output voltage exceeds a predetermined threshold voltage intrinsic to the charge pump prior to the completion of the logic high phase of the clock cycle, the charging can be interrupted by the means of opening a specific internal switching element on the charging current path, while the positions of all the other switching elements stay unchanged before the expiration of the logic high phase of the clock cycle. This phase is referred to as the charging phase. During the logic low phase of the clock cycle, the internal switching elements are positioned as such to allow the fly capacitor or flying capacitors to transfer the charges accumulated during the charging phase to an external load for the entire duration of the logic low phase. This phase is referred to as the transfer phase. Hence, a charge pump is frequently referred to as a multi-phase charge pump.  
         [0011]     Many electronic and electrical devices and instruments that utilize charge pumps these days are portable and battery powered. A typical battery, with an output voltage denoted as V BATT , has an operating voltage range. When the battery is fully charged, V BATT  is at the higher boundary of the operating voltage range. During its usage, V BATT  moves nonlinearly towards the lower boundary of the operating voltage range. Within the operating voltage range of the battery, a typical regulated charge pump outputs a constant post-regulation voltage, denoted as V OUT , to the load. When V BATT  reaches the lower boundary of the operation voltage range, the electronic or electrical device or instrument senses this condition and shuts down.  
         [0012]     Either an unregulated charge pump or a regulated charge pump produces a pre-regulation output voltage that is a multiple of the input voltage to the charge pump. Such a multiple is commonly referred to as a mode. A multiple, and therefore a mode, can be fractional. For example, a 1.5× mode regulated charge pump means the pre-regulation output voltage of the charge pump is 1.5 times of that of the input voltage of the charge pump. The commonly found modes or multiples in today&#39;s charge pumps are 1×, 1.5×, and 2×. Typically, the input voltage to the charge pump, denoted as V IN , is equivalent to V BATT .  
         [0013]     Because of the constant voltage level requirement for V OUT , and the decreasing voltage level nature of V BATT , it is not desirable for the regulated charge pump to have only one mode multiple from energy conversion efficiency standpoint. For example, a typical Li-Ion battery has a V BATT  operating voltage range between approximately 3.0V and approximately 4.2V. In a typical Li-Ion battery powered mobile electronics device, the desired V OUT  is approximately 3.3V. Assuming a 1.5× mode regulated charge pump, and a V BATT  at approximately 3.1V, at the beginning of the operation, the pre-regulation output voltage of the charge pump is approximately 1.5 times 3.1V, or 4.65V. With the desired V OUT  at approximately 3.3V, this gives a theoretical maximum charge pump efficiency of approximately 71%, or 3.3V/4.65V. Assuming later on the Li-Ion battery is charged to its full capacity, with V BATT  at approximately 4.2V, this time the pre-regulation output voltage of the charge pump is approximately 1.5 times 4.2V, or 6.3V. This gives a theoretical maximum charge pump efficiency of approximately 52%, or 3.3V/6.3V. This represents an approximately 19% loss of efficiency due to the specific V BATT  change.  
         [0014]     To prevent such efficiency loss, an automatic mode switching capability intrinsic to the charge pump, driven by V BATT  change, is desirable. Using the same example specified in the above paragraph, this time a 1×/1.5× automatic mode switching regulated charge pump is assumed. At the beginning of the operation, the pre-regulation output voltage of the charge pump is still approximately 1.5 times 3.1V, or 4.65V, which still gives a theoretical maximum charge pump efficiency of approximately 71%, or 3.3V/4.65V. Later on the Li-Ion battery is charged to its full capacity, with V BATT  at approximately 4.2V. This time, since V BATT  is higher than the 3.3V V OUT , the operation of the charge pump switches automatically from 1.5× mode to 1× mode, and the pre-regulation output voltage of the charge pump is approximately 1 times 4.2V, or 4.2V. This gives a theoretical maximum charge pump efficiency of approximately 79%, or 3.3V/4.2V. The automatic mode switching from 1.5× to 1×, triggered by the V BATT  change, increases the charge pump efficiency by approximately 8%. This simple example only illustrates automatic mode switching between 1× mode and 1.5× mode in a regulated charge pump. More sophisticated automatic mode switching scheme can switch among more than two modes, driven by V BATT  change and desired V OUT  level.  
         [0015]     3. Description of Prior Art  
         [0016]     U.S. Pat. No. 6,504,422B1, which issued on Jan. 7, 2003, and U.S. Pat. No. 6,794,926B2, which issued on Sep. 21, 2004, both to William E. Rader, et al., and assigned to Semtech Corporation, propose a charge pump power supply including two or more modes or operation. This prior art provides a switching circuit containing ten switching elements S 1 -S 10 , or switches, and is illustrated by  FIG. 4 . The opening and closing of these switches dictate the charging current flow from a regulated intermediate voltage source V IN  to two flying capacitors  18  and  20 , and transfer current flow from these flying capacitors to a load, thus enable the mode switching among 1×, 1.5×, 2×, and 3× modes. The same prior art also provides a voltage regulation circuit, illustrated by  FIG. 5 , in which an additional switching element  54  is used between a battery voltage V BATT  and the regulated intermediate voltage V IN , which is in turn used to provide input voltage to the switching circuit in  FIG. 4 . Thus, in order to switch among operation modes and regulate V OUT , the prior art uses eleven switching elements in total, three more than necessary as it will be explained in detail in the present invention.  
         [0017]     Also, although the same prior art claims that a 3× mode is achievable, it is not practical by using only two external flying capacitors  18  and  20  and one external output capacitor  22  as illustrated by  FIG. 4 . While in theory V OUT  can be a 3× multiple of V IN , in practice, as it is well known in the art, in order to accommodate an actually load, an additional flying capacitor is needed.  
         [0018]     Further more, the same prior art provides a block diagram of a switching control circuit, as illustrated in  FIG. 6 , which includes a mode select block  30 , a phase generator block  32 , a switch control block  38 . However, practical implementation circuits were not given for these blocks.  
       BRIEF SUMMARY OF THE INVENTION  
       [0019]     The present invention relates to an inductor-less DC/DC regulator commonly known in the art as charge pump or switched capacitor. It provides a complete and practical regulated multi-mode multi-phase inductor-less DC/DC regulator design, which was not provided by the cited prior art described in detail in U.S. Pat. No. 6,504,422B1 and U.S. Pat. No 6,794,926B2. The design comprises a resistor divider array, a voltage reference array, a switching control circuit, a switching and regulation circuit, and an output voltage. The design is illustrated in a set of detail circuit schematic diagrams in  FIGS. 1-3 .  
         [0020]     The resistor divider array comprises three resistors in series, between the DC power source and a common zero volt reference voltage, commonly known in the art as ground. The outputs of the resistor divider array are two DC voltages above ground that go to the switching control circuit. The voltage reference array comprises two constant DC reference voltage sources, commonly known in the art as bandgap references, in series. The outputs of the voltage reference array are two constant DC voltages above ground that go to the switching control circuit and the switching and regulation circuit. The outputs of the resistor divider array are compared to the outputs of the voltage reference array in the switching control circuit. The switching control circuit comprises two comparators with hysteresis feature, a clock source, two latching devices commonly known in the art as D flip flops, and a plurality of logic gates and pass elements. The comparison between the output voltages from the resistor divider array and the output voltages from the voltage reference array is done by the comparators with hysteresis feature. The results of the comparisons determine the desirable operation mode for the regulated charge pump.  
         [0021]     Once the desirable operation mode is determined, the clock source, the latching devices, and the logic gates and pass elements of the switching control circuit produce clocked switching control signals to the switching and regulation circuit. The switching and regulation circuit comprises a network of eight switching elements and two external charge storage capacitors, commonly known in the art as flying capacitors, and a voltage regulation circuit that also includes one of the eight switching elements. Thus, the present invention uses three fewer switching elements than the cited prior art described in detail in U.S. Pat. No. 6,504,422B1 and U.S. Pat. No 6,794,926B2. The switching elements are selectively actuated under the direction of the switch control signals to allow at least two different operation modes, each comprises at least two different phases. At least some of the switching elements change configurations when the phase changes to charge and discharge the external flying capacitors to provide a voltage at the output of the switching and regulation circuit. This voltage is then fed back to the voltage regulation circuit to enable the switching and regulation circuit to produce a regulated output voltage to the load.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIG. 1  is an inductor-less DC/DC regulator circuit schematic diagram of one embodiment of the present invention.  
         [0023]      FIGS. 2   a - c  are circuit schematic diagrams illustrating one embodiment of a switching control circuit of the inductor-less DC/DC regulator of  FIG. 1 .  
         [0024]      FIG. 3  is a circuit schematic diagram illustrating one embodiment of a switching and regulation circuit of the inductor-less DC/DC regulator of  FIG. 1 .  
         [0025]      FIG. 4  is a circuit diagram of a switching circuit of a prior art charge pump.  
         [0026]      FIG. 5  is a circuit diagram of an input voltage regulator of a prior art charge pump.  
         [0027]      FIG. 6  is a block diagram of a control circuit of a prior art charge pump.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     The present invention relates to an inductor-less DC/DC regulator commonly known in the art as charge pump or switched capacitor. A block diagram of an exemplary embodiment of an inductor-less DC/DC regulator, denoted generally by the numeral  100 , is shown in  FIG. 1 . The inductor-less DC/DC regulator  100  is connected in series between a DC power source  1000 , such as a battery, with a voltage level of V BATT , and a load  900 . The inductor-less DC/DC regulator provides a regulated constant DC output voltage, V OUT , to the load  900 .  
         [0029]     In  FIG. 1 , the inductor-less DC/DC regulator  100  comprises a resistor divider array  105 , a voltage reference array  175 , a switching control circuit  200 , and a switching and regulation circuit  600 . The switching control circuit  200  comprises a control signal generator  300 , a switching signal generator I  400 , and a switching signal generator II  500 . The level of the input voltage to the inductor-less DC/DC regulator  100 , V IN , is equivalent to V BATT .  
         [0030]     The mode in which the inductor-less DC/DC regulator  100  operates, after start up and during normal operation, is determined by the output voltage level, V BATT , of the power source  1000 , and the desired output voltage level, V OUT , to the load  900 .  
         [0031]     The resistor divider array  105  comprises three resistors  110 ,  120 ,  130  in series, with resistance values of R1, R2, R3, respectively. This three resistor arrangement enables mode selection and automatic mode switching among 1×, 1.5×, and 2× modes. The resistor divider array  105  outputs two voltage levels denoted as V H  and V L ; V H  always has a higher voltage level than V L . The values of R1, R2, and R3 are a function of V IN . The following formulas give the values of V H  and V L : 
 
 V   H   =V   IN ×( R 2 +R 3)/( R 1 +R 2 +R 3)  1) 
 
 V   L   =V   IN   ×R 3/( R 1 +R 2 +R 3)  2) 
 
         [0032]     The voltage reference array  175  comprises two constant DC voltage sources  190  and  180 , commonly known as bandgap voltage references, in series. Each bandgap voltage reference has an intrinsic output voltage that is a constant DC value over a wide range of temperatures. The two bandgap voltage reference arrangement enables mode selection and automatic mode switching among 1×, 1.5×, and 2× modes. The output of the bandgap voltage reference  190  with reference to ground is its intrinsic output voltage value V VRL . The output of the the bandgap voltage reference  180  with reference to ground is a combination of the intrinsic output voltage values of  190  and  180 , and is a constant DC voltage with a value of V VRH . V VRH  is always higher than V VRL  by the intrinsic output voltage value, V VRHI , of the bandgap voltage reference  180 . The values of V VRHI  and V VRL  are determined by V IN  and V OUT .  
         [0033]     After start up and during the normal operation of the inductor-less DC/DC regulator  100 , the following conditions determine the desirable mode in which it operates: 
        1) If V L &lt;V VRL , and V H &lt;V VRH , the condition indicates a low V IN  with reference to V OUT , and a 2× mode is desirable.     2) If V L &gt;V VRL , and V H &lt;V VRH , the condition indicates a medium V IN  with reference to V OUT , and a 1.5× mode is desirable.     3) If V L &gt;V VRL , and V H &gt;V VRH , the condition indicates a high V IN  with reference to V OUT , and a 1× mode is desirable.        
 
         [0037]     The condition under which V L &lt;V VRL  and V H &gt;V VRH  does not occur if the values of R2, R3, V VRH , and V VRL  are chosen as such: V VRHI /V VRL &lt;1+R2/R3, or V VRHI / V VRL &lt;R2/R3, in which V VRHI  is the intrinsic output voltage value of the bandgap voltage reference  180 .  
         [0038]     As shown in an exemplary embodiment of the control signal generator  300 , illustrated in  FIG. 2   a , the actual comparison between V H  and V VRH  is performed by a comparator  310 . The actual comparison between V L  and V VRL  is performed by a comparator  320 . The comparators  310  and  320  have a built-in feature commonly known in the art as hysteresis. The hysteresis feature prevents a comparator from switching output by false or insignificant conditions such as a high voltage short burst on one of its inputs induced by an external noise source. The logic values of the outputs of the comparators  310  and  320 , V CH  and V CL , respectively, are given below: 
        1) V CH =logic high, or H, and V CL =H, which indicates that conditions of V L &lt;V VRL  and V H &lt;V VRH  have been detected by the comparators, and a 2× mode is desirable.     2) V CH =H, V CL =logic low, or L, which indicates that conditions of V L &gt;V VRL  and V H &lt;V VRH  have been detected, and a 1.5× mode is desirable.     3) V CH =L, V CL =L, which indicates that conditions of V L &gt;V VRL  and V H &gt;V VRH  have been detected, and a 1× mode is desirable.        
 
         [0042]     Thus, the desirable operation mode of the inductor-less DC/DC regulator  100  at any given time is controlled by the logic values of the outputs of the comparators  310  and  320 , V CH  and V CL , respectively, at that particular time. If, at a certain point of time during normal operation, the battery output voltage, V BATT , changes in either direction and crosses a predetermined threshold voltage, the logic values of either V CH  or V CL , or both, change as well, indicating an automatic mode switching is desirable at that particular point of time. The actually initial mode selection immediately after start up is accomplished by positioning the switching elements Q 1 -Q 8  of a switching and regulation circuit  600  in  FIG. 3  to configurations particular to the desirable mode. The actually automatic switching between modes during normal operation is accomplished by changing the switching elements Q 1 -Q 8  from configurations particular to the current mode to configurations particular to the desirable mode. The mechanism of configuring the switching elements Q 1 -Q 8  will be explained in more detail later.  
         [0043]     There are two operation phases for the inductor-less DC/DC regulator  100 , the charging phase and the transfer phase. The time durations of the charging and transfer phases and the automatic switching between charging and duration phases are controlled by a fixed frequency clock signal, CLK, generated by an internal clock source  330 , illustrated in  FIG. 2   a . The charging phase happens during the logic high interval of a clock cycle. In charging phase, the switching elements Q 1 -Q 8  of a switching and regulation circuit  600  in  FIG. 3  are positioned in certain configurations to allow a charging current to flow into the flying capacitors  810  and  820  from the battery  1000 . The transfer phase happens during the logic low interval of a clock cycle. In transfer phase, the switching elements Q 1 -Q 8  are positioned in certain configurations to allow a transfer current to flow out of the flying capacitors  810  and  820  to the load  900 . The automatic switching between the charging and transfer phases happens twice during one clock cycle. The mechanism of actuating the switching elements Q 1 -Q 8  between phases will be explained in more detail later.  
         [0044]     As shown in the control signal generator  300  in  FIG. 2   a , V CH  and V CL  further propagate into the D logic inputs of latching devices  340  and  350 , commonly known in the art as D latches or D flip flops, respectively. The use of the D latches  340  and  350  is to couple the V CH  and V CL  with the output of an internal clock source  330  to produce clocked outputs V QH , V QBH , and V QL  to drive the subsequent logic gates U 1 -U 7  of the switching signal generator I  400  in  FIG. 2   b , and logic gates U 8 -U 10  and controlled passing elements  510  and  520  of the switching signal generator II  500  in  FIG. 2   c . The clock source  330  provides a fixed frequency clock signal, CLK, to the CLK inputs of the D flip flops  340  and  350 . D flip flop  340  has two logic outputs, Q and /Q. The logic level of Q output, V QH , follows that of V CH  with a delay of a clock cycle. The logic level of /Q output, V QBH , is the logic inverse of that of V QH . For example, when V QH  has a logic level of H, V QBH  has a logic level of L. D flip flop  350  has one logic output, Q. The logic level of Q output, V QL , follows that of V CL  with a delay of a clock cycle. The logic levels of V QH , V QBH , and V QL , are given as follows: 
        1) V QH =H, V QBH =L, and V QL =H, all with 1 clock cycle delay, when a 2× mode is desirable, with V CH =H and V CL =H.     2) V QH =H, V QBH =L, and V QL =L, all with 1 clock cycle delay, when a 1.5× mode is desirable, with V CH =H, V CL =L.     3) V QH =L, V QBH =H, and V QL =L, all with 1 clock cycle delay, when a 1× mode is desirable, with V CH =L, V CL =L.        
 
         [0048]     The clock signal CLK controls the duration of the charging and transfer phases, and the switching between the charging and transfer phases. The charging phase occurs during the logic high interval of a clock cycle, the transfer phase occurs during the logic low interval of a clock cycle.  
         [0049]     In an exemplary embodiment of a switching signal general I  400  depicted by  FIG. 2   b , V QH , V QL  are used in conjunction with the clock signal CLK to drive a network of logic gates U 1 -U 7  to provide switching control signals Q 4 G, Q 5 G, Q 6 G, Q 7 G, and Q 8 G to actuate switching elements Q 4 , Q 5 , Q 6 , Q 7 , and Q 8  of a switching and regulation circuit  600  in  FIG. 3 . In an exemplary embodiment of switching signal general II  500  depicted by  FIG. 2   c , the clock signal CLK is used in conjunction with V QBH  to drive a network of logic gates U 8 -U 10  and controlled passing elements  510  and  520  to produce switching control signals Q 1 G and Q 3 G to actuate switching elements Q 1  and Q 3 , and switching and regulation control signal REG to enable or disable a voltage regulation circuit  505  of a switching and regulation circuit  600  in  FIG. 3 . Table 1 below shows the logic levels of Q 1 G, Q 3 G, Q 4 G, Q 5 G, Q 6 G, Q 7 G, Q 8 G, and REG during each of the three modes in both charging and transfer phases.  
                                                                                         TABLE 1                                       Switching Control Signal Logic Levels            Mode   Phase   V CH     V CL     V QH     V QBH     V QL     CLK   Q1G   REG   Q3G   Q4G   Q5G   Q6G   Q7G   Q8G               1×   Charging   L   L   L   H   L   H   L   H   L   L   L   L   L   H       1×   Transfer   L   L   L   H   L   L   H   L   H   L   L   L   L   L       1.5×   Charging   H   L   H   L   L   H   H   H   H   L   H   L   H   H       1.5×   Transfer   H   L   H   L   L   L   L   L   L   H   L   H   L   H       2×   Charging   H   H   H   L   H   H   H   H   H   L   L   H   L   H       2×   Transfer   H   H   H   L   H   L   L   L   L   H   L   H   L   H                  
 
         [0050]     In an exemplary embodiment of a switching and regulation circuit  600  depicted by  FIG. 3 , all switching elements Q 1 -Q 8  are of a transistor type commonly known in the art as enhancement mode N channel MOSFET. The state, or configuration, of a typical enhancement mode N channel MOSFET, either open or close, is controlled by the logic voltage level applied to its gate terminal. The typical enhancement mode N channel MOSFET is at open or off state when a logic low voltage of value L applied to its gate terminal, and is at close or open state when a logic high voltage of value H applied to its gate terminal. In the switching and regulation circuit  600 , the configurations of switching elements Q 1 -Q 8  are controlled by Q 1 G, REG, and Q 2 G-Q 8 G, respectively. Table 2 below shows the configurations of the switching elements Q 1 -Q 8  during each of the three modes in both charging and transfer phases. The switching element Q 2  is not actuated directly by signal REG, rather, it is used as both a switching element and an output voltage regulation pass transistor as explained in detail below.  
                                                                 TABLE 2                                       Switching Element Configurations            Mode   Phase   Q1   Q2   Q3   Q4   Q5   Q6   Q7   Q8               1×   Charging   open   close   open   open   open   open   open   close       1×   Transfer   close   open   close   open   open   open   open   open       1.5×   Charging   close   close   close   open   close   open   close   close       1.5×   Transfer   open   open   open   close   open   close   open   close       2×   Charging   close   close   close   open   open   close   open   close       2×   Transfer   open   open   open   close   open   close   open   close                  
 
         [0051]     The regulated output of the inductor-less DC/DC regulator  100 , V OUT , is regulated as shown in an exemplary embodiment of a voltage regulator circuit  605  of the switching and regulation circuit  600  in  FIG. 3 . The V OUT  is first divided down by a resistor divider comprises resisters  630  and  640 , with resistance values of R4 and R5, respectively. The after division voltage, V OUTF , with a value of V OUT ×R5/(R4+R5), is then fed back to the inverting input of an error amplifier  610 . R4 and R5 are chosen in such a way that when V OUT  reaches the desired output voltage level, V OUTF  is equal to the output voltage of the bandgap voltage reference  190 , V VRL . During a transfer phase under any operation mode, the REG is always at logic low, which disables the error amplifier  610  and forces a logic low output on the output of the error amplifier  610  to keep the switching and regulation element  620  at open or off state. During a charging phase, the REG is always at logic high to enable the error amplifier  610 . The error amplifier  610  amplifies the voltage differential between V OUTF  and V VRL . Its output drives the gate of the switching and passing element  620  to adjust the charging current coming into flying capacitors  810  and  820  during 1.5× and 2× modes, or  810  during 1× mode. The output voltage V OUT  is thus regulated to the desired voltage level.