Abstract:
The invention relates to a dynamic conversion circuit for improving the transient response of a switching DC-DC converter, such as in a voltage regulator module (VRM). The dynamic conversion circuit may be applied to a single phase or multiphase interleaved VRM of either isolated or non-isolated design configurations, and enhances power transfer from the input to the output of the DC-DC converter and tightly regulates the output voltage during harsh load current transients.

Description:
FIELD OF THE INVENTION 
   This invention relates generally to a voltage regulator module (VRM). In particular, the invention relates to a dynamic conversion circuit for enhancing the transient response of a DC-DC converter of a VRM for demanding loads such as microprocessors. 
   BACKGROUND OF THE INVENTION 
   A voltage regulator module (VRM) is used to regulate a DC voltage supplied to a load, such as microprocessor. A VRM includes a power converter, such as a DC-DC converter, and may include other components such as a controller for controlling operation of the power converter. An example of a DC-DC converter is a synchronous buck converter, as shown in  FIG. 1 , which has minimal components, and therefore is widely used in VRM applications. In microprocessor applications, the input voltage to the VRM is typically 12V DC . The output voltage may be 5.0 V DC , 3.3 V DC , or lower. 
   As microprocessors become more advanced, required supply voltages become lower. Supply voltages are expected to be as low as 0.5 V DC  in the near future, which will require currents up to 200 A or more. Currently, the CPU of a typical personal computer operates at 3 GHz, and operating frequencies are expected to reach 10 GHz in the near future. A consequence of the low supply voltage and high clock frequency is the high slew rate (di/dt) of the load current at power up. For example, when a microprocessor wakes from sleep mode to full operating mode, the step of the output current may be as high as 200 A, with a slew rate of 1,000 A/μs or higher. The slew rate may reach 1,000 A/μs in future designs. The voltage supplied to current microprocessors is required to be regulated within 2%, and 1% for future VRMs (“VRM 9.1 DC-DC converter design guidelines”, Intel Order Number 298646-001, January 2002). The absolute value of such voltage regulation is currently 30 mV and 10 mV for future designs. Such tight voltage regulation is required to maintain normal operation of CMOS transistors in the microprocessor under all conditions. For instance, under worst case (high slew rate of the output current) conditions, the output voltage should not drop by more than 30 mV to avoid abnormal operation of the CPU. However, the voltage drop of VRMs based on existing designs may be so large that the output voltage regulation limit may easily be exceeded. 
   Various VRM topologies and control methods have been proposed in an attempt to satisfy the transient response requirements of microprocessors. However, such designs are not well-suited to the harsher dynamic requirements of next generation microprocessors. 
   For example, simply increasing the output capacitance can reduce the output voltage ripple, and also help maintain the output voltage during a sudden load change. However, for a single phase 1.5 V DC /25 A VRM, for instance, a design that can meet the steady state and transient voltage regulation specification typically requires at least 5,000 μF output capacitance. Such filter capacitors are bulky and expensive. It is estimated that for a VRM supplying 0.5 V DC at  100 A, the required output capacitance would be more than 10,000 μF, and should have considerably lower equivalent series inductance (ESL) and equivalent series resistance (ESR) to be effective during load transients.  FIG. 2  (top curve only) shows such a relationship between the output capacitance and load current for typical prior VRMs. Although multiphase topology, which helps to reduce output capacitance, may be used for applications when the load current exceeds 20 A, the value of the capacitance is still exceedingly high at high load current. 
   Reducing the output inductance of a buck converter can improve its dynamic response. However, the inductance can not be reduced unbounded, otherwise the output voltage ripple will increase above acceptable limits (e.g., above 10 mV for next generation microprocessors). The increased voltage ripple will in turn reduce the room for the output voltage drop during dynamics. In addition, a larger ripple current through the filter inductor implies a larger RMS current through the power switches, which will reduce the overall efficiency of the VRM under steady state operation. Moreover, even though the inductance can be reduced for a faster dynamic response, it is not enough to provide adequate response speed for future microprocessors if the output capacitance is required to be small to reduce cost and to satisfy size and volume constraints. 
   Multiphase interleaved VRM topology provides two or more power converters in parallel and shares the same output capacitors among converters. In each of the power converters (or each phase), the filter inductor can be smaller than that of a single phase VRM to achieve a faster dynamic response. The large output voltage ripple in each phase due to the small inductance can be cancelled by the ripple of other phases. The more phases are in parallel, the smaller the ripple will be, but at the expense of increased circuit cost. Multiphase topology can therefore enhance the output current capability of a VRM. However, if the output current can be provided by a single phase VRM or a VRM with fewer phases, then adopting a multiphase topology or adding extra phases in parallel solely for the purpose of reducing the ripple voltage adds considerable complexity, size, and cost. More importantly, it is very difficult for a conventionally-controlled multiphase VRM to achieve the dynamic response required by future microprocessors, without having very large output capacitance. 
   Current mode control has a faster dynamic response than that of conventional voltage mode control, in situations where only a small perturbation such as a small load change occurs. However, its dynamic performance is not superior to that of voltage mode control when a large transient occurs. More importantly, in current mode control, the current is detected by employing a sensing resistor or a current transformer. However, for an output current of 100 A or higher, it would be impractical to use a resistor to accurately and efficiently sense the current. On the other hand, a current transformer is bulky and the sensed current must be averaged, resulting in further increases in the reaction time and drop in the output voltage when a large load step happens. 
   The voltage droop control method takes advantage of the upper and lower limits of the VRM output voltage to gain more room for dynamic responses. When the load current is low, the reference voltage is set to be higher than the nominal value but still within the specified upper limit. When a load step-up happens, the output voltage will drop but will have more room to drop than if it were starting from the nominal value. When the load current is high, the reference voltage is set to be low; thus when a load step-down happens, the output voltage has more room for the overshoot. However, this small room is far from being enough to handle the harsh dynamic requirements of the next generation microprocessors. Moreover, the voltage droop control method also requires current sensing, which again is not very practical, as discussed above. 
   Operating the power converter at a very high frequency will improve the dynamic response of a VRM having a very small output capacitance. However, design of an efficient power converter operating at a very high frequency is difficult. Further, the efficiency of a power converter decreases eventually to an unacceptable or unsatisfactory level as its operating frequency increases. In general, increasing the switching frequency of a power converter solely for the purpose of improving the dynamic performance is not an optimum solution. 
   A linear regulator array inserted between the VRM and the load was disclosed in U.S. Pat. No. 6,429,630, issued Aug. 6, 2002 to Pohlman et al. This intermediate linear regulator removes the strict requirement on the output voltage regulation of the VRM, making the design of the VRM much simpler. However, during normal steady state operation at full load, for example, the voltage drop across the linear regulator together with the DC current through it results in power loss. The power loss may not be a problem when the load consumes only a small amount of current, and this solution can possibly provide the required dynamic response. However, loads such as the next generation CPU will demand a large load current, which would require a linear regulator to dissipate power excessively during normal steady state operation. In addition, partitioning of the CPU into different power zones and an associated interface are required to make linear regulation feasible, because a single transistor is not capable of delivering a high current and at the same time effectively dissipating the heat due to the large power loss. Wide acceptance of such designs is unlikely, especially when other solutions potentially exist. Therefore, the linear regulator is impractical for applications in future microprocessors. 
   A stepping inductor method for fast transient response of switching converters is disclosed in U.S. Pat. No. 6,188,209, issued Feb. 13, 2001 to Poon et al. Relative to the basic buck converter, this design requires significantly more circuit components, which may be difficult and expensive to implement in a multiphase interleaved VRM, because all of the components need to be repeated for each phase. Moreover, the control circuit for load transients is analog based and the output voltage is compared to fixed hysteresis reference voltages to trigger and terminate the transient operation of the converter independently of the load current conditions. This implies that the transient circuit works the same way for a 25%, 50%, and 100% load step, for instance. Therefore, the voltage response during a load transient is not regulated and may exceed the specified limits of the output voltage during many load conditions. 
   A transient override circuit is proposed in U.S. Pat. No. 6,696,882, issued Feb. 24, 2004 to Markowski et al. This circuit detects the load voltage level to trigger a transient operation mode of the VRM. In transient operation mode, the power switch of a buck converter is forced to be turned on, and the synchronous power switch of the buck converter is turned off, to override the current through the output inductor. However, the circuit and the control method are analog based, and, importantly, are not able to regulate the output voltage during the transient. 
   SUMMARY OF THE INVENTION 
   According to one aspect of the invention there is provided a dynamic conversion circuit for increasing power output of a switching DC-DC converter during a load transient, comprising: a series circuit comprising a switch, the series circuit connected in parallel with at least a portion of the DC-DC converter; wherein the switch is activated in accordance with the load transient; and wherein activation of the switch comprises turning the switch on and off at a frequency higher than a switching frequency of the DC-DC converter. 
   The switch may be activated in accordance with a load transient associated with at least one of: (i) a decrease in the output voltage of the DC-DC converter below a minimum output voltage; and (ii) an increase in output current of the DC-DC converter above an operating output current. 
   In one embodiment, the series circuit further comprises a series inductor. Preferably, the inductor of the series circuit is of a smaller inductance value than an output inductor of the DC-DC converter. In another embodiment, the at least a portion of the DC-DC converter comprises a series output inductor. In another embodiment, the series circuit is connected in parallel with the DC-DC converter. 
   Activation of the switch may comprise turning the switch on and off with a pulse train of constant duty cycle, the pulse train having a frequency higher than the switching frequency of the DC-DC converter. In another embodiment, activation of the switch may comprise turning the switch on and off with a pulse train of varying duty cycle, the pulse train having a frequency higher than the switching frequency of the DC-DC converter. 
   In another embodiment, the dynamic conversion circuit may further comprise a controller for sensing the output voltage of the DC-DC converter and controlling activation of the switch. 
   In various embodiments, the DC-DC converter may be of isolated or non-isolated circuit topologies, such as buck, boost, and buck-boost circuit topologies. In a preferred embodiment, the DC-DC converter is a buck converter. 
   According to another aspect of the invention there is provided a voltage regulator module (VRM), comprising: a switching DC-DC converter having an input for accepting an input DC voltage and an output for outputting a converted DC voltage to a load; the dynamic conversion circuit described above; and a controller for activating the switch of the dynamic conversion circuit during a load transient; wherein activation of the switch comprises turning the switch on and off at a frequency higher than a switching frequency of the DC-DC converter. 
   The voltage regulator module may further comprise at least a second DC-DC converter. In various embodiments, the DC-DC converters may be of isolated or non-isolated circuit topologies, such as buck, boost, and buck-boost circuit topologies. In a preferred embodiment, the DC-DC converters are buck converters. 
   According to another aspect of the invention there is provided a method for increasing power output of a switching DC-DC converter during a load transient, comprising: connecting a series circuit in parallel with at least a portion of the DC-DC converter, the series circuit comprising a switch; and activating the switch in accordance with the load transient; wherein activating the switch comprises turning the switch on and off at a frequency higher than a switching frequency of the DC-DC converter. 
   In one embodiment, the method may comprise connecting a series circuit in parallel with at least a portion of the DC-DC converter, the series circuit comprising a switch and an inductor. In another embodiment, the method may comprise connecting the series circuit in parallel with a series output inductor of the DC-DC converter. Another embodiment may comprise connecting the series circuit in parallel with the DC-DC converter. 
   Activating the switch in accordance with the load transient may comprise activating the switch in accordance with at least one of: (i) a decrease in the output voltage of the DC-DC converter below a minimum output voltage; and (ii) an increase in output current of the DC-DC converter above an operating output current. 
   In one embodiment, activating the switch may comprise turning the switch on and off with a pulse train of constant duty cycle, the pulse train having a frequency higher than the switching frequency of the DC-DC converter. In another embodiment, activating the switch may comprise turning the switch on and off with a pulse train of varying duty cycle, the pulse train having a frequency higher than the switching frequency of the DC-DC converter. 
   The method of the invention may further comprise connecting two or more DC-DC converters in parallel, and connecting the series circuit in parallel with the two or more DC-DC converters. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
     Embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram of a prior art single phase synchronous buck converter; 
       FIG. 2  is a plot of estimated output capacitance versus load current for the invention compared with prior art VRMs; 
       FIG. 3  is a block diagram of a VRM according to the invention; 
       FIG. 4  is a schematic diagram of a single phase VRM circuit according to a first embodiment of the invention; 
       FIG. 5  is a schematic diagram of a single phase VRM circuit according to a second embodiment of the invention; 
       FIG. 6  is a schematic diagram of a multiphase interleaved VRM circuit according to a third embodiment of the invention; 
       FIG. 7  shows waveforms of the single phase VRM circuit of  FIG. 4 ; 
       FIG. 8  shows waveforms of the multiphase interleaved VRM circuit of  FIG. 6 ; and 
       FIG. 9  is a plot showing the results of a simulation comparing the output voltage waveforms of a VRM of the invention and a conventional voltage mode controlled VRM during a load transient, in which V g =12 V DC , V o =1.5 V, I o =25 A, C o =500 μF, f s =250 kHz, and the load steps from 0.5 A to 25 A. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
   According to one aspect of the invention there is provided a dynamic conversion circuit for use with a power converter, such as a switched mode DC-DC converter. The dynamic conversion circuit may be used with a power converter in a voltage regulator module. The dynamic conversion circuit is capable of responding rapidly to sudden changes in the load connected to the power converter output, which would otherwise result in a decrease in the output voltage from its nominal value. The dynamic conversion circuit prevents or minimizes any reduction in output voltage of the power converter resulting from a sudden increase in the load, by increasing the output current of the power converter during a load transient. Thus, the dynamic conversion circuit substantially improves the voltage regulation of the VRM under dynamic load conditions. The dynamic conversion circuit may be used with any isolated or non-isolated switching DC-DC converter, such as, for example, buck, boost, or buck-boost, for any load requiring tight voltage regulation under both steady-state and transient conditions. The invention will be described primarily with respect to a buck converter; however, it will be appreciated that the invention is not limited thereto. Further, the power conversion circuit may be used with either single phase or multiphase interleaved power converters, depending on how much load current is required. The dynamic conversion circuit is particularly suitable for a VRM for a microprocessor, which may present an extremely dynamic load to the VRM and at the same time require high current and regulation of supply voltage within very narrow limits. 
   According to the invention, increasing the switching frequency of the DC-DC converter is unnecessary, because an increased switching frequency is not needed to improve the dynamic response of the converter. The switching frequency may be kept below 500 kHz to achieve a higher efficiency and at the same time maintain a very fast dynamic response with greatly reduced output capacitance. The greatly reduced output capacitance enables the use of ceramic capacitors, which are smaller in size and have a much smaller equivalent series resistance (ESR). Consequently, a VRM according to the invention will require less space on a PCB board and cost will be reduced. 
     FIG. 3  is a block diagram showing a VRM, which includes a power converter  20 , a dynamic conversion circuit  30 , and a controller  50 . The VRM is connected to a load  60 . The dynamic conversion circuit  30  is shown connected in parallel with the power converter  20 ; however, in some embodiments, the dynamic conversion circuit  30  may be connected in parallel with only a portion of the power converter  20 . Such embodiments are discussed in detail below. As shown in  FIG. 3 , the controller  50  is connected to the output of the power converter (i.e., the output of the VRM), and has connections to the dynamic conversion circuit and optionally to the power converter. The controller  50  may be incorporated into the dynamic conversion circuit  30 , or it may be a separate block as shown in  FIG. 3 . The controller may be implemented digitally, as described in our co-pending U.S. patent application Ser. No. 11/261,661, incorporated herein by reference in its entirety. 
   In one embodiment the dynamic conversion circuit comprises a switch, and, optionally, an output inductor connected in series with the switch. In one embodiment the dynamic conversion circuit is connected in parallel with the power converter. In such embodiment, the dynamic conversion circuit substantially provides a connection between the power supply (e.g., the DC bus) and the load when the switch of the dynamic conversion circuit is on, thereby providing the load with the required current, and minimizing any voltage drop experienced by the load. In another embodiment, the dynamic conversion circuit is connected in parallel with at least a portion of the power converter circuit, and thereby substantially bypasses that portion of the power converter circuit when the switch of the dynamic conversion circuit is on. 
   It will be appreciated that for proper operation of the VRM the dynamic conversion circuit should function only during a load transient; i.e., only when the current demand of the load rises above the steady state current so as to cause a drop in the output voltage of the power converter. Accordingly, the controller  50  shown in  FIG. 3  senses the output voltage and/or current of the power converter. When the output voltage drops to or below a threshold voltage, and/or when the output current rises above an operating current (i.e., a steady state current), the controller sends a signal to the dynamic conversion circuit, activating the switch of the dynamic conversion circuit. Activating refers to turning the switch of the dynamic conversion circuit on and off at a frequency higher than the switching frequency of the power converter, such as for example, 2 to 10 times higher, or 2 to 100 times higher, or higher as may be possible with available technology. The controller may optionally control operation of the power converter during a load transient in a way that maximizes output current of the power converter (e.g., by providing gate signals for appropriately opening/closing switches of the power converter). The controller monitors the output voltage and/or current and keeps activating the switch of the dynamic conversion circuit as required to maintain the output voltage at the desired value. 
   According to another aspect of the invention there is provided a VRM comprising a DC-DC converter, a dynamic conversion circuit as described herein, and a controller. 
   In one embodiment, the invention provides a single phase VRM as shown in  FIG. 4 . This embodiment comprises a synchronous buck converter with switches S 1 , S 2 , output inductor L o , and output capacitor C o , a dynamic conversion circuit with switch S aux , inductor L aux , and a controller. Preferably the controller is digitally implemented to realize the present control method for fast load transient response of the VRM. Inductor L aux  in the dynamic conversion circuit has a substantially smaller value than that of L o . V g  is the input DC voltage, normally from the motherboard DC bus if the load is a microprocessor. S 1  and S 2  are the switching power devices, which accept the pulse width modulation (PWM) gate signals generated by the controller. L o  and C o  comprise the output filter of the synchronous buck converter. The load shown in  FIG. 4  is a microprocessor. 
   The auxiliary power switch S aux  of the dynamic conversion circuit is connected to the node formed by the connection of power switches S 1 , S 2  and then is connected in series to auxiliary inductor L aux , which is connected to the load terminal. Thus, the series circuit of S aux  and L aux  is connected in parallel with inductor L o . 
   During normal steady state operation or when a load transient is within a certain range (e.g., a load transient small enough that V o  remains at or above a minimum (threshold) value), the pulse width of the gate signals to the synchronous buck converter switches S 1  and S 2  is determined by the sensed load voltage, the nature of the power converter, and the way the system is compensated. The waveforms of the gate signals V gs1  and V gs2  of S 1  and S 2  are shown in  FIG. 7 , in the time section referred to as Normal Steady State Mode (t 0 -t 2 , t 3 -∞). In this operation mode, the power switch S aux  of the dynamic conversion circuit is in its off state, i.e., the dynamic conversion circuit will not have any effect when the load condition is normal and the VRM is in its normal steady state operation. 
   In  FIG. 7 , a sudden load current step ΔI o  occurs at time t 1 . After a short processing time delay t d , at time t 2 , the controller detects the load change and turns on the power switch S 1 . The switch S 1  is turned on and kept on for duration of t a  and turned off at time t 3 , while switch S 2  is kept off during this period. The time duration t a  is calculated by the controller according to an algorithm. With this control method, the gate pulse to S 1 , V gs1  can be provided quickly and may be of sufficient width to supply current to the output filter inductor L o  during a load transient. The current through L o  can therefore be ramped up quickly to supply the load and thus maintain the output voltage level. The gate signals V gs1  and V gs2  during such a load transient are shown in  FIG. 7 , in the time section referred to as Dynamic Mode (t 2 -t 3 ). 
   The dynamic conversion circuit is also activated by the controller during this load transient. When S 1  is turned on and S 2  is turned off for the time period t a , the power switch S aux  of the dynamic conversion circuit is activated. Here, “activated” refers to switching on and off of S aux  many times within the time period t a  (i.e., at a frequency higher than the switching frequency of the buck converter). Switching on and off of S aux  may be carried out with or without modulating the pulse width of the gate drive signal V gs     —     aux . Three examples of such gate drive signals are shown in  FIG. 7 . 
   In  FIG. 7 , the time period t a  is expanded to show the gate signals of S 1  and S aux  in Dynamic Mode (t 2 -t 3 ). In particular, it can be seen that during t a , the switch S aux  is activated and is switched at a fixed frequency much higher than that of the synchronous buck converter (e.g., 10 times higher). Because the inductor L aux  in the dynamic conversion circuit has a substantially smaller value than that of L o , the power transferred from the input to the output of the VRM during a load transient is greatly increased. 
   Three gate patterns of S aux  during a load transient are shown in  FIG. 7 . However, the gate signal of S aux  is not limited to those three patterns. The first gate pattern of S aux  (option  1  in  FIG. 7 ) switches S aux  at a fixed switching frequency higher than that of the main power circuit, for example, 10 times higher. The pulse width of the gate signal is constant, predefined by the controller. 
   The second gate pattern of S aux  (option  2  in  FIG. 7 ) also switches S aux  at a frequency higher than that of the main power circuit (e.g., 10 times higher). The gate signal is pulse width modulated. The output voltage of the VRM is sensed and compared with a reference voltage. The error between the sensed output voltage and the reference voltage is minimized by a compensator similar to the compensator of the main power circuit. However, the compensator for the dynamic conversion circuit may have a larger gain. The compensation may be implemented digitally by the controller. The pulse width of the gate is thus varying. Initially the duty cycle of the gate signal of S aux  is the same as the duty cycle of the main power circuit in steady state operation. As the output voltage drops due to the load transient, the duty cycle of V gs     —     aux  increases according to the compensated PWM modulation. The duty cycle decreases as the output voltage increases. This gate pattern of S aux  during a transient is realized by the controller. 
   The third gate pattern of S aux , (option  3  in  FIG. 7 ) also switches S aux  at a frequency higher than that of the main power circuit. The pulse width of the gate signal is predefined to be large initially and then is decreased linearly as a function of time. The decreasing rate of the duty cycle is also predefined or calculated by the controller. 
   Another embodiment of a VRM according to the invention is shown in  FIG. 5 . In this embodiment the main power conversion circuit is a synchronous buck converter. V g  is the input DC voltage. S 1  and S 2  are switching power devices, which accept pulse width modulation (PWM) gate signals generated by the controller. L o  and C o  are the output filter inductor and capacitor of the synchronous buck converter. The dynamic conversion circuit comprises an auxiliary power switch S aux  which is connected to the input of the VRM in this embodiment, and then connected in series to an auxiliary inductor L aux , which is connected to the load directly. Thus, the series circuit of the switch S aux  and the inductor L aux  is connected in parallel with the input and output of the DC-DC converter circuit. The operation modes and the control method of this embodiment are the same as that of the first embodiment, and are discussed above in detail. 
   A further embodiment of a VRM according to the invention is shown in  FIG. 6 . This embodiment relates to a multiphase interleaved synchronous buck converter. In  FIG. 6 , a four phase converter is shown; however, any number of phases may be implemented. Further, the phases are not limited to buck converters. 
   In  FIG. 6 , S a1 , S b1 , and L o1  are the power switches and the output filter inductor of the first branch of the multiphase interleaved synchronous buck converter. S a2 , S b2 , and L o2  are the power switches and the output filter inductor of the second branch of the multiphase synchronous buck converter, and so on. C o  is the output filter capacitor of the VRM, which is shared by all of the synchronous buck converter branches. I o  is the load current and represents the load. 
   During normal steady state operation mode or when a load transient is within a certain range (e.g., a load transient small enough that V o  remains at or above a minimum value), the pulse width of the gate signal to the synchronous buck converters is PWM modulated based on voltage mode control. However, the gate signals V gs     —     a1 , V gs     —     a2 , V gs     —     a3 , and V gs     —     a4 are phase shifted as illustrated in  FIG. 8 . The gate signals V gs     —     b1 , V gs     —     b2 , V gs     —     b3 , and V gs     —     b4  are complementary of gate signals V gs     —     a1 , V gs     —     a2  V gs     —     a3  and V gs     —     a4 . Under this operation mode, the power switch S aux  of the dynamic conversion circuit is off. This operation mode is shown in the duration of t 0 -t 2  and t 3 -∞ in  FIG. 8 . 
   During a load transient in the duration of t o1 -t 2  in  FIG. 8 , the switches S a1 , S a2 , S a3 , and S a4  ( FIG. 6 ) are turned on and kept on for a period of t a  defined by the controller, while the switches S b1 , S b2 , S b3 , and S b4  are kept off during this transient. The current through L o1 , L o2 , L o3  and L o4  can therefore be ramped up quickly to supply the load and thus help maintain the output voltage level. The dynamic conversion circuit is also activated by the controller during this load transient. When S a1 , S a2 , S a3 , and S a4  are turned on and S b1 , S b2 , S b3 , and S b4  are turned off for a time period of t a , the power switch S aux  of the dynamic conversion circuit is activated, as described above in respect of the embodiment shown in  FIG. 4 . Thus S aux  is turned on and off at a frequency higher than the switching frequency of the buck converters. Exemplary gate signal patterns are shown in  FIG. 8 , and are the same as the examples described above. 
   The inductor L aux  in the dynamic conversion circuit has a much smaller value than that of L o1 , L o2 , L o3 , and L o4 . The power transferred from the input to the output of the VRM during a load transient is thus further accelerated. Because of this dynamic conversion circuit, the values of inductors L o1 , L o2 , L o3 , and L o4  can be larger than that of prior multiphase interleaved synchronous buck converters. This is because during the load transient, power is transferred from the input to the output primarily through the small inductor L aux  of the dynamic conversion circuit. Also different from prior circuits, the power transfer through L aux  is regulated during the transient for a much better regulated output voltage. Relatively larger L o1 , L o2 , L o3 , and L o4  will reduce the current ripple of the circuit, and hence increase the efficiency of the converter. The control loop of the VRM will also be more stable if the inductors L o1 , L o2 , L o3 , and L o4  have larger values. Since the filter inductors of the branches can be large, paralleling more phases for the purpose of reducing the ripple current becomes unnecessary. Thus the number of paralleled phases can be minimized, and phases are only paralleled for the purpose of transferring more load current. 
   The invention is further illustrated by way of the following non-limiting example. 
   EXAMPLE 
   A voltage regulator module based on a buck converter, including a dynamic conversion circuit as described herein, suitably, was simulated in PSPICE v.9.0 and its performance evaluated with respect to a VRM based on a typical buck converter. The input and output voltages of the two VRMs was 12 V dc  and 1.5 V dc  respectively, and the switching frequency of the two circuits was 250 kHz. The rated output current was 25 A and the load transient was from 0.5 A to 25 A, at a slew rate of 1000 A/μs. The results of the simulation are shown in  FIG. 9 , where it can be seen that the voltage drop of the VRM of the invention was less than 10% of that of the typical VRM. According to the simulation, to avoid exceeding a 70 mV output voltage drop at a 100% load current transient (25 A), an output capacitance of only 500 μF was required. In contrast, the conventional voltage mode controlled single phase VRM needed at least 5000 μF output filter capacitance. This is an approximately 10-fold reduction in output capacitance, which represents substantial savings in space on the printed circuit board, and ultimately in cost. 
   All cited documents are incorporated herein by reference in their entirety. 
   Those of ordinary skill in the art will recognize, or be able to ascertain through routine experimentation, equivalents to the embodiments disclosed herein. Such equivalents are within the scope of the invention and are covered by the appended claims.