Abstract:
An array substrate for an electronic display includes a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; a silicide layer on the source and drain electrodes; and a first passivation layer on the source electrode and the drain electrode. The array substrate and fabrication method thereof prevent degradation of a thin-film transistor (TFT) used in driving pixels of the electronic display.

Description:
[0001]    The present application claims the priority benefit of Korean Patent Application No. 10-2013-0134824 filed in Republic of Korea on Nov. 7, 2013, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. 
       BACKGROUND 
       [0002]    1. Field of the Disclosure 
         [0003]    The present disclosure relates to an array substrate, and particularly, an array substrate including an oxide semiconductor layer and a method of fabricating the same. 
         [0004]    2. Discussion of the Related Art 
         [0005]    Recently, facing an information laden society, a field of processing and displaying mass information has rapidly advanced, and many kinds of flat display devices are developed and highly favored. 
         [0006]    As the flat display devices, liquid crystal display devices (LCDs), plasma display panel device (PDPs), field emission display devices (FEDs), electroluminescent display device (ELDs), organic light emitting diodes (OLEDs) are used. These display devices have advantages of thin profile, lightweight, and low power consumption, and are rapidly substituted for conventional cathode ray tubes (CRTs). 
         [0007]    The flat display device typically includes an array substrate where a thin film transistor (TFT) as a switching element turning on/off a pixel is formed in each pixel. 
         [0008]    For the purpose of explanation, an LCD most widely used among the flat display devices is illustrated in connection with the figures. The LCD has advantages of high performance in displaying moving images and high contrast ratio and is used for laptop computers, desktop monitors, TVs, or the like. 
         [0009]      FIG. 1  is a cross-sectional view illustrating an array substrate for an LCD according to the related art. 
         [0010]    Referring to  FIG. 1 , the array substrate  10  includes a plurality of gate lines on a substrate  1 , and a plurality of data lines  15  crossing the gate lines to define a plurality of pixel regions P. 
         [0011]    A TFT T is formed at a switching region near a crossing portion of the gate line and the data line  15 A common electrode  21  and a pixel electrode  25  are also formed at a display region and used in displaying an image. 
         [0012]    The TFT T includes a gate electrode  3 , a gate insulating layer  5 , an oxide semiconductor layer  7 , and source and drain electrodes  11  and  13 , respectively. 
         [0013]    An etch stopper  9  is formed between the source and drain electrodes  11  and  13  and the oxide semiconductor layer  7 , and includes semiconductor contact holes  9   a  exposing each of both side portions of the oxide semiconductor layer  7 . The source and drain electrodes  11  and  13  contact the respective side portions of the oxide semiconductor layer  7  through the respective semiconductor contact holes  9   a.    
         [0014]    A first passivation layer  17  is formed on the entire surface of the substrate  1  having the TFT T, and a second passivation layer  19  is formed on the first passivation layer. The common electrode  21  is formed on the second passivation layer  19  corresponding to the entire display region and is made of a transparent conductive material. 
         [0015]    A third passivation layer  23  is formed on the common electrode  21 . The first to third passivation layers  17 ,  19 , and  23  include a drain contact hole  13   a  exposing the drain electrode  13 . 
         [0016]    The pixel electrode  25  is formed on the third passivation layer  23  in each pixel region P and contacts the drain electrode  13  through the drain contact hole  13   a.    
         [0017]    The pixel electrode  25  includes a plurality of bar-shaped openings OP therein, and thus, produces a fringe electric field along with the common electrode  21  therebelow. 
         [0018]    The above-described array substrate  10  is used for a fringe field switching mode LCD. 
         [0019]    In the array substrate  10 , the oxide semiconductor layer  7  is reacted with hydrogen gas when depositing the first passivation layer  17 , and thus, hydrogen atoms act as a carrier in the oxide semiconductor layer  7 . This causes a problem in that the oxide semiconductor layer  7  then changes into a conductor. Further, the semiconductor layer  7  has an increase in propensity for oxygen vacancy generation due to ionic bonds, and this causes an increase of electron density. 
         [0020]    Particularly, when forming the source and drain electrodes  11  and  13 , oxygen concentration at a back channel region after dry-etching or wet-etching remarkably decreases. Thus, the oxide semiconductor layer  7  changes into a conductor, and caused increased leakage in the TFT. 
         [0021]    To solve the above problems, the etch stopper  9  is formed so that the oxide semiconductor layer  7  is not exposed to hydrogen gas during deposition of the first passivation layer  17 . However, this causes problems of more complicated design and processes with an associated increase of production costs. 
         [0022]    Further, defect frequency increases, and thus, production efficiency is reduced. 
         [0023]    Particularly, metal wire such as the source and drain electrodes is formed using low-resistance metal materials such as copper (Cu) in order to achieve display devices having large size and high resolution, and in this case, oxidation of metal wire is caused due to a high oxidation property of Cu and thus, leakage current occurs from the TFT. Therefore, reliability of the TFT element is reduced. 
       SUMMARY 
       [0024]    Accordingly, the present disclosure is directed to an array substrate and a method of fabricating the same that can improve reliability of an oxide semiconductor and adjust properties of the oxide semiconductor to minimize deterioration, obtain production simplification by reducing production processes, prevent leakage current, and increase reliability of a TFT element by preventing oxidation of metal wire made of a material such as copper. 
         [0025]    Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims as well as the appended drawings. 
         [0026]    To achieve these and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, an array substrate includes a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; source and drain electrodes on the oxide semiconductor layer; a silicide layer on the source and drain electrodes; and a first passivation layer on the source and drain electrodes. 
         [0027]    In another aspect, a method of an array substrate includes forming a gate electrode, a gate insulating layer, an oxide semiconductor layer, source and drain electrodes, on a substrate; injecting a gas mixture containing silane (SiH 4 ) onto the source and drain electrodes to form a silicide layer on the source and drain electrodes; performing a surface treatment for a back channel region of the oxide semiconductor layer between the source and drain electrodes having the silicide layer thereon; and forming a first passivation layer on the source and drain electrodes. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings: 
           [0029]      FIG. 1  is a cross-sectional view illustrating an array substrate for an LCD according to the related art; 
           [0030]      FIG. 2  is a cross-sectional view illustrating an array substrate for an LCD according to an exemplary embodiment of the present disclosure; 
           [0031]      FIGS. 3A to 3I  are cross-sectional views illustrating the array substrate for the LCD according to the exemplary embodiment of the present disclosure; 
           [0032]      FIGS. 4A and 4B  are graphs illustrating transfer properties of TFTs including oxide semiconductor layers according to a comparative example and the exemplary embodiment of the present disclosure, respectively; and 
           [0033]      FIG. 5A  illustrates an occurrence of oxidation of metal wires using Cu not having silicide layer thereon; and 
           [0034]      FIG. 5B , illustrates no occurrence of oxidation of metal wires using Cu and having the silicide layer thereon according to the exemplary embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0035]    Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. 
         [0036]      FIG. 2  is a cross-sectional view illustrating an array substrate for an LCD according to an embodiment of the present disclosure. 
         [0037]    Referring to  FIG. 2 , the array substrate  100  may include a plurality of gate lines (not shown) spaced apart from each other on a substrate  101 , and a plurality of data lines  115  crossing the plurality of gate lines to define respective pixel regions P. 
         [0038]    A TFT T may be formed at a switching region TrA near a crossing portion of the gate line and the data line  115 , and a pixel electrode  125  may be formed at a display region to displaying an image. 
         [0039]    A gate electrode  103  may be formed at the switching region TrA, and a gate insulating layer  105  may be formed on the entire surface of the substrate  101  having the gate electrode  103 . 
         [0040]    An oxide semiconductor layer  107  may be formed on the gate insulating layer  105  over the gate electrode  103 . Source and drain electrodes  111  and  113 , respectively, may be formed on the oxide semiconductor layer  107  and spaced apart from each other. 
         [0041]    The gate electrode  103 , the gate insulating layer  105 , the oxide semiconductor layer  107 , and the source and drain electrodes  111  and  113  form the TFT T at the switching region TrA. 
         [0042]    A TFT T using an oxide semiconductor has field-effect mobility of several times to hundreds of times greater than that of a TFT using amorphous silicon. 
         [0043]    For example, when an oxide semiconductor material containing at least one of zinc oxide, tin oxide, Ga—In—Zn oxide, and In—Sn oxide, which each have amorphous structure, or doped with at least one of Al, Ni, Cu, Ta, Mo, Hf, and Ti, can have field-effect mobility of at least 20 times greater than that of amorphous silicon. 
         [0044]    Further, the oxide semiconductor layer  107  can have high mobility even though deposited at low temperature, and thus, reliability can be increased. 
         [0045]    It is preferred, but not limited, that at least one of the gate electrode  103 , the gate line, the source and drain electrodes  111  and  113 , and the data line  115  have a multiple-layered structure, for example, double-layered structure that includes a lower layer made of one of Mo, Ti, and MoTi, and a upper layer made of low-resistance metal material such as Cu on the lower layer. 
         [0046]    In this case, Mo, Ti, and MoTi have good adhesion onto the substrate  101 , e.g., made of glass material, and function to improve coupling of the Cu layer to the substrate  101 . 
         [0047]    Further, using a multiple-layered structure with the Cu layer allows a width of signal wire to be reduced, and an increase of wire resistance can be prevented even though a length of the signal wire increases. 
         [0048]    In this regard, to achieve an LCD device having a large size and high resolution, reduction of the width and an increase in length of the signal wire are required, which causes an increase of wire resistance. Accordingly, current or voltage supplied to the pixel region P is not uniform, and display quality is degraded. 
         [0049]    Therefore, reducing wire resistance is needed, and to do this, a low-resistance metal material such as Cu, Ag, or the like can be used to form the metal wire in the display device. 
         [0050]    Particularly, processing to pattern Cu is easier than that of patterning Ag. Also, specific resistance of Cu is about 30% or less of that of Al. For example, Cu has specific resistance of about 2.1 to about 2.3 μΩcm and Al has specific resistance of about 3.1 μΩcm. Also, Cu has a better tolerance to hillock than Al. 
         [0051]    Accordingly, because the gate electrode  103 , the gate line, the source and drain electrodes  111  and  113 , and the data line  115  are formed using Cu of low resistance, even though the display device has a large size and high resolution, signal delay can be prevented. Thus, operational problems can be prevented due to voltage drop, or non-uniform current or voltage supplied to the pixel region P causing a degradation of display quality. 
         [0052]    Further, assuming that wire resistance is the same as that of the related art, a width of the patterned wire can be much reduced, and aperture ratio can be increased. 
         [0053]    To address this problem in the present disclosure, the TFT T may include a silicide layer  200  formed on the source and drain electrodes  111  and  113 . 
         [0054]    Accordingly, even though the TFT T includes the oxide semiconductor layer  107  and the metal wires contains Cu, degradation of operational properties of the TFT T can be avoided and an etch stopper ( 9  of  FIG. 1 ) can be eliminated. Accordingly, the production process can be simplified, and production efficiency can be improved. 
         [0055]    Further, oxidation of the metal wire using Cu can be prevented, and thus, current leakage and reduction of reliability due to the current leakage can also be prevented. 
         [0056]    Referring to  FIG. 1 , a first passivation layer  117  may be formed on the entire surface of the substrate  101  having the TFT T, and may be made of an inorganic insulating material, for example, silicon oxide (SiO 2 ). A second passivation layer  119  may be formed on the first passivation layer  117 , and may be made of an organic insulating material, for example, photo acryl. The second passivation layer  119  may have a flat surface. 
         [0057]    A common electrode  121  may be formed on the second passivation layer  119  corresponding to the entire display region. A part of the common electrode  121  corresponding to each switching region TrA may be removed, and thus, parasitic capacitance due to overlapping the common electrode  121  and the source and drain electrodes  111  and  113  can be reduced. 
         [0058]    A third passivation layer  123  may be formed on the common electrode  121 . The first to third passivation layers  117 ,  119 , and  123  may include drain contact holes  113   a,    113   b,  and  113   c,  respectively, exposing the drain electrode  113 . 
         [0059]    A pixel electrode  125  may be formed on the third passivation layer  123  in each pixel region P and contact the drain electrode  113  through the drain contact holes  113   a,    113   b,  and  113   c.    
         [0060]    The pixel electrode  125  in each pixel region P may include a plurality of bar-shaped openings OP. According to this configuration of the pixel electrode  125 , the array substrate  100  may be used for a fringe field switching (FFS) mode LCD. 
         [0061]    As described above, the array substrate  100  may include the TFT T using the oxide semiconductor layer  107 , and the metal wires using Cu of low resistance, and thus, the etch stopper of the related art can be eliminated, and degradation of the TFT T can be avoided. 
         [0062]    Accordingly, production processes can be simplified and production efficiency can be improved. 
         [0063]    Further, oxidation of the metal wire using Cu can be prevented, and reduction of reliability due to current leakage can also be prevented. 
         [0064]    In this exemplary embodiment, instead of forming the related art etch stopper, a surface treatment on the back channel region of the oxide semiconductor layer  107  using oxygen may be performed before depositing the first passivation layer  117 . Accordingly, oxygen is supplemented at the surface of the back channel where oxygen was reduced by the prior art processes. Also, converting the surface of the oxide semiconductor layer  107  into an insulating material using an oxygen surplus can minimize current leakage at the back channel region. Accordingly, degradation of property of the TFT T can be prevented. 
         [0065]    The surface treatment may be conducted using an oxygen (O 2 ) treatment, ozone (O 3 ) treatment, a thermal treatment under an oxygen atmosphere, or the like. 
         [0066]    Cu used for the metal wires such as the source and drain electrodes  111  and  113  and the data line  115  is easily oxidized. Accordingly, it is difficult to conduct the surface treatment of the oxide semiconductor layer  107 . 
         [0067]    Here, the silicide layer  200  functions to prevent the source and drain electrode  111  and  113  from being exposed to oxygen (O 2 ) or ozone (O 3 ) in the surface treatment for the oxide semiconductor layer  107 . Accordingly, current leakage due to the oxidation of the metal wire can be prevented, and reliability can be improved. 
         [0068]    Further, the silicide layer  200  functions as a diffusion barrier layer for Cu used in the source and drain electrodes  111  and  113 . 
         [0000]    In other words, Cu ions of the source and drain electrodes  111  and  113  diffuse to the first passivation layer  117  made of oxide silicon (SiO 2 ), and an insulation property of the first passivation layer  117  is reduced. However, in the embodiment, the silicide layer  200  is formed on the source and drain electrodes  111  and  113 , and the diffusion of the Cu ions can be prevented. 
         [0069]    Also, oxidation can be prevented by the silicide layer  200 . 
         [0070]    A method of fabricating the array substrate  100  for the LCD of the embodiment is explained as follows. 
         [0071]      FIGS. 3A to 3I  are cross-sectional views illustrating the array substrate for the LCD according to an embodiment of the present disclosure. 
         [0072]    Referring to  FIG. 3A , a gate electrode  103 , a gate line (not shown), a gate insulating layer  105 , an oxide semiconductor layer  107 , source and drain electrodes  111  and  113 , and a data line  115  may be formed on a transparent substrate  101 . 
         [0073]    The gate electrode  103 , the gate insulating layer  105 , the oxide semiconductor layer  107 , and the source and drain electrodes  111  and  113  form a TFT Tr in a switching region TrA. 
         [0074]    The gate electrode  103 , the gate line, the source and drain electrodes  111  and  113 , and the data line  115  may have a double-layered structure that includes a first layer of Mo, Ti, or MoTi, and a second layer, on the first layer, of Cu having low resistance. 
         [0075]    The first layer functions to improve adhesion between the substrate  101  and the second layer of Cu. 
         [0076]    The gate insulating layer  105  may be formed, for example, in a PECVD (plasma enhanced chemical vapor deposition) method, and be made of an inorganic insulating material, for example, silicon oxide (SiO 2 ) or silicon nitride (SiNx). 
         [0077]    The oxide semiconductor layer  107  may be made of one of zinc oxide, tin oxide, Ga—In—Zn oxide, and In—Sn oxide, which each have amorphous structure, such the one doped with one of Al, Ni, Cu, Ta, Mo, Hf, and Ti using a sputtering method. The oxide semiconductor layer  107  may be patterned using a mask process so that the oxide semiconductor layer  107  having an island shape is formed corresponding to the gate electrode  103 . 
         [0078]    Referring to  FIG. 3B , a gas mixture containing silane (SiH 4 ) may be injected onto the source and drain electrodes  111  and  113 . 
         [0079]    The gas mixture may be a mixture of silane (SiH 4 ) and nitrogen (N 2 ), or a mixture of silane (SiH 4 ), nitrogen (N 2 ), and one of helium (He) and argon (Ar). 
         [0080]    When the gas mixture containing silane and nitrogen is injected onto the source and drain electrodes  111  and  113 , silicon of silane is diffused into Cu of the source and drain electrodes  111  and  113  so that a silicide layer  200  is formed at the surfaces of the source and drain electrodes  111  and  113 . 
         [0081]    The silicide layer  200  functions to prevent the source and drain electrodes  111  and  113  using Cu from being oxidized during the surface treatment process for the oxide semiconductor layer  107  or when depositing a first passivation layer  117  made of silicon oxide (SiO 2 ). 
         [0082]    Further, the silicide layer  200  functions to prevent Cu ions from being diffused to the first passivation layer  117  of silicon oxide (SiO 2 ). 
         [0083]    By using the silicide layer  200 , an etch stopper can be eliminated without degradation of the TFT T, and thus, production processes can be simplified and production efficiency can be improved. 
         [0084]    Further, because the oxidation of the metal wire using Cu can be prevented, current leakage in the TFT can be prevented. 
         [0085]    Then, referring to  FIG. 3C , a surface treatment may be conducted for a back channel region of the oxide semiconductor layer  107  exposed between the source and drain electrodes  111  and  113 . The surface treatment may be an oxygen plasma treatment, an ozone treatment, or a thermal treatment in an oxygen rich atmosphere. 
         [0086]    For an example, the back channel region of the oxide semiconductor layer  107  may be surface-treated using the oxygen plasma treatment, and this treatment may be conducted under at a power of about 10 W to about 2000 W, and a oxygen flow rate of about 10 sccm to about 100 sccm. 
         [0087]    In another example, the back channel region may be surface-treated using an ozone treatment through UV irradiation in an ozone atmosphere. In yet another example, the back channel region may be surface-treated using heat of about 100 degrees Celsius to about 300 degrees Celsius. 
         [0088]    Through the surface treatment as described above, the problem that the oxide semiconductor layer  107  is reacted with hydrogen gas when depositing the first passivation layer  117  and changed into a conductor can be prevented. 
         [0089]    Further, the problem that the semiconductor layer  107  is more susceptible to oxygen vacancy generation due to ionic bonds increasing electron density can be prevented. Further, the problem that when forming the source and drain electrodes  111  and  113 , oxygen concentration at the back channel region after dry-etching or wet-etching remarkably decreases, and thus the oxide semiconductor layer  107  changes into a conductor can be prevented. 
         [0090]    Accordingly, deterioration of current leakage of the oxide semiconductor layer  107  can be prevented. 
         [0091]    Particularly, even though the source and drain electrodes  111  and  113  use Cu of low resistance, since the silicide layer  200  is formed on the source and drain electrodes  111  and  113 , the source and drain electrodes  111  and  113  are not affected by the surface treatment of the oxide semiconductor layer  107 . Thus, oxidation of the source and drain electrodes  111  and  113  can be prevented. 
         [0092]    Referring to  FIG. 3D , the first passivation layer  117  may be formed on the substrate  101  having the surface-treated oxide semiconductor layer  107  by ionizing a gas mixture containing silane (SiH 4 ) and nitrous oxide (N 2 O) and depositing the ionized gas, using a PECVD. Then, referring to  FIG. 3E , the first passivation layer  117  may be patterned in a mask process to form a first drain contact hole  113   a.    
         [0093]    The process of forming the silicide layer  200  in  FIG. 3B , the process of surface-treating the oxide semiconductor layer  107  in  FIG. 3C , and the process of forming the passivation layer in  FIGS. 3D and 3E  may be performed continuously in the same chamber. In this case, in the process of forming the silicide layer  200 , the gas mixture containing silane is injected to grow the silicide layer  200  with the power of the chamber off. 
         [0094]    In other words, the gas mixture containing silane is injected onto the source and drain electrodes  111  and  113  in a state that the gas mixture is not ionized. 
         [0095]    Referring to  FIG. 3F , an organic material, for example, photo acryl may be deposited on the first passivation layer  117  to form a second passivation layer  119 , and the second passivation layer  119  may be patterned using a mask process to form a second drain contact hole  113   b  corresponding to the first drain contact hole  113   a  and exposing the drain electrode  113 . 
         [0096]    Alternatively, the first and second drain contact holes  113   a  and  113   b , respectively, may be simultaneously formed in a method of forming the first and second passivation layers  117  and  119 , and then patterning the first and second passivation layers  117  and  119 . In other words, the first and second drain contact holes  113   a  and  113   b  can be formed in the same mask process. 
         [0097]    Referring to  FIG. 3G , a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) may be deposited on the second passivation layer  119 , and patterned using a mask process to form a common electrode  121 . The common electrode  121  may be formed on the entire display region, and have an opening corresponding to at least part of each switching region TrA. 
         [0098]    Referring to  FIG. 3H , an inorganic insulating material, for example, silicon oxide or silicon nitride may be deposited on the common electrode  121  to form a third passivation layer  123 . Then, the third passivation layer  123  may be patterned in a mask process to form a third drain contact hole  113   c,  corresponding to the first and second drain contact holes  113   a  and  113   b,  and exposing the drain electrode  113 . 
         [0099]    Referring to  FIG. 3I , a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) may be deposited on the third passivation layer  123 , and patterned using a mask process to form a pixel electrode  125  in each pixel region P. The pixel electrode  125  may contact the drain electrode  113  through the first to third drain contact holes  113   a  to  113   c,  and includes a plurality of openings OP in each pixel region P. 
         [0100]    Through the above-described processes, the array substrate  100  may be fabricated. This array substrate  100  may be used as an array substrate for a FFS mode LCD. 
         [0101]    Alternatively, a pixel electrode having a plate shape may be formed in each pixel region on an array substrate, a common electrode may be formed on a substrate opposing to the array substrate, and the array substrate and the opposing substrate are attached to form a twisted nematic (TN) mode LCD, electronic controlled birefringence (ECB) mode LCD, or vertical alignment (VA) mode LCD. 
         [0102]    Alternatively, a bar-shaped pixel electrode and a bar-shaped common electrode may be alternated in each pixel region at an array substrate, and this array substrate may be an array substrate used for an in plane switching (IPS) mode LCD. 
         [0103]    Also, the array substrate of the embodiment can be applied as an array substrate for other flat display devices such as an OLED device. 
         [0104]    As described above, in the array substrate  100 , the silicide layer  200  may be formed on the source and drain electrodes  111  and  113 , and the surface treatment may be performed for the back channel region of the oxide semiconductor layer  107 . Accordingly, even though the TFT T may include the oxide semiconductor layer  107  and the metal wires use Cu layer of low resistance, the etch stopper can be eliminated and degradation of the TFT T can be prevented. 
         [0105]      FIGS. 4A and 4B  are graphs illustrating transfer properties of TFTs including oxide semiconductor layers according to a comparative example and the embodiment of the present disclosure, respectively.  FIGS. 4A and 4B  each shows a relationship of drain current to gate voltage with a drain voltage kept at 0.1V and 10V. 
         [0106]    In the comparative example, the etch stopper is eliminated from the related art array substrate through process simplification. Accordingly, referring to  FIG. 4A , the voltage-to-current transfer curve shows that the comparative TFT does not have properties of a switching element, but is a conductor. 
         [0107]    However, in the disclosed embodiment, the silicide layer  200  may be formed on the source and drain electrodes  111  and  113 , and the surface treatment may be conducted for the back channel region of the oxide semiconductor layer  107 . In this case, referring to  FIG. 4B , the TFT T of the disclosed embodiment has properties of a switching element. 
         [0108]    In other words, in the disclosed embodiment, since the silicide layer  200  may be formed on the source and drain electrodes  111  and  113 , and the surface treatment may be conducted for the back channel region of the oxide semiconductor layer  107 , production process can be simplified, and degradation of the TFT T can be prevented. Further, oxidation of the metal wires using Cu can be prevented, and thus, reduction of reliability due to current leakage can be prevented. 
         [0109]    In other words, in case that the silicide layer  200  is not formed on the source and drain electrodes  111  and  113 , the source and drain electrodes  111  and  113  are oxidized by the surface treatment for the oxide semiconductor layer  107 . This is shown in  FIG. 5A , illustrating an occurrence of oxidation of metal wires using Cu not having silicide layer thereon. When the oxidation occurs, a reduction of reliability is caused by leakage current. 
         [0110]    However, in the disclosed embodiment, because of the silicide layer  200 , the oxidation of the source and drain electrodes  111  and  113  can be prevented. This is shown in  FIG. 5B , illustrating no occurrence of oxidation of metal wires using Cu having the silicide layer thereon. 
         [0111]    As described above, when the silicide layer  200  is formed on the source and drain electrodes  111  and  113 , the oxidation of the source and drain electrodes  111  and  113  using Cu can be prevented. Therefore, reduction of reliability due to current leakage can be prevented. 
         [0112]    It will be apparent to those skilled in the art that various modifications and variations can be made in a display device of the present disclosure without departing from the sprit or scope of the disclosure. Thus, it is intended that the present disclosure covers the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.