Abstract:
Presented herein are system(s), method(s), and apparatus for an audio decoding accelerator. In one embodiment, there is presented an audio decoder for decoding audio data. The audio decoder comprises a controller and a computation engine. The controller receives the audio data, and provides parameters, where the parameters are associated with the audio data. The computation engine calculates at least one of a plurality of predetermined functions for said parameters.

Description:
RELATED APPLICATIONS  
       [0001]     [Not Applicable] 
       FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     [Not Applicable] 
       MICROFICHE/COPYRIGHT REFERENCE  
       [0003]     [Not Applicable] 
       BACKGROUND OF THE INVENTION  
       [0004]     The encoding and decoding of audio data involves the calculation of complex and computationally intense mathematical or logical functions. For example, the MPEG-1, Part 3 standard utilizes frequency transformation, such as the modified discrete cosine transformation to encode audio data. During decoding, the inverse functions are applied, which are also computationally intense.  
         [0005]     Real-time operation is desirable in many audio data applications, wherein the audio data is decoded at approximately, or faster than the audio data is played. Additionally, many audio data applications can include more than one encoded audio data signal. For example, surround sound can include several audio data signals. The foregoing dramatically increase the computational requirements of the audio encoding and decoding hardware.  
         [0006]     An audio decoder usually includes a processor that executes firmware. The foregoing is desired for handling other aspects of the audio encoding and decoding in addition to the function computations. However, the processor may not be optimized for performing the specific function computations.  
         [0007]     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     Presented herein are system(s), method(s), and apparatus for an audio decoding accelerator.  
         [0009]     In one embodiment, there is presented an audio decoder for decoding audio data. The audio decoder comprises a controller and a computation engine. The controller receives the audio data, and provides parameters, where the parameters are associated with the audio data. The computation engine calculates at least one of a plurality of predetermined functions for said parameters.  
         [0010]     In another embodiment, there is presented a method for decoding audio data. The method comprises receiving the audio data; writing parameters associated with the audio data to a memory; and calculating at least one of a plurality of predetermined functions for said parameters.  
         [0011]     In another embodiment, there is presented an audio decoder for decoding audio data. The audio decoder comprises a controller and a computation engine. The controller is adapted to receive the audio data, and provide parameters, where the parameters are associated with the audio data. The computation engine is connected to the controller, and adapted to calculate at least one of a plurality of predetermined functions for said parameters.  
         [0012]     These and other advantages, aspects and novel features of the present invention, as well as details of illustrative aspects thereof, will be more fully understood from the following description and drawings.  
     
    
     BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS  
       [0013]      FIG. 1  is a block diagram describing an exemplary audio decoder in accordance with an embodiment of the present invention;  
         [0014]      FIG. 2  is a block diagram describing an exemplary audio encoder in accordance with an embodiment of the present invention;  
         [0015]      FIG. 3  is a block diagram describing the encoding of audio data in accordance with the MPEG-1, Part3 standard;  
         [0016]      FIG. 4  is a block diagram describing the decoding of audio data in accordance with the MPEG-1, Part 3 standard;  
         [0017]      FIG. 5  is a block diagram describing an exemplary audio encoder in accordance with an embodiment of the present invention; and  
         [0018]      FIG. 6  is a block diagram describing an exemplary audio decoder in accordance with an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     Referring now to  FIG. 1 , there is illustrated a block diagram of an exemplary audio decoder  100  in accordance with an embodiment of the present invention. The audio decoder comprises a controller  105  for receiving the audio data and providing parameters, and a computation engine  110  for calculating at least one of a number of predetermined functions for the parameters.  
         [0020]     The audio decoder  100  receives encoded audio data at the controller  105 . To decode the audio data, a number of mathematical or logic functions are performed on portions of the audio data. The process of encoding audio data can include application of mathematical or logic functions. These functions can include, for example, the inverse modified discrete cosine transformation (IMDCT), or the inverse fast Fourier transformation (IFFT), to name a couple. Accordingly, the encoded audio data includes the results of the foregoing functions.  
         [0021]     Inverse functions are applied to decode the audio data. The inverse functions can be computationally intense. Accordingly, controller  105  provides the portions of the encoded audio data, parameters upon which the inverse functions (which are also functions) are to be applied. The computation engine  110  applies the functions to the parameters.  
         [0022]     Referring now to  FIG. 2 , there is illustrated a block diagram of an exemplary audio encoder  200  in accordance with an embodiment of the present invention. The audio encoder comprises a controller  205  for receiving the audio data and providing parameters, and a computation engine  210  for calculating at least one of a number of predetermined functions for the parameters.  
         [0023]     The audio encoder  200  receives audio data. The process of encoding audio data can include application of mathematical or logic functions. These functions can include, for example, the modified discrete cosine transformation, or the fast Fourier transformation, to name a couple.  
         [0024]     The functions can be computationally intense. Accordingly, controller  205  provides the portions of the audio data, parameters upon which the functions are to be applied. The computation engine  210  applies the functions to the parameters.  
         [0025]     Aspects of the present invention can be used with a variety of audio encoding standards. By way of example, embodiments of the present invention will now be described in the context of the MPEG-1, Part 3 standard. Discussion will now turn to a brief description of the MPEG-1, Part 3 standard, followed by exemplary embodiments of the present invention in the context of the MPEG-1, Part 3 standard.  
         [0000]     MPEG-1 Part 3  
         [0026]      FIG. 3  illustrates a block diagram describing the encoding of an audio signal  301 , in accordance with the MPEG-1, Layer 3 standard, MPEG-4 AAC or Dolby Digital AC-3 decoder. The audio signal  301  is captured and used for further audio post processing depending upon the speed. The samples of the audio signal  301  are then grouped into frames  303  (F 0  . . . F n ) of 1024 samples such as, for example, (F x (0) . . . F x (1023))  
         [0027]     The frames  303  (F 0  . . . F n ) are then grouped into windows  305  (W 0  . . . W n ) each one of which comprises 2048 samples or two frames such as, for example, (W x (0) . . . W x (2047)) comprising frames (F x (0) . . . F x (1023)) and (F x+1 (0) . . . F x+1 (1023)). However, each window  305  W x  has a 50% overlap with the previous window  305  W x−1 . Accordingly, the first 1024 samples of a window  305  W x  are the same as the last 1024 samples of the previous window  105  W x−1 . For example, W 0 =(W 0 (0) . . . W 0 (2047))=(F 0 (0) . . . F 0 (1023)) and (F 1 (0) . . . F 1 (1023)), and W 1 =(W 1 (0) . . . W 1 (2047))=(F 1 (0) . . . F 1 (1023)) and (F 2 (0) . . . F 2 (1023)). Hence, in the example, W 0  and W 1  contain frames (F 1 (0) . . . F 1 (1023)).  
         [0028]     A window function w(t) is then applied to each window  305  (W 0  . . . W n ), resulting in sets (wW 0  . . . wW n ) of 2048 windowed samples  307  such as, for example, (wW x (0) . . . wW x (2047)). A Modified Discrete Cosine or Fourier Transform (MDCT/FT) is then applied to each set (wW 0  . . . wW n ) of windowed samples  307  (wW x (0) . . . wW x (2047)), resulting sets (MDCT 0  . . . MDCT n ) of 1024 frequency coefficients  309  such as, for example, (MDCT x (0) . . . MDCT x (1023)).  
         [0029]     The sets of frequency coefficients  309  (MDCT 0  . . . MDCT n ) are then quantized and coded for transmission, forming an audio elementary stream (AES). The AES can be multiplexed with other AESs. The multiplexed signal, known as the Audio Transport Stream (Audio TS) can then be stored and/or transported for playback on a playback device. The playback device can either be at a local or remote located from the encoder. Where the playback device is remotely located, the multiplexed signal is transported over a communication medium such as, for example, the Internet. The multiplexed signal can also be transported to a remote playback device using a storage medium such as, for example, a compact disk.  
         [0030]     During playback, the Audio TS is de-multiplexed, resulting in the constituent AES signals. The constituent AES signals are then decoded, yielding the audio signal. During playback the speed of the signal may be decreased to produce the original audio at a slower speed.  
         [0031]      FIG. 4  is a block diagram describing the decoding of an encoded audio signal. The encoded audio signal comprises sets (MDCT 0  . . . MDCT n ) of 1024 frequency coefficients  409 . An inverse modified discrete cosine transform (IMDCT) is applied to each set (MDCT 0  . . . MDCT n ) of 1024 frequency coefficients  409 . The result of applying the IMDCT is the sets (wW 0  . . . wW n ) of windowed samples  407  (wW x (0) . . . wW x (2047) equivalent to sets (wW 0  . . . wW n ) of windowed samples  407  (wW x (0) . . . wW x (2047)) of  FIG. 3 .  
         [0032]     An inverse window function w I (t) is then applied to each set (wW 0  . . . wW n ) of 2048 windowed samples  407 , resulting in windows  405  (W 0  . . . W n ) each one of which comprises 2048 samples. Each window  405  (W 0  . . . W n ) comprises 2048 samples from two frames such as, for example, (W x (0) . . . W x (2047)) comprising frames (F x (0) . . . F x (1023)) and (F x+1 (0) . . . F x+1  (1023)) as illustrated in  FIG. 3 . The frames  403  (F 0  . . . F n ) of 1024 samples such as, for example, (F x (0) . . . F x (1023)), are then extracted from the windows  405  (W 0  . . . W n ).  
         [0033]     A window function WF is then applied to frames  402  (FR 0  . . . FR m ) to “smooth out” the samples and ensure that the resulting signal does not have any artifacts that may result from repeating each frame. The window function results in the windowed frames  404  (WF 0  . . . WF L ) of 1024 samples. The window function WF can be one of many widely known and used window functions, or can be designed to accommodate the design requirements of the system. The windowed frames  404  (WF 0  . . . WF L ) of 1024 samples are then run through a digital-to-analog converter (DAC) to get an analog signal  401 .  
         [0034]     Referring now to  FIG. 5 , there is illustrated a block diagram describing an exemplary audio encoder  500  in accordance with an embodiment of the present invention. The audio encoder  500  will be described with reference to  FIG. 3 . The audio encoder  500  comprises a controller  505 , a computation engine  510 , and memory  515 .  
         [0035]     The controller  505  is adapted to receive the audio data  301 . The audio data  301  comprises samples from an analog signal. As noted above, pursuant to the MPEG-1, Part 3 standard, a wide variety of mathematical and logical functions are performed on the audio data  301  to encode the audio data  301 . These functions can include application of a windowing function, the modified discrete cosine transformation, or the fast Fourier transformation.  
         [0036]     The computation engine  510  connected to the controller, calculates the appropriate one of the functions on the audio data  301 . The computation engine  510  can be a hardware accelerator that is specifically designed for performing the calculations of the mathematical or logical function. According to certain aspects of the present invention, the controller  505  can provide inputs to the computation engine  510  that select the particular function to be performed.  
         [0037]     In certain embodiments, a memory  515  connected to the controller can store the audio data  201 . The controller  505  can provide pointers to addresses in the memory  515  storing the audio data  301  upon which a particular function is to be performed. Additionally, the computation engine  510  can write the results functions to the memory  515 .  
         [0038]     Referring now to  FIG. 6 , there is illustrated a block diagram describing an exemplary audio decoder  600  in accordance with an embodiment of the present invention. The audio decoder  600  will be described with reference to  FIG. 4 . The audio decoder  600  comprises a controller  605 , a computation engine  610 , and memory  615 .  
         [0039]     The controller  605  receives encoded audio data. The encoded audio data comprises sets (MDCT 0  . . . MDCT n ) of 1024 frequency coefficients  409 . The controller  605  can provide the frequency coefficients  409 , as parameters, for application of the inverse modified cosine transformation or inverse fast Fourier transformation.  
         [0040]     The computation engine  610  connected to the controller, calculates the appropriate one of the functions on the parameters. The computation engine  610  can be a hardware accelerator that is specifically designed for performing the calculations of the mathematical or logical function. According to certain aspects of the present invention, the controller  605  can provide inputs to the computation engine  610  that select the particular function to be performed.  
         [0041]     In certain embodiments, a memory  615  connected to the controller can store the frequency coefficients  409 . The controller  605  can provide pointers to addresses in the memory  615  storing the frequency coefficients  409  upon which a particular function is to be performed. Additionally, the computation engine  610  can write the results functions to the memory  615 .  
         [0042]     In certain embodiments of the present invention, the controller  605  and computation engine  610  can work in parallel. The controller  605  can be preparing the next set of data for the computation engine  610 , while computation engine  610  is busy in decoding the current data. With the foregoing parallelism, decoder speed can be increased. Additionally, the foregoing aids the decoding of different standard streams, if scheduling is done on a frame by frame basis. Additionally, in certain embodiments of the present invention, two different audio formats are simultaneous as the computation engines work in parallel. The controller can operate on audio data in a first format, while the controller can operate on audio data in a second format.  
         [0043]     The degree of integration of the system will primarily be determined by the speed and cost considerations. Because of the sophisticated nature of modern processor, it is possible to utilize a commercially available processor, which may be implemented external to an ASIC implementation. If the processor is available as an ASIC core or logic block, then the commercially available processor can be implemented as part of an ASIC device wherein certain functions can be implemented in firmware. In one embodiment, the foregoing can be integrated into an integrated circuit. Additionally, the functions can be implemented as hardware accelerator units controlled by the processor.  
         [0044]     While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.