Abstract:
A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to clock compensation, and more particularly to compensating a local clock of a device that receives data from a host for frequency offset when transmitting data from the device to the host.  
         BACKGROUND OF THE INVENTION  
         [0002]    A host and a device typically transmit and receive data to and from each other. For example in a personal computer environment, a disk drive controller (host) is often connected to a disk drive (device). The host is typically implemented using a relatively accurate host clock generator. The accuracy is often required to meet the specifications of a host processor and/or other host components.  
           [0003]    The host and the device may be connected using a Serial Advanced Technology Attachment (SATA) standard, although other protocols may be used. The SATA standard is a simplified packet switching network between a host and a device. SATA typically employs balanced voltage (differential) amplifiers and two pairs of wires to connect transmitters and receivers of the host and the device in a manner similar to 100BASE-TX Ethernet. The SATA standard is disclosed in “Serial ATA: High Speed Serialized AT Attachment”, Serial ATA Organization, Revision 1.0, Aug. 29, 2001, and its Supplements and Errata, which are hereby incorporated by reference.  
           [0004]    To reduce costs, the device may be implemented using a less accurate clock. For example, the device may include a resonator, which may be crystal or ceramic based. The resonator generates a reference clock for a frequency synthesizer of a phase-locked loop (PLL), which generates a higher-frequency clock. Ceramic resonators are cheaper than crystal resonators but not as accurate. The resonator can be an individual component. Alternately, the resonator can be implemented inside a clock chip (such as crystal voltage controlled oscillator (VCO)).  
           [0005]    When the device is implemented using lower accuracy clock generators, the transmitted data from the device to the host may not meet data transmission standards, such as SATA or other standards. As a result, the device must be implemented with a more expensive local clock generator with improved accuracy, which increases the cost of the device.  
         SUMMARY OF THE INVENTION  
         [0006]    A device according to the present invention communicates with a host and includes a transmitter, a receiver and a clock generator that generates a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset.  
           [0007]    In other features, the frequency compensator includes a low pass filter that communicates with the frequency offset circuit. The frequency compensator includes an accumulator that communicates with the low pass filter and that generates a phase offset. The frequency compensator includes an interpolator that receives a local phase from the clock generator and the phase offset from the accumulator. The interpolator outputs a compensated clock signal to the transmitter.  
           [0008]    In yet other features, the clock generator includes a phase-locked loop circuit that includes a reference frequency generator, a phase detector that communicates with the reference frequency generator, a low pass filter that communicates with the phase detector, and a voltage controlled oscillator that communicates with the low pass filter. The reference frequency generator includes at least one of a crystal resonator and a ceramic resonator.  
           [0009]    In still other features, a 1/N divider has an input that communicates with the voltage controlled oscillator and an output that communicates with the phase detector. A 1/M divider has an input that communicates with the reference frequency generator and an output that communicates with the phase detector. N and M are adjusted to create a spread spectrum modulation signal for spread spectrum operation. An interpolator communicates with an output of the voltage controlled oscillator and an input of the 1/N divider for smoothing.  
           [0010]    In still other features, a summer has a first input that communicates with an output of the low pass filter and an output that communicates with an input of the accumulator. A frequency modulation generator communicates with a second input of the summer and selectively generates a spread spectrum modulation signal when spread spectrum operation is enabled and a constant signal when spread spectrum operation is disabled.  
           [0011]    In other features, the host and the device communicate using a serial ATA standard. The host can be a disk controller and the device can be a disk drive.  
           [0012]    Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:  
         [0014]    [0014]FIG. 1 is a functional block diagram illustrating a host connected to a device;  
         [0015]    [0015]FIG. 2 is a functional block diagram illustrating a frequency offset compensator according to the present invention for a transmitter of the device of FIG. 1;  
         [0016]    [0016]FIG. 3 is a more detailed functional block diagram of a first embodiment of the frequency offset compensator for the transmitter of the device;  
         [0017]    [0017]FIG. 4 is a functional block diagram of a second embodiment of a frequency offset compensator for the transmitter of the device and a triangular wave generator for optional spread spectrum operation;  
         [0018]    [0018]FIG. 5 is an exemplary implementation of the frequency offset compensator of FIGS. 3 and 4;  
         [0019]    [0019]FIG. 6 illustrates clock timing for an exemplary interpolator shown in FIGS.  3 - 5 ;  
         [0020]    [0020]FIG. 7 illustrates the host and the device of FIG. 1 with a connection based on the SATA standard;  
         [0021]    [0021]FIG. 8 illustrates a disk controller and a disk drive with a connection based on the SATA standard;  
         [0022]    [0022]FIGS. 9 and 10 illustrate phase-locked loop (PLL) circuits according to the prior art; and  
         [0023]    [0023]FIG. 11 illustrates a closed loop PLL for spread spectrum operation according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements.  
         [0025]    Referring now to FIG. 1, a host  10  includes a receiver  12  and a transmitter  14 . A device  20  includes a receiver  22  and a transmitter  24 . The transmitter  14  of the host  10  transmits host data  26  to the receiver  22  of the device  20 . The transmitter  24  of the device  20  transmits device data  28  to the receiver  12  of the host  10 .  
         [0026]    Referring now to FIG. 2, the device  20  includes a frequency offset compensator generally identified at  38 . A local clock generator  40  generates a local clock frequency f local . The device  20  also includes a clock data recovery circuit  44  that determines a clock frequency f data  of the host  10  from data transmitted by the host  10 . A frequency offset calculator  48  compares the host frequency f data  to the local frequency f local  and generates a frequency offset f offset . The f offset  is used to compensate f local . For example, f offset  and f local  are summed by a summer  50 . The compensated frequency is used to clock the transmitter  24  of the device  20 . By compensating the frequency of the transmitter  24  of the device  20 , a less expensive local clock generator can be used to reduce the cost of the device  20 .  
         [0027]    Referring now to FIG. 3, the host data  26  is received by the receiver  22  of the device  20 . A clock data recovery and frequency offset calculator  60  communicates with the receiver  22 . A phase-locked loop (PLL)  64  generates a local phase p local , which is output to the clock data recovery and frequency offset calculator  60 . The clock data recovery and frequency offset calculator  60  outputs a receiver clock to the receiver  22  and a frequency offset f offset  to a low pass filter (LPF)  66 , which has an output that is connected to an accumulator  68 .  
         [0028]    The accumulator  68  generates a phase offset p offset , which is input to an interpolator  72 . The interpolator  72  also receives p local  from the PLL  64 . The interpolator  72  generates a compensated clock signal based on p offset  and p local . An output of the interpolator  72  communicates with the transmitter  24 , which transmits the device data  28 .  
         [0029]    Referring now to FIG. 4, an optional spread spectrum mode of operation may also be provided. A frequency modulator generator  84  selectively generates a constant output and/or a spread spectrum modulation signal based upon a spread spectrum control signal (SSC). For example, the frequency modulation generator  84  can generate a triangular wave, a sine wave or any other spread spectrum modulation signal. An output of the frequency modulation generator  84  is input to a first input of a summer  86 . A second input of the summer  86  communicates with an output of the filter  66 . An output of the summer  86  communicates with an input of the accumulator  68 .  
         [0030]    When the spread spectrum control (SSC) is enabled, the output of the filter  66  is summed with the spread spectrum modulation signal to generate the phase offset p offset , which is input to the interpolator  72 . When spread spectrum control is disabled, the output of the filter  66  is summed with a constant output of the frequency modulation generator  84  to generate the phase offset p offset , which is input to the interpolator  72 .  
         [0031]    Referring now to FIG. 5, an exemplary implementation of the frequency offset compensator  38  is shown. The device  20  employs a second order timing recovery circuit. The clock data recovery and frequency offset calculator  60  includes a clock data recovery circuit  100  having an output connected to gain circuits  102  and  104 . An output of the gain circuit  102  (phase error) communicates with a first input of a summer  106 . An output of the gain circuit  104  (frequency error) communicates with a first input of a summer  108 .  
         [0032]    An output of the summer  108  communicates with a delay element  112 , which has an output connected to a second input of the summer  106  and a second input of the summer  108 . The delay elements can be registers. An output of the summer  106  is connected to an accumulator  110  including a summer  114  and a delay element  118 . The output of the summer  114  is connected to a first input of the summer  114 . An output of the summer  114  is connected to the delay element  118 , which has an output connected to a second input of the summer  114  and to a first input of an interpolator  122 .  
         [0033]    In an exemplary implementation, the interpolator  122  operates using 128-phases at 375 MHz, although higher or lower phases and/or frequencies can be used. A second input of the interpolator  122  is connected to an output of the PLL  64 . An output of the interpolator  122  is input to the clock data recovery circuit  100 . The clock data recovery and frequency offset calculator  60  outputs the frequency offset f offset , which is input to the LPF  66 . An output of the LPF  66  is connected to the summer  86 .  
         [0034]    An output of the frequency modulation generator  84  is connected to a second input of the summer  86 . An output of the summer  86  is connected to a first input of a summer  152  in the accumulator  68 . An output of the summer  152  is connected to a delay element  156 , which has an output that is connected to the interpolator  72  and to a second input of the summer  152 . The interpolator  72  operates using 128-phases at 750 MHz, although higher or lower phases and/or frequencies can be used.  
         [0035]    Referring now to FIG. 6, operation of the interpolators is illustrated briefly. The interpolators divide a clock frequency into multiple phases. For example, the interpolator  72  divides a clock frequency into 128 phases. Interpolation and frequency adjustment is performed by jumping the phase forward or backward. For example, CLK 0  is T/128 before CLK 1 . CLK 3  is 2T/ 128  after CLK 0 . CLK 0  is 5T/ 128  before CLK 6 .  
         [0036]    Referring now to FIG. 7, the host  10  and the device  20  may be connected by a serial ATA medium  180 . Referring now to FIG. 8, the host  10  can be a disk controller  10 - 1  and the device  20  can be a disk drive  20 - 1 . Still other hosts, devices and connection standards can be employed.  
         [0037]    Referring now to FIGS.  9 - 11 , several exemplary implementations of the PLL  64  are shown. In FIG. 9, the PLL  64  includes a phase detector  200  having an input connected to a reference frequency. An output of the phase detector  200  is input to a low pass filter  202 , which has an output that is connected to a first input of a summer  203 . A spread spectrum control (SSC) signal is input to a second input of the summer  203 . An output of the summer is input to a voltage controlled oscillator (VCO)  204 , which has an output that is fed back to the phase detector  200 . In FIG. 10, the PLL  64  supports open-loop spread spectrum operation. The reference frequency is input to a divide by M circuit  210 . The output of the VCO  204  is fed back through a divide by N circuit  214 . M and N are modulated to generate a triangular wave.  
         [0038]    In FIG. 11, the PLL  64  supports closed loop spread spectrum operation. The reference frequency is input to the divide by M circuit  210 . The output of the VCO  204  is fed back to a first input of an interpolator  216 . A frequency modulation generator  220  outputs a spread spectrum modulation signal, such as a triangular wave, sine wave, etc., to an accumulator  220 . An output of the accumulator  220  is input to a second input of the interpolator  216 . M and N are modulated to generate a triangular wave. The interpolator  216  provides smoothing. The reference frequency for the PLL  64  may be generated by a resonator, although other reference frequency generators can be used.  
         [0039]    Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.