Abstract:
In accordance with an aspect of an input/output device for providing fast translation between differential signals from a core of an integrated circuit and higher voltage signals that are external to the core, an I/O buffer includes low voltage devices for receiving core input signals, a cascode stage for setting a bias between the input devices and an output stage, and an output stage including a current mirror for providing a translated external output. Another aspect of the invention further includes a feedback path to cut off the current mirror to prevent static current and a keeper device to maintain an output level after cut off of the current mirror.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application relates to and claims priority from U.S. Provisional Patent Application Ser. No. 60/506,217, filed Sep. 26, 2003, and is incorporated herein by reference for all purposes. 

   FIELD OF THE INVENTION 
   The present invention relates generally to input/output circuits, and more particularly, to buffer circuits capable of fast translation between core and external signals. 
   BACKGROUND OF THE INVENTION 
   Conventional I/O buffers can include circuitry (typically in the I/O portion of an integrated circuit) to provide fast translation between core and external signals. Core signals may have lower voltage differential signaling levels, for example between 0 and 1 V, whereas external output signals may have higher voltage signaling, for example ranging between 0 and 3.3 V. 
     FIG. 1  illustrates a conventional translation scheme in conventional I/O buffer  10 . Core differential signals X/XB are provided to gates of transistors N 1 /N 2 , respectively. The drains of N 1  and N 2  are coupled to nodes D and B, respectively. The external signal output OUT is provided from node B in this example. In accordance with the state of the input differential signals X/XB, therefore, either N 1  or N 2  will turn on, pulling either node D or B toward Vss, respectively. Nodes D and B are further respectively coupled to the gates of P 2  and P 1 . Accordingly, if D is pulled toward Vss (having a value of about 0 V, for example) by action of N 1  and signals X/XB, P 2  will turn on, pulling node B (and thus external signal OUT) toward Vdd (having a value of about 3.3 V, for example). Conversely, if node B is pulled toward Vss (and thus external signal OUT) by action of N 2  and signals X/XB, P 1  will turn on, pulling D toward Vdd, and further turning off P 2 . 
   One problem with the conventional approach is that transistors with sufficient voltage ratings to tolerate the higher voltage output usually have high threshold voltages. Transistors with low threshold voltage and high breakdown voltage are either not available or are a costly process option. When X/XB are core differential signals having a maximum signaling value of about 1V, N 1  and N 2  are only driven weakly by signals X/XB because of the threshold voltage being so high. The result is slow responsiveness, which is a problem in, for example, applications where fast translation is desired. 
   SUMMARY OF THE INVENTION 
   The present invention relates to a circuit for providing fast translation from differential signals at the lower core voltage to higher voltage signals external to the core. In accordance with an aspect of the invention, an I/O buffer includes low voltage devices for receiving core input signals, a cascode stage for setting a bias between the input devices and an output stage, and an output stage including a current mirror for providing a translated external output. Another aspect of the invention further includes a feedback path to cut off the current mirror to prevent static current and a keeper device to maintain an output level after cut off of the current mirror. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures, wherein: 
       FIG. 1  illustrates a conventional I/O buffer; 
       FIG. 2  illustrates an I/O buffer for providing fast translation between input core differential signals and an external output signal according to the present invention; and 
       FIG. 3  illustrates another embodiment of an I/O buffer in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention will now be described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention. Notably, the figures and examples below are not meant to limit the scope of the present invention. Moreover, where certain elements of the present invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present invention will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the invention. Further, where an embodiment is described with singular components, the invention is not limited thereto, and it should be understood that plural components can be substituted therefor unless expressly stated otherwise herein. Still further, the present invention encompasses present and future known equivalents to the known components referred to herein by way of illustration. 
   An example implementation of a fast translation I/O buffer  20  in accordance with the present invention is illustrated in  FIG. 2 . As shown in  FIG. 2 , N 1  and N 2  have been replaced with N 1 ′ and N 2 ′ which are low-voltage devices capable of responding faster to changes in low-voltage core differential signals X/XB. The problem of the commonly available lower threshold core devices having too low of a breakdown voltage tolerance is addressed by transistors N 3  and N 4  (comprising cascode stage  22 ), which protect the drains of N 1 ′ and N 2 ′ from overvoltage. As further shown in this illustrative example, N 3  is coupled between the sources of N 1 ′ and P 1  at node C and transistor N 4  is coupled between the sources of N 2 ′ and P 2  at node A. Transistors N 3  and N 4  have threshold voltages similar to transistors P 1  and P 2 , in accordance with the desired external signaling voltage levels of OUT. The gates of transistors N 3  and N 4  are coupled to a bias voltage Vbias which is sufficiently high to overcome the higher threshold voltages of these devices. 
   As further shown in  FIG. 2 , in the output stage current mirror comprised of transistors P 1  and P 2 , the gate of P 1  is further coupled to node D. As is still further shown in this example, the output stage is further comprised of driver INV 1  which is coupled to node B between P 2  and N 4  and provides external signal OUT. 
   In operation, depending on the differential state of X/XB, either transistor N 1 ′ or N 2 ′ will more reliably and responsively pull either node C or A, respectively, toward Vss. Because N 3  and N 4  are supplied the same bias voltage at their gates, the node pulled more toward Vss will cause the respective transistor N 3  or N 4  to be turned on, pulling either node D or B, respectively, more toward Vss. This causes either P 1  or P 2  to pull the other node toward Vdd. 
   For example, where X/XB is high/low, for example 1V/0V, respectively, node A is pulled toward Vss by N 2 ′ turning on, causing the voltage difference between Vbias and node A to exceed the threshold voltage of N 4 . Meanwhile, N 1 ′ turns off, keeping the voltage at node C too close to Vbias and preventing N 3  from turning on. Because N 4  turns on, however, node B is pulled toward Vss, which is inverted by INV 1 , and so external signal OUT is driven high. Meanwhile, transistor P 2 , having its gate coupled to node D, stays off because N 3  stays off by action of N 1 ′ and the bias voltage supplied to the gate of N 3 . 
   Conversely, where X/XB is low/high, respectively, node C is pulled toward Vss by N 1 ′ turning on, causing the voltage difference between Vbias and node C to exceed the threshold voltage of N 3 . Meanwhile, N 2 ′ turns off, keeping the voltage at node A too close to Vbias and preventing N 4  from turning on. Because N 3  turns on, however, node D is pulled toward Vss. Meanwhile, transistor P 2 , having its gate coupled to node D, turns on, pulling node B toward Vdd, which is inverted by INV 1 , and so external signal OUT is driven low. Meanwhile, N 4  stays off by action of N 2 ′ and the bias voltage supplied to the gate of N 4 . 
   By virtue of the present invention, therefore, including the lower voltage devices N 1 ′ and N 2 ′, and biased devices N 3  and N 4 , the buffer  20  of  FIG. 2  is able to provide faster and more reliable translation between core and external signals. 
   Although the buffer  20  in  FIG. 2  provides advantages over the prior art, certain issues remain. For example, in a differential input state where XB is high and X is low, N 1  and N 3  turn on, causing node D to be pulled toward Vss and P 1  and P 2  to conduct. But, as P 1  conducts, node D is also pulled toward Vdd, causing excessive current and power to be consumed. 
   Another embodiment of the invention is illustrated in  FIG. 3 . As shown in  FIG. 3 , this embodiment of the invention further includes a feedback transistor N 5  coupled between transistor N 3  and node D, and keeper transistor P 3 , having its source coupled to node B and its gate coupled to the output OUT. The gate of N 5  is also coupled to the output OUT. 
   By virtue of this arrangement, for example, in the input differential signaling state when X is low and XB is high, node C is driven toward Vss, causing N 3  to turn on. Meanwhile, if the output OUT was previously in the high state (opposite of what needs to be signaled now), N 5  will be turned on, and node D will be pulled low, causing P 2  to conduct and pull node B toward Vdd. This will cause the output signal OUT to be driven low as desired, thus driving node E low. This situation causes P 3  to turn on, keeping node B pulled toward Vdd and shutting off N 5 , thus removing the path of static current in the XB signal path, which static current was a problem in the previous embodiment. 
   Although the present invention has been particularly described with reference to the preferred embodiments thereof, it should be readily apparent to those of ordinary skill in the art that changes and modifications in the form and details may be made without departing from the spirit and scope of the invention. It is intended that the appended claims include such changes and modifications.