Abstract:
A method for storage includes collecting information regarding respective performance characteristics of a plurality of memory units in a memory array, each memory unit including one or more cells of the memory array. When data are received for storage in the memory array, a memory unit is selected responsively to the respective performance characteristics, and the received data are stored in the selected memory unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Application No. 60/867,399, filed Nov. 28, 2006; U.S. Provisional Patent Application No. 60/868,342, filed Dec. 3, 2006; and U.S. Provisional Patent Application No. 60/870,398, filed Dec. 17, 2006. All of these related applications are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to memory devices, and particularly to methods and systems for writing and reading data to and from memory devices. 
     BACKGROUND OF THE INVENTION 
     Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data are written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. The possible bit values that can be stored in an analog memory cell are also referred to as the memory states of the cell. 
     Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume one of two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, can be programmed to assume more than two possible memory states and thus store two or more bits per memory cell. In some cases, the number of bits stored per cell and the nominal analog values used in storing the bits may be varied in the course of operation of a memory. 
     For example, U.S. Pat. Nos. 6,643,169 and 6,870,767, whose disclosures are incorporated herein by reference, point out that there exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits per cell may be increased when fidelity is less important and decreased when fidelity is more important. These patents describe a memory that can change between storage modes on a cell by cell basis. 
     Similarly, U.S. Pat. No. 6,466,476, whose disclosure is incorporated herein by reference, describes a multi-bit-per-cell non-volatile memory that stores different portions of a data stream using different numbers of bits per cell. In particular, data that require a high degree of data integrity (such as the header of a data frame) are stored using a relatively small number of bits per memory cell, while more error-tolerant data (such as music, images, or video) are stored using a relatively large number of bits per memory cell. Write circuitry decodes an input data stream and determines the number of bits to be written in each memory cell. 
     U.S. Patent Application Publication 2005/0024941, whose disclosure is incorporated herein by reference, describes a method and system for archiving data according to the desired data lifetime. For example, short-term data can be archived using larger programming voltage pulse increments than for long-term data; using a lower target threshold voltage than for long-term data; using wider programming voltage pulses than for long-term data; using higher starting programming voltages than for long-term data; using fewer programming voltage pulses than for long term data; using lower maximum programming voltages than for long term data; or using more levels per cell than for long-term data. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a method for storage that includes collecting information regarding respective performance characteristics of a plurality of memory units in a memory array, each memory unit comprising one or more cells of the memory array. The method includes receiving data for storage in the memory array, selecting a memory unit responsively to the respective performance characteristics, and storing the received data in the selected memory unit. 
     There is also provided, in accordance with another embodiment of the present invention, a method for storage, which includes receiving data from a host processor for storage by a memory controller in a memory array and receiving an input at the memory controller indicating that the memory controller is to operate in a power-saving mode. The data are written from the memory controller to the memory array in accordance with write parameters appropriate to the power-saving mode. 
     There is additionally provided, in accordance with an embodiment of the present invention, a method for storage, which includes receiving an instruction from a host processor to a memory controller to transfer data between a buffer and a memory array and receiving an input at the memory controller indicating that the memory controller is to operate in a high-throughput mode. The data are transferred between the buffer and the memory array using the memory controller at a throughput rate appropriate to the high-throughput mode. 
     Other embodiments of the present invention provide storage apparatus, which includes a memory controller that is configured to carry out the methods described above. 
     The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram that schematically illustrates a system for data storage, in accordance with an embodiment of the present invention; 
         FIG. 2  is a flow chart that schematically illustrates a method for storing data, in accordance with an embodiment of the present invention; and 
         FIG. 3  is a flow chart that schematically illustrates a method for storing data, in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Overview 
     Embodiments of the present invention that are described hereinbelow provide methods and devices for controlling performance features of a memory, and particularly for controlling the power consumption of the memory. These methods are typically implemented in a memory controller, which handles requests by a host processor to write to, erase and read from the memory. In deciding how to handle write requests, the memory controller accesses a record, which may be stored, for example, in a database, of respective performance characteristics of different memory units (groups of cells) in the memory. The controller chooses one or more memory units to use in serving a given write requests by matching the performance characteristics of the memory units to performance requirements, such as power consumption or throughput. 
     In some embodiments, the controller has different operating modes, which are invoked by instructions from the host processor or other input. The controller handles read and write requests differently depending on the operating mode. For example, when the memory is installed in a battery-powered device, the controller may receive an input when the device is disconnected from external power, indicating that it should operate in a power-saving mode. In power-saving mode, the controller will choose to write data to memory units that are characterized by relatively low power consumption, as indicated by the record of performance characteristics mentioned above. Additionally or alternatively, while in power-saving mode, the controller may write the data in a manner that saves power by writing at low bit-density, low voltage, or coarse precision, or using small number of programming steps, and/or low pre-processing strength (specifically low encoding strength), for example. 
     System Description 
       FIG. 1  is a block diagram that schematically illustrates a system  20  for data storage, in accordance with an embodiment of the present invention. For the sake of illustration in the description that follows, it will be assumed that system  20  is part of a portable, battery-powered device, such as digital camera or portable media player. Such devices are normally capable of being connected to an external source of power, such as an AC power line or dedicated DC power supply or power supplied by a personal computer or other console via certain types of data connections, such as a USB connection. When the device is unplugged from the external power source, it is desirable that system  20  reduce its relative power consumption in order to prolong battery life. 
     System  20  comprises a memory subsystem  22  and a host processor  24 , which writes data to and reads data from the memory subsystem. The host processor may also provide indications of application requirements to the memory subsystem with respect to certain read and write requests. For example, for a given file that is to be written to the memory subsystem, the host processor may indicate the desired throughput rate and/or reliability of writing, storing and/or reading the data in the file. The memory subsystem uses these indications in determining how and where to store the data, as explained in detail hereinbelow. 
     Memory subsystem  22  comprises a memory array  26 , which is accessed and controlled by a memory controller  28 . The memory controller selects the cells in the array to which data are to be written and read from in response to each request from host processor  24 . The memory controller may also encode the data with suitable error correction codes before writing to the array, as well as decoding and correcting errors in the data upon readout. For these purposes, the controller may implement encoding and signal processing functions of the types described, for example, in PCT Patent Application PCT/IL2007/000580, filed May 10, 2007, which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference. Controller  28  and array  26  may be fabricated together on a single integrated circuit (IC) die, or they may alternatively be embodied in separate components, for example, on separate dies in a multi-chip package (MCP) or on separate IC. Although only a single memory array is shown in  FIG. 1 , controller  28  may alternatively interface with multiple memory arrays simultaneously in the manner described herein. Additionally or alternatively, although host processor  24  is shown in  FIG. 1  as being separate from controller  28 , the host processor and controller may be implemented as circuit component in the same chip 
     Memory array  26  comprises a matrix of memory cells  30 . In the examples that follow, it will be assumed that array  26  comprises analog non-volatile memory (NVM), such as MLC Flash memory. Alternatively, the principles of the present invention may be applied, mutatis mutandis, to memories of other kinds. For purposes of performance management by controller  28 , cells  30  are divided into groups, which are referred to herein as memory units. A group for this purpose may comprise only a single cell, but typically each memory unit comprises multiple cells, for example:
         A group of cells that is simultaneously programmed or read (such as a row of cells sharing a common wordline).   A page, corresponding to a certain data value or set of data values that are simultaneously programmed to a group of cells, or a sector within a page.   A group of pages, such as a block (which is typically a group of pages that are simultaneously erased).   An entire die or plane (wherein a die typically comprises two planes).       

     Controller  28  maintains a record of performance characteristics of the memory units in a memory  32 . The record may conveniently be held in a control database  34 , but other data structures may alternatively be used for this purpose. Typically, memory  32  comprises a volatile memory, such as random-access memory (RAM), which is used by the controller to hold control information and may be backed up in memory array  26  when system  20  is powered down. Alternatively, database  34  may be held in an area of array  26  or in a separate programmable read-only memory (PROM) (assuming the database is written once and not updated thereafter). 
     Table I below lists some of the performance characteristics that may be recorded for each memory unit in database  34 . These characteristics are listed by way of example, and not limitation. In practice, database  34  may contain only a subset of these characteristics, and may also contain other relevant characteristics that are not listed below: 
     
       
         
               
             
               
               
             
           
               
                 TABLE I 
               
               
                   
               
               
                 MEMORY UNIT PERFORMANCE CHARACTERISTICS 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Status (cells available for data, bad cells, etc.) 
               
               
                   
                 Capacity parameters (number of bits/cell). 
               
               
                   
                 Wear level (number of write/erase cycles performed on 
               
               
                   
                 this unit). 
               
               
                   
                 Signal characteristics, relating to the data storage 
               
               
                   
                 quality and reliability of the memory unit, including: 
               
               
                   
                   Noise variance of data stored in cells of the 
               
               
                   
                   unit. 
               
               
                   
                   Level of data retention error in the cells. 
               
               
                   
                   Number of errors detected in recent read 
               
               
                   
                   operations. 
               
               
                   
                   Number of program-and-verify (P&amp;V) iterations 
               
               
                   
                   required to program cells in this unit. 
               
               
                   
                   Required number of erase iterations. 
               
               
                   
                 Speed characteristics, including: 
               
               
                   
                   Time required to program the cells in the unit. 
               
               
                   
                   Time required to erase the cells in the unit. 
               
               
                   
                   Sensing time (also referred to as busy time, i.e., 
               
               
                   
                   time elapsed between a command by controller 28 to 
               
               
                   
                   read data from the memory unit and data output 
               
               
                   
                   from array 26). 
               
               
                   
                   The amount (and hence duration) of post-processing 
               
               
                   
                   (such as error correction code [ECC] decoding) 
               
               
                   
                   required to detect the data read from the unit. 
               
               
                   
                   The amount (and hence duration) of pre-processing 
               
               
                   
                   (such as ECC encoding) required to reliably 
               
               
                   
                   prepare the data for storage in this unit 
               
               
                   
                 Power consumption characteristics, including: 
               
               
                   
                   Power and maximum voltage value required for 
               
               
                   
                   writing data to the cells in the unit. 
               
               
                   
                   Power required for erasing the unit. 
               
               
                   
                   Power required for reading data from the cells in 
               
               
                   
                   the unit. 
               
               
                   
                   
               
             
          
         
       
     
     In practice, the power consumption characteristics may be understood more broadly to include a number of the signal and speed characteristics listed above. For example, in some memory devices, factors causing slow performance (such as a large number of P&amp;V cycles required to write to a cell or a long sensing time to read from a cell) also result in larger power consumption. Similarly, large numbers of errors in the cells in a given unit may require controller  28  to expend more power in correcting the errors when reading from these cells. 
     The highest voltage value required to write data to a given unit (listed above under power consumption characteristics) may be determined using methods described in the above-mentioned U.S. Provisional Patent Application No. 60/868,342. In analog memory devices that are known in the art, nominal voltage values, which are typically uniform over the entire memory array, are used for writing the appropriate bit values to the cells. The analog values that are actually stored in the memory cells, however, often deviate from the nominal values in accordance with a certain statistical distribution. Therefore, in subsystem  22 , the statistical properties of the distribution of analog values stored in the cells of each memory unit may be measured, and the actual voltage values corresponding to different bit values may be adjusted for each unit based on these statistical properties. In consequence, different units may have different programming voltages, which are recorded in database  34 . For example, memory units whose analog values have a relatively low mean and low variance may be assigned a lower programming voltage and thus are identified as requiring lower programming power. 
     The performance characteristics of each memory unit may be tested in production of memory array  26  and recorded in database  34  prior to installation of the memory array in system  20 . Alternatively or additionally, these characteristics may be measured and/or updated after array  26  has been installed in system  20 . For example, the performance characteristics may be measured by a diagnostic routine that runs when subsystem  22  is first powered up, and deliberately initiates certain program, read and erase operations. This sort of routine may be re-run intermittently over the life of system  20 , typically as a background task of controller  28 . As another option, controller  28  may monitor normal read, write and erase operations in order to update the database. 
     Subsystem  22  has a power-saving mode, which is invoked by a power control input  36  to controller  28 . The input may be invoked by host processor  24  or manually by a user of system  20 . Alternatively or additionally, controller  28  may be configured to sense, via input  36 , whether system  20  is connected to an external source of power, as explained above, or is operating on internal battery power. The controller implements power-saving measures when operating on internal battery power. As a part of these measures, the controller may choose particular memory units to which it will write data depending on the specific power consumption characteristics of these memory units. The power-saving measures may be facilitated by preparatory and backup action that the control takes when external power is connected, as described further hereinbelow. 
     Behavior of controller  28  in power-saving mode may differ from one device to another. For example, digital cameras typically perform memory write operations while operating on battery power. In this case, the controller may choose memory units with low power consumption for writing images to memory. On the other hand, images are typically read out of the camera while the camera is connected to and receives power from a computer, so that power saving is not a consideration during read. By contrast, files are generally written to a portable media player (such as an MP3 player) while the player is connected to and receives power from a computer. In this case, it is more important that the files be written to subsystem  22  in a way that will facilitate low power consumption upon reading from memory array  26 , which is usually performed under battery power. 
     As noted above, controller  28  may also have high-throughput and high-reliability modes of operation, which are typically invoked by host processor  24  in response to application requirements. (Typically, these alternative modes require relatively high power consumption.) For example, the high-throughput mode may be invoked for storage of video data, as opposed to audio or still-image data, which can tolerate low throughput. As another example, controller  28  may use the high-throughput mode to write data rapidly from a buffer to memory array  26  when the buffer is about to overflow, or to read data from the memory array to a buffer when the buffer is nearly empty. The high-reliability mode may be used when writing data to the memory array in order to specify a certain coding strength to be used by the controller or a target bit error rate (BER) that is to be maintained in the stored data. 
     Methods for Reducing Power Consumption 
       FIG. 2  is a flow chart that schematically illustrates a method for storing data, in accordance with an embodiment of the present invention. Initially, power consumption characteristics of each memory unit in array  26  are measured, at a measurement step  40 . As noted above, this step may be carried out either by memory controller  28  in situ or by an external tester at the time of production, or both. Typical power consumption characteristics are listed above in Table I. The measured characteristics are recorded in database  34 , at a recording step  42 . After the power consumption characteristics have been recorded, memory subsystem  22  is ready to operate in power-saving mode when required. (Some aspects of power-saving mode operation, however, may be implemented without a database of power consumption characteristics.) 
     Controller  28  checks which mode it is to use upon receiving data from host processor for writing to memory array  26 , at a data input step  44 . As noted above, power control input  36  may be activated by various different components and factors. In the present example, it is assumed that input  36  is connected to sense when system  20  is receiving power from an external source (referred to herein as a “line”), at a power sensing step  46 . 
     If controller  28  determines at step  46  that the line power is on, it writes the data to memory array  26  in full-power mode, at a full-power writing step  48 . Typically, when lines power is available, the controller employs a strong pre-processing algorithm. For example, the controller may compute a strong error-correcting code, and may write the data together with the code to a memory unit at the full data density that the unit is able to sustain (i.e., using the full number of bits/cell that the cells of the memory unit are capable of storing). An another example, the controller may use a strong compression algorithm to compress the data in full-power mode and a weaker algorithm in power-saving mode. Optionally, the controller may choose the memory unit and coding scheme so as to reduce the power that will be required to read out the data subsequently, as described further hereinbelow with reference to  FIG. 3 . 
     On the other hand, if controller  28  determines at step  46  that line power is off, it writes the data to memory array  26  in power-saving mode. For this purpose, the controller chooses one or more memory units whose power consumption characteristics (as recorded in database  34 ) indicate that they will require relatively low power to write, at a unit selection step  50 . The selected memory units, for example, may be those that require relatively low voltage and low power and few P&amp;V cycles for programming, as explained above. 
     Controller  28  writes the data to the selected memory units in accordance with write parameters appropriate to the power-saving mode, at a low-power write step  52 . These write parameters may include, for example, data density, programming step size, and/or coding strength, as explained below:
         Writing data at reduced density—The controller writes fewer bits/cell than would be possible if the cells were used at full capacity. Specifically, the controller may use only the lower voltage levels, thus exploiting only a narrow, low-voltage window within the overall range of levels supported by the cells. For instance, the controller may use only the two or four lowest levels of an eight-level (three bit) cell. As a result, the voltage and power applied in programming the cells are reduced.   Using larger incremental-step pulse programming (ISPP) increments in programming the cells—Flash memories are programmed by applying successive voltage steps to the cells, until the cells reach the desired levels. Increasing the size of the steps may reduce overall power consumption, although at the cost of larger programming errors.   Reducing the strength of pre-processing algorithms (such as ECC and/or compression algorithms, as noted above)—The “strength” of an ECC algorithm, for example, expresses the number and severity of errors that the code is able to correct or, equivalently, the computing power that must be invested in implementing the code. Reducing the strength of the code may mean using a simpler code or no code at all. In this way, the power consumed by the controller itself in code computation is reduced, at the possible expense of reduced reliability. When using this means of reducing power consumption, the controller may choose to write the data to memory units that have particularly good signal characteristics, as indicated in database  34  and listed in Table I above.
 
Additionally or alternatively, controller  28  may use other write parameters and may adopt other power-conserving measures, such as operating subsystem  22  at a reduced clock speed.
       

     When lines power is restored to system  20 , controller  28  may compensate for the compromises that were made in writing data in power-saving mode, at a data compensation step  54 . Specifically, the controller may copy over data that were written at low density to other cells at full density. Additionally or alternatively, the controller may compress data that were written without compression in power-saving mode or may apply another stage of stronger compression to data that were only weakly compressed in power-saving mode. It may also be possible to perform maintenance tasks, such as refreshing cells, and to compute and store stronger error-correction codes at this stage. After copying the data in this manner, the controller may reuse the cells that originally held the data to storing additional data. 
       FIG. 3  is a flow chart that schematically illustrates a method for storing data, in accordance with another embodiment of the present invention. This method is directed particularly to writing data (typically in full-power mode) in a manner that will reduce the power needed to read the data in power-saving mode. It is useful, for example, in portable media players, which commonly write media files to memory while plugged into (and receiving power from) a personal computer, but then read and play back the media files under internal battery power. 
     The method of  FIG. 3  is initiated when controller  28  receives data to write to memory array  26 , at a data input step  60 . The controller chooses memory units to which to write the data, at a unit selection step  62 , based on the power-consumption characteristics of the units as recorded in database  34 . For example, the controller may choose units that have low read power and/or low sensing time. 
     Controller  28  may choose a coding scheme that is appropriate for low-power readout, at a coding selection step  64 . Typically, coding schemes that permit the controller to minimize the amount of decoding computation are desirable in this context. For example, the controller may use a turbo code, which is decoded at read time using an iterative decoding scheme. As a result, when the controller decodes the data subsequently in power-saving mode, it may simply stop at a certain point in the iteration, in order to avoid excess power consumption, and output the data even if not all of the errors have been resolved. As another example, the controller may choose a coding scheme that is appropriate to the wear level of the memory unit: When the wear level is low, so that few errors are expected on readout, the controller may use a weak error-correcting code, which minimizes power consumption in decoding. At higher wear levels, the controller may use a stronger code in order to deal with the higher expected error rate. (On the other hand, given cells having different wear levels, the controller may still choose to store data in cells with the higher wear level if these cells are characterized by low power consumption.) 
     After choosing the memory units and coding scheme, controller  28  encodes and writes the data to memory array  26 , at a data writing step  66 . 
     Although the methods of  FIGS. 2 and 3  are described, for the sake of convenience and clarity, with reference to system  20  ( FIG. 1 ), the principles embodied in these methods and in the use of the performance characteristics listed in Table I may similarly be applied in other sorts of memory and storage subsystems. It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.