Abstract:
In some embodiments, laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates are presented. In this regard, a substrate in introduced having a dielectric layer wherein material has been removed from a surface and the cavity has been plated with conductive material resulting in a feature width of less than about 10 micrometers. Other embodiments are also disclosed and claimed.

Description:
FIELD OF THE INVENTION  
       [0001]     Embodiments of the present invention generally relate to the field of integrated circuit packages, and, more particularly to a laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates.  
       BACKGROUND OF THE INVENTION  
       [0002]     The demand for enhanced performance and body size reduction of integrated circuit components continues to increase design and fabrication complexity due to the higher bandwidth requirements needed to enable higher clock frequencies. The substrates designed for these components will need to be manufactured with even smaller feature sizes to enable optimization of bandwidth. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0003]     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:  
         [0004]      FIG. 1  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention;  
         [0005]      FIG. 2  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention;  
         [0006]      FIG. 3  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention;  
         [0007]      FIG. 4  is a flow chart of an example method for fabricating a high density interconnect flip chip substrate, in accordance with one example embodiment of the invention; and  
         [0008]      FIG. 5  is a block diagram of an example electronic appliance suitable for implementing a high density interconnect flip chip substrate, in accordance with one example embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0009]     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.  
         [0010]     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.  
         [0011]      FIG. 1  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. In accordance with the illustrated example embodiment, package substrate  100  includes one or more of dielectric layers  102  and  106 , core layer  104 , cavities  108  and  110 , and surface  112 .  
         [0012]     Dielectric layers  102  and  106  represent material such as epoxy resin that has been added to core layer  104  as part of a build-up process. Although not shown, conductive traces may be routed within and through-holes may be routed through dielectric layers  102  and  106 .  
         [0013]     Core layer  104  represents a substrate core that may be made of a metal such as copper. Core layer  104  may be laminated with dielectric material as part of a substrate build-up and may have insulated traces routed through it.  
         [0014]     Cavities  108  and  110  represent areas where dielectric material has been removed from layer  102  below surface  112 . As part of a process of fabricating a high density interconnect flip chip substrate, for example as described in reference to  FIG. 4 , cavities  108  and  110  may have been created by a hybrid process involving laser ablation and imprinting technology. Cavity  108  is intended to represent a cavity with a line/space geometry of equal to or less than about 10 micrometers that was created through laser ablation. Cavity  110  is intended to represent a cavity with a line/space geometry of greater than about 10 micrometers that was created through imprinting technology.  
         [0015]      FIG. 2  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown, package substrate  200  includes conductive plating layer  202  which has plated cavities  108  and  110  and surface  112 . Conductive plating layer  202  may be a layer of copper.  
         [0016]      FIG. 3  is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As part of a planarization process, conductive plating layer  202  over surface  112  has been removed, leaving cavities  108  and  110  filled with conductive material.  
         [0017]     In one embodiment, package substrate  300  is coupled on surface  112  with an integrated circuit die such as a flip chip silicon die. In another embodiment, surface  112  is laminated with another dielectric layer as part of a continued build-up process.  
         [0018]      FIG. 4  is a flow chart of an example method for fabricating a high density interconnect flip chip substrate, in accordance with one example embodiment of the invention. It will be readily apparent to those of ordinary skill in the art that although the following operations may be described as a sequential process, many of the operations may in fact be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged or steps may be repeated without departing from the spirit of embodiments of the invention.  
         [0019]     According to but one example implementation, the method of  FIG. 4  begins with lamination ( 402 ) of dielectric material (for example layer  102 ) on a core layer (for example layer  104 ).  
         [0020]     Next, feature formation ( 404 ) takes place in dielectric layer  102 . In one embodiment, imprinting technology is utilized to displace dielectric material, effectively removing from the surface ( 112 ) and creating features where the required feature width is greater than about 10 micrometers. Non-imprinted areas may be masked off (appearing as blank areas) on the micro-tool. In one embodiment, nickel plated micro-tools are used to stamp surface  112  to generate patterns and structures in dielectric layer  102 . In one embodiment, subsequent to an imprint performed, a release coating is applied by spray coating. In one embodiment, imprinting is done at a temperature of not more than about 170 C and a pressure of not more than about 2 atm.  
         [0021]     In some embodiments, laser ablation is then utilized to pattern dielectric layer  102  where the required feature width is less than about 10 micrometers, for example in the necking regions of the substrate. In one embodiment, a high fluence eximer laser operating at a wavelength of about 248 nm is utilized.  
         [0022]     Next, any residue left behind in the feature formation would be removed ( 406 ). In one embodiment, plasma etching with tetrafluoromethane or carbon tetrafluoride is used to remove residual dielectric material from cavities  108  and  110 .  
         [0023]     Lastly, surface  112  and cavities  108  and  110  plated and planarized ( 408 ). In one embodiment, a damascene-style process flow would be followed where the features would be plated with copper and a chemical mechanical planarization process would be followed to remove the overplated copper. In one embodiment, planarization includes a high removal rate copper slurry with removal rates of about 15 um/min. Additional steps may be needed to complete the substrate and to couple the substrate with an integrated circuit die.  
         [0024]      FIG. 5  is a block diagram of an example electronic appliance suitable for implementing a high density interconnect flip chip substrate, in accordance with one example embodiment of the invention. Electronic appliance  500  is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, desktops, cell phones, wireless communication subscriber units, wireless communication telephony infrastructure elements, personal digital assistants, set-top boxes, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance  500  may include one or more of processor(s)  502 , memory controller  504 , system memory  506 , input/output controller  508 , network controller  510 , and input/output device(s)  512  coupled as shown in  FIG. 5 . Processor(s)  502 , or other integrated circuit components of electronic appliance  500 , may be housed in a package including a substrate described previously as an embodiment of the present invention.  
         [0025]     Processor(s)  502  may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s)  502  are Intel® compatible processors. Processor(s)  502  may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system.  
         [0026]     Memory controller  504  may represent any type of chipset or control logic that interfaces system memory  508  with the other components of electronic appliance  500 . In one embodiment, the connection between processor(s)  502  and memory controller  504  may be referred to as a front-side bus. In another embodiment, memory controller  504  may be referred to as a north bridge.  
         [0027]     System memory  506  may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s)  502 . Typically, though the invention is not limited in this respect, system memory  506  will consist of dynamic random access memory (DRAM). In one embodiment, system memory  506  may consist of Rambus DRAM (RDRAM). In another embodiment, system memory  506  may consist of double data rate synchronous DRAM (DDRSDRAM).  
         [0028]     Input/output (I/O) controller  508  may represent any type of chipset or control logic that interfaces I/O device(s)  512  with the other components of electronic appliance  500 . In one embodiment, I/O controller  508  may be referred to as a south bridge. In another embodiment, I/O controller  508  may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003.  
         [0029]     Network controller  510  may represent any type of device that allows electronic appliance  500  to communicate with other electronic appliances or devices. In one embodiment, network controller  510  may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller  510  may be an Ethernet network interface card.  
         [0030]     Input/output (I/O) device(s)  512  may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance  500 .  
         [0031]     In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.  
         [0032]     Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.