Abstract:
The invention described herein provides a method and apparatus that allows direct digital to IF/RF conversion using pulse-shaping. The method facilitates obtaining a flat or near flat output spectrum after digital to analog conversion with a minimal loss in signal energy. As opposed to pulse-shortening, where the DAC output pulse and consequently the energy per sample are reduced to a fraction a&lt;1 of the maximum, the pulse-shaping does not shorten the DAC pulse. For each sample, pulse-shaping first stores the energy delivered by DAC and then releases the stored energy to the output during a short period of time aT. This way little signal energy is lost even for very small values of a. With pulse-shaping, the duration aT of the output pulse contributes to the spectral flatness in a way similar to that pulse-shortening, but has the additional benefit that the shape of the output pulse contributes significantly to a flat spectrum. Two embodiments of the pulse-shaping method are described in the context of two types of DAC that are used: one with current output and the other with voltage output. Then, two examples of pulse-shaping implementation are given for a single-ended current-output DAC and for a differential current-output DAC.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to wireless data communications systems and is particularly concerned with direct digital to RF conversion.  
       BACKGROUND OF THE INVENTION  
       [0002]     With advances in digital technology and digital signal processing, more and more functionality is moved from analog circuits to digital circuits. This has many advantages including higher integration, steeper costs descend, accuracy, repeatability and reliability. Digital communications is one the fields that have both driven and tremendously benefited from this trend.  
         [0003]     Many digital receivers today utilize IF (intermediate frequency) or RF (radio frequency) sampling to reduce the number of analog components to a minimum. With IF/RF sampling, the sample and hold (S/H) analog to digital converter (ADC) samples and quantize directly the IF/RF signal as opposed to base-band sampling where the signal is first down-converted to base-band (low frequencies), filtered and that sampled. IF/RF sampling provides better performance (precise filtering and quadrature demodulation) while reducing the number of analog components (local oscillator, mixer, amplifiers, filters). In order to increase the analog input signal frequency f without raising the clock frequency for the ADC f CLK , IF/RF sampling utilizes sub-sampling. With sub-sampling, for an analog frequency band f min &lt;f&lt;f max , f CLK  is chosen such that there exists an integer n that satisfies: n·f CLK /2&lt;f min  and f max &lt;(n+1)·f CLK /2. Sub-sampling implicitly down-converts the signal from f to f−rnd(n/2)·f CLK· , where rnd( ) denotes rounding to the nearest integer. The integer rnd(n/2) is called sub-sampling factor and can be as large as tens or hundreds depending on the design.  
         [0004]     Theoretically, sub-sampling can be also applied at the transmission since the digitized signal has a repetitive frequency spectrum with a period of f CLK . The repetitions are usually called images and spectrum between 0 and f CLK /2 is typically called main image. Sub-sampling could be used at transmission if the digital to analog converter (DAC) could output each sample as an infinitely short pulse of energy proportional with the sample value. This is not possible, because an infinitely short pulse with non-zero energy must have infinite amplitude. Therefore, typical DAC implementations output each sample as a pulse having the energy proportional with the sample value and the duration equal to the sample period T=1/f CLK . Mathematically, this is equivalent to multiplying the digital signal spectrum by an attenuated sine function: 
 
 sinc ( f )=sin(2 π·f/f   CLK )/(2 π·f/f   CLK ). 
 
         [0005]      FIG. 1  shows the power spectral density (PSD) for a typical DAC, clocked at 100 MHz, with the main image being centered at 25 MHz and having approximately 24 MHz bandwidth. We note that images extend to and beyond 1000 MHz. However, we note that the signal level and implicitly the signal to noise ratio (SNR) decreases with frequency. For example, the image at 825 MHz is attenuated more that 30 dB and has less than 20 dB SNR, compared to the main image that has almost 50 dB SNR. We also note that all the images except the main one suffer significant linear distortions with differences in frequency response between f min  and f max  as high as 7-8 dB.  
         [heading-0006]     To overcome the effects of the attenuated sine, some DAC manufactures have proposed shortening the DAC pulse to a fraction of the sample period T aT, a&lt;1. With a shortened pulse, the attenuated sine function becomes: 
 
 sinc ( a·f )=sin(2 π·a·f/f   CLK )/(2π· a·f/f   CLK ) 
 
 One can easily prove that the smaller the a, the flatter the spectrum. Unfortunately, decreasing a causes a proportional decrease in the energy per sample, the signal power and consequently the SNR. 
 
         [0008]      FIG. 2  shows the power spectral density (PSD) for a pulse-shortening DAC with a=⅙ and clocked at 100 MHz. Again, the main image is centered at 25 MHz and has approximately 24 MHz bandwidth. We note that the signal level for the main image is reduced by almost 8 dB, compared to that of  FIG. 1 , but the response at the high frequencies is definitively improved. For example the image at 825 MHz is attenuated approximately 22 dB and has almost 30 dB SNR. We note also that linear distortions now affect only part of the images. For the image at 825 MHz there is practically no linear distortion.  
         [0009]     One can infer that making a smaller would produce better and better results. Unfortunately, for small a values the improvement in the frequency response is offset by the reduction in the overall signal energy.  FIG. 3  shows the power spectral density (PSD) for a pulse-shortening DAC with a={fraction (1/20)} and clocked at 100 MHz. The main image is again centered at 25 MHz and has an approximately 24 MHz bandwidth. We note that, for the main image, the signal level is reduced by 13 dB and the SNR is approximately 38 dB. The frequency response is almost flat, with all images attenuated less then 5 dB in comparison with the main one. However, their performance cannot be better than the main image, which is already strongly attenuated. By taking all possible combinations one can easily show that the image at 825 MHz is always attenuated at least 15 dB and therefore, it cannot provide an SNR better than 36 dB.  
       SUMMARY OF THE INVENTION  
       [0010]     The invention described herein provides a method and apparatus that allows direct digital to IF/RF conversion using pulse-shaping. The method facilitates obtaining a flat or near flat output spectrum after digital to analog conversion with a minimal loss in signal energy. As opposed to pulse-shortening, where the DAC output pulse and consequently the energy per sample are reduced to a fraction a&lt;1 of the maximum, the pulse-shaping does not shorten the DAC pulse. For each sample, pulse-shaping first stores the energy delivered by DAC and then releases the stored energy to the output during a short period of time aT. This way little signal energy is lost even for very small values of a. With pulse-shaping, the duration aT of the output pulse contributes to the spectral flatness in a way similar to that pulse-shortening, but has the additional benefit that the shape of the output pulse contributes significantly to a flat spectrum.  
         [0011]     In the following sections, two embodiments of the pulse-shaping method are described in the context of two types of DAC that are used: one with current output and the other with voltage output. Then, two examples of pulse-shaping implementation are given for a single-ended current-output DAC and for a differential current-output DAC. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The present invention will be further understood from the following detailed description with reference to the drawings in which:  
         [0013]      FIG. 1  graphically illustrates the power spectral density. (PSD) for a typical digital-to-analog converter (DAC);  
         [0014]      FIG. 2  graphically illustrates the power spectral density (PSD) for a typical digital-to-analog converter (DAC) with pulse-shortening for a=⅙;  
         [0015]      FIG. 3  graphically illustrates the power spectral density (PSD) for a typical digital-to-analog converter (DAC) with pulse-shortening for a={fraction (1/20)};  
         [0016]      FIG. 4  illustrates a typical current-output digital-to-analog converter (DAC);  
         [0017]      FIG. 5  illustrates a digital-to-analog converter (DAC) with pulse-shaping in accordance with a first embodiment of the present invention;  
         [0018]      FIG. 6  illustrates a typical voltage-output digital-to-analog converter (DAC);  
         [0019]      FIG. 7  illustrates a digital-to-analog converter (DAC) with pulse-shaping in accordance with a second embodiment of the present invention;  
         [0020]      FIG. 8  illustrates a first implementation of the embodiment of  FIG. 5 ;  
         [0021]      FIG. 9  illustrates a second implementation of the embodiment of  FIG. 5 ;  
         [0022]      FIG. 10  illustrates a pulse and clock generator for the implementations of  FIGS. 8 and 9 :  
         [0023]      FIG. 11  graphically illustrates the signals for the pulse and clock generator of  FIG. 10 ;  
         [0024]      FIG. 12  graphically illustrates the power spectral density (PSD) for a pulse-shaping digital-to-analog converter (DAC) with a=⅙;  
         [0025]      FIG. 13  graphically illustrates the power spectral density (PSD) for a pulse-shaping digital-to-analog converter (DAC) with a={fraction (1/20)} 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0026]     Referring to  FIG. 4  there is illustrated a typical current-output digital-to-analog converter (DAC). The DAC  10  has a data port  12  and a clock input  14  and an output  16  coupled it to ground through a load resistor (R)  18 . With a current-output DAC as shown in  FIG. 4 , the output current I at a given moment is proportional to the last sample value written into the DAC  10 , as long as the voltage at the DAC output  16  is smaller than a certain limit, V max . The sample values are written into the DAC  10  through the DATA port  12  every rising (or every falling in certain implementations) edge of the CLK DAC . The voltage limit V&lt;V max  ensures the proper operation of the controlled current source at the DAC output  16 . Knowing V max  and the full-scale current IFS one can calculate the maximum value for the load resistor as: 
 
 R   0   =V   max   /I   FS  
 
 Hence any resistor value larger than R 0  will prevent the DAC output from reaching the full-scale current due to voltage limitation. For each sample, the energy delivered by DAC to the load is: 
 
 E   0   =R   0   I   2   T  
 
 With a constant I, power delivered to the load is proportional with the load resistance and thus, using a load equal to R 0  maximizes the signal power at the output for the given DAC parameters V max  and I FS . 
 
         [0029]     Referring to  FIG. 5  there is illustrated a digital-to-analog converter (DAC) with pulse shaping in accordance with a first embodiment of the present invention. The DAC  10  has a data port  12  a clock input  14  and in the output  16 . The output  16  is coupled to the load resistor  18 ′ through an inductor  20 . A pair of switches  22  and  24  are operable to couple either side of the inductor  20  to ground.  
         [0030]     In operation, with the pulse shaping method as described with regard to the first embodiment of the present invention, the energy produced by a current-output DAC  10  every sample is stored in the inductor  20  during a first stage and then released from the inductor  20  to the load  18 ′ during a second stage. The first stage lasts for a time (1−a)T while second stage lasts for a time aT. The principle of the method is shown in  FIG. 5 . The inductor  20 , with value L, is used to store temporarily the energy. T is the load resistor  18 ′, a value of R. The first switch  22  (SW 1 ) stays closed in the first stage and opens in second stage. The second switch  24  (SW 2 ) is an optional switch that can be used to force the DAC output voltage to zero during the second stage. If used, SW 2  it is open in the first stage and closed in the second stage.  
         [0031]     The value L of inductor  20  is chosen so that DAC output current can reach the full-scale value in less time than (1−a)T, hence L is given by: 
 
 L=V   max    T (1− a )/ I   FS   =R   0    T (1− a ) 
 
 The energy stored in inductor during the first stage is: 
 
 E   L   =L I   2 /2 =R   0    I   2    T (1 −a )/2= E   0 (1 −a )/2 
 
 The current pulse through the load resistor has an exponential-decay shape: 
 
 i=I (1−exp(− t R/L )) 
 
 where exp( ) denote the exponential function and t is the time elapsed from the moment SW 1  opened and SW 2  closed. When compared to the rectangular shape produced by pulse-shortening, the exponential shape smooths the zeros in the frequency response and therefore gives better performance at high frequencies. The steeper the exponential descend the flatter the output spectrum. 
 
 The energy transferred from L to the load R in the second stage is: 
 
 E   R   =E   L (1−exp(−2  a T R/L ))= E   L (1−exp(−2  a /(1 −a ) R/R   0 )) 
 
 E R  can be rewritten as: 
 
 E   R   =E   0 (1− a )/2(1−exp(−2  a /(1 −a ) R/R   0 )) 
 
 For any given a, one can always choose a load resistor R such that exp(−2 a/(1−a) R/R 0 ) is arbitrarily close to zero. Larger R values will give sharper exponential descend and better energy transfer from L to R. Also, for the purpose of the present embodiment of the invention, we expect a to be less than ½ (actually much less than). Thus, with a desired design, E R  will not be less than E 0 /4. At the same time E R  is always less than E 0 /2. Recall that E 0  is the energy delivered by DAC over one sample into an optimal load R 0  according to the known method. We see that, using the pulse shaping method disclosed herein, one can use arbitrarily short pulses (small a values) and maintain the output signal power within 3-6 dB of the power delivered by the known conversion method. Note also that energy efficiency limit (1−a)/2 increases while a decreases, which means that efficiency levels closer to 3 dB can be obtained for smaller a. 
 
         [0038]     Referring to  FIG. 6  there is illustrated a typical voltage-output digital-to-analog converter (DAC). With a voltage-output DAC as shown in  FIG. 6 , the output voltage V at a given moment is proportional with the last sample value written into the DAC as long as the current at the DAC output is less than a certain limit I max . This current limitation ensures proper operation of the controlled voltage source at the DAC output. Knowing I max  and the full-scale voltage V FS  one can calculate the minimum value for the load resistor as: 
 
 R   0   —V   FS   /I   max  
 
 Any resistor value less than R 0  will prevent the DAC output from reaching the full-scale voltage due to current limitation. For each sample, the energy delivered by DAC to the load is: 
 
 E   0   =V   2   /R   0   T  
 
 With a constant V, power delivered to the load is inversely proportional to the load resistance and thus, using a load equal to R 0  maximizes the signal power at the output for the given DAC parameters V FS  and I max . 
 
         [0041]     Referring to  FIG. 7  there is illustrated a digital-to-analog converter (DAC) with pulse-shaping in accordance with a second embodiment of the present invention. The DAC  10  has a data port  12  a clock input  14  and in the output  16 . The output  16  is coupled via first and second switches  30  and  32  to a load resistor  34 . A capacitor  36  is coupled between the first and second switches  30  and  32  and ground.  
         [0042]     In operation, with the pulse shaping method as described with regard to the second embodiment of the present invention, the energy produced by a voltage-output DAC every sample is stored in a capacitor during a first stage and then released from the capacitor to the load during a second stage. The first stage lasts a time (1−a)T while second stage lasts a time aT. The principle of the method is shown in  FIG. 7 . The capacitor  36  having a value C is used to temporarily store the energy output by the DAC  10 . The load resistor  34  has a value R. The switch  30  (SW 1 ) stays open during the first stage and is closed for the second stage. The switch  32  (SW 2 ) is an optional switch that can be used to force the DAC output current to zero during the second stage. If used, SW 2  is closed during the first stage and open during the second stage. If SW 2  is not used, it is replaced by a short-circuit.  
         [heading-0043]     We choose the value C of the capacitor  36 , such that DAC output voltage can reach the full-scale value in less than (1−a)T 
 
 C=I   max    T (1 −a )/ V   FS   =T (1− a )/ R   0  
 
 The energy stored in capacitor during the first stage is: 
 
 E   C   =C V   2 /2= V   2    T (1− a )/(2  R   0 )= E   0 (1 −a )/2 
 
 The current pulse through the load resistor has an exponential-decay shape: 
 
 i=I (1−exp(− t /( R C )) 
 
 where exp( ) denotes the exponential function and t is the time elapsed from the moment SW 1  closed and SW 2  opened. When compared to the rectangular shape produced by pulse-shortening, the exponential shape smoothens the zeros in the frequency response and therefore gives better performance at high frequencies. The steeper the exponential descend the flatter the output spectrum. 
 
 The energy transferred from the capacitor  36 , whose value is C, to the load resistor  34  whose value is R during the second stage is: 
 
 E   R   =E   0 (1−exp(−2  a T /( R C )))= E   C (1−exp(−2  a /(1− a ) R   0   /R )) 
 
 E R  can be rewritten as: 
 
 E   R   =E   0 (1 −a )/2(1−exp(−2  a /(1− a ) R   0   /R )) 
 
 For any given a, one can always choose a load resistor value R such that exp(−2 a/(1−a) R 0 /R) is arbitrarily close to zero. A smaller value of R will give sharper exponential descend and better energy transfer from the capacitor  36  to the resistor  34 . Also, for the purpose of this embodiment of the present invention, we expect a to be less than ½ (actually much less than). Thus, with a desired design E R  should not be less than E 0 /4. At the same time E R  is always less than E 0 /2. Recall that E 0  is the energy delivered by DAC over one sample into an optimal load R 0  according to the standard method. We see that, using the pulse shaping method disclosed herein, one can use arbitrarily short pulses (small a values) and still maintain the output signal power within 3-6 dB of the power delivered by the known conversion method. Note also that energy efficiency limit (1−a)/2 increases while a decreases, which means that efficiency levels closer to 3 dB can be obtained for smaller a values. 
 
         [0050]     Referring to  FIG. 8  there is illustrated a first implementation of the embodiment of  FIG. 5 . The DAC  10  has a data port  12 , a clock input  14  and in the output  16 . The output  16  is coupled to the load resistor  48  through an inductor  42 . A first diode couples ground the output  16  to ground in the forward biased direction. Second and third diodes  44  and  46 , in forward biased direct couple the inductor  42  to a V pulse  input  50  and the load resistor  48 , respectively.  
         [0051]     Most of the high-speed DAC available on market today have a current output.  
         [0052]      FIG. 8  shows a possible implementation of the pulse-shaping for a current-output DAC. When compared to  FIG. 5 , we see that SW 1  is implemented using the high-speed diodes  44  and  46  (D 2  and D 3 ) and that SW 2  is implemented with the high-speed diode  40  (D 1 ). The control of the two switches implemented with diodes is performed via the periodic voltage V PULSE  input at  50 . V PULSE  is negative for a time (1−a)T and positive for a time aT.  
         [0053]     When V PULSE  is negative, the second diode  44  (D 2 ) is forward biased, thus acts like a closed switch. At the same time the first and second diodes  40  and  46  (D 1  and D 3 ) are reversed biased and therefore they act like open switches. Then, the output current of the DAC flows to ground via the inductor  42  and the second diode  44 . The voltage on the load resistor  48  is zero.  
         [0054]     When V PULSE  is positive, the second diode  44  is reversed biased and thus acts like an open switch. The energy stored in the inductor  42  forward biases the third diode  46 , i.e. makes it act like a closed switch, and discharges the inductor through the third diode  46  into the load resistor  48 . The first diode  40  can be forward biased if the current in the inductor  42  exceeds the DAC output-current, in which case the first diode  40  acts like a closed switch, and hence protects the DAC output against negative voltages.  
         [0055]     Referring to  FIG. 9  there is illustrated a second implementation of the embodiment of  FIG. 5 . Many high-speed DACs produced today have differential current output. With such a DAC, there are two current outputs, one sourcing the current I proportional with the last sample value written into DAC and the other one sourcing I FS -I.  FIG. 9  shows a possible implementation of the pulse-shaping for a differential current-output DAC. The pulse-shaping differential output DAC  10 ′ includes an upper branch coupled to an output  16   a  and having a first diode  40   a  coupled to ground, a first inductor  42   a , a second diode  44   a  coupled to a V PULSE  input  50  and a third diode  46   a  coupled to one end of a primary of a k:1 transformer  52  whose center is grounded. DAC  10 ′ similarly includes a lower branch coupled to an output  16   b  and having a fourth diode  40   b  coupled to ground, a second inductor  42   b , a fifth diode  44   b  coupled to the V PULSE  input  50  and a sixth diode  46   b  coupled to the other end of primary of a k:1 transformer  50 . The load resistor  52  is coupled across the secondary of the transformer  50  and has a value R L =R/k.  
         [0056]     When compared to  FIG. 5 , we see that SW 1  is implemented on each branch using two high-speed diodes  44   a ,  46   a  (D 2 , D 3 ) for upper branch and  44   b ,  46   b  (D 5 , D 6 ) for the lower branch. We see also that SW 2  is implemented with one high-speed diode per branch  40   a  (D 1 ) on upper and  40   b  (D 4 ) on lower. Hence, the implementation is similar to that of  FIG. 8 .  
         [0057]     In operation, the control of the two switches on each branch is performed by the periodic voltage V PULSE  applied at the input  50 . V PULSE  is negative for a time (1−a)T and positive for aT. An addition beyond the previous implementation example ( FIG. 8 ), is the transformer  52  used to convert the differential signal to a single ended one. The transformer  52  may have a k:1 impedance ratio that can be used to reduce the effective value of the load resistor by k times, i.e. R L =R/k. This allows us to choose a large R. Recall that a larger R results in better energy transfer from inductors to load and also improves the flatness of the spectrum.  
         [0058]     When V PULSE  is negative, diodes  44   a  and  44   b  (D 2  and Ds) are forward biased and thus they act like closed switches. At the same time all the other diodes are reversed biased and therefore they act like open switches. Then, the output currents of the DAC flows to ground via the first inductor  42   a . (L 1 ) and the second diode  44   a  (D 4 ) for the upper branch and the second inductor  42   b  (L 2 ) and the fifth diode  44   b  (D 5 ) for the lower. The voltage on the load resistor R is zero.  
         [0059]     When V PULSE  is positive, diodes  44   a  and  44   b  (D 2  and D 5 ) are reversed biased and thus they act like an open switches. The energy stored in inductors  42   a  and  42   b  (L 1  and L 2 ) causes diodes  46   a  and  46   b  (D 3  and D 6 ) to become forward biased, i.e. these diodes act like closed switches, and the inductors  42   a  and  42   b  discharge through the primary windings of transformer  50  and coupled into the load resistor  52  via the secondary windings. If the current in inductors exceeds the DAC output-current, diodes  40   a  and  40   b  become forward biased, so that they act like closed switches and hence they protect the DAC outputs against negative voltages.  
         [0060]     Referring to  FIG. 10  there is illustrated a pulse and clock generator for the implementations of  FIGS. 8 and 9 . Both circuits in  FIGS. 8 and 9  require a generator that will produce periodic pulses that have width aT and period T.  FIG. 10  shows a simple solution to obtain these pulses from a clock signal of frequency 1/T. The pulse and clock generator includes a clock input  60  coupled to a buffer  62  (U 1 ) with non-inverted (A) and inverted (B) outputs  64   a  and  64   b , respectively, a first delay  66  coupled to the non-inverting output  64   a  and a second delay  68  coupled to the inverting output  64   b . Optionally three non-inverting buffers  70 ,  72 , and  74  (U 2 , U 3  and U 4 ) may be applied to the out of first delay  66 , the non-inverting output  64   a  and second delay  68 , respectively. The output of buffer  70  is applied as output to a DAC clock output  80 . The output of buffer  72  is capacitively coupled via a capacitor  76  to V pulse  output  82 . The output of buffer  74  is also capacitively coupled via a capacitor  78  to V pulse  output  82 . A V bias  input  86  is coupled via a bias resistor  84  to a V pulse  output  82 .  
         [0061]     In operation, the non-inverted output (A)  64   a  from buffer  62  (U 1 ) is delayed through the first delay  66  and buffer  70  (U 2 ) to produce the clock for DAC (CLK DAC ) at the output  80 . A delayed version of the output of the inverting output  64   b  (B) is added to (A) using U 3 , U 4  and C 1 , C 2  to produce V PULSE  at output  82 . The resistor  84  (R B )) ensures a negative bias for V PULSE . The operation of the pulse and clock generator is detailed in  FIG. 11 . The width of the pulse aT is controlled by the second delay  68 . The first delay  66  is used to ensure proper alignment of CLK DAC  with V PULSE . Note also that the circuit produces both positive and negative pulses with width aT, but only the positive ones are used (negative pulses have no effect).  
         [0062]     Referring to  FIG. 12  there is graphically illustrated the power spectral density (PSD) for a pulse-shaping digital-to-analog converter (DAC) with a=⅙.  FIG. 12  shows the power spectral density (PSD) for a pulse-shaping DAC with a=⅙ and clocked at 100 MHz. The main image is centered at 25 MHz and has approximately 24 MHz bandwidth. Note that the signal level for the main image is reduced by only 4-5 dB compared to an 8 dB reduction obtained with a pulse-shortening DAC. The response at the higher frequencies is also better than with pulse shortening. For example, the image at 825 MHz is attenuated only 18 dB rather than 22 dB and has almost 34 dB SNR. Also note that the zero at 600 MHz (6 times the clock frequency) is smoother then with pulse-shortening. This is a result of the exponential-decay shape used with pulse-shaping. For the image at 825 MHz there is practically no linear distortion.  
         [0063]     Referring to  FIG. 13  there is graphically illustrated the power spectral density (PSD) for a pulse-shaping digital-to-analog converter (DAC) with a={fraction (1/20)}  FIG. 13  shows the power spectral density (PSD) for a pulse-shaping DAC with a={fraction (1/20)} and clocked at 100 MHz. The main image is again centered at 25 MHz and has approximately 24 MHz bandwidth. Note that, for the main image, the signal level is reduced by only 4 dB as opposed to 13 dB obtained with pulse-shortening. Consequently, the SNR is almost 48 dB instead of 38 dB. The benefit of pulse-shaping becomes obvious at higher frequencies which are attenuated less than 4 dB compared to the main image. For example, the image at 825 MHz is attenuated only 7 dB and therefore exhibits almost 45 dB SNR as opposed to 36 dB obtained with the pulse-shortening DAC. As a further advantage, still better performance can be obtained if a is further reduced.