Abstract:
A control device for controlling a switching converter includes a switch controller that generates a control signal with a switching period for controlling switching of a switch of the switching converter and setting a first interval in which a current flows in the switch, a second interval in which energy is transferred onto a storage element of the switching converter, and a third, wait, interval, at the end of the second interval. The duration of the first interval is determined based on a control voltage indicating the output voltage. A pre-distortion stage receives the control voltage and generates a pre-distorted control voltage as a function of the control voltage and a relationship between one of the first and third time intervals and the switching period, wherein the switch controller is configured to control a duration of the first interval based on the pre-distorted control voltage.

Description:
BACKGROUND 
     Technical Field 
       [0001]    The present disclosure relates to a device and a method for quasi-resonant-mode voltage control of a switching converter, in particular (but without this implying any loss of generality) a power-factor-correction converter (in what follows referred to as PFC converter). 
       Description of the Related Art 
       [0002]    As it is known, voltage converters used in switched-mode power supplies 
         [0003]    (SMPSs) or in solid-state lighting (SSL) systems are used to satisfy stringent specifications as regards the corresponding electrical performance. In particular, converters are used to guarantee a high quality factor (with a substantially unit power factor—PF, for example higher than 0.9), and a high efficiency/low power consumption in conditions of absence of load (for example, with a dissipated power of less than 300 mW). 
         [0004]    In general, these power converters are designed to convert a quantity received at the input, for example an AC voltage coming from the electrical mains supply, into a regulated output quantity, for example a DC voltage, to supply an electrical load, for example, a group of LEDs. 
         [0005]    The high power factor, for example, satisfies the limitations to harmonic current emission envisaged by the standards (for example, by the IEC 61000-3-2 standard in Europe, and the JEITA-MITI standard in Japan); whereas high efficiency/low power consumption meet the energy-efficiency specifications, for example ENERGY STAR 2.0 for external power supplies or ENERGY STAR 5.0 for computers and the like. 
         [0006]    In particular, when a high output power is desired (for example, higher than 50-75 W), it is known to use power converters having a two-stage architecture, where a first stage typically defines a PFC converter, for example of a voltage-boost type. The PFC converter in this case carries out an operation of boosting of the AC mains voltage, generating at output a regulated DC voltage, for example having the value of 400 V. The PFC converter is controlled by an appropriate control device for regulating the power factor in the absorption from the electric power mains. 
         [0007]    By way of example,  FIG. 1  shows the electrical diagram of a power converter, for example a PFC converter of a voltage-boost type, designated as a whole by 1, controlled by a corresponding control device, designated by 2 (it is underlined, however, that what follows may apply to different converter topologies, for example of a flyback or buck-boost type). 
         [0008]    The control device  2  is made as an integrated circuit, and has a package and corresponding input and output pins. The integrated circuit may be mounted on a same printed circuit board (PCB) with the circuit components that define the power converter  1 . 
         [0009]    In particular, the power converter  1  has, in this configuration: an input terminal IN, on which an input voltage V in  (rectified sinusoid) is present, generated by a rectifier stage  3  (illustrated schematically) starting from an AC mains voltage V AC , for example supplied by the electrical mains supply; and an output terminal OUT, on which an output voltage V out  is present, for example a DC voltage, of a value higher than the input voltage V IN , which is regulated at a desired value (for example, 400 V). 
         [0010]    A filter capacitor  4   a,  having high-frequency filtering functions, is connected to the input terminal IN, whereas a storage capacitor  4   b,  having charge-storage functions, is connected to the output terminal OUT. Both filter capacitor  4   a  and storage capacitor  4   b  are further connected to a reference, or ground, terminal (GND). 
         [0011]    The power converter  1  comprises: an inductor  5 , connected between the input terminal IN and a first internal node N 1 ; a switch element  6 , in particular a power MOSFET, connected between the first internal node N 1  and the reference terminal; and a diode element  7 , having its anode connected to the first internal node N 1  and its cathode connected to the output terminal OUT. 
         [0012]    The switch element  6  has a first current-conduction terminal, in particular the drain terminal of the respective MOSFET, connected to the first internal node N 1 , a second current-conduction terminal, in particular the source terminal of the respective MOSFET, connected to the reference terminal, and a control terminal, coinciding with the gate terminal of the respective MOSFET. 
         [0013]    A voltage divider  8  is connected between the output terminal OUT and the reference terminal and is formed by a first voltage-divider resistor  8   a,  connected in series to a second voltage-divider resistor  8   b,  defining an internal node N 2  from which a feedback voltage V is taken. 
         [0014]    The power converter  1  further comprises an auxiliary winding  9 , magnetically coupled to the inductor  5  and on which a monitoring voltage V ZCD  is present. 
         [0015]    The control device  2  has: a first input terminal  2   a,  connected to the second internal node N 2  and designed to receive the feedback voltage V FB ; a second input terminal  2   b,  connected to the auxiliary winding  9  by a first coupling resistor  10  and designed to receive the monitoring voltage V ZCD , being a function of the voltage across the auxiliary winding  9 ; and an output terminal  2   c,  connected to the control terminal of the switch element  6  by a second coupling resistor  11  and designed to supply a control signal GD for controlling switching of the same switch element  6  in pulse-width modulation (PWM), with a suitable timing. 
         [0016]    The control device  2  has further terminals  2   d,    2   e  connected to a supply voltage V CC  and to the reference terminal, respectively. 
         [0017]    In particular, the control device  2  may be configured to control operation of the power converter  1  in so-called quasi-resonant mode, also defined as “transition mode”, “critical mode”, or “borderline mode”. 
         [0018]    At each switching cycle, the control device  2  controls closing of the switch element  6  for an interval T ON  (‘ON’ interval of the duty cycle), during which the current coming from the power supply circulates in the inductor  5  and in the switch element  6  towards ground, determining a storage of energy in the same inductor  5 . 
         [0019]    In voltage-control mode, the duration of the on interval T ON  is set by the control device  2  by an appropriate feedback control loop based on a value indicative the output voltage V out , in this case obtained from the feedback voltage V FB , which is compared with an appropriate reference voltage (as described in detail hereinafter). 
         [0020]    In a way not illustrated herein, the control loop may alternatively be based on a peak-current control. 
         [0021]    The control device  2  then controls opening of the switch element  6  for an interval T OFF  (‘OFF’ interval of the duty cycle), during which the energy previously stored in the inductor  5  is transferred to the load, and the charge-storage element  4   b,  via the diode element  7 . 
         [0022]    In particular, upon completion of energy transfer, the current in the inductor  5  is zero. A resonance condition around the value of the input voltage V in  occurs on the voltage at the first internal node N 1 , on account of the capacitance present on the same first internal node N 1 , mainly due to the parasitic capacitance of the drain terminal of the MOSFET of the switch element  6  and to the parasitic capacitance of the diode element  7  (being off). 
         [0023]    According to the quasi-resonant control mode, the switch element  6  is closed (and the corresponding MOSFET is switched on) at the minimum of the resonant oscillation present on the drain voltage of the corresponding MOSFET, with a certain delay with respect to the instant of zeroing of the current in the inductor  5 , so that the converter operates in a condition of switching at zero current and voltage, enabling a high efficiency and minimal on-losses. This control is also referred to as “valley-switching”, in so far as closing of the switch element  6  occurs at the valley of the oscillation of the MOSFET drain voltage. 
         [0024]    Detection of the valley condition, and thus determination of the duration of the off interval T OFF , is made by the control device  2  on the basis of the monitoring voltage V ZCD , which in turn is a function of the voltage across the auxiliary winding  9 . 
         [0025]      FIG. 2  shows the plots, corresponding to the control mode illustrated, of the current I L  in the inductor  5  and of the control signal GD (with the on interval T ON , during which energy is stored in the inductor  5 , and the off interval T OFF  being shown). Further shown are a so-called free-wheeling time interval T FW , in which the inductor current I L  circulates through the diode element  7  (transferring energy onto the storage element  4   b ), and a delay time interval T R , which corresponds to the waiting interval for valley switching, i.e., the interval between the instant when the inductor current I L  goes to zero and the instant when the switch element  6  is closed again. 
         [0026]    With reference to  FIG. 3 , a more detailed description of an embodiment, of a known type, of the control device  2 , which implements the control method discussed previously, is now presented. This control device  2  corresponds, for example, to the device coded STCMB1, produced and marketed by the present Applicant. 
         [0027]    The control device  2  comprises an error-amplifier stage  12 , having an inverting input terminal, which is connected to the first input terminal  2   a  and receives the feedback voltage V FB , and a non-inverting input terminal, which receives a reference voltage V REF , of an appropriate value (for example, generated within the control device  2  by a band-gap generator starting from the supply voltage V CC ); the error-amplifier stage  12  generates, as a function of the difference between the feedback voltage V FB  and the reference voltage V REF , a control voltage V C , indicative of the value of the output voltage V out  of the power converter  1 . 
         [0028]    In a way not described in detail, a compensation network, of an RC type, is coupled to the output of the error-amplifier stage  12 , designed to define the DC gain of the error-amplifier stage  12  and the corresponding operating frequency bandwidth, ensuring stability of the control loop. 
         [0029]    The control device  2  further comprises a comparator stage  15 , having a first comparison terminal, which is coupled to the output of the error-amplifier stage  12 , and receives the control voltage V C , a second comparison terminal, which receives a ramp voltage V R , and an output, which generates a comparison signal S C . 
         [0030]    In particular, the ramp voltage V R  is generated by charging of a capacitor  16 , having capacitance C, with an appropriate, constant, charging current I C  generated by a current generator  17 . A switch  18 , controlled by a control signal SW, is further connected in parallel to the capacitor element  16 , to determine start of charging and subsequent discharging thereof (and thus the alternately ascending and descending pattern of the ramp voltage V R ). 
         [0031]    The control device  2  further comprises an S/R flip-flop  19 , having: a reset input R, which is connected to the output of the comparator stage  15  and receives the comparison signal S C ; a set input S connected to a timing stage  20 ; a negated output Q, which defines the aforesaid control signal SW of the switch  18 ; and an output Q, which supplies, via a driver unit  21 , the control signal GD for controlling switching of the switch element  6  of the power converter  1 . 
         [0032]    The timing stage  20  comprises a detection unit  26 , which is coupled to the second input  2   b  of the control device  2  and receives the monitoring voltage V ZCD . The detection unit  26  generates a detection signal ZCD indicating onset of the zero-current condition in the inductor  5 . 
         [0033]    The timing stage  20  further comprises: a delay unit  22 , which is connected to the output of the detection unit  26  and is configured to apply an appropriate time delay to the detection signal ZCD; an OR logic gate  24 , having a first input connected to the output of the delay unit  22 , a second input connected to a starter unit  25 , and an output, which supplies the set signal S to the S/R flip-flop  19 . 
         [0034]    During operation, considering the bandwidth of the error-amplifier stage  12  being sufficiently narrow, for example less than 20 Hz, the control voltage V C  may be considered substantially constant (i.e., a DC value) over a mains cycle. 
         [0035]    The peak value V R   _   pk  of the ramp voltage V R  may be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       R 
                        
                       
                           
                       
                        
                       _ 
                        
                       
                           
                       
                        
                       p 
                        
                       
                           
                       
                        
                       k 
                     
                   
                   = 
                   
                     
                       
                         I 
                         C 
                       
                       C 
                     
                      
                     
                       T 
                       ON 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0036]    Assuming that the switch element  6  is initially on, the ramp voltage V R  increases until it reaches the value of the control voltage V C , thus switching the output of the comparator stage  15 , which resets the S/R flip-flop  19  and causes opening of the same switch element  6 . 
         [0037]    Consequently, the output of the comparator stage  15  determines the duration of the on interval T ON  of the switch element  6 , according to the expression: 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                     ON 
                   
                   = 
                   
                     
                       C 
                       
                         I 
                         
                           C 
                            
                           
                               
                           
                         
                       
                     
                      
                     
                       V 
                       C 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    which has been obtained starting from the aforesaid Eq. (1) by setting: V R pk =V C . 
         [0038]    It should be noted that, on the aforesaid hypothesis of the control voltage V C  being constant, also the duration of the on interval T ON  is substantially constant during each mains period. 
         [0039]    After opening of the switch element  6 , the inductor  5  transfers the energy accumulated onto the storage capacitor  4   b  and to the load, until it is completely demagnetized. At that point, the diode element  7  stops conducting, and the voltage on the first internal node N 1 , and thus the drain voltage of the MOSFET, is floating. 
         [0040]    This voltage would tend to reach the instantaneous mains voltage via the oscillation due to the resonant coupling between the corresponding parasitic capacitance and the inductance of the inductor  5 . 
         [0041]    However, the sudden drop in voltage that occurs on the aforesaid first internal node N 1  following upon demagnetization of the inductor  5  is detected by the detection unit  26  of the timing stage  20 , which generates a pulse, upon detection of a falling edge of the monitoring voltage V ZCD . 
         [0042]    This pulse in the detection signal ZCD, appropriately delayed by the delay unit  22  as a function of the delay time interval T R , thus sets the S/R flip-flop  19  and closes the switch element  6  again, thus determining a new operating cycle of the power converter  1 . 
         [0043]    In this way, the control method envisages that start of each new switching cycle occurs after the current in the inductor  5  has reached a zero level, after an appropriate delay. 
         [0044]    It should be noted that the presence of the OR logic gate  24  in the timing stage  20  enables start of a new operating cycle, for example, in the start-up phase (or upon return from a deactivation condition), when the monitoring voltage V ZCD  at the second input  2   b  of the control device  2  is not yet present. This feature further enables the power converter  1  not to stop in the case where, for any reason, the same monitoring voltage V ZCD  is not present on the second input  2   b.    
         [0045]    In greater detail, and with reference also to the diagrams of  FIG. 4  (which shows the main electrical quantities in the control device  2 ), the input voltage V IN  may be considered substantially a rectified sinusoid, i.e., V IN (θ)=V IN,pk |sin θ|, where θ ∈ (0, π). 
         [0046]    The peak value I L   _   pk  of the inductor current I L  is thus given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         L 
                          
                         
                             
                         
                          
                         _ 
                          
                         
                             
                         
                          
                         p 
                          
                         
                             
                         
                          
                         k 
                       
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           IN 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                        
                       
                         T 
                         ON 
                       
                     
                     L 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0047]    Substituting Eq. (2): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         L 
                          
                         
                             
                         
                          
                         _ 
                          
                         
                             
                         
                          
                         p 
                          
                         
                             
                         
                          
                         k 
                       
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           IN 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       L 
                     
                      
                     
                       C 
                       
                         I 
                         C 
                       
                     
                      
                     
                       V 
                       C 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0048]    As may be noted from the diagrams of  FIG. 2 , the switching period T(θ) of the power converter  1  may be expressed as: 
         [0000]        T (θ)= T   ON   +T   FW (θ)+ T   R    (5)
 
         [0000]    where the sum T FW (θ)+T R  constitutes the off interval T OFF . 
         [0049]    Furthermore, the input current I IN  of the power converter  1  may be determined by averaging the inductor current I L (t,θ) over one switching cycle. Once again with reference to  FIG. 2 , it may be immediately verified that the following equation applies: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       IN 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       
                         I 
                         
                           L 
                            
                           
                               
                           
                            
                           _ 
                            
                           
                               
                           
                            
                           p 
                            
                           
                               
                           
                            
                           k 
                         
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                         
                     
                      
                     
                       
                         
                           T 
                           ON 
                         
                         + 
                         
                           
                             T 
                             FW 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0050]    Substituting in Eq. (6) the previous Eqs. (4) and (5): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       IN 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       C 
                       
                         I 
                         
                           C 
                            
                           
                               
                           
                         
                       
                     
                      
                     
                       
                         V 
                         
                           IN 
                           , 
                           
                             p 
                              
                             
                                 
                             
                              
                             k 
                           
                         
                       
                       L 
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                      
                     
                         
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         
                           T 
                           ON 
                         
                         + 
                         
                           
                             T 
                             FW 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                       
                         
                           T 
                           ON 
                         
                         + 
                         
                           
                             T 
                             FW 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         + 
                         
                           T 
                           
                             R 
                              
                             
                                 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0051]    From Eq. (7) it emerges in particular that the input current is purely sinusoidal (thus guaranteeing an ideally unitary power factor and an ideally zero distortion) only in the case where the delay time interval T R  is zero or substantially negligible. 
         [0052]    However, it is known that there are several situations and applications in which, in order to maximize efficiency of the power converter, one can lengthen the delay time interval T R , which thus may not be zero. 
         [0053]    For example, so-called valley-skipping control techniques, of a known type, envisage that, in conditions of medium or low load, one or more of the valleys of the monitoring voltage V ZCD  are skipped for the purposes of the control operations so as to limit the switching frequency. 
         [0054]    On the basis of what has been discussed previously, however, the increase of the delay time interval T R  entails an increase of the distortion characteristics (the so-called THD—Total Harmonic Distortion—factor) of the power converter, and in particular an increase in the harmonic current emission, which may not allow to achieve the expected performance (for example, a THD of less than 10% may be desired). 
         [0055]    In other words, existing control solutions involve a compromise between the characteristics of distortion and the characteristics of efficiency that is possible to achieve, in particular in operating conditions of medium or low load. 
       BRIEF SUMMARY 
       [0056]    One or more embodiments of the present disclosure solve the problems highlighted above and in particular provide a control solution that make it possible to combine the advantageous effects of the control techniques discussed previously, which instead envisage maximization of efficiency (by appropriate lengthening of the delay time interval T R ) or, alternatively, minimization of the harmonic current emission. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0057]    For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein: 
           [0058]      FIG. 1  shows a general circuit diagram of a power converter and of a corresponding control device, of a known type; 
           [0059]      FIG. 2  shows diagrams of electrical quantities associated to the power converter of  FIG. 1 ; 
           [0060]      FIG. 3  shows a more detailed block diagram of a control device of the power converter of  FIG. 1 ; 
           [0061]      FIG. 4  shows diagrams of electrical quantities in the control device of  FIG. 3 ; 
           [0062]      FIG. 5  shows a block diagram of a control device of a switching converter, for example of the type illustrated in  FIG. 1 , according to one embodiment of the present solution; 
           [0063]      FIG. 6  shows diagrams of electrical quantities in the control device of  FIG. 5 ; 
           [0064]      FIG. 7  is a circuit diagram of a current generator in the control device of  FIG. 5 ; 
           [0065]      FIGS. 8 and 9  show plots of electrical quantities of the control device of  FIG. 3  and of  FIG. 5 , respectively; 
           [0066]      FIG. 10  is a general block diagram of an electronic device that uses a power converter; 
           [0067]      FIG. 11  shows a circuit diagram of a power converter and of a corresponding control device, according to a further embodiment of the present solution; 
           [0068]      FIG. 12  shows diagrams of electrical quantities in the power converter of  FIG. 11 ; 
           [0069]      FIG. 13  shows diagrams of electrical quantities corresponding to yet a further embodiment of the present solution; 
           [0070]      FIG. 14  shows a circuit diagram of a control device of a power converter, according to the aforesaid further embodiment of the present solution; and 
           [0071]      FIG. 15  shows plots of electrical quantities in the control device of  FIG. 14 . 
       
    
    
     DETAILED DESCRIPTION 
       [0072]    Considering that the switching period may be expressed as T(θ)=T ON (θ)+T FW (θ)+T R , and that the on time interval T ON (θ) depends on the instantaneous mains phase angle θ (where 0≦θ=2πf L t≦π, f L  being the mains frequency), being in fact not necessarily constant as in traditional solutions, the aforesaid Eq. (7) may be rewritten as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       IN 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       C 
                       
                         I 
                         
                           C 
                            
                           
                               
                           
                         
                       
                     
                      
                     
                       
                         V 
                         
                           IN 
                           , 
                           
                             p 
                              
                             
                                 
                             
                              
                             k 
                           
                         
                       
                       L 
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                      
                     
                         
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                         
                     
                      
                     
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0073]    As will be discussed in detail, one aspect of the present solution stems from the realization, by the present Applicant, that, in the aforesaid Eq. (8) a distortion factor may be recognized, associated to the operation of averaging in the switching period and causing a distortion in the value of the input current I IN (θ). 
         [0074]    This distortion factor is given by the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       T 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     - 
                     
                       T 
                       R 
                     
                   
                   
                     T 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0000]    and is thus linked to the switching operation and depends on the values of the time intervals T ON , T FW , and T R . This distortion factor intervenes in the aforesaid Eq. (8) as a multiplying factor, depending on the phase angle θ, thus distorting the plot, which would otherwise be sinusoidal, of the input current I IN . 
         [0075]    One aspect of the present solution consequently envisages an appropriate compensation of the aforesaid distortion by pre-distorting the value of the control voltage V C  by a pre-distortion factor given by the inverse of the aforesaid distortion factor, i.e., given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     - 
                     
                       T 
                       R 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0076]    This term, corresponding to the inverse of the distortion term introduced by the averaging operation described previously, thus enables the effects of distortion thereof to be substantially cancelled out, given that the control voltage V C  intervenes in the aforesaid Eq. (8) as a multiplying factor of the input current I IN . 
         [0077]    The control method thus envisages generation of a pre-distorted control voltage V CT (θ) starting from the control voltage V C , given by the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       CT 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       KV 
                       C 
                     
                      
                     
                         
                     
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where K is an appropriate constant, and V C  is the control voltage originally provided in the control device  2  (in the case illustrated previously, the voltage present at the output of the error-amplifier stage  12 ) in order to determine the duration of the on interval T ON . 
         [0078]    Considering Eq. (8) and substituting therein the expression for the pre-distorted control voltage V CT (θ), the following expression is obtained, once the distortion factor has been eliminated with the aforesaid pre-distortion factor, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       IN 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       C 
                       
                         I 
                         C 
                       
                     
                      
                     
                       
                         V 
                         
                           IN 
                           , 
                           pk 
                         
                       
                       L 
                     
                      
                     
                       KV 
                       C 
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    which is a perfect sinusoid, in particular independent of the duration of the delay time interval T R  (and, equivalently of the on and free-wheeling intervals T ON  and T FW ). 
         [0079]    With reference to  FIG. 5 , a description of a possible embodiment of a control device  30 A according to the present solution is now made. It should be noted that, in general, the control device  30 A is realized in a way equivalent to the control device  2  described previously, and may also be used, for example, in a power converter  1 , for instance a PFC converter of a voltage-boost type, having a configuration equivalent to the one discussed with reference to  FIG. 1 . It is, however, emphasized that what illustrated herein, as on the other hand highlighted also hereinafter, may find advantageous application also in other topologies of power converters and in different configurations of the corresponding control device. 
         [0080]    As is shown in the aforesaid  FIG. 5 , the control device  30 A differs from the control device  2  described previously owing to the presence of a pre-distortion stage  32 , set between the output of the error-amplifier stage  12  and the inverting input of the comparator stage  15 . 
         [0081]    In particular, the pre-distortion stage  32  has an input  32   a,  which is connected to the output of the error-amplifier stage  12  and receives the control voltage V C , and an output  32   b,  which supplies the pre-distorted control voltage V CT (θ) to the inverting input terminal of the comparator stage  15 . 
         [0082]    The pre-distortion stage  32  comprises a controlled current generator  34 , having a control input, which is coupled to the input  32   a  of the pre-distortion stage  32  and receives the control voltage V C . This controlled current generator  34  generates at the output, on a charging node N i , a charging current I CH , the value of which is a function of the control voltage V c , according to the expression: 
         [0000]        I   CH (θ)= G   M   V   C    (13)
 
         [0000]    where G M  is the voltage/current gain of the controlled current generator  34 . 
         [0083]    As illustrated, the controlled current generator  34  further has a supply input, which receives, for example, the supply voltage V CC  of the power converter  1 . 
         [0084]    The pre-distortion stage  32  further comprises a charging capacitor  36 , connected between the node N i  and the reference terminal. 
         [0085]    It should be noted that, depending on the applications, the charging capacitor  36  may be integrated with the other circuit elements of the control device  30 A (being, that is, obtained within the same die and/or package); or else, the charging capacitor  36  may be a discrete component, electrically connected to an input terminal of the control device  30 A. In the latter case, the charging node N i  constitutes a further input terminal of the control device  30 A. 
         [0086]    The control device  30 A further comprises: 
         [0087]    a discharge resistor  38 , connected to the charging node Ni and further, via a discharge switch  39 , to the reference terminal. 
         [0088]    The discharge switch  39  receives, as a control signal, the negated signal  ZCD , which constitutes the negated version of the detection signal ZCD generated by the detection unit  26 , indicating onset of the zero-current condition in the inductor  5 . 
         [0089]    In use, the discharge resistor  38  is connected in parallel to the charging capacitor  36 , when the negated signal  ZCD  is high, i.e., during the time interval T(θ)−T R  in which the inductor  5  is magnetized (see also the subsequent  FIG. 6 ), i.e., when the inductor current I L  is non-zero. 
         [0090]    The same discharge resistor  38  is, instead, disconnected and decoupled from the charging capacitor  36  when the negated signal  ZCD  is low, i.e., when the inductor  5  is demagnetized and the inductor current I L  is zero. 
         [0091]    Consequently, the charging capacitor  36  charges during the delay time interval T R  in which the inductor  5  is demagnetized, whereas it discharges during the remaining time interval of the switching period (T ON (θ)+T FW (θ)), in which the inductor  5  is magnetized by the inductor current I L . 
         [0092]    In other words, discharge of the charging capacitor  36  occurs during the time interval, in the switching period T, in which the inductor current I L  is non-zero. 
         [0093]    The voltage across the charging capacitor  36  is the pre-distorted control voltage V CT (θ) that is supplied to the inverting input terminal of the comparator stage  15  (it should be noted that no modification is, instead, made to the circuit components connected to the non-inverting terminal of the same comparator stage  15 ). 
         [0094]    On the hypothesis that the control voltage V C  is substantially constant during a mains half-period (as discussed previously), also the charging current I CH (θ) is substantially constant. 
         [0095]    In particular, for the following considerations, it is assumed that the following expression applies: 
         [0000]        T (θ)&lt;&lt; R   T   C   T &lt;&lt;1/ f   L    (14)
 
         [0000]    where f L  is the mains frequency; i.e., it is assumed that the switching period is much lower than the time constant R T C T  defined by the discharge resistor  38  and the charging capacitor  36 , and that the same time constant R T C T  is much lower than the mains period. If this assumption is valid, the ripple of the switching frequency on the charging capacitor  36  is negligible. Further, the charging current I CH (θ) is substantially constant during each mains half-period. 
         [0096]    Applying the charge-balance relation on the charging capacitor  36  (considering that the charging current I CH  flows towards the charging capacitor  36  throughout the period T(θ) and that discharge towards the reference terminal occurs during the interval T(θ)−T R ), the following expression may be obtained: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         I 
                         CH 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                       T 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           CT 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         R 
                         T 
                       
                     
                      
                     
                       [ 
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
         [0097]    Substituting in Eq. (15), Eq. (13) for the charging current I CH (θ), and solving with respect to the pre-distorted control voltage V CT (θ), the following expression is obtained: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       CT 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       G 
                       M 
                     
                      
                     
                       R 
                       T 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
         [0000]    which has the same form as Eq. (11), and thus satisfies the control target, with the constant K given by: 
         [0000]      K=G M R T    (17)
 
         [0098]    It may thus be concluded that the solution proposed makes it possible to obtain an input current I IN  that is always sinusoidal, in particular even in the case where the delay time interval T R  is non-zero. 
         [0099]    As mentioned previously, in the solution proposed, the on interval T ON  is not constant, as in traditional solutions, but depends upon the instantaneous mains phase θ, according to the expression 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       T 
                       ON 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       C 
                       
                         I 
                         C 
                       
                     
                      
                     
                       G 
                       M 
                     
                      
                     
                       R 
                       T 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
           
         
       
     
         [0100]    In a way similar to what has been shown previously in  FIG. 4 ,  FIG. 6  shows the main electrical quantities in the control device  30 A, the plot of which reflects what has been illustrated previously. 
         [0101]    With reference to  FIG. 7 , a possible circuit embodiment of the controlled current generator  34  is now discussed, in this case comprising an operational amplifier  40 , having its non-inverting terminal that is connected to the control input of the controlled current generator  34  and receives the control voltage V C , its output terminal connected to the base terminal of a transistor  41 , and its inverting terminal connected to the emitter terminal of the same transistor  41 . 
         [0102]    The controlled current generator  34  further comprises: a resistor  43 , connected between the aforesaid emitter terminal of the transistor  41  and the reference terminal; and a current mirror  44 , constituted, in a per se known manner (not described in detail herein), by a pair of transistors  44   a,    44   b.    
         [0103]    In particular, a first branch of the current mirror  44  is connected to the collector terminal of the transistor  41 , whereas a second branch of the current mirror  44  is connected to the output of the controlled current generator  34 , to supply the charging current I CH . 
         [0104]    It may be immediately verified that, in this solution, the charging current I CH  is given by the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     CH 
                   
                   = 
                   
                     s 
                      
                     
                       
                         V 
                         C 
                       
                       
                         R 
                         M 
                       
                     
                   
                 
               
               
                 
                   ( 
                   19 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where R M  is the resistance of resistor  43 , and s is the mirroring factor of the current mirror  44 . 
         [0105]    It follows that the aforesaid voltage/current gain G M  is in this case given by 
         [0000]    
       
         
           
             
               
                 
                   
                     G 
                     M 
                   
                   = 
                   
                     s 
                     
                       R 
                       M 
                     
                   
                 
               
               
                 
                   ( 
                   20 
                   ) 
                 
               
             
           
         
       
     
         [0106]    The present Applicant has tested and validated the solution proposed by several simulations and experimental tests. 
         [0107]    By way of example,  FIGS. 8 and 9  provide a comparison between the performance of a control device according to the known art (in particular, the control device  2  of  FIG. 3 ), shown in  FIG. 8 , and the performance of the control device  30  according to the present solution, shown in  FIG. 9 . 
         [0108]    In both cases, the power converter operates at half load, and the valley-skipping mode is enabled in order to increase efficiency. 
         [0109]    It may be immediately verified that the solution proposed enables drastic reduction of the waveform distortion, obtaining a substantial reduction of the distortion factor THD, from approximately 29% (in the traditional solution) to approximately 10% (in the proposed solution). 
         [0110]    As mentioned previously, the power converter  1  and the corresponding control device  30 A may advantageously be used in a switching power supply  50 , as illustrated in  FIG. 10 . 
         [0111]    In particular, the switching power supply  50  comprises the rectifier stage  3  (for example, of the diode-bridge type), connected to the electrical mains supply  52 , in the example via an EMI filter  53 , and the input capacitor element  4   a,  connected to the output of the rectifier stage  3 , on which the input voltage V IN  is present. 
         [0112]    The switching power supply  50  further comprises the power converter  1 , having its input terminal IN connected to the input capacitor element  4   a  and its output terminal OUT connected to the charge-storage element  4   b,  as previously defined. 
         [0113]    The control device  30 A controls operation of the power converter  1  for ensuring a desired power factor in the absorption from the electrical mains supply  52 . 
         [0114]    The switching power supply  50  further comprises an output power converter  56 , in the example of a DC/DC type, having its input connected to the output capacitor element  4   b  and designed to supply to a load or final user (not illustrated) a desired value of output voltage, for example with a value that is appropriately reduced with respect to the value of the output voltage V OUT . 
         [0115]    The advantages of the solution proposed emerge clearly from the foregoing description. 
         [0116]    In any case, it is once again emphasized that the present solution allows to overcome the limits of control solutions of a known type, making it possible to obtain, among other features, an ideally sinusoidal input current I IN  and in any case a distortion factor of less than 10%. 
         [0117]    At the same time, the control solution proposed enables use, without any repercussions, of control techniques aimed at maximizing the efficiency in any load condition (such as the valley-skipping techniques, or in general techniques that envisage an appropriate duration, even lengthened, of the delay time interval T R ). 
         [0118]    Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure. 
         [0119]    In particular, it is once again emphasized that, even though in the foregoing description explicit reference has been made to a converter of a boost type, the present solution may advantageously be applied also to other topologies of converters, not only for power-factor-control applications. 
         [0120]    In this regard,  FIG. 11  shows the application of the solution proposed to a power converter, designated by  1 ′, of a flyback type. 
         [0121]    In order not to burden the present discussion, the circuit configuration of the power converter  1 ′, which is of a known type, is not described in detail, but it is only highlighted that the solution previously described finds similar application also in this power converter  1 ′, with some differences due to the different circuit topology thereof. 
         [0122]    In particular, in this case, the primary winding of the transformer of the flyback converter corresponds to the inductor  5  of the boost converter (and for this reason is designated by the same reference number); the inductor current I L  flows in this case through the inductor element constituted by this primary winding. 
         [0123]    The control voltage V C  is in this case obtained starting from a feedback current I FB , which is drawn from an insulated secondary winding  60  of the transformer of the power converter  1 ′. This feedback current I FB  generates, in a control resistor  51 , connected between the supply terminal and the first input terminal  2   a  of the control device  30 B, the control voltage V C . 
         [0124]    In a way altogether similar to what has been described previously, the control voltage V C  is pre-distorted by the pre-distortion stage  32  to generate the pre-distorted control voltage V CT (θ). The pre-distortion stage  32  is obtained in a way altogether similar to what has been discussed previously, with the only difference that the discharge switch  39  is controlled in this case by the signal Q of the S/R flip-flop  19 . 
         [0125]    In fact, in this case, as will be evident to a person skilled in the field, the distortion factor associated to the averaging operation of the inductor current I L  during the switching period, is given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       T 
                       ON 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     T 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   21 
                   ) 
                 
               
             
           
         
       
     
         [0126]    It should be noted that in this case this distortion factor is linked, to the duration of the first time interval T ON  with respect to the switching period T(θ). In fact, also assuming a negligible delay time interval TR, the distortion factor is not zero (T ON /T). 
         [0127]    The discharge switch  39  is in this case closed when the signal Q is high (and the control signal GD is also high), i.e., during the on interval T ON , whereas it is off when the signal Q is low (and the control signal GD is also low), i.e., during the off interval T OFF  of the switching period T(θ). 
         [0128]    Also in this case, the discharge of the charging capacitor  36  occurs during the time interval, in the switching period T, during which the current I L  is non-zero (with the current I L  that flows, in this case, through the inductor element  5  constituted by the primary winding of the transformer). 
         [0129]    It follows that, in this embodiment, the pre-distortion factor by which the control voltage V C  in the pre-distortion stage  32  is multiplied is given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     T 
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   
                     
                       T 
                       ON 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   22 
                   ) 
                 
               
             
           
         
       
     
         [0130]    For completeness, hereinafter all the significant equations relating to this further embodiment are in any case provided. Moreover, in a way similar to what has been discussed previously,  FIG. 12  shows the main electrical quantities in the power converter  1 ′. 
         [0131]    Applying, as discussed previously, considerations of charge balance with respect to the charging capacitor  36  of the pre-distortion stage  32 : 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         I 
                         CH 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                       T 
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           CT 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         R 
                         T 
                       
                     
                      
                     
                       
                         T 
                         ON 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   23 
                   ) 
                 
               
             
           
         
       
     
         [0132]    Considering that also in this case the aforesaid Eq. (13) is valid, the following expression is obtained: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       CT 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       G 
                       M 
                     
                      
                     
                       R 
                       T 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   24 
                   ) 
                 
               
             
           
         
       
     
         [0133]    Moreover, considering that V R   _   pk =V CT (θ) for the comparator stage  15  and also Eq. (2) discussed previously, it is obtained: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       T 
                       ON 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       G 
                       M 
                     
                      
                     
                       R 
                       T 
                     
                      
                     
                       C 
                       I 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   25 
                   ) 
                 
               
             
           
         
       
     
         [0134]    Substituting the aforesaid Eq. (25) in Eq. (3), the peak value of the inductor current is given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         L 
                          
                         _ 
                          
                         pk 
                       
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           IN 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       L 
                     
                      
                     
                       G 
                       M 
                     
                      
                     
                       R 
                       T 
                     
                      
                     
                       C 
                       I 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   26 
                   ) 
                 
               
             
           
         
       
     
         [0135]    The input current of the power converter, obtained by averaging the inductor current I L (t,θ) over a switching period, is in this case given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       IN 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       
                         I 
                         
                           L 
                            
                           _ 
                            
                           pk 
                         
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         T 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   27 
                   ) 
                 
               
             
           
         
       
     
         [0136]    Substituting Eq. (26) and considering that the expression V IN (θ)=V IN,pk |sin θ| is once again valid: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       in 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           G 
                           M 
                         
                          
                         
                           R 
                           T 
                         
                       
                       
                         2 
                          
                         
                             
                         
                          
                         L 
                       
                     
                      
                     
                       C 
                       I 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       V 
                       
                         in 
                         , 
                         pk 
                       
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     θ 
                   
                 
               
               
                 
                   ( 
                   28 
                   ) 
                 
               
             
           
         
       
     
         [0137]    As desired, this current is sinusoidal in all conditions, irrespective, in particular, of the duration of the delay time interval T R . 
         [0138]    Even though it will not be discussed in detail, it will at this point be evident how the solution discussed may find advantageous applications also in further topologies of power converters, for example of the buck-boost, SEPIC, Ćuk, zeta (inverse SEPIC) type and corresponding variants, for example in all converters that have a conversion, or gain, factor between the input and the output of the type: 
         [0000]    
       
         
           
             
               M 
                
               
                 ( 
                 D 
                 ) 
               
             
             = 
             
               D 
               
                 1 
                 - 
                 D 
               
             
           
         
       
     
         [0000]    where D is the duty cycle of the switching period, i.e., the ratio between the on interval T ON  and the switching period T. 
         [0139]    A further possible variant of the present solution is now described, once again with reference, by way of example, to the application for a power converter of a voltage-boost type. 
         [0140]    As illustrated in the plots of  FIG. 13 , and as on the other hand will be known to a person skilled in the field, on account of the parasitic capacitance at the drain terminal of the MOSFET that implements the switch element of the power converter, it may happen that the inductor current I L  becomes negative. Consequently, it may happen that the peak value I L   _   pk  of the inductor current I L  is lower than the expected value. 
         [0141]    Known control solutions envisage, to compensate this effect, appropriate increase of the duration of the on interval T ON , for example, by appropriately delaying the start of the ramp of the ramp voltage V R , which starts as soon as the inductor current I L  becomes positive (instead of being thus synchronized with the control signal GD). 
         [0142]    As an alternative to this known technique, the present solution may achieve the desired effect of lengthening the duration of the on interval T ON , by appropriate driving the discharge switch  39  of the pre-distortion stage  32  via a modified version of the negated signal  ZCD , as shown in  FIG. 14 . 
         [0143]    In particular, the discharge switch  39  is in this case driven by a modified driving signal  ZCD , having a duration appropriately lengthened with respect to the negated signal  ZCD . 
         [0144]    As shown in the plots of the aforesaid  FIG. 13  and also of  FIG. 15 , the duration of the modified driving signal is appropriately lengthened with respect to the negated signal  ZCD , in this way making it possible to obtain an increase of the pre-distorted control voltage V CT  and, thus, a desired increase of the on interval T ON . 
         [0145]    In this example, the modified driving signal  ZCD_E  may be obtained by comparing the inductor current with a positive threshold TH; in particular, the modified driving signal  ZCD_E  switches upon crossing of the threshold TH by the inductor current I L . 
         [0146]    Finally, it is emphasized that the power converter could be supplied also by a power-supply source different from the electrical mains supply. Also, the converter according to the present solution may advantageously provide a voltage regulator or converter, to which the foregoing treatment has made explicitly reference, by way of non-limiting example, or a current regulator or converter (for example, in driver devices for LEDs or in battery chargers). 
         [0147]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.