Abstract:
A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines respectively connected to the memory cells, a plurality of first and second word lines respectively connected to the memory cells, a plurality of first drivers for driving the first word lines selected during a read operation, and a plurality of second drivers for driving the second word lines selected during a write operation, the second driver having a different drive capability from the first driver&#39;s.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-151430 filed on Jun. 25, 2009, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a semiconductor memory device. 
       BACKGROUND 
       [0003]    Examples of a memory embedded in a large scale integrated circuit (LSI) include a semiconductor memory device such as a static random access memory (SRAM). Examples of an SRAM includes a 1-read 1-write (1R1W)-SRAM, a 2-read 1-write (2R1W)-SRAM, and so forth in terms of configuration of a read port and a write port. 
         [0004]      FIG. 1  is a diagram illustrating a configuration of an example of a 2R1W-SRAM. In  FIG. 1 , BL_ 0 L, BL_ 0 R, BL_ 1 L, and BL_ 1 R denote bit lines. In  FIG. 1 , WL_ 0 L, WL_ 0 R, W_ 1 L, and W_ 1 R denote word lines. In  FIGS. 1 ,  1 - 00 ,  1 - 01 ,  1 - 10 , and  1 - 11  (MC 00 , MC 01 , MC 10 , and MC 11 ) denote memory cells that are provided in a memory cell array  1 . In  FIG. 1 ,  2 - 0 L,  2 - 0 R,  2 - 1 L, and  2 - 1 R are word line drivers that drive the word lines WL_ 0 L, WL_ 0 R, W_ 1 L, and W_ 1 R, respectively. In  FIG. 1 , only the four memory cells  1 - 00 ,  1 - 01 ,  1 - 10 , and  1 - 11  provided in the memory cell array  1  are illustrated for simplicity of description. Two word lines WL_xL and WL_xR and two bit lines BL_xL and BL_xR are connected to each memory cell MC. For example, the two word lines WL_ 0 L and WL_ 0 R and the two bit lines BL_ 0 L and BL_ 0 R are connected to the memory cell  1 - 00 . The word line drivers  2 - 0 L,  2 - 0 R,  2 - 1 L, and  2 - 1 R have the same configuration and the same occupied area. 
         [0005]      FIG. 2  is a diagram illustrating a configuration of the memory cell  1 - 00  illustrated in  FIG. 1 . In  FIG. 2 , Vdd denotes a power-supply voltage, and Vss denotes the ground voltage. The other memory cells  1 - 01 ,  1 - 10 , and  1 - 11  have the same configuration of the memory cell  1 - 00 . The memory cell  1 - 00  has six transistors Tr 1  to Tr 6 . 
         [0006]      FIG. 3  is a diagram illustrating a configuration of an example of a 1R1W-SRAM. In  FIG. 3 , BL_ 0 L, BL_ 0 R, B_ 1 L, and BL_ 1 R denote bit lines. In  FIG. 3 , WL_ 0  and W_ 1  denote word lines. In  FIGS. 3 ,  11 - 00 ,  11 - 01 ,  11 - 10 , and  11 - 11  (MC 00 , MC 01 , MC 10 , and MC 11 ) denote memory cells that are provided in a memory-cell array  11 . In  FIGS. 3 ,  12 - 0  and  12 - 1  are word line drivers that drive the word lines WL —0 and WL _ 1 , respectively. In  FIG. 3 , only the four memory cells  11 - 00 ,  11 - 01 ,  11 - 10 , and  11 - 11  provided in the memory-cell array  11  are illustrated for simplicity of description. One word line WL_x and two bit lines BL_xL and BL_xR are connected to each memory cell MC. For example, the one word lines WL_ 0  and the two bit lines BL_ 0 L and BL_ 0 R are connected to the memory cell  11 - 00 . The word line drivers  12 - 0  and  12 - 1  have the same configuration and the same occupied area. 
         [0007]      FIG. 4  is a diagram illustrating a configuration of the memory cell  11 - 00  illustrated in  FIG. 3 . In  FIG. 4 , Vdd denotes a power-supply voltage, and Vss denotes the ground voltage. The other memory cells  11 - 01 ,  11 - 10 , and  11 - 11  have the same configuration of the memory cell  11 - 00 . The memory cell  11 - 00  has six transistors Tr 11  to Tr 16 . 
         [0008]    The memory cell  1 - 00  illustrated in  FIG. 2  has the same configuration of the memory cell  11 - 00  illustrated in  FIG. 4 . A cell area occupied by the memory cell  1 - 00  is the same as a cell area occupied by the memory cell  11 - 00 . A read operation is performed by accessing the memory cell  1 - 00  using a pair of one word line and one bit line. In a 2-read operation, two word lines and two bit lines are used. In a 1-read operation, one word line and one bit line are used. When the 1-read operation is performed for the memory cell  1 - 00  illustrated in  FIG. 2 , only the capacitance of one transfer gate (Tr 5  or Tr 6 ) of the memory cell  1 - 00  influences the word line (WL_ 0 L or WL_ 0 R) as a load imposed thereon. Thus, when the 2R1W-SRAM illustrated in  FIG. 1  operates as an SRAM that performs the 1-read operation, the power consumption of the 2R1W-SRAM in a case of the 1-read operation may be reduced, compared with the power consumption of the 1R1W-SRAM illustrated in  FIG. 3  in a case of the 1-read operation. The occupied area of the word line drivers  2 - 0 L and  2 - 0 R that drive the word lines may be reduced, compared with that of the word line driver  12 - 0  illustrated in  FIG. 3 . 
         [0009]    In order to increase a speed at which an operation of an SRAM having a configuration such as the configuration illustrated in  FIGS. 1 and 2  is performed, in particular, in order to increase a speed at which a read operation of the SRAM is performed, it is desirable to sharply increase the potential of word lines. Accordingly, in order to sharply increase the potential of word lines, it is desirable to increase the physical size of word line drivers or to reduce a load imposed on each of the word line drivers by dividing a memory-cell array. Even when either the physical size of word line drivers is increased or a load imposed on each of the work-line drivers is reduced, the area of the entire SRAM is increased, and the power consumption of the SRAM is increased. 
         [0010]    It is desirable for the semiconductor memory device of the related art to realize a high-speed operation without causing the occupied area of a driver section to be increased or causing the power consumption of the entire semiconductor memory device to be increased. 
       [Patent Document 1] Japanese Laid-open Patent Publication No. 2006-269023 
     [Patent Document 2] Japanese Laid-open Patent Publication No. 5-218354 
     [Patent Document 3] Japanese Laid-open Patent Publication No. 6-295588 
     SUMMARY 
       [0011]    According to an aspect of an embodiment, a semiconductor memory device includes a plurality of memory cells, a plurality of bit lines respectively connected to the memory cells, a plurality of first and second word lines respectively connected to the memory cells, a plurality of first drivers for driving the first word lines selected during a read operation, and a plurality of second drivers for driving the second word lines selected during a write operation, the second driver having a different drive capability from the first driver&#39;s. 
         [0012]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0013]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0014]      FIG. 1  is a diagram illustrating a configuration of an example of a 2R1W-SRAM; 
           [0015]      FIG. 2  is a diagram illustrating a configuration of a memory cell illustrated in  FIG. 1 ; 
           [0016]      FIG. 3  is a diagram illustrating a configuration of an example of a 1R1W-SRAM; 
           [0017]      FIG. 4  is a diagram illustrating a configuration of a memory cell illustrated in  FIG. 3 ; 
           [0018]      FIG. 5  is a diagram illustrating a configuration of an example of a semiconductor memory device according to a first embodiment; 
           [0019]      FIGS. 6A and 6B  are graphic charts for explaining the potential of a word line; 
           [0020]      FIGS. 7A and 7B  are plan views for explaining examples of physical layouts of driver sections; 
           [0021]      FIGS. 8A and 8B  are plan views for explaining other examples of the physical layouts of the driver sections; 
           [0022]      FIG. 9  is a diagram illustrating a configuration of an example of a semiconductor memory device according to a second embodiment; 
           [0023]      FIGS. 10A and 10B  are graphic charts for explaining the potential of a word line; 
           [0024]      FIG. 11  is a diagram illustrating a configuration of an example of a semiconductor memory device according to a third embodiment; 
           [0025]      FIGS. 12A and 12B  are graphic charts for explaining the potential of a word line; 
           [0026]      FIGS. 13A and 13B  are plan views for explaining examples of physical layouts of driver sections; and 
           [0027]      FIGS. 14A and 14B  are plan views for explaining other examples of the physical layouts of the driver sections. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0028]    Hereinafter, semiconductor memory devices according to disclosed embodiments will be described with reference to the accompanying drawings. 
         [0029]      FIG. 5  is a diagram illustrating a configuration of an example of a semiconductor memory device according to a first embodiment. In the present embodiment, the present technique is applied to a 1R1W-SRAM. 
         [0030]    In  FIG. 5 , BL_ 0 L, BL_ 0 R, BL_ 1 L, and BL_ 1 R denote bit lines. In  FIG. 5 , WL_ 0 L, WL_ 0 R, W_ 1 L, and W_ 1 R denote word lines. In  FIGS. 5 ,  21 - 00 ,  21 - 01 ,  21 - 10 , and  21 - 11  (MC 00 , MC 01 , MC 10 , and MC 11 ) denote memory cells that are provided in a memory cell array  21 . In  FIG. 5 ,  22 - 0 L,  22 - 0 R,  22 - 1 L, and  22 - 1 R are word line drivers that drive the word lines WL_ 0 L, WL_ 0 R, W_ 1 L, and W_ 1 R, respectively. In  FIG. 5 , only the four memory cells  21 - 00 ,  21 - 01 ,  21 - 10 , and  21 - 11  provided in the memory-cell array  21  are illustrated for simplicity of description. Two word lines WL_xL and WL_xR and two bit lines BL_xL and BL_xR are connected to each memory cell MC. For example, the two word lines WL_ 0 L and WL_ 0 R and the two bit lines BL_ 0 L and BL_ 0 R are connected to the memory cell  21 - 00 . The word line drivers  22 - 0 L and  22 - 1 L have the same configuration and the same occupied area. The word line drivers  22 - 0 R and  22 - 1 R have the same configuration and the same occupied area. Note that an occupied area is an area in a plan view when viewed from a direction perpendicular to a semiconductor substrate surface (not illustrated) on which an SRAM is formed, i.e., a reference plane. 
         [0031]    Each of the memory cells  21 - 00 ,  21 - 01 ,  21 - 10 , and  21 - 11  has a configuration in which p-channel metal oxide semiconductor (MOS) transistors and n-channel metal oxide semiconductor (MOS) transistors that are, for example, the same as the p-channel transistors and the n-channel transistors included in the memory cell  1 - 00  illustrated in  FIG. 2  or the memory cell  11 - 00  illustrated in  FIG. 4  are connected to one another. Accordingly, an illustration and a description thereof are omitted. 
         [0032]    In the present embodiment, for a designed operating speed (or an operating frequency) of the 1R1W-SRAM, a word line driver  22 - x L, which drives the word line WL_xL that is one of the two word lines WL_xL and WL_xR connected to each memory cell MC and that is activated (i.e., selected) by a read operation, and a word line driver  22 - x R, which drives the other word line WL_xR, are formed so that the size of the word line driver  22 - x L is larger than the size of the word line driver  22 - x R. Note that a size is a size of the above described occupied area. In other words, the drive capability of the word line driver  22 - x L which is activated by the read operation is set to be higher than the drive capability of the word line driver  22 - x R. 
         [0033]      FIGS. 6A and 6B  are graphic charts for explaining the potential of a word line. In  FIGS. 6A and 6B , the vertical axis represents the potential of the word line WL_xL in arbitrary units, and the horizontal axis represents time in arbitrary units.  FIG. 6A  illustrates, for example, the potential of the word line WL_ 0 L in a case in which the word line WL_ 0 L illustrated in  FIG. 1  is selected, and  FIG. 6B  illustrates, for example, the potential of the word line WL_ 0 L in a case in which the word line WL_ 0 L illustrated in  FIG. 5  is selected. As is also clear from comparison between  FIGS. 6A and 6B . In  FIG. 6A , a time at which the potential of the word line WL_ 0 L reaches a level that is about half the maximum value in accordance with the drive capability of the word line driver  2 - 0 L is a time t 1   a . However, in  FIG. 6B , because the size and drive capability of the word line driver  22 - 0 L are larger than those of the word line driver  2 - 0 L, a time at which the potential of the word line WL_ 0 L reaches a level that is about half the maximum value moves to a time t 1   b  that is earlier than the time t 1   a.    
         [0034]    In order to increase a speed at which an operation of an SRAM is performed, in particular, in order to increase a speed at which a read operation is performed, it is necessary to sharply increase the potential of word lines. Accordingly, in order to sharply increase the potential of word lines, in the present embodiment, the word line driver  22 - x L, which drives the word line WL_xL that is one of the two word lines, and a word line driver  22 - x R, which drives the other word line WL_xR, are formed so that the size of the word line driver  22 - x L is larger than the size of the word line driver  22 - x R. In this manner, a required high speed operation of the SRAM may be realized without increasing the area of the entire SRAM or without increasing the power consumption of the SRAM. 
         [0035]    By increasing the size of the word line driver  22 - x L that drives the word line WL_xL which is one of the two word lines, the occupied area of the entire SRAM is increased. Because the size of the word line driver  22 - x R that drives the other word line WL_xR is not increased (i.e., may be reduced), the increase in the occupied area of the entire SRAM may be minimized. In short, it is only necessary that the size of the word line driver  22 - x L which is one of the two word line drivers be larger than the size of the word line driver  2 - x L illustrated in  FIG. 1 . It is only necessary that the size of the other word line driver  22 - x R be smaller than the size of the word line driver  22 - x L, and the size of the word line driver  22 - x R may be the same as or slightly different from (i.e., larger or smaller than) that of the word line driver  2 - x R illustrated in  FIG. 1 . Whether the size of the word line driver  22 - x R is to be made larger than, smaller than, or the same as the size of the word line driver  2 - x R illustrated in  FIG. 1  may be determined in accordance with a designed operating speed of the SRAM and an allowable range of increase in the occupied area of the entire SRAM when the word line drivers  22 - x L and  22 - x R are formed so that the size of the word line driver  22 - x L is larger than the size of the word line driver  22 - x R. Particularly, when the size of a pair of the word line drivers  22 - x L and  22 - x R is smaller than, for example, the size of one word line driver  12 - x  included in the SRAM in which a read operation and a write operation are performed using one word line as illustrated in  FIG. 3 , a high positive effect may be obtained in terms of occupied area. In other words, in the present embodiment, a high speed operation may be realized without causing the occupied area of a driver section to be increased or causing the power consumption of the entire SRAM to be increased. 
         [0036]      FIGS. 7A and 7B  are plan views for explaining examples of layouts of driver portions.  FIG. 7A  illustrates a driver section that is formed using, for example, the word line drivers  2 - 0 L and  2 - 0 R illustrated in  FIG. 1 , and  FIG. 7B  illustrates a driver section that is formed using, for example, the word line drivers  22 - 0 L and  22 - 0 R illustrated in  FIG. 5 . The word line driver  2 - 0 L has a p-channel MOS transistor region  2   p - 0 L, in which p-channel MOS transistors are formed, and an n-channel MOS transistor region  2   n - 0 L, in which n-channel MOS transistors are formed. On the other hand, the word line driver  22 - 0 L has a p-channel MOS transistor region  22   p - 0 L, in which p-channel MOS transistors are formed, and an n-channel MOS transistor region  22   n - 0 L, in which n-channel MOS transistors are formed. As is also clear from comparison between  FIGS. 7A and 7B , in the examples, the size of the p-channel MOS transistor region  22   p - 0 L and the size of the n-channel MOS transistor region  22   n - 0 L of the word line driver  22 - 0 L are larger than the size of the p-channel MOS transistor region  2   p - 0 L and the size of the n-channel MOS transistor region  2   n - 0 L, respectively, of the corresponding word line driver  2 - 0 L. Furthermore, the size of a p-channel MOS transistor region  22   p - 0 R and the size of an n-channel MOS transistor region  22   n - 0 R of the word line driver  22 - 0 R are smaller than the size of a p-channel MOS transistor region  2   p - 0 R and the size of an n-channel MOS transistor region  2   n - 0 R, respectively, of the corresponding word line driver  2 - 0 R. 
         [0037]    In the examples illustrated in  FIGS. 7A and 7B , the length of the individual MOS transistor regions  2   p - 0 L and  2   p - 0 R in the horizontal direction and the length of the individual MOS transistor regions  22   p - 0 L and  22   p - 0 R in the horizontal direction are the same. Furthermore, the length of the individual MOS transistor regions  2   n - 0 L and  2   n - 0 R in the horizontal direction and the length of the individual MOS transistor regions  22   n - 0 L and  22   n - 0 R in the horizontal direction are the same. However, a ratio of the length of the individual MOS transistor regions  2   p - 0 L and  2   n - 0 L in the vertical direction to the length of the individual MOS transistor regions  2   p - 0 R and  2   n - 0 R in the vertical direction is 1.0:1.0 (both of the values are in arbitrary units). On the other hand, a ratio of the length of the individual MOS transistor regions  22   p - 0 L and  22   n - 0 L in the vertical direction to the length of the individual MOS transistor regions  22   p - 0 R and  22   n - 0 R in the vertical direction is 1.5:0.5 (both of the values are in the arbitrary units). In the examples illustrated in  FIGS. 7A and 7B , the size of the driver section illustrated in  FIG. 7A  is the same as that of the driver section illustrated in  FIG. 7B . 
         [0038]      FIGS. 8A and 8B  are plan views for explaining other examples of the layouts of the driver sections. In  FIGS. 8A and 8B , elements identical to those illustrated in  FIGS. 7A and 7B  are denoted by the same reference numerals, and a description thereof is omitted. In  FIGS. 7A and 7B , the word line drivers  2 - x L and  2 - x R and the word line drivers  22 - x L and  22 - x R are disposed in the vertical direction. However, in  FIGS. 8A and 8B , the word line drivers  2 - x L and  2 - x R and the word line drivers  22 - x L and  22 - x R are disposed in the horizontal direction. 
         [0039]    The size of the p-channel MOS transistor region  22   p - 0 L and the size of the n-channel MOS transistor region  22   n - 0 L of the word line driver  22 - 0 L are larger than the size of the p-channel MOS transistor region  2   p - 0 L and the size of the n-channel MOS transistor region  2   n - 0 L, respectively, of the corresponding word line driver  2 - 0 L. The size of the p-channel MOS transistor region  22   p - 0 R and the size of the n-channel MOS transistor region  22   n - 0 R of the word line driver  22 - 0 R are smaller than the size of the p-channel MOS transistor region  2   p - 0 R and the size of the n-channel MOS transistor region  2   n - 0 R, respectively, of the corresponding word line driver  2 - 0 R. 
         [0040]    In the examples illustrated in  FIGS. 8A and 8B , the length of the individual MOS transistor regions  2   p - 0 L,  2   n - 0 L,  2   p - 0 R, and  2   n - 0 R in the vertical direction and the length of the individual MOS transistor regions  22   p - 0 L,  22   n - 0 L,  22   p - 0 R, and  22   n - 0 R in the vertical direction are the same. Furthermore, the lengths of the individual MOS transistor regions  2   p - 0 L and  2   p - 0 R in the horizontal direction are the same, and the lengths of the individual MOS transistor regions  2   n - 0 L and  2   n - 0 R in the horizontal direction are the same. However, the lengths of the individual MOS transistor regions  22   p - 0 L,  22   n - 0 L,  22   p - 0 R, and  22   n - 0 R in the horizontal direction are different from one another. Furthermore, a ratio of the length of the word line driver  2 - 0 L to the length of the word line driver  2 - 0 R in the horizontal direction is 1.0:1.0 (both of the values are in arbitrary units). A ratio of the length of the word line driver  22 - 0 L to the length of the word line driver  22 - 0 R in the horizontal direction is 1.5:0.5 (both of the values are in the arbitrary units). In the examples illustrated in  FIGS. 8A and 8B , the size of the driver section illustrated in  FIG. 8A  is the same as the size of the driver section illustrated in  FIG. 8B . 
         [0041]    In the examples illustrated in  FIGS. 7A and 7B  and  FIGS. 8A and 8B , the size of the driver section illustrated in each of  FIGS. 7A and 8A  is the same as the size of the driver section illustrated in a corresponding one of  FIGS. 7B and 8B . However, in the driver section illustrated in each of  FIGS. 7B and 8B , the drive capability of the word line driver  22 - x L that drives the word line WL_xL which is activated by the read operation is set to be higher than the drive capability of the word line driver  2 - x L. The drive capability of the word line driver  22 - x R that drives the word line WL_xR is set to be equal to or lower than the drive capability of the word line driver  2 - x R. Thus, a high-speed operation may be realized without causing the occupied area of the drive section to be increased or causing the power consumption of the entire SRAM to be increased. 
         [0042]      FIG. 9  is a diagram illustrating a configuration of an example of a semiconductor memory device according to a second embodiment. In the present embodiment, the present technique is applied to a 1R1W-SRAM. In  FIG. 9 , elements identical to those illustrated in  FIG. 5  are denoted by the same reference numerals, and a description thereof is omitted. 
         [0043]    In the present embodiment, in order to distribute a load imposed on a word line, division of the word line is performed. Specifically, from a pair of the word lines WL_xL and WL_xR, only the word line WL_xL that is activated by the read operation is divided into two word lines. In the example illustrated in  FIG. 9 , the word line WL_ 0 L is divided into two word lines, namely, divided word lines WL_ 0 LL and WL_ 0 LR. Furthermore, the word line WL_ 0 L is driven by a word line driver  32 - 0 L 1 . The divided word line WL_ 0 LL is further driven by a corresponding word line driver  32 - 0 L 2 , and the divided word line WL_ 0 LR is further driven by a corresponding word line driver  32 - 0 L 3 . As described above, a driver section for the pair of the word lines WL_ 0 L and WL_ 0 R is formed using the word line drivers  32 - 0 L 1 ,  32 - 0 L 2 ,  32 - 0 L 3 , and  22 - 0 R. 
         [0044]    Note that the number of divisions for a word line is two in the example illustrated in  FIG. 9 . However, in  FIG. 9 , when three or more memory cells MC are provided in a memory-cell array  31 , the number of divisions for a word line may be set to an appropriate value that is equal to or larger than two. 
         [0045]    The drive capability of a combination of the word line drivers  32 - 0 L 1  and  32 - 0 L 2  or a combination of the word line drivers  32 - 0 L 1  and  32 - 0 L 3  is set to be, for example, higher than the drive capability of the word line driver  2 - 0 L illustrated in  FIG. 1 , whereby a speed at which an operation of the SRAM is performed may be increased, and, in particular, a speed at which the read operation is performed may be increased. Furthermore, the word line drivers  32 - 0 L 1 ,  32 - 0 L 2 , and  32 - 0 L 3  are provided only for the word line WL_ 0 L that is activated by the read operation. Only the word line driver  22 - 0 R may be provided for the other word line WL_ 0 R. In other words, by providing three word line drivers  32 - x L 1 ,  32 - x L 2 , and  32 - x L 3  for the word line WL_xL, the occupied area of the entire SRAM is increased. Because the size of the word line driver  22 - x R that drives the other word line WL_xR is not increased (i.e., may be reduced), the increase in the occupied area of the entire SRAM may be minimized. Thus, a high-speed operation may be realized without causing the occupied area of a driver section to be increased or causing the power consumption of the entire SRAM to be increased. 
         [0046]      FIGS. 10A and 10B  are graphic charts for explaining the potential of a word line. In  FIGS. 10A and 10B , the vertical axis represents the potential of the word line WL_xL in arbitrary units, and the horizontal axis represents time in arbitrary units.  FIG. 10A  illustrates, for example, the potential of the word line WL_ 0 L in a case in which the word line WL_ 0 L illustrated in  FIG. 1  is selected, and  FIG. 10B  illustrates, for example, the potential of the word line WL_ 0 L in a case in which the word line WL_ 0 LL illustrated in  FIG. 9  is selected. As is also clear from comparison between  FIGS. 10A and 10B , in  FIG. 10A , a time at which the potential of the word line WL_ 0 L reaches a level that is about half the maximum value in accordance with the drive capability of the word line driver  2 - 0 L is the time t 1   a . However, in  FIG. 10B , because the drive capability of the combination of the word line drivers  32 - 0 L 1  and  32 - 0 L 2  is higher than the drive capability of the word line driver  2 - 0 L, a time at which the potential of the divided word line WL_ 0 LL reaches a level that is about half the maximum value moves to a time t 2   b  that is earlier than the time t 1   a . A time t 2   a  illustrated in  FIG. 10B  is a time at which the potential of the divided word line WL_ 0 LL reaches the maximum value. 
         [0047]    The layout of the driver portion may be basically determined as in the examples that are described with reference to  FIGS. 7A and 7B  or  FIGS. 8A and 8B  except that the three word line drivers  32 - x L 1 ,  32 - x L 2 , and  32 - x L 3  are provided for the word line WL_xL. 
         [0048]      FIG. 11  is a diagram illustrating a configuration of an example of a semiconductor memory device according to a third embodiment. In the present embodiment, the present technique is applied to a 1R1W-SRAM. In  FIG. 11 , elements identical to those illustrated in  FIG. 5  are denoted by the same reference numerals, and a description thereof is omitted. 
         [0049]    In the present embodiment, for a designed operating speed (or an operating frequency) of the 1R1W-SRAM, a word line driver  42 - x R, which drives the word line WL_xR that is one of the two word lines WL_xL and WL_xR connected to each memory cell MC and that is activated (i.e., selected) by the write operation, and a word line driver  42 - x L, which drives the other word line WL_xL, are formed so that the size of the word line driver  42 - x R is smaller than the size of the word line driver  42 - x L. In other words, the drive capability of the word line driver  42 - x R that is activated by the write operation is set to be lower than the drive capability of the word line driver  42 - x L. The reason for this is that, when a time allowance that is longer than a certain value is provided for the write operation (a time margin is provided for the write operation), the potential of the word lines may be slowly increased. Accordingly, the size of the word line driver  42 - x R that is activated by the write operation is reduced as small as possible, thereby reducing the occupied area of a driver section and reducing power consumption in a case of the write operation. 
         [0050]      FIGS. 12A and 12B  are graphic charts for explaining the potential of a word line. In  FIGS. 12A and 12B , the vertical axis represents the potential of the word line WL_xR in arbitrary units, and the horizontal axis represents time in arbitrary units.  FIG. 12A  illustrates, for example, the potential of the word line WL_ 0 R in a case in which the word line WL_ 0 R illustrated in  FIG. 1  is selected, and  FIG. 12B  illustrates, for example, the potential of the word line WL_ 0 R in a case in which the word line WL_ 0 R illustrated in  FIG. 11  is selected. As is also clear from comparison between  FIGS. 12A and 12B , in  FIG. 12A , a time at which the potential of the word line WL_ 0 R reaches a level that is about half the maximum value in accordance with the drive capability of the word line driver  2 - 0 R is a time t 1   a . However, in  FIG. 12B , because the size and drive capability of the word line driver  42 - 0 R are smaller than those of the word line driver  2 - 0 R, a time at which the potential of the word line WL_ 0 R reaches a level that is about half the maximum value moves to a time t 3   b  that is later than the time t 1   a.    
         [0051]    When a time margin is provided for a write operation of an SRAM, it is not necessary to sharply increase the potential of word lines that are activated by the write operation. Accordingly, in order to slowly increase the potential of word lines, in the present embodiment, the word line driver  42 - x R, which drives the word line WL_xR that is one of the two word lines, and the word line driver  42 - x L, which drives the other word line WL_xL, are formed so that the size of the word line word line driver  42 - x R is smaller than the size of the word line driver  42 - x L. In this manner, a designed frequency operation of the SRAM may be realized without increasing the area of the entire SRAM or without increasing the power consumption of the SRAM. 
         [0052]    By reducing the size of the word line driver  42 - x R that drives the word line WL_xR which is one of the two word lines, the occupied area of the entire SRAM is not increased because the size of the word line driver  42 - x L that drives the other word line WL_xL is not increased (i.e., may be reduced). In short, it is only necessary that the size of the word line driver  42 - x R which is one of the two word line drivers be smaller than the size of the word line driver  2 - x R illustrated in  FIG. 1 . It is only necessary that the size of the other word line driver  42 - x L be larger than the size of the word line driver  42 - x R, and the size of the word line driver  42 - x L may be the same as or slightly different from (i.e., larger or smaller than) that of the word line driver  2 - x L illustrated in  FIG. 1 . Whether the size of the word line driver  42 - x L is to be made larger than, smaller than, or the same as the size of the word line driver  2 - x L illustrated in  FIG. 1  may be determined in accordance with a designed operating speed of the SRAM and an allowable range of increase in the occupied area of the entire SRAM when the word line drivers  42 - x R and  42 - x L are formed so that the size of the word line driver  42 - x R is smaller than the size of the word line driver  42 - x L. When a time margin is provided for the write operation, even in a case in which the size of the word line driver  42 - x L is the same as that of the word line driver  2 - x L, by forming the word line driver  42 - x R so that the size of the word line driver  42 - x R is smaller than the size of the word line driver  2 - x R, the occupied area of a driver section may be reduced without changing performance of the SRAM, and the power consumption of the entire SRAM may be reduced. Particularly, when the size of a pair of the word line drivers  42 - x L and  42 - x R is smaller than, for example, the size of one word line driver  12 - x  included in the SRAM in which a read operation and a write operation are performed using one word line as illustrated in  FIG. 3 , a high positive effect may be obtained in terms of occupied area. In other words, in the present embodiment, a high-speed operation may be realized without causing the occupied area of a driver section to be increased or causing the power consumption of the entire SRAM to be increased. 
         [0053]      FIGS. 13A and 13B  are plan views for explaining examples of layouts of driver portions.  FIG. 13A  illustrates a driver section that is formed using, for example, the word line drivers  2 - 0 L and  2 - 0 R illustrated in  FIG. 1 , and  FIG. 13B  illustrates a driver section that is formed using, for example, the word line drivers  42 - 0 L and  42 - 0 R illustrated in  FIG. 11 . The word line driver  2 - 0 L has the p-channel MOS transistor region  2   p - 0 L, in which p-channel MOS transistors are formed, and the n-channel MOS transistor region  2   n - 0 L, in which n-channel MOS transistors are formed. On the other hand, the word line driver  42 - 0 L has a p-channel MOS transistor region  42   p - 0 L, in which p-channel MOS transistors are formed, and an n-channel MOS transistor region  42   n - 0 L, in which n-channel MOS transistors are formed. As is also clear from comparison between  FIGS. 13A and 13B , in the examples, the size of the p-channel MOS transistor region  42   p - 0 R and the size of the n-channel MOS transistor region  42   n - 0 R of the word line driver  42 - 0 R are smaller than the size of the p-channel MOS transistor region  2   p - 0 R and the size of the n-channel MOS transistor region  2   n - 0 R, respectively, of the corresponding word line driver  2 - 0 R. Furthermore, the size of a p-channel MOS transistor region  42   p - 0 L and the size of an n-channel MOS transistor region  42   n - 0 L of the word line driver  42 - 0 L are the same as the size of the p-channel MOS transistor region  2   p - 0 L and the size of the n-channel MOS transistor region  2   n - 0 L, respectively, of the corresponding word line driver  2 - 0 L. 
         [0054]    In the examples illustrated in  FIGS. 13A and 13B , the length of the individual MOS transistor regions  2   p - 0 L and  2   p - 0 R in the horizontal direction and the length of the individual MOS transistor regions  42   p - 0 L and  42   p - 0 R in the horizontal direction are the same. Furthermore, the length of the individual MOS transistor regions  2   n - 0 L and  2   n - 0 R in the horizontal direction and the length of the individual MOS transistor regions  42   n - 0 L and  42   n - 0 R in the horizontal direction are the same. However, the length of the individual MOS transistor regions  42   p - 0 R and  42   n - 0 R in the vertical direction is shorter than the length of the individual MOS transistor regions  2   p - 0 R and  2   n - 0 R in the vertical direction. When it is considered that the length of a combination of the MOS transistor regions  2   p - 0 L and  2   p - 0 R (or  2   n - 0 L and  2   n - 0 R) in the vertical direction is 1.0 in arbitrary units, the length of a combination of the MOS transistor regions  42   p - 0 L and  42   p - 0 R (or  42   n - 0 L and  42   n - 0 R) in the vertical direction is 0.8 in the arbitrary units. In the examples illustrated in  FIGS. 13A and 13B , the size of the driver section illustrated in  FIG. 13B  is smaller than the size of the driver section illustrated in  FIG. 13A . 
         [0055]      FIGS. 14A and 14B  are plan views for explaining other examples of the layouts of the driver sections. In  FIGS. 14A and 14B , elements identical to those illustrated in  FIGS. 13A and 13B  are denoted by the same reference numerals, and a description thereof is omitted. In  FIGS. 13A and 13B , the word line drivers  2 - 0 L and  2 - 0 R and the word line drivers  42 - 0 L and  42 - 0 R are disposed in the vertical direction. However, in  FIGS. 14A and 14B , the word line drivers  2 - 0 L and  2 - 0 R and the word line drivers  42 - 0 L and  42 - 0 R are disposed in the horizontal direction. 
         [0056]    The size of the p-channel MOS transistor region  42   p - 0 L and the size of the n-channel MOS transistor region  42   n - 0 L of the word line driver  42 - 0 L are the same as the size of the p-channel MOS transistor region  2   p - 0 L and the size of the n-channel MOS transistor region  2   n - 0 L, respectively, of the corresponding word line driver  2 - 0 L. The size of the p-channel MOS transistor region  42   p - 0 R and the size of the n-channel MOS transistor region  42   n - 0 R of the word line driver  42 - 0 R are smaller than the size of the p-channel MOS transistor region  2   p - 0 R and the size of the n-channel MOS transistor region  2   n - 0 R, respectively, of the corresponding word line driver  2 - 0 R. 
         [0057]    In the examples illustrated in  FIGS. 14A and 14B , the length of the individual MOS transistor regions  2   p - 0 L,  2   n - 0 L,  2   p - 0 R, and  2   n - 0 R in the vertical direction and the length of the individual MOS transistor regions  42   p - 0 L,  42   n - 0 L,  42   p - 0 R, and  42   n - 0 R in the vertical direction are the same. Furthermore, the length of the individual MOS transistor regions  2   p - 0 L and  2   p - 0 R in the horizontal direction and the length of the individual MOS transistor region  42   p - 0 L in the horizontal direction are the same. The length of the individual MOS transistor regions  2   n - 0 L and  2   n - 0 R in the horizontal direction and the length of the individual MOS transistor region  42   n - 0 L in the horizontal direction are the same. However, the lengths of the individual MOS transistor regions  42   p - 0 L,  42   n - 0 L,  42   p - 0 R, and  42   n - 0 R in the horizontal direction are different from one another. Furthermore, when it is considered that the length of a combination of the MOS transistor regions  2   p - 0 L,  2   n - 0 L,  2   p - 0 R, and  2   n - 0 R in the horizontal direction is 1.0 in arbitrary units, the length of a combination of the MOS transistor regions  42   p - 0 L,  42   n - 0 L,  42   p - 0 R, and  42   n - 0 R in the horizontal direction is 0.8 in the arbitrary units. In the examples illustrated in  FIGS. 14A and 14B , the size of the driver section illustrated in  FIG. 14B  is smaller than the size of the driver section illustrated in  FIG. 14A . 
         [0058]    In the examples illustrated in  FIGS. 13A and 13B  and  FIGS. 14A and 14B , the size of the driver section illustrated in each of  FIGS. 13B and 14B  is smaller than the size of the driver section illustrated in a corresponding one of  FIGS. 13A and 14A . In the driver section illustrated in each of  FIGS. 13B and 14B , the drive capability of the word line driver  42 - x R that drives the word line WL_xR which is activated by the write operation is set to be lower than the drive capability of the word line driver  2 - x R. The drive capability of the word line driver  42 - x L that drives the word line WL_xL is set to be equal to or lower than the drive capability of the word line driver  2 - x L. Thus, the occupied area of the driver section is reduced, and a high-speed operation may be realized in a range of the time margin provided for the write operation without causing the power consumption of the entire SRAM to be increased. 
         [0059]    In each of the first to third embodiments described above, it is supposed that a 1R1W-SRAM is used. However, a memory cell that is the same as the memory cell which is illustrated in  FIG. 2  and which is used for a 2R1W-SRAM may be used as a memory cell that is used in each of the first to third embodiments. For this reason, when development of both a 1R1W-SRAM and a 2R1W-SRAM is performed, it is not necessary to independently develop each of a memory cell for the 1R1W-SRAM and a memory cell for the 2R1W-SRAM. Accordingly, a time taken by development (i.e., the number of man-hours needed to perform design and an actual production process) may be reduced. Thus, cost of development of the 1R1W-SRAM and the 2R1W-SRAM may be reduced. Note that, in a 2R1W-SRAM, two word lines are activated by a read operation, and two word lines are also activated by a write operation. However, in a 1R1W-SRAM such as the 1R1W-SRAM in each of the above-described embodiments, one word line is activated by a read operation, and two word lines are activated by a write operation. 
         [0060]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the embodiment. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.