Abstract:
Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to a floating body cell (FBC). The present disclosure is particularly applicable to forming FBCs in semiconductor devices. 
       BACKGROUND 
       [0002]    FBCs are simple and attractive in terms of scaling over conventional dynamic random-access memory (DRAM) because of the FBCs&#39; capacitor-less structure. FBCs make use of a floating body to store data in the form of a floating body potential. For example, the value 1 is achieved in FBCs when a positive voltage is applied to a bitline (BL) to initialize impact ionization, and holes are accumulated in the body that raise the body potential. The value 0 is achieved when a negative voltage is applied to the BL, and holes are extracted from the body and reduce the body potential. Despite the foregoing, FBCs still experience issues associated with DRAM, such as refresh procedures to replenish the charge lost during read or after prolonged use. Additionally, limited data storage capacity in FBCs exacerbates the refresh rate issue. 
         [0003]    A need therefore exists for methodology enabling formation of improved FBCs with faster programming and lower refresh rates, and the resulting device. 
       SUMMARY 
       [0004]    An aspect of the present disclosure is an efficient method for forming an FBC with faster programming and a lower refresh rate. 
         [0005]    Another aspect of the present disclosure is an FBC with faster programming and a lower refresh rate. 
         [0006]    Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims. 
         [0007]    According to the present disclosure, some technical effects may be achieved in part by a method including: forming a silicon on insulator (SOI) layer on a substrate; forming a hetero junction band-engineered layer (band-engineered layer) surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions. 
         [0008]    Aspects of the present disclosure include forming the gate prior to the band-engineered layer, forming a hard mask on the gate, recessing the SOI layer forming recesses on each side of the gate, forming the band-engineered layer lining the recesses, forming the source region and the drain region on the band-engineered layer, and removing the hard mask. Additional aspects include forming a gate oxide layer on the SOI layer prior to forming the gate, and forming the source and drain regions coplanar with the gate oxide layer. Further aspects include forming a silicon layer on the band-engineered layer, forming a dummy gate on the silicon layer prior to forming the source region and the drain region, and forming the gate by: removing the dummy gate, the silicon layer and the band-engineered layer below the dummy gate, forming a cavity, forming a gate oxide layer on sidewalls and a bottom surface of the cavity, and filling the cavity with a gate material. An additional aspect includes forming the band-engineered layer as a multi-layer stack. Another aspect includes forming the band-engineered layer with a decreasing concentration of germanium (Ge) from a bottom surface of the multi-layer stack to a top surface of the multi-layer stack. Further aspects include recessing the SOI layer, forming a gate oxide layer on a sidewall and a bottom surface of the recess, forming a gate on the gate oxide layer, recessing the SOI layer on each side of the gate, forming the band-engineered layer on the recessed SOI layer, and forming the source region and the drain region on the band-engineered layer. Additional aspects include forming a silicon layer on the band-engineered layer, etching a portion of the silicon layer, the band-engineered layer, and the SOI layer, forming a gate oxide layer on a sidewall and a bottom surface of the etched portion, and forming a gate on the gate oxide layer, prior to forming the source and drain regions. Yet another aspect includes forming a buried oxide (BOX) layer on the substrate prior to forming the SOI layer. 
         [0009]    Another aspect of the present disclosure is a device including: a SOI layer on a substrate, a gate on the SOI layer, a band-engineered layer on the SOI layer, on at least one side of the gate, and a source region and a drain region at opposite sides of the gate, at least one of the source region and the drain region being on the band-engineered layer. 
         [0010]    Aspects include the SOI layer being recessed on each side of the gate, the band-engineered layer lining each recess, and both the source region and the drain region being formed on the band-engineered layer. Another aspect includes the source region and the drain region extending above a top surface of the SOI layer. Further aspects include a gate oxide layer on side and bottom surfaces of the gate, and the band-engineered layer being on both sides of the gate. Yet another aspect includes the band-engineered layer including a multi-layer stack under the gate and on both sides of the gate. An additional aspect includes the multi-layer stack including Ge with an increasing concentration from a bottom surface of the multi-layer stack to a top surface of the multi-layer stack. Additional aspects include a portion of the SOI layer being recessed, a gate oxide layer lining a side surface and a portion of a bottom surface of the recess, forming an L-shape, the gate being formed on the gate oxide layer, and the band-engineered layer being on a non-recessed portion of the SOI layer. Additional aspects include a first recess in the SOI layer having a first depth, a gate oxide layer lining a side surface and a portion of a bottom surface of the first recess, forming an L-shape, the gate being formed on the gate oxide layer, a second recess in the SOI layer having a second depth, less than the first depth at one side of the gate, a third recess in the SOI layer having a third depth at the other side of the gate, wherein the band-engineered layer lines the second and third recesses and both the source region and the drain region are formed on the band-engineered layer. Another aspect includes a BOX layer under the SOI layer. 
         [0011]    Another aspect of the present disclosure includes: forming a BOX layer on a silicon substrate, forming a SOI layer on the BOX layer, forming a gate on the SOI layer, forming a band-engineered layer on the SOI layer at least at one side of the gate, forming a silicon layer on the band-engineered layer, and forming source and drain regions at opposite sides of the gate, each in either the silicon layer or the SOI layer. An additional aspect includes forming a gate oxide layer prior to forming the gate, the gate oxide layer being formed on a bottom surface and at least one side surface of the gate. 
         [0012]    Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
           [0014]      FIGS. 1 through 10  schematically illustrate a method for forming an FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment; 
           [0015]      FIGS. 11 through 13  schematically illustrate a method for forming an alternative FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment; 
           [0016]      FIGS. 14 through 21  schematically illustrate a method for forming an alternative FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment; 
           [0017]      FIGS. 22 through 30  schematically illustrate a method for forming an alternative FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment; 
           [0018]      FIGS. 31 through 39  schematically illustrate a method for forming an alternative FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment; 
           [0019]      FIGS. 40 through 46  schematically illustrate a method for forming an alternative FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment; and 
           [0020]      FIGS. 47 through 54  schematically illustrate a method for forming an alternative FBC with faster programming and a lower refresh rate, in accordance with an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” 
         [0022]    The present disclosure addresses and solves the current problem of refresh and programming rates attendant upon utilizing FBCs for DRAMS. In accordance with embodiments of the present disclosure, an FBC is formed with a band-engineered layer to improve the programming and refresh rates. An FBC with a band-engineered layer experiences a smaller energy potential for the impact ionization rate thereby resulting in greater impact ionization for faster programming and a lower refresh rate. Embodiments of FBCs according to the present disclosure may also include a larger storage volume leading to larger memory windows that prolong retention and lower refresh rates. 
         [0023]    Methodology in accordance with embodiments of the present disclosure includes forming a BOX layer on a silicon substrate, forming a SOI layer on the BOX layer, forming a gate on the SOI layer, forming a band-engineered layer on the SOI layer at least at one side of the gate, forming a silicon layer on the band-engineered layer, and forming source and drain regions at opposite sides of the gate, each in either the silicon layer or the SOI layer. 
         [0024]    Adverting to  FIG. 1 , a method of forming an FBC with a faster programming rate and a lower refresh rate, according to an exemplary embodiment, begins with a substrate  101 . The substrate  101  may be formed of silicon (Si). Next, as illustrated in  FIG. 2 , a SOI layer  201  may be formed by forming a BOX layer  203  within the substrate  101 . The BOX layer  203  may be formed by oxygen implantation in the substrate  101  followed by a high temperature anneal to create a BOX layer  203  formed of silicon dioxide. As a result, a SOI layer  201  is formed above the BOX layer  203 . The SOI layer  201  may be 5 to 30 nanometers (nm) thick for a fully depleted SOI and 50 to 80 nm thick for a partially-depleted SOI. 
         [0025]    As illustrated in  FIG. 3 , a gate oxide layer  301  is formed above the SOI layer  201 . The gate oxide layer  301  may be formed of any gate oxide material. Further, as illustrated in  FIG. 4 , a poly-silicon (poly-Si) layer  401  may be formed above the gate oxide layer  301 . Further, a hard mask layer  501  may be formed above the poly-Si layer  401 , as illustrated in  FIG. 5 . The hard mask layer  501  may be patterned and subsequently etched by a reactive ion etch (RIE) to form recesses  601  in the hard mask layer  501 , the poly-Si layer  401  and the gate oxide layer  301 , as illustrated in  FIG. 6 , thereby forming a gate stack  603  on the SOI layer  201 . Further, spacers  701  may be formed on either side of the gate  603  ( FIG. 7 ). 
         [0026]    Adverting to  FIG. 8 , the gate stack  603  and the spacers  701  may be used as a mask to form recesses  803  in the SOI layer  201  thereby forming a patterned SOI layer  801 . An RIE may be used to form the recesses  803 . As illustrated in  FIG. 8 , the recesses  803  may be formed in the SOI layer  201  substantially down to the BOX layer  203 . For example, at recesses  803 , the SOI layer  201  may be 1 to 5 nm in depth. 
         [0027]    Adverting to  FIG. 9 , the recesses  803  may subsequently be lined with a band-engineered layer  901 . The band-engineered layer  901  can be p-doped or un-doped Si—Ge or Ge when the SOI layer  201  is p-type and may be formed to a thickness of 1 to 5 nm. Subsequently, the remaining recesses  803  may be filled with Si and in-situ doped to form source and drain regions  903  that are 5 to 30 nm thick. After the source and drain regions  903  are formed, they may be laser annealed at 1000 to 1200° C. to activate the source/drain junction without diffusion. Then, the hard mask layer  501 , in addition to parts of the spacers  701 , may be removed, such as by chemical mechanical polishing (CMP), resulting in an FBC with faster programming and a lower refresh rate, as illustrated in  FIG. 10 . 
         [0028]    A method of forming an FBC with faster programming and a lower refresh rate, according to an alternative exemplary embodiment, may begin similar to  FIGS. 1 through 8  of the method discussed above. However, as illustrated in  FIG. 11 , less deep recesses  1103  (for example to a depth of 2.5 to 15 nm, around half of the initial SOI thickness) may be formed in the SOI layer  201  that do not extend down to the BOX layer  203 , forming a patterned SOI layer  1101 . Subsequently a band-engineered layer  1201  may be formed to line the recesses  1103 , as illustrated in  FIG. 12 . The band-engineered layer  1201  can be p-doped or un-doped Si—Ge or Ge when the SOI layer  1101  is p-type and may be formed to a thickness of 1 to 5 nm. Further, an Si layer may be grown above the band-engineered layer  1201  to fill the recesses  1103 , which may be in-situ doped to form raised source and drain regions  1203  at a thickness of 5 to 30 nm. After the source and drain regions  1203  are formed, they may be laser annealed at 1000 to 1200° C. The recesses  1103  may be formed such that the raised source and drain regions  1203  are coplanar with the gate oxide layer  301 . After formation of the source and drain regions  1203 , the hard mask layer  501 , in addition to parts of the spacers  701 , may be removed, as illustrated in  FIG. 13 , resulting in an FBC with faster programming and a lower refresh rate. Further, by forming shallower recesses  1103 , a larger data storage volume is generated in the SOI layer  1101 , improving charge retention and data storage volume and lowering the refresh rate of the FBC. 
         [0029]    Although the resulting FBC is illustrated as including the band-engineered layer  1201 , alternatively the FBC may exclude the band-engineered layer  1201 . In this case, the enlarged storage volume of the raised source and drain regions  1203  and the SOI layer  1101  provides improved charge retention and a lowered refresh rate, though the programming speed may be slower. 
         [0030]    Adverting to  FIG. 14 , a method of forming an FBC with faster programming and a lower refresh rate, according to another exemplary embodiment, begins with a substrate  101  with a SOI layer  201  and a BOX layer  203 , similar to  FIG. 2  discussed above. As illustrated in  FIG. 15 , a band-engineered layer  1501  may be formed on the SOI layer  201 . As discussed above, the band-engineered layer  1501  can be p-doped or un-doped Si—Ge or Ge when the SOI layer  201  is p-type and may be formed to a thickness of 1 to 5 nm. 
         [0031]    Next, a Si layer  1601  may be formed on the band-engineered layer  1501 , as illustrated in  FIG. 16 . The Si layer  1601  may be formed to a thickness of 5 to 30 nm. Further, a sacrificial layer  1603  may be formed on the Si layer  1601 . The sacrificial layer may be subsequently patterned and etched to form a dummy gate  1701 , as illustrated in  FIG. 17 . Spacers  1703  may be formed on opposite sides of the dummy gate  1701 . The spacers  1703  may be formed of an inter-layer dielectric (ILD) material and may be laser annealed. After the spacers  1703  are formed, source and drain regions  1801  ( FIG. 18 ) may be implanted within the Si layer  1601  on opposite sides of the spacers  1703 . After formation of the source and drain regions  1801 , the source and drain regions  1801  may be laser annealed at 1000 to 1200° C. 
         [0032]    An ILD  1901  may be subsequently formed above the source and drain regions  1801 , the dummy gate  1701  and the spacers  1703 . After formation of the ILD  1901 , the ILD  1901  may be removed down to the dummy gate  1701 , such as by CMP. Then, the dummy gate  1701  and the portion of the Si layer  1601  and the band-engineered layer  1501  directly below the dummy gate  1701  are removed, forming the cavity  1903 , as illustrated in  FIG. 19 . An etch may be used to remove the portion of the Si layer  1601  and the portion of the band-engineered layer  1501  to form the cavity  1903 . Next, a gate oxide layer  2001  may be formed on sidewalls and a bottom surface of the cavity  1903 , as illustrated in  FIG. 20 . Adverting to  FIG. 21 , after formation of the gate oxide layer  2001 , the cavity  1903  may be filled with a gate material  2101 , such as poly-Si, resulting in an FBC with faster programming and a lower refresh rate and a larger data storage volume. 
         [0033]    Although the resulting FBC is illustrated as including the band-engineered layer  1501 , alternatively the FBC may exclude the band-engineered layer  1501 . In this case, the enlarged storage volume of the raised source and drain regions  1801  and the SOI layer  201  provides improved charge retention and a lowered refresh rate, though the programming speed may be slower. 
         [0034]    Adverting to  FIG. 22 , the method described above with respect to  FIGS. 14 through 21  may alternatively include a multi-layer stack of SiGe/Si/SiGe for the band-engineered layer. As illustrated in  FIG. 22 , the process may begin the same as the structure shown in  FIG. 15  with the band-engineered layer  1501 , the SOI layer  201  and the BOX layer  203  within the substrate  101 . However, the SOI layer  201  may be thinner than in the structure of  FIG. 15 . A Si layer  2301  may be deposited on the band-engineered layer  1501 , as illustrated in  FIG. 23 . The Si layer  2301  may be thinner than the Si layer  1601 , for example having a thickness of 2 to 15 nm. Subsequently, a second band-engineered layer  2401  may be formed on the Si layer  2301 . The second band-engineered layer  2401  can be p-doped or un-doped Si—Ge or Ge when the SOI layer  201  is p-type and may be formed to a thickness of 1 to 5 nm. Thus, a multi-layer stack of band-engineered layers is created. Forming additional layers of Si and band-engineered layers may occur to increase the number of band-engineered layers within the multi-layer stack. Next, another Si layer  2501  may be formed on the second (or top) band-engineered layer  2401 . The Si layer  2501  may be thicker than the Si layer  2301 , such as 5 to 30 nm thick. Subsequent to formation of the Si layer  2501 , a sacrificial layer  2503  may be formed on the Si layer  2501 . The sacrificial layer  2503  may be subsequently patterned and etched to form a dummy gate  2601 , as illustrated in  FIG. 26 . Spacers  2603  may be formed on either side of the dummy gate  2601 . The spacers  2603  may be formed of an ILD material. After formation of the spacers  2603 , source and drain regions  2701  ( FIG. 27 ) may be formed within the Si layer  2501  on opposite sides of and below the spacers  2603 , and the source and drain regions  2603  may be laser annealed at 1000 to 1200° C. 
         [0035]    An ILD  2801  may be subsequently formed above the source and drain regions  2701 , the dummy gate  2601  and the spacers  2603 . The ILD  2801  may then be removed down to the dummy gate  2601 , such as by CMP, and the dummy gate  2601  and the portion of the Si layer  2501  and the second band-engineered layer  2401  directly below the dummy gate  2601  may be removed, forming the cavity  2803 , as illustrated in  FIG. 28 . An etch may be used to remove the portion of the Si layer  2501  and the second band-engineered layer  2401  to form the cavity  2803 . Next, a gate oxide layer  2901  may be formed on sidewalls and a bottom surface of the cavity  2803 , as illustrated in  FIG. 29 . Adverting to  FIG. 30 , the cavity  2803  may be filled with a gate material  3001 , such as poly-Si, resulting in an FBC with faster programming and a lower refresh rate and larger data storage volume. 
         [0036]    Adverting to  FIG. 31 , an alternative method to the method described above with respect to  FIGS. 22 through 29  may begin with the substrate  101 , the BOX layer  203  and the SOI layer  201 . Next a first band-engineered layer  3201  may be formed above the SOI layer  201 , as illustrated in  FIG. 32 . The first band-engineered layer  3201  may be formed with a decreasing concentration of Ge from a bottom surface of the first band-engineered layer  3201  to a top surface of the first band-engineered layer  3201 . Likewise, the first band-engineered layer  3201  may be formed with an increasing concentration of Si from the bottom surface of the first band-engineered layer  3201  to the top surface of the first band-engineered layer  3201 . Thus, the first band-engineered layer  3201  may be formed of Si x —Ge y , where x represents the concentration of Si increasing from 0 to 0.9 from the bottom surface of the first band-engineered layer  3201  and y represents the concentration of Ge decreasing from 1 to 0.1 from the bottom surface of the first band-engineered layer. 
         [0037]    Alternatively, rather than a single band-engineered layer  3201  with decreasing and increasing Ge and Si concentrations, respectively, multiple band-engineered layers (e.g., a multi-layer stack) may form the first band-engineered layer  3201 , where each layer has a different concentration of Ge and Si and the concentrations of Ge and Si across the layers decrease and increase respectively, as each layer is added. 
         [0038]    As illustrated in  FIG. 33 , a second band-engineered layer  3301  may be formed above the first band-engineered layer  3201 , and may be formed similar to the band-engineered layers discussed above in the first two embodiments without a varying concentration of Si and/or Ge. Alternatively, the first band-engineered layer  3201  may be the only band-engineered layer formed above the SOI layer  201 . Next, a Si layer  3401  is formed on the second band-engineered layer  3301  to a thickness of 5 to 30 nm, as illustrated in  FIG. 34 . Further, a sacrificial layer  3403  is formed above the Si layer  3401 . The sacrificial layer  3403  may be subsequently patterned and etched to form the dummy gate  3501  illustrated in  FIG. 35 . Spacers  3503  of ILD material may be formed on opposite sides of the dummy gate  3501 . Next, source and drain regions  3601  ( FIG. 36 ) may be formed within the Si layer  3401  on either side of and below the spacers  3503 . The source and drain regions  3601  may be laser annealed at 1000 to 1200° C. 
         [0039]    An ILD  3701  may be subsequently formed above the source and drain regions  3601 , the dummy gate  2601  and the spacers  2603 . The ILD  3701  may subsequently be removed down to the dummy gate  3501 , such as by CMP, and the dummy gate  3501  and a portion of the Si layer  3401  and the second band-engineered layer  3301  directly below the dummy gate  3501  may be removed, forming the cavity  3703 , as illustrated in  FIG. 37 . An etch may be used to remove the portion of the Si layer  3401  and the portion of the second band-engineered layer  3301  to form the cavity  3703 . Next, a gate oxide layer  3801  may be formed on sidewalls and a bottom surface of the cavity  3703 , as illustrated in  FIG. 38 . Adverting to  FIG. 39 , the cavity  3703  may be filled with a gate material  3901 , such as poly-Si, resulting in an FBC with faster programming and a lower refresh rate and a deeper quantum well for hole storage. 
         [0040]    Adverting to  FIG. 40 , a method of forming an FBC with faster programming and a lower refresh rate and larger data storage volume, according to another exemplary embodiment, begins with a substrate  4000  formed of Si. Next, a BOX layer  4003  may be formed on the substrate  4000 . The BOX layer  4003  may be formed by oxygen implantation in the substrate  4000  followed by a high temperature anneal to create the BOX layer  4003  formed of silicon dioxide or by bonding a BOX layer to the substrate. An SOI layer  4001  is formed above the BOX layer  4003 . The SOI layer  4001  may be thickened, such as to a thickness of 50 to 80 nm, resulting in the thicker SOI layer  4001  as compared to the SOI layers discussed above. 
         [0041]    Next, the SOI layer  4001  may be etched according to any conventional etching process to form a recess  4101  to a depth of 10 to 30 nm, as illustrated in  FIG. 41 . Adverting to  FIG. 42 , a gate oxide material may be formed on a sidewall and portion of a bottom surface of the recess  4101  forming an L-shaped gate oxide layer  4201 . After forming the L-shaped gate oxide layer  4201 , a gate material  4301  (such as poly-Si) may be formed on the L-shaped gate oxide layer  4201 , as illustrated in  FIG. 43 . A dielectric spacer  4401  may be subsequently deposited over the gate material  4301 , as illustrated in  FIG. 44 , forming a gate stack  4403 . Where the etch forms a pillar in the SOI layer  4001 , the resulting gate stack is formed around the pillar. Where the etch forms a trench, the resulting gate stack is a conventional planar metal oxide semiconductor (MOS). 
         [0042]    Adverting to  FIG. 45 , recesses  4501  may be formed on opposite sides of the gate  4403  to a depth of 10 to 30 nm. The recesses  4501  may subsequently be lined with a band-engineered layer  4601 , as illustrated in  FIG. 46 . The band-engineered layer  4601  can be p-doped or un-doped Si—Ge or Ge when the SOI layer  4001  is p-type and may be formed to a thickness of 1 to 5 nm. Subsequently, the recesses  4501  may be filled with Si and in-situ doped to form source and drain regions  4603 . Further, the source and drain regions  4603  may be laser annealed at 1000 to 1200° C. The result is an FBC with faster programming and a lower refresh rate and larger data storage volume. 
         [0043]    Although the resulting FBC is illustrated as including the band-engineered layer  4601 , alternatively the FBC may exclude the band-engineered layer  4601 . In this case, the enlarged storage volume of the raised source and/or drain region  4603  and the SOI layer  4001  provides improved charge retention and a lowered refresh rate, though programming speed may be slower. 
         [0044]    Adverting to  FIG. 47 , a method of forming an FBC with faster programming and a lower refresh rate, according to another exemplary embodiment, begins with a substrate  4700 . The substrate  4700  may be formed of Si. Next, a BOX layer  4703  may be formed on the substrate  4700 . The BOX layer  4703  may be formed by oxygen implantation in the substrate  4700  followed by a high temperature anneal to create the BOX layer  4703  formed of silicon dioxide or by bonding a BOX layer to the substrate. An SOI layer  4701  is formed above the BOX layer  4703 . The SOI layer  4701  may be formed to a thickness of 50 to 80 nm. 
         [0045]    Subsequently, a band-engineered layer  4801  may be formed on the SOI layer  4701 , as illustrated in  FIG. 48 . The band-engineered layer  4801  can be p-doped or un-doped Si—Ge or Ge when the SOI layer  4701  is p-type and may be formed to a thickness of 1 to 5 nm. Further, a Si layer  4901  is formed on the band-engineered layer  4801  ( FIG. 49 ). Next, the Si layer  4901 , the band-engineered layer  4801  and the SOI layer  4701  may be etched according to any conventional etching process to form a recess  5001  to a depth of 20 to 50 nm, as illustrated in  FIG. 50 . Adverting to  FIG. 51 , a gate oxide material may be formed on a sidewall and portion of a bottom surface of the recess  5001  forming an L-shaped gate oxide layer  5101 . After forming the L-shaped gate oxide layer  5101 , a gate material  5201  (such as poly-Si) may be formed on the L-shaped gate oxide layer  5101 , as illustrated in  FIG. 52 . A dielectric spacer  5301  may be subsequently deposited over the gate material  5201 , as illustrated in  FIG. 53 , forming a gate stack  5303 . 
         [0046]    Adverting to  FIG. 54 , portions of the Si layer  4901  and the SOI layer  4701  may be implanted and laser annealed to form a drain region  5401   a  and a source region  5401   b , respectively. Although in the embodiments above the source and drain regions may be on opposite sides of the gate based on the symmetry of the gate, for the embodiment discussed with respect to  FIG. 54 , the drain region  5401   a  is level with and/or above the gate  5303  within the Si layer  4901  and the source region  5401   b  is below the gate  5303  in the SOI layer  4701 . The result is an FBC with faster programming and a lower refresh rate. 
         [0047]    Although the resulting FBC is illustrated as including the band-engineered layer  4801 , alternatively the FBC may exclude the band-engineered layer  4801 . In this case, the enlarged storage volume of the raised drain region  5401   a  and the SOI layer  4701  provides improved charge retention and a lowered refresh rate. 
         [0048]    The embodiments of the present disclosure achieve several technical effects, including an FBC with faster programming because of a higher rate of impact ionization, additional quantum well storage capability, improved charge retention and a lowered refresh rate. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices. 
         [0049]    In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.