Abstract:
A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal.

Description:
TECHNICAL FIELD 
     This invention relates to a divider circuit, particularly but not exclusively for dividing by odd integers, and to a transistor stage therefor. 
     BACKGROUND OF THE INVENTION 
     Clock divider circuits are useful in a number of applications, particularly in counters, where a complete cycle of an output signal represents a predetermined number of incoming clock cycles. The cycles of the output signal can be used to “count” the incoming clock cycles. 
     It is desirable for such clock divider circuits to work at low power and at high frequencies. For example, desired operating parameters might be a current consumption of 10 μA at a supply voltage of 3.3 V, with an operating frequency of around 100 MHz. It is also desirable that such divider circuits consume a minimum amount of silicon when implemented on an integrated circuit. 
     Existing counters are generally based on binary counters. As the basic unit for a binary counter is a divide-by-two unit, extra logic is required to implement counts by odd numbers. This extra logic reduces the highest operating frequency obtainable by the counting circuit and also consumes chip area. Moreover, existing binary counters rarely produce an output signal which has a 50% duty cycle. 
     Signals having a 50% duty cycle are particularly desirable because in such signals, there is the maximum possible time for the rising and falling edges to achieve safe logic levels. This reduces pulse shrinkage and the consequent uncertainties, both in terms of amplitude and timing of the signal. Moreover, some circuits use both the rising and falling edges of a clock signal, so that it provides greater design flexibility to have a timing point midway through a clock cycle. 
     The present invention provides a dividing circuit which exhibits an improvement in operating frequency with reduced silicon consumption, particularly for dividing by an odd integer, referred to by N herein. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention there is provided a transistor stage for a dividing circuit, the stage comprising: 
     a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node; 
     a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, 
     wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and 
     control nodes of a second transistor of each said transistor pair are connected in common to provide a clock node for the stage. 
     Although two “pairs” of transistors are referred to, there is no need for the transistors to be matched, or otherwise be dependent on one another in their operating parameters. 
     In the described embodiment, the first transistors are directly connected to the respective first and second voltage levels, and the second transistors are directly connected between the first transistors and the output node. This provides a simple transistor configuration which does not consume an excessive amount of silicon in an integrated circuit yet which provides a high frequency, low power operating transistor stage. In an environment where the first voltage level is a power supply voltage for the stage and the second voltage level is ground, the first pair of transistors are PMOS transistors and the second pair of transistors are NMOS transistors. 
     Another aspect of the present invention provides a dividing circuit comprising a plurality (N) of transistor stages connected in a ring, each stage comprising: 
     a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node; 
     a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, 
     wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage, 
     wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal. 
     In the embodiment described herein, N is an odd integer. The circuit is particularly useful as a divide-by-three or divide-by-five circuit, where N is three or five respectively. However, the number of transistor stages can be extended to any number. It is for counting with such small odd integers that the circuit of the present invention represents a considerable improvement over existing binary counters and necessary associated logic. 
     The dividing circuit described herein can operate at low powers, for example drawing a current of less than 10 μA at a supply voltage of 3.3 V and can operate up to high frequencies. It is envisaged that operation up to a frequency of 1 GHz is possible, limited only by the characteristics of a single CMOS transistor. 
     For a better understanding of the present invention and to show how the present invention may be carried into effect, reference will now be made by way of example to the accompanying drawings and detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a circuit diagram of a divide-by-three circuit. 
     FIG. 2 illustrates input and output signals for a divide-by-three circuit such as that shown in FIG.  1 . 
     FIG. 3 illustrates a truth table of each stage of the divide-by-three circuit of FIG.  1 . 
     FIG. 4 illustrates in tabular form a sequence of logic changes on nodes of a divide-by-three circuit such as that shown in FIG.  1 . 
     FIGS. 5 a  to  5   d  illustrate representations of input and output signals in operation of a divide-by-three circuit such as that shown in FIG. 1, where the input signal has a 50% duty cycle. 
     FIGS. 6 a  to  6   d  illustrate representations of input and output signals for a divide-by-three circuit such as that shown in FIG. 1, where the input signal has a 20% duty cycle. 
     FIG. 7 illustrates a circuit diagram of a divide-by-five circuit. 
     FIGS. 8 a  to  8   f  illustrate representations of input and output waveforms for a divide-by-five circuit such as that shown in FIG. 7, where the input clock signal has a 50% duty cycle. 
     FIG. 9 illustrates a programmable dividing circuit. 
     FIGS. 10 a  to  10   b  show waveforms illustrating operation of a dividing circuit such as that shown in FIG.  9 . 
     FIG. 11 illustrates a block diagram of a phase-locked-loop circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a divide-by-three (divider) circuit which comprises three stages S 1 , S 2 , and S 3  connected in a ring with an input node of each stage connected to an output node of a preceding stage. Each stage comprises a first pair of p-channel MOS transistors T 1 , T 2  and a second pair of n-channel MOS transistors T 3 , T 4 . Only the first stage S 1  is described in detail herein, the remaining stages being the same. The transistors T 1 , T 2  of the first pair are connected in series between a supply voltage Vdd and an output node  01 . The transistors T 3 , T 4  of the second pair are connected in series between the output node  01  and ground. The gate of the outermost transistor of each pair T 1 , T 4  is connected to an input node I 1  for the stage S 1 . The gates of the inner two transistors T 2 , T 3  are connected to receive an input clock signal CLK IN and form a clock node for the stage. 
     S 2  and S 3  represent similar stages, each of which have an outer set of transistors connected to an input node for the stage and an inner set of transistors connected to the input clock signal CLK IN. An output signal may be taken from the divider circuit at the output node of any of the stages, but in FIG. 1, a single output signal CLK OUT is shown for convenience at the output of the third stage S 3 . 
     As shown in FIG. 2, the divider circuit represents a divide-by-three counter. That is, one cycle of the output signal CLK OUT represents three cycles of the input clock signal CLK IN. To achieve this, the divider circuit causes a change in state in the output signal CLK OUT which is dependent not only on a clock edge, but also on a logical state of data preceding the clock edge. In this context, the data is the signal applied to the input node of a stage S 1 , S 2 , or S 3  from the preceding stage. There follows an explanation as to how the divider circuit of FIG. 1 achieves this. 
     FIG. 3 represents the truth table for each stage S 1 , S 2 , and S 3  of the divider circuit. Considering the stage S 1 , when the voltage at the input node I 1  has logic state zero, transistor T 4  is off and transistor T 1  is turned on. In this situation, when the input clock signal CLK IN has a logic state of zero, transistor T 2  is likewise turned on, creating a current path which allows the output node  01  to be pulled up to Vdd, as shown in the first line of the truth table of FIG.  3 . However, when the input clock signal CLK IN has a logic state of one, the transistor T 2  is turned off with the consequence that the output node  01  “floats” at the logic state it held previously. That is, the output node  01  represents a high impedance state to the subsequent stage and is not driving any output current. 
     When the voltage at the input node I 1  is in logic state one, the transistor T 1  is turned off and the transistor T 4  is turned on. Now, with the input clock signal CLK IN at logic state zero, the transistor T 3  remains off and so the output node  01  floats. When the logic state of the input clock signal CLK IN changes to a one, the transistor T 3  is turned on to create a current path allowing the transistors T 3  and T 4  to pull the output node  01  down to ground. 
     The effect of this around the ring can be seen with reference to FIG.  4 . Because there is an odd number of stages S 1 , S 2 , and S 3  in the ring, it is inevitable that before each edge of the incoming input clock signal CLK IN, two consecutive stages will have the same logic level on their outputs. In an initial state discussed in FIG. 4, the nodes marked V 1  and V 3  both have a zero logic state. When the incoming input clock signal CLK IN changes state, the second of these logic states in the ring (at V 1  in the example of FIG. 4) which was floating at a zero is forced to change its state to a one. Thus, the inputs of stages S 1  and S 2  (marked as V 1  and V 2 ) now have the same logic level one. On the next change of state of the input clock signal CLK IN, the state of an input signal at the input node I 1  is logic level one and the state of the input clock signal CLK IN is logic level one, which drives the state of the output node  01  (marked as V 2  in FIG. 4) from its preceding floating state of a logic level one to a logic level zero. This sequence continues, resulting in the repeating cycle marked as R in FIG. 4, which is represented by the output waveform in FIG.  2 . 
     Initialization is not required to start the divider circuit. It will self-start within a few cycles of the input signal as a result of small asymmetries in the layout. However, initialization circuitry may be added if desired to force a particular initial state. It will readily be appreciated that logic circuitry such as that marked as L in FIG. 1 may be inserted between any two sequential stages of the ring, provided that the logic circuitry L is not inverting. 
     Power consumption of the divider circuit is very low compared with existing divider circuits. One reason for this is that only one internal node changes state on each clock edge, so that the power consumption is dominated by the charge/discharge currents of the capacitance of a single node. Moreover, the maximum operating frequency of the divider circuit can be very high, because the delay introduced by each stage S 1 , S 2 , or S 3  is only that introduced by a single transistor. In other words, each stage S 1 , S 2 , or S 3  only comprises one “layer” of transistor logic requiring a change in state between input and output. 
     The divider circuit of FIG. 1 has the useful property of maintaining a duty cycle of 50% in the output signal if the input signal has a duty cycle of 50%. FIG. 5 a  represents the input waveform at a duty cycle of 50%. FIGS. 5 b  to  5   d  represent the output waveforms at the nodes marked V 1 , V 2 , and V 3  in FIG. 1 respectively. As can be seen from FIGS. 5 a  to  5   d , when the input clock signal CLK IN has a duty cycle of 50%, the output waveform of each stage S 1 , S 2 , or S 3  also has a duty cycle of 50%. Furthermore, the output waveform of each stage S 1 , S 2 , or S 3  has a specific and predictable phase relationship with the output waveform of other stages, providing the designer with great flexibility concerning applications of the divider circuit. 
     The divider circuit also has the property of “improving” the duty cycle of the input clock signal CLK IN, where the duty cycle is not 50%. The manner of operation of the divider circuit ensures that an output signal always has a duty cycle closer to 50% than the input clock signal CLK IN. If the percentage difference from 50% of the duty cycle of the incoming input clock signal CLK IN is designated Δ IN , the difference from Δ OUT  from 50% of the duty cycle in the output signal is Δ IN  divided by N, where N is the number of stages in the dividing circuit. Thus, the “error” in the duty cycle is reduced by the number of stages in the divider circuit ring. An example of this is shown for the divide-by-three circuit of FIG. 1 in the waveforms of FIGS. 6 a  to  6   d . FIG. 6 a  represents the input clock signal CLK IN having a duty cycle of 20%. FIG. 6 b  to  6   d  represent the output signals at each of the output nodes V 1  to V 3 , from which it can readily be seen that the duty cycle of the output signal at any of the nodes is 60%. That is, according to the above calculation          A   OUT     =         [     50   -   20     ]     3     =     10        %   .                                
     The principle of the divide-by-three circuit illustrated in FIG.  1  and described above can readily be extended to other odd numbers, e.g., 5,7,9 etc. FIG. 7 is a circuit diagram of a divide-by-five circuit, having five stages S 1  to S 5 , each stage having the transistor configuration described with reference to FIG.  1 . FIGS. 8 a  to  8   f  represent the waveforms for the circuit of FIG.  7 . FIG. 8 a  represents the input signal at a 50% duty cycle, and FIGS. 8 b  to  8   f  represent the output signals at each output nodes V 1  to V 5 . 
     FIG. 9 illustrates how a programmable dividing circuit may be constructed to divide by a selected odd integer. FIG. 9 illustrates a programmable dividing circuit which can selectively divide by three or by five. The transistor configuration of each stage S 1  to S 5  is not shown in FIG. 9 but is the same as for FIG. 7. A divide-by-five circuit is constructed as illustrated in FIG.  7 . However, instead of connecting the output V 6  of the last transistor stage S 5  to the input of the first transistor stage S 1  directly, the output V 6  of the fifth transistor stage S 5  is supplied to one input  2  of a multiplexer  6 . The output V 4  of the third transistor S 3  stage is supplied to the other input  4  of the multiplexer  6 . 
     An output  8  of the multiplexer  6  is connected to the input node of the first transistor stage S 1  and also provides the output signal CLK OUT. A select input  10  receives a select signal SEL which controls whether the output V 4  of the third transistor stage S 3  or the output V 6  of the fifth transistor stage S 5  is supplied to the first transistor stage S 1  and also serves as the output for the circuit. It will be appreciated that any suitable multiplexer could be used to selectively supply the output of the third stage S 3  or fifth stage S 5  as the input to the first transistor stage S 1 . 
     FIG. 10 illustrates operation of the circuit of FIG. 9 with an input signal CLK IN having a 50% duty cycle as illustrated in FIG. 10 a . FIG. 10 b  illustrates the state of the select signal SEL supplied to the select input  10  of the multiplexer  6 . At time t 0 , the select signal SEL is low, causing the first input  4  of the multiplexer  6  to be supplied to its output  8  and thus connecting in a ring the three transistor stages S 1 , S 2 , and S 3 . The circuit thus operates as a divide-by-three circuit, as can be seen from the output waveforms between time t 0  and t 1  in FIGS. 10 c  to  10   h . At time t 1 , the select signal SEL goes high, thus connecting the second input  2  to the output  8  of the multiplexer  6 . In this case therefore, the five transistor stages S 1  to S 5  are connected in a ring so that the circuit operates as a divide-by-five circuit, as can be seen from the waveforms in FIGS. 10 c  to  10   h  after time t 1 . 
     As can be seen from the waveforms in FIG. 10, it is possible to change the dividing integer N “on the fly” by appropriately selecting the time at which the state of the select input is changed. 
     It will readily be appreciated that the principle illustrated above with respect to a programmable divide-by-three/divide-by-five circuit can be applied to any selected odd numbers by appropriately selecting the transistor stages whose outputs are supplied to the multiplexer  6 . Moreover, it is possible to construct a circuit which can selectively divide by three or more odd integers by having a multiplexer  6  with three or more inputs to which the outputs of the appropriate transistor stages are supplied. 
     FIG. 11 is a diagram of a basic phase-locked-loop circuit in which the dividing circuits described herein are particularly useful. The phase-locked-loop circuit receives a reference clock input REF CLK IN and generates a PLL clock output PLL CLK OUT. An input divider  50  creates from the reference clock input REF CLK IN a reference input frequency for a phase detector  52 . The phase detector  52  also receives as an input a feedback signal φ generated in a manner described in the following. An error output e is generated according to the relative phase of the reference signal and the feedback signal φ and is supplied to a charge pump  54 . A loop filter  56  shapes the output of the charge pump  54  and generates a correction signal for a voltage controlled oscillator  58 . The output of the voltage controlled oscillator  58  is passed through a feedback divider  60  to generate the second input (feedback signal φ) to the phase detector  52 . The output of the voltage controlled oscillator  58  is also passed through an output divider  62  to generate the clock output PLL CLK OUT. 
     A dividing circuit in accordance with the present invention can usefully be used to implement any of the input divider  50 , feedback divider  60 , or output divider  62  to provide a phase-locked-loop satisfying required technology, frequency and power constraints. 
     From the foregoing, it will be appreciated that although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims, the interpretation of which are to be made in accordance with established doctrines of claim interpretation.