Abstract:
Embodiments of the present invention relate to a thin film transistor array panel and a display device including the same. An exemplary embodiment of the present invention provides a thin film transistor array panel and a display device including the same, including: an insulation substrate including an upper surface and a lower surface; a light blocking member disposed on or facing the upper surface of the insulation substrate and defining a plurality of openings; and a thin film transistor disposed on the upper surface of the insulation substrate. The insulation substrate may include a plurality of recesses formed in the opening in the lower surface of the insulation substrate, each recess positioned to correspond to one of the openings.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to, and the benefit of, Korean Patent Application No. 10-2015-0041812 filed in the Korean Intellectual Property Office on Mar. 25, 2015, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     (a) Field of the Invention 
     Embodiments of the present invention relate generally to flat panel displays. More specifically, embodiments of the present invention relate to a thin film transistor array panel and a display device including the same. 
     (b) Description of the Related Art 
     Display devices that are widely used currently include a liquid crystal display, an organic light emitting diode display, an electrophoretic display, and the like. Such display devices include a thin film transistor array panel on which a plurality of pixels and a plurality of driving signal lines are formed. 
     Recently, demand for a light and slim display device has steadily increased, and accordingly, a thin substrate such as a plastic flexible substrate having a thickness equal to or less than 2 mm has been developed and used. However, unlike a glass substrate, a plastic substrate has characteristics that cause phase retardation to increase, such that visibility may be reduced. Accordingly, a thin film transistor array panel including the plastic substrate and a display device including the thin film transistor array panel may cause deterioration of image quality. 
     The above information disclosed in this Background section is only to enhance the understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. 
     SUMMARY 
     Embodiments of the present invention provide a thin film transistor array panel and a display device including the same, that may improve image quality by increasing visibility. 
     An exemplary embodiment of the present invention provides a thin film transistor array panel, including: an insulation substrate including an upper surface and a lower surface; a light blocking member disposed on or facing the upper surface of the insulation substrate and defining a plurality of openings; and a thin film transistor disposed on the upper surface of the insulation substrate. The insulation substrate may include a plurality of recesses formed in the lower surface of the insulation substrate, each recess positioned to correspond to one of the openings. 
     Each recess may include opposing lateral surfaces and a bottom surface extending therebetween. 
     At least one lateral surface may be substantially perpendicular to its corresponding bottom surface. 
     At least one lateral surface may form an angle of about 105° to 150° with respect to its corresponding bottom surface. 
     A cross-sectional shape of each recess may be an arc, sine wave, semicircular, or semi-elliptical shape. 
     The insulation substrate may comprise at least one of polyimide, polyamide, and polycarbonate. 
     A thickness of the insulation substrate may be from about 2 μm to about 50 μm. 
     A height of each recess may be equal to or less than ⅔ of the thickness of the insulation substrate. 
     The thin film transistor array panel may further include a passivation film formed below the lower surface of the insulation substrate. 
     The thin film transistor may include a gate electrode; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a pair of ohmic contact members formed on the semiconductor; and a source electrode and a drain electrode formed on the ohmic contact members. 
     Another embodiment of the present invention provides a display device, including: an insulation substrate including an upper surface and a lower surface; a light blocking member disposed on or facing the upper surface of the insulation substrate and defining a plurality of openings; a thin film transistor disposed on the upper surface of the insulation substrate; and a plurality of color filters formed in the openings. The insulation substrate includes a plurality of recesses formed in the lower surface of the insulation substrate, each recess positioned to correspond to one of the openings. 
     Each recess may include opposing lateral surfaces and a bottom surface extending therebetween. 
     At least one lateral surface may be substantially perpendicular to its corresponding bottom surface. 
     At least one lateral surface may form an angle of about 105° to 150° with respect to its corresponding bottom surface. 
     A cross-sectional shape of each recess may be an arc, sine wave, semicircular, or semi-elliptical shape. 
     The insulation substrate may comprise at least one of polyimide, polyamide, and polycarbonate. 
     A thickness of the insulation substrate may be from about 2 μm to about 50 μm. 
     A height of each recess may be equal to or less than ⅔ of the thickness of the insulation substrate. 
     The display device may further include a passivation film formed below the lower surface of the insulation substrate. 
     According to the exemplary embodiments of the present invention, a thin film transistor array panel and a display device including the same may exhibit increased visibility and thus improved image quality by patterning an area of the display substrate corresponding to a pixel area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a layout view of a thin film transistor array panel included in a display device according to an exemplary embodiment of the present invention. 
         FIG. 2  is a layout view of pixels of a thin film transistor array panel included in a display device according to an exemplary embodiment of the present invention. 
         FIG. 3  is a plan view illustrating a structure of a pixel of the thin film transistor array panel according to an exemplary embodiment of the present invention. 
         FIG. 4  is a cross-sectional view of an embodiment of the thin film transistor array panel of  FIG. 3  taken along line I-I. 
         FIG. 5  is a cross-sectional view of another embodiment of the thin film transistor array panel of  FIG. 3  taken along line I-I. 
         FIG. 6  is a cross-sectional view of a further embodiment of the thin film transistor array panel of  FIG. 3  taken along line I-I. 
         FIG. 7  is a cross-sectional view of a still further embodiment of the thin film transistor array panel of  FIG. 3  taken along line I-I. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. 
     In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The various Figures are thus not to scale. Like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. 
     All numerical values are approximate, and may vary. All examples of specific materials and compositions are to be taken as nonlimiting and exemplary only. Other suitable materials and compositions may be used instead. 
     First, a thin film transistor array panel of a display device according to an exemplary embodiment of the present invention will be described with reference to  FIGS. 1 and 2 .  FIG. 1  is a layout view of a thin film transistor array panel included in a display device according to an exemplary embodiment of the present invention, and  FIG. 2  is a layout view of pixels of a thin film transistor array panel included in a display device according to an exemplary embodiment of the present invention. 
     First, referring to  FIGS. 1 and 2 , a display device according to an exemplary embodiment of the present invention includes a thin film transistor array panel  300 . The thin film transistor array panel  300  may be included in various flat panel displays (FPDs), such as a liquid crystal display (LCD), an organic light emitting diode display (OLED), an electrowetting display (EWD), and the like. 
     In this case, the thin film transistor array panel  300  according to the exemplary embodiment of the present invention may be used in a liquid crystal display in which a roof layer is formed on one substrate and which is manufactured by injecting a liquid crystal layer in a microcavity formed between a substrate and the roof layer. 
     The thin film transistor array panel  300  includes a display area DA displaying an image, and a peripheral area PA disposed around the display area DA. 
     A plurality of signal lines including a plurality of gate lines (GL 1 , GL 2 , GL 3 , and so on) and a plurality of data lines (DL 1 , DL 2 , DL 3 , and so on), and a plurality of pixel areas PX connected to the signal lines, are disposed in the display area DA. 
     The data lines (DL 1 , DL 2 , DL 3 , and so on) transmit data voltages for image signals, and they may substantially extend in a column direction and may be substantially parallel to each other. The gate lines (GL 1 , GL 2 , GL 3 , and so on) transmit gate signals, and they may substantially extend in a row direction and may be substantially parallel to each other. 
     The plurality of pixel areas PX may be substantially arranged in a matrix form. One pixel area PX may include at least one switching element (not shown) connected to at least one data line (DL 1 , DL 2 , DL 3 , and so on) and at least one gate line (GL 1 , GL 2 , GL 3 , and so on), and at least one pixel electrode  191  connected to the at least one switching element. The switching element may include at least one thin film transistor integrated in the thin film transistor array panel  300 . The switching element may be controlled by the gate signals transmitted through the gate lines (GL 1 , GL 2 , GL 3 , and so on), such that the data voltages transmitted through the data lines (DL 1 , DL 2 , DL 3 , and so on) may be transmitted to the pixel electrode  191 . The pixel area PX may display a corresponding image depending on the data voltage applied to the pixel electrode  191 . 
     The pixel area PX of the thin film transistor array panel  300  may be divided into a plurality of openings OA that transmit light, and a light blocking area BA (see  FIGS. 4-7 ) that prevents light leakage between the openings OA. In this case, the thin film transistor array panel  300  may include a light blocking member (not shown) disposed to differentiate the opening OA and the light blocking area BA, that is, to form the light blocking area BA. The light blocking member is referred to as a black matrix, and it prevents light leakage between pixels. The signal lines such as the gate lines (GL 1 , GL 2 , GL 3 , and so on), the data lines (DL 1 , DL 2 , DL 3 , and so on) and the like, and at least some of the switching elements disposed in the pixel area PX, may be covered by the light blocking member of the pixel area PX. 
     Next, further details of the thin film transistor array panel of the display device according to an exemplary embodiment of the present invention will be described with reference to  FIGS. 3 to 7  and the above-described drawings. 
       FIG. 3  is a plan view illustrating a structure of a pixel of the thin film transistor array panel according to an exemplary embodiment of the present invention, and  FIGS. 4 to 7  are cross-sectional views of different embodiments of the thin film transistor array panel of  FIG. 3  taken along line I-I. 
     Referring to  FIGS. 3 and 4 , the thin film transistor array panel  300  of the display device according to the exemplary embodiment of the present invention may include an insulation substrate  110  that is made of transparent plastic or the like, and that includes an upper surface and a lower surface. 
     The insulation substrate  110  may be formed of a polyimide, polyamide, or polycarbonate. The polyimide, the polyamide, or the polycarbonate has excellent mechanical strength and a maximum process feasible temperature of about 450° C. to secure excellent heat resistance as compared to other polymer materials. Accordingly, the insulation substrate  110  formed of polyimide, polyamide, or polycarbonate may stably function as a substrate even though high temperature heat is applied thereto while forming the thin film transistor. 
     A thickness (d) of the insulation substrate  110  may be equal to or less than about 50 μm for slimness of the thin film transistor array panel  300  and the display device including the thin film transistor array panel  300 , and it may be equal to or greater than about 2 μm so that a structure stacked on the insulation substrate  110  may be adequately supported. 
     The lower surface of the insulation substrate  110  may include at least one concavity  111  or recess formed to face (i.e. formed or positioned within) the opening OA that light of the pixel transmits through. 
     Generally, the degree of transparency of the insulation substrate  110  is proportional to the thickness (d) of the substrate, and phase retardation thereof is inversely proportional to the thickness (d) of the substrate. 
     Since the thin film transistor array panel  300  includes the concavity(s)  111  positioned to correspond to the opening OA that passes light therethrough, the thickness of the insulation substrate  110  is reduced in the area of the opening OA. 
     That is, since a thickness of the insulation substrate  110  in an area that is viewed by a user is reduced, transparency of the insulation substrate  110  may increase and phase retardation may decrease, thus improving image quality of the display. Although the concavity  111  is shown as being formed only in the substrate  110 , it may also be formed in other layers that have been deposited on substrate  110 . That is, concavity  111  may not only extend into substrate  110 , but may also extend into or through other layers formed on substrate  110 . Embodiments of the invention contemplate concavities  111  that extend into or through any number of layers in addition to substrate  110 . 
     In this case, the concavity  111  may be formed in the lower surface of the insulation substrate  110  corresponding to the opening OA, by various methods. For example, the concavity  111  may be formed by a chemical etching method using a hydrazine-based alkali solution, or it may be formed by processing etching gas into plasma and dry-etching the insulation substrate  110 . Further, the concavity  111  may be formed by irradiating a laser beam on the insulation substrate, and it may also be formed by an imprinting method. Any method of forming an opening, cavity, recess, or cutout is contemplated. 
     The concavity  111  may include lateral surfaces  113  and a bottom surface  112  extending between the lateral surfaces  113 . Referring to  FIG. 4 , each lateral surface  113  of the concavity  111  may be substantially perpendicular to the bottom surface  112  so that a cross-section of the concavity  111  may be rectangular. 
     In this case, as a difference between a height (h) of the concavity  111  and the thickness (d) of the insulation substrate is smaller, transparency of the insulation substrate  110  is improved. Preferably, the height (h) of the concavity  111  may be equal to or less than ⅔ of the thickness (d) of the insulation substrate in order to ensure adequate support for the various structures stacked on the insulation substrate  110 . 
     However, a cross-sectional shape of the concavity  111  is not limited thereto, and it may be varied according to various exemplary embodiments. Referring to  FIG. 5 , the lateral surface  113  of concavity  111  may form an angle of about 105° to 150° with respect to the bottom surface  112 , so that a cross-section of the concavity  111  may be trapezoidal. Any numerical value is contemplated for this angle. 
     According to the present exemplary embodiment, the lateral surfaces  113  of the concavity  111  are not necessarily coated by a separate coating process. 
     Referring to  FIGS. 6 and 7 , a cross-section of the concavity  111  may be an arc, sine wave, semicircular, or semi-elliptical shape. Any arcuate or nonlinear profile is contemplated. 
     A passivation film (not shown) may be disposed below the concavity  111 . The passivation film is disposed in a lower portion of the insulation substrate  110  to protect the thin film transistor array panel  300  and the display device including the thin film transistor array panel. Further, the passivation film may prevent the concavity  111  of the insulation substrate  110  from being visible to a user. 
     Since the passivation film is formed as a multi-layered structure, a mechanical strength of the thin film transistor array panel  300  may increase, and the passivation film may include a moisture prevention layer (not shown) for preventing penetration of moisture. 
     A plurality of gate lines  121  is disposed on an upper surface of the insulation substrate  110 . The gate lines  121  transmit gate signals, and may extend substantially in a horizontal direction. The gate lines  121  may extend not only to the display area (DA) of the thin film transistor array panel  300  but also to the peripheral area (PA) of the thin film transistor array panel  300 , and they may include a plurality of gate electrodes  124  disposed in the display area (DA). 
     A gate insulating layer  140  made of, for example, a silicon nitride (SiNx) or a silicon oxide (SiOx) is disposed on the gate line  121 . 
     A plurality of semiconductor layers  154  may be disposed on the gate insulating layer  140  of the display area (DA). Each of the semiconductor layers  154  is disposed on a corresponding gate electrode  124 . The semiconductor layers  154  may be made of hydrogenated amorphous silicon, polysilicon, oxide semiconductor, or the like. 
     A pair of ohmic contact members  163  and  165  may be disposed on each of the semiconductor layers  154 . The ohmic contact members  163  and  165  may be formed of a material such as n+ hydrogenated amorphous silicon, in which an n-type impurity such as phosphorus is doped at a high concentration, or silicide. Alternatively, the ohmic contact members  163 ,  165  may be omitted. 
     A plurality of data lines  171  are disposed on the ohmic contact members  163  and  165 , and the gate insulating layers  140 . The data lines  171  are disposed in the display area (DA). Further, a plurality of drain electrodes  175  of the display area (DA) may be disposed on the ohmic contact members  163  and  165 , and the gate insulating layer  140 . 
     The data lines  171  substantially extend in a vertical direction to cross the gate lines  121 . Each of the data lines  171  may include a source electrode  173  extending toward the gate electrode  124 . 
     The drain electrode  175  may face the source electrode  173  over the gate electrode  124 . 
     The gate electrode  124 , the source electrode  173 , and the drain electrode  175  may collectively form a thin film transistor Q in one pixel area PX, together with the semiconductor  154 . 
     A passivation layer  180  is disposed on the data line  171 . The passivation layer  180  may be made of a material such as an inorganic insulation material or an organic insulation material. 
     The passivation layer  180  includes a contact hole  185  exposing the drain electrode  175 . 
     A plurality of pixel electrodes  191  is disposed on the passivation layer  180 . 
     Each pixel electrode  191  is physically and electrically connected to a corresponding drain electrode  175  through the corresponding contact hole  185 , so as to receive a data voltage from that drain electrode  175 . 
     The pixel electrodes  191  may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof. 
     In the display area (DA), a thin film transistor Q and the pixel electrode  191  connected thereto may form one pixel area PX. 
     The pixel area PX of the thin film transistor array panel  300  may be divided into a plurality of openings OA that light of the pixel transmits through, and a light blocking area BA that prevents light leakage between the openings OA. In this case, the thin film transistor array panel  300  may include a light blocking member (not shown) disposed to differentiate the opening OA and the light blocking area BA. The light blocking member is referred to as a black matrix, and it prevents light leakage between pixels. The signal lines such as the gate lines (GL 1 , GL 2 , GL 3 , and so on), the data lines (DL 1 , DL 2 , DL 3 , and so on), and the like, and at least some of the switching elements disposed in the pixel area PX, may be covered by the light blocking member of the pixel area PX. 
     While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Furthermore, different features of the various embodiments, disclosed or otherwise understood, can be mixed and matched in any manner to produce further embodiments within the scope of the invention. 
     
       
         
               
             
               
               
               
             
               
               
             
               
               
               
             
           
               
                   
               
               
                 &lt;Description of symbols&gt; 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 110: insulation substrate 
                 111: concavity 
               
               
                   
                 112: bottom surface 
                 113: lateral surface 
               
               
                   
                 121: gate line 
                 124: gate electrode 
               
               
                   
                 140: gate insulating layer 
                 154: semiconductor 
               
               
                   
                 171: data line 
                 173: source electrode 
               
               
                   
                 175: drain electrode 
                 180: passivation layer 
               
               
                   
                 185: contact hole 
                 191: pixel electrode 
               
             
          
           
               
                   
                 300: thin film transistor array panel 
               
             
          
           
               
                   
                 DA: display area 
                 PA: peripheral area 
               
               
                   
                 OA: opening 
                 Q: switching element 
               
               
                   
                 PX: pixel area