Abstract:
A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to integrated circuits, and, more particularly, to a digital delay interpolator. 
       BACKGROUND 
       [0002]    Digital delay interpolation is a method for performing a fine delay with a better resolution. FIG. 1 shows a prior art digital delay interpolator, disclosed in the U.S. Published Patent Application No. 2003/0006817. This delay interpolator comprises a plurality of delay stages to control delay time of an output signal from two input signals having different phase delays. The digital delay interpolator includes four delay stages (100-110-120-130) that have the same internal structure. The first delay stage 100 includes inverters 510, 520, 530, 540, a phase mixer 550, and a multiplexer 3×2 560. The input signals IN1 and IN2 are inverted by inverters 510, 520 that provide the inverted replicas thereof to the phase mixer 550. The phase mixer 550 includes inverters 552, 554 having outputs connected to each other, and generates the first phase mixing signal PB1 (see FIG. 2) having an intermediate phase between the signals IN1D and IN2D. The signals IN1D and IN2D are inverted by the inverters 530, 540 and the multiplexer 560 generates the output signals OUT1 and OUT2 by selecting one of signals outputted by the inverters 530, 540, and the phase mixed signal PB1. The delay stages 110, 120 and 130 are identical to the first delay stage 100. 
         [0003]    With this architecture, the signal outputted from the fourth stage 130 has a delay resolution equal to Δ/6, wherein Δ is the delay between the input signals IN1 and IN2 of the first stage 100. In order to obtain a resolution equal to Δ/2 K , K stages in cascade are necessary. Therefore, the accuracy of this delay interpolator may be enhanced only by increasing the number of stages in cascade, that may cause relatively long propagation delays along the whole structure and a large power consumption. 
       SUMMARY 
       [0004]    The present applicant has found that it is possible to realize a digital delay interpolator by using 2×1 multiplexers as building blocks connected in parallel to each other. 
         [0005]    In particular, it has been found that it is possible to obtain any phase mixing resolution without connecting stages in cascade, with a single-stage digital delay interpolator, that may comprise an array of multiplexers, preferably identical to each other, configured to be input with first (IN 1 ) and second (IN 2 ) input voltages, one delayed in respect to the other. The multiplexers of the array may be configured to selectively output on respective output lines either the first (IN 1 ) or the second (IN 2 ) input voltage depending on the logic value of a respective selection signal and being configured such that their output lines are connected in common to an output line (SOUT) of the single-stage digital delay interpolator. 
         [0006]    Optionally, in order to further enhance the resolution of the delay, it is possible to realize a mixed series-parallel architecture by connecting in cascade a plurality of stages each composed of multiplexers connected in parallel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a diagram of a prior art digital delay interpolator. 
           [0008]      FIG. 2  is a time graph that schematically shows the output signals of the circuit depicted in  FIG. 1 . 
           [0009]      FIG. 3  depicts a two-input multiplexer and time graphs that illustrate its functioning. 
           [0010]      FIG. 4  depicts a parallel connection of N two-input multiplexers and associated time graphs. 
           [0011]      FIG. 5  depicts a connection of N two-input multiplexers according to the present disclosure and shows and relative time graphs. 
           [0012]      FIG. 6  is an embodiment of a single-stage mux-based digital delay interpolator, according to the present disclosure. 
           [0013]      FIG. 7  is an embodiment of a multi-stage mux-based digital delay interpolator, according to the present disclosure. 
           [0014]      FIG. 8  is an embodiment of a two-stage mux-based digital delay interpolator with N1=N2=4, according to the present disclosure. 
           [0015]      FIG. 9  is a time graph that schematically shows the output signals and other possible blending signals (with dashed line) of the interpolator of  FIG. 8 . 
           [0016]      FIG. 10  is an embodiment of a two-stage flipped mux-based digital delay interpolator, according to the present disclosure. 
           [0017]      FIG. 11  is an embodiment of a m-bit single stage flipped mux-based digital delay interpolator, according to the present disclosure. 
           [0018]      FIG. 12  is a time graph that schematically shows the output signals and other possible blending signals (with dashed line) of the interpolator of  FIG. 11 . 
           [0019]      FIG. 13  is an embodiment of a multi-stage flipped mux-based digital delay interpolator, according to the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    For sake of clarity, in the ensuing description reference will be made to the case in which the digital delay interpolator illustratively includes a plurality of identical multiplexers, though similar observations hold mutatis mutandis if the multiplexers are different from each other. 
         [0021]    The present disclosure provides a digital delay interpolator constructed by using 2×1 multiplexers as building blocks (“mux-based” digital delay interpolator). Differently from the typical digital delay interpolators discussed above, the digital delay interpolator of the present disclosure controls the delay time of an output signal, from two input signals having different phase delay, without using inverters. This may save a relevant amount of silicon area, as will be explained hereinafter. 
         [0022]    Referring to  FIG. 3 , in order to understand how a digital delay interpolator can be realized using only multiplexers, a multiplexer and the graphs that illustrate its functioning are shown. When a selected input signal VIN undergoes to a step variation, the output signal VOUT of the multiplexer does not vary for a certain time ti, that represents the intrinsic delay of the multiplexer, then varies substantially linearly during a time interval tr, called rise-time of the multiplexer, as far as the output VOUT equals the supply voltage VDD. Therefore, the total delay time of the multiplexer td, i.e. the time elapsed from the instant at which the step variation of the selected input occurs and the instant at which the output VOUT overcomes VDD/2, is 
         [0000]    
       
         
           
             
               t 
               d 
             
             = 
             
               
                 t 
                 i 
               
               + 
               
                 
                   
                     t 
                     r 
                   
                   2 
                 
                 . 
               
             
           
         
       
     
         [0000]    The rise-time tr of the multiplexer is determined by the output capacitance of the multiplexer and by a pull-up/pull-down current delivered by the multiplexer for charging/discharging its output capacitance. 
         [0023]    When a plurality of N identical multiplexers are connected in parallel and selects a same input VIN as shown in  FIG. 4 , the overall pull-up/pull-down current is multiplied by N. By neglecting the fanout load capacitance of the interpolator, also the overall output capacitance is multiplied by N, the rise-time tr is unchanged and so is the total delay time td.  FIG. 5  shows the case in which a step signal VIN 1  is selected by a number x of multiplexers and a replica step signal VIN 2  delayed by a delay A is selected by the remaining N−x multiplexers. From the instant t=ti up to the instant t=ti+Δ, the overall output capacitance of the parallel connection is N times the output capacitance of a single multiplexer, though it is charged by x multiplexers. Therefore, the output signal VOUT varies substantially according to the following equation: 
         [0000]    
       
         
           
             
               
                 V 
                 OUT 
               
               = 
               
                 
                   V 
                   DD 
                 
                  
                 
                   
                     
                       t 
                       - 
                       
                         t 
                         i 
                       
                     
                     
                       t 
                       r 
                     
                   
                   · 
                   
                     x 
                     N 
                   
                 
               
             
             , 
           
         
       
     
         [0000]    in the hypothesis that the pull-down/pull-up current sunk by the N−x multiplexers is negligible with respect to the pull-up/pull-down current delivered by the x multiplexers. At a time t1=ti+Δ, the output signal VOUT is thus 
         [0000]    
       
         
           
             
               
                 V 
                 OUT 
               
                
               
                  
                 
                   
                     t 
                     1 
                   
                   = 
                   
                     
                       t 
                       j 
                     
                     + 
                     Δ 
                   
                 
               
             
             = 
             
               
                 V 
                 DD 
               
                
               
                 
                   Δ 
                   
                     t 
                     r 
                   
                 
                 · 
                 
                   
                     x 
                     N 
                   
                   . 
                 
               
             
           
         
       
     
         [0024]    From the instant t1=ti+Δ onwards, all the N multiplexers charge the output capacitance of the parallel connection of multiplexers, thus the output signal VOUT is 
         [0000]    
       
         
           
             
               V 
               OUT 
             
             = 
             
               
                 V 
                 OUT 
               
                
               
                  
                 
                   
                     t 
                     1 
                   
                   = 
                   
                     
                       t 
                       i 
                     
                     + 
                     Δ 
                   
                 
               
                
               
                 
                   + 
                   
                     V 
                     DD 
                   
                 
                  
                 
                   
                     
                       t 
                       - 
                       Δ 
                       - 
                       
                         t 
                         i 
                       
                     
                     
                       t 
                       r 
                     
                   
                   . 
                 
               
             
           
         
       
     
         [0025]    Therefore, if Δ&lt;t r /2, the output VOUT surpasses the intermediate discrimination threshold VDD/2 at a time instant t=td for which 
         [0000]    
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 2 
               
               = 
               
                 
                   V 
                   OUT 
                 
                  
                 
                    
                   
                     
                       t 
                       1 
                     
                     = 
                     
                       
                         t 
                         i 
                       
                       + 
                       Δ 
                     
                   
                 
                  
                 
                   
                     + 
                     
                       V 
                       DD 
                     
                   
                    
                   
                     
                       
                         t 
                         d 
                       
                       - 
                       Δ 
                       - 
                       
                         t 
                         i 
                       
                     
                     
                       t 
                       r 
                     
                   
                 
               
             
             , 
           
         
       
     
         [0000]    that is 
         [0000]    
       
         
           
             
               t 
               d 
             
             = 
             
               
                 t 
                 i 
               
               + 
               
                 
                   t 
                   r 
                 
                 2 
               
               + 
               
                 Δ 
                 · 
                 
                   
                     
                       N 
                       - 
                       x 
                     
                     N 
                   
                   . 
                 
               
             
           
         
       
     
         [0026]    The above equation demonstrates that, by connecting in parallel a plurality of multiplexers and applying a same step input signal VIN to an input terminal of x multiplexers controlled to select the input signal VIN, and applying to the remaining N−x multiplexers a replica of the step input signal VIN delayed by a delay Δ&lt;t r /2, the total delay time td of the parallel connection depends linearly on the number x and is between 
         [0000]    
       
         
           
             
               t 
               i 
             
             + 
             
               
                 t 
                 r 
               
               2 
             
           
         
       
       
         
           and 
         
       
       
         
           
             
               t 
               i 
             
             + 
             
               
                 t 
                 r 
               
               2 
             
             + 
             
               Δ 
               . 
             
           
         
       
     
         [0000]    It is possible to show that a similar result holds also considering an additional fanout load capacitance of the interpolator. 
         [0027]    Therefore, it is possible to realize a delay interpolator made only of properly controlled multiplexers connected in parallel to each other, without using inverters. For example, the single-stage digital delay interpolator of  FIG. 6  is capable of generating an output SOUT with a delay determined with an accuracy of Δ/N, Δ being the delay between the input signals IN 1  and IN 2 . 
         [0028]      FIG. 7  depicts a multi-stage mux-based digital delay interpolator, that includes a generic number K of delay stages in cascade. With the exception of last stage, each stage includes two pluralities of Ni 2×1 multiplexers. The two input signals of each multiplexers of the generic i-th stage are the two signals outputted from the previous stage ((i−1)th) having a different phase delay. Both pluralities of multiplexers have outputs connected to each other, thus two signals are outputted from each but the last stage. Control signals are provided to the multiplexers in order to choose the signals in input to the multiplexers to be outputted to the next stage. Being 2·Ni, the number of multiplexers of the generic i-th stage (with the exception of the last stage, comprising NK multiplexers), the overall delay phase resolution (minimum delay step) of the mux-based delay interpolator is given by Δ/N, where N=N1· . . . ·NK. 
         [0029]    An exemplary embodiment of a mux-based digital delay interpolator with K=2 (two stages) and N1=N2=4 is shown in  FIG. 8 . The signals IN 1  (phase delay equal to 0) and IN 2  (phase delay equal to Δ) are the input signals of the first delay stage  310  in the cascade. Referring to  FIG. 8  and  FIG. 9 , when F 10 =0, F 11 =0, F 12 =0 the signal IN 1  is selected by the multiplexers  410 ,  420 ,  430 ,  440 ,  460 ,  470 ,  480  and the signal IN 2  is selected by the multiplexer  450 , thus, apart a constant delay offset given by ti+tr/2, the output signal OUT 2  is the phase mixing signal PB 1  with a phase delay equal to Δ/4 and the output signal OUT 1  is the selected signal IN 1 . Therefore, the phase difference between OUT 1  and OUT 2  is equal to Δ/4. 
         [0030]    Referring to  FIG. 8  and  FIG. 9 , when F 10 =0, F 11 =0, F 12 =1, the signal IN 1  is selected by the multiplexers  410 ,  420 ,  430 ,  460 ,  470 , and the signal IN 2  is selected by the multiplexers  440 ,  450 ,  480 ; thus, apart a constant delay offset given by ti+tr/2, the output signal OUT 1  is the phase mixing signal PB 1 , with a phase delay equal to Δ/4, and the output signal OUT 2  is the phase mixing signal PB 2  with phase delay equal to Δ/2. The phase difference between OUT 1  and OUT 2  is equal to Δ/4. 
         [0031]    When F 10 =0, F 11 =1, F 12 =1, the signal IN 1  is selected by the multiplexers  410 ,  420 ,  460 , and the signal IN 2  is selected by the multiplexers  430 ,  440 ,  450 ,  470 ,  480 ; therefore, apart a constant delay offset given by ti+tr/2, the output signal OUT 1  is the phase mixing signal PB 2  with a phase delay equal to A/2 and the output signal OUT 2  is the phase blending signal PB 3  with phase delay equal to 3Δ/4. The phase difference between OUT 1  and OUT 2  is equal to Δ/4. 
         [0032]    Finally when F 10 =1, F 11 =1, F 12 =1, then the signal IN 1  is selected by the multiplexer  410 , and the signal IN 2  is selected by the multiplexers  420 ,  430 ,  440 ,  450 ,  460 ,  470 ,  480 . Therefore, apart a constant delay offset given by ti+tr/2, the output signal OUT 1  is the phase mixed signal PB 3  with phase delay equal to 3Δ/4, and the output signal OUT 2  is the selected signal IN 2  (phase delay equal to Δ). The phase difference between OUT 1  and OUT 2  is equal to Δ/4. 
         [0033]    Referring to  FIG. 8 , the last stage  320  includes only one plurality of multiplexers ( 610 ,  620 ,  630 ,  640 ) in order to generate the output signal SOUT of the digital delay interpolator. Let us indicate as Δ2 the phase delay between OUT 1  and OUT 2 , Δ 2 =Δ/4 according to previous description. The output signal of the final delay stage SOUT is generated in response to the control code bits F 20 , F 21 , F 22 , F 23 . 
         [0034]    To exemplify the operation of the present disclosure, let us assume for the first stage  310 , F 10 =0, F 11 =1, F 12 =1 so that, referring to  FIG. 8  and  FIG. 9 , signal OUT 1  is the phase mixed signal PB 2 , and signal OUT 2  is the phase mixing signal PB 3 . When F 20 =0, F 21 =0, F 22 =0, F 23 =0, the signal OUT 1  is selected by all the multiplexers  610 ,  620 ,  630 ,  640 , of the last stage, so, apart a constant delay offset given by ti+tr/2, the signal SOUT is the selected signal OUT 1 . 
         [0035]    When F 20 =0, F 21 =0, F 22 =0, F 23 =1, the signal OUT 1  is selected by the multiplexers  610 ,  620 ,  630 , and the signal OUT 2  is selected by the multiplexer  640 ; in this way, apart a constant delay offset given by ti+tr/2, the signal SOUT is the phase mixing signal PB 4  with a phase delay Δ 2 /4 from OUT 1 . When F 20 =0, F 21 =0, F 22 =1, F 23 =1, the signal OUT 1  is selected by the multiplexers  610 ,  620 , and the signal OUT 2  is selected by the multiplexers  630 ,  640 . In this way, the signal SOUT, apart a constant delay offset given by ti+tr/2, is the phase mixing signal PB 5  with a phase delay Δ 2 /2 from OUT 1 . 
         [0036]    Similarly when F 20 =0, F 21 =1, F 22 =1, F 23 =1, the signal OUT 1  is selected by the multiplexer  610 , and the signal OUT 2  is selected by the multiplexers  620 ,  630 ,  640 . In this way, the signal SOUT, apart a constant delay offset given by ti+tr/2, is the phase mixing signal PB 6  with a phase delay 3Δ 2 /4 from OUT 1 . 
         [0037]    Finally, when F 20 =1, F 21 =1, F 22 =1, F 23 =1, the signal OUT 2  is selected by all the multiplexers  610 ,  620 ,  630 ,  640 , of the last stage; in this way the signal SOUT is, apart a constant delay offset given by ti+tr/2, the selected signal OUT 2 . Therefore, the interpolator of  FIG. 8  allows generating a phase mixing signal SOUT with a resolution (delay step) equal to Δ/(N 1 ·N 2 )=Δ/16, using only two delay stages in cascade. 
         [0038]    In the architecture of  FIG. 8 , an eventual mismatch between the two propagation paths of the inputs of the two multiplexers may cause imperfect equally spaced phase mixing signals. This asymmetry may add up among all multiplexers in each stage, thus worsening the integral nonlinearity (INL) of the delay characteristic of the interpolator. 
         [0039]    This effect can be reduced by using the flipped stages shown in  FIG. 10 , wherein the role of the inputs of some of the multiplexers is switched and the respective control signals of the multiplexers are inverted. In this embodiment, the inputs D 0  and D 1  of multiplexers  711 ,  713 ,  715 ,  717  are connected to IN 1  and IN 2 , respectively, and the inputs D 0  and D 1  of multiplexers  712 ,  714 ,  716  and  718  are connected to IN 2  and IN 1 , respectively. This “flipped” architecture avoids the accumulation of asymmetries among more than just one multiplexer and thus reduces the integral nonlinearity (INL). 
         [0040]      FIG. 11  shows an embodiment of a Ni-bit flipped single stage MUX-based digital delay interpolator ( 810 ) that includes Ni multiplexers. The Ni-bit single stage of delay interpolator allows to generate Ni−1 possible phase mixing signal ( FIG. 12 ) using only one delay stage. The output signal SOUT is a selected signal between the phase mixing signals and the input signals IN 1  and IN 2  in response to the control signals FK 0 , FK 1 , FK 2 , . . . , FKj, . . . , FKNi−1. 
         [0041]    The “flipped” architecture of the digital delay interpolator may compensate for certain second order effects that increase the INL. For example, the output capacitance on the output of the multiplexers depends upon the values of the control signals of the multiplexers. Moreover, the intrinsic delay time ti and the pull-up/pull-down current of each multiplexer may depend upon the logic value of the respective control signal. In the “flipped” architecture, there are about N/2 multiplexers whose control signal is 0 and about N/2 multiplexers whose control signal is 1. Therefore, the output capacitance of the flipped stage remains substantially constant and the non-linear behavior due to dependence of the intrinsic delay time ti and the pull-up/pull-down currents on the control signals values is substantially reduced.  FIG. 13  shows the generalization to the multi-stage case of the flipped single stage MUX-based digital delay interpolator shown in  FIG. 11 .