Abstract:
An amplifier circuit performs audio signal processing and other signal processing by using a noise reduction feedback network. The noise reduction feedback network turns on automatically when output signals are in or near voltage saturation state. The network provides feedback signals to the input terminals of the amplifier&#39;s control stage and modulates the control signals. It prevents audio frequency noise associated with “clipping”.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to U.S. provisional patent application Ser. No. 60/620,149, filed on Oct. 18, 2004, which is hereby incorporated herein by reference. 
     
    
     TECHNICAL FIELD  
       [0002]     The present invention relates generally to audio signal processing, and in particular, relates to a system that includes a Class D amplifier for audio signal amplification and other audio signal processing.  
       BACKGROUND INFORMATION  
       [0003]     Class-D audio amplifiers are often used for audio amplification because of their power efficiency. Typically, the Class D audio amplifier is operated in the switch mode with minimized internal power consumption. It produces a rectangular wave at the output stage that is filtered before delivered to a load. The filtered signal wave is an amplified version of the input signal wave. Class D audio amplifiers are usually used for high power applications. For low power applications, Class A/B amplifiers are still popular.  
         [0004]     When the input audio signal exceeds the audio amplifier&#39;s linear range, the output of the amplifier saturates. Oscillations at the audible band are often observed when the amplifier enters the saturation condition and exits the saturation condition, as indicated in  FIG. 6 . This may result in the “clipping” of audible noises. This problem is more severe in the class D audio amplifier because the switching power supply can skip switching cycles due to the minimum on and off time constraints. If the power supply skips sufficient cycles, the effective operation frequency may enter the audible frequency range and induce unexpected audible noises.  
         [0005]     There are several known methods to resolve the problem. The first method is to limit the amplitude of the input signal with a clamping circuit. However, without information on the audio source&#39;s output impedance, this may not be practical and can degrade the audio signal quality. The second method is to add an automatic gain control (AGC) pre-amplifier before the input of the class-D audio amplifier. This AGC pre-amplifier limits the input signal amplitude to prevent the output saturation, but the implementation is rather complex and adds a significant cost. The limitation may get more severe for low frequency audio signals. The third method is to add a high-pass filter to limit the minimum audio frequency passing into the class-D amplifier, but may not solve the problem completely.  
         [0006]     Accordingly, more improvements are needed to reduce audio noise near saturation in the class D audio amplifier.  
       SUMMARY  
       [0007]     The following embodiments and aspects are illustrated in conjunction with systems, circuits, and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements.  
         [0008]     A method introduces a noise reduction feedback network. The noise reduction feedback network is coupled to an output stage and a control stage of an audio amplifier. It includes a detect circuit and a modulation circuit. The detect circuit is coupled to the output stage to monitor output voltages, detect output voltages near saturation states, and produce a control signal or multiple control signals to the modulation circuit. Once output voltages are near saturation state, the modulation circuit produces adjustable currents to the control stage to modulate output signal(s) and remove audible oscillations near saturation.  
         [0009]     In a non-limiting embodiment, the detect circuit may include two back-to-back transistors or two back-to-back “Zener” diodes being coupled to the output stage. The two transistors are activated once the output voltages are in the near saturation states. Adjustable signals are produced by the modulation circuit according to the output voltages when two transistors are activated. These adjustable signals feed back to the control stage. The sinusoidal output waveforms become more “curved” rather than being clipped in near saturation region.  
         [0010]     In another non-limiting embodiment, the detect circuit may include a transistor coupled between a supply voltage, Vcc, and the output stage, and a second transistor coupled between the ground and the output stage. Both transistors are activated as long as the output voltage is not in a near saturation state. The first transistor becomes deactivated once the output voltage is near the Vcc region and the second transistor becomes deactivated once the output voltage is near the ground voltage region. The first transistor is also coupled to a third transistor in the current circuit. These two transistors are such coupled that the third transistor is only activated once the first transistor is deactivated and becomes deactivated once the first transistor is activated. The second transistor is also coupled to a fourth transistor in the current circuit. These two transistors are such coupled that the fourth transistor is only activated once the second transistor is deactivated and becomes deactivated once the second transistor is activated. If the output voltage is near saturation state, either the third transistor or the fourth transistor in the current circuit produces an adjustable current to the control stage to modulate the output signals. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0011]     The following figures illustrate embodiments of the invention. These figures and embodiments provide examples of the invention and they are non-limiting and non-exhaustive.  
         [0012]      FIG. 1  is a circuit schematic showing embodiments of a system having a Class D amplifier and other components that are useable for audio signal amplification and other audio signal processing.  
         [0013]      FIG. 2  is an example of the invention in a bridge tied load (BTL) Class D amplifier.  
         [0014]      FIG. 3  shows output waveforms with and without the invention in the BTL Class D amplifier.  
         [0015]      FIG. 4  is a circuit block diagram showing embodiments of a system having an audio amplifier and other components that are useable for audio signal amplification and other audio signal processing.  
         [0016]      FIG. 5  is another example of a noise reduction feedback network.  
         [0017]      FIG. 6  shows a waveform with “clipping” audible noise in an amplifier without the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0018]     Embodiments of a system and method that uses an audio amplifier and accompanying circuitry to achieve low noise audio signal amplification and other audio signal processes are described in detail herein. In the following description, some specific details, such as example circuits and example values for these circuit components, are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc.  
         [0019]     The present invention relates to circuits and methods of producing low noise amplified audio signals. Proposed circuits in an audio amplifier can monitor output signals, detect output signals near saturation state, and produce an adjustable current to a control stage of the amplifier to modulate output signals and remove oscillation near saturation.  
         [0020]      FIG. 1  is an embodiment of a system according to the invention. The system comprises a control stage, A, an output stage, O, and a noise reduction feedback network, Y.  
         [0021]     An input signal, Vin, is coupled to an input node, X 1 , through a capacitor, Cin 1 , and a resistor, Rin 1 . Another input node, X 2 , is coupled to ground through a resistor, Rin 2 , and a capacitor, Cin 2 . The nodes, X 1  and X 2 , are coupled together by a capacitor, C 2 . The signals at the node, X 1 , comprise three components: AC portions of Vin, a feedback signal from the node, S 1 , and a feedback signal from the upper portion of a noise reduction feedback network, Y. The signals at the node, X 2 , comprise three components: a portion of signal from X 1  coupled through C 2 , a feedback signal from the node, S 2 , and a feedback signal from the lower portion of the noise reduction feedback network, Y.  
         [0022]     The control stage A includes 4 transistors, M 1 , M 2 , M 3 , and M 4 , that serve as power output switching devices. M 1  and M 2  drive output switching node, S 1 ; while M 3  and M 4  drive output switching node, S 2 . In the upper half of the control stage A, M 2 &#39;s source terminal is coupled to ground and M 1 &#39;s drain terminal is coupled to a power supply, Vcc. M 2 &#39;s drain terminal and M 1 &#39;s source terminal are both coupled to the switching node S 1 . The node S 1  is coupled to the input node, X 1 , through a resistor, Rfb 1 . In the lower half of the control stage A, M 4 &#39;s source terminal is coupled to ground and M 3 &#39;s drain terminal is coupled to the power supply, Vcc. M 4 &#39;s drain terminal and M 3 &#39;s source terminal are both coupled to the switching node S 2 . The node S 2  is coupled to the input node, X 2 , through a resistor, Rfb 2 .  
         [0023]     The noise reduction feedback network comprises adjustable current sources (I 1  and I 2 ), and a control circuit triggered by the output signal difference between V+ and V−, Vd. The control circuit is in an “OFF” state unless Vd exceeds a preset voltage level. The adjustable current sources are controlled by the control circuit. When current sources are turned on by the control circuit, extra current flows to the input nodes, X 1 , and X 2 . This extra current sets the minimum switching frequencies of two comparators, CMP 1  and CMP 2 , in the control stage A. The input node, X 1 , is a negative summing node for the comparator, CMP 1 , and it is a positive summing node for the comparator, CMP 2 . The input node, X 2 , is a positive summing node for the comparator, CMP 1 , and it is a negative summing node for the comparator, CMP 2 . The output signal of CMP 1  provides an input signal of a logic gate driver, LDR 1 . An output of LDR 1 , LDR 11 , drives the gate of the transistor, M 1 . Another output of LDR 1 , LDR 12 , drives the gate of the transistor, M 2 . The output signal of CMP 2  provides an input signal of a logic gate driver, LDR 2 . An output of LDR 2 , LDR 21 , drives the gate of the transistor, M 3 . Another output of LDR 2 , LDR 22 , drives the gate of the transistor, M 4 .  
         [0024]     In output stage, O, a rectangular waveform at the node S 1  is filtered by an inductor, LL 1 , and a capacitor, Cout 1 , which is coupled to ground, and then delivered to an output node, V+. A rectangular waveform at the node S 2  is filtered by an inductor, LL 2 , and a capacitor, Cout 2 , which is coupled to ground, and then delivered to an output node, V−. The output stage O is used to drive a load, such as a loudspeaker, SP. A capacitor, C 3 , is connected in parallel with SP and coupled between V+ and V−.  
         [0025]     An example of one embodiment of the present invention used in a bridge tied load (BTL) Class D amplifier is shown  FIG. 2 . The system comprises a class D amplifier circuit AA, an output stage, OO, and a noise reduction feedback network, YY.  
         [0026]     An input signal is coupled to a node XX 1  through a capacitor, C 6 , and a resistor R 3 . Ground is coupled to a node XX 2  through a capacitor, C 28 , and a resistor R 6 . The capacitor, C 6 , is introduced to block DC components of input signal. XX 1  and XX 2 , are coupled by a capacitor, C 12 . The signal at a node SW 1  is fed back to XX 1  through a resistor, R 10 , a grounded capacitor, C 17 , and a resistor, R 11 . The signal at a node SW 2  is fed back to XX 2  through a resistor, R 18 , connected to a grounded capacitor, C 16 , and through a resistor, R 19 .  
         [0027]     The rectangular waveform at SW 1  is filtered by an inductor, L 1 , and a capacitor, C 7 , and then delivered to an output node OUT  1 +. The rectangular waveform at SW 2  is filtered by an inductor, L 2 , and a capacitor, C 22 , and then delivered to an output node OUT  1 −. The stage OO further includes a loudspeaker, SP 1 :A, and a capacitor, C 9 , connected in parallel with SP 1 :A and coupled between OUT  1 + and OUT  1 −. C 9  filters high frequency noise between nodes OUT 1 + and OUT 1 −.  
         [0028]     The noise reduction feedback network YY connects the output node, OUT 1 + and OUT 1 −, and the input nodes, XX 1  and XX 2 . A node, T 1 , is connected with OUT 1 + through a resistor, R 30 . A node, T 2 , is connected with OUT 1 − through a resistor, R 31 . The node T 1  is connected with the node T 2  through a resistor R 29 . The combination of R 29 , R 30 , and R 31  helps to define adjustable currents of the circuit YY in the discussion below.  
         [0029]     The node T 1  is also connected to the node T 2  through a resistor, R 12 , two back-to-back transistors Q 11  and Q 12 , and a resistor, R 15 . In the upper half of the circuit YY, the emitters and collectors of transistors Q 11  and Q 12  are all connected. The base of the transistor Q 11  is connected to the bases of a transistor Q 7 , and a transistor Q 8 . The emitters of the transistor Q 7  and the transistor Q 8  are connected and further connected to the node T 1  through a resistor R 36 . The collector of the transistor Q 7  is connected to the node X 1  through a diode, D 22 , and a resistor R 22 ; and the collector of the transistor Q 8  is connected to the node X 1  through a diode, D 21 , and the resistor R 22 . In the lower half of the circuit YY, the base of the transistor Q 12  is connected to the bases of a transistor Q 9 , and a transistor Q 10 . The emitters of the transistor Q 7  and the transistor Q 8  are connected and further connected to the node T 2  through a resistor R 37 . The collector of the transistor Q 9  is connected to the node XX 2  through a diode, D 23 , and a resistor R 24 ; and the collector of the transistor Q 10  is connected to the node X 2  through a diode, D 24 , and the resistor R 24 .  
         [0030]     The back-to-back transistors, Q 11  and Q 12 , have a minimum turn-on voltage, V 1 . The transistors, Q 7 , Q 8 , Q 9 , and Q 10 , typically have a turn-on voltage V 2 . In the conditions, the voltage difference, Vd, between the node OUT 1 + and the node OUT 1 − exceeds V 1 . The transistors, Q 11  and Q 12  are turned on. Once |Vd| exceeds V 1 +2V 2 , either Q 7  or Q 8  is turned on in the upper half of circuit YY. The current feeds back to the node XX 1  through either D 22  or D 21  and the resistor, R 22 . The extra current increases the voltage switching frequency at the node XX 1  and defines a minimum switching frequency for the top comparator in the upper half of YY. The increased minimum frequency produces a more “curved” sinusoidal waveform in the near “clipping” range. This helps to eliminate the audio noises when output sinusoidal waves enter and exit the voltage “clipping” range. A similar analysis applies to the lower half of circuit YY. Once |Vd| exceeds V 1 +2V 2 , either Q 9  or Q 10  is turned on in the lower half of circuit YY. The current feeds back to the node XX 2  through either D 23  or D 24  and the resistor, R 24 . The extra current increases the voltage switching frequency at the node XX 2  and defines the minimum switching frequency for the lower comparator in the lower half of YY.  
         [0031]      FIG. 3  illustrates output waveforms in the BTL Class D amplifier with and without the present invention. The BTL circuit without the noise reduction feedback network produces low frequency oscillation that may be in the audible frequency range; however; the circuit with the network produces clean output voltages without any low frequency oscillations.  
         [0032]     The noise reduction feedback network is not limited to the example given above. It can be applied to any class D audio amplifier and other audio amplifiers.  FIG. 4  provides schematic showing a system that comprises an audio input, a control stage, an output stage, and a noise reduction network that receives the feedback signals from the output stage. The noise reduction network modulates the control stage to eliminate the audible oscillation at the output stage when the output is near saturation.  
         [0033]     Another example of embodiments of the invention is illustrated in  FIG. 5 . Vout+ and Vout− are two input nodes of a noise reduction feedback network while FB 1  and FB 2  are two output nodes of the noise reduction network in  FIG. 5 ( a ). FIGS.  5 ( b ) and  5 ( c ) are detailed schematics showing embodiments of the circuit. In  FIG. 5 ( b ), Vout+ is connected to the base of a transistor, Q 3 , through a resistor, R 13 , and the base of a transistor, Q 4 , through a resistor, R 14 . The emitter of the transistor, Q 3 , is coupled to a power source, Vcc, and the emitter of the transistor, Q 4 , is coupled to the ground. The base of a transistor, Q 1 , is connected to the collector of the transistor, Q 3 , and they are coupled to the ground through a resistor, R 5 . The emitter of the transistor, Q 1 , is coupled to the power source, Vcc, through a resistor, R 1 ; while the collector of Q 1  is connected to a node FB 1  through a resistor, R 2 . The base of a transistor, Q 2 , is connected to the collector of the transistor, Q 4 , and they are coupled to the power source, Vcc, through a resistor, R 6 . The emitter of the transistor, Q 2 , is coupled to the ground through a resistor, R 4 ; while the collector of Q 2  is connected to the node FB 1  through a resistor, R 3 . In  FIG. 5 ( c ), Vout− is connected to the base of a transistor, Q 7 , through a resistor, R 15 , and the base of a transistor, Q 8 , through a resistor, R 16 . The emitter of the transistor, Q 7 , is coupled to the power source, Vcc, and the emitter of the transistor, Q 8 , is coupled to the ground. The base of a transistor, Q 5 , is connected to the collector of the transistor, Q 7 , and they are coupled to the ground through a resistor, R 11 . The emitter of the transistor, Q 5 , is coupled to the power source, Vcc, through a transistor, R 7 ; while the collector of Q 5  is connected to a node FB 2  through a resistor, R 8 . The base of a transistor, Q 6 , is connected to the collector of the transistor, Q 8 , and they are coupled to the power source, Vcc, through a resistor, R 12 . The emitter of the transistor, Q 6 , is coupled to the ground through a resistor, R 10 ; while the collector of Q 6  is connected to the node FB 2  through a resistor, R 9 .  
         [0034]     When the output voltage at Vout+, VOUT+, is in the range between Vbe(Q 4 ) and (Vcc−Vbe(Q 3 )), transistors, Q 3  and Q 4 , are activated; while transistors, Q 1  and Q 2 , are deactivated. The noise reduction network does not provide feedback signals to the node FB 1 . When VOUT+ is less than Vbe(Q 4 ), the transistor, Q 4 , becomes deactivated; while the transistor, Q 2 , becomes activated. The network provides an adjustable feedback current through Q 2  to the node FB 1 . When VOUT+ is larger than (Vcc−Vbe(Q 3 )), the transistor, Q 3 , becomes, deactivated; while the transistor, Q 1 , becomes activated. The network provides an adjustable feedback current through Q 1  to the node FB 1 . The same analysis applies to the node Vout− and the node FB 2  in circuit of  FIG. 5 ( c ). When the output voltage at Vout−, VOUT−, is in the range between Vbe(Q 8 ) and (Vcc−Vbe(Q 7 )), transistors, Q 7  and Q 8 , are activated; while transistors, Q 5  and Q 6 , are deactivated. The noise reduction network does not provide feedback signal to the node FB 2 . When VOUT− is less than Vbe(Q 8 ), the transistor, Q 8 , becomes deactivated; while the transistor, Q 6 , becomes activated. The network provides an adjustable feedback current through Q 6  to the node FB 2 . When VOUT− is larger than (Vcc−Vbe(Q 7 )), the transistor, Q 7 , becomes deactivated; while the transistor, Q 5 , becomes activated. The network provides an adjustable feedback current through Q 5  to the node FB 2 .  
         [0035]     Assume Vbe(Q 3 )=Vbe(Q 4 )=Vbe(Q 7 )=Vbe(Q 8 )=Vbe, the noise reduction network in FIGS.  5 ( b ) and  5 ( c ) produces an adjustable feedback current through the node FB 1  when VOUT+ in the range [0, Vbe] and [Vcc−Vbe, Vcc]; and an adjustable feedback current through the node FB 2  when VOUT− in the range [0, Vbe] and [Vcc−Vbe, Vcc]. These feedback currents define a minimum switching frequency of the amplifier control stage in  FIG. 4 . The increased minimum frequency produces a more “curved” sinusoidal waveform in the near “clipping” range of output signals, which is schematically shown in  FIG. 5 ( d ).  
         [0036]     In present invention, a noise reduction feedback network is introduced between an amplifier control stage and an output stage. The noise reduction feedback network couples with the input terminals of the amplifier control stage with output terminals of the output stage. It monitors the output voltages of the output stage, and remains “inactivated” as long as output voltages are not near saturation. The waveforms of output voltage are the amplified curves of input voltages with substantially the same shape. Once output voltages are near saturation, the noise reduction feedback network starts to be activated. In one embodiment, it sends an adjustable current to the input terminals of amplifier control stage. The adjustable current increases and defines the minimum switching frequency of the amplifier control stage. As a result, the waveforms of output voltage near saturation become more “curved” sinusoidal waveforms comparing with those of input signal. In another embodiment, the noise reduction feedback network reduces the close-loop gain of the amplifier control stage. It has the similar effect on the output voltage near saturation and the waveforms of output voltage near saturation become more “curved” sinusoidal waveforms comparing with those of input signal. The present invention has many advantages over approaches in references. The circuit is very simple and has high efficiency and fast loop response. The output signals in non-saturation region, together with its quality, are not affected by the “inactivated” noise reduction feedback network. The output signals near saturation and inside saturation regions are amplified by less close-loop gains than those in non-saturation regions. Their waveforms become more “curved”, which, in turn, greatly reduce or eliminate audio noises near or in the saturation regions.  
         [0037]     The description of the invention and its applications as set forth herein is illustrative and is not intended to limit the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and practical alternatives to and equivalents of the various elements of the embodiments are known to those of ordinary skill in the art. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.