Abstract:
The invention concerns a capacitor whereof one first electrode consists of a highly doped active region (D) of a semiconductor component (T) formed on one side of a surface of a semiconductor body, and whereof the second electrode consists of a conductive region (BR) coated with insulation (IL) formed beneath said active region and embedded in the semiconductor body.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to the forming of capacitors in integrated circuits, and in particular the forming of capacitors associated with sram cells. 
     2. Discussion of the Related Art 
       FIG. 1  shows an SRAM cell circuit with six transistors. The cell includes a memory point formed of two inverters I 1  and I 2  connected head-to-tail and having their two inputs, respectively BLTI, BLFI, connected to bit lines BLT, BLF by N-channel MOS transistors (NMOS) T 1 , T 2 . The gates of transistors T 1  and T 2  are connected to a word line WL. Inverter I 1  comprises a PMOS transistor TP 1  and an NMOS transistor TN 1 . The gates of transistors TP 1  and TN 1  are connected to terminal BLTI of the inverter. The drains of transistors TP 1  and TN 1  are connected and form the output terminal of the inverter. The sources of transistors TP 1  and TN 1  are respectively connected to a supply voltage VDD and a ground GND. Inverter I 2  has the same structure and includes a PMOS transistor TP 2  and an NMOS transistor TN 2 . 
       FIG. 2  shows a simplified top view of an embodiment in CMOS technology of the SRAM cell of  FIG. 1 . For simplicity, the P- and N-channel transistors are shown with the same gate widths. N-channel transistors T 1 , T 2 , TN 1 , and TN 2  are formed in a P-type substrate (SUB) and P-channel transistors TP 1  and TP 2  are formed in an N-type well (NWELL). The drain regions of transistors TN 1 , T 1 , and TN 2 , T 2  are confounded. The transistor gates, formed of polysilicon, are shown in hatchings. The gates of transistors TP 1 , TN 1 , respectively TP 2 , TN 2 , are interconnected. The drains of transistors TP 1  and TN 1  are connected to the gates of transistors TP 2 , TN 2  by a conductive line formed in an upper metal layer (METAL 1 ) via vias or contacts (the locations of which are shown with crosses). The drains of transistors TP 2  and TN 2  are connected to the gate of transistors TP 1 , TN 1  by a conductive line formed in the same metal layer (METAL 1 ). Vias form the contact between the source regions of transistors T 1 , T 2 , TN 1 , TN 2 , TP 1 , TP 2  and metal lines, not shown, respectively connected to lines BLT, BLF and to voltages GND, GND, VDD, and VDD. The N-type well is grounded and the substrate is at a predetermined voltage. For clarity, the STI transistor insulation trenches have not been shown. The STI trenches are preferably the inverse of the active areas (drains or sources). 
     Inverters I 1  and I 2  form a bistable structure or memory point that can take two states. When transistors T 1  and T 2  are on, an appropriate control of bit lines BLT, BLF enables modifying the state of the memory point and thereby programming a piece of information. When transistors T 1  and T 2  are off, the memory cell keeps the information in the form of a charge on the gate capacitors of the transistors of one or the other of the inverters. 
     If an ionizing radiation hits cell  2 , this creates parasitic electric charges that may change the stored state. Because recent SRAM cells are formed with MOS transistors having smaller and smaller dimensions, the gate capacitance of the transistors forming the inverters is smaller and smaller and the memory point is more and more sensitive to ionizing radiations, all the more as supply voltage VDD of the inverters is smaller and smaller. 
     To increase the resistance against ionizing radiations of an SRAM cell of small surface area formed with small-size transistors, it has been provided to couple the gates of the memory point transistors with additional capacitors. The problem of forming such capacitors without increasing the SRAM cell surface area then has to be overcome. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a capacitor structure that can be arranged in an integrated circuit without increasing the circuit surface. 
     Another object of the present invention is to provide such a structure enabling association of capacitors with an SRAM cell without increasing the surface area of said cell. 
     Another object of the present invention is to provide a method for manufacturing such a capacitor. 
     An object of the present invention is to provide a method for manufacturing such a capacitor. 
     To achieve these objects, as well as others, the present invention provides a buried capacitor formed by a conductive region coated with an insulator, formed in an active region of a component of the integrated circuit. 
     More specifically, the present invention provides a capacitor having a first electrode formed of a heavily-doped active region of a semiconductor component formed on the side of a surface of a semiconductor bulk, and having its second electrode formed of a conductive region coated with an insulator formed under said active region and embedded in the semiconductor bulk. 
     According to an embodiment of the present invention, the coated conductive region comprises an extension above a portion of which is formed a contact opening towards the second electrode. 
     According to an embodiment of the present invention, the heavily-doped active region is the drain or source region of a MOS transistor. 
     The present invention also aims at an SRAM cell comprising two inverters coupled head-to-tail, each of which comprises two MOS transistors of two conductivity types formed side by side, having their drains connected to each other and having their gates connected to each other, and comprising two capacitors such as described previously, the respective first electrodes of which are the drains of said transistors and the second electrodes of which are a same coated region connected to the gates of said transistors via a contact opening formed between the two transistors. 
     The present invention also aims at a DRAM cell comprising a MOS transistor having its source region connected to a bit line, having its gate connected to a word line, and comprising a capacitor such as described hereabove, the first electrode of which is the drain region of said transistor and the second electrode of which is a coated region connected to a supply line. 
     The present invention also aims at an integrated circuit in which the insulator coating the lower surface of the coated region exhibits a larger dielectric constant than the insulator coating the rest of the coated conductive region. 
     The present invention also aims at a method for manufacturing a capacitor having a first electrode formed of a heavily-doped active region of a semiconductor component, comprising the steps of: 
     a/ forming at the surface of an initial semiconductor substrate a conductive region coated with an insulator; 
     b/ growing by epitaxy a semiconductor layer to cover the initial substrate and bury the coated region; 
     c/ forming said heavily-doped active region across the entire thickness of said semiconductor layer, above a portion of the coated conductive region. 
     According to an embodiment of the present invention, the heavily-doped active region is one of the drain region and of the source region of a MOS transistor. 
     According to an embodiment of the present invention, before forming the drain and source regions, an opening is made above another portion of the coated conductive region in said semiconductor layer and in the insulator coating the conductive region to connect the conductive region to a conductive layer used to form the gate of the transistor. 
     According to an embodiment of the present invention, the opening is made at the step of digging the STI insulation trenches of said MOS transistor. 
     The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1 and 2 , previously described, respectively show a circuit and a simplified top view of a conventional SRAM cell; 
         FIGS. 3A and 3B  are top and perspective views of a MOS transistor having its drain forming a first electrode of a capacitor according to the present invention; 
         FIG. 4  is a simplified top view of an SRAM cell associated with capacitors according to the present invention; 
         FIG. 5  shows a circuit equivalent to the structure of  FIG. 4 ; 
         FIGS. 6A ,  6 B,  6 C illustrate a step of the manufacturing of inverter I 1  of the SRAM cell of  FIG. 4  respectively in a top view and in cross-section views taken in planes B-B, C-C; 
         FIGS. 7A to 10A ,  7 B to  10 B, and  7 C to  10 C respectively show same top and cross-section views for subsequent steps of the manufacturing of inverter I 1 ; 
         FIG. 10D  shows a cross-section view of inverter I 1  along a plane D-D at the step illustrated in  FIGS. 10A to 10C ; and 
         FIG. 11  shows a cross-section view of two DRAM cells according to the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The same reference numerals designate the same elements in  FIGS. 1 and 2  and in the next drawings. Only those elements necessary to the understanding of the present invention have been shown. 
       FIG. 3A  is a simplified top view of an N-type MOS transistor, T, having its drain forming a first electrode of a capacitor C according to the present invention.  FIG. 3B  is a perspective view of the transistor and of the capacitor of  FIG. 3A . In  FIG. 3B , in the cross-section portions, the insulating regions are hatched. 
     As illustrated in  FIGS. 3A and 3B , transistor T comprises a gate G formed of polysilicon on a thin gate oxide layer GO at the surface of a substrate SUB. The transistor comprises a source region S and a drain region D, both heavily doped, formed on either side of gate G in the substrate surface. The transistor is surrounded with an STI shallow insulation trench formed in the substrate surface. 
     According to the present invention, a conductive region BR coated with an insulator (IL) is formed in drain region D of transistor T so that a portion of region BR is separated from an opposite portion of drain region D by insulator IL surrounding conductive region BR. In  FIGS. 3A ,  3 B and in the next drawings, coated region BR is arranged so that only the lower surface of drain region D rests on the upper surface of a portion of coated region BR. The present invention however also aims at the cases where the drain region partially or completely surrounds the lateral surfaces of a portion of region BR. A first capacitor C is formed between the opposite portions of drain D and of region BR, separated by the insulator coating region BR. A second capacitor C′ is formed between the opposite portions of region BR and of substrate SUB, separated by the insulator coating region BR. An opening V with insulator-coated walls is formed above another portion of region BR. A conductive layer, for example, polysilicon, fills opening V to form a contact towards region BR therein. 
     Thus, according to a first advantage of the present invention, a capacitor having as one electrode a heavily-doped active region of a component (here, the drain of a transistor) is formed, the surface area taken up by the active region and the capacitor altogether being no greater than the surface area of the active region. 
     According to a second advantage of the present invention which will appear from the following description, the contact with the second capacitor electrode may be formed at the same time as the MOS transistor gates. 
     According to a third advantage which will also appear from the following description of a manufacturing process, the insulator between the active region and the underlying conductive region may be chosen independently from the insulator between this conductive region and the substrate, whereby capacitors C and C′ may be optimized independently. 
       FIG. 4  shows a simplified top view of an SRAM CMOS cell with six transistors associated with capacitors according to the present invention. The SRAM cell comprises two inverters I 1  and I 2  and two transistors T 1 , T 2  having the same connections and the same dimensions as in  FIG. 2 . According to a preferred embodiment of the present invention, a same coated region BR 1  is arranged so that the drain regions of transistors TP 1  and TN 1  of inverter I 1  each directly rest on a portion of coated region BR 1 . Further, a projection of the etched polysilicon region forming the gates of transistors TP 1  and TN 1  is formed to electrically connect said gates to region BR 1  via a contact opening V 1 . Opening V 1  is made between transistors TP 1  and TN 1  above the border between well NWELL and substrate SUB. As illustrated hereafter in relation with  FIG. 5 , four capacitors are formed around coated region BR 1  connected to the gates of transistors TP 1  and TN 1  of inverter I 1 . Similarly, the drain regions of transistors TP 2  and TN 2  of inverter I 2  each directly rest on a coated region BR 2  connected by an opening V 2  to the gates of transistors TP 2  and TN 2 , and four capacitors are formed around coated region BR 2  connected to the gates of transistors TP 2  and TN 2  of inverter I 2 . The eight capacitors connected to the gates of the transistors of inverters I 1  and I 2  increases the resistance of the SRAM cell against ionizing radiations. 
     This preferred embodiment of the present invention takes advantage of the fact that a conventional CMOS manufacturing process requires that a P-channel transistor formed in an N-type well, here, transistor TP 1  of inverter I 1 , is separated by a minimum predetermined distance from the closest N-channel transistor formed in the substrate, here, transistor TN 1  of inverter I 1 . The minimum predetermined distance depends on the process used but, advantageously, in a standard CMOS process conventionally used to form an SRAM cell, the distance separating transistors TP 1  and TN 1  is sufficient for the accuracy of the process to enable forming opening V 1  and the gate layer excrescence without having to move further apart transistors TP 1  and TN 1 . Thus, the surface area of inverter I 1  coupled to capacitors according to the present invention is identical to the surface of a conventional inverter. The same occurs for inverter I 2 , whereby the present invention enables forming an SRAM cell resistant against ionizing radiations which takes up the same surface area as a conventional SRAM cell non resistant against radiations. 
       FIG. 5  shows a circuit equivalent to the structure of  FIG. 4  and indicates, in particular, the connections of the capacitors according to the present invention. Inverters I 1  and I 2  are shown in the form of blocks. A capacitor C 1 , formed between drain D of transistor TP 1  and region BR 1  connected to the gate of transistor TP 1 , couples the input and the output of inverter I 1 . Similarly, a capacitor C 2  formed between the drain of transistor TN 1  and region BR 1  couples the input and the output of inverter I 1 . A capacitor C 1 ′, formed between conductive region BR 1  and well NWELL, couples the input of inverter I 1  to ground GND. A capacitor C 2 ′, formed between region BR 1  and the substrate, couples the input of inverter I 1  to a bias voltage VPOL of substrate SUB. Similarly, capacitors C 3 , C 4 , respectively formed between the drains of transistors TP 2 , TN 2 , and region BR 2 , couple the input and the output of inverter I 2 . A capacitor C 3 ′ according to the present invention, formed between conductive region BR 2  and well NWELL, couples the input of inverter I 2  to ground GND. A capacitor C 4 ′ according to the present invention, formed between region BR 2  and the substrate, couples the input of inverter I 2  to voltage VPOL. 
       FIGS. 6 to 10  hereafter illustrate manufacturing steps of capacitors according to an embodiment of the present invention. As an example,  FIGS. 6 to 10  hereafter illustrate manufacturing steps of the capacitors associated with inverter I 1  of the SRAM cell of  FIG. 4 . 
       FIGS. 6A ,  6 B, and  6 C respectively show a top view and cross-section views along planes B-B, C-C of inverter I 1  after the first steps of a manufacturing process according to the present invention. Plane B-B cuts transistor TP 1  lengthwise. The source and drain of transistor TP 1  are respectively to the left and to the right of the cross-section view along plane B-B. 
     In first steps, a thin insulating layer IL 1  is deposited at the surface of an initial lightly-doped P-type single-crystal silicon substrate SUB. A layer of a conductor such as polysilicon is deposited above layer IL 1 , and the two deposited layers are etched by means of a first mask to define region BR 1 , here according to a rectangle having a first end (B-B cross-section) located under the drain of transistor TP 1 , and having its other end located under the drain of transistor TN 1 . A step of thermal oxidation followed by an isotropic etching of the oxide are then performed so that there remains a thin silicon oxide layer IL 2  at the surface and on the sides of the polysilicon region and that the silicon oxide is removed at the surface of substrate SUB. 
       FIGS. 7A ,  7 B, and  7 C respectively show the same views as  FIGS. 6A ,  6 B, and  6 C at a subsequent step, after having grown by epitaxy a single-crystal silicon layer  10  from the initial substrate, to cover the initial substrate and completely bury region BR 1  by lateral growth. The doping type and level of epitaxial layer  10  are chosen to optimize the MOS transistors to be formed and are not necessarily identical to those of the initial substrate. The initial substrate and epitaxial layer  10  altogether then form a semiconductor substrate or bulk in which is embedded insulator-coated conductive region BR 1 . 
       FIGS. 8A ,  8 B, and  8 C respectively show the same views as  FIGS. 7A ,  7 B, and  7 C after having: 
     planarized the surface of single-crystal silicon  10 ; 
     formed wells NWELL (not shown); and 
     formed in layer  10  and the substrate shallow trenches (STI) intended to be filled with an insulator to laterally insulate the MOS transistors from the inverter. 
     To simplify the drawings, the insulation trenches are in the present drawings shown to be narrower than they really are in practice. According to the present invention, the mask conventionally used to dig the insulation trenches is also used to dig an opening V 1  substantially located at the center of region BR 1  (C-C cross-section). Due to the etch selectivity between silicon oxide and silicon, above region BR 1 , the etching naturally stops on the oxide coating region BR 1 . 
       FIGS. 9A ,  9 B, and  9 C respectively show the same views as  FIGS. 8A ,  8 B, and  8 C after having: 
     filled the STI trenches and opening V 1  with an insulator such as silicon oxide; 
     covered with a gate oxide layer the single-crystal silicon of the circuit surface; 
     removed the insulator present at the center of opening V 1  on the upper surface of conductive region BR 1 , while leaving in place an insulator IL 3  on the vertical walls of opening V 1 ; 
     deposited at the circuit surface a polysilicon layer to form the gate layer of the transistors and fill opening V 1  to form an electric contact with buried region BR 1 ; and 
     etched the polysilicon, then the gate oxide, to define gates G of MOS transistors TN 1 , TP 1  of the inverter, connected together. According to the present invention, the gates of transistors TN 1 , TP 1  are also connected to region BR 1  by opening V 1 . 
       FIGS. 10A ,  10 B, and  10 C respectively show the same views as  FIGS. 9A ,  9 B, and  9 C after forming of drain and source regions D and S of PMOS transistor TP 1  and NMOS transistor TN 1 . According to the present invention, the doping of drain regions D of the transistors is such that the drain regions extend in depth to reach insulator IL 1  covering the upper surface of conductive region BR 1 . Various conventional alternative embodiments of drain and source regions may be used, for example, to form structures with LDD-type spacers. 
       FIG. 10D  shows a cross-section view of inverter I 1  of  FIGS. 10A to 10C  along a plane D-D crossing buried conductive layer BR 1  across its entire length and crossing the drain regions of transistors TP 1 , TN 1 .  FIG. 10D  further shows well NWELL not shown in  FIGS. 6 to 9  for clarity. 
     The manufacturing process illustrated in  FIGS. 6 to 10  is particularly simple to implement. Further, this method requires two specific masks only (described in relation with  FIGS. 6 and 9 ), which makes it particularly inexpensive. 
     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the type and thickness of the thin insulator (IL 1 ) arranged between the lower surface of the conductive regions and the initial substrate may be chosen adequately to optimize the value of the capacitors coupling coated conductive regions BR with well NWELL and with the substrate. As an example, the insulator may be an oxynitride having a thickness from 1 to 2 nm, AL 2 O 3  having a thickness from 1 to 3 nm, or Ta 2 O 5  having a thickness from 2 to 3 nm. 
     The present invention has been described in relation with a specific method for manufacturing a specific structure comprising buried coated conductive regions, but it will be within the abilities of those skilled in the art to adapt the present invention to manufacturing processes enabling forming a structure comprising equivalent buried coated conductive regions. 
     The present invention has been described in relation with a capacitor formed with a buried insulator-coated conductive region coupling the drain and the gate of a transistor, but it will readily adapt to a capacitor coupling the drain or the source of a MOS transistor to another element of the integrated circuit connected to the buried region. 
       FIG. 11  shows as an example a cross-section view of two DRAM cells according to the present invention. Each DRAM cell comprises a control transistor TC laterally surrounded with STI trenches, having its source S connected to a bit line not shown, having its gate G connected to a word line not shown, and having its drain D directly resting on a coated conductive region BR. The coated conductive region is connected to a supply line not shown. Capacitor C formed between the opposite surfaces of drain D and of region BR forms the memory point of the DRAM cell. It should be noted by those skilled in the art that the putting in common of coated region BR between the two DRAM cells provides a gain in surface area. 
     The present invention will also be easily adapted to one or several capacitors coupling other active regions belonging to other types of components of an integrated circuit directly resting on the coated region. The present invention will be especially easily adapted to capacitors coupling several active regions of several components, each of which directly rests on a portion of the same buried region. The present invention will also easily adapt to a bipolar technology. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.