Abstract:
A voltage comparator circuit is composed of a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal, and a waveform shaping circuit connected to the output terminal. The differential amplifier circuit includes: a first differential transistor pair responsive to the pair of input signals to output first and second output currents; a second differential transistor pair responsive to the pair of input signals to output third and fourth output currents; a first current mirror circuit developing a first internal current in response to the first output current; a third current mirror circuit complementary to the first current mirror circuit and developing a third internal current in response to the third output current; a second current mirror circuit developing a second internal current in response to the third output current and the third internal current; and a fourth current mirror circuit complementary to the second current mirror circuit and developing a fourth internal current in response to the fourth output current and the first internal current. A resultant current which is said second and fourth currents added together is drawn from or supplied to the output terminal of the differential amplifier circuit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a voltage comparator circuit, and in particular, relates to a voltage comparator circuit suitable for a high-speed differential signal interface.  
         [0003]     2. Description of the Related Art  
         [0004]     Differential signaling is one of the well-known approaches for achieving a high-speed signal interface. For example, RSDS™ (Reduced Swing Differential Signaling), and mini-LVDS™ (Low Voltage Differential Signaling) are going to be standardized as an interfacing scheme between an LCD (Liquid Crystal Display) driver and a timing controller within an LCD apparatus.  
         [0005]     Receiver circuits used for differential signaling typically incorporate a voltage comparator circuit with differential inputs. Differential signals received by a differential signal receiver typically have a frequency of approximately 85 MHz for RSDS™, and 200 MHz for mini-LVDS™. The amplitude of the differential signal component of the differential signals is approximately ±50 mV, and the amplitude of the common-mode signal component ranges from 0.3 V to V DD -0.5 V, where V DD  is a power supply voltage. A voltage comparator circuit within a receiver circuit is required to meet the specifications described above. With a circuit configuration presently released, however, it is difficult to satisfy both the specifications of the common-mode signal component, and an operation speed at the same time.  
         [0006]     A voltage comparator circuit adapted to differential signals is typically based on a differential amplifier topology.  FIG. 1  is a circuit diagram illustrating a structure of a differential amplifier circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 03-62712). The conventional differential amplifier circuit is provided with first and second differential transistor pairs DF 11  and DF 12 , first to fifth current mirror circuits CM 11  to CM 15 , and first and second constant current sources I 11  and I 12 .  
         [0007]     The first differential transistor pair DF 11  is composed of first and second P-channel MOS transistors MP 11  and MP 12 . Correspondingly, the second differential transistor pair DF 12  is composed of first and second N-channel MOS transistors MN 11  and MN 12 .  
         [0008]     The first current mirror circuit CM 11  has an input terminal connected to the drain of the first P-channel MOS transistor MP 11 , a common terminal connected to an earth terminal (V SS  terminal), and an output terminal connected to the input terminal of the fifth current mirror circuit CM 15 . The second current mirror circuit CM 12 , on the other hand, has an input terminal connected to the drain of the second P-channel MOS transistor MP 12 , a common terminal connected to the V SS  terminal, and an output terminal connected to an output terminal OUT of the differential amplifier circuit.  
         [0009]     The third current mirror circuit CM 13  has an input terminal connected to the drain of the first N-channel MOS transistor MN 11 , a common terminal connected to a power supply terminal (V DD  terminal), and an output terminal connected to the drain of the second P-channel MOS transistor MP 12  and also to the input terminal of the second current mirror circuit CM 12 . The fourth current mirror circuit CM 14  has an input terminal connected to the drain of the second N-channel MOS transistor MN 12 , a common terminal connected to the V DD  terminal; and the output terminal is connected to the input terminal of the first current mirror circuit CM 11  and also to the drain of the first P-channel MOS transistor MP 11 . Finally, the fifth current mirror circuit CM 15  has an input terminal connected to the output terminal of the first current mirror circuit CM 11 , a common terminal connected to the V DD  terminal, and an output terminal connected to the output terminal of the second current mirror circuit CM 12  and also to the output terminal OUT of the differential amplifier circuit.  
         [0010]     The first constant current source I 11  is connected between the V DD  terminal and the commonly-connected sources of the first and second P-channel MOS transistor MP 11  and MP 12 . The second constant current source I 12  is connected between the V SS  terminal and the commonly-connected sources of the first and second N-channel MOS transistors MN 11  and MN 12 .  
         [0011]     The gates of the first P-channel MOS transistor MP 11  and the first N-channel MOS transistor MN 11  are commonly connected to an inverting input terminal In −  of the differential amplifier circuit. Correspondingly, the gates of the second P-channel MOS transistor MP 12  and the second N-channel MOS transistor MN 12  are commonly-connected to non-inverting input terminal In + .  
         [0012]     Operation analysis the conventional differential amplifier circuit shown in  FIG. 1  is given in the following.  
         [0013]     First, basic operation of a differential transistor pair is described with reference to  FIGS. 2 and 3 .  FIG. 2  shows a basic circuit configuration of the differential transistor pair, and  FIG. 3  shows input-to-output characteristics of the differential transistor pair. The studied differential transistor pair is composed of N-channel MOS transistors MN 21  and MN 22  having commonly-connected sources. A constant current source ISS for supplying an electric current Iss is connected between the commonly-connected sources and a V SS  terminal. When a set of DC voltages Vi 1  and Vi 2  are supplied to the gates of the N-channel MOS transistors MN 21 , and MN 22 , respectively, the following formula (1) holds: 
 
 V   i1   −V   GS1   +V   GS2   −V   i2 =0  (1) 
 
 where V GS1  and V GS2  are gate-source voltages of the N-channel MOS transistors MN 21  and MN 22 , respectively. 
 
         [0014]     Additionally, the gate-source voltages V GS1  and V GS2  are represented by the following formulas:  
             β   =       W   L     ⁢   μ   ⁢           ⁢     C   O               (   2   )                 V   GS1     =           2   ⁢     I   d1       β       +     V   T               (   3   )                 V   GS2     =           2   ⁢     I   d2       β       +     V   T               (   4   )             
 
 where I d1  and I d2  are drain currents through the MOS transistors MN 21  and MN 22 , respectively, and W and L are the gate width and length of the N-channel MOS transistors MN 21  and MN 22 , respectively; μ is the mobility, and C 0  is the gate oxide film capacitance per unit area; finally, V T  is the threshold voltage of the N-channel MOS transistors MN 21  and MN 22 . 
 
         [0015]     From formulas (1) to (4), a minimum voltage difference ΔV id  between the input voltages V i1  and V i2  at which the whole of the bias current Iss from the constant current source ISS flows only through the N-channel MOS transistor MN 21  is indicated by the following formula (5):  
               Δ   ⁢           ⁢     V   id       =         V   i1     -     V   i2       =         (           2   ⁢     I   SS       β       +     V   T       )     -     V   T       =         2   ⁢     I   SS       β                   (   5   )             
 
         [0016]     In the following, a common gate-source voltage VGS 0  is defined as the gate-source voltages of the N-channel MOS transistors MN 21  and MN 22  for V i1 =V i2 . Since the drain currents Id 1  and Id 2  through the N-channel MOS transistors MN 21  and MN 22  are each identical to half of the bias current Iss, the common gate-source voltage VGS 0  is represented by the following formula (6):  
               V   GS0     =           I   SS     β       +     V   T               (   6   )             
 
         [0017]     From formulas (5) and (6), the minimum voltage difference ΔVid at which the differential transistor pair appropriately operates is represented as follows: 
 
∴Δ V   id =√{square root over (2)}( V   GS0   −V   T )  (7) 
 
         [0018]     Formula (7) presents the condition under which the bias current flows through only one MOS transistor within the differential transistor pair.  
         [0019]     Thus, the bias current flows through only one transistor, not through the other transistor within the differential transistor pair, when the input voltage difference is equal to or more than the value defined by formula (7). This operation is the basic principle of comparator operation. The differential transistor pair exhibits the input-to-output characteristics shown in  FIG. 3 ; the horizontal axis represents the voltage difference between the input voltages Vi 1  and Vi 2 , and the vertical axis represents the drain currents through the N-channel MOS transistors MN 21  and MN 22 .  
         [0020]     It should be noted that the comparator operation may be sufficiently achieved when the voltage difference is equal to or below the value defined by formula (7), depending on a configuration of a next circuit stage connected to the differential transistor pair; this is because the differential transistor pair has a sufficient gain.  
         [0021]     Next, the conventional differential amplifier circuit in  FIG. 1  is then analyzed in the following. The circuit shown in  FIG. 1  is responsive to the input voltage levels to operate in selected one of three operation modes: (1) an operation mode in which both the first and second differential transistor pairs DF 11  and DF 12  are activated, (2) an operation mode in which only the first differential transistor pair DF 11  is activated; and (3) an operation mode in which only the second differential transistor pair DF 12  is activated.  
         [0022]     (1) In Case when Both of First and Second Differential Transistor Pairs DF 11  and DF 12  are Activated  
         [0023]     Both of the first and second differential transistor pairs DF 11  and DF 12  are activated when the conditions defined by the following formula are satisfied. 
 
 V   DD −( V   GS(MP)   +V   DS(sat)(I11) )&gt; V   in   &gt;V   GS(MN)   +V   DS(sat)(I12)   (8) 
 
 where Vin is any of the input voltages Vin −  and Vin +  supplied to the inverting and non-inverting input terminals In −  and In + , respectively; V GS(MP)  is the gate-source voltage of the P-channel MOS transistors MP 11  or MP 12 , and V GS(MN)  is the gate-source voltage of the N-channel MOS transistor MN 11  or MN 12 ; V DS(sat)(I11)  is a drain-source voltage at saturation of a P-channel MOS transistor (not shown) within the current source I 11 ; and V DS(sat)(I12)  is the drain-source voltage at saturation of an N-channel MOS transistor (not shown) within the current source I 12 . It should be noted that a drain-source voltage at saturation of a MOS transistor is a voltage barely enough for the MOS transistor to operate in a pentode region. 
 
         [0024]     (1-a) Operation for Vin − &gt;Vin +   
         [0025]     First, a description is given for a case where the input voltage Vin −  is higher than the input voltage Vin + , and the difference between the input voltages Vin −  and Vin +  is larger than the voltage ΔVid, defined by formula (7). It should be noted that the input voltages Vin −  and Vin +  are defined as the voltages applied to the inverting input terminals In −  and In + , respectively. In this case, the differential amplifier circuit performs voltage comparator operation, and thus the bias current I 1  flows only through the P-channel MOS transistor MP 12  within the differential transistor pair DF 11 ; the current through the first P-channel MOS transistor MP 11  is nil. Correspondingly, the bias current I 2  flows only through the N-channel MOS transistor MN 11  within the differential transistor pair DF 12 , and the current through the N-channel MOS transistor MN 12  is nil.  
         [0026]     In this case, each current mirror circuit operates as follows. The current mirror circuit CM 13  develops an output current having a level identical to that of the bias current I 2 , since the N-channel MOS transistor MN 11  allows the bias current I 2  to be drawn from the input of the current mirror circuit CM 13 ; it should be noted that the circle attached to each of the blocks referred to as each current mirror circuit represents the input terminal. The second current mirror circuit CM 12  receives an input current which is the drain current I 1  of the second P-channel MOS transistor MP 12  and the output current I 2  of the third current mirror circuit CM 13  added together. The current mirror circuit CM 12  is designed to have a mirror ratio of k; that is, the current mirror circuit CM 12  develops an output current having a current level of k times of that of the input current inputted thereto. Therefore, the output current I O(CM12)  of the current mirror circuit CM 12  is represented by the following formula: 
 
 I   O(CM 12)   =k ( I   1   +I   2 )  (9) 
 
         [0027]     On the other hand, the input current of the current mirror circuit CM 14  is nil, since the current through the N-channel MOS transistor MN 12  is nil. This results in that the output current of the current mirror circuit CM 14  is set nil. Additionally, the current mirror circuit CM 11  receives an input current which is the output current of the current mirror circuit CM 14  and the drain current of the P-channel MOS transistor MP 11  added together. The output current of the current mirror circuit CM 14  and the drain current of the P-channel MOS transistor MP 11  are both nil, and therefore the input current of the current mirror circuit CM 11  is also nil. Accordingly, the output current of the current mirror circuit CM 11  is set nil. Since the output current of the current mirror circuit CM 11  is nil, the input current of the current mirror circuit CM 15  is nil, and therefore the output current of the current mirror circuit CM 15  is also nil.  
         [0028]     As is understood from the foregoing, the differential amplifier circuit operates to draw a current from the output terminal OUT due to the operation of the current mirror circuit CM 12 . The current level I OUT  on the output terminal OUT is represented by the following formula: 
 
 I   OUT   =k ( I   1   +I   2 )  (10) 
 
 This results in that the voltage level on the output terminal OUT is pulled down to the low level (GND). 
 
         [0029]     (1-b) Operation for Vin − &lt;Vin +   
         [0030]     Next, a description is given for a case where the input voltage Vin +  is higher than the input voltage Vin − , and the difference between the input voltages Vin +  and Vin −  is equal to or above the value defined by Formula (7). In this case, the differential amplifier circuit performs the comparator circuit operation, and therefore the bias current I 1  flows only through the P-channel MOS transistor MP 11  within the differential transistor pair DF 11 , and the current through the P-channel MOS transistor MP 12  is set nil. Correspondingly, the bias current I 2  flows only through the N-channel MOS transistor MN 12  within the differential transistor pair DF 12 , and the current through the N-channel MOS transistor MN 11  is set nil.  
         [0031]     In this case, each current mirror circuit operates as follows. The current mirror circuit CM 14  develops an output current having a level identical to that of the bias current I 2 , since the N-channel MOS transistor MN 12  allows the bias current I 2  to be drawn from the input of the current mirror circuit CM 14 . The current mirror circuit CM 11  receives an input current which is the drain current I 1  of the P-channel MOS transistor MP 11  and the output current I 2  of the current mirror circuit CM 14  added together Therefore, the output current I O(CM11)  of the current mirror circuit CM 11  is represented by the following formula: 
 
 I   O(CM 11)   =I   1   +I   2   (11) 
 
         [0032]     The output of the current mirror circuit CM 11  is connected with the input of the current mirror circuit CM 15 , and therefore the input current of the current mirror circuit CM 15  is (I 1 +I 2 ). The current mirror circuit CM 15  is designed to have a mirror ratio of k, that is, the current mirror circuit CM 15  develops an output current having a current level of k times of that of the input current inputted thereto. Therefore, the output current I O(CM15)  of the current mirror circuit CM 15  is represented by the following formula: 
 
 I   O(CM 15)   =k ( I   1   +I   2 )  (12) 
 
         [0033]     On the other hand, the input current of the current mirror circuit CM 13  is nil, since the drain current of the N-channel MOS transistor MN 11  is set nil. Therefore, the output current of the current mirror circuit CM 13  is also set nil. The current mirror circuit CM 12  receives an input current which is the output current of the current mirror circuit CM 13  and the drain current of the P-channel MOS transistor MP 12  added together. Since these currents are both nil, the input current of the current mirror circuit CM 12  is nil, and the output current thereof is also set nil.  
         [0034]     From the foregoing, the differential amplifier circuit operates to supply a current from the output terminal OUT due to the operation of the current mirror circuit CM 15 . The current I OUT  developed on the output terminal OUT is represented by the following formula: 
 
 I   OUT   =k ( I   1   +I   2 )  (13) 
 
 This results in that the voltage level on the output terminal OUT is pulled up to the high level (V DD ). 
 
         [0035]     In summary, the differential amplifier circuit operates to draw or supply a current through the output terminal I OUT  in response to the voltage level difference between the inverting input terminal In −  and the non-inverting input terminal In + , when both the first differential transistor pairs DF 11  and DF 12  are activated. The current level on the output terminal OUT is represented by formulas (10) and (13).  
         [0036]     (2) In Case where Only First Differential Transistor Pair DF 11  is Activated  
         [0037]     Only the first differential transistor pair DF 11  is activated when the input voltages Vin −  and V in   +  satisfy conditions defined by the following formulas: 
 
0 &lt;V   in   &lt;V   GS(MN)   +V   DS(sat)(I12)   (14) 
 
 where V GS(MN)  is the gate-source voltage of the N-channel MOS transistors MN 11  or MN 12 , and V DS(sat)(I12)  is the drain-source voltage at saturation of the N-channel MOS transistor (not shown) within the current source I 12 . 
 
         [0038]     In such input voltage range, a sufficient drain-source voltage is not established across the MOS transistor within the constant current source I 12 , and therefore the bias current I 2  is set nil. As a result, the differential transistor pair DF 12  is deactivated.  
         [0039]     (2-a) Operation for Vin − &gt;Vin +   
         [0040]     First, a description is given for a case where the input voltage Vin −  is higher than the input voltage Vin + , and the voltage difference between the input voltages Vin −  and Vin +  are equal to or above the minimum voltage difference ΔVid defined by formula (7). Under these conditions, the bias current I 1  flows only through the P-channel MOS transistor MP 12  within the differential transistor pair DF 11 , and therefore the current through the first P-channel MOS transistor MP 11  is nil. Additionally, the bias current I 2  through the differential transistor pair DF 12  is nil.  
         [0041]     In this case, each current mirror circuit operates as follows: No electric current flows through the current mirror circuits CM 13  and CM 14 , since the bias current I 2  is nil. The input current of the current mirror circuit CM 11  is set nil, since the output current of the current mirror circuit CM 14  and the drain current of the P-channel MOS transistor MP 11  are nil. Therefore, the output current of the current mirror circuit CM 11 , which is identical to the input current of the current mirror circuit CM 15 , is also set nil. Because the input current of the current mirror circuit CM 15  is nil, the output current thereof is also set nil.  
         [0042]     The current mirror circuit CM 12 , on the other hand, receives the drain current of the P-channel MOS transistor MP 12  within the differential transistor pair DF 11 , while the output current of the current mirror circuit CM 13  is nil. That is, the input current of the current mirror circuit CM 12  is identical to the drain current I 1  of the P-channel MOS transistor MP 12 , and therefore the current mirror circuit CM 12  develops an output current having a current level of k times of that the input current. Accordingly, the differential amplifier circuit operates to draw a current from the output terminal OUT due to the operation of the current mirror circuit CM 12 . The current level I OUT  on the output terminal OUT is equal to k·I 1 , and the output voltage on the output terminal OUT is pulled down to the low level (GND).  
         [0043]     (2-b) Operation for Vin − &lt;Vin + )  
         [0044]     Next, a description is given for a case where the voltage Vin +  is higher than the voltage Vin − , and the voltage difference between the voltages Vin +  and Vin −  is equal to or above the minimum voltage difference defined by formula (7). Under these conditions, the bias current I 1  flows only through the P-channel MOS transistor MP 11  within the differential transistor pair DF 11 , and the current through the P-channel MOS transistor MP 12  is nil. Additionally, the bias current I 2  of the differential transistor pair DF 12  is nil.  
         [0045]     In this case, each current mirror circuit operates as follows: No electric current flows through the current mirror circuits CM 13  and CM 14 , since the bias current I 2  of the differential transistor pair DF 12  is nil. Since the output current of the current mirror circuit CM 13  and the drain current of the P-channel MOS transistor MP 12  are both nil, the input current of the current mirror circuit CM 12  is also nil, and the output current of the current mirror circuit CM 12  is set nil.  
         [0046]     The current mirror circuit CM 11 , on the other hand, receives the drain current of the P-channel MOS transistor MP 11  within the differential transistor pair DF 11 , while the output current of the current mirror circuit CM 14  is nil. That is, the input current of the current mirror circuit CM 11  is identical to the drain current I 1  of the P-channel MOS transistor MP 11 , and the current mirror circuit CM 11  develops an output current having a current level identical to that of the input current I 1 , which is to be supplied to the input of the current mirror circuit CM 15 .  
         [0047]     The current mirror circuit CM 15  receives the output current of the current mirror circuit CM 11  on the input, and therefore develops an output current having a current level of k times of that of the input current inputted thereto. The differential amplifier circuit supplies a current from the output terminal OUT due to the operation of the current mirror circuit CM 15 . The current level I OUT  on the output terminal OUT is equal to k·I 1 . This results in that the voltage level on the output terminal OUT is pulled up to the high level (V DD ).  
         [0048]     In summary, the differential amplifier circuit operates to draw or supply a current through the output terminal OUT in response to the input voltage difference between the inverting input terminal In −  and the non-inverting input terminal In + . The current level on the output terminal OUT is represented by the following formula in the both cases: 
 
 I   OUT   =kI   1   (15) 
 
         [0049]     (3) In Case where Only the Second Differential Transistor Pair DF 12  is Activated  
         [0050]     Only the second differential transistor pair DF 12  is activated in a case where the input voltages Vin −  and Vin +  satisfy conditions defined by the following formulas: 
 
 V   DD   &gt;V   in   &gt;V   DD −( V   GS(MP)   +V   DS(sat)(I11) )  (16) 
 
 where V GS(MP)  is the gate-source voltage of the P-channel MOS transistors MP 11  or MP 12 , and V DS(sat)(I11)  is the drain-source voltage at saturation of the P-channel MOS transistor (not shown) within the current source I 11 . 
 
         [0051]     In such input voltage ranges, a sufficient drain-source voltage is not established across the MOS transistor within the constant current source I 12 , and therefore the bias current I 2  is set nil. As a result, the differential transistor pair DF 11  is deactivated.  
         [0052]     The current level on the output terminal OUT is correspondingly obtained through the same analysis as the forgoing, and the current level I OUT  on the output terminal OUT is represented by the following formula in any case where the differential amplifier circuit operates to draw or supply a current through the output terminal: 
 
 I   OUT   =kI   2   (17) 
 
         [0053]     The above-described analysis proves that the drive capability of the differential amplifier circuit directly depends on the bias currents fed to the differential transistor pair; increasing the drive capability requires increasing the bias currents. Additionally, the drive current developed on the output terminal is used for charging or discharging the load capacitance connected with the output terminal OUT of the differential amplifier circuit. Therefore, the operation speed of the differential amplifier circuit depends on the bias currents. In other words, enhancing the operation speed of the differential amplifier circuit requires  
         [0054]     Next, power consumption of the differential amplifier circuit shown in  FIG. 1  is analyzed in the following.  
         [0055]     When the input voltage Vin −  is higher than the input voltage Vin + , and the difference between the input voltages Vin −  and Vin +  are equal to or above the minimum voltage difference ΔVid defined by formula (7), the power source V DD  provides the constant current source I 11  with the bias current having a current level of I 1 , and also provides the common terminal of the current mirror circuit CM 13  with a current having a current value of 2·I 2 . Therefore, the total static power consumption P (Tota1)  is represented by the following formula, if the current through the output terminal OUT is ignored: 
 
 P   (Total)   =V   DD ( I   1 +2 I   2 )  (18) 
 
         [0056]     On the other hand, when the input voltage Vin −  is lower than the input voltage Vin + , and the difference between the input voltages Vin −  and Vin +  is equal to or above the minimum voltage difference ΔVid defined by formula (7), the power source V DD  provides the constant current source I 11  with the bias current having the current level of I 1 , the common terminal of the current mirror circuit CM 14  with a current having the current level of 2·I 2 , and the input terminal of the current mirror circuit CM 15  with a current having the current level of I 1 +I 2 . Therefore, the total static power consumption P (Total)  is represented by the following formula, if the current through the output terminal OUT is ignored: 
 
 P   (Total)   =V   DD (2 I   1 +3 I   2 )  (19) 
 
         [0057]     The conventional differential amplifier shown in  FIG. 1  suffers from various drawbacks. Firstly, enhancing the operating speed requires increasing the bias currents developed by the constant current sources I 11  and I 12 .  
         [0058]     Additionally, the circuit architecture of the conventional differential amplifier is complicated; for example, two sets of differential transistors pairs DF 11  and DF 12  within the conventional differential amplifier necessitates performing an increased number of current mirroring steps.  
         [0059]     Furthermore, an increased number of the current mirror circuits develop output currents in response to the bias currents distributed by the constant current sources I 11  and I 12 , and this undesirably increases the power consumption.  
         [0060]     Additionally, there are different numbers of transistors along a signal path from the differential transistor pair DF 11  to the output terminal OUT, and along another signal path from the differential transistor pair DF 12  to the output terminal OUT. That is, the signal path from the differential transistor pair DF 12  requires additional one current mirroring step by using the current mirror circuits CM 13  or CM 14  to develop the output current to be added to the output current associated with the differential transistor pair DF 11 . In other words, the signal path from the differential transistor pair DF 12  to the output terminal OUT is long compared to that from the differential transistor pair DF 11 . This implies that the conventional differential amplifier circuit exhibits different characteristics in the cases where only the differential transistor pair DF 11  is activated and where only the differential transistor pair DF 12  is activated.  
       SUMMARY OF THE INVENTION  
       [0061]     In an aspect of the present invention, a voltage comparator circuit is composed of a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal, and a waveform shaping circuit achieving waveform shaping of the output signal received from the differential amplifier circuit. The differential amplifier circuit includes: a first differential transistor pair responsive to the pair of input signals to output first and second output currents; a second differential transistor pair complementary to the first differential transistor pair, and responsive to the pair of input signals to output third and fourth output currents; a first current mirror circuit developing a first internal current in response to the first output current; a third current mirror circuit complementary to the first current mirror circuit and developing a third internal current in response to the third output current; a second current mirror circuit developing a second internal current in response to the third output current and the third internal current; and a fourth current mirror circuit complementary to the first current mirror circuit and developing a fourth internal current in response to the fourth output current and the first internal current. A resultant current which is said second and fourth currents added together is drawn from or supplied to the output terminal of the differential amplifier circuit.  
         [0062]     In the voltage comparator circuit thus constructed, the number of circuit elements along a first signal path from the first differential transistor pair to the output terminal is allowed to be identical to that along a second signal path from the second differential transistor pair to the output terminal. Such architecture effectively improves circuit symmetry, and thereby enhances the performance of the voltage comparator circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0063]     The above and other advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanied drawings, in which:  
         [0064]      FIG. 1  shows a conventional differential amplifier circuit;  
         [0065]      FIG. 2  is a circuit diagram illustrating an exemplary structure of a differential amplifier stage;  
         [0066]      FIG. 3  is a graph illustrating input-to-output characteristics of the differential amplifier stage shown in  FIG. 2 ;  
         [0067]      FIG. 4  is a circuit diagram illustrating an exemplary structure of a voltage comparator circuit incorporating a differential amplifier circuit in one embodiment of the present invention;  
         [0068]      FIG. 5  illustrates a circuit structure example of a CMOS inverter;  
         [0069]      FIG. 6  illustrates a circuit diagram illustrating an exemplary circuit structure of a differential amplifier circuit according to the present invention;  
         [0070]      FIGS. 7A and 7B  illustrate specific circuit structures of current mirror circuits in one embodiment;  
         [0071]      FIGS. 8A and 8B  illustrate other specific circuit structures of current mirror circuits in one embodiment;  
         [0072]      FIG. 9  is a circuit diagram illustrating a circuit structure of the differential amplifier circuit according to the present invention in the case where the differential amplifier circuit incorporates the current mirror circuits shown in  FIGS. 8A and 8B ;  
         [0073]      FIG. 10  is a circuit diagram illustrating a circuit structure of the differential amplifier circuit according to the present invention in the case where the differential amplifier circuit incorporates the current mirror circuits shown in  FIGS. 7A and 7B ; and  
         [0074]      FIG. 11  is a graph illustrating waveforms of input and output voltages obtained a circuit simulation of voltage comparator circuit according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0075]     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art would recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.  
         [0076]     The design of the voltage comparator circuit according to the present invention is based on the analysis of the conventional differential amplifier circuit. In one embodiment, as shown in  FIG. 4 , a voltage comparator circuit is composed of a differential amplifier circuit  40  and a set of CMOS inverters  41  to  43 . The CMOS inverters  41  to  43  are serially-connected to the output of the differential amplifier circuit  40 . The serially-connected CMOS inverters  41  to  43  are used for waveform shaping. The CMOS inverter  43  functions as an output stage of the voltage comparator circuit.  
         [0077]     An exemplary circuit configuration of the CMOS inverters  41  to  43  is shown in  FIG. 5 . With reference to  FIG. 5 , the CMOS inverters  41  to  43  are each provided with an N-channel MOS transistor MN 51  and a P-channel MOS transistor MP 51 . The gates of the N-channel MOS transistor MN 51  and the P-channel MOS transistor MP 51  are commonly connected to the input terminal, and the drains thereof are commonly connected to the output terminal. The source of the P-channel MOS transistor MP 51  is connected to a power source V DD  (or a V DD  terminal), and the source of the N-channel MOS transistor MN 51  is connected to an earth terminal V SS  (or a V SS  terminal)  
         [0078]      FIG. 6  is a circuit diagram illustrating a circuit structure of the differential amplifier circuit  40  according to the present invention. The differential amplifier circuit  40  is provided with a first differential transistor pair DF 61  having P-channel MOS transistors MP 61  and MP 62 ; a second differential transistor pair DF 62  having N-channel MOS transistors MN 61  and MN 62 ; first to fourth current mirror circuits CM 61  to CM 64 ; and constant current sources I 61  and I 62 .  
         [0079]     The current mirror circuit CM 61  has an input terminal connected to the drain of the P-channel MOS transistor MP 61  within the differential transistor pair DF 61 , a common terminal connected to the earth terminal (or the V SS  terminal), and an output terminal connected to the input terminal of the current mirror circuit CM 64 .  
         [0080]     The current mirror circuit CM 62  has an input terminal connected to the drain of the P-channel MOS transistor MP 62  of the differential transistor pair DF 61 , a common terminal connected to the negative power source VSS (GND), and an output terminal connected to the output terminal OUT of the differential amplifier.  
         [0081]     The current mirror circuit CM 63  has an input terminal connected to the drain of the N-channel MOS transistor MN 61  of the differential transistor pair DF 62 ; a common terminal connected to the power supply terminal (or the V DD  terminal); and an output terminal connected to the drain of the P-channel MOS transistor MP 62  and also to the input terminal of the current mirror circuit CM 62 .  
         [0082]     The current mirror circuit CM 64  has an input terminal connected to the output of the current mirror circuit CM 61  and also to the drain of the N-channel MOS transistor MN 62  of the differential transistor pair DF 62 ; a common terminal connected to the power supply terminal; and an output terminal connected to the output terminal of the current mirror circuit CM 62 , and also to the output terminal OUT of the differential amplifier circuit.  
         [0083]     The constant current source I 61  is connected between the V DD  terminal and the commonly-connected sources of the P-channel MOS transistors MP 61  and MP 62 . On the other hand, the constant current source I 62  is connected between the V SS  terminal and the commonly-connected sources of the N-channel MOS transistors MN 61  and MN 62 .  
         [0084]     In the differential amplifier circuit, the gates of the P-channel MOS transistor MP 61  and the N-channel MOS transistor MN 61  are commonly connected to an inverting input terminal In − , and the gates of the P-channel MOS transistor MP 62  and the N-channel MOS transistor MN 62  are commonly connected to a non-inverting input terminal In + . The differential amplifier circuit adopts the circuit architecture incorporating two complementary differential transistor pairs, and thereby enlarges the allowable input voltage range approximately between the voltage levels V SS  and V DD .  
         [0085]     The current mirror circuits CM 61  and CM 62  provide current mirroring for the respective drain outputs of the differential transistor pair DF 61 . Correspondingly, the current mirror circuits CM 63  and CM 64  provide current mirroring for the respective drain outputs of the differential transistor pair DF 62 . The output of the current mirror circuit CM 61  is connected to the input of the current mirror circuit CM 64 . The output of the current mirror circuit CM 63  is connected to the input of the current mirror circuit CM 62 . The outputs of the current mirror circuits CM 62  and CM 64  are commonly connected to the output terminal OUT.  
         [0086]     The current mirror circuits CM 62  and CM 64  are designed to have a mirror ratio of k (&gt;1); the ratio of the input current to the output current is 1:k within the current mirror circuits CM 62  and CM 64 . Setting the mirror ratio k to a value larger than one effectively improves the drive capability of the differential amplifier circuit. In addition, the circuit architecture effectively improves symmetry of the circuit characteristics, in which the number of circuit stages along the signal path associated with the P-channel differential transistor pair is the same as that associated with the P-channel differential transistor pair is same.  
         [0087]     Operation of the differential amplifier circuit shown in  FIG. 6  is described below. The circuit shown in  FIG. 6  adopts the rail-to-rail differential amplifier architecture. The differential amplifier circuit in this embodiment operates differently depending on the voltage levels of the input voltages, especially, in terms of operations of the constant current sources I 61  and I 62 .  
         [0088]     In order to activate the constant current source I 61 , it is necessary to establish a sufficient drain-source voltage across a P-channel MOS transistor (not shown) within the constant current source I 61 . In order to achieve this, the input voltages Vin −  and Vin +  of the inverting and non-inverting input terminals In −  and In +  are required to satisfy the following formula: 
 
 V in&lt; V   DD −( V   GS(MP)   +V   DS(sat)(I61) ), 
 
 where Vin is any of the input voltages Vin −  and Vin + , V DS(sat)(I61)  is the drain-source voltage at saturation of the P-channel MOS transistor within the constant current source I 61 , and V GS(MP)  is the gate-source voltage of the P-channel MOS transistors MP 61  or MP 62 . 
 
         [0089]     Correspondingly, in order to activate the constant current source I 62 , it is necessary to establish a sufficient drain-source voltage across an N-channel MOS transistor (not shown) within the constant current source I 62 . The input voltages Vin −  and Vin +  of the inverting and non-inverting input terminals In −  and In +  are required to satisfy the following formula: 
 
 V in&gt; V   GS(MN61)   +V   DS(sat)(I62) , 
 
 where V DS(sat)(I62)  is the drain-source voltage at saturation of the N-channel MOS transistor within the constant current source I 62 , and V GS(MN)  is the gate-source voltage of the N-channel MOS transistors MN 61  or MN 62 . 
 
         [0090]     In other words, both of the differential transistor pairs DF 61  and DF 62  are activated when it holds: 
 
 V   GS(MN)   +V   DS(sat)(I62)   &lt;Vin   −   &lt;V   DD −( V   GS(MP)   +V   DS(sat)(I61) ). 
 
         [0091]     Additionally, only the differential transistor pair DF 62  is activated with the differential transistor pair DF 61  deactivated, when it holds: 
 
 V in&gt; V   DD ( V   GS(MP61)   +V   DS(sat)(I61) ). 
 
         [0092]     Finally, only the differential transistor pair DF 61  is activated with the differential transistor pair DF 62  deactivated, when it holds: 
 
 V in&lt; V   GS(MN)   +V   DS(sat)(I62) . 
 
         [0093]     (1) In Case where Both the First and Second Differential Transistor Pairs DF 61  and DF 62  are Activated  
         [0094]     A description of the operation of the differential amplifier circuit in this embodiment is given for a case where the input voltage Vin −  is higher than the input voltage Vin + , and the voltage difference between the input voltages Vin −  and Vin +  is equal to or above the minimum voltage difference ΔVid defined by formula (7) with both of the differential transistor pairs DF 61  and Df 62  activated.  
         [0095]     In this case, the bias current I 1  flows only through the P-channel MOS transistor MP 62  within the first differential transistor pair DF 61 , and the current through the P-channel MOS transistor MP 61  is set nil. On the other hand, the bias current I 2  flows only through the N-channel MOS transistor MN 61  within the second differential transistor pair DF 62 , and the current through the N-channel MOS transistor MN 62  is set nil.  
         [0096]     In this operation, each current mirror circuit operates as follows. The output current of the current mirror circuit CM 61  is set nil since the input terminal of the current mirror circuit CM 61  is connected with the drain of the P-channel MOS transistor MP 61 , and the drain current thereof is nil. The input terminal of the current mirror circuit CM 63  is connected to the drain of the N-channel MOS transistor MN 61 . The drain current of the N-channel MOS transistor MN 61  is set to I 2 , and therefore an output current I OUT(CM63)  of the current mirror circuit CM 63  is also set to I 2 .  
         [0097]     The input terminal of the current mirror circuit CM 62  is connected with the drain of the P-channel MOS transistor MP 62  and also with the output terminal of the current mirror circuit CM 63 . Since the drain current of the P-channel MOS transistor MP 62  is I 1  and the output current of the current mirror circuit CM 63  is I 2 , the current mirror circuit CM 62  receives a current (I 1 +I 2 ) on the input terminal thereof. In addition, since the mirror ratio of the current mirror circuit CM 62  is k, the output current I OUT(CM62)  of the current mirror circuit CM 62  is represented by the following formula: 
 
 I   OUT(CM 62)   =k ( I   1   +I   2 )  (20) 
 
 In other words, the current mirror circuit CM 62  draws the output current I OUT(CM62)  through the output terminal thereof, and the voltage level on the output terminal is pulled down to the low level, namely, to the potential level V SS . 
 
         [0098]     The input terminal of the current mirror circuit CM 64  is connected with the drain of the N-channel MOS transistor MN 62  and also with the output terminal of the current mirror circuit CM 61 . Since the drain current of the N-channel MOS transistor MN 62  and the output current of the current mirror circuit CM 61  are both nil, the output current of the current mirror circuit CM 64  is also nil.  
         [0099]     Therefore, the differential amplifier circuit in this embodiment draws a current having a current level of k·(I 1 +I 2 ) from the output terminal OUT, and the voltage level on the output terminal is pulled down to the low level, namely, to the potential level V SS .  
         [0100]     Next, a description is made for a case where the input voltage Vin −  is lower than the input voltage Vin + , and the difference between the input voltages Vin −  and Vin +  is equal to or above the minimum voltage difference ΔVid defined by formula (7).  
         [0101]     In this case, the bias current I 1  flows only through the P-channel MOS transistor MP 61  within the first differential transistor pair DF 61 , and the current through the P-channel MOS transistor MP 62  is set nil. On the other hand, the bias current I 2  flows only through the N-channel MOS transistor MN 62  within the second differential transistor pair DF 62 , and the current through the N-channel MOS transistor MN 61  is set nil.  
         [0102]     In this case, each current mirror circuit operates as follows. The drain current of the P-channel MOS transistor MP 61  is I 1 , and the drain thereof is connected with the input terminal of the current mirror circuit CM 61 . Therefore, the output current of the first current mirror circuit CM 61  is also I 1 .  
         [0103]     The drain current of the current mirror circuit CM 63  is nil, and the drain thereof is connected with the input terminal of the current mirror circuit CM 63 . Therefore, the output current of the third current mirror circuit CM 63  is also nil. The second current mirror circuit CM 62  receives an input current which is the drain current of the P-channel MOS transistor MP 62  and the output current of the third current mirror circuit CM 63  added together. Since these currents are both nil, the input current and the output current of the second current mirror circuit CM 62  are both nil.  
         [0104]     The input terminal of the fourth current mirror circuit CM 64  is connected to the drain of the N-channel MOS transistor MN 62 , and also to the output terminal of the first current mirror circuit CM 61 . The fourth current mirror circuit CM 64  receives an input current having a current level of (I 2 +I 1 ), which is the drain current of the N-channel MOS transistor MN 62  and the output current of the first current mirror circuit CM 61  added together. Since the fourth current mirror circuit CM 64  has a mirror ratio of k, an output current I OUT(CM64)  of the fourth current mirror circuit CM 64  is represented by the following formula: 
 
 I   OUT(CM 64)   =k ( I   1   +I   2 )  (21) 
 
         [0105]     Therefore, the differential amplifier circuit supplies the current I OUT (=k(I 2 +I 1 )) from the output terminal OUT thereof, and the voltage level of the output terminal OUT is pulled up to the high level, namely, to the power supply level VDD.  
         [0106]     As is understood from formulas (20) and (21), the current level of the pull-down current is identical to that of the pull-up current on the output terminal OUT. Therefore, rising and falling edges are shaped in a symmetry manner even when the output terminal is connected with an increased load capacitance. This advantageously helps the voltage comparator to develop a digital signal having a duty ratio of 50% through waveform shaping.  
         [0107]     The above-mentioned is the description for the case where both the differential transistor pairs DF 61  and DF 62  are activated. Decrease in a common-mode signal voltage of the input differential signals results in that the differential transistor pair DF 62 , which consists of the N-channel transistors, is deactivated. Increase in the common-mode signal voltage of the input differential signals, on the other hand, the differential transistor pair DF 61 , which consists of the P-channel transistors, is deactivated. Operations in these respective cases are described in the following.  
         [0108]     (2) In Case where Only the First Differential Transistor Pair DF 61  is Activated  
         [0109]     First, a description is made of a case where the common-mode signal voltage of the input differential signals is decreased so that only the first differential transistor pair DF 61  is activated with the second differential transistor pair DF 62  deactivated.  
         [0110]     Referring to  FIG. 6 , the constant current source I 62 , which provides the bias current I 2  for the N-channel differential transistor pair DF 62 , is composed of an N-channel MOS transistor. The bias current I 2  is controlled to a desired current level by controlling the voltage level on the gate of this N-channel MOS transistor.  
         [0111]     In this case, the minimum input voltage Vin(min) at which the N-channel differential transistor pair DF 62  is activated is represented by the following formula: 
 
 V   in(min.)   =V   GS(MN)   +V   DS(sat)(I62)   (22) 
 
 Where V GS(MN)  is the gate-source voltage of the N-channel MOS transistor MN 61  or MN 62 , and V DS(sat)(I62)  is the drain-source voltage at saturation point of the N-channel MOS transistor within the constant current source I 62 . The drain-source voltage at saturation of the N-channel MOS transistor is defined as a voltage barely enough to operate in the pentode region. 
 
         [0112]     The N-channel differential transistor pair DF 62  is deactivated when any of the input voltages is equal to or below Vin(min); in this case only the P-channel differential transistor pair DF 61  is activated.  
         [0113]     First, a description is made of a case where the input voltage Vin − , which is the input voltage of the inverting input terminal In − , is higher than that of the input voltage Vin + , which is the input voltage of the non-inverting input terminal In + , with only the P-channel differential transistor pair DF 61  activated In this case, the bias current I 1  flows only through the second P-channel MOS transistor MP 62  within the first differential transistor pair DF 61 , and the current through the first P-channel MOS transistor MP 61  is set nil. On the other hand, the second differential transistor pair DF 62  is deactivated, and therefore the drain currents of the first and second N-channel MOS transistors MN 61  and MN 62  are both set nil.  
         [0114]     In this case, each current mirror circuit operates as follows. Since the second differential transistor pair DF 62  is deactivated, the input current of the third current mirror circuit CM 63  connected to the second differential transistor pair DF 62  is nil. Therefore, the output current of the current mirror circuit CM 63  is nil. The input current of the current mirror circuit CM 64  is also nil, because the drain current of the N-channel MOS transistor MN 62  is nil.  
         [0115]     The input current of the first current mirror circuit CM 61 , having the input terminal connected to the drain of the first P-channel MOS transistor MP 61 , is nil, and therefore the output current thereof is consequently nil. Therefore, the input current of the current mirror circuit CM 64 , which is output current of the current mirror circuit  61  and the drain current of the N-channel MOS transistor MN 62  added together, is nil. Accordingly, the output current of the current mirror circuit CM 64  is also set nil.  
         [0116]     The input current of the second current mirror circuit CM 62  is identical to the drain current of the P-channel MOS transistor MP 62 , because the input terminal of the second current mirror circuit CM 61  is connected to the drain of the P-channel MOS transistor MP 62  and also to the output terminal of the third current mirror circuit CM 63 , and the output current of the third current mirror circuit CM 63  is nil. Therefore, the output current I OUT(CM62)  of the second current mirror circuit CM 62  is represented by the following formula: 
 
 I   OUT(CM 62)   =kI   1   (23) 
 
         [0117]     In other words, the differential amplifier circuit  40  draws the current I OUT (=k·I 1 ) from the output terminal OUT. The voltage level on the output terminal OUT is pulled down to the low level, that is, to the earth level V SS .  
         [0118]     Next, a description is made of a case where the input voltage Vin −  is lower than the input voltage Vin + . When the difference of the input voltages Vin −  and Vin +  is larger than the minimum voltage difference ΔVid defined by formula (7), the bias current I 1  flows only through the first P-channel MOS transistor MP 61  within the first differential transistor pair DF 61 , and the current through the second P-channel MOS transistor MP 62  is nil. On the other hand, the second differential transistor pair DF 62  is deactivated, and thus the drain currents of the first N-channel MOS transistor MN 61  and the second N-channel MOS transistor MN 62  are set nil.  
         [0119]     In this case, each current mirror circuit operates as follows. Since the second differential transistor pair DF 62  is deactivated, the input current of the third current mirror circuit CM 63 , having the input terminal connected to the second differential transistor pair DF 62 , is set nil. Therefore, the output current of the third current mirror circuit CM 63  is nil. Also, the input current of the current mirror circuit CM 64  is nil, because the input terminal of the current mirror circuit CM 64  is connected to the drain of the N-channel MOS transistor MN 62  with the drain current thereof being nil.  
         [0120]     The input current of the first current mirror circuit CM 61 , having the input terminal connected to the drain of the first P-channel MOS transistor MP 61 , has a current level of I 1 , being identical to the drain current of the P-channel MOS transistor MP 61 , and the output current of the first current mirror circuit CM 61  consequently has a current level of I 1 .  
         [0121]     The input current of the second current mirror circuit CM 62 , having the input terminal connected to the drain of the second P-channel MOS transistor MP 62  and the output terminal of the third current mirror circuit CM 63 , is set nil, since both of the drain current of the second P-channel MOS transistor MP 62  and the output current of the third current mirror circuit CM 63  are nil. Therefore, the output current of the second current mirror circuit CM 62  is also set nil.  
         [0122]     The input current of the fourth current mirror circuit CM 64 , having the input terminal connected to the drain of the second N-channel MOS transistor MN 62  and the output terminal of the first current mirror circuit CM 61 , has a current level of I 1 , since the drain current of the second N-channel MOS transistor MN 62  is nil and the output current of the first current mirror circuit CM 61  has a current level of I 1 . Additionally, the fourth current mirror circuit CM 64  has a mirror ratio of k. Therefore, the output current I OUT(CM64)  of the fourth current mirror circuit CM 64  is represented by the following formula: 
 
 I   OUT(CM 64)   =kI   1   (24) 
 
         [0123]     In this operation, the differential amplifier circuit  40  supplies the current I OUT (=k·I 1 ) from the output terminal OUT. The voltage level on the output terminal OUT is pulled up to the high level, that is, to the power supply level V DD .  
         [0124]     As is understood from formulas (23) and (24), the current level of the pull-down current is identical to that of the pull-up current on the output terminal OUT. Therefore, rising and falling edges are shaped in a symmetry manner even when the output terminal is connected with an increased load capacitance. This advantageously helps the voltage comparator to develop a digital signal having a duty ratio of 50% through waveform shaping.  
         [0125]     (3) In Case where Only the Second Differential Transistor Pair DF 62  is Activated  
         [0126]     Next, a description is made of a case where the common-mode signal voltage of the input voltages Vin −  and Vin +  is increased so that the first differential transistor pair DF 61  is deactivated with only the second differential transistor pair DF 62  activated.  
         [0127]     Referring to  FIG. 6 , the constant current source I 61 , which provides the bias current I 1  for the P-channel differential transistor pair DF 61 , is composed of a P-channel MOS transistor. The bias current I 1  is controlled to a desired current level by controlling the voltage level on the gate of this P-channel MOS transistor.  
         [0128]     In this case, a maximum input voltage Vin(max) at which the P-channel differential transistor pair DF 61  is activated is represented by the following formula: 
 
 V   in(max.)   =V   DD −( V   GS(MP)   +V   DS(sat)(I61) )  (25) 
 
 where V GS(MP)  is the gate-source voltage of the P-channel MOS transistors MP 61  or MP 62 , and V DS(sat)(I61)  is the drain-source voltage at saturation of the P-channel MOS transistor within the constant current source I 61 . The drain-source voltage at saturation of the P-channel MOS transistor is defined as a voltage barely enough to operate in the pentode region. 
 
         [0129]     The P-channel differential transistor pair DF 61  is deactivated when any of the input voltages is equal to or above Vin(max); in this case only the N-channel differential transistor pair DF 62  is activated.  
         [0130]     Firstly, a description is made of a case where the input voltage Vin −  is higher the input voltage Vin +  with only the N-channel differential transistor pair DF 62  activated. In this case, the bias current I 2  flows only through the N-channel MOS transistor MN 61  within the second differential transistor pair DF 62 , and the current through the second N-channel MOS transistor MN 62  is set nil. On the other hand, the first differential transistor pair DF 61  is deactivated, and therefore the drain currents of the first P-channel MOS transistor MP 61  and the second P-channel MOS transistor MP 62  are nil.  
         [0131]     In this case, each current mirror circuit operates as follows. Since the first differential transistor pair DF 61  is deactivated, the input current of the first current mirror circuit CM 61 , having the input terminal connected to the first differential transistor pair DF 61 , is nil. Therefore, the output current of the current mirror circuit CM 61  is set nil. The input current of the third current mirror circuit CM 63 , having the input terminal connected to the drain of the first N-channel MOS transistor MN 1 , has a current level of I 2 , since the drain current of the first N-channel MOS transistor MN 1  has a current level of I 2 . Therefore, the output current of the third current mirror circuit CM 63  also has a current level of I 2 .  
         [0132]     The input terminal of the second current mirror circuit CM 62  is connected to the output terminal of the third current mirror circuit CM 63 , and also to the drain of the second P-channel MOS transistor MP 62 . The P-channel differential transistor pair MP 61  is deactivated, and thus the drain current of the second P-channel MOS transistor MP 62  is nil. Therefore, the input current of the second current mirror circuit CM 62  has a current level of I 2 , and the current level I OUT(CM62)  of the output current of the second current mirror circuit CM 62  is represented by the following formula: 
 
 I   OUT(CM 62)   =kI   2   (26) 
 
         [0133]     The input current of the fourth current mirror circuit CM 64 , having the input terminal connected to the drain of the second N-channel MOS transistor MN 62  and the output terminal of the first current mirror circuit CM 61 , is nil, because the drain current of the second N-channel MOS transistor MN 62  and the output current of the first current mirror circuit CM 61  are both nil. Therefore, the output current of the fourth current mirror circuit is also nil.  
         [0134]     Accordingly, the differential amplifier circuit  40  draws the output current I OUT (=k·I 2 ) from the output terminal OUT, and the voltage level on the output terminal OUT is consequently pulled down to the low level, that is, to the earth level V SS .  
         [0135]     Next, a description is made of a case where the input voltage Vin −  is lower than the input voltage Vin +  with only the second differential transistor pair DF 62  activated. When the difference between the input voltages Vin −  and Vin +  is larger than the minimum voltage difference ΔVid defined by formula (7), the bias current I 2  flows only through the second N-channel MOS transistor MN 62  within the second differential transistor pair DF 62 , and the current through the first N-channel MOS transistor MN 61  is set nil. On the other hand, the first differential transistor pair DF 61  is deactivated, and therefore the drain currents of both of the first and second P-channel MOS transistors MP 61  and MP 62  are nil.  
         [0136]     In this case, each current mirror circuit operates as follows. Since the first differential transistor-pair DF 61  is deactivated, the input current of the first current mirror circuit CM 61  connected to the first differential transistor pair DF 61  is nil. Therefore, the output current of the first current mirror circuit CM 61  is nil.  
         [0137]     Additionally, the input current of the third current mirror circuit CM 63 , having the input terminal connected to the drain of the first N-channel MOS transistor MN 61 , is set nil, since the drain current of the first N-channel MOS transistor MN 61  is nil. Therefore, the output current of the third current mirror circuit CM 63  is also set nil.  
         [0138]     The input terminal of the second current mirror circuit CM 62  is connected with the output terminal of the third current mirror circuit CM 63  and the drain of the second P-channel MOS transistor MP 62 . Since the P-channel differential transistor pair DF 61  is deactivated, the drain current of the second P-channel MOS transistor MP 62  is nil. The output current of the third current mirror circuit CM 63  is also nil. Therefore, the input current of the second current mirror circuit CM 62  is nil, and the output current I OUT(CM62)  thereof is consequently nil.  
         [0139]     The input terminal of the fourth current mirror circuit CM 64  is connected to the output terminal of the first current mirror circuit CM 61  and the drain of the second N-channel MOS transistor MN 62 . Since the output current of the first current mirror circuit CM 61  is nil and the drain current of the second N-channel MOS transistor MN 62  has a current level of I 2 , the input current of the fourth current mirror circuit CM 64  has a current level of I 2 . Additionally, the fourth current mirror circuit CM 64  has a mirror ratio of k. Therefore, the output current I OUT(CM64)  of the fourth current mirror circuit CM 64  is represented by the following formula: 
 
 I   OUT(CM 64)   =kI   2   (27) 
 
         [0140]     In other words, the differential amplifier circuit  40  supplies the current I OUT (=k·I 2 ) from the output terminal OUT. The voltage level on the output terminal OUT is pulled up to the high level, that is, to the power supply level V DD .  
         [0141]     As is understood from formulas (26) and (27), the current level of the pull-down current is identical to that of the pull-up current on the output terminal OUT. Therefore, rising and falling edges are shaped in a symmetry manner even when the output terminal is connected with an increased load capacitance. This advantageously helps the voltage comparator to develop a digital signal having a duty ratio of 50% through waveform shaping.  
         [0142]     Thus, the current level of the pull-down current is identical to that of the pull-up current, even when the operations of the first differential transistor pair DF 61  and the second differential transistor pair DF 62  are switched. This allows the output digital signal to have a duty ratio of 50% after the waveform shaping due to the waveform symmetry.  
         [0143]     A description is then given of analysis of the power consumption of the differential amplifier circuit  40  shown in  FIG. 6 . The analysis addresses a case where both of the differential transistor pairs DF 61  and DF 62  are activated.  
         [0144]     When the input voltage Vin −  is higher than the input voltage Vin + , and the difference therebetween is equal to or above the minimum voltage difference ΔVid defined by formula (7), the current through the current mirror circuit CM 64  is nil. The power supply V DD  provides the first constant current source I 61  with a current having a current level of I 1 , and the common terminal of the third current mirror circuit CM 63  with a current having a current level of 2I 2 . Consequently, the total static power consumption P (Total)  is represented by the following formula: 
 
 P   (Total)   =V   DD ( I   1 +2 I   2 )  (28) 
 
 It should be noted that the current through the output terminal OUT is ignored in this analysis. 
 
         [0145]     On the other hand, when the input voltage Vin −  is lower than input voltage Vin + , and the difference between the input voltages Vin −  and Vin +  is equal to or above the minimum voltage difference ΔVid defined by formula (7), the current through the third current mirror circuit CM 63  is nil. The power supply V DD  provides the first constant current source I 61  with a current having a current level of I 1 , and the input terminal of the fourth current mirror circuit CM 4  with a current having a current level of I 1 +I 2 . It should be noted that the current through the output terminal of the fourth current mirror circuit CM 4  is the current flowing outside from the output terminal OUT. Consequently, the total static power consumption P (Total)  is indicated by the following formula: 
 
 P   (Total)   =V   DD (2 I   1   +I   2 )  (29) 
 
 It should be noted that the current through the output terminal OUT is ignored in this analysis. 
 
         [0146]     As is understood from the comparison of the formulas (28) and (29) with the formulas (18) and (19), the power consumption presented by formula (29) is lower than that presented by formula (19). In other words, the power consumption of the differential amplifier circuit  40  shown in  FIG. 6  is lower than that of the differential amplifier circuit shown in  FIG. 1 .  
         [0147]     Although the voltage comparator circuit is desired to develop a rectangular wave, the output signal of the differential amplifier circuit  40  shown in  FIG. 6  exhibits waveform distortion as the increase in the frequency. In this embodiment, therefore, a set of CMOS inverter circuit  41  to  43  is serially connected to the output of the differential amplifier circuit  40  as shown in  FIG. 4 . The serially-connected CMOS inverter circuits  41  to  43  provide waveform shaping to develop a rectangular wave. Specifically, the threshold level of the CMOS inverters  41  to  43  is set to approximately half of the VDD. When the level of the input of each inverter is lower than the threshold level, each inverter pulls up the output thereof to the high level (V DD ). When the level of the input of each inverter is higher than the threshold level, on the other hand, each inverter pulls down the output thereof to the low level (V SS ). Such operation achieves waveform shaping. The use of the multiple CMOS inverters is effective for achieve improved waveform shaping compared to a case where only one CMOS inverter is used for the waveform shaping.  
         [0148]     The following is a description of the current mirror circuits incorporated within the differential amplifier circuit  40  shown in  FIG. 6 . Shown in  FIGS. 7A and 7B  are Widlar-type current mirror circuits.  FIG. 7A  illustrates a current mirror circuit CM 7   a  configured to draw a pair of input and output currents. The current mirror circuit CM 7   a  is provided with an N-channel MOS transistor MN 71  and an N-channel MOS transistor MN 72 . The gates of the N-channel MOS transistors MN 71  and MN 72  are commonly connected to the drain of the N-channel MOS transistor MN 71 . The drain of the N-channel MOS transistor MN 71  is connected the input terminal of the current mirror circuit CM 7   a . The sources of the N-channel MOS transistors MN 71  and MN 72  are commonly-connected to the common terminal of the current mirror circuit CM 7   a . The drain of the N-channel MOS transistor MN 72  is connected to the output terminal of the current mirror circuit CM 7   a.    
         [0149]      FIG. 7B  illustrates a current mirror circuit CM 7   b  configured to output a pair of input and output currents. The current mirror circuit CM 7   b  is provided with P-channel MOS transistors MP 71  and MP 72 . The gates of the P-channel MOS transistors MP 71  and MP 72  are commonly connected to the drain of the P-channel MOS transistor MP 71 . The drain of the P-channel MOS transistor MP 71  is connected to the input terminal of the current mirror circuit CM 7   b . The sources of the P-channel MOS transistors MP 71  and MP 72  are commonly-connected to the common terminal of the current mirror circuit CM 7   b . The drain of the P-channel MOS transistor MP 72  is connected to the output terminal.  
         [0150]     The mirror ratio k of the current mirror circuit CM 7   a  is dependent on the dimensions of the gate widths and lengths of the N-channel MOS transistors MN 71  and MN 72 . When the gate width and length of the N-channel MOS transistor MN 71  or the P-channel MOS transistor MP 71  are WM 1  and LM 1 , respectively, and the gate width and length of the N-channel MOS transistor MN 72  are WM 2  and LM 2 , respectively, the following formula holds:  
                   W   M1       L   M1       ⁢     :     ⁢       W   M2       L   M2         =     1   ⁢     :     ⁢   k             (   30   )             
 
 The same applies for the current mirror circuit CM 7   b.  
 
         [0151]     In this time, a relation of the input and output currents I in  and I OUT  of the current mirror circuits CM 7   a  (or CM 7   b ) is given by the following formula: 
 
 I   OUT   =kI   in   (31) 
 
         [0152]     This is based on the fact that a drain current I D  is proportional to W/L as is depicted by the formulas (2) to (4) which indicates a relation of the gate-source voltage VGS and the drain current ID of the MOS transistor. The ratios of the gate widths (W) to the gate lengths (L) of the MOS transistors are adjusted to achieve the desired mirror ratio k.  
         [0153]      FIG. 10  is a circuit diagram illustrating a specific circuit structure in which the current mirrors shown in  FIGS. 7A and 7B  are incorporated as the current mirror circuits CM 61  to CM 64  within the differential amplifier circuit  40  shown in  FIG. 6 . The association of circuit elements within the differential amplifier circuit shown in  FIG. 10  with those within the differential amplifier circuit shown in  FIG. 6  is as follows.  
         [0154]     The first differential transistor pair DF 61  in  FIG. 6  corresponds to a differential transistor pair DF 101  in  FIG. 10 , and the P-channel MOS transistors MP 61  and MP 62  within the differential transistor pair DF 61  correspond to P-channel MOS transistors MP 101  and MP 102 , respectively. The second differential transistor pair DF 62  corresponds to a differential transistor pair Df 102 , and the N-channel MOS transistors MN 61  and MN 62  within the differential transistor pair DF 62  correspond to N-channel MOS transistors MN 101  and MN 102 , respectively.  
         [0155]     The first current mirror circuit CM 61  corresponds to a current mirror circuit CM 101 , and the input and output terminals of the first current mirror circuit CM 61  correspond to the drains of N-channel MOS transistors MN 103  and MN 104 , respectively. The second current mirror circuit CM 62  corresponds to a current mirror circuit  102 , and the input and output terminals of the second current mirror circuit CM 62  correspond to the drains of N-channel MOS transistors MN 105  and MN 106 , respectively. The third current mirror circuit CM 63  corresponds to a current mirror circuit  103 , and the input and output terminals of the third current mirror circuit CM 63  correspond to the drains of P-channel MOS transistors MP  103  and MP  104 , respectively. The fourth current mirror circuit CM 64  corresponds to a current mirror circuit  104 , and the input and output terminals correspond to the drains of the P-channel MOS transistors MP 105  and MP 106 , respectively. The constant current sources I 61  and I 62  correspond to constant current sources I 101  and I 102 , respectively.  
         [0156]     Strictly speaking, the allowable input voltage range of the differential amplifier circuit shown in  FIG. 10  does not cover the entire voltage range between the earth level V SS  and the power supply level V DD  due to voltage drops across the respective current mirror circuits. That is, there are operation regions where the differential amplifier circuit does not operate in the vicinities of the earth level V SS  (GND) and the power supply level V DD . This implies that the differential amplifier circuit shown in  FIG. 10  does not achieve rail-to-rail operation in a strict sense.  
         [0157]     For example, the allowed input voltage range in the vicinity of the earth level V SS  (GND) is represented by the following formula: 
 
 V   in   &lt;V   (CM)   −V   GS(MP)   +V   DS(sat)   (32) 
 
 where Vin is any of the input voltages of the input terminals In −  and In + , and V (CM)  is the voltage drop across the current mirror circuit; V GS(MP)  is the gate-source voltage of the P-channel MOS transistor MP 101  or MP 102 , and V DS(sat)  is the drain-source voltage at saturation of the P-channel MOS transistor MP 101  or MP 102 . The drain-source voltage at saturation of the P-channel MOS transistor MP 101  or MP 102  is defined as a voltage barely enough to operate in the pentode region. 
 
         [0158]     Inputting the input voltages that dissatisfy the requirement defined by formula (32) results in that desired characteristics is not obtained. The voltage drop V (CM)  across the current mirror circuits in  FIG. 7B  is indicated by the following formula: 
 
 V   (CM)   =V   GS   (33) 
 
 where V GS  is the gate-source voltage of the MOS transistor, represented by the following formula:  
                 V   GS     =           2   ⁢     I   D       β       +     V   T         ⁢     
     ⁢     β   =       W   L     ⁢   μ   ⁢           ⁢     C   0                 (   34   )             
 
 where V T  is the threshold voltage of the MOS transistor, and I D  is the drain current. 
 
         [0159]     The voltage drop V (CM)  in formula (33) is identical to the gate-source voltage V GS  of the N-channel MOS transistor, and the voltage V GS(MP)  in formula (32) is identical to the gate-source voltage VGS of the P-channel MOS transistor. Therefore, formula (32) implies that the input voltage Vin may not be allowed to be decreased down to the earth level V SS  due to variations of the circuit elements. The same goes for the operation range in the vicinity of the power supply level V DD . That is, the input voltage Vin may not be allowed to be increased up to the power supply level V DD  due to variations of the circuit elements.  
         [0160]     The current mirror circuit structures shown in  FIGS. 8A and 8B  effectively decrease the voltage drops V (CM)  across the current mirror circuits, that is, effectively enlarges the allowable input voltage range compared with the current mirror circuit structures shown in  FIGS. 7A  and  7 B.  
         [0161]     The current mirror circuit structures shown in  FIGS. 8A and 8B  are described in the following.  FIG. 8A  illustrates a structure of a current mirror circuit CM 8   a  configured to draw a pair of input and output currents. The current mirror circuit CM 8   a  is provided with N-channel MOS transistors MN 81 , MN 82 , and MN 83 , and a constant current source I 8   a  and a constant voltage source V 8   a . The input terminal of the current mirror circuit CM 8   a  is connected to the drain of the N-channel MOS transistor MN 81  and also to the source of the N-channel MOS transistor MN 83 . The drain of the N-channel MOS transistor MN 83  is connected to the gates of the N-channel MOS transistors MN 81  and MN 82 , and also to the constant current source I 8   a . The gate of the N-channel MOS transistor MN 83  is connected to the constant voltage source V 8   a , and is pull up to a voltage level of the voltage V 1  with respect to the common terminal. The drain of the N-channel MOS transistor MN 82  is connected to the output terminal of the current mirror circuit CM 8   a . The sources of the N-channel MOS transistors MN 82  and MN 81  are commonly-connected to the common terminal of the current mirror circuit CM 8   a.    
         [0162]      FIG. 8B  illustrates a current mirror circuit CM 8   b  configured to supply a pair of input and output currents. The current mirror circuit CM 8   b  is provided with P-channel MOS transistors MP 81 , MP 82 , and MP 83 , a constant current source I 8   b , and a constant voltage source V 8   b . The input terminal of the current mirror circuit CM 8   b  is connected to the drain of the P-channel MOS transistor MP 81  and the source of the P-channel MOS transistor MP 83 . The drain of the P-channel MOS transistor MP 83  is connected to the gates of the P-channel MOS transistors MP 81  and MP 82 , and the constant current source I 8   b . The gate of the P-channel MOS transistor MP 83  is connected to the constant voltage source V 8   b , and is set to a voltage level lower by V 1  than the voltage level of the common terminal. The drain of the P-channel MOS transistor MP 82  is the output terminal of the current mirror circuit CM 8   b . The sources of the P-channel MOS transistors MP 82  and MP 81  are connected, and the connection point is the common terminal of the current mirror circuit CM 8   b.    
         [0163]     A description is made of the input-to-output characteristics of the current mirror circuits CM 8   a /CM 8   b  in the following. The current Iin from the input terminal and the current I 1  from the constant current source I 8   a  (or I 8   b ) flow through the drain of the N-channel MOS transistor MN 81  or the P-channel MOS transistor MP 81 . Therefore, a drain current I D(M1)  of the N-channel MOS transistor MN 81  or the P-channel MOS transistor MP 81  is the currents Iin and I 1  added together, and therefore the drain current I D(M1)  is represented by the following formula: 
 
 I   D(M 1)   =I   in   +I   1   (35) 
 
         [0164]     When dimensions of the N-channel MOS transistors MN 81  and MN 82  are designed as defined by formula (30), a relation of the input and output currents Iin and I OUT  of the current mirror circuits CM 8   a  and CM 8   b  is represented by the following formula: 
 
 I   OUT   =k ( I   in   +I   1 )  (36) 
 
         [0165]     When the input current Iin is extremely larger than the constant current I 1 , the following formula holds: 
 
 I   OUT   ≅kI   in   (37) 
 
         [0166]     Formula (37) indicates that the current mirror circuits in  FIG. 8A  operate to exhibit a mirror ratio of k.  
         [0167]     The current mirror circuit structures shown in  FIGS. 8A and 8B  effectively reduces the voltage drops thereacross compared to those of the current mirror circuits shown in  FIGS. 7A and 7B . The voltage drops V (CM)  across the current mirror circuits shown in  FIGS. 8A and 8B  are represented by the following formula: 
 
 V   (CM)   =V   1   −V   GS(M 3)   (38) 
 
 where V 1  is the voltage developed by the constant voltage source V 8   a  or V 8   b , and V GS(M3)  is the gate-source voltage of the N-channel MOS transistor MN 83  or the P-channel MOS transistor MP 83 . 
 
         [0168]     There is a limit to the reduction in the voltage drop V (CM)  across the current mirror circuits due to the fact that the voltage V 1  is required to satisfy a certain requirement. Specifically, the voltage V 1  is required to satisfy a condition in which the N-channel MOS transistor MN 81  or the P-channel MOS transistor MP 81  operates in the pentode region. The condition is represented by the following formula: 
 
 V   DS(sat)(M 1)   &lt;V   1   −V   GS(M 3)   (39) 
 
 where V GS(M3)  is the gate-source voltage of the MOS transistors MN 83  or MP 83 , and V DS(sat)(M1)  is the drain-source voltage at saturation of the MOS transistors MN 81 /MP 81 , which is defined as a voltage barely enough to operate in the pentode region. 
 
         [0169]     Formula (39) describes a lower limit of the constant voltage source voltage V 1 , and there is also an upper higher limit as well. An excessive increase in the constant voltage source voltage V 1  undesirably results in that the MOS transistors MN 83  and MP 83  enter a triode region, causing a problem that the MOS transistors MN 83  and MP 83  do not carry out desired operation. The condition defining the higher limit of the constant voltage source voltage V 1  is represented by the following formula: 
 
 V   DS(sat)(M 3)   &lt;V   GS(M 1) −( V   1   −V   GS(M 3) )  (40) 
 
 where V GS(M1)  is the gate-source voltage of the MOS transistor MN 81  or MP 81 ; VGS(M 3 ) is the gate-source voltage of the MOS transistor MN 83  or MP 83 ; and V DS(sat)(M3)  is the drain-source voltage at saturation of the MOS transistor MN 83  or MP 83 , which is defined as a voltage barely enough to operate in the pentode region. 
 
         [0170]     The voltage V 1  is required to be configured so as to meet the two requirements defined by formulas (39) and (40). When the voltage V 1  is configured to satisfy these requirements, the voltage drops V (CM)  of the current mirror circuits may be decreased down to approximately 0.2 V. As a result, the input voltages Vin −  and Vin +  of the differential amplifier circuit are allowed to range approximately from the earth level V SS  to the power supply level V DD . In other words, the use of the current mirror circuits shown in  FIG. 8  within the differential amplifier circuit  40  in  FIG. 6  effectively expands the allowable input voltage range.  
         [0171]      FIG. 9  is a circuit diagram illustrating a specific circuit structure in which the current mirrors shown in  FIGS. 8A and 8B  are incorporated as the current mirror circuits CM 61  to CM 64  within the differential amplifier circuit  40  shown in  FIG. 6 ; the current mirror circuits shown in  FIG. 8A  are incorporated as the current mirror circuits CM 61  and CM 62  shown in  FIG. 6 , and the current mirror circuits shown in  FIG. 8B  are incorporated as the current mirror circuits CM 63  and CM 64 . The association of circuit elements within the differential amplifier circuit shown in  FIG. 9  with those within the differential amplifier circuit shown in  FIG. 6  is as follows.  
         [0172]     The first differential transistor pair DF 61  in  FIG. 6  corresponds to a differential transistor pair DF 91  in  FIG. 9 , and the P-channel MOS transistors MP 61  and MP 62  forming the differential transistor pairs correspond to P-channel MOS transistors MP 91  and MP 92 . The second differential transistor pair DF 62  corresponds to a differential transistor pair DF 92 , and the N-channel MOS transistors MN 61  and MN 62  forming the differential transistor pairs correspond to N-channel MOS transistors MN 91  and MN 92 . The constant current sources I 61  and I 62  correspond to constant current sources I 91  and I 92 .  
         [0173]     The first current mirror circuit CM 61  corresponds to N-channel MOS transistors MN 93 , MN 94  and MN  95 , a constant current source I 95 , and a constant voltage source V 91 . The input terminal of the first current mirror circuit CM 61  corresponds to a connection point of the drain of the N-channel MOS transistor MN 94  and the source of the N-channel MOS transistor MN 95 , and the output terminal of the first current mirror circuit CM 61  corresponds to the drain of the N-channel MOS transistor MN 93 . A correspondence with the current mirror circuit in  FIG. 8A  is as follows. The constant current source I 95  and the constant voltage source V 91  correspond to the constant current source I 8   a  and the constant voltage source V 8   a  in  FIG. 8A , respectively. The N-channel MOS transistors MN 94 , MN 93 , and MN 95  correspond to the N-channel MOS transistors MN 81 , MN 82 , and MN 83  in  FIG. 8A , respectively.  
         [0174]     The second current mirror circuit CM 62  corresponds to N-channel MOS transistors MN 96 , MN 97 , and MN 98 , a constant current source I 96 , and the constant voltage source V 91 . The constant voltage source V 91  supplies a bias voltage, and is shared by the first and second current mirror circuits CM 61  and CM 62 . The input terminal of the second current mirror circuit CM 62  corresponds to a connection point of the drain of the N-channel MOS transistor MN 96  and the source of the N-channel MOS transistor MN 98 , and the output terminal corresponds to the drain of the N-channel MOS transistor MN 97 . The current from the third current mirror circuit is inputted through the N-channel MOS transistor MN 98 . A correspondence with the current mirror circuit in  FIG. 8A  is as follows. The constant current source I 96  and the constant voltage source V 91  correspond to the constant current source I 8   a  and the constant voltage source V 8   a , respectively. The N-channel MOS transistors MN 96 , MN 97 , and MN 98  correspond to the N-channel MOS transistors MN 81 , MN 82 , and MN 83 , respectively.  
         [0175]     The third current mirror circuit CM 63  corresponds to P-channel MOS transistors MP 93 , MP 94 , and MP 95 , a constant current source I 93 , and a constant voltage source V 92 . The input terminal corresponds to a connection point of the drain of the P-channel MOS transistor MP 94  and the source of the P-channel MOS transistor MP 95 , and the output terminal corresponds to the drain of the P-channel MOS transistor MP 93 . A correspondence with the current mirror circuit in  FIG. 8B  is as follows. The constant current source I 93  and the constant voltage source V 92  correspond to the constant current source I 8   b  and the constant voltage source V 8   b  in  FIG. 8B , respectively. The P-channel MOS transistors MP 94 , MP 93 , and MP 95  correspond to the P-channel MOS transistors MP 81 , MP 82 , and MP 83  in  FIG. 8B , respectively.  
         [0176]     The fourth current mirror circuit CM 64  corresponds to P-channel MOS transistors MP 96 , MP 97 , and MP 98 , a constant current source I 94 , and the constant voltage source V 92 . The constant voltage source V 92  only supplies the bias, and is shared by the third and fourth current mirror circuits CM 63  and CM 64 . The input terminal of the fourth current mirror circuit CM 64  corresponds to a connection point of the drain of the P-channel MOS transistor MP 96  and the source of the P-channel MOS transistor MP 98 , and the output terminal of the fourth current mirror circuit CM 64  corresponds to the drain of the P-channel MOS transistor MP 97 . The current from the first current mirror circuit is inputted through the P-channel MOS transistor MP 98 ; the current flows from the P-channel MOS transistor MP 98  toward the N-channel MOS transistor MN 93 . A correspondence with the current mirror circuit in  FIG. 8B  is as follows. The constant current source I 94  and the constant voltage source V 92  correspond to the constant current source I 8   b  and the constant voltage source V 8   b  in  FIG. 8B , respectively. The P-channel MOS transistors MP 96 , MP 97 , and MP 98  correspond to the P-channel MOS transistors MP 81 , MP 82 , and MP 83  in  FIG. 8B , respectively.  
         [0177]      FIG. 11  illustrates simulated waveforms of the input voltages, the output signal of the differential amplifier circuit designed as mentioned above, and a resultant output signal developed by the serially-connected CMOS inverters.  
         [0178]     As thus described, the voltage comparator circuit of the present invention is especially suitable for a high-speed differential interface circuit operating on a low power source voltage and exhibiting a wide allowable input voltage range. The use of the circuit according to the present invention makes it possible to realize a voltage comparator circuit that is low in the power consumption, wide in the allowable input voltage range, and is high in a speed, with a fewer number of elements.  
         [0179]     It is apparent that the present invention is not limited to the above-described embodiments, which may be modified and changed without departing from the scope of the invention.