Abstract:
The switching sequence of a phase-shifted zero-voltage-transition (PS-ZVT) full bridge converter circuit is alternated between two modes by periodically reversing the switching sequence for diagonally opposed switching devices of the bridge. Over a period of operation, each of the switching devices periodically conduct the entire free-wheeling current that occurs during load current reversal transitions so as to balance their average power dissipation and reduce the overall power dissipation of the converter circuit.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to phase-shifted zero-voltage-transition converter circuits, and more particularly to a switching sequence control method that balances power dissipation in the switching devices of the converter circuit. 
       BACKGROUND OF THE INVENTION 
       [0002]    Phase-shifted zero-voltage-transition (PS-ZVT) full bridge converter circuits eliminate switching losses and substantially decrease electromagnetic interference (EMI) by utilizing the effects of parasitic capacitance in switching devices such as MOSFETs and IGBTs in conjunction with parasitic and/or additional inductance to ensure that the switching devices each transition to a conductive state when the switched voltage is essentially zero. See, for example, the U.S. Pat. No. 4,864,479 to Steigerwald et al., incorporated by reference herein. 
         [0003]    One example of a prior art full bridge DC-DC transistor converter is shown in  FIG. 1 . The MOSFET transistors Q 1 , Q 2 , Q 3  and Q 4  define the legs of the bridge circuit, and diagonally opposed transistor pairs are alternately gated on and off to establish an AC current in the primary winding T 1  of a center-tapped transformer T using input voltage Vbus. The center-tap of transformer T is grounded, and the secondary windings T 2  and T 3  are coupled to a common node N through diodes D 5  and D 6 . The voltage at node N is filtered by an LC filter comprising the series combination of inductor Lf and capacitor Cf, and the capacitor voltage Vc(t) is applied to a resistive load RL. Each transistor Q 1 , Q 2 , Q 3 , Q 4  is depicted as including a diode D 1 , D 2 , D 3 , D 4  (which may be the transistor body diode) and a parasitic output capacitance C 1 , C 2 , C 3  and C 4 , both connected in parallel with the current-carrying path of the respective transistor. 
         [0004]    Once the diagonally opposed transistors Q 1  and Q 4  are gated on to establish primary winding current in the direction of arrow A, the winding current can be reversed through a resonant transition with zero voltage at transistor turn-on. First, transistor Q 4  is gated off, and the primary winding current free-wheels through transistor Q 1  and the output capacitances C 3  and C 4 , charging capacitance C 4  and discharging capacitance C 3 . Once capacitance C 3  has been discharged, diode D 3  becomes forward biased and continues to carry the free-wheeling current. Also, transistor Q 3  is gated on at the zero-voltage transition, and the free-wheeling current flows through both diode D 3  and the source-to-drain circuit of transistor Q 3 . When transistor Q 1  is gated off, the free-wheeling current charges capacitance C 1  and discharges capacitance C 2 . Once capacitance C 2  is discharged, transistor Q 2  can be gated on with a zero-voltage transition, the primary winding current in the direction of arrow B flows through transistors Q 2  and Q 3 . The next transition occurs when transistor Q 3  is gated off, transistor Q 4  is gated on at zero voltage to share the free-wheeling current with diode D 4 , and transistor Q 1  is gated on at zero voltage to complete the transition. 
         [0005]    One factor to be considered in the design of a PS-ZVT converter is the transistor power dissipation, particularly since the transistors that conduct the entire free-wheeling current (Q 1  and Q 2  in the above example) dissipate more power than the transistors (Q 3  and Q 4 ) that share the free-wheeling current with a free-wheeling diode. In an actual converter circuit based on  FIG. 1 , for example, the average power dissipation of transistors Q 1  and Q 2  is 33 W, while the average power dissipation of transistors Q 3  and Q 4  is 19 W. The imbalance could be even more pronounced in the case of bipolar transistors such as IGBTs because they cannot conduct in reverse to share the free-wheeling current. Since convenience and economy usually dictate the use of identical devices for each bridge transistor, the selected devices must be designed to tolerate the maximum power dissipation, 33 W in this case. It would clearly be more cost effective if identical lower-wattage devices could be used in place of the higher-wattage devices. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention is directed to an improved control method for a PS-ZVT bridge converter that achieves balanced average power dissipation in each of the bridge switching devices and lower overall power dissipation. The switching sequence of the switching devices is alternated between two modes by periodically reversing the switching sequence for diagonally opposed switching devices of the bridge. Over a period of operation, each of the switching devices periodically conduct the entire free-wheeling current that occurs during load current reversal transitions so as to balance their average power dissipation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a circuit diagram of a prior art PS-ZVT DC-DC transistor bridge converter; 
           [0008]      FIGS. 2A and 2B  are two alternate timing diagrams for controlling the switching sequence of the bridge transistors of  FIG. 1 ; and 
           [0009]      FIG. 3  is a block diagram of a logic circuit for carrying out the control of this invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0010]    The timing diagram of  FIG. 2A  graphically illustrates a first switching sequence of bridge transistors Q 1 -Q 4  corresponding to the description of  FIG. 1  set forth above. A full switching cycle occurs over the interval of t 1 -t 5 , with the first current reversal transition occurring in the interval t 1 -t 2 , and the second current reversal transition occurring in the interval t 3 -t 4 . As indicated, the transistors in the left leg of the bridge (Q 1  and Q 2 ) carry the full free-wheeling current during the transition intervals, and transistors in the right leg of the bridge (Q 3  and Q 4 ) share the free-wheeling current with a respective free-wheeling diode D 3  and D 4 . For the exemplary converter application mentioned in respect to  FIG. 1 , the average power dissipation of transistors that carry the full free-wheeling current (Q 1  and Q 2 ) is 33 W, while the average power dissipation of transistors that share the free-wheeling current (Q 3  and Q 4 ) is 19 W. 
         [0011]    The timing diagram of  FIG. 2B  illustrates a second switching sequence that is essentially the reverse of the first switching sequence illustrated by  FIG. 2A . In the second switching sequence, the transistors in the right leg of the bridge (Q 3  and Q 4 ) carry the full free-wheeling current during the transition intervals, and transistors in the left leg of the bridge (Q 1  and Q 2 ) share the free-wheeling current with a respective free-wheeling diode D 1  and D 2 . The operation of the converter circuit is unchanged, but now the average power dissipation of transistors Q 3  and Q 4  is 33 W, while the average power dissipation of transistors Q 1  and Q 2  is 19 W. 
         [0012]    In general, the control method of the present invention reduces the average power dissipation of the converter circuit by alternately driving the bridge transistors Q 1 -Q 4  according to the first and second switching sequences of  FIGS. 2A and 2B . For example, the first switching sequence is used for a predetermined number N 1  of cycles, whereafter the second switching sequence is used for a predetermined number N 2  of cycles, and so on. If N 1 =N 2 , the average power dissipated in each of the transistors Q 1 -Q 4  over an extended period of operation will be the same. Specifically, the average power dissipated in each transistor will be the median or average of the two power dissipation levels ordinarily observed. For the above example, the average power dissipation will now be (19 W+33 W)/2, or 26 W. This means that the transistors Q 1 -Q 4  can be designed to withstand an average power dissipation of 26 W instead of 33 W, a reduction of over 21%. Even with devices of the same capacity, the reduced power dissipation will improve transistor durability and reduce the transistor operating temperature (which in turn, reduces the on-resistance, and therefore the power dissipation). The power dissipation reduction may also permit savings in the converter packaging and heat sink. 
         [0013]    The above-described alternate switching sequence can be implemented with a suitably programmed digital signal processor or microprocessor, or a digital logic circuit, for example.  FIG. 3  depicts a suitable digital logic circuit. 
         [0014]    Referring to  FIG. 3 , the reference numeral  10  generally designates a commercially available PS-ZVT bridge drive controller such as the UC3875 Phase Shift Resonant Controller produced by Texas Instruments, or equivalent. The controller  10  produces four phase-sequenced gate drive signals on lines  12 ,  14 ,  16 ,  18  for the four transistors of a full bridge circuit such as shown in  FIG. 1 . The gate drive signals are identified as UL (for the upper left transistor Q 1 ), LL (for the lower left transistor Q 2 ), UR (for the upper right transistor Q 3 ) and LR (for the lower right transistor Q 4 ). But as demonstrated by the timing diagram of  FIG. 2B , the gate drive signals for the diagonally opposed bridge transistors can be reversed to provide an alternate mode of operation in which the power dissipated by the transistors in the right and left legs of the bridge will be reversed. 
         [0015]    In the illustrated logic circuit, the gate signals UL and LR are applied to the input ports IN 0  and IN 1  of 2:1 multiplexers (MUX)  20  and  22 ; and the gate signals UR and LL are applied to the input ports IN 0  and IN 1  of 2:1 multiplexers (MUX)  24  and  26 . The outputs of MUXs  20  and  22  are coupled to the diagonally opposed bridge transistors Q 1  and Q 4 , respectively; and the outputs of MUXs  24  and  26  are coupled to the diagonally opposed bridge transistors Q 3  and Q 2 , respectively. A first Modulo-N counter  28  clocked by the UL signal on line  12  controls the logic level at the select input (SEL) of MUX  22 ; inverter  30  applies a signal of the opposite logic level to the select input (SEL) of MUX  20 . A second Modulo-N counter  32  clocked by the UR signal on line  16  controls the logic level at the select input (SEL) of MUX  26 ; inverter  34  applies a signal of the opposite logic level to the select input (SEL) of MUX  24 . 
         [0016]    The Modulo-N counters  28  and  32  both count the number of switching cycles of the bridge converter, but with a one-half cycle phase shift. Each counter operates at a 50% duty cycle as illustrated, producing a logic-one output for N switching cycles followed by a logic-zero output for N switching cycles, and so on. In the logic-one case, the gate signals UL, LR, UR and LL control the transistors Q 1 , Q 4 , Q 3  and Q 2 , respectively, to carry out the switching sequence of  FIG. 2A . In the logic-zero case, the gate drive signals LR, UL, LL and UR control the transistors Q 1 , Q 4 , Q 3  and Q 2 , respectively, to carry out the switching sequence of  FIG. 2B . 
         [0017]    In summary, the control of the present invention provides a way of reducing the maximum average power dissipated in the switching devices of a PS-ZVT bridge converter. This allows the use of identical lower-wattage devices in place of higher-wattage devices required for the traditional control, while preserving the high efficiency and low switching loss (and EMI) provided by ZVS circuit topologies. Additional savings may be realized in the thermal interface material of the converter package, and the package size can be reduced as well. 
         [0018]    While the present invention has been described with respect to the illustrated embodiment, it is recognized that numerous modifications and variations in addition to those mentioned herein will occur to those skilled in the art. For example, IGBTs or other switching devices may used in place of the illustrated MOSFETs, the specifics of the logic circuit may be different than shown, and so on. Accordingly, it is intended that the invention not be limited to the disclosed embodiment, but that it have the full scope permitted by the language of the following claims.