Abstract:
A method is provided for manufacturing a semiconductor device with a highly controlled impurity layer without influence from the heat treatment involved in epitaxial growth. The method comprises: forming a dummy gate layer above a semiconductor substrate; forming a spacer layer closely adjacent to each side of the dummy gate layer; selectively forming a silicon layer by epitaxial growth above the semiconductor substrate; forming a gate electrode after removing the dummy gate layer; forming a source/drain region by introducing an impurity into the semiconductor substrate through the silicon layer; and changing the silicon layer into silicide.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by an elevated source/drain technology which forms a silicon layer on a source/drain region by selective epitaxial growth.  
           [0003]    2. Related Art  
           [0004]    In elevated source/drain technology, a single-crystal silicon layer is formed by epitaxial growth on a source/drain region formed in a semiconductor substrate, then a suicide reaction takes place on the silicon layer, and thus forms a silicide layer on the semiconductor substrate. This process enables an impurity layer of the source/drain region to be shallower, and thereby contributes to the miniaturization of elements.  
           [0005]    Referring to the elevated source/drain technology, the technology generally requires heat treatment reaching a temperature of 700° C. or higher in a process forming silicon by epitaxial growth. Consequently, an impurity profile in the source/drain region previously formed by ion implantation is changed, which may make it difficult to suit an impurity profile requested by design specifications.  
           [0006]    In addition, when using a metal gate, performing the above-mentioned heat treatment of 700° C. or higher after forming the metal gate can deteriorate the properties of a gate insulating layer, as a result of a surface reaction between a material of the metal gate and a material of the gate insulating layer.  
           [0007]    An object of the present invention is to provide a method for manufacturing a semiconductor device which can form a highly controlled impurity layer without influence from the above-mentioned heat treatment in the process of epitaxial growth.  
         SUMMARY  
         [0008]    A manufacturing method according to the present invention comprises: forming a dummy gate layer above a semiconductor substrate; forming a spacer layer closely adjacent to each side of the dummy gate layer above the semiconductor substrate; selectively forming a silicon layer by epitaxial growth above the semiconductor substrate; forming a gate electrode after removing the dummy gate layer; forming a source/drain region by introducing an impurity into the semiconductor substrate through the silicon layer; and changing the silicon layer into silicide.  
           [0009]    According to the present invention, after forming the silicon layer by epitaxial growth, the gate electrode is formed, and then the source/drain region is formed. Therefore, an impurity layer can be formed without the effect of high-temperature annealing in the process of epitaxial growth, which restricts the diffusion of an impurity, and thereby enables a shallow impurity layer having an impurity profile along with design specifications to be successfully formed. At the same time, the gate electrode can be formed without any effects of high-temperature annealing in the process of epitaxial growth, which enables to not only polysilicon but also metal such as tantalum to be used as a material of the gate electrode. Thus, the range of materials that can be selected for the gate electrode can be expanded.  
           [0010]    In the present invention, “forming a certain layer above a semiconductor substrate” includes forming a certain layer directly on a semiconductor substrate and forming the certain layer through another layer on the semiconductor substrate. Also in the present invention, “a silicon layer” may include not only a layer made of silicon as a single component but also a layer composed of silicon and another material such as germanium. Moreover, “a source/drain region” means a source region and/or a drain region.  
           [0011]    A manufacturing method according to the present invention is described below in further detail.  
           [0012]    A first aspect according to the present invention may comprise: forming an insulating layer for isolation on a semiconductor substrate; forming a dummy gate layer above the semiconductor substrate; forming a spacer layer closely adjacent to each side of the dummy gate layer above the semiconductor substrate; selectively forming a silicon layer by epitaxial growth above the semiconductor substrate; forming a gate electrode after removing the dummy gate layer; forming an extension region by introducing an impurity into the semiconductor substrate from which the spacer layer is removed by ion implantation after removing the spacer layer; forming an insulating layer for a side wall closely adjacent to each side of the gate electrode; forming a source/drain region by introducing an impurity into the semiconductor substrate through the silicon layer by ion implantation; and changing the silicon layer into silicide.  
           [0013]    In this aspect, after depositing a material different from the dummy gate layer above the semiconductor, the spacer layer may be formed by anisotropic etching.  
           [0014]    A second aspect according to the present invention may comprise: forming an insulating layer for isolation on a semiconductor substrate; forming a groove in a predetermined region after forming an insulating layer above the semiconductor substrate; forming a dummy gate layer above the semiconductor substrate, the dummy gate layer including a lower portion in the groove and an upper portion which is wider than the width of the groove, the upper portion having a side positioned outside of the groove; patterning the insulating layer by using the dummy gate layer as a mask, and forming a spacer layer closely adjacent to each side of the dummy gate layer above the semiconductor substrate; selectively forming a silicon layer by epitaxial growth above the semiconductor substrate; forming a gate electrode after removing the dummy gate layer; forming an extension region by introducing an impurity into the semiconductor substrate from which the spacer layer is removed by ion implantation after removing the spacer layer; forming an insulating layer for a side wall closely adjacent to each side of the gate electrode; forming a source/drain region by introducing an impurity into the semiconductor substrate through the silicon layer by ion implantation; and changing the silicon layer into silicide.  
           [0015]    The first and second aspects may comprise, after forming the silicon layer, forming a stopper layer composed of silicon oxide on the surface of the silicon layer by thermal oxidation. This enables the stopper layer, which protects the silicon layer from etching, to be selectively formed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0017]    [0017]FIG. 2 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0018]    [0018]FIG. 3 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0019]    [0019]FIG. 4 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0020]    [0020]FIG. 5 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0021]    [0021]FIG. 6 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0022]    [0022]FIG. 7 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0023]    [0023]FIG. 8 is a sectional view schematically showing a step of the manufacturing method according to the first embodiment.  
         [0024]    [0024]FIG. 9 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0025]    [0025]FIG. 10 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0026]    [0026]FIG. 11 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0027]    [0027]FIG. 12 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0028]    [0028]FIG. 13 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0029]    [0029]FIG. 14 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0030]    [0030]FIG. 15 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0031]    [0031]FIG. 16 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment.  
         [0032]    [0032]FIG. 17 is a sectional view schematically showing a step of the manufacturing method according to the second embodiment. 
     
    
     DETAILED DESCRIPTION  
       [0033]    Embodiments of the present invention are described below with reference to the drawings.  
         [0034]    First Embodiment  
         [0035]    FIGS.  1  to  8  are sectional views showing a manufacturing method according to the first embodiment.  
         [0036]    (a) As shown in FIG. 1, an insulating layer for isolation  12  is formed in a semiconductor substrate  10  composed of, for example, silicon. The insulating layer for isolation  12  may be formed by a known. The insulating layer for isolation  12  is formed by, for example, a method of shallow trench isolation.  
         [0037]    Next, a silicon oxide layer is formed on the surface of the semiconductor substrate  10  by thermal oxidization. Then a silicon nitride layer is formed on the silicon oxide layer by CVD. Subsequently, a protective layer  14  and a dummy gate layer  16  are formed by patterning the silicon oxide layer and the silicon nitride layer, respectively, through lithography (e.g. lithography utilizing light, an X-ray, or an electron beam) and etching (e.g. reactive ion etching) processes. The width of the protective layer  14  is equivalent to the gate length.  
         [0038]    The protective layer  14  formed in this step has a function to protect the semiconductor substrate  10  in a later step (d) of etching the dummy gate layer  16 . The thickness of the protective layer  14  is set so as to provide this protective function and to be removed as easily as possible. Taking these points into account, the protective layer  14  has a thickness in a range from a few to about ten nanometers. The protective layer  14  can be omitted when it is unnecessary. The thickness of the dummy gate  16  is set in consideration of the plugging capability of an electrode material used in a later step (e) of forming a gate electrode. The dummy gate  16  may have a thickness, for example, in a range from about ten (10) to about one hundred (100) nanometers.  
         [0039]    Next, a spacer layer  18  is formed closely adjacent to each side of the dummy gate layer  16 . The spacer layer  18 , after depositing a silicon oxide layer on the substrate by CVD, is formed by anisotropic etching such as reactive ion etching. Therefore, the spacer layer  18  is composed of a material that is different from the material of the dummy gate  16 , so as to take a sufficiently different selective ratio from the dummy gate layer  16  in the etching process. In this embodiment, the dummy gate layer  16  is composed of silicon nitride, while the spacer layer  18  is composed of silicon oxide.  
         [0040]    (b) As shown in FIG. 2, a silicon layer  20  is selectively formed on the semiconductor substrate  10  by epitaxial growth. The thickness of the silicon layer  20  is determined in consideration of the thickness necessary for a silicide step on the semiconductor substrate  10  and the thickness necessary for thermal oxidation in the next step (c) of forming a silicon oxide layer (a stopper layer). Taking this point into account, the thickness of the silicon layer  20  is set in a range from about fifty (50) to about one hundred (100) nanometers.  
         [0041]    The silicon layer  20  is formed by epitaxial growth. The silicon layer  20  is formed, for example, as shown below. First, the surface of the semiconductor substrate  10  is cleaned by, for example, RCA cleaning. The RCA cleaning includes a step of removing a natural oxide film by light etching with dilute hydrofluoric acid in the last part of its process. Next, the oxide film on the surface of the semiconductor substrate  10  is completely removed by performing heat treatment in a hydrogen atmosphere or in a vacuum. Then, a gas such as SiH x Cl 4-x  (x=0 to 4), Si 2 H 6 , Si 3 H 8 , GeH 4 , H 2 , and Cl 2  is supplied to deposition equipment, while the semiconductor substrate  10  is heated to a temperature of 800° C. or higher. Accordingly, the silicon layer  20  is selectively formed on the exposed portion of the semiconductor substrate  10  by epitaxial growth.  
         [0042]    (c) As shown in FIG. 3, a stopper layer  22  composed of silicon oxide is selectively formed on the surface of the silicon layer  20  by thermal oxidation. The stopper layer  22  has a function to protect the silicon layer  20  in a later step (e) of etching. Taking this function into consideration, the stopper layer  22  has a thickness in a range from about three (3) to about twenty (20) nanometers.  
         [0043]    (d) As shown in FIG. 4, the dummy gate layer  16  composed of silicon nitride is removed by etching with thermal phosphoric acid. In this step, the semiconductor substrate  10  is covered by the protective layer  14  composed of silicon oxide, while the silicon layer  20  is covered by the stopper layer  22  and the spacer layer  18  both composed of silicon oxide. Therefore, both the semiconductor substrate  10  and the silicon layer  20  are free from damage caused by etching with thermal phosphoric acid. Then, the protective layer  14  is removed by light etching with dilute hydrofluoric acid, and thereby the semiconductor substrate  10  is exposed.  
         [0044]    (e) As shown in FIG. 5, a gate insulating layer  24 , a gate electrode  26 , and a cap layer  28  are formed. The gate insulating layer  24  is composed of a high dielectric material such as tantalum oxide, as well as silicon oxide, silicon oxynitride, and silicon nitride. The gate electrode  26  may be composed of polysilicon or metal such as tungsten and tantalum. The cap layer  28  may be composed of silicon oxide or silicon nitride. If the gate electrode  26  is composed of metal such as tantalum, the cap layer is preferably composed of a material with no oxygen such as silicon nitride so as to prevent oxidation of the metal. The cap layer  28  has a function to prevent oxidation of the gate electrode  26  in a step following etching of the gate electrode  26 .  
         [0045]    In this embodiment, since the gate electrode  26  is formed in a groove portion from which the dummy gate layer  16  is removed, the width of the upper portion of the gate electrode  26  is set wider than the width of the groove portion, so that the groove portion can be completely filled in consideration of mask alignment.  
         [0046]    When using tantalum for the gate electrode  26 , the gate insulating layer  24  is a silicon nitride layer, the gate electrode  26  is a multilayered structure of a first tantalum nitride layer, a tantalum layer, and a second tantalum nitride layer, and the cap layer  28  is a silicon nitride layer. In this case, the gate insulating layer  24 , the gate electrode  26 , and the cap layer  28  are formed, for example, by the following process. First, the gate insulating layer is deposited through steps of plasma CVD or high density plasma, atomic layer deposition or sputtering. Next, the gate electrode and the cap layer are formed by patterning with dry etching such as reactive ion etching. The first tantalum nitride layer in the gate electrode  26  functions mainly as a work function control, while the second tantalum nitride layer provides oxidation resistance. Japanese Unexamined Patent Application Publication No. 2001-298193 describes an embodiment of a tantalum gate electrode of such a multilayered structure and is hereby incorporated by reference in its entirety.  
         [0047]    Since the silicon layer  20  is covered by the stopper layer  22  and the spacer layer  18  in this step, the silicon layer  20  is free from damage caused while etching the gate electrode  26 .  
         [0048]    (f) As shown in FIG. 6, the spacer layer  18  composed of silicon oxide is etched by, for example, dilute hydrofluoric acid. At the same time, the stopper layer  22  on the silicon layer  20  is etched. Then, an impurity is introduced into the exposed portion (an area from which the spacer layer  18  is removed) of the semiconductor substrate  10 , by oblique ion implantation, and thereby an extension layer  30  is formed. The extension layer  30  is formed to be shallower than a source/drain region which is to be formed in the next step (g).  
         [0049]    (g) As shown in FIG. 7, an insulating layer for a side wall  32  is formed along with each side of the gate insulating layer  24 , the gate electrode  26 , and the cap layer  28 . The insulating layer for a side wall  32  is formed by anisotropic etching such as reactive ion etching, after forming an insulating layer such as a silicon oxide layer or a silicon nitride layer by CVD over the semiconductor substrate  10 . If the gate electrode  26  is composed of metal such as tantalum, a silicon nitride layer with no oxygen is preferably used so as to prevent oxidation of the metal.  
         [0050]    Next, an impurity is introduced into the semiconductor substrate  10  through the silicon layer  20  by ion implantation (shown as oblique ion implantation in the figure), and thereby a source/drain region  34  is formed. Then, the impurity in the source/drain region is activated by annealing. The temperature of annealing is preferably set so as to restrict thermal diffusion of the impurity and not to harm the gate electrode. In particular, if the gate electrode  26  is composed of metal such as tantalum, low temperature annealing (e.g., 450 to 600° C.) is preferable, because the metal may react to the gate insulating layer under a high temperature of about 700° C. or higher, and thus a gate structure fails to be formed successfully.  
         [0051]    (h) As shown in FIG. 8, a suicide layer  36  is formed on the silicon layer  20 . The silicide layer  36  is formed by the following. Transition metal such as cobalt, nickel, and titanium, is deposited by sputtering. Subsequently, a silicide layer is formed by self-aligning with the silicon layer  20  by annealing. In this silicide process, the temperature of annealing is preferably set so as to restrict thermal diffusion of the impurity and not to harm the gate electrode. Using nickel as the metal enables the silicide process to be carried out at a low temperature of about 500° C. Even if the gate electrode is composed of metal such as tantalum, this process allows the metal to be unharmed, and also restricts thermal diffusion of the impurity layer.  
         [0052]    After this step, an interlayer insulating layer and a wiring layer are formed by conventional processing which completes a semiconductor device.  
         [0053]    Major effects and operation of the manufacturing method according to the present invention are described below.  
         [0054]    In this embodiment, the silicon layer  20  is formed by epitaxial growth in step (b), the gate electrode  26  is formed in step (e) thereafter, and then the extension region  30  and the source/drain region  34  are formed in steps (f) and (g), respectively. Therefore, the extension region  30  and the source/drain region  34  can be formed without being damaged by the high-temperature annealing in step (b). This restricts the diffusion of an impurity, and thereby enables a shallow impurity layer with an impurity profile according to design specifications to be successfully formed. Forming such a shallow impurity layer is critical for the miniaturization of a device.  
         [0055]    At the same time, the gate electrode  26  can be formed free from damage caused by high-temperature annealing in step (b), which enables to not only polysilicon but also metal such as tantalum to be used as a material of the gate electrode. In general, if the gate electrode is composed of metal, the gate electrode reacts to the gate insulating layer (an interface reaction) under a high temperature of about 700° C. or higher, and thus a gate structure fails to be formed successfully.  
         [0056]    Therefore, in this embodiment, an annealing process is performed in the temperature range from about 450 to about 600° C. in steps (g) and (h), for example, after step (b), enabling a shallow impurity layer to be formed and a gate electrode to be a metal layer.  
         [0057]    In this embodiment, the protective layer  22  composed of silicon oxide is selectively formed on the surface of the silicon layer  20  by thermal oxidation in step (c). The protective layer  22  provides enough thickness to function as a stopper in etching the gate electrode, and thus metal whose selective ratio to silicon oxide is small can be used as a material of the gate electrode.  
         [0058]    Second Embodiment  
         [0059]    FIGS.  9  to  17  are sectional views showing a manufacturing method according to the second embodiment. Parts shown in these drawings that are substantially the same as those in FIGS.  1  to  8  (the first embodiment) are marked with the same numbers, and their descriptions are omitted. The second embodiment is different from the first embodiment in terms of forming a dummy gate layer and a spacer layer.  
         [0060]    (a) As shown in FIG. 9, the insulating layer for isolation  12  is formed in the semiconductor substrate  10  composed of, for example, silicon. Next, the silicon oxide layer  13  is formed on the surface of the semiconductor substrate  10  by CVD. Subsequently, a groove portion  13   a  is formed by patterning the silicon oxide layer  13  through lithography and etching methods. The width of the groove portion  13   a  is equivalent to the gate length. Then, a protective layer  14  composed of silicon oxide is formed on the semiconductor substrate  10  by thermal oxidation in the groove portion  13   a . The protective layer  14  has a function to protect the semiconductor substrate  10  in a later step (d) of etching a dummy gate layer. The thickness of the protective layer  14  is the same as described in the first embodiment.  
         [0061]    Next, a first dummy gate layer  16   a  is formed above the semiconductor substrate  10 , filling the groove portion  13   a . The first dummy gate  16   a  is formed by photolithography and anisotropic etching such as reactive ion etching, after depositing a silicon nitride layer on the substrate by CVD. The first dummy gate layer  16   a  has a lower portion in the groove portion  13   a  and an upper portion, which is above the groove portion  13   a , and wider than the width of the groove portion  13   a . Also, each side of the upper portion is positioned a certain distance from the groove portion  13   a.    
         [0062]    Next, as shown in FIG. 10, a second dummy gate layer  16   b  is formed closely adjacent to each side of the first dummy gate layer  16   a  as a side wall. The second dummy gate layer  16   b  is formed by anisotropic etching such as reactive ion etching, after depositing a silicon nitride layer on the substrate by CVD. Accordingly, a dummy gate layer  16  comprising the first dummy gate layer  16   a  and the second dummy gate layer  16   b  as a side wall is formed. The dummy gate layer  16  is formed of a material different from that of the silicon oxide layer  13 , so as to take a selective ratio which is sufficiently different from the silicon oxide layer  13  in the next step of etching. In this embodiment, like in the first embodiment, the dummy gate layer  16  is composed of silicon nitride, and the spacer layer is composed of silicon oxide.  
         [0063]    (b) As shown in FIG. 11, the spacer layer  18  is formed by etching the silicon oxide layer  13 , using the dummy gate layer  16  as a mask.  
         [0064]    Next, the silicon layer  20  is selectively formed on the exposed surface of the semiconductor substrate  10  by epitaxial growth. The thickness of the silicon layer  20  is determined in consideration of the thickness necessary for a silicide process on the semiconductor substrate  10  and the thickness necessary for thermal oxidation in the next step (c) of forming a silicon oxide layer (stopper layer). Taking this point into account, the thickness of the silicon layer  20  can be in a range from about fifty (50) to about one hundred (100) nanometers. The silicon layer  20  is formed in the same way as in the first embodiment.  
         [0065]    Since the following steps (c) to (h) are the same as those in the first embodiment, only major points are described below.  
         [0066]    (c) As shown in FIG. 12, the stopper layer  22  composed of silicon oxide is selectively formed on the surface of the silicon layer  20  by thermal oxidation. The stopper layer  22  has a function to protect the silicon layer  20  in a later step of etching (e).  
         [0067]    (d) As shown in FIG. 13, the dummy gate layer  16  composed of silicon nitride is removed by etching with thermal phosphoric acid. In this step, the semiconductor substrate  10  is covered by the protective layer  14  composed of silicon oxide, while the silicon layer  20  is covered by the stopper layer  22  and the spacer layer  18  both composed of silicon oxide. Therefore, both the semiconductor substrate  10  and the silicon layer  20  are free from damage caused by etching with thermal phosphoric acid.  
         [0068]    Then, the protective layer  14  is removed by light etching with dilute hydrofluoric acid, and thereby the semiconductor substrate  10  is exposed.  
         [0069]    (e) As shown in FIG. 14, the gate insulating layer  24 , the gate electrode  26 , and the cap layer  28  are formed. The gate insulating layer  24 , the gate electrode  26 , and the cap layer  28  may be formed by adopting the same method and materials as in the first embodiment. Also in this step, since the silicon layer  20  is covered by the stopper layer  22  and the spacer layer  18 , the silicon layer  20  is free from damage caused while etching the gate electrode  26 .  
         [0070]    (f) As shown in FIG. 15, like in the first embodiment, the spacer layer  18  composed of silicon oxide is etched by, for example, dilute hydrofluoric acid. Then an impurity is introduced into the exposed portion of the semiconductor substrate  10 , from which the spacer layer  18  is removed, by (e.g., oblique) ion implantation, and thereby an extension layer  30  is formed.  
         [0071]    (g) As shown in FIG. 16, the insulating layer for a side wall  32  is formed at each side of the gate insulating layer  24 , the gate electrode  26 , and the cap layer  28 . The insulating layer for a side wall  32  is formed by adopting the same method and materials in the first embodiment.  
         [0072]    Next, an impurity is introduced into the silicon layer  20  and the semiconductor substrate  10  by ion implantation (shown as oblique ion implantation in the figure), and thereby a source/drain region  34  is formed on the semiconductor substrate  10 . Then, an impurity in the source/drain region is activated by annealing. The temperature of annealing is, like in the first embodiment, preferably set so as to restrict thermal diffusion of the impurity and not to harm the gate electrode. In particular, if the gate electrode  26  is composed of metal such as tantalum, low temperature annealing (about 550° C.) is preferable.  
         [0073]    (h) As shown in FIG. 17, a silicide layer  36  is formed on the silicon layer  20 . The silicide layer  36  is formed by the same method as in the first embodiment. In this silicide process, the temperature of annealing is preferably set so as to restrict thermal diffusion of the impurity and not to harm the gate electrode. Using nickel as the metal enables the silicide process to be carried out at a low temperature of about 500° C. Even if the gate electrode is composed of metal such as tantalum, this process allows the metal to be unharmed, and also restricts thermal diffusion of the impurity layer.  
         [0074]    After this step, an interlayer insulating layer and a wiring layer are formed by conventional processing which completes a semiconductor device.  
         [0075]    In the second embodiment, the dummy gate layer  16  comprises the first dummy gate layer  16   a  and the second dummy gate layer  16   b . Forming the dummy gate layer  16  through two steps enables the patterning of the first dummy gate layer  16   a  as well as the gate electrode  26  and the cap layer  28  by using the same mask. Of course, the dummy gate layer  16  may be formed in one step of patterning.  
         [0076]    The second embodiment produces the same effects and operation as the first embodiment. That is to say, in this embodiment, the silicon layer  20  is formed by epitaxial growth in step (b), the gate electrode  26  is formed in step (e) thereafter, and then the extension region  30  and the source/drain region  34  are formed in steps (f) and (g), respectively. Therefore, the extension region  30  and the source/drain region  34  can be formed without being damaged by the high-temperature annealing in step (b). This restricts the diffusion of an impurity, and thereby enables a shallow impurity layer with an impurity profile according to design specifications to be successfully formed.  
         [0077]    At the same time, the gate electrode  26  can be formed free from damage caused by the high-temperature annealing in step (b), which enables not only polysilicon but also metal such as tantalum to be used as a material of the gate electrode.  
         [0078]    Therefore, in this embodiment, the annealing process is performed at a temperature range from about 450 to about 600° C. after step (b), for example, in steps (g) and (h), so as to form a shallow impurity layer and use metal for the gate electrode.  
         [0079]    In this embodiment, the protective layer  22  composed of silicon oxide is selectively formed on the surface of the silicon layer  20  by thermal oxidation in step (c). The protective layer  22  provides enough thickness to function as a stopper in etching the gate electrode, and thus metal whose selective ratio to silicon oxide is small can be used as a material of the gate electrode.  
         [0080]    The present invention is not limited to the above embodiments, and can be applied to various modes without departing from the spirit of the invention.  
         [0081]    The entire disclosure of Japanese Patent Application No. 2002-292276 filed Oct. 4, 2002 is incorporated by reference.