Abstract:
A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and one of the regenerative sense amplifiers for each of the rows, respectively. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected after redistribution of charge initially stored in the selected storage cell onto the sense-write conductor takes place. The sense voltage resulting from the charge redistributed on the opposite sense-write conductor is subsequently amplified by the sense amplifier, and provided in inverted and noninverted form on the two respective sense-write conductors. A CMOS transmission gate clocked by a first control signal and its logical complement balances the two sense-write conductors to precisely the same voltage. First and second clocked CMOS inverters are cross-coupled to form a label with its output nodes each coupled, respectively, to one of a pair of the sense-write conductors. The clocking of the latch circuit is performed by a second clock signal and its logical complement delayed somewhat from the first clock signal and its logical complement to effectively electrically isolate the pair of sense-write conductors during the balancing and sensing charge redistribution operations.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to read-write circuitry for semiconductor memories. 
     2. Description of the Prior Art 
     Single transistor storage cells have been recently utilized to implement random access memories. The single transistor storage cells usually include a MOSFET having its gate connected to a selection conductor, its drain connected to a sense-write conductor and its source connected to a storage node. The storage cell also includes a storage capacitor connected between the storage node and a common voltage supply conductor. In order to achieve a large number of storage cells in a small amount of semiconductor chip area it is desirable that the storage capacitor be very small. A plurality of such storage cells are connected to a single sense-write conductor and thereby comprise one row of many rows forming a rectangular array of storage cells. Consequently, the capacitance associated with the sense-write conductor is very large compared to that of the storage capacitor of each storage cell. Sensing is accomplished by selection of the storage cell by turning on the MOSFET, and causing the charge stored on the storage capacitor of the selected storage cell to be redistributed to the capacitance of the sense-write conductor, resulting in a relatively small voltage transition of the sense-write conductor. Consequently, sensitive sense amplifiers have been developed which are capable of sensing and amplifying such small voltage transitions. Read-write circuitry is normally coupled directly to the sense-write conductors. However, such read-write circuitry increases the capacitance of the sense-write conductor even more, and reduces the size of the voltage transition achieved by selecting a storage cell. Heretofore, the solution has been to increase the size of the storage capacitor of each storage cell, thereby increasing the size and cost of the semiconductor memory or by increasing the sensitivity of the sense amplifier, which normally involves more complex, more area consuming, and consequently, more expensive sense amplifier circuitry, which in turn increases the cost of the memory product. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide a semiconductor memory system wherein complementary CMOS sense amplifier circuitry is coupled to a pair of sense-write conductors, and a complementary transmission gate clocked by a first signal and its complement is used to balance the pair of sense-write conductors, and coupling circuitry clocked by a second signal and its complement is used to electrically isolate the two sense-write conductors during the balancing and sensing charge redistribution operations. 
     Briefly described, the invention is a semiconductor memory having a plurality of storage cells and a sense-write conductors coupled to a plurality of the storage cells. A complementary sense amplifier circuit is coupled to one of the sense-write conductors. A dummy storage cell having a storage node is also coupled to the sense-write conductor. The complementary sense amplifier circuit coupled to the sense-write conductor acts to amplify a sense signal imparted to the sense-write conductor by a selected storage cell and also acts to isolate the sense-write conductor so that it is electrically floating at times other than during a read operation or a write operation. In one embodiment the complementary sense-amplifier is also coupled to a second sense-write conductor, and includes balancing circuitry including a complementary field effect transistor transmission gate responsive to a first clock signal for balance both sense-write conductors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a complementary field-effect transistor amplifier according to the invention. 
     FIG. 2 is a partial schematic diagram of a semiconductor memory chip in accordance with the invention. 
     FIG. 3 is a schematic diagram of a complementary field effect transistor inverter. 
    
    
     DESCRIPTION OF THE INVENTION 
     Referring first to FIG. 2, it is seen that semiconductor memory chip 10 includes a left hand array 12 of one transistor memory storage cells including storage cells 19 and 24 connected to sense-write conductor 28 and storage cells 22 and 26 coupled to sense-write conductor 30. The dotted lines indicate expansion of the number of rows and columns of identical storage cells. Memory chip 10 also includes a right hand array 14 including a plurality of identical storage cells such as 49 connected to sense-write conductor 50 and a plurality of one transistor storage cells connected to sense-write conductor 53. 
     Again, the dotted lines indicate expansion of rows and columns of storage cells. The construction of the one transistor memory cell is described with reference to memory cell 19, which includes MOSFET 20 and storage capacitor 32. MOSFET 20 has its drain connected to sense-write conductor 28 and its source connected to a storage node 19&#39; and its gate connected to column selection conductor 65. Storage capacitor 32 has one electrode connected to the source of MOSFET 20 and its other electrode connected to common voltage conductor 34. 
     It is seen that all of the storage cells in arrays 12 and 14 are arranged in rows and columns, and that in each array all of the storage cells in a given row have the drain of their respective MOSFETs connected to the same sense-write conductor. It is also seen that the gate of each MOSFET in a given column is connected to the same column selection conductor, such as column selection conductors 65, 66, 68 or 69. 
     Semiconductor memory chip 10 also includes two columns of dummy storage cells. Column 16 includes dummy storage cells 36 and 36&#39;, while column 18 includes dummy storage cells 48 and 48&#34;. There is one dummy storage cell for each row of storage cells in each of arrays 12 and 14. 
     Each of the dummy storage cells, including dummy storage cell 36, is schematically the same as the storage cells in arrays 12 and 14. For example, dummy storage cell 36 includes MOSFET 38 having its drain connected to sense-write conductor 28, its gate connected to dummy storage cell selection conductor 60, and its source connected to storage node 40&#39; and to one electrode of storage capacitor 40 and the other electrode of which is connected to common voltage conductor 34. The dummy storage cell in each row of each array is connected to the sense-write conductor, such as 28, 30, 50 or 53 of that particular row of the respective array. 
     Each of the column selection conductors such as 65 and 66 in array 12 is driven by column decode circuitry 64. The structure of the circuitry included in column decode circuitry 64 is readily implementable using techniques similar to ones known to those skilled in the art, and typically includes decode gates and address inverters. For example, see U.S. Pat. No. 3,760,380 assigned to the present assignee, by Hoffman et al. 
     The inputs to the address inverters are the address inputs 91, 94, to MOS memory chip 10. Similarly, the column selection conductor such as 68 and 69 of right hand array 14 are connected to column decode circuitry 67, which is similar to the circuitry of column decode circuitry 64, except that different address inputs are connected thereto. 
     A sense amplifier, such as 45, is connected between the sense-write conductors of each array for each row in the memory. Sense-amplifier 45 is connected between sense-write conductor 28 and sense-write conductor 50. Similarly, sense amplifier 52 is connected between sense-write conductors 30 and 53. Incidentally, the dotted extension of the sense-write conductors and the column selection conductors in FIG. 2 indicate that the memory array and the decode section are expandable in both the horizontal and vertical directions. 
     Associated with each row of storage cells and the respective sense amplifier is an input-output control circuit such as 44&#39; or 55&#39;. Input-output control circuit 44&#39; includes MOSFET 44, which has its gate electrode connected to conductor 43&#39; and its drain connected to sense-write conductor 50. MOSFET 44 has its source connected to data conductor 51. Input-output control circuit 44&#39; also includes MOSFET 43 having its gate connected to conductor 43&#39;, its drain connected to sense-write conductor 28, and its source connected to data conductor 51. The other input-output control circuits, one associated with each row of the memory storage cells, are constructed entirely similarly. The source electrodes of all of the MOSFETs, such as 43, 44, 55, 56 are connected to the common data conductor 51. The gate electrodes of such MOSFETs are respectively coupled to row decode means 46 and 47 which in a practical implementation are split from each other so that half of the row decode circuitry is situated to the right side of sense amplifiers 45 and the other half is located to the left thereof. 
     The circuitry in row decode circuits 46 and 47 is also readily implementable by those skilled in the art and may be quite similar in structure to that in column decode circuitry 64 and 67. Control circuitry 57 is coupled to row decode circuitry 46 and 47, dummy storage cell decode circuitry 61 and 62, and column decode circuitry 64 and 67. Data input terminal 58 and data output terminal 59 are also connected to control circuitry 57, as is data conductor 51. Control circuitry 57 is intended to represent generalized timing, clocking, and input-output circuitry readily implementable by those skilled in the art of semiconductor memory design. See the above mentioned patent by Hoffman et al. 
     Column address inputs 91 are coupled to column decode circuit 64 and column address inputs 94 coupled to column decode circuit 67. There are M column address inputs where 2 M  is the number of columns of storage cells in memory chip 10. Row address inputs 95 are coupled to row decode circuitry 46 and/or 47. There are N row address inputs if there are 2 N  rows of storage cells in memory chip 10. 
     It should be pointed out that the structure and operation of MOSFETs is well known to those skilled in the semiconductor art. However, for a more detailed description of MOSFETs the reader may refer to Physics and Technology of Semiconductor Devices by A. S. Grove, John Wiley and Sons, Inc., 1967. It should be noted that as used herein the terms &#34;source&#34; and &#34;drain&#34; used with reference to the connections of MOSFETs, are interchangeable, since these electrodes of a MOSFET function as either sources or drains, depending upon bias conditions, since a MOSFET is a bilateral device as far as switching applications are concerned. It should also be pointed out that the acronym MOSFET is widely used to include all IGFET (insulated gate field effect transistors), including silicon gate field effect transistors. The same remark applies to the acronym CMOS. 
     The operation of memroy chip 10, as it relates to the inventive concept herein, is described with reference to the FIG. 2. 
     Any particular combination of the row selection and column selection address inputs results in the selection of one and only one storage cell, which may be in either array 12 or array 14. In other words, one column is selected and one row is selected; this results in selection of the storage cell at the intersection thereof. 
     Assume for purposes of discussion, that a logical &#34;1&#34; is stored at storage node 19&#39; of storage cell 19. Storage cell 19 is selected by applying a logical &#34;1&#34; to column selection conductor 65 by means of column decode circuit 64. This accomplishes selection of the desired column. Prior to column selection, however, sense-write conductors 28 and 50 have been equilized in potential. This may be accomplished by means of complementary MOS transistor precharge circuitry, which may be associated with sense amplifier 45 or separate therefrom. When MOSFET 20 of storage cell 19 is turned on, the charge stored on storage capacitor 32 will be redistributed with charge stored on the capacitance of sense-write conductor 28, causing a sense voltage to appear on sense-write conductor 28. Also, some charge will be coupled between column selection conductors 65 and sense-write conductor 28 by parasitic capacitance between the gate and drain of MOSFET 20. 
     The operation of the memory circuit is such that whenever any column in array 12 is selected, dummy storage cell decode circuit 62 causes dummy storage cell selection conductor 63 to turn on all of the dummy storage cells connected thereto, so that the gate-to-drain parasitic capacitance associated with MOSFET 48&#39; couples the same amount of charge onto sense-write conductor 50 as the gate-to-drain capacitance of MOSFET 20 couples onto sense-write conductor 28. Therefore, after all of the charge initially stored on storage capacitor 32 and the parasitic capacitance of sense-write conductor 28, is redistributed on storage capacitor 32, the voltage difference, (or lack of a voltage difference) between sense-write conductors 28 and 50 is due solely to the amount of charge representative of the stored logic state, initially stored on storage capacitor 32 of the selected storage cell 19. 
     Sense amplifier 45 is designed to be sensitive enough to detect this voltage difference as being indicative of an initially stored logical &#34;1&#34; or logical &#34;0&#34; in storage cell 19. Typically, the voltage difference for a stored logical &#34;1&#34; may be about 200 millivolts for the present state of the art, even though initially a voltage of the order of 15 or more volts different from the equalization voltage of the sense-write conductors was initially stored on the storage capacitance. This is because the capacitance of the storage capacitor, such as capacitor 32, is far smaller than the parasitic capacitance associated with the sense-write conductors. 
     Those skilled in the art will recognize that sense amplifier 45 is typically controlled by a read/write input to RAM 10, although such input is not discussed herein. 
     In order to increase the size of the voltage transition of a sense-write conductor corresponding to a stored logical state of the selected storage cell, it is very desirable that the circuitry coupled to the sense-write conductors to accomplish read and write operations add as little capacitance as possible. As explained in more detail hereinafter sense amplifier 45 acts to sense the small voltage transition and may regeneratively amplify it so that a large logical &#34;1&#34; or logical &#34;0&#34; voltage appears on sense-write conductor 50. Then, during the following portion of a read operation, the amplified voltage on sense-write conductor 50 is transferred or coupled to data conductor 51, which is then amplified and gated, by input or output circuitry associated with control circuitry 57, to data output terminal 59. 
     Row selection, as mentioned above is accomplished by means of a voltage applied to, for example, conductor 43&#39; by row decode circuitry 46, thereby turning on MOSFET 44. During a writing operation, input data applied to data input terminal 58 is gated by circuitry in section 57 to data conductor 51 and is then coupled to the sense-write conductor 50 and is coupled to sense amplifier 45, overriding whatever state is stored therein, and from there is coupled to the opposite sense-write conductor and through MOSFET 20 to storage node 32 of selected storage cell 19. 
     Referring now to FIG. 1, sense amplifier 45&#39; is included in previously described sense amplifier 45 of FIG. 2. Sense amplifier 45&#39; includes balancing or equalizing circuitry including P channel MOSFET 110 and N channel MOSFET 114 coupled in parallel between sense-write conductors 28 and 50. The gate of MOSFET 110 is connected to conductor 113, which has a clock signal designated C applied thereto. The gate of MOSFET 114 is connected to conductor 112, which has clock signal designated C applied thereto. The signals applied to conductors 113 and 112 can be generated externally or internally to semiconductor random access memory 10, or may be generated by a circuit such as 45A in FIG. 3 which is merely a conventional complementary field effect transistor inverter having the clock signal C applied to its input in generating complementary clock signal C at its output. 
     Sense amplifier circuit 45&#39; also includes complementary isolation circuitry including P channel MOSFETs 115, 116 and N channel MOSFETs 122 and 124. MOSFET 115 has its drain connected to sense-write conductor 50, its gate connected to clock conductor 112&#39; and its source connected to node 121. MOSFET 116 has its drain connected to sense-write conductor 28, its gate connected to clock conductor 112&#39;, and its source connected to node 119. MOSFET 122 has its drain connected to sense-write conductor 50, its gate connected to complementary clock conductor 113&#39;, and its source connected to node 128. MOSFET 124 has its drain connected to sense-write conductor 28, its gate connected to complementary clock conductor 113&#39;, and its source connected to node 126. The signals C&#39; and C&#39; applied to conductors 113 and 113&#39; are delayed from C and C so that sense-write conductors 28 and 50 are electrically floating or isolated during the sensing charge redistribution operation described above. 
     Sense amplifier circuitry 45&#39; also includes cross-coupled regenerative circuitry including P channel MOSFETS 118 and 120 and N channel MOSFETs 130 and 132. MOSFET 118 has its drain connected to node 119, its gate connected to sense-write conductor 50, and its source connected to V DD  conductor 34&#39;. MOSFET 120 has its drain connected to node 121, its gate connected to sense-write conductor 28, and its source connected to V DD . MOSFET 130 has its source connected to node 126, its gate connected to sense-write conductor 50, and its source connected to V SS  common voltage conductor 34. MOSFET 132 has its source connected to node 128, its gate connected to sense-write conductor 28, and its source connected to V SS . 
     The operation of complementary sense amplifiers 45&#39; is described as follows. Assume that sense-write conductors 28 and 50 are both precharged to approximately the same voltage by precharging circuitry (not shown) in sense amplifier circuitry 45 of FIG. 2. Also assume that this voltage is approximately midway between V DD  and V SS . The first thing that happens is that clock signal C is set to a logical &#34;1&#34;, which would be approximately V DD  volts, and C is set to a logical &#34;0&#34;, or V SS  volts. MOSFETs 110 and 114 are then both turned on, causing sense-write conductors 28 and 50 to be established at precisely the same voltage, since they will be electrically floating or isolated, and the charge associated with the capacitance thereof will be equally distributed between the two conductors. During this time P channel MOSFETs 115 and 116 and N channel MOSFETs 122 and 124 are off, completely isolating both sense-write conductors 28 and 50 from V DD  and V SS . Then, after the balancing operation is complete the next thing that happens is that a storage cell is selected. For purposes of explanation, assume that storage cell 19 is selected, and that a logical &#34;1&#34;, i.e., V DD  volts, is stored on storage capacitor 32. Then column selection conductor 65 goes to a logical &#34;1&#34; turning on N channel MOSFET 20. The charge stored on capacitor 32 is then redistributed to the capacitance 30&#39; associated with sense-write conductor 28. The result is a small increase in voltage on sense-write conductor 28, since the capacitance of capacitor 30&#39; is typically much greater than that of storage capacitor 32. As a result of this operation, the voltage of sense-write conductor 28 is typically 200 millivolts greater than the potential of sense-write conductor 50. 
     The next thing that happens is that clock signal C goes from V DD  to V SS  volts, turning off MOSFETs 110 and 114, thereby isolating sense-write conductors 28 and 50 from each other, leaving them electrically floating. 
     Then clock signal C&#39; goes from a logical &#34;1&#34; to a logical &#34;0&#34; and C&#39; goes from a logical &#34;0&#34; to a logical &#34;1&#34;. Thus, MOSFETs 115, 116, 122, and 124 are all turned on, so that the two branches of the sense amplifier 45&#39; are effectively cross-coupled, with node 28 being approximately 200 millivolts higher in voltage than node 50. If all of the field effect transistor geometries are symmetrically chosen for sense amplifier 45&#39;, the 200 millivolt difference is enough to cause the circuit to regeneratively and rapidly switch to a state in which sense-write conductor 28 is at V DD  volts, and sense-write conductor 50 is at V SS  volts. This re-establishes a potential of V SS  volts on capacitor 32, thereby refreshing the stored state which was destructively read out. Column selection conductor 65 is then returned to a logical &#34;0&#34;, and the sensing operation and refreshing operation is complete. 
     Provision of the complementary sense amplifier, as described above, substantially in the center of semiconductor chip 10 also provides chip layout, or topology, advantages in that a single elongated &#34;tub&#34; region, for example, an N-tub region, may be provided in the center of the chip, wherein all of the P channel IGFETs in the plurality of sense amplifiers 45, 52, etc., may be fabricated. Interconnection with the N channel IGFETs is thereby facilitated by means of relatively simple metallization interconnections. 
     In summary, the invention provides complementary field effect transistor sense amplifiers for a random access memory, which sense amplifiers are far more sensitive to small sense voltage transitions on the bit sense conductors than sense amplifiers of the prior art. Such sense amplifiers, according to the invention, dissipate no DC power, and consequently dissipate far less overall power than known sense amplifiers of the prior art.