Abstract:
A polishing slurry for the chemical-mechanical polishing (CMP) process used in the integrated circuit manufacture process is disclosed. The slurry of the present invention may comprise colloid silica (SiO2) as abrasive particles, and a corrosion inhibitor (e.g., benzotriazole (BTA)). The slurry does not require any oxidizing agent. The slurry may be used as a barrier slurry in copper CMP processes; and it has a similar polishing rate for copper, barrier, and dielectric materials on patterned wafers. The slurry of the present invention also reduces CMP defectivity on polished wafers.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates in general to the field of chemical-mechanical polishing (CMP) processes used in the semiconductor integrated circuit manufacturing, and more particularly, to compositions and methods of slurries used in, e.g., copper CMP.  
         BACKGROUND OF THE INVENTION  
         [0002]    Without limiting the scope of the invention, its background is described in connection with chemical-mechanical polishing and polishing slurry, as an example.  
           [0003]    Developments in semiconductor technology have led to the fabrication of integrated circuit (IC) wafers with circuits having multiple levels of interconnections. In order to reduce RC delay caused by interconnect, a variety of new materials have been introduced into the IC manufacturing process. For example, copper is used to replace aluminum due to its lower resistance and better electromigration resistance. Low dielectric constant materials (low k), such as fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), organosilicate glass (OSG), Black Diamond™, SiLK™ are used to reduce the capacitance coupling among wires. Due to the difficulty of etching copper in a plasma etch chamber, a damascene process is typically used to create copper wiring.  
           [0004]    In the damascene process, openings in a dielectric layer are formed through patterning and etching process. In a single damascene structure, the openings are trench or via, and in a dual damascene structure, the openings are trench and via together. The openings are then coated with a barrier layer, such as Ta or TaN, to prevent copper diffusion and to improve adhesion, followed by formation of the copper seed layer. The openings are then filled with copper through, e.g., an electroplating process. The chemical mechanical polishing (CMP) process is used to remove excess portions of copper and to planarize the surface.  
           [0005]    In a CMP process, material removal is achieved through the interaction between polishing pad, polishing slurry and wafer. The polishing slurry is a critical part of the polishing system. To a large extent, it determines the polishing performance. A copper CMP process is typically a multi-step process. In the first step, a slurry with a high polishing rate for copper and low polishing rate for the barrier is used to remove a majority or all of the redundant copper from the wafer surface. The high selectivity of copper removal rate to barrier removal rate is designed so the polish stops at the barrier layer. Hence, the non-uniformity from electro-chemical plating will not be transferred into the final copper thickness variation. In the second step of the CMP process, the barrier layer is removed to completely cut off un-designed connections among wires in the layer. The slurry used in the barrier removal step is called barrier slurry and is typically different from that used in the first step.  
           [0006]    There are currently two types of barrier slurry, the high-selectivity slurry (HSS) and the low-selectivity slurry (LSS). The HSS slurry has a higher removal rate for the barrier than that for the copper and dielectric layer. The LSS slurry polishes copper, dielectric material, and barrier layer at similar rate. Sometimes, a third step, called the buff step is used to improve defectivity.  
           [0007]    Typically, copper CMP barrier slurries contain abrasive material (such as silica or alumina), a corrosion inhibitor (such as benzotriazole (BTA)), an oxidizer (such as hydrogen peroxide, potassium iodate), and one or more of a long list of additives including surfactant, stabilizer, complexing agent, biocides, et al. The various chemicals and abrasive particles are used to balance the polishing and passivation reactions at the wafer/pad interface to achieve desired selectivity and lower defectivity.  
         SUMMARY OF THE INVENTION  
         [0008]    It has been found, however, that present barrier slurry used in copper CMP process has disadvantages. One problem encountered with current slurries used in the industry is polishing induced defects. Scratching from the CMP process is a major source of defects, and copper is more susceptible to CMP scratches due to its material characteristics. Because of its susceptibility to sheering, most barrier slurry with fuimed silica is difficult to handle (pump and filter) in a manufacturing environment. Large undesirable particles (agglomerate) are considered to be the major sources of defectivity.  
           [0009]    Another problem encountered with current barrier slurry is the selectivity. For low selectivity slurry (LSS), it is desirable that the polishing rate for copper, barrier and dielectric material is similar. In order to achieve such polish rate parity, it is a current common practice to add an oxidizing agent to the slurry to increase the copper removal rate. In order to maintain the polishing rate for copper and to reduce the decay of oxidizer, some stabilizing agent is typically also added to the slurry.  
           [0010]    However, it has been recognized in the current invention that the addition of oxidizer, even in the presence of stabilizer, can cause polish rate instability and limited slurry pot life. It has also been recognized that the oxidizer will chemically attack copper, causing undesirable copper corrosion. It has further been recognized that the polish rate parity among copper, barrier, and dielectrics achieved on pilot wafers may not be realized on patterned wafers.  
           [0011]    Therefore, what is needed in copper CMP is a barrier slurry that provides lower defectivity and desired selectivity for the patterned wafers. In one embodiment of the present invention, the fumed silica abrasive material is replaced with colloid silica in the barrier slurry. In another embodiment of the present invention, the oxidizer is removed from barrier slurry and the desired selectivity on patterned wafers is achieved through the control of mix ratio between the abrasive particle (colloid silica) and corrosion inhibitor (BTA).  
           [0012]    One advantage of an embodiment of the polishing slurry of the current invention is the lower defectivity. The use of colloid silica allows more aggressive filtration at the slurry re-circulation loop and point of use (POU). A second advantage of the slurry of to the present invention is a reduction in the undesirable attack of copper by the barrier slurry. Two more advantages of the present invention are the ability to achieve desired selectivity on the patterned wafers and the significant improvement of pot life. Yet another advantage of the present invention is a reduction of cost associated with manufacture and delivery of the barrier slurry.  
           [0013]    More specifically, the present invention provides a polishing slurry comprising a dispersing medium, a colloidal silicon suspended in the dispersing medium, and a corrosion inhibitor in the polishing slurry medium.  
           [0014]    The present invention also provides a method of polishing a damascene structure using a chemical-mechanical polishing (CMP) apparatus. A damascene structure is provided, as well as a polishing pad. A polishing slurry is applied to the interface between the damascene structure and the polishing pad. Polishing is then performed using polishing parameters of the CMP apparatus, removing at least a portion of the metal layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures in which corresponding numerals in the different figures refer to corresponding parts and in which:  
         [0016]    [0016]FIG. 1 is a diagram illustrative of a cross-section of a damascene structure before a copper CMP process;  
         [0017]    [0017]FIG. 2 is diagram illustrative of a cross-section of a damascene structure after first step of copper CMP, polish stops on barrier;  
         [0018]    [0018]FIG. 3 is diagram illustrative of a cross-section of a damascene structure after barrier removal; and  
         [0019]    [0019]FIG. 4 is a graph that shows the removal rate and its dependence on varying concentrations of the compositions according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]    While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts that may be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention.  
         [0021]    For the sake of simplicity, in FIG. 1, a single damascene trench structure is illustrated. The situation for single damascene of via, or dual damascene, where trench and via are formed together is similar. FIG. 1 is a cross sectional view of a wafer  10  depicting a conventional single damascene structure for trench. The damascene structure was built on the top of the inter-level dielectric layer (ILD)  11 . The intra-metal dielectric layer (IMD)  14  is depicted on the top of the ILD layer  11 . Patterning and etching are performed to create trench  16 . A barrier layer  18  is deposited, as a way to improve the adhesion between the metal layer  12  and the dielectric layer  14 . The barrier layer  18  also acts as a diffusion barrier is for the metal layer  12 . The wafer  10  is coated with a thin conductive layer of copper, called a seed layer, and immersed in a solution containing cupric ions for electroplating. The plated metal layer  12  covers the entire wafer surface  10 , and fills the trench  16 .  
         [0022]    A CMP process is then used to remove the excess portions of copper and planarize the surface. A copper CMP process is typically a multi-step process. In the first step, a slurry of high selectivity of copper to barrier is used to removal majority or all redundant copper from the wafer surface. The high selectivity of copper removal rate to barrier removal rate is designed so the polish can stop at the barrier layer. Hence, the non-uniformity form electro-chemical deposition will not be transferred into the final copper thickness variation.  
         [0023]    [0023]FIG. 2 is a cross-sectional view of a damascene structure after the first step of a typical copper CMP process. Typically, after the removal of the excess copper of copper layer  12 , some of the copper layer disposed inside the trench is also removed due to bending of the polishing pad. The undesirable thinning of the copper inside trench, known as “dishing” is shown as dishing  20 . In the second step of the CMP process the barrier layer is removed to completely cut off un-designed or unintended connections among wires in the layer. The slurry used in the barrier removal step is called a barrier slurry, which is typically different from that used in the first step. There are currently two types of barrier slurry, the high-selectivity slurry (HSS), and the low-selectivity slurry (LSS). The HSS slurry has a higher removal rate for the barrier than that for the copper and dielectric layer. The LSS slurry polishes copper, dielectric material and barrier layer at similar rate. The low selectivity slurry polishes off some copper residue left from previous step, providing a relatively wider process margin. It also planarizes the surface, reducing the dishing at the cost of dielectric material removal.  
         [0024]    [0024]FIG. 3 is diagram illustrative of a cross-section of a damascene structure after the barrier removal with LSS approach. The thinning of dielectric layer  14  and reduction of dishing  20  are illustrated. The slurry used for barrier polish in the copper CMP process needs to provide lower defectivity and designed selectivity on the patterned wafers. The present invention provides such a low defectivity slurry. In the current invention, a colloidal silica is used to provide abrasive particles, in place of fumed silica typically used in the slurry. The use of colloid silica enables the aggressive filtration at the slurry re-circulation loop and point-of-use (POU) with less risk of shearing.  
         [0025]    In the prior art, an oxidizer is typically added to the barrier slurry to increase the polishing rate for copper, and to achieve desired selectivity. One problem with the prior art is that oxidizer will decay over time, causing a reduction of the copper polish rate over time. This will impose a limited pot life on the mixed slurry. Another problem with the prior art is that oxidizer attacks the copper thereby causes undesirable copper corrosion. The third problem with the prior art is that the test for slurry polishing rate was typically performed on pilot wafers (blank wafers without any pattern).  
         [0026]    The present invention recognizes that the removal rate on pilot wafers is not necessary equal to that on the patterned wafers. It is possible for a barrier slurry to achieve desired selectivity on patterned wafers without the addition of oxidizer.  
         [0027]    In one embodiment of the present invention, a barrier slurry is achieved through on-platen mix of abrasive component of colloid silica slurry (e.g., Rodel CUS1201A, 30% solids) and BTA component (e.g., 330 ppm by weight) with different mix ratio. The mix ratio is, in one exemplary case, of 150 ml/min of abrasive component, and 50 ml/min of BTA component, in another exemplary case, of 100 ml/min of abrasive component, and 100 ml/min of BTA component, and in a third exemplary case, of 50 ml/min of abrasive component, and 150 ml/min of BTA component. The rate on pilot wafer is obtained by measuring the thickness difference before and after polish. The method to obtain the polish rate on patterned wafers is illustrated in FIG. 4.  
         [0028]    To obtain the polish rate on patterned wafers, a series of patterned wafers may be polished by the primary slurry (e.g., Cabot Microelectronics iCue™ 5001), and stopped by the optical end point signal, which indicates that the copper is cleared. The wafers may then be polished with the designed barrier slurry with different polish times (e.g., 0.25 min (15 sec), 0.5 min (30 sec), 0.75 min (45 sec), and 1 min (60 sec)). The resulting thickness is measured and plotted against the polish time, as illustrated for exemplary process in FIG. 4. In FIG. 4, the horizontal axis is the polishing time in the unit of minute, and the vertical axis is the post thickness in the unit of angstrom. The slope of the plot represents the removal rate on a patterned wafer, in the unit of angstroms/minute.  
         [0029]    In another embodiment of the present invention, a barrier slurry is pre mixed from abrasive component of colloid silica slurry (e.g., Rodel CUS1201A, 30% solids) and BTA component. The pre mixed slurry has, for example, 15% of solids, but different BTA concentration (e.g., 200 ppm, 800 ppm, and 1000 ppm, all by weight).  
         [0030]    While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.