Abstract:
A fiber optic transceiver or receiver having circuitry for detecting signal strength of a photo-diode therein is disclosed. In one embodiment, the photo-current generated by the photo-diode is provided to a pre-amplifier circuit. The pre-amplifier circuit generates differential signals including a first signal and a second signal whose difference is representative of the detected photo-current. The fiber optic receiver further includes a post-amplifier circuit that is coupled to the pre-amplifier circuit to receive the differential signals. In one embodiment, the post-amplifier circuit includes circuitry to accurately derive a signal strength of the photo-current from the differential signals.

Description:
The present application claims priority to, under 35 U.S.C. 119(e), United States Provisional Patent Application bearing serial No. 60/357,608, filed Feb. 14, 2002, which is incorporated herein by reference. 

   BRIEF DESCRIPTION OF THE INVENTION 
   The present invention relates generally to signal detectors, and particularly to optical signal strength detectors. 
   BACKGROUND OF THE INVENTION 
   It is useful to measure the received optical power in fiber optic links in order to determine the integrity of the signal path and terminal devices. The photo-current in the photo-diode is proportional to the received power. Hence, one way of measuring received optical power is to measure the photo-current level. 
   Typical optoelectronic receivers utilize a photo-detector which is integrated in the same TO (Transistor Outline) package as the pre-amplifier. Most TO packages have only four pins. Two of the pins are connected to receive a differential signal from the pre-amplifier, one of the pins receives a power supply voltage, and one of the pins is for ground. Since all four pins of the TO packages each have a defined function, there is no separate lead available to output the photo-current. A fifth pin would not be an ideal solution because space is at a premium in TO packages. 
   Several prior art signal detectors measure the photo-current level without the use of a fifth pin. At low signal amplitudes (e.g., at 0.5 mV or less), however, these signal detectors exhibit a significant loss of gain—and thus accuracy. This loss of gain at low signal amplitudes is caused by a breakdown of the switch-like behavior of these signal detectors. 
   SUMMARY OF THE INVENTION 
   The present invention provides a more accurate method and apparatus for measuring the photo-current of a photo-diode in a fiber optic receiver or transceiver. In particular, the photo-current level is derived from the differential output of a pre-amplifier circuit. 
   An aspect of the present invention includes a voltage difference detector circuit that comprises first, second, third, fourth, fifth, and sixth circuit elements. The first circuit element is configured to receive a first voltage of a differential voltage pair. The second circuit element is configured to receive a second voltage of the differential voltage pair. The third circuit element connects the first circuit element to the second circuit element and is configured such that a first current proportional to a difference between the first voltage and the second voltage passes through the third circuit element. The fourth circuit element is coupled to the first circuit element and to the fifth circuit element and is configured to be affected by the first current such that a second current substantially equal in amplitude to the first current passes through the fourth circuit element to the fifth circuit element when the second voltage is greater than the first voltage. The sixth circuit element is coupled to the second circuit element and to the fifth circuit element and is configured to be affected by the first current such that a third current substantially equal in amplitude to the first current passes through said sixth circuit element to the fifth circuit element when the first voltage is greater than the second voltage. As a result, the difference between the first voltage and the second voltage may be determined by reference to the second current and the third current that flow to the fifth circuit element. 
   Another aspect of the present invention also includes a voltage difference detector circuit that comprises a voltage-to-current converter, a first current regulator, a second current regulator, and a current-to-voltage converter. The voltage-to-current converter is configured to 1) receive a first voltage and a second voltage of a differential voltage pair, 2) convert a difference between the first voltage and the second voltage to a first current, 3) draw a second current from the first current regulator substantially equal to a current offset plus the first current, and 4) draw a third current from the second current regulator substantially equal to a current offset minus the first current. The first current regulator is configured to produce at least a first amount of current and to produce a fourth current that flows to the current-to-voltage converter when the first amount of current is greater than the second current—the fourth current is substantially equal to a difference between said second current and said first amount of current. The second current regulator is configured to produce at least a second amount of current and to produce a fifth current that flows to the current-to-voltage converter when the second amount of current is greater than the third current—the fifth current is substantially equal to a difference between the third current and the second amount of current. The current-to-voltage converter is configured to convert the fourth current to a third voltage and to convert the fifth current to a fourth voltage. The third voltage and the fourth voltage are proportional to a difference between the first voltage and the second voltage. 
   Still another aspect of the present invention also includes a signal detector circuit that comprises a first portion, a second portion, a first resistor, and a second resistor. The first portion is coupled to receive a first signal. The second portion is coupled to receive a second signal that is complementary to the first signal. The first resistor is coupled to the first portion and the second portion. The second resistor is coupled to the first portion and the second portion. A current generated in response to a difference between the first signal and the second signal and flowing across the first resistor causes a corresponding current to flow across the second resistor to produce a potential difference that is representative of said difference between the first and second signals. 
   Yet another aspect of the present invention also includes a signal detector circuit. The signal detector circuit includes a first left transistor with a first emitter terminal coupled to a first resistor and a first left constant current source, a first collector terminal coupled to a left current drain, a second left constant current source, and a third left current source, and a first base terminal that receives a first signal, which fluctuates between a maximum voltage and a minimum voltage. The signal detector circuit also includes a first right transistor with a second emitter terminal coupled to the first resistor and a first right constant current source, a second collector terminal coupled to a right current drain, a second right constant current source, and a third right current source, and a second base terminal that receives a second signal that is complementary to the first signal. The signal detector circuit further includes a second resistor coupled to the left current drain and the right current drain. A current generated in response to a difference between the first signal and the second signal and flowing across the first resistor causes a corresponding current to flow across the second resistor to produce a potential difference that is representative of a difference between the first signal and the second signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Aspects of the present invention will be more readily apparent from the following description and appended claims when taken in conjunction with the accompanying drawings, in which: 
       FIG. 1A  is a block diagram of an optical communication system according to an embodiment of the present invention; 
       FIG. 1B  is a graph of the light intensity of an exemplary light signal sent by the transmitter over a period of time; 
       FIG. 1C  is a graph of the signal strength of an exemplary electrical signal produced by a photo-diode over a period of time; 
       FIG. 1D  is a graph of the signal strength of exemplary differential signals produced by a first stage circuit over a period of time; 
       FIG. 2A  is a diagram of a signal detector circuit in accordance with the present invention; 
       FIG. 2B  is a graph of the voltage at points A L  and B L  of the signal detector circuit of  FIG. 2A ; 
       FIG. 2C  is a graph of the voltage at points A R  and B R  of the signal detector circuit of  FIG. 2A ; 
       FIG. 2D  is a graph of the voltage across a first resistor of the signal detector circuit of  FIG. 2A ; 
       FIG. 2E  is a graph of the voltage across a second resistor of the signal detector circuit of  FIG. 2A ; 
       FIG. 2F  is a diagram of another signal detector circuit in accordance with the present invention; and 
       FIG. 2G  is a graph of the voltage across the second resistor of the signal detector circuit of  FIG. 2F . 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
   Preferred embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described. It will be appreciated that in the development of any such embodiment, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. 
     FIG. 1A  shows a block diagram of an optical communication system  100  according to one embodiment of the present invention. The communication system  100  includes an optoelectronic transmitter/transceiver  102  that transmits a light signal  104  with an associated frequency and light intensity. The transmitter  102  typically includes a laser and optics (not illustrated) to transmit the light signal  104 . A light intensity graph  106  included in  FIG. 1B  shows the light intensity of an exemplary light signal  104  sent by the transmitter  102  over a period of time. The light intensity corresponds to the voltage of the light signal  104 . The peak-to-peak amplitude or signal strength of the light signal  104  is denoted on the light intensity graph  106  by the symbol  2 Δ. 
   The communication system  100  also includes an optoelectronic receiver/transceiver  110  that receives the light signal  104  from the transmitter  102 . 
   The receiver  110  contains a photo-diode  112 , a first stage circuit  118  (e.g., a Pre-Amplifier Circuit), and a second stage circuit  124  (e.g., a Post-Amplifier Circuit). In an exemplary implementation, the photo-diode  112  and the first stage circuit  118  are integrated into a Transistor Outline (TO) package  119 , which is typically part of the optoelectronic receiver/transceiver  110 . 
   The photo-diode  112  receives the light signal  104  from the transmitter  102  and converts it to an electrical signal  114 . The electrical signal  114  has an associated signal strength corresponding to the voltage of the electrical signal  114 . A signal intensity graph  116  included in  FIG. 1C  shows the signal strength of an exemplary electrical signal  114  produced by the photo-diode  112  over a period of time. The peak-to-peak amplitude or signal strength of the electrical signal  114  is denoted on the signal intensity graph  116  as  2 Δ′. The signal strength  2 Δ′ of the electrical signal  114  is proportional to the signal strength  2 Δ of the light signal  104 . This proportionality is a function of the photo diode&#39;s  112  scaling or loss factors. 
   The first stage circuit  118  receives the electrical signal  114  from the photo-diode  112  and produces amplified differential signals  120 . The amplified differential signals  120  consist of a positive pre-amplifier output and a negative pre-amplifier output. The amplified differential signals  120  have a signal strength that corresponds to the voltage thereof. A signal intensity graph  122  included in  FIG. 1D  shows the signal strength of exemplary differential signals  120  produced by the first stage circuit  118  over a period of time. In  FIG. 1D , the positive pre-amplifier output corresponds to the dashed line and the negative pre-amplifier output corresponds to the solid line. As shown by the signal intensity graph  122 , the voltage of the positive pre-amplifier output is at a maximum (e.g., at MΔ′) when the voltage of the negative pre-amplifier output is at a minimum (e.g., at −MΔ′) and vice versa. In other words, the amplified differential signals  120  are nominally equal in amplitude, but 180 degrees out of phase. 
   The peak-to-peak amplitude or signal strength of the differential signals  120  is represented on the signal intensity graph  122  as 2MΔ′, where M corresponds to the amplification factor of the first stage circuit  118 . The signal strength  2 Δ of the light signal  104  may be derived from the signal strength 2MΔ′ of the differential signals  120  by first determining the signal strength  2 Δ′ of the electrical signal  114  using the amplification factor M of the first stage circuit  118  and then determining the signal strength  2 Δ of the light signal  104  using the scaling or loss factors of the photo diode  112 . 
   The second stage circuit  124  receives the differential signals  120  from the first stage circuit  118  for further processing. The present invention provides particular circuit designs for use as part of the second stage circuit  124  to determine the signal strength 2MΔ′ of the differential signals  120 . 
   Signal Detector Circuit 
     FIG. 2A  shows a general circuit layout for a signal detector circuit  200  for use in or as the second stage circuit  124  of  FIG. 1A  in accordance with an embodiment of the present invention. As shown in  FIG. 2A , the signal detector circuit  200  includes a first resistor  206  with a resistance value of R 1 , a second resistor  208  with a resistance value of R 2 , a first left transistor  202  (i.e., a first transistor positioned to the left of the first resistor  206  in  FIG. 2A ), a first right transistor  204  (i.e., a first transistor positioned to the right of the first resistor  206  in  FIG. 2A ), a first left current source  212  producing a current I 1   L , a first right current source  214  producing a current I 1   R , a second left transistor  216 , a second right transistor  218 , a third left resistor  220  with a resistance value of R 3   L , a third right resistor  222  with a resistance value of R 3   R , a fourth left resistor  224  with a resistance value of R 4   L , a fourth right resistor  226  with a resistance value of R 4   R , a third left transistor  228 , a third right transistor  230 , a fifth left resistor  232  with a resistance value of R 5   L , a fifth right resistor  234  with a resistance value of R 5   R , a sixth left resistor  236  with a resistance value of R 6   L , a sixth right resistor  238  with a resistance value of R 6   R , a second left current source  240  producing a current I 2   L , and a second right current source  242  producing a current I 2   R . 
   On the left side of the signal detector circuit  200 , the emitter terminal of the first left transistor  202  is coupled to the first resistor  206  and the first left current source  212 . The collector terminal of the first left transistor  202  is coupled to the source terminal of the second left transistor  216 , the source terminal of the third left transistor  228 , and the second left current source  240 . The base terminal of the first left transistor  202  is coupled to the first stage circuit  118  ( FIG. 1A ) and receives a first of the differential signals  120  produced by the first stage circuit  118 . 
   The gate terminal of the second left transistor  216  is coupled to the third and fourth left resistors  220 ,  224 . The third left resistor  220  is also coupled to a power source and the fourth left resistor  224  is also coupled to circuit ground. The drain terminal  213  of the second left transistor  216  is coupled to the second resistor  208  and the drain terminal  211  of the second right transistor  218 . The second resistor  208  is also coupled to circuit ground. 
   The gate terminal of the third left transistor  228  is coupled to the fifth and sixth left resistors  232 ,  236 . The fifth left resistor  232  is also coupled to a power source and the sixth left resistor  236  is also coupled to circuit ground. The drain terminal  215  of the third left transistor  228  is coupled to a power source. The source terminal of the third left transistor  228  is coupled to the source terminal of the second left transistor  216  and coupled to the second left current source  240 . Thus, the third left transistor  228  acts as a third left power source. 
   On the right side of the signal detector circuit  200 , the emitter terminal of the first right transistor  204  is coupled to the first resistor  206  and the first right current source  214 . The collector terminal of the first right transistor  204  is coupled to the source terminal of the second right transistor  218 , the source terminal of the third right transistor  230 , and the second right current source  242 . The base terminal of the first right transistor  204  is coupled to the first stage circuit  118  ( FIG. 1A ) and receives a second of the differential signals  120  produced by the first stage circuit  118 . 
   The gate terminal of the second right transistor  218  is coupled to the third and fourth right resistors  222 ,  226 . The third right resistor  222  is also coupled to a power source and the fourth right resistor  226  is also coupled to circuit ground. The drain terminal  211  of the second right transistor  218  is coupled to the second resistor  208  and the drain terminal  213  of the second left transistor  216 . 
   The gate terminal of the third right transistor  230  is coupled to the fifth and sixth right resistors  234 ,  238 . The fifth right resistor  234  is also coupled to a power source and the sixth right resistor  238  is also coupled to circuit ground. The drain terminal  217  of the third right transistor  230  is coupled to a power source. The source terminal of the third right transistor  230  is coupled to the source terminal of the second right transistor  218  and coupled to the second right current source  242 . Thus, the third right transistor  230  acts as a third right power source. 
   Preferably, the first left transistor  202  and first right transistor  204  are bipolar junction transistors (BJTs) and the second left transistor  216 , second right transistor  218 , third left transistor  228 , and third right transistor  230  are field effect transistors (FETs). The use of these transistors, however, should not be read as a limitation of the invention as other transistor types or combinations may be used without departing from the scope of the present invention. 
   With respect to the current I EL , which is the current flowing out of the emitter of the first left transistor  202 , it is actually equal to the current I CL , which is the current flowing into the collector of the first left transistor  202 , plus the current flowing into the base terminal of the first left transistor  602 . But in preferred embodiments of the present invention, the current I EL  is substantially equal to the current I CL  because the current I CL  is much greater than the current flowing into the base terminal of the first left transistor  202 . Similarly, the current I ER , which is the current flowing out of the emitter of the first right transistor  204 , is substantially equal to the current I CR , which is the current flowing into the collector of the first left transistor  204 , because the current I CR  is much greater than the current flowing into the base terminal of the first right transistor  204 . So for purposes of describing the present invention, the currents I EL  and I CL  and the currents I ER  and I CRL , respectively, are assumed to be identical. And the values of the currents I 1   L , I 1   R , I 2   L , and I 2   R  produced by the first left current source  212 , the first right current source  214 , the second left current source  240 , and the second right current source  242 , respectively, are all approximately equal. 
   Further, the signal detector circuit  200  is preferably configured such that the power sources, resistors, and circuit ground connected directly or indirectly to the gate terminals of the second and third left transistors  216 ,  228  and the second and third right transistors  218 ,  230 , respectively, turn these transistors on and off (e.g., enable the flow of current through the source and drain terminals of these transistors) instead of controlling the flow of current through the source and drain terminals of these transistors so that it corresponds to the voltage at the respective gate terminals of these transistors. So significant current flows through the source and drain terminals of these transistors only when “pulled” or “pushed” by other aspects of the signal detector circuit  200 . 
   The arrows on the source terminals of the second and third left transistors  216 ,  228  and the second and right transistors  218 ,  230  indicate the only direction in which current may flow through these terminals. So if the amplitude of the current I CL  is less than the amplitude of the current I 2   L , which is produced by the second left current source  240 , current flows into and out of the source and drain terminals, respectively, of the second left transistor  216 . Conversely, if the amplitude of the current I CL  is greater than the amplitude of the current I 2   L , current flows from the source terminal of the third left transistor  228 . 
   Similarly, if the amplitude of the current I CR  is less than the amplitude of the current I 2   R , which is produced by the second right current source  242 , current flows into and out of the source and drain terminals, respectively, of the second right transistor  218 . Conversely, if the amplitude of the current I CR  is greater than the amplitude of the current I 2   R , current flows from the source terminal of the third right transistor  230 . 
   Additionally, the voltage drop across the respective collector and emitter terminals of the first left and right transistors  202 ,  204  is preferably greater than or equal to 0.5 volts. This ensures that the first left and right transistors  202 ,  204  are turned on. A voltage drop greater than or equal to 0.5 volts is preferably accomplished with standard transistor biasing techniques known in the art. 
   Persons skilled in the art recognize that when in the active region, the current that flows through the collector and emitter terminals of a transistor is limited by the current received at the base terminal of these transistors and/or the voltage drop across the base terminal and the emitter terminal of these transistors. In other words, such inputs to a transistor may enable a certain amount of current to flow through a transistor, but this amount of current only flows if connected circuitry makes this current available. In embodiments of the present invention, the amplitude of the current produced by the constant current sources  212 ,  214 ,  240 ,  242  and the resistive value of the first resistor are preferably selected so that the current that flows through the collector and emitter terminals of the first left and right transistors  202 ,  204  is only a function of the voltage drop across the first resistor  206  and not the gain of these transistors. 
   Operation of the Signal Detector Circuit 
   In the course of the operation of the signal detector circuit  200 , the base terminal of the first left transistor  202  receives one of the differential signals  120  produced by the first stage circuit  118  and the base terminal of the first right transistor  204  receives the other differential signal  120  produced by the first stage circuit  118 . Again, the voltages received at the base terminals of the first left transistor  202  and the first right transistor  204 , respectively, are nominally equal in amplitude, but 180 degrees out of phase. So if the differential signal  120  received at the base terminal of the first left transistor  202  (i.e., at point A L ) has a voltage of K+MΔ′, the differential signal  120  at the base terminal of the first right transistor  204  (i.e., at point A R ) has a voltage of K−MΔ′ and vice versa. K is preferably a DC voltage offset sufficiently high enough to at least ensure that the first left transistor  202  and the first right transistor  204  are turned on regardless of the value of the differential signals  120 . More specifically, the offset voltage across the base and emitter of a typical transistor (e.g., the first left transistor  202  and the first right transistor  204 ) is usually 0.6 or 0.7 volts. Persons skilled in the art recognize that the voltage at the base of a typical transmitter (e.g., K+MΔ′ to K−MΔ′) must be greater than the offset voltage in order for the transistor to be turned on. Numerous circuits (not illustrated) known in the art may be used to add the DC offset voltage K to the differential signals  120  produced by the first stage circuit  118  without departing from the scope of the present invention. 
   The voltage at point A L  over time is shown in  FIG. 2B  as a solid line. As shown in  FIG. 2B , the differential signal  120  received at point A L  has a peak-to-peak amplitude of 2MΔ′ and fluctuates between a maximum voltage of K+MΔ′ and a minimum voltage of K−MΔ′. The voltage at point A R  over time is shown in  FIG. 2C  as a solid line. As shown in  FIG. 2C , the differential signal  120  received at point A R  also has a peak-to-peak amplitude of 2MΔ′ and fluctuates between a maximum voltage of K+MΔ′ and a minimum voltage of K−MΔ′. 
   When the voltage at point A L  is equal to K+MΔ′, the voltage at the emitter terminal of the first left transistor  202  (i.e., at point B L ) is equal to (K+MΔ′−0.7V), 0.7V being a typical offset voltage across the base and emitter of a transistor. Similarly, when the voltage at point A R  is equal to K−MΔ′, the voltage at the emitter terminal of the first right transistor  204  (i.e., at point B R ) is equal to (K−MΔ′−0.7V). The voltage at points B L  and B R  are shown in  FIGS. 2B and 2C , respectively, as dashed lines. As shown in  FIG. 2B , the peak-to-peak voltage at point B L  over time is the same as the voltage at point AL but offset by 0.7V. Similarly, the peak-to-peak voltage at B R  over time is the same as the voltage at A R  but offset by 0.7V. 
   When the voltage at point B L  is equal to (K+MΔ′−0.7V) and the voltage at point B R  is equal to (K−MΔ′−0.7V), the voltage V R1  across the first resistor  206  is equal to (K+MΔ′−0.7V)−(K−MΔ′−0.7V), which is equal to 2MΔ′. When the voltage at point B L  is equal to (K−MΔ′−0.7V) and the voltage at point B R  is equal to (K+MΔ′−0.7V), the voltage V R1  across the first resistor  206  is equal to (K−MΔ′−0.7V)−(K+MΔ′−0.7V), which is equal to −2MΔ′. The voltage V R1  over time is shown in  FIG. 2D  and varies from a maximum voltage of 2MΔ′ to a minimum voltage of −2MΔ′. The current I R1  flowing through the first resistor  206 , therefore, is equal to (V R1 /R 1 ) and varies from (2MΔ′/R 1 ) to (−2MΔ′/R 1 ) over time. 
   The value of the current I EL  flowing out of the emitter terminal of the first left transistor  202  is equal to the current I 1   L  produced by the first left current source  212  plus the current I R1  flowing through the first resistor  206 . Therefore, when the voltage at point A L  is at a maximum voltage of K+MΔ′, the current I EL  is equal to (I 1   L +2MΔ′/R 1 ). And when the voltage at point A L  is at a minimum voltage of K−MΔ′, the current I EL  is equal to (I 1   L +(−2MΔ′/R 1 )). 
   So when the voltage at point A L  is at a maximum voltage of K+MΔ′, current I CL , which is assumed to be equal to the current I EL , is (I 1   L +2MΔ′/R 1 ). If the current I 2   L  produced by the second left current source  240  is equal to I 1   L , a current equal to (2MΔ′/R 1 ) is pulled from the third left transistor  228  and no significant amount of current flows into the second left transistor  216 . 
   And when the voltage at point A L  is at a minimum voltage of K−MΔ′, current I CL  is (I 1   L +(−2MΔ′/R 1 )). If the current I 2   L  produced by the second left current source  240  is equal to I 1   L , a current equal to (2MΔ′/R 1 ) is pushed through the second left transistor  216  and no significant amount of current flows through the third left transistor  228 . 
   In other words, when the current flowing through the first left transistor  202  is less than the current produced by the second left current source  240 , the excess amount of the current produced by the second left current source  240  flows through the second left transistor  216 . And when the current flowing through the first left transistor  202  is greater than the current produced by the second left current source  240 , the shortfall of current flows through the third left transistor  228  and combines with the current produced by the second left current source  240 . 
   As noted above, current only flows through the transistors illustrated in  FIG. 2A  in the direction of the corresponding arrows. So when current flows (i.e., is pushed) through the second left transistor  216 , all of this current flows through the second resistor  208 —none of-this current flows through the second right transistor  218 . The voltage drop across the second resistor  208  when the voltage at point A R  is at a minimum voltage of K−MΔ′, therefore, is equal to (2MΔ′/R 1 )*R 2 . 
   The first and second left current sources  212 ,  240 , therefore, are preferably configured to ensure that 1) a positive current always flows through the first left transistor  202 , a requirement for the first left transistor  202  to remain on and 2) a current proportional to the differential signals  120  flows through the second left transistor  216  when the current I 2   L  exceeds the current I CL . To do so, these current sources preferably each produce a current greater than (2MΔ′/R 1 ). 
   The value of the current I ER  flowing out of the emitter terminal of the first right transistor  204  is equal to the current I 1   R  produced by the first right current source  214  minus the current I R1  flowing through the first resistor  206 . Therefore, when the voltage at point A R  is at a minimum voltage of K−MΔ′, the current I ER  is equal to (I 1   R +(−2MΔ′/R 1 )). And when the voltage at point A R  is at a maximum voltage of K+MΔ′, the current I ER  is equal to (I 1   R +2MΔ′/R 1 )). 
   So when the voltage at point A R  is at a minimum voltage of K−MΔ′, current I CR , which is assumed to be equal to the current I ER , is (I 1   R +(−2MΔ′/R 1 )). If the current I 2   R  produced by the second right current source  242  is equal to I 1   R , a current equal to (−2MΔ′/R 1 ) is pushed through the second right transistor  218  and no significant amount of current flows through the third right transistor  230 . 
   And when the voltage at point A R  is at a maximum voltage of K+MΔ′, current I CR  is (I 1   R +2MΔ′/R 1 ). If the current I 2   R  produced by the second right current source  242  is equal to I 1   R , a current equal to (2MΔ′/R 1 ) is pulled from the third right transistor  230  and no significant amount of current flows into the second right transistor  218 . 
   In other words, when the current flowing through the first right transistor  204  is greater than the current produced by the second right current source  242 , the shortfall of current flows through the third right transistor  230  and combines with the current produced by the second right current source  242 . And when the current flowing through the first right transistor  204  is less than the current produced by the second right current source  242 , the excess amount of the current produced by the second right current source  242  flows through the second right transistor  218 . 
   When current flows (i.e., is pushed) through the second right transistor  218 , all of this current flows through the second resistor  208 —none of this current flows through the second left transistor  216 . The voltage drop across the second resistor  208  when the voltage at point A R  is at a minimum voltage of K−MΔ′, therefore, is equal to (2MΔ′/R 1 )*R 2 . 
   The first and second right current sources  214 ,  242 , therefore, are preferably configured to ensure that 1) a positive current always flows through the first right transistor  204 , a requirement for the first right transistor  204  to remain on and 2) a current proportional to the differential signals  120  flows through the second right transistor  218  when the current I 2   R  exceeds the current I CR . To do so, these current sources preferably each produce a current greater than (2MΔ′/R 1 ). 
   So regardless of which differential signal is at a minimum voltage of K−MΔ′, the voltage across the second resistor  208  (i.e., the voltage V R2 ) is equal to (2MΔ′/R 1 )*R 2 . The ideal output of the signal detector circuit  200  or the voltage drop, V R2 , across the second resistor  208  is illustrated in  FIG. 2E . 
   Since the values of R 1  and R 2  are known, the signal strength 2MΔ′ of the differential signals  120  can be determined from the voltage V R2  across the second resistor  208 . As stated above, the signal strength 2Δ of the light signal  104  may be derived from the signal strength 2MΔ′ of the differential signals  120  by first determining the signal strength 2Δ′ of the electrical signal  114  using the amplification factor M of the first stage circuit  118  and then determining the signal strength  2 Δ of the light signal  104  using the scaling or loss factors of the photo diode  112 . 
   In some embodiments, the voltage drop across the second resistor  208  is input to, for example, an A/D converter  252 —as illustrated in  FIG. 2F . The output of the A/D converter may then be read by a microprocessor  254  or other device. The result can thus be read by an external system via a standard transceiver interface. 
   As stated above, output of the signal detector circuit  200  illustrated in  FIG. 2E  is an idealized output. In actuality, the voltage wave forms illustrated in  FIGS. 2B-2D  are not perfect square waves. Instead, a certain amount of time is required for the voltages to swing from a maximum amplitude to a minimum amplitude and vice versa. As a result, there will be periods of time in which neither of the voltages at the base terminals of-the first left transistor  202  and the first right transistor  204 , respectively, are equal to the minimum voltage of K−MΔ′. During these periods of time, one of these voltage is between 0 and K−MΔ′ and the other is between 0 and K+MΔ′. So the current that flows through the second resistor  208 , for these periods of time, varies between (2MΔ′/R 1 ) to (−2MΔ′/R 1 ). An exemplary, actual voltage drop, V R2 , across the second resistor  208  is illustrated in  FIG. 2G  (this too is a somewhat idealized illustration as the actual voltage wave form is not likely entirely linear). As a result, a capacitor  250  may be included in some embodiments of the present invention in parallel with the second resistor  208 , as also illustrated in  FIG. 2F , in order to smooth out the wave form illustrated in  FIG. 2G . In still other embodiments, the period of the differential signals is known so that the voltage V R2  is sampled only during periods of stability, which correspond to when the voltages at the base terminals of one or the other of the first left transistor  202  and the first right transistor  204  is equal to the minimum voltage of K−MΔ′. 
   But even with the slight errors described in the previous paragraph, the present invention represents an improvement over prior art signal detector circuits. This is due in part to the fact that the present invention does not rely upon the gain of the transistors included therein. Instead, the transistors are merely turned on to enable the flow of current. And the current across the second resistor  208  results from current across the first resistor  206 , which is a function of the relative values of the differential signals  120 , and the fact that current flows through transistors in only one direction regardless of temperature or method of manufacture. And any offset voltage variations of the transistors illustrated in  FIG. 2A  or  FIG. 2F  due to temperature are largely offset by equal changes in corresponding transistors (e.g., a change in the offset voltage of the first left transistor  202  is largely offset by an equal change in the offset voltage of the first right transistor  204 ). 
   While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art having the benefit of this disclosure without departing from the inventive concepts described herein.