Abstract:
A semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a column address controller configured to deassert a column address to a logic low level in response to a deasserted detection signal. The semiconductor integrated circuit may selectively support one of first and second memory capacities and one of the first and second input/output modes using the logic levels of the first and second pads.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2011-0009077 filed on Jan. 28, 2011 in the Korean Intellectual Property Office, which is incorporated by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a semiconductor circuit, and more particularly, to a semiconductor integrated circuit. 
     2. Related Art 
     A semiconductor integrated circuit may be manufactured is with various memory capacities and input/output modes. 
     A conventional semiconductor integrated circuit such as, for example, DRAM may be configured as X8 — 512M, X16 — 512M, and X16 — 256M. 
     X8 — 512M is a 512 Mb DRAM with eight input/output data terminals DQ 0  to DQ 7 . Similarly, X16 — 512M 512 Mb DRAM with 16 input/output terminals DQ 0  to DQ 15 , and X16 — 256M is a 256 Mb DRAM with 16 input/output terminals DQ 0  to DQ 15 . 
     According to a specification of the semiconductor integrated circuit as shown in  FIG. 1 , X8 — 512M uses row addresses A 0  to A 13  and column addresses A 0  to A 9 , X16 — 512M uses row addresses A 0  to A 12  and column addresses A 0  to A 9 , and X16 — 256M uses row addresses A 0  to A 12  and column addresses A 0  to A 8 . 
     As shown in  FIG. 1 , when the number of column addresses is reduced by one bit, half of the X16 — 512 Mb DRAM may be operated as X16 — 256M. 
     A conventional semiconductor integrated circuit includes a pad IOX 8  to select either a X8 or X16 input/output mode. 
     Referring to  FIG. 2 , X8 — 512M fixes the pad IOX 8  to a logic high level, and X16 — 512M and X16 — 256M fix the pad IOX 8  to a logic low level. 
     Furthermore, since X8 — 512M uses a row address A 13 , X8 — 512M controls the corresponding pad to receive the row address A 13  from outside. Since X16 — 512M and X16 — 256M do not use the row address A 13 , X16 — 512M and X16 — 256M float the corresponding pad. 
     The conventional semiconductor integrated circuit uses a fuse circuit provided therein, in order to support various products such as X8 — 512M, X16 — 512M, and X16 — 256M. In particular, the fuse circuit is used to support 256 Mb DRAM using 512 Mb DRAM. That is, the type of a product may be defined by blowing a fuse of the fuse circuit or not. 
     However, the fuse cannot be restored to the original state after it is blown. That is, only 256 Mb of 512 Mb may be used after the corresponding fuse is blown. 
     Therefore, since the conventional semiconductor integrated circuit decides a memory capacity through a fuse, it is difficult to change the quantity of products shipped to deal with changing demand. 
     Whether or not to blow a fuse is determined during a probe test. In this state, it is difficult to estimate the demand, that is, determine whether to use 256 Mb or 512 Mb. Furthermore, the fuse may cause problems during a blowing process, thereby reducing the reliability of the semiconductor memory integrated circuit. 
     SUMMARY 
     A semiconductor integrated circuit capable of supporting various products without using a fuse is described herein. 
     In one embodiment of the present invention, a semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a column address controller configured to generate a column address at a logic low level in response to the detection signal, wherein the semiconductor integrated selectively supports one of first and second memory capacities and one of the first and second input/output modes using the logic levels of the first and second pads. 
     In another embodiment of the present invention, a method may comprise receiving a first signal via a first pad, receiving a second signal via a second pad allocated to discriminate between a first input/output mode and a second input/output mode, generating a detection signal in response to logic levels of the first and second pads, and generating a column address at a logic low level in response to a deasserted detection signal. One of first and second memory capacities may be selectively supported and one of the first and second input/output modes may be selectively supported using the first and second signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features, aspects, and embodiments are described in conjunction with the attached drawings: 
         FIG. 1  is a table showing an address specification of a semiconductor integrated circuit; 
         FIG. 2  is a table showing a pad setting method of a conventional semiconductor integrated circuit; 
         FIG. 3  is a table showing a pad setting method of a semiconductor integrated circuit according to one embodiment of the invention; 
         FIG. 4  is a block diagram of a semiconductor integrated circuit  100  according to an embodiment of the invention; 
         FIG. 5  is a block diagram of a semiconductor integrated circuit  101  according to an embodiment of the invention; and 
         FIG. 6  is a block diagram of a semiconductor integrated circuit  102  according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     A semiconductor integrated circuit according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments. 
     A semiconductor integrated circuit according to one embodiment, for example, 512 Mb DRAM may support various product configurations such as, for example, X8 — 512M, X16 — 512M, and X16 — 256M. 
     At this time, X8 — 512M represents a 512 Mb DRAM using eight input/output terminals DQ 0  to DQ 7 , X16 — 512M represents a 512 Mb DRAM using 16 input/output terminals DQ 0  to DQ 15 , and X16 — 256M represents a 256 Mb DRAM using 16 input/output terminals DQ 0  to DQ 15 . 
     The semiconductor integrated circuit according to an embodiment of the invention does not use a fuse circuit, but may support the above-described products through a pad bonding method. 
     As known from  FIG. 1  showing the address specification of the semiconductor integrated circuit, X16 — 256M does not use the column address A 9  while the X8 — 512M and X16 — 512M configurations do. 
     Therefore, in order to use a semiconductor integrated circuit as X16 — 256M, the semiconductor integrated circuit may be set so as not to use the column address A 9 . 
     The X8 type (X8 — 512M) and the X16 type (X16 — 512M and X16 — 256M) may be discriminated through a pad IOX 8  for discriminating an input/output type (X8 or X16). 
     Furthermore, a row address A 13  which is not used in X16 — 512M and X16 — 256M may be used to discriminate X16 — 512M and X16 — 256M from the X8 — 512M. 
     In the semiconductor integrated circuit according to an embodiment, logic levels of the pad IOX 8  and a pad A 13  receiving a row address are used as a signal for discriminating a particular I/O configuration X8 — 512M, X16 — 512M, or X16 — 256M for one semiconductor integrated circuit chip. 
     Furthermore, when a semiconductor integrated circuit is configured for the X16 — 256M configuration, the semiconductor integrated circuit is set so as not to use the column address A 9 . 
     First, referring to  FIG. 3 , X8 — 512M fixes the pad IOX 8  to a logic high level, and X16 — 512M and X16 — 256M fix the pad IOX 8  to a logic low level, during packaging of the semiconductor integrated circuit. 
     Furthermore, since X8 — 521M uses the row address A 13 , X8 — 512M controls the corresponding pad to receive the row address A 13  from outside, and X16 — 512M and X16 — 256M fix the pads allocated to receive the row address A 13  to a logic high level and a logic low level, respectively. 
     The fixing of the pad IOX 8  to a logic high level may be performed by bonding the corresponding pad to a power supply voltage terminal VDD. 
     The fixing of the pad IOX 8  to a logic low level may be performed by bonding the corresponding pad to a ground terminal VSS. 
     A circuit may use signals from the pad IOX 8  and the row address A 13  to control use of the column address A 9  in the case of X16 — 512 and X16 — 256M. That circuit may be configured in a predetermined area (for example, a peripheral circuit area) inside the semiconductor integrated circuit. 
     According to the table of  FIG. 3 , the pad IOX 8  and the row address A 13  have a logic low level L for a X16 — 256M configuration. 
     Therefore, when both of the pad IOX 8  and the row address A 13  have a logic low level, an input of the column address A 9  may be blocked. 
       FIG. 4  illustrates an X8 — 512M-type semiconductor integrated circuit  100 . The semiconductor integrated circuit  100  includes pads  101  to  103 , a detector  110 , and a column address controller  120 . The column address controller  120  includes an address blocking unit  121 . 
     Since the X8 — 512M type uses the row address A 13  as shown in  FIG. 3 , a pad A 13  is configured to normally receive the row address A 13  from outside, and a pad IOX 8  is fixed to a logic high level. 
     The detector  110  includes a plurality of inverters IV 1  to IV 3  and a NAND gate ND 1 . 
     The detector  110  is configured to output a detection signal HALFC_A 9  at a logic low level in response to the high-level pad IOX 8 . 
     The column address controller  120  is configured to control a column operation of the semiconductor integrated circuit in response to a column address inputted from outside. 
     The address blocking unit  121  includes a plurality of inverters IV 4  and IV 5  and a NAND gate ND 2 . 
     The address blocking unit  121  is configured to block an is input of the column address A 9  in response to the detection signal HALFC_A 9 . That is, the address blocking unit  121  fixes an internal column address iA 9  to a logic low level in response to an asserted detection signal HALFC_A 9  at a high level, and receives the column address A 9  as the internal column address iA 9  in response to a deasserted detection signal HALFC_A 9  at a low level. 
     In the X8 — 512M-type semiconductor integrated circuit  100 , since the pad IOX 8  is fixed to a logic high level, the detection signal HALFC_A 9  becomes a logic low level such that the column address A 9  is received as the internal column address iA 9 . 
       FIG. 5  illustrates an X16 — 512M-type semiconductor integrated circuit  101 . The semiconductor integrated circuit  101  includes a plurality of pads  101  to  103 , a detector  101 , and a column address controller  120 . The column address controller  120  includes an address blocking unit  121 . 
     The detector  110 , the column address controller  120 , and the address blocking unit  121  may be similar to the circuit illustrated in  FIG. 4 . 
     For the X16 — 512M-type semiconductor integrated circuit  101  does not use the row address A 13 . Therefore, as shown in  FIG. 3 , the pad A 13  is fixed to a logic high level and the pad IOX 8  is fixed to a logic low level. 
     In the X16 — 512M-type semiconductor integrated circuit  101 , since the pad A 13  is fixed to a logic high level, the detection signal HALFC_A 9  becomes a logic low level. Accordingly, the X16 — 512M-type semiconductor integrated circuit  101  receives the column address A 9  as an internal column address iA 9 . 
       FIG. 6  illustrates an X16 — 256M-type semiconductor integrated circuit  102 . The X16 — 256M-type semiconductor integrated circuit  102  includes a plurality of pads  101  to  103 , a detector  110 , and a column address controller  120 . The column address controller  120  includes an address blocking unit  121 . 
     The detector  110 , the column address controller  120 , and the address blocking unit  121  may be similar to the circuit illustrated in  FIG. 4 . 
     As illustrated in  FIG. 3 , since the X16 — 256M-type semiconductor integrated circuit  102  does not use the row address A 13 , the pad A 13  is fixed to a logic low level, and the pad IOX 8  is fixed to a logic low level. 
     In the X16 — 256M-type semiconductor integrated circuit  102 , since both of the pad A 13  and the pad IOX 8  are fixed to a logic low level, the detection signal HALFC_A 9  becomes a logic high level, which drives the internal column address iA 9  to a logic low level. 
     According to the embodiment, since a fuse is not used, it is possible to improve the reliability and productivity of the semiconductor integrated circuit. 
     While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor integrated circuit described herein should not be limited based on the described embodiments. Rather, the semiconductor integrated circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.