Abstract:
In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to semiconductor devices, and more particularly, to a method of forming a storage node of capacitor in a semiconductor memory such as a DRAM (Dynamic Random Access Memory) and a structure thereof.  
         [0003]     2. Description of the Related Art  
         [0004]     A memory cell of DRAM is generally constructed of one access transistor and one storage capacitor. The capacitor is largely classified as a laminated type or a trench type depending on its formed position on a semiconductor substrate.  
         [0005]     Semiconductor manufacturers for manufacturing a semiconductor memory that employs the laminated-type capacitor have continuously researched producing capacitors with a higher capacitance in a limited area in conformity with various requirements of semiconductor users. The need for this continuous research is derived from the high integration of memory cells that produces a tightened critical dimension which results in low capacitance of the memory cells. However, in order to guarantee a refresh operating period within a range of regulated value, the capacitance must instead be increased.  
         [0006]     Capacitors are generally composed of a storage node as a lower electrode node and a plate node as an upper electrode. High integration causes the bottom critical dimension (CD) of the storage node to be too small which causes a leaning phenomenon resulting in the collapse of the storage node.  
         [0007]     To prevent the leaning phenomenon, two methods have widely been used in this field. First is the method of increasing the bottom CD of straight type storage node. Second is the a method of lowering the height of storage node. However, the straight type method is undesirable because it is difficult to increase the bottom CD after a design rule was first decided, and the latter method is undesirable because it is unlikely to obtain the desired capacitance.  
         [0008]     The former method was recently improved to provide a larger bottom CD and reduce the occurrence rate of the leaning phenomenon within a limited area. In this improved method, and in forming the storage node of the capacitor, an active region, a gate, a bit line contact, a storage node contact or buried contact, and bit line patterns are formed in a diagonal direction slightly slanted as compared with the existing straight structure, and thereon, the capacitor storage node is formed. This improved method significantly increases the bottom CD of the storage node as compared with the storage node of the existing straight type, and this is known in this field as a diagonal structure. However, this diagonal structure has severely complicated manufacturing processes in forming the storage node.  
         [0009]     To avoid the complicated manufacturing processes of the diagonal structure, a new method for forming a storage node of square type was recently developed which shared advantages of the straight structure and the diagonal structure. In this method for the square type, an active region, a gate, a bit line and a capacitor storage node contact etc. are formed by the existing straight structure. Then, entirely thereon, a buffer layer is formed, and a contact is formed in the buffer layer, to thus connect the capacitor storage node of square type with a capacitor storage node contact of the straight structure. This new method has been regarded as increasing the storage node of the square type so that the bottom CD of the capacitor storage node is largely increased to about twice that of the storage node of the straight type based on the straight structure.  
         [0010]     The method of manufacturing the storage node of square type in the prior art will be described referring to  FIGS. 1 through 6 , as follows, only to provide a thorough understanding of the present invention to be described later.  
         [0011]      FIG. 1  is a plan view illustrating a disposed relationship for storage nodes of capacitor based on a square type in a semiconductor memory according to an example of the prior art. FIGS.  2  to  6  are sectional views showing sequential processes in manufacturing the storage node referred to  FIG. 1 .  
         [0012]     Referring first to  FIG. 1 , vertically on the drawing, six word line patterns  13  as gates of a plurality of access transistors are formed, and horizontally on the drawing, four bit line patterns  16  connected to drains of the access transistors are formed. Storage nodes  23  of square type of the capacitors form an oblong structure in a diagonal direction to the bit line patterns  16  and the word line patterns  13 . Herewith, each contact  17  of the storage node of capacitor and its lower structure are formed by a straight structure as the afore-mentioned. A reference number  14  indicates a bit line contact for connecting a bit line with a drain, and  14   a  designates a bit line pad. FIGS.  2  to  6  are sectional views taken along A-A′ and B-B′ cutting lines shown in  FIG. 1 .  
         [0013]     On the left drawings of  FIGS. 2 through 6 , cross-sectional views taken along A-A′ cutting line direction of  FIG. 1 , namely, the direction of a word line connected to a gate of access transistor, are illustrated per process. On the right drawings of FIGS.  2  to  6 , cross-sectional views taken along B-B′ cutting line direction of  FIG. 1 , namely, the direction of a bit line connected to a drain of the access transistor, are illustrated per process.  
         [0014]      FIG. 2  illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure. A device separate layer  3  is formed on a determined region of a semiconductor substrate  11  to define a plurality of active regions. A gate oxide layer  5  is formed on the active regions. Thereon, a plurality of parallel word line patterns  13  traversing the active regions are formed. The word line pattern  13  contains a word line  7   b  and a capping layer pattern  7   c  laminated sequentially. An impurity ion is implanted into the active regions by using the word line pattern  13  and the device separate layer  3  as an ion implantation mask, to form impurity regions  4   s ,  4   d . The active impurity regions  4   d  between one pair of word line patterns  13  traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, the impurity region  4   s  formed on both sides of each common drain region  4   d  is pertinent to a source region of the DRAM cell transistor. A word line spacer  7   a  is formed on a sidewall of the gate oxide layer  5  and the word line patterns  13 . A first interlayer insulation layer  13   a  is formed on an entire face of the semiconductor substrate containing the word line spacer  7   a . The first interlayer insulation layer  13   a  is etched by using an etch mask pattern, to form the bit line pad  14   a  connected with the common drain region  4   d  and a capacitor storage node pad  12  connected with the source region  4   s . Then, a second interlayer insulation layer  16   a  is formed on an entire face of the semiconductor substrate containing the bit line pad  14   a  and the capacitor storage node pad  12 . The second interlayer insulation layer  16   a  is patterned to form the bit line contact  14  referred to  FIG. 1 . Then, the bitline contact  14  is connected with the plurality of bit line patterns  16  having a sidewall spacer  15 . The bit line patterns  16  are formed, involving a bit line  16   b  and a bit line capping layer pattern  16   c  each laminated sequentially and traversing the word line patterns  13 . Each bit line  16   b  is electrically connected to the bit line pad  14   a  through the bit line contact  14 . A third interlayer insulation layer  15   a  is formed on an entire face of the semiconductor substrate containing the bit line spacer  15 . The third interlayer insulation layer  15   a  and the second interlayer insulation layer  16   a  are continuously patterned to form a capacitor storage node contact  17 .  
         [0015]     The lower structure of semiconductor substrate composed of the active region  4   s ,  4   d , the bitline contact  14 , the capacitor storage node pad  12 , the bitline pattern  16 , the word line pattern  13  and the capacitor storage node contact  17  etc., is formed by the straight structure.  
         [0016]     Referring to  FIG. 3 , a buffer layer  18  is formed on the semiconductor substrate  11  having the capacitor storage node contact  17 . An aperture for connecting the storage node of square type with the capacitor storage node contact  17  is formed through a photolithography and etching process. Metallic material such as tungsten etc. is deposited in the aperture and then a flattening is performed to form a pad contact  19 .  
         [0017]     Referring to  FIG. 4 , film material such as silicon nitride layer etc. is deposited to form an etching stop layer  20  on the semiconductor substrate having the pad contact  19 . Thereon, a mold oxide layer  21  for a formation of the storage node of capacitor is formed by a thick thickness.  
         [0018]     In  FIG. 5 , an etching mask pattern is formed in the mold oxide layer  21 , and an aperture part  22  is formed to expose an upper part of the pad contact  19  connected with the storage node of the capacitor, through an etching process.  
         [0019]     In  FIG. 6 , a chemical vapor deposition(CVD) process is performed on an entire face of the semiconductor substrate having the aperture part  22 , to form a conductive layer  23  of polysilicon etc. The conductive layer remained on an upper part of the mold oxide layer is removed through a process such as a flattening etc., to form the capacitor storage node of square type. The capacitor storage node  23   a  through  23   e  of square type provides a sectional face of the storage node of the capacitor based on the square type referred to  FIG. 1 .  
         [0020]     In the prior art described above, in order to form a capacitor storage node of square type on a semiconductor substrate based on a conventional straight lower structure, a buffer layer is adapted. Thus, there is a problem of an additional step of forming a pad contact on the buffer layer, the pad contact being for connecting the storage node of square type with a storage node contact of straight structure.  
       SUMMARY OF THE INVENTION  
       [0021]     In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     The above and other features of exemplary embodiments of the present invention will become readily apparent from the description of the exemplary embodiment that follows, Referring to the attached drawings in which:  
         [0023]      FIG. 1  is a plan view illustrating a disposed relationship of storage nodes of capacitors based on a square type in a semiconductor memory according to the prior art.  
         [0024]      FIGS. 2 through 6  are cross-sectional views of sequential processes for manufacturing the storage node referred to  FIG. 1 .  
         [0025]      FIG. 7  is a plan view illustrating a disposed relationship of storage nodes of capacitors based on a square type in a semiconductor memory according to an exemplary embodiment of the present invention.  
         [0026]      FIGS. 8 through 13  are cross-sectional views of sequential processes for a manufacturing of the storage node referred to  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0027]     It will be understood by those skilled in the art that the present invention can be embodied by numerous different types and is not limited to the following described embodiments. The following various embodiments are exemplary in nature.  
         [0028]      FIG. 7  is a plan view showing a capacitor storage nodes of a square type in a semiconductor memory according to an exemplary embodiment of the present invention.  FIGS. 8 through 13  are cross-sectional views of sequential processes for manufacturing the storage node referred to in  FIG. 7 .  
         [0029]     Referring to  FIG. 7 , vertically on the drawing, six word line patterns  113  as gates of a plurality of access transistors are formed, and horizontally on the drawing, four bit line patterns  116  connected to drains of the access transistors are formed. Storage nodes  123  of the capacitors based on a square type form an oblong structure in a diagonal direction to the bit lines  116  and the word lines  113 . Herewith, a storage node contact  117  of each capacitor storage node, an interlayer insulation layer and its below structure are formed by a straight structure as the afore-mentioned. The capacitor storage node  123  is in contact with an inner face of an aperture part  125  that is formed at a portion of the storage node contact  117  based on the straight structure, to be thus electrically connected to the storage node contact  117 . A reference number  114  indicates a bit line contact for connecting a bit line with a drain, and  114   a  designates a bit line pad. FIGS.  8  to  13  are cross-sectional views taken along C-C′ and D-D′ cutting lines referred to  FIG. 7 .  
         [0030]     On the left drawings of  FIGS. 8 through 13 , cross-sectional views taken along line C-C of  FIG. 7 , namely, a direction of a word line connected to a gate of access transistor, are illustrated per process. On the right drawings of FIGS.  8  to  13 , cross-sectional views taken along line D-D′ of  FIG. 7 , namely, a direction of a bit line connected to a drain of the access transistor, are illustrated per process.  
         [0031]      FIG. 8  illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure. A device separate layer  103  is formed on a determined region of a semiconductor substrate  111  to define a plurality of active regions. A gate oxide layer  105  is formed on the active regions. Thereon, a conductive layer and a word line capping layer are formed sequentially. The conductive layer is formed of polysilicon layer or metallic polycide layer. The word line capping layer can be desirably formed of silicon nitride layer. The word line capping layer and the conductive layer are continuously patterned to form a plurality of parallel word line patterns  113  traversing the active regions. The word line pattern  113  contains a word line  107   b  and a capping layer pattern  107   c  laminated sequentially. An impurity ion is implanted into the active regions by using the word line patterns  113  and the device separate layer  103  as an ion implantation mask, to form impurity regions  104   s ,  104   d . The active impurity regions  104   d  between one pair of word line patterns  113  traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, the impurity regions  104   s  formed on both sides of the common drain region  104   d  are pertinent to a source region of the DRAM cell transistor. A word line spacer  107   a  is formed on a sidewall of the gate oxide layer  105  and the word line patterns  113  through a general method. The word line spacer  107   a  can be desirably formed of material layer same as the word line capping layer pattern  107   c . A first interlayer insulation layer  113   a  is formed on an entire face of the semiconductor substrate containing the word line spacer  107   a . The first interlayer insulation layer  113   a  is etched by using an etch mask pattern, to form the bit line pad  114   a  connected with the common drain region  104   d  and a capacitor storage node pad  112  connected with the source region  104   s . Then, a second interlayer insulation layer  116   a  is formed on an entire face of the semiconductor substrate containing the bit line pad  114   a  and the capacitor storage node pad  112 . The second interlayer insulation layer  116   a  is patterned to form the bit line contact  114  referred to  FIG. 7 . Then, the plurality of bit line patterns  116  having a sidewall spacer  115  are formed being connected with the bitline contact  114 . The bit line patterns  116  are formed traversing the word line patterns  113 . The bit line pattern  116  involves a bit line  116   b  and a bit line capping layer pattern  116   c  laminated sequentially. The bitline  116   b  is formed of a conductive layer such as a tungsten layer or tungsten polycide layer, and the bitline capping layer pattern  116   c  is formed of silicon nitride layer. The bitline spacer  115  is formed at a sidewall of the bitline  116   b . The bitline spacer  115  is formed of a nitride layer having an etch selection rate for silicon oxide. Each bitline  116   b  is electrically connected to the bit line pad  114   a  through the bit line contact  114 . A third interlayer insulation layer  115   a  is formed on an entire face of the semiconductor substrate containing the bit line spacer  115 . The third interlayer insulation layer  115   a  and the second interlayer insulation layer  116   a  are continuously patterned to form the capacitor storage node contact  117 . The capacitor storage node contact  117  may be formed of polysilicon.  
         [0032]     The lower structure of semiconductor substrate constructed of the active regions  104   s ,  104   d , the bitline contact  114 , the capacitor storage node pad  112 , the bitline pattern  116 , the word line pattern  113  and the capacitor storage node contact  117  may be formed by the straight structure.  
         [0033]     Referring to  FIG. 9 , a buffer layer  118  made of PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) is formed on the semiconductor substrate having the capacitor storage node contact  117 . The buffer layer  118  can be formed to prevent the structure below the buffer layer from being damaged. Subsequently, an etching stop layer  120  is formed on the buffer layer  118 . Then, a mold oxide layer  121  having a high etch selection rate as compared with the etching stop layer is formed. The etching stop layer  120  can be formed of silicon nitride layer if the mold oxide layer  121  is made of PE-TEOS material.  
         [0034]     That is, the mold oxide layer  121 , on which a capacitor storage node of square type will be formed, e.g., a single layer of PE-TEOS or a multilayer containing the PE-TEOS layer, is formed thick.  
         [0035]      FIG. 10  illustrates a process of forming a first aperture part  122 , that is, after etching a portion of the mold oxide layer until a top surface of the etching stop layer is exposed, to be overlapped with an upper portion of the conductive region, by using an etch mask pattern (not shown) formed by, for example, a square type. To prevent an excessive etching, the etching is preferably stopped at the etching stop layer  120 . The etch mask can be formed of polysilicon.  
         [0036]     Referring to  FIG. 11 , after etching a portion of the mold oxide layer  121 , the etching stop layer  120  is removed, and the buffer layer  118  is etched to form the first aperture part  122  for exposing the capacitor storage node contact  117 . The conductive region  117  exposed in the first aperture part  122  is illustrated as the capacitor storage node contact  117  in the drawing. This conductive region may be in communication with a source region of the transistor.  
         [0037]     Referring to  FIG. 12 , the capacitor storage node contact  117  exposed in the first aperture part  122  is selectively etched, to form a second aperture part  125  in which the capacitor storage node  123  of square type will be formed. The second aperture part is formed by highly determining an etch selection rate for the mold oxide layer  121 , the etching stop layer  120  and the bitline spacer  115  and by selectively dry etching only the capacitor storage node contact  117  exposed in the first aperture part  122 . The etching process to form the second aperture part can be appropriately formed to a depth of about 100 Å through about 3000 Å. In addition, if the capacitor storage node contact is formed of polysilicon, and when the capacitor storage node contact  117  is etched to form the second aperture part  125 , the polysilicon used as the etch mask when forming the first aperture part is removed together, thus eliminating the additional step of removing the etch mask when separating the capacitor storage node  123 .  
         [0038]     Referring to  FIG. 13 , a conductive layer for a formation of the capacitor storage node of square type is deposited on the semiconductor substrate having the first aperture part  122  and the second aperture part  125 . The conductive layer is preferably formed of a material such as amorphous silicon or polysilicon through a conventional technique such as a CVD process. Further, a residual conductive layer on the mold oxide layer is removed by a planarization process to form the capacitor storage node of square type. The planarization process may be a CMP (Chemical and Mechanical Polishing) process or an etch back process, or can employ an anisotropic etching process. The capacitor storage nodes  123   a  to  123   e  referred to in  FIG. 13  are cross-sectional views from the capacitor storage nodes  123   a  to  123   e  referred to  FIG. 7 . The capacitor storage node  123   a  to  123   e  is electrically contacted with a sidewall of the selectively etched storage node contact  117 .  
         [0039]     The capacitor storage node  123  of square type can be widely applied to a semiconductor memory device for a DRAM cell. Further, the capacitor storage node of square type can be formed by a box shape based on a solid stack structure, a cylinder type or a hemisphere(HSG) type, or others.  
         [0040]     According to this embodiment of the present invention, the following advantages can be provided in forming a capacitor storage node of square type.  
         [0041]     First, there is no need to perform a process of forming a contact through a buffer layer, as in the prior art where a precise photolithography and etching process is required in the process of forming the contact through use of the buffer layer. In addition, an etch mask and a storage node contact are formed of polysilicon, and in selectively etching the storage node contact, the etch mask is etched together, and thus the step of removing the etch mask in separating the capacitor storage node can be omitted. Therefore, the number of processes can be reduced.  
         [0042]     Second, the capacitor storage node may be formed in such a way that a lower face of the storage node is contacted with an upper part of the etched conductive region, because of the recess at an edge portion of upper portion of the interlayer insulation layer. Thus, an area of the storage node is extended by the contacted area. As a result, capacitance can be increased.  
         [0043]     Third, the capacitor storage node may be formed by a square type to increase a bottom critical dimension of the storage node, thus reducing the leaning phenomenon.  
         [0044]     Fourth, the capacitor storage node is formed being contacted with a sidewall through an aperture part formed in a storage node contact extending the contact area connected electrically, thus increasing process stability.  
         [0045]     It will be apparent to those skilled in the art that modifications and variations can be made in the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention cover any such modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. For instance, the storage node may be formed of variously varied type and material and the number of manufacturing processes may be added or reduced. Accordingly, these and other changes and modifications are seen to be within the true spirit and scope of the invention as defined by the appended claims.