Abstract:
Method and device for transmitting binary signals by means of digital self-synchronizing scramblers, the information of the storage elements used being utilized, in combination with that of the input signal, for detecting the degenerative condition of a long series of identical bits. 
     If the said condition is still existing after a number of consecutive clock periods, a change is made in it by inverting one bit of the input signal. 
     The detection and the inversion also take place at the receiving end, thus ensuring an unerring working of the system.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a method for transmitting binary signals by means of digital self-synchronising so-called scramblers. 
     Scramblers of this type are known from J.E. Savage: &#34;Some Simple Self-Synchronising Digital Data Scramblers&#34;, The Bell System Technical Journal 46 (February 1967) pp. 449-487. The scramblers are utilized in order to avoid long series of zeros or ones on the transmission path, in consequence of which a better clock extraction can be obtained, the chances of crosstalk and irregularities are reduced, and a considerable amount of secrecy can be achieved. Depending upon the input signal the known selfsynchronising scramblers may degenerate in certain states, id est, they stop continuing their function by transmitting an uninterrupted series of zeros (&#34;0&#34;) or ones (&#34;1&#34;) on the transmission path. 
     SUMMARY OF THE INVENTION 
     The invention provides a solution for the said problem by utilizing the information of the storage elements used and that of the input signal for detecting the so-called degenerative condition. If the said condition is maintained during a fixed number of consecutive clock periods, one bit of the input signal is inverted by means of logic circuits in consequence of which the degenerative condition comes to an end when the input signal remains otherwise unchanged. 
     The utilization of the method according to the invention yields excellent results, and it does not present serious difficulties even though there is a chance that the input signal changes at the very moment when a bit of the input signal is being inverted. With the aforesaid method there is an erroneous bit at the receiving end when descrambling has taken place, which bit is caused by the inversion at the transmitting end. The invention offers a solution in this case because of the fact that the degenerative condition detected at the transmitting end is also detected at the receiving end. Thus when the said condition is maintained during the said fixed number of consecutive clock periods, one bit of the output signal is similarly inverted by means of logic circuits, in consequence of which the original information is restored. 
     The invention also relates to a device for carrying out the method, which device comprises at the transmitting end a feedback shift register for producing a maximum length series. The storage elements of the shift register are connected to an OR-gate in such a way that by means of a second shift register connected to the output of this OR-gate, and after the abovementioned fixed number of clock periods, a degenerative condition can be detected with the help of another OR-gate connected to the second shift register. This other OR gate is connected on the one output side to an exclusive OR-gate at the input of the first mentioned shift register, and on the other output side to the parallel read input of the second shift register, which has such a read condition that only one bit of the input signal can be inverted. 
     At the receiving end the device comprises a shift register, the storage elements of which are each connected to an input of an exclusive OR-gate. These OR-gates on their other input sides are connected, via an exclusive OR-gate with one fixed input signal (&#34;1&#34;) and to the input of the shift register. The outputs of these OR-gates are connected to an AND-gate with an ignored output and which is capable of delivering a signal when ascertaining a degenerative condition in an input signal. This delurred signal is capable of controlling a second shift register in such a way that, after the fixed number of clock periods, a pulse can be delivered, via an OR-gate with an ignored output. This ignored output is connected to an exclusive OR-gate in the output of the first shift register and on the other side to the parallel read input of the second shift register, which has such a read condition that only one bit of the output signal can be inverted. 
    
    
     BRIEF DESCRIPTION OF THE VIEWS 
     The above mentioned and other features, objects and advantages, and a manner of attaining them are described more specifically below by reference to an embodiment of this invention shown in the accompanying drawings, wherein: 
     FIG. 1 shows a schematic block wiring diagram of prior art shift register scrambling device at the transmitting end, in which the invention is not utilized; 
     FIG. 2 is a schematic block wiring diagram of an associated prior art shift register descrambling device at the receiving end for the signals transmitted by the scrambling device in FIG. 1; 
     FIG. 3 is a schematic block wiring diagram of a device according to the invention at the transmitting end, and 
     FIG. 4 shows a schematic block wiring diagram of an associated device according to the invention at the receiving end for the signals transmitted by the device in FIG. 3. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     1. The Prior Art 
     FIG. 1 shows a shift register with an input C1 and an output A1, which register is formed by four storage elements 1, 2, 3 and 4, of which the outputs are W, X, Y and Z, respectively. The outputs Z and Y are coupled modulo-2 in an exclusive OR-gate 5, the output of which is connected to an input of the element 4. The output Z is coupled modulo-2 to the input C1 in an exclusive OR-gate 6. Clock pulses are delivered by way of a conductor K. 
     Table 1 shows on the left of the left-hand part the 15 code words for the case of a &#34;0&#34; input signal and on the left of the right hand part the 15 code words for the case of a &#34;1&#34; input signal. The output signal A1 at the output of the device according to FIG. 1 forms the input signal of the device according to FIG. 2. 
     FIG. 2 shows a shift register with an input A1 and an output C2, which register is formed by four storage elements 7, 8, 9 and 10, of which the outputs are indicated by S, T, U and V, respectively. The input A1 and the output S are coupled modulo-2 by means of an exclusive OR-gate 11, the output of which is coupled modulo-2 to the output V by means of an exclusive OR-gate 12. 
     The output signal C2 of the device according to FIG. 2 has to correspond with the input signal C1 of FIG. 1 with a shift of four clock periods. 
     Table 1 shows on the right of the left-hand part the 15 code words for the case of an output signal C2 = 0 and on the right of the right-hand part the 15 code words for the case of an output signal C2 = 1. 
     Table 2 shows on the left that if at the transmitting end the input signal changes from &#34;0&#34; into &#34;1&#34; after the 12th code word, a degenerative condition will occur. Now the signal A1 changes permanently into &#34;1&#34; as long as C1 remains &#34;1&#34;. From a mathematical point of view there is no error, but the object for which the circuit is utilized, viz. the interruption of long series of zeros or ones on the transmission path is now missed. Table 2 shows on the right that a degenerative condition will also occur if the signal C1 changes from &#34;1&#34; into &#34;0&#34; after the 11th code word. 
     2. Transmitter According to an object of this invention, the putting of an end to the degenerative condition, after the code word WXYZ = 0001 or WXYZ = 0000, occurs, during four consecutive clock periods (see top half of Table 2) is reached because the input signal C1 is inverted by means of an additional circuit in the next or fifth clock period. For this purpose the circuit at the transmitting end has been provided with: two exclusive OR-gates 13, 14, two OR-gates 15, 16, each having four inputs, and a 4-bit shift register 17 (see FIG. 3). These parts are connected as follows: The input signal V, as well as an ignored output of the OR gate 16 (via a connection T) are applied to the exclusive OR gate 13. The output of this OR-gate 13 is connected to an input of the OR gate 6. The two inputs of the OR gate 14 are connected in parallel to the two inputs of the OR-gate 6. The output of the OR-gate 14 is connected to an input of the OR-gate 15 by means of a connection M. 
     The outputs W, X and Y of the storage elements 1, 2 and 3 respectively are also connected to separate inputs of the OR-gate 15. By means of a connection N an output of OR gate 15 is connected to the shift register 17, of which four outputs are connected to four inputs of the OR gate 16. 
     
                                           TABLE 1__________________________________________________________________________C1  W X Y Z Al         S T U V C2  C1                       W X                          Y  Z A1                                 S T U V C2__________________________________________________________________________1 0 1 1 1 1 1           1 1 1 1 1 1 12 0 1 1 1 0 0 1         2 1 0 1 1 0 0       13 0 0 1 1 1 1 0 1       3 1 1 0 1 1 1       0                                       14 0 1 0 1 0 0 1 0 1     4 1 0 1 0 0 0       1                                       0                                       15 0 0 1 0 1 1 0 1 0 1 0 5 1 1 0 1 0 0       0                                       1                                       0                                       1 16 0 1 0 1 1 1 1 0 1 0 0 6 1 1 1 0 1 1       0                                       0                                       1                                       0 17 0 1 1 0 0 0 1 1 0 1 0 7 1 0 1 1 1 1       1                                       0                                       0                                       1 18 0 0 1 1 0 0 0 1 1 0 0 8 1 0 0 1 0 0       1                                       1                                       0                                       0 19 0 0 0 1 1 1 0 0 1 1 0 9 1 1 0 0 1 1       0                                       1                                       1                                       0 110  0 1 0 0 0 0 1 0 0 1 0 10                     1 0 1 0 1 1       1                                       0                                       1                                       1 111  0 0 1 0 0 0 0 1 0 0 0 11                     1 0 0 1 1 1       1                                       1                                       0                                       1 112  0 0 0 1 0 0 0 0 1 0 0 12                     1 0 0 0 0 0       1                                       1                                       1                                       0 113  0 0 0 0 1 1 0 0 0 1 0 13                     1 1 0 0 0 0       0                                       1                                       1                                       1 114  0 1 0 0 1 1 1 0 0 0 0 14                     1 1 1 0 0 0       0                                       0                                       1                                       1 115  0 1 1 0 1 1 1 1 0 0 0 15                     1 1 1 1 0 0       0                                       0                                       0                                       1 11 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1       0                                       0                                       0                                       0 12 0 1 1 1 0 0 1 1 1 1 0 2 1 0 1 1 0 0       1                                       0                                       0                                       0 13 0 0 1 1 1 1 0 1 1 1 0 3 1 1 0 1 1 1       0                                       1                                       0                                       0 14 0 1 0 1 0 0 1 0 1 1 0 4 1 0 1 0 0 0       1                                       0                                       1                                       0 15 0 0 1 0 1 1 0 1 0 1 0 5 1 1 0 1 0 0       0                                       1                                       0                                       1 1__________________________________________________________________________ 
    
     
                                           TABLE 2__________________________________________________________________________C1   W X Y Z A1          S T U V C2   C1 W X Y Z A1                                    S T U V C2__________________________________________________________________________10  0  1 0 0 0 0 1 0 0 1 0   9                       1  1 0 0 1 1 0 1 1 0 111  0  0 1 0 0 0 0 1 0 0 0  10                       1  0 1 0 1 1       1                                          0                                          1                                          1 112  0  0 0 1 0 0 0 0 1 0 0  11                       1  0 0 1 1 1       1                                          1                                          0                                          1 113  1  0 0 0 1 1 0 0 0 1 0  12                       0  0 0 0 0 0       1                                          1                                          1                                          0 113  1  0 0 0 1 1 1 0 0 0 0  12                       0  0 0 0 0 0       0                                          1                                          1                                          1 113  1  0 0 0 1 1 1 1 0 0 0  12                       0  0 0 0 0 0       0                                          0                                          1                                          1 113  1  0 0 0 1 1 1 1 1 0 0  12                       0  0 0 0 0 0       0                                          0                                          0                                          1 113  1→00 0 0 1 1 1 1 1 1 1  12                       0→1                          0 0 0 0 0       0                                          0                                          0                                          0 0 9  1  1 0 0 1 1 1 1 1 1 1  10                       0  1 0 0 0 0       0                                          0                                          0                                          0 010  1  0 1 0 1 1 1 1 1 1 1  11                       0  0 1 0 0 0       0                                          0                                          0                                          0 011  1  0 0 1 1 1 1 1 1 1 1  12                       0  0 0 1 0 0       0                                          0                                          0                                          0 012  1  0 0 0 0 0 1 1 1 1 0→1                     13                       0  0 0 0 1 1       0                                          0                                          0                                          0 1→013  1  1 0 0 0 0 0 1 1 1 1  14                       0  1 0 0 1 1       1                                          0                                          0                                          0 014  1  1 1 0 0 0 0 0 1 1 1  15                       0  1 1 0 1 1       1                                          1                                          0                                          0 015  1  1 1 1 0 0 0 0 0 1 1   1                       0  1 1 1 1 1       1                                          1                                          1                                          0 0 1  1  1 1 1 1 1 0 0 0 0 1   2                       0  1 1 1 0 0       1                                          1                                          1                                          1 0__________________________________________________________________________ This transmitter circuit works as follows. When the code word WXYZ = 0001 presents itself with a &#34;1&#34; as input signal V, T being = &#34;0&#34;, then M = V ⊕ T ⊕ Z = 1 ⊕ 0 ⊕ 1 = 0. All four of the inputs of the OR-gate 15 are now &#34;0&#34;, in consequence of which N = 0. At the next clock pulse the output P of the shift register 17 will become &#34;0&#34;. If this condition occurs during four consecutive clock periods, then output T will become = 1, so that at the fifth clock period the input signal will be inverted, because of the fact that the signal T now becomes &#34;1&#34;. If the input signal V is still (1,) the degenerative condition thereby comes to an end, which appears from Table 2. 
    
     If the code word WXYZ = 0000 presents itself with &#34;0&#34; as input signal at V, then output M = V ⊕ T ⊕ Z = 0. If this condition occurs during four consecutive clock periods, then outputs PQRS = 0000, after which outputs T becomes = &#34;1&#34; and the inversion of signal V will take place at the next clock period. 
     When outputs PQRS = 0000, the shift register 17 is put in the parallel read condition by means of an input U, in consequence of which outputs PQRS will become = 0001 at the next clock period and the inversion of the input 
     3. Receiver 
     Table 2 shows that the output signal C2 of the descrambler is retarded 4 clock periods with respect to the input signal A1 of the descrambler. In Table 2 the possible retardation of the transmission path is left out of consideration, so that the output signal A1 of the scrambler coincides with the input signal A1 of the descrambler. 
     In the receiving circuit the code words STUV = 1111 and STUV = 0000 indicate the two degenerative conditions. When an input signal &#34;1&#34; or &#34;0&#34;. One of these two degenerative conditions has presented itself during four consecutive clock periods, the inversion of the output signal C2 has to take place. For that purpose the circuit according to FIG. 2 has been provided with the following elements (FIG. 4): 6 exclusive OR-gates 18-23, an AND-gate 24 with an ignored output and four inputs, an OR-gate 25 with an ignored output, and four inputs and a 4-bit shift register 26. These elements are connected as follows: The inputs of the exclusive OR gates 19, 20, 21 and 22, respectively, are connected to the outputs STUV of the storage element 7, 8, 9 and 10. The other inputs of these gates are connected to the output of the exclusive OR-gate 23, of which one input is connected to the input A1, the other input being always &#34;1&#34;. 
     As the output signal C2 of the exclusive OR-gate 12 can exhibit several transitions per bit period, it is sampled at the right moment by means of a storage element 27. Thus a constant output signal DC2, which is retarded one clock period with respect to C2, is obtained per bit period. The exclusive OR-gate 18 serves to effect the possible inversion of the output signal C2. One input of the OR-gate 18 is connected to the OR-gate 25 as well as to the input for the parallel read condition of the shift register 26. The four outputs of the shift register 26 are connected to the four inputs of the OR-gate 25. The ignored output of the AND gate 24, which is connected to the outputs of the OR-gates 19, 20, 21 and 22, is connected to an input of the shift register 26. 
     The circuit works as follows: After one of the degenerative conditions of outputs STUV = 1111  or STUV = 0000 has presented itself during four consecutive clock periods, which condition is ascertained because of the fact that the outputs STUV are compared with the input signal A1 by means of the OR-gates 19, 20, 21 and 22, the following takes place: In the case of the code word STUV = 1111 with the input signal A1 = &#34;1&#34; all the input signals of the AND gate 24 are &#34;1&#34; and its output signal is &#34;0&#34;. If this condition occurs four clock periods at a stretch, all the inputs of the OR-gate 25 are &#34;0&#34;, in consequence of which the inversion of the output signal C2 is effected by means of the OR-gate 18. The same occurs when outputs STUV = 0000 with the input signal A1 = &#34;0&#34;. In this case too the output of the AND gate 24 = &#34;0&#34; during four periods at a stretch, similarly affects the shift register 26 to effect the OR-gates 25 and 18. 
     While there is described above the principles of this invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of this invention.