Abstract:
An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Description:
BACKGROUND 
       [0001]    For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. As semiconductor devices have become highly integrated, a MIM capacitor having a higher capacitance per unit of chip area is required. The MIM capacitor is widely used for applications such as an analog to digital (AD) converter, a RF device, a switching capacitor filter, and a CMOS image sensor (CIS). To meet the requirements of high integration, an integrated circuit of a semiconductor device has been proposed with a stacked MIM capacitor, which has a high capacitance per unit of chip area. 
         [0002]    In integrated circuit of the semiconductor device, thin film resistors (TFRs) are attractive components for high precision analog and mixed signal applications, and have been utilized in electronic circuits of many important technological applications. Special cares are required as integrating the TFRs into existing process flows of an integrated circuit. Generally, in fabricating a TFR in an integrated circuit, materials of the TFR are evaporated or sputtered onto a substrate and subsequently patterned and etched. As such, the TFR is embedded between the inter-metal dielectric (IMD) layers. The TFR needs an electrical connection. Therefore, two extra mask layers are required to form the TFR itself and to form the contact points of the TFR. 
         [0003]    As the semiconductor devices being required to perform multiple functions and become highly integrated, the stacked MIM capacitor and the TFR are often integrated in one integrated circuit of the semiconductor devices. However, as aforementioned, two extra mask layers are required in fabricating the TFR in the integrated circuit. Therefore, the cost of fabrication of an integrated circuit with both of the stacked MIM capacitor and the TFR is increased by additional masks for the TFR. Besides, process margin and the reliability of the integrated circuit produced are also limited by multiple deposition and dry/wet etch steps which are required to incorporate the TFR into the integrated circuit. Accordingly, improvements in structures and methods of forming the integrated circuit with both of the stacked MIM capacitor and the TFR continue to be sought. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
           [0005]      FIG. 1  is a schematic view of at least a portion of an integrated circuit according to various embodiments of the present disclosure. 
           [0006]      FIG. 2  is a schematic view of at least a portion of an integrated circuit according to various embodiments of the present disclosure. 
           [0007]      FIG. 3  is a schematic view of at least a portion of an integrated circuit according to various embodiments of the present disclosure. 
           [0008]      FIG. 4  is a schematic view of at least a portion of an integrated circuit in an intermediate stage of manufacture according to various embodiments of the present disclosure. 
           [0009]      FIG. 5  is schematic views of the integrated circuit shown in  FIG. 4  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0010]      FIG. 6  is schematic views of the integrated circuit shown in  FIG. 5  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0011]      FIG. 7  is schematic views of the integrated circuit shown in  FIG. 6  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0012]      FIG. 8  is schematic views of the integrated circuit shown in  FIG. 7  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0013]      FIG. 9  is a schematic view of the integrated circuit shown in  FIG. 8  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0014]      FIG. 10  is a schematic view of the integrated circuit shown in  FIG. 9  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0015]      FIG. 11  is a schematic view of the integrated circuit shown in  FIG. 10  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0016]      FIG. 12  is a schematic view of the integrated circuit shown in  FIG. 11  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0017]      FIG. 13  is a schematic view of the integrated circuit shown in  FIG. 12  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0018]      FIG. 14  is a schematic view of the integrated circuit shown in  FIG. 13  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0019]      FIG. 15  is a schematic view of the integrated circuit shown in  FIG. 14  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0020]      FIG. 16  is a schematic view of the integrated circuit shown in  FIG. 15  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0021]      FIG. 17  is a schematic view of the integrated circuit shown in  FIG. 16  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0022]      FIG. 18  is a schematic view of the integrated circuit shown in  FIG. 17  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
           [0023]      FIG. 19  is a schematic view of the integrated circuit shown in  FIG. 18  in a subsequent stage of manufacture according to various embodiments of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. 
         [0025]    The singular forms “a”, “an” and “the” used herein include plural referents unless the context clearly dictates otherwise. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are intended for illustration. 
         [0026]    Conventionally, it needs two extra masks and corresponding Litho/Etch processes in fabricating a TFR into an integrated circuit with a stack MIM capacitor. Therefore, the cost of fabrication of an integrated circuit with both of the stacked MIM capacitor and the TFR is increased, and process margin and the reliability of the integrated circuit produced are also limited. In this regard, an integrated circuit and a method of manufacturing the integrated circuit are provided according to various embodiments of the present disclosure. 
         [0027]      FIG. 1  is a schematic view of at least a portion of an integrated circuit according to various embodiments of the present disclosure. The integrated circuit includes a first capacitor  110 , a first dielectric layer  120 , a second capacitor  130 , at least one first via  140 , a thin film resistor  150 , a second dielectric layer  160 , and a plurality of second vias  170 . The first capacitor  110  has a capacitor bottom metal  112 , a capacitor top metal  114 , and an inter-electrode dielectric layer  116 . As illustrated in  FIG. 1 , in various embodiments of the present disclosure, the inter-electrode dielectric layer  116  of the first capacitor  110  is sandwiched by the capacitor bottom metal  112  and the capacitor top metal  114  of the first capacitor  110  to form a metal-insulator-metal (MIM) capacitor. The capacitor top metal  114  of the first capacitor  110  may be made of, for example, tantalum nitride (TaN), titanium nitride (TiN), aluminium-copper alloy (AlCu), or the combination thereof. In various embodiments of the present disclosure, the capacitor bottom metal  112  of the first capacitor  110  is a film lamination consisting of two titanium nitride (TiN) films, and an aluminium-copper alloy (AlCu) film which is sandwiched by the two TiN films. The inter-electrode dielectric layers of the first capacitor and the second capacitor are multi-layers structures consisting of a silicon oxide (SiO 2 ) film, a silicon nitride (Si x N y ) film, a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, or an aluminum oxide (Al 2 O 3 ) film. In various embodiments of the present disclosure, the area of the capacitor bottom metal  112  of the first capacitor  110  is larger than that of the capacitor top metal  114  of the first capacitor  110  for forming the electrical connection of the capacitor bottom metal  112  conveniently. 
         [0028]    As illustrated in  FIG. 1 , the first dielectric layer  120  covers the first capacitor  110 . The first dielectric layer  120  may be formed of silicon oxide (SiO 2 ), silicon nitride (Si x N y ), or the combination thereof. In advanced technologies having smaller critical dimensions, a variety of inter-level dielectric materials may be used, such as medium k dielectric materials, low-k dielectric materials having k less than 3.5, or ELK dielectric materials having a dielectric constant k less than 3.0. For example, inter-level dielectric materials such as undoped silica glass (USG), phosphor doped silicate glass (PSG), fluorine doped silicate glass (FSG), a boron doped silicate glass (BSG) layer, or a boron phosphorous-doped silicate glass (BPSG) layer may be used. 
         [0029]    Referring to  FIG. 1 , the second capacitor  130  is disposed on the first dielectric layer  120 , and the second capacitor  130  also has a capacitor bottom metal  132 , a capacitor top metal  134 , and an inter-electrode dielectric layer  136 . In various embodiments of the present disclosure, the inter-electrode dielectric layer  136  of the second capacitor  130  is sandwiched by the capacitor bottom metal  132  and the capacitor top metal  134  of the second capacitor  130  to form a metal-insulator-metal (MIM) capacitor. The capacitor top metal  134  of the second capacitor  130  is made of tantalum nitride (TaN), titanium nitride (TiN), aluminium-copper alloy (AlCu), or the combination thereof. At least one first via  140  is disposed in the first dielectric layer  120 , and electrically connected to the capacitor top metal  114  of the first capacitor  110  and the capacitor bottom metal  132  of the second capacitor  130 . The first via  140  is made of conductive materials to offer an electrical connection between the first capacitor  110  and the second capacitor  130  which are disposed in different levels. In various embodiments of the present disclosure, the first via  140  is made of copper. Accordingly, two metal-insulator-metal (MIM) capacitors, the first capacitor  110  and the second capacitor  130  are electrically connected in series through the first via  140 , and can be regarded as a stacked metal-insulator-metal (MIM) capacitor. Therefore, the density of capacitors in the integrated circuit is increased without requiring an excessive amount of surface area of the semiconductor substrate  100 . 
         [0030]    As illustrated in  FIG. 1 , the thin film resistor  150  is disposed on the first dielectric layer  120 . It should be noticed that the thin film resistor  150  and the capacitor bottom metal  132  of the second capacitor  130  are substantially at the same layer, which is disposed on the first dielectric layer  120 . In addition, the material of the capacitor bottom metal  132  of the second capacitor  130  is substantially the same as the material of the thin film resistor  150 . Accordingly, the thin film resistor  150  and the capacitor bottom metal  132  of the second capacitor  130  can be fabricated in the same step. In other words, the fabrication of the thin film resistor  150  can be integrated into the fabrication of the capacitor bottom metal  132  of the second capacitor  130 , and therefore the cost of fabricating an integrated circuit with both of a stacked MIM capacitor and a thin film resistor is reduced. In various embodiments of the present disclosure, the capacitor bottom metal  132  of the second capacitor  130  and the thin film resistor  150  are made of tantalum nitride (TaN), titanium nitride (TiN), silicon-chrome (SiCr), tantalum, or the combination thereof. 
         [0031]    As shown in  FIG. 1 , the second dielectric layer  160  is disposed on the first dielectric layer  120  and covering the second capacitor  130  and the thin film resistor  150 . The second dielectric layer  160  may be formed of silicon oxide (SiO 2 ), silicon nitride (Si x N y ), or the combination thereof. In advanced technologies having smaller critical dimensions, a variety of inter-level dielectric materials may be used, such as medium k dielectric materials, low-k dielectric materials having k less than 3.5, or ELK dielectric materials having a dielectric constant k less than 3.0. For example, inter-level dielectric materials such as undoped silica glass (USG), phosphor doped silicate glass (PSG), fluorine doped silicate glass (FSG), a boron doped silicate glass (BSG) layer, or a boron phosphorous-doped silicate glass (BPSG) layer may be used. As illustrated in  FIG. 1 , the plurality of second vias  170  is disposed in the second dielectric layer  160 , and respectively connected to the capacitor top metal  134  of the second capacitor  130  and the thin film resistor  150 . The plurality of second vias  170  is made of conductive materials to offer an electrical connection between different levels. In various embodiments of the present disclosure, the plurality of second vias  170  is made of aluminum-copper alloy (AlCu). As shown in  FIG. 1 , some second vias  170  are electrically connected to the capacitor top metal  134  of the second capacitor  130 ; other second vias  170  are electrically connected to the thin film resistor  150 . The plurality of second vias  170  offers respective electrical connecting paths of the capacitor top metal  134  of the second capacitor  130  and the thin film resistor  150 . The second vias  170 , which are electrically connected to the capacitor top metal  134  of the second capacitor  130 , offer an electrical connecting path for the capacitor top metal  134  of the second capacitor  130 ; Other second vias  170 , which are electrically connected to the thin film resistor  150 , offer an electrical connecting path for the thin film resistor  150 . Therefore, the electrically conductive path of the thin film resistor  150  is established. For example, a signal current may flow in through the second via  170  on one side of the thin film resistor  150 , then flow to the thin film resistor  150 , and finally flow out through the second via  170  on another side of the thin film resistor  150 . 
         [0032]    Also shown in  FIG. 1 , in various embodiments of the present disclosure, the integrated circuit further includes at least one third via  180  is disposed in the first dielectric layer  120  and the second dielectric layer  160 , and electrically connected to the capacitor bottom metal  112  of the first capacitor  110 . The third via  180  is made of conductive materials to offer an electrical connection from the capacitor bottom metal  112  of the first capacitor  110  to a higher level. In various embodiments of the present disclosure, the third via  180  includes an eighth via  182 , an interlayer connection  184 , and a ninth via  186 . The eighth via  182  is disposed in the first dielectric layer  120  and connected to the capacitor bottom metal  112  of the first capacitor  110 . The interlayer connection  184  is disposed on the first dielectric layer  120  and connected to the eighth via  182 . The ninth via  186  is disposed in the second layer  160  and connected to the interlayer connection  184 . Therefore, the electrically conductive path of the stacked metal-insulator-metal (MIM) capacitor, which includes the first capacitor  110  and the second capacitor  130 , is established. For example, a signal current may flow in through the second via  170 , the second capacitor  130 , the first via  140 , the first capacitor  110 , the eighth via  182 , the interlayer connection  184 , and flow out through the ninth via  186 . 
         [0033]    Also illustrated in  FIG. 1 , in various embodiments of the present disclosure, the integrated circuit further includes a plurality of bonding pads  280  disposed on the second dielectric layer  160 . Wherein at least one of the plurality of bonding pads  280  is electrically connected to the capacitor bottom metal  112  of the first capacitor  110 , at least another one of the plurality of bonding pads  280  is electrically connected to the capacitor top metal  134  of the second capacitor  130 , and at least another two of the plurality of bonding pads  280  are electrically connected to the thin film resistor  150 . The plurality of bonding pads  280  is made of conductive materials such as metals and metal alloys. As shown in  FIG. 1 , one bonding pad  280  connected to the third via  180  is electrically connected to the capacitor bottom metal  112  of the first capacitor  110 , another one bonding pad  280  connected to the second vias  170  is electrically connected to the capacitor top metal  134  of the second capacitor  130 . These two bonding pads  280  can be respectively regarded as an input or an output of the stacked metal-insulator-metal (MIM) capacitor, which includes the first capacitor  110  and the second capacitor  130 . Besides, another two bonding pads  280  connected to the second vias  170  are electrically connected to the thin film resistor  150 . These two bonding pads  280  can be respectively regarded as an input or an output of the thin film resistor  150 . All of the plurality of bonding pads  280  may be further formed a bonding wire, a metal clip or a bump to electrically connect to a circuit board or other semiconductor chips. 
         [0034]      FIG. 2  is a schematic view of at least a portion of an integrated circuit according to various embodiments of the present disclosure. The integrated circuit includes a first capacitor  110 , a first dielectric layer  120 , a second capacitor  130 , at least one first via  140 , a thin film resistor  150 , a second dielectric layer  160 , and a plurality of second vias  170 . The positions of above elements and the connections between them are similar to those described above, and therefore the details are omitted here. The differences between the integrated circuit illustrated in  FIG. 2  and that in  FIG. 1  is that the integrated circuit illustrated in  FIG. 2  further includes a first interlayer metal pad  190 . The first interlayer metal pad  190  is disposed between the capacitor bottom metal  132  of the second capacitor  130  and the plurality of first vias  140 . The first interlayer metal pad  190  is made of conductive materials. In various embodiments of the present disclosure, the first interlayer metal pad  190  is made of copper. As shown in  FIG. 2 , the first interlayer metal pad  190  connected to the capacitor bottom metal  132  further reduces the resistance of the capacitor bottom metal  132  of the second capacitor  130 , and therefore increases the quality factor (Q) of the second capacitor  130 . Accordingly, the stacked metal-insulator-metal (MIM) capacitor, which includes the first capacitor  110  and the second capacitor  130 , can provide higher quality factor characteristics when being operated in high frequency. 
         [0035]      FIG. 3  is a schematic view of at least a portion of an integrated circuit according to various embodiments of the present disclosure. The integrated circuit includes a first capacitor  110 , a first dielectric layer  120 , a second capacitor  130 , at least one first via  140 , a thin film resistor  150 , a second dielectric layer  160 , and a plurality of second vias  170 . The positions of above elements and the connections between them are similar to those described above, and therefore the details are omitted here. The differences between the integrated circuit illustrated in  FIG. 3  and that in  FIG. 2  is that the integrated circuit illustrated in  FIG. 3  further includes a third capacitor  210 , a second interlayer metal pad  220 , at least one fourth via  230 , and at least one fifth via  240 . The third capacitor  210  is disposed on the first dielectric layer  120 . The third capacitor  210  has a capacitor bottom metal  212 , a capacitor top metal  214 , and an inter-electrode dielectric layer  216 . In various embodiments of the present disclosure, the inter-electrode dielectric layer  216  of the third capacitor  210  is sandwiched by the capacitor bottom metal  212  and the capacitor top metal  214  of the second capacitor  210 . The second interlayer metal pad  220  is disposed below the capacitor bottom metal  212  of the third capacitor  210  and electrically contacted to the capacitor bottom metal  212  of the third capacitor  210 . In various embodiments of the present disclosure, the first interlayer metal pad  190 , the second interlayer metal pad  220 , and the first via  140  are made of copper. The fourth via  230  is disposed in the second dielectric layer  160  and electrically connected to the capacitor top metal  214  of the third capacitor  210 . The fifth via  240  is disposed in the second dielectric layer  160  and electrically connected to the capacitor bottom metal  212  of the third capacitor  210 . As shown in  FIG. 3 , the second interlayer metal pad  220  connected to the capacitor bottom metal  132  reduces the resistance of the capacitor bottom metal  212  of the third capacitor  210 , and therefore increases the quality factor (Q) of the third capacitor  130 . Accordingly, the third capacitor  130  can provide high-Q characteristics when being operated in high frequency. Besides, another two bonding pads  280 , which are respectively connected to the fourth via  230  and the fifth via  240 , are electrically connected to the third capacitor  210 . These two bonding pads  280  can be respectively regarded as an input or an output of the third capacitor  210 . Similarly, the bonding pads  280  may be further formed a bonding wire, a metal clip or a bump to electrically connect to a circuit board or other semiconductor chips. 
         [0036]    It should be noticed that the capacitor bottom metal  212 , the capacitor top metal  214 , and the inter-electrode dielectric layer  216  of the third capacitor  210  are respectively at the same layers as those of the second capacitor  130 . In other words, the capacitor bottom metal  212  of the third capacitor  210  and the capacitor bottom metal  132  of the second capacitor  130  are substantially at the same layer; the top metal  214  of the third capacitor  210  and the capacitor top metal  134  of the second capacitor  130  are substantially at the same layer; the inter-electrode dielectric layer  216  of the third capacitor  210  and the inter-electrode dielectric layer  136  of the second capacitor  130  are substantially at the same layer. Therefore, the third capacitor  210  can be simultaneously fabricated when the second capacitor  130  is fabricated. In other words, the stacked MIM capacitor (the first capacitor  110  and the second capacitor  130 ), the high-Q MIM capacitor (the third capacitor  210 ), and the thin film resistor  150  can be fabricated in one integrated circuit at the same time, and the cost of manufacturing the integrated circuit with multi-functions (the stacked metal-insulator-metal (MIM) capacitor, the high-Q MIM capacitor, and the thin film resistor  150 ) can be further reduced. 
         [0037]    Also illustrated in  FIG. 3 , in various embodiments of the present disclosure, the integrated circuit further includes a fourth capacitor  250 , at least one sixth via  260 , and at least one seventh via  270 . The fourth capacitor  250  is disposed on the first dielectric layer  120 . The fourth capacitor  250  has a capacitor bottom metal  252 , a capacitor top metal  254 , and an inter-electrode dielectric layer  256 . The sixth via  260  is disposed in the second dielectric layer  160  and is electrically connected to the capacitor top metal  254  of the fourth capacitor  250 . The seventh via  270  is disposed in the second dielectric layer  160  and is electrically connected to the capacitor bottom metal  252  of the fourth capacitor  250 . As shown in  FIG. 3 , since there is not an interlayer metal pad connected to the capacitor bottom metal  252 , the fabrication of the fourth capacitor  250  is independent of the fabrication of interlayer metal pad, and therefore reduce the risk of mismatch which may caused by the process variation of the fabrication of interlayer metal pad. Accordingly, the third capacitor  130  can provide high-match characteristics. Besides, another two bonding pads  280 , which are respectively connected to the sixth via  260  and the seventh via  270 , are electrically connected to the fourth capacitor  250 . These two bonding pads  280  can be respectively regarded as an input or an output of the fourth capacitor  250 . Similarly, the bonding pads  280  may also be further formed a bonding wire, a metal clip or a bump to electrically connect to a circuit board or other semiconductor chips. 
         [0038]    It should be noticed that the capacitor bottom metal  252 , the capacitor top metal  254 , and the inter-electrode dielectric layer  256  of the fourth capacitor  250  are respectively at the same layers as those of the second capacitor  130 . In other words, the capacitor bottom metal  252  of the fourth capacitor  250  and the capacitor bottom metal  132  of the second capacitor  130  are substantially at the same layer; the top metal  254  of the fourth capacitor  250  and the capacitor top metal  134  of the second capacitor  130  are substantially at the same layer; the inter-electrode dielectric layer  256  of the fourth capacitor  250  and the inter-electrode dielectric layer  136  of the second capacitor  130  are substantially at the same layer. Therefore, the fourth capacitor  250  can be simultaneously fabricated when the second capacitor  130  is fabricated. In other words, the stacked MIM capacitor (the first capacitor  110  and the second capacitor  130 ), the high-match MIM capacitor (the fourth capacitor  250 ), and the thin film resistor  150  can be fabricated in one integrated circuit at the same time. Furthermore, in various embodiments of the present disclosure, the stacked MIM capacitor (the first capacitor  110  and the second capacitor  130 ), the high-Q MIM capacitor (the third capacitor  210 ), the high-match MIM capacitor (the fourth capacitor  250 ), and the thin film resistor  150  can be fabricated in one integrated circuit at the same time. Accordingly, the cost of manufacturing the integrated circuit with multi-functions (the stacked metal-insulator-metal (MIM) capacitor, the high-Q MIM capacitor, the high-match MIM capacitor, and the thin film resistor  150 ) can be further reduced. 
         [0039]    A method for fabricating an integrated circuit according to various embodiments of the present disclosure will now be described in conjunction with  FIG. 4-17 .  FIG. 4  is a schematic view of at least a portion of an integrated circuit in an intermediate stage of manufacture according to various embodiments of the present disclosure. A first film lamination  310  including a capacitor bottom metal film  312 , an inter-electrode dielectric film  316 , and a capacitor top metal film  314  is formed on a semiconductor substrate  100 . The first film lamination  310  may be formed by sequentially depositing the capacitor bottom metal film  312 , the inter-electrode dielectric film  316 , and the capacitor top metal film  314 . The capacitor bottom metal film  312 , the inter-electrode dielectric film  316 , and the capacitor top metal film  314  may be respectively formed by suitable processes, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, PLD, other suitable techniques, or combinations thereof. In various embodiments of the present disclosure, the capacitor bottom metal film  312  is a film lamination consisting of two titanium nitride (TiN) films and an aluminum-copper alloy (AlCu) film which is sandwiched by the two TiN films. In various embodiments of the present disclosure, the inter-electrode dielectric film  316  is a multi-layers structure consisting of a silicon oxide (SiO 2 ) film, a silicon nitride (Si x N y ) film, a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, or an aluminum oxide (Al 2 O 3 ) film. 
         [0040]      FIGS. 5-8  are schematic views of the integrated circuit shown in  FIG. 4  in a subsequent stage of manufacture according to various embodiments of the present disclosure. The first film lamination  310  is patterned to form a first capacitor  110  having a capacitor bottom metal  112 , an inter-electrode dielectric layer  116 , and a capacitor top metal  114 . As illustrated in  FIG. 5 , a photo resist mask  320  may be formed on the capacitor top metal film  314  to delineate where the capacitor top metal  114  is desired. The capacitor top metal film  314  is then etched with a suitable etchant. The photo resist mask  320  is then stripped, and the capacitor top metal film  314  is formed as shown in  FIG. 6 . As illustrated in  FIG. 7 , another photo resist mask  330  may be formed on the capacitor top metal film  314 , the capacitor bottom metal film  312 , and the inter-electrode dielectric film  316  to delineate where the capacitor bottom metal  112  and the inter-electrode dielectric layer  116  are desired. The capacitor bottom metal film  312  and the inter-electrode dielectric film  316  are both etched with a suitable etchant. The photo resist mask  330  is then stripped, and the capacitor bottom metal  112  and the inter-electrode dielectric layer  116  are formed as shown in  FIG. 8 . It should be noticed that the capacitor bottom metal film  312  remains larger area than that of the capacitor top metal film  314  to conveniently form electrical connections of the capacitor bottom metal  112  in the following steps. 
         [0041]      FIG. 9  is a schematic view of the integrated circuit shown in  FIG. 8  in a subsequent stage of manufacture according to various embodiments of the present disclosure. A first dielectric layer  120  is deposited to cover the first capacitor  110 . The first dielectric layer  120  may be formed by a suitable process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, PLD, other suitable techniques, or combinations thereof. The first dielectric layer  120  may be formed of silicon oxide (SiO 2 ), silicon nitride (Si x N y ), or the combination thereof. In advanced technologies having smaller critical dimensions, a variety of inter-level dielectric materials may be used, such as medium k dielectric materials, low-k dielectric materials having k less than 3.5, or ELK dielectric materials having a dielectric constant k less than 3.0. For example, inter-level dielectric materials such as undoped silica glass (USG), phosphor doped silicate glass (PSG), fluorine doped silicate glass (FSG), a boron doped silicate glass (BSG) layer, or a boron phosphorous-doped silicate glass (BPSG) layer may be used. At least one first via  140  and at least one eighth via  182  penetrating the first dielectric layer  120  are formed. The first via  140  is electrically connected to the capacitor top metal  114  of the first capacitor  110 . The eighth via  182  is electrically connected to the capacitor bottom metal  112  of the first capacitor  110 . As illustrated in  FIG. 10 , in various embodiments of the present disclosure, at least one first interlayer metal pad  190  is formed to electrically connect to the first via  140 . The first interlayer metal pad  190  is predetermined to electrically connect to a capacitor bottom metal film of a second film lamination formed in the following steps. Also shown in  FIG. 10 , in various embodiments of the present disclosure, at least one second interlayer metal pad  220  is also formed to be predetermined to electrically connect to a capacitor bottom metal film of a second film lamination formed in the following steps. The difference between the second interlayer metal pad  220  and the first interlayer metal pad  190  is that the second interlayer metal pad  220  is not electrically connected to the first via  140 , but the first interlayer metal pad  190  is. 
         [0042]      FIG. 11  is a schematic view of the integrated circuit shown in  FIG. 10  in a subsequent stage of manufacture according to various embodiments of the present disclosure. A second film lamination  340  including a capacitor bottom metal film  342 , an inter-electrode dielectric film  346 , and a capacitor top metal film  344  is formed on the first dielectric layer  120 . The second film lamination  340  may be formed by sequentially depositing the capacitor bottom metal film  342 , the inter-electrode dielectric film  346 , and the capacitor top metal film  344 . The capacitor bottom metal film  342 , the inter-electrode dielectric film  346 , and the capacitor top metal film  344  may be respectively formed by suitable processes, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, PLD, other suitable techniques, or combinations thereof. In various embodiments of the present disclosure, the capacitor bottom metal film  312  is made of tantalum nitride (TaN), titanium nitride (TiN), silicon-chrome (SiCr), tantalum, or the combination thereof. In various embodiments of the present disclosure, the inter-electrode dielectric film  346  is a multi-layers structure consisting of a silicon oxide (SiO 2 ) film, a silicon nitride (Si x N y ) film, a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, or an aluminum oxide (Al 2 O 3 ) film. In various embodiments of the present disclosure, the capacitor top metal film  344  is made of tantalum nitride (TaN), titanium nitride (TiN), aluminium-copper alloy (AlCu), or the combination thereof. 
         [0043]      FIGS. 12-15  are schematic views of the integrated circuit shown in  FIG. 11  in a subsequent stage of manufacture according to various embodiments of the present disclosure. As illustrated in  FIG. 12-15 , the second film lamination  340  is patterned to form a second capacitor  130  and a thin film resistor  150 . The second capacitor  130  has a capacitor bottom metal  132 , an inter-electrode dielectric layer  136 , and a capacitor top metal  134 . In various embodiments of the present disclosure, the second film lamination  340  is patterned to further form a third capacitor  210 . The third capacitor  210  has a capacitor bottom metal  212 , an inter-electrode dielectric layer  216 , and a capacitor top metal  214 . In various embodiments of the present disclosure, the second film lamination  340  is patterned to further form a fourth capacitor  250 . The fourth capacitor  250  has a capacitor bottom metal  252 , an inter-electrode dielectric layer  256 , and a capacitor top metal  254 . As illustrated in  FIG. 12 , photo resist masks  350  may be formed on the capacitor top metal film  344  to delineate where the capacitor top metal  134  of the second capacitor  130 , the capacitor top metal  214  of the third capacitor  210 , and the capacitor top metal  254  of the fourth capacitor  250  are desired. The capacitor top metal film  344  is then etched with a suitable etchant. The photo resist masks  350  is then stripped, and the capacitor top metal film  134  of the second capacitor  130 , the capacitor top metal  214  of the third capacitor  210 , and the capacitor top metal  254  of the fourth capacitor  250  are formed as shown in  FIG. 13 . As illustrated in  FIG. 14 , another photo resist mask  360  may be formed on the inter-electrode dielectric film  346 , the capacitor top metal film  134  of the second capacitor  130 , the capacitor top metal  214  of the third capacitor  210 , and the capacitor top metal  254  to delineate where the capacitor bottom metals and the inter-electrode dielectric layers are desired. The capacitor bottom metal film  342  and the inter-electrode dielectric film  346  are both etched with a suitable etchant. The photo resist mask  360  is then stripped, and the capacitor bottom metals  132 ,  212 , and  252  of the second capacitor  130 , the third capacitor  210 , and the fourth capacitor  250  and the inter-electrode dielectric layers  136 ,  216 , and  256  of the second capacitor  130 , the third capacitor  210 , and the fourth capacitor  250  are formed as shown in  FIG. 15 . It should be noticed that the capacitor bottom metal film  342  remain larger area than those of the capacitor top metal films  344  to conveniently form electrical connections of the capacitor bottom metal  132  of the second capacitor  130 , the capacitor bottom metal  212  of the third capacitor  210 , and the capacitor bottom metal  252  of the fourth capacitor  250  in the following steps. 
         [0044]      FIG. 16  is a schematic view of the integrated circuit shown in  FIG. 15  in a subsequent stage of manufacture according to various embodiments of the present disclosure. A second dielectric layer  160  is deposited to cover the first dielectric layer  120 , the second capacitor  130 , and the thin film resistor  150 . In some embodiments of the present disclosure, the second dielectric layer  160  is deposited to cover the first dielectric layer  120 , the second capacitor  130 , the third capacitor  210 , and the thin film resistor  150 . In other some embodiments of the present disclosure, the second dielectric layer  160  is deposited to cover the first dielectric layer  120 , the second capacitor  130 , the third capacitor  210 , the fourth capacitor  250 , and the thin film resistor  150 . The processes of forming the second dielectric layer  160  and the materials of the second dielectric layer  160  are similar to those of the first dielectric layer  120 , and therefore the details are omitted here. A plurality of second vias  170  and at least one ninth via  186  penetrating the second dielectric layer  160  are formed. The plurality of second vias  170  is electrically connected to the capacitor top metal  134  of the second capacitor  130  and the thin film resistor  150  respectively. The ninth via  186  is electrically connected to the capacitor bottom metal  112  of the first capacitor  110 . In various embodiments of the present disclosure, at least one fourth via  230  penetrating the second dielectric layer  160  is formed. The fourth via  230  is connected to the capacitor top metal  214  of the third capacitor  210 . And at least one fifth via  240  penetrating the second dielectric layer  160  is formed. The fifth via  240  is connected to the capacitor bottom metal  212  of the third capacitor  210 . In various embodiments of the present disclosure, forming at least one sixth via  260  penetrating the second dielectric layer  160  is formed. The sixth via  260  is electrically connected to the capacitor top metal  254  of the fourth capacitor  250 . And at least one seventh via  270  penetrating the second dielectric layer  160  is formed. The seventh via  270  is electrically connected to the capacitor bottom metal  252  of the fourth capacitor  250 . Aforementioned vias  170 ,  186 ,  230 ,  240 ,  260 , and  270  may be formed by litho-etching the second dielectric layer  160  to produce corresponding openings in the second dielectric layer  160 . And the corresponding openings are fulfilled with a conductive materials such as metals or metal alloys. 
         [0045]      FIGS. 17-19  are schematic views of the integrated circuit shown in  FIG. 16  in a subsequent stage of manufacture according to various embodiments of the present disclosure. As shown in  FIG. 19 , a plurality of bonding pads  390  disposed on the second dielectric layer  160  is formed. At least one of the plurality of bonding pads  390  is electrically connected to the capacitor bottom metal  112  of the first capacitor  110 . At least another one of the plurality of bonding pads  390  is electrically connected to the capacitor top metal  134  of the second capacitor  130 , and at least two of the plurality of bonding pads  390  are electrically connected to the thin film resistor  150 . In various embodiments of the present disclosure, at least another one of the plurality of bonding pads  390  is electrically connected to the capacitor bottom metal  212  of the third capacitor  210 , and at least another one of the plurality of bonding pads  390  is electrically connected to the capacitor top metal  214  of the third capacitor  210 . In various embodiments of the present disclosure, at least another one of the plurality of bonding pads  390  is electrically connected to the capacitor bottom metal  252  of the third capacitor  250 , and at least another one of the plurality of bonding pads  390  is electrically connected to the capacitor top metal  254  of the third capacitor  250 . The plurality of bonding pads  390  may be formed as illustrated in  FIG. 17 , a conductive layer  370  is formed on the second dielectric layer  160 . The conductive layer  370  is electrically connected to aforementioned vias  170 ,  186 ,  230 ,  240 ,  260 , and  270 . As illustrated in  FIG. 18 , a photo resist mask  380  may be formed on the conductive layer  370  to delineate where the plurality of bonding pads  390  is desired. The conductive layer  370  is then etched with a suitable etchant. The photo resist mask  380  is then stripped, and the plurality of bonding pads  390  is formed as shown in  FIG. 19 . 
         [0046]    The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.