Abstract:
In a coherent optical receiver of an optical communications network, a method of recovering a clock signal from a high speed optical signal received through an optical link. A set of compensation vectors are adaptively computed for compensating Inter-symbol Interference (ISI) due to at least polarization impairments of the optical signal. A channel delay is estimated based on the computed compensation vectors. The estimated channel delay is subtracted from the computed compensation vectors to generate corresponding modified compensation vectors. Finally, the modified compensation vectors are used to derive a recovered clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This is the first application filed in respect of the present invention. 
       MICROFICHE APPENDIX 
       [0002]    Not Applicable. 
       TECHNICAL FIELD 
       [0003]    The present invention relates to clock recovery in optical communications systems, and more particularly to clock recovery with channel coefficients. 
       BACKGROUND OF THE INVENTION 
       [0004]    In high-speed optical communications networks, optical signals received through an optical fiber link suffer inter-symbol interference (ISI) due to, among other things, chromatic dispersion (CD) and polarization mode dispersion (PMD). In the presence of severe inter-symbol interference (ISI), clock recovery using conventional clock phase detector algorithms can fail. For example for the optical channel, chromatic dispersion (CD) and polarization mode dispersion (PMD) can dramatically reduce the clock phase sensitivity such that the phase lock condition is lost. An approach for deriving clock phase after signal equalization (e.g. for distortion compensation) is known from K. H. Mueller and M. Muller, “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Trans. Comm., Vol.COM-24, No. 5, May 1976. 
         [0005]      FIG. 1  illustrates a coherent optical receiver known, for example, from Applicant&#39;s co-pending U.S. patent application Ser. No. 11/551,367 filed Oct. 20, 2006, and U.S. patent applications Ser. Nos. 11/315,342 and 11/315,345, both of which were filed Dec. 23, 2005. The entire contents of U.S. patent applications Ser. Nos. 11/551,367, 11/315,342 and 11/315,345 are incorporated herein by reference. 
         [0006]    As may be seen in  FIG. 1 , an inbound optical signal is received through an optical link  2 , split into orthogonal received polarizations by a Polarization Beam Splitter  4 , and then mixed with a Local Oscillator (LO) signal  6  by a conventional 90° optical hybrid  8 . The composite optical signals emerging from the optical hybrid  8  are supplied to respective photodetectors  10 , which generate corresponding analog electrical signals. The photodetector signals are sampled by respective Analog-to-Digital (A/D) converters  12  to yield raw multi-bit digital signals I X , Q X  and I Y , Q Y  corresponding to In-phase (I) and Quadrature (Q) components of each of the received polarizations. 
         [0007]    From the A/D converter  12  block, the respective n-bit signals I X , Q X  and I Y , Q Y  of each received polarization are supplied to an agile signal equalizer  14  which operates to compensate chromatic dispersion and polarization rotation impairments. In general, the signal equalizer  14  comprises a respective dispersion compensation block  16  for each of the X- and Y-polarizations, and a polarization compensation block  18 . The dispersion compensation blocks  16  have a width sufficient to enable compensation of moderate-to-severe dispersion (e.g. on the order of 10000 ps/nm) based on a set of dispersion compensation coefficients  20 , and generate respective intermediate vectors {T A   X } and {T A   Y }. These intermediate vectors {T A   X } and {T A   Y } are then input to the polarization compensation block  18 , which uses a set of polarization compensation vectors H XX , H XY , H YY  and H YX  to impose a phase rotation which compensates polarization impairments of the optical signal, and so de-convolve the transmitted symbols from the raw digital sample streams I X , Q X , and I Y , Q Y  generated by the A/D converters  12 . The compensated signals  22  output from the equalizer  14  represent multi-bit estimates X′(n) and Y′(n) of the symbols encoded on each transmitted polarization of the received optical signal. These symbol estimates  22  X′(n), Y′(n), are supplied to a carrier recovery block  24  for LO frequency control, symbol detection and data recovery, such as described in Applicant&#39;s co-pending U.S. patent application Ser. No. 11/366,392 filed Mar. 2, 2006. 
         [0008]    As shown in  FIG. 1 , a Least Mean Squares (LMS) update block  26  computes the polarization compensation vectors H XX , H XY , H YY  and H YX  based on the intermediate vectors {T A   X } and {T A   Y }, as well as symbol phase and error information received from the carrier recovery block  24 . As described in Applicant&#39;s co-pending U.S. patent application Ser. No. 11/551,367, the polarization compensation vectors H XX , H XY , H YY  and H YX  are updated at a sufficiently high rate to enable tracking, and therefore compensation, of polarization rotation transients at speeds on the order of 50 kHz. 
         [0009]    In the receiver of  FIG. 1 , clock recovery can be performed as described in Applicant&#39;s co-pending U.S. patent applications Ser. Nos. 11/315,342 and 11/315,345. Thus, with reference to  FIG. 2 , respective Upper Side Band (USB) and Lower Side Band (LSB) signals for each polarization are tapped from the output of the dispersion compensators  16  (i.e. the intermediate vectors {T A   X } and {T A   Y }) and supplied to a clock recovery circuit  28  comprising an optimization block  30 , a phase detector  32 , loop filter  34  and an Voltage controlled Oscillator (VCO)  36 . The optimization block  30  implements a polarization compensation function, based on a set of filter coefficients. In the systems of U.S. patent applications Ser. Nos. 11/315,342 and 11/315,345, these filter coefficients are angle θ(n+1) and phase θ(n+1) filter coefficients generated by a coefficient calculator (not shown). However, because both the optimization block  28  and the polarization compensator  18  perform similar functions, the polarization compensation vectors H XX , H XY , H YY  and H YX  computed by the LMS update block  26  can be used for this purpose, as shown in  FIG. 2 . The signal appearing at the output of the optimization block  30  is then supplied to the clock phase detector  32  and the phase detection result is passed to the loop filter  34 , which supplies respective control signals to coarse (C) and fine (F) tuning ports of the voltage controlled Oscillator (VCO)  36 . The output of the VCO  36  is used to drive the A/D converters  12 , signal equalizer  14  and the carrier recovery block  22 . As described in Applicant&#39;s co-pending U.S. patent applications Ser. Nos. 11/315,342 and 11/315,345, the phase detector  32  also generates a lock detection function ƒ(θ p ,φ p ), which can be used to detect a signal lock condition. 
         [0010]    As may be appreciated, the signal path from the A/D converters  12 , through the clock recovery circuit  28  and back to the A/D converters  12  defines a digital Phase Locked Loop (PLL) which tunes the VCO output to phase and frequency match symbols modulated onto the received optical signal. Similarly, the signal path from the dispersion compensators  16 , through the polarization compensator  18 , the carrier recovery block  24 , LMS update block  26  and back to the polarization compensator  18  forms an equalizer adaptation loop which adaptively optimizes the compensation vectors H XX , H XY , H YY  and H YX . 
         [0011]    The coherent optical receiver of  FIGS. 1 and 2  is capable of digital clock recovery from a high-speed (e.g. symbol rates above 10 Gbaud) optical signal composed of two independently modulated orthogonal polarizations, even in the presence of moderate to severe ISI due to chromatic dispersion (CD) and polarization mode dispersion (PMD), and polarization transients on the order of 50 kHz. 
         [0012]    As noted above, because both the polarization compensator  18  and the optimization block  30  perform similar functions, the compensation vectors H XX , H XY , H YY  and H YX  computed by the LMS update block  26  can be used for both signal equalization and clock phase detection. This arrangement in beneficial in that it eliminates the need for separate angle θ(n+1) and phase φ(n+1) filter coefficient computation blocks, and therefore reduces the cost of the receiver. However, this arrangement suffers a limitation in that the equalizer adaptation loop can interact with the clock recovery PLL to yield a double nested loop. In some cases, this interaction can lead to a random walk behaviour of the compensation vectors H XX , H XY , H YY  and H YX  and the VCO clock phase. Over time, this random walk behaviour can drive the clock phase to one side of the eye opening and thereby severely limit the ability of the equalizer  14  to compensate ISI. In extreme cases, this can lead to severe performance penalties or even system breakdown. 
         [0013]    Accordingly, techniques for separating adaptation and clock recovery loops are highly desirable. 
       SUMMARY OF THE INVENTION 
       [0014]    An aspect of the present invention provides, in a coherent optical receiver of an optical communications network, a method of recovering a clock signal from a high speed optical signal received through an optical link. A set of compensation vectors are adaptively computed for compensating Inter-symbol Interference (ISI) due to at least polarization impairments of the optical signal. A channel delay is estimated based on the computed compensation vectors. The estimated channel delay is subtracted from the computed compensation vectors to generate corresponding modified compensation vectors. Finally, the modified compensation vectors are used to derive a recovered clock signal. 
         [0015]    An advantage of the present invention is that the equalizer adaptation loop can continue to be used for both signal equalization and clock recovery functions. However, while the equalizer adaptation loop compensates ISI due to both polarization effects (PMD and polarization rotation) and channel delay, the clock recovery PLL operates on signals that are compensated for ISI other than channel delay. This effectively separates the equalizer adaptation loop from the clock recovery PLL and thereby prevents undesirable interaction between these two functions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    Further features and advantages of the present invention will become apparent from the following detailed description, taken in combination with the appended drawings, in which: 
           [0017]      FIG. 1  is a block diagram schematically illustrating a coherent optical receiver known from Applicant&#39;s co-pending U.S. patent application Ser. No. 11/551,367; 
           [0018]      FIG. 2  is a block diagram schematically illustrating a clock recovery circuit usable in the coherent receiver of  FIG. 1 , and implementing methods known from Applicant&#39;s co-pending U.S. patent applications Ser. Nos. 11/315,342 and 11/315,345; 
           [0019]      FIG. 3  is a block diagram schematically illustrating channel coefficient calculation in accordance with a representative embodiment of the present invention; 
           [0020]      FIG. 4  is a block diagram schematically illustrating principle operations of the delay removal block of the embodiment of  FIG. 3 ; 
           [0021]      FIG. 5  is a block diagram schematically illustrating principle operations of the phase vector calculation block of  FIG. 4 ; 
           [0022]      FIG. 6  is a block diagram schematically illustrating principle operations of the phase unwrapping calculation block of  FIG. 4 ; 
           [0023]      FIG. 7  is a block diagram schematically illustrating principle operations of the delay estimation block of  FIG. 4 ; and 
           [0024]      FIG. 8  is a block diagram schematically illustrating principle operations of the delay subtraction block of  FIG. 4 . 
       
    
    
       [0025]    It will be noted that throughout the appended drawings, like features are identified by like reference numerals. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0026]    The present invention provides a method and system for separating the equalizer adaptation loop from the clock recovery PLL, by removing channel delay from the compensation coefficients supplied to the clock recovery PLL. A representative embodiment of the present invention is described below with reference to  FIGS. 3-8 . 
         [0027]    Referring to  FIG. 3 , in very general terms, the present invention provides a delay removal block  38  which estimates and subtracts the channel delay from the set of complex compensation vectors (Hxx, Hxy, Hyy, Hyx). The resulting modified compensation vectors (H′xx, H′xy, H′yy, H′yx) can then be supplied to the optimization block  30  of the clock recovery circuit  28 . The original compensation vectors (Hxx, Hxy, Hyy, Hyx) are supplied to the polarization compensator  18  in a normal manner. 
         [0028]    Referring to  FIG. 4 , the delay removal block  38  operates by processing the compensation vectors (Hxx, Hxy, Hyy, Hyx) to compute channel phase information (at  40 ). The channel phase information is then “unwrapped” (at  42 ) to facilitate estimation of the channel delay (at  44 ). The estimated channel delay is then subtracted from the compensation vectors (Hxx, Hxy, Hyy, Hyx), at  46 , to yield the modified compensation vectors (H′xx, H′xy, H′yy, H′yx). Each of these functions are described in greater detail below with reference to  FIGS. 5-8 . 
         [0029]    As may be appreciated, each compensation vector is composed of a respective term for each term of the intermediate vectors {T A   X } and {T A   Y }. Thus, in an embodiment in which each intermediate vector {T A   X } and {T A   Y } comprises N=256 terms, each compensation vector will also include N=256 terms. For convenience, each term of a compensation vector may be referred to as an equalization coefficient, and referenced with an index [i], where i=0 . . . (N-1). A set of corresponding equalizing coefficients (Hxx[i], Hxy[i], Hyy[i], Hyx[i]) define a transfer function for equalizing the i th  terms of the intermediate vectors {T A   X } and {T A   Y }. In matrix notation, the transfer function may be written as: 
         [0000]    
       
         
           
               
             
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         [0030]    The channel delay compensated by this set of coefficients cannot be obtained from any one of the four coefficients, hence traditional delay estimate methods do not apply. Instead, the channel delay is calculated from the determinant of this matrix transfer function, as shown in  FIG. 5 . The determinant D[i] is defined as: 
         [0000]    
       
      
       D[i]=H 
       xx 
       [i]·H 
       yy 
       [i]−H 
       yx 
       [i]·H 
       xy 
       [i] 
      
     
         [0031]    The Square-root-Determinant transfer function, SD[i], can also be calculated. The magnitude of SD[i] is given by |SD[i]|=|D[i]| 1/2 , and its phase is calculated as 
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         [0000]      FIG. 5  illustrates a representative method of performing this calculation. Thus, the determinant D[i] is computed at  48 . The phase of the determinant, ∠D[i], can then be obtained, at  50 , for example using a look-up table as shown in  FIG. 5 . Dividing the phase of the determinant ∠D[i] by 2 (at  52 ) yields the desired phase ∠SD[i]. 
         [0032]    As may be appreciated, the phase ∠SD[i] computed using this method may have virtually any value. However, any computed value beyond a range of ±π is equivalent to a corresponding value within this range. Accordingly, the computed phase values ∠SD[i] are preferably “unwrapped” to their equivalent true phase value, φ[i], which lies within the range (−π≦φ[i]≦π). 
         [0033]    As may be seen in  FIG. 6 , one method of unwrapping the computed phase values ∠SD[i] is to normalize the computed phase values ∠SD[i], at  54 , such that the normalized phase φ N [i] corresponding to the baseband frequency (e.g. frequency, f=0) has a value of zero, and then compute the true phase φ[i] of each successive frequency bin, above and below the baseband, based on the difference between the normalized phase values of each neighbouring pair of frequency bins. For example, consider an embodiment in which each intermediate vector {T A   X } and {T A   Y } comprises N=256 terms, so i=0 . . . 255. The frequency bins of each intermediate vector {T A   X } and {T A   Y } span a frequency range of −1/T . . . +1/T (where T is the symbol period) and the center frequency bin (in this case, at i=127) corresponds with the baseband frequency. In this case, the normalized phase φ N [i] for each frequency bin (i=0 . . . 255) can be computed as φ N [i]=∠SD[i]−∠SD[127]. The true phase φ[i] of the baseband frequency bin (i=127) can then be set equal to its normalized phase (thus, φ[127]=φ N [127]=0). Then, for positive frequency bins (i=128 . . . 255), the true phase φ[i] can be found by: 
         [0000]      φ[i]=φ N [i] if M0 is minimum 
         [0000]      φ[ i]=φ   N   [i ]+π if  M 1 is minimum 
         [0000]      φ[ i]=φ   N   [i ]−π if  M 2 is minimum 
         [0000]      where: 
         [0000]        M 0=|φ N   [i]−φ[i− 1]| 
         [0000]        M 1=|φ N   [i]+π−φ[i− 1]| 
         [0000]        M 2=|φ N   [i]−π−φ[i− 1]| 
         [0034]    This operation is schematically illustrated in  FIG. 6 . For negative frequency bins (i=126 . . . 0), the true phase φ[i] can be found by: 
         [0000]      φ[i]=φ N [i] if M0 is minimum 
         [0000]      φ[ i]=φ   N   [i]+π  if  M 1 is minimum 
         [0000]      φ[ i]=φ   N   [i]−π  if  M 2 is minimum 
         [0000]      where: 
         [0000]        M 0=|φ N   [i]−φ[i+ 1]| 
         [0000]        M 1=|φ N   [i]+π−φ[i+ 1]| 
         [0000]        M 2=|φ N   [i]−π−φ[i+ 1]| 
         [0035]    The true phase vector φ[i], i=0 . . . N represents the phase response of SD[i] (with respect to frequency). The linear component of this phase response is the delay compensated by the equalizing coefficients. Accordingly, the delay τ est  can be estimated from a linear fit across the true phase vector φ[i], i=0 . . . N, using any of a variety of known fitting algorithms. 
         [0036]      FIG. 7  shows an alternative method, in which the delay τ est  is calculated as a fraction of the symbol interval T by subtracting the phase at positive ½ symbol rate from the phase at negative ½ symbol rate. Thus 
         [0000]    
       
         
           
             
               τ 
               est 
             
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         [0037]    Continuing the above example, the frequency bins corresponding to +½T and −½T are located at i=191 and i=63, respectively. In this case, τ est =(φ[63]−φ[191]). 
         [0038]    Cycle slips and framing errors during signal acquisition can appear as a delay in the equalizing coefficients. Left un-checked, this delay can offset the equalizing coefficients to one side, and thus affect their ability to compensate ISI. This problem can be overcome by implementing a secondary loop  54  to low-pass-filter the delay estimate τ est  to yield a channel delay, τ apply , which can be applied to the equalizing coefficients Hxx[i], Hxy[i], Hyy[i] and Hyx[i]. One method of low-pass filtering the delay estimate τ est  is to integrate τ est  over a predetermined period of time (or, equivalently, a predetermined number of successive values). Low-pass filtering τ est  in this manner effectively zeros the delay over time, thereby centering the clock phase estimate and so ensuring optimum performance of the equalizer  14 . 
         [0039]    Referring to  FIG. 8 , the channel delay τ apply  can then be converted into a phase offset e −j     ω     τ  (for example via a multiplication block  56  and a look-up table  58 ) and subtracted from the equalizing coefficients Hxx[i], Hxy[i], Hyy[i] and Hyx[i], at  60 , to generate modified coefficients H′xx[i], H′xy[i], H′yy[i] and H′yx[i] that are delay-free, and centered for optimal compensation performance. 
         [0040]    Referring back to  FIG. 3 , the modified coefficients H′xx[i], H′xy[i], H′yy[i] and H′yx[i] can then be supplied to the optimization block  30  of the clock recovery circuit  28 . With this arrangement, the phase detector  32  operates on signals that are compensated for ISI except channel delay. On the other hand, the carrier recovery block  24  receives symbol estimates  22  which are compensated for ISI including channel delay. Consequently, the clock recovery digital PLL is decoupled from the LMS adaptation loop. 
         [0041]    The embodiment(s) of the invention described above is(are) intended to be exemplary only. The scope of the invention is therefore intended to be limited solely by the scope of the appended claims.