Abstract:
A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a division of U.S. application Ser. No. 13/909,057 filed Jun. 3, 2013, and incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor technology, and particularly to a semiconductor device and a fabrication method thereof. 
         [0004]    2. Description of the Prior Art 
         [0005]    In general, there are two basic types of non-volatile memory (NVM) cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. Recently, MONOS or SONOS structure is also developed to replace floating gate with ONO. In a split-gate structure the control gate is still positioned above the floating gate, but it is offset laterally from it. Another split-gate structure includes for example a select gate formed overlying a portion of a channel region adjacent the source region. The select gate is electrically isolated from a control gate formed overlying a portion of a channel region adjacent the drain region. The select gate controls channel current. 
         [0006]    Conventionally, the select gate is formed in a way similar to forming a spacers utilizing an anisotropic etch process, and a width of 1.5 T of a split gate structure can be obtained. As shown in FIG.  1 , after a gate structure  12  is formed on a semiconductor substrate  10 , a selective gate material layer  14  is deposited. Thereafter, as shown in  FIG. 2 , undesired portion of the selective gate material layer  14  is removed by etching through a photoresist layer  16 . Thereafter, as shown in  FIG. 3 , an anisotropic etch process is performed to remove the photoresist layer  16 , if any left in the previous etch process, and to forma select gate  18  in a spacer shape. Accordingly, the obtained split gate structure can have a width of the width of 1.5 transistors, denoted as 1.5 T. However, because the shape of the select gate relies on the anisotropic properties of the etch process, it is difficult to control the shape finally obtained. Furthermore, as the procedures are similar to those for forming spacers, the upper portion of the obtained select gate always has a width (line width) gradually decreasing toward the top, and it is difficult to increase the width along the upper portion. 
         [0007]    In the demands for minimizing the memory device size and fabrication cost, the size of the split gate structure having a select gate is also wanted to be minimized. However, even though the width of the control gate can be decreased in accordance with the minimization of the feature size benefit from an improved process limit in the future, the select gate width may be still limited to an acceptable scale, such that the split gate structure maybe unable to meet the desired width of 1.5 T. The reason is if the width of the select gate having a spacer shape is further minimized, the width of the upper portion will be too narrow to maintain its properties or performance. Accordingly, there is still a need for a novel method of forming a split gate structure having a select gate with good performance to meet a demand of a minimized size. 
       SUMMARY OF THE INVENTION 
       [0008]    An objective of the present invention is to provide a semiconductor device and a method of fabricating a semiconductor device, such that the problem that the minimization of whole size must be restricted by an acceptable minimized width of the upper portion of the select gate is solved. 
         [0009]    According to an embodiment, a semiconductor device is provided. The semiconductor device includes a first gate structure disposed on a semiconductor substrate, a first spacer and a second spacer disposed on two opposite-to-each-other sidewalls of the first gate structure, and a second gate structure disposed on the semiconductor substrate. The second gate structure is immediately adjacent to the first spacer and not adjacent to the second spacer. A width of a top surface of the second gate structure is not less than a width of a bottom surface of the second gate structure. 
         [0010]    According to another embodiment, a method of fabricating a semiconductor device includes steps as follows. A semiconductor substrate is provided. A charge trapping film is formed on the semiconductor substrate. A first gate material layer is formed on the charge trapping film. A first hard mask is formed and patterned on the first gate material layer. The first gate material layer and the charge trapping film are etched through the first hard mask to forma transient first gate structure and a temporary gate structure. A first spacer and a second spacer are formed on a first sidewall of the transient first gate structure and a second sidewall of the temporary gate structure, respectively. The first sidewall and the second sidewall are opposite to each other. A second gate structure is formed between the first spacer and the second spacer. A second mask is formed on the second gate structure, the first spacer and the second spacer. A patterned photoresist layer is formed to partially cover the first hard mask above the transient first gate structure. An etch process is performed through the patterned photoresist layer to remove the first hard mask above the temporary gate structure and the temporary gate structure, and to partially remove the first hard mask above the transient first gate structure and the transient first gate structure to forma first gate structure. The first gate structure is immediately adjacent to the first spacer. 
         [0011]    The patterned photoresist layer, the first hard mask and the second hard mask are removed. 
         [0012]    In the semiconductor device and the fabrication method according to the present invention, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device may still have an excellent performance upon miniaturization. 
         [0013]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIGS. 1 to 3  are schematic cross-sectional views illustrating a method of fabricating a select gate according to a conventional technology. 
           [0015]      FIGS. 4 to 9  are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. 
           [0016]      FIG. 10  is a schematic plan view illustrating a semiconductor device according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Please refer to  FIGS. 4-9  illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention. As shown in  FIG. 4 , a semiconductor substrate  20  is provided. A transient first gate structure  28   a  and a temporary gate structure  28   b  are formed on the semiconductor substrate  20 . The transient first gate structure  28   a  includes a charge trapping film  22   a  and a gate material layer  24   a.  The temporary gate structure  28   b  includes a charge trapping film  22   b  and a gate material layer  24   b.  The semiconductor device may be formed for example as follows. A charge trapping film is formed on the semiconductor substrate  20 . Material of the charge trapping film may include, for example, a multilayer of oxide-nitride-oxide (ONO), but be not limited thereto. Agate material layer maybe formed on the charge trapping film. The gate material may include for example one or more selected from polysilicon, metal, metal oxide, metal nitride, metal silicide, and the like. The hard mask material layer is formed on the gate material layer through for example a chemical vapor deposition (CVD) process. Material of the hard mask material layer may include for example one selected from Si 3 N 4 , SiO 2 , SiON, SiC, and SiCN. The hard mask material layer maybe patterned through for example a photolithography process and an etch process to form a patterned hard mask having a portion of hard masks  26   a  and a portion of hard mask  26   b.  The gate material layer and the charge trapping film are etched through the hard masks  26   a  and  26   b  to form gate material layers  24   a  and  24   b  and charge trapping films  22   a  and  22   b,  respectively. 
         [0018]    Thereafter, as shown in  FIG. 5 , the spacer  30  and the spacer  32  are formed on two sidewalls opposite to each other of the transient first gate structure  28   a  and the temporary gate structure  28   b,  respectively. The spacers  30  and  32  may be formed through blanketly forming a dielectric layer, such as an oxide layer, by a CVD process and then etching the dielectric layer. Other spacers (not shown) may be also formed on other sidewalls of the transient first gate structure  28   a  and the temporary gate structure  28   b.  Because the hard masks  26   a  and  26   b  are still on the transient first gate structure  28   a  and the temporary gate structure  28   b,  the spacer  30  and the spacer  32  may also cover the sidewalls of the hard masks  26   a  and  26   b.  However, it does not affect the structure and the process of the present invention if any of the upper portions of the sidewalls of the hard masks  26   a  and  26   b  is not covered with the spacers. A gate dielectric  34  may be formed on the semiconductor substrate  20 , if desired, through for example a thermal oxidation process. 
         [0019]    Thereafter, a second gate structure is filled into the space between the spacer  30  and the spacer  32 , through for example a deposition process, a planarization process and an etch back process. As shown in  FIG. 6 , a gate material layer  36  is formed all over, for example, that a polysilicon layer is formed through a CVD process, to cover the semiconductor substrate  20 , so as to fill the space between the spacer  30  and the spacer  32  and to extend onto the hard masks  26   a  and  26   b.    
         [0020]    Thereafter, as shown in  FIG. 7 , a planarization process, such as a chemical-mechanical polishing (CMP) process, is performed and stopped at the hard masks  26   a  and  26   b  as a stop layer, to remove the gate material layer on the hard masks  26   a  and  26   b  and to planarize the gate material layer between the spacer  30  and the spacer  32 . Thereafter, an etch back, such as an anisotropic etch process, is performed to remove a portion of the gate material layer between the spacer  30  and the spacer  32 , and the gate material layer  36   a  having a predetermined or desired height is allow to remain, so as to form a second gate structure. The gate material layer  36   a  has a height preferably less than the height of the gate material layer  24   a.  Material of the gate material layer  36   a  and material of the gate material layer  24   a  may be the same or different. Thereafter, a hard mask  38  is formed on the second gate structure, the spacer  30 , and the spacer  32  through, for example, a CVD process, to form a hard mask material layer filling the space among the second gate structure, the spacer  30  and the spacer  32  and extend onto the hard masks  26   a  and  26   b.  Material of the hard mask material layer may include for example one selected from Si 3 N 4 , SiO 2 , SiON, SiC and SiCN. Thereafter, an etch process is performed to remove the hard mask material layer above the hard masks  26   a  and  26   b  to obtain a hard mask  38  having a height the same as the hard mask  26   a  and  26   b.  But, the height of the hard mask  38  is not particularly limited. The hard masks  26   a  and  26   b  and the hard mask  38  may include the same or different material having the same or different etch rates. 
         [0021]    Thereafter, as shown in  FIG. 8 , a patterned photoresist layer  40  is formed and partially covers the hard mask  26   a  above the transient first gate structure  28   a.  The patterned photoresist layer  40  may be formed using a microlithography process. The covered transient first gate structure  28   a  is the first gate structure wanted to be formed. By etching through the patterned photoresist layer  40 , the hard mask  26   b  not covered by the patterned photoresist layer  40  and the temporary gate structure  28   b  under the hard mask  26   b  can be removed, and also the portion of the hard mask  26   a  not covered by the patterned photoresist layer  40  and the portion of the transient first gate structure  28   a  under the portion of the hard mask  26   a  can be removed. The remaining transient first gate structure  28   a  is the first gate structure located immediately adjacent to the spacer  30 . Furthermore, since the first gate structure is formed by performing an anisotropic etch process through the patterned photoresist layer  40 , the resulted width of the first gate structure is related to the width of the patterned photoresist layer  40 . When the patterned photoresist layer  40  has a width allowed to be the process limit (supposed that it is T) and in the situation that the patterned photoresist layer  40  partially covers the hard mask  26   a  and extend onto the hard mask  38  having a protection effect, the width of the first gate structure  28   a  obtained can be less than T. 
         [0022]    Thereafter, as shown in  FIG. 9 , the patterned photoresist layer  40 , the hard mask  26   a  and the hard mask  38  are removed. The hard mask  26   a  and the hard mask  38  may be removed through, for example, a wet etch process. 
         [0023]    It is noticed that, regarding the coverage of the patterned photoresist layer  40  as shown in  FIG. 8 , when the hard mask  26   a  has an etching rate different from the hard mask  38 , in other words, when the hard mask  26   a  is more easily etched to be removed than the hard mask  38 , the hard mask  38  can protect the second gate structure, spacer  30  and spacer  32  thereunder to prevent them from being etched. Accordingly, the patterned photoresist layer  40  can only cover a portion of the hard mask  26   a  or preferably extend to cover a portion of the hard mask  38 , or the entire hard mask  38  if desired. The gate material layer  24   a,  the spacer  30 , and the gate material layer  36   a  under the hard mask  26   a  and the hard mask  38  may be damaged due to etch through the joint of the hard mask  26   a  and the hard mask  38 . Accordingly, the patterned photoresist layer  40  is allowed to extend to cover at least a portion of the hard mask  38  in order to further make sure to cover the joint of the hard mask  26   a  and the hard mask  38 . When the hard mask  26   a  has not an etch selectivity with respect to the hard mask  38 , for example, when the hard mask  26   a  includes the same material as the hard mask  38 , the hard mask  26   a  and the hard mask  38  are both easily etched to be removed. The hard mask  38  cannot protect the second gate structure, spacer  30  and spacer  32  thereunder during the etch process, and, accordingly, the patterned photoresist layer  40  is allowed to not only cover a portion of the hard mask  26   a  but also extend to cover the entire hard mask  38  for protecting the spacer  30 , the gate material layer  36   a  and the spacer  32  thereunder. 
         [0024]    Thereafter, lightly-doped regions  46  and  48  may be formed within the semiconductor substrate  20  beneath the first gate structure  28   a  and the semiconductor substrate  20  beneath the second gate structure  36   a  and extend to source/drain regions  50  and  52  after the patterned photoresist layer  40 , the hard mask  26   a  and the hard mask  38  are removed. 
         [0025]    Thereafter, a spacer  42  may be formed on another sidewall of the first gate structure  28   a  after the patterned photoresist layer  40 , the hard mask  26   a,  and the hard mask  38  are removed. In this procedure, a spacer  44  may also formed on the sidewall of the spacer  32  of the second gate structure. 
         [0026]    The semiconductor device made by the process described above includes the spacer  30  and the spacer  42  on two sidewalls of the first gate structure  28   a.  The spacer  30  and the spacer  42  are opposite to each other. The second gate structure  36   a  is disposed to be immediately adjacent to the spacer  30  and not to the spacer  42 . In the unique process according to the present invention, the second gate structure  36   a  is filled into the space between the spacer  30  and the spacer  32 , such that the width W 1  of the top surface  54  of the second gate structure  36   a  will not be less than the width W 2  of the bottom surface of the second gate structure  36   a.  In other words, the width W 1  of the top surface  54  of the second gate structure  36   a  will be greater than or equal to the width W 2  of the bottom surface of the second gate structure  36   a.  Furthermore, with respect to the upper portion of the second gate structure  36   a,  the width of the upper portion will gradually increase toward the top surface  54 , such that the upper portion is in a shape having a gradually enlarged opening with respect to a cross-sectional view as shown by  FIG. 9 . Furthermore, the top surface of the second gate structure  36   a  is planar, and this is a great difference from an arc or curve shape which is common for the top surface shape of a conventional spacer-shaped select gate. A spacer  44  may be further formed on the sidewall of the spacer  32  on the sidewall of the second gate structure  36   a  together to serve as a spacer of the second gate structure  36   a.    
         [0027]    The above describes a structure of a single semiconductor device according to the present invention. When a plurality of the semiconductor devices each according to the present invention are arranged on a semiconductor substrate, the layout may be as shown by the plan view in  FIG. 10 , but not limited thereto. As shown in  FIG. 10 , the gate material layers  24   a  and  24   a ′ and the gate material layers  36   a  and  36   a ′ may be each in a bar shape and disposed on the semiconductor substrate  20 . A spacer  30  is disposed between the gate material layer  24   a  and the gate material layer  36   a.  A spacer  30 ′ is disposed between the gate material layer  24   a ′ and the gate material layer  36   a ′. A spacer  42  and spacers  32  and  44  are disposed on the outer sidewalls of the gate material layer  24   a  and the gate material layer  36   a,  respectively. A spacer  42 ′ and spacers  32 ′ and  44 ′ are disposed on the outer sidewalls of the gate material layer  24   a ′ and the gate material layer  36   a ′, respectively. The drawings show some widths represented using the symbol “W 3 ”. The distance of the second semiconductor device from the first semiconductor device may be one T, and the second semiconductor device is arranged as a mirror image of the first semiconductor device. Using the fabrication method according to the present invention, when the line width (feature width) meets the process limit (T), i.e. W 3  equals to T, the obtained gate material layer  24   a  and  24   a ′ each may have a width less than T and the width of each of the gate material layer  36   a  and  36   a ′ is substantially T/2. 
         [0028]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.