Abstract:
The present invention provides a method of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The method comprises the steps of providing a target value, obtaining a first and second test result of the wafers processed through the first and second path respectively, calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and selecting one of the first and second paths according to the estimates.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method and apparatus of tool matching for a semiconductor manufacturing process.  
           [0003]    2. Description of the Prior Art  
           [0004]    One of the critical factors for success of mass production is yield, defined as the proportion of the number of qualified products to the total number of products. In semiconductor manufacturing, the products are wafers or chips, and the corresponding wafer yield and chip yield are significant. Improvement of the wafer and chip yield reduces the cost and increases production efficiency since most of the wafers or chips are qualified and few are wasted. Therefore, manufacturing engineers are dedicated to the improvement of yield.  
           [0005]    Conventionally, for improvement of the yield, engineers choose, from the available tools for each one step or operation in the manufacturing process of a product, the one in the best condition. However, the combination of the selected tools is only a possibly but not absolutely optimized path since the tools are selected individually for each step and correlation between the tools is ignored.  
         SUMMARY OF THE INVENTION  
         [0006]    Therefore, the object of the present invention is to provide a method and apparatus of tool matching for a semiconductor manufacturing process, wherein the correlation between the tools is taken into account so that an absolutely optimized path is provided.  
           [0007]    The present invention provides a method of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The method comprises the steps of providing a target value, obtaining a first and second test result of the wafers processed through the first and second path respectively, calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and selecting one of the first and second path according to the estimates.  
           [0008]    The present invention also provides a method of tool matching for a semiconductor manufacturing process having a plurality of paths completed by serial combinations of tools for processing of lots of wafers. The method comprises the steps of providing a target value T, obtaining groups of test results of lots of wafers processed through the paths, calculating a mean value and variation of each group of the test results, wherein the mean value and variation of lot j of the wafers processed through path i are W(i,j) and σ(i,j) respectively, providing weights for the lots of the wafers, wherein the weight for lot j of the wafers processed through path i is R(i,j), calculating estimates P of the paths, wherein the estimate of path i using the wafers from M0 th  to Mc th  lot is  
           P        (   i   )       =       ∑     j   =     m   o         j   =     m   c                R        (     i   ,   j     )            [              W        (     i   ,   j     )       -   T          +     σ        (     i   ,   j     )         ]           ,                         
 
           [0009]    and selecting one of the paths according to the estimates.  
           [0010]    The present invention further provides an apparatus of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The apparatus comprises means for providing a target value, means for obtaining a first and second test result of the wafers processed through the first and second path respectively, means for calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and means for selecting one of the first and second path according to the estimates. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:  
         [0012]    [0012]FIG. 1 is a block diagram showing an apparatus of tool matching for a semiconductor manufacturing process according to one embodiment of the invention.  
         [0013]    [0013]FIG. 2 is a flow chart showing a method of tool matching for a semiconductor manufacturing process according to one embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]    In the embodiment of the invention will be described in the following, a manufacturing process comprises four steps S 1 , S 2 , S 3  and S 4 . The available tools for the step S 1 , S 2 , S 3  and S 4  are TL(1,1), TL(1,2) and TL(2,1), TL(2,2), TL(2,3), TL(2,4) and TL(3,1), TL(3,2) and TL(4,1), TL(4,2), TL(4,3) respectively. Thus there are 48(2×4×2×3) paths L available.  
         [0015]    [0015]FIG. 1 is a block diagram showing an apparatus of tool matching for a semiconductor manufacturing process according to one embodiment of the invention.  
         [0016]    A wafer acceptance tester  13  carries out wafer acceptance tests of lots of wafers processed through the 48 paths L. A group of test results for each one lot of wafers is obtained. The storage device  12  stores the test results of the lots of the wafers indexed to the corresponding paths through which the wafers are processed.  
         [0017]    A processing device  11  obtains the test results from the storage device  12  and calculates a mean value W and a variation σ of the test results for each lot of the wafers. A weight R is also provided by the processing device  11  for each lot. The weights R are obtained by Exponential Weighting Moving Average based on the lots. The storage device  12  also stores each of the mean values W and variations σ.  
         [0018]    A target value T is provided and sent to the processing device  11 . The target value T is the expected value of the test result of the processed wafer.  
         [0019]    Then, an estimate P for each path L is calculated by the processing device  11 . The estimate P(i) of path i L(i) is  
           ∑     j   =     m   o         j   =     m   c              R          (     i   ,   j     )          [              W        (     i   ,   j     )       -   T          +     σ        (     i   ,   j     )         ]           ,                         
 
         [0020]    wherein j is the order of the lots processed through the path L(i), Mc is the last lot, M0 is the first lot, R(i,j) is the weight of lot j processed through the path L(i), W(i,j) is the mean value of the test results of lot j processed through the path L(i) and σ(i,j) is the variation of the test results of lot j processed through the path L(i).  
         [0021]    Finally, the estimates P of the paths L appear on the display  14 . The engineers select one path with the smallest estimate, which is the prior choice for accomplishment of the target value.  
         [0022]    Additionally, the wafer acceptance tester  13  carries on the tests of the following lots of the wafers so that there are more test results stored in the storage device  12  and the estimates P of the paths L are continually updated.  
         [0023]    In the embodiment, the difference [|W(i,j)−T|] and the variation σ(i,j) have an equal weight. However, they may have different weights k 1  and k 2  for a special estimation, that is to say, the estimate P(i) of path i L(i) is  
         ∑     j   =     m   o         j   =     m   c                  R        (     i   ,   j     )            [       k1               W        (     i   ,   j     )       -   T            +     k2                   σ        (     i   ,   j     )           ]       .                           
 
         [0024]    . Further, the weight R(i,j) is a time-dependent parameter and increases with the order of the lot.  
         [0025]    [0025]FIG. 2 is a flow chart showing a method of tool matching for a semiconductor manufacturing process according to one embodiment of the invention.  
         [0026]    In the embodiment of the invention described here, a manufacturing process comprises four steps S 1 , S 2 , S 3  and S 4 . The available tools for the step S 1 , S 2 , S 3  and S 4  are TL(1,1), TL(1,2) and TL(2,1), TL(2,2), TL(2,3), TL(2,4) and TL(3,1), TL(3,2) and TL(4,1), TL(4,2), TL(4,3) respectively. Thus there are 48(2×4×2×3) paths L available.  
         [0027]    In step  21 , wafer acceptance tests of lots of wafers processed through the 48 paths L are carried out. A group of test results for each lot of wafers is obtained. The test results of the lots of the wafers indexed to the corresponding paths through which the wafers are processed are stored.  
         [0028]    In step  22 , a mean value W and a variation a of the test results for each lot of the wafers are obtained. A weight R is also provided for each lot. The weights R are obtained by Exponential Weighting Moving Average based on the lots. Each of the mean values W and variations σ are also stored.  
         [0029]    In step  23 , A target value T is provided, which is the expected value of the test result of the processed wafer.  
         [0030]    In step  24 , an estimate P for each path L is calculated. The estimate P(i) of path i L(i) is  
           ∑     j   =     m   o         j   =     m   c              R          (     i   ,   j     )          [              W        (     i   ,   j     )       -   T          +     σ        (     i   ,   j     )         ]           ,                         
 
         [0031]    wherein j is the order of the lots processed through the path L(i), Mc is the last lot, M0 is the first lot, R(i,j) is the weight of lot j processed through the path L(i), W(i,j) is the mean value of the test results of lot j processed through the path L(i) and σ(i,j) is the variation of the test results of lot j processed through the path L(i).  
         [0032]    Finally, in step  25 , the estimates P of the paths L are listed. The engineers select one path with the smallest estimate, which is the prior choice for accomplishment of the target value.  
         [0033]    Additionally, the tests of the following lots of the wafers are carried out so that there are more test results generated and the estimates P of the paths L are continually updated.  
         [0034]    In conclusion, the present invention provides a tool matching method wherein the wafer acceptance test results are stored in a continually updated database, a weight is assigned to each lot of the wafers and the performances of the available paths are statistically estimated using the database. Thus, a quantified estimate is provided for tool matching for a semiconductor manufacturing process.  
         [0035]    While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.