Abstract:
A metal gate transistor may include a metal layer over a high dielectric constant dielectric layer. The dielectric layer abstracts electronegativity from said metal layer, altering its workfunction. The workfunction of the metal layer may be set to compensate for the dielectric layer abstraction.

Description:
BACKGROUND  
       [0001]     The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include metal gate electrodes.  
         [0002]     MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high dielectric constant (k) dielectric materials, instead of silicon dioxide, can reduce gate leakage. A high-k material has a dielectric constant greater than 10. Such a dielectric may not, however, be compatible with polysilicon. For that reason, it may be desirable to replace polysilicon based gate electrodes with metal gate electrodes for devices that include high-k gate dielectrics.  
         [0003]     The optimal workfunction for a metal gate electrode will differ depending upon whether it is used to form an NMOS transistor or a PMOS transistor. When the same material is used to make metal gate electrodes for NMOS and PMOS transistors, the gate electrodes cannot demonstrate the desired workfunction for both types of devices. If a material is chosen to ensure an acceptable workfunction for an NMOS transistor&#39;s gate electrode, then the workfunction for the PMOS transistor&#39;s gate electrode will be unsatisfactory. Similarly, choosing a material that ensures an acceptable workfunction for the PMOS transistor&#39;s gate electrode will prevent the NMOS transistor&#39;s gate electrode from having a suitable workfunction. Selecting a midgap material (i.e., a material that gives the metal gate electrodes for NMOS and PMOS transistors an intermediate workfunction) will yield a suboptimal workfunction for both transistors.  
         [0004]     It may be possible to address this problem by forming the NMOS transistor&#39;s metal gate electrode from a first material and the PMOS transistor&#39;s metal gate electrode from a second material. The first material may ensure an acceptable workfunction for the NMOS gate electrode, while the second material may ensure an acceptable workfunction for the PMOS gate electrode. Processes for forming such dual metal gate devices may, however, be complex and expensive.  
         [0005]     Accordingly, there is a need for an improved process for making a semiconductor device that includes a metal gate electrode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIGS. 1A-1D  represent cross-sections of structures that may be formed when carrying out an embodiment of the present invention;  
         [0007]      FIG. 2  provides a chart showing how various elements&#39; workfunctions scale with their electronegativity; and  
         [0008]      FIGS. 3A-3D  represent cross-sections of structures that may be formed when carrying out a second embodiment of the present invention. 
     
    
       [0009]     Features shown in these figures are not intended to be drawn to scale.  
       DETAILED DESCRIPTION  
       [0010]      FIGS. 1A-1D  illustrate structures that may be formed when carrying out one embodiment of the present invention. Initially, dielectric layer  101  is formed on substrate  100 , generating the  FIG. 1A  structure. Substrate  100  may comprise a bulk silicon or silicon-on-insulator substructure. Alternatively, substrate  100  may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although several examples of materials from which substrate  100  may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.  
         [0011]     Dielectric layer  101  preferably comprises a high-k gate dielectric layer. Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide. Although a few examples of materials that may be used to form dielectric layer  101  are described here, that layer may be made from other materials that reduce gate leakage.  
         [0012]     Dielectric layer  101  may be formed on substrate  100  using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process. Preferably, a conventional atomic layer CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate  100  and dielectric layer  101 . The CVD reactor may be operated long enough to form a layer with the desired thickness. In most applications, dielectric layer  101  may be less than about 60 Angstroms thick, and more preferably between about 5 Angstroms and about 40 Angstroms thick.  
         [0013]     After dielectric layer  101  is formed on substrate  100 , a metal gate electrode is formed on dielectric layer  101 . In a preferred embodiment, the metal gate electrode is formed by initially forming metal layer  102  on dielectric layer  101 —generating the  FIG. 1B  structure. Metal layer  102  may comprise any conductive material from which a metal gate electrode may be derived. Preferably, metal layer  102  has etch and thermal stability characteristics that render it suitable for making metal gate electrodes for semiconductor devices. In this regard, it may be desirable for metal layer  102  to tolerate relatively high temperatures, e.g., temperatures that exceed about 90° C. If metal layer  102  can withstand such relatively high temperatures, it may be easier to integrate that layer into the overall process for making the semiconductor device.  
         [0014]     Examples of high temperature resistant materials, from which metal layer  102  may be made, include tungsten, platinum, ruthenium, palladium, molybdenum and niobium, as well as alloys formed form these and other elements. Metal layer  102  may alternatively comprise other, less conductive, metal compounds. Such compounds include metal carbides, e.g., titanium carbide, zirconium carbide, tantalum carbide, and tungsten carbide, metal nitrides, e.g., titanium nitride and tantalum nitride, and conductive metal oxides, e.g., ruthenium oxide.  
         [0015]     Although metal layer  102  preferably comprises materials that may withstand high temperature anneal processes, metal layer  102  may comprise other materials, e.g., aluminum, titanium, or tantalum. Although a few examples of materials that may be used to form metal layer  102  are described here, that layer may be made from many other materials. The term “metal layer,” as used in this application, thus encompasses any conductive material from which a gate electrode may be derived.  
         [0016]     Metal layer  102  may be formed on dielectric layer  101  using a conventional CVD or PVD process, e.g., a conventional atomic layer CVD process, and preferably is between about 25 Angstroms and about 2,000 Angstroms thick. Dopants may be added to metal layer  102 , as it is formed. For example, when a CVD process is used to make layer  102 , dopants may be integrated into layer  102  as it is deposited. Because the amount of dopant that is introduced into layer  102  may vary depending upon the deposition temperature, it may be possible to change the dopant level by changing the temperature. As an example, decreasing the deposition temperature may cause the amount of chlorine that is added to metal layer  102  to increase. The resulting dopant concentration may also be affected by the type and quantity of elements that are included in the process gases, which are fed into the CVD reactor.  
         [0017]     Dopants may be added to first metal layer  102 , as it is formed or after it is formed, to shift layer  102 &#39;s workfunction to ensure that it falls within the desired range. When a CVD process is used to add dopants to metal layer  102 , the resulting dopant concentration may be controlled by varying the type and quantity of elements that are included in the process gases, which are fed into the CVD reactor, and the deposition temperature. The optimal concentration of any dopant that is added to first metal layer  102  to shift its workfunction to a targeted level may depend upon the composition and properties of layer  102  (including its initial workfunction), the type of dopant used, and the target workfunction.  
         [0018]     As deposited, metal layer  102  may not be suitable for forming a gate electrode if it lacks an acceptable workfunction. In this embodiment of the present invention, impurities are added to metal layer  102  to shift its workfunction. Those impurities may comprise one or more elements that raise or lower metal layer  102 &#39;s workfunction, when added to it. In a preferred embodiment, a sufficient amount of that element, or elements, is added to layer  102  to shift that layer&#39;s workfunction by at least about 0.1 eV. When forming an NMOS transistor from layer  102 , an element with relatively low electronegativity, e.g., an electronegativity value that is less than about 1.7, should be used. When forming a PMOS transistor, an element with relatively high electronegativity, e.g., an electronegativity value that is greater than about 2.8, should be used.  
         [0019]      FIG. 2  provides a chart showing how a material&#39;s workfunction scales with electronegativity. Adding to metal layer  102  a significant quantity of a material with a relatively high electronegativity will raise the workfunction of metal layer  102 , while adding to metal layer  102  a significant quantity of a material with a relatively low electronegativity will lower the workfunction of metal layer  102 . As is apparent from this chart, elements that may reduce the workfunction of a midgap film (e.g., a film with a workfunction that is between about 4.3 eV and about 4.9 eV), rendering it suitable for forming an NMOS gate electrode, include: lanthanide metals, scandium, zirconium, hafnium, aluminum, titanium, tantalum, niobium, and tungsten. Other potentially useful elements include the alkali metals and alkaline earth metals. Aluminum and cerium may be particularly preferred elements for reducing the workfunction of metal layer  102 . Elements that may increase the workfunction of a midgap film, rendering it suitable for forming a PMOS gate electrode, include: nitrogen, chlorine, oxygen, fluorine, and bromine. Chlorine may be a particularly preferred element for raising the workfunction of metal layer  102 .  
         [0020]     The elements that best serve to raise or lower the workfunction of metal layer  102  to the desired level will depend upon metal layer  102 &#39;s composition and properties. Even elements with an electronegativity value as low as 2.2 (e.g., platinum, palladium, ruthenium, and iodine) may raise the workfunction of some metal layers. Although a few examples of the elements, which can shift metal layer  102 &#39;s workfunction, are identified here, other elements may be used instead. The process of the present invention thus contemplates the use of any element that may serve to modify metal layer  102 &#39;s workfunction. In some embodiments, the layer  102  may be made up of multiple sublayers.  
         [0021]     The workfunction shifting elements identified above may be added to metal layer  102  using any conventional doping process. Examples of such processes include ion implantation, plasma enhanced ion implantation, furnace diffusion, and plasma deposition. Such elements may also be added to metal layer  102  by first depositing a film that contains them onto the surface of layer  102 , then causing material from that film to diffuse into layer  102 .  FIG. 1C  illustrates the use of an ion implantation process to introduce workfunction shifting elements into metal layer  102 .  
         [0022]     In the course of processing the semiconductor structures, some of the doping, which initially sets the workfunction, is lost to or abstracted by the high-k dielectric layer  101 , enabling the layer  101  to saturate its valence requirements. The resulting saturated high-k dielectric film  101  is advantageous, but occurs at the expense of the needed dopant concentration in the overlying metal layer  102 . Thus, in order to achieve the desired target workfunction for the overlying metal layer  102 , the layer  102  may be initially overdoped so that after abstraction by the underlying layer  101 , the layer  102  is at the desired target workfunction level.  
         [0023]     Thus, experiments may be done to determine how much of the dopant is abstracted from the metal layer  102 . That amount may then be added to the initial doping of the layer  102  so that after abstraction, the layer  102  ends up at the target workfunction.  
         [0024]     The optimal concentration of the impurity, or impurities, added to metal layer  102  to shift its workfunction to the targeted level will depend upon the composition and properties of layer  102  (including its initial workfunction), the type of impurity used, and the target workfunction. The amount of a first impurity needed to shift metal layer  102 &#39;s workfunction from 4.3 eV to 4.2 eV (e.g., to tailor layer  102  for an NMOS application) will very likely be substantially less than the amount of a second impurity needed to shift the workfunction from 4.3 eV to 5.0 eV (e.g., to tailor layer  102  for a PMOS application). In most applications, adding a suitable element to metal layer  102  until it comprises between about 3 and about 50 atomic percent of the resulting impurity containing metal layer should be sufficient to shift the workfunction to an acceptable degree. In many applications, it should suffice to add the impurity until it comprises between about 5 and about 20 atomic percent of the resulting layer.  
         [0025]     After impurities are added to layer  102 , conventional techniques may be used to etch that layer and layer  101  to form metal gate electrode  103 , as shown in  FIG. 1   d . Subsequent steps for completing the transistor, e.g., forming source and drain regions, and the device&#39;s contacts, are well known to those skilled in the art and will not be described in more detail here.  
         [0026]      FIGS. 3A-3D  represent cross-sections of structures that may be formed when carrying out a second embodiment of the method of the present invention. In this embodiment, the method of the present invention is used to form a CMOS device with NMOS and PMOS transistors that have acceptable workfunctions.  
         [0027]     After forming metal layer  202  on dielectric layer  201  (e.g., using the materials and process steps described above), portion  210  of metal layer  202  is masked, e.g., by photoresist  215 , generating the  FIG. 3A  structure. In a preferred embodiment, metal layer  202  has a final target workfunction of between about 4.3 eV and about 4.9 eV. The PMOS transistor for the CMOS device will be created where metal layer  202  is masked, while the NMOS transistor for the CMOS device will be created where metal layer  202  remains exposed.  
         [0028]     After masking portion  210 , impurities are added to exposed portion  211  of metal layer  202 , as illustrated in  FIG. 3B . The impurities comprise one or more of the elements specified above, and may be added to metal layer  202  using any of the processes described previously. Again, those impurities are added in a concentration in excess of that needed to achieve the final target workfunction so that after abstraction, the target workfunction is achieved.  
         [0029]     When an NMOS transistor will be formed where metal layer  202  is exposed, an element should be selected that will shift the workfunction of metal layer  202  to a level suitable for the metal gate electrode for an NMOS transistor. In a preferred embodiment, a sufficient amount of a first element should be added to exposed portion  211  of metal layer  202  to lower the final target workfunction of that first portion of that layer to between about 4.0 eV and about 4.2 eV. Elements suitable for NMOS transistor fabrication are identified above.  
         [0030]     After doping exposed portion  211  with an element that shifts the workfunction of that portion of metal layer  202  to a level favorable for an NMOS transistor, portion  211  is masked (e.g., by photoresist  216 ) and portion  210  is exposed. After masking portion  211 , impurities are added to exposed portion  210 , as illustrated in  FIG. 3C . When a PMOS transistor will be formed where metal layer  202  is exposed, an element should be selected that will shift the workfunction of metal layer  202  to a level suitable for the metal gate electrode for a PMOS transistor. In a preferred embodiment, a sufficient amount of a second element should be added to exposed portion  210  of metal layer  202  to raise the final target workfunction of that second portion of that layer to between about 5.0 eV and about 5.2 eV. Elements suitable for PMOS transistor fabrication are identified above. To achieve the final target workfunction after abstraction, extra doping should be used so that after abstraction, the final target workfunction is achieved.  
         [0031]     The order in which different portions of metal layer  202  are doped is unimportant. As illustrated, a first portion of metal layer  202  may be doped with an element that has a relatively low electronegativity value before a second portion of metal layer  202  is doped with an element that has a relatively high electronegativity value. This embodiment of the present invention also contemplates, however, a process in which a first portion of layer  202  is doped with an element that has a relatively high electronegativity value before a second portion of metal layer  202  is doped with an element that has a relatively low electronegativity value.  
         [0032]     As mentioned above, the optimal concentration of the impurities that are added to metal layer  202  to adequately reduce the workfunction of a first portion of that layer and to increase the workfunction of a second portion of that layer will depend upon the composition and properties of layer  202 , the type of impurities used, and the target workfunctions. In most applications, it should suffice to add the impurities to the metal layer until they comprise between about 3 and about 50 atomic percent of the first and second portions, respectively, of the resulting impurity containing metal layer.  
         [0033]     It has been found that the final target workfunction of a first portion of a titanium carbide metal layer—with a workfunction of about 4.5 eV—may be shifted to a value of about 4.2 eV by adding a sufficient amount of aluminum to generate a layer that includes about 11 atomic percent aluminum. The workfunction of a second portion of such a metal layer may be shifted to a value of about 5.1 eV by adding a sufficient amount of chlorine to generate a layer that includes about 12 atomic percent chlorine.  
         [0034]     After the workfunctions of different portions of metal layer  202  have been shifted to enable gate electrodes with acceptable electrical properties to be derived from metal layer  202  for both NMOS and PMOS transistors, metal layer  202  and dielectric layer  201  may be etched, generating the  FIG. 3D  structure. That structure will include NMOS gate electrode  220 , which will have a workfunction suitable for an NMOS transistor, and PMOS gate electrode  230 , which will have a workfunction suitable for a PMOS transistor. Because those skilled in the art are familiar with the steps for completing the NMOS and PMOS transistors, a further description of those steps will be omitted.  
         [0035]     While a subtractive metal gate process is illustrated, the same techniques may be applied to any metal gate process, including a replacement metal gate process.  
         [0036]     Although the foregoing description has specified certain steps and materials that may be used in the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims.