Abstract:
A package to encase a semiconductor package is manufactured by the following steps. First, an electrically conductive frame is provided. This frame has a plurality of leadframes arranged in a matrix with each leadframe having a plurality of spaced leads extending outwardly from a central aperture. The electrically conductive frame further includes a plurality of connecting bars joining outer end portions of adjacent ones of the leadframes. Second, a groove is formed in the connecting bars to form a reduced thickness portion between the outer end portions of adjacent ones of the leadframes. Third, a semiconductor device is electrically coupled to inner portions of said leads. Fourth, the frame and the semiconductor devices are encapsulated in a molding compound. Finally, the molding compound and the frame are cut along the grooves to form singulated semiconductor packages having outer lead portions with a height greater than the height of the reduced thickness portion.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This patent application claims priority to U.S. Provisional Patent Application Ser. No. 60/741,965 that was filed on Dec. 2, 2005. The subject matter of provisional patent application U.S. 60/741,965 is incorporated by reference in its entirety herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     This invention relates to a leadless semiconductor package and a method to manufacture such a package. More particularly, the invention relates to a method to manufacture leadless semiconductor packages having reduced lead burrs and improved solder fillets. 
     Semiconductor device packages provide environmental protection to one or more integrated circuit devices, referred to as semiconductor dies, encased within the package. The semiconductor dies have input/output (I/O) pads electrically interconnected to inner lead portions of a leadframe or an interposer by wire bonds, tape bonds or the like. Opposing outer lead portions of the leadframe or interposer are electrically interconnected to circuits on a printed circuit board, flex circuit or other external circuitry. A polymer molding resin encases the semiconductor die and at least the inner lead portion of the leadframe or interposer. 
     When the outer lead ends of the leadframe or interposer terminate at a face of the package body and do not extend beyond the package footprint, the package is referred to as a “no-lead” or “leadless” semiconductor package. Conventional leadless packages include quad flat no-lead (QFN) packages having four sets of leads disposed around the perimeter of a bottom surface of a square package and dual flat no-lead (DFN) packages having two sets of leads disposed on opposing sides of the bottom of the package. 
     To facilitate the manufacture of certain leaded and leadless semiconductor packages, a matrix of leadframes is provided in sheet form. Such a matrix is referred to as a frame. During manufacture, a semiconductor die is attached to a die pad disposed within an aperture defined by the inner leads of a leadframe. The die is then electrically interconnected to the inner lead ends. When die are attached to each die pad and electrically interconnected to each leadframe making up a frame, the entire assembly is encapsulated by a molding resin. After the molding resin cures or otherwise hardens, individual packages are separated from the encapsulated frame by a process referred to as singulation. 
     One method of singulation is referred to as saw singulation. A saw is used to cut through the molding resin and the metallic leadframe. Because the molding resin is relatively hard and the metallic leadframe is relatively soft, the saw blade must cut through dissimilar materials and it is not possible to optimize the saw blade design for either material. Metallic debris from sawing adheres to the saw blade distorting the cut surface and reducing the usable life of the blade. Incomplete cutting of the leadframe results in the formation of burrs. A burr may extend from one outer lead end to a closely spaced adjacent outer lead end causing a short circuit. 
     One method to overcome difficulty with saw singulation is disclosed in U.S. Pat. No. 6,744,118 to Ikenaga et al. that is incorporated by reference in its entirety herein. With reference to  FIG. 1 , Ikenaga et al. disclose a leadframe  100  having a reduced thickness section  102  positioned along a saw track  104  or  104 ′. The leadframe is partially etched from one side to form the reduced thickness section  102 . One side. etching is referred to in the art as “half-etching”. The reference discloses that the width of the saw blade can not equal the width of the reduced thickness section because there are variations along the width of the etched section and cutting would not go smoothly. Accordingly, the saw blade width is selected to be either greater than the width of the reduced thickness section (saw track  104 ′) or less than the width of the reduced thickness section (saw track  104 ). With saw track  104 ′, the problems of sliver formation remains and debris formation, while reduced are still issues. 
     Selecting saw track  104  reduces the amount of metal that must be cut by the saw blade, reduces the accumulation of metallic debris on the saw blade and also reduces the number of burrs formed.  FIG. 2  illustrates a disadvantage with this approach. A portion  106  of the outer edge of the lead  108  is recessed from the perimeter  110  of the molded plastic package body, a condition referred to as “pull-back.” Pull-back results in reduced area for a contact with a printed circuit board  112  affecting mounting integrity. Further, a solder fillet  114  does not extend to the package perimeter  110  making inspection difficult. Still further, the surface area  115  at the base of the lead is reduced. During assembly, the leads are arranged side by side and supported by an adhesive tape. The wirebonding process applies force to the leads when bonding a gold bond wire. If this force is not controlled, the leads will bend. Since the force which can be applied to a “pull-back” lead is limited, the diameter of a gold wire that may be used for wirebonding is also limited. 
     Another approach to saw singulation is disclosed in U.S. Pat. No. 6,605,865 to Jeong et al. that is incorporated by reference in its entirety herein. As shown in  FIG. 3 , U.S. Pat. No. 6,605,865 discloses a package  116  having a leadframe  118  with a reduced thickness projection  120 . A punch shears surface  122  singulating the package. However, the reduced thickness of the projection reduces the stability of the lead, making bonding of wires  124  more difficult. Shearing introduces stresses to the leads and package that may impact reliability by causing delamination or microcracks. 
     Accordingly, there remains a need for a method to manufacture leadless semiconductor packages that does not have the above recited disadvantages and there remains a need for an improved leadless semiconductor package. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with a first embodiment of the invention, there is provided a frame for a semiconductor package. The frame includes a plurality of leadframes arranged in a matrix and interconnected by connecting bars. Each leadframe includes leads and the connecting bars interconnect leads of adjacent leadframes to one another. The connecting bars have grooves disposed between the leads of the adjacent leadframes reducing the amount of metal to be cut by a saw blade during singulation. 
     In accordance with a second embodiment of the invention, there is provided a frame for a semiconductor package having a plurality of leadframes arranged in a matrix and interconnected by connecting bars. Semiconductor die are mounted on die pads circumscribed by inner lead ends of respective ones of the leadframes and the assembly then encapsulated with molding resin. The molded assembly is then cut along the connecting bars to singulate individual semiconductor packages. Each leadframe includes leads and the connecting bars interconnect leads of adjacent leadframes to one another. The connecting bars have reduced thickness portions between adjacent leads of each leadframe such that, after singulation, portions of the leads exposed on the sides of the semiconductor package have a larger profile height than the reduced thickness portions. 
     In accordance with a third embodiment of the invention, there is provided a method to manufacture a semiconductor package that includes the steps of providing a frame having a plurality of leadframes arranged in a matrix and interconnected by connecting bars, wherein each leadframe has a plurality of leads and the connecting bars interconnect leads of adjacent leadframes to one another; forming grooves in the connecting bars between adjacent leads of each leadframe to form reduced thickness portions; electrically connecting semiconductor die to the inner leads of respective ones of the leadframes; collectively encapsulating the leadframes and semiconductor die with a molding compound; and cutting the molding compound and frame along the connecting bars to singulate individual semiconductor packages wherein portion of the leads exposed on sides of the individual semiconductor packages have greater profile heights than the reduced thickness portions. 
     The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other objects, features and advantages of the invention will be apparent from the description, drawings and claims. 
    
    
     
       BREIF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a portion of a leadframe matrix as known from the prior art before singulation. 
         FIG. 2  is a cross-sectional view of an outer lead portion of a semiconductor package following singulation from the leadframe matrix of  FIG. 1 . 
         FIG. 3  is a cross-sectional view of a semiconductor package having projecting reduced thickness outer lead portions as known form the prior art. 
         FIG. 4  is a partial perspective view of a frame of the present invention illustrating a saw line for singulation. 
         FIG. 5  is a partial profile view of the frame of  FIG. 4 . 
         FIG. 6  is a bottom view of a leadframe component of the frame of  FIG. 4 . 
         FIG. 7  is a top view of a leadframe component of the frame of  FIG. 6 . 
         FIG. 8  is a schematic view of a frame of  FIG. 4 . 
         FIGS. 9A-9G  depict semiconductor device packages of the invention during sequential manufacturing steps. 
         FIG. 10  is a partial cross-sectional view of a semiconductor package of the invention mounted to a printed circuit board. 
         FIG. 11  illustrates an alternative semiconductor package of the invention where the semiconductor die is connected to a leadframe by flip-chip bonding. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 4  is a partial perspective view, and  FIG. 5  a partial profile view, of a frame  10  of the present invention. The frame  10  is formed from an electrically conductive material, such as copper or a copper-base alloy. By copper-base, it is meant that alloy contains more than 50%, by weight, of copper. A saw track  12  illustrates the path a saw blade  22  will traverse to separate adjacent leadframes  14 ,  14 ′. Each leadframe  14  includes leads  16  and leads  16 ′ of adjacent leadframes are connected to one another by connecting bars  18 . As discussed hereinbelow, the connecting bars  18  are provided with grooves  20  reducing the amount of metal through which saw blade  22  must cut during singulation. The top side etching profile may optionally include an undercut  21  where the leads  16 ,  16 ′ are connected prior to sawing. This undercut  21  reduces the amount of metal that will be removed during sawing and further minimizes the formation of side burrs. 
       FIG. 6  illustrates a bottom view of a leadframe  14  which is a component of a frame while  FIG. 7  is a top view of the leadframe  14 . Leadframe  14  includes a plurality of leads  16 . A die pad  23  is disposed in a central aperture defined by inner ends of the leads  16 . Extending from corners of the die pad  23  are tie bars  24 . The tie bars  24  are formed as generally straight bars having protrusions  26  extending from an end opposing the die pad  23 . As previously described, disposed around the perimeter of the leadframe  14  are connecting bars  18  to interconnect leads  16  to leads  16 ′ of an adjacent leadframe. Saw track  12  extends along the connecting bar  18 , in a direction generally perpendicular to the long axis of the leads. 
     Each lead  16  has a first lead surface  28  disposed on a bottom surface of the lead and a bond site  30  on a top surface of the lead. The leads  16  are spaced apart from each other and from the die pad  23  to electrically isolate the leads and die pad. In the illustrated embodiment, the leadframe  14  has eight leads  16  disposed on each of the four sides of the die pad  23 . The reduced thickness portions of the leadframe  14  are indicated by cross-hatching in  FIG. 6 . For example, end portions of the leads  16  and perimeter of the die pad  23  may be reduced in thickness to form lips  32 ,  34  which help lock the die pad  23  and leads  16  in the molding resin. Also, the connecting bars  18  are provided with reduced thickness portions (grooves)  20  disposed between adjacent leads  16  of the leadframe  14 . 
     It will be appreciated that the number and positioning of the leads may be modified as needed for a particular application. For example, the leadframe may include two sets of leads disposed on opposing sides of the die pad for use in a dual, no-lead, semiconductor package. Furthermore, it will be appreciated that the die pad may be eliminated for certain package configurations, such as for the flip-chip configuration of  FIG. 11  discussed hereinbelow. 
       FIG. 8  is a schematic view of the frame  10 . The frame includes a plurality of leadframes  14  arranged in a matrix. The illustrated matrix is an  8 × 8  matrix of leadframes, however the frame  10  may include any convenient number of leadframes in any desired array pattern. 
       FIGS. 9A-9G  depict semiconductor packages  50  of the invention during sequential manufacturing steps. In  FIG. 9A , leadframe  14  is interconnected to an adjacent leadframe  14 ′ by connecting bar  18 . The sheet of electrically conductive material forming an array of leadframes  14 ,  14 ′ has a profile height, “h”, that is equal to a desired profile height for die pad  23  and leads  16 . While  FIG. 9A  illustrates two interconnected leadframes, it is contemplated that any number of leadframes may be interconnected for the assembly of multiple packages. 
     The features of the leadframe  14 , including die pad  23 , leads  16 , connecting bars  18  and tie bars  24 , are formed by any known process such as stamping, chemical etching, laser ablation, or the like. The reduced thickness areas in each of those features is formed by a controlled subtractive process such as chemical etching or laser ablation. For example, each surface intended to form a contact surface of a lead  16 , a full thickness portion of a connecting bar  18  and a center portion of a die pad  23  may be coated with a chemical resist and the remaining surfaces exposed to a suitable etching agent for a time effective to reduce the thickness of the exposed areas to a desired reduced thickness, “t”. Typically reduced thicknesses are desired for the saw line portion of the connecting bars, the lips of the die pad and leads and for the tie bars. The reduced thickness, “t”, may be between 30% and 70% of the thickness of the profile height “h” and more preferably is between 40% and 60% of the profile height. 
     Referring to  FIG. 9B , after the leadframe  14  is formed, the bond sites  30  of the leads  16  and the bond sites  36  of the die pad  23  may be plated with a material to facilitate bonding with a bond wire. For example, the bond sites  30 ,  36  may be plated with one or more of nickel, palladium, gold, silver and other wire-bondable metals or metal alloys. 
     Referring to  FIG. 9C , in preparation of wirebonding, the bottom surface  28  of each lead  16  and the bottom surface of the die pad  23  are secured to a surface  38 . In the illustrated embodiment, the surface  38  if formed on an adhesive tape. Next, a semiconductor die  40  is secured to the die pad using a conventional bonding material such as solder, epoxy, double sided tape, or the like. 
     Referring to  FIG. 9D , after the die  40  is secured to the die pad  23 , bond wires  42  are connected between I/O pads  44  on a surface of the die  40  and bond sites  30  on the leads. In some embodiments, bond wires  42  also electrically interconnect an I/O pad to the die pad via bond site  36 . Wirebonding may be by ultrasonic bonding, where a combination of pressure and ultrasonic vibration burst are applied to form a metallurgical cold weld, thermocompression bonding, where a combination of pressure and elevated temperature are applied to form weld, or thermosonic bonding where a combination pressure, elevated temperature and ultrasonic bursts are applied to form a weld. The wire  42  used in bonding is preferably, gold, a gold-base alloy, aluminum or an aluminum-base alloy. As an alternative to wirebonding, tape automated bonding (TAB) may be used. 
     The reduced thickness portions of the connecting bars  18  do not affect the stability of the leads  16  during wirebonding because the contacts  30  are adjacent a portion of the connecting bar  18  that has a thickness equal to the full profile height “h” of the leads  16 . This is unlike prior-art arrangements where the removal of material between contacts of adjacent leadframes reduces the contact area between the contacts and the surface  38  making the leads relatively less stable during wirebonding. 
     Referring to  FIG. 9E , after wirebonding is completed, the die  40 , leadframe  14  and bond wires  42  are encapsulated with a molding compound  46 . The molding compound is disposed about the package components by any convenient technique, such as transfer molding or injection molding. The molding compound  46  is an electrically insulating material such as a polymer molding resin, for example, an epoxy. A typical flow temperature for the polymer molding resin is between about 250° C. and about 300° C. Alternatively, the molding compound may be a low temperature thermal glass composite. 
     The reduced thickness of the tie bars  24  and of the lips  34  allows the molding compound  46  to be received under the tie bars  24  and lips  34  allowing tie bars and lips  34  to mechanically lock the die pad  23  in the molding compound  46  and help retain the die pad in the package. Similarly, lips  32  anchor the contacts  16  in the package. 
     Referring to  FIG. 9F , after molding, the surface  38  is removed and bottom surfaces  28  of the contacts  16  may be plated with a material to facilitate electrical interconnection with external circuitry. For example, the bottom surfaces  28  may be plated with one or more of nickel, palladium, gold, silver, or other suitable material. 
     With reference to  FIG. 9G , saw singulation or other suitable process is then used to cut through the molding compound  46  and the connecting bar  18  to separate adjacent lead frames  14 ,  14 ′ and to form individual semiconductor packages. As best seen in  FIGS. 4 and 5 , the reduced thickness portions of the connecting bars  18  created by the grooves  20  reduce the amount of metal through which the saw blade  22  must pass when singulating the leadframes. Further, the grooves  20  create space between the exposed surfaces  28  of the leads  16 . Even if the leads  16  are post-singulation plated, this space reduces or eliminates the possibility of burrs or smears causing shorting between leads. 
     With reference back to  FIG. 9G , each semiconductor package  50  has a bottom (first) package face  52 . an opposing top (second) package face  54  and package side faces  56  extending between the bottom package face  52  and the top package face  54 . The package faces are formed in part by molding compound  46 . The bottom surface of each lead  16  and the bottom surface of the die pad  22  are exposed on the bottom face  52  of the package  50 . 
     The package  50  may be electrically coupled to an external circuit, such as a printed circuit, flex circuit, another semiconductor package, a test device or other component or device. As depicted in  FIG. 10 , the package  50  may be soldered to a printed circuit board  60 . Advantageously, the portion of the lead  16  exposed at the side surface  56  of the package  50  is the full profile height of the lead  16 , enabling a full height solder fillet  62  during board mounting. Comparing the prior art fillets of  FIGS. 2 and 3  to the fillet of  FIG. 10  shows that the lead  16  of the invention has a greater contact area (exposed area) on both the bottom surface  52  and the side surface  56  of the package  50  improving board mounting integrity over that achieved by the prior art. Further, the contact  16  of the invention provides a more visible solder fillet  62  which makes inspection easier than with prior art fillets that either lack or have a reduced visible fillet. 
     Referring to  FIG. 11 , in an alternative embodiment of the invention, semiconductor device packages  66  including integrated circuit devices  40  are connected to the leadframes  14  by a flip-chip bond. These packages are substantially similar to the packages shown in  FIG. 9  and may be formed using the same method with the exception that the die pad  23  and wires  42  of  FIG. 9  have been eliminated and the I/ 0  pads  44  on the chip are electrically interconnected to the bond sites  30  on the leads  16  by soldering or the like. 
     In general, the frame of the present invention includes a plurality of leadframes interconnected by connecting bars which are provided with grooves disposed between adjacent leads of each leadframe to reduce the amount of metal through which a saw blade must pass when singulating packages. Furthermore, the grooves create space between exposed leads reducing or eliminating the possibility of burrs or smears causing shorting between leads. The grooves do not affect the stability of the leads during electrical interconnection of the leads to an integrated circuit device, ensuring consistent bond integrity. Also, the resulting package has full lead material exposed on the side allowing for a solder fillet during board mounting. 
     While described in terms of encapsulating integrated circuit devices, the packages of the invention may also be used to encapsulate hybrid devices where one or more passive or optical devices are coupled to one or more integrated circuit devices on a single die pad. 
     A number of embodiments of the present invention have been described. Nevertheless, it will be understood that various modification may be made without departing from the spirit and the scope of the invention. Accordingly, other embodiments are within the scope of the claims that follow.