Abstract:
A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si 1-y Ge y  layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly seletive etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si 1-y Ge y , and strained Si 1-y Ge y  depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si 1-y Ge y C or a heavily doped layer to make electrical contacts of the SiGe/Si heterojunction diodes.

Description:
FIELD OF INVENTION 
   This invention relates to transferring a SiGe layer onto a second substrate and forming a new material structure that has emerging applications in microelectronics and optoelectronics. In particular, a strained Si/SiGe layer on an insulator structure is useful for fabricating high speed devices such as complementary metal oxide semiconductor (CMOS) transistors, modulation doped field effect transistors (MODFETs), high electron mobility transistors (HEMTs), and bipolar transistors (BTs); SiGe layer on Si heterostructures can be used to produce photodetectors to provide Si-based far infrared detection for communication, surveillance and medical applications. 
   BACKGROUND OF THE INVENTION 
   For applications in microelectronics, high carrier mobilities are desirable. It has been found that electron mobility in strained Si/SiGe channels is significantly higher than that in bulk Si. For example, measured values of electron mobility in strained Si at room temperature are about 3000 cm 2 /Vs as opposed to 400 cm 2 /Vs in bulk Si. Similarly, hole mobility in strained SiGe with high Ge concentration (60%-80%) reaches up to 800 cm 2 /Vs the value of which is about 5 times the hole mobility of 150 cm 2 /Vs in bulk Si. The use of these materials in state-of-the-art Si devices is expected to result in much higher performances, higher operating speeds in particular. However, the underlying conducting substrate for MODFETs and HBTs or the interaction of the underlying substrate with active design region in CMOS are undesirable features which limit the full implementation of high speed devices. To resolve the problem, an insulating layer is proposed to isolate the SiGe device layer from the substrate. Therefore, there is a need for techniques capable of fabricating strained Si/SiGe on insulator materials. 
   There are two available techniques for making SiGe-On-Insulator (SGOI). One is via SIMOX as reported in a publication by T. Mizuno et al. entitled “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology,” IEDM, 99-934. However, this method has several limits because the oxygen implantation induces further damages in the relaxed SiGe layer in addition to the existing defects caused by lattice mismatch. And, the high temperature anneal (&gt;1100° C.) needed to form oxide after the oxygen implantation is detrimental to the strained Si/SiGe layers since Ge tends to diffuse and agglomerate at temperatures above 600° C., this effect becomes more significant when Ge content is higher than 10%. 
   The second technique of making SiGe on insulator is via selective etching with the aid of an etch stop. In U.S. Pat. No. 5,906,951 by J. O. Chu and K. E. Ismail which issued in May 1999, a method of utilizing wafer bonding and backside wafer etching in KOH with a p ++ -doped SiGe etch-stop to transfer a layer of strained Si/SiGe on a SOI substrate was described. However, the etching selectivity of SiGe to p ++ -doped SiGe etch-stop in KOH decreases sharply as the doping level in the etch stop layer is below 10 19 /cm 3 , therefore, the strained Si/SiGe layer may also be subjected to KOH etching if etching could not stop uniformly at the p ++  SiGe etch-stop layer due to variation of dopants in the p ++  etch-stop layer. Furthermore, since the SiGe etch-stop layer is heavily doped with boron in the range from about 5×10 19  to about 5×10 20 /cm 3 , there are chances of auto-doping of the strained Si/SiGe during thermal treatment. 
   For fiberoptic applications, SiGe/Si heterojunction diodes are a good choice for demodulating 1.3-1.6 μm light at 300K. The use of 30% to 50% Ge is suggested to achieve absorption at the desired 1.3-1.6 μm wavelength and low defects such as dislocations in the SiGe layer is needed to enhance the photodetector sensitivity. The state-of-the-art technology to achieve SiGe/Si heterojunction diodes with higher responsivity, low noise, and fast response is to form a 100-period SiGe/Si strained layer superlattice. However, the SiGe alloy no longer behaves like the bulk material due to the quantum size effect. The net result of the quantum size effect is that the absorption occurs at wavelengths (1.1-1.3 μm) shorter than expected. Therefore, a bulk SiGe alloy with desirable Ge content and low defects is needed to fabricate photodetector that would absorb lights in the range of 1.3-1.6 μm. 
   The invention provides a method capable of transferring a low defect SiGe layer onto a desirable substrate using the etch-back method but without any additional heavily doped etch-stop layer. The key feature of this invention is that a SiGe layer serves both as the layer over which the epitaxial strained Si/SiGe is grown but also as an etch-stop layer itself in some specific etching solutions. In other words, the SiGe layer is a self-etch-stop in this case. As a result, the process of fabricating strained Si/SiGe on insulator or a SiGe/Si heterostructure is greatly simplified and the quality of the strained Si/SiGe or SiGe/Si heterostructure is significantly improved. 
   SUMMARY OF THE INVENTION 
   In accordance with the present invention, a method for transferring low defect SiGe bulk layer onto a second substrate and forming strained Si/SiGe on an insulator (SGOI) or SiGe/Si heterostructure is described. This approach comprises the steps of selecting a semiconductor substrate, forming a first expitaxial graded layer of Si 1-x Ge x  over the semiconductor substrate, forming a second relaxed Si 1-y Ge y  over the first graded Si 1-x Ge x  layer, selecting a second substrate, bonding the first substrate to said second substrate to form a joined substrate, grinding and polishing the first substrate from its backside to remove the majority of said first substrate, etching the remaining material of the first substrate and stopping at the Si 1-x Ge x  utilizing a SiGe highly selective wet etch process, applying chemical-mechanical planarization (CMP) to remove the defective portion of the graded Si 1-x Ge x  layer, smoothing the surface of the Si 1-x Ge x  layer by a CMP process step, growing strained Si/SiGe layers over the smoothed surface of the Si 1-x Ge x  layer for MOSFET, MODFET, HEMT or BT for microelectronic applications, or growing SiGe photodectors for applications in optoelectronics. 
   The invention provides a method capable of transferring a low defect SiGe layer onto a desirable substrate using the etch-back method but without any additional heavily doped etch-stop layer. The key feature of this invention is that a SiGe layer serves both as the layer over which the epitaxial strained Si/SiGe is grown but also as an etch-stop layer itself in some specific etching solutions. In other words, the SiGe layer is a self-etch-stop in this case. As a result, the process of fabricating strained Si/SiGe on insulator or a SiGe/Si heterostructure is greatly simplified and the quality of the strained Si/SiGe or SiGe/Si heterostructure is significantly improved. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention is described in more details thereinafter relative to non-limitative embodiments and with reference to the attached drawings, wherein show: 
       FIG. 1  is a cross section view of the first substrate with epitaxially grown graded Si 1-x Ge x  and relaxed Si 1-y Ge y  layers. 
       FIG. 2  is a cross section view of the first semiconductor substrate shown in  FIG. 1  bonded to a second substrate with or without an insulator layer. 
       FIG. 3  is a cross section view of the first substrate shown in  FIG. 2  thinned by grinding and polishing from its back side. 
       FIG. 4  is a cross section view of the remainder of the first substrate shown in  FIG. 3  after the step of etching and stopping at the graded Si 1-x Ge x  layer by a highly selective wet etching process. 
       FIG. 5  is a cross section view of the remaaining Si 1-x Ge x  layer from  FIG. 4  polished away and the Si 1-y Ge y  layer smoothed with a chemical-mechanical planarization (CMP) process. 
       FIG. 6  is a cross section view of an epitaxially grown strained Si/SiGe layer or a p-i-n photodetector epitaxially grown over the smoothed Si 1-y Ge y  layer from FIG.  5 . 
       FIG. 7  is a cross section view of an alternative substrate similar to the substrate shown in  FIG. 2  expect for the presence of intermediate agent layer  100 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The embodiment which will now be described in conjunction with the above drawings relates to the formation of a layer of monocrystalline strained Si/SiGe on an insulator material (SGOI) or a SiGe layer on Si with the aid of planarization of surfaces, wafer bonding and a selective wet etching process using SiGe as the etch-stop layer. 
   The top surface of layer  40  shown in  FIG. 1  is turned upside down and bought into intimate contact with surface  90  of substrate  80 . The two surfaces  42  and  90  are brought together by the wafer bonding approach. The bonded surfaces of  42  and  90  are annealed at a temperature in the range from about 20° C. to about 500° C. for a time period in the range from about 2 hours to about 50 hours. Another embodiment, as shown in  FIG. 7 , uses at least one intermediate agent layer  100  such as Ge, or metal materials which either have a low-melting point or react with silicon to form a silicide such materials may be tungsten (W), cobalt (Co), titanium (Ti) etc. to achieve high bonding strength at anneal temperatures in the range from 100° C. to 800° C. The anneal can be either a furnace anneal or a rapid thermal anneal (RTA). 
   Epitaxial layer  30  is comprised substantially or completely of relaxed Si 1-y Ge y  formed on upper surface  22  of layer  20 . Layer  30  may have a thickness in the range from 200 nm to 1000 nm. The Ge content y in layer  30  is chosen to match the crystal lattice constant of upper surface  22  of layer  20  such that layer  30  is relaxed or essentially strain free. The Ge content y in layer  30  may be equal to or about the value of x at upper surface  22 . The value y may be in the range from about 0.2 to about 0.5. An encapsulation layer  40  may be formed over the relaxed layer  30 . Encapsulation layer  30  may be formed on upper surface  32  of layer  30  via PECVD, LPCVD, UHV CVD or spin-on techniques. Encapsulation layer  40  may have an upper surface  42 . The encapsulation material may be, for example, Si, SiO 2 , Poly Si, Si 3 N 4 , low-k dielectric materials, for example, Diamond Like Carbon (DLC), Fluorinated Diamond Like Carbon (FDLC), a polymer of Si, C, O, and H or a combination of any two or more of the foregoing materials. One example of a polymer of Si, C, O, and H is SiCOH which is described in U.S. Pat. No. 6,147,009 to Grill, et al. which is incorporated herein by reference. The deposition temperature for forming layer  40  may be below 900° C. The thickness of the encapsulation layer is in the range from 5 nm to about 500 nm. Encapsulation layer  40  functions to protect upper surface  32  of layer  30  or to provide an isolation layer. 
   In  FIG. 2 , a second substrate  80  is bonded to upper surface  32  of layer  30  or to upper surface  42  of layer  40 . Prior to wafer bonding, surface  32  of layer  30  or surface  42  of layer  40  is polished by a Chemo-Mechanical Planarization or Polishing (CMP) process to smooth surface  42  to a planar surface having a surface roughness in root mean square (RMS) in the range from about 0.3 nm to about 1 nm. Substrate  80  which may be a semiconductor such as Si, SiGe, SiGeC, SiC, sapphire, glass, ceramic, or metal and has an upper surface  90  which may be polished as above to provide a smooth upper surface  90  having a RMS in the range from about 0.3 nm to about 1 nm. 
   For a further description on polishing to reduce surface roughness, reference is made to Ser. No. 09/675,841 filed Sep. 29, 2000 by D. F. Canaperi et al. entitled “A Method of Wafer Smoothing for Bonding Using Chemo-Mechanical Polishing (CMP)” which is incorporated herein by reference. 
   For a further description on bonding wafers to provide a bonded structure, reference is made to Ser. No. 09/675,840 filed Sep. 29, 2000 by D. F. Canaperi et al. entitled “Preparation of Strained Si/SiGe on Insulator by Hydrogen Induced Layer Transfer Technique” which is incorporated herein by reference. The method of making SGOI by wafer bonding and H-implantation induced layer transfer is described in Ser. No. 09/675,840. This method can produce SiGe with higher Ge content onto an insulator compared to the prior art. Further, this method can reduce the amount of defects in th SiGe layer due to the elimination of the misfit dislocations compared to the prior art. However, with this method, the transferred SiGe layer is relatively thin (&lt;1 μm) and transferring a high Ge content layer is still difficult to achieve due to implantation of H and annealing at 500 to 600° C. to induce layer transfer. 
   The top surface  42  of layer  40  shown in  FIG. 1  is turned upside down and brought into contact with surface  90  of substrate  80 . The two surfaces  42  and  90  are brought together by the wafer bonding approach. The bonded surfaces or  42  and  90  are annealed at a temperature in the range from about 20° C. to about 500° C. for a time period in the range from about 2 hours to about 50 hours. Another embodiment uses intermediate layers such as Ge, or metal materials which either have a low-melting point or react with silicon to form a silicide such materials may be tungsten (W), cobalt (Co), titanium (Ti) etc. to achieve high bonding strength at anneal temperatures in the range from 100° to 800° C. The anneal can be either a furnace anneal or a rapid thermal anneal (RTA). 
     FIG. 3  shows the removal of the majority of the first substrate  10  which is in the range from about 600 μm to about 750 μm in thickness with a grinding or combination of grinding and polishing process. The remaining layer  70  of the first substrate  10  has a thickness in the range from about 50 μm to about 100 μm. 
     FIG. 4  shows the removal of layer  70  such as with a wet etching process in a solution of ethylenediamine, pyrocatechol, pyrazine, water (EPPW or EDP) at a temperature in the range from about 90° C. to about 120° C. or in a solution of 20% KOH at a temperature in the range from about 70 to about 85° C. or in another organic Si etch solution of TMAH (tetramethyl ammoniumhydroxide, (CH 3 ) 4 NOH). The etching selectivity of Si (100) to Si 1-x Ge x  (y=0.15˜0.3) in EPPW is experimentally determined to be in the range of 50-1800. The etching selectivity of Si (100) to Si 1-x Ge x  (y=0.2˜0.3) in KOH is experimentally determined to be in the range of 350-1280, and the etching selectivity of Si (100) to Si 1-x Ge x  (y=0.2˜0.3) in TMAH is experimentally determined to be in the range of 50-115. In a prior art of U.S. Pat. No. 5,476,813 which issued Dec. 19, 1995 to H. Naruse by a mixed solution of KOH, K 2 Cr 2 O 7 , and propanol is used for selective etching of silicon while stopping at SiGe layer. However, a much lower selectivity of about 17 to 20 is achieved. In our invention, EPPW, KOH or TMAH has a much higher etching rate of Si compared to Si 1-y Ge y  (y&gt;0.1), as a result, the etching process stops nicely at the relaxed Si 1-y Ge y  without any additional etch-stop layer such as the p ++  SiGe etch-stop as described in U.S. Pat. No. 5,906,951 which issued May 25, 1999 to J. O. Chu et al. 
     FIG. 5  shows the cross-section view of a SiGe layer on insulator or a SiGe/Si heterostructure after applying a CMP process step to remove the step-graded Si 1-x Ge x  layer  20 . The structure has relaxed Si 1-y Ge y  layer  30  on top. The chemical-mechanical planarization (CMP) process is used to remove the graded Si 1-x Ge x  layer  20  and to adjust the thickness of the transferred relaxed Si 1-y Ge y  layer  30 . A final touch polishing and cleaning is used to smooth and clean the surface for epitaxial growth of strained Si/SiGe or for the deposition of a layer of n +  Si as needed for forming a p-i-n photodetector. 
   In  FIG. 6 , a layer  60  of strained Si/SiGe or of n +  Si is epitaxially grown or formed over SiGe layer  30 . For the epitaxial growth of strained Si/SiGe layer, an optional epitaxial SiGe buffer layer  72  over layer  30  may be needed before the growth of the strained Si/SiGe layer  60 . 
   It should be noted in the drawing that like elements or components are referred to by like and corresponding reference numerals. 
   While there has been described and illustrated a method for forming strained Si or SiGe on SiGe on insulator (SGOI) or strained SiGe/Si heterostructure using wafer bonding and wet etching, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.