Abstract:
Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

Description:
[0001]    This application is a divisional of Ser. No. 11/374,939 filed on Mar. 14, 2006, which was a divisional of Ser. No. 10/905,980; filed on Jan. 28, 2005, now U.S. Pat. No. 7,071,047. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the field of integrated circuit manufacture; more specifically, it relates to methods of forming buried isolation regions in semiconductor substrates and methods of forming semiconductor devices with buried isolation. 
       BACKGROUND OF THE INVENTION 
       [0003]    Conventional methods of fabricating silicon on insulator (SOI) substrates, such as subjecting silicon wafers to oxygen ion implantation or oxygen plasmas suffer from relatively high defect levels in the buried oxide (BOX) layer so formed. Additionally, for some applications the buried oxide layer inhibits optimum operation of devices formed in the silicon layer. Therefore, there is a need for improved methods of forming buried isolation regions in semiconductor substrates and for methods of forming semiconductor devices with buried isolation and still provide optimum operation of the devices. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention utilizes nano-masking techniques to create nano-openings in specific regions of a semiconductor substrate or an insulating layer on the semiconductor substrate. Various semiconductor processes are then performed using the nano-openings to generate or modify a buried insulating layer in the semiconductor substrate. 
         [0005]    A first aspect of the present invention is a method of forming a semiconductor structure, comprising: (a) providing a single crystal silicon substrate; (b) forming a hard mask layer on a top surface of the substrate; (c) forming a nano-mask layer on a top surface of the hard mask layer without performing a photolithographic process, the nano-mask layer having a masking pattern; (d) etching the masking pattern into the hard mask layer to form a patterned hard mask layer having openings, the openings extending from a top surface of the patterned hard mask layer to the top surface of the substrate, wherein the openings, distances between the openings, or both the openings and the distances between the openings independently have at least one spatial extent extending parallel to the top surface of the patterned hard mask layer; and (e) after removing the nano-mask layer, forming a single crystal group IV semiconductor layer on a top surface of the patterned hard mask layer, the single crystal group IV semiconductor layer filling the openings in the patterned hard mask layer. 
         [0006]    A second aspect of the present invention is a method of forming a semiconductor structure, comprising: (a) providing a single crystal silicon substrate; (b) forming a dummy gate on a top surface of the substrate; (c) forming a nano-mask layer on a top surface of the substrate and on a top surface of the dummy gate without performing a photolithographic process, the nano-mask layer having a masking pattern; (d) etching the masking pattern into the substrate wherever the substrate is not covered by the dummy gate to form a patterned silicon region having openings in the substrate, the openings extending from a top surface of the substrate a predetermined distance into the substrate, wherein the openings, distances between the openings, or both the openings and the distances between the openings independently have at least one spatial extent extending parallel to the top surface of the patterned layer; (e) after removing the nano-mask layer, forming a protective layer on the top surface of the substrate and on sidewalls of the openings; (f) oxidizing the substrate exposed in bottoms of the openings to form a buried patterned silicon dioxide layer; g) removing the protective layer from the sidewalls of the openings; and (h) filling the openings with a single crystal group IV semiconductor material. 
         [0007]    A third aspect of the present invention is a method of forming a semiconductor structure, comprising: (a) providing a single crystal silicon substrate; (b) forming a dummy gate on a top surface of the substrate; (c) forming a nano-mask layer on a top surface of the substrate and on a top surface of the dummy gate without performing a photolithographic process, the nano-mask layer having a masking pattern; (d) etching the masking pattern into the substrate wherever the substrate is not covered by the dummy gate to form openings in the substrate, the openings extending from a top surface of the substrate a predetermined distance into the substrate, wherein the openings, distances between the openings, or both the openings and the distances between the openings independently have at least one spatial extent extending parallel to the top surface of the patterned layer; and (e) annealing the substrate to reflow silicon adjacent to the top surface of the substrate, sealing off the openings from the top surface of the substrate and coalescing the openings into buried voids. 
         [0008]    A fourth aspect of the present invention is a semiconductor structure, comprising: a substrate comprising a silicon lower layer, a patterned buried oxide layer on a top surface of the silicon lower layer, the patterned buried oxide layer having openings, the openings extending through the patterned oxide layer, the openings filled with a single crystal group IV semiconductor material, wherein a width of the openings, a distance between the openings, or both the width of the openings and the distances between the openings independently have at least one spatial extent less than a photolithographic definable dimension, the at least one spatial extent extending parallel to a top surface of the substrate; a single crystal group IV semiconductor layer on top of the patterned and filled buried oxide layer; a gate dielectric on the top surface of the silicon substrate; a gate electrode on a top surface of the gate dielectric; and a source and a drain in the substrate and on opposite sides of the gate electrode. 
         [0009]    A fifth aspect of the present invention is a semiconductor structure, comprising: a silicon substrate; a gate dielectric on a top surface of the silicon substrate; a gate electrode on a top surface of the gate dielectric; a source and a drain in the substrate and on opposite sides of the gate electrode; and a first void or group of voids in the substrate under the source and a second void or group of voids in the substrate under the drain. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0011]      FIGS. 1A through 1H  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor substrate according to a first embodiment of the present invention; 
           [0012]      FIGS. 2A through 2E  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor substrate according to a second embodiment of the present invention; 
           [0013]      FIGS. 3A through 3E  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor device in a semiconductor substrate according to a third embodiment of the present invention; 
           [0014]      FIGS. 4A through 4L  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor device in a semiconductor substrate according to a fourth embodiment of the present invention; and 
           [0015]      FIGS. 5A through 5J  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor device in a semiconductor substrate according to a fifth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    All of the nano-mask layers utilized by the present invention are formed without photolithographic processing. A photolithographic process is one in which a pattern is formed in a photoresist layer by exposing the resist layer to energy that will create a pattern in the resist layer through either a photo-mask using light wavelength radiation (i.e., visible or ultra-violet) or X-ray radiation, or by direct write (i.e., without a mask) of the pattern into the photoresist with an electron beam. An image development process step is often required as well in photolithographic processing. Nano-mask layers often have patterns wherein one or more of the features of the pattern (i.e., a opening width, an island width, a distance between islands or a distance between openings) have a dimension that is less than that obtainable by conventional photolithographic processes. These dimensions are specified as being in the “nanometer” range and, in one example, are between about 2 nm to about 100 nm. 
         [0017]      FIGS. 1A through 1H  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor substrate according to a first embodiment of the present invention. In  FIG. 1A , a silicon substrate  100  has been exposed to a high power oxygen implantation to create an oxygen rich layer  105  a distance D 1  from a top surface  110  of substrate  100  into the substrate. Oxygen rich layer  105  defines an upper portion of silicon substrate  100  as a silicon layer  115  between the oxygen rich layer and the top surface of the substrate. Oxygen rich layer  105  may contain regions of silicon dioxide. As the exact stoichiometry of oxides of silicon can vary somewhat in semiconductor structures, for the purposes of the present invention, the term silicon dioxide includes compounds of silicon and oxygen having the specific formulas SiO 2  as well as the general formula Si x O y . In one example, distance D 1  is about 20 nm to about 100 nm. 
         [0018]    In  FIG. 1B , a hard mask layer  120  is formed on top surface  110  of substrate  100 . In one example, hard mask layer  120  comprises silicon nitride about 50 nm thick. A nano-mask  125  is formed on a top surface  130  of hard mask layer  120 . Nano-mask layer  125  comprises void regions  135  extending from a top surface  140  of nano-mask layer  125  to top surface  130  of hard mask layer  120  and solid regions  145 . In a first example void regions  135  are holes in a continuous solid region  145 . In a second example, solid regions  145  are islands surrounded by void region  135 . Void regions  135  have at least one spatial extent of dimension D 2  in a direction parallel to top surface  110  of substrate  100  and solid regions  145  have at least one spatial extent of dimension D 3  in a direction parallel to top surface  110  of substrate  100 . In a first example, D 2  and D 3  are each independently between about 2 nm and about 100 nm. In a second example, D 2  and D 3  are each independently between about 2 nm and about 50 nm. 
         [0019]    Two examples of methods of forming layers that may be used as nano-mask are as follows. The first method of forming nano-mask layers utilizes block copolymers. Block copolymers include two or more chemically distinct polymer chains covalently linked to form a single molecule. Owing to mutual repulsion, block copolymers tend to segregate into different domains and self-organized microstructures emerge from which one copolymer can be selectively removed. The second method of forming nano-mask layers utilizes nano-crystals. 
         [0020]    In a first block copolymer example, a polymethylmethacrylate (PMMA) in polystyrene (PS) copolymer is spin applied on a surface and then heated to between about 100° C. to about 400° C. to drive off the PMMA polymer or portions thereof in order to form a nano-mask layer. Alternatively, the PMMA can be removed by use of a solvent that preferentially dissolves PMMA over PS. Prior to removal of the PMMA, the PMMA/PS copolymer layer may be vertically orientated into cylindrical domains perpendicular the to the surface which the PMMA/PS copolymer has been applied in an electric field. 
         [0021]    In a second block copolymer example a PMMA/PS copolymer layer can be made to self-assemble into a hexagonally packed array of PMMA cylinders in a polystyrene matrix. The PMMA cylinders can be made to orient normal to the plane of the film by, among other known means, spin-coating a dilute polymer solution in toluene, or other solvent, onto the substrate and annealing the resulting film. The PMMA cylinders are then removed by exposure to electron-beam or ultraviolet radiation and dissolution in acetic acid or other effective solvent. The resulting nano-mask layer typically has hexagonally packed holes about 20 nanometers in maximum width (or diameter). By controlling the molecular weights and relative ratios of the two polymer blocks, one can control the hole size range from about 2 nanometers up to about 100 nanometers and the hole separations from about 2 nanometers up to about 100 nanometers. 
         [0022]    In a third block copolymer example, PS/polybutadiene (PB) block copolymer is used as a starting material for a nano-mask layer. The PS/PB block copolymer self-assembles into a hexagonally packed array of PB cylinders embedded in a PS matrix. The PB cylinders are made to orient normal to the plane of the nano-mask layer that will be produced by, among other known means, spreading a drop of dilute PS/PB block copolymer solution in toluene, or like solvent, onto the surface of a de-ionized water bath and allowing the toluene to evaporate. This leaves behind a film typically about 100 to about 200 nm thick, which may then be deposited upon a surface to be nano-masked. The PB cylinders are then removed by annealing and reaction with ozone, which reacts more rapidly with the PB than with the PS, thereby leaving behind a nano-mask layer with holes typically about 13 nm in maximum width (or diameter. By controlling the molecular weights of the copolymers, one can control the hole size to range from about 2 to about 100 nanometers in maximum width (or diameter) and spaced from about 2 to about 100 nanometers apart. 
         [0023]    In a fourth block copolymer example, a PS/PB block copolymer layer (as described in the third block copolymer example supra) is treated with OsO 4 , which selectively binds to the PB cylinders. This now causes ozone to attack the PS component at a faster rate than PB, thereby leaving behind a pattern of islands instead of holes. 
         [0024]    In a fifth block-copolymer example, a PS/polyisoprene (PI) block copolymer is used. The PS/PI block copolymer is similar to the PS/PB block copolymer described in the third and fourth block-copolymer examples supra, except that the PI self-assembles into spheres instead of cylinders. Hence, there is no need to orient the PI component normal to the plane of the nano-mask layer that will be produced. PS-PI films may also be treated with OSO 4  to create an inverted pattern. 
         [0025]    In a sixth block-copolymer example, a PS/poly(styrene-b-ferrocenyldimethysiliane) (PFS) block copolymer is spin applied and the PS removed by oxygen reactive ion etching (RIE) to form islands of PFS. 
         [0026]    In a first nano-crystal example, a polymaleic anhydride polymer layer is pulse plasma deposited on a surface to be nano-masked, The polymer surface is then treated with an alkanethiol solution such as a mixture of about 0.0008% by volume 1,6-hexanedithiol, about 12% by volume aqueous ammonia (35% by weight) and about 88% by volume 2-propanol in darkness at room temperature. After rinsing, the treated surface is immersed in a toluene solution containing about 0.016% by weight CdSe nano-crystals in darkness at room temperature during which time CdSe nano-crystals attach to the treated surface. In one example, CdSe nano-crystals of about 2.4 to about 4 nm may be used. 
         [0027]    In a second nano-crystal example, CdS nano-crystals are substituted for CdSe nano-crystals. 
         [0028]    While several examples of nano-mask preparation have been given, any nano-mask layer comprising islands of material about 2 nm to about 100 nm in width (or diameter) spaced about 2 nm to about 100 nm apart or comprising a material having voids, extending from a top surface to a bottom surface of the nano-mask layer, about 2 nm to about 100 nm in width (or diameter) and spaced about 2 nm to about 100 nm apart may be used to practice the present invention provided the material is sufficiently resistant to the etch process that will transfer the nano-mask pattern into an underlying material may be used. 
         [0029]    In  FIG. 1C , hard mask layer  120  (see  FIG. 1B ) is removed (for example by a RIE process) to form a patterned hard mask layer  120 A and expose silicon substrate  100  wherever the hard mask layer is not protected by patterned nano-mask layer  125 . The nano-mask layer pattern is thus transferred to the hard mask layer. 
         [0030]    In  FIG. 1D , nano-mask layer  125  (see  FIG. 1C ) is removed and a patterned silicon layer  115 A is formed (for example by RIE stopping on oxygen rich layer  105 ) wherever silicon layer  115  (see  FIG. 1C ) was not protected by patterned hard mask layer  120 A. Patterned silicon layer  115 A comprises void regions  161 , extending from a top surface  162  of patterned silicon layer  115 A to oxygen rich layer  105 , and solid regions  163 . In a first example void regions  161  are holes in a continuous solid region  163 . In a second example, solid regions  163  are islands surrounded by void region  161 . Void regions  161  have at least one spatial extent of dimension D 2  in a direction parallel to top surface  162  of solid regions  163  and solid regions  163  have at least one spatial extent of dimension D 3  in a direction parallel to top surface  162  of solid region  163 . Values for D 2  and D 3  have been described supra. 
         [0031]    In  FIG. 1E , silicon nitride spacers  150  are formed on exposed sidewalls  155  of solid regions  163 . Spacers  150  may be formed by deposition of a conformal silicon nitride layer followed by an RIE selective to etch silicon nitride over silicon dioxide and silicon. In one example, the conformal silicon nitride layer is between about 2 nm and about 5 nm thick. After formation of spacers  150 , a thermal oxidation is performed to transform oxygen rich layer  105  (see  FIG. 1D ) into a buried oxide layer  105 A. In one example thermal oxidation is performed in an oxygen, water vapor or oxygen/water vapor atmosphere at about 1000° C. to about 1200° C. for about 10 milliseconds to about 600 seconds. 
         [0032]    In  FIG. 1F , patterned hard mask layer  120 A (see  FIG. 1E ) and spacers  150  (see  FIG. 1E ) are removed and a single crystal group IV semiconductor layer  160  is formed. Group IV semiconductor layer  160  may comprise silicon, germanium or a mixture of silicon germanium denoted by the formula Si x Ge y  where x=0 to 1 and y=1−x. When x=0, group IV semiconductor layer  160  contains germanium but no silicon. When x=1, group IV semiconductor layer  160  contains silicon but no germanium. In one example, poly-Si x Ge y  is deposited and converted to a single crystal layer by annealing in hydrogen at about 850° C. using patterned silicon layer  115 A as a seed layer. A single crystal silicon seed (layer) allows (at relatively high temperatures such as used during epitaxial deposition or during 850° C. or higher temperature anneals) the silicon seed (layer) and silicon deposited on the silicon seed (layer) to coalesce into a single silicon layer having the same single crystal structure as the silicon seed (layer) had. In another example, epitaxial Si x Ge y  is grown using patterned silicon layer  115 A as a seed layer followed by a hydrogen anneal at about 850° C. In both examples a relatively defect free group IV semiconductor layer  160  over relatively defect free buried oxide layer  105 A results, however, the epitaxial example generally produces a more defect free Si x Ge y  layer. Alternatively, a combination laser anneal and thermal anneal in hydrogen may be performed. 
         [0033]    In  FIG. 1G , the anneals performed supra relative to  FIG. 1F  result in patterned silicon layer  115 A (see  FIG. 1F ) and group IV semiconductor layer  160  (see  FIG. 1F ) coalescing into a single layer having the same single crystal structure as silicon layer  115  (see  FIG. 1A ) had. A chemical-mechanical-polish (CMP) of group IV semiconductor layer  160  (see  FIG. 1F ) is performed to form a single crystal group IV semiconductor layer  165 . If single crystal group IV semiconductor layer  160  (see  FIG. 1F ) contained germanium, then single crystal group IV semiconductor layer  165  will contain silicon and germanium. A top surface  166  of buried oxide layer  105 A is a distance D 4  below a top surface  167  of group IV semiconductor layer  165 . In one example D 4  is about 20 nm to about 300 nm. Thus, a silicon-on-insulator (SOI) substrate has been fabricated. 
         [0034]    In  FIG. 1H , a source  170 , drain  175  and channel region  180  of a field effect transistor (FET)  185  have been formed in group IV semiconductor layer  165 . Trench isolation  190  has also been formed in group IV semiconductor layer  165 . A gate dielectric  195  and a gate electrode have been formed over channel region  180 . Gate electrode  200  is illustrated with optional insulating sidewall spacers  205  and an insulating capping layer  210 . 
         [0035]      FIGS. 2A through 2E  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor substrate according to a second embodiment of the present invention. In  FIG. 2A , a silicon dioxide layer  215  is formed on a top surface  220  of a silicon substrate  225 . In one example silicon dioxide layer  215  is about 5 nm to about 100 nm thick. 
         [0036]    In  FIG. 2B , nano-mask layer  125  is formed on top surface  230  of silicon dioxide layer  215 . Nano-mask layer  125  has been described supra in relationship to the first embodiment of the present invention. 
         [0037]    In  FIG. 2C , silicon dioxide layer  215  (see  FIG. 2B ) is removed (for example by a RIE process) to form a patterned silicon dioxide layer  215 A and exposing silicon substrate  225  wherever the silicon dioxide layer  215  is not protected by nano-mask layer  125 . Patterned silicon dioxide layer  215 A comprises void regions  231  extending from a top surface  232  of patterned silicon layer  215 A to top surface  220  of substrate  225  and solid regions  233 . In a first example void regions  231  are holes in a continuous solid region  233 . In a second example, solid regions  233  are islands surrounded by void region  231 . Void regions  231  have at least one spatial extent of dimension D 2  in a direction parallel to top surface  232  of solid regions  233  and solid regions  233  have at least one spatial extent of dimension D 3  in a direction parallel to top surface  232  of solid region  233 . Values for D 2  and D 3  have been described supra. 
         [0038]    In  FIG. 2D , nano-mask layer  125  (see  FIG. 2C ) is removed and single crystal group IV semiconductor layer  235  is formed using exposed silicon substrate  225  as a seed. Group IV semiconductor layer  235  may comprise silicon, germanium or a mixture of silicon germanium denoted by the formula Si x Ge y  where x=0 to 1 and y=1−x. When x=0, group IV semiconductor layer  235  contains germanium but no silicon. When x=1, group IV semiconductor layer  235  contains silicon but no germanium. In one example, poly-Si x Ge y  is deposited and converted to a single crystal layer by annealing in hydrogen at about 850° C. followed by a CMP. In another example, epitaxial Si x Ge y  is grown using patterned silicon layer  215 A as a seed layer followed by annealing in hydrogen at about 850° C. followed by a CMP. Again, the epitaxial example generally produces a more defect free silicon layer. Alternatively, a combination laser anneal and thermal anneal in hydrogen may be performed. A top surface  236  of patterned buried oxide layer  215 A is a distance D 4  below a top surface  237  of group IV semiconductor layer  235 . In one example D 4  is about 20 nm to about 300 nm. Thus, a silicon-on-insulator (SOI) or Si x Ge y -on-insulator substrate has been fabricated, though the insulator portion is not continuous. 
         [0039]    In  FIG. 2E , source  170 , drain  175  and channel region  180  of a FET  185 A have been formed in group IV semiconductor layer  235 . Trench isolation  190  has also been formed in group IV semiconductor layer  235 . An optional well  240  has been formed in substrate  225 . Wells are regions of substrates doped, for example, by ion implantation in which the diffused portions of FETs are fabricated. Optional well  240  may extend part way under trench isolation  190 . Gate dielectric  195  and gate electrode  200  have been formed over channel region  180 . Gate electrode  200  is illustrated with optional insulating sidewall spacers  205  and insulating capping layer  210 . The openings in silicon dioxide layer  215 A allow direct contact between group IV semiconductor layer  235  and substrate  225 , thus providing improved cooling and body potential control of FET  185 A. 
         [0040]      FIGS. 3A through 3E  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor device in a semiconductor substrate according to a third embodiment of the present invention. In  FIG. 3A , silicon dioxide layer  215  is formed on a top surface  220  of a silicon substrate  225 . In one example, silicon dioxide layer  215  is about 5 nm to about 100 nm thick. A silicon nitride layer  245  is formed on top surface  230  of silicon dioxide layer  215 . In one example, silicon nitride layer  245  is about 50 nm to about 100 nm thick. An opening  250  is formed in silicon nitride layer  245  exposing silicon dioxide layer  215  in the opening. 
         [0041]    In  FIG. 3B , nano-mask  125  is formed on a top surface  230  of silicon dioxide layer  215 . Nano-mask layer  125  has been described supra in relationship to the first embodiment of the present invention. 
         [0042]    In  FIG. 3C , silicon dioxide layer  215  (see  FIG. 3B ) is removed (for example by a RIE process selective to silicon nitride) to form a patterned silicon dioxide layer  215 B and exposing silicon substrate  225  wherever the silicon dioxide layer is not protected by nano-mask layer  125 . Patterned silicon dioxide layer  215 B comprises void regions  251  extending from a top surface  252  of patterned silicon layer  215 B to top surface  220  of substrate  225  and solid regions  253 . In a first example void regions  251  are holes in a continuous solid region  253 . In a second example, solid regions  253  are islands surrounded by void region  251 . Void regions  251  have at least one spatial extent of dimension D 2  in a direction parallel to top surface  232  of solid regions  253  and solid regions  253  have at least one spatial extent of dimension D 3  in a direction parallel to top surface  252  of solid region  253 . Values for D 2  and D 3  have been described supra. 
         [0043]    In  FIG. 3D , nano-mask layer  125  (see  FIG. 3C ) and nitride layer  245  are removed and single crystal group IV semiconductor layer  235  is formed using exposed silicon substrate  225  as a seed. In one example, poly-Si x Ge y  is deposited and converted to a single crystal layer by annealing in hydrogen at about 850° C. followed by a CMP. In another example, epitaxial Si x Ge y  is grown using substrate  225  as a seed layer followed by annealing in hydrogen at about 850° C. followed by a CMP. Again, the epitaxial example generally produces a more defect free silicon layer. Alternatively, a combination laser anneal and thermal anneal in hydrogen may be performed. Top surface  266  of patterned buried oxide layer  215 B is a distance D 4  below a top surface  267  of group IV semiconductor layer  235 . In one example D 4  is about 20 nm to about 300 nm. Thus, a silicon-on-insulator (SOI) substrate has been fabricated, though the insulator portion is not continuous. 
         [0044]    In  FIG. 3E , source  170 , drain  175  and channel region  180  of a FET  185 C have been formed in group IV semiconductor layer  235 . Source  170  and drain  175  are aligned over second regions  265  of patterned silicon dioxide layer  215 B and channel region  180  and gate electrode  200  are aligned over (island or voided) first region  260  of patterned oxide layer  215 B. Trench isolation  190  has also been formed in group IV semiconductor layer  235 . An optional well  240  has been formed in substrate  225 . Optional well  240  may extend part way under trench isolation  190  and is doped opposite to the doping type of substrate  225  and/or to a different doping concentration. Gate dielectric  195  and gate electrode  200  have been formed over channel region  180 . Gate electrode  200  is illustrated with optional insulating sidewall spacers  205  and insulating capping layer  210 . The openings in silicon dioxide layer  215 B allow direct contact between group IV semiconductor layer  235  and substrate  225 , thus providing improved cooling and body potential control of FET  185 B. It should be noted that first region(s)  260  may extend partially under source  170  and/or drain  175  and that second region(s)  265  may extend partially under gate electrode  200 . 
         [0045]      FIGS. 4A through 4L  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor device in a semiconductor substrate according to a fourth embodiment of the present invention. In  FIG. 4A , trench isolation  190  and optional well  240  are formed in a silicon substrate  270 . 
         [0046]    In  FIG. 4B , a dummy gate  280  is formed on a top surface  275  of substrate  270  over optional well  240 . In one example, dummy gate  280  comprises tungsten, hafnium, or tantalum or polysilicon. Dummy gate  280  should comprise a material resistant to the temperatures of subsequent oxidation and anneal processes. Dummy gate  280  may comprise several layers, for example a layer of silicon dioxide in contact with optional well  240  and a layer of tungsten over the oxide and, if desired, a silicon nitride cap. Dummy gate  280  may be encapsulated with a material to prevent oxidation of the dummy gate during subsequent oxidation processes. In one example, a silicon nitride layer is formed over all exposed surfaces of dummy gate  280  to protect the dummy gate from subsequent processing steps. In one example, dummy gate  280  has a thickness of between about 50 nm and about 300 nm. A hard mask layer  290  is formed on top surface  275  of substrate  270  and a top surface  285  of dummy gate  280 . In one example, hard mask layer  290  is silicon dioxide or a layer of silicon nitride over a layer of silicon dioxide. 
         [0047]    In  FIG. 4C , nano-mask  125  is formed on a top surface  295  of silicon dioxide layer  290 . Nano-mask layer  125  has been described supra in relationship to the first embodiment of the present invention. 
         [0048]    In  FIG. 4D , silicon dioxide layer  290  (see  FIG. 4C ) is removed (for example by a RIE process) to form a patterned silicon dioxide layer  290 A and exposing silicon substrate  270  wherever the silicon dioxide layer is not protected by nano-mask layer  125 . Patterned silicon dioxide layer  290 A comprises regions of silicon dioxide and void regions formed completely through patterned silicon dioxide layer  290 A. The pattern and image dimensions of nano-mask layer  125  are transferred to patterned hard mask layer  290 A. 
         [0049]    Next, openings  300  are etched in silicon substrate  270  using, for example, a RIE process wherever silicon substrate  270  is not protected by patterned silicon dioxide layer  290 A. Openings  300  may comprise voids surrounding islands of silicon or voids formed in silicon substrate  270 . Patterned silicon dioxide layer  290 A comprises void regions openings  300  extending from a top surface  275  of substrate  270  a distance D 5  into the substrate and silicon regions  302 . In a first example openings regions  300  are holes in a continuous solid region  302 . In a second example, solid regions  302  are islands surrounded by openings region  300 . Openings  300  have at least one spatial extent of dimension D 2  in a direction parallel to top surface  301  of solid regions  302  and solid regions  302  have at least one spatial extent of dimension D 3  in a direction parallel to top surface  301  of solid region  302 . Values for D 2  and D 3  have been described supra. Openings  300  are etched to a depth D 5 . In one example D 5  is between about 20 nm to about 300 nm. Optionally, the nano-mask layer  125  may be removed after etching hard mask layer  290  but before etching silicon substrate  270 . 
         [0050]    In  FIG. 4E , nano-mask layer  125  (see  FIG. 4D ) has been removed and silicon nitride spacers  305  formed on sidewalls  310  of openings  300  and in  FIG. 4F , a patterned buried oxide layer  315  is formed by thermal oxidation of silicon exposed at bottoms  320  of openings  300 . In one example thermal oxidation is performed in an oxygen, water vapor or oxygen/water vapor atmosphere at about 1000° C. to about 1200° C. for about 5 minutes to about 60 minutes. 
         [0051]    In  FIG. 4G , silicon nitride spacers  305  (see  FIG. 4F ) are removed and epitaxial group IV semiconductor material selectively deposited in openings  300  forming an epitaxial or poly-group IV semiconductor nodules  322 . Group IV semiconductor nodules  322  may comprise silicon, germanium or a mixture of silicon germanium denoted by the formula Si x Ge y  where x=0 to 1 and y=1-x. When x=0, group IV semiconductor nodules  322  contain germanium but no silicon. When x=1, group IV semiconductor nodules  322  contain silicon but no germanium. A hydrogen anneal at about 850° C. is then performed in order to reflow silicon substrate  270  and the group IV semiconductor nodules  322 . The anneal process also removes defects from buried oxide layer  315 . 
         [0052]    In  FIG. 4H , the anneals performed supra relative to  FIG. 4G  result in group IV semiconductor nodules  322  (see  FIG. 4G ) and silicon substrate  270  coalescing into a single layer having the same single crystal structure as silicon substrate  270 . If group IV semiconductor nodules  322  (see  FIG. 4G ) contained germanium, then the regions of substrate  270  between oxide layer  315  and top surface  275  of substrate  270  will contain silicon and germanium. Any remaining traces of patterned hard mask layer  290 A (see  FIG. 4G ) are removed and in  FIG. 4I , source  170 , drain  175  are formed, for example, by ion implantation, and channel region  180  thus defined. A top surface  316  of patterned buried oxide layer  315  is a distance D 4  below top surface  275  of substrate  270 . In one example D 4  is about 20 nm to about 300 nm. It should be noted that buried oxide layer  315  does not extend appreciably under dummy gate  280 . 
         [0053]    In  FIG. 4J , a silicon dioxide layer  325  is blanket deposited and a CMP process performed to co-planarize a top surface  330  of silicon dioxide layer  325  and a (new) top surface  335  of dummy gate  280 . 
         [0054]    In  FIG. 4K , dummy gate  280  (see  FIG. 4J ) is removed and a gate dielectric layer  340  is deposited, followed by deposition of a gate conductor layer  345 . Alternatively a thin gate oxide may be thermally grown instead of depositing a gate dielectric. 
         [0055]    In  FIG. 4L , gate conductor layer  345  and gate dielectric layer  340  (see  FIG. 4K ) have been subjected to a CMP process to form a gate electrode  350 . A FET  185 D comprising source  170 , drain  175 , channel  180 , gate dielectric  340  and gate electrode  350  has thus been fabricated. The openings in buried oxide layer  315  allow direct contact between silicon layer channel region  180  and substrate  270 , thus providing improved cooling and body potential control of FET  185 D. It should be noted that buried oxide layer  315  may extend partially under gate electrode  200 . 
         [0056]      FIGS. 5A through 5J  are partial cross-sectional views illustrating the steps to form a buried isolation region in a semiconductor device in a semiconductor substrate according to a fifth embodiment of the present invention. In  FIG. 5A , trench isolation  190  and optional well  240  are formed in a silicon substrate  270 . 
         [0057]    In  FIG. 5B , dummy gate  280  is formed on a top surface  275  of substrate  270  over optional well  240 . In one example, dummy gate  280  comprises tungsten, hafnium, tantalum or polysilicon. Dummy gate  280  has been described supra, in reference to the fourth embodiment of the present invention. Dummy gate  280  may be encapsulated as well. In one example, a silicon nitride layer is formed over all exposed surfaces of dummy gate  280  to protect the dummy gate from subsequent processing steps. 
         [0058]    In  FIG. 5C , nano-mask  125  is formed on a top surface  295  of silicon dioxide layer  290 . Nano-mask layer  125  has been described supra in relationship to the first embodiment of the present invention. 
         [0059]    In  FIG. 5D , openings  300  are etched in silicon substrate  270  using, for example, a RIE process wherever silicon substrate  270  is not protected by patterned nano-mask layer  290 A. Alternatively, a hard mask layer may be used as in the fourth embodiment of the present invention to transfer nano-mask  125  pattern to silicon substrate  270 . In a first example openings regions  300  are holes in a continuous solid region  302 . In a second example, solid regions  302  are islands surrounded by openings region  300 . Openings regions  300  have at least one spatial extent of dimension D 2  in a direction parallel to top surface  301  of solid regions  302  and solid regions  302  have at least one spatial extent of dimension D 3  in a direction parallel to top surface  301  of solid region  302 . Values for D 2  and D 3  have been described supra. Openings  300  are etched to a depth D 5 . In one example D 5  is between about 20 nm to about 300 nm. 
         [0060]    Next, in  FIG. 5E , nano-mask layer  125  (see  FIG. 5D ) is removed. 
         [0061]    In  FIG. 5F , a hydrogen anneal at about 1100° C. is performed which cause the silicon substrate to flow and openings  300  (see  FIG. 5E ) to coalesce into voids  355  located on either side of dummy gate  280  a distance D 6  from top surface  275  of silicon substrate  270 . In one example, D 6  is about 20 nm to about 250 nm. While each void  355  are illustrated as a single cavity, each void  355  may comprise a void region (i.e. a group of adjacent individual cavities separated from one another by thin walls of silicon some of which cavities may be interconnected). 
         [0062]    In  FIG. 5G , source  170  and drain  175  are formed, for example, by ion implantation, and channel region  180  thus defined. It should be noted that voids  355  do not extend appreciably under dummy gate  280 . 
         [0063]    In  FIG. 5H , silicon dioxide layer  325  is blanket deposited and a CMP process performed to co-planarize top surface  330  of a silicon dioxide layer  325  and (new) top surface  335  of dummy gate  280 . 
         [0064]    In  FIG. 5I , dummy gate  280  (see  FIG. 5H ) is removed and gate dielectric layer  340  is deposited, followed by deposition of gate conductor layer  345 . Alternatively a thin gate oxide may be thermally grown instead of depositing a gate dielectric. 
         [0065]    In  FIG. 5J , gate conductor layer  345  and gate dielectric layer  340  (see  FIG. 5I ) have been subjected to a CMP process to form gate electrode  350 . An FET  185 E comprising source  170 , drain  175 , channel  180 , gate dielectric  340  and gate electrode  350  has thus been fabricated. The space between voids  355  allow direct contact between silicon layer channel region  180  and substrate  270 , thus providing improved cooling of FET  185 E. Additionally, there are no buried oxide defects to contend with. It should be noted that voids  355  may extend partially under gate electrode  350 . 
         [0066]    Thus, the present invention provides improved methods of forming buried isolation regions in semiconductor substrates and for methods of forming semiconductor devices with buried isolation and still provide cooling and control of body potential of the devices. 
         [0067]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.