Abstract:
A video processing method includes: reading a video signal including a plurality of first fields and a plurality of second fields, where the number of the first fields is different from the number of the second fields; and processing the plurality of first fields of the video signal and/or the plurality of second fields of the video signal to generate a plurality of first pictures and a plurality of second pictures, where the number of the first pictures is equal to the number of the second pictures.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to Telecine processing, and more particularly, to video processing methods capable of preventing rough movements of video objects, and related devices.  
         [0003]     2. Description of the Prior Art  
         [0004]     Movies are typically made and played at a speed of 24 frames per second. If a movie need to be played by a video playback device such as a television or a digital versatile disc (DVD) player, the video frames of the movie can be converted into video data of National Television System Committee (NTSC) format or Phase Alternating Line (PAL) format by utilizing Telecine processing.  
         [0005]     3:2 pull-down processing is a typical processing method of the Telecine processing mentioned above. Please refer to  FIG. 1 . After performing the 3:2 pull-down processing, a received video signal carrying the video frames of the movie is converted into NTSC format to generate interlace fields of 60 Hz, as shown in  FIG. 1 . If a portion of the original video frames of the movie is illustrated by utilizing a sequence {A, B, C, D} with A, B, C, and D of the sequence {A, B, C, D} respectively representing the contents of the video frames of the movie, a series of fields generated after performing the 3:2 pull-down processing can be represented by utilizing a sequence {A, A, A, B, B, C, C, C, D, D}, where the fields comprises even fields and odd fields. According to  FIG. 1 , within the same time interval for playing the contents A, B, C, and D of the original video frames of the movie, the contents A, B, C, and D of the odd or even fields are respectively played three times, two times, three times, and two times, meaning that after the 3:2 pull-down processing mentioned above, the contents A, B, C, and D are eventually displayed at varied display time points rather than the original display time points for playing the contents A, B, C, and D of the original video frames of the movie. Therefore, regarding a displayed video object moving around, rough movements of the video object lead to unfaithful playback.  
         [0006]     A conventional method attempting to solve the problem of rough movements of the video object according to the prior art is performing motion interpolation along the time axis, meaning that performing interpolation along the time axis to generate new images. For example, regarding a partial sequence {A, A, A, B, B} of the odd/even fields mentioned above, along the time axis, first cut the time interval corresponding to the contents A and B into five segments, and then perform interpolation on the contents A and B along the time axis to make each video object moving smoothly. Although this method may maintain the original refresh rate of 60 Hz, the calculation, cutting, and reconstruction along the time axis lead to heavy load of a software application program or hardware device implemented by utilizing this method. In addition, if a calculation error occurs, the coming display results may have an erroneous moving trace or an erroneous image.  
       SUMMARY OF THE INVENTION  
       [0007]     It is an objective of the claimed invention to provide video processing methods and devices that are capable of preventing rough movements of video objects, in order to achieve best image quality.  
         [0008]     According to one embodiment of the claimed invention, a video processing method is disclosed. The video processing method comprises the following steps: reading a video signal comprising a plurality of first fields and a plurality of second fields, where the number of the first fields is different from the number of the second fields; and processing the plurality of first fields of the video signal and/or the plurality of second fields of the video signal to generate a plurality of first pictures and a plurality of second pictures, where the number of the first pictures is substantially equal to the number of the second pictures, and the plurality of first pictures correspond to the plurality of first fields and the plurality of second pictures correspond to the plurality of second fields.  
         [0009]     According to one embodiment of the claimed invention, a video processing device is further disclosed. The video processing device comprises: a buffer comprising a plurality of buffering areas, where the plurality of buffering areas are utilized for storing an input video signal corresponding to a first refresh rate, the input video signal comprises a plurality of first fields and a plurality of second fields, and the number of the first fields is different from the number of the second fields; a buffering control circuit, coupled to the buffer, the buffering control circuit reading the fields from the buffering areas to generate an output video signal corresponding to a second refresh rate, where the output video signal comprises a plurality of first pictures and a plurality of second pictures, and the number of the first pictures is substantially equal to the number of the second pictures; and a frequency control circuit, coupled to the buffering control circuit, for controlling the ratio of the second refresh rate to the first refresh rate, where the ratio of the second refresh rate to the first refresh rate is equal to a first predetermined value.  
         [0010]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a diagram of 3:2 pull-down processing and the corresponding displayed pictures according to the prior art.  
         [0012]      FIG. 2  illustrates a video processing method for generating pictures while performing de-interlacing processing on a plurality of fields according to one embodiment of the present invention.  
         [0013]      FIG. 3  is a diagram of a video processing device of the embodiment shown in  FIG. 2 .  
         [0014]      FIG. 4  illustrates a video processing method for generating pictures while performing de-interlacing processing on a plurality of fields according to one embodiment of the present invention.  
         [0015]      FIG. 5  is a diagram of a video processing device of the embodiment shown in  FIG. 4 .  
     
    
     DETAILED DESCRIPTION  
       [0016]     Please refer to  FIG. 2  and  FIG. 3 .  FIG. 2  illustrates a video processing method for generating pictures while performing de-interlacing on a plurality of fields according to one embodiment of the present invention, where  FIG. 3  is a diagram of a video processing device of the embodiment shown in  FIG. 2 . The interlaced fields with refresh rate f 1  equal to 60 Hz is generated by performing the 3:2 pull-down processing shown in  FIG. 1  and carried by a video signal  208 . As mentioned above, the fields comprise a series of odd/even fields, which can be represented by utilizing a sequence {A 1 , A 2 , A 1 , B 2 , B 1 , C 2 , C 1 , C 2 , D 1 , D 2 }. Here, A 1 , B 1 , C 1 , and D 1  represent odd fields, and A 2 , B 2 , C 2 , and D 2  represent even fields. Within the video processing device shown in  FIG. 3 , a buffering control circuit  220  is capable of temporarily storing the odd/even fields in specific buffering areas in a buffer  210 . The buffering control circuit  220  is capable of reading the contents that are temporarily stored (i.e., the fields) from the buffering areas and performing the de-interlacing to generate another video signal  228  corresponding to another refresh rate f 2 . As shown in  FIG. 2 , the pictures generated by performing the de-interlacing processing can be represented by utilizing a new sequence {A, A, A, B, B, B, C, C, C, D, D, D}, where these pictures are carried by the video signal  228  and correspond to the refresh rate f 2 .  
         [0017]     A frequency control circuit  230  of the video processing device shown in  FIG. 3  is capable of controlling the ratio of the refresh rate f 2  to the refresh rate f 1 , where the ratio can be equal to a first predetermined value. In this embodiment, as the refresh rate f 1  is equal to 60 Hz and the refresh rate f 2  is equal to 72 Hz, the ratio of the refresh rate f 2  to the refresh rate f 1  is equal to 6/5 accordingly. That is, the first predetermined value is equal to 6/5. The refresh rate f 1  is a reciprocal of the refresh period T 5  shown in  FIG. 2 , and the refresh rate f 2  is a reciprocal of the refresh period T 6  shown in  FIG. 2 . According to this embodiment, the pictures generated by performing the de-interlacing processing is outputted by utilizing the refresh rate f 2  and represented by the sequence {A, A, A, B, B, B, C, C, C, D, D, D}. During the de-interlacing processing shown in  FIG. 2 , an additional picture B (a picture of the content B) and an additional picture D (a picture of the content D) are newly generated, whereby the number of pictures A is substantially equal to the number of pictures B, and the number of pictures C is substantially equal to the number of pictures D, where the rest may be deduced by analogy. As a result, each video object displayed by utilizing the pictures moves smoothly, and the problem of rough movements is solved.  
         [0018]     In addition, the frequency control circuit  230  of this embodiment is capable of switching the ratio of the refresh rate f 2  to the refresh rate f 1  between the first predetermined value and a second predetermined value (e.g., 4/5) when needed.  
         [0019]     Please refer to  FIG. 4  and  FIG. 5 .  FIG. 4  illustrates a video processing method generating pictures while performing de-interlacing on a plurality of fields according to another embodiment of the present invention, where  FIG. 5  is a diagram of a video processing device of the embodiment shown in  FIG. 4 . The interlaced fields with refresh rate f 1  equal to 60 Hz is generated by performing the 3:2 pull-down processing shown in  FIG. 1  and carried by a video signal  308 . As mentioned above, these fields can be represented by utilizing the sequence {A 1 , A 2 , A 1 , B 2 , B 1 , C 2 , C 1 , C 2 , D 1 , D 2 }. Within the video processing device shown in  FIG. 5 , a buffering control circuit  320  is capable of temporarily storing the odd/even fields in specific buffering areas in a buffer  310 . The buffering control circuit  320  is capable of reading the contents that are temporarily stored (i.e., the fields) from the buffering areas and performing the de-interlacing to generate another video signal  328  corresponding to another refresh rate f 3 . As shown in  FIG. 4 , the pictures generated by performing the de-interlacing can be represented by utilizing a new sequence {A, A, B, B, C, C, D, D}, where these pictures are carried by the video signal  328  and correspond to the refresh rate f 2 .  
         [0020]     A frequency control circuit  330  of the video processing device shown in  FIG. 5  is capable of controlling the ratio of the refresh rate f 3  to the refresh rate f 1 , where the ratio can be equal to a predetermined value. According to this embodiment, as the refresh rate f 1  is equal to 60 Hz and the refresh rate f 3  is equal to 48 Hz, the ratio of the refresh rate f 3  to the refresh rate f 1  is equal to 4/5 accordingly. The refresh rate f 1  is a reciprocal of the refresh period T 5  shown in  FIG. 4 , and the refresh rate f 3  is a reciprocal of the refresh period T 4  shown in  FIG. 4 . According to this embodiment, the pictures generated by performing the de-interlacing is outputted by utilizing the refresh rate f 3  and represented by the sequence {A, A, B, B, C, C, D, D}. During the de-interlacing processing shown in  FIG. 4 , a redundant picture A (a picture of the content A) and a redundant picture C (a picture of the content C) are discarded, whereby the number of pictures A is substantially equal to the number of pictures B, and the number of pictures C is substantially equal to the number of pictures D, where the rest may be deduced by analogy. As a result, each video object displayed by utilizing the pictures moves smoothly, and the problem of rough movements is solved.  
         [0021]     It is noted that in general, display devices that are typically utilized as monitors may have an upper bond of the refresh rate tolerance up to 75 Hz, so any of the video processing methods shown in  FIG. 2  and  FIG. 4  can be applied to these display devices. Regarding televisions, they may have an upper bond of the refresh rate tolerance up to 63 Hz and an lower bond of the refresh rate tolerance around 47 Hz, so the video processing method shown in  FIG. 4  can be applied to the televisions, i.e., converting the refresh rate into 48 Hz is a gradual implementation method, which is steadier, in contrast to converting the refresh rate into 72 Hz.  
         [0022]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.