Abstract:
A pulse amplifier implemented in standard CMOS, comprises a control circuit for controlling a driver stage for driving a class D output stage that comprises a first PMOS-transistor and a first NMOS-transistor with interconnected drain contacts. A driver stage comprises a first driver and a second driver coupled with the output stage. Furthermore, a second NMOS transistor and second to fifth PMOS transistors are provided and interconnected in a way that most of the control signals needed to switch the high voltage output, specifically the drivers, are generated within a low voltage block. These factors contribute to lowering the total power dissipation.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of copending International Application No. PCT/SE03/00820 filed May 21, 2003 which designates the United States, and claims priority to Swedish application no. 0201859-6 filed Jun. 17, 2002. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The invention relates generally to pulse amplifiers and more specifically to an arrangement for reducing power consumption in such amplifiers. 
     BACKGROUND OF THE INVENTION 
     In an ADSL (Asymmetric Digital Subscriber Line) modem, power consumption is a very important factor, especially on the Central Office (CO) side. If the power consumption can be lowered, the number of lines per line card can be increased without additional cooling. One of the large power consumers in an ADSL modem is the Line Driver (LD). The power efficiency of standard ADSL line drivers is quite low. 
     In an attempt to increase the power efficiency of line drivers, new methods of designing the line drivers have been investigated. 
     One of these methods involves using a class D amplifier. The output stage of the class D amplifier drives the modulated input signal onto the line through a low pass LC filter which demodulates the signal into a continuous ADSL signal. 
     Today, various techniques are used to implement class D amplifiers, but most use the same inverter-type of switching output stage. However, it is expensive to manufacture high-voltage components such as those needed to obtain the voltage levels required by ADSL. Thus, it would be advantageous if low-voltage components could be used instead. Also, solutions to date for class D implementations are designed for audio band frequencies (up to 4 kHz). DSL applications use much higher frequencies (several MHz). This places tougher requirements on speed in the class D implementation. 
     In ADSL, the maximum voltage amplitude needed on the line is 30 V peak-to-peak at the CO side with a PAR (Peak to Average Ratio) of 4.5. If a transformer is used, the voltage requirements on the output stage can be reduced. However, the output stage should still be able to handle relatively high voltages. The transformer turn ratio should be kept as low as possible since a high transformer turn ratio will increase the required output current and degrade the receive path. Higher currents lead to larger output transistors and hence larger power consumption in the drivers. 
     In a manner known per se, the class D output stage comprises an NMOS transistor and a PMOS transistor that must not be on at the same time. If both transistors were on at the same time, a high current would be obtained through the transistors. This high current would destroy the output stage or for shorter duration lead to power loss. 
     In order to ensure that the NMOS and PMOS transistors are not on at the same time, a time delay is introduced between the turn-off time of the NMOS transistor and the turn-on time of the PMOS transistor and vice versa. This so-called deadtime should be as short as possible since it leads to distortion. 
     The resistance of the output transistors when on should be as low as possible in order to reduce the power loss. 
     Since the ADSL line driver market is very competitive, small die sizes and relatively inexpensive manufacturing processes are important. 
     SUMMARY OF THE INVENTION 
     The object of the invention is to bring about an output stage driver implemented in a standard CMOS process, that is able to switch a high output voltage with a very short deadtime and that has a low total power consumption. 
     This is attained by the arrangement according to the invention in a pulse amplifier, implemented in standard CMOS, that comprises a control circuit for controlling a driver stage for driving a class D output stage that comprises a first PMOS transistor and a first NMOS transistor with interconnected drain contacts, the interconnection point constituting an output terminal of the pulse amplifier. The first PMOS transistor is connected with its source and bulk contacts to a first supply voltage terminal for a first supply voltage, and the first NMOS transistor is connected with its source contact to a second supply voltage terminal for a second, lower supply voltage. The driver stage comprises a first driver that is connected with its input terminal to a first output terminal of the control circuit and with its output terminal to a gate contact of the first NMOS transistor, and a second driver that is connected with its input terminal to a second output terminal of the control circuit and with its output terminal to a gate contact of a second NMOS transistor. The second NMOS transistor is connected with its source contact to said second supply voltage terminal and with its drain contact to a drain contact of a second PMOS transistor. The second PMOS transistor is connected with its source and bulk contacts to the interconnection point between a gate contact of the first PMOS transistor and a drain contact of a third PMOS transistor and to a drain contact of a fourth PMOS transistor and with its gate contact to a voltage node. The third PMOS transistor is connected with its bulk contact to said first supply voltage terminal, with its source contact to an interconnection point between a gate contact of the fourth PMOS transistor and a drain contact of a fifth PMOS transistor and with its gate contact to a first control voltage node. The fourth and fifth PMOS transistors are connected with their source and bulk contacts to said first supply voltage terminal, and the fifth PMOS transistor is connected with its gate contact to a second control voltage node. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The invention will be described more in detail below with reference to the appended drawing on which 
         FIG. 1  is a circuit diagram of an embodiment of an arrangement according to the invention in a pulse amplifier, and 
         FIGS. 2   a–f  are pulse diagrams in different nodes in the amplifier in  FIG. 1 . 
     
    
    
     DESCRIPTION OF THE INVENTION 
       FIG. 1  is a circuit diagram of an embodiment of an arrangement according to the invention in a pulse amplifier  1 . 
     The pulse amplifier  1  comprises a control circuit  2 , a driver stage  3  that is connected to the control circuit  2 , and a class D output stage  4  that is connected to the driver stage  3 . The pulse amplifier  1 , the control circuit  2 , the driver stage  3 , and the class D output stage  4  are all implemented in standard CMOS. 
     In a manner known per se, the output stage  4  comprises a PMOS transistor M 1  and an NMOS transistor M 2  with interconnected drain contacts. The interconnection point between the drain contacts of the transistors M 1 , M 2  constitutes an output terminal  10  of the pulse amplifier  1 . 
     Also in a manner known per se, the PMOS transistor M 1  is connected with its source and bulk contacts to a supply voltage terminal VDDH and the NMOS transistor M 2  is connected with its source contact to a supply voltage terminal VSS. The voltage supplied via the terminal VSS is lower than the voltage supplied via the terminal VDDH. 
     The control circuit  2  has one input terminal  5  and two output terminals  6 ,  7 . The input terminal  5  is connected to the input terminal of an inverter I 1  and to one input terminal of a NOR gate N 1  whose other input terminal is connected to the output terminal  6  of the control circuit  2 . The output terminal of the inverter I 1  is connected to one input terminal of a NOR gate N 2  whose other input terminal is connected to the output terminal  7  of the control circuit  2 . The output terminal of the NOR gate N 1  is connected to the output terminal  7  of the control circuit  2  via two series-connected inverters I 2 , I 3 . The output terminal of the NOR gate N 2  is connected to the output terminal  6  of the control circuit  2  via two series-connected inverters I 4 , I 5 . 
     The inverters I 1 –I 5  and the NOR gates N 1 , N 2  are all connected with their supply voltage terminals to a supply voltage terminal VDDL and the supply voltage terminal VSS. 
     The supply voltage terminal VDDL is to be at a lower potential than the supply voltage terminal VDDH. Hereby, the overall power dissipation is reduced. 
     In accordance with the invention, the driver stage comprises two drivers D 1 , D 2 . The driver D 1  is connected with its input terminal to the output terminal  6  of the control circuit  2  and with its output terminal to the gate contact of the NMOS transistor M 2 . The driver D 2  is connected with its input terminal to the output terminal  7  of the control circuit  2  and with its output terminal to the gate contact of an NMOS transistor M 7 . 
     In accordance with the invention, the drivers D 1 , D 2  are connected with their supply voltage terminals to the supply voltage terminal VDDL and the supply voltage terminal VSS. 
     The NMOS transistor M 7  is connected with its source contact to the supply voltage terminal VSS and with its drain contact to the drain contact of a PMOS transistor M 6 . 
     The PMOS transistor M 6  is connected with its source and bulk contacts to a voltage node X and with its gate contact to a voltage node E. 
     In the embodiment in  FIG. 1 , the voltage node X is connected to an interconnection point between the gate contact of the PMOS transistor M 1  and the drain contact of a PMOS transistor M 3 , and to the drain contact of a PMOS transistor M 5 . 
     The voltage node E is an interconnection point between one terminal of a resistor R 3  and one terminal of a parallel-connection of a resistor R 4  and a capacitor C 1 . The other terminal of the resistor R 3  is connected to the supply voltage terminal VDDH and the other terminal of the parallel-connection of the resistor R 4  and the capacitor C 1  is connected to the supply voltage terminal VSS. 
     The PMOS transistor M 3  is connected with its bulk contact to the supply voltage terminal VDDH, with its source contact to an interconnection point between the gate contact of the PMOS transistor M 5  and the drain contact of a PMOS transistor M 4  and with its gate contact to a control voltage node Y. 
     In the embodiment in  FIG. 1 , the control voltage node Y is an interconnection point between one terminal of a resistance element R 1  and interconnected source and bulk contacts of a PMOS transistor M 9 . The other terminal of the resistance element R 1  is connected to the supply voltage terminal VDDH. The PMOS transistor M 9  is connected with its gate contact to the voltage node E and with its drain contact to the drain contact of an NMOS transistor M 11 . The NMOS transistor M 11  is connected with its source contact to the supply voltage terminal VSS and with its gate contact to a control voltage node  9 . 
     In the embodiment in  FIG. 1 , the control voltage node  9  is an interconnection point between drain contacts of a PMOS transistor M 12  and an NMOS transistor M 14 . The source contact of the PMOS transistor M 12  is interconnected with the drain contact of a PMOS transistor M 13 . The bulk contact of the PMOS transistor M 12  is interconnected with the bulk and source contacts of the PMOS transistor M 13  to the supply voltage terminal VDDL. The gate contact of the PMOS transistor M 12  is connected to the output terminal  7  of the control circuit  2 . The source contact of the NMOS transistor M 14  is connected to the supply voltage terminal VSS, and the gate contacts of the PMOS transistor M 13  and the NMOS transistor M 14  are connected to the output terminal of the driver D 1 . 
     The PMOS transistors M 5 , M 4  are connected with their source and bulk contacts to the supply voltage terminal VDDH, and the PMOS transistor M 4  is connected with its gate contact to a control voltage node Z. 
     In the embodiment in  FIG. 1 , the control voltage node Z is an interconnection point between one terminal of a resistance element R 2  and interconnected source and bulk contacts of a PMOS transistor M 8 . The other terminal of the resistance element R 2  is connected to the supply voltage terminal VDDH. The PMOS transistor M 8  is connected with its gate contact to the voltage node E and with its drain contact to the drain contact of an NMOS transistor M 10 . The NMOS transistor M 10  is connected with its source contact to the supply voltage terminal VSS and with its gate contact  8  to the output terminal of the driver D 1 . 
     With reference to the pulse diagrams in  FIGS. 2   a–f , the function of the pulse amplifier in  FIG. 1  will now be described. 
       FIG. 2   a  illustrates an input pulse signal V 5  that is received on the input terminal  5  of the control circuit  2  and is to be amplified. 
     From the input pulse signal V 5 , the control circuit  2  generates a control pulse signal V 6  illustrated in  FIG. 2   b  on its output terminal  6  and a control pulse signal V 7  illustrated in  FIG. 2   c  on its output terminal  7 . 
     The control pulse signal V 6  in  FIG. 2   b  is used to control the NMOS transistor M 2  and the control pulse signal V 7  in  FIG. 2   c  is used to control the PMOS transistor M 1 . 
     In order for the NMOS transistor M 2  and the PMOS transistor M 1  not to be on at the same time, the control pulse signals V 6  and V 7  are generated by the control circuit  2  such that the pulses do not overlap, i.e. are not high at the same time, as apparent from  FIGS. 2   b  and  2   c.    
     With reference to the pulse diagram in  FIG. 2 , an embodiment of one period t 1 –t 12  of the amplifier in  FIG. 1  will be described. 
     At time t 1 , the input signal V 5  at node  5  switches from VDDL down to VSS. 
     At time t 2 , after a delay due to the logic gates N 2 , I 4  and I 5 , the control pulse signal V 6  at node  6  is forced down to VSS. 
     At time t 4 , after a delay due to the delay above and the logic gates N 1 , I 2  and I 3 , the control pulse signal V 7  at node  7  is forced up to VDDL. 
     Hence, two non-overlapping control pulse signals V 6 , V 7  are generated that first switch the transistor M 2  off and then turn the transistor M 1  on. The transistor M 2  is switched off directly by the driver D 1  and the transistor M 1  is switched on through the driver D 2  and the transistors M 7  and M 6 . 
     At time t 5 , the output signal V 10  at node  10  is pulled up to VDDH. 
     When the transistor M 7  is switched on by the driver D 2  node X will be pulled down towards VSS. However, the transistor M 6  will limit the current when node X approaches the potential of voltage node E, thus insuring that the gate-bulk voltage of the transistor M 1  is not exceeded. 
     At time t 3 , the output signal of the driver D 1  pulls the voltage V 8  at the gate contact node  8  of the transistor M 10  down from VDDL to VSS and switches off the transistor M 4  since resistor R 2  pulls node Z up to VDDH. The transistor M 4  is needed to keep the gate potential of the transistor M 5  at VDDH when the gate of the transistor M 1  is pulled down to VSS. 
     Hence, the output signal V 10  at node  10  has been switched to VDDH from VSS by the input signal V 5  at node  5  traversing from VDDL to VSS. 
     Likewise, when the input signal at node  5  switches from VSS up to VDDL at time t 6 , the two non-overlapping control signals V 6 , V 7  are generated in the same manner as above except that now, the signal V 7  at node  7  is switched down to VSS at time t 7  before the signal V 6  at node  6  is switched up to VDDL at time t 9 . 
     When node  7  is switched down to VSS, the transistor M 12  is turned on and since the potential in node  8  still is at VSS, the transistor M 3  is turned on through transistors M 11  and M 9  since node  9  is pulled up to VDDL at time t 8  by transistors M 12  and M 13 . 
     As the transistor M 3  starts to turn on, the potential at the gate of the transistor M 5  will fall down towards the potential at node X thus causing the transistor M 5  to turn on. The transistor M 5  will be on until is has pulled node X up to VDDH and turned M 1  off. 
     At time t 10 , the transistors M 2  and M 10  are switched on directly by driver D 1  and the output voltage V 10  at node  10  is pulled down to VSS at time t 12 . Driver D 1  also turns on transistor M 4 . 
     At time t 11 , the control voltage V 9  at node  9  is pulled down to VSS through the transistor M 14 . 
     Hence, the transistor M 3  is turned off since node Y is pulled up to VDDH by the resistor R 1  when the transistor M 11  is turned off. 
     Hence, the output signal V 10  at node  10  has been switched back to VSS from VDDH by the input signal V 5  on node  5  traversing from VSS to VDDL. 
     In this manner, a high output voltage VDDH at node  10  can be switched by a low voltage (VDDL) input signal V 5 . 
     Also, most of the control signals needed to switch the high voltage output, specifically the drivers, are generated within the low voltage block. 
     These factors contribute to lowering the total power dissipation. 
     The arrangement according to the invention can also be used in a so-called differential mode with two output terminals and two amplifier stages. In such an application, the same control circuit  2  as well as R 3 , R 4  and C 4  can be used for both amplifier stages. However, nodes  6  and  7  have to be interchanged so that node  6  is connected to M 7  of the second stage via a driver in that second stage and node  7  is connected to M 2  of the second stage also via a driver in that second stage. Thus, the second stage output will switch opposite to the first stage, i.e. when the first stage switches up to VDDH, the second stage switches down to VSS.