Abstract:
An electric circuit device connecting first and second external elements, the electric circuit device including: a first electronic component; a first bus bar electrically connected to the first electronic component; a second bus bar electrically connected to the electronic component and overlapped with the first bus bar in a direction perpendicular to main surfaces of the first and second bus bars; a first external terminal electrically connecting the first bus bar to the first external element; a second external terminal electrically connecting the second bus bar to the second external element; a first region in the first external terminal electrically coupled to the first external element; and a second region in the second external terminal electrically coupled to the second external element, and at least partially overlapped with the first region in the direction.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-252507, filed on Dec. 24, 2015, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    A certain aspect of the present invention relates to an electric circuit device. 
       BACKGROUND 
       [0003]    There has been known a structure in which a terminal of an electronic component is coupled to a bus bar. Japanese Patent Application Publication Nos. 2005-237118, 2014-11338, and 11-4584 disclose an art that makes the direction of the electrical current flowing through a terminal such as a positive bus bar coupled to a switching element be opposite to the direction of the electrical current flowing through a terminal such as a negative bus bar. 
       SUMMARY OF THE INVENTION 
       [0004]    When the direction of the electrical current flowing through the positive bus bar is made to be opposite to the direction of the electrical current flowing through the negative bus bar, inductance such as parasitic inductance can be reduced. However, the inductance is not sufficiently reduced. 
         [0005]    According to an aspect of the present invention, there is provided an electric circuit device including: a first electronic component, a first bus bar electrically connected to the first electronic component, a second bus bar electrically connected to the electronic component and overlapped with the first bus bar in a direction perpendicular to main surfaces of the first and second bus bars, a first external terminal electrically connecting the first bus bar to the first external element, a second external terminal electrically connecting the second bus bar to the second external element, a first region in the first external terminal electrically coupled to the first external element, and a second region in the second external terminal electrically coupled to the second external element. The second region is at least partially overlapped with the first region in the direction. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1A  is a plan view of an electric circuit device in accordance with a first embodiment, and  FIG. 1B  is a cross-sectional view taken along line A-A in  FIG. 1A ; 
           [0007]      FIG. 2A  is a plan view of an electric circuit device in accordance with a first comparative example, and  FIG. 2B  is a plan view of the electric circuit device of the first embodiment; 
           [0008]      FIG. 3  is a circuit diagram of an electric circuit device in accordance with a second embodiment; 
           [0009]      FIG. 4A  is a plan view of the electric circuit device of the second embodiment, and  FIG. 4B  is a cross-sectional view taken along line A-A in  FIG. 4A ; 
           [0010]      FIG. 5  is a plan view of a capacitor mounted to a bus bar in the second embodiment; 
           [0011]      FIG. 6A  through  FIG. 6C  are cross-sectional views taken along lines A-A, B-B, and C-C in  FIG. 5 , respectively; 
           [0012]      FIG. 7  is a cross-sectional view illustrating an exemplary case where an external terminal is coupled to an external conductor in the second embodiment; 
           [0013]      FIG. 8  is a graph of inductance versus distance between external terminals; and 
           [0014]      FIG. 9  is a circuit diagram of an electric circuit device in accordance with a third embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Hereinafter, embodiments of the present invention will be described. 
       First Embodiment 
       [0016]      FIG. 1A  is a plan view of an electric circuit device in accordance with a first embodiment, and  FIG. 1B  is a cross-sectional view taken along line A-A in  FIG. 1A .  FIG. 1B  illustrates external conductors in addition to the electric circuit device. As illustrated in  FIG. 1A  and  FIG. 1B , in an electric circuit device  100 , bus bars  12   a  and  12   b  are stacked so that the bus bars  12   a  and  12   b  sandwich an insulating layer  14  and overlap with each other in a plan view. A hole  16   a  is formed in the bus bar  12   a  and the insulating layer  14 . An electronic component  20  is located above the bus bars  12   a  and  12   b . The electronic component  20  includes a connection terminal  22   a  and a connection terminal  22   b . The connection terminal  22   a  is coupled to the bus bar  12   a . The connection terminal  22   b  is coupled to the bus bar  12   b  through the hole  16   a . This configuration electrically connects the electronic component  20  to the bus bars  12   a  and  12   b.    
         [0017]    External terminals  18   a  and  18   b  electrically connect the bus bars  12   a  and  12   b  to external elements, respectively. The external terminals  18   a  and  18   b  are protrusion portions protruding from the bus bars  12   a  and  12   b , respectively. The insulating layer  14  is located between the external terminals  18   a  and  18   b . The external terminals  18   a  and  18   b  overlap with each other in a plan view. The external terminals  18   a  and  18   b  are electrically connected to external elements through external conductors  42   a  and  42   b , respectively. The external conductors  42   a  and  42   b  are respectively in contact with the external terminals  18   a  and  18   b  in regions  40   a  and  40   b  indicated by cross-hatching in  FIG. 1A . This configuration electrically connects the external conductors  42   a  and  42   b  to the external terminals  18   a  and  18   b  respectively. 
         [0018]    The bus bars  12   a  and  12   b  and the external terminals  18   a  and  18   b  are made of metal plates such as, for example, copper plates. The bus bar  12   a  and the external terminal  18   a  may be made of a metal plate integrally formed. The bus bar  12   b  and the external terminal  18   b  may be made of a metal plate integrally formed. The insulating layer  14  is, for example, an insulating resin layer. The electronic component  20  is, for example, a capacitor or a switching element. A plurality of the electronic components  20  may be mounted to the bus bars  12   a  and  12   b . The connection terminals  22   a  and  22   b  are metal terminals formed of, for example, copper. The numbers of the connection terminals  22   a  and  22   b  may be one or more than one. The external conductors  42   a  and  42   b  are formed of metal members such as, for example, copper plates. The external conductors  42   a  and  42   b  may be included in the electric circuit device  100 , or may not be included in the electric circuit device  100 . 
         [0019]      FIG. 2A  is a plan view of an electric circuit device in accordance with a first comparative example, and  FIG. 2B  is a plan view of the electric circuit device of the first embodiment. In  FIG. 2A  and  FIG. 2B , a path  50  schematically indicates a current path in the bus bar  12   a  and the external terminal  18   a , and a path  52  schematically indicates a current path in the bus bar  12   b  and the external terminal  18   b . As illustrated in  FIG. 2A , the external terminals  18   a  and  18   b  do not overlap with each other in a plan view. When a positive voltage is applied to the external terminal  18   a  and a negative voltage is applied to the external terminal  18   b , an electrical current is supplied from the external terminal  18   a  to the electronic component  20  through the bus bar  12   a . The electrical current from the electronic component  20  reaches the external terminal  18   b  through the bus bar  12   b . In a region  60  at the electronic component  20  side in the bus bars  12   a  and  12   b , the paths  50  and  52  overlap with each other and head in opposite directions. Accordingly, the parasitic inductance is reduced. 
         [0020]    However, in a region  62  at the external terminals  18   a  and  18   b  sides in the bus bars  12   a  and  12   b , the paths  50  and  52  do not overlap with each other nor head in opposite directions. Accordingly, in the region  62 , the parasitic inductance cannot be reduced. 
         [0021]    As illustrated in  FIG. 2B , the external terminals  18   a  and  18   b  overlap with each other in a plan view. The paths  50  and  52  in the bus bars  12   a  and  12   b  mostly overlap with each other and head in approximately opposite directions. Furthermore, also in the external terminals  18   a  and  18   b , the paths  50  and  52  mostly overlap with each other and head in approximately opposite directions. Accordingly, the first embodiment can reduce the parasitic inductance formed between the external terminals  18   a  and  18   b  compared to the first comparative example. 
         [0022]    In the first embodiment, as illustrated in  FIG. 1A  and  FIG. 1B , the external terminal  18   a  (a first external terminal) electrically connects the bus bar  12   a  (a first bus bar) to an external element. The external terminal  18   b  (a second external terminal) electrically connects the bus bar  12   b  (a second bus bar) to an external element. The region  40   a  (a first region) that is in the external terminal  18   a  and coupled to an external element and the region  40   b  (a second region) that is in the external terminal  18   b  and coupled to an external element at least partially overlap with each other in a plan view. This configuration can reduce the inductance formed between the external terminals  18   a  and  18   b  as illustrated in  FIG. 2B . 
         [0023]    The region  40   a  is a region that comes into contact with, for example, the external conductor  42   a  (a first external conductor), and the region  40   b  is a region that comes into contact with, for example, the external conductor  42   b  (a second external conductor). 
         [0024]    The electronic component  20  electrically connected to the bus bar  12   a  and the electronic component  20  electrically connected to the bus bar  12   b  may be the same electronic component or different electronic components. 
         [0025]    In  FIG. 1B , the insulating layer  14  is located between the external terminals  18   a  and  18   b , and the insulating layer  14  is located between the bus bars  12   a  and  12   b . This configuration can electrically separate the external terminal  18   a  from the external terminal  18   b , and can electrically separate the bus bar  12   a  from the bus bar  12   b.    
       Second Embodiment 
       [0026]    A second embodiment is an exemplary electric circuit device used as a smoothing capacitor connected between power sources.  FIG. 3  is a circuit diagram of an electric circuit device in accordance with the second embodiment. As illustrated in  FIG. 3 , a plurality of capacitors  20   a  are connected in parallel between the external terminals  18   a  and  18   b . First connection terminals  22   a  of the capacitors  20   a  are coupled to the bus bar  12   a . Second connection terminals  22   b  of the capacitors  20   a  are coupled to the bus bar  12   b . The bus bars  12   a  and  12   b  are respectively coupled to the external terminals  18   a  and  18   b . A direct voltage is applied between the external terminals  18   a  and  18   b , for example. The external terminals  18   a  and  18   b  are, for example, positive and negative terminals, respectively. 
         [0027]      FIG. 4A  is a plan view of the electric circuit device in accordance with the second embodiment, and  FIG. 4B  is a cross-sectional view taken along line A-A in  FIG. 4A .  FIG. 4A  omits the illustration of a chassis at the upper side. As illustrated in  FIG. 4A  and  FIG. 4B , an electric circuit device  104  includes plate-like bus bars  12   a  and  12   b . The bus bar  12   a  is located on the upper surface of the insulating layer  14 , and the bus bar  12   b  is located on the lower surface of the insulating layer  14 . The capacitors  20   a  are located on the upper surface of the bus bar  12   a  and the lower surface of the bus bar  12   b  through adhesive agents  26 . Holes  16   a  penetrating through the bus bar  12   a  and the insulating layer  14  and holes  16   b  penetrating through the bus bar  12   b  and the insulating layer  14  are formed. The connection terminal  22   a  electrically connects the capacitor  20   a  and the bus bar  12   a , and the connection terminal  22   b  electrically connects the capacitor  20   a  and the bus bar  12   b . At the upper side of a substrate  10 , the connection terminal  22   b  is coupled to the bus bar  12   b  through the hole  16   a . At the lower side of the substrate  10 , the connection terminal  22   a  is coupled to the bus bar  12   a  through the hole  16   b.    
         [0028]    A hole portion  19   a  is formed in the external terminal  18   a , a hole portion  19   b  is formed in the external terminal  18   b , and a hole portion  19   c  is formed in the insulating layer  14 . The hole portions  19   a  through  19   c  are formed so that they at least partially overlap with each other. A box-shaped chassis  30  is located so as to surround the bus bars  12   a  and  12   b  and the capacitors  20   a . The external terminals  18   a  and  18   b  are located on a surface of the chassis  30 . The external terminals  18   a  and  18   b  are electrically connected to the bus bars  12   a  and  12   b , respectively. 
         [0029]      FIG. 5  is a plan view of the capacitor  20   a  mounted to the bus bar  12   a  in the second embodiment.  FIG. 6A  through  FIG. 6C  are cross-sectional views taken along lines A-A, B-B, and C-C in  FIG. 5 , respectively. As illustrated in  FIG. 5  through  FIG. 6C , six connection terminals  22   a  are coupled to an external electrode  25   a  formed on a first surface of the capacitor  20   a , and six connection terminals  22   b  are coupled to an external electrode  25   b  formed on a second surface of the capacitor  20   a . Each of the external electrodes  25   a  and  25   b  is formed across approximately the entirety of the side surface of the capacitor  20   a . The external electrodes  25   a  and  25   b  are made of a metal film such as a copper film or a nickel film. The connection terminal  22   a  of the upper-side capacitor  20   a  is coupled to the bus bar  12   a  with the use of solder. The connection terminals  22   b  of the upper-side capacitor  20   a  are coupled to the bus bar  12   b  through the hole  16   a  with the use of solder in units of three. The connection terminals  22   a  of the lower-side capacitor  20   a  are coupled to the bus bar  12   a  through the hole  16   b  with the use of solder in units of three. The connection terminals  22   b  of the lower-side capacitor  20   a  are coupled to the bus bar  12   b  with the use of solder. The capacitor  20   a  is a stacked ceramic capacitor. The stacked ceramic capacitor is a capacitor in which dielectric ceramic sheets sandwiched between internal electrodes are stacked. The internal electrodes are electrically connected to the external electrodes  25   a  and  25   b . The connection terminals  22   a  may be interconnected by connection wiring lines. The connection terminals  22   b  may be interconnected by connection wiring lines. 
         [0030]    As illustrated in  FIG. 3  through  FIG. 6C , the external terminal  18   a  is electrically connected to the connection terminals  22   a  of the capacitors  20   a  through the bus bar  12   a . The external terminal  18   b  is electrically connected to the connection terminals  22   b  of the capacitors  20   a  through the bus bar  12   b . Thus, the capacitors  20   a  are connected in parallel between the external terminals  18   a  and  18   b . The bus bar  12   a  mutually connects the connection terminals  22   a , and the bus bar  12   b  mutually connects the connection terminals  22   b . The bus bars  12   a  and  12   b  reduce the parasitic inductances formed between the external terminals  18   a  and  18   b  and the capacitors  20   a . Furthermore, one capacitor  20   a  includes the connection terminals  22   a  and the connection terminals  22   b . This configuration distributes the electrical currents flowing through the bus bars  12   a  and  12   b , and reduces the parasitic inductance. Two or more holes  16   a  or two or more holes  16   b  are provided with respect to one capacitor  20   a . This configuration secures the paths of the electrical currents flowing through the bus bars  12   a  and  12   b . One hole  16   a  or one hole  16   b  may be provided with respect to one capacitor  20   a , and the number of the connection terminals  22   a  or  22   b  may be increased. This configuration reduces the parasitic inductance between the bus bar  12   a  or  12   b  and the capacitor  20   a.    
         [0031]      FIG. 7  is a cross-sectional view illustrating an exemplary case where the external terminal is in contact with an external conductor in the second embodiment. The external terminal  18   a , the insulating layer  14 , and the external terminal  18   b  are stacked so that the hole portions  19   a ,  19   c , and  19   b  overlap with each other. Hole portions  43   a  and  43   b  are respectively formed in the external conductors  42   a  and  42   b . The external conductor  42   a  is in contact with the upper surface of the external terminal  18   a , thereby being electrically connected to the external terminal  18   a . The external conductor  42   b  is in contact with the lower surface of the external terminal  18   b , thereby being electrically connected to the external terminal  18   b . The hole portion  43   a  at least partially overlaps with the hole portion  19   a , and the hole portion  43   b  at least partially overlaps with the hole portion  19   b . A washer  44   a  is located on the external conductor  42   a , and a washer  44   b  is located under the external conductor  42   b . A bolt  48  in which spiral screw threads are formed penetrates through the hole portions  43   a ,  19   a ,  19   b ,  19   c , and  43   b . A nut  49  is screw-engaged with the tip of the bolt  48 . Tightening the bolt  48  and the nut  49  makes the external terminal  18   a  and the external conductor  42   a  be attached firmly to each other and makes the external terminal  18   b  and the external conductor  42   b  be attached firmly to each other. Thus, the contact resistance between the external terminal  18   a  and the external conductor  42   a  and the contact resistance between the external terminal  18   b  and the external conductor  42   b  are reduced. 
         [0032]    The external conductors  42   a  and  42   b  are respectively coupled to terminals  47   a  and  47   b  through connection conductors  46   a  and  46   b . The connection conductors  46   a  and  46   b  are covered with insulating coating films  45 . The connection conductors  46   a  and  46   b  are, for example, cables. The region  40   a  in which the external terminal  18   a  is in contact with the external conductor  42   a  and the region  40   b  in which the external terminal  18   b  is in contact with the external conductor  42   b  overlap with each other in a plan view. Thus, as in  FIG. 2B  of the first embodiment, the parasitic inductance between the external terminals  18   a  and  18   b  is reduced. 
         [0033]    The electric circuit device of the second embodiment is used for, for example, the primary smoothing capacitor of an inverter used for a driving motor of an electric vehicle. The exemplary specification of the electric circuit device is as follows. The operation voltage is 200 V, the rated voltage is 400 V, the electrostatic capacitance is 240 μF, the maximum ripple current is 300 A, and the short-circuit fault current is 1200 A. The operation voltage may be, for example, 48 V or greater and 720 V or less. The electrostatic capacitance may be, for example, 47 μF or greater and 630 μF or less. As described above, the electric circuit device of the second embodiment can be used for the primary smoothing capacitor of a source circuit such as an inverter or a converter. 
         [0034]    The insulating layer  14  may be made of an insulating resin with high thermal resistance such as, for example, an epoxy resin or a polyimide resin. The bus bars  12   a  and  12   b  may be made of a metal plate such as, for example, a copper plate. The bus bars  12   a  and  12   b  and the external terminals  18   a  and  18   b  may have film thicknesses of, for example, approximately 0.25 mm or greater. This configuration can reduce the resistances and the inductances of the bus bars  12   a  and  12   b  and the external terminals  18   a  and  18   b . The bus bar  12   a  and the external terminal  18   a  may be integrally formed into a plate-shape. The bus bar  12   b  and the external terminal  18   b  may be integrally formed into a plate-shape. The connection terminals  22   a  and  22   b  may be made of a metal plate such as, for example, a copper plate. Each of the connection terminals  22   a  and  22   b  may have a resistance of, for example, approximately 1 mΩ. The chassis  30  may be made of an insulating material such as a frame-retardant resin, ceramics, or a metal coated with an insulating substance. An insulating layer with high thermal resistance such as a silicon resin may be located between the chassis  30  and the bus bars  12   a  and  12   b  and between the chassis  30  and the external terminals  18   a  and  18   b.    
         [0035]    The dielectric strength in the air is approximately 3 kV/mm. This corresponds to 0.21 mm when 630 V is applied between the external terminals  18   a  and  18   b . Temperature, humidity, and atmospheric pressure change the dielectric strength in the air. Considering the margin for the change in dielectric strength, the distance between the external terminals  18   a  and  18   b  is preferably made to be 0.5 mm or greater when the air is located between the external terminals  18   a  and  18   b . When the insulating layer  14  is located between the external terminals  18   a  and  18   b  and the insulating layer  14  is made of an epoxy resin with high insulation (e.g., FR-4) or a polyimide resin, the distance between the external terminals  18   a  and  18   b  can be made to be approximately 0.1 mm. The end surface of the insulating layer  14  is located further out than the end surfaces of the external terminals  18   a  and  18   b  by approximately 0.5 mm or greater. This configuration further inhibits breakdown at the end surfaces of the external terminals  18   a  and  18   b . The insulating layer  14  located between the bus bars  12   a  and  12   b  may be made of the same material and have the same film thickness as the insulating layer  14  located between the external terminals  18   a  and  18   b.    
         [0036]    The bolt  48  and the nut  49  preferably have electrical insulation. The bolt  48  and the nut  49  are preferably made of, for example, a polytetrafluoroethylene resin, a polychlorotrifluoroethylene resin, a polyvinylidene fluoride resin, aluminum oxide, silicon nitride, polycarbonate, a polyether ether ketone resin, a wholly aromatic polyimide resin, rigid polyvinyl chloride, a polyphenylene sulfide resin, RENY (glass fiber 50% reinforced polyamide MXD6), a polyacetal resin, or a glass epoxy resin. 
         [0037]    The inductance between the external terminals  18   a  and  18   b  was simulated by changing the distance between the external terminals  18   a  and  18   b  in a plan view.  FIG. 8  is a graph of inductance versus the distance between the external terminals. In  FIG. 8 , the case where the distance is zero corresponds to the second embodiment, and the hole portions  19   a  and  19   b  overlap with each other in this case. The external terminals  18   a  and  18   b  have dimensions of approximately 15 mm×15 mm in a plan view, and the distance when the external terminals  18   a  and  18   b  are the furthest away from each other (the arrangement illustrated in  FIG. 2A ) is 45 mm. Six capacitors  20   a  were provided, and the equivalent parallel capacity of each capacitor  20   a  was 13 nH. As illustrated in  FIG. 8 , as the distance between the external terminals  18   a  and  18   b  increases, the inductance increases. Even when the external terminals  18   a  and  18   b  do not completely overlap with each other, the inductance decreases as long as the external terminals  18   a  and  18   b  at least partially overlap with each other. 
         [0038]    In the second embodiment, the hole portion  19   a  (a first hole portion) is located in the external terminal  18   a , and the hole portion  19   b  (a second hole portion) is located in the external terminal  18   b . The hole portions  19   a  and  19   b  at least partially overlap with each other. This configuration allows the bolt  48  to be in the same axis as the hole portions  19   a  and  19   b , for example. The region  40   a  in which the external terminal  18   a  is in contact with the external conductor  42   a  and the region  40   b  in which the external terminal  18   b  is in contact with the external conductor  42   b  can be located so as to overlap with each other in a plan view. Thus, the parasitic inductance can be further reduced. The external terminals  18   a  and  18   b  may be located in other than the middle of sides of the bus bars  12   a  and  12   b , respectively. 
         [0039]    When the bolt  48  and the nut  49  (contact members) are screw-engaged with each other, the external conductor  42   a  is made to come into contact with a region in the external terminal  18   a , and the external conductor  42   b  is made to come into contact with a region in the external terminal  18   b . Thus, the contact resistances between the external terminal  18   a  and the external conductor  42   a  and between the external terminal  18   b  and the external conductor  42   b  can be reduced, and the parasitic inductance can be also reduced. The contact members may be a member other than the bolt  48  and the nut  49 . 
         [0040]    The insulating layer  14  is located between the external terminal  18   a  and the external terminal  18   b . This configuration can electrically insulate the external terminal  18   a  from the external terminal  18   b , and reduce the distance between the external terminal  18   a  and the external terminal  18   b . The insulating layer  14  may be located between the bus bars  12   a  and  12   b.    
         [0041]    The bus bar  12   a  mutually electrically connects the connection terminals  22   a  (first terminals) of the capacitors  20   a . The bus bar  12   b  mutually electrically connects the connection terminals  22   b  (second terminals) of the capacitors  20   a . As described above, when two or more electronic components are located, the inductances in the bus bars  12   a  and  12   b  increase. Thus, the external terminals  18   a  and  18   b  are preferably located so as to overlap with each other. 
         [0042]    When the capacitor  20   a  is located so as to overlap with the bus bars  12   a  and  12   b , the inductances between the capacitor  20   a  and the bus bars  12   a  and  12   b  can be reduced. Thus, the effect of the inductance due to the electrical currents flowing through the external terminals  18   a  and  18   b  and the bus bars  12   a  and  12   b  increases. Therefore, the external terminals  18   a  and  18   b  are preferably located so as to overlap with each other. 
         [0043]    As illustrated in  FIG. 6A  through  FIG. 6C , the upper-side capacitor  20   a  (a first electronic component located on the opposite side of the bus bar  12   a  from the bus bar  12   b ) and the lower-side capacitor  20   a  (a second electronic component located on the opposite side of the bus bar  12   b  from the bus bar  12   a ) are provided. The positions at which the connection terminals  22   a  of the upper-side and lower-side capacitors  20   a  are coupled to the bus bar  12   a  overlap with each other in a plan view. The positions at which the connection terminals  22   b  of the upper-side and lower-side capacitors  20   a  are coupled to the bus bar  12   b  overlap with each other in a plan view. When the connection terminals  22   a  and  22   b  are coupled to the bus bars  12   a  and  12   b , the stress between the bus bar  12   a  and the bus bar  12   b  becomes unbalanced. The positions at which the lower and upper connection terminals  22   a  (or  22   b ) are coupled to the bus bar  12   a  (or  12   b ) are made to overlap with each other. This configuration inhibits the strain caused by stress due to the connection terminals  22   a  and  22   b  from being produced in the bus bars  12   a  and  12   b . In addition, even when the temperatures of the bus bars  12   a  and  12   b  increase, the strain caused by thermal stress due to the connection terminals  22   a  and  22   b  is less likely to be produced in the bus bars  12   a  and  12   b.    
       Third Embodiment 
       [0044]    A third embodiment is an exemplary inverter.  FIG. 9  is a circuit diagram of an electric circuit device in accordance with the third embodiment. As illustrated in  FIG. 9 , paths  56   a  through  56   c  are located in parallel between the external terminals  18   a  and  18   b . In each of the paths  56   a  through  56   c , two switching elements  21  are connected in series. Terminals  58   a  through  58   c  are respectively coupled to nodes between the switching elements  21  in the paths  56   a  through  56   c . First ends of the paths  56  are commonly coupled to the bus bar  12   a , and second ends of the paths  56  are commonly coupled to the bus bar  12   b . The bus bars  12   a  and  12   b  are respectively coupled to the external terminals  18   a  and  18   b . The external terminals  18   a  and  18   b  are primary terminals, and the terminals  58   a  through  58   c  are secondary terminals. 
         [0045]    The switching element  21  is, for example, an Insulated Gate Bipolar Transistor (IGBT), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a SiCFET, or a GaNFET. Alternatively, the switching element  21  may be a diode or a thyristor. 
         [0046]    Direct-current power is supplied to the external terminals  18   a  and  18   b . When the switching elements  21  are properly controlled, the terminals  58   a  through  58   c  output three-phase alternating-current power. As described above, the third embodiment functions as an inverter. 
         [0047]    A high-powered motor such as an electric vehicle or an air compressor uses large current, and thus is required to have high heat release performance and low resistance. Thus, a large bus bar is employed. In a source circuit using a switching element, an electrical current can be instantly shut down or allowed to flow by appropriately controlling the switching element. When the switching element shuts down the electrical current, the parasitic inductances of the bus bars  12   a  and  12   b  and the external terminals  18   a  and  18   b  generate spike surge voltage in the switching element. 
         [0048]    The surge voltage exceeding the withstand voltage of the switching element causes the failure of the switching element. Thus, it is important for the electric circuit device used in a source circuit using a switching element to reduce the parasitic inductance. Thus, in the electric circuit device of the third embodiment, the external terminals  18   a  and  18   b  are located so as to overlap with each other as in the first and second embodiments. This configuration can reduce the parasitic inductance. 
         [0049]    An AC-DC converter or a DC-DC converter may be used as the source circuit using a switching element instead of the inverter. 
         [0050]    As described above, the electronic component may be a capacitor as in the second embodiment, or may be a switching element as in the third embodiment. The electronic component may be other electronic components. As in the second embodiment, the connection terminals  22   a  and  22   b  of a single electronic component may be coupled to the bus bar  12   a  and the bus bar  12   b . As in the third embodiment, different electronic components may be coupled to the bus bar  12   a  and the bus bar  12   b.    
         [0051]    Although the embodiments of the present invention have been described in detail, it is to be understood that the various change, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.