Abstract:
A portable frequency synthesizer is provided with fine tuning over a broad bandwidth using a Fractional N type Delta Sum Phase Locked Loop circuit that enables elimination of boundary value spurs. In the system, frequencies where spurs occur are calculated to define a region of fractional N values that cannot be used with a first time base. To avoid the boundary spurs, a second time base reference is selected that can generate boundary spurs that do not overlap with the first time base. Circuitry is provided to select the appropriate time base and the fractional N values to generate desired output frequencies throughout the synthesizer range while avoiding the boundary spurs.

Description:
BACKGROUND 
     1. Technical Field 
     The present invention relates to a fine resolution signal synthesizer that operates over a continuous frequency bandwidth using a Fractional N Delta Sum Phase Locked Loop. 
     2. Related Art 
     Traditional fine resolution synthesizers are made using one of three different techniques. The first is a Direct Synthesis technique that includes a phase locked loop that provides frequency adjustment using one of a sum, difference, multiply or a divide component. The second is a Direct Digital Synthesis (DDS) technique that creates and varies the output frequency using digital techniques. The third is a Delta Sigma approach, also know as a Fractional N Delta Sum Phase Locked Loop. 
     The size and power requirements for synthesizers using the first and second techniques, Direct Synthesis and DDS respectively, make those devices undesirable for use as a portable component for field testing over a desired test frequency range. The third technique, the Fractional N approach, is more ideal for creation of a portable device due to its limited size and power requirements for the same frequency range. A major drawback of this Fractional N approach, however, is a phenomenon called boundary spurs. Boundary spurs are spurious discrete frequencies that occur at particular frequency division values relative to the set time base provided in the phase locked loop. The boundary value spurs typically occur at fractional frequency values of the selected frequency division time base that approach N/4, N/2, 3N/4 and N. 
     SUMMARY 
     Embodiments of the present invention enable elimination of boundary value spurs for a Fractional N type frequency synthesizer. Elimination of the boundary spurs enables the Fractional N type synthesizer to be more readily used as a portable synthesizer over a wide frequency range. 
     Embodiments of the invention are based on the fact that boundary spurs can be pushed out in frequency far enough to enable them to be rejected by the closed loop zero crossing loop bandwidth. The pushed out spurs still, however, imply that a range of fractional values cannot be used, reducing the usefulness of the synthesizer system. To avoid the pushed out boundary spurs, however, two separate time bases are used to create two different locations where the pushed out boundary spurs can occur. 
     To create the two time base system, embodiments of the invention first calculate if the division ratio will create a boundary spur within a user defined range in the phase locked loop bandwidth. If so, it then uses a second reference frequency or time base that requires a new division ratio. The new division ratio will give the desired output frequency while moving its boundary spurs out of the loop bandwidth of the first reference. The value of the second reference frequency is selected that will give a spurious free alternate division ratio for frequency division ratios causing spurs with the first reference. 
     In one embodiment, a calculation is made at every output frequency of the synthesizer to determine if a spur occurs. For instance, for a selected synthesizer output frequency, a calculation is made to determine if the fractional frequency division value used with a first time base reference will create a spur. If a spur is determined to occur, then the calculation is redone to determine new whole and fractional frequency division values for a second time base where the spur will not occur. 
     For circuitry to accomplish embodiments of the present invention, in a first embodiment two separate time base references are provided within a single phase locked loop. A switch separately connects the different time bases to the phase locked loop in the signal synthesizer. Either calculations or a lookup table are used to determine when boundary spurs occur using the first time base. The second time base is selected to prevent any overlap of boundary spurs. The switch and frequency selections are then controlled to connect to the second time base where boundary spurs occur using the first time base to effectively eliminate the spurs. 
     In another circuit embodiment two separate phase locked loops are provided, each with its own timebase. A switch then selects the output of the desired phase locked loop to avoid boundary spurs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Further details of the present invention are explained with the help of the attached drawings in which: 
         FIG. 1  shows a block diagram of components of a Fractional N Delta Sum Phase Locked Loop according to one embodiment of the present invention that allows selection between two time bases connected to a single phase locked loop; 
         FIGS. 2A and 2B  illustrate boundary spurs resulting from selection of two different frequency time base references; 
         FIG. 3  illustrates frequency values that enable calculation of time base reference frequencies for pushing spurs out of range; 
         FIG. 4  is a flowchart illustrating a sequence of steps of a calculation to determine if a spur occurs, and if so calculating frequency division values to use with a second time base to avoid spurs; and 
         FIG. 5  shows a block diagram of components of a synthesizer system according to another embodiment of the present invention that allows selection between two phase locked loops, each having a different time base. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a block diagram of components of a Fractional N Delta Sum Phase Locked Loop with components according to one embodiment of the present invention that allows selection between two separate time bases  16  and  18 . By providing a switch  20  to selectively connect one of the time bases  16  and  18 , and by appropriately choosing the operating frequency of the time bases  16  and  18  boundary spurs can be avoided. 
     The phase locked loop of  FIG. 1  is formed from a variable frequency signal source  2 , phase detector  4 , time base reference  6 , frequency divider  8 , and integrator  10 . In operation, the phase locked loop phase detector  4  receives inputs from the time base frequency reference  6  and the signal source  2  through frequency divider  8 . The output of the phase detector  4  through integrator  10  provides a voltage control signal to the signal source  2  to assure it is phase aligned with the time base reference  6 . 
     For a fractional N type phase locked loop, the frequency divider  8  is made up of an N times frequency divider  12  as well as a fractional N divider  14  for fine tuning. The frequency divider  12  provides for a division by a whole number (NW) representing Nwhole, and can be found in a typical phase locked loop that does not offer fine tuning. The second frequency divider  14  allows fine resolution tuning by adjusting both the numerator NF and denominator DF to provide NF/DF, or a fractional division represented as Nfrac=NF/DF. An example device that provides both the first Nwhole frequency divider  12  and the Nfrac frequency divider  14  is the Skyworks SKY72300 series fractional-N synthesizer. However, when using the fractional N type synthesizers boundary spurs can occur at values that are ¼ the time base reference frequency, namely where NF/DF=¼, ½, ¾, 1. The integrator  10  or other filter placed in the path of integrator  10  can attenuate the spurs, but do little to attenuate them within the loop bandwidth. Thus, typical designers do not use the fractional N type phase locked loops when a continuous tuning bandwidth is required. For instance, an Fo bandwidth of 1.5 to 3 GHz will likely allow use of the fractional N type device with boundary spurs in the range of −40 dBc. However, for a higher range from 13-40 GHz, the spurs will be increased in amplitude due to frequency multiplication to a level of 20×Log 40 GHz/3 GHz or +22.5 dB. The boundary spurs on the 40 GHz signal will now be in the −17.5 dBc range. This is unacceptable without use of embodiments of the present invention, so a lab grade instrument has previously not been available using the fractional N type device. 
     To enable recovering the unusable areas of the phase locked loop where spurs occur, two different time base oscillators are used in embodiments of the present invention. A selection is made between the two time base oscillators to avoid spurs. This creates a frequency synthesizer with a continuous frequency spectrum without boundary spurs that can be used up into the 40 GHz frequency range. 
     In a first embodiment of the present invention shown in  FIG. 1 , the time base reference  6  is constructed using two time base oscillators  16  and  18 . Switch  20  selectively connects one of the time bases  16  and  18  to the phase detector  4  of the phase locked loop. The time base frequencies are selected to avoid the frequency spurs as discussed with respect to  FIGS. 2A-2B  and  FIG. 3 . 
     As shown in  FIGS. 2A and 2B , the frequency FREF 1  of the first time based oscillator  16  is selected to occur so that spurs  30  occur at different locations than the spurs  35  of oscillator  18  operating at FREF 2 . By using different FREF 1  and FREF 2  values and corresponding frequency division values (NW and NF/DF), the output frequency (Fo) boundary spurs  30  shown in  FIG. 2A  in hashed lines can be pushed over in frequency far enough to avoid spurs  35  in  FIG. 2B  to let the phase locked loop (entire circuit of  FIG. 1 ) reject them. In one embodiment, the time base  16  is selected by switch  20 , while the switch  20  is transitioned to connect time base  18  at frequencies where spurs  30  occur. 
     A controller  22  is programmed to control the switch  20 , as well as the frequency division values NW and NF/DF in frequency dividers  12  and  14  to provide a range of frequencies Fo without encountering spurs. The controller can also vary the frequency F OSC  of oscillator  2 , which in exemplary circuitry can be set from 1.5-3 GHz. The controller can be a microprocessor, digital signal processor, or other control device that can store control software and provide signals to control external devices of the phase locked loop. Programming of the controller can be done to avoid frequency spurs while providing a desired frequency spectrum for the synthesizer output Fo. 
       FIG. 3  illustrates how frequency values can be calculated to enable selection of time base reference frequencies, and other values for the circuit of  FIG. 1  to push spurs out of range. First of all, the spurs are identified by hatched lines along an amplitude vs. frequency plot. The unacceptable operational range ΔF F  is the frequency range within the loop bandwidth where spurs will appear. The acceptable operation range is ΔF A . Spurs appearing in this range will be rejected by the loop bandwidth. The spurs are periodic, and the spur repeat frequency is ΔF SP . The time base reference frequency F REF  is shown. Also as indicated, the frequency F REF  is one integer value of Nwhole, with fractional values Nfrac differentiating frequency values within F REF . Thus, the first F REF  range is shown as Nwhole=N, the second is shown as Nwhole=N+1, and so forth. 
     Relations exist to identify desirable frequencies to enable selecting F REF1  and F REF2 . First, the spur repeat frequency will be a multiple of ¼ of the reference frequency, ΔF sp =F REF /4, as spurs occur periodically at ¼ intervals. The value F REF  can be either the frequency F REF1  of the time base  16 , or F REF2  of the time base  18 . With switch  20  maintaining a base connection to time base  16  unless a spur is encountered, a first focus is on F REF1 . Since the acceptable frequency range ΔF A =ΔF SP −ΔF F , then ΔF A =F REF1 /4−ΔF F . The maximum value for N (N MAX ) used in divider  12  will be related to the maximum frequency of the oscillator  2 , Fosc MAX , as follows: N MAX =Fosc MAX /F REF1 . The value N MAX  can then be used to determine F REF2  relative to F REF1  as follows: F REF2 =F REF1 +ΔF A /N MAX . The minimum value of N MIN  used in divider  12  can then be set based on the difference between the frequencies of time base references  16  and  18  as follows: N MIN =ΔF F /(F REF2 −F REF1 ) to assure the time bases are appropriately set. 
     In one example, calculation of values is performed so that F REF1  and F REF2  do not create overlapping spurs. For this example, assume F REF1 =26 MHz, arbitrarily set ΔF F =1 MHz, and let F MAX =3 GHz. Then the following calculations can be performed:
 
Δ F   SP   =F   REF1 /4=26 MHz/4=6 MHz
 
Δ F   A   =F   sp   −ΔF   F   =F   REF /4 −ΔF   F =26/4 MHz−1 MHz=5 MHz
 
 N   MAX   =Fosc   MAX   /F   REF =115.3846 GHz
 
 F   REF2   =F   REF1   +ΔF   F   /N   MAX =26.0476 MHz
 
 N   MIN   =ΔF   F /( F   REF2   −F   REF1 )=21.
 
       FIG. 4  provides a flowchart illustrating a sequence of steps of a calculation to determine if a spur occurs with time base reference  16  that can be used with the controller  22 , and if so calculating frequency division values to use with the second time base  18  to avoid spurs. After starting in step  100 , the desired output frequency Fo is selected in step  102  and values for Nwhole and Nfrac are determined using F REF1  of time base  16 . In step  106  a determination is made if the Nfrac is in a forbidden zone that will create a spur. The determination in step  106  can be either calculated or identified in a look up table. If in step  106  Nfrac is not in a forbidden zone, the process proceeds to  110  to end with the Nwhole, Nfrac for F REF1  being used. If in step  106  Nfrac is in the forbidden zone, the process proceeds to step  108  to determine Nwhole and Nfrac values using F REF2  of time base  18  with either a calculation or look up table so that spurs do not occur. The process then proceeds from  108  to step  110  to use the values determined for F REF2 . 
     In one embodiment, a calculation is made at every desired output frequency of the synthesizer to determine if a spur occurs. For instance, for a selected synthesizer output frequency, a calculation is made to determine if fractional Nfrac frequency division value used with a first time base reference F REF1  will create a spur. If a spur is determined to occur, then the calculation is redone to determine new whole Nwhole and fractional Nfrac frequency division values for the second time base F REF2  where the spur will not occur. Instead of calculations each time, the values can likewise be read from a lookup table. 
       FIG. 5  shows a block diagram of components of a synthesizer system according to another embodiment of the present invention that allows selection between two phase locked loops, each having a different time base. The system includes two phase locked loops  200  and  202  with a switch  204  selectively providing the output Fo. The phase locked loops  200  and  202  each have components similar to those in the phase locked loop of  FIG. 1 , so the components of phase locked loop  200  that are similar are labeled with the same reference number with a version “A” afterward, and the components of phase locked loop  202  that are similar are labeled with the version “B.” For example, the oscillator  2  of  FIG. 1  is carried over as oscillator  2 A in phase locked loop  200 , and oscillator  2 B in phase locked loop  202 . 
     The difference between the phase locked loop of  FIG. 1 , and the phase locked loops  200  and  202  of  FIG. 5  is that the switch  20  and time based references  16  and  18  of  FIG. 1  are replaced by a single oscillator  216  in phase locked loop  200  and a single oscillator  218  in phase locked loop  202 . Thus, instead of selecting between two time based references in a single phase locked loop in  FIG. 1 , the circuit of  FIG. 4  selects between two separate phase locked loops, each with a different time base  216  or  218 . The controller  222  in  FIG. 5 , similar to the controller of  FIG. 1 , allows control of the output frequency Fo so that spurs don&#39;t occur. The controller  222 , thus, controls the switch  204 , frequency dividers  8 A and  8 B, and oscillators  2 A and  2 B of both phase locked loops  200  and  202 . 
     Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims.