Abstract:
A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential V PP  to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of V PP /2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about V PP /2.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation of co-pending U.S. patent application Ser. No. 10/997,688, filed Nov. 24, 2004, which is hereby incorporated by reference as if set forth herein. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to programmable integrated circuits. More specifically, the present invention relates to a circuit and method for supplying programming potentials to programmable devices at voltages larger than BVDss of programming transistors.  
         [0004]     2. Background  
         [0005]     User-programmable devices are known in the art. Such devices include, for example, field programmable gate arrays (FPGA&#39;s). To implement a particular circuit function in an FPGA, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit.  
         [0006]     Programmable elements such as antifuses are programmed by placing a programming-voltage potential across them that is sufficient to disrupt a normally high-resistance antifuse layer disposed between two antifuse electrodes to create a low-resistance connection between the two electrodes. The programming voltage potential is steered to the antifuse by programming transistors disposed on the integrated circuit.  
         [0007]     As integrated circuit devices scale, the voltages that are applied to circuits are lowered, which necessitates the lowering of voltages used to program non-volatile devices on integrated circuits. In the case of antifuses, this means an ever thinning of films such that manufacturability, as well as leakage and breakdown voltage become difficult to control or tolerate.  
         [0008]     Referring first to  FIG. 1 , an example prior-art arrangement for programming antifuses is shown in schematic diagram form. Any of antifuses  10 ,  12 ,  14 , and  16  may be programmed by turning on the appropriate ones of transistors  18 ,  20 ,  22 ,  24 ,  26 , and  28 , to appropriately supply the potentials V PP  and ground, as is known in the art. Transistor  30  is turned off to protect the output of inverter  32  when V PP  is applied to track  34  or is present on track  34  through an already programmed one of the other antifuses.  
       SUMMARY OF THE INVENTION  
       [0009]     A circuit is provided for programming an antifuse coupled between a first node and a second node. At least one transistor is provided for supplying a programming potential V PP  to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of V PP /2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating greater than about V PP /2 but less than about V PP . 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  is a simplified schematic diagram of prior-art programming circuitry illustrating the problem solved by the present invention.  
         [0011]      FIG. 2  is a simplified schematic diagram showing illustrative programming circuitry that may be used to carry out the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]     Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.  
         [0013]     In older semiconductor technologies the BVDss (Drain breakdown voltage with the gate grounded) of transistors used in integrated circuits was only slightly less than the BVJ (unction breakdown voltage). In scaling the technology BVJ has not dropped as fast as the BVDss or BVG (Gate oxide breakdown voltage). With the advent of deep sub-micron technology the BVDss (e.g., 6 volts) is substantially lower than the BVJ (e.g., 12 volts). The drain breakdown voltage is however a constant with respect to the Gate Voltage, so an N-Channel transistor with a BVDss of 6 volts can support 12 volts on its drain if the gate is at 6 volts. By utilizing this feature (along with bootstrap techniques as described in U.S. Pat. No. 6,765,427 to minimize gate oxide stress), it is possible to place two transistors in series with the appropriate biases to switch voltages equal to/or slightly less than BVJ without having to engineer special high voltage transistors. This saves mask count and wafer cost as well as making a design easily portable to different foundries.  
         [0014]     Referring now to  FIG. 2 , a simplified schematic diagram shows illustrative programming circuitry that may be used to carry out the present invention.  FIG. 2  shows a portion of a programmable integrated circuit including an output buffer  40 , and CMOS inverters  42  and  44 . CMOS inverter  42  includes a p-channel MOS transistor  46  and an n-channel MOS transistor  48  and CMOS inverter  44  includes a p-channel MOS transistor  50  and an n-channel MOS transistor  52 . The input of CMOS inverter  42  is coupled to an input wiring track  54  via an isolation transistor  56 . The input of CMOS inverter  44  is coupled to an input wiring track  58  via an isolation transistor  60 . CMOS inverter  42  includes an additional p-channel MOS transistor  62  coupled between V CC  and its output and an additional n-channel MOS transistor  64  coupled between the n-channel MOS transistor  48  and ground. Similarly, CMOS inverter  44  includes an additional p-channel MOS transistor  66  coupled between Vcc and its output and an additional n-channel MOS transistor  68  coupled between the n-channel MOS transistor  52  and ground. In addition, each of the CMOS inverters  42  and  44  includes an additional n-channel MOS transistor,  70  and  72 , respectively, coupled between its input and ground. The output of output buffer  40  is coupled to a vertically-oriented output wiring track  44  via an isolation transistor  76 .  
         [0015]     Persons of ordinary skill in the art will appreciate that output buffer  40 , and inverters  42  and  44  are merely representative of circuit inputs and outputs that might be encountered in a typical user-programmable integrated circuit such as an FPGA and that the present invention is disclosed using these elements for purposes of illustration only.  
         [0016]     A portion of an interconnect wiring architecture is also shown in  FIG. 2 . Horizontal wiring track  78  is shown intersecting vertical wiring track  80 . Antifuse  82  is coupled between horizontal wiring track  78  and vertical wiring track  80 . In addition, input wiring track  54  is shown intersecting vertical wiring track  80 . Antifuse  84  is coupled between input wiring track  54  and vertical wiring track  80 . Similarly, input wiring track  58  is also shown intersecting vertical wiring track  80 . Antifuse  86  is coupled between input wiring track  58  and vertical wiring track  50 . Output wiring track  44  is shown intersecting horizontal wiring track  78 . Antifuse  88  is coupled between output wiring track  74  and vertical wiring track  80 .  
         [0017]     According to an embodiment of the present invention, unidirectional programming may be advantageously employed. Unidirectional programming makes only one of the two programming potential levels, rather than both of them, available to each of the wiring resources. In the illustrative example of  FIG. 2 , Vpp is made available to vertical wiring track  80  and ground is made available to horizontal wiring track  78 , input wiring tracks  54  and  58 , and output wiring track  74 .  
         [0018]     As may be seen from an examination of  FIG. 2 , a bootstrap circuit including n-channel MOS transistors  90  and  92  may be used to supply either the V PP  programming potential or the potential V PP /2 to vertical wiring track  80 . Either V PP /2 or ground potential may be supplied to horizontal wiring track  78  through n-channel MOS transistors  94  and  96 , connected in series between horizontal wiring track  78  and ground. Either V PP /2 or ground potential may be supplied to output wiring track  74  through n-channel MOS transistor  98 . Finally, either V PP /2 or ground potential may be supplied to input wiring track  54  through n-channel MOS isolation transistor  56  and n-channel MOS transistor  70  and either V PP /2 or ground potential may be supplied to input wiring track  58  through n-channel MOS isolation transistor  60  and n-channel MOS transistor  72 .  
         [0019]     Programming circuitry  98  is configured to supply the potentials V PP , V PP /2 and ground. Persons of ordinary skill in the art are familiar with such programming circuitry, the details of which are omitted herein order to avoid obscuring the present invention. Steering circuitry  100  is configured to selectively supply the potentials V PP , V PP /2 and ground to the various circuit nodes in  FIG. 2  during a programming cycle depending on which antifuses are to be programmed as is known in the art. Persons of ordinary skill in the art are also familiar with such steering circuitry, the details of which are omitted herein order to avoid obscuring the present invention  
         [0020]     To illustrate the operation of the present invention, the process for programming antifuse  82 , programming antifuse  84  but not antifuse  86 , and programming antifuse  88  will be disclosed, again with reference to  FIG. 2 .  
         [0021]     In order to connect vertical wiring track  80  to horizontal wiring track  78 , antifuse  82  must be programmed. Isolation transistors  56 ,  60 , and  76  and n-channel MOS transistors  70  and  72  are turned on and the potential V PP /2 is applied to the sources of n-channel MOS transistors  70 ,  72 , and  98  in order to protect the inputs of CMOS inverters  42  and  44  and the output of buffer  40 .  
         [0022]     As may be seen from  FIG. 2 , the potential V PP  will be precharged onto vertical wiring track  80  through the bootstrap circuit made up of transistors  90  and  92  by turning these devices on then off as is known in the art. A potential of about 4 volts is applied to the drain of n-channel MOS transistor  90  and the select input coupled to its gate is turned on and then turned off. This traps the potential at the gate capacitance of n-channel MOS transistor  92 . The potential V PP  is then applied to the drain of n-channel MOS transistor  92 . This action bootstraps the gate voltage of n-channel MOS transistor  94  to V PP +4 volts, thus assuring that there will be no V T  drop across n-channel MOS transistor  92  and the entire potential V PP  will appear on vertical wiring track  80 .  
         [0023]     The source of n-channel MOS transistor  96  is coupled to ground. N-channel MOS transistors  94  and  96  are turned on. The gate of n-channel MOS transistor  94  is driven to the potential V PP/ 2 and the gate of n-channel MOS transistor  96  is driven to V PP /2. Under these conditions, the voltage at the source of n-channel MOS transistor  94  will be one V T  below V PP /2. The entire potential V PP  will be applied across antifuse  82 . The gate of n-channel MOS transistor  96  is driven to zero volts if antifuse  82  is not to be programmed. Under these conditions, the voltage at the source of n-channel MOS transistor  94  will be one V T  below V PP /2.  
         [0024]     In order to program antifuse  84  while leaving antifuse  86  unprogrammed, a potential of about 4 volts is applied to the drain of n-channel MOS transistor  90  and the select input coupled to its gate is turned on and then turned off. This traps the potential at the gate capacitance of n-channel MOS transistor  92 . The potential V PP  is then applied to the drain of n-channel MOS transistor  92 . This action bootstraps the gate voltage of n-channel MOS transistor  92  to V PP +4 volts, thus assuring that there will be no V T  drop across n-channel MOS transistor  94  and the entire potential V PP  will appear on vertical wiring track  80 . Both n-channel isolation transistors  56  and  60  will have V PP /2 applied to their gates. N-channel MOS transistor  70  will have V PP /2 applied to its gate and n-channel MOS transistor  72  will have zero volts applied to its gate. Since n-channel MOS transistors  56  and  70  are in series, as are n-channel MOS transistors  60  and  72 , the same voltage conditions that applied to series-connected n-channel MOS transistors  94  and  96  during the programming (or not) of antifuse  82  are present in this programming scenario.  
         [0025]     During programming of either antifuse  84  or antifuse  86 , zero volts is applied to the gates of both n-channel MOS transistors  64  and  68 , and to the gates of p-channel MOS transistors  62  and  66 . This turns off n-channel MOS transistors  64  and  68 , and turns on p-channel MOS transistors  62  and  66 . Under these conditions, the sources of the n-channel MOS transistors  48  and  52  in the inverters  42  and  44  are pulled up to V CC  by p-channel MOS transistors  62  and  66 , thus protecting the inverter transistors.  
         [0026]     In order to program antifuse  88 , a potential of about 4 volts is applied to the drain of n-channel MOS transistor  90  and the select input coupled to its gate is turned on and then turned off. This traps the potential at the gate capacitance of n-channel MOS transistor  92 . The potential V PP  is then applied to the drain of n-channel MOS transistor  92 . This action bootstraps the gate voltage of n-channel MOS transistor  92  to V PP +4 volts, thus assuring that there will be no V T  drop across n-channel MOS transistor  94  and the entire potential V PP  will appear on vertical wiring track  80 . This potential will appear on horizontal wiring track  78  through the already-programmed antifuse  82 . Isolation transistor  76  is turned off and n-channel MOS transistor  98  is turned on, thus placing the V PP  potential across antifuse  88 .  
         [0027]     The use of this programming circuit and technique allows n-channel MOS transistors  56 ,  60 ,  70 ,  72 ,  94 , and  96  to have BVDss ratings of less than V PP . BVDss of an n-channel transistor refers to the breakdown voltage (e.g., the classic breakdown voltage between drain and the well or body of a transistor when the gate and source of the transistor are substantially at ground).  
         [0028]     While the present disclosure has been of an illustrative embodiment used to program an antifuse on an integrated circuit, persons of ordinary skill in the art will appreciate that the techniques of the present invention are applicable to providing a high voltage to elements other than antifuses, such as non-volatile memory cells and the like disposed on the integrated circuit and to supplying such voltage potentials to devices located off of the integrated circuit.  
         [0029]     While the invention has been described with reference to an exemplary embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.