Abstract:
Embodiments of the invention use crystallographic etching of SOI wafers with a (110)-oriented epi layer to form both the vertical input facet and the re-entrant mirror. Proposed layout design combined with proposed orientation of the epi enables both vertical facets and re-entrant (upward-reflecting) mirror facets to be made in a single wafer-level wet etch process.

Description:
FIELD OF THE INVENTION 
       [0001]    Embodiments of the present invention are directed to photonic circuits and, more particularly, to combining vertical and angled facets in silicon photonic waveguides. 
       BACKGROUND INFORMATION 
       [0002]    Silicon photonic circuits generally route optical signals in planar waveguides, and it is difficult to provide a path for light to enter/exit the circuits vertically. Routing light in or out of the wafer surface can be valuable for several reasons, such as coupling into a normal-incidence photodetector on the wafer surface, for wafer-level optical test/characterization, or other potential applications. 
         [0003]    Of particular interest is the integration of planar silicon waveguides with Ge-based photodetectors. This is being addressed in several ways, all of which have various challenges. Planar photodetectors, in which the Ge is grown on top of the Si waveguide are quite large, because the optical coupling is inefficient and a long distance is needed for sufficient coupling of light to occur from the Si to the Ge. 
         [0004]    To avoid this difficulty, trench sidewall photodetectors have been proposed, where the waveguide is terminated by a vertical facet. In this case, a facet with sufficient smoothness is difficult to form, and the epitaxial growth of the Ge-based photodetector can be very challenging. 
         [0005]    Coupling light to and from planar silicon photonic devices, particularly in a low-cost, high volume manufacturing (HVM) compatible way, represents a significant challenge, and a major hurdle to commercialization. Currently, manual techniques are required to prepare facets on the edges of silicon photonics chips at the die level to couple light to and from the devices. 
         [0006]    Currently, input facets are prepared manually by dicing and polishing at the die level.  FIG. 1  shows a cross-sectional side view of a photonic waveguide including a Si handle wafer  100 , a buried oxide layer  102 , and an Si device layer  104 . A re-entrant mirror (REM)  106  may be formed in the device layer  104  as similarly described in co-pending application Ser. No. 12/567,601, herein incorporated by reference. A device, such as a photodetector  108  may be over the re-entrant mirror  106 . The coupling of light into and out of the silicon waveguide is done through facets  110  at the die edge that are prepared by dicing and mechanical polishing at die-level. This is a tedious manual process, which is not scalable to HVM. Grating couplers may also be used, but these have high loss for larger (&gt;1 um) waveguide based devices and require a high-profile package, because they are inherently non-planar. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The foregoing and a better understanding of the present invention may become apparent from the following detailed description of arrangements and example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and the invention is not limited thereto. 
           [0008]      FIG. 1  is side view of a silicon photonic waveguide device having a diced and manually prepared input facet; 
           [0009]      FIG. 2  is a top layout view of a silicon waveguide device with a bended waveguide according to one embodiment; and 
           [0010]      FIGS. 3A-3F  comprise side-by-side side and top views of a wafer illustrating the fabrication steps for creating waveguide device having a re-entrant total internal reflection (TIR) mirror device with an input facet according to one embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    Described is a new way of creating vertical facets to enable light to be coupled edgewise into planar silicon photonic devices, using an HVM-compatible wafer-level crystallographic wet etch process. In addition, embodiments of the invention also describes how such facets may be combined with re-entrant mirrors (REMs) for out-of-plane reflection, which may be useful for SiGe based optical receiver modules, among other uses. 
         [0012]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0013]      FIG. 2  shows a layout top view of the device according to one embodiment. As shown, a Si (110) wafer includes vertical planes (111). A re-entrant (111) mirror may be formed therewith. A waveguide bends approximately 54.7° into the (110) direction waveguide to bring the light from the (111) input facet such that it impinges correctly on the reentrant (111) mirror angled approximately 35.3° to the wafer plane. This is explained in greater detail below. 
         [0014]    Referring to  FIG. 3A , there is shown a top view and a side view of one embodiment of the inventive device in the first stages of fabrication. A silicon on insulator wafer comprises an epi Si device layer (110)  300 , atop a buried oxide layer (BOX)  302  on a handle wafer  304 . 
         [0015]      FIG. 3B  shows the device wafer  300  having a nitride layer  306  patterned  308  on its surface. As shown in  FIG. 3C , the Si wafer  300  may be etched down to the buried oxide (BOX)  302  to create a trench  310  using, for example a deep reactive ion etch (DRIE). In  FIG. 3D , the oxide layer  302  may be etched, such as by, for example, a wet etch in hydrofluoric acid (HF) to create an undercut area  312  beneath the Si device layer  300 . 
         [0016]    Referring now to  FIG. 3E , a vertical input (or output) facet  314  may be formed by patterning in the nitride layer  306 . Thereafter a dry etch may be used to etch down to the oxide layer  302 . This dry etch may result in a rather poor quality sidewall, not yet suitable for use as an input facet. 
         [0017]    Referring to  FIG. 3F  the wafer  304  may be wet etched such as by being immersed in a crystallographic etchant such as potassium hydroxide (KOH). In some embodiments, ammonium hydroxide (NH4OH), ethylene diamene pyrocatechol (EDP) or tetramethyl ammonium hydroxide (TMAH) may be used. As shown, this wet etch creates a key hole cavity  320  in the Si waveguide layer  300  the BOX layer  302  and the handle wafer  304 . Optionally, if the handle wafer  304  is prior heavily boron-doped (˜1020 cm-3) by implantation, the handle wafer  304  may not be etched. As shown, this wet etch essentially polishes and creates a smooth surface vertical facet  318  suitable for the input/out of light and, in addition creates the re-entrant mirror (REM)  322  oriented at an angle approximately 35.3° to the horizontal wafer plane. 
         [0018]    As shown in  FIG. 4 , the nitride layer  306  may be optionally removed. The wafer  304  may be re-planarized by depositing and reflowing a thick oxide layer  400 , for example, to seal the key hole  320  and then dry etched. Alternately a polymeric material may be used for replanarization. According to embodiments, the waveguide  330  in the Si layer  300  should bend at approximately 54.7°, into (110) direction between the input facet  318  and the re-entrant mirror  322 . A photodetector (such as  108  shown in  FIG. 1 ) may be formed on the surface of the wafer  300 , positioned above the mirror  322 . Such compact Ge photodetectors can be fabricated using standard surface processing. 
         [0019]    In (110) silicon, two families of (111) planes are oriented vertically and 2 families of (111) planes are oriented at an angle of 35.3° to the wafer surface. By laying out the waveguide as shown in  FIGS. 2 and 4 , one can combine the vertical input facet  318  with the re-entrant mirror facet  322 . In addition, the 35.3° angle is sufficient for total internal reflection, so the mirror  322  is essentially lossless. 
         [0020]    The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
         [0021]    These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.