Abstract:
A drive circuit and drive method for lowering electrical current consumption by stopping individual operational amplifiers during writing onto pixels. The drive circuit of an embodiment of the present invention is comprised of a plurality of amplifier circuits formed for each different generated voltage potential based on a reference voltage; and a control unit for grouping a plurality of amplifier circuits to output adjacent gradation voltage into groups of two or more, and controlling individually turning single amplifier circuit and all other amplifier circuits in each group on and off.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The disclosure of Japanese Patent Application No. 2010-13375 filed on Jan. 25, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a drive circuit and a drive method for display devices. 
         [0004]    2. Description of Related Art 
         [0005]    The use of portable display devices in recent years typified by cellular telephones has made energy-saving essential in order to extend usage time in display control circuits for liquid crystal displays that drastically affect the battery usage time. Achieving low-power consumption or energy-saving in display control circuits requires efficient drive methods and drive circuits that use those methods. 
         [0006]    The technology in Japanese Unexamined Patent Publication No. 2008-129386 discloses a drive circuit for shortening the write period onto the pixel by separately controlling an initial first period of the write period, and a following second period.  FIG. 9  shows a block diagram of the structure of the liquid crystal display device described in Japanese Unexamined Patent Publication No. 2008-129386 is shown in  FIG. 9 . A diagram showing the structure of the source driver 15 of Japanese Unexamined Patent Publication No. 2008-129386 is shown in  FIG. 10 . 
         [0007]    An operational amplifier (hereafter called, “op-amp”) is formed in each of the nodes of the gradation setter unit  20  in source driver  15  as shown in  FIG. 10 . 
         [0008]    Until reaching a full charge after writing starts in the first period, the pixel charges to the gradation voltage potential of the designated node in the node group containing the node that must reach the target gradation voltage. Moreover, multiple wiring equivalent to the number of nodes in the node group is coupled in parallel between the designated node and the pixels. In the second period after the pixel has charged up to the target gradation voltage potential, the above described parallel coupling is eliminated and only the node matching the target gradation voltage potential remain coupled to the pixel. 
         [0009]      FIG. 11  shows the voltage potential V_A 1  ( a ) for node A 1 , the control signal SN 1  ( b ), and the control signal SC 1  ( c ).  FIG. 11  shows the waveform when the target gradation voltage is between V 1  through V 4  (gradation voltage of node group GN 1 ). As shown in  FIG. 11 , multiple wiring is coupled in parallel between the specified node and the pixel so that the wiring resistance drops and the pixel can charge within a short time. Afterwards, in the second period, the pixel can charge up to the target gradation voltage potential by coupling only to the specified node. 
         [0010]    The technology in Japanese Unexamined Patent Publication No. 2009-145639 discloses a drive circuit for lowering electrical power consumption by shorting one end of a first stored charge element and one end of a second stored charge element, to set an intermediate voltage potential when switching one end of the first stored charge element and one end of the second stored charge element between a high voltage potential and a low voltage potential. 
         [0011]    However these drive circuits contained no function for partial control of the op-amps and therefore have the problems that all of the op-amps are operating during the period when writing onto the pixel and that there is large electrical current consumption. 
       SUMMARY 
       [0012]    The drive circuit of the conventional art therefore had the problem of large current consumption because all the op-amps are operated during writing onto the pixels. 
         [0013]    The drive circuit according to an aspect of the present invention includes multiple amplifier circuits formed for each different gradation voltage potential generated based upon a reference voltage; and a control circuit for separately switching on or off: one amplifier circuit, and all other amplifier circuits within each group of amplifiers by grouping the multiple amplifier circuits for outputting adjacent voltages into sub-groups of two or more amplifier circuits. 
         [0014]    The drive method according to another aspect of this invention groups multiple amplifier circuits formed for each different gradation voltage generated based upon the reference voltages, into two or more amplifier circuits to output the adjacent gradation voltages; in the first period during the period when writing onto the pixel, operates a single amplifier circuit, and stops all other amplifier circuits in each group, in order to write onto the pixel from the amplifier circuit with the corresponding data in the second period following the first period. 
         [0015]    This type of structure which groups amplifier circuits formed at each different gradation voltage into units of two or more adjacent amplifier circuits to output the gradation voltages; is capable of separately switching on and off one op-amp circuit and all other op-amps in each group. Electrical power consumption can therefore be reduced in this way by operating only one op-amp within each group in the first period in the period for writing onto the pixel. 
         [0016]    The present invention can separately stop the op-amps in the period when writing onto the pixels and is therefore capable of reducing the electrical power consumption 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a block diagram showing the structure of the display device utilizing the drive circuit of the first embodiment; 
           [0018]      FIG. 2  is a drawing showing the structure of the drive circuit of the first embodiment; 
           [0019]      FIG. 3A  is a drawing showing each type of control signal waveform from the control unit supplied by drive circuit of the first embodiment; 
           [0020]      FIG. 3B  is a graph showing the voltage fluctuations in the data line DL_m; 
           [0021]      FIG. 4A  is a truth table showing the logic operation for the 64 gradation in the gradation voltage selector circuit of the drive circuit of the present embodiment; 
           [0022]      FIG. 4B  is a truth table showing the logic operation for the 64 gradation in the gradation voltage selector circuit of the drive circuit of the present embodiment; 
           [0023]      FIG. 5  is a circuit diagram showing the structure of the drive circuit of the second embodiment; 
           [0024]      FIG. 6A  is a drawing showing each type of control signal waveform from the control unit supplied by drive circuit of the second embodiment; 
           [0025]      FIG. 6B  is a graph showing the voltage fluctuations in the data line DL_m; 
           [0026]      FIG. 7  is a graph showing an example of the γ (gamma) curve for the 64 gradations; 
           [0027]      FIG. 8  is a circuit diagram showing the structure of the drive circuit of the third embodiment; 
           [0028]      FIG. 9  is a block diagram showing the structure of the display device described in Japanese Unexamined Patent Publication No. 2008-129386; 
           [0029]      FIG. 10  is a circuit diagram showing the structure of the drive circuit described in Japanese Unexamined Patent Publication No. 2008-129386; 
           [0030]      FIG. 11  is a diagram for describing the operation of the drive circuit described in Japanese Unexamined Patent Publication No. 2008-129386. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       [0031]    The structure of the display device utilizing the drive circuit of the first embodiment of the present invention is described next while referring to  FIG. 1 .  FIG. 1  is a block diagram showing the entire structure of the display device in the embodiment. The example described in this embodiment describes a drive circuit for processing 64 gradation display data, however the present invention is not limited to this example. 
         [0032]    The display device of this embodiment as shown in  FIG. 1  is comprised of a liquid crystal panel (hereafter referred to as, LCD (Liquid Crystal Display)  10 , a source driver unit  150 , a gate driver  50 , a gradation voltage generator circuit  200 , and a control unit  600 . The drive circuit of the present invention is comprised of a source driver unit  150 , and a gradation voltage generator circuit  200 . 
         [0033]    Liquid crystal pixels (hereafter referred to as pixels) are arrayed in a matrix of j lines and m rows within the LCD panel  10 . The pixels arrayed in this matrix are driven while coupled to j scanning lines SL_ 1  through SL —   j  and m data lines DL_ 1  through DL_m. 
         [0034]    Pixels are generally comprised of a thin film transistor (TFT) and a capacitor Cs and auxiliary capacitance Cj (not shown in drawing) for the liquid crystal cell. The capacitance Cs and auxiliary capacitance Cj are the capacitance across the drain electrode of the TFT and the common electrode (VCOM) of the LCD panel  10 . The capacitance Cs and auxiliary capacitance Cj hold the electrical charge accumulated across one frame period. 
         [0035]    Changing the orientation of the liquid crystal molecules according to the electrical charge quantity accumulated in the capacitor Cs and auxiliary capacitor Cj; and changing the amount of light transmittance from the backlight generates the gradation display. The TFT source electrode is coupled to the corresponding data line DL_ 1  through DL_m; and the TFT gate electrode is coupled to the corresponding scanning lines SL_ 1  through SL_j. 
         [0036]    The gate driver  50  sequentially selects the scanning lines SL_ 1  through SL_j, switching on the TFT of pixels coupled to the selected scanning lines SL_ 1  through SL_j. While the TFT are switched on, the output terminals S 1  through Sm of source driver unit  150  supply a gradation voltage corresponding to the display data, by way of the data lines DL_ 1  through DL —   m  to the capacitor Cs and auxiliary capacitor Cj for each pixel. 
         [0037]    The control unit  600  is a control circuit for controlling the gradation voltage generator circuit  200  and the source driver unit  150 . The control circuit  600  transfers the display data DATA, the control signal DAC_ON, the control signal OUTSW_ON, the strobe signal STRB, and the clock signal SCLK to the source driver unit  150 ; and also transfers the control signal A 1 ON and the control signal A 2 ON and the control signal GSWON to the gradation voltage generator circuit  200 . 
         [0038]    The source driver unit  150  is comprised of a data latch unit  400 , a DA converter circuit  300 , and the switching elements OUTSW 1  through OUTSWm. The data latch unit  400  is a two-stage structure comprised of the latch circuits  400 _ 1  through  400   —   m  and the latch circuits  401 _ 1  through  401   —   m . The initial stage latch circuits  400 _ 1  through  400   —   m  sequentially loads a one line portion of the display data DATA within one horizontal period in synchronization with the clock signal SCLK output from the control unit  600 . 
         [0039]    The second stage latch circuits  401 _ 1  through  401   —   m  receives the data from the initial stage latch circuits  400 _ 1  through  400   —   m  conveyed in synchronization with the strobe signal STRB output from the control unit  600 . The strobe signal STRB is output in the initial horizontal period so that data from the second stage latch circuits  400 _ 1  through  401   —   m  is retained within one horizontal period. 
         [0040]    The DA converter circuit  300  is comprised of the gradation voltage select circuits  300 _ 1  through  300   —   m . The gradation voltage select circuits  300 _ 1  through  300   —   m  outputs one optional gradation voltage from among the gradation voltages V 1  through V 64  from the gradation voltage generator circuit  200  according to data accumulated in the second stage latch circuits  400 _ 1  through  401   —   m.    
         [0041]    The switch elements OUTSW 1  through OUTSWm are installed between each source output terminal S 1  through Sm and each gradation voltage select circuit  300 _ 1  through  300   —   m . Each of the switch elements OUTSW 1  through OUTSWm are electrically shorted when the control signal OUTSW_ON is high. Each of the switch elements OUTSW 1  through OUTSWm are electrically open when the control signal OUTSW_ON is low. 
         [0042]    The source driver unit  150  is grouped into source driver circuits  150 _ 1  through  150   —   m  corresponding to each of the source driver output terminals S 1  through Sm. Each of the source driver circuits  150 _ 1  through  150   —   m  includes two stage latch circuits, a gradation voltage selector circuit, and a switch element. 
         [0043]    The drive circuit of this embodiment is described next while referring to  FIG. 2 .  FIG. 2  is a drawing showing the structure of the drive circuit of this embodiment. In  FIG. 2 , the latch circuits  400 _ 1  through  400   —   m  and the latch circuits  401 _ 1  through  401   —   m  of the source driver circuits  150 _ 1  through  150   —   m  are omitted. 
         [0044]    The gradation voltage generator circuit  200  includes the resistors R 1  through R 65 , the op-amps OP 1  through OP 64 , and the switch elements GSW 1  through GSW 64  as shown in  FIG. 2 . The resistors R 1  through R 65  generate a gradation voltage reference potential. The resistors R 1  through R 65  are serially coupled between the high level reference voltage VREFH and the low level reference voltage VREFL. A node N 1  is installed between the resistors R 1  and R 2 , a node N 2  between the resistor R 2  and resistor R 3 , and so on, and a node N 64  is installed between the resistor R 64  and resistor R 65 . The voltage potential of each of the nodes N 1  through N 64  is the reference voltage potential for each gradation voltage. 
         [0045]    Each of the nodes N 1  through N 64  are coupled to the non-inverting input terminals (+) of the op-amps OP 1  through OP 64 . The output from the op-amps OP 1  through OP 64  is coupled to the inverting input terminals (−). The op-amps OP 1  through OP 64  in other words, comprise a voltage follower. 
         [0046]    In the gradation voltage generator circuit  200 , four adjacent gradations are set as one group. In the present embodiment, the op-amps OP 1  through OP 4  are set as one group; the op-amps OP 5  through OP 8  as one group; and so on, and the op-amps OP 61  through OP 64  are set as one group. 
         [0047]    The op-amps OP 1  through OP 64  respectively output the gradation voltages V 1  through V 64 . If the gradation voltage V 1  is a high voltage potential and the gradation voltage V 64  is a low voltage potential; then the optimal gradation voltage is the second highest gradation voltage from among the (high gradation voltage side) of V 1  through V 32  that were sub-grouped into four gradations each. The optimal gradation voltage among the gradation voltages V 1  through V 4  for example is the gradation voltage V 2 . 
         [0048]    Moreover, among the low gradation voltage side of gradation voltage group V 33  through V 64 , the optimal gradation voltage is the second lowest voltage from the sub-groups of four gradations each. The optimal gradation voltage among the gradation voltages V 61  through V 64  for example is the gradation voltage V 63 . This optimal gradation voltage is described later on. 
         [0049]    The control unit  600  controls the op-amps OP 1  through OP 64  grouped into four gradations by way of the control signals A 1 ON and A 2 ON. The control signal A 1 ON controls the op-amp (OP 2 , OP 6 , . . . , OP 63 ) that outputs the optimal gradation voltage. If the control signal A 1 ON for example is high then the op-amps (OP 2 , OP 6 , . . . , OP 63 ) that output the optimal gradation voltage set to the operating state. If the control signal A 1 ON is low, then the op-amps (OP 2 , OP 6 , . . . , OP 63 ) that output the optimal gradation voltage set to the stop state and their output moreover is in a HiZ (high-impedance) state. 
         [0050]    The control unit  600  controls op-amps other than for outputting an optimal gradation voltage (OP 1 , OP 3 , OP 4 , . . . , OP 61 , OP 62 , OP 64 ) by way of the control signal A 2 ON. If the control signal A 2 ON for example is high, then the op-amps (OP 1 , OP 3 , OP 4  - - - OP 61 , OP 62 , OP 64 ) are in the operating state. If the control signal A 2 ON is low, then the op-amps (OP 1 , OP 3 , OP 4  - - - OP 61 , OP 62 , OP 64 ) set to the stop state and their output moreover is in a HiZ (high-impedance) state. 
         [0051]    The switch elements GSW 1  through GSW 64  are installed along the wiring that outputs the optimal gradation voltages and other gradation voltages grouped into sub-groups of four gradations each. Among the gradation voltages V 1  through V 4  in the group with high gradation voltages for example, the optimal gradation voltage is V 2 . The switch element GSW 1  is therefore installed between the gradation voltage V 1  and gradation voltage V 2 , the switch element GSW 3  between the gradation voltage V 2  and gradation voltage V 3 , and the switch element GSW 4  between the gradation voltage V 2  and gradation voltage V 4 . 
         [0052]    The optimal gradation voltage is V 63  among the gradation voltages V 61  through V 64  in the group with low gradation voltages. The switch element GSW 61  is therefore installed between the gradation voltage V 61  and the gradation voltage V 63 ; a switch element GSW 62  between the gradation voltage V 62  and the gradation voltage V 63 ; and a switch element GSW 64  between the gradation voltage V 63  and the gradation voltage V 64 . 
         [0053]    The control unit  600  controls the switch elements GSW 1  through GS 64  by way of the control signal GSWON. If the GSWON for example is high then each of the switch elements GSW 1  through GSW 64  is electrically shorted state. If the GSWON is low then each of the switch elements GSW 1  through GSW 64  is in an electrically open state. 
         [0054]    The wiring resistance pR for the gradation wiring expresses the parasitic resistance component in the aluminum wiring itself. The gradation voltage select circuits  300 _ 1  through  300   —   m  are comprised of the switch elements  302 _ 1  through  302 _ 6 , and the switch elements  303 _ 1  through  303 _ 6 . The switch elements  302 _ 1  and  303 _ 1  correspond to the lowest order bits of the display data; and the switch elements  302 _ 2  and  303 _ 2  correspond to the second bit from the bottom of the display data. 
         [0055]    The switch elements  302 _ 1  and  303 _ 1 , and the switch elements  302 _ 2  and  303 _ 2  are controlled by way of the control signal DAC_ON from the control unit  600  and are not dependent on the display data. When the control signal DAC_ON is high, all of the switch elements  302 _ 1  and  303 _ 1 , and switch elements  302 _ 2  and  303 _ 2  are set to an electrically shorted state (hereafter described as parallel operation). In parallel operation, the nodes Nd_ 1  and, N_ 1  and, N_ 2  and, N_ 3 , N_ 4  are set to the same voltage potential; and the node Nd- 2  and, N_ 61  and, N- 62  and, N_ 63 , N_ 64  are set to the same electrical potential. 
         [0056]    The switch elements  302 _ 3  through  302 _ 6 , and the switch elements  303 _ 3  through  303 _ 6  are switched on and off according to data other than the lower two bits of display data. 
         [0057]    The switch elements OUTSW 1  through OUTSWm are output terminals for the source driver  150  and are installed between each of the source output terminals S 1  through Sm and the gradation voltage select circuits  300 _ 1  through  300   —   m . If the control signal OUTSW_ON is high, then the switch elements OUTSW 1  through OUTSWm are set to an electrically shorted state. If the control signal OUTSW_ON is low, then the switch elements OUTSW 1  through OUTSWm are set to an electrically open state. 
         [0058]    When the switch elements OUTSW 1  through OUTSWm are in an electrically shorted state, gradation voltages from any one of an optional gradation voltage V 1  through V 64  selected by the gradation voltage select circuits  300 _ 1  through  300   —   m  is output from the source output terminals S 1  through Sm to each of the pixels  10 _ 1  through  10   —   m  by way of the data lines DL_ 1  through DL_m. 
         [0059]    The operation of the drive circuit of this embodiment is here described next while referring to  FIG. 3A  and  FIG. 3B .  FIG. 3A  shows the waveforms for each type of control signal (A 1 ON, A 2 ON, GSWON, DAC_ON, OUTSW_ON) that the control unit  600  supplies to the drive circuit.  FIG. 3B  is a graph showing the fluctuations in voltage potential along the data line DL_m. The example in the figure shows the case where any of the gradation voltages V 1  through V 4  are the voltage potential on the data lines DL —   m  during writing onto the pixel. 
         [0060]    In  FIG. 3A  and  FIG. 3B , the horizontal axis indicates the time and the vertical axis indicates the voltage amplitude.  FIG. 3A  shows each of the high and low levels for the respective control signals (A 1 ON, A 2 ON, GSWON, DAC_ON, OUTSW_ON). These control signals are also digital signals. In  FIG. 3A  and  FIG. 3B , the period T 1  between of Q 0  through Q 4  is a single horizontal period, the period T 2  for Q 1  through Q 3  is the write period for writing onto the pixel, the period T 3  of Q 1  through Q 2  is the first period, and the period T 4  of Q 2  through Q 3  is the second period. 
         [0061]    In the horizontal front porch period of Q 0  through Q 1 , the control signal states are set so that A 1 ON is in the high state, A 2 ON is low, GSWON is low, DAC_ON is low, and the OUTSW_ON is low. In this period, only the op-amps (OP 2 , OP 6 , . . . , OP 63 ) that output the optimal gradation voltage operate among the op-amps OP 1  through OP 64  divided into sub-groups of four gradations each; and all other op-amps (OP 1 , OP 3 , OP 4 , OP 5 , OP 7 , OP 8 , . . . , OP 61 , OP 62 , OP 64 ) are in a stopped state. The electrical current consumption by the op-amp itself during the single horizontal period (Q 0  through Q 1 ) is therefore one-fourth (¼) of the total current consumption. 
         [0062]    The first period utilizes parallel drive during the write period onto the pixel. During the first period for Q 1  through Q 2 , the control signal A 1 ON is in the high state, the control signal A 2 ON is low, the control signal GSWON is high, the control signal DAC_ON is high, the control signal OUTSW_ON is set to the high state. The control signal GSWON switching to the high state, causes the switch element GSW 1  through GSW 64  to switch to the electrically shorted state. The op-amps (OP 2 , OP 6 , . . . , OP 63 ) outputting the optimal gradation voltage each respectively drive four gradation lines. The wiring resistance in this case is therefore one-fourth of the wiring resistance when driving one gradation wire. 
         [0063]    The control signal DAC_ON switching to the high state, causes the switch element  302 _ 1  through  302 _ 2 , the switch element  303 _ 1  through  303 _ 2  of the lower two bits of the DA converter circuit  300  to set to an electrically shorted state regardless of the display data. The ON resistance of the switch elements  302 _ 1  through  302 _ 2  up to node Nd_ 1  therefore drops because the switch elements  302 _ 1  through  302 _ 2  are coupled in parallel. Moreover, the ON resistance of the switch elements  303 _ 1  through  303 _ 2  up to node Nd_ 21  therefore drops because the switch elements  303 _ 1  through  303 _ 2  are coupled in parallel. 
         [0064]    In the second period of Q 2  through Q 3 , the control signal A 1 ON is in the high state, the control signal A 2 ON is high, the control signal GSWON is low, the control signal DAC_ON is low, and the control signal OUTSW_ON is in the high state. In this period all of the op-amps OP 1  through OP 64  are in the operating state. The DA converter circuit  300  writes the data display dependent gradation voltage (any of voltages V 1  through V 4  in the example in  FIG. 3 ) onto the pixels  10 _ 1  through  10   —   m.    
         [0065]    Next, in the horizontal back porch period of the Q 3  through Q 4  period, the control signal states are sets so the control signal A 1 ON is in the high state, A 2 ON is low, GSWON is low, control signal DAC_ON is low, and the control signal OUTSW_ON is low. The writing onto the pixel ends in this way. In this period, only the op-amps (OP 2 , OP 6 , . . . , OP 63 ) outputting the optimal gradation voltage operate from among the op-amps OP 1  through OP 64  divided into sub-groups of four gradations each, and all other op-amps (OP 1 , OP 3 , OP 4 , OP 5 , OP 7 , OP 8 , . . . , OP 61 , OP 62 , OP 64 ) are in a stopped state. The electrical current consumption by the op-amp itself in this embodiment is therefore one-fourth (¼) of the total current consumption. 
         [0066]      FIG. 4A  and  FIG. 4B  are truth tables showing the logic operation 64 gradation (6 bits) of the gradation voltage select circuits  300 _ 1  through  300   —   m  in the drive circuit for this embodiment. The above related optimal gradation voltage is described next while referring to  FIG. 4A  and  FIG. 4B . In the actual display device AC drive inversion is utilized in each line or each frame to prevent burnout. Due to this inversion operation, the V 1  voltage potential may be low and the V 64  voltage potential may be high. 
         [0067]    The gradation voltage relation for 64 gradations when established as gradation voltage V 1 &gt;gradation voltage V 2 &gt;gradation voltage V 3  - - - &gt; gradation voltage V 64  is described using  FIG. 4A  and  FIG. 4B . The input signals for the gradation voltage select circuits  300 _ 1  through  300   —   m  are the control signal DAC_ON from the control unit  600 , the display data D 5  through D 0  accumulated in the second stage latch circuits  401 _ 1  through  401   —   m , and the gradation voltages V 1  through V 64  from the gradation voltage generator circuit  200 . 
         [0068]    The output signals from the gradation voltage select circuits  300 _ 1  through  300   —   m  are the gradation voltages V 1  through V 64  equals [000000], then the output voltage is the gradation voltage V 1 . If the input signal DAC_ON=0, and D 5  through D 0 =[000001], then the output voltage is the gradation voltage V 2 , and so on. If the input signal DAC_ON=0, and D 5  through D 0 =[111111] then the output voltage is the gradation voltage V 64 . 
         [0069]    Moreover, if the input signal DAC_ON=1, then the specified optimal gradation voltage from among the adjacent sub-groups divided into four gradations each, is output and is not dependent on the display data D 1  through D 0  accumulated in the second stage latch circuits  401 _ 1  through  401   —   m.    
         [0070]    As shown in  FIG. 4B , when the display data accumulated in the second stage latch circuits  401 _ 1  through  401   —   m  is for example [000000] through [000011], the gradation voltage selector circuit selects the gradation voltage V 2  as the optimal gradation voltage. Also, when the display data accumulated in the second stage latch circuits  401 _ 1  through  401   —   m  is for example [000100] through [000111], then the selector circuit selects the gradation voltage V 6  as the optimal gradation voltage; and so on, and when the display data accumulated in the second stage latch circuits  401 _ 1  through  401   —   m  is [011100] through [011111], the selector circuit selects the gradation voltage V 30  as the optimal gradation voltage. 
         [0071]    When the display data accumulated in the second stage latch circuits  401 _ 1  through  401   —   m  is [100000] through [100011], the gradation voltage selector circuit selects the gradation voltage V 35  as the optimal gradation voltage. When the display data accumulated in the second stage latch circuits  401 _ 1  through  401   —   m  is [100100] through [100111], the gradation voltage selector circuit selects the gradation voltage V 39  as the optimal gradation voltage, and so on, and when the display data accumulated in the second stage latch circuits  401 _ 1  through  401   —   m  is [1111000] through [111111], the gradation voltage selector circuit selects the gradation voltage V 63  as the optimal gradation voltage. 
         [0072]    The optimal gradation voltage is described next. In the gradation voltage V 1  through V 32  group having a high gradation voltage, the second highest among the gradation voltages divided into sub-groups of four gradients each is set as the optimal gradation voltage. The reason for this selection is that a transition is made to the second period just before reaching the optimal gradient voltage in the first period, in order to maintain a long drive period in the second period, and in this way allow writing a gradient voltage corresponding to the display data on the pixel at the point in time that the second period has ended in order to avoid deterioration in the image quality. 
         [0073]    If the optimal gradation voltage was set to V 1 , then a transition to the second period is made at the stage where the gradation voltage at the end of the first period, reaches a voltage (gradation voltage of approximately V 2  to V 3 ) somewhat lower than the gradation voltage V 1 . If the gradation voltage selector circuit selected the gradation voltage V 4  in the second period then the voltage potential lowers to the gradient voltage V 4  from approximately the gradation voltage V 2  to V 3 . The voltage is in this way raised to a gradation voltage V 2  to V 3  and the voltage then lowered to a gradation voltage V 4  so that wasteful voltage fluctuations of approximately 1.5 gradations are made to occur. 
         [0074]    If the optimal gradation voltage was set to V 4 , then a transition to the second period is made at the stage where the gradation voltage at the end of the first period, reaches a voltage (gradation voltage of approximately V 5  through V 6 ) somewhat lower than the gradation voltage V 4 . If the gradation voltage selector circuit selected a gradation voltage V 1  in the second period, then the voltage potential of gradation voltage V 1  must be raised approximately 4.5 gradations from gradation voltage V 5  to V 6 . However drive performance is low since parallel drive is not used in the second period so the voltage potential might not rise to gradation voltage V 1  in the second period. 
         [0075]    In order to suppress wasteful voltage fluctuations in the first period and obtain highly efficient drive performance in the second period in this way, the optimal gradation voltage among the high gradation voltages V 1  through V 4  is set as gradation voltage V 2 , which is the second highest gradation voltage. The optimal gradation voltage among the low gradation voltages V 61  through V 64  is set in the same way as gradation voltage V 63 , which is the second from the lowest gradation voltage. 
         [0076]    The present invention as described above is capable of separately switching one op-amp circuit, and all other op-amps on and off within each group formed by dividing the multiple op-amps into sub-groups of two or more op-amps for outputting adjacent gradation voltages. The invention can in this way operate just one op-amp among each group in the first period within one write period. The electrical power consumption can in this way be reduced. 
         [0077]    Moreover, the outputs from op-amps other than the single operating op-amp are electrically shorted in the first period. The wiring resistance can in this way be reduced and the write period when writing onto the pixel can be shortened. In the second period following the first period, all op-amps outputting adjacent gradation voltages within a single group are set to the operating state. Gradation voltages that correspond to the display data can in this way be written onto the pixel. 
         [0078]    Electrical current consumption in periods other than the second period can be lowered by stopping all other than one of the op-amps sub-divided into groups. This embodiment is capable of setting three of the four op-amps to the stopped state. The electrical current consumption can therefore be reduced by three-fourths in all periods other than the second period compared to when operating all of the four op-amps. 
       Second Embodiment 
       [0079]    The structure of the drive circuit of the second embodiment of this invention is described next while referring to  FIG. 5 .  FIG. 5  is a diagram showing the structure of the drive circuit of this embodiment. The point where this embodiment differs from the first embodiment is that the gradation voltage generator circuit  200  shown in  FIG. 2  has been replaced by a gradation voltage generator circuit  201 , and that the switch elements DSW 1  through DSW 64  have been newly added. The example in this embodiment describes processing the 64 gradation display data the same as in the first embodiment. In  FIG. 5 , the same reference numerals are assigned to the same structural elements as in  FIG. 2  and their description is omitted. 
         [0080]    The switch elements DSW 1  through DSW 64  are installed on the output side of the respective op-amps OP 1  through OP 64 . The switch elements DSW 1  through DSW 64  are switch circuits that switch on and off regardless of the switch elements GSW 1  through GSW 64 . The control unit  600  controls the switch elements DSW 1  through DSW 64  by way of the control signals GSWON. 
         [0081]    The operation of the drive circuit of this embodiment is described here while referring to  FIGS. 6A and 6B .  FIG. 6A  is a drawing showing a waveform of each control signal (A 1 ON, A 2 ON, GSWON, OUTSW_ON) supplied to the drive circuits from the control unit  600 .  FIG. 6B  is a graph showing voltage fluctuations along the data line DL_m. The point where  FIG. 6A  and  FIG. 6B  differ from  FIG. 3A  and  FIG. 3B  is that the control signal A 2 ON change timing has shifted from Q 2  to Q 5 . 
         [0082]    Even if an operation start signal has been input after the stop state, op-amps generally require a start-up time to allow the voltages in the internal circuitry to stabilize. In the present embodiment, the timing to start operation of op-amps (OP 1 , OP 3 , OP 4 , . . . , OP 61 , OP 62 , OP 64 ) other than those outputting an optimal gradation voltage, starts earlier (Q 5 ) than the start of the second period (Q 2 ). The output from op-amps other than for outputting an optimal gradation voltage can in this way be stabilized by the start of the second period. The drive circuit of this embodiment can therefore smoothly write a gradation voltage corresponding to the display data in the second period, and can shorten the total write time. 
         [0083]    The drive circuit of this embodiment moreover can stop three-quarters (¾) of the op-amps in the period T 5  for Q 5  through Q 2  within the first period T 3 . The drive circuit can in this way reduce electrical power consumption within the op-amp itself. 
       Third Embodiment 
       [0084]      FIG. 7  is a graph showing an example of the γ (gamma) curve for the 64 gradations. In  FIG. 7 , the horizontal axis indicates the gradation and the vertical axis indicates the gradation voltage. The γ (gamma) curve generally differs according to the positive or negative polarity or the respective individual liquid crystal panel characteristics. In the example shown in  FIG. 7  utilizing 64 gradations, there is a large differential in the adjacent optimal voltages of the upper side (gradation voltage V 1 ) and the lower side (gradation voltage V 64 ). However the differential between the gradation voltage in the vicinity of the middle section (gradation voltage V 32 ) and the adjacent gradation voltages is small. 
         [0085]    The drive circuit of this embodiment of the present invention is here applied to an LCD panel  10  having the gamma curve as shown in  FIG. 7 . The structure of the drive circuit of the third embodiment is described here while referring to  FIG. 8 .  FIG. 8  is a diagram showing the structure of the drive circuit of the present embodiment. In  FIG. 8 , the same reference numerals are assigned to the same structural elements as in  FIG. 2  and their description is omitted. 
         [0086]      FIG. 8  shows an example of the upper eight gradation portion among the 64 gradations. Unlike the first embodiment, the upper and lower four gradation portion among the 64 gradations are not configured for parallel drive. Namely, compared to  FIG. 2 , there are no switch elements (GSW 1  through GSW 4 ) on the output side of the op-amp (OP 1  through OP 4 ) for electrically shorting the gradation wiring. 
         [0087]    The timing at which the control unit  600  outputs each type of control signal is identical to the timing in the first embodiment. The control unit  600  utilizes the control signal A 1 ON for on and off control of the 4 gradation portion of op-amps (OP 1  through OP 4 ). The switch elements  302 _ 1  through  302 _ 2  of the gradation select circuit coupled to the gradation voltages V 1  through V 4  are constantly switching on and off according to the display data. 
         [0088]    The group of gradation voltages V 1  through V 4  is not driven in parallel so the drive performance becomes small compared to the vicinity of the middle gradation group in the first period. Therefore in order to boost drive performance, the line resistance value pRL for gradation voltages V 1  through V 4  must be made smaller than the other line resistance pR. 
         [0089]    The example in  FIG. 8  shows the upper side eight gradation portion, however the same structure may be utilized for the lower side gradation voltages V 61  through V 64 . In other words, there are no switch elements (GSW 61  through GSW 64 ) on the output side of the op-amp (OP 61  through OP 64 ) for electrically shorting the gradation wiring. 
         [0090]    The control unit switches the op-amps (OP 61  through OP 64 ) on and off by way of the control signal A 1 ON. Also, the switch elements  303 _ 1  through  303 _ 2  of the gradation select circuit coupled to the gradation voltages V 61  through V 64  are constantly switching on and off according to the display data. 
         [0091]    The group of gradation voltages V 61  through V 64  is not driven in parallel so the drive performance becomes small compared to the vicinity of the middle gradation group in the first period. The line resistance value pRL for the gradation voltages V 61  through V 64  must be made smaller than the other line resistance pR in order to boost the drive performance. 
         [0092]    The present embodiment is therefore capable of suppressing increases in electrical current consumption due to voltage fluctuations when there is a large voltage differential between adjacent gradation voltages in the groups divided into sub-groups. 
         [0093]    The present invention as described above is capable of operating just the op-amp that outputs the optimal gradation voltage and switching off all other op-amps in the initial first period of the write period within an op-amp group comprised of multiple op-amps for outputting adjacent gradation voltages. In the second period following the first period, all op-amps are operated and a gradation voltage corresponding to the display data can in this way be written onto the pixel. Electrical current consumption by the drive circuit can in this way be reduced. 
         [0094]    The technology in Japanese Unexamined Patent Publication No. 2008-129386 includes a comparator circuit for preventing punch-through current due to the op-amps that output each gradation voltage shorting to each other. The present invention however operates only one of the grouped op-amps in the first period within one horizontal period and therefore no punch-through current flows between the op-amps. No comparator circuit is therefore needed so the drive circuit can have a smaller surface area. 
         [0095]    The present invention moreover performs no parallel drive when there is a large differential in gradation voltages between the op-amps sub-divided into groups. The present invention in this way suppresses increased electrical current consumption while preventing undesirable voltage fluctuations during pixel writing. 
         [0096]    The present invention is not limited to the above embodiments and all manner of changes and adaptations not departing from the scope and spirit of the present invention are permitted. The number of op-amps, the number of gradations and the γ (gamma) curves and so on for the op-amps divided into groups as described in the embodiments are only examples and do not limit this invention.