Abstract:
A digital free-running clock oscillator comprises a circuit synchronizing the operation of the oscillator with an asynchronous timing signal from an external source, and is provided with a protection circuit for preventing a logic race condition in the synchronizing circuit during a period of coincident transition of the oscillator output and the external timing signal.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to oscillators, and more particularly to a free-running oscillator synchronized with an external asynchronous pulse. 
     Computer systems are required to work efficiently with data stores of different speeds within the same system. If a semiconductor data store is used, the characteristics of the dynamic storage devices require that data in the storage elements be refreshed periodically. If store refresh operations are accomplished internally of the data store, the response time of the store will vary, and, accordingly, fully synchronous operation of a data store and the system central processor is not practical or desirable. Nevertheless, data transfer between the two units must be synchronized. One means of effecting synchronization between asynchronously operating units of a computer system involves resynchronization or restarting of a clock signal source of one unit, for example a free-running oscillator forming a part of such unit, with a clock signal from another unit. However, clock synchronizing circuits using logic gates are particularly susceptible to logic race conditions inasmuch as the asynchronous clock signals of the various units of the system drift with respect to each other. Such logic race conditions can result in the generation of clock signals having pulse widths of insufficient duration for proper system operation. 
     Accordingly, it is an object of the invention to provide an improved synchronizing circuit for a free-running clock signal generator. 
     Another object of the invention is to provide an improved free-running clock signal generator having a digital logic circuit for synchronizing the generation of the clock signals with an asynchronous clock signal from an external source. 
     Another object of the invention is to provide an improved digital-logic clock signal synchronizing circuit which provides protection against logic race conditions. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a free-running clock signal oscillator comprises a logic element supplying a clock-signal output connected in driving relation to a precision delay line, wherein the output of the delay line is connected back to the input of the logic element whereby the delay line serves as the timing element of the oscillator. The logic element also receives as an input a control signal from an asynchronously operating external source with which the clock signal output is to be synchronized. This control signal turns the oscillator on and off, thereby synchronizing the operation of the oscillator with the control signal. The control signal is coupled to the aforementioned logic element through a logic-race protection circuit which prevents a transition of the control signal when the clock signal output is in transition and when a potential logic-race condition exists in the logic element of the oscillator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     While the invention is set forth particularity in the appended claims, other objects, features, the organization and method of operation of the invention will become more apparent, and the invention will best be understood, by referring to the following detailed description in conjunction with the accompanying drawings in which: 
     FIG. 1 is a logic diagram of a free-running clock signal generator of the type utilized in the present invention; 
     FIG. 2 is a logic diagram of a free-running clock signal generator in accordance with the instant invention; and 
     FIGS. 3, 4 and 5 are timing diagrams useful in explaining the operation of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the drawings for a more detailed description of the construction, operation and other features of the instant invention by characters of reference, FIG. 1 shows a free-running oscillator circuit comprising a NAND logic element or gate 10 having an input terminal 12 receiving an asynchronous control signal CS. An output terminal 14 of the NAND gate 10 is connected to an input terminal of a delay element 16 having a time delay of T2, while an output 18 of the delay element 16 is connected as a second input of the NAND gate 10. When the CS control signal is enabled or high, the oscillator runs but when the CS signal is disabled or low, the oscillator output signal KS at the output terminal 14 of the NAND gate 10 remains high. The CS control signal therefore turns the oscillator output with the rising edge of the CS signal. A first transition from high to low of the KS output signal follows the transition of the CS control signal from low to high by one gate delay, the delay of the NAND logic element 10. Subsequent transitions of the KS clock signal occur after delay T2 plus the gate delay of the NAND gate 10. The oscillator circuit of FIG. 1 represents the prior art which has a disadvantage of possible unstable operation due to a logic race condition when the CS control signal changes state at the same time the KS output of the NAND gate 10 changes. At such time a KS clock signal having less than acceptable pulse width can occur. 
     Referring now to FIG. 2 in conjunction with the timing diagrams of FIGS. 3 and 4, a free-running clock synchronizer circuit in accordance with the present invention includes a transparent latch circuit 30 receiving a CS1 control signal on an input terminal 32. The latch circuit 30 may comprise a conventional storage element such as a D bistable or flip-flop. An output terminal 34 of the latch circuit 30, signal CSL, is connected as one input of a NAND logic element or gate 36, the output of which is the clock signal KS1. Clock signal KS1 is coupled to input terminal 37 of delay line 38 adapted to produce a first output at tap 40 after a time delay T1. This first output at tap 40 of the delay line 38, signal DL1, is connected as a first input of an AND gate 41 while a second output tap 44 of the delay line 38, signal DL2, is connected as a second input of the NAND gate 36. The delay at the second output tap 44 of the delay line 38 is T2, T2 being greater than T1. The CSL signal is connected as a second input of the AND gate 41, an output of which is supplied as a first input of a NAND gate 42. Tap 44 of the delay line 38 further provides a second input to NAND gate 42 via an inverter 46, and NAND gate 42 supplies a signal DLE at terminal 48 which is connected to a latch-enable input 50 of the latch circuit 30. 
     The KS1 signal output of the NAND gate 36 is a square wave clock signal with a period 2(T2+D1) where D1 is the gate delay of the NAND gate 36. The latch circuit 30 functions normally as a transparent logic element that passes the CS1 control signal directly, with only one gate delay, to the NAND gate 36 as control signal CSL on terminal 34. The CSL signal gates the KS1 oscillator output signal off and on so the oscillator output signal is synchronized with the SC1 control signal. 
     The enabling (high) output at terminal 48 of the NAND gate 42 normally enables the latch circuit 30 to pass the CS1 control signal as the CSL signal. But after the positive portion of the KS1 signal has traversed the delay line 38 and appears at the T1 output tap 40 as the DL1 signal, the CSL and DL1 signals enable the AND gate 41 which causes the DLE signal output at terminal 48 of the NAND gate 42 to go low for a period T2-T1 and disable latch 30, i.e. when a positive-to-negative transition of the KS1 signal may occur. As shown in FIG. 3, the CS1 signal might also be in transition from high to low during such period. The disabled latch circuit 30 then protects the oscillator circuit from an undefined or unstable logic condition of NAND gate 36 caused by the CS1 control signal changing state at or near the same time the KS1 output of the NAND gate 36 changes. In particular, the latch circuit 30 prevents KS1 from returning immediately to a positive level until after the DLE signal concludes and latch 30 generates the falling edge of CSL. The circuit output is then synchronized with the rising edge of the CSL signal so that delaying the generation of the falling edge of the CSL signal does not adversely affect circuit operation. It is seen, however, that the circuit is prevented from generating pulses shorter than a given duration. 
     FIG. 4 is an expansion of the potentially unstable period when the DLE signal is low, and shows the gate delays associated with the generation of a minimum-width negative transition of the KS1 clock signal. The protection circuit comprising the gates 41, 42, 46 and the latch circuit 30 ensures that a negative portion of the KS1 signal will have a length of at least three gate delays. 
     Referring to FIG. 5, if the CSL signal is in the logic low state when the DL1 signal goes true, the AND gate 41 is disabled and the DLE signal output on terminal 48 is inhibited from going low thereby preventing the latch circuit 30 from closing when the CS1 signal is in transition from low to high. 
     While the principles of the invention are clear in reference to the foregoing illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications of structure, arrangement, and components used in the practice of the invention, and otherwise, which are particularly adapted for specific environments and operating requirements without departing from those principles. The appended claims are, therefore, intended to cover and embrace any such modifications, within the limits only of the true spirit and scope of the invention.