Abstract:
An image-sensing apparatus has a solid-state image-sensing device and a horizontal and a vertical scanning circuit. The solid-state image-sensing device has a plurality of pixels arranged in a matrix, and each pixel includes a photoelectric conversion element. The solid-state image-sensing device further has an adder circuit for adding together the outputs of a plurality of pixels. The horizontal and vertical scanning circuits are for reading out signals from the individual pixels. The operation of at least one of the horizontal and vertical scanning circuits is selectable between progressive scanning and interlaced scanning, and one among a plurality of units of stages that constitute that scanning circuit outputs a select signal during interlaced scanning.

Description:
[0001]    This application is based on Japanese Patent Application No. 2002-173077 filed on Jun. 13, 2002, the contents of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to an image-sensing apparatus, and more particularly to an image-sensing apparatus that can perform interlaced scanning.  
           [0004]    2. Description of the Prior Art  
           [0005]    In an image-sensing apparatus, it is common to increase the frame rate by performing interlaced scanning, i.e., by reading out pixel data every other row or every other column.  
           [0006]    Conventionally, interlaced scanning is achieved by validating only the outputs from the desired stages of a shift register. For this reason, in interlaced scanning, to obtain the same scanning rate as when all photoelectric conversion elements are scanned, quite inconveniently, it is necessary to feed the shift register with pulses having a higher frequency than when all photoelectric conversion elements are scanned.  
         SUMMARY OF THE INVENTION  
         [0007]    An object of the present invention is to provide an image-sensing apparatus that can perform interlaced scanning at the same scanning rate as when all photoelectric conversion elements are scanned without requiring pulses having a higher frequency than when all photoelectric conversion elements are scanned.  
           [0008]    To achieve the above object, according to one aspect of the present invention, an image-sensing apparatus is provided with a solid-state image-sensing device and a horizontal and a vertical scanning circuit. Here, the solid-state image-sensing device has a plurality of pixels arranged in a matrix, and each pixel includes a photoelectric conversion element. The solid-state image-sensing device also has an adder circuit for adding together the outputs of a plurality of pixels. The horizontal and vertical scanning circuits are for reading out signals from the individual pixels. The operation of at least one of the horizontal and vertical scanning circuits is selectable between progressive scanning and interlaced scanning, and one at a time among a plurality of units of stages that constitute that scanning circuit outputs a select signal during interlaced scanning.  
           [0009]    According to another aspect of the present invention, an image-sensing apparatus is provided with a solid-state image-sensing device and a scanning circuit. Here, the solid-state image-sensing device has a plurality of pixels, and each pixel includes a photoelectric conversion element. The scanning circuit is for scanning the pixels. The operation of the scanning circuit is selectable between progressive scanning and interlaced scanning, and interlaced scanning is switchable between a first mode and a second mode that differ in the number of lines skipped by interlacing.  
           [0010]    According to still another aspect of the present invention, an image-sensing apparatus is provided with a solid-state image-sensing device and a scanning circuit. Here, the solid-state image-sensing device has a plurality of pixels arranged in a matrix, and each pixel includes a photoelectric conversion element. The scanning circuit is for scanning the pixels. The scanning circuit performs scanning at a frequency equal to or higher than twice the scanning signal frequency. The operation of the scanning circuit is selectable between progressive scanning and interlaced scanning. Interlaced scanning is performed at a higher frame rate than progressive scanning, or alternatively interlaced scanning is performed with a lower scanning pulse frequency than progressive scanning. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    This and other objects and features of the present invention will become clear from the following description, taken in conjunction with the preferred embodiments with reference to the accompanying drawings in which:  
         [0012]    [0012]FIG. 1 is a block diagram of an image-sensing apparatus according to the invention;  
         [0013]    [0013]FIG. 2 is a block diagram of the X-Y address area sensor shown in FIG. 1;  
         [0014]    [0014]FIG. 3 is a circuit diagram of the vertical scanning circuit shown in FIG. 2;  
         [0015]    [0015]FIG. 4 is a circuit diagram of the flip-flop shown in FIG. 3;  
         [0016]    [0016]FIG. 5 is a circuit diagram of the horizontal scanning circuit shown in FIG. 2;  
         [0017]    [0017]FIG. 6 is a circuit diagram of the flip-flop shown in FIG. 5;  
         [0018]    [0018]FIG. 7 is a timing chart of the signals generated by the timing generator shown in FIG. 1;  
         [0019]    [0019]FIG. 8 is a block diagram of the scan mode switcher shown in FIG. 1;  
         [0020]    [0020]FIGS. 9A to  9 C are timing charts of the signals fed to the vertical scanning circuit shown in FIG. 2;  
         [0021]    [0021]FIGS. 10A to  10 C are timing charts of the signals fed to the horizontal scanning circuit shown in FIG. 2;  
         [0022]    [0022]FIG. 11 is a block diagram of another image-sensing apparatus according to the invention;  
         [0023]    [0023]FIG. 12 is a block diagram of the X-Y address area sensor shown in FIG. 11;  
         [0024]    [0024]FIG. 13 is a circuit diagram of the vertical scanning circuit shown in FIG. 12;  
         [0025]    [0025]FIG. 14 is a circuit diagram of the flip-flop shown in FIG. 13;  
         [0026]    [0026]FIG. 15 is a circuit diagram of the horizontal scanning circuit shown in FIG. 12;  
         [0027]    [0027]FIG. 16 is a circuit diagram of the flip-flop shown in FIG. 15;  
         [0028]    [0028]FIG. 17 is a block diagram of the scan mode switcher shown in FIG. 11;  
         [0029]    [0029]FIGS. 18A to  18 C are timing charts of the signals fed to the vertical scanning circuit shown in FIG. 12;  
         [0030]    [0030]FIGS. 19A to  19 C are timing charts of the signals fed to the horizontal scanning circuit shown in FIG. 12;  
         [0031]    [0031]FIG. 20 is a block diagram of still another image-sensing apparatus according to the invention;  
         [0032]    [0032]FIG. 21 is a block diagram of the X-Y address area sensor shown in FIG. 20;  
         [0033]    [0033]FIG. 22 is a circuit diagram of the vertical scanning circuit shown in FIG. 21;  
         [0034]    [0034]FIG. 23 is a circuit diagram of the flip-flop shown in FIG. 22;  
         [0035]    [0035]FIG. 24 is a circuit diagram of the horizontal scanning circuit shown in FIG. 21;  
         [0036]    [0036]FIG. 25 is a circuit diagram of the flip-flop shown in FIG. 24;  
         [0037]    [0037]FIG. 26 is a block diagram of the scan mode switcher shown in FIG. 20;  
         [0038]    [0038]FIGS. 27A to  27 C are timing charts of the signals fed to the vertical scanning circuit shown in FIG. 21;  
         [0039]    [0039]FIGS. 28A to  28 C are timing charts of the signals fed to the horizontal scanning circuit shown in FIG. 21;  
         [0040]    [0040]FIG. 29 is a circuit diagram of each of the pixels constituting the sensing portion shown in FIGS. 2, 12, and  21 ;  
         [0041]    [0041]FIG. 30 is a timing chart of the relevant signals during detection of pixel-to-pixel variations;  
         [0042]    [0042]FIG. 31 is a diagram showing a first circuit configuration for interconnection between pixels;  
         [0043]    [0043]FIG. 32 is a diagram showing a second circuit configuration for interconnection between pixels;  
         [0044]    [0044]FIG. 33 is a diagram showing a third circuit configuration for interconnection between pixels; 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0045]    Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an image-sensing apparatus according to the invention. In FIG. 1, reference numeral  10 _ 1  represents an X-Y address area sensor, reference numeral  20  represents a timing generator, and reference numeral  30 _ 1  represents a scan mode switcher.  
         [0046]    [0046]FIG. 2 is a block diagram of the X-Y address area sensor  10 _ 1 . As shown in FIG. 2, the X-Y address area sensor  10 _ 1  includes a sensing portion  1  having a plurality of pixels G( 1 ,  1 ), G( 1 ,  2 ), . . . , G( 1 , n), G( 2 ,  1 ), G( 2 ,  2 ), . . . G( 2 , n), . . . , G(m,  1 ), G(m,  2 ), . . . , and G(m, n), each having a photoelectric conversion element, arranged in a matrix-like formation, a vertical scanning circuit  2 _ 1  for vertically scanning the sensing portion  1 , and a horizontal scanning circuit  3 _ 1  for horizontally scanning the sensing portion  1 . Here, m and n each represent a positive integral number.  
         [0047]    The sensing portion  1  includes m vertical scanning lines L_ 1 , L_ 2 , . . . , and L_m; n signal lines S_ 1 , S_ 2 , . . . , and S_n; n horizontal scanning lines C_ 1 , C_ 2 , . . . , and C_n, n MOS transistors T_ 1 , T_ 2 , . . . , and T_n; and a readout line OUT. Let p be an integral number fulfilling 1≦p≦m and q be an integral number fulfilling 1≦q≦n. Then, the pixel G(p, q) is connected to the vertical scanning line L_p and to the signal line S_q. Moreover, the signal line S_q is connected, through the drain-source channel of the corresponding transistor T_q, commonly to the readout line OUT. Furthermore, the transistor T_q has its gate connected to the horizontal scanning line C_q.  
         [0048]    In the sensing portion  1 , when the vertical scanning line L_p is driven with a low-level direct-current voltage, the data of the pixels G(p,  1 ), G(p,  2 ), . . . , and G(p, n) are delivered to the signal lines S_ 1 , S_ 2 , . . . , and S_n, respectively. On the other hand, when the horizontal scanning line C_q is driven with a low-level direct-current voltage, the transistor T_q is turned ON, and the data on the signal line S_q are fed out via the readout line OUT.  
         [0049]    The vertical scanning circuit  2 _ 1  receives a vertical scanning start signal φVS from the timing generator  20 , and receives six vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, φV2 — 1, φV2 — 2, and φV2 — 3 and signals CNT 1 , CNT 2 , and CNT 3  from the scan mode switcher  30 _ 1 .  
         [0050]    The horizontal scanning circuit  3 _ 1  receives a horizontal scanning start signal φHS from the timing generator  20 , and receives six horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, φH2 — 1, φH2 — 2, and φH2 — 3 and signals CNT 1 , CNT 2 , and CNT 3  from the scan mode switcher  30 _ 1 .  
         [0051]    [0051]FIG. 3 shows the circuit configuration of the vertical scanning circuit  2 _ 1 . In FIG.  3 , reference numerals  211 _ 1 ,  211 _ 2 , . . . represent flip-flops, reference numerals  212 _ 1 ,  212 _ 2 , . . . represent NAND gates, and reference numerals  213 _ 1 ,  213 _ 2 , . . . represent inverters. There are provided m of each of these flip-flops, NAND gates, and inverters.  
         [0052]    The flip-flops  211 _ 1 ,  211 _ 2 , . . . are latches of the type that, while a strobe signal is active, outputs the input thereto intact and that, when the strobe signal becomes inactive, holds and outputs the immediately previous input thereto. Incidentally, this type of latch is called a G latch. The flip-flops  211 _ 1 ,  211 _ 2 , . . . are connected in series to form a shift register.  
         [0053]    The flip-flop  211 _ 1  receives the vertical scanning start signal φVS. The flip-flops  211 _ 2 ,  211 _ 3 , . . . and,  211   —   m  receive the outputs of the flip-flops  21 _ 1 ,  211 _ 2 , . . . , and  211 _(m−1), respectively.  
         [0054]    The NAND gates  212 _ 1 ,  212 _ 5 ,  212 _ 9 , . . . receive at one input terminal thereof the signal CNT 1 , and receive at the other input terminal thereof the outputs of the flip-flops  211 _ 1 ,  211 _ 5 ,  211 _ 9 , . . . , respectively.  
         [0055]    The NAND gates  212 _ 2 ,  212 _ 4 ,  212 _ 6 , . . . receive at one input terminal thereof the signal CNT 2 , and receive at the other input terminal thereof the outputs of the flip-flops  211 _ 2 ,  211 _ 4 ,  211 _ 6 , . . . , respectively.  
         [0056]    The NAND gates  212 _ 3 ,  212 _ 7 ,  212 _ 11 , . . . receive at one input terminal thereof the signal CNT 3 , and receive at the other input terminal thereof the outputs of the flip-flops  211 _ 3 ,  211 _ 7 ,  211 _ 11 , . . . , respectively.  
         [0057]    The output of the NAND gate  212   —   p  is fed to the inverter  213   —   p . With the output of the inverter  213   —   p , the vertical scanning line L_p of the sensing portion  1  is driven.  
         [0058]    As shown in FIG. 4, the flip-flops  211 _ 1 ,  211 _ 2 , . . . , and  211   —   m  each include an analog switch  2111 , an inverter  2112 , an analog switch  2113 , inverters  2114  and  2115 , and an analog switch  2116 , an inverter  2117 , and an analog switch  2118 .  
         [0059]    A signal fed into the flip-flop  211   —   p  is fed through the analog switch  2111  to the inverter  2112 . The output of the inverter  2112  is fed through the analog switch  2113  to the inverter  2114 , and is fed also to the inverter  2115 . The output of the inverter  2115  is fed through the analog switch  2116  to the inverter  2112 . The output of the inverter  2114  is used to drive the vertical scanning line L_p of the sensing portion  1 , and is fed to the inverter  2117 . The output of the inverter  2117  is fed through the analog switch  2118  to the inverter  2114 .  
         [0060]    In the flip-flops  211 _ 1 ,  211 _ 5 ,  211 _ 9 , . . . , the analog switch  2111  is turned ON and OFF by the vertical scanning signal φV 1 _ 1  so as to be ON when the vertical scanning signal φV1 — 1 is high and OFF when the vertical scanning signal φV1 — 1 is low.  
         [0061]    In the flip-flops  211 _ 1 ,  211 _ 5 ,  211 _ 9 , . . . , the analog switch  2116  is turned ON and OFF by the inverted signal φV1 — 1′ of the vertical scanning signal φV1 — 1 so as to be OFF when the vertical scanning signal φV1 — 1 is high and ON when the vertical scanning signal φV1 — 1 is low.  
         [0062]    In the flip-flops  211 _ 1 ,  211 _ 5 ,  211 _ 9 , . . . , the analog switch  2113  is turned ON and OFF by the vertical scanning signal φV2 — 1 so as to be ON when the vertical scanning signal φV2 — 1 is high and OFF when the vertical scanning signal φV2 — 1 is low.  
         [0063]    In the flip-flops  211 _ 1 ,  211 _ 5 ,  211 _ 9 , . . . , the analog switch  2118  is turned ON and OFF by the inverted signal φV2 — 1′ of the vertical scanning signal φV2 — 1 so as to be OFF when the vertical scanning signal φV2 — 1 is high and ON when the vertical scanning signal φV2 — 1 is low.  
         [0064]    In the flip-flops  211 _ 2 ,  211 _ 4 ,  211 _ 6 , . . . , the analog switch  2111  is turned ON and OFF by the vertical scanning signal φV1 — 2 so as to be ON when the vertical scanning signal φV1 — 2 is high and OFF when the vertical scanning signal φV1 — 2 is low.  
         [0065]    In the flip-flops  211 _ 2 ,  211 _ 4 ,  211 _ 6 , . . . , the analog switch  2116  is turned ON and OFF by the inverted signal φV1 — 2′ of the vertical scanning signal φV1 — 2 so as to be OFF when the vertical scanning signal φV1 — 2 is high and ON when the vertical scanning signal φV1 — 2 is low.  
         [0066]    In the flip-flops  211 _ 2 ,  211 _ 4 ,  211 _ 6 , . . . , the analog switch  2113  is turned ON and OFF by the vertical scanning signal φV2 — 2 so as to be ON when the vertical scanning signal φV2 — 2 is high and OFF when the vertical scanning signal φV2 — 2 is low.  
         [0067]    In the flip-flops  211 _ 2 ,  211 _ 4 ,  211 _ 6 , . . . , the analog switch  2118  is turned ON and OFF by the inverted signal φV2 — 2′ of the vertical scanning signal φV2 — 2 so as to be OFF when the vertical scanning signal φV2 — 2 is high and ON when the vertical scanning signal φV2 — 2 is low.  
         [0068]    In the flip-flops  211 _ 3 ,  211 _ 7 ,  211 _ 11 , . . . , the analog switch  2111  is turned ON and OFF by the vertical scanning signal φV1 — 3 so as to be ON when the vertical scanning signal φV1 — 3 is high and OFF when the vertical scanning signal φV1 — 3 is low.  
         [0069]    In the flip-flops  211 _ 3 ,  211 _ 7 ,  211 _ 11 , . . . , the analog switch  2116  is turned ON and OFF by the inverted signal φV1 — 3′ of the vertical scanning signal φV1 — 3 so as to be OFF when the vertical scanning signal φV1 — 3 is high and ON when the vertical scanning signal φV1 — 3 is low.  
         [0070]    In the flip-flops  211 _ 3 ,  211 _ 7 ,  211 _ 11 , . . . , the analog switch  2113  is turned ON and OFF by the vertical scanning signal φV2 — 3 so as to be ON when the vertical scanning signal φV2 — 3 is high and OFF when the vertical scanning signal φV2 — 3 is low.  
         [0071]    In the flip-flops  211 _ 3 ,  211 _ 7 ,  211 _ 11 , . . . , the analog switch  2118  is turned ON and OFF by the inverted signal φV2 — 3′ of the vertical scanning signal φV2 — 3 so as to be OFF when the vertical scanning signal φV2 — 3 is high and ON when the vertical scanning signal φV2 — 3 is low.  
         [0072]    [0072]FIG. 5 shows the circuit configuration of the horizontal scanning circuit  3 _ 1 . As shown in FIG. 5, the horizontal scanning circuit  3 _ 1  has largely the same configuration as the vertical scanning circuit  2 _ 1 . One difference is that the vertical scanning start signal φVS and the vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, φV2 — 2, φV2 — 2, and φV2 — 3 used in the latter are here replaced with the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, φH2_ 1 , φH2 — 2, and φH2 — 3, respectively. The horizontal scanning lines C_q of the sensing portion  1  are driven with the outputs of the inverters  213   —   q  constituting the horizontal scanning circuit  3 _ 1 .  
         [0073]    Another difference is that, as shown in FIG. 6, the flip-flops  211 _ 1 ,  211 _ 2 , . . . , and  211   —   m  used in the horizontal scanning circuit  3 _ 1  lack the inverter  2115 , analog switch  2116 , inverter  2117 , and analog switch  2118  as compared with the flip-flops  211 _ 1 ,  211 _ 2 , . . . , and  211   —   m  used in the vertical scanning circuit  2 _ 1 . This is because the horizontal scanning signals have higher frequencies than the vertical scanning signals, and therefore the omission of the inverter  2115 , analog switch  2116 , inverter  2117 , and analog switch  2118  does not affect the operation required here.  
         [0074]    The timing generator  20  generates a vertical scanning start signal φVS, a first vertical scanning signal φV1, a second vertical scanning signal φV2, a horizontal scanning start signal φHS, a first horizontal scanning signal φH1, and a second horizontal scanning signal φH2 shown in a timing chart in FIG. 7. In FIG. 7, reference symbol VB represents a vertical blanking period, reference symbol HB represents a horizontal blanking period, and reference symbol DR represents a data readout period.  
         [0075]    In the vertical scanning start signal φVS, a pulse appears during the horizontal blanking period HB immediately following a vertical blanking period VB. In the first and second vertical scanning signals φV1and φV2, a pulse appears during each horizontal blanking period. The pulses that appear in the vertical scanning start signal φVS are low, and the pulses that appear in the first and second vertical scanning signals φV1and φV2are high.  
         [0076]    In the horizontal scanning start signal φHS, a pulse appears immediately before each horizontal blanking period HB ends. In the first and second horizontal scanning signals φH1 and φH2, pulses appear at predetermined time intervals all the time. Within a horizontal blanking period HB, one pulse appears in each of the first and second horizontal scanning signals φH1 an φH2 during the period after a pulse appears in the horizontal scanning start signal φHS until the end of that horizontal blanking period HB. The pulses that appear in the horizontal scanning start signal φHS are low, and the pulses that appear in the first and second horizontal scanning signals φH1 an φH2 are high.  
         [0077]    [0077]FIG. 8 shows the circuit configuration of the scan mode switcher  30 _ 1 . The scan mode switcher  30 _ 1  includes selectors  311 ,  312 ,  313 ,  314 ,  315 ,  316 ,  317 , and  318  and a control circuit  319 . The scan mode switcher  30 _ 1  receives the first vertical scanning signal φV1, second vertical scanning signal φV2, first horizontal scanning signal φH1, and second horizontal scanning signal φH2 output from the timing generator  20 .  
         [0078]    The selectors  311  and  312  choose and output one of the first vertical scanning signal φV1and a high-level direct-current voltage VDD, whichever the control circuit  319  instructs them to choose. The selectors  313  and  314  choose and output one of the second vertical scanning signal φV2and the high-level direct-current voltage VDD, whichever the control circuit  319  instructs them to choose.  
         [0079]    The selectors  315  and  316  choose and output one of the first horizontal scanning signal φH1 and the high-level direct-current voltage VDD, whichever the control circuit  319  instructs them to choose. The selectors  317  and  318  choose and output one of the second horizontal scanning signal φH2 and the high-level direct-current voltage VDD, whichever the control circuit  319  instructs them to choose.  
         [0080]    From the scan mode switcher  30 _ 1 , the first vertical scanning signal φV1is output as a vertical scanning signal φV1 — 1, the signal output from the selector  311  is output as a vertical scanning signal φV1 — 2, the signal output from the selector  312  is output as a vertical scanning signal φV1 — 3, the second vertical scanning signal φV2 is output as a vertical scanning signal φV2 — 1, the signal output from the selector  313  is output as a vertical scanning signal φV2 — 2, the signal output from the selector  314  is output as a vertical scanning signal φV2 — 3.  
         [0081]    From the scan mode switcher  30 _ 1 , the first horizontal scanning signal φH1 is output as a horizontal scanning signal φH1 — 1, the signal output from the selector  315  is output as a horizontal scanning signal φH1 — 2, the signal output from the selector  316  is output as a horizontal scanning signal φH1 — 3, the second horizontal scanning signal φH2 is output as a horizontal scanning signal φH2 — 1, the signal output from the selector  317  is output as a horizontal scanning signal φH2 — 2, the signal output from the selector  318  is output as a horizontal scanning signal φH2 — 3.  
         [0082]    When a first scan mode is requested by a scan mode select signal, the control circuit  319  controls the selectors  311 ,  312 ,  313 ,  314 ,  315 ,  316 ,  317 , and  318  in such a way that the selectors  311  and  312  choose the first vertical scanning signal φV1, that the selectors  313  and  314  choose the second vertical scanning signal φV2, that the selectors  315  and  316  choose the first horizontal scanning signal φH1, and that the selectors  317  and  318  choose the second horizontal scanning signal φH2. The control circuit  319  also generates and outputs signals CNT 1 , CNT 2 , and CNT 3 . When the first scan mode is requested by the scan mode select signal, the control circuit  319  turns the signals CNT 1 , CNT 2 , and CNT 3  high.  
         [0083]    When a second scan mode is requested by the scan mode select signal, the control circuit  319  controls the selectors  311 ,  312 ,  313 ,  314 ,  315 ,  316 ,  317 , and  318  in such a way that the selector  311  chooses the high-level direct-current voltage VDD, that the selector  312  chooses the first vertical scanning signal φV1, that the selector  313  chooses the high-level direct-current voltage VDD, that the selector  314  chooses second vertical scanning signal φV2, that the selector  315  chooses the high-level direct-current voltage VDD, that the selector  316  chooses the first horizontal scanning signal φH1, that the selector  317  chooses the high-level direct-current voltage VDD, and that the selector  318  chooses the second horizontal scanning signal φH2. Moreover, when the second scan mode is requested by the scan mode select signal, the control circuit  319  turns the signal CNT 1  high, the signal CNT 2  low, and the signal CNT 3  high.  
         [0084]    When a third scan mode is requested by the scan mode select signal, the control circuit  319  controls the selectors  311 ,  312 ,  313 ,  314 ,  315 ,  316 ,  317 , and  318  in such a way that the selectors  311 ,  312 ,  313 ,  314 ,  315 ,  316 ,  317 , and  318  choose the high-level direct-current voltage VDD. Moreover, when the third scan mode is requested by the scan mode select signal, the control circuit  319  turns the signal CNT 1  high and the signals CNT 2  and CNT 3  low.  
         [0085]    With the individual circuit blocks configured as described above, in the first scan mode, the vertical scanning start signal φVS and the vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, φV2 — 1, φV2 — 2, and φV2 — 3 behave as shown in a timing chart in FIG. 9A. Thus, the pixels of all the rows of the sensing portion  1  are scanned progressively, starting with the first row. On the other hand, the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, φH2 — 1, φH2 — 2, and φH2 13  3 behave as shown in a timing chart in FIG. 10A. Thus, the pixels of all the columns of the sensing portion  1  are scanned progressively, starting with the first column. As a result, in the first scan mode, the data of all the pixels of the sensing portion  1  are read out.  
         [0086]    In the second scan mode, the vertical scanning start signal φVS and the vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, φV2 — 1, φV2 — 2, and φV2 — 3 behave as shown in a timing chart in FIG. 9B. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first row, then those in the third row, then those in the fifth row, and so forth. On the other hand, the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, φH2 — 1, φH2 — 2, and φH2 — 3 behave as shown in a timing chart in FIG. 10B. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first column, then those in the third column, then those in the fifth column, and so forth. As a result, in the second scan mode, the data of the pixels that are located simultaneously in the odd-numbered rows and in the odd-numbered columns of the sensing portion  1  are read out.  
         [0087]    In the third scan mode, the vertical scanning start signal φVS and the vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, φV2 — 1, φV2 — 2, and φV2 — 3 behave as shown in a timing chart in FIG. 9C. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first row, then those in the fifth row, then those in the ninth row, and so forth. On the other hand, the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, φH2 — 1, φH2 — 2, and φH2 — 3 behave as shown in a timing chart in FIG. 10C. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first column, then those in the fifth column, then those in the ninth column, and so forth. As a result, in the third scan mode, the data of the pixels that are located simultaneously in the (4X−3)th rows and in the (4Y−3)th columns of the sensing portion  1  are read out. Here, X and Y each represent a positive integral number.  
         [0088]    In this way, in the first embodiment, interlaced scanning is possible. The scanning circuit is composed of G latch type flip-flops, and, for these flip-flops, a plurality of lines through which to feed them with strobe signals (signals that make them take in data) so that each flip-flop is fed with a strobe signal through one of those lines that corresponds to that flip-flop. Thus, by applying scanning pulses to the lines through which strobe signals are fed to the flip-flops corresponding to the pixels that need to be scanned, and by applying, instead of scanning pluses, a direct-current voltage, i.e., a always active signal, to the lines through which strobe signals are fed to the flip-flops corresponding to the pixels that do not need to be scanned, it is possible to perform interlaced scanning. In addition, interlaced scanning can be performed at the same scanning rate as when all photoelectric conversion elements are scanned without increasing the frequency of scanning pulses than when all photoelectric conversion elements are scanned.  
         [0089]    [0089]FIG. 11 is a block diagram of another image-sensing apparatus incorporating a scanning circuit according to the invention. In FIG. 11, reference numeral  10 _ 2  represents an X-Y address area sensor, reference numeral  20  represents a timing generator, and reference numeral  30 _ 2  represents a scan mode switcher. The timing generator  20  here is the same as in the first embodiment, and therefore its descriptions will not be repeated.  
         [0090]    [0090]FIG. 12 is a block diagram of the X-Y address area sensor  10 _ 2 . As shown in FIG. 12, the X-Y address area sensor  10 _ 2  includes a sensing portion  1 , a vertical scanning circuit  2 _ 2  for vertically scanning the sensing portion  1 , and a horizontal scanning circuit  3 _ 2  for horizontally scanning the sensing portion  1 . The sensing portion  1  here is the same as in the first embodiment, and therefore its descriptions will not be repeated.  
         [0091]    The vertical scanning circuit  2 _ 2  receives a vertical scanning start signal φVS, a first vertical scanning signal φV1, and a second vertical scanning signal φV2 from the timing generator  20 , and receives signals SEL_A, SEL_B, SEL — 1, SEL_ 2 , and SEL_ 3  from the scan mode switcher  30 _ 2 .  
         [0092]    The horizontal scanning circuit  3 _ 2  receives a horizontal scanning start signal φHS, a first horizontal scanning signal φH1, and a second horizontal scanning signal φH2 from the timing generator  20 , and receives signals SEL_A, SEL_B, SEL — 1, SEL_ 2 , and SEL_ 3  from the scan mode switcher  30 _ 2 .  
         [0093]    [0093]FIG. 13 shows the circuit configuration of the vertical scanning circuit  2 _ 2 . In FIG. 13, reference numerals  221 _ 1 ,  221 _ 2 , . . . ,  222 _ 1 ,  222 _ 2 , . . .  223 _ 1 ,  223 _ 2 , . . . represent flip-flops, reference numerals  224 _ 1 ,  224 _ 2 , . . . represent selectors each having four input terminals, and reference numerals  225 _ 1 ,  225 _ 2 , and  225 _ 3  represent selectors each having two input terminals.  
         [0094]    The flip-flops  221 _ 1 ,  221 _ 2 , . . . are connected in series to form a shift register. The flip-flops  222 _ 1 ,  222 _ 2 , . . . are connected in series to form a shift register. The flip-flops  223 _ 1 ,  223 _ 2 , . . . are connected in series to form a shift register.  
         [0095]    The flip-flops  221 _ 1 ,  221 _ 2 , . . . are all G latch type flip-flops, and each include, as shown in FIG. 14, an analog switch  2211 , inverters  2212 ,  2213 , and  2214 , an analog switch  2215 , and a NAND gate  2216 . In the flip-flop  221 _ 1 , the signal output from the selector  225 _ 1  is fed through the analog switch  2211  to the inverter  2212 . In the flip-flops  221   —   p  other than the flip-flop  221 _ 1 , the output of the inverter  2213  of the flip-flop  221 _(p−1) is fed through the analog switch  2211  to the inverter  2212 . The output of the inverter  2212  is fed to the inverter  2213 . The output of the inverter  2213  is fed to the inverter  2214 , and is also fed through the analog switch  2215  to the inverter  2212 .  
         [0096]    Let k be a positive integral number. Then, in the flip-flop  211 _( 2   k −1), the analog switch  2211  is turned ON and OFF by the first vertical scanning signal φV1 and the analog switch  2215  is turned ON and OFF by the inverted signal φV1′ of the first vertical scanning signal φV1 in such a way that the analog switches  2211  and  2215  are, when the first vertical scanning signal φV1 is high, ON and OFF, respectively, and, when the first vertical scanning signal φV1 is low, OFF and ON, respectively.  
         [0097]    On the other hand, in the flip-flop  211 _ 2   k , the analog switch  2211  is turned ON and OFF by the second vertical scanning signal φV2 and the analog switch  2215  is turned ON and OFF by the inverted signal φV2′ of the second vertical scanning signal φV2 in such a way that the analog switches  2211  and  2215  are, when the second vertical scanning signal φV2 is high, ON and OFF, respectively, and, when the second vertical scanning signal φV2 is low, OFF and ON, respectively.  
         [0098]    In the flip-flop  221 _ 1 , the NAND gate  2216  receives at one input terminal thereof the output of the inverter  2214 , and receives at the other input terminal thereof the inverted signal φVSR0 of the vertical scanning start signal φVS. In the flip-flops  221   —   p  other than the flip-flop  221 _ 1 , the NAND gate  2216  receives at one input terminal thereof the output of the inverter  2214 , and receives at the other input terminal thereof the output of the inverter  2214  of the flip-flop  221 _(p−1).  
         [0099]    The flip-flops  222 _ 1 ,  222 _ 2 , . . . and the flip-flops  223 _ 1 ,  223 _ 1 , . . . are configured largely in the same manner as the flip-flops  221 _ 1 ,  221 _ 2 , . . . . Only differences are that, in the flip-flop  222 _ 1 , the signal output from the selector  225 _ 2  is fed through the analog switch  2211  to the inverter  2212  and that, in the flip-flop  223 _ 1 , the signal output from the selector  225 _ 3  is fed through the analog switch  2211  to the inverter  2212 .  
         [0100]    The selectors  224 _ 1 ,  224 _ 5 ,  224 _ 9 , . . . , i.e., the selectors  224 _( 4   k− 3), each receive at the first input terminal thereof the output of the NAND gate  2216  of the flip-flop  221 _( 4   k −3), receive at the second input terminal thereof the output of the NAND gate  2216  of the flip-flop  222 _( 2   k −1), receive at the third input terminal thereof the output of the NAND gate  2216  of the flip-flop  223   —   k , and receive at the fourth input terminal thereof a high-level direct-current voltage VDD.  
         [0101]    The selectors  224 _ 2 ,  224 _ 4 ,  224 _ 6 , . . . , i.e., the selectors  224 _ 2   k , each receive at the first input terminal thereof the output of the NAND gate  2216  of the flip-flop  221 _ 2   k , and receive at the second, third, and fourth input terminals thereof the high-level direct-current voltage VDD.  
         [0102]    The selectors  224 _ 3 ,  224 _ 7 ,  224 _ 1   1 , i.e., the selectors  224 _( 4   k −1), each receive at the first input terminal thereof the output of the NAND gate  2216  of the flip-flop  221 _( 4   k −1), receive at the second input terminal thereof the output of the NAND gate  2216  of the flip-flop  222 _ 2   k , and receive at the third and fourth input terminals thereof the high-level direct-current voltage VDD.  
         [0103]    The selector  224   —   p  selects and outputs one of the four inputs thereto according to the signals SEL_A and SEL_B. Superficially, the selector  224   —   p  outputs the signal fed to the first input terminal thereto when the signals SEL_A and SEL_B are both low, outputs the signal fed to the second input terminal thereto when the signal SEL_A is high and the signal SEL_B is low, outputs the signal fed to the third input terminal thereto when the signal SEL_A is low and the signal SEL_B is high, and outputs the signal fed to the fourth input terminal thereto when the signals SEL_A and SEL_B are both high. With the outputs of the selector  224   —   p , the vertical scanning line L_p of the sensing portion  1  is driven.  
         [0104]    The selectors  225 _ 1 ,  225 _ 2 , and  225 _ 3  each receive at the first input terminal thereof the vertical scanning start signal φVS, and receive at the second input terminal thereof the high-level direct-current voltage VDD. The selectors  225 _ 1 ,  225 _ 2 , and  225 _ 3  each choose and output one of the two inputs thereto according to the signals SEL_ 1 , SEL_ 2 , and SEL_ 3 . Specifically, the selectors  225 _ 1 ,  225 _ 2 , and  225 _ 3  each output the signal fed to the first input terminal thereof, i.e., the vertical scanning start signal φVS, when the corresponding one of the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  is high, and output the signal fed to the second input terminal thereof, i.e., the high-level direct-current voltage VDD, when the corresponding one of the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  is low.  
         [0105]    [0105]FIG. 15 shows the circuit configuration of the horizontal scanning circuit  3 _ 2 . As shown in FIG. 15, the horizontal scanning circuit  3 _ 2  has largely the same configuration as the vertical scanning circuit  2 _ 2 . One difference is that the vertical scanning start signal φVS and the first and second vertical scanning signals φV1 and φV2 used in the latter are here replaced with the horizontal scanning start signal φHS and the first and second horizontal scanning signals φH1 and φH2. The horizontal scanning lines C_q of the sensing portion  1  are driven with the outputs of the selectors  224 _q constituting the horizontal scanning circuit  3 _ 2 .  
         [0106]    Another difference is that, as shown in FIG. 16, the flip-flops  221 _ 1 ,  221 _ 2 , . . . ,  222 _ 1 ,  222 _ 2 , . . .  223 _ 1 ,  223 _ 2 , . . . used in the horizontal scanning circuit  3 _ 2  lack the analog switch  2215  as compared with the flip-flops  221 _ 1 ,  221 _ 2 , . . . ,  222 _ 1 ,  222 _ 2 , . . . ,  223 _ 1 ,  223 _ 2 , . . . used in the vertical scanning circuit  2 _ 2 . This is because the horizontal scanning signals have higher frequencies than the vertical scanning signals, and therefore the omission of the analog switch  2215  does not affect the operation required here.  
         [0107]    [0107]FIG. 17 shows the circuit configuration of the scan mode switcher  30 _ 2 . The scan mode switcher  30 _ 2  includes selectors  321 ,  322 ,  323 ,  324 , and  325  and a control circuit  326 . The selectors  321 ,  322 ,  323 ,  324 , and  325  each choose and output one of the high-level direct-current voltage VDD and a low-level direct-current voltage VSS according to the signals from the control circuit  326 .  
         [0108]    From the scan mode switcher  30 _ 2 , the signal output from the selector  321  is output as a signal SEL_A, the signal output from the selector  322  is output as a signal SEL_B, the signal output from the selector  323  is output as a signal SEL_ 1 , the signal output from the selector  324  is output as a signal SEL_ 2 , and the signal output from the selector  325  is output as a signal SEL_ 3 .  
         [0109]    When a first scan mode is requested by a scan mode select signal, the control circuit  326  controls the selectors  321 ,  322 ,  323 ,  324 , and  325  in such a way that the selectors  321  and  322  choose the low-level direct-current voltage VSS, that the selector  323  chooses the high-level direct-current voltage VDD, and that the selectors  324  and  325  choose the low-level direct-current voltage VSS.  
         [0110]    When a second scan mode is requested by the scan mode select signal, the control circuit  326  controls the selectors  321 ,  322 ,  323 ,  324 , and  325  in such a way that the selector  321  chooses the high-level direct-current voltage VDD, that the selector  322  chooses the low-level direct-current voltage VSS, that the selector  323  chooses the low-level direct-current voltage VSS, that the selector  324  chooses the high-level direct-current voltage VDD, and that the selector  325  chooses the low-level direct-current voltage VSS.  
         [0111]    When a third scan mode is requested by the scan mode select signal, the control circuit  326  controls the selectors  321 ,  322 ,  323 ,  324 , and  325  in such a way that the selector  321  chooses the low-level direct-current voltage VSS, that the selector  322  chooses the high-level direct-current voltage VDD, that the selectors  323  and  324  choose the low-level direct-current voltage VSS, and that the selector  325  chooses the high-level direct-current voltage VDD.  
         [0112]    With the individual circuit blocks configured as described above, in the first scan mode, the drive signals for the vertical scanning lines L_ 1 , L_ 2 , . . . of the sensing portion  1  behave with respect to the vertical scanning start signal φVS and the first and second vertical scanning signals φV1 and φV2 as shown in a timing chart in FIG. 18A. Thus, the pixels of all the rows of the sensing portion  1  are scanned progressively, starting with the first row. On the other hand, the horizontal scanning start signal φHS and the first and second horizontal scanning signals φH1 and φH2 behave as shown in a timing chart in FIG. 19A. Thus, the pixels of all the columns of the sensing portion  1  are scanned progressively, starting with the first column. As a result, in the first scan mode, the data of all the pixels of the sensing portion  1  are read out.  
         [0113]    In the second scan mode, the drive signals for the vertical scanning lines L_ 1 , L_ 2 , . . . of the sensing portion  1  behave with respect to the vertical scanning start signal φVS and the first and second vertical scanning signals φV1 and φV2 as shown in a timing chart in FIG. 18B. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first row, then those in the third row, then those in the fifth row, and so forth. On the other hand, the horizontal scanning start signal φHS and the first and second horizontal scanning signals φH1 and φH2 behave as shown in a timing chart in FIG. 19B. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first column, then those in the third column, then those in the fifth column, and so forth. As a result, in the second scan mode, the data of the pixels that are located simultaneously in the odd-numbered rows and in the odd-numbered columns of the sensing portion  1  are read out.  
         [0114]    In the third scan mode, the drive signals for the vertical scanning lines L_ 1 , L_ 2 , . . . of the sensing portion  1  behave with respect to the vertical scanning start signal φVS and the first and second vertical scanning signals φV1 and φV2 as shown in a timing chart in FIG. 18C. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first row, then those in the fifth row, then those in the ninth row, and so forth. On the other hand, the horizontal scanning start signal φHS and the first and second horizontal scanning signals φH1 and φH2 behave as shown in a timing chart in FIG. 19C. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first column, then those in the fifth column, then those in the ninth column, and so forth. As a result, in the third scan mode, the data of the pixels that are located simultaneously in the (4X−3)th rows and in the (4Y−3)th columns of the sensing portion  1  are read out. Here, X and Y each represent a positive integral number.  
         [0115]    In this way, in the second embodiment, interlaced scanning is possible. Here, interlaced scanning is achieved by providing a plurality of shift registers having different numbers of stages and performing scanning by the use of one selected from among those shift registers. Thus, interlaced scanning can be performed at the same scanning rate as when all photoelectric conversion elements are scanned without increasing the frequency of scanning pulses than when all photoelectric conversion elements are scanned. In addition, in the second embodiment, twice the frame rate achieved in the first embodiment is achieved with scanning pulses having the same frequency. In other words, in the second embodiment, the same frame rate as in the first embodiment is achieved with scanning pulses having half the frequency of those used in the first embodiment.  
         [0116]    [0116]FIG. 20 is a block diagram of still another image-sensing apparatus incorporating a scanning circuit according to the invention. In FIG. 20, reference numeral  10 _ 3  represents an X-Y address area sensor, reference numeral  20  represents a timing generator, and reference numeral  30 _ 3  represents a scan mode switcher. The timing generator  20  here is the same as in the first embodiment, and therefore its descriptions will not be repeated.  
         [0117]    [0117]FIG. 21 is a block diagram of the X-Y address area sensor  10 _ 3 . As shown in FIG. 21, the X-Y address area sensor  10 _ 3  includes a sensing portion  1 , a vertical scanning circuit  2 _ 2  for vertically scanning the sensing portion  1 , and a horizontal scanning circuit  3 _ 2  for horizontally scanning the sensing portion  1 . The sensing portion  1  here is the same as in the first embodiment, and therefore its descriptions will not be repeated.  
         [0118]    The vertical scanning circuit  2 _ 3  receives a vertical scanning start signal φVS from the timing generator  20 , and receives four vertical scanning signals φV1 — 1, φV1 — 2, φV — 3, and φV2 — 1 and signals SEL_ 1 , SEL_ 2 , and SEL_ 3  from the scan mode switcher  30 _ 3 .  
         [0119]    The horizontal scanning circuit  3 _ 3  receives a horizontal scanning start signal φHS from the timing generator  20 , and receives four horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, and φH2 — 1 and signals SEL_ 1 , SEL_ 2 , and SEL_ 3  from the scan mode switcher  30 _ 3 .  
         [0120]    [0120]FIG. 22 shows the circuit configuration of the vertical scanning circuit  2 _ 3 . In FIG. 22, reference numerals  231 _ 1 ,  231 _ 2 , . . . represent flip-flops, reference numerals  232 _ 1 ,  232 _ 2 , . . . represent inverters, reference numerals  233 _ 1 ,  233 _ 2 , . . . ,  234 _ 1 ,  234 _ 2 , . . . ,  235 _ 1 ,  235 _ 2 , . . . represent AND gates, reference numerals  236 _ 1 ,  236 _ 2 , . . . ,  237 _ 1 ,  237 _ 2 , . . .  238 _ 1 ,  238 _ 2  . . . represent analog switches, and reference numerals  239 _ 1 ,  239 _ 2 , . . . represent inverters.  
         [0121]    The flip-flops  231 _ 1 ,  231 _ 2 , . . . are all G latch type flip-flops. The flip-flops  231 _ 1 ,  231 _ 2 , . . . are connected in series to form a shift register.  
         [0122]    The flip-flop  231 _ 1  receives the vertical scanning start signal φVS. The flip-flops  231   —   p  other than the flip-flop  231 _ 1  each receive the output of the flip-flop  231 _(p−1). The output of the flip-flop  231   —   p  is fed to the inverter  232   —   p.    
         [0123]    The AND gates  233 _ 1 ,  234 _ 1 , and  235 _ 1  each receive at one input terminal thereof the inverted signal φVSR0 of the vertical scanning start signal φVS, and receive at the other input terminal thereof the output of the inviter  232 _ 1 . The AND gates  233   —   p  other than the AND gate  233 _ 1  each receive at one input terminal thereof the output of the inverter  232 _(p−1), and receive at the other input terminal thereof the output of the inverter  232   —   p.    
         [0124]    Let k be a positive integral number. Then, the AND gates  234 _( 4   k −3) other than the AND gate  234 _ 1  each receive at one input terminal thereof the output of the inverter  232 _( 4   k −5), and receive at the other input terminal thereof the output of the inverter  232 _( 4   k −3). The AND gates  235 _( 4   k −3) other than the AND gate  235 _ 1  each receive at one input terminal thereof the output of the inverter  232 _( 4   k −7), and receive at the other input terminal thereof the output of the inverter  232 _( 4   k −3).  
         [0125]    The AND gates  234 _ 2   k  and  235 _ 2   k  each receive at one input terminal thereof a low-level direct-current voltage VSS, and receive at the other input terminal thereof the output of the inverter  232 _ 2   k.    
         [0126]    The AND gate  234 _( 4   k −1) receives at one input terminal thereof the output of the inverter  232 _( 4   k −3), and receives at the other input terminal thereof the output of the inverter  232 _( 4   k −1). The AND gate  235 _( 4   k −1) receives at one input terminal thereof the low-level direct-current voltage VSS, and receives at the other input terminal thereof the output of the inverter  232 _( 4   k −1).  
         [0127]    The outputs of the AND gates  233   —   p ,  234   —   p , and  235   —   p  are fed, respectively through the analog switches  236   —   p ,  237   —   p , and  238   —   p , commonly to the inverter  239   —   p . With the output of the inverter  239   —   p , the vertical scanning line L —   p  of the sensing portion  1  is driven.  
         [0128]    The analog switches  236   —   p ,  237   —   p , and  238   —   p  are turned ON and OFF by the signals SEL_ 1 , SEL_ 2 , and SEL_ 3 , respectively. Specifically, when the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are high, the analog switches  236   —   p ,  237   —   p , and  238   —   p , respectively, are ON, and, when the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are low, the analog switches  236   —   p ,  237   —   p , and  238   —   p , respectively, are OFF.  
         [0129]    As shown in FIG. 23, the flip-flops  231   —   p  each include an analog switch  2311 , inverters  2312  and  2313 , and an analog switch  2314 . A signal fed into the flip-flop  231   —   p  is fed through the analog switch  2311  to the inverter  2312 . The output of the inverter  2312  is fed to the inverter  2313 . The output of the inverter  2313  is fed through the analog switch  2314  to the inverter  2312 . The output of the inverter  2313  is used as the output of the flip-flop  231   —   p.    
         [0130]    In the flip-flop  231 _( 8   k −1), the analog switch  2311  is turned ON and OFF by the vertical scanning signal φV1 — 1 and the analog switch  2314  is turned ON and OFF by the inverted signal φV1 — 1′ of the vertical scanning signal φV1 — 1 in such a way that, the analog switches  2311  and  2314  are, when the vertical scanning signal φV1 — 1 is high, ON and OFF, respectively, and, when the vertical scanning signal φV1 — 1 is low, OFF and ON, respectively.  
         [0131]    In the flip-flop  231 _( 4   k −1), the analog switch  2311  is turned ON and OFF by the vertical scanning signal φV1 — 2 and the analog switch  2314  is turned ON and OFF by the inverted signal φV1 — 2′ of the vertical scanning signal φV1 — 2 in such a way that the analog switches  2311  and  2314  are, when the vertical scanning signal φV1 — 2 is high, ON and OFF, respectively, and, when the vertical scanning signal φV1_ 2  is low, OFF and ON, respectively.  
         [0132]    In the flip-flop  231 _( 8   k −3), the analog switch  2311  is turned ON and OFF by the vertical scanning signal φV1 — 3 and the analog switch  2314  is turned ON and OFF by the inverted signal φV1 — 3′ of the vertical scanning signal φV1 — 3 in such a way that the analog switches  2311  and  2314  are, when the vertical scanning signal φV1 — 3 is high, ON and OFF, respectively, and, when the vertical scanning signal φV1 — 3 is low, OFF and ON, respectively.  
         [0133]    In the flip-flop  231 _ 2   k , the analog switch  2311  is turned ON and OFF by the vertical scanning signal φV2 — 1 and the analog switch  2314  is turned ON and OFF by the inverted signal φV2 — 1′ of the vertical scanning signal φV2 — 1 in such a way that the analog switches  2311  and  2314  are, when the vertical scanning signal φV2 — 1 is high, ON and OFF, respectively, and, when the vertical scanning signal φV2 — 1 is low, OFF and ON, respectively.  
         [0134]    [0134]FIG. 24 shows the circuit configuration of the horizontal scanning circuit  3 _ 3 . As shown in FIG. 24, the horizontal scanning circuit  3 _ 3  has largely the same configuration as the vertical scanning circuit  2 _ 3 . One difference is that the vertical scanning start signal φVS and the vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, and φV21 used in the latter are here replaced with the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, and φH2 — 1, respectively. The horizontal scanning lines C_q of the sensing portion  1  are driven with the outputs of the inverters  239   —   q  constituting the horizontal scanning circuit  3 _ 3 .  
         [0135]    Another difference is that, as shown in FIG. 25, the flip-flops  231 _ 1 ,  231 _ 2 , . . . , and  231   —   m  used in the horizontal scanning circuit  3 _ 3  lack the analog switch  2314  as compared with the flip-flops  231 _ 1 ,  231 _ 2 , and  231   —   m  used in the vertical scanning circuit  2 _ 3 . This is because the horizontal scanning signals have higher frequencies than the vertical scanning signals, and therefore the omission of the analog switch  2314  does not affect the operation required here.  
         [0136]    [0136]FIG. 26 shows the circuit configuration of the scan mode switcher  30 _ 3 . The scan mode switcher  30 _ 3  includes selectors  331 ,  332 ,  333 ,  334 ,  335 , and  336  and a control circuit  337 . The scan mode switcher  30 _ 3  receives a first vertical scanning signal φV1, a second vertical scanning signal φV2, a first horizontal scanning signal φH1, a second horizontal scanning signal φH2, and a high-level direct-current voltage VDD, all output from the timing generator  20 .  
         [0137]    The selector  331  chooses and outputs one of the first vertical scanning signal φV1, the second vertical scanning signal φV2, and the high-level direct-current voltage VDD, whichever the control circuit  337  instructs it to select. The selector  332  chooses and outputs one of the first vertical scanning signal φV1and the second vertical scanning signal φV2, whichever the control circuit  337  instructs it to select. The selector  333  chooses and outputs one of the second vertical scanning signal φV2and the high-level direct-current voltage VDD, whichever the control circuit  337  instructs it to select.  
         [0138]    The selector  334  chooses and outputs one of the first horizontal scanning signal φH1, the second horizontal scanning signal φH2, and the high-level direct-current voltage VDD, whichever the control circuit  337  instructs it to select. The selector  335  chooses and outputs one of the first horizontal scanning signal φH1 and the second horizontal scanning signal φH2, whichever the control circuit  337  instructs it to select. The selector  336  chooses and outputs one of the second horizontal scanning signal φH2 and the high-level direct-current voltage VDD, whichever the control circuit  337  instructs it to select.  
         [0139]    From the scan mode switcher  30 _ 3 , the first vertical scanning signal φV1 is output as a signal φV1 — 1, the signal output from the selector  331  is output as a signal φV1 — 2, the signal output from the selector  332  is output as a signal φV1 — 3, and the signal output from the selector  333  is output as a signal φV2 — 1.  
         [0140]    From the scan mode switcher  30 _ 3 , the first horizontal scanning signal φH1 is output as a signal φH1 — 1, the signal output from the selector  334  is output as a signal φH1 — 2, the signal output from the selector  335  is output as a signal φH1 — 3, and the signal output from the selector  336  is output as a signal φH2 — 1.  
         [0141]    When a first scan mode is requested by a scan mode select signal, the control circuit  337  controls the selectors  331 ,  332 ,  333 ,  334 ,  335 , and  336  in such a way that the selectors  331  and  332  choose the first vertical scanning signal φV1, that the selector  333  chooses the second vertical scanning signal φV2, that the selectors  334  and  335  choose the first horizontal scanning signal φH1, and that the selector  336  chooses the second horizontal scanning signal φH2. The control circuit  337  also generates and outputs signals SEL_ 1 , SEL_ 2 , and SEL_ 3 . When the first scan mode is requested by the scan mode select signal, the control circuit  337  turns the signal SEL_ 1  high and the signals SEL_ 2  and SEL_ 3  low.  
         [0142]    When a second scan mode is requested by the scan mode select signal, the control circuit  337  controls the selectors  331 ,  332 ,  333 ,  334 ,  335 , and  336  in such a way that the selector  331  chooses the second vertical scanning signal φV2, that the selector  332  chooses the first vertical scanning signal φV1, that the selector  333  chooses the high-level direct-current voltage VDD, that the selector  334  chooses the second horizontal scanning signal φH2, that the selector  335  chooses the first horizontal scanning signal φH1, and that the selector  336  chooses the high-level direct-current voltage VDD. Moreover, when the second scan mode is requested by the scan mode select signal, the control circuit  337  turns the signal SEL_ 1  low, the signal SEL_ 2  high, and the signal SEL_ 3  low.  
         [0143]    When a third scan mode is requested by the scan mode select signal, the control circuit  337  controls the selectors  331 ,  332 ,  333 ,  334 ,  335 , and  336  in such a way that the selector  331  chooses the high-level direct-current voltage VDD, that the selector  332  chooses the second vertical scanning signal φV2, that the selector  333  chooses the high-level direct-current voltage VDD, that the selector  334  chooses the high-level direct-current voltage VDD, that the selector  335  chooses the second horizontal scanning signal φH2, and that the selector  336  chooses the high-level direct-current voltage VDD. Moreover, when the third scan mode is requested by the scan mode select signal, the control circuit  337  turns the signals SEL_ 1  and SEL_ 2  low and the signal SEL_ 3  high.  
         [0144]    With the individual circuit blocks configured as described above, in the first scan mode, the vertical scanning start signal φVS and the vertical scanning signals φV1 — 1, φV1 — 2, φV1 — 3, and φV2 — 1 behave as shown in a timing chart in FIG. 27A. In addition, the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are high, low, and low, respectively. Thus, the pixels of all the rows of the sensing portion  1  are scanned progressively, starting with the first row. On the other hand, the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, and φH2_ 1  behave as shown in a timing chart in FIG. 28A. In addition, the signal SEL_ 1 , SEL_ 2 , and SEL_ 3  are high, low, and low, respectively. Thus, the pixels of all the columns of the sensing portion  1  are scanned progressively, starting with the first column. As a result, in the first scan mode, the data of all the pixels of the sensing portion  1  are read out.  
         [0145]    In the second scan mode, the vertical scanning start signal φVS and the vertical scanning signals φV — 1, φV1 — 2, φV1 — 3, and φV2 — 1 behave as shown in a timing chart in FIG. 27B. In addition, the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are low, high, and low, respectively. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first row, then those in the third row, then those in the fifth row, and so forth. On the other hand, the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, and φH2 — 1 behave as shown in a timing chart in FIG. 28B. In addition, the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are low, high, and low, respectively. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first column, then those in the third column, then those in the fifth column, and so forth. As a result, in the second scan mode, the data of the pixels that are located simultaneously in the odd-numbered rows and in the odd-numbered columns of the sensing portion  1  are read out.  
         [0146]    In the third scan mode, the vertical scanning start signal φVS and the vertical scanning signals φV1  — 1, φV1 — 2, φV1 — 3, and φV2 — 1 behave as shown in a timing chart in FIG. 27C. In addition, the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are low, low, and high, respectively. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first row, then those in the fifth row, then those in the ninth row, and so forth. On the other hand, the horizontal scanning start signal φHS and the horizontal scanning signals φH1 — 1, φH1 — 2, φH1 — 3, and φH2 — 1 behave as shown in a timing chart in FIG. 28C. In addition, the signals SEL_ 1 , SEL_ 2 , and SEL_ 3  are low, low, and high, respectively. Thus, the pixels of the sensing portion  1  are scanned in the following order: the pixels in the first column, then those in the fifth column, then those in the ninth column, and so forth. As a result, in the third scan mode, the data of the pixels that are located simultaneously in the (4X-3)th rows and in the (4Y-3)th columns of the sensing portion  1  are read out. Here, X and Y each represent a positive integral number.  
         [0147]    In this way, in the third embodiment, interlaced scanning is possible. The scanning circuit is composed of G latch type flip-flops, and, for these flip-flops, a plurality of lines through which to feed them with strobe signals (signals that make them take in data) so that each flip-flop is fed with a strobe signal through one of those lines that corresponds to that flip-flop. Thus, by applying scanning pulses to the lines through which strobe signals are fed to the flip-flops corresponding to the pixels that need to be scanned, and by applying, instead of scanning pluses, a direct-current voltage, i.e., a always active signal, to the lines through which strobe signals are fed to the flip-flops corresponding to the pixels that do not need to be scanned, it is possible to perform interlaced scanning. In addition, interlaced scanning can be performed at the same scanning rate as when all photoelectric conversion elements are scanned without increasing the frequency of scanning pulses than when all photoelectric conversion elements are scanned. Furthermore, in the third embodiment, twice the frame rate achieved in the first embodiment is achieved with scanning pulses having the same frequency. In other words, in the third embodiment, the same frame rate as in the first embodiment is achieved with scanning pulses having half the frequency of those used in the first embodiment.  
         [0148]    Now, how each pixel G(x, y) of the sensing portion  1  is configured in the embodiments described above will be described. FIG. 29 shows an example of the circuit configuration of the pixel G(x, y). Here, x and y each represent a positive integral number.  
         [0149]    A photodiode PD has its anode connected to ground GND, and has its cathode connected to the drain of a p-channel MOS transistor T 1 . The source of the transistor Ti is connected to the gate and drain of a p-channel MOS transistor T 2 , and to the gate of a p-channel MOS transistor T 3 . The gate of the transistor T 1  is driven by a signal φS1. The transistor T 2  receives a signal φVPS at its source.  
         [0150]    The source of the transistor T 3  is connected to the gate of a p-channel MOS transistor T 4 , to the source of a p-channel MOS transistor T 5 , and to one end of a capacitor C that receives at the other end a direct-current voltage VDD. The drain of the transistor T 3  is connected to ground GND.  
         [0151]    The source of the transistor T 4  is connected to the drain of a p-channel MOS transistor T 6 . The drain of the transistor T 4  is connected to ground GND. The gate of the transistor T 5  is driven by a signal φRST. The transistor T 5  receives at its drain a direct-current voltage RSB lower than but roughly equal to the direct-current voltage VDD. The source of the transistor T 6  is connected to a signal line _y. The gate of the transistor T 6  is connected to a vertical scanning line L_x.  
         [0152]    First, the operation of the pixel during image sensing will be described. It is to be noted that the following description deals with an example in which the image-sensing apparatus as a whole is set to operate in the mode in which the data of all the pixels are read out. During image sensing, the signal φS1 remains low, and thus the transistor T 1  remains ON. The signal φRST remains high, and thus the transistor T 5  remains OFF. The signal φVPS is a low direct-current voltage that makes the transistor T 2  operate in a subthreshold region.  
         [0153]    A current commensurate with the amount of incident light occurs in the photodiode PD, and, owing to the subthreshold characteristic of the MOS transistor, a voltage natural-logarithmically proportional to the photoelectric current appears at the gates of the transistors T 2  and T 3 . A current commensurate with this voltage flows through the capacitor C to the drain of the transistor T 3 , and thus the capacitor C is charged. Accordingly, the gate voltage of the transistor T 4  is natural-logarithmically proportional to the integral of the amount of light incident on the photodiode PD.  
         [0154]    When the signal φV_x that drives the vertical scanning line L_x turns low, the transistor T 6  turns ON and thereby causes the transistor T 4  to operate as a source follower. As a result, a voltage natural-logarithmically proportional to the integral of the amount of light incident on the photodiode PD appears on the signal line S_y.  
         [0155]    This example assumes that the pixels have integration capability and are of the logarithmic conversion type. However, the pixels may lack integration capability, and may be of any other type than the logarithmic conversion type.  
         [0156]    Next, the operation of the pixel during detection of pixel-to-pixel variations in sensitivity will be described with reference to a timing chart shown in FIG. 30. It is to be noted that the following description deals with an example in which the image-sensing apparatus as a whole is set to operate in the mode in which the data of all the pixels are read out. After the signal φV_x that drives the vertical scanning line L_x turns low and thus the data of the pixel is read out, first, the signal φS1 is turned high to turn the transistor T 1  OFF. This starts resetting.  
         [0157]    Now, positive electric charge starts flowing into the transistor T 2  through its source to recombine with the positive electric charge accumulated at the gate and drain of the transistor T 2  and at the gate of the transistor T 3 . Thus, the potential at the gate and drain of the transistor T 2  rises up to a certain level.  
         [0158]    However, when the potential at the gate and drain of the transistor T 2  has risen up to that certain level, resetting slows down. This tendency is particularly marked when a bright object has suddenly become dim. To overcome this, next, the signal φVPS fed to the source of the transistor T 2  is raised to a higher voltage than during image sensing. Raising the source voltage of the transistor T 2  in this way results in increasing the amount of positive electric charge that flows into the transistor T 2  through its source, and thus prompts the recombination therewith of the negative electric charge accumulated at the gate of the transistor T 3 .  
         [0159]    Accordingly, the potential at the gate and drain of the transistor T 2  rises further. Then, the signal φVPS fed to the source of the transistor T 2  is turned back to the low voltage it has during image sensing to bring the potential state of the transistor T 2  back to its original state. After the potential state of the transistor T 2  has been brought back to its original state in this way, first, a low-level pulse is fed as the signal φRST to transistor T 5  to turn it ON so that the voltage at the node between the capacitor C and the gate of the transistor T 4  is initialized.  
         [0160]    When the voltage at the node between the capacitor C and the gate of the transistor T 4  becomes commensurate with the gate voltage of the transistor T 2  thus reset, the signal φV_x that drives the vertical scanning line L_x is turned low to turn the transistor T 6  ON. This causes an output current that represents the pixel-to-pixel variation in sensitivity of this particular pixel to flow by way of the signal line S_y.  
         [0161]    At this time, the transistor T 4  operates as a source follower, and therefore the noise component appears as a voltage signal on the signal line S_y. Thereafter, a low-level pulse is fed again as the signal φRST to the transistor T 5  to turn it ON so that the voltage at the node between the capacitor C and the gate of the transistor T 4  is reset, and then the signal φS1 is turned low to turn the transistor T 1  ON, making the pixel ready to perform image sensing.  
         [0162]    In a case where pixel data are read out from every two-by-two unit of pixels, the signal φS1 is replaced with a signal φS4, which will be described later; in a case where pixel data are read out from every four-by-four unit of pixels, the signal φS1 is replaced with a signal φS16, which will be described later.  
         [0163]    [0163]FIG. 31 shows a first circuit configuration for interconnection between pixels. FIG. 31 shows 16 pixels extracted from the sensing portion  1  which form a four-by-four unit. In each pixel G( x, y ), the photodiode PD has its cathode connected to the drain of a p-channel MOS transistor T 7 ( x, y ).  
         [0164]    The sources of the transistors T 7 ( 2   x− 1,  2   y− 1), T 7 ( 2   x− 1,  2   y ), T 7 ( 2   x,    2   y− 1), and T 7 ( 2   x,    2   y ) are connected commonly to the drain of a p-channel MOS transistor T 8 ( x, y ). The gate of the transistor T 7 ( x, y ) is driven by a signal φA4. The source of the transistor T 8 ( x, y ) is connected to the node between the transistors T 1  and T 2  of the pixel G( 2   x− 1,  2   y -1). The gate of the transistor T 8 ( x, y ) is driven by a signal φS4.  
         [0165]    Moreover, the sources of the transistors T 7 ( 2   x− 1,  2   y− 1), T 7 ( 2   x− 1,  2   y ), T 7 ( 2   x,    2   y− 1), and T 7 ( 2   x,    2   y ) are connected commonly also to the drain of a p-channel MOS transistor T 9 ( x, y ). The sources of the transistors T 9 ( 2   x− 1,  2   y− 1), T 9 ( 2   x− 1,  2   y ), T 9 ( 2   x,    2   y− 1), and T 9 ( 2   x,    2   y ) are connected commonly to the drain of a p-channel MOS transistor T 10 ( x, y ). The gate of the transistor T 9 ( x, y ) is driven by a signal φA16. The source of the transistor T 10 ( x, y ) is connected to the node between the transistors T 1  and T 2  of the pixel G( 4   x− 3,  4   y− 3). The gate of the transistor T 10 ( x, y ) is driven by a signal φS16.  
         [0166]    In the first scan mode, i.e., when the data of all the pixels are read out, a signal φPDDA (a signal that turns high when the photodiode PD needs to be disabled) is used as the signal φS1, while the signals φS4, φS16, φA4, and φA16 are kept high. Accordingly, the transistors T 7 ( x, y ), T 8 ( x, y ), T 9 ( x, y ) and T 10 ( x, y ) are OFF all the time, and the transistor T 1  turns ON at readout. Thus, the photoelectric current occurring in each pixel G( x, y ) is read out pixel by pixel.  
         [0167]    In the second scan mode, i.e., when the data of the pixels that are located simultaneously in the odd-numbered rows and in the odd-numbered columns are read out, the signal φPDDA is used as the signal φS4, while the signals φS1, φS16, and φA16 are kept high, and the signal φA4 is kept low. Accordingly, the transistors T 1 , T 9 ( x, y ), and T 10 ( x, y ) are OFF all the time, the transistor T 7 ( x, y ) is ON all the time, and the transistor T 8 ( x, y ) turns ON at readout. Thus, the photoelectric currents occurring in four pixels (forming a two-by-two unit), namely G( 2   x− 1,  2   x− 1), G( 2   x− 1,  2   x ), G( 2   x,    2   x− 1), and G(  2   x,    2   x ), are added together in the pixel G( 2   x− 1,  2   x− 1), and the sum is read out.  
         [0168]    In the third scan mode, i.e., when the data of the pixels that are located simultaneously in the (4x-3)th rows and in the (4x-3)th columns are read out, the signal φPDDA is used as the signal φS16, while the signals φS1 and φS4 are kept high, and the signals φA4 and φA16 are kept low. Accordingly, the transistors T 1  and T 8 ( x, y ) are OFF all the time, the transistors T 7 ( x, y ) and T 9 ( x, y ) are ON all the time, and the transistor T 10 ( x, y ) turns ON at readout. Thus, the photoelectric currents occurring in 16 pixels (forming a four-by-four unit), namely G( 2   w− 1,  2   w− 1), G( 2   w− 1,  2   w ), G( 2   w− 1,  2   w+ 1), G( 2   w− 1,  2   w+ 2), G( 2   w,    2   w− 1), G( 2   w,    2   w ), G( 2   w,    2   w+ 1), G( 2   w,    2   w+ 2), G( 2   w+ 1,  2   w− 1), G( 2   w+ 1,  2   w ), G( 2   w+ 1,  2   w+ 1), G( 2   w+ 1,  2   w+ 2), G( 2   w+ 2,  2   w− 1), G( 2   w+ 2,  2   w ), G( 2   w+ 2,  2   w+ 1), and G( 2   w+ 2,  2   w+ 2), are added together in the pixel G( 2   w− 1,  2   w− 1), and the sum is read out. Here, w represents an odd number.  
         [0169]    [0169]FIG. 32 shows a second circuit configuration for interconnection between pixels. FIG. 32 shows 16 pixels extracted from the sensing portion  1  which form a four-by-four unit. In each pixel G( x, y ), the photodiode PD has its cathode connected to the drain of a p-channel MOS transistor T 11 ( x, y ) and to the drain of a p-channel MOS transistor T 12 ( x, y ).  
         [0170]    The sources ofthe transistors T 11 ( 2   x− 1,  2   y− 1), T 11 ( 2   x− 1,  2   y ), T 11 ( 2   x,    2   y− 1), and T 11 ( 2   x,    2   y ) are connected commonly to the node between the transistors T 1  and T 2  of the pixel G( 2   x− 1,  2   y− 1). The gate of the transistor T 11 ( x, y ) is driven by the signal φS4.  
         [0171]    The sources of the transistors T 12 ( 2   w− 1,  2   w− 1), T 12 ( 2   w− 1,  2   w ), T 12 ( 2   w− 1,  2   w+ 1), T 12 ( 2   w− 1,  2   w+ 2), T 12 ( 2   w,    2   w− 1), T 12 ( 2   w,    2   w ), T 12 ( 2   w,    2   w+ 1), T 12 ( 2   w,    2   w+ 2), T 12 ( 2   w+ 1,  2   w− 1), T 12 ( 2   w+ 1,  2   w ), T 12 ( 2   w+ 1,  2   w+ 1), T 12 ( 2   w+ 1,  2   w+ 2), T 12 ( 2   w+ 2,  2   w− 1), T 12 ( 2   w+ 2,  2   w ), T 12 ( 2   w+ 2,  2   w+ 1), T 12 ( 2   w+ 2,  2   w+ 2) are connected commonly to the node between the transistors T 1  and T 2  of the pixel G( 2   w− 1,  2   w− 1). The gate of the transistor T 12 ( x, y ) is driven by the signal φS16. Here, w represents an odd number.  
         [0172]    In the first scan mode, i.e., when the data of all the pixels are read out, a signal φPDDA (a signal that turns high when the photodiode PD needs to be disabled) is used as the signal φS1, while the signals φS4 and φS16 are kept high. Accordingly, the transistors T 11 ( x, y ) and T 12 ( x, y ) are OFF all the time, and the transistor T 1  turns ON at readout. Thus, the photoelectric current occurring in each pixel G( x, y ) is read out pixel by pixel.  
         [0173]    In the second scan mode, i.e., when the data of the pixels that are located simultaneously in the odd-numbered rows and in the odd-numbered columns are read out, the signal φPDDA is used as the signal φS4, while the signals φS1 and φS16 are kept high. Accordingly, the transistors T 1  and T 12 ( x, y ) are OFF all the time, and the transistor T 11 ( x, y ) turns ON at readout. Thus, the photoelectric currents occurring in four pixels (forming a two-by-two unit), namely G( 2   x− 1,  2   x− 1), G( 2   x− 1,  2   x ), G( 2   x,    2   x− 1), and G( 2   x,    2   x ), are added together in the pixel G( 2   x− 1,  2   x− 1), and the sum is read out.  
         [0174]    In the third scan mode, i.e., when the data of the pixels that are located simultaneously in the (4x-3)th rows and in the (4x-3)th columns are read out, the signal φPDDA is used as the signal φS16, while the signals φS1 and φS4 are kept high. Accordingly, the transistors T 1  and T 11 ( x, y ) are OFF all the time, and the transistor T 12 ( x, y ) turns ON at readout. Thus, the photoelectric currents occurring in 16 pixels (forming a four-by-four unit), namely G( 2   w− 1,  2   w− 1), G( 2   w− 1,  2   w ), G( 2   w− 1,  2   w+ 1), G( 2   w− 1,  2   w+ 2), G( 2   w,    2   w− 1), G( 2   w,    2   w ), G( 2   w,    2   w+ 1), G( 2   w,    2   w+ 2), G( 2   w+ 1,  2   w− 1), G( 2   w+ 1,  2   w ), G( 2   w+ 1,  2   w+ 1), G( 2   w+ 1,  2   w+ 2), G( 2   w+ 2,  2   w− 1), G( 2   w+ 2,  2   w ), G( 2   w+ 2,  2   w+ 1), and G( 2   w+ 2,  2   w+ 2), are added together in the pixel G( 2   w− 1,  2   w− 1), and the sum is read out. Here, w represents an odd number.  
         [0175]    [0175]FIG. 33 shows a third circuit configuration for interconnection between pixels. FIG. 33 shows 16 pixels extracted from the sensing portion  1  which form a four-by-four unit. In each pixel G( x, y ), the photodiode PD has its cathode connected to the drain of a p-channel MOS transistor T 13 ( x, y ) and to the drain of a p-channel MOS transistor T 14 ( x, y ). Moreover, in each pixel G( x, y ), the node between the transistors T 1  and T 2  is connected to the source of a p-channel MOS transistor T 15 ( x, y ) and to the source of a p-channel MOS transistor T 16 ( x, y ).  
         [0176]    The sources of the transistors T 13 ( 2   x− 1,  2   y− 1), T 13 ( 2   x− 1,  2   y ), T 13 ( 2   x,    2   y− 1), and T 13 ( 2   x,    2   y ) and the drains of the transistors T 15 ( 2   x− 1,  2   y− 1), T 15 ( 2   x− 1,  2   y ), T 15 ( 2   x,    2   y− 1), and T 15 ( 2   x,    2   y ) are connected together. The gate of the transistor T 13 ( x, y ) is driven by the signal φS4. The gate of the transistor T 15 ( 2   x− 1,  2   y− 1) is driven by a signal φB4. The transistors T 15 ( 2   x− 1,  2   y ), T 15 ( 2   x,    2   y− 1), and T 15 ( 2   x,    2   y ) receive at their gates the high-level direct-current voltage VDD, and thus the transistors T 15 ( 2   x− 1,  2   y ), T 15 ( 2   x,    2   y− 1), and T 15 ( 2   x,    2   y ) are OFF all the time irrespective of the selected scan mode.  
         [0177]    The sources of the transistors T 14 ( 2   w− 1,  2   w− 1), T 14 ( 2   w− 1,  2   w ), T 14 ( 2   w− 1,  2   w+ 1), T 14 ( 2   w− 1,  2   w+ 2), T 14 ( 2   w,    2   w− 1), T 14 ( 2   w,    2   w ), T 14 ( 2   w,  2 w+ 1), T 14 ( 2   w,    2   w+ 2), T 14 ( 2   w+ 1,  2   w− 1), T 14 ( 2   w+ 1,  2   w ), T 14 ( 2   w+ 1,  2   w+ 1), T 14 ( 2   w+ 1  2   w+ 2), T 14 ( 2   w+ 2,  2   w− 1), T 14 ( 2   w+ 2,  2   w ), T 14 ( 2   w+ 2,  2   w+ 1), T 14 ( 2   w+ 2,  2   w+ 2) and the drains of the transistors T 16 ( 2   w− 1,  2   w− 1), T 16 ( 2   w− 1,  2   w ), T 16 ( 2   w− 1,  2   w+ 1), T 16 ( 2   w− 1,  2   w+ 2), T 16 ( 2   w,    2   w− 1), T 16 ( 2   w,    2   w ), T 16 ( 2   w,    2   w+ 1), T 16 ( 2   w,    2   w+ 2), T 16 ( 2   w+ 1,  2   w− 1), T 16 ( 2   w+ 1,  2   w ), T 16 ( 2   w+ 1,  2   w+ 1), T 16 ( 2   w+ 1,  2   w+ 2), T 16 ( 2   w− 1) T 16 ( 2   w+ 2,  2   w ), T 16 ( 2   w+ 2,  2   w+ 1), T 16 ( 2   w+ 2,  2   w+ 2) are connected together. Here, w represents an odd number. The gate of the transistor T 14 ( x, y ) is driven by the signal φS16. The gate of the transistor T 16 (4x−3, 4y−3) is driven by a signal φB16. The transistors T 16 ( x, y ) other than the transistor T 16 (4x−3, 4y−3) receive at their gates the high-level direct-current voltage VDD, and thus the transistors T 16 ( x, y ) other than the transistor T 16 (4x−3, 4y−3) are OFF all the time irrespective of the selected scan mode.  
         [0178]    In the first scan mode, i.e., when the data of all the pixels are read out, a signal φPDDA (a signal that turns high when the photodiode PD needs to be disabled) is used as the signal φS1, while the signals φS4, φS16, φB4, and φB16 are kept high. Accordingly, the transistors T 13 ( x, y ), T 14 ( x, y ), T 15 ( x, y ) and T 16 ( x, y ) are OFF all the time, and the transistor T 1  turns ON at readout. Thus, the photoelectric current occurring in each pixel G( x, y ) is read out pixel by pixel.  
         [0179]    In the second scan mode, i.e., when the data of the pixels that are located simultaneously in the odd-numbered rows and in the odd-numbered columns are read out, the signal φPDDA is used as the signal φS4, while the signals φS1, φS16, and φB16 are kept high, and the signal φB4 is kept low. Accordingly, the transistors T 1 , T 15 ( x, y ), and T 16 ( x,y ) are OFF all the time, the transistor T 15 ( x, y ) is ON all the time, and the transistor T 13 ( x, y ) turns ON at readout. Thus, the photoelectric currents occurring in four pixels (forming a two-by-two unit), namely G( 2   x− 1,  2   x− 1), G( 2   x− 1,  2   x ), G( 2   x,    2   x− 1), and G( 2   x,    2   x ), are added together in the pixel G( 2   x− 1,  2   x− 1), and the sum is read out.  
         [0180]    In the third scan mode, i.e., when the data of the pixels that are located simultaneously in the (4x-3)th rows and in the (4x-3)th columns are read out, the signal φPDDA is used as the signal φS16, while the signals φS1, φS4, and φB4 are kept high, and the signal φB16 is kept low. Accordingly, the transistors T 1 , T 13 ( x, y ), and T 15 ( x, y ) are OFF all the time, the transistor T 16 ( x, y ) is ON all the time, and the transistor T 14 ( x, y ) turns ON at readout. Thus, the photoelectric currents occurring in 16 pixels (forming a four-by-four unit), namely G( 2   w− 1,  2   w− 1), G( 2   w− 1,  2   w ), G( 2   w− 1,  2   w+ 1), G( 2   w− 1,  2   w+ 2), G( 2   w,    2   w− 1), G( 2   w,    2   w ), G( 2   w,    2   w+ 1), G( 2   w,    2   w+ 2), G( 2   w+ 1,  2   w− 1), G( 2   w+ 1,  2   w ), G( 2   w+ 1,  2   w+ 1), G( 2   w+ 1,  2   w+ 2), G( 2   w+ 2,  2   w− 1), G( 2   w+ 2,  2   w ), G( 2   w+ 2,  2   w+ 1), and G( 2   w+ 2,  2   w+ 2), are added together in the pixel G( 2   w− 1,  2   w− 1), and the sum is read out. Here, w represents an odd number.  
         [0181]    With any of the above-described circuit configurations for interconnection between pixels, when interlaced scanning is performed, the photoelectric currents occurring in the pixels that need to be scanned and the photoelectric currents occurring in the pixels that do not need to be scanned are added together. This helps prevent lowering of sensitivity in interlaced scanning.  
         [0182]    As compared with the circuit configuration shown in FIG. 31, the circuit configurations shown in FIGS. 32 and 33 require a larger number of transistors, but improve circuit symmetry and thus make it very easy to produce a mask layout. Furthermore, the circuit configuration shown in FIG. 33 helps make the parasitic capacitance of the photodiode equal among pixels, and thus helps alleviate variations in low-brightness sensitivity in a case where the data of all the pixels are read out.  
         [0183]    The embodiments described above deal with cases in which the present invention is applied to a scanning circuit used in an image-sensing apparatus. It is to be understood, however, that the present invention is applicable not only to scanning circuits used image-sensing apparatuses but also to other types of scanning circuits, for example those used in display apparatuses.  
         [0184]    According to the present invention, interlaced scanning is achieved by, on one hand, feeding pulses as scanning signals to the input terminals of flip-flops belonging to a group corresponding to the photoelectric conversion elements that need to be scanned and, on the other hand, feeding a DC bias signal to the input terminals of flip-flops belonging to a group corresponding to the photoelectric conversion elements that do not need to be scanned so as to make those flip-flops active. In this way, interlaced scanning can be performed at the same scanning rate as when all photoelectric conversion elements are scanned without increasing the frequency of scanning pulses than when all photoelectric conversion elements are scanned.  
         [0185]    Thus, according to the present invention, it is possible to achieve a higher scanning rate with scanning pulses having the same frequency, or achieve the same scanning rate with scanning pulses having a lower frequency.  
         [0186]    Alternatively, according to the present invention, interlaced scanning is achieved by providing a plurality of shift registers having different numbers of stages and performing scanning by the use of one selected from among those shift registers. In this way, interlaced scanning can be performed at the same scanning rate as when all photoelectric conversion elements are scanned without increasing the frequency of scanning pulses than when all photoelectric conversion elements are scanned.