Abstract:
A method implemented according to the invention allows a user to specify with particularity hierarchical structures such as computer hardware and peripheral equipment in such a way that it simplifies the storing, retrieving, and manipulation of the information.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to the following copending, concurrently filed, and commonly assigned United States patent applications which are hereby incorporated by reference: 
     U.S. patent application Ser. No. 09/126,022, now U.S. Pat. No. 6,263,382, entitled “SIZER FOR INTERACTIVE COMPUTER SYSTEM CONFIGURATION” to Christoph Schmitz, Keith L. Kelley, Charles A. Bartlett, and Manoj J. Varghese; 
     U.S. patent application Ser. No. 09/126,025, now U.S. Pat. No. 6,253,312, entitled “METHOD OF DEVELOPING PHYSICAL REQUIREMENTS FOR COMPUTER CONFIGURATION” to Christoph Schmitz, Keith L. Kelley, Charles A. Bartlett, and Manoj J. Varghese; and 
     U.S. patent application Ser. No. 09/126,024, now U.S. Pat. No. 6,192,670, entitled “PRICE/PERFORMANCE BASED COMPUTER CONFIGURATION” to Christoph Schmitz, Keith L. Kelley, Charles A. Bartlett and Manoj J. Varghese. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a system that uses hardware description files (HDF) to generate component selection information. The method enables a application specific computer system configuration device (a “sizer”) and a framework that provides common services to all sizers (a “framework”) to store, retrieve, and process computer hardware information so that a user can interactively configure a computer system. 
     2. Description of the Related Art 
     The original computers were very complex devices that required skilled technicians and scientists to operate. When a new device, such as a printer, was added to the computer, special software and hardware needed to be developed specifically for the new device. With the advent of personal computers, it became impractical to require users to develop new software and hardware whenever new hardware was added. 
     Computer components eventually became standardized and one of the important pieces of the puzzle was the Disk Operating System, or DOS. Originally DOS only supported a small number of devices such as printers, floppy drives, and hard disk drives. In addition, DOS was severely limited in the number of different computer configurations and components such as memory and peripherals that could be supported. 
     Today, the typical consumer is presented with an astonishing number of choices with respect to the configuration of a new computer. A computer can be tailored to the particular needs of every user, from a multi-national corporation with immense database requirements to an individual who only desires to log into the Internet. There are computers specialized to perform such tasks as bulk memory storage, communications, and game playing. Depending upon a user&#39;s needs, a computer can be configured with anywhere from 16 Megabytes (Megs) to hundreds of Megs of Random Access Memory (RAM). Static storage such as hard disk drives can vary in capacity from gigabytes (10 9  bytes) to Terabytes (10 12  bytes) of data, each arranged in any one of a large number of configurations. Obviously, large amounts of RAM and static storage cost proportionally more money. As a result, there is usually a tradeoff between price and performance. 
     The number of possible devices that can be added to any particular system has also grown. Computers now routinely come with devices that were unavailable even a few decades ago, such as speakers, CD-ROM drives, and fax modems. In addition, a user can add a large number of additional components such as tape drives, network cards, and specialized, game playing devices such as a joy stick. The number of possible choices for a computer system configuration is multiplied by the number of manufacturers that produce each component producing perhaps millions of possible systems. 
     SUMMARY OF THE INVENTION 
     Using a method implemented according to the invention, computer hardware is specified using a hardware description language (HDL) and the specifications are stored in Hardware Definition Files (HDF). Using HDL and HDFs, a device such as a interactive computer system configuration device, or sizer, is able to allow a user to interactively specify requirements for a computer and peripheral hardware. Although HDL is effective at describing computer hardware, HDL is designed to describe hierarchical structures in general and is not limited to computer hardware. 
     HDL does not have control flow nor assignment statements, that is, it is purely designed to define data. In one embodiment, data is an ordered collection of trees whose leaves consist of strings and integers. Moreover, the branches of the trees are labeled with identifiers. HDL has no direct tie to computer hardware, but, since computer hardware is built hierarchically (a system consists of memory/CPU/storage subsystems, a memory subsystem consists of modules, which in turn have attributes, all of which can be addressed by a keyword), a tree can be effectively used to describe computer hardware. Rarely does one want to describe only one instance of a tree. Typically, one is interested in a whole sequence of trees that share some more or less complex property. The complex property is expressed in its own tree rather than enumerate it in every tree individually. This feature is built into HDL and makes the hardware description file very concise. The general approach facilitates extending or modifying a hardware description. For example, a peripheral devices such as a tape backups or printer can be added to a model without compromising the format of the model as it already exists. 
     In one embodiment, HDL enables a user to create extendable and modifiable hardware descriptions that can be utilized by a sizer framework to generate a computer system configured to a customer&#39;s specifications. Every piece of hardware can be represented in HDL as a tree. A computer box has room for, among other things, a mother board, a network interface card (NIC), and disk drives. The computer box, the mother board, the network card, and the disk drives can all be represented in HDL as hardware trees. In the case of the computer box, the tree would contain a leaf, or terminal, which could be replaced by a tree representing a disk drive. In this way, a disk drive can be added to the representation of the computer box without compromising any other device that might already be present, like an existing network card. If there are no available terminals in the HDL description of the computer box, HDL makes apparent that another disk drive could not be added to the configuration. In addition, a terminal that represents a half size slot would not be able to accommodate a tree representing a full size device. In one embodiment, a decision on the disk drive&#39;s inclusion may be facilitated by a method that converts requirements between physical and logical representations. In this way, HDL prevents a user of a sizer utilizing HDL from creating an unusable configuration. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which: 
     FIG. 1 is a block diagram of a computer system capable of being programmed in accordance with the present invention; 
     FIG. 2 is a block diagram of a computer system capable of being configured by an interactive computer system configuration device using the present invention; 
     FIG. 3 is a block diagram of a computer system configuration program, or sizer, including application specific sizer modules, a sizer framework, and hardware definition files; 
     FIG. 4 is a portion of a hardware description file; and 
     FIGS. 5-26 are hardware description files implemented according to the invention. 
    
    
     DETAILED DESCRIPTION OF INVENTION 
     Turning to FIG. 1, illustrated is a typical computer system S in which the sizing techniques according to the invention can be run. The computer system S in the illustrated embodiment is a PCI bus based machine, having a peripheral component interconnect (PCI) bus  10 . The PCI bus  10  is controlled by PCI controller circuitry located within a memory/accelerated graphics port (AGP)/PCI controller  14 . This controller  14  (the “host bridge”) couples the PCI bus  10  to a processor  32  and a memory subsystem  20 . 
     The host bridge  14  in the disclosed embodiment is a 440LX Integrated Circuit by Intel Corporation, also known as the PCI AGP Controller (PAC). The processor  32  is preferably a Pentium II. The processor  32  could be replaced with a different processor other than the Pentium II without detracting from the spirit of the invention. 
     The PCI bus  10  couples a variety of devices that generally take advantage of a high speed data path. This includes a network interface controller (NIC)  42 , which preferably supports the ThunderLan™ power management specification by Texas Instruments, and a floppy disk drive  74 . The floppy disk drive  74  preferably would be a 3½″ floppy disk. A video display  82 , a mouse  70 , and a keyboard  68  can also be coupled to the host bridge  14 , enabling interaction with the computer system S. 
     Finally, a sizer application  200  (see FIG. 3) would run on the processor  32  and utilize the other devices of computer system S (see previously incorporated U.S. patent application entitled “Sizer For Interactive Computer System Configuration”). 
     The computer system S illustrates only one platform in which the system according to the present invention can be implemented. The disclosed techniques can, without distracting from the spirit of the invention, be implemented in any device that executes computer programs, regardless of whether the device contains less, additional, or different components than the system in FIG.  1 . 
     THE TARGET SYSTEM CONFIGURATION 
     The techniques of the current invention can be utilized any time it is necessary to describe a hierarchical structure such as a computer system. In one embodiment of the present invention, the methods can be used within a sizer to create a system configuration. 
     Turning to FIG. 2, illustrated is a computer system R capable of being configured by a sizer using HDL. The computer system R contains multiple processors  129 ,  130 , and  131 . The processors  129 ,  130 , and  131  are each connected to their own host buses  101 ,  102 , and  103  respectively, which in turn connect to a PCI bus  110 . The PCI bus  110  is controlled by PCI controller circuitry located within a memory/accelerated graphics port (AGP)/PCI controller  114 . This controller  114  (the “host bridge”) couples also the PCI bus  110  to four memory subsystems  120 - 123 . The PCI bus  110  couples a variety of devices that generally take advantage of a high speed data path. This includes a small computer system interface (SCSI) controller  136 , with both an internal port  138  and an external port  140 . In addition, a video display  182  can be coupled PCI controller  114  for display of data by the computer system R. 
     There is a relatively loose connection between the computer system R and the memory subsystems  120 - 123 . The major constraint includes the number of controllers  114  which can be installed in the computer system R. In one embodiment, this information is maintained by a sizer framework  206  from information retrieved from hardware description files  208 - 214  (see FIG.  3 ). The information in the HDFs may contain additional data such as a user-defined PCI slot reservation for non-performance related expansions such as NICs or a Remote Insight Board. 
     Turning now to FIG. 3, illustrated is a sizer capable of utilizing HDL and HDFs to generate a system configuration, including a price/performance calculation (see previously incorporated U.S. patent application entitled “Price/Performance Based Computer Configuration”). A sizer, complete with application sizer modules  202  and  204 , a sizer framework  206 , and hardware description files (HDFs)  208 - 214  is shown. In this embodiment of the present invention, the application sizer modules  202  and  204  are designed individually for a specific application such as a computer designated as a Microsoft SQL server, a Microsoft NT server, or an Oracle database server. The sizer framework  206  contains all functionality common to any current or future application sizers. The methods of the present invention, when utilized by a sizer, enable a software developer to create and modify application sizers simply by creating or modifying an HDF. 
     The HDFs  208 - 214  are read in by the sizer framework  206  and contain descriptions of all hardware available to be configured into the computer system R. Examples of hardware, besides entire computer systems, that may be described in HDFs are memory chips, hard disks, network interface cards (NICs), memory controllers, and CD-ROM drives. A application sizer  202  or  204  may not need all the descriptions read into memory from the HDFs but the sizer framework  206 , not knowing what a specific application sizer  202  or  204  needs, reads in all that are available. In this embodiment of the present invention, the application sizers  202  and  204  have no direct connection with the HDFs  208 - 214 , but instead rely on the sizer framework  206  for information on available hardware. In another embodiment, the application sizers  202  &amp;  204  may utilize HDL and HDF directly, either solely or in conjunction with the framework  206 . 
     Turning now to FIG. 4, illustrated is a portion of a hardware description file (HDF) describing the structure of a family of servers from the ProLiant family manufactured by the Compaq Computer Company, Houston, Tex. The line numbers are not part of the HDF but are added for the reader&#39;s convenience. 
     FIG. 4 illustrates several of the language constructs of HDL. For instance, the “%” characters at lines  1 ,  8 ,  22 ,  28 , and  34  indicate the start of a device record. and the string between the “%” characters indicate the record&#39;s tag. The lines beginning with the word “TYPE” at  2 ,  9 ,  23 ,  29 , and  35  specify the type of record the next few lines contain. Lines  17 - 20  which start with the word “INCLUDE” indicate that this device may require additional records in order to be included into a configured system. 
     Starting at line  1 , the term “PL1600-SLOTS” between the “%” characters indicate that a device referred to in lines  1 - 6  is ProLiant 1600 server and that the subject of the record is the slots available in the device. Line  2  indicates that the record is of type STRUCT. Lines  3 - 6  list the slot constraints of the device, 0 PCI hot plug slots, 2 PCI slots, 4 shared slots, and 0 Extended Industry Standard Architecture (EISA) slots. 
     Another record starts at line  8  and ends at line  20 . Line  8  indicates that this record contains information about the ProLiant 1600R server family. Line  6  stores the human readable name of the device, the “ProLiant 1600.” Lines  11 - 16  contain a description of the device. Line  17  indicates that the device can have a maximum of 2 processors. Lines  19  and  20  would be understood by HDL to indicate that other records needed to be included when a ProLiant 1600 server is configured. In the tree-like structure of HDL, these lines generate terminals that would accept another record. The terminal at line  19  would correspond to a “PL — 1600-SLOTS” record like that found in lines  1 - 6 . 
     Having described the system S that runs HDL, the system R that is configured by means of a sizer using HDL, the sizer  200  that uses HDL, and an example of a HDL file used by the sizer  200  a more formal description can be made using Backus-Naur notation, a well known metalanguage for describing programming languages. The purpose of a formal description is that it is independent of any hardware description and can apply generally to any appropriate embodiment. 
     First, the goal is to describe a context free grammar (CFG) G=(N,T,P,S) that generates all syntactically legal HDL programs. The set of terminal and non-terminal symbols T and N will not be enumerated explicitly. Rather a terminal symbol will be displayed as a TERMINAL, whereas a non-terminal symbol will be rendered as a Non-terminal. In one embodiment according to the present invention, the start symbol S is identical to File. 
     A start can be made by giving production rules for basic types, such as digits, alphanumeric characters, characters, numbers, identifiers, and strings. Note that in this embodiment of the present invention there is no provision for scientific notation, so a number in the HDL context is an integer. Another embodiment might include provisions for scientific notation, as well as such concepts as imaginary numbers. 
     Digit0| . . . |9 
     Alphaa| . . . |z|A| . . . |Z 
     CharAlpha|+|−| —   
     Number−Digit|Digit|Number Digit| 
     IdAlpha|Id Char 
     Stringε|String Char 
     The operations of addition, subtraction, and multiplication are provided for integers, the selection operation “.” is available for structured objects as well. Parenthesis allow grouping and prioritizing of expressions. In another embodiment, addition operations such as division and matrix multiplication might be defined. 
     ExpExp+Factor|Exp−Factor 
     FactorFactor*Term 
     TermId|Term.Id|(Exp)|Number 
     A declaration of the basic types can be adorned with attributes (pertaining to a graphical representation of a basic type) and a comment (pertaining to a textual representation of a basic type). Values can be further adorned by the keyword GLOBAL. Another embodiment&#39;s might define other attributes. 
     Atts/ICON:Number|/INVISIBLE|/NOICON 
     Atts/COLLAPSED|/PROMOTED?VIRTUAL|/ENCRYPT 
     AttListAttList Atts|Atts 
     AttListATTRIBUTE S AttList|ε 
     Comms/NOTEXT|/STRINGID:Number|/TABLEID:Number 
     CommListCommList Comms|Comms 
     CommCOMMENT CommList|ε 
     globalε|GLOBAL 
     Declarations are comprised of a few syntax constructs. In this embodiment, there is the notion of a tuple, such as (1,2,3). Also, there is an enumeration of quoted strings with or without an IN operator attached to it. These blocks are then combined with various keywords, such as ORDER, OPTIMIZE, FROM, etc. 
     Num TupleListNum TupleList, Number|Number 
     Num Tuple(Num TupleList) 
     TupleListTupleList, Exp|Exp 
     Tuple(TupleList) 
     OrderORDER Tuple 
     OptOPTIMIZE Num Tuple Tuple 
     XAdvXADVANCE Tuple|ε 
     SizeSIZE Num Tuple 
     Elem“String” 
     ElemsElem|Elems, Elem 
     FromFROM Elems 
     InElem“String” IN Num Tuple 
     InElemsInElem|InElems, InElem 
     From InFROM InElems 
     A declaration body can be named, as in INTERGER χ5;, or unnamed, as in TYPE INTERGER 5;. In this example of one embodiment, a declaration starts with a virtual file name that is enclosed by % signs. After that, precisely one unnamed declaration follows. In the event of a declaration of TYPE STRUCT;, one or more named declarations follow. 
     IntBodyNumber Att Comm; 
     StringBody“String” Att Comm; 
     BagBodyFrom Att Comm; 
     SetBodySize FromIn Att Comm; 
     KnapsackBodyOrder XAdv Opt Size FromIn Att Comm; 
     Here are unnamed declarations. 
     IntDeclINTERGER IntBody 
     StringDeclSTRING StringBody 
     BagDeclBAG BagBody 
     SetDeclSET SetBody 
     KnapsackDecKNAPSACK Kanpsack Body 
     Here are named declarations. 
     NIntDeclINTERGER Id IntBody 
     NStringDeclSTRING Id StringBody 
     NBagDeclBAG Id BagBody 
     NSetDeclSET Id SetBody 
     NKnapsackDeclKNAPSACK Id Knapsack Body 
     NIncDeclINCLUDE Id “String”; 
     NValueDeclVALUE Id Expression Global Att Comm; 
     NDeclNIntDecl|NKnapsackDecl|NValueDecl|NIncDecl 
     A series of named declaration is part of a struct type. 
     NDeclsNDecl|NDecl NDec| 
     To specify the declaration itself, we now only need two rules: 
     DeclBodyIntDecl|StringDecl|BagDecl|SetDecl 
     DeclKnapsackDecl|STRUCT Att Comment; NDecls 
     Declaration% String % TYPE DeclBody 
     A start symbol File generates a syntactically legal HDL program which is stored in a ASCII file with extension .hdf (Hardware Description File). The specific file extension is not important; “hdf” is used for illustrative purposes only 
     FileDeclaration|File Description 
     It is now possible to describe trees and collections of trees formally. In order to do this, notation and operations on collection of trees need to be specified. The first definition defines a notation of an ordered sequence. 
     DEFINITION 1: 
     Given a countable set S={s 1 , . . . } of elements, we call a sequence s i1 , . . . ,s ik  of those elements where i 1 , . . . i k  ε IN an ordered collection of elements or BAG and we will denote it as &lt;s ik , . . . ,s in &gt;. The set of all bags of size k are denoted B k (S). The union of all B k (S) is called B(S), or even shorter B. 
     In order to manipulate the bags, it is necessary to define some operations on the bags. The following definitions specify five possible operations on bags, including ways to count, combine, and sum bags. 
     DEFINITION 2: 
     1. A Size operator, η: 
     
       
         |&lt;x 1 , . . . ,x n &gt;|=η 
       
     
     2. A Concatenation operator, ⊕: 
     
       
         &lt;a 1 , . . . ,a n &gt;⊕&lt;b 1 , . . . ,b m &gt;=&lt;a 1 , . . . ,a n ,b 1 , . . . ,b m &gt; 
       
     
     3. An Inner product operator, {circle around (x)}: 
     
       
         &lt;a 1 , . . . ,a n &gt;{circle around (x)}&lt;b 1 , . . . ,B m &gt;=&lt;&lt;a 1 ,b 1 &gt;, . . . ,&lt;a 1 ,b m &gt;, . . . ,&lt;a n ,b 1 &gt;, . . . ,&lt;a n b m &gt;&gt; 
       
     
     This binary operator can be generalized to the n-ary use. Given a bag b,-fold application can be denoted: 
     b{circle around (x)} . . . {circle around (x)}b as b n . Given a bags B, all n-fold 
     Products are denoted: 
     [2 B ] n  and their union 2 B . 
     4. An outer product operator, x: 
     
       
         &lt;a 1 , . . . ,a n &gt;x&lt;b 1 , . . . ,b n &gt;=(a 1 b 1 ), . . . ,(a n b n )&gt; 
       
     
     Note that for an outer product operator to be appropriate both bags to have the same number of elements. 
     5. For bags of integers B(Z), the sum operator, Σ:          ∑     〈       a   1     ,                …                   a   n         〉       =       ∑     i   =   1     n            a   i     .                              
     6. A Filtering operator, using set theoretic notation: 
     
       
         B′=&lt;xεB|x&gt;5&gt; 
       
     
     This expression indicates that all elements x greater than 5 are removed from bag B to create a new bag B′. 
     Next, the notion of a tree with branches that are tagged is inductively defined. 
     DEFINITION 3: 
     Given a countable set S of leaf elements and a countable set T of tags, then: 
     1. xεT if xεS 
     2. &lt;(t 1 ,x 1 ), . . . ,(t n ,x n )&gt;εT if x1, . . . ,X n εT and t 1 , . . . ,t n εT. 
     3. No other element is in T. 
     T(S,T) is denoted as the set of tagged trees relative to S and T, or T for short. 
     Furthermore, a partial function, α, is inductively defined as: 
     
       
         α:B(T)×T(S,T)→B(S): 
       
     
     This next definition captures the notion of selecting a subset of leaves in a tree along a given path. 
     DEFINITION 4: Selecting the leaves of a tree. 
     1. If a=&lt;(t 1 ,a 1 ), . . . ,(t n ,a n )&gt; and t=&lt;x,y, . . . &gt; with x=t I  for some IεI ⊂ {1, . . . ,m}, then          α        (     t   ,   a     )       =       ⊕     i              ∈              T            α        (       〈     y   ,   …     〉     ,     a   i       )                                
     2. If a=&lt;(t 1 a 1 ), . . . ,(t n ,a n )&gt; and t=&lt;x, . . . &gt; with x ≠t I  for all iε{1, . . . ,n}, then          α        (     t   ,   a     )       =       ⊕     i              ∈                {     1   ,                …                 m       }              α        (     t   ,     a   i       )                                
     In the event any of those operands are undefined, the result would be undefined. 
     3. If aεS and t=, then α(a,t)=a. 
     4. In all other cases, α is undefined. 
     Using notation defined above, it is now possible to give the meaning of the different statements that HDL describes. The idea is to incrementally construct the following mapping: 
     
       
         τ:Σ*→B(T*(Σ*,Σ*∪Z)) 
       
     
     In words, “set of bags of trees using words as labels and words or integers as leaves.” Here, Σ is the set of all words over the HDL alphabet. Each declaration in a HDL file describes one mapping of a word tag to a tagged collection of trees whose leaves are either strings or integers. To achieve this, the following partial function is defined that maps declarations of HDL into a ordered collection of trees: 
     
       
         μ:Σ*→B(T*(Σ*,Σ*∪Z)) 
       
     
     Rules can now be assigned to the context free grammar that was defined earlier. In one embodiment of the present invention, this may be formalize as an attributive grammar with synthesized and inherited attributes, but, in this embodiment, a more direct path is taken by rolling some cases into one for the sake of conciseness. 
     RULE 5: Given μ and Declaration* % x % y, where x,yεE, τ new =τ 1 ∪(x,μ(y)) 
     The next two rules explain language constructs, From and FromIn, which are generated by non-terminals, or branches of a tree. 
     RULE 6: Given μ and τ and From*χ=“χ l ”, . . . , “χ n ”, where x 1 , . . . ,x n εΣ, then          μ   new     =     μ   ⋃     (     χ   ,         ⊕   n       i   =   1            σ        (     χ   i     )           )                              
     RULE 7: Given μ and τ and 
     
       
         FromIn*χ=“χ 1 ”,“χ n ”IN(α 1 ,b 1 ), . . . ,IN(α n ,b n ) 
       
     
     where χ 1 , . . . ,χπεΣ* and α 1 b 1 , . . , α n , b n εIN, define          B   =           ⊕   n       i   =   1            σ        (     χ   i     )         =     &lt;     γ   1           ,   …              ,       γ   m     .                            
     For each γ 1  that originated in σ(χ 1 ), define (a 1   j , b j )=(a i , b i ), Then 
     
       
         B′=&lt;&lt;k 1 , . . . ,k 1 .ε2 B |k 1 ≦≦k 1 ,∀m 
       
     
     
       
         ε{1, . . . ,1}:mε[a 1   m ,a 1   m ]&gt; 
       
     
     Then 
     
       
         μ new =μ∪(χ 1 B 1 ) 
       
     
     Most of the production rules are concerned with an aspect of visualization. The collections of trees described in the following rule by the declaration of TYPE KNAPSACK and TYPE SET are identical. 
     RULE 8: Given μ and τ and KnapsackDec|*ω=χγγ′z or SetDecl|χω=χγγ′z 
     where 
     
       
         γ=SIZE(s 1 ,s 2 ) 
       
     
      and 
     
       
         γ 1 =“y 1 ”IN(a 1 ,b 1 ), . . . ,“χ n ”IN(a n ,b n ) 
       
     
     Then 
     
       
         B″=&lt;tεμ(y′)||t|ε[S 1 ,S 2 ]&gt; 
       
     
      and 
     
       
         μ new =μ∪(ω 1 B″) 
       
     
     The following declaration of type TYPE BAG is based solely on From: 
     RULE 9: Given μ and τ and BagDec|χωχγz, 
     where 
     
       
         y=“y 1 ”, . . . ,“γ n ” 
       
     
     Then 
     
       
         μ new =μ∪(ω,μ(y)) 
       
     
     The meaning of the literals should now be obvious: 
     RULE 10: Given μ and τ and String*χ or Number*χ, then 
     
       
         μ new =μ∪(I,&lt;I&gt;) 
       
     
     The following rule defines a STRUCT declaration. Initially, it restricts our meaning of functions to structs that do not contain named VALUE declarations. 
     RULE 11: Given μ and τ and 
     
       
         String*ω=TYPE STRUCT;t 1 i 1 b 1 ; . . . t n i n b n   
       
     
     under the condition that 
     
       
         t 1 , . . . ,t π ε{INTERGER, STRING, BAG, SET, KNAPSACK} 
       
     
      and 
     
       
         GNTId*i 1 | . . . |i n , 
       
     
      define 
     
       
         μ new =μ∪(ω,&lt;i 1 , . . . ,i n ,&gt;x(μ(b 1 ){circle around (x)} . . . ,{circle around (x)}μ(b π ))) 
       
     
     Next, the focus is on expressions. Expressions can only be evaluated in the context of a tagged tree T. So far, only a collection of tagged trees has been talked about. The trees can be visualized along a timeline, that is, at each point in time, only one of the trees in a collection will exist. It therefore makes sense to speak of a “current” tree in a collection of trees. 
     RULE 12: Given a tagged tree T, the following expressions are defined: 
     1. Using grammatical rules TermId|Term. Id that result in word I 1 .I 2  . . . I n , we will define μ T (I 1 .I 2  . . . I n )=Σα(&lt;I 1 , . . . , I n &gt;, T) 
     2. From FactorFactor * Term that result in word I 1 *I 2 , define μ T (I 1 .*I 2 )=μ T (I 1 )*μT(I 2 ) 
     3. From ExpExp +Factor|Exp−Factor that result in word I 1 +I 2 , I 1 −I 2 , define 
     
       
         μ T (I 1 +I 2 )=μ T (I 1 )+μ T (I 2 ) 
       
     
     
       
         μ T (I 1 −I 2 )=μ T (I 1 )−μ T (I 2 ) 
       
     
     The last gap of the meaning function can now be closed, the named VALUE declaration in TYPE STRUCT: 
     RULE 13: Given μ and τ and String*ω=I VALUE i b, 
     where 
     
       
         I=TYPE STRUCT;t 1 i 1 b 1 ; . . . t π i π b π ; 
       
     
      and under the condition that 
     
       
         t 1 , . . . ,t π ε{INTERGER, STRING, BAG, SET, KNAPSACK} 
       
     
      and 
     
       
         Id*i 1 | . . . |i n , call μ T (I)=&lt;T 1 , . . . ,T m &gt; 
       
     
      then, 
     
       
         μ new =μU(ω,&lt;T 1 {circle around (x)}(t,μ T1 ,(b)), . . . ,T 1 {circle around (x)}(t,μ T1 ,(b))&gt;) 
       
     
     Describing tagged trees is not enough to make HDL useful. The language needs to provide an interface that allows mainstream computer languages such as C++ to interface with the formal objects that are defined in the previous section. Here is a list of queries that may be implemented in a host language to make HDL useful. 
     1. A facility that implements r or, in other words, given a virtual file name η, construct the sequence of tagged trees that are associated with it. Since a sequence of trees can be visualized to exist along a timeline, only the first tree needs to be constructed. To get the second, third, etc., the following method is needed. 
     2. A method to iterate to the successor of the current tree. This also entails a signal when the list of possible tagged trees is exhausted. 
     3. An evaluator of expressions with regard to a specific tree. Basically, this would be an implementation of the previously defined a function, as well as an arithmetic expression evaluator. 
     Finally, in the case of a KNAPSACK declaration, there has to be a special query that sets it apart from a SET declaration, for they describe the same set: So far the actual order of the tagged trees is left unspecified. In the case of KNAPSACK, all trees T=&lt;T 1 , . . . , T n &gt; are ordered according to an expression I 1  such that 
     
       
         μ T1 (I)≦ . . . ≦μ Tn (I) 
       
     
     This is reflected in the syntax by giving the keyword ORDER followed by expression I. Furthermore, signs, S 1 , . . . S m ε{−1,1}, and expressions, I 1 , . . . , I m , are given by the keyword OPTIMIZE. This induces the following subset of trees: 
     
       
         S((s 1 ,s 2 ),(a 1 , . . . ,a n ))=&lt;tεT||t|ε[s 1 ,s 2 ],s 1 με(χ 1 )≧a 1 , . . . ,s n μ t (χ n )≧a n &gt; 
       
     
     and queries of the following form are allowed: 
     
       
         Find Y((s 1 ,s 2 ),(a 1 , . . . ,a n ))=min {μ_(I)|tεS((s 1 ,s 2 ),(a 1 , . . . ,a n ))} 
       
     
     This is essentially a multidimensional range query, for which there are multiple efficient data structures known in the art. 
     HARDWARE DEFINITION FILES 
     Given this hardware definition language, hardware definition files can be created that describe a variety of products, including boards, controllers, drive cages, and controller combinations, fits, drives, memory, network interface cards, and the like. Turning to FIGS. 5-24, illustrated are a number of such files. 
     Turning to FIG. 5, illustrated is a board&#39;s hardware description file. This is typical of a number of the remaining hardware description files. Typically, each hardware device has at least a price pertaining to the part, a total price (only different if the part price is a composite), part number, and human readable name. These data items are kept in a global hardware definition file discussed below. 
     Referring to FIG. 5, the board&#39;s hardware description file includes this typical structure, which illustrates part price, part number, and external name. 
     Turning to FIG. 6, illustrated is a controller&#39;s hardware description file. If drive controller redundancy is required, a separate entry will provide for a controller redundant pair, since they act as a logical unit. As can be seen in the controller&#39;s hardware description file, drive cages, number of channels, number of internal channels, number of logical controllers, number of physical controllers, number of logical channels, number of PCI slots, part number, external name, are all described. 
     Turning to FIG. 7, illustrated is the conversion&#39;s hardware description file, which is similar to the board&#39;s hardware description file of FIG.  5 . Again, it provides the basic information of price, part number, and external name. 
     Turning to FIG. 8, illustrated is a drive cage/controller table that provides stored combinations of parts that be combined in numerous ways. This structure prevents a query according to a primary criteria on any of a number of secondary criteria. Of note, these are further described in concurrently filed application entitled “Method of Developing Physical Requirements for Computer Configuration,” especially in the source code appendix. Referring to FIG. 8, as can be seen, number of channels, number of bays, shared channels, fiber channels, and the like are all provided in this drive cage/controller table. 
     Turning to FIG. 9, illustrated is a drive cage fit file DCFit which is used to describe the fit for a drive cage. 
     Turning to FIG. 10, shown is a description file which maps part numbers into names. 
     Turning to FIG. 11, a drive cage file is used to define the attributes of particular drive cages. This includes virtual drive heights, the virtual height of a drive cage, number of channels, plugability, and a variety of other attributes. 
     Turning to FIG. 12, illustrated is a drives file, which is typically used to define hard drives. The illustrated file includes external name, here a 2.1 GB wide ultra SCSI, attribute such as speed, drive heights, capacity, and related drives. 
     Turning to FIG. 13, shown is a hubs file which is similar to the board file of FIG.  5 . 
     Turning to FIG. 14, shown is a memory fit file MemFit which is used to define memory modules fit capability. 
     Turning to FIG. 15, illustrated is a memory module file, which defines attributes of various memory modules, including its external name and capacity. 
     Turning to FIG. 16, illustrated is a NICFit file which defines the “fit” of network interface cards. 
     Turning to FIG. 17, shown is a NICs file which is used to define various network interface cards. The illustrated file, for example, is a Netelligent 10/100 TX PCI UTP controller, which provides 10 or 100 base T. It includes bits fields for describing the type of network that it is adapted for, bandwidth, and number of connectors. 
     Turning to FIG. 18, shown is a part number file, which is similar to the description file of FIG.  10 . 
     Turning to FIG. 19, illustrated is a main file for a server. It defines the number of slots, PCI slots, shared EISA slots, ranking, upgradeability, physical configuration, hot plugability, display, memory, number of slots, price, external name, processor, memory, and slot fits, and availability. These are typically repeated for a variety of other servers. 
     Turning to FIG. 20, illustrated is a price list file, which is similar to the part number file of FIG.  18 . 
     Turning to FIG. 21, illustrated is a power supply file that is similar to the board file o FIG.  5 . 
     Turning to FIG. 22, illustrated is a processor fit file that defines the configuration of the processor. It includes, for example, the type of processor, the maximum number of processors, speed, and cache size. 
     Turning to FIG. 23, illustrated is a processor file that defines the attributes of a stand alone processor, such as a Pentium Pro™. 
     Turning to FIG. 24, illustrated is a slot fit file that defines the configuration for a slot, particularly within a drive cage. 
     Turning to FIG. 25, illustrated is a file CPQHDW which defines sets of servers, drives, NICs, and a master record to bind the three. 
     Finally, Turning to FIG. 26, illustrated is a global file which binds together price list, part number, and description. 
     All of these files are loaded by the sizer framework using the language definitions described above, and employed by the various class and categories described in co-pending entitled “Sizer for Interactive Computer System Configuration” in developing recommended system configurations. 
     The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details of the illustrated circuitry and construction and method of operation may be made without departing from the spirit of the invention.