Abstract:
An analog to digital converter system with clock timing compensation includes an analog to digital converter circuit having an input terminal for receiving an analog signal to be sampled and converted to a digital value, one or more output terminals providing one or more logical output signals, and a clock terminal for receiving a sampling clock signal for clocking the sampling of the input signal. A thermally compensated clock circuit is responsive to a clock signal for providing the sampling clock signal, and includes a low pass filter circuit comprising a resistor element and a varactor diode, and a varactor bias network for providing a thermally compensated varactor bias voltage to the varactor diode. The clock timing circuit with varactor diodes can be used to provide very fine resolution adjustments to the individual clock circuits in a multiple analog to digital converter circuit system. The thermally compensated varactor bias networks allow the clock timing to stay within specification over a wide temperature range.

Description:
This invention was made with Government support under Contract No. DAAB07-97-C-D614 awarded by the Department of the Army. The Government has certain rights in this invention. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     This invention relates to analog to digital converter circuits, and more particularly to techniques for ensuring accurate clock timing over wide temperature ranges. 
     BACKGROUND OF THE INVENTION 
     The timing alignment of the sampling clock that is used by each analog to digital converter is important for good image rejection of the interleaved output of multiple analog to digital converters. Clock phase alignment has typically been accomplished using fixed low value capacitors, solder pad jumper matrices on printed wiring boards, matched length cabling, fixed element passive delay lines, or active integrated circuits (programmable delay lines). These techniques suffer from one of the following disadvantages: lack of a means for temperature compensation or of a simple adjustment of the delay value, degradation of the clock phase jitter value, or insufficient adjustment resolution. 
     It would therefore be an advantage to provide a technique for improved clock alignment resolution. 
     SUMMARY OF THE INVENTION 
     In accordance with one aspect of the invention, an analog to digital converter system with clock timing compensation is described. The system includes an analog to digital converter circuit having an input terminal for receiving an analog signal to be sampled and converted to a digital value, one or more output terminals providing one or more logical output signals, and a clock terminal for receiving a sampling clock signal for clocking the sampling of the input signal. A thermally compensated clock circuit is responsive to a clock signal for providing the sampling clock signal, and includes a low pass filter circuit comprising a resistor element and a varactor diode, and a varactor bias network for providing a thermally compensated varactor bias voltage to the varactor diode. 
     According to another aspect of the invention, varactor diodes are used in a low pass filter configuration to provide very fine resolution adjustments to the individual clock circuits in a multiple analog to digital converter circuit system. A thermally compensated varactor bias network allows the clock timing to stay within specification over a wide temperature range. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other features and advantages of the present invention will become more apparent from the following detailed description of an exemplary embodiment thereof, as illustrated in the accompanying drawings, in which: 
     FIG. 1 is a schematic diagram of a clock timing circuit for an analog to digital converter in accordance with the invention. 
     FIG. 2 is a schematic block diagram of multiple analog to digital converters connected in parallel as a ping pong ADC circuit, and wherein clock timing circuits are used in accordance with the invention for each analog to digital converter. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates a circuit technique in accordance with an aspect of this invention for providing timing alignment of the clock phase for an analog to digital converter (ADC) circuit. Device  52  is an ADC device, in this exemplary embodiment a commercially available device such as the Analog Devices AD9070 ADC, providing 10 bit resolution at 100 MHz with a nominal clock rate of 87.5 MHz. The device  52  has analog input terminals AIN and /AIN, for receiving the analog inputs to the device  52 . The input signals at these two inputs differ from each other only in that they are 180° out of phase. The AIN terminal is typically considered the in-phase input terminal for receiving the in-phase version of the input signal, and the /AIN terminal the input terminal for the receiving the out-of-phase version of the input signal. In-phase and out-of-phase signals are commonly used in analog-to-digital conversion techniques to improve common mode noise rejection at the sensitive inputs of the analog-to-digital converter circuit. For this exemplary embodiment, the typical AIN and /AIN input frequencies of the circuit are in the range of 5 MHz to over 80 MHz, although this range will differ for each application. 
     A ten-bit digitized output for the device  52  representative of the amplitude of the input signal is represent by the logic levels on outputs D 0 -D 9 . 
     A differential clock circuit  60  provides sampling clock signals at ENCODE and /ENCODE device terminals for the ADC device  52 . The ENCODE terminal receives the in-phase version of the clock signal, and the /ENCODE terminal receives the out-of-phase (180°) version of the sampling clock signal. In this exemplary embodiment, the clock signal frequency is fixed at 87.5 MHz, although the clock frequency will of course be dependent on the application. 
     An adjustable low pass filter provides a timing alignment delay in accordance with an aspect of the invention on the differential clock circuit. In this embodiment, the clock circuit responds to clock signals CLOCK_T and CLOCK_at terminals  62  and  64 , respectively. Resistors R 1 /R 2  and varactor diodes D 1 /D 2  comprise the adjustable low pass filters that provides the alignment time delay. Thus, resistor R 1  and diode D 1  are connected in series between terminal  62  and node  72  to provide a first low pass filter, with the ENCODE device terminal connected at node  66 . Similarly, resistor R 2  and diode D 2  are connected in series between terminal  64  and node  74  to provide a second low pass filter, with the /ENCODE device terminal connected at node  70 . 
     The varactor diodes D 1  and D 2  have the well known characteristic of a voltage-dependent junction capacitance, wherein the capacitance decreases with the reverse-bias voltage. 
     Respective resistors R 3 /R 4  are connected in series with resistors R 1 /R 2 , and are used to decrease the sensitivity of the varactor bias adjustment, in case the varactor diodes selected for a particular circuit have a larger than needed capacitance range. The resistors R 3 /R 4  are not necessary in some applications; if the capacitance value of the varactor diodes (discussed below) is not too high for the amount of time delay range desired, then these resistances can be set to zero ohms. 
     Resistor R 5  is connected between device terminals ENCODE and /ENCODE, and is the differential clock termination resistor for ADC device  52 . For some ADC devices, this resistor is employed to properly terminate the ENCODE and /ENCODE differential clock signals. The clock signal rise and fall times are important for good performance of the ADC circuits. The value of R 5  is set to match the line impedance of the differential clock signal, e.g. for an exemplary application, 50 ohms. For this exemplary line impedance value, the value of R 5  can be set to 100 ohms. 
     Capacitor C 1  is connected between connected nodes  72 ,  74  and ground, and serves two purposes. The first is to provide an RF path to ground for the clock signal present at diodes D 1  and D 2 . The second purpose is provide one of two filter stages for the varactor bias voltage provided at resistor R 6 . 
     A varactor diode bias network  80  is connected to common nodes  72  and  74 , to provide a bias voltage for the varactor diodes D 1 , D 2 . A first bias voltage filter stage is formed by resistor R 8  and capacitor C 2 , with resistor R 8  connected between node  76  and a reference voltage at node  79 , +10 V in this exemplary embodiment. Capacitor C 2  is connected between node  76  and ground. 
     The varactor diode bias voltage should be very clean from extraneous noise that may appear on the +10 V reference voltage. Noise on the varactor diode bias would cause the varactor diodes to introduce timing jitter of the clock signal and therefore degrade the ADC performance. The first bias filter stage formed by R 8  and C 2  is a simple low pass filter. The characteristics of the low pass filter can be changed to match the requirements of the particular application. 
     The bias network  80  further includes resistor R 7 , which with R 8  sets the room temperature voltage value. R 7  and R 8  form a voltage divider network. The +10 V reference voltage applied to network  80  is changed to a lower voltage needed by the varactor diodes by the amount set by the relationship of the R 7  and R 8  resistance values. For example, if R 7  and R 8  were both 1000 ohms, then the voltage that would appear at node  74  would be half the +10 V reference voltage. The particular values of R 7  and R 8  are selected to set the time delay of the ADC clock signal at room temperature. 
     The bias network  80  further includes resistors R 9  and R 10  and thermistors RT 1  and RT 2  used as necessary to provide temperature compensation. Thermistor RT 1  is connected in series with resistor R 9  between node  76  and ground. Thermistor RT 2  is connected in series with resistor R 10  between node  76  and the +10 V reference voltage. The clock delay value is proportional to the varactor bias voltage provided by network  80 . The varactor bias voltage is compensated for temperature variations by R 9 , R 10 , RT 1  and RT 2 . For some applications, one or more of R 9 , R 10 , RT 1  and RT 2  can be set to zero ohms, in order to achieve proper temperature compensation. 
     Exemplary element values and devices for the circuit elements of FIG. 1 for one application are set out below, although these parameters will vary according to the requirements of a particular application. 
     R 1 , R 2 =51.1 ohms 
     R 3 , R 4 =0 ohms 
     R 6 =10000 ohms 
     R 7 =6980 ohms 
     R 8 =6040 ohms 
     R 9 = 4300  ohms 
     R 10 , RT 2 =not installed 
     RT 1 =U.S. Sensor Corp. part number 502FG1K 
     C 1 , C 2 =0.1 microfarad 
     D 1 , D 2 =Philips Semiconductor part number BB405B 
     The circuit of FIG. 1 employs a resistor/capacitor low pass filter, with the capacitor replaced by a varactor diode, and allows for a very high degree of clock alignment resolution. The use of varactor diodes in a low pass filter configuration does not add to the phase jitter of the clock signal. Other techniques using programmable active components would have an adverse effect on the clock phase jitter. The varactor diode bias network is easily adjusted with a thermistor to provide temperature compensation of the clock timing adjustment alignment. 
     The circuit technique illustrated in FIG. 1 can be employed as a means of aligning the clock signal for multiple analog to digital converters, to allow use of lower sampling speed analog to digital converters operating in parallel to appear as a single analog to digital converter operating at a higher sampling rate. For some applications, for example, the clock alignment needs an adjustment resolution of 1 picosecond or less. In addition to the fine adjustment resolution, the alignment circuit cannot be allowed to degrade the clock phase jitter parameter. 
     This invention is particularly useful for systems which employ multiple analog to digital converters in parallel, commonly referred to as “ping pong” ADC circuits. An advantage is that lower cost analog to digital converters can be used to duplicate the performance of a single high speed analog to digital converter. Another advantage of the invention is that the sampling rate performance of high resolution analog to digital converter circuits can be increased beyond the available single par solutions for the equivalent resolution. All wideband RF applications using analog to digital converters could benefit from the invention. 
     FIG. 2 shows an exemplary ping-pong ADC circuit  100  employing the present invention. The analog input is passed through a transformer  102  in this exemplary embodiment to transform a single-ended analog input signal into differential signals which are 180° out-of-phase for the ADC devices  52 A,  52 B. A clock amplifier circuit  104  is responsive to the sampling clock input to provide differential clock signals which are 180° out of phase for the timing alignment circuits  60 A,  60 B. As illustrated in FIG. 2, the differential clock signals are connected to the first timing alignment circuit  60 A in the same phase sense as for the circuit of FIG. 1, i.e. with the in-phase and out-of-phase clock signals connected to the respective ENCODE and /ENCODE terminals of ADC device  52 A. However, the differential clock signals are connected to the second timing alignment circuit  60 B in the reverse order, i.e. the in-phase and out-of-phase clock signals are connected to the respective /ENCODE and ENCODE terminals of the ADC  52 B. 
     In this way, the two ADC devices  52 A,  52 B are sampling the analog input signal on opposite edges of the ENCODE clock signal. For example, the first ADC device  52 A will sample the analog input signal on the rising edge of the clock signal and the second ADC device  52 B will sample the analog input signal on the falling edge of the clock signal. In order for the circuit  100  to have high performance, the two ADC devices  52 A,  52 B need to be precisely 180° out of phase. THe precise control of this timing relationship is provided by the timing alignment circuits  60 A,  60 B in accordance with an aspect of the invention. Each of the circuits  60 A,  60 B is as described above with respect to circuit  60  of FIG. 1, and each includes a varactor bias network as discussed above to provide the timing compensation. 
     It is understood that the above-described embodiments are merely illustrative of the possible specific embodiments which may represent principles of the present invention. Other arrangements may readily be devised in accordance with these principles by those skilled in the art without departing from the scope and spirit of the invention. For example, while the illustrative embodiments shown in FIGS. 1 and 2 have employed differential input and clock signals, the invention can be employed with single-ended analog signals and single-ended clock signals.