Abstract:
A stacked module device and corresponding module and method are provided where at least some modules have input ports connected to receive first resource related signals and output ports connected to provide second resource related signals. The first and second signals are different, and each module comprises a resource signal transformation unit for generating the second signal from the first signals. The resource signal transformation units of each module are of the same construction. Resources may be addresses. Further, a software configurable address assignment is provided.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention generally relates to devices having stacked modules, and to corresponding stackable modules and operation methods, and in particular to the assignment of resources in such devices.  
         [0003]     2. Description of the Related Art  
         [0004]     Stacked module devices exist where a number of compatible modules are stacked onto a host board. The modules may be PCBs (Printed Circuit Boards) which are placed one on top of the other, but the modules may also be single chips, or larger groups of components. In any case, a module has a bottom connector to connect to the neighboring module located below the respective module, and a top connector to connect to the next upper module.  
         [0005]     Such stacked module devices often receive resource related signals from the very bottom. Resource signals may in this context be, for instance, clock signals, chip select signals, or address signals. The lowest module receives the signals and feeds the signals through to the next module which is located upwards. This module does substantially the same, i.e., it forwards the received signals to the next upper module. By this scheme, all of the modules are enabled to access the resources.  
         [0006]      FIG. 1  depicts a conventional stacked module device having four modules  100 - 130 . In the example of  FIG. 1 , six resource related input signals are fed through the modules, thereby forming a signal bus. As apparent from  FIG. 1 , each module may use one or more of the resources, for instance to synchronize to a specific clock, to use specific chip select signals, or to be addressable at a given address, or access a separate memory (not shown) at a given address.  
         [0007]     However, there may be a resource conflict if two or more modules  100 - 130  access the same resources. For that reason, each module  100 - 130  requires an individual resource selection device  140 - 170  to assign resources to the respective stack position. The resource selection devices  140 - 170  may be preconfigured, or there may be an extra signalling bus connecting the resource selection devices to each other, allowing the devices  140 - 170  to communicate to each other in order to avoid a conflict.  
         [0008]     However, the necessity to provide selection devices on every stack position is often found to be detrimental since this involves additional hardware efforts and reduces flexibility. Moreover, adding a further module to the stack may require a reconfiguration of the existing modules in the stack. This may further reduce the reliability of the entire system.  
       SUMMARY OF THE INVENTION  
       [0009]     An improved device having stacked modules, and a corresponding module and method are provided that may improve reliability and operating range and further reduce the component parts.  
         [0010]     In an embodiment, a device having stacked modules is provided where at least some of the modules have input ports connected to receive first resource related signals from a first neighboring module, and output ports connected to provide second resource related signals to a second neighboring module. The second resource related signals are different from the first resource related signals. Each one of the at least some modules comprise a resource signal transformation unit, which is adapted to generate the second resource related signals from the first resource related signals. The resource signal transformation unit of each one of the at least some modules are of the same construction.  
         [0011]     In a further embodiment, a module which is stackable into or onto a module stack device is provided. The stackable module has input ports connected to receive first resource related signals from a first neighboring module, and output ports connected to provide second resource related signals to a second neighboring module. The second resource related signals are different from the first resource related signals. Each one of the at least some modules comprise a resource signal transformation unit which is adapted to generate the second resource related signals from the first resource related signals. The resource signal transformation units of each one of the at least some modules are of the same construction.  
         [0012]     In yet another embodiment there is provided a method of operating a device having stacked modules. The method comprises, in at least some of the modules, receiving first resource related signals at input ports of the respective module from a first neighboring module, generating second resource related signals from the first resource related signals where the second resource related signals are different from the first resource related signals, and providing the second resource related signals at output ports of the respective module to a second neighboring module. Generating the second resource related signals from the first resource related signals comprises operating a resource signal transformation unit which is of the same construction in each one of the at least some modules.  
         [0013]     In still a further embodiment, a method of operating a device having stacked modules is provided. The method comprises receiving, in a first module, a first address signal, and accessing the first module at an address represented by the first address signal. The method further comprises configuring a software configurable address assignment unit of the first module to output a second address signal to a second module. The method further comprises receiving in the second module the second address signal and accessing the second module at an address represented by the second address signal.  
         [0014]     According to a further embodiment, there is provided a device having a stack of modules. At least some of the modules have one or more input terminals to receive a first number of address bits and one or more output terminals to output a second number of address bits. The at least some modules comprise means adapted to determine the second number of address bits.  
         [0015]     According to still a further embodiment, a method of operating a stack of modules is provided where at least some of the modules perform the step of receiving a first number of address bits, determining a second number of address bits, and outputting the second number of address bits. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The accompanying drawings are incorporated into and form a part of the specification for the purpose of explaining the principles of the invention. The drawings are not to be construed as limiting the invention to only the illustrated and described examples of how the invention can be made and used. Further features and advantages will become apparent from the following and more particular description of the invention, as illustrated in the accompanying drawings, wherein:  
         [0017]      FIG. 1  illustrates a conventional stacked module device having four modules;  
         [0018]      FIG. 2  illustrates a stackable module according to an embodiment;  
         [0019]      FIG. 3  illustrates a stacked module device according to an embodiment;  
         [0020]      FIG. 4  illustrates a stackable module according to another embodiment;  
         [0021]      FIG. 5  illustrates a stacked module device according to another embodiment;  
         [0022]      FIG. 6  illustrates a stackable module according to yet another embodiment;  
         [0023]      FIG. 7  illustrates a stackable module according to a further embodiment;  
         [0024]      FIG. 8  illustrates yet another stackable module according to an embodiment;  
         [0025]      FIG. 9  illustrates a further stackable module according to an embodiment;  
         [0026]      FIG. 10  illustrates still a further stackable module according to an embodiment;  
         [0027]      FIG. 11  illustrates a stackable module according to yet another embodiment;  
         [0028]      FIG. 12  illustrates a stackable module according to still a further embodiment;  
         [0029]      FIG. 13  illustrates a stackable module according to another embodiment; and  
         [0030]      FIG. 14  is a flow chart illustrating an iterative method of performing a software based address assignment according to an embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0031]     The illustrative embodiments of the present invention will be described with reference to the figure drawings wherein like elements and structures are indicated by like reference numbers.  
         [0032]     Referring now to the drawings, a number of embodiments will be described, allowing for automatic, configuration-free resource assignment in stacked bus systems or other stacked module devices.  
         [0033]     In an embodiment, the modules take the first one or first ones of the input signals from the bottom connector, i.e., the connector which is directed to the host board. The module then shifts the resource vector by the amount of resources used by the module.  
         [0034]      FIG. 2  depicts an example where the resource related signals are clock signals. The module  200  uses the first clock signal CLK 0  and shifts the remaining clock input signals by one position. That is, what was received as signal CLK 1  will be supplied to the next module as CLK 0 . The highest clock signal to be provided to the next module is connected to a predefined signal source, such as ground.  
         [0035]      FIG. 3  illustrates a device having four modules as discussed above. However, in the embodiment of  FIG. 3 , the number of clock input signals is reduced to four. As apparent from the figure, each module is of the same construction and has no hardware consuming resource selection device. Nevertheless, each module uses a different clock signal, thus avoiding a resource conflict.  
         [0036]     In the example of  FIG. 3 , each module uses the clock signal received at its first input port. By forwarding the clock signal received at the second input port to the first output port, each module assigns the respective clock signal to the next module in the stack. That is, each module has a connection between the second input port and the first output port, and this connection works as assignment means to assign the respective clock resource to the respective next module.  
         [0037]     Further, to allow the remaining modules to properly assign the respective resource, each module further transfers the signals received at the remaining input ports to the respective shifted output ports. That is, module  300  has signal transfer means to forward the third clock input signal CLK 2  received at the third input port to the second output port, thereby enabling module  310  to assign this clock signal to module  320 .  
         [0038]     Another embodiment is described in  FIGS. 4 and 5 . The resource related input signals of these embodiments are chip select signals. Again, each module uses one chip select signal so that the remaining signals are shifted by one port position. The highest output port is then connected to a predefined signal source which is shown in  FIGS. 4 and 5  to be outside the respective module, but which may also be provided within the respective module.  
         [0039]     As described above, the resources are automatically assigned by allowing each module to take out as many resource related input signals as it needs and forward all remaining signals, being shifted, to the next upper module.  
         [0040]      FIG. 6  illustrates an example where the module  600  takes out two resource related input signals, and the remaining signals are shifted by two port positions. Further embodiments exist where three, four, five or more resource related input signals are used in each module.  
         [0041]     While it was discussed above that each module takes out the first signal(s), other embodiments may use the last signal(s). This is depicted in an embodiment in  FIG. 7 , where module  700  uses the last input signal and shifts the remaining input signals by one port position to the right. Thus, the first output port is then connected to a predefined signal source.  
         [0042]     It is noted that in other embodiments, other predefined port positions may be used by the modules, even if these ports are located somewhere in the middle.  
         [0043]     The above-discussed embodiments may for instance be used for assigning resources which require a point-to-point connection in stacked bus systems. It is to be noted that such resources are not restricted to clocks and chip selects, but may include any other point-to-point connection.  
         [0044]     As discussed above, all of the modules are of the same construction in the described examples. This allows same circuitry to be duplicated for all memory interfaces, thereby allowing the implementation of any combination of memory banks in composite devices. A 2-wire configuration EEPROM (Electrically Erasable Programmable Read-Only Memory) may be used to describe the memory banks. The software can then discover the resource assignment in effect.  
         [0045]     While the above embodiments have discussed clock signals, chip select signals and other point-to-point resources, further embodiments may use address signals as resource signals to allow a configuration-free address allocation for stacked modules in bus systems or other stacked module devices. As will be described in more detail below, the embodiments allow for distributing addresses to stacked modules with or without logical gates, particularly with only a single gate and/or with low additional efforts.  
         [0046]     Generally, every module may have n address input bits a 0  to a n-1  and the same number of address output bits b 0  to b n-1  where the output b 0  to b n-1  may be calculated by a logical function and where the input address [a 0 , a n-1 ] or the output address [b 0 , b n-1 ] is used as an address on the current stack.  
         [0047]     For instance, referring to  FIGS. 8 and 9 , the module  800  receives three input address signals forming an input address. The module  800  uses this input address in the stack. Further, the module has a logic  810 , which has in the embodiment zero or one logic gate, to generate an output address from the input address. The output address is then provided to the next upper module.  
         [0048]     The embodiment of  FIG. 9  differs from that of  FIG. 8  in that the model  900  does not use the input address by itself, but the output address.  
         [0049]     As will be described in more detail below, when shifting address lines and using a single gate, up to seven modules can get individual addresses in a three-bit address bus. The amount of distinguishable modules depends on the kind of gate used. In the three-bit address bus example, four addresses may be distinguished when not using any logical gate, six addresses may be distinguished when using a NOT gate, and seven addresses may be used when having an XOR or XNOR gate.  
         [0050]     Discussing first an embodiment where logic  810 ,  910  is a binary adder, the address is incremented by one from module to module. For a three-bit address bus, the use of an adder logic may then lead to eight individually addressable modules.  
         [0051]     A much more simple implementation is shown in  FIG. 10 , where the logic  810  has no logical gate. Rather, the second input address bit is sent to the first output address port, the third input address bit is forwarded to the second output address port, and the third output port is connected to a predefined signal source.  
         [0052]     The (binary and decimal) addresses resulting from the arrangement of  FIG. 10  for each stack position is shown in the following table (assuming the most significant bit to be present at the first port):  
                                       Stack               position   Address bin   Address dec                   1   000   0       2   001   1       3   011   3       4   111   7                  
 
         [0053]     The bit mapping performed by module  1000  shown in  FIG. 10  between the input address and the output address is given in the following table:  
                                                                                 Address in   Address out                a 2     a 1     a 0     b 2     b 1     b 0                         0   0   0   0   0   1           0   0   1   0   1   1           0   1   1   1   1   1           1   1   1   1   1   1                      
 
         [0054]     The corresponding function equations for module  1000  are given by the following formulas: 
 
AD 0 =a 0  
 
AD 1 =a 1  
 
AD 2 =a 2  
 
b 0 =1 
 
b 1 =a 0  
 
b 2 =a 1  
 
         [0055]     Where AD i  denotes the address bits provided by the host board.  
         [0056]     Referring now to  FIG. 11 , a module  1100  is shown having a single NOT gate  1110 . As discussed with reference to  FIG. 10 , the address bits received at the second and third input ports are shifted by one port position. However, the remaining output port is supplied with the inverted bit received at the first input port. This leads to the following address assignment:  
                                       Stack               position   Address bin   Address dec                   1   000   0       2   001   1       3   011   3       4   111   7       5   110   6       6   100   4                  
 
         [0057]     The corresponding address bit mapping is shown in the following table:  
                                                                                 Address in   Address out                a 2     a 1     a 0     b 2     b 1     b 0                         0   0   0   0   0   1           0   0   1   0   1   1           0   1   1   1   1   1           1   1   1   1   1   0           1   1   0   1   0   0           1   0   0   0   0   0                      
 
         [0058]     The function equations for the described module having a single NOT gate is as 
 
AD 0 =a 0  
 
AD 1 =a 1  
 
AD 2 =a 2  
 
b 0 ={overscore (a 2 )}
 
b 1 =a 0  
 
b 2 =a 1  
 
         [0059]      FIG. 12  shows another embodiment where the module  1200  has an XOR gate  1210 . The resulting stack addresses and address functions are the following:  
                                       Stack               position   Address bin   Address dec                   1   001   1       2   011   3       3   111   7       4   110   6       5   101   5       6   010   2       7   100   4                    
         [0060]    
       
         
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                   
               
               
                   
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                 a 1   
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                 b 1   
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         [0061]     A similar result is achieved by using an XNOR gate  1310  in the module  1300  shown in  FIG. 13 .  
                                       Stack               position   Address bin   Address dec                   1   000   0       2   001   1       3   010   2       4   101   5       5   011   3       6   110   6       7   100   4                  
 
         [0062]    
       
         
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                   
               
               
                   
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                 a 2   
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                 a 0   
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                 b 1   
                 b 0   
               
               
                   
                   
               
               
                   
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         [0063]     Thus, when having no logical gate, four modules can be distinguished. Using a NOT gate, six modules can be distinguished. Using an XOR or XNOR gate, seven modules can be distinguished, and using an adder logic, up to eight modules can be individually addressed.  
         [0064]     In any of the above embodiments, the number of resource related input signals, such as the number of address bits, may be arbitrarily chosen and may in particular differ from the number of modules. Further, in the arrangements of FIGS.  8  to  13 , it is possible to have the least significant bits at the highest port positions while having the most significant bits at the lowest port positions, but other embodiments may have other port assignments.  
         [0065]     In an embodiment, the number of modules is chosen not to exceed two to the power of the number of address bits, in order to allow each module to get assigned a unique address.  
         [0066]     Further, in any of the above embodiments, a 2-wire configuration EEPROM may be used. This may allow for an automatic chip select/clock assignment for all memory interfaces, and for an automatic 2-wire address generation. Further, embodiments may exist where software can determine the stacked configuration from the 2-wire EEPROMs, and the software can then adjust memory controller settings based on parameters read from the 2-wire EEPROMs.  
         [0067]     In a further embodiment, there may be provided an I/O (input/output) expander that may use the same 2-wire address as the EEPROM. The I/O expander may be combined with the 2-wire EEPROM. In an embodiment, after reset, all input and output ports are high, i.e., the addresses are set to zero. The bottom-most module then replies to the 2-wire address zero while all other modules reply to 2-wire address seven.  
         [0068]      FIG. 14  depicts a flow chart that may be used for software configuration. After reset is detected in step  1400 , the software detects in step  1410  whether the bottom-most module exists. If so, the I/O expander which may be an 8-bit I/O expander, is configured in step  1420  to drive an upper-side address of one. The second module will then respond to the address one, and the software can then configure this module to provide an output address of two. By reiterating, the software continues assigning incremented addresses until it reaches the end of the stack. This may be a process which is executed once after hardware reset.  
         [0069]     While the invention has been described with respect to the physical embodiments constructed in accordance therewith, it will be apparent to those skilled in the art that various modifications, variations and improvements of the present invention may be made in the light of the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. In addition, those areas in which it is believed that those of ordinary skill in the art are familiar, have not been described herein in order to not unnecessarily obscure the invention described herein. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrative embodiments, but only by the scope of the appended claims.