Abstract:
A CMOS buffer is disclosed having a reference potential that provide TTL logic response. The circuit is configured to draw substantially zero current. A reference potential generator develops a potential that is one N channel transistor threshold above about 1.2 volts for TTL compatibility. A single reference potential generator will provide a potential for a plurality of buffers so that its dissipation is low and is shared among the buffers. The result is a low power buffer circuit that is compensated for variations in supply voltage, temperature and device parameters.

Description:
BACKGROUND OF THE INVENTION 
     Complementary metal oxide semiconductor (CMOS) integrated circuit structures employ complementary insulated gate field effect transistor (IGFET) devices to perform the active circuit functions. The structures involved can also include active bipolar junction transistor (BJT) devices. In a typical prior art CMOS input buffer the usual approach is to employ a conventional inverter having the N channel and P channel devices ratioed to provide the desired switching threshold. The TTL logic levels of 0.8 volt or below for a logic low and 2 volts or above for a logic high are such that for a logic high input both inverter transistors will normally conduct and therefore dissipate power. Regenerative circuit elements can be added to the inverter to aid in logic level discrimination, but these too dissipate power. When the circuit application calls for a large number of input buffers the power dissipation can become a significant problem. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a CMOS buffer that can discriminate between TTL logic levels and dissipate very little power. 
     It is a further object of the invention to provide a CMOS buffer that provides a large output signal swing and discriminate between TTL logic levels while dissipating very little power. 
     These and other objects are achieved in the following manner. The circuit input terminal is coupled to the source of a common gate transistor, which has its gate returned to a source of reference potential, and to the gate of a common source transistor. These two transistors have their drains connected to the drains of complementary load transistors which have their gates cross coupled to their respective drains in a latching configuration. The drain of the common source input transistor comprises the stage output terminal. For a logic high input the common source transistor will be turned on to provide a logic low output which turns the common gate transistor&#39;s load device on. The common gate transistor is biased to be turned off which turns the load for the common source transistor off. With a logic low input the common gate transistor is biased be turned on and the common source transistor will be off. This provides a logic high output which acts to turn off the common gate transistor&#39;s load transistor and turn on the common source transistor&#39;s load transistor. 
     The reference voltage supplied to the common gate transistor is achieved as follows. A totem pole output stage includes a current sink BJT coupled to a current source BJT with their juncture forming the reference voltage point. The sink transistor base is driven by a similar device diode connected to form a current mirror. The current source transistor base is also coupled to a similar device diode connected to form a current mirror therewith. The two mirrors are connected together through an N channel IGFET having its control electrode returned to the reference voltage point. Thus, the devices form a dual current mirror, the input current to which will determine the current flowing in the totem pole output stage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of the basic buffer circuit of the invention. 
     FIG. 2 is a schematic diagram of the circuit employed in developing the reference potential for the circuit of FIG. 1. 
     FIG. 3 is a schematic diagram of an alternative circuit for developing the reference potential. 
     FIG. 4 is a schematic diagram of the circuit of FIG. 2 with added transient arresting circuits. 
    
    
     DESCRIPTION OF THE INVENTION 
     FIG. 1, is a schematic diagram of the buffer circuit of the invention. An operating power supply V DD  is connected + to terminal 10 and - to ground terminal 11. Logic signals applied to input terminal 12 appear inverted at output terminal 13. A common source N channel IGFET 14 acts as an inverting amplifier responsive to the logic input. N channel IGFET 15 is connected as a common gate device that establishes the logic response level. The gate of transistor 15 is coupled to V REF  terminal 16 which is returned to a suitable source of potential which will be described in detail hereinafter. V REF  is typically one V TN  (one N channel transistor threshold) above the logic switching reference. V REF  =V TN  +1.2 for TTL logic. It will be noted that this reference level of 1.2 volts is well above the TTL logic low of 0.8 volt and well below the TTL logic high of 2 volts. 
     P channel IGFET&#39;s 17 and 18 respectively serve as loads for transistors 14 and 15. The gates of transistors 17 and 18 are cross coupled to their respective drains so as to create a regenerative or latching load action. 
     With a logic low at terminal 12 transistor 14 will be turned off and transistor 15 will be turned on. This will pull node 19 down so as to turn transistor 17 on. Thus, output terminal 13 will be close to +V DD . This action will turn off transistor 18. It can be seen that there is an off transistor in each of the branches of the circuit which therefore will draw no current. 
     In the logic high state at terminal 12 transistor 14 will be turned on and transistor 15 wil be turned off. This action will pull output terminal 13 close to ground and thereby turn transistor 18 on. This will pull node 19 close to +V DD  and turn off transistor 17. Again, each branch has an off transistor so the circuit will draw no current. 
     It will be noted that the back gate of transistor 15 is returned to ground. This will be the normal case in CMOS construction because all N channel IGFET&#39;s have their back gates in common on a P type semiconductor substrate which is connected to the negative supply rail. This back gate connection involves the well-known body effect in IGFET devices. When input terminal 12 is low, the body effect reduces the threshold of transistor 15 thereby aiding its turn on. When input terminal 12 is high, the body effect increases the threshold of transistor 15 thereby aiding its turn off. This body effect acts to increase the apparent gain of transistor 15 and accentuates its switching between the on and off states. 
     FIG. 2 is a schematic diagram of a preferred circuit for developing V REF  that is applied to terminal 16 of FIG. 1. It will be used where NPN BJT devices are available on the CMOS circuit chips. NPN transistors 20 and 21 are coupled in totem pole fashion between the power supply rails. Their juncture operates at the V REF  potential in the following manner. 
     P channel IGFET&#39;s 22 and 23 form a current mirror the input of which is developed by current flowing in resistor 24. For small current levels (relatively large resistor 24), this current will approximate: ##EQU1## where V TP  is the threshold voltage of a P channel transistor 
     R 24  is the resistance of resistor 24. If transistors 22 and 23 are the same size the same current will flow in transistor 23 and the circuit elements connected in series therewith. NPN BJT 25 is diode connected to drive BJT 20 as a current mirror. BJT 26 is diode connected to drive BJT 21 as a current mirror. Typically transistors 20 and 21 are ratioed larger than transistors 25 and 26 so that the current flowing in transistors 20 and 21 is a multiple of I. 
     N channel IGFET 27 and resistor 28 are coupled in series with transistors 25 and 26 so that I flows in them also. The gate of IGFET 27 is returned to V REF  terminal 16 to create a stabilizing negative feedback loop in the control circuit. The base of transistor 20 will be V BE  above V REF . Since transistor 25 will have the same V BE  node 29 will also be at V REF . Thus, node 30 will be approximately V TN  (one N channel IGFET threshold) below V REF . Node 30 will be at a potential: 
     
         V.sub.30 =V.sub.BE26 +IR 28 
    
     where: 
     V BE26  is the base to emitter voltage of transistor 26 
     R 28  is the value of resistor 28 
     Since resistor 28 is ratioed to resistor 24 and resistor 24 sets the current level I, the voltage drop across resistor 28 is relatively constant and independent of process variation. In effect, the voltage drop across resistor 28 in combination with the V BE  of BJT 26 determines the voltage at node 30 and V REF  =V 30  +V TN . 
     While the V REF  circuit of FIG. 2 draws current the actual value can be kept small and a single such circuit can provide a reference potential for a plurality of buffers of the kind disclosed in FIG. 1. In the example to be given sixteen such buffers will be coupled to one reference circuit. 
     FIG. 3 is a schematic diagram of an all IGFET version of the reference circuit. This circuit form will be used where the CMOS circuit chips do not include NPN BJT&#39;s. Transistors 20, 21, 25 and 26 of FIG. 2 have been replaced by N channel IGFET&#39;s 32 through 35 respectively. The circuit operates as explained above except that V TN  will replace V BE . 
     It can be seen from FIG. 1 that the logic signals applied to terminal 12 will be coupled to terminal 16 via the gate to source capacitance of transistor 15. When a plurality of such buffers are commonly coupled to a single reference circuit the resulting logic signal transients can be substantial. FIG. 4 shows a version of the FIG. 2 circuit modified to reduce the effects of such transients. Resistor 36 is coupled between the collector and base of transistor 26 and capacitor 37 is coupled between the base and collector of transistor 21. Resistor 38 is coupled between the gates of transistors 22 and 23 and capacitor 39 is coupled from the gate of transistor 23 to the gate of transistor 27. These transient suppressing R.C. networks render terminal 16 substantially immune to the logic switching transients. 
     Example 
     The circuits of FIGS. 1 and 2 were simulated to determine the effects of transistor parameters, temperature and V DD . The simulation employed a program that has been highly successful in predicting the behavior of CMOS circuits. Sixteen buffers were coupled to a single reference generator. The following component values were employed. 
     
         ______________________________________COMPONENT      VALUE*         UNITS______________________________________Transistor 14  85/2           micronsTransistor 15  140/2          micronsTransistor 17  25/2           micronsTransistor 18  15/2           micronsTransistors 22 and 23          450/4          micronsResistor 24     23K           ohmsTransistor 27  140/2          micronsResistor 28    6.5K           ohms______________________________________ *The dual numbers are W/L ratios. 
    
     The NPN transistors were of high Beta construction and transistors 20 and 21 were ratioed at 5 times the size of transistors 25 and 26. V DD  was varied from 4.5 to 5.5 volts, temperature was varied from -40° C. to +120° C., and transistor parameters were varied over the extreme ranges normally encountered in processing. The buffer propagation delay varied over 2 to 7 ns. The quiescent current was 1.2 ma maximum. By contrast prior art buffers for similar speed performance typically draw about 1.5 ma which would translate to 24 ma for sixteen such circuits. Thus, the circuit of the invention produces a twenty times improvement in dissipated power. 
     The invention has been described and an operating example detailed. When a person of ordinary skill in the art reads the foregoing description, alternatives and equivalents, within the spirit and intent of the invention, will be apparent. Accordingly, it is intended that the scope of the invention be limited only by the claims that follow.