Abstract:
A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of U.S. Provisional Application 61/155,801 filed on Feb. 26, 2009, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     This present application relates generally to semiconductor devices, and more particularly to memory arrays, and even more particularly to the design and operation of static random access memory (SRAM) arrays and/or register files that use single ended sensing to sense the data in a bit cell. 
     BACKGROUND 
     Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a data bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a data bit into a selected SRAM cell or reading a stored data bit from the selected SRAM cell. 
     A register file is an array of processor registers in a central processing unit (CPU). Integrated circuit-based register files are usually implemented by way of fast SRAMs with multiple ports. Such SRAMs are distinguished by having dedicated read and write ports, whereas ordinary multi-ported SRAMs will usually read and write through the same ports. 
     With the scale of integrated circuits decreasing, the operation voltages of integrated circuits are reduced and similarly the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which are used to measure how reliable the data bits of the SRAM cells can be read from and written into, respectively, are reduced. Due to the existence of static noise, the reduced read and write margins may increase the possibility of errors in the respective read and write operations. 
     For single ended sensing of a memory cell, the precharged local bit-line either stays at the precharged level or it is discharged to ground level depending on the data that is stored in the bit-cell. When the local bit-line is kept floating during the case where the cell does not have the data value to discharge the local bit-line, the leakage from the pass gates (all cells in one column) discharges the local bit-line to zero during low frequency operation, thus making a false sensing. To avoid this false sensing issue, the local bit-line is kept at Vdd through a weak (small current) precharger device, i.e. a “keeper” circuit. 
       FIG. 1  illustrates a conventional sense amplifier circuit  100  that can be a portion of a SRAM array or register files, and includes a keeper circuit  102 . The size of components of the keeper  102  is very critical in order to assure that the bit-cell overpowers the keeper  102  for a normal read operation. The circuit  100  is connected to bit-lines, i.e. top bit-line  108   a  and bottom bit-line  108   b . The precharger  110  charges the local bit-line  108   a  and  108   b  to high state according to the control signals  114  when there is no read operation. During manufacturing of the memory as disclosed in  FIG. 1 , there are acceptable variations in performance parameters. Process corners refer to integrated circuits with lowest and/or highest desirable performance parameters. Skew corners refer to integrated circuits with both lowest and highest desirable performance parameters in their sub-circuits. At low voltages, and skew corners (e.g. slow array transistors in bit-line  108   a  or  108   b  and fast periphery transistors in a keeper  102 ), the bit-cell connected to the bit-line  108   a  or  108   b  will not be able to overpower this keeper  102 . Therefore, there is a limitation on the lowest desirable power supply voltage, i.e. Vdd_min, for the circuit to operate without error. 
     One way to make this circuit  100  work properly under low voltage is to increase the resistance of the keeper  102 , such as increasing the channel length of the keeper transistor  104  or decreasing the width of the same. This will make the keeper  102  easier to be overcome by the bit-cell connected to the bit-line  108   a  or  108   b . However, this method has its limits due to the area that the keeper transistor  104  occupies and also the current flow level necessary for the keeper  102  to provide the leakage current from the pass gates and thus make it operational. 
     Another way to make the circuit  100  operational under low voltage is to make the trip point voltage of the NAND gate  106  higher, where the trip point is the highest voltage where the sense amplifier output switches from a high level to a low level. For that purpose, for example, when the NAND gate  106  comprises NMOS and PMOS, the value of β of the NAND gate  106  can be increased, where β is the ratio of Wp/Wn, and Wp and Wn are the gate widths of PMOS transistor and NMOS transistor, respectively. This ratio β determines the trip point in CMOS circuits. However, this will make the circuit  100  susceptible to noise closer to the high state voltage because the trip point is higher. For example, when there is noise in the bit-line  108   a  or  108   b  close to a high state, the output voltage could be lowered by the noise below the trip point of the NAND gate  106 , which triggers an erroneous operation. 
     Therefore, methods to avoid false sensing the local bit-line under low voltage for SRAM and/or register files are desired. 
     SUMMARY 
     A sense amplifier scheme for SRAM is disclosed. In accordance with one aspect of the present invention, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit (or a sense amplifier receiver). The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output. The trip point is the highest voltage where the sense amplifier output switches from a high level to a low level. 
     In one embodiment, the gate node of the NMOS transistor in the keeper circuit is connected to the power supply node and its source node is connected to the bit line. The drain node of the NMOS transistor can be connected to the power supply node through a feedback PMOS transistor. In another embodiment, the gate and drain node of the NMOS transistor are connected to the power supply node and its source node is connected to the bit line through a PMOS transistor. In yet another embodiment, the drain node of the NMOS transistor that is configured as a diode by connecting its gate and drain node of the NMOS transistor, is connected to the power supply node through a PMOS transistor. The source node of the NMOS transistor can be connected to the bit line. 
     In another embodiment, the source node of the NMOS transistor is connected to the power supply node through a PMOS transistor and its drain node is connected to the bit line. The gate node of the NMOS transistor can be connected to the power supply node or to the source node of the NMOS transistor. 
     In one embodiment, the noise threshold control circuit (or a sense amplifier receiver) can be a half-Schmitt trigger circuit or a Schmitt trigger circuit. However, the specific embodiments discussed are merely illustrative of specific ways to implement the invention, and do not limit the scope of the invention. A skilled person will appreciate other alternative ways of implementations. 
     In accordance with another aspect of the present invention, a memory circuit includes a SRAM array, which includes a sense amplifier circuit described here. The memory circuit can also be a part of register files or another circuit, device, and/or system. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic diagram of a conventional sense amplifier circuit; 
         FIG. 2  is a schematic diagram of a sense amplifier circuit according to one embodiment of the present disclosure; 
         FIG. 3  is a schematic diagram of a half-Schmitt trigger circuit for used as an exemplary noise threshold control circuit  206  in  FIG. 2 ; 
         FIG. 4  is a graph of the output of the bit-line read/sense amplifier/read showing a trip point or the voltage at which the sense amplifier receiver switches with the same bit-line slope for (1) a prior art circuit with β=3.3, (2) a prior art circuit with β=16.7, and (3) a proposed circuit according to one embodiment of the disclosure with β=3.3; 
         FIG. 5  is a graph of the output of the bit-line read/sense amplifier/read showing the bit-line slopes for (1) a prior art circuit with β=3.3, (2) a prior art circuit with β=16.7, and (3) a proposed circuit according to one embodiment of the disclosure with β=3.3, with different bit-line voltage lines for prior art circuit and the proposed circuit; 
         FIG. 6  is a schematic diagram of another embodiment of the sense amplifier circuit according to one aspect of the present disclosure; 
         FIG. 7A  is a schematic diagram of yet another embodiment of the sense amplifier circuit according to the present disclosure; 
         FIG. 7B  is a schematic diagram of an variation of the sense amplifier circuit according to the embodiment depicted in  FIG. 7A ; and 
         FIG. 8  is a schematic diagram of yet another embodiment of the sense amplifier circuit according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The circuits of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. A skilled person will appreciate alternative implementations. 
       FIG. 2  is a schematic diagram of a sense amplifier circuit  200  according to one embodiment of the present invention. The sense amplifier circuit  200  has a keeper circuit  202 . The circuit  200  is connected to bit-lines, i.e. top bit-line  208   a  and bottom bit-line  208   b . The precharger  210  charges the local bit-line  208   a  and  208   b  to a high state according to the control signals  214  when there is no reading operation. 
     Further, the keeper circuit  202  has NMOS transistors  204  and a noise resistant NAND gate  206 . In this particular example, the gate node of the NMOS transistor  204  in the keeper circuit  202  is connected to the power supply node and its source node is connected to the bit line. The drain node of the NMOS transistor  204  is connected to the power supply node through a PMOS transistor. The NMOS  204  is only in sub-threshold until the bit-line read voltage reaches V dd -V T , where V T  is the threshold voltage of the transistor, thus effectively making the keeper circuit  202  weaker, i.e. easier to be overcome by the bit-line as its voltage decreases. In one embodiment, the noise resistant NAND gate  206  (or a noise threshold control circuit) is a half-Schmitt trigger; in another embodiment, the noise resistant NAND gate  206  is a Schmitt trigger as depicted in  FIG. 2 . However, in alternative embodiments, alternative circuits may be formed by rearranging the devices so that the β ratio is decreased or the trip point is lowered. 
       FIG. 3  is a schematic diagram of one example of the noise threshold control circuit  206  as indicated by NAND gate symbol in  FIG. 2 , using a half-Schmitt trigger circuit. 
     By lowering the trip point of the sense amplifier out, it is possible to use a lower precharge voltage level on the bit-line and avoid false sensing of the bit-line read. The trip point is the highest voltage where the sense amplifier output switches from a high level to a low level. The response time of the bit-line to output is reduced because of the improved bit-line slope of the new circuit design. The response time of the sense amplifier output is faster due to the new scheme. Further, in at least some embodiments, the local bit-line is precharged to V dd -V T , instead of V dd . 
     The keeper circuit  204  using NMOS transistors as shown in  FIG. 2  make the keeper circuit  202  effectively weaker, i.e. easier to overcome by the bit-line. However, this in turn can make the prior art circuit susceptible to noise when there are voltage fluctuations on the bit-line  108   a  or  108   b . To avoid the noise susceptibility, a noise threshold control circuit  206 , e.g. a half-Schmitt trigger or a Schmitt trigger circuit is used in place of the prior art NAND gate  106 . This scheme makes it possible to perform the bit-line read operation without false sensing at lower power voltage by having a lower trip point. 
       FIG. 4  is a graph of the trip point or the voltage at which the sense amplifier receiver switches with the same bit-line slope for (1) a prior art circuit with β=3.3, (2) a prior art circuit with β=16.7, and (3) a proposed circuit with β=3.3. The bit-line read plot is based on the prior art circuit  100  shown in  FIG. 1 . In  FIG. 4 , the prior art circuit  100  with β=3.3 has the trip point at point (1). The prior art circuit  100  with β=16.7 has the trip point at point (2). The purpose of increased β is to make the keeper circuit  102  weaker so that the bit-line read can overcome the keeper circuit  102  at lower power supply voltage. As shown in  FIG. 4 , the trip point (2) is higher than trip point (1). In one circuit simulation under the power supply voltage of 0.7V according to one of the embodiments, the difference is about 34 mV. However, by increasing the trip point, the sense amplifier output is susceptible to the bit line read voltage fluctuations caused by noise. This makes the prior art circuit difficult to operate at lower voltage. In comparison, the proposed circuit  200  with β=3.3 according to one of the embodiments has trip point at point (3). The trip point (3) is lower than (1) or (2). In the simulation under the power supply voltage of 0.7V, the difference between (3) and (1) is about 77 mV, and the difference between (3) and (2) is about 111 mV. This makes the proposed circuit easier to operate at lower voltage. Also, in another simulation with the power supply voltage of 0.6V, both sense amplifier circuits according to prior art do not work at all, i.e. the sense amplifier outputs do not switch when the bit-line voltage dropped, while the proposed circuit operates properly. 
       FIG. 5  is a graph of the output of the bit-line read/sense amplifier/read showing the bit-line slopes for (1) a prior art circuit with β=3.3, (2) a prior art circuit with β=16.7, and (3) a proposed circuit with β=3.3, with different the bit-line voltage lines for prior art circuit and the proposed circuit.  FIG. 5  shows a separate bit-line read voltage plot for the circuit  200  according to one of the embodiments. The same bit-line read voltage based on the prior art circuit  100  shown in  FIG. 1  is shown to facilitate understanding. As shown, the prior art circuit with β=16 has a shorter response time (the time where the trip point (2) is positioned) compared to the response time of point (1) of the prior art circuit  100  with β=3.3. However, the proposed circuit response time (the time where the trip point (3) is positioned) is even shorter than the prior art with β=16.7 (the time where the trip point (2) is positioned). In one simulation under the power supply voltage of 0.7V, the difference between (3) and (1) is about 0.9 ns, while the difference between (3) and (2) is about 0.2 ns. 
       FIG. 6  is a schematic diagram of another embodiment of the sense amplifier circuit  600  according to the present disclosure. In this embodiment, the NMOS  604  transistor in the keeper circuit  602  is configured as a diode by connecting its gate and drain node of the NMOS transistor  604 . The drain node of the NMOS transistor  604  is connected to the power supply node Vdd through a PMOS transistor  606 . The source node of the NMOS transistor  604  is connected to the bit line  208   a  and/or  208   b.    
       FIG. 7A  is a schematic diagram of yet another embodiment of the sense amplifier circuit  700  according to the present invention. In this embodiment, the gate and drain node of the NMOS transistor  704  in the keeper circuit  702  are connected to the power supply node Vdd and its source node is connected to the bit line  208   a  and/or  208   b  through a PMOS transistor  706 . 
       FIG. 7B  is a schematic diagram of a variation of the sense amplifier circuit show in  FIG. 7A . In this embodiment, the gate and drain node of the NMOS transistor  714  in the keeper circuit  712  are connected to the power supply node Vdd and its source node is connected to the bit line  108   a  and/or  108   b  through a PMOS transistor  716 . 
       FIG. 8  is a schematic diagram of yet another embodiment of the sense amplifier circuit  800  according to the present disclosure. In this embodiment, the source node of the NMOS transistor  804  in the keeper circuit  802  is connected to the power supply node through a PMOS transistor  806  and its drain node is connected to the bit line  208   a  and/or  208   b . The gate node of the NMOS transistor  804  is connected to the power supply node Vdd. According to this embodiment, the noise threshold control circuit  808  including strong NMOS transistors  810  are connected in parallel to conventional NAND gate  206  to lower the trip point of the sense amplifier output  212  by effectively lowering the value of β of the NAND gate  206 . 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, a single bit line circuit instead of a pair of bit-line circuit as shown in  FIGS. 2-3 ,  6 - 9  can use an inverter with a single input and output instead of NAND gates with two inputs. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the invention described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, any development, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such developments.