Abstract:
Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage generator to adjust the reference voltage without handling the core voltage in response to a test signal of a test mode, and a voltage generator for generating a bit-line precharging voltage and/or a cell plate voltage in accordance with the reference voltage.

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention is related to a voltage regulation circuit and method of regulating the voltage and particularly, to a voltage regulation circuit and method of regulating the voltage, capable of generating an optimized bitline precharge voltage and cell plate voltage with regulating a reference voltage without handling the core voltage by controlling a reference voltage generator to adjust the reference voltage in response to a control signal in a test mode. 
   2. Discussion of Related Art 
   A bitline precharge voltage is connected to a bitline and used to initialize the bitline in a standby mode of a DRAM, while a cell plate voltage is connected to a plate of a capacitor of a DRAM cell and used to restrain a leakage current by reducing a difference of voltage levels crossing both ends of a cell transistor. 
     FIG. 1  is a diagram of a conventional voltage regulating circuit generating the bitline precharge voltage and the cell plate voltage. 
   A reference voltage generator  11  composed of first and second resistors, R 11  and R 12 , in the same size generates a reference voltage Vref of (½)VCORE by dividing a core voltage VCORE during an active mode. A bitline precharge voltage generator  12  and a cell plate voltage generator  13  input the reference voltage Vref and each output a bitline precharge voltage VBLP and a cell plate voltage VLP. 
   With the bitline precharge voltage generator  12  and the cell plate voltage generator  13 , the reference voltage Vref is variable when the core voltage VCORE changes, which makes the bitline precharge voltage VBLP and the cell plate voltage VLP be variable. However, there is a disadvantage that is not able to adjust the bitline precharge voltage VBLP and the cell plate voltage VLP when the core voltage VCORE maintains a constant voltage level. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to a voltage regulation circuit and method of regulating the voltage, capable of regulating a bitline precharging voltage and cell plate voltage with regulating a reference voltage without handling the core voltage by controlling a reference voltage generator in response to a control signal in a test mode. 
   One aspect of the present invention is to provide a voltage regulating circuit comprising: a reference voltage generator outputting a reference voltage from dividing a core voltage of a semiconductor memory device; a controller operating the reference voltage generator to regulate the reference voltage in compliance with a test signal in a test mode without adjusting the core voltage; and a voltage generator outputting a bitline precharge voltage and/or a cell plate voltage variable in response to the reference voltage. 
   The reference voltage generator makes the reference voltage in accordance with a ratio of resistors connected n series. 
   The controller includes: a first transistor increasing the reference voltage by inactivating one of the resistors of the reference voltage generator, being driven responding to a first test mode signal; and a second transistor decreasing the reference voltage by inactivating the other of the resistors of the reference voltage generator, being driven responding to a second test mode signal. 
   Another aspect of the present invention is to provide a voltage regulating circuit comprising: a reference voltage generator outputting a reference voltage from dividing a core voltage in accordance with a ratio of resistors connected between the core voltage terminal and a ground terminal; a first transistor increasing the reference voltage by inactivating one of the resistors which is connected to the core voltage terminal without adjusting the core voltage; a second transistor decreasing the reference voltage by inactivating the other of the resistors which is connected to the ground terminal without adjusting the core voltage; and a voltage generator outputting a bitline precharge voltage and/or a cell plate voltage variable in response to the reference voltage. 
   Further, the present invention provides a method of regulating a voltage, comprising: generating a bitline precharge voltage and/or a cell plate voltage with using a reference voltage provided from a reference voltage generator in response to a core voltage; increasing the reference voltage by controlling the reference voltage generator in response to a first test mode signal without adjusting the core voltage and increasing the bitline precharge voltage and/or the cell plate voltage with using the increased reference voltage; and decreasing the reference voltage by controlling the reference voltage generator in response to a second test mode signal without adjusting the core voltage and decreasing the bitline precharge voltage and/or the cell plate voltage with using the decreased reference voltage. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings: 
       FIG. 1  is a diagram of a conventional voltage regulating circuit; 
       FIG. 2  is a diagram of a voltage regulating circuit in accordance with the present invention; 
       FIG. 3  is a waveform diagram of the voltage regulating circuit in accordance with the present invention; 
       FIG. 4  is a diagram of a voltage regulating circuit in accordance with another embodiment of the present invention; and 
       FIG. 5  is a diagram of a voltage regulating circuit in accordance with still another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout the specification. 
   Hereinafter, it will be described about an exemplary embodiment of the present invention in conjunction with the accompanying drawings. 
     FIG. 2  is a diagram of a voltage regulating circuit in accordance with the present invention. 
   A controller  21  is composed of a PMOS transistor P 21  connected between a terminal of a core voltage VCORE and a first node Q 21  and driven by an output signal of an inverter  121  inversing a test mode voltage-up signal tm_up, and an NMOS transistor N 21  connected between a second node Q 22  and a ground terminal VSS and driven by a test mode voltage-down signal tm_down, which varies a resistance value by altering a current path from a reference voltage generator  22 . 
   The reference voltage generator  22  is constructed of plural resistors, e.g., first through fourth resistors R 21 ˜R 24 , establishing a reference voltage Vref at a third node Q 23  in accordance with resistance ratios of the first and second resistors, R 21  and R 22 , and of the third and fourth resistors R 23  and R 24 . Here, the sum of the first and second resistors R 21  and R 22  is as same as that of the third and fourth resistors R 23  and R 24 . The reference voltage Vref is variable because the first or fourth resistor, R 21  or R 24 , can be inactive by the controller  21 . 
   The bitline precharge voltage generator  23  and the cell plate voltage generator  24  input the reference voltage Vref and then output the bitline precharge voltage VBLP and the cell plate voltage VCP. 
   It will be now described about the operation of the voltage regulating circuit for controlling the bitline precharge voltage and the cell plate voltage in accordance with the present invention. 
   If the test mode voltage-up signal tm_up and the test mode voltage_down signal tm_down are applied with a logical low in a normal state, the test mode voltage-up signal of a low state is inversed to a high state by an inverter I 21  and thereby the PMOS transistor P 21  is turned off. And, the test mode voltage-down signal tm_down of a low state turns the NMOS transistor N 21  off. Thus, the reference voltage generator  22  outputs the reference voltage Vref of (½)VCORE from dividing the core voltage VCORE with the ratios of the first and second resistors R 21  and R 22 , and of the third and fourth resistors R 23  and R 24 . The reference voltage Vref is supplied to the bitline precharge voltage generator  23  and the cell plate voltage generator  24  to set the bitline precharge voltage VBLP and the cell plate voltage VCP those are leveled on (½)VCORE. 
   In elevating the bitline precharge voltage VBLP and the cell plate voltage VCP with maintaining the core voltage VCORE constant, when the test mode voltage-up signal tm_up is applied with a high state and the test mode voltage-down signal tm_down is applied with a low state, the test mode voltage-up signal of a high state is inversed to a low state by an inverter  121  and thereby the PMOS transistor P 21  is turned on. And, the test mode voltage-down signal tm_down of a low state turns the NMOS transistor N 21  off. As the PMOS transistor P 21  is turned on, the first resistor R 21  becomes inactive. The reference voltage generator  22  outputs the reference voltage Vref higher than (½)VCORE from dividing the core voltage VCORE with the ratios of the first and second resistors R 21  and R 22 , and of the third and fourth resistors R 23  and R 24 . The reference voltage Vref is supplied to the bitline precharge voltage generator  23  and the cell plate voltage generator  24  to set the bitline precharge voltage VBLP and the cell plate voltage VCP that are higher than (½)VCORE. 
   In falling the bitline precharge voltage VBLP and the cell plate voltage VCP with maintaining the core voltage VCORE constant, when the test mode voltage-up signal tm_up is applied with a low state and the test mode voltage-down signal tm_down is applied with a high state, the test mode voltage-up signal tm_up of a low state is inversed to a high state by an inverter  121  and thereby the PMOS transistor P 21  is turned on. And, the test mode voltage-down signal tm_down of a high state turns the NMOS transistor N 21  off. As the NMOS transistor N 21  is turned on, the fourth resistor R 24  becomes inactive. Thus, the reference voltage generator  22  outputs the reference voltage Vref lower than (½)VCORE from dividing the core voltage VCORE with the ratios of the first and second resistors R 21  and R 22 , and of the third and fourth resistors R 23  and R 24 . The reference voltage Vref is supplied to the bitline precharge voltage generator  23  and the cell plate voltage generator  24  to set the bitline precharge voltage VBLP and the cell plate voltage VCP that are lower than (½)VCORE. 
   As aforementioned, in the voltage regulating circuit according to the present invention, as shown in  FIG. 3 , the bitline precharge voltage VBLP and the cell plate voltage VCP are adjusted higher than (½)VCORE when the test mode voltage-up signal tm_up is applied with a high state and the test mode voltage-down signal tm_down is applied with a low state (A), while lower than (½)VCORE when the test mode voltage-up signal tm_up is applied with a low state and the test mode voltage-down signal tm_down is applied with a high state (B). 
     FIG. 4  is a diagram of a voltage regulating circuit in accordance with another embodiment of the present invention. 
   The controller  31  is composed of a PMOS transistor P 31  connected between a terminal of a core voltage VCORE and a first node Q 31  and driven by an output signal of an inverter  131  inversing a test mode voltage-up signal tm_up, and an NMOS transistor N 31  connected between a second node Q 32  and a ground terminal VSS and driven by a test mode voltage-down signal tm_down, which varies a resistance value by altering a current path from a reference voltage generator  32 . The reference voltage generator  32  is constructed of plural resistors, e.g., first through fourth resistors R 31 ˜R 34 , establishing a reference voltage Vref at a third node Q 33  in accordance with resistance ratios of the first and second resistors, R 31  and R 32 , and of the third and fourth resistors R 33  and R 34 . Here, the sum of the first and second resistors R 31  and R 32  is as same as that of the third and fourth resistors R 33  and R 34 . The reference voltage Vref is variable because the first or fourth resistor, R 31  or R 34 , can be inactive by the controller  31 . The bitline precharge voltage generator  33  inputs the reference voltage Vref and then outputs the bitline precharge voltage VBLP. 
     FIG. 5  is a diagram of a voltage regulating circuit in accordance with still another embodiment of the present invention. 
   The controller  41  is composed of a PMOS transistor P 41  connected between a terminal of a core voltage VCORE and a first node Q 41  and driven by an output signal of an inverter  141  inversing a test mode voltage-up signal tm_up, and an NMOS transistor N 41  connected between a second node Q 42  and a ground terminal VSS and driven by a test mode voltage-down signal tm_down, which varies a resistance value by altering a current path from a reference voltage generator  42 . The reference voltage generator  42  is constructed of plural resistors, e.g., first through fourth resistors R 41 ˜R 44 , establishing a reference voltage Vref at a third node Q 43  in accordance with resistance ratios of the first and second resistors, R 41  and R 42 , and of the third and fourth resistors R 43  and R 44 . Here, the sum of the first and second resistors R 41  and R 42  is as same as that of the third and fourth resistors R 43  and R 44 . The reference voltage Vref is variable because the first or fourth resistor, R 41  or R 44 , can be inactive by the controller  41 . The cell plate voltage generator  43  inputs the reference voltage Vref and then outputs the cell plate voltage VCP. 
   Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitution, modifications and changes may be thereto without departing from the scope and spirit of the invention. 
   As stated above, the present invention is able to adjust the bitline precharge voltage ad the cell plate voltage by regulating the reference voltage with controlling the reference generator in response to the test mode signals.