Abstract:
A voltage regulator including a comparing circuit, a first circuit, a transistor, a voltage reference circuit, and a latching circuit. The comparing circuit compares a first and second voltage references and generates an output based on the comparison. The first circuit amplifies the output of the comparing circuit. The transistor includes: a gate configured to receive a first output of the first circuit; a first terminal connected to a voltage supply terminal; and a second terminal. A regulated output voltage of the voltage regulator is based on a voltage at the second terminal. The voltage reference circuit generates the second voltage reference based on the voltage at the second terminal. The latching circuit, based on a second output of the first circuit: adjusts the second voltage reference; and switches between forcing the second output of the first circuit to be in a first state to be in a second state.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present disclosure is a continuation of U.S. patent application Ser. No. 14/190,729 (now U.S. Pat. No. 8,952,747), filed Feb. 26, 2014. This application claims the benefit of U.S. Provisional Application No. 61/770,701, filed on Feb. 28, 2013. The entire disclosure of the application referenced above is incorporated herein by reference. 
    
    
     FIELD 
     The present disclosure relates to voltage regulators, and more particularly to non-linear voltage regulators. 
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     Voltage regulators receive an input voltage reference and supply an output voltage reference to another circuit such as a chip core or output drivers. While the input voltage reference may vary, the voltage regulator attempts to regulate the output voltage reference. For example, fluctuation of the output voltage reference may need to be regulated within a predetermined range of a predetermined voltage level. 
     The voltage regulator may be implemented by an integrated circuit (IC) along with the chip core and/or the output drivers. To perform voltage regulation, the voltage regulator usually requires a relatively large capacitor that is either attached externally to a pin of the IC or integrated in the IC. 
     SUMMARY 
     A voltage regulator includes a comparing circuit configured to compare a first voltage reference to a second voltage reference and to generate an output. A first circuit is configured to apply gain to the output of the comparing circuit and to buffer the output of the comparing circuit. A first transistor includes a gate in communication with an output of the first circuit, a first terminal in communication with a first voltage reference and a second terminal in communication with an output of the voltage regulator. A second circuit is configured to apply gain to the output of the first circuit and to buffer the output of the first circuit. A latching circuit is configured to receive an output of the second circuit. A voltage reference circuit is configured to generate the second voltage reference based on the output of the voltage regulator. A reference adjusting circuit is configured to receive an output of the latching circuit and to selectively adjust the second voltage reference. 
     In other features, a capacitor is connected to the output of the voltage regulator. The capacitor has a value in a range from 10 pF to 200 pF. 
     Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a functional block diagram and electrical schematic of an example of a voltage regulator according to the present disclosure. 
         FIG. 2  is a functional block diagram and electrical schematic of another example of a voltage regulator according to the present disclosure. 
         FIGS. 3A and 3B  illustrate the voltage regulator of  FIG. 2  in different states during operation. 
     
    
    
     In the drawings, reference numbers may be reused to identify similar and/or identical elements. 
     DESCRIPTION 
       FIG. 1  shows of an example of a voltage regulator  50  according to the present disclosure. The voltage regulator  50  may be implemented in an integrated circuit  51 . A voltage reference circuit  52  generates and outputs a first voltage reference V ref1  to a first input of a comparing circuit  54 . A second input of the comparing circuit  54  receives a second voltage reference V ref2 . The comparing circuit  54  compares the first voltage reference V ref1  to the second voltage reference V ref2  and generates a high or low signal based on the comparison. The second voltage reference V ref2  may be based on an output voltage of the voltage regulator  50 . 
     A buffer/gain circuit  58  applies gain and provides buffering to a signal output by the comparing circuit  54 . An optional level shifting circuit  62  may be used to adjust a signal level of the output of the buffer/gain circuit  58 . For example, the level shifting circuit  62  may shift a voltage level from a first voltage level to a second voltage level. 
     An output of the level shifting circuit  62  (or the buffer/gain circuit  58 ) is input to a gate of a transistor T 1 . A first terminal of the transistor T 1  is connected to a voltage reference V S . A second terminal of the transistor T 1  is connected to an output node of the voltage regulator V out . In some examples, the output node of the voltage regulator  50  is connected to a chip core, output drivers, etc.  64  and a capacitor C. The transistor T 1  is OFF when the output voltage V out  is above a target voltage level and ON when the output voltage V out  falls below the target voltage level. 
     An output of the buffer/gain circuit  58  is also connected to a buffer/gain circuit  66 , which applies gain and provides buffering to the output of the buffer/gain circuit  58 . The increased gain minimizes the possibility of a stable intermediate state and conditions the signal for input to a latching circuit  70 . The latching circuit  70  forces an output of the buffer/gain circuit  66  either high or low and prevents stable intermediate states between high or low. 
     An output of the latching circuit  70  is input to a reference adjusting circuit  74 . The output V out  of the voltage regulator  50  is fed back a voltage reference circuit  78 . The voltage reference circuit  78  and/or the reference adjusting circuit  74  set a value of the second voltage reference V ref2  supplied to the comparing circuit  54 . During one mode, the voltage reference circuit  78  sets the second voltage reference V ref2 , and during another mode, the voltage reference circuit  78  and the reference adjusting circuit  74  set the second voltage reference V ref2 . The reference adjusting circuit  74  helps to define an acceptable voltage range for the output voltage and to prevent the transistor T 1  from oscillating on and off. 
       FIG. 2  shows another example of a voltage regulator  100  according to the present disclosure. The voltage regulator  100  may be implemented in an integrated circuit. The voltage reference circuit  52  generates and outputs a first voltage reference V ref1  and outputs the first voltage reference V ref1  to the comparing circuit  54 . The comparing circuit  54  compares the voltage reference V ref1  to the second voltage reference V ref2  and generates a high or low signal based on the comparison. The comparing circuit  54  may include an amplifier or operational amplifier (opamp)  114  having an inverting input connected to the voltage reference V ref1  from the voltage reference circuit  52  and a non-inverting input connected to the second voltage reference V ref2 . 
     The second voltage reference V ref2  may be based on an output voltage of the voltage regulator  100 . The buffer/gain circuit  58  applies gain and provides buffering to the output of the comparing circuit  54 . The buffer/gain circuit  58  may include first and second inverters  118  and  122 , respectively, connected in series to an output of the comparing circuit  54 . An output of the second inverter  122  is connected to an input of the optional level shifting circuit  62  (when used) or to the gate of the transistor T 1 . The transistor T 1  may include a PMOS transistor. 
     The output of the buffer/gain circuit  58  is connected to the buffer/gain circuit  66 , which provides increased gain and buffering to the output of the buffer/gain circuit  58 . The buffer/gain circuit  66  may include first and second inverters  132  and  134  that are connected in series. 
     The latching circuit  70  is connected to the output of the buffer/gain circuit  66 . The latching circuit  70  forces the output of the buffer/gain circuit  70  either high or low and prevents intermediate states. The latching circuit  70  may include a first inverter  140  and a second inverter  144 . The second inverter  144  has an input connected to an output of the first inverter  142  and an output connected to the input of the first inverter  142 . 
     The output of the latching circuit  70  is input to the reference adjusting circuit  74 . The reference adjusting circuit  74  may include a resistor R 3 , an inverter  146 , and a transistor T 2 . The inverter  146  includes an input connected to a gate of the transistor T 2 . The transistor T 2  may include an NMOS transistor. One end of the resistor R 3  is connected to a first terminal of the transistor T 2 . A second terminal of the transistor T 2  is connected to a reference potential. Another end of the resistor R 3  is connected to the output-based voltage reference circuit  78 . 
     The output V out  of the voltage regulator  100  is fed back to the voltage reference circuit  78 . The voltage reference circuit  78  adjusts the output voltage V out  to a voltage that is comparable to the first reference voltage V ref1 . The voltage reference circuit  78  and the reference adjusting circuit  74  set a value of the second voltage reference V ref2  supplied to the comparing circuit  54 . The voltage reference circuit  78  may include a voltage divider circuit including first and second resistors R 1  and R 2 . 
     During one mode, the voltage reference circuit  78  sets the second voltage reference V ref2 , and during another mode, the voltage reference circuit  78  and the reference adjusting circuit  74  set the second voltage reference V ref2 . More particularly in  FIG. 2 , the resistor R 3  is selectively connected to the resistors R 1  and R 2  to adjust the second reference voltage V ref2  that is input to the comparing circuit  54 . 
       FIGS. 3A and 3B  illustrate the voltage regulator  100  of  FIG. 2  in different states.  FIG. 3A  illustrates the voltage regulator  100  when the second voltage reference V ref2  is less than the first voltage reference V ref1 . Example voltage reference levels are presented herein for purposes of illustration only. In this example, the voltage regulator is regulating to a target voltage level of 2.5V. The voltage supply is 3.3V. The voltage reference circuit  78  generates a 1.0V reference. When the output voltage is at 2.3V, the voltage reference circuit  78  generates a reference voltage of 0.99V and the voltage reference adjusting circuit  74  does not impact the second voltage reference V ref2 . 
     In this example, the output of the comparing circuit  54  is low. The transistor T 1  is ON and the output is pulled towards 3.3V. The optional level shifting circuit  62  is used to shift the voltage from 2.5V to 3.3V to allow the drive transistor T 1  to be turned ON and OFF. The input of the buffer/gain circuit  66  is low, which means that the output of the inverter  146  is high. The transistor T 2  is OFF. Therefore, the resistor R 3  is not connected to ground and does not affect the second voltage reference V ref2 . With the resistor R 3  disconnected in this manner, the second voltage reference is based on: 
     
       
         
           
             
               
                 
                   
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     In  FIG. 3B , eventually the output voltage is pulled higher than the target voltage level. The state of the comparing circuit  54  goes high, which changes the state of the transistor T 1  to off and the state of the transistor T 2  to on. With the resistor R 3  connected in this manner, the second voltage reference is based on: 
     
       
         
           
             
               
                 
                   
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     The voltage regulator turns on the transistor T 1  when the output voltage V out  falls below an acceptable level. To minimize the possibility that the output voltage V out  increases to an excessively high voltage, the feedback path including elements  54 ,  58 ,  62 ,  66 ,  70 ,  74  and  78  runs very fast. Digital elements in this path (elements  58 ,  66  and  70 ) provide high switching speed and low capacitive loading so that the overall path can respond very quickly. 
     The voltage regulators according to the present disclosure rely less upon large capacitors (typically about 1 μF to about 20 μF) and performs most of the smoothing inside the voltage regulator. As a result, the capacitor can be a factor of 10,000 times smaller while still supporting large supply currents. For example, the capacitor C may be about 10 pF to about 200 pF. Additional capacitors are not required for voltage regulation. Therefore, the capacitor can be implemented on-chip with significantly lower cost, reduced die size and without using an extra pin for an external capacitor. 
     The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure.