Abstract:
Presented is a circuit and method capable to digitally control and, in particular, to control the switching of one or two MOSFETs used as rectifiers in switched mode power supply isolated topologies. Basic circuit implementation of the presented technique is also introduced. A controller has a fixed frequency square wave signal main clock input, generically switching from a low to a high value in two different time intervals. The controller has one or two square wave outputs, swinging from low to high in phase or in opposite with respect to the clock signal. The digital control method is able to generate output signals timed to anticipate output transitions from high to low level with respect to the clock signal transitions. In the control scheme, one or two other secondary inputs set the amount of anticipation time of the respective transitions of the outputs. In isolated SMPS topologies with the PWM controller located on the primary side, the clock signal is derived from the secondary output of the isolation transformer, while the outputs are meant to drive one or two MOSFET gates. The method is able to provide the proper gate drive signals, solving all the known problems in controlling synchronous rectification.

Description:
TECHNICAL FIELD 
     This invention is directed toward switched mode power supplies, and more particularly, to a method and device for controlling synchronous rectifiers used within a switched mode power supply. 
     BACKGROUND OF THE INVENTION 
     In the power conversion area, especially in low DC output voltage converters, the utilization of MOSFETs as rectifiers is a technique increasingly used for the beneficial effect on efficiency due to the low conduction losses on these devices. 
     The way the synchronous rectifiers (SRs) are controlled is fundamental for the correct operation of the circuit. Proper techniques have therefore to be used to drive these SRs according to the law of the diode that the SR is meant to replace. This driving signal is derived from the main PWM control signal, which determines the different states of the switch mode circuit and therefore the operating conditions for the diodes of the circuit. 
     The way the driving signal can be derived from the main PWM signal to properly control SRs depends on the kind of topology used, and on the presence of voltage isolation in that topology. In a non-isolated switched mode power supply topology, the synchronous rectifier control circuit can get the information about the switching transitions (turn-off and turn-on) of the main switch from the main control circuit in a very simple way. 
     In isolated topologies with a primary side control, the absence of a PWM controlling signal on the secondary side of the isolation barrier makes the generation of the proper control signals for the SRs even more difficult. 
     If the equivalent diode law is not respected, the well known phenomena of cross conduction and shoot-through between switches will occur, as described in detail below. In all of these circumstances, one of the switches is forced to conduct in the first quadrant, opposite to its useful sense of conduction as a diode. Therefore, switching losses can become predominant, wasting most of the benefits introduced by the reduction of conduction losses by the rectifiers, or can even prevent proper operation of the circuit. 
     The required timing of the driving signal for the synchronous rectifier is shown in FIG. 2, having to a general switch mode topology configuration with one switch and only one diode, where the conduction times possible for switch and diode are complementary. 
     The dead time intervals shown in that figure prevent contemporary cross-conduction of the main switch and the SR, but they must be reduced to the lowest possible time value to minimize SR parasitic diode conduction times, and the consequent lost of efficiency. 
     In fact, an important issue in control of MOSFET SRs is related to the body-diode behavior. Physical MOSFETs used as SRs show, in fact, bad characteristics in terms of a parasitic diode, whose operation is involved at least during transitions between different states. 
     The operation of the body-diode is dependent on the timing of the driving signals, and in particular by the turn-off instant of the SR with respect to the time interval in which the diode (which has been replaced by a MOSFET SR) is supposed to be conducting. 
     A too early turn-off of the SR will cause an increase of conduction losses due to the body-diode drop which will therefore conduct all the current. The switching losses caused by the reverse recovery current of the body-diode will be dependent by the carried current at the instant in which the voltage between anode and cathode reverses, becoming negative. 
     In isolated topologies, if the main PWM is located on the secondary side, the task of driving synchronous rectifiers can be easily solved. In fact, because the PWM signal is available on the secondary side, it can be used to generate the driving signal for the SRs. Delays can be added to the PWM signal to compensate the propagation delays which are suffered by the driving signal transferred to the primary side through some coupling device. The required timing for this kind of operation is shown in FIG. 3, in the more general case of two complementary signals on the secondary side. Even in this application, dead times among driving signals are necessary to prevent eventual cross conduction between the SRs and between SRs and the main MOSFET. 
     However, secondary side control configuration shows several system disadvantages, such as requirement of an auxiliary power supply for startup of the converter, requirement of a crossing-isolation circuit able to transfer the PWM control driving signal to primary switches, and difficulties to transfer the information about the primary switch current to the PWM controller in current mode control loops. Therefore, the use of PWM control on the primary side is mandatory to realize switched mode power supplies (SMPS) with top performances in terms of high efficiency, small dimensions and low cost. 
     In isolated topologies, if the main PWM control circuit is on the primary side, its signal cannot be available on the secondary side in a simple, effective and cheap way. This information can be however derived on the secondary side from the output of the isolation transformer. In this case, however, it is noted that the synchronizing signal withdrawn at the output of isolation transformer is the effect of primary main switch commutations. This signal, in fact, shows a behavior similar to the main PWM signal, at least in continuous conduction mode (CCM), but it is affected by the parasitic elements of the circuit. In addition, if the CCM working condition is not respected, it may also present some oscillations during part of the signal, which can determine false driving information. Therefore, the control technique meant to provide SR driving signals has to be able to prevent eventual rising of wrong operative conditions derived by any timing effects on the synchronization of the signal available on the secondary PWM synchronization signal with respect to the primary PWM signal. 
     Using the output of the isolation transformer as the PWM synchronization signal, a very simple way to make MOSFETs operate as rectifiers in isolated topologies based on forward topology is a technique called “self-driven synchronous rectification.” 
     A very basic example of this technique, which has been developed in many different proprietary versions, is provided in the single ended forward topology of FIG.  4 A. 
     If the gate of MOSFET  3  is connected to node  5 , and the gate of MOSFET  4  is connected to node  6 , the two MOSFETs are driven correctly, according to the equivalent diodes law. Unfortunately, this technique suffers a very serious inconvenience. As it can be observed in the related timing diagram of FIG. 4B, the driving signal is dependent on the way in which the main transformer is demagnetized during a magnetic reset. As a consequence, the time in which the body diodes of the MOSFET  4  is forced to conduct can be very large, due to the fact that the driving signal for the gate is missing. This fact damages the main benefits introduced by synchronous rectification, restricting the use of this method for driving SRs only in combination with some particular, and proprietary magnetic reset techniques. 
     In addition, this technique is hard to implement when the primary input voltage has a very wide range of variation. Common factors are limited to about 2:1, because it is difficult to always provide a driving signal value compatible with the appropriate ranges of the gates. 
     Therefore, in isolated topologies with primary side control, the most proper approach to drive SRs requires a control circuit able to handle the synchronization signal (clock) separate from the output of the isolation transformer, and to solve any other problem regarding the timing of the driving signals (Out 1 , Out 2 ) with respect to the clock input. In FIG. 5, the general Clock signal at a fixed switching frequency, with primary switch On and Off time intervals is shown. 
     The control circuit has to deal with proper timing generation of the SR driving signal from the clock signal input. According to FIG. 2, and as already explained, proper deadtimes between the clock signal and the SR driving signal must be provided to avoid cross conduction between devices. 
     Another well known phenomenon to be dealt by the controller is the so-called shoot through problem, that may happen on the secondary side of an isolated topology. The specific mechanism of this improper operation condition is dependent by the circuit topology, and it will be discussed in detail below. In general, while the transition in which a synchronous rectifier has to be turned on is easy to implement, the turn-off transition requires a special treatment. In fact, the circuitry that generates the driving signal from the clock introduces a propagation delay, which is added to the one coming from the isolation transformer. This intrinsic delay in generating the SR transition creates the deadtime necessary to avoid improper circuit conditions. However, this delay, bringing in terms of loss of efficiency because it causes body diode conduction, has to be minimized for efficiency optimization. 
     Instead, the turn-off transitions in FIG. 5 shown as Transition A for Out 1 , and Transition B for Out 2 , if not properly handled, can bring the circuit to a very critical behavior. In fact, in this case, the intrinsic delay generates a late turn-off of the bi-directional synchronous rectifier switches, creating improper circuit conditions. These improper circuit conditions are normally made impossible by the presence of the unidirectional diodes. The general condition can be defined as the creation of short circuit loops, which can generate very high current peaks, limited only by the parasitic elements in the circuit. The particular analysis of this phenomenon will be described in details for each of the main isolated topology family. 
     Therefore, the introduction of a special deadtime is necessary, which is able to avoid the generation of the improper operation conditions. This deadtime can be realized by generating a proper anticipation of the turn-off transition, which guarantees that the SR can be off before the clock signal transition. This anticipation, however, as in the turn-on transition, has to be minimized to reduce the body-diode conduction time, to avoid penalties on the efficiency. In particular, the amount of anticipation can be used as an optimization parameter to adjust the operation of the circuit to its physical implementation by design. In fact, the time slope of the decreasing current on the SR, which has been turned off, is dependant on several parameters like input and output voltage of the converter, the amount of previously driven current, and most importantly by the parasitic elements in the circuit like the leakage inductance. The anticipation time can be adapted to the specific operation condition of the circuit to achieve the best performance in terms of efficiency, setting to a minimum the conduction times of the body-diodes and the consequent reverse recovery currents. 
     In FIG. 5 the required anticipation intervals, denominated ΔT 1  and ΔT 2  are introduced in the most general case of two complementary outputs generated from a clock input. 
     The mechanism of generation of the shoot-through will be now examined for the main isolated topologies of SMPS converters. 
     A single ended forward topology power supply circuit is displayed in FIG.  6 . Operation of this circuit shows evidence in particular of the eventual generation of the shoot-through. 
     A synchronous rectifiers control circuit  7 , receiving the clock information from the voltage at a circuit node  8 , generates the MOSFET driving signals for an SR  9 , which is working as a forward rectifier, as well as generating driving signals for an SR  10  which is working as free-wheeling for the current of an output inductor  11 . 
     In particular, in this kind of circuit configuration, when a primary MOSFET  12  is turned on by a PWM controller  13 , the SR  9  must also be on and the SR  10  must be off. On the contrary, when the primary MOSFET  12  is off, the SR  10  must be on and the SR  9  must be off. 
     The voltage formation on node  8  shows some delay with respect to the primary MOSFET  12  drive signal, mainly coming from parasitics of an isolation transformer  14 . This delay, added to the propagation delay of the SRs controller  7 , causes a delayed turn-off of the SR  9  or of the SR  10 , and, as a consequence, shoot-through on the secondary output of the isolation transformer loop occurs in both transitions in which the MOSFET  12  is turned-on or off. 
     In fact, when the MOSFET  12  is turned-on, the voltage node  8  tends to go positive. This voltage forward biases the body diode of the SR  9  and, due to the delay in turning off the SR  10 , an unlimited current can flow in the short circuit loop formed by the SR  10 , the body-diode of the SR  9  and the secondary winding of the isolation transformer  14 . The value of the short circuit current is only limited by the parasitics of the circuit and eventually by the primary side protection circuits included in the PWM. 
     In the other transition, when the MOSFET  12  is turned off, the voltage on node  8  goes negative. If the SR  9  is still on due to the delay of the clock input formation, this negative voltage forward biases the body-diode of the SR  10 , and a short circuit loop is formed by the body-diode of the SR  10 , the SR  9  (still on) and the secondary winding of the isolation transformer  14 . 
     The detailed timing of the SRs turn off transitions relative to the forward topology circuit is shown in FIG.  7 . In both the two SR turning-off transitions for the free wheeling SR  10  (FW), and for the forward rectifier SR  9  (FR), the time interval t 0 -t 1  is the amount of anticipation, while t 0 -t 3  is the entire deadtime between the two complementary driving signals. In the interval t 0 -t 2  the body-diode conducts, reversing after t 2 . 
     A flyback topology circuit is displayed in FIG.  8 . Most of the considerations made for the forward topology circuit of FIG. 6 are still valid, but, in this case, the topology shows only one MOSFET working as a rectifier  15 . 
     The SR  15  has to be turned on when the main primary switch  12  is off and vice-versa. When the MOSFET  12  is turned on, the voltage at the output of the isolation transformer  14 , referenced by node  16 , goes from V o  to −V in , and if the SR  15  is not already off, a short circuit loop is generated with an output capacitor  17  put in parallel to a negative voltage that tries to impulsively discharge the capacitor with an unlimited current. This causes an unavoidable serious drop in the regulated output voltage. The detailed timing of the SR turn-off transition, relative to the flyback topology circuit of FIG. 8 is shown in FIG.  9 . It is apparent that the flyback topology circuit suffers from the same problems as the forward topology circuit. 
     Similar consideration are valid for all the forward derived double ended isolated topologies (push-pull, half bridge, full bridge), displayed in FIG.  10 . 
     In FIG. 10, a first synchronization clock input taken from a node  20  is used by an SR control circuit  21  to generate the proper timing signal for an SR  22 . In a similar way, a second synchronization clock input taken from a node  23  is used to generate the proper timing signal for an SR  24 . In both cases the synchronization clock and the relative output driving signal are displayed in FIG.  11 . In this case, the anticipation times in turning off the MOSFETs are necessary to avoid loss of all the energy stored in the transformer leakage inductance, in the short circuit loop formed in both transitions by the two SRs (one SR and one body-diode) and the secondary winding of the isolation transformer, with a worsening of the converter efficiency. 
     The detailed timing of the SRs turn-off transitions (two identical), relative to the forward double-ended topologies circuit is shown in FIG.  11 . 
     A control driven approach implementing an analog method to generate the anticipations of the turn-off transition in the driving timing, is disclosed in U.S. Pat. No. 5,736,890 to Yee et al. Part of the method appears to be implemented in a preliminary silicon from SRMOS Inc. (public advertising since November 1999). 
     This analog method uses two different analog ramps and one threshold variable with T ON  or T OFF , in order to generate the anticipation time. Three passive components (capacitors) are needed to generate the ramps and the variable threshold. Two of these capacitors have to be accurate in order to have a precise anticipation time. Stability in time and temperature are not good due to the dependence on passive components. 
     Another control driven approach, using a Phase Lock Loop (PLL) based system to realize the anticipations of the turn off transitions, has been recently implemented by International Rectifier, in a preliminary IC, IR1175 (public advertising since January 2000). This method is quite complex in terms of design relations needed to set the desired control, requiring a large amount of external components and relatively high pin count needed to set all the parameters that are necessary for the correct operation of the control technique. Beside this, the method presents a slow response time to switching frequency variations. If some noise problem causes a variation in the switching frequency, the Phase Lock Loop is slow to react to this variation, with a consequent wrong generation of the anticipation times, causing loss of overall efficiency of the converter. A faster response time can be achieved to the detriment of a worse accuracy of the anticipation time, which is also a cause of negative effect on the efficiency of the converter. 
     Until now, no adequate device and method to control MOSFET synchronous rectifiers in a switched mode power supply that minimizes short circuiting due to improper control timing of the MOSFET synchronous rectifiers was available. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention use a control-driven approach to drive synchronous rectifiers in SMPS isolated topologies. The control-driven technique presents several advantages with respect to the self-driven approach. 
     The technique conveniently uses the PWM controller on the primary side of the isolated topology, deriving synchronization information directly from the secondary side. It realizes independence from the isolation transformer reset technique, because the conduction time of the body-diode of the MOSFETs is minimized, while the driving signal values can be always made compatible with the gates ranges. It is also possible to allow discontinuous conduction mode operation of the converter. 
     Presented is a switched mode power supply that includes a transformer with primary and secondary windings, a primary power transistor coupled to the primary windings, and a switched synchronous rectifier coupled to the secondary windings of the transformer. A digital controller is provided to control the operation of the switched synchronous rectifier. The controller accepts an anticipation value at an input, and then compares a clock signal and a generated internal clock signal to one another with reference to the anticipation value. When the comparison is finished, a signal is generated to drive the switched synchronous rectifier, and the cycle repeats itself. 
     In other embodiments, two sets of comparison circuitry are available to drive a first and a second switched synchronous rectifier. The comparison circuitry can be realized using a set of up/down counters, and can be controlled by finite state logic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a block diagram showing the input and output connections of a digital controller device according to an embodiment of the invention. 
     FIG. 1B is a timing diagram showing an input signal and two output signals generated by a digital controller device according to an embodiment of the invention. 
     FIG. 2 is a timing diagram showing driving signals for a prior art synchronous rectifier. 
     FIG. 3 is a timing diagram showing signals for an isolated topology power supply of a prior art control device. 
     FIG. 4A shows a proprietary forward topology power supply according to the prior art and 
     FIG. 4B is a timing diagram showing signals generated by the prior art control device shown. 
     FIG. 5 is a timing diagram showing the timing of output driving signals with respect to a clock signal input. 
     FIG. 6 is a schematic diagram of a single ended forward topology power supply according to the prior art. 
     FIG. 7 is a timing diagram showing signals of the single ended forward topology power supply according to FIG.  6 . 
     FIG. 8 is a schematic diagram of a single ended flyback topology circuit according to the prior art. 
     FIG. 9 is a timing diagram showing timing signals of the flyback topology circuit shown in FIG.  8 . 
     FIG. 10 is a schematic diagram of a doubled ended topology circuit according to the prior art. 
     FIG. 11 is a timing diagram showing timing signals of the double ended circuit shown in FIG.  10 . 
     FIG. 12 is a block diagram showing the digital controller according to an embodiment of the invention. 
     FIGS. 13-19 are timing diagrams showing signals used by and generated within the digital controller shown in FIG.  12 . 
     FIGS. 20-22 are schematic diagram showing pin configurations of devices including an embodiment of the inventive digital controller. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     All the prior art techniques that are based on analog approach to implement the turn-off transitions anticipation function, show weakness due to the need of several external components, mainly capacitors with very tight tolerance, and stability needed to allow the correct operation of the relative technique and apparatus. 
     Other prior art techniques that use the PLL approach to create the turn-off transitions anticipation function require a very large number of external components, causing a high pin count in the synthesizing device, necessary to set all the parameters that are used for the proper operation of the control method, by means of complex design relations. In addition these prior art circuits show very slow response to transients, due to switching frequency and duty-cycle perturbations, which reflects negatively on the overall efficiency of the converter. 
     The presented method and the related implementing apparatus show several advantages and benefits over those circuits of the prior art. An embodiment of the invention solve the known operation problems regarding the generation of synchronous rectifier driving signals, like cross-conduction, and shoot-through, while it minimizes body-diode conduction. In particular the presented digital technique uses the implementation of a straightforward circuit configuration when inserted in an SMPS topology circuit. The synthesizing device can be formed with a very minimal pin count. No particular accuracy, or stability in time and temperature is required for the eventual external components, resistors, to be used to set the anticipation times. In addition the method shows excellent characteristics in terms of fast response to transitions coming from converter switching frequency and duty-cycle sudden variations. 
     The method herein disclosed is fast because the circuit control is made cycle-by-cycle, so it acts suddenly on the next successive cycle after a disturbance of the steady state occurs. In addition, due to the high flexibility of the digital approach, eventual correctional algorithms can be easily implemented in the switching frequency synchronization, generating error correction procedures and similar improvements of the presented approach. 
     A minor limitation of the method resides in the fact that the anticipation time can be only by discrete steps, due to the digital nature of the method, making the theoretical efficiency optimization process only partial. However, the time step can be reduced by increasing the internal digital oscillator frequency, so that a more precise resolution can be achieved, and consequently a more flexible determination of switching timing. By increasing the internal oscillating frequency, this efficiency can be made very large. 
     The presented method generates proper driving signals for synchronous rectifiers from a clock signal input, related to the main PWM signal of the switch-mode circuit. 
     In general, the presented circuit has the structure as shown in FIG. 1A. A digital controller  30  accepts as inputs a clock, and a first and second anticipation times. Based on those signals, the digital controller  30  produces control signals OUT 1  and OUT 2  for the gates of the MOSFET synchronous rectifiers. In particular the circuit operates according to the timing displayed in FIG. 1B, generating proper anticipation times corresponding to the turning off transitions of the outputs. 
     These functions are implemented through the concept of synchronizing the operation of the control circuit to the clock signal at the converter switching frequency, and in particular to its transitions. This is performed by means of two digital counter blocks which play different roles: one operates the measure of the intense switching period, cycle-by-cycle, storing this information for the next cycle. The other one makes the same measurements for the On or Off time of the clock signal according to the specific need of the circuit topology. 
     The precision and resolution of the system is directly related to an internal digital frequency of operation used to implement this method. Because the period and On/Off time intervals parameters of the previous cycle are available, a proper timing of the outputs can be generated of the following cycle, and in particular a proper anticipation on the turning off transitions can be set. The amount of the anticipation can be set accordingly with the resolution of the system, in terms of discrete quantities of minimum digital pulse period. 
     Timing of the presented control technique will be shown below, together with the detailed explanation of the control method operation, according to the non-limiting description of the apparatus through which it is implemented. 
     In the more general case of two complementary signals on the secondary side, the general structure of the digital controller  30  includes an internal clock oscillator  32 ; a finite state machine  34 ; pairs UP/DOWN counters  36 , 37 , 38 , 39 ; and first and second control output logic blocks  40 ,  42 , as shown in FIG.  12 . This digital controller  30  has three inputs and two outputs. The inputs are the clock (CK), and the anticipation time setting for the OUT 1  (x 1 ) and the anticipation time setting for the OUT 2  (x 2 ). The outputs are the driving signals for the two MOSFETs on the secondary side of the converter (OUT 1 , OUT 2 ). 
     The clock signal CK, input into the digital controller  30 , has a square wave signal having a frequency f s  and a period T s . The finite state machine, synchronized with a rising edge of the internal oscillator clock signal CK 1  at frequency f 1 &gt;f s  (period T 1 ) is the brain of the system and generates the two signals OUT 1  and OUT 2  without any overlap in turn on and turn off conditions. The anticipation times are externally set through the relative inputs x 1 , for set anticipation  1 , and x 2 , for set anticipation  2 . The four counters each have a DOWN phase in which the counter anticipates the turn off of a corresponding one of the outputs OUT 1 . The four counters also each have an UP phase in which the counter UP continuously obtains get the information about the duration of the switching period for the OUT 2 , or about the duration of the T on  time for the OUT 1 . In this way, during a switching period, the anticipation in the turn off of the outputs is based upon the information stored in the most immediately previous switching period. A continuous monitoring of the switching period and of the T on  time is obtained cycle by cycle. The number of bits of the counters  38 ,  39  relative to the OUT 2  are chosen according to the operating switching frequency range of the converter, and according to the frequency f 1  of the internal oscillator. The numbers of bits of the counters  36 ,  37  relative to the OUT 1  are chosen according to the operating T on  time of the converter and according to the frequency f 1  of the internal oscillator. 
     In steady state conditions (fixed switching frequency and fixed duty-cycle), for two consecutive switching periods, the part of the system relative to the OUT 2  operates as follows (FIG.  13 ). During a first switching period T s , on the rising edge of the clock input CK, the first counter  38  for the OUT 2  starts to count in its UP phase the pulses of the internal clock (CK 1 ). On the next rising edge of the clock input CK, (the end of the first period T s ) the counter  38  stops its calculation. The number of pulses counted (n 2 ) takes account of the duration of the switching period. This information is stored in order to be used in the next switching period. 
     During the second switching period, on the rising edge of the clock input CK, the counter  38  counts during its DOWN phase the pulses of the internal clock stopping its calculation at n 2 -x 2 . At this time the OUT 2  is turned off. The second counter  39  for the OUT 2 , counting the new number of pulses of the internal clock CK 1  during its UP phase, updates the information about the duration of the switching period T s . During the next (third) switching period, the counter  38  returns to its UP phase and the counter  39  returns to its DOWN phase. 
     The amount of anticipation in turning off the OUT 2  is given by (x 2 *T 1 ), and is set by the OUT 2  anticipation time input. In each period the function of the counters, UP or DOWN, is exchanged with respect to the previous period. 
     For the part of the digital controller  30  relative to the OUT 1 , the other UP/DOWN counters  36 ,  37  take into account the information about the duration of the TON time used to anticipate the turn off of the OUT 1  (FIG.  14 ). 
     During the first switching period, the first counter  36  for the OUT 1  starts to count the number of pulses of the internal clock CK 1 , on the rising edge of the clock input CK, and stops its calculation on the falling edge. The number of pulses of CK 1  counted is n 1 , and this information takes in account of the T ON  time. 
     During the second switching period, the first counter  36  counts during its DOWN phase the pulses of the internal clock CK 1 , stopping its calculation at n 1 -x 1  which gives an anticipation in turning off the OUT 1  equal to (x 1 *T 1 ), this anticipation is set through x 1 , the anticipation time  1  input. The second counter  37  for the OUT 1  counts upward the number of pulses of the internal clock CK 1  between the rising edge and the falling edge of the clock input CK during the current period during its UP phase. During the third switching period, the counter  36  returns to its UP phase and the counter  37  enters its DOWN phase to count n 1 -x 1  pulses in order to turn off the OUT 1 . 
     For the OUT 2 , when a variation in the switching frequency occurs, three different cases are possible: 
     First, the switching period in which the anticipation is realized could be smaller than the previous period (FIG.  15 ). Normally, with the described way of operation, the turning off of the OUT 2  would be delayed and not anticipated with respect to the clock input CK. In the digital controller  30 , this condition is avoided forcing, in any case, the turn-off of the OUT 2  with the rising edge of the clock input. 
     Second, the switching period in which the anticipation is realized could be larger than the previous period (FIG.  16 ). In this case, the digital controller  30  causes of an early turn off of the OUT 2 . The conduction time of the body diode of the MOSFET is not minimized, but this larger conduction time of the body diode of the MOSFET is present only for one clock cycle CK, and the loss of efficiency of the SMPS circuit is very low. 
     Third, the switching period in which the anticipation is realized could have a TON time equal or larger than the previous period (FIG.  17 ). In this case the digital controller  30  keeps the OUT 2  OFF. Even in this case, the conduction time of the body diode of the MOSFET is not minimized for only one cycle causing a very low loss of efficiency. 
     For the OUT 1 , when a variation in the T ON  time occurs, two different cases are possible. 
     First, the TON time in which the anticipation is realized could be smaller than the previous T ON  time (FIG.  18 ). With the described way of operation, the turn off of the OUT 1  would be delayed and no anticipation with respect to the clock input signal CK would be made. The digital controller  30  avoids this condition by forcing in any case the turn off of the OUT 1 , with the falling edge of the clock input signal CK. 
     Second, the T ON  time in which the anticipation is realized could be larger than the previous T ON  time (FIG.  19 ). In this case, an early turn off of the OUT 1  occurs. The conduction time of the body-diode of the MOSFET is not minimized just for one cycle and the loss of efficiency is very low. 
     The disclosed method implements a cycle-by-cycle control because the measurement taken in a given period determines the action in the next subsequent period. By setting the values for x 1  and x 2 , the amount of anticipation in turning-off the MOSFET synchronous rectifier is chosen among different discrete values. The time step is T 1 , so the higher the internal oscillator frequency f 1  is, the more accurate the anticipation time is. 
     This method of controlling the turn off time of synchronous rectifiers is being implemented by STMicroelectronics, S.r.l., in the design of a silicon device family: STSR2: Device designed to drive two synchronous rectifiers in Forward Topology applications. This IC includes the described control system, two high current N-Channel MOSFET drivers and a clock buffer circuit used to adapt the clock signal to the accepted values, with the pin output shown in FIG.  20 . 
     This device has an advanced version named STSR2A, in a 14 pin package, including the possibility of setting both anticipation times for the two turn-off transitions, and other features not pertinent with the topic of this application. 
     A STSR3 device is designed to drive one synchronous rectifier in Flyback Topology applications. This IC includes the described control system, with the same logic operation, but only for the part relative to OUT 2 . It includes one high current N-Channel MOSFET driver and a clock buffer circuit needed to adapt the clock signal to the accepted values, with the pin output shown in FIG.  21 . 
     A STSR4 device is designed to drive two synchronous rectifiers in Double-Ended Topology applications (Push Pull, Half Bridge, Full Bridge). The device includes a dual structure, based on the duplication of the described control systems for the part relative to OUT 1 , two high-current N-Channel MOSFET drivers and two clock buffer circuits needed to adapt the clock signal to the accepted values, with the pin output shown in FIG.  22 . 
     The elements of the power supply circuits shown in FIGS. 20-22 are referred using numbers of the corresponding elements of FIGS. 6,  8 , and  10 , respectively. For conciseness, those elements with operations and functions that are the same in FIGS. 20-22 compared to FIGS. 6,  8 ,  10  are not described in more detail herein. 
     The circuits of FIGS. 20-21 do include a clock buffer  44  for buffering the clock signal being input to the digital controller  30  and the circuit of FIG. 22 includes first and second clock buffers  44   a ,  44   b  for buffering the two clock signals being input to the digital controller. Also, the circuits of FIGS. 20 and 22 include two drivers  46 ,  48  for driving the respective synchronous rectifiers with the respect output signals OUT 1 , OUT 2  and the circuit of FIG. 21 includes a single driver  46  for driving the single synchronous rectifier with the output signal OUT. 
     Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.