Abstract:
A dynamic random access memory includes a semiconductor substrate having an active region including first and second diffusion regions of a transfer transistor, an insulating layer formed on the semiconductor substrate and having first and second contact holes, and a stacked capacitor having a storage electrode which is electrically coupled to the first diffusion region through the first contact hole formed in the insulating layer and an opposed electrode. The DRAM also includes a word line electrically isolated from the semiconductor substrate, and a bit line electrically isolated from the semiconductor substrate and electrically coupled to the second diffusion region through the second contact hole formed in the insulating layer. The second contact hole is substantially positioned at a center of the bit line. The word line has a bent portion located between the first and second contact holes so that the word line is separated from the second contact hole at a predetermined distance.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to a dynamic random access memory, and more particularly to a dynamic random access memory having an improved layout. Further, the present invention is concerned with a method of arranging a memory cell pattern of the dynamic random access memory. 
     Recently, the layout of structural elements of a dynamic random access memory (hereinafter simply referred to as a DRAM) has been designed by using a computer. In order to reduce the amount of data to be processed, the layout is designed by using straight lines extending in two orthogonal directions and straight lines extending at an angle of 45° with respect to each of the orthogonal directions. However, advanced computers has an ability to process an extremely large amount of data at high speeds and thus makes it possible to design the layout by using oblique lines which extend at angles other than 45° with respect to the aforementioned orthogonal directions. 
     Referring to FIG. 1, there is illustrated a layout of a DRAM of a stacked capacitor type. In FIG. 1, AR indicates an active (diffusion) region including a drain region and a source region, a word line and S indicates a source area. D indicates a drain area. WL indicates a word line and WL&#39; denotes the distance between the adjacent word lines WL. BL indicates a bit line and BL&#39; indicates an extension portion of the bit line BL. BH indicates a bit line contact hole and SE indicates a storage electrode. SH indicates a storage electrode contact hole. GP is the space between the extension portion BL&#39; of the bit line BL and the adjacent bit line BL. 
     FIG. 2 is a sectional view taken along line II-II shown in FIG. 1. A P-type silicon semiconductor substrate 1 has a source region S and drain region D of a transfer transistor, both of which are active regions (impurity diffused regions) buried in the Si substrate 1. A field insulating layer 2 and a gate insulating layer 3 are formed on the Si substrate 1. CP indicates an opposed electrode (cell plate) of a storage capacitor. The bit line BL is formed at a layer level lower than that of the opposed electrode CP. The word line WL&#39; the bit line BL&#39; the storage electrode SE and the opposed electrode CP are stacked in this order. A stacked capacitor is composed of the storage electrode SE, a dielectric film DE and the cell plate CP. This arrangement would become popular as the size of memory cells is further reduced. 
     In the arrangement shown in FIGS. 1 and 2, each bit line contact hole BH used for electrically coupling the bit line BL and the source region S of the transfer transistor must be positioned so that it keeps away from the word line WL. The storage electrode contact hole SH used for electrically coupling the storage electrode SE and the drain region D of the transfer transistor must be positioned so that it keeps away from both the word line WL and the bit line BL. 
     Each bit line BL must be provided with the extension portion BL&#39; which is formed so that it surrounds the contact hole BH. The presence of the extension portion BL&#39; increases the surface area of the bit line BL so that a parasitic capacitance is increased. In addition, the arrangement shown in FIGS. 1 and 2 causes short circuiting in the vicinity of the bit line extension portion BL&#39;, since the distance GP between the bit line extension portion BL&#39; and the adjacent bit line BL is smaller than the distance between the adjacent bit lines BL. 
     Length DM of each memory cell measured in the direction in which each bit line BL extends is described as follows. ##EQU1## where a: half the width of the bit line contact hole BH 
     e: alignment margin of each of the contact holes 
     d: the width of the word line WL 
     c: half the width of the storage electrode contact hole SH 
     WL&#39; the distance between the adjacent word lines WL 
     It can be seen from FIG. 1 that A=a+e+d+e+c=a+c+d+2e. The bit line contact hole BL and the storage electrode contact hole SH are arranged approximately in a line so that the length DM of each memory cell is great. 
     SUMMARY OF THE INVENTION 
     It is a general object of the present invention to provide a DRAM having an improved layout in which the aforementioned disadvantages are eliminated. 
     A more specific object of the present invention is to provide a DRAM having an improved layout which has no bit line extension portion for forming a bit line contact hole and which is directed to preventing the occurrence of short circuiting between the adjacent bit lines. 
     The above-mentioned objects of the present invention are a dynamic random access memory comprising: a semiconductor substrate having an active region including first and second diffusion regions of a transfer transistor; an insulating layer formed on the semiconductor substrate and having first and second contact holes; a stacked capacitor having a storage electrode which is electrically coupled to the first diffusion region through the first contact hole formed in the insulating layer and an opposed electrode; a word line electrically isolated from the semiconductor substrate; and a bit line electrically isolated from the semiconductor substrate and electrically coupled to the second diffusion region through the second contact hole formed in the insulating layer. The second contact hole is substantially positioned at a center of the bit line. The word line has a bent portion located between the first and second contact holes so that the word line is separated from the second contact hole at a predetermined distance. 
     The aforementioned objects of the present invention are also achieved by a dynamic random access memory comprising: a semiconductor substrate having a plurality of active regions, each including first and second diffusion regions of a transfer transistor; an insulating layer formed on the semiconductor substrate and having a plurality of first contact holes and a plurality of second contact holes; a plurality of stacked capacitors, each having a storage electrode which is electrically coupled to a corresponding one of the first diffusion regions through a corresponding one of the first contact holes formed in the insulating layer and an opposed electrode; a plurality of word lines electrically isolated from the semiconductor substrate; and a plurality of bit lines electrically isolated from the semiconductor substrate, each of the bit lines being electrically coupled to a corresponding one of the second diffusion regions through a corresponding one of the second contact holes formed in the insulating layer. Each of the second contact holes is substantially positioned at a center of a corresponding one of the bit lines. Each of the word lines having a bent portion located between a corresponding one of the first contact holes and a corresponding one of the second contact holes so that a corresponding one of the word lines is separated from the corresponding one of the second contact holes at a predetermined distance. 
     Another object of the present invention is to provide a method of arranging a memory cell pattern of the above-mentioned dynamic random access memory. 
     This object of the present invention is achieved by a method of arranging structural elements of a dynamic random access memory including a semiconductor substrate having first and second diffusion regions, an insulating layer having first and second contact holes, a word line, a bit line and a stacked capacitor having a storage electrode, wherein the storage electrode is in contact with the first diffusion region through the first contact hole, and the bit line is in contact with the second diffusion region through the second contact hole, the method comprising the steps of determining a first position which is separated from a center of the bit line at a first predetermined distance; determining a second position which is located at the center of the bit line and which is separated from the first position at a second predetermined distance, and determining a position of the word line so that the word line is located between the first and second contact holes. The first position corresponds to a center of the first contact hole. The second position corresponds to a center of the second contact hole. 
     The above object of the present invention is also achieved by a method comprising the steps of determining a first position which is located at a center of the bit line, determining a second position which is located on an imaginary line extending from the first position at a predetermined angle with respect to the bit line and which is separated from the center of the bit line at a predetermined distance, and determining a position of the word line so that the word line is positioned between the first and second contact holes. The first position corresponds to a center of the second contact hole. The second position corresponds to a center of the first contact 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a diagram illustrating a conventional layout of a DRAM of a stacked capacitor type; 
     FIG. 2 is a cross sectional view taken along line II-II shown in FIG. 1; 
     FIG. 3 is a diagram illustrating the principle of the present invention; 
     FIG. 4 is a diagram illustrating a pattern according to a preferred embodiment of the present invention; 
     FIGS. 5A and 5B are diagrams illustrating the influence of a bird&#39;s beak; 
     FIG. 6 is a diagram of a pattern according to the embodiment of the present invention in which four memory cells are illustrated; 
     FIGS. 7A, 7B and 7C are diagrams illustrating how the present invention was made; and 
     FIG. 8 is a block diagram of a folded bit line type DRAM. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention is based on the following considerations. 
     First, in order to eliminate the aforementioned extension portion BL&#39; which projects from the bit line BL and which surrounds the bit line contact hole BH, it is the best way to arrange the bit line contact hole BL so that the center thereof is positioned on the center line of the bit line BL. 
     Second, it is advantageous to arrange the storage electrode contact hole SH so that the center thereof is positioned at an equal distance from the adjacent bit lines BL and at an equal distance from the adjacent word lines WL. 
     Third, an imaginary line which connects the bit line contact hole BH and the corresponding storage electrode contact hole SH crosses the bit line BL at an angle with respect to the direction in which the bit line BL extends, that is, the center line thereof. Active regions such as source and drain regions are arranged on the basis of the imaginary line. In addition, the shape of each word line WL is determined, taking into consideration the pattern of the active regions. 
     Referring to FIG. 3, there is illustrated the principle of the present invention based on the above-mentioned first to third considerations. In FIG. 3, those parts which have the same names of structural elements as those shown in FIG. 1 are given the same reference characters. CL indicates a center line of the bit line BL&#39; and C BH  indicates the center of the bit line contact hole BH. C SH  indicates the center of the storage electrode contact hole SH, and 0 indicates an angle formed between the center line CL and an imaginary line which connects the center C BH  and C SH . 
     A distance A between the center C BH  of the bit line contact hole BH and the center C SH  of the storage electrode contact hole SH, that is, the length A of the imaginary line therebetween is described as follows. 
     
         A=a+c+d+2e 
    
     The distance between the center line CL of the bit line BL and the center C SH  of the storage electrode contact hole BH is written as follows. 
     
         1/2b+c+e 
    
     It can be seen from FIG. 3 that two right-angled isosceles triangles TA are formed. Thus, the angle θ is written as follows. 
     
         θ=sin.sup.-1 [(1/2b+e+c)/(a+c+d+2e)]                 (1) 
    
     The memory cell pattern is determined so that formula (1) is satisfied. It is possible to determine the memory cell pattern so that the angle θ is nearly equal to the right term of formula (1). 
     Referring to FIG. 4, there is illustrated a layout of a DRAM according to a preferred embodiment of the present invention. In FIG. 4, those parts which have the same names as those shown in the previous figures are given the same reference characters. In FIG. 4, a letter b denotes the width of the bit line BL&#39; and AR, indicates a bent portion of the active region AR. Z is a bent portion of the word line WL. Z1, Z2 and Z3 indicate areas of the word line WL which form the bent portion Z of the word line WL. 
     The center C BH  of the bit line contact hole BH is positioned on the center line CL of the bit line BL. Although the bit line BL shown in FIG. 4 has an extension portion for forming the bit line contact hole BH, it is smaller than that shown in FIG. 1. Thus, the distance between the extension portion of the bit line BL and the adjacent bit line BL is increased so that the occurrence of short circuiting therebetween can be reduced. 
     The length A of the imaginary line which connects the center C BH  of the bit line contact hole BH and the center C SH  of the storage electrode contact hole SH is equal to a+c+d+2e, as described previously. The angle θ of the line with respect to the center line CL of the bit line BL is selected, as defined by formula (1). The minimum distance between the center C SH  of the storage electrode contact hole SH and the center line CL of the bit line BL is equal to 1/2b+c+e. 
     The active area AR extends along the imaginary line which connects the center C BH  of the bit line contact hole BH and the center C SH  of the storage electrode contact hole SH. That is, the active area AR is arranged obliquely with respect to the bit line BL. The active area AR has a bent portion AR&#39; which is symmetrically bent or curved with respect to a line which passes through the center C SH  of the storage electrode contact hole SH and which is perpendicular to the center line CL of the bit line BL. 
     The bent portion AR&#39; of the active area AR reduces the influence of bird&#39;s beaks. Referring to FIG. 5A, there is illustrated a silicon nitride (Si 3  N 4 ) film used for selectively oxidizing the Si substrate to thereby produce an oxide layer (field insulating layer) for element-to-element isolation. Oxygen is supplied with a short end of the Si 3  N 4  film along various directions, as shown by arrows in FIG. 5A. Thus, the bird&#39;s beak occurs at the short end of the Si 3  N 4  film and an Si substrate surface portion in the vicinity of the short end is oxidized, as indicated by arrow OX shown in FIG. 5B. Although an Si substrate surface portion in the vicinity of a long end of the Si 3  N 4  is also oxidized, as indicated by arrow OY shown in FIG. 5B, it is smaller than that indicated by the arrow OX. The bent portion AR, of the active region AR is provided for taking into account the occurrence of the above-mentioned bird&#39;s beak. It should be noted that it is impossible to provide a bent portion which straight extends from the active area AR because of the presence of the bit line contact hole BH. 
     The direction in which each word line WL extends is perpendicular to the direction in which each bit line BL extends. Each word line WL has the bent portion Z, which is composed of the areas Z1, Z2 and Z3. The area Z1 is orthogonal to the center line CL of the bit line CL. The areas Z2 and Z3 are located on both sides of the area Z1. Each of the areas Z2 and Z3 is orthogonal to the corresponding line which connects the center C BH  of the bit line contact hole BH and the center C SH  of the storage electrode contact hole SH. The areas Z2 and Z3 are arranged symmetrically with the area Z1. 
     According to the layout shown in FIG. 4, the length L of each memory cell measured in the direction in which the bit line BL extends is as follows. ##EQU2## It can be seen from the above formula that the length L of memory cell is not based on the distance WL&#39; between the adjacent word lines. As a result, it is possible o to increase the distance WL&#39; and reduce the possibility of the occurrence of short circuiting. 
     When the minimum distance between the adjacent lines is 0.5 [μm], the parameters are selected as follows. 
     a=c=0.3 [μm] 
     b=d=0.5 [μm] 
     e=0.4 [μm] 
     WL&#39;=0.5 [μm] 
     In this case, the length of each memory cell in the direction in which the bit line BL extends is 3.29 [μm]. On the other hand, the length of each memory in the same direction according to the aforementioned prior arrangement shown in FIG. 1 is 3.35 [μm] when the distance between the adjacent word lines is set equal to 0.5 [μm]. 
     The distance between the adjacent word lines according to the arrangement shown in FIG. 4 is 0.8 [μm]. On the other hand, the distance between the adjacent word lines according to the prior arrangement shown in FIG. 1 is 0.5 [μm]. 
     The distance between the adjacent bit lines according to the arrangement shown in FIG. 4 is 1.0 [μm]. On the other hand, the distance between the adjacent bit lines according to the prior arrangement shown in FIG. 4 is 0.5 [μm]. 
     The area of each memory cell according to the arrangement shown in FIG. 4 is slightly less than that shown in FIG. 1. The distance between the adjacent bit lines BL and the word lines WL in the memory cells is 1.6-2 times that of the prior arrangement. 
     The cross section taken along line II&#39;-II&#39; is almost the same as that shown in FIG. 2. The stacked capacitor is not limited to the structure shown in FIG. 2. For example, it is possible to form the stacked capacitor so that the storage electrode SE has a single fin. It is also possible to form the stacked capacitor so that the single fin or the lowermost fin from among a plurality of fins is separated from the insulating layer and the opposed electrode is also provided between the single fin or the lowermost fin and the insulating layer. 
     FIG. 6 is a diagram showing the layout of four memory cells. In FIG. 6, those parts which are the same as those in the previous figures are given the same reference numerals. It will be noted that the bent portion AR&#39; of each active area AR shown in FIG. 6 is greater than that shown in FIG. 4. That is, the bent portion AR&#39; of each active area AR is located under the corresponding word line WL. It will also be noted that a curved part Z&#39; of each word line WL which crosses the bit line BL is curved without having the areas Z1, Z2 and Z3. Even in the arrangement shown in FIG. 6, the imaginary line connecting the center C BH  of the bit line contact hole BH and the center C SH  of the storage electrode contact hole C SH  is perpendicular to the curved part Z&#39; of the word line WL. All of memory cell patterns can be formed by repeatedly arranging the layout shown in FIG. 6. 
     FIGS. 7A, 7B and 7C are diagrams illustrating how the present invention was made. In FIGS. 7A through 7C, those parts which have the same names as those described previously are given the same reference letters. Referring to FIG. 7A, the dot line illustrates the pattern of the conventional word line WL as shown in FIG. 1. A contact hole formed in a fine pattern is approximately of a circle shape due to the intensity distribution of light. Thus, it is possible to consider each contact hole as a circle on the pattern layout drawing. The word lines are required to be separated from the bit line contact holes BH at a predetermined distance. Thus, it is possible to partially shape each word line WL into a circular arc in order to keep away from the bit line contact holes BH at the predetermined distance. As a result, dot areas between the adjacent word lines WL become available. Thus, as shown in FIG. 7B, it becomes possible to obliquely shift the positions of the storage electrode contact holes SH. Due to the positional change in the storage electrode contact holes SH, it becomes possible to shift the positions of the bit lines BL so that the bit line contact holes BH are located at the center thereof, as shown in FIG. 7B. Thereby, it is possible to substantially eliminate the bit line extension portions as shown in FIG. 1 or FIG. 7A so that each bit line BL is substantially straight. In addition, it is possible to increase the distance between the adjacent bit lines BL from GP (FIG. 7A) to GP&#39; (FIG. 7B). Further, due to this positional change of the storage electrode contact holes SH, it becomes possible to shift the positions of the word lines WL&#39;  as illustrated in FIG. 7C. As a result, it becomes possible to increase the distance between the opposite edges of the adjacent word lines WL from W1 to WI&#39;, as shown in FIG. 7C. On the other hand, the distance between the other opposite ends of the adjacent word lines WL is decreased, as shown in FIG. 7C. It is possible to arbitrarily determine the distances W1&#39; and W2&#39; on the basis of various requirements. Moreover, 
     FIG. 8 is a block diagram of a folded bit line type DRAM. A plurality of pairs of bit lines, such as BL1 and BL1, extend from corresponding sense amplifiers S/A. A plurality of word lines extend so as to cross the bit lines, as described previously. A memory cell MC is coupled between one of the bit lines and one of the word lines. The pattern arrangements according to the present invention are suitable for the folded bit line type DRAM as shown in FIG. 8. However, the arrangements are also applied to an open bit line type DRAM. 
     The present invention is not limited to the memory cell shown in FIG. 2, but includes memory cells as disclosed in U.S. Pat. Nos. 4,641,166, 4,649,406, 4,754,313 and 4,190,566 and U.S. Ser. Nos. 206,791 filed on June 15, 1988 and 274,279 filed on Nov. 21, 1988, the disclosure of which is hereby incorporated by reference. 
     The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention.