Abstract:
A method an apparatus for testing logic circuits containing a set of scan chains, each set of scan chains comprising a multiplicity of scan chains. The apparatus comprising: a scan input; a scan output; an input shift register coupled between the scan input and the set of scan chains, each first stage of different scan chains of the set of scan chains coupled to a different stage of the input shift register; and an output shift register coupled between the scan output and the set of scan chains, each last stage of different scan chains coupled to a different stage of the output shift register.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to the field of testing integrated circuits; more specifically, it relates to a method and an apparatus for testing integrated circuits using scan chains.  
         BACKGROUND OF THE INVENTION  
         [0003]    As the size and complexity of logic chips such as application specific integrated circuit (ASIC) chips grew, scan based testing was developed as an alternative to conventional testing in order to reduce test equipment time and costs. However, as the number logic gates have grown, even scan based testing has created several problems for automatic test equipment (ATE). A first problem is buffer overflow for ATEs with fixed size buffers. A second problem is insufficient data transfer bandwidth between the ATE and the product under test. A third problem, becoming increasingly important for low power applications such as used in portable devices and in aerospace applications, is power consumption requirements of the chip designs limit the maximum internal scan cycle rate for large dense complementary metal-oxide-silicon (CMOS) devices. A fourth problem is as ASICs grow in complexity and contain more functions, applications require more signal inputs and outputs (I/Os) and the number of I/Os left available for testing becomes limited.  
           [0004]    Therefore, there is a need for a method of reducing the amount of test data to be stored, that increases the effective test rate within the constraints of limited bandwidth and is not limited by external data I/O bandwidth without exceeding internal chip design and power consumption constraints.  
         SUMMARY OF THE INVENTION  
         [0005]    A first aspect of the present invention is an apparatus for testing logic circuits containing a set of scan chains, comprising: a scan input; a scan output; an input shift register coupled between the scan input and the set of scan chains, each first stage of different scan chains of the set of scan chains coupled to a different stage of the input shift register; and an output shift register coupled between the scan output and the set of scan chains, each last stage of different scan chains coupled to a different stage of the output shift register.  
           [0006]    As second aspect of the present invention is a method for testing logic circuits containing a set of scan chains, comprising: providing a scan input; providing a scan output; providing an input shift register coupled between the scan input and the set of scan chains, each first stage of different scan chains of the set of scan chains coupled to a different stage of the input shift register; and providing an output shift register coupled between the scan output and the set of scan chains, each last stage of different scan chains coupled to a different stage of the output shift register; writing a test pattern to the scan input; propagating the test pattern through the scan chains; and reading a resultant pattern at the scan output. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0008]    [0008]FIG. 1 is a block diagram of a system for testing a logic device according to a first embodiment of the present invention;  
         [0009]    [0009]FIG. 2 is a block diagram of a system for testing a logic device according to a second embodiment of the present invention;  
         [0010]    [0010]FIGS. 3A and 3B are diagrams illustrating a load operation resulting in conflicting values of care bits;  
         [0011]    [0011]FIGS. 4A and 4B are diagrams illustrating a load operation resulting in non-conflicting values of care bits;  
         [0012]    [0012]FIG. 5 is a block diagram of a system for testing a logic device according to a third embodiment of the present invention;  
         [0013]    [0013]FIG. 6 is a schematic diagram of an exemplary integral multiple input signature register logic/output shift register combination;  
         [0014]    [0014]FIG. 7 is a schematic diagram of an exemplary integral linear feedback shift register logic/input shift register combination and a typical spreading network; and  
         [0015]    [0015]FIG. 8 is a block diagram of a system for testing a logic device according to a modification of the first embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    For the purposes of the present invention, a stage of a register or a scan chain is defined to include one or more latches. These latches may include latch types such as flip-flops. A stage holds or latches a data bit. Even though a single clock may be described for each register or scan chain, it should be understood that multiple clock signals may be required by specific implementations of the present invention.  
         [0017]    [0017]FIG. 1 is a block diagram of a system for testing a logic device according to a first embodiment of the present invention. In FIG. 1, test system  100  includes a first input shift register  105 A, a first set of scan chains  110 A and a first output shift register  115 A. First input shift register  105 A receives serial scan in data (SI 0 ), which is a test pattern, from a first serial input line  120 A. The number of first scan chains  110 A is equal to the number of stages in first input shift register  105 A. (See FIG. 8 and discussion infra for a case where the number of scan chains is less than the number of stages of the input and output shift registers.) Each stage of first input shift register  105 A is coupled to a different first stage of a single scan chain  1110 A via bus  125 A. In the present example, first input shift register  105 A comprises 16 stages (i.e. the first input shift register  105 A is a 16-bit register) and there are 16 scan chains  110 A and bus  125 A is 16 bits wide. The number of scan chains may be any number and the value of 16 is used only for exemplary purposes.  
         [0018]    Each scan chain  110 A, may include hundreds or thousands of stages arranged in series and coupled to the combinational logic of the integrated circuit being tested. (As is well known in the art, in practice each scan chain comprises an input scan chain and an output scan chain in parallel with a different set of combinational logic coupled to corresponding stages in the input and the output scan chains).  
         [0019]    The number of stages in first output shift register  115 A is equal to the number of first scan chains  110 A. Each stage of first output shift register  115 A is coupled to a different last stage of a single scan chain  1110 A via a bus  130 A. In the present example, first output shift register  115 A comprises 16 stages (i.e. first output shift register  115 A is a 16-bit register) and bus  130 A is 16 bits wide. First output shift register  115 A sends serial scan out data (SO 0 ), which is the resultant test pattern after the test pattern passes through the combinational logic, to a first serial output line  135 A. Thus, the sequential relationship between SI 0  and SO 0  is kept intact.  
         [0020]    Movement of bits between stages of first input shift register  105 A is controlled by a clock signal ISR CLK. Movement of bits between stages of first scan chains  1110 A is controlled by a clock signal SCAN CLK. Movement of bits between stages of first output shift register  115 A is controlled by a clock signal OSR CLK.  
         [0021]    Test system  100  is operated, in the present example, in loops of 16 cycles. The number of cycles per loop is equal to the number of stages in first input and first output shift registers  105 A and  115 A. The number of loops is equal to the number of stages in first scan chains  110 A. In the first cycle of each loop, all three clocks ISR CLK, SCAN CLK and OSR CLK are cycled once. This moves one bit into first input shift register  105 A, one 16-bit word from the input shift register into the first stage of scan chains  110 A (one bit per scan chain), and one 16-bit word out of the last stages of first scan chains  110 A (one bit per scan chain) into first output shift register  115 A. Next both the ISR CLK and OSR CLK are cycled 15 times which serially moves 15 new data bits into first input shift register  105 A and serially moves 15 data bits out of first output shift register  115 A. A feature of the present invention is that the frequency of the ISR and OSR CLK signals may be higher than the SCAN CLK frequency. The ISR and OSR frequency may be adjusted to match that of ATE while the SCAN CLK runs a lower, chip design frequency. In the present example, ISR CLK and OSR CLK could run 16 times faster than SCAN CLK. If each first scan chain  110 A contains, for example, 1000 stages each, then 16,000 cycles (1000 loops of 16 cycles each) will be required to fully scan all 1000 stages of the 16 scan chains. Test system  100 , runs in full scan mode.  
         [0022]    Finally, it should be recognized that the very first scan clock cycle transfers old data from first input shift register  105 A into first scan chains  110 A and it may be desirable to continue testing for one extra loop (16 cycles) to shift the old data out of the last stages of first scan chains  110 A and scan in new data before terminating the test operation.  
         [0023]    Test system  100  may also include any number of additional groups of input shift registers, scan chain sets and output shift registers. A second such group is illustrated in FIG. 1. Test system  100  further includes a second input shift register  105 B, a second set of scan chains  110 B and a second output shift register  115 B. Second input shift register  105 B, second scan chains  110 B (except for the number of scan chains which may be different) and second output shift register  115 B are identical to and operate identically to first input shift register  105 A, first scan chains  110 A and first output shift register  115 A, respectively. Second input shift register  105 B receives serial scan in data (SI 1 ) via a second serial input  120 B. Second output shift register  115 B sends serial scan out data (SO 1 ) to a second serial output line  135 B. Thus, the sequential relationship between SI 1  and SO 1  is kept intact.  
         [0024]    [0024]FIG. 2 is a block diagram of a system for testing a logic device according to a second embodiment of the present invention. In FIG. 2 a test system  140 , includes (in addition to all the components of test system  100  illustrated in FIG. 1 and described supra) a first mask buffer  145 A, a second mask buffer  145 B, a first mask logic  150 A, a second mask logic  150 B and a multiple input signature register logic (MISR)  155 . First mask buffer  145 A and first mask logic  150 A are coupled between first scan chains  110 A and MISR logic  155 . Second mask buffer  145 B and second mask logic  150 B are coupled between second scan chains  110 B and MISR logic  155 . MISR logic  155  is coupled to first output shift register  115 A and second output shift register  115 B. MISR logic  155 , first output shift register  115 A and second output shift register  115 B are implemented integral to one another. An exemplary integral MISR logic/output shift register is illustrated in FIG. 6 and described infra.  
         [0025]    First mask buffer  145 A and second mask buffer  145 B are identical and operate identically so only first mask buffer  145 A will be described. The operation of mask buffers and mask logic is well known in the industry and will only be described briefly. First mask buffer  145 A is capable of storing one or more mask words in one or more rows of stages. The number of stages in each set of stages is equal to the number of scan first chains  110 A. The input of each stage (or input of each corresponding stage from a different row) of first mask buffer  145 A is coupled to a single, different stage of first input shift register  105 A by a bus  164 A. This allows for loading of a pattern(s) into first mask buffer  145 A by cycling clock signal MB CLK. The output of each stage (or outputs of each corresponding stage from a different row) of first mask buffer  145 A is coupled to a single, different first input of a single different AND gate within first mask logic  150 A. The number of AND gates is equal to the number of first scan chains  110 A. The number of inputs to each AND gate is equal to the number of mask words stored in first mask buffer  145 A plus one additional input. The additional input of each AND gate is coupled to the output of a single, different first scan chain  110 A via bus  130 A. First mask logic  150 A also includes mask select circuits (not shown) to allow “ANDing” of no, one or multiple mask words with the data in first scan chains  110 A. Movement of data from first mask buffer  145 A/first mask logic  150 A to MISR  155  is under the control of MB CLK.  
         [0026]    The output of each AND gate of first mask logic  150 A (or of each first scan chain  110 A if masking is not enabled) is coupled to a single, different gate in MISR logic  155  via a bus  160 A. MISR logic  155  in conjunction with first and second output shift registers  115 A and  115 B, selectively concatenate and compresses the outputs of first and second mask logic  150 A and  150 B onto serial output lines  135 A and  135 B. Movement of data though MISR logic  155  and first output shift register  115 A to serial output line  135 A is under the control of under the control of a OSR/MISR logic CLK. MISR logic  155  may be bypassed by a MISR ENABLE signal. The masks applied by first mask logic  150 A and second mask logic  150 B may be changed or the masking operation disabled by a MASK SELECT signal.  
         [0027]    Test system  140  runs in compressed data mode and the output of MISR logic logic  155  is not true test result data (as in test system  100  of FIG. 1) but a signature representing the data bits of each word read out of first and second scan chains  110 A and  110 B. However, since each time a word is written out of first and second scan chains  115 A and  115 B failing bit information may be overwritten. MISR logic  155 , by “XORing” each old bit in a MISR stage with the corresponding new bit from the last stages of each first scan chain  110 A captures that information.  
         [0028]    In the present example, each compressed scan operation begins with 16 prefix cycles to load first and second input shift registers  105 A and  105 B to a fixed initial state and to unload the last MISR signature accumulated by the last compressed scan operation from first and second output shift registers  115 A and  115 B. This is accomplished by cycling ISR CLK and OSR/MISR CLK 16 times with MISR logic  155  disabled (MISR ENABLE=off) and SCAN CLK low (off). SI 0  and SI 1  are tied to fixed constant values during these first 16 cycles.  
         [0029]    In the example of each first scan chain  110 A having 1000 stages, MISR logic  155  is next enabled (MISR ENABLE=on) and 1000 ISR CLK, SCAN CLK and OSR/MISR CLK simultaneous cycles are applied. There is one simultaneous ISR CLK, SCAN CLK and OSR/MISR CLK cycle applied for each first scan chain  110 A stage. If first and second inputs  120 A and  120 B and first and second outputs  135 A and  135 B are bidirectional, first and second inputs  120 A and  120 B are held in the input mode and first and second outputs  135 A and  135 B are held in the output mode. Input states on first and second inputs  120 A and  120 B are applied for each cycle. Each of these cycles accumulates two 16-bit words from first and second scan chains  110 A and  110 B into MISR logic  155  and transfers the current contents of first and second input shift registers  105 A and  105 B into scan first and second chains  110 A and  110 B respectively, while first and second input shift registers  105 A and  105 B, MISR logic  155 , first and second scan chains  110 A and  110 B and first and second output shift registers  115 A and  115 B are each shifted by one bit position.  
         [0030]    If this is the last compressed operation, then 16 prefix cycles to unload the last MISR signature from first and second output shift registers  115 A and  115  are required. This is accomplished by simultaneous cycling of ISR CLK and OSR/MISR CLK 16 times with MISR logic  155  disabled (MISR ENABLE=off) and SCAN CLK low (off). SI 0  and SI 1  are tied to fixed constant values during these last 16 cycles. Thus, a complete test requires 1032 cycles as compared to the 16,000 cycles required for test system  100  of FIG. 1.  
         [0031]    It should be recognized that only a single new data bit is loaded into each input shift register each cycle and the remaining bits are shifted by one bit position. The input shift registers are thus not completely updated for each scan chain shift, resulting in highly correlated test patterns that can create problems as illustrated in FIGS. 3A and 3B and resolved as illustrated in FIGS. 4A and 4B and described infra.  
         [0032]    It is also possible to configure the second embodiment of the present invention without first and second mask buffers  145 A and  145 B and without first and second mask logic  150 A and  150 B.  
         [0033]    [0033]FIGS. 3A and 3B are diagrams illustrating a load operation resulting in conflicting values of care bits. FIG. 3A illustrates a 4-bit input shift register  165  and four 8-stage scan chains  171 ,  172 ,  173  and  174 . A test pattern “K J I H G F E D C B A” is cycled through an input shift register  165  via an input  170  into scan chains  171 ,  172 ,  173  and  174 . First four clock cycles (only the input shift register clock is active) fill input serial register with the pattern “D C B A.” Then eight additional clock cycles (both the input shift register clock and the scan chain clocks are active) fill up each scan chain  171 ,  172 ,  173  and  174 . Since each input shift register clock moves a single bit into input shift register  165  but four bits from input shift register  165  into scan chains  171 ,  172 ,  173  and  174  (1-bit into each scan chain  171 ,  172 ,  173  and  174 ) a diagonal pattern of is created in scan chains  171 ,  172 ,  173  and  174  as illustrated by lines  175 .  
         [0034]    [0034]FIG. 3B illustrates a desired test pattern of 0s and 1s for a test of the combination logic (not shown) coupled to scan chains  171 ,  172 ,  173  and  174 . Dashes indicate don&#39;t care bits while any bit-position with a 0 or a 1 is a care bit. Care bits are bits that test for specific faults in the combinational logic. Generally, few bits are care bits, the vast majority only being used to “fill” the test pattern. These “fill” bits are called don&#39;t care bits. Illustrated by ovals  176  in FIG. 3B, the fourth bit-position (from the top) in scan chain  173  contains a 1 while the fifth bit-position of scan chain  172  contains a 0. Since both these bit-positions were filled using bit “J” from the test pattern, a conflict over the care bit values in the input pattern exists. A similar conflict exists between bit-position six of scan chain  173  and bit position seven of scan chain  172 . An input pattern of “-0-1-0-0-1-” would establish the correct care bits in scan chain  172 . However, the care bits in positions  5  and  7  of scan chain  173  would still be incorrect. Theses conflicts are resolvable by the technique illustrated in FIGS. 4A and 4B and described infra.  
         [0035]    [0035]FIGS. 4A and 4B are diagrams illustrating a load operation resulting in non-conflicting values of care bits. A test pattern “M L K J I H G F E D C B A” is cycled through input shift register  165  via input  170  into scan chains  171 ,  172 ,  173  and  174 . The first four clock cycles (only the input shift register clock is active) fill input serial register with the pattern “D C B A.” Note the two extra bit-positions L and M. Then ten additional clock cycles fill up each scan chain  171 ,  172 ,  173  and  174 . However, instead of cycling both the input scan register clock and the scan chain clocks together for all ten cycles, the scan chain clock is not cycled on the seventh and tenth cycle. Thus a bit still gets loaded into input shift register  170  on the seventh and tenth clock cycles, but no bits are transferred from input shift register  170  to scan chains  171 ,  172 ,  173  and  174 . Thus the diagonal pattern illustrated in FIG. 3A is as illustrated by lines  175  has been disturbed and the pattern marked by line  180  created.  
         [0036]    In FIG. 4B, the input pattern “-0-1-10-10-1-” is seen to produce the desired pattern without conflicts. This solution is relatively easy to implement by simple programming of an automatic test pattern generator (ATPG) that generates the test pattern, without the ATPG program having to solve complex Boolean equations as is required by current test techniques.  
         [0037]    For the present example of four 8-stage scan chains, a valid 32-bit test vector (4×8) with correct values for the 8 care bits can be derived from an input pattern of only 13 bits. This is over a 2-fold reduction in the size of the test pattern needed by conventional test methodologies. The size of the input pattern is a result of the number of care bits and care bit “conflicts.” Typical ASICs have a much lower percentage of care bits than the 25% shown in this example, thus the reduction in the size of their test patterns is much greater.  
         [0038]    It should be pointed out that some conflicts could also be resolved by only cycling the scan chain clocks while the input shift registers are held off. For example, the particular bit pattern illustrated in FIG. 4B could be achieved by first applying  4  input shift register clock cycles while holding the scan chain clocks off to load a “0 0 1 1” pattern into the input shift register and then cycling the scan clock for 8 cycles with the input shift register clock inactive.  
         [0039]    [0039]FIG. 5 is a block diagram of a system for testing a logic device according to a third embodiment of the present invention. In FIG. 5 a test system  190 , includes (in addition to all the components of test system  140  illustrated in FIG. 2 and described supra) a linear feedback shift register (LFSR) logic  195 , a spreading network  200  and buses  205 A and  205 B. Buses  125 A and  125 B feed through LFSR logic  195  and spreading network  200  is coupled to first scan chain  110 A by bus  205 A and coupled to second scan chain  110 B by bus  205 B. LFSR logic  195 , first input shift register  105 A and second input shift register  105 B are implemented integral to one another. An exemplary integral LSFR logic/input shift register is illustrated in FIG. 7 and described infra.  
         [0040]    While LFSR logic is illustrated in FIG. 5, an LFSR is an example of a general class of devices called pseudo-random pattern generators (PRPGs) that are known to persons skilled in the art. Therefore any PRPG logic may be subsituted for LFSR logic  195 . Another device that may substituted for LFSR logic  195  is a cellular automata (CA).  
         [0041]    ISR CLK of FIGS. 1 and 2 is now ISR/LFSR CLK. ISR/LFSR CLK controls first and second input shift registers  105 A and  105 B. LFSR logic  195  is controlled by LFSR ENABLE. The two 16-bit words from first and second input shift registers  105 A and  105 B are concatenated into one 32-bit word bu LFSR logic  195  under the control of an LFSR enable signal LFSR ENABLE. Because of the XOR gate(s) contained in an LFSR, LFSR logic  195  acts as a pseudo random pattern generator (PRPG) by hashing the two 16-bit words within first and second input shift registers  105 A and  105 B when the LFSR logic is enabled. LFSR logic  195  (if enabled) and first and second input shift registers  105 A and  105 B or just first and second input shift registers  105 A and  105 B (if LFSR logic  195  is not enabled) shift a first 16-bit word in into spreading network  200  via bus  125 A and shifts a second 16-bit word into spreading network  200  via bus  125 B.  
         [0042]    LFSRs have a “diagonal repeat” problem similar to that described supra in reference to FIGS. 3A and 3B. Spreading network  200  eliminates this problem. An exemplary spreading network is also illustrated in FIG. 7 and described infra. Spreading network  200  may be bypassed and the two 16 bit words directly passed to scan chains  110 A and  110 B by buses  205 A and  205 B respectively, without any changes of bit values or positions.  
         [0043]    Test system  190  can be operated in full scan mode as described supra in reference to test system  100  (see FIG. 1) or compressed scan mode as also described supra in reference to test system  140  (see FIG. 2).  
         [0044]    It should be understood that the clocking and control signals illustrated in FIGS. 1, 2 and  3  and described supra can come from separate control inputs or can be derived by combination and/or clock gating techniques from a smaller number of shared control and clock inputs. The actual control signal and clock interfaces and decoding depends on chip I/O constraints and the number of different operating modes between which a user wishes to switch. One of the advantages of the present invention is that circuits requiring more scan chains than the number of I/O pins would normally allow can still be tested since multiple can scan chains share the same I/Os. Testing such a constrained system is difficult with conventional ATE.  
         [0045]    [0045]FIG. 6 is a schematic diagram of an exemplary integral MISR logic/output shift register (OSR) combination. In FIG. 6, MISR/OSR  250  includes a multiplicity of stages  255  interdigitated with a multiplicity of XOR gates  260  in a continuous loop, each stage  255  being coupled between a first input of a previous XOR gate  260  and an output of a subsequent XOR gate  260 . There is one XOR gate  260  for each scan chain. A second input of each XOR gate  260  is coupled to a last stage of a different scan chain. Stages  255  comprise the OSR portion of MISR/OSR  250  and XOR gates  260  and a feedback path  262  comprise the MISR logic portion of MISR/OSR  250 . The operation of MISR/OSR  250  is readily deducible by a person of ordinary skill in the art, from FIG. 6. Other types of MISRs that may be combined with OSR&#39;s that may be substituted for MISR/OSR  250 , and their operation, are well known to persons of ordinary skill in the art.  
         [0046]    [0046]FIG. 7 is a schematic diagram of an exemplary integral linear feedback shift register logic/input shift register (ISR) combination and a typical spreading network. In FIG. 7, LFSR/ISR  270  includes a multiplicity of input stages  275 A through  275 N, a final stage  280  and a XOR gate  285  arranged in a loop. SIO is coupled to a first input of XOR gate  285 . The output of each input stage  275 A through  275 N is coupled to the input of a subsequent input stage  275 A through  275 N and a corresponding XOR gate  295 A through  295 N except the output of input stage  275 N is coupled to the input of final stage  280  and to a second input of XOR gate  285  as well as a first input of XOR gate  295 N. The output of end stage  280  is coupled to a third input of XOR gate  285 . Stages  275 A through  275 N and  280  comprise the ISR portion of LFSR/ISR  250  and XOR gate  285  and paths  287 ,  288  and  289  comprise the LFSR logic portion of LFSR/ISR  270 . In addition to the single feedback shown in FIG. 6, there are many other feedback configurations that may be used as is well known in the art. In the present example, the output of XOR gate  285  is coupled to the input of input gate  275 A.  
         [0047]    Exemplary spreading network  290  includes a multiplicity of XOR gates  295 . A first input of each XOR gate  295  is coupled to a different stage  275  of LFSR  270 . A second input of each XOR gate is coupled to the output of end stage  280  of LFSR  270 . The output of each XOR gate  295  is coupled to a first stage of a different scan chain. The operation of LSFR  270  and spreading network  290  are readily deducible by a person of ordinary skill in the art, from FIG. 7. Other forms of spreading networks are well known in the art and may br substituted for the example shown.  
         [0048]    Test system  100 A may also include any number of additional groups of input shift registers, scan chain sets and output shift registers. A second such group is illustrated in FIG. 8. Test system  100 A further includes a second input shift register  105 D, a multiplicity of scan chains  110 D and a second output shift register  11  SD. Second input shift register  105 D receives serial scan in data (SI 1 ), which is a test pattern, from a serial input line  120 D. Second input shift register  105 D is coupled to scan chains  110 D by bus  125 D and scan chains  110 D are coupled to second output shift register  11  SD by bus  130 D Second output shift register  11  SD sends serial scan out data (SO 1 ) to a serial output line  135 D. The number of scan chains  110 D is not equal to the number of stages in second input shift register  105 D or first output shift register  115 D. Each stage of first input shift register  105 D is coupled to a different first stage of a single scan chain  110 D via bus  125 D. In the present example, first input shift register  105 D comprises 16 stages which include 12 wired stages  121 D and  4  un-wired stages  122 D. First output shift register  115 C comprises 16 stages which include 12 wired stages  123 D and 4 un-wired stages  124 D. There are 12 scan chains  110 D and bus  125 D is 12 bits wide.  
         [0049]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.