Abstract:
A method and apparatus provides resistor networks with two or more resistance values, which may accommodate different circuit configurations with a common circuit assembly. Also, the present invention provides a packaging method using multiple-value resistor networks as connecting and disconnecting mechanisms for the signal lines on the package.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to resistor elements and resistor networks.  
           [0002]    Electronic circuit modules sometimes contain resistor networks to incorporate multiple resistors of the same value.  
           [0003]    A 64-bit memory module normally contains 16 resistor networks, each with 4 resistor elements with a value of 10 ohms.  
           [0004]    In order to construct usable memory module packages with partially defective memory chips, the on-board resistors are required to have certain combinations of values.  
           [0005]    Using 64 or 128 single individual resistors is certainly one way to accommodate this situation. However, the assembly process is more time consuming. It is also subject to certain limitation on the total number of onboard components.  
           [0006]    Using different printed circuit boards for different configurations is another way to cope with the situation. However, the inventory and production control becomes quite complex.  
         BRIEF SUMMARY OF THE INVENTION  
         [0007]    This invention proposes a method and apparatus to generate resistor networks with multiple values.  
           [0008]    This invention provides a method to accommodate different component configurations with a single printed-circuit board.  
           [0009]    This invention further provides a method to simplify the manufacturing process of an electronic circuit module. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a diagram of a prior art resistor network.  
         [0011]    [0011]FIG. 2 is a diagram of a prior art memory circuit block.  
         [0012]    [0012]FIG. 3 is a diagram of a prior art memory module.  
         [0013]    [0013]FIG. 4 shows a number of preferred embodiments of the present invention for a multiple-value resistor network.  
         [0014]    [0014]FIG. 5 shows a preferred embodiment of the present invention for a memory circuit block.  
         [0015]    [0015]FIG. 6 shows a preferred embodiment of the present invention for a memory module.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    The present invention will be illustrated with some preferred embodiments.  
         [0017]    [0017]FIG. 1 is a diagram of a prior art resistor network. The resistor network  101  contains resistors  102 ,  103 ,  104 , and  105 . All four resistors are of the same value, for example, 10 ohms.  
         [0018]    [0018]FIG. 2 is a diagram of a prior art memory circuit block. The memory circuit block  201  consists of a memory chip  202  and a resistor group  203 . The resistor group contains two resistor networks  204  and  205 .  
         [0019]    Each resistor network contains 4 resistor elements of the same value, 10 ohms. A resistor element serves as a connecting mechanism to link a data bit line  206  on the memory chip to a data bit line  207  on the memory circuit block.  
         [0020]    [0020]FIG. 3 is a diagram of a prior art memory module. The memory module  301  contains eight memory circuit blocks  302 . A memory circuit block  302  consists of a memory chip  303  and a resistor group  304 .  
         [0021]    The resistors serve as connecting mechanisms to link the data bit lines on the memory chips to the data bit lines on the memory circuit blocks. The data bit lines on the memory circuit blocks are connected to the edge connector  305  of the memory module.  
         [0022]    [0022]FIG. 4 shows a number of preferred embodiments of the present invention for a multiple-value resistor network.  
         [0023]    The resistor network  401  contains resistors  411 ,  412 ,  413 , and  414 . The resistors  411 ,  412 , and  413  are of one value, for example 10 ohms. The shaded resistor  414  has a different value, for example, 1 mega ohms.  
         [0024]    [0024]FIG. 4 shows eight different combinations of multiple-value resistor networks with two different values. Shaded resistors are with a resistance value of 1 mega ohms. Blank resistors are with a resistance value of 10 ohms.  
         [0025]    There are a total of 16 ways to combine four resistors with two possible values. Besides the eight combinations  401 ,  402 ,  403 ,  404 ,  405 ,  406 ,  407 , and  408  shown in FIG. 4, six more combinations may be obtained by turning resistor networks  401 ,  402 ,  403 ,  404 ,  407 , and  408  clockwise 180 degrees. The remaining two combinations contain only one resistance value, either 10 ohms or 1 mega ohms.  
         [0026]    [0026]FIG. 5 shows a preferred embodiment of the present invention for a memory circuit block. The memory circuit block  501  consists of two memory chips  502 ,  503 , and a resistor group  504 . The resistor group contains four resistor networks, each with 4 resistors.  
         [0027]    The resistors  510 ,  511 ,  512 ,  513 ,  514 ,  515 ,  516 , and  517  link the data bit lines on the memory chip  502  to the memory bit lines  530 ,  531 ,  532 ,  533 ,  534 ,  535 ,  536 , and  537  on the memory circuit block.  
         [0028]    The resistors  520 ,  521 ,  522 ,  523 ,  524 ,  525 ,  526 , and  527  link the data bit lines on the memory chip  503  to the memory bit lines  530 ,  531 ,  532 ,  533 ,  534 ,  535 ,  536 , and  537  on the memory circuit block.  
         [0029]    In memory chip  502 , memory bit positions D 1 , D 3 , D 4 , D 6 , and D 7  are marked as defective because they contain at least one defective memory blocks. The remaining bits D 0 , D 2 , and D 5  contains only functional memory blocks.  
         [0030]    Resistors  510 ,  512 , and  515  with a low resistance value serve as connecting mechanisms to link the functional data bits D 0 , D 2 , and D 5  to the data lines  530 ,  532 , and  535  of the circuit block. Resistors  511 ,  513 ,  514 ,  516 , and  517  with a high resistance value serve as disconnecting mechanisms to block D 1 , D 3 , D 4 , D 6 , and D 7  from the circuit block data lines.  
         [0031]    In memory chip  503 , memory bit positions D 0 , D 2 , D 5  are marked as defective because they contain at least one defective memory blocks. The remaining bits D 1 , D 3 , D 4 , D 6 , and D 7  contains only functional blocks.  
         [0032]    Resistors  521 ,  523 ,  524 ,  526 , and  527  with a low resistance value serve as connecting mechanisms to link the functional data bits D 1 , D 3 , D 4 , D 6 , and D 7  to the data line  531 ,  533 ,  534 ,  536  and  537  of the circuit block. Resistors  520 ,  522 , and  525  with a high resistance value serve as disconnecting mechanisms to block D 0 , D 2 , D 5  from the circuit block data lines.  
         [0033]    [0033]FIG. 6 shows a preferred embodiment of the present invention for a memory module. The memory module  601  contains eight memory circuit blocks  602 . A memory circuit block  602  consists of two memory chips  603 ,  604 , and a resistor group  605 .  
         [0034]    The resistors serve either as connecting mechanisms to link the functional chip data bit lines to the circuit block data bit lines or as disconnecting mechanisms to block the defective chip data bit lines from the circuit block data bit lines.  
         [0035]    The data bit lines on the memory circuit blocks are connected to the edge connector  606  of the memory module.