Abstract:
A method of forming a circuit includes providing a substrate; providing an interconnect region positioned on the substrate; bonding a device structure to a surface of the interconnect region; and processing the device structure to form a first stack of layers on the interconnect region and a second stack of layers on the first stack. The width of the first stack is different than the width of the second stack.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This is a divisional of application Ser. No. 11/092,500, entitled “SEMICONDUCTOR MEMORY DEVICE”, filed on Mar. 29, 2005, which claims priority to U.S. Pat. No. 7,052,941 filed on Jun. 21, 2004, the contents of both of which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates generally to semiconductor circuitry and, more particularly, to semiconductor memory devices.  
         [0004]     2. Description of the Related Art  
         [0005]     Advances in semiconductor manufacturing technology have provided computer chips with integrated circuits that include many millions of active and passive electronic devices, along with the interconnects to provide the desired circuit connections. As is well-known, most integrated circuits include laterally oriented active and passive electronic devices that are carried on a single major surface of a substrate. Active devices typically include transistors and passive devices typically include resistors, capacitors, and inductors. However, these laterally oriented devices consume significant amounts of chip area.  
         [0006]     It is desirable to provide computer chips that can operate faster so that they can process more data in a given amount of time. The speed of operation of a computer chip is typically measured in the number of instructions per second it can perform. Computer chips can be made to process more data in a given amount of time in several ways. In one way, the number of devices included in the computer chip can be increased so that it can operate faster because more information can be processed in a given period of time. For example, if one computer chip operates on 32-bit data, then another computer chip that operates on 64-bit data can process information twice as fast because it can perform more instructions per second. However, the 64-bit computer chip will need more devices since there are more bits to process at a given time.  
         [0007]     The number of devices can be increased by making the devices included therein smaller, but this requires advances in lithography and increasingly expensive manufacturing equipment. The number of devices can also be increased by keeping their size the same, but increasing the area of the computer chip. However, the yield of the computer chips fabricated in a run decreases as their area increases, which increases the overall cost.  
         [0008]     Computer chips can also be made faster by decreasing the time it takes to perform certain tasks, such as storing and retrieving information to and from memory. The time needed to store and retrieve information to and from memory can be decreased by embedding the memory with the computer chip on the same surface as the other devices. However, there are several problems with doing this. One problem is that the masks used to fabricate the memory devices are not compatible with the masks used to fabricate the other devices on the computer chip. Hence, it is more complex and expensive to fabricate a computer chip with memory embedded in this way. Another problem is that memory devices tend to be large and occupy a significant amount of area. Hence, if most of the area on the computer chip is occupied by memory devices, then there is less area for the other devices. The total area of the computer chip can be increased, but as discussed above, this decreases the yield and increases the cost.  
         [0009]     Accordingly, it is highly desirable to provide new structures and methods for fabricating computer chips which operate faster and are cost effective to fabricate.  
       BRIEF SUMMARY OF THE INVENTION  
       [0010]     The present invention provides a method of forming a circuit which includes providing a substrate; providing an interconnect region positioned on the substrate; bonding a device structure to a surface of the interconnect region; and processing the device structure to form a first stack of layers on the interconnect region and a second stack of layers on the first stack. The width of the first stack is greater than the width of the second stack.  
         [0011]     The present invention also provides a semiconductor device which includes a first stack of material layers. A second stack of material layers is positioned on the first stack, wherein the first and second stacks have different widths. First and second control terminals coupled to the first and second stacks, respectively, so that the first and second stacks each operate as an electronic device. One of the first and second stacks operates as a transistor and the other one operates as a negative differential resistance device.  
         [0012]     The present invention further provides a circuit which includes a substrate which carries electronic devices. An interconnect region is carried by the substrate, wherein the interconnect region has interconnects coupled to the electronic devices. A device structure is positioned on an upper surface of the interconnect region. The device structure has a first stack of layers positioned on a second stack of layers, wherein the first stack has a width different from the second stack, The device structure is electrically coupled to the electronic devices through the interconnects.  
         [0013]     These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIGS. 1-11  are simplified sectional views of steps in the fabrication of a memory device in accordance with the present invention.  
         [0015]      FIG. 12  is simplified sectional views of a memory device having tapered slope in its body in accordance with the present invention.  
         [0016]      FIGS. 13-14  are simplified sectional views of steps in the fabrication of a memory device with narrowed semiconductor width in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]      FIGS. 1-12  are simplified sectional views of steps in fabricating a semiconductor memory circuit  100  in accordance with the present invention. In the following figures, like reference characters indicate corresponding elements throughout the several views. In  FIGS. 1-12 , only a few memory devices are shown in circuit  100 , but it should be understood that circuit  100  generally includes a number of memory devices and that only a few are shown for simplicity and ease of discussion.  
         [0018]     Circuit  100  can be included in a computer chip where the memory devices are positioned above the computer circuitry. The memory devices are typically coupled to the computer circuitry through interconnects which include a conductive line and/or a conductive via. Circuit  100  has several advantages. One advantage is that the memory devices are positioned above the computer circuitry which is desirable since the memory devices typically occupy much more area than the computer circuitry. Another advantage of circuit  100  is that the memory devices are positioned closer to the computer circuitry so that signals can flow therebetween in less time. Still another advantage of circuit  100  is that the computer circuitry are fabricated with a different mask set than the memory devices. Hence, the masks are less complicated and less expensive to make. A further advantage is that the memory devices are fabricated from blanket semiconductor layers after they have been bonded to the interconnect region. Hence, the memory devices do not need to be aligned with the computer circuitry, which is a complicated and expensive process.  
         [0019]     In  FIG. 1 , partially fabricated circuit  100  includes an interconnect region  131  carried by a substrate  130 . Interconnect region  131  provides support for structure positioned thereon its surface  131   a . Interconnect region  131  includes a dielectric material region  133  with interconnect lines  132  and conductive vias  134 . Dielectric material region  133  can be formed using many different methods, such as CVD (Chemical Vapor Deposition) and SOG (Spin On Glass). Typically interconnect lines  132  and vias  134  are coupled to electronic circuitry (not shown) carried by substrate  130  near a surface  130   a . Interconnect lines  132  and vias  134  include conductive materials, such as aluminum, copper, tungsten, tungsten silicide, titanium, titanium silicide, tantalum, and doped polysilicon, among others.  
         [0020]     A conductive contact region  121  is positioned on surface  131   a  of region  131 . Region  121  can include one or more material layers, however, it is shown here as including one layer for simplicity. A device structure  101  is positioned on surface  121   a  of conductive region  121 . In accordance with the invention, structure  101  is bonded thereto surface  121   a  using wafer bonding. More information on wafer bonding can be found in co-pending U.S. patent application titled “WAFER BONDING METHOD” and “SEMICONDUCTOR BONDING AND LAYER TRANSFER METHOD” filed on the same date herewith by the same inventor and incorporated herein by reference.  
         [0021]     In this embodiment, device structure  101  includes a stack of semiconductor layers which include an n + -type doped layer  124   a  with a p-type doped layer  124   b  positioned on it. An n + -type doped layer  124   c  is positioned on layer  124   b  and a p-type doped layer  124   d  is positioned on layer  124   c . An n-type doped layer  124   e  is positioned on layer  124   d  and a p + -type doped layer  124   f  is positioned on layer  124   e . In this embodiment, these layers can be doped using diffusion doping, epitaxial growth, ion implantation, plasma doping, or combinations thereof. More information on wafer bonding can be found in a co-pending U.S. patent application titled “SEMICONDUCTOR LAYER STRUCTURE AND METHOD OF MAKING THE SAME” filed on the same date herewith by the same inventor and incorporated herein by reference. In this invention, device structure  101  preferably includes single crystalline material which can have localized defects, but is generally of better quality than amorphous or polycrystalline material.  
         [0022]     It should be noted that device structure  101  will be processed further, as shown in  FIGS. 2-12 , to form one or more desired device(s) which can be many different types. For example, the device(s) can include a memory device, such as a capacitorless Dynamic Random Access Memory (DRAM) device. In this particular example, the electronic device(s) include a Negative Differential Resistance (NDR) type Static Random Access Memory (SRAM) device, which has vertically and serially connected a thyristor and a MOSFET (Metal-Oxide Semiconductor Field-Effect-Transistor). As will be discussed in more detail below, the NDR SRAM device can operate faster and is more stable than a planar NDR SRAM device.  
         [0023]     In  FIG. 2 , a hardmask region  125  is positioned on a surface  101   a  of device structure  101  and a photoresist region  126  is positioned on hardmask region  125 . Hardmask region  125  can include dielectric materials, such as silicon oxide and silicon nitride. Hardmask region  125  can also include anti-reflective films, such as high-K SiON, in order to reduce reflection during photo process. Photoresist region  126  is patterned and exposed using a photo mask (not shown) so that portions of it can be removed and other portions (shown) remain on hardmask region  125 . Photoresist region  126  defines a top portion of the device to be fabricated, as indicated by a dotted line  101   d . In  FIG. 3 , device structure  101  is partially etched in a known manner to form stacks  127  and photoresist region  126  is removed. Stacks  127  are formed because the etch does not substantially remove the material in region  101  below hardmask region  125 .  
         [0024]     In  FIG. 4 , mask regions  128  are positioned around each stack  127 . Mask regions  128  extend from a surface  129   a  of layer  124   c  to mask region  125  of each stack  127 . Sidewall mask region  128  can include a dielectric material, such as oxide and/or nitride, deposited by CVD (Chemical Vapor Deposition), and dry etched to form the sidewall. Sidewall mask region  128  and mask  125  protect stack  127  and a portion of a surface  129   a  from a subsequent etch step, as will be discussed presently.  
         [0025]     In  FIG. 5 , device structure  101  is etched again to surface  131   a  of interconnect region  131  except for portions protected by mask regions  125  and  128 . Stack  127  now includes a stack region  127   a  positioned on electrode  121 , which is electrically connected to interconnect  132  through vias  134 . Stack  127  also includes a stack region  127   b  positioned on stack  127   a . In this example, stack  127   a  is wider than stack  127   b  so that a ledge  129  is formed therein stack  127 . Here, stack  127   a  has a width W 1  and stack  127   b  has a width W 2  where W 1  is greater than W 2 .  
         [0026]     Stack regions  127   a  and  127   b  include layers of semiconductor materials stacked on top of each other and are defined by sidewalls  119   a  and  119   b , respectively. Hence, the devices formed from stacks  127   a  and  127   b  are called “vertical” devices because their layer structure and sidewalls  119   a  and  119   b  extend substantially perpendicular to surface  131   a . In other words, the layers of stack  127  are on top of each other so that current flow through pn junctions included therein is substantially perpendicular to surface  131   a  and parallel to sidewalls  119   a  and  119   b.    
         [0027]     This is different from conventional devices which are often called lateral or planar devices. Lateral devices have their layer structure extending horizontally relative to a surface of a material region that carries them. In other words, the pn junctions included in a lateral device are positioned side-by-side so that current flow through them is substantially parallel to the supporting surface.  
         [0028]     In  FIG. 6 , a dielectric material region  133   a  is deposited on interconnect region  131 , planarized, and etched back so that it partially surrounds stacks  127 . In this embodiment, material region  133   a  extends up stacks  127  to layers  124   a . Material region  133   a  is processed so that it covers electrodes  121  and prevents oxidation during a gate oxidation process, as will be discussed presently.  
         [0029]     A dielectric region  123  is deposited around an outer periphery of each stack  127 . Dielectric region  123  can include silicon dioxide, silicon nitride, or combinations thereof. It can also include high dielectric constant (high-k) materials, such as Al 2 O 3 , ZrO 2 , HfO 2 , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , TiO 2 , and BST (Barium Strontium Titanate). Region  123  can be thermally grown or deposited using thermally evaporation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It is beneficial if the thermal growth or deposition can be done using a temperature below about 500° C. so that electrode  121 , interconnect region  131 , and the electronic circuitry carried by substrate  130  are not damaged or undesirably changed.  
         [0030]     In  FIG. 7 , a conductive region  140  is positioned on stacks  127  so that it surrounds them. Region  140  is positioned on dielectric material region  133   a , hardmask region  125 , and dielectric region  123  of each stack. Conductive region  140  can include the same or similar material as those included in vias  134 , interconnects  132 , and/or region  121 . Conductive region  140  operates as a control terminal to modulate the current flow through stack  127 . Also, dielectric layer  133   a  separates bottom electrodes  121  from each adjacent stack  127 . Conductive region  140   c  between stacks  127  is thicker than conductive region  140   d  because during the deposition process, more conductive material is deposited between adjacent stacks  127 .  
         [0031]     In  FIG. 8 , conductive region  140  is partially etched away so that portions surrounding stacks  127  remains. After etching, a portion  140   a  of conductive region  140  remains on region  133   a  and extends up stack  127   a  and a portion of conductive region  140   b  remains on surface  129   a  of ledge  129  and extends up stack  127   b . The etching can be done by anisotropic etching, such as dry etching, and is done in such a way that conductive regions  140   a  and  140   b  are not coupled together. Portion  140   a  couples each adjacent stack  127   a  together. However, portions  140   b  of each adjacent stack are not coupled together.  
         [0032]     In  FIG. 9 , a dielectric material region  133   b  is deposited on dielectric material region  133   a  and can include the same material. Material region  133   b  extends up stack  127   a  to stack  127   b . A conductive region  141  is positioned on dielectric material region  133   b  so that it surrounds stacks  127   b . In  FIG. 10 , conductive region  141  is partially etched away so that portions  141   a  remain around conductive region  140   b  and dielectric region  123 .  
         [0033]     In  FIG. 11 , a dielectric region  133   c  is deposited on dielectric region  133   b  so that it surrounds stacks  127 . Dielectric region  133   c  can include the same material as regions  133 ,  133   a , and/or  133   b . Trenches are formed through portions of dielectric region  133   c  to p + -type region  124   f  of each stack  127 . Contacts  142  are then formed therein so that they extend to a surface  101   a  of structure  101 . A conductive interconnect  143  is formed on surface  101   a  and is coupled to each via  142 . It should be noted that another device structure, similar to device structure  101 , can be bonded to conductive interconnect  143  and surface  101   a  and processed as described above so that multiple layers of devices structures are carried by interconnect region  131 .  
         [0034]     It should also be noted that sidewalls  119   a  and  119   b  of stacks  127   a  and  127   b , respectively, are substantially perpendicular to surface  131   a . However, in some embodiments, sidewalls  119   a  and/or  119   b  can be oriented at an angle, other than 90°, relative to surface  131   a . For example, the angle can be 70° so that the sidewalls of stacks  127   a  and  127   b  are sloped relative to surface  131   a.    
         [0035]      FIG. 12  shows device  100  with stacks  127   a  and  127   b  wherein sidewall  119   a  is sloped and sidewall  119   b  is perpendicular to surface  131   a . If the sidewalls are sloped, then it is easier to deposit material between adjacent stacks  127 . Further, conductive contact  121  can be made wider so the alignment is easier during device processing. Sloped sidewalls also increase the stability of stacks  127  even though its aspect ratio is high. The aspect ratio is the ratio of the height of stack  127  between conductive contact  121  and layer  124   f  relative to its width, W 1 .  
         [0036]      FIGS. 13 and 14  are simplified sectional views of steps in fabricating a semiconductor memory circuit  102  in accordance with the present invention. In  FIG. 13 , circuit  102  is the same or similar to device  100  shown in  FIG. 2 , only hardmask region  125  is thicker. In this embodiment, hardmask region  125  is exposed and overetched so that the portions of hardmask  125  between photoresist region  126  and layer  124   f  have widths W 4 , which is less than width W 2  as shown in  FIG. 5 . Overetching undercuts hardmask region  125  so that its width W 4  is less than width W 3 . Since width W 4  is made smaller, the width of stack  127   b  will also be made smaller, as shown in  FIG. 14 . Here, stack  127   b  is shown in phantom with dotted lines. At this point, region  101  can be etched, as shown in  FIG. 4 , and the processing can move to the subsequent steps described above.  
         [0037]     The present invention is described above with reference to preferred embodiments. However, those skilled in the art will recognize that changes and modifications may be made in the described embodiments without departing from the nature and scope of the present invention. Various further changes and modifications will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof.