Abstract:
A detector having an offset cancellation function, and a power factor correction apparatus and a power supplying apparatus having the same are provided. The detector detecting a level of an input signal may include a level shifter shifting the level of the input signal, and a comparator amplifying a voltage difference between the level of the signal shifted by the level shifter and a ground, and providing a compensation current according to an offset generated at the time of amplifying a voltage to cancel the offset.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority and benefit of Korean Patent Application No. 10-2014-0057689, filed on May 14, 2014, with the Korean Intellectual Property Office, the disclosure of which is incorporated in its entirety herein by reference. 
       BACKGROUND 
       [0002]    Some embodiments of the present disclosure may relate to a detector having an offset cancellation function canceling an offset of a detected voltage, and a power factor correction apparatus and a power supplying apparatus having the same. 
         [0003]    In general, a high efficiency power supplying apparatus having a simple structure and a small size and stably supplying power may be needed in devices, such as computers, printers, copy machines, monitors, communications terminals, and the like. 
         [0004]    The power supplying apparatus may impose limitations on harmonic content caused by an input terminal of an electronic device in order to reduce inefficient influence in an input power line and reduce interference in an external electronic device. A power factor correction apparatus, a power factor correction circuit, may be used to satisfy the limitations on the harmonic wave. The above-mentioned power factor correction apparatus uses a power factor correction mode, and may be classified as a passive mode power factor correction apparatus and an active mode power factor correction apparatus. Currently, active mode power factor correction apparatuses are more commonly used than passive mode power factor correction apparatuses. 
         [0005]    The active mode power factor correction apparatus is classified as a continuous conduction mode (CCM) power factor correction apparatus, a critical conduction mode (CRM) power factor correction apparatus, and a discontinuous conduction mode (DCM) power factor correction apparatus, depending on a waveform of a current flowing in an inductor adopted for use therein. 
         [0006]    Here, such a CRM power factor correction apparatus may detect the time when the current flowing in the inductor has a level of zero, in order to turn on a switch after a predetermined delay time. The inductor current may be sensed by a sensing resistor between a ground and an output in which alternating current (AC) power is rectified. Therefore, a voltage detecting circuit, for detecting a voltage having a level lower than 0V, may need to sense the current. 
       RELATED ART DOCUMENT 
       [0007]    U.S. Patent Application Publication No. 2003/0095421 
       SUMMARY 
       [0008]    Some embodiments of the present disclosure may provide a detector having an offset cancellation function, and a power factor correction apparatus and a power supplying apparatus having the same. 
         [0009]    According to an aspect of the present disclosure, a detector, detecting a level of an input signal, may include: a level shifter shifting the level of the input signal; and a comparator amplifying a voltage difference between the level of the signal shifted by the level shifter and a ground, and providing a compensation current according to an offset generated at the time of amplifying a voltage to cancel the offset. 
         [0010]    According to another aspect of the present disclosure, a power factor correction apparatus may include: a power factor correcting unit correcting a power factor of input power; a controlling unit controlling an operation of the power factor correcting unit according to an output signal of the power factor correcting unit and a detection signal obtained by detecting a level of the input power; and a detector detecting a current level of the input power to provide the detected current level to the controlling unit, amplifying the detected current level at the time of detecting the current level, and providing a compensation current according to an offset generated at the time of amplifying a voltage to cancel the offset. 
         [0011]    According to another aspect of the present disclosure, a power supplying apparatus may include: a power factor correcting unit correcting a power factor of input power; a power converting unit converting the power of which the power factor has been corrected by the power factor correcting unit into driving power and outputting the driving power; a controlling unit controlling an operation of the power factor correcting unit according to an output signal of the power factor correcting unit and a detection signal obtained by detecting a level of the input power; and a detector detecting a current level of the input power to provide the detected current level to the controlling unit, amplifying the detected current level at the time of detecting the current level, and providing a compensation current according to an offset generated at the time of amplifying a voltage to cancel the offset. 
         [0012]    The comparator may have an offset canceling period and a signal detecting period after the offset canceling period, and the offset canceling period and the signal detecting period may be repeated. 
         [0013]    The comparator may include a first transconductance amplifier amplifying the voltage difference between the level of the signal shifted by the level shifter and the ground; and a second transconductance amplifier providing a compensation current according to an offset generated by an amplification operation of the first transconductance amplifier. The first transconductance amplifier may have an output signal which is input to the second transconductance amplifier, and the output signal of the first transconductance amplifier and an output signal of the second transconductance amplifier may be combined and output. 
         [0014]    The comparator may further include: a first switch connected between an output terminal of the level shifter and an input terminal of the first transconductance amplifier; a second switch connected between a terminal of the first switch and the ground; a third switch connected between an output terminal of the first transconductance amplifier and an input terminal of the second transconductance amplifier; and a capacitor connected between the input terminal of the second transconductance amplifier and the ground. The comparator may further include an inverting amplifier invert-amplifying an output signal generated by using or combining the output signal of the first transconductance amplifier and the output signal of the second transconductance amplifier. 
         [0015]    The first and second switch may be turned-on and the third switch may be turned-off during the offset canceling period, and the first and second switches may be turned-off and the third switch may be turned-on during the signal detecting period. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0017]      FIG. 1  is a schematic circuit diagram of a power supplying apparatus according to an exemplary embodiment of the present disclosure; 
           [0018]      FIG. 2  is a schematic circuit diagram of a detector adopted in the power supplying apparatus illustrated in  FIG. 1 ; 
           [0019]      FIG. 3  is a schematic circuit diagram of a comparator illustrated in  FIG. 2 ; and 
           [0020]      FIGS. 4A ,  4 B, and  4 C are graphs illustrating main signal waveforms in a case in which an offset does not occur, a case in which a negative (−) offset occurs, and a case in which a positive (+) offset occurs, respectively. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. 
         [0022]    The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. 
         [0023]    In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements. 
         [0024]      FIG. 1  is a schematic circuit diagram of a power supplying apparatus according to an exemplary embodiment of the present disclosure. 
         [0025]    Referring to  FIG. 1 , a power supplying apparatus  100  according to an exemplary embodiment of the present disclosure may include a power factor correcting unit  120 , a controlling unit  130 , a detector  140 , and a power converting unit  150 . 
         [0026]    The power factor correcting unit  120  may correct a power factor by switching input power. In the case in which alternating current (AC) power is input to the power supplying apparatus  100 , power rectified by a rectifying unit  110  may be input to the power factor correcting unit  120 . 
         [0027]    The power factor correcting unit  120  may include an inductor L, a power switch SW, a diode D, and a capacitor Cout. 
         [0028]    The inductor L may charge/discharge and output power having a level of power rectified according to the switching operation of the power switch SW. Thus, for example, a voltage level may be increased and a phase difference between a voltage and a current may be corrected, thereby correcting a power factor. 
         [0029]    The diode D may provide a power transfer path. The capacitor Cout may stabilize the output power and transfer the stabilized power to the power converting unit  150 . 
         [0030]    The power converting unit  150  may convert the power having the power factor, corrected in the power factor correcting unit  120 , into driving power Vo, and output the converted driving power Vo. 
         [0031]    The controlling unit  130  may control the switching operation of the power switch SW depending on, for instance, but not limited to, a level of the power having the corrected power factor and/or a level of the rectified power. 
         [0032]    For example, the level of the rectified power may be a level of a current flowing in the inductor L, but not limited thereto. 
         [0033]    The detector  140  may detect the level of current flowing in the inductor L, and may also detect a zero current. 
         [0034]      FIG. 2  is a schematic circuit diagram of a detector adopted in the power supplying apparatus illustrated in  FIG. 1 . 
         [0035]    Referring to  FIG. 2 , the detector  140  may include a level shifter  141  and a comparator  142 . 
         [0036]    The level shifter  141  may be configured to include first and second resistors R 1  and R 2 . The first resistor R 1  may be connected to an input terminal to which a reference voltage Vref 1  is input, and the second resistor R 2  may be connected to a detecting terminal detecting the current flowing in the inductor L. A threshold voltage for the detection of the current by the detector  140  may be represented by Vcszcd and may be expressed by the following Equation 1. 
         [0000]        Vcszcd=−V ref1*( R 2 /R 1)  (Equation 1)
 
         [0037]      FIG. 3  is a schematic circuit diagram of the comparator illustrated in  FIG. 2 . 
         [0038]    Referring to  FIG. 3 , the comparator  142  may include first and second amplifiers Gm 1  and Gm 2 . The first and second amplifiers Gm 1  and Gm 2  may be, for example, but not limited to, transconductance amplifiers. In addition, the comparator  142  may include an inverting amplifier U 1 . 
         [0039]    The first amplifier Gm 1  may amplify a voltage difference between positive (+) and negative (−) input terminals of the comparator  142 . The second amplifier Gm 2  may perform an offset cancellation function. The inverting amplifier U 1  may amplify an output from the first amplifier Gm 1  so that a voltage output Vout by the comparator  142  may have relatively smooth waveform. 
         [0040]    In the case in which a voltage gain obtained by the first amplifier Gm 1  is sufficiently high, an input offset voltage of the comparator  142  may mainly occur from an input offset voltage of the first amplifier Gm 1  (therefore, only cancellation of the input offset voltage of the first amplifier Gm 1  will be considered). 
         [0041]    The comparator  142  may have an offset canceling period, and a signal detecting period after terminating the offset canceling period in an operating interval. The offset canceling period and the signal detecting period may be repeated. 
         [0042]    During a process in which the offset cancellation is performed, first and second switches SWc 1  and SWc 2  may be turned-on and a third switch SWd 1  may be turned-off. Thus, both input terminals of the first amplifier Gm 1  may be connected to a ground. In a case in which the input of the first amplifier Gm 1  does not have an offset voltage, a current output by the first amplifier Gm 1  may be ‘0’. Here, in order to adjust a balance in the comparator  142 , a level of a current output by the second amplifier Gm 2  may be 0. 
         [0043]    For a simple description, for example, if the second amplifier Gm 2  does not have an input offset voltage, a level of a voltage Vc stored in an offset cancellation capacitor Cc may be equal to that of a reference voltage Vref 2  of the second amplifier Gm 2 . 
         [0044]    On the other hand, for example, if the first amplifier Gm 1  has any offset voltage Voff 1 , the second amplifier Gm 2  may need to supply any current to compensate for the current output by the first amplifier Gm 1  by the offset voltage. Thus, the voltage Vc stored in the offset cancellation capacitor Cc may be expressed by the following Equation 2. 
         [0000]        Vc−V ref2 =V off1*( GM 1 /GM 2)  (Equation 2)
 
         [0045]    where GM 1  and GM 2  refer to transconductance of the first and second amplifiers Gm 1  and Gm 2 , respectively. Here, it can be indicated that when GM 1  is designed to be greater than GM 2  in the above-mentioned Equation 2, a small amount of the input offset voltage of the comparator  142  may be adjusted together with adjusting a relatively significant amount of voltage stored in the offset cancellation capacitor Cc. 
         [0046]    Here, an effect by an abnormal charge injected into the offset cancellation capacitor Cc from the second switch SWc 2  may be reduced. In addition, a level of a Gm 1  common mode voltage in a cancellation circuit may be 0, and this voltage may be the same common mode voltage for sensing. 
         [0047]    Meanwhile, during signal detection, the third switch SWd 1  may be turned-on and the first and second switches SWc 1  and SWc 2  may be turned-off. In order to perform the signal detection, the first amplifier Gm 1  may be operated together with the inverting amplifier U 1 . In this case, the second amplifier Gm 2  may continuously supply a current for compensation together with the supply of the voltage stored in the offset cancellation capacitor Cc. 
         [0048]    The first and second amplifiers Gm 1  and Gm 2  may be configured by, for example, but not limited to, a P channel MOSFET composed of a differential pair, and the currents supplied by the first and second amplifiers Gm 1  and Gm 2  may be added to each other, transferred to a current mirror (not illustrated), copied, and converted to be finally connected to an final output. As illustrated in  FIG. 3 , the first and second amplifiers Gm 1  and Gm 2  may share an output terminal. The inverting amplifier U 1  may be configured to include, for instance, but not limited to, a CMOS inverter and a common source amplifier configured of a P-channel MOSFET. The first to third switches SWc 1 , SWc 2 , and SWd 1  are configured to include, for example, but not limited to, an N-channel MOSFET, and the offset cancellation capacitor Cc may form a Cc value by capacitance of a gate terminal of the N-channel MOSFET of the third switch SWd 1 . 
         [0049]      FIGS. 4A ,  4 B, and  4 C are graphs illustrating main signal waveforms in a case in which an offset does not occur, a case in which a negative (−) offset occurs, and a case in which a positive (+) offset occurs, respectively. 
         [0050]    Referring to  FIGS. 3 ,  4 A,  4 B, and  4 C, waveforms when the offset voltage is 0V ( FIG. 4A ), −25 mV ( FIG. 4B ), and 25 mV ( FIG. 4C ) in the case in which the zero current is in a range of time of 2.5 μs to 7.5 μs are illustrated. The offset canceling operation may be performed after 7.5 μs. 
         [0051]    An input voltage Va of the first amplifier Gm 1  during the offset canceling period may be 0V, and an input voltage Vc of the second amplifier Gm 2  may have the same high level as those of an output voltage Vb and the output voltage Vout of the inverting amplifier U 1 . 
         [0052]    In a zero current detecting period, the input voltage Vc of the second amplifier Gm 2  may have the same voltage level as that in the offset canceling period, and the input voltage Va of the first amplifier Gm 1  may not be 0V, but may have a voltage level higher than a voltage level Vcs of a detection signal by 10 mV. The output voltage Vb and the output voltage Vout from the inverting amplifier U 1  may be changed to a level matched to that of the input voltage Va of the first amplifier Gm 1 . 
         [0053]    In detail, it may be appreciated that the input voltage Vc of the second amplifier Gm 2  may be set to a predetermined level matched to that of the offset voltage Voff, but the offset voltage Voff may not influence the output voltage Vout. Here, the cancellation of the offset voltage Voff may be verified. 
         [0054]    As set forth above, according to some exemplary embodiments of the present disclosure, the zero current detecting operation may be accurate, whereby malfunctioning of the circuit or a distribution problem in detecting IC characteristics may be solved. 
         [0055]    While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.