Abstract:
A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e.g., shallow trench isolation) and non-planar (e.g., thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for modeling a semiconductor structure. In particular, the present invention relates to a method for modeling capacitance in conductive regions in a semiconductor substrate. 
     2. Discussion of the Related Art 
     Accurate extraction of impedance (e.g., capacitance) is essential for evaluating and predicting the performance of an integrated circuit manufactured under a given manufacturing process. Accurate values of impedance can be obtained only with accurate modeling of semiconductor structures manufactured under that process. A number of techniques for accurate extraction of impedance from interconnect structures of a semiconductor structure are disclosed in U.S. Pat. No. 5,901,063 (the “&#39;063 Patent”), entitled “System and Method for Extracting Parasitic Impedance From an Integrated Circuit Layout,” Ser. No. 08/804,524, filed on Feb. 21, 1997, issued on May 4, 1999, and assigned to Frequency Technology, Inc., which is also the Assignee of the present application. The disclosure of the &#39;063 Patent is hereby incorporated by reference in its entirety. 
     FIGS. 1 a  and  1   b  depict corresponding cross-sectional and top views of a typical CMOS semiconductor structure  100  using a conventional thermal oxide isolation technique, showing only two conductor layers  101  and  102  above the substrate. In more recent integrated circuit processes, the number of conductor layers is typically more numerous than is shown in FIGS. 1 a  and  1   b , often consisting of multiple layers of polysilicon and metal. FIGS. 1 a  and  1   b  show two conductor layers merely for illustrative purposes. As shown in FIGS. 1 a  and  1   b , a semiconductor substrate  106  includes doped regions  106   a  and  106   b  of opposite conductivities, forming a P-well and an N-well for forming N-channel and P-channel transistors respectively. Thermal oxide regions  103   a ,  103   b ,  103   c  and  103   d  are provided to electrically isolate semiconductor regions  108   a ,  108   b  and  108   c  from each other. Thermal oxide regions  103   a - 103   d  are typically formed by the well-known LOCOS process that oxidize the substrate silicon surface at high temperature. Devices, such as transistors and capacitors, are formed within the semiconductor regions. 
     The first conductor layer  101  above substrate  106  is used to provide both device electrodes and interconnect conductor traces between device electrodes. For example, in FIGS. 1 a  and  1   b , conductors  101   b ,  101   c  and  101   e  may be used as gate electrodes, and conductors  101   a  and  101   d  can be used as interconnect conductor traces. Conductor layer  101  is typically provided by doped polysilicon. Conductor layer  101  is isolated from substrate  106  by one or more dielectric layers  111 . Conductors  101   a  and  101   d  are routed over thermal oxide regions  103   a  and  103   c . To form diffusion (e.g., source and drain regions for an active device) regions, a well-known self-aligned process step introduces impurities (“dopants”) into the regions  104   a ,  104   b ,  104   c ,  104   d ,  104   e  and  104   f , using interconnect conductor layer  101  as a masking layer. 
     A layer of dielectric  109  is provided to isolate conductor layer  101  from conductor layer  102 . Conductor layer  102  can be provided by either polysilicon or metal. Openings in dielectric layers  109  and  111  are provided and filled with a conductive material  105  to electrically connect (as “contacts”) conductors in conductor layer  101  or diffusion regions  104  with conductors in conductor layer  102 . For example, contacts  105   a  and  105   b  are provided to connect conductors  102   a  and  102   b  to diffusion regions  104   a  and  104   b , and contacts  105   c  and  105   d  are provided to electrically connect conductors  102   c  and  102   e  to conductors  101   c  and  101   e , respectively. 
     Because thermal oxide (e.g., thermal oxide formed under the LOCOS process) is much thicker than the portion of silicon substrate from which the thermal oxide is formed, thermal oxidation results in an undulating surface topography at the surface of the substrate, as shown in Figure la. Subsequent growth or depositions of materials, such as dielectric layers  111 , conductor  101  and dielectric layer  109 , are typically conformal to this surface topography, as can be seen in FIG. 1 a . In the prior art, the capacitance in an active area between an electrode and a conductive portion of the substrate (e.g., a source or a drain region) is evaluated with the operation of the active device, and a capacitance between a conductor line in the “field region” (e.g., thermal oxide regions  103   a  and  103   c ) and a conductive portion of the substrate is simply ignored because of the width of the field region. Under thermal oxide isolation, the width of the field region is relatively large because of the so-called bird&#39;s beak structure (e.g., bird&#39;s beak  112 ). 
     Recently, the width of the field region is greatly reduced by using deposited oxide isolation. One deposited oxide isolation technique is known as “shallow trench isolation” (STI), which is illustrated by FIGS. 2 a  and  2   b . FIGS. 2 a  and  2   b  depict corresponding cross-sectional and top views of a semiconductor structure  200 , which includes two interconnect conductor layers  201  and  202 . (To simplify discussion of the figures, like reference numerals are provided like features). Unlike semiconductor structure  100 , however, rather than providing thermal oxide regions  103   a - 103   d , shallow trenches are etched in substrate  106  to isolate areas  108   a ,  108   b  and  108   c . An oxide is then deposited over the surface of substrate  106  and to fill the trenches. A chemical-mechanical polishing (CMP) step planarizes the surface of substrate  106  by polishing the deposited oxide away from the surface of substrate  106 , thus providing the filled STI trenches  203   a ,  203   b ,  203   c  and  203   d . Dielectric layers  111 ,  109  and  110 , conductor layers  201  and  202 , and contacts layer  105  can be provided in substantially the same manner as dielectric layers  111 ,  109  and  110 , conductor layers  101  and  102  and contacts layer  105 , respectively, as discussed above with respect to FIGS. 1 a  and  1   b . Alternatively, after each layer of conductor material (i.e., conductor layers  201  and  202 ) is deposited, a CMP step can be applied to planarize the resulting surface, as shown in FIG. 2 a.    
     Because STI trenches  203   a - 203   d  can be made much narrower than corresponding thermal oxide regions  103   a - 103   d , capacitance between a conductor in the first conductor layer  201  (e.g., conductor  201   a  or  201   d ) and a conducting portion of the substrate(e.g., any of diffusion regions  104   a ,  104   c - 104   f ) can no longer be ignored. In addition, even though one goal of CMP is to provide a completely planarized surface, because of selectivity of the process and local non-uniformity, “dishing” can often occur. At submicron feature sizes, to achieve high performance, accurate extraction of impedance can be achieved only with accurate modeling of the conductor layers and the substrate. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a method extracts capacitance in a semiconductor structure including a substrate, and two or more conductor layers above the substrate. The method includes (a) computing the capacitance between each conductor in the conductor layers and conductors in the proximity of the conductor, without regard to any conductor that is in the substrate; (b) grouping the conductors in the conductor layers with the conductors in the substrate; and (c) computing the capacitance between each of the conductors in the conductor layers and the conductors within the substrate. An example of a conductor in the substrate is a diffusion region. The method of the present invention is applicable to conductive layers of polysilicon. 
     According to one embodiment, the capacitance between each conductor in the conductor layers and the conductors within the substrate is provided by an area-perimeter approximation. In one implementation, the area-perimeter approximation computes, for each conductor in the conductor layers overlapping a conductor in the substrate in an area, a parallel plate capacitance between the conductor in the conductor layers and the conductor in the substrate. Further, the area-perimeter approximation can include a capacitance between a lateral face of either one of the overlapping conductors along an edge of the area and a horizontal surface of the other one of the overlapping conductors. The same treatment can be given for capacitances between a lateral face of a conductor and a conductive region in the substrate. Alternatively, a 3-dimensional field server can be provided for even higher accuracy in calcuating the capacitance. 
     According to another aspect of the present invention, a method approximates the capacitance between a contact conductor and a conductor in a first conductor layer, the contact conductor being provided between a conductor in a second conductor layer and a diffusion region in the substrate. That method includes: (a) in a computer model, creating an open circuit between the contact conductor and the diffusion region by creating a gap between the contact conductor and the diffusion region; and (b) solving, using a 3-dimensional electric field solver, the capacitance between the contact conductor and the conductor in the first conductor layer. An alternative method includes: (a) in a computer model, replacing the contact conductor with a second conductor in the first conductor layer of comparable dimensions as the replaced contact conductor; and (b) computing a capacitance between the first and second conductors in the first conductor layer. 
     The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 a  and  1   b  depict corresponding cross-sectional and top views of a semiconductor structure  100  formed using a conventional thermal oxidation technique; semiconductor structure  100  includes two interconnect conductor layers  101  and  102 . 
     FIGS. 2 a  and  2   b  depict corresponding cross-sectional and top views of a semiconductor structure  200  formed using a shallow trench isolation (STI) technique; semiconductor structure  200  includes two interconnect conductor layers  201  and  202 . 
     FIG. 3 shows a configuration of conductors that includes conductor  301  in a conductor layer Mi i+1 , conductor  304  in a conductor layer M I , and conductors  302  and  303  in a conductor layer M I−1 . 
     FIG. 4 depicts a configuration  400  of conductors including conductors  401  and  402  immediately above substrate  106 , and diffusion regions  403  and  404  in substrate  406 . 
     FIG. 5 shows overlapping top conductor  510  and bottom conductor  512  of the two conductor layers immediately above the substrate, respectively. 
     FIGS. 6 a ,  6   b  and  6   c  show the raised, recessed and flat STI trench topographies modeled in one embodiment of the present invention. 
     FIG. 7 illustrates a method by which capacitance C CP  and capacitance C CS , corresponding respectively to the capacitance between contact  105   a  and conductor  201   b , and the capacitance between contact  105   a  and substrate  106   a.    
     FIG. 8 shows an alternative method of FIG.  7 . 
    
    
     To simplify the detailed description and to highlight corresponding elements in the figures, like reference numerals are assigned to like features. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides an accurate model to allow extraction of capacitance in planar (e.g., STI) and non-planar (e.g., thermal oxide isolation) semiconductor structures. The present invention is especially applicable to STI structures which includes “dummy” diffusion regions. Dummy diffusion regions are semiconductor regions between oxide-filled trenches. These semiconductor regions minimize dishing by limiting the length of the trenches, rather than to be used as source or drain regions. Because the first conductor layer above the silicon substrate is used as a masking layer during the introduction of impurities to form source and drain regions, exposed semiconductor regions become source and drain regions in active areas, and dummy diffusion areas outside the active areas. 
     One embodiment of the present invention uses a two-step process. First, capacitance for each interconnect conductor in each conductor layer above the substrate is extracted without consideration of the diffusion regions. This extraction can be accomplished, for example, using the method disclosed in the &#39;063 Patent incorporated by reference above. The method disclosed in the &#39;063 Patent maps each conductor in the layer being analyzed (“LBA”) and the neighboring conductors in the same conductor layer and the conductor layers immediately above and below the LBA to a “bin” representing a configuration of conductors having its parasitic capacitances already characterized and parameterized (e.g., using the well-known field solver “Raphael”). FIG. 3 illustrates this approach. As shown in FIG. 3, a configuration of conductors includes conductor  301  in a conductor layer M I+1 , conductor  304  in a conductor layer M i , and conductors  302  and  303  in a conductor layer M i−1 . In this method disclosed in the &#39;063 Patent, substrate  106  is a conducting plane. In one implementation of the method disclosed in the &#39;063 Patent, capacitance is calculated based on, among other parameters, the separation “d” between adjacent conductors in the LBA. A table of capacitance values is provided for various values of separation “d”. In one instance, for example, capacitance per micron is shown to range between 50-100 aF per micron length, depending on the value of “d”. 
     Next, when calculating the capacitances for the conductors in the first conductor layer above the substrate (e.g., layer  201  of FIG.  2 ), the diffusion regions are treated like any conductor (i.e., the STI trenches or the thermal oxide regions are treated like insulators). However, since it was found that capacitances between a conductor in the first conductor layer above the substrate and the diffusion regions vary only over a range of 35-50 aF per micron length, for a wide range of separations “d”, the dependence on separation “d” is disregarded. FIG. 4 depicts a configuration  400  of conductors including conductors  401  and  402  immediately above substrate  106 , and diffusion regions  403  and  404  in substrate  106 . In this embodiment, each capacitance in the conductor layers immediately above the LBA (obtained in the first step using the method disclosed in the &#39;063 Patent) is corrected by an area-perimeter approximation, rather than a 3-D field solution. 
     One area-perimeter approximation for overlapping conductors (as seen from the top view) is illustrated by FIG.  5 . FIG. 5 shows top conductor  510  and bottom conductor  512  of the two conductor layers immediately above the substrate, respectively. Conductors  510  and  512  overlap over an area defined by edges  501 ,  502 ,  503  and  504 , respectively, corresponding to capacitance C st1  between the side face of conductor  510  along edge  501  facing area  508  on the top face of conductor  512 , capacitance C sb1  between the side face of conductor  512  along edge  502  facing area  505  on the bottom face of conductor  510 , capacitance C st2  between the side face of conductor  510  along edge  503  facing area  506  on the top face of conductor  512 , and capacitance C sb2  between the side face of conductor  512  along edge  504  facing area  507  on the bottom face of conductor  510 . Capacitance C over  in overlap region  509  can be approximated by the capacitance of a parallel plate capacitor. As far as capacitance per unit length is concerned, C sb2  equals C sb1 , while C st1  equals C st2 . 
     Capacitances corresponding to non-overlapping conductors, e.g., capacitance C â ;  between an end face of conductor  201   c  and diffusion region  104   b  and capacitance C á  between a side face of conductor  201   a  and diffusion region  104   a , are also calculated. These capacitances (i.e., capacitances C st1 , C sb1 , C over , C α  and C β , collectively, “delta capacitances”) are used to correct the capacitances of the two conductor layers immediately above the substrate computed under the method of the &#39;063 Patent. 
     The area-perimeter approach does not require the 3-D geometry search used in the method of the &#39;063 Patent. Further, look-up tables under the present invention are much smaller than those used in the method of the &#39;063 Patent. It is found that the area-perimeter approach is sufficiently accurate for modeling capacitance between the interconnect conductor layers above the substrate and the diffusion regions. To correct for the local topography, different empirically determined look-up tables can be provided for calculating the delta capacitances. In one embodiment, three lookup tables corresponding to the raised, recessed and flat topographies of the STI trenches, respectively, are provided. These topographies are illustrated by FIGS. 6 a ,  6   b  and  6   c.    
     FIG. 7 illustrates a method by which capacitance C CP  and capacitance C CS , corresponding respectively to the capacitance between contact  105   a  and conductor  201   b , and the capacitance between contact  105   a  and substrate  106   a . FIG. 7 differs from the corresponding portion of FIG. 2 by showing a gap (i.e., creating an open circuit) between contact  105   a  and diffusion region  104   a . With gap  701 , the potentials on conductor  201   b , substrate  106   a  and contact  105   a  are independently determined in well-known field solvers such as “Raphael.” Consequently, the capacitances C CP  and C CS  are obtained. One needs only discard the capacitance C CD , which is merely the artifact capacitance created by the artificial open circuit between contact  105   a  and diffusion region  104   a.    
     Alternatively, same capacitances C CP  and C C  can be obtained by substituting contact  105   a  by an artificial conductor  201   t  of the layer  201 , such as illustrated in FIG.  8 . Capacitances C CP  and C C  can be obtained as the capacitance between conductors  201   a  and  201   t , and the capacitance between conductor  201   t  and substrate  106   a , using a field solver (e.g., Raphael), the method disclosed in the &#39;063 Patent discussed above, or the area-perimeter method discussed above. Contact  201   t  can be created in a “virtual” masking layer in the artwork of the layout of semiconductor structure  200 , substituting each of the contacts in layer  105  by an artificial conductor of the same drawn dimensions as the replaced contact in layer  105 . Where there are more than one conductor layer between conductor  202   a  and diffusion region  104   a , the method is slightly modified to include an artificial conductor of the same drawn dimensions for each conductor layer between conductor  202   a  and diffusion region  104   a.    
     The detailed description above is provided to illustrate the specific embodiments discussed above, and is not intended to be limiting. Numerous variations and modifications within the present invention are possible. The present invention is set forth in the following claims.