Abstract:
A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    Field of Invention 
         [0002]    This invention relates to a semiconductor process, and particularly relates to a semiconductor process capable of reducing contact resistance, and a semiconductor device that can be formed with the semiconductor process. 
         [0003]    Description of Related Art 
         [0004]    In the strained silicon technology for MOS transistors, a source/drain region of an NMOS transistor usually includes a strained silicon-phosphorus (SiP) epitaxial layer. A metal silicide is usually formed over the SiP layer to reduce the contact resistance. 
         [0005]    In a conventional process, the metal silicide is not formed until a contact hole is formed over and exposing the SiP epitaxial layer. Since SiP is easily oxidized during the period, native oxide is easily formed on the SiP epitaxial layer separating the same from the metal silicide, so that the contact resistance is raised. 
       SUMMARY OF THE INVENTION 
       [0006]    In view of the foregoing, this invention provides a semiconductor process capable of reducing contact resistance. 
         [0007]    This invention also provides a semiconductor device that can be formed with the semiconductor process of this invention. 
         [0008]    The semiconductor process of this invention is described below. A SiP epitaxial layer is formed serving as a source/drain region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer. 
         [0009]    The semiconductor device of this invention includes a SiP epitaxial layer serving as a source/drain region, a first metal silicide layer over the SiP epitaxial layer, a second metal silicide layer over the first metal silicide layer, and a contact plug over the second metal silicide layer. 
         [0010]    In an embodiment of the semiconductor device, the first metal silicide layer comprises a crystalline metal silicide layer, and the second metal silicide layer comprises an amorphous metal silicide layer. 
         [0011]    Because a crystalline metal silicide layer is formed on the SiP epitaxial layer to prevent oxidation, native oxide is not formed on the SiP epitaxial layer, so the contact resistance is lowered and a knob for Rc-tuning between NMOS and PMOS is provided. 
         [0012]    In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIGS. 1A, 2 and 3  illustrate, in a cross-sectional view, a semiconductor process according to an embodiment of this invention, and  FIG. 1B  illustrates, in a perpendicular cross-sectional view, the structure as shown in  FIG. 1A . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0014]    This invention will be further explained with the following embodiment and the accompanying drawings, which are not intended to restrict the scope of this invention. For example, although the device as illustrated in the embodiment is a metal-gate fin device, this invention can also be applied to another kind of fin device or 3D device or even a planar device of which the process includes forming a SiP epitaxial layer. 
         [0015]      FIGS. 1A, 2 and 3  illustrate, in a cross-sectional view, a semiconductor process according to an embodiment of this invention, and  FIG. 1B  illustrates, in a perpendicular cross-sectional view, the structure as shown in  FIG. 1A . 
         [0016]    Referring to  FIG. 1A / 1 B, silicon fin structures  100  for N-FinFETs are formed, an isolation layer  102  is formed filling in between the fin structures  100 , a sacrifice gate dielectric  104 , a sacrifice gate layer  106  and a sacrifice cap layer  108  are formed and patterned such that the patterned sacrifice gate layer  106  crosses over the fin structure  100 , a spacer  110  is formed on the sidewall of the patterned sacrifice gate layer  106 , a recess  112  is fol. lied in the fin structure  100  between the spacers  110 , and then a SiP epitaxial layer  114  is formed based on the recessed fin structure  100 , usually with in-situ N-doping. The SiP layer  114  may have a diamond-shaped head in the cross-sectional view showing the “fin” shape of the fin structure  100 , as shown in  FIG. 1B . 
         [0017]    After the SiP epitaxial layer  114  is grown, a post-SiP cleaning process is usually performed, possibly using SC1 (or APM as Ammonia/Peroxide Mix) for surface clean. 
         [0018]    Referring to  FIG. 2 , a metal layer  116  is formed in contact with the SiP epitaxial layer  114 . The metal layer  116  may include Ti/TiN, cobalt (Co), or nickel (Ni). A first metal silicidation reaction is performed by heating to form a crystalline metal silicide layer  118  directly on the SiP epitaxial layer  114 . The heating is possibly carried out by a rapid thermal process (RTP). The first metal silicidation reaction is possibly conducted at a temperature between 700° C. and 800° C. When the metal layer  116  includes Ti/TiN, the crystalline metal silicide layer  118  includes C54 TiSi. The thickness of the crystalline metal silicide layer  118  possibly ranges from 5 nm to 15 nm. 
         [0019]    After that, the remaining metal layer  116  or the unreacted metal is removed (not shown), leaving the crystalline metal silicide layer  118 . This process is usually called a stripping process. 
         [0020]    Referring to  FIG. 3 , after the gap between the sacrifice gates  106  is filled with an insulating layer  120 , a replacement metal gate (RMG) process is conducted. In the RMG process, the sacrifice cap layer  108 , the sacrifice gate dielectric  104  and the sacrifice gate layer  106  are removed leaving an opening, and then a gate dielectric layer  122 , a metal gate  124  and a cap layer  126  are formed in the opening. 
         [0021]    In addition, after the remaining metal layer  116  is removed but before the RMG process, SiGe epitaxial S/D regions may be formed for PMOS transistors (not shown). 
         [0022]    Referring to  FIG. 3  again, another insulating layer  128  is then formed over the resulting structure, a contact hole  130  is formed through the insulating layers  128  and  120 . A barrier metal layer is then formed in the contact hole  130 , possibly including a first metal layer  132  including Ti or Ni/Co, and a second metal layer  134  including TiN or WN. Accordingly, the barrier metal layer may possibly include Ti/TiN, Ni/Co/TiN, Ti/WN, or Ni/Co/WN. 
         [0023]    A second metal silicidation reaction between the barrier metal layer ( 132 ) and the SiP epitaxial layer  114  is performed by heating, by which silicon atoms pass through the crystalline metal silicide layer  118  for reaction, to form an amorphous metal silicide layer  136  on the crystalline metal silicide layer  118 . When the first metal layer  132  includes titanium, the amorphous metal silicide layer  136  includes α-TiSi. When the first metal layer  132  including Ni/Co, the amorphous metal silicide layer  136  contains nickel and cobalt. The heating is possibly carried out by a rapid thermal process (RTP). 
         [0024]    The second metal silicidation reaction is possibly conducted at a temperature between 550° C. and 600° C. The thickness of the amorphous metal silicide layer  136  may possibly range from 30 nm to 50 nm. 
         [0025]    In a particular embodiment, the metal layer  116  and the barrier layer  132 + 134  both include Ti/TiN, the crystalline metal silicide layer  118  includes C54 TiSi, and the amorphous metal silicide layer  136  includes α-TiSi. 
         [0026]    Thereafter, the contact hole  130  is filled with a metal material to form a contact plug  140 . The metal material of the contact plug  140  may include tungsten (W), cobalt, copper (Cu) or aluminum (Al). 
         [0027]    Because a crystalline metal silicide layer is formed on the SiP epitaxial layer to prevent oxidation, native oxide is not formed on the SiP epitaxial layer, so the contact resistance is lowered and a knob for Re-tuning between NMOS and PMOS is provided. 
         [0028]    This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.