Abstract:
An output pad circuit is provided that adjusts a driving output current size within the chip based on a control signal. Thus, the output pad circuit adjusts a driving output current size, without attaching an external buffer or exchanging the output pad circuit, when an external load size varies during a chip design. The output pad circuit includes a tri-state inverter having an output being a tri-state level when a control signal is low level, but operating as an inverter when the control signal is high level.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device, and more particularly, to an output pad circuit. 
     2. Background of the Related Art 
     As shown in FIG. 1, a related art output pad circuit includes an inverter IN1 for inverting an input data signal Din, and a CMOS inverter IN2 receiving an output of the inverter IN1. The inverter IN2 includes a PMOS transistor P1 and an NMOS transistor N1 coupled in series between a supply voltage Vcc and a ground voltage Vss. The gates of the NMOS transistor N1 and the PMOS transistor P1 are commonly coupled and receive the output of inverter IN1. An output pad circuit as shown in FIG. 2 is identical in composition to that of FIG. 1, except for the sizes of transistors P1, P2, N1, N2, i.e., the Beta ratios thereof. 
     The operation of the related art output pad circuit will now be described with reference to the accompanying drawings. First, when the input data signal Din is at a high level, the output value of the inverter IN1 becomes a low level, and the PMOS transistor P1 in the CMOS inverter IN2 is turned on in accordance with the output value of the inverter IN1. Accordingly, a high level data signal Dout is outputted through an output terminal. 
     When the input data signal Din is at a low level, the NMOS transistor N1 In the CMOS inverter IN2 is turned on in accordance with a high level output signal of the inverter IN1. Accordingly, a low level data signal Dout is outputted through the output terminal. The operation of the output pad circuit as shown in FIG. 2 is identical to that of FIG. 1. 
     Thus, the output pad circuits of FIGS. 1 and 2 function identically but are differentiated by respective sizes of the transistors P1, P2, N1, N2. Thus a respective size of an output driving current is different in accordance with the size of the respective transistors. Namely, the respective driving output currents of the inverters IN2, IN3 are different because of the sizes of the transistors P1, P2, N1, N2. 
     In comparing the inverter IN2 of the output pad circuit in FIG. 1 and the inverter IN3 of the output pad circuit in FIG. 2, PMOS transistor P2 and NMOS transistor N2 in inverter IN3 are respectively twice the respective size of PMOS transistor P1 and NMOS transistor N1 in inverter IN2. That is, the transistors are identical in length, but the transistors P2, N2 in the inverter IN3 are twice as the large as transistors P1, N1 in the inverter IN2 in width. 
     In such output pad circuits, the size of the output driving current is determined in accordance with that of the output transistors so that respective output pad circuits generate a proper output driving current value. The size of the output driving current of an output pad current is determined during a chip design by an external application connected to the corresponding output pad circuit. 
     That is, when the load on an output pad circuit is large, there is applied an output pad circuit having a correspondingly large output driving current. However, when a load on an output pad circuit is not large, the output pad circuit employs a correspondingly lesser output driving current. 
     In the related art output pad circuit, when the size of the output driving current of an output pad circuit does not match with an external load, an increased operation time for an external circuit or an increased peak current value during a level transition can occur. Namely, when the size of the output driving current in an output pad circuit is small compared to an external load, it takes more time for a voltage level to the external load to be assumed. To decrease the transition time, an external buffer circuit is required, or the preset output pad circuit in a chip can be replaced by an output pad circuit having a larger output driving current. 
     When the size of the output driving current in the output pad circuit is larger than an external load, a peak current value at a transition level of the output pad circuit becomes large enough to generate ground bouncing. As a result, an input/output ground fluctuates so that marginal driving voltages V iL , V iH  in the output pad circuit can vary, which leads to an erroneous operation in the chip. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to solve at least the above-described problems and disadvantages in the related art. 
     Another object is to provide a control signal which controls a driving output current of an output pad circuit. 
     Another object of the present invention to provide an output pad circuit using a tri-state inverter control signal. 
     A further object of the invention is to adjust the size of the output pad circuit in a chip interior without attaching a buffer or exchanging an output pad when an external load on the output pad circuit varies, for example, during a chip design. 
     To achieve the above-described objects and/or advantages in whole or in part, there is provided an output pad circuit using a tri-state inverter control signal including a first PMOS transistor and a first NMOS transistor respectively coupled in series between a supply voltage and a ground voltage and having respective gates receive an input data signal from an inverter. The output pad circuit further includes an additional tri-state inverter in which when a control signal is at a low level an output value of the tri-state inverter is rendered to a tri-state level. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein: 
     FIG. 1 is a schematic circuit diagram showing a related art output pad circuit used when a load on the output pad circuit is small; 
     FIG. 2 is a schematic circuit diagram showing a related art output pad circuit used when a load on the output pad circuit is large; 
     FIG. 3 is a schematic circuit diagram showing a preferred embodiment of an output pad circuit according to the present invention; and 
     FIG. 4 is a schematic circuit diagram showing another preferred embodiment of an output pad circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     As shown in FIG. 3, an output pad circuit according to a first preferred embodiment of the present invention includes an inverter IN1; a CMOS inverter IN2 and a tri-state inverter TIN1. The CMOS inverter IN2 includes a PMOS transistor P1 and an NMOS transistor N1 having commonly coupled gates that receive an output of the inverter IN1. The PMOS transistor P1 and the NMOS transistor N1 are coupled in series between a supply voltage Vcc and a ground voltage Vss. The tri-state inverter TIN1 includes an inverter IN4, PMOS transistors P3, P4 and NMOS transistors N3, N4. The transistors P3, P4, N3, N4 are coupled in series between the supply voltage Vcc and the ground voltage Vss. 
     A control signal CS is applied to the gate of the PMOS transistor P3 through the inverter IN4 and to the gate of NMOS transistor N4. The output of the inverter IN1 in the output pad circuit is applied to the gates of the PMOS transistor P4 and the NMOS transistor N3. An output terminal between the PMOS transistor P4 and the NMOS transistor N3 is coupled to an output terminal in the output pad circuit. When control signal CS is at a low level, an output of the tri-state inverter TIN1 assumes a tri-state level, and when control signal CS is at a high level, tri-state inverter TIN1 serves as an inverter. 
     Operations of the output pad circuit according to the first preferred embodiment will now be described. When the input data signal Din is at a high level and the control signal CS is at a low level, the output value of tri-state inverter TIN1 is rendered to a tri-state level. The PMOS transistor P1 is turned on in accordance with the low level signal outputted from inverter IN1 and the output data signal Dout from inverter IN2 becomes a high level. Therefore, the size of the output driving current is determined according to the size (c/0.8 μm) of the PMOS transistor P1 in the CMOS inverter IN2. 
     When input data signal Din and control signal CS are both at a high level, the PMOS transistors P3, P4 in the tri-state inverter TIN1 are turned on. Further, the NMOS transistor N3 is turned off. Thus, the tri-state inverter TIN1 outputs a high level data signal Dout. Also, the output driving current is determined in accordance with the size of the PMOS transistor P1 in CMOS inverter IN2 and the size of the PMOS transistors P3, P4 in tri-state inverter TIN1. 
     At this time, the output driving current of the tri-state inverter TIN1 is determined by the sizes of the pair of PMOS transistors P3 and P4 which are coupled in series to equal to an output driving current of a PMOS transistor having a size of c/0.8 μm. Further, the PMOS transistor P1 in the CMOS inverter IN2 and the PMOS transistors P3, P4 in tri-state inverter TIN1 are coupled in parallel with each other. Accordingly, the output driving current becomes equal to the output driving current of a PMOS transistor having a size of 2c/0.8 μm. In other words, the output driving current is doubled. 
     When the input data signal Din and the control signal CS are both respectively at a low level, an output value of the tri-state inverter TIN1 is a tri-state level and an output value of inverter IN2 becomes a low level. Thus, a low level output data signal Dout is outputted through the external output terminal. At this time, the output driving current is determined by the size d/0.8 μm of the NMOS transistor N1 in the CMOS inverter IN2. 
     When the input data signal Din is at a low level and the control signal CS is at a high level, the output value of the CMOS inverter IN2 is a low level, and the PMOS transistors P3, P4 in tri-state inverter TIN1 are turned off. However, the NMOS transistors N3, N4 are turned on so that the CMOS inverter IN2 and the tri-state inverter TIN1 respectively together output a low level data signal Dout. Consequently, the output driving current is determined by the sizes of the NMOS transistor N1 in the CMOS inverter IN2 and the size of the NMOS transistors N3, N4 in the inverter TIN1. 
     At this time, the output driving current of tri-state inverter TIN1 is determined by the pair of the NMOS transistors N3, N4, which are coupled in series to equal an output driving current of an NMOS transistor of a size d/0.8 μm. In the meantime, because the NMOS transistor N1 in the CMOS inverter IN2 and the NMOS transistors N3, N4 in the tri-state inverter TIN1 are respectively coupled in series, the output driving current serves to drive an output current of an NMOS transistor of a size 2d/0.8 μm. In other words, the output driving current is doubled. 
     As a result, the output pad circuit according to the first preferred embodiment employs the control signal CS of the tri-state inverter TIN1 to vary the size of the output driving current. In the first preferred embodiment, the output driving current is varied between a prescribed level and double the prescribed level. However, the present invention is not intended to be limited to this. For example, the output driving current could be varied between the prescribed level and predetermined ratios of the prescribed level. Thus, an increased change with regard to an external load at a chip design stage can be handled by adjusting the size of an output driving current within the chip. 
     As shown in FIG. 4, an output pad circuit according to a second preferred embodiment of the present invention replaces the tri-state inverter TIN1 of the first preferred embodiment with a tri-state inverter TIN2. The tri-state inverter TIN2 includes a NAND gate NA1 for NANDing the input data signal Din and the control signal CS, an AND gate AN1 for ANDing an output signal of inverter IN1 and control signal CS, a PMOS transistor P5 and an NMOS transistor N5. The PMOS transistor P5 and the NMOS transistor N5 are coupled in series between the supply voltage Vcc and the ground voltage Vss and the respective gates of which receive output values of the NAND gate NA1 and the AND gate AN1. 
     Operations of the output pad circuit according to the second preferred embodiment of the present invention, are similar to the first preferred embodiment. Thus, a detailed description will be omitted because the output driving current obtains similar results to the first preferred embodiment. 
     As described above, preferred embodiments of the output pad circuit according to the present invention employ control signals in tri-state inverters to vary a size of an output driving current. Thus, if there is a large change with regard to an external load at a chip design stage, the size of the output driving current can be adjusted within a chip to prevent an erroneous chip operation due to mismatching an output pad circuit and a corresponding external load. 
     The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.