Abstract:
Methods of operating a memory, and memories for performing such methods, include determining that a particular area of the memory is defective, locating a free area of the memory, programming data intended for the particular area of the memory to the free area of the memory, checking the particular area of the memory for data previously programmed to the particular area of the memory, and moving any previously-programmed data from the particular area of the memory to the free area of the memory.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/323,144 entitled “Memory for Accessing Multiple Sectors of Information Substantially Concurrently,” filed on Dec. 12, 2011 (allowed), which is a divisional of U.S. patent application Ser. No. 12/470,944 entitled “Increasing the Memory Performance of Flash Memory Devices by Writing Sectors Simultaneously to Multiple Flash Memory Devices,” filed on May 22, 2009, issued as U.S. Pat. No. 8,078,797 on Dec. 13, 2011, which is a continuation of U.S. patent application Ser. No. 11/404,570, of same title, filed on Apr. 13, 2006, issued as U.S. Pat. No. 7,549,013 on Jun. 16, 2009, which is a continuation of U.S. patent application Ser. No. 10/832,421 of the same title, filed on Apr. 26, 2004, issued as U.S. Pat. No. 7,111,140 on Sep. 19, 2006, which is a continuation of U.S. patent application Ser. No. 10/152,969 of the same title, filed May 20, 2002, issued as U.S. Pat. No. 6,728,851 on Apr. 27, 2004, which is a continuation of U.S. patent application Ser. No. 10/071,972 of the same title, filed Feb. 5, 2002, issued as U.S. Pat. No. 6,757,800 on Jun. 29, 2004, which is a continuation of U.S. patent application Ser. No. 09/705,474 of the same title, filed on Nov. 2, 2000, issued as U.S. Pat. No. 6,397,314 on May 28, 2002, which is a continuation of U.S. patent application Ser. No. 09/487,865 of the same title, filed Jan. 20, 2000, issued as U.S. Pat. No. 6,202,138 on Mar. 13, 2001, which is a continuation of U.S. patent application Ser. No. 09/030,697 of the same title, filed on Feb. 25, 1998, issued as U.S. Pat. No. 6,081,878 on Jun. 27, 2000, all of which applications are commonly assigned and incorporated in their entirety herein. 
     
    
     FIELD 
       [0002]    This invention relates to the field of digital systems, such as personal computers and digital cameras, employing nonvolatile memory as mass storage, for use in replacing hard disk storage or conventional film. More particularly, this invention relates to an architecture for increasing the performance of such digital systems by increasing the rate at which digital information is read from and written to the nonvolatile memory. 
       BACKGROUND 
       [0003]    With the advent of higher capacity solid state storage devices (nonvolatile memory), such as flash or EEPROM memory, many digital systems have replaced conventional mass storage devices with flash and/or EEPROM memory devices. For example, personal computers (PCs) use solid state storage devices for mass storage purposes in place of conventional hard disks. Digital cameras employ solid state storage devices in cards to replace conventional films. 
         [0004]      FIG. 1  shows a prior art memory system  10  including a controller  12 , which is generally a semiconductor (or integrated circuit) device, coupled to a host  14  which may be a PC or a digital camera. The controller  12  is further coupled to a nonvolatile memory bank  16 . Host  14  writes and reads information, organized in sectors, to and from memory bank  16  which includes a first nonvolatile memory chip  18  and a second nonvolatile memory chip  20 . Chip  18  includes: an I/O register  22  having a port  24  connected to a port  26  of controller  12  via a first bus  28  which includes 8 bit lines; and a storage area  30  coupled with I/O register  22 . Chip  20  includes: an I/O register  32  having a port  34  connected to a port  36  of controller  12  via a second bus  38  which includes 8 bit lines; and a storage area  40  coupled with I/O register  32 . The first and second buses  28 ,  38  are used to transmit data, address, and command signals between the controller and the memory chips  18  and  20 . The least significant 8 bits (LSBs) of 16 bits of information are provided to chip  18  via the first bus  28 , and the most significant 8 bits (MSBs) are provided to the chip  20  via the second bus  38 . 
         [0005]    Memory bank  16  includes a plurality of block locations  42  each of which includes a plurality of memory row locations. Each block location of the memory bank is comprised of a first sub-block  44  located in the first non-volatile memory chip, and a corresponding second sub-block  46  located in the second non-volatile memory chip. Each memory row location includes a first row-portion  48  and a corresponding second row-portion  50 . In the depicted embodiment each of the first and second row-portions  48  and  50  includes storage for 256 bytes of data information plus an additional 8 bytes of storage space for overhead information. Where a sector includes 512 bytes of user data and 16 bytes of non-user data (the latter commonly referred to as overhead information), 256 bytes of the user data and 8 bytes of the overhead information of the sector may be maintained in the first row portion  48  of chip  18  and the remaining 256 bytes of user data and remaining 8 bytes of overhead information of the same sector may be maintained in the second row portion  50  of chip  20 . Thus, half of a sector is stored in a memory row location  48  of chip  18  and the other half of the sector is stored in memory row location  50  of chip  20 . Additionally, half of the overhead information of each stored sector is maintained by chip  18  and the other half by chip  20 . 
         [0006]    In general, reading and writing data to flash memory chips  18  and  20  is time consuming Writing data to the flash memory chips is particularly time consuming because data must be latched in I/O registers  22  and  32 , which are loaded 1 byte at a time via the first and second buses, and then transferred from the I/O registers  22  and  32  to the memory cells of the flash memory chips  18  and  20  respectively. The time required to transfer data from the I/O registers to memory, per byte of data, is proportional to the size of the I/O registers and the size of the flash memory chip. 
         [0007]    During a write operation, controller  12  writes a single sector of information to memory bank  16  by: (1) transmitting a write command signal to each of chips  18  and  20  via buses  28  and  38  simultaneously; (2) transmitting address data to chips  18  and  20  specifying corresponding sub-blocks  44  and  46  of the chips via buses  28  and  38  simultaneously; and (3) sequentially transmitting a byte of user data to each of chips  18  and  20  via buses  28  and  38  simultaneously for storage in the corresponding sub-blocks  44  and  46 . The problem with such prior art systems is that while two bytes of information are written and read at a time, only one sector of information is accommodated at a time by the memory bank  16  during a write command initiated by the host  14 . 
         [0008]    Another prior art digital system  60  is shown in  FIG. 2  to include a controller  62  coupled to a host  64 , and a nonvolatile memory bank  66  for storing and reading information organized in sectors to and from nonvolatile memory chip  68 , included in the memory bank  66 . While not shown, more chips may be included in the memory bank, although the controller, upon command by the host, stores an entire sector in one chip. A block, such as block  0 , includes 16 sectors S 0 , S 1 , . . . , S 15 . Also included in the chip  68  is an I/O register  70 , which includes 512 bytes plus 16 bytes, a total of 528 bytes, of storage space. The controller transfers information between host  64  and memory  66  a byte at-a-time. A sector of 512 bytes of user data plus 16 bytes of overhead information is temporarily stored in the I/O register during a write operation and then transferred to one of the blocks within the memory device for storage thereof. During a read operation, a sector of information is read from one of the blocks of the memory device and then stored in the I/O register for transfer to the controller. An important problem with the prior art architecture of  FIG. 2  is that while a total of 528 bytes may be stored in the I/O register  36 , only one byte of sector information may be transferred at a time between the controller and the memory bank thereby impeding the overall performance of the system. 
         [0009]    Both of the prior art systems of  FIGS. 1 and 2  maintain LBA to PBA mapping information for translating a host-provided logical block address (LBA) identifying a sector of information to a physical block address (PBA) identifying the location of a sector within the memory bank. This mapping information may generally be included in volatile memory, such as a RAM, within the controller, although it may be maintained outside of the controller. 
         [0010]      FIG. 3  shows a table diagram illustrating an example of an LBA-PBA map  300  defined by rows and columns, with each row  302  being uniquely identified, addressed, by a value equal to that of the LBA received from the host divided by 16. The row numbers of  FIG. 3  are shown using hexadecimal notation. Thus, for example, row  10 H (in Hex.) has an address value equal to 16 in decimal. Each row  302  of map  300 , includes a storage location field  304  for maintaining a virtual PBA value, an ‘old’ flag field  306 , a ‘used’ flag field  308 , and a ‘defect’ flag field  310 . The flag fields provide information relating to the status of a block of information maintained within the memory bank (in  FIGS. 1 and 2 ). The virtual PBA field  304  stores information regarding the location of the block within the memory bank. 
         [0011]      FIG. 4  shows a table diagram illustrating an exemplary format for storage of a sector of data maintained in a memory bank. The virtual PBA field  304  ( FIG. 3 ) provides information regarding the location of a block  400  of information with each block having a plurality of sectors  402 . Each sector  402  is comprised of a user data field  404 , an ECC field  406 , an ‘old’ flag field  408 , a ‘used’ flag field  410  and a ‘defect’ flag field  412 . 
         [0012]    A further problem associated with prior art systems of the kind discussed herein is that the table  300  (in  FIG. 3 ) occupies much ‘real estate’ and since it is commonly comprised of RAM technology, which is in itself costly and generally kept within the controller, there is substantial costs associated with its manufacturing. Furthermore, as each row of table  300  is associated with one block of information, the larger the number of blocks of information, the larger the size of the table, which is yet an additional cost for manufacturing the controller and therefore the digital system employing such a table. 
         [0013]    What is needed is a digital system employing nonvolatile memory for storage of digital information organized in sector format for reducing the time associated with performing reading and writing operations on the sectors of information thereby increasing the overall performance of the system while reducing the costs of manufacturing the digital system. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a block diagram of a prior art memory system in which a single sector of information is written, two bytes at a time during a write operation, to a memory bank including two memory units each having capacity to store 256 bytes of user data in a single row location. 
           [0015]      FIG. 2  is a block diagram of a prior art memory system in which a single sector of information is written, one byte at a time during a write operation, to a memory bank including at least one memory unit having capacity to store 512 bytes of user data in a single row location. 
           [0016]      FIG. 3  is a table diagram illustrating an exemplary map for translating a host-provided logical block address (LBA) identifying a sector of information to a physical block address (PBA) identifying a location for the sector within a memory bank. 
           [0017]      FIG. 4  is a table diagram illustrating an exemplary format for storage of a sector of data maintained in a memory bank. 
           [0018]      FIG. 5  is a generalized block diagram of a memory system in accordance with the present invention in which two sectors of information are written, two bytes at a time during a single write operation, to a memory bank including at least two memory units each having capacity to store 512 bytes of user data in a single row location. 
           [0019]      FIG. 6  is a detailed block diagram of the memory system of  FIG. 5 . 
           [0020]      FIG. 6   a  is a first portion of the detailed block diagram of  FIG. 6 . 
           [0021]      FIG. 6   b  is a second portion of the detailed block diagram of  FIG. 6 . 
           [0022]      FIG. 7  is a table diagram generally illustrating a memory storage format for storing a block, including 32 sectors, of information in a memory bank including two non-volatile memory units wherein an even sector and an odd sector are stored in a single memory row location and wherein even data bytes of both sectors are stored in a row portion located in a first of the memory units and odd data bytes of both sectors are stored in a second row portion located in the second of the memory units. 
           [0023]      FIG. 8A  is a table diagram generally illustrating organization of an exemplary LBA-PBA map for use in accordance with the present invention. 
           [0024]      FIG. 8B  shows a block diagram illustrating formats of address information identifying sectors and associated blocks of information in accordance with the present invention. 
           [0025]      FIG. 9  is a timing diagram illustrating the timing of control, address, and data signals for a write operation performed by the memory system of  FIG. 6  wherein two sectors of information are simultaneously written, during a single write operation, to a memory bank having the memory storage format illustrated in  FIG. 7 . 
           [0026]      FIG. 10  is a table diagram illustrating a memory bank having a memory storage format as depicted in  FIG. 7  wherein a single sector is written to a particular memory row location of the memory bank. 
           [0027]      FIG. 11  is a table diagram illustrating a memory bank having an alternative memory storage format as depicted in  FIG. 7  wherein a single sector is written to a particular memory row location of the memory bank. 
           [0028]      FIG. 12  is a flowchart illustrating a process of simultaneously writing two sectors of information to two memory units during a single write operation in accordance with the present invention. 
           [0029]      FIG. 12-1  is a first portion of the flowchart of  FIG. 12 . 
           [0030]      FIG. 12-2  is a second portion of the flowchart of  FIG. 12 . 
           [0031]      FIG. 12   a  shows a flow chart of the steps performed in executing the defect management routine of  FIG. 12 . 
           [0032]      FIG. 13  is a table diagram generally illustrating an alternative memory storage format for storing a block, including 32 sectors, of information in a memory bank including two non-volatile memory units wherein an even sector and an odd sector are stored in a single memory row location and wherein an even sector is stored in a first row portion located in a first of the two memory units and an odd sector is stored in a second row portion located in the second of the two memory units. 
           [0033]      FIG. 14  shows a timing diagram illustrating the timing of control, address, and data signals for a process of erasing a block of a memory bank in accordance with principles of the present invention. 
           [0034]      FIG. 15  is a flowchart illustrating a process of erasing a block, including a first sub-block stored in a first memory unit and a second sub-block stored in a second memory unit, in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0035]      FIG. 5  shows a generalized block diagram at  500  of a memory system in accordance with principles of the present invention. The system includes a memory card  502  coupled to a host system  504 . In one embodiment, host  504  is a digital camera and memory card  502  is a digital film card, and in another embodiment, host  504  is a personal computer system and memory card  502  is a PCMCIA card. Memory card  502  includes: a non-volatile memory bank  506  including a plurality of non-volatile memory units  508  for storing sectors of information organized in blocks; a memory controller  510  coupled to the memory bank via a memory bus  512 , and coupled to the host  504  via a host bus  514 . Memory controller  510  controls transfer of sector-organized information between host  504  and memory bank  506 . Each sector of information includes a user data portion and an overhead portion. The memory controller performs write and read operations, in accordance with the present invention, to and from the memory units of the memory bank as further explained below. 
         [0036]    In the present invention, the non-volatile memory bank  506  may include any number of non-volatile memory units  508  while in a preferred embodiment, the non-volatile memory bank has an even number of memory units. Also in the preferred embodiment, each of the non-volatile memory units is a flash memory integrated circuit device. 
         [0037]      FIG. 6  shows a detailed block diagram at  600  of the memory system of  FIG. 5 .  FIG. 6   a  is a first portion of the detailed block diagram of  FIG. 6 .  FIG. 6   b  is a second portion of the detailed block diagram of  FIG. 6 . Controller  510  is shown to include: a host interface  610  connected to the host  504  via host bus  514  for transmitting address, data, and control signals between the controller and the host; a data buffer  614  having a port  616  coupled to a port  618  of the host interface; a microprocessor  620  having a port  622  coupled to a port  624  of the host interface; a code storage unit  626  having a port  628  coupled to a port  630  of the microprocessor; a boot ROM unit  632  having a port  634  coupled to port  630  of the microprocessor and to port  628  of the code storage unit; a space manager  636  having a port  638  coupled to a port  640  of the microprocessor; a flash state machine  642  including a port  644  coupled to a port  646  of the microprocessor, a port  648  coupled to a port  650  of the space manager, and a port  645  coupled to a port  647  of the data buffer; a memory input/output unit  652  having a port  654  coupled to a port  656  of the flash state machine; an error correction code logic unit (ECC logic unit)  660  having a port  662  coupled to a port  664  of the flash state machine, and a port  666  coupled to a port  668  of the data buffer  614 . 
         [0038]    In the depicted embodiment, memory bank  506  includes two non-volatile memory units (although additional memory units may be included, only two are shown for simplicity); a first flash memory chip  670  designated FLASH 0  and a second flash memory chip  672  designated FLASH 1 . First flash memory chip  670  includes a first input/output register (first I/O register)  671  and a storage area  669 . Second flash memory chip  672  includes a second input/output register (second I/O register)  673  and a storage area  674 . 
         [0039]    Memory bus  512  is used to transmit address, data, and control signals between the controller  510  and memory bank  506 . Memory bus  512  includes a flash bus  675  connected to a port  676  of memory I/O unit  652  for transmitting address, data, and command signals between flash memory chips  670 ,  672  and the memory I/O unit  652 . Flash bus  675  includes 16 bit lines, 8 bit lines of which form a first bus  680  connected to a port  682  of I/O register  671  of the first flash memory chip, and another 8 bit lines of which form a second bus  684  connected to a port  686  of I/O register  673  of the second flash memory chip. 
         [0040]    Memory bus  512  also includes: a control bus  690  which connects a control signal (CTRL signal) output  692  of the flash state machine  642  to an input  694  of the first flash memory chip and to an input  696  of the second flash memory chip; a chip enable line  698  which connects a chip enable (CE) output  700  of the flash state machine  642  to an enable input  702  of the first flash memory chip and to enable an input  704  of the second flash memory chip; and a ready/busy signal (FRDY-BSY* signal) line  706  which connects an output  708  of the first flash memory chip and an output  710  of the second flash memory chip to an input  712  of the flash state machine  642 . 
         [0041]    Microprocessor  620 , at times (for example, during initialization of the memory system), executes program instructions (or code) stored in ROM  632 , and at other times, such as during operation of the memory system, the microprocessor executes code that is stored in code storage unit  626 , which may be either a volatile, i.e., read-and-write memory (RAM) or a non-volatile, i.e., EEPROM, type of memory storage. Prior to the execution of program code from code storage unit  626 , the program code may be stored in the memory bank  506  and later downloaded to the code storage unit for execution thereof. During initialization, the microprocessor  620  can execute instructions from ROM  632 . 
         [0042]    Sector-organized information, including user data and overhead information, is received at host interface  610  from host  504  via host bus  514  and provided to the data buffer  614  for temporary storage therein. Sectors of information stored in the data buffer are retrieved under control of flash state machine  642  and provided to memory bank  506  in a manner further described below. It is common in the industry for each sector to include 512 bytes of user data plus overhead information. Although a sector may include other numbers of bytes of information, in the preferred embodiment, a sector has 512 bytes of user data and 16 bytes of overhead information. 
         [0043]    ECC logic block  660  includes circuitry for performing error coding and correction on the sector-organized information. ECC logic block  660  performs error detection and/or correction operations on the user data portions of each sector stored in the flash memory chips  670 ,  672  or data received from host  504 . 
         [0044]    When required, the space manager  636  finds a next unused (or free) non-volatile memory location within the memory bank for storing a block of information with each block including multiple sectors of information. In the preferred embodiment, a block includes 32 sectors although, alternatively a block may be defined to include another number of sectors such as, for example, 16. The physical address of a storage block located within memory bank  506 , referred to as a virtual physical block address (virtual PBA), and the physical block address of a sector of information located within the memory bank  506 , referred to as an actual physical block address (actual PBA), is determined by the space manager by performing a translation of a logical block address (LBA) received from the host. An actual LBA received from host  504  (a host-provided LBA) identifies a sector of information. Space manager  636  includes a space manager memory unit, which is preferably a volatile memory unit, for storing an LBA-PBA map for translating a modified version of the host-provided LBAs to virtual PBAs as further explained below. In the depicted embodiment, the space manager includes a space manager RAM unit (SPM RAM unit)  720  for storing the LBA-PBA map under the control of a space manager controller (SPM controller)  724  which is coupled to the SPM RAM unit. 
         [0045]      FIG. 7  shows a table diagram generally illustrating organization of user data, error correction information, and flag information stored in memory bank  506  in accordance with an embodiment of the present invention. Memory bank  506  includes a plurality of M blocks  727  designated BLCK 0 , BLCK 1 , BLCK(M-1), each having a virtual physical block addresses (PBA). Each of the blocks  727  includes a plurality of N memory row locations  728  designated ROW 0 , ROW 1 , . . . ROW 15  where, in the preferred embodiment, N=16. Each block  727  of memory bank  506  is comprised of a first sub-block  730  of first flash memory chip  670 , and a corresponding second sub-block  731  of second flash memory chip  672 . Corresponding sub-blocks  730 ,  731 , which together form a block, are identified by the same virtual PBA. Each memory row location  728  includes a first row-portion  732  and a corresponding second row-portion  733  In the depicted embodiment each of the first and second row-portions  732 ,  733  includes storage for 512 bytes of data information plus additional storage space for other information. In the depicted embodiment, the storage of information in the first row-portions  732  of the first flash memory chip is accomplished in a manner dissimilar from that in the second row-portions  733  of the second flash memory chip. 
         [0046]    Each of the first row-portions  732  includes: a first even sector field  734  for storing even data bytes D 0 , D 2 , D 4 , . . . D 510  of an even sector (S 0 , S 2 , S 4 , . . . ) of information; a first spare field  736 ; a first odd sector field  738  for storing even data bytes D 0 , D 2 , D 4 , . . . D 510  of an odd sector (S 1 , S 3 , S 5 , . . . ) of data; and a second spare field  740 . Each of the second row-portions  733  includes: a second even sector field  742  for storing odd data bytes D 1 , D 3 , D 5 , . . . D 511  of the even sector of data which has its corresponding even data bytes stored in first even sector field  734 ; a first error correction field  744  for storing error correction information corresponding to the even sector of information stored collectively in fields  734  and  742 ; a second odd sector field  746  for storing odd data bytes of the odd sector of information which has it&#39;s even data bytes stored in first odd sector field  738 ; a second error correction field  748  for storing ECC information corresponding to the odd sector of information stored collectively in fields  738  and  746 ; a block address field  750 ; and a flag field  752 . Fields  734  and  742  form an even sector location while fields  738  and  746  form an odd sector location. It is understood in the present invention that fields  734  and  742  could alternatively form an odd sector location while fields  738  and  746  could alternatively form an even sector location, and that fields  734  and  738  could alternatively be used to store odd data bytes while fields  742  and  746  could alternatively be used to store even data bytes. Additionally, first row-portion  732  could alternatively be used for storing the overhead information relating to the sectors stored in the memory row location  728 . 
         [0047]    Flag field  752  is used for storing flag information which is used by controller  510  ( FIG. 6 ) during access operations as further explained below. Block address field  750  is used for storing a modified version of a host-provided LBA value which is assigned to a block, as further described below. Only a single block address entry is required in the block address field per block. In a preferred embodiment, a modified host-provided LBA value is entered in block address field  759  of the Nth row, ROW  15 , of the row locations  728  of each block  727 . 
         [0048]    In operation, the controller  510  ( FIG. 6 ) accesses an even sector of information stored collectively in the first and second flash memory chips by simultaneously accessing first and second even sector fields  734 ,  742  of corresponding row-portions of the first and second flash memory chips via the first and second split buses  680 ,  684  ( FIG. 6 ), respectively. The first and second split buses  680 ,  684  ( FIG. 6 ) include lines coupled to receive the even and odd data bytes respectively of a sector of information. The controller  510  ( FIG. 6 ) accesses an odd sector of information stored collectively in the first and second flash memory chips by simultaneously accessing the first and second odd sector fields  738 ,  746  via the first and second split buses  680 ,  684  ( FIG. 6 ), respectively. The split buses  680 ,  684  ( FIG. 6 ) also provide for: transmission of ECC information between the flash memory chips and the flash state machine  642  and ECC logic unit  660  of the memory controller  510 ; and transmission of address information from flash state machine  642  to the flash memory chips. 
         [0049]    Controller  510  ( FIG. 6 ) monitors the status of blocks  727  of memory bank  506  using the space manager  636 . In one embodiment, controller  510  ( FIG. 6 ) monitors the status of each block location  727  of the memory bank using block level flags including a used/free block flag and a defect block flag stored in a used flag location  754  and a defect flag location  756  respectively of the flag field  752 . Block level flags provide information concerning the status of a whole block  727  of the memory bank and therefore, only a single block level flag entry is required in the flag locations  754  and  756  per block. The used/new block flag indicates whether the corresponding block  727  is currently being “used” to store information or whether it is available (or free) to store information. The defect block flag indicates whether the corresponding block  727  is defective. 
         [0050]    In another embodiment, controller  510  ( FIG. 6 ) monitors the status of each memory row location  728  of the memory bank using flags including a used/free row flag stored in the used flag location  754 , a defect row flag stored in the defect flag location  756 , an old row flag stored in an old flag location  758  of the flag field  752 , an even sector move flag stored in an even sector move flag location  760 , and an odd sector move flag stored in an odd sector move flag location  762 . In this embodiment, the used/new flag indicates whether the corresponding memory row location  728  is currently being “used” to store information or whether it is available (or free) to store information. The defect flag indicates whether the memory block  727  is defective. If either of a corresponding pair of non-volatile memory locations  732 ,  733  is determined to be defective, then the whole memory block  727  is declared to be defective as indicated by the value in the defect flag location  756  being set, and the defective block can no longer be used. In a preferred embodiment, locations  758 ,  754 , and  756  are included in a single 3-bit flag location  764 . 
         [0051]    The even and odd sector move flag locations  760 ,  762  store values indicating whether the corresponding even and odd sectors stored in the non-volatile memory sector location have been moved to another location within the non-volatile memory bank  506  ( FIG. 6 ). For example, if an even sector of information stored collectively in a particular pair of even sector fields  734 ,  742  of a row location  728  has been moved to another pair of even sector fields in the non-volatile memory bank  506 , the value in the corresponding even sector move flag location  760  is set. Similarly, if an odd sector of information stored collectively in the odd sector fields  738 ,  746  of the same row location has been moved to another pair of odd sector fields in the non-volatile memory bank, then the value in the corresponding odd sector move flag location  672  is set. The location within the non-volatile memory bank  506  to which a sector of information has been moved is indicated in the LBA-PBA map stored in the SPM RAM  720  in an MVPBA address location, as taught in a patent application, filed by the inventors of this application, entitled “Moving Sectors Within a Block of Information In a Flash Memory Mass Storage Architecture”, Ser. No. 08/831,266, filed Mar. 31, 1997, the disclosure of which is incorporated herein by reference. In a preferred embodiment, locations  760  and  762  are formed by a single 2-bit move-flag location  766 . 
         [0052]      FIG. 8A  shows a table diagram generally illustrating organization of an exemplary LBA-PBA map at  800 , which is stored in SPM RAM  720  ( FIG. 6 ), for translating a modified version of the host-provided LBA&#39;s to PBA&#39;s. The modified host-provided LBA is derived by dividing the host-provided LBA by the number of sectors with a block, as explained in more detail below. The depicted LBA-PBA map includes: a plurality of map row locations  802  which are addressable by a modified host-provided LBA or by a virtual PBA; a virtual PBA field  804  for storing a virtual PBA value identifying a block  727  ( FIG. 7 ) within the memory bank; and a flag field  806  for storing flag information. As previously mentioned, the actual PBA specifies the location of a sector of information in the memory bank and the virtual PBA specifies the location of a block  727  ( FIG. 7 ) in the memory bank. Virtual PBA values are retrieved by space manager  636  ( FIG. 7 ) from the depicted map and transferred to port  648  of the flash state machine  642  for use in addressing blocks within memory bank  506 . 
         [0053]      FIG. 8B  shows a block diagram illustrating a host-provided-LBA format  810  and an actual PBA format  820 . LBA format  810  includes “offset bits”  812 , which comprise the least significant bits of the host-provided LBA value. As explained above, in the preferred embodiment, each block  727  ( FIG. 7 ) includes memory space for storing 32 sectors of information, each sector includes 512 bytes of user data and 16 bytes of overhead information. Because each block  727  ( FIG. 7 ) includes 32 sectors in the preferred embodiment, five offset bits  812  are required to identify each of the 32 sectors in each block. In this embodiment, the translation of the host-provided-LBA to actual and virtual PBA values is performed by first masking the five least significant “offset” bits  812 , of the host-provided-LBA, shifting the result to the right by 5 bits and using the shifted value as a modified host-provided LBA value or an “LBA-map-value” to address a map row location  802  in the LBA-PBA map  800  ( FIG. 8A ). This, in effect, is dividing the host-provided LBA by 32. The actual PBA value  820 , which specifies the location of a sector within a block of the memory bank, is formed by concatenating offset bits  812  of the LBA value with a virtual PBA  822  value stored in the corresponding field  804  ( FIG. 8A ) of the LBA-PBA map. That is, the virtual PBA value  822  is used to identify a block within the memory bank and the five remaining offset bits  812  are used to address a sector within the identified block. 
         [0054]    Upon initialization of memory system  600  ( FIG. 6 ), the virtual PBA value stored in the virtual PBA field  804  of each map row location  802  is set to an all ‘1’s state. Each time a block  727  ( FIG. 7 ) is accessed by the controller, such as during a write operation, the virtual PBA value stored in the corresponding virtual PBA field  804  of the corresponding map row location is modified by the space manager controller  724  ( FIG. 6 ) to specify a new virtual PBA value. When a block within the memory bank  506  is erased, the old virtual PBA value (the virtual PBA value corresponding to the erased block), rather than a modified version of the host-provided LBA, is used to address the SPM RAM  720  ( FIG. 6 ) and the used flag, stored within the flag field of the SPM RAM  720 , is cleared. This same ‘used’ flag within the flag field of the SPM RAM  720  is set at the time when the corresponding virtual PBA is updated pointing to the new block in the memory bank where sector information is maintained (step  1214 ). 
         [0055]      FIG. 9  shows a timing diagram illustrating the timing of control, address, and data signals for a write operation performed by memory system  600  ( FIG. 6 ) wherein two sectors of information are simultaneously written in the non-volatile memory bank  506  ( FIG. 6 ) during a single write operation. The diagram includes: a wave form  902  representing a first flash signal which transmits time multiplexed command, address, and data information from flash state machine  642  ( FIG. 6 ) of the controller via bus  680  ( FIG. 6 ) to port  682  of the first flash memory chip; a wave form  904  representing a second flash signal which transmits time multiplexed command, address, and data signals from the flash state machine via bus  684  ( FIG. 6 ) to port  686  of the second flash memory chip; a time line  905 ; and a plurality of control signal wave forms. 
         [0056]    The control signal wave forms include: a wave form  906  representing a command line enable signal (CLE signal) transmitted from flash state machine  642  ( FIG. 6 ) to the first and second flash memory chips via control bus  690  ( FIG. 6 ); a wave form  908  representing an address line enable signal (ALE signal) transmitted from the flash state machine to the flash memory chips via the control bus; a wave form  910  representing a write enable signal (WE signal) transmitted from the flash state machine to the flash memory chips via the control bus; a wave form  912  representing a read enable signal (RE signal) transmitted from the flash state machine to the memory chips via the control bus; a wave form  914  representing a flash chip enable signal (FCE* signal) transmitted from chip enable signal output  700  ( FIG. 6 ) of the flash state machine via chip enable line  698  to the first and second flash memory chips; a wave form  916  representing a flash ready/busy signal (FRDY_BSY* signal) transmitted from outputs  708  and  710  ( FIG. 6 ) of the first and second flash memory chips to the flash state machine via flash ready/busy signal line  706 . 
         [0057]    The write operation commences at a time to at which the FCE* signal (wave form  914 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to begin receiving command, address, data, and control signals. Prior to time t 0 , the FRDY_BSY* signal (wave form  916 ), transmitted from the flash memory chips to input  712  of the flash state machine ( FIG. 6 ), is already activated indicating that the first and second flash memory chips are ready to receive access commands. At a subsequent time t 1 , the CLE signal (wave form  906 ) is activated, transitioning from a LOW state to a HIGH state, thereby enabling the first and second flash memory chips to read command signals. At a time t 2 , the first and second flash signals (wave forms  902  and  904 ) simultaneously transmit a serial data shift-in command signal  80 H to the first and second flash memory chips via the first and second first split buses  680  and  684  respectively. At a time t 3 , while the serial data shift-in command signals  80 H are active, the WE signal (wave form  910 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to read the serial data command signals  80 H. At a time t 4 , the CLE signal (wave form  906 ) is deactivated, transitioning back to the LOW state, thereby disabling the flash memory chips from reading command signals. 
         [0058]    Also at time t 4 , the ALE signal (wave form  908 ) is activated, transitioning from a LOW state to a HIGH state, thereby enabling the first and second flash memory chips to read packets of address information. At times t 5 , t 6 , and t 7 , the first and second flash signals (wave forms  902  and  904 ) each transmit first, second, and third address packets ADD 0 , ADD 1 , and ADD 2  respectively to the first and second flash memory chips. At a time t 8 , the ALE signal (wave form  908 ) is deactivated, transitioning from the HIGH state to a LOW state, thereby disabling the first and second flash memory chips from reading address information. During time intervals between times t 5  and t 6 , t 6  and t 7 , and t 7  and t 8 , the WE signal (wave form  910 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to read the read the first, second, and third address packets ADD 0 , ADD 1 , and ADD 2  respectively. The three address packets ADD 0 , ADD 1 , and ADD 2  specify a row-portion  732 ,  733  within a first sub-block  730  ( FIG. 16 ). 
         [0059]    At a time t 9 , the first and second flash signals (wave forms  902  and  904 ) begin simultaneously transmitting interleaved even and odd data bytes wherein the even and odd bytes form one sector of information. The even bytes are transmitted to the first flash memory chip via bus  680  ( FIG. 6 ) and the odd sector bytes are transmitted to the second flash memory chip via bus  684  ( FIG. 6 ). The even data bytes D 0 , D 2 , D 4 , . . . D 510  of the even sector are received by the first flash chip and stored in the first even sector field  734  ( FIG. 16 ) of the corresponding location  732  of the first flash memory chip. This is done by storing a byte each time the write enable signal WE* (Wave form  910 ) is activated. The odd data bytes D 1 , D 3 , D 5 , . . . D 511  of the even sector are received by the second flash chip and stored in the second even sector field  742  ( FIG. 16 ) of the corresponding location  733  thereof with each byte being stored when the WE* signal is activated. At a time t 10 , the first and second flash signals (wave forms  902  and  904 ) complete transmission of the interleaved even and odd data bytes of the even sector: 
         [0060]    Immediately after time t 10 , during an interval between time t 10  and a time t 11 , the first flash signal (wave form  902 ) transmits four packets of filler information (FFH, hexadecimal F, equivalent binary value “1111,” decimal value “15”) to the first flash memory chip via the first split bus  680  ( FIG. 6 ) while the second flash signal (wave form  904 ) transmits error correction codes (ECC) to the second flash memory chip via the second split bus  684  ( FIG. 6 ). The filler information FFH transmitted during this time period is received by the first flash memory chip and stored in the first spare field  736  ( FIG. 16 ). The error correction code transmitted during this time period is received by the second flash memory chip and stored in the first error correction field  744  ( FIG. 16 ) of the nonvolatile memory section  733  of the second flash memory chip. This error correction code, generated by ECC logic unit  660  ( FIG. 16 ), relates to the even sector transmitted during the preceding time interval between time t 10  and t 11 . 
         [0061]    At a time t 11 , the first and second flash signals (wave forms  902  and  904 ) begin simultaneously transmitting interleaved even and odd data bytes, synchronous with the write enable signal WE* (wave form  910 ), of an odd sector to the first and second flash memory chips via the first and second first split buses  680  and  684  ( FIG. 6 ) respectively. The even data bytes D 0 , D 2 , D 4 , . . . D 510  of the odd sector are received by the first flash chip and stored to the first odd sector field  738  ( FIG. 16 ) of the corresponding location  732  of the first flash memory chip. The odd data bytes D 1 , D 3 , D 5 , . . . D 511  of the odd sector are received by the second flash memory chip and stored to the second odd sector field  746  ( FIG. 16 ) of the corresponding location  733  of the second flash memory chip. At a time t 12 , the first and second flash signals (wave forms  902  and  904 ) complete transmission of the interleaved even and odd data bytes of the odd sector. 
         [0062]    Immediately after time t 12 , during an interval between time t 12  and a time t 13 , the first flash signal (wave form  902 ) transmits no information to the first flash memory chip thereby maintaining the value in corresponding storage location bytes of the first flash memory chip at FFH (hexadecimal) or all 1&#39;s in binary. Meanwhile, between time t 12  and time t 13 , while the second flash signal (wave form  904 ) transmits error correction codes (ECC) to the second flash memory chip via the second split bus  684  ( FIG. 6 ). The filler information FFH transmitted during this time period is received by the first flash memory chip and stored to the second spare field  740  ( FIG. 16 ). The error correction code transmitted during this time period is received by the second flash memory chip and stored to the second error correction field  748  ( FIG. 16 ) of the nonvolatile memory section  733  of the second flash memory chip. This error correction code, generated by ECC logic unit  660  ( FIG. 16 ), relates to the odd sector transmitted during the preceding time interval between time t 11  and t 12 . 
         [0063]    At a time t 17 , the first and second flash signals (wave forms  902  and  904 ) each transmit a read command signal  70 H to the first and second first and second flash memory chips via the first and second split buses  680  and  684  respectively. While the read command signals  70 H are active, the WE signal (wave form  910 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to read the read command signals  70 H. At a time t 18 , the CLE signal (wave form  906 ) is deactivated, transitioning back to the LOW state, thereby disabling the flash memory chips from reading command signals. 
         [0064]    At a time t 18 , the first and second flash signals (wave forms  902  and  904 ) each transmit a status command signal STATUS to the first and second first and second flash memory chips via the first and second split buses  680  and  684  respectively. While the read command signals  70 H are active, the WE signal (wave form  910 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to read the read command signals  70 H. 
         [0065]      FIG. 10  shows a table diagram generally illustrating the memory storage format, as depicted in  FIG. 7 , for storing a block of information in memory bank  506  ( FIG. 6 ) wherein a single sector is written to a particular memory row location of the memory bank. As shown, a memory row location  728  designated ROW 1  has an even sector S 2  and an odd sector S 3  stored therein in accordance with the format described above in reference to  FIG. 7 . A memory row location  728  designated ROW 2  has a single even sector S 4  stored in the first and second even sector fields  734  and  742  of a corresponding pair of row-portions of the first and second flash memory chips  670 ,  672 . Because no odd sector is required to be stored in this case, fields  736 ,  738 ,  746 ,  748 ,  750 , and  752  are shown to be erased. 
         [0066]      FIG. 11  shows a table diagram illustrating the alternative memory storage format, as depicted in  FIG. 7 , for storing a block of information in memory bank  506  ( FIG. 6 ) wherein a single sector is written to a particular memory row location of the memory bank. As mentioned above, field  764  is a three bit field which is used for storing the old row flag in the first bit place, the used/free row flag in the second bit place, and the defect row flag in the third bit place. Also as described above, field  766  is a two bit field which is used for storing the even sector move flag in the first bit place and the odd sector move flag in the second bit place. 
         [0067]    The memory row location designated ROW 1 , having sectors S 2  and S 4  stored therein, has a value “00” stored in field  766  indicating that both sectors have been moved elsewhere in the memory bank. The memory row location designated ROW 2 , having a single even sector S 4  stored in the first and second even sector fields  734  and  742 , has a value “01” stored in field  766  indicating that the information in S 4  has been updated and now resides elsewhere in the memory bank. A value of logic state “0” generally indicates that moved sectors have been updated by the host. Therefore, when the remaining sectors are moved from the old block which was not updated by the host, it can be determined that these sectors are not to be overwritten by the old data during the move 
         [0068]    A memory location  728  designated ROW 1  has an even sector S 2  and an odd sector S 3  stored therein in accordance with the format described above in reference to  FIG. 7 . A memory location  728  designated ROW 2  has a single even sector S 4  stored in the first and second even sector fields  734  and  742  of a corresponding pair of row-portions of the first and second flash memory chips  670 ,  672 . Because no odd sector is required to be stored in this case, fields  736 ,  738 ,  746 ,  748 ,  750 , and  752  are shown to be erased. 
         [0069]      FIG. 12  is a flowchart illustrating a process of simultaneously writing two sectors of information to two memory units during a single write operation in accordance with the present invention.  FIG. 12-1  is a first portion of the flowchart of  FIG. 12 .  FIG. 12-2  is a second portion of the flowchart of  FIG. 12 . In step  1202 , the memory controller  510  ( FIG. 6 ) receives host addressing information from host  504  which specifies addresses for one or more sector locations, in the form of a logical block address (host-provided LBA) or in the form of cylinder head sector (CHS) information. If the host addressing information is in the form of CHS information, the controller translates the CHS information to LBA information. As mentioned, the sectors are organized in blocks and therefore, the host-provided LBA&#39;s may correspond to sectors of more than one block. This information is used by microprocessor  620  ( FIG. 6 ) as will be further discussed below. 
         [0070]    Microprocessor  620  ( FIG. 6 ) executes instructions, which are stored in code storage unit  626  ( FIG. 6 ) to carry out the depicted process. In step  1204 , a sector count value is set equal to the number of sector locations of a current block, being addressed by the host wherein a sector location may, for example, be comprised of fields  734  and  742  ( FIG. 7 ) or fields  738  and  746  ( FIG. 7 ) of the memory bank. The microprocessor determines at  1206  whether or not each of the sector locations specified by the host-provided LBA values has been accessed by the host before. This determination is made by reading the contents of the corresponding virtual PBA field  804  ( FIG. 8A ) of the LBA-PBA map  800  stored in SPM RAM  720  ( FIG. 6 ). As explained above in reference to  FIG. 8A , if the virtual PBA value corresponding to a host-provided LBA is set to the all ‘1’s state, then the corresponding LBA was not accessed by the host before. Memory space in memory bank  506  is erased a block at a time. If any sectors of a block have been accessed since a last erasure of the block, then the block is indicated as having been accessed by virtue of the virtual PBA value in field  804  ( FIG. 8A ) of the corresponding map row location of the LBA-PBA map being a value other than “all 1’s”. 
         [0071]    If it is determined that one or more sector locations, of the current block, specified by the host-provided-LBA&#39;s have been accessed previously by the host, the write process proceeds to step  1210  in which microprocessor  620  ( FIG. 6 ) sets the corresponding one of the move flags  760 ,  762  ( FIG. 7 ) corresponding to the current sector location, and the write process proceeds to step  1208 . As earlier discussed, maintaining the ‘move’ flag in non-volatile memory is optional and may be entirely eliminated without departing from the scope and spirit of the present invention. In the absence of move flags, the microprocessor maintains the status of sectors as to whether or not they have been moved to other blocks. This is done by keeping track of two values for each block. One value is the starting sector location within a block where sectors have been moved and the second value is the number sectors within the block that have been moved. With these two values, status information as to whether or not and which sectors of a block have been moved to other block(s) may be reconstructed. 
         [0072]    If it is determined, at step  1206 , that none of the sector locations of the current block specified by the host-provided-LBA have been previously accessed, the write process proceeds directly to step  1208 . 
         [0073]    In step  1208 , the space manager  636  ( FIG. 6 ) of the controller searches for a free (or unused) block, such as block  727  ( FIG. 7 ) located within the nonvolatile memory bank, each free block being identified by a specific virtual PBA value. The microprocessor determines at  1212  whether a free block is located, and if not, an error is reported by the controller  510  ( FIG. 6 ) to the host indicating that the nonvolatile memory bank is unable to accommodate further storage of information. As this can result in a fatal system error, the inventors of the present invention have exercised great care in preventing this situation from occurring. 
         [0074]    Once a free block within the nonvolatile memory is located at step  1208 , the depicted process proceeds to step  1214 . In step  1214 , microprocessor  620  prompts space manager  636  ( FIG. 6 ) to assign a virtual PBA value  822  ( FIG. 8B ) to the free block found in step  1208 . This virtual PBA value is stored in the LBA-PBA map  800  ( FIG. 8A ) in a map row location  802  ( FIG. 8A ) identified by the masked bits  814  ( FIG. 8B ) of the host-provided LBA corresponding to the current block. The masked bits  814  ( FIG. 8B ) of the current host-provided LBA are obtained by shifting the host-provided LBA to the right by the 5 offset bits (or by dividing by 32). For example, if the host-identified LBA is  16 H (hexadecimal notation), the row in which the virtual PBA is stored is row  0 .Also at step  1214 , the microprocessor appends the ‘offset’ bits  812  ( FIG. 8B ) to the virtual PBA corresponding to the found free block to obtain an actual PBA value  820  ( FIG. 8B ). At  1216 , the microprocessor determines whether the actual PBA value is an even or odd value. At  1216 , alternatively, the host-provided LBA may be checked in place of the actual PBA value to determine whether this value is odd or even. 
         [0075]    If it is determined at  1216  that the actual PBA value is even, the process proceeds to  1218  at which the microprocessor determines whether the sector count is greater than one, i.e., there is more than one sector of information to be written at the point the controller requests that more than one sector to be transferred from the host to the internal buffer of the controller and the process proceeds to  1232  at which the microprocessor determines whether two sectors of information have been transferred from the host to the data buffer  614  ( FIG. 6 ) (through the host interface circuit  610 ). That is, where there is more than one sector of information that needs to be written to nonvolatile memory, as detected by the flash state machine  642 , two sectors of information are transferred at-a-time from the host to the data buffer  614 . The data buffer  614  is used to temporarily store the sectors&#39; information until the same is stored into the memory bank  506 . In the preferred embodiment, each sector includes 512 bytes of user data and 16 bytes of overhead information. 
         [0076]    Where two sectors of information have not yet been transferred to the data buffer  614 , the microprocessor waits until such a transfer is completed, as shown by the ‘NO’ branch loop at  1232 . 
         [0077]    At step  1234 , the microprocessor initiates the writing of the two sectors that have been temporarily saved to the data buffer to the memory bank  506  ( FIG. 6 ) by issuing a write command, followed by address and data information. The write operation at step  1234  is performed according to the method and apparatus discussed above relative to  FIGS. 7 and 9 . 
         [0078]    Upon completion of writing two sectors of information, the write operation is verified at  1235 . If information was not correctly programmed into the sectors at step  1234 , the process continues to step  1237  where a defect management routine is performed, as will be discussed in greater detail below. After execution of the defect management routine, the sector count is decremented by two at step  1236 . At  1235 , if the write operation was verified as being successful, step  1236  is executed and no defect management is necessary. The microprocessor then determines at  1238  whether the sector count is equal to zero and if so, it is assumed that no more sectors remain to be written and the process proceeds to  1228 . If, however, more sectors need to be written the process proceeds to step  1240  at which the host-provided LBA is incremented by two to point to the next sector that is to be written. 
         [0079]    At step  1240 , the microprocessor determines whether the last sector of the block has been reached. The block boundary is determined by comparing the ‘offset’ value of the current LBA to the number of sectors in a block, and if those values are equal, a block boundary is reached. For example, in the preferred embodiment, since a block includes 32 sectors, the ‘offset’ value of the current LBA is compared against ‘32’ (in decimal notation). If alternatively, a block is defined to have other than 32 sectors, such as  16  sectors, the latter is compared against the ‘offset’. If a block boundary in the nonvolatile memory is reached, the write process continues from step  1206  where the virtual PBA value corresponding to the current LBA value is checked for an all ‘1’s condition and so on. If a block boundary is not reached at step  1242 , the write process continues from step  1218 . 
         [0080]    At step  1218 , if it is determined that the sector count is not greater than one, the microprocessor proceeds to determine at  1220  whether data buffer  614  ( FIG. 6 ) has received at least one sector of information from the host. If not, the microprocessor waits until one sector of information is transferred from the host to the data buffer  614 . Upon receipt of one sector of information, writing of the next sector is initiated and performed at step  1222  according to the method and apparatus discussed above relative to  FIGS. 10 and 11 . Upon completion of writing a sector of information, the write operation is verified at  1223 . If information was not correctly programmed into the sector at step  1222 , the process continues to step  1225  where a defect management routine is performed, as will be discussed in greater detail below. After execution of the defect management routine, at step  1224 , the sector count is decremented by one. If at  1223 , it is determined that the write operation was correctly performed, the process continues to step  1224  and no defect management routine is executed. At  1226 , the microprocessor determines whether the sector count is equal to zero and, if not, the host-provided LBA is incremented by one and the write process continues to step  1242  where the microprocessor checks for a block boundary as explained above. 
         [0081]    If at step  1226 , as in step  1238 , it is determined that no more sectors remain to be written, i.e. the sector count is zero, the depicted process proceeds to  1228  at which the microprocessor determines whether the move flag is set. As noted above, the move flag would be set at step  1210  if it was determined at  1206  that an LBA was being re-accessed by the host. 
         [0082]    If it is determined at  1228  that the move flag is not set, the write process ends. However, upon a determined at  1228  that the move flag is set, the block is updated. That is, those sectors of the current block that were not accessed are moved to corresponding sector locations in the block within memory bank  506  identified by the virtual PBA value assigned in step  1214  to the free block found in step  1208 . This is perhaps best understood by an example. 
         [0083]    Let us assume for the purpose of discussion that the sectors identified by LBAs 1, 2, 3, 4, 5 and 6 have already been written and that the host now commands the controller to write data to sectors identified by LBAs 3, 4 and 5. Further, let us assume that during the first write process when LBAs 1-6 were written, they were stored in a block location in the memory bank  506  ( FIG. 6 ) identified by a virtual PBA value of “3” and the LBA locations 3, 4 and 5 are now (during the second write process) being written to a location in the memory bank identified by a virtual PBA value of “8”. During writing of locations identified by host-provided LBA values of 3, 4, and 5, the microprocessor at step  1206  determines that these block locations are being re-accessed and the move flag at  1210  is set. Furthermore, at step  1230 , after the sectors, identified by host-provided LBAs 3, 4, and 5, have been written to corresponding sectors of the block identified by virtual PBA “8”, sectors in the block identified by virtual PBA “3” that were not re-accessed during the write operation are moved from the block identified by virtual PBA “3” to corresponding sector locations of the block identified by virtual PBA “8” and the block identified by virtual PBA “3” is thereafter erased. This example assumes that remaining sectors of the block identified by virtual PBA “3”, such as sectors  0  and  7 - 31  (assuming there are 32 sectors in a block), were not accessed since the last erase of the block in which they reside and therefore contain no valid sector information. Otherwise, if those sectors were previously accessed, then they would also be moved to the virtual PBA location 8. 
         [0084]    Step  1230  may be implemented in many ways. The inventors of the present invention disclose various methods and apparatus which may be alternatively employed for performing the move operation of step  1230 . In patent application Ser. No. 08/946,331 entitled “Moving Sequential Sectors Within a Block of Information In a Flash Memory Mass Storage Architecture”, filed on Oct. 7, 1997, and Ser. No. 08/831,266 entitled “Moving Sectors Within a Block of Information In a Flash Memory Mass Storage Architecture”, filed on Mar. 31, 1997, the disclosures of which are herein incorporated by reference. 
         [0085]      FIG. 12   a  shows the steps performed by the microprocessor if the defect management routine at steps  1237  and  1225  (in  FIG. 12 ) is executed. The block management routine is executed when the write operation is not successfully verified; the block(s) being programmed is in some way defective and a different area in the nonvolatile memory, i.e. another block need be located for programming therein. 
         [0086]    At step  1600 , the block that was being unsuccessfully programmed is marked as “defective” by setting the “defect” flags  756  (in  FIG. 7 ). At step  1602 , the space manager within the controller is commanded to find a free block. At step  1604 , the information that would have been programmed at steps  1234 ’ and  1222  (in  FIG. 12 ) i.e. the block marked “defective” is programmed into corresponding sector locations within the free block found in step  1602 . 
         [0087]    At step  1606 , the block marked “defective” is checked for the presence of any sector information that was previously written thereto successfully. If any such sectors exist, at step  1608 , these previously-programmed sectors are moved to the free block, as is additional block information in the process of  FIG. 12 . 
         [0088]      FIG. 13  shows a table diagram generally illustrating a memory storage format for storing a block, including 32 sectors, of information in memory bank  506  in accordance with an alternative embodiment of the present invention. In this embodiment, an even sector is stored in a first row portion located in a first of the two memory units and an odd sector is stored in a second row portion located in the second of the two memory units. In the depicted embodiment, memory bank  506  includes a plurality of M blocks  1302  designated BLCK 0 , BLCK 1 , BLCK(M-1) each having a physical block addresses (PBA). Each of the blocks  1302  includes a plurality of N memory row locations  1304 , and in a preferred embodiment, N=16. Each block  1302  of memory bank  506  is comprised of a first sub-block  1306  of first flash memory chip  670 , and a corresponding second sub-block  1308  of second flash memory chip  672  wherein the corresponding sub-blocks are identified by the same virtual PBA. Each memory row location  1304  includes a first row-portion  1310  and a corresponding second row-portion  1312 . In the depicted embodiment each of the first and second row-portions  1310 ,  1312  includes storage for 512 bytes of data information plus additional storage space for error correction information (ECC information) and flag information. 
         [0089]    Each of the first row-portions  1310  includes an even sector field  1314  for storing an even sector (S0, S2, S4, . . . ) of information, and an even sector error correction field  1316  for storing error correction information corresponding to the even sector stored in field  1314 . Each of the second row-portions  1312  includes an odd sector field  1318  for storing an odd sector (S1, S3, S5, . . . ) of information, an odd sector error correction field  1320  for storing error correction information corresponding to the odd sector stored in  1318 , a block address field  1322 , and a flag field  1324 . It is understood in the present invention that field  1314  could alternatively be used to store an odd sector while field  1318  could alternatively be used to store an even sector. Also, first row-portion  1310  could alternatively be used for storing the block address and flags. 
         [0090]    Flag field  1324  is used for storing flag information which is used by controller  510  ( FIG. 6 ) during access operations as further explained below. Block address field  1322  is used for storing the block address permanently assigned to block  1302 , such as “0” for BLCK0. Only a single block address entry is required in the block address field per block. In a preferred embodiment, a block address entry is entered in block address field  1322  of the last row  1304 , which is row  15 . 
         [0091]    In this alternative embodiment, the first and second split buses  680 ,  684  ( FIG. 6 ) include lines coupled to receive data bytes of the even and odd sectors respectively. The controller  510  ( FIG. 6 ) writes two sectors simultaneously by simultaneously writing a byte of an even sector and an odd sector simultaneously via the first and second split buses  680 ,  684  ( FIG. 6 ), respectively. The split buses  680 ,  684  ( FIG. 6 ) also provide for: transmission of ECC information between the flash memory chips and the flash state machine  642  and ECC logic unit  660  of the memory controller  510 ; and transmission of address information from flash state machine  642  to the flash memory chips. 
         [0092]      FIG. 14  shows a timing diagram illustrating the timing of control signals, address signals, and data signals for an erase operation of the memory system of  FIG. 6 . The diagram includes: the wave form  902  representing the first flash signal which transmits time multiplexed command, address, and data information from the flash state machine  642  ( FIG. 6 ) via first split bus  680  ( FIG. 6 ) to the first flash memory chip; the wave form  904  representing the second flash signal which transmits time multiplexed command, address, and data signals transmitted from the flash state machine via second split bus  684  ( FIG. 6 ) to the second flash memory chip; a time line  1450 ; and a plurality of control signal wave forms. The control signal wave forms, all of which are described above, include: wave form  906  representing the command line enable (CLE) signal; wave form  908  representing the address line enable (ALE) signal; wave form  910  representing the write enable (WE) signal; wave form  912  representing the read enable (RE) signal; wave form  914  representing the flash chip enable (FCE*) signal; and wave form  916  representing the flash ready/busy signal (FRDY_BSY* signal). 
         [0093]    The erase operation commences at a time E 0  at which the FCE* signal (wave form  914 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to begin receiving command, address, and data signals. At a subsequent time E 1 , the CLE signal (wave form  906 ) is activated, transitioning from a LOW state to a HIGH state, thereby enabling the first and second flash memory chips to read-command signals. At a time E 2 , the first and second flash signals (wave forms  902  and  904 ) each transmit a command signal. The first flash signal (wave form  902 ) transmits an ‘erase set’ command,  60 H, via the first split bus  680  ( FIG. 6 ) to the first flash memory chip while the second flash signal (wave form  904 ) transmits a read status command signal  70 H via the second split bus  684  ( FIG. 6 ) to the second flash memory chip. At a time E 3 , while the command signals  60 H and  70 H are active, the WE signal (wave form  910 ) transitions from a HIGH state to a LOW state thereby enabling the first and second flash memory chips to read the command signals  60 H and  70 H. At a time E 4 , the CLE signal (wave form  906 ) is deactivated, transitioning back to the LOW state, thereby disabling the flash memory chips from reading command signals. 
         [0094]    Also at time E 4 , the ALE signal (wave form  908 ) is activated, transitioning from a LOW state to a HIGH state, thereby enabling the first and second flash memory chips to read packets of address information. At times E 5  and E 6 , the first flash signal (wave form  902 ) transmits first and second address packets ADD 0  and ADD 1  respectively to the first flash memory chip wherein the first and second address packets ADD 0  and ADD 1  specify a sub-block  730  ( FIG. 7 ) of the first flash memory chip  670  of the memory bank. At a time E 7 , the ALE signal (wave form  908 ) is deactivated. During time intervals between times E 3  and E 4 , and E 4  and E 5 , the WE signal (wave form  910 ) transitions to the LOW state to enable the flash memory chip to read the address packets. 
         [0095]    At a time E 8 , the CLE signal (wave form  906 ) is again activated to enable the first and second memory chips to read command signals. At a time E 9 , the first flash signal (wave form  902 ) transmits DOH, which is an ‘erase confirm command’ to the first flash memory chip. This command; as sampled by the CLE signal, actually initiates the erase operation within the flash chips, after which, the contents of data fields  734  and  738  of each memory row portion  732  of the addressed sub-block  730  ( FIG. 7 ) of the first flash memory chip  670  are erased, i.e. set to an “all 1&#39;s” state. At a time E 10 , the FRDY-BSY* signal (wave form  912 ) transitions from a HIGH state to a LOW state to indicate to the flash state machine  642  ( FIG. 6 ) that at least one of the flash memory chips is busy. 
         [0096]    At a time E 11 , the CLE signal (wave form  906 ) is activated to enable the first and second flash memory chips to read command signals. At a time E 12 , the first and second flash signals (wave forms  902  and  904 ) each transmit a command signal. The first flash signal (wave form  902 ) transmits a read command signal  70 H via the first split bus  680  ( FIG. 6 ) to the first flash memory chip while the second flash signal (wave form  904 ) transmits an erase command signal  60 H via the second split bus  684  ( FIG. 6 ) to the second flash memory chip. At a time E 13 , while the command signals  70 H and  60 H are active, the WE signal (wave form  910 ) transitions to the LOW state to enable the first and second flash memory chips to read the command signals  60 H and  70 H. At a time E 14 , the CLE signal (wave form  906 ) is deactivated to disable the flash memory chips from reading command signals and the ALE signal (wave form  908 ) is activated thereby enabling the first and second flash memory chips to read packets of address information. At times E 15  and E 16 , the second flash signal (wave form  904 ) transmits first and second address packets ADD 0  and ADD 1  respectively to the second flash memory chip wherein the first and second address packets ADD 0  and ADD 1  specify a sub-block  731  ( FIG. 7 ) of the second flash memory chip  672  of the memory bank. At a time E 17 , the ALE signal (wave form  908 ) is deactivated. During time intervals between times E 13  and E 14 , and E 14  and E 15 , the WE signal (wave form  910 ) enables the flash memory chips to read the address packets. At a time E 18 , the CLE signal (wave form  906 ) is again activated to enable the first and second memory chips to read command signals. At a time E 19 , the first flash signal (wave form  902 ) transmits DOH to the first flash memory chip to erase the contents of data fields  734  and  738  of each memory row portion  732  of the specified block and thereby set them to an “all 1&#39;s” state. 
         [0097]    To summarize, during a time interval TEB 1 , between the times E 0  and E 11 , the memory controller erases an addressed sub-block  730  ( FIG. 7 ) of the first flash memory chip  670 . Also, during a time interval TEB 2 , between the times E 11  and E 20 , the memory controller erases a corresponding addressed sub-block  731  ( FIG. 7 ) of the second flash memory chip  672 . At a time E 21 , the FRDY BSY* signal (wave form  916 ) transitions from a LOW state to a HIGH state to indicate to the flash state machine  642  ( FIG. 6 ) that both of the flash memory chips are finished with the erase operation. 
         [0098]    Immediately after time E 21 , the first and second flash signals (wave forms  902  and  904 ) each transmit a read status command signal  70 H to the first and second flash memory chips respectively. While the read command signals  70 H are active, the WE signal (wave form  910 ) transitions to the LOW state thereby enabling the first and second flash memory chips to read the read command signals  70 H. At a time E 22 , the first and second flash signals (wave forms  902  and  904 ) both transmit a status data back to the controller. 
         [0099]    So, the status of both flash memory chips are read simultaneously after the erase operation is performed on the two corresponding addressed sub-blocks of the flash memory chips as described above. 
         [0100]    If either of the sub-blocks  730 ,  731  of the memory chips has an error, the entire block  727  ( FIG. 7 ) within the chips is marked defective by setting the contents of the defect flag  756  ( FIG. 7 ) in the second flash memory chip  672 . 
         [0101]      FIG. 15  is a flowchart illustrating a process of erasing a block, including a first sub-block stored in a first memory unit and a second sub-block stored in a second memory unit, in accordance with the present invention. Microprocessor  620  ( FIG. 6 ) executes instructions, which are stored in code RAM  626  ( FIG. 6 ) to carry out the depicted process. 
         [0102]    In step  1502 , microprocessor  620  ( FIG. 6 ) loads a block address to be erased. In step  1504 , the microprocessor initiates the erase operations described above in reference to the timing diagram at  1400  ( FIG. 14 ). At  1506 , the microprocessor determines whether the erase operation is finished by reading the flash ready/busy (FRDY_BSY*) signal (wave form  916  of  FIG. 14 ) which transitions from a LOW state to a HIGH state to indicate to the flash state machine  642  ( FIG. 6 ) that both of the flash memory chips are finished with the erase operation. At  1508 , the microprocessor reads the status of the flash chips  670 ,  672  ( FIG. 6 ). At  1508 , the microprocessor determines whether the erase operation performed in step  1504  was  12   a  operation performed in step  1504  was not successful in both of the flash chips, then the microprocessor marks the block in both of the flash chips  670 ,  672  defective. 
         [0103]    Although the present invention has been described in terms of specific embodiments, it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modification as fall within the true spirit and scope of the invention.