Abstract:
A latching comparator circuit with hysteresis, including bi-state circuit means responsive to an input signal and to a reference signal for, while in a first state, changing to a second state when the input signal has a first predetermined relationship with the reference signal, and for, while in the second state, changing to the first state when the input signal has a second predetermined relationship with the reference signal. Latch means is included for connection with the bi-state circuit means and is responsive to a control signal for preventing the bi-state circuit means from changing from one of the two states to the other of the two states after the bi-state circuit means changes to the other of the two states.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to latching comparator circuits. More specifically, the present invention relates to a novel analog voltage comparator circuit having hysteresis latching capability with respect to a reference voltage. 
     In many applications, it is necessary to provide a circuit which provides an output signal of one of two output levels dependent upon the input signal. In harsh electrical environments such as found in automobile electronics, the input signal may be plagued with switch bounce transients and glitches which could result in erroneous output levels from the comparator circuit. In addition, some amount of hysteresis about a threshold voltage is preferred in the detection of the input signal for changing the state of the output signal. 
     Latching comparators are known within the digital logic field so as to latch an input data signal, which is either high or low, as an output signal. However, these digital circuits respond only to the predetermined high and low levels of the input signal and are not sufficiently flexible to provide hysteresis about a predetermined reference voltage. In summary, the circuits used in digital logic are ineffective for providing switch debounce capability so as to latch an output signal when the input signal makes a first crossing of a threshold in relation to a reference voltage. 
     SUMMARY OF THE INVENTION 
     The present invention discloses a latching comparator circuit with hysteresis that &#34;cleans-up&#34; a signal provided on an input line within the harsh electrical environment such as found in automobile electronics. The present invention looks at the input signal which is provided on the input line through a switch. The action of the switch results in substantial amounts of noise and transients in the input signal during the initial switching action period and the subsequent switch bounce period. The present invention latches upon the initial crossing of a predetermined threshold and ignores the large noise spikes for a predetermined period after the threshold crossing has been reached. 
     The present invention provides switch debounce capability in addition to having threshold hysteresis about a reference voltage. The threshold hysteresis permits different levels of the input signal to change the output signal level. One threshold would be utilized in changing the output state as the input signal fell from a high voltage to a low voltage. A second and different threshold level would be utilized in changing the output state when the input signal rose from a low level to a high level. The threshold levels are symmetrically located about the reference voltage. 
     In accordance with the present invention, a latching comparator circuit with hysteresis is disclosed which provides bi-state circuitry which is responsive to an input signal and a reference signal for, while in a first state, changing to a second state when the input signal has a first predetermined relationship with the reference signal, and for, while in a second state, changing to the first state when the input signal has a second predetermined relationship with the reference signal. Latching circuitry is connected to the bi-state circuitry that is responsive to a control signal for preventing the bi-state circuitry from changing from one of the two states to another of the two states after the bi-state circuitry has changed to the other of the two states. In addition, delay circuitry may be coupled to the bi-state circuitry and the latching circuitry so as to provide the control signal to the latching circuitry. The control signal is provided in response to the first and second states of the bi-state circuitry so as to delay, for a predetermined period of time, the enabling of the latch circuitry which has disabled the bi-state circuitry from changing states after a change in states is made. 
     It is an object of the present invention to provide a latching comparator circuit with hysteresis. 
     It is yet another object of the present invention to provide a latching comparator circuit with hysteresis latching capability about a reference voltage and delay circuitry for prevent changes in the output voltage for a predetermined period of time after an initial change. 
     It is yet another object of the present invention to provide a circuit capable of debouncing noise generated by a switch in an input line so as to permit a noise-free signal indicative of the analog input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates in FIGS. 1(a)-1(c) a schematic representation of the operation of the present invention in one mode of operation. 
     FIG. 2 illustrates in FIGS. 2(a)-2(c) a schematic representation of the operation of the present invention in another mode of operation. 
     FIG. 3 illustrates the latching comparator circuit of the present invention coupled to a time delay circuit which provides control signals to the latching comparator circuit. 
     FIG. 4 illustrates by graphical representation the input signal, the output signal, and the control signals associated with the latching comparator of the present invention. 
     FIG. 5 is a schematical representation of an alternate embodiment of the latching comparator circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, there is shown in FIG. 1(a) a schematic representation of the latching comparator circuit of the present invention. A supply voltage, V cc , is coupled to the input of current source, I 1 , and the inputs of current sources, I 4  and I 5 . The emitter of transistor Q 1  is coupled to the output of current source I 4 , the base of transistor Q 3 , and one end of resistor R 1 . The collector of transistor Q 1  is coupled to ground. The base of transistor Q 1  is adapted to receive an input voltage, V IN . 
     Transistors Q 3  and Q 4  are included as paired transistors to form a differential amplifier. Transistor Q 3  has an emitter coupled to the output of current source I 1  and the emitter of transistor Q 4 . Transistors Q 3  and Q 4   each have a pair of collectors. One collector of transistor Q 3  is coupled to the base and collector of transistor Q 9 , which has its emitter coupled to ground. Transistor Q 4  has one collector coupled to the collector of transistor Q 10 , which has an emitter coupled to ground and a base coupled to the base of transistor Q 9 . The collector of transistor Q 10  is adapted to provide an output voltage, V OUT , from the latching comparator circuit. Transistors Q 9  and Q 10  are configured as a differential to singled-ended turnaround circuit to provide an output from the differential amplifier transistor pair of transistors Q 3  and Q 4 . 
     The base of transistor Q 4  is coupled to the output of current source I 5  and the emitter of transistor Q 2  and one end of resistor R 2 . The collector of transistor Q 2  is coupled to ground. The base of transistor Q 2  is adapted to receive a reference voltage, V REF . 
     The other end of resistor R 1  is coupled to the collector of transistor Q 5 , which has an emitter coupled to ground. The base of transistor Q 5  is coupled to the other collector of transistor Q 3  in addition to being coupled to the collector of transistor Q 7  and the input of current sink I 2 . The output of current sink I 2  is coupled to ground. The emitter of transistor Q 7  is coupled to ground while the base is adapted to receive a control signal, UNLATCH A. 
     The other end of resistor R 2  is coupled to the collector of transistor Q 6 , which has an emitter coupled to ground. The base of transistor Q 6  is coupled to the other collector of transistor Q 4  in addition to being coupled to the collector of transistor Q 8  and the input of current sink I 3 . The output of current sink I 3  is coupled to ground. The emitter of transistor Q 8  is coupled to ground while the base is adapted to receive a control signal, UNLATCH B. 
     In the preferred embodiment of the invention, current sinks I 2  and I 3  are each capable of sinking up to 1/3 the amount of current provided by current source I 1 . The hysteresis in the comparator switching point occurs when one transistor in the differential amplifier transistor pair (Q 3  and Q 4 ) passes an amount of current greater than 1/3 the amount of current provided by current source I 1  into either current sinks I 2  or I 3 . At the switching points the amount of current required to overcome one of the current sinks I 2  or I 3 , corresponds to a 2:1 current ratio for the current flowing through transistors Q 3  and Q 4 . Also at the switching points, the difference between transistors Q 3  and Q 4  base-to-emitter voltages, ΔV be , is approximately 18 mV. The difference in the V be  &#39;s in transistors Q 3  and Q 4  can be mathematically expressed as ##EQU1## where: K=Boltzman&#39;s constant 
     T=absolute temperature (°K) 
     q=charge of electron 
     I c3  =transistor Q 3  collector current 
     I c4  =transistor Q 4  collector current. 
     At room temperature, KT/q is approximately 0.026 and the ln 2 equals 0.693. 
     Summarizing, the two switch points will occur approximately ±18 mV around the reference voltage. The hysteresis about the reference voltage at which the switching points occur may be modified by merely designing current sinks I 2  and I 3 , which are of equal current sinking capabilities, to both sink equally greater or lesser amounts of current provided by current source I 1 . 
     Referring to FIG. 1(a) and FIG. 4, during the time period t 0  -t 1 , the UNLATCH B signal is &#34;high&#34;, therefore supplying a current to the base of transistor Q 8 , which is effectively turned &#34;on&#34;. With transistor Q 8  turned &#34;on&#34;, it is in saturation and effectively holds transistor Q 6  turned &#34;off&#34; by diverting all of the current I 1  through the collector and emitter of transistor Q 8  to ground. During the time period t 0  -t 1 , the input voltage V IN  is much greater than the reference voltage V REF  which results in the circuit output voltage V OUT  being held &#34;high&#34;. Since transistor Q 6  is turned &#34;off&#34; and the voltage V REF  is applied to the base of transistor Q 2 , current source I 5  provides a current through the emitter and collector of transistor Q 2  to ground. 
     At time t 1 , V IN  begins to fall and crosses through the upper threshold, V REF  +ΔV T , and V REF  until the time t 2  when it reaches the lower threshold level V REF  -ΔV T  which is 18 mV below V REF . As V IN  falls, transistor Q 1  is biased &#34;on&#34; and begins to conduct to ground the current I 4  supplied by a current source I 4 . Correspondingly, as current is conducted through transistor Q 1  to ground, the base voltage of transistor Q 3  falls such that transistor Q 3  begins to conduct a portion of the current I 1  in an amount equal to the reduction of current conducted by transistor Q 3 . For example, when V IN  equals V REF , the current flowing into the emitter of Q 3  equals the current flowing into the emitter of Q 4 . Therefore, 1/2 I 1  is flowing into the emitter of transistor Q 3  with 1/2 I 1  flowing into the emitter transistor Q 4 . 1/4 of the current I 1  is conducted through one collector of transistor Q 3  through current sink I 2  to ground. The other 1/4 of the current I 1  conducted through transistor Q 3  is supplied down to the base and collector of transistor Q 9  but is insufficient to turn on transistor Q 9  so as to result in a change in the &#34;high&#34; output voltage at the collector of transistor Q 10  which is presently biased &#34;off&#34;. 
     At time t 2 , V IN  has fallen to the lower threshold voltage such that transistor Q 3  conducts 2/3 of the current I 1  while the transistor Q 4  conducts 1/3 of the current I 1  as illustrated in FIG. 1(b). At this time, 1/3 of the current I 1  is provided to ground through current sink I 2  while another 1/3 of the current I 1  is provided to the base and collector of transistor Q 9 . The 1/3 of the current I 1  being conducted through transistor Q 4  is conducted through transistor Q 8  to ground. 
     As V IN  falls slightly below the lower threshold, transistor Q 3  begins to conduct a proportion of the current greater than 2/3 of the current I 1 . Since current sink I 2  is only capable of sinking to ground 1/3 of the current I 1 , any additional current provided to current sink I 2  is forced into the base of transistor Q 5  so as to turn &#34;on&#34; transistor Q 5 . As a result of the base current being supplied to transistor Q 5 , transistor Q 5  goes into saturation and pulls the emitter of transistor Q 1  low. This positive feedback forces transistor Q 3  to conduct all of the current I 1  provided by current source I 1 . With transistor Q 5  saturated, current I 4  provided by current source I 4  is conducted through the collector to emitter of transistor Q 5  along with the base current of approximately 1/6 I 1  to ground. In this condition, as illustrated in FIG. 1(c), the comparator circuit is now latched in the &#34;on&#34; state and cannot be unlatched by any change in the input voltage V IN . It should be noted that as transistor Q 5  begins to conduct, transistor Q 9  is provided with a base and collector current equivalent to 1/2 I 1 , which sends transistor Q 9   into saturation, and provides transistor Q 10  is also provided with a base current sufficient to send transistor Q 10  into saturation, which results in V OUT  going &#34;low&#34;. 
     During the time period t 2  -t 3 , there is an extreme amount of noise or transients on the input line which is reflected in V IN . The noise on the input line may exceed the upper and lower threshold levels of a comparator circuit. However, the input line noise is ignored such that V OUT  remains at a constant &#34;low&#34; state irrespective of the input noise. At time t 3 , the noise has subsided from V IN  and V IN  settles to a &#34;low&#34; state. At time t 4 , the unlatch control signals change such that the UNLATCH B signal goes &#34;low&#34;, and the UNLATCH A signal goes &#34;high&#34;. This results in a current turning &#34;on&#34; transistor Q 7  while at the same time removing the current from the base of transistor Q 8  thereby turning transistor Q 8  &#34;off&#34;. In this condition, the circuit is now prepared to latch in the other direction. Transistor Q 7  goes into saturation and conducts 1/2 I 1  through the collector and emitter to ground, thereby turning &#34;off&#34; transistor Q 5 . With transistor Q 5  turned &#34;off&#34;, the current I 4  supplied by current source I 4  is conducted through transistor Q 1  to ground. This condition is illustrated in FIG. 2(a). 
     During the time period t 4  -t 5 , V IN  is held &#34;low&#34; which corresponds to a latched output voltage V OUT  also being &#34;low&#34;. Also during the time period t 4  -t 5 , the circuit is prepared to latch when V IN  rises above the upper threshold V REF  +ΔV T . 
     At time t 5 , V IN  begins to rise which results in a reduction of the current I 1  conducted through transistor Q 3  and an equal increase of current conducted through transistor Q 4 . When V IN  equals V REF , equal amounts of current are conducted through transistors Q 3  and Q 4 . When V IN  equals V REF , 1/2 of the I 1  is provided through transistor Q 3  with 1/4 of the current I 1  being provided to ground through transistor Q 7  and the other 1/4 of the current I 1  being supplied to the turnaround circuit of transistors Q 9  and Q 10 . In addition 1/2 of the current I 1  is conducted through transistor Q 4  with 1/4 of the current I 1  being conducted through transistor Q 10  to ground and the other 1/4 of the current being supplied to ground by current sink I 3 . 
     At time t 6 , V IN  has reached the upper threshold such that transistor Q 4  is conducting 2/3 of the current I 1  while transistor Q 3  is conducting 1/3 of the current I 1 . This condition is illustrated in FIG. 2(b). With transistor Q 3  conducting 1/3 of the current I 1 , 1/6 of the current I 1  is conducted through transistor Q 9  which supplies a portion of the base current to transistor Q 7  and the other 1/6 of the current I 1  is supplied to ground through transistor Q 7 . 2/3 of the current I 1  is conducted through transistor Q 4  with 1/3 being conducted to ground through transistor Q 10 . The other 1/3 of the current I 1  is conducted through current sink I 3  to ground. 
     As V IN  goes slightly above the upper threshold voltage, additional current is supplied through transistor Q 4  with a corresponding reduction of current flowing through transistor Q 3 . A portion of the additional current being conducted by transistor Q 4  is provided through a collector which is coupled to current sink I 3 . This additional portion of current overcomes the current sinking capability of current sink I 3  so as to provide the additional portion of current to the base of transistor Q 6 . The current supplied to the base of transistor Q 6  causes transistor Q 6  to turn &#34;on&#34; or saturate. As transistor Q 6  goes into saturation, the current I 5  supplied by current source I 5  flows through transistor Q 6  along with the base current of transistor Q 6  (2/3 of the current I 1 ) to ground. At the point where the current is removed from transistor Q 3 , transistor Q 9  turns &#34;off&#34; which results in the turning &#34;off&#34; of transistor Q 10 , which causes additional current to flow through transistor Q 6  and V OUT  going &#34;high&#34;. 
     With transistor Q 6  conducting 2/3 of the current I 1  and current sink I 3  conducting 1/3 of the current I 1  to ground, the comparator circuit is now latched in an opposite state. During the time period t 6  -t 7 , V IN  is subject to noise and transients due to the switch bounce on the input line. At time t 7 , the noise has subsided and V IN  has reached the high level. During the time period t 6  -t 8 , the output of the comparator circuit V OUT  is latched at a &#34;high&#34; output voltage. Any changes in V IN  will not be reflected in V OUT . 
     At time t 8 , the noise has subsided with V IN  being &#34;high&#34; such that the comparator circuit may be prepared for latching as V IN  goes below the lower threshold voltage. At time t 8 , the UNLATCH A signal goes &#34;low&#34; and the UNLATCH B signal goes &#34;high&#34;, thereby placing the circuit in the condition as discussed with reference to FIG. 1(b). 
     FIG. 3 illustrates latching comparator 100 of the present invention having the output voltage V OUT  coupled to time delay 110. Time delay 110 provides the control signal Q or UNLATCH A to latching comparator 100. Time delay 110 also provides a Q or UNLATCH B signal to latching comparator 100. Time delay 110 provides the UNLATCH A and UNLATCH B signals in response to the status of latching comparator as indicated by V OUT . Upon receiving a change in V OUT  from the latching comparator 100, time delay 110 delays for a predetermined period of time, τ, a change in the status of the UNLATCH A and UNLATCH B signals. With reference to FIG. 4 for the time period t 0  -t 2 , V OUT  is &#34;high&#34; with UNLATCH A being &#34;low&#34; and UNLATCH B being &#34;high&#34;. At time t 2 , V OUT  goes &#34;low&#34; and in response time delay 110 inhibits the changing of the status of UNLATCH A and UNLATCH B signals for the time period τ, which in this case is the time period t 2  -t 4 . At time t 4 , time delay 110 permits the status of the UNLATCH A and UNLATCH B signals to change with the UNLATCH A signal going &#34;high&#34; and the UNLATCH B signal going &#34;low&#34;. 
     Correspondingly, at time t 6 , V OUT  goes &#34;low&#34; to &#34;high&#34; while the UNLATCH A signal and the UNLATCH B signal are respectively &#34;high&#34; and &#34;low&#34;. During the predetermined period of time, in this case the time period t 6  -t 8 , the UNLATCH A and UNLATCH B signals remain unchanged. At time t 8 , time delay 110 permits the UNLATCH A signal to go &#34;low&#34; and the UNLATCH B signal to go &#34;high&#34;. It should be noted that the time period t 2  -t 4  and the time period t 6  -t 8  are equal in time duration. The time period τ can be adjusted according to the duration of the input noise at V IN . Time delay 110 permits the latching comparator to be disabled after latching for a predetermined period of time τ so as to inhibit a change in the output voltage V OUT  during the period that the noise is affecting V IN . 
     FIG. 5 illustrates an alternate embodiment of the present invention. In FIG. 5, transistor Q 3  and Q 4  have respectively been replaced with transistors Q&#39; 3  and Q&#39; 4  with each having only a single collector. The output circuit now includes transistors Q 9 , Q 10 , Q 11 , and Q 12 . Transistor Q 11  has a base coupled to the base of transistor Q&#39; 3  while transistor Q 14  correspondingly has a base connected to the base of transistor Q&#39; 4 . The collectors of transistors Q 11  and Q 12  are connected to the emitters of transistors Q&#39; 3  and Q&#39; 4 . The emitter of transistor Q 11  is coupled to the collector and base of transistor Q 9  with the emitter of transistor Q 9  being coupled to ground. The emitter of transistor Q 12  is coupled to the collector of transistor Q 10  with the collector of transistor Q 10  being adapted to provide the output voltage supply V OUT . The base of transistor Q 10  is coupled to the base and collector of transistor Q 9 . The emitter of transistor Q 10  is coupled to ground. 
     A single control signal CS may be supplied at the control signal input which provides a noninverted signal to transistor Q 8  and an inverted signal to transistor Q 7 . The control signal is inverted by inverter I 1  as applied to the base of transistor Q 7 . A single control signal provides the identical function as the UNLATCH A and UNLATCH B signals thereby eliminating the need for two control signals from the time delay unit. 
     In a preferred embodiment of the invention, input transistors Q 1  and Q 2  along with the differential amplifier transistor pair Q&#39; 3  and Q&#39; 4  are transistors of the PNP type. Transistors Q 5 , Q 6 , Q 7 , Q 8 , Q 9 , Q 10 , Q 11 , and Q 12  are transistors of the NPN type. Current source I 1 , current sources I 4  and I 5 , and current sinks I 2  and I 3  are all transistorized current sources that are well known in the art of semiconductor circuits. Time delay 110 may be implemented as a JK flipflop having a predetermined period of time delay before changing the output level. Inverter I 1  may be implemented as a standard digital logic inverter, such as TTL compatible logic. Although resistors R 1  and R 2  are included in the preferred embodiment, it is recognized that the circuit will perform adequately without these resistors. Transistors Q 1  and Q 2  are included and provide input source buffering. Transistors Q 1  and Q 2  respectively isolate the input signal and reference signal sources from the circuit so as not to pull them to ground during the operation of the circuit. 
     In the operation of the latching comparator circuit of the present invention, a typical current supplied by current source I 1  is equal to 15 uA with current sources I 4  and I 5  each capable of providing up to 10 uA of current. Current sinks I 2  and I 3  are each capable of sinking up to 5 uA of current. Resistors R 1  and R 2  each are 20 K ohm resistors. In relation to voltages, V cc  equals 5 volts while V REF  equals 1 volt along with V IN  ranging from 0 to 5 volts. With V cc  equaling 5 volts, it is possible to vary the reference voltage from about 0 volts to about 3 volts. With respect to the threshold levels, it is possible to increase or decrease these levels symmetrically about the reference voltage by designing the current sinking capabilities of current sinks I 2  and I 3  with respect to the difference in V be&#39;s  of transition Q 3  and Q 4 . As described herein V REF  equals 1 volt, with the upper and lower threshold voltages symmetrically located 18 mV (difference in transistor Q 3  and Q 4  V be&#39;s ) above and below V REF  which corresponds to a 2:1 current ratio in transistors Q 3  and Q 4 . However, it is readily envisioned that the upper and lower threshold levels may be varied by changing variable current sinks I 2  and I 3  to equally sink greater or lesser amounts of current. It is envisioned that the current ratios in transistors Q 3  and Q 4  may be increased to approximately a 20:1 current ratio. 
     The previous description of the preferred embodiments are provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.