Abstract:
A transistor biasing circuit having a single biasing transistor for biasing first and second operational transistors. The biasing transistor has means connecting its base to its collector and means are provided to connect the base of each of the first and second operational transistors to the collector circuit of the biasing transistor. Each of the three transistors are arranged in a circuit between a pair of voltage terminals which are connected to a power supply. The arrangement of the resistors in the circuit paths of the biasing transistor and the operational transistors are in such a way as to provide circuit means for stabilizing the collector currents of the first and second transistors regardless of variations in the factor of h FE . This circuit arrangement provides an improved stabilization of the collector currents over prior art devices.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The field of art to which this invention pertains is transistor biasing circuits for a pair of operational transistors wherein means are provided to minimize variation in the collector currents of the operational transistors even though there may be variations in the factor h FE . 
     2. Description of the Prior Art 
     Prior art circuits have been developed to attempt a minimization of variation in collector currents in a transistor biasing circuit regardless of variations in the factor h FE . However such circuits have not resulted in the kind of improvement desired in modern circuit arrangements. Accordingly the present invention deals with an improvement over such prior art circuits to further minimize the variation in collector currents of such circuits regardless of the variations in the factor h FE . 
     Reference is had to related application Ser. No. 635,283 assigned to same assignee and filed on even date herewith. 
     SUMMARY OF THE INVENTION 
     It is an important feature of the present invention to provide an improved transistor biasing circuit for a pair of operational transistors. 
     It is another feature of the present invention to provide a transistor biasing circuit for a pair of operational transistors to minimize variations in collector currents thereof in response to variations in the factor h FE . 
     It is another feature of the present invention to provide a transistor biasing circuit having a pair of transistors biased by a single biasing transistor wherein the biasing transistor has its collector connected in the circuit paths of the base circuits of each of the operational transistors and wherein the various resistance values associated with the biasing arrangements of each transistor are designed to minimize variations in collector currents in response to variations in the factor h FE . 
     It is another object of the present invention to provide a transistor biasing circuit as described above wherein the transistor which precedes the biasing transistor has a gain of less than one and the transistor which follows the biasing transistor has a gain of greater than one. 
     It is another object of the present invention to provide a circuit arrangement as described above wherein the transistor which precedes the biasing transistor has a gain greater than one and the transistor which follows the biasing transistor has a gain greater than one. 
     These and other objects, features and advantages of the present invention will be understood from the drawings and the following description wherein reference numerals are utilized to designate a preferred embodiment. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 and 2 are schematics showing prior art arrangements which relate to the present invention. 
     FIG. 3 is a schematic of a transistor biasing circuit according to the present invention. 
     FIG. 4 is another form of the biasing circuit according to the present invention, and FIG. 5 is an illustrative diagram of a general circuit of the present invention having the various elements thereof identified in a manner which permits a ready application of the claims appended hereto. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention relates to a transistor biasing circuit by which the bases of two transistors can be supplied with a stabilized biasing voltage under the condition of equal collector currents and different emitter resistances. 
     In the prior art circuit as shown in FIG. 1, when the base-emitter voltage V BE  and current amplification factor h FE  of a biasing transistor Q 2  are equal to those of an amplifying transistor Q 1  which has a base supplied with the biasing voltage; the values of the DC collector currents of both transistors and the ratio thereof can be designed at a predetermined value, even if the factor h FE  is varied. 
     Such a biasing circuit is described below with reference to FIG. 1. An amplifying transistor Q 1  has an emitter which is grounded through a resistor 1, a collector connected through a load resistor 3 to a power or voltage source B + , and a base connected through a capacitor 17 to a signal input terminal t 1 . An output terminal t 2  is available at a capacitor 12 which is connected to the collector of the transistor Q 1 . 
     A biasing circuit BK, consisting of a transistor Q 2  and resistors 4, 5 and 6, supplies a bias voltage to the base of the transistor Q 1 . Q 2  has its emitter grounded through a resistor 4, and its collector connected through a resistor 6 to the voltage source B + . A resistor 5 forms a base biasing circuit between collector and base, and the collector is connected through a resistor 2 to the base of the transistor Q 1 . The resistance values of the resistors 1 to 6 are referred to herein as R 1  to R 6  ; the voltages between the bases and emitters of the transistors Q 1  and Q 2 , as V BE1  and V BE2  ; the DC base currents of the transistors Q 1  and Q 2 , as I B1  and I B2  ; their DC collector currents as I C1  and I C2  ; and their DC emitter currents as I E1  and I E2 , respectively. 
     The DC equation for voltage at the collector of the transistor Q 2  is as follows: 
     
         I.sub.E1 R.sub.1 + V.sub.BE1 + I.sub.B1 R.sub.2 = I.sub.E2 R.sub.4 + V.sub.BE2 + I.sub.B2 R.sub.5                              (1) 
    
     in the equation (1), if it is assumed that V BE1  ≈ V BE2  and the factor h FE  of each of the transistors Q 1  and Q 2  is equal, the result is the following equation (2): ##EQU1## 
     If the following equation (3) is satisfied 
     
         I.sub.C1 = k I.sub.C2                                      (3) 
    
     where k is a constant and the equation (2) is rearranged, the following equation (4) is derived. ##EQU2## 
     The condition for satisfying the equation (4) regardless of variations in h FE  is as follows: 
     
         k R.sub.1 = R.sub.4                                        (5) 
    
     
         k R.sub.2 = R.sub.5                                        (6) 
    
     when the resistances R 1 , R 2 , R 4  and R 5  are selected to satisfy the equations (5) and (6), the following equation is derived by substituting the equations (5) and (6) into the equation (2): ##EQU3## therefore 
     
         I.sub.C1 = k I.sub.C2                                      (3) 
    
     this means that the equation (3) is obtained. Therefore it can be said that the equation (3) is satisfied when the resistances R 1 , R 2 , R 4  and R 5  are selected to satisfy equations (5) and (6). 
     It is well known that the DC current I C1  is temperature stabilized when the equation (3) is satisfied, and this means that the current I C1  does not change with temperature for the reason that: ##EQU4## Therefore when equation (3) is satisfied I C1  and hence I C2  is constant regardless of changes in h FE . 
     An example where the bases of the two transistors Q 1  and Q 3  are biased by a biasing transistor Q 2  such as shown in FIG. 1 will be described with reference to FIG. 2 in which corresponding elements are marked with the same reference numerals as used in FIG. 1. 
     In FIG. 2, reference letter Q 3  shows an amplifying transistor which forms another transistor amplifier, and in this case the transistor Q 3  is connected at the rear state of the transistor Q 1 . The emitter of the transistor Q 3  is grounded through a resistor 7. Its collector is connected through a load resistor 9 to the voltage source B + , and an output terminal t 3  is coupled to the collector. The base of transistor Q 3  is connected through a capacitor 18 to the collector of the transistor Q 1 . The collector of the transistor Q 2 , of the biasing circuit BK, is connected through a resistor 8 to the base of the transistor Q 3 . A capacitor 19, connected between the collector of the transistor Q 2  and ground prevents an input signal at the base of the transistor Q 3  from being fed back to the base of the transistor Q 1  through the resistors 8 and 2. 
     The resistance values of the resistors 7 to 9 are referred to herein as R 7  to R 9  ; the base-emitter voltage of the transistor Q 3  as V BE3  ; its DC base current as I B3  ; its DC collector current as I C3  ; and its DC emitter current as I E3 . When the transistors Q 1  and Q 3  are formed, for example in a single semiconductor as an integrated circuit, the transistors Q 1  and Q 3  have substantially the same characteristics as each other. Therefore it is desirable for the collector DC currents, I C1  and I C3 , to be stabilized at substantially the same value because the most appropriate DC operational currents of both transistors are substantially the same. 
     In the embodiment of FIG. 2 equations similar to (1) to (4) in the case in FIG. 1 are established, and when the resistances R 4 , R 5 , R 7  and R 8  are selected to satisfy the following equations (7) and (8) under the assumption of V BE2  ≈ V BE3 , the resulting equation (9) is satisfied: 
     
         k R.sub.7 = R.sub.4                                        (7) 
    
     
         k R.sub.8 = R.sub.5                                        (8) 
    
     
         i.sub.c3 = k I.sub.C2                                      (9) 
    
     accordingly, by satisfying equations (5), (6), (7) and (8), both equations (3) and (9) can be satisfied together, and both transistors Q 1  and Q 3  are stabilized with reference to ambient temperature under the condition of equal collector currents. 
     If transistor Q 1  is used as an attenuator having a gain of less than 1, then to make the dynamic range of the transistor Q 1  sufficiently wide, the resistance R 1  is selected large. It may appear unusual to use a transistor amplifier having a gain less than 1 in combination with another transistor amplifier having a high gain much greater than 1. However such a circuit construction is often used to control the total gain of the two cascaded transistor amplifiers. Usually the preceding amplifier which operates as an attenuator is a gain controlled amplifier, but the related circuit of FIG. 3 does not show any gain control means for the sake of brevity. 
     FIG. 4 shows another case in which each of the transistors Q 1  and Q 3  has a gain greater than 1, and the succeeding transistor Q 3  has a wider dynamic range than the preceding transistor Q 1 . 
     Where Q 1  is used as an attenuator, if the gain of the transistor Q 1  is kept constant it is necessary to make the resistance R 3  great in proportion to the resistance R 1 . It is also necessary to make the collector current I C1  constant, and the resistances R 2 , R 4  and R 5  are required to be great in proportion to resistance R 1 . 
     If it is possible to increase the resistances R 7 , R 8  and R 9  together in proportion to the resistance R 1 , there may not be a problem. There may be, however, a situation where the resistance R 9  cannot be made sufficiently large. The reason is as follows. Since the resistance R 9  includes the input impedance of the following stage, namely the amplifier circuit associated with the transistor Q 3 , which requires a low input impedance, R 9  cannot be made suitably large. 
     Accordingly, when the resistances R 7  and R 8  are selected great in proportion to R 1  and R 2  so as to make the collector DC current I C3  constant, the AC current gain determined by the ratio (R 9  /R 7 ) becomes small. 
     Also, if the resistance R 7  becomes too great, an intense thermal noise may occur. Therefore, it is not desirable to make the resistance R 7  great. In this case, in order to make the dynamic range of the first stage amplifier circuit wide enough, the resistance R 1  must be selected great regardless of the thermal noise. 
     There is another case where the resistance R 1  must be small, while the resistance R 7  is required to be large in order to make the gain of the transistor Q 1  sufficiently high and to make the dynamic range of the transistor Q 3  sufficiently wide. When the resistances R 4  and R 5  of the biasing circuit BK and the resistances R 1  and R 2  are selected to make the transistor Q 1  stabilized at the most appropriate collector current, the transistor Q 3  cannot be stabilized at the same collector current. On the other hand when the resistances R 4  and R 5  of the biasing circuit BK and the resistances R 7  and R 8  are selected to make the transistor Q 3  stabilized at the most appropriate collector current, the transistor Q 1  cannot be stabilized at the same collector current. 
     In view of the above defects of the prior art, the present invention provides a single biasing circuit for biasing both bases of two transistors regardless of the difference of the resistance values mentioned above. 
     Furthermore, the present invention provides a biasing circuit by which the DC collector currents of respective transistors can be held at a desired constant value regardless of variations in the factor h FE  by independently selecting the emitter resistances of the respective transistors. 
     In the embodiment of the present invention shown in FIG. 3, elements corresponding to those in FIGS. 1 and 2 are marked with the same reference numerals and letters and their description is omitted for simplicity. 
     In FIG. 3, a resistor 10 having a resistance value R 10  is connected between the junction of resistors 2 and 6 and the collector of the transistor Q 2 , other circuit elements are substantially the same as those in FIG. 2. 
     If in the embodiment of FIG. 3 the resistances R 4 , R 5 , R 7  and R 8  are selected to satisfy the above equations (7) and (8), the equation (9) can be satisfied. In this case, it is assumed that the factor h FE  of the transistors Q 1 , Q 2  and Q 3  are equal with one another (which means that when they are varied, they vary equally) and the equation V BE1  ≈ V BE2  ≈ V BE3  is satisfied. 
     If the current flowing through the resistor 10 is taken as I 10 , it can be expressed by the following equation: ##EQU5## 
     The DC voltage at the connection point between the resistors 2 and 6 is expressed by the following equation: 
     
         I.sub.E1 R.sub.1 + V.sub.BE1 + I.sub.B1 R.sub.2 = I.sub.E2 R.sub.4 + V.sub.BE2 + I.sub.B2 R.sub.5 + I.sub.10 R.sub.10          (11) 
    
     since V BE1  ≈ V BE2 , the equation (11) can be rewritten as follows: ##EQU6## 
     If the equation (10) is substituted into the right side of equation (12), the right side is expressed as follows: ##EQU7## 
     In contrast if in the circuit of the present invention as shown in FIG. 3, R 1  = 50 ohms, R 2  = 5k ohms, R 3  = 0 ohm, R 4  = 90 ohms, R 5  = 15k ohms, R 6  = 9.1k ohms, R 7  = 30 ohms, R 8  = 5k ohms, R 9  = 0 ohm, R 10  = 60 ohms and the capacitors 12 and 13 are removed, the variation factor of the current I C1  upon the factor h FE  being varied from 200 to 100 is 0.00415 and that of the current I C3  is 0.01687. 
     Since the third term in the expression (13) is sufficiently small as compared with the first term, the third term can be neglected, and the expression (13) or the right side of the equation (12) can be written as follows: ##EQU8## 
     Therefore, if the right side of the equation (12) is replaced by the expression (14) and the equation I C1  = k I C2  is substituted thereinto, the equation (12) can be rewritten as follows: ##EQU9## 
     The condition for satisfying equation (15) regardless of variations in the factor h FE  is as follows: 
     
         k R.sub.1 = R.sub.4 + R.sub.10                              (16) 
    
     
         k R.sub.2 = R.sub.5                                         (17) 
    
     therefore if the resistance R 1 , R 2 , R 4 , R 5 , R 7 , R 8  and R 10  are selected to satisfy equations (7), (8), (16) and (17), I C1  = I C3  = k I C2  is satisfied and both the transistors Q 1  and Q 3  are stabilized under the condition of R 1  &gt; R 7  with the most appropriate collector current. 
     If in the circuit of FIG. 2, R 1  = 50 ohms, R 2  = 5k ohms, R 3  = 0 ohm, R 4  = 150 ohms, R 5  = 15k ohms, R 6  =9.1k ohms, R 7  = 30 ohms, R 8  = 9.1k ohms, R 9  = 0 ohm and the capacitors 12 and 13 are removed, the variation factor of the current I C1  upon the factor h FE  being varied from 200 to 100, is 0.00114 and that of the current I C3  is 0.14223, respectively. 
     When the emitter resistor 1 of the preceding transistor Q 1  is desired to be small and the emitter resistor 7 of the following transistor Q 3  is desired to be great in order to make the gain of the preceding transistor Q 1  sufficiently high and to make the dynamic range of the transistor Q 3  sufficiently wide, the circuit shown in FIG. 4 is used instead of the circuit of FIG. 3. The only physical difference in the circuit of FIG. 4 as compared to FIG. 3 is that the base biasing connections for the transistors Q 1  and Q 3  are interchanged. 
     Therefore it can be understood that the transistors Q 1  and Q 3  of FIG. 4 operate in the same manner as the transistors Q 3  and Q 1  of FIG. 3, respectively and that the transistors Q 1  and Q 3  of FIG. 4 are stabilized under the condition of I C1  = I C3  = k I C2  and R 1  &lt; R 7 . Accordingly, further detailed explanation is omitted. 
     It is understood from the explanation of FIGS. 3 and 4 that both the transistors Q 1  and Q 3  are commonly biased by a single biasing circuit BK and are stabilized under the condition of I C1  = I C3  = k I C2  and R 1  ≠ R 7 . 
     The FIG. 3 arrangement shows a case which is less often used than the arrangement shown in FIG. 4. In FIG. 3 the gain of Q 1  is less than 1 and the gain of Q 3  is greater than 1. In that case R 1  is greater than R 7 . In contrast, in the circuit of FIG. 4 of the gain of Q 1  is greater than 1 as well as the gain of Q 3  being greater than 1. In the arrangement of FIG. 4, then, R 7  is greater than R 1 . This is the more common arrangement, that is, where the transistors Q 1  and Q 3  are both amplifying transistors. As indicated above, the only difference between FIG. 4 and FIG. 3 is that in FIG. 3 the base circuit of Q 3  is connected directly to the collector Q 2  and the collector circuit of the transistor Q 1  is connected to the collector circuit Q 2  through the resistor R 10 . In contrast, in FIG. 4 the collector circuit Q 3  is connected to the collector of Q 2  through R 10 , while the collector circuit of Q 1  is connected directly to the collector of transistor Q 2 . 
     It will be apparent that various modifications of the present invention can be accomplished by a person skilled in the art without departing from the spirit and scope of the present invention as set forth in the appended claims.