Abstract:
The present invention provides a method for single-end compensation of an operational amplifier, which comprises: designing an operational amplifier having a single-end offset style, preparing a common-mode circuit, a switch circuit, a comparator, a digital circuit and a compensation circuits. When a single-end offset voltage of the operational amplifier is converted, output of the comparator will change state and will be detected by the digital circuit, so that the digital circuit will fix a group of digital signals, and instruct the switch circuit to block an average signal of the common mode circuit, allowing a set of double-end input signals to be inputted to the operational amplifier directly.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to an improvement of operational amplifier, and more particularly to a method for single-end offset compensation of an operational amplifier.  
       BACKGROUND OF THE INVENTION  
       [0002]     Referring to  FIG. 1 , which shows the offset phenomenon of an operational amplifier. A signal V o  symmetrical to zero voltage is inputted to the operational amplifier  1 , an ideal output should be a signal AmpV o  symmetrical to zero voltage (as shown on the top right of  FIG. 1 ), “Amp” represents the amplification factor of the operational amplifier  1 . However, the real output will often be AmpV o +V offset  (as shown on the bottom right of  FIG. 1 ) which is deviated from the zero votage due to some design or manufacturing defects of the operational amplifier  1 . V offset  is the offset voltage generated by the operational amplifier  1 .  
         [0003]     Due to the manufacturing deviation of the operational amplifier  1 , sometimes the value of the V offset  is positive, but sometimes it is negative, so it will have an unpredictable influence over the circuit connected to the operational amplifier  1 .  
         [0004]     The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.  
       SUMMARY OF THE INVENTION  
       [0005]     The primary objective of the present invention is to provide a method for single-end compensation of an operational amplifier, which comprises: designing an operational amplifier having a single-end offset style, preparing a common-mode circuit, a switch circuit, a comparator, a digital circuit and a compensation circuit;  
         [0006]     wherein a set of double-end input signals of the operational amplifier is initially inputted to the common circuit and the switch circuit, and then the common mode circuit will generate an average signal that will be transmitted to the operational amplifier via the switch circuit;  
         [0007]     outputs of the operational amplifier will generate a single-end offset voltage which is inputted to the comparator, so that the comparator will generate an initial output to trigger the digital circuit;  
         [0008]     the digital circuit will generate a group of digital signals to make the compensation circuit generate a compensation current;  
         [0009]     the compensation current is provided to the operational amplifier to compensate the single-end offset voltage of the operational amplifier;  
         [0010]     when the single-end offset voltage of the operational amplifier is converted, the output of the comparator will change state and will be detected by the digital circuit, so that the digital circuit will fix the group of digital signals and instruct the switch circuit to block the average signal of the common mode circuit, allowing the set of double-end signals to be inputted to the operational amplifier directly.  
         [0011]     The present invention will become more obvious from the following description when taken in connection with the accompanying drawings, which show, for purpose of illustrations only, the preferred embodiment in accordance with the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  shows the offset phenomenon of an operational amplifier;  
         [0013]      FIG. 2  is a circuit diagram of an operational amplifier;  
         [0014]      FIG. 3  is a circuit diagram of an operational amplifier with an offset voltage;  
         [0015]      FIG. 4  is a circuit diagram of an operational amplifier with an offset compensation in accordance with the present invention;  
         [0016]      FIG. 5  is a block diagram of an operational amplifier with single-end offset compensation in accordance with the present invention;  
         [0017]      FIG. 6  shows the common mode circuit in accordance with the present invention;  
         [0018]      FIG. 7  shows a circuit diagram of the digital circuit in accordance with the present invention;  
         [0019]      FIG. 8  shows a compensation circuit in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0020]     Referring to  FIG. 2 , which is a circuit diagram of an operational amplifier  1  and includes a first differential amplifier and a second differential amplifier. The first amplifier comprises two MOS transistors m 1  and m 2 , and the second amplifier comprises MOS transistors m 3 , m 4 , m 5 , m 6 , m 7  and m 8 . Input signals Vin, Vip are inputted to the points “a” and “b” and ouput signals are outputted from the points “c” and “d”. In an ideal condition, the current passing through the MOS transistors m 1 , m 2  will be 1/s Is (Is=I 1 =I 2 =I 3 ), and the current passing through the MOS transistors m 3 , m 4 , m 5  and m 6 , m 7 , m 8  will also be 1/2 Is. In this situation, the offset voltage V offset  between the output points “c” and “d” is zero.  
         [0021]     Referring to  FIG. 3 , which is a circuit diagram of an operational amplifier  1  with an offset voltage V offset . The currents passing through the MOS transistors m 1  and m 2  are unbalanced, wherein the current of the MOS transistor m 1  is 1/2 Is+ΔI, while the current of the MOS transistor m 2  is 1/2 Is−ΔI. Consequently, the currents passing through the MOS transistors m 3 , m 4 , m 5  and m 6 , m 7  and m 8  are unbalanced in such a manner the current of the MOS transistors m 3 , m 4 , m 5  is 1/2 Is−ΔI and the current of the MOS transistors m 6 , m 7  and m 8  is 1/2 Is+ΔI. In this situation, an offset voltage V offset  will be generated between the output points “c” and “d”.  
         [0022]     Referring to  FIG. 4 , which is a circuit diagram of an operational amplifier  1  with an offset compensation. A current resource  14  is connected to the point A and its current value is 2ΔI, and the current resource  14  will be added to the current of MOS transistors m 3 , m 4  and m 5 , so that the current of the MOS transistors m 3 , m 4  and m 5  will be changed from 1/2 Is−Δ I to 1/2 Is+Δ I that is equal to the current of the MOS transistors m 6 , m 7  and m 8 . In this case, no offset voltage V offset  will be generated between the output points “c” and “d”.  
         [0023]     Referring to  FIG. 5 , which is a block diagram of an operational amplifier  1  with single-end offset compensation in accordance with the present invention and comprises an operational amplifier  1 , a common-mode circuit  2 , a switch circuit  3 , a comparator  4 , a digital circuit  5  and a compensation circuit  6 .  
         [0024]     Conventionally, input signals Vin and Vip should be inputted to the operational amplifier  1 , however, in the present invention, input signals Vin and Vip are initially inputted to the common-mode circuit  2  and the switch circuit  3 . After the input signals Vin and Vip are inputted to the common mode circuit  2 , a signal (Vin+Vip)/2 will be generated by the common mode circuit  2  and outputted from point D to the switch circuit  3 , and then transmitted from the switch circuit  3  to the operational amplifier  1 . Meanwhile, the switch circuit  3  will prevent the input signals Vin and Vip from inputting to operational amplifier  1 .  
         [0025]     The operational amplifier  1  is deliberately designed to be a single-end offset circuit, for example, the currents I 2  and I 3  in  FIG. 4  are deliberately designed to be different from each other. This can be achieved simply by making the sizes of the MOS transistors different with each other. When the operational amplifier  1  is designed to be a single-side offset circuit, a single-end offset voltage will be generated apparently between the output points “c” and “d”. The voltages of points “c” and “d” is inputted to the comparator  4 , and the difference of the voltages of points “c” and “d” will cause the comparator  4  to generate output signal to trigger the digital circuit  5  through point “B”, and thereafter for driving the compensation circuit  6 .  
         [0026]     The compensation circuit  6  acts as the current resource I 4  as shown in  FIG. 4  and is connected to the operational amplifier  1  at the point A. As the current of the compensation circuit  6  increases, it will provide a compensation action for the offset voltage V offset  of operational amplifier  1 . Therefore, the offset voltage between the points “c” and “d” of the operational amplifier  1  will be reduced.  
         [0027]     Once the offset voltage between the points “c” and “d” is converted, the output signal of the comparator  4  will accordingly change state, and the digital circuit  5  will detect this change and keep a group of digital signals of the digital circuit  5  constant. Meanwhile, the digital circuit  5  will control the switch circuit  3  via the point “C” so as to block the output signals (Vin+Vip)/2 of the common mode circuit  2 , while allowing the input signals Vin and Vip to be inputted to the operational amplifier  1  directly. Since the operational amplifier  1  has received the compensation from the compensation circuit  6 , no offset voltage will be generated on the operational amplifier  1 .  
         [0028]     It is to be noted that the operational amplifier  1  is not a close circuit but an open circuit since it is provided with no feedback circuit.  
         [0029]     Referring to  FIG. 6 , which shows the common mode circuit  2  which is a symmetrical MOS circuit. After it is inputted from both ends thereof with the input signals Vin and Vip, a signal V EQ  will be generated at the point D, and the signal V EQ =(Vin+Vip)/2. The average signal V EQ  will then be transmitted to the operational amplifier  1  via the switch circuit  3 . If the operational amplifier  1  is very ideal, no offset voltage V offset  will be produced. However, the operational amplifier  1  is purposely designed to be a single-end offset circuit, consequently, the signal V EQ  will enable the operational amplifier  1  to generate an obvious offset voltage V offset  initially.  
         [0030]     Referring to  FIG. 7 , which shows a circuit diagram of the digital circuit  5 . The digital circuit  5  comprises an oscillation circuit  51 , a counter  52 , a latch  53  and a detection circuit  54 . The initial output of the comparator  4  triggers the oscillation circuit  51  via the point “B”, the counter  52  serves to count the oscillation time. As the oscillation time increases, the outputs e, f, g, h, i, j, k, l and m of the latch  53  will each generate a constant digital signal one by one gradually, for driving the compensation circuit  6 . When the output of the comparator  4  change state, it will be detected by the detection circuit  54 , so that a signal will be sent to lock the output state of the latch  53  and to make the switch circuit  3  block the output signals (Vin+Vip)/2 of the common mode circuit  2 , allowing the input signals Vin and Vip to be inputted to the operational amplifier  1  directly.  
         [0031]     The oscillation circuit  51  can be replaced with a clock circuit on an IC chip.  
         [0032]     Referring to  FIG. 8 , which shows a compensation circuit  6 . The compensation circuit  6  comprises 9 sets of double MOS transistors that are connected in parallel. An end of the compensation circuit  6  is connected to the operational amplifier  1  via the point A, the outputs e, f, g, h, i, j, k, l and m of the latch  53  are inputted to the gates of the 9 upper MOS transistors respectively, so as to turn on the respective upper transistors. The gates of the 9 lower MOS transistors are connected one another and controlled by a steady bias voltage. Once the upper MOS transistors are turned on, current will be allowed to flow through the lower MOS transistors. The outputs e, f, g, h, i, j, k, l and m of the latch  53  generate constant digital signal one by one gradually to turn on the respective upper MOS transistors. When the current generated by the parallel-connected MOS transistors is great enough, the operational amplifier  1  will be compensated, thus eliminating the offset voltage V offset .  
         [0033]     While we have shown and described embodiment in accordance with the present invention, it should be clear to those skilled in the art that further embodiments may be made without departing from the scope of the present invention.