Abstract:
In a display control apparatus for applying to a display panel first gamma voltages within a first voltage region with reference to two first reference voltages, a gamma voltage generating circuit is adapted to generate second gamma voltages within a second voltage range. A maximum voltage of the second voltage range is lower than a maximum voltage of the first voltage range. At least one digital-to-analog converter is adapted to select one of the second gamma voltages in accordance with a digital video data signal, and at least one output buffer is adapted to step up the selected one of the second gamma voltages into a respective one of the first gamma voltages. The respective one of the first gamma voltages is applied to the display panel.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a display control apparatus for a display panel such as a liquid crystal display (LCD) panel, a plasma display panel or an inorganic electroluminescence (EL) display panel.  
         [0003]     2. Description of the Related Art  
         [0004]     Generally, a prior art display control apparatus is constructed by a gamma voltage generating circuit adapted to generate gamma voltages (multi-gradation voltages) within a voltage range, a digital-to-analog (DA) converter circuit including a plurality of DA converters each adapted to select one of the gamma voltages in accordance with display data, and an output buffer circuit including a plurality of output buffers each adapted to amplify the selected gamma voltages and apply it to a display panel. Each of the output buffers is formed by an operational amplifier, a feedback resistor and a resistor, to form an amplifier (see: JP-11-184444 A). This will be explained later in detail.  
         [0005]     Since the output buffer has amplification, the voltage level of the selected gamma voltage can be decreased, so that the operating voltage of the DA converter is decreased. Thus, the breakdown voltage of the DA converter can be decreased so that the DA converter can be decreased in size if the DA converter is manufactured by a conventional manufacturing process for the low breakdown voltage elements, thus decreasing the apparatus in size.  
       SUMMARY OF THE INVENTION  
       [0006]     In the above-described prior art display control apparatus, however, the amplification of the output buffer depends upon the selected gamma voltage and a voltage required for driving the display panel. Therefore, if the displayed white level or the displayed black level is adjusted, the white level voltage or the black level voltage as well as the resistance values of the output buffer need to be adjusted.  
         [0007]     Additionally, since the level shift circuit is required the apparatus would be increased in size.  
         [0008]     According to the present invention, in a display control apparatus for applying to a display panel first gamma voltages within a first voltage region with reference to two first reference voltages, a gamma voltage generating circuit is adapted to generate second gamma voltages within a second voltage range. A maximum voltage of the second voltage range is lower than a maximum voltage of the first voltage range. At least one digital-to-analog converter is adapted to select one of the second gamma voltages in accordance with a digital display data signal, and at least one output buffer is adapted to step up the selected one of the second gamma voltages to a respective one of the first gamma voltages. The respective one of the first gamma voltages is applied to the display panel. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0010]      FIG. 1  is a block circuit diagram illustrating a prior art display control apparatus;  
         [0011]      FIG. 2  is a detailed circuit diagram of the gamma voltage generating circuit of  FIG. 1 ;  
         [0012]      FIG. 3  is a detailed circuit diagram of the DA converter of  FIG. 1 ;  
         [0013]      FIG. 4  is a detailed circuit diagram of the output buffer of  FIG. 1 ;  
         [0014]      FIG. 5  is a block circuit diagram illustrating a first embodiment of the display control apparatus according to the present invention;  
         [0015]      FIG. 6  is a detailed circuit diagram of the gamma voltage generating circuit of  FIG. 5 ;  
         [0016]      FIG. 7  is a detailed circuit diagram of the DA converter of  FIG. 5 ;  
         [0017]      FIG. 8  is a detailed circuit diagram of the output buffer of  FIG. 5 ;  
         [0018]      FIG. 9  is a block circuit diagram illustrating a second embodiment of the display control apparatus according to the present invention;  
         [0019]      FIG. 10  is a detailed circuit diagram of the output buffer of  FIG. 9 ;  
         [0020]      FIG. 11  is a timing diagram for explaining the operation of the output buffer of  FIG. 10 ;  
         [0021]      FIG. 12  is a block circuit diagram illustrating a third embodiment of the display control apparatus according to the present invention;  
         [0022]      FIG. 13  is a detailed circuit diagram of the gamma voltage generating circuit of  FIG. 12 ;  
         [0023]      FIG. 14  is a detailed circuit diagram of the output buffer of  FIG. 12 ;  
         [0024]      FIG. 15  is a timing diagram for explaining the operation of the gamma voltage generating circuit of  FIG. 13 ; and  
         [0025]      FIG. 16  is a timing diagram for explaining the operation of the output buffer of  FIG. 14 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]     Before the description of the preferred embodiments, a prior art display control apparatus will be explained with reference to  FIGS. 1, 2 ,  3  and  4  (see: JP-11-184444 A).  
         [0027]     In  FIG. 1 , a prior art display control apparatus  100  is such as an LCD control apparatus is provided between a controller  200  and a display panel  300  such as an LCD panel.  
         [0028]     The display control apparatus  100  is constructed by a gamma voltage generating circuit  101 , a latch circuit  102 , a level shift circuit  103 , a DA converter circuit  104 , and an output buffer circuit  105 .  
         [0029]     The controller  200  is operated under a low voltage condition, while the display panel  300  is operated under a high voltage condition. Therefore, since the display control apparatus  100  is positioned between the controller  200  and the display panel  300 , the display control apparatus  100  is operated under the low voltage condition and the high voltage condition. In more detail, the latch circuit  102  is operated under the low voltage condition while the gamma voltage generating circuit  101 , the level shift circuit  103 , the DA converter circuit  104  and the output buffer circuit  105  are operated under the high voltage condition.  
         [0030]     The gamma voltage generating circuit  101  generates gamma voltages (multi-gradation voltages) V 1  to V H  corresponding to a gamma curve of the display panel  300  with reference to a white level voltage V W  and a black level voltage V B . This will be explained later in detail.  
         [0031]     The latch circuit  102  is formed by latches  102 - 1 ,  102 - 2 , . . . ,  102 - n  for receiving video data signals D- 1 , D- 2 , . . . , D-n from the controller  200 .  
         [0032]     The level shift circuit  103  is formed by level shifters  103 - 1 ,  103 - 2 , . . . ,  103 - n  for shifting the video data signals D- 1 , D- 2 , . . . , D-n under the low voltage condition to generate video data signals D′- 1 , D′- 2 , . . . , D′-n under the high voltage condition.  
         [0033]     The DA converter circuit  104  is formed by DA converters  104 - 1 ,  104 - 2 , . . . ,  104 - n  for performing DA conversions upon the level-shifted video data signals D′- 1 , D′- 2 , . . . , D′-n using the gamma voltages V 1  to V H  to generate analog voltages VS- 1 , VS- 2 , . . . , VS-n. This will be explained later in detail.  
         [0034]     The output buffer circuit  105  is formed by output buffers  105 - 1 ,  105 - 2 , . . . ,  105 - n  for amplifying the analog voltages VS- 1 , VS- 2 , . . . , VS-n to generate video output voltages V out - 1 , V out - 2 , . . . , V out -n which are applied to the display panel  300  such as data lines thereof. This will be explained later in detail.  
         [0035]     As illustrated in  FIG. 2 , the gamma voltage generating circuit  101  of  FIG. 1  is formed by an operational amplifier  1011  serving as a voltage follower  1011  for performing an impedance conversion upon the white level voltage V W , an operational amplifier  1012  serving as a voltage follower for performing an impedance conversion upon the black level voltage V B , and a voltage divider  1013  formed by resistors connected in series whose ends are connected to the outputs of voltage followers  1011  and  1012 . The resistance values of the resistors of the voltage divider are adapted for the gamma curve of the display panel  300  to generate gamma voltages V 1 , V 2 , . . . , V H  within a range from V B  to V W .  
         [0036]     As illustrated in  FIG. 3 , the DA converter  104 - i  of  FIG. 1  is formed by a decoder  1041  for decoding the level-shifted video data signal D′-i to generate a selection signal SEL, and a selector  1042  for selecting one of the gamma voltages V 1  to V H  in accordance with the selection signal SEL to generate the analog voltage VS-i. In this case, since the gamma voltages V 1  to V H  are of a large amplitude, the switching elements of the DA converter  104 - i  need to be high breakdown voltage elements, which would increase the size thereof.  
         [0037]     As illustrated in  FIG. 4 , the output buffer  105 - i  of  FIG. 1  is formed by an operational amplifier  1051 , a feedback resistor  1052  and a resistor  1053 , thus forming an amplifier having an amplification β defined by 
 
β=1 +R   f   /R   1  
 
         [0038]     where R f  is a resistance value of the feedback resistor  1052 ; and  
         [0039]     R 1  is a resistance value of the resistor  1053 .  
         [0040]     Since the output buffer  105 - i  has the amplification β, the voltage level of the analog voltage VS-i can be decreased by 1/β, so that the operating voltage of the DA converter  104 - i  is decreased. Thus, the breakdown voltage of the DA converter  104 - i  can be decreased so that the DA converter  104 - i  can be decreased in size if the DA converter  104 - i  is manufactured by a conventional manufacturing process for the low breakdown voltage elements, thus decreasing the apparatus in size.  
         [0041]     In the output buffer  105 - i , however, the amplification β depends upon the analog voltage VS-i and a voltage required for driving the display panel  300 . Therefore, if the displayed white level or the displayed black level is adjusted, the white level voltage V W  or the black level voltage V B  as well as the resistance values Rf and R 1  need to be adjusted. In the case of adjusting the resistance values Rf and R 1 , various resistors and switching circuits therefor need to be provided in advance, which would complicate the circuit configuration. Note that, the finer the adjustment of the resistance values Rf and R 1 , the larger the number of resistors and switching circuits. Further, in the case of only one of the displayed white level and the displayed black level being adjusted, an offset adjustment would be required, which would further complicate the circuit configuration.  
         [0042]     Still, since the level shift circuit  103  is required between the latch circuit  102  and the DA converter circuit  104 , the apparatus would be increased in size.  
         [0043]     In  FIG. 5 , which illustrates a first embodiment of the display control apparatus according to the present invention, a display control apparatus  10  such as an LCD control apparatus is provided between a controller  20  and a display panel  30  such as an LCD panel. Note that the controller  20  and the display panel  30  correspond to the controller  200  and the display panel  300 , respectively, of  FIG. 1 .  
         [0044]     The display control apparatus  10  is constructed by a gamma voltage generating circuit  11 , a latch circuit  12 , a DA converter circuit  14 , and an output buffer circuit  15 . Since the level shift circuit  103  of  FIG. 1  is not provided, the apparatus  10  can be decreased in size. Also, the latch circuit  12  and the DA converter circuit  14  are operated under the low voltage condition while the gamma voltage generating circuit  11  and the output buffer circuit  15  are operated under the high voltage condition.  
         [0045]     As illustrated in  FIG. 6 , the gamma voltage generating circuit  11  of  FIG. 5  includes resistors  111 ,  112 ,  113  and  114  in addition to the elements of the gamma voltage generating circuit  101  of  FIG. 2 . The resistors  111  and  112  divide the white level voltage V W  to generate 
 
V W /(1+α) 
 
         [0046]     where β is a resistance ratio of the resistor  111  to the resistor  112 . Similarly, the resistors  113  and  114  divide the black level voltage V B  to generate 
 
V B /(1+α) 
 
         [0047]     where α is a resistance ratio of the resistor  113  to the resistor  114 . Therefore, the voltage divider  1013  generates gamma voltages VG 1 , VG 2 , . . . , VG H  with reference to V B /(1+α) to V W /(1+α).  
         [0048]     The gamma voltages VG 1 , VG 2 , . . . , VG H  can be processed within a circuit which can be manufactured by a conventional process for manufacturing low breakdown voltage elements.  
         [0049]     Also, in  FIG. 6 , since the resistance ratio α is accurately realized by the relative sizes of the resistors  111 ,  112 ,  113  and  114 , the gamma voltages VG 1 , VG 2 , . . . , VG H  can be accurately determined by the resistance ratio α.  
         [0050]     As illustrated in  FIG. 7 , the DA converter  14 - i  of  FIG. 5  includes a selector  1042 ′ instead of the selector  1042  of  FIG. 3 . The selector  1042 ′ selects one of the gamma voltages VG 1  to VG H  in accordance with the selection signal SEL to generate the analog voltage VS-i. In this case, since the gamma voltages VG 1  to VG H  are of a small amplitude, the switching elements of the DA converter  14 - i  need to be low breakdown voltage elements, which would decrease the size thereof.  
         [0051]     As illustrated in  FIG. 8 , the output buffer  15 - i  of  FIG. 5  includes a feedback resistor  1052 ′ and a resistor  1053 ′ instead of the feedback resistor  1052  and the resistor  1053  of  FIG. 4 . That is, the resistance ratio of the feedback resistor  1052 ′ to the resistor  1053 ′ is set to be α. Therefore, the output buffer  15 - i  forms an amplifier having an amplification (1+α).  
         [0052]     As stated above, the gamma voltage generating circuit  11  generates the gamma voltages VG 1  to VG H  which are 1/(1+α) times the gamma voltages VG 1  to VG H . Therefore, if the DA converter  12 - i  selects the gamma voltage VG X , then 
 
VS-i=VG X  
 
= V   X /(1+α) 
 
         [0053]     On the other hand, since the output buffer  12 - i  generates the video output signal V out -i by amplifying the gamma voltage VG X  by the amplification (1+α), i.e., 
 
 V   out - i=VG   X ·(1+α) 
 
=V X  
 
         [0054]     Thus, the video output signal V out -i applied to the display panel  30  is the same as the gamma voltage V X  which should be originally applied to the display panel  30 .  
         [0055]     Also, in  FIG. 8 , since the resistance ratio α is accurately realized by the relative sizes of the resistors  1052 ′ and  1053 ′, the amplification (1+α) of the output buffer  15 - i  can be accurately determined by the resistance ratio α.  
         [0056]     Thus, in the above-described first embodiment, the gamma voltage generating circuit  11  generates the gamma voltages VG 1  to VG H  with reference to V W /(1+α) and V B /(1+α) by adjusting the relative sizes of the resistors  111 ,  112 ,  113  and  114 . The gamma voltages VG 1  to VG H  are so low that they are processed in elements which can be manufactured by a conventional process for manufacturing low breakdown voltage elements, and are 1/(1+α) of the voltage V 1  to V H  which should be originally applied to the display panel  20 . One of the gamma voltages VG 1  to VG H  is selected by the DA converter  12 - i  and is amplified with the amplification (1+α) of the output buffer  15 - i  to obtain the video output signal V out -I the same as the originally-applied to the display panel  20 .  
         [0057]     In the above-described first embodiment, if the displayed white level or the displayed black level is adjusted, only the white level voltage V W  or the black level voltage V B  is adjusted. Therefore, no resistors and switching circuits for adjusting the displayed white level or the displayed black level are necessary in the output buffer  15 - i , which would simplify the circuit configuration.  
         [0058]     In  FIG. 9 , which illustrates a second embodiment of the display control apparatus according to the present invention, the controller  20  of  FIG. 5  is replaced by a controller  20 A, and the output buffer  15 - i (i=1, 2, . . . , n) of  FIG. 5  is replaced by an output buffer  15 A-i(i=1, 2, . . . , n). Timing signals φ a  and φ b  opposite in phase to each other are supplied from the controller  20 A to the output buffer  15 - i.    
         [0059]     As illustrated in  FIG. 10 , the output buffer  15 A-i includes a capacitor  1054  and switches  1055  to  1059  in addition to the elements of the output buffer  15 - i  of  FIG. 8 . The switch  1055  is connected to the non-inverted input of the operational amplifier  1051 ; the switch  1056  is connected between the resistor  1053 ′ and the ground terminal GND; the switch  1057  is connected between the output of the operational amplifier  1051  and the capacitor  1054 ; the switch  1058  is connected between the capacitor  1054  and the input of the operational amplifier  1051 , and the switch  1059  is connected between the output of the operational amplifier  1051  and the display panel  30 . The switches  1055 ,  1056  and  1057  are turned ON and OFF by the timing signal φ a , while switches  1058  and  1059  are turned ON and OFF by the timing signal φ b . That is, when the timing signals φ a  and φ b  are high and low, respectively, the switches  1055 ,  1056  and  1057  are turned ON and the switches  1058  and  1059  are turned OFF, while, when the timing signals φ a  and φ b  are low and high, respectively, the switches  1058  and  1059  are turned ON and the switches  1055 ,  1056  and  1057  are turned OFF. Note that V i  and V 0  designate voltages at a non-inverted input and an output of the operational amplifier  1051 .  
         [0060]     The operation of the output buffer  15 A-i of  FIG. 10  is explained next with reference to  FIG. 11 .  
         [0061]     In a charging time period T 1  where the timing signals φ a  and φ b  are high and low, respectively, the switches  1055 ,  1056  and  1057  are turned ON and the switches  1058  and  1059  are turned OFF. As a result, the analog voltage VS-i which is in this case VG X =V X /(1+α) is supplied via the turned-ON switch  1055  to a non-inverted input of the operational amplifier  1051 , so that the input voltage V i  is given by  
               V   i     =     VG   X                 =       V   X     /       (     1   +   α     )     .                 
 
 Also, since the switch  1056  is turned ON, the operational amplifier  1051  with the resistors  1052 ′ and  1053 ′ serves as an amplifier having the amplification of (1+α), so that the output voltage V 0  is given by  
               V   0     =       V   i     ·     (     1   +   α     )                   =       VG   X     ·     (     1   +   α     )                   =         V   X     /     (     1   +   α     )       ·     (     1   +   α     )                   =       V   X     .               
 
         [0062]     Thus, since the switch  1057  is turned ON, the capacitor  1054  is charged by the voltage V 0  (=V X ), so that the voltage V 0  at the capacitor  1054  is also V 0  (=V X ). In this case, since the switches  1058  and  1059  are turned OFF, the voltages V 0  and V C  are isolated from the input voltage V i  and the video output signal V out -i.  
         [0063]     Next, in a holding time period T 2  where the timing signals φ a  and φ b  are low and high, respectively, the switches  1058  and  1059  are turned ON and the switches  1055 ,  1056  and  1057  are turned OFF. As a result, since the switch  1058  is turned ON, the input voltage V i  becomes the voltage V C  at the capacitor  1054 , so that the capacitor  1054  is moved from a charging state to a holding state. That is,  
               V   i     =     V   C                 =       VG   X     ⁡     (     1   +   α     )                   =     V   X               
 
         [0064]     In this case, since the input impedance of the operational amplifier  1051  is very large, the capacitor  1054  is hardly discharged, so that the voltage V C  remains at about the same level. Thus, the capacitor  1054  can serve as an analog memory which carries out a storing operation during the charging time period T 1  and carries out an outputting operation during the holding time period T 2 .  
         [0065]     On the other hand, since the switch  1056  is turned OFF, the operational amplifier  1051  serves as a voltage follower, so that the output voltage V 0  is same as the input voltage V i , i.e., V 0 =V i . Also, since the switch  1059  is turned ON, the video output signal V out -i is given by  
                 V   out     -   i     =     V   0                 =     V   i                 =     V   X               
 
         [0066]     Note that the video output signal V out -i during the time period T 1  remains at the level during the time period T 2  due to the line-to-line capacitance, since the switch  1059  is turned OFF.  
         [0067]     Thus, in the second embodiment, in the same way as in the first embodiment, the output buffer  15 A-i amplifies the compressed gamma voltages VG X  with the amplification of (1+α) to generate the original gamma voltages V X  (=VG x ·(1+α)). In addition, during the holding time period T 2 , since the switch  1056  is turned OFF, the output of the operational amplifier  1051  is shunted from the ground terminal GND, so that no current flows through the resistors  1052 ′ and  1053 ′, which would decrease the power consumption.  
         [0068]     In  FIG. 12 , which illustrates a third embodiment of the display control apparatus according to the present invention, the controller  20  of  FIG. 5  is replaced by a controller  20 B, the gamma voltage generating circuit  11  of  FIG. 5  is replaced by a gamma voltage generating circuit  11 B, and the output buffer  15 - i (i=1, 2, . . . , n) of  FIG. 5  is replaced by an output buffer  15 B-i(i=1, 2, . . . , n). Timing signals φ a  and φ b  opposite in phase to each other are supplied from the controller  20 B to the gamma voltage generating circuit  11 B and the output buffer  15 B-i.  
         [0069]     As illustrated in  FIG. 13 , the gamma voltage generating circuit  11 B is formed by an operational amplifier  131 W, capacitors  132 W and  133 W, and switches  134 W,  135 W,  136 W and  137 W for the white level voltage V W , an operational amplifier  131 B, capacitors  132 B and  133 B, and switches  134 B,  135 B,  136 B and  137 B for the black level voltage V B , and a voltage divider  138  formed by resistors connected in series whose ends are connected to the switches  137 W and  137 B. The resistance values of the resistors of the voltage divider  138  are adapted for the gamma curve of the display panel  30  to generate gamma voltages VG 1 , VG 2 , . . . , VG H  within a range from V B /(1+α) to V W /(1+α).  
         [0070]     The white level voltage V W  is applied to the non-inverted input of the operational amplifier  131 W. The output of the operational amplifier  131 W is connected via the capacitor  132 W and the switch  134 W to the inverted input of the operational amplifier  131 W. In this case, the switch  134 W is connected in parallel to the capacitor  132 W to discharge the capacitor  132 W. Also, the capacitor  133 W is connected via the switch  135 W to the ground terminal GND. In this case, the switch  135 W is used for charging the capacitor  133 W. Further, the switch  136 W is used for connecting the capacitor  132 W and  133 W in parallel to each other. The output of the operational amplifier  131 W is connected to the voltage divider  138 . The capacitance ratio of the capacitor  132 W to the capacitor  133 W is 1/α.  
         [0071]     The switches  134 W and  135 W are turned ON and OFF by the timing signal φ a , and the switches  136 W and  137 W are turned ON and OFF by the timing signal φ b .  
         [0072]     The black level voltage V B  is applied to the non-inverted input of the operational amplifier  131 B. The output of the operational amplifier  131 B is connected via the capacitor  132 B and the switch  134 B to the inverted input of the operational amplifier  131 B. In this case, the switch  134 B is connected in parallel to the capacitor  132 B to discharge the capacitor  132 B. Also, the capacitor  133 B is connected via the switch  135 B to the ground terminal GND. In this case, the switch  135 B is used for charging the capacitor  133 B. Further, the switch  136 B is used for connecting the capacitor  132 B and  133 B in parallel to each other. The output of the operational amplifier  131 B is connected to the voltage divider  138 . The capacitance ratio of the capacitor  132 B to the capacitor  133 B is 1/α.  
         [0073]     The switches  134 B and  135 B are turned ON and OFF by the timing signal φ a , and the switches  136 B and  137 B are turned ON and OFF by the timing signal φ b .  
         [0074]     As illustrated in  FIG. 14 , the output buffer  15 B-i is formed by an operational amplifier  151 , capacitor  152  and  153 , and switches  154 ,  155 ,  156  and  157 .  
         [0075]     The analog voltage VS-i is applied to the non-inverted input of the operational amplifier  151 . The output of the operational amplifier  151  is connected via the capacitor  152  and the switch  154  to the inverted input of the operational amplifier  151 . In this case, the switch  154  is connected in parallel to the capacitor  152  to discharge the capacitor  152 . Also, the capacitor  153  is connected via the switch  155  to the ground terminal GND. In this case, the switch  155  is used for charging the capacitor  153 . Further, the switch  156  is used for connecting the capacitors  152  and  153  in parallel to each other. The output of the operational amplifier  151  is connected via the switch  157  to the display panel  20 . The capacitance ratio of the capacitor  152  to the capacitor  153  is 1/α.  
         [0076]     The switches  154  and  155  are turned ON and OFF by the timing signal φ a  and the switches  156  and  157  are turned ON and OFF by the timing signal φ b .  
         [0077]     The operation of the gamma voltage generating circuit  11 B of  FIG. 13  is explained next with reference to  FIG. 15 .  
         [0078]     In a time period T 1  where the timing signals φ a  and φ b  are high and low, respectively, the switches  134 W and  135 W are turned ON and the switches  136 W and  137 W are turned OFF. As a result, the output of the operational amplifier  131 W is connected directly to the inverted input thereof, and the capacitor  133 W is connected between the output of the operational amplifier  131 W and the ground terminal GND. Therefore, since the capacitor  132 W is short-circuited by the switch  134 W, the operational amplifier  131 W is operated as a voltage buffer. Therefore, the output voltage V 1W  of the operational amplifier  131 W is the white level voltage V W , i.e., 
 
V 1W =V W  
 
         [0079]     In this case, the capacitor  133 W is charged at Q 1  represented by 
 
 Q 1 =αC·V   W  
 
         [0080]     where αC is the capacitance of the capacitor  133 W.  
         [0081]     In this case, since the switch  137 W is turned OFF, the voltage V 1W  is isolated from the voltage divider  138 .  
         [0082]     Next, in a time period T 2  where the timing signals φ a  and φ b  are low and high, respectively, the switches  136 W and  137 W are turned ON and the switches  134 W and  135 W are turned OFF. As a result, the capacitors  132 W and  133 W are connected in parallel between the non-inverted input and output of the operational amplifier  131 W. In this case, since the voltage between the inverted input voltage V W  and the output voltage V 1W  of the operational amplifier  131 W is applied to a combined capacitance of the capacitors  132 W and  133 W, the capacitors  132 W and  133 W are charged at Q 2  by 
 
 Q 2=( V   W −V 1W )·( C+αC ) 
 
         [0083]     where C and αC are the capacitances of the capacitors  132 W and  133 W, respectively. Here, Q 1 =Q 2 , then 
 
 V   1W   =V   W /(1+α) 
 
         [0084]     Also, since the switch  137 W is turned ON, the voltage V 2W  is also given by 
 
 V   2W   =V   W /(1+α) 
 
         [0085]     The above-described operation for the white level voltage V W  is true for the black level voltage V B . Therefore, during the discharging period T 2 , 
 
 V   1B   =V   2B   =V   B /(1+α) 
 
         [0086]     Thus, during the time period T 2 , the voltage V 2W  (=V W /(1+α)) and the voltage V 2B (=V B /(1+α)) are applied to the voltage divider  138 . As a result, gamma voltages VG 1  to VG H  are generated with reference to V W /(1+α) and V B /(1+α) by adjusting the capacitance ratio  11   a  of the capacitor  132 W ( 132 B) to the capacitor  133 W ( 133 B). In this case, if a current hardly flows from the gamma voltage generating circuit  11 B to the DA converter  14 - i , since the switch  137 W ( 137 B) is turned OFF during the time period T 1 , the output voltage V 2W (V 2B ) remains at the same level as that during the discharging period T 2 , as indicated by a dotted line.  
         [0087]     In the gamma voltage generating circuit  11 B, although currents only flow to charge the capacitors  132 W and  133 W ( 132 B and  133 B), since the operational amplifier  131 W ( 131 B) is shunted from the voltage divider  138  as well as the ground terminal GND during the time period T 2 , the power consumption can be decreased.  
         [0088]     The operation of the output buffer  15 B-i of  FIG. 14  is explained next with reference to  FIG. 16 .  
         [0089]     In a charging time period T 1  where the timing signals φ a  and φ b  are high and low, respectively, the switches  154  and  156  are turned ON and the switches  155  and  157  are turned OFF. As a result, since the capacitors  152  and  153  are short-circuited by the turned-ON switches  154  and  156  to discharge them, the operational amplifier  151  serves as a voltage follower. Therefore, the analog voltage VS-i which is in this case VG X =V X /(1+α) is the same as that of the output voltage V 0  of the operational amplifier  151 , i.e.,  
               V   0     =     VG   X                 =       V   X     /       (     1   +   α     )     .                 
 
 In this case, since the switch  157  is turned OFF, the voltage V 0  is isolated from the video output signal V out -i. 
 
         [0090]     Next, in a holding time period T 2  where the timing signals φ a  and φ b  are low and high, respectively, the switches  155  and  157  are turned ON and the switches  154  and  156  are turned OFF. As a result, the capacitors  152  and  153  are connected in series between the output of the operational amplifier  151  and the ground terminal GND, and also, the connection node between the capacitors  152  and  153  is connected to the inverted input of the operational amplifier  151 . In this case, since the input voltage V i  is applied to this connection node by the hypothetical short-circuit between the two inputs of the operational amplifier  151 , the capacitor  152  is charged at Q 3  by 
 
 Q 3 =C ·( V   0   −V   i ) 
 
         [0091]     where C is the capacitance of the capacitor  152 . Also, the capacitor  153  is charged at Q 4  by  
         Q   ⁢           ⁢   4     =     α   ⁢           ⁢     C   ·     V   i             
       Here   ,           ⁢     
     ⁢       Q   ⁢           ⁢   3     =     Q   ⁢           ⁢   4       ,     
     ⁢   then       
                 V   0     =       (     1   +   α     )     ⁢     V   i                   =       (     1   +   α     )     ·       V   X     /     (     1   +   α     )                     =     V   X             ⁢               
 
         [0092]     Also, since the switch  157  is turned ON, the video output signal V out -i is given by  
                 V   out     -   i     =     V   0                 =     V   X               
 
         [0093]     Note that the video output signal V out -i during the time period T 1  remains at the level during the time period T 2  due to the line-to-line capacitance, since the switch  157  is turned OFF.  
         [0094]     Thus, in the third embodiment, in the same way as in the second embodiment, the gamma voltage generating circuit  11 B generates the compressed gamma voltage VG 1  and the output buffer  15 B-i amplifies the compressed gamma voltage VG X  with the amplification of (1+α) to generate the original gamma voltage V X (=VG X ·(1+α)).  
         [0095]     In any of the above-described embodiments, since the DA converter  14 - i  is subject to the compressed gamma voltage V X /(1+α), the DA converter  14 - i  can be manufactured by a process for manufacturing low breakdown voltage elements, which would decrease the manufacturing cost. Also, when one of the displayed white level or the displayed black level is adjusted, only the white voltage V W  or the black voltage V B  is adjusted. Therefore, no adjustment of individual gamma voltages is necessary, which would simplify the circuit configuration.  
         [0096]     In the above-described third embodiment, the output buffer  15 B-i requires no resistor elements such as the resistors  1052 ′ and  1053 ′ in the first and second embodiments, which would decrease the power consumption. In the first and second embodiments, note that, if the video output signal V out -i is 5 μA, a current of 5 μA flows the resistors  1052 ′ and  1053 ′, which would increase the power consumption.