Abstract:
A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and −V 1  when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source V DD  and a control low power source V NEG . The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or −V 1  if IN is high when EN is high. Only single type V T  transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority of U.S. Provisional Application No. 62/295,151 (Attorney Docket No. GFSP2016PRO17US0), entitled “A Single VT Transistor Solution for Passing Changeable Negative Voltage to Selected Pins of Memory Cell” filed on Feb. 15, 2016, which is herein incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    In certain types of integrated circuits (ICs), changeable negative voltages may be employed. For example, certain types of functional circuits of the IC may require changeable negative voltages to improve their performance. However, conventional transmission circuits for passing a changeable negative voltage to the functional circuit require large area, may employ different type of V T  transistors and may require extra bias or clamping voltages. For example, conventional driver circuits include a p-type metal oxide transistor and a n-type metal oxide transistor coupled in series between high and low power sources. Such conventional driver circuits require large layout area especially when the design needs to have deep n-type well. 
         [0003]    In addition, the control signal used as an input of the driver circuit is very difficult to define the voltage level. The potential difference between high power source and the negative voltage is much larger than the normal device working range, it creates reliability problems for conventional driver circuits. For example, in a conventional driver circuit for passing the negative changeable voltage has V DD , such as 5V, as the high power source and the negative changeable voltage as its low power source. In such case, the p-type transistor and the n-type transistor both have reliability issues due to the negative voltage low power source. However, if V SS  or 0V is used as the high power source, the circuit would not function when the changeable negative voltage is 0V. 
         [0004]    The disclosure is directed to a compact and reliable changeable negative voltage transmission circuit for supplying a changeable negative voltage to a functional circuit of an integrated circuit. 
       SUMMARY 
       [0005]    Embodiments of the present disclosure generally relate to semiconductor devices. In one embodiment, a circuit for passing a changeable negative voltage (V NEG ) is disclosed. The V NEG  has a negative high state=−V 1  and a negative low state=0V. A control circuit block is disposed between control high and control low power sources, which the control low power source is V NEG . The control circuit block is configured to receive an enable signal EN and an input signal IN. Enable signal EN includes an enable high state and an enable low state. When EN is in the enable high state, V NEG =−V 1 . When EN is in the enable low state, V NEG =0V. The input signal IN includes an input high state and an input low state. The control circuit block is further configured to generate first output control signal CON and second output control signal CON_B in response to input signal IN. The transistors in the control circuit block are the same gate threshold (V T ) type transistors. A control circuit block is disposed between control high and control low power sources. The output driver circuit is configured to receive the CON and CON_B signals from the control circuit block. The output driver circuit is further configured to generate an output signal OUT. OUT=0V when IN is in the input low state; OUT=−V 1  when IN is in the input high state and EN is in the enable high state; and OUT=0V when EN is in the enable low state. 
         [0006]    In another embodiment, an output driver circuit for passing a changeable negative voltage is described. The output driver circuit includes a high power source and a low power source. The high power source is V SS  which=0V. The low power source includes a changeable negative voltage V NEG , which V NEG =0V when an enable signal EN is in an enable low state and V NEG =−V 1  when an enable signal EN is in an enable high state. The output driver circuit further includes first and second metal oxide semiconductor transistors. The transistors are coupled in series between high and low power sources and are the same gate threshold (V T ) type transistors. The output driver circuit further includes a first input, a second input and an output. The first input is coupled to a first gate of the first transistor and is configured to receive a first control signal CON_B. The second input is coupled to a second gate of the second transistor and is configured to receive a second control signal CON. CON and CON_B are complementary signals. The output is commonly coupled to the first and second transistors and is configured to generate an output signal OUT in response to the first and second input signals CON_B and CON. OUT=−V 1  when CON=a second control high state, CON_B=−V 1  and EN=enable high state, otherwise, OUT=0V. 
         [0007]    In yet another embodiment, a method for passing a negative changeable voltage V NEG  is disclosed. The method includes providing the negative changeable voltage which V NEG  has a negative high state=−V 1  and a negative low state=0V. An enable signal EN is provided to a control circuit block. The enable signal EN has an enable high state (V NEG =−V 1 ) and an enable low state (V NEG =0V). An input signal IN having an input high state and an input low state is provided to the control circuit block. Control output signals CON and CON_B are generated to an output circuit block in response to the input signal IN. An output signal is generated in response to CON and CON_B. OUT=0V when IN is in the input low state and EN is in the enable high state; OUT=−V 1  when IN is in the input high state and EN is in the enable high state; and OUT=0V when EN is in the enable low state. 
         [0008]    These and other objects, along with advantages and features of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which: 
           [0010]      FIG. 1  shows a simplified plan view of an embodiment of a semiconductor wafer; 
           [0011]      FIG. 2 a    shows an exemplary application of a device for receiving a negative voltage from a negative voltage transmission circuit; 
           [0012]      FIG. 2 b    shows an exemplary table containing biasing conditions for the device of  FIG. 2   a;    
           [0013]      FIG. 3  shows simplified block diagram of an embodiment of a changeable negative voltage transmission circuit; 
           [0014]      FIG. 4 a    shows a schematic diagram of an embodiment of a changeable negative voltage transmission circuit; 
           [0015]      FIG. 4 b    shows a schematic diagram of another embodiment of a changeable negative voltage transmission circuit; and 
           [0016]      FIG. 5  shows a timing diagram of the changeable negative voltage transmission circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Embodiments generally relate to semiconductor devices or integrated circuits (ICs). The devices or ICs can be incorporated into or used with, for example, consumer electronic products, particularly portable consumer products, such as cell phones, laptop computers and personal digital assistants (PDAs). 
         [0018]    The fabrication of devices may involve the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the ICs to perform the desired functions. To form the features and interconnections, layers are repeatedly deposited on the substrate and patterned as desired using lithographic techniques. For example, a wafer is patterned by exposing a photoresist layer with the pattern on a reticle with an exposure source. After exposure, the photoresist layer is developed, where the pattern of the reticle is transferred to the photoresist, and a photoresist etch mask is created. An etch is performed using the etch mask to replicate the pattern on the wafer below, which may include one or more layers, depending on the stage of the process. In the formation of an IC, numerous reticles may be used for different patterning processes. Furthermore, a plurality of ICs may be formed on the wafer in parallel. 
         [0019]      FIG. 1  shows a simplified plan view of an embodiment of a semiconductor wafer  101 . The semiconductor wafer, for example, may be a silicon wafer. The wafer may be a lightly doped p-type wafer. Other types of wafers, such as silicon-on-insulator (SOI), or silicon germanium wafer as well as doped wafers with other types of dopants or dopant concentrations may also be useful. 
         [0020]    The wafer includes an active surface  111  on which devices  115  are formed. A plurality of devices may be formed on the wafer in parallel. The devices, for example, are arranged in rows along a first (x) direction and columns along a second (y) direction. Wafer dicing process is then performed. When the process is completed, the wafer is diced along the dicing channels to singulate the devices into individual chips. 
         [0021]      FIG. 2 a    shows a cross-sectional view of an application of a device  200  which includes a functional circuit receiving a changeable negative voltage. The device includes a substrate. The device, for example, may be a part of the wafer, as described in  FIG. 1 . Common elements may not be described or described in detail. The substrate, for example, may be a semiconductor substrate, such as a silicon substrate. Other types of substrates or wafers may also be useful. The device may include doped regions having different dopant concentrations. For example, the device may include heavily doped (x + ), intermediately doped (x) and lightly doped (x) regions, where x is the polarity type which can be p or n. 
         [0022]    The substrate of the device, as shown, includes a device region  208 . The device region may include a functional circuit or device component which receives a changeable negative voltage. In one embodiment, the device region is a memory cell region with a memory cell  209 . The memory cell may be a non-volatile memory (NVM) cell. Other types of device components which employs or utilizes a changeable negative voltage may also be useful. 
         [0023]    Although the memory cell region is shown with one memory cell, it is understood that the cell region may include numerous memory cells interconnected to form a memory array. In addition, the device may include other device regions, such as low voltage (LV) device regions, medium voltage (MV) device regions and high voltage (HV) device regions. 
         [0024]    As shown, the device region includes first and second device wells. The first device well is a low voltage p-well (LVPWELL) and the second device well is a low voltage n-well (LVNWELL). A deep n-type well (DNWELL) may be provided. The DNWELL extends below the LVPWELL and LVNWELL. 
         [0025]    The memory cell includes a select gate (SG) and a first floating gate (FG) disposed on the substrate over the LVPWELL. A gate includes a gate electrode  232  over a gate dielectric  231 . As shown, the FG electrode is heavily doped with n-type dopants (n +  doped). Adjacent to the SG and FG are n +  doped first and second S/D regions  236  and  238 . The SG and first and second S/D regions of the SG form a select transistor. As shown, the second S/D region of the FG and the first S/D region of the SG form a common S/D region. In one embodiment, a second FG is disposed over the LVNWELL. The FG electrode is a n +  doped FG electrode. The second FG gate includes a n +  S/D region disposed in the LVNWELL adjacent to the second FG. The LVPWELL includes a p +  doped region which serves as a contact (PW) to the LVPWELL. 
         [0026]    The various components may serve as memory cell terminals. In one embodiment, the SG serves as SG terminal, the first S/D region of the SG serves as a source line (SL) terminal cell and the second S/D region of the first FG serves as a bitline (BL) terminal. The first S/D region of the second FG serves as a control gate line (CGL) terminal. The PW contact is a PW terminal for biasing the LVPWELL. 
         [0027]      FIG. 2 b    shows a table  201  containing bias or operating voltages for program and erase operations for different memory cell terminals. As shown, the PW is biased with a negative voltage −V 1  during a program operation and 0V during an erase operation for the selected cell. To one PW terminal, the bias is a changeable negative voltage. The negative voltage −V 1  may be, for example, −3V. Other negative voltages for −V 1  may also be useful. 
         [0028]      FIG. 3  shows a simplified block diagram of an embodiment of a negative voltage transmission circuit  300 . The transmission circuit transmits a changeable negative voltage. In one embodiment, the transmission circuit includes a control block or circuit  340  and an output block or circuit  310 . The control block, in one embodiment, is a level shifter circuit. Other types of control blocks may also be useful. The control block includes various sub-blocks coupled in series between a first power source and a second power source. In one embodiment, the first power source is V DD  or operating voltage of the device and the second power source is V NEG , which is a changeable negative voltage or power source. The changeable negative voltage V NEG  may be changed between two states, a negative low state and a negative high state. In one embodiment, the negative high state is −V 1  and the negative low state is 0V (V SS ). In one embodiment, −V 1 =−3V. Providing V NEG  with other negative voltages for −V 1  may also be useful. As for V DD , it may be about 5V. Providing other V DD  may also be useful. 
         [0029]    As shown, the control block includes an enable sub-block  350 , an input or select sub-block  360 , a reset sub-block  390 , a clamp sub-block  370  and a pull-down sub-block  380 . The enable sub-block is coupled to the first power source and receives an enable signal EN. In one embodiment, EN includes a first state and a second state. For example, the EN includes an active enable state and an inactive enable state. In one embodiment, the active EN is a logic 1 signal and the inactive state is logic 0 signal. For example, the active EN signal=V DD  (5V) and the inactive EN=V SS  (0V). The enable signal EN and V NEG  are correlated. In one embodiment, when EN is active, such as 5V, then V NEG =−V 1 . On the other hand, when EN is inactive, such as 0V, V NEG =0V. 
         [0030]    The input or select sub-block is coupled in series with the enable sub-block and receives input or select signals. The select signals are IN and its complement INB. The select signals IN and INB have active and inactive states. In one embodiment, an active IN signal is a logic 1 signal, such as V DD  (5V) and an inactive IN signal is a logic 0 signal, such as V SS  (0V). As for INB, an active INB signal is a logic 0 signal and an inactive INB signal is a logic 1 signal, such as V DD . Either active select signals IN and INB are input to the select sub-block or inactive select signals IN and INB is input to the select sub-block. For example, the sub-block receives active IN and INB signals or the sub-block receives inactive IN and INB signals. The node between the input and enable sub-block is node NM. When EN is active, which means the second power source V NEG  is at negative high state, the voltage at NM (V NM ) is less than V DD  due to a voltage drop of at least one transistor gate threshold voltage (V T ). For example, V NM =V DD −V T . Typically, the voltage drop caused by V T  is 0.7V. As such, V NM =V DD −0.7V. Additional transistors may be provided to provide a smaller V NM . For example, V NM =V DD −N*V T . In one embodiment, V NM +V 1 &lt;V DD . When EN is inactive, which means the second power source V NEG  is at negative low state, the voltage at NM (V NM ) is equal to V DD . 
         [0031]    The clamp sub-block is coupled in series with the input sub-block while the pull-down sub-block is disposed in series with the clamp sub-block and is coupled to V NEG . Between the input sub-block and clamp sub-block are first and second nodes NA and NB. In one embodiment, the clamp sub-block maintains the voltage at both NA and NB to be higher than V SS  (0V). This avoids reliability issues with transistors of the various sub-blocks, such as the enable, input and reset sub-blocks. 
         [0032]    Between the clamp sub-block and the pull-down sub-block are first and second output nodes NOA and NOB. In one embodiment, output signals of the control block, CON_B and CON, are coupled to NOA and NOB. For example, CON_B is coupled to NOA and CON is coupled to NOB. The two control block output signals, CON and CON_B, are complementary signals. 
         [0033]    As for the pull-down sub-block is configured to pull down CON or CON_B signal to V NEG , depending on IN. For example, CON is pull down to V NEG  when IN is inactive (IN=0V) or CON=V MN  when IN is active (IN=V DD ). On the other hand, CON_B is pulled down to V NEG  when IN=active or CON_B=V NM  when IN is inactive. 
         [0034]    The reset sub-block is configured to receive an enable reset pulse ENR_P. When the pulse is received, the reset sub-block pulls down node NM from V DD . In one embodiment, the sub-block creates a path between V DD  to V SS  as a result of ENR_P. This can eliminate the unwanted steady state of NM node. 
         [0035]    The output block, in one embodiment, is a switch circuit. The switch circuit is coupled between first and second output power sources. In one embodiment, the first power source is V SS  and the second power source is the changeable negative voltage source V NEG . In one embodiment, switch circuit employs one type of V T  transistors only. The switch circuit is controlled by the control block output signals CON and CON_B and generates an output signal OUT in response. In one embodiment, the switch circuit is configured to generate OUT=0V when IN is inactive (IN=0V) and EN is active (EN=V DD ). In the case where IN is active (IN=V DD ) and EN is active (EN=V DD ), OUT=−V 1 . In the case EN is inactive (EN=0V), OUT=0V. 
         [0036]      FIG. 4 a    shows a schematic diagram of an embodiment of a changeable negative voltage transmission circuit  400 . The transmission circuit is similar to that described in  FIG. 3 . Common elements may not be described or described in detail. The transmission circuit transmits a changeable negative voltage. In one embodiment, the transmission circuit includes a control block or circuit  340  and an output block or circuit  310 . 
         [0037]    The control block, in one embodiment, is a level shifter circuit. Other types of control blocks may also be useful. The control block includes first and second paths  441  and  442  coupled between V DD  and V NEG . The first path may be referred to as the left path and the second path may be referred to as the right path. The first path includes a plurality of transistors coupled in series between V DD  and V NEG ; the second path includes a plurality of transistors coupled in series V DD  and V NEG . The changeable negative voltage V NEG  may be changed between two states, 0V or −V 1  while V DD  may be about 5V. In one embodiment, −V 1  is about −3V. Other voltages for V NEG  and V DD  may also be useful. 
         [0038]    A transistor  470  may be a metal oxide semiconductor (MOS) transistor. The MOS transistor includes a gate  473  between first and second S/D terminals  477  and  478 . The gate is disposed on a substrate which may include a gate electrode  475  disposed over a gate dielectric  474 . As for the S/D terminals, they may be heavily doped regions in a transistor well in the substrate. The transistor well serves as a body  471  of the transistor in the substrate. A transistor may be a p-type or a n-type transistor. For a p-type transistor, the transistor well is n-type while the S/D regions are p-type; for a n-type transistor, the transistor well is p-type while the S/D regions are n-type. A p-type transistor is designated as MPx and a n-type transistor is designated as MNx. 
         [0039]    As shown, transistors which are in series have first and second S/D terminals which form a common S/D terminal. For example, a first S/D terminal of one transistor is coupled to a second S/D terminal of another transistor. The first S/D terminal of the first transistor in a path is coupled to V DD  and the second S/D terminal of the last transistor in a path is coupled to V NEG . 
         [0040]    In one embodiment, the first path and second path of the input sub-block, clamp sub-block and pull-down sub-block each includes the same number of transistors coupled in series. The fist path and second path of enable sub-block each includes the same number of transistors or can be with different number of transistors. As shown, the first path, from V DD  to V NEG , includes transistors MN 5 , MP 1 , MP 3 , MN 3  and MN 1  coupled in series. The second path, from V DD  to V NEG , includes transistors MP 5 , MP 2 , MP 4 , MN 4  and MN 2  coupled in series. 
         [0041]    In one embodiment, the second terminals of MN 5  and MP 5  are coupled to first terminals of MP 1  and MP 2 . This common connection form node NM. The second terminal of MP 1  and the first terminal of MP 3  form node NA. The second terminal of MP 2  and the first terminal of MP 4  form node NB. The second terminal of MP 3  and the first terminal of MN 3  form output node NOA. The second terminal of MP 4  and the first terminal of MN 4  form output node NOB. The node NA is coupled to the gate of MN 4  while the node NB is coupled to gate of MN 3 . The node NOA is coupled to the gate of MN 2  while the node NOB is coupled to gate of MN 1 . The second terminal of MN 3  and the first terminal of MN 1  form node NC; the second terminal of MN 4  and the first terminal of MN 2  form node ND. 
         [0042]    An enable reset transistor MN 6  is provided for the control block. The first terminal of the enable reset transistor is coupled to node NM and the second terminal of the enable reset transistor is coupled to the gate of MP 4 . The various transistors of the control block have their body biased. In one embodiment, MN 5  is biased with V SS , the body of MP 5  is biased with V DD , the bodies of MP 1 , MP 2 , MP 3  and MP 4  are biased with the voltage at node NM (V NM ). As for MN 1 , MN 2 , MN 3  and MN 4 , their bodies are biased with V NEG . The body and second terminal of MN 6  are biased with V SS . 
         [0043]    The various transistors are provided for the sub-blocks of the control block. In one embodiment, transistors MN 5  and MP 5  are provided for the enable sub-block  350 . The gate of transistor MN 5  is coupled to V DD  and the gate of transistor MP 5  receives EN. The transistors MP 1  and MP 2  form the input or select sub-block  360 . The gate of transistor MP 1  receives IN and the gate of transistor MP 2  receives INB. The transistors MP 3  and MP 4  form the clamp sub-block  370 . The gates of transistors MP 3  and MP 4  are biased at V SS . The transistors MN 1 , MN 2 , MN 3  and MN 4  form the pull-down sub-block  380  and enable reset transistor MN 6  form the reset sub-block  390 . Output signal CON is coupled to node NOB and output signal CON_B is coupled to node NOA. 
         [0044]    As for the output block, it includes transistors MN 7  and MN 8  coupled in series between V SS  and V NEG . For example, the output block includes first and second n-type transistors coupled in series between V SS  and V NEG . The output signal OUT is generated at OUT terminal disposed between the second terminal of transistor MN 7  and first terminal of transistor MN 8 . The output signal OUT is generated in response to input signals CON and CON_B signals of the output block from the control block. 
         [0045]    As previously discussed, V NM  may be reduced by providing transistor MN 5  with additional voltage drops created by additional series transistors. As shown in  FIG. 4 b   , transistor MN 5  is configured to have first and second series transistors MN 5 A and MN 5 B. This increases the voltage drop from V DD  to 2*V T , i.e., V T  is the threshold voltage of each transistor. Larger voltage drops may be created by providing additional transistors. For example, V NM =V DD −N*V T , where N is the number of series transistors of MN 5 . In one embodiment, V NM +V 1 &lt;V DD . 
         [0046]    Referring back to  FIG. 4 a   , the clamp sub-block is coupled in series with the input sub-block while the pull-down sub-block is disposed in series with the clamp sub-block, which is coupled in series to V NEG . In one embodiment, the clamp sub-block maintains node NA and NB to be above V SS . This reduces reliability issues with the various transistors of the input enable and reset sub-blocks. Between the clamp sub-block and the pull-down sub-block are output signals of the control block, CON_B and CON coupled to nodes NOA and NOB. The two control block output signals, CON and CON_B, are complementary signals. 
         [0047]    In one embodiment, the various transistors of the transmission circuit are all the same V T  type. For example, the transistors of the control block and output block are of the same V T  type. Providing transistors which are the same V T  type facilitates a compact design and minimum mask layer requested, both of which reduce manufacturing costs. 
         [0048]      FIG. 5  shows the timing diagram  500  of the transmission circuit. As shown, V DD  is 5V and V SS  is 0V. As for V NEG , it switches between 0V or −V 1  (e.g., −3V). Other voltage values for V DD  and V NEG  may also be useful. The EN signal and the changeable V NEG  are related. In one embodiment, when V NEG  is equal to −V 1 , EN=V DD  (active); when V NEG  is equal to 0V, EN=0V (inactive). When the EN signal is active and the IN signal is inactive (e.g., 0V), CON is equal to −V 1  and CON_B=0V. This causes the OUT signal to equal to 0V. On the other hand, when the IN signal is active (e.g., V DD ), CON is equal to V NM  and CON_B=−V 1 . This causes the OUT signal to equal to −V 1 . As shown, the voltage difference between V NM  and −V 1  is equal to V DIFF . 
         [0049]    In the case EN signal is inactive and V NEG  is at negative low state 0V, the output block is inactive (OUT=0V). However, when the EN signal is inactive, an active IN signal may be received. An inactive EN may cause the CON signal to be elevated from −V 1  to 0V and the CON_B signal to be elevated from V NM  to V DD . The voltage difference between the CON and CON_B signals is equal to V DIFF . A reset pulse ENR_P is generated when ENB goes active again. The reset pulse resets the control block. For example, the reset pulse resets the internal nodes of the control circuit, such as NM, NA, NB, NOA and NOB, so that CON and CON_B can go to the desired voltage level. In one embodiment, the ENR_P is about 1 ns. Providing pulses of other widths may also be useful. Resetting the CON and CON_B signals to the state prior to an active IN signal when EN signal is inactive enables the circuit to operate as normal. Otherwise, the NM node will be kept at V DD  until the next IN signal transition edge. 
         [0050]    The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.