Abstract:
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present application may relate to co-pending U.S. application Ser. No. 11/097,903, filed Apr. 1, 2005 and U.S. application Ser. No. ______ (Attorney Docket No. 1496.00416/04-2001), filed Jun. 16, 2005, which are each hereby incorporated by reference in their entirety. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to memory systems generally and, more particularly, to a method and/or architecture for implementing a programmable data strobe signal that may be suitable for a DDR memory application.  
       BACKGROUND OF THE INVENTION  
       [0003]     In conventional double data rate (DDR) memories, data and data strobe signals (i.e., DQS) are returned from a memory module during each read cycle. The data strobe signal DQS is a bidirectional signal. Noise or unwanted signal toggling may propagate into a memory controller when the controller is not actively reading data from the memory module. Referring to  FIG. 1 , an example of a circuit  10  illustrating a conventional data strobe architecture for double data rate (DDR) memory is shown. Conventional approaches lack a programmable coarse delay in a first data rate domain.  
         [0004]     It would be desirable to implement a data strobe enable architecture suitable for use in a double data rate (DDR) memory application that provides a programmable coarse delay in a first data rate domain.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.  
         [0006]     The objects, features and advantages of the present invention include implementing a memory architecture that may implement an enable feature for a data strobe signal that may (i) prevent unwanted toggles of a signal from propagating at unwanted times and/or (ii) provide a programmable enable signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:  
         [0008]      FIG. 1  is a detailed diagram illustrating a conventional circuit;  
         [0009]      FIG. 2  is a block diagram of a memory controller;  
         [0010]      FIG. 3  is a block diagram of a preferred embodiment of the present invention;  
         [0011]      FIG. 4  is a more detailed diagram of the circuit of  FIG. 3 ; and  
         [0012]      FIG. 5  is a timing diagram illustrating the assertion and deassertion of the enable signal. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0013]     Referring to  FIG. 2 , a block diagram of a circuit  80  is shown illustrating a context of the present invention. The circuit  80  generally comprises a circuit  82  and a memory  84 . The circuit  82  may be implemented as an application specific integrated circuit (ASIC). The memory  84  may be implemented as a memory circuit, such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM). However, other types of memories may be implemented to meet the design criteria of a particular implementation.  
         [0014]     The circuit  82  generally comprises a control circuit  86  and a buffer circuit  88 . The control circuit  86  generally comprises a hardmacro circuit  87  and a memory controller  60 . In general, the control circuit  86  may be implemented as a mix of soft and hard macro functions configured to implement a memory control function. The memory controller  60  may be implemented as a memory controller, a memory application design, a memory interface design or other type of memory implementation. The memory controller  60  may include a programmable circuit  100 . The programmable circuit  100  may be implemented as a DDR Programmable Gateon circuit. The hardmacro circuit  87  may be part of a data path. The hardmacro circuit  87  may include a number of multiplexers, gates and/or other circuitry. The hardmacro circuit  87  may be connected to the buffer circuit  88 . While a single hardmacro circuit  87  is shown, a number of hardmacro circuits  87  are normally implemented to create a number of data paths from the circuit  82  to the memory  84 . The hardmacro circuit  87  may present and/or receive a number of signals (e.g., DQS_OUT, CLK2X_DQS_OUT and/or DQS_IN) that may be referred to as a DQS path. The control circuit  86  may present a number of signals (e.g., CK_OUT and CKN_OUT) to the buffer circuit  88 . The buffer  88  may be connected between the control circuit  86  and the memory  84 . The hardmacro circuit  87  may present a signal (e.g., DQS_INTN) to the programmable circuit  100 . The programmable circuit  100  may present a signal (e.g., GATEON_INTN) to the hardmacro circuit  87 .  
         [0015]     Referring to  FIG. 3 , a block diagram of the circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  may be implemented as a data strobe enable architecture. The circuit  100  generally comprises a block (or circuit)  102 , a block (or circuit)  104  and a block (or circuit)  106 . The circuit  102  may be implemented as a first stage. The circuit  104  may be implemented as a second stage. The circuit  106  may be implemented as a third stage. The first stage  102  may have an input  110  that may receive a signal (e.g., MC_GATEON) and an input  112  that may receive a signal (e.g., CLK1X). The first stage  102  may also have an input  113  that may receive a select signal (e.g., SEL — 0). The first stage  102  may also have an input  115  that may receive a select signal (e.g., SEL — 1). The signal CLK1X may be implemented as a single speed clock signal. The first stage  102  may have an output  114  that may present a signal (e.g., GATEON — 1X) to an input  116  of the second stage  104 . The second stage  104  may also have an input  118  that may receive a signal (e.g., CLK2X). The signal CLK2X may be implemented as a double speed clock signal. The signal CLK2X may be a multiple (e.g., 2X) of the signal CLK1X. The circuit  104  may have an input  119  that may receive a select signal (e.g., SEL — 2). The second stage  104  may have an output  120  that may present a signal (e.g., GATEON — 2X) to an input  122  of the third stage  106 . The third stage  106  may also have an input  124  that may receive a signal (e.g., DQS_INTN). The third stage  106  may have an input  125  that may receive a signal (e.g., SEL — 3). The third stage  106  may have an output  126  that may present a signal (e.g., GATEON_INTN).  
         [0016]     The memory controller  60  asserts a normally “HIGH” on the data strobe enable signal (e.g., MC_GATEON) when issuing a READ command to a memory module. The signal MC_GATEON is normally generated internally to the memory controller  60 . The signal MC_GATEON is then held HIGH by the first stage  102  for the entire burst of read operations. For example, for a read burst of 8, the signal MC_GATEON will generally be held HIGH for four clock cycles of the signal CLK1X. Three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, ¼, and 1/16 of a 1x clock cycle) may be provided to account for variations within the system  100  (e.g., CAS latency, I/O buffer delays, PCB flight time, cross-point skews of memory clocks, etc.). Other granularities may be implemented to meet the design criteria of a particular implementation. The circuit  100  is normally implemented as a self-timed circuit. The last falling edge of a data strobe signal (e.g., DQS) will turn off a read DQS path.  
         [0017]     The data strobe signal DQS is normally implemented as a bidirectional signal. Noise or unwanted signal toggling may propagate into the memory controller  60  when the controller is not actively reading data from the memory device. To avoid unwanted noise, or false propagating of the signal DQS into the controller, the memory controller  60  should use the signal GATEON_INTN of each hardmacro circuit  87  to gate off the paths. It is generally desirable to gate off the READ DQS path when the memory controller  60  is not reading from the memory circuit  84 .  
         [0018]     Referring to  FIG. 4 , a more detailed diagram of the circuit  100  is shown.  FIG. 4  illustrates an example of a programmable gateon circuit that demonstrates the signal DQS gating during the pre- and post-amble phase of the read cycle. The first stage  102  generally comprises a number of flip-flops  140   a - 140   n,  a multiplexer  142 , a multiplexer  144 , a multiplexer  146  and a flip-flop  148 . Each of the flip-flops  140   a - 140   n  presents a delay to the signal MC_GATEON. Additionally, each of the flip-flops  140   a - 140   n  are normally clocked by the clock signal CLK1X. The multiplexer  144  has a number of inputs labeled  0 - 3  that each receive a corresponding output from the flip-flops  140   a - 140   c.  For example, the input  0  may directly receive the signal MC_GATEON. The input  1  may receive a signal from the flip-flop  140   a,  the input  2  may receive a signal from the flip-flop  140   b  and the input  3  may receive a signal from the flip-flop  140   c.  Similarly, the multiplexer  142  has a number of inputs  0 - 3  that may receive signals from the flip-flops  140   d - 140   n.  For example, the input  0  may receive a signal from the flip-flop  140   d.  The input  1  may receive a signal from the flip-flop  140   e,  the input  2  may receive a signal from the flip-flop  140   f  and the input  3  may receive a signal from the flip-flop  140   n.  The particular number of flip-flops  140   a - 140   n  may be varied to meet the design criteria of a particular implementation. Additionally, the multiplexers  142  and  144  may implement a greater number or a lesser number of inputs  0 - 3  to meet the design criteria of a particular implementation. The select signal SEL — 0 (e.g., the zero and first bits of the multi-bit select signal) generally presents signals to a select input S0 and a select input S1 of the multiplexer  142  and the multiplexer  144 . The select inputs S0 and S1 control which of the inputs  0 - 3  may be presented at the output of the multiplexer  142  and the multiplexer  144 .  
         [0019]     The multiplexer  146  generally has an input  0  that receives a signal from the multiplexer  144  and an input  1  that receives a signal from the multiplexer  142 . The multiplexer  146  has a select signal S0, that may be part of the signal SEL — 1. The flip-flop  148  receives the signal from the multiplexer  146  and presents the signal GATEON — 1X.  
         [0020]     The second stage  104  generally comprises a number of flip-flops  150   a - 150   f,  a gate  152  and a multiplexer  154 . The flip-flops  150   a,    150   b,    150   c,    150   d  are generally clocked by the clock signal CLK2X. The flip-flops  150   e  and  150   f  are generally clocked by the inverse (e.g., 180 degrees out of phase) of the clock signal CLK2X (e.g., −CLK2X). The multiplexer  154  has a number of inputs  0 - 3  that receive signals from different flip-flops  150   c - 150   f.  The select signal SEL — 2 provides the select signals S0 and S1 and allow the multiplexer  154  to present the signal GATEON — 2X.  
         [0021]     The third stage  106  generally comprises a multiplexer  170 , an inverter  172 , a gate  174 , a flip-flop  176 , an inverter  178  and a gate  180 . The multiplexer  170  has a number of inputs  0 - 3  that receive different delayed versions of the signal GATEON — 2X. The signal GATEON — 2X is presented to an input  0  of the multiplexer  170 . The signal GATEON — 2X is also passed through a delay element  190 , which then goes to the input  1  of the multiplexer  170 . Similarly, a delay  192  is presented to an input  2  of the multiplexer  170 . Similarly, a delay  194  is presented to an input  3  of the multiplexer  170 . The select signal SEL — 3 provides the select signal S0 and S1 and allow the multiplexer  170  to present a signal (e.g., DELY_GATEON — 2X) to the gate  180 . The signal DELY_GATEON — 2X may be a delayed version of the signal GATEON — 2X.  
         [0022]     Referring to  FIG. 5 , a timing diagram is shown illustrating the assertion and deassertion of the signal MC_GATEON.  FIG. 5  also shows the clock signal CLK1X, the clock signal CLK2X, a clock signal CK, a system reset signal (e.g., SYSTEM_RESET), a signal CORE_CMD, a signal BUS_CMD, a signal DQ, the signal DQS, the signal MC_GATEON, the signal GATEON_INTN, the select signal SEL — 0, the select signal SEL — 1, the select signal SEL — 2, and the select signal SEL — 3.  
         [0023]     The circuit  100  is normally implemented as a self-timed circuit. The last falling edge of the signal DQS will turn off the read DQS paths. Three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, ¼, and 1/16of a 1x clock cycle) may be provided to account for propagation variations (e.g., CAS latency, I/O buffer delays, PCB flight time, crosspoint skews of CK/CK#, etc.). The coarse delay may be selected by the signal SEL — 0 and the signal SEL — 1. In one example, each delay step may be implemented as one 1x clock cycle. The medium delay may be selected by the signal SEL — 2. Each medium delay step may provide 0.25 of a 1X clock cycle. The fine delay may be selected by the signal SEL — 3. Each fine delay step may provide 0.0625 of a 1X clock cycle. The delay steps of 1, 0.25 and 0.0625 have been described as examples. Each delay step may be modified to meet the design criteria of a particular implementation.  
         [0024]     The following TABLE 1 illustrates example delay settings for different CAS latencies without encountering I/O buffer delays, PCB flight time, crosspoint skews of the differential clock signal CK/CK#, etc.:  
                                                         TABLE 1                                   CAS latency   SEL_1, SEL_0   SEL_2   SEL_3                                        2   001   01   00           2.5   001   11   00           3   010   01   00           4   011   01   00           5   100   01   00                      
 
         [0025]     The CAS latency programming is normally controlled by the signals SEL — 0 and SEL — 1. The following TABLE 2 illustrates delay encoding values of the signals SEL — 0 and SEL — 1:  
                       TABLE 2                       SEL_1, SEL_0   Delays (1× Clock Cycles)   Applied CAS Latency                   000   0   2       001   1   2, 2.5, 3       010   2   2.5, 3, 4       011   3   3, 4, 5       100   4   4, 5       Others   5 or 6 or 7   N/A                  
 
         [0026]     The adjusted delays may be varied from one to two 1x clock cycles over process, voltage and temperature (PVT) conditions. A training sequence may be needed to determine and set the optimal delay settings.  
         [0027]     The following TABLE 3 summarizes the descriptions and connections of the circuit  100 :  
                           TABLE 3                       Signal   Type   Description   Connect To/From                   CLK2X   IN   Twice the frequency of CLK1X   From PLL       CLK1X   IN   1× clock input   From PLL or local 2× clock                   driver       SYSTEM_RESET   IN   Asynchronous, active low   From core logic               reset       GATEON_RST_IN   IN   Used for resetting   From core logic               GATEON_INTN to inactive               state after each training               sequence       MC_GATEON   IN   Level signal to enable the   From core logic               read data path inside the DP               hardmacro       SEL_0, SEL_1   IN   Coarse delay settings for   From core logic               different CAS latency       SEL_2   IN   Medium delay settings for   From core logic               adjusting GATEON_INTN               assertion timing       SEL_3   IN   Fine delay settings for   From core logic               adjusting GATEON_INTN               assertion timing       DQS_INTN   IN   Inverted DQS signal to   From DP hardmac               control the deassertion of               GATEON_INTN signal       GATEON_INTN   OUT   GATEON output control   To DP hardmacro               signal. Inactive state is               0. Will transition to 1               during the preamble of the               read cycle.                  
 
         [0028]     The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation. Additionally, inverters may be added to change the particular polarity of the signals.  
         [0029]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.