Abstract:
The present invention discloses a dual power switch and a voltage regulator using the dual power switch. The dual power switch comprises a PMOS power switch and an NMOS power switch connected in parallel and operating according to corresponding predetermined conditions, respectively.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a dual power switch and a voltage regulator employing the dual power switch. 
     2. Description of Related Art 
     Voltage regulators include linear regulators, buck converters, boost converters, buck-boost converters, inverter converters, fly-back converters, AC-DC converters, and the like. All these regulators must employ one or more power switches. In general, as shown in  FIGS. 1 and 2 , such power switch is either a PMOS transistor (device  10  in  FIG. 1 ) or an NMOS transistor device  20  in  FIG. 2 ). When the power switch  10  or  20  is ON, current flows from the input terminal Vin to the output terminal Vout (depending on the structure of the voltage regulator, the output terminal Vout in the figures does not necessarily correspond to the output terminal of a regulator which supplies power to a load; in the context of this specification, the terminals Vin and Vout represent both sides of the power switch). The operation of the power switch  10  or  20  is controlled by a control circuit  15  or  25 . In some applications, because the NMOS transistor  20  requires a higher gate voltage, a charge pump  23  may be required to pump up the voltage for the control circuit  25 . 
     The above mentioned prior art has the drawback that the resistance of a PMOS power switch in ON state is high, while the power consumption of an NMOS power switch is high. A circuit designer has to choose one between the two, but can not gain both. 
     In view of the foregoing, it is desired to provide a dual power switch. 
     SUMMARY OF THE INVENTION 
     A first objective of the present invention is to provide a dual power switch to overcome the drawback in the prior art. 
     A second objective of the present invention is to provide a voltage regulator. 
     In accordance with the foregoing and other objectives, in one aspect, the present invention discloses a dual power switch comprising a PMOS power switch and an NMOS power switch connected in parallel. The PMOS power switch and the NMOS power switch operate according to corresponding predetermined conditions, respectively. For example, they can operate according to a voltage difference between the two sides of the dual power switch, or a current amount flowing through either power switch. 
     Preferably, the dual power switch further includes a first control circuit and a second control circuit to respectively control the PMOS power switch and the NMOS power switch. The dual power switch may further include a determination circuit to determine whether to enable the first control circuit, the second control circuit, or both. 
     The present invention also provides a voltage regulator employing the above mentioned dual power switch. 
     It is to be understood that both the foregoing general description and the following detailed description are provided as examples, for illustration but not for limiting the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings. 
         FIGS. 1 and 2  are schematic circuit diagrams showing prior art circuits. 
         FIG. 3  is a schematic circuit diagram showing an embodiment of the present invention. 
         FIG. 4  is a circuit diagram showing another embodiment of the present invention. 
         FIG. 5  shows an embodiment of the determination circuit of  FIG. 3 . 
         FIG. 6  shows an embodiment of the determination circuit of  FIG. 4 . 
         FIGS. 7 and 8  show, by way of example, how the dual power switch of the present invention can be applied to a buck converter. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the first embodiment shown in  FIG. 3 , in the present invention, a PMOS power switch  10  and an NMOS power switch  20  are connected in parallel, and one or both of which are selectively chosen to conduct current between the input terminal Vin and the output terminal Vout. The operation of the power switch  10  is controlled by a control circuit  15 , and the operation of the power switch  20  is controlled by a control circuit  25 . Moreover, the circuit further includes a determination circuit  30  to determine whether to enable the control circuit  15 , the control circuit  25 , or both. 
     Depending on the requirement from a circuit designer or by the application of the circuit, the determination circuit  30  can determine whether to send one or both of enable signals  31  and  32  according to various criteria. And, it is not necessary for the determination circuit  30  to provide two enable signals  31  and  32 , controlling the control circuits  15  and  25 . For example, in one embodiment, the control circuit  15  is always active, while the determination circuit  30  only provides one enable signal  32  to control the control circuit  25 . 
     As an example, the determination circuit  30  determines whether to enable the control circuit  15  or control circuit  25  or both according to a voltage difference between the two sides of the dual power switch. As a more specific example, let us assume that the control circuit  15  is always active, that the resistance of the PMOS power switch  10  in ON state is 1 Ω, and that that resistance of the NMOS power switch  20  in ON state is 0.1 Ω. Then, it can be arranged such that the enable signal  32  is issued to enable the control circuit  25  when Vin&gt;Vout+0.1V, and the control circuit  25  is disabled when Vin&lt;Vout+0.001V. 
       FIG. 5  shows an example to embody the determination circuit  30  for the arrangements described in the previous paragraph. In  FIG. 5 , resistors R 1  and R 2  constitute a voltage divider to obtain a dividend voltage from the input terminal Vin, and resistors R 3  and R 4  constitute another voltage divider to obtain a dividend voltage from the output terminal Vout. The dividend voltage obtained from the output terminal Vout, added by a bias voltage of a voltage source  34 , is inputted to the negative input of the comparator  33 ; the dividend voltage obtained from the input terminal Vin is directly inputted to the positive input of the comparator  33 . The comparator  33  generates the enable signal  32  according to the comparison result. The comparator  33  should preferably be a hysteretic comparator because the enable signal  32  is issued and stopped according to different criteria (Vout+0.1V and Vout+0.001V). If the criteria are the same, then the comparator  33  can be a normal comparator. Further, note that the voltage source  34  is shown to represent a voltage difference in a broad sense. The voltage source  34  does not have to be a physical device. For example, if there is an input offset voltage between the two inputs of the comparator  33 , which is equal to the bias voltage of the voltage source  34 , then the voltage source  34  is not required and the same effect is achieved. 
     In the circuit of  FIG. 3 , alternatively, the determination circuit  30  can determine whether to enable the control circuit  15  or control circuit  25  or both according to the current flowing through the two power switches. Referring to  FIG. 4  which shows another embodiment of the present invention, wherein the current flowing through the PMOS power switch  10  is defined as I PMOS  and the current flowing through the NMOS power switch  20  is defined as I NMOS , the determination circuit  30  receives information relating to I PMOS  and I NMOS  and determines whether to issue enable signals according to such information. Again, the determination circuit  30  does not necessarily have to issue two enable signals  31  and  32 ; it can only issue one of them. Assuming that the control circuit  15  is always active, that the resistance of the PMOS power switch  10  in ON state is 1 Ω, and that that resistance of the NMOS power switch  20  in ON state is 0.1 Ω, then it can be arranged such that the enable signal  32  is issued to enable the control circuit  25  when I PMOS &gt;100 mA, and the control circuit  25  is disabled when I NMOS &lt;10 mA. 
       FIG. 6  shows an example to embody the determination circuit  30  for the arrangements described in the previous paragraph. In  FIG. 6 , the determination circuit  30  receives information relating to I PMOS  and I NMOS . The information for example are a ratio of I PMOS  and a ratio of I NMOS  (i.e., K 1 ·I PMOS  and K 2 ·I NMOS ). Such information are converted to voltage signals by resistors R 5  and R 6 , and compared with reference voltages Vref 1  and Vref 2  by comparators  35  and  36 , respectively. The comparison in the comparator  35  determines whether I PMOS  is larger than 100 mA, and the comparison in the comparator  36  determines whether I NMOS  is larger than 10 mA. A logic circuit  38  performs logic operation on the outputs of the comparators  35  and  36 : when I PMOS  is larger than 100 mA, the logic circuit  38  outputs a high level signal; when I PMOS  is not larger than 100 mA and I NMOS  is larger than 10 mA, the logic circuit  38  still outputs a high level signal; only when I PMOS  is not larger than 100 mA and I NMOS  is not larger than 10 mA, the logic circuit  38  outputs a low level signal. The determination circuit  30  generates the enable signal  32  according to the above criteria, and transmits the enable signal  32  to the control circuit  25 . 
     Note that the above details are provided as examples, and anyone skilled in this art can made various modifications based thereon, such as modifying the resistances of the power switches in ON state, the criteria of determination based on the voltage difference or the current amount, etc. The hardware of the determination circuit  30  should certainly be modified accordingly. 
     In comparison with prior art, the present invention has the advantages that the NMOS power switch  20  can be activated during heavy load condition to provide a lower conduction resistance (and more current supply), while the NMOS power switch  20  (and the charge pump, if there is one) can be disabled during light load condition to reduce power consumption. Thus, the circuit gains the benefits of both the PMOS power switch and the NMOS power switch, and a circuit designer can design a circuit more easily. 
       FIGS. 7 and 8  show two examples of how the dual power switch of the present invention can be applied to a buck converter. Under the same spirit, those skilled in this art can apply the dual power switch of the present invention to other kinds of voltage regulators, and the details of such applications are not redundantly repeated here. 
     The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, the present invention is not limited to the application of voltage regulators; it can be applied to any other kind of circuits. As another example, what is shown in the figures to be one unit block can be combined with another circuit unit, or divided into separate circuits or devices (for example, the control circuit  15  and the control circuit  25  can be integrated as one unit). As a further example, two circuits which are shown in the figures to be in direct connection with each other can be indirectly connected with each other, with devices which do not affect the primary function of the overall circuit interposing between them. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.