Abstract:
A method for reducing surface recombination in an area next to a mesa in devices containing active and passive sections. This is obtained by growing, by metalorganic vapor phase epitaxy (MOVPE), a thin epitaxial layer of material with larger bandgap than a waveguide material and preferably smaller surface recombination rate than the waveguide material. This thin layer is preferably non-intentionally doped to avoid creating a surface leakage path, thin enough to allow for carrier to diffuse to and thermalize in the waveguide layer and thick enough to prevent carriers to tunnel through it.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly-assigned U.S. provisional patent application Serial No. 60/402,666, filed Aug. 12,2002, by Patrick Abraham, and entitled “RIDGE WAVEGUIDE DEVICE SURFACE PASSIVATION BY EPITAXIAL REGROWTH,” which application is incorporated by reference herein. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention.  
           [0003]    This invention relates to microelectronic and optoelectronic components, and more particularly, to ridge waveguide device surface passivation by epitaxial regrowth.  
           [0004]    2. Description of the Related Art.  
           [0005]    A ridge waveguide provides lateral control of electrical and optical confinement in active and passive sections of integrated optical devices. The ridge (or mesa) is formed above the active or guiding region, where the active or guiding region is not restricted in the lateral direction. The electrical lateral confinement is achieved by the finite spread of injection current in the active or guiding layer, due to the finite width of the above ridge. The optical lateral confinement is obtained by the waveguiding due to the ridge.  
           [0006]    In the case of a laser or a semiconductor optical amplifier (SOA), the waveguide can be active and electrical carrier injection allows for amplification of the light traveling in the waveguide. In the case of a tuning section with a distributed Bragg reflector, a phase section, a branch of a Mach-Zehnder interferometer, the waveguide can be passive and electrical carrier injection is then intended to produce a refractive index change.  
           [0007]    Precise control of the optical and electrical confinement requires the ridge (or mesa) etch to stop precisely and controllably with respect to the waveguide. FIG. 1 is a perspective view of a typical ridge waveguide structure. For the electrical confinement to be efficient, the mesa structure  1  has to be defined as close as possible to area  2  of the waveguide layer  3  where the carrier needs to be injected. A selective etch stopping on the waveguide  3  material is thus the preferred way of achieving this.  
           [0008]    This proves to work well for ridge lasers where quantum wells (QWs) are located typically 1000 Å or more from the surface in the middle of the waveguide  3 . However, exposing the surface of the waveguide  3  of an active section with a shallow QW or exposing the surface of a passive waveguide in which carriers are injected becomes a problem. This is because the surface recombination properties of the waveguide  3  material may not be adequate for it to be exposed. In the case of a shallow QW under the surface, the energy released by non-radiative carrier recombination at the surface  4  next to the mesa  1  accelerates the aging of the active section. In the case of a passive section, the problem is even more severe because there is no QW in the waveguide layer  3  with high carrier collection efficiency to keep the carrier away from the surface. The effect is then clearly visible on both the injection efficiency and the aging of the passive section.  
           [0009]    [0009]FIG. 2 is a perspective view of a typical ridge waveguide structure with a surface passivation layer defined by selective wet etch. The problem described above can be solved for all active or all passive section devices by introducing a stop etch layer  5  above the waveguide and separated from it by a thin (typically 50 nm) layer  6  whose bandgap is larger than that of the waveguide material  7 . After patterning of the surface to define the mesa and removing the contact layer  8 , a selective wet etch is used to remove the upper cladding layer  9  and stop on the stop etch layer  5 . Another selective wet etch can then be used to remove the stop etch layer  5  outside the mesa and stop on the passivation layer  6 . This layer acts as a barrier and keeps the carriers away from the surface  10 . The accuracy of the etch is preserved and the perturbation on the electrical and optical confinement is minimum.  
           [0010]    In the case of an integrated optical device where both active and passive sections are present, the use of such a solution has never been reported and would be difficult to implement because of the difficulty to preserve the integrity or continuity of an etch stop layer.  
           [0011]    It is common practice to deposit a dielectric layer on the sidewalls and on either side of the ridge of ridge waveguide lasers to prevent short circuits between the metal contacting the top of the ridge and the waveguide material in the field. U.S. Pat. No. 5,640,410, which is incorporated by reference herein, describes such a method. FIG. 3 shows a cross section perpendicular to the ridge of a completed device fabricated using a similar method, where  11  is the substrate,  12  is the highly doped lower cladding layer,  13  is the waveguide layer,  14  is the highly doped semiconductor contact layer of opposite conduction type than the lower cladding layer  12 ,  15  is a dielectric layer  16  is the metal contacting the top of the ridge and  17  is the metal layer contacting the bottom of the substrate. Although such a layer as the dielectric layer  15  is referred to as a passivation layer in U.S. Pat. No. 5,640,410, it does not reduce significantly the carrier recombination at the surface of the exposed waveguide layer  13 , because it does not remove the main cause for the formation of nonradiative recombination traps at the surface of the waveguide layer  13 , namely the fact that the crystal stops at the waveguide upper interface, and it does not prevent the carriers in the waveguide layer to reach them.  
           [0012]    An efficient way to remove the recombination traps at the surface of the waveguide layer is to have the crystalline material extend further than the upper interface of the waveguide layer. It can be done by using a structure where the ridge is buried, e.g., BRS (Buried Ridge Structure) or pn BH (Buried Heterostructure), instead of a ridge waveguide structure. However, this structure is totally different from a ridge waveguide structure and requires the development and use of additional process steps that limit the end-to-end chip yield:  
           [0013]    A buried ridge structure requires etching through the waveguide to form mesas.  
           [0014]    Etch through the waveguide layer can potentially create defects where the waveguide layer intersects the mesa sidewalls. This is especially true with the use of plasma dry etch.  
           [0015]    Defects created where the waveguide layer intersects the mesa sidewalls can propagate further in the waveguide layer and degrade the performance and lifetime of the device.  
           [0016]    A combination of dry and wet etch can be used to limit the risk of defect formation where the waveguide layer intersects the mesa walls. However, the control of etch depth uniformity and undercut uniformity is then degraded by the poor uniformity of the wet etch process over large surfaces without a stop etch layer.  
           [0017]    The mesa height needs to be very uniform over the surface of the wafer for the coverage by the subsequent regrowths and the device performance to be uniform.  
           [0018]    Etching of deep mesas and thick and/or multiple regrowth degrades the morphology of the wafer and greatly contributes to decreasing chip yield.  
           [0019]    Furthermore, a buried hetero-structure or a buried ridge structure may be incompatible with other critical functions such as the modulator due to high capacitance.  
         SUMMARY OF THE INVENTION  
         [0020]    The present invention describes a method for reducing surface recombination in an area next to a mesa in optoelectronic devices, such as tunable lasers, containing active sections and/or passive sections. This is obtained by epitaxially growing, by metalorganic vapor phase epitaxy (MOVPE), a thin epitaxial layer of material with a larger bandgap than a waveguide material in order to reduce carrier surface recombination with the waveguide material in the area.  
           [0021]    The waveguide is comprised of an InGaAsP alloy substantially lattice-matched to InP, and the thin layer is comprised of InP or another InGaAsP alloy substantially lattice-matched to InP and with a higher bandgap than the waveguide.  
           [0022]    The thin epitaxial layer is doped in such a manner as to avoid creating a surface leakage path, and more specifically, is non-intentionally doped to minimize the conductivity of the thin layer.  
           [0023]    The result is an optical semiconductor device, comprising a mesa and an area next to the mesa having a thin epitaxial layer of material with a larger bandgap than a waveguide material and a smaller carrier surface recombination rate than the waveguide material.  
           [0024]    The carrier surface recombination is reduced by the combined effects of:  
           [0025]    Moving the crystal discontinuity—the interface between the semiconductor and air or vacuum or a polycrystalline layer—that is responsible for recombination defects away from the waveguide.  
           [0026]    Preventing carriers from accumulating close to the crystal discontinuity described above by choosing the material of the thin epitaxial layer so that it has a larger band gap than the waveguide.  
           [0027]    Making the thin epitaxial layer thin enough that carriers are likely to be captured by the waveguide layer where their energy is lower and no more surface recombination defects are present.  
           [0028]    Making the thin layer thick enough that carriers in the waveguide can&#39;t tunnel through it to recombine at the surface of the thin epitaxial layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]    Referring now to the drawings in which like reference numbers represent corresponding parts throughout:  
         [0030]    [0030]FIG. 1 is a perspective view of a typical ridge waveguide structure;  
         [0031]    [0031]FIG. 2 is a perspective view of a typical ridge waveguide structure with a surface passivation layer defined by selective wet etch;  
         [0032]    [0032]FIG. 3 is a cross-sectional view of a ridge waveguide laser with a dielectric layer isolating the metal contacting the top of the ridge from the waveguide layer;  
         [0033]    FIGS.  4 A- 4 B are perspective views showing the steps in manufacturing a ridge waveguide device according to an embodiment of the present invention;  
         [0034]    FIGS.  5 A- 5 B and FIGS.  5 C- 5 E are perspective and cross-section views, respectively, showing the steps in manufacturing a ridge waveguide device according to another embodiment of the present invention; and  
         [0035]    [0035]FIG. 6 is a flowchart that illustrates the steps performed in manufacturing the device according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0036]    FIGS.  4 A- 4 B are perspective views showing the steps in manufacturing a ridge waveguide device according to an embodiment of the present invention.  
         [0037]    In FIG. 4A, an optoelectronic device structure, comprising an InGaAsP waveguide  18  grown on a highly doped lower cladding layer  19  itself grown on an InP (100) plane n-type substrate with a mesa  20  to form a ridge waveguide, is shown after a ridge wet etch, using a HCl-water solution and stopping selectively on the InGaAsP waveguide layer  18 , has been performed. The ridge main axis is oriented parallel to the [011] crystallographic direction. The InGaAsP contact layer  21  on top of the mesa  20  is still covered with the dielectric layer  22  used as a mask during the etch of the mesa  20 . The interface  23  between an active section and a passive section where the thickness of the waveguide layer  18  changes is shown.  
         [0038]    As shown in FIG. 4B, the dielectric stripe mask  22  formed by the dielectric film constituting the upper layer of the mesa structure is directly used as a selective growth mask and an approximately 60 nm thick non-intentionally doped InP layer  24  is epitaxially grown by MOVPE to cover surfaces where the waveguide material was previously exposed, including at the active-passive interface  23 . It is also possible to use relatively light doping in layer  24 , provided only that a significant shunt current will not flow in it and that the desired heterobarrier is formed with waveguide layer  18 . The (n−11)A type crystallographic planes  25  and  26  form at the bottom of the ridge and next to the InGaAsP contact layer  21 , respectively. The growth rate on (n−11) A type planes is considerably smaller than on a (100) plane. This produces the thickness of layer  24  in the corner at the foot of the ridge to be weakly dependent on the thickness of the InP layer grown in the field next to the ridge. This makes it possible to minimize and stabilize the effect of the InP layer  24  on the optical mode confinement in the waveguide. After the growth of layer  24 , the process can then proceed with removing the dielectric layer on top of the mesa.  
         [0039]    FIGS.  5 A- 5 B and FIGS. SC-SE are perspective and cross-section views, respectively, showing a method in passivating the surface of the waveguide in a multi-section device according to another embodiment of the present invention. In this case, the last epitaxial growth before performing the ridge etch finishes with an approximately 30 nm thick Inp layer  27  on top of the InGaAsP contact layer  21 .  
         [0040]    In FIG. 5A, an optoelectronic device structure, comprising an InGaAsP waveguide  18  grown on a highly doped lower cladding layer  19  itself grown on an InP (100) plane n-type substrate with a mesa  20  to form a ridge waveguide, is shown immediately after the dielectric layer (used as a mask to perform the ridge wet etch stopping selectively on the InGaAsP waveguide layer  18 ) has been removed. The approximately 30 nm thick InP layer  27  is exposed on top of the mesa  20 . The ridge wet-etch is performed using a HCl-water solution and stopping selectively on the InGaAsP waveguide layer  18 . Other selective etches that are well-known to those skilled in the art may also be used. The ridge main axis is oriented parallel to the [011] crystallographic direction. The interface  23  between an active and a passive section where the thickness of the waveguide layer  18  changes is shown.  
         [0041]    As shown in FIG. SB, an approximately 60 nm thick non-intentionally doped InP layer  28  is grown by MOVPE to cover all the surfaces including where the waveguide material was previously exposed and the active-passive interface  23 . As in the previous example, a light doping may be incorporated, and (n−11)A type crystallographic planes  25  and  26  form at the bottom of the ridge and next to the InGaAsP contact layer  21 , respectively. For the same reason, the slow growth rate on (n−11)A type planes makes it possible to minimize and stabilize the effect of the InP layer  28  on the optical mode confinement in the waveguide.  
         [0042]    FIGS.  5 C- 5 E show a method for removing the InP layer  28  on top of the InGaAsP contact layer using a selective etch. In this method, an epitaxial semiconductor film is selectively removed, rather than a dielectric film with much different interface chemistry. Thus, the method results in a much lower damage contact surface for improved contact resistance.  
         [0043]    [0043]FIG. 5C shows a cross-section along plane A outlined in FIG. 5B after a dielectric layer  29  and a thick photo-resist layer  30  have been deposited on the surface covering the field and the ridge and have been etched to open the top of the mesa  31  and expose the InP layer  28 . FIG. SD shows the same structure after a selective InP etch has been performed with an HCl-water solution to remove the InP layer covering the InGaAsP contact layer  21 . Other selective etches that are well-known to those skilled in the art may also be used. The etch stops on the InGaAsP contact layer  21 , but produces trenches  32  to be etched between the InP mesa  20  and the dielectric layer  29 . FIG. 5E shows a cross-section of the same structure after the dielectric has been selectively etched using a buffered solution of HF to suppress the trenches  32 . The process can then proceed by removing the thick photo-resist  30  and depositing the top metal contact on the InGaAsP contact layer  21  and the isolation dielectric  29 .  
         [0044]    [0044]FIG. 6 is a flowchart that illustrates the steps performed in manufacturing the device according to the preferred embodiment of the present invention.  
         [0045]    Block  33  represents a wafer with active and passive areas defined thereon.  
         [0046]    Block  34  represents a dielectric and photoresist deposition on the wafer.  
         [0047]    Block  35  represents a photoresist exposure with a mesa/ridge mask.  
         [0048]    Block  36  represents a photoresist development, leaving the resist only on the mesa/ridge.  
         [0049]    Block  37  represents a dielectric etch off, where it is exposed at the surface.  
         [0050]    Block  38  represents a mesa/ridge selective etch, stopping on the waveguide layer.  
         [0051]    Block  39  is a decision block that determines whether a first or second embodiment of the method is used. If the first embodiment is used, then control transfers to Blocks  40  and  41 ; otherwise, if the second embodiment is used, then control transfers to Blocks  42  and  43 . Thereafter, control transfers to Block  44  in both the first and second embodiments.  
         [0052]    In the first embodiment, Block  40  represents an epitaxial regrowth of passivation material and Block  41  represents the removal of the dielectric mask.  
         [0053]    In the second embodiment, Block  42  represents the removal of dielectric mask and Block  43  represents an epitaxial regrowth of passivation material.  
         [0054]    Block  44  represents the deposition of an isolation dielectric and photoresist.  
         [0055]    Block  45  represents a photoresist and dielectric etch (for a via opening).  
         [0056]    Block  46  is a decision block that determines whether a first or second embodiment of the method is used. If the first embodiment is used, then control transfers to Blocks  47 ,  48  and  49 ; otherwise, if the second embodiment is used, then control transfers to Blocks  50 ,  51 ,  47 ,  48  and  49 .  
         [0057]    In the first embodiment, Block  47  represents the photoresist removal, Block  48  represents a photoresist deposition, exposure with a metal mask and development to define the metal area, and Block  49  represents a metal deposition.  
         [0058]    In the second embodiment, Block  50  represents an InP selective etch to uncover the contact layer, Block  51  represents a dielectric etch to suppress trenches along the mesa top, Block  47  represents a photoresist removal, Block  48  represents a photoresist deposition, exposure with a metal mask and development to define the metal area, and Block  49  represents metal deposition.  
       CONCLUSION  
       [0059]    This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.