Abstract:
In a three-phase DC-to-AC inverter including, for driving each leg of the load, a controlled power driver such a pulse-width modulated field-effect transistor (FET) or insulated gate bipolar transistor (IGBT) pair, an estimator for estimating the current in each leg of the load. A low-resistance leg resistor is connected in series in the lower leg of each transistor pair. The voltages across the leg resistors are applied to two differential amplifiers to generate two discrete voltage difference values that are transmitted to an estimator. The estimator solves specified differential equations using suitably interconnected combiners, integrators, amplifiers and multipliers, or discrete digital equivalent or programmed computer equivalent, to derive a value for the estimated current in each leg of the load.

Description:
This application relates to current sensors and estimators for use with inverters such as pulse-width modulated field-effect transistors for driving a three-phase load, and in particular to an estimator for estimating the current flowing in each of the three legs of a three-phase load. 
     BACKGROUND OF THE INVENTION 
     It is conventional to use Hall-effect devices to measure the current in each of the legs of a three-phase load supplied by a pulse-width modulated inverter. Such inverters typically use three pairs of field-effect transistors (FETs) or equivalent to supply the three-phase load (which may be, for example, a three-phase AC motor). Hall-effect devices are large and expensive. It is an object of this invention to replace such devices with a small and economical solid-state circuit that makes use of sensing resistors in the return legs of the inverter circuit in combination with an estimator for receiving certain signals representing selected parameters and computing an estimated current value for each leg. 
     It is known to introduce a resistor into one or more of the return legs of the FETs of an inverter. See, for example, U.S. Pat. No. 5,825,641 issued to Mangtani on Oct. 20, 1998. However, Mangtani does not provide any provision to utilize the voltages developed across the sensing resistors to generate an estimate of the respective currents flowing in the legs of the load. 
     Voltages across sensing resistors have also been used to control brushless motors; see for example U.S. Pat. No. 5,469,033 issued to Huang on Nov. 21, 1995. However, Huang makes no provision for producing a signal representative of the current flowing in each leg of the load. 
     SUMMARY OF THE INVENTION 
     For measuring leg current in each leg of a three-phase load powered by an inverter including an FET arrangement of the type described above, or equivalent, the present invention replaces the conventional Hall-effect device with simple sensing resistors, one in each return leg A, B, and C of each field-effect transistor (FET) pair of the inverter. By comparing and processing the voltages produced across the sensing resistors, estimated values of the current in each leg of the load are obtained. The sensing resistors should be of low resistance so as not to generate unacceptable power losses. 
     If the voltages produced by these leg resistors in the three return legs of the FETs are expressed as V a , V b  and V c  respectively, and if the voltages V a  and V c  are applied to the input terminals of a first differential amplifier, and if the voltages V b  and V c  are applied to the input terminals of a second differential amplifier, the output voltages of these differential amplifiers will be respectively of the form 
     
       
         D vac =K(V a −V c )/(TS+1) 
       
     
     and 
     
       
         D vbc =K(V b −V c )/(TS+1) 
       
     
     Where 
     D vac  is the differential voltage output of the first differential amplifier, whose input terminals are connected across legs A and C of the circuit (in each case between the associated sensing resistor of the respective leg and the FET connected to the sensing resistor); 
     D vbc  is the differential voltage output of the second differential amplifier, whose input terminals are connected across legs B and C of the circuit (in each case between the associated sensing resistor of the respective leg and the FET connected to the sensing resistor); 
     K is the gain of the differential amplifier; and 
     1/(TS+1) is a dimensionless value representing the filter bandwidth in the differential amplifier. The value T is an intrinsic value representing the resistance-capacitance time constant of the differential amplifier, and S is the Laplace operator. 
     The continuous output analog differential voltage signals produced by the two differential amplifiers may conveniently be converted to digital signals that are processed in a microprocessor to produce estimated values of the current in each leg of the load. These estimated current values may in turn be displayed for the benefit of the operator of the three-phase load being driven by the inverter, or may be used to drive a suitable feedback loop or circuit, or otherwise. The particular use to which the estimated load leg current values are put is not per se part of the present invention. 
     More specifically, the three-phase DC-to-AC inverter for which the present invention is suitable conventionally includes three pairs of FETs that are pulse-width modulated. Insulated gate bipolar transistors (IGBTs) may be substituted for the FETs; this specification should be read with this possibility in mind. Alternative equivalent inverter circuits may be devised. For the purpose of this specification, the AC power drivers such as FETs in such circuits are referred to as controlled power drivers, and in the case of FETs, the control is supplied by means of an individual pulse-width modulated gate control signal applied to each FET. 
     According to the invention, the current is estimated in each leg of the load by providing first, second and third resistors respectively in the return legs of associated pairs of FETs to derive a load current-sensitive voltage across each resistor. These voltages are applied as follows to a pair of differential amplifiers: The voltage appearing at the junction of the return leg A of the first pair of FETs and the associated first resistor is applied to a first input terminal of the first differential amplifier, and the voltage appearing at the junction of the return leg C of the third pair of FETs and the associated third resistor is applied to a second input terminal of the first differential amplifier. The voltage appearing at the junction of the return leg B of the second pair of FETs and the associated second resistor is applied to a first input terminal of the second differential amplifier, and the voltage appearing at the junction of the return leg C of the third pair of FETs and the associated third resistor is applied to a second input terminal of the second differential amplifier. (Note that in this specification, the designations “first”, “second”, “third”, and legs “A”, “B”, and “C”, and related identifying symbols, are arbitrary.) The two differential amplifiers receiving these input voltages generate the output differential voltages D vac  and D vbc  respectively. 
     A leg current estimator, preferably including a suitable signal processing circuit within a microcontroller, is provided to process the output signals D vac  and D vbc  obtained from the                   I   aE            t       =     z        [       D   Vac     -         I   aE     M          (     M   -   α     )       +         I   cE     M          (     M   -   γ     )         ]         ;                          
     differential amplifiers to solve the equations:                   I   bE            t       =     z        [       D   Vbc     -     D   Vac     +         I   aE     M          (     M   -   α     )       -         I   bE     M          (     M   -   β     )         ]         ;         and                    I   cE            t       =     z        [       -     D   Vbc       +         I   bE     M          (     M   -   β     )       -         I   cE     M          (     M   -   γ     )         ]         ;                          
     where 
     I aE  is the estimated current in leg A; 
     I bE  is the estimated current in leg B; 
     I cE  is the estimated current in leg C; 
     t is time; 
     z is the dimensionless bandwidth of the processing circuitry (which may be set by the operator and may arbitrarily take the value of 10,000 in the absence of any good reason for choosing a different value; normally the value of z is selected to ensure that analysis occurs within the range of linear performance of the load; for higher load frequencies, the value of z should be higher, for lower load frequencies, the value of z may be lower); M is the half-period of the pulse width modulating signal (i.e., M may be expressed as ½f, where f is the pulse-width modulating signal carrier frequency); and the values α, β and γ are derived as follows: 
     
       
         α=V L  sin(ωt−φ) 
       
     
      β=V L  sin(ωt−φ−2π/3) 
     
       
         γ=V L  sin(ωt−φ−4π/3) 
       
     
     where V L  is the amplitude, ωis the load voltage frequency, and φis the phase angle of the load voltage. These three values α, β and γ are set by the operator in the microcontroller depending upon the three-phase power application required. Note that the values α, β and γ are proportional to the instantaneous load leg voltages in legs A, B, C respectively. 
     Solving the differential equations listed above using the microprocessor or other suitable estimator enables the microprocessor to calculate values representative of load leg currents. As discussed, these values may be displayed, used to control or set feedback values for AC power driver circuit control, or otherwise used by the operator to advantage. However, the use of such values representative of the estimated current in each leg of the load is not a part of the present invention. 
     An embodiment of the invention including an estimator using discrete devices will be described in this specification. Depending upon the means used to derive and process data representing the voltage differences D vac  and D vbc , the discrete devices may be analog or digital or some suitable combination of the two. Further, to the extent that discrete digital devices may be employed, a general-purpose or special-purpose digital computer or microprocessor could be used in substitution for discrete devices, with the requisite operations optionally performed by suitable programming. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of an inverter coupled with a block diagram of load leg current sensing and computation apparatus, incorporating an embodiment of the present invention. 
     FIG. 2 is a diagrammatic signal-processing flowchart of a suitable signal processor. 
     FIG. 3 is a graphic representation of the waveform used to drive one exemplary pair of the FETs of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Considering first FIG. 1, within box  50  are components and signals presented in flowchart format for simplicity of description; outside the box  50  the circuit diagram is conventional, all connections required for circuit completion being illustrated in that part of the diagram lying outside box  50 . 
     A three-phase load, such as exemplary three-phase AC motor  10 , is supplied from a pulse-width modulated inverter powered by a DC source providing input voltage V dc  via DC terminals  57 ,  58  across a smoothing capacitor C 1 . The inverter comprises six FETs in three pairs: F 1 , F 2  (for leg A of the load), F 3 , F 4  (for leg B of the load), and F 5 , F 6  (for leg C of the load). The emitters and collectors of each FET pair are connected in series across the DC supply, and each leg of the load is connected to an associated junction point between the associated transistor pair. The emitters and collectors of these FETs are respectively connected in parallel with diodes Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  so as to maintain continuity of output current. Note that such diodes are standard for use with FETs and are normally physically incorporated into the FETs themselves. The FETs are respectively gated by gates  11 ,  12 ,  13 ,  14 ,  15  and  16  to which the appropriate pulse-width modulated control signals  51 ,  52 ,  53 ,  54 ,  55 ,  56  respectively, are applied in dependence upon the type of load and the calculated leg current, the latter being estimated as discussed generally above and as discussed further below. 
     A microcontroller  17  including a microprocessor is provided that receives as inputs the converted differential voltage signal outputs of differential amplifiers  21  and  22  whose analog outputs are respectively converted by analog/digital converters  61  and  62  to digital signals suitable for processing by the microcontroller  17 . Although illustrated as separate components in FIG. 1, analog/digital converters  61 ,  62  may be incorporated into the microcontroller  17 , and may be omitted entirely if followed by discrete analog devices (the latter being an alternate embodiment of the estimator of FIG. 2, to be described below). The microcontroller  17  performs suitable computations on these digitised differential voltage signals in order to estimate the leg current in each leg. On a continual basis, the microcontroller  17  provides suitable output pulse-width modulated drive signals  51 ,  52 ,  53 ,  54 ,  55 ,  56  to the gates  11 ,  12 ,  13 ,  14 ,  15  and  16  respectively of the FETs F 1 , F 2 , F 3 , F 4 , F 5 , F 6  respectively, so that the FETs provide appropriate current to the respective leg of the load. 
     Typical of the output gate drive signals produced by the microprocessor  17  are the waveform pair Pa, Na for leg A as shown in FIG.  3 . These two waveforms represent the control pulse-width modulated switching signals  51 ,  52  applied to gates  11  and  12  of FETs F 1 , F 2  respectively, the wave form designated Pa being representative of the drive signal  51  applied to gate  11  and illustrating pulse width components M and α, and the wave form Na being representative of the drive signal  52  applied to gate  12 . Note that wave form Na is the mirror image of the wave form Pa; in other words, the two wave forms at any point in time are of equal value but opposite polarity. A similar description applies to production of pulse-width modulated switching signals  53 ,  54  for leg B (in response to pulse width components M and β), and pulse-width modulated switching signals  55 ,  56  for leg C (in response to pulse width components M and γ). Such drive signals and the circuits for producing them are well known and will not be described further in this specification. 
     In the lower legs of the inverter circuit are load current sensing resistors  18 ,  19  and  20  for each of the legs A, B and C respectively. These resistors  18 ,  19  and  20  should have sufficient resistance that reliable differential voltages are applied to differential amplifiers  21  and  22  within a preferred input voltage range for these differential amplifiers, but as the resistors dissipate power otherwise available for the load  10 , the resistance of each of the resistors should be as low as practicable. Depending upon the particular application, representative resistance values for the resistors  18 ,  19  and  20  can be, for example, in the 0.05 Ω range. 
     The voltages developed across the resistors  18 ,  19  and  20 , designated V a , V b  and V c  respectively, constitute input voltages to the differential amplifiers  21  and  22 . Voltages V a  and V c  are respectively applied to the two input terminals of differential amplifier  21 , and voltages V b  and V c  are applied to the input terminals of differential amplifier  22 . 
     The differential amplifiers  21  and  22  have a gain K and a frequency response represented by the dimensionless value 1/(TS+1), T being the inherent RC time constant of the differential amplifier, and S the Laplace operator, as previously mentioned, so that the output D vac  of differential amplifier  21  is 
     
       
         K(V a −V c )/(TS+1) 
       
     
     and the output D vbc  of differential amplifier  22  is 
     
       
         K(V b −V c )/(TS+1) 
       
     
     The respective converted or unconverted outputs of differential amplifiers  21  and  22  are applied to a suitable estimator. The estimator may be a general-purpose or special-purpose digital computer or microprocessor, or may be composed of discrete components, either analog or digital in character. As the signals representing voltages obtainable across the resistors  18 ,  19  and  20  are real-time signals, and consequently the output signals obtainable from the differential amplifiers  21  and  22  may conveniently be analog in character, an analog estimator circuit could directly follow the differential amplifiers  21  and  22  without requiring conversion of their outputs to digital signals. Alternatively, the estimator circuit could be a digital circuit that either could be built from discrete digital components, or could be an integral part of a computer or processor, in which cases analog-to-digital converters  61  and  62  would be provided to convert the analog output signals of the differential amplifiers to digital format. As a further alternative, the differential amplifiers  21  and  22  could be replaced by digital devices after conversion of the voltage signals obtained across resistors  18 ,  19  and  20  to digital format. Various discrete digital devices could, of course, be replaced by functional operations of the computer or microprocessor, if used, operating in response to a suitable computer program. 
     For convenience and as an aid to understanding, a discrete-device alternative is illustrated in FIG.  2 . The discrete devices illustrated may be analog or digital in character; if analog, the analog-to-digital converters  61  and  62  would be omitted. However, the entire signal processor of FIG. 2 could instead form a portion of the microcontroller  17  or of a separate microprocessor, or the operations required of the estimator arrangement of FIG. 2 could be performed by a general-purpose digital computer. Note that operations performed on analog signals will tend to produce smooth signal outputs, whereas if digital operations are performed, a given signal waveform is approximated by a step-wise series of values. This is inherent in digital operations, and is of no adverse consequence as long as the digital signal sampling rate is high enough to meet the practicalities of the requirement for which estimated leg load current is being estimated. 
     The signal processor of FIG. 2 produces three outputs at terminals  23 ,  24  and  25  representative of the estimated currents in each leg of the load; specifically: 
     the signal at terminal  23  is representative of the estimated current I aE  in leg A; 
     the signal at terminal  24  is representative of the estimated current I bE  in leg B; and 
     the signal at terminal  25  is representative of the estimated current I cE  in leg C. 
     More particularly, as will be seen in FIG. 2, the output D vac  of differential amplifier  21  is applied after analog-to-digital conversion to terminal  26 , and the output D vbc  of differential amplifier  22  is applied after analog-to-digital conversion to terminal  27 . These signals at terminals  26  and  27  are supplied to an intermediate combiner (summation device)  28  that produces an output (D vbc −D vac ) and the signals at terminals  26  and  27  are also applied as shown to combiners  29  and  31 . In FIG. 2, the polarity signs “+” and “−” at the input terminals of each combiner indicate whether addition or subtraction is to be performed within the combiner. The output of combiner  28  is applied as an input to combiner  30 , which also accepts a second input from amplifier  45 , as discussed further below. The outputs of combiners  29 ,  30  and  31  are each applied to integrators  32 ,  33  and  34  each of which processes its associated input signal value u A , u B , or u C  (each value is generically referred to simply as “u”) to produce an output signal value        y   =       1   s                   u                            
     where s is the Laplace operator, and y is therefore the integral of u, expressed as ∫u. Of course, the value y and the value u for any one of the integrators  32 ,  33 ,  34  will not be the same as for any of the other of these integrators, except coincidentally. 
     The outputs of the integrators  32 ,  33  and  34  are applied to amplifiers  35 ,  36  and  37  respectively, each of which has a gain z. Therefore, using the same notation, the output of amplifier  35  is zy 1 , and similarly the output of amplifier  36  is zy 2 , and the output of amplifier  37  is zy 3 , where Y 1 , Y 2 , and y 3  are the outputs of integrators  32 ,  33  and  34  respectively. These outputs are applied to multipliers  38 ,  39  and  40  that multiply together the values of the two input signals applied to each. Also applied to these multipliers as a second input to each are signals provided at terminals  47 ,  48  and  49  of the form 
     
       
         (M−α)/M, (M−β)/M, and (M−γ)/M 
       
     
     respectively, where M is the half-period of the pulse-width modulation carrier signal; and the values α, β and γ are derived as follows: 
     
       
         α=V L  sin(ωt−Φ) 
       
     
     
       
         β=V L  sin(ωt−Φ−2π/3) 
       
     
     
       
         γ=V L  sin(ωt−Φ− 4π/3)   
       
     
     where V L  is the amplitude, ω is the load voltage frequency, and Φ is the phase angle of the load voltage frequency, all of which values are set by the microcontroller. 
     The output I aE  (M−α)/M of multiplier  38  is applied to combiners  41  and  42 . The output I bE  (M−β)/M of multiplier  39  is applied to combiners  42  and  43 . The output I cE  (M−γ)/M of multiplier  40  is applied to combiners  43  and  41 . The output of combiner  41  is applied through amplifier  44  to combiner  29 . The output of combiner  42  is applied through amplifier  45  to combiner  30 . The output of combiner  43  is applied through amplifier  46  to combiner  31 . The gain of each of amplifiers  44 ,  45  and  46  is normally  1 , but the gain can be adjusted to compensate for disparities between the actual leg currents and the estimated leg current values generated by the apparatus of FIG.  2 . These amplifiers  44 ,  45  and  46  may be used to increase current output or, if serving no other useful purpose, may be omitted from the circuit, in which latter case the outputs of combiners  41 ,  42  and  43  would be applied as direct inputs to combiners  29 ,  30  and  31  respectively. 
     Note that for each estimated leg current value appearing at output terminals  23 ,  24 ,  25 , there is an output circuit comprising a combiner followed by an integrator followed by an amplifier, each of which output circuits includes as one of its inputs a signal derived from one or both differential amplifiers, and as the other of its inputs a combined signal comprising the difference between the signal fed back from an associated multiplier and a second signal obtained from the multiplier associated with another feedback loop. For example, the output circuit for the leg A current estimate comprises combiner  29 , integrator  32  and amplifier  35 . A feedback loop for this output circuit comprises multiplier  38 , combiner  41 , and optional amplifier  44 . The combiner  41  accepts as its inputs the output of associated multiplier  38  and the output of multiplier  40 , and produces a difference signal that is fed back as one of the two inputs to combiner  29 . In the case of this leg A processing subcircuit, the other input to combiner  29  is derived directly from the digital output obtained from the differential amplifier  21 , and a similar situation exists for the leg C processing subcircuit; in this latter instance, the leg C output combiner  31  receives as one of its inputs the digital output of differential amplifier  22 . However, for the leg B processing subcircuit, the signals from the two differential amplifiers are subtracted from one another in the intermediate combiner  28 , whose output constitutes one of the inputs to the leg B output combiner  30 . In other respects the leg current estimator subcircuits for the three legs of the load are essentially similar, although it is noted that combiner  31  provides the negative sum of its two inputs, whereas the other two output combiners  29 ,  30  provide output signals representing the difference between the two input signals to each. Note that each of the three feedback loops for the three leg current estimator subcircuits accepts a unique combination of inputs. 
     The result of the signal processing of FIG. 2 is that the signals that appear at terminals  23 ,  24  and  25  are representative of the estimated values of the currents in the three legs of the load; to repeat, these estimated currents are the following: I aE  is the estimated current in leg A; I bE  is the estimated current in leg B; and I cE  is the estimated current in leg C. In other words, the circuit of FIG. 2 has solved the differential equations listed above. (In this specification, “solution” of a differential equation or other equation, or performance of any other computation, means solution or performance within engineering tolerances, depending upon the end use of the estimated leg current data derived). Note that the estimated current values may differ somewhat from the actual load leg current values. For steady-state current, the relationship between the estimated leg currents and the actual leg currents for the respective legs is expected to be linear, and if necessary the estimated value for each leg current may be adjusted by adjusting the gain of amplifiers  44 ,  45 ,  46  empirically. Or a correction factor could be applied by the microcontroller  17  to the output signals at terminals  23 ,  24 ,  25 . Note also that if the leg current is not steady-state but subject to change, the dynamic response of the estimator circuitry of FIG. 2 in response to such change will result in instantaneous estimated leg current values that track actual leg current values, but may not faithfully reflect the higher-frequency changes in actual current value if the effective estimator circuit bandwidth is too low. The fidelity of the tracking will depend upon the choice of the value “z” in the differential equations previously set forth. 
     While the FETs are pulse modulated, the outputs D vac  and D vbc  from differential amplifiers  21  and  22  are substantially continuous signals, that is, their waveform is not a pulse form. and when applied after analog-to-digital conversion to the input terminals  26  and  27  of the estimator, these outputs are processed in accordance with the operations described above to solve the differential equations listed above, repeated here for convenience:                   I   aE            t       =     z        [       D   Vac     -         I   aE     M          (     M   -   α     )       +         I   cE     M          (     M   -   γ     )         ]         ;                    I   bE            t       =     z   [         D   Vbc     -     D   Vac     +         I   aE     M          (     M   -   α     )       -         I   bE     M          (     M   -   β     )         ;                              
     and 
     where all parameters have the definitions previously given.                 I   cE            t       =     z        [       -     D   Vbc       +         I   bE     M          (     M   -   β     )       -         I   cE     M          (     M   -   γ     )         ]                              
     Once the estimated load leg currents have been derived, they may be put to use in various ways. The diagram of FIG. 1 illustrates two possible uses of the estimated load leg current calculated values. In one instance, the microcontroller  17  uses the estimated load leg current values to provide drive signals  64  to a monitor  63  that displays, in any suitable and conventional fashion, the estimated load leg current values. The operator of the motor  10  or other equipment may, in response to such displayed information, take steps to modify the operation or control of the motor  10  or other three-phase AC load whose load current is being monitored. 
     In another possible application, the microcontroller  17  provides feedback control signals  66  representative of the estimated load currents in each of the three legs of the load to a feedback control loop or circuit  65 . Many possible types of feedback control exist; for example, in the event that estimated load current in any given leg of the load were perceived to be too high (above some threshold value) a circuit breaker could open or an impedance could be added to the load to reduce the current, or some other suitable action could be taken to avoid burn-out of the motor  10  or other AC load being controlled. The control signals to be supplied by the feedback control loop  65  could therefore be applied in many different ways—in a fairly direct manner to the load itself or circuitry coupled to the load, to auxiliary or peripheral equipment associated with the load, to the drivers of the FETs or IGBTs, or the feedback control signals could be fed back to the microcontroller  17  to adjust some of the parameters governing the operation of the microcontroller  17 . For example, the values α, β and γ could be adjusted by the feedback control loop  65  in response to the values of the calculated estimated load leg current. Note that the feedback control loop  65 , while shown as a discrete external circuit, could itself be incorporated into the microcontroller  17 . Note also that the diagram of FIG. 1 does not illustrate any digital/analog conversion for converting digital values reflective of estimated load currents into analog control signals; such may be provided in conventional fashion as required. 
     The circuit of FIG. 1 shows two possible exemplary feedback output signal sets. A first signal set  67  comprises a feedback of suitable feedback control signals into the microcontroller  17  to control some aspect of the operation of the microcontroller  17 , or some setting of input parameter values for the microcontroller  17 . If the feedback is to be used to control some aspect of the operation or set values of the microcontroller  17 , then it would make good design sense to incorporate the feedback control loop  65  within the microcontroller  17 , in which case, the feedback control loop  65  might not be a discrete electronic device, but might simply be part of the internal circuitry of the microcontroller  17 , or incorporated into the programming for the microcontroller  17 . 
     Alternatively, the feedback control circuit  65  could provide gate drive signals  71 ,  72 ,  73 ,  74 ,  75  and  76  to FETs F 1 , F 2 , F 3 , F 4 , F 5  and F 6  respectively. In such a case, these drive signals would replace the drive signals  51 ,  52 ,  53 ,  54 ,  55  and  56  previously discussed. These illustrated feedback arrangements are exemplary only and not exhaustive of the possibilities. 
     Note that the particular use of the calculated estimated load leg current values through display in a monitor, feedback as discussed above or otherwise, etc., is not per se part of the present invention. The present invention is concerned only with the means of deriving the estimated load leg current values. The circuit designer may decide how best to use these estimated load current values for display, feedback or other purposes; such display, feedback or other purposes and the designs implementing such other purposes are not part of the present invention. 
     Variants of the inventive apparatus will readily occur to those skilled in the art. For example, it is within the preference of the designer to select either analog or digital devices to perform various of the requisite computation functions and operations. Further, to the extent operations are made on digital data, the operations may be programmed operations within a general-purpose or special-purpose computer or microprocessor. The invention as claimed should be understood to include such variants, as it is within the ordinary skill in the design of such apparatus to make substitutions of the foregoing type. The invention is not limited to the specific preferred embodiment illustrated and described above, but is to be accorded the full scope set forth in the appended claims.