Abstract:
A variable-gain amplifier (VGA), with one or more amplifier stages, has two or more offset correction sources connected to apply offset correction signals at different locations in the VGA. In one embodiment, each amplifier stage has both an input offset correction source and an output offset correction source. In another embodiment, each amplifier stage of a multi-stage VGA has an input offset correction source. By sequentially calibrating each amplifier stage, starting with the initial stage and proceeding downstream, the entire VGA can be calibrated to achieve gain-independent compensation for the adverse affects of input and output voltage offsets at the input and output, respectively, of each stage.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to electrical circuits, and, in particular, to variable-gain amplifiers.  
         [0003]     2. Description of the Related Art  
         [0004]     Variable-gain amplifiers (VGAs) are often implemented using multiple amplifier stages connected in series, where each successive amplifier stage further amplifies the output from the previous amplifier stage. As indicated by its name, a VGA can be operated over a range of different gain settings, where each amplifier stage contributes, e.g., proportionately, to the overall amplifier gain.  
         [0005]     In such a multi-stage VGA, deviations from ideal operations can result from voltage offsets that can occur at both the input and the output of each amplifier stage, where the input and output offset levels can be independent from each other and also independent from the offsets at different stages. These offsets can result from process variations during fabrication/manufacturing as well as from changes in operating conditions such as age, temperature, humidity, and the like.  
         [0006]     One conventional technique for compensating multi-stage VGAs for these input and output offsets relies on AC-coupling and zero-forcing during squelch intervals. One disadvantage of this technique is that a relatively long squelch interval (e.g., about 50-100 nanosec) is typically required, during which time the amplifier is not available for signal processing of user data. As a result, analog storage of the offset compensation is required. Moreover, zero-forcing involves the use of a high-gain, low-offset, high-speed auxiliary amplifier, which typically increases the cost, size, and complexity of the VGA.  
       SUMMARY OF THE INVENTION  
       [0007]     Problems in the prior art are addressed in accordance with the principles of the present invention by a technique for calibrating a variable-gain amplifier that does not suffer from all of the disadvantages of conventional techniques that rely on AC-coupling and zero-forcing. According to certain embodiments, the present invention is circuitry having a VGA comprising one or more amplifier stages and two or more offset correction sources connected to apply two or more offset correction signals at two or more different locations within the VGA. According to other embodiments, the present invention is a method for calibrating a VGA comprising one or more amplifier stages and two or more offset correction sources connected to apply two or more offset correction signals at two or more different locations within the VGA, the method comprising controlling the two or more offset correction sources to achieve desired corresponding amplifier stage output signals.  
         [0008]     The offset correction achieved using such techniques can be independent of the VGA&#39;s gain setting. Moreover, no additional poles need to be added to the signal path, and the offset correction results can be stored in digital storage elements, thereby eliminating the need for sample/hold or similar analog memory elements that require periodic refreshing and which are typically used in conventional VGA calibration techniques. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.  
         [0010]      FIG. 1  shows a schematic diagram of a three-stage variable-gain amplifier, according to one embodiment of the present invention;  
         [0011]      FIG. 2  shows a flow diagram representing a method for calibrating VGAs, such as the VGA of  FIG. 1 , according to one embodiment of the present invention; and  
         [0012]      FIG. 3  shows a flow diagram representing a method for calibrating VGAs, such as a modified version of the VGA of  FIG. 1 , according to another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0000]     VGAs Having Input and Output Offset Correction Sources  
         [0013]      FIG. 1  shows a schematic diagram of a three-stage variable-gain amplifier  100 , according to one embodiment of the present invention. As shown in  FIG. 1 , VGA  100  has three amplifier stages  102   a - c  and four offset correction sources, represented by four digital-to-analog (D/A) converters  104   a - d  operating under the control of digital controller  106 .  
         [0014]     Ignoring the offset correction voltages Vc 1 -Vc 4  applied by D/A converters  104   a - d  for the time being, under ideal conditions, an input signal Vin is input to and amplified by initial amplifier stage  102   a  to generate output signal Vo 1 , which is then input to second amplifier stage  102   b , which generates output signal Vo 2 , which is then input to third and final amplifier stage  102   c , which generates output signal Vo 3 , which is also the output signal for VGA  100 .  
         [0015]     Unfortunately, due to process variations and/or changes in operating conditions, an offset voltage that occurs in an amplifier stage can be treated as if it were either an offset voltage appearing at the input of the amplifier stage or an offset voltage appearing at the output of the amplifier stage. These are represented in  FIG. 1  by offset voltages injected at summation nodes  108   a - f . For example, at summation node  108   a , an input offset voltage Vofsi 1  is shown being injected at the input of initial amplifier stage  102   a  at summation node  108   a , while an output offset voltage Vofso 1  is shown being injected at the output of initial amplifier stage  102   a  at summation node  108   b . Similarly, input and output offset voltages Vofsi 2  and Vofso 2  are shown being injected into the input and output of second amplifier stage  102   b  at summation nodes  108   c  and  108   d , respectively, and input and output offset voltages Vofsi 3  and Vofso 3  are shown being injected into the input and output of third amplifier stage  102   c  at summation nodes  108   e  and  108   f , respectively. These offset voltages, which are amplified (with the exception of Vofso 3 ) by the downstream amplifier stages, contribute undesirable noise to the VGA output signal Vo 3 , which can lead to bit errors or other undesirable data processing artifacts downstream of VGA  100 . In addition, offset voltages can limit the dynamic range of the amplifier and produce an undesirable, gain-dependent signal component. Note that summation nodes  108   c  and  108   e  represent the injection of input offset voltages at stages  102   b  and  102   c , respectively. As such, those summation nodes should not necessarily be interpreted as representing actual elements in the amplifier architecture. On the other hand, offset correction voltages from D/A converters  104   a - d  may be considered to be applied at actual summation nodes (i.e., nodes  108   a ,  108   b ,  108   d , and  108   f ) in the amplifier architecture.  
         [0016]     As shown in  FIG. 1 , to compensate for these various input and output offset voltages, offset correction voltages Vc 1 -Vc 4  are applied into the amplifier signal path at summation nodes  108   a ,  108   b ,  108   d , and  108   f , respectively. Ideally, offset correction voltages Vc 1 -Vc 4  are selected to compensate exactly for the effects of the six offset voltages Vofsi 1 -Vofsi 3  and Vofso 1 -Vofso 3 , such that output signal Vo 3  corresponds only to an amplified version of input signal Vin, independent of the VGA&#39;s gain setting. In reality, offset correction voltages Vc 1 -Vc 4  are selected at least to reduce and hopefully minimize the net effect of the various offset voltages in a manner that is substantially independent of the gain setting of the VGA.  
         [0017]      FIG. 2  shows a flow diagram representing a method for calibrating VGAs, such as VGA  100  of  FIG. 1 , according to one embodiment of the present invention. At step  202 , the amplifier settings are initialized. In one implementation, this involves setting Vin and all of the offset correction voltages Vc 1 -Vc 4  to 0V. Steps  204 ,  214 , and  216  sequentially select different amplifier stages, one at a time starting with the initial amplifier stage and proceeding downstream to the final amplifier stage. The following processing steps are described in the context of initial amplifier stage  102   a  of VGA  100  of  FIG. 1  being the currently selected amplifier stage. Those same processing steps are analogously applied when each other amplifier stage is subsequently selected.  
         [0018]     At step  206 , the gains of the amplifier stages are initialized, e.g., to unity. For this particular embodiment, all that is needed is that the gains of the currently selected amplifier stage and any preceding amplifier stages be initialized. In some VGA designs, however, the amplifier stages might be controlled together, in which case, all of the gains would be initialized together. Either way, the implementation of this particular embodiment of the present invention should not be affected.  
         [0019]     At step  208 , the output signal Vo 1  of initial amplifier stage  102   a  is measured, and offset correction signal Vc 2  is adjusted (i.e., up or down as appropriate) until Vo 1 =0V. With Vin and Vc 1  both initialized to 0V and amplifier stage  102   a  set at unity gain, Equation (1) applies as follows: 
 
Vo 1 =Vofsi 1 +Vofso 1 +Vc 2 .  (1) 
 
 After adjusting Vc 2  in step  208  such that Vo 1 =0V, Equation (2) applies as follows: 
 
Vc 2 =−Vofso 1 −Vofsi 1 .  (2) 
 
         [0020]     At step  210 , the gains of the amplifier stages are changed, e.g., to 2. Here, too, for this particular embodiment, all that is needed is that the gains of the currently selected amplifier stage and any preceding amplifier stages be changed. Changing the gains of the amplifier stages will typically result in changes to the output signals of the amplifier stages (e.g., output signal Vo 1  of amplifier stage  102   a ).  
         [0021]     At step  212 , output signal Vo 1  of initial amplifier stage  102   a  is measured, and offset correction signals Vc 1  and Vc 2  are adjusted until the sign of Vo 1  just changes. For example, if, after changing the gains of the amplifier stages, Vo 1 &gt;0V, then Vc 1  and Vc 2  are incrementally adjusted according to Equations (3) and (4) as follows: 
 
Vc 1 =Vc 1 −Δν  (3) 
 
Vc 2 =Vc 1 +Δν,  (4) 
 
 where Δν is an appropriate, selected voltage increment (e.g., 0.5 mV). Otherwise, if, after changing the gains of the amplifier stages, Vo 1 &lt;0V, then Vc 1  and Vc 2  are incrementally adjusted according to Equations (5) and (6) as follows: 
 
Vc 1 =Vc 1 +Δν  (5) 
 
Vc 2 =Vc 1 −Δν.  (6) 
 
 The incremental adjustments of Equations (3) and (4) or of Equations (5) and (6) are continued until the sign of Vo 1  just changes. 
 
         [0022]     With Vin=0V and the gain amplifier stage  102   a  set at 2, Equation (7) applies as follows: 
 
Vo 1 =2*(Vofsi 1 +Vc 1 )+Vofso 1 +Vc 2 .  (7) 
 
 Just before the incremental adjustments of step  212 , Vc 1 =0V (from the earlier amplifier initialization) and Vc 2  is given by Equation (2). Substituting these equations into Equation (7) yields Equation (8) as follows: 
 
Vo 1 =Vofsi 1 .  (8) 
 
 Using the incremental adjustments of Equations (3)-(4) or Equations (5)-(6) ensures that the relationship between the overall (i.e., accumulated) change ΔVc 1  to offset correction voltage Vc 1  and the overall change ΔVc 2  to offset correction voltage Vc 2  is given by Equation (9) as follows: 
 
ΔVc 2 =−Vc 1 .  (9) 
 
 Based on Vc 1  having been initialized to 0V and Equation (2) resulting from step  208 , the overall changes to Vc 1  and Vc 2  result in Equations (10) and (11) as follows: 
 
Vc 1 =ΔVc 1   (10) 
 
and 
 
Vc 2 =−Vofso 1 −Vofsi 1 −ΔVc 1 .  (11) 
 
 Substituting Equations (10) and (11) into Equation (7) yields Equation (12) as follows: 
 
Vo 1 =2*(Vofsi 1 +ΔVc 1 )+Vofso 1 −Vofso 1 −Vofsi 1 −ΔVc 1 ,  (12) 
 
 which reduces to Equation (13) as follows: 
 
Vo 1 =Vofsi 1 +ΔVc 1 .  (13) 
 
 At the point where Vo 1  just changes sign (i.e., Vo 1 ≈0), Equation (13) implies Equation (14) as follows: 
 
ΔVc 1 =−Vofsi 1 ,  (14) 
 
 where Vc 1 =ΔVc 1 , since Vc 1  was previously initialized to 0V. Substituting Equation (14) into Equation (11) yields Equation (15) as follows: 
 
Vc 2 =−Vofso 1 .  (15) 
 
 Thus, at the completion of step  212 , offset correction Vc 1  substantially—if not exactly—compensates for the input offset voltage Vofsi 1  of amplifier stage  102   a , and offset correction Vc 2  substantially—if not exactly—compensates for the output offset voltage Vofso 1  of amplifier stage  102   a.  
 
         [0023]     In the context of VGA  100  of  FIG. 1 , following the application of steps  206 - 212  for initial amplifier stage  102   a , second amplifier stage  102   b  is selected at step  216 , and the offset correction voltages for second amplifier stage  102   b  are updated at step  218  based on the calibration results from the previous amplifier stage (in this case, initial amplifier stage  102   a ). In particular, the input offset correction voltage for second amplifier stage  102   b  is kept at the value (i.e., Vc 2 ) derived for the output offset correction voltage for initial amplifier stage  102   a , while the output offset correction voltage for second amplifier stage  102   b  (i.e., Vc 3 ) is set to −Vc 2 , which on average reduces the number of steps required to compensate the output offset voltage during the incremental adjustments of step  212 .  
         [0024]     After the processing of  FIG. 2  has been completed for the final amplifier stage (e.g., amplifier stage  102   c  of  FIG. 1 ), all of the offset correction sources will have been configured to compensate substantially—if not exactly—for all of the input and output offset voltages at the various stages of the VGA.  
         [0025]     Those skilled in the art will appreciate that some or all of the settings previously described for the method of  FIG. 2  may be changed for different implementations of the present invention. For example, the generalized compensation on the output offset correction source during adjustment of the input offset correction source is given by Equation (16) as follows: 
 
ΔVci=ΔVc( i− 1)*( G− 1),  (16) 
 
 where G is the gain of the amplifier stage, where G&gt;1. This relationship may be useful for VGAs whose amplifier stages cannot produce gains of 2 for steps  210  and  212 . 
 
         [0026]     Similarly, in theory, the method of  FIG. 2  could be implemented for gain settings other than unity for steps  206  and  208 , and the offset correction signals Vci and even the input voltage Vin do not necessarily have to be initialized to 0V, as long as their non-zero values are taken into account during the calibration processing.  
         [0027]     Referring again to  FIG. 1 , VGA  100  has a single analog multiplexer (mux)  110  and a single differential comparator  112 . As shown in  FIG. 1 , mux  110  receives samples of the outputs (Vo 1 -Vo 3 ) from all three amplifier stages (which are tapped from the amplifier&#39;s signal path using elements—possibly including analog-to-digital converters—that are not shown in  FIG. 1 ). Digital controller  106  controls mux  110  to output a selected amplifier stage output signal (i.e., one of Vo 1 -Vo 3 ) for application to differential comparator  112 , which compares the selected output signal to ground to determine whether the sign of the selected output signal is positive or negative, which information is fed back to digital controller  106  for use during the incremental adjustments of step  212  to determine when the sign of the selected output signal just changes. Because the preferred method of  FIG. 2  calibrates each amplifier stage sequentially, VGA  100  can advantageously be implemented with a single differential comparator that is operationally multiplexed using mux  110  for use in calibrating all of the amplifier stages. Of course, such multiplexing is not required, and a different differential comparator could be implemented for each different amplifier stage output signal.  
         [0000]     VGAs Having Input Offset Correction Sources  
         [0028]     VGA  100  of  FIG. 1  has an input offset correction source and an output offset correction source for each of its amplifier stages. In an alternative embodiment of the present invention, a VGA might have only input offset correction sources. This can be achieved by modifying VGA  100  to eliminate D/A converter  104   d , summation node  108   f , and their associated wiring. The resulting multi-stage VGA may be considered to have only input offset correction sources, one per stage.  
         [0029]      FIG. 3  shows a flow diagram representing a method for calibrating such a modified VGA, according to another embodiment of the present invention. The method of  FIG. 3  is similar to the method of  FIG. 2  without steps  208  and  210 . In particular, at step  302 , the amplifier settings are initialized. In one implementation, this involves setting Vin and all of the offset correction voltages Vc 1 -Vc 3  to 0V. Steps  304 ,  310 , and  312  sequentially select different amplifier stages, one at a time starting with the initial amplifier stage and proceeding downstream to the final amplifier stage. The following processing steps are described in the context of initial amplifier stage  102   a  of VGA  100  of  FIG. 1  being the currently selected amplifier stage. Those same processing steps are analogously applied when each other amplifier stage is subsequently selected.  
         [0030]     At step  306 , the gains of the amplifier stages are initialized, e.g., to a high-gain setting, such as 2. At step  308 , output signal Vo 1  of initial amplifier stage  102   a  is measured, and offset correction signal Vc 1  is adjusted until the sign of Vo 1  just changes. At the completion of step  308 , offset correction Vc 1  substantially—if not exactly—compensates for both the input offset voltage Vofsi 1  and the output offset voltage Vofso 1  of amplifier stage  102   a.    
         [0031]     In the context of the modified version of VGA  100  of  FIG. 1 , following the application of steps  306 - 308  for initial amplifier stage  102   a , second amplifier stage  102   b  is selected at step  312  and processing returns to step  306  to calibrate the second amplifier stage. After the processing of  FIG. 3  has been completed for the final amplifier stage (e.g., amplifier stage  102   c  of  FIG. 1 ), all of the input offset correction sources will have been configured to compensate substantially—if not exactly—for all of the input and output offset voltages at the various stages of the VGA.  
         [0032]     Although the present invention has been described in the context of a three-stage VGA, in general, the present invention can be implemented for any VGA having one or more amplifier stages. Moreover, although the present invention has been described in the context of multi-stage VGAs in which one or two voltage correction signals are applied at each amplifier stage, in theory, the invention can be implemented for a multi-stage VGA in which one or more of the amplifier stages do not receive any voltage correction signals.  
         [0033]     Digital controller  106  can be implemented using any suitable circuitry, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. For example, the digital controller can be implemented as a relatively small macro in an integrated circuit that also implements the rest of VGA  100 . As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing steps in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer.  
         [0034]     The present invention can be embodied in the form of methods and apparatuses for practicing those methods. The present invention can also be embodied in the form of program code embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium or carrier, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits.  
         [0035]     Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.  
         [0036]     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.  
         [0037]     Although the steps in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.