Abstract:
A bandgap reference circuit incorporates first, second, and third current sources, first and second amplifiers, first and second bipolar transistors, a feedback device, a first resistor, and a second resistor. The first resistor is coupled between one input of the second amplifier and the base of the first bipolar transistor. The second resistor is coupled between the base of the first bipolar transistor and the base of the second bipolar transistor. The first and second amplifies and the first to third current sources constitute negative feedback loops which force the voltages at the inputs of the amplifiers to be substantially equal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
       [0001]    The present invention generally relates to reference circuits, and more specifically to a bandgap reference circuit. 
       2. Description of the Related Art 
       [0002]    A bandgap reference circuit is used to generate a precise and a stable output voltage. The generated voltage is independent of process, voltage, and temperature. The bandgap reference circuit is widely used in various analog and digital circuits that require a precise voltage for operation. 
         [0003]      FIG. 1  illustrates one commonly used bandgap reference circuit  100 . Referring to  FIG. 1 , the bandgap reference circuit  100  includes PMOS transistors M 1 , M 2 , and M 3 , an operational amplifier OP, resistors R 1  and R 2 , and bipolar transistors Q 1 , Q 2 , and Q 3 . If the base current is neglected, the output voltage VOUT of the bandgap reference circuit  100  can be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   VOUT 
                   = 
                   
                     
                       VEB 
                        
                       
                           
                       
                        
                       3 
                     
                     + 
                     
                       VT 
                       × 
                       ln 
                        
                       
                           
                       
                        
                       N 
                       × 
                       
                         ( 
                         
                           
                             R 
                              
                             
                                 
                             
                              
                             2 
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0004]    Where VEB 3  is the emitter-base voltage of the bipolar transistor Q 3 , VT is the thermal voltage at room temperature, and N is the ratio of the emitter areas of the bipolar transistor Q 2  to the emitter areas of the bipolar transistor Q 1 . 
         [0005]    As can be seen from the equation (1), by adjusting the resistance ratio of resistors R 2  to R 1 , the conventional bandgap reference circuit  100  can provide a stable reference voltage VOUT having a zero temperature coefficient. The voltage level of the voltage VOUT is at around 1.25V, which is approximately equal to the silicon energy gap measured in electron volts, i.e., the silicon bandgap voltage. 
         [0006]    However, in order to meet the application requirements of different integrated circuits, a reference voltage with a substantially zero temperature coefficient at different voltage levels is needed. 
       SUMMARY OF THE INVENTION 
       [0007]    One aspect of the present invention is a bandgap reference circuit that provides a reference voltage and a reference current. 
         [0008]    According to one embodiment of the present invention, the bandgap reference circuit comprises first, second, and third current sources, first and second amplifiers, first and second bipolar transistors, a feedback device, a first resistor, and a second resistor. The first amplifier has a first input, a second input, and a first output. The second amplifier has a third input, a fourth input, and a second output. The first current source is coupled between a power supply node and the first input of the first amplifier. The second current source is coupled between the power supply node and the second input of the first amplifier. The third current source is coupled between the power supply node and the third input of the second amplifier. The first bipolar transistor has a base, an emitter coupled to the first current source, and a collector coupled to a ground node. The second bipolar transistor has a base, an emitter coupled to the second current source, and a collector coupled to the ground node. The first resistor is coupled between the third input of the second amplifier and the base of the first bipolar transistor. The feedback device is coupled between the third current source and the base of the second bipolar transistor and the first feedback device is controlled by the second output of the second amplifier. The second resistor is coupled between the base of the first bipolar transistor and the base of the second bipolar transistor. The fourth input of the second amplifier is coupled to one of the first input of the first amplifier and the second input of the first amplifier. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The invention will be described according to the appended drawings in which: 
           [0010]      FIG. 1  illustrates one commonly used bandgap reference circuit; 
           [0011]      FIG. 2  shows a schematic diagram of a bandgap reference circuit according to a first embodiment of the present invention; 
           [0012]      FIG. 3  shows a schematic diagram of a bandgap reference circuit for a second embodiment of the present invention; 
           [0013]      FIG. 4  shows a schematic diagram of a bandgap reference circuit for a third embodiment of the present invention; and 
           [0014]      FIG. 5  shows a schematic diagram of a bandgap reference circuit for a fourth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]      FIG. 2  shows a schematic diagram of a bandgap reference circuit  200  according to one embodiment of the present invention. Referring to  FIG. 2 , the bandgap reference circuit  200  comprises a current source unit  22 , an operational amplifier OP 1 , an operational amplifier OP 2 , a bipolar transistor Q 1 , a bipolar transistor Q 2 , a feedback transistor MA, a resistor R 1 , and a resistor R 2 . 
         [0016]    The current source unit  22  provides a plurality of stable bias currents I 1 , I 2 , and I 3 . In this embodiment, the current source unit  22  is a current mirror formed by a plurality of PMOS transistors M 1 , M 2 , and M 3 . Referring to  FIG. 2 , the PMOS transistor M 1  has a source coupled to a supply voltage VDD, a gate coupled to an output of the operational amplifier OP 1 , and a drain coupled to an inverting input of the operational amplifier OP 1 . The PMOS transistor M 2  has a source coupled to the supply voltage VDD, a gate coupled to the output of the operational amplifier OP 1 , and a drain coupled to a non-inverting input of the operational amplifier OP 1  and an inverting input of the operational amplifier OP 2 . The PMOS transistor M 3  has a source coupled to the supply voltage VDD, a gate coupled to the output of the operational amplifier OP 1 , and a drain coupled to a non-inverting input of the operational amplifier OP 2 . 
         [0017]    The bipolar transistor Q 1  has a base, an emitter coupled to the inverting input of the operational amplifier OP 1 , and a collector coupled to a ground node. The bipolar transistor Q 2  has a base, an emitter coupled to the non-inverting input of the operational amplifier OP 1  and the inverting input of the operational amplifier OP 2 , and a collector coupled to the ground node. 
         [0018]    Referring to  FIG. 2 , the feedback transistor MA is a NMOS transistor having a drain coupled to the non-inverting input of the operational amplifier OP 2 , a gate coupled to an output of the operational amplifier OP 2 , and a source coupled to the base of the bipolar transistor Q 2 . The resistor R 1  is connected between the non-inverting input of the operational amplifier OP 2  and the base of the bipolar transistor Q 1 . The resistor R 2  is coupled between the base of the bipolar transistor Q 1  and the base of the bipolar transistor Q 2 . 
         [0019]    Referring to  FIG. 2 , the operational amplifier OP 1  and the current source unit  22  constitute a first negative feedback loop which forces the voltages VD 1  and VD 2  to be substantially equal. The operational amplifier OP 2 , the feedback transistor MA, and the current source unit  22  constitute a second negative feedback loop which forces the voltages VD 2  and VD 3  to be substantially equal. 
         [0020]    Since the gates of the PMOS transistors M 1 , M 2 , and M 3  are connected to each other, the sources of the PMOS transistors M 1 , M 2 , and M 3  are connected to the common supply voltage VDD, and the voltages at the drains of the PMOS transistors M 1 , M 2 , and M 3  are substantially equal, the currents I 1 , I 2 , and I 3  flowing through the PMOS transistors M 1 , M 2 , and M 3  are proportional to the W/L ratio of the transistors. 
         [0021]    Referring to  FIG. 2 , the voltages VD 1  and VD 3  can be expressed as: 
         [0000]        VD 1= VREF+VEB 1= VD 3= VREF+I 3 A×R 1  (2)
 
         [0022]    VREF is a summed voltage at a summing node N 1 . VEB 1  is the emitter-base voltage of the bipolar transistor Q 1 , and I 3 A is the current flowing through the resistor R 1 . 
         [0023]    Thus, equation (2) can rearranged into the following equation (3): 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                      
                     
                         
                     
                      
                     3 
                      
                     A 
                   
                   = 
                   
                     
                       VEB 
                        
                       
                           
                       
                        
                       1 
                     
                     
                       R 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0024]    Since the emitter-base voltage of the bipolar transistor Q 1  is nearly complementary to absolute temperature (i.e., a CTAT voltage), the current I 3 A is a CTAT current. 
         [0025]    By ignoring the base currents of the bipolar transistors Q 1  and Q 2 , voltages VD 1  and VD 2  can be expressed as: 
         [0000]        VD 1= VREF+VEB 1= VD 2= VREF+I 3 B×R 2+ VEB 2  (4)
 
         [0026]    VEB 2  is the emitter-base voltage of the bipolar transistor Q 2 , and I 3 B is the current flowing through the resistor R 2 . 
         [0027]    Thus, equation (4) can rearranged into the following equation (5): 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                      
                     
                         
                     
                      
                     3 
                      
                     B 
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             VEB 
                              
                             
                                 
                             
                              
                             1 
                           
                           - 
                           
                             VEB 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         ) 
                       
                       
                         R 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     = 
                     
                       
                         Δ 
                          
                         
                             
                         
                          
                         VBE 
                       
                       
                         R 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0028]    Since the voltage difference ΔVBE is proportional to an absolute temperature (i.e., a PTAT voltage), the current I 3 B is a PTAT current. 
         [0029]    Referring to  FIG. 2 , one CTAT current I 3 A flowing through R 1  is summed with one PTAT current I 3 B flowing through R 2  at the summing node N 1  (ignoring the base currents of the bipolar transistors Q 1  and Q 2 ). Therefore, the bandgap reference circuit  200  can provide a stable output current IREF having a zero temperature coefficient by adjusting the value of the resistor R 1  and the value of the resistor R 2 . The bandgap reference circuit  200  can also provide the stable output current IREF having a desired temperature coefficient by adjusting the value of the resistor R 1  and the value of the resistor R 2 . For example, the positive temperature coefficient of the output current IREF is obtained by decreasing the value of the resistor R 2 , and the negative temperature coefficient of the output current IREF is obtained by decreasing the value of the resistor R 1 . In order to mirror the current IREF, a PMOS transistor M 4  is added in the current source unit  22 . Since the amount of the output current IREF current is substantially equal to that of the current flowing through the PMOS transistor M 3  (ignoring the base currents of the bipolar transistors Q 1  and Q 2  and the input currents of the operational amplifier OP 2 ), the PMOS transistor M 4  provides an output current I 4  proportional to the W/L ratio of the transistors. 
         [0030]    Referring to  FIG. 3 , a resistor R 3  is coupled between the summing node N 1  and the ground node. Therefore, the stable reference voltage VREF is obtained at the summing node N 1 . A resistor R 4  is coupled between the drain of the PMOS transistor M 4  and the ground node. Therefore, the other stable reference voltage VREF 1  is obtained. In order to provide the more precise current I 4 , an operational amplifier OP 3  and a feedback transistor MB are added in  FIG. 4 . The operational amplifier OP 3 , the feedback transistor MB, and the current source unit  42  constitute a third negative feedback loop which forces the voltages VD 3  and VD 4  to be substantially equal. 
         [0031]    Compared with the prior art, the bandgap reference circuit  300  of  FIG. 3  can provide the stable reference voltage VREF 1  at a lower voltage level (e.g., less than about 0.6V) since the resistor R 4  is directly connected to the ground node, rather than the bipolar transistor Q 3  shown in  FIG. 1 . In addition, since the voltages VD 1 , VD 2  and VD 3  are substantially equal and the gates of the PMOS transistors M 1 , M 2 , M 3 , and M 4  are connected to each other, the PMOS transistors M 1 , M 2 , M 3 , and M 4  can be biased at the saturation region or at the linear region to provide proportional currents which are proportional to the W/L ratio of the transistors. With such circuit configuration, the bandgap reference circuit  300  of the invention can provide the output voltage VREF 1  in a wide voltage range from 0V to VDD-VSD,M 4  depending on the value of the resistor R 4 , wherein VSD,M 4  is the source-drain voltage of the PMOS transistor M 4 . That is, the output voltage VREF 1  can be close to the supply voltage VDD. 
         [0032]    Referring to  FIG. 3 , the operational amplifier OP 1 , the operational amplifier OP 2 , and the feedback transistor MA maintain the voltages VD 1 , VD 2  and VD 3  at substantially equal voltages by negative feedback. However, it should be obvious that the present invention is not limited to this configuration. For example, the inverting input of the operational amplifier OP 2  can receive the voltage VD 1  rather than the voltage VD 2  in  FIG. 2 . In another embodiment of the present invention, a feedback transistor MC is a PMOS transistor as shown in  FIG. 5 . The non-inverting input of the operational amplifier OP 2  receives the voltage VD 2 , and the inverting input of the operational amplifier OP 2  receives the voltage VD 3 . In yet another embodiment of the present invention, the non-inverting input of the operational amplifier OP 2  receives the voltage VD 1  rather than the voltage VD 2  in  FIG. 5 . With such circuit configurations, the voltages VD 1 , VD 2  and VD 3  are substantially equal. 
         [0033]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention as recited in the following claims.