Abstract:
The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims benefit to U.S. Provisional Patent Application Ser. No. 60/771,009, filed Feb. 8, 2006, entitled “ISI Reduction Technique”, which is incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates generally to signal processing circuits, and more specifically to a switch-capacitor circuit for reducing the Inter-Symbol-Interference (ISI) effect. 
         [0004]    2. Background Art 
         [0005]    Switch-Capacitor (SC) circuits are widely used in all kinds of signal processing circuits and are based on capacitors that are switched to signal voltages. Typically, the switching takes place at the beginning of every clock cycle. After the switching, the capacitor is charged to the signal voltage. This process takes some time and the speed of charging depends on the time constant involved. 
         [0006]    At the same time the capacitor is being charged up to its new voltage, it is being discharged from the voltage it had at the end of the previous clock cycle. 
         [0007]    Both the charging and discharging process can be described by the same time constant and therefore can have the same speed. Because the discharging is imperfect, some voltage from the previous clock cycle may remain. This phenomenon is called Inter-Symbol-Interference (ISI). 
         [0008]    For most circuits, the accuracy that is required for the charging process is usually similar to the accuracy required for the discharging process. In such a case, ISI does not significantly limit the maximum clock frequency. However, there exist certain types of circuits which do not require a high level of accuracy for charging, but still require a high level of accuracy for discharging. In such cases, ISI does limit the maximum clock frequency. Thus, if the ISI problem could be reduced in these types of circuits, the maximum clock frequency of such circuits could be increased. For example, a SubRange ADC consisting of a Coarse and Fine ADC is a circuit affected by ISI. Here, ISI leads to errors in the decision of both the Coarse and Fine decision. 
         [0009]    Referring now to  FIG. 1 , there is shown a simple prior art switch-capacitor circuit  100  having a voltage source  102  having a variable voltage output Vin, an output resistance  104 , a capacitor  106 , and switches,  108   a ,  108   b , and  108   c , that are operated during non-overlapping clock phases phi( 1 ) (switches  108   a ,  108   b ) and phi( 2 ) (switch  108   c ). Vin may be the output voltage of a circuit, such as a Track-Hold (TH) amplifier (not shown). 
         [0010]    As can be seen from  FIG. 1 , the voltage source  102  is coupled to the switch  108   a  via a line  102   a . The switch  108   a  is coupled to the capacitor  106  via a line  106   a , and to the switch  108   c  via a line  106   b . Further, the capacitor  106  is coupled to the switch  108   b  via a line  106   c . As is further shown in  FIG. 1 , the voltage source  102  is coupled to the switch  108   c  via a line  102   b , and a line  102   c , and to the switch  108   b  via the line  102   b , and a line  102   d.    
         [0011]    During clock phase phi( 1 ), the capacitor  106  is charged to Vin through resistance  104 . During the same time interval, capacitor  106  is also being discharged through resistance  104 . The effect of discharging of the previous voltage across the capacitor  106  is clearly visible in the nodal voltage Va. At the beginning of phi( 1 ), Va starts at the previous value of Vin. Because Va is not equal to Vin at the end of phi( 1 ), Vb during phi( 2 ) is also not equal to Vin during phi( 1 ). Thus, both voltages Va and Vb are not ideal. 
         [0012]    Some circuits are negatively impacted by the non-ideal behavior of Va and others more by the non-ideal behavior of Vb. For example, a SubRange ADC with a Coarse and Fine ADC is negatively affected by the non-ideal behavior of Va. The ISI kick comes from the Fine ADC (modeled by the capacitor C). The Coarse ADC is also connected to node a during phi( 1 ). The amplifiers inside the Coarse ADC amplify Va. The outputs of these amplifiers are highly distorted because of the ISI kick and this has a negative impact on the Coarse-Fine timing of the SubRange ADC. An example of a circuit that is sensitive to the non-ideal behavior of Vb is the Fine ADC of a SubRange ADC. When Vb differs too much from Vin, distortion inside the ADC occurs. Thus, what is needed is an improved switch-capacitor circuit that improves the non-ideal behavior of Va and Vb. 
         [0013]    One method for reducing the ISI effect is to increase the bandwidth of the circuits. However, because this solution also increases current consumption, it is neither an attractive nor practical solution. 
         [0014]    Another method for reducing ISI is based on shorting the capacitor  106  for a short amount of time. Referring now to  FIG. 2 , there is shown a switch-capacitor circuit in which ISI cancellation is achieved by shorting the capacitor (here: a capacitor  206 ). Corresponding to the switch-capacitor circuit  100  shown in  FIG. 1 , the switch-capacitor circuit  200  shown in  FIG. 2  comprises a voltage source  202  having a variable voltage output Vin, an output resistance  204 , a capacitor  206 , and switches,  208   a ,  208   b , and  208   c , that are operated during non-overlapping clock phases phi( 1 ) (switches  208   a ,  208   b ) and phi( 2 ) (switch  208   c ). Further, the switch-capacitor circuit  200  comprises a switch  208   d  for shorting the capacitor  206 . 
         [0015]    As can be seen from  FIG. 2 , the voltage source  202  is coupled to the switch  208   a  via a line  202   a . The switch  208   a  is coupled to the capacitor  206  via a line  206   a , and to the switch  208   c  via a line  206   b . Further, the capacitor  206  is coupled to the switch  208   b  via a line  206   c . As is further shown in  FIG. 2 , the voltage source  202  is coupled to the switch  208   c  via a line  202   b , and a line  202   c , and to the switch  208   b  via the line  202   b , and a line  202   d . In addition, the switch  208   d  is coupled to the capacitor  206  (and to the switches  208   a ,  208   c ) via a line  208   e , and to the capacitor  206  (and to the switch  208   b ) via a line  208   f.    
         [0016]    The above shorting of the capacitor  206  by the switch  208   d  is illustrated by switch phi( 3 ) at the beginning of the clock cycle phi( 1 ). Although this solution is relatively simple to implement, this technique has several disadvantages. One disadvantage is that the output terminal of the amplifier is temporarily shorted which creates huge current spikes in the amplifier. Another disadvantage is that the time to charge the capacitor  206  up to Vin (during phi( 1 )) effectively becomes shorter since no charging is possible during phi( 3 ). The charging of the capacitor  206  begins after phi( 3 ). As a result, the maximum clock frequency of the circuit effectively decreases depending on the duration of phi( 3 ). 
         [0017]    Therefore, what is needed is a new technique and circuit that reduces the ISI effect without the problems encountered in the prior art. 
       BRIEF SUMMARY OF THE INVENTION 
       [0018]    The present invention comprises a method and a system, such as a switch-capacitor circuit, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
         [0019]    The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention. 
           [0020]      FIG. 1  illustrates a simple prior art switch-capacitor circuit with timing and voltages. 
           [0021]      FIG. 2  illustrates another prior art switch-capacitor circuit. 
           [0022]      FIG. 3  illustrates a switch-capacitor circuit in accordance with one embodiment of the present invention. 
           [0023]      FIG. 4  illustrates another switch-capacitor circuit in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known processes and steps have not been described in detail in order not to unnecessarily obscure the present invention. 
         [0025]    The present invention generally pertains to a technique and circuit configuration for reducing the Inter-Symbol-Interference (ISI) effect in a switch capacitor circuit. 
         [0026]    Referring now to  FIG. 3 , there is shown a switch-capacitor circuit  300  in accordance with one embodiment of the present invention. The switch-capacitor circuit  300  comprises a voltage source  302 , an output resistance  304 , switches  310   a ,  310   b ,  310   c ,  310   d ,  310   e ,  310   f ,  310   g ,  310   h ,  310   i , and capacitors  306 ,  308 . 
         [0027]    Capacitor  306  is connectable with the voltage source  302  and the output resistance  304 . Capacitor  308  can be connected to the capacitor  306  in parallel through switches  310   f,g  and anti-parallel through switches  310   d,e.    
         [0028]    In further detail, as is shown in  FIG. 3 , the voltage source  302  is coupled to the switch  310   a  via a line  302   a . The switch  310   a  is coupled to the switch  310   h  via a line  306   a , and to the switch  310   c  via a line  306   b . Further, the switch  310   h  is coupled to the capacitor  306  via a line  310   a . Further, the capacitor  306  is coupled to the switch  310   i  via a line  310   b . The switch  310   i  is coupled to the switch  310   b  via a line  306   c . As is further shown in  FIG. 3 , the voltage source  302  is coupled to the switch  310   c  via a line  302   b , and a line  302   c , and to the switch  310   b  via the line  302   b , and a line  302   d.    
         [0029]    In addition, the switch  310   f  is coupled to the switch  310   h  (and to the switches  310   a ,  310   c ) via a line  311   a . Further, the switch  310   g  is coupled to the switch  310   i  (and to the switch  310   b ) via a line  311   b.    
         [0030]    As is shown in  FIG. 3 , the switch  310   f  is coupled to the capacitor  308  via a line  311   c , and to the switch  310   d  via a line  311   d.    
         [0031]    Correspondingly, the switch  310   g  is coupled to the capacitor  308  via a line  311   e , and to the switch  310   e  via a line  311   f.    
         [0032]    Still further, the switch  310   d  is coupled to the switch  310   i  (and to the switches  310   b ,  310   g ) via a line  311   g  (and the line  311   b , etc.). 
         [0033]    Correspondingly, the switch  310   e  is coupled to the switch  310   h  (and to the switches  310   c ,  310   a ,  310   f ) via a line  311   h  (and the line  311   a , etc.). 
         [0034]    Switches  310   a ,  310   b ,  310   c  are operated in a way analogous to the prior art switch-capacitor circuit  100  of  FIG. 1  (in particular, the corresponding switches  108   a ,  108   b ,  108   c ), that is to say they are operated during non-overlapping clock-phases phi( 1 ) (switches  310   a ,  310   b ) and phi( 2 ) (switch  310   c ) (see  FIG. 1 ). 
         [0035]    Switch-capacitor circuit  300  splits the capacitor (e.g., the capacitor  106 ) from the prior art switch capacitor circuit  100  into two equal parts, capacitor  306 , and capacitor  308  (i.e., two capacitors  306 ,  308  of the same capacitance), and connects capacitor  308 , to non-overlapping clock-phases phi(x) (switches  310   f,g ) and phi(y) (switches  310   e,d ) (i.e., electrically couples the capacitor  308  during the clock-phase phi(x) to the lines  311   a ,  311   b  via the switches  310   f ,  310   g  (but not via the switches  310   d ,  310   e ), and electrically couples the capacitor  308  during the clock-phase phi(y) to the lines  311   a ,  311   b  via the switches  310   d ,  310   e  (but not via the switches  310   f ,  310   g , i.e., inversely as during the clock-phase phi(x))). The operation frequency of these switches (switches  310   f,g , and switches  310   e,d ) is half that of phi( 1 ) and phi( 2 ). 
         [0036]    For reasons of symmetry, capacitor  306 , may be connected by switches  310   h,i  to the circuit  300 . These switches can be always left on or be operated on phi(x) or phi(y). 
         [0037]    At the beginning of phi( 1 ) the switches  310   f,g , in series with capacitor  308 , are also being operated (beginning of phi(x)), but not the switches  310   d ,  310   e . Therefore, the capacitors  306  and  308  are both charged to a first voltage V 1 . 
         [0038]    During phi( 2 ), the voltage V 1  existing across capacitors  306  and  308  remains constant, since both capacitors  306  and  308  are disconnected from the voltage source  302  and the resistance  304 , while the voltage source  302  changes its output voltage without any impact on the capacitors  306  and  308  during phi( 2 ) being disconnected from these. 
         [0039]    Then, at a new beginning of phi( 1 ), the switches  310   d  and  310   e  are also being operated (beginning of phi(y)), but not the switches  310   f  and  310   g , thus applying an anti-parallel connection between the capacitors  306  and  308 . Consequently, the voltage V 1  still existing across capacitor  306 , is compensated by an equal voltage V 2  existing across capacitor  308 , which is opposite in sign. The net voltage is zero, which means a total discharge. This discharge path does not go through resistance  304 , but goes from capacitor  306  to capacitor  308 , and is therefore very fast. 
         [0040]    As, during phi( 1 ), the capacitors  306  and  308  being connected anti-parallel are now connected with the voltage source  302 , which has changed its output voltage during the last phi( 2 ), the capacitors  306  and  308  are charged with a third voltage V 3  and a fourth voltage V 4 , respectively, wherein the voltages V 3  and V 4  have the same absolute value, but are opposite in sign. 
         [0041]    During phi( 2 ), the voltages V 3  and V 4  existing across capacitors  306  and  308 , respectively, remain constant, since both capacitors  306  and  308  are disconnected from the voltage source  302  and the resistance  304 , while the voltage source  302  changes its output voltage without any impact on the capacitors  306  and  308  during phi( 2 ) being disconnected from these. 
         [0042]    Then, at a further new beginning of phi( 1 ) the switches  310   f  g, in series with capacitor  308 , are also being operated (beginning of phi(x)), but not the switches  310   d ,  310   e , and the capacitors are now connected in parallel again. Consequently, the voltage V 3  still existing across capacitor  306 , is compensated by an the voltage V 4  existing across capacitor  308 . The net voltage is zero, which means a total discharge. The discharge path goes from capacitor  306  to capacitor  308 , and is therefore very fast. 
         [0043]    At this point, a full cycle has been carried out and the process described above starts anew. 
         [0044]    Summarizing, the charge compensation in the circuit  300  is obtained by flipping the capacitor  308 , with respect to capacitor  306 , and applying an anti-parallel connection. 
         [0045]    Typically, capacitors do not have a symmetrical layout, but one terminal of a capacitor is shielding the other terminal from unwanted electric fields. The shield prevents unwanted electric fields to enter the shielded terminal. The shielding terminal should be used as the transmitter and this terminal is always connected to a fixed voltage (either through a switch or through a resistor). The terminal that is shielded should be used as the receiver and this terminal is sometimes floating. A floating terminal is sensitive to unwanted electric fields and therefore it needs to be shielded. 
         [0046]    When the capacitor  308  is flipped and anti-parallel connected, the transmitter becomes the receiver while it still “sees” unwanted electric fields. This now becomes an issue, since this node is floating. 
         [0047]    Referring now to  FIG. 4 , there is shown another switch-capacitor circuit  400  in accordance with another embodiment of the present invention. The switch-capacitor circuit  400  of  FIG. 4  cancels the ISI while the shielded terminal is always the receiver. 
         [0048]    The switch-capacitor circuit  400  comprises voltage sources  402 ,  403 , output resistances  404 ,  405 , capacitors  406 ,  407 ,  408 ,  409  and switches  410   a ,  410   b ,  410   c ,  410   d ,  410   e ,  410   f ,  410   g ,  410   h ,  410   i ,  410   k ,  410   l ,  410   m ,  410   n ,  410   o ,  410   p ,  410   q.    
         [0049]    The circuit is based on differential signals and also on split capacitors, similar as in the embodiment shown in  FIG. 3 , but switch-capacitor circuit  400  further splits capacitors  306  and  308  of  FIG. 3  into capacitors  406 ,  407  and into capacitors  408 ,  409 , respectively. The capacitors  406 - 409  all have the same capacitance. 
         [0050]    The capacitor  406  is connectable to the voltage source  402  and output resistance  404  and the capacitor  407  is connectable to the voltage source  403  and the output resistance  405 . Capacitor  408  can be connected in parallel to capacitor  406  through switches  410   e,f  and can also be connected in parallel to capacitor  407  through switches  410   i,k . Capacitor  409  can be connected in parallel to capacitor  407  through switches  410   g,h  and can also be connected in parallel to capacitor  406  through switches  410   l,m.    
         [0051]    In further detail, as is shown in  FIG. 4 , the voltage source  404  is coupled to the switch  410   a  via a line  402   a , and the voltage source  405  is coupled to the switch  410   b  via a line  405   a.    
         [0052]    The switch  410   a  is coupled to the switch  410   d  via a line  411   a , to the switch  410   l  via a line  411   b , to the switch  410   e  via a line  411   c , and to the switch  410   n  via a line  411   d.    
         [0053]    Further, the switch  410   b  is coupled to the switch  410   d  via a line  411   e , to the switch  410   i  via a line  411   f , to the switch  410   g  via a line  411   g , and to the switch  410   p  via a line  411   h.    
         [0054]    The switch  410   n  is coupled to the capacitor  406  via a line  412   a . In addition, the capacitor  408  is coupled to the switch  410   e  via a line  412   b , and to the switch  410   i  via a line  412   c.    
         [0055]    Further, the switch  410   p  is coupled to the capacitor  407  via a line  412   d . In addition, the capacitor  409  is coupled to the switch  410   g  via a line  412   d , and to the switch  410   l  via a line  412   e.    
         [0056]    Still further, the capacitor  406  is coupled to the switch  410   o  via a line  413   a , and the capacitor  408  is coupled to the switch  410   f  via a line  413   b , and to the switch  410   k  via a line  413   c.    
         [0057]    The capacitor  407  is coupled to the switch  410   q  via a line  413   d , and the capacitor  409  is coupled to the switch  410   m  via a line  413   e , and to the switch  410   h  via a line  413   f.    
         [0058]    As can be further seen in  FIG. 4 , the switch  410   o  is coupled to the switch  410   f  via a line  414   a , and to the switch  410   c  and the switch  410   m  via a line  414   b.    
         [0059]    Correspondingly, the switch  410   q  is coupled to the switch  410   h  via a line  414   c , and to the switch  410   c  and the switch  410   k  via a line  414   d.    
         [0060]    Switches  410   a - d  are operated in a way analogous to the prior art switch-capacitor circuit  100  of  FIG. 1  (in particular, the corresponding switches  108   a ,  108   b  (which correspond to switches  410   a - c ), and the switch  108   c  (which corresponds to switch  410   d )), that is to say they are operated during non-overlapping clock-phases phi( 1 ) (switches  410   a - c ) and phi( 2 ) (switch  410   d ). 
         [0061]    Switches  410   e - m  are operated during non-overlapping clock-phases phi(x) (switches  410   e - h ) and phi(y) (switches  410   i - m ). The operation frequency of these switches is half that of phi( 1 ) and phi( 2 ). 
         [0062]    For reasons of symmetry, the capacitor  406  may be connected by switches  410   n,o  to the circuit  400 , and the capacitor  407  may be connected by switches  410   p,q  to the circuit  400 . These switches can be always left on or be operated on phi(x) or phi(y). 
         [0063]    At the beginning of phi( 1 ), in addition to the switches  410   a - c , the switches  410   e ,  410   f ,  410   g ,  410   h  are also being operated (beginning of phi(x)), but not the switches  410   i ,  410   k ,  410   l ,  410   m . Thus, during phi( 1 ), capacitors  406  and  408  are connected in parallel and are both charged to a first voltage V 1 , while capacitors  407  and  409  are connected in parallel and are both charged to a second voltage V 2 , wherein the second voltage V 2  has the same absolute value than the first voltage V 1 , but is opposite in sign. 
         [0064]    During phi( 2 ), the voltages V 1  and V 2  existing across capacitors  406 ,  408  and capacitors  407 , 409 , respectively, remain constant, since all capacitors  406 - 409  are disconnected from the voltage sources  402 ,  403  and the resistances  404 ,  405 , while the voltage sources  402  and  403  change their output voltages without any impact on the capacitors  406 - 409  during phi( 2 ) being disconnected from these. 
         [0065]    Then, at a new beginning of phi( 1 ), in addition to the switches  410   a - c , the switches  410   i ,  410   k ,  410   l ,  410   m  are also being operated (beginning of phi(y)), but not the switches  410   e ,  410   f ,  410   g ,  410   h . Therefore, during phi(y), capacitors  406  and  409  are connected in parallel and also capacitors  407  and  408  are connected in parallel. Since the capacitors  406  and  409  ( 407  and  408 ) are oppositely charged and their net voltage is zero, the capacitors  406  and  409  ( 407  and  408 ) are completely discharged. The respective discharge paths do not go through the resistances  404 ,  405 , but go from capacitor  406  to capacitor  409  and from capacitor  407  to capacitor  408 , respectively, and are therefore very fast. 
         [0066]    As, during phi( 1 ), the capacitors  406  and  409  are now connected with the voltage source  402 , which has changed its output voltage during the last phi( 2 ), the capacitors  406  and  409  are charged with a third voltage V 3 . Similarly, as, during phi( 1 ), the capacitors  407  and  408  are connected with the voltage source  403 , which has also changed its output voltage during the last phi( 2 ), the capacitors  407  and  408  are charged with a fourth voltage V 4 , wherein the voltage V 4  has the same absolute value as the voltage V 3 , but is opposite in sign. 
         [0067]    During phi( 2 ), the voltages V 3  and V 4  existing across capacitors  406 ,  409  and capacitors  407 ,  408 , respectively, remain constant, since all capacitors,  406 - 409  are disconnected from the voltage sources  402 ,  403  and the resistances  404 ,  405 , while the voltage sources  402  and  403  change their output voltages without any impact on the capacitors  406 - 409  during phi( 2 ) being disconnected from these. 
         [0068]    Then, at a further new beginning of phi( 1 ), in addition to the switches  410   a - c , the switches  410   e ,  410   f ,  410   g ,  410   h  are also being operated (beginning of phi(x)), but not the switches  410   i ,  410   k ,  410   l ,  410   m . Now, capacitors  406  and  408  are connected in parallel and also capacitors  407  and  409  are connected in parallel. Since capacitors  406  and  408  ( 407  and  409 ) are oppositely charged and their net voltage is zero, capacitors  406  and  408  ( 407  and  409 ) are completely discharged. At this point, a full cycle has been carried out and the process described above starts anew. 
         [0069]    While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.