Abstract:
A decoder arrangement ( 10 ) includes a processor ( 12 ) programmed to decode multiple streams ( 111 - 11   n ), including multiple streams of different formats. In terms of functionality, the decoder arrangement includes a routing stage ( 13 ) routes each streams to different decoder stages ( 141 - 14   n ), each capable of decoding a stream of a particular format to yield an uncompressed stream at its output. Each of plurality of buffer stages ( 161 - 16   n ) stores a successive frame of an uncompressed stream output by an associated decoder stage. An output stage scales and the frames stored by the buffer stages to a common size for input to a display device ( 22 ).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 60/653,538, filed Feb. 16, 2005, the teachings of which are incorporated herein. 
     This application claims the benefit, under 35 U.S.C. §365 of International Application PCT/US2006/003520, filed Feb. 1, 2006 published in accordance with PCT Article 21(2) on Aug. 24, 2006 in English. 
    
    
     TECHNICAL FIELD 
     This invention relates to a decoder for decoding compressed streams. 
     BACKGROUND ART 
     Traditionally, video decoders have been hardware-based. In other words, typical video decoders take the form of discrete, stand-alone devices dedicated for this purpose. With hardware decoder implementations, decoding streams of different formats usually requires a different chipset for each stream type and relatively lengthy firmware downloads. Multiple chipsets can prove to be very costly and making firmware changes in real-time becomes impractical. 
     Thus a need exists for a decoder arrangement that overcomes the disadvantages of the prior art. 
     BRIEF SUMMARY OF THE INVENTION 
     Briefly, in accordance with a preferred embodiment of the present principles, there is provided a decoder for decoding at least first and second compressed streams. The decoder comprises first and second decoder stages, each capable of decoding a separate one of the at least first and second streams to yield first and second uncompressed streams, respectively. A routing stage routes the at least first and second streams to the at least first and second decoder stages, respectively. At least first and second buffer stages each store a separate one of the first and second uncompressed streams output by the first and second decoder stages. An output stage combines the uncompressed streams stored by the at least first and second buffer stages. 
     In practice, the decoder arrangement of the present principles comprises a processor programmed with software to perform the function of each of the decoder stages. Software decoders allow for a high degree of customization and afford greater flexibility and control over the decoding process. Source video material used in non-linear editors (NLEs) can come from different sources and can undergo compression in different formats, such as MPEG2, DV, JPG2K for example. The material also can have different presentation sizes, for instance, standard definition NTSC vs. high-definition 1080i. The decoder arrangement of the present principles can decode video streams regardless of their native compression format or image size by making use of decoder stages capable of decoding different formats. The decoder arrangement of the present principles can decompress frames of different formats and compose the uncompressed frames onto a common “canvas.” Further, with the availability of relatively inexpensive multiprocessor systems, the decoder arrangement of the present principles can execute on multiple parallel threads so that processing throughput can scale with the number and speed the available processors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a block schematic diagram of a decoder arrangement in accordance with a preferred embodiment of the present principles. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  depicts a block schematic drawing of a decoder arrangement  10  in accordance with a preferred embodiment of the present principles for uncompressing a plurality of compressed video streams  11   1 - 11   n , where n is an integer greater than zero. In practice, one or more of the video streams  11   1 - 11   n  can have a different format from the others. For example, one of the streams can take the form of an MPEG 2 stream, while another stream could take the form of a DV25 or DV50 stream. The particular format of each stream remains unimportant, as long as the particular format of the stream is known a priori. 
     In practice the decoder  10  of the present principles comprises a programmed processor  12 , such as a microprocessor, microcomputer or the like, which operates in stages as described in greater detail below. When programmed to operate as a software decoder, the processor  12  will possess an input routing stage  13  that routes the compressed video streams  11   1 - 11   n  to an appropriate one of a plurality of decoder stages  14   1 - 14   n  depending of the compression format of the incoming stream. Each of decoder stages  14   1 - 14   n  operates to de-compress an incoming of a particular format. Typical compression formats include MPEG 2, DV25, and DV50 for standard definition (SD) video, and MPEG 2, H.264-MPE4 AVC and D 100 for high definition video. Thus, depending on the composition of the compressed video streams  11   1 - 11   n , one or more of the decoder stages  14   1 - 14   n  will have the capability of de-compressing video in one of the MPEG 2, DV25, and DV50 SD formats or in one of the MPEG 2, H.264-MPE4 AVC and DV 100 HD formats. 
     Upon receipt of an incoming one of the streams  11   1 - 11   n  of a specific compression format, a decoder stage associated with that format will decode the stream to yield successive uncompressed frames. Each uncompressed frame output by a decoder stage undergoes storage in a corresponding one of presentation buffer stages  18   1 - 18   n , respectively, sized to receive the uncompressed frame. In practice, each of the presentation buffer stages  18   1 - 18   n  holds a frame of a particular size which depends on the decompression format of its associated decoding stage. Typically, each of the presentation buffer stages  18   1 - 18   n  will have one of the following standard sizes: 
     NTSC (720×480) 
     PAL (720×576) 
     1080i (1920×1080) 
     720p (1280×720) 
     Uncompressed SD frames will typically conform to either the NTSC or PAL format. Uncompressed HD frames, depending on their size, will undergo storage in a buffer stage capable of accommodating 1080i or 720p HD frames. If a decoded frame image does not conform to size of a presentation buffer stage, as can occur with some MPEG 2 video frames, the frame undergoes a clipping or cropping operation. For example, a 720×512 MPEG 2 frame will have 32 lines clipped before placed in presentation buffer stage. 
     A scaler  20  scales the frames read from each of the presentation buffer stages  18   1 - 18   n  and also performs the required color space conversion associated with a video display renderer  22 . For example, if the video display renderer  22  has an input frame size of 1920×1080 pixels associated with 1080i HD frames, the scaler  20  will scale all frames to that size. Any frames smaller than 1920×1080 pixels will undergo up-conversion by the scaler  20 . Conversely, if the video display renderer  22  has an input frame size of 720×480 pixels, then the scaler  20  will down-convert larger size frames. 
     The decoder arrangement  10  of  FIG. 1  improves efficiency by affording temporal parallelism. With software-based decoder arrangements, reading the compressed video stream can involve time spent with disk access. Additionally, writing frames of the uncompressed output stream typically will involve time spent performing bus transfers to display hardware. Waiting for to complete such input/output (I/O) tasks to occur does not constitute an efficient use of processing cycles. The decoder arrangement  10  of the present principles makes use of the presentation buffers  18   1 - 18   n  to decouple the decoding stages  14   1 - 14   n  from the scaler  20  that performs the scaling and color space conversion. After a frame (N) undergoes decoding and storage in a presentation buffer, a decoder stage can decode the next frame (N+1) as the scaler  20  formats the now uncompressed frame (N) for output. A lock semaphore protects each presentation buffer stage to prevent one thread from overrunning the other. 
     As discussed above, the decoder arrangement  10  makes use of a processor  12  for executing a software based program for decoding a plurality of streams  11   1 - 11   n , typically, although not necessarily in serial fashion. Although  FIG. 1  depicts the processor  12  as being dedicated to the decoding task, the processor could perform other operations in addition to decoding. Although not explicitly depicted in  FIG. 1 , the processor  12 , when networked with other processors in a large system, could detect the number of other of processors available. If another processor besides processor  12  becomes available, then spatial parallelism becomes automatically enabled. Most video compression algorithms process an individual frame using a series of smaller sub-picture areas called macroblocks. The total number of macroblocks blocks can be divided among the available processors by creating multiple threads of execution. If the number of blocks for each processor remains less than the total number of blocks requiring decoding, then the time required to decode each frame is less. When using this method, each thread of execution is synchronized at the end of each frame to prevent image tearing. 
     The software-based decoding arrangement  10  affords several advantages are compared to stand-alone hardware decoders. For example, the decoder arrangement  10  can expand easily to support new compression standards as they become available since all that becomes necessary is a software update. In addition, individual 3 rd -party CODEC components can be replaced if faster or better substitutes are found. Further, the decoder arrangement  10  can switch compression types on a video frame boundary, typically every 33 ms at NTSC rates and 40 ms at PAL rates to provide seamless decoding operations for all supported compression formats. 
     The foregoing describes a decoder arrangement for decoding video streams of different formats.