Abstract:
An electronic device including a host system including a source; and a target system operably coupled to the host system via a combined power I/O line; wherein the target system includes a pass transistor and a switching system cooperative to allow the source to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication.

Description:
TECHNICAL FIELD 
     The present disclosure relates to power and communications connections for electronic devices. In particular the present disclosure relates to combined power and input/output lines. 
     BACKGROUND 
     In the field of mobile devices, such as cellular telephone and Blackberries, a small form factor is an increasingly important design consideration. Such devices typically include battery packs having power lines and input/output lines. In some instances, however, the small form factor of battery packs makes it difficult to provide sufficient pins for communicating. 
     Accordingly, it is known to provide a combined power and input/output pin or pins on an integrated circuit or other device. Such solutions typically include a diode and capacitor or a resistor and capacitor to extract power and store it for the device. 
     The diode-capacitor solution, however, has proven to be disadvantageous in low voltage systems. More particularly, in such systems, the diode drop may be insurmountable. 
     The resistor-capacitor solution is disadvantageous owing to baud rate and power consumption contention. That is, low power consumption requires large resistors which require longer on-times and lower baud rates which increase power consumption. 
     As such, there is a need for a system and method for minimizing the pins for communicating between a power supply and target device. In particular, there is a need for an improved combined power and input/output solution. 
     SUMMARY 
     An electronic device includes a host system having a source of a current; and a target system operably coupled to the host system via a combined power I/O line; wherein the target system includes a pass transistor and a switching system cooperative to allow the source to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication. 
     A method for providing power and I/O on a single line according to embodiments includes driving a combined I/O power line to charge a power supply capacitor in a first mode; and alternately connecting and disconnecting a pass transistor to charge and discharge the power supply capacitor during a communication over the combined I/O power line in a second mode. 
     A combined power and input/output system according to embodiments includes a host system; and a target system operably coupled to the host system via a combined power and I/O line; wherein the host system is configured to charge a power supply capacitor in the target system in a first mode via the combined power and I/O line and communicate via the combined power and I/O line in a second mode. 
     Additional objects and advantages of the present invention will become apparent to one skilled in the art upon reading and understanding exemplary embodiments described herein with reference to the following drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings accompanying and forming part of this specification are included to depict certain aspects of the disclosure. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. A more complete understanding of the disclosure and the advantages thereof may be acquired by referring to the following description, taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein: 
         FIG. 1  is a block diagram of a system according to an embodiment of the invention. 
         FIG. 2  is a timing diagram illustrating operation of the circuit system of  FIG. 1 . 
         FIG. 3A-FIG .  3 E illustrate exemplary switching controls according to embodiments of the invention. 
         FIG. 4  is a circuit diagram illustrating an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The disclosure and various features and advantageous details thereof are explained more fully with reference to the exemplary, and therefore non-limiting, embodiments illustrated in the accompanying drawings and detailed in the following description. Descriptions of known programming techniques, computer software, hardware, operating platforms and protocols may be omitted so as not to unnecessarily obscure the disclosure in detail. It should be understood, however, that the detailed description and the specific examples, while indicating the preferred embodiments, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those skilled in the art from this disclosure. 
     As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, product, article, or apparatus that comprises a list of elements is not necessarily limited only those elements but may include other elements not expressly listed or inherent to such process, process, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present). 
     Additionally, any examples or illustrations given herein are not to be regarded in any way as restrictions on, limits to, or express definitions of, any term or terms with which they are utilized. Instead these examples or illustrations are to be regarded as being described with respect to one particular embodiment and as illustrative only. Those of ordinary skill in the art will appreciate that any term or terms with which these examples or illustrations are utilized encompass other embodiments as well as implementations and adaptations thereof which may or may not be given therewith or elsewhere in the specification and all such embodiments are intended to be included within the scope of that term or terms. Language designating such non-limiting examples and illustrations includes, but is not limited to: “for example,” “for instance,” “e.g.,” “in one embodiment,” and the like. 
     Turning now to the drawings and, with particular attention to  FIG. 1 , a diagram illustrating an exemplary combination power supply input/output system  100  is shown. As will be explained in greater detail below, embodiments use a fixed on-time for an input/output pin drive, which allows rapid output transitions and minimizes the effects of bus contention.  FIG. 2  illustrates an exemplary timing diagram for operation of the circuit of  FIG. 1 . 
     In the embodiment illustrated, a host system  104  is in communication with a target system  102 . The host system may include a source  134 , transmitter  126 , receiver  128 , and switches  130 ,  132 . The switches  130 ,  132  may be embodied as, for example, switching transistors. The host system  104  couples via a line  122  to the target system  102 . The source  134  may be a current source or a voltage source. Thus, the figures are exemplary only. In operation, the switches  130 ,  132  function to switch the current from the source  134  or the transmitter  126  or receiver  128  to drive the host line  122 . 
     In particular, in a first or power mode, the host system  104  will drive the host line  122  high for a few milliseconds using the source  134 . As seen at time  202   a  ( FIG. 2 ), this causes the voltage Vdd  208  to ramp up and gives the target system  102  enough time to be powered by the parasitic diode present in the pass transistor  108 . When sufficient voltage is present on the Vdd power supply capacitor  106 , the pass transistor  108  will become active and the charge rate will increase, as shown at  208   a . The output of OR gate  114 , rectifier drive  115 , follows the host at  206   a.    
     After some time passes, as shown at  206   b , the target device  102  will disconnect the pass transistor  108 , allowing the host system  104  to begin communications without discharging the target power. 
     The bit stream from the host  104  on line  122  is shown at  202   b . During this communications mode input phase, the target system  102  will assert the pass transistor  108  for a short period after each rising edge from the host  122 . That is, as shown at  209   a - 209   e , rectifier drive  206   c  is high for a brief period, corresponding to the assertion of the pass transistor  108 . 
     This provides an opportunity for the Vdd capacitor  106  to charge up a little during each data bit, as shown for example, at  208   b . As can be appreciated, the maximum baud rate is dictated by the on period of the pass transistor  108 . 
     When the host  104  is finished transmitting, it is possible for the target  102  to communicate in an output phase with the host  104  as shown at  204  by pulling the host power line  122  low during each bit, as shown at  204   a . When the target is not pulling the power line  122  low, it can assert the pass transistor  108  for the entire high portion of the data bit, i.e., rectifier drive  115  via transistor  112 . This synchronization is possible because the target knows the entire duration of each data bit. 
     A software override of the pass transistor  108  can be provided to allow software to force power to be available for a high current activity such as writing to an EEPROM. When the host/target communications are complete, the host can disable the power connection and the target Vdd will decay at  208   c  until the target is powered off. Further details of a power boost circuit implementation are described in commonly assigned, co-pending U.S. patent application Ser. No. 13/841,829, filed concurrently herewith, and which is hereby incorporated by reference in its entirety as if fully set forth herein. 
     Several embodiments of a pass transistor circuit are illustrated in  FIG. 3A-FIG .  3 E. In each case, a host  122  provides power via a pass transistor  108  to charge voltage Vdd  124 . Depending on the embodiment, it can be a switch control  302  ( FIG. 3A ), tristate  304  ( FIG. 3B ), transistor  306 , or combinations thereof,  308 ,  310 . 
     A combined power supply input/output system in accordance with an embodiment of the invention is illustrated in greater detail in  FIG. 4 . In the embodiment illustrated, a microcontroller (MCU)  408  acts as the host system and couples via an I/O port  404  to a target system  400 . The target system  400  includes pass transistor  434  and switching system  470 , as well an input system  460 . 
     A power supply capacitor  440  couples to target system  400  and pass transistor  434  via port  402 . I/O line  439  couples I/O port  404  to RX  412  and TX  414  I/O and to the power supply capacitor  440  via pass transistor  434 . The MCU  408  provides host system I/O and a source of current (not shown) to charge the power supply capacitor in a manner similar to that discussed above. 
     In operation, the switching system  470  and pass transistor  434  cooperate to allow for I/O operations and power supply operations. Switching system  470  includes AND gate  436  and weak FET  437  and FET  438 . One input of the AND gate  436  is provided by multiplexer  426  of the input system  460  while the other is from a “Strong Drive Enable.” 
     The input system  460  includes OR gate  432  which can receive SLEEP and RESET inputs, as well as an input from multiplexer  430 . The SLEEP and RESET inputs allow the capacitor to charge at full speed by enabling transistor  437  during these conditions. When the device wakes, active control of transistor  437  can resume. 
     The input system  460  includes common TX/RX lines  410 / 412  enabling the data received or transmitted to control the pass transistor  434 . When the line power line is not low, this connection allows capacitor  440  to be recharged as quickly as possible. The input system  460  includes a multiplexer  416  that allows multiple peripherals or software to be used to control the entire system. Other possible peripherals that would be suitable include a PWM or Manchester encoders. 
     The output of multiplexer  416  is provided via lines  423  and  422  as inputs to multiplexer  430 , 426  respectively. In addition the output of  416  is provided via lines  426 ,  426  to one shots  419 , 429  respectively, as the other inputs to the multiplexers  430 , 426 . A pulse timer  420  controls the operation of the one shots  419 ,  429 . The inputs to the multiplexers are selected using the short drive high and short drive low signals. 
     This provides the option to control the pass transistor  434  with either a short pulse to recharge the capacitor  440  or a continuous pulse to the capacitor  440 . For high speed signals low current applications it is likely more appropriate to control the pass transistor  434  with short fixed pulses and prevent the possibility of discharging the capacitor  440  by having both transistor  434  and the host pull down transistor active at the same time. For low speed high current applications this risk is minimized and it may be more appropriate to allow for a longer charge time. Additionally pulse timer  420  is available to program the duration of the recharge pulse in multiples of the clock signal FOSC. 
     In some embodiments, the supplied voltage from the host ( 408 ) may be at a lower than desired operating voltage. In this case, a simple boost power supply can be constructed from an external inductor (unlabeled) and internal boost power supply transistor  400 . This boost supply could be synchronous by using the additional rectifying transistor (unlabeled) or this could be a asynchronous by using a diode in place of the rectifying transistor. 
     Although the foregoing specification describes specific embodiments, numerous changes in the details of the embodiments disclosed herein and additional embodiments will be apparent to, and may be made by, persons of ordinary skill in the art having reference to this description. In this context, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of this disclosure. Accordingly, the scope of the present disclosure should be determined by the following claims and their legal equivalents.