Abstract:
The present application relates to a light emission control and scan driver and a display device having the drivers. A light emission control and scan driver includes a plurality of driver stages for outputting light emission control signals and scan signals, each of which including: a light emission control driving unit for providing control signals to the scan units and a scan driving unit. Control signals may be light emission control signals. The light emission control driving unit has a first input signal terminal, a first clock terminal, a second clock terminal and a light emission control output terminal, and outputs light emission control signals at the light emission control output terminal based on input signals input at the first input signal terminal, light emission timing control signals input at the first clock terminal and inverted light emission timing control signals input at the second clock terminal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims benefits of Chinese Patent Application No. 201410142701.9, filed on Apr. 10, 2014 in the State Intellectual Property Office of China, the disclosure of which is incorporated herein by reference in its entirety. 
       TECHNICAL FIELD  
       [0002]    The present disclosure relates to a display device, particularly to a light emission control driver, a light emission control and scan driver and a display device having the driver. 
       BACKGROUND ART  
       [0003]    Organic light emitting diode (OLED) display devices, as a new generation of display device technology, have advantages of self luminescence, large viewing angle, high contrast, low power consumption, high response speed, high resolution, full colors and thin form factor. AMOLED might be one of future potential main stream display device technologies. 
         [0004]    As shown in  FIG. 1 , a conventional OLED display device includes a scan driver  10 , a data driver  20 , a light emission control driver  30  and a pixel array  40 . The pixel array  40  has a plurality of pixels  50 , which are connected to scan lines S 1  to Sn, data lines D 1  to Dm and light emission control lines E 1  to En respectively. The scan driver  10  is configured to provide scan signals to scan lines S 1  to Sn successively, the data driver  20  is configured to provide data signals to data lines D 1  to Dm, while the light emission control driver is configured to provide light emission control signals to light emission control lines E 1  to En. 
         [0005]    When scan signals are supplied to scan lines successively, pixel rows connected with scan lines are selected. Accordingly, the selected pixels receive data signals (data voltages) from data lines. The data voltages control currents flowing from the power supply ELVDD to the OLEDs, and hence control the OLEDs to generate light with corresponding luminance, and thereby display images. The duration for a pixel to emit light is controlled by a light emission control signal from a light emission control line. 
         [0006]    The scan driver  10 , the data driver  20  and the light emission control driver  30  are controlled by a timing controller  60 . The timing controller  60  may provide scan driving control signals (SDS) to the scan driver  10 , provide data driving control signals (DDS) to the data driver  20 , and provide light emission driving control signals (EDS) to the light emission control driver  30 . The timing controller  60  can control the pulse width and/or the number of pulses of the light emission control signals output from the light emission control driver  30  by controlling the light emission driving control signals (EDS). 
         [0007]    According to a conventional design, the scan driver  10  and the light emission control driver  30  are driven by different control timing signals respectively and independently. It is desired to have an effective simplified circuit design to reduce TFT elements and/or control timing signals required by the circuit. 
         [0008]    The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not form the prior art that is already known in this country to the person of ordinary skill in the art. 
       SUMMARY OF INVENTION  
       [0009]    The present application discloses a light emission control driver, a light emission control and scan driver and an organic light emitting display device having the drivers that can effectively simplify circuit design and reduce TFT elements and/or control timing signals required by the circuit. 
         [0010]    Other features and advantages of the present disclosure will become apparent through the following detail description or will be partially learned by practicing the present disclosure. 
         [0011]    According to an aspect of the present disclosure, there is provided a light emission control and scan driver comprising a plurality of driver stages for outputting light emission control signals and scan signals. Each driver stage may comprise: 
         [0012]    a light emission control driving unit having a first input signal terminal, a first clock terminal, a second clock terminal and a light emission control output terminal and configured to output light emission control signals at the light emission control output terminal based on input signals input at the first input signal terminal, light emission timing control signals input at the first clock terminal and inverted light emission timing control signals input at the second clock terminal. The inverted light emission timing control signals are inverted signals of the light emission timing control signals; and 
         [0013]    a scan driving unit having a second input signal terminal, a third clock terminal, a fourth clock terminal and at least one scan output terminal and configured to output at least one scan signal at the at least one scan output terminal according to control signals based on the light emission control signals of the light emission control driving unit input at the second input signal terminal, first scan timing control signals input at the third clock terminal and second scan timing control signals input at the fourth clock terminal. 
         [0014]    For example, the control signals are the light emission control signals. 
         [0015]    For example, the light emission control driving unit comprises a first controlled inverter, a second controlled inverter and a third inverter. Each of the first controlled inverter and the second controlled inverter comprises a first input terminal, a second input terminal, a third input terminal and an output terminal, and the first controlled inverter and the second controlled inverter are configured that: when the second input terminal is at low level and the third input terminal is at high level, the first controlled inverter and the second controlled inverter are turned on and output signals at the output terminal with reversed phases to signals at the first input terminal, and when the second input terminal is at high level and the third input terminal is at low level, the first controlled inverter and the second controlled inverter are turned off. The first input terminal, the second input terminal and the third input terminal of the first controlled inverter are respectively electrically coupled to the output terminal of the third inverter, the second clock terminal and the first clock terminal, and the output terminal of the first controlled inverter is electrically coupled to the input terminal of the third inverter. The first input terminal, the second input terminal and the third input terminal of the second controlled inverter are respectively electrically coupled to the first input signal terminal, the second clock terminal and the first clock terminal of the light emission control driving unit, and the output terminal of the second controlled inverter is electrically coupled to the input terminal of the third inverter. 
         [0016]    For example, the output terminal of the third inverter is directly or indirectly electrically coupled to the light emission control output terminal of the light emission control driving unit. 
         [0017]    For example, each of the first controlled inverter and the second controlled inverter comprises: a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors. A source node of the second transistor and a drain node of the third transistor are electrically coupled to the output terminal, gate nodes of the second transistor and the third transistor are electrically coupled to the first input terminal, a drain node of the second transistor is electrically coupled to a source node of the first transistor, and a source node of the third transistor is electrically coupled to a drain node of the fourth transistor. A drain node of the first transistor is electrically coupled to a second power supply, and a gate node of the first transistor is electrically coupled to the third input terminal. A source node of the fourth transistor is electrically coupled to a first power supply, and a gate node of the fourth transistor is electrically coupled to the second input terminal. 
         [0018]    For example, the plurality of driver stages comprise a first driver stage to a nth driver stage and are configured such that the first input signal terminal of the first driver stage receives start pulse signals, and the first input signal terminals of other driver stages receive light emission control signals output from the light emission control output terminals of a previous driver stage. 
         [0019]    For example, the start pulse signal has a pulse width equal to or greater than that of the light emission timing control signal. 
         [0020]    For example, the scan driving unit comprises at least one output unit each comprising: 
         [0021]    a first output transistor having a source node electrically coupled to a first power supply, a drain node electrically coupled to one scan output terminal of the at least one scan output terminal and a gate node electrically coupled to the second input signal terminal, and configured to be turned on or off based on the control signals input at the second input signal terminal; 
         [0022]    a first output unit having an input terminal electrically coupled to one of the third clock terminal and the fourth clock terminal and an output terminal electrically coupled to the one scan output terminal, and configured to be turned on or off according to the control signals input at the second input signal terminal. 
         [0023]    For example, the first output unit is configured to output signals input at the input terminal while being turned on. 
         [0024]    For example, the first output unit comprises complementary second output transistor and third output transistor. A source node of the second output transistor and a source node of the third output transistor are electrically coupled to an input terminal of the first output unit, a drain node of the second output transistor and a drain node of the third output transistor are electrically coupled to an output terminal of the first output unit, a gate node of the second output transistor is configured to be electrically coupled to the control signals, and a gate node of the third output transistor is configured to be electrically coupled to an inverted signal of the control signal. 
         [0025]    For example, the scan driving unit comprises a fourth inverter, a first output transistor, a second output transistor, complementary third output transistor and fourth output transistor, complementary fifth output transistor and sixth output transistor, the at least one scan output terminal comprising a first scan output terminal and a second scan output terminal. An input terminal of the fourth inverter is electrically coupled to an output terminal of the third inverter. A source node of the first output transistor is electrically coupled to a first power supply, a drain node of the first output transistor is electrically coupled to the first scan output terminal, and a gate node of the first output transistor is electrically coupled to an output terminal of the third inverter. A source node of the second output transistor is electrically coupled to a first power supply, a drain node of the second output transistor is electrically coupled to the second scan output terminal, and a gate node of the second output transistor is electrically coupled to an output terminal of the third inverter. Source nodes of the third output transistor and the fourth output transistor are electrically coupled to each other and with the third clock terminal, drain nodes of the third output transistor and the fourth output transistor are electrically coupled to each other and with the first scan output terminal, a gate node of the third output transistor is electrically coupled to an output terminal of the third inverter, and a gate node of the fourth output transistor is electrically coupled to an output terminal of the fourth inverter. Source nodes of the fifth output transistor and the sixth output transistor are electrically coupled to each other and with the fourth clock terminal, drain nodes of the fifth output transistor and the sixth output transistor are electrically coupled to each other and with the second scan output terminal, a gate node of the fifth output transistor is electrically coupled to an output terminal of the third inverter, and a gate node of the sixth output transistor is electrically coupled to an output terminal of the fourth inverter. 
         [0026]    For example, for odd numbered driver stages, the first clock terminal and the second clock terminal are configured to receive the light emission timing control signals and the inverted light emission timing control signals respectively, and the third clock terminal and the fourth clock terminal are configured to receive the first scan timing control signals and the second scan timing control signals respectively. For even numbered driver stages, the first clock terminal and the second clock terminal are configured to receive the inverted light emission timing control signals and the light emission timing control signals respectively, and the third clock terminal and the fourth clock terminal are configured to receive the second scan timing control signals and the first scan timing control signals respectively. 
         [0027]    According to another aspect of the present disclosure, there is provided a light emission control driver comprising a plurality of driver stages for outputting light emission control signals. Each driver stage may comprise: 
         [0028]    a light emission control driving unit having a first input signal terminal, a first clock terminal, a second clock terminal and a light emission control output terminal and configured to output light emission control signals at the light emission control output terminal based on input signals input at the first input signal terminal, light emission timing control signals input at the first clock terminal and inverted light emission timing control signals input at the second clock terminal. The inverted light emission timing control signals are inverted signals of the light emission timing control signals. 
         [0029]    For example, the light emission control driving unit comprises a first controlled inverter, a second controlled inverter and a third inverter. Each of the first controlled inverter and the second controlled inverter comprises a first input terminal, a second input terminal, a third input terminal and an output terminal, and the first controlled inverter and the second controlled inverter are configured that: when the second input terminal is at low level and the third input terminal is at high level, the first controlled inverter and the second controlled inverter are turned on and output signals at the output terminal with reversed phases of signals at the first input terminal, and when the second input terminal is at high level and the third input terminal is at low level, the first controlled inverter and the second controlled inverter are turned off. The first input terminal, the second input terminal and the third input terminal of the first controlled inverter are respectively electrically coupled to the output terminal of the third inverter, the second clock terminal and the first clock terminal, and the output terminal of the first controlled inverter is electrically coupled to the input terminal of the third inverter. The first input terminal, the second input terminal and the third input terminal of the second controlled inverter are respectively electrically coupled to the first input signal terminal, the second clock terminal and the first clock terminal of the light emission control driving unit, and the output terminal of the second controlled inverter is electrically coupled to the input terminal of the third inverter. 
         [0030]    For example, the output terminal of the third inverter is directly or indirectly electrically coupled to the light emission control output terminal of the light emission control driving unit. 
         [0031]    For example, each of the first controlled inverter and the second controlled inverter comprises: a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors. A source node of the second transistor and a drain node of the third transistor are electrically coupled to the output terminal, gate nodes of the second transistor and the third transistor are electrically coupled to the first input terminal, a drain node of the second transistor is electrically coupled to a source node of the first transistor, and a source node of the third transistor is electrically coupled to a drain node of the fourth transistor. A drain node of the first transistor is electrically coupled to a second power supply, and a gate node of the first transistor is electrically coupled to the third input terminal. A source node of the fourth transistor is electrically coupled to a first power supply, and a gate node of the fourth transistor is electrically coupled to the second input terminal. 
         [0032]    For example, the plurality of driver stages comprise a first driver stage to a nth driver stage and are configured such that the first input signal terminal of the first driver stage receives start pulse signals, and the first input signal terminals of other driver stages receive light emission control signals output from the light emission control output terminals of a previous driver stage. 
         [0033]    For example, the start pulse signal has a pulse width equal to or greater than that of the light emission timing control signal. 
         [0034]    For example, for odd numbered driver stages, the first clock terminal and the second clock terminal are configured to receive the light emission timing control signals and the inverted light emission timing control signals respectively, and for even numbered driver stages, the first clock terminal and the second clock terminal are configured to receive the inverted light emission timing control signals and the light emission timing control signals respectively. 
         [0035]    According to another aspect of the present disclosure, there is provided a display device comprising: 
         [0036]    a pixel array comprising a plurality of pixels each comprising a pixel driving circuit and an organic light emitting diode and connected to scan lines, data lines, light emission control lines and power supplies, the pixel driving circuit being configured to receive data signals from the data lines and control driving currents supplied to the organic light emitting diodes; 
         [0037]    the light emission control and scan driver as describe above for providing scan signals to the scan lines and providing light emission control signals to the light emission control lines; and 
         [0038]    a data driver for providing data signals to the data lines. 
         [0039]    For example, the display device further comprises a timing controller for providing start pulse signals, light emission timing control signals, inverted light emission timing control signals, first scan timing control signals and second scan timing control signals to the light emission control and scan driver. 
         [0040]    For example, the pixel driving circuit is further connected to a previous scan line, and the light emission control and scan driver is further configured to provide scan signals to the previous scan line. 
         [0041]    According to the technical proposal of the present disclosure, it is possible to effectively simplify circuit designs and reduce TFT elements and/or control timing signals required by circuits. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0042]    The foregoing and other features and advantages of the disclosure will be apparent to those skilled in the art in view of the following detailed description, taken in conjunction with the accompanying drawings. 
           [0043]      FIG. 1  schematically shows an OLED display according to conventional implementation; 
           [0044]      FIG. 2  shows a block diagram of a light emission control and scan driver according to an illustrative embodiment of the present disclosure; 
           [0045]      FIG. 3  shows an illustrative embodiment of a light emission control driving unit of a driver stage of the light emission control and scan driver shown in  FIG. 2 ; 
           [0046]      FIG. 4  shows an illustrative embodiment of a scan driving unit of a driver stage of the light emission control and scan driver shown in  FIG. 2 ; 
           [0047]      FIG. 5  shows an illustrative timing diagram applicable to the driver stage circuit of the light emission control driving unit and the scan driving unit shown in  FIGS. 3 and 4 ; 
           [0048]      FIG. 6  shows an illustrative timing diagram for a light emission control and scan driver including four driver stages; 
           [0049]      FIG. 7  shows a circuit diagram of an illustrative embodiment of a controlled inverter in the illustrative driver stage shown in  FIG. 3 ; 
           [0050]      FIG. 8  shows a block diagram of a light emission control driver including a plurality of driver stages according to an illustrative embodiment of the present disclosure; 
           [0051]      FIG. 9  shows a display device according to an illustrative embodiment of the present disclosure; and 
           [0052]      FIG. 10  shows an illustrative embodiment for the pixel driving circuit of the display device shown in  FIG. 9 . 
       
    
    
     DETAILED DESCRIPTION  
       [0053]    Exemplary embodiments of the disclosure will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. Exemplary embodiments of the disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. 
         [0054]    The described features, structures, or/and characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are disclosed to provide the thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosure may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure. 
         [0055]    The present disclosure provides a novel driving circuit that integrates the light emission control driving circuit and the scan driving circuit to effectively simplify circuit design and the required control timing signals. 
         [0056]      FIG. 2  is a block diagram of a light emission control and scan driver  200  according to an illustrative embodiment of the present disclosure, which shows a driving circuit architecture according to the present disclosure. 
         [0057]    As shown in  FIG. 2 , the light emission control and scan driver  200  may include a plurality of driver stages  200 - 1 ,  200 - 2 ,  200 - 3  and  200 - 4 . It is easy to understand that the number of driver stages is not limited thereto. Each driver stage includes a light emission control driving unit and a scan driving unit. For example, the first driver stage  200 - 1  includes light emission control driving unit X 1  and scan driving unit X 5 . The second driver stage  200 - 2  includes light emission control driving unit X 2  and scan driving unit X 6 . The third driver stage  200 - 3  includes light emission control driving unit X 3  and scan driving unit X 7 . The fourth driver stage  200 - 4  includes light emission control driving unit X 4  and scan driving unit X 8 . 
         [0058]    The output of the light emission control driving unit may be input into the scan driving unit to control operation of the scan driving unit. 
         [0059]    In addition, it is easy to understand that the light emission control driving unit according to the present disclosure may be used separately to constitute a light emission control driver  400  including a plurality of driver stages, as shown in  FIG. 8 . 
         [0060]    The architecture of the light emission control driving unit and the scan driving unit according to the illustrative embodiment will be described below. 
         [0061]    The light emission control driving unit includes three input terminals and one output terminal, namely the first input signal terminal in, the first clock terminal ck 1 , the second clock terminal ck 2  and the light emission control output terminal out. 
         [0062]    The scan driving unit includes three input terminals and two output terminals, namely the second input signal terminal in 2 , the third clock terminal ck 3 , the fourth clock terminal ck 4 , the first scan output terminal out 1  and the second scan output terminal out 2 . 
         [0063]    The three input terminals in, ck 1  and ck 2  of the light emission control driving unit X 1  of the first driver stage  200 - 1  receive start pulse signal ste (namely the frame pulse signal with a period typically of 16.667 ms, see  FIG. 6 ), light emission timing control signal cke 1  and inverted light emission timing control signal cke 2  respectively. The output terminal outputs light emission control signal En 1  and is connected to the input signal terminal in 2  of the scan driving unit X 5  and the first input signal terminal of the light emission control driving unit X 2  of the next driver stage  200 - 2 . 
         [0064]    The input terminals ck 1 , ck 2  of the light emission control driving unit X 2  of the second driver stage  200 - 2  are connected to signals cke 2  and cke 1  respectively. The output terminal out outputs light emission control signal En 2  and is connected to the input signal terminal in 2  of the scan driving unit X 6  and the first input signal terminal of the light emission control driving unit X 3  of the next driver stage  200 - 3 . 
         [0065]    Connections for terminals ck 1  and ck 2  of light emission control driving unit X 3  of the third driver stage  200 - 3  are the same to that of X 1 , and X 3  outputs light emission control signal En 3 . Connections for terminals ck 1  and ck 2  of light emission control driving unit X 4  of the fourth driver stage  200 - 4  are the same to that of X 2 , and X 4  outputs light emission control signal En 4 , and so on. That is, for every two driver stages, connection manners of clock signals are repeated for the light emission control driving unit. 
         [0066]    The input terminal in 2  of scan driving unit X 5  of the first driver stage  200 - 1  is connected to the output terminal of light emission control driving unit X 1  of the same stage. The third clock terminal ck 3  and the fourth clock terminal ck 4  are connected to the first and second scan timing control signals ckv 1  and ckv 2  respectively. Output terminals out 1  and out 2  output scan signals G 1   n  and G 1 . 
         [0067]    The input terminal in 2  of scan driving unit X 6  of the second driver stage  200 - 2  is connected to the output terminal of light emission control driving unit X 2 . The third clock terminal ck 3  and the fourth clock terminal ck 4  are connected to signals ckv 2  and ckv 1  respectively. Output terminals out 1  and out 2  output signals G 2   n  and G 2 . 
         [0068]    Connections for the third clock terminal ck 3  and the fourth clock terminal ck 4  of scan driving unit X 7  of the third driver stage  200 - 3  are the same to that of X 5 , and X 7  outputs scan signals G 3   n  and G 3 . Connections for the third clock terminal ck 3  and the fourth clock terminal ck 4  of scan driving unit X 8  of the fourth driver stage  200 - 4  are the same to that of X 6 , and X 8  outputs scan signals G 4   n  and G 4 , and so on. That is, for every two driver stages, connection manners of clock signals are repeated for the scan driving unit. 
         [0069]      FIG. 3  shows an illustrative embodiment of a light emission control driving unit  200 - 1   a  of a driver stage of the light emission control and scan driver in  FIG. 2 . 
         [0070]    Referring to  FIG. 3 , the light emission control driving unit  200 - 1   a  includes a first controlled inverter Y 1 , a second controlled inverter Y 2  and a third inverter Y 3 . 
         [0071]    The first controlled inverter Y 1  and the second controlled inverter Y 2  are inverters controlled by clock signals and each includes a first input terminal in 3 , a second input terminal in_p, a third input terminal in_n and an output terminal out 3 . When the second input terminal in_p is at low level and the third input terminal in_n is at high level, the controlled inverter is turned on, and the output terminal out 3  outputs a signal with reversed phase to the signal at the first input terminal in 3 . On the contrary, when the second input terminal in_p is at high level while the third input terminal in_n is at low level, the controlled inverter is shut down. 
         [0072]    The three input terminals in 3 , in_p and in_n of the second controlled inverter Y 2  are electrically coupled to the first input signal terminal in, the first clock terminal ck 1  and the second clock terminal ck 2  respectively. For the first driver stage, the input terminal in 3  may receive the start pulse signal ste. For other driver stages, the input terminal in 3  may receive the output signal from the light emission control output terminal of the previous driver stage. Input terminals in_p and in_n may receive light emission timing control signal cke 1  and inverted light emission timing control signal cke 2  respectively. The output terminal out 3  of the second controlled inverter Y 2  is connected to node n 1 . 
         [0073]    The input terminal in 4  of the third inverter Y 3  is connected to node n 1 . Y 3  outputs control signal at the output terminal out 4  with reversed phase to signal at node n 1 . The output terminal out 4  of the third inverter Y 3  is electrically coupled to the light emission control output terminal out. 
         [0074]    The input terminal in 3  of the first controlled inverter Y 1  is electrically coupled to the output terminal of the third inverter Y 3 , and input terminals in_p and in_n are electrically coupled to the second clock terminal ck 2  and the first clock terminal ck 1  respectively and may receive signal cke 2  and cke 1  respectively. The output terminal out 3  of the first controlled inverter Y 1  is electrically coupled to node n 1 . 
         [0075]    The output signal of the light emission control driving unit  200 - 1   a  may be input into the scan driving unit to control operation of the scan driving unit. 
         [0076]      FIG. 4  shows an illustrative embodiment of a scan driving unit  200 - 1   b  of a driver stage of the light emission control and scan driver in  FIG. 2 . 
         [0077]    Referring to  FIG. 4 , the scan driving unit  200 - 1   b  includes a fourth inverter Y 4 , a first output transistor M 1 , a second output transistor M 2 , a fourth output transistor M 4 , a third output transistor M 3 , a sixth output transistor M 6  and a fifth output transistor M 5 . The first output transistor M 1 , the second output transistor M 2 , the third output transistor M 3  and the fifth output transistor M 5  may be for example PMOS transistors, while the fourth output transistor M 4  and the sixth output transistor M 6  may be for example NMOS transistors. However, the present invention is not limited thereto. 
         [0078]    The input terminal in 4  of the fourth inverter Y 4  is electrically coupled to the output terminal out 4  of the third inverter Y 3 . The fourth inverter Y 4  outputs signals with reversed phase to signals of input terminal in 4 . 
         [0079]    Source nodes of the fourth output transistor M 4  and the third output transistor M 3  are electrically coupled to each other and with the third clock terminal ck 3 , and can receive the first scan timing control signal ckv 1 . Drain nodes of the fourth output transistor M 4  and the third output transistor M 3  are electrically coupled to each other and with the first scan output terminal out 1 . Gate node of the fourth output transistor M 4  is electrically coupled to output terminal out 4  of the third inverter Y 3 . Gate node of the third output transistor M 3  is electrically coupled to output terminal out 4  of the third inverter Y 4 . 
         [0080]    The fourth output transistor M 4  and the third output transistor M 3  may constitute an output unit that is turned on or off depending on signals output from the output terminal out 4  of the third inverter Y 3 . It is easy to understand that the present disclosure is not limited thereto. The output unit may also be implemented in other ways. For example, the fourth output transistor M 4  or the third output transistor M 3  may also constitute the output unit by itself. 
         [0081]    Similarly, source nodes of the sixth output transistor M 6  and the fifth output transistor M 5  are electrically coupled to each other and with the fourth clock terminal ck 4 , and can receive the second scan timing control signal ckv 2 . Drain nodes of the sixth output transistor M 6  and the fifth output transistor M 5  are electrically coupled to each other and with the second scan output terminal out 2 . Gate node of the sixth output transistor M 6  is electrically coupled to output terminal of the third inverter Y 3 . Gate node of the fifth output transistor M 5  is electrically coupled to output terminal of the fourth inverter Y 4 . 
         [0082]    Source node of the first output transistor M 1  may be electrically coupled to the power supply VDD. Drain node of the first output transistor M 1  may be electrically coupled to the first scan output terminal out 1 . Gate node of the first output transistor M 1  may be electrically coupled to output terminal out 4  of the third inverter Y 3 . 
         [0083]    Source node of the second output transistor M 2  may be electrically coupled to the power supply VDD. Drain node of the second output transistor M 2  may be electrically coupled to the second scan output terminal out 2 . Gate node of the second output transistor M 2  may be electrically coupled to output terminal out 4  of the third inverter Y 3 . 
         [0084]    Operations of the light emission control driving unit and the scan driving unit according to illustrative embodiments of the present disclosure will be described below with reference to timing diagrams. 
         [0085]      FIG. 5  shows an illustrative timing diagram applicable to the driver stage circuit of the light emission control driving unit and the scan driving unit shown in  FIGS. 3 and 4 . 
         [0086]    The following description is presented with the first driver stage  200 _ 1  as an example. However, it is easy to understand the following description is also applicable to other driver stages. Specifically, for the first driver stage, the first input terminal in may receive the start pulse signal ste. For other driver stages, the input terminal in may receive the output signal of the light emission control output terminal of the previous driver stage. For odd numbered driver stages, the first clock terminals ck 1  and the second clock terminals ck 2  can receive light emission timing control signals cke 1  and inverted light emission timing control signals cke 2  respectively, and the third clock terminals ck 3  and the fourth clock terminals ck 4  can receive the first scan timing control signals ckv 1  and the second scan timing control signals ckv 2  respectively. For even numbered driver stages, the first clock terminals ck 1  and the second clock terminals ck 2  can receive inverted light emission timing control signals cke 2  and light emission timing control signals cke 1  respectively, and the third clock terminals ck 3  and the fourth clock terminals ck 4  can receive the second scan timing control signals ckv 2  and the first scan timing control signals ckv 1  respectively. 
         [0087]    Referring to  FIGS. 3 to 5 , in the first time interval T 1 , the input signal of the first input signal terminal is at high level, the light emission timing control signal cke 1  is at low level, and the inverted light emission timing control signal cke 2  is at high level. Therefore, the terminal in_p of the first controlled inverter Y 1  is at high level, the terminal in_n is at low level. The terminal in_p of the second controlled inverter Y 2  is at low level and the terminal in_n is at high level. As such, the first controlled inverter Y 1  is turned off, and the second controlled inverter Y 2  is turned on. 
         [0088]    Therefore, the output of the second controlled inverter Y 2  is an inverted signal of the input signal, that is, node n 1  is at low level. 
         [0089]    The output of the third inverter Y 3  is at high level, that is, the output signal of the light emission control output terminal out (referring to  FIGS. 2 and 6 , En 1 ) is at high level. The output of the fourth inverter Y 4  is at low level. 
         [0090]    Since gate nodes of the first output transistor M 1  and the second output transistor M 2  are electrically coupled to the output terminal of the third inverter Y 3 , the first output transistor M 1  and the second output transistor M 2  are turned off. 
         [0091]    Since gate nodes of the fourth output transistor M 4  and the sixth output transistor M 6  are electrically coupled to output terminal of the third inverter Y 3 , gate nodes of the third output transistor M 3  and the fifth output transistor M 5  are electrically coupled to the output terminal of the fourth inverter Y 4 , output transistors M 3 , M 4 , M 5 , and M 6  are turned on. As a result, the first scan output terminal out 1  outputs the first scan timing control signal ckv 1 , that is out 1 =ckv 1 ; while the second scan output terminal out 2  outputs the second scan timing control signal ckv 2 , that is out 2 =ckv 2 . That is, referring to  FIGS. 2 and 6 , output signals G 1   n  and G 1  are the first scan timing control signal ckv 1  and the second scan timing control signal ckv 2  respectively. 
         [0092]    In the second time interval T 2 , the input signal of the first input signal terminal in is at low level, the light emission timing control signal cke 1  is at high level, and the inverted light emission timing control signal cke 2  is at low level. Therefore, the terminal in_p of the first controlled inverter Y 1  is at low level, the terminal in_n is at high level, the terminal in_p of the second controlled inverter Y 2  is at high level and the terminal in_n is at low level. As such, the first controlled inverter Y 1  is turned on, and the second controlled inverter Y 2  is turned off. The third inverter Y 3  and the first inverter Y 1  form a locking loop to keep n 1  at low level. The light emission control output terminal out is maintained at high level. The output of the fourth inverter Y 4  is at low level. 
         [0093]    Since gate nodes of the first output transistor M 1  and the second output transistor M 2  are electrically coupled to the output terminal of the third inverter Y 3 , the first output transistor M 1  and the second output transistor M 2  maintain in the off state. 
         [0094]    Since gate nodes of the fourth output transistor M 4  and the sixth output transistor M 6  are electrically coupled to output terminal of the third inverter Y 3 , gate nodes of the third output transistor M 3  and the fifth output transistor M 5  are electrically coupled to the output terminal of the fourth inverter Y 4 , output transistors M 3 , M 4 , M 5  and M 6  maintain in the on state. As a result, the first scan output terminal out 1  outputs the first scan timing control signal ckv 1 , that is out 1 =ckv 1 ; while the second scan output terminal out 2  outputs the second scan timing control signal ckv 2 , that is out 2 =ckv 2 . 
         [0095]    In the third time interval T 3 , the input signal of the first input signal terminal in is at low level, the light emission timing control signal cke 1  is at low level, and the inverted light emission timing control signal cke 2  is at high level. Therefore, the terminal in_p of the first controlled inverter Y 1  is at high level, the terminal in_n is at low level. The terminal in_p of the second controlled inverter Y 2  is at low level and the terminal in_n is at high level. As such, the first controlled inverter Y 1  is turned off, and the second controlled inverter Y 2  is turned on. 
         [0096]    Therefore, the output of the second controlled inverter Y 2  is an inverted signal of the input signal, that is, node n 1  is at high level. 
         [0097]    The output of the third inverter Y 3  is at low level, that is, the light emission control output terminal out is at low level. The output of the fourth inverter Y 4  is at high level. 
         [0098]    Since gate nodes of the first output transistor M 1  and the second output transistor M 2  are electrically coupled to the output terminal of the third inverter Y 3 , the first output transistor M 1  and the second output transistor M 2  are turned on. 
         [0099]    Since gate nodes of the fourth output transistor M 4  and the sixth output transistor M 6  are electrically coupled to output terminal of the third inverter Y 3 , gate nodes of the third output transistor M 3  and the fifth output transistor M 5  are electrically coupled to the output terminal of the fourth inverter Y 4 , output transistors M 3 , M 4 , M 5  and M 6  are turned off. As a result, the first and second scan output terminals out 1  and out 2  output VDD signal, and thus are at high level, that is, out 1 =VDD, out 2 =VDD. 
         [0100]    In the fourth time interval T 4 , the input signal of the first input signal terminal in is at low level, the light emission timing control signal cke 1  is at high level, and the inverted light emission timing control signal cke 2  is at low level. Therefore, the terminal in_p of the first controlled inverter Y 1  is at low level, the terminal in_n is at high level, the terminal in_p of the second controlled inverter Y 2  is at high level and the terminal in_n is at low level. As such, the first controlled inverter Y 1  is turned on, and the second controlled inverter Y 2  is turned off. The third inverter Y 3  and the first inverter Y 1  form a locking loop to keep n 1  at high level. The light emission control output terminal out is maintained at low level. The output of the fourth inverter Y 4  is at high level. 
         [0101]    Since gate nodes of the first output transistor M 1  and the second output transistor M 2  are electrically coupled to the output terminal of the third inverter Y 3 , the first output transistor M 1  and the second output transistor M 2  are turned on. 
         [0102]    Since gate nodes of the fourth output transistor M 4  and the sixth output transistor M 6  are electrically coupled to output terminal of the third inverter Y 3 , gate nodes of the third output transistor M 3  and the fifth output transistor M 5  are electrically coupled to the output terminal of the fourth inverter Y 4 , output transistors M 3 , M 4 , M 5  and M 6  are turned off. As a result, the first and second scan output terminals out 1  and out 2  output VDD signal, and thus are at high level, that is, out 1 =VDD, out 2 =VDD. 
         [0103]    In the fifth time interval T 5 , the input signal of the first input signal terminal in is at low level, the light emission timing control signal cke 1  is at low level, and the inverted light emission timing control signal cke 2  is at high level. Therefore, the terminal in_p of the first controlled inverter Y 1  is at high level, the terminal in_n is at low level, the terminal in_p of the second controlled inverter Y 2  is at low level and the terminal in_n is at high level. As such, the first controlled inverter Y 1  is turned off, and the second controlled inverter Y 2  is turned on. 
         [0104]    Therefore, the output of the second controlled inverter Y 2  is an inverted signal of the input signal, that is, node n 1  is at high level. 
         [0105]    The output of the third inverter Y 3  is at low level, that is, the light emission control output terminal out is at low level. The output of the fourth inverter Y 4  is at high level. 
         [0106]    Since gate nodes of the first output transistor M 1  and the second output transistor M 2  are electrically coupled to the output terminal of the third inverter Y 3 , the first output transistor M 1  and the second output transistor M 2  are turned on. 
         [0107]    Since gate nodes of the fourth output transistor M 4  and the sixth output transistor M 6  are electrically coupled to output terminal of the third inverter Y 3 , gate nodes of the third output transistor M 3  and the fifth output transistor M 5  are electrically coupled to the output terminal of the fourth inverter Y 4 , output transistors M 3 , M 4 , M 5  and M 6  are turned off. As a result, the first and second scan output terminals out 1  and out 2  output VDD signal, and thus are at high level, that is, out 1 =VDD, out 2 =VDD. 
         [0108]    As can be seen, in the third time interval T 3  and after T 3 , node n 1  maintains at high level, the light emission control output terminal out maintains at low level, and output signals of the first and second scan output terminals out 1  and out 2  (referring to  FIGS. 2 and 6 , G 1   n  and G 1 ) maintain at high level. In addition, as shown in  FIG. 5 , the high level output signal of the light emission control output terminal out corresponds to one period of the light emission timing control signal cke 1 . The low level outputs of the first and second scan output terminals out 1  and out 2  are in phase with the first and second scan timing control signals ckv 1  and ckv 2 . 
         [0109]    Referring to  FIGS. 2-6 , for the second driver stage, the input terminal in may receive the output signal of the light emission control output terminal of the first driver stage. The first clock terminals ck 1  and the second clock terminals ck 2  can receive inverted light emission timing control signals cke 2  and light emission timing control signals cke 1  respectively, and the third clock terminals ck 3  and the fourth clock terminals ck 4  can receive the second scan timing control signals ckv 2  and the first scan timing control signals ckv 1  respectively. 
         [0110]    In the first time interval T 1 , the input signal of the first input signal terminal of the second driver stage (namely, the output signal of the light emission control output terminal of the first driver stage) is at high level, the light emission timing control signal cke 1  is at low level, and the inverted light emission timing control signal cke 2  is at high level. Therefore, the terminal in_p of the first controlled inverter Y 1  of the second driver stage is at low level, and the terminal in_n is at high level. The terminal in_p of the second controlled inverter Y 2  is at high level, and terminal in_n is at low level. As such, the first controlled inverter Y 1  is turned on, and the second controlled inverter Y 2  is turned off. Referring to the above description of the first driver stage, it is easy to understand that after being turned on once (after the first frame), the third inverter Y 3  and the first inverter Y 1  form a locking loop to keep n 1  at high level, the light emission control output terminal out maintains at low level, and the output of the fourth inverter Y 4  is at high level. 
         [0111]    Referring to  FIG. 5  and the above description for the first driver stage, at this point, outputs of the first and second scan output terminals out 1  and out 2  of the second driver stage are at high level. 
         [0112]    Similarly, referring to  FIG. 5  and the above description for the first driver stage, in the second and third time intervals T 2  and T 3 , the output signal En 2  of the light emission control output terminal of the second driver stage is at high level, output signals G 2   n  and G 2  of the first and second scan output terminals out 1  and out 2  of the second driver stage are respectively the second scan timing control signal ckv 2  and the first scan timing control signal ckv 1 . In the fourth time interval T 4  and after T 4 , the output signal En 2  of the light emission control output terminal of the second driver stage maintains at low level, the output signals G 2   n  and G 2  of the first and second scan output terminals out 1  and out 2  of the second driver stage maintain at high level. 
         [0113]    The output timing state of other driver stages may be obtained similarly as shown in  FIG. 6 , which shows an illustrative timing diagram for a light emission control and scan driver  200  including four driver stages each including a light emission control driving unit and a scan driving unit as shown in  FIGS. 3-4 . 
         [0114]    The operating principle and illustrative timing diagrams of the light emission control and scan driver according to the present disclosure have been described above with reference to  FIGS. 5 and 6 . However, the present disclosure is not limited thereto. For example, timings of ckv 2  and ckv 1  may be adjusted according to signals required for driving pixels. As another example, the start pulse signal ste may have a pulse width that is greater than that of the light emission timing control signal cke 1  but smaller than one period of the light emission timing control signal cke 1 . 
         [0115]      FIG. 7  shows a circuit diagram of an illustrative embodiment of a controlled inverter  300  for use in the illustrative driver stage shown in  FIG. 3 . 
         [0116]    The controlled inverter  300  includes a first transistor T 1 , a second transistor T 2 , a third transistor T 3  and a fourth transistor T 4 . The first transistor T 1  and the second transistor T 2  may be for example NMOS transistors, and the third transistor T 3  and the fourth transistor T 4  may be for example PMOS transistors. 
         [0117]    Source node of the second transistor T 2  and drain node of the third transistor T 3  are electrically coupled to the output terminal of the controlled inverter  300 , gate nodes of the second transistor T 2  and the third transistor T 3  are electrically coupled to the first input terminal, drain node of the second transistor T 2  is electrically coupled to source node of the first transistor T 1 , and source node of the third transistor T 3  is electrically coupled to drain node of the fourth transistor T 4 . 
         [0118]    Drain node of the first transistor T 1  is electrically coupled to the second power supply VSS, and gate node of the first transistor T 1  is electrically coupled to the third input terminal in_n. 
         [0119]    Source node of the fourth transistor T 3  is electrically coupled to the first power supply VDD, and gate node of the fourth transistor T 4  is electrically coupled to the second input terminal in_p. 
         [0120]    Those skilled in the art can understand the operating principle of the circuit shown in  FIG. 7 , which will not be described herewith for clarity. Apparently, the present disclosure is not limited thereto and the controlled inverter may be implemented in other ways. 
         [0121]    According to illustrative embodiments, the light emission control driving circuit and the scan driving circuit are integrated together to effectively simplify circuit design and the required control timing signals. 
         [0122]      FIG. 9  shows a display device  900  according to an illustrative embodiment of the present disclosure. 
         [0123]      FIG. 10  shows an illustrative embodiment of the pixel driving circuit applicable to the display device shown in  FIG. 9 . The pixel driving circuit shown in  FIG. 10  is similar to that commonly used in the art and detail description thereof will be omitted. 
         [0124]    The display device  500  according to an illustrative embodiment of the present disclosure will be described below with reference to  FIGS. 9 and 10 . 
         [0125]    Referring to  FIGS. 9 and 10 , the display device  500  includes a pixel array  40 . The pixel array  40  includes a plurality of pixels  50  each including a pixel driving circuit  152  and an organic light emitting diode OLED and connected to scan lines S 1  to Sn, data lines D 1  to Dm, light emission control lines E 1  to En, a first power supply ELVDD and a second power supply ELVSS. The pixel driving circuit receives data signals from the data lines and controls driving currents supplied to the organic light emitting diodes. 
         [0126]    The display device  500  further includes the light emission control and scan driver  200  according to the present disclosure as described above for providing scan signals to the scan lines and providing light emission control signals to the light emission control lines and a data driver  20  for providing data signals to the data lines. 
         [0127]    The display device  500  may further include a timing controller  60  for providing start pulse signals, light emission timing control signals, inverted light emission timing control signals, first scan timing control signals and second scan timing control signals to the light emission control and scan driver. 
         [0128]    It is easy to understand that the illustrated and described embodiments of light emission control driver, light emission control and scan driver and display device are only for illustration rather than limiting the present invention. 
         [0129]    For example, depending on specific pixel driving circuits, it is also possible to omit the second scan output terminal out 2  and relevant circuits. That is, the output transistors M 2 , M 5  and M 6 , and the fourth input terminal ck 4  and the second scan output terminal out 2  in the scan driving unit are omitted. Then the output signals do not include signals G 1 , G 2 , . . . Gn. Alternatively, it is also possible to combine output signals G 1  and G 1   n  into a scan signal including a plurality of pulse trains. 
         [0130]    As another example, the output signal of the light emission control output terminal out may be inverted by adding an inverter. 
         [0131]    Illustrative embodiments of the present disclosure have been shown and described in particular above. It is understood that the present disclosure is not limited to the disclosed embodiments but rather intended to encompass various modifications and equivalent arrangements within the spirit and scope of the appended claims.