Abstract:
Described are power-on reset methods and circuits for resetting and subsequently enabling integrated circuits in response to applied power. A POR circuit in accordance with one embodiment is capable of operating at exceptionally low temperatures and supply voltages, and is relatively tolerant to process variations. The POR circuit compares a band-gap reference signal to a temperature-compensated reference signal that varies in inverse proportion to temperature. The temperature-compensated reference signal extends the useful temperature range of the POR circuit.

Description:
BACKGROUND 
   Band-gap reference (BGR) circuits provide stable reference voltages that vary little with process, supply-voltage, and temperature (PVT). Many circuits—including dynamic random-access memories, flash memories, and analog devices—employ BGR circuits. 
   The band-gap voltage Vbg of conventional BGR circuits is typically about 1.25 volts. Modern integrated circuits, however, are using ever-lower supply voltages, putting downward pressure on the output voltage of BGR circuits. Some modern devices, for example, employ 1.2-volt power supplies (e.g., Vdd is 1.2 volts), making it impractical to derive a 1.25-volt BGR voltage. Researchers have therefore directed their attention to the creation of BGR circuits with reduced band-gap voltage levels. For a more detailed discussion of BGR circuits, see U.S. Pat. No. 6,489,835 to Yu et al. and U.S. Pat. No. 6,323,630 to Banba, both of which are incorporated herein by reference. 
     FIG. 1A  (prior art) depicts a BGR circuit  100  capable of producing a stable BGR voltage with supply voltages below one volt. A differential amplifier Dal receives a pair of input voltages Va and Vb. Input voltage va is derived, in part, from the forward voltage Vf 1  of a diode D 1 , while input voltage Vb is derived, in part, from the forward voltage Vf 2  of a collection of N diodes D 2 . The output from differential amplifier Dal provides the requisite gate bias for PMOS transistors P 1 , P 2 , and P 3  to maintain the equivalence of input voltages Va and Vb (i.e., Va=Vb). PMOS transistors P 1 , P 2 , and P 3  are identical and have the same bias voltages, so their respective currents I 1 , I 2 , and I 3  are equal (i.e., I 1 =I 2 =I 3 ). 
   The input terminals of differential amplifier Da 1  connect to the drains of respective transistors P 1  and P 2  via respective voltage dividers R 4  (resistors R 4   a  and R 4   b ) and R 2  (resistors R 2   a  and R 2   b ). Assuming R 2   a =R 4   a  and R 2   b =R 4   b  gives:
 
I 1   a =I 2   a 
 
I 1   b =I 2   b 
 
 Va=Vf   1 [ R   4   b /( R   4   a+R   4   b )]
 
 Vb=Vf   2 + dvf[R   2   b /( R   2   a+R   2   b )]
 
 dVf=Vf   1 − Vf   2 
 
Because the voltage across R 1  is dVf, this gives:
 
I 2   a =dVf/R 1 
 
 I   2   b=Vf   1 /( R   2   a+R   2   b )
 
Thus, I 2 =I 2   a +I 2   b =[Vf 1 /(R 2   a +R 2   b )]+dvf/R 1 
 
   
     
       
             
             
           
         
             
                 
             
           
           
             
               Vref = 
               R3*I3=R3*I2 
             
             
               = 
               R3{[Vf1/(R2a+R2b)] + (dVf/R1)} 
             
             
               = 
               [R3/(R2a+R2b)] * {Vf1+[dVf(R2a+R2b)/R1]} 
             
             
                 
             
           
        
       
     
   
   The resistance ratio (R 2   a +R 2   b )/R 1  can be set so that vref is not temperature dependent, and the resistance ratio R 3 /(R 2   a +R 2   b ) can be used to adjust the Vref level within the range of the power supply. Voltage dividers R 4  and R 2  reduce voltages Va and Vb below Vf 1 , which may be advantageous for very low Vdd levels. The ratio between R 2   a  and R 2   b  (and similarly between R 4   a  and R 4   b ) is optimized for a given application. BGR circuit  100  is discussed in more detail in the above-referenced Banba patent. 
     FIG. 1B  is waveform diagram  150  approximating a pair of simulated responses of BGR circuit  100  to the application of a 1.8-volt supply voltage Vdd. (As with other designations in the present disclosure, Vdd refers to both the signal and the corresponding signal node. Whether a given designation refers to a signal or a node will be clear from the context.) 
   Diagram  150  includes two response curves: a first curve  160  depicts the response of BGR signal Vbg to the application of supply voltage Vdd at a first temperature, and a second curve  165  depicts the response of BGR signal Vbg to the application of the same supply voltage Vdd at a second, lower temperature. The slower response of curve  165  indicates that the response of BGR circuit  100  shifts later in time with reduced temperatures. This shift occurs because the forward voltages vf of diodes D 1  and D 2  increase with reduced temperature, so Vdd must rise higher before diodes D 1  and D 2  conduct. 
   Typical integrated circuits (ICs) function over a range of power-supply voltages, and can be expected to fail if operating with supply voltage outside this range. ICs therefore commonly include a so-called “Power-On-Reset” (POR) circuit that resets the IC to a known state upon application of power and holds the known state until the power supply voltages settle at or near some predetermined level. Typically, the POR circuit is powered by the same source as the rest of the IC. 
     FIG. 2A  depicts a conventional POR circuit  200 , which includes a BGR circuit  200 , a voltage comparator  210  (a differential amplifier), and a voltage divider  215  connected between supply voltage Vdd and ground. BGR  205  provides a BGR signal Vbg to the non-inverting input of comparator  210 ; voltage divider  215  provides a reference voltage Va, a fraction of supply voltage Vdd, to the inverting input of comparator  210 . Comparator  210  compares band-gap voltage Vbg and reference voltage Va to generate a POR signal. 
     FIG. 2B  is a waveform diagram  220  depicting the response of POR circuit  200  to power applied to supply terminals vdd and ground, at time zero, to produce a rising potential difference between vdd and ground. For illustrative purposes, supply voltage Vdd is assumed to rise linearly from zero to 1.8 volts over a power-up time of about 300 microseconds (line  225 ). BGR circuit  205  can be any of many such circuits, but is assumed to be like BGR circuit  100  for this illustration. Response curves  160  and  165  of BGR circuit  100  are therefore included in FIG.  2 B. 
   Reference voltage Va is merely a divided version of supply voltage Vdd, and thus increases linearly in proportion to Vdd as Vdd ramps up from zero to 1.8 volts. In contrast, BGR signal Vbg ramps up in a non-linear fashion due to the non-linear components (diodes and transistors) employed to generate BGR signal Vbg. The level of BGR signal Vbg can therefore cross the level of reference voltage Va a number of times, producing one or more undesirable “windows” W in the POR signal. In this example, the low-temperature Vbg curve  165  produces a troublesome window, but the higher temperature Vbg curve  160  does not. The relationship between reference voltage va and curves  160  and  165  illustrate that POR circuits are especially susceptible to producing windows when operating at extreme values of process, temperature, and voltage. If such windows are unavoidable, it is preferred that they disappear early and at a relatively low vdd value. 
   SUMMARY 
   The present invention is directed to power-on reset (POR) methods and circuits for resetting and subsequently enabling integrated circuits in response to applied power. A POR circuit in accordance with one embodiment is capable of operating at exceptionally low temperatures and supply voltages, and is relatively tolerant to process variations. To achieve these benefits, the POR circuit compares a conventional BGR signal with a temperature-compensated reference signal that varies in inverse proportion to temperature. 
   The claims, and not this summary, define the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
       FIG. 1A  (prior art) depicts a BGR circuit  100  capable of producing a stable band gap voltage with supply voltages below one volt. 
       FIG. 1B  is waveform diagram  150  approximating simulated responses of BGR circuit  100  to the application of a 1.8-volt supply voltage vdd. 
       FIG. 2A  depicts a conventional POR circuit  200 . 
       FIG. 2B  depicts the response of POR circuit  200  of  FIG. 2A  to power applied to supply terminal vdd at time zero. 
       FIG. 3A  depicts a power-on-reset (POR) circuit  300  in accordance with one embodiment of the invention. 
       FIG. 3B  depicts the response of POR circuit  300  of  FIG. 3A  to power applied to supply terminal vdd at time zero. 
   

   DETAILED DESCRIPTION 
     FIG. 3A  depicts a power-on-reset (POR) circuit  300  in accordance with one embodiment of the invention. POR circuit  300  is capable of operating at exceptionally low temperatures and operating voltages, and is relatively tolerant of process variations. As in the conventional POR circuit  200  of  FIG. 2A , POR circuit  300  includes a comparator that compares a BGR signal Vbg to a second reference voltage to produce a POR signal. As detailed below, however, the second reference signal Vr in POR circuit  300  is non-linear with respect to vdd, and this nonlinearity compensates for temperature variation that might otherwise lead to undesirable windows in the POR signal. 
   POR circuit  300  includes many components in common with POR circuit  200  of  FIG. 2 , like-identified elements being the same or similar. POR circuit  300  is modified, however, to include a second reference circuit  310  that produces a temperature-compensated second reference signal Vr. Reference circuit  310  includes a PMOS transistor  315  in which the source (a first current-handling terminal) is connected to Vdd (a first power-supply terminal), the drain (a second current-handling terminal) is connected to ground (a second power-supply terminal), and the gate (a control terminal) is connected to a temperature-compensated control terminal Vtc. A voltage divider R 5  divides the voltage across diode D 1 , producing control signal Vtc on an intermediate voltage-divider terminal. The forward voltage vf 1  across D 1  is inversely proportional to temperature, so control signal Vtc is likewise inversely proportional to temperature. Control signal Vtc is substantially constant with variations in power-supply voltage once Vdd exceeds Vtc by the threshold voltage Vtp of PMOS transistor  315 . The drain of transistor  315  connects to ground via a voltage divider R 6  that produces, on an intermediate node defined between resistors R 6   a  and R 6   b , the non-linear reference signal vr to comparator  210 . 
     FIG. 3B  is a waveform diagram  350  depicting the response of POR circuit  300  to power applied to supply terminal vdd at time zero. As in the example of  FIG. 2B , supply voltage vdd rises linearly from zero to 1.8 volts over about 300 microseconds. A conventional start-up circuit (not shown) provides a POR-start-up signal PORsu to the control terminal of an NMOS transistor N 1 . Signal PORsu briefly pulls line vp low to start POR circuit  300  and then turns of transistor N 1  to allow differential amplifier Da 1  to establish the bias voltage for PMOS transistors P 1 , P 2 , and P 3 . 
   When Vdd rises high enough to forward bias PMOS transistors P 1 , P 2 , and P 3 , transistor P 1  provides current I 1   b  through voltage divider R 5 , causing control signal Vtc to rise abruptly (time T 1 ). Later, when Vdd reaches Vtc plus Vtp (vdd=vtc+vtp) to forward bias transistor  315 , reference signal Vr rises abruptly (time T 2 ). With both of transistors P 1  and  315  forward biased, reference signal Vr rises linearly with supply voltage vdd. 
   Reference signal Vr, in comparison to reference signal Va of conventional POR circuit  200  of  FIGS. 2A and 2B , exhibits two noteworthy characteristics. First, reference signal Vr does not rise with Vdd until BGR signal Vbg has progressed significantly toward its ultimate reference level, and thus avoids crossing BGR signal Vbg to produce undesirable windows. Second, the time at which reference signal Vr begins to rise (e.g. time T 2 ) is inversely proportional to temperature; consequently, as the Vbg curve moves to the right (later in time), so too does the curve associated with reference signal Vr. The values of resistors R 6   a  and R 6   b  within voltage divider R 6  are selected to achieve a desired cross-over point for reference voltages Vbg and Vr; the sum of the values of resistors R 5   a  and R 5   b  is equal to R 2   b , and the ratio of R 5   a  and R 5   b  is selected to establish a desired time for the second reference signal vr to begin rising. The values of the various components of BGR circuit  300  will vary depending on the application. Selecting appropriate values is well within the skill of those in the art. 
   While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, while a BGR circuit is modified in the foregoing examples to provide the temperature-compensated reference signal Vtc, alternative methods of providing the requisite temperature compensation might also be used. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection establishes some desired electrical communication between two or more circuit nodes, or terminals. Such communication may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.