Abstract:
The switched charge multiplier-divider according to the present invention is constructed of CMOS devices. Capacitor charge theory is employed to implement the circuit of the switched charge multiplier-divider. The switched charge multiplier-divider includes an output capacitor and controls the voltage across the output capacitor, so that it is proportional to the product of the charge current and the charge-time interval. The switched charge multiplier-divider is ideal for use in the power factor correction (PFC) of switching mode power supplies. Potentially, it can also be applied to automatic gain control (AGC) circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to the art of electronics and more particularly relates to an analog multiplier-divider. 
     2. Description of the Prior Art 
     There are many uses of analog multiplier-dividers in modem electronics. Multiplier-dividers produce an output signal that is proportional to a ratio of two or more input signals. The input and output signals can either be voltages or currents. 
     One common use for multiplier-dividers is in power factor correction (PFC) circuits. PFC circuits commonly use multiplier-dividers to generate a control signal based on an input current, a feedback signal, and an input voltage. Other uses of multiplier-divider circuits include but are not limited to automatic gain control (AGC) circuits. 
     There are many known ways of constructing analog multiplier-dividers, such as logarithmic amplifiers and antilog amplifiers. The implementation of a logarithmic amplifier normally uses the p-n junction volt-ampere characteristic; it is given by 
     
       
           I   D   =I   0 ×[exp( V   D   /ηV   T )−1]  (1) 
       
     
     where I 0  is the reverse saturation current; V D  is the forward bias voltage; η is the constant; V T =T/11,600 and T is the temperature ° K. Since the output current I D  is the exponential function of the forward bias voltage V D , the linear operating region is small. The book “Analog Integrated Circuit Design” by David A. Johns and Ken Martin (1997, p 366-367) teaches another known analog multiplier-divider. This particular multiplier-divider is also implemented by using p-n junction devices. As FIG. 1 shows, it is referred to as a four-quadrant multiplier. 
     The prior-art multiplier-divider shown in FIG. 1 is built using bipolar transistor devices. It supplies an output current with the amplitude that is proportional to the product of a first input current and a current ratio. The current ratio is equal to the amplitude of a second input current divided by the amplitude of a bias current. 
     Many other known prior-art multiplier-dividers are all based on the principles as the prior-art multiplier-divider shown in FIG.  1 . Those prior-art multiplier-dividers share the same disadvantages because they are built using bipolar transistor devices. 
     One disadvantage of the prior-art multiplier-divider shown in FIG. 1 is its high manufacture cost. For many present-day applications, such as PFC circuits, integrated circuits manufacture using bipolar process are not suitable because bipolar devices still occupy lots of die space and increase the cost. 
     Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is that the output of the circuit varies significantly with temperature. Referring to equation (1), it is obviously that bipolar devices have high temperature coefficients. Thus, the output of the circuit is highly susceptible to temperature changes. 
     Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is high power consumption. The prior-art multiplier-divider requires a constant non-zero biasing current to operate bipolar transistors in linear mode. This results in significant power consumption. 
     Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is poor noise immunity. This is because the prior-art multiplier-divider uses high-gain bipolar transistor devices. With such devices, even relatively small input signal distortion can result in significant output signal distortion. 
     Another disadvantage of the prior-art multiplier-divider of FIG. 1 is that it has a narrow input range, limited to the linear operating region of bipolar transistors. Outside this narrow input signal range, the multiplier-divider shown in FIG. 1 is highly susceptible to distortion. 
     Therefore, it is needed to improve the drawbacks of the prior-art multiplier-dividers. In particular, an improved multiplier-divider that has a smaller die size while being suitable for a wider range of operating temperatures is absolutely needed. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, the multiplier-divider of the present invention produces an output signal in response to three input signals. The output signal is proportional to the product of a first input signal and a second input signal divided by a third input signal. 
     A general objective of the present invention is to provide a general-purpose multiplier-divider. It is a further objective of the present invention to provide a multiplier-divider that is suitable to apply in a power factor correction (PFC) circuit of a switch mode power supply. 
     Another objective of the present invention is to provide a multiplier-divider that is manufactured in CMOS process. The multiplier-divider according to the present invention exclusively uses MOSFET-based devices. Therefore, the multiplier-divider according to the present invention can be manufactured at a significantly reduced die-size level, and at a lower cost than the prior-art multiplier-divider. 
     Another objective of the present invention is to provide a multiplier-divider having a characteristic equation that is substantially independent of temperature, compared to prior-art multiplier-dividers. 
     Another objective of the present invention is to provide a multiplier-divider with reduced power consumption. The multiplier-divider according to the present invention does not require a constant biasing current. 
     Another objective of the present invention is to provide a multiplier-divider with improved noise immunity. The accuracy of the output signal of the multiplier-divider according to the present invention is not significantly affected by small noise components from the input signals. 
     Briefly, the present invention relates to a switched charge multiplier-divider. The switched charge multiplier-divider is built according to the principle of capacitor charge theory. The voltage across the capacitor is proportional to the product of the charge current and the charge time interval, and is divided by the capacitance of the capacitor. By using a modulated charge current and a programmable charge time to switch the capacitor, the voltage across the capacitor can be controlled. This capacitor voltage is the output voltage of the switched charge multiplier-divider. 
     The switched charge multiplier-divider according to the present invention can perform signal multiplication and division. Use of the capacitor charge technique enables the implementation of a multiplier-divider with reduced power consumption, improved noise immunity, a wider operating range, and a lower temperature coefficient. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
     FIG. 1 shows a conventional multiplier-divider. 
     FIG. 2 shows a block diagram of a switched charge multiplier-divider according to a preferred embodiment of the present invention. 
     FIG. 3 shows the switched charge multiplier-divider according to a preferred embodiment of the present invention. 
     FIG. 4 shows a sawtooth signal generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention. 
     FIG. 5 shows a dynamic current sink of the sawtooth signal generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention. 
     FIG. 6 shows a pulse generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention. 
     FIG. 7 shows a timing diagram of the sawtooth signal generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention. 
     FIG. 8 shows a timing diagram of the pulse generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings wherein the contents are for purposes of illustrating preferred embodiments of the invention only and not for purposes of limiting same. 
     FIG. 1 shows a prior-art multiplier-divider. The prior-art multiplier-divider is constructed of an array of six bipolar transistors  10 ,  11 ,  12 ,  13 ,  14  and  15 . A base of each of the transistors  10 ,  11 ,  12 ,  13 ,  14  and  15  are all tied together. 
     A collector of the transistor  10  is connected to the base of the transistor  10 . An emitter of the transistor  10  is connected to the ground reference. The collector of the transistor  10  is connected to a first positive input terminal. A collector of the transistor  11  is connected to a negative output terminal. A collector of the transistor  12  is connected to a positive output terminal. A collector of the transistor  13  is connected to the negative output terminal. An emitter of the transistor  12  and an emitter of the transistor  13  are connected to a second positive input terminal. A collector of the transistor  14  is connected to the positive output terminal. An emitter of the transistor  11  and an emitter of the transistor  14  are connected to a second negative input terminal. A collector of the transistor  15  is connected to a first negative input terminal. The collector of the transistor  15  is connected to the base of the transistor  15 . An emitter of the transistor  15  is connected to the ground reference. Operation of this circuit will be well known to those skilled in the art and does not need to be discussed in further detail herein. 
     As discussed above, one major drawback of this prior-art multiplier-divider is that it is constructed of bipolar transistor devices. This results in a large die-size and introduces high temperature dependence into the characteristic of the prior-art multiplier-divider. 
     To overcome these problems, the present invention proposes a switched charge multiplier-divider  100  constructed of MOSFET devices. FIG. 2 shows a block diagram of the switched charge multiplier-divider  100  according to the present invention. The switched charge multiplier-divider  100  has a first multiplier input terminal for receiving a first multiplier input signal V B , a second multiplier input terminal for receiving a second multiplier input signal I A , and a divisor input terminal for receiving a divisor input signal V C . The switched charge multiplier-divider  100  also has an output terminal for generating an output voltage signal V M . The magnitude of the output voltage signal V M  is proportional to the magnitude of the first multiplier input signal V B  multiplied by the magnitude of the second multiplier input signal I A , divided by the divisor input signal V C . The first multiplier input signal V B  and the divisor input signal V C  are voltage signals and the second multiplier input signal I A  is a current signal. The output of the switched charge multiplier-divider  100  can be expressed as,                V   M     ∝     k   ×     (         I   A     ×     V   B         V   C       )               (   2   )                                
     where k is an constant. 
     However, it is to be understood that voltage input/output could be converted to current input/output, and that current input/output could be converted to voltage input/output without departing from the spirit of the invention. Methods of converting a current to a voltage, and vice-versa, are well known to those skilled in the art. 
     The switched charge multiplier-divider  100  is implemented according to the principle of capacitor charge theory. An important equation describing the behavior of capacitors is: 
     
       
           Q=C×V=I×T   (3) 
       
     
     where Q is the charge, C is the capacitance of the capacitor, V is the voltage across the capacitor, I is the charge current, and T is the charge time. 
     According to equation (3), a programmable charge time T 1  can be expressed as,                T   1     =         V   B     ×     C   1         I   1               (   4   )                                
     where a charge current I 1  charges a capacitor that has a capacitance C 1 .          I   1     =       V   C       R   1                              
     Then equation (4) can also be shown as,                T   1     =       R   1     ×     C   1     ×       V   B       V   C                 (   5   )                                
     Charging a capacitor with a capacitance C 2  with the second multiplier input signal I A  for the duration of the programmable charge time T 1  will produce the output voltage signal V M  at the output of the multiplier-divider  100 ,          V   M     =           I   A       C   2       ×     T   1       =           C   1       C   2       ×     R   1     ×         I   A     ×     V   B         V   C         =     k   ×         I   A     ×     V   B         V   C                                    
     where R 1  is the resistance of the resistor, C 1  and C 2  are the capacitances of the capacitors, k is a constant equal to R 1 ×(C 1 /C 2 ). 
     Therefore, a basic model of the multiplier-divider is built as described above. 
     FIG. 3 shows a preferred embodiment of the switched charge multiplier-divider  100  according to the present invention. The switched charge multiplier-divider  100  includes a sawtooth signal generator  110 , a charge-time control circuit  120 , a linear charging circuit  130 , a sample-hold circuit  140 , and a pulse generator  200 . The sawtooth signal generator  110  generates a sawtooth signal V SAW  that has a fixed period. The maximum voltage and the slew rate of the sawtooth signal V SAW  are proportional to the magnitude of the divisor input signal V C . The sawtooth signal V SAW  is compared with the first multiplier input signal V B  to generate a charge-time signal V CT . The charge-time signal V CT  determines the programmable charge time T 1  of the charge-time control circuit  120 . The programmable charge time T 1  is thus controlled by the divisor input signal V C  and the first multiplier input signal V B . The linear charging circuit  130  includes a charge circuit that is charged by the second multiplier input signal I A . The charge time of the linear charging circuit  130  is determined by the programmable charge time T 1 . The sample-hold circuit  140  samples an output-stage signal V C2  of the linear charging circuit  130  and holds the output voltage signal V M  at the output terminal of the switched charge multiplier-divider  100 . 
     The pulse generator  200  produces control signals including a pulse signal PLS, a sampling signal SMP and a clear signal CLR. As FIG. 8 shows, the sampling signal SMP follows the pulse signal PLS after a delay time t D1 . The clear signal CLR follows the sampling signal SMP after a delay time t D2 . 
     FIG. 6 shows the pulse generator  200  according to a preferred embodiment of the present invention. The pulse generator  200  includes a current source  210 , a switch  211 , a switch  212 , and a current sink  213 . The pulse generator  200  further includes a capacitor  220 , a hysteresis comparator  221 , a NOT-gate  222 , a NOT-gate  223 . The pulse generator  200  further includes a comparator  230 , a NOT-gate  231 , a NOT-gate  232 , a NAND-gate  240 , a NAND-gate  241 , and a NOT-gate  242 . The pulse generator  200  further includes a NOT-gate  250 , a NOT-gate  251 , a NOT-gate  252 , and an AND-gate  253 . The pulse generator  200  further includes a NOT-gate  260 , a NOT-gate  261 , a NOT-gate  262 , an AND-gate  263 , and a NAND-gate  270 . 
     An input of the current source  210  is connected to a voltage source V DD . The switch  211  is connected between an output of the current source  210  and an input junction. The switch  212  is connected between the input junction and an input of the current sink  213 . An output of the current sink  213  is connected to the ground reference. An input of the hysteresis comparator  221  is connected to the input junction. The capacitor  220  is connected between the input of the hysteresis comparator  221  and the ground reference. An output of the hysteresis comparator  221  is connected to an input of the NOT-gate  222 . An output of the NOT-gate  222  is connected to an input of the NOT-gate  223 . A voltage terminal V R  is connected to an output of the NOT-gate  223 . 
     A positive input of the comparator  230  is connected to an output terminal of the sawtooth signal generator  110  for receiving the sawtooth signal V SAW . A negative input of the comparator  230  is supplied with a reference voltage V REF . An output of the comparator  230  is connected to an input of the NOT-gate  231 . An output of the NOT-gate  231  is connected to an input of the NOT-gate  232 . An output of the NOT-gate  232  is connected to a voltage terminal V S . 
     A first input of the NAND-gate  240  is connected to the output of the NOT-gate  223 . A second input of the NAND-gate  240  is connected to an output of the NAND-gate  241 . A first input of the NAND-gate  241  is connected to an output of the NAND-gate  240 . A second input of the NAND-gate  241  is connected to the output of the NOT-gate  232 . The output of the NAND-gate  240  outputs a clock signal CK 1 , which is supplied to a control terminal of the switch  212 . The clock signal CK 1  is also supplied to a control terminal of the switch  211  via the NOT-gate  242 . 
     An input of the NOT-gate  250  is connected to the output of the NAND-gate  240  for receiving the clock signal CK 1 . An input of the NOT-gate  251  is connected to an output of the NOT-gate  250 . An input of the NOT-gate  252  is connected to an output of the NOT-gate  251 . An output of the NOT-gate  252  is connected to an input of the AND-gate  253 . An inverted input of the AND-gate  253  is connected to the output of the NAND-gate  240 . The AND-gate  253  of the pulse generator  200  outputs the sampling signal SMP. 
     An input of the NOT-gate  260  is connected to the voltage terminal V R . An input of the NOT-gate  261  is connected to an output of the NOT-gate  260 . An input of the NOT-gate  262  is connected to an output of the NOT-gate  261 . An output of the NOT-gate  262  is connected to an input of the AND-gate  263 . An inverted input of the AND-gate  263  is connected to the voltage terminal V R . The AND-gate  263  of the pulse generator  200  outputs the clear signal CLR. 
     A first input of the NAND-gate  270  is connected to the output of the NAND-gate  240 . A second input of the NAND-gate  270  is connected to the voltage terminal V R . The output of the NAND-gate  270  of the pulse generator  200  outputs the pulse signal PLS. 
     FIG. 8 is a timing diagram illustrating the operation of internal signals and output signals generated by the pulse generator  200 . The operation of this circuit will be well known to those skilled in the art and therefore detailed description thereof is not included herein. 
     When the pulse generator  200  generates the pulse signal PLS, the sawtooth signal generator  110  will output a sawtooth signal V SAW  in response to the divisor input signal V C . After the pulse signal PLS goes low, the charge-time control circuit  120  will compare the sawtooth signal V SAW  with the first multiplier input signal V B  to produce a charge-time signal V CT . The programmable charge time T 1  of the charge-time signal V CT  will be proportional to the magnitude of the first multiplier input signal V B  divided by the divisor input signal V C . The linear charging circuit  130  will charge a capacitor  131  for the duration of the programmable charge time T 1 . The capacitor  131  will be charged by a current having an amplitude proportional to the magnitude of the second multiplier input signal I A . At this point, the charge of the capacitor  131  will determine the magnitude of the output voltage signal V M  of the switched charge multiplier-divider  100 . When the pulse generator  200  supplies the sampling signal SMP, the output-stage signal V C2  of the linear charging circuit  130  will be sampled by the sample-hold circuit  140  to produce the output voltage signal V M  of the multiplier-divider  100 . The delay time t D2  is inserted between the falling-edge of the sampling signal SMP and the rising-edge of the clear signal CLR to reset the switched charge multiplier-divider  100 . 
     FIG. 4 shows the sawtooth signal generator  110  according to a preferred embodiment of the present invention. The sawtooth signal generator  110  includes a switch  111 , a NOT-gate  112 , a switch  113 , a capacitor  114  having a capacitance C 1 , and a dynamic current sink  115 . A control terminal of the switch  111  and an input of the NOT-gate  112  are supplied with the pulse signal PLS of the pulse generator  200 . An output of the NOT-gate  112  is connected to a control terminal of the switch  113 . The switch  111  is supplied with the divisor input signal V C  and is connected to the output terminal of the sawtooth signal generator  110 . The capacitor  114  is connected between the output terminal of the sawtooth signal generator  110  and the ground reference. The switch  113  is connected between the output terminal of the sawtooth signal generator  110  and an input of the dynamic current sink  115 . An output of the dynamic current sink  115  is connected to the ground reference. A modulated terminal of the dynamic current sink  115  is supplied with the divisor input signal V C . 
     As the pulse generator  200  supplies a logic-high pulse signal PLS, the switch  111  will close. This will cause the divisor input signal V C  to charge the capacitor  114 . When the pulse signal PLS goes low, the switch  111  will open, and the switch  113  will close. At this point, the capacitor  114  will begin to discharge via the dynamic current sink  115 . To ensure that the discharge time will be independent of the divisor input signal V C , the dynamic current sink  115  generates a sink current I 1 , that is proportional to the magnitude of the divisor input signal V C . Therefore the maximum voltage and the slew rate of the sawtooth signal V SAW  will be proportional to the magnitude of the divisor input signal V C . 
     FIG. 5 shows the dynamic current sink  115  according to a preferred embodiment of the present invention. The dynamic current sink  115  generates the sink current I 1  that is proportional to the magnitude of the divisor input signal V C . This is used to regulate the discharge time of the capacitor  114 , so that the period length of the sawtooth signal V SAW  will be independent of the magnitude of the input signals of the switched charge multiplier-divider  100 . 
     The dynamic current sink  115  includes an operational amplifier  116 , a resistor  117  having a resistance R 1 , and a MOSFET  118 . A positive terminal of the operational amplifier  116 , which is also the modulated terminal of the dynamic current sink  115 , is supplied with the divisor input signal V C . A negative terminal of the operational amplifier  116  is connected to a source of the MOSFET  118 . A drain of the MOSFET  118 , which is also the input of the dynamic current sink  115 , is connected to the output terminal of the switch  113  shown in FIG. 4. A first terminal of the resistor  117  is connected to the source of the MOSFET  118 . A second terminal of the resistor  117 , which is also the output of the dynamic current sink  115 , is connected to the ground reference. An output terminal of the operational amplifier  116  is connected to a gate of the MOSFET  118 . The dynamic current sink  115  generates the sink current I 1  that is proportional to the magnitude of the divisor input signal V C , divided by the resistance R 1  of the resistor  117 . Operation of this circuit will be well known to those skilled in the art and therefore a detailed description thereof is not included herein. 
     Referring to FIG. 3, the output terminal of the sawtooth signal generator  110  supplies the sawtooth signal V SAW  to the charge-time control circuit  120 . The charge-time control circuit  120  includes a comparator  121 , an AND-gate  122 , and a NOT-gate  123 . 
     A negative terminal of the comparator  121  is connected to the output terminal of the sawtooth signal generator  110 . The first multiplier input signal V B  is supplied to a positive terminal of the comparator  121 . An output of the comparator  121  is connected to a first input terminal of the AND-gate  122 . A second input terminal of the AND-gate  122  is connected to an output of the NOT-gate  123 . The pulse signal generator  200  supplies the pulse signal PLS to an input of the NOT-gate  123 . An output of the AND-gate  122  generates the charge-time signal V CT  to determine the programmable charge time T 1 . 
     The comparator  121  will compare the first multiplier input signal V B  with the sawtooth signal V SAW  of the sawtooth signal generator  110 . When the pulse signal PLS supplied by the pulse signal generator  200  goes low, the AND-gate  122  will output a charge-time signal V CT , in which the on-time of said charge-time signal V CT  is proportional to the magnitude of the first multiplier input signal V B . 
     The charge-time signal V CT  is supplied to the linear charging circuit  130 . The linear charging circuit  130  includes a capacitor  131  has the capacitance C 2 , a switch  132 , and a switch  133 . 
     An input terminal of the linear charging circuit  130  is supplied with the second multiplier input signal I A  of the switched charge multiplier-divider  100 . The switch  132  is connected between the input terminal of the linear charging circuit  130  and an output terminal of the linear charging circuit  130 . A control terminal of the switch  132  is connected to the output of the AND-gate  122 . A turn-on time t 132  of the switch  132  will be proportional the product of the resistance R 1  of the resistor  117 , the capacitance C 1  of the capacitor  114 , and the magnitude of the first multiplier input signal V B . The turn-on time t 132  of the switch  132  will be inversely proportional to the magnitude of the divisor input signal V C . The switch  133  is connected between the output terminal of the linear charging circuit  130  and the ground reference. The pulse generator  200  supplies the clear signal CLR to a control terminal of the switch  133 . The capacitor  131  is connected between the output terminal of the linear charging circuit  130  and the ground reference. 
     When the switch  132  is closed by the charge-time signal V CT  supplied by the AND-gate  122 , the second multiplier input signal I A  of the switched charge multiplier-divider  100  will supply a current to charge the capacitor  131 . The amplitude of this current will be proportional to the magnitude of the second multiplier input signal I A . When the pulse generator  200  generates a logic-high clear signal CLR, the switch  133  will close, and the charge stored in the capacitor  131  will be discharged. 
     The sample-hold circuit  140  includes an operational amplifier  141 , a switch  142 , and a capacitor  143 . A positive input of the operational amplifier  141  is connected to the output terminal of the linear charging circuit  130 . A negative input of the operational amplifier  141  is connected to an output of the operational amplifier  141 . The switch  142  is connected between the output of the operational amplifier  141  and the output of the switched charge multiplier-divider  100 . A control terminal of the switch  142  is controlled by the sampling signal SMP of the pulse generator  200 . The capacitor  143  is connected between the output of the switched charge multiplier-divider  100  and the ground reference. 
     The operational amplifier  141  is a buffer for the charge of the capacitor  131 . When a logic-high sampling signal SMP from the pulse generator  200  closes the switch  142 , the voltage at the output of the operational amplifier  141  will be equal to the potential of the capacitor  131 . The maximum voltage of the capacitor  131  will determine the output voltage signal V M  at the output of the switched charge multiplier-divider  100 . Within a constant factor, the magnitude of this output voltage signal V M  will be proportional to the magnitude of the first multiplier input signal V B  multiplied by the magnitude of the second multiplier input signal I A , divided by the magnitude of the divisor input signal V C . The capacitor  143  is included as a holding capacitor to keep the output voltage signal V M . 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims or their equivalents.