Abstract:
A method for controlling a low-power state of a pair of serial interfaces using a pair of flow-control signal lines may include enabling a first of the flow-control lines by a first one of the interfaces for signaling a transmission request to the second interface. The method may also include, in response to the transmission request, waking up to a live state from a low-power state and enabling a second flow-control line for signaling a transmission authorization to the first interface. In response to the transmission authorization, the method may include initiating a transmission of a message to the second interface, and upon reaching an offset before the end of the message transmission, disabling the first flow-control line by the first interface. The method may also include, at the end of the message transmission, disabling the second flow-control line and going back into the low-power state.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to power saving in serial communication interfaces, more particularly, in serial interfaces using flow-control signals. 
       BACKGROUND OF THE INVENTION 
       [0002]      FIG. 1  schematically shows a conventional full-duplex serial communication system. It includes a pair of similar serial interfaces SIF 1  and SIF 2 , such as UARTs, connected to each other in a 5-wire configuration. These wires carry four signals and a common ground. The ground wire is not shown. 
         [0003]    Each serial interface has a transmit output TX, a receive input RX, a flow-control output RTS, and a flow-control input CTS. The TX and RTS outputs of interface SIF 1  are connected respectively to the RX and CTS inputs (RX 2 , CTS 2 ) of interface SIF 2 . The RX and CTS inputs of interface SIF 1  are connected respectively to the TX and RTS outputs (TX 2 , RTS 2 ) of interface SIF 2 . 
         [0004]    Historically “RTS” and “CTS” stand for “Request To Send” and “Clear To Send”. This terminology is no longer relevant to the way these signals are used today in UARTs. In practice, an active state of the RTS signal indicates to the remote interface that it may send data, and an inactive state indicates that the remote interface should stop sending data, for instance because the receive buffer in the local interface is full. 
         [0005]      FIG. 2  is a diagram showing an exemplary message transmission sequence from interface SIF 1  to SIF 2 . The signals and lines are named according to the corresponding input/output terminals of interface SIF 1 . 
         [0006]    The signals are active-low, i.e. a signal at “1” is inactive and a signal at “0” is active. Initially all signals are inactive (at “1”), for instance during power-on. At some point in time, for instance after a reset in each of the interfaces, the RTS and CTS signals become active. The signal CTS is shown as becoming active after signal RTS, but this order of events is not necessary. A transmission of a serial data message on line TX may only start when signal CTS is active, from a time t0. The state of signal RTS is irrelevant to the transmission. 
         [0007]    A message transmission on line TX is shown as black areas. The transmission may start as soon as signal CTS is enabled, at time t0. At a time t1, the remote interface SIF 2  disables signal CTS to indicate that it can no longer receive data. Interface SIF 1  responds by suspending the message transmission. In practice, interface SIF 1  finishes the transmission of the current atomic data unit, for instance a byte, before actually stopping the transmission, whereby the transmission may continue for a short period of time after t1, as shown. 
         [0008]    When the remote interface SIF 2  is ready to receive data again, it activates signal CTS at a time t2, from which the interrupted transmission may resume on line TX. When the transmission is finished, both interfaces are idle and the signals RTS and CTS remain active as long as the interfaces are powered, meaning that each interface is ready to receive data. 
         [0009]    In some applications, it is desirable to set the interfaces SIF 1  and SIF 2  in a low-power state while they are not communicating, for instance by turning off their clocks. When the interfaces need to communicate again, they should be able to wake each other up. Such a goal has been achieved, for example, by providing additional signal lines between the interfaces, whose sole purpose is to allow each interface to wake-up the other interface from a low-power state. This approach is described, for instance, in “Transport Bus Driver for Bluetooth Power Control Handling Guidelines” published by Microsoft and available from the following link: http://feishare.com/attachments/article/291/transport-bus-driver-for-bluetooth-power-handling.pdf. 
       SUMMARY OF THE INVENTION 
       [0010]    Serial interfaces that can mutually control their low-power states using standard signal lines and involving minimal modifications of a standard serial interface are thus desirable. 
         [0011]    This desire is addressed by a method for controlling a low-power state of a pair of similar serial interfaces using a pair of flow-control signal lines. The method includes enabling a first of the flow-control lines by a first of the interfaces for signaling a transmission request to the second interface, and in response to the transmission request by the second interface, waking up to a live state from a low-power state; enabling the second flow-control line by the second interface for signaling a transmission authorization to the first interface. The method also includes, in response to the transmission authorization by the first interface, initiating a transmission of a message to the second interface, and upon reaching an offset before the end of the message transmission, disabling the first flow-control line by the first interface. The method further includes, at the end of the message transmission, disabling the second flow-control line by the second interface and going back into the low-power state. 
         [0012]    According to an embodiment, the method may also include providing an end-of-transmission flag in the header of each message of a sequence of messages and setting the end-of-transmission flag in only the last message of the sequence. The method may further include disabling the second flow-control line at the end of the message that has the end-of-transmission flag set. 
         [0013]    According to an embodiment, the method may further include transmitting a second message by the second interface to the first interface and, after disabling the second flow-control line by the second interface during transmission of the second message, suspending transmission of the second message, disabling the second flow-control line, and enabling the second flow-control line again for signaling a transmission request to the first interface. The method may also include enabling the first flow-control line for signaling a transmission authorization to the second interface, and, in response to the transmission authorization by the second interface, continuing transmission of the second message. 
         [0014]    According to an embodiment, the method may further include conveying a message length in a header of the transmitted message, and identifying the end of the message transmission by comparing the received data count to the message length. According to an embodiment, the offset is equal to an atomic data unit whose transmission is not suspended by a flow-control signal. 
         [0015]    A method may also be provided for controlling a low-power state of a receiver serial interface. The method may include waking-up from the low-power state when a flow-control input of the interface is enabled; receiving a message on a serial data input of the interface, and returning to the low-power state at the end of the message. 
         [0016]    A method may also be provided for controlling a low-power state of a transmitter serial interface. The method may include transmitting a message on a serial data output, and disabling a flow-control output before the end of the message transmission. The method may further include going into the low-power state when a flow-control input is disabled. 
         [0017]    A serial interface may be provided that may include a serial data input, a flow-control input, and circuitry configured for setting the interface in a low-power state at the end of a message received on the serial data input, and waking-up the interface to a live state from the low-power state when the flow-control input is enabled. 
         [0018]    According to an embodiment, the circuitry is further configured for retrieving a message length conveyed in a header of the message received on the serial data input, and identifying the message end by comparing the received data count to the message length. 
         [0019]    A serial interface may be provided that may include a serial data output, a flow-control output and a flow-control input, and circuitry configured for transmitting a message on the data output, disabling the flow-control output before the end of the message, and setting the interface in a low-power state when the flow-control input is disabled. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1  schematically shows a conventional full-duplex serial communication system in accordance with the prior art. 
           [0021]      FIG. 2  is a diagram showing an exemplary message transmission sequence between the two serial interfaces of  FIG. 1 . 
           [0022]      FIG. 3  is a diagram showing an exemplary message transmission sequence between two interfaces implementing a low-power state control protocol in accordance with an embodiment of the present invention. 
           [0023]      FIG. 4  is a diagram showing an exemplary bidirectional message transmission sequence between the two interfaces implementing a low-power state control protocol in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0024]    A protocol is disclosed herein that allows transmitting bidirectional low-power state control commands between serial interfaces, over a pair of lines that are conventionally used for flow-control, such as the RTS/CTS lines used in UARTs. 
         [0025]      FIG. 3  is a diagram showing an exemplary message transmission sequence between two interfaces SIF 1  and SIF 2  implementing such a protocol, in similar conditions as in  FIG. 2 . The signals and lines are named according to the corresponding input/output terminals of interface SIF 1 . 
         [0026]    Initially, both interfaces are in a low-power state (LoPw), such as with their clock signals turned off. The interfaces are thus unable to process incoming data, whereby the RTS and CTS signals are both inactive (at “1”). Eventually, interface SIF 1  needs to transmit data to interface SIF 2  through line TX. Interface SIF 1  is awoken locally, for instance by a local host processor, and activates signal RTS (pulling it to “0”). The activation of signal RTS represents a wake-up command (WU) for interface SIF 2 . Interface SIF 2  responds by awakening and activating signal CTS at a time t0, indicating that it is ready to receive data. 
         [0027]    From time t0, both interfaces are live. Interface SIF 1  starts transmitting data through signal TX. At a time t1, like in  FIG. 2 , the remote interface SIF 2  may disable signal CTS to indicate that it can no longer receive data. Interface SIF 1  responds by suspending the message transmission after the current atomic data unit. When the remote interface SIF 2  is ready to receive data again, it activates signal CTS at a time t2, from which the interrupted transmission may resume on line TX. 
         [0028]    The waveforms of signals RTS, CTS and TX are similar to those of  FIG. 2  up to time t2. However, the activation of signal RTS does not only mean that interface SIF 1  may receive data; it has the additional role of waking-up the remote interface SIF 2 . 
         [0029]    At a time t3, before the end of the message transmission, the interface SIF 1  disables signal RTS even though it may be ready to receive data. This particular event prepares the interface SIF 1  to switch into its low-power state at the end of the message, awaiting a confirmation by the remote interface. 
         [0030]    When the full message is received by the remote interface SIF 2  at a time t4, the interface SIF 2  disables signal CTS and switches into its low-power state. Interface SIF 1  takes the rising edge of signal CTS as the expected confirmation and switches in turn into its low-power state. 
         [0031]    The remote interface SIF 2  is thus configured to identify when the “full message” is received, i.e. identify an end-of-transmission EoT. A message usually includes a header that indicates the length of the message. Thus the remote interface may keep track of the current number of bytes received for the message, and it registers an end-of-transmission when the last byte of the message is received. 
         [0032]    With this configuration, the interface SIF 2  would switch into the low-power state after each message. In practice, however, a transmission may include a sequence of closely spaced or even contiguous messages, because the amount of data to be sent may not fit in one message. In this situation, going through a low-power state after each message would increase the time intervals between messages, and thus reduce the data transmission rate. 
         [0033]    To avoid this situation, the message headers may be designed to include an end-of-transmission flag that is set only in the last message of a transmission sequence. The remote interface is then configured to read this flag in each message and disable signal CTS only at the end of the message having the flag set. 
         [0034]    The event of signal RTS going high while the transmission on line TX is unfinished may occur in normal circumstances where interface SIF 1  would request interface SIF 2  to stop sending data. The above-described operation does not interfere with this. Therefore the offset between the time t3 when signal RTS is disabled and the time t4 when the full message is received is preferably as small as possible to shorten the time interval t4-t3. Indeed, during this interval, signal RTS is disabled and prevents interface SIF 2  from sending data to interface SIF 1 . 
         [0035]    Optimally, the offset thus corresponds to an atomic data unit, i.e. the smallest unit that will still be transmitted after a flow stop signal (signal CTS going high). The atomic data unit is often a “character” or byte. The figures show such a choice of the offset. 
         [0036]    The right-hand side of  FIG. 3  illustrates an exemplary circuit for controlling the low-power state of interface SIF 2 . A similar circuit would be provided in interface SIF 1 . An AND gate  10  receives the signals RTS and CTS. The output of gate  10  produces a low-power state switch signal LP that is at “1” only when both signals RTS and CTS are high, i.e. inactive. Signal LP is fed to a first input of an OR gate  12 . A second input of gate  12  receives a system clock signal CK. Gate  12  thus produces an internal clock signal CK′ for the interface, that is turned off when signal LP is high. Signal CTS may be controlled by a state-machine SM that takes into account signals RTS and TX to conform signal CTS to the previously described protocol. The state-machine may be a modified version of one included in a standard interface. 
         [0037]      FIG. 4  is a diagram showing an exemplary bidirectional message transmission sequence between two interfaces implementing the same protocol. This figure is intended in particular to demonstrate that the above protocol is compatible with a bidirectional transmission. 
         [0038]    In addition to the signals of  FIG. 3 ,  FIG. 4  shows signal RX representing data received by interface SIF 1  from interface SIF 2 . Up to time t0, the events are similar to those of  FIG. 3 . 
         [0039]    From time to, interface SIF 1  sends a message to interface SIF 2  on line TX and also receives a message from interface SIF 2  on line RX. At a time t1′, interface SF 1  disables the RTS signal to stop the incoming transmission on RX. This event happens while the outgoing transmission on TX is ongoing. 
         [0040]    Signal RTS is enabled again at a time t2′. Interface SIF 2  resumes the transmission on line RX. The ongoing message transmission on line TX does not reach its end between times t1′ and t2′, therefore the interface SIF 2  does not detect an end-of-transmission, although signal RTS is high, and does not disable signal CTS to go into the low-power state. 
         [0041]    Times t3 and t4 mark a low-power switching phase, as in  FIG. 3 . At time t3, interface SIF 1  disables signal RTS while one byte remains to be transmitted for the message on line TX (it is assumed that one byte is the atomic data unit). This event is also interpreted by interface SIF 2  as a flow stop signal, in a standard manner, whereby interface SIF 2  reacts by suspending the transmission on line RX, after the current, atomic byte. 
         [0042]    At time t4, as soon as the last byte of the message is received, interface SIF 2  disables signal CTS and switches into low-power state. Interface SIF 1 , seeing both signals RTS and CTS high, in turn switches into low-power state. However, interface SIF 2  still has data to send—the situation is similar to that of interface SIF 1  in  FIG. 3 . Interface SIF 2  is awoken locally and enables signal CTS at a time t5. Interface SIF 1  interprets this as a wake-up event, goes live, and enables signal RTS at a time t6. At this point, interface SIF 2  continues the transmission on line RX. 
         [0043]    In this situation, the interface SIF 2  “knows” it still has data to send, and the interface SIF 1  “knows” it still has data to receive (because the received byte count has not reached the message length conveyed in the message header). It is then preferable that the interfaces do not actually go through their low-power state, because the wake-up delays (t4-t5 for interface SIF 2 , and t6-t5 for interface SIF 1 ) may be non-negligible. Since each interface “knows” that it needs to stay awake, it may immediately enable signal RTS or CTS after it was disabled, reducing the delay to one system clock cycle. 
         [0044]    At a time t7, one byte before the end of the transmission on line RX, interface SIF 2  disables signal CTS Interface SIF 1  awaits the last byte on line RX, then disables line RTS at time t8. With both lines RTS and CTS being high, both the interfaces switch into low-power state. Times t7 and t8, for interface SIF 2 , are analogous to times t3 and t4, for interface SIF 1 . 
         [0045]      FIG. 4  reveals, between times t3 and t4, the optimal choice of the offset between the rising edge of signal RTS and the end of the message. This offset is one byte (or one atomic data unit), so that the transmissions on both lines TX and RX stop at the same time. If the offset were chosen smaller, time t4 would occur before the interface SIF 2  has fully transmitted one byte. The last bits of the byte would be lost as interface SIF 2  goes into low-power state. This data loss could be reduced or avoided by additional circuitry for delaying the low-power state switching. If the offset were chosen bigger, this would lengthen the interval t4-t3, reducing the global data rate of the link. 
         [0046]    In exceptional circumstances, the ends of transmission EoT on lines RX and TX could be simultaneous, i.e. lines RTS and CTS would both be disabled at the same time. With the simplified circuit of  FIG. 3 , this would immediately put both interfaces in the low-power state, whereby the last byte of each transmission (TX, RX) would be lost. To avoid this, each interface may be configured to remain live until the last byte of the current incoming message has effectively been received.