Abstract:
Method and system that produce requisite drive signals to fully exercise and test electromechanical elements of a liquid rocket stage including solenoid valve drives, DC motor drives and actuator drive signals. The electrical driver tester includes a signal processor, power driver circuits, and A/D and D/A circuits to monitor and control the drive circuitry. Drive current is monitored and a signal proportional to the current is produced for the purpose of analyzing current profiles as part of the test regimen for the device under test. Actuator speed and positioning are controlled in real time with a tailored lead lag control algorithm implemented with digital signal processor hardware.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority of U.S. provisional patent application Ser. No. 61/644,490 filed May 9, 2012, which is incorporated by reference herein. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to the field of automatic test systems for testing electromechanical components, including but not limited to solenoid valves, direct current (DC) motors and DC actuators, and more particularly, to automatic test equipment for evaluating operational characteristics of such electromechanical components within a liquid rocket stage assembly. To the extent different, the present invention also relates generally to devices and methods for testing components of electromechanical systems. 
     BACKGROUND OF THE INVENTION 
     Automated test equipment for testing the performance of rocket stage electromechanical components has been available for a number of years and is well established. Equipment is available to determine the characteristics of such components, such as valve open/close times, motor speed, motor friction, electrical noise and positioning accuracy. 
     The previous systems often utilized analog control circuitry that requires an intermediate system of interface circuitry between a test computer and an actuator control system. 
     As examples in the prior art, U.S. Pat. No. 6,876,942 (Hagerott et al.) describes methods and systems for enhanced automated system testing, and U.S. Pat. No. 7,457,717 (Davidson) describes a system for trouble shooting and verifying operation of spare assets. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a more accurate and simpler system, than one that uses analog control circuitry as in the prior art, and/or that has a fully digital design with a direct digital data transfer between a test computer and an electromechanical device driver tester. 
     A method in accordance with the invention includes analog interfacing circuits, digital processing hardware and purpose-designed software algorithms to accurately control motor velocity and/or positioning. The design and method calculate in real-time, an optimal drive signal to control the velocity and/or position of the electric motors. The motor parameters of current, velocity and/or position are produced so they may be electrically monitored. These parameters may also be read directly from the device over a computer backplane. 
     Other objects, features and characteristics of the present invention, as well as methods of operation and functions of related elements of the structure, the combination of parts and economics of manufacture will become more apparent upon consideration of the following detailed description and appended claims with reference to the accompanying drawings, all of which form a part of this specification. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following drawings are illustrative of embodiments of the invention and are not meat to limit the scope of the invention as encompassed by the claims. 
         FIG. 1  shows a functional block diagram of the present invention showing three types of circuit drivers. 
         FIGS. 2A ,  2 B and  2 C show circuitry being tested by this device, wherein  FIG. 2A  is a schematic of a two-port solenoid valve that controls two gases flowing into a common chamber,  FIG. 2B  is a schematic of the actuator device that is driven by an actuator driver showing extend and retract motors and a feedback transformer that generates feedback from a reference signal dependent on actuator shaft position, and  FIG. 2C  is a schematic of the motor driven switch showing a common contact and multiple output contacts that sequentially engage as the motor moves the shaft from an open position to a close position. 
         FIG. 3  shows the command interpreter that receives all the device commands over a VXI backplane. 
         FIG. 4  shows a schematic of the electromechanical driver circuitry used to drive the devices shown in  FIGS. 2A ,  2 B and  2 C, including the discrete drivers that are used to drive the motor switch and solenoid valves, a schematic of the actuator driver used to drive the actuators, extend and retract portions of the driver, the reference excitation signal and the feedback interface. 
         FIGS. 5A ,  5 B,  5 C and  5 D are software algorithm diagrams for the actuator driver, wherein the software is state-driven with differing tasks accomplished during the fixed timing cycle based upon the current operational state. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Preferred embodiments of the invention will be described with reference to  FIGS. 1-5D  wherein the same reference numerals refer to the same or similar elements. 
       FIG. 1  is a block diagram of an example of a basic circuit  10  used in the present invention. The circuit  10  contains three different types of drivers, valve or solenoid drivers  12 , actuator drivers  14 , and a switch motor driver  16 , only one of which is shown in  FIG. 1 . The number of each type of driver can vary depending on the needs and use of the systems. There may be multiple instances of each of the driver types. In some embodiments, the circuit  10  could be designed with less than all three types of drivers, as well as with one or more additional types of drivers. Also, the circuit  10  may be designed with all three different types of drivers but, during operation, use only one type or only two types. 
     The device in accordance with the invention preferably uses a common drive voltage from a source thereof  18 , for all of the drivers  12 ,  14 ,  16  so that changing this common drive voltage from source  18  causes changes in the drive voltage to all drivers  12 ,  14 ,  16  simultaneously. Each driver  12 ,  14 ,  16  has a pair of analog sense lines  20 ,  22  to monitor the drive voltage and current, respectively. These drive voltage and current signals may be monitored with test instruments, such as digital multi meters or oscilloscopes, to determine device performance characteristics, including but not limited to valve opening and closing times represented by the output from the valve drivers  12 , motor spin rates, actuator accuracy and brush noise. To this end, the sense lines lead to a connector  7  on the backplane 
     Loads are provided as part of the device to determine if each of the drivers  12 ,  14 ,  16  is functioning within its ratings. Thus, there are driver self-test loads  6  leading to a connector  5  on the backplane as shown in  FIG. 1 . 
     As also shown in  FIG. 1 , a control logic  8  is provided between one or more VXI backplane connectors  46  and the drivers  12 ,  14 ,  16 . The control logic  8  provides various signals to the drivers  12 ,  14 ,  16 , e.g., a respective set of valve enable and hold current setting signals to each valve driver  12 , a respective set of seek position and seek enable signals to each actuator driver  14 , and an enable signal to each switch motor driver  16 . The control logic  8  may comprise a microprocessor as well as other computer hardware and/or software necessary to implement the invention, which hardware and/or software would be readily identifiable by one skilled in the art without undue experimentation. More generally, the control logic  8  may be referred to as a processor or processor means. 
     Each valve driver  12  provides valve open and close signals via lines  13 . Each actuator driver  14  provides and receives several signals via lines  15 , such as providing an extend, retract, common and reference signals and receiving a feedback signal. Each switch motor driver  16  provides a close drive, open drive and switch common signals via lines  17 . 
     Additional features of the valve driver  12  include the configuration of the valve driver  12  to include or supply a high current FET switch that connects the power of the test system including circuit  10  to the valve under test, e.g., valve  24  discussed below. Additionally or alternatively, the valve driver  12  can supply a programmable current to the valve under test. The current serves to model as the worst case leakage current of the valve under test at the system level. Additionally or alternatively, the valve driver  12  may be configured to supply a matching network of zener diode and snubber resistor such that the valve hysteresis current does not produce large voltage spikes at the FET switch/driver. Moreover, current and voltage through the valve under test are available as analog signals such that these signals may be further monitored by analog test instruments for electro mechanical parametric measurements of valve open time, valve closing time and losses within the valve. The manner in which such signals may be processed to enable review are known to those skilled in the art to which the invention pertains. 
     Additional features of the actuator driver  14  include the configuration of the switch motor driver  16  to include or supply a high current FET switch that connects the test system power to the extend and retract motor of the actuator under test, e.g., actuator  26  discussed below. Additionally or alternatively, the actuator driver  14  may be configured to supply a programmable current to the actuator under test. The current is generated by switching the FET switch or switches at a constant frequency with a pulse width modulation (PWM) methodology to control the acceleration and speed of the actuator. Additionally or alternatively, the actuator driver  14  may be configured to supply a matching network of zener diode(s) and snubber resistor(s) such that the extend and retract motor hysteresis current does not produce large voltage spikes at the FET driver. The voltage to the extend and retract motors and the combined current of both motors for each actuator under test are available as analog signals such that these signals may be further monitored by analog test instruments for electro mechanical parametric measurements of actuator lag, rate, position accuracy, motor brush noise and losses within the motors. The manner in which such signals may be processed to enable review are known to those skilled in the art to which the invention pertains. 
     Using the control logic, additional control schemes involving the actuator drivers  14  are possible. For example, the control logic  8  may be configured to accurately position the actuators  26  with a minimum overshoot or undershoot in actuator positioning and/or actuator control current, to fold back the drive current at the end stops of the actuator so that damage to the mechanical end stops is prevented and to accurately measure the actuator position digitally over the VXI bus interface. 
     Additional features of the switch motor driver  16  include the configuration of the switch motor driver  16  to include or supply a high current FET switch that connects the test system power to the motorized switch under test, e.g., switch  38  discussed below. Additionally or alternatively, the switch motor driver  16  can supply a matching network of zener diode(s) and snubber resistor(s) such that the motorized switch hysteresis current does not produce large voltage spikes at the FET driver. Moreover, current and voltage through the motor switch under test are available as analog signals such that these signals may be further monitored by analog test instruments for electro mechanical parametric measurements of motor voltage, motor current and/or motor brush noise. The manner in which such signals may be processed to enable review are known to those skilled in the art to which the invention pertains. 
       FIG. 2A  is a schematic of a two-port solenoid valve  24  that is often used in a rocket stage to simultaneously open fuel and oxidizer valves to provide a combustible mix of fuel and oxidizer to a rocket engine thrust chamber, and its representation is understood by those skilled in the art. The solenoid valve  24  is driven by the one of the valve drivers  12  via the lines  13  depicted in  FIG. 1 . Other uses of the two-port solenoid valve  24  are also envisioned as being within the scope and spirit of the invention. 
       FIG. 2B  is a schematic of an actuator  26  with dedicated extend and retract motor terminals  28 ,  30 , respectively. When the extend terminal  28  is provided with power or energized, a schematically represented actuator rod  32  of the actuator  26  extends outward (moves in the direction of arrow A) and when the retract terminal  30  is provided power or energized, the actuator rod  32  retracts inward (moves in the direction of arrow B). The reference signal  34  is typically an AC signal that drives a variable transformer  34 . The transformer secondary  36  is mounted on the actuator rod  32 , preferably such that maximum feedback values are obtained at the maximum extend or retract positions of the actuator rod  32  and a null value is obtained at a center position of the actuator rod  32 . The position feedback signal obtained from the transformer secondary  36  is either “in phase” or “out of phase” with the reference signal driving the transformer  34  at the maximum extend and retract positions. The actuator  26  is driven by the actuator drivers  14 , i.e., the extend and retract motor terminals are coupled to the corresponding lines  15  from one of the actuator drivers  14  shown in  FIG. 1 . Similarly, the common terminal is coupled to the respective common one of the lines  15  from the actuator driver  14  shown in  FIG. 1 , and the reference signal terminal is coupled to the respective reference signal one of the lines  15  from the actuator driver  14  shown in  FIG. 1 . Finally, the position feedback signal is provided to the actuator driver  14  via the respective one of the lines  15 , see  FIG. 1 . 
       FIG. 2C  is a schematic of a motor driven switch  38  with dedicated open and close terminals  40 ,  42 , respectively. When the open terminal  40  is provided power, a ganged switch  44  is moved to the all open position and when the close terminal  42  is provided power, the ganged switch  44  is moved to the all close position. The motor driven switch  38  may be driven by the switch motor driver  16  shown in  FIG. 1 . In particular, the open terminal to, close terminal  42  and common terminal are coupled to the corresponding lines  17  from one the switch motor driver  16  shown in  FIG. 1 . 
       FIG. 3  shows a software flow diagram of a command interpreter in accordance with an exemplifying embodiment of the invention. This flow diagram may be executed by a processor, including control logic  8  in  FIG. 1 , accessing a computer program embodied on non-transitory computer-readable media which is configured to provide the steps of the flow diagram. 
     After a start stage  48 , commands are received, step  50 , over VXI backplane connectors  46  shown in  FIG. 1 . The control logic  8 , also shown in  FIG. 1 , receives and decodes each received command, step  52 , and when necessary, sends control logic signals via lines  21 ,  23 ,  25  to control the three different types of drivers  12 ,  14 ,  16 , and self-test loads (driver self-test loads  6  shown in  FIG. 1 ) of this invention. The test loads  6  may be switched to, for example, the valve drivers  12 , for the purpose of self-testing of the valve drivers  12 , the actuator drivers  14  for the purpose of testing the actuator drives and the switch motor driver  16  for the purpose of testing the switch motor driver  16 . The switching may be performed via the VXI backplane, or in any other manner known to those skilled in the art to which this invention pertains. 
     Command data consists of, for example, on/off enable settings for each driver  12 ,  14 ,  16  of the device  10 , but the particular enable setting signals may differ for the different drivers  12 ,  14 ,  16 . Additionally, the seek position data for each actuator driver  14  is set-up prior to giving the actuator-enable signal that enables the actuator control algorithm shown in  FIGS. 5A-5D . 
     More specifically, if in step  52 , the command is determined to be a “WRITE” command by the control logic  8 , a driver parameter is set in step  54  and the flow diagram ends in step  56 . If in step  52 , the command is determined to be a “READ” command by the control logic  8 , the queried data is set to an output register in step  58 , a pause is taken at step  60  until a determination is made by the control logic  8  that data is read at  62 , and after data is read in step  62 , the flow diagram ends in step  56 . 
     The “WRITE” and “READ” commands are exemplifying, non-limiting commands and other commands may be determined and processed accordingly by the control logic  8 . 
       FIG. 4  shows a top level schematic of a preferred embodiment of the invention, utilizing a Digital Signal Processor (DSP)  64  in a closed loop control system  66 . The control system  66  is used to perform, for example, the control algorithms detailed in  FIG. 5  to efficiently drive an actuator to a preprogrammed seek position. The system  66  includes the Digital Signal Processor  64  with floating point arithmetic capabilities connected via a parallel expansion bus to a Field Programmable Gate Array (FPGA)  68  used to expand the input/output of the DSP  64 . 
     The DSP  64  contains, preferably in FLASH memory, all system functions and actuator seek algorithm. System functions include a VXI communication interface FPGA  70 , actuator motor control  72 , and all timing needed by other devices. Control system  66  also includes actuator drivers  74 , sampling analog-to-digital (A/D) converters  76 , dynamic actuator performance parameters D/A converters  78  and a direct digital synthesis (DDS) reference waveform generator  80 . 
     The DDS reference waveform generator  80 , a multiplying DAC  82 , and a high voltage operational amplifier  84  form a precision sine wave signal reference source which drives the primary input transformer of the actuator reference signal input. 
     An attenuator network  86 , a precision differential A/D buffer/driver  88  and an 18 bit A/D converter  90  form a means to sample and re-construct the transducer reference source. This is required in order to determine plus or minus actuator position. 
     A positional transducer feedback input stage is formed from switching gain attenuator networks  92 , precision differential A/D buffer/drivers  94 , one for each switching gain attenuator network  92 , and an 18 bit A/D converter  76 , one associated with each buffer/driver  94 . The FPGA  68  serves as the ADC timing control and serial input register to hold the A/D conversion results. The DSP  64  is configured to trigger conversion to the FPGA  68  and reads the conversion results. 
     The DSP  64 , FPGA  68  and dynamic actuator performance parameters D/A converters  78  comprise dynamic analog signal sense points for the actuator angular position (theta) and instantaneous angular velocity (omega) and actuator input torque (tau). 
     Actuator motor control  72  or drivers, are preferably saturated, high-side MOSFET devices used to provide power to each coil in either actuator. 
     The VXI communication interface FPGA  70  is preferably a host register-based VXI controller. An ancillary RS232 communication port  93  coupled to the DSP  64  is used for diagnostic purposes. 
     A buffer  94  and a 16 bit A/D converter  76  comprise a current sensing mechanism in each actuator drive coil. Current sensing provides protection for the actuator and is used to indicate a stalled condition, for example, as in resting against a physical end stop. 
     A buffer  98  and high-side MOSFET driver devices  100  are used to provide power to or for both valve drivers and motor drivers  12 ,  16 . A 20 mA current source  102  is used to supply a leakage current for the valve drivers  12 . Both motor drivers  16  and valve drivers  12  preferably contain flyback diodes and inline resistors to match the impedance of the valve or motor being tested. 
       FIGS. 5A-5D  shows exemplifying software flows used for this invention. 
       FIG. 5A  shows an initialization process beginning with step  110 . In step  112 , the system FPGA registers are initialized and then in step  114 , the proportional/derivative (PD) control loop parameter structure is initialized. The serial peripheral interface (SPI) used for VXI communication is configured in step  116 . In step  118 , theta (representing position), and omega (representing velocity) envelope detector structures are initialized. The envelope structures maintain information about the angle and velocity signals. In step  120 , the internal DSP peripheral registers, timers, interrupts, external interfaces, etc. are initialized. The DSP flags and variables are initialized in step  122 . Input/output (I/O) ports of the DSP  64  are initialized in step  124 , which I/O control portions are for the motor drivers, LED&#39;s, etc. The signal sense DACs are initialized in step  126 , these are the angle and speed sensor DACs used by the test program. Finally, the DDS  80 , i.e., the transducer reference, is initialized in step  128 . The reference transducer is used to excite feedback signals to measure actuator position. Once the initialization stage is complete, the process continues to the main loop  130 . The manner in which the initialization and configuration steps are performed would be readily understood by one skilled in the art in view of the disclosure herein. 
       FIG. 5B  shows the software main loop and periodic tasks that are executed within this loop. In step  132 , a 20 micro second timer is processed and if a timer flag is determined to equal 1 in step  134 , the timer flag is set back to zero in step  140 . If not, a secondary loop is processed to determine whether a 1 millisecond (msec) timer flag has been tripped in step  136 . If not, the process returns to the main loop  130 . If so, the 1 msec timer flag is set to zero in step  138 . 
     From step  140 , the pitch, yaw and reference ADC&#39;s are triggered in step  142 , read in step  144  and a determination is made in step  146  whether the reference ADC is greater than zero volts. If so, in step  148 , the ADC bit weight is converted to degrees and in step  150 , the values for the current envelope are computed, i.e., pitch theta, pitch omega, yaw theta and yaw omega. Then the process proceeds to part  2  of the main loop  152 . If the reference ADC is not greater than zero volts, then the process proceeds to part  2  of the main loop  152 . 
     In part  2  of the main loop  152 , pitch theta, pitch omega, yaw theta and yaw omega are computed and may be scaled if so desired in step  154 . In step  156 , pulse width modulator (PWM) counters are incremented, which pulse width modulators are used to control the device to the actuator transistors. The PWNM duty cycle counters are processed in step  158 , and a determination is made in step  160  whether any are equal to zero. If so, the PWM duty cycle counters are re-initialized in step  162 . 
     Actuator drive portions are turned off or on in step  164 , and a process is started in step  166  to seek parameters, i.e., a proportional/derivative actuator (PD_Actuator) process is started. A PD_Actuator_control process is executed in step  168  for the yaw condition and in step  170  for the pitch condition. In step  172 , SPI I/O command on the VXI interface is tested for and a determination is made whether a VXI command request is present in step  174 . This means that a check is made for an incoming command over the VXI interface. If not, the main loop ends at  182 . On the other hand, if a command is present. The VXI command is executed at  176 , and a determination is made at  178  whether data must be transmitted to the VXI interface. If not, the process ends at  182 . If data is to be transmitted, the data is written to the VXI interface at  180  and then the process ends at  182 . 
       FIG. 5C  shows detail of the actuator seek position control loop showing a preferred embodiment of two actuator control techniques with the use of predefined conditional states. These control stages are executed in steps  168  and  170  in  FIG. 5B . The general actuator control algorithm for pitch/yaw may be executed every 1.0 msec. First, a determination is made at  184  whether pitch or yaw is being controlled. If yaw, the yaw parameter structure is pointed to at  186 . If pitch, the pitch parameter structure is pointed to at  188 . The parameter structure holds information about a control loop gains, timeout variables, present/seek angles and position and velocity values. 
     In step  190 , an omega sensor signal (average samples) is de-noised and Omega_avg is computed. Omega (velocity) is derived from the position (theta) feedback and tends to be noisy due to the derivative nature (high pass filters) and is preferably averaged to obtain a stable measurement. 
     In step  192 , a determination is made as to whether a seek timeout counter overflows, and if not, a determination is made in step  194  as to whether the actuator is against a stop. If not, a proportional effort (E_p) is computed in step  196 , which equals a seek angle less the current angle. 
     If in step  192 , the seek timeout counter overflows, the process proceeds to step  200 , subroutine S 131  (see  FIG. 5D ). Also, if it is determined in step  194  that the actuator is against a stop, the process proceeds to set a stalled error status in step  198  and then proceeds to step  200 , subroutine S 131 . 
     Subroutine S 131  functions to end the seek turn off divers and set the proper status. As shown in  FIG. 5D , in step  200 A, the actuator is disabled and the driver transistors are turned off. The position_mode_count is then set to zero in step  200   b  and the process returns to subroutine S 0 , step  248 . 
     From step  196 , a determination is made whether the state is equal to eight in step  202 , and if not, the position mode control operates to set an ERR variable to the proportional error (E_p), and continues to the second part  208  of the process. If state is equal to eight, then the ERR variable is set in step  206  to )E_p*Kp)+(OMEGA_dmd-OMEGA-avg)*Kd. This constitutes a calculation of the PD error signal wherein OMEGA-dmd is the look-up table (LUT) demand velocity. 
     In the second part  208  of the process, sense DAC values are calculated for the position (theta), velocity (omega) and torque (tau). In step  210 , the variables Theta, Omega and Tau are then written to the sensor DACs in step  212 . The process then meanders through a control loop state table. 
     If the State is equal to one as determined in step  214 , the process proceeds to subroutine S 0 , step  216  (see  FIG. 5D ). In subroutine S 0 , the PD_Status is set to zero in step  216 A, a determination of whether there is a seek request is made in step  216 B and if not, the process returns in step  216 C. If there is a seek request, the process proceeds to subroutine S 4 , step  224 . 
     If the State is equal to four as determined in step  222 , the process proceeds to subroutine S 4 , step  224  (see  FIG. 5D ). In subroutine S 4 , seek timeout counters, driver switching mode parameters are initialized in step  224 A, Kp is set to Kp_LUT(E_P)*0.5 in step  224 B. The parameter Kp_LUT is the proportional gain defined in a look-up table (LUT). A determination is made at step  224 C whether the variable E_P is greater than or equal to the Theta_brk, which is defined as the breakpoint angle where the PD controller switches to the position mode. If so, the subroutine proceeds to subroutine S 8 , in step  228 . If not, in step  224 D, the proportional gain is boosted by K_turbo so that K−p equals K−P*K_turbo, and the subroutine proceeds to subroutine S 8 , in step  228   
     If the State is equal to eight as determined in step  226 , the process proceeds to subroutine S 8 , step  228  (see  FIG. 5D ). In subroutine S 8 , the trajectory velocity demand is obtained as a function of E_d and E−p in step  228 , wherein a determination is made as to whether the demand trajectory velocity is from a look-up table or a function of the E_p mode in step  228 A. If a function of the E_p mode, the variable OMEGA_dmd is calculated as E_p*K_s0 in step  228 D and the process proceeds to step  228 F. If a function of the look-up table, the variable OMEGA_dmd is calculated as OMEGA-LUT(E_d:E_p) in step  228 B, a determination is made as to whether the variable is at the floor or the ceiling of the table in step  228 C. If not, the process proceeds to step  228 F. If so, the minimum or maximum value for OMEGA_LUT is used in step  228 E. 
     In step  228 F, a determination is made whether E_P is less than or equal to 3.0 degrees. If so, the proportional gain parameter K_pt is enhanced in step  228 G and the derivative gain parameter K_dt is enhanced in step  228 H. The process proceeds to step  228 I, also when E_P is not determined to be less than or equal to 3.0 degrees. 
     In step  228 I, the closed loop prop gain K_p is calculated to be K_p0*K_pt, then in step  228 J, the closed loop prop gain K_d is calculated to be K_d0*K_dt, and in step  228 K, the PWM duty cycle count (PWM_dc_count) for the driver on time is obtained, e.g., in a range between greater than or equal to zero and less than or equal to 25. A determination is then made at  228 L as to whether E_P is less than or equal to 1.0 degree and if not, the process returns at step  228 M. If it is, the process proceeds to subroutine S 130 , in step  236 . 
     Referring back to  FIG. 5C , if the State is equal to one-hundred twenty-nine as determined in step  230 , the process proceeds to subroutine S 129 , step  232  (see  FIG. 5D ). In subroutine S 129 , a determination is made whether the PD_TIMEOUT counter expired, and if not, the process returns at step  232 B. If the counter expired, the process proceeds to subroutine S 132 , in step  232 C. 
     If the State is equal to one-hundred thirty as determined in step  234 , the process proceeds to subroutine S 130 , step  236  (see  FIG. 5D ). In subroutine S 130 , the position, mode test counters and PWM parameters are initialized in step  236 A and then the process proceeds to subroutine S 71 , in step  240 . 
     If the State is equal to seventy-one as determined in step  238 , the process proceeds to subroutine S 71 , step  240  (see  FIG. 5D ). In subroutine S 71 , a determination is made as to whether the E−P is greater than or equal to the seek angle target window in step  240 A and if not, the process returns at step  240 C. If E_p is greater than or equal to the seek angle target window, the variable PWM_dc_count is set to equal E_p*K_q0 in step  240 B and the process returns at step  240 C. 
     If the State is equal to one-hundred thirty-one as determined in step  242 , the process proceeds to subroutine S 131 , step  200  (see  FIG. 5D ), which is discussed above. 
     If the State is equal to one-hundred thirty-two as determined in step  243 , the process proceeds to subroutine S 132 , step  244  (see  FIG. 5D ). In subroutine S 132 , the position mode counter is incremented in step  244 A. A determination is made as to whether the position mode counter is greater than the maximum value in step  244 B. If greater than the maximum value, the process proceeds to S 0  in step  244 , and if not the process returns at step  244 D. 
     If the State does not equal any of the numbers mentioned above, the process returns at step  246 . 
     The structure and functionality disclosed above may be implemented using software and/or hardware and would be able to be constructed by one of ordinary skill in the art to which this invention pertains in view of the disclosure herein. Generally, the structure and functionality would be implemented using one or more electronic components and a program that controls and/or configures the electronic component(s) to provide the desired functionality. The drawings illustrate non-limiting exemplifying embodiments and other electronic components and configurations or assemblies of electronic components may also be used. 
     Several computer programs resident on transitory or non-transitory computer-readable media may be used in the invention. For example, one or more computer programs is/are designed to control the control logic  8  to cause testing drive signals to be generated by the drivers  12 ,  14 ,  16 , sense and monitor the current and voltage readings from the drivers  12 ,  14 ,  16 , monitor the feedback signals received by the actuator drivers  14 , perform the self-testing of the drivers  12 ,  14 ,  16  using the driver self-test loads  6 , if desired (see  FIG. 1 ), and initiate and set the control logic  8  to perform the command interpretation shown in  FIG. 3 . 
     In the context of this document, computer-readable media or medium could be any non-transitory means that can contain, store, communicate, propagate or transmit a program for use by or in connection with the method, system, apparatus or device. The computer-readable medium can be, but is not limited to (not an exhaustive list), electronic, magnetic, optical, electromagnetic, infrared, or semi-conductor propagation medium. The medium can also be (not an exhaustive list) an electrical connection having one or more wires, a portable computer diskette, a random access memory (RAM), a read-only memory (ROM), an erasable, programmable, read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disk read-only memory (CDROM). The medium can also be paper or other suitable medium upon which a program is printed, as the program can be electronically captured, via for example, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory. Also, a computer program or data may be transferred to another computer-readable medium by any suitable process such as by scanning the computer-readable medium. 
     Having thus described a few particular embodiments of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only, and is not limiting. The invention is limited only as defined in the claims and equivalents thereto.