Abstract:
A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application claims priority from U.S. Provisional Patent Application No. 61/983,276 filed on Apr. 23, 2014, which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Technical Field 
     This relates generally to a method, apparatus and system for an edge rate controlled output buffer. 
     Description of Related Art 
     Traditionally, low power and low voltage edge rate controlled buffers are inverter based output buffers. Such buffers tend to have high current peak due to shoot-through current, inductive supply noise due to large voltage drop, and electromagnetic interference (EMI) due to high output edge switching rates. 
     It is also challenging to control edge rate over PVT, due to non-linear edge rate behavior that is variable over process, voltage and temperature (PVT). Current approaches show input current signal dependent propagation delay, which creates large and unexpected mismatch between falling and rising transition. 
       FIG. 1  depicts a prior art approach using inverter staggered type edge rate. In such an approach, a precise clock scheme is needed to control accurate edge rate. In addition, the open-loop approach of  FIG. 1  is not suitable for large load change requirement, because it is difficult to have load independent control. As a result, the edge rate varies not only input control signal, but also capacitive load. 
       FIG. 2  depicts another prior art approach to implement for input current, T IN1  and I IN2 . Utilizing a simple feedback based buffer and having large Cdg non-linear capacitance of MP and MN causes the slope to be non-linear with a constant input signal. Hence, a large feedback capacitor (C F &gt;&gt;Cdg) must be used along with the large input current signal. This requires silicon large area and often creates large propagation delay in order to drive a large linear feedback capacitor C F . Since there is no direct charge initialization of the feedback capacitor C F , the startup voltage mismatch between the drivers (MP or MN) and the feedback initial voltage creates signal dependent propagation delay. This signal dependent delay will cause the crossing point distortion in an eye diagram test. As a result, the approach of  FIG. 2  is unable to accurately initialize feedback capacitance over PVT in order to achieve signal insensitive propagation delay. 
     Therefore, there is a need for an accurate and improved control edge rate control over process, voltage and temperature that minimizes signal dependent startup time in order to achieve good signal integrity. 
     SUMMARY 
     Embodiments include a circuit for minimizing variation over process, voltage and temperature for edge rate and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The appended drawings illustrate example embodiments. 
         FIG. 1  depicts a prior art approach using inverter staggered type edge rate. 
         FIG. 2  depicts another prior art approach using a separate feedback capacitor for MP and MN. 
         FIG. 3  depicts two buffers generating differential signaling. 
         FIG. 4  depicts an edge rate controlled output driver circuit of example embodiments. 
         FIGS. 5A and 5B  respectively depict a first current/voltage generator and a second current/voltage generator of the edge rate controlled output driver circuit of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments include a method, apparatus and system of insensitive parasitic capacitance of drivers for low voltage, low power applications that accurately control edge rate over process and temperature and provide for a signal independent propagation delay to help maintain good differential signal integrity. 
       FIG. 3  depicts two buffers generating differential signaling, with different startup times of drivers causing the crossing point to shift. As shown in  FIG. 3 , “turning on” time mismatch will largely vary the crossing point when two buffers generate differential signaling. Traditionally, trimming the input current does not solve the problem. In some cases, it may alleviate the trimming; however, it will vary over process, voltage and temperature (PVT). This also causes the crossing point distortion, which is undesirable. 
     In differential signaling, the crossing point (of two signals Vout,p and Vout,n of  FIG. 3 ): should not vary much over process, supply voltage, and temperature; and is desirably in the middle of a valid supply range for good signal integrity. In one example, if trimming is used to meet edge rate specifications, then time delay may be associated with this trimming. This delay associated with trimming may affect the startup time of the amplifier, such that the crossing point may not occur at the desired crossing point range. In addition, this delay will vary across PVT. 
       FIG. 4  depicts an edge rate controlled output driver circuit of example embodiments.  FIG. 5A  depicts a current/voltage generator  402  of  FIG. 4 .  FIG. 5B  depicts a current/voltage generator  404  of  FIG. 4 . The circuit of  FIG. 4  has four states, which are:
         State0: Low to high voltage transition of V OUT , in which only S 1 , S 2 , S 8  and S 7  ( FIG. 5A ) switches are closed,   State1: High voltage output of V OUT , in which only S 1 , S 2 , S 3  ( FIG. 5B ) and S 8  switches are closed (Vp=Vthn),   State2: High to low voltage transition of V OUT , in which only S 5 , S 6 , S 3  ( FIG. 5B ) and S 4  switches are closed, and   State3: Low voltage output of V OUT , in which only S 5 , S 6 , S 7  ( FIG. 5A ) and S 4  switches are closed (Vp=VDD−Vthp).
 
In order to remove signal dependent propagation delay and to minimize propagation delay, Vp is equal to VDD−Vthp at the beginning of State0, and Vp is equal to Vthn at the beginning of State2.
       

     In  FIG. 4 , MN 2  and MP 2  are buffers, which are used to decouple large nonlinear parasitic Cgd of each driver MN 1 /MP 1  from C FB  (e.g., Cdg&gt;5-10×C FB ). MN 3  and MP 3  are also buffers, which are used for level shifting to help in low voltage applications (canceling the required voltage due to the buffers MN 2  and MP 2 ). The gate-source voltages of MN 2 /MP 3  (and of MP 2 /MN 3 ) are largely canceling out each other, so that the node Vp provides the required gate-source voltage of drivers MN 1 /MP 1 . 
     In one embodiment, the current/voltage generator ( 402  or  404 ) may convert from operating as a current generator (I IN1  or I IN2 ) to operating as a voltage generator, after V OUT  rails out. This is achieved by cascoding device with gate-source connected device. For example, referring to  FIG. 5B , S 3  is activated when S 1  ( FIG. 4 ) and S 2  are closed. Also, referring to  FIG. 4 , MP 1  and C FB  form capacitive feedback amplifier with a constant current to generate desired slew control of V OUT . The node Vp is constant during the slew controlled swing region because the circuit works as an integrator. After V OUT  swing reaches the positive rail (VDD), the switch S 3  ( FIG. 5B ) is turned on, and Vp node voltage is defined as being near Vthn (e.g., MN 1  device threshold voltage) rather than ground. Alternatively, if there were no gate-source connected device, then Vp node voltage would be near ground, so that the voltage across the feedback capacitor C FB  would be VDD, after V OUT =VDD. 
     In one embodiment, S 3  switch action is automatic and implemented in the same gate-source connected device to initialize charges on the feedback capacitor C FB  for signal independent startup of the drivers. For example, after Vp node voltage goes below the current reference voltage, the gate-source connected device becomes a diode-connected device, such that Vp node voltage is defined as being near Vthn (e.g., MN 1  device threshold voltage), after V OUT =VDD (as described in the immediately preceding paragraph). MN 1  driver will be turned on during the next state, so the initial voltage (VDD−Vthn) across the feedback capacitor C FB  is desired to remove signal dependent startup. 
     The circuit of  FIG. 4  benefits from controlling the edge rate of output signals that are generated by a transmitter or driver to eliminate any high order of harmonics to reduce EMI/EMC emission. The following are examples of such systems: USB 1.1 and USB 2.0 type of signaling drivers or any edge rate controlled digital data communication physical layer drivers, any capacitive touch screen controller drivers, and the like. 
       FIG. 5B  shows the gate-source connected device S 3 , which will be in “Off state” during transition. After V OUT  rails out and is ready for the next state, the gate-source connected device S 3  cancels the gate-source voltage of MN_I_IN_REF_CC 2 , so that the Vp node voltage is defined as being near Vthn. MN 1  and the current source I IN2  include the same type of device, so their threshold voltages can track well over PVT. As described hereinabove, for turning MN 1  on, the Vp node voltage is initialized to be near Vthn, which avoids the need to equalize the charge stored on the feedback capacitor C FB . As a result, the MN 1  amplifier has a quick startup (turning on) time with no signal dependent propagation delay. 
     Example embodiments help to minimize variation over PVT for edge rate and propagation delay. As a result, the improved circuit leads to a robust solution over PVT, signal independent propagation delay, low quiescent current consumption, low supply solution, insensitivity to nonlinear driver device capacitance, small form-factor, load insensitive edge rate control, minimization of undesirable handoff transient response, etc. 
     While the foregoing is directed to example embodiments, other and further embodiments are possible, within the scope of the claims.