Abstract:
Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to programmable logic devices (PLDs), and, more particularly, to specialized processing blocks which may be included in such devices. 
     As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof. 
     One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations. 
     For example, a PLD sold by Altera Corporation, of San Jose, Calif., under the name STRATIX® II includes DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed. In order to support four 18-by-18 multiplication operations, the block has 4×(18+18)=144 inputs. Similarly, the output of an 18-by-18 multiplication is 36 bits wide, so to support the output of four such multiplication operations, the block also has 36×4=144 outputs. 
     The operations performed by such DSP blocks frequently require rounding. However, known DSP blocks, including that provided in the aforementioned STRATIX® II PLD, have limited rounding capabilities. 
     It would be desirable to be able to provide improved rounding capabilities of the DSP block of a PLD. 
     SUMMARY OF THE INVENTION 
     The present invention relates to improved rounding circuitry for specialized processing blocks for PLDs. 
     As one example only, one type of specialized processing block with which the invention may be used is described in copending, commonly-assigned U.S. patent application Ser. No. 11/447,329, filed Jun. 5, 2006, which is hereby incorporated by reference herein in its entirety. Such a specialized processing block preferably includes a plurality of fundamental processing units instead of discrete multipliers. Each fundamental processing unit preferably includes the equivalent of at least two multipliers and logic to sum the partial products of all of the at least two multipliers. As a result, the sums of the all of the multiplications are computed in a single step, rather than summing the partial products of each multiplier to form individual products and then summing those products. Such a fundamental processing unit can be constructed with an area smaller than that of the individual multipliers and adders. If a single multiplication is required to be performed, one of the multipliers in the fundamental processing unit is used, while the inputs to the other(s) are zeroed out. Nevertheless, because the provision of the fundamental processing unit reduces the area of the specialized processing block, efficiency is improved. 
     In a preferred embodiment, the fundamental processing unit includes the equivalent of two 18-by-18 multipliers and one adder so that it can output the sum of the two multiplication operations. While each of the 18-by-18 multipliers can be configured for a smaller multiplication operation (e.g., 9-by-9 or 12-by-12), the integrated nature of the fundamental processing unit means that the individual multiplier outputs are not accessible. Only the sum is available for use by the remainder of the specialized processing block. Therefore, to obtain the result of a single non-complex multiplication that is 18 bits-by-18 bits or smaller, an entire fundamental processing unit must be used. The second multiplier, which cannot be disengaged, simply has its inputs zeroed. 
     The specialized processing block with which the invention may be used preferably also has one or more additional adders for additional processing of the output of the fundamental processing unit, as well as optional pipeline registers and a flexible output stage. Therefore the specialized processing block preferably can be configured for various forms of filtering and other digital signal processing operations. In addition, the specialized processing block preferably also has the capability to feed back at least one of its outputs as an input, which is useful in adaptive filtering operations, and to chain both inputs and outputs to additional specialized processing blocks. 
     The specialized processing block with which the invention may be used, as described in the above-incorporated patent application, preferably includes flexible rounding circuitry, which preferably allows the user to select between rounding to the nearest integer and rounding to the nearest even. As is known, rounding to the nearest even operates identically to rounding to the nearest integer, except when the remainder is exactly equal to one-half. In rounding to the nearest integer, when the remainder is exactly equal to one-half, the result always is rounded up to the next integer. In rounding to the nearest even, when the remainder is exactly equal to one-half, the result is rounded up if the next integer is even, but rounded down if the next integer is odd. The flexible rounding circuitry preferably also allows the user to select the bit position of the result at which rounding takes place. The location of the flexible rounding circuitry within the specialized processing block preferably also is selectable so that critical timing paths are not affected unnecessarily by rounding operations. 
     The present invention provides circuitry that preferably performs adding and rounding substantially simultaneously, and in any event preferably within a single clock cycle, to minimize delays in the critical timing paths. It should be noted, however, that such circuitry can be used in any application in which adding and rounding are performed within a critical timing path, and not only in the specialized processing block that is described above and in the above-incorporated patent application. 
     The present invention implements addition with a form of look-ahead rounding, adding two numbers together both with and without an input rounding bit, and then selecting the correct result at the end of the calculation. 
     The addition in question is an addition of two multi-bit numbers. In a preferred embodiment, for example, the adder inputs may be two 44-bit numbers. As stated above, the user can select the rounding position. Accordingly, there must be a range of bits encompassing the allowable rounding positions, where two or three numbers may be input, while in other positions only two numbers may be input. 
     According to one aspect of the present invention, the outputs of the all of the individual bit positions, regardless of whether there are two or three inputs at any particular bit position, are converted to sum and carry vectors for input to a two-input adder. In a preferred embodiment, this is accomplished by using, on each of the positions that may have two or three inputs, a 3:2 compressor to produce a sum vector and a carry vector, and using on each of the positions that may have only two inputs, a 2:2 compressor to produce a sum vector and a carry vector. Although a 2:2 compressor does not perform any actual compression (the number of outputs remains the same as the number of inputs), it converts the inputs to sum and carry vectors that are aligned with the sum and carry vectors from the three-input bit positions. 
     According to another aspect of the present invention, the compression is formed by a prefix network, such as a Kogge-Stone prefix network, in which each node may be a compressor. In a particularly preferred embodiment of this aspect of the invention, the nodes that perform 2:2 compression are ordinary 2:2 compressors. However, the nodes that may have either two or three inputs, and therefore may perform either 2:2 compression or 3:2 compression, preferably are specialized 3:2 compressors that may simultaneously perform both the 2:2 compression and the 3:2 compression. 
     Therefore, in accordance with the present invention, there is provided combined adding and rounding circuitry for a programmable logic device, for adding two multi-bit input numbers and rounding a resulting sum to a user-programmable bit position selectable from among a subset of available bit positions. The combined rounding and adding circuitry includes multi-bit addition circuitry, and input circuitry for (a) accepting, in each bit position, bits of the two multi-bit input numbers and (b) accepting, in each bit position in the subset, an additional input of a rounding bit. The input circuitry outputs data to the multi-bit addition circuitry in a format common to each bit position regardless of the number of inputs to the input circuitry at that bit position. 
     In a method according to the invention, for each bit position outside the subset, a bit from each of the multi-bit numbers is processed to produce a first output having a first number of output bits. For each bit position in the subset, a bit from each of the multi-bit numbers is processed with a rounding input to produce a second output having that first number of output bits. The first and second outputs are combined to produce a rounded sum. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a high-level diagram of one preferred embodiment of a specialized processing block with which the present invention may be used; 
         FIG. 2  is a functional diagram of the specialized processing block of  FIG. 1 ; 
         FIG. 3  is a block diagram of a preferred embodiment of a fundamental processing unit for a specialized processing block with which the present invention may be used; 
         FIG. 4  is a preferred embodiment of an output stage of a specialized processing block with which the present invention may be used; 
         FIG. 5  is a functional diagram of a specialized processing block with which the present invention may be used, configured as part of a finite impulse response filter; 
         FIG. 6  is a schematic diagram of a portion of a specialized processing block with which the present invention may be used showing a location of rounding logic in accordance with one embodiment of the present invention; 
         FIG. 7  is schematic diagram showing detail of the rounding adder in the rounding logic of  FIG. 6 ; 
         FIG. 8  is a diagram of a Kogge-Stone prefix network that may be used to implement the present invention; 
         FIG. 9  is a schematic diagram of a conventional 2:2 compressor; 
         FIG. 10  is a schematic diagram of a conventional 3:2 compressor; 
         FIG. 11  is a schematic diagram of a compressor that simultaneously performs 2:2 compression and 3:2 compression; 
         FIG. 12  is a diagram of a sparse Kogge-Stone prefix network according to an alternate embodiment of the invention; and 
         FIG. 13  is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Rounding is a technique for reducing the precision of a number by removing a lower-order range of bits from that number&#39;s representation and possibly modifying the remaining portion of the number to more accurately represent its former value. For example, if the original number has N bits of precision, the rounded number may have only M bits of precision (where N&gt;M), meaning that N−M bits of precision are removed from the number in the process of rounding. 
     The round-to-nearest method returns the closest number to the original. This is commonly referred to as “round-to-nearest-integer” (RNI), but as it works for numbers less than one as well, “round-to-nearest” is more appropriate. By convention, according to this method an original number lying exactly halfway between two numbers (and therefore having two numbers that are “nearest”) always rounds up to the larger of the two. For example, when rounding the 3-bit, two&#39;s complement fraction 0.25 (binary 0.01) to the nearest 2-bit two&#39;s complement fraction, this method returns 0.5 (binary 0.1). The original fraction lies exactly midway between 0.5 and 0.0 (binary 0.0), so this method rounds up. Because it always rounds up, this method is also called “biased rounding.” 
     The “convergent rounding,” or “round-to-nearest-even” (RNE), method also returns the closest number to the original. However, in cases where the original number lies exactly halfway between two numbers, this method returns the nearest even number, which in a binary representation is the one containing a least significant bit of 0. So for the example above, the result would be 0.0, since that is the even-numbered choice as between 0.5 and 0.0. Because it rounds either up or down based on the surrounding values rather than always rounding in the same direction, this method is also called “unbiased rounding.” 
     Some examples are shown in the following table, in which 6-bit numbers are rounded to 4-bits of precision: 
     
       
         
               
               
               
               
               
               
             
           
               
                   
               
               
                 Original 
                   
                   
                   
                   
                   
               
               
                 number 
                   
                 First 4 
                 Last two 
                 RNI Result 
                 RNE Result 
               
               
                 (decimal 
                   
                 bits odd 
                 bits &lt;/&gt; 
                 (decimal 
                 (decimal 
               
               
                 equivalent) 
                 Sign 
                 or even? 
                 one-half? 
                 equivalent) 
                 equivalent) 
               
               
                   
               
             
             
               
                 010111  
                 + 
                 Odd 
                 Greater 
                 011000 (24) 
                 011000 (24) 
               
               
                 (23) 
                   
                 (LSB = 1) 
                 (.11B = .75) 
                   
                   
               
               
                 001001  
                 + 
                 Even 
                 Less 
                 001000 (8) 
                 001000 (8) 
               
               
                 (9) 
                   
                 (LSB = 0) 
                 (.01B = .25) 
                   
                   
               
               
                 001010  
                 + 
                 Even 
                 Equal 
                 001100 (12) 
                 001000 (8) 
               
               
                 (10) 
                   
                 (LSB = 0) 
                 (.10B = .50) 
                   
                   
               
               
                 001110  
                 + 
                 Odd 
                 Equal 
                 010000 (16) 
                 010000 (16) 
               
               
                 (14) 
                   
                 (LSB = 1) 
                 (.10B = .50) 
                   
                   
               
               
                 110111  
                 − 
                 Odd 
                 Greater 
                 111000 (−8) 
                 111000 (−8) 
               
               
                 (−9) 
                   
                 (LSB = 1) 
                 (.11B = .75) 
                   
                   
               
               
                 101001  
                 − 
                 Even 
                 Less 
                 101000 (−24) 
                 101000 (−24) 
               
               
                 (−23) 
                   
                 (LSB = 0) 
                 (.01B = .25) 
                   
                   
               
               
                 110110  
                 − 
                 Odd 
                 Equal 
                 111000 (−8) 
                 111000 (−8) 
               
               
                 (−10) 
                   
                 (LSB = 1) 
                 (.10B = .50) 
                   
                   
               
               
                 110010  
                 − 
                 Even 
                 Equal 
                 110100 (−12) 
                 110000 (−16) 
               
               
                 (−14) 
                   
                 (LSB = 0) 
                 (.10B = .50) 
                   
                   
               
               
                   
               
             
          
         
       
     
     In any event, either of these forms of rounding involves, for a particular bit position, adding 0.5 10 —i.e., 1B in the next most significant place—to the result and then truncating, with the differences being (1) how to handle the situation where the remainder is exactly one-half, and (2) how to handle the fact that in any particular bit position, 1 may or may not be added, which is a user-selectable choice. Rounding circuitry must therefore be able to handle both the possibility that a 1 will be added, and the possibility that it will not. The present invention provides such circuitry. 
     The invention will now be described with reference to  FIGS. 1-12 , where  FIGS. 1-5  show an example of a specialized processing block in which the invention may be used. 
       FIG. 1  shows a high-level diagram of one preferred embodiment  10  of a specialized processing block with which the invention, while  FIG. 2  is a functional diagram of the same embodiment  10 , it being recognized that rounding logic according to the invention also can be used with any other circuitry that needs to be able to handle the possibility of either two or three inputs at a user-programmable choice of positions. 
     As seen in  FIG. 1 , specialized processing block  10  includes optional input pre-MUX stage  11 , optional input register stage  12 , optional input multiplexing stage  13 , multiplication stage  14 , optional pipeline register stage  15  and adder/output stage  16 . 
     The function of input pre-MUX stage  11 , if provided, is to format the regular inputs, loopback inputs and cascade inputs (see below) into a form suitable for registering. 
     Regular inputs do not require any specific formatting. Cascade inputs may be a one-register delayed version of a previous input, and therefore may need formatting accordingly. However, such formatting also can be done in programmable logic of the programmable logic device of which specialized processing block  10  is a part, so if formatting of cascade inputs is the only pre-MUX function required, input pre-MUX stage  11  can be omitted or, if provided, bypassed. The loopback input  17  may be arranged so that it is always connected to a particular multiplier or group of multipliers. The formatting performed by input pre-MUX stage  11  may include the direction of particular inputs to particular bit locations depending on the function to be performed by specialized processing block  10 . The formatting may be carried out in one embodiment according to a stored table identifying the various possible operations (e.g., simple or complex multiplications of various sizes, shifting operations, rotation operations, etc.) and specifying the corresponding formatting required. 
     The output of input pre-MUX stage  11 , if provided, may be registered by optional input register stage  12 . If there in no input pre-MUX stage  11 , then the input register function, if needed, can be performed in the programmable logic portion of the programmable logic device of which block  10  is a part. Therefore, input register stage  12  is considered optional. Input register stage  12 , even if provided, preferably can be optionally bypassed in cases where unregistered outputs are needed or desired. 
     Input multiplexing stage  13 , if provided, takes registered or unregistered inputs from input pre-MUX stage  11  and inputs potentially from elsewhere in the programmable logic device and formats the data for the different operational modes. In that respect it is similar to input pre-MUX stage  11 , and therefore frequently if one of input pre-MUX stage  11  and input multiplexing stage  13  is provided, the other will not be provided. 
     As one example of the type of formatting performed by input pre-MUX stage  11  or input multiplexing stage  13 , consider an 18-by-18 complex multiplication in which:
 
Real Result= Re [( a+jb )×( c+jd )]=( ac−bd )
 
Imag Result= Im [( a+jb )×( c+jd )]=( ad+bc )
 
This complex operation requires four 18-by-18 multiplications and hence eight 18-bit inputs, but because there are only four unique 18-bit shared inputs, input multiplexing stage  13  will take the inputs a, b, c and d and perform the necessary duplication so those four inputs are properly routed to the correct multiplier inputs for each of the real and imaginary calculations. Similarly, for 9- and 12-bit mode operations, input pre-MUX stage  11  and/or input multiplexing stage  13  ensures correct alignments of the input bits in order to obtain correct results.
 
     Multiplication stage  14  preferably includes a plurality of fundamental processing units as described above. In a preferred embodiment, each specialized processing block  10  (see  FIG. 2 ) includes four fundamental processing units  30 , meaning that it can perform up to eight multiplications in groups of two multiplications that are summed together. In that embodiment, the fundamental processing units in specialized processing block  10  preferably are grouped into identical half-blocks, so that each half-block in its own right can be considered a specialized processing block within the invention. 
     Each fundamental processing unit preferably includes the functionality for a sum of two 18-by-18 multiplications. The fundamental processing units preferably are all identical, but in some embodiments, it is possible to provide a negation function on only some inputs of some multipliers, as maybe required for, e.g., complex multiplication where, as is apparent above, subtraction may be required. Alternatively, the negation function may be provided in the adder portion of the fundamental processing unit, so that one or more adders can also perform subtraction. 
     The structure of a preferred embodiment of a fundamental processing unit is shown in  FIG. 3 . Each fundamental processing unit  30  preferably supports a sum of two 18-by-18 multiplications and preferably includes two partial product generators  31 , two ten-vector-to-two-vector compressors  32 , a 4-to-2 compressor  33 , and two carry-propagate adders  34 . Adders  34  preferably include one 30-bit adder  340  and one 24-bit adder  341 , which are selectably connectable by a control signal  342 . For smaller multiplications such as 9-by-9 or 12-by-12, only 24 bits are required, so the two adders can be disconnected to allow two independent multiplications. For larger multiplications such as 18-by-18, the two adders  34  should be linked as a single adder. 
     Each partial product generator  31  preferably creates nine 20-bit signed Booth-encoded vectors (Booth-encoding is a known technique that can reduce the number of partial products), as well as a 17-bit unsigned carry vector (negative partial products are in ones-complement format, with the associated carry-in bit in the carry vector). An additional 19-bit signed partial product may be generated in the case of unsigned multipliers (which preferably will always be zero for signed multipliers). Although preferably up to 11 vectors may be generated, the carry bits preferably can be combined with the partial product vectors, requiring only 10 vectors to be compressed. 
     The partial products preferably are compressed down to two 39-bit vectors (36 bits plus sign extension bits). Any sign extensions should be preserved properly past the 36-bit 18-by-18 multiplier boundary, so that any sign extensions can be valid up to the 72-bit 36-by-36 multiplier boundary (in a case where two fundamental processing units are combined to implement a 36-by-36 multiplication as described below). After compression, the results preferably are processed in mux-and-shift circuitry  35 , which preferably include combinatorial logic where any sign-extension, zero-filling or shifting of the results before addition, as may be required depending on the operation being performed, can be accomplished prior to final combination of the results in 4-to-2 compressor  33  and carry-propagate adders  34 . For each of circuits  350 ,  351 , the inputs preferably are two 39-bit vectors for a total of 78 input bits, while the outputs preferably are two 54-bit vectors for a total of 108 bits. The extra thirty bits are the result of sign extension, zero-filling, and or shifting. Multiplexer  352  indicates a selection between sign extended or zero-filled results. The four 54-bit vectors are input to compressor  33  which outputs two 54-bit vectors, which are added in adders  34  to produce a 54-bit output. 
     As discussed above, because the partial products from both multipliers are added at once, the two multipliers of a fundamental processing unit cannot be used for two independent multiplications, but a single multiplication can be carried out by zeroing the inputs of the second multiplier. 
     For smaller multiplications, independent subset multipliers (9-by-9 and 12-by-12 cases) may be handled as follows: 
     For two 9-by-9 multiplications, the first 9-by-9 multiplication preferably is calculated using the most significant bits (MSBs) of the first multiplier (on the left in  FIG. 3 ), and the second 9-by-9 multiplication preferably is calculated using the least significant bits (LSBs) of the second multiplier (on the right in  FIG. 3 ). The MSBs of the right multiplier are filled with the sign extensions of the corresponding values, as appropriate. The outputs of the left multiplier (sum and carry vectors) are left-shifted by 18 bits. The two multiplier outputs preferably are then compressed together and the two resulting final vectors are then added with the two adders  34 , which are not connected for this operation. The first 9-by-9 result preferably will be output on the MSBs of the left (30-bit) adder  340 , while the second 9-by-9 result preferably will be output on the LSBs of the right (24-bit) adder  341 . 
     Independent 12-by-12 multiplications can be calculated in a manner similar to a 9-by-9 multiplication, using the MSB/LSB method. 
     In both cases, preferably the right multiplier outputs are zeroed above 24 bits to prevent any interference with the independent left multiplier result. 
     In the case of summed multiplications, regardless of the precision, all inputs preferably are shifted to occupy the MSBs of the multipliers used, and the output vectors preferably are not shifted. The output vectors, however, preferably are fully sign-extended, so that sign-extension out of the adders  34  can be used for the full width of the accumulator (below). 
     Preferably, for complex multiplications and other operations that require subtraction of products, the adder inputs can be negated (effectively making the adder an adder/subtractor). Alternatively, however, one or more of the multipliers can be provided with the ability to selectively negate its output vectors, by inverting the input (ones&#39; complement), and adding the multiplicand to the result. The multiplicand addition can be performed in the compression of the partial products, so that the negation can be implemented before adders  34 . 
     Pipeline register stage  15 , which preferably may be bypassed at the user&#39;s option, preferably allows outputs of multiplication stage  14  to be registered prior to further addition or accumulation or other processing. 
     Adder/output stage  16  preferably selectively shifts, adds, accumulates, or registers its inputs, or any combination of the above. Its inputs preferably are the outputs of the two fundamental processing units in specialized processing block  10 . As seen in  FIG. 4 , those two inputs  40 ,  41  are input to respective register/shifter units  42 ,  43 , which optionally may shift or sign extend inputs  40 ,  41 . In a preferred embodiment, each of inputs  40 ,  41  is a 54-bit vector, which is shifted or sign-extended to create a respective 72-bit vector. 
     The outputs of units  42 ,  43  preferably are input to a 3:2 compressor  44 , along, preferably, with the output  45  of stage  16  itself. This feedback provides an accumulation function to specialized processing block  10 . Preferably, the fed-back output  45  passes through multiplexer  46 , which can alternatively select a zero (e.g., ground) input when accumulation is not necessary or desired. 
     The outputs of compressor  44  are provided (through appropriate multiplexers as described below) to two adders  47 ,  48 , which may be chained together under programmable control, depending on the use to which they are to be put, as described below. The outputs of adders  47 ,  48  preferably may be registered in registers  49 ,  400  or not, as determined by multiplexers  401 ,  402 . Registered or not, outputs  47 ,  48  preferably make up the output vector of specialized processing block  10 . As an alternative path, multiplexers  403 ,  404 ,  405  allow adders  47 ,  48  to be bypassed where the outputs of fundamental processing units  30  are to be output without further processing. 
     In the case, described above, where each fundamental processing unit  30  can perform a sum of two 18-by-18 multiplications, two fundamental processing units  30  can perform a 36-by-36 multiplication, which, as is well known, can be decomposed into four 18-by-18 multiplications. In such a case, two compressed 72-bit vectors preferably are output by compressor  44  and preferably are added together by the two 44-bit adders  47 ,  48 , which are programmably connected together for this mode by AND gate  406 . The upper 16 bits may be ignored in this mode. 
     In other modes with narrower outputs, where adders  47 ,  48  need not be connected together, adders  47 ,  48  optionally may be arranged to chain the output of specialized processing block  10  with the similar output of another specialized processing block  10 . To facilitate such a mode, the output of register  400 , for example, may be fed back to 4:2 multiplexer  407 , which provides two inputs to adder  47 . The other inputs to multiplexer  407  may be the two vectors output by compressor  44  and chain-in input  408  from another specialized processing block  10 , which may be provided via chain-out output  409  from register  49  of that other specialized processing block  10 . 
     Thus, in chaining mode, 44-bit adder  48  may be used to add together the results within one of specialized processing blocks  10 —configured, e.g., as a single multiplier, a sum of multipliers, or an accumulator.—with the results of the previous block. By using multiplexer  407  to select as inputs to adder  47  the output of adder  48  and the output of another specialized processing block  10 , the output of the current specialized processing block  10  can be the chained sum of the outputs of the current and previous specialized processing blocks  10 . If the chaining mode is used, only a 44-bit accumulator is available, which will still give a 6-bit to 8-bit guard band, depending on the number of multipliers. However, as is apparent, the chaining mode is not available for the 36-bit mode, in which both adders  47 ,  48  are needed to obtain the result of a single specialized processing block  10 . 
     The output paths may be slightly different depending on the mode of operation. Thus, multiplexers  401 ,  402  allow selection of registered or unregistered outputs of adders  47 ,  48 . It will be appreciated, however, that, as shown, registered outputs preferably are used in cascade or chained mode. 
     In addition, at least one output may be looped back, as at  17 , to an input of specialized processing block  10 . Such a loopback feature may be used, for example, if specialized processing block  10  is programmably configured for adaptive filtering. Although multiple loopbacks may be provided, in a preferred embodiment, one loopback  17  to single multiplier or group of multipliers is provided. 
     The specialized processing block  10  of the present invention may be programmably configured as a long chain finite impulse response (FIR) filter. As shown in  FIG. 5 , four fundamental processing units  30  are configured as part of such a FIR filter  50 . As discussed above, this may be considered to be either one or two specialized processing blocks  10 . As shown, each of adders  48  is used to add the results of four multiplications, with adders  47  used in the chaining or cascade mode described above to add together the outputs of adders  48  (as well, possibly, as the outputs of adders  48  of other specialized processing blocks  10 ) to form a long FIR filter. The coefficients of the FIR filter are input at  51 , while the data to be filtered are input via register chain  52 , preferably formed in one of input pre-MUX stage  11 , input register stage  12  or input multiplexing stage  13 . To account for delay introduced by the output cascade chain, at least one extra delay  53  (e.g., in the form of an extra register) preferably is provided in input cascade chain  52 . Preferably, the number of delays corresponds to the number of adders  47  or, more particularly, output registers  409  for which delays  53  compensate. Generally, this would amount to one delay  53  for each pair of fundamental processing units  30 . As discussed above, although in a preferred embodiment two fundamental processing units  30  make up a half-block, they also could be considered a specialized processing block  10  in their own right. 
     As discussed above, the present invention provides rounding circuitry that may be used in an environment such as specialized processing block  10 . As discussed, the rounding circuitry preferably allows the user to select between round-to-nearest mode and round-to-nearest-even mode. Truncation—i.e., always rounding down—also may be provided as an option. Similarly, always rounding up may be provided as an option. In addition, the rounding circuitry preferably allows the user to select the bit at which rounding will occur. 
     The calculation of round-to-nearest is trivial as it involves simply adding one-half (i.e., adding 1 in the next most significant position after the rounding position) and then truncating the result (i.e., replacing all values after the rounding position with zeroes). The calculation of round-to-nearest-even is more complicated, as it involves determining whether the value of the bits beyond the rounding position is exactly one-half or not. As discussed above, in either case the circuitry needs to be able to accept an additional input at any rounding position which the user is permitted to select. 
     Thus, in embodiment  60  of  FIG. 6 , which may be programmably implemented in specialized processing block  10 , instead of waiting for rounding logic  600  before deciding between addition  61  and addition  62 , addition  61  (without input of the rounding bit) and addition  62  (with input of the rounding bit) are carried out simultaneously and the result of rounding logic  600  is used to control multiplexer  63 , which selects between adders  61 ,  62 . This look-ahead rounding decreases the time needed to perform rounding operations between registers  64  and  65 , and therefore increases the maximum permissible clock speed. 
       FIG. 7  shows how adder  62  may be implemented to accept handle the possibility of either two or three inputs in any of the permissible user-selected rounding positions. In the embodiment of  FIG. 7 , the addition to be performed is of two 44-bit numbers, with the user allowed to select any of 16 positions between the seventh and twenty-second positions to be the rounding position. Thus, the first (least significant) six positions and the last (most significant)  22  positions accept only two inputs, but any one of the seventh through twenty-second positions may accept either two or three inputs. 
     As seen in  FIG. 7 , the six least significant positions accept two 6-bit vectors into 6-bit 2:2 compressor  71 , and the 22 most significant positions accept two 22-bit vectors into 22-bit 2:2 compressor  72 . For the 16 positions where there may be three inputs, 16-bit 3:2 compressor  73  accepts three 16-bit vectors—two vectors represent those 16 bits in the numbers to be added, and one vector represents the rounding bit (only one of those 16 bits is a one while the others are 0). All three compressors output two vectors—sum and carry—which are input to a conventional 44-bit two-input adder  74 . As discussed above, while the 2:2 compressors  71 ,  72  do not perform any actual compression, they convert the data at the 28 two-input positions to a sum-and-carry vector format that lines up with the output of 3:2 compressor  73 . 
     In another aspect of the invention, instead of implementing the addition with two parallel conventional adders as in  FIGS. 6 and 7 , the addition may be implemented using a prefix network, such as the modified Kogge-Stone prefix network  80  shown in  FIG. 8 , followed by an adder  88 . As is well known, a Kogge-Stone prefix network is one of many techniques for performing carry look-ahead operations. This allows calculation of carry values for all bit positions without having to use, for example, a time-consuming ripple-carry adder. 
     Using the modified prefix network in accordance with the present invention, the prefix network and one full adder can replace both adder  61  (including compressors  71 - 73 ) and adder  62 . This is preferably accomplished by providing, in each of those positions of the prefix network that may accept three inputs, a modified three-input compressor that can simultaneously perform 2:2 compression and 3:2 compression. 
     In the representation of  FIG. 8 , each node in the first, or input, level  81  is a compressor. The nodes indicated by solid dots are 2:2 compressors. The nodes corresponding to positions that the user can designate as the rounding position are indicated by hashing and can simultaneously perform 2:2 compression and 3:2 compression. Level  81  corresponds to compressors  71 - 73 . 
       FIG. 9  shows the structure of a known 2:2 compressor  90  including an XOR gate  91  and an AND gate  92 , which takes two inputs  93 ,  94  and produces sum (S) and carry (C) vectors  95 ,  96 .  FIG. 10  shows the structure of a known 3:2 compressor  100  including two XOR gates  91 ,  101 , and three AND gates  92 ,  102 ,  103  that are ORed together by OR gate  104 . XOR gate  101  and OR gate  104  provide the sum (S) and carry (C) vector outputs  105 ,  106 , respectively. 
       FIG. 11  shows a modified 3:2 compressor  110  according to the present invention in which XOR gate  101  and OR gate  104  provide the sum (S′) and carry (C′) vector outputs  105 ,  106  for 3:2 operation as in  FIG. 10 , while XOR gate  91  and AND gate  92  provide the sum (S) and carry (C) vector outputs  107 ,  108  for 2:2 operation as in  FIG. 9 . In accordance with the invention, each node of prefix network level  81  that may accept three inputs is implemented using compressor  110 , allowing prefix network  80  to simultaneously calculate the two-input case as in adder  61  and the three-input case as in adder  62 . 
     In subsequent levels  82 - 87  of prefix network  80 , each node preferably includes Generate (G) and Propagate (P) circuitry. G and P circuitry can be described as follows: Two input bits are used—an “A” bit from a first vector, and a “B” bit from a second vector. A single-bit Generate circuit outputs 1 if a carry is generated—i.e., if A OR B=1. A single-bit Propagate circuit outputs 1 if a carry-in is propagated out—i.e., if A AND B=1. The function of prefix network  80  is to calculate a carry bit for each position along the two input vectors, and it does this by combining single-bit G and P circuitry into multi-bit G and P circuitry. Each node in levels  82 - 87  contains multi-bit G and P circuitry, which is constructed out of the single-bit G and P circuitry as follows: The output of a G node when it is being fed by G and P nodes is G out =G 2 +G 1 P 1 , where G 2  is from the node immediately above, and G 1  is from the node above and to the right. The output of a P node when it is being fed by G and P nodes is P out =P 2 P 1 , where P 2  is from the node immediately above, and P 1  is from the node above and to the right. On each successive level, the G and P nodes are combined with multi-bit G and P circuitry, until each position along the vector contains a G and P result that is a combination of all inputs at the top of the prefix network, for all bit positions to the right of it. At the bottom of the network, carry bits for each position can be calculated from the G and P results. Prefix network  80  of  FIG. 8  (levels  82 - 87 ) is a Kogge-Stone network, but any other network topology can be adapted to this method. 
     In levels  82 - 87 , each node that is hatched has two sets of multi-bit G and P circuits—one from the rounding=0 (i.e., from the 2:2 compressors in the rounding range) and one from the rounding=1 (i.e., from the 3:2 compressors in the rounding range). At the bottom of the prefix network two carry vectors are output—one for round=0 and one for round=1, although to the right of the rounding range there is only one carry vector. One of the two carry vectors is selected by round logic similar to round logic  60 , e.g., using multiplexer  89  before adder  88 . The selected carry vector is added with the A and B vectors. A single bit add is just A XOR B XOR CARRY, and therefore adder  88  may be a simple XOR. Levels  82 - 87  plus the adder  88  correspond to adder  74 . 
     As seen in  FIG. 12 , a sparser prefix network  120  can be provided in place of prefix network  80 . In prefix network  120 , every bit position in the permissible round range is populated, because the user may select any of those positions as the round position and therefore prefix network  120  accommodates the possibility of the round bit being input to any of those positions. However, outside the round range, prefix network  120  is sparsely populated. Thus, in the 44-bit example shown of this embodiment, with a round range from bit  7  through bit  22 , bits  23  through  44  preferably are populated only every fourth bit (except that from bit  42  to bit  44  is only a two-bit skip). Similarly, at the least significant bit end of the network, bits  1  and  5  are populated (with a four-bit skip from bit  1  to bit  5  and a two-bit skip from bit  5  to bit  7 ). Rather than three-input adder  88  as in the fully populated network  80 , a 4-bit adder is required to add 4 bits of A, and 4 bits of B, with a carry-in provided by prefix network  120 . A carry may be generated locally in the 4-input adder which may be a known adder such as a ripple-carry adder, carry look-ahead adder, etc. 
     While a 44-bit addition is used as an example in  FIGS. 6-12 , it is only an example, and the invention applies to addition operations of any size. Similarly, while a 16-bit round range is shown in the examples, the round range could encompass any subset of the total number of bit positions (including all of the bit positions). The number of bits encompassed by 3:2 compressor  73 , or the number of positions in the first level  81 ,  121  of prefix network  80 ,  120  that include modified 3:2 compressor  110 , would be adjusted accordingly. 
     Thus it is seen that improved rounding capabilities for a specialized processing block for a programmable logic device, where user programming requires rounding circuitry to be flexible and where timing constraints should be observed, have been provided. 
     A PLD  130  incorporating such circuitry according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system  900  shown in  FIG. 13 . Data processing system  900  may include one or more of the following components: a processor  901 ; memory  902 ; I/O circuitry  903 ; and peripheral devices  904 . These components are coupled together by a system bus  905  and are populated on a circuit board  906  which is contained in an end-user system  907 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  120  can be used to perform a variety of different logic functions. For example, PLD  120  can be configured as a processor or controller that works in cooperation with processor  901 . PLD  120  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  120  can be configured as an interface between processor  901  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  130  as described above and incorporating this invention. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.