Abstract:
A method for processing a semiconductor wafer in a PECVD deposition chamber with a circular pedestal and a recessed portion formed around the outer top surface of the pedestal. The method may include using a circular wafer carrier ring with a recessed portion.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    Under 35 U.S.C. §120, this continuation application claims priority to and benefits of U.S. patent application Ser. No. 13/153,939 (TI-68426), entitled (“THIN EDGE CARRIER RING”), filed on Jun. 6, 2011, which claims priority to and benefits of U.S. Provisional Application No. 61/351,378, filed on Jun. 4, 2010. The entirety of both applications is incorporated herein by reference. 
     
    
     FIELD 
       [0002]    This disclosure relates to the field of integrated circuit processing. More particularly, this disclosure relates thin film PECVD deposition. 
       BACKGROUND 
       [0003]    During the manufacturing of an integrated circuit a number of dielectric films may be deposited. One technique used to deposit dielectric films at temperatures less than approximately 550 C is PECVD (plasma-enhanced chemical vapor deposition). Some PECVD tools are single wafer tools which a deposit dielectric thin film onto one wafer at a time. One important deposition criteria for the dielectric thin film is thickness uniformity across the wafer including the edges of the wafer. In order to provide uniform thickness out to and including the edges of a wafer the deposition may extend beyond the wafer edge. In PECVD deposition processes using pressures greater than about 12 Torr, a ring of deposited dielectric (also called a deposition fence) may form just outside the edge of the wafer on the pedestal or the wafer carrier ring upon which the wafer is positioned. The deposition fence typically presents a particle problem when the thickness builds up after dielectric deposition upon multiple wafers. The deposition fence may peel due to accumulated film stress or the deposition fence may become sufficiently thick to come into contact with the robot slider which transfers wafers into and out of the chamber. When the robot slider comes into contact with the deposition  fence, pieces of the deposition fence may break off and redeposit on the wafer resulting in depressed yield. 
         [0004]    Several methods have been developed to deal with the deposition fence. One method is to open the chamber and remove the deposition fence after a specified number of wafers have been processed. Another method is to periodically run a plasma clean step such as a NF3 plasma step to etch away the dielectric fence. Both solutions reduce the time that the deposition tool is available for manufacturing thus increasing manufacturing cost. 
       SUMMARY 
       [0005]    The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the disclosure. This summary is not an extensive overview of the disclosure, and is neither intended to identify key or critical elements of the disclosure, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to a more detailed description that is presented later. 
         [0006]    A PECVD deposition chamber with a circular pedestal with a recessed portion in the outer top surface of the pedestal. A PECVD deposition chamber with a circular wafer carrier ring with a recessed portion in the outer top surface of the wafer carrier ring. 
     
    
     
       DESCRIPTION OF THE VIEWS OF THE DRAWING 
         [0007]      FIG. 1  is a cross-section of a PECVD deposition chamber illustrating the deposition plasma. 
           [0008]      FIG. 2 . is a cross-section of a PECVD deposition chamber illustrating a deposition fence. 
           [0009]      FIG. 3  is a cross-section of a PECVD deposition chamber with a wafer carrier ring formed according to embodiments. 
           [0010]      FIGS. 4A and 4B  are a top down view and cross-sectional illustrations of a wafer carrier ring. 
           [0011]      FIGS. 5A and 5B  are a top down view and a cross-sectional illustration of a wafer carrier ring formed according to embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    The present disclosure is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. One skilled in the relevant art, however, will readily recognize that the disclosure can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure. 
         [0013]    Single wafer PECVD dielectric deposition tools come in a variety of designs. A dielectric tool may have a single chamber which processes a single wafer at a time or may have multiple chambers. A dielectric tool may also have a single chamber with multiple deposition stations for processing multiple wafers at a time. Multiple deposition stations may provide a more uniform film thickness by averaging out deposition nonuniformity that may occur in one of the deposition stations. In a multi-station deposition tool the wafer typically is placed on a carrier ring which transports the wafer from station to station. 
         [0014]    The inside of a typical multi-station, single wafer deposition chamber is shown in  FIG. 1 . Wafer  1008  sits atop pedestal  1004 . Carrier ring,  1006 , which is used to transport the wafer from one deposition station to the next, surrounds the wafer  1008  providing an extended surface beyond the edge of the wafer. This extended surface facilitates uniform thin film deposition out to and including the edge of the wafer  1008 . Reactants are dispensed from top electrode and showerhead,  1010 , into the plasma  1012  and recombine at the plasma  1012 /wafer  1008  interface to deposit dielectric on the wafer  1008  and recombine along the plasma edge  1016 /chamber ambient interface to form a dielectric fence  1014  on the wafer carrier ring  1006 . The deposition fence  1014  may increase in thickness as additional wafers are processed. 
         [0015]    As is illustrated in  FIG. 2 , the deposition fence  2014  may build up to a thickness where the robot slider  2018  which transports wafers into and out of the chamber, comes into contact with the deposition fence causing pieces of the deposition fence,  2014 , to be broken off resulting in particles that may redeposit on wafer  2008  and depress yield. 
         [0016]    An embodiment is illustrated in  FIG. 3  which addresses the deposition fence problem. Pedestal  3004  has a central region  3005  surrounded by an outer region  3003 , which is recessed with respect to central region  3005 . Carrier ring  3006  surrounds central region  3005  and sits over outer region  3003  of pedestal  3004 . Carrier ring  3006  includes a central region  3007 , which surrounds and has an upper surface that is substantially coplanar with the upper surface of central region  3005  of pedestal  3004 , a second region  3008 , which surrounds central region  3007  and has an upper surface that is substantially coplanar with the upper surface of wafer  3010  when wafer  3010  is positioned on regions  3005  and  3007 , and a third or outer region  3009 , which surrounds and is recessed with respect to region  3008 . Reactants dispensed from the top electrode and showerhead in a deposition chamber recombine along the interface between the plasma edge and chamber ambient to form dielectric deposition fence  3014  on outer region  3009  of carrier ring  3006 . Outer region  3009  of the carrier ring  3006  where the deposition fence  3014  forms is recessed with respect to region  3008  so that the distance from the top of the deposition fence  3014  to the robot slider  3018  is increased. This increased distance, permits more wafers to be processed between plasma chamber cleans or openings thus increasing the time to process product wafers and reducing manufacturing cost. 
         [0017]    Top down and side views of a typical carrier ring  4000  are shown in  FIGS. 4A and 4B . As shown in  FIG. 4B  the typical carrier ring  4000  has a center recess region  4004  in which the wafer rests, which is surrounded by region  4002 . Region  4002  is of a uniform thickness  4018  out to the edge of the carrier ring. Thickness  4018  of region  4002  exceeds the thickness of center recess region  4004  by the thickness of wafers to be transported by carrier ring  4000 . 
         [0018]    A top down and side view of a carrier ring  5000  according to an embodiment which addresses the deposition fence problem are shown in  FIGS. 5A and 5B . As shown in  FIG. 5B , carrier ring  5000  has a center recess region  5004  in which the wafer rests. Center recess region  5004  is surrounded by region  5002 , which has a thickness that exceeds the thickness of center recess region  5004  by the thickness of wafers to be transported by carrier ring  5000 . Carrier ring  5000  also has an outer portion  5006  where a deposition fence may form. Outer portion  5006  is recessed with respect to region  5002  to provide an increased distance between a deposition fence that forms in this area and a robot slider arm that transports a wafer into and out of the deposition chamber or transports the carrier ring plus the wafer from one deposition station to the next. 
         [0019]    In an example embodiment, the multi-station deposition chamber is a Novellus Vector deposition chamber for the deposition of organo-silicate glass (OSG). As shown in  FIG. 5B  an outer portion of the wafer carrier ring  5006  is recessed. The ring recess  5006  may be in the range of 0.5 to 0.8 inches wide and 0.03 to 0.06 inches deep. In a preferred embodiment the ring recess is about 0.6 +/−0.005 inches wide and about 0.0425 +/+0.005 inches deep. Using the preferred embodiment, the ratio of the number of wafers able to be processed using a wafer carrier ring with the preferred embodiment recess to the number of wafers able to be processed without a recess prior to a chamber clean is approximately 1.6. This 60% increase in the number of wafers processed between chamber cleans may significantly reduce manufacturing cost. 
         [0020]    Although the example embodiment used for illustration is a Novellus Vector, other Novellus PECVD deposition equipment may also benefit. In addition, other multi-station deposition tools and other single wafer, single station deposition tools may benefit. Although the example embodiment used for illustration is an OSG dielectric deposition, other films that are deposited with a pressure greater than about 12 Torr and may form deposition fences may also benefit. 
         [0021]    While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.