Abstract:
A charge pump circuit includes a switch for transmitting an electric charge between a pumping node and an output of the charge pump circuit such that a pre-charge voltage level is applied to a control node during pre-charge operation and a pumping control voltage level is applied to the control node during pumping operation, and a control circuit for changing a level of the control node in response to a control signal to turn off the switch.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of Korean Patent Application No. 2005-55277, filed Jun. 24, 2005 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a charge pump circuit and, more particularly, to a charge pump circuit and a semiconductor memory device having the same in which electric current consumption is reduced during a power down mode.  
         [0004]     2. Description of Related Art  
         [0005]     A typical charge pump circuit repetitively performs pre-charge operations and pumping operations to pump a pumping node and transmit an electric charge of the pumping node to an output of the charge pump via a charge transmission transistor to thereby generate a high voltage.  
         [0006]     A semiconductor memory device includes the high voltage generating circuit to generate a high voltage, which is applied to a word line driver. A word line driver drives a word line with the high voltage.  
         [0007]     The semiconductor memory device operates in a power down mode to reduce consumption of an external power voltage applied from an external portion. However, the high voltage generating circuit of the semiconductor memory device, and more particularly the charge transmission transistor, stays turned on to continuously transmit an electric current from the pumping node to the output of the charge pump even though it does not need to generate the high voltage during the power down mode.  
         [0008]     Thus, the semiconductor memory device having the high voltage generating circuit is not suitable for a portable device that needs low power consumption.  
         [0009]      FIG. 1  is a block diagram illustrating a high voltage generating circuit. The high voltage generating circuit of  FIG. 1  includes a control signal generating circuit  10 , pre-charge circuits  12  and  14 , capacitors C 1  and C 2 , level shifters  16  and  18 , and NMOS transistors N 1  and N 2 .  
         [0010]     The control signal generating circuit  10  generates a pre-charge control signal P 1  having an opposite phase to an active command ACT and generates first and second pumping control signals P 2  and P 3 , which have opposite phase to each other when the active command ACT having a high level is applied. The pre-charge circuits  12  and  14  respectively pump nodes A and B by a pre-charge voltage level, for example, an external power voltage VEXT level, in response to the pre-charge control signal P 1 . The capacitors C 1  and C 2  respectively pump nodes A and B by the external power voltage VEXT level in response to the first and second pumping control signals P 2  and P 3 . The level shifters  16  and  18  respectively control nodes C and D to have the pre-charge voltage level, for example, the external power voltage VEXT level, during the pre-charge operation, and respectively change the levels of the nodes C and D to, for example, a voltage “VEXT+VPP” level in response to first and second pumping control signals P 2  and P 3  during the pumping operation. The NMOS transistors N 1  and N 2  are turned on in response to the levels of the nodes C and D, respectively, to transmit the electric charge of the node A to the node B and the electric charge of the node B to the high voltage VPP generating terminal.  
         [0011]      FIG. 2  is a timing diagram illustrating operation of the high voltage generating circuit of  FIG. 1 . During a pre-charge time period T 1 , when the active command ACT having a low level is applied, the pre-charge control signal P 1  having a high level is generated from the control signal generating circuit  10 . When the pre-charge control signal P 1  having a high level is generated, the pre-charge circuits  12  and  14  pre-charge the nodes A and B to the external power voltage VEXT level, respectively. The level shifters  16  and  18  pre-charge the nodes C and D to the external power voltage VEXT level in response to the pre-charge control signal P 1 .  
         [0012]     During a first pumping time period T 2 , when the active command ACT having a high level is applied, the first pumping control signal P 2  having a high level is generated from the control signal generating circuit  10 . When the first pumping control signal P 2  having a high level is generated, a voltage of the node A is pumped to a voltage 2VEXT level by the capacitor C 1 . The level shifter  16  changes a level of the node C to a voltage “VEXT+VPP” level from the external voltage VEXT level in response to the first pumping control signal P 2 . The NMOS transistor N 1  is turned on in response to the voltage “VEXT+VPP” level. As a result, charge sharing is performed between the nodes A and B, and the nodes A and B have a voltage 1.5VEXT, respectively.  
         [0013]     During a second pumping time period T 3 , the first pumping control signal P 2  having a low level and the second pumping control signal P 3  having a high level are generated from the control signal generating circuit  10 . When the second pumping control signal P 3  having a high level is generated, the node B is pumped to a voltage 2.5VEXT level by the capacitor C 2 . The level shifter  18  changes the node D to a voltage “VEXT+VPP” level from the external power voltage VEXT in response to the second pumping control signal P 3 . The NMOS transistor N 2  is turned on in response to the voltage “VEXT+VPP” level. As a result, charge sharing is performed between the node B and the high voltage VPP generating terminal, so that the high voltage VPP level is pumped.  
         [0014]     The high voltage generating circuit of  FIG. 1  generates the same control signals P 1 , P 2  and P 3  as the pre-charge time period T 1  if a power down command PD is activated. As a result, the node B becomes the external power voltage VEXT level, and the node D also becomes the external power voltage VEXT level. Thus, the NMOS transistor N 2  is not turned off but turned on continuously, whereby the electric current continuously flows to the high voltage VPP generating terminal from the node B.  
         [0015]     Accordingly, it is difficult to reduce the electric current consumed in the high voltage generating circuit even through the power down command PD is generated.  
       SUMMARY OF THE INVENTION  
       [0016]     According to an exemplary embodiment of the present invention a charge pump circuit includes a switch for transmitting an electric charge between a pumping node and an output of the charge pump circuit such that a pre-charge voltage level is applied to a control node during pre-charge operation and a pumping control voltage level is applied to the control node during pumping operation, and a control circuit for changing a level of the control node in response to a control signal to turn off the switch.  
         [0017]     The switch is a first NMOS transistor. The control circuit includes a second NMOS transistor which is turned on in response to the control signal to make the control node become a ground voltage level. The switch is a first PMOS transistor. The control circuit includes a second PMOS transistor which is turned on in response to the control signal to make the control node become a power voltage level.  
         [0018]     According to an exemplary embodiment of the present invention a charge pump circuit includes a first charge transmission transistor for transmitting an electric charge between a pumping node and an output of the charge pump circuit in response to a level of a control node, a pre-charge circuit for pre-charging the pumping node and the control node to a pre-charge voltage level during pre-charge operation, and for pumping the pumping node and changing a level of the control node to a pumping control voltage level during pumping operation, and a control circuit for controlling a level of the control node in response to a control signal to turn off the first charge transmission transistor.  
         [0019]     The first charge transmission transistor is a first NMOS transistor. The control circuit includes a second NMOS transistor which is turned on in response to the control signal to make the control node become a ground voltage level. The first charge transmission transistor is a first PMOS transistor. The control circuit includes a second PMOS transistor which is turned on in response to the control signal to make the control node become a power voltage level. The pre-charge circuit includes a pre-charge circuit for pre-charging the pumping node and at least one additional node to the pre-charge voltage level during the pre-charge operation, a first pumping circuit for pumping the at least one additional node in response to a first pumping control signal during the pumping operation, a second charge transmission transistor for transmitting the electric charge to the pumping node from the at least one additional node during the pumping operation, a first level shifter for applying the pre-charge voltage level to a gate of the second charge transmission transistor during the pre-charge operation and applying a pumping control voltage level to a gate of the second charge transmission transistor during the pumping operation, in response to the first pumping control signal, a second pumping circuit for pumping the pumping node in response to a second pumping control signal during the pumping operation, and a second level shifter for applying the pre-charge voltage level to a gate of the first charge transmission transistor during the pre-charge operation and applying the pumping control voltage level to a gate of the first charge transmission transistor during the pumping operation, in response to the second pumping control signal.  
         [0020]     According to an exemplary embodiment of the present invention a semiconductor memory device includes a command decoder for generating an active command and a power down command in response to a command signal applied from an external portion, and a charge pump circuit including a switch for transmitting an electric charge between a pumping node and an output of the charge pump circuit such that a pre-charge voltage level is applied to a control node during pre-charge operation and a pumping control voltage level is applied to the control node during pumping operation, and a control circuit for changing a level of the control node in response to a control signal to turn off the switch.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]     The present invention will become more apparent to those of ordinary skill in the art by describing in detail, preferred embodiments thereof with reference to the attached drawings in which:  
         [0022]      FIG. 1  is a block diagram illustrating a charge pump circuit;  
         [0023]      FIG. 2  is a timing diagram illustrating operation of the charge pump circuit of  FIG. 1 ;  
         [0024]      FIG. 3  is a block diagram illustrating a charge pump circuit according to an exemplary embodiment of the present invention;  
         [0025]      FIG. 4  is a timing diagram illustrating operation of the charge pump circuit of  FIG. 3 ; and  
         [0026]      FIG. 5  is a block diagram illustrating a semiconductor memory device having the charge pump circuit according to an exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0027]      FIG. 3  is a block diagram illustrating a charge pump circuit according to an exemplary embodiment of the present invention. The charge pump circuit of  FIG. 3  includes an NMOS transistor N 3  in addition to a configuration of the charge pump circuit of  FIG. 1 .  
         [0028]     Like reference numerals of  FIGS. 1 and 3  denote like parts and perform like functions, and thus functions of like parts will not be described.  
         [0029]     The NMOS transistor N 3  is turned on to control the node D to have a ground voltage level when the power down command PD having a high level is generated. As a result, the NMOS transistor N 2  is turned off, so that the electric current does not flow to the high voltage VPP generating terminal from the node B.  
         [0030]      FIG. 4  is a timing diagram illustrating operation of the charge pump circuit of  FIG. 3 .  
         [0031]     Operation of a charge pump circuit according to an embodiment of the present invention in the pre-charge time period T 1 , the first pumping time period T 2  and the second pumping time period T 2  is similar to those of  FIG. 2 .  
         [0032]     When the power down command PD is generated during the pre-charge time period T 1  after the second pumping time period T 3 , the control signals P 1 , P 2  and P 3  are generated substantially identically to the pre-charge time period T 1 . The nodes A, B and C become the external power voltage VEXT level identically to the pre-charge time period T 1 . The NMOS transistor T 3  is turned on in response to the power down signal PD having a high level to control the node D to have the ground voltage VSS level. Thus, the NMOS transistor N 3  is turned off, so that the electric current does not flow to the high voltage VPP generating terminal from the node B.  
         [0033]     According to an embodiment of the present invention, the charge pump circuit of the present invention can substantially prevent the electric current from flowing through the NMOS transistor N 3  when the NMOS transistor N 3  is turned off in response to the power down command PD. Thus, the high voltage VPP generating terminal is not supplied with the electric current and so drops to the ground voltage VSS level.  
         [0034]      FIG. 5  is a block diagram illustrating a semiconductor memory device having the charge pump circuit according to an embodiment of the present invention. The semiconductor memory device of  FIG. 5  includes a command decoder  100 , a charge pump circuit  110 , and a memory cell array. The command decoder  100  decodes a command signal COM applied from an external portion to generate an active command ACT and a power down command PD. The charge pump circuit  100  performs the pumping operation in response to the active command ACT to generate the high voltage VPR The charge pump circuit  100  removes the electric current which flows to a high voltage VPP generating terminal (e.g., an output of the charge pump circuit) in response to the power down command PD, removing the electric current which flows to the high voltage VPP generating terminal from the node B. The memory cell array  120  receives the high voltage VPP to drive the word line (not shown) by the word line driver (not shown).  
         [0035]     In  FIG. 5 , a command signal corresponding the power down command PD is inputted to the command decoder  100  and the power down command PD is generated by the command decoder  100 . The power down command PD can be applied directly to the charge pump circuit  110  from an external portion.  
         [0036]     The charge pump circuit of the semiconductor memory device according to an embodiment of the present invention removes the electric current which flows through the NMOS transistor N 2  of  FIG. 3 , e.g., the charge transmission transistor, in response to the power down command PD, whereby consumption of the external power voltage VEXT does not occur.  
         [0037]     In embodiments described herein, the charge pump circuit is described as performing a two-step pumping operation. The charge pump circuit may perform a pumping operation having a different number of steps, e.g., a three- or four-step pumping operation.  
         [0038]     In a device including the pumping node and the charge transmission transistor, the pumping node and a gate of the charge transmission transistor are pre-charged to the pre-charge voltage so that the charge transmission transistor is turned on during the power down mode.  
         [0039]     In embodiments described herein, a gate of the NMOS transistor becomes the ground voltage VSS level when the power down command PD is activated in case where the charge transmission transistor is comprised of the NMOS transistor. A gate of the PMOS transistor may become the external power voltage VEXT level when the power down command PD is activated in a case where the charge transmission transistor is comprised of the PMOS transistor.  
         [0040]     In embodiments described herein, the external power voltage VEXT level is used as the pre-charge voltage level. A voltage obtained by subtracting a threshold voltage of the NMOS transistor from the external power voltage VEXT can be used as the pre-charge voltage level.  
         [0041]     In embodiments described herein, the external power voltage VEXT is used as a power voltage. An internal power voltage generated by using the external power voltage VEXT can be used as a power voltage.  
         [0042]     The high voltage generating circuit according to an embodiment of the present invention can reduce power consumption by removing the electric current which flows to the output of the charge pump circuit from the pumping node.  
         [0043]     The semiconductor memory device having the high voltage generating circuit according to an embodiment of the present invention can reduce consumption of the electric current consumed in the charge pump circuit during the power down mode.  
         [0044]     Thus, if the semiconductor memory device according to an embodiment of the present invention is implemented, consumption of the external power can be reduced.