Abstract:
A high power AM-band transmitter amplifier comprises four switches in an H-Bridge configuration and operates by adjusting the duty cycle of the voltage waveform on a transformer. The duty cycle is adjusted by changing the phase relationship between the diagonal switch pairs. An embodiment of the amplifier operates efficiently by the addition of a current source that may comprise inductor and capacitor circuits to assure zero voltage switching of all the switches. The inventive H-Bridge configuration can also be utilized in a phase modulated power supply.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates generally to an H-Bridge switching circuit that can be used in a power amplifier for a radio transmitter or a switching power supply. 
   It has been well known in the switching power supply industry that high efficiency systems can be designed by chopping a voltage to produce another voltage. Pulse width regulated power supplies operate at efficiencies in excess of 97%. However, the higher switching frequencies needed to operate in the AM band tend to increase switching losses. Also, it becomes difficult to turn FETs, which are commonly used in switching power supplies, on and off quickly enough when the duty cycle is small. 
   It has always been a goal to produce AM transmitters that will be more efficient. AM transmitters using two stages to do the modulation and the amplification of the audio signal are known and are suitable for handling transmitters up to a power of 10 kW. However, it is difficult to reach necessary efficiencies (e.g., 86%) using a separate modulator and amplifier for higher power level (e.g., 25 kW, 50 kW and 100 kW) transmitters. An amplification-modulation scheme that is much more efficient is required for the higher power levels. 
   One way to improve efficiency is to remove sections of the transmitter or to group different parts of the transmitter. In general, an AM transmitter comprises a power supply, modulator, power amplifier, combiner, and output network. Each of these parts has an associated energy loss that adds up to form the total system loss. 
   It is known to combine the modulation and the amplification into one stage to improve efficiency. To perform the modulation of the transmitters, known systems turn the amplifiers off and on. These amplifiers are added through RF combiner transformers on the output of each RF stage. This means that many amplifiers are needed to reduce the change in amplitude when one module is turned off or on. These systems prove impractical below the 10 kW power level because of the large number of amplifiers needed to apply this scheme. 
   A design known from U.S. Pat. No. 4,580,111 can operate fairly efficiently, however, one difficulty with this type of design is that it is only practical for high power (e.g., 10 kW and above—at, e.g., 9 kW watts and below, particularly at 5 kW and below, this circuit becomes increasingly impractical). To build this type of design, enough modules are needed so the step size in turning a module off and on will be small. 
   SUMMARY OF THE INVENTION 
   The present invention provides a scheme for reducing the duty cycle to zero when necessary and, in an embodiment of the invention, addresses the increasing switching losses that occur at high frequencies. The present invention works equally well at high power as well as low power (below 10 kW). 
   An amplifier using the inventive H-Bridge circuit performs the amplification by reducing the duty cycle of the signal from each amplifier going to the RF combining transformers. Instead of turning the amplifiers off and on, as is known in the art, the proposed design increases and decreases the power of all amplifiers. This allows each amplifier to operate on its own. Amplification can be made with one amplifier as well as with many amplifiers combined. Thus, the inventive amplifier remains practical to implement below 10 kW. A practical single amplifier can operate as low as 500 watts or even less. 
   Two inventive features address the goal of reducing the duty cycle and the switching losses associated with high frequency switching. An embodiment of the invention utilizing the first feature involves adjusting the duty cycle at an RF frequency by changing the phase relationship between diagonal switch pairs (e.g., FETs Q 1  and Q 3 ) rather than reducing the duty cycle on any one switch. This allows the duty cycle on any one switch to remain at 50% while changing the duty cycle on the combiner transformer to as large or small as necessary. When the switching frequencies get higher, it becomes difficult to turn the switching devices on and off quickly enough when the duty cycle is small. A small duty cycle drive signal either turns the switch on for a longer than desired period of time or does not turn the switch on at all. The present invention provides a solution to this problem by keeping the duty cycle on each switch at 50%. To reduce the amplitude of the output RF waveform, the duty cycle on the transformer is reduced, and not the duty cycle on the switch. 
   An embodiment of the invention involves the second feature of making the amplifier itself efficient. As mentioned earlier, high efficiency systems can be achieved by chopping a voltage to produce another voltage. This is used extensively in the power supply industry. However, maximizing the efficiency in the application of high-power RF transmitters calls for switching frequencies that are on the order of 10 times higher. When the frequency is raised, the switching losses go up and the efficiency goes down. To improve the efficiency of this system, it is necessary to turn each switch (e.g., FET) on when the voltage across it is zero. Zero voltage switching is achieved by providing current into the amplifier using circuits consisting of inductors and capacitors. 
   According to an embodiment of the invention, a power amplifier (PA) operates generally, but not exclusively, in the AM frequency range (540 kHz–1710 kHz). The PA performs both the amplification function and the modulation in the same design. The PA comprises switches that are four field effect transistors (FETs) connected in an H-Bridge configuration with a transformer at the horizontal part of the “H”. The FETs are operated out of the normal phasing to provide a duty cycle modulated waveform across the transformer. This signal is then filtered to provide the standard AM modulation. To produce a high efficiency PA, two coils are provided to assure zero voltage from drain to source of each FET when they are turned on, regardless of the modulation level. 
   According to another embodiment of the invention, a switching power supply, the filter and load normally in the amplifier may be replaced with a rectifier circuit, filter, and load. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is explained in more detail below, with reference to the drawing figures illustrating exemplary embodiments of the invention. 
       FIG. 1A  is a circuit schematic of an embodiment of the inventive power amplifier H-Bridge circuit; 
       FIG. 1B  is a circuit block schematic showing the replacement of a filter and load with a rectifier circuit, filter, and load for operation as a switching power supply; 
       FIG. 2  is a timing chart illustrating the phase relationship between the drive of switches Q 1  and Q 2 ; 
       FIG. 3  is a timing chart illustrating the voltage on transformer T 1  for a known H-bridge design; 
       FIG. 4  is a timing chart illustrating a specific drive phase relationship between switches Q 1  and Q 3 ; 
       FIG. 5  is a timing chart illustrating the specific voltage across transformer T 1  using this design; 
       FIG. 6  is a graph illustrating the peak filtered output voltage vs. overlap phase; 
       FIGS. 7A–D  are timing charts illustrating the relationships between various circuit signals in relation to the phases the drives of switches Q 1 –Q 4 ; 
       FIG. 8  is a block diagram of an RF system in which the inventive circuit operates; 
       FIG. 9  is a block diagram of the exciter circuit used to drive the H-Bridge circuit; 
       FIG. 10  is a timing chart illustrating the transformer voltage and load current when the drives of Q 1  and Q 3  do not overlap; 
       FIG. 11  is a timing chart illustrating the transformer voltage and load current when the drives of Q 1  and Q 3  overlap completely; and 
       FIG. 12  is a circuit schematic according to an additional embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Various embodiments of the invention are described in the following text.  FIGS. 1A ,  1 B illustrate a schematic diagram of an embodiment of the inventive power amplifier H-Bridge circuit  10 .  FIG. 1A  shows the circuit used to feed a filter and load F, L for power amplification, and  FIG. 1B  shows the replacement of the filter and load F, L with a rectifier, filter, and load R, F, L for use as a power supply. 
     FIGS. 8 and 9  illustrate an exemplary context in which the H-Bridge circuit  10  may be used for an AM-band PA, and thus provide an overview of an applied variation of an inventive embodiment. 
   As illustrated in  FIG. 8 , an RF system  100  comprises an audio source  102 , an RF signal generator  104 , and a Global Positioning System (GPS)  106 . A power amplifier power supply  110  and low voltage power supply  118  are used to supply power to the various components of the RF system  100  (numbers in parentheses in  FIG. 8  indicate the number of individual components that may be used in an exemplary system). An exciter  108  that accepts signals from the generators  102 ,  104 ,  106 , provides drive signals to the power amplifier  90 , and the power amplifier  90  sends its signals to a combiner  112  whose output is connected to an output network  114  used to interface to an antenna  116  that is used to transmit the RF signals. A controller  120  is present to provide control signals to the power supply  110  and the output network  114  and also to receive status from the various system components. 
   As shown in  FIG. 9 , the H-Bridge circuit  10  is driven by the exciter  108  having two inputs to the power amplifier  90 . The power amplifier  90  splits the two inputs into four with the use of two inverters  92 ,  92 ′. An audio signal is sent by the audio source (e.g., audio processor or signal generator)  102  to the exciter  108  that produces a proper overlap for a particular audio level. The exciter  108  sends out two signals phased to yield the desired RF amplitude in the filtered output which is proportional to the audio input signal. The two signals from the exciter  108  are sent to the power amplifier  90  where each signal is split. One part of the signal is sent directly to a circuit that adds dead time  94  while the other part of the signal is inverted first, via the inverters  92 ,  92 ′ before being sent to the dead time circuitry  94 . This produces the drive RF Drive Q 1 –Q 4  for the four FETs Q 1 –Q 4 . 
   In the embodiment of the inventive H-Bridge circuit  10  shown in  FIG. 1 , FETs Q 1  and Q 2  are switched out of phase with, e.g., about 35 nS of dead time (i.e., the time that both Q 1  and Q 2  are off) between them, as illustrated in the timing diagram of  FIG. 2  (the drives being illustrated, as described above, by  FIG. 9 ). The dead times specified are somewhat arbitrary, but 35 nS has worked well in experiments conducted by the inventor for the embodiments described herein. The longer the dead time, the lower the current needs to be in the inductors L 1  and L 2  described below because they have a longer time to change the voltage state of junction points of the switches. 
   Thus, as illustrated in  FIG. 7A , which illustrates a more detailed timing relationship of the signals, FET Q 2  is switched off at time t 3 , and then 35 nS later (for example), at a later time t 4 , FET Q 1  is switched on. FET Q 1  remains on until time t 7  when it is switched off, and 35 nS later (for example), FET Q 2  is switched on at a later time t 8 . FETs Q 3  and Q 4  operate exactly like FETs Q 1  and Q 2 , where FETs Q 3  and Q 4  are also out of phase with a set dead time. 
   The switches (FETs Q 1 –Q 4 ) that are used in this embodiment may be, e.g., those from Advanced Power Technology, PN APT5010JFLL; these FETs have a fairly fast recovery diode. This particular part is specified for an application calling for a B+ voltage of 400 volts since it can operate to 500 volts, however, design could be used at other voltages with other devices. 
   With the positive voltage as marked on  FIG. 1A , when both FETs Q 1  and Q 3  are turned on by a respective first and third drive signals V G1 , V G3 , ( FIG. 7A , between t 6  and t 7 ) a B+ voltage V T1  is place across the transformer T 1 . The duty cycle where both FETs Q 1  and Q 3  are turned on depends on the phase relationship between the drive signals V G1 , and V G3 . When both Q 2  and Q 4  are turned on by a respective second and fourth drive signals V G2 , V G4 , the opposite (−B+) voltage V T1  is placed across the transformer. This is different than a known H-Bridge design, where FETs Q 1  and Q 3  would be turned on at the same time (i.e., always in phase), and then subsequently turned off. The known H-Bridge design would always produce a 50% duty cycle square wave across the transformer, as illustrated in  FIG. 3 . 
   As shown in the drawings, reference character B stands for bulk supply and is produced by the power amplifier power supply  110 . B+ represents the positive voltage and B− the negative (a relative ground). In a typical application, B+ may be, e.g., 400 volts above B−. B− is shown in  FIG. 1  with a ground symbol having a “B” in it. The source of FETs Q 2  and Q 3  are connected to B− as well as the grounded side of C 2  and C 3 . 
   According to the H-Bridge  10  design, FETs Q 1  and Q 3  are not turned on at the same time but are shifted in phase. FET Q 1  is turned on first (t 4 ) then FET Q 3  is turned on some time later (t 6 ). Similarly, FET Q 2  is turned on first (t 8 ) and then FET Q 4  is turned on some time later (one cycle after t 2 , as shown in the figure).  FIG. 4  shows a specific phase relationship of the drive on FETs Q 1  and Q 3 . FETs Q 2  and Q 4  have a corresponding phase relationship. The voltage B+ will only appear across transformer T 1  (V T1 ) when both FETs Q 1  and Q 3  are turned on. The voltage −B+ would only appear across T 1  (V T1 ) when FETs Q 2  and Q 4  are both on.  FIG. 5  shows the voltage V T1  across transformer T 1  with a specific phase relationship between FETs Q 1  and Q 3 .  FIG. 5  also shows where there is overlap between the drive signals of FETs Q 1  and Q 3  as well as the overlap between the drive signals of FETs Q 2  and Q 4 .  FIG. 7A  illustrates the phase relationships between the drives of FETs Q 1 –Q 4 . 
   The overlap time when both FETs Q 1  and Q 3  are turned on (t 6  to t 7 ) determines the amplitude of the filtered output signal (this similarly applies for FETs Q 2  and Q 4 ). If FETs Q 1  and Q 3  happen to be out of phase, then the resulting voltage across the transformer V T1  will be zero (e.g., as illustrated in  FIG. 10 ). This produces a filtered output of zero. If FETs Q 1  and Q 3  have some time where they are simultaneously turned on, the filtered output will be greater than zero. By changing the time of the drive signal overlap with the adjustment circuitry  92 ,  92 ′,  94 ,  96 ,  108 , i.e., the phase difference between the drives of FETs Q 1  and Q 3 , the filtered output can also be changed. Therefore, by adjusting the overlap of the on state of FETs Q 1  and Q 3 , the output RF voltage can go from zero to, theoretically, 1.27 times the B+ voltage, as the amplitude of the filtered output sine wave can be determined by calculating the first coefficient of the Fourier series for the transformer voltage V T1 . For the maximum RF filtered output, the transformer voltage is a square wave with the first Fourier coefficient of 4(B+)/π=1.27(B+). A graph of the overlap in degrees vs. filtered output voltage in percent of B+ voltage is shown in  FIG. 6 . The theoretical amplitude is represented by the equation 4(B+)/π·sin(θ overlap /2). 
   Another important aspect of the design is to have the power amplifier operate efficiently. To improve the efficiency of this system, it is necessary to turn each switch (e.g., FET) on when the voltage V DSQ1,2,3,4  across it is zero. This minimizes the power losses associated with switching the FETs on. Zero voltage switching is achieved by providing current I L1  into the junction point of FETs Q 1  and Q 2  (the source of FET Q 1  and drain of FET Q 2 ) during the dead time. The same would also be true for FETs Q 3  and Q 4  (a current I L2  into the junction point). The current into the junction point of FETs Q 1  and Q 2  is the current I L1  supplied by an inductor L 1 , minus the current used by the load I LOAD . The current into the junction point of FETs Q 3  and Q 4  is the current I L2  supplied by an inductor L 2 , plus the current used by the load I LOAD . 
   As mentioned above, one source of current is the load L itself (I LOAD ). The load current I LOAD  coming from the junction point of FETs Q 1  and Q 2  is more than sufficient to assure a zero voltage across FETs Q 1  and Q 2  when they are turned on, except for two cases. When the drives to FETs Q 1  and Q 3  are in phase (this would correspond to the maximum positive audio modulation) and when the drives to FETs Q 1  and Q 3  are out of phase (this would correspond to the maximum negative audio modulation), there is not enough load current I LOAD  to assure zero voltage switching of FETs Q 1  and Q 2 . 
   Under these conditions, the load current I LOAD , when FETs Q 1  or Q 2  are turned off, is theoretically zero. This can be seen in  FIGS. 10 and 11 . This means that no current is available to change the voltage state at the junction point of FETs Q 1  and Q 2  to assure their zero voltage switching. There is a time when the drive going to Q 1  and Q 3  are either in phase (as shown in  FIG. 11 ) or out of phase (as shown in  FIG. 10 ). The phase reference will be determined by the audio  102  supplied to the exciter  108 . The exciter  108  produces the drive wave forms for FETs Q 1  and Q 3 . The phase relationship between FETs Q 1  and Q 3  are constantly changing as the audio signal  102  going to the exciter  108  is varied. When the audio voltage is at a minimum during a negative modulation peak of audio, the exciter  108  will send out two signals that will produce drive signals to FETs Q 1  and Q 3  that are out of phase as in  FIG. 10 . This will produce no voltage across the transformer and no filtered output voltage. When the audio voltage is at its maximum peak, the exciter  108  will send drive signals that are in phase as shown in  FIG. 11 . This will produce a filtered output RF peak voltage of 1.27 times the B+ voltage. 
   Significantly, inductor L 1  is thus utilized to provide enough current I L1  going into the junction point of FETs Q 1  and Q 2  to assure zero voltage switching at all phase relationships between drive of FETs Q 1  and Q 3 , especially when the drive to FETs Q 1  and Q 3  are in phase or out of phase. The other side of inductor L 1  is connected to a capacitor network of, e.g., two equal valued capacitors C 1  and C 2  that provide a B+/2 voltage source at their junction point. For example, if B+ is 400 volts, and B− is 0 volts (a relative reference voltage), then the junction point of C 1  and C 2  would be B+/2 or 200 volts. These capacitors can sink and source the current I L1  going through L 1 . The reactance of capacitors C 1  and C 2  is small at the frequency of operation. By connecting one capacitor C 1  to B+ and one capacitor C 2  to B−, the junction point of the two capacitors more quickly converges to B+/2 volts when the RF drive is first turned on. 
   To provide zero voltage switching for FETs Q 3  and Q 4 , a much smaller inductor than inductor L 1  is needed. Inductor L 2  is provided for this purpose. The reason for this is explained by way of example in a typical application and with reference to the timing diagrams in the  FIGS. 7A–D . When FET Q 2  is turned off, the load current I LOAD  is about −18 amps. This means that +18 amps would be going into the junction point of FETs Q 1  and Q 2 . A current going into the junction point of FETs Q 1  and Q 2  will raise the voltage on FET Q 2  V DSQ2  to B+ when FET Q 2  is turned off. When FET Q 1  is turned on, the voltage across it V DSQ1  will be zero. The same would be true when considering the time when FET Q 1  is turned off. 
   However, this is not the case when FET Q 3  or FET Q 4  is turned off. In view of the timing charts, the load current I LOAD  when FET Q 3  is turned off is about −16 amps. This would be pulling +16 amps out of the junction point of FET Q 3  and FET Q 4 . But to change voltage states of the junction point of FETs Q 3  and Q 4 , the current must be going into the junction. For a zero voltage turn on of FET Q 4 , enough current must be provided to compensate for the load current I LOAD  and to provide additional current for changing voltage states of the junction of FETs Q 3  and Q 4 . 
   For this reason, inductor L 2  must provide significantly more current than inductor L 1 . Considering the timing chart, when FET Q 3  is turned off, the current I L2  in L 2  is about 35 amps. This is enough current to compensate for the 16 amps being pulled out of the junction point of FETs Q 3  and Q 4  by the load current I LOAD , with 19 amps remaining going into the junction point of FETs Q 3  and Q 4  to raise the voltage at that junction to B+ when FET Q 3  is turned off. When FET Q 4  is turned on, the voltage across it VDSQ 4  will be zero. Therefore, it can be seen that the load current I LOAD  at all phase relationships between FETs Q 1  and Q 3  is in the opposite direction than is needed for zero voltage switching of FETs Q 3  and Q 4 . Thus, to assure zero voltage switching of FETs Q 3  and Q 4 , enough current has to be injected in their junction point (the drain of Q 3  and source of Q 4 ) to overcome the load current I LOAD  plus enough to assure zero voltage switching. This current IL 2  is provided by inductor L 2 . The other side of inductor L 2  is connected to two equal capacitors C 3  and C 4  which will provide a B+/2 voltage source in the same way as described above for capacitors C 1  and C 2 . Since capacitors C 3  and C 4  are sinking and sourcing more current than capacitors C 1  and C 2 , their capacitance will be larger. 
   There are no special requirements for the inductors L 1  and L 2  used to provide the necessary current. For example, an air core inductor wound on a plastic form with litz wire may be used. The litz wire will help to reduce losses in these parts. However, the proper values of the inductors are important. In an exemplary application, inductor L 2  should have, e.g., a reactance of 9 Ω at the frequency of operation. Inductor L 1  is less critical and should have, e.g., a reactance of 1000 at the operating frequency. The value of inductor L 2  is more critical since it must provide current I L2  to compensate for the load current I LOAD  and to provide current necessary for zero voltage switching. If inductor L 2  has too large of an inductance, there will not be enough current to assure zero voltage switching of FETs Q 3  and Q 4 . The value of inductor L 1  is less critical, since it only needs to provide current at the extremes of modulation (maximum negative and positive modulation). 
   The capacitors C 1 –C 4  may be any low loss capacitor, e.g., polypropylene. Multiple capacitors, e.g., three to four, may be connected in parallel for the capacitor network C 3 , C 4  to give a value of 1.5–2.0 μF. For capacitor network C 1 , C 2 , one or two or more capacitors may be connected in parallel to give a value of 0.5–1.0 μF. The actual values of the capacitors are not critical, as long as they are sufficient to handle the respective currents from inductor L 1  and inductor L 2 , and have a small reactance at the operating frequency. 
   As noted previously, the values stated above are illustrative of an exemplary embodiment. For example, these values are useful with respect to operation within the AM Broadcast Band (0.5 to 1.71 MHz), but suitable values could be used at any desired frequency of operation. Additionally, a voltage of 400 volts was described for the B+ voltage, but a design could utilize a much lower (or a much higher) voltage. The load resistance for the above parameters was based on a 10 Ω value. This also can be changed based on a particular application. 
     FIG. 12  illustrates an alternative embodiment of the invention similar to that illustrated by  FIG. 1A , but with the original coil L 1  and capacitors C 1 , C 2  removed. If the modulation does not go to extremes, then switches Q 1  and Q 2  operate adequately without the coil L 1  and the capacitors C 1  and C 2 . Even if the modulation does go to extremes, the coil L 1  and the capacitors C 1  and C 2  are not necessary, although the circuit will operate less efficiently. 
   For a limited modulation, L 1  may be replaced by a coil L 1  in series with a capacitor C 5  (see block  120 ) as illustrated in  FIG. 12 . This improves the efficiency of the design over a small operating area. In the exemplary embodiment shown, coil L 1  may be 5.5 uH, coil L 2  may be a 0.9 μH coil, capacitors C 3  and C 4  may be 0.47 μF capacitors, and C 5  may be a 0.0012 μF capacitor. These values can easily be adapted to various operating ranges of the circuit. 
   Additionally, if a different load impedance is utilized (exemplary values described above relate to a 10 Ω load with no reactance), various values of the components, particularly coils L 1  and L 2  would be utilized. 
   The H-Bridge circuit according to an embodiment of the invention has been described in terms of an RF amplifier, but nothing precludes the applicability of such a circuit to phase modulated power supplies. This circuit could be used to operate power supplies at a much higher frequency and still maintain high efficiency, although such an application would require that the load be replaced with a rectifier arrangement R, F, L, e.g., a bridge rectifier. 
   For the purposes of promoting an understanding of the principles of the invention, reference has been made to the preferred embodiments illustrated in the drawings, and specific language has been used to describe these embodiments. However, no limitation of the scope of the invention is intended by this specific language, and the invention should be construed to encompass all embodiments that would normally occur to one of ordinary skill in the art. 
   The particular implementations shown and described herein are illustrative examples of the invention and are not intended to otherwise limit the scope of the invention in any way. For the sake of brevity, conventional electronics, control systems, and other functional aspects of the systems (and components of the individual operating components of the systems) may not be described in detail. Furthermore, the connecting lines, or connectors shown in the various figures presented are intended to represent exemplary functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device. Moreover, no item or component is essential to the practice of the invention unless the element is specifically described as “essential” or “critical”. Numerous modifications and adaptations will be readily apparent to those skilled in this art without departing from the spirit and scope of the present invention.