Abstract:
A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes a set of correction coefficients for each packet from the I and Q signals in an IQ measurement section at the front of the packet. The IQ balancer uses the correction coefficients for correcting the I/Q gain and I/Q phase errors on a packet-by-packet basis. Optionally, delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section.

Description:
This application is a continuation in part of Ser. No. 10,350,622, filed on Jan. 24, 2003. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates generally to signal receivers having in-phase (I) and quadrature phase (Q) signal processing and more particularly to methods and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. 
   2. Description of the Prior Art 
   Most modern radio signal receivers estimate the data that was transmitted by processing in-phase (I) and quadrature phase (Q) signal components. The I and Q signals should have a phase difference (I/Q phase) of 90° at the carrier frequency of the incoming signal and a gain ratio (I/Q gain) of unity. However imperfections in the analog circuitry used in the radio frequency (RF) quadrature downconverters in most modern signal receivers cause the I/Q gain and I/Q phase to be out of balance (I/Q gain not equal to one and I/Q phase not equal to 90°). These imbalances cause a degradation in bit error rate (BER) in estimating the transmitted data. 
   Existing signal receivers use several methods for correcting I/Q gain and I/Q phase imbalances within the receivers. In one method, an offline test signal is used during manufacture or installation to align the I/Q gain to unity and the I/Q phase to 90° in the signal receiver. However, the performance of the receivers using the test signal method is limited by drift in the analog circuitry after the alignment. This limitation is reduced by performing the alignment periodically during operation. However, the periodic alignment adds overhead that reduces the efficiency of a signal communication channel. 
   A second method uses an adaptive algorithm that processes the I and Q signals for converging to adjustments to the I and Q signals while the receiver is on-line. However, the BER performance of the receivers using the adaptive algorithm method is degraded because the receiver is estimating the transmitted data during the same on-line time period that the adaptive algorithm is converging. Of course, the adaptive algorithm could be performed on a test signal but this would add overhead and reduce signal efficiency. 
   Existing receivers using the test signal method or the adaptive algorithm method sometimes use correction coefficients for balancing I/Q gain and I/Q phase of the I and Q signals. However, such receivers that are known determine the I/Q gain and the I/Q phase corrections at points in the signal path that are separated from the RF quadrature downconverter by subsequent downconversion and/or demodulation of the I and Q signals. The performance of such receivers is limited because the imbalances are converted to image signals by the downconversion and/or demodulation and the degradation effect of such image signals cannot be completely eliminated once they are formed. 
   There is a need for a method for correcting I/Q gain and I/Q phase imbalance in a signal receiver without adding overhead to the signal communication channel and without degrading BER while converging on correction coefficients. 
   SUMMARY OF THE INVENTION 
   It is therefore an object of the present invention to provide a method and apparatus in a signal receiver for balancing I/Q gain and I/Q phase by computing packet-fixed correction coefficients for I and Q signals of an on-line operational incoming signal. 
   Briefly, in a preferred embodiment, the signal receiver of the present invention includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes correction coefficients for each incoming packet from the I and Q signals in an IQ measurement section at the front of the packet. Delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section. 
   Advantages of the present invention for balancing I/Q gain and I/Q phase are that no test signal is required, no communication overhead is added, and the correction coefficients are determined without degrading BER during the determination time period. 
   These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various figures. 

   
     IN THE DRAWINGS 
       FIG. 1  is a block diagram of a signal receiver of the present invention; 
       FIGS. 2A and 2B  are first and second embodiments, respectively, of IQ balancers of the receiver of  FIG. 1 ; 
       FIGS. 2C and 2D  are variations of the IQ balancers of  FIGS. 2A and 2B , respectively; and 
       FIG. 3  is a time chart of a packet received by the receiver of FIG.  1 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  is a block diagram of a signal receiver  10  of the present invention. The receiver  10  includes an antenna  12 , a low noise amplifier (LNA)  14 , a quadrature downconverter  16  including a local oscillator system (LO)  18 , and in-phase (I) and quadrature (Q) phase digital-to-analog converters (A/D)s  20 I and  20 Q. The antenna  12  converts a wireless radio frequency (RF) signal into a conducted form and passes the conducted RF signal to the LNA  14 . The LNA  14  amplifies the conducted signal and passes an amplified RF signal to the quadrature downconverter  16 . The quadrature downconverter  16  splits the amplified RF signal into in-phase (I) and quadrature phase (Q) signals that are processed in analog I and Q channels, respectively. The analog I channel includes an I mixer  22 I, an I lowpass filter  24 I, the analog portion of the A/D  20 I, and associated hardware such as amplifiers, matching elements and additional filters. Similarly, the analog Q channel includes a Q mixer  22 Q, a Q lowpass filter  24 Q, the analog portion of the A/D  20 Q, and associated hardware such as amplifiers, matching elements and additional filters. 
   The LO  18  generates an in-phase (I) LO signal, denoted as cos w c t, and a quadrature phase (Q) LO signal, denoted as sin w c t, and passes the I and Q LO signals to the I and Q mixers  22 I and  22 Q, respectively. The I and Q mixers  22 I and  22 Q use the I and Q LO signals to frequency downconvert the amplified RF signal from the LNA  14 . The I and Q filters  24 I and  24 Q filter the I and Q downconverted signals to provide intermediate I and Q signals to the I and Q A/Ds  20 I and  20 Q, respectively. The carrier frequency of the intermediate I and Q signals may be baseband (zero frequency), near to but not exactly zero frequency, or some other frequency that is intermediate between the RF frequency and zero frequency depending upon other system considerations. 
   The quadrature downconverter  16  has an I/Q gain imbalance (error)  32  represented by ΔA and an I/Q phase imbalance (error)  34  represented by Δφ. It should be noted that the I/Q gain error ΔA  32  and the I/Q phase error Δφ  34  are not actual blocks in the block diagram of the quadrature downconverter  16 , but are instead representations of imperfections in the quadrature downconverter  16 . It is this I/Q gain error ΔA  32  and this I/Q phase error Δφ  34  that the receiver  10  of the present invention corrects before the received signal is frequency converted again and/or demodulated in order to estimate the transmitted data. 
   The I/Q gain error ΔA  32  results in a gain ratio (I/Q gain) different than unity between an effective gain for the I signal and an effective gain for the Q signal. The effective gain for the I signal is the signal gain from the point at which the amplified signal from the LNA  14  is split into the I and Q signal components in the quadrature downconverter  16  until the point at which the intermediate I signal is converted to a digital form in the A/D  20 I. The effective gain of the Q signal is the signal gain from the point at which the amplified RF signal from the LNA  14  is split into the I and Q signal components in the quadrature downconverter  16  until the intermediate Q signal is converted to a digital form in the A/D  20 Q. 
   Similarly, it should be noted that the I/Q phase imbalance (error) Δφ  34  results in a relative phase (I/Q phase) that is different than 90° between the effective phase of the I signal that is digitized by the A/D  20 I and the effective phase of the Q signal that is digitized by the Q A/D  20 Q. The relative phase (I/Q phase) includes the phase of the I signal LO cos w c t relative of the phase of the Q LO signal sin w c t and the effective signal phase shift from the point at which the amplified signal is split into I and Q signal components until the point at which the intermediate I signal is converted to a digital form in the A/D  20 I relative to the effective signal phase shift from the point at which the amplified signal is split into I and Q signal components until the point at which the intermediate Q signal is converted to a digital form in the A/D  20 Q. 
   The receiver  10  includes an IQ coefficient calculator  50 A or  50 B, an IQ balancer  52 A or  52 B, and a digital IQ signal receiver  54 . The receiver  10  may also include optional I and Q latency time delay devices  42 I and  42 Q, optional I and Q average detectors  44 I and  44 Q, and optional I and Q average correctors  46 I and  46 Q, The I and Q delay devices  42 I and  42 Q, the I and Q average detector  44 I and  44 Q, and the IQ coefficient calculator  50 A,B receive the digital I and Q signals from the I and Q A/Ds  20 I and  20 Q, respectively. After a certain number N of digital sample indexes n, equivalent to a latency time delay D where D equals N times the digital sample time for the indexes n, the I and Q delay devices  42 I and  42 Q reissue the digital I and Q signals to the I and Q average correctors  46 I and  46 Q. 
   Typically, the digital I and Q signals are received as packets ( FIG. 3 ) and the index N is equal to some portion of the total number of indexes n that are used for sampling one packet. The index N may be varied from close to 100% to 5% or even less of the total number of indexes n depending upon system considerations. Increasing the index N increases latency and decreases noise in the corrections. Decreasing the index N decreases latency and increases noise in the corrections. Preferably, the index N is about 10% to 30% of the total number of indexes n. For example, for a packet having a total number 942 of sample indexes n, the index N may be 192. 
   The I and Q average detectors  44 I and  44 Q use the number N of indexes n to calculate the averages for the digital I and Q signals, respectively, and pass I and Q average corrections to the I and Q average correctors  46 I and  46 Q. The I and Q average correctors  46 I and  46 Q use the I and Q average corrections based upon the first N of the indexes n for removing DC offset from digital I and Q signals for the entire packet from beginning to end. The IQ balancer  52 A,B receives the zero average digital I and Q signals, denoted i n  and q n , respectively, from the I and Q average correctors  46 I and  46 Q. In an alternative embodiment, the optionally delayed I and Q signals are passed directly to the IQ balancer  52 A,B and the averaging is performed further downstream in the digital IQ signal receiver  54 . 
   The first N of the indexes n of the digital I and Q signals from the A/Ds  20 I and  20 Q are selected or defined as an IQ measurement section D of the packet (FIG.  3 ). The IQ coefficient calculator  50 A,B uses the first N of the n indexes to calculate first and second correction coefficients. When the optional I and Q delay devices  42 I and  42 Q are not used, the digital I and Q signals from the I and Q A/Ds  20 I and  20 Q are passed directly to the I and Q average detectors  46 I and  46 Q or the IQ balancer  52 A,B. In this case the latency time of the IQ measurement section D may be avoided, however, the symbols in the IQ measurement section D of the packet ( FIG. 3 ) are not corrected in the IQ balancer  52 A,B. 
   The first and second correction coefficients correspond roughly to phase and gain correction coefficients. In a first embodiment, the IQ coefficient calculator  50 A calculates a first correction coefficient C 1  and a second correction coefficient C 2  as described in equations 1 and 2, below. In a second embodiment, the IQ coefficient calculator  50 B calculates a first correction coefficient C′ 1  and a second correction coefficient C′ 2  as described in equations 3 and 4, below. 
               C   1     =         ∑     n   =   1     N     ⁢          q   n                ∑     n   =   1     N     ⁢            i   n     -       q   n     ⁡     (       ∑     n   =   1     N     ⁢       i   n     ⁢       q   n     /       ∑     n   =   1     N     ⁢       q   n     ⁢     q   n               )                          (   1   )                 C   2     =     -       ∑     n   =   1     N     ⁢       i   n     ⁢       q   n     /       ∑     n   =   1     N     ⁢       q   n     ⁢     q   n                         (   2   )                 C   1   ′     =         ∑     n   =   1     N     ⁢          q   n                ∑     n   =   1     N     ⁢            i   n     -       q   n     ⁡     (       ∑     n   =   1     N     ⁢       i   n     ⁢       q   n     /       ∑     n   =   1     N     ⁢       q   n     ⁢     q   n               )                          (   3   )                 C   2   ′     =       -       ∑     n   =   1     N     ⁢            q   n          ⁢     (       ∑     n   =   1     N     ⁢       i   n     ⁢       q   n     /       ∑     n   =   1     N     ⁢       q   n     ⁢     q   n               )               ∑     n   =   1     N     ⁢            i   n     -       q   n     ⁡     (       ∑     n   =   1     N     ⁢       i   n     ⁢       q   n     /       ∑     n   =   1     N     ⁢       q   n     ⁢     q   n               )                          (   4   )             
 
   The IQ balancer  52 A,B uses the first and second correction coefficients C 1  and C 2  (or C′ 1  and C′ 2 ) to balance and correct the digital I and Q signals i n  and q n  in order to provide corrected digital I and Q signals, denoted as i ·c   n  and q c   n . It should be noted that the correction coefficients in the present invention are fixed for each packet. Where the optional I and Q delay devices  42 I and  42 Q are included, the correction coefficients are applied to the entire packet of delayed I and Q signals. Where the I and Q delay devices  42 I and  42 Q are not included, the IQ measurement section D ( FIG. 3 ) is the packet is not corrected. In this case the correction coefficients are applied to the portion of the packet that follows the IQ measurement section D. The corrected digital I and Q signals i ·c   n  and q c   n  are passed to the digital IQ signal receiver  54 . The digital IQ signal receiver  54  includes synchronization, demodulation, equalization, and bit detection subsystems for estimated the data that was carried by the wireless RF signal. 
     FIGS. 2A and 2B  are functional block diagrams of first and second embodiments of the IQ balancers  52 A and  52 B, respectively. The first embodiment IQ balancer  52 A includes a phase balancer  62 A, a summer  64 A, and a gain balancer  66 A. The phase balancer  62 A multiplies the Q signal q n  by the second coefficient C 2  to provide a phase correction signal C 2 *q n  to the summer  64 A. The summer  64 A adds the phase correction signal C 2 *q n  to the I signal i n  and passes the sum C 2 *q n +i n  to the gain balancer  66 A. The gain balancer  66 A multiplies the sum C 2 *q n +i n  by the first coefficient C 1  to provide the corrected I signal i c   n =C 1 *(C 2 *q n +i n ). The Q signal q n  is passed straight through as the corrected Q signal q c   n . Of course, the processing of the I and Q signals i n  and q n  could be exchanged. 
   Similarly, the second embodiment IQ balancer  52 B includes a phase balancer  62 B, a summer  64 B, and a gain balancer  66 B. The phase balancer  62 B multiplies the Q signal q n  by the second coefficient C′ 2  and provides a phase correction signal C′ 2 *q n  to the summer  64 B. The gain balancer  66 B multiplies the I signal i n  by the first coefficient C′ 1  and provides an amplitude correction signal C′ 1 *i n  to the summer  64 B. The summer  64 B adds the phase correction signal C′ 2 *q n  to the amplitude correction digital C′ 1 *i n  and provides the corrected I signal i ·c   n =C′ 1 *i n  as the sum. The Q signal q n  is passed straight through as the corrected Q signal q c   n . Of course, the processing of the I and Q signals i n  and q n  could be exchanged. 
   Simple algorithms for computing the correction coefficients in the IQ coefficient calculator  50 A,B are described with the aid of equations 5-12. 
               K   1     =       ∑     n   =   1     N     ⁢       i   n     ⁢     q   n                 (   5   )                 K   2     =       ∑     n   =   1     N     ⁢       q   n     ⁢     q   n                 (   6   )                 K   3     =       K   1       K   2               (   7   )                 K   4     =       ∑     n   =   1     N     ⁢          q   n                    (   8   )                 K   5     =       ∑     n   =   1     N     ⁢            i   n     -       K   3     ⁢     q   n                        (   9   )                 C   1     =       C   1   ′     =       K   4       K   5                 (   10   )             
 
 C   2   =−K   3   (11)
 
 C′   2   =−C′   1   K   3   (12)
 
   The IQ coefficient calculator  50 A,B computes the correction coefficients using the following algorithm: Given a vector of finite length N with indexes n for indexed I elements i n  and an equal length vector of indexed Q elements q n , let a first term K 1  equal the dot product (cross correlation) of the i n  elements and the q n  elements, let a second term K 2  equal a dot product (autocorrelation) of the q n  elements and the q n  elements, let a third term K 3  equal the quotient of the first term K 1  divided by the second term K 2 , let a fourth term K 4  equal the sum of the absolute values of the q n  elements, let Z be a vector of elements representing the i n  elements minus the product of the q n  elements times the third term K 3 , and finally let a fifth term K 5  equal a sum of the absolute values of the Z elements. 
   For the first embodiment where the IQ balancer  52 A corrects I and Q signals according to i c   n =C 1 *(C 2 *q n +i n ) and q c   n =q n , the IQ coefficient calculator  50 A computes the first correction coefficient C 1  equal to the fourth term K 4  divided by the fifth term K 5  and computes the second correction coefficient C 2  equal to the negative of the third term K 3 . 
   For the second embodiment where the IQ balancer  52 B corrects the I and Q signals according to i c   n =C′ 1 *i n +C′ 2 *q n  and q c   n =q n , the coefficient calculator  50 B computes the first correction coefficient C′ 1  equal to the fourth term K 4  divided by the fifth term K 5  and computes the second correction coefficient C′ 2  equal to the negative of the product of the first coefficient C′ 1  times the third term K 3 . 
   It should be understood that it is equivalent to exchange the processing of the i n  and q n  vectors for the equivalent result in the first embodiment and in the second embodiment. 
     FIGS. 2C and 2D  are block diagrams of symmetrical variations of the IQ balancers  52 A and  52 B referred to with reference identifiers  52 C and  52 D, respectively. The IQ balancer  52 C includes a phase balancer  62 C, a summer  64 C, and a gain balancer  66 C. The phase balancer  62 C multiplies the Q signal q n  by a coefficient C 2q  for providing a phase correction signal C 2q *q n  and multiplies the I signal i n  by a coefficient C 2i  for providing a phase correction signal C 2i *i n . The summer  64 C sums the phase correction signal C 2q *q n  with the I signal i n  and sums the phase correction signal C 2i *i n  with the Q signal q n  and then passes the sums to the gain balancer  66 C. The gain balancer  66 C multiplies the sum C 2q *q n +i n  by a coefficient C 1i  to provide the corrected I signal i c   n =C 1i *(C 2q *q n +i n ) and multiplies the sum C 2i *i n +q n  by a coefficient C 1q  to provide the corrected Q signal q c   n =C 1q *(C 2i *i n +q n ). It should be apparent that the values of any two of the coefficients C 1i , C 1q , C 2i  and C 2q  depend upon the values of the first coefficient C 1 , the second coefficient C 2 , and whatever values are selected for the other two of the coefficients C 1i , C 1q , C 2i  and C 2q . For example, if C 1q  is selected as unity (one) and C 2i  is selected as zero, then C 1i  equals the first coefficient C 1  and C 2q  equals the second coefficient C 2 . It should be noted that in this case the block diagram of  FIG. 2C  reduces to the block diagram of FIG.  2 A. 
   The IQ balancer  52 D includes a phase balancer  62 D, a summer  64 D, and a gain balancer  66 D. The phase balancer  62 D multiplies the Q signal q n  by a coefficient C′ 2q  for a phase correction signal C′ 2q *q n  and multiplies the I signal i n  by a coefficient C′ 2i  for a phase correction signal C′ 2i *i n . The gain balancer  66 D multiplies the Q signal q n  by a coefficient C′ 1q  and multiplies the I signal i n  by a coefficient C′ 1i . The summer  64 D adds the phase correction signal C′ 2q *q n  to the I gain signal C′ 1i *i n  to provide the corrected I signal C′ 2q *q n +C′ 1i *i n  and adds the phase correction signal C′ 2i *i n  to the Q gain signal C′ 1q *q n  to provide the corrected I signal C′ 2i *i n +C′ 1q *q n . It should be apparent that the values of any two of the coefficients C′ 1i , C′ 1q , C′ 2i  and C′ 2q  depend upon the values of the first coefficient C′ 1 , the second coefficient C′ 2 , and whatever values are selected for the other two of the coefficients C′ 1i , C′ 1q , C′ 2i  and C′ 2q . For example, if C′ 1q  is selected as unity (one) and C′ 2i  is selected as zero, then C′ 1i  is the first coefficient C′ 1  and C′ 2q  is the second coefficient C′ 2 . It should be noted that in this case the block diagram of  FIG. 2C  reduces to the block diagram of FIG.  2 A. 
   Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.