Abstract:
Power management methods, systems and circuitry are provided for efficiently energizing implanted stimulators. Efficiency is achieved by automatically adjusting the power-supply voltage of the stimulator channel so that the magnitude of the voltage of the current-sink or current-source providing the stimulation current is regulated within a narrow band just above the minimum acceptable level. Adjustment is done once in every cycle of the external high-frequency power source in order to achieve regulation with a very fine time resolution throughout each stimulation period. The power supply voltage is generated and adjusted by rectifying the high-frequency voltage of the secondary coil of a transcutaneous magnetic link by closing and opening a solid-state switch at appropriate times during positive half cycles for a current-sink, and during negative half-cycles for a current-source. The timing of switch closure and opening is dictated by a logic controller on the basis of two binary signals generated by two separate comparators, one of which comparing the voltage of the secondary coil with the generated power-supply voltage, and the other comparing the current-sink or current-source voltage with a reference voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a U.S. National Phase application, under 35 U.S.C. §371, of International Application no. PCT/IB2009/054249, with an international filing date of Sep. 29, 2009, which is hereby incorporated by reference for all purposes. 
     BACKGROUND 
     Electrical stimulation of nerves and tissues by implanted stimulators is widely utilized for treating a number of disorders including deafness, blindness, pain and sleep apnea. Stimulation is performed by forcing constant-current pulses between pairs of implanted electrodes in intimate contact with the tissue. Stimulator may contain just one pair of electrodes or a plurality of electrodes, out of which, appropriate pairs are selected for stimulating different localities of tissue in a sequential manner. There exist various different circuit architectures for generating the current pulses and commuting them among electrode pairs. A simplified schematic of one example is shown in  FIG. 1 . The stimulator contains N electrodes E 1 , E 2 , . . . , E N , which, in most cases, are capacitively coupled to the tissue. These electrodes are connectable to a dc power supply source  101  of voltage V +  by means of switches S 1A , S 2A , . . . , S NA , and to a current sink  102  of stimulation current I by means of switches S 1B , S 2B , . . . , S NB . Any pair of electrodes can be selected for stimulation by connecting one of the electrodes to the voltage source  101  and the other to the current sink  102 . If, for example, electrode E 1  is connected to the voltage source  101  and electrode E 2  is connected to the current sink  102  by closing S 1A  and S 2B , a constant current I set by the current sink  102  enters the tissue at electrode E 1  and exits the tissue at electrode E 2 , and flows in that direction for a prescribed time. It is possible to reverse the direction of current by closing switches S 1B  and S 2A  instead of S 1A  and S 2B . As a matter of fact, each stimulation event of the selected electrode pair is usually performed in two phases; once with the current flowing in one direction through the electrode pair, and next with the same current flowing in the reverse direction through the same electrode pair. By making the durations of these two phases of stimulation identical, the average charge injected into the tissue is nullified to prevent the occurrence of potentially harmful chemical reactions between the electrodes and tissue. This type of stimulation is commonly known as “biphasic stimulation.” If only one of the two phases is applied, then, stimulation is called “monophasic stimulation.” 
     A simplified schematic of an alternative stimulator circuit architecture is shown in  FIG. 2 . This stimulator differs from that of  FIG. 1  in two aspects: (i) the stimulation current I is set by a current source  202  instead of the current sink  102  of  FIG. 1 , and (ii) a power supply voltage source  201  of negative dc voltage V −  is employed instead of the positive dc voltage V +  of  FIG. 1 . Otherwise, the structure and operation of this stimulator is essentially identical to that of the stimulator shown in  FIG. 1 . 
     In most cases, the energy dissipated in the stimulator circuit of  FIG. 1  or  FIG. 2  is supplied by a transcutaneous magnetic link. One conventional energy supply circuit is shown in  FIG. 3 . It contains a magnetic link  31  and a rectifier/filter circuit  32 . The external primary coil  301  of the magnetic link is driven with a high-frequency alternating voltage V PC  from an external power supply  305 . The alternating voltage V SC  of the implanted secondary coil  302  is half-wave rectified with a diode  303 , and the rectified voltage is filtered with a capacitor  304  to generate the dc power supply voltage V + . More sophisticated cases may involve amplitude doubling of the secondary coil alternating voltage V SC , full-wave rectification instead of half wave, and/or post-filter regulation. 
       FIG. 3  also depicts the stimulation current I sunk from V +  by the current sink  102  via electrodes E 1  and E 2  in compliance with the stimulator architecture shown in  FIG. 1 . Total equivalent resistance of the two switches connecting these two electrodes between V +  and current sink  102  (e.g., S 1A  and S 2B , or S 1B  and S 2A ) is represented with R in  FIG. 3 . Also shown in  FIG. 3  is an equivalent load impedance Z L , which represents the combined impedance of (i) the two electrode-tissue interfaces, (ii) the bulk of the stimulated tissue, and (iii) the capacitance of the electrode coupling capacitors. 
     Notice from  FIG. 3  that V +  is the sum of the following three individual voltages: (i) The voltage V S  of the current sink  102 , (ii) the voltage V L  of the load impedance Z L , and (iii) the voltage V R  of the total switch resistance R. Among these three voltages, V R  can be made as small as desired by reducing the switch resistance R. V S , on the other hand, should be kept greater than a minimum level acceptable by the current sink  102  for maintaining the constant stimulation current I. This acceptable minimum level, however, can be made as low as several hundred millivolts by proper design. V L , on the other hand, is highly variable because (i) the range in which I is prescribed may be no less than two decades wide, and (ii) Z L  varies not only with time during the duration of stimulation due to its capacitive components but also from one electrode pair to another depending on the condition of the electrode-tissue interfaces and the condition of the tissue itself. In cochlear stimulators, for example, the prescribed value of I may vary between tens of microamps and several milliamps, while Z L  may vary from less than a kilohm up to a ten kilohm or so. Therefore, V L  may be anywhere within the range between ten millivolts and ten volts. 
     For proper operation of the stimulator, the power supply voltage V +  must be set to accommodate even the highest end of this wide range of V L . Otherwise, whenever a maximum V L  is demanded, V S  will drop below the acceptable minimum needed by the current sink  102  for providing the prescribed stimulation current. If, on the other hand, V +  is set to be sufficiently high to accommodate the maximum expected V L , then, under typical conditions of much lesser V L , V S  will rise much above the acceptable minimum level needed by the current sink  102 . This will result in unnecessary waste of energy on the current sink  102 . For a numerical illustration of this undesirable outcome, consider an example in which the expected maximum load impedance (Z L ) is 10 kΩ and the maximum expected stimulation current (I) is 1 mA. Therefore, the maximum expected value of V L  is 10 V. Assuming a negligible switch resistance (R) and a minimum acceptable V S  of 1 V for proper current-sink operation, V +  should be set to 11 V to cover this worst-case situation. But then, if a load impedance of 1 kΩ is stimulated with a current of 1 mA, V L  will fall to 1 V, and V S  will rise to 10 V. The current sink will then operate with a voltage excess of 9 V leading to a waste power of 9(V)×1 (mA)=9 mW. 
     Methods of minimizing the waste of energy on the current source or sink of a nerve stimulator are disclosed in a number of patents. U.S. Pat. No. 7,295,872 issued Nov. 13, 2007 in the name of inventors Shawn Kelly et. al., for example, discloses a technique of replacing the current source/sink circuitry with a voltage source whose voltage varies with time in such a way that the desired constant current is maintained through the electrodes. Unfortunately, the viability of this technique depends on a quantitatively accurate knowledge of the load impedance, which is almost never available due to the uncertainties associated with the electrical properties of the electrode-tissue interface and of the current path through the tissue. 
     U.S. Pat. No. 7,444,181 issued Oct. 28, 2008 in the name of inventors Jess Weigian et. al., discloses a technique of measuring the voltage of the current source or sink once in a stimulation period and making adjustments to the power supply voltage to minimize the voltage of the current source or sink. Measured voltage is assessed by a microcontroller to determine whether the power supply voltage should be decremented or incremented in fixed steps. Due to a lack of continuous control of the power supply voltage during stimulation period, however, adjustment has to be made for the largest value of the load impedance observed in each stimulation period. This can result in excessive loss of energy during the early part of a stimulation period when load impedance is relatively small. Also, the technique necessitates a complex hardware to implement its algorithmic prescriptions. Furthermore, the voltage regulator used for adjusting the power supply voltage can potentially consume the energy saved from the current source/sink. 
     U.S. Pat. No. 7,519,428 issued Apr. 14, 2009 in the name of inventor Logan P. Palmer, teaches a technique by which electrodes can operate from two separate power-supply voltages, one being twice as large as the other. Electrodes with sufficiently small load voltage are supplied from the smaller of these voltages, while the others are supplied from the larger voltage. Energy consumption is halved whenever the former group of electrodes are stimulated, but this does not necessarily imply a minimized consumption. Furthermore, a priori knowledge of the maximum load voltage is needed for each electrode individually for correct power-supply voltage assignment. 
     SUMMARY OF THE INVENTION 
     The present invention provides power management methods, systems and circuitry for energizing the stimulator channels with a dedicated power-supply voltage adjusted automatically once in every high-frequency cycle throughout each stimulation period to regulate the magnitude of the current-sink or current-source voltage within a narrow band just above the minimum acceptable level for the current sink or source to sustain the demanded stimulation current. The term “stimulation channel,” as used herein, refers to the electrical path comprising (i) the current source or sink by which a stimulation current is forced through a pair of electrodes, (ii) said pair of electrodes, and if present, their coupling capacitors, (iii) switches by which said pair of electrodes are selected and connected between the power supply voltage and the current source or sink, and (iv) the tissue situated in between said pair of electrodes. 
     Since the duration of even the shortest stimulation pulse is no shorter than a hundred or so high-frequency cycles, regulation of the current-sink or current-source voltage is accomplished with a very fine time resolution. While the current-sink or current-source voltage is thus regulated independently of the value of stimulation current or load and switch impedances, power supply voltage automatically adjusts itself in each high-frequency cycle to be the sum of (i) load and switch voltages, and (ii) current-sink or current-source voltage whose magnitude is thus minimized. Unnecessary energy loss on the current sink or current source is thus eliminated. 
     The present invention can be practiced in any of the two architectures shown in  FIG. 1  and  FIG. 2 , respectively. It can be practiced also in variants of these architectures, where, for example, each stimulation channel has a separate current sink or source. Also, it is applicable in monophasic or biphasic stimulation. 
     The power-supply voltage is obtained by rectifying the high-frequency alternating voltage of the secondary coil of a transcutaneous magnetic link, and is stored across a filtering capacitor. Rectification and automatic adjustment of the power-supply voltage is accomplished by closing and opening a solid-state switch between the secondary coil and capacitor at appropriate times during positive half cycles for a current-sink, and during negative half-cycles for a current-source. The timing of switch closure and opening is dictated by a logic controller on the basis of two binary signals generated by two separate comparators, first of which compares the high-frequency alternating voltage of the secondary coil with the generated power-supply voltage, and the second compares the current-sink or current-source voltage with a reference voltage. The leading and trailing edges of the binary signal of the former of these two comparators identify the instants of the high-frequency alternating voltage of the secondary coil crossing over or under the generated power-supply voltage in each high-frequency cycle. If switch closure is needed in any given high-frequency cycle, the logic controller initiates it at the appropriate one of these two instants when the voltage across the switch vanishes. Thus the energy consumed on the switch is minimized. Whether a switch closure is needed or not in a given high-frequency cycle is determined by the logic controller from the prevailing level of the binary signal generated by the second comparator. The switch is closed if the current-sink or current-source voltage is less than the reference voltage, otherwise it is kept open for the entire duration of the high-frequency cycle. Adjustment of the power-supply voltage is deemed complete when the current-sink or current-source voltage exceeds the reference voltage. The logic controller opens the switch at that particular instant of the high-frequency cycle. If adjustment has not been completed before the instant voltage across the switch vanishes again, the switch is nevertheless opened at that instant in order not to start discharging the capacitor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features and benefits of the present invention will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings wherein: 
         FIG. 1  shows the circuit architecture of an implanted stimulator equipped with a positive power-supply voltage and a current sink (prior art); 
         FIG. 2  shows the circuit architecture of an implanted stimulator equipped with a negative power-supply voltage and a current source (prior art); 
         FIG. 3  depicts a schematic diagram of a transcutaneous magnetic link supplying power to a stimulation channel operating with a positive power-supply voltage and a current sink (prior art); 
         FIG. 4  shows, in accordance with the present methods, systems and circuits, a schematic diagram of power management for a stimulation channel operating with a positive power-supply voltage and a current sink; 
         FIG. 5  depicts, in accordance with the present methods, systems and circuits, a set of voltage waveforms exemplifying the periodic steady-state operation of the embodiment shown in  FIG. 4 , in one of the high-frequency cycles of a stimulation period; 
         FIG. 6  shows, in accordance with the present methods, systems and circuits, a circuit diagram of one exemplary topology of the logic controller and switch depicted in  FIG. 4 ; 
         FIG. 7  depicts, in accordance with the present methods, systems and circuits, simulated waveforms representing the transient and steady-state behavior of the embodiment shown in  FIG. 4  employing the logic-controller and switch circuit of  FIG. 6 ; 
         FIG. 8  depicts, in accordance with the present methods, systems and circuits, a schematic diagram of power management for a stimulation channel operating with a negative power-supply voltage and a current source; 
         FIG. 9  depicts, in accordance with the present methods, systems and circuits, a set of voltage waveforms exemplifying the periodic steady-state operation of the embodiment shown in  FIG. 8 , in one of the high-frequency cycles of a stimulation period; 
         FIG. 10  shows, in accordance with the present methods, systems and circuits, a circuit diagram of one exemplary topology of the logic controller and switch depicted in  FIG. 8 ; 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Shown in  FIG. 4  is an exemplary embodiment of the disclosed power management method as applied to a stimulation channel of the architecture of  FIG. 1 . The external primary coil  301  of a transcutaneous magnetic link  31  is driven with a high-frequency sinusoidal voltage V PC  from an external power supply  305 . The sinusoidal voltage V SC  of the implanted secondary coil  302  is half-wave rectified by turning on and off a switch  403  between nodes  404  and  405  at appropriate times, and the rectified voltage is filtered with a capacitor  304  of capacitance C to generate a positive power-supply voltage V + . Optionally, a second capacitor can be connected in parallel with the secondary coil so that the capacitance of this second capacitor and the inductance of the secondary coil form a resonant tank circuit, which helps increase the amplitude of V SC . Selection of a sinusoidal waveform for V PC , and hence for V SC , is for illustrative purposes only; other alternating waveforms of gradually rising and falling edges (e.g., triangular waveform) can also be employed. It is also possible to double or triple the amplitude of V SC  prior to rectification. 
       FIG. 4  also depicts a stimulation current I being sunk from V +  by the current sink  102  via electrodes E 1  and E 2 . Total equivalent resistance of the two switches connecting these electrodes between V +  and current sink  102  in the architecture of  FIG. 1  (e.g., S 1A  and S 2B , or S 1B  and S 2A ) is represented with R in  FIG. 4 . Also shown in  FIG. 4  is the load impedance Z L , which represents the combined impedance of (i) the two electrode-tissue interfaces at E 1  and E 2 , (ii) the bulk of the stimulated tissue, and (iii) the capacitance of electrode coupling capacitors. 
     Switch  403  is controlled according to the binary signals generated by the two voltage comparators  406  and  407 . Comparator  406  compares the voltage V S  of current-sink  102  with a positive reference voltage V REF  provided by the voltage source  409 , and generates a binary output signal Y HL  whose binary levels represent the cases of V S  being more positive or less positive than V REF . V REF  is set slightly more positive than the minimum acceptable value of V S  for which the current sink can function properly for the demanded stimulation current. Alternatively, comparator  406  can be replaced with a Schmitt trigger of a small hysteresis range around a built-in reference voltage equivalent to V REF . Comparator  407  compares the instantaneous value of the secondary-coil sinusoidal voltage V SC  with the power-supply voltage V + , and generates a binary output signal Y CLK  whose binary levels represent the cases of V SC  being more positive or less positive than V + . Y HL  and Y CLK  are fed into a logic controller  408 , whose binary output signal Y S  opens or closes the switch  403  in each and every high-frequency cycle in accordance with the Rule-1 stated below:
         Rule-1: In each high-frequency cycle, sample the output Y HL  of comparator  406  at the instant when the output Y CLK  of comparator  407  indicates that V SC  is crossing over V + , and take one of the following two actions:   Action-1 of Rule-1 If the sampled level of Y HL  indicates a V S  less positive than V REF , then, close the switch  403 , and keep it closed until (i) V S  crosses over V REF , or (ii) V SC  crosses under V + , whichever comes first. Open the switch  403  when the earlier of these two events occurs, and keep it open until the next instant of sampling.   Action-2 of Rule-1 If the sampled level of Y HL  is indicative of V S  being more positive than V REF , then, keep switch  403  open until the next instant of sampling.       

     Shown in  FIG. 5  is a set of voltage waveforms exemplifying the periodic steady-state operation of the embodiment of  FIG. 4  in one of the high-frequency cycles of a stimulation period. For purely illustrative purposes, a binary-high level is assumed to represent (i) the condition V SC &gt;V +  for V CLK , and (ii) the condition V S &gt;V REF  for Y HL , and a binary-low level is assumed for the condition of switch closure for Y S . Those skilled in the art will appreciate that the logic controller  408  and the switch  403  can be designed to execute Rule-1 also with complementary representations of Y CLK  Y HL , and Y S . 
     Execution of the power management method in periodic steady-state can now be explained in conjunction with  FIG. 4  and  FIG. 5 .  FIG. 5  shows V SC  crossing over V +  at time t 1 . This event is signalled to logic controller  408  by the comparator  407  raising Y CLK  to the binary-high level. At this instant, logic controller  408  samples the output signal Y HL  of comparator  406 , which signals the condition of V S  being less positive than V REF . In compliance with Action-1 of Rule-1, logic controller  408  closes the switch  403  by lowering its output signal Y S  to the binary-low level as fast as it can. The secondary coil  302  now starts charging the capacitor  304  while also supporting the stimulation current I. As a consequence, V +  starts rising. V S , tracking V + , also starts rising. Eventually, at time t 2 , V S  reaches V REF . This event is detected by the comparator  406 , which consequently raises its output signal Y HL  to the binary-high level. Logic controller  408  responds by also raising its output signal Y S  to the binary-high level, and thus opens the switch  403  in accordance with Action-1 of Rule-1. Due to the nonzero response time of the comparator  406 , logic controller  408  and switch  403 , however, the instant of switch opening is somewhat delayed with respect to the actual instant of V S  crossing over V REF . This delay causes V S  to slightly overshoot V REF  before switch  403  is opened. Thereafter, secondary coil  302  is left open, and the stimulation current I starts draining the charge accumulated on the capacitor  304 . As a consequence, V +  starts declining at a rate of I/C per unit time until V SC  crosses it over again at time t 5  of the next high-frequency cycle when logic controller  408  will renew sampling and update V +  in accordance with Rule-1. During the time between t 2  and t 5 , V S  tracks the declining V +  with a difference V R +V L , where V R =I×R and V L =I×Z L . This difference remains constant to a very good approximation because the time-constant of the possible variation of V R +V L  is usually much longer than the time difference between t 2  and t 5 . Therefore, the ripple on V S  (i.e., the total variation of V S  between t 2  and t 5 ) is almost the same as the ripple on V +  (i.e., the total variation of V +  between t 2  and t 5 ). Assuming that the duration t 2 −t 1  of the closed state of switch  403  is negligibly short in comparison with the period T of the high-frequency cycle, the common ripple is given approximately by IT/C. By selecting a sufficiently large C, this ripple can be minimized, and thus V S  is stabilized within a narrow band around V REF  regardless of the value of I or Z L  or R. Notice that V +  adjusts itself once in each high-frequency cycle to keep V S  regulated within this band around V REF  throughout an entire stimulation period. As noted before, V REF  is set slightly larger than the minimum voltage needed by the current sink to function properly. Therefore, the current sink  102  consumes the minimum necessary energy at all times while the prescribed stimulation current is successfully sunk independently of load and switch impedances. 
     For a better understanding of the reasoning behind various aspects of Rule-1, attention is now turned first to the fact that, if switch  403  is to be closed to raise V +  in any high-frequency cycle, closure should not commence before V SC  crosses over V + , and should not continue after V SC  crosses under V + . This is because switch closure outside this interval would discharge the capacitor  304  instead of charging it. Notice that Action-1 of Rule-1 mandates switch closure right at the beginning of this interval, as exemplified by time t 1  and time t 5  in  FIG. 5 , because the energy consumption of switch  403  increases with delay in closure. 
     Turning attention next to the timing of switch opening, Action-1 of Rule-1 mandates opening at the moment of V S  crossing over V REF  if this moment arrives before V SC  crosses under V + , as exemplified by time t 2  in  FIG. 5 . This timing is indeed optimum because (i) a later opening would extend V S  far above V REF  since charging can continue until V SC  crosses under V + , and (ii) an earlier opening would prematurely end the charging process, and thus prevent V S  from reaching V REF . In any case, opening of the switch should not be delayed beyond the moment of V SC  crossing under V +  in order to avoid discharge. This is why Action-1 of Rule-1 mandates opening at the moment of V SC  crossing under V +  even if V S  is still short of V REF . This case is unlikely to be encountered in any high-frequency cycle during the periodic steady-state of a stimulation period, and therefore, is not exemplified in  FIG. 5 , but may be observed in the first few high-frequency cycles of the initial transient state of a stimulation period if a large stimulation current is demanded. A large stimulation current necessitates a large V + , which, in turn, necessitates a large amount of charge to be delivered to the capacitor  304 . If such a large charge cannot be completely delivered by the time V SC  crosses under V + , V S  enters the next cycle with a value below V REF . However, this deficiency is progressively reduced in the following cycles, and thus the steady-state phase of the stimulation period is eventually reached. This case will be further exemplified later in  FIG. 7 . 
     Attention is finally turned to the reasoning behind Action-2 of Rule-1. As explained before, the delay in signal propagation through comparator  406 , logic controller  408  and switch  403  causes V S  to slightly overshoot V REF  before switch  403  is opened. Once the switch has been opened, V S  starts declining, and eventually crosses under V REF  again. This is seen to occur at time t 3  in the example of  FIG. 5 . In the case of a weak stimulation current I, however, the rate of decline may be so slow that V S  may remain above V REF  at the sampling time of the next high-frequency cycle (e.g., time t 5  in  FIG. 5 ). In such a case, Action-2 of Rule-1 keeps switch  403  open for the entirety of the next high-frequency cycle even if V S  crosses under V REF  sometime during that next cycle. This prevents switch closure at a time other than the moment of V SC  crossing over V + , and thus minimizes the energy consumed by switch  403 . This case will be further exemplified later in  FIG. 7 . 
     As understood from the description given so far, the circuitry by which the disclosed power management method is applied to the architecture of  FIG. 1  comprises the capacitor  304 , comparators  406  and  407 , the logic controller  408  and the switch  403 . These are connected to the rest of the stimulation hardware as per  FIG. 4 . Except for the capacitor  304 , these circuits are preferably integrated on the same chip together with other circuitry needed for performing stimulation. Considering the fact that V +  is variable, a separate constant positive power-supply voltage or a combination of positive and negative power-supply voltages is preferably employed for energizing these circuits as well as other circuits needed for performing the stimulation. These separate power-supply voltages can be generated from the secondary coil  302  with any conventional method such as the one illustrated in  FIG. 3 . 
     In regard to the implementation specifics of these circuits, the comparators  406  and  407  can be constructed in any suitable comparator topology known in the art. Switch  403  can be implemented with any suitable solid-state device known in the art, most preferably with a PMOSFET device. Logic controller  408  should be designed as an application specific circuit because it has the specific duty of executing Rule-1. 
     The circuit diagram of one exemplary topology of the logic controller  408  and the switch  403  is shown in  FIG. 6 . This exemplary topology employs only a positive power-supply voltage V DD  applied to node  606 , whereas node  607  is connected to the ground. Those skilled in the art will appreciate that an additional negative power-supply voltage can be incorporated by disconnecting node  607  from ground and connecting it to the negative power-supply voltage. 
     Notice that the PMOSFET device Ms implements the switch  403 , whereas the circuit  60  implements the logic controller  408 . 
     The gate terminal of Ms is attached to the output node  603  of the logic controller  60 . Node  603  carries the binary switch-control signal Y S  described previously in conjunction with  FIG. 4  and  FIG. 5 . The bulk terminal of M S  (not shown in  FIG. 6 ) is connected to the constant positive power-supply voltage rail V DD  at node  606 . The remaining two terminals of M S  are connected to node  404  of  FIG. 4  and node  405  of  FIG. 4 , respectively. The propagation delay of the logic controller  60  may be unacceptably long if the gate capacitance of M S  is large. If necessary, this problem can be solved by inserting a non-inverting buffer circuit between the output of the logic controller  60  and the gate of M S  instead of directly interconnecting them as shown in  FIG. 6 . 
     Logic controller  60  comprises a dynamic inverter circuit  61  and a static two-input NAND gate  62 . The dynamic inverter is built with NMOSFET devices M 1  and M 2 , and PMOSFET device M 3 . The NAND gate is built with NMOSFET devices M 4  and M 5 , and PMOSFET devices M 6  and M 7 . C P  represents the parasitic capacitance of node  601 . Notice that the dynamic inverter  61  drives one of the two inputs of the NAND gate  62  with its output signal Y I  at node  601 , whereas the other input of the NAND gate is driven at node  602  by the Y CLK  signal described previously in conjunction with  FIG. 4  and  FIG. 5 . One of the inputs of the dynamic inverter  61  receives at node  604  the same Y CLK  signal, and the other input receives at node  605  the Y HL  signal described previously in conjunction with  FIG. 4  and  FIG. 5 . Node  607  is designated as ground. Note that all NMOSFET devices have their bulk (not shown in  FIG. 6 ) connected to node  607 , and all PMOSFET devices have their bulk (not shown in  FIG. 6 ) connected to node  606 . 
     The operation of the logic controller  60  can now be explained with reference to  FIG. 4 ,  FIG. 5 , and  FIG. 6 . 
     Consideration is given first to the case of Y CLK  being at ground (i.e., binary-low level). As previously explained, this binary level of Y CLK  signals the case of V SC  being less positive than V + , for which the switching PMOSFET M S  should be kept open. Indeed, whenever Y CLK  is at ground, NAND gate  62  keeps Y S  at V DD  (i.e., binary-high level), and therefore M S  remains in cutoff (i.e., open switch state). As to the behavior of the dynamic inverter in the case of Y CLK  being at ground, notice that M 3  keeps the output signal Y I  of the dynamic inverter at the binary-high level V DD  regardless of the binary level of Y HL . Therefore, C P  is kept charged to V DD  whenever Y CLK  is at ground. 
     Consideration is given next to the case of Y CLK  making a transition from ground to V DD  while Y HL  is at V DD . This is the sampling moment when Action-2 of Rule-1 is to be executed. The rising Y CLK  forces M 3  into cutoff and M 1  into conduction, and thus disconnects node  601  from V DD , and connects node  608  to ground. Since M 2  is also conducting due to Y HL  being at V DD , C P  is discharged, and hence, Y I  is forced to ground. Now that one of its inputs being lowered to ground, the NAND gate  62  keeps its output Y S  at V DD  although its second input receiving Y CLK  is raised to V DD . Y S  being at V DD , M S  retains its cutoff state (i.e., open switch state). Notice that, even if Y HL  happens to return later to ground (i.e., V S  crossing under V REF ) while Y CLK  is still at V DD  (i.e., V SC  being more positive than V + ), M S  will continue to be in cutoff because C P  cannot be recharged to V DD  before the next falling edge of Y CLK.  After the arrival of the next falling edge of Y CLK ) Y S  is kept at V DD  anyway, as explained in the preceding paragraph. Therefore, M S  remains in cutoff for the entire cycle if V S  is more positive than V REF  at the beginning of the cycle, as mandated by Action-2 of Rule-1. 
     If Y HL  is at the ground level when Y CLK  makes a transition from ground to V DD , Action-1 of Rule-1 is to be executed. In this case, the rising Y CLK  again forces M 3  into cutoff and M 1  into conduction, and thus disconnects node  601  from V DD , and connects node  608  to ground. But, since Y HL  is at the ground level, M 2  remains in cutoff, and despite the fact that node  608  is connecting the ground, node  601  is left afloat. This enables C P  to retain its charge, and thus to keep Y I  at V DD . Now, the NAND gate  62  with both inputs at V DD , lowers Y S  to ground, and thus turns M S  on (i.e., closed switch state). If, subsequently, the rising V S  crosses over V REF , and therefore, Y HL  rises to V DD  before Y CLK  drops to ground, then, M 2  turns on, and together with the conducting M 1 , discharges C P  to ground. Y I  being lowered to ground, the NAND gate  62  raises Y S  to V DD , and thus forces M S  into cutoff (i.e., open switch state). Since C P  cannot be recharged to V DD  before the next falling edge of Y CLK , M S  remains in cutoff even if Y HL  happens to return to ground any time before Y CLK  drops to ground. If, on the other hand, Y CLK  drops to ground before Y HL  rises to V DD , then, the NAND gate  62  raises Y S  to V DD , and thus forces M S  into cutoff (i.e., open switch state) at the moment Y CLK  drops to ground. 
     Further illustration of the transient and steady-state behavior of the entire stimulator circuit of  FIG. 4  employing the logic-controller and switch circuit of  FIG. 6  is provided in  FIG. 7  in the form of simulated waveforms. These waveforms belong to the voltages V SC , V + , V S , Y S , and the stimulation current I during the first ten 5-MHz cycles of a long stimulation period. Notice that only the positive half cycles of V SC  are shown for the sake of brevity. V REF  is set to 0.9 V, V DD  is set to 10 V, and a stimulation episode is started up shortly after t=6 μs by stepwise demanding 1-mA stimulation current from the current sink. First sampling instant after start-up arrives at the beginning of the second cycle shortly after t=6.2 μs when V SC  crosses over V + . Since V S  is smaller than V REF  at this instant of sampling, Y S  is lowered to ground, and thus the switch  403  is closed at that instant. Notice that, V SC  crosses under V +  in that second cycle while V S  is still considerably short of V REF . The switch  403  is nevertheless opened by Y S  raising to V DD  in order not to start discharging the capacitor  304 . Since V S  is left below the minimum acceptable level for the current sink to function properly, the stimulation current has not reached the demanded level of 1 mA by the end of that second cycle. The switch  403  is again closed when V SC  crosses over V +  in the third cycle just after t=6.4 μs, and charging of V S  to V REF  is completed before V SC  crosses under V + , and therefore, the switch  403  is opened earlier in that third cycle. Notice the absence of switch closure in the fourth cycle starting at t=6.6 μs. This is due to the fact that V S  has somewhat overshot V REF  in the previous cycle, and has not declined back to V REF  yet at the sampling moment of the fourth cycle. The transient events observed in the second, third and fourth cycles come to an end at the fifth cycle, beyond which the periodic steady-state prevails. In this state, switch closure lasts for a brief interval in each cycle, V S  is stabilized around V REF , but V +  continues to rise to accommodate the increasing load impedance. 
     The disclosed power management method has so far been described on the embodiment shown in  FIG. 4 , which is applicable to the stimulation channels of the architecture shown in  FIG. 1 . A second embodiment of the same method applicable to the stimulation channels of the architecture of  FIG. 2  is shown in  FIG. 8 . A comparison between  FIG. 8  and  FIG. 4  reveals three differences: (i) Current sink  102  of  FIG. 4  is replaced with the current source  202  in  FIG. 8 , (ii) positive voltage reference  409  of  FIG. 4  is replaced with a negative voltage reference  809  in  FIG. 8 , and (iii) the positive power-supply voltage V +  of  FIG. 4  is replaced with a negative power-supply voltage V −  in  FIG. 8 . The voltages V R , V L , V S  and V REF  defined in  FIG. 8  are all negative valued. 
     The duty of comparator  806 , comparator  807  and logic controller  808  is essentially the same as the duty of their respective counterparts shown in  FIG. 4 . These circuits as well as other circuits needed for stimulation are preferably supplied from a separate constant negative power-supply voltage or a pair of negative and positive power-supply voltages, which can be generated from the secondary coil  302  with any conventional method. The rule by which the logic controller rectifies V SC  and regulates V S  is based on the same principles as Rule-1 but differs from the latter in the polarity of the conditional statements in order to enable rectification at negative half cycles. The rule is stated below as Rule-2:
         Rule-2: In each high-frequency cycle, sample the output Y HL  of comparator  806  at the instant when the output Y CLK  of comparator  807  indicates that V SC  is crossing under V − , and take one of the following two actions:   Action-1 of Rule-2 If the sampled level of Y HL  indicates a V S  less negative than V REF , then, close the switch  803 , and keep it closed until (i) V S  crosses under V REF , or (ii) V SC  crosses over V − , whichever comes first. Open the switch  803  when the earlier of these two events occurs, and keep it open until the next instant of sampling.   Action-2 of Rule-2 If the sampled level of Y HL  is indicative of V S  being more negative than V REF , then, keep switch  803  open until the next instant of sampling.       

     Shown in  FIG. 9  is a set of voltage waveforms exemplifying the periodic steady-state operation of the embodiment of  FIG. 8  in one of the high-frequency cycles of a stimulation period. For purely illustrative purposes, a binary-low level is assumed to represent (i) the condition V SC &lt;V −  for Y CLK , and (ii) the condition V S &lt;V REF  for Y HL , and a binary-high level is assumed for the condition of switch closure for Y S . Those skilled in the art will appreciate that the logic controller  808  and the switch  803  can be designed to execute Rule-2 also with complementary representations of Y CLK,  Y HL , and Y S . A person skilled in the art can also interpret the waveforms given in  FIG. 9  along the lines of the description given previously for  FIG. 5 . 
     In regard to the implementation of the embodiment exemplified in  FIG. 8 , the comparators  806  and  807  can be constructed in any suitable comparator topology known in the art. Switch  803  can be implemented with any suitable solid-state device known in the art, most preferably with an NMOSFET device. Logic controller  808  should be designed as an application specific circuit because it has the specific duty of executing Rule-2. 
     The circuit diagram of one exemplary topology of the logic controller  808  and the switch  803  is given in  FIG. 10 . This exemplary topology employs only a negative power-supply voltage V SS  applied to node  907 , whereas node  906  is connected to the ground. Those skilled in the art will appreciate that an additional positive power-supply voltage can be incorporated by disconnecting node  906  from ground and connecting it to the positive power-supply voltage. 
     Notice that the NMOSFET device M S  implements the switch  803 , whereas the circuit  90  implements the logic controller  808 . 
     The gate terminal of M S  is attached to the output node  903  of the logic controller  90 . Node  903  carries the binary switch-control signal Y S  previously described in conjunction with  FIG. 8  and exemplified in  FIG. 9 . The bulk terminal of M S  (not shown in  FIG. 10 ) is connected to the constant negative power-supply voltage V SS  at node  907 . The remaining two terminals of M S  are connected to node  804  of  FIG. 8  and node  805  of  FIG. 8 , respectively. The propagation delay of the logic controller  90  may be unacceptably long if the gate capacitance of M S  is large. If necessary, this problem can be solved by inserting a non-inverting buffer circuit between the output of the logic controller  90  and the gate of M S  instead of directly interconnecting them as in  FIG. 10 . 
     Logic controller  90  comprises a dynamic inverter circuit  91  and a static two-input NOR gate  92 . The dynamic inverter is built with PMOSFET devices M 1  and M 2 , and NMOSFET device M 3 . The NOR gate is built with PMOSFET devices M 4  and M 5 , and NMOSFET devices M 6  and M 7 . C P  represents the parasitic capacitance of node  901 . Notice that the dynamic inverter  91  drives one of the two inputs of the NOR gate  92  with its output signal Y I  at node  901 , whereas the other input of the NOR gate is driven at node  902  by the Y CLK  signal described previously in conjunction with  FIG. 8  and exemplified in  FIG. 9 . One of the inputs of the dynamic inverter  91  receives at node  904  the same Y CLK  signal, and the other input receives at node  905  the Y HL  signal previously described in conjunction with  FIG. 8  and exemplified in  FIG. 9 . Node  906  is designated as ground. Note that all NMOSFET devices have their bulk (not shown in  FIG. 10 ) connected to node  907 , and all PMOSFET devices have their bulk (not shown in  FIG. 10 ) connected to node  906 . 
     The operation of the logic controller  90  can now be explained with reference to  FIG. 8 ,  FIG. 9 , and  FIG. 10 . 
     Consideration is given first to the case of Y CLK  being at ground (i.e., binary-high level). As previously explained, this binary level of Y CLK  signals the case of V SC  being less negative than V + , for which the switching NMOSFET M S  should be kept open. Indeed, whenever Y CLK  is at ground, NOR gate  92  keeps Y S  at V SS  (i.e., binary-low level), and therefore M S  remains in cutoff (i.e., open switch state). As to the behavior of the dynamic inverter in the case of Y CLK  being at ground, notice that M 3  keeps the output signal Y I  of the dynamic inverter at the binary-low level V SS  regardless of the binary level of Y HL . Therefore, C P  is kept charged to the negative rail voltage V SS  whenever Y CLK  is at ground. 
     Consideration is given next to the case of Y CLK  making a transition from ground down to V SS  while Y HL  is at V SS . This is the sampling moment when Action-2 of Rule-2 is to be executed. The falling Y CLK  forces M 3  into cutoff and M 1  into conduction, and thus disconnects node  901  from V SS , and connects node  908  to ground. Since M 2  is also conducting due to Y HL  being at V SS , C P  is discharged to ground, i.e., Y I  rises to ground. Now that one of its inputs being raised to ground, the NOR gate  92  keeps its output Y S  at V SS  although its second input receiving Y CLK  is lowered to V SS . Y S  being at V SS , M S  retains its cutoff state (i.e., open switch state). Notice that, even if Y HL  happens to return later to ground (i.e., V S  crossing over V REF ) while Y CLK  is still at V SS  (i.e., V SC  is more negative than V + ), M S  will continue to be in cutoff because C P  cannot be recharged to V SS  before the next rising edge of Y CLK . After the arrival of the next rising edge Y CLK , Y S  is kept at V SS  anyway, as explained in the preceding paragraph. Therefore, M S  remains in cutoff for the entire cycle if V S  is more negative than V REF  at the beginning of the cycle, as mandated by Action-2 of Rule-2. 
     If Y HL  is at the ground level when Y CLK  makes a transition from ground down to V SS , Action-1 of Rule-2 is to be executed. In this case, the falling Y CLK  again forces M 3  into cutoff and M 1  into conduction, and thus disconnects node  901  from V SS , and connects node  908  to ground. But, since Y HL  is at the ground level, M 2  remains in cutoff, and despite the fact that node  908  is connecting the ground, node  901  is left afloat. This enables C P  to retain its charge, and thus to keep Y I  at V SS . Now, the NOR gate  92  with both inputs at V SS , raises Y S  to ground, and thus turns M S  on (i.e., closed switch state). If, subsequently, the falling V S  crosses under V REF , and therefore, Y HL  drops to V SS  before Y CLK  rises to ground, then, M 2  turns on, and together with the conducting M 1 , discharges C P  up to ground. Y I  being raised to ground, the NOR gate  92  lowers Y S  to V SS , and thus forces M S  into cutoff (i.e., open switch state). Since C P  cannot be charged to V SS  before the next rising edge of Y CLK,  M S  remains in cutoff even if Y HL  happens to return to ground any time before Y CLK  rises to ground. If, on the other hand, Y CLK  rises to ground before Y HL  drops to V SS , then, the NOR gate  92  lowers Y S  to V SS , and thus forces M S  into cutoff (i.e., open switch state) at the moment Y CLK  rises to ground.