Abstract:
A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.

Description:
RELATED APPLICATIONS 
     This application claims priority from U.S. Provisional Patent Application No. 61/002,972, filed Nov. 13, 2007, and incorporated herein by this reference. 
    
    
     COPYRIGHT NOTICE 
     © 2007-2008 Elemental Technologies, Inc. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 37 CFR §1.71(d). 
     TECHNICAL FIELD 
     This invention pertains to methods and apparatus for decoding or encoding video data using one or more sequential processors together with a group or groups of parallel general purpose SIMD processors. 
     BACKGROUND OF THE INVENTION 
     Encoding and decoding systems and methods for MPEG and other block-based video bit-stream data are now widely known. The fundamentals are well summarized in U.S. Pat. No. 6,870,883 (“Iwata”), incorporated herein by this reference. Iwata discloses a three-processor system and method for video encoding and decoding, to achieve a modicum of parallelism and improved performance over a strictly sequential solution. the interdependency of bits or blocks of the video frame. It is also difficult to maximize the performance by keeping all processors as busy as possible due to differing requirements of the processors. 
     One property of video is that for any given block of pixels (e.g. macroblock) in the video frame, there is a high correlation to neighboring blocks. Video compression technologies take advantage of this through the use of prediction. When the video is encoded, the encoder predicts block properties based on neighboring blocks and then encodes the difference (residual) from the prediction. The video decoder computes the same prediction and adds the residual to the prediction to decompress the video. Since only residuals to the predictions are sent, the amount of information sent between the encoder and the decoder is compressed. One drawback to having block properties predicted based off neighboring blocks is that if a neighboring block contains an error, for example due to interference during a broadcast, then all subsequent blocks will also contain an error causing an entire frame of video to be corrupted. For this reason, these video compression standards contain a notion of a slice. 
     A “slice” of video data contains a set of blocks that can be decoded without any other neighboring block information (from outside the slice). At each slice, the predictors are reset, trading off compression efficiency for error resilience. The majority of encoded MPEG2 content, for example, uses one slice per line of blocks. If an error is introduced in any given block, the system can recover on the next line of blocks. 
     Two other properties of video that allow it to be compressed are these: high frequency information can be discarded without the human vision system detecting a noticeable change in the results; and, motion tends to be localized to certain areas of the picture. Video compression standards take advantage of these two properties by a method called quantization and motion estimation/motion compensation, respectively. 
     Finally, to further compress the video data, a lossless variable length encoding scheme is used in video compression technologies. These methods may even use a context adaptive algorithm causing further dependency on data previously encoded or decoded in the data stream. 
     Some known solutions utilize multiple sequential processors or arrays of processors connected by a network such as Ethernet or high speed memory interface. These solutions suffer in efficiency from insufficient number of processors, and memory bandwidth/latency in sending data to all the processors. 
     Other proposals for parallelizing video decoding and encoding have been proposed such as that disclosed in U.S. Pat. No. 6,870,883 which describes a system for decoding video using multiple processors. That system requires the computationally expensive ability to transfer data to and from processors at each macroblock. 
     The need remains for improvements in methods and systems for video data processing to improve throughput while maintaining video quality and controlling costs. 
     SUMMARY OF THE INVENTION 
     In general, the present disclosure concerns improvements in video encoding/decoding technology. In one embodiment, improvements can be achieved by using two different processor systems, namely a Sequential Processor Array (“SPA”) and a Parallel Processor Array (“PPA”). The SPA and PPA encode/decode a video stream in a predefined, coordinated manner. In one illustrative system, in a decoder, a sequential processor array is provided comprising at least one general purpose sequential processor and arranged to receive a video data input stream; and a general purpose parallel processor array is provided. A data bus interconnects the sequential processor array and the parallel processor array. A first memory is coupled to the sequential processor array to store SPA program instructions, Macroblock coefficient data and Macroblock metadata produced by the SPA from incoming video data. A second memory is coupled to the parallel processor array and is arranged for storing PPA program instructions and macroblock coefficient data, macroblock metadata, reference frame data and output video frame data. 
     Additional aspects and advantages of this invention will be apparent from the following detailed description of preferred embodiments, which proceeds with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block diagram illustrating a multi-processor video decompression/compression system architecture consistent with the present invention. 
         FIG. 2  is a simplified flow diagram illustrating a method of parallel variable length decode of encoded video data using an array of general purpose sequential processors. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     With the advent of general purpose multi-core processors from Intel or AMD which have either 2, 4 or 8 processors and massively multi-processor systems such as NVIDIA&#39;s G80 GPU which, as of this writing, contains up to 128 SIMD (single instruction, multiple data) processors, a relatively inexpensive commodity desktop PC can provide a massive amount of processing power. What is needed, and is described herein, are methods for utilizing systems that include sequential and parallel processors so as to greatly enhance the speed and efficiency of decoding and decompression of block-based video data. The decompressed video frames can then be displayed on a computer or television screen, or used in further video processing such as image enhancement, scaling, or encoding for re-transmission. 
     Our invention in various embodiments takes advantage of slices and other independent portions of the video to greatly increase the coding speed and efficiency. In one presently preferred embodiment, our methods can be used in a system of the general type illustrated in  FIG. 1 , containing a sequential processor array (“SPA”  101 ) and a Parallel Processor Array (“PPA”  102 ). The SPA contains one or more high performance general purpose sequential processing units that are designed to execute sequential instructions on sequential data. The PPA contains one or more groups of homogeneous general purpose SIMD multiprocessors  107  that are designed to operate on highly parallel problems where many processors can work in parallel. The SPA and PPA each has access to one or more physical RAMs (Random Access Memory)  103  and  104 , respectively, and are connected together by a high speed bi-directional data and communication bus  105 . 
     Each multiprocessor  107  contains one or more SIMD (Single Instruction Multiple Data) processors, and also contains a memory cache (illustrated as RAM but may be other types of cache)  115  allowing fast access and communication between each SIMD processor in the multiprocessor. There is also, in the illustrated embodiment, a random access memory (RAM  104 ) shared by all multiprocessors in the array  102 , that store the video frames, macroblock coefficient data, macroblock metadata, and multiprocessor instructions. There is a PPA sequencer and memory arbiter  106  to automatically and efficiently select processors to execute a set of instructions  114 . Each multiprocessor can process batches of instructions and one batch is executed after the other. The scheduler selects batches of instructions for each multiprocessor. If, and when, a multi-processor is instructed to wait for memory or a synchronization event, the scheduler will swap in new instructions to execute on that processor. 
     Decode Method 
     One aspect of the present invention involves using two methods or processes in parallel to efficiently apply processing resources to decode or encode block-based video data. We use the term “parallel” to refer to processes that generally run concurrently, in a coordinated fashion. We do not use the term to require a strict step by step, or clock by clock parallelism. The following description is for decoding, but it can be applied to encoding in a similar manner as further explained below. 
     The first of the pair of methods we will call Parallel Variable Length Decode or “PVLD.” As the name implies, this method applies parallel processing to the variable-length decoding aspect of video decoding. It decompresses a video frame of a variable length inter-block dependant encoded stream  116 , and produces an independent variable length macroblock coefficient data buffer  110  and a fixed size macroblock metadata buffer  111 . This data, for one frame in a preferred embodiment, is then copied to the PPA&#39;s RAM memory  104  through the high speed communication bus  105 . In an alternative embodiment, a memory address can be sent to the PPA  107 , for example in the case of a single shared RAM device (not shown). 
     The second process of the pair we will call Parallel Block Decode or “PBD.” The PBD process decompresses each macroblock by decoding the run-length compressed coefficient data using the metadata and using stored reference frames  112 . The output of this method is the desired output video frame  113 . As soon as the data is copied to the PPA, the SPA can start on the next frame, thus the first method PVLD in a preferred embodiment is always decompressing one frame ahead of the second method, the PBD. Since both methods are running in parallel and both of these processes make use of many processors (in array  101  and array  102 , respectively, the speed and efficiency of decoding an entire video stream is greatly improved compared to prior solutions. 
     Referring again to  FIG. 1 , the coefficient data buffer ( 110  and  117 ) contains a run length encoded version of the frequency coefficients representing the residual data from the prediction, and the metadata buffer contains other properties of each macroblock that instruct the multiprocessors in the PPA how to decode each macroblock. Buffer  110  contains the coefficient data, or is accumulating that data, for a Frame “n+1” when the PPA buffer  117  is working on decoding the coefficient data from the last (i.e., the next preceding) Frame n. As noted, the SPA starts on the next frame of data as soon as it stores a completed frame of coefficient data in the buffer  117  for the PPA to conduct PBD. In this embodiment, there is no harm if the block decode in the PPA temporarily falls behind, as the next frame data can wait in the buffer. However, it need not wait for a full frame of data to begin processing macroblocks. 
     Processing Slices of Macroblock Data 
     As discussed in the background section, slices can be decoded independently of other slices. Slices also contain blocks that are dependent on other blocks in the slice and are best decoded sequentially; therefore, in a preferred embodiment, each slice is decoded using a sequential processor  108 , but more than one slice can be decoded in parallel using a group of sequential processors  101 . Each sequential processor  108  in the SPA decodes an assigned slice, and outputs the independent coefficients and metadata into another array for use in the second process (PBD). If there are not enough sequential processors for all slices of a frame, slices may be assigned, for example in a round-robin fashion, until all slices are decoded. 
     Slices of data are variable in byte length due to the nature of the variable length encoding as well as the amount of compression due to prediction for each slice, however. To accommodate this aspect, a process is illustrated in  FIG. 2  to pre-process the data in such a way that a frame of video can be decoded in parallel using multiple sequential processors.  201  shows the variable sized slices packed in a buffer. This buffer contains the encoded bits from the video stream with all slices packed together. The data is pre-processed by finding the point in the buffer where each slice begins and the pointers for each slice are stored in an index array shown in  202 . This index array is then read by the each processor in the SPA ( 203 ) to find the location of the slice that each processor is responsible for decoding. Once the set of macroblocks in each SPA processor&#39;s array has been VLC decoded to coefficients and meta data, the resulting (RLE compressed) coefficients and metadata for each block in a slice is stored in an array ( 204  and  205  respectively and  117  and  118  respectively). Another index table is used to tell each processor in the PPA where each macroblock is located in the coefficient buffer ( 204 ). In the case of this invention, the index table is stored at the top of the coefficient buffer for convenience. Each processor in the PPA then reads the address offset for the macroblock data that it is responsible for decoding from this table as shown in ( 117 ). 
     Once all the slices have been decoded, the decompressed slice data is sent to the PPA for the PBD and decoding of the next frame of slices can be started on the SPA. Since each macroblock in the PBD is independent of other macroblocks, many more processors can be applied to decompressing all of the blocks in parallel. 
     Each processor in a multiprocessor communicates through a RAM that is local to the group of processors. Each processor&#39;s function depends on the macroblock decoding phases. 
     In some cases, such as high bit rate video decoding or encoding, some of the sequential decoding or encoding in the PVLD could be offloaded to the PPA. In some embodiments, where this capability is implemented, the decision depends on which phase of the codec is the bottleneck in the system. A methodology for making this determination for load balancing is described in the next section. 
     Load Balancing to Optimize Throughput 
     To properly load balance the system using the PPA and the SPA the system must calculate the theoretical performance (for example, in frames per second) of the different processor load distributions using various inputs and some pre-calibrated constants. The following is a sample calculation. 
     Let: 
     Ns=# of processors for SPA 
     Np=# of processors for PPA 
     Cs=clock rate of one of the processors in either the SPA and PPA (assume all have the same clock rate) 
     Cp=clock rate of one of the processors in the PPA (assume all have the same clock rate) 
     Cts=available clock rate per array of SPA processors=Cs*MIN(Ns, # slices in the video) 
     Ctp=available clock rate per array of PPA processors=Cp*MIN(Np, # slices in the video) 
     B=bits per frame of a video stream (initial value set to avg bitrate/FPS and then continuously refined by analyzing previously processed frames and frame type) 
     P=total pixels in video frame 
     T=transfer rate of high speed bus 
     Ks=SPA processor clocks per bit for a given system found experimentally or by calibration, and may be different depending on I, P or B frames 
     Kp=PPA processor clocks per bit for a given system found experimentally or by calibration, and may be different depending on I, P or B frames 
     Kpp=PPA processor clocks per pixel for a given system found experimentally or by calibration, and may be different depending on I, P, or B frames. 
     First, the theoretical time for VLC decode or encode in the SPA and PPA is calculated using this equation:
 
 Tvs=B*Ks/Cts  
 
The PPA calculation is this equation.
 
 Tvp=B*Kp/Ctp  
 
     The transfer time is calculated by this equation: Tt=B/T for both the more compressed VLC representation, and the Metadata/Coefficient representation of the frame. B changes depending on the VLC representation or the Metadata/Coefficient representation. 
     The pixel processing time is calculated by a new K and a new Ct:
 
 Ctp=Cp *MIN( Np ,# Macroblocks in the frame)
 
 Tpp=P*Kpp/Ctp  
 
     The total FPS is then defined by: 
     1/(Tvs+Tt+MAX(Tpp−Tvs, 0)) when running the PPA and SPA in parallel or; 
     1/(Tvp+Tt+Tpp) when offloading the VLC processing to the PPA. 
     These two values are compared and the proper load balancing is chosen based on the better theoretical performance. 
     A calculation of this type can be run on every frame and variables B, Ks, Kp, and Kpp can be refined based on actual frame processing times vs calculated. B preferably is constantly updated based on historical values and the frame type (such as I, P or B frames). K may also be adjusted based on the historical values of real vs theoretical performance. 
     Tables 1, 2 and 3 Below Show Examples of Sample Results. 
     This example shows the difference of processing the VLC decode using the PPA vs the SPA and why decoding the VLC step on the 16 processor PPA can achieve a higher overall performance than a 4 processor SPA despite each PPA having a much smaller clocks/second value and a longer transfer time per frame. Processing the VLC on the PPA achieves a 74 frames per second overall performance where the SPA achieves a 60 frames per second overall performance. In this case, the system would execute the VLC decode on the PPA instead of the SPA. A new clock/bit measurement and clock/pixel measurement may then be calculated to determine how the next frame will be decoded. 
     
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Stream Properties 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 7.50E+07 
                 bps 
                 average Bits/sec 
               
               
                 30 
                 FPS 
                 Frames per second 
               
               
                 30 
                 Slic# 
                 # slices 
               
               
                 25769803776 
                 T 
                 transfer rate bits/sec 
               
               
                 2.50E+06 
                 Bv 
                 average VLC encoded 
               
               
                   
                   
                 bits/frame 
               
               
                 8.33E+06 
                 Br 
                 average RLE encoded 
               
               
                   
                   
                 bits/frame 
               
               
                 1920 
                 X 
                 Res X 
               
               
                 1080 
                 Y 
                 Res Y 
               
               
                 2073600 
                   
                 Total pixels 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 SPA 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 4 
                 Ns 
                 Number of Processors 
               
               
                   
                 Cs 
                 Clock rate per each 
               
               
                   
                   
                 processor Clocks/second 
               
               
                 2.40E+09 
                 Ks 
                 clock/bit constant 
               
               
                 9.60E+09 
                 Ct 
                 Total clock rate for SPA 
               
               
                 1.61E−02 
                 Tvs 
                 processing time for 1 frame 
               
               
                   
                   
                 in SPA in seconds 
               
               
                 9.70E−05 
                 Ttv 
                 Transfer time VLC 
               
               
                 3.23E−04 
                 Ttr 
                 Transfer time RLE 
               
               
                   
                 FPS if VLC done in SPA 
                 60.71937 FPS 
               
               
                   
               
             
          
         
       
     
                                   TABLE 3               PPA                                16   Ns   Number of Processors       1.50E+09   Cs   Clock rate per each processor               Clocks/second       62   Kp   clock/bit constant       2.40E+10   Ct   Total clock rate for PPA       80   Kx   Clock/pixel constant       6.46E−03   Tvp   VLC processing time for 1 frame in               PPA in seconds       6.91E−03   Txp   Pixel processing time for 1 frame in               PPA in seconds           FPS if VLC   74.25368 FPS           done in PPA                    
Encoding Video Data
 
     The encoding of video is accomplished in a similar way, but in reverse. The video frames are first placed in to the PPA&#39;s RAM memory  104  through a second file decoding process, or a memory copy from a capture device such as a camera. The PPA then executes various pixel processes of an encoder resulting in coefficients. These processes include Intra and Inter prediction, mode selection, motion estimation, motion compensation, DCT and IDCT, Quantization and inverse Quantization. 
     The resulting coefficients and metadata is then placed into an array similar to  204  and  205  for further processing by the SPA. The SPA then takes the coefficient and meta data and encodes using a variable length coding process (VLC) resulting in a video stream.
 
If there are multiple slices in the picture, the SPA can process each slice in parallel resulting in higher overall performance.
 
     It will be obvious to those having skill in the art that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. The scope of the present invention should, therefore, be determined only by the following claims.