Abstract:
A method of differently producing driving clock signals for a shift register of a gate lines driving circuit of a Liquid Crystal Display (LCD), the method includes the steps of determining whether an ambient temperature is greater than or not in comparison to a predetermined threshold temperature; in response to the determining indicating that the ambient temperature is greater, using a first ON voltage and a first charge canceling method; and in response to the determining indicating that the ambient temperature is not greater, using a second ON voltage and a second charge canceling method, where the second ON voltage is different from the first ON voltage and where the second charge canceling method is different from the first charge canceling method. The second charge canceling method may have a shorter duration than that of the first charge canceling method. The second ON voltage may be greater than the first ON voltage.

Description:
PRIORITY STATEMENT 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0128077, filed on Oct. 25, 2013 in the Korean Intellectual Property Office KIPO, the contents of which application are herein incorporated by reference in their entireties. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The present disclosure of invention relates to a DC-to-DC power converter such as usable in a Liquid Crystal Display (LCD) apparatus that uses a DC-DC converter and to a method of driving a display panel using the DC-to-DC converter. More particularly, the present disclosure relates to a DC-DC converter configured for improving display quality across operating temperatures including that at a low temperature as well as at a higher temperature, and to a display apparatus having the DC-DC converter and to a method of driving a display panel using the DC-DC converter. 
         [0004]    2. Description of Related Technology 
         [0005]    Generally, a liquid crystal display (“LCD”) apparatus includes a first substrate including a pixel electrode, a second substrate including a common electrode and a liquid crystal layer disposed between the first and second substrate. An electric field is generated by voltages applied to the pixel electrode and the common electrode. By adjusting an intensity of the electric field, a transmittance of a light passing through the liquid crystal layer may be adjusted so that a desired image may be displayed. 
         [0006]    Generally, a display apparatus includes a display panel and a panel driver. The display panel includes a plurality of gate lines and a plurality of data lines disposed on a respective first substrate. The panel driver includes a gate lines driver providing gate signals to corresponding ones of the gate lines, a data lines driver providing data voltages to corresponding ones of the data lines. The panel driver further includes a timing controller configured for controlling respective driving timings of the gate lines driver and the data lines driver and it further includes a DC-DC converter configured for converting an input power level into appropriate output levels of respective driving voltages used for driving the panel driver. 
         [0007]    When the display apparatus is operated at a relatively low temperature, characteristics of switching elements within the gate lines driver tend to be deteriorated relative to those of higher temperatures so that charging rates for achieving desired pixel voltages are decreased and as a result the desired pixel voltages may not be timely reached. Thus, a display quality of the display panel may be deteriorated when operating at the relatively low temperature. 
         [0008]    It is to be understood that this background of the technology section is intended to provide useful background for understanding the here disclosed technology and as such, the technology background section may include ideas, concepts or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to corresponding invention dates of subject matter disclosed herein. 
       SUMMARY 
       [0009]    Exemplary embodiments in accordance with the present inventive concepts provide a DC-DC converter that produces temperature-adjusted clock signals differently at low ambient temperatures below a predetermined threshold than at higher temperatures to thereby improve a display quality of a display panel. 
         [0010]    Exemplary embodiments of the present inventive concept also provide a display apparatus having the DC-DC converter where the display apparatus includes a gate lines driver circuit having shift register stages driven by the temperature-adjusted clock signals. 
         [0011]    Exemplary embodiments of the present inventive concept also provide a method of driving a display panel using the DC-DC converter. 
         [0012]    In an exemplary embodiment of a DC-DC converter according to the present disclosure of inventive concepts, the DC-DC converter includes a temperature compensating part and a clock generating part. The temperature compensating part generates a first ON voltage at an ambient temperature equal to or greater than a predetermined threshold temperature and a second ON voltage at a temperature less than the threshold temperature based on a generated select signal. The clock generating part generates a first clock signal and a first clock bar signal based on the first ON voltage using a first charge sharing resistor at the temperature equal to or greater than the threshold temperature. The clock generating part generates a different second clock signal and a second clock bar signal based on the second ON voltage using a second charge sharing resistor at the temperature less than the threshold temperature. The first clock bar signal having different timing from the first clock signal. The second clock bar signal having different timing from the second clock signal. 
         [0013]    In an exemplary embodiment, the second ON voltage may be greater than the first ON voltage. 
         [0014]    In an exemplary embodiment, a resistance of the second charge sharing resistor may be greater than a resistance of the first charge sharing resistor. 
         [0015]    In an exemplary embodiment, the select signal may be determined by a combined resistance of a variable resistor varied according to an ambient temperature, a first resistor which is connected to the variable resistor in series and a second resistor which is connected to the variable resistor in parallel. 
         [0016]    In an exemplary embodiment, the variable resistor may be a negative temperature coefficient (“NTC”) thermistor. A resistance of the NTC thermistor may decrease when the ambient temperature increases. 
         [0017]    In an exemplary embodiment, the temperature compensating part may include a first selecting part configured to selectively output the first ON voltage and the second ON voltage according to the select signal. The first selecting part may include a first input terminal to which the first ON voltage is applied, a second input terminal to which the second ON voltage is applied, a selecting terminal to which the select signal is applied and an output terminal configured to output one of the first ON voltage and the second ON voltage. 
         [0018]    In an exemplary embodiment, the clock generating part may include a first generating circuit configured to generate the first clock signal and the second clock signal, a clock terminal connected to the first generating circuit, a second generating circuit configured to the first clock bar signal and the second clock bar signal, a clock bar terminal connected to a first end of the second generating circuit and a second selecting part configured to connect the first charge sharing resistor and the second charge sharing resistor to a second end of the second generating circuit according to the select signal. 
         [0019]    In an exemplary embodiment, the first generating circuit and the second generating circuit may be disposed inside a DC-DC driving chip. The second selecting part may be disposed outside of the DC-DC driving chip. 
         [0020]    In an exemplary embodiment, the first generating circuit, the second generating circuit and the second selecting part may be disposed in a DC-DC driving chip. 
         [0021]    In an exemplary embodiment, the first clock signal may have a level substantially the same as a level of the first clock bar signal at an end portion of a charge sharing duration at the temperature equal to or greater than the threshold temperature. 
         [0022]    In an exemplary embodiment, the second clock signal may have a level different from a level of the second clock bar signal at an end portion of a charge sharing duration at the temperature less than the threshold temperature. 
         [0023]    In an exemplary embodiment of a display apparatus according to the present inventive concept, the display apparatus includes a display panel, a DC-DC converter, a gate driver and a data driver. The display panel displays an image. The DC-DC converter includes a temperature compensating part and a clock generating part. The temperature compensating part generates a first ON voltage at a temperature equal to or greater than a threshold temperature and a second ON voltage at a temperature less than the threshold temperature based on a gate clock signal according to a select signal. The clock generating part generates a first clock signal and a first clock bar signal based on the first ON voltage using a first charge sharing resistor at the temperature equal to or greater than the threshold temperature. The clock generating part generates a second clock signal and a second clock bar signal based on the second ON voltage using a second charge sharing resistor at the temperature less than the threshold temperature. The gate driver generates a gate signal based on the first clock signal, the first clock bar signal, the second clock signal and the second clock bar signal and provides the gate signal to the display panel. The data driver generates a data voltage and to provide the data voltage to the display panel. The first clock bar signal having different timing from the first clock signal. The second clock bar signal having different timing from the second clock signal. 
         [0024]    In an exemplary embodiment, the second ON voltage may be greater than the first ON voltage. 
         [0025]    In an exemplary embodiment, a resistance of the second charge sharing resistor may be greater than a resistance of the first charge sharing resistor. 
         [0026]    In an exemplary embodiment, the select signal may be determined by a combined resistance of a variable resistor varied according to an ambient temperature, a first resistor which is connected to the variable resistor in series and a second resistor which is connected to the variable resistor in parallel. 
         [0027]    In an exemplary embodiment, the temperature compensating part may include a first selecting part configured to selectively output the first ON voltage and the second ON voltage according to the select signal. The first selecting part may include a first input terminal to which the first ON voltage is applied, a second input terminal to which the second ON voltage is applied, a selecting terminal to which the select signal is applied and an output terminal configured to output one of the first ON voltage and the second ON voltage. 
         [0028]    In an exemplary embodiment, the clock generating part may include a first generating circuit configured to generate the first clock signal and the second clock signal, a clock terminal connected to the first generating circuit, a second generating circuit configured to the first clock bar signal and the second clock bar signal, a clock bar terminal connected to a first end of the second generating circuit and a second selecting part configured to connect the first charge sharing resistor and the second charge sharing resistor to a second end of the second generating circuit according to the select signal. 
         [0029]    In an exemplary embodiment of a method of driving a display panel according to the present inventive concept, the method includes generating a first ON voltage at a temperature equal to or greater than a threshold temperature and a second ON voltage at a temperature less than the threshold temperature based on a gate clock signal according to a select signal, generating a first clock signal and a first clock bar signal based on the first ON voltage using a first charge sharing resistor at the temperature equal to or greater than the threshold temperature and generating a second clock signal and a second clock bar signal based on the second ON voltage using a second charge sharing resistor at the temperature less than the threshold temperature, generating a gate signal based on the first clock signal, the first clock bar signal, the second clock signal and the second clock bar signal, generating a data voltage and displaying an image based on the gate signal and the data voltage. The first clock bar signal having different timing from the first clock signal. The second clock bar signal having different timing from the second clock signal. 
         [0030]    In an exemplary embodiment, the second ON voltage may be greater than the first ON voltage. 
         [0031]    In an exemplary embodiment, a resistance of the second charge sharing resistor may be greater than a resistance of the first charge sharing resistor. 
         [0032]    According to the DC-DC converter, the display apparatus having the DC-DC converter and the method of driving the display panel using the DC-DC converter, the DC-DC converter generates a first clock signal using a first charge sharing resistor at a temperature equal to or greater than a threshold temperature and a second clock signal using a second charge sharing resistor at a temperature less that the threshold temperature. Thus, the decrease of the charging rate of the pixel voltage due to deterioration of the characteristics of the switching element of the gate driver may be compensated. Thus, the display quality of the display panel may be improved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0033]    The above and other features and advantages of the present disclosure of inventive concepts will become more apparent by describing in detailed exemplary embodiments in accordance with the same and with reference to the accompanying drawings, in which: 
           [0034]      FIG. 1  is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present disclosure of inventive concepts; 
           [0035]      FIG. 2  is a block diagram illustrating a DC-DC converter of  FIG. 1 ; 
           [0036]      FIG. 3  is an equivalent circuit diagram illustrating a temperature compensating part of the DC-DC converter of  FIG. 2 ; 
           [0037]      FIG. 4  is a temperature versus voltage graph illustrating an operation of the temperature compensating part of the DC-DC converter of  FIG. 3 ; 
           [0038]      FIG. 5  is a voltage versus time waveform diagram illustrating a first clock signal and a second clock signal according to the operation of the temperature compensating part of the DC-DC converter of  FIG. 3 ; 
           [0039]      FIG. 6  is a flowchart illustrating an operation of the DC-DC converter of  FIG. 2 ; 
           [0040]      FIG. 7  is an equivalent circuit diagram illustrating a clock generating part of the DC-DC converter of  FIG. 2 ; 
           [0041]      FIG. 8A  is a waveform diagram illustrating a first clock signal and a first clock bar signal generated by the DC-DC converter of  FIG. 2 ; 
           [0042]      FIG. 8B  is a waveform diagram illustrating a second clock signal and a second clock bar signal generated by the DC-DC converter of  FIG. 2 ; and 
           [0043]      FIG. 9  is a block diagram illustrating a clock generating part of a DC-DC converter according to an exemplary embodiment of the present inventive concepts. 
       
    
    
     DETAILED DESCRIPTION 
       [0044]    Hereinafter, the present disclosure of inventive concepts will be explained in detail with reference to the accompanying drawings. 
         [0045]      FIG. 1  is a block diagram illustrating a display apparatus according to an exemplary embodiment in accordance with the present disclosure of inventive concepts. 
         [0046]    Referring to  FIG. 1 , the display apparatus includes a display panel  100  (e.g., a Liquid Crystal Display (LCD) panel) and a panel driver. The panel driver includes a timing controller  200 , a gate lines driver  300 , a gamma reference voltage generator  400 , a data lines driver  500  and a DC-DC converter  600 . 
         [0047]    The display panel  100  has a display region on which an electronically defined image is displayed and a peripheral region adjacent to but outside the display region. 
         [0048]    The display panel  100  includes a plurality of gate lines GL, a plurality of data lines DL and a plurality of unit pixels connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1 and the data lines DL extend in a second direction D2 crossing the first direction D1. 
         [0049]    Each unit pixel includes a switching element (not shown—for example a thin film transistor), a liquid crystal capacitor (not shown) and a storage capacitor (not shown). The liquid crystal capacitor and the storage capacitor are electrically connected to the switching element. The unit pixels may be disposed in a matrix form in accordance with the crossing gate lines and data lines. 
         [0050]    The timing controller  200  receives input image data signal RGB and an input control signal CONT from an external apparatus (not shown). The input image data signal may include red image data R, green image data G and blue image data B. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal. 
         [0051]    The timing controller  200  generates a first control signal CONT 1 , a third control signal CONT 3 , a fourth control signal CONT 4  and a data signal DATA based on the input image data signal RGB and the input control signal CONT. 
         [0052]    The timing controller  200  generates the first control signal CONT 1  for controlling an operation of the gate lines driver  300  based on the input control signal CONT, and outputs the first control signal CONT 1  to the DC-DC converter  600 . The first control signal CONT 1  may further include a vertical start signal and a gate clock signal. 
         [0053]    The timing controller  200  generates the third control signal CONT 3  for controlling an operation of the data lines driver  500  based on the input control signal CONT, and outputs the third control signal CONT 3  to the data lines driver  500 . The third control signal CONT 3  may include a horizontal start signal and a load signal. 
         [0054]    The timing controller  200  generates the data signal DATA based on the input image data signal RGB. The timing controller  200  outputs the data signal DATA to the data lines driver  500 . 
         [0055]    The timing controller  200  generates the fourth control signal CONT 4  for controlling an operation of the gamma reference voltage generator  400  based on the input control signal CONT, and outputs the fourth control signal CONT 4  to the gamma reference voltage generator  400 . 
         [0056]    The gate lines driver  300  generates gate signals for driving the gate lines GL in response to a second control signal CONT 2  received from the DC-DC converter  600 . The gate lines driver  300  sequentially outputs respective gate signals to respective ones of the gate lines GL. 
         [0057]    The gate lines driver  300  may be directly mounted on the display panel  100 , or may be connected to the display panel  100  as a tape carrier package (TCP) type. Alternatively, the gate lines driver  300  may be monolithically integrated as part of the display panel  100 . 
         [0058]    The gamma reference voltage generator  400  generates a gamma reference voltage VGREF in response to the fourth control signal CONT 4  received from the timing controller  200 . The gamma reference voltage generator  400  provides the gamma reference voltage VGREF to the data lines driver  500 . The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA. 
         [0059]    In an exemplary embodiment, the gamma reference voltage generator  400  may be disposed in the timing controller  200 , or in the data lines driver  500 . 
         [0060]    The data lines driver  500  receives the third control signal CONT 3  and the data signal DATA from the timing controller  200 , and receives the gamma reference voltages VGREF from the gamma reference voltage generator  400 . The data driver  500  converts the data signal DATA into corresponding data voltages of the analog type using the gamma reference voltages VGREF. The data lines driver  500  sequentially outputs the respective analog data voltages to corresponding ones of the data lines DL. 
         [0061]    The data lines driver  500  may be directly mounted on the display panel  100 , or may be connected to the display panel  100  in a TCP type. Alternatively, the data lines driver  500  may be monolithically integrated as part of the display panel  100 . 
         [0062]    The DC-DC converter  600  receives the first control signal CONT 1  from the timing controller  200 . The DC-DC converter  600  generates the second control signal CONT 2  based on the first control signal CONT 1 . The DC-DC converter  600  adjusts a level of the first control signal CONT 1  to generate the second control signal CONT 2 . The DC-DC converter outputs the second control signal CONT 2  to the gate lines driver  300 . 
         [0063]    A structure and an operation of the DC-DC converter  600  are explained referring to  FIGS. 2 to 8B  in detail. 
         [0064]      FIG. 2  is a block diagram illustrating an overview of the DC-DC converter  600  of  FIG. 1 . 
         [0065]    Referring to  FIGS. 1 and 2 , the DC-DC converter  600  receives a gate clock signal CPV from the timing controller  200 . The DC-DC converter  600  responsively generates a clock signal CKV and a corresponding clock bar signal CKVB based on the gate clock signal CPV received from the timing controller  200 . The DC-DC converter  600  outputs voltage levels representing the clock signal CKV and the clock bar signal CKVB to the gate lines driver  300 . 
         [0066]    Although not shown in figures, the DC-DC converter  600  receives a first vertical start signal from the timing controller  200  and adjusts a level of the first vertical start signal to generates a second vertical start signal. The DC-DC converter  600  may output the second vertical start signal to the gate lines driver  300 . 
         [0067]    In the present exemplary embodiment, the outputting of the converted level signals (e.g. the clock signal CKV and the clock bar signal CKVB) generated by the DC-DC converter  600  to the gate lines driver  300  is mainly explained. However, the present disclosure of inventive concepts is not limited thereto. Other converted level signals which are generated by the DC-DC converter  600  may be outputted to the data lines driver  500  and the gamma reference voltage generator  400 . These other converted level signals may be functions of temperature compensation just as are the converted level gate driver signals (e.g. the clock signal CKV and the clock bar signal CKVB) detailed here. 
         [0068]    Hereinafter, the generating of the clock signal CKV and the clock bar signal CKVB by the DC-DC converter  600  based on the gate clock signal CPV is mainly explained. 
         [0069]      FIG. 3  is an equivalent circuit diagram illustrating a temperature compensating part of the DC-DC converter  600  of  FIG. 2 .  FIG. 4  is a graph illustrating an operation of the temperature compensating part of the DC-DC converter  600  of  FIG. 3 .  FIG. 5  is a waveform diagram illustrating a first clock signal and a second clock signal according to the operation of the temperature compensating part of the DC-DC converter  600  of  FIG. 3 . 
         [0070]    Referring to  FIGS. 2 to 5 , the DC-DC converter  600  includes the temperature compensating part generating an ON voltage VON where the latter is used to generate the clock signal CKV and the clock bar signal CKVB. 
         [0071]    When an ambient temperature (as determined by an ambient temperature determining device—not shown) is less than a predetermined threshold temperature (Tamb&lt;Tthresh), the temperature compensating part outputs the VON signal as a generated second ON voltage VHI. When the ambient temperature is equal to or greater than the threshold temperature (Tamb≧Tthresh), an operating mode is determined to be a normal temperature mode and instead a “normal” first ON voltage VNO(rmal) is generated. In other words, when the ambient temperature is less than the threshold temperature, the temperature compensating part generates the boosted, second ON voltage VHI which is different from (greater than) the normal-mode, first ON voltage VNO. When the ambient temperature is less than the threshold temperature, the operating mode is deemed to be the abnormal low temperature mode. 
         [0072]    In the given examples, the second ON voltage VHI is greater than the first ON voltage VNO. 
         [0073]    In  FIG. 3 , the temperature compensating part includes a first selecting part S 1 . The first selecting part S 1  includes a first input terminal to which the first ON voltage VNO is applied, a second input terminal to which the second ON voltage VHI is applied, a selecting terminal to which a select signal SS is applied and an output terminal selectively outputting one of the first ON voltage VNO and the second ON voltage VHI according to the select signal SS. 
         [0074]    For example, the first selecting part S 1  may include an analog signal multiplexer and/or the first selecting part S 1  may include an operational amplifier. 
         [0075]    In one embodiment, the select signal SS is determined by applying a constant current ((A)) to a combined resistance of a variable resistor RTNC varied according to the ambient temperature, a first resistor R 1  which is connected to the variable resistor RTNC in series and a second resistor R 2  which is connected to the variable resistor RTNC in parallel. The select signal SS may be a voltage signal that is a function of the applied constant current signal ((A)) and the temperature-dependent resistance of variable resistor RTNC. 
         [0076]    A first end of the first resistor R 1  is connected to the selecting terminal and a second end of the first resistor R 1  is connected to a first end of the variable resistor RTNC. A second end of the variable resistor RTNC is connected to a ground. A first end of the second resistor R 2  is connected to the first end of the variable resistor RTNC and a second end of the second resistor R 2  is connected to the second end of the variable resistor RTNC. 
         [0077]    For example, the variable resistor RTNC may be a negative temperature coefficient (“NTC”) thermistor. When the ambient temperature TEMP increases, a resistance of the NTC thermistor responsively decreases. 
         [0078]    In  FIG. 3 , Element A connected to the selecting terminal is a reference current source used to select one of the first ON voltage VNO and the second ON voltage VHI. For example, the reference current may be about 50 uA. 
         [0079]    In  FIG. 4 , the utilized ON voltage VON is determined according to the ambient temperature TEMP. For example, when the ambient temperature TEMP is less than a predetermined first (e.g., threshold) temperature T1, the utilized ON voltage VON is the higher, second ON voltage VHI. When the ambient temperature greater than a second temperature T2 (and thus also greater than the predetermined first (e.g., threshold) temperature T1), the utilized ON voltage VON is the lower first ON voltage VNO. 
         [0080]    An interposed variable curve for the utilized ON voltage VON corresponding to the ambient temperature TEMP between the first temperature T1 and the second temperature T2 is defined by a variable resistor RTNC. 
         [0081]    The threshold temperature may be set as any temperature between and inclusive of the first temperature T1 and the second temperature T2. For example, the threshold temperature may be set equal to the first temperature T1. Alternatively, the threshold temperature may be set equal to the second temperature T2. Yet otherwise and as an example, the threshold temperature may be set equal to an average between the first temperature T1 and the second temperature T2. 
         [0082]    In  FIG. 5 , when the ambient temperature is determined to be equal to or greater than the threshold temperature (Tamb≧Tthresh; solid plot line case), and in response, the DC-DC converter  600  generates a first clock signal CKV 1  based on the first ON voltage VNO (a.k.a. Vnormal). When the ambient temperature is less than the threshold temperature (Tamb&lt;Tthresh; dashed plot line case), the DC-DC converter  600  generates a second clock signal CKV 2  based on the second ON voltage VHI (the abnormal level). 
         [0083]    The first clock signal CKV 1  may have a high level of the first ON voltage VNO and a low level of a gate off voltage (Voff, which could be common voltage Vcom). The second clock signal CKV 2  may have a high level of the second ON voltage VHI and a low level of the gate off voltage. The first clock signal CKV 1  and the second clock signal CKV 2  may have the same timing. 
         [0084]    Although not shown in  FIG. 5 , when the ambient temperature is equal to or greater than the threshold temperature, the DC-DC converter  600  may generate a first clock bar signal based on the first ON voltage VNO. The first clock bar signal has a different timing from the first clock signal CKV 1  (for example, 180 degrees out of phase). When the ambient temperature is less than the threshold temperature, the DC-DC converter  600  may generate a second clock bar signal based on the second ON voltage VHI. The second clock bar signal has a different timing from the second clock signal CKV 2 . 
         [0085]    The first clock bar signal may have a high level of the first ON voltage VNO and a low level of a gate off voltage. The second clock bar signal may have a high level of the second ON voltage VHI and a low level of the gate off voltage. The first clock bar signal CKV 1  and the second clock bar signal CKV 2  may have the same timing. 
         [0086]    When the ambient temperature is relatively low, characteristics of the switching elements in the gate lines driver  300  may be deteriorated. Accordingly, relatively higher voltage (VHI) may be required to turn on the switching elements in the gate driver  300  at the low ambient temperature and at speeds comparable to those attained when the ambient temperature is normal and VNO (also denoted here as Vnormal) is used. 
         [0087]    Thus, the DC-DC converter  600  may generate the second clock signal CKV 2  and the second clock bar signal based on the second ON voltage VHI which is greater than the first ON voltage VNO at a temperature less than the threshold temperature. Therefore, the decrease of the charging rate of pixel units of the display panel  100  due to deterioration of the characteristics of the switching elements of the gate lines driver  300  may be compensated for and the pixel units may be charged for lengths of time substantially the same as those used when the ambient temperature is normal even though the ambient temperature is subnormal (Tamb&lt;Tthresh). 
         [0088]      FIG. 6  is a flowchart illustrating an operation of the DC-DC converter  600  of  FIG. 2 .  FIG. 7  is an equivalent circuit diagram illustrating a clock generating part of one embodiment of the DC-DC converter  600  of  FIG. 2  wherein a DC-DC integrated circuit (IC) is used.  FIG. 8A  is a waveform diagram illustrating the first clock signal and the first clock bar signal generated by the DC-DC converter  600  of  FIG. 2 .  FIG. 8B  is a waveform diagram illustrating the second clock signal and the second clock bar signal generated by the DC-DC converter  600  of  FIG. 2 . 
         [0089]    Referring to  FIGS. 2 to 8B , the DC-DC converter  600  includes the clock generating part which generates the clock signal CKV and the clock bar signal CKVB. 
         [0090]    The clock generating part generates the first clock signal CKV 1  and the first clock bar signal CKVB 1  having a timing different from the first clock signal CKV 1  based on the first ON voltage VNO using a first charge sharing resistor RCSN at a temperature equal to or greater than the threshold temperature. The clock generating part generates the second clock signal CKV 2  and the second clock bar signal CKVB 2  having a timing different from the second clock signal CKV 2  based on the second ON voltage VHI using a second charge sharing resistor RCSL at a temperature less than the threshold temperature. In particular, the repetition periods of CKV 1  (solid line plot in  FIG. 8A ) and CKV 2  (solid line plot in  FIG. 8B ) are substantially the same even though the switching rates of CKV 1  ( FIG. 8A ) and CKV 2  ( FIG. 8B ) are not the same. (More specifically, for the illustrated embodiment, CKV 1  ( FIG. 8A ) drops to a mid-level (halfway between Von and Voff) much more rapidly than does CKV 2  ( FIG. 8B ). Also and as seen in the timing diagrams, the repetition periods of CKVB 1  (dashed line plot in  FIG. 8A  for the “bar” version of the clock) and CKVB 2  (dashed line plot in  FIG. 8B ) are substantially the same even though the switching rates of CKVB 1  ( FIG. 8A ) and CKVB 2  ( FIG. 8B ) are not the same. (More specifically, for the illustrated embodiment, CKVB 1  ( FIG. 8A ) drops to a mid-level (halfway between Von and Voff) much more rapidly than does CKVB 2  ( FIG. 8B ). Yet more specifically, the drop of CKV 1  to the mid-level (halfway between Von and Voff) is due to a charge sharing operation (whose circuit is not shown) where the CKV line is shorted to the CKVB line so that their opposed charges cancel each other out. This charge sharing operation is carried out for a longer length of time and/or at a faster rate in the case of  FIG. 8A  than it is in the case of  FIG. 8B . Hence the waveforms are different. 
         [0091]    More specifically and for the embodiment of  FIG. 7 , the DC-DC IC in the clock generating part includes a first generating circuit C 1  generating the first clock signal CKV and a second generating circuit C 2  generating the second clock signal CKVB. The DC-DC IC has a first clock terminal TCKV outputting the first clock signal CKV and a second clock terminal TCKVB outputting the bar clock signal CKVB. The DC-DC integrated circuit further has a third or control terminal TCKVBCS that may be used to determine if the second generating circuit C 2  is generating the normal mode first clock bar signal CKVB 1  or the subnormal temperature and thus higher second clock bar signal CKVB 2 . The second generating circuit C 2  is coupled by way of the control terminal TCKVBCS to a second selecting part S 2  which is further connected to a normal-mode, first charge sharing resistor RCSN and to a low-temperature mode, second charge sharing resistor RCSL, where the second selecting part S 2  determines which will be operatively coupled to the second generating circuit C 2  according to a supplied select signal SS. 
         [0092]    The first generating circuit C 1  generates the first and second clock signals CKV 1  and CKV 2  based on the first and second ON voltages VNO and VHI and the gate off voltage. Although not shown in figures, the first generating circuit C 1  may generate the first and second clock signals CKV 1  and CKV 2  using two switching elements connected in series. 
         [0093]    The second generating circuit C 2  generates the first and second clock bar signals CKVB 1  and CKVB 2  based on the first and second ON voltages VNO and VHI and the gate off voltage. Although not shown in figures, the second generating circuit C 2  may generate the first and second clock bar signals CKVB 1  and CKVB 2  using two switching elements connected in series. 
         [0094]    The second generating circuit C 2  includes a charge sharing circuit (not shown). The clock signal CKV 1  and CKV 2  and the clock bar signal CKVB 1  and CKVB 2  are charge-shared in a push-pull method using a selectively picked one of the charge sharing resistors RCSN and RCSL which are connected between the first generating circuit C 1  and the second generating circuit C 2  via the second selecting part S 2 . 
         [0095]    In other words, in the present exemplary embodiment of  FIG. 7 , the first generating circuit C 1  and the second generating circuit C 2  are monolithically integrally disposed inside a DC-DC driving chip DC-DC IC. The second selecting part S 2  is disposed outside of the DC-DC driving chip DC-DC IC. 
         [0096]    The second selecting part S 2  may be connected to the second generating circuit C 2  through a clock bar charge sharing terminal TCKVBCS. 
         [0097]    The second selecting part S 2  includes an input terminal connected to the clock bar charge sharing terminal TCKVBCS, a first output terminal connected to the first charge sharing resistor RCSN, a second output terminal connected to the second charge sharing resistor RCSL and a selecting terminal to which the select signal SS is applied. 
         [0098]    For example, the second selecting part S 2  may include a multiplexer and/or the second selecting part S 2  may include an operational amplifier. 
         [0099]    The select signal SS is determined by a combined resistance of the variable resistor RTNC varied according to the ambient temperature, the first resistor R 1  which is connected to the variable resistor RTNC in series and the second resistor R 2  which is connected to the variable resistor RTNC in parallel. The select signal SS may be a voltage signal obtained by way of a reference current signal ((A)) as applied to a variable resistance network. 
         [0100]    The select signal SS may be the same as the signal applied to the first selecting part S 1 . 
         [0101]    Hereinafter, an operation of the DC-DC converter  600  is explained in detail referring to  FIG. 6 . 
         [0102]    The temperature compensating part determines if it is operating a low temperature compensating circuit or not according to an internally detected (inside the DC-DC IC) level of the select signal SS (step S 100 ). 
         [0103]    When the ambient temperature is equal to or greater than the threshold temperature, the temperature compensating part does not operate the low temperature compensation and generates the normal first ON voltage VNO as the ON voltage VON. The clock generating part uses the normal temperature charge sharing resistor RCSN according to the select signal SS (step S 200 ). 
         [0104]    When the ambient temperature is less than the threshold temperature, the temperature compensating part operates the low temperature compensation and generates the second ON voltage VHI as the ON voltage VON. The clock generating part uses the low temperature charge sharing resistor RCSL according to the select signal SS (step S 300 ). 
         [0105]    The clock generating part operates in a charge sharing mode to generate the clock signal CKV and the clock bar signal CKVB using one of the normal temperature charge sharing resistor RCSN and the low temperature charge sharing resistor RCSL (step S 400 ). 
         [0106]    For example, the second chare sharing resistor RCSL is greater than the first charge sharing resistor RCSN. For example, the second chare sharing resistor RCSL may have a resistance value that is about ten times that of the first charge sharing resistor RCSN. 
         [0107]    As shown in  FIG. 8A , the DC-DC converter  600  generates the first clock signal CKV 1  and the first clock bar signal CKVB 1  based on the first ON voltage VNO using the first charge sharing resistor RCSN at a temperature equal to or greater than the threshold temperature (normal temperature mode). 
         [0108]    For example, the first clock bar signal CKVB 1  may be an inverted version signal of the first clock signal CKV 1 . 
         [0109]    When the first clock signal CKV 1  decreases from a high level to a low level, the first clock bar signal CKVB 1  increases from the low level to the high level in a charge sharing duration. 
         [0110]    When the first clock signal CKV 1  increases from the low level to the high level, the first clock bar signal CKVB 1  decreases from the high level to the low level in the charge sharing duration. 
         [0111]    Increment of the first clock signal CKV 1  is substantially equal to decrement of the first clock bar signal CKVB 1  in the charge sharing duration. Decrement of the first clock signal CKV 1  is substantially equal to increment of the first clock bar signal CKVB 1  in the charge sharing duration. 
         [0112]    In addition, the first clock signal CKV 1  may have a level substantially the same as a level of the first clock bar signal CKVB 1  at an end portion of the charge sharing duration. 
         [0113]    As shown in  FIG. 8B , the DC-DC converter  600  generates the second clock signal CKV 2  and the second clock bar signal CKVB 2  based on the second ON voltage VHI using the second charge sharing resistor RCSL at a temperature less than the threshold temperature (low temperature mode). 
         [0114]    For example, the second clock bar signal CKVB 2  may be an inverted version signal of the second clock signal CKV 2 . 
         [0115]    The second clock signal CKV 2  may have a periodicity timing substantially the same as that of the first clock signal CKV 1 . The second clock bar signal CKVB 2  may have a timing substantially the same as a timing of the first clock bar signal CKVB 1 . 
         [0116]    A high level of the second clock signal CKV 2  is based on the second ON voltage VHI so that the high level of the second clock signal CKV 2  may be greater than the high level of the first clock signal CKV 1  which is based on the first ON voltage VNO. 
         [0117]    When the second clock signal CKV 2  decreases from a high level to a low level, the second clock bar signal CKVB 2  increases from the low level to the high level in a charge sharing duration. 
         [0118]    When the second clock signal CKV 2  increases from the low level to the high level, the second clock bar signal CKVB 2  decreases from the high level to the low level in the charge sharing duration. 
         [0119]    Increment of the second clock signal CKV 2  is substantially equal to decrement of the second clock bar signal CKVB 2  in the charge sharing duration. Decrement of the second clock signal CKV 2  is substantially equal to increment of the second clock bar signal CKVB 2  in the charge sharing duration. 
         [0120]    In the low temperature mode, the second clock signal CKV 2  may have a level different from a level of the second clock bar signal CKVB 2  at an end portion of the charge sharing duration. 
         [0121]    The increment of the second clock signal CKV 2  is less than the increment of the first clock signal CKV 1  shown in  FIG. 8A  in the charge sharing duration. The decrement of the second clock signal CKV 2  is less than the decrement of the first clock signal CKV 1  shown in  FIG. 8A  in the charge sharing duration. 
         [0122]    Thus, the second clock signal CKV 2  generated in the low temperature mode may maintain the high level longer than does the first clock signal CKV 1  generated in the normal temperature mode. In addition, during an end portion of a gate on duration which highly affects the pixel charging ratio, the second clock signal CKV 2  may maintain the high level relatively longer. 
         [0123]    Thus, a decrease of the charging rate of the pixel electrodes to the desired pixel voltage due to deterioration of the characteristics of the switching elements of the gate lines driver  300  at the low temperature may be compensated for. 
         [0124]    According to the present exemplary embodiment, the DC-DC converter  600  may generate the second clock signal CKV 2  and the second clock bar signal CKVB 2  based on the second ON voltage VHI which is greater than the first ON voltage VNO at the temperature less than the threshold temperature. In addition, the DC-DC converter may generate the second clock signal CKV 2  and the second clock bar signal CKVB 2  using the second charge sharing resistor RCSL having a resistance greater than a resistance of the first charge sharing resistor RCSN. Thus, the decrease of the charging rate of a pixel of the display panel  100  due to deterioration of the characteristics of the switching element of the gate driver  300  may be compensated for. Therefore, the display quality of the display apparatus may be improved even though the ambient temperature is subnormal. 
         [0125]      FIG. 9  is a block diagram illustrating a clock generating part of a DC-DC converter according to another exemplary embodiment in accordance with the present inventive concepts. 
         [0126]    The display apparatus according to the present exemplary embodiment is substantially the same as the display apparatus of the previous exemplary embodiment explained referring to  FIGS. 1 to 8B  except for a position of the second selecting part S 2  being monolithically integrally incorporated inside the DC-DC IC. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment of  FIGS. 1 to 8B  and any repetitive explanation concerning the above elements will be omitted. 
         [0127]    Referring to  FIGS. 1 to 3  and  9 , the display apparatus includes a display panel  100  and a panel driver. The panel driver includes a timing controller  200 , a gate lines driver  300 , a gamma reference voltage generator  400 , a data lines driver  500  and a DC-DC converter  600 . 
         [0128]    The DC-DC converter  600  includes a temperature compensating part generating an ON voltage VON to generate the clock signal CKV and the clock bar signal CKVB. 
         [0129]    When an ambient temperature is equal to or greater than a threshold temperature, the temperature compensating part generates a first ON voltage VNO. When the ambient temperature is equal to or greater than the threshold temperature, an operating mode is a normal temperature mode. When the ambient temperature is less than the threshold temperature, the temperature compensating part generates a second ON voltage VHI which is different from the first ON voltage VNO. When the ambient temperature is less than the threshold temperature, an operating mode is a low temperature mode. 
         [0130]    In  FIG. 3 , the temperature compensating part includes a first selecting part S 1 . The first selecting part S 1  includes a first input terminal to which the first ON voltage VNO is applied, a second input terminal to which the second ON voltage VHI is applied, a selecting terminal to which a select signal SS is applied and an output terminal selectively outputting one of the first ON voltage VNO and the second ON voltage VHI according to the select signal SS. 
         [0131]    The DC-DC converter  600  includes the clock generating part the clock signal CKV and the clock bar signal CKVB. 
         [0132]    The clock generating part generates the first clock signal CKV 1  and the first clock bar signal CKVB 1  having a timing different from the first clock signal CKV 1  based on the first ON voltage VNO using a first charge sharing resistor RCSN at a temperature equal to or greater than the threshold temperature. The clock generating part generates the second clock signal CKV 2  and the second clock bar signal CKVB 2  having a timing different from the second clock signal CKV 2  based on the second ON voltage VHI using a second charge sharing resistor RCSL at a temperature less than the threshold temperature. 
         [0133]    The clock generating part includes a first generating circuit C 1  generating the first clock signal CKV 1  and the second clock signal CKV 2 , a clock terminal TCKV outputting the first clock signal CKV 1  and the second clock signal CKV 2 , a second generating circuit C 2  generating the first clock bar signal CKVB 1  and the second clock bar signal CKVB 2 , a clock bar terminal TCKVB connected to a first end of the second generating circuit C 2  and outputting the first clock bar signal CKVB 1  and the second clock bar signal CKVB 2  and a second selecting part S 2  connecting the first charge sharing resistor RCSN and the second charge sharing resistor RCSL to a second end of the second generating circuit C 2  according to the select signal SS. 
         [0134]    In the present exemplary embodiment, the first generating circuit C 1 , the second generating circuit C 2  and the second selecting part S 2  are monolithically integrally disposed inside a DC-DC driving chip DC-DC IC. Thus a circuit of the DC-DC converter  600  may be simplified. 
         [0135]    According to the present exemplary embodiment, the DC-DC converter  600  may generate the second clock signal CKV 2  and the second clock bar signal CKVB 2  based on the second ON voltage VHI which is greater than the first ON voltage VNO at the temperature less than the threshold temperature. In addition, the DC-DC converter may generate the second clock signal CKV 2  and the second clock bar signal CKVB 2  using the second charge sharing resistor RCSL having a resistance greater than a resistance of the first charge sharing resistor RCSN. Thus, the decrease of the charging rate of a pixel of the display panel  100  due to deterioration of the characteristics of the switching elements of the gate lines driver  300  may be compensated. Therefore, the display quality of the display apparatus may be improved even if ambient temperature is below normal. 
         [0136]    According to the present inventive concepts as explained above, a decrease of the pixel charging ratio at the low temperature mode is compensated for so that the display quality of the display apparatus may be improved. 
         [0137]    The foregoing is illustrative of the present inventive concepts and is not to be construed as limiting thereof. Although a few exemplary embodiments of the present disclosure have been described, those skilled in the art will readily appreciate in light of the foregoing that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure of inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the present teachings. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also functionally equivalent structures.