Abstract:
The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor.

Description:
This is a divisional of application Ser. No. 08/858,670, filed May 19, 1997 now U.S. Pat. No. 5,900,657. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to MOS switches and, more particularly, to a MOS switch that reduces clock feedthrough in a switched capacitor circuit. 
     2. Description of the Related Art 
     A MOS transistor is a device that controls a channel current, which flows from the drain to the source of the transistor, in response to a voltage applied to the gate of the transistor. As a result of this ability to control the channel current, MOS transistors are commonly used as voltage-controlled switches where the transistor provides a very-low resistance current path when turned on, and a very-high resistance current path when turned off. 
     FIGS.  1 A- 1 B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional NMOS transistor  10 . As shown in FIGS.  1 A- 1 B, transistor  10  includes n+ spaced-apart source and drain regions  14  and  16  which are formed in a p-type substrate  12 , and a channel region  18  which is defined between source and drain regions  14  and  16 . In addition, transistor  10  also includes a dielectric layer  20  which is formed over channel region  18 , and a gate  22  which is formed over dielectric layer  20 . 
     In operation, when voltages are applied to source and drain regions  14  and  16  so that the drain-to-source voltage V DS  is greater than zero, and a voltage is applied to gate  22  so that the gate-to-source voltage V GS  is greater than the threshold voltage V T , transistor  10  turns on, thereby allowing a channel current I C  to flow from drain region  16  to source region  14 . 
     On the other hand, when the drain-to-source voltage V DS  is greater than zero,. and a voltage is applied to gate  22  so that the gate-to-source voltage V GS  is equal to or less than the threshold voltage V T , transistor  10  turns off, thereby preventing channel current I C  from flowing from drain  16  to source  14  (except for a leakage current). 
     One of the most common applications for MOS switches, which are used in a wide variety of applications, is in a switched capacitor circuit. FIGS.  2 A- 2 B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional switched capacitor circuit  50 . 
     As shown in FIGS.  2 A- 2 B, circuit  50  includes transistor  10  of FIG. 1 and a capacitor  52  which is connected between source region  14  and ground. In addition, drain region  16  is connected to receive an input signal V IN , while gate  22  is connected to receive a clock signal CLK. 
     In operation, when the drain-to-source voltage V DS  is greater than zero, and the gate-to-source voltage V GS  is greater than the voltage on the source region  14  by the threshold voltage V T , transistor  10  turns on. When transistor  10  turns on, a channel current I C  flows from drain region  16  through source region  14  and charges up capacitor  52  to the voltage of the input signal V IN  (assuming that the time that the clock signal CLK is high is much greater than the time constant defined by the turn-on resistance of transistor  10  and the capacitance of capacitor  52 ). 
     One drawback to the use of transistor  10  in switched capacitor circuit  50 , however, is that the voltage applied to gate  22  via the clock signal CLK is capacitively coupled to source region  14  via a parasitic gate overlap capacitor C 1  which is formed from gate  22 , dielectric layer  20 , and source region  14 , and via a parasitic lateral fringing field capacitor C 2  formed from gate  22 , an insulation layer formed over source region  14 , and source region  14 . 
     This capacitive coupling, known as clock feedthrough, causes a small negative charge to accumulate at the surface of source region  14  below gate  22  (the lower plates of the parasitic capacitors C 1  and C 2 ), and a corresponding small positive charge to accumulate on the top plate of capacitor  52  when the clock voltage on gate  22  begins to rise, but is insufficient to turn on transistor  10  because the voltage on gate  22  is now greater than the voltage on source region  14 . 
     Once the clock signal CLK turns transistor  10  on, capacitor  52 , as noted above, charges up to the voltage of the input signal V IN . Since capacitor  52  charges up to the input voltage V IN , the small positive charge that accumulated on the top plate of capacitor  52  during the preturn-on period presents no problems. 
     The problem, however, comes after transistor  10  turns off. As the clock voltage on gate  22  continues to fall after transistor  10  has turned off, the capacitive coupling causes a small positive charge to accumulate at the surface of source region  14  below gate  22  (the lower plates of the parasitic capacitors C 1  and C 2 ), and a corresponding small negative charge to accumulate on the top plate of capacitor  52  because the voltage on gate  22  is now lower than the voltage on source region  14 . 
     The small negative charge on the top plate of capacitor  52  functions as a negative offset voltage which, in turn, reduces the magnitude of the voltage held by capacitor  52 . As a result, the voltage held by capacitor  52  at the end of the switched cycle erroneously represents the voltage of the input signal V IN  by the small negative offset voltage. 
     One technique for reducing the negative offset voltage is to utilize a switched capacitor circuit with complementary MOS transistors. FIG. 3 shows a schematic diagram that illustrates a conventional switched capacitor circuit  70  that utilizes complementary MOS transistors. 
     As shown in FIG. 3, circuit  70  includes transistor  10  and capacitor  52  of FIGS. 2A and 2B, and a PMOS transistor  72 . As shown, PMOS transistor  72  has a source  74  which is connected to drain  16  of transistor  10 , a drain  76  which is connected to source  14  of transistor  10 , and a gate  78  connected to receive an inverted clock signal /CLK. 
     In operation, when the clock signal CLK is high and the inverted clock signal /CLK is low, both transistors  10  and  72  are on. After transistors  10  and  72  turn off, the capacitive coupling of NMOS transistor  10  causes a small negative charge to accumulate on the top plate of capacitor  52 , while PMOS transistor  72  causes of small positive charge to accumulate on the top plate of capacitor  52 . 
     As a result, the negative charge that is injected onto the top plate of capacitor  52  by transistor  10  is theoretically cancelled out by the positive charge that is injected onto the top plate of capacitor  52  by transistor  72 . 
     In actual practice, however, circuit  70  fails to completely remove the negative charge from capacitor  52  because the feedthrough parasitic capacitances of NMOS transistor  10  are typically not the same as the feedthrough parasitic capacitances of PMOS transistor  72 . 
     In addition, the turn-on delays of NMOS transistor  10  and PMOS transistor  72  are not the same. As a result, the channel conductances of transistors  10  and  72  will typically not track each other during turn on and turn off. Thus, there is a need for a MOS switch that reduces clock feedthrough in a switched capacitor circuit. 
     SUMMARY OF THE INVENTION 
     Conventional MOS-based switched capacitor circuits suffer from the accumulation of a small positive charge on the source of the MOS transistor which occurs after the transistor has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor. 
     This small positive charge, known as clock feedthrough, also causes a small negative charge to accumulate on the capacitor which, in turn, prevents another device from accurately reading the voltage stored on the capacitor. In the present invention, clock feedthrough is reduced by utilizing a split-gate transistor, and by continuously biasing one of the gates. 
     A switched capacitor circuit in accordance with the present invention, which is formed in a semiconductor substrate, includes a transistor that has spaced-apart source and drain regions formed in the substrate, and a channel region which is defined between the source and drain regions. The channel region, in turn, has first, second, and third portions. 
     The transistor of the circuit also includes a layer of first dielectric material which is formed over the channel region, a first gate which is formed on the layer of first dielectric material over the first portion of the channel region, and a layer of second dielectric material which is formed over the first gate. Further, a second gate is formed on the layers of first and second dielectric materials over the second and third portions of the channel region and a portion of the first gate. 
     In addition to the transistor, the switched capacitor circuit also includes a capacitor which is connected to the source region and ground, or to the source region and another node. 
     In operation, the second gate is continuously biased with a voltage, while a control signal is applied to the first gate where the control signal switches the transistor on and off. 
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a cross-sectional diagram illustrating a conventional NMOS transistor  10 . 
     FIG. 1B is a schematic diagram illustrating transistor  10  of FIG.  1 A. 
     FIG. 2A is a cross-sectional diagram illustrating a conventional switched capacitor circuit  50 . 
     FIG. 2B is a schematic diagram illustrating switched capacitor circuit  50  of FIG.  2 A. 
     FIG. 3 is a schematic diagram illustrating a conventional switched capacitor circuit  70  that utilizes complementary MOS transistors. 
     FIG. 4A is a cross-sectional diagram illustrating a switched capacitor circuit  100  in accordance with the present invention. 
     FIG. 4B is a schematic diagram illustrating circuit  100  of FIG.  4 A. 
     FIG. 5 is a schematic diagram illustrating switched capacitor circuit  100  as part of a sample and hold circuit  200  in accordance with the present invention. 
     FIG. 6 is a schematic diagram illustrating transistor  110  as part of an integrator circuit  300  in accordance with the present invention. 
     FIG. 7 is a schematic diagram illustrating a switched capacitor circuit  400  that utilizes complementary MOS transistors in accordance with the present invention. 
     FIG. 8A is a cross-sectional diagram illustrating a switched capacitor circuit  500  in accordance with an alternative embodiment of the present invention. 
     FIG. 8B is a schematic diagram illustrating circuit  500  of FIG.  8 A. 
     FIG. 9 is a schematic diagram illustrating a switched-capacitor amplifier circuit  600  that utilizes transistors  110  and  510  in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIGS.  4 A- 4 B show cross-sectional and schematic diagrams, respectively, that illustrate a switched capacitor circuit  100  in accordance with the present invention. As described in greater detail below, circuit  100  reduces clock feedthrough by utilizing a split-gate MOS transistor where one of the gates is continuously dc biased. 
     As shown in FIGS.  4 A- 4 B, circuit  100  includes a split-gate transistor  110  that has n+spaced-apart source and drain regions  114  and  116  which are formed in a p-type substrate  112 , and a channel region  118  which is defined between source and drain regions  114  and  116 . Channel region  118 , in turn, includes a first portion  118 A, a second portion  118 B, and a third portion  118 C. 
     In addition, transistor  110  also includes a lower dielectric layer  120  which is formed over channel region  118 , a first gate  122  which is formed on dielectric layer  120  over the first portion  118 A of channel region  118 , and an upper dielectric layer  124  which is formed on the top and sidewall surfaces of first gate  122 . 
     Further, a second gate  126 , which has a lower level  126 A, an upper level  126 B, and an intermediate level  126 C connected to lower and upper levels  126 A and  126 B, is formed on dielectric layer  120  and a portion of dielectric layer  124  so that the lower level  126 A is formed over the second portion  118 B of channel region  118 , and the upper level  126 B is formed over the third portion  118 C of channel region  118  and a portion of gate  122 . 
     As further shown in FIGS. 4A and 4B, switched capacitor circuit  100  also includes a capacitor  130  which is connected between source region  114  and ground. 
     Since transistor  110  is a split-gate transistor, the channel length of transistor  110  is approximately twice the length of transistor  10  of FIGS.  2 A- 2 B. In addition, to maintain the speed of transistor  110 , the width must be formed to be approximately twice the size of the width of transistor  10 . If slower speeds are acceptable, smaller widths may be used. 
     In operation, drain region  116  is connected to receive an input signal V IN , first gate  122  is connected to receive a clock signal CLK, and second gate  126  is continuously biased by a positive dc voltage source, such as the supply voltage Vcc, which, in turn, causes the surface of the second and third portions  118 B and  118 C of channel region  118  to invert. 
     As shown in FIG. 4A, the surface of the second portion  118 B, which is under the lower level  126 A of second gate  126 , is strongly inverted, while the surface of the third portion  118 C, which is under the upper level  126 B of second gate  126 , is weakly inverted due to the larger separation distance between upper level  126 B and the surface of channel region  118 . 
     When the voltage of the input signal V IN  is greater than the voltage on source region  114 , and the voltage of the clock signal CLK is greater than the voltage on source region  114  by the threshold voltage V T , transistor  110  turns on. 
     When transistor  110  turns on, a channel current I C  flows from drain region  116  through source region  114  and charges up capacitor  130  to the voltage of the input signal V IN  (assuming that the time that the clock signal CLK is high is much greater than the time constant defined by the turn-on resistance of transistor  110  and the capacitance of capacitor  130 ). 
     When the drain-to-source voltage V DS  is greater than zero, and the gate-to-source voltage V GS  falls below the threshold voltage V T , transistor  110  turns off. In the present invention, the time required for the clock signal CLK to fall from a logic high to a low must be long compared to the minimum time required to turn off transistor  110  which, for scaled CMOS, is approximately 1 nS. 
     As the voltage on first gate  122  continues to fall after transistor  110  has turned off, a very small positive charge accumulates at the surface of the third portion  118 C of channel region  118  due to the capacitance of a parasitic capacitor C P  formed from gate  122 , second dielectric layer  124 , and the weakly inverted third portion  118 C of channel region  118 , while a corresponding very small negative charge accumulates on the top plate of capacitor  130 . 
     Thus, transistor  110  of the present invention eliminates the capacitance associated with the gate overlap parasitic capacitor C 1  of FIGS.  2 A- 2 B, and reduces the capacitance associated with the lateral fringing field parasitic capacitor C 2  of FIGS.  2 A- 2 B since the bottom plate of parasitic capacitor C P  is located in the weakly inverted region of the third portion  118 C of channel region  118  rather than source region  14  as is the case with the lateral fringing field parasitic capacitor C 2  of FIGS.  2 A- 2 B. 
     The reduced clock feedthrough provided by transistor  110  can be used in a variety of circuits. FIG. 5 shows a schematic diagram that illustrates transistor  110  as part of a sample and hold circuit  200  in accordance with the present invention. 
     As shown in FIG. 5, circuit  200  includes transistor  110  and capacitor  130  of FIGS. 4A and 4B, and an operational amplifier  210  having a positive input connected to source region  114 , and a negative input connected to the output of amplifier  210 . 
     In addition, switched capacitor circuits are not limited to applications where the capacitor is connected to ground. FIG. 6 shows a schematic diagram that illustrates transistor  110  as part of an integrator circuit  300  in accordance with the present invention. 
     As shown in FIG. 6, circuit  300  includes transistor  110  of FIGS. 4A and 4B, an operational amplifier  310  that has a positive input connected to ground and a negative input connected to source region  114 , and a capacitor  320  which is connected between the negative input and the output of amplifier  310 . In addition, drain  116  is connected to a current source I IN  rather than the voltage source V IN . 
     Further, as with circuit  70  of FIG. 3, circuit  100  can be formed to use complementary MOS transistors. FIG. 7 shows a schematic diagram that illustrates a switched capacitor circuit  400  that utilizes complementary MOS transistors in accordance with the present invention. 
     As shown in FIG. 7, circuit  400  includes transistor  110  and capacitor  130  of FIGS. 4A and 4B, and a PMOS split-gate transistor  410 . As shown, PMOS transistor  410  has a source  412  which is connected to drain  116  of transistor  110 , a drain  414  which is connected to source  114  of transistor  10 , a first gate  416  which is connected to receive an inverted clock signal /CLK, and a second gate  418  which is connected to ground or a negative voltage. 
     FIGS.  8 A- 8 B show cross-sectional and schematic diagrams, respectively, that illustrate a switched capacitor circuit  500  in accordance with an alternative embodiment of the present invention. 
     As shown in FIGS.  8 A- 8 B, circuit  500  includes a double split-gate transistor  510 , and a pair of matched capacitors  520  and  530 . Transistor  510  differs from transistor  110  in that transistor  510  includes a channel region  118  that, in addition to first, second, and third portions  118 A,  118 B, and  118 C, also includes a fourth portion  118 D and a fifth portion  118 E. 
     In addition, transistor  510  also includes a third gate  540  that has a lower level  540 A, an upper level  540 B, and an intermediate level  540 C connected to lower and upper levels  540 A and  540 B. Third gate  540  is formed on dielectric layer  120  and a portion of dielectric layer  124  so that the lower level  540 A is formed over the fourth portion  118 D of channel region  118 , and the upper level  540 B is formed over the fifth portion  118 E of channel region  118  and a portion of gate  122 . Further, the top plate of capacitor  520  is connected to source region  114 , while the top plate of capacitor  530  is connected to drain region  116 . 
     In operation, first gate  122  is connected to receive a clock signal CLK, second gate  126  is continuously biased by a positive dc voltage source Vcc, and third gate  540  is continuously biased by the positive dc voltage source Vcc. The positive bias voltages applied to second and third gates  126  and  540  cause the surfaces of the second, third, fourth, and fifth portions  118 B,  118 C,  118 D, and  118 E of channel region  118  to invert. 
     As shown in FIG. 8A, the surfaces of the second and fourth portions  118 B and  118 D are strongly inverted, while the surfaces of the third and fifth portions  118 C and  118 E are weakly inverted due to the larger separation distances between upper levels  126 B and  540 B and the surface of channel region  118 . 
     When the voltage on capacitor  530  is greater than the voltage on source region  114 , and the voltage of the clock signal CLK is greater than the voltage on source region  114  by the threshold voltage VT, transistor  510  turns on. 
     When transistor  510  turns on, a channel current I C  flows from drain region  116  through source region  114  and charges up capacitor  520  to one-half the voltage on capacitor  530  (assuming that the time that the clock signal CLK is high is much greater than the time constant defined by the turn-on resistance of transistor  510  and the capacitance of capacitor  520 ). 
     When the voltage of the clock signal CLK is less than the voltage on source region  114  by the threshold voltage V T , transistor  510  turns off. In the present invention, the time required for the clock signal CLK to fall from a logic high to a low must be long compared to the minimum time required to turn off transistor  510  which, for scaled CMOS, is approximately 1 nS. 
     As the voltage on first gate  122  continues to fall after transistor  510  has turned off, a very small positive charge accumulates at the surface of the third portion  118 C of channel region  118 , and at the surface of fifth portion  118 E due to the capacitance of parasitic capacitors C P1  and C P2  formed from gate  122 , second dielectric layer  124 , and the weakly inverted third and fifth portions  118 C and  118 E of channel region  118 . At the same time, a corresponding very small negative charge accumulates on the top plates of capacitors  520  and  530 . 
     Thus, transistor  510  eliminates the capacitances associated with the source and drain gate overlaps, and reduces the capacitances associated with the source and drain lateral fringing fields since the bottom plates of the parasitic capacitors C P1  and C P2  are located in the weakly inverted third and fifth portions  118 C and  118 E of channel region  118 . 
     The reduced clock feedthrough provided by transistors  110  and  510  can be used together in a variety of circuits. FIG. 9 shows a schematic diagram that illustrates a switched-capacitor amplifier circuit  600  that utilizes transistors  110  and  510  in accordance with the present invention. 
     As shown in FIG. 9, circuit  600  includes a first split-gate transistor  110 A which is connected between ground and an input node N IN , and a second split-gate transistor  110 B which is connected between ground and an intermediate node N M . 
     In addition, circuit  600  also includes a first capacitor C 1  which is connected between the input node N IN  and the intermediate node N M , and a second capacitor C 2 , which is smaller than capacitor C 1 , which is connected between the intermediate node N M  and an output node N OUT . 
     Further, circuit  600  additionally includes a double split-gate transistor  510 A which is connected between the intermediate node N M  and the output node N OUT , and an operational amplifier  610  which has a negative input connected to the intermediate node N M , an output connected to the output node N OUT , and a positive input connected to ground. 
     In operation, when transistor  110 A is turned off, transistors  110 B and  510 A are turned on. Under these conditions, the intermediate and output nodes N M  and N OUT  are pulled to ground which, in turn, places an input voltage V IN  across capacitor C 1 . 
     Next, transistors  110 B and  510 A are turned off, followed by the turn on of transistor  110 A. Under these conditions, the voltage on the intermediate node N M  tries to move towards −V IN . This causes the output of operational amplifier  610  to go high which, in turn, places the voltage V IN  across capacitor C 2 . As a result, an output voltage V OUT  at the output node N OUT  is defined by the equation V OUT =V IN (C 1 /C 2 ). 
     It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.