Abstract:
A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

Description:
[0001]     A semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof.  
       CROSS-REFERENCE TO RELATED APPLICATION  
       [0002]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-314627, filed Oct. 29, 2002, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0003]     1. Field of the Invention  
         [0004]     This present invention relates to a semiconductor memory device and a manufacturing method thereof, for example, a nonvolatile semiconductor memory device and its manufacturing method that are suitable for high integrality.  
         [0005]     2. Description of the Related Art  
         [0006]     A top view of a conventional NOR type non volatile semiconductor memory device is shown in  FIG. 6 . As shown in  FIG. 6 , a plurality of element region (ER) are arranged in a horizontal direction of the  FIG. 6 . Each of the element regions is electrically separated from each other by element isolation regions STI (Shallow Trench Isolation). A plurality of word lines WL 1  portions of which are used as gate electrodes are arranged in a vertical direction of  FIG. 6  so as to intersect each of the element regions.  
         [0007]     Drain contacts  102   a  are arranged between two word lines WL 1  and connects between a drain region formed on a upper surface of the semiconductor substrate  100  and a bit line  115 . The drain contact  102   a  is used in common at memory cells that are arranged at both sides of the drain contact  102   a.    
         [0008]     A source line  103  is arranged in parallel to the word line WL 1  at an opposite side where the drain contacts  102   a  are not formed. The source line  103  is connected to source regions that are formed on an upper surface of the semiconductor substrate  100 . A source contact  102   b  is formed on the source line  103 . The source contact  102   b  is connected between the source line  103  and another line (not shown) that is formed in a same layer as the bit line  115 .  
         [0009]      FIGS. 4 and 5  show cross sectional views of the A-A and the B-B shown in  FIG. 6  respectively. As shown in  FIG. 5 , a plurality of element isolation regions (STI) are formed on an upper surface of the semiconductor substrate  100 , thereby forming a plurality of element regions each of which is arranged between the two element isolation regions. A word line WL 1  is formed so as to intersect each of the element regions.  
         [0010]     As shown in  FIGS. 4 and 5 , the word line WL 1  is formed on a silicon oxide layer  101  (a first gate insulating film) that is formed on the semiconductor substrate  100 . The word line WL 1  also includes a poly crystalline silicon layer  104  that is used as a first floating gate, a poly crystalline silicon layer  105  that is used as a second floating gate, an ONO layer  106  that is used as a second gate insulating film, a control gate electrode comprised of a poly crystalline silicon layer  107  and a tungsten silicon layer  108  (WSi), and a TEOS layer  109  that was used as a mask layer to form a gate electrode.  
         [0011]     A silicon nitride layer  110  is formed on the side surface of the word line WL 1 . A silicon nitride layer  111  is formed to cover the silicon nitride layer  110 . Silicon oxide layers  112  and  131  are formed to fulfill between gate electrodes covered by the silicon nitride layer  111 . And then, portions of the silicon oxide layers  112  and  131  are removed and flatted by using a CMP method.  
         [0012]     Conventionally, drain contacts  102   a  and source line  103  are formed at different manufacturing steps. First, the source line  103  is formed, and then the drain contacts  102   a  are formed. Details of the manufacturing step are as follows.  
         [0013]     Portions of a silicon oxide layer  101 , a silicon nitride layer  111 , silicon oxide layers  112  and  131  are removed to a direction vertical to the element region and the element isolation region, and parallel to the word line WL 1  by using a RIE method (Reactive Ion Etching), thereby forming a contact hole to reach source regions that are formed on an upper surface of the semiconductor substrate  100 . And the, a metal layer  114   b , for instance, tungsten layer W is formed in the contact hole, thereby forming a source line  103 .  
         [0014]     After that, a silicon oxide layer  113  that is used as an interlayer insulating layer is formed and flatted by using a CMP (Chemical Mechanical Polishing) method. At positions where the source line  103  is not formed, portions of a silicon oxide layer  101 , a silicon nitride layer  111 , silicon oxide layers  112 ,  131 , and  113  are removed so as to expose upper surfaces of the silicon substrate  100  by using a RIE method, thereby forming contact holes. A metal layer  114   a , for instance, tungsten W is then formed in the contact hole, thereby forming drain contacts  102   a . After that, portion of the silicon oxide layer  112  is removed so as to expose an upper surface of the source line  103  by using a RIE method, thereby forming a contact hole. A metal layer  116 , for instance, tungsten W is then formed in the contact hole, thereby forming a source contact  102   b  that electrically connects between the source line  103  and line layer (not shown).  
         [0015]     It is noted that a conventional semiconductor memory devices with a source line structure are shown in following materials. IEDM98-975-978 (Novel 0.44 μm 2  Ti-Salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded Application), Japanese patent laid open Hei10-326896, Hei6-334156, Hei7-74325, Hei11-265947, 2002-76147, Hei9-129854, and 2001-68571.  
         [0016]     The conventional semiconductor memory device has a following problem. In the conventional semiconductor memory device, the drain contact  102   a  is formed after the source line  103  and the silicon oxide layer  113  are formed. Therefore, it is necessary to form a contact hole with a depth that is total thickness of the source line  103  and the silicon oxide layer  113 , and fulfill the metal layer  114   a  in the contact hole. In this result, an aspect ratio of the contact hole is higher and it is difficult to fulfill the metal layer  114   a  in the contact hole, thereby resulting in occurrence of voids and a poor conduction.  
         [0017]     It is necessary to use different photo resist masks when a RIE method is achieved in order to form the source line  103  and the drain contact  102   a . Furthermore, it is necessary to form a contact hole of the source contact  102   b  so as to connect between the source line  103  and a conductive line. In this result, the source contact  102   b  may be deviated from the source line  103 , thereby resulting in a poor conduction.  
       SUMMARY OF INVENTION  
       [0018]     A first aspect of the present invention is providing a semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.  
         [0019]     A second aspect of the present invention is providing a semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layer; an insulating film formed above side and top surfaces of the gate electrode of the semiconductor memory device; a first interlayer insulating layer formed between the gate electrode of the semiconductor memory device; a first contact layer formed in the first interlayer insulating layer and connected to the diffusion layer; a second interlayer insulting layer formed on the first inter layer insulating layer; a second contact layer formed in the second interlayer insulating layer and connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.  
         [0020]     A third aspect of the present invention is providing a method of manufacturing a semiconductor memory device having a gate electrode and a diffusion layer, comprising forming a plurality of memory cells each of which including the gate electrode and the diffusion layer; forming a first interlayer insulating film among the gate electrodes of the plurality of the memory cells; forming a first contact hole and a second contact hole, the first contact hole reaches one of the diffusion layers of the plurality of the memory cells and the second contact hole reaches at least two of the diffusion layers of the plurality of the memory cells; forming a first conductive layer in the first contact hole and a second conductive layer in the second contact hole; forming a second interlayer insulating film on the first interlayer insulating film; forming a third contact hole in the second interlayer insulating film; forming a third conductive layer in the third contact hole, the third conductive layer connected to the first conductive layer; and forming a bit line connected to the third conductive layer.  
         [0021]     A fourth aspect of the present invention is providing a method of manufacturing a semiconductor memory device having a gate electrode and a diffusion layer, comprising forming a plurality of memory cells each of which including the gate electrode and the diffusion layer; forming a first interlayer insulating film among the gate electrodes of the plurality of the memory cells; removing portions of the first interlayer insulating film and forming a first contact hole and a second contact hole, the first contact hole reaches one of the diffusion layers of the plurality of the memory cells and the second contact hole reaches at least two of the diffusion layers of the plurality of the memory cells; forming a first conductive layer in the first contact hole and a second conductive layer in the second contact hole; forming a second interlayer insulating film on the first interlayer insulating film, the first conductive layer, and the second conductive layer; removing a portion of the second interlayer insulting film and forming a third contact hole; forming a third conductive layer in the third contact hole, the third conductive layer connected to the first conductive layer; and forming a bit line connected to the third conductive layer.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIG. 1  shows a C-C cross sectional view of a non-volatile memory device associated with a first embodiment of the present invention shown in  FIG. 3 .  
         [0023]      FIG. 2  shows a D-D cross sectional view of the non-volatile memory device associated with the first embodiment of the present invention shown in  FIG. 3 .  
         [0024]      FIG. 3  shows a top view of the non-volatile memory device associated with the first embodiment of the present invention.  
         [0025]      FIG. 4  shows a manufacturing step of the non-volatile memory device associated with a first embodiment of the present invention.  
         [0026]      FIG. 5  shows a manufacturing step of the non-volatile memory device associated with the first embodiment of the present invention.  
         [0027]      FIG. 6  shows a A-A cross sectional view of a conventional non-volatile memory device shown in  FIG. 8 .  
         [0028]      FIG. 7  shows a A-A cross sectional view of a conventional non-volatile memory device shown in  FIG. 8 .  
         [0029]      FIG. 8  shows a top view of a conventional non-volatile memory device.  
         [0030]      FIG. 9  shows a diagram of a memory card in which a semiconductor memory device is arranged.  
         [0031]      FIG. 10  shows a diagram of a memory card in which a semiconductor memory device and a controller are arranged.  
         [0032]      FIG. 11  shows a diagram of a card holder to which a memory card is inserted.  
         [0033]      FIG. 12  shows a diagram of a connecting apparatus, a board, and a connecting wire.  
         [0034]      FIG. 13  shows a diagram of a PC, a connecting apparatus, and a connecting wire.  
         [0035]      FIG. 14  shows a diagram of an IC chip including a semiconductor memory device, and an IC card on which the IC card is allocated.  
         [0036]      FIG. 15  shows a schematic diagram of an IC card and an IC chip. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0037]     Hereinafter, we will explain about an embodiment of the present invention with reference to drawings, specifically NOR type non-volatile memory device.  
       First Embodiment  
       [0038]     A top view of a first embodiment of the present invention is shown in  FIG. 3 . A plurality of element regions are arranged in a parallel direction in  FIG. 3 . Each of the element regions is electrically separated from each other by an element isolation region. A plurality of word lines WL 2  are arranged in a vertical direction in  FIG. 3  so as to intersect each of the element regions.  
         [0039]     A C-C cross sectional view in  FIG. 3  is shown in  FIG. 1  and a D-D cross sectional view in  FIG. 3  is shown in  FIG. 2 . As shown in  FIGS. 1 and 2 , a drain contact  202   a  that connects between a bit line  215  and a drain region formed on an upper surface of a semiconductor substrate  200  is formed. The drain contact  202   a  is used in common at memory cells that are arranged at both sides of the drain contact  202   a . It is noted that the bit line  215  may be comprised of, for instance, one of a barrier metal Ti and a barrier metal TiN, a metal layer, and one of a barrier metal Ti and a barrier metal TiN.  
         [0040]     A source line  203  that is parallel to the word lines WL 2  is arranged and connected to source regions  301  that are formed on upper surfaces of the semiconductor substrate  200 . A source contact  202   b  is formed on the source line  203  and connects between a conductive line (not shown) and the source line  203 .  
         [0041]     As shown in  FIG. 2 , element isolation regions STI are formed on the upper surface of the semiconductor substrate  200 , thereby resulting in forming element regions ER each of which is electrically isolated by the element isolation regions STI. The word lines WL 2  are formed above the element regions ER so as to intersect the element regions ER.  
         [0042]     As shown in  FIGS. 1 and 2 , the word line WL 2  is formed on a silicon oxide layer  201  (a first gate insulating film) that is formed on the semiconductor substrate  200 . The word line WL 2  also includes a poly crystalline silicon layer  204  that is used as a first floating gate, a poly crystalline silicon layer  205  that is used as a second floating gate, an ONO layer  206  that is used as a second gate insulating film, a control gate electrode comprised of a poly crystalline silicon layer  207  and a tungsten silicon layer  208  (WSi), and a TEOS layer  209  that was used as a mask layer to form a gate electrode.  
         [0043]     Manufacturing steps will be explain with reference to  FIGS. 4 and 5 . As shown in  FIG. 4 , the silicon oxide layer  201  is formed on the semiconductor substrate  200 . The poly crystalline silicon layer  204 , a silicon nitride layer (not shown), and a silicon oxide layer (not shown) are formed on the silicon oxide layer  204 . A resist layer is then formed on the silicon oxide layer (not shown) and is processed into a pattern of a gate electrode by using a photolithography technique. Portions of the silicon nitride layer (not shown) and the silicon oxide layer (not shown) are removed by using a RIE method and the patterned photo resist layer as a mask. And then he patterned resist layer is removed. After that, portion of the poly crystalline silicon layer  204  is patterned by using a RIE method and the patterned silicon oxide layer (not shown).  
         [0044]     Portions of the silicon oxide layer  201  and the silicon substrate  200  are removed by using a RIE method and the patterned poly crystalline silicon layer  204  as a mask, thereby forming trench grooves of STI (Shallow Trench Isolation) in an upper surface of the silicon substrate  200 . After that, a silicon oxide layer (not shown) is formed on the upper surface of the silicon substrate  200  and a inner wall of the trench grooves of the STI by using a thermal oxide method.  
         [0045]     A silicon oxide layer (not shown) is formed in the trench grooves of the STI so as to fulfill the trench grooves of the STI by using a HDP (High Density Plasma) method. The silicon oxide layer (not shown) is removed and flattened so as to expose an upper surface of the poly crystalline silicon  204  by using a CMP (Chemical Mechanical Polish) method. The silicon nitride layer (not shown) that is formed on the silicon oxide layer (not shown) is then removed by using a phosphorous acid process. A poly crystalline silicon  205  to which phosphorus (P) is doped is formed by using a low pressure CVD method and is patterned into gate electrodes by using a RIE method.  
         [0046]     An ONO layer  206 , a P doped poly crystalline silicon  207 , a WSi layer  208 , and a silicon oxide layer  209  are formed by using a low pressure CVD method. A patterned photo resist layer (not shown) is formed on the silicon oxide layer  209  by using a photolithography technique. Portions of he silicon oxide layer  209  are removed by using a RIE method and the patterned photo resist layer as a mask.  
         [0047]     Portions of the WSi layer  208 , the poly crystalline silicon layer  207 , the ONO layer  206 , the poly crystalline silicon layers  205  and  204  are removed by using a RIE method and the patterned silicon oxide layer  209  as a mask, thereby forming the word lines WL 2  (gate electrodes). A silicon oxide layer  230  is then formed on the side and top surfaces of each of the word lines WL 2 .  
         [0048]     Impurities are then injected into the region where source and drain regions (not shown) are to be formed by using an ion implantation method and the word lines WL 2  as a mask, thereby forming diffusion layers  301 . A silicon nitride layer  210  is then formed by using a low pressure CVD method and portions of the silicon nitride layer  210  is removed by using a RIE method, thereby forming side wall insulating films on the side surfaces of the word lines WL 2 .  
         [0049]     A silicon nitride layer  211  is then formed on the silicon nitride layer  210 . A silicon oxide layer  212  is then formed on the silicon nitride layer  211  by using a CVD method, and is removed so as to expose an upper surface of the silicon nitride layer  211  by using a CMP method. And then, a silicon oxide layer  231  is formed by using a plasma CVD method. The silicon oxide layer  231  is then flattened by using a CMP method not so as to expose the upper surface of the silicon nitride layer  211  that is formed above the gate electrode. In this case, the silicon oxide layer  231  remains above the gate electrode. Therefore, when a contact hole  219  that will be mentioned later is formed, even if the contact hole  219  gets out of right position, the silicon oxide layer  231  that is formed above the gate electrode prevents the contact hole  219  from reaching the gate electrode.  
         [0050]     It is noted that the silicon oxide layer  231  may be flattened by using a CMP method so as to expose the upper surface of the silicon nitride layer  211  that is formed above the gate electrode. In this case, a height of the silicon oxide layer  231  can be lowered. In this result, we can gat low etching ratio.  
         [0051]     After that, a drain contact  202   a  and a source line  203  will be formed as follows. As shown in  FIG. 4 , a photo resist layer (not shown) is formed on the silicon nitride layer  231 . By using-a photolithography technique and a same photo mask, the photo resist layer is patterned into a mask by which the drain contact  202   a  and the source line  230  are to be formed. And then, portions of the silicon oxide layer  231  and the silicon oxide layer  212  are removed by using a RIE method and the patterned photo resist layer as a mask. The patterned photo resist layer is then removed.  
         [0052]     Portions of the silicon nitride layer  211  are removed so as to expose the upper surface of the semiconductor substrate  200  by using a RIE method. Ti layers  214   a ,  214   b  and W layers  214   a ,  214   b  are then formed, thereby forming the drain contact  202   a  and the source line  203 . Portions of the Ti layers  214   a ,  214   b  and W layers  214   a ,  214   b  are removed and flattened so as to expose an upper surface of the silicon oxide layer  231  by using a CMP method. It should be noted that this embodiment of the present invention is different from the conventional non-volatile semiconductor memory device in that the drain contact and the source line are formed simultaneously.  
         [0053]     As shown in  FIG. 5 , a silicon oxide layer  213  is formed and a resist layer (not shown) is then formed on the silicon oxide layer  213 . The photo resist layer is patterned into a predetermined pattern by using a photolithography technique and a same photo mask. Portions of the silicon oxide layer  213  are then removed by using a RIE method and the patterned photo resist layer as a mask, thereby simultaneously forming a contact hole  219  that is connected to the bit line  215  (See  FIG. 1 ) and the drain contact  202   a , and a contact hole  216  (shadowed) by which the source line  203  is connected to another line (not shown) that is formed in a same layer as the bit line  215 .  
         [0054]     From this embodiment of the present invention, the same photo mask can be used at the manufacturing step of the drain contact  202   a  and the source line  203 . Moreover, the same mask can be used at the manufacturing step of the contact holes  219  and  216 . Therefore, a height of the drain contact  202   a  is same as that of the source line  203 , and a height of the contact hole  219  is same as that of the contact hole  216 . From this, the aspect ratio of the drain contact  202   a  can be made lower, thereby resulting in preventing a poor conduction.  
         [0055]     As stated above, in the conventional technique, a photo mask by which the drain contact is formed is different from a photo mask by which the source line. On the other hand, in this embodiment of the present invention, the photo mask by which the drain contact  202   a  is formed is same as photo mask by which the source line  203  is formed. Therefore, it can enhance a precision of patterning, resulting in preventing a poor conduction as even downsizing progressed.  
         [0056]     In this embodiment of the present invention, a NOR type non-volatile memory device is explained. However, it is noted that it can be an NAND type non-volatile memory device.  
         [0057]     We will explain about applications having an above-mentioned semiconductor memory device. A memory card having the above mentioned semiconductor memory device is shown in  FIG. 9 . As shown in  FIG. 9 , the semiconductor memory device receives/outputs predetermined signals and data from/to an external device (not shown).  
         [0058]     A signal line (DAT), a command line enable signal line (CLE), an address line enable signal line (ALE) and a ready/busy signal line (R/B) are connected to the memory card having the above mentioned semiconductor memory device. The signal line (DAT) transfers data, address or command signals. The command line enable signal line (CLE) transfers a signal which indicates that a command signal is transferred on the signal line (DAT). The address line enable signal line (ALE) transfers a signal which indicates that an address signal is transferred on the signal line (DAT). The ready/busy signal line (R/B) transfers a signal which indicates whether the memory device is ready or not. Another example of a memory card is shown in  FIG. 10 . The memory card shown in  FIG. 45  differs from the memory card presented in  FIG. 9  in that the memory card includes a controller which controls the semiconductor memory device and receives/transfers predetermined signals from/to an external device (not shown).  
         [0059]     The controller includes an interface unit (I/F), a micro processor unit (MPU), a buffer RAM and an error correction code unit (ECC). The interface unit (I/F) receives/outputs predetermined signals from/to an external device (not shown). The micro processor unit converts a logical address into a physical address. The buffer RAM stores data temporarily. The error correction code unit generates an error correction code. And a command signal line (CMD), a clock signal line (CLK) and a signal line (DAT) are connected to the memory card.  
         [0060]     Although we explain about the memory cards as shown above, the number of the control signal lines, bit width of the signal line (DAT) and a circuit construction of the controller could be modified suitably.  
         [0061]     Another application is shown in  FIG. 11 . A memory card holder to which the memory card is inserted, is shown in  FIG. 11 . And the card holder is connected to electronic device (not shown). The card holder may have a part of the functions of the controller.  
         [0062]     Another application is shown in  FIG. 12 . As shown in  FIG. 12 , the memory card or the card holder to which the memory card is inserted, is inserted to a connecting apparatus. The connecting apparatus is connected to a board via a connecting wire and an interface circuit. The board has a CPU (Central Processing Unit) and a bus.  
         [0063]     Another application is shown in  FIG. 13 . As shown in  FIG. 13 , the memory card or the card holder to which the memory card is inserted, is inserted to a connecting apparatus. The connecting apparatus is connected to PC (Personal Computer) via connecting wire.  
         [0064]     Another application is shown in  FIGS. 14 and 15 . As shown in  FIG. 14 , An IC chip that includes the above-mentioned semiconductor memory device is located on an IC card that is made of plastic or something like that.  FIG. 15  shows a detail block diagram of the IC card and the IC chip presented in  FIG. 14 . The IC chip has a connecting terminal that is configured to connect to an external device (not shown), and a memory chip that includes the above-mentioned semiconductor memory device, a ROM, a RAM, and a CPU. The CPU contains a calculation section and a control section that is configured to connect to the semiconductor memory device.  
         [0065]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended and their equivalents.