Abstract:
A Fast Fourier Transform device of a discrete multitone modulation system can be implemented by very large scale integrated (VLSI) architecture. The I-FFT/F-FFT functions are modified to avoid complex-valued operations. A time recursive parallel lattice structure is used to reduce the complexity in hardware requirement for the I-FFT/F-FFT.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a discrete multitone transmission technology and, more particularly, to a Fast Fourier Transform device for a discrete multitone system, wherein the Fast Fourier Transform device is realized with a parallel lattice architecture by simplifying the demand for multipliers and adders through conjugate symmetry to further reduce manufacturing cost. 
     2. Description of the Prior Art 
     The recent progress of Internet access has led to the urgent demand for high-speed data transmission technology. Various multiple modulation/demodulation circuits, such as carrierless-amplitude-phase (CAP), discrete multitone modulation (DMT), quadrature amplitude modulation (QAM) technologies, have been proposed to break through the transmission bottleneck of twisted-pair phone lines. Among these advanced modulation schemes, the DMT can achieve highest transmission rate since it incorporates lots of advanced DSP techniques, such as dynamic bit allocation, multi-dimensional tone encoding, frequency-domain equalization, etc. As a consequence, the ADSL (asymmetric digital subscriber lines) standard committee has chosen the DMT as the physical-layer transmission standard. 
     In a conventional DMT system, Fast Fourier Transform (FFT) algorithm is basically adopted. However, Fast Fourier Transform is a reversible operation, which includes Forward Fast Fourier Transform, hereinafter F-FFT, and Inverse Fast Fourier Transform, hereinafter I-FFT. Therefore, the term &#34;Fast Fourier Transform&#34; as used in the following description includes both F-FFT and I-FFT, unless otherwise specified. 
     The Fast Fourier Transform device as embodied in a discrete multitone system of prior art is commonly realized with a butterfly structure formed with Fast Fourier Transform algorithm of decimation-in-time and decimation-in-frequency. Such a butterfly structure will require (6Nlog 2  2N) real adders and (4Nlog 2  2N) real multipliers for 2N-point Fast Fourier Transform device. Taking 512 (N=256) points for example, 13824 adders and 9216 multipliers will be needed. Hence, such a large demand for hardware components will increase the complexity of wiring and the required layout area, and it will become difficult for very large scale integrated (VLSI) circuit implementation due to increasing manufacturing cost. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide a Fast Fourier Transform device constituted with a time-recursive approach to reduce the computational complexity and thus eliminate complex operators by taking advantage of data symmetry so as to save the total hardware complexity. 
     It is another object of this invention to provide a Fast Fourier Transform device constituted with a parallel lattice architecture to make the entire structure more regular and modular and to simplify the complexity of wiring suitable for VLSI implementation. 
     To achieve the foregoing objects, this invention can be realized with a Fast Fourier Transform device. The Fast Fourier Transform device of the present invention includes an Inverse Fast Fourier Transform module and a Forward Fast Fourier Transform module. The Inverse Fast Fourier Transform converts x(n)s (n=0, 1, . . . , N-1) into X(k)s (k=0, 1, . . . , 2N-1), the x(n)s are inputted into said Inverse Fast Fourier Transform module by the real part x r  (n)s and imaginary part x i  (n)s, respectively, the Inverse Fast Fourier Transform module calculate their corresponding MDCT(k) function and MDST(k)function, adds them up and then output them, wherein, ##EQU1## FFT module is provided for receiving the X(k)s and calculating the corresponding MDCT(n) and MDST(n) function, combining the results outputting the corresponding x(n)s, wherein, ##EQU2## 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The objects, features and advantages of this invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a block diagram showing the Fast Fourier Transform device in the DMT system according to the present invention; 
     FIG. 2 is a diagram showing the structure of an I-FFT module of FIG. 1; 
     FIG. 3 is a detailed circuit diagram showing the lattice module IM k  of FIG. 2; 
     FIG. 4 is a detailed circuit diagram showing the special module SC1 of FIG. 2; 
     FIG. 5 is a diagram showing the architecture of a F-FFT module of FIG. 1; 
     FIG. 6 is a detailed circuit diagram showing the lattice module FM n  of FIG. 5; and 
     FIG. 7 is a detailed circuit diagram showing the special module SC2 of FIG. 5. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a diagram showing the Fast Fourier Transform device in the DMT system according to the present invention. Modulator 7 transmits signals to demodulator 8 through transmission channel 9. Modulator 7 includes a conjugate converter 1, I-FFT module 2, and parallel-to-serial converter 3. Receiving terminal 8 includes serial-to-parallel converter 4 and F-FFT module 5. If the data to be processed by I-FFT module 2 are of 2N points, then the F-FFT module 5 is the converting module for processing the 2N points data. 
     In the modulator 7, the data of x(0), x(1), x(2), . . . , x(N-1), x(N) are inputted into the I-FFT module 2, wherein the data of x(0), x(1), x(2), . . . , x(N-1) are further converted by the conjugate converter 1 into corresponding conjugate data of x(0)*, x(1)*, x(2)*, . . . , x(N-1)* and forwarded as the input data to the I-FFT module 2. The data of X(0), X(1), X(2), . . . , X(2N-2), X(2N-1) are the output data converted by the I-FFT module 2 and processed by the parallel-to-serial converter 3 as output signal y(n). 
     In the demodulator 8, the serial-to-parallel converter 4 receives signal y(n) and processes into data X(0), X(1), X×(2), . . . ,X(2N-2), X(2N-1), which are then inputted into the F-FFT module 5 for converting into x(0), x(1), x(2), . . . , x(N-1) for output. All signals processed by the demodulator 8 are added with a symbol ˜ to denote possible noise or interference during transmission through the transmission channel 9. Therefore, the received signals with noise or interference component are added with &#34;˜&#34; to differ from the original signals. 
     Since only the Fast Fourier Transform device is specified in this invention, the modulator 7 as shown in FIG. 1, for simplicity, does not include units such as bit allocation of the DMT system, TCM encoder, constellation encoder, cyclic prefix, digital/analog converter. Similarly, bit re-allocation, TCM decoder, constellation decoder, remove cyclic prefix, analog/digital converter contained in the demodulator 8 are not shown in the drawing. 
     Parallel Lattice Structure of the I-FFT Module 
     In accordance with this invention, the data inputted to the I-FFT module 2 have the following restriction so the I-FFT module 2 may only output in real number: 
     
         x(n)=x*(2N-n), for n=0, 1, . . . , N-1                     (1) 
    
     where x(n) including the real part and imaginary section is x(n)=x r  (n)+jx i  (n), wherein x(0)=x(N)=0. The series of data of 2N in length after I-FFT is represented as: ##EQU3## where, ##EQU4## X(k) of equation (2) can be divided into two parts: ##EQU5## Next, equation (2) can be simplified as follows by making use of the conjugate symmetrical properties of the input data: ##EQU6## It can be determined from equation (4) that Fast Fourier Transform calculations include two-part operations of real numbers, where the first part is a discrete cosine transform-like operation with x r  (n) (wherein n=0, 1, . . . , N-1) as input. Whereas the second part is a discrete sine transform-like operation with x i  (n) (wherein n=0, 1, . . . , N-1) as input. For simplicity, the first part of equation (4) is defined as a modified discrete cosine transform (MDCT) function and the second part as a modified sine transform (MDST) function. Moreover, MDCT function and MDST function demonstrate the following characteristics: 
     
         MDCT(k)=MDCT(2N-k) 
    
     
         MDST(k)=-MDST(2N-k)                                        (5) 
    
     Consequently, the calculation with I-FFT can be focused on the calculations of MDCT(k) function and MDST(k) function in k=0, 1, . . . , N-1. Then the calculations of MDCT(k) function and MDST(k) function in k=N+1, . . . , 2N-1 are expanded based upon equation (5), except for k=N, which requires special processing. In this manner, the hardware complexity is reduced by 50%. 
     Refer to FIG. 2, the structure of I-FFT module 2 of FIG. 1 is shown. The I-FFT module 2 is a 2N-point transform module which includes a first MDCT/MDST module array 20, an expanding circuit 21, 2(N-1) R type registers R 1  ˜R N-1  and R N+1  ˜R 2N-1 , and (2N) left shift registers 23. 
     The first MDCT/MDST module array 20 is for receiving data x(n) and performs calculations of the MDCT function and MDST function to output the calculated outcome. Since MDCT/MDST module array 20 focuses only on the calculations of MDCT(k) function and MDST(k) function in k=0, 1, . . . , N-1 due to the features shown in equation (5), the expanding circuit 21 extends the MDCT(k) function and MDST(k) function to the calculations for k=N, N+1, . . . , 2N-1. Further, the expanding circuit 21 performs multiplexing from the calculated outcomes of MDCT(k) (x,(n) as input) and MDST(k) (x i  (n) as input) as consecutive output options. For example, the result of MDCT(k) (x r  (n) as input) can first be outputted for storing in the corresponding R type registers R 1  -R N-1  and R N+1  -R 2N+1 , and then adding up in the expanding circuit 21 with the result of MDST(k) (x i  (n) as input) outputted later. Since equation (4) further includes multiplication 2, so the data outputted from the expanding circuit 21 will be shifted left by one bit by the corresponding left shift register 23 for outputting data X(0), X(1), X(2), . . . , X(2N-2), X(2N-1). 
     Refer again to FIG. 2, the first MDCT/MDST module array 20 comprises (N-1) lattice modules IM 1  IM N-1  and a specific module SC1 for receiving input data x(n). Since each x(n) includes a real part x r  (n) and an imaginary part x i  (n), according to equations (4) and (5), the present invention performs calculations of MDCT(k) function and MDST(k) function, and x r  (n) and x i  (n) are inputted to the MDCT/MDST module array 20, respectively. For example, x r  (n) (n=0, 1, . . . , N-1) can first be inputted to the first MDCT/MDST module array 20 for calculating the result of the MDCT section and then x i  (n) (n=0, 1 . . . , N-1) is inputted to the first MDCT/MDST module array 20 for calculating the result of the MDST section. In FIG. 2, lattice modules IM 1  to IM N-1  have two output terminals for outputting MDCT(k) and MDST(k), respectively. For example, the two terminals of IM1 output MDCT(1) and MDST(1) respectively, and the two terminals of IM2 output MDCT(2) and MDST(2) respectively. Similarly, the two terminals of IM N-1  output MDCT(N-1) and MDST(N-1) respectively. In particular, from equation (4), X(0) and X(N) can be simplified as follows: ##EQU7## and therefore can be outputted respectively from the two terminals of the special module SC1. In FIG. 2, each lattice module and the special module SC1 are attached with a block ↓N to denote that we pick up the MDCT/MDST results at the time x r  (N-1) and x i  (N-1) finish the updating in the mudule array 20. 
     Expanding circuit 21 comprises (N-1) multiplexers MUX 1  ˜MUX N+1  and 2(N-1) adders A 1  ˜A N-1  and A N+1  ˜A 2N-1 , multiplexers MUX 1  ˜MUX N+1  are for receiving the output data from lattice module IM 1  to IM N+1 , respectively. For example, the multiplexer MUX 1  receives the output data MDCT(1) and MDST(1) of the lattice module IM 1 . Similarly, the multiplexer MUX N-1  receives the output data MDCT(N-1) and MDST(N-1) of the lattice module IM N-1 . The output terminals of multiplexers MUX 1  to MUX N-1  connect to adders A 1  to A N-1 , respectively. Adders A 1  to A N-1  connect to R type registers R 1  to R N-1 . Since the first MDCT/MDST module array 20 focuses only on the calculations of MDCT(k) function and MDST(k) function in k=0, 1, . . . , N-1, according to the feature demonstrated by equation (5), the expanding circuit 21 extends the calculations of MDCT(k) function and MDST(k) function in k=N, N+1, . . . , 2N-1. Hence, the output terminals of multiplexers MUX 1  to MUX N-1  further connect to adders A 2N-1  to A N+1 , with adders A N+1  to A 2N-1  connecting to R type registers R 1  to R N-1 , respectively. 
     Multiplexers MUX 1  to MUX N-1  multiplexing options for sequential outputs of the calculated MDCT and MDST results, as described above, if x r  (n)(n=0, 1, . . . , N-1) is first inputted to the first MDCT/MDST module array 20 for calculating the result of MDCT section and x i  (n)(n=0, 1, . . . , N-1) is inputted further to the first MDCT/MDST module array 20 for calculating the result of MDST section, then multiplexers MUX 1  to MUX N-1  can choose through adders A 1  to A N-1  to first save MDCT result in the corresponding R type registers R 1  to R N-1  to R 2N-1 , and then multiplexers MUX 1  to MUX N-1  choose to add up the MDST result in the corresponding adders A 1  to A N-1  and A N+1  to A 2n-1  with the MDCT result stored previously in corresponding R type register R 1  to R N-1  R N+1  to R 2N-1 . Since the special module SC1 can output MDCT(0) and MDST(N) directly, it therefore can connect to the corresponding shift registers 23 directly. 
     To realize lattice modules IM 1  to IM N-1 , this invention adopts the time recursive technology as shown in K. J. Ray Liu, et al., &#34;Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transform,&#34; IEEE Trans. Circuits and Systems for Video Technology, Vol. 4, No. 2, pp. 168-180, April 1994. First, data are sequentially inputted from x r  (t) to x r  (t+N-1) and the MDCT function is defined as: ##EQU8## When the new data x r  (t+N) arrived, then the MDCT function is updated as: ##EQU9## Equation (8) can be rewritten as: ##EQU10## where ##EQU11## and ##EQU12## The relationship between X c  (k, t+1) and X c  (k, t) can be obtained by comparing equations (7) and (10) as follows: 
     
         X.sub.c (k, t+1)=X.sub.c (k, t)-x.sub.r (t)+(-1).sup.k x.sub.r (t+N)(12) 
    
     Since the initial condition is zero, so x r  (t)=0. Therefore, X c  (k, t+1) can be simplified as: 
     
         X.sub.c (k,t+1)=X.sub.c (k,t)+(-1).sup.k x.sub.r (t+N)     (13) 
    
     For the same reason, the relationship between X s  (k, t+1) and X s  (k, t) can be obtained as follows: 
     
         X.sub.s (k,t+1)=X.sub.s (k,t)                              (14) 
    
     Consequently, each lattice module of IM 1  to IM N-1  can be realized with the circuit as shown in FIG. 3 according to equations (9), (13) and (14). 
     FIG. 3 is a circuit diagram showing the lattice module IM k  (k=1, 2, . . . , N-1), said lattice module IM k  includes: a symbol converter 30, four multipliers 31 to 34, three adders 35 to 37 and two delays 38 to 39. The symbol converter 30 receives x r  (n), which is then multiplied with (31 1) k  and forwarded to the adders 35 for adding up with X c  (k, t) to yield a sum X c  (k, t+1). X c  (k, t+1) is supplied to the multipliers 31 and 33 for performing multiplication with Γ c  (k) and -Γ s  (k), respectively, and supplied to the adders 36 and 37, where Γ c  (k)=cos(πk/N) and Γ s  (k)=sin(πk/N). The output of adder 36 is connected to the delay 38, the output of the delay 38 is X c  (k, t). The output of adder 37 is connected to the delay 39, the output of the delay 39 is X s  (k, t), and X s  (k, t) is X s  (k, t+1)(as show in equation (14)). X s  (k, t+1) is supplied to the multipliers 34 and 32 for performing multiplication with Γ c  (k) and Γ s  (k), respectively, and supplied to the adders 37 and 36. The output to the adder 36 for retrieval when x r  (N-1) finishes the updating is the result of MDCT(k). 
     Further, consider the MDST function as: ##EQU13## 
     for k=0, 1, . . . , N-1 
     It can be obtained from the calculations according to the equations (8) to (11): ##EQU14## Equations (17) and (18) are similar to equations (10) and (11). Except for that x i  (n) is received by the symbol converter 30, it can be realized with the lattice module IM k  circuit as shown in FIG. 3 that the output to the adder 37 being retrieved when x i  (N-1) finishes updating is the outcome of MDST(k). 
     However, since the calculations of X(0) and X(N) can be simplified as equation (6), the special module SC1 circuit is as shown in FIG. 4. The special module SC1 comprises a symbol converter 40, two adders 41 and 42, and two delays 44 and 45. It can be known from equation (6) that the calculations of MDCT(0) and MDCT(N) only require x r  (n), therefore, x r  (0), x r  (1), . . . , x r  (N-1) are sequentially supplied to the adder 41 by feeding the output of the adder 41 to the delay 43 for adding x r  (0), x 1  (1), . . . , x r  (N-1) up sequentially and outputting the calculated outcome of MDCT(0). And the symbol converter 40 multiplies x r  (0), x 1  (1), . . . , x r  (N-1) with (-1) k  and supplies to the adder 42 by feeding the output of adder 42 to the delay 44 for adding x r  (0), -x 1  (1), . . . , (-1) N-1  X r  (N-1) up sequentially and outputting the calculated outcome of MDCT(N). 
     Parallel Lattice Structure of F-FFT Module 
     In the demodulator 8, the received signals are demodulated with the F-FFT module 5, namely: ##EQU15## Since X(k)(k=0, 1, . . . , 2N-1) are real numbers, so equation (19) can be rewritten as: ##EQU16## It can be known from equation (20) that the F-FFT can be divided into a two-part calculation of MDCT and MDST, and can be realized by adopting two real-number circuits (for calculating MDCT function and MDST function) in joint quantitative calculation of dividing with (1/2N). Therefore, the F-FFT of the invention has nothing to do with complex-valued calculations. Besides, in a DMT system, the data at points n=N, N+1, . . . , 2N-1 form a conjugate symmetry with the data at points n=0, 1, . . . , N-1, therefore, focus can be placed only on the calculation of point data n=0, 1, . . . , N-1 and the calculation of point data n=N, N+1, . . . , 2N-1 can be omitted. This practice will reduce hardware complexity by an additional 50%. 
     Refer to FIG. 5, the architecture of the F-FFT module 5 of FIG. 1 is illustrated. In FIG. 5, the F-FFT module 5 is a 2N-point converting module which includes a second MDCT/MDST module array 50 and (2N-1) right shift registers. The second MDCT/MDST module array 50 is for receiving data x (0), x (1), . . . , x (2N-1) and for calculating MDCT and MDST. The Right shift register 52 shifts each data item log 2  (2N) bits to the right for the data outputted from the second MDCT/MDST module 50, performs quantitative calculation by dividing by (1/2N) with equation (20), and outputs data x(0), x r  (1), x i  (1), . . . , x r  (N-1), x i  (N-1), x(n) only needs to combine the corresponding real part and imaginary part with (x r  (n)+jx i  (n)). 
     Refer again FIG. 5, the second MDCT/MDST module array 50 includes (N-1) lattice modules FM 1  to FM N-1  and a special module SC2 for receiving input data X(k)(k=0, 1, . . . , 2N-1). In FIG. 6, each of the lattice modules FM 1  to FM N-1  have two output terminals for outputting MDCT(n) and MDST(n), respectively. For example, the two output terminals of FM 1  output MDCT(1) and MDST (1), respectively, and the two output terminals of FM 2  output MDCT(2) and MDST (2), respectively. Similarly, the two output terminals of FM N-1  output MDCT(N-1) and MDST(N-1), respectively. With equation (20) x (0) can be simplified as the following equation: ##EQU17## So the output can be outputted from the output of the special module SC2. 
     To realize lattice module FM 1  to FM N-1 , the time-recursive equation of MDCT, same as the calculations in equation (7) to (11), is: ##EQU18## Likewise, the time-recursive equation of MDST is: ##EQU19## where ##EQU20## and ##EQU21## The two are the auxiliary MDCT and auxiliary MDST of the F-FFT module 5. Similar to equations (12) and (13), the updating equations can be obtained for x r  (n,t+1) and x i  (n,t+1) as follows: 
     
         x.sub.r (n,t+1)=x.sub.4 (n,t)+X(t+2N)                      (26) 
    
     and 
     
         x.sub.i (n,t+1)=x.sub.i (n,t)                              (27) 
    
     So each of the lattice modules FM 1  to FM N-1  can be realized with the circuit as shown in FIG. 6. 
     FIG. 6 is a detailed circuit diagram showing the lattice modules FM n  (n=1, 2, . . . , N-1), the lattice module FM n  includes: four multipliers 61 to 64, three adders 65 to 67, and two delays 68 to 69. The adder 65 receives X (k) and adds up with x r  (n,t) to yield x r  (n,t+1). Said x r  (n,t+1) is supplied to the multipliers 61 and 63, respectively, for multiplying with Γ c  (n) and -Γ s  (n) and supplied to the adders 66 and 67 where δ c  (n)=cos(πn/N) and Γ s  (n)=sin(πn/N). The output of the adder 66 is connected to the delay 68 and the output of the delay 68 is x r  (n,t). The output of the adder 67 is connected to the delay 69 and the output of the delay 69 is x i  (n,t), wherein x i  (n,t) is namely x i  (n,t+1). Said x i  (n,t+1) is supplied to the multipliers 64 and 62, respectively, for multiplying with Γ c  (n) and Γ s  (n) and supplied to the adders 67 and 66. The outcomes of MDCT(n) and MDST(n) can be retrieved from the output of adders 66 and 67. 
     However, since the calculation of x(0) can be simplified as equation 21), the special module SC2 circuit is as shown in FIG. 7. Said special module SC2 includes: an adder 70 and a delay 71. It can be known from equation (21), the calculation of MDCT(0) needs only to feed x(0), x (1), . . . , x (2 N-1) supplied to the adder 70 through the output of the adder 41 to the delay 43 for adding up those x (0), x (1), . . . , x (2N-1) and then outputting the calculated outcomes of MDCT(0). Basically, the special module SC2 is an accumulator. 
     The Analysis of Circuit Complexity 
     In the following the parallel lattice architecture of Fast Fourier Transform of the present invention will be compared with the butterfly structure realized with conventional Cooley-Tukey theory. A 2N-point Fast Fourier Transform realized with a butterfly structure will include log 2  (2N) stages, each stage will require N multipliers and 2N adders. Since input data are composed of complex-valued data, the multiplication operation of each complex-valued data will require four real multipliers and two real adders. Therefore, a Fast Fourier Transform device realized with a butterfly structure will require (4Nlog 2  2N) real multipliers and (6Nlog 2  2N) real-number adders in total. 
     In accordance with this invention, the I-FFT is divided into two real transform circuits (namely, MDCT and MDST) and the I-FFT circuit can be realized with only real number operand. As shown in FIG. 2, the special module SC1 includes two adders, whereas each of the (N-1) lattice modules IM 1  to IM N-1  includes four real multipliers and three real adders. Besides, the complete I-FFT module 2 will further need additional 2(N-1) adders, (N-1) multiplexers and 2(N-1) R type registers, that is, 4(N-1) real multipliers and [5(N-1)+2] real adders in total. The F-FFT is as shown in FIG. 5. The special module SC2 is an accumulator, the entire F-FFT module 5 will need 4(N-1) real multipliers and [3(N-1)+1] real adders. 
     The following Tables 1 and 2 show a comparison table of the parallel lattice architecture among the conventional Butterfly structure (prior art 1), &#34;The quick Fourier transform: An Fast Fourier Transform based on symmetries&#34; by H. Guo et al. in IEEE Trans. Signal Processing (Vol. 46, No. 2, pp. 335-341, Feb. 1998)(prior art 2), and the present invention in terms of 2N point Fast Fourier Transform device, wherein Table 1 is a comparison table of multipliers, and Table 2 a comparison table of adders. 
     
                       TABLE 1______________________________________I-FFT              F-FFTPrior Art         Prior Art                  The In-                        Prior Art                               Prior Art                                      The In-N    1        2        vention                        1      2      vention______________________________________256  9216     3202     1020  9216   1601   1020512  20480    7426     2044  20480  3713   20441024 45056    16898    4092  45056  8449   40922048 98304    37890    8188  98304  18945  81884096 212992   83970    16380 212992 41985  163808192 458752   184322   32764 458752 92161  32764______________________________________ 
    
     
                       TABLE 2______________________________________I-FFT              F-FFTPrior Art         Prior Art                  The In-                        Prior Art                               Prior Art                                      The In-N    1        2        vention                        1      2      vention______________________________________256  13824    15100    1277  13824  6530   766512  30720    33788    2557  30720  14850  15341024 67584    74748    5117  67584  33282  30702048 147456   163836   10237 147456 73730  61424096 319488   356348   20477 319488 161794 122868192 688128   770044   40957 688128 352258 24574______________________________________ 
    
     To summarize, the invention provides with a Fast Fourier Transform device suitable for DMT system realized as a VLSI circuit. According to this invention, I-FFT/F-FFT functions are modified to avoid the complex-valued operations. Moreover, this invention utilizes a time-recursive parallel lattice structure to reduce the complexity in required hardware for the I-FFT/F-FFT. Taking 512 (N=256) points, for example, the required multipliers is only 11% of those of the prior art, and the required adders 9% of those of the prior art. This practice is the best resolution for reducing manufacturing cost for an orthogonal frequency division multiplexing (OFDM) or transceiver system. 
     Although the present invention has been described in its preferred embodiment, it is not intended to limit the invention to the precise embodiment disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.