Abstract:
The present application provides a thin film transistor and a method of manufacturing same capable of suppressing diffusion of aluminum to oxide semiconductor and selectively etching oxide semiconductor and aluminum oxide. The thin film transistor includes: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer includes at least a first insulating film made of a first insulating material, and a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present application claims priority to Japanese Priority Patent Application JP 2009-050741 filed in the Japan Patent Office on Mar. 4, 2009, the entire content of which is hereby incorporated by reference. 
       BACKGROUND 
       [0002]    The present application relates to a thin film transistor (TFT) having an oxide semiconductor layer as a channel (active layer), a method of manufacturing the same, and a display device using the thin film transistor. 
         [0003]    Oxide semiconductor such as zinc oxide, indium gallium zinc oxide (InGaAnO), or the like displays excellent property as an active layer of a semiconductor device. In recent years, the oxide semiconductor is being developed with aim for applications to a TFT, a light emitting device, a transparent conductive film, and the like. For example, a TFT using oxide semiconductor has electron mobility higher than that of a TFT using amorphous silicon (a-Si: H) which is used in an existing liquid crystal display device, and has excellent electric property. There is also an advantage that high mobility is expected even at low temperature around the room temperature. 
         [0004]    On the other hand, it is known that, heat resistance of the oxide semiconductor is insufficient, oxygen, zinc, and the like desorbs by heat treatment in the TFT manufacturing process, and a lattice defect occurs. The lattice defect electrically causes shallow impurity level and lower resistance in an oxide semiconductor layer. Consequently, the operation becomes an operation of a normally-on type, that is, depletion-type in which drain current flows without applying gate voltage. The defect level becomes higher, the threshold voltage decreases, and leak current increases. There is consequently a disadvantage such that the characteristic fluctuation of a TFT using oxide semiconductor is large (J. Non-Crystalline Solids 354 (2008) 2826). 
         [0005]    To address the disadvantage, a technique is being proposed that, for example, a gate insulating film which is in contact with a channel layer made of oxide semiconductor is made of amorphous aluminum oxide (Al 2 O 3 ) and used as a sealing film that reduces the defect level in the interface (see, for example, Japanese Patent No. 3,913,756). 
       SUMMARY 
       [0006]    When the aluminum oxide is used for the sealing film (gate insulating film), however, an issue occurs such that aluminum (Al) in the aluminum oxide is diffused in the oxide semiconductor, and the long-term property deteriorates. In addition, there is another issue that it is difficult to perform selective etching between the aluminum oxide and oxide semiconductor, process margin is narrow, and the yield is low. 
         [0007]    It is desirable to provide a thin film transistor and a method of manufacturing the same capable of suppressing diffusion of an element of a sealing film into a channel layer (oxide semiconductor). 
         [0008]    It is also desirable to provide a thin film transistor and a method of manufacturing the same realizing selective etching to a sealing film and a channel layer (oxide semiconductor) and to provide a display device realizing stable display by using the thin film transistor. 
         [0009]    According to an embodiment of the present application, there is provided a thin film transistor including: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer has a two-layer structure formed by at least: a first insulating film made of a first insulating material; and a second insulating film made of a second insulting material. The second insulating material has etching selectivity to each of the oxide semiconductor and the first insulating material and is provided between the first insulating film and the channel layer. 
         [0010]    The oxide semiconductor is at least one of ZnO, ITO, and In-M-Zn—O (where M is at least one of Ga, Al, Fe, and Sn). For example, the first insulating material is Al 2 O 3 , and the second insulating material is at least one of SiO X , SiN X , Y 2 O 3 , TaO, and HfO and their oxynitrides. 
         [0011]    In the thin film transistor, the second insulating film having etching selectivity to each of the oxide semiconductor and the first insulating material is provided between the channel layer whose main component is the oxide semiconductor and the first insulating film such as Al 2 O 3 . Therefore, diffusion into the channel layer of the element in the first insulting film is suppressed and selective etching to the first insulating film and the channel layer with the second insulting film therebetween is enabled. 
         [0012]    A first method of manufacturing a thin film transistor according to an embodiment of the present application relates to a method of manufacturing a bottom-gate type thin film transistor and includes the following steps (elements) of: 
         [0013]    (A1) forming a gate electrode on a substrate; 
         [0014]    (B1) forming a gate insulating film on the gate electrode and, after that, forming a channel layer whose main component is oxide semiconductor on the gate insulating film; 
         [0015]    (C1) forming a second insulating film made of a second insulating material and a first insulating film made of a first insulating material in this order on the channel layer; 
         [0016]    (D1) forming a channel protection film on the first insulating film and, after that, etching the first insulating film using the second insulating film as a stopper; 
         [0017]    (E1) etching the second insulating film using the processed first insulating film as a mask and using the channel layer as a stopper; 
         [0018]    (F1) forming a pair of electrodes serving as a source and a drain so as to be in contact with the channel layer; and 
         [0019]    (G1) using the second insulating material having etching selectivity to each of the oxide semiconductor and the first insulating material. 
         [0020]    A second method of manufacturing a thin film transistor according to an embodiment of the present application is provided for manufacturing a thin film transistor of a top-gate type and includes the following steps (elements): 
         [0021]    (A2) forming a first insulating film made of a first insulting material and a second insulting film made of a second insulating material in this order on a substrate; 
         [0022]    (B2) forming a pair of electrodes serving as a source and a drain on the second insulating film; 
         [0023]    (C2) forming a channel layer whose main component is oxide semiconductor on the second insulating film and the pair of electrodes; 
         [0024]    (D2) forming a gate insulating film on the channel layer and etching the channel layer using the pair of electrodes as a stopper; 
         [0025]    (E2) forming a gate electrode on the gate insulating film; and 
         [0026]    (F2) making the second insulating material have etching selectivity to each of the oxide semiconductor and the first insulating material. 
         [0027]    In the thin film transistor and the method of manufacturing the same of the embodiment of the invention, the second insulating film is provided between the channel layer whose main component is oxide semiconductor and the sealing film (the first insulating film), and the second insulating film has etching selectivity to each of the oxide semiconductor and the first insulating film. With the configuration, diffusion to the channel layer (oxide semiconductor), of the element of the sealing film is suppressed, and selective etching to the sealing film and the channel layer (oxide semiconductor) is enabled. Consequently, both of the sealing effect by the sealing film made of aluminum oxide or the like and improvement in yield are satisfied, and long-term property of the thin film transistor improves. 
         [0028]    Additional features and advantages are described herein, and will be apparent from the following Detailed Description and the figures. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0029]      FIG. 1  is a cross section illustrating the configuration of a TFT according to a first embodiment of the present application. 
           [0030]      FIGS. 2A to 2C  are cross sections illustrating a method of manufacturing the TFT illustrated in  FIG. 1  in process order. 
           [0031]      FIGS. 3A to 3C  are cross sections illustrating processes subsequent to  FIGS. 2A to 2C . 
           [0032]      FIGS. 4A to 4C  are cross sections illustrating processes subsequent to  FIGS. 3A to 3C . 
           [0033]      FIG. 5  is a plan view corresponding to the process of  FIG. 3B . 
           [0034]      FIG. 6  is a plan view corresponding to the process of  FIG. 4A . 
           [0035]      FIGS. 7A to 7C  are cross sections illustrating a method of forming a TFT according to a second embodiment. 
           [0036]      FIGS. 8A and 8B  are cross sections illustrating processes subsequent to  FIGS. 7A to 7C . 
           [0037]      FIGS. 9A and 9B  are cross sections illustrating processes subsequent to  FIGS. 8A and 8B . 
           [0038]      FIG. 10  is a diagram illustrating an example of the configuration of a display device. 
           [0039]      FIG. 11  is an equivalent circuit diagram illustrating an example of a pixel drive circuit illustrated in  FIG. 10 . 
           [0040]      FIG. 12  is a plan view illustrating a schematic configuration of modules including the display device. 
           [0041]      FIG. 13  is a perspective view illustrating the appearance of application example 1 of the display device. 
           [0042]      FIG. 14A  is a perspective view illustrating the appearance of the surface side of application example 2, and  FIG. 14B  is a perspective view illustrating the appearance of the back side. 
           [0043]      FIG. 15  is a perspective view illustrating the appearance of application example 3. 
           [0044]      FIG. 16  is a perspective view illustrating the appearance of application example 4. 
           [0045]      FIG. 17A  is a front view illustrating an open state of application example 5,  FIG. 17B  is a cross section,  FIG. 17C  is a front view illustrating a closed state,  FIG. 17D  is a left side view,  FIG. 17E  is a right side view,  FIG. 17F  is a top view, and  FIG. 17G  is a bottom view. 
       
    
    
     DETAILED DESCRIPTION 
       [0046]    The present application will be described below with reference to the drawings according to an embodiment. The description will be given in the following order. 
         [0047]    1. First embodiment (example of bottom-gate-type TFT) 
         [0048]    (1) General configuration of TFT 
         [0049]    (2) Manufacturing method of TFT 
         [0050]    2. Second embodiment (example of top-gate-type TFT) 
         [0051]    3. Configuration example of display device using TFT 
         [0052]    4. Configuration example of modules including display device 
         [0053]    5. Concrete application examples 1 to 5 
       First Embodiment 
       [0054]    General Configuration of TFT 
         [0055]      FIG. 1  illustrates a sectional configuration of a bottom-gate-type thin film transistor (TFT) according to a first embodiment of the present application. A TFT  1  has, on a substrate  11  with an insulating film  12  in between, a gate electrode  13 , a gate insulating film  14 , a channel layer  15 , and a sealing layer  16  (a first insulating film  16   a  and a second insulating film  16   b ) in this order. 
         [0056]    The substrate  11  is, for example, a silicon substrate and may be made of another material such as quart, glass, metal, resin, resin film, or the like. The insulating film  12  is made of an insulating film material such as silicon (Si). 
         [0057]    The gate electrode  13  controls electron density in the channel layer (oxide semiconductor layer)  15  by gate voltage applied to the TFT  1  and has a two-layer structure of, for example, a molybdenum (Mo) layer having a thickness of 50 nm and an aluminum (Al) layer or an aluminum alloy layer having a thickness of 400 nm. An example of the aluminum alloy layer is an aluminum-neodymium alloy layer. 
         [0058]    The gate insulting film  14  is made of, for example, an insulting film material including silicon (Si) like the insulating film  12 . The gate insulating film  14  covers the gate electrode  13  and is formed, for example, so as to cover the entire surface of the substrate  11  including the surface of the gate electrode  13 . 
         [0059]    The channel layer  15  is an oxide semiconductor layer containing, as a main component, conductive oxide semiconductor such as zinc oxide (ZnO), Indium Tin Oxide (ITO), or In-M-Zn—O (M is at least one of Ga, Al, Fe, and Sn). 
         [0060]    The sealing layer  16  has a two-layer structure of, for example, the first insulating film  16   a  and the second insulating film  16   b . The first insulating film  16   a  is made of aluminum oxide (Al 2 O 3 ) as a main component. The first insulating film  16   a  suppresses desorption of oxygen or the like from the channel layer  15  whose main component is oxide semiconductor by excellent gas barrier resistance of aluminum oxide, and suppresses changes in carrier concentration in the oxide semiconductor to stabilize the electric property of the TFT  1 . The thickness of the first insulating film  16   a  is preferably in a range of 10 nm to 500 nm both inclusive. When the film thickness is less than 10 nm, the sealing capability decreases. When the film thickness is greater than 500 nm, the etching process time becomes longer more than necessary. More preferably, the film thickness is in a range of 50 nm to 300 nm both inclusive. 
         [0061]    The second insulating film  16   b  is interposed between the first insulating film  16   a  and the channel layer  15  and has the function of preventing diffusion of aluminum (Al) in the first insulating film  16   a  into the channel layer  15 . The second insulating film  16   b  is made of a material having excellent etching selectivity to the oxide semiconductor of the channel layer  15  and the first insulating material with the same gas (or solution). Concrete examples of the oxide semiconductor as the main component are silicon oxide (SiO X ), silicon nitride (SiN X ), yttrium oxide (Y 2 O 3 ), tantalum oxide (Ta 2 O 6 ), and hafnium oxide (HfO 2 ). 
         [0062]    In a region opposing the gate electrode  13  in the sealing layer  16 , a channel protection film  17  made of the same material as that of the insulating film  12  is provided. In regions extending from the surface of the channel protection film  17  to the surface of the channel layer  15  via the side faces of the sealing layer  16 , a pair of source and drain electrodes  18 A and  18 B are provided. The source and drain electrodes  18 A and  18 B are formed by metals such as molybdenum (Mo), aluminum, and titanium or a multilayer film of the elements. 
         [0063]    On the sealing layer  16  and the source and drain electrodes  18 A and  18 B, for example, a protection film  19  made of the same material as that of the insulating film  12  is provided. The protection film  19  has through holes  19 A and  19 B in correspondence with the source and drain electrodes  18 A and  18 B, respectively. To the source and drain electrodes  18 A and  18 B, wirings  20 A and  20 B are electrically connected via the through holes  19 A and  19 B, respectively. 
         [0064]    The TFT  1  is manufactured, for example, as follows. 
         [0065]    Manufacturing Method 
         [0066]    First, as illustrated in  FIG. 2A , on the substrate  11  made of glass, SiOx is deposited by, for example, CVD (Chemical Vapor Deposition) to form the insulating film  12 . Subsequently, for example, by sputtering, a molybdenum (Mo) layer is formed and, after that, the gate electrode  13  is formed by photolithography and dry etching. Next, the gate insulating film  14  is formed on the entire surface of the substrate  11  by, for example, plasma CVD. After formation of the gate insulating film  14 , for example, the channel layer  15  is formed by sputtering using an oxide target of In—Ga—Zn in vacuum. Subsequently, by continuous sputtering in the same vacuum, for example, SiOx is deposited with a thickness of 10 nm as the second insulting layer  16   b  and, further continuously, for example, Al 2 O 3  is deposited with a thickness of 50 nm as the first insulating layer  16   a  by sputtering. 
         [0067]    As illustrated in  FIGS. 2B and 2C , for example, SiOx is deposited with a thickness of 300 nm by CVD. Subsequently, a resist (photosensitive resin film) is patterned by photolithography and SiOx is dry-etched with C 2 HF 5  gas to which oxygen is added, thereby forming the channel protection film  17 . By the etching selectivity between the first insulating film  16   a  (Al 2 O 3 ) and the channel protection film  17  (SiOx), the first insulating film  16   a  becomes a stopper (etching stop layer). 
         [0068]    Subsequently, as illustrated in  FIG. 3A , the resist is patterned by photolithography and, after that, the first insulating film  16   a  (Al 2 O 3 ) is processed in a predetermined shape by dry etching using chlorine gas. At this time, by the etching selectivity between the first insulating film  16   a  and the second insulating film  16   b  (SiOx layer), the second insulating film  16   b  becomes a stopper. As illustrated in  FIG. 3B , by dry etching using C 4 F 8  gas to which hydrogen is added, the second insulating film  16   b  (SiOx layer) is processed. At this time, by the etching selectivity between the second insulating film  16   b  (SiOx layer) and the channel layer  15  (oxide layer of In—Ga—Zn), the channel layer  15  becomes a stopper. By making the second insulating film  16   b  interposed between the first insulting film  16   a  and the channel layer  15 , in the embodiment, the process margin in the process of etching the channel layer  15  is widened, and the yield improves. 
         [0069]    Next, by wet etching using dilute hydrochloric acid, the channel layer  15  is isolated transistor by transistor. 
         [0070]    The resist is patterned by photolithography and, after that, the channel layer  15  is selectively removed by dry etching using chlorine gas. Subsequently, by selectively removing the gate insulating film  14  by dry etching using C 2 HF 5  gas to which oxygen is added, the gate electrode  13  in an electrode extracting part is exposed as illustrated in the plan view of  FIG. 5 . 
         [0071]    As illustrated in  FIG. 3C , Mo is deposited with a thickness of 100 nm by using, for example, sputtering and the source and drain electrodes  18 A and  18 B are formed by dry etching using Cl 2 CF 4  gas to which oxygen is added. 
         [0072]    As illustrated in  FIGS. 4A and 6 , a SiN film is formed on the entire surface by, for example, CVD to form the protection film  19 . Subsequently, the protection film  19  (SiN) is selectively removed by dry etching using the C 2 HF 5  gas to which oxygen is added, thereby forming the through holes  19 A and  19 B. After that, the wirings  20 A and  20 B are formed by sputtering. By the above process, the bottom-gate-type TFT  1  illustrated in  FIG. 1  is completed. 
         [0073]    In the embodiment, as the sealing layer  16  on the channel layer  15  (oxide semiconductor layer), in addition to the first insulating film  16   a  (aluminum oxide), the second insulating film  16   b  made of the insulating material (such as SiOx) other than aluminum oxide is interposed between the first insulating film  16   a  and the channel layer  15 . By making the second insulating film  16   b  exist between the channel layer  15  and the first insulating film  16   a , selective etching between the aluminum oxide and the oxide semiconductor is enabled. Further, by the second insulating film  16   b , diffusion of aluminum in aluminum oxide into the channel layer  15  (oxide semiconductor) is prevented, and the defect level in the interface of the oxide semiconductor layer is lowered. Thus, both the sealing effect by the aluminum oxide and improvement in the yield are satisfied, and the long-term properties of the TFT are improved. 
         [0074]    Although the example of applying the present application to the bottom-gate-type TFT has been described above, the invention is also applicable to a top-gate-type TFT. The manufacturing process of the top-gate-type TFT will be described as a second embodiment. The same reference numerals are designated to the same components as those of the foregoing embodiment, and their description will not be repeated. 
       Second Embodiment 
       [0075]    The top-gate-type TFT of the second embodiment has, as illustrated in  FIG. 9B , on the substrate  11  with the insulating film  12  in between, the sealing layer  16  (the first insulating film  16   a  and the second insulating film  16   b ), the channel layer  15 , the gate insulting film  14 , and the gate electrode  13  in this order. 
         [0076]    First, as illustrated in  FIG. 7A , the insulating film  12  (SiOx) having a thickness of 100 nm is formed by, for example, CVD on the substrate  11  made of glass, for example, Al 2 O 3  is deposited with a thickness of 50 nm as the first insulting film  16   a  and, for example, SiOx is deposited with a thickness of 100 nm as the second insulating film  16   b . Subsequently, as illustrated in  FIG. 7B , titanium (Ti) is deposited with a thickness of 10 nm and Mo is deposited with a thickness of 100 nm by using sputtering and, after that, the Ti/Mo film is selectively removed by dry etching using Cl 2 CF 4  gas to which oxygen is added by photolithography. By the operation, the source and drain electrodes  18 A and  18 B are formed. Next, as illustrated in  FIG. 7C , by sputtering using an oxide target of In—Ga—Zn, the channel layer  15  is formed on the second insulating film  16   b  and the source and drain electrodes  18 A and  18 B. 
         [0077]    As illustrated in  FIG. 8A , for example, by CVD, SiOx is deposited with a thickness of 300 nm, thereby forming the gate insulting film  14 . Subsequently, the gate insulating film  14  (SiOx) is selective removed by dry etching using C 2 HF 5  gas to which oxygen is added. After that, by wet etching using dilute hydrochloric acid, the channel layer  15  is isolated. By etching selectivity between the gate insulting film  14  (SiOx layer) and the channel layer  15  (the oxide layer of In—Ga—Zn), at the time of etching the gate insulating film  14 , the channel layer  15  serves as a stopper. At the time of etching the channel layer  15 , by etching selectivity between the channel layer  15  (the oxide layer of In—Ga—Zn) and the source and drain electrodes  18 A and  18 B as an underlayer, the source and drain electrodes  18 A and  18 B become stoppers. 
         [0078]    As illustrated in  FIG. 8B , Ti is deposited with a thickness of 10 nm and Mo is deposited with a thickness of 100 nm by sputtering. After that, by dry etching using Cl 2 CF 4  gas to which oxygen is added, those metal films are selectively removed, thereby forming the gate electrode  13 . 
         [0079]    Subsequently, as illustrated in  FIG. 9A , Al 2 O 3  is deposited with a thickness of 100 nm on the gate electrode  13 , the gate insulating film  14 , and the source and drain electrodes  18 A and  18 B by, for example, sputtering, thereby forming the protection film  19 . Subsequently, the through holes  19 A and  19 B are formed by dry etching using chlorine gas and, after that, the wirings  20 A and  20 B are formed as illustrated in  FIG. 9B . By the above process, a top-gate-type TFT  2  is completed. 
         [0080]    In the embodiment, as the sealing layer  16  below the channel layer  15  (oxide semiconductor layer), in addition to the first insulating film  16   a  (aluminum oxide), the second insulating film  16   b  made of the insulating material (such as SiOx) other than aluminum oxide is interposed between the first insulating film  16   a  and the channel layer  15 . By making the second insulating film  16   b  exist between the channel layer  15  and the first insulating film  16   a , in a manner similar to the first embodiment, diffusion of aluminum in aluminum oxide into the channel layer  15  (oxide semiconductor) is prevented, and the defect level in the interface of the oxide semiconductor layer is lowered. 
         [0081]    An application example of the thin film transistor will be described below. 
         [0082]      FIG. 10  illustrates the configuration of a display device used as an ultrathin organic light emitting color display. The display device has a display region  110  in which pixels PXLC made by a plurality of organic light emitting elements  10 R,  10 G, and  10 B which will be described later as display elements are disposed in matrix. In the periphery of the display region  110 , a horizontal selector (HSEL)  121  as a signal unit, a write scanner (WSCN)  131  as a scanner unit, and a power supply scanner (DSCN)  132  are formed. 
         [0083]    In the display region  110 , signal lines DTL 101  to DTL 10   m  are disposed in the column direction, and scan lines WSL 101  to WSL 10   m  and power supply lines DSL 101  to DSL 10   m  are disposed in the row direction. At the cross point between the signal line DTL and the scan line WSL, a pixel circuit  140  including the organic light emitting element PXLC (any one of red, blue, and green (sub-pixel)) is provided. The signal lines DTL are connected to the horizontal selector  121 , and a video signal is supplied from the horizontal selector  121  to the signal line DTL. The scan lines WSL are connected to the write scanner  131 . The power supply lines DSL are connected to the power supply scanner  132 . 
         [0084]      FIG. 11  illustrates an example of the pixel circuit  140 . The pixel circuit  140  is an active-type drive circuit having a sampling transistor  3 A, a drive transistor  3 B, a retentive capacitor  3 C, and a light emitting element  3 D formed by the organic light emitting element PXLC. The transistors  3 A and  3 B are the above-described thin film transistors of the present application. 
         [0085]    The gate of the sampling transistor  3 A is connected to the scan line WSL 101 , one of the source and the drain of the sampling transistor  3 A is connected to the signal line DTL 101 , the other is connected to the gate “g” of the drive transistor  3 B. The drain “d” of the drive transistor  3 B is connected to the corresponding power supply line DSL 101 , and the source “s” is connected to the anode of the light emitting element  3 D. The cathode of the light emitting element  3 D is connected to a grounding wiring  3 H. The grounding wiring  3 H is disposed commonly to all of the pixels PXLC. The retentive capacitor  3 C is connected between the source “s” and the gate “g” of the drive transistor  3 B. 
         [0086]    The sampling transistor  3 A is conducted in accordance with a control signal supplied from the scan line WSL 101 , samples the signal potential of the video signal supplied from the signal line DTL 101 , and retains the signal potential in the retentive capacitor  3 C. The drive transistor  3 B receives supply of current from the power supply line DSL 101  at a first potential, and supplies the drive current to the light emitting element  3 D in accordance with the signal potential retained in the retentive capacitor  3 C. The light emitting element  3 D emits light with luminance according to the signal potential of the video signal by the supplied drive current. 
         [0087]    In the display device, the sampling transistor  3 A is conducted according to the control signal supplied from the scan line WSL, samples the signal potential of the video signal supplied from the signal line DTL, and retains the signal potential in the retentive capacitor  3 C. Current is supplied from the power supply line DSL at a first potential to the drive transistor  3 B. According to the signal potential retained in the retentive capacitor  3 C, the drive current is supplied to the light emitting element  3 D (organic light emitting elements of red, blue, and green). Each of the light emitting elements  3 D emits light with luminance according to the signal potential of the video signal by the supplied drive current. 
       Modules and Application Examples 
       [0088]    Next, application examples of the display device will be described. The display device may be applied as display devices of electronic devices in all of fields for displaying a video signal entered from the outside or generated internally as an image or a video image, such as a television apparatus, a digital camera, a notebook-sized personal computer, a portable terminal device such as a cellular phone, and a video camera. 
         [0089]    Modules 
         [0090]    The display device of the embodiments is assembled, for example, as a module illustrated in  FIG. 12 , in various electronic devices in application examples 1 to 5 and the like which will be described later. The module has, for example, at one side of the substrate  11 , a region  210  exposed from the sealing substrate  50  (and the adhesive layer  60 ). To the region  210 , wirings of a signal line drive circuit  120  and a scan line drive circuit  130  are extended and external connection terminals (not illustrated) are formed. The external connection terminal may be provided with a flexible printed circuit (FPC)  220  for inputting and outputting signals. 
       Application Example 1 
       [0091]      FIG. 13  illustrates the appearance of a television apparatus to which the display device is applied. The television apparatus has, for example, a video image display screen  300  including a front panel  310  and a filter glass  320 . The video display screen  300  is constructed by the display device according to any of the embodiments. 
       Application Example 2 
       [0092]      FIGS. 14A and 14B  illustrate the appearance of a digital camera to which the display device is applied. The digital camera has, for example, a light emission unit  410  for flash, a display unit  420 , a menu switch  430 , and a shutter button  440 . The display unit  420  is constructed by the display device according to any of the foregoing embodiments. 
       Application Example 3 
       [0093]      FIG. 15  illustrates the appearance of a notebook-sized personal computer to which the display device of the foregoing embodiment is applied. The notebook-sized personal computer has, for example, a body  510 , a keyboard  520  for operation of entering characters and the like, and a display unit  530  for displaying an image. The display unit  530  is constructed by the display device according to any of the foregoing embodiments. 
       Application Example 4 
       [0094]      FIG. 16  illustrates the appearance of a video camera to which the display device is applied. The video camera has, for example, a body  610 , a lens  620  for shooting a subject, provided on the front face of the body  610 , a shooting start-stop switch  630 , and a display unit  640 . The display unit  640  is constructed by the display device according to any of the foregoing embodiments. 
       Application Example 5 
       [0095]      FIGS. 17A to 17G  illustrate the appearance of a cellular phone to which the display device is applied. The cellular phone is obtained by, for example, coupling an upper-side casing  710  and a lower-side casing  720  via a coupling unit (hinge)  730  and has a display  740 , a sub-display  750 , a picture light  760 , and a camera  770 . The display  740  or the sub-display  750  is constructed by the display device according to any of the foregoing embodiments. 
         [0096]    The thin film transistor of the present application has been described above by the embodiments. However, the invention is not limited to the embodiments. The configuration of the thin film transistor of the present application may be freely modified as long as effects similar to those of the foregoing embodiments are obtained. 
         [0097]    For example, in the first embodiment, the channel layer  15 , the second insulting film  16   b , and the first insulating film  16   a  are continuously formed in this order in vacuum. Only the channel layer  15  and the second insulating film  16   b  may be continuously formed and temporarily exposed to the atmosphere. After that, the first insulting layer  16   a  may be newly formed. Also after formation of the first insulating film  16   a , an upper layer may be continuously formed in vacuum. 
         [0098]    Although the case of using the aluminum oxide film as the first insulating film  16   a  has been described in the foregoing embodiments, for example, gallium oxide (Ga 2 O 3 ) or zirconium oxide (ZrO 2 ) may be used. In this case as well, process may be performed while providing etching selectivity between the second insulating film  16   b  and the channel layer  15  made of oxide semiconductor. 
         [0099]    It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims.