Abstract:
Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO 3  film is disposed over the metal layer. A resistor layer comprising a SrZrO 3  film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a Divisional of co-pending application Ser. No. 11/723,547, filed on 20 Mar. 2007, and for which priority is claimed under 35 U.S.C. §120; the entire contents of which is hereby incorporated by reference. 
         [0002]    This application is related to U.S. patent application Ser. No. 11/108,823, filed Apr. 19, 2005, commonly owned by Winbond and entitled as “NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF”, the contents of which are hereby incorporated by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The invention relates to a non-volatile memory and a fabrication method thereof, and more particularly, to a resistive non-volatile memory and a fabrication method thereof. 
         [0005]    2. Description of the Related Art 
         [0006]    Memory devices are typically divided into volatile and non-volatile types. With volatile memory devices, such as DRAM or SRAM, a continuous power supply is required to store data. For non-volatile memory devices, such as ROM, data can be stored therein for long periods of time without power supply. 
         [0007]    As mobile phones, digital cameras, personal digital assistants (PDAs), notebooks, and other portable electronic devices become more popular, non-volatile memory devices are widely applied therein due to their ability to retain stored data without requiring power supply and low energy consumption. Among non-volatile memory devices, flash memory is currently popular. As the semiconductor technology improves, flash memory devices face challenges of high operating voltage (causing difficulty for device size conservation) and gate oxide thinning (causing unsatisfactory retention time). Thus, many new non-volatile memories have been developed to replace flash memories. Among these, resistive non-volatile memory provides high write and erase speeds, low operating voltage, long retention time, simple structure, low power consumption, small size, and low cost. 
         [0008]      FIG. 1  is a schematic diagram of a conventional resistor type non-volatile memory  10 , disposed on a substrate  12 , comprising a dielectric layer  14 , a bottom electrode  16 , a resistor layer  18 , and a top electrode  20 . The bottom electrode  16  comprises a platinum film. The resistor layer  18  comprises a chromium (Cr) doped strontium titanate single crystal and provides reversible resistance switching. 
         [0009]    However, according to conventional methods, fabrication of the resistor layer  18  still presents problems. For example, two methods are typically used. In one, a single crystal structure of SrTiO 3  is formed with an orientation ( 100 ) and then undergoes flame fusion to form a Cr doped SrTiO 3  single crystal. Alternatively, a pulse laser sputtering process is used to grow a Cr doped SrZrO 3  film. However, the single crystal structure used in the previous method generates high cost. The latter method is not suitable for large area films. Thus, neither method can meet the requirements of mass production. 
       BRIEF SUMMARY OF THE INVENTION 
       [0010]    An embodiment of the invention provides a non-volatile memory formed on a substrate. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO 3  film is disposed over the metal layer. A resistor layer comprising a SrZrO 3  film is disposed on the buffer layer. A top electrode is disposed on the resistor layer. 
         [0011]    Further provided is a method of fabricating a non-volatile memory on a substrate. A metal layer acting as a bottom electrode of the non-volatile memory is formed over the substrate. A buffer layer comprising a LaNiO 3  (LNO) film is then formed over the metal layer. A resistor layer comprising a SrZrO 3  (SZO) film is formed on the buffer layer. A top electrode is then formed on the resistor layer. 
         [0012]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0013]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0014]      FIG. 1  is a schematic diagram of a conventional resistor type non-volatile memory; 
           [0015]      FIG. 2   a  is a cross-section of a first embodiment of a resistive non-volatile memory of the invention; 
           [0016]      FIG. 2   b  is a cross-section of a control memory; 
           [0017]      FIGS. 3   a  and  3   b  show an experimental structure and a control structure, respectively; 
           [0018]      FIGS. 4   a  and  4   b  show two X-ray diffraction patterns corresponding to the experimental structure of  FIG. 3   a  and the control structure of  FIG. 3   b , respectively; 
           [0019]      FIGS. 5   a  and  5   b  show voltage vs. current measurement results for the experimental DUT in  FIG. 2   a  and the control DUT in  FIG. 2   b , respectively; 
           [0020]      FIGS. 6   a  and  6   b  respectively depict current paths inside the experimental DUT in  FIG. 2   a  and inside the control DUT in  FIG. 2   b;    
           [0021]      FIG. 7  is a cross-section of a second embodiment of a resistive non-volatile device of the invention; and 
           [0022]      FIG. 8  shows a platinum layer acting as a bottom electrode directly contacting a silicon substrate without titanium film therebetween. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0024]      FIG. 2   a  is a cross-section of a first embodiment of a resistive non-volatile memory  110   a  of the invention. As shown in  FIG. 2   a , the memory  110   a  comprises a substrate  112 , a dielectric layer  114 , a bottom electrode  116 , a buffer layer  117 , a resistor layer  118 , and top electrodes  120  stacked in sequence. A predetermined area of buffer layer  117  is not covered by resistor layer  118  such that a metal connector  122  therein directly contacts buffer layer  117 . Top electrodes  120  and metal connector  122  can be formed using the same metal layer and the same photo mask. Top electrodes  120  can together act as one terminal of the resistive non-volatile memory  110   a,  and metal connector  122  as the other. 
         [0025]    In an embodiment, the dielectric layer  114  comprises a silicon oxide layer with a thickness of 100 to 500 nm on a substrate of P-type silicon. The bottom electrode  116  comprises a titanium film  116   a  of about 1 nm to 100 nm and a platinum film  116   b  of about 10 nm to 500 nm, where platinum film  116   b  is stacked on the titanium film  116   a  over the dielectric layer  114 . The buffer layer  117  comprises a LaNiO 3  film of highly preferred ( 100 ) and ( 200 ) orientation structure at a thickness of about 20 nm to 500 nm. The resistor layer  118  comprises a SrZrO 3  film doped with dopants comprising V, Cr, Fe, Nb, or combination thereof. The dopant concentration is about 0.05% to 1.5% by atomic percentage. The thickness of the resistor layer  118  is about 20 nm to 500 nm. The top electrodes  120  and the metal connector  122  comprise an aluminum film. 
         [0026]    In an embodiment of a method of fabricating the non-volatile memory  110   a,  a substrate  112 , such as a silicon substrate, is first provided and then cleaned by standard Radio Corporation of America (RCA) cleaning process. After cleaning, a thermal oxidation is preformed to grow a silicon oxide layer on the substrates  112  as the dielectric layer  114  to isolate leakage current from the substrate  112 . Then, E-gun evaporation is performed to form a titanium film  116   a  on the dielectric layer  114 . Similarly, another E-gun evaporation is performed to form a platinum film  116   b  on the titanium film  116   a . Then, a radio-frequency (RF) magnetron sputtering process is performed to form a LaNiO 3  film as a buffer layer  117  on the platinum film  116   b.  In the radio-frequency magnetron sputtering process, the LaNiO 3  film  117  is grown at 250° C. Plasma power density is about 3.3 W/cm 2 , with working pressure 10 mTorr and gas flow rate 40 sccm. The ratio between Ar and O 2  is 6:4. Note that the formed LaNiO 3  film has a highly preferred orientation structure, such as ( 100 ) or ( 200 ). 
         [0027]      FIG. 3   a  shows an experimental structure  200   a  formed according to the process described.  FIG. 3   b  shows a control structure  200   b,  formed with the buffer layer  117  directly contacting the dielectric layer  114 . The control structure in  FIG. 3   b  differs from experimental structure  200   a  in the omission of bottom electrode  116 . LaNiO 3  film with a lattice orientation of ( 100 ) is preferred since a SrZrO 3  film stacked thereon has a larger resistive ratio between two current states and requires less voltage to switch between the two current states, in comparison with the SrZrO 3  film stacked on a ( 110 )-oriented LaNiO 3  film.  FIGS. 4   a  and  4   b  show two X-ray diffraction patterns corresponding to the experimental structure  200   a  of  FIG. 3   a  and the control structure  200   b  of  FIG. 3   b , respectively. Apparently, the peaks in  FIG. 4   b  illustrates that the LaNiO 3  film in  FIG. 3   b  has a lattice orientation of ( 100 ), as does the LaNiO 3  film formed on a platinum film in  FIG. 3   a , as shown by the peaks in  FIG. 4   a . Irrespective of whether it is formed directly on a SiO 2  film or a platinum film, a LaNiO 3  film has a lattice orientation of ( 100 ), which is preferred. 
         [0028]    The experimental structure  200   a  in  FIG. 3   a  and the control structure  200   b  in  FIG. 3   b  can be further processed simultaneously, for the purpose of device characteristic measurement. A radio-frequency magnetron sputtering process is then performed using SrZrO 3  as a target material to form a SrZrO 3  film with a thickness of 20 nm to 500 nm (of which 45 nm is preferred) acting as the resistor layer  118  on buffer layer  117 . In an embodiment, the target material is doped with dopants comprising V, Cr, Fe, Nb, or a combination thereof at a dopant concentration about 0.05% to 1.5% by atomic percentage. As a result, the resistor layer  118  formed on buffer layer  117  has a corresponding dopant concentration. In addition, the growth temperature of the resistor layer  118  is about 500° C. Plasma power density is about 3.3 W/cm 2 , with working pressure about 10 mTorr, and gas flow rate about 40 sccm. The ratio between Ar and O 2  is about 6:4. During the RF magnetron sputtering process, a predetermined area of buffer layer  117  is shielded, preventing from being coated by resistor layer  118 , such that the buffer layer  117  in the predetermined area is not covered by resistor layer  118 . A thermal evaporating process is performed to form an aluminum film having a thickness of 300 nm on the resistor layer  118 . A patterning process performed with a proper mask defines a pattern of the aluminum film and to form top electrodes  120  and metal connector  122 , creating the cross-section shown in  FIG. 2   a  for the experimental structure  200   a  of  FIG. 3   a  and the cross-section shown in  FIG. 2   b  for the control structure  200   b  of  FIG. 3   b . For convenience and clarity, memory  110   a  shown in  FIG. 2   a  is referred to as an experimental device under test (DUT) and memory  110   b  shown in  FIG. 2   b  as a control DUT, hereinafter. 
         [0029]      FIGS. 5   a  and  5   b  demonstrate voltage vs. current measurement results for the experimental DUT  110   a  in  FIG. 2   a  and the control DUT  110   b  in  FIG. 2   b , respectively. As shown in  FIG. 5   b , a −13V bias voltage to the control DUT  110   b  suddenly increases the current therethrough, switching its current state from low to high, while a 12V voltage bias returns the control DUT  110   b  to the low current state, indicating that resistance of the control DUT  110   b  can be converted or switched by way of changing the polarity of a bias voltage, implementing a memory function. The resistive ratio for the high current state to the low current state around 0V voltage bias exceeds 10 3 , as can be seen in  FIG. 5   b , and the switching between the current states is repeatable. The measurement results in  FIG. 5   a  show, even so, an improved property of the experimental DUT  110   a,  which has an additional platinum film under the LaNiO 3  film in comparison with the control DUT  110   b . Applying a −3V voltage bias suddenly increases the device current to the limited current (1 mA), indicating successful switching from a low current state to a high current state. Without limiting the device current, applying a −2V voltage bias also suddenly returns the device current to its original current state, switching from the high current state to the low current state. As shown in  FIG. 5   a , current state switching from high to low or low to high also occurs when applying 2V or 3V voltage bias, respectively. The phenomenon shown in  FIG. 5   a  implies that changing the magnitude of a bias voltage can alter the resistance of the experimental DUT  110   a  such that a state is “remembered” therein. The resistive ratio for the experimental DUT  110   a  around 0V bias voltage is as high as over 10 5 , and the switching between the current states is also repeatable. 
         [0030]    It has also been found that a voltage pulse to switch the current state of control DUT  110   b  from low to high requires a pulse magnitude of −20V and a pulse width of 5 nanoseconds while that to switch from high to low requires a pulse magnitude of 20V and a very long pulse width of 500 microseconds. Comparatively, the current state of experimental DUT  110   a  has proven to be switchable from low to high by a voltage pulse having a pulse magnitude of −6V and a pulse width of 10 nanoseconds and from high to low by a voltage pulse having a pulse magnitude of −4V and a pulse width of 10 nanoseconds. The experimental DUT  110   a  thus demonstrates superior performance compared to the control DUT  110   b  lacking a platinum film. 
         [0031]      FIGS. 6   a  and  6   b  respectively depict current paths inside the experimental DUT  110   a  in  FIG. 2   a  and inside the control DUT  110   b  in  FIG. 2   b . The experimental DUT  110   a  in  FIG. 2   a  at its high current state shows a resistance of 20 Ohm but the control DUT  110   b  in  FIG. 2   b  at its high current state shows a relatively significant resistance of 15 kOhm. Thus, the 15 kOhm is attributable to the path P LNO  in  FIG. 6   b  that extends horizontally inside the thin and highly resistive LaNiO 3  film. The overall current path in  FIG. 6   a  cannot otherwise be as low as 20 Ohm. The platinum film provides a bypass P Pt , through which the majority of the current in  FIG. 6   a  goes horizontally inside the highly conductive platinum film  116   b  rather than inside the highly resistive LaNiO 3  film. The lower resistance of the current path in  FIG. 6   a  mainly results in the lower voltage magnitudes or the narrower voltage pulse widths required for operating the experimental DUT  110   a  in  FIG. 2   a.    
         [0032]      FIG. 7  is a cross-section of a second embodiment of a resistive non-volatile device  700  of the invention. The device  700  in  FIG. 7  is similar to the experimental DUT  110   a  in  FIG. 2   a , differing in that buffer layer  117  and resistor layer  118  of  FIG. 7  do not cover a predetermined area of bottom electrode  116  where metal connector  122  contacts the bottom electrode  116 . It is believed that device  700  in  FIG. 7  exhibits the same device properties as the experimental DUT  110   a  in  FIG. 2   a.    
         [0033]    Titanium film  116   a  in  FIG. 2   a  acts as an adhesive layer for a platinum layer  116   b  to be formed on a silicon oxide layer. If the platinum layer is to be formed directly on a silicon substrate, a titanium film therebetween can be omitted.  FIG. 8  shows a platinum layer  116   b  acting as a bottom electrode and directly contacting silicon substrate  112  without a titanium film therebetween. 
         [0034]    Compared with the control DUT  110   b  of  FIG. 2   b , the experimental DUT  110   a  of  FIG. 2   a  has an additional bottom electrode  116  between buffer layer  117  and dielectric layer  114 , obtaining lower operation voltages and narrower pulse width for current state switching. Hence, the experimental DUT  110   a  is better suited to integration in advanced integrated circuits that require low voltage power supply and low power consumption. 
         [0035]    While the invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.