Abstract:
An LDO circuit with a current sink stage reduces significantly overshooting of the output voltage due to sudden changes of output current. The activation of the current sink stage is independent of the overshoot percentage of the regulated output voltage. The disclosure doesn&#39;t require large output capacitors to avoid the possibility of brownouts of chips supplied by the LDO.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present document relates to DC-to-DC converters. In particular, the present document relates to a current sink stage for low drop-out (LDO) regulators. 
         [0003]    2. Background 
         [0004]    LDOs are traditionally unidirectional power supplies i.e. they can either sink or source current. 
         [0005]    In case of an LDO sourcing current there is either no sink capability or very small current sink capability, which would be triggered only if the voltage at output overshoots a certain percentage more than the expected regulated voltage. The voltage at the output of LDO can overshoot in an event of sudden removal of load. 
         [0006]    If the voltage at output overshoots but is within the specified tolerance the current sink would usually not be enabled. This results in skewing of the potential at internal nodes of the LDO and slower response to a load transient (sudden requirement of current by the load), a slower response translating to a larger dip in the regulated output voltage, which may generate a brown-out condition for the chip being powered by LDO, this is especially true for ICs requiring low voltages 
         [0007]    A common way to reduce the dip in the output voltage is to increase the output decoupling capacitor which means a larger footprint on the very expensive PCB real estate especially in the case of handheld devices. 
         [0008]    Current sinks are also needed to avoid back powering of the battery if current is pushed into the output of LDO by some source external to a PMIC. 
         [0009]    Using bi-directional push-pull LDOs may be a solution but they are very complex to compensate and require additional quiescent current. The additional current eats into a very tight power budget for a PMIC in low power mode. 
         [0010]    A current sink is implemented using either a comparator or an amplifier. Both have advantages and disadvantages. An amplifier would regulate the voltage at the output by regulating the current it sinks depending on the current sourced into the output of LDO, but are difficult to compensate. Comparators on the other hand don&#39;t require any compensation but may suffer from chattering and they don&#39;t regulate the output voltage if current pushed into the LDO output is less than the current sink capability of the comparator. 
         [0011]      FIG. 1  prior art shows a simplified schematic of an implementation of an LDO with a current sink or over-voltage sink. 
         [0012]    P 1  is the pass device and A 1  is an amplifier controlling the gate of P 1 . R 2 , R 1  &amp; Rprot form a feedback resistor divider network for regulating the output voltage. C 1  is an external decoupling capacitor. The load is an external IC powered by the LDO 
         [0013]    A 2  and transistor N 1  form an over-voltage sink. A 2  can be configured as a comparator or as an amplifier. Under normal operation Vov is lower than the reference voltage Vref and the gate of N 1  is pulled to ground, so no current is sunk from the output. In an overvoltage condition, if the voltage at Vov is higher than or equal to Vref, the current sink is activated. The gate of N 1  is driven by A 2  to sink the current from output voltage VOUT. 
         [0014]    If A 2  is configured as a comparator, the gate of N 1  is driven either to supply or ground. If A 2  along with N 1  and capacitor C 1  is configured as an amplifier, the gate of N 1  is regulated depending on the difference between Vov and Vref 
         [0015]      FIG. 2  prior art shows a plot of a response of the LDO of  FIG. 1 , wherein A 2  is configured as a comparator and a current of 1 mA is sourced into the output of the LDO. As the current sourced is lower than the sink capability of comparator we observe a 20 mV of saw tooth at the output of LDO. The gate of N 1  swings between ground and supply voltage. If such an LDO has to power a sensitive analog chip, such a saw tooth response at the output is undesirable. The output voltage, when the sourced current is removed, raises nearly 35 mV above the regulated target voltage and all the internal nodes of LDO are completely skewed at this point. 
         [0016]      FIG. 3  prior art shows a plot of a response of the LDO of  FIG. 1 , wherein A 2  is configured as an amplifier and a current of 1 mA is sourced into the output of the LDO. As  FIG. 3  shows, the output voltage of the LDO is regulated and the gate of N 1  is regulated to sink 1 mA of current. The output voltage, when the sourced current is removed, is nearly 10 mV higher than the regulated target voltage and all the internal nodes of LDO are completely skewed at this point. 
         [0017]    It is a challenge for designers of LDOs to achieve LDOs, wherein activation of current sink is independent of the percentage overshoot above the regulated output voltage, that regulate the output voltage to a defined output voltage if the current sourced into LDO is less than the current sink capability, wherein a dip in the output voltage is within a minimal load transient specification, any possibility of brown-out condition is avoided, and which don&#39;t require larger capacitors at the output to avoid a possibility of brown-out condition. 
         [0018]    Solutions are desired to avoid the drawbacks mentioned above. 
       SUMMARY 
       [0019]    A principal object of the present disclosure is to achieve an LDO, wherein activation of current sink is independent of an overshoot in the regulated output voltage. 
         [0020]    A further object of the disclosure is to achieve an LDO, wherein a current sink stage sinks a regulated amount of current. The current is regulated as it is controlled by a feedback loop. The current sunk by the circuit will be equal to the current sourced into the LDO, limited by maximum current sink capability. 
         [0021]    A further object of the disclosure is to achieve an LDO that doesn&#39;t require any compensation for this current sink circuit. 
         [0022]    A further object of the disclosure is to achieve an LDO regulating the output voltage to a defined output voltage if the current sourced into LDO is less than the maximum current sink capability of the current sink. 
         [0023]    A further object of the disclosure is to achieve an LDO, wherein the dip in the output voltage is within a load transient specification for a series of randomly occurring load pulses that can skew the internal nodes of the LDO and any possibility of brown-out condition is avoided. 
         [0024]    In accordance to the objects of the disclosure a Low Drop-Out voltage regulator (LDO) with a current sink circuitry, wherein the activation of the current sink is independent of a percentage of an overshoot of the regulated output voltage has been achieved. The LDO with current sink stage disclosed firstly comprises: an LDO comprising: a port for a VDD supply voltage, a port for output of the LDO, and a pass device, wherein a source of the pass device is connected to VDD supply voltage and a gate of the pass transistor is configured to be biased a threshold voltage below the VDD supply voltage of the pass device. Furthermore the LDO comprises an output voltage divider capable of providing a feedback voltage, which is proportional to the output voltage, and a differential amplifier, configured to comparing the feedback voltage with a reference voltage and to regulating a gate of the pass device depending on a difference between the feedback voltage and the reference voltage. Moreover the LDO comprises a current sink circuitry comprising a sensing circuit configured to detecting an overshoot of the output voltage of the LDO and a circuit configured to sinking current from the output of the LDO in case of detection of said overshoot of the output voltage, wherein an activation of the circuit configured to sinking current is independent of a percentage of overshoot above a target value of the output voltage and current from the output of the LDO is sunk as long as an overshoot of the output voltage of the LDO exists. 
         [0025]    In accordance to the objects of the disclosure a method to achieve an LDO with a current sink stage, wherein activation of the current sink is independent of a percentage of an output voltage overshoot has been disclosed. The method disclosed comprises the steps of: (1) an LDO comprising a pass device, an output node, a circuitry capable of sensing proportionally an output voltage, a circuitry capable of detecting an overshoot of the output voltage of the LDO, and a current sink stage, (2) sensing the output voltage of the LDO, generating a feedback voltage, which is proportional to the output voltage, comparing the feedback voltage to a reference voltage, and regulating a gate of the pass device in order to keep the output voltage on a target value, (3) sensing the output voltage of the LDO in order to detect an output voltage overshoot, wherein a result of the sensing to detect an output voltage overshoot is not proportional to the output voltage and is independent of the sensing of the output voltage in order to generate the feedback voltage, and (4) activating the current sink stage in case an output voltage overshoot has been detected in order to sinking current from the output node until the output voltage overshoot condition is remediated, wherein the activation of the current sink stage is independent of the percentage of the output voltage overshoot. 
     
    
     
       SHORT DESCRIPTION OF THE FIGURES 
         [0026]    The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein 
           [0027]      FIG. 1  prior art shows a simplified schematic of an implementation an LDO with a current sink or over-voltage sink. 
           [0028]      FIG. 2  prior art shows a plot of a response of the LDO of  FIG. 1 , wherein A 2  is configured as a comparator and wherein 1 mA of current is sourced into the output of the LDO. 
           [0029]      FIG. 3  prior art shows a plot of a response of the LDO of  FIG. 1 , wherein A 2  is configured as an amplifier and wherein 1 mA of current is sourced into the output of the LDO. 
           [0030]      FIG. 4  depicts a circuit of an LDO with a current sink stage according to the present disclosure. 
           [0031]      FIG. 5  exhibits the response of the LDO with the current sink circuit disclosed, shown in  FIG. 4 , for 1 mA of current sourced into output of LDO (load current). 
           [0032]      FIG. 6  shows the response of a 300 mA LDO using the prior art current sink implementation shown in  FIG. 1  to a load transient from 0 mA to 300 mA in 1 us. 
           [0033]      FIG. 7  shows the response of 300 mA LDO using the current sink implementation disclosed to a load transient from 0 mA to 300 mA in 1 us. 
           [0034]      FIG. 8  shows a comparison between the circuit of  FIG. 1  prior art and the circuit disclosed of  FIG. 4  using a novel current sink for full scale load transient. 
           [0035]      FIG. 9  illustrates a flowchart of a method to activate a current sink of an LDO independent of a percentage of overshoot of the output voltage of the LDO. 
       
    
    
     DETAILED DESCRIPTION 
       [0036]    The present disclosure relates to an LDO, wherein a dip in the output voltage of the LDO due to a random train of load transient is kept within a minimal load transient specification and any possibility of brown-out condition is avoided. An overshoot of the output voltage occurs if the output voltage exceeds a range of the output voltage defined by a circuit specification. 
         [0037]      FIG. 4  depicts a circuit of an LDO with a current sink stage  40  according to the present disclosure. The circuit disclosed comprises a sensing circuit to detect an overvoltage condition and a circuit to sink the current from output. 
         [0038]    Current source I 1  and transistors Pa 1 , Pa 2 , Pa 3 , and Na 1  are part of a sensing circuit to detect an overvoltage condition of the output voltage. Current sources I 1  and I 2  and transistors Pa 3 , Na 2  and Na 3  are a part of current sink circuit. 
         [0039]    It should be noted that sensing of an overshoot condition is performed from a different point than sensing the output voltage via resistive voltage divider R 1  and R 2  using feedback voltage Vfb, which is compared with the reference voltage Vref to generate the voltage Diffout. 
         [0040]    It should be noted that the sensing of the overshoot condition of the output voltage is not proportional to the output voltage, since this circuit does not use a resistor divider tap as shown in  FIG. 1  to sense an overvoltage condition. 
         [0041]    Transistors Pa 1 , Pa 2  and Na 1 , being a part of the over-shoot voltage sensing circuit, generate the potential “vcas” to bias the gate of transistor Pa 3 . Transistors Pa 1  and Pa 2  are sized such that transistor Pa 3  would conduct only when Vgate voltage is less than VDD_PASS minus threshold voltage Vth P8 . Transistors Pa 1 , Pa 2 , P 8  and P 9  are of the same type, and are matched. 
         [0042]    I 1  is a current source used to bias transistor N 4  under no load condition due to a very large ratio between transistors P 3  and pass device P 9 . Under normal operating condition transistor Pa 3  is OFF as the voltage difference Vgate−vcas is less than threshold voltage for Pa 3 . 
         [0043]    Current source I 2  makes sure than in normal operating condition, if there is any leakage from Pa 3  to VSINK, the potential at gate of Na 3  is pulled to ground. 
         [0044]    In an event of overvoltage of feedback voltage Vfb being higher than reference voltage Vref causing potential at Diffout to increase, node Fst 1  is pulled low to turn off transistor N 4 . Current source I 1  tries to pull the voltage Vgate to VDD_PASS. 
         [0045]    As the potential difference between Vgate and vcas gets higher than threshold voltage of Pa 3 , the current I 1  starts to flow from transistor Pa 3  to transistor Na 2 . Transistors Na 2  and Na 3  form a current mirror. Transistor Na 3  starts to sink current from VOUT. Transistor P 7  is a current source load for N 3 . Capacitor C 1  is a Miller capacitor to increase stability of the LDO. As shown in  FIG. 4  Vout is connected to the drain of Na 3 . The gates of N 1  and N 2  are connected to the gate of device Na 1 . 
         [0046]    The current from current source I 1  and a ratio between transistors Na 3  and Na 2  define the maximum current that can be sunk from VOUT. Once the potential at VOUT starts to decrease, the internal nodes of the LDO start to return to their normal operating condition and eventually Pa 3  is switched off. As Na 3  sinks current from the output node VOUT, the external capacitor Cout at the LDO output “VOUT” is discharged. The output voltage VOUT is gradually reduced to correct the regulating voltage. As voltage VOUT reduces, so does feedback voltage Vfb and the current in the two branches to the differential amplifier Amp is balanced. This results in restoring the correct voltage at Diffout. As the voltage at Diffout is restored, the voltage at node Fst 1  raises and voltage Vgate is restored to a threshold voltage below VDD_PASS. As this results in the gate-source voltage across transistor Pa 3  to be less than the PMOS threshold voltage and transistor pa 3  is turned off. 
         [0047]    Current source I 2  is much smaller compared to current source I 1 . Current source I 2  could alternatively be replaced by a large resistor or a MOS transistor operating as a resistor. 
         [0048]    It has to be noted that the activation of the current sink is independent of the percentage of overshoot of the regulated output voltage. The amount of, current sunk is regulated The circuit of  FIG. 4  regulates the output voltage to programmed output voltage if the current sourced into the LDO is less than the current sink capability. Per normal LDO operation, transistor P 9  supplies current in case the output voltage is lower than a target voltage. The current sink loop is stabilized by an external capacitor Cout at VOUT. 
         [0049]    Devices P 1 , P 2  and P 3  form a current mirror. Similarly N 1 , N 2  and Na 1  also form a current mirror. The current generated by current source Bias is the current that when it flows into diode connected transistor P 1  is mirrored into transistors P 2  and P 3  depending on the mirror ration between P 1 , P 2 , and P 3 . 
         [0050]    Device Na 1  is always conducting. Na 1  acts as a current source to help generate the voltage Vcas, to determine when device Pa 3  conducts. Pa 3  turns on when Vgate&gt;Vcas plus a threshold voltage. 
         [0051]    The current mirrored from P 1  to P 2  flows into diode connected transistor N 1  and sets the voltage “nbias”. 
         [0052]      FIG. 5  exhibits the response of the LDO with the current sink circuit disclosed, shown in  FIG. 4 , for 1 mA of current sourced into output of LDO. As it can be observed the current sink disclosed regulates the voltage of the LDO at the required voltage of 3.3 V with a very small and short voltage jump of 60 mV with a duration of about 0.08 milliseconds, when 1 ma of current is pushed into the LDO. 
         [0053]      FIG. 6  shows the response of a 300 mA LDO using the prior art current sink implementation shown in  FIG. 1  to a load transient from 0 mA to 300 mA in 1 us. 
         [0054]      FIG. 6  shows from top down the Vgate voltage, the voltage at FST 1 , DiffOut voltage, the output voltage VOUT, and the load current. As it can be seen a release of load results in complete skewing of the internal nodes of the LDO, the gate of pass device is pulled to supply, the potential at node Fst 1  is pulled to ground. An output voltage dip of 118 mV is caused by a load transient of 300 mA independent of the amplifier or comparator configuration of A 2  in  FIG. 1 . A 1  of  FIG. 1  is the LDO circuit of  FIG. 4 , minus the sub-circuit containing devices PA 1 , PA 2 , PA 3 , NA 1 , NA 2 , NA 3  and I 2 . 
         [0055]      FIG. 7  shows the response of 300 mA LDO, using the current sink of the implementation disclosed, to a load transient from 0 mA to 300 mA in 1 us. 
         [0056]      FIG. 7  shows from top down the Vgate voltage, the voltage at FST 1 , DiffOut voltage, the output voltage Vout, and the load current. As it can be seen a release of the load current does not result in skewing of the internal nodes of the LDO, the gate Vgate of pass device is biased a threshold voltage below the supply, the potential at node Fst 1  is same as its normal operating point of 550 mV. The resulting load transient dip is 37 mV only. 
         [0057]      FIG. 8  shows a comparison between the circuit of  FIG. 1  prior art and the circuit of  FIG. 4  disclosed using a novel current sink for full scale load transient. 
         [0058]      FIG. 8  compares the output of the LDOs shown in  FIG. 1  prior art and in  FIG. 4  along with the potential at internal nodes between two events of full scale load transient. Trace  88  shows the load current of the full scale load event. 
         [0059]    Traces  80  and  81  show the voltage Vgate, trace  80  shows the trace of the prior art current sink, trace  81  shows the trace of the current sink disclosed. Traces  82  and  83  show the voltage FST 1 , trace  82  shows the trace of the prior art current sink, trace  83  shows the trace of the current sink disclosed. Traces  84  and  85  show the voltage Diffout, trace  84  shows the trace of the prior art current sink, trace  85  shows the trace of the current sink disclosed. Traces  86  and  87  show the output voltage Vout, trace  86  shows the trace of the prior art current sink, trace  87  shows the trace of the current sink disclosed. As it obvious that the novel current sink circuit disclosed has far better response compared to the old circuit. 
         [0060]    Referring also the  FIG. 4 , it should be noted that a main point of the current sink disclosed is that the output Diffout of the differential amplifier remains relatively constant in case of the randomly occurring full scale load transient. In an event of overvoltage of feedback voltage Vfb being higher than reference voltage Vref causing potential at Diffout to slightly increase and turning on transistor N 3 , node Fst 1  is pulled low to turn off transistor N 4 . Current source I 1  tries to pull the voltage Vgate to VDD_PASS. As the potential difference between Vgate and vcas gets higher than threshold voltage of Pa 3 , the current I 1  starts to flow from transistor Pa 3  to transistor Na 2 . Transistors Na 2  and Na 3  form a current mirror. Transistor Na 3  starts to sink current from VOUT. Once the potential at VOUT starts to decrease, the internal nodes of the LDO start to return to their normal operating condition and eventually Pa 3  is switched off. It should be understood that the regulation process of the output voltage using the current sink is performed during a fraction of a millisecond as shown in trace  85 . 
         [0061]    Trace  87  shows an important advantage of the present disclosure, namely the dip of the output voltage is much smaller than the dip of the prior art. This may be of special importance in case the LDO is supplying a chip and a voltage dip such as with prior art is beyond an acceptable voltage swing of the chip. Such a situation would cause a brown-out of the chip which is unacceptable. 
         [0062]      FIG. 9  illustrates a flowchart of a method to achieve an LDO with a current sink stage, wherein activation of the current sink is independent of a percentage of an output voltage overshoot. A first step  90  describes the provision of an LDO comprising a pass device, a circuitry capable of sensing proportionally an output voltage, a circuitry capable of detecting an overshoot of the output voltage of the LDO, and a current sink stage. Step  91  shows sensing the output voltage of the LDO, generating a feedback voltage, which is proportional to the output voltage, comparing the feedback voltage to a reference voltage, and regulating a gate of the pass device in order to keep the output voltage on a target value. Step  92  illustrates sensing the output voltage of the LDO in order to detect an output voltage overshoot, wherein a result of the sensing to detect an output voltage overshoot is not proportional to the output voltage and is independent of the sensing of the output voltage in order to generate the feedback voltage. The final step  93  depicts in case an output voltage overshoot has been detected in order to sinking current from the output node until the output voltage overshoot condition is remediated, wherein the activation of the current sink stage is independent of the percentage of the output voltage overshoot.