Abstract:
A phase-lock loop (PLL) has an oscillator comprising a plurality of operating curves. A method for implementing a multi-transfer curve in a phase lock loop. By means of a finite state machine cooperating with a current cell, the unwanted loop gain is effectively reduced to produce a wide-ranging operating curve.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to electronic circuits, and in particular, to phase-lock loops.  
         [0002]     In modern technologies, signals having gigahertz frequency, requiring phase-lock loops are the foundation for various applications. A phase-lock loop (PLL) is a circuit that generates a periodic output signal having a constant phase relationship with respect to a periodic input signal.  
         [0003]      FIG. 1  shows a block diagram of a conventional charge pump-based phase-lock loop  100 . Phase/frequency detector (PFD)  102  compares the phase θ Ref  of the input signal F Ref  to the phase θ back  of the feedback signal F back  and generates an error signal, either an up signal (when θ Ref  leads θ back ) or a down signal (when θ back  leads θ Ref ), where the width of the error signal pulse indicates the magnitude of the difference between θ Ref  and θ Back .  
         [0004]     Charge pump  104  generates an amount of charge equivalent to the error signal (either up or down) from PFD  102 . Depending on whether the error signal is an up signal or a down signal, the charge is either added to or subtracted from the capacitors in loop filter  106 . In this description, the loop filter  106  has a relatively simple design, comprising a capacitor C s  in parallel with the series combination of a resistor R and a relatively large capacitor C L . As such, loop filter  106  operates as an integrator that accumulates the net charge from charge pump  104 , and the architecture is also known as a charge pump-based loop filter. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage V LF  is applied to voltage-to-current converter (V2C)  108 , and a corresponding current ILF is applied to the current control oscillator (CCO)  110 . A CCO is a device that generates a periodic output signal (F osc  in  FIG. 1 ), whose frequency is a function of the CCO input current (C LF  in  FIG. 1 ). In addition to being the output signal from PLL  100 , the CCO output signal F osc  is used to generate the feedback signal F Back  for the closed-loop PLL circuit.  
         [0005]     An optional feedback divider  112  is placed in the feedback path, respectively, if the frequency of the output signal F osc  is to be either a fraction or a multiple of the frequency of the input signal F Ref . If not, the feedback divider applies a factor of 1 to the feedback signals, respectively.  
         [0006]     Due to the effect of the feedback path in PLL  100 , the steady-state output signal F osc  will have a fixed phase relationship with respect to the input signal F Ref . Unless some phase offset is purposely added, the phases of the input and output signals will be synchronized with minimal offset.  
         [0007]      FIG. 4   a  shows a transfer curve according to the diagram in  FIG. 1 , where the input voltage V LF  induces a corresponding output oscillating signal at frequency F osc  through the V2C and CCO. For low-noise PLL applications, it is important for CCO  108  in  FIG. 1  to have a relatively low gain. This implies that the slope of the transfer curve should be relatively low, such as those shown in  FIG. 4   b . It is therefore desirable to design a selectable operating curve for the CCO to generate a stable oscillating loop signal.  
         [0008]     Conventionally, each CCO is tested in the factory to characterize its set of operating curves to pre-determine which digital control input values (i.e. N=2 in  FIG. 4   b ) are appropriate for different desired output frequencies. When a particular CCO is selected for a particular application, such as PLL  100  of  FIG. 1 , the appropriate operating curve is permanently burned into the device. This factory testing and hard-wiring of the CCO adds to the cost of manufacturing the PLLs. It also limits the operating frequency range of each PLL to the permanently selected operating curve.  
       SUMMARY OF THE INVENTION  
       [0009]     An object of the present invention is to provide an integrated circuit having a phase-lock loop (PLL). The PLL comprises a phase/frequency detector (PFD), a charge pump-based loop filter, a state machine, and a voltage controlled oscillator (VCO) with a plurality of operating curves. An error signal is generated by the phase/frequency detector (PFD) based on comparing an input signal and a PLL feedback signal. A filtered voltage corresponding to the error signals is generated by the charge pump-based loop filter. A state condition is determined based on comparing the input signal and the PLL feedback signal by the state machine.  
         [0010]     The voltage controlled oscillator (VCO) comprises a current cell, a voltage-to-current converter (V2C), and a current-controlled oscillator (CCO). One of the operating curves is selected according to the state condition and a first current is generated accordingly by the current cell. The voltage-to-current converter (V2C) selects an operating point on a selected operating curve and converts the filtered voltage to a second current. An oscillating signal is generated by the current-controlled oscillator (CCO) according to the operating point, and is used to generate the PLL feedback signal.  
         [0011]     Another object of the present invention is to provide a method for implementing a multi-transfer curve in a phase lock loop. The method comprises the following steps.  
         [0012]     In an initial mode, a current operating curve based on comparing an input signal and a PLL feedback signal is determined, a default current to select a default operating point on the current operating curve is provided, and an oscillating signal according to the default operating point is output. When the comparison of the input signal and the PLL feedback signal meets a predetermined requirement, the procedure switches to a normal mode.  
         [0013]     In normal mode, a filtered current based on comparing the input signal and the PLL feedback signal is generated, an operating point on the current operating curve according to the filtered current is selected, and the oscillating signal according the operating point is output. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:  
         [0015]      FIG. 1  is a block diagram of PLL according to the related art;  
         [0016]      FIG. 2  is a block diagram of PLL according to the present invention;  
         [0017]      FIG. 3  is a detailed diagram for charge pump-based filter loop in  FIG. 2 ;  
         [0018]      FIG. 4   a  shows a transfer curve according to the related art;  
         [0019]      FIG. 4   b  shows a plurality of transfer curves according to the present invention; 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]     A detailed description of an embodiment of the present invention is provided in the following.  
         [0021]      FIG. 2  shows a block diagram of a charge bump-based phase-lock loop  200 , according to one embodiment of the present invention. In PLL  200 , phase frequency detector (PFD)  102 , charge pump  104 , loop filter  106 , voltage to current (V2C)  108 , current control oscillator (CCO)  110  and feedback divider  112  are analogous to the corresponding components of PLL  100  of  FIG. 1 . In addition, PLL  200  comprises frequency detector  202 , state machine  204 , current cell  206  and current adder  208 . These components are designed to enable PLL  200  to automatically select an appropriate operating curve whenever the PLL  200  is powered on.  
         [0022]     In  FIG. 2 , the frequency detector  202  detects the frequency difference of the reference signal F Ref  and the feedback signal F Back , and the state machine  204  determines whether a condition state is appropriate. The state machine delivers digital values N (the value of N depends on implementation) for the current cell  206  to select an appropriate operating current curve and output a current accordingly.  
         [0023]     The PLL  200  operates in two modes, initial mode, and normal mode. The major heuristic is, the state machine  204  determines which operating curve to use by applying a digitized value to the current cell  206 , the V2C  108  determines which operating point on the operating curve to use by converting the input voltage V LF  to a current I LF , and the total current (output current of the current cell  206  and I LF ) allows the CCO  110  to function on the operating curve.  
         [0024]     During the initial mode, the charge pump  104  is off, and a default voltage is applied to V LF , for example, ½ VDD, as shown in  FIG. 3 . The state machine generates a sequence of digital control input values N that are input to current cell  206  to sequentially select different current operating curves. The V2C  108  converts the voltage V LF  to a current I LF . The current I LF  and currents from the current cell are added by the current adder  208  and applied to the CCO  110  for determining a most appropriate current operating curve. For each current operating curve, with reference voltage V Ref  applied, CCO  110  generates an output signal F osc  having a constant frequency, and through feedback, the most appropriate current operating curve will eventually be determined and fixed, such that the normal mode is entered.  
         [0025]     In normal mode, the current cell  206  operates on the most appropriate operating curve determined in initial mode, the predetermined voltage ½ VDD is turned off, and the charge pump  104  is turned on to fine tune the most appropriate operating point on the operating curve. In  FIG. 2 , by comparing F Ref  and F Back  in the PFD  102 , an up signal or a down signal is applied to the charge pump  104 , so as to obtain a filtered voltage V LF . The V2C  108  converts the voltage VLF to a current I LF . The current I LF  and currents from the current cell are added by the current adder  208  and applied to the CCO  110  for generating an oscillating signal F osc . In normal mode, when fine tuning, the V LF  may exceed the range from 0 to VDD if the operating curve is inappropriately selected. When this happens, the mode switches back to initial mode, and another operating curve will be reselected, such that the oscillating signal will eventually converge at the wanted frequency, as shown in  FIG. 4   b.    
         [0026]      FIG. 3  shows a detailed block diagram of the charge pump-based loop filter. In initial mode, the current source is disabled by a switch C 1 , no current is output from the charge pump and the voltage V LF  is predetermined at ½ VDD. In another embodiment of the invention, the voltage V LF  can be carefully determined to be another fixed value, depending on the implementation of state machine  204  (in  FIG. 2 ). When in normal mode, the switch C 1  is turned on to enable the current source, and the predetermined voltage ½ VDD is simultaneously disabled. The charge pump  104  is enabled, and outputs the voltage V LF  corresponding to the up signal and down signal generated from PFD  102 .  
         [0027]      FIG. 4   b  shows a plurality of operating curves of the PLL  200 . In one embodiment, an appropriate operating curve (N=2) is first selected in initial mode through cooperation of state machine  204  and current cell  206 . The process is then switched to normal mode, and through feedback, V LF  (which is default to ½ VDD) is shifted causing the operating point to induce the wanted frequency F osc .  
         [0028]     Embodiments of the present invention provide advantages over the PLLs of the related art. Since the current operating curve is automatically fixed to the appropriate curve during power up, there is no need to tune the current cell in the factory. Additionally there is no need to keep an inventory of different current cell for different applications, since each current cell will be automatically leveled to the appropriate operating curve for the particular application. In addition, since the current cell is not permanently burned, the PLL can be used and then re-used for different applications. Each time the PLL is powered up, the current cell will be auto leveled to the appropriate operating curve, and can be repeated whenever needed, such as reset.  
         [0029]     Another advantage of the present invention is that very few additional components need to be added to the conventional design of PLL  100  of  FIG. 1  to achieve the auto-calibrating PLL of the present invention. Although timers and state machines may not already be present in conventional PLLs, because they are low-speed logic, the added cost is negligible compared to the savings.  
         [0030]     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.