Abstract:
A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.

Description:
BACKGROUND  
       [0001]     Digital circuits require a clock signal to operate. Typically, the clock signal is provided by a crystal oscillator and associated circuitry, which usually does not provide a clock signal having a duty cycle of 50%. For example, the clock signal may have a duty cycle of 45%, where the logic high time of the clock signal is 45% of the clock cycle and the logic low time of the clock signal is the remaining 55% of the clock cycle.  
         [0002]     One type of circuit that requires a clock signal to operate is memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and double data rate synchronous dynamic random access memory (DDR-SDRAM). For memory circuits operating at high frequencies, a clock signal having a duty cycle as close to 50% as possible is desired so that the memory has approximately an equal amount of time on both the logic high and logic low portions of the clock signal for transferring data. A duty cycle of 50% allows the maximum amount of time for latching both rising edge data and falling edge data in a memory circuit.  
       SUMMARY  
       [0003]     One embodiment of the invention provides a duty cycle correction circuit. The duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.  
         [0005]      FIG. 1  is a block diagram illustrating one embodiment of a memory system including a duty cycle correction circuit.  
         [0006]      FIG. 2  is a block diagram illustrating one embodiment of a duty cycle correction circuit.  
         [0007]      FIG. 3   a  is a block diagram illustrating one embodiment of a duty restoration circuit.  
         [0008]      FIG. 3   b  is a timing diagram illustrating one embodiment of the timing of signals for the duty restoration circuit.  
         [0009]      FIG. 4  is a block diagram illustrating one embodiment of a correction circuit.  
         [0010]      FIG. 5   a  is a block diagram illustrating one embodiment of an averaging circuit.  
         [0011]      FIG. 5   b  is a schematic diagram illustrating one embodiment of the averaging circuit.  
         [0012]      FIG. 5   c  is a timing diagram illustrating one embodiment of the timing of signals for the averaging circuit.  
         [0013]      FIG. 5   d  is a graph illustrating embodiments of the relationship between the delay between the two inputs to the averaging circuit verses the delay between one input and the output of the averaging circuit.  
         [0014]      FIG. 6  is a timing diagram illustrating one embodiment of the timing of signals for a synchronous mirror delay circuit.  
         [0015]      FIG. 7  is a timing diagram illustrating one embodiment of the timing of signals for the correction circuit.  
         [0016]      FIG. 8  is a timing diagram illustrating one embodiment of a portion of the output signal of the correction circuit.  
         [0017]      FIG. 9  is a graph illustrating one embodiment of a curve of duty cycle percent verses cycle number for the duty cycle correction circuit.  
         [0018]      FIG. 10  is a timing diagram illustrating one embodiment of the timing of signals for the duty cycle correction circuit.  
         [0019]      FIG. 11  is a block diagram illustrating one embodiment of an improved correction circuit.  
         [0020]      FIG. 12  is a graph illustrating one embodiment of a curve of duty cycle percent verses cycle number for the improved correction circuit.  
         [0021]      FIG. 13  is a diagram illustrating one embodiment of an improved duty cycle correction circuit. 
     
    
     DETAILED DESCRIPTION  
       [0022]      FIG. 1  is a block diagram illustrating one embodiment of a memory system  100  including a duty cycle correction circuit. Memory system  100  includes a semiconductor chip  102  and a memory circuit  106 . Semiconductor chip  102  is electrically coupled to memory circuit  106  through communication link  104 . Semiconductor chip  102  includes duty cycle correction circuit  110 . Duty cycle correction circuit  110  is electrically coupled to external clock (CLK EXT ) signal path  112 , inverted external clock (bCLK EXT ) signal path  114 , corrected clock (CLK COR ) signal path  116 , and inverted corrected clock (bCLK COR ) signal path  118 .  
         [0023]     Duty cycle correction circuit  110  receives the CLK EXT  signal on signal path  112  and the bCLK EXT  signal on signal path  114 . The duty cycle of the CLK EXT  signal and the duty cycle of the corresponding bCLK EXT  signal are not 50%. Duty cycle correction circuit  110  corrects the duty cycle by bringing the duty cycle of the CLK EXT  signal and duty cycle of the bCLK EXT  signal closer to a specified duty cycle, such as 50%, by using a synchronous mirror delay circuit. Duty cycle correction circuit  110  outputs the CLK COR  signal on signal path  116  and the bCLK COR  signal on signal path  118 . In one embodiment, duty cycle correction circuit  110  corrects the duty cycle of the clock signal to 50%. The corrected clock signal is used in the operation of memory circuit  106 .  
         [0024]     Memory circuit  106  communicates with chip  102  through communication link  104 . In one embodiment, the CLK COR  signal and the bCLK COR  signal are passed to memory circuit  106  through communication link  104  for use in transferring data between memory circuit  106  and chip  102  or another device. Memory circuit  106  includes a random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR-SDRAM), or other suitable memory. In one embodiment, memory circuit  106  and chip  102  are a single semiconductor chip.  
         [0025]      FIG. 2  is a block diagram illustrating one embodiment of duty cycle correction circuit  110 . Duty cycle correction circuit  110  includes correction circuits  130  and  136  and duty restoration circuits  134  and  140 . The bCLK input of correction circuit  130  is electrically coupled to the CLK input of correction circuit  136  through bCLK EXT  signal path  114 . The CLK input of correction circuit  130  is electrically coupled to the bCLK input of correction circuit  136  through CLK EXT  signal path  112 .  
         [0026]     The output of correction circuit  130  is electrically coupled to input A of duty restoration circuit  134  and input B of duty restoration circuit  140  through clock out (CLK OUT ) signal path  132 . The output of correction circuit  136  is electrically coupled to input B of duty restoration circuit  134  and input A of duty restoration circuit  140  through inverted clock out (bCLK OUT ) signal path  138 . The output of duty restoration circuit  134  is electrically coupled to CLK COR  signal path  116 . The output of duty restoration circuit  140  is electrically coupled to bCLK COR  signal path  118 . In one embodiment, duty restoration circuit  130  or duty restoration circuit  140  is not included in duty cycle correction circuit  110 .  
         [0027]     The bCLK input of correction circuit  130  receives the bCLK EXT  signal on signal path  114  and the CLK input of correction circuit  130  receives the CLK EXT  signal on signal path  112 . Correction circuit  130  outputs the CLK OUT  signal to input A of duty restoration circuit  134  and input B of duty restoration circuit  140  through CLK OUT  signal path  132 . The CLK OUT  signal has a duty cycle closer to 50% than the CLK EXT  signal input into correction circuit  130 .  
         [0028]     The CLK input of correction circuit  136  receives the bCLK EXT  signal on signal path  114  and the bCLK input of correction circuit  136  receives the CLK EXT  signal on signal path  112 . Correction circuit  136  outputs the bCLK OUT  signal to input B of duty restoration circuit  134  and input A of duty restoration circuit  140  through bCLK OUT  signal path  138 . The bCLK OUT  signal has a duty cycle closer to 50% than the bCLK EXT  signal input into correction circuit  136 .  
         [0029]     Input A of duty restoration circuit  134  receives the CLK OUT  signal from correction circuit  130  through signal path  132  and input B of duty restoration circuit  134  receives the bCLK OUT  signal from correction circuit  136  through signal path  138 . Duty restoration circuit  134  outputs the CLK COR  signal on signal path  116  based on the CLK OUT  signal and the bCLK OUT  signal. The CLK COR  signal has a logic high time equivalent to the time between the rising edge of the CLK OUT  signal and the rising edge of the bCLK OUT  signal. The CLK COR  signal has a logic low time equivalent to the time between the rising edge of the bCLK OUT  signal and the rising edge of the CLK OUT  signal.  
         [0030]     Input A of duty restoration circuit  140  receives the bCLK OUT  signal from correction circuit  136  through signal path  138  and input B of duty restoration circuit  140  receives the CLK OUT  signal from correction circuit  130  through signal path  132 . Duty restoration circuit  140  outputs the bCLK COR  signal on signal path  118  based on the bCLK OUT  signal and the CLK OUT  signal. The bCLK COR  signal has a logic high time equivalent to the time between the rising edge of the bCLK OUT  signal and the rising edge of the CLK OUT  signal. The bCLKcoR signal has a logic low time equivalent to the time between the rising edge of the CLK OUT  signal and the rising edge of the bCLK OUT  signal.  
         [0031]     In operation, the CLK COR  signal has the same cycle time as the CLK EXT  signal and a duty cycle closer to 50% than the CLK EXT  signal. The bCLK COR  signal has the same cycle time as the bCLK EXT  signal and a duty cycle closer to 50% than the bCLK EXT  signal.  
         [0032]      FIG. 3   a  is a block diagram illustrating one embodiment of a duty restoration circuit  150 . Duty restoration circuit  150  is similar to duty restoration circuit  134  and duty restoration circuit  140 . Duty restoration circuit  150  includes duty restoration block  156 , input path A  152 , input path B  154 , and output path C  158 .  
         [0033]      FIG. 3   b  is a graph  159  illustrating one embodiment of the timing of signals for duty restoration circuit  150 . Graph  159  illustrates signal A  160  on input path A  152 , signal B  162  on input path B  154 , and signal C  164  on output path C  158 . In response to the rising edge  166  of signal A, signal C  164  transitions to a logic high at  168 . In response to the rising edge  170  of signal B  162 , signal C  164  transitions to a logic low at  172 . The time between the rising edge  168  of signal C  164  and the falling edge  172  of signal C  164  equals the time between the rising edge  166  of signal A  160  and the rising edge  170  of signal B  162 . In response to the next rising edge  174  of signal A  160 , signal C  164  again transitions to a logic high at  176 . The process repeats for each rising edge of signal A  160  and each rising edge of signal B  162 .  
         [0034]      FIG. 4  is a block diagram illustrating one embodiment of a correction circuit  200 . Correction circuit  200  is similar to correction circuit  130 . Correction circuit  200  is similar to correction circuit  136 , except that the bCLK EXT  signal and the CLK EXT  signal inputs are swapped. Correction circuit  200  includes averaging circuits  210  and  214 , duty restoration circuit  204 , delay circuit  213 , and synchronous mirror delay circuit (SMD)  206 . Duty restoration circuit  204  is similar to duty restoration circuit  150 .  
         [0035]     Inputs A and B of averaging circuit  210  are electrically coupled to bCLK EXT  signal path  114 . Inputs A and B of averaging circuit  210  are the bCLK inputs of correction circuits  130  and  136 . Output C of averaging circuit  210  is electrically coupled to input A of duty restoration circuit  204  through delayed inverted clock (DEL_bCLK) signal path  212 . Input A of averaging circuit  214  is electrically coupled to CLK EXT  signal path  112  and input B of averaging circuit  214  is electrically coupled to SMD  206  through synchronous mirror delay output (SMD_OUT) signal path  208 .  
         [0036]     Input A of averaging circuit  210  is the CLK input of correction circuits  130  and  136 . Output C of averaging circuit  214  is electrically coupled to input B of duty restoration circuit  204  through average (AVE) signal path  202 . Output C of duty restoration circuit  204  is electrically coupled to the input of delay circuit  213  and an input of SMD  206  through clock (CLK) signal path  218 . Output C of duty restoration circuit  204  is the output of correction circuits  130  and  136 . The output of delay circuit  213  is electrically coupled to SMD  206  through synchronous mirror delay input (SMD_IN) signal path  216 .  
         [0037]     Inputs A and B of averaging circuit  210  receive the bCLK EXT  signal on signal path  114  and output C of averaging circuit  210  outputs the DEL_bCLK signal to input A of duty restoration circuit  204  through signal path  212 . The DEL_bCLK signal on signal path  212  is a delayed bCLK EXT  signal, where the delay is equal to the delay through averaging circuit  214 .  
         [0038]     Input A of averaging circuit  214  receives the CLK EXT  signal on signal path  112  and input B of averaging circuit  214  receives the SMD_OUT signal from SMD  206  through signal path  208 . Output C of averaging circuit  214  outputs the AVE signal to input B of duty restoration circuit  204  through signal path  202 . The AVE signal has a rising edge between the rising edge of the CLK EXT  signal and the rising edge of the SMD_OUT signal.  
         [0039]     Duty restoration circuit  204  functions similar to duty restoration circuit  150 . Duty restoration circuit  204  receives the DEL_bCLK signal on signal path  212  and the AVE signal on signal path  202  and outputs the CLK signal to delay circuit  213  and SMD  206  through signal path  218 . The CLK signal has a logic high time equal to the time between the rising edge of the DEL_bCLK signal and the rising edge of the AVE signal.  
         [0040]     Delay circuit  213  receives the CLK signal and delays the CLK signal to compensate for the delay through averaging circuit  214  and the delay through duty restoration circuit  204 . Delay circuit  213  outputs the delayed CLK signal, SMD_IN, to SMD  206  through signal path  216 .  
         [0041]     SMD  206  receives the CLK signal and the SMD_IN signal and outputs the SMD_OUT signal to input B of averaging circuit  214 . The SMD_OUT signal has a rising edge a logic high time of the CLK signal after the falling edge of the CLK signal, as will be described in further detail with respect to  FIG. 6 .  
         [0042]      FIG. 5   a  is a block diagram illustrating one embodiment of an averaging circuit  220 . Averaging circuit  220  is similar to averaging circuit  210  and averaging circuit  214 . Averaging circuit  220  includes average circuit  226 , input path A  222 , input path B  224 , and output path C  228 .  
         [0043]      FIG. 5   b  is a schematic diagram illustrating averaging circuit  220  in more detail. Averaging circuit  220  includes inverters  230 ,  234 , and  236 . The input of inverter  230  is electrically coupled to input path A  222  and the output of inverter  230  is electrically coupled to the input of inverter  236  and the output of inverter  234  through path  232 . The input of inverter  234  is electrically coupled to input path B  224 . The output of inverter  236  is electrically coupled to output path C  228 .  
         [0044]      FIG. 5   c  is a timing diagram  240  illustrating one embodiment of the timing of signals for averaging circuit  220 . Timing diagram  240  includes signal A  242  on input path A  222 , signal B  244  on input path B  224 , and signal C  246  on output path C  228 . Signal C  246  has a rising edge  248  between a rising edge  250  of signal A  242  and a rising edge  252  of signal B  244 . The time between the rising edge  250  of signal A  242  and the rising edge  248  of signal C  246  is indicated at  254 . The time between the rising edge  250  of signal A  242  and the rising edge  252  of signal B  244  is indicated at  256 . In one embodiment, the rising edge of signal B  244  leads the rising edge of signal A  242 .  
         [0045]      FIG. 5   d  is a graph  260  illustrating three embodiments of the relationship between the time  256  verses the time  254  for averaging circuit  220 . The x-axis  256  is the absolute value of the time between the rising edge  250  of signal A  242  and the rising edge  252  of signal B  244  (TIME(A-B)). The y-axis  254  is the time between the rising edge  250  of signal A  242  and the rising edge  248  of signal C  246  (TIME(A-C)). The time  254  is a function of the time  256  based on the design of averaging circuit  220 . The function is defined as: 
 TIME( A−C )=[TIME( A−B )] X   Equation I         where X is slope of a curve in graph  260 .          
         [0047]     Curves  262   a ,  262   b , and  262   c  represent three ideal functions for averaging circuit  220  with no delay between input path A  222 , input path B  224 , and output path C  228 . In this case, X=0.4 for curve  262   a , X=0.5 for curve  262   b , and X=0.6 for curve  262   c.    
         [0048]     Curves  266   a ,  266   b , and  266   c  represent three non-ideal functions for averaging circuit  220  and account for a delay between input path A  222 , input path B  224 , and output path C  228 , indicated at  272 . In this case, X=0.4 for curve  266   a , X=0.5 for curve  166   b , and X=0.6 for curve  266   c . Averaging circuit  220  acts as an ideal averaging circuit if TIME(A-B) is low, as indicated at  268 . As TIME(A-B) increases, however, averaging circuit  220  does not act ideally, as indicated at  270 . Averaging circuit  220  is designed based on the frequency of the clock signal that is going to be corrected and the desired amount of duty cycle correction. In one embodiment, where the rising edge of signal B  244  leads the rising edge of signal A  242 , TIME(A-C) is replaced with the time between the rising edge of signal B  244  and the rising edge of signal C  246  (TIME(B-C)).  
         [0049]      FIG. 6  is a timing diagram  280  illustrating one embodiment of the timing of signals for synchronous mirror delay circuit  206 . Timing diagram  280  includes CLK signal  292  on signal path  218 , SMD_IN signal  294  on signal path  216 , and SMD_OUT signal  296  on signal path  208 . The CLK signal  292  is delayed through delay circuit  213  to provide the SMD_IN signal  294  delayed as indicated at  282 . The SMD_OUT signal  296  has a rising edge  288  at a time that is equal to the time of the CLK signal  292  at the falling edge  284  plus the time between the rising edge  298  of the SMD_IN signal  294  and the falling edge  284  of CLK signal  292  as indicated at  286 . The time  286  is equivalent to the time indicated at  290 . This process is repeated for each cycle of CLK signal  292 .  
         [0050]      FIG. 7  is a timing diagram  300  illustrating one embodiment of the timing of signals for correction circuit  200 . Timing diagram  300  includes CLK EXT  signal  302  on signal path  112 , bCLK EXT  signal  304  on signal path  114 , DEL_bCLK signal  306  on signal path  212 , SMD_OUT signal  296  on signal path  208 , AVG signal  308  on signal path  202 , CLK signal  292  on signal path  218 , and SMD_IN signal  294  on signal path  216 .  
         [0051]     The DEL_bCLK signal  306  is generated through averaging circuit  210  from bCLK EXT  signal  304 . The first rising edge  314  of AVE signal  308  is generated from the rising edge  312  of CLK EXT  signal  302 . The rising edge  314  of AVE signal  308  generates the rising edge  310  of CLK signal  292  through duty restoration circuit  204 . The rising edge  310  of CLK signal  292  generates the rising edge  316  of SMD Equation I IN signal  294  through delay circuit  213 . The falling edge  324  of CLK signal  292  is generated through duty restoration circuit  204  from the rising edge  332  of DEL_bCLK signal  306 .  
         [0052]     The rising edge  318  of SMD_OUT signal  296  occurs after a time  322  from the falling edge  324  of CLK signal  292 . Time  322  is equal to time  320 , which is the time between the rising edge  316  of SMD_IN signal  294  and the falling edge  324  of CLK signal  292 . From the rising edge  318  of SMD_OUT signal  296  and the rising edge  326  of CLK EXT  signal  302 , averaging circuit  214  generates a rising edge  328  of AVE signal  308 . The rising edge  328  of AVE signal  308  generates rising edge  330  of CLK signal  292  through duty restoration circuit  204 . The process repeats for each cycle of CLK EXT  signal  302 .  
         [0053]      FIG. 8  is a timing diagram  400  illustrating one embodiment of a portion of CLK signal  292 . CLK signal  292  includes logic high time portion TH n−1    402 , logic high time portion TH n    406 , time between the rising edge of SMD Equation I OUT signal  296  and the rising edge of CLK EXT  signal  302  indicated as Dn  404 , time between the rising edge of SMD_OUT signal  296  and the rising edge of CLK signal  292  indicated as C n    408 , and time between the rising edge of CLK signal  292  and the rising edge of CLK EXT  signal  302  indicated as Rn  410 . The “n” indicates the cycle number for CLK signal  292 . The relationships for TH n−1 , TH n , D n , C n , and R n  are as follows: 
   D   n =( T   cyc −2· TH   n−1 )  Equation II    C   n=X·D   n   Equation III    R   n=   D   n   −C   n   Equation IV    TH   n   =δ·T   cyc   +R   n   Equation V         where T cyc  is the cycle time of CLK EXT  signal  302 , δ is the duty cycle of CLK EXT  signal  302 , and X is the slope of a curve in graph  260  for averaging circuit  220 . For example, for a CLK EXT  signal with a duty cycle of 40%, δ=0.4, and X=0.4, CLK signal  292  results in: TH 0 =0.4·T cyc , TH 1 =0.52·T cyc , TH 2 =0.448·T cyc , TH 3 =0.4912·T cyc , TH 4 =0.46528·T cyc , TH 5 =0.4803·T cyc , TH 6 =0.4718·T cyc , etc.          
         [0055]      FIG. 9  is a graph  430  illustrating one embodiment of a curve  436  of duty cycle percent  432  verses cycle number  434 . Graph  430  indicates the duty cycle of CLK signal  292  after applying Equations II-V. The duty cycle percent  432  of curve  436  oscillates around a center point  438  as the cycle number increases. After several cycles, curve  436  reaches a steady state based on the duty cycle of CLK EXT  signal  302 , the value of X for averaging circuit  220 , and the final value of R n . The final value of R n  is designated as β. The value for β is calculated as follows:  
             β   =       (     1   -     2   ·   δ       )     ·     (       1   -   X       2   -   X       )               Equation   ⁢           ⁢   VI               
         [0056]     Using Equations II-VI, the final amount of duty cycle correction can be determined. For example, for a CLK EXT  signal with a duty cycle of 40%, 6=0.4, and an averaging circuit with X=0.6, the duty cycle of the CLK EXT  signal can be corrected to 45.7%. The corresponding bCLK EXT  signal with a duty cycle of 60%, 6=0.6, and an averaging circuit with X=0.6 can be corrected to 54.3%.  
         [0057]      FIG. 10  is a timing diagram  450  illustrating one embodiment of the timing of signals for duty cycle correction circuit  110 . Timing diagram  450  includes CLK EXT  signal  302  on signal path  112 , CLK OUT  signal  452  on signal path  132 , bCLK EXT  signal  304  on signal path  114 , bCLK oUT  signal  454  on signal path  138 , and CLK COR  signal  456  on signal path  116 . For this embodiment, X=0.6 for the averaging circuit of correction circuit  130  and the averaging circuit of correction circuit  136 . The duty cycle of CLK EXT  signal  302  is 40% and the corresponding duty cycle of bCLK EXT  signal  304  is 60%.  
         [0058]     The CLK EXT  signal  302  having a duty cycle of 40% is corrected to generate CLK OUT  signal  452  having a duty cycle of 45.7% through correction circuit  130 . The bCLK EXT  signal  304  having a duty cycle of 60% is corrected to generate bCLK OUT  signal  454  having a duty cycle of 54.3% through correction circuit  136 . The rising edge  458  of CLK OUT  signal  452  generates the rising edge  460  of CLK COR  signal  456  through duty restoration circuit  134 . The rising edge  462  of bCLK OUT  signal  454  generates the falling edge  464  of CLK COR  signal  456  through duty restoration circuit  134 . The process repeats for each cycle of CLK EXT  signal  302 . The duty cycle of CLK COR  signal  456  is 50%.  
         [0059]      FIG. 11  is a block diagram illustrating one embodiment of an improved correction circuit  500 . Improved correction circuit  500  can be used in place of correction circuit  130 . Improved correction circuit  500  can be used in place of correction circuit  136  by swapping the bCLK EXT  signal and CLK EXT  signal inputs. Improved correction circuit  500  includes correction circuits  502  and  504  and averaging circuit  510 . Correction circuit  502  and correction circuit  504  are similar to correction circuit  200 . Averaging circuit  510  is similar to averaging circuit  220 .  
         [0060]     The bCLK input of correction circuit  502  is electrically coupled to bCLK EXT  signal path  114  and the CLK input of correction circuit  502  is electrically coupled to CLK EXT  signal path  112 . The output of correction circuit  502  is electrically coupled to input A of averaging circuit  510  through CLK OUT  signal path  506 . The bCLK input of correction circuit  504  is electrically coupled to bCLK EXT  signal path  114  and the CLK input of correction circuit  504  is electrically coupled to CLK EXT  signal path  112 . The output of correction circuit  504  is electrically coupled to input B of averaging circuit  510  through CLK 2 OUT signal path  508 . The output of averaging circuit  510  is electrically coupled to signal path  512 .  
         [0061]     Correction circuit  504  is enabled one clock cycle after correction circuit  502 . The CLK EXT  signal is duty cycle corrected by correction circuit  502  to output the CLK 1OUT  signal to averaging circuit  510  through signal path  506 . The CLK EXT  signal is also duty cycle corrected by correction circuit  504  to output the CLK 2 OUT signal to averaging circuit  510  through signal path  508 . The CLK 2 OUT signal is similar to the CLK OUT  signal, but is delayed one clock cycle to the CLK 1OUT  signal. The CLK 1OUT  signal and the CLK 2OUT  signal are averaged by averaging circuit  510 . Averaging circuit  510  outputs a corrected clock signal on signal path  512 . Improved correction circuit  500  can be used in place of correction circuit  136  to correct the duty cycle of the bCLK EXT  signal by swapping the bCLK EXT  signal and CLK EXT  signal inputs.  
         [0062]      FIG. 12  illustrates a graph  550  illustrating one embodiment of a curve  560  of duty cycle percent  552  verses cycle number  554  for improved correction circuit  500 . Curve  556  indicates the duty cycle  552  of the CLK 1OUT  signal on signal path  506 . Curve  556  oscillates around a center point  562 , such as 50%. Curve  558  indicates the duty cycle  552  of the CLK 2OUT  signal on signal path  508 . Curve  558  also oscillates around center point  562 . Curve  558  is similar to curve  556  but is delayed by one clock cycle. Curve  560  indicates the duty cycle  552  of the output signal of averaging circuit  510  on signal path  512 . Curve  560  is close to the center point  562 . Improved correction circuit  500  results in less jitter in the output signal on signal path  512 .  
         [0063]      FIG. 13  is a block diagram illustrating one embodiment of an improved duty cycle correction circuit  600 . Improved duty cycle correction circuit  600  includes duty cycle correction circuits  110   a  and  110   b . Duty cycle correction circuits  110   a  and  110   b  are similar to duty cycle correction circuit  110 .  
         [0064]     The bCLK input of duty cycle correction circuit  110   a  is electrically coupled to bCLK EXT  signal path  114  and the CLK input of duty cycle correction circuit  110   a  is electrically coupled to CLK EXT  signal path  112 . The CLKCOR output of duty cycle correction circuit  110   a  is electrically coupled to the bCLK input of duty cycle correction circuit  110   b  through signal path  602 . The bCLK COR  output of duty cycle correction circuit  110   a  is electrically coupled to the CLK input of duty cycle correction circuit  110   b  through signal path  604 . The CLK COR  output of duty cycle correction circuit  110   b  is electrically coupled to CLK COR  signal path  116  and the bCLK COR  output of duty cycle correction circuit  110   b  is electrically coupled to bCLK COR  signal path  118 .  
         [0065]     Any suitable number of duty cycle correction circuits  110  can be coupled together as duty cycle correction circuit  110   a  and duty cycle correction circuit  110   b  to provide an improved duty cycle correction circuit. Each successive duty cycle correction circuit  110  further improves on the duty cycle correction of the previous duty cycle correction circuit  110 .