Abstract:
A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

Description:
REFERENCE TO PRIORITY APPLICATION  
       [0001]     This application claims priority to Korean Application Nos. 2005-63391, filed Jul. 13, 2005, and 2005-83981, filed Sep. 9, 2005, the disclosures of which are hereby incorporated herein by reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to integrated circuit memory devices and, more particularly, to nonvolatile memory devices and methods of fabricating nonvolatile memory devices.  
       BACKGROUND OF THE INVENTION  
       [0003]     One class of nonvolatile memory devices includes electrically erasable programmable read only memory (EEPROM), which may be used in many applications including embedded applications and mass storage applications. In typical embedded applications, an EEPROM device may be used to provide code storage in personal computers or mobile phones, for example, where fast random access read times may be required. Typical mass storage applications include memory card applications requiring high capacity and low cost.  
         [0004]     One category of EEPROM devices includes NAND-type flash memories, which can provide a low cost and high capacity alternative to other forms of nonvolatile memory. A typical NAND-type flash memory includes a plurality of NAND-type strings therein that are disposed side-by-side in a semiconductor substrate. Each of these NAND-type strings may be associated with respective bit lines that are connected to a page buffer. In some cases, the NAND-type strings may be configured to provide byte-erase capability in addition to a more conventional block erase capability. Examples of byte-erasable EEPROM memory devices are disclosed in U.S. Pat. No. 7,006,381 to Dormans et al. and in an article entitled “Device Architecture and Reliability Aspects of a Novel 1.22 um 2  EEPROM cell in 0.18 um Node for Embedded Application,” Microelectronics Engineering 72, pp. 415-420 (2004).  
         [0005]     Each EEPROM cell within a NAND-type string includes a floating gate electrode and a control gate electrode, which is electrically connected to a respective word line. These EEPROM cells may be cells that support a single or a multi-level programmed state. EEPROM cells that support only a single programmed state are typically referred to as single level cells (SLC). In particular, an SLC may support an erased state, which may be treated as a logic 1 storage value, and a programmed state, which may be treated as a logic 0 storage value. The SLC may have a negative threshold voltage (Vth) when erased (e.g., −3V&lt;Vth&lt;−1V) and a positive threshold voltage when programmed (e.g., 1V&lt;Vth&lt;3V). This programmed state may be achieved by setting a corresponding bit line to a logic 0 value (e.g., 0 Volts), applying a program voltage (Vpgm) to a selected EEPROM cell and applying a pass voltage (Vpass) to the unselected EEPROM cells within a string.  
         [0006]     The programmed state or erased state of an EEPROM cell may be detected by performing a read operation on a selected cell. As will be understood by those skilled in the art, a NAND string will operate to discharge a precharged bit line BL when a selected cell is in an erased state and a selected word line voltage (e.g., 0 Volts) is greater than the threshold voltage of the selected cell. However, when a selected cell is in a programmed state, the corresponding NAND string will provide an open circuit to the precharged bit line because the selected word line voltage (e.g., 0 Volts) is less than the threshold voltage of the selected cell and the selected cell remains “off”. Other aspects of NAND-type flash memories are disclosed in U.S. application Ser. No. 11/358,648, filed Feb. 21, 2006, and in an article by Jung et al., entitled “A 3.3 Volt Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1748-1757, November (1997), the disclosures of which are hereby incorporated herein by reference.  
       SUMMARY OF THE INVENTION  
       [0007]     Embodiments of the invention including nonvolatile memory devices having byte-erase capability. These memory device include a byte-erasable EEPROM memory array that is configured to support independent erasure of first and second pluralities of EEPROM memory cells that share a first semiconductor well region within a substrate and are electrically coupled by first and second byte selection transistors, respectively, to a global control line. This byte-erasable EEPROM memory array further includes a first local control line, which is electrically coupled to control electrodes of the first plurality of EEPROM cells and a first current carrying terminal of the first byte selection transistor, and a second local control line, which is electrically coupled to control electrodes of the second plurality of EEPROM cells and a first current carrying terminal of the second byte selection transistor. This first and second local control lines may be collinear and extend across the first semiconductor well region.  
         [0008]     According to additional aspects of these nonvolatile memory devices, the first semiconductor well region is a region of first conductivity type (e.g., P-type) and the first byte selection transistor is formed within a second semiconductor well region of second conductivity type (e.g., N-type) that forms a P-N rectifying junction with the first semiconductor well region of first conductivity type. Each of the first and second pluralities of EEPROM memory cells can be a 2T or 3T EEPROM cell. A 2T EEPROM cell can include an NMOS transistor and a EEPROM transistor connected in series and a 3T EEPROM cell can include a pair of NMOS transistors and an EEPROM transistor connected in series. According to still further aspects of these embodiments, the first and second pluralities of EEPROM memory cells may share a common source line that extends across the first semiconductor well region. This common source line may include a common source line diffusion region of second conductivity type that is formed within the first semiconductor well region using selective dopant implantation and drive-in/diffusion steps.  
         [0009]     According to still further embodiments of the invention, a nonvolatile memory device is provided that includes a semiconductor well region of first conductivity type on a semiconductor substrate and a byte-erasable EEPROM memory array in the semiconductor well region. The byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that share a ground selection line extending opposite the semiconductor well region. The first and second pluralities of EEPROM memory cells include EEPROM transistors having channel regions of first conductivity type that form non-rectifying junctions with the semiconductor well region.  
         [0010]     Additional embodiments of the invention include a semiconductor well region of first conductivity type on a semiconductor substrate. This semiconductor well region includes a common source diffusion region of second conductivity type therein that forms a P-N rectifying junction with the semiconductor well region. A byte-erasable EEPROM memory array is provided in the semiconductor well region. The byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is an electrical schematic of a byte-erasable EEPROM memory device according to an embodiment of the present invention.  
         [0012]      FIG. 2A  is an electrical schematic of a portion of the EEPROM memory device of  FIG. 1  that highlights the state of applied voltages during a byte program operation.  
         [0013]      FIG. 2B  is an electrical schematic of a portion of the EEPROM memory device of  FIG. 1  that highlights the state of applied voltages during a byte erase operation.  
         [0014]      FIG. 2C  is an electrical schematic of a portion of the EEPROM memory device of  FIG. 1  that highlights the state of applied voltages during a byte read operation.  
         [0015]      FIG. 3  is an electrical schematic of a byte-erasable EEPROM memory device according to another embodiment of the present invention.  
         [0016]      FIG. 4A  is an electrical schematic of a portion of the EEPROM memory device of  FIG. 3  that highlights the state of applied voltages during a byte program operation.  
         [0017]      FIG. 4B  is an electrical schematic of a portion of the EEPROM memory device of  FIG. 3  that highlights the state of applied voltages during a byte erase operation.  
         [0018]      FIG. 5  is a layout schematic that illustrates a portion of the byte-erasable EEPROM memory device of  FIG. 3 .  
         [0019]      FIG. 6A  is an enlarged layout schematic of a byte-erasable EEPROM memory device that illustrates a central portion of the layout schematic of  FIG. 5 , which is highlighted with dotted lines as region A.  
         [0020]      FIG. 6B  is a cross-sectional view of the EEPROM memory device of  FIG. 6A , taken along line  6 B- 6 B′ in  FIG. 6A .  
         [0021]      FIG. 6C  is a cross-sectional view of the EEPROM memory device of  FIG. 8A , taken along line  6 C- 6 C′ in  FIG. 6A .  
         [0022]      FIG. 7A  is an enlarged layout schematic of a byte-erasable EEPROM memory device that illustrates a left-side portion of the layout schematic of  FIG. 5 , which is highlighted with dotted lines as region B.  
         [0023]      FIG. 7B  is a cross-sectional view of the EEPROM memory device of  FIG. 7A , taken along line  7 B- 7 B′ in  FIG. 7A .  
         [0024]      FIG. 7C  is a cross-sectional view of the EEPROM memory device of  FIG. 7A , taken along line  7 C- 7 C′ in  FIG. 7A . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0025]     The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters. Signals may also be synchronized and/or undergo minor boolean operations (e.g., inversion) without being considered different signals.  
         [0026]     Referring now to  FIG. 1 , a byte-erasable electrically erasable programmable read only memory (EEPROM)  10  according to first embodiments of the present invention is illustrated as including first and second arrays of EEPROM cells. The first and second arrays are illustrated as being formed in first and second P-well semiconductor regions, respectively. The first P-well region is identified by the reference numeral  15  and the second P-well region is identified by the reference numeral  17 . Both of these P-well regions are illustrated as being formed within a larger N-well region, which is identified by the reference numeral  13 . The N-well region  13  is formed within a bulk semiconductor substrate (not shown). This semiconductor substrate may be an integrated circuit chip in some embodiments of the invention.  
         [0027]     The EEPROM cells within the first and second arrays are three-transistor (3T) cells. Each of these 3T cells includes two NMOS transistors and one EEPROM transistor, connected as illustrated. In particular, each of the first and second arrays is illustrated as supporting a corresponding pair of 8×8 sub-arrays of EEPROM cells. The sixteen EEPROM transistors in row 1 of the first array are identified by the reference characters MCT 1 _ 1 , MCT 1 _ 2 , . . . , MCT 1 _ 16 , where “MCT” designates “memory cell transistor.” The 8×8 sub-array on the left side of the first array spans columns 1-8, corresponding to bit lines BL 0 -BL 7 , and spans rows 1-8, corresponding to local control lines LCL 1 _ 1 , LCL 2 _ 1 , . . . , LCL 8 _ 1 . The 8×8 sub-array on the right side of the first array spans columns 9-16, corresponding to bit lines BL 8 - 15 , and spans rows 1-8, corresponding to local control lines LCL 1 _ 2 , LCL 2 _ 2 , . . . , LCL 8 _ 2 . Similarly, the 8×8 sub-array on the left side of the second array spans columns 17-24, corresponding to bit lines BL 16 - 23 , and spans rows 1-8, corresponding to local control lines LCL 1 _ 3 , LCL 2 _ 3 , . . . , LCL 8 _ 3 . The 8×8 sub-array on the right side of the second array spans columns 25-32, corresponding to bit lines BL 24 - 31 , and spans rows 1-8, corresponding to local control lines LCL 1 _ 4 , LCL 2 _ 4 , . . . , LCL 8 _ 4 .  
         [0028]     The eight rows of EEPROM cells that span the first and second arrays are paired in groups so that rows 1-2 are electrically coupled to common source line CSL 0 , rows 3-4 are electrically coupled to common source line CSL 1 , rows 5-6 are electrically coupled to common source line CSL 2 , and rows 7-8 are electrically coupled to common source line CSL 3 , as illustrated. Moreover, the EEPROM cells in rows 1-8 are electrically coupled corresponding string selection lines SSL 0 -SSL 7  and ground selection lines GSL 0 -GSL 7 , as illustrated. The local control lines LCL 1 _ 1 , LCL 1 _ 2 , LCL 1 _ 3  and LCL 1 _ 4  are electrically coupled to terminals of corresponding byte selection transistors BST 1 _ 1 , BST 1 _ 2 , BST 1 _ 3  and BST 1 _ 4 , respectively, which have gate terminals electrically coupled to corresponding byte selection lines BSL 0 -BSL 3 . Each of these byte selection transistors BST 1 _ 1 , BST 1 _ 2 , BST 1 _ 3  and BST 1 _ 4  is electrically coupled to a corresponding global control line GCL 0 . Similarly, the local control lines LCL 2 _ 1 , LCL 2 _ 2 , LCL 2 _ 3  and LCL 2 _ 4  are electrically coupled to terminals of corresponding byte selection transistors BST 2 _ 1 , BST 2 _ 2 , BST 2 _ 3  and BST 2 _ 4 , respectively. Each of these byte selection transistors BST 2 _ 1 , ST 2 _ 2 , BST 2 _ 3  and BST 2 _ 4  is electrically coupled to a corresponding global control line GCL 1 . The local control lines, byte selection transistors and global control lines associated with rows 3-7 (not shown) are configured in a similar manner. Finally, the local control lines LCL 8 _ 1 , LCL 8 _ 2 , LCL 8 _ 3  and LCL 8 _ 4  are electrically coupled to corresponding byte selection transistors BST 8 _ 1 , BST 8 _ 2 , BST 8 _ 3  and BST 8 _ 4 , respectively. Each of these byte selection transistors BST 8 _ 1 , BST 8 _ 2 , BST 8 _ 3  and BST 8 _ 4  is electrically coupled to a corresponding global control line GCL 7 .  
         [0029]     Operation of the byte-erasable EEPROM  10  of  FIG. 1  will now be described more fully with respect to  FIGS. 2A-2C . In particular,  FIG. 2A  illustrates an operation to program the EEPROM transistor MCT 1 _ 1  illustrated in  FIG. 1 . In  FIG. 2A , the EEPROM transistor MCT 1 _ 1  is within a 3T EEPROM cell, which is designated by the reference label “A”. As illustrated by the right side of  FIG. 2A , programming cell “A” can be achieved by establishing a voltage difference of 18 Volts between a channel region (at −8 Volts) and a control electrode (at +10 Volts) of the corresponding EEPROM transistor MCT 1 _ 1 . The channel region is held at −8 Volts by setting the first P-well region  15  to a voltage of −8 Volts. The control electrode is electrically connected to the corresponding local control line, which is shown as LCL 1 _ 1  in  FIG. 1 . The local control line LCL 1 _ 1  is set to a +10 Volt level by turning on the PMOS byte selection transistor BST 1 _ 1  using a 0 Volt gate voltage (BSL 0 =0 Volts) and setting the N-well region  13  to +10 Volts. Turning on the byte selection transistor BST 1 _ 1  will cause the local control line LCL 1 _ 1  to be biased at the same voltage as the global control line GCL 0  (i.e., +10 Volts). The source terminal of the selected EEPROM transistor MCT 1 _ 1  (within cell “A”) is set to a “floating” condition (F) by driving the ground selection line GSL 0  at a voltage of −8 Volts. The drain terminal of the EEPROM transistor MCT 1 _ 1  is set to a voltage of −8 Volts by driving the bit line BL 0  at a voltage of −8 Volts and turning on the corresponding NMOS string selection transistor by setting the string selection line SSL 0  to −5 Volts (to thereby establish a gate-to-channel voltage of +3 Volts in the NMOS string selection transistor).  
         [0030]     The EEPROM transistor MCT 1 _ 8 , which is designated by the reference label “B”, is maintained in a program inhibited state by holding the source and drain terminals of the transistor MCT 1 _ 8  in a floating condition (F) to thereby prevent the 18 Volt difference between the control electrode and the channel region (i.e., P-well region  15 ) from charging the floating gate electrode extending therebetween. These floating conditions are achieved by holding the gate-to-channel voltages in the corresponding string selection and ground selection transistors at 0 Volts (GSL 0 =−8 Volts and P-well  15 =−8 Volts; SSL 0 =−5 Volts and BL 7 =floating).  
         [0031]     The bit lines BL 8 -BL 15  and the local control line LCL 1 _ 2  are also held in floating conditions to thereby prevent the EEPROM transistors MCT 1 _ 9 -MCT 1 _ 16 , which are designated by reference label “C”, from being programmed. As illustrated, the local control line LCL 1 _ 2  may be held in a floating condition by holding the byte selection transistor BST 1 _ 2  in an “off” condition to thereby prevent the high voltage on the global control line GCL 0  from being passed to the local control line LCL 1 _ 2 . Thus, the byte of EEPROM cells designated by the reference label “C” can be independently programmed relative to the EEPROM cells designated by the reference labels “A” and “B”. The bit lines BL 16 -BL 23  and the local control lines LCL 1 _ 3 , LCL 2 _ 3 , . . . , LCL 8 _ 3  may also be held in floating conditions to thereby prevent the EEPROM transistors in the second P-well region  17 , which are designated by reference label “F”, from being programmed. Finally, the unselected byte of EEPROM transistors designated by the reference labels “D” and “E” may be disposed in a program inhibited condition by holding the global control line GCL 1  in a floating condition or biasing it at a negative voltage (e.g., −5 Volts), which is passed to the local control line LCL 2 _ 1  via the byte selection transistor BST 2 _ 1 .  
         [0032]      FIGS. 1 and 2 B illustrate operations to erase the byte of EEPROM transistors MCT 1 _ 1 -MCT 1 _ 8  independently of erasing the other byte of EEPROM transistors MCT 1 _ 9 -MCT 1 _ 16  located within the same P-well region  15 . In particular,  FIG. 2B  identifies the EEPROM transistors MCT 1 _ 1 -MCT 1 _ 8  by the reference labels “A” and identifies EEPROM transistors MCT 1 _ 9 -MCT 1 _ 16  by the reference labels “B”. As shown on the right side of  FIG. 2B , the EEPROM transistors in group “A” can be “byte-erased” by establishing an 18 Volt potential from the control electrode (−8 Volts) to the channel region (+10 Volts), which is shown as the first P-well region  15 . The −8 Volt potential is established on the control electrodes by driving the local control line LCL 1 _ 1  from a global control line GCL 0  that is biased at −8 Volts and by turning on the PMOS byte selection transistor BST 1 _ 1 . In contrast, the EEPROM transistors in group “B” do not undergo a byte erase operation because the control electrodes for these transistors are held in a floating condition (F) by virtue of the fact that the corresponding byte selection line BSL 1  is held at +10 Volts to thereby turn off the byte selection transistor BST 1 _ 2 .  
         [0033]     In addition, The EEPROM transistors identified by the reference labels “C”, which are also located within the first P-well region  15 , do not undergo an erase operation because the corresponding global control line GCL 1  (and local control line LCL 2 _ 1 ) is driven at a potential of +5 Volts (or floated). Thus, as illustrated by the right side of  FIG. 2B , for the case of the EEPROM transistors within group “C”, only a 5 Volt potential is established between the corresponding control electrodes (at +5 Volts) and the corresponding channel regions (at +10 Volts). Finally, the EEPROM transistors identified by the labels “D” and “E” are precluded from undergoing an erase operation by virtue of the fact that the corresponding byte selection line BSL 2  is held at +10 Volts, thereby turning off the byte selection transistors BST 1 _ 3 , . . . , BST 8 _ 3 , and the second P-well  17  is held at 0 Volts.  
         [0034]      FIGS. 1 and 2 C illustrate bias conditions that support operations to read an 8-bit byte of data from the EEPROM transistors MCT 1 _ 1 -MCT 1 _ 8 , which are identified by the reference label “A”. These bias conditions also preclude reading of data from the other EEPROM transistors located within the N-well  13 . As shown by  FIG. 2C , the eight bit lines BL 0 -BL 7  are initially precharged to a positive precharge voltage (Vpre) and then a positive global control line voltage (Vcc) is applied to the global control line GCL 0 . This positive voltage of Vcc is passed from the global control line GCL 0  to the corresponding local control line associated with the group A EEPROM transistors by turning on the byte selection transistor BST 1 _ 1 . The byte selection transistor BST 1 _ 1  may be turned on by biasing the N-well region  13  at a positive voltage (shown as Vcc) and setting the byte selection line BSL 0  at 0 Volts to thereby establish a negative gate-to-channel voltage across the byte selection transistor BST 1 _ 1 . In addition, the NMOS string selection transistors and NMOS ground selection transistors for the group “A” EEPROM transistors are enabled to support a read operation by driving the string selection line SSL 0  and GSL 0  at a positive voltage (Vcc), which establishes a positive gate-to-channel voltage relative to the P-well region  15 . In response to these applied voltages, a bit line sense amplifier (not shown) will evaluate changes in the voltages of the initially precharged bit lines BL 0 -BL 7  to determine the states (programmed (cell data  0 ) or erased (cell data=1)) of the group “A” EEPROM transistors.  
         [0035]     Referring now to  FIG. 3 , a byte-erasable electrically erasable programmable read only memory (EEPROM)  10 ′ according to a second embodiment of the present invention is illustrated as including two-transistor (2T) EEPROM cells. Each of these 2T cells includes one NMOS transistor and one EEPROM transistor, connected as illustrated. In contrast to the EEPROM  10  of  FIGS. 1 and 2 A- 2 C, the EEPROM  10 ′ of  FIG. 3  does not include any NMOS string selection transistors or string selection lines. Otherwise, the EEPROM  10 ′ of  FIG. 3  is equivalent to the EEPROM  10  of  FIG. 1 .  
         [0036]     Operation of the EEPROM  10 ′ during programming and erasing will now be described more fully with respect to  FIGS. 3 and 4 A- 4 B. In particular,  FIG. 4A  illustrates the bias conditions necessary to program the EEPROM transistor highlighted with the reference label “A”. As illustrated on the right side of  FIG. 4A , these bias conditions include establishing an 18 Volt potential from the channel region to the control electrode of the EEPROM transistor “A” and biasing the corresponding bit line BSL 0  at −8 Volts. The channel region is set to a −8 Volt potential by setting the voltage of the first P-well  15  at −8 Volts. The control electrode is set to a potential of +10 Volts by driving the global control line GCL 0  at +10 Volts and turning on the byte selection transistor BST 1 _ 1  by setting the byte selection line BSL 0  to 0 Volts while the N-well region  13  is biased at +10 Volts. In contrast, the EEPROM transistor highlighted with the reference label “B” is maintained in its initially erased state by setting the corresponding bit line BL 7  to a positive power supply voltage (e.g., Vcc). Thus, as illustrated by the right side of  FIG. 4A , the EEPROM transistor “B” does not undergo a program operation because both the control electrode and drain terminal are held at positive voltages (e.g., 10 Volts and Vcc). Similarly, the EEPROM transistor highlighted with the reference label “C” is precluded from undergoing a program operation by driving its control electrode at 0 Volts. This is achieved by driving the global control line GCL 1  at 0 Volts and turning on the byte selection transistor BST 2 _ 1 . The EEPROM transistor “D” within the first P-well region  15  and the EEPROM transistor “E” within the second P-well region  17  are similarly precluded from undergoing program operations by driving their corresponding bit lines (BL 8  and BL 16 ) at positive voltages (Vcc) and driving their corresponding control electrodes at 0 Volts (LCL 1 _ 2 =0 Volts and LCl_ 3 =0 Volts). Thus, as illustrated by  FIG. 4A , bias conditions that support programming may be modified relative to the bias conditions of  FIG. 2A  in order to account for a reduction in EEPROM cell size (i.e., reduction from 3T cell to 2T cell).  
         [0037]      FIG. 4B  illustrates bias conditions that support operations to erase one byte of EEPROM cells, shown by reference label “A”, but avoid erasure of other bytes of EEPROM cells located within the same P-well region  15  (reference labels “B” and “C”) and an adjacent P-well region  17  (reference label “D”). As illustrated on the right side of  FIG. 4B , an 18 Volt potential may be established between the control electrodes and the channel regions of the group A EEPROM cells by driving the global control line GCL 0  at −8 Volts and turning on the byte selection transistor BST 1 _ 1  so that the local control line LCL 1 _ 1  is held at −8 Volts. In addition, the first P-well region  15  is held at +10 Volts so that charge accumulated in any of the floating gate electrodes of any of the group A EEPROM cells can be withdrawn. The group B EEPROM cells are precluded from undergoing an erase operation by disposing the local control line LCL 1 _ 2  (see,  FIG. 3 ) in a floating condition by turning off the byte selection transistor BST 1 _ 2 . The group C EEPROM cells are precluded from undergoing an erase operation by driving the corresponding global control line GCLn- 2  (e.g., GCL 6 ) and the corresponding local control line LCLn- 1 _ 1  (e.g, LCL 7 _ 1 ) at a positive voltage (Vcc), while holding the first P-well region  15  at +10 Volts. Finally, the group D EEPROM cells are precluded from undergoing an erase operation by biasing the second P-well region  17  at 0 Volts and disposing the corresponding local control line LCL 1 _ 3  (see,  FIG. 3 ) in a floating state.  
         [0038]     Referring to  FIG. 5 , a layout schematic of the programmable read only memory (EEPROM)  10 ′ of  FIGS. 3 and 4 A- 4 B will now be described. In particular,  FIG. 5  illustrates an N-well region  13  containing a plurality of P-well regions  15  and  17 . The illustrated portion of the central P-well region  15  contains two consecutive rows of 2T EEPROM cells that span 16 columns. For purposes of discussion herein, these two rows will be treated as the first two rows illustrated on the left side of  FIG. 3 , which are disposed within the P-well region  15 . The reference labels LCL_R (“R”=right side of corresponding P-well region) within the central P-well region  15  correspond to the local control lines LCL 1 _ 2  and LCL 2 _ 2  in  FIG. 3  and a reference labels LCL_L (“L”=left side of corresponding P-well region) within the central P-well region  15  correspond to the local control lines LCL 1 _ 1  and LCL 2 _ 1 . The reference labels GSL within the central P-well region  15  correspond to gate line segments attached to ground selection lines GSL 0  and GSL 1 . The region  33 , which includes left side region  33 L and right side region  33 R, includes the layout pattern of a plurality of N-type diffusion regions (representing source/drain regions of the NMOS transistors and EEPROM transistors). These N-type diffusion regions are identified by the reference labels  33 L 1 - 33 L 8  and  33 R 1 - 33 R 8 . The reference labels  33   s  and  33 CS identify the layout pattern of the joined N-type diffusion regions that are connected to the common source line CSL 0  (see  FIG. 3 ) at the common source contact via CSC.  
         [0039]     The layout reference  37  represents an electrically conductive wiring pattern that electrically connects an end of a corresponding local control line to a source terminal of a corresponding byte selection transistor, which is located within the N-well region  13 . The layout reference  36   s  corresponds to the source regions of the byte selection transistors and the layout reference  36   d  corresponds to the drain regions of the byte selection transistors. The gate terminals of these byte selection transistors (see, e.g. BST 1 _ 1  in  FIG. 3 ) are electrically connected to the metal byte selection lines identified by the references BSL_R and BSL_L.  
         [0040]      FIG. 5  also includes two highlighted regions A and B, which are identified by dotted lines. Region A is illustrated more fully by  FIG. 6A  and region B is illustrated more fully by  FIG. 7A . In particular,  FIG. 6A  includes two cross-sectional lines  6 B- 6 B′ and  6 C- 6 C′ and the following additional reference labels:  50 D,  50 S,  50 S/D, MCU, MCT and GST, which are not otherwise illustrated by  FIG. 5 . The reference label MCU identifies the layout area associated with each 2T EEPROM cell, the reference label MCT identifies the layout area associated with an EEPROM transistor within the 2T EEPROM cell and the reference label GST identifies the layout area associated with a ground select transistor (which has a gate electrode connected to corresponding ground selection lines GSL).  
         [0041]      FIG. 6B  illustrates a cross-sectional view of a portion of the EEPROM  10 ′ of  FIG. 3 , taken along line  6 B- 6 B′ in  FIG. 6A . As illustrated by  FIG. 6B , a bit line  55  is vertically coupled by electrically conductive vias CDC to corresponding N-type drain regions  50 D of EEPROM transistors  28   a , which are located within a first P-well region  15 . This first P-well region  15  is located within a larger N-well region  13 . This N-well region  13  may be a deep N-type diffusion region within a semiconductor substrate  11 . Each EEPROM transistor within a corresponding MCT layout region includes a control electrode  27   a , which is part of a longer local control line (LCL_L), a floating gate electrode  23   a , a tunnel oxide layer  21 , an inter-electrode insulating layer  25   a  and source/drain regions ( 50 D and  50 S/D). Each ground select transistor  28   b  within a corresponding GST layout region includes a vertical dual-gate structure including a gate insulating layer  21  and conductive regions  23   b  and  27   b , which are electrically connected together (in a third dimension, not shown). The insulating region  25   b  does not preclude all contact between the conductive regions  23   b  and  27   b . The conductive regions  23   b  and  27   b  collectively form a portion of the ground select line GSL. Referring now to  FIG. 6C , a pair of shallow trench isolation (STI) regions  19  are illustrated along with N-type diffusion regions  33 CS, which electrically connected the source regions  50   s  of adjacent GSTs. These diffusion regions  33 CS are connected by electrically conductive vias CSC to respective common source lines CSL  43 .  
         [0042]      FIG. 7A , which is an enlarged layout view of region B in  FIG. 5 , includes an additional reference  35 , which identifies an N-type diffusion region pattern (e.g., an implant mask pattern) from which source and drain regions  36 S and  36 D are defined (e.g., after implant and diffusion/drive-in anneal). Regions  34 R and  34 L represent dummy diffusion patterns associated with dummy transistors that provide a vertical support for a via contact to the corresponding wiring patterns  37  (see  FIG. 7B ) and  39  (see  FIG. 7C ).  FIG. 7A  also includes two cross-sectional lines  7 B- 7 B′ and  7 C- 7 C′ that highlight the layout and cross-sectional construction of a plurality of EEPROM transistors and ground selection transistors (GSTs), respectively. In particular,  FIG. 7B  illustrates the spaced-apart P-well regions  15  and  17  within a larger N-well region  13 . The P-well regions contain patterned shallow trench isolation regions  19 , which provide local electrical isolation of adjacent transistors. On the left side of  FIG. 7B , the local control line (LCL_R) is illustrated as spanning a plurality of EEPROM transistors  28   a  and the dummy transistor (identified by region  34 R). The wiring pattern  37  provides an electrical jumper connection to a source region  36 S of a corresponding byte selection transistor BST_R having a gate electrode with underlying gate insulating layer  22 . The drain region  36 D of the byte selection transistor BST_R is electrically connected to a corresponding global control line (GCL), which is identified by the reference label  40 . Similarly, on the right side of  FIG. 7B , the local control line (LCL_L) is illustrated as spanning a plurality of EEPROM transistors  28   a  and the dummy transistor (identified by region  34 L). The wiring pattern  37  provides an electrical jumper connection to a source region  36 S of a corresponding byte selection transistor BST_L. The drain region  36 D of the byte selection transistor BST_L is commonly connected to the drain region  36 D of the adjacent byte selection transistor BST_R and the global control line  40 .  
         [0043]      FIG. 7C  highlights the layout and cross-sectional construction of a plurality of ground selection transistors  28   b  having gate electrodes that are linked together along a corresponding ground selection line GSL. In  FIG. 7C , the dummy transistors at the locations identified by reference numerals  34 R and  34 L extend underneath electrically conductive vias  38  that are joined together by a ground selection line segment  39  (omitted from  FIG. 7A , but shown in  FIG. 7C ). The ground selection line segment(s)  39  links the spaced-apart ground selection lines into a continuous wiring pattern that spans multiple P-well regions, as illustrated by  FIG. 3 .  
         [0044]     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.