Abstract:
A control circuit optimizes the track seeking operation of a disk drive by automatically adjusting the phase margin of a compensator circuit that generates a control signal used to drive the actuator of the disk drive to optimize the actual performance of the drive during track seeking operations. Parametric values of coefficients associated with the compensation circuit used for driving the head of the disk drive are adjusted responsive to the determination of the system phase margin to change the phase margin and bring it within a desired range. More specifically, the present invention provides a method and apparatus for automatically controlling the phase margin in a compensation control circuit for a disk drive having a head driven by an actuator. The head is driven with a control signal that is generated by a compensator circuit. Feedback from the head is employed to create a position signal, which is used to generate a position error signal. The position error signal is combined with a disturbance signal of predetermined frequency. The resulting signal is fed into the compensator circuit, which has a transfer function that can be expressed mathematically in terms of one or more coefficients. The phase margin of the system is computed by taking the phase difference between the disturbance signal and the component of the position error signal that has the same frequency as the disturbance signal. The values of the compensator circuit coefficient are adjusted to bring the phase margin within an acceptable range.

Description:
FIELD OF THE INVENTION 
     The present invention relates to optimizing track seeking operations for disk drives, and more particularly to a method and apparatus for automatically adjusting the phase margin in a servo control circuit for a disk drive to provide optimal track seeking operations. 
     BACKGROUND OF THE INVENTION 
     When a head in a disk drive is moved by its corresponding servo-controlled actuator from one disk track to another selected disk track, a servo system controls the actuator and closely monitors and controls the velocity and position of the head on the disk in real time to achieve optimal performance. For this purpose, as is well-known to one of ordinary skill in the field, position information is derived and fed back in the form of an error correction signal to a compensator circuit. The compensator circuit generates a signal that is applied to the actuator to accurately control the radial position of the head over the disk. 
     The operating phase margin of the servo control circuit is typically preset for large numbers of disk drives based on an assumed set of worst case conditions. However, past experience has shown that actuator friction varies from drive to drive over a large population of drives and that friction also varies with changes in operating temperature. It is well-known that as friction varies, so does the phase margin of the servo system, which directly affects the stability and performance of the disk drive over time. 
     Of course, when the phase margin for the servo control is set to an assumed worst case situation, individual disk drives not operating in the worst case do not receive optimal servo control information. Further, when actuator friction changes under normal operating temperature changes the preset phase margin compensation does not change which results in the inability of the servo control to optimize to actual operating conditions for a specific disk drive. 
     Previously known control systems for optimizing the seek performance of disk drives in real time adjust a seek velocity profile, which controls the velocity at which the actuator is driven as a function of the length of a specific seek to be performed. Such systems monitor the occurrence of head overshoots and related parameters to update the seek velocity profile. These systems do not account for the reduction in performance caused by a suboptimal phase margin. 
     SUMMARY OF THE INVENTION 
     The present invention optimizes the track seeking operation of individual disk drives by automatically adjusting the phase margin of a compensator circuit which generates a control signal. The control signal is used to drive the actuator of a disk drive and optimize the actual performance of the drive during track seeking operations. Parametric values of coefficients associated with the transfer function of the compensator circuit are adjusted in response to the determination of the phase margin. The adjustment of the compensator circuit coefficients changes the phase margin of the compensator to bring it within a desired range. 
     More specifically, the present invention provides a method and apparatus for automatically controlling the phase margin in a compensation control circuit for a disk drive having a head driven by an actuator. The head is driven or positioned in response to the control signal generated by the compensator circuit. Feedback from the head is used to generate a position signal, which is used to generate a position error signal. The position error signal is combined with a disturbance signal of predetermined frequency. The resulting signal is fed into the compensator circuit, which has a transfer function that can be expressed mathematically in terms of one or more coefficients. The phase margin of the system is determined by analyzing the phase difference between the disturbance signal and the component of the position error signal that has the same frequency as the disturbance signal. The values of the compensator circuit transfer function coefficient are adjusted in response to the actual phase margin of the operating disk drive system to bring the phase margin within an acceptable range. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of an automatic continuous phase margin compensation control circuit for use with an operating disk drive system according to the present invention. 
     FIG. 2 is a flow diagram illustrating a preferred method of implementing continuous phase margin compensation for a disk drive system according to the present invention. 
     While the invention is susceptible to various modifications and alternative forms, a specific embodiment thereof has been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular form disclosed. On the contrary, the applicant&#39;s intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The phase margin of a disk drive control circuit has a dramatic effect on the overall performance of the disk drive. If the phase margin falls outside a desirable range of approximately 35° to 50°, the performance of the disk drive is degraded. If the phase margin is less than approximately 35°, head settling times are lengthened beyond an optimal value. On the other hand, phase margins in excess of approximately 50° result in slower than desirable system response times. The present invention provides optimization of individual disk drive performance in real time by maintaining phase margin within an acceptable range. 
     Referring to the drawings, FIG. 1 is a block diagram of an automatic continuous phase margin compensation control circuit 10 for use with an operating disk drive system according to the present invention. As will be apparent to those having ordinary skill in the field, the digital functions of the present invention may be implemented using hardware, software or a combination of the two. The control circuit 10 operates to drive or control an actuator 11 of a head disk assembly (HDA) 12. The actuator 11 is typically considered part of the HDA 12 but is illustrated as a separate unit for the sake of clarity. The operation of the control circuit 10 of the present invention is governed by a central processing unit (CPU) that executes a control program stored in a memory device (not shown). The operation of control programs to control disk drives is well-known to those of ordinary skill in the field. The CPU has the capability to access a memory device and perform calculations on various parameters stored therein via a control program. The control program operating the control circuit 10 must be modified in accord with the teachings of this invention in a manner that is within the scope of one of ordinary skill in the field. 
     As is well-known in the field, the control program that operates the control circuit of the present invention manages information about the position of the disk heads. Specifically, the control program reads track identification information on the disk and uses this information to keep track of the location of the head and to calculate optimum seek velocity of the heads during seek operations. 
     A feedback signal from the head of the HDA 12 in the form of an analog position signal is supplied via a demodulation circuit 13 to an analog-to-digital (A/D) convertor 16. The demodulation circuit 13 converts encoded bit patterns detected by the HDA 12 into an analog signal, which is converted into digital form by the A/D convertor 16 and fed into a summing node 17. The output of the A/D convertor 16 corresponds to the radial position of the heads of the HDA 12 over the disks within a tolerance of +/-1/2 tracks. A track counter variable 19 is provided by the control program as an input to the summing node 17. The track counter variable 19 is calculated by the control program according to well-known methods. In one such method, the control program keeps a running total of tracks crossed by the HDA 12. 
     The output of the summing node 17, which corresponds to the radial position of the heads of the HDA 12 over the disks, is fed into a summing node 21. The tracking information maintained by the control program allows it to generate a reference signal 23, which corresponds to the destination track of the HDA 12. The reference signal 23 is input into the summing node 21. Thus, the output of the summing node 21 is a position error signal (PES). The position error signal corresponds to the difference between the current position of the heads of the HDA 12 and their desired position or destination. The PES signal is fed into a summing node 20 along with a disturbance signal of frequency F BW  generated from a sine table 26. The output of the summing node 20 is fed into a compensator circuit 18 of the type well-known to those of ordinary skill in the field. The compensator circuit 18 has a frequency domain transfer function H(z) of the general form: ##EQU1## 
     As will be fully described hereinafter, the coefficients A and B associated with the terms in this transfer function are established by the phase margin compensation control circuit 10 of the present invention to optimize performance of the disk drive. The output of the compensator circuit 18 is fed into a digital-to-analog (D/A) convertor 22, which converts it into an analog control signal. The output of the D/A convertor 22 can be amplified if needed to a level suitable for driving the actuator 11 associated with the HDA 12. As will be apparent to one of ordinary skill in the art, the control circuit formed by the demodulation circuit 13, the A/D convertor 16, the compensator circuit 18, the track counter variable 19, the D/A convertor 22, the reference signal 23, the summing nodes 17, 20 and 21, and the actuator 11 are well-known and accordingly not described in detail. 
     The sine table 26 is part of or stored in a memory device associated with the control circuit 10, as will be appreciated by those of ordinary skill in the field. The sine table 26 consists of a plurality of successive memory locations that contain data corresponding to a point on a sinusoidal waveform having a sufficiently large magnitude to produce a measurable disturbance of the PES signal. The frequency of the sine wave generated by the sine table 26 is variable under program control depending on the speed at which values are read out of the sine table 26. The phase of a sine wave with respect to a reference point is known since the address of a specific point on the sinusoid is known and each successive address location represents a fixed phase difference. For example, if the sine table 26 contains 360 entries, each successive entry differs from the preceding entry by 1°. The sine table 26 is desirably constructed to wrap around so that a waveform of indefinitely long duration can be created. For purposes of the present invention, the frequency of the sine wave generated corresponds to the operating bandwidth of the specific HDA that is being optimized by the control circuit 10. This bandwidth is designated as F BW . 
     A disturbance signal having a frequency of F BW  is generated from the sine table 26 under program control by a pointer designated as &#34;SINE PTR&#34; as will be understood by one of ordinary skill in the field. The value of the SINE PTR pointer corresponds to an address of one of the values stored in the sine table 26. Because any specific point of the sinusoidal disturbance signal can be called from the sine table 26 at any time, the control program can accurately control the phase of the disturbance signal with respect to other signals provided by the sine table 26. The initial value chosen for SINE PTR may be calculated or stored in memory as a default value for use by the control program. As will be apparent to one of ordinary skill in the field, the specific initial value of SINE PTR is irrelevant to the practice of the invention because the value of SINE PTR merely corresponds to a single point on a sinusoidal waveform. 
     In a preferred embodiment of the invention, the value of SINE PTR is an integer between 0 and 32,767 counts. This range corresponds to 360° because it represents one cycle of a sine wave. The value of SINE PTR is incremented once per interrupt cycle (for example, 20,160 times per second) of the microprocessor that runs the control program. As is readily apparent to one of ordinary skill in the art, the value of SINE PTR can be incremented by a predetermined amount when each interrupt occurs. In a preferred embodiment, the incremental value of SINE PTR is 893 counts. Thus, the value of SINE PTR increases by 893 times 20,160 counts each second (18,002,900 counts per second). The frequency F BW  for a given embodiment can be calculated by dividing the total number of counts per second by the number of counts corresponding to the range of SINE PTR. Thus, the frequency F BW  in a preferred embodiment of the invention is 18,002,900/32,768 or 550 Hz. The sine table 26 may contain any desired number of entries. In a preferred embodiment, the sine table 26 contains 32 entries. Since SINE PTR has 32,768 possible values, the value of the SINE PTR is divided by 2 10  (1 k) and added to the initial memory address of the sine table 26 to obtain successive addresses in the sine table 26. 
     A sinusoidal waveform of frequency F BW  is read out of the sine table 26 under program control and provided to the summing node 20. As previously noted, the other input to the summing node 20 is the output of the summing node 21 (PES). In addition to providing the waveform of frequency F BW  to the summing node 20, the control program selects a point having a predetermined phase relationship with respect to the disturbance signal from the sine table 26 and causes a waveform F P  of frequency F BW  to be supplied to a multiplying node 28. The output signal of the summing node 21 (the PES signal) is also fed into the multiplying node 28. The output signal of the multiplying node 28, a phase measurement signal designated as F prod , is supplied to an averaging filter 30. The output signal of the averaging filter 30 is supplied to an integrator 32. The output signals from the averaging filter 30 and the integrator 32 are both fed into a summing node 34. Finally, the output signal of the summing node 34 and the SINE PTR selection signal are supplied to a summing node 36, which has an output signal designated as F P  PTR. As will be fully explained hereinafter, the output of the summing node 34 is used to determine the phase margin of the system. It is within the contemplation of the present invention for the output of the summing node 34 to be monitored by the control program using well-known methods. For example, if the invention is implemented with digital circuitry, the value of the output of the summing node 34 may be read into the CPU over a data bus 33 or converted into an analog voltage by an A/D convertor (not shown) for measurement by the CPU using conventional techniques. If the invention is implemented in software, the value of the summing node 34 is stored in a memory location where it can be accessed by the CPU. 
     The F P  PTR signal is used to point at successive iterative positions in the sine table 26 so that the phase relationship between the F P  signal and the disturbance signal changes with each successive iteration. As the output of the integrator 32 changes, F P  PTR changes to point at successive values until the output of the averaging filter 30 goes to zero. When this occurs, enough information is known to allow the control program to determine the phase margin of the system. To do this, the control program subtracts the waveform position (phase reference) indicated by the output of the summing node 34 and the waveform position pointed to by SINE PTR to calculate the angular difference between the waveform points indicated by these two signals. As previously discussed, the phase margin can be computed from this information by the control program because each incremental value of the sine table 26 corresponds to a fixed amount of angular displacement between waveform positions. 
     The significance of the averaging filter 30 being driven to zero by successive iterations is rooted in well-known mathematical principles. The PES signal includes sinusoidal frequency components of various frequencies, including a component at frequency F BW . The product of two sinusoids having different frequencies has an average value of zero, but the product of two sinusoids having the same frequency yields a measurable result. Therefore, the F prod  signal and the output of the averaging filter 30 are proportional to the F BW  component of the PES signal, because other components of the PES signal are zeroed out by the operation of the multiplying node 28. 
     Specifically, the product F prod  of two sinusoids having phases of A and B respectively is expressed as follows: 
     
         F.sub.prod =sin A*sin B=0.5[cos (A-B)-cos (A+B)]           (2) 
    
     To simplify the equation, let B=A+C because the two sinusoids of interest, F BW  and PES, are of the same frequency, but phase shifted by C. Thus, 
     
         F.sub.prod =0.5*[cos (-C)-cos (2A+C)](3) 
    
     Further, if A is defined to be the phase of the disturbance signal and C is defined to be the phase of F P  relative to A, two values of C would cause the value of F prod  to equal zero. These two frequencies are separated by 180°, but only the one of these values that is phase advanced by 90° compared to the disturbance signal is stable. Thus, if C is defined to be 90°, 
     
         F.sub.prod =0.5*sin 2A                                     (4) 
    
     Under these conditions, F prod  has an average value of zero. Therefore, it is known that when the output of the averaging filter 30 is zero, F P  is advanced 90° with respect to the disturbance signal. Thus, the phase margin of the system is determined when the output of the averaging filter 30 is zero because the phase relationship between F prod  and the disturbance signal is known at this point. 
     It is within the contemplation of the present invention for the output of the averaging filter 30 to be monitored by the control program using well-known methods. For example, if the invention is implemented with digital circuitry, the value of the output of the filter 30 may be read into the CPU over a data bus 31 or converted into an analog voltage by an A/D convertor (not shown) for measurement by the CPU using conventional techniques. If the invention is implemented in software, the value of the averaging filter 30 is stored in a memory location where it can be accessed by the CPU. It is additionally within the contemplation of the present invention for the control program to delay measurement of the phase margin for a predetermined period of time, after which it is assumed that the output of the averaging filter 30 is sufficiently close to zero to allow an accurate determination of the phase margin to be made. 
     After the phase margin is determined, the operating coefficients of the transfer function associated with the compensator circuit 18 are adjusted to change the phase margin, bringing it within a desired range. If the invention is implemented as a hardware circuit, the coefficients of the compensator are determined by the values of electronic components (for example, programmable resistor networks) associated with the compensator circuit. As will be apparent to one of ordinary skill in the field, the phase margin of the hardware compensator circuit can be altered by employing the control program to change the values of selected compensator circuit components, such as the values of resistors in programmable resistor networks. In the hardware embodiment, control information is passed to the compensator circuit 18 via a data bus 25 from the CPU. This information is used to set the value of components, thereby setting the value of the coefficients associated with the compensator circuit 18. The use of control programs to alter the value of components in compensator circuits is well-known. 
     In a software embodiment of the present invention, the coefficients are stored in memory where they can be altered by the control program. When the control program determines the appropriate value for a given coefficient, the value is stored in a memory location corresponding to that coefficient. Coefficient values are generated by the control program based on empirical observations of a plurality of HDAs and how the phase margins of the compensator circuits of the observed HDAs change as the coefficients are changed. By quantifying the coefficient values that correspond to various phase margins, a mathematical formula that relates each coefficient (for example, all A 2  s, all A 1  s, etc.) in terms of phase margin is derived. Thus, equations may be developed that predict a combination of coefficients necessary to change the phase margin of the compensator 18 to a known level. 
     The methods used to derive these equations are, of course, commonly known. One example of such a method is the least squares method of curve fitting. A mathematical expression for each coefficient is derived by curve fitting empirically measured coefficients for a population of HDAs. As will be apparent to one of ordinary skill in the art, the accuracy of the mathematical representations of the coefficients is directly proportional to the size of the population of empirically measured HDAs. 
     As an example, assume that we wish to generate mathematical expressions for compensator circuit coefficients based on observations of five compensator circuits having a phase lead or lag ranging from -20° to 20° and are gain normalized at frequency F BW . It is necessary to curve fit each of the transfer function coefficients (i.e., all A 2  s, A 1  s and A 0  s, etc.) in order to have a first or second order equation which represents the A coefficients in terms of phase. Thus, if the five exemplary compensator circuits have the following A 0  coefficients: 
     
         ______________________________________A.sub.0 coefficients           Phase______________________________________1.0             -20°0.9768          -10°0.9496            0°0.9284           10°0.9034           20°______________________________________ 
    
     the least squares curve fit results in the following values for the A0 coefficients of the five compensator circuits: 
     
         A0=-0.0024x+0.9513                                         (5) 
    
     where x is a desired phase adjustment value, which corresponds to the difference between the desired phase margin of the system and its actual phase margin. This equation is implemented by the control program to alter the value of the A0 coefficient of the HDA 12 being controlled to produce any desired phase margin. When equations for all coefficients are computed in this manner and stored in memory by the control program, the phase margin of the compensator circuit 18 will approximate the value associated therewith. 
     FIG. 2 is a flow diagram illustrating a preferred method of implementing continuous phase margin compensation for a disk drive according to the present invention. At step 38, the control program selects a predetermined phase value for the disturbance signal from the sine table 26 using the SINE PTR index pointer. A phase offset signal F P  is also generated from the look-up sine table 26 and multiplied by the PES signal to yield the phase margin measurement signal F prod  signal at step 40. As previously noted, the control circuit 10 of the present invention iteratively selects successive values corresponding to a phase difference between the disturbance signal and F prod  to cause the value of the phase margin measurement signal to go to zero. Thus, the average value of the phase margin measurement signal is determined and the phase relationship between the disturbance signal and F prod  is iteratively modified based on the value F P  PTR until the average value of F prod  is zero. In this manner, successive values of phase difference are offset relative to the initial value of SINE PTR based on the effect a given phase difference has on the performance of the control circuit 10, as manifested by the output signal from the summing node 34. Stated another way, successive values of phase difference between the disturbance signal and F prod  are pointed to in the sine table 26 according to the value of the output signal of the summing node 34+SINE PTR. 
     When the output of the averaging filter 30 reaches zero, the phase margin of the system is determined at step 44. As previously noted, the phase margin is equal to the difference between the phase at the locations in the sine table 26 pointed to by F P  PTR and SINE PTR. Thus, the phase of the output from the summing node 34 is expressed as follows: 
     
         Phase=SINE PTR-(F.sub.P PTR-90°)                    (6) 
    
     and the phase margin of the system is expressed as: 
     
         Phase Margin=180°-Phase                             (7) 
    
     Coefficients of the transfer function associated with the compensator circuit 18 are adjusted at step 46 as previously described to bring the phase margin of the system within a desired range. 
     Thus, there has been described herein a control circuit and method for the continuous optimization of the phase margin of disk drives necessitated by changes in the specific operating conditions of each individual disk drive. The phase margin is automatically adjusted during actual operation of the disk drive. It will be understood that various changes in the details and arrangements of the implementation described herein will occur to those skilled in the art without departing from the principle and scope of the present invention. Thus, while the invention has been described with reference to the presently contemplated best mode for practicing the invention, it is intended that this invention only be limited by the scope of the appended claims. 
     The following program listing is a present preferred listing for the automatic phase margin compensation control circuit and method described above: ##SPC1##