Abstract:
A photosensor array includes data and scan lines ( 124, 148 ), circuitry of each data line/scan line pair formed in a backplane ( 110 ) on a substrate ( 102 ). On a first electrode scan line ( 148 ) a switching element ( 112 ) responds to a scan signal, connecting a first terminal ( 106 ) to a second terminal ( 108 ). A front plane ( 120 ) has sensing elements ( 122 ) indicating a measure of a received stimulus and including a charge collection electrode ( 130 ). An insulating layer ( 140 ) disposed between the backplane ( 110 ) and the front plane ( 120 ) contains at least a first via ( 136 ) connecting the first terminal ( 108 ) of the switching element ( 112 ) in the backplane ( 110 ) to a charge collection electrode ( 130 ) of the sensing element ( 122 ) in the front plane ( 120 ). A second via ( 126 ) connects between the second terminal ( 108 ) of the switching element ( 112 ) and the data line ( 124 ).

Description:
FIELD OF THE INVENTION 
       [0001]    This invention generally relates to digital radiographic imaging and more particularly relates to an imaging array having an improved fill factor and reduced capacitive coupling between data electrodes and conductive structures. 
       BACKGROUND OF THE INVENTION 
       [0002]    A digital radiography imaging panel acquires image data from a scintillating medium using an array of individual sensors, arranged in a row-by-column matrix so that each sensor provides a single pixel of image data. 
         [0003]    For these devices, hydrogenated amorphous silicon (a-Si:H) is commonly used to form the photodiode and the thin-film transistor (TFT) switch.  FIG. 1A  shows a cross-section (not to scale) of a single imaging pixel  10  in a prior art a-Si:H based flat panel imager. Each imaging pixel  10  has, as shown in  FIG. 1B , a photodiode  70  and a TFT switch  71 . 
         [0004]    A layer of X-ray converter material (e.g., luminescent phosphor screen  12 ), shown in  FIG. 1 , is coupled to the photodiode-TFT array. Photodiode  70  comprises the following layers: a passivation layer  14 , an indium tin oxide layer  16 , a p-doped Si layer  18 , an intrinsic a-Si:H layer  20 , an n-doped Si layer  22 , a metal layer  24 , a dielectric layer  26 , and glass substrate  28 . X-ray photon path  30  and visible light photon path  32  are also shown in  FIG. 1A . When a single X-ray is absorbed by the phosphor, a large number of light photons are emitted isotropically. Only a fraction of the emitted light reaches the photodiode and gets detected. 
         [0005]      FIG. 1B  shows a block diagram of the flat panel imager  80 . Flat panel imager  80  consists of a sensor array  81  comprising a matrix of a-Si:H n-i-p photodiodes  70  and TFTs  71 , with gate driver chips  82  connected to the blocks of gate lines  83  and readout chips (not shown) connected to blocks of data lines  84  and bias lines  85 , having charge amplifiers  86 , optional double correlated sampling circuits with programmable filtering (not shown) to help reduce noise, analog multiplexer  87 , and analog-to-digital converter (ADC)  88 , to stream out the digital image data at desired rates. The operation of the a-Si:H-based indirect flat panel imager is known by those skilled in the art, and thus only a brief description is given here. 
         [0006]    Incident X-ray photons are converted to optical photons in the phosphor screen  12 , and these optical photons are subsequently converted to electron-hole pairs within the a-Si:H n-i-p photodiodes  70 . In general, a reverse bias voltage is applied to bias lines  85  to create an electric field (and hence a depletion region) across the photodiodes and enhance charge collection efficiency. The pixel charge capacity of the photodiodes is determined by the product of the bias voltage and the photodiode capacitance. The image signal is integrated by the photodiodes while the associated TFTs  71  are held in a non-conducting (“off”) state. This is accomplished by maintaining gate lines  83  at a negative voltage. The array is read out by sequentially switching rows of TFTs  71  to a conducting state by means of TFT gate control circuitry. When a row of pixels is switched to a conducting (“on”) state by applying a positive voltage to corresponding gate line  83 , charge from those pixels is transferred along data lines  84  and integrated by external charge-sensitive amplifiers  86 . The row is then switched back to a non-conducting state, and the process is repeated for each row until the entire array has been read out. The signal outputs from external charge-sensitive amplifiers  86  are transferred to analog-to-digital converter (ADC)  88  by parallel-to-serial multiplexer  87 , subsequently yielding a digital image. The flat panel imager is capable of both single-shot (radiographic) and continuous (fluoroscopic) image acquisition. 
         [0007]    Because of the scale of sensor devices and the proximity of data lines to other electrodes and conductive components, the problem of capacitive coupling is a particular concern with digital radiology sensors. Unless some corrective action is taken, capacitive coupling can degrade functions of the sensing array for both signal measurement and data accuracy. There have been a number of proposed solutions in response to this problem. For example, U.S. Pat. No. 5,770,871 (Weisfield) describes the use of an insulating anti-coupling layer interposed between charge collection electrodes and data lines. Similarly, U.S. Pat. No. 6,858,868 (Nagata et al.) describes an interlayer insulating film provided between data and analog signal electrodes. U.S. Pat. No. 6,124,606 (den Boer et al.) describes the use of an insulating layer having a low dielectric constant for reducing parasitic capacitance where collector electrodes overlap switching devices. U.S. Pat. No. 6,734,414 (Street) describes a method for reduced signal coupling by a particular routing pattern for readout control signal lines for columns of pixels. 
         [0008]    For many types of conventional sensing devices, the photosensor device itself, typically a photodiode or PIN diode, only occupies a portion of the surface area. Switching devices used to switch the photosensor component to a read-out device take up a sizeable portion of the area of each pixel. As a result, the sensor device suffers from relatively poor fill-factor and is able to use only a fractional portion of the light emitted from the phosphor screen. As one example, U.S. Pat. No. 5,516,712 (Wei et al.) describes a pixel with side-by-side photosensor and switching thin-film transistor (TFT) elements. More recently, designs using photosensors stacked atop their switching components have been employed, providing some measure of improved efficiency. For example, U.S. Pat. No. 6,707,066 (Morishita) describes a photodetection apparatus having photodiodes positioned atop switching TFT devices, thus closer to scintillation material in the imaging device. U.S. Pat. No. 5,619,033 (Weisfield) describes a stacked arrangement with the photodiode atop its switching TFT component, relative to the illumination path. 
         [0009]    The use of tightly stacked photosensor and TFT components has advantages for increasing the effective fill factor of the sensing array. However, with more compact packaging comes the complication of increased signal coupling between data and switching electrodes and increased thermal or “dark state” noise due to Johnson noise effects. The capacitive coupling problem becomes even more acute when the imaging array is formed on a conductive stainless steel substrate. Stainless steel and similar metals have characteristics such as good flexibility and are relatively robust and lightweight. The use of a stainless steel substrate allows manufacture of a thin imaging plate for radiographic imaging. However, capacitive coupling effects can compromise the overall performance of a plate formed on a stainless steel substrate. 
         [0010]    One way to reduce thermal noise is to increase the conductivity of data traces, thereby reducing resistance. This can be effected by increasing conductor thickness and by a suitable choice of conductive material. The conductive materials that are conventionally used for making connections to array sensing electronics are not ideal conductors and must be selected from among a somewhat limited group of materials. Typically, for example, chromium is used for connection to doped silicon components. Aluminum, although a better conductor, exhibits a tendency to diffuse into silicon and to form hillock- and whisker-type defects at high temperatures, rendering it an unsuitable alternative for many semiconductor designs. 
         [0011]    Techniques for reducing capacitive coupling effects include increasing the separation distance between conductive surfaces and decreasing the effective dielectric constant of the insulation between switching and signal electrodes. However, current fabrication techniques typically form these metal electrode structures on the backplane with a thin a-SiN:H dielectric separation layer that is typically only a few hundred nanometers thick, resulting in generally higher coupling, higher crosstalk levels. This could also result in increasing the likelihood of interlayer shorts manufacturing defects. 
         [0012]    Thus, what is needed is an apparatus that provides both high fill factor for improved efficiency and, at the same time, reduces capacitive coupling and crosstalk between control and signal lines in the array device. 
       SUMMARY OF THE INVENTION 
       [0013]    It is an object of the present invention to provide a photo-sensor array having array circuitry that includes data lines and scan lines and, for each data line/scan line pair, cell circuitry; the cell circuitry of each data line/scan line pair comprising:
       a) a backplane comprising:
           (i) a substrate;   (ii) a first electrode scan line disposed over the substrate;   (iii) a switching element for responding to a scan signal from the scan line by electrically connecting a first terminal to a second terminal to provide an electric signal to pass between the first terminal and the second terminal;   
           b) a front plane, comprising:
           (i) one or more sensing elements for receiving a stimulus and for providing an electric signal indicating a measure of the received stimulus, the sensing element including a charge collection electrode;   (ii) a data line for reading out the electric signal;   
           c) an insulating layer of at least about 2 microns thickness disposed between the backplane and the front plane, containing at least:
           (i) a first via forming an electrical connection between the first terminal of the switching element in the backplane and a charge collection electrode of the sensing element in the front plane; and   (ii) a second via forming electrical connection between the second terminal of the switching element and the data line.   
               
 
         [0024]    It is an advantage of the present invention that it provides a photosensor array having a high fill factor and having reduced thermal noise and capacitive coupling. 
         [0025]    It is a feature of the present invention that it provides improved isolation of data, gate switching, and bias electrodes. The arrangement of the present invention provides significantly reduced coupling when using a conductive substrate. The apparatus of the present invention allows the use of a data line having lower resistance for improved conductivity, resulting in reduced thermal noise. The thick insulator between the front and back planes and the gate dielectric layer helps to reduce capacitive coupling and cross-talk, as well as helps to minimize the possibilities of shorts between conductive layers. 
         [0026]    These and other objects, features, and advantages of the present invention will become apparent to those skilled in the art upon a reading of the following detailed description when taken in conjunction with the drawings wherein there is shown and described an illustrative embodiment of the invention. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter of the present invention, it is believed that the invention will be better understood from the following description when taken in conjunction with the accompanying drawings, wherein: 
           [0028]      FIG. 1A  is a cross-sectional view showing an imaging pixel in a flat-panel imager; 
           [0029]      FIG. 1B  is a schematic diagram showing components of a flat-panel imager; 
           [0030]      FIG. 2  is schematic cross-sectional view of a pixel sensing circuit according to an embodiment of the present invention; 
           [0031]      FIG. 3  is a top view of a pixel sensing circuit showing representative locations of data and signal electrodes in one embodiment; 
           [0032]      FIG. 4  is a schematic diagram showing sources of parasitic capacitive coupling; 
           [0033]      FIG. 5A  is schematic cross-sectional view showing a TFT switching element of the pixel; 
           [0034]      FIG. 5B  is a top view showing the layered structure for the TFT device in  FIG. 5A ; 
           [0035]      FIG. 6A  is schematic cross-sectional view showing TFT formation with an insulating separation layer in a subsequent fabrication step; 
           [0036]      FIG. 6B  is a top view showing the locations for vias etched into the insulating separation layer in  FIG. 6A ; 
           [0037]      FIG. 7A  is schematic cross-sectional view showing the photodiode deposited atop the TFT device in a subsequent fabrication step; 
           [0038]      FIG. 7B  is a top view showing the photodiode layout for the step shown in  FIG. 7A ; 
           [0039]      FIG. 8A  is schematic cross-sectional view showing via and bias line formation in a subsequent fabrication step; and 
           [0040]      FIG. 8B  is a top view showing the completed pixel sensing circuit of  FIG. 8A . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0041]    The present description is directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with the invention. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. 
         [0042]    Referring to  FIG. 2 , there is shown a cross-sectional view of a pixel sensing circuit  100  according to an embodiment of the present invention. A substrate  102  on which circuit  100  is formed can be glass, plastic, or an inorganic film, polyimide, acrylic resin, benzocyclobutene (BCB), or the like or some other material, including stainless steel, for example, coated with a dielectric, such as BCB or spin-on glass. Electronic components and sensors are fabricated as part of a backplane  110  or a front plane  120 . An insulating layer  140  separates backplane  110  from front plane  120 . Insulating layer  140  can be, for example, benzocyclobutene (BCB), polyimide, sol-gel, acrylic, or some other suitable material having a suitably low dielectric constant (for example, SiO2, SiNx, and SiON). 
         [0043]    Backplane  110  has a switching element  112 , typically a thin-film transistor (TFT) or similar component. A gate electrode  114 , connected to a scan line, enables switching element  112 , forming a closed electrical circuit between terminals  106  and  108  through a channel  116 . Doped regions  144  and  146  are provided over channel  116  as shown. Backplane  110  can be formed using conventional TFT deposition and etching techniques, building up an array of switching elements  112  on substrate  102 . A gate dielectric layer  142  insulates gate electrode  114 . 
         [0044]    Front plane  120  has a photosensor  122  that is typically a-Si:H PIN diode or other thin-film semiconductor structure  132  having a top electrode  134  made of transparent conductive material and a bottom electrode  130  for charge collection. Photosensor  122  provides a signal according to the level of radiation of a suitable wavelength that it receives. A bias line  128  provides a voltage bias for photosensor  122 . A first via  126  is formed in order to connect a data electrode  124  on the surface of front plane  120  with terminal  106  on switching element  112 , which is on backplane  110 . A portion of bottom electrode  130  forms another via  136  that connects photosensor  122  with terminal  108  on backplane  110 . Front plane  120  may have a passivation-layer  104 . An optional antireflection material can also be used. 
         [0045]    It can be seen that the arrangement of  FIG. 2  allows stacking of photosensor  122  on top of switching elements  112 , relative to the plane of substrate  102 . This not only provides a compact arrangement, but also helps to increase fill factor for each pixel. Unlike earlier embodiments using silicon substrates and components, the apparatus of the present invention can use more conductive metals, such as aluminum, rather that less conductive metals that are conventionally used, such as chromium, for example. For example, the use of via  126  allows data line  124  to be formed from aluminum. There is minimal concern with component degradation due to migration of metal atoms into the base materials of switching element  112 . This would be a problem with conventional designs where data electrodes come into contact with silicon. Besides, using the method of the present invention, the data line is typically formed at the end of the fabrication process and there are no subsequent high-temperature steps. This eliminates potential reliability problems associated with high-temperature formation of hillock- and whisker-type defects in the aluminum layer, such as are known to be the cause of electrical shorts. In addition, a thick aluminum layer, of the order of 1 micron or more, can be used with this arrangement. This can further reduce electrical resistance of the data line and thus reduce data line thermal noise. 
         [0046]      FIG. 3  is a top view of a pixel sensing circuit showing representative locations of data and signal electrodes in one embodiment. The proximity of bias line  128 , gate line  148 , and data line  124  would typically represent a parasitic capacitive coupling problem. Typically, gate and data lines are separated by no more than about 200 to 300 nm of silicon nitride. This can cause unwanted capacitive coupling, as shown in  FIG. 4 . However, when using the arrangement of the present invention, as shown in  FIG. 2 , gate line  148  is on backplane  110 , well-separated from bias line  128  and data line  124  which are formed on front plane  120 . Typical separation distance is at least greater than about 2 microns, more preferably in excess of 3 microns with the present invention, using a material having a lower dielectric constant, such as BCB in insulating layer  140 . This reduces coupling and also provides an inherent improvement in fabrication yields. 
         [0047]    Referring to the cross-sectional representation of  FIG. 4 , some of the more significant potential sources of parasitic capacitance are represented. There is a capacitance C 1  between data line  124  and bottom electrode  130  of photosensor  122 . There is another parasitic capacitance C 2  between data line  124  and anode  134  of photosensor  122 . Notably, due largely to the width of insulating layer  140  that lies between data line  124  and substrate  102 , parasitic capacitance between data line  124  and substrate  102 , if conductive, would be minimal with this embodiment. There is also parasitic capacitance at the “crossover” of data line  124  and gate line  148  or at bias line  128  and gate line  148 . This effect is mitigated by the design of the present invention, which increases the separation between data line  124  and bias lines  128 . Additionally, for embodiments where substrate  102  is conductive, another source of parasitic capacitance is between terminal  106  and substrate  102 . 
         [0048]      FIGS. 5A through 8B  show various steps for fabrication of pixel sensing circuit  100 .  FIG. 5A  is a side view showing TFT formation in a fabrication step for backplane  110 .  FIG. 5B  is a top view showing the layered structure for the TFT device in  FIG. 5A . In this step, it is instructive to note that only gate line  148  and its extending gate electrodes  114  are formed on substrate  102 , as components of backplane  110 . As has been noted earlier, other signal lines are formed as components of front plane  120 . 
         [0049]    Switching element  112  is formed as a TFT, by depositing gate dielectric layer  142  onto gate electrode  114 , then depositing channel  116  and doped regions  144 ,  146 . Electrodes  106 ,  108 , which can be metal or other suitable conductive material, are deposited as a final step in fabrication of backplane  110 . As can be appreciated by those skilled in the electronic device fabrication arts, other arrangements for TFT structure and other fabrication sequences are possible. 
         [0050]    The side view of  FIG. 6A  and top view of  FIG. 6B  show the fabrication of insulating layer  140 . To form insulating layer  140 , material is deposited, then etched to expose electrodes  106  and  108 , to which vias  136  and  126 , respectively, will be connected to provide electronic communication between backplane  110  and front plane  120 . Alternatively, photosensitive dielectric material, such as photo-acrylic or the like, can be used as dielectric layer  140 . In that case, vias  126  and  136  can be formed using a process similar to photolithography. 
         [0051]    The side view of  FIG. 7A  and top view of  FIG. 7B  show fabrication of front plane  120  components. Component layers of photosensor  122  are deposited, with cathode  130 , as charge collection electrode of photosensor  122 , making one connection to terminal  108  of switching element  112  through via  136 . Via  126  is formed using a metal or other conductive material that makes electrical connection to terminal  106  of switching element  112 . When photosensor  122  is a photodiode, it may be fabricated using an n+ doped layer formed over cathode  130 , an amorphous silicon layer formed over the n+ doped layer, and a p+ doped layer formed atop the amorphous silicon layer. Anode  134  can then be formed over the p+ doped layer. 
         [0052]    The side view of  FIG. 8A  and top view of  FIG. 8B  show final steps in the fabrication of front plane  120  of pixel sensing circuit  100  in this embodiment. Via  126  is joined to data electrode  124  that extends to multiple pixel sensing circuits  100  in the same column of the pixel or sensor array. Data electrode  124  can be relatively thick aluminum layer, of the order of 1 micron or more, or can be thin copper, such as 0.5 microns in one embodiment. Optionally, data electrode  124  can be formed using a stack of metal layers, including layers of aluminum or copper, for example. Bias line  128  is added to provide a bias signal to anode  134  of photosensor  122 . 
         [0053]    As one advantage, the method of the present invention allows fabrication of sensor array  81  at lower temperatures, including those in the range of 100-200 degrees C., simplifying manufacture. This also allows an expanded variety of inner layer dielectrics to be used, making it easier to fabricate a flat panel imaging apparatus using standard processes. For example, the use of acrylic as an inner layer dielectric is a standard practice in display LCD manufacturing; however, the use of this type of material for imaging panels has been constrained by temperature. 
         [0054]    The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the scope of the invention as described above, and as noted in the appended claims, by a person of ordinary skill in the art without departing from the scope of the invention. For example, photosensor  122 , shown as a PIN diode in  FIG. 2  and elsewhere, could also be some other type of sensor component or a metal insulator semiconductor (MIS) photosensor. An MIS photosensor could have a gate dielectric formed over the charge collection electrode, an amorphous silicon layer formed over the gate insulator, an n+ layer formed over the amorphous silicon layer, and a bias electrode. 
         [0055]    Thus, what is provided is an imaging array having an improved fill factor, reduced data line capacitive coupling, and low-resistance data line metallization, thereby offering reduced noise and an improved signal-to-noise ratio. 
       PARTS LIST 
       [0000]    
       
           10  pixel 
           12  phosphor screen 
           14  passivization layer 
           16  indium tin oxide layer 
           18  Si layer 
           20  a-Si:H layer 
           22  Si layer 
           24  metal layer 
           26  dielectric layer 
           28  glass substrate 
           30  X-ray photon path 
           32  visible light photon path 
           70  photodiode 
           71  TFT switch 
           80  flat panel imager 
           81  sensor array 
           82  driver chip 
           83  gate lines 
           84  data line 
           85  bias line 
           86  amplifier 
           87  multiplexer 
           88  A-D converter 
           100  pixel sensing circuit 
           102  substrate 
           104  layer 
           106  terminal 
           108  terminal 
           110  backplane 
           112  switching element 
           114  gate electrode 
           116  channel 
           120  front plane 
           122  photosensor 
           124  data electrode 
           126  via 
           128  bias line 
           130  bottom electrode 
           132  thin-film semiconductor structure 
           134  top electrode 
           136  via 
           140  insulating layer 
           142  layer 
           144  doped region 
           146  doped region 
           148  gate line