Abstract:
An apparatus and a method for producing passive components on an integrated circuit device. The integrtated circuit device has post wafer fabrication integrated passive components situated on the opposite substrate side of the device&#39;s integrated circuitry. Electrical contact pads of the passive components are configured to be coupled to the electronics package contact pads to complete the electronic package.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation-in-part (and claims the benefit of priority under 35 USC 120) of U.S. patent application Ser. No. 11/304,084, filed Dec. 15, 20053. The disclosure of the prior application is considered part of and is hereby incorporated by reference in the disclosure of this application. 
     
    
     TECHNICAL FIELD  
       [0002]     The invention relates to an integrated circuit package, and more particularly, to incorporating passive components on a back side of a substrate having a fabricated integrated circuit device.  
       BACKGROUND ART  
       [0003]     As electronic packages increase in required functionality as well as the number of functions an electronic package is expected to perform, passive components are frequently needed to accomplish specific circuit tuning. Circuit tuning either adds tunable characteristics to the package or enables the package to perform properly. Enabling proper performance is especially required in many radio-frequency (RF) applications. For example, high-Q inductors are frequently needed in RF applications.  
         [0004]     Adding discrete passive components to electronic packages typically results in an increase in both the size and weight of the package. These increases counter contemporary goals of increased portability and miniaturization. Adding discrete passive components in electronic packages also requires a dedicated production line, frequently including surface mounting equipment and added process setups. The added equipment and processes increase both capital investment and assembly lead-time, resulting in higher product costs.  
         [0005]     Currently, these problems are being addressed by fabricating passive components, (eg., inductors, capacitors, and resistors) over the active circuitry Of an integrated circuit device. Integrating passive components requires various fabrication methods such as thin-film, photolithographic, and plating processes. Vias are formed over a top passivation layer of an integrated circuit device thus allowing integrated passive components to connect to the underlying integrated circuitry elements.  
         [0006]     Consequently, current solutions for adding passive components to an integrated circuit device require custom-designed contact via openings to be at the top passivation layer for each product device. If a product is not initially designed to accept passive components, they cannot be simply added to the device. Therefore, what is need is a simple, inexpensive, and reliable means to add passive components to any integrated circuit without requiring, for example, custom designed contact vias or precise photolithography.  
       SUMMARY  
       [0007]     Embodiments of the present invention have integrated passive components formed on the back side of a substrate while integrated circuit devices are formed on the front side of the substrate. All operations may be carried out at the substrate (e.g., wafer) level prior to singulation of individual dice formed before package assembly. The die containing integrated circuit devices on the front side and integrated passive components on the back side is electrically connected to the substrate device circuitry and/or directly electrically connected to bond features of the packaging device itself. The electrical connections can be achieved by joining appropriate areas with, for example, solder, conductive polymer, or metal-to-metal bonding processes. An optional polymer material, such as epoxy or acrylic, can be used to fill any gaps between the individual die and the substrate of the packaging device to assist in further anchoring the integrated circuit device to the package substrate. The integrated circuit device will then undergo a standard wire bonding process to connect bond pads on the individual die to the package substrate.  
         [0008]     Overall, no photolithographic processes are needed since no contact via holes are formed. Processing takes place on the smooth back side of a substrate so there are no topological issues. Consequently, quality and yield will be higher compared with integration of passive components on the front side (i.e., the active circuit side). Further, 100% of the back side of the substrate is available on which to fabricate passive components.  
         [0009]     Accordingly, in one exemplary embodiment the present invention is an integrated circuit fabricated from a substrate having a front side and a back side. The front side of the substrate has one or more integrated circuit devices fabricated thereon. At least one passive component is fabricated onto the back side of the substrate. The passive component is comprised of a metal structure.  
         [0010]     In another exemplary embodiment, the present invention is an electronics package. The electronics package includes a package substrate having a plurality of package substrate bond pads and an integrated circuit die. The integrated circuit die is fabricated from a substrate having a front side and a back side. One or more integrated circuit devices are fabricated on the front side of the substrate and a plurality of integrated circuit bond pads are fabricated on the integrated circuit devices. At least one passive component is fabricated onto the back side of the substrate. The passive component is comprised of a metal structure having a plurality of passive component bond pads. The bond pads are arranged to correspond to certain ones of the plurality of package substrate bond pads.  
         [0011]     In another exemplary embodiment, the present invention is a method of forming one or more passive components on a substrate. The method includes forming at least one integrated circuit on a front side of a substrate, forming a photoresist layer over a back side of the substrate and patterning and etching the photoresist layer to form one or more passive component structures. The passive component structures are filled with metal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is an isometric drawing of a passive element fabricated on a back side of an integrated circuit substrate in accordance with an exemplary embodiment of the present invention.  
         [0013]      FIG. 2  is an integrated circuits die fabricated in accordance with methods of the present invention and mounted in a ball grid array (BGA) package.  
         [0014]      FIG. 3  is an integrated circuit die fabricated in accordance with methods of the present invention and mounted in a Quad Flat-Pack No-Lead (QFN) package.  
         [0015]      FIGS. 4A-4F  are exemplary fabrication steps of an integrated circuit device produced in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]     In  FIG. 1 , an integrated circuit die  100  includes a substrate  101  having a front side  103  and a back side  105 . In a specific exemplary embodiment, the substrate  101  is portion of a silicon wafer. However, a skilled artisan will recognize that other semiconducting and non-semiconducting materials may be used instead of silicon for the substrate  101 . Other semiconducting materials include, for example, elemental semiconductors such as germanium, compound semiconductors such as group III-V, and II-VI materials, and semiconducting alloys (e.g., Al x Ga 1−x As, HG 1−x CD x Te). Additionally, non-semiconducting materials such as, for example, a polyethylene-terephthalate (PET) substrate deposited with silicon dioxide or a quartz photomask, each of which may be deposited with polysilicon followed by an excimer laser annealing (ELA) anneal step.  
         [0017]     On the back side  105  of the substrate  101 , one or more passive components are formed. In this exemplary embodiment, a large single inductor  107  is formed. The inductor  107  terminates with a bond pad  109  on either end. Techniques disclosed herein apply readily to various types of passive components (e.g., inductors, resistors, capacitors, etc.). The passive components may be fabricated individually or in various combinations and with varying sizes.  FIG. 1  therefore should be viewed as merely illustrative only of a generalized concept to be described in greater detail below.  
         [0018]     With reference to  FIG. 2 a  ball grid array (BGA) package  200  includes a BGA substrate  201 , a plurality of BGA balls  203 , and a plurality of BGA via connections  205 . The BGA package type is generally known in the art. Mounted to the BGA substrate  201  is an integrated circuit die  207  fabricated in accordance with an exemplary embodiment of the present invention. The integrated circuit die  207  includes a plurality of passive component bond pads  209 A and a plurality of passive components  209 B fabricated on the back side of the integrated circuit die  207 .  
         [0019]     Electrical connections are made from the plurality of passive components  209 B through the plurality of passive component bond pads  209 A to the plurality of BGA vias  205  to the plurality of BGA balls  203 . Connections between the plurality of passive component bond pads  209 A and the plurality of BGA vias  205  occurs through, for example, conductive epoxy, solder, conductive polymers, metal-to-metal bonding, etc.  
         [0020]     Integrated circuit devices (not shown) are fabricated on the front side of the integrated circuit die  207 . A plurality of bond wires  211  connect the front side integrated circuit devices to the BGA substrate  201 . The BGA substrate  201  and the integrated circuit die  207  are protected with an encapsulant  213 .  
         [0021]     In  FIG. 3 , a Quad Flat-Pack No-Lead (QFN) package  300  includes a QFN substrate  301  with a plurality of contact pads  303 . The QFN package type is generally known in the art. Mounted to the QFN substrate  301  is an integrated circuit die  307  fabricated in accordance with an exemplary embodiment of the present invention. The integrated circuit die  307  includes a plurality of passive component bond pads  305 A and a plurality of passive components  305 B fabricated on the back side of the integrated circuit die  307 . Electrical connections are made from the plurality of passive components  305 B through the plurality of passive component bond pads  305 A to the plurality of contact pads  303 . Connections between the plurality of passive component bond pads  305 A and the plurality of contact pads  303  are through, for example, conductive epoxy, solder, conductive polymers, metal-to-metal bonding, etc.  
         [0022]     Integrated circuit devices (not shown) are fabricated on the front side of the integrated circuit die  307 . A plurality of bond wires  309  connect the front side integrated circuit devices to the QFN substrate  301 . The QFN substrate  301  and the integrated circuit die  307  are protected with an encapsulant  313 .  
         [0023]     Exemplary fabrication steps for producing integrated circuit dice according to various embodiments of the present invention are presented graphically with reference to  FIGS. 4A-4F . Using the techniques disclosed, integrated passive components may be readily produced using, for example, thin-film and plating techniques on the back side of a substrate (such as, for example, a silicon wafer). The substrate is then singulated into individual dice. An integrated circuit device is formed, using traditional fabrication techniques on a front side of the substrate. Integrated passive components are then fabricated on the back side of the substrate.  
         [0024]     In  FIG. 4A , the substrate  401  has integrated circuit devices  403  fabricated upon the front side of the substrate  401 . The integrated circuit devices  403  are optionally covered with a temporary coating  405 . The temporary coating  405  protects the integrated circuit devices  403  for later processing steps which occur on the back side of the substrate  401 . The temporary coating  405  may be, for example, an organic or metallic coating (e.g., photoresist or a deposited or sputtered metal layer).  
         [0025]     In  FIG. 4B , an optional dielectric material  407  is formed on the back side of the substrate  401 . The optional dielectric material may be either an organic or inorganic material. In a specific exemplary embodiment, the optional dielectric material  407  is a high-k dielectric material (e.g., zirconium-doped tantalum oxide, zirconium oxide, tantalum pentoxide, etc.) . A high-k dielectric layer increases the Q-factor of an inductor.  
         [0026]     With reference to  FIG. 4C , a metal seed layer  409  is applied to either the back side of the substrate  401  or to the optional dielectric material  407 . The metal seed layer  409  forms a seed metal layer for additional layers. The metal seed layer  409  may be, for example, an electrolytically plated metal layers such as a titanium-tungsten-copper (TiW-Cu,) layer. Skilled artisans will recognize that other metals may be selected. The metal seed layer  409  is then coated with photoresist. Various passive components may be patterned and etched leaving an etched photoresist layer  411 .  
         [0027]     In  FIG. 4D , a metal deposition  413  deposits metal into the open areas in the etched photoresist layer  411  thus forming a metal structure. The metal deposition  413  may be, for example, an electroplated layer comprised substantially of copper. Other techniques for forming one or more metal layers, for example, sputtering, may also be used. Additionally, other metals may be chosen so as to affect electrical characteristics of the passive component. For example, a metal having low conductivity may be used for forming resistive elements. Also, a combination of various metal types or metal alloys may be used in different geometric areas. A skilled artisan will recognize that certain types of metal may not require the metal seed layer  409 . In these cases, a patterned photoresist  411  may be applied directly to the back side of the substrate  401  and metal applied (e.g., deposited, sputtered, etc.) without a need for either the optional dielectric material  407  or the metal seed layer  409 . The choice of layers is dependent upon factors such as metal choice and metal-forming methods employed.  
         [0028]     In  FIG. 4E , the photoresist layer  411  may be stripped and exposed portions of the metal seed layer  409 , if used, are etched. Alternatively, the photoresist layer  411  may simply be left in place. If present, exposed portions of the optional dielectric material  407  are also removed. The temporary coating  405  ( FIGS. 4A-4E ) is removed as illustrated in  FIG. 4F .  
         [0029]     In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that embodiments of the present invention may be readily used in various types of semiconductor packaging such as Dual Flat-Pack No-Lead (DFN), QTAPP® (thin array plastic package), ULGA® (ultra-thin land grid array), BCC® (bumped chip carrier), or other package types. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.