Abstract:
A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority from Japanese application JP2011-123747 filed on Jun. 1, 2011, the content of which is hereby incorporated by reference into this application. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a display device. 
         [0004]    2. Description of the Related Art 
         [0005]    Liquid crystal displays are in wide use as display devices of information communication terminals, such as a computer or a television set receiver. In addition, an organic EL display (OLED), a field emission display (FED), and the like are also known as flat panel display devices. A liquid crystal display is a device in which the alignment of a liquid crystal composition sealed between two substrates is altered by changing an electric field and thus the extent of transmission for light passing through the two substrates and the liquid crystal composition is controlled, thereby displaying images. 
         [0006]    In a display device, including the liquid crystal display, applying a voltage corresponding to a predetermined grayscale value to each pixel of a screen, pixel transistors for applying a voltage corresponding to a grayscale value to each pixel are disposed. Generally, gates of the pixel transistors for one line of the screen are connected to a signal line (hereinafter, referred to as a “scanning signal line”), and the scanning signal line is controlled by a driving circuit so as to output an active voltage for turning on the pixel transistors sequentially line by line. In addition, there is a display device having a bidirectional scanning function capable of outputting the active voltage in both a forward direction and a backward direction so as to perform display by reversing upwards and downwards on the screen. 
         [0007]    JP8-55493 A discloses a circuit for realizing bidirectional scanning, and switches for changing the forward direction and backward direction are provided for each line. JP2008-276849 A discloses an image display device in which a circuit for performing the forward scanning is provided at one end of each scanning signal line and a circuit for performing the backward scanning is provided at the other end thereof in order to realize the bidirectional scanning. The specification of U.S. Pat. No. 5,859,630 discloses a circuit capable of performing bidirectional scanning, disposed on one side of a display region. 
       SUMMARY OF THE INVENTION 
       [0008]    In JP8-55493 A described above, two transistors are necessary for each line in order to switch the scanning directions, and, in JP2008-276849 A, driving circuits for performing scanning in the respective directions at both sides of the display region are necessary. Therefore, the scale of the circuit is inevitably increased. In addition, in the specification of U.S. Pat. No. 5,859,630, the circuit capable of performing bidirectional scanning is disposed on one side of the display region, and thus the scale of a circuit on one side is increased. In recent years, there has been demand for reduction in a bezel region which is a peripheral region of the display region, and an increase in the scale of the circuit prevents a reduction in the bezel region and causes an increase in power consumption. 
         [0009]    The present invention has been made in consideration of the circumstances, and an object thereof is to provide a display device having a driving circuit which can perform bidirectional scanning and reduce the scale of the circuit. 
         [0010]    According to an aspect of the present invention, there is provided a display device including a driving circuit that sequentially applies an active potential for turning on a pixel transistor to a plurality of output signal lines, wherein the driving circuit includes a first output signal line, a second output signal line, and a third output signal line that are the plurality of output signal lines and are three output signal lines which are continuously arranged; a first clock signal line to which a first clock signal which is a clock signal is applied; a second clock signal line to which a second clock signal which is a clock signal whose active potential does not temporally overlap the active potential of the first clock signal is applied; a first transistor that is a transistor of which one of the source and the drain is directly or indirectly connected to the second output signal line and the other of the source and the drain is directly or indirectly connected to the first clock signal line; and a second transistor that directly or indirectly provides a non-active potential to a gate of the first transistor when the second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at the opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is directly or indirectly connected to the first output signal line and the third output signal line via rectifying circuits, respectively. 
         [0011]    In the display device according to the aspect of the present invention, the first output signal line may output the active potential when a third clock signal which is a clock signal whose active potential does not temporally overlap the active potential of the first and second clock signals is applied thereto. In addition, the third output signal line may output the active potential when a fourth clock signal which is a clock signal whose active potential does not temporally overlap the active potential of the first to third clock signals is applied thereto. Further, when the active potential is output in order of the first output signal line, the second output signal line and the third output signal line, the first to fourth clock signals may be four-phase clocks which become the active potential in order of the third clock signal, the first clock signal, the fourth clock signal and the second clock signal, and, when the active potential is output in order of the third output signal line, the second output signal line and the first output signal line, the first to fourth clock signals may be four-phase clocks which become the active potential in order of the fourth clock signal, the first clock signal, the third clock signal and the second clock signal. 
         [0012]    In the display device according to the aspect of the present invention, a transistor for voltage resistance whose gate is fixed to an intermediate voltage of which the absolute value is smaller than the active potential may be provided between the gate of the first transistor and either of the source and the drain of the second transistor. 
         [0013]    In the display device according to the aspect of the present invention, a transistor for voltage decrease whose gate is fixed to an intermediate voltage of which the absolute value is smaller than the active potential may be provided between the second clock signal line and a gate of a transistor which outputs a low potential to the second output signal line during a period when the second output signal line does not output the active potential. 
         [0014]    In the display device according to the aspect of the present invention, the first transistor and a transistor which outputs a low potential to the second output signal line during a period when the second output signal line does not output the active potential may be divided by a last stage circuit block. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a diagram schematically illustrating a liquid crystal display according to an embodiment of the present invention. 
           [0016]      FIG. 2  is a diagram illustrating a configuration of a liquid crystal panel. 
           [0017]      FIG. 3  is a diagram schematically illustrating a configuration of a driving circuit. 
           [0018]      FIG. 4  is a detailed diagram illustrating a circuit configuration of a circuit block of a left driving circuit. 
           [0019]      FIG. 5  is a diagram illustrating a circuit configuration of an initial stage circuit block which is an initial stage of the circuit. 
           [0020]      FIG. 6  is a diagram illustrating a circuit configuration of a last stage circuit block which is a last stage of the circuit. 
           [0021]      FIG. 7  is a diagram illustrating an operation timing chart when a circuit of the circuit block shown in  FIG. 4  performs forward scanning. 
           [0022]      FIG. 8  is a diagram illustrating an operation timing chart when a circuit of the circuit block shown in  FIG. 4  performs backward scanning. 
           [0023]      FIG. 9  is a diagram illustrating a circuit block which is a modified example of the circuit block of the left driving circuit. 
           [0024]      FIG. 10  is a diagram illustrating a circuit block which is a modified example of the circuit block of the left driving circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]    Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the drawings, the same or equivalent elements are given the same reference numerals, and repeated description will be omitted. 
         [0026]      FIG. 1  schematically shows a liquid crystal display  100  according to an embodiment of the present invention. As shown in this figure, the liquid crystal display  100  includes an upper frame  110 , a lower frame  120 , a liquid crystal panel  200  fixed so as to be interposed therebetween, and a backlight device (not shown). 
         [0027]      FIG. 2  shows a configuration of the liquid crystal panel  200  shown in  FIG. 1 . The liquid crystal panel  200  includes two substrates of a TFT (Thin Film Transistor) substrate  220  and a color filter substrate  230 , and a liquid crystal composition is sealed between the substrates. The TFT substrate  220  is provided with a driving circuit  210  which sequentially applies a predetermined voltage to scanning signal lines G 1  to G n , and a driving IC (Integrated Circuit)  260  which applies a voltage corresponding to a grayscale value of a pixel to a plurality of data signal lines (not shown) extending so as to intersect the scanning signal lines G 1  to G n  in a pixel region  202  and controls the driving circuit  210 . In addition, the driving circuit  210  includes a right driving circuit  212  located on the right side of the pixel region  202  in the figure and a left driving circuit  214  located on the left side of the pixel region. 
         [0028]      FIG. 3  is a diagram schematically illustrating a circuit configuration of the driving circuit  210 . The right driving circuit  212  is a driving circuit which applies a high voltage (active voltage) for electrically connecting sources and drains of TFTs to gates of the TFTs disposed at each pixel in relation to odd-numbered scanning signal lines G 2i−1  (where i is a natural number) and the left driving circuit  214  is a driving circuit which applies a high voltage for electrically connecting sources and drains of TFTs to gates of the TFTs disposed at each pixel in relation to even-numbered scanning signal lines G 2i . Except for a start signal VST, the right driving circuit  212  performs an output using an output of the left driving circuit  214  as a trigger, and the left driving circuit  214  performs an output using an output of the right driving circuit  212  as a trigger. The right driving circuit  212  is driven by clock signals CK 1  and CK 3 , and the left driving circuit  214  is driven by clock signals CK 2  and CK 4 . In addition, the clock signals CK 1  to CK 4  are four-phase clocks which become a high voltage in order of CK 1 , CK 2 , CK 3 , and CK 4  during forward scanning, and are four-phase clocks which become an active voltage in order of CK 4 , CK 3 , CK 2  and CK 1  during backward scanning. 
         [0029]    The forward scanning starts by the right driving circuit  212  outputting a high voltage to the scanning signal line G 1  and finishes by the left driving circuit  214  outputting a high voltage to the scanning signal line G n . The backward scanning starts by the left driving circuit  214  outputting a high voltage to the scanning signal line G n  and finishes by the right driving circuit  212  outputting a high voltage to the scanning signal line G 1 . In addition, the right driving circuit  212  includes an initial stage circuit block  216  in the initial stage, a plurality of circuit blocks  213  outputting a high voltage to the odd-numbered scanning signal lines G 2i−1 , and a last stage circuit block  217  in the last stage. The circuit blocks  213  receive signals of three consecutive even-numbered scanning signal lines G 2i−2  G 2i  and G 2i+2  and output signals of two consecutive odd-numbered scanning signal lines G 2i−1  and G 2i+1 . The left driving circuit  214  includes an initial stage circuit block  216  in the initial stage, a plurality of circuit blocks  215  outputting a high voltage to the even-numbered scanning signal lines G 2i , and a last stage circuit block  217  in the last stage. The circuit blocks  215  receive signals of three consecutive odd-numbered scanning signal lines G 2i−1 , G 2i+1  and G 2i+3 , and output signals of two consecutive even-numbered scanning signal lines G 2i  and G 2i+2 . 
         [0030]      FIG. 4  shows a circuit configuration of the circuit block  215  of the left driving circuit  214  in detail. Here, the names of the terminals shown in  FIG. 4  are changed not to the names of the terminals of the circuit block  215  in  FIG. 3  but to the names of the external terminals of the driving circuit  210  in  FIG. 3  in order to make a description with reference to the timing chart of  FIG. 7  described later. As shown in  FIG. 4 , the circuit block  215  is a circuit operated by two clocks CK 2  and CK 4 , and shows two portions outputting a high voltage to two scanning signal lines G 2i  and G 2i+2 . In addition, the letter T denotes a transistor, and the letter N denotes a node. Further, each transistor is made of LTPS (Low Temperature Poly Silicon). 
         [0031]    As shown in this figure, the circuit for outputting a high voltage to the scanning signal line G 2i  includes a diode transistor T 1  which is a rectifying circuit input during forward scanning, a transistor T 2  which fixes a gate electrode of a transistor T 5  described later to a voltage VGL, a transistor T 3  which charges a storage node N 3  a storage node reset transistor T 4 , the transistor T 5  which outputs a high voltage to the gate line, a transistor T 6  which fixes the gate line to the voltage VGL using the storage node, a transistor T 7  which resets the storage node using an input signal during the forward scanning, an initial reset transistor T 8 , a transistor T 9  for resetting the gate electrode of the transistor T 5 , a voltage mitigation transistor T 10  which restricts a voltage increased by the transistor T 5  to an intermediate voltage VDH, a transistor T 11  which decreases a voltage charged by the transistor T 3  to the intermediate voltage VDH, a diode transistor T 12  which is a rectifying circuit input during backward scanning, and a transistor T 13  which resets the storage node using an input signal during the backward scanning. In addition, the intermediate voltage VDH turns on the transistor, but is lower than the gate line high voltage VGH. In the drawings, the intermediate voltage VDH and the voltage VGL are suffixed with letter “L”. The letter L denotes belonging to left driving circuit  214 . 
         [0032]      FIG. 5  shows a circuit configuration of the initial stage circuit block  216  which is an initial stage of the circuit. The initial stage circuit block  216  has a configuration where the initial reset transistor T 8  is not provided as compared with the circuit block  215 . 
         [0033]      FIG. 6  shows a circuit configuration of the last stage circuit block  217  which is a last stage. The last stage circuit block  217  has a configuration where transistors T 14  and T 15  connected to inspection terminals are further provided as compared with the circuit block  215 . 
         [0034]    In addition,  FIG. 7  shows a timing chart of an operation of the circuit for one stage of the circuit block  215  in  FIG. 4  for outputting a high voltage to the scanning signal line G 2i . Hereinafter, an operation of the circuit in  FIG. 4  will be described with reference to the timing chart of  FIG. 7 . 
         [0035]    First, in the circuit block  215 , at the timing t 1 , the high voltage of the start signal VST_L is input to the left driving circuit  214  so as to set the voltage of the storage node N 3  to be high as a reset operation. Next, at the timing t 2 , when the high voltage of the scanning signal line G 2i−1  is input, the transistor T 7  is first turned on, in turn a low voltage VGL_L is applied to the node N 3  such that the node N 3  becomes the low voltage, the transistor T 1  is turned on, and the node N 1  becomes a high voltage and is maintained thereat. Therefore, the node N 2  becomes a high voltage via the transistor T 10  of which the gate is supplied with the intermediate voltage VDH, and thus the transistor T 5  is turned on. 
         [0036]    Next, at the timing t 3 , when the clock signal CK 2  becomes a high voltage, the voltage of the node N 2  which is the gate of the transistor T 5  is further increased due to a so-called bootstrap effect, a high signal is output to the scanning signal line G 2i , and then a low signal is output thereto following an operation of the clock signal CK 2 . 
         [0037]    Next, at the timing t 4 , when the clock signal CK 4  becomes high, the transistor T 3  is turned on, the node N 3  rises to a high level, and the transistor T 9  is turned on. Therefore, the node N 1  falls to a low level. The node N 1  makes the node N 2  fall to a low level via the transistor T 10  so as to decrease the voltage between the source and the drain of the transistor T 2 , and the transistor T 6  is turned on by the high voltage of the node N 3 . Therefore, the scanning signal line G 2i  is supplied with a low voltage VGL_L and is thus fixed to the low voltage. 
         [0038]    Here, the transistor T 10  has high voltage resistance as a double-gate configuration formed by overlapping two transistors so as to resist the increased voltage due to the clock signal CK 2  becoming high. The high signal output to the scanning signal line G 2i  is an input signal of the circuit block  213  of the right driving circuit  212 , which outputs a high signal to the scanning signal line G 2i+1  through an operation equivalent to the above-described operation. 
         [0039]      FIG. 8  shows a timing chart when the circuit block  215  performs the backward scanning from the scanning signal line G n  to the scanning signal line G 1 . Except that the phases of the clock signals CK 1  to CK 4  differ and become high in reverse order, the timing chart during backward scanning is also the same as that during forward scanning. Hereinafter, an operation of the circuit in  FIG. 4  will be described with reference to the timing chart of  FIG. 8 . 
         [0040]    First, in the circuit block  215 , at the timing t 5 , a high voltage of the start signal VST_L is input to the left driving circuit  214  so as to set the voltage of the storage node N 3  to be high as a reset operation. Next, at the timing t 6 , when the high voltage of the scanning signal line G 2i+1  is input, the transistor T 13  is first turned on, a low voltage VGL_L is applied to the node N 3  such that the node N 3  becomes the low voltage, in turn the transistor T 12  is turned on, and the node N 1  becomes a high voltage and is maintained thereat. Therefore, the node N 2  becomes a high voltage via the transistor T 10  of which the gate is supplied with the intermediate voltage VDH, and thus the transistor T 5  is turned on. 
         [0041]    Next, at the timing t 7 , when the clock signal CK 2  becomes a high voltage, the voltage of the node N 2  which is the gate of the transistor T 5  is further increased due to a so-called bootstrap effect, a high signal is output to the scanning signal line G 2i , and then a low signal is output thereto following an operation of the clock signal CK 2 . 
         [0042]    Next, at the timing t 8 , when the clock signal CK 4  becomes high, the transistor T 3  is turned on, the node N 3  rises to a high level, and the transistor T 9  is turned on. Therefore, the node N 1  falls to a low level. The node N 1  makes the node N 2  fall to a low level via the transistor T 10  so as to decrease a voltage between the source and the drain of the transistor T 2 , and the transistor T 6  is turned on by the high voltage of the node N 3 . Therefore, the scanning signal line G 2i  is supplied with a low voltage VGL_L and is thus fixed to the low voltage. 
         [0043]    As described above, since, in the embodiment of the present invention, the driving circuit applying a high signal to the odd-numbered scanning signal lines and the driving circuit applying a high signal to the even-numbered scanning signal lines are disposed with the pixel region interposed therebetween, the scale of the circuit can be reduced to a half of the case where the driving circuit is disposed on one side of the pixel region, and thus the bezel region of the display device can be reduced. 
         [0044]    In addition, since the circuit performing the forward scanning and the circuit performing the backward scanning use the same circuit, a circuit performing the backward scanning is not required to be disposed, and thus it is possible to reduce the scale of the circuit and to thereby reduce the bezel region of the display device. 
         [0045]    In addition, since the circuit block has the double-gate configuration formed by overlapping transistors, a high voltage resistance circuit can be formed even using LTPS. 
         [0046]      FIG. 9  shows a circuit block  301  which is a modified example of the circuit block  215  of the left driving circuit  214  according to the above-described embodiment. A difference from the circuit block  215  is that the transistor T 8  is not provided, and the transistor T 8  is provided for charging the storage node N 3  using the start signal VST_L in the above-described embodiment. However, since all the clock signals CK 1  to CK 4  become a high voltage and thereby the storage node N 3  can be charged, it is possible to further reduce the scale of the circuit with the configuration where the transistor T 8  is not provided. 
         [0047]      FIG. 10  shows a circuit block  302  which is a modified example of the circuit block  215  of the left driving circuit  214  according to the above-described embodiment. A difference from the circuit block  215  is that the transistor T 11  is not provided, and the transistor T 11  is disposed such that the high voltage of the clock signal CK 4  is not directly applied to the gates of the transistors T 2  and T 6 . However, in a case where a manufacturing line is suppressed from being contaminated with Na, it is possible to further reduce the scale of the circuit with the configuration where the transistor T 11  is not provided. 
         [0048]    In addition, although the above-described embodiment uses an NMOS type transistor whose source and drain are electrically connected to each other by inputting a high voltage to a gate thereof as an active voltage, a PMOS type transistor whose source and drain are electrically connected to each other by inputting a low voltage to the gate thereof as an active voltage may be used. 
         [0049]    Further, although, in the above-described embodiment, the clock signals use four kinds of four-phase clocks, other two or more kinds of clock signals may be used. 
         [0050]    The liquid crystal display according to the respective embodiments may be applied to liquid crystal displays of any type of an IPS (In-Plane Switching) type, a VA (Vertically Aligned) type, and a TN (Twisted Nematic) type. In addition, the present invention is not limited to the liquid crystal display, and may be applied to an organic EL display, a field emission display (FED), and other display devices using the driving circuit. 
         [0051]    While there have been described what are at present considered to be certain embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claim cover all such modifications as fall within the true spirit and scope of the invention.