Abstract:
An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and a charge transferring transistor. The charge transferring transistor may be a dual gate transistor having first and second gate terminals. A suitable bias may be applied to the second gate terminal to alter the capacitance of the floating diffusion node. The amount of electrons that may be accommodated by the floating diffusion node may be altered with application of a varying voltage level bias at the second gate terminal. By implementing a dual gate transistor, dynamic range compression and anti-blooming charge overflow may be implemented directly in the pixel to reduce image sensor pixel size and cost.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This application claims priority to U.S. Provisional Application No. 62/241,862, filed on Oct. 15, 2015, entitled “Image Sensor Pixels Having Dual Gate Charge Transferring Transistors,” invented by Jaroslav Hynecek, and is incorporated herein by reference and priority thereto for common subject matter is hereby claimed. 
     
    
     BACKGROUND 
       [0002]    This relates to solid-state image sensor arrays and, more specifically, to complementary metal-oxide semiconductor (CMOS) image sensor arrays that are illuminated from the back side or the front side of a corresponding image sensor substrate. The image sensor pixels have incorporated therein a mechanism to drain overflow charge away from the image sensor pixels, thereby preventing charge from spilling into neighboring pixels in the array when a particular pixel or a group of pixels is overexposed. The invention describes in detail a charge transferring gate structure resulting in an improved overflow charge control that is particularly suitable for small size pixels illuminated from the back side of the substrate. The new transfer gate structure allows introducing the signal dynamic range compression directly into the pixel. 
         [0003]    Typical image sensors sense light by converting impinging photons into electrons (or holes) that are integrated (collected) in sensor pixels. Upon completion of each integration cycle, the collected charge is converted into voltage signals, which are supplied to corresponding output terminals associated with the image sensor. Typically, this charge-to-voltage conversion is performed directly within the pixels, and the resulting analog pixel voltage signals are transferred to the output terminals through various pixel addressing and scanning schemes. The analog pixel voltage signals can sometimes be converted on-chip to a digital equivalent before being conveyed off-chip. Each pixel includes a buffer amplifier (i.e., source follower) that drives output sensing lines that are connected to the pixels via respective addressing transistors. 
         [0004]    After charge-to-voltage conversion is completed and after the resulting signals are transferred out from the pixels, the pixels are reset before a subsequent new charge is accumulated. In pixels that include floating diffusions (FD) serving as a charge detection node, this reset operation is accomplished by momentarily turning on a reset transistor that connects the floating diffusion node to a voltage reference (typically the pixel source follower current drain node) for draining (or removing) any charge transferred onto the floating diffusion node. However, removing charge from the floating diffusion node using the reset transistor generates thermal kTC-reset noise. This kTC reset noise is removed using correlated double sampling (CDS) signal processing techniques in order to achieve desired low noise performance. Typical CMOS image sensors that utilize CDS require three transistors (3T) or four transistors (4T) per pixel, one of which serves as a charge transferring transistor. It is possible to share some of the pixel circuit transistors among several photodiodes, which also reduces the pixel size. 
         [0005]    It is typically necessary for image sensors to simultaneously satisfy three requirements. In particular, image sensors need to accumulate holes to reduce dark current, provide an efficient blooming control, and guarantee complete charge transfer from the photodiode when the transfer gate is turned fully on. These three requirements are not easily satisfied simultaneously, which typically results in some pixel performance sacrifice. Another problem is that once the pixel is designed and manufactured with a particular transfer gate length and doping levels, the blooming performance of the pixel is fixed and cannot be changed. This typically results in some sacrifice of the pixel charge well capacity that has to be built into the pixel to serve as a margin for effective anti-blooming operations. 
         [0006]    It would therefore be desirable to be able to provide improved image sensor pixel designs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is an example of a simplified cross-sectional side view of an image sensor pixel consisting of a photodiode, a charge transfer gate, a floating diffusion, a retrograde doped BTP p-well, a p+ dark current back side quenching layer, and pixel isolation implants. 
           [0008]      FIG. 2  is a circuit diagram of a pixel of the type shown in  FIG. 1 . 
           [0009]      FIG. 3  is a cross-sectional side view of an illustrative pixel having a dual gate charge transfer transistor structure that provides modulation of the punch-through potential based on a second transfer gate bias in accordance with an embodiment. 
           [0010]      FIG. 4  is a circuit diagram of a pixel of the type shown in  FIG. 3  in accordance with an embodiment. 
           [0011]      FIG. 5  is an illustrative graph showing the relationship between the number of electrons collected in a pixel photodiode of the type shown in  FIGS. 3 and 4  and the corresponding output voltage from the pixel during charge readout in accordance with an embodiment. 
           [0012]      FIG. 6  is a block diagram of a processor system employing the image sensor pixels of  FIGS. 3-5  in accordance with an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]      FIG. 1  shows a simplified circuit diagram of a pixel  100  in one arrangement of a CMOS image sensor. The diagram of  FIG. 1  illustrates pixel regions such as the pixel photodiode that collects photon-generated carriers, the charge transferring (Tx) gate  104  of the charge transferring transistor, and the floating diffusion (FD)  109 . Pixel  100  may be fabricated within substrate  101 , which has a p+ type doped layer  102  deposited on the back side surface of the substrate. Layer  102  may prevent generation of excessive dark current by the interface states. The device substrate may further include epitaxial p− type doped layer  119  situated above p+ type doped layer  102 . Photons  122  that enter this region may generate charge carriers  120  that are collected in the potential well of the photodiode (PD) formed in region  106 . The surface of epitaxial layer  119  may be covered by oxide layer  103  that isolates doped poly-silicon charge transferring gate  104  from the substrate. Poly-silicon gate  104  may have spacers  110  formed at the gate edges that serve as a patterning mask separating the edge of p+ type doped photodiode pinning implant  105  from the n-type doped implant  106  in which the potential well for storing electrons is formed. 
         [0014]    The photodiode may be formed by n− type doped layer  106  and p+ type doped potential pinning layer  105  which, similar to p+ type doped layer  102 , also reduces interface states generated dark current. Pinning layer  105  may extend to the edge of the pixel and may join with p+ type doped pixel separation implant region  121 . The complete pixel separation may be further accomplished by p+ type (BTP) retrograde doped layer  107 , which extends under transfer gate  104  and under floating diffusion  109 , and by implants  108  that extend all the way to the bottom of the pixels and join with p+ type doped layer  102 . The photodiode bulk depletion region is indicated in  FIG. 1  by dashed line  111 . Floating diffusion diode  109  senses charge transferred from the photodiode and may be connected to the pixel source follower transistor gate (not shown in  FIG. 1  for the sake of drawing simplicity). The floating diffusion, the source follower, and the remaining pixel circuit components may all be built into the p-type doped well with retrograde p+ type doped BTP region  107  that diverts the photon generated carriers into the photodiode potential well located in layer  106 , and thus prevents their loss. The whole pixel may be covered by several inter-level (IL) oxide layers  115  (only one of which is shown in  FIG. 1  for the sake of drawing simplicity) that are used for the pixel metal wiring and interconnect isolation. The pixel active circuit components may be connected to the wiring by metal via plugs  117  deposited through contact holes  116 . 
         [0015]    Blooming control in pixel  100  may be accomplished in several ways, such as by continuously pulsing the charge transferring gate  104  from an off state to a partial on state to drain off some of the accumulated charge (which has already almost filled the photodiode well) to floating diffusion  109 , and from floating diffusion  109  through the reset means to the pixel source-follower drain node. Another method of blooming control is to form a buried channel region under charge transferring gate  104  between the photodiode n− type doped layer  106  that is integrating charge and floating diffusion region  109 . This buried channel may be built above p+ type doped BTP layer  107  by a suitable n-type doped implant or may be formed naturally when floating diffusion  109  and layer  106  are sufficiently close together. The current path for the overflow electrons is shown in  FIG. 1  by arrow  114 . This path may occur at the location where depletion region  112  from n-type doped photodiode region  106  is closest to floating diffusion depletion region  113 . 
         [0016]      FIG. 2  shows an equivalent circuit diagram  200  of the pixel  100  shown in  FIG. 1 . As shown in  FIG. 2 , photodiode  201  accumulates the photon generated charge and may be connected to floating diffusion node  206  (shown as capacitor Cn) by charge transferring transistor  202 . It is also possible to connect several photodiodes and several charge transferring transistors to the same charge detection node. Floating diffusion node  206  may be connected to the gate of source follower transistor  203  which has a drain that is connected to column Vdd drain bias line  211 . The source of source follower transistor  203  may be connected through row select transistor  204  to column sense line  210 . Floating diffusion node  206  may be reset by reset transistor  205  that is connected between floating diffusion node  206  and column drain bus  211 . The gate of charge transferring transistor  202  may receive charge transfer control signals from row bus line  209 , the gate of reset transistor  205  may receive reset control signals from row bus line  208 , and the gate of addressing transistor  204  may receive addressing control signals from row bus line  207 . 
         [0017]    A simplified cross sectional diagram of an illustrative image sensor pixel of one invention embodiment is shown in  FIG. 3 . As shown in  FIG. 3 , image sensor pixel  300  may include a pixel photodiode that collects photon generated carriers, a floating diffusion such as floating diffusion node  309 , and a dual gate charge transfer transistor that includes a first charge transferring gate  304  and a second charge transferring gate  322 . First charge transferring gate  304  may receive a first charge transfer control signal Tx 1  whereas second charge transferring gate  322  receives a second charge transfer control signal Tx 2 . The pixel may be fabricated within substrate  301 , which may include p+ type doped layer  302  deposited on a back side surface. This layer may prevent the generation of excessive dark current by the interface states. The device substrate may further include epitaxial p− type doped layer  319  situated above p+ type doped layer  302 . Photons  325  that enter this region may generate carriers  320  that are collected in the potential well of the photodiode formed in region  306 . The surface of epitaxial layer  319  may be covered by oxide layer  303  which isolates the doped poly-silicon charge transferring gates  304  and  322  from the substrate. The poly-silicon gates may have spacers  310  formed at the gate&#39;s edges that serve as a patterning mask separating the edge of the n+ type doped floating diffusion region from the charge transferring gate  322  and separating the edge of p+ type doped photodiode pinning implant  305  from n− type doped implant  306  (e.g., where the potential well for storing electrons is formed). 
         [0018]    The photodiode may be formed by n− type doped layer  306  and p+ type doped potential pinning layer  305 . Similarly to p+ type doped layer  302 , p+ type doped potential pinning layer  305  may reduce interface states generated dark current. Pinning layer  305  may extend to the edge of the pixel and join with p+ type doped pixel separation implants  321 . Complete pixel separation may be further accomplished by p+ type (BTP) retrograde doped layer  307  and implants  308 . P+ type retrograde doped layer  307  may extend under transfer gate  304 , transfer gate  322 , and under floating diffusion  309 . Implants  308  may extend all the way to the bottom of the pixels and join with p+ type doped layer  302 . The photodiode bulk depletion region is indicated in pixel  300  by dashed line  311 . Floating diffusion  309  may sense charge transferred from the photodiode and may be connected to the pixel source follower transistor gate (not shown in  FIG. 3  for the sake of drawing simplicity). The floating diffusion, the source follower, and the remaining pixel circuit components may be built in the p-type doped well which may include retrograde p+ type doped region  307 . Retrograde p+ type doped region  307  may divert the photon generated charge into the photodiode potential well located in layer  306  and thus prevent their loss. The whole pixel may be covered by several inter-level (IL) oxide layers  315  (only one is shown in  FIG. 3  for the sake of drawing simplicity) that may be used for the pixel metal wiring and interconnect isolation. The pixel active circuit components may be connected to the wiring by metal via plugs  317  deposited through contact holes  316 . 
         [0019]    Blooming control in pixel  300  may be accomplished by modulating the punch-through potential under transferring gates  304  and  322  by changing the bias of the second charge transferring gate  322  during the charge integration period. The current path for the overflow electrons is shown in the drawing by arrow  314  and may occur at the place where depletion region  312  from the photodiode is closest to depletion region  313  from the floating diffusion. The position of the edge of depletion region  313  may be shifted by the gate bias Tx 2  as indicated by arrow  324 . A larger distance between the depletion layer edges represents lower overflow current whereas a smaller distance between the depletion layer edges represents a higher overflow current. During the charge integration cycle, the interface between the silicon and silicon dioxide under the charge transferring gate  304  may be filled with holes as indicated by region  318 . This may be necessary for the reduction of dark current. Accumulation of holes may be accomplished by a suitable negative charge transferring gate bias Tx 1  and by a threshold shift implant. 
         [0020]    Dynamic range compression in pixel  300  may be accomplished by providing a positive bias Tx 2  for charge transferring gate  322  during readout. When a larger amount of charge is transferred onto the floating diffusion from the photodiode, the floating diffusion potential may be lowered from its reset level. When the floating diffusion potential becomes lower than the potential under the charge transferring gate  322 , electrons from the floating diffusion may flow under this gate as indicated by region  323 . This may cause the floating diffusion capacitance to increase and the corresponding charge conversion factor to decrease. It is thus possible to select a suitable DC bias for the charge transfer control signal Tx 2  provided to gate  323  during the readout period (e.g., to control the potential and the number of electrons at which the pixel conversion gain changes from its high level to a lower level). This is shown in more detail in  FIG. 5 . 
         [0021]    A simplified circuit diagram of an illustrative image sensor pixel such as pixel  300  of  FIG. 3  is shown in  FIG. 4 . As shown in  FIG. 4 , photodiode  401  that accumulates the photon generated charge may be connected to the floating diffusion node  406  (shown as capacitor Cn) by the charge transferring transistor  402 . Transistor  402  may be a dual gate charge transferring transistor having first and second charge transferring gates that receive control signals Tx 1  and Tx 2  respectively. It may also be possible to connect several photodiodes and several charge transferring transistors to the same charge detection node using the single gate charge transferring transistors or a dual gate charge transferring transistors. Floating diffusion node  406  may be coupled to the gate of the source follower transistor  403 . The drain of source follower transistor  403  may be coupled to column Vdd drain bias line  411 . The source of source follower transistor  403  may be coupled through row select transistor  404  to column sense line  410 . Floating diffusion node  406  may be reset by reset transistor  405  that is connected between floating diffusion node  406  and column drain bus  411 . The gates of the charge transferring transistor  402  (e.g., gates  304  and  322  as shown in  FIG. 3 ) may receive charge transfer control signals Tx 1  and Tx 2  over row bus lines  409  and  410  respectively. The gate of reset transistor  405  may receive reset control signals from row bus line  408 . The gate of addressing transistor  404  may receive addressing control signals Sx over row bus line  407 . 
         [0022]      FIG. 5  shows an illustrative graph  500  illustrating the relation between the number of electrons transferred from the photodiode onto the floating diffusion and the corresponding pixel output voltage change. As shown in  FIG. 5 , curve  501  represents the conversion gain characteristic of the pixel when charge transferring gate bias Tx 2  is provided to second charge transferring gate  322  at a relatively low voltage level during readout. Curve  502  represents the conversion gain characteristic of the pixel when charge transfer gate bias Tx 2  is provided to second charge transferring gate  322  at an intermediate voltage level that is greater than the relatively low voltage level during readout. Curve  504  represents the conversion gain characteristic of the pixel when charge transferring gate bias Tx 2  is provided to second charge transferring gate  322  at a relatively high voltage level that is greater than the intermediate voltage level during readout. When the DC bias Tx 2  applied to charge transferring gate  322  during a readout period is at its minimum level (e.g., the relatively low voltage level of curve  501 ), the floating diffusion may accommodate approximately 3000 electrons. When DC bias Tx 2  is applied to charge transferring gate  322  at a relatively high level (e.g., as shown by curve  504 ), the floating diffusion may accommodate approximately 12,000 electrons. Curve  504  may represent the condition when charge transferring gate  322  is at its off biasing condition during readout. Line  505  may represent the condition when charge transferring gate  322  is at its fully on biasing condition during readout. These numbers are merely illustrative examples and may depend on the particular charge transferring gate design. 
         [0023]      FIG. 6  shows in simplified form a typical processor system  1000 , such as a digital camera, which includes an imaging device such as imaging device  1001  (e.g., an imaging device  1001  such as an image sensor that includes pixels with dual gate charge transferring transistors as described above in connection with  FIGS. 3-6 ). Processor system  1000  is exemplary of a system having digital circuits that could include imaging device  1001 . Without being limiting, such a system could include a computer system, still or video camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other systems employing an imaging device. 
         [0024]    Processor system  1000 , which may be a digital still or video camera system, may include a lens such as lens  1096  for focusing an image onto a pixel array when shutter release button  1097  is pressed. Processor system  1000  may include a central processing unit such as central processing unit (CPU)  1095 . CPU  1095  may be a microprocessor that controls camera functions and one or more image flow functions and communicates with one or more input/output ( 110 ) devices  1091  over a bus such as bus  1093 . Imaging device  1001  may also communicate with CPU  1095  over bus  1093 . System  1000  may include random access memory (RAM)  1092  and removable memory  1094 . Removable memory  1094  may include flash memory that communicates with CPU  1095  over bus  1093 . Imaging device  1001  may be combined with CPU  1095 , with or without memory storage, on a single integrated circuit or on a different chip. Although bus  1093  is illustrated as a single bus, it may be one or more buses or bridges or other communication paths used to interconnect the system components. 
         [0025]    Various embodiments have been described illustrating an imaging system (e.g., image sensor pixel array) which that has the capability of controlling anti-blooming by changing the bias of a second gate of a dual gate charge transferring transistor during the charge integration period, and that also has the capability of in-pixel dynamic range compression. 
         [0026]    The image sensor pixel may include a photodiode that generates charge in response to image light, a floating diffusion node, and a charge transferring transistor configured to transfer the generated charge from the photodiode to the floating diffusion node. The charge transferring transistor may be a dual gate transistor having first and second gates (e.g., gate terminals). 
         [0027]    The dual gate transistor may have a first gate adjacent to the photodiode and a second gate adjacent to the floating diffusion node. The first gate may be negatively biased to fill the interface between the silicon and silicon dioxide under the first gate with holes to reduce dark current. Blooming control in the image sensor pixel may be accomplished by modulating the punch-through potential under the gates of the charge transferring transistor and by changing the bias of the second charge transferring gate during the charge integration period. 
         [0028]    A positive bias may be applied to the second gate of the charge transferring transistor to control the dynamic range of the image sensor pixel. A suitable bias may be provided to the second gate during the readout period to control the potential and the number of electrons at which the pixel conversion gain changes from its high to low level. The bias may cause electrons to flow under the second gate and alter the capacitance and charge conversion factor of the floating diffusion node. 
         [0029]    The foregoing description is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The foregoing embodiments may be implemented individually or in any combination.