Abstract:
Apparatuses are disclosed which comprise a coarse tuning circuitry, a fine tuning circuitry and at least one switchable capacitance.

Description:
FIELD OF THE INVENTION 
     The present application relates to oscillators with controllable frequency, circuits like phase locked loops (PLLs) incorporating such oscillators and associated methods. 
     BACKGROUND 
     Controllable oscillators (COs) generally are oscillators which output one or more output signals with a frequency, said frequency being determined by a control signal supplied to the controllable oscillator. Examples for controllable oscillators are voltage-controlled oscillators (VCOs) where the control signal is a voltage signal or digitally controlled oscillators (DCOs) and numerically controlled oscillators (NCOs) where the control signal is a digital signal. 
     Such controllable oscillators are for example controlled by a phase locked loop (PLL) to generate an output signal with a phase and/or frequency having a predetermined relationship with a phase and/or frequency of a reference signal supplied to the phase locked loop. 
     In PLLs generally the phase of the reference signal and a phase of a signal corresponding to or derived from an output signal of a controllable oscillator are aligned. For example in narrowband PLLs where the frequency range of the oscillator is comparatively small, it may take a relatively long time until phase alignment (also referred to as locking of the PLL) is reached. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  shows a schematic diagram of a phase locked loop circuit arrangement according to an embodiment. 
         FIG. 2  shows a schematic diagram of a digitally controlled oscillator according to an embodiment. 
         FIG. 3  shows a flow diagram illustrating method according to an embodiment. 
         FIG. 4  shows a flow diagram illustrating a method according to an embodiment. 
         FIG. 5  shows a diagram illustrating some features of some embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following, some embodiments of the present invention will be described in detail. It is to be understood that the following description is given only for the purpose of illustration and is not to be taken in a limiting sense. The scope of the invention is not intended to be limited by the embodiments described hereinafter with reference to the accompanying drawings, but is intended to be limited only by the appended claims and equivalents thereof. 
     It is to be understood that in the following description of embodiments any direct connection or coupling between functional blocks, devices, components, circuit elements or other physical or functional units shown in the drawings or described herein could also be implemented by an indirect connection or coupling, i.e. a connection or coupling comprising one or more intervening elements. Furthermore, it should be appreciated that functional blocks or units shown in the drawings may be implemented as separate circuits in some embodiments, but may also be fully or partially implemented in a common circuit in other embodiments. In other words, the description of various functional blocks is intended to give a clear understanding of various functions performed in a device and is not to be construed as indicating that these functional blocks have to be implemented as separate physical units. For example, one or more functional blocks may be implemented by programming a processor like a single digital signal processor accordingly or by providing a single integrated circuit. On the other hand, the function of a single functional block may also be implemented using more than one physical entity. 
     It should be noted that the drawings are provided to give an illustration of some aspects of embodiments of the present invention and therefore are to be regarded as schematic only. In particular, the elements shown in the drawings are not necessarily to scale with each other, and the placement of various elements of the drawings is chosen to provide a clear understanding of the respective embodiment and is not to be construed as necessarily being a representation of the actual relative location of the various components and implementations of embodiments of the invention. 
     The features of the various embodiments described herein may be combined with each other unless specifically noted otherwise. On the other hand, describing an embodiment with a plurality of features is not to be construed as indicating that all those features are necessary for practicing the present invention, as other embodiments may comprise less features and/or alternative features. 
     Turning now to the figures, in  FIG. 1  a phase locked loop (PLL) according to an embodiment is shown. 
     The embodiment of  FIG. 1  comprises a digitally controlled oscillator (DCO)  12  which outputs an output signal out having a controllable frequency. Output signal out is fed to a frequency divider  14  which outputs a frequency divided signal to a phase frequency detector (PFD)  10 . Phase frequency detector  10  also receives a reference signal refclk and outputs one or more signals indicative of a frequency difference and/or a phase difference between the reference signal refclk and the frequency divided output signal of frequency divider  14 , for example a phase error signal indicating a phase difference and a frequency error signal indicating a frequency difference. 
     It should be noted that in some implementations instead of phase frequency detector  10  a phase detector and a frequency detector separate from the phase detector may be provided. It should be noted that the term “phase detector” is generally to be construed as encompassing phase frequency detectors, as also phase frequency detectors are capable of detecting or measuring a phase difference, and likewise the term “frequency detector” is to be construed as encompassing phase frequency detectors as the latter are capable of detecting or measuring a frequency difference. 
     One or more output signals of phase frequency detector  10  are fed to one or more loop filters  11 , and one or more output signals of loop filters  11  are fed to one or more control inputs of DCO  12  to control the frequency of output signal out. 
     In case of separate phase and frequency error signals, for example separate loop filters  11  may be provided in some implementations for a phase error signal output by phase frequency detector  10  and a frequency error signal output by phase frequency detector  10 . 
     It should be noted that instead of a digitally controlled oscillator, in other embodiments another type of controllable oscillator, for example a voltage-controlled oscillator (VCO), may be provided. 
     Furthermore, an output signal of phase frequency detector  10 , for example a phase error signal, is submitted to a control  13 , which controls specific capacitances of DCO  12 , for example to decrease a time span needed until a phase alignment is reached, as will be further explained below. 
     Loop filter  11  and control  13  form a control circuitry which controls DCO  12 , for example components thereof discussed later with reference to  FIG. 2 , based on a phase error signal and/or a frequency error signal generated by phase frequency detector  10 . 
     In  FIG. 2 , a core portion of a digitally controlled oscillator according to an embodiment is shown. The DCO core portion of  FIG. 2  may for example be used for implementations of DCO  12  of  FIG. 1 , but may also be used independent therefrom. 
     The DCO core of  FIG. 2  comprises a cross-coupled pair of transistors  20 ,  21 , for example NMOS transistors or PMOS transistors, an inductivity  29 , coarse tuning varactors  28 , a fine tuning varactor matrix  27 , a first capacitor  26  with a capacitance C 1 , a first switch  25  coupled with first capacitor  26 , a second capacitor  24  having a capacitance C 2 , and a second switch  23  coupled with second capacitor  24 . Inductivity  29 , coarse tuning varactors  28 , fine tuning varactor matrix  27 , first capacitor  26  with first switch  25 , and second capacitor  24  with second switch  23  are coupled in a parallel manner and supplied by a positive supply voltage  210  like Vdd, and ground or V ss , i.e. a negative supply voltage  22 , as shown in  FIG. 2 . The overall capacitance value of coarse tuning varactors  28 , fine tuning varactor matrix  27 , first capacitor  26  and second capacitor  24  together with the inductivity value of inductivity  29  determines a frequency of a signal output by the oscillator. 
     Coarse tuning varactors  28  may comprise one or more individual varactors which may be controlled individually by a control signal (not shown). Fine tuning varactor matrix  27  may comprise a plurality of varactors, the capacitance values of the individual varactors of fine tuning varactor matrix  27  being smaller than the capacitance values of varactors of coarse tuning varactors  28 . In an embodiment, all varactors of fine tuning varactor matrix  27  nominally have the same capacitance value and may be activated or deactivated individually. Varactors of coarse tuning varactors  28  may have different capacitance values or equal capacitance values. 
     In an embodiment, the capacitance values C 1  and C 2  are greater than the individual capacitance values of fine tuning varactor matrix  27 . 
     Examples for the operation of a DCO having a DCO core for example as shown in  FIG. 2  when used in a PLL, for example the PLL shown in  FIG. 1 , will next be explained with reference to  FIGS. 3-5 . 
     In  FIG. 3 , a flow diagram of a method according to an embodiment is shown. At  30 , a coarse tuning, for example using coarse tuning varactors  28  of the embodiment of  FIG. 2 , is performed. In an embodiment, the coarse tuning is performed to reduce a frequency error between a reference signal and a signal derived from an output signal of a DCO. For example, coarse tuning varactors  28  may be controlled based on a frequency error detected by phase frequency detector  10 . 
     In an embodiment, at or near the end of coarse tuning  30 , the frequency of the signal derived from the output signal of the DCO, for example the output signal of frequency divider  14  of  FIG. 1 , matches the frequency of the reference signal, for example refclk of  FIG. 1 , with a predetermined accuracy, while a phase relationship between these signals is still essentially random. 
     At  31 , individual capacitors of the DCO are controlled based on a phase error, for example a phase error determined by phase frequency detector  10  of  FIG. 1  or any other phase detector. 
     An example for such a capacitor control according to an embodiment is schematically shown in  FIG. 4 . 
     In an embodiment, a DCO is initialized such that a first capacitor, for example first capacitor  26  of  FIG. 2 , is switched off, for example by setting switch  25  to an open position, and a second capacitor, for example second capacitor  24 , is switched on, for example by setting switch  23  to a closed position. An open position in this respect refers to a position where the switch is not conducting between its terminals, while a closed position refers to a position where the switch is conducting between its terminals. 
     At  40 , a phase error is measured, for example by phase frequency detector  10  of  FIG. 1  as mentioned. 
     At  41 , it is checked if the phase error exceeds a predetermined upper threshold. If yes, the first capacitor is switched on or, taking  FIG. 2  as an example, switch  25  is closed. 
     If no, at  43  it is checked if the phase error is smaller than a lower threshold. If yes, at  44  the second capacitor is switched off or, taking again  FIG. 2  as example, switch  23  is opened. 
     If this is not the case (no at  43 ), at  45  the first capacitor is switched off, and the second capacitor is switched on, or, in other words, the system is set to the initial state again. After  42 ,  44  or  45 , the method is resumed at  40 . 
     Returning now to  FIG. 3 , at  32  a fine tuning is performed, for example by using fine tuning varactor matrix  27 . In an embodiment, fine tuning varactor matrix  27  is controlled based on a phase error until e.g. the phase error is below a predetermined value. When this is the case, the PLL is “locked”. 
     It should be noted that the various acts described with reference to  FIGS. 3 and 4  need not be performed in the order shown. For example, capacitor control  31  and fine tuning  32  may be performed in parallel, or even coarse tuning  30 , capacitor control  31  and fine tuning  32  may be performed in parallel. Regarding  FIG. 4 , for example  41  and  43  may be exchanged. Also, the various acts of  FIG. 3  may be performed in a loop, i.e. repeatedly, and/or the loop shown in  FIG. 4  may be terminated after a predetermined time, when a locking has been achieved or may also be performed continuously. 
     In some embodiments, a phase detector, for example a phase frequency detector like phase frequency detector  10  of  FIG. 1 , may have a phase detection range smaller than 360 degrees or, in other words, the phase error can only be detected within a limited range smaller than 360 degrees and may for example show a saturation value outside this range. In such an embodiment, the switching of the first capacitor and second capacitor explained with reference to  FIG. 4  may be used to leave the saturation range of the detector, e.g. by switching the first capacitor and/or second capacitor if the phase detector outputs a value indicating saturation. 
     In other embodiments, additionally or alternatively an oscillator like a DCO used may exhibit a saturation behavior. For example, the oscillator may not change its output frequencies while values of a fine tuning control signal are outside a predetermined range. This will now be explained using an example with reference to  FIG. 5 . In  FIG. 5 , the DCO frequency is shown depending on a fine tuning value for an example implementation, e.g. a value of a signal controlling activation/deactivation of the varactors of fine tuning varactor matrix  27  of the embodiment of  FIG. 2 . Areas  52 ,  50  correspond to a saturation of the DCO. In an embodiment, in case of area  50 , a second capacitor like second capacitor  24  may be activated or switched on to leave the saturation range, and in case of saturation area  52  a first capacitor like first capacitor  26  of  FIG. 2  may be switched off or deactivated to leave the saturation area. When leaving the saturation area, tuning is then performed in a non-saturation area  51  which may be linear or approximately linear, although this need not be the case. In area  51  of the curve, fine tuning may be effected quickly. 
     It should be noted that the above embodiments serve only as examples, and a plurality of variations and modifications are possible, some of which have already been mentioned above. Some further examples or modifications will be explained below. 
     While in  FIG. 2  coarse tuning and fine tuning is both performed using varactors, in other embodiments switchable capacitors may be provided for coarse tuning and/or fine tuning. In other words, a coarse tuning circuitry may be implemented using other capacitances than varactors, and also a fine tuning circuitry may be implemented using other capacitances than varactors. Furthermore, while in the embodiments described above a first capacitor and a second capacitor are used for example to quickly reduce a phase error, in other embodiments more capacitors may be provided, or first capacitor and/or second capacitor may be implemented by a plurality of individual capacitors. For example, a plurality of capacitors with different values may be provided.