Abstract:
Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Description:
BACKGROUND 
     1. Field of Invention 
     The invention relates generally to magnetic random access memory, and more particularly, to Spin Torque Transfer Magnetic Random Access Memory (STT-MRAM). 
     2. Description of Related Art 
     This section is intended to introduce the reader to various aspects of the art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art. 
     Magnetic Random Access Memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance. MRAM differs from volatile Random Access Memory (RAM) in several respects. Because MRAM is non-volatile, MRAM can maintain memory content when the memory device is not powered. Though non-volatile RAM is typically slower than volatile RAM, MRAM has read and write response times that are comparable to that of volatile RAM. Unlike typical RAM technologies which store data as electric charge, MRAM data is stored by magnetoresistive elements. Generally, the magnetoresistive elements are made from two magnetic layers, each of which holds a magnetization. The magnetization of one layer (the “pinned layer”) is fixed in its magnetic orientation, and the magnetization of the other layer (the “free layer”) can be changed by an external magnetic field generated by a programming current. Thus, the magnetic field of the programming current can cause the magnetic orientations of the two magnetic layers to be either parallel, giving a lower electrical resistance across the layers (“1” state), or antiparallel, giving a higher electrical resistance across the layers (“0” state). The switching of the magnetic orientation of the free layer and the resulting high or low resistance states across the magnetic layers provide for the write and read operations of the typical MRAM cell. 
     Though MRAM technology offers non-volatility and faster response times, the MRAM cell is limited in scalability and susceptible to write disturbances. The programming current employed to switch between high and low resistance states across the MRAM magnetic layers is typically high. Thus, when multiple cells are arranged in an MRAM array, the programming current directed to one memory cell may induce a field change in the free layer of an adjacent cell. This potential for writes disturbances, also known as the “half-select problem,” can be addressed using a spin torque transfer technique. 
     A conventional spin torque transfer MRAM (STT-MRAM) cell includes a magnetic tunnel junction (MTJ), which is a magnetoresistive data storing element including two magnetic layers (one pinned and one free) and an insulating layer in between, a bit line, a word line, a source line, and an access transistor. A programming current typically flows through the access transistor and the MTJ. The pinned layer polarizes the electron spin of the programming current, and torque is created as the spin-polarized current passes through the MTJ. The spin-polarized electron current interacts with the free layer by exerting a torque on the free layer. When the torque of the spin-polarized electron current passing through the MTJ is greater than the critical switching current density (J c ), the torque exerted by the spin-polarized electron current is sufficient to switch the magnetization of the free layer. Thus, the magnetization of the free layer can be aligned to be either parallel or antiparallel to the pinned layer, and the resistance state across the MTJ is changed. 
     The STT-MRAM has advantageous characteristics over the MRAM because the spin-polarized electron current eliminates the need for an external magnetic field to switch the free layer in the magnetoresistive elements. Further, scalability is improved as the programming current decreases with decreasing cell sizes, and the writing disturbance and half-select problem is addressed. Additionally, STT-MRAM technology allows for a higher tunnel magnetic resistance ratio, meaning there is a larger ratio between high and low resistance states, improving read operations in the magnetic domain. 
     However, the STT-MRAM cell structure utilizes programming currents of bidirectional polarity to program the magnetic cell into the high and low resistance states. Bidirectional programming logic requires more silicon space to form the memory cell and is generally more complicated and less efficient than unidirectional programming logic. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       Certain embodiments are described in the following detailed description and in reference to the drawings in which: 
         FIG. 1  depicts a block diagram of a processor-based system in accordance with an embodiment of the present technique; 
         FIG. 2  depicts a schematic diagram of a portion of a memory array having memory cells fabricated in accordance with embodiments of the present invention; 
         FIG. 3  depicts a portion of a STT-MRAM cell in accordance with embodiments of the present invention; 
         FIG. 4  depicts a chart relating programming current and net spin polarization of a memory cell in accordance with embodiments of the present invention; 
         FIG. 5  depicts a portion of a STT-MRAM cell with an additional magnetic tunnel junction, as well as portions of STT-MRAM cells in low and high resistance states, in accordance with embodiments of the present invention; 
         FIGS. 6-11  depict portions of STT-MRAM cells in accordance with various embodiments of the present invention; and 
         FIG. 12  depicts a portion of a memory array implementing cross point architecture in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     A spin torque transfer magnetic random access memory (STT-MRAM) cell is programmed by switching the magnetization of the free layer in the cell&#39;s magnetic tunnel junction (MTJ). A programming current of bidirectional polarity is generally utilized to switch the magnetization of the free layer and program the cell. However, a STT-MRAM cell that is capable of being programmed into high and low resistance states with a unidirectional current would be more efficient and require less silicon space than the conventional bidirectional STT-MRAM cell. In accordance with embodiments of the present invention, a STT-MRAM cell structure may be designed to create an imbalance between two opposing spin torque transfer effects to enable unidirectional current programming. The following discussion describes the systems and devices, and the operation of such systems and devices in accordance with the embodiments of the present technique. 
       FIG. 1  depicts a processor-based system, generally designated by reference numeral  10 . As is explained below, the system  10  may include various electronic devices manufactured in accordance with embodiments of the present technique. The system  10  may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, etc. In a typical processor-based system, one or more processors  12 , such as a microprocessor, control the processing of system functions and requests in the system  10 . As is explained below, the processor  12  and other subcomponents of the system  10  may include resistive memory devices manufactured in accordance with embodiments of the present technique. 
     The system  10  typically includes a power supply  14 . For instance, if the system  10  is a portable system, the power supply  14  may advantageously include a fuel cell, a power scavenging device, permanent batteries, replaceable batteries, and/or rechargeable batteries. The power supply  14  may also include an AC adapter, so the system  10  may be plugged into a wall outlet, for instance. The power supply  14  may also include a DC adapter such that the system  10  may be plugged into a vehicle cigarette lighter, for instance. 
     Various other devices may be coupled to the processor  12  depending on the functions that the system  10  performs. For instance, a user interface  16  may be coupled to the processor  12 . The user interface  16  may include buttons, switches, a keyboard, a light pen, a mouse, a digitizer and stylus, and/or a voice recognition system, for instance. A display  18  may also be coupled to the processor  12 . The display  18  may include an LCD, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, LEDs, and/or an audio display, for example. Furthermore, an RF sub-system/baseband processor  20  may also be coupled to the processor  12 . The RF sub-system/baseband processor  20  may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). One or more communication ports  22  may also be coupled to the processor  12 . The communication port  22  may be adapted to be coupled to one or more peripheral devices  24  such as a modem, a printer, a computer, or to a network, such as a local area network, remote area network, intranet, or the Internet, for instance. 
     The processor  12  generally controls the system  10  by implementing software programs stored in the memory. The software programs may include an operating system, database software, drafting software, word processing software, and/or video, photo, or sound editing software, for example. The memory is operably coupled to the processor  12  to store and facilitate execution of various programs. For instance, the processor  12  may be coupled to the system memory  26 , which may include spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), and/or static random access memory (SRAM). The system memory  26  may include volatile memory, non-volatile memory, or a combination thereof. The system memory  26  is typically large so that it can store dynamically loaded applications and data. In some embodiments, the system memory  26  may include STT-MRAM devices, such as those discussed further below. 
     The processor  12  may also be coupled to non-volatile memory  28 , which is not to suggest that system memory  26  is necessarily volatile. The non-volatile memory  28  may include STT-MRAM, MRAM, read-only memory (ROM), such as an EPROM, resistive read-only memory (RROM), and/or flash memory to be used in conjunction with the system memory  26 . The size of the ROM is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memory  28  may include a high capacity memory such as a tape or disk drive memory, such as a hybrid-drive including resistive memory or other types of non-volatile solid-state memory, for instance. As is explained in greater detail below, the non-volatile memory  28  may include STT-MRAM devices manufactured in accordance with embodiments of the present technique. 
       FIG. 2  illustrates an STT-MRAM cell  50 , which may be fabricated to form an array of memory cells in a grid pattern including a number of rows and columns, or in various other arrangements depending on the system requirements and fabrication technology. An arrangement of memory cells may be implemented in the system memory  26  or the volatile memory  28  depicted in  FIG. 1 . 
     The STT-MRAM cell  50  includes a stack  52 , an access transistor  54 , a bit line  56 , a word line  58 , a source line  60 , read/write circuitry  62 , a bit line reference  64 , and a sense amplifier  66 . The stack  52  may include a magnetic tunnel junction (MTJ), including a free layer, and a pinned layer. As will be described further below with specific reference to FIGS.  3  and  5 - 11 , the “stack”  52  may refer to multiple free layers and pinned layers, a heat generating layer, a piezoelectric material, nonmagnetic layers, and additional MTJ components in accordance with embodiments of the present technique. 
     In various embodiments described below, the heat generating layer is referred to as a “layer” when the material is formed above or below the MTJ or a pinned layer in the stack, or parallel to the layers of the MTJ or stack. As also used herein, it should be understood that when a layer is said to be “formed on” or “disposed on” another layer, there may be intervening layers formed or disposed between those layers. Similarly, if materials are said to be “adjacent” to other materials, there may be intervening materials therebetween. Conversely, if a layer or material is said to be “formed directly on,” “disposed directly on,” or formed/disposed “directly adjacent to” or “in direct contact with,” the materials or layers include no intervening materials or layers therebetween. 
     When the STT-MRAM cell  50  is selected to be programmed, a programming current is applied to the cell, and the current is spin-polarized by one of the pinned layers and exerts a torque on the free layer, which switches the magnetization of the free layer to “write to” or “program” the cell. In a read operation of the STT-MRAM cell  50 , a current is used to detect the resistance state of the memory cell stack  52 . Further, incorporating a piezoelectric layer in the stack  52  may decrease the critical switching current required to switch the magnetization of the free layer, thus allowing a smaller programming current to write the STT-MRAM cell  50 . 
     As previously discussed, a programming current (or a “write current”) is applied for the write operation of the STT-MRAM cell  50 . To initiate the write operation, the read/write circuitry  62  may generate a write current to the bit line  56 . As will be further described, the current density of the write current determines the switch in magnetization of the free layer in the stack  52 . Once the free layer is magnetized according to the current density of the programming current, the programmed state is written to the STT-MRAM cell  50 . Thus, the STT-MRAM cell  50  may be programmed by a unidirectional current, enabling a simpler unidirectional programming logic on the STT-MRAM cell  50 . The conventional STT-MRAM cell changes between low and high resistance states by driving a write current in opposite directions, requiring bidirectional programming logic. For example, a write current would be driven from a transistor source to a transistor drain, and then through a MTJ to program the memory cell to a high resistance state. To program a memory cell to a low resistance state, a write current would be driven from a MTJ to a transistor drain to a transistor source. In the embodiments in accordance with the present technique, such bidirectional programming logic may not be necessary, as a unidirectional current may program the STT-MRAM cell  50 . As will be explained in  FIG. 12 , in some embodiments, the STT-MRAM cell  50  may be implemented in a cross point architecture to decrease the size of a STT-MRAM array. 
     To read the STT-MRAM cell  50 , the read/write circuitry  62  generates a read current to the bit line  56  and the source line  60  through the stack  52  and the transistor  54 . The programmed state of the STT-MRAM cell  50  depends on the resistance across the stack  52  which may be determined by the voltage difference between the bit line  56  and the source line  60 . In some embodiments, the voltage difference may be compared to a reference  64  and amplified by a sense amplifier  66 . 
     One embodiment of the present invention, a STT-MRAM cell capable of being programmed by a unidirectional current, is depicted in  FIG. 3 . Each of the stacks illustrated and described below may be incorporated in the STT-MRAM cell  50 , described in  FIG. 2 . The STT-MRAM cell stack  100  includes a top pinned layer  102 , separated from a free layer  106  by a top nonmagnetic layer  104 , and a bottom pinned layer  110 , separated from the free layer  106  by a bottom nonmagnetic layer  108 . As discussed further below, the pinned layers  102  and  110  and the free layer  106  are typically ferromagnetic materials. The top and bottom nonmagnetic layers  104  and  108  may serve as insulators between the free layer  106  and the top and bottom pinned layers  102  and  110 . The memory cell stack  100  may also include a heat generating layer  112 . 
     The memory cell may be programmed by switching the magnetization of the free layer  106  in the memory cell stack  100 , and the cell may be read by determining the resistance across the top pinned layer  102 , the free layer  106  and the bottom pinned layer  110 . The unidirectional arrow illustrated in each of the top pinned layer  102  and the bottom pinned layer  110  represent that the pinned layers  102  and  110  have a fixed magnetization. Furthermore, the magnetization of the top pinned layer  102  and the bottom pinned layer  110  are orientated in the same direction. The bidirectional arrow illustrated in the free layer  106  represents that the free layer  106  may be switched to have a magnetization in a direction parallel to the bottom pinned layer  110 , which gives a low resistance, or in a direction antiparallel to the bottom pinned layer  110 , which gives a high resistance. 
     The structure of the cell stack  100  and the parallel magnetizations of the top pinned layer  102  and the bottom pinned layer  110  may enable the memory cell to be programmed with a unidirectional current. More specifically, when a memory cell is selected to be programmed to a low resistance state, a programming current  114  is applied to the cell. The programming current  114  used to program the stack  100  to a low resistance state may be in the range of about 20 microamperes to about 1 miliampere. As the programming current  114  travels through stack  100 , the electron spin of the programming current  114  is first polarized by the bottom pinned layer  110 . When the spin polarized programming current  114  then reaches the free layer  106 , it aligns the free layer  106  to have the same magnetization as the bottom pinned layer  110 . If the current continues to the top pinned layer  102 , the magnetization of the top pinned layer  102  will not change since the programming current  114  was polarized in the same direction by the bottom pinned layer  110 . The magnetization of the free layer  106  is the same as the magnetization of the bottom pinned layer  110 , and the memory cell is programmed to a low resistance state. 
     If the memory cell is selected to be programmed to a high resistance state, a larger programming current  114  travels through stack  100 . The programming current  114  used to program the stack  100  to a high resistance state may be in the range of about 50 microamperes to about 1.5 miliampere. The larger current may generate greater heat in the heat generating layer  112  to locally heat up the bottom pinned layer  110  to reduce its magnetization and spin polarization efficiency. Though the heat generating layer  112  is shown in this embodiment as a means of modulating the spin torque effect of the bottom pinned layer  110 , this embodiment and other embodiments of the present technique may also implement other approaches or combinations of different approaches for modulating the imbalance between the opposing spin torques. For example, some embodiments may use voltage-induced stress, including but not limited to using piezoelectric materials within the STT-MRAM cell. 
     Since the bottom pinned layer  110  has decreased magnetization and spin polarization efficiency in response to the larger programming current  114 , the programming current will pass the bottom pinned layer  110  either unpolarized or not highly polarized. The programming current  114  will then travel through the free layer  106  and to the top pinned layer  102 . The top pinned layer  102  will reflect the electrons of the programming current  114  that have spin polarized to the opposite direction of the magnetization of the top pinned layer  102 . The reflected electrons with spin polarization opposite from the top pinned layer  102  will then switch the magnetization of the free layer  106  such that the magnetization of the free layer  106  is antiparallel to the magnetization of both the top and the bottom pinned layers  102  and  110 , and the memory cell is programmed to a high resistance state. 
     Thus, a unidirectional current may program a memory cell to either a low resistance state or a high resistance state. The spin torque effect on the free layer  106  from the current polarized by the bottom pinned layer  110  is opposite to the spin torque effect on the free layer  106  from the current reflected by the top pinned layer  102 . The structure of the stack  100  in this embodiment and the parallel magnetization of the two pinned layers  102  and  110  enable the spin torque effect of the bottom pinned layer  102  to dominate at a low current density, and the spin torque effect of the top pinned layer  102  to dominate at a high current density. Therefore, the programming current  114  need only be varied in current density, and not in direction. 
     The top pinned layer  102 , free layer  106 , and bottom pinned layer  110  may comprise ferromagnetic materials, including but not limited to materials such as Co, Fe, Ni or its alloys, NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X═B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or other half-metallic ferromagnetic material such as Fe3O4, CrO2, NiMnSb and PtMnSb, and BiFeO. The heat generating layer  112  may comprise refractory metals including, for example, nitride, carbide, and Boride, TiN, ZrN, HfN, VN, NbN, TaN, TiC, ZrC, HfC, VC, NbC, TaC, TiB 2 , ZrB2, HfB 2 , VB 2 , NbB2, TaB2, Cr3C2, Mo2C, WC, CrB2, Mo2B5, W2B5, or compounds such as TiAlN, TiSiN, TiW, TaSiN, TiCN, SiC, B4C, WSix, MoSi2, or elemental materials such as doped silicon, carbon, Pt, Niobium, Tungsten, molybdenum, or metal alloys such as NiCr, for example. The top nonmagnetic layer  104  and bottom nonmagnetic layer  108  can be either conductive or nonconductive. In some embodiments, conductive nonmagnetic layers may comprise Cu, Au, Ta, Ag, CuPt, CuMn, or other nonmagnetic transition metals, or any combination of the above nonmagnetic conductive materials. Nonconductive nonmagnetic layers may comprise Al x O y , MgO, AlN, SiN, CaO x , NiO x , HfO 2 , Ta 2 O 5 , ZrO 2 , NiMnO x , MgF 2 , SiC, SiO 2 , SiO x N y , or any combination of the above nonmagnetic nonconductive materials. 
     The chart illustrated in  FIG. 4  represents the relationship between an applied programming current and the net spin polarization between the free and pinned layers, according to one embodiment of the present invention. The positive values in the net spin polarization axis represent that the free layer is parallel to the bottom pinned layer. This condition results when the programming current is smaller, and the spin torque from the bottom pinned layer dominates and switches the free layer to be parallel to the bottom pinned layer. The negative values in the net spin polarization axis represent that the free layer is antiparallel to the bottom pinned layer. This condition results when the programming current is larger, and local heating decreases the spin torque from the bottom layer, such that the spin torque from the top pinned layer dominates and reflects the polarized electron current that switches the free layer to be antiparallel to the bottom pinned layer. 
     As previously discussed, the nonmagnetic layers separating a free layer from a pinned layer in a STT-MRAM cell stack can be conductive or nonconductive. Furthermore, a memory cell stack may comprise a combination of conductive or nonconductive nonmagnetic layers. If either or both of the nonmagnetic layers are nonconductive, the memory cell stack may provide a good sensing margin, meaning that the separation between the two programmable states of low and high resistivity are greater. For example a desirable resistance ratio in some embodiments may range from 100-300%. However, it may sometimes be advantageous to construct a memory cell where all the nonmagnetic layers are conductive. In such embodiments, the resistance change may not be as large as a memory cell with nonconductive nonmagnetic layers. Adding a magnetic tunnel junction (MTJ) may improve the sensing margin, or increase the resistance change of a memory cell. 
       FIG. 5  illustrates one embodiment of the present invention which includes an additional MTJ to improve the sensing margin of a memory cell. The memory cell stack  200  includes a bottom unidirectional programming stack  204  with a programming free layer  220  stacked between a top pinned layer  216  and a bottom pinned layer  224 . The bottom unidirectional programming stack  204  may further include a top nonmagnetic layer  218  between the programming free layer  220  and the top pinned layer  216 , and a bottom nonmagnetic layer  222  between the programming free layer  220  and the bottom pinned layer  224 . The nonmagnetic layers  218  and  222  may be either conductive or nonconductive, and may insulate the magnetization of the surrounding layers. When a low programming current passes through from the bottom of the stack  200 , the bottom pinned layer may spin polarize the current, and the spin polarized programming current switches the magnetization of the programming free layer  220 . When a high programming current passes through from the bottom of the stack  200 , the larger heat from the larger current and the heat generated by the heat generating layer  226  decrease the magnetization of the bottom pinned layer  224  such that the programming current, still non-polarized or not highly polarized, travels to the top pinned layer  216  where it is spin polarized and reflected back to the programming free layer  220  to switch the programming free layer  220  to be antiparallel to the bottom pinned layer  224 . The original portion  204  may further comprise an antiferromagnetic layer  214  on top of the top pinned layer  216  to help pin the top pinned layer  216  and maintain its magnetization and stability. 
     The memory cell stack  200  may also comprise an additional MTJ  202 , with a pinned layer  206  and a sensing free layer  210  separated from pinned layer  206  by a nonmagnetic barrier layer  208 . The additional MTJ  202  may improve the sensing margin and increase the resistance ratio of the memory cell. The additional MTJ  202  is magnetostatically coupled to be antiparallel to a programming free layer  220  in the bottom unidirectional programming stack  204 , such that changing the magnetization of the programming free layer  220  will change the magnetization of the sensing free layer  210 . Further, the additional MTJ  202  may be separated from the bottom unidirectional programming stack  204  by a spin randomizing separation layer  212 . The spin randomizing separation layer  212  randomizes the spin of the programming current and may eliminate or reduce any coupling effects between the sensing free layer  210  and the antiferromagnetic layer  214 . 
     The antiparallel magnetostatic coupling of the sensing free layer  210  to the programming free layer  220  may improve the sensing margin and the resistance ratio between the two programmed states. The two programmed states include a low resistance state  230  and a high resistance state  260 . In the low resistance state  230 , the programming current is spin polarized by the bottom pinned layer  234  and switches the magnetization of the programming free layer  232  to be parallel to the magnetization of the bottom pinned layer  234 . In the high resistance state  260 , the programming current travels through the bottom pinned layer  268  and is spin polarized by the top pinned layer  262  and reflected to switch the programming free layer  264  in a magnetization antiparallel to the bottom pinned layer  266 . 
       FIG. 6  illustrates one embodiment where an antiferromagnetic layer  314  is added to the memory cell stack  300  to help pin the bottom pinned layer  310  and maintain stability of the memory cell. As previously discussed, the bottom pinned layer  310  may have decreased magnetization and spin polarization efficiency when heat is applied, such that a current may pass the bottom pinned layer  310  with less polarization to be spin polarized by the top pinned layer  302  and reflected to switch the free layer  306 . The heat from a larger programming current may reduce magnetization, and a heat generating layer  312  may further decrease the magnetization and spin polarization efficiency of the bottom pinned layer  310 . The heat generating layer  312  may also provide antiferromagnetic coupling between the antiferromagnetic layer  314  and the bottom pinned layer  310 . 
     In another embodiment, as depicted in  FIG. 7 , a “synthetic free layer”  352  replaces a free layer in a memory cell stack  350 . As used herein, a “synthetic layer” refers to a structure having a nonmagnetic layer sandwiched between two ferromagnetic layers, which may have opposite magnetization, as described below. Referring again to  FIG. 7 , the synthetic free layer  352  may include a top free layer  358  and a bottom free layer  362  with a nonmagnetic layer  360  in between to promote antiferromagnetic coupling between the two free layers  358  and  362  such that the two free layers  358  and  362  are always opposite in magnetization. The top free layer  358  is coupled to the top nonmagnetic layer  356 , and the bottom free layer  362  is coupled to the bottom nonmagnetic layer  364 . Thus, to program the memory cell, the programming current switches both free layers  358  and  362 . Therefore, in this embodiment, the top pinned layer  354  may be opposite in magnetization from the bottom pinned layer  366 . 
     To program a cell to a low resistance state, a programming current entering the bottom of the stack  350  would be spin polarized by the bottom pinned layer  366  and would flip the bottom free layer  362  and then the top free layer  358 . The bottom free layer  362  would have the same magnetization as the bottom pinned layer  366 . To program a cell to a high resistance state, a large programming current would be applied, and the increased heat from the large programming current, and the heat generated by the heat generating layer  368  would decrease the magnetization and spin polarization efficiency of the bottom pinned layer  366 . Thus, the large programming current would pass the bottom pinned layer  366  with low polarization to be spin polarized by the top pinned layer  354 , which has an opposite magnetization from the bottom pinned layer  366 . The spin polarized programming current reflected from the top pinned layer  366  would switch the top free layer  358 , and then the bottom free layer  362 . The bottom free layer  362  would have the opposite magnetization as the bottom pinned layer  366 . Further, an antiferromagnetic layer  370  may also be added to the memory cell stack  350  to help pin the bottom pinned layer  366  and maintain stability of the memory cell. 
     Another embodiment of the present invention, illustrated in  FIG. 8 , includes a STT-MRAM cell stack  400  with a “synthetic top pinned layer”  402  which replaces a top pinned layer in the previously described embodiments. The synthetic top pinned layer  402  may include a first pinned layer  404  and a second pinned layer  408  separated by a nonmagnetic layer  406 . The nonmagnetic layer  406  promotes antiferromagnetic coupling between the surrounding pinned layers  404  and  408 , and may comprise conductive nonmagnetic material, such as Ru, Ir and Re. Because the two pinned layers  404  and  408  of the synthetic top pinned layer  402  are coupled through the nonmagnetic layer  406 , the two pinned layers  404  and  408  may be less affected by an incoming programming current and will keep magnetization even when temperature rises or when spin polarization occurs. The pinned layers  404  and  408  are thus less susceptible to spin polarizing effects and maintain their fixed magnetizations, thus improving the memory cell integrity. An antiferromagnetic layer  420  may also be added to the memory cell stack  400  to help pin the bottom pinned layer  416  and maintain stability of the memory cell. Further, the heat generating layer also provides antiferromagnetic coupling between the bottom pinned layer  416  and the antiferromagnetic layer  420 . 
       FIG. 9  depicts yet another embodiment of the present invention with an additional MTJ  452  in a memory cell stack  450 . The additional MTJ  452  includes a sensing free layer  456  and a pinned layer  460 , separated by a nonmagnetic barrier layer  458  to insulate the magnetizations of the sensing free layer  456  and the pinned layer  460 . The sensing free layer  456  is magnetostatically coupled to the free layer  468  to be antiparallel, thus improving the sensing margin. The additional MTJ  452  may be separated from the bottom unidirectional programming cell stack  454  by a nonmagnetic layer  462 , which promotes antiferromagnetic coupling between the surrounding pinned layers  460  and  464 . As will be appreciated, the pinned layer  460 , the nonmagnetic layer  462  and the pinned layer  464  make up a synthetic top pinned layer  465 . The synthetic top pinned layer  465  is a portion of both MTJ  452  and the unidirectional programming cell stack  454 . 
     As known by those skilled in the art, a ferromagnetic layer with a magnetization perpendicular to the plane of the layer may utilize a lower programming current to switch magnetization. Thus, another embodiment of the present invention may include ferromagnetic layers with magnetization perpendicular to the layer plane, as depicted in  FIG. 10 . As used herein a “layer plane” refers to the horizontal plane in which the associated layer is disposed. A STT-MRAM cell stack  500  includes a top pinned layer  502 , separated by a top nonmagnetic layer  504  from a free layer  506 , and a bottom pinned layer  510  separated by a bottom nonmagnetic layer  508  from the free layer  506 . The stack may further comprise a heat generating layer  512 . The unidirectional arrows illustrated in the top and bottom pinned layers  502  and  510  represent their fixed magnetization and are oriented perpendicularly to the layer plane. The bidirectional arrow illustrated in the free layer  506  represents that the magnetization of the free layer  506  may switch, depending on whether the memory cell is selected to be programmed to a low or high resistance state. As previously described, the structure of stack  500  enables a unidirectional programming current to switch the magnetization of the free layer  506  in either a direction parallel or antiparallel to the bottom pinned layer  510 . Further, a smaller programming current may enable such resistance changes due to the perpendicular magnetization of the layers in relation to their layer planes. 
     The magnetization of the free layer  506  from  FIG. 10  does not necessarily have to be perpendicular to the plane of the layer in other embodiments, as illustrated in  FIG. 11 . In another embodiment, a memory cell stack  550  comprises a top pinned layer  566  and a bottom pinned layer  574  having magnetizations perpendicular to the layer plane, and a programming free layer  570  having a magnetization parallel to the layer plane. This structure may help to increase the programming speed of the memory cell because of the interaction between the electron spin of the programming current and the magnetization of the programming free layer  570 . Less time is needed for the programming free layer  570  to switch in magnetization. An additional MTJ  552  with a sensing free layer  560  may be magnetostatically coupled to the programming free layer  570  to be antiparallel, thus improving the sensing margin between the two programmed states. Further, even if there is no resistance change between the magnetizations of the free and pinned layers  566 ,  570 , and  574  since the direction of magnetizations are perpendicular, the resistance change may be read from the additional MTJ  552 . 
     As depicted in  FIG. 12 , STT-MRAM cells may be arranged in an array implementing cross point architecture in accordance with an embodiment of the present invention. 
     In the architecture  600 , a rectifying device  602  is applied to the STT-MRAM cell  604 . The rectifying device  602  may enable a current path to a selected cell  606  and isolate non-selected cells by blocking the current path. In this embodiment, a diode is used as the rectifying device  602 , but any suitable rectifying device or any suitable biasing scheme may be used to enable the current path to a selected cell  606  and block the current path to non-selected cells. 
     To program a STT-MRAM cell to a low resistance state, a voltage V 1  is applied to a word line  608  connected to the selected cell  606 , and a lower voltage V 0  is applied to the rest of the word lines. A lower voltage V 0  (a voltage lower than V 1 ) is applied to a bit line  610  connected to the selected cell  606  to forward bias the rectifying device  612  of the selected cell  606  and create a programming current I 1  flowing through the selected cell  606 . The rest of the bit lines are biased at V 1  (or a voltage higher than V 0 ) to reverse bias the other rectifying devices and block the current to the non-selected cells. This enables the selected STT-MRAM cell  606  to be programmed to a low resistance state with a unidirectional current, in accordance with the present technique. 
     To program a STT-MRAM cell to a high resistance state, a voltage V 2  is applied to the word line  608  connected to the selected cell  606 . When programming a selected cell  606  to a high resistance state, the voltage V 2  applied across the rectifying device  612  and the selected cell  606  is larger than V 1 . As previously discussed, this may induce a larger programming current I 2  through the selected cell  606  to program the selected cell  606  to a high resistance state. The non-selected word lines are again biased at V 0  (a voltage lower than V 2 ), and non-selected bit lines are biased at V 2  (a voltage higher than V 0 ) to reverse bias the other rectifying devices so that the non-selected cells will not be disturbed by the write operation. Thus, the selected STT-MRAM cell  606  may be programmed to a high resistance state with a unidirectional current. 
     While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.