Abstract:
A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a novel type of semiconductor component. The present invention more specifically applies to power components and to protection components intended to handle high voltages, such components being generally called discrete components, although several such components may be provided on the same chip, and/or they may be associated with logic circuits provided on the same chip.  
         [0003]     2. Discussion of the Related Art  
         [0004]      FIGS. 1A and 1B  show as an example a perspective view and a cross-section view of a conventional vertical power diode. This diode is formed from a substrate comprising a heavily-doped N-type region  1  (N + ) and a lightly-doped N-type region  2  coated with a P-type layer  3 . The upper surface is coated with an anode metallization  4  and the lower surface is coated with a cathode metallization  5 . Reference numeral  6  designates an insulating layer.  
         [0005]      FIG. 2  is a perspective view of a vertical power thyristor. The thyristor comprises a lightly-doped N-type substrate  10 . On the upper surface side is formed a P-type well  11  containing an N-type cathode region  12 . On the lower surface side is formed a P-type anode layer  13 . An anode metallization MA, a cathode metallization MK, and a gate metallization MG are also provided. To prevent for the anode metallization from short-circuiting to substrate  10 , or to separate this thyristor from a neighboring component, a peripheral P-type insulating wall  15  is generally provided.  
         [0006]     It should incidentally be noted that in the present description, the term “diode” designates a PN or Schottky diode intended to be used as a power, protection, or avalanche diode. A diode is a bipolar component having two terminals intended to be connected to elements of a dielectric or electronic circuit, discrete or integrated, that, according to cases, conducts a forward current and blocks a reverse current (rectifying diode), or conversely, conducts a reverse current when the voltage thereacross exceeds a given threshold (protection diode). In the thyristor of  FIG. 2 , the separation surface between P-type insulating wall  15  and N-type substrate  1  is never intended to be conductive, but only either to enable the component periphery to be entirely at the rear surface potential, or to insulate well  1  from an adjacent well containing another component. This separation surface is not associated with terminals intended to be connected to elements of an electric or electronic circuit. Such a separation surface does not form a diode (sometimes conductive, sometimes blocked) connected to terminals of connection to a circuit.  
         [0007]     A disadvantage of vertical components is their on-state resistance. Indeed, the thicknesses of the various layers and regions are optimized according to the desired diode characteristics. In particular, the thickness of N-type layer  2  (diode) or  10  (thyristor) must be sufficiently high for the component to have a desired breakdown voltage but must also be as small as possible to limit the on-state resistance of the component. In the case of a diode, N +  layer  1  has no active function in the diode operation. It is only used to ensure an ohmic contact with the metallization and is used to reduce the diode&#39;s on-state resistance linked to the fact that a silicon wafer has, in current technologies, a thickness of from 300 to 500 μm, in most cases much greater than the desired thickness of N layer  2  (for example, 60 μm to hold 600 V). In the case of the thyristor, the thickness of layer  10  is also required by the thickness of the silicon wafer and various means, often complex, are used to reduce it.  
         [0008]     Another disadvantage of vertical components is that the surface area of the active junctions is linked to the semiconductor chip surface area taken up by the components, the junctions being horizontal (in planes parallel to the main diode surfaces).  
         [0009]     Further, such components intended to handle high voltages pose many problems to ensure a proper breakdown voltage at the periphery of the semiconductor or Schottky junction, as well as to insulate the entire component and ensure its protection (insulating wall).  
         [0010]     A PNN +  diode and a thyristor have been described as an example only of vertical components, the problems indicated hereabove generally relating to vertical power or high-voltage components, for example, Schottky diodes, bidirectional components, or MOS-type voltage-controlled components.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention aims at providing novel types of diodes, and more generally novel types of semiconductor power or high-voltage components enabling avoiding at least some of the above-mentioned disadvantages of vertical components, in particular increasing the active junction surface area with respect to the surface area of the chip in which the component is formed, reducing the on-state voltage drop, and simplifying the peripheral structure of the individual components.  
         [0012]     To achieve these and other objects, the present invention provides a semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof.  
         [0013]     According to an embodiment of the present invention, the contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.  
         [0014]     According to an embodiment of the present invention, the conductive fingers are metal fingers.  
         [0015]     According to an embodiment of the present invention, the semiconductor component is of multicellular type and the junctions are formed of several cylinders perpendicular to the main substrate surfaces.  
         [0016]     According to an embodiment of the present invention, the component is a diode comprising an alternation of regions of a first conductivity type and of a second conductivity type extending across the entire substrate thickness, the regions of a first type being crossed by conductive fingers connected to a metallization extending over an entire surface of the substrate, and the regions of the second type being crossed by conductive fingers connected to a metallization on the other substrate surface.  
         [0017]     According to an embodiment of the present invention, the diode is formed in an N-type semiconductor substrate, the conductive fingers penetrating into the N-type regions being surrounded with heavily-doped N-type regions.  
         [0018]     According to an embodiment of the present invention, the component is a bipolar transistor alternately comprising a region of a first conductivity type, a region of a second conductivity type, and a region of the first conductivity type, each of these regions extending across the entire thickness of the substrate and being in contact with at least one conductive finger, each of these conductive fingers being respectively connected to an emitter metallization, to a base metallization, and to a collector metallization.  
         [0019]     According to an embodiment of the present invention, the component is a thyristor successively comprising a first region of a first conductivity type, a second region of the second conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, each of these regions extending across the entire substrate thickness, a conductive finger extending into the entire first region, at least one conductive finger extending into the entire second region, and at least one conductive finger extending into the entire fourth region.  
         [0020]     According to an embodiment of the present invention, in the thyristor, the first conductivity type is type N, the second conductivity type is type P, the first region being a cathode region and the fourth region an anode region, and localized metallizations extend vertically between the gate region and the cathode region to form localized gate-cathode short-circuits.  
         [0021]     The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIGS. 1A and 1B , previously described, are simplified perspective and cross-section views of a conventional vertical diode structure;  
         [0023]      FIG. 2 , previously described, is a simplified cross-section view of a conventional vertical thyristor structure;  
         [0024]      FIGS. 3 and 4  are simplified perspective views of two embodiments of a diode according to the present invention;  
         [0025]      FIGS. 5A and 5B  respectively are a simplified cross-section view and a circuit diagram of a diode according to the present invention;  
         [0026]      FIGS. 6A and 6B  respectively are a simplified cross-section view and a circuit diagram of a diode assembly according to the present invention;  
         [0027]      FIGS. 7A and 7B  respectively are a simplified cross-section view and a circuit diagram of another diode assembly according to the present invention;  
         [0028]      FIGS. 8A and 8B  respectively are a simplified cross-section view and a circuit diagram of another diode assembly according to the present invention;  
         [0029]      FIGS. 9A and 9B  respectively are a simplified cross-section view and a circuit diagram of another diode assembly according to the present invention;  
         [0030]      FIGS. 10A and 10B  are a simplified perspective view and a cross-section view of a bipolar transistor according to the present invention; and  
         [0031]      FIGS. 11A and 11B  are a simplified perspective view and a cross-section view of a thyristor according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0032]     As conventional in the field of semiconductor representation, the various drawings are not to scale. Especially, in these various drawings, the lateral dimensions have been greatly exaggerated with respect to the vertical directions. Indeed, a silicon wafer currently has a thickness of from 300 to 500 μm—and greater thicknesses may be chosen for an implementation of the present invention—while patterns and vias may be defined according to dimensions on the order of from 1 to 10 μm.  
         [0033]      FIG. 3  is a simplified perspective view of a portion of a semiconductor component in which is formed an assembly of diode cells according to the present invention. The main surfaces of the component correspond to the upper and lower surfaces of a semiconductor wafer, and the vertical surface, having its thickness designated as e, corresponds to the thickness of the semiconductor wafer.  
         [0034]     The junction of each diode cell is formed vertically across the thickness of the semiconductor wafer.  
         [0035]     In  FIG. 3 , the structure is formed from a lightly-doped N-type silicon wafer  21 . For each cell, a plate-shaped metallization  22  vertically formed in a trench extends along the entire height or most of the height of the semiconductor wafer. A P-type region  23  is adjacent to a portion of N-type wafer  21  and a plate-shaped metallization  24  extends vertically in a trench adjacent to said portion of N-type wafer  21 . Thus, the diode junction is a vertical junction between N and P regions  21  and  23 . It is only useful to provide between the N region and metallization  22  a very thin N + -type layer (not shown) to ensure the ohmic contact without requiring, as in the case of conventional diodes, provision of a thick N +  region. Thus, the on-state voltage drop in the diode is reduced.  
         [0036]      FIG. 4  shows a currently preferred alternative topology of a multicellular diode according to the present invention, it being understood that in certain cases, a single diode cell may be used. The structure is formed again in an N-type substrate  21 , the thickness of which is designated as e. The metallizations, instead of corresponding to plates formed in parallel trenches, are formed of cylindrical fingers. A way to form such a structure is to form from a wafer surface first openings  22  preferably extending across the entire height e of the substrate. From these openings is formed a P-type diffusion  23 , after which the openings are filled with metal to form vias  22 . Second openings  24 , in quincunx with respect to openings  22 , also extend preferably across the entire substrate height. A short N +  diffusion (not shown) is formed from the second openings which are filled with metal to form vias  24 . All vias  22  are interconnected and all vias  24  are interconnected by anode and cathode metallizations, not shown, insulating layers, not shown, ensuring the necessary insulations. A diode with vertical junctions having a low on-state resistance and a density much greater than what could be obtained with a conventional diode with a horizontal junction is obtained between these metallizations, for example, respectively formed on the upper and lower structure surfaces. This type of structure further has the advantage of avoiding breakdown voltage problems at the diode periphery posed by conventional structures.  
         [0037]     It should be noted that, instead of providing simple conductive fingers  24 , metal could be present all around useful N-type areas  21 . The structure can then be seen as a conductive (metal) plate comprising openings containing concentric cylindrical elements comprising a central via  22 , surrounded with a P-type semiconductor cylinder  23 , surrounded with an N-type semiconductor cylinder  21 , possibly surrounded with an N +  semiconductor cylinder.  
         [0038]     The above description essentially aims at the diode structure and the order of the manufacturing steps may be modified.  
         [0039]     In the following, term “via” or “finger” will be used to designated the plate-shaped elements of  FIG. 3  as well as the finger-shaped elements of  FIG. 4 .  
         [0040]      FIG. 5A  shows a more detailed cross-section view of a structure such as that in  FIGS. 3 and 4 . The same elements as in  FIGS. 3 and 4  are designated with the same reference numerals. Reference numerals  26  and  27  designate insulating layers. Insulating layer  26  on the upper substrate surface covers all the N regions and insulating layer  27  on the lower substrate surface covers all the P regions. An upper surface metallization M 1  is in contact with all vias  22  in contact with P-type regions  23  and a lower surface metallization M 2  is in contact with all vias  24  in contact with N + -type regions  25 , themselves in contact with portions of N substrate  21 .  
         [0041]     In the example of  FIG. 5A , the upper layer vias have been shown as substantially through vias and the lower layer vias have been shown as non-through vias. However, other options may be chosen according to the selected manufacturing technologies.  
         [0042]      FIG. 5B  shows the equivalent diagram of the structure of  FIG. 5A  between metallizations M 1  and M 2 . According to an advantage of the present invention, the junction surface area of the assembly of diode cells in parallel may be much greater than the surface area of the chip containing these diode cells, and this, all the more as thicker semiconductor wafers than is usual may be used. Another advantage of this type of manufacturing is that it is possible to form several components according to the present invention on a same wafer, each of these components being easily surroundable, if useful, with an insulating wall formed in any known fashion.  
         [0043]      FIGS. 6A and 6B  show a simplified cross-section view and an equivalent diagram of two diodes or diode cells D 1  and D 2  in series (tandem assembly) formed in an N-type semiconductor substrate  30 . In  FIG. 6A , the left-hand diode comprises two almost through conductive fingers  31  and  32 , both starting from the upper surface. Finger  31  is surrounded with a P region  33  and finger  32  is surrounded with an N +  region  34 . The right-hand diode comprises a conductive finger  35  starting from the upper surface surrounded with a P region  36  and a conductive finger  37  starting from the lower surface surrounded with an N +  region  38 . Insulating layers are formed so that an upper metallization M 1  is in contact with finger  31 , an insulated metallization M 3  connects conductive fingers  32  and  35 , and a lower surface metallization M 2  is in contact with conductive finger  37 .  
         [0044]     As shown in partial cross-section view in  FIG. 7A  and in the form of a diagram in  FIG. 7B , by assembling two pairs of diode such as diodes D 1  and D 2  of  FIGS. 6A and 6B , and by providing insulating walls, a rectifying bridge can be formed. In  FIG. 7A , the left-hand diode is identical to the left-hand diode of  FIG. 6A  and its elements are also designated with the same reference numerals. The essential difference between  FIGS. 6A  and  7 A is the positioning of the metallizations. As previously, upper surface metallization M 1  contacts finger  31  and lower surface metallization M 2  contacts finger  37 . However, this time, metallization M 3  short-circuiting conductive fingers  32  and  35  is not locked in an insulating layer, but is accessible from the upper surface. Further, the entire structure is surrounded with a wall  39  made of an insulating material.  
         [0045]     By forming two structures identical to that in  FIG. 7A , and by connecting, for the two structures, metallizations M 1  together, metallizations M 2  together, and metallizations M 3  to separate terminals, a rectifying bridge assembly such as that illustrated in  FIG. 7B  is obtained.  
         [0046]      FIG. 8A  and  FIG. 8B  show a combination of diodes forming a bi-directional avalanche diode. This diode is formed in an N-type semiconductor substrate  40 . A conductive finger  41  starting from the upper surface is surrounded with a P-type region  42  and a conductive finger  43  starting from the lower surface is surrounded with a P-type region  44 . An upper surface metallization M 1  is in contact with finger  41  and a lower surface metallization M 2  is in contact with finger  43 .  
         [0047]      FIG. 9A  is a cross-section view and  FIG. 9B  is a circuit diagram of an assembly of two diodes in antiparallel. The two diodes are formed in an N-type substrate  50 . The left-hand diode comprises a conductive finger  51  surrounded with a P region  52 , solid with an upper metallization M 1 . A conductive finger  53  surrounded with an N +  region  54  is solid with a lower metallization M 2 . Conversely, the right-hand diode comprises a conductive finger  55  surrounded with an N + -type region solid with upper metallization M 1  and a conductive finger  57  surrounded with an N+ region  58  solid with lower metallization M 2 . The two diodes are separated by an insulating wall  59 .  
         [0048]     In the various drawings, the fingers are illustrated as through or not fingers. This depends on the embodiments and on the selected manufacturing technologies. In the case of through fingers, their end unconnected to a contact is isolated.  
         [0049]      FIGS. 10A and 10B  show a partial perspective view and a cross-section view of a realization according to the present invention of a bipolar transistor. The bipolar transistor is formed in an N-type substrate  60  and comprises a heavily-doped N-type emitter region  61  around a central conductive finger  62  extending across all or substantially all the substrate thickness. A P-type base region  63  is arranged around the emitter between the emitter and a collector region corresponding to substrate  60 . As better shown in  FIG. 10B , conductive fingers  64  starting from the lower surface are surrounded with N +  regions  65  and are used as a collector contact. An intermediary metallization M 3  on the upper surface side is solid with conductive fingers  66  contacting base region  63 . As illustrated in  FIG. 10A , conductive fingers  66  are spaced apart as a grid to enable proper operation of the base. However, in a realization of the type of that of  FIG. 4 , fingers  64  may in fact form a conductive cylinder completely surrounding the shown transistor cell.  
         [0050]      FIGS. 11A and 11B  illustrate a thyristor structure respectively in perspective and in cross-section view. The structure is formed in an N-type semiconductor substrate  70 . In a central region, a conductive finger  71  is surrounded with a heavily-doped N-type region  72  corresponding to the thyristor cathode and with a P layer  73 . These regions may be formed by successively diffusing, from a through or substantially through opening, a P dopant, then an N dopant, or by simultaneously diffusing dopants having adequately different diffusion rates. Finger  71  is connected to a cathode metallization MK. Conductive fingers  74  penetrate into P-type region  73  and form gate contact points solid with a gate metallization MG. On the lower surface side, at the component periphery, are formed conductive fingers  75  surrounded with a P-type region  76  that forms the thyristor anode and which is connected by fingers  75  to an anode metallization MA. It should be noted that, as conventional in a thyristor, localized gate-cathode short-circuits may be formed by means of conductive fingers  77  only partially penetrating into the substrate between N region  72  and P region  74 . Insulating regions, with no reference numerals, are intended to separate the various metallizations and to insulate the appropriate areas. The entire structure may be surrounded with an insulating wall.  
         [0051]     A triac may be formed by assembling two thyristors of the above type in parallel and an in opposition.  
         [0052]     The various illustrated structures are likely to have various alterations and modifications, and it should be noted by those skilled in the art that the alterations described for certain embodiments apply to other embodiments.  
         [0053]     In the same way as an assembly of diode cells in parallel has been illustrated in  FIGS. 3, 4 , and  5 A, thyristors or multicellular transistors may be formed by repeating a pattern. Each of the cells may be formed from parallel trenches, as in  FIG. 3 , or have a cylindrical geometry, as in  FIG. 4 . Cylinders with a non-circular cross-section, for example polygonal, may of course be chosen. Similarly, many component associations may be simply formed in the same substrate, separated or not by insulating walls.  
         [0054]     On the other hand, many embodiments will readily occur to those skilled in the art, and will be possible according to the technical development, the forming of conductive fingers or of plates formed in trenches being examples only of possible approaches of the forming of the described structures with vertical junctions.  
         [0055]     It should be noted that, since a greater density of components is obtained with vertical junction components according to the present invention than with conventional horizontal junction components, more heat will be generated per surface area unit when the components are on (although the on-state voltage drop is smaller due to the possible optimization of the thickness of the reverse voltage strength layer). However, this heat may advantageously be extracted by means of the through conductive fingers. Indeed, metal fingers have a heat conductivity from 2 to 3.5 times greater than the equivalent silicon volume. These fingers may take up a large surface area and, in particular, the peripheral “fingers” may take up the entire free surface area between elementary cells of a component.  
         [0056]     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.