Abstract:
An arrangement having a first converting element configured to convert an input current linearly into an auxiliary current, a second converting element configured to convert the auxiliary current into an output voltage, and a separating element configured to separate slow changes of the auxiliary current from fast changes of the auxiliary current, wherein the first, second, and separating elements are arranged as a dynamic control loop regulating the input current with the slow changes.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to German Patent Application Serial No. 102007006347.6, which was filed Feb. 8, 2007, and is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    A large number of methods are known nowadays for data transmission in digital radio communication systems, RFID systems being one example. In accordance with the particular system, the data transfer takes place between a transponder, implemented, for example as a radio tag, and a reading device. At low communication frequencies, inductive fields provide the transmission medium, while electromagnetic fields are used at higher frequencies. In systems of this type the inductive or electromagnetic field is modulated by information. Modulation consists in a modification of the signal parameters of a carrier frequency, that are the amplitude, the frequency or the phase, in accordance with a modulating signal, known as the baseband signal. 
         [0003]    The field has to be demodulated in order to regain the baseband signal, i.e. the real information. Since both the transponder and the reading device contain a source of information, and therefore an exchange of information in both directions takes place, both pieces of equipment often contain both a modulator and a demodulator. 
         [0004]    To regain the information, an antenna is now used to extract electrical power from the field. An inductive current arises in the antenna coil as soon as it comes into the region of an electromagnetic field. The modulation of the field is thus converted into the modulation of a proportional electrical current. The information can now be detected in the changes of this current over time. Parallel circuits, also known as shunt circuits, are used to detect the current. 
         [0005]    A digital radio communication system involves, amongst other things, a highly dynamic electromagnetic field. In other words, depending on the distance between the transmitting and receiving equipments, the information is transmitted in a form of a highly variable field. The modulated field therefore has a rapidly changing modulation component, representing the information, and a slower component resulting from changes in the distance between the transmitter and receiver, or from changes in the transmission medium. 
         [0006]    After converting the field into a proportional current, it is therefore necessary to normalize the current before being able to process the information contained in the current any further, so that subsequent circuit elements are not loaded beyond appropriate limits. 
         [0007]    Normalization of this type is referred to as dynamic compression. In the past, one way of achieving dynamic compression has been to use a number of diodes in series. Another way of achieving compression has been to use a specialized analogue/digital converter, in which two demodulation units are provided with variable sensitivity modules, thereby switching between several outputs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    Examples of the invention are explained below with reference to the drawings; the illustrations have been drawn so that components that are the same, or that have the same effect, are given the same reference. The elements illustrated are not to scale. For the sake of understanding, some elements have been shown disproportionately large or in an extremely simplified form. 
           [0009]      FIG. 1  shows a block diagram of receiving unit in a communication system; 
           [0010]      FIG. 2  shows a block diagram of an example implementation for reducing the dynamic range of an input current using a dynamic control loop; 
           [0011]      FIG. 3  shows a circuit diagram illustrating the principle of the example implementation; 
           [0012]      FIGS. 4   a  and  4   b  show first steps to realizing the example implementation; 
           [0013]      FIG. 5  shows further steps to realizing the example implementation; 
           [0014]      FIG. 6  shows a circuit diagram of the example implementation; and 
           [0015]      FIG. 7  shows extended circuit diagram of the example implementation, including differential amplifier, reference voltage and sample-and-hold function 
       
    
    
     DESCRIPTION OF THE INVENTION 
       [0016]      FIG. 1  shows a block diagram of a receiver in a radio communication system, such as might, for instance, be used in RFID systems. 
         [0017]    A conversion unit  1 , which converts an information modulated electromagnetic field into an electrical current, comprises a receiving unit  1   a  and a shunt circuit  1   b . This shunt circuit might, for instance, be implemented as a parallel circuit. The transmitted information, which is present as a field at the receiving unit  1   a , can be converted into rapid changes in electrical current by means, for instance, of a shunt resistor. 
         [0018]    As a result of changes in the distance between the transmitter and receiver in this radio communication system, the electromagnetic field that carries the modulated field strength has a further modification superimposed upon it; it is, in other words, also modulated by the changing distance. One of the effects of larger changes in distance is that the field has a wide dynamic range, and this is reflected in a slow change in the current flowing through the shunt element. The changing current, comprising both a slow and a fast component, is now passed to a decoupling unit  2 . The modulated current, which will be referred to below as the input current I 1 , is converted in a linear current converter  2   a  into an auxiliary current I 1 ′, and is fed to a current/voltage converter  2   b . An output voltage U 1  is present at the output of the decoupling unit  2 , which contains a dynamic control loop, and this voltage is passed to a demodulation unit  3 . The information is extracted in the demodulation unit  3 ; the extraction will not be considered here in any more detail. 
         [0019]    In  FIG. 2 , a block diagram of an example of the implementation of the decoupling unit  2  is represented in more details. A linear current converter  2   a  is connected to a current/voltage converter  2   b . A control feedback loop, comprising a low-pass filter  2   c  and a current regulator  2   d , is also connected from the output of the current converter  2   a  through a summing node to the input of the current converter  2   a.    
         [0020]    The input current I 1 , consisting of a rapidly changing current together with a slowly changing current, is now present at the input to the linear current converter  2   a . This current converter  2   a  transfers all the current components of the input current I 1  linearly, yielding the auxiliary current I 1 ′ at its output. Due to the linear current conversion, both the slowly changing and the rapidly changing currents are present in the auxiliary current I 1 ′. By means of the current/voltage converter  2   b , an output signal U 1 , used for further processing of the information, is generated from the auxiliary current I 1 ′. In addition to being passed to the current/voltage converter, the auxiliary current I 1 ′ is also fed back. The regulating variable in this control loop is that proportion of the auxiliary current I 1 ′ that contains the slowly changing current I 5 . The auxiliary current I 1 ′ is filtered in a low-pass filter  2   c  in such a way that only that component of the current that is changing slowly  15  is present at the output of the low-pass module. The current I 5  is converted in a current regulation circuit  2   d  to yield the second auxiliary current I 3 . This auxiliary current I 3  is also referred to as the feedback variable. By means of the constant current I 2  the additive superimposition of the input current I 1  with the auxiliary current I 3  results in compensation for the slow changes. 
         [0021]    Dynamic regulation is implemented here through components  2   c  and  2   d  in the form of a feedback control loop. The variable regulated in this control loop is the current I 5 , which only contains the slowly changing component in the input current. If the feedback control loop  2   c  and  2   d  is now formed in such a way that currents I 3  and I 1  are additively superimposed, so that the slower changes in the current are compensated, then an output voltage U 1  will be present at the output of the current/voltage converter  2   b  which will be at one level, modulated with the information. 
         [0022]    As a result of this constant output level, subsequent circuits operate independently of the slow changes in current, and therefore independently of the changing distance between the transmitting and receiving units of such a communication system. 
         [0023]      FIG. 3  illustrates the general principles of a circuit according to the block diagram of  FIG. 2 . N-channel and P-channel transistors are used, each of which has a drain and a source connection in addition to a gate connection. N-channel transistors are given names beginning with an “N”, while those for P-channel transistors begin with a “P”. An input transistor N 1 , whose gate connection serves as the input and whose drain is connected to the source of transistor P 1 , is shown. The gate and source of transistor P 1  are connected together, while its gate is also connected to transistor P 2 . The drains of both transistors and P 1  and P 2  are connected to a positive power supply voltage. The source of transistor P 2  is also connected to a load resistor R 1 . The second terminal of the load resistor R 1  is connected to the reference potential GND. A load capacitor C 1  is connected in parallel with load resistor R 1 . The output voltage U 1  is developed across resistor R 1  and capacitor C 1 . The node where the output voltage U 1  is developed is also connected to a current regulator  3   d . The output of the current regulator  3   d  is, in turn, connected to the source of the input transistor N 1 . The current regulator  3   d  therefore forms a feedback loop. A constant current source Q 1 , also connected to the source of transistor N 1 , is connected at the other end to the reference potential GND. 
         [0024]    The input transistor N 1  passes the input current I 1 . Because transistors P 1  and P 2  form a current mirror, they convert current I 1  into an auxiliary current I 1 ′. The output voltage U 1  developed across resistor R 1  and capacitor C 1  is generated by the auxiliary current I 1 ′. It follows that R 1  is an element that converts current to voltage. The purpose of capacitor C 1  here is merely to filter out those high-frequency components of the voltage spectrum that make no significant contribution to the information content. The auxiliary current I 1 ′ is then converted into a second auxiliary current I 3  with the aid of current regulator  3   d . This is then additively combined with input current I 1  in such a way that a constant current I 2  is generated in the constant current source Q 1 . 
         [0025]      FIGS. 4   a  and  4   b  illustrate a first possible approach to realizing the example implementation, along with various curves of current and one of voltage against time t. As compared with  FIG. 3 ,  FIGS. 4   a  and  4   b  show the feedback loop in more detail. The other components described in relation to  FIG. 3  are therefore retained, and connected in the same way. 
         [0026]    In contrast to  FIG. 3 , the feedback loop in  FIG. 4   a  is initially formed with the aid of a differential amplifier ΔU, whose first input is connected to the output voltage U 1  and whose second input is connected to the reference voltage U 2 . The output of the differential amplifier is a difference voltage U 6 , and is connected to a sample-and-hold switch A. The output of the switch A is connected to a low-pass capacitor C 2  and to the gate terminal of transistor Q 2 . The second terminal of capacitor C 2  is in turn connected to the reference potential GND. The drain of transistor Q 2  is connected to the positive power supply voltage, while its source is connected to input transistor N 1 . 
         [0027]    In contrast to  FIG. 3 , the controlling feedback variable is initially the output voltage U 1 . This voltage U 1  is compared with the reference voltage U 2  by differential amplifier ΔU. The output of the differential amplifier ΔU is now at a difference voltage U 6 ; this contains both a rapidly changing voltage and a slowly changing voltage, and depends on the difference between the voltages U 1  and U 2 . Because the output is connected with low-pass capacitor C 2 , the slowly changing voltage component is separated from the rapidly changing voltage component. C 2  effectively provides a short circuit for the rapid voltage changes. The slowly changing voltage is referred to from here on as U 3 , and at the same time provides a control voltage for control transistor Q 2 . The current I 3  passed by control transistor Q 2  as a result of the voltage U 3  is, in turn, referred to as the second auxiliary current. Due to the constant current I 2 , a change in the current I 1  will lead to I 3  being additively superimposed on current I 1  at current node B, compensating for the change. Slow changes in the current I 1  will control current I 3  through control transistor Q 2  by means of its gate voltage U 3 . Fast changes in the current I 1  will be directly controlled at this point by the source potential of transistor Q 2 . A relatively fast rise in current I 1  causes a rise in the source potential of Q 2 . Since U 3  only contains a slowly changing component, the gate potential of transistor Q 2  remains the same, and the resulting gate-source voltage will therefore be smaller. This reduces the second auxiliary current I 3 , and compensates for fast changes in current I 1  at current node B. 
         [0028]    These relationships are clarified through the current and voltage curves of  FIG. 4   b . The compensation is achieved through the constant current I 2  and through the additive superimposition of currents I 1  and I 3  at current node B. This illustrates the principle of how the feedback that has been described, and which generates current I 3 , does not affect the rapid changes in current. This achieves a constant output voltage level U 1 , which only varies if rapid changes in current at resistor R 1  lead to rapid changes in voltage. 
         [0029]      FIG. 5  illustrates a further way of realizing the example implementation. Because the two examples are similar, only the differences between  FIGS. 4   a  and  4   b , and  FIG. 5  will be described below. 
         [0030]    The difference as compared with  FIGS. 4   a  and  4   b  is that the output of the differential amplifier ΔU is connected to the gate of transistor P 3 . The source of this transistor is connected to input transistor N 1 , while its drain is connected to the reference potential GND. The constant current source Q 1  is omitted from  FIG. 5 . The differential amplifier, furthermore, is operated from both a positive supply +UB and a negative supply −UB, because the voltage including the slow changes in voltage U 3  has a negative arithmetic sign. 
         [0031]    Because the variable current source Q 2  is replaced by transistor P 3 , it is necessary for the difference voltage U 6  in the feedback loop also to be able to adopt negative values. For this reason, the differential amplifier ΔU, in contrast to  FIGS. 4   a  and  4   b , is also supplied with a negative power supply voltage. This enables the gate-source voltage of U 3  to have a more negative voltage than the source terminal of the input transistor N 1 . This voltage U 3  regulates the current I 1 . The constant current I 2  is developed here in transistor P 3 , and is not shown here. 
         [0032]    The two possible implementations illustrated in  FIGS. 4   a  and  4   b , and  FIG. 5 , incorporate an optional sample-and-hold function. Switch A, which opens or closes when operated, permits the regulation loop to be interrupted briefly, thereby allowing output voltage U 1  to be sampled in a more controlled way. 
         [0033]    A circuit diagram of the example implementation is shown in  FIG. 6 . This circuit diagram corresponds substantially to the foregoing illustrations. 
         [0034]    The difference from the foregoing figures consists primarily of some transistor references. The current mirror transistors are referred to in  FIG. 6  as P 0  and P 1 , the constant current source, implemented as a transistor, is referred to as N 16 , the variable current source as N 17 , and the low-pass capacitor is labelled C 3 . 
         [0035]    The feedback loop also has a different structure. In  FIG. 6 , the output voltage level U 1  is applied to the gate of transistor N 18 . The source of N 18  is connected to the reference potential, its drain to the source of transistor P 23  and to the gate of transistor P 26 . The source of P 26  is in turn connected to the drain of N 21 , and its drain to the source of transistor P 24 . The drains of P 24  and P 23  are connected to the positive reference potential GND +UB. The drain of N 21  is also connected to low-pass capacitor C 3  and to the gate of control transistor N 17 . The second terminal of C 3  is connected to the reference potential GND. The drain terminal of N 17  is connected to the positive reference potential GND, while the source of the transistor is connected to the drain of transistor N 16 . The gates of N 21  and N 16  are connected to the N-channel bias voltage U 4 , whereas the gates of P 23  and P 24  are connected to the P-channel bias voltage U 5 . 
         [0036]    The output voltage level U 1  is then set to a voltage through transistor N 18 . This static sensor output voltage charges or discharges the low-pass capacitor C 3  through the current-controlled inverter consisting of transistors P 24 , P 26  and N 24 . This inverter is biased by the N-channel or P-channel bias voltages U 4  and U 5 . The voltage dropped across C 3  controls the second auxiliary current I 3 , and this flows to the source terminal of input transistor N 1 . The constant current source, implemented in transistor N 16 , which is also biased by bias voltage U 5 , carries the additively superimposed constant current I 2  in the drain-source channel, consisting of the input current I 1  and the second auxiliary current I 3 . 
         [0037]      FIG. 7  shows a more detailed circuit of the example implementation, and differs from the circuit of  FIG. 6  in the following ways. It contains the differential amplifier ΔU described for the possible implementations, a reference voltage source that generates reference voltage U 2 , and the sample-and-hold switch A in the feedback loop. 
         [0038]    The output voltage U 1  is connected to the gate of transistor N 25  for this reason. The drain of N 25  is connected to the gate and source terminals of transistor P 35 . Its source, however, is connected to the source terminal of transistor N 24  and the drain of N 26 . Similarly, the drain of N 24  is connected to the source of P 34 . The gate of P 34  has a connection to the gate of P 35 . The drains of P 34  and P 35  are connected to the positive power supply voltage. The gate terminal of N 24  is joined to the gate and source terminals of P 42  and to the drain of P 43 . The gate and source of P 43  are at the reference potential GND. The drain of P 42  is joined to the gate and source of P 41 . The drain of P 41  is joined to the gate and source of P 40 . The drain of P 40  is at the positive operating potential. The drain of N 24  is connected to the drain of N 27  and to the drain of P 33 . The gate of N 27  is connected to the output of an inverter, while the gate of P 33 , on the other hand, is connected to the input of the inverter. The input to the inverter is labelled “HOLD”, and represents a voltage input. The sources of P 33  and N 27  are connected to the low-pass capacitor C 3 . From this point on, the feedback loop matches that shown in  FIG. 6 . 
         [0039]    The output voltage U 1  is compared with the reference voltage U 2  by a differential amplifier ΔU, consisting of N 24  and N 25 . The output voltage U 1  is therefore present at the input transistor N 25  of the differential amplifier ΔU. The differential amplifier ΔU is loaded by a current mirror, consisting of P 34  and P 35 , and is supplied with operating current through transistor N 26 , which is biased by voltage U 5 . The second input of the differential amplifier ΔU, which corresponds to the gate terminal of transistor N 24 , is fed from the reference voltage U 2 . This voltage U 2  is obtained from a reference voltage source consisting of a series connection of transistors P 40 , P 41 , P 42  and P 43 , tapped at the source terminal of transistor P 42 . This series circuit therefore comprises a potential divider, configured in such a way that the reference voltage level U 2  is approximately 400 mV. The resulting output voltage from the differential amplifier U 6  is now available at the drain terminal of transistor N 24 . This terminal is connected to the CMOS switch illustrated, consisting of P 33  and N 27 . The CMOS switch thereby implements the sample-and-hold switch A. The switch A is driven by the inverter. When the “Hold” input is held high, the switch consisting of P 33  and N 27  is conductive, passing the difference voltage signal U 6  to capacitor C 3 . 
         [0040]    On the basis of the fact that the electrical current converted, referred to below as the input current, consists of a rapidly changing component and a slowly changing component, this invention provides equipment and a method for reducing the dynamic range. Because the information is only contained in the rapidly changing current component, the slow changes in current are compensated by means of a dynamic control loop. The control loop is designed in such a way that the working point of this control loop does not change in response to fast changes in the current. This results in data transmission that is independent of slow changes in current; in other words, it does not depend on the field strength and therefore not on the distance between the transmitting and receiving units, and provides the data with a constant level of output current.