Abstract:
A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Description:
This application is a continuation of U.S. Pat. application Ser. No. 08/672,784 filed Jun. 28, 1996, now U.S. Pat. No. 6,115,769. 
    
    
     TECHNICAL FIELD 
     The present invention relates to electrical circuitry, and more particularly to a technique for generating accurate delay of electrical signals. 
     BACKGROUND OF THE INVENTION 
     In asynchronous bus isolating/bridging applications, such as a SCSI isolator or bus extender, signals need to be precisely delayed by a predetermined amount in order to guarantee or even improve setup or hold times on the resultant output bus. Current techniques involve the use of a dynamically varying string of standard cells (such as inverters or buffers), of length determined by comparison to a reference delay or clock, to achieve a fixed delay. The delay elements are duplicated throughout the chip. This approach is large, very difficult to test and not very precise. 
     It is desirable to provide a precise delay circuit that is small. In addition, the delay elements should be tolerant of process, voltage, and temperature variations. The following techniques achieves all these goals. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a method and apparatus for generating precise delays of electrical signals. The approach is based on a phase-locked loop (PLL), and uses a reference clock, typically a crystal oscillator, as a timing reference. This removes the necessity of using a self calibration feature. The PLL locks to the reference clock, generating some integer multiple of the reference frequency. The PLL has a voltage-controlled oscillator (VCO) that is made up of a string of delay elements. These delay elements are precisely controlled by the closed loop dynamic of the PLL. Hence, the delay is precisely controlled by the timing reference. By using a PLL with a timing reference, we can achieve the goals of process, voltage, and temperature insensitivity. We then duplicate the delays (which make up the VCO) to particular locations on the chip where a controlled delay is needed. In the preferred embodiment, the delay cells are current controlled. In this case, a number of currents are distributed throughout the chip to the delay cells. Finally, programmability can be incorporated by using a number of delay cells and selecting the desired delay through a multiplexer. 
     To summarize, we provide a precise delay that is generated by a timing reference via a PLL. The delay is then duplicated across the chip in the form of a delay cell which is current controlled. The delay cells tend to be much smaller than existing solutions. The techniques described hereinbelow reduce gate count from those of prior techniques, which saves chip area, test time and overall chip cost. 
     It is thus an object of the present invention to provide a precise delay of an electrical signal. 
     It is another object of the present invention to provide a method for delaying an electrical signal when propagating from one electrical element/device to another. 
     It is yet another object of the present invention to provide a delay technique using a phase-locked loop. 
     It is still another object of the present invention to provide a high precision programmable delay element. 
     It is yet another object of the present invention to provide an improved bus isolator/bridge circuit. 
     It is yet another object of the present invention to provide an improved bus isolator/bridge circuit having controllable delay elements. 
     Those having normal skill in the art will recognize the foregoing and other objects, features, advantages and applications of the present invention from the following more detailed description of the preferred embodiments as illustrated in the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of a phase-locked loop circuit. 
     FIG. 2 is a block diagram of a voltage-controlled oscillator circuit. 
     FIG. 3 is a schematic of a ring oscillator circuit. 
     FIGS. 4A and 4B is a schematic of a delay cell. 
     FIG. 5 is a schematic of a delay cell having a differential structure. 
     FIG. 6 is a schematic of two single-ended delay cells cascaded together. 
     FIG. 7 is a schematic showing current mirroring from a current source. 
     FIG. 8 is a schematic of a VCO in combination with an isolator circuit. 
     FIG. 9 is a block diagram for a bus isolator/bridge circuit. 
     FIG. 10 is a schematic of a programmable delay circuit. 
     FIGS. 11A and 11B show a computer bus, and extension thereof. 
     FIG. 12 shows a computer system having devices with dissimilar characteristics coupled to a controller. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a PLL synthesizer circuit  10  comprises a phase detector  12 , loop filter  14 , voltage controlled oscillator (VCO)  16 , and a divider  18 . The phase detector  12  compares the phase of the timing reference  20  and the output  24  of divider  18 . If there is a phase difference, an error signal  26 , which is proportional to the phase difference, is sent to the loop filter  14 . The VCO  16  then responds to the DC voltage  28  from the loop filter  14 . As the voltage  28  increases, so does the frequency of the VCO, and conversely, as the voltage  28  decreases, so does the frequency of the VCO. The divider  18  allows for providing an output clock having a frequency that is N times the frequency of the timing reference or clock frequency appearing at  20 . For example, if the input clock or timing reference  20  had a frequency of 40 MHz, and the divider had an N value of 5, the output frequency would be 200 MHz (i.e. 40 MHz ×5).    
     The operation of the VCO  16  will now be described. The present invention preferably employs a current starved architecture. However, the techniques described herein can be generalized to any architecture that uses delay cells. Referring now to FIG. 2, a current controlled oscillator (ICO)  32  is used to provide a VCO  16  by adding a voltage-to-current converter  30  to its front end. One embodiment of the ICO is shown in FIG.  3 . Using inverters  34  as delay cells, a ring oscillator is built having an odd number M of cascaded delay cells. The frequency of the oscillator can be computed by the relationship 
     
       
         freq=½ Mτ   d   
       
     
     where M is the number of stages and τ d  is the delay of the inverter. Stated another way, the delay of the inverter can be expressed as 
     
       
         τ d =2freq/ M   
       
     
     The frequency freq of the VCO is precisely controlled by the timing reference signal  20  (FIG.  1 ). Thus, as can be seen by the equations above, the delay τ d  of each inverter cell is also precisely controlled. The delay is precisely controlled by the closed loop dynamic of the PLL. 
     Inverters  34  are current starved inverters in the preferred embodiment. As its name suggests, the current in the inverter is starved by current sources in order to slow down the delay. The current starved inverter architecture used to create delay cells  36  is shown in FIG. 4A, and comprises an inverter  34  (comprising transistor pair MP 1  and MN 1 ) with two current sources  40  and  42 . The amount of current provided by the current sources  40  and  42  determines the delay through the inverter  34 . The current sources  40  and  42  are preferably realized, as shown in FIG. 4B, by transistors MP 2  and MN 2 , respectively. 
     A differential structure can also be used. This would allow an even number of delay stages in the VCO where one stage would be cross coupled. The cell shown in FIG. 5 is a differential starved inverter delay cell  136 . It can be used for differential type data, or followed by a differential to single-ended converter. Delay cell  136  comprises a differential inverter  134  and current sources  40  and  42 . As with the delay cell shown in FIG. 4B, current sources  40  and  42  determine the delay through differential inverter  134 . 
     To prevent inversion of the data signal, or to increase the delay of the cell, two single-ended delay cells  36  can be cascaded together as shown at  236  of FIG.  6 . If more delay is required, more delay cells can be cascaded. 
     Now that we have a complete and precise delay, as described above, we duplicate similar delay cells throughout the integrated circuit device, and mirror the VCO current to the delay cells. Since this current directly relates to a known delay, this current can be used to generate substantially the same delay in these other similar delay cells. 
     Referring now to FIG. 7, current from current source  44  is mirrored by current mirror  46  to current sources  45 . These current sources  45  are used to provide (1) a reference current I ref  to other delay cells in the integrated circuit, and (2) to provide a reference current I ref2  to the ICO delay cells. The delay cells in a given integrated circuit device will exhibit similar propagation characteristics. Thus, mirroring current to both the ICO delay cells of the VCOD (which have a given, known delay in the ICO), as well as the other delay cells, will produce a substantially similar delay in both the ICO delay cells and the other delay cells of the integrated circuit device. 
     FIG. 8 shows how the mirrored current  48  from the VCO  16  is used to control the delay in other delay cells  56 . As can be seen, this mirrored current  48  is used to control current sources  50  of delay cells  56 . In addition, the V-I output current  31  is used to control current sources  52  of delay cells  56 . Delay cells  56 , each including current sources  50  and  52  and a current-starved inverter  54 , provide similar function and characteristics as the delay cell  36  of FIGS. 4A-B. Thus, the delay provided by delay cells  56  is substantially the same as that provided by delay cells  36  in the ICO  32 . It is therefore possible to accurately and precisely delay electrical signals propagated from circuits such as  58  and  60  to circuits  62  and  64 , respectively. 
     An application for using the previously described precision delay technique is shown in FIG. 9. A bus isolator/bridge circuit  96  is shown, and comprises the above described PLL  10  along with digital and delay circuitry  76 . The isolator bridge circuit  96  can be used to couple together to ports, such as computer buses, as will be later described below. 
     Programmability can be built in by cascading several delay cells together and selecting the desired delay through a multiplexer. This is shown in FIG.  10 . Delay cells  56  are serially cascaded together in the preferred embodiment. The outputs of each successive stage are coupled to the input of multiplexer  66 . By proper selection of the multiplexer&#39;s control lines, it is possible to delay the propagation of the IN signal to the OUT signal by 1X, 2X . . . or ZX. Traditional techniques are used to manipulate the multiplexer control lines, such as hardwiring such lines to switches to allow user selectable delays, coupling the control lines to a microprocessor/controller for programmable control by such microprocessor/controller, etc. 
     A system using the above described delay techniques will now be described. A bus isolator/bridge may be desired to isolate two computer busses from one another, or bridge one bus to the other. Certain computer busses, such the small computer system interface (SCSI) bus, have well defined signal characteristics, such as allowable voltages/currents, timing, noise, etc. These signal characteristic requirements dictate certain constraints on cabling used to interconnect devices on the SCSI bus. Using an isolator on such a bus allows one to effectively extend the bus, as will now be shown by the following examples. 
     Referring to FIG. 11A, there is shown as SCSI bus cable interconnecting a plurality of devices on a SCSI bus. In the embodiment shown, SCSI controller  72  is coupled to a plurality of storage devices  74  via SCSI bus  70 . Due to the above described signal characteristic constraints, there is a limited number of devices that are allowed to be coupled to SCSI bus  70 . There is also a constraint as to the physical length of the SCSI cable providing the bus interconnect to the devices. By adding a bus isolator/bridge, the bus can be effectively extended. This is shown in FIG. 11B, where bus isolator/bridge  96  allows for connecting an additional SCSI cable  78 , to allow for coupling of additional SCSI devices  80  to controller  72 . 
     FIG. 12 shows another application of an isolator/bridge. Here, a computer  82  has an electronics board  84  contained therein. A bus controller  86  on board  84  is used to communicate with one or more devices  88  inside the computer chassis, via bus  90 . Use of bus isolator  96  allows for coupling external devices  92  to controller  86  via bus  94 . This bus may have different performance characteristics than internal bus  90 , and hence the bus isolator provides downwards compatibility. When advances in bus technology occur, certain older devices are still capable of being used in combination with new, higher performance devices. 
     In asynchronous bus isolating/bridging applications, such as a SCSI isolator or bus extender, signals need to be precisely delayed by a predetermined amount in order to guarantee or even improve setup or hold times on the resultant output bus. Thus, the above described delay techniques are particularly useful for such isolation/bridge applications. However, it should be noted that the above uses of an isolator/bridge are by way of example only. The key aspect of the invention described herein is how to provide precise delays, and a bus isolator is but one example of why precise delays might be desired. There are likely numerous other applications for precise delays that could advantageously utilize the techniques described hereinabove. 
     While we have illustrated and described the preferred embodiments of our invention, it is to be understood that we do not limit ourselves to the precise constructions herein disclosed, and the right is reserved to all changes and modifications coming within the scope of the invention as defined in the appended claims.