Abstract:
A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention is related to integrated circuits (ICs) and more particularly to circuits and methods of measuring and monitoring device temperature on ICs.  
         [0003]     2. Background Description  
         [0004]     It is well known that diode current can be approximated by I=I 0 (e qV/kT −1), where I 0  is the diode turn on current, q is the charge magnitude, V is the junction bias voltage, k is the Boltzmann&#39;s constant and T is junction temperature. Similarly, field effect transistor (FET) characteristics, including threshold voltage (V T ), device drain to source current (I ds ) and leakage currents are related to the temperature of the material (e.g., semiconductor) embodying the FET by well known relationships. In a typical integrated circuit (IC), individual circuit device currents combine to drive capacitive loads at circuit nodes. So, if local (device or junction) temperature is known, device current and, correspondingly, circuit performance can be calculated very precisely. Consequently, an accurate device model requires an accurate device current description.  
         [0005]     Current through semiconductor (e.g., silicon) junctions and devices generates heat locally. On a typical IC chip, each such junction or device may act as a local heat source and, more particularly, as a point heat source. How heat is conducted away from each point source depends upon its surrounding and thermally connected structures. For example, how the point source cools may depend in part on whether the circuit is in bulk silicon (Si) or silicon on insulator (SOI), whether the heat source is a single isolated device on a silicon island or is one heat source amongst a group of heat sources, whether metal directly contacts the heat source and etc. Glass (Si/SiO) is a poor heat conductor. So, circuits and even individual devices on a silicon island may be thermally insulated from each other, even though they reside on the same chip. Unfortunately, heat dissipation in modern SOI is not well understood. Previously, only crude imprecise temperature measurements have been available, e.g., chip level thermal measurements or using thermal imaging to characterize circuit-wide temperatures. Measuring gate resistance has provided the temperature of a structure one or two layers above the device active region, the region of concern and, still provides a somewhat distorted reflection of the channel temperature. So, for example, each junction/device is simulated, normally, at the same temperature as every other junction/device on the same circuit or a chip.  
         [0006]     Further, device temperature may vary depending upon its immediate history. For example, a device in memory select logic may be switched on after several cycles of dormancy and so, may add little to ambient temperature. By contrast a device in a multiplexor may be switching aperiodically, making a variable contribution to ambient; an inverter in a clock buffer may be switching every cycle, cumulatively contributing to ambient and, itself being at a significantly higher temperature than ambient.  
         [0007]     Consequently, because so little information is available about instantaneous thermal conditions at and for any particular device, normally, device current is modeled at one or more particular temperatures, e.g., nominal and both expected extremes. In addition, because it has been difficult, if not impossible, to characterize heat variations other than for large areas, individual device temperature and thermal time constants are not well known. However, without an accurate description of these parameters, e.g., a temperature to time relationship, it has not been possible to construct thermally accurate device models, much less monitor local circuit/device temperature during actual operation, e.g., to signal a shut down when device temperature exceeds an acceptable limit.  
         [0008]     Thus, there is a need for an accurate characterization of IC structure temperatures and for a way to monitor junction and device temperatures during chip operation.  
       SUMMARY OF THE INVENTION  
       [0009]     It is a purpose of the invention to improve semiconductor device models;  
         [0010]     It is another purpose of the invention to accurately model device temperature in integrated circuits (ICs);  
         [0011]     It is yet another purpose of the invention to accurately determine device operating temperature;  
         [0012]     It is yet another purpose of the invention to monitor device temperature in real time and on the fly.  
         [0013]     The present invention relates to a device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:  
         [0015]      FIG. 1  shows an example of a device temperature measurement circuit as applied to a typical inverter;  
         [0016]      FIG. 2  shows an example of how to determine a relaxation thermal time constant for a suitable device model;  
         [0017]      FIG. 3A  shows an example of a ring oscillator that includes a device temperature measurement circuit substantially as described in  FIG. 1 ;  
         [0018]      FIG. 3B  shows a timing diagram for a simple example of using the circuit of  FIG. 3A  for measuring and monitoring chip/circuit temperature, e.g., in a microprocessor. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0019]     Turning now to the drawings and, more particularly,  FIG. 1  shows an example of a device temperature measurement circuit  100  according to a preferred embodiment of the present invention, as applied to a typical inverter  102 . In particular, a preferred embodiment device temperature measurement circuit  100  measures the temperature of the particular device itself, which may be well above ambient. Further, the present invention has application both to characterization of temperature related device characteristics and to device temperature monitoring. This particular example is described with reference to application in a typical insulated gate complementary field effect transistor (FET) circuit (inverter  102 ) in what is commonly referred to as CMOS; and, more particularly, with reference to silicon on insulator (SOI), wherein devices are formed in P-type and N-type semiconductor (silicon) surface islands on an insulator (oxide) layer. However, the present invention has application to characterization and modeling in any suitable technology with an isolatable, contactable body, e.g., Silicon on sapphire. Further, a preferred embodiment device temperature measurement circuit  100  can be in a separate characterization circuit or, included in an actual circuit and used for auto-sensing, e.g., where it may be advantageous to monitor a critical functional device for excessive heating.  
         [0020]     In this example, the inverter  102  includes an N-type FET (NFET)  102 N and a P-type FET (PFET)  102 P. A clamping NFET  104  is connected to the body  106  of inverter NFET  102 N. A constant current source  108 , preferably in the range of 10 μA-100 nA and located on chip, is connected in parallel with the clamping NFET  104  to the body  106  of inverter NFET  102 N, the device being characterized/monitored for temperature. Constant current source  108  may be, for example, an NFET current-mirror circuit. A diode  110  represents the natural PN junction between the body and the source of the NFET  102 N in this example. Essentially, inverter NFET  102 N heats up during use and that heat is reflected in the forward bias voltage (V f ) of diode  110 . By forcing a known current through the diode  110  with NFET  102 N off and measuring the voltage across the diode  110  (V f ) at various temperatures, a voltage to temperature relationship is defined for the diode. Thereafter, the junction temperature may be determined from the diode voltage at the same current. During normal operation, clamping NFET  104  is switched on, shunting the current from current source  108  and clamping the body  106  of inverter NFET  102 N, more or less, to ground. Junction temperature may be monitored, periodically, by switching off both NFETs  102 N,  104  and measuring junction voltage. Of course, it is understood that the present invention has application to any suitable circuit including, for example, complex logic circuits such as adders, multiplexers, repeaters, etc.  
         [0021]      FIG. 2  shows an example  120  of how to determine a relaxation thermal time constant for a suitable device model according to a preferred embodiment of the present invention. First, beginning in step  122  chip junctions are calibrated, for example, using a hot-chuck or temperature chamber. Next, in step  124  the temperature of the chip, wafer, etc., is elevated or ramped with the inverter NFET  102 N and clamping NFET  104  held off. In step  126 , the junction voltage across the junction diode  110  is measured at multiple temperatures, e.g., by measuring voltage across the current source  108  and, correspondingly, the voltage across clamping NFET  104 . After each measurement in step  128  the voltage-temperature for the junction is logged in a calibration table to very precisely relate junction temperature and voltage for that particular device. In step  130 , if the maximum temperature has not been reached, calibration is still underway and returning to step  124  ramping continues. Once the maximum test temperature is reached in step  130  and calibration and resulting calibration table are complete. The clamping NFET  104  is switched on in step  132 , and the hot chuck or temperature chamber is allowed to cool to room temperature.  
         [0022]     The resulting voltage-temperature calibration table can be used with a preferred embodiment device temperature measurement circuit (e.g.,  100 ) to generate a temperature based relaxation curve and determine a relaxation thermal time constant for the particular device, e.g.,  102 N. Essentially, the circuit (inverter  102 ) is operated at its highest expected capacity with the switch dormant and temperature is monitored over a selected cooling period. The relaxation thermal time constant may be used to model the device or similar devices. So, turning on the clamping NFET  104  shunts current from current source  108  and provides a ground bias to the body  106  of inverter NFET  102 N. Then, in step  134  the inverter  102  is switched, e.g., at maximum operating frequency. After sufficient time for the junction to reach an expected maximum operating temperature, in step  136  the switching inverter  102  is stopped and the clamping NFET  104  is switched off. Finally, in step  138  the junction voltage measured at regular intervals using an on-chip A/D converter. The digital output of the A/D converter (not shown) can be stored or sent off chip where the measurements are logged. Thereafter, the logged voltage measurements may be converted to temperature using the voltage-temperature calibration table. The converted information may be used in the junction model for a much more precise accurate device model.  
         [0023]      FIG. 3A  shows an example of a simple circuit implementation  140  of a preferred embodiment device temperature measurement circuit, e.g.,  100  in  FIG. 1 , in a ring oscillator  142 . The ring oscillator  142  of this example includes 5 inverting stages  144 ,  146 ,  102 ,  148  and  150 . One stage  144  is a NAND gate and the remaining stages  146 ,  102 ,  148  and  150  are inverters. An enable or gating signal (gate_osc)  152  is a common input to the NAND gate  144  and the gate of clamping NFET  104 . The NAND gate output  154  is in phase with measurement circuit inverter output  156 . The voltage (V f ) may be provided to an over-temp circuit  158  for selectively generating an alarm when an over-temperature condition is detected. Over-voltage circuit  158  may be, for example, a simple comparator for comparison against a reference voltage (V ref ) or, as noted hereinabove, an A/D converter.  
         [0024]      FIG. 3B  shows a timing diagram for a simple example of using the circuit of  FIG. 3A  for measuring and monitoring chip/circuit temperature according to a preferred embodiment of the present invention, e.g., in a microprocessor. First, in period  160  with the gating signal  152  high, the clamping NFET  104  is on, shunting current from current source  108 ; and, NAND gate  144  inverts the output of inverter  150 . So, the oscillator  142  is free running. After sufficient time for the inverter junction to heat to its steady state operating temperature, in period  162  the gating signal  152  is dropped, which turns clamping NFET off and simultaneously forces the output  154  of NAND gate  144  high, stopping the oscillator. The output  156  of inverter  102  is high and a voltage (V f ) develops across the junction at  106  in response to the current from current source  108 . As noted above, the voltage (V f ) may be provided, for example to a comparator  158 . The comparator may trigger an over temperature alarm (also not shown), whenever the voltage (V f ) indicates that the temperature exceeds a maximum allowed value. Thereafter, e.g., if no alarm is triggered or if the alarm does not result in halting the oscillator  100  (e.g., for cooling), in period  164  the gating signal  152  may be raised so that the oscillator resumes oscillating. The measurement may be repeated in  166  at some selected future time, e.g., periodically or upon request.  
         [0025]     Advantageously, the forward voltage (V f ) of the P-N junction (and therefore its temperature) may be sensed immediately and on the fly. Thus, the temperature of the device itself (which may be well above ambient) is being individually determined and time sensitive temperature data is not lost, e.g., due to line charging delays from using an external current source or from transient settling time delays. Sensing can be either off-chip or on-chip using an analog comparator or, an A/D converter in combination with a digital compare and a scannable typical threshold value. The result is much more accurate than measuring neighboring device temperatures and trying to extrapolate temperature for the actual device of interest. Instead, application of the present invention measures the actual device temperature in the actual logic gate. Temperature can be monitored in any circuit, even on a device embedded in an IC chip mounted in a module in active operation, e.g., a microprocessor in a computer.  
         [0026]     While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.