Abstract:
Semiconductor structures formed using redeposition of an etchable layer. A starting material is etched and redeposited during the etch on a sidewall of a foundation. The foundation may be removed or may form an integral part of the structure. The starting material may contain one or more layers of material. The structures are adapted for a variety of capacitor structures.

Description:
This application is a divisional of U.S. application Ser. No. 09/103,202, filed Jun. 23, 1998, now U.S. Pat. No. 6,027,860 which is a continuation of U.S. application Ser. No. 08/905,785, filed Aug. 13, 1997, now U.S. Pat. No. 5,792,593. 
    
    
     FIELD OF THE INVENTION 
     The invention relates to the fabrication of semiconductors and more particularly to the fabrication of a structure formed by redepositing a starting material. 
     BACKGROUND OF THE INVENTION 
     Sidewall passivation occurs during a chemical deposition on sidewalls of a structure. Typically, sidewall passivation is used to enhance a mask in order to increase the integrity of the mask thereby eliminating undercut and other etching defects caused when portions of the mask itself are consumed during an etch. The chemical deposit is then typically removed since it is used to perform the process and is not a structural goal of the total process. 
     SUMMARY OF THE INVENTION 
     The invention is a method for forming a structure wherein a starting material is etched and redeposited during the etch on a sidewall of a foundation. In one embodiment the foundation is removed subsequent to the etch to leave the redeposited starting material and unetched starting material to form the structure. This structure may be a capacitor electrode. In this embodiment a capacitor may be formed by forming a dielectric layer and a conductive layer overlying the structure. 
     In a second embodiment the foundation may form an integral part of the final structure. In this case a capacitor can be formed by depositing a dielectric and a conductive layer overlying the structure. 
     In still a further embodiment a capacitor may be formed using a single etch wherein redeposition occurs during the single etch. In this case two conductive layers are formed overlying a substrate and a dielectric layer is formed interposed between the conductive layers. The etch is performed after masking of the layers with a foundation. The etch creates particles or portions of each layer which are then deposited on a sidewall of the foundation to create the capacitor. 
     When a photoresist mask is used as the foundation the size of the structure made by the method of the invention is determined only by photolithography limits. The smallest size mask definable by lithography may be used for forming the container cell. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional view of a masked portion of a substrate having a starting material and positioned in an etching environment 
     FIG. 2 is the portion of the substrate shown in FIG. 1 following an etch and redeposit of the starting material. 
     FIG. 3 is the portion of the substrate shown in FIG. 2 following the removal of the mask. 
     FIG. 4 is a top planar view of the portion of the substrate shown in FIG.  3 . 
     FIG. 5 is the portion of the substrate and the structure shown in FIG. 3 following the formation of a dielectric layer, a conductive layer and a mask 
     FIG. 6 is the portion of the substrate and the structure shown in FIG. 5 following an etch of the dielectric layer and the conductive layer and following the removal of the mask 
     FIG. 7 is a cross-sectional view of a portion of a substrate and masked conductive layers interposed with a dielectric layer. 
     FIG. 8 is the portion of the substrate shown in FIG. 7 following etching and redeposition of the conductive layers and the dielectric layer. 
     FIG. 9 is the cross sectional view of the portion of the substrate shown in FIG. 8 following the removal of the mask. 
     FIG. 10 is a cross-sectional view of conductive layers interposed with a dielectric layer and masked with a conductive plug and overlying a portion of a substrate. 
     FIG. 11 is the portion of the substrate of FIG. 10 following an etch and redeposition of the conductive layers and the dielectric layer. 
     FIG. 12 is a cross-sectional view of a dielectric layer and a conductive layer redeposited on a sidewall of a conductive plug. 
     FIG. 13 is a colored copy of a photograph taken with a scanning electron microscope showing an isometric view of a structure of the invention. 
     FIG. 14 is a colored copy of a photograph taken with a scanning electron microscope showing a cross-sectional view of a structure of the invention Similar structures of the invention can be seen in the background. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention is a method for forming a structure by redepositing a deposited material during an etch of the deposited material. 
     The redeposit is mechanical in that the etch accelerates particles of the deposited material some of which bombard sidewalls of a foundation provided to create a base on which the accelerated particles can form the redeposited material. Thus the redeposited material has the same chemical composition as the originally deposited (or formed) material. 
     In one embodiment shown in FIG. 1 a starting material  5  is deposited to overlie a substrate  10 . In a preferred embodiment the starting material  5  is platinum although other materials such as TiPt, TiNPt, r, TiAlN—Pt Ru, RuO 2 , RuPt, RuO 2 Pt, W, WPt, WSi, TiSi, Ta, TaN, TaSi, doped and undoped Poly Si, Al, Pd and Ir may be used. A foundation  15  is formed overlying the starting material  5 . In this embodiment the foundation  15  is a photoresist mask the size of which is limited only by photolithic techniques. Although the foundation  15  shown in the accompanying drawings is rectangular any shape may be formed. The starting material  5  is etched in an argon plasma environment at radio frequencies using an Ion Mill etcher as an RF ion source  20 . Etching with argon in an Ion Mill etcher is well known to those skilled in the art. It is also possible to use other materials as etchants. 
     During etching portions of the starting material  5 , in this case platinum, are redeposited as portions  25  on the sidewalls of the foundation  15 , see FIG.  2 . Typically, the angle of incidence between the starting material  5  and the trajectory of an accelerated etchant ion is selected to maximize the amount of redeposition of the starting material  5  on the sidewalls of the foundation  15 . A 90 degree angle of incidence typically works well. 
     In FIGS. 3 and 4 the photoresist has been striped leaving the structure  27  comprising platinum portions  5  and  25  formed by the method of the invention. 
     The platinum structure  27  may be used as a storage node electrode for a container cell capacitor. In this case the process is continued, as shown in FIGS. 5 and 6, in order to complete the capacitor fabrication. 
     In FIG. 5 a dielectric layer  30  has been deposited to overlie the platinum structure  27 . This deposition is followed by the deposition, typically a sputtering, of a conductive layer  35  to overlie the dielectric layer  30 . The dielectric layer  30  and the conductive layer  35  are then patterned with mask  38 . The dielectric layer  30  and the conductive layer  35  are etched according to means known to those skilled in the art to form the capacitor  40  shown in FIG.  6 . 
     In a case where Osmium, Iridium, or Ruthenium is used in place of Platinum, the structures formed by the process of the invention may be oxidized thereby forming OsO x , IrO 2  or RuO 2  respectively. 
     In a further embodiment, shown in FIGS. 7-9, tree starting materials, two conductive layers  50  and  55  having a dielectric layer  60  interposed therein, are deposited overlying a substrate  65  (see FIG.  7 ). The conductive layers  50  and  55  are patterned with a foundation  70 , typically a photoresist mask, and then the conductive layers  50  and  55  and the dielectric layer  60  are etched insitu, typically using a single etch step. 
     In FIG. 8, as conductive layer  55  is etched it is redeposited on the sidewalls of the foundation  70  to form a vertical conductive (to the substrate) layer  75 . The etch continues and the dielectric layer  60  is redeposited to form a vertical-dielectric layer  80 . The etch further continues to etch conductive layer  50  which is redeposited during the etch as vertical conductive layer  90 . Among the appropriate materials for the conductive layers  50  and  55  are platinum, conductive oxides, and polysilicon. The redeposited layers  75  and  90  are the same material as the original conductive layers  50  and  55 . Therefore if  50  and  55  are platinum the redeposited layers  75  and  90  are also platinum. The same is true of the dielectric layer. Dielectric layer  60  may be chosen from a group of dielectrics selected from the group consisting of Ba(1-x)SrxO 3 , PbZr(1-x)TixO 3 , PZT with various dopants such as LA etc., Sr(1-x)BixTaO 3 , Sr(1-x)BixTiO 3  and all of the other Smolenski compounds, PbMg(1-x)NbxTiO 3  (PMN), compounds with PbTiO 3  (PMN-PT), CaBi 2 Nb 2 O 9 , SrBi 2 Nb 2 O 9 , BaBi 2 Nb 2 O 9 , PbBi 2 Nb 2 O 9 , BiBi 2 NbTiO 9 , BaBi 4 Ti 4 O 15 , CaBi 2 Ta 2 O 9 , SrBi 2 Ta 2 O 9 , BaBi 2 Ta 2 O 9 , PbBi 2 Ta 2 O 9 , Bi 4 Ti 3 O 12 , SrBi 4 Ti 4 O 15 , BaBi 4 Ti 4 O 15 , PbBi 4 Ti 4 O 15 , (Pb, Sr)Bi 2 Nb 2 O 9 , (Pb, Ba)Bi 2 Nb 2 O 9 , (Ba, Ca)Bi 2 Nb 2 O 9 (Ba, Sr)Bi 2 Nb 2 O 9 , BaBi 2 Nb 2 O 9 , Ba 0.75 Bi 2.25 Ti 0.25 Nb 1.75 O 9 , Ba 0.5 Bi 2.5 Ti 0.5 Nb 1.5 O 9 , Ba 0.25 Bi 2.75 Ti 0.75 Nb 125 O 9 , Bi 3 TiNbO 9 , SrBi 2 Nb 2 O 9 , Sr 0.8 Bi 2.2 Ti 0.2 Nb 1.80   O   9 , Sr 0.6 Bi 2.4 Ti 0.4 Nb 1.6 O 9 , Bi 3 TiNb 9 , PbBi 2 Nb 2 O 9 , Pb 0.75 , Bi 2.25 Ti 0.25 Nb 1.75 O 9 , Pb 0.5 Bi 2.5 Ti 0.5 Nb 1.5 O 9 , Pb 0.25 Bi 2.75 Ti 0.75 Nb 125 O 9 , Bi 3 TiNbO 9 , PbBi 4 Ti 4 O 15 , Pb 0.75 Bi 4.25 Ti 3.75 Ga 0.25 O 15 , Pb 0.5 Bi 4.5 Ti 3.5 Ga 0.5 O 15 , and Bi 5 Ti 3 GaO 15 . Although it is desirable, in order to minimize processing steps, to use only one etchant and only etch step it is possible to perform the method of the invention using multiple etchants or multiple etch steps. 
     As in the previous embodiment the foundation  70  is removed using conventional methods, see FIG.  9 . The structure  100  of the invention remains. In this case the structure  100  is a storage cell capacitor formed using a single etch process performed in an argon plasma environment at radio frequencies using an Ion Mill etcher as an RF ion source wherein the angle of incidence is 90 degrees. Variations of this etch, including etchants and angle of incidence, may be used as long as the desired sidewall deposition occurs during the etch. 
     In still a further embodiment, as shown in FIGS. 10 and 11, two conductive layers  105  and  110 , interposed with a deposited dielectric layer  115 , are deposited to overlie a substrate  120 . A conductive plug  125  is fabricated by conventional means to overlie conductive layer  105 . A polysilicon plug is one preferred choice for the conductive plug  125  however the conductive plug  125  may be of a material selected from the group consisting of TiPt, TiNPt, TiAlN—Pt, Ru, RuO 2 , RuPt, RuO 2 Pt, W, WPt, WSi, Ti, TiSi, Ta, TaN, TaSi, doped and undoped Poly Si, Al, Pd and Ir. Other conductive materials may be used as well. 
     FIG. 11 shows the redeposition of the conductive layers  105  and  110  and the redeposition of dielectric layer  115  following an etch of the layers  105 ,  110 , and  115 . A storage node capacitor  130  is formed during the redeposition. The storage node capacitor  130  has conductive layer  110  as a storage node electrode and has conductive layer  105  and conductive plug  125  as a cell plate electrode. 
     In an alternate embodiment the deposition of conductive layer  105  may be eliminated. The storage node electrode thus formed has conductive layer  110  as the storage node electrode and has the conductive plug  125  as the cell plate electrode, see FIG.  12 . 
     While the invention has been described in its preferred embodiments it is to be understood that the words which have been used are words of description rather than limitation and that changes may be made within the purview of the appended claims without departing from the true scope and spirit of the invention in its broader aspects.