Abstract:
The present amplifier is designed in such a way that the amplifier will exhibit a linear characteristic in response to small variations of the input signal and a hard switching characteristic in response to large variations of that input signal. Due to the design of this amplifier, the output signal will generally be proportional to the input signal, but will be able to respond more quickly to a sudden increase of the input signal. The present amplifier is particularly useful in an amplifying circuit of a videoamplifier.

Description:
FIELD OF THE INVENTION 
     The present invention relates to an amplifier with a broad bandwidth and more particularly to a videoamplifier with a broad bandwidth. 
     BACKGROUND OF THE INVENTION 
     If the output signal of an amplifier is treated as a binary signal, the amplifier should have a hard switching characteristic. On the other hand, if the output signal should have a plurality of different values, an amplifier with a linear characteristic should be used. However, the large signal behavior of conventional linear amplifiers has proved not to be satisfactory in certain applications such as videoamplifiers where the output signal must have many different values corresponding to different picture half-tones and must also follow large, rapid changes in the input. 
     In particular, if a sudden stepwise rise occurs in the input signal of a linear videoamplifier, it is observed that the output signal cannot keep up with the rise of the input signal, because the output voltage of such a videoamplifier is only increased with a limited slew rate. It does not have a hard switching characteristic. Thus, the output signal will reach the desired voltage level only after a certain rise time. If the signal that has to be amplified is a pulse signal which has a pulse width on the order of or even smaller than the rise time of the amplifier, the output signal will not be able to reach its full amplitude. Consequently, the bandwidth of the linear amplifier is limited by this rise time. 
     A videoamplifier is shown in U.S. Pat. No. 4,414,574. This amplifier is concerned with the problem of cutting off the beam current of a CRT when the input is zero volts. U.S. Pat. No. 3,689,848 shows a voltage-to-current converter circuit having a differential amplifier coupled to the output through transistors in a Darlington configuration. This circuit is designed to simulate a voltage controlled current source with good thermal stability. 
     It would be desirable, therefore, to provide an amplifier, and more particularly a videoamplifier, which has an increased bandwidth and is capable of reproducing variations in the output level over a wide range of amplitudes, even when the pulse width of the input signal is small. It would also be desirable to have an amplifier which had a linear response to small variations in the input signal and a hard switching response to large variations in the input signal. 
     SUMMARY OF THE INVENTION 
     The present invention relates to an amplifier in a one-stage or a multi-stage amplifying circuit which is designed in such a way that it exhibits a linear characteristic in a range of small variations of the input signal and a hard switching characteristic in the range of large variations of the input signal. Due to the hard switching characteristics of the transistor means used in the amplifier, the slew rate of the amplifier is increased and the rise time of the output signal in response to a large stepwise rise of the input signal is reduced. On the other hand, when the variation of the input signal is small or when the input signal is substantially constant after a large stepwise rise, the linear characteristic of the transistor means is predominant so that the output signal is kept at the desired level proportional to the input level. 
     The present invention provides an amplifier for generating an output signal from an input signal comprising: a first current source connected to a branched circuit; a first transistor means provided in a first branch of the branched circuit, the first transistor means being responsive to the input signal to control a current flowing in the first branch; a second circuit source provided in a second branch of the branched circuit; a second transistor means provided in the second branch between the first current source and the second current source to generate the output signal; and a feedback circuit connected to the output signal and the second transistor means for deriving a control signal for the second transistor means from the output signal. The embodiments of this amplifier, as described hereinafter, result in a simple, low-cost circuit construction and also reduced energy dissipation in the transistor means. 
     In the amplifier of the present invention, preferably both the first and second transistor means exhibit a linear characteristic in response to small variations in the input signal and a hard switching characteristic in response to large variations in the input signal. As a result, this amplifier is particularly useful in the amplifying circuit of a videoamplifier since it is capable of amplifying typical video signals such as a pulse-like signal whose amplitude varies between sixteen distinct values corresponding to sixteen different picture half-tones. Even if the frequency of the input signal to a videoamplifier of the present invention is large, such as 150 to 200 MHz, the maximal rise time of the output signal of the amplifier will be smaller than the pulse width so that all sixteen output levels will be fairly distinguishable from each other. 
     Other details, objects and advantages of the present invention will become more readily apparent from the following description and accompanying drawings of presently preferred embodiments thereof. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings, preferred embodiments of the present invention are illustrated, by way of example only, wherein: 
     FIG. 1 is a circuit diagram showing an embodiment of the amplifier according to the present invention; 
     FIG. 2 shows a circuit diagram of a modification of the embodiment shown in FIG. 1; 
     FIG. 3 is a circuit diagram showing a second embodiment of the amplifier according to the present invention; 
     FIG. 4 shows a circuit diagram of a modification of the embodiment shown in FIG. 3; and 
     FIG. 5 shows a circuit diagram of another modification of the embodiment shown in FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As shown in FIG. 1, the amplifier of the present invention comprises a first current source 10, preferably a constant current source, connected to a branched circuit 12 which has first and second parallel branches, 14 and 16, respectively, connected in series to current source 10. The first branch 14 includes a first transistor means, preferably transistor T 1 , which has its collector connected to a positive voltage terminal. The input signal to the amplifier, preferably voltage V i , is supplied to the base of transistor T 1 . 
     The second branch 16 includes a second transistor means, preferably transistor T 2 , the collector of which is connected to a second current source 18, preferably a constant current source. The output signal of the amplifier, preferably voltage V o , is picked up at a point between current source 18 and transistor T 2 . A capacitive load is connected to the output of the amplifier and is represented by a capacitor C. A feedback circuit 20 for controlling base voltage V b2  of transistor T 2  is connected to second constant current source 18 and the base of transistor T 2  and preferably comprises a resistor R 1  connected between the collector and the base of transistor T 2 , and a resistor R 2  and a capacitor C 2  connected in parallel between the base of transistor T 2  and ground. 
     Preferably, transistors T 1  and T 2  are of the same type and current I 2  flowing through current source 18 is one half of current I tail  flowing through current source 10. Consequently, current I 1  flowing through transistor T 1  is equal to current I 2  and, therefore, the base voltage V b2  of transistor T 2  is normally equal to the input voltage V i . 
     In response to small or slow variations of input voltage V i , base voltage V b2  changes in accordance with V i . If, for instance, input voltage V i  is increased, the base-emitter voltage drop across transistor T 2  is reduced so that the emitter voltage V e  of both transistors T 1  and T 2  becomes larger. As the base-emitter voltage of transistor T 2  tends to be reduced, the voltage drop across transistor T 2  is increased and consequently output voltage V o  is also increased. Base voltage V b2  of transistor T 2  is increased due to the effect of the voltage dividing resistors R 1  and R 2 . A new equilibrium is reached when V b2  equals the new level of input voltage V i . The amplification factor A of the amplifier is given by the following equation: 
     
         A=V.sub.o /V.sub.i =V.sub.o /V.sub.b2 =1+R.sub.1 /R.sub.2  (1) 
    
     Hard switching occurs in the event there is a large sudden increase in the input voltage V i . When this occurs, feedback circuit 20 increases base voltage V b2  of transistor T 2  only with a certain delay which in the present embodiment is determined by the capacitance of capacitors C and C 2 . In this situation, transistors T 1  and T 2  behave like switches with transistor T 1  being fully opened while transistor T 2  is fully closed (i.e., the maximum current is flowing through transistor T 1  while none is flowing through transistor T 2 ). Consequently, all of current I 2  is available for charging load capacitor C. This results in the desired superproportional increase in the output voltage V o . 
     During the hard switching of transistors T 1 , T 2 , the slew rate, i.e., the maximal rate of increase of output voltage V o  is given by equation (2): 
     
         V.sub.o =I.sub.2 /C.sub.tot                                (2) 
    
     wherein C tot  is the total output capacitance. If V o  is a sinusoidal output signal with a maximum amplitude of V max , then the bandwidth (indicated by f(-3 dB) is given by equation (4). Equation (3) shows some of the intermediate substitutions made in equation (2) to get equation (4). ##EQU1## Using equation (4), one can see that if the maximum output amplitude V max  is 10 V and the total output capacitance is 8 p  F, and if I tail  is set to 108 mA, the bandwidth f(-3 dB) is as large as 150 MHz. 
     The capacitance of C 2  should be adjusted so as to optimize the small signal behavior of the amplifier. Considering a straight frequency curve, C 2  should be on the order of: 
     
         C.sub.2 =2·re·A·(C+C.sub.c)(1/R.sub.1 1/R.sub.2)+C.sub.c R.sub.1 /R.sub.2                       (5) 
    
     wherein C c  is the collector-base capacitance of transistor T 2 , re is the emitter impedance (i.e. U BE  /I C ) of transistor T 2  and A is the amplification factor as shown in equation (1). 
     FIG. 2 shows a circuit diagram of a modification of the amplifier shown in FIG. 1 wherein: transistor T 2  has been replaced by a series connection of two transistors T 21  and T 22  ; resistor R 1  has been replaced by a series connection of two resistors R 11  and R 12  ; the base of transistor T 22  is connected to a point between resistors R 11  and R 12  ; and a capacitor C 3  having a value substantially equal to C c  is provided for compensating the influence of the collector-base capacitance C c  of transistor T 21  and is connected in parallel to resistor R 11 . 
     Current source 10 is preferably formed by a transistor T 3  and an emitter resistor R 3  which is connected to a negative voltage terminal V 1 . The base of transistor T 3  is connected to another negative voltage terminal V 2 . Current source 18 is preferably formed by a series connection of two transistors T 41  and T 42  and an emitter resistor R 4  connected to a positive voltage terminal V 3 . The base of transistor T 42  is connected to voltage terminal V 4 . The base of transistor T 41  is connected to voltage terminal V 4  and to output terminal V o  through resistors R 5  and R 6  respectively. A capacitor C 4  is connected in parallel with resistor R 5  and has a capacitance substantially equal to the capacitance C c  of transistor T 42 . 
     The advantage of having a series of transistors (T 21  and T 22 ) and (T 41  and T 42 ) instead of single transistors (T 1  and T 2 ) is that the power dissipated in each transistor is reduced and the collector-emitter tension of each transistor is reduced. 
     Preferably, transistors T 1 , T 21  and T 3  are npn-transistors of the same type. They have a very small collector-base capacitance (e.g. C c  =2 pF) and a limit frequency of 2 GHz. The emitter current gain α&#39; (i.e. h FE ) is about 50. Preferably, transistors T 41  and T 42  are pnp-transistors that also have a small collector-base capacitance substantially equal to that of transistors T 21  and T 22 . 
     Preferably, the following values are used in the embodiment shown in FIG. 2. The voltage V 1  is on the order of -5 V while the voltage V 3  is about 35 V. The resistance of resistors R 11 , R 12 , R 5  and R 6  is about 1kΩ and the resistance of R 2  is about 100Ω. If input voltage V i  varies in a range of 0.1 to 1.1 V, output voltage V o  will vary in a range of approximately 5 to 25 V. Preferably, current I tail  is about 80 mA, output capacitance C is about 4 pF and capacitance C 2  is approximately 50 pF. 
     A different embodiment of the present invention is shown in FIG. 3. This embodiment is different from the previously described embodiment in that the collector of transistor T 1  is connected to another current source 22 formed by a pnp-transistor T 5  and an emitter resistor R 6  connected to positive voltage terminal V 3 . The collector of transistor T 5  is directly connected to the base of this transistor and is also connected to ground via a resistor R 7  which has a comparatively high resistance. Alternatively, resistor R 7  can even be omitted. Current source 18 is formed by a single transistor T 6 , the base of which is directly coupled to the base of transistor T 5 . 
     If transistor T 1  opens, the base voltage of transistor T 5  drops so that the current I 1  delivered by current source 22 increases. As current sources 18 and 22 are interlocked with each other due to the common potential of the bases of transistors T 6  and T 5 , the increase in current I 1  is reflected by a similar increase in current I 2 . If transistor T 1  is fully open and transistor T 2  is fully closed, I 2  becomes equal to I tail . Consequently, the slew rate of this embodiment is twice as high as in the embodiments of FIGS. 1 and 2. 
     In the modified amplifier shown in FIG. 4, single transistor T 2  is again replaced by a series of transistors. Current source 22 includes a transistor T 7  interposed between the collector of transistor T 5  and the connecting point of resistor R 7 . The base of transistor T 7  is connected to a constant voltage terminal V 4 . Current source 18 comprises transistor T 6  as described in conjunction with FIG. 3 and transistors T 41  and T 42  as described in connection with FIG. 2. The only difference is that the base of transistor T 42  is connected to a positive voltage terminal V 5  rather than V 4 . Voltage V 5  is smaller than V 3  but larger than V 4 . 
     FIG. 5 shows another modification of the amplifier shown in FIG. 3. Additional transistors T 8  and T 9  are connected in series between transistors T 2  and T 6 . Another transistor T 10  is connected between transistors T 1  and T 5 . The bases of transistors T 8  and T 10  are connected to constant voltage terminal V 4 , and the base of the transistor T 9  is connected to constant voltage terminal V 5 . A capacitor C 1  is connected in parallel with resistor R 1  and resistor R 7  is removed. 
     In the amplifier shown in FIG. 5, preferably, voltage V 1  has a value of about -5 V, while voltage V 3  has a value of about 42 V. The voltages of V 4  and V 5  are selected in such a manner that transistors T 8 , T 9  and T 10  are not saturated. For example, preferably, V 4  is set to 4 V, and V 5  is set to 38 V. As a result, the voltage drop across transistors T 1  and T 2 , and across transistors T 5  and T 6  will be comparatively small. 
     In general, the collector-base capacitance of a transistor is dependent on the collector-base voltage V CB . The amplifier shown in FIG. 5 has the advantage that the collector-base capacitance C c  of transistors T 1 , T 2  and T 6  is almost constant, so that the influence of changes of the input and output voltages on the collector-base capacitance and hence on the frequency curve of the amplifier is eliminated. Specifically, when output voltage V o  changes, the collector-base capacitance C c  of transistor T 2  and, consequently, the input capacitance C in  of this transistor is almost constant. The sum of the collector-base capacitance C c  of transistors T 8  and T 9  is constant as well. Thus, the frequency curve of the amplifier is fixed by the constant values of R 1 , C 1 , R 2 , C 2 , and C in . 
     Capacitor C 1  is provided to make the proper selection of capacitor C 2  less critical. The value of the capacitance of C 1  should be chosen as low as practically possible. A straight frequency curve is obtained if: 
     
         C.sub.2 +C.sub.in ≅C.sub.1 ·R.sub.1 /R.sub.2 (6) 
    
     The total output capacitance C tot  is given by the following equation: ##EQU2## In a preferred embodiment, C has a value of 4 pF, C c  has a value of 1 to 2 pF, and C 1  is set to 1 pF, while C 2  is set to about 6 to 12 pF. This results in C tot  having a value of about 7 to 9 pF. Transistors T 9  and T 10  prevent large changes of the collector-base voltages of transistors T 6  and T 1 , respectively, so that the collector-base capacitances C c  of transistors T 6  and T 1  are also substantially constant. Furthermore, transistors T 8 , T 9  and T 10  dissipate the largest part of the power, so that transistors T 1 , T 2 , T 5 , and T 6  have very low power dissipations, typically smaller than 1 watt. This has the advantage that the temperature offset of these transistors is reduced. 
     While presently preferred embodiments of practicing the invention have been shown and described with particularity in connection with the accompanying drawings, the invention is not limited to the examples shown and described herein. It will occur to a person skilled in the art that the examples shown and described herein may be modified in various ways without departing from the spirit of the present invention. Such modifications are considered to be within the scope of the following claims.