Abstract:
A fabrication method for a metal interconnect having an inner air spacer, applicable to multilevel interconnects technologies, is disclosed. The inner air spacer is formed adjacent to a metal layer to provide a lower dielectric constant in a metal interconnect structure. The inner air spacer is formed by initially forming a dielectric spacer on a sidewall of a second dielectric layer, which sidewall defines a trench opening. The trench opening is then filled with the metal layer. The dielectric spacer is removed to form an air gap between the metal layer and the second dielectric layer. The air gap is sealed off with a portion of a third dielectric layer to form the inner air spacer adjacent to a sidewall of the metal layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 89102690, filed Feb. 17, 2000. 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method for a metal interconnect having an inner air spacer, applicable to multilevel interconnect technologies. 
     2. Description of Related Art 
     In order to build an integrated circuit, it is necessary to fabricate many active devices on a single substrate. Initially, each of the devices must be electrically isolated from the others, and specific devices must subsequently be interconnected in fabrication sequence so as to implement the desired circuit function, such as processing data in a microprocessor. 
     The data processing capability of the microprocessor has been extended to respond to more powerful and sophisticated program software, while such extension inevitably requires an increase in the operation speed of a metal oxide semiconductor (MOS) device. The operation speed of the MOS device is increased by creating an environment having a low dielectric constant between adjacent metal lines in a multilevel interconnect structure, while such environment is essential for reducing a cross-talk error and a capacitance between the metal lines. Since air was known to have a very low dielectric constant (about 1), an optimal dielectric constant for reduction of cross-talk and adverse capacitive coupling in polysilicon and metal interconnect, an air gap structure formed between the metal lines has been adopted in most interconnect process. As a result, the circuit speed is improved and logical cross-talk errors are avoided. FIGS. 1A and 1B are schematic diagrams illustrating a conventional method of fabricating the air gap structure. 
     Referring to FIG. 1A, a dielectric layer  100  is provided above a device layer (not shown), wherein the dielectric layer  100  has metal plugs  102  formed therein. Metal lines  104  are formed on the dielectric layer  100  to cover the metal plugs  102 . As a result, the metal lines  104  are not in direct contact with the metal layer (not shown) below the dielectric layer  100 , except through the metal plugs  102  in order to prevent an electrical short. 
     Referring to FIG. 1B, an inter-metal dielectric (IMD) layer  106  is formed to cover the metal lines  104  and the dielectric layer  100  by a method, such as plasma enhanced chemical vapor deposition (PECVD). The IMD layer is usually made of material, such as silicon dioxide, due to its low dielectric constant (about 3.9). According to the method taught by such prior art, one skilled in the art would expect to form a void or air gap  108  between two adjacent metal lines  104 , as shown in FIG.  1 B. However, the air gap  108  formed as such, does not effectively reduce the dielectric constant between the metal lines  104 . Moreover, the air gap  108  can only be formed between metal lines  104  that are in a denser distribution. Therefore, other materials, such as hydrogen silsesquioxane (HSQ) which provides a lower dielectric constant (about 2.9-3.0) and offers a better topographical planarity is needed to reduce the dielectric constant between the metal lines. 
     However, when HSQ is applied to interconnect technology, particularly for gap filling, it was found that its dielectric constant became undesirably high as a result of subsequent processing. For example, after the deposition of the silicon oxide layer by PECVD, the dielectric constant of the deposited HSQ layer undesirably increased from about 2.9 to about 3.6. This rise in dielectric constant is believed to be a result of the oxidation of the top surface of the HSQ due to exposure to an oxygen-containing ambient at an elevated temperature. The undesirable increase in the dielectric constant of the HSQ layer adversely impacts the intrametal capacitance and, therefore circuit speed. 
     SUMMARY OF THE INVENTION 
     The invention provides a metal interconnect structure having an inner air spacer between metal interconnects, applicable to multilevel interconnect technologies, and a fabrication method thereof. 
     As embodied and broadly described herein, the invention provides an inner air spacers, which is formed adjacent to sidewall of a metal layer in a dual damascene structure. The inner air spacer is formed as an air recess adjacent to the metal layer and are delineated by a metal layer, a second dielectric layer, and a third dielectric layer on the first dielectric layer. 
     According to one aspect of the present invention, a fabrication method for a metal interconnect structure having an inner air spacer between metal interconnects is provided. A first dielectric layer is formed on a MOS device layer, followed by forming an anti-reflection coating (ARC) layer on the first dielectric layer. The first dielectric layer and the ARC layer are patterned to form a contact opening, which contact opening is filled with a metal plug. A second dielectric layer is formed on the metal plug and the ARC layer. The second dielectric layer is then patterned to form a trench opening before forming dielectric spacers on sidewalls of the trench opening. A metal layer is formed to fill the trench opening, and the metal layer outside the trench opening is removed by chemical mechanical polishing (CMP). The second dielectric layer and the dielectric spacer are removed to expose the metal layer with curve-in edges before forming a third dielectric layer on the metal layer. As a result, the inner air spacers are formed as voids between the curve-in edges of the metal layer and the third dielectric layer. 
     Since the inner air spacer is formed closely adjacent to the metal layer, the dielectric constant between the metal interconnects is significantly reduced. The inner air spacer formed as above is also compatible with other dielectric materials to achieve the objective of reducing the dielectric constant. Furthermore, the inner air spacers can be formed on the sidewalls of the metal layers that are located wider apart. Thus, this ensures a uniform reduction of the dielectric constant between the metal interconnects and improves the circuit speed. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIGS. 1A and 1B are schematic, cross-sectional diagrams illustrating a conventional method of fabricating a metal interconnect having an air gap structure; 
     FIGS. 2A through 2D are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect having an inner air spacer according to the first embodiment of this invention; and 
     FIGS. 3A through 3D are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect having an inner air spacer according to the second embodiment of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Description of the present invention is made in two embodiments showing different modes of fabricating a metal interconnect structure having inner air spacers. FIG. 2A through 2D, are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect structure having an inner air spacer according to the first embodiment of this invention. Moreover, FIGS. 3A through 3D are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect structure having an inner air spacer according to the second embodiment of this invention. 
     First Embodiment 
     Referring to FIG. 2A, a first dielectric layer  200  is formed on a MOS device layer (not shown). An anti-reflection coating (ARC) layer  202  is then formed on the first dielectric layer  200 . The first dielectric layer  200  is made of material, such as silicon dioxide, while the ARC layer  202  may be made of any anti-reflective materials, but is preferably made of silicon oxy-nitride. The ARC layer  202  in this case prevents etching damage done to the first dielectric layer  200  and improves the photolithographic ability in a photolithographic process. The ARC layer  202  and the first dielectric layer  200  are patterned to form a contact opening (not shown), and the contact opening is then filled with a first metal layer  204  to form a metal plug  204   a.  The metal plug  204   a  may include any conductive material, but it preferably includes a tungsten plug. 
     Referring to FIG. 2B, a second dielectric layer  206  is formed on the metal plug  204   a  and the ARC layer  202 . By performing a photolithographic and etching process, a part of the second dielectric layer  206  is removed to form a trench opening  208 , wherein the trench opening  208  exposes the metal plug  204   a  and a part of the ARC layer  202 . A dielectric spacer  206   a  is formed on a sidewall of the trench opening  208 . The method for forming the dielectric spacer  206   a  includes forming an insulating layer in the trench opening  208 , followed by performing an etching back process, so that a part of the insulating layer remains to form the dielectric spacer  206   a.  Although the dielectric spacer  206   a  can be made of materials different from the material for making the second dielectric layer  206 , same material has been used for making both the dielectric spacer  206   a  and the second dielectric layer  206  in this embodiment. 
     Referring to FIG. 2C, the trench opening  208  is filled with a second metal layer  210 . The second metal layer  210  is formed on the second dielectric layer  206  to fill the trench opening  208 . The second metal layer  210  outside the trench opening  208  is removed until the second dielectric layer  210  is exposed. The method for removing the second metal layer  210  includes an etching back process, such as chemical mechanical polishing (CMP). The second metal layer  210  and the metal plug  204   a  together form a dual damascene structure having a T-shape cross-section. Since the dielectric spacer  206   a  is formed on the sidewall of the trench opening  208 , the second metal layer  210  has curve-in sidewalls at both ends, as shown in FIG.  2 C. 
     Referring to FIG. 2D, the second dielectric layer  206  and the dielectric spacer  206   a  are removed to expose the second metal layer  210  and the ARC layer  202 . The method for removing the second dielectric layer  206  and the dielectric spacer  206   a  preferably includes dry etching using a plasma. A third dielectric layer  212  is then formed on the second metal layer  210 . It is emphasized in this embodiment that, the space occupied previously by the dielectric spacer  206   a  is not filled with the third dielectric layer  212  due to the curve-in sidewall profile of the second metal layer  210 . As a result, the space, which is delineated by the second metal layer  210  and the third dielectric layer  212 , forms the inner air spacer  214  on the ARC layer, as shown in FIG.  2 D. 
     Second Embodiment 
     Referring to FIG. 3A, a first dielectric layer  300  is formed on a MOS device layer (not shown). An ARC layer  302  is then formed on the first dielectric layer  300 . The first dielectric layer  300  is made of material, such as silicon dioxide, while the ARC layer  302  may be made of any anti-reflective materials, but is preferably made of silicon oxy-nitride. The ARC layer  302  in this case prevents etching damage done to the first dielectric layer  300  and improves the photolithographic ability in the photolithographic process. The ARC layer  302  and the first dielectric layer  300  are patterned during the photolithographic and etching process to form a contact opening (not shown), and the contact opening is then filled with a first metal layer  304  to form a metal plug  304   a.  The metal plug  304   a  may include any conductive material, but is preferably made of tungsten. A second dielectric layer  306  is formed on the metal plug  304   a  and the ARC layer  302 . A part of the second dielectric layer  306  is removed to form a trench opening  308 , wherein the trench opening  308  exposes the metal plug  304   a  and a part of the ARC layer  302 . 
     Referring to FIG. 3B, a dielectric spacer  310  is formed on a sidewall of the trench opening  308 . The method for forming the dielectric spacer  310  includes forming an insulating layer in the trench opening  308 , followed by performing an etching back process, so that a part of the insulating layer remains on the sidewall of the second dielectric layer  306  to form the dielectric spacer  310 . Although the dielectric spacer  310  can be made of the same material for making the second dielectric layer  306 , the dielectric spacer  310  is made of the material different from the material for making the second dielectric layer  306  in this embodiment. For example, the dielectric spacer  310  is preferably made of silicon nitride. However, the material for making the dielectric spacer  310  is not limited to silicon nitride, any insulating materials can be used to achieve the same result of the present invention. With the dielectric spacer  310  serving as a mask, the exposed part of the ARC layer is removed simultaneously during the formation of the dielectric spacer  310 . Therefore, a part of the first dielectric layer  300  is exposed in the trench opening  308 . 
     Referring to FIG. 3C, the trench opening  308  is filled with a second metal layer  312 . The second metal layer  312  is formed on the second dielectric layer  306  to cover the metal plug  304   a  and the first dielectric layer  300 . The second metal layer  312  outside the trench opening  308  is removed until the second dielectric layer  306  is exposed. The method for removing the second metal layer  312  includes an etching back process, such as CMP. The second metal layer  312  and the metal plug  304   a  together form a dual damascene structure having a T-shape cross-section. Since the dielectric spacer  306   a  is formed on the sidewall of the trench opening  308 , the second metal layer  312  has curve-in sidewalls at both ends, as shown in FIG.  3 C. The dielectric spacer  310  and a part of the ARC layer  302  underneath the dielectric spacer  310  are removed until the first dielectric layer  300  is exposed. This forms an air gap  314  between the second metal layer  312  and the second dielectric layer  306 . Although the method for removing the dielectric spacer  310  and the ARC layer  302  preferably includes dry etching by a plasma, one skilled in the art should be able to expect other etching processes to remove the dielectric spacer  310  according to the present invention. 
     Referring to FIG. 3D, the air gap  314  is sealed off by forming a third dielectric layer  316  on the second metal layer  310  and the second dielectric layer  306 . The air gap  314 , after being sealed off, forms an inner air spacer  314   a  on the first dielectric layer  300 , wherein the inner air spacer  314   a  is delineated by the second metal layer  310 , the second dielectric layer  306 , and the third dielectric layer  316 . As shown in FIG. 3D, the inner air spacer  314   a  is formed adjacent to a curved sidewall of the second metal layer  310 . 
     Summarizing from the two embodiments above, it is understood that the inner air spacer is formed closely adjacent to the metal layer, so that the dielectric constant between the metal interconnects is significantly reduced. The inner air spacer formed as above is also compatible with other dielectric materials in order to reduce the dielectric constant, while such fabrication method does not create too much complexity to the current process. Furthermore, the inner air spacers can be formed on the sidewalls of the metal interconnects that are located wider apart. Thus, this ensures a uniform reduction of the dielectric constant between the metal interconnects and improves the circuit speed as a consequence. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.