Abstract:
A feed-forward path is combined with a feed-back path to produce an output signal representation of an input signal frequency. The feed-forward path adjusts the output signal representation in response to a change in the input signal frequency, and does so in a response time that is independent of the feed-back path. Input frequencies can be represented as voltages, and first and second input frequency ranges which differ from one another can both be represented in the same range of voltages.

Description:
TECHNICAL FIELD OF THE INVENTION 
   The invention relates generally to the use of periodic signaling and, more particularly, to producing an output signal that is representative of the frequency of an input periodic signal. 
   BACKGROUND OF THE INVENTION 
   There are myriad applications which require the capability to obtain information about the frequency of a periodic signal. Conventional frequency-to-current conversion circuits produce an output current that represents the frequency of an input periodic signal, and conventional frequency-to-voltage conversion circuits produce an output voltage that represents the frequency of an input periodic signal. These, conventional approaches typically use a feed-back loop to synchronize the output signal to the frequency of the periodic input signal. The feed-back loop requires a certain amount of locking time to lock the output signal representation to the frequency of the input signal. This locking time can present difficulties in some situations, for example, when the frequency of the input signal abruptly changes by a relatively large amount. 
   It is desirable in view of the foregoing to provide for an output signal representation of an input signal frequency while also avoiding the locking time associated with the operation of conventional feed-back control loops. 
   SUMMARY OF THE INVENTION 
   Exemplary embodiments of the invention combine a feed-forward path with a feed-back path to produce an output signal representation of an input signal frequency. The feed-forward path adjusts the output signal representation in response to a change in the input signal frequency, and does so in a response time that is independent of the feed-back path. In some embodiments, input frequencies are represented as voltages, and first and second input frequency ranges which differ from one another can both be represented in the same range of voltages. 
   Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with a controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
       FIG. 1  diagrammatically illustrates exemplary embodiments of a frequency-to-current converter according to the invention; 
       FIG. 2  diagrammatically illustrates a portion of  FIG. 1  in more detail according to exemplary embodiments of the invention; 
       FIG. 3  is a timing diagram which illustrates selected signals from FIGS.  1 , 2  and  4 ; 
       FIG. 4  diagrammatically illustrates a portion of  FIG. 1  in more detail according to exemplary embodiments of the invention; and 
       FIG. 5  diagrammatically illustrates a portion of  FIG. 4  in more detail according to exemplary embodiments of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1 through 5 , discussed herein, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. 
     FIG. 1  diagrammatically illustrates a frequency-to-current conversion apparatus according to exemplary embodiments of the invention. The apparatus of  FIG. 1  includes a frequency-to-voltage converter  11  which produces at  12  an output voltage that represents the frequency of an input signal received at  10 . In response to the voltage at  12 , a voltage-to-current converter  13  produces at  14  an output current Iout that represents the frequency of the input signal received at  10 . A feed-back control path (or loop) at  15  provides feed-back control signaling between the output  14  of the voltage-to-current converter  13  and another node  16  of the voltage-to-current converter  13 . The feed-back control path  15  provides adjustment capability, but the combination of the frequency-to-voltage converter  11  and the voltage-to-current converter  13  represents a feed-forward path which permits the output  14  to adjust immediately to frequency changes at the input  10 . As described in detail herein below, this feed-forward adjustment can be accomplished without incurring any time delay associated with operation of the feed-back control path  15 . 
     FIG. 2  illustrates the frequency-to-voltage converter  11  of  FIG. 1  in more detail according to exemplary embodiments of the invention. The frequency-to-voltage converter  11  of  FIG. 2  includes a first frequency-to-voltage conversion circuit including a current source I 1  coupled in series with a parallel combination of a switch S 1  and a capacitor C 1 . Similarly, a second frequency-to-voltage conversion circuit includes a current source I 2  coupled in series with a parallel combination of a switch S 2  and a capacitor C 2 . The switches S 1  and S 2  are controlled by a delayed version  25  of the input frequency Fext, which delayed version  25  is produced by a suitable delay circuit  23 . The input frequency Fext also controls a switch S 3  that is connected between a selector  26  and a sample/hold capacitor C 3  (C 3 &lt;C 1 , C 3 &lt;C 2 ) at the output  12  of the frequency-to-voltage converter  11 . The selector  26  has a first input connected to a node  21  of the first frequency-to-voltage conversion circuit, and has a second input connected to a node  22  of the second frequency-to-voltage conversion circuit. Under control of the output  20  of a comparator  24 , the selector  26  connects one of the nodes  21  and  22  to the switch S 3 . The comparator  24  compares the voltage at the node  21  to a reference voltage, in this example, a 2 volt reference voltage. 
   If the capacitor C 2  is selected to have a larger value than the capacitor C 1 , while the currents I 1  and I 2  are selected to be the same, then the operation of switches S 1  and S 2  at the input frequency Fext will result in voltage waveforms at nodes  21  and  22  such as illustrated at  21  and  22  in  FIG. 3 . The ramp slope in the waveform at  21  is set by the current I 1  and the capacitor C 1 , and the ramp slope in the waveform at  22  is set by the current I 2  and the capacitor C 2 . For the example of  FIG. 2 , where C 2  is 10×C 1 , the slope of the ramp at  21  is 10× the slope of the ramp at  22 . The lower slope value of the ramp at  22  permits lower frequencies to be represented within the same voltage headroom as the higher frequencies that are represented at  21 , without running into the upper limit of the available voltage headroom and clipping the top of the waveform (see  21  in  FIG. 3 ). When the input frequency Fext changes from the higher frequency indicated at  31  to the lower frequency indicated at  32 , the waveform at  21  clips off at the available voltage headroom (for example 3 volts), while the waveform at  22  can easily represent the lower frequency  32  as a waveform with a 0.4 volt peak. 
   Accordingly, and referring also  FIG. 2 , the comparator  24  determines when the voltage at node  21  goes above the 2 volt reference level, and changes its output voltage level  20  to indicate that the node  21  has exceeded the 2 volt reference level. This causes the selector  26  of  FIG. 2  to switch such that the sampling switch S 3  is no longer connected to node  21 , but is now connected to node  22 . This causes the sampled voltage across capacitor C 3  at  12  to change from the 1.8 volt level associated with the peak voltage on node  21  at the higher frequency  31  to the 0.4 volt level associated with the peak voltage on node  22  at the lower frequency  32 . In some embodiments, the ramp slope of the waveform at  21  in  FIG. 3  is 2M V/s, and the ramp slope of the waveform at  22  in  FIG. 3  is 200 k V/s. These slopes have a 10:1 ratio that corresponds to the aforementioned capacitance ratio where C 2 =10×C 1 , and with I 1 =I 2 . Because the ramp slope ratio of the waveforms at  21  and  22  is known, this factor can be compensated for by suitable adjustments in the voltage-to-current converter  13  (see also  FIG. 1 ) as described hereinbelow. 
     FIG. 4  diagrammatically illustrates the voltage-to-current converter  13  and the feed-back control path  15  of  FIG. 1  in more detail according to exemplary embodiments of the invention. As shown in  FIG. 4 , a buffer and a resistor are used to convert the voltage  12  provided at the output of the frequency-to-voltage converter I 1  into a current I 3 . In particular, the current I 3  is simply the voltage at  12  divided by the resistance of the resistor R. A p-type current mirror  42 , an n-type mirror current mirror  43 , and current divider  44  together constitute a current modifier which produces a current I 4  that is inversely proportional to the current I 3 . Because the peak voltages of the waveforms  21  and  22  ( FIGS. 2 and 3 ) are inversely proportional to the input frequency Fext, this also means that the current I 3  is inversely proportional to Fext. Accordingly, the current I 4 , which is inversely proportional to the current I 3 , is directly proportional to Fext. 
   At  45 , the current I 4  is selectively divided as necessary to compensate for the ramp slope ratio of the waveforms  21  and  22  of  FIG. 3 . In the example described above, the C 2 /C 1  ratio is 10/1 and the ramp slope ratio between waveform  21  and waveform  22  of  FIG. 3  is 10/1, so the divider at  45  divides the current I 4  by 10 whenever the output  20  of the comparator  24  indicates that the capacitor C 2  (and corresponding waveform  22  of  FIG. 3 ) is being used to represent the input frequency Fext. This selective division, by the ramp slope ratio of 10 in this example, insures that the output current Iout at  14  compensates for the flatter ramp slope at  22  in  FIG. 3 . 
   As shown in  FIG. 4 , the output current Iout drives a capacitor C 4  which is used in combination with the feed-back path  15  to increase the accuracy of the output current Iout. Note, however, that the output current Iout is produced via the aforementioned feed-forward path which causes Iout to track changes in Fext immediately, without incurring the delay associated with operation of the feed-back path  15 . 
   The feed-back path of  FIG. 5  includes a 10 ns one-shot  47  triggered by Fext. The one-shot  47  is used to enable a charge-pump circuit  46  which monitors the peak voltage on capacitor C 4  for the 10 ns period of the one-shot. During the 10 ns period, if the peak voltage on capacitor C 4  exceeds a reference voltage of 1.2 volts, the charge pump  46  will pump a control voltage at  40  across capacitor C 5 . This control voltage at  40  is input to a transconductor amplifier  48  for comparison with the 1.2 volt reference. The output of the transconductor amplifier  48  is coupled to the node  16  of the frequency-to-current converter  13 . In the example of  FIG. 4 , the node  16  is a current summing node, and the transconductor amplifier  48  either adds to or subtracts from the current going to the p-type mirror  42 . In this fashion, the feed-back path at  15  can adjust I 3  such that Iout, in cooperation with switch S 4  (controlled by a delayed version of Fext produced by a suitable delay circuit  49 ) will maintain the peak voltage across capacitor C 4  at 1.2 volts. 
     FIG. 3  illustrates the voltage and current at  14  in timewise correspondence with the other signals of  FIG. 3 . In response to an abrupt frequency change, the feed-forward path adjusts the voltage at  14  across capacitor C 4  immediately to bring the peak voltage back near 1.2 volts. Thereafter, the feed-back path can operate to adjust for errors so that the peak voltage at  14  is maintained at 1.2 volts. 
   In one embodiment, the period of Fext at  31  is 900 ns, and the period of Fext at  32  is 2 us. 
     FIG. 5  diagrammatically illustrates the current divider  44  of  FIG. 4  in more detail according to exemplary embodiments of the invention. As shown in  FIGS. 4 and 5 , the current divider  44  is coupled at  400  to the n-type current mirror  43 , and produces the modified current I 4  at  401 . With the illustrated arrangement of transistors  51 - 54  and current sources Ia and Ib, operation of the current modifier  42 - 44  of  FIGS. 4 and 5  produces I 4 =(Ia×Ib)/I 3 , such that the current I 4  is inversely proportional to the current I 3  as desired. The current modifier at  42 - 44  of  FIGS. 4 and 5  is merely one example of many well-known suitable techniques for generating a result current (I 4 ) that is inversely proportional to an input current (I 3 ). 
   Referring again to  FIG. 3 , in the example illustrated therein, the relationship between the output current Iout and the input signal frequency Fext is as follows: Iout=Fext×10 −12 . Because the peak value of the voltage at  14  across C 4  is maintained at 1.2 volts, the proportionality of Iout to Fext can be adjusted by changing the value of C 4 . 
   Although the present invention has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.