Abstract:
A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to French Patent Application Serial No. FR0956700, in the name of Chrystelle Lagahe Blanchard, filed Sep. 28, 2009, incorporated herein, in its entirety, by this reference. 
       TECHNICAL FIELD 
       [0002]    The invention relates to the field of the fabrication of substrates for applications in electronics, optics and in opto-electronics. 
       BACKGROUND 
       [0003]    The present invention more particularly relates to a process for bonding and transferring a layer of material onto a substrate, implemented during the fabrication of substrates for the aforementioned applications. 
         [0004]    During a transfer process of this type, two substrates, respectively referred to as the “donor” and “receiver,” are bonded to one another by molecular adhesion. Then, the donor substrate is thinned, for example by grinding or polishing, in such a manner that a part of the donor substrate is transferred onto the receiver substrate. 
         [0005]    Such a process allows multilayer substrates of any given type to be obtained, for example comprising at least two layers of materials, semiconductor or otherwise. 
         [0006]    Such a transfer process also allows a substrate comprising one or more intermediate layers to be obtained, sandwiched between the surface layer removed from the donor substrate and the base layer corresponding to the receiver substrate. It also allows a layer comprising all or part of one or more micro-components from a donor substrate to be transferred to a receiver substrate, as is for example illustrated in the document U.S. Pat. No. 5,234,860. 
         [0007]    One particular example of this type of multilayer substrate consists of one of those known to those skilled in the art by the acronym “SeOI” meaning “Semiconductor On Insulator.” 
         [0008]    It has been observed that the substrates fabricated by these transfer techniques generally exhibit an annular region, referred to as “peripheral ring,” in which the bonding between the layers is non-existent or of poorer quality, owing to the presence of chamfers on the donor and receiver substrates used and commonly available. The presence of these chamfers leads to a low bonding energy around the edges of the assembled substrates, or even of a total lack of adhesion. 
         [0009]    As a result, the mechanical thinning step, conventionally implemented in order to form the transferred layer, tends to cause peripheral partial de-lamination of this layer at the bonding interface. Furthermore, the thermo-mechanical forces applied to the substrate during the thinning step can lead to a flaking phenomenon at the periphery of the transferred layer, such that this transferred layer then exhibits an irregular circumference. 
         [0010]    The existence of this partial de-lamination and of this irregular circumference of the transferred layer creates a risk of particulate contamination for the equipment or for the substrates themselves, bits of the layer indeed being able to break off during later processing. 
         [0011]    This risk is further accentuated in the case where the process of bonding the two donor and receiver substrates is carried out at low temperature. This is the case, for example, when the materials brought into contact are not able to withstand high temperatures (for example “SOQ” for “Silicon On Quartz” or “SOS” for “Silicon On Sapphire” substrates) or when at least one of the assembled substrates contains electronic or opto-electronic components for example. 
         [0012]    According to the document JP 09-017984, a process for fabrication of an SOI substrate is known. 
         [0013]    This document makes reference to a prior art process consisting in:
       bonding by molecular adhesion a donor substrate coated with an insulating layer and a receiver substrate,   performing an annular trimming of the entirety of the donor substrate and of a part of the receiver substrate,   etching the part of the receiver substrate work-damaged by the trimming step,   and then grinding a part of the donor substrate in order to obtain the surface layer of the SOI structure.       
 
         [0018]    However, this process tends to amplify the phenomenon of peripheral partial de-lamination of the transferred layer at the bonding interface. Indeed, in the case of a bonded structure whose consolidation has only been carried out at low temperature, the mechanical stresses introduced during the annular mechanical trimming of the entirety of the donor substrate and of a part of the receiver substrate can lead to localized or extended de-bonding of the bonding interface. The thereto-mechanical stresses on the structure are indeed significant during this step. 
         [0019]    Another trimming process is described in this same document JP 09-017984. It comprises the following steps:
       trimming of only a part of the donor substrate up to around 50 μm before the bonding interface, so as not to damage the receiver substrate,   successive selective etching of the residual annular portion of the donor substrate by means of a TMAH (tetramethylammonium hydroxide) solution, then of the oxide.       
 
         [0022]    This allows etching of the receiver substrate to be avoided. 
         [0023]    However, in certain cases of bonded structures, notably in the case where the donor substrate is a substrate of the SOI type comprising a buried layer of oxide and whose surface layer includes microcomponents (circuits), the selective etching of the silicon of the donor substrate previously partially trimmed will stop at the buried layer of oxide of the donor substrate and at the base of the layer including the circuit; thus, a “loosely bonded and irregular” layer of 5 to 10 μm (thickness of the circuit) not removed will remain at the periphery of the structure. 
       BRIEF SUMMARY 
       [0024]    The aim of the invention is to overcome the aforementioned drawbacks of the state of the art and to provide a process for transfer of a layer onto a receiver substrate which includes a trimming step. This process:
       allows the problems of flaking and of de-lamination of the final substrate and the formation of a transferred layer with irregular circumference to be avoided,   is less complex, faster to implement and less costly than the processes already known from the state of the art.       
 
         [0027]    For this purpose, the invention relates to a process for bonding and transferring a layer of material onto a receiver substrate, used during the fabrication of a substrate intended notably for applications in the fields of electronics, optics or opto-electronics. 
         [0028]    According to the invention, this process comprises the following steps:
       bond by molecular adhesion the said receiver substrate and a donor substrate,   apply heat treatment to the aforementioned stack in order to consolidate the bonding interface,   thin the donor substrate by grinding,   perform an annular trimming of the donor substrate and of a part of the receiver substrate,   after the aforementioned steps, carry out a chemical etching step of the exposed surface of the remaining part of the donor substrate and of the exposed surface of the receiver substrate.       
 
         [0034]    According to other advantageous and non-limiting features of the invention, taken alone or in combination:
       the grinding is carried out before the trimming;   the grinding is carried out after the trimming;   electronics components are formed within and/or on the said donor substrate and/or the said receiver substrate prior to the bonding;   the donor substrate is a bulk substrate;   the chemical etching step is stopped after removal of the area work-damaged during the grinding step;   the chemical etching step is followed by a step for polishing of the exposed face of the layer of material coming from the donor substrate;   the donor substrate is a substrate of the “silicon on insulator” or “SOI” type comprising a silicon base substrate, a buried insulating layer and a surface layer also made of silicon;   the grinding comprises the removal of a part of the base substrate, and the etch step is stopped after removal of the residue from the said base substrate;   a layer of oxide is formed or deposited on the said donor substrate and/or on the said receiver substrate prior to the bonding;   the layer of oxide is planarized in order to smooth out any topology of the component or components present at the surface and to give the surface the characteristics required for the bonding by molecular adhesion;   the grinding is performed up to the point where the thickness of the donor substrate reaches around 50 μm;   the receiver substrate is trimmed to a depth in the range between around 2 and 10 μm starting from its surface;   the donor and receiver substrates are formed from silicon and the etching solution is a solution of tetramethylammonium hydroxide TMAH with a concentration of 25% by weight in water.       
 
         [0048]    Other features and advantages of the invention will become apparent from its description which will now be presented with reference to the appended drawings which show, by way of non-limiting examples, several possible embodiments. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0049]    In these drawings: 
           [0050]      FIGS. 1A to 1F  are schematic views showing the various steps of a first embodiment of the bonding and transfer process according to the invention; 
           [0051]      FIGS. 2A to 2F  are schematic views showing the various steps of a second embodiment of the bonding and transfer process according to the invention; and 
           [0052]      FIGS. 3A to 3E  are schematic views showing the various steps of a third embodiment of the bonding and transfer process according to the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0053]    The process according to the invention is applicable to the bonding of any type of substrate and to the transfer of layers of various natures coming from these substrates. 
         [0054]    The invention is however particularly applicable in the case where the materials used to fabricate all or part of these substrates are not able to withstand high temperatures, notably greater than 450° C. The term “materials used to fabricate all or part of these substrates” is understood to mean one or more of the layers composing it or else an electronic component formed within and/or on at least one of these substrates. 
         [0055]    A first embodiment will now be described in conjunction with  FIG. 1 . 
         [0056]    With reference to  FIG. 1A , a first substrate  1  is shown, referred to as “donor,” of the “semiconductor on insulator” (SeOI) type, which comprises a layer of insulator  11  sandwiched (buried) between a surface layer  12  and a base substrate  13 , this layer  12  and this base  13  being made of semiconductor material. 
         [0057]    Preferably, the insulating layer  11  is a layer of oxide. 
         [0058]    One particular application of this process consists in using a donor substrate of the SOI type in which the layers  12  and  13  are made of silicon and the layer  11  of silicon dioxide SiO 2 . 
         [0059]    A second substrate, referred to as “receiver,” reference  2 , can also be seen in  FIG. 1A . 
         [0060]      FIGS. 1A to 1F  show the case where electronic components are present in some of the layers of the donor and receiver substrates, however the process is also applicable to substrates which do not comprise any of these. 
         [0061]    When they are present, these electronic components may have been formed within and/or on the said surface layer  12  and/or within and/or on the said receiver substrate  2 . 
         [0062]    These electronic components are for example circuits, typically circuits of the CMOS type, an acronym which stands for “Complementary Metal Oxide Semiconductor.” 
         [0063]    The components formed within the surface layer  12  carry the reference  121  and those formed on top the reference  122 , whereas the components formed within the receiver substrate  2  carry the reference  21  and those formed on top the reference  22 . 
         [0064]    The components  21  and/or  22  of the base substrate  2  may have been formed directly within or on this substrate or may have been the result of a previous transfer of layers, as is the case in the stacking of circuits in three dimensions, known to those skilled in the art by the term “3D stack.” 
         [0065]    The donor substrate  1  presents two opposing faces, namely a face  14 , referred to as “front,” and an opposing face  15  referred to as “back.” In a similar manner, the receiver substrate  2  comprises a front face  24  and a back face  25 . 
         [0066]    As can be seen in  FIG. 1B , a layer of oxide is formed or deposited on the front face  14  of the donor substrate  1  and/or on the front face  24  of the receiver substrate  2 . These layers of oxide are respectively referenced  3  and  4 . 
         [0067]    These layers of oxide  3 ,  4  are formed by thermal oxidation and/or deposition by chemical vapor deposition (CVD) techniques. 
         [0068]    In the case of the base substrate  2 , it will be noted that the layer of oxide  4  could completely encapsulate it, although this has not been shown in the figures. 
         [0069]    Advantageously, in the case where electronic components are present, the layers of oxide  3  and/or  4  are planarized, so as to smooth out the topology associated with the presence of the components and to give the surface the characteristics required later for bonding by molecular adhesion. 
         [0070]      FIG. 1C  shows the step for bonding the two substrates  1  and  2 , carried out in such a manner that the layer or layers of oxide  3 ,  4  are sandwiched between these two substrates. 
         [0071]    After bonding, heat treatment is applied so as to consolidate the bonding interface referenced  5 . 
         [0072]    In the case illustrated in  FIGS. 1A to 1F , where the substrates  1  and  2  comprise electronic components, the temperature of this heat treatment is relatively modest, preferably in the range between around 300° C. and 400° C., in order to avoid the degradation of these components. 
         [0073]    According to a first variant embodiment of the process of the invention, shown in  FIGS. 1D to 1F , the following step consists in carrying out a thinning by grinding of the base substrate  13 , in such a manner as to conserve only a thin layer  130  whose thickness is preferably in the range between 10 and 50 micrometers. 
         [0074]    This is followed by a trimming step (see  FIG. 1E ) which consists in removing the peripheral annular edge of the donor substrate  1 , layers of oxide  3 ,  4  which may be present and of a part of the receiver substrate  2 . 
         [0075]    The depth of this trimming into the receiver substrate  2  is preferably in the range between around 2 and 10 micrometers starting from its front face  24 , in other words its face oriented towards the bonding interface  5 . 
         [0076]    The object of this step is to obtain a clean edge, without flakes, at the periphery of the transferred layer. 
         [0077]    For this purpose, the receiver substrate  2  is fixed onto a rotating support and a grinding wheel, which is also rotating, is brought into contact with the periphery of the stack of aforementioned layers. This trimming step can thus be performed by means of conventional trimming equipment, known to those skilled in the art as “edge-grinding” (or alternatively “edge-trimming”) equipment. 
         [0078]    The trimming step may potentially comprise one or more steps with different depths and widths. 
         [0079]    Finally, the last step of the process, shown in  FIG. 1F , consists in carrying out a selective etching of the residual layer of semiconductor material  130  present on the top of the stack of layers. 
         [0080]    This etching may be carried out by means of various etching solutions known to those skilled in the art. 
         [0081]    However, in the particular case where the layers to be etched are made of silicon, this etching is carried out for example by means of a solution of the NaOH or KOH type, or preferably by means of a chemical solution of TMAH (which denotes a solution of tetramethylammonium hydroxide). 
         [0082]    Preferably, a TMAH solution is used whose concentration is 25% by weight in water, at a temperature typically in the range between 70° C. and 90° C. The TMAH solution is a silicon etchant solution which exhibits a high selectivity to oxide. The insulating layer  11  is then used as an etch-stop layer. 
         [0083]    By way of example, an etch using a solution of TMAH typically takes 1 minute to 2 hours considering that the etch rate of the semiconducting layer  130  is around 25 to 30 micrometers/hour. 
         [0084]    Another objective of this etch step is to clean and smooth the trimmed edge. Indeed, the mechanical trimming causes an increase in the roughness of the surface processed and generates a large number of particles. The etch process allows the surface to be smoothed and the trimmed edge to be cleaned, so as to avoid any contamination during the technological steps implemented later. 
         [0085]    Furthermore, the process according to the invention avoids having to resort to hydrofluoric acid HF used in certain processes of the prior art, and which increases the de-lamination of the layers and etches the oxides. 
         [0086]    At the end of the step shown in  FIG. 1F , a final substrate referenced  6  is obtained, which comprises the receiver substrate  2  onto which the surface layer  12  has been transferred. The insulating layer  11  is conserved or not depending on the applications targeted. 
         [0087]      FIGS. 2A to 2F  illustrate one variant embodiment of the process which has been described in conjunction with  FIGS. 1A to 1F . 
         [0088]      FIGS. 2A to 2C  are identical to  FIGS. 1A to 1C  and will not be described again. Identical elements carry the same numerical references. 
         [0089]    This process differs from the preceding one in that the trimming is carried out before the step for grinding the base substrate  13 . This trimming is illustrated in  FIG. 2D . 
         [0090]    Subsequently, the grinding of the trimmed base substrate  13  is performed so as to obtain the layer  130 , with a thickness in the range between 10 and 50 micrometers, as previously described. 
         [0091]    The step shown in  FIG. 2F  corresponds to the etch process, carried out according to the same procedures and with the same results as that described for the first embodiment of the invention. 
         [0092]    In these two embodiments of the invention, it will be noted that the thinning step ( FIG. 1D  or  2 E) is always carried out retaining a minimum thickness of the donor substrate  13 . The advantage of this sequencing is that the final active surface of the layer transferred onto the receiver substrate  2  is never exposed during the trimming step and is therefore protected from any potential particulate contamination or scratching. 
         [0093]    A third variant embodiment will now be described in conjunction with  FIGS. 3A to 3E . It differs from the two preceding ones in that the donor  1  and receiver  2  substrates are bulk substrates. The donor substrate  1  is also coated with a layer of oxide  3 . The elements in common with the preceding embodiments carry the same references. 
         [0094]    After the bonding step shown in  FIG. 3B , a heat treatment of the aforementioned stack is carried out in order to consolidate the bonding interface  5 . This treatment can be conducted up to a temperature of 1100° C. for a duration of 2 hours since the substrates  1  and  2  do not comprise any electronic components, and of course as long as the nature of their constituent materials allows it. 
         [0095]    The steps for thinning by grinding ( FIG. 3C ), trimming ( FIG. 3D ) and etching ( FIG. 3E ) are then carried out under the conditions previously described. The thinned layer of the donor substrate  1  carries the reference  10 . 
         [0096]    The etch is stopped in this case at the end of the etching time needed to remove the area work-damaged during the grinding process. The layer thinned by grinding, cleaned by the etch and with its work-damaged area removed carries the reference  10 ′. Once again, it will be noted that, thanks to this sequencing of the process of the invention, the surface of this active layer  10 ′ was never exposed during the trimming process and has remained protected. 
         [0097]    Hereinafter, two exemplary embodiments of the invention are presented. 
       EXAMPLES 
     Example 1 
     Fabrication of an SOI Comprising Electronic Components 
       [0098]    A silicon receiver substrate has been oxidized and a layer of oxide has been deposited at low temperature (between 200° C. and 500° C.) onto a donor substrate of the SOI type comprising electronic components. 
         [0099]    The donor substrate has been planarized until a surface condition is obtained that is compatible with direct bonding by molecular adhesion, in other words until a roughness of less than 3 Å RMS (3 angströms) has been obtained for a scan width of 2 μm by 2 μm. 
         [0100]    After cleaning and surface activation, the two substrates have been assembled. The bonded structure has then been subjected to a heat treatment at 350° C. for 1 hour, in order to consolidate the bonding interface. 
         [0101]    The back face of the donor substrate has then been thinned by grinding down to around 35 μm. The trimming step has subsequently been applied to around 3 mm from the edge of the substrate. 
         [0102]    This structure has then been immersed in a solution of TMAH at 80° C., for 1 hour 30 minutes, which allows the selective etching of the silicon with respect to the oxide until the entire thickness of residual silicon (from the mechanical support back part of the SOI donor substrate) has been removed. 
       Example 2 
     Fabrication of an SOI Using a Bulk Donor Substrate 
       [0103]    After having carried out the oxidation of a silicon receiver substrate, it is bonded with a donor substrate also made of silicon. 
         [0104]    The assembly has been subjected to an annealing step for stabilization of the bonding, using a heat treatment at 1100° C. for 2 hours under an oxygen atmosphere. 
         [0105]    The thinning of the donor substrate has subsequently been carried out then the trimming of the stack over a 0.5 to 3 mm width, and 2 to 10 micrometers depth into the support. 
         [0106]    Following this, an etch has been performed by means of TMAH (concentration 25% by weight in water, temperature 60° C.), in such a manner as to remove the area work-damaged by the thinning step, in other words the exposed surface of the donor substrate remnant, and to process the faces exposed by the receiver substrate trimming step. This etch step results in the removal of around 0.5 to 2 micrometers of the thickness. 
         [0107]    Lastly, a final polishing of the SOI structure has been carried out, in order to obtain a surface layer of silicon with a thickness in the range between 3 and 100 micrometers.