Abstract:
A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The techniques described herein relate generally to comparators and in particular to a comparator with offset compensation and improved dynamic range. 
         [0003]    2. Discussion of the Related Art 
         [0004]    Comparators are used in many applications for comparing two input signals. For example, comparators are important building blocks of analog-to-digital converters (ADCs). An important parameter of a comparator is its resolution, which is the minimum voltage difference that can be detected. The resolution of a comparator can directly limit the accuracy of an ADC. 
         [0005]    The mismatch of transistors within a comparator can create an offset voltage that limits the resolution of the comparator. To address this problem, comparators have been designed that compensate for the offset voltage. For example,  FIG. 1  shows a comparator  100 , as described in U.S. Published Patent Application 2010/0237907, that compensates for the offset voltage of its components, among other functions. 
         [0006]    Comparator  100  is formed of a first stage  10  and a second stage  20 . The first stage  10  is a pre-amplifier stage that can reduce the output switching noise and amplify the input signal to increase the resolution of the comparator. The first stage  10  substantially forms a voltage/current converter which, during an autozeroing step, stores an offset-compensated bias condition so that the offset voltage can be compensated. 
       SUMMARY 
       [0007]    Some embodiments relate to a comparator having a first stage configured to receive first and second input signals and to produce first and second output signals; and a second stage coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage is configured to receive a supply voltage. The second stage is also configured provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. 
         [0008]    Some embodiments relate to a comparator having a first stage configured to receive first and second input signals and to produce first and second output signals at first and second output terminals, respectively. The comparator also has a second stage configured to be coupled to a supply voltage and the first and second output terminals of the first stage. The second stage is configured to establish a voltage at one or more of the first and second output terminals that is close enough to the supply voltage to allow operation of the first stage when one or more of the first and second input signals reaches the supply voltage. 
         [0009]    Some embodiments relate to a comparator having a first stage configured to receive first and second input signals and to produce first and second output signals. The comparator also has a second stage coupled to the first stage at first and second input terminal of the second stage. The second stage is configured to receive a supply voltage. The second stage includes means for providing a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. 
         [0010]    Some embodiments relate to a comparator having first and second stages. The second stage includes a first current source coupled between a first supply voltage and a first input terminal of the second stage. The second stage also includes a second current source coupled between the first supply voltage a second input terminal of the second stage. The second stage further includes a latch coupled between a second supply voltage and the first and second input terminals of the second stage. 
         [0011]    The foregoing is a summary of some embodiments that is provided by way of illustration and is not intended to be limiting. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]    In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like reference character. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily drawn to scale, with emphasis instead being placed on illustrating various aspects of the invention. 
           [0013]      FIG. 1  shows a two-stage comparator as described in U.S. Published Patent Application 2010/0237907. 
           [0014]      FIG. 2  shows an embodiment of a two-stage comparator with improved dynamic range, according to some embodiments. 
           [0015]      FIG. 3  shows an equivalent circuit representing the comparator of  FIG. 2  during an autozeroing step. 
           [0016]      FIG. 4  shows an equivalent circuit representing the comparator of  FIG. 2  during a tracking step. 
           [0017]      FIG. 5  shows an equivalent circuit representing the comparator of  FIG. 2  during a latching step. 
           [0018]      FIG. 6  shows another embodiment of a comparator using an alternative arrangement in which the second stage has current sources between the inputs to the second stage and a ground terminal. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Although the two-stage comparator architecture of  FIG. 1  has various advantages, as described above, it has been appreciated that the comparator  100  may have a limited dynamic range due to the architecture of the second stage  20  of comparator  100 . In the circuit of  FIG. 1 , the voltages V 1  and V 2  which are provided as inputs to the second stage  20  are limited in value when switches S 5  and S 6  are turned on because of the voltage drop across the diode-connected PMOS transistors  1  and  2 . Voltages V 1  and V 2  cannot reach a voltage as high as the supply voltage (VCC) because the voltage drop across the diode-connected PMOS transistors  1  and  2  is approximately 0.6 V. For example, if VCC is 1.8 V, the diode drop across PMOS transistors  1  and  2  prevents V 1  and V 2  from rising above approximately 1.2 V. This constraint on the voltages V 1  and V 2  limits the allowable range of input voltages INN and INP for comparator  100 . When V 1  and V 2  cannot rise above 1.2 V, the voltage V 3  at the common terminal between transistors MN 1  and MN 2  should not rise above 1.0 V for proper operation of comparator  100 . Due to the gate-source voltage of transistors MN 1  and MN 2  of approximately 0.6 V, the input voltages INN and INP are not allowed to exceed 1.6 V or terminal V 3  will be at too high a voltage for proper operation of comparator  100 . Since the input voltages INN and INP cannot exceed 1.6 V, and cannot reach the supply voltage of 1.8 V, the dynamic range of the comparator is reduced by approximately 10%. 
         [0020]    The Applicants have developed a comparator architecture the reduces the limitations on voltages V 1  and V 2  and can allow the full range of input voltages INN and INP to be accepted at the input of the comparator. In some embodiments, voltages V 1  and/or V 2  can reach a value that is close to that of the supply voltage. For example, terminals V 1  and V 2  can be separated from the supply terminal VCC by current sources having a voltage drop of approximately 0.2 V, which is less than the 0.6 V diode drop of the diode-connected transistors  1  and  2  of comparator  100 . This configuration can allow voltages V 1  and V 2  to reach a higher value. 
         [0021]      FIG. 2  shows an embodiment of a comparator  200  having a first stage  30  and a second stage  40 . In some embodiments, first stage  30  of comparator  200  may be substantially the same as first stage  10  of comparator  100 . In the embodiment of  FIG. 2 , first stage  30  comprises a pair of input transistors MN 1 , MN 2 , herein of the NMOS type, having gate terminals connectable respectively to input terminal  11  and input terminal  12  through respective switches S 7  and S 8 . The gate terminals of input transistors MN 1 , MN 2  are connectable to a common mode DC voltage VCM through respective switches S 10  and S 9 . First terminals (herein the source terminals) of input transistors MN 1 , MN 2  are connected together at a common terminal having voltage V 3 , which common terminal is connected to a first current source I 1  supplying a bias current. Second terminals (herein drain terminals) of input transistors MN 1 , MN 2  are connected to a respective output  13 ,  14  of the first stage  30  and to first terminals (herein drain terminals) of a pair of load transistors MP 1 , MP 2 , herein of the PMOS type. Second terminals (herein source terminals) of load transistors MP 1 , MP 2  are connected to a supply terminal at a supply voltage VCC. Capacitors C 1  and C 2  are connected between source and gate terminals of a respective load transistor MP 1 , MP 2 . Switches S 1  and S 2  are connected between the gate and drain terminals of a respective load transistor MP 1 , MP 2 . 
         [0022]    In comparator  200 , the first stage  30  substantially forms a voltage/current converter which stores an offset-compensated bias condition during an autozeroing step. During the subsequent tracking and latching steps, the first stage  30  may generate, on its outputs  13  and  14 , current signals that are dependent on input signals INP and INN, independent of the offset caused by component mismatch in the first stage  30 . 
         [0023]    The outputs  13 ,  14  of the first stage are connectable to input terminals  21  and  22  of second stage  40  through respective switches S 5  and S 6 . Input terminals  21  and  22  of second stage  40  are connected to current sources I 2  and I 3 , respectively, which are coupled to the supply terminal at VCC. Terminals  13 ,  14  at voltages V 1 , V 2 , respectively, are separated from the supply voltage VCC by current sources I 2  and I 3 . Advantageously, current sources I 2  and I 3  may have a low voltage drop VDSAT across their terminals, such as approximately 0.2 V. The low voltage drop of 0.2 V across each of the current sources I 2 , I 3  can allow the voltages V 1  and V 2  to reach 1.6 V when VCC is 1.8 V. When terminals V 1  and V 2  can reach 1.6 V, the comparator  200  can accept inputs INN and INP having voltages as high as the supply voltage, e.g., 1.8 V. Thus, the dynamic range of the comparator  200  can be higher than the dynamic range of comparator  100  because comparator  200  can accept a wider range of input voltages. 
         [0024]    Inputs  21  and  22  of second stage  40  are also connected to first terminals of a pair of bias transistors MP 3 , MP 4 , herein of the PMOS type. Second terminals of the bias transistors MP 3 , MP 4  are connected to a latch  45  which includes output transistors MN 3 , MN 4 , capacitors C 3  and C 4 , and switches S 3  and S 4 . Specifically, the second terminals of the bias transistors MP 3  and MP 4  are connected to first terminals of the pair of output transistors MN 3 , MN 4 , herein of the NMOS type. The first terminals of the pair of output transistors also form the output terminals OUTP, OUTN of the comparator  200 . Second terminals of output transistors MN 3 , MN 4  are connected to a common terminal such as a supply terminal configured to be grounded in operation (i.e., at 0 V). Capacitors C 3  and C 4  are connected between a first terminal of a respective output transistor MN 3 , MN 4  and the gate terminal of the other output transistor MN 3 , MN 4 . Switches S 3  and S 4  are connected between the gate and first terminals of a respective output transistor MN 3 , MN 4 . 
         [0025]    Switches S 1 -S 10  receive control signals that control the comparator  200  in a sequence of three steps including an autozeroing step, a tracking step and a latching step. The operation of comparator  200  will now be described with reference to  FIGS. 3-5 , which show the equivalent circuit of comparator  200  in the autozeroing, tracking and latching steps, respectively. 
         [0026]    Autozeroing Step 
         [0027]      FIG. 3  shows the equivalent circuit of comparator  200  in the autozeroing step. As shown in  FIG. 3 , switches S 5 , S 6 , S 7 , S 8 , are opened and switches S 1 , S 2 , S 3 , S 4 , S 9  and S 10  are closed. Accordingly, the gate terminals of input transistors MN 1 , MN 2  of first stage  30  are connected to common mode DC voltage VCM and disconnected from the input terminals  11 ,  12 ; outputs  13  and  14  of first stage  30  are disconnected from second stage  40 ; load transistors MP 1  and MP 2  are in a transdiode configuration and second stage  40  is in a reset state. In this configuration, load transistors MP 1  and MP 2  are respectively biased with the current that is set by input transistors MN 1 , MN 2  connected thereto. During this step, capacitors C 1  and C 2  store gate-source voltages VGS of load transistors MP 1  and MP 2 . Second stage  40  is maintained in a reset state, with positive feedback of the latch  45  disabled due to switches S 3  and S 4  being closed. 
         [0028]    Tracking Step 
         [0029]      FIG. 4  shows the equivalent circuit of comparator  200  in the tracking step. During the tracking step, switches S 9  and S 10  are opened and switches S 7  and S 8  are closed, thereby providing input signals INN and INP to the gates of input transistors MN 1  and MN 2 , respectively. Switches S 1  and S 2  are opened, causing the gates of transistors MP 1  and MP 2  to be controlled by the voltages stored on capacitors C 1  and C 2 , respectively. Switches S 5  and S 6  are closed, connecting first stage  30  to second stage  40  and allowing the signal currents to flow through switches S 5  and S 6 . Switches S 3  and S 4  remain closed, maintaining output transistors MN 3 , MN 4  in a transdiode configuration. Capacitors C 3  and C 4  are in parallel to one another and store the voltage existing between outputs OUTP and OUTN of comparator  200  based on offset currents present in second stage  40 . 
         [0030]    Latching Step 
         [0031]      FIG. 5  shows the equivalent circuit of comparator  200  in the latching step. During the latching step switches S 3 , S 4 , S 5 , and S 6  are opened, while switches S 1 , S 2 , S 9  and S 10  remain open and switches S 7  and S 8  remain closed. At this point, the second stage  40  is disconnected from the first stage  30 . The latch  45  then uses positive feedback to latch one output terminal OUTP or OUTN to a high voltage level and the other output terminal OUTP or OUTN to a low voltage level, depending on the current that was received from the first stage  30  at terminals  21 ,  22 . 
         [0032]      FIG. 6  shows another embodiment of a comparator  300  that includes a first stage  50  and a second stage  60 . In the embodiment of  FIG. 6 , first stage  50  comprises a pair of input transistors MP 5 , MP 6 , herein of the PMOS type, having gate terminals connectable respectively to inputs receiving input signals INP and INN through respective switches. The gate terminals of input transistors MP 5 , MP 6  are connectable to a common mode DC voltage VCM through respective switches. First terminals of input transistors MP 5 , MP 6  are connected together and to a first current source I 1  supplying a bias current. Second terminals of input transistors MP 5 , MP 6  are connected to a respective output terminal  51 ,  52  of the first stage  50  and to first terminals of a pair of load transistors MN 5 , MN 6 , herein of the NMOS type. Second terminals of load transistors MN 5 , MN 6  are connected to a supply terminal that is configured to be grounded in operation. Capacitors C 1  and C 2  are connected between source and gate terminals of a respective load transistor MN 5 , MN 6 . Switches S 1  and S 2  are connected between the gate and drain terminals of a respective load transistor MN 5 , MN 6 . 
         [0033]    In comparator  300 , the first stage  50  substantially forms a voltage/current converter which stores an offset-compensated bias condition during an autozeroing step. During the subsequent tracking and latching steps, the first stage  50  may generate, on its outputs  51  and  52 , current signals that are dependent on input signals INP and INN, independent of the offset caused by component mismatch in first stage  50 . 
         [0034]    The outputs  51 ,  52  of the first stage are connectable to input terminals  53  and  54  of second stage  60  through respective switches S 5  and S 6 . Input terminals  53  and  54  of second stage  40  are connected to current sources I 2  and I 3 , respectively, which are coupled to a supply terminal configured to be grounded in operation. In second stage  60 , terminals  53  and  54  at voltages V 1 , V 2 , respectively, when switches S 5  and S 6  are closed, are separated from the ground terminal by current sources I 2  and I 3 . Advantageously, current sources I 2  and I 3  may have a low voltage drop across their terminals, such as approximately 0.2 V. The low voltage drop of 0.2 V across each of the current sources I 2 , I 3  can allow the voltages V 1  and V 2  to reach a voltage as low as 0.2 V. When terminals V 1  and V 2  can reach a voltage as low as 0.2 V, inputs signals INN and INP of the comparator  300  can be as low as 0V. Thus, the dynamic range of the comparator  300  can be relatively high because it can receive input voltages all the way down to 0 V. 
         [0035]    Input terminals  53  and  54  of second stage  60  are also connected to first terminals of a pair of bias transistors MN 7 , MN 8 , herein of the NMOS type. Second terminals of the bias transistors MN 7 , MN 8  are connected to a latch  65  which includes PMOS output transistors MP 7 , MP 8 , capacitors C 3  and C 4 , and two switches. In this embodiment, latch  65  is connected to the supply terminal at VCC. 
         [0036]    Comparator  300  may operate in a similar manner to that of comparator  200 . However, due to the use of a PMOS differential pair of transistors MPS, MP 6 , the acceptable input voltages for comparator  300  can be from 0 to VCC/2 volts, as compared to the acceptable input voltages for comparator  200  of VCC/2 to VCC volts. 
         [0037]    Modifications and changes can be made to the comparator disclosed and illustrated herein without departing from the scope of the present invention. For example the transistors can be replaced by other equivalent elements, for example bipolar transistors and/or transistors of different type. 
         [0038]    This invention is not limited in its application to the details of construction and the arrangement of components set forth in the foregoing description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. 
         [0039]    Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.