Abstract:
An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current. Further, a current limiting stage is coupled to the output node for limiting the selected current to a predefined magnitude.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to German Patent Application Ser. No. 102008008831.5, entitled “Current Limited Voltage Source with Wide Input Current Range,” filed on Feb. 13, 2008, which is hereby incorporated by reference for all purposes. 
     TECHNICAL FIELD 
     The invention relates generally to electronics and, more particularly, to current limited voltage sources with wide input current ranges. 
     BACKGROUND 
     Adjustable current sources are used in a variety of applications. An example of one application is the use in squib drives for automotive airbags. A reason for using the adjustable current source is the variable resistance of the squib and other application specific requirements. However, the adjustable current flowing through the squib is also used to generate a supply voltage for other electronic circuits. A simplified circuit diagram of a typical application of an adjustable current driver is shown in  FIG. 1 . 
     Referring to  FIG. 1 , the reference numeral  100  generally designates the conventional system. In this illustrative example, the magnitude of the adjustable current I ADJ  can be varied between three different target values I 1 , I 2 , and I 3 . The target values may range from 10 mA to 100 mA due to production spread of the resistance of squib Rx and other requirements of the application. In this example, the resistance of squib Rx may, for example, vary between about 1Ω and about 6Ω. The adjustable current source  102  is typically controlled by a digital control signal CNTL 0 . After the current I ADJ  has passed through the squib Rx, it is used to generate a substantially constant output supply voltage V OUT  at the output node or pin  114 . Output voltage V OUT  is used as a voltage supply for diagnostic circuitry  108 , which can determine, for example, the state of the squib Rx and other components. Output voltage V OUT  can also be used to supply further signal processing circuitry  112 . In order to maintain the output voltage V OUT  at a rather constant level, a Zener diode Dz is used that should provide a desired voltage level for the output voltage V OUT . 
     One problem with the system  100  is that the pins  104  and  106  can be shorted to a supply voltage level. A short circuit between pins  104  and  106  can result in large currents flowing into circuit  100 , potentially damaging or destroying various circuits. Therefore, a current limiter  110  is provided to limit the amount of current that can pass through the Zener diode Dz and flow into the circuit  116 . In a typical application, the current is limited to twice the target value (i.e., for a target value of 10 mA, the current limit is set to 20 mA and for a target value of 100 mA, the limit will be set to 200 mA). However, a Zener diode Dz, which is integrated on a semiconductor device, occupies a substantial amount chip area in order to be able to withstand currents as high as several milliamps. Additionally, if a current exceeds the current limit, the output voltage V OUT  at pin  114  would rise regardless of the breakdown voltage of the Zener diode. 
     Some other examples of conventional systems are European Patent No. EP1769974; U.S. Pat. No. 7,142,407; U.S. Pat. No. 7,154,733; and U.S. Patent Pre-Grant Publ. No, 2005/0225924. 
     SUMMARY 
     Accordingly, an integrated electronic device is generally provided which includes an adjustable current source for providing an adjustable current and for adjusting the magnitude of the adjustable current to a target value in response to a configuration signal. The circuitry generally comprises an auxiliary adjustable current source, which provides an auxiliary adjustable current, which has a magnitude that corresponds to the target value. There can also be a current selecting stage, which is generally adapted to receive the adjustable current and the auxiliary adjustable current and to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current. The circuitry comprises an output supply voltage level regulating loop coupled to the output node. The output supply voltage level regulating loop is generally adapted to keep the output supply voltage level at a preset value. Further, there can be a current limiting stage for limiting the selected current to a predefined magnitude. The current from the adjustable current source can be used, for example, to drive an adjustable current through a squib. After being passed through the squib, the current flows back into the integrated semiconductor device and is generally used for generating the supply voltage. Within the integrated semiconductor device according to the present invention, the auxiliary adjustable current source provides a second current (i.e., the auxiliary adjustable current) which has basically the same magnitude as the received adjustable current should have. The two currents are passed through a current selection stage, which provides at its output only a current which corresponds to the lesser of the two currents (i.e., the lesser of the adjustable and the auxiliary adjustable current). The auxiliary adjustable current is generally an internal current of the integrated semiconductor device, whereas the adjustable current is generally passed outside the integrated semiconductor device and can therefore be subject to short circuits and so forth. 
     Therefore, in case of a short circuit between any pin of the device under diagnosis, the selected current which can then used to generate the output voltage will not exceed a predefined target value. Since the integrated electronic device in accordance with a preferred embodiment of the present invention generally does use a Zener diode, the respective chip area for the diode can be saved. Furthermore, the output voltage is generally much more stable, as the output voltage level, can be regulated by a dedicated loop. 
     There are many different ways of implementing the current selection stage. Generally, the minimum current selection stage must be capable to limit the magnitude of the selected current (i.e., the current output to the output node) to a value which is not generally greater than a predetermined value if the received adjustable current exceeds a certain magnitude due to any failure. An advantageous implementation may be based on the auxiliary adjustable current source which can be coupled to the current selecting stage. The auxiliary adjustable current source can be set to the same magnitude as the current limit. The current selecting stage can then be adapted to choose a current as the selected current which has the magnitude of the adjustable current and the auxiliary adjustable current. In order to adjust the adjustable current source, the same control signals can be used as for the auxiliary adjustable current source. 
     The current selecting stage can adapted to output a selected current of a magnitude being the magnitude of a first current and a second current. The current selecting stage generally comprises a first current difference node adapted to provide a difference current of the first current minus the second current. There can also be a second current difference node adapted to provide the selected current by building the difference of the first current minus the difference current. Furthermore, there can be a current mirror coupled between the first difference node and the second difference node for supplying the difference current to the second difference node. The current mirror is generally adapted such that the current output from the current mirror to the second difference node becomes substantially zero when the second current is greater than the first current. This advantageous effect is provided by the current mirror as there is a diode coupled transistors in the current mirror, which prevents current from flowing in both directions. Accordingly, the current selecting stage can smoothly switch its output current (i.e., the selected current) between the first current and the second current, either of which has the smaller magnitude generally without producing spikes or unwanted noise in the circuit. There is generally no need to use comparators or high impedance nodes in the circuit in order to provide the necessary switching signals for switching the output current from one current (or magnitude) to another. The circuitry also can uses a current based comparison principle. Therefore, there is generally no need to translate currents into voltages, which typically requires comparators, high impedance nodes and large capacitors in order to smooth out transients or peaks due to switching. Furthermore, since no capacitors are required, chip area can be saved. In terms of the present invention, the first current is the adjustable current and the second current is the auxiliary adjustable current. 
     Additionally, the output supply voltage level regulating loop can includes an error amplifier and an output transistor coupled with a control gate to an output of the error amplifier. The error amplifier can then be adapted to compare the output supply voltage level with a reference voltage level. Further, the error amplifier provides a control voltage to the output transistor, which can be based on the comparison result. The control loop generally keeps the output voltage at the output node constant. 
     In the previous configuration of the output supply voltage level regulation loop, the output transistor can preferably be implemented such that its physical dimensions (i.e. the width to length ratio or W/L ratio) are adjustable in response to the selected target magnitude of the current. This allows the integrated electronic device to be more appropriately adapted to different target magnitudes of the adjustable current. 
     Furthermore, in the above configuration of the voltage regulation loop, an error amplifier can be used, which can advantageously be based on a Miller compensation. This allows different values of a load capacitance to be compensated so as to provide a stable design over a wide range of capacitive loads. This takes account of the varying capacitive loads that may be coupled to the output node in a specific application and the stability of closed loop control architectures. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a first pin that is adapted to be coupled to a load; a second pin that is adapted to be coupled to the load; a third pin; a first current source that is coupled to the first pin, wherein the first current source is adjustable, and wherein the first current source provides a first current to the first pin; a second current source that is adjustable and that provides a second current; a selector that is coupled to the second pin, the second current source, and the third pin, wherein the selector is adapted to receive the first current from the second pin and to receive the second current from the second current source, and wherein the selector outputs the lesser of the first and second currents to the third pin; a voltage regulator that is coupled to the third pin; and a current limiter that is coupled to the voltage regulator. 
     In accordance with a preferred embodiment of the present invention, the voltage regulator further comprises an error amplifier having a first input, a second input, and an output, wherein the first input is coupled to the third pin and the selector, and wherein the error amplifier receives a reference voltage at its second input; and a transistor that is coupled to the output of the error amplifier at its control electrode, the third pin at one of its passive electrodes, and the current limiter at one of its passive electrodes. 
     In accordance with a preferred embodiment of the present invention, the error amplifier further comprises a first amplifier that is coupled to the third pin and that receives the reference voltage; a second amplifier that is coupled between the first amplifier and the control electrode of the transistor; and a third amplifier that is coupled between the third pin and the control electrode of the transistor. 
     In accordance with a preferred embodiment of the present invention, the transistor further comprises a plurality of transistors, wherein each transistor is coupled to the output of the error amplifier at its control electrode and the third pin at one of its passive electrodes; and a plurality of switches, wherein each switch is coupled between at least one of the transistors and the current limiter, and wherein each electrode is actuated by a control signal. 
     In accordance with a preferred embodiment of the present invention, the current limiter further comprises a third current source that provides a reference current; and a first transistor that is diode connected and that is coupled to the third current source; and a second transistor that is coupled to the voltage regulator at one of its passive electrodes and that is coupled to the control electrode of the first transistor at its control electrode. 
     In accordance with a preferred embodiment of the present invention, the second current source further comprises a third transistor that is coupled to the control electrode of the first transistor at its control electrode; a first switch that is coupled to between a passive electrode of the third transistor and the selector, wherein the first switch is actuated by a control signal; a fourth transistor that is coupled to the control electrode of the first transistor at its control electrode; a second switch that is coupled to between a passive electrode of the fourth transistor and the selector, wherein the second switch is actuated by a control signal; a fifth transistor that is coupled to the control electrode of the first transistor at its control electrode; and a third switch that is coupled to between a passive electrode of the fifth transistor and the selector, wherein the third switch is actuated by a control signal. 
     In accordance with a preferred embodiment of the present invention, the first current source further comprises a plurality of first current sources; and a plurality of switches, wherein each switch is coupled between at least one of the first current sources and the first pin, and wherein each switch is actuated by a control signal. 
     In accordance with a preferred embodiment of the present invention, the apparatus further comprises diagnostic circuitry that is coupled to the third pin. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a first pin that is adapted to be coupled to a load; a second pin that is adapted to be coupled to the load; a third pin; an adjustable current source that provides a first current to the first pin, wherein the adjustable current source includes a plurality of first current sources; and a plurality of first switches, wherein each switch is coupled between the first pin and at least one of the first current sources, and wherein each switch is actuated by a first control signal; an auxiliary current source that provides a second current, wherein the auxiliary current source includes a reference current source; a first transistor that is diode-connected and that is coupled to the reference current source at one of its passive electrodes; a plurality of second transistors, wherein each second transistor is coupled to the control electrode of the first transistor at its control electrode; and a plurality of second switches, wherein each second switch is coupled to a passive electrode of at least one of the second transistors, and wherein each second switch is actuated by a second control signal; a selector that is coupled to the second pin, the auxiliary current source, and the third pin, wherein the selector is adapted to receive the first current from the second pin and to receive the second current from the auxiliary current source, and wherein the selector outputs the lesser of the first and second currents to the third pin; a voltage regulator that is coupled to the second pin; and a current limiter including; the reference current source; the first transistor; a plurality of third transistors, wherein each third transistor is coupled to the control electrode of the first transistor at its control electrode; and a plurality of third switches, wherein each third switch is coupled between a passive electrode of at least one of the third transistors and the voltage regulator, and wherein each third switch is actuated by a third control signal. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a first pin that is adapted to be coupled to a load and that provides a first current; a second pin; a current source that is adjustable and that provides a second current; a selector that is coupled to the first pin, the current source, and the second pin, wherein the selector outputs a selected current to the second pin, and wherein the selector includes a first current difference node that provides a difference current, wherein the difference current is the first current minus the second current; a second current difference node that provides the selected current, wherein the selected current is the first current minus the difference current; and a current mirror that is coupled between the first difference node and the second difference node, wherein the current mirror supplies the difference current to the second difference node, and wherein the current mirror is configured such that the difference current output to the second difference node becomes substantially zero when the second current is greater than the first current; a voltage regulator that is coupled to the second pin; and a current limiter that is coupled to the voltage regulator. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a simplified circuit diagram of conventional system; 
         FIG. 2  is a simplified circuit of a system in accordance with a preferred embodiment of the present invention; 
         FIG. 3  is a simplified circuit diagram of the voltage regulator of  FIG. 2  in accordance with a preferred embodiment of the present invention; 
         FIG. 4  is a simplified circuit diagram of the selector of  FIG. 2  in accordance with a preferred embodiment of the present invention; 
         FIG. 5  is a simplified circuit diagram of the system of  FIG. 2  in accordance with a preferred embodiment of the present invention; 
         FIG. 6  is bode diagram depicting characteristics of the system of  FIG. 2  in accordance with a preferred embodiment of the present invention; 
         FIG. 7  shows a simulated bode diagram of the voltage regulator of  FIG. 3 ; 
         FIG. 8  shows the variation of the phase margin as a function of the load capacitance of voltage regulator of  FIG. 3 ; 
         FIG. 9  shows waveforms relating to a transient simulation of the voltage regulator of  FIG. 3 ; 
         FIG. 10  shows a simulated bode diagram relating to the system of  FIG. 5 ; 
         FIG. 11  shows waveforms relating to a transient simulation of system of  FIG. 5 ; and 
         FIG. 12  shows waveforms of currents relating to the selector of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
     Referring to  FIG. 2-5  of the drawings, the reference numeral  200  generally depicts a system in accordance with a preferred embodiment of the present invention. The system  200  generally comprises an adjustable current source  202  and a circuit  204 . Circuit  204  is preferably integrated onto an integrated circuit or IC, while current source  202  may be external. However, current source  202  is preferably integrated onto an IC with circuit  202 . 
     Current source  202  is generally controlled by a digital control signal CNTL 1  so as to provide an adjustable current I ADJ . To accomplish this, current source  202  is generally comprised of current sources  502 ,  504 , and  506  that can supply currents I 1 , I 2 , and I 3  and which are generally coupled to switches S 1 , S 2 , and S 3 . Control signal CNTL 1  actuates one or more of switches S 1 , S 2 , and S 3  to generate the current I ADJ  with a target value of I 1 , I 2 , or I 3 . The adjustable current IADJ flows through node or pin  204  device under diagnosis or load Rx, which is also generally coupled pin  206 . The device under diagnosis Rx can be a squib of an airbag and may have a resistance value between about 1Ω and 6Ω due to production spread. The adjustable current I ADJ  may be varied between 10 mA and 100 mA in order to compensate the varying resistances of device Rx, and for other application specific purposes related to diagnosis. 
     Circuit  204  is generally comprised of selector  208 , auxiliary current source  210 , diagnostic circuit  210 , voltage regulator  212 , and current limiter  214 . Circuit  204  generally receives current I ADJ  through pin  206  and operates to provide an output voltage V OUT  at node or pin  218  by the use of the current I ADJ . 
     In operation, the auxiliary current source  210  provides an auxiliary current I AUX  with a target value, similar to that of current source  202 . This current source  210  can be separate from other elements in circuit  204  or current source  202  (as shown in  FIG. 1 ) or may share components within other elements in circuit  202  or current source  202  (as shown in  FIG. 5 ). For example, current source  218  shares current source  218  and transistor Q 2  with current limiter  214  as shown in  FIG. 5 . In this example configuration, current source  218  provides a reference current I REF  to transistor Q 2  (which is preferably a diode-connected NMOS FET). The control electrode (gate in an arrangement employing FETs) of transistor Q 2  is coupled to the control electrodes (gates in an arrangement employing FETs) to transistors Q 20  through Q 22  (which are preferably NMOS FETs) in current mirror configurations. Coupled to a passive electrode (drain in an arrangement employing FETs) of each of transistors Q 20  through Q 22  are switches S 4  through S 6  (respectively). These switches S 4  through S 6  are actuated by a control signal CNTL 2  so as to provide one of currents I L1  through I L3  as a target value of the current I AUX . Additionally, control CNTL 1  and CNTL 2  can be the same signal. 
     The selector  208  (which is generally coupled to pin  206 , current source  210 , and pin  216 ) generally provides a selection current I SEL , which is the preferably lesser of an auxiliary current I AUX  (generally provided by current source  210 ) and current I ADJ . In an automotive application, for example, any external pin of the system  100  (such as pin  206 ) can be shorted to other electronic circuitry (e.g., a car battery) thereby causing a large current to flow into circuit  204 . The current, which is supplied to the circuit  204 , would then be the sum of the current I ADJ  and an additional amount of current due to the short circuit. By employing the selector  208 , the selection current I SEL  would be the auxiliary current I AUX  during the described short circuit because the magnitude of current I AUX  is smaller. 
     To accomplish this, selector  208  is preferably comprised of transistors Q 4  through Q 11  (which are preferably PMOS FETs) transistors Q 12  through Q 18  (which are preferably NMOS FETs) that are arranged into a number of current mirrors. Current source  210  is generally coupled to a first current mirror (transistors Q 7  and Q 6 ) so that the current I AUX  can be applied to difference node DN 1 . Current source  202  is generally coupled to two current mirror (transistors Q 12  through Q 14 ) so that current I ADJ  can be applied to difference node DN 1  and difference node DN 2  through another current mirror (transistors Q 4  and Q 5 ). At difference node DN 1 , a difference current I DIFF  is generated (which is current I ADJ  minus current I AUX ). The difference current I DIFF  is supplied to two current mirrors (transistors Q 8  and Q 9  and transistors Q 15  and Q 16 ) so as to apply the difference current I DIFF  to the difference node DN 2  so that the selection current I SEL  output from the difference node is current I ADJ  minus the difference current I DIFF . However, because transistor Q 8  is diode-connected, the difference current I DIFF  is approximately zero when current I AUX  is greater than current I ADJ . Thus, the selection current I SEL  output at the difference node DN 2  is current I ADJ  when current I AUX  is greater than current I ADJ  (I SEL =I ADJ −0=I ADJ ) of is current I AUX  when current I AUX  is less than current I ADJ  (I SEL =I ADJ −I DIFF =I ADJ −(I ADJ −I AUX )=I AUX ). The select current I SEL  can then be supplied to other current mirrors (transistors Q 17 , Q 18 , Q 10 , and Q 11 ). It is generally advantageous to use current mirrors as shown, as the currents through the different branches are basically independent from each other. However, in a simplified configuration it might be possible to use diode elements in the current paths in order to prevent currents from flowing in the opposite direction, thereby achieving a similar effect. Additionally, advantage of the selector  208  is that no comparators and no high impedance nodes are required in order to determine the respective conditions in order to switch from one current (e.g., I ADJ ) to the other (e.g., I AUX ) and vice versa. The switching to the respective smaller current occurs automatically and smoothly without the need for further sophisticated and area consuming components. 
     This selection current I SEL  can then be applied to pin or node  216 . A voltage regulator  212  is also generally coupled to the node  216  for regulating and stabilizing the output voltage level V OUT . Voltage regulator  212  generally comprises an error amplifier  218  and a transistor Q 1  (preferably an NMOS FET). Error amplifier  218  can be an operational amplifier, in particular, an operational transconductance amplifier, which is shown in greater detail in  FIG. 3 . This error amplifier  218  generally includes two inputs and an output. The output of the error amplifier  218  is generally coupled to the control electrode of transistor Q 1  (gate in an arrangement employing FETs), while one input is coupled to node  216  and the other receives a reference voltage V REF . In operation, the error amplifier  218  generally compares the output voltage V OUT  with reference voltage V REF  to provides a control signal to transistor Q 1 , so as to open and close the channel of transistor Q 1  in response to the comparison result. 
     To perform as desired, the error amplifier  212  is generally comprised of three amplifiers  302 ,  304 , and  306  that are arranged in stages. The first stage is generally comprised of amplifier  302  (which is preferably a transconductance operational amplifier with a gain of gm 1 , an output resistance of R 1  and an output capacitance of C 1 ) that receives the output voltage V OUT  and reference voltage V REF . The second stage is generally comprised of amplifier  304  (which is preferably a transconductance operational amplifier with a gain of gm 2 , an output resistance of R 2  and an output capacitance of C 2 ) that receives the output amplifier  302  and that outputs a signal to the control electrode of transistor Q 1 . Additionally, capacitance C 2  generally represents the gate-source capacitance of transistor Q 1  which can be large because transistor Q 1  has a rather large aspect ratio (width to length ratio) in order to cope with large currents. A feedback connection is provided from node  216  to the control electrode of transistor Q 1 , so as to provide Miller compensation (which is discussed below), with the Miller capacitance C 3  being dimensioned so as to compensate for different load capacitance values C L . The Miller compensation moves the pole to higher frequencies beyond the unity gain bandwidth UGB (or transient frequency ft, which is the same as the UGB). This will be explained in more detail with respect to  FIG. 4 . The load capacitance can vary from, basically, zero to several hundred nF. The feedback path is generally comprised of amplifier  306  (which is preferably a transconductance operational amplifier with a gain of gm 3  and an input impedance is R 3  that is generally equal to 1/gm 3 . 
     Further, the reference voltage V REF  is generated in generally flexible and precise manner by use of a bandgap voltage V BG  (a voltage generated by a bandgap voltage source), coupled to an amplifier  502 . The amplifier  502  is generally coupled to transistor Q 19  (preferably an NMOS FET) and a resistive divider including resistors R 4  and R 5  and programmable resistor R P . This allows the reference voltage V REF  to be determined very precisely and variably through the digitally programmable resistor R P . 
     In conjunction with the voltage regulation provided by voltage regulator  212 , a current limit  214  is also included to generally provide current limiting. Current limiter  214  is coupled to a passive electrode of transistor Q 1  (source in an arrangement employing FETs) for limiting the current through transistor Q 1  to a desired current level. Current limiter is generally comprised of a reference current source  218  and current mirror (transistors Q 2  and Q 3 ). Preferably, reference current source is coupled to and provides a reference current I REF  to transistor Q 2  (which is preferably a diode-connected NMOS FET) and transistor Q 3  is coupled to transistor Q 1 . As the current through transistor Q 1  is already limited by the selector  208  to the magnitude of the selection current I SEL , the current limiter  214  is an additional precautionary measure to generally prevent large currents. 
     Moreover, the output voltage V OUT  can also be used to supply diagnostic circuitry  210  which are used to determine the state of the device under diagnosis Rx, as, for example, a squib. The capacitor C L  represents the capacitive load, coupled to the output node  216 . This capacitive load will typically vary over a wide range. 
     As an alternative configuration, transistor Q 1  can be replaced transistors Q 23  through Q 25  and transistor Q 3  can be replaced with switches S 7  through S 9  and transistors Q 26  through Q 28 . In this configuration, the aspect ratio (W/L ratio) of transistor Q 1  is generally variable in order to scale the output transistor Q 1  for different magnitudes of current I SEL , which can be accomplished by using transistor Q 23  through Q 25 . According to the selected target value I 1 , I 2  or I 3 , a corresponding output path through either transistor Q 23 , Q 24 , or Q 25  is selected by switching one of the switches S 7 , S 8  or S 9  with digital control signal CNTL 3 . 
     The desired dimensions for the transistors Q 23  through Q 25  for different currents I SEL  can be derived from the following considerations. The open loop gain was given by the following:
 
Gain( Adc )= gm 1 ·R   1   ·gm 2 ·R   2   ·GM 0 ·RM 0  (1)
 
In equation (1) the terms gm 1 ·R 1  and gm 2 ·R 2  are independent from the magnitude of the selection current I SEL  (i.e., GM 0  and RM 0  in equation (1) are dependent from the drain source current through the output transistor Q 1 ). Substitution of GM 0  and RM 0  by the simplified standard equations for MOSFETs in saturation provides the following result:
 
                     Gain   ⁡     (   Adc   )       =     gm   ⁢           ⁢     1   ·     R   1     ·   gm     ⁢           ⁢     2   ·     R   2     ·       2   ·     I   DS     ·   μ   ·   Cox   ·     W   L         ·     1     λ   ⁢           ⁢     I   DS                     (   2   )               
where λ, μ, and Cox are technology parameters and IDS is the drain source current of the MOSFET transistor Q 1  having a gate width of W and a length of L. When the adjustable current I ADJ  is varied, the current I SEL  is also adapted or scaled and thereby the drain source current IDS through transistor Q 1 . In order to take account of the changing current I SEL  the scaling factor 1/k, can be introduced, such that:
 
                     I   SEL     =       1   k     ·     I   DS               (   3   )                 Gain   ⁡     (   Adc   )       =     gm   ⁢           ⁢     1   ·     R   1     ·   gm     ⁢           ⁢     2   ·     R   2     ·       2   ·     I   SEL     ·   μ   ·   Cox   ·     W   L         ·     1     λ   ⁢           ⁢     I   SEL                     (   4   )               
However, the factor k in equation (4) can be compensated by reducing the width W of transistor Q 1  also by a factor of k, as could be seen from the following equation:
 
                           Gain   ⁡     (   Adc   )       =       ⁢     gm   ⁢           ⁢     1   ·     R   1     ·   gm     ⁢           ⁢     2   ·     R   2     ·       2   ·       I   DS     k     ·   μ   ·   Cox   ·     W     L   ·   k           ·     k     λ   ⁢           ⁢     I   DS                         =       ⁢     gm   ⁢           ⁢     1   ·     R   1     ·   gm     ⁢           ⁢     2   ·     R   2     ·       2   ·     I   DS     ·   μ   ·   Cox   ·     W   L         ·     1     λ   ⁢           ⁢     I   DS                           (   5   )               
Therefore, the gain can be made independent from the drain source current IDS, if the transistor is scaled accordingly.
 
     The same scaling principle applies automatically with respect to the first pole of the open loop transfer, the frequency of which is fpa as indicated by following equation: 
                   fpa   =     1     2   ⁢           ⁢     π   ·     R   2     ·     C   3     ·   GM     ⁢           ⁢     0   ·   RM     ⁢           ⁢   0               (   6   )               
Since equation (6) contains also the factor GM 0 ·RM 0 , fpa will remain unchanged as long as width W is reduced by the same factor k as the drain source current IDS through transistor Q 1 .
 
     Finally, the frequency of the second pole fpo is also unaffected from a scaled drain source current IDS through transistor Q 1  as could be seen from following equation: 
                   fpo   =       GM   ⁢           ⁢     0   ·     C   3           2   ⁢           ⁢     π   ·     C   L     ·     C   2                   (   7   )               
Equation (7) includes the factor GM 0 /C 2 , where capacitance C 2  is the gate source capacitance of transistor Q 1 . The gate source capacitance C 2  scales by factor k if the width W is reduced by k, as shown by the following equation:
 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           
                             GM 
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                                 W 
                                 
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                                   L 
                                 
                               
                             
                           
                           
                             
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                               Cox 
                               · 
                               
                                 W 
                                 L 
                               
                             
                           
                           
                             C 
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     An outcome of the above considerations is that it is possible to dimension the transistors Q 23  to Q 25  in order to compensate a changing drain source current (which is the selection current I SEL ) in the output transistors Q 23  to Q 25 . It is possible to maintain gain and stability characteristics although the circuit is switched from one current to another. As an example, assuming that current I ADJ  is set to a target value I 2 , current I ADJ  can be changed from a target magnitude of I 2  to I 1  by activating or actuating switches S 1 , S 7 , and S 4  while deactivating or deactuating the other switches. Transistor Q 23  will be switched on and transistors Q 24  and Q 25  will be switched off. Although the magnitude of the selected current I SEL  is changed, gain and stability of the control loop remain unaffected, since transistor Q 23  is scaled in accordance with the above equations. 
     Now turning to  FIG. 6 , an illustrative example of a Bode diagram in order to explain the Miller compensation as shown in  FIG. 3 . The stability analysis is based on the open loop. The loop is opened (disconnected) between the positive input of the error amplifier  212  and the node  216 . The stability coefficients are given by equations (1), (6), and (7) above and by the following equations: 
                     f   ⁢           ⁢   τ     =       gm   ⁢           ⁢   1       2   ⁢           ⁢     π   ·     C   3                   (   9   )               
The parameter fpa relates to the frequency of the first pole (as discussed above) and fpo to the frequency of the second pole (as discussed above). The transit frequency fτ (or unity gain bandwith UGB) depends on the gain gm 1  of the first stage and the value of the Miller compensation capacitance C 2 .
 
     Turning to  FIG. 7 , a simulated Bode diagram (AC response) of the voltage regulator  212  of  FIG. 3  employed in circuit  200  is shown. In this example, current I ADJ  is 20 mA, which is equal to the selection current I SEL , and a load capacitor C L  is 330 nF. As can be seen in  FIG. 5 , the phase margin at fτ is generally sufficient (i.e., greater than 40 degrees) because a target is to provide enough phase margin for a broad range of load capacitance values. 
       FIG. 8  shows the variation of the phase margin as a function of the value of load capacitance C L . For the voltage regulator  212  of  FIG. 3  having the parameters as set out above, the voltage regulator  212  generally provides sufficient phase margin for a load capacitance between zero and several tenths of μF. 
       FIG. 9  shows the transient behavior of the voltage regulator  212  of  FIG. 3 . If the current I ADJ  is switched to a greater value (e.g., from about 20 mA to 40 mA), the selection current I SEL  will also change. The output voltage V OUT  has a slight overshoot of about 0.1V and settles quickly (within about 10 μs to 20 μs) to the target voltage level of 8 V. 
       FIG. 10  shows a simulation of the circuit of  FIG. 5 . The bode diagrams shown relates to different target values of current I ADJ  and therefore to different currents of the selection current I SEL . However, the waveforms of magnitudes and phases of the open loop simulation are basically similar for different currents. 
       FIG. 11  shows a corresponding transient response for a varying current I ADJ  and a respective selection current I SEL . The output voltage V OUT  remains largely unchanged even though the magnitude of the current passed through the output transistors is substantially changed. 
       FIG. 12  shows waveforms of the input currents I ADJ  and I AUX  and the output current I SEL  selector  208 . As shown, the selection current I SEL  output from selector  208  is generally the lesser of the currents I ADJ  and I AUX . 
     Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.