Abstract:
A non-volatile semiconductor memory device includes a p-type Si substrate, an n-type well formed in the Si substrate, a control gate of a p-type buried diffusion region formed in the n-type well, an active region formed in the Si substrate in the vicinity of the n-type well and covered by a tunneling insulation film, and a floating gate electrode formed on the Si substrate so as to achieve a capacitance coupling with the p-type buried diffusion region, wherein the floating gate electrode extends on the active region over the tunneling insulation film, and the active region including a pair of n-type diffusion regions are formed at both sides of the floating gate electrode as source and drain regions, the n-type diffusion region forming the source region having an n−-type diffusion region at the side facing the n-type diffusion region forming said drain region.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
         [0001]    The present application is based on Japanese priority application No.2001-201055 filed on Jul. 2, 2001, the entire contents of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    The present invention generally relates to semiconductor devices. Especially it is related to a non-volatile semiconductor memory device.  
           [0003]    A non-volatile semiconductor memory device is a semiconductor memory device capable of holding information over long time period even if the supply of electric power is turned off. EEPROMs and flash memory devices are typical examples.  
           [0004]    In these semiconductor memory devices, information is held in a floating gate electrode in the form of electric charges. Especially, as for a flash memory device, the cell area is small and it is suited to construct a large scale integrated circuit together with other semiconductor devices, especially logic semiconductor devices.  
           [0005]    A typical conventional flash memory device has the floating gate electrode formed on a channel region via an intervening tunneling oxide film. Furthermore, a control electrode is formed on the floating gate electrode via an insulation film.  
           [0006]    However, the flash memory device having such a stacked electrode structure has a problem in that the fabrication process thereof is complex.  
           [0007]    On the other hand, a flash memory device having a single-layer gate structure is proposed in a related art of the present invention.  
           [0008]    [0008]FIG. 1A is a plan view showing the construction of a flash memory device  10  according to such a related art, while FIGS. 1B and 1C show the cross-sectional view taken along a A-A′ line and B-B′ line of FIG. 1A.  
           [0009]    Referring to FIGS.  1 A- 1 C, an active region  11 A is defined by a field oxide film  11 F formed on a Si substrate  11 , and another active region  11 B including a buried diffusion region  11 Bu is defined in the vicinity of the active region  11 A so as to extend parallel to the active region  11 A. Further, diffusion regions  11   a  and  11   b  of n+-type are formed inside the active region  11 A as shown in the cross-sectional view of FIG. 1B.  
           [0010]    On the Si substrate  11 , a gate electrode  13 G is formed via a gate oxide film  12 G at the part located between the diffusion regions  11   a  and  11   b.  By providing the gate electrode  13 G, there is formed a MOS transistor having a channel region between the diffusion regions  11   a  and  11   b  in the active region  11 A. This MOS transistor is used for reading the information.  
           [0011]    Furthermore a different n+-type diffusion region  11   c  is formed in the vicinity of the diffusion region  11   b  inside the active region  11 A at the opposite side of the diffusion region  11   a,  as shown in the cross-sectional view of FIG. 1B. Between the diffusion regions  11   b  and  11   c,  there is formed a floating gate electrode  13 FG via a tunneling oxide film  12 Tox. Further, an LDD region  11   d  of n-type is formed in a part of the diffusion region  11   b  at the side facing to the diffusion region  11   c.    
           [0012]    Referring to the cross-sectional view of FIG. 1C, the floating gate electrode  13 FG on the gate oxide film  12 G extends over the field oxide film  11 F toward the active region  11 B, wherein the floating gate electrode  13 FG extends further over the gate oxide film  12 G covering the surface of Si substrate  11  in the active region  11 B.  
           [0013]    [0013]FIGS. 2A and 2B show the writing operation of the flash memory device  10  of FIGS.  1 A- 1 C.  
           [0014]    Referring to FIGS. 2A and 2B, the diffusion region  11   b  is grounded and a positive voltage of +5-+10V is applied to the diffusion region  11   c  at the time of writing. Thereby, hot electrons are formed in the vicinity of the diffusion region  11   c.    
           [0015]    Simultaneously, a positive writing voltage of +15-20V is applied to the buried diffusion region  12 Bu in the active region  11 B. With this, the potential of the floating gate electrode  13 Fg, which is capacitance-coupled to the buried diffusion region  12 Bu, is lowered via the gate insulation film  12 G. As a result, there occurs injection of the hot electrons into the floating gate electrode  13 Fg in the active region  11 A, and the electrons thus injected are held stability in the floating gate electrode  13 Fg.  
           [0016]    [0016]FIGS. 3A and 3B show the erasing operation of flash memory device  10  of FIGS.  1 A- 1 C.  
           [0017]    Referring to FIGS. 3A and 3B, the diffusion region  11   c  is set to a floating state at the time of the erasing operation of the flash memory device and a positive erasing voltage of +15- +20V is applied to the diffusion region  11   b.  As a result, the potential of the diffusion region  11   b  is lowered and the electrons accumulated in the floating gate electrode  13 Fg are pulled out to the diffusion regions  11   d  and  11   b  through the tunneling insulation film  12 Tox.  
           [0018]    Thus, the flash memory device  10  of FIGS.  1 A- 1 C has a desirable characteristic in that the production of the device is easy due to the single-layer structure of the gate electrode.  
           [0019]    On the other hand, as will be understood from the plane view of FIG. 1A, the flash memory device has a problem in that the memory cell area tends to become large due to the use of two gate electrodes, the selection gate electrode  13 G and the floating gate electrode  13 Fg, at the time of reading.  
         SUMMARY OF THE INVENTION  
         [0020]    Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and the fabrication process thereof wherein the foregoing problems are eliminated.  
           [0021]    Another and more specific object of the present invention is to provide a flash memory device of single-layer gate structure that can reduce the memory cell area.  
           [0022]    Another object of the present invention is to provide a non-volatile semiconductor memory device, comprising:  
           [0023]    a p-type Si substrate;  
           [0024]    an n-type well formed in said Si substrate;  
           [0025]    a control gate formed of a p-type buried diffusion region formed in said n-type well;  
           [0026]    an active region formed in said Si substrate in the vicinity of said n-type well, said active region being covered by a tunneling insulation film; and  
           [0027]    a floating gate electrode formed on a surface of said Si substrate so as to achieve a capacitance coupling with said p-type buried diffusion region,  
           [0028]    said floating gate electrode extending over said active region in a state that said tunneling insulation film is interposed between said floating gate electrode and said surface of said Si substrate,  
           [0029]    said active region including a pair of n-type diffusion regions at both sides of said floating gate electrode respectively as a source region and a drain region,  
           [0030]    said n-type diffusion region forming said source region having an n−-type diffusion region at the side facing said n-type diffusion region forming said drain region.  
           [0031]    Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:  
           [0032]    a p-type Si substrate;  
           [0033]    a plurality of n-type wells formed repeatedly on said Si substrate, each of said n-type wells extending in said Si substrate in a first direction;  
           [0034]    a control gate formed of a p-type buried diffusion region, said p-type buried diffusion region being formed in each of said n-type wells so as to extend in said first direction;  
           [0035]    a plurality of active regions formed on said Si substrate between a pair of adjacent n-type wells, each of said active regions extending in said first direction and being covered with a tunneling insulation film;  
           [0036]    a floating gate electrode provided on each of said n-type wells so as to achieve a capacitance coupling with said p-type buried diffusion region in said n-type well via an insulation film covering said surface of said Si substrate, said floating gate electrode extending over an active region adjacent to n-type well;  
           [0037]    n-type diffusion regions formed at both sides of said floating gate electrode in each of said active regions;  
           [0038]    a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, said bit lines making a contact with corresponding n-type diffusion regions in each of said active regions; and  
           [0039]    a plurality of word lines respectively extending over said Si substrate in said first direction in correspondence said plurality of n-type wells, each of said word lines making a contact with a control gate in a corresponding n-type well.  
           [0040]    Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:  
           [0041]    a p-type Si substrate;  
           [0042]    a plurality of n-type wells formed on said Si substrate repeatedly, each of said n-type wells extending in said Si substrate in a first direction;  
           [0043]    a pair of buried diffusion regions formed in each of said n-type wells so as to extend in said first direction, each of said pair of buried diffusion regions forming a control gate;  
           [0044]    a pair of active region formed on a surface of said Si substrate in a part located between a pair of neighboring n-type wells, each of said active regions extending in said first direction and being covered with a tunneling insulation film;  
           [0045]    a floating gate electrode provided on each of said n-type wells so as to achieve a capacitance coupling with one of said p-type buried diffusion regions in said n-type well via an insulation film covering said surface of said Si substrate, said floating gate electrode extending over said active region adjacent to said n-type well;  
           [0046]    a pair of n-type diffusion regions formed in each of said active regions at both sides of said floating gate electrode;  
           [0047]    a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, each of said bit lines making a contact with a corresponding n-type diffusion region in each of said active regions; and  
           [0048]    a plurality of word lines extending over said Si substrate in said first direction respectively in correspondence to said plurality of n-type wells, each of said word lines making a contact with a control gate in a corresponding n-type well.  
           [0049]    Another object of the present invention is to provide a non-volatile semiconductor device, comprising:  
           [0050]    a p-type Si substrate;  
           [0051]    an n-type buried diffusion region formed in said Si substrate as a control gate;  
           [0052]    an active region formed in said Si substrate in the vicinity of said n-type buried diffusion region, said active region being covered by a tunneling insulation film; and  
           [0053]    a floating gate electrode formed over a surface of said Si substrate so as to make a capacitance coupling with said n-type buried diffusion region via an insulation film;  
           [0054]    said active region including a triple-well structure formed of said p-type Si substrate, an n-type well formed in said Si substrate and a p-type well formed in said n-type well,  
           [0055]    said floating gate electrode extending over said active region in the state that said tunneling insulation film is interposed between said floating gate electrode and said surface of said Si substrate, said Si substrate including a pair of n-type diffusion regions in said p-type well at both sides of said floating gate electrode respectively as a source region and a drain region.  
           [0056]    Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:  
           [0057]    a p-type Si substrate;  
           [0058]    a plurality of n-type buried diffusion regions formed on said Si substrate repeatedly, each of said n-type buried diffusion regions extending in a first direction and forming a control gate;  
           [0059]    a triple-well structure formed on said Si substrate between a pair of neighboring n-type buried diffusion regions, said triple-well structure including said p-type substrate, an n-type well formed in said p-type Si substrate, and a p-type well formed in said n-type well;  
           [0060]    an active region extending in said p-type well in said first direction, said active region being covered with a tunneling insulation film;  
           [0061]    a floating gate electrode provided on said Si substrate so as to achieve a capacitance coupling with said n-type buried diffusion region via an insulation film covering a surface of said Si substrate, said floating gate electrode extending over an active region adjacent to said n-type buried diffusion region;  
           [0062]    a pair of n-type diffusion regions formed in each of said active regions at both lateral sides of said floating gate electrode;  
           [0063]    a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, each of said bit lines making a contact with an n-type diffusion region in each of said plurality of active regions; and  
           [0064]    a plurality of word lines extending over said Si substrate in said first direction respectively in correspondence to said plurality of n-type wells, each of said word lines making a contact with a control gate in a corresponding n-type well.  
           [0065]    Another object of the present invention is to provide a semiconductor integrated circuit device having a non-volatile memory cell array, comprising:  
           [0066]    a p-type Si substrate;  
           [0067]    a plurality of n-type buried diffusion regions formed on said Si substrate repeatedly in said first direction as a control gate;  
           [0068]    a triple-well structure formed in a part of said Si substrate located between a pair of neighboring n-type buried diffusion regions and another pair of neighboring n-type buried diffusion regions, said triple-well structure including said p-type Si substrate, an n-type well formed in said Si substrate and a p-type well formed in said n-type well;  
           [0069]    a pair of active regions extending in said first direction in said p-type well, each of said active regions being covered with a tunneling insulation film;  
           [0070]    a floating gate electrode provided on said Si substrate so as to achieve a capacitance coupling with said n-type buried diffusion region via an insulation film covering a surface of said Si substrate, said floating gate electrode extending over said active region adjacent to said n-type buried diffusion region;  
           [0071]    a pair of n-type diffusion regions formed in each of said active regions at both sides of said floating gate electrode;  
           [0072]    a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, each of said bit lines making a contact with said n-type diffusion region in said active regions; and  
           [0073]    a plurality of word lines extending over said Si substrate in said first direction respectively in correspondence to said plurality of n-type wells, each of said word lines making a contact with a corresponding control gate in said n-type wells.  
           [0074]    Another object of the present invention is to provide a NAND-type non-volatile semiconductor memory device, comprising:  
           [0075]    a p-type Si substrate;  
           [0076]    a plurality of triple well structures each formed in said p-type Si substrate repeatedly, each of said triple well structures comprising said p-type Si substrate, an n-type well formed in said Si substrate so as to extend in said fist direction and a p-type well formed in said n-type well formed in said n-type well so as to extend in said first direction;  
           [0077]    an active region formed in said p-type well in each of said plurality of triple well structures, said active region being covered with a tunneling insulation film;  
           [0078]    a plurality of buried diffusion regions formed in said Si substrate in the vicinity of each of said triple well structures, each of said buried diffusion regions extending in said first direction and being aligned with each other in said first direction, said buried diffusion regions being further repeated in a second direction different from said first direction;  
           [0079]    a plurality of floating gate electrodes each provided on said Si substrate so as to extend over a part thereof located between a buried diffusion region and a neighboring active region so as to achieve a capacitance coupling with said buried diffusion region via an insulation film formed on a surface of said Si substrate, said plurality of diffusion regions extending over said tunneling insulation film on said active region; and  
           [0080]    a plurality of word lines extending over said Si substrate in a second direction across said plurality of triple well structures and said buried diffusion regions that are repeated in said second direction, each of said word lines making a contact with a buried diffusion region which is crossed with said word line,  
           [0081]    said floating gate electrode being repeated in said first direction in correspondence to said plurality of buried diffusion regions aligned in said first direction, said floating gate electrode being further repeated in said second direction,  
           [0082]    said plurality of word lines being repeated in said first direction.  
           [0083]    Another object of the present invention is to provide a NAND-type non-volatile semiconductor memory device, comprising:  
           [0084]    a p-type Si substrate;  
           [0085]    a plurality of triple well structures formed in said p-type Si substrate repeatedly, each of said triple well structures comprising a part of said p-type Si substrate and an n-type well formed in said Si substrate so as to extend in said first direction and a p-type well formed in said n-type well in said first direction;  
           [0086]    a pair of active regions formed in each of said plurality of triple well structures in said p-type well, each of said active regions extending in said fist direction and covered with a tunneling oxide film;  
           [0087]    a plurality of buried diffusion regions each formed on said Si substrate in the vicinity of one of said triple well structures, each of said buried diffusion regions extending in said first direction and arranged in said first direction in two rows; and  
           [0088]    a plurality of floating gate electrodes provided on said Si substrate so as to extend between each buried diffusion region and an active region neighboring thereto, each of said floating gate electrodes extending on said active region over said tunneling oxide film and making a capacitance coupling with said buried diffusion region via an insulation film formed on a surface of said Si substrate,  
           [0089]    said plurality of triple well structures and said two rows of buried diffusion regions forming respectively a first structural unit and a second structural unit repeated over a surface of said Si substrate alternately in a second direction different from said first direction,  
           [0090]    said non-volatile semiconductor memory device further having a plurality of word lines extending over said Si substrate in said second direction across said plurality of triple well structures and said buried diffusion regions that are repeated in said second direction, each of said word lines making a contact with a buried diffusion region each time said word line crosses a buried diffusion region;  
           [0091]    said floating gate electrode being formed repeatedly in said first direction in correspondence to said plurality of buried diffusion regions aligned in said first direction,  
           [0092]    said plurality of word lines being repeated in said first direction.  
           [0093]    According to the present invention, it is no longer necessary to form the select gate for each memory cell in the flash memory device of the single-layer gate structure, and it becomes possible to reduce the memory cell area by about 50%. By integrating such flash memory devices having a reduced cell area with each other, it becomes possible to construct a highly integrated flash-memory integrated circuit device. Furthermore, it becomes possible to reduce the operational voltage at the time of wiring or erasing of the flash memory device. Furthermore, it becomes possible to reduce the cost of constructing a hybrid integrated circuit device in which a flash memory device is integrated together with other devices such as a logic circuit device.  
           [0094]    Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0095]    FIGS.  1 A- 1 C are diagrams showing the construction of a single-layer gate flash memory device according to a related art of the present invention;  
         [0096]    [0096]FIGS. 2A and 2B are diagrams explaining the writing operation of the single-layer gate flash memory device of the related art of the present invention;  
         [0097]    [0097]FIGS. 3A and 3B are diagrams explaining the erasing operation of the single-layer gate flash memory device according to the related art of the present invention;  
         [0098]    [0098]FIG. 4 is a diagram showing the construction of a flash memory device according to a first embodiment of the present invention;  
         [0099]    [0099]FIGS. 5A and 5B are diagrams showing the cross-sectional view of the flash memory device of FIG. 4;  
         [0100]    [0100]FIGS. 6A and 6B are diagrams explaining the writing operation of the flash memory device of FIG. 4;  
         [0101]    [0101]FIGS. 7A and 7B are diagrams explaining the erasing operation of the flash memory device of FIG. 4;  
         [0102]    [0102]FIG. 8 is a diagram showing the construction of a flash memory device according to a second embodiment of the present invention in a plan view;  
         [0103]    [0103]FIGS. 9A and 9B are diagrams showing the construction of the flash memory device of FIG. 8 in a cross-sectional view;  
         [0104]    [0104]FIGS. 10A and 10B are diagrams explaining the erasing operation of the flash memory device of FIG. 9;  
         [0105]    [0105]FIG. 11 is a diagram showing the layout of a flash-memory integrated circuit according to a third embodiment of the present invention;  
         [0106]    [0106]FIG. 12 is a circuit diagram showing the circuit construction of the flash-memory integrated circuit of FIG. 11;  
         [0107]    [0107]FIG. 13 is a diagram showing the layout of a modification of the flash-memory integrated circuit of FIG. 11;  
         [0108]    [0108]FIG. 14 is a circuit diagram showing the constitution of the flash-memory integrated circuit of FIG. 13;  
         [0109]    [0109]FIG. 15 is a diagram showing the construction of a flash memory device according to a fourth embodiment of the present invention in a plan view;  
         [0110]    [0110]FIGS. 16A and 16B are diagrams showing the constitution of the flash memory device of FIG. 15 in a cross-sectional view;  
         [0111]    [0111]FIGS. 17A and 17B are diagrams explaining the writing operation of the flash memory device of FIG. 16;  
         [0112]    [0112]FIGS. 18A and 18B are diagrams explaining a different writing operation of the flash memory device of FIG. 16;  
         [0113]    [0113]FIGS. 19A and 19B are diagrams explaining the erasing operation of the flash memory device of FIG. 16;  
         [0114]    [0114]FIG. 20 is a diagram showing the layout of a flash-memory integrated circuit according to a fifth embodiment of the present invention;  
         [0115]    [0115]FIG. 21 is a circuit diagram showing the circuit construction of the flash-memory integrated circuit of FIG. 20;  
         [0116]    [0116]FIG. 22 is a diagram showing the layout of a modification of the flash-memory integrated circuit of FIG. 20;  
         [0117]    [0117]FIG. 23 is a circuit diagram showing the construction of the flash-memory integrated circuit of FIG. 22  
         [0118]    [0118]FIG. 24 is a diagram showing the layout of a flash-memory integrated circuit according to a sixth embodiment of the present invention;  
         [0119]    [0119]FIG. 25 is a circuit diagram showing the circuit construction of the flash-memory integrated circuit of FIG. 24;  
         [0120]    [0120]FIG. 26 is a diagram showing the layout of a modification of the flash-memory integrated circuit of FIG. 24;  
         [0121]    [0121]FIG. 27 is a diagram showing the construction of the flash-memory integrated circuit of FIG. 26. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0122]    [First Embodiment] 
         [0123]    [0123]FIG. 4 is a plane view showing the construction of the flash memory device according to a first embodiment of the present invention while FIGS. 5A and 5B show the cross-sectional view of the flash memory device of FIG. 4  taken along the lines A 1 -A 1 ′ and B 1 -B 1 ′ in FIG. 4.  
         [0124]    Referring to FIG. 4 and FIGS. 5A and 5B, an active region  21 A is defined on a p-type Si-substrate  21  by a field oxide film  21 F, and another active region  21 B is formed in the vicinity of the active region  21 A in a parallel relationship with the active region  21 A.  
         [0125]    As shown in the cross-sectional view of FIG. 5A, n+-type diffusion regions  21   a  and  21   b  are formed in the Si substrate  21  in correspondence to the active region  21 A, and a floating gate electrode  23  is formed on the Si substrate  21  in correspondence to the channel region formed between the diffusion regions  21   a  and  21   b,  with a tunneling oxide film  22 Tox interposed therebetween. In the constitution of FIG. 5A, an n-type LDD region  21   c  is formed adjacent to the n+-type diffusion region  21   a.    
         [0126]    As shown in the cross-sectional view of FIG. 5B, the floating gate electrode  23  extends over the field oxide film  21 F that defines the active region  21 A, wherein the floating gate electrode  23  extends further over the oxide film  22 G that covers the surface of the Si substrate  11  in the active region  11 B.  
         [0127]    In the active region  11 B, there is formed a well  21   d  of n+-type so as to cross the floating gate electrode  23  as shown in the plane view of FIG. 4, and a buried diffusion region  21   e  of p+-type is formed in the n+-type well  21   d  so as to cross the floating gate electrode  23  as shown in the plan view of FIG. 4.  
         [0128]    [0128]FIGS. 6A and 6B are diagrams that explain the writing operation of the flash memory device  20 .  
         [0129]    Referring to FIG. 6B, a positive voltage of about +5 volts is applied to the diffusion region  21   b  in the active region  21 A, and a positive writing voltage of +7- +12V is applied to the n+-type well  21   d  and the p+-type buried diffusion region  21   e  in the active region  21 B as shown in FIG. 6A. Thereby, the hot electrons formed in the vicinity of the diffusion region  21   b  are injected into the floating gate electrode  23  in the active region  21 A through the tunneling oxide film  22 Tox.  
         [0130]    Under the foregoing condition, it becomes possible to perform writing (program) of information by way of channel hot electron injection.  
         [0131]    [0131]FIGS. 7A and 7B are diagrams that explain the erasing operation of the flash memory device  20 .  
         [0132]    Referring to FIG. 7B, a positive voltage of about +5 volts is applied to the diffusion regions  21   a  and  21   c  at the time of erasing operation and the diffusion region  21   b  is made to a floating state. Further, as shown in FIG. 7A, a negative erasing voltage of about −10V is applied in this state to the p+-type buried diffusion region  21   e  in the active region  21 B and further to the n+-type well  21   d.  As a result, the electrons accumulated in the floating gate electrode  23  are discharged to the diffusion region  21   c  and  221   a  as a result of Fowler-Nordheim-type tunneling effect.  
         [0133]    Under the foregoing condition, erasing of information by way of Fowler-Nordheim tunneling effect becomes possible.  
         [0134]    Further, reading of information becomes possible by applying a voltage of 5V to the p+-type buried diffusion region  21   e  and a voltage of 1V to the diffusion region  21   b.    
         [0135]    Thus, in the flash memory device of this embodiment, it becomes possible to omit the select-gate electrode  13 G used in the flash memory device  10  of the related art explained previously, due to the use of the single-layer gate structure, and the cell area is reduced. Further, it becomes possible to construct a large scale integrated circuit having a large integration density together with the transistors constituting other high-speed logic circuits. Furthermore, it becomes possible to reduce the voltage at the time of erasing and writing operations.  
         [0136]    [Second Embodiment] 
         [0137]    [0137]FIG. 8 shows the construction of a flash memory device  30  according to a second embodiment of the present invention in a plan view, while FIGS. 9A and 9B show the cross-sectional view of the flash memory device  30  respectively taken along the line A 1 -A 1 ′ and line B 1 -B 1 ′ of FIG. 8. In the drawings, those parts corresponding to the parts explained previously are designated by the same reference numerals and the description thereof will be omitted.  
         [0138]    Referring to FIG. 8, the Flash memory device has a construction similar to the flash memory device  20  of the previous embodiment except that it can be seen that the width of the floating gate electrode  23  is reduced as compared with the device of the previous embodiment.  
         [0139]    In the flash memory device  30  of FIG. 8, the writing operation is carried out similarly to the previous embodiment explained with reference to FIGS. 6A and 6B. On the other hand, the erasing operation is carried out by applying a large negative voltage of about −15V to the n+-type wells  21   d  and  21   e  as shown in FIG. 10A. As a result, the electrons accumulated in the floating gate electrode  23  are discharged to the Si substrate  21  through the tunneling oxide film  22 Tox in the active region  21 A as a result of the Fowler-Nordheim-type tunneling effect. Thereby, it should be noted that the diffusion regions  21   a  and  21   b  are set to the floating state in the active region  21 A as shown in FIG. 10B.  
         [0140]    Similarly to the first embodiment, it becomes possible to perform writing of information by injection of channel hot electrons. Further, it becomes possible to perform erasing of information by the Fowler-Nordheim tunneling effect. When reading information, a voltage of 5V is applied to the p+-type buried diffusion region  21   e  and a voltage of 1V to the diffusion region  21   b.    
         [0141]    In the flash memory device  30 , it should be noted that the electrons are pulled out to the Si substrate  21 A at the time of erasing operation as shown in FIGS. 10A and 10B. Thus, it becomes possible to omit the LDD region  21   c  that was formed adjacent to the diffusion region  21   a  in flash memory device  20  of the previous embodiment. Further, it becomes possible to reduce the distance between the diffusion region  21   a  and the diffusion region  21   b  in the active region  21 A. Associated with this, it becomes possible to reduce the width of the floating gate electrode  23 .  
         [0142]    By reducing the width of the floating gate electrode  23  in the flash memory device  30  of this embodiment, it becomes possible to reduce the area of the flash memory cell.  
         [0143]    [Third Embodiment] 
         [0144]    [0144]FIG. 11 is a diagram showing the layout of the memory integrated circuit device that uses the flash memory device  20  of FIG. 4 or the flash memory device  30  of FIG. 8.  
         [0145]    Referring to FIG. 11, the active region  21 A and the active region  21 B are formed on the surface of the Si substrate  11  so as to be repeated alternately, and word lines WL are formed so as to extend in correspondence to the active regions  21 B. Thereby, each of the word lines WL makes a contact to the buried diffusion region  21   e  at a contact hole  21 H formed in an interlayer insulation film of which representation is omitted. Furthermore, a number of bit lines BL are formed so as to extend across the diffusion regions  21 A and  21 B, wherein each of the bit lines is caused to make a contact to the diffusion region  21   a  or the diffusion region  21   b  in the active region  21 A via a contact hole  21 I.  
         [0146]    [0146]FIG. 12 shows the circuit diagram of the flash-memory integrated circuit of FIG. 11.  
         [0147]    Referring to FIG. 12, it can be seen that the flash-memory integrated circuit of this embodiment forms a NOR-type circuit.  
         [0148]    The following Table 1 summarizes an example of driving conditions for each of the writing operation, erasing operation and the reading operation of the NOR-type flash memory integrated circuit device of FIG. 12, wherein it should be noted that Table 1 shows the writing, erasing and reading operations for the flash memory cell (i+1) marked up by a circle in FIG. 12. In the flash memory cell (i+1), it should be noted that the buried electrode  21   e  is connected to the word line WL(i+1) and the diffusion region  21   a  is connected to the bit line BL(i+1). Furthermore, the diffusion region  21   c  is connected to the adjacent bit line BL(i+2).  
                                                                                 TABLE 1                       program   BL(I)   Float   Erase1   BL(i)   Float   Read   BL(I)   Float                                    BL(I + 1)   0V       BL(I + 1)   5V   BL(I + 1)   0V           BL(I + 2)   5V       BL(I + 2)   Float   BL(I + 2)   1V           BL(I + 3)   Float       BL(I + 3)   5V   BL(I + 3)   Float           BL(I + 4)   Float       BL(I + 4)   Float   BL(I + 4)   Float           WL(I)   0V       WL(i)   −10V   WL(I)   0V           WL(I + 1)   10V       WL(I + 1)   −10V   WL(I + 1)   5V           WL(I + 2)   0V       WL(I + 2)   −10V   WL(I + 2)   0V                   Eerase2   BL(I)   Float                       BL(I + 1)   Float                       BL(I + 2)   Float                       BL(I + 3)   Float                       BL(I + 4)   Float                       WL(I)   −15V                       WL(I + 1)   −15V                       WL(I + 2)   −15V                      
 
         [0149]    Table 1 is referred to.  
         [0150]    At the time of writing, the bit lines BL(i+1) and BL(i+2) are selected and the bit line BL(i+1) is grounded. Further, a positive voltage of +5V is applied to the adjacent bit line BL(i+2) and other non-selected bit lines BL(i+3) and BL(i+4) are made to a floating state, and a writing voltage of +10V is applied to the selected word line WL(i+1) while grounding the non-selected word lines WL(i) and WL(i+2).  
         [0151]    As a result, the writing voltage is applied to the buried diffusion region  21   e  as explained previously, and the hot electrons formed in the vicinity of diffusion region  21   b  are injected into the floating gate electrode  23  through tunneling oxide film  22 Tox.  
         [0152]    In Table 1, it should be noted that “Erase 1” represents the erasing operation in which the electric charges are pulled out from the floating gate electrode  23  of the flash memory device (i+1) to the diffusion region  21   a,  as explained with reference to FIGS. 7A and 7B. In the erasing operation of “Erase 1”, the diffusion region  21   a  is supplied with the drive voltage of +5V from the bit line BL(i+1) and an erasing voltage of −10V is supplied to the floating gate electrode  23  from the word line WL(i+1). Further, in the erasing operation according of “Erase 1”, the bit line BL(i+1) adjacent to the selected bit line BL(i+2) is made to the floating state.  
         [0153]    In a flash-memory integrated circuit, such an erasing operation is achieved simultaneously also in other flash memory cells. Thus, the drive voltage of +5V is applied to other bit lines such as the bit line BL(i+3) with every one interval. The remaining bit lines, such as the bit line BL(i) or the bit line BL(i+4), are made to the floating state. Further, the erasing voltage of −10V is applied uniformly to all of the word lines, for example the word lines WL(i) and WL(i+2).  
         [0154]    In Table 1, “Erase 2” shows the condition of the erasing operation in which the electric charges are pulled out from the floating gate electrode  23  of the flash memory device (i+1) to the Si substrate  21  as explained with reference to FIGS. 10A and 10B. In the erasing operation according to “Erase 2”, the bit lines BL(i)−BL(i+4) are made to the floating state and all the word lines WL(i)−WL(i+2) are applied with the erasing voltage of −15V.  
         [0155]    When reading out information from the memory cell (i+1), the word line WL(i+1) corresponding to the memory cell (i+1) is selected and a reading voltage of +5V is applied thereto as represented in “Rread” of Table 1. Further, the other word lines WL(i) and WL(i+2) are grounded. Furthermore, the bit lines BL(i+1) and BL(i+2) corresponding to the memory cell (i+1) are selected and the bit line BL (i+1) is grounded while a drive voltage of +5V is applied to the bit line BL(i+2). The remaining bit lines BL(i), BL(i+3) and BL (i+4) are made to a floating state. With this, conduction or unconduction of the selected memory cell is detected by detecting the voltage appearing across the selected bit line pair and the desired reading of information is achieved.  
         [0156]    [0156]FIG. 13 shows the layout of a flash-memory integrated circuit according to a modification of the present embodiment. In FIG. 13, those parts corresponding to the parts explained previously are designated with the same reference numerals and the explanation thereof will be omitted.  
         [0157]    Referring to FIG. 13, a first structural unit is formed in the present modification from two adjacent active regions  21 A and  21 A and a second structural unit is formed also of two adjacent buried diffusion region  21   e  and  21   e,  and the first and second structural units are repeated alternately. Thereby, the two adjacent buried diffusion regions  21   e  are formed commonly in the n+-type well  21   d.    
         [0158]    [0158]FIG. 14 shows the circuit diagram of the flash-memory integrated circuit of FIG. 13.  
         [0159]    Referring to FIG. 14, a pair of transistor arrays are formed between a pair of adjacent the word lines such as the word line WL (i) and the word line WL (i+1) in the present modification. With this, it can be seen that the integration density is improved slightly in the flash-memory integrated circuit of FIG. 13 over the flash-memory integrated circuit of FIG. 11.  
         [0160]    As the operation of the circuit of FIG. 14 is substantially the same with the one explained previously with reference to Table 1, further explanation thereof will be omitted.  
         [0161]    [Fourth Embodiment] 
         [0162]    [0162]FIG. 15 shows the construction of a flash memory device  40  according to a fourth embodiment of the present invention in a plane view, while FIGS. 16A and 16B show the flash memory device  40  in a cross-sectional view taken respectively along lines A 2 -A 2 ′ and B 2 -B 2 ′ of FIG. 15. In the drawings, those parts corresponding to the parts explained previously are designated with the same reference numerals and the description thereof will be omitted.  
         [0163]    Referring to FIG. 15 and further to FIGS. 16A and 16B, it can be seen that an n-type well  21 N is formed in the Si substrate  21  in correspondence to the active region  21 A in this embodiment, and a p-type well  21 P is formed in the n-type well  21 N. On the other hand, the n+-type well  21   d  used in the previous embodiment is removed from the active region  21 B. Further, a buried diffusion region  21   e ′ of n+-type is formed.  
         [0164]    Next, the writing operation of the flash memory device  40  will be explained with reference to FIGS. 17A and 17B.  
         [0165]    Referring to FIGS. 17A and 17B, the n-type well  21 N and the p-type well  21 P in the active region  21 A are grounded at the time of writing operation, and the diffusion region  21   a  is grounded also in this state. Further, a drive voltage of about +5 volts is applied to the diffusion region  21   b  and a writing voltage of +10V is applied to the buried diffusion region  21   e ′ in the active region  21 B simultaneously. As a result, the hot electrons formed in the p-type well  21 P in the vicinity of the diffusion region  21   b  are injected into the floating gate electrode  23  through the tunneling oxide film  22 Tox.  
         [0166]    [0166]FIGS. 18A and 18B show a different writing operation of the flash memory device  40 .  
         [0167]    Referring to FIGS. 18A and 18B, the n-type well  21 N and the p-type well  21 P in the active region  21 A are set to 0V at the time of the writing operation, and a writing voltage of +20V is applied simultaneously to the buried diffusion layer  21   e  in the active region  21 B. As a result, hot electrons are injected into the floating gate electrode  23  from the p-type well  21 P through the tunneling oxide film  22 Tox by the Fowler-Nordheim-type tunneling effect.  
         [0168]    [0168]FIGS. 18A and 18B show the erasing operation of the flash memory device  40 .  
         [0169]    Referring to FIGS. 18A and 18B, a positive voltage of about +15 V is applied to the n-type well  21 N and the p-type well  21 P in the active region  21 A, and the buried diffusion region  21   e ′ in the active region  21 B is grounded. As a result, the electrons in the floating gate electrode  23  are pulled out to the p-type well  21 P through the tunneling insulation film  22 Tox by the Fowler-Nordheim-type tunneling effect.  
         [0170]    Under the foregoing condition, it becomes possible to carry out writing and erasing (program) of information based on the Fowler-Nordheim tunneling effect. Further, reading of information becomes possible by applying a voltage of 5V to the buried diffusion region  21   e ′ and a voltage of 1V to the diffusion region  21   b.    
         [0171]    [Fifth Embodiment] 
         [0172]    [0172]FIG. 20 is a diagram showing the layout of a flash-memory integrated circuit according to a fifth embodiment of the present invention, wherein the flash-memory integrated circuit is constructed by the flash memory device  40  explained previously. Further, FIG. 21 shows the circuit diagram corresponding to FIG. 19. In the drawings, those parts explained previously are designated with the same reference numerals and description thereof will be omitted.  
         [0173]    Referring to FIG. 20, the layout of the integrated circuit device of the present embodiment is similar to the one explained previously with reference to FIG. 11, except that the n+-type well  21   d  in the active region  21 B of FIG. 11 is removed. In place of the well  21   d,  it can be seen that a dual well structure including the well  21 N and the well  21 P is formed in the active region  21 A.  
         [0174]    Next, the operation of the flash memory device  40  of FIG. 20 will be explained for writing, erasing and reading operations with regard to the flash memory cell (i+1), which is marked up by circle in the FIG. 21, while referencing to Table 2.  
                                                                             TABLE 2                        program   BL(I)   FLOAT   Erase   BL(I)   FLOAT   READ   BL(I)   FLOAT                                    BL(I + 1)   0V   BL(I + 1)   FLOAT   BL(I + 1)   0V           BL(I + 2)   5V   BL(I + 2)   FLOAT   BL(I + 2)   1V           BL(I + 3)   FLOAT   BL(I + 3)   FLOAT   BL(I + 3)   FLOAT           BL(I + 4)   FLOAT   BL(I + 4)   FLOAT   BL(I + 4)   FLOAT           WL(I)   0V   WL(I)   0V   WL(I)   0V           WL(I + 1)   0V   WL(I + 1)   0V   WL(I + 1)   0V           WL(I + 2)   10V   WL(I + 2)   0V   WL(I + 2)   5V           WL(I + 3)   0V   p-well   15V   WL(I + 3)   0V                   n-well   15V                      
 
         [0175]    Table 2 is referred to as an example.  
         [0176]    At the time of the writing operation, the bit lines BL(i+1) and BL(i+2) are selected similarly to the case of Table 1 and the bit line BL(i+1) is grounded. Further, a drive voltage of +5V is applied the bit line BL(i+2) while the non-selected bit lines BL(i), BL (i+3) and BL(i+4) are set to floating state. In this state, the word line WL (i+1) is selected and a writing voltage of +10V is applied thereto, while the non-selected word lines such as the word lines WL(i) and WL(i+2) are grounded. As a result, hot electrons are formed in the vicinity of the diffusion region  21   b  in the active region  21 A corresponding to the selected flash memory cell, and the hot electrons thus formed are injected into the floating gate electrode  23 .  
         [0177]    At the time of the erasing operation, on the other hand, the erasing voltage of +15V is applied to the p-type well  21 P and the n-type well  21 N, and all the bit lines BL(i)−BL(i+4) are set to the floating state. Further, all the word lines WL(i)−WL(i+2) are grounded. As a result, the electrons in the floating gate electrode  23  are pulled out to the corresponding p-type well  21 P in all of the memory cells and there takes place a flash-erase operation, which is pertinent to a flash memory device.  
         [0178]    At the time of the reading operation, a read voltage of 5V is applied to the word line WL(i+1) of the selected memory cell (i+1), and other word lines WL(i) and WL(i+2) are grounded. Furthermore, the bit line BL(i+1) corresponding to the selected memory cell (i+1) is grounded, and the drive voltage of +5V is applied to the bit line BL(i+2). Other bit lines BL(i), BL(i+3) and BL(i+4) are made to the floating state.  
         [0179]    According to this embodiment, it is no longer unnecessary to apply a negative voltage at the time of erasing operation, unlike the operation of Table 1 explained previously, and it becomes possible to simplify construction of the power supply system of the flash memory device.  
         [0180]    [0180]FIG. 22 shows the layout of the flash-memory integrated circuit according to a modification of the present embodiment, while FIG. 23 shows the circuit diagram of the apparatus of FIG. 22. In the drawings, those parts corresponding to the parts explained previously are designated by the same reference numerals and description thereof will be omitted.  
         [0181]    Referring to FIG. 22, it can be seen that the flash-memory integrated circuit of the present modification has a layout in which a first structural unit formed of a pair of mutually adjacent active regions  21 A and a second structural unit formed of a pair of mutually adjacent active regions  21 B are repeated on the Si substrate. Also it can be seen that the mutually adjacent active regions  21 A and  21 A are formed commonly in the p-type well  21 P. As a result, it becomes possible to improve the integration density in the construction of FIG. 22 as compared with the construction of FIG. 20.  
         [0182]    As can be seen in the circuit diagram of FIG. 23, the flash-memory integrated circuit of this embodiment also has the construction of NOR-type. As the driving conditions of the circuit of FIG. 23 are similar to the one explained previously with reference to Table 2, further description thereof will be omitted.  
         [0183]    [Sixth Embodiment] 
         [0184]    [0184]FIG. 24 shows the construction of a flash-memory integrated circuit according to a sixth embodiment of the present invention while FIG. 25 shows the circuit diagram of the integrated circuit device of FIG. 24. In the drawings, those parts corresponding to the parts explained previously are designated with the same reference numerals and the description thereof will be omitted.  
         [0185]    Referring to FIG. 24, a double well structure including the n+-type well  21 N formed outside the p+-type well  21 P is formed in the Si substrate  11  along the active region  21 B, similarly to the previous embodiment. Further, the word line WL and the select gate SG extend over the Si substrate  21  so as to intersect perpendicularly to the extending direction of the wells  21 N and  21 P. At the intersection point of the word line WL and the p+-type well  21 P in the plane view of FIG. 24, n+-type diffusion regions  21 S and  21 D, which constitute the source region and the drain region of the flash memory device, are formed so as to be separated by a channel region that corresponds to the word line WL. Further, at the edge part of the p+-type well  21 P, the n+-type diffusion regions  21 S and  21 D form the selection transistor together with the select gate SG. Thus, the n+-type diffusion regions  21 S and  21 D are formed in the p+-type well  21 P so as to extend therewith alternately, repeatedly, and intermittently.  
         [0186]    Further, there are formed buried diffusion regions  21 A 1 - 21 A 5  in the Si substrate  21  such that each of the buried diffusion regions  21 A 1 - 21 A 5  is connected to a corresponding word lines WL, wherein each of the buried diffusion regions  21 A 1 - 21 A 5  extends over a limited length in the direction parallel to the extending direction of the p+-type well  21 P and the n+-type well  21 N. Further, a number of floating gate electrodes  23  are formed on the Si substrate  21  via an intervening tunneling oxide film (not shown) such that the floating gate electrodes bridge the buried diffusion regions, such as the region  21 A 1  and the adjacent p+-type well  21 P in the plan view of FIG. 24, and the floating gate electrode  23  forms a capacitance coupling with the buried diffusion region  21 A 1  and the gate oxide film (not shown). As a result, the electric potential of the floating gate electrode  23  is controlled through the buried diffusion region  21 A 1  in response to the voltage signal on the word line WL. Thus, writing and erasing of information are achieved by causing injection or pulling out of hot electrons to and from the floating gate electrode  23  between the source region  21 S and the drain region  21 D. Further, reading of information is achieved also between the source region  21 S and the drain region  21 D via the bit line BL.  
         [0187]    Referring to the circuit diagram of FIG. 25, it can be seen that the NAND-type flash-memory integrated circuit includes word lines WL(i)−WL(i+3) and that select gates SG 0  and SG 1  are formed outside of the word line WL(i) and outside of the word line WL(i+3) respectively. Further, a selection transistor is formed at the intersection of the select gate SG and the bit line BL(i) or the bit line BL(i+1).  
         [0188]    The following Table 3 shows the operational condition of erasing, writing and reading of the memory cell (i+1) in the NAND-type flash-memory integrated circuit of FIG. 25.  
                                                                             TABLE 3                       Program   SG0   3V   Erase   SG0   FLOAT   READ   SG0   5V                                    SG1   0V   SG1   FLOAT   SG1   5V           BL(I)   0V   BL(I)   FLOAT   BL(I)   ˜1V           BL(I + 1)   3V   BL(I + 1)   FLOAT   BL(I + 1)   ˜1V           WL(I)   10V   WL(I)   0V   WL(I)   5V           WL(I + 1)   20V   WL(I + 1)   0V   WL(I + 1)   0V           WL(I + 2)   10V   WL(I + 2)   0V   WL(I + 2)   5V           WL(I + 3)   10V   WL(I + 3)   0V   WL(I + 3)   5V           p-well   0V   p-well   15V   p-well   0V           n-well   0V   n-we;;   15V   n-well   0V                      
 
         [0189]    Table 3 is referred to as an example.  
         [0190]    At the time of the writing operation, a control voltage of +3V is applied to the select gate SG 0  and the select gate SG 1  is grounded. Further, the non-selected bit line BL(i) is grounded and a drive voltage of 3V is applied to the selected bit line BL (i+1). Furthermore, a controlled voltage of +10V is applied to the non-selected word lines WL(i), WL(i+2) and WL(i+3), and a writing voltage of about +20V is applied to the selected word line WL(i+1), and the p+-type well  21 P and n+-type well  21 N are grounded.  
         [0191]    At the time of erasing operation, on the other hand, the select gates SG 0  and SG 1  are made to the floating state as shown in Table 3, and all the bit lines including the bit lines BL(i) and BL(i+1) are set to the floating state. Further, all the word lines including the word line WL(i)−WL(i+3) are grounded. In this state, an erasing voltage of +15V is applied to the p+-type well  21 P and the n+-type well  21 N. As a result, the electrons accumulated in the floating gate electrode  23  are pulled out to the Si substrate  21  in the foregoing memory cell.  
         [0192]    At the time of reading operation, the p+-type well  21 P and the n+-type well  21 N are grounded and a control voltage of +5V is applied to the select gate SG 0  and SG 1 . Further, a drive voltage of +1V is applied to the bit lines BL(i) and BL(i+1), and the selected word line WL(i+1) is grounded. Furthermore, a voltage of +5V is applied to the non-selected word lines WL(i) and WL(i+2), and WL(i+3).  
         [0193]    Thus, according to this embodiment, it becomes possible to form a flash-memory integrated circuit of the NAND-type by using the flash memory device having a single-layer gate structure.  
         [0194]    Referring to FIG. 26, a pair of active regions  21 B forming the second structural unit are formed commonly in the p-type well  21 P in the present embodiment. As a result, it becomes possible to improve the integration density as compared with the layout of the previous embodiment of FIG. 23.  
         [0195]    In the present embodiment, a pair of active regions  21 B constituting the second structural unit are formed commonly in the p-type well  21 P, and as a result, the integration density is improved as compared with the layout of the previous embodiment of FIG. 23.  
         [0196]    As the writing, erasing and reading operations of the flash-memory integrated circuit of FIGS. 26 and 27 are similar to the previous embodiments, further description thereof will be omitted.  
         [0197]    Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.