Abstract:
This invention relates to a flash-successive approximation analog-to-digital converter combining the low speed, high resolution successive approximation method of conversion with the high speed, low resolution flash method of conversion, which provides the advantages of higher conversion speed with no increased conversion error.

Description:
This is a continuation of Application Ser. No. 07/218,462, filed July 13, 1988, which was abandoned upon the filing hereof. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a successive approximation analog-to-digital converter, and in particular to a flash-successive approximation analog-to-digital converter for improving conversion speed by using both successive approximation conversion and flash conversion. So far, the conversion speed of analog-to-digital converter (hereinafter referred to ADC) has been reduced by improvement of the processing technique. The processing technique is classified into two classes: the successive approximation method having low speed and high resolution, and the flash method having high speed and low resolution. 
     An ADC using the successive approximation conversion, as shown in FIG. 1, comprises sample and holder(2), comparator(3), n bit successive approximation register(4) and n bit digital-to-analog converter(5) (hereinafter referred to DAC), and functions as follows. 
     The analog signal inputted through the input terminal(I) is sampled by sample and holder(2), compared with the signal outputted from n bit DAC(5) and inputted to an n bit successive approximation register (hereinafter referred to as SAR(4)). 
     The SAR(4) outputs in parallel the digital data corresponding to the reference voltages, and the DAC(5) converts the data into an analog signal. For example, if the SAR(4) outputs the data of &#34;100 . . . 0&#34;, the n bit DAC(5) outputs the analog signal of Vref/2 (here, Vref is reference voltage) which is then compared with the sampled input signal by comparator(3). 
     If the sampled analog input signal is greater than Vref/2, the comparator(3) outputs a &#34;1&#34; and the most significant bit(MSB) of the output data of SAR(4) is set to &#34;1&#34;. If the sampled analog input signal is less than Vref/2, the comparator outputs a &#34;0&#34; and the most significant bit (MSB) of the output data of SAR(4) is set to &#34;0&#34;. In this manner the ADC determines the value of the MSB corresponding to the analog input signal. 
     Then in order to determine the next most significant bit the SAR(4) outputs &#34;X100 . . . 0&#34; (here, X is the pre-determined MSB whose value is set at &#34;1&#34; or &#34;0&#34;. If the value of &#34;X&#34; is &#34;1&#34; the n-bit DAC(5) outputs 3/4 Vref. If the value of &#34;X&#34; is &#34;0&#34; the n-bit DAC(5) outputs 1/4 Vref. Again the output of n-bit DAC(5) is compared with the sampled analog input signal. 
     In this way, the input analog signal and the analog signal outputted from SAR(4) are compared with each other by comparator(3). If the sampled analog input signal is less than the output of DAC(5) the comparator outputs an &#34;0&#34; and the next most significant bit of the output data of SAR(4) is set to an &#34;0&#34;. If the sampled analog input signal is greater than the output of DAC(5), the comparator outputs a &#34;1&#34; and the next significant bit of the output data of SAR(4) is set to a &#34;1 &#34;. 
     The SAR(4) will then output a &#34;XX100 . . . &#34; and the process will continue. If the above procedures are repeated to the least significant bit(LSB), the conversion is terminated and the SAR outputs the n-bit digital data corresponding to the input analog signal. 
     In the above, the number of bits represents the degree of resolution; the more the number of bits becomes, the more precise the converted digital data corresponding to the analog input signal will be. 
     Such successive approximation results in less error, but the conversion speed is comparatively slow. 
     FIG. 2 shows a block diagram for explaining a half flash A/D converter, which comprises sample and holder(7), n/2 bit flash A/D converter(8), latch(9), n/2 bit D/A converter(10), subtractor(11) and n/2 bit flash A/D converter(12). At first, the analog signal inputted through the input terminal(6) is sampled by sample and holder(7), and the sampled analog input signal is inputted to n/2 bit flash A/D converter(8). Flash converter (8) comprises 2 n/2  comparators and an encoder, and the upper n/2 bits are determined at once. The digital data corresponding to the upper n/2 bits is latched into n/2 bit DAC(10) by latch (9), and the equivalent analog signal is determined. The analog signal which corresponds to the upper n/2 bits is subtracted from the analog input signal in subtractor(11). 
     This subtracted signal is further delivered to the other n/2 bit flash A/D converter(12), which determines the remaining lower n/2 bit digital data. 
     Such a half flash conversion is speedily made, but has a drawback is that a conversion error is generated while determining the lower n/2 bits. 
     Comparing the conversion time of the successive approximation A/D converter and the half-flash converter, the latter reduces the conversion time by 1 order of magnitude even though the number of bits increases (i.e. the resolution increases), because the number of bits does not affect the conversion time but only increases the number of comparators and encoders. 
     However, the conversion error is inversely proportional to conversion speed, and the successive approximation A/D converter has less conversion error than the half flash A/D converter. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a flash-successive approximation A/D converter which combines the advantages of the successive approximation A/D converter and the half flash A/D converter so that the conversion speed is faster than the successive approximation while the conversion error remains the same. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram for showing a prior art successive approximation analog-to-digital converter; 
     FIG. 2 is a block diagram for showing a prior art half flash analog-to-digital converter; and 
     FIG. 3 is a block diagram for showing a flash-successive approximation analog-to-digital converter according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, an embodiment of the present invention is explained with reference to FIG. 3. 
     FIG. 3 is a circuit diagram of a flash-successive approximation ADC according to the present invention. A flash conversion circuit (29) is comprised of sample and holder(21), n/2 bit flash converter(22), latch(23), and n/2 bit DAC(24), and subtractor(25), these components are connected respectively for determining the upper n/2 bits, and for outputting an analog signal corresponding to the upper n/2 bits. The analog signal inputted through the input terminal(20) is sampled by sample and holder(21), and is input to n/2 bit flash converter(22) which produces the upper n/2 bit digital data. 
     The above n/2 bit flash converter(22) comprises n/2 comparators and encoders, wherein the sampled signal is compared simultaneously with the reference voltages delivered by the dividing steps of 2 n/2 , the signals resulting from the comparison are delivered to the encoders, outputting the entire upper n/2 bit digital data set. 
     The upper n/2 bit signals are delivered through latch(23) to the n/2 bit DAC(24), generating an analog signal which corresponds to the upper n/2 bits. A successive approximation conversion circuit (30) includes n/2 bit successive approximation converter (27) and n/2 bit DAC (28), respectively connected for determining the lower n/2 bits. The sampled analog signal is inputted to subtractor (25) and the analog signal corresponding to the upper n/2 bits is subtracted from it, leaving an analog signal corresponding to the lower n/2 bits (V1), which is inputted to comparator (26). 
     For example, if the n/2 bit successive approximation converter (27) initially outputs data &#34;1000 . . .&#34; to the n/2 bit DAC (28), the DAC (28) outputs the analog signal of Vref/2, which is then compared to V1 by comparator (26). If V1 is greater than Vref/2, the comparator (26) outputs a &#34;1&#34;. If V1 is less than Vref/2, the comparator outputs a &#34;0&#34;. The comparator (26) output sets the MSB of successive approximation converter (27) to the digital MSB value corresponding to V1. Then in order to determine the next most significant bit, the successive approximation converter (27) outputs &#34;X100 . . .&#34; (where X is the predetermined MSB whose value is set at &#34;1&#34; or &#34;0&#34;). If the value of X is &#34;1&#34; the n/2 bit DAC (28) outputs 3/4 Vref. If the value of X is &#34;0&#34; the n/2 bit DAC (28) outputs 1/4 Vref. Again the output of the DAC (28) is compared with the analog signal V1. If V1 is less than the output of DAC (28), the comparator outputs a &#34;0&#34; and the next MSB of the output data of successive approximation converter (27) is set to &#34;0&#34;. If the analog signal V1 is greater than the output of DAC (28), the comparator outputs a &#34;1&#34; and the next MSB of the output data of successive approximation converter (27) is set to &#34;1&#34;. Continuing this process, the n/2 bit successive approximation converter (27) determines sequentially the lower n/2 bit data from MSB to LSB and outputs it. The lower n/2 bit data is coupled with the upper n/2 bit data to yield an n-bit data set corresponding to the original sampled analog signal. 
     As mentioned hereinbefore, the operational effect of the present invention is first to reduce the conversion speed in comparison to the successive approximation bit ADC, and second to reduce the conversion error in comparison to the flash successive approximation ADC. This is accomplished by determining the upper n/2 bits in a flash conversion and the lower n/2 bits in a successive approximation conversion. Half the process is accomplished with the speed of a flash converter, but the conversion error remains unchanged because the lower n/2 bits (which are most susceptible to conversion error) are determined by successive approximation. 
     As this invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, the present embodiment is illustrative and should not limit the scope of the invention. All changes that fall within meets and bounds of the claims, or are equivalent to such meets and bounds are intended to be embraced by the claims.