Abstract:
An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences.

Description:
BACKGROUND 
     1. Field of the Invention 
     This invention relates generally to clocking systems. In particular, the present invention relates to computers with a multiple clock signal distribution network. 
     2. Description of the Related Art 
     Computer systems typically include clock generator sources that have multiple clock signal outputs with multiple frequencies. Although such clock generator sources are commercially available in the form of integrated circuit (IC) chips, computer systems (especially large computer systems such as servers) frequently need more clock signal outputs than the limited number provided by a single chip. They therefore use a multiple chip clock distribution network consisting of a plurality of “fanout” ICs that receive a single input clock signal and drive a plurality of clock output signals. 
     Regardless of the number of clock output signals, they must all arrive at their respective loads in phase within a small skew window from each other. A skew window on the order of a few hundred pico-seconds (ps) is difficult to achieve because the input to output propagation delays between different fanout ICs are usually several times larger than the targeted skew window. 
     A common solution to this problem incorporates commercially available programmable delay chips in the multiple chip clock distribution network. With step sizes down to 20 ps, these programmable delay chips allow the clock signals in a computer system to be de-skewed manually. Delay can be added to clocks coming from fanout ICs having shorter propagation delays to compensate for fanout ICs with longer propagation delays in the distribution network. But even with only a few programmable delay chips in the computer system the process of manually calibrating the clock signals by taking repeated skew measurements and then adjusting (usually via DIP switches) the programmable delays can be quite time consuming. Additionally, changes in temperature and voltage affect each fanout IC differently resulting in an unacceptable skew between the different fanout ICs even though a manual calibration has been successfully performed. 
     BRIEF SUMMARY 
     An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram illustrating an automatic clock deskew circuit according to an example embodiment of the invention. 
     FIG. 2 is an illustration of a phase-frequency detector operation. 
     FIG. 3 is another illustration of the phase-frequency detector operation. 
    
    
     DETAILED DESCRIPTION 
     This application describes an automatic clock calibration circuit adapted for use in a validation system for validating the proper operation of a computer system. However, such circuit, and the use of such a circuit in a server system, is merely exemplary. There are various possible embodiments of the invention which may of course be used in systems other than a validation system for validating the proper operation of a computer system. 
     FIG. 1 illustrates an automatic clock de-skew circuit  100  according to an example embodiment of the invention. Only two clock frequencies and a limited number of clock output signals are shown in FIG. 1 merely for the sake of clarity. A clock signal distribution network could, of course, have more clock frequencies and clock output signals. 
     Clock Source  101  generates clock signals CLK 1  and CLK 2 , and corresponding reference clock signals CLK 1 _REF and CLK 2 _REF. Clock source  101  may be a programmable PLL clock generator IC chip. (Although illustrated as a single block, clock source  101  need not be a programmable PLL clock generator or a single IC chip, but may comprise any combination of elements for providing the clock signals desired for the system.) Since there are four fanout buffers  103 - 1  to  103 - 4 , two copies of each of the two clock signals are provided and each one of the resulting four clock signals (CLK 1 _A, CLK 1 _B, CLK 2 _A, CLK 2 _B) is provided to a corresponding one of the four fanout buffers  103 - 1  to  103 - 4  via a programmable delay chip  102 - 1  to  102 - 4 . (In any given computer system, the number of clock loads in the system dictates how many fanout buffers are required. The number of required fanout buffers in turn dictates the number of copies of clock signals that are required. In large systems, there may be clock loads in excess of  100 .) 
     The clock outputs of fan-out buffers  103 - 1  to  103 - 4  are routed in precisely matched lengths to corresponding system loads (not shown). These system loads may be located throughout a computer system. Indeed, the automatic clock calibration circuit shown in FIG. 1 may be located on a clock board “separate” from other boards and/or the remainder of the computer system. In addition, a feedback output from each fanout buffer (CLK 1 _BUF 1 _FB, CLK 1 _BUF 2 _FB, CLK 2 _BUF 1 _FB, CLK 1 _BUF 2 _FB) is routed to MUX 1   104  matching the same length as the loads. Since the characteristics of fanout buffers  103 - 1  to  103 - 4  allow for very tight skew control for each output (preferably 0 ps), the feedback clock signals will arrive at MUX 1   104  at the same time that the other clock signals arrive at their system loads. 
     The output of MUX 1   104  drives one input of phase detector  106 . Similarly, reference clocks CLK 1 _REF and CLK 2 _REF are input into MUX 2   105 , whose output drives the other input of phase detector  106 . Phase detector  106  outputs digital pulses whose width is proportional to the phase error. These pulses are filtered and amplified in the Filter &amp; Gain Stage  107  to convert the phase error information into a voltage for the Analog to Digital converter  108 - 1 . This operation is under the control of microcontroller  108  via control bus  109 . 
     Control bus  109  is associated with circuitry (not shown) which decodes local bus addresses to provide latch enable signals to clock source  101 , programmable delay elements  102 , a frequency counter, and a LED display (not shown) as well as driving and reading configuration pins of various selectable devices at DC levels. There may also be control signals for selection of clock signal families or groups. This is because a user may want to check only one clock signal family or group, and microcontroller  108  may accept only a single asynchronous external clock source that must be externally divided down by an appropriate value. 
     The example embodiment in FIG. 1 provides a method of automatically eliminating skew in large clock distribution networks or, at least, holding the skew between all clocks to less than about 40 or 50 ps. The circuitry is capable of accurately determining the phase relationship between multiple clock signals of the same frequency and adjusting individual delays of those signals to minimize their skew. It does this by constantly monitoring the system level skew and automatically adjusting the programmable delay chips. When an out of tolerance condition is detected, the system either warns the operator of the condition and/or automatically re-adjust the programmable delay chips. 
     If a delay update is made to a single clock line while the computer system is operating, the adjustment can potentially occur precisely when the clock is transitioning, resulting in a transient or in a non-monotonic edge which can compromise the rest of the system. Consequently, automatic calibration is preferably performed at the user&#39;s selection (such as by pressing a button, etc.). Thereafter, the phase skews will be constantly measured (within either families or groups) and visual indicators may signal to the user that re-calibration is necessary due to skew measurements exceeding a certain range. 
     During automatic calibration, microcontroller  108  periodically compares each clock in a plurality of clock signals (such as a smaller clock group or family) against the reference signal for that plurality of clock signals (such as a family&#39;s reference signal clock) and determines the one clock signal that has the longest delay. It then automatically adjusts the delay values of the programmable delay elements  102  of all other clocks in the plurality of clock signals (or in the smaller clock group or family) to match the delay of the one clock signal that has the longest delay in order to minimize skews, match phase error and maintain frequency offsets within a family or group of clock signals. The clock signals in the process may include various numbers of groups of clock signals. For example, there may be one or more clock families derived from a single common clock source. 
     The functionality of phase detector  106  is similar to that of phase comparators used in phase-locked loops. A simple iterative algorithm can be employed to minimize the skew, as long as the skew is relatively small. 
     FIGS. 2 and 3 illustrate an exemplary operation used in conjunction with phase detector  106 . If the reference clock leads as shown at the top left of FIG. 2, then the down output (D) will be a monotonous high signal while the Up output (U) will toggle at a duty cycle proportional to the magnitude of the phase difference as shown at the top right of FIG.  2 . In the reverse case when the feedback clock leads as shown at the bottom left of FIG. 2, the Up (U) output will be monotonously high while the Down output (D) will toggle as shown at the bottom right of FIG.  2 . The behavior is stable in marginal cases. If both clock signals are perfectly in phase as shown in the middle of the left half of FIG. 2, then the Up and Down output will be monotonously high as shown in the middle of the right half of FIG.  2 . If the clock signals are 180 degrees out-of-phase, then the Up and Down outputs will both toggle at 50%. If a plurality of feedback signals are provided for a single reference clock signal as shown in the example of FIG. 3, then a plurality of corresponding Up (U) output signals can be output by phase detector  106 . 
     The algorithm that is preferably implemented in microcontroller  108  to carry out this operation is a two pass process. The first pass determines which fanout buffer in the same clock frequency has the longest delay compared to the reference clock. The second pass will then incrementally adjust the delays to the fanout buffers until the two are matched. The very first time this algorithm is run, all programmable delays are set to zero. In subsequent executions, this algorithm changes the settings in the programmable delays. A version of this algorithm is represented in the following pseudo code. Of course, several different software implementations are possible that can yield similar results. 
     
       
         
               
             
               
               
             
               
               
             
               
               
             
               
             
               
               
             
               
               
             
               
               
             
               
             
           
               
                   
               
             
             
               
                 PASS 1 
               
               
                 For n=1 to NumClocks 
               
             
          
           
               
                   
                 MaXDelay(n) = 0 
               
               
                   
                 Set MUX2 select for CLKn_REF 
               
               
                   
                 For m=1 to NumBuffers 
               
             
          
           
               
                   
                 Set MUX1 select for CLKn_BUFm_FB 
               
               
                   
                 Delay (m) = A2D_Output 
               
               
                   
                 If Delay (m)&gt;MaXDelay(n) then MaXDelay(n)=Delay(m) 
               
             
          
           
               
                   
                 Next m 
               
             
          
           
               
                 Next n 
               
               
                 PASS 2 
               
               
                 For n=1 to NumClocks 
               
             
          
           
               
                   
                 Set MUX2 select for CLKn_REF 
               
               
                   
                 For m=1 to NumBuffers 
               
             
          
           
               
                   
                 Set MUX1 select for CLKn_BUFm_FB 
               
               
                   
                 While A2D_Output&lt;MaXDelay(n) Increment DELAYn_m 
               
               
                   
                 While A2D_Output&gt;MaXDelay(n) Decrement DELAYn_m 
               
             
          
           
               
                   
                 Next m 
               
             
          
           
               
                 Next n 
               
               
                   
               
             
          
         
       
     
     The accuracy of this scheme is dependent upon the resolution of A to D converter  108 - 1 , the sensitivity of phase detector  106  and the sensitivity of Filter &amp; Gain Stage  107 . With a full range (360 degrees) phase detector  106 , a 10 nsec clock and a 9 bit A to D converter  108 - 1 , the skew accuracy is less than 20 ps. The following equation calculates the skew accuracy for a given implementation:        Skew   =         PhaseDetectorRange                   (   Degrees   )         360                   Degrees   /   cycle         ×       ClkPeriod                   (     ns   /   Cycle     )         2   n                                
     Of course, the example embodiments of the invention are not limited to personal computers. Indeed, the invention may be used in any processing device employing a large number of clock signals. 
     Other features of the invention may be apparent to those skilled in the art from the detailed description of the exemplary embodiments and claims when read in connection with the accompanying drawings. While the foregoing and following written and illustrated disclosure focuses on disclosing exemplary embodiments of the invention, it should be understood that the same is by way of illustration and example only, is not to be taken by way of limitation and may be modified in learned practice of the invention. While the foregoing has described what are considered to be exemplary embodiments of the invention, it is understood that various modifications may be made therein and that the invention may be implemented in various forms and embodiments, and that it may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim all such modifications and variations.