Abstract:
A method of operating a power up circuit is disclosed. The method includes receiving an input voltage and creating a plurality of sample voltages from the input voltage. One of the sample voltages is selected and compared to a reference voltage. The power up circuit produces a brown-out signal in response to the step of comparing.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    Embodiments of the present invention relate to a system on a chip (SoC) having a dynamic rising brown-out threshold voltage to provide power up control and to support energy harvesting. 
         [0002]    Power consumption of electronic devices has become an increasingly important design consideration. This is especially important with the proliferation of portable electronic devices using battery power as well as alternative energy sources. Utilizing these alternative energy sources is often referred to as energy harvesting. These alternative energy sources are typically characterized by low output voltage and high source impedance. They include amorphous solar cells, thermoelectric transducers, radio frequency receivers, and other available sources. Due to the relatively low output voltage of these sources, they are often combined with a charge pump to provide a usable output voltage level. The charge pump, however, has a very high source impedance with very low steady state output current capacity. This low steady state output current capacity complicates both power up and normal device operation. Embodiments of the present invention are directed to improving problems associated with power up operation of electronic devices as will be described in detail. 
       BRIEF SUMMARY OF THE INVENTION 
       [0003]    In a preferred embodiment of the present invention, there is disclosed a method of operating a power up circuit of a System on a Chip (SoC). The method includes receiving an input voltage and creating a plurality of sample voltages from the input voltage. One of the sample voltages is selected and compared to a reference voltage. The power up circuit produces a brown-out signal in response to the step of comparing. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0004]      FIG. 1  is a diagram of a System on a Chip (SoC) showing various power sources that may be used to operate the SoC; 
           [0005]      FIG. 2  is a diagram showing a power up problem that may be encountered with an energy harvesting power supply; 
           [0006]      FIG. 3  is a schematic diagram of a power up circuit of the present invention that may be used with the SoC of  FIG. 1 ; 
           [0007]      FIG. 4  is a diagram showing threshold voltages of a digital-to-analog converter circuit of  FIG. 3 ; 
           [0008]      FIG. 5  is a timing diagram showing operation of the circuit of  FIG. 3 ; and 
           [0009]      FIG. 6  is a timing diagram showing supply voltage variations of the circuit of  FIG. 3  during power up. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0010]    Referring to  FIG. 1 , there is a diagram of a system on a chip (SoC) showing various power sources that may be used to operate the SoC. The SoC  100  may be used in a variety of electronic devices such as laptop computers, tablets, cell phones, and other portable electronic devices. It may include a processor  106 , nonvolatile memory  108 , volatile memory  110 , an input-output circuit  112 , and a transmit-receive circuit  114 . The SoC may further include a power control circuit  102  and a power up circuit  104 . 
         [0011]    The SoC  100  may be powered by a variety of power sources. For example, the SoC may be powered by a regulated power supply having a voltage source  120  and small source resistance  122 . Alternatively, the SoC may be powered by a battery  124  with a corresponding source resistance  126  that depends on the charge of the battery. For example, a battery having a low charge may have an acceptable open circuit voltage but may have an unacceptable output voltage under load conditions. The SoC may also be powered by an energy harvesting circuit having an appropriate energy transducer and charge pump  128 . The energy harvesting circuit has a large source resistance  130  due to the charge pump so that steady state output current depends on the size of each charge packet and the operating frequency of the charge pump. 
         [0012]    In operation, power is applied to SoC  100  from one of the energy sources and the SoC attempts to bootstrap or boot itself. This is generally a process whereby the processor reads basic software such as an operating system from nonvolatile memory. The operating system then loads other software as needed and performs power management functions via power control circuit  102 . For example, the processor may regulate I/O  112 , or XMIT/REC  114  operations based on available power or may enter standby or sleep modes of operation. One of the problems with booting the SoC, however, is that the energy source is generally unknown by the SoC prior to a successful boot operation. Thus, power up circuit  104  must accommodate a variety of energy sources during the boot operation. 
         [0013]    A regulated supply voltage  120  with small source resistance  122 , such as with a USB port or charger, may successfully boot due to available steady state current at an acceptable operating voltage. However, a low battery or energy harvesting system may fail to boot as shown at  FIG. 2 . The diagram of  FIG. 2  illustrates a power-on reset (POR) signal POR_ON  202 , a fixed brown-out detection (BOD) threshold, and minimum (Vmin) and maximum (Vmax) operating supply voltage levels as a function of time during power up. The BOD threshold is used to detect an supply voltage interruption or supply voltage failure so that pending I/O operations may be terminated and the processor may conduct an orderly shutdown of the SoC. During power up, supply voltage level  200  increases above a POR threshold so that signal POR_ON goes high  202 . The high level of POR_ON enables the power up circuit  104 . The supply voltage  200  continues to increase to a level  204  above the BOD threshold and Vmin. At this level, the processor attempts to boot the SoC. An energy source with a high source resistance, however, may require a greater current than the energy source can supply. In this case, the supply voltage decreases  206  to a level below the BOD threshold. The power control circuit  102  then informs the processor  106  of a power supply failure or brown-out. Processor  106  responsively ceases the boot operation and removes the load current. POR_ON is still high, so the power up circuit  104 , power control circuit  102 , and processor  106  resume the power up operation  208 . The supply voltage again increases to a level  210  that is greater than the BOD threshold and Vmin. The processor again attempts to boot the SoC with the same result. This process may continue and a successful boot may never be achieved. Embodiments of the present invention are directed to resolving this potential problem as will be discussed in detail. 
         [0014]    Referring to  FIG. 3 , there is a schematic diagram of a power up circuit of the present invention that may be used with the SoC of  FIG. 1 . The power up circuit is powered by p-channel transistor  330  and capacitor  320  to produce a relatively stable local supply voltage Vpu during power up. The power up circuit includes a digital-to-analog (DAC) converter, a reference generator, a comparator, and a digital counter. Preferred embodiments of these circuits will now be described in detail. However, one of ordinary skill in the art with reference to the instant specification will understand that other suitable design alternatives may also be used without departing from the inventive concept of the present invention. 
         [0015]    The DAC will now be described with reference to  FIGS. 3 and 4 . The DAC includes series-connected resistors R 1  through R 6   300 - 310  and switches  312 - 318 . Resistor R 1   300  is coupled to receive input voltage Vin. Vin may be an external power supply voltage from one of the previously described power supplies ( FIG. 1 ) to power the SoC. Resistor R 6   310  is coupled to power supply voltage Vss or ground as indicated by the small triangle. Series-connected resistors R 1 -R 6  divide voltage Vin to provide a decreasing series of sample voltages. In a preferred embodiment of the present invention, series-connected resistors are desirable to accommodate low voltage operation. However, other circuit elements such as diodes or transistors may be used alone or in combination with the resistors to provide suitable voltage drops. Switches  312 - 316  are arranged to couple one of the sample voltages to a positive input terminal of comparator  320  as determined by bits T[1:0] from counter  326 . 
         [0016]      FIG. 4  illustrates threshold voltages of the DAC as a function of time during power up. POR_ON is an output voltage of power-on reset (POR) circuit  332  in response increasing Vin  400 . The POR circuit may one of various designs known to those of ordinary skill in the art as disclosed by Bhowmik et al. in U.S. patent application Ser. No. 14/140,204, filed Dec. 24, 2013, and incorporated herein by reference in its entirety. The POR_ON signal remains low until Vin reaches a predetermined threshold such as a transistor threshold voltage. The POR_ON signal then goes high and remains approximately equal to Vin  400 . 
         [0017]    Reference voltage Vref is preferably produced by a bandgap reference (BGR) circuit  334 . The BGR circuit may one of various designs known to those of ordinary skill in the art such as a Widlar or Brokaw design. The BGR circuit may also be a low voltage design as disclosed by Banba in U.S. Pat. No. 6,160,391, filed Jul. 27, 1998, and incorporated herein by reference in its entirety. Alternatively, reference voltage Vref may be produced by other reference sources such as a diode drop or transistor threshold voltage as is known by those of ordinary skill in the art. 
         [0018]    The vertical scale of  FIG. 4  also indicates minimum (Vmin) and maximum (Vmax) operating voltages of the SoC as well as Vin  400  threshold voltages. Threshold voltage θf is a falling BOD threshold generated at the junction of resistors R 1  and R 2 . Threshold voltage θr 1  is a first rising BOD threshold generated at the junction of resistors R 2  and R 3 . Threshold voltage θr 2  is a second rising BOD threshold generated at the junction of resistors R 3  and R 4 . Threshold voltage θr 3  is a third rising BOD threshold generated at the junction of resistors R 4  and R 5 . Threshold voltage θr 4  is a fourth rising BOD threshold generated at the junction of resistors R 5  and R 6 . 
         [0019]    During power up of the SoC, a rising level of Vin  400  generates corresponding rising sample voltages  402 - 410 . For example, when input voltage Vin is equal to threshold voltage θf, sample voltage  402  is equal to Vref. Likewise, when input voltage Vin is equal to threshold voltage θr 1 , sample voltage  404  is equal to Vref. Threshold voltage θf is preferably slightly less than Vmin and indicates a brown-out or power fail condition to power control circuit  102  ( FIG. 1 ) when Vin falls below θf. During normal circuit operation, threshold voltage θr 1  is preferably slightly greater than Vmin and indicates there is no brown-out or power fail condition to power control circuit  102  ( FIG. 1 ) when Vin rises above θr 1 . Vin  400  is equal to threshold values θr 2  through θr 4  when respective sample voltages  406 - 410  equal reference voltage Vref. 
         [0020]    Switches  312  through  318  are arranged to apply a selected sample voltage to the positive input terminal of comparator  320 . The switches may be bipolar transistors, metal oxide semiconductor (MOS) transistors, complementary MOS (CMOS) transmission gates, logic gates, or other suitable switching means. The negative input terminal is coupled to receive reference voltage Vref from BGR circuit  334 . The output terminal of comparator  320  is coupled to one input terminal of AND gate  322 . The other input terminal of AND gate  322  is coupled to receive signal VBG_ON. VBG_ON is produced by BGR circuit  334  to indicate reference voltage Vref has achieved a stable reference value. When the output of comparator  320  and VBG_ON are both high, AND gate  322  produces a high level of signal /BOD to indicate there is no brown-out or power fail condition. Alternatively, an active low level of /BOD indicates Vin is less than threshold θf, and the corresponding sample voltage at the junction of resistors R 1  and R 2  is less than Vref. Switches  312  through  316  are controlled by bits T[1:0] from counter  326 . Counter  326  is initially cleared to T[1:0]=00 by a low level of either POR_ON or /BOOT. Here, /BOOT is an active low signal to indicate that the SoC has successfully booted. Alternatively, a high level of /BOOT indicates that the SoC has not successfully booted. Counter  326  is incremented by a low-to-high transition of /BOD as will be explained in detail. 
         [0021]    Operation of the power up circuit of  FIG. 3  will now be explained with reference to the timing diagrams of  FIGS. 5 and 6 . Times t 1  through t 9  are the same for  FIGS. 5 and 6  during the power up operation. Initially, Vin is 0 V, switches  312  through  318  are in their 0 position, and counter  326  is initialized to T[1:0]=00. Vin  600  rises and charges capacitor  328  through p-channel transistor  330  to provide local supply voltage Vpu. At time t 1 , Vin is sufficiently high to activate a high level of POR_ON followed closely by a high level of VBG_ON. The high level of VBG_ON enables and gate  322 , but Vin is still below threshold θr 1 , so /BOD remains low. Thus, switch  318  remains in its 0 position. 
         [0022]    At time t 2 , Vin crosses threshold θr 1   604  and produces a sample voltage at the junction of resistors R 2  and R 3  that is greater than Vref. This sample voltage is applied to the positive input terminal of comparator  320  through switches  312 ,  316 , and  318  and produces a high level output. The high level output is applied to AND gate  322  to produce a high level of /BOD. The high level of /BOD moves switch  318  to its 1 position and signals power control circuit  102  to boot the SoC. The low-to-high transition of /BOD also increments counter  326  to produce T[1:0]=01 and move switches  312  and  314  to their respective 1 positions. The SoC begins the boot process, but the power supply series resistance is too high to complete the process. Thus, Vin falls along curve  606 . 
         [0023]    At time t 3 , Vin crosses threshold θf and produces a low level output from comparator  320 . The low level output produces a low level of /BOD and moves switch  318  to its 0 position. The low level of /BOD indicates a brown-out or power fail to power control circuit  102 , and the boot operation is terminated. With the resulting reduction in load current, Vin rises along curve  608 . 
         [0024]    At time t 4 , Vin crosses threshold θr 2   610  and produces a sample voltage at the junction of resistors R 3  and R 4  that is greater than Vref. This sample voltage is applied to the positive input terminal of comparator  320  through switches  312 ,  316 , and  318  and produces a high level output. The high level output is applied to AND gate  322  to produce a high level of /BOD. The high level of BOD moves switch  318  to its 1 position and signals power control circuit  102  to boot the SoC. The low-to-high transition of /BOD also increments counter  326  to produce T[1:0]=10 and moves switches  312  and  314  to their respective 0 positions and switch  316  to its 1 position. The SoC begins the boot process, but the power supply series resistance is too high to complete the process. Thus, Vin falls along curve  612 . 
         [0025]    At time t 5 , Vin again crosses threshold θf and produces a low level output from comparator  320 . The low level output produces a low level of /BOD and moves switch  318  to its 0 position. The low level of /BOD indicates a brown-out or power fail to power control circuit  102 , and the boot operation is terminated. With the resulting reduction in load current, Vin rises along curve  614 . 
         [0026]    At time t 6 , Vin crosses threshold θr 3   618  and produces a sample voltage at the junction of resistors R 4  and R 5  that is greater than Vref. This sample voltage is applied to the positive input terminal of comparator  320  through switches  314 ,  316 , and  318  and produces a high level output. The high level output is applied to AND gate  322  to produce a high level of /BOD. The high level of /BOD moves switch  318  to its 1 position and signals power control circuit  102  to boot the SoC. The low-to-high transition of /BOD also increments counter  326  to produce T[1:0]=11 and moves switches  312  and  314  to their respective 1 positions. The SoC begins the boot process, but the power supply series resistance is too high to complete the process. Thus, Vin falls along curve  620 . 
         [0027]    At time t 7 , Vin again crosses threshold θf and produces a low level output from comparator  320 . The low level output produces a low level of /BOD and moves switch  318  to its 0 position. The low level of /BOD indicates a brown-out or power fail to power control circuit  102 , and the boot operation is terminated. With the resulting reduction in load current, Vin rises along curve  622 . 
         [0028]    At time t 8 , Vin crosses threshold θr 4   624  and produces a sample voltage at the junction of resistors R 5  and R 6  that is greater than Vref. This sample voltage is applied to the positive input terminal of comparator  320  through switches  314 ,  316 , and  318  and produces a high level output. The high level output is applied to AND gate  322  to produce a high level of /BOD. The high level of /BOD moves switch  318  to its 1 position and signals power control circuit  102  to boot the SoC. The low-to-high transition of /BOD also increments counter  326  to produce T[1:0]=00 and moves switches  312  through  316  to their respective 0 positions. The SoC once again begins the boot process, and Vin decreases along curve  628  to Vmin. The boot process is completed even with the high power supply series resistance by using charge stored in the SoC system capacitance. Once the boot operation is complete, the SoC controls system operation and regulates power supply loading. Thus, Vin rises along curve  630  to an operational level. 
         [0029]    At time t 9 , the power control circuit  102  produces a low level /BOOT signal to indicate the boot operation is complete. The low level of /BOOT is applied to one input of NAND gate  324  to produce a high level output signal. The high level output signal assures that counter  326  is reset to T[1:0]=00 even if the boot operation is complete before Vin reaches threshold θr 4 . Thus, switches  312  through  318  are all reset to their respective 0 positions. 
         [0030]    Embodiments of the present invention offer several advantages over the prior art. First, power up problems as discussed with regard to  FIG. 2  related to power supplies with unknown source resistance are greatly reduced or eliminated. Second, existing system capacitance of the SoC is used to provide sufficient load current to boot the SoC. No additional power supply constraints are imposed on the SoC. Third, the power up circuit employs an incremental BOD rising threshold voltage to incrementally increase available charge stored on the system capacitance until a successful boot is completed. It would not be possible to initially set the BOD rising threshold high, since a low power supply voltage within specified limits but below the high BOD rising threshold would never permit the SoC to boot. Fourth, a separate BOD falling threshold is used to detect a brown-out or power fail condition. This permits an orderly shutdown of the SoC in order to terminate pending I/O requests and reject new I/O requests. Finally, the present invention is equally compatible with wired power supplies, low battery power supplies, and energy harvesting power supplies. 
         [0031]    Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling with the inventive scope as defined by the following claims. For example, although a preferred embodiment of the present invention discloses a variable BOD rising threshold responsive to a two-bit counter, any number of bits may be used. The BOD rising threshold may be determined by a one-bit counter or flip-flop for simplicity or by a greater number of counter bits for greater threshold resolution. Other combinations will be readily apparent to one of ordinary skill in the art having access to the instant specification.