Abstract:
A method and apparatus for enhancing noise tolerance in dynamic Silicon-On-Insulator (SOI) logic gates improves the performance of dynamic gates using SOI technology. In particular implementations of logic, the logic inputs can be used to enable a pull-up chain constructed from a plurality of transistors. This pull-up chain holds the preset voltage on the summing node of the dynamic logic gate while the logic inputs are in a combination where parasitic bipolar transistors in the input logic chains conduct. The pull-up chain prevents spurious operation of the logic gate due to the conduction of the parasitic bipolar transistors. The pull-up also prevents spurious operation due to charge sharing that occurs when a device in the logic chain is enabled while another device is disabled. The charge sharing occurs due to charging the diffusion capacitance of the device which is disabled.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to digital integrated circuits, and more particularly to dynamic logic circuits implemented in Silicon-On-Insulator (SOI) technology with enhancements that improve noise tolerance by reducing bipolar current effects and charge sharing effects within the circuits. 
     2. Description of the Related Art 
     Dynamic logic is widely used in integrated circuits, especially Very Large Scale Integrated (VLSI) circuits. Because dynamic logic uses comparably less transistors per gate than static logic, circuit densities are increased, making dynamic logic desirable for use in VLSI circuits such as microprocessors and memories. 
     Specifically, Complementary Metal Oxide Semiconductor (CMOS) technology has been the technology of choice for low power designs, because the bulk of the power dissipation in these circuits occurs when the transistors are switching. This characteristic has made CMOS implementations preferable for low power static designs, such as microprocessors and other components for use in notebook computers, and recently for desktops in keeping with the trend in “green” desktop computer design. CMOS technology uses P-channel and N-channel MOS devices in a static complementary configuration to form logic gates. 
     Dynamic gates are not typically complementary designs, as the P-channel devices and the N-channel devices are used to perform different functions in the gate. One transistor type is used to pre-charge an evaluation node, and the complementary type is use to discharge the node in response to logic inputs. 
     Silicon-On-Insulator (SOI) technology is a relatively new technology having enhanced low power characteristics, which make it ideal for implementing low power dynamic gates. Additionally, parasitic substrate capacitance is decreased, enhancing the switching speed of transistors implemented in SOI. Rather than embedding the channel material in a semiconductor substrate, the channel material is formed on top of an oxide layer, decreasing leakage resistance and parasitic capacitance. Devices are isolated by Shallow Trench Insulation (STI), rather than the substrate, further reducing capacitive effects and noise coupling from other devices. 
     There is a drawback associated with transistors formed in SOI technology, however. A parasitic bipolar transistor exists in both non-insulated MOS implementations and the SOI implementation. The bipolar transistor has an emitter and collector formed by the doped regions at the two ends of the channel (N+ material for an N-channel MOS transistor). The base of the transistor is formed by the substrate. In non-insulated MOS technology, the substrate is typically biased so that the transistor will always be off. For N-channel material, this bias is accomplished by connecting the substrate to the lowest negative potential in the circuit. In SOI implementations, because the channel material is deposited on an insulator, the base of the parasitic bipolar transistor (formed by the body of the MOS transistor) has no electrical connection. Therefore, when the doped material at the ends of the channel change voltage, the parasitic transistor may turn on until its base capacitance is charged. The conduction is produced by the forward bias of the emitter or collector (formed by the end of the channel) to the base (formed by the un-doped region in the middle of the channel). This is known as the “bipolar effect”, and can cause malfunction of dynamic gates implemented in SOI technology. The bipolar effect can cause glitches that discharge the evaluation node when the input state of a transistor coupled to that node changes in such a way that the parasitic bipolar transistor conducts momentarily. 
     Charge sharing is a problem common to both non-insulated MOS implementations and SOI implementations. When two or more transistors are connected in a chain so that both must conduct to discharge the summing node of a dynamic logic gate, if a device farther away from the summing node is in a non-conducting state and a device closer to the summing node is enabled, the preset voltage on the summing node can be dissipated due to charging the diffusion capacitance of the farther device. 
     The bipolar effect and the charge sharing effect decrease the noise immunity of a dynamic logic gate, as well as increasing the sensitivity to coupling from other input signals and sub-threshold variations in voltages at the gate&#39;s logic inputs. 
     It would therefore be desirable to implement dynamic logic circuits in such a way that the bipolar effect and charge sharing effect can be reduced or eliminated. 
     SUMMARY OF THE INVENTION 
     The objective of enhancing noise immunity in Silicon-On-Insulator (SOI) dynamic logic gates is accomplished in a dynamic logic gate that includes a pre-charge transistor, one or more logic ladders having multiple logic inputs and a pull-up ladder for holding a summing node at a pre-charge state. The pull-up ladder has multiple transistors and the gates of the transistors are each coupled to a unique logic input. The logic ladder and pull-up ladder are both coupled to the summing node of the logic gate. 
     The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1A is a pictorial diagram depicting the structure of a MOS transistor formed on a semiconductor substrate; 
     FIG. 1B is a pictorial diagram depicting the structure of a MOS transistor formed on an insulating substrate; 
     FIG. 2 is a schematic diagram of a prior art half sum circuit; 
     FIG. 3A is a schematic diagram of a half sum circuit in accordance with a preferred embodiment of the invention; and 
     FIGS. 3B,  3 C and  3 D are schematic diagrams of a half sum adder circuit in accordance with alternative embodiments of the invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     With reference now to the figures and in particular with reference to FIG. 1A, there is depicted a Metal Oxide Semiconductor (MOS) transistor  10  on a semiconductor substrate  14 . The doped regions  18  provide conduction barriers when the potential on a gate  16  is such that no field is developed in a channel  13 . Substrate  14  is connected to the point of lowest potential in the circuit (in this case ground). This substrate connection serves as a bias to prevent conduction of a parasitic bipolar transistor  12  that is formed by doped regions  18  and a substrate  13 . 
     Referring now to FIG. 1B, there is depicted a MOS transistor  20 , formed on an insulating substrate  21 . Within MOS transistor  20 , a parasitic bipolar transistor  22  is formed by a channel  24  and doped regions  28 . Since there is no bias connection to channel  24 , the base of parasitic bipolar transistor  22  is effectively floating. If any of the doped regions  28  that form the source and drain connections to MOS transistor  20  are pulled low, the emitter-base or collector-base junction of parasitic bipolar transistor  22  will conduct momentarily, causing current to flow from the opposite doped region  28 . 
     Referring now to FIG. 2 a prior art half-sum circuit is depicted. Logic inputs X and Y are supplied to a first logic input ladder formed by transistors N 0  and N 1 , and a second logic input ladder formed by transistors N 2  and N 3 , respectively. The inversion of input Y by inverter I 0  and input X by I 1  provide an exclusive-NOR (XNOR) logic function at Node 0 , in that one of the two logic input chains will conduct if inputs X and Y are in different logic states. Inverter I 2  converts the XNOR result at Node 0  to an XOR result. Half-latch device P 3  holds Node 0  in a logic high state after it is preset by pre-charge transistor PO when CLK is set to a logic low state. Node 0  will be held in the logic high state until one of the logic input ladders conducts. Foot device N 4  provides that the logic input ladders will not conduct when CLK is in the logic low state. This would prevent Node 0  from being pre-charged, and cause excessive current to be drawn during the pre-charge phase. 
     In this circuit, when logic input Y is switched from a logic high to a logic low while logic input X is in a logic low state and Node 1  is charged, parasitic bipolar transistor Q 0  will conduct momentarily, causing current to be drawn from Node 0 . Due to this conduction and further aggravating the problem if noise occurs at input X simultaneously, Node 0  could evaluate to an erroneous logic low state, causing improper operation of the logic gate. Similarly, when logic input Y is in a logic low state and logic input X transitions from a logic high state to a logic low state, device N 2  will turn on, causing current to be drawn from Node 0  until the potential at Node 2  is equal to the potential at Node 0 . This charge sharing effect can cause the pre-charge voltage at Node 0  to be dissipated, just as in the case of the bipolar effect. 
     Improvements have been made in the dynamic logic circuits to obviate mis-operation of the logic caused by the bipolar effect. The techniques disclosed in co-pending application Ser. No. 09/382,760 “METHOD AND APPARATUS FOR REDUCING BIPOLAR CURRENT EFFECTS IN SILICON-ON-INSULATOR (SOI) DYNAMIC CIRCUITS” could be used, but for the type of circuit depicted in FIG. 2, an alternative solution is preferable. Because inverters I 0  and I 1  will effectively filter noise at their inputs, it is not necessary to prevent the bipolar effect for all state changes of the logic inputs than can create bipolar effects, but only for those state changes where the transistor exhibiting the bipolar effect is coupled to a noisy circuit, such as a long line from another circuit. Therefore, transistor N 2  does not have to be “treated” for the bipolar effect, because its gate is coupled to an inverter located proximally in the circuit. By arranging the logic input ladders so that the bipolar effect occurs when the logic signals occur in a particular combination (in our exemplary embodiments, when both logic signals are in a logic low state), a series-connected transistor chain can be used as a pull-up to prevent the summing node from being erroneously discharged, with the inputs of the transistors in the pull-up chain coupled to the logic inputs of the gate. This represents an improvement over the technique disclosed in the above-referenced patent application, as fewer devices are required for particular types of gates, such as the half-sum circuit. 
     Referring now to FIG. 3A, an improved half-sum circuit is depicted, having increased noise tolerance due to reduction of the bipolar effect and charge sharing effect. Transistors P 11  and P 12  form a pull-up ladder, wherein the pre-charge at Node 10  will be maintained by the pull-up ladder when logic inputs X and Y are in a logic low state. This pull-up ladder “assists” the half-latch formed by transistor P 13  when one of inputs X or Y transitions to a low state while the other is at a logic low state or simultaneously transitions to a low state. When logic input X is low and logic input Y makes a transition to a low state, parasitic bipolar transistor Q 0  may momentarily conduct if Node 11  is charged. Without the pull-up chain, Node 10  might be erroneously pulled low by conduction through the collector of parasitic bipolar transistor Q 0 . Instead, transistors Pll and P 12  supply enough current to prevent the bipolar effect from erroneously discharging Node 10 . When logic input Y is low and logic input X makes a transition to a low state, the diffusion capacitance of N 13  must be charged. Transistors P 11  and P 12  also supply enough current to prevent this charge-sharing effect from erroneously discharging Node 10 . 
     Referring now to FIG. 3B, an alternative embodiment of the improved half-sum added is depicted. In this embodiment, for the high to low transition of input X while input Y is low, the logic input ladder formed by transistors N 22  and N 23  may exhibit charge-sharing, as transistor N 22  begins to conduct. The diffusion capacitance of transistor N 23  is then charged by the conduction of transistor N 22 , if the voltage at Node 21  was at a low level prior to the transition. Similarly, the input ladder formed by transistors N 20  and N 21  exhibits the charge-sharing effect for the high to low transition of input Y while input X is low if Node 21  is at a low level. For these logic states, the pull-up ladder formed by transistors P 20  and P 21  will conduct, preventing the charge-sharing effect from discharging Node 20 . Referring now to FIG. 3C, a second alternative embodiment of the half-sum circuit is depicted. In this embodiment, a bipolar effect may occur in the input logic ladder formed by transistors N 30  and N 31  when input X transitions to a logic high state while input Y is at a logic low and a charge-sharing effect can occur when input Y transitions to a logic high while X is in a logic low state. The operation of the pull-up ladder formed by transistors P 31  and P 32  will hold Node 30  high, preventing the charge-sharing effect from dissipating the precharge voltage. In this circuit, the input to transistor P 32  is coupled to inverter I 30 , so that the pull-up ladder will operate when input Y is in a logic high state. 
     Referring now to FIG. 3D, a half-sum circuit is depicted wherein both input ladders may exhibit a bipolar effect. The input ladder formed by transistors N 40  and N 41  will exhibit the effect when input Y is at a logic low and input X transitions to a logic low. Similarly, when input X is at a logic low and input Y transitions to a logic low, the bipolar effect may be exhibited by the input logic ladder formed by transistors N 42  and N 43 . As in the prior described circuits, the pull-up ladder formed by transistors P 41  and P 42  will act to prevent the bipolar effect from dissipating the pre-charge voltage on Node 40 . 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, the N-channel devices forming the logic ladders could be replaced by P-channel devices, while the P-channel devices forming the pull-up ladder are replaced with a pull-down ladder formed from N-channel devices, essentially reversing the voltage level operation of the circuit without changing the essential structure or method steps that characterize the invention.