Abstract:
A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application and claims priority to U.S. utility application Ser. No. 12/846763, filed Jul. 29, 2010, entitled “Semiconductor Chip Layout,” which application is incorporated by reference herein in its entirely. 
     
    
     BACKGROUND 
       [0002]    Current memory circuits that use double data rate (DDR) and quadruple data rate (QDR) access schemes have separate address, write data, read data and status pins. These access schemes require high frequency data transmission links that provide low bit error rate (BER), high bandwidth and low on-chip latency. Bandwidth is the amount of information exchanged during read and write operations. Latency is the time lapsed between an event in an input signal and a corresponding event in an output signal that results from the event in the input signal. For example, in a memory circuit latency is the time lapsed between the receipt of a ‘Read’ command at an input pin of the memory circuit and the transmission of the corresponding read data to the output pins of the memory circuit. 
         [0003]    In a device that has a serial transmission link one or more serializer-deserializer (SERDES) circuits convert data packets between serial and parallel formats. It is common practice to place the SERDES circuits and other associated logic components along the periphery of the silicon chip. Such architecture results in a wide spread in latencies in the silicon, depending on the distance between the SERDES and the specific functional block that is the source or the destination of the data. Thus, worst case timing latency is determined by the longest path set by the I/O which is the furthest away from any one device resource. A typical layout of I/O at the periphery would result in the worst case path from one corner of the die to the opposite corner. The resulting distance that an input signal must traverse could be the width plus the height of the die. 
         [0004]    Error rates are expected to increase for high speed data links. Many circuits have a cyclic redundancy check (CRC) circuit to perform error checking on data packets. Error checking is performed across the entire data packet, which may be striped across multiple data lines to increase bandwidth and to reduce latency. However, such an approach requires that multiple data lines converge into the CRC circuit to allow error checking, thus adding to the length of the traces that signals must traverse for an operation. 
         [0005]    Moreover, heaviest packet traffic in a device typically occurs as communication among functional blocks formed in or on the silicon substrate. Data lines formed in or on the silicon substrate are dimensionally constrained, thus representing significant capacitive and resistive loads to the paths the signals must traverse. In addition, communication lines in or on silicon further need to circumvent the functional blocks that create barriers to signal routing, adding to the lengths of the communication lines. As a result, on die packet traffic routed through communication lines on a silicon substrate with a significant density of functional blocks will experience increased latencies. 
         [0006]    In an application using a SERDES circuit, placement of a power pin next to a data pin in a package substrate complicates “signal escape” to an external component. Routing signals in a printed circuit board from a signal pad at the center of the chip through a “picket fence” of power pins exposes the data signal on the signal pad to interference, cross-talk, and distortion. Thus packages where the signal pins are toward the outer edges of the packet reduce the picket fence effect. To overcome the above problem, it is customary to place I/O signals at the edge of the silicon substrate. However such placement can negatively impact the overall latency of the circuit. Package pin-out configuration is a concern in integrated circuit design. 
         [0007]    Tx/Rx differential pairs are typically grouped closely together in high speed communication systems. Each Tx transmitter includes a transmit channel that conveys read data and status information out of a package. Each Rx receiver includes a receive channel that receives address, control and write data from outside of the package. In networking devices, the proximity of Tx and Rx channels can result in data crosstalk and an increase in bit flips. 
         [0008]    Bandwidth becomes more significant when a SERDES block is combined with a high speed memory block. Due to the proximate locations of Tx to Rx, a conventional systems have a significantly limited signal line density, which adversely affects the available bandwidth. In high speed communication systems, it is increasingly critical to have a significant amount of line/signal density for improving the device bandwidth. 
         [0009]    U.S. Pat. No. 7,405,946 to Hall et al. (“Hall”) separates transmitter contacts from receiver contacts in a high speed interface pattern. However, Tx data channels in Hall&#39;s pattern must be positioned parallel to Rx data channels to convey data from the transmitter out to the host. Parallel Tx/Rx channels tend to degrade data signals and increase error rates. In Hall&#39;s Tx/Rx pattern, the data line transporting a high speed Tx signal must cross over an Rx data line before exiting the PC board. Such proximity of Rx contacts to Tx contacts contributes to noise coupling between Tx and Rx signals. Thus, Hall does not resolve the problem of Inter Signal Interference (ISI) for high speed data links. 
         [0010]    Accordingly, there is a need for an IC device layout that takes into account the routing delay for high speed data signals on a PCB or a SOC. In addition, a need exists for simplified data path routing for high speed networking devices to minimize the routing length through the silicon die. Further, a need exists for reducing the amount of interference between Rx and Tx signals while easing printed circuit board layout. 
       SUMMARY 
       [0011]    The present invention provides a layout for a semiconductor device coupled to a second device. To optimize the high speed transmission rates in the present invention, at least two functional circuit blocks (“IP cores”) are symmetrically located with respect to a central axis on a semiconductor die; each core being accessible via a plurality of Tx and Rx data lines. A serial interface is centered on the die between the two IP cores. The serial interface includes multiple ports which serve as nodes coupled to various data lines. In particular, the serial interface includes multiple transmitter ports and multiple receiver ports. The ports are coupled together by Tx data lines and Rx data lines. The die itself has multiple metal layers and is encapsulated in a package having multiple routing layers. 
         [0012]    The present invention is also directed to a semiconductor device coupled to a second device, where the semiconductor device contains a die divided into two partitions. An IP core is contained in each partition. Further, multiple receiver terminals are located in the first partition of the die, and multiple transmitter terminals are located in the second partition of the die. A serial interface is further incorporated on the die and is positioned adjacent to one of the IP cores, wherein the serial interface includes transmitter ports and receiver ports. The IC device also includes Tx data lines, originating from respective Tx ports wherein each Tx port serializes and transmits a serial data signal for output on a Tx data line to one of said IP cores; and Rx data lines, originating from respective receiver ports, wherein each receiver port receives and deserializes a serial data signal for output on an Rx data line to one of said IP cores. 
         [0013]    Another embodiment of the invention is directed to a stacked die that includes multiple dies attached together. At least one die in the stack assembly has Rx terminals in a first partition of the die and Tx terminals in a second partition of the die. At least one of the dies in the stack has a serial interface in a central region of the chip layout. Thus, it is not necessary for all the dies in the stack assembly to have the same chip layout as the die of the present invention. 
         [0014]    The invention is also directed to a stacked die assembly that operates with reduced power, and propagation delay. By centrally locating the SERDES interface on the top surface of the die the driving distance is reduced by approximately one half. The reduced driving distance correlated to the layout of the invention reduces the system latency as well as power. 
         [0015]    Other features of the invention will be described in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  illustrates a device layout that includes a memory block and a SERDES interface; 
           [0017]      FIG. 2  illustrates a device layout that includes multiple functional blocks and a SERDES interface; 
           [0018]      FIG. 3A  illustrates a package layout for the embodiment of  FIG. 1 ; 
           [0019]      FIG. 3B  illustrates the package layout of  FIG. 3A  with conductor traces; 
           [0020]      FIG. 4A  illustrates a conventional routing pattern for two ICs mounted on a printed circuit board; 
           [0021]      FIG. 4B  illustrates the extensive crossover problem that occurs when two conventional chips are positioned next to each other; 
           [0022]      FIG. 5A  illustrates a routing pattern for two BE devices mounted on a printed circuit board; 
           [0023]      FIG. 5B  illustrates an alternative routing pattern for two BE devices mounted on a printed circuit board; 
           [0024]      FIG. 6A  illustrates a routing pattern of a BE device coupled to a conventional device on a printed circuit board with a minimal amount of crossover; 
           [0025]      FIG. 6B  illustrates an alternative routing pattern for the two devices of  FIG. 6A ; 
           [0026]      FIG. 7  illustrates a cross section of a semiconductor package of the present invention; and 
           [0027]      FIG. 8  illustrates a cross section of a stacked die assembly in accordance with one embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    The present invention balances the access time and propagation delays for a signal entering a die across all physical corners of the silicon. This is achieved by providing a SERDES interface in the center of the die.  FIG. 1  illustrates a die layout of the present invention divided by an axis  112  into an upper partition  50  and a lower partition  52 . Each partition of the die layout contains an IP core  10 A,  10 B that is either a memory array, programmable logic array or network processor block. The memory core  10 A,  10 B may be either an SRAM, DRAM, 1T-SRAM or Flash. A serial interface  115  is positioned on axis  112  between the two IP cores  10 A,  10 B with serial interface  115  having Receiver/Transmitter (Rx/Tx) units  122   a,    124   a  /  122   b,    124   b , respectively. In a preferred embodiment, when partitions  50 ,  52  have an equal area, axis  112  is centrally located on semiconductor die  400 . However, in other embodiments, axis  112  can be shifted so that the SERDES interface is positioned off center on die surface  400 . The serial interface contains one or more SERDES blocks. The semiconductor die of this invention has multiple metal layers  190 , upon which are various circuit patterns. 
         [0029]    It is not necessary for the IP cores of the present invention to have the same function or to be limited to memory blocks. In all embodiments, at least one IP core (functional block) is located in each partition. In one embodiment, each partition may constitute an equivalent half, that is, each partition may have the same area. However, it is not necessary that the partitions of the present invention have the same area as illustrated in  FIG. 1 . 
         [0030]      FIG. 2  illustrates an alternate chip layout where partition  50  has a smaller area than partition  52 . In  FIG. 2  more than two IP cores are arranged on die  275 . In the upper partition  50  of substrate  275  is mounted memory core  10 A, logic core  35 A and network processor  25 A. The lower partition  52  of substrate  275  contains memory core  10 B, logic core  35 B, and network processor  25 B. The layout of  FIG. 2  also includes a memory access controller and/or error detection software  40 . Each pair of IP cores is preferably symmetrically located about axis  112 . Along axis  112  is positioned a SERDES interface composed of two SERDES blocks  115 . 
         [0031]    Each SERDES block  115  contains Rx/Tx unit  122   a ,  124   a  /  122   b ,  124   b , respectively. Each Tx port in Tx unit  122   b ,  124   b  contains a differential pair of transmitters, the transmitter pairs are grouped with the transmitters of the same Tx unit. Each Rx port in Rx unit  122   a ,  124   a  contains a differential pair of receivers that are isolated from the Tx ports in Tx unit  122   b ,  124   b . In addition, each Tx port and each Rx port has clocking functionality to implement a PLL circuitry. Although 16 Tx ports and 16 Rx ports are shown, the present invention is also applicable to a SERDES block that has a different number of Tx/Rx ports. Preferably, the Rx ports in Rx units  122   a ,  124   a  occupy a portion of the upper partition  50  of the die layout and the Tx ports in Tx unit  122   b ,  124   b  occupy a lower partition  52  of the die layout. By placing the SERDES block in approximately the center of the die, the distance of the data access from opposite edges of the die is more uniform than in the prior art. As a result, the layout of the present invention provides a symmetrical or nearly symmetrical point of entry for each data signal. 
         [0032]      FIG. 3A  illustrates a more detailed layout of the invention. Elements  316 - 1  to  316 - 16  correspond to Rx terminals, whereas elements  315 - 1  to  315 - 16  correspond to Tx terminals. The Tx terminals are separated from the Rx terminals. Terminals refer to nodes on the edge of a package that are coupled to data lines. In addition, the present invention provides connections to Rx/Tx ports inside a serial interface on the die. The ports are equidistant from the four corners of the die substrate to a central region on the die. 
         [0033]      FIG. 3A  shows the layout of package substrate  300  in an integrated circuit memory device according to some embodiments of the present invention. Package substrate  300  may be divided into a number of divisions  301  forming an M×N matrix. According to the embodiment of  FIG. 3A , there are M (=22)×N (=22) divisions  301  in package substrate  300 . Other values for M and N may be used instead of a 22×22 matrix. Further, the values of M and N need not be the same. Divisions  301  of package substrate  300  may overlap different area portions of die substrate  400  which may include functional components (“blocks”) formed in circuit substrate  400 . For example, the divisions in the shaded portion  320  of  FIG. 3A  may overlap various functional blocks formed in die substrate  400 . Such functional blocks may include logic and memory circuits, as well as memory arrays  10 A and  10 B, coupled to SERDES circuits  115 , and CRC circuit  40  of  FIG. 1 , which shows a layout of die substrate  400 . While the embodiment depicted in  FIG. 1  includes two memory arrays and two SERDES circuits, some embodiments of the present invention may use a different number of memory arrays and SERDES circuits. The divisions  301  in portion  321  ( 322 ) of package substrate  300  overlap first (second) SERDES circuit  115 . The divisions  301  in portion  310  of package substrate  300  overlap CRC circuit  40  ( FIG. 1 ), according to the embodiment depicted in  FIG. 3A . Specifically, a given division  301  in package substrate  300  may overlap more than one functional component formed in die substrate  400 . Also within shaded portion  320 , divisions  344 - 1   a  ( 344 - 2   a ) and  344 - 1   b  ( 344 - 2   b ) may be coupled to conducting balls providing a signal or power to a sensitive circuit like a PLL (phase-locked loop) circuit in substrate  400 . Portion  321  ( 322 ) may include receiver portion  321   a  ( 322   a ) overlapping receiver unit  122   a  ( 124   a ) in SERDES  115  of  FIG. 1 . Portion  321  ( 322 ) may also include transmitter portion  321   b  ( 322   b ) overlapping transmitter unit  122   b  ( 124   b ) in SERDES  115  of  FIG. 1 . Outside and along the edges of shaded portion  320  of package substrate  300 , according to the embodiment shown in  FIG. 3A , portions  315 - 1  to  315 - 16  and portions  316 - 1  to  316 - 16  may be provided. Portions  315 - 1  to  315 - 16  overlap divisions  301  of package substrate  300  that may be coupled to Tx data channels  550 - 1  to  550 - 16  of package substrate  300  (see,  FIG. 3B ) through conducting balls  215 , according to some embodiments of the present invention. Portions  316 - 1  to  316 - 16  overlap divisions  301  of package substrate  300  coupled to Rx data channels  552 - 1  to  552 - 16  (see,  FIG. 3B ) through conducting balls  216 . Some of the divisions (e.g.  351  and  352 ) in package substrate  300  may be coupled to a biasing voltage for die (circuit) substrate  400 , associated with a ground voltage provided through divisions  361  and  362 , respectively. 
         [0034]    Portion  375 - 1  ( 375 - 2 ) may be used to provide an extra Tx data channel  551 - 1  ( 551 - 2 ) (see,  FIG. 3B ) to integrated circuit  100 . Likewise, portions  376 - 1  ( 376 - 2 ) overlap divisions  301  in package substrate  300  that may provide an extra Rx data channel  553 - 1  ( 553 - 2 ) (see,  FIG. 3B ) to integrated circuit  100 . 
         [0035]      FIG. 3B  is a layout of package substrate  300  showing the positions of conducting balls  215 - 1   a ,  215 - 1   b  to  215 - 15   a ,  215 - 15   b ,  216 - 1   a ,  216 - 1   b  to  216 - 15   a ,  216 - 15   b , coupled to package substrate  300 . Also shown are conducting balls  515 - 1   a ,  515 - 1   b ,  515 - 2   a ,  515 - 2   b ,  516 - 1   a , and  516 - 1   b , and  516 - 2   a ,  516 - 2   b  coupled to package substrate  300 . Also shown in  FIG. 3B  are Rx data lines  552 - 1  to  552 - 16 ,  553 - 1  and  553 - 2 , and Tx data lines  550 - 1  to  550 - 16 ,  551 - 1  and  551 - 2  in package substrate  300 , according to some embodiments of the present invention. By using Tx/Rx data lines in package substrate  300  as shown in  FIG. 3B , the latency of a memory array for a data line in a package substrate having a length of approximately 8-10 mm according to the embodiment depicted in  FIG. 3B  may be less than 100 picoseconds, and more preferably, the latency is less than 70 picoseconds (ps) or less within the package substrate. By comparison, the latency for a Tx/Rx data line in the prior art carrying data signals from one edge of a die to the opposite edge of the die within a silicon substrate may have a latency ten times greater than the present invention, or about 2.4 ns. 
         [0036]    In the present invention, a Tx signal will take longer to travel from bump  30  in the serial interface  322   b  through the die ( 400  of  FIG. 1 ) to the die edge than to travel from serial interface  322   b  through the package substrate  300  and out to ball  215 - 10   a, b  (which is the edge of the package). In other words, it is faster in the present invention to route a signal through the package than to transport a signal from the serial interface  322   b  through the die ( 400  of  FIG. 1 ) out to the edge of the silicon die, and then to travel through the package from the die edge to ball  215 - 10   a, b . Similarly, it is faster to route an Rx signal from the package edge at  216 - 9   a, b  through the package substrate  300  to the bump  37  in the serial interface  322   a  than to travel from ball  216 - 9   a, b  to the die edge and then through the die ( 400  of  FIG. 1 ) to bump  37 . 
         [0037]    Conducting balls  216 - 1   a,b  to  216 - 16   a,b  are coupled to Rx data lines  552 - 1  to  552 - 16 ; conducting balls  516 - 1   a,b  are coupled to Rx data line  553 - 1 ; and conducting balls  516 - 2   a ,  516 - 2   b  are coupled to Rx data line  553 - 2 . Conducting balls  215 - 1   a ,  215 - 1   b  to  215 - 16   a ,  215 - 16   b  are coupled to Tx data lines  550 - 1  to  550 - 16 ; conducting balls  515 - 1   a ,  515 - 1   b  are coupled to Tx data line  551 - 1 ; and conducting balls  515 - 2   a ,  515 - 2   b  are coupled to Tx data line  551 - 2 . All other elements in  FIG. 3B  are as described in detail in  FIG. 3A  above. According to some embodiments of the present invention, Rx data lines  552 - 1  to  552 - 16 ,  553 - 1 ,  553 - 2 , and Tx data lines  550 - 1  to  550 - 16 ,  551 - 1 ,  551 - 2  may carry their respective signals as differential signals. 
         [0038]    A semiconductor device that contains the layout of the present invention will be referred to in this description as a Bandwidth Engine (BE) device. The problems overcome by adopting the layout of the BE device will be explained in reference to the prior art system of  FIGS. 4A and 4B . 
         [0039]      FIG. 4A  includes two conventional ICs on a board  250 . IC  415  is coupled to IC  420 . The terminals Tx/Rx of devices  415  and  420  are arranged in pairs on the peripheral edges of their packages. On lateral edges of IC  415 , Tx/Rx pairs are Tx 0 /Rx 0 , Tx n /Rx n , and Tx 1 /Rx 1 , Tx m /Rx m . IC  420  has a similar arrangement of Tx/Rx pairs, namely, Tx 0 /Rx 0 , Tx n /Rx n , and Tx 1 /Rx 1 , Tx m /Rx m . 
         [0040]    Data line  70  in  FIG. 4A  must cross over three data lines  72 ,  74  and  76  in order to couple Tx 1  terminal on IC  415  to Rx 1  terminal on IC  420 . Similarly, Tx data line  84  must cross over data lines  80  and  82  in order to couple to Tx n  terminal on IC  415  to Rx n  terminal on chip  420 . Every data line in  FIG. 4A  must cross over one or more data lines of an adjacent terminal. Such crossover can lead to noise coupling. The present invention reduces data line cross over by grouping Tx terminals separately from Rx terminals on the lateral edges of a chip and by isolating Tx ports from Rx ports in the serial interface of the chip layout. 
         [0041]      FIG. 4B  illustrates the extensive crossover problem that occurs when two conventional chips are positioned next to each other. Data lines couple IC  425  to IC  430 . Rx data lines  42 ,  44 ,  46 ,  48  in  FIG. 4B  must cross over an adjacent Tx data line to connect an Rx terminal on IC  425  to a Tx terminal on IC  430 . Similarly, Tx data lines  52 ,  54 ,  56  and  58  in  FIG. 4B  must cross over an adjacent Rx data line for a TX terminal on IC  425  to connect to an Rx terminal on IC  430 . The problems of  FIGS. 4A and 4B  are overcome by separating the Rx terminals from the Tx terminals. 
         [0042]    The present invention will be further explained in reference to  FIG. 5A .  FIG. 5A  illustrates two BE devices  100  and  200  on substrate  555 . Specifically, chip  100  is shown as positioned above chip  200 . The two BE devices are coupled via multiple data lines  32 - 38  and  22 - 28 . For simplicity, data lines originating from Rx terminal on chip  100  are referred to as Rx data lines, and data lines originating from Tx terminals on chip  100  are referred to as Tx data lines. Tx terminals (Tx 0 , Tx 1 , Tx 2 , . . . Tx n ) on chip  100  are isolated from Rx terminals (Rx 0 , Rx 1 , Rx 2 , . . . Rx m ). Similarly, Tx terminals (Tx 0 , Tx 1 , Tx 2 , . . . Tx m ) on chip  200  are isolated from Rx terminals on the same chip (Rx 0 , Rx 1 , Rx 2 , . . . Rx n ). Data line  22  is shown connected at one end to Rx 0  terminal  14  of chip  100 , and at the other end to chip  200  via Tx 0  terminal. In operation, each Tx terminal Tx 0 , Tx 1 , Tx 2 , . . . Tx n  of device  100  serializes and transmits a serial data signal for output on a Tx data line to an IP core on device  200 . Meanwhile, each Rx terminal Rx 0 , Rx 1 , Rx 2 , . . . Rx m  on device  100  receives and deserializes a serial data signal for input on an Rx data line to an IP core on device  100 . Data line  32  couples Tx 0  terminal on chip  100  to Rx 0  terminal on chip  200 . Thus, Rx terminals (Rx 0 , Rx 1 , Rx 2 , . . . Rx m  and Rx 0 , Rx 1 , Rx 2 , . . . Rx n ) are segregated from Tx terminals (Tx 0 , Tx 2 , Tx 2 , . . . Tx m  and Tx 0 , Tx 2 , Tx 2 , . . . Tx n ) on their respective chips. This segregation results in Tx data lines  32 ,  34 ,  36 ,  38  on chip  100  being nonadjacent to Rx data lines  22 ,  24 ,  26 ,  28  on chip  200 . In addition, none of the Rx data lines need to cross over any other data line, including Tx data lines. Consequently, the layout of the Tx data lines and Rx data lines produces a simplified routing pattern. Further, by isolating the Tx terminals from Rx terminals as shown in  FIG. 5A  package  555  may include fewer routing layers. Since the Rx terminals are radially separated from the Tx terminals their respective data lines may traverse through the same routing layer. Alternatively, the latency advantages of the invention can also be attained by having Rx data lines traverse through a first routing layer and Tx data lines traverse through a second routing layer different from the first routing layer. The total number of package substrate layers will vary depending on the number of power and ground layers needed for the particular product that incorporates the devices of the present invention. 
         [0043]    The present invention may also be implemented by positioning chip  100  on either side of chip  200 . For example,  FIG. 5B  illustrates an alternative embodiment in which chip  200  is positioned to the right of chip  100 . Chip  100  is an IC device with Rx and Tx terminals grouped around a central axis (an example of Chip  100  is a BE device, however, Chip  100  need not necessarily be restricted to that of a BE device), while chip  200  may be either a BE device or a BE-compliant device. In  FIG. 5B , chip  200  is a BE-compliant device and is shown with a memory access controller (MAC). In the configuration of  FIG. 5B , none of data lines  570  cross over any other data line. As a result, parallel crosstalk is substantially reduced in the present invention, which enables Tx data lines and Rx data lines to be provided in a single routing layer. The IC device architecture of the present invention also benefits systems that contain devices with an architecture dissimilar to the IC devices of the present invention as will become obvious in reference to  FIGS. 6A and 6B . 
         [0044]      FIG. 6A  illustrates a BE device  100  coupled to IC  600  on board  150 . IC  600  is a conventional IC device that does not have Tx/Rx terminals segregated in accordance with the present invention.  FIG. 6B  illustrates a conventional IC  600  positioned next to a BE device  100 . Unlike  FIGS. 5A and 5B , the system of  FIGS. 6A and 6B  contain at least one data line ( 130  and  140  respectively) that does not cross over an adjacent data line. Thus, Tx data lines in  FIGS. 5A and 5B  cross over only a minimal number of Rx data lines. Therefore when a BE device is coupled to a conventional chip the signal and data routing patterns are also improved over the prior art. 
         [0045]      FIG. 7  illustrates a cross section of a package containing a multi-layer PCB and suitable functional blocks. SERDES interface  60  lies on the central axis, and is flanked by IP core  62  and IP core  64 . Unlike the present invention, conventional packages contain anywhere from eight or more layers. In the present invention, BE device  100  has a PCB  70  that may contain as few as four layers since the signals over the Rx data lines are less likely to interfere with signals being transmitted over a Tx data line. In  FIG. 7 , PCB  70  includes a ground plane  66 , power plane  68  and two routing layers  65 ,  67 . Vias  75  couple the terminals on the upper surface of the package to routing layers  65  and  67 . The chip layout of the present invention is also advantageous in a stacked die assembly.  FIG. 8  illustrates one example of such an assembly. Package  700  is shown as including a BE device  720 , which may be an ASIC. BE device  720  is connected to substrate  780  through balls  225 . An adhesive is applied to second and third dies  740 ,  750  respectively to mount the dies to BE device  720 . In a less preferred embodiment, dies  740 ,  750  may be wire bonded to BE device  720 . Wirebonding is a less preferred way of connecting the stack because it will increase the propagation delay of the signals. Both dies  740  and  750  are coupled to BE device  720  through bumps  235 , while BE device  720  is coupled to substrate  780  through conducting balls  225 . Vias  81 - 84  in BE  720  allow IC  720  to communicate with dies  740  and  750 . Similarly, substrate  780  is provided with conducting balls  311  that attach to a PCB. Dies  740  and  750  may contain either an ASIC, FPGA, CPU memory, or logic. Alternatively, dies  740  and  750  may have identical functions that provide BE device  720  with a new feature or an expanded memory capacity. 
         [0046]    The present invention has been described by various examples above. However, the aforementioned examples are illustrative only and are not intended to limit the invention in any way. The skilled artisan would readily appreciate that the examples above are capable of various modifications. Thus, the invention is defined by the claims set forth below.