Abstract:
A method and system for wireless communication is provided and may include generating a single analog quadrature signal in a chip including RF transmitters and receivers using a baseband processor, and generating output RF signals based on the quadrature signal in corresponding RF transmitters. The output RF signals may be communicated to the RF receivers via a feedback path including circuitry external to the RF receivers. The dedicated circuitry may include a transmit/receive switch and/or an on-chip or off-chip balun. The quadrature signal may include in-phase and quadrature-phase components. The output RF signal communicated via the feedback path may be down-converted utilizing mixers in the RF receivers and communicated to the baseband processor. Distortion in the quadrature signal may be estimated utilizing the communicated down-converted output RF signals and subsequently generated quadrature signals may be predistorted based on the distortion estimation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
       [0001]    This application makes reference to, claims priority to, and claims the benefit of U.S. Provisional Application Ser. No. 60/868,818, filed on Dec. 6, 2006. 
         [0002]    This application makes reference to U.S. patent application Ser. No. 11/618,876, filed on Dec. 31, 2006. 
     
    
       [0003]    Each of the above stated applications is hereby incorporated herein by reference in its entirety. 
       FIELD OF THE INVENTION 
       [0004]    Certain embodiments of the invention relate to wireless communications. More specifically, certain embodiments of the invention relate to a method and system for a linearized transmitter including a power amplifier. 
       BACKGROUND OF THE INVENTION 
       [0005]    Power amplifier (PA) circuits, which are utilized in wireless local area network (WLAN) systems, may be required to operate over a wide range of frequencies. Throughout most of the world, WLAN systems operate in the industrial scientific and industrial (ISM), and/or unlicensed national information infrastructure (U-NII) frequency bands. The ISM band comprises 2.4-2.4835 GHz and 5.725-5.85 GHz frequency ranges, while the U-NII band comprises 5.15-5.25 GHz, 5.25-5.35 GHz and 5.725-5.825 GHz frequency ranges. The IEEE has adopted a series of resolutions 802.11, which specify allowable frequency bands for use in WLAN systems and devices. The IEEE 802.11 resolutions define a 2.4 GHz frequency band, and a 5 GHz frequency band. The 2.4 GHz frequency band comprises the 2.4-2.4835 GHz portion of the ISM band. The 5 GHz frequency band comprises the U-NII frequency band. IEEE 802.11b and IEEE 802.11 g comprise specifications for the operation of WLAN systems and devices for the 2.4 GHz frequency band, while IEEE 802.11a comprises specifications for the operation of WLAN systems and devices for the 5 GHz frequency band. 
         [0006]    A PA circuit in a wireless system is typically a large signal device. In WLAN systems, the PA circuit may transmit output signals at average power levels in the range of 10 dBm to 15 dBm, and peak power levels of about 25 dBm, for example. In WLAN systems, which use OFDM or CCK modulation, output power levels may vary widely such that the ratio of the peak power level to the average power level may be large, for example, 12 dB for OFDM and 6 dB for CCK. Because of these large swings in output power levels, PA circuits may distort the output signal. Distortion, however, is a characteristic, which may be observed in PA circuits that are utilized across a wide range of applications, and may not be limited to PA circuits utilized in wireless systems. There are two metrics, which may be utilized to evaluate the distortion performance of PA circuits. These metrics may be referred to as amplitude modulation to amplitude modulation (AM-AM) distortion, and amplitude modulation to phase modulation (AM-PM) distortion. 
         [0007]    The AM-AM distortion provides a measure of the output power level, p out , in response to the input power level, p in . The input power level, and output power level are each typically measured in units of dBm, for example. In an ideal, non-distorting, PA circuit, the output power level changes linearly in response to a change in the input power level. Thus, for each Δp in  change in the input power level there may be a corresponding change in the output power level Δp out . The AM-AM distortion may be observed when, for example, the output power level in response to a first input power level may be p out ≈αp in1 , where the output level in response to a second input power level may be p out2 ≈βp in2 , when α≠β. 
         [0008]    The AM-PM distortion provides a measure of the phase of the output signal in relation to the input signal (or output phase) in response to the input power level. Output phase is typically measured in units of angular degrees. The AM-PM distortion may be observed when, for example, the output phase changes in response to a change in input power level. 
         [0009]    Limitations in the performance of PA circuitry due to distortion may be exacerbated when the PA is integrated in a single integrated circuit (IC) device with other radio frequency (RF) transmitter circuitry [such as digital to analog converters (DAC), low pass filters (LPF), mixers, and RF programmable gain amplifiers (RFPGA)]. Whereas the pressing need to increase the integration of functions performed within a single IC, and attendant increase in the number of semiconductor devices, may push semiconductor fabrication technologies toward increasingly shrinking semiconductor device geometries, these very semiconductor fabrication technologies may impose limitations on the performance of the integrated PA circuitry. For example, utilizing a 65 nm CMOS process may restrict the range of input power levels for which the PA provides linear output power level amplification. 
         [0010]    The AM-AM distortion and/or the AM-PM distortion comprise transmitter impairments that may result in signal transmission errors that may result in unintentional and/or undesirable modifications in the magnitude and/or phase of transmitted signals. When transmitting quadrature RF signals, the AM-AM distortion and/or the AM-PM distortion may cause unintentional and/or undesirable modifications in the magnitude and/or phase of the I components and/or Q components in the transmitted signals. 
         [0011]    The transmission of erroneous signals from an RF transmitter may result in erroneous detection of data contained within the received signals at an RF receiver. The result may be reduced communications quality as measured, for example, by packet error rate (PER), and/or bit error rate (BER). 
         [0012]    Communications standards may specify a limit for Error Vector Magnitude (EVM) in a transmitted signal. For example, IEEE 802.11 g standard for WLAN communications specifies that EVM dB  for a 54 Mbps transmitted signal may be no greater than −25 dB. Thus, some conventional RF transmitters may be required to limit the peak power level for signals generated by the PA to ensure that the transmitted signals comply with EVM specifications. One potential limitation imposed by the reduced output power level is the reduced operating range in wireless communications. In this regard, the EVM specification may reduce the allowable distance between a transmitting antenna and a receiving antenna for which signals may be transmitted from an RF transmitter and received by an RF receiver, in relation to the operating range that would be theoretically possible if the RF transmitter were able to transmit signals at the maximum, or saturation, output power level that could be generated by the PA. 
         [0013]    Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings. 
       BRIEF SUMMARY OF THE INVENTION 
       [0014]    A method and system for a linearized transmitter including a power amplifier, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
         [0015]    These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         [0016]      FIG. 1  is a block diagram illustrating and exemplary multiband mobile terminal, which may be utilized in connection with an embodiment of the invention. 
           [0017]      FIG. 2  is a block diagram of an exemplary multiband RF transmitter, in accordance with an embodiment of the invention. 
           [0018]      FIG. 3  is an exemplary block diagram illustrating a single chip RF transmitter and receiver utilizing feedback of the RF output from the transmitter through the receiver, in accordance with an embodiment of the invention. 
           [0019]      FIG. 4  is a flowchart illustrating exemplary steps for generating a plurality of output RF signals in a multiband RF transmitter, in accordance with an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    Certain embodiments of the invention may be found in a method and system for a linearized transmitter including a power amplifier. Various embodiments of the invention may comprise a multiband RF transmitter that receives a digital baseband signal. The received digital baseband signal may be subsequently converted to an analog representation and filtered to generate a quadrature signal. The multiband RF transmitter may then utilize the single quadrature signal to generate a plurality of RF output signals, where each of the RF output signals comprises a frequency selected from distinct frequency bands. In an exemplary multiband RF transmitter utilized in an WLAN system, one of the plurality of RF output signals may comprise a frequency selected from the 2.4 GHz frequency band, while a second one of the plurality of RF output signals may comprise a frequency selected from the 5 GHz frequency band. 
         [0021]    In some conventional systems, multiple RF output signals from distinct frequency bands may be generated by a corresponding plurality of transmitter chains, where each of the transmitter chains may comprise circuitry the receives a digital baseband signal and generates a single analog RF output signal among the plurality of RF output signals. 
         [0022]    Various embodiments of the invention may comprise a demarcation point, which may divide the transmitter chain into a transconductance stage and a gain stage. The transconductance stage may receive a single digital baseband signal and generate a single analog quadrature signal. The gain stage may receive a single quadrature signal and generate a single RF output signal. In various embodiments of the invention, a multiband RF transmitter may generate a plurality of RF output signals by utilizing a single transconductance stage, and a plurality of gain stages, where the number of gain stages may be equal to the number of RF output signals. In such various embodiments of the invention, the quadrature signal output from the transconductance stage may be input to each of the gain stages. Each gain stage may then generate a corresponding one of the plurality of RF output signals. 
         [0023]      FIG. 1  is a block diagram illustrating and exemplary multiband mobile terminal, which may be utilized in connection with an embodiment of the invention. Referring to  FIG. 1 , there is shown mobile terminal  120  and a plurality of antennas  121   a  and  121   b . The mobile terminal  120  may comprise a multiband RF transceiver  122 , a digital baseband processor  129 , a processor  125 , a memory  127 , and a plurality of switches  124   a  and  124   b . The multiband RF transceiver  122  may comprise a multiband RF receiver  123   a , and a multiband RF transmitter  123   b . The antenna  121   a  may enable the transmission and/or reception of signals within one of a plurality of RF frequency ranges. The antenna  121   b  may enable the transmission and/or reception of signals within a distinct one of the plurality of RF frequency ranges. The transmit and receive antenna  121   a  may be communicatively coupled to the multiband RF receiver  123   a  and the multiband RF transmitter  123   b  via the switch  124   a . The transmit and receive antenna  121   b  may be communicatively coupled to the multiband RF receiver  123   a  and the multiband RF transmitter  123   b  via the switch  124   b . The switch  124   a  may be utilized to switch the antenna  121   a  between transmit and receive functions. The switch  124   b  may be utilized to switch the antenna  121   b  between transmit and receive functions. 
         [0024]    The multiband RF transmitter  123   b  may comprise suitable logic, circuitry, and/or code that may enable processing of one or more RF signals for transmission. A plurality of RF signals may be transmitted, each within a distinct frequency range. The multiband RF transmitter  123   b  may enable transmission of RF signals in frequency bands utilized by various wireless communications systems, such as GSM and/or CDMA, for example. 
         [0025]    The multiband RF receiver  123   a  may comprise suitable logic, circuitry, and/or code that may enable processing of received RF signals within one or more distinct frequency ranges. The multiband RF receiver  123   a  may enable receiving RF signals in frequency bands utilized by various wireless communication systems, such as WLAN, Bluetooth, GSM and/or CDMA, for example. 
         [0026]    The digital baseband processor  129  may comprise suitable logic, circuitry, and/or code that may enable processing and/or handling of digital baseband signals. In this regard, the digital baseband processor  129  may process or handle signals received from the multiband RF receiver  123   a  and/or signals to be transferred to the multiband RF transmitter  123   b  for transmission via a wireless communication medium. The digital baseband processor  129  may also provide control and/or feedback information to the multiband RF receiver  123   a  and to the multiband RF transmitter  123   b , based on information from the processed signals. The digital baseband processor  129  may communicate information and/or data from the processed signals to the processor  125  and/or to the memory  127 . Moreover, the digital baseband processor  129  may receive information from the processor  125  and/or to the memory  127 , which may be processed and transferred to the multiband RF transmitter  123   b  for transmission via the wireless communication medium. 
         [0027]    The processor  125  may comprise suitable logic, circuitry, and/or code that may enable control and/or data processing operations for the mobile terminal  120 . The processor  125  may be utilized to control at least a portion of the multiband RF receiver  123   a , the multiband RF transmitter  123   b , the digital baseband processor  129 , and/or the memory  127 . In this regard, the processor  125  may generate at least one signal for controlling operations within the mobile terminal  120 . 
         [0028]    The memory  127  may comprise suitable logic, circuitry, and/or code that may enable storage of data and/or other information utilized by the mobile terminal  120 . For example, the memory  127  may be utilized for storing processed data generated by the digital baseband processor  129  and/or the processor  125 . The memory  127  may also be utilized to store information, such as configuration information, which may be utilized to control the operation of at least one block in the mobile terminal  120 . For example, the memory  127  may comprise information necessary to configure the multiband RF receiver  123   a  to enable receiving RF signals in the appropriate frequency band(s). 
         [0029]    In an exemplary embodiment of a transmitting mobile terminal  120 , the mobile terminal  120  may comprise a multiband RF transmitter  123   b , a digital baseband processor  129 , a processor  125 , a memory  127 , and a plurality of switches  124   a  and  124   b , for example. In an exemplary embodiment of a receiving mobile terminal  120 , the mobile terminal  120  may comprise a multiband RF receiver  123   a , a digital baseband processor  129 , a processor  125 , a memory  127 , and a plurality of switches  124   a  and  124   b , for example. 
         [0030]      FIG. 2  is a block diagram of an exemplary multiband RF transmitter, in accordance with an embodiment of the invention. Referring to  FIG. 2 , there is shown a single chip RF transmitter  200 , baluns  216   a  and  216   b , and antennas  121   a  and  121   b . The single chip RF transmitter  200  may comprise a multiband RF transmitter  123   b , and a baseband processor  240 . The multiband RF transmitter  123   b  may comprise a transconductance stage  250  and a plurality of gain stages  252   a  and  252   b . The gain stage  252   a  may comprise a power amplifier (PA)  214   a , a power amplifier driver (PAD)  212   a , an RF programmable gain amplifier (RFPGA)  210   a , a transmitter In-phase signal (I) mixer  208   a , a transmitter Quadrature-phase signal (Q) mixer  208   b , and a plurality of tunable capacitors  223   a ,  223   b  and  223   c . The gain stage  252   b  may comprise a PA  214   b , PAD  212   b , RFPGA  210   b , I mixer  208   c , Q mixer  208   d , and a plurality of tunable capacitors  223   d ,  223   e  and  223   f . The transconductance stage  250  may comprise, an I transconductance amplifier (gm)  206   a , a Q gm  206   b , an I low pass filter (LPF)  204   a , a Q LPF  204   b , an I digital to analog converter (I DAC)  202   a , and a Q DAC  202   b.    
         [0031]    The transconductance stage  250  may comprise suitable logic, circuitry and/or code that may enable generation of an analog quadrature signal based on an input digital baseband signal. The analog quadrature signal may comprise an I component signal and a Q component signal. 
         [0032]    The gain stage  252   a  may comprise suitable logic, circuitry and/or code that may enable generation of an RF output signal based on an analog input quadrature signal. The gain stage  252   a  may generate the RF output signal by upconverting the analog input quadrature signal based on a carrier frequency selected from a frequency range, for example a 2.4 GHz frequency range. The upconverted signal may be amplified through one or more amplification stages and output as the RF output signal. 
         [0033]    The gain stage  252   b  may be substantially similar to the gain stage  252   a . The gain stage  252   b  may generate an RF output signal by upconverting the input quadrature signal based on a carrier frequency selected from a different frequency range from that selected in the gain stage  252   a , for example a 5 GHz frequency range. 
         [0034]    The PA  214   a  may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate a transmitted signal of sufficient signal power (as measured by dBm, for example) for transmission via a wireless communication medium. The PA  214   b  may be substantially similar to the PA  214   a.    
         [0035]    The PAD  212   a  may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate an amplified output signal. The PAD  212   a  may be utilized in multistage amplifier systems wherein the output of the PAD  212   a  may be an input to a subsequent amplification stage. The PAD  212   b  may be substantially similar to the PAD  212   a.    
         [0036]    The RFPGA  210   a  may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate an amplified output signal, wherein the amount of amplification, as measured in dB, may be determined based on an input control signal. In various embodiments of the invention, the input control signal may comprise binary bits. The RFPGA  210   b  may be substantially similar to the RFPGA  210   a.    
         [0037]    The transmitter I mixer  208   a  may comprise suitable logic, circuitry, and/or code that may enable generation of an RF signal by upconversion of an input signal. The transmitter I mixer  208   a  may utilize an input local oscillator signal labeled as LO 208a  to upconvert the input signal. The upconverted signal may be an RF signal. The transmitter I mixer  208   a  may produce an RF signal for which the carrier frequency may be equal to the frequency of the signal LO 208a . The carrier frequency may be selected from a frequency range, for example, a 2.4 GHz frequency range. The selected carrier frequency may be a center frequency for the RF signal generated by the transmitter I mixer  208   a.    
         [0038]    The transmitter Q mixer  208   b  may be substantially similar to the transmitter I mixer  208   a . The frequency of the input local oscillator signal LO 208b  may be equal to the frequency of the local oscillator signal LO 208a , however, the local oscillator signal LO 208b  may have a different phase in relation to the local oscillator signal LO 208a . For example, the phase of the local oscillator signal LO 208b  may be shifted 90° relative to the local oscillator signal LO 208a . 
         [0039]    The tunable capacitor  223   a  may be coupled to a signal within the gain stage  252   a . Tuning of the tunable capacitor  223   a  may enable a changing of the capacitance value of the tunable capacitor  223   a  along with a corresponding modification of the center frequency of the coupled signal. The tunable capacitors  223   b ,  223   c ,  223   d ,  223   e  and  223   f  may be substantially similar to the tunable capacitor  223   a.    
         [0040]    The I gm  206   a  may comprise suitable, logic, circuitry, and/or code that may enable generation of an output current, the amplitude of which may be proportional to an amplitude of an input voltage to the I gm  206   a . A measure of proportionality between input voltage and output current may be determined based on the transconductance parameter, gm I , associated with the I gm  206   a . The Q gm  206   b  may be substantially similar to the I gm  206   a . The transconductance parameter associated with the Q gm  206   b  is gm Q . 
         [0041]    The I LPF  204   a  may comprise suitable logic, circuitry, and/or code that may enable selection of a cutoff frequency, wherein the LPF may attenuate the amplitudes of input signal components for which the corresponding frequency is higher than the cutoff frequency, while the amplitudes of input signal components for which the corresponding frequency is less than the cutoff frequency may “pass,” or not be attenuated, or attenuated to a lesser degree than input signal components at frequencies higher than the cutoff frequency. In various embodiments of the invention, the I LPF  210   a  may be implemented as a passive filter, such as one that utilizes resistor, capacitor, and/or inductor elements, or implemented as an active filter, such as one that utilizes an operational amplifier. In an exemplary embodiment of the invention, the I LPF  210   a  may receive a differential input signal and output a differential output signal. The Q LPF  204   b  may be substantially similar to the I LPF  204   a.    
         [0042]    The I DAC  202   a  may comprise suitable logic, circuitry, and/or code that may enable conversion of an input digital signal to a corresponding analog representation. The Q DAC  202   b  may be substantially similar to the I DAC  202   a.    
         [0043]    The baseband processor  240  may comprise suitable logic, circuitry, and/or code that may enable processing of binary data contained within an input digital baseband signal. The baseband processor  240  may perform processing tasks, which correspond to one or more layers in an applicable protocol reference model (PRM). For example, the baseband processor  240  may perform physical (PHY) layer processing, layer  1  (L 1 ) processing, medium access control (MAC) layer processing, logical link control (LLC) layer processing, layer  2  (L 2 ) processing, and/or higher layer protocol processing based on input binary data. The processing tasks performed by the baseband processor  240  may be referred to as being within the digital domain. The baseband processor  240  may also generate control signals based on the processing of the input binary data. 
         [0044]    In operation, the multiband RF transmitter  123   b  may receive a digital baseband signal from the baseband processor  240 . The digital baseband signal may comprise an I component, I BB , and a Q component, Q BB . Signal I BB  may be input to the I DAC  202   a  while the signal Q BB  may be input to the Q DAC  202   b.    
         [0045]    The analog signals generated by the I DAC  202   a  and the Q DAC  202   b  may comprise undesirable frequency components. The I LPF  204   a  and Q LPF  204   b  may attenuate signal amplitudes associated with these undesirable frequency components. 
         [0046]    The I gm  206   a  may receive the filtered signal from the I LPF  204   a  and generate an I component signal, I Quad , of an analog quadrature signal output from the transconductance stage  250 . The Q gm  206   b  may receive the filtered signal from the Q LPF  204   b  and generate a Q component signal, Q Quad , of the analog quadrature signal output from the transconductance stage  250 . 
         [0047]    The gain stage  252   a  may receive the analog quadrature signal from the transconductance stage  250 . The baseband processor  240  may configure the transmitter I mixer  208   a  to select a carrier frequency for the LO 208a  signal. The carrier frequency LO 208a  may be selected from a frequency range, for example a 2.4 GHz frequency range. The LO 208a  may be utilized to upconvert the I Quad  signal. The baseband processor  240  may also configure the transmitter Q mixer  208   b  to select a carrier frequency for the LO 208b  signal. The carrier frequency LO 208b  may be equal to the carrier frequency LO 208a . The LO 208b  may be utilized to upconvert the Q Quad  signal. The upconverted I Quad  and Q Quad  signals may be combined to form a composite analog RF signal, RF S1 . The center frequency for the signal RF S1  may be based on the carrier frequency LO 208a , for example. The tunable capacitor  223   a  may enable modification of the center frequency for the analog signal RF S1 . The frequency modified signal RF S1 (LO 208a ′) may be received by the RFPGA  210   a . The frequency modification, Δf 1 , may be represented as in the following equations: 
         [0000]      Δ f   1   =LO′   208a   −LO   208a   [1a]
 
         [0000]      where: 
         [0000]      |Δ f   1 |≦0  [1b]
 
         [0048]    The baseband processor  240  may configure the RFPGA  210   a  to amplify the signal RF S1 (LO 208a ′) by a gain level, as measured in dB, for example. The RFPGA  210   a  may generate an amplified signal RF S2 . The tunable capacitor  223   b  may enable modification of the center frequency for the signal RF S2 . The frequency modified signal RF S2 (LO 208a ″) may be received by the PAD  212   a . The frequency modification, Δf 2 , may be represented as in the following equations: 
         [0000]      Δ f   2   =LO″   208a   −LO′   208a   [2a]
 
         [0000]      where: 
         [0000]      |Δ f   2 |≦0  [2b]
 
         [0049]    The PAD  212   a  may amplify the signal RF S2 (LO 208a ″) by a gain level, as measured in dB, for example. The PAD  212   a  may generate an amplified signal RF S3 . The tunable capacitor  223   c  may enable modification of the center frequency for the signal RF S3 . The frequency modified signal RF S3 (LO 208a ′″) may be received by the PA  214   a . The frequency modification, Δf 3 , may be represented as in the following equations: 
         [0000]      Δ f   3   =LO′″   208a   −LO″   208a   [3a]
 
         [0000]      where: 
         [0000]      |Δ f   3 |≦0  [3b]
 
         [0000]    The values Δf 1 , Δf 2  and/or Δf 3  may be independently determined. 
         [0050]    The PA  214   a  may amplify the signal RF S3 (LO 208a ′″) by a gain level, as measured in dB, for example. The PA  214   a  may generate an RF output signal RF out1 . The balun  216   a  may enable energy from the signal RF out1  to be transferred to the antenna  121   a  from which the transferred signal energy may be transmitted via a wireless communication medium. 
         [0051]    The operation of the gain stage  252   b  may be substantially similar to the operation of the gain stage  252   a . The gain stage  252   b  may generate a signal RF out2 . Within the gain stage  252   b , the I mixer  208   c  and Q mixer  208   d  may be configured to select a carrier frequency, represented by LO 208c  and LO 208d  respectively, which may be selected from a frequency range that is different from that utilized for selecting the carrier frequency, LO 208a  and LO 208b . For example, the carrier frequency for LO 208c  and LO 208d  may be selected from a 5 GHz frequency range. The tunable capacitor  223   d  may enable generation of a modification Δf 4 , the value of which may be independent of the value of Δf 1 , Δf 2 , and/or Δf 3 , for example. The tunable capacitor  223   e  may enable generation of a modification Δf 5 , the value of which may be independent of the value of Δf 1 , Δf 2 , Δf 3  and/or Δf 4 , for example. The tunable capacitor  223   f  may enable generation of a modification Δf 6 , the value of which may be independent of the value of Δf 1 , Δf 2 , Δf 3 , Δf 4  and/or Δf 5 , for example. 
         [0052]      FIG. 3  is an exemplary block diagram illustrating a single chip RF transmitter and receiver utilizing feedback of the RF output from the transmitter through the receiver, in accordance with an embodiment of the invention.  FIG. 3  shows a system utilizing a feedback path from the RF output to the baseband processor  240  via the multiband receiver  123   a . The feedback may be utilize to enable the baseband processor  240  to estimate AM-AM and/or AM-PM distortion in one or more of the plurality of RF output signals generated by the multiband RF transmitter  123   b . After estimating the AM-AM and/or AM-PM distortion, the baseband processor  240  may digitally predistort subsequent baseband signals to linearize the PA circuits  214   a  and/or  214   b  within the multiband RF transmitter  123   b.    
         [0053]    Referring to  FIG. 3 , there is shown a single chip RF transceiver  300 , baluns  216   a ,  216   b ,  222   a  and  222   b , switches  124   a  and  124   b , and antennas  121   a  and  121   b . The antennas  121   a  and  121   b , and switches  124   a  and  124   b  are described in  FIG. 1 . The single chip RF transceiver  300  may comprise a multiband RF receiver  123   a , a multiband RF transmitter  123   b , a signal attenuation block  218 , a feedback I mixer  220   a , a feedback Q mixer  220   b , a baseband processor  240  and a switch  235 . A detailed description of the multiband RF transmitter  123   b  may be found in  FIG. 2 . The multiband RF receiver  123   a  may comprise a plurality of RF low noise amplifiers (RFLNA)  224   a  and  224   b , a plurality of receiver I mixers  226   a  and  226   c , a plurality of receiver Q mixers  226   b  and  226   d , an I path selector switch  234   a , a Q path selector switch  234   b , a plurality of I high pass variable gain amplifiers (HPVGA)  228   a  and  228   c , a plurality of Q HPVGA  228   b  and  226   d , a plurality of I LPFs  230   a  and  230   c , a plurality of Q LPFs  230   b  and  230   d , a plurality of I analog to digital converters (DAC)  232   a  and  232   c , and a plurality of Q DACs  232   b  and  232   d.    
         [0054]    In various embodiments of the invention, the baluns  216   a ,  216   b ,  222   a  and  222   b  may be integrated within the single chip RF transceiver  300 . In various embodiments of the invention, electrical connections between components shown in  FIG. 3  may be differential. In various other embodiments of the invention, electrical connections between components shown in  FIG. 3  may be single ended. 
         [0055]    The switch  235  may enable one of a plurality of inputs to be selectively coupled to an output. In an exemplary embodiment of the invention, the switch  235  may select from among 2 input signals, and couple the selected input signal to a single output. The I path selector switch  234   a  and the Q path selector switch  234   b  may be substantially similar to the switch  235 . 
         [0056]    The signal attenuation block  218  may comprise suitable logic, circuitry, and/or code that may enable generation of an output signal, the amplitude and/or power level of which may be based on an input signal after insertion of a specified level of attenuation. In various embodiments of the invention the attenuation level may be programmable over a range of attenuation levels. In an exemplary embodiment of the invention, the range of attenuation levels may comprise −32 dB to −40 dB, although various embodiments of the invention may not be limited to such a specific range. 
         [0057]    The feedback I mixer  220   a  may comprise suitable logic, circuitry, and/or code that may enable downconversion of an input signal. The feedback I mixer  220   a  may utilize an input local oscillator signal labeled as LO 220a  to downconvert the input signal. The feedback Q mixer  220   b  may be substantially similar to the feedback I mixer  220   a . The feedback Q mixer  220   b  may utilize an input local oscillator signal labeled LO 220b  to downconvert the input signal. In an exemplary embodiment of the invention, the phase of the local oscillator signal LO 220b  may be shifted 90° relative to the local oscillator signal LO 220a . 
         [0058]    The RFLNA  224   a  may comprise suitable logic, circuitry, and/or code that may enable amplification of weak signals (as measured by dBm, for example), such as received from an antenna. The input signal to the RFLNA  224   a  may be an RF signal received at the antenna  121   a , which is communicatively coupled to the RFLNA  224   a  through the balun  222   a.    
         [0059]    The receiver I mixer  226   a  may be substantially similar to the feedback I mixer  220   a . The receiver I mixer  226   a  may utilize an input local oscillator signal labeled as LO 226a  to downconvert the input signal. The frequency for the signal LO 226a  may be selected from a frequency range, for example, a 2.4 GHz range. 
         [0060]    The receiver Q mixer  226   b  may be substantially similar to the feedback Q mixer  220   b . The receiver Q mixer  226   b  may utilize an input local oscillator signal labeled as LO 226b  to downconvert the input signal. The frequency of the signal LO 226b  may be equal to the frequency of the signal LO 226a , however the phase of the signal LO 226b  may be shifted 90° relative to the phase of the signal LO 226a , for example. 
         [0061]    The I HPVGA  228   a  may comprise suitable logic, circuitry, and/or code that may enable attenuation of input signals to generate an attenuated output signal, wherein the amount of attenuation, as measured in dB for example, may be determined based on an input control signal. In various embodiments of the invention, the input control signal may comprise binary bits. In various embodiments of the invention, the HPVGA  228   a  may provide attenuation levels that range from 0 dB to −30 dB in 3 dB increments. The Q HPVGA  228   b , I HPVGA  228   c  and Q HPVGA  228   d  may be substantially similar to the I HPVGA  228   a.    
         [0062]    The I LPF  230   a , Q LPF  230   b , I LPF  230   c  and Q LPF  230   d  may be substantially similar to the I LPF  204   a.    
         [0063]    The I ADC  232   a  may comprise suitable logic, circuitry, and/or code that may enable conversion of an input analog signal to a corresponding digital representation. The I ADC  232   a  may receive an input analog signal, which may be characterized by a signal amplitude. The I ADC  232   a  may quantize the analog signal by correlating ranges of analog signal level values to corresponding numerical values. The I ADC  232   a  may determine analog signal levels at distinct time instants by measuring, or integrating, the analog signal level of the input signal during a time interval referred to as δt. The time interval between measurements, or sampling interval, may be determined based on a sampling rate, which is typically long in comparison to the integration time interval δt. The Q ADC  232   b , I ADC  232   c  and Q ADC  232   d  may be substantially similar to the I ADC  232   a.    
         [0064]    In operation, the baseband processor  240  may configure the multiband RF receiver  123   a  and/or multiband RF transmitter  123   b  for two distinct modes of operation comprising a normal operating mode, and a calibration mode. In the normal operating mode, the multiband RF transmitter  123   b  may transmit RF signals via the antennas  121   a  and/or  121   b , while the multiband RF receiver  123   a  may receive RF signals via the antennas  121   a  and/or  121   b . In the calibration mode, at least one of the plurality of RF output signals, RF out1  and RF out2 , from the multiband RF transmitter  123   b  may be selectively coupled via the switch  235  to an input of the signal attenuation block  218 . The selectively coupled RF output signal may be attenuated, downconverted into I and Q component signals, and inserted in the multiband RF receiver  123   a  as feedback signals. Thus, the calibration mode may enable a closed feedback loop from the baseband processor  240 , to the multiband RF transmitter  123   b , to a feedback point within the multiband RF receiver  123   a , and back to the baseband processor  240 . 
         [0065]    As shown in  FIG. 3 , each selected RF output signal from the multiband RF transmitter  123   b  follows the feedback path through the I HPVGA  228   a  and Q HPVGA  228   b , the I LPF  230   a  and Q LPF  230   b , and the I ADC  232   a  and Q ADC  232   b  within the multiband RF receiver  123   a . In various embodiments of the invention, each RF output signal may utilize a separate feedback path through the multiband RF receiver  123   a  to the baseband processor  240 , or may utilize dedicated circuitry external to the multiband RF receiver  123   a  to establish one or more feedback paths from the RF output signals to the baseband processor  240 . 
         [0066]    Referring to  FIG. 3 , in a normal operating mode, the baseband processor  240  may generate control signals that enable configuration of the I path selector switch  234   a  such that I path selector switch  234   a  may be configured to select an input from the receiver I mixer  226   a . The I path selector switch  234   a  may enable the output signal from the receiver I mixer  226   a  to be coupled to an input to the I HPVGA  228   a . The baseband processor  240  may also generate control signals that enable configuration of the Q path selector switch  234   b  such that Q path selector switch  234   b  may be configured to select an input from the receiver Q mixer  226   b . The Q path selector switch  234   b  may enable the output signal from the receiver Q mixer  226   b  to be coupled to an input to the Q HPVGA  228   b.    
         [0067]    In the normal operating mode, the multiband RF receiver  123   a  may receive RF signals via the antenna  121 . The RFLNA  224  may amplify the received RF signal, which may then be sent to the receiver I mixer  226   a , Q mixer  226   b , I mixer  226   c  and/or receiver Q mixer  226   d . The receiver I mixer  226   a  may downconvert the amplified RF signal. Similarly, the receiver Q mixer  226   b  may also downconvert the amplified RF signal. The I mixer  226   a  and Q mixer  226   b  may downconvert the amplified RF signal by utilizing a frequency selected from one of a plurality of frequency bands. For example, the frequency utilized by the I mixer  226   a  and Q mixer  226   b  may be selected from a 2.4 GHz frequency band. 
         [0068]    While the receiver I mixer  226   c  and the receiver Q mixer  226   d  may also downconvert the amplified RF signal. The I mixer  226   c  and Q mixer  226   d  may downconvert the amplified RF signal by utilizing a frequency selected from a distinct one of the plurality of frequency bands. For example, the frequency utilized by the I mixer  226   c  and Q mixer  226   d  may be selected from a 5 GHz frequency band. 
         [0069]    The baseband processor  240  may generate control signals that configure the I HPVGA  228   a  to amplify an I component portion of a received downconverted signal. In an exemplary embodiment of the invention, the I HPVGA  228   a  may amplify signal components for which the corresponding frequency may be higher than baseband. Similarly, the baseband processor  240  may generate control signals that configure the Q HPVGA  228   b  to amplify a Q component portion of the received downconverted signal. The I HPVGA  228   c  and Q HPVGA  228   d  may amplify I component and Q component portions of a distinct downconverted signal. 
         [0070]    The I LPF  230   a  may filter the amplified signal received from the I HPVGA  228   a  such that the output of the I LPF  230   a  is an analog baseband signal. The analog baseband signal may comprise a sequence of symbols. Similarly, the Q LPF  230   b  may generate an analog baseband signal. The I LPF  230   c  and Q LPF  230   d  may filter amplified signals from the I HPVGA  228   c  and Q HPVGA  228   d  respectively. 
         [0071]    The I ADC  232   a  may convert an amplitude of a symbol in the analog baseband signal received from the I LPF  230   a  to a sequence of bits. The sequence of bits may be contained in a digital baseband signal. Similarly, the Q ADC  232   b  may convert an amplitude of a symbol in the analog baseband signal received from the Q LPF  230   b  to a sequence of bits. The I ADC  232   c  may convert an amplitude of a symbol in the analog baseband signal received from the I LPF  230   c  to a sequence of bits. The Q ADC  232   d  may convert an amplitude of a symbol in the analog baseband signal received from the Q LPF  230   d  to a sequence of bits. The baseband processor  240  may receive the sequence of bits from the I ADC  232   a  and Q ADC  232   b , and/or from the I ADC  232   c  and Q ADC  232   d , and perform various processing tasks as set forth above. 
         [0072]    In the calibration mode, the baseband processor  240  may generate control signals that may enable configuration of the I path selector switch  234   a  to select an input from the feedback I mixer  220   a . The I path selector switch  234   a  may enable the output signal from the feedback I mixer  220   a  to be coupled to an input to the I HPVGA  228   a . The baseband processor  240  may also generate control signals that may enable configuration of the Q path selector switch  234   b  to select an input from the feedback Q mixer  220   b . The Q path selector switch  234   b  may enable the output signal from the feedback Q mixer  220   b  to be coupled to an input to the Q HPVGA  228   b.    
         [0073]    While the exemplary system illustrated in  FIG. 3  shows 2 feedback mixers, various embodiments of the invention may also utilize a single feedback mixer. In various embodiments of the invention that utilize a single feedback mixer, the output from the single feedback mixer may be input to the I HPVGA  228   a  and Q HPVGA  228   b , for example. 
         [0074]    Referring to  FIG. 3 , in the calibration mode, the baseband processor  240  may generate control signals that may enable configuration of the switch  235  to perform selection of an RF output signal from the plurality of RF output signals, RF out1  and RF out2 , generated by the multiband RF transmitter  123   b . The selected RF output signal may be coupled to the input of the signal attenuation block  218  and utilized as a feedback signal. The signal attenuation block  218  may adjust the amplitude of the selected RF output signal to a level more suitable for input to the feedback mixers  220   a  and  220   b . The signal attenuation block  218  may be configured by the baseband processor  240  to apply a specified attenuation level to the input signal selected from the multiband RF transmitter  123   b . The feedback I mixer  220   a  may downconvert an attenuated RF signal to generate an I component signal. The feedback Q mixer  220   b  may downconvert the attenuated RF signal to generate a Q component signal. The I HPVGA  228   a  may receive input signals from the feedback I mixer  220   a , while the Q HPVGA  228   b  may receive input signals from the feedback Q mixer  220   b.    
         [0075]    The I LPF  230   a  may filter the amplified signal received from the I HPVGA  228   a  such that the output of the I LPF  230   a  may be based on an analog baseband component of the amplified signal received from the I HPVGA  228   a . Similarly, the Q LPF  230   b  may generate an analog baseband signal. 
         [0076]    One possible limitation of the PA circuits  214   a  and/or  214   b  is that the output signal may become increasingly distorted as the output power levels from the PA circuits  214   a  and/or  214   b  increase. The distortion may be detected through AM-AM distortion measurements, and/or AM-PM distortion measurements. 
         [0077]    In various embodiments of the invention, the calibration mode may enable the baseband processor  240  to compensate for AM-AM distortion and/or AM-PM distortion. In one aspect of the invention, the calibration mode may enable the baseband processor  240  to send input digital baseband signals I BB  and Q BB  to the multiband RF transmitter  123   b , from which a plurality analog RF output signals may be generated. An analog RF output signal may be selected by the switch  235  and subsequently attenuated by the signal attenuation block  218 , and downconverted by the feedback I mixer  220   a  and/or the feedback Q mixer  220   b . The downconverted signal generated by the feedback I mixer  220   a  may comprise an I signal component derived from the selected RF output signal, while the downconverted signal generated by the feedback Q mixer  220   b  may comprise a Q signal component. The downconverted signal from the feedback I mixer  220   a  may be inserted into the multiband RF receiver  123   a  path as a feedback signal, I F , input to the I HPVGA  228   a , while the downconverted signal from the feedback Q mixer  220   b  may be inserted into the multiband RF receiver  123   a  path as a feedback signal, Q F , input to the Q HPVGA  228   b . The feedback signals, I F  and Q F , may be processed within the multiband RF receiver  123   a  path and received as digital baseband signals, I FB  and/or Q FB  respectively, at the baseband processor  240 . 
         [0078]    Based on the digital baseband signals I BB  and Q BB , and the feedback digital baseband signals I FB  and Q FB , the baseband processor  240  may estimate AM-AM and/or AM-PM distortion in the RF output signals, RF out1  and/or RF out2 , from the multiband RF transmitter  123   b . Based on the AM-AM and/or AM-PM distortion estimates, the baseband processor  240  may predistort subsequent digital baseband signals I BB  and/or Q BB . By predistorting the digital baseband signals I BB  and/or Q BB , the baseband processor  240  may linearize the PA circuits  214   a  and/or  214   b  in the multiband RF transmitter  123   b . By linearizing the PA circuits  214   a  and/or  214   b , the analog RF output signals, RF out1  and/or RF out2 , generated by the PA circuits  214   a  and  214   b  may change linearly in response to changes in the undistorted digital baseband signals I BB  and Q BB  from the baseband processor  240 . 
         [0079]    In various embodiments of the invention, digital predistortion may be utilized to linearize the PA circuits  214   a  and/or  214   b , which may thereby enable the PA circuits  214   a  and/or  214   b  to transmit signals at higher average output power levels while still complying with relevant EVM specifications, for example. Further details describing exemplary methods of calibration for digital predistortion are disclosed in U.S. patent application Ser. No. 11/618,876 filed Dec. 31, 2006, which is hereby incorporated herein in its entirety. 
         [0080]      FIG. 4  is a flowchart illustrating exemplary steps for generating a plurality of output RF signals in a multiband RF transmitter, in accordance with an embodiment of the invention. Referring to  FIG. 4 , in step  402 , the baseband processor  240  may generate a digital baseband signal. In step  404 , the transconductance stage  250  may generate an analog quadrature signal based on the digital baseband signal. In step  406 , a processor  125  may select a plurality of carrier frequencies. Each carrier frequency may be selected from a distinct frequency band. The number of selected carrier frequencies may be equal to the number of gain stages  252   a  and  252   b . In step  408 , each gain stage  252   a  and  252   b  may generate an analog RF output signal. Each analog RF output signal may be generated by utilizing a distinct carrier frequency from the plurality of carrier frequencies selected in step  406 . 
         [0081]    Various aspect of a system for a linearized transmitter including a power amplifier may include at least one transconductance amplifier  206   a  that enables generation of a single analog quadrature signal. Transmitter mixers  208   a ,  208   b ,  208   c  and  208   d  may enable generation of a plurality of upconverted RF signals in a corresponding plurality of RF processing chains based on the generated single analog quadrature signal. In various embodiments of the invention, a gain stage, for example gain stage  250 , may also be referred to as an RF processing chain. Power amplifier circuit  214   a  and  214   b  may enable generation of a corresponding plurality of RF output signals within a wireless communication system  120  based on the generated plurality of upconverted RF signals. 
         [0082]    The single analog quadrature signal may comprise an in-phase component and a quadrature-phase component. The transmitter mixers  208   a ,  208   b ,  208   c  and  208   d  may enable generation of the plurality of each of the plurality of upconverted RF signals based on the generated single analog quadrature signal and a selected center frequency. The selected center frequency may be selected from a frequency range. The frequency range may be distinct from a previous frequency range and/or a subsequent frequency range utilized for generating a previous one of the plurality of upconverted RF signals and/or a subsequent one of the plurality of upconverted RF signals. Tunable capacitors  223   a  and  223   d  may enable independent adjustment of a center frequency for each of the generated plurality of upconverted RF signals. The independent adjustment increases, decreases or leaves unchanged, the center frequency for each of the generated plurality of upconverted RF signals. 
         [0083]    One or more sets of RFPGA circuits  210   a  and  210   b  may enable generation of a first stage amplified signal based on each of the generated a plurality of first stage amplified signals each based on a corresponding one of the generated plurality of upconverted RF signals following the independent adjustment of the center frequency. Tunable capacitors  223   b  and  223   e  may enable independent adjustment of a center frequency for each of the plurality of first stage amplified signals. The independent adjustment increases, decreases or leaves unchanged, the center frequency for each of the plurality of first stage amplified signals. 
         [0084]    One or more sets of PAD circuits  212   a  and  212   b  may enable generation of one or more pluralities of subsequent stage amplified signals based on the generated plurality of first stage amplified signals following the independent adjustment of the center frequency for each of the plurality of generated first stage amplified signals. At least one set of tunable capacitors  223   c  and  223   f  may enable independent adjustment of a center frequency for each of the generated one or more pluralities of subsequent stage amplified signals. The independent adjustment increases, decreases or leaves unchanged, the center frequency for each of the generated one or more pluralities of subsequent stage amplified signals. 
         [0085]    PA circuits  214   a  and  214   b  may enable generation of each of the corresponding plurality of RF signals based on a corresponding last of the generated one or more pluralities of subsequent stage amplified signals following independent adjustment of the center frequency for each of the generated one or more pluralities of subsequent stage amplified signals. The PA circuits  214   a  and  214   b  may enable transmission of at least a portion of the generated corresponding plurality of RF signals via a wireless communication medium. 
         [0086]    A switch  235  may enable selection of one or the corresponding plurality of generated RF output signals. Feedback mixer circuits  220   a  and  220   b  may enable generation of one or more feedback signals by performing a frequency downconversion operation on the selected one of the corresponding plurality of generated RF output signals. An I path selector switch  234   a  and/or Q path selector switch  234   b  may enable insertion of the generated feedback signals at corresponding insertions point(s) in a receiver circuit  123   a . Each insertion point may be between a corresponding receiver mixer circuit  226   a ,  226   b ,  226   c  and/or  226   d , and a corresponding one or more circuits,  228   a ,  230   a  and  232   a  for example, that generates a based band signal corresponding to one of the generated feedback signals. Transconductance amplifiers  206   a  and  206   b  may enable generation of the single quadrature signal in a single transconductance stage circuit  250 . 
         [0087]    Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. 
         [0088]    The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. 
         [0089]    While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.