Abstract:
The apparatus corrects a data detection error caused by baseline wandering in an optical PRML read channel. The apparatus includes error detection circuitry and error correction circuitry. The error detection circuitry monitors a serial output signal from the optical PRML read channel and a first set of input signals to the optical PRML read channel to detect an error event associated with baseline wandering. The error detection circuitry deems the error event to have occurred when three conditions are satisfied. First, a bit sequence represented by the serial output signal matches a first bit sequence associated with the error event. Second, a first difference in a first set of consecutive values represented by the first set of input signals is within a first range of values associated with the error event. Third, a second difference in a second set of consecutive values of the first input signal is within a second range of values associated with the error event. The error detection circuitry responds to satisfaction of all three conditions by asserting an error signal. The error correction circuitry responds to assertion of the error signal by modifying a pair of consecutive bits represented by the serial output signal to generate a corrected output signal having a second bit sequence.

Description:
BRIEF DESCRIPTION 
     The present invention relates generally to data detection in an optical Partial Response Maximum Likelihood (PRML) read channel, and particularly to error correction circuitry for improving data detection by correcting errors due to a dominant error event in an optical PRML read channel. 
     BACKGROUND 
     DVD, an acronym for Digital Video Disc or Digital Versatile Disc, is a relatively new type of Compact-Disc Read-Only-Memory (CD-ROM) with a minimum capacity of approximately 4.7 gigabytes. FIG. 1 illustrates in block diagram form apparatus for recording to and reading data from DVD  22 . Recording Unit  20  takes digital data m k  and records it on DVD  20 . (The subscript “k” is used throughout to indicate generally a time-variant signal and the subscript “kn” indicates the value of a time-variant signal at a time k+n.) DVD player  24  includes Optical Pick-up Unit (OPU)  26 , and an optical Partial Response Maximum Likelihood (PRML) Read Channel (Read Channel)  30 . OPU  26  converts information read from DVD  22  into an analog RF signal on line  27 . Read Channel  30  takes this RF signal and generates a digital signal q k . Read Channel  30  includes Automatic Gain Control (AGC) &amp; Equalization Circuitry  32 , Analog-to-Digital Converter (ADC)  34  and Viterbi Decoder  36 . AGC &amp; Equalization Circuitry  32  filters and limits the voltage magnitude of the RF signal on line  27 , producing the analog signal on line  33 . ADC  34  samples the analog signal on line  33  and produces a multi-bit digital signal, y k , on line  35  that represents the magnitude of the analog signal on line  33 . Viterbi Decoder  36  analyzes the y k  signal over several sample values and determines the most likely value represented by each sample. Viterbi Decoder  36  represents the most likely values via its output signal, q k , on line  40 , which is a single bit in a Non-Return to Zero Inverted (NRZI) format. Ideally, q k  should be identical to m k ; however, errors prevents this. 
     Much of the error in q k  is caused by baseline wandering. As used herein, baseline wandering refers to low frequency disturbances of a radio frequency signal. FIG. 2A illustrates an ideal input signal to ADC  34 , which is free from baseline wandering. The signal graphed in FIG. 2A remains centered about a baseline, zero volts in this example, throughout the illustrated time period. FIG. 2B illustrates a second input signal to ADC  34 , which is subject to baseline wandering. The illustrated input signal has no fixed baseline; i.e., it exhibits a variable DC offset. The variable DC offset of the radio frequency signal produces a time variable error in y k , the output of ADC  34 . FIG. 3A is a histogram of the y k  signal given an input signal to ADC  34  that is free from baseline wandering; i.e., given the signal of FIG.  2 A. In the absence of baseline wandering, the histogram of the y k  signal represents five distinctive sample values, 1, ⅔, 0, −⅔ and −1. Baseline wandering of the signal to be sampled by ADC  34  produces a quite different histogram. FIG. 3B is a histogram of the y k  signal given the input signal of FIG.  2 B. FIG. 3B indicates that ADC  34  does not produce distinct sample values in the presence of baseline wandering, producing instead every sample value between approximately −1.25 to 1.25. FIG.  3 C through FIG. 3G are individual histograms for each ideal sample value. Thus, FIG. 3C is a histogram of sample values corresponding the ideal value of 1; FIG. 3D is a histogram of sample values corresponding to the ideal value of ⅔; FIG. 3E is a histogram of sample values corresponding to the ideal value of 0; FIG. 3F is a histogram of sample values corresponding to the ideal value of −⅔; and FIG. 3G is a histogram of sample values corresponding to the ideal value of −1. These histograms reveal that baseline wandering destroys the one to one correspondence between ideal sample values and the values output by ADC  34 . For example, FIGS. 3C and 3D indicate that a y k  value of +¾ may be due to either an ideal sample value of either 1 or ⅔. Thus, a need exists for circuitry to correct data detection errors caused by baseline wandering. 
     SUMMARY 
     The apparatus of the present invention corrects a data detection error caused by baseline wandering in an optical PRML read channel. The apparatus includes error detection circuitry and error correction circuitry. The error detection circuitry monitors a serial output signal from the optical PRML read channel and a first set of input signals to the optical PRML read channel to detect an error event associated with baseline wandering. The error detection circuitry deems an error event to have occurred when three conditions are satisfied. First, a bit sequence represented by the serial output signal matches a first bit sequence associated with the error event. Second, a first difference in a first set of consecutive values represented by the first set of input signals is within a first range of values associated with the error event. Third, a second difference in a second set of consecutive values of the first input signal is within a second range of values associated with the error event. The error detection circuitry responds to satisfaction of all three conditions by asserting an error signal. The error correction circuitry responds to assertion of the error signal by modifying a pair of consecutive bits represented by the serial output signal to generate a corrected output signal having a second bit sequence. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Additional features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which: 
     FIG. 1 illustrates prior art apparatus for recording to, and reading data from, a DVD. 
     FIG. 2A illustrates an ideal input signal, free from baseline wandering, to the ADC of FIG.  1 . 
     FIG. 2B illustrates a input signal to the ADC of FIG. 1, which is subject to baseline wandering. 
     FIG. 3A is a histogram of the output signal from the ADC of FIG. 1 given an input signal that is free from baseline wandering. 
     FIG. 3B is a histogram of the output signal from the ADC of FIG. 1 given the input signal of FIG.  2 B. 
     FIG. 3C is a histogram of sample values corresponding to the ideal value of 1. 
     FIG. 3D is a histogram of sample values corresponding to the ideal value of ⅔. 
     FIG. 3E is a histogram of sample values corresponding to the ideal value of 0. 
     FIG. 3F is a histogram of sample values corresponding to the ideal value of −⅔. 
     FIG. 3G is a histogram of sample values corresponding to the ideal value of −1. 
     FIG. 4 illustrates an optical PRML Read Channel including the Post-Processor of the present invention. 
     FIG. 5 illustrates trellis diagrams for when the ideal NRZ bit stream is [0000111000 b ], but is falsely detected by the PRML read channel as [0001111000 b ]. 
     FIG. 6 illustrates trellis diagrams for when the ideal NRZ bit [1111000111 b ] is falsely detected by the PRML read channel as [1110000111 b ]. 
     FIG.7 illustrates an embodiment of the Post-Processor of FIG.  4 . 
     FIG. 8 illustrates an embodiment of the Output Sequence Detector of FIG.  7 . 
     FIG. 9 illustrates an embodiment of the First Difference Comparator of FIG.  7 . 
     FIG. 10 illustrates an embodiment of the Second Difference Comparator of FIG.  7 . 
     FIG. 11 illustrates an embodiment of the Error Correction Circuitry of FIG.  7 . 
     FIG. 12 illustrates the timing relationship between the various signals for the Error Correction Circuitry of FIG.  11 . 
    
    
     DETAILED DESCRIPTION 
     FIG. 4 illustrates in block diagram form optical PRML Read Channel (Read Channel)  50 , which includes Post-Processor  52  of the present invention. Post-Processor  52  improves data detection within Read Channel  50  by correcting errors in the q k  signal that result from a dominant error event produced by baseline wandering. Briefly described, Post-Processor  52  first determines whether a bit sequence of the q k  signal matches that associated with the dominant error event. Next, Post-Processor  52  compares difference sequences of the y k  signal to difference sequences known to produce the dominant error event. Post-Processor  52  deems the error event to have occurred if the q k  bit sequence matches that associated with the dominant error event and the associated difference sequences match those known to produce to the dominant error event. If the dominant error event has occurred, Post-Processor  52  corrects the q k  signal to produce the corrected output signal, p k . 
     A. The Dominant Error Event 
     Prior to a detailed discussion of Post-Processor  52 , consider first the dominant error event within Read Channel  50 . Produced by baseline wandering, the dominant error event causes a m k  NRZI bit sequence of x000100100x b  (the earliest bit occupies the far left position of the bit sequence) to be detected as a q k  NRZI bit sequence of x001000100x b . (Bolding in the m k  and q k  NRZI bit sequences indicates the location of the error event.) The dominant error event can be described in terms of states of Viterbi Decoder  36 , which are defined by Non-Return to Zero (NRZ) format, rather than NRZI format. The dominant error event can be produced by either of two complementary cases: 
     (1) The transmitted NRZ bit stream is [0000111000 b ], but is falsely detected as the NRZ bit stream of [0001111000 b ]; and 
     (2) The transmitted NRZ bit stream is [1111000111 b ], but is falsely detected as the NRZ bit stream of [1110000111 b ]. 
     The trellis diagrams of FIGS. 5 and 6 illustrate the sequence of events leading to each of the two complementary cases. Each trellis diagram includes a number of linked circles, which represent Viterbi Decoder states. Each trellis diagram includes two sequences of states, the ideal sequence of states and the falsely detected sequence of states. The NRZ states of the ideal sequence are linked by dashed lines, while the NRZ states of the falsely detected sequence are linked by solid lines. The identity of each state is identified by a three bit number, s k , within the state, which is defined as [p k2 , p k1 , p k0 ]. Immediately to the right of each state is a box indicating the input, p k ,and the output, y k , for the state. For all states p k  is a member of {1,0} and y k  is a member of {3, 2, 0, −2, 3} and is equal to ½p k3 +p k2 +p k1 +½p k0 . 
     FIG. 5 illustrates trellis diagrams for Case  1 : the ideal NRZ bit stream is [00001110000 b ], but is falsely detected as [0001111000 b ]. States  72 - 76  indicate the erroneous sequence of states, while States  82 - 86  indicate the ideal sequence of States. While in State  70 , rather than generating a p k  of 0, Viterbi Decoder  36  generates a p k  of 1. This single instance of an erroneous value of p k ,subsequently causes Viterbi Detector  36  to branch through States  72 - 76 . This sequence of States produces four erroneous values of [y k3 , y k2 , y k1  y k0 ] equal to [3, 2, 0, −2]. This sequence of states also produce a difference sequence [(y k3 −y k2 ), (y k2 −y k1 ), (y k1 −y k0 )] equal to [1, 2, 2]. In contrast, the correct sequence of States  82 - 86  produces [y k3 , y k2 , y k1 , y k0 ] equal to [2, 0, 2, −3] and a difference sequence [(y k3 −y k2 ), (y k2 −y k1 ), (y k2 −y 0 )] equal to [2, 2, 1]. 
     FIG. 6 illustrates trellis diagrams for Case  2 : The transmitted NRZ bit [1111000111   b   ] is falsely detected as [1110000111 b ]. States  92 - 96  indicate the erroneous sequence of states, while States  100 - 104  indicate the ideal sequence. While in State  90 , rather than generating a p k  of 1, Viterbi Decoder  36  outputs a p k  of 0. This single instance of an erroneous value of p k , subsequently causes Viterbi Detector  36  to branch through States  92 - 96 . This sequence of States produces [y k3 , y k2 , y k1 , y k0 ] equal to [−3, −2, 0, 2] and a difference sequence [(y k3 −y k2 ), (y k2 −y k1 ), (y k1 −y k0 )] equal to [−1, −2, −2]. In contrast, the correct sequence of States  100 - 104  produces [y k3 , y k2 , y k1 , y k0 ] equal to [−2, 0, 2, 3] and a difference sequence [(y k3 −y k2 ), (y k2 −y k1 ), (y k1 −y k0 )] equal to [−2, −2, −1]. 
     Comparison of output and difference sequences for both the correct and erroneous sequences of States for Cases  1  and  2  reveals that their absolute values are the same. For example, the absolute values of the difference sequence for the erroneous sequence of States for Case  1  is [|1|, |2|, |2|] and the absolute values of the difference sequence for the erroneous sequence of States for Case  2  is [|−1|, |−2|, |−2|]. The absolute values of the difference sequences for the correct sequence of States for Cases  1  and  2  is [2, 2, 1]. Combining knowledge of the absolute values of difference sequences for the correct and incorrect sequence of States with knowledge of the sequence of input values associated with the dominant error event permits correction and detection of errors caused by the dominant error event. In particular, an error associated with the dominant error event may be detected by searching for a sequence of p k  values of [10001 b ] and determining whether the resulting input difference sequence [|y k3 −y k2 |, |y k2 −y k1 |, |y k1 −y k0 |] is closer to the absolute values for the correct difference sequence, [2, 2, 1], or the absolute values for the erroneous difference sequence, [1, 2, 2]. 
     B. The Post-Processor 
     FIG. 7 illustrates Post-Processor  52  in block diagram form. Post-Processor  52  includes Error Detection Circuitry  100  and Error Correction Circuitry  102 . Error Detection Circuitry  100  examines the signals input to and output from Viterbi Decoder  36  to determine whether an error associated with the dominant error event has occurred. If so, Error Detection Circuitry  100  informs Error Correction Circuitry  102  by asserting the Error signal on line  104 . Error Correction Circuitry  102  responds to assertion of the Error signal by replacing the erroneous sequence of bits of q k  with the correct sequence of bits. 
     Error Detection Circuitry  100  includes Output Sequence Detector  110 , Difference Sequence Comparator  114  and logical AND gate  120 . Output Sequence Detector  110  examines the output from Viterbi Detector  36 , the q k  signal, to determine whether the current output sequence matches that associated with the dominant error event. In particular, Output Sequence Detector  110  determines whether [q k4 , q k3 , q k2 , q k1 , q k0 ] equals [10001 b ]. If so, Output Sequence Detector  110  asserts the Sequence Detect signal on line  112 . Difference Sequence Comparator  114  takes the input to Viterbi Decoder, the y k  signal, and generates a difference sequence that it compares to the incorrect difference sequence. In particular, Difference Sequence Comparator  114  compares input difference sequence [|y k3 −y k2 |, |y k2 −y k1 |, |y k1 −y 0 |] to [2, 2, 1]. If the Difference Sequence Comparator  114  determines that the two sequences resemble one another, it asserts a First and a Second Difference Detect signal. These two signals, along with the Sequence Detect signal, are input to logical AND gate  120 . When all three of its input signals are asserted, logical AND gate asserts the Error signal on line  104 , indicating to Error Correction Circuitry  102  that a sequence of bits output by Viterbi Decoder  36  should be corrected. In particular, the Error signal indicates that an error occurred five clock cycles ago. This effects the design of Error Correction Circuitry  102 . 
     Difference Sequence Comparator  114  includes First Difference Comparator  130  and Second Difference Comparator  136 . First Difference Comparator  130  examines the |y k3 −y k2 | term of the input difference sequence and compares it to a first range of values about the value associated with the dominant error event; i.e. 2. When |y k3 −y k2 | is approximately 2, then First Difference Comparator  130  asserts the First Difference Detect signal. Second Difference Comparator  136  examines the |y k0 −y k1 | term of the input difference sequence and compares it to a second range of values about the value associated with the dominant error event, 1. When |y k1 −y k0 | is approximately 1, Second Difference Comparator  136  asserts the Second Difference Detect Signal. Difference Sequence Comparator  114  does not include circuitry for examining difference term |y k2 −y k1 | because the same value is associated with both the correct and dominant error event difference sequences. 
     Error Correction Circuitry  102  includes First Delay Circuit  150 , Second Delay Circuit  154  and Bit Flip Circuitry  156 . First Delay Circuit  150  receives on line  111  the r k  signal, a delayed version of q k , which it further delays to generate the s k  signal on line  152 . Second Delay Circuit  154  receives the Error signal on line  104 , which it further delays prior to coupling it to Bit Flip Circuitry  156 . In response to the Delayed Error signal, Bit Flip Circuitry  156  flips those bits of the s k  signal representing q k0  and q k1  to generate the corrected p k  signal. 
     B1. The Output Sequence Detector 
     FIG. 8 illustrates, in block diagram form, Output Sequence Detector  110 , which determines whether [q k4 , q k3 , q k2 , q k1 , q k0 ] matches the bit sequence associated with the dominant error event; i.e., [11000 b ]. Output Sequence Detector  110  includes serially-coupled Latches  170 ,  172 ,  174 ,  176  &amp;  180  and logical AND gate  182 . The first of the serially-coupled Latches, Latch  170  has its D-input coupled to the NRZI output of Viterbi Decoder  36 , the q k  signal. The Q output of Latch  170  is used to route the value of q k4  to logical AND gate  182 . The Q output of Latch  170  is coupled to the D-input of Latch  172 , whose Q Bar output is coupled to logical AND gate  182  to represent the inverse of q k3 . Latch  174  receives as its input the Q output of Latch  172 . The Q Bar output of Latch  174  is coupled to logical AND gate  182  to represent the inverse of q k2 . The Q output of Latch  174  is coupled to the input of Latch  176 , which couples its Q Bar output to logical AND gate  182  to represent the inverse of q k1 . Latch  180  receives its input from the Q output of Latch  176 . The Q output of Latch  180  is coupled to logical AND gate  182  to represent q k0  and is coupled to Error Correction Circuitry  102  as the r k  signal. Logical AND gate  182  asserts its output, the Seq Detect signal on line  112 , whenever each signal input to it is asserted; i.e. when q k4 =1, inverse(q k3 )=1, inverse(q k2 )=1, inverse(q k1 )=1, and q k0 =1, which occurs only when [q k4 , q k3 , q k2 , q k1 , q k0 ] equals [10001 b ]. 
     B2. The First Difference Comparator 
     FIG. 9 illustrates, in block diagram form, First Difference Comparator  130 , which determines whether the |y k3 −y k2 | term of the input difference sequence is approximately equal to the value associated with the dominant error event sequence; i.e. 2. First Difference Comparator  130  includes Third Delay Circuit  190 , serially-coupled Latches  194 ,  196  &amp;  198 , Subtractor  200 , Absolute Value Circuit  202 , Less-Than-Equal Circuit  208 , Greater-Than Circuit  214 , and logical AND gate  218 . Third Delay Circuit  190  receives as its input the multi-bit y k  signal, which it delays and couples to Latch  194 . Latches  194  &amp;  196  further delay this signal to generate a representation of y k3 , which is coupled to Subtractor  200  and Latch  198 . Latch  198  delays its input to generate as its output a signal representing y k2 . Subtractor  200  subtracts y k3  from y k2  to generate a First Difference signal on line  201 . The First Difference signal is coupled to Absolute Value Circuit  202 , which determines the absolute value of y k3 −y k2  and represents it as the First Absolute Value signal on line  204 . Less-Than-Equal Circuit  208  determines whether the value represented by the First Absolute Value signal is less than, or equal to 2.5. If so, Less-Than-Equal Circuit  204  asserts its output signal, LTE, on line  210 . Greater-Than Circuit  214  operates simultaneous to Less-Than-Equal Circuit  208 , determining whether the value represented by the First Absolute Value signal is greater than 1.5. If so, Greater-Than Circuit  214  asserts its output signal, GT 1 , on line  216 . When both the LTE 1  and GT 1  signals are asserted logical AND gate  218  asserts its output signal, 1 st  Dif Detect, indicating that the value of the |y k3 −y k2 | term of the input difference sequence is within a range of values associated with the dominant error event. 
     B3. The Second Difference Comparator 
     FIG. 10 illustrates, in block diagram form, Second Difference Comparator  136 , which determines whether the |y k1 −y k0 | term of the input difference sequence is approximately equal to the value associated with the dominant error event; i.e., 1. Second Difference Comparator  136  includes Latches  230  &amp;  232 , Subtractor  234 , Absolute Value Circuit  240 , Less-Than-Equal Circuit  246 , Greater-Than Circuit  252  and logical AND gate  256 . Latch  230  receives as its input the y k2  signal from First Difference Comparator  130 , which it further delays to generates its output, the y k1  signal. Latch  230  couples the y k1  signal to both Latch  232  and Subtractor  234 . Latch  232  delays the y k1  signal to generate the y k0  signal, which it couples to Subtractor  234 . Subtractor  234  subtracts y k0  from y k1  to generates the Second Difference signal, which it outputs on line  236 . Absolute Value Circuit  240  generates the Second Absolute Value signal by taking the absolute value of the Second Difference signal. Less-Than-Equal Circuit  246  determines whether the Second Absolute Value is less than, or equal to, 1.5. If so, Less-Than-Equal Circuit  246  asserts its output, the LTE 2  signal. Operating simultaneous to Less-Than-Equal Circuit  246 , Greater-Than Circuit  252  determines whether the Second Absolute Value is greater than 0.5. If so, Greater-Than Circuit  252  asserts its output, the GT 2  signal. When both the LTE 2  and GT 2  signals are asserted logical AND gate  256  asserts its output signal, 2nd Dif Detect, indicating that the value of the |y k1 −y k0 | term of the input difference sequence is within a range of values associated with a dominant error event. 
     B4. The Error Correction Circuitry 
     FIG. 11 illustrates, in block diagram form, Error Correction Circuitry  102 , which corrects the Viterbi Decoder output when a dominant error event is detected. In particular, when [q k1 , q k0 ] is erroneously detected as [01 b ] Error Correction Circuitry  102  forces [q k1 , q k0 ] to equal [10 b ] by flipping two bits. Error Correction Circuitry  102  includes First Delay Circuit  150 , Second Delay Circuit  154  and Bit Flip Circuitry  156 . First Delay Circuit  150  delays the r k  signal to produce the s k  signal on line  278  and Second Delay Circuit  154  delays the Error signal to produce the Enable signal on line  155 . Bit Flip Circuitry  156  responds to assertion of the Enable signal by simultaneously flipping q k1  while it is represented by the s k  signal and q k0  while it is represented by the u k  signal on line  283 . 
     First Delay Circuit  150  is realized as four serially coupled Latches  270 ,  272 ,  274  &amp;  276  and outputs the s k  signal on line  278 . Second Delay Circuit  154  is also realized by five serially coupled latches (not illustrated) to produce the Enable signal on line  155 . Bit Flip Circuitry  156  includes logical XOR gate  280 , Latch  282  and logical XOR gate  284 . Logical XOR gate  280  performs an exclusive OR operation on the s k  and Enable signals to flip q k1 , producing its output signal t k  on line  281 , which is coupled to Latch  282 . Latch  282  couples its output, the u k  signal, on line  283  to logical XOR gate  284 . Logical XOR gate performs an exclusive OR operation on the u k  and Enable signals to produce the p k  signal. 
     FIG. 12 illustrates the timing relationship between the various signals relevant to Error Correction Circuitry  102 . The transitions of the clock, CK signal  298 , to which Error Correction Circuitry  102  responds are labeled “k 0 , k 1 , k 2  . . . ” etc, with lower numbered transitions occurring earlier than higher numbered transitions. In FIG. 12, the error in the q k  signal  300  occurs at q k0  and q k1 ; however, this error is not recognized by Error Detect Circuitry  102  until CK k5 , at which time Error signal  304  is asserted. (The location of the representation of q k0  and q k1  in the signals of FIG. 12 is indicated by a circle. ) At this point the r k  signal represents q k0 . Thus, by the time an error is detected the erroneous bits, q k0  and q k1 , are beginning to exit Output Sequence Detector  110 . First and Second Delay Circuits  150  and  154  adjust the relative delay between the Enable signal  306  and the s k  signal  308  so that Enable signal  306  is active while both q k0  and q k1  are represented by Bit Flip Circuitry  156 . In response to the four clock cycle delay provided by First Delay Circuit  150 , during CK k9  the s k  signal  308  represents q k0  and during CK k10  the s k  signal  308  represents q k1 . Consequently, during CK k10  Bit Flip Circuitry  156  represents both q k0 , via the u k  signal  314 , and q k1 , via the t k  signal  312 . Second Delay Circuit  154  delays the Error signal  304  by five clock cycles to bring the Enable signal  306  active at CK k10 . 
     During clock cycle CK k9  the inputs to logical XOR gate  280  are S k9 , representing q k0 , and Enable signal  306 , which is inactive. Logical XOR gate  280  responds to these inputs by bringing t k9  to a voltage level representative of a logical 1. Latch  282  then latches t k9 . The next clock cycle, CK k10 , the inputs to logical XOR gate are s k10 , which now represents q k1 , and Enable signal  306 , which is now active. At c k10 , logical XOR gate  280  outputs a voltage level representative of a logical 1, thereby flipping q k1  as subsequently represented by the t k  signal  312  and Bit Flip Circuitry  156 . In response to CK k10 , Latch outputs t k9  as u k10 . During CK k10  Logical XOR gate  284  responds to the high levels of u k10  and the Enable signal  306 , by outputting a voltage level representative of a logical 0. This flips the subsequent representation of q k0  from a logical 1 to a logical 0. Latch  282  responds to CK k10  by latching in t k10 , which it outputs during CK k11  as a representation of q k1 , via u k11 . Logical XOR gate responds to u k11  and the inactive Enable signal  306  by outputting a logical high. 
     ALTERNATE EMBODIMENTS 
     While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.