Abstract:
A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.

Description:
TECHNICAL FIELD 
     The present invention regards a process for manufacturing buried channels and cavities in semiconductor material wafers. 
     BACKGROUND OF THE INVENTION 
     As known, present applications require channels or cavities inside a silicon substrate, for example for making suspended masses of microactuators and/or sensors of various kinds, such as speed, acceleration, and pressure sensors, or for insulating electronic components. 
     At present, buried cavities can be made basically in two ways. According to a first solution, shown in FIG. 1, two monocrystalline silicon wafers  1 , appropriately excavated so as each of them presents a half-cavity, are bonded together using an adhesive layer (for example, silicon oxide  2 ) so that the two half-cavities form a buried cavity  3 . 
     According to a second solution, shown in FIG. 2, a wafer  1  of monocrystalline silicon, appropriately excavated so as to present final cavities  4 , is bonded to a glass layer  5  (anodic bonding process). 
     Such solutions are costly, highly critical, have low productivity, and are not completely compatible with the usual technological phases involved in the manufacture of microelectronic components. In addition, in the solution of FIG. 2, it is not always possible to make also an integrated circuit. 
     SUMMARY OF THE INVENTION 
     The embodiments of the present invention provide a process that eliminates the disadvantages of the known solutions. 
     According to an embodiment of the present invention, a process for manufacturing buried cavities in semiconductor material wafers and a semiconductor material wafer are provided. The process includes forming a nucleus region in a monocrystalline body surrounded by a protective structure, forming a cavity beneath the nucleus region, removing at least a top portion of the protective structure, and growing an epitaxial layer on the body and over the nucleus region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For an understanding of the present invention, a preferred embodiment thereof is now described, as a non-limiting example, with reference to the attached drawings, wherein: 
     FIG. 1 shows a cross section through a semiconductor material wafer made according to a known solution; 
     FIG. 2 presents a cross section of another known solution; 
     FIGS. 3 to  11  show cross sections through a semiconductor material wafer in successive manufacturing steps according to the present invention; and 
     FIG. 12 shows, on a reduced scale, the wafer obtained with the manufacturing process according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 shows a wafer  10  of monocrystalline silicon formed by a substrate  11  having a surface  12 . On the surface  12  an etching-aid region  13  is formed, and has a thickness preferably comprised between 450 and 1000 nm; the etching-aid region  13  is obtained, for example, by chemical vapor deposition (CVD) of a polycrystalline silicon layer and subsequent definition of the polycrystalline silicon layer, using a resist mask. The etching-aid region  13  has the function of modifying the shape of the desired cavities or channels, as explained hereinafter. 
     Subsequently, a thermal oxidation is carried out (FIG.  4 ); a first pad layer  15  of silicon oxide is then grown on the etching-aid region  13  and on the surface  12  of the wafer  10  where the latter is not covered by the etching-aid region  13 . The first pad layer  15  has, for example, a thickness comprised between 20 and 100 nm. Thereafter a first etch-shielding layer  16  of silicon nitride having a thickness, for example, comprised between 90 and 200 nm, and then a nucleus layer  17  of polycrystalline silicon having a thickness comprised between 1 and 2 μm are deposited. The nucleus layer  17  is preferably deposited by CVD. A thermal oxidation is then carried out, forming a second pad layer  18  of silicon oxide, having a thickness comprised, for example, between 20 and 60 nm, on the nucleus layer  17 ; and then a second etch-shielding layer  19  of silicon nitride is deposited, and has a thickness comprised, for example, between 90 and 200 nm. In this way, the intermediate structure of FIG. 4 is obtained, which presents a stack of layers  16 - 19 . 
     A resist mask  20  is then formed (FIG. 5) and covers the entire wafer  10 , except for a window  21  above the etching-aid region  13 . Using the resist mask  20 , the second etch-shielding layer  19 , the second pad layer  18 , the nucleus layer  17 , and the first etch-shielding layer  16  are etched in succession by dry and wet etchings. Etching ends automatically on the first pad layer  15 . At the end of etching, a hole  22  extends through the stack of layers  16 - 19  down to the first pad layer  15 . Advantageously, the width of the hole  22  is comprised between 1 and 5 μm, and its length and shape (in the direction perpendicular to the plane of the drawing) are determined by the length and shape of the etching-aid region  13  and, ultimately, by the desired characteristics of the cavity to be made. 
     Subsequently (FIG.  6 ), the resist mask  20  is removed, and the exposed surface of the nucleus layer  17  facing the hole  22  is thermally oxidized and forms an oxide portion  24  having a thickness comprised between, for example, 20 and 100 nm and joining to, without solution of continuity, the second pad layer  18 . 
     A third etch-shielding layer  25  of silicon nitride is then deposited and has a thickness comprised preferably between 90 and 200 nm (FIG. 7) and completely coats the walls and the bottom of the hole  22 . The third etch-shielding layer  25  is then anisotropically etched and is removed in the horizontal portions on the second etch-shielding layer  19  and on the bottom of the hole  22 . A coating region  25 ′ remains on the lateral walls of the hole (now indicated with  22 ′) and joins, without solution of continuity, with the first and second etch-shielding layers  16 ,  19 , also of silicon nitride, forming with the latter a protective structure  26 , which completely envelops the second nucleus layer  17  (FIG.  8 ). 
     Next, the uncovered portion of the first pad layer  15 , beneath the hole  22 ′, is dry or wet etched, in a time controlled way, uncovering the etching-aid region  13 . The intermediate structure shown in FIG. 8 is thus obtained. 
     The substrate  11  is then etched, in a time controlled way, using tetramethylammoniumhydroxide (TMAH) having the formula (CH 3 ) 4 NOH (FIG.  9 ). The shape of the etching is determined by both the presence of the etching-aid region  13  and the etch directionality. In fact, since the etching-aid region  13  is of polycrystalline silicon, it is removed preferentially with respect to the substrate  11 , which is of monocrystalline silicon, and determines the etch extent, parallel to the surface  12 . On the other hand, with the structure of FIG. 9, where the surface  12  of the wafer has orientation &lt;100&gt;, the oblique etching speed, according to the orientation &lt;111&gt;, is much lower than the etching speed according to the orientation &lt;100&gt; (V &lt;111&gt; &lt;&lt;V &lt;100&gt; ), and the monocrystalline silicon of the substrate  11  is preferentially etched along the vertical. 
     It follows that, on the whole, etching occurs according to fronts having a width determined by the progressive removal of the etching-aid region  13 , and extends in depth into the substrate  11 , as shown in FIG. 9, where the dashed lines and the dashed and dotted lines indicate successive etching fronts, and the arrows indicate the etching advancement direction. At the end of etching, after a preset time, dependent on the width of the etching-aid region  13 , a tub shaped cavity  30  is formed in the substrate  11 . In this step, the nucleus layer  17  is protected by the protective structure  26 . 
     The wall of the cavity  30  is then thermally oxidized and forms a protective layer  31  (FIG. 10) having a thickness preferably comprised between 60 and 300 nm. 
     Subsequently (FIG.  11 ), the nitride material is etched, removing the second etch-shielding layer  19 , and then the second oxide pad layer  18  is etched. Given the greater thickness of the protective layer  31 , as compared to the second pad layer  19 , in this step the protective layer  31  is, at most, removed only partially. 
     Using a resist mask, the nucleus layer  17  is suitably shaped so as to be removed everywhere, except above and around the cavity  30 ; in addition, the first etch-shielding layer  16  and the first pad layer  15  are etched and removed where they are exposed. Consequently, the surface  12  of the substrate  11  is once more exposed, except for at the cavity  30 . 
     Finally (FIG.  12 ), epitaxial growth is carried out starting from the substrate  11  (where this is not covered) and from the nucleus layer  17 . In particular, a so-called pseudo-epitaxial layer  33  is formed by a monocrystalline portion  33   a  on the substrate  11  and a polycrystalline portion  33   b  on the nucleus layer  17 , these portions being separated by a transitional region  33   c , as shown in FIG.  12 . The substrate  11  and the pseudo-epitaxial layer  33  thus form a wafer  34 . In addition, the epitaxial growth over the nucleus layer  17  takes place also horizontally, closing the hole  22 ′. Consequently, the cavity  30  is closed on all its sides and is completely embedded in the wafer  34 . 
     The wafer  34  then undergoes further processing steps according to the devices to be made. In particular, in the polycrystalline portion  33   b , suspended structures are made, such as membranes, induction coils, accelerometers, etc., and in the monocrystalline portion  33   a  of the pseudo-epitaxial layer  33  electronic processing and control components are integrated. 
     The advantages of the described process are the following: first, the process enables forming closed cavities in a silicon wafer with process steps that are fully compatible with semiconductor manufacturing processes. The process does not present particular critical aspects, and enables good productivity, contained costs, and the integration of microstructures and electronic components. 
     Finally, it is clear that modifications and variations can be made to the process described and illustrated herein, all of which fall within the scope of the invention, as defined in the attached claims. In particular, the size, shape and number of holes  22 ′ are suitably chosen on the basis of the size and shape of the cavity  30  to be formed and of the characteristics of the TMAH etching on the substrate  11 . In particular, in the case of a hole  22 ′ of an elongated shape, it is possible to obtain elongated channels; in the case of suspended structures of large area, it is possible to make a number of holes  22 ′ above a same etching-aid region  13  so as to form a number of initial cavities which then join up to form a final, large size cavity parallel to the surface  12  of the substrate  11 . 
     In addition, the thermal oxidation used to form the protective layer  31  may be omitted, and the nucleus layer  17  can be made in two steps by depositing a thin vapor-phase layer and then growing a polycrystalline layer epitaxially up to the desired thickness. 
     Finally, after forming the cavity  30 , the removal of the second etch-shielding layer  19  and of the second pad layer  18  can be carried by wet etching, also removing the coating region  25 ′ and the oxide portion  24 . 
     While a preferred embodiment of the invention has been illustrated and described, it is to be understood that various changes can be made therein without departing from the spirit and scope thereof. Thus, the invention is to be limited only by the scope of the claims that follow and the equivalents thereof.