Abstract:
A data transmission method and a transmission/reception device are described, the data transmission taking place via intermediate memories without the transmitter receiving direct feedback from the receiver regarding the success of the data transmission. Furthermore, at least one transmission and/or reception device is described which forms an interface between at least two control units and has intermediate memories.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method of data transmission and a transmission and reception device therefor.  
         BACKGROUND INFORMATION  
         [0002]    German Published Patent Application No. 1 01 10 042.6 (not a prior publication) of Mar. 2, 2001 describes a distributed control and analysis system in motor vehicles, where decentralized control units (such as sensors having appropriate electronics for control and/or analysis) are connected to a central control unit via a point-to-point link for data exchange. A data line connects the central control unit to each decentralized unit; both the decentralized control units and the central control unit are designed for transmitting and receiving signals (data). No appropriate configuration of the transmission and reception device or the appropriate method of data transmission between these components is described in the aforementioned document. The preferred application refers to the field of environment sensors in motor vehicles, in particular radar sensor systems.  
         SUMMARY OF THE INVENTION  
         [0003]    Advantageously, data to be transmitted is advantageously temporarily stored in the area of the interface between the central and the decentralized element until it is picked up by the receiving control unit. Having a plurality of intermediate memories through which the data to be transmitted is pushed forward with each pickup operation as in a FIFO memory is particularly advantageous. In this way, the load on the interface, in particular of the transmitting control unit, is reduced.  
           [0004]    It is advantageous that no retransmission of data is required if the data is not picked up or if a transmission error occurs. The intermediate memories of the interface are filled sequentially until no more memory location is available. The load on the transmitter is thus reduced.  
           [0005]    Furthermore, the transmitting control unit receives no direct feedback on whether or not the transmitted data has been picked up by the receiving control unit. A failed transmission is recognized by a pile-up of transmitted data. The transmitting control unit is unable to transmit further data in this event. This has the advantage that no feedback from receiver to sender is required, which reduces the load on the interface and the components involved. Yet the transmitter receives feedback in the event of a failed transmission. The transmitter learns indirectly through this indirect handshake whether or not the receiver has picked up data.  
           [0006]    The data load on the interface is reduced substantially due to the omission of feedback and the omission of retransmission of data. The transmitting and receiving control unit only has to manage transmit and receive operations; therefore the program run time in the particular component is substantially reduced, in particular when the subroutine for access to the interface is called. Also in this way the load on the interface and thus on the components involved is substantially reduced.  
           [0007]    In a preferred embodiment, the data transmission method and the data transmission and reception device are used in conjunction with a system for environment sensing in a motor vehicle, where a predefined number of decentralized control units (such as sensors having analysis and control electronics) are connected to a central control unit. The above-described method is particularly well suited for a point-to-point wiring, because it is capable of providing a plurality of interfaces between a central control unit and a plurality of decentralized control units in a simple manner.  
           [0008]    However, the interface having the above-mentioned advantages is also well suited as an interface between two individual control units.  
           [0009]    It is particularly advantageous that the advantages in communication between control units occur in both directions.  
           [0010]    The above-described procedure having the advantage of reducing the load on the interface and the components involved is also used to advantage in other data communication interfaces, both in other automotive applications and in non-automotive applications. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 shows a schematic diagram of a decentralized control system using the example of the preferred application of an environment sensor system based, for example, on radar sensors.  
         [0012]    [0012]FIG. 2 shows the details of the interface between the central control units and the decentralized control units.  
         [0013]    [0013]FIG. 3 shows the response of the interface in the event of a data pile-up. 
     
    
     DETAILED DESCRIPTION  
       [0014]    [0014]FIG. 1 shows a schematic diagram of a decentralized control system having a central control unit  10 , which may be connected to other control units via a data communication system  12 . In the example shown, a total of six decentralized control units  12 ,  14 ,  16 ,  18 ,  20 ,  22  are connected to central control unit  10  by point-to-point links. A bidirectionally operated interface  24 ,  26 ,  28   30 ,  32 ,  34  is provided between the central control unit and each decentralized control unit. In the preferred embodiment, this interface is a current-based dual wire interface. Data is exchanged between the central control unit and the decentralized control units via the particular interface, preferably the central control unit both transmitting data to and receiving data from the decentralized control units, and each decentralized control unit transmitting data to and receiving data from the central control unit.  
         [0015]    Environment sensing, using radar, infrared or ultrasound sensors, lasers, or video cameras, for example, in motor vehicles represents a preferred field of application. These sensors and thus the decentralized control units are located on the outside of the vehicle, for example, in the bumpers, on the vehicle side, while the central control unit is mounted at a central location, for example, in the vehicle passenger compartment. Thus this is a system having distributed, intelligent components, i.e., components provided with at least one processor. Depending on the application, more or less decentralized control units may be provided. In addition, the procedure described in the following may also be used with any other interface between two control units where data is to be exchanged placing the least possible load on the interface and the components involved. The application is not restricted to environment sensing in motor vehicles, but may also be used in other decentralized systems in motor vehicles, for example, brake systems, engine control systems, etc. or in non-automotive systems.  
         [0016]    [0016]FIG. 2 shows the interface between a first and a second control unit in a preferred configuration in greater detail. FIG. 2 shows central control unit  100 , a selected decentralized control unit  120 , and interface  110  between the two. The particular control units include at least one processor  1000 , which has an SPI interface  1002  among other things. Processor  1000  communicates with a transmitting and/or receiving module  1004  via this interface. Therefore, this module also has an SPI interface  1006  as an interface to processor  1000 . Furthermore, the interface module has at least one transmit memory  1008  and a current-based dual wire interface PAS ( 1010 ). The above-mentioned elements are hardware elements whose implementation is known per se. The size and number of transmit memories are selected according to the application. In one exemplary application, one transmit memory having a length of one byte has been found adequate. It is to be noted that the SPI interface and/or the PAS interface have their own intermediate memories in one embodiment.  
         [0017]    Receiver  1020  on the side of the decentralized unit basically has a transmitting/receiving module  1200 , which also has a current-based dual wire interface PAS  1202  for communication with transmitting/receiving module  1004  of the central unit, at least one receive memory  1204 ,  1206 , and an SPI interface  1208 , via which the module is connected to an SPI interface  1210  of a processor  1212 . The above-mentioned elements are hardware elements whose implementation is known per se. The size and number of receive memories are selected according to the application. In one exemplary application, two receive memories, having a length of one byte each, have been found adequate. It is to be noted that the SPI interface and/or the PAS interface have their own intermediate memories in one embodiment.  
         [0018]    For reasons of clarity, the receive side of module  1004  and the transmit side of module  1200  are not shown in FIG. 2. Module  1004  has at least one receive memory (similar to  1204 ,  1206 ) for receiving messages, whose input is connected to interface  1010  and whose output is connected to SPI interface  1006 . Also in this case, the size and number of receive memories are selected according to the application. In one exemplary application, two receive memories, having a length of one byte each, have been found adequate, with the SPI interface and the PAS interface having their own intermediate receive memories in one embodiment. Module  1200  has at least one transmit memory (similar to  1008 ) for transmitting messages, whose input is connected to interface  1208  and whose output is connected to interface  1202 . Also in this case, the size and number of transmit memories are selected according to the application. In one exemplary application, one transmit memory, having a length of one byte, has been found adequate, with the SPI interface and/or the PAS interface having their own intermediate transmit memories in one embodiment.  
         [0019]    Furthermore, a data link  1012  is provided between module  1004  and processor  1000  and a data link  1014  is provided between module  1200  and processor  1212 , over which data links the particular processor receives information from the module on the data received and to be picked up.  
         [0020]    [0020]FIG. 2 shows the interface between central control unit  100  and a selected decentralized control unit  120 . In the preferred embodiment, a plurality of decentralized control units are provided, so that each of the decentralized control units includes a module such as module  1200 , and has a preferably current-based interface to module  1004 . Depending on the number of decentralized control units to be served, this module includes current-based interfaces, transmit memories, receive memories, etc., but only one SPI interface to processor  1000 .  
         [0021]    In the preferred embodiment, modules  1004  and  1200  are ASICs, which include at least the elements illustrated and whose function sequence explained below is hard wired. The number of transmit and receive memories varies according to the application, so that, for example, three receive memories and two transmit memories, one receive memory and two transmit memories, etc. may be provided for each channel. The length of the buffer memory depends on the length of the data to be transmitted and may be one byte or more depending on the embodiment.  
         [0022]    [0022]FIG. 3 shows, using an example, a transmit sequence from the central control unit to a decentralized control unit in which a data pile-up occurs because the decentralized control unit does not pick up the transmitted data. The sequence in modules  1004  and  1200  for such a transmission operation is shown. The handling is hard wired in the modules.  
         [0023]    At time T 1 , processor  1000  transmits data X 1  to module  1004  via its SPI interface. Module  1004  loads this data, since its memories are free, via the PAS interface into module  1200 , which stores the data in free receive memory  1206 . At the same time, the module transmits to computer  1212  the information that data is available for pickup. The memory is not emptied until processor  1212  picks up the data. At the next point in time X 2  in the cycle, processor  1000  transmits additional data X 2  in the same manner. Assuming that processor  1212  has not picked up data X 1 , data X 2  remains in receive memory  1204 . It is only forwarded when the next memory is free. Since this is not the case, the data is not forwarded. At time T 3 , the next data X 3  is transmitted by processor  100  via the interface. This data is stored in the memory of PAS interface  1202  of module  1200 . Now three memories are full because no data was picked up. Data X 3  is not forwarded because processor  1212  did not pick up data X 2  and X 1 .  
         [0024]    At time T 4 , processor  1000  transmits data X 4 , which remains pending in a transmit memory of PAS interface  1010  of module  1004 , since all receive memories of module  1200  are full. Module  1200  reports to module  1004  that all memories are full. Therefore, module  1004  stores the data in its memories. At time T 5 , processor  1000  transmits data X 5 , which remains in transmit memory  1008  of module  1004 . This memory is not emptied until the PAS memory is free. At time T 6 , processor  1000  receives the message from module  1004  that all memories are full, so that no transmission is possible. Consequently, microcomputer  1000  recognizes that the data transmission has failed, and data X 6  is retransmitted at a later time.  
         [0025]    Thus, this pile-up condition shows an indirect handshake of the data transmission in which no feedback to the transmitter occurs if the data transmission is successful, and feedback occurs after a certain number of transmissions if the transmission is unsuccessful.  
         [0026]    If the processor has read data X 1 , data X 2  through X 5  are pushed forward by one memory location, so as to enable the transmission of data X 6 . Processor  1000  is informed thereof by the message “all memories full” being reset. Normally not all memories are full. The transmitted data is entered in the last free memory in the direction of operation and is pushed forward to the next one when the latter becomes free until the receive processor it.  
         [0027]    Transmission of data from the decentralized control unit to the central control unit takes place in a similar manner.