Abstract:
There are provided a driving apparatus having a current detection function and a motor driving apparatus having a current detection function that are capable of detecting current without a voltage drop by using a dummy transistor connected to a driving transistor in parallel. The driving apparatus includes: a driving unit including at least one transistor connected between a driving power terminal supplying driving power and a ground and switched according to a switching control signal to drive a preset device; and a detecting unit including at least one dummy transistor connected to the at least one transistor in parallel and switched together with the at least one transistor according to the switching control signal to detect current flowing in the at least one dummy transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority of Korean Patent Application No. 10-2012-0084158 filed on Jul. 31, 2012, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a driving apparatus having a current detection function for an electronic product, and more particularly, to a motor driving apparatus having a current detection function for driving a motor. 
         [0004]    2. Description of the Related Art 
         [0005]    Recently, due to demand for personal, home, and office electrical appliances, electronic devices and the like, the use of electrical devices and electronic devices has rapidly increased. 
         [0006]    Interiors of these devices may be provided with a driving circuit in order to drive a specific operation. An example of such a device may include a motor. 
         [0007]    A brushless direct current (BLDC) motor generally means a DC motor able to conduct a current or adjust a current direction using a non-contact position detector and a semiconductor element rather than using a mechanical contact unit such as a brush, a commutator, or the like, in a DC motor. 
         [0008]    In order to drive the BLDC motor, a driving apparatus may be used. 
         [0009]      FIG. 1  is a configuration diagram of a general motor driving apparatus. 
         [0010]    Referring to  FIG. 1 , a general motor driving apparatus  10  may include a controlling unit  11  and a driving unit  12 . 
         [0011]    The controlling unit  11  may control driving of the motor, and the driving unit  12  may drive the motor by turning four field effect transistors (FETs) on or off according to a driving signal of the controlling unit  11 . 
         [0012]      FIG. 2  is a diagram showing driving signals of the motor driving apparatus. 
         [0013]    Referring to  FIG. 2 , the driving signals transferred from the controlling unit  11  to the driving unit  12  may be divided into four types thereof and may be transferred in a sequence of identification numerals {circle around ( 1 )}, {circle around ( 2 )}, {circle around ( 3 )}, and {circle around ( 4 )}. 
         [0014]    That is, a first PMOS FET P 1  and a second NMOS FET N 2  may be turned on by a driving signal represented by identification numeral {circle around ( 1 )}, and the first PMOS FET P 1  and the second NMOS FET N 2  may be turned off while a second PMOS FET P 2  and a first NMOS FET N 1  maybe turned on by a driving signal represented by identification numeral {circle around ( 2 )}. 
         [0015]    Again, the second PMOS FET P 2  and the first NMOS FET N 1  may be turned off and the first PMOS FET P 1  and the second NMOS FET N 2  may be turned on by a driving signal represented by identification numeral {circle around ( 3 )}, and the first PMOS FET P 1  and the second NMOS FET N 2  may be turned off and the second PMOS FET P 2  and the first NMOS FET N 1  may be turned on by a driving signal represented by identification numeral {circle around ( 4 )}. 
         [0016]    In this driving scheme, when the first PMOS FET P 1  and the second PMOS FET P 2  are turned on, pulse width modulation (PWM) signals (oblique line portions of  FIG. 2 ) are generated, whereby a speed of the motor may be adjusted. 
         [0017]    The motor driving apparatus as described above may perform a control operation of detecting current flowing in the motor through a resistor connected to a ground and providing a PWM signal based on the detected signal to appropriately adjust a speed of the motor to a set level or stop the driving of the motor at the time of overcurrent in order to accurately drive the motor. 
         [0018]    However, the detection scheme as described above has a problem in that power efficiency may be reduced due to a voltage drop by the resistor. 
       RELATED ART DOCUMENT 
       [0000]    
       
         (Patent Document 1) Korean Patent Laid-open Publication No. 10-2006-0045357 
       
     
       SUMMARY OF THE INVENTION 
       [0020]    An aspect of the present invention provides a driving apparatus having a current detection function and a motor driving apparatus having a current detection function that are capable of detecting current without a voltage drop by using a dummy transistor connected in parallel with a driving transistor. 
         [0021]    According to an aspect of the present invention, there is provided a driving apparatus having a current detection function, the driving apparatus including: a driving unit including at least one transistor connected between a driving power terminal supplying driving power and a ground and switched according to a switching control signal to drive a preset device; and a detecting unit including at least one dummy transistor connected to the at least one transistor in parallel and switched together with the at least one transistor according to the switching control signal to detect current flowing in the at least one dummy transistor. 
         [0022]    The at least one dummy transistor may have at least one dummy transistor has a resistance element greater than a resistance element of the at least one transistor. 
         [0023]    The detecting unit may detect the current flowing in the at least one dummy transistor according to a ratio of the resistance element of the at least one dummy transistor to the resistance element of the at least one transistor. 
         [0024]    The detecting unit may further include a detection resistor connected between the at least one dummy transistor and the ground to detect the current flowing in the at least one dummy transistor. 
         [0025]    The at least one dummy transistor and the at least one transistor may have the same electrical polarity. 
         [0026]    According to another aspect of the present invention, there is provided a motor driving apparatus having a current detection function, the motor driving apparatus including: a driving unit including a plurality of pairs of transistors connected between a driving power terminal supplying driving power and a ground, connected to each other in parallel, and switched according to a switching control signal to drive a motor; and a detecting unit including at least one dummy transistor connected in parallel with at least one transistor of the plurality of pairs of transistors and switched together with the at least one transistor according to the switching control signal to detect current flowing in the at least one dummy transistor. 
         [0027]    In the driving unit, the plurality of pairs of transistors may include: a first pair of transistors including a first p-type metal oxide semiconductor field-effect transistor (PMOS FET) electrically connected between the driving power terminal supplying driving power and the ground and a first n-type MOS FET (NMOS FET) electrically connected between the first PMOS FET and the ground; and a second pair of transistors including a second PMOS FET connected to the driving power terminal in parallel with the first PMOS FET and electrically connected between the driving power terminal and the ground and a second NMOS FET electrically connected between the second PMOS FET and the ground. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0029]      FIG. 1  is a configuration diagram of a general motor driving apparatus; 
           [0030]      FIG. 2  is a diagram showing driving signals of the motor driving apparatus; 
           [0031]      FIG. 3  is a schematic circuit diagram of a driving apparatus according to an embodiment of the present invention; 
           [0032]      FIG. 4  is a schematic configuration diagram of a motor driving apparatus according to the embodiment of the present invention; and 
           [0033]      FIG. 5  is a diagram showing current flow in the motor driving apparatus according to the embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0034]    Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements. 
         [0035]      FIG. 3  is a schematic circuit diagram of a driving apparatus according to an embodiment of the present invention. 
         [0036]    Referring to  FIG. 3 , the driving apparatus according to the embodiment of the present invention may include a driving unit  110  and a detecting unit  120 . 
         [0037]    The driving unit  110  may include at least one transistor  111  connected between a driving power terminal supplying driving power VDD and a ground. 
         [0038]    The at least one transistor  111  may be switched on or off by receiving a driving signal applied from the outside to a gate thereof, thereby driving a target device to be driven. 
         [0039]    The detecting unit  120  may include at least one dummy transistor  121  and a detection resistor  122 . 
         [0040]    The dummy transistor  121  may receive the driving signal in a gate thereof in a similar manner to the transistor  111  of the driving unit  110 . Therefore, when the transistor  111  of the driving unit  110  is switched on, the dummy transistor  121  may also be switched on, while when the transistor  111  of the driving unit  110  is switched off, the dummy transistor  121  may also be switched off. 
         [0041]    To this end, the dummy transistor  121  and the transistor  111  of the driving unit  110  may have the same electrical polarity. 
         [0042]    The detection resistor  122  may be connected between the dummy transistor  121  and the ground to detect current flowing in the dummy transistor  121 . 
         [0043]    Here, the dummy transistor  121  may form circuit area and resistance ratios with the transistor  111  of the driving unit  110  and have a circuit area and resistance larger than those of the transistor  111  of the driving unit  110 . 
         [0044]    Therefore, the current flowing in the dummy transistor  121  may have a current value depending on the circuit area and resistance ratios with respect to current flowing in the transistor  111  of the driving unit  110 . 
         [0045]    For example, the circuit area and resistance ratios of the dummy transistor  121  to the transistor  111  of the driving unit  110  may be set to be 1000:1. Therefore, a ratio of the current flowing in the dummy transistor  121  to the current flowing in the transistor  111  of the driving unit  110  may be 1:1000. 
         [0046]    That is, almost all of the current flowing due to the driving power supply VDD may flow in the transistor  111  of the driving unit  110  and only a small amount of current in which a resistance drop is barely generated may flow in the dummy transistor  121 . 
         [0047]    A detection signal detected by the detection resistor  122  may be transferred to an external control circuit. Since the external control circuit may already recognize the circuit area and resistance ratios of the dummy transistor  121  and the transistor  111  of the driving unit  110 , the external control circuit may scale current information included in the detection signal to obtain accurate current information. 
         [0048]      FIG. 4  is a schematic configuration diagram of a motor driving apparatus according to the embodiment of the present invention. 
         [0049]    The motor driving apparatus according to the embodiment of the present invention may include a driving unit  210  and a detecting unit  220 . The driving unit  210  may include a transistor switched on or off according to the driving signal, and a motor may be driven according to switching on or off operation of the transistor. 
         [0050]    More specifically, the driving unit  210  may have two pairs of transistors, and each of the two pairs of transistors may include two transistors. As a result, the driving unit  210  may include a total of four transistors. The fourth transistors may be configured of two p-type metal oxide semiconductor field effect transistors (PMOS FETs) P 1  and P 2  and two n-type MOS FETs (NMOS FETs) N 1  and N 2 . 
         [0051]    The PMOS FETs P 1  and P 2  may include a first PMOS FET denoted by reference numeral P 1  and a second PMOS FET denoted by reference numeral P 2 , and the NMOS FETs N 1  and N 2  may include a first NMOS FET denoted by reference numeral N 1  and a second NMOS FET denoted by reference numeral N 2 . The first PMOS FET P 1  may be electrically connected between the driving power terminal for supplying the driving power VDD and the ground, and the first NMOS FET N 1  may be electrically connected between the first PMOS FET P 1  and the ground. 
         [0052]    The second PMOS FET P 2  may be connected to the driving power terminal in parallel with the first PMOS FET P 1  and be electrically connected between the driving power terminal and the ground, and the second NMOS FET N 2  may be electrically connected between the second PMOS FET P 2  and the ground. 
         [0053]    In addition, the motor is connected to a connection point between the first PMOS FET P 1  and the first NMOS FET N 1  and a connection point between the second PMOS FET P 2  and the second NMOS FET N 2 , such that the motor may be driven by switching operations of the first PMOS FET P 1  and the second NMOS FET N 2  and switching operations of the second PMOS FET P 2  and the first NMOS FET N 1 . 
         [0054]    Briefly describing a motor driving operation, the first PMOS FET P 1  and the second NMOS FET N 2 , and the second PMOS FET P 2  and the first NMOS FET N 1  may be alternately turned on or off by driving signals POUT 1 , POUT 2 , NOUT 1 , and NOUT 2  from the outside. 
         [0055]    That is, the first PMOS FET P 1  and the second NMOS FET 
         [0056]    N 2  may be turned off and the second PMOS FET P 2  and the first NMOS FET N 1  may be turned on by the driving signals POUT 1 , POUT 2 , NOUT 1 , and NOUT 2  from the outside, and the second PMOS FET P 2  and the first NMOS FET N 1  may be turned off and the first PMOS FET P 1  and the second NMOS FET N 2  may be turned on by the driving signals POUT 1 , POUT 2 , NOUT 1 , and NOUT 2 . 
         [0057]    The detecting unit  220  may include dummy transistors ND 1  and ND 2  and detection resistors R 1  and R 2 . The dummy transistors ND 1  and ND 2  may include a first dummy transistor denoted by reference numeral ND 1  and a second dummy transistor denoted by reference numeral ND 2 . 
         [0058]    The dummy transistors ND 1  and ND 2  may be connected to at least one MOS FET of the driving unit in parallel. 
         [0059]    More specifically, the dummy transistors ND 1  and ND 2  may be connected to the first NMOS FET N 1  and the second NMOS FET N 2  in parallel, respectively. 
         [0060]    The driving signals NOUT 1  and NOUT 2  input to gates of the first NMOS FET N 1  and the second NMOS FET N 2  may be input to gates of the dummy transistors ND 1  and ND 2 . 
         [0061]    That is, the first dummy transistor ND 1  may be connected to the first NMOS FET N 1  in parallel to receive the driving signal NOUT 1  together with the first NMOS FET N 1 , and the second dummy transistor ND 2  may be connected to the second NMOS FET N 2  in parallel to receive the second driving signal NOUT 2  together with the second NMOS FET N 2 . 
         [0062]    Although not shown, the first and second dummy transistors ND 1  and ND 2  may also be connected to the first and second PMOS FETs in parallel, respectively, to receive the driving signals POUT 1  and POUT 2  together with the first and second PMOS FETs. 
         [0063]    The detection resistors R 1  and R 2  may be connected between the respective first and second dummy transistor ND 1  and ND 2  and the ground. 
         [0064]      FIG. 5  is a diagram showing current flow in the motor driving apparatus according to the embodiment of the present invention. 
         [0065]    Referring to  FIGS. 4 and 5 , as described above, the first PMOS FET P 1  and the second NMOS FET N 2  may be turned off and the second PMOS FET P 2  and the first NMOS FET N 1  may be turned on by the driving signals POUT 1 , POUT 2 , NOUT 1 , and NOUT 2 , and the second PMOS FET P 2  and the first NMOS FET N 1  may be turned off and the first PMOS FET P 1  and the second NMOS FET N 2  may be turned on by the driving signals POUT 1 , POUT 2 , NOUT 1 , and NOUT 2 . Therefore, current flow as depicted by arrows in  FIGS. 4 and 5  may be generated. 
         [0066]    In this case, the dummy transistors ND 1  and ND 2  may form circuit area and resistance ratios with the first and second NMOS FETs N 1  and N 2 , and have a circuit area and resistance that are larger than those of the first and second NMOS FETs N 1  and N 2 . 
         [0067]    Therefore, current flowing in the dummy transistors ND 1  and ND 2  may have a current value depending on the above-mentioned circuit area and resistance ratios with respect to the current flowing in the first and second NMOS FETs N 1  and N 2 . 
         [0068]    For example, the circuit area and resistance ratios of the dummy transistors ND 1  and ND 2  to the first and second NMOS FETs N 1  and N 2  may be set to 1000:1. Therefore, a ratio of the current flowing in the dummy transistors ND 1  and ND 2  to the current flowing in the first and second NMOS FETs N 1  and N 2  may be 1:1000. 
         [0069]    That is, almost all of the current flowing due to the driving power supply VDD may flow in the first and second NMOS FETs N 1  and N 2  and only a small amount of current in which a resistance drop is barely generated may flow in the dummy transistors ND 1  and ND 2 . 
         [0070]    As in the Related Art Document, in the case in which a detection resistor is connected between an NMOS FET used for driving of the motor and a ground, a voltage of driving power may be represented by the following Equation 1. 
         [0000]    
       
         
           
             
               
                 
                   VDD 
                   = 
                   
                     
                       
                         ( 
                         
                           
                             Ron 
                             PMOS 
                           
                           + 
                           
                             Ron 
                             NMOS 
                           
                           + 
                           
                             R 
                             sensing 
                           
                           + 
                           
                             R 
                             inductor 
                           
                         
                         ) 
                       
                       × 
                       I 
                     
                     + 
                     
                       
                         L 
                         inductor 
                       
                        
                       
                         
                           d 
                            
                           
                               
                           
                            
                           I 
                         
                         
                           d 
                            
                           
                               
                           
                            
                           t 
                         
                       
                     
                     + 
                     BEMF 
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                      
                     
                         
                     
                      
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
         [0071]    However, in the motor driving apparatus according to the embodiment of the present invention, the detection resistor is connected between the dummy transistor and the ground to detect the current, a voltage of the driving power may be represented by the following Equation 2. 
         [0000]    
       
         
           
             
               
                 
                   VDD 
                   = 
                   
                     
                       
                         ( 
                         
                           
                             Ron 
                             PMOS 
                           
                           + 
                           
                             Ron 
                             NMOS 
                           
                           + 
                           
                             R 
                             inductor 
                           
                         
                         ) 
                       
                       × 
                       I 
                     
                     + 
                     
                       
                         L 
                         inductor 
                       
                        
                       
                         
                           d 
                            
                           
                               
                           
                            
                           I 
                         
                         
                           d 
                            
                           
                               
                           
                            
                           t 
                         
                       
                     
                     + 
                     BEMF 
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                      
                     
                         
                     
                      
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
         [0072]    Comparing Equations 1 and 2, it may be appreciated that a voltage drop due to the detection resistor Rsensing is removed. 
         [0073]    A detection signal detected by the detection resistors R 1  and R 2  may be transferred to an external control circuit. Since the external control circuit already recognizes the circuit area and resistance ratios of the dummy transistors ND 1  and ND 2  to the first and second NMOS FETs N 1  and N 2 , the external control circuit may scale current information included in the detection signal to obtain accurate current information. 
         [0074]    As set forth above, according to the embodiment of the present invention, a dummy transistor connected to a driving transistor in parallel is used to detect current without a voltage drop, whereby a reduction in power efficiency due to power detection can be prevented. 
         [0075]    While the present invention has been shown and described in connection with the embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.