Abstract:
A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques. An angle between the lid and the semiconductor device can be controlled by adjusting relative widths of one or both the layers of solderable materials.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to the field of passivating semiconductor die, especially hermetically. More particularly, this invention relates to mounting and sealing an optically transparent lid onto an optically active semiconductor integrated circuit.  
         BACKGROUND OF THE INVENTION  
         [0002]    In the manufacture of integrated circuits (chips) it is well known that it is desirable to encapsulate the chip protected from mechanical damage and contamination. These techniques are known to passivate the chips. There are a variety of well known techniques available for encapsulating the chip. These techniques include mounting the chip within a cavity in a package, wire bonding the chip to a lead frame and then enclosing the package with a lid. Another well known technique includes mounting the chip to a lead frame, wire bonding the chip to the lead frame and then passivating the chip and a portion of the lead frame in a molded plastic or plastic epoxy body. A third common technique for passivating a chip includes flip-chip bonding the chip to a printed circuit board and then covering the chip with a plastic resin.  
           [0003]    An EPROM is a read-only memory device. The program or data which is stored in an EPROM can only be erased by causing or allowing optical radiation (ultraviolet and visible) to impinge on the surface of the EPROM. Accordingly, conventional chip packaging techniques are inadequate because they are opaque to optical radiation. To solve this problem, makers of EPROMs mount the EPROM chip within the cavity of a ceramic package and hermetically seal the assembly with an optically transparently lid.  
           [0004]    Micro-electro-mechanical devices (MEMs) are another well known class of silicon semiconductors devices. MEMs are useful for a variety of applications including strain gauges, accelerometers, electronic levels, and also for displays or other optical devices. Because of their extremely small moving parts, MEMs are particularly susceptible to ambient conditions. Accordingly, MEMs are traditionally sealed within the cavity of an hermetic package which is then hermetically sealed to control the environment to which the MEM is subjected.  
           [0005]    When the MEM is to be used in a display application, it is required that optical energy (light) be able to penetrate the package, impinge on the surface of the MEM for modulation, and then escape from the package for forming a display image. The ability of light to enter and leave the package is also required for other optical devices as well. Though conventional ceramic packages are hermetic, because they are opaque they are unsuitable for use with a display or optical MEM. In certain display or optical MEM applications, the MEM is mounted within the cavity of a ceramic package. The assembly is made hermetic by affixing a transparent lid to the ceramic package with an hermetic seal in much the same way as an EPROM package.  
           [0006]    It is well known that much of the cost associated with manufacturing silicon semiconductor devices is incurred through the packaging technology. This is particularly true with hermetic ceramic packages. The cost of packages including an optically transparent window is considerably more expensive still.  
           [0007]    Under certain circumstances when building a display or other optical MEM assembly it is important that the MEM and transparent lid have a precise physical relationship to one another. For some applications, it is important that the MEM and transparent lid be precisely parallel to one another. For other applications, it is important that the MEM and transparent lid are a precise angle between the structures. Conventional silicon semiconductor chip packaging technology does not take into account an ability to control an angle between the chip and the package lid.  
           [0008]    What is needed is a method of and an apparatus for hermetically sealing MEMs intended for use in a display application. What is needed is a method of and an apparatus for hermetically sealing MEMs intended for use in an optical application. What is further needed is a method of and an apparatus for sealing MEMs having a high pin count. Also what is needed is a method of and an apparatus for protecting MEMs which is relatively inexpensive. There is a need for a method of and an apparatus for hermetically sealing the display MEM which can be mounted to the MEM through an uncomplicated manufacturing process. What is further needed is a method and apparatus for sealing display MEMs where an angle of the lid relative to the MEM can be precisely controlled through the assembly process.  
         SUMMARY OF THE INVENTION  
         [0009]    A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder layer is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques. An angle between the lid and the semiconductor device can be controlled by adjusting relative widths of one or both the layers of solderable materials.  
           [0010]    Alternatively, the lid can be sealed to the substrate using other techniques. In a first alternative, an epoxy can be used. An optional first spacing material is formed in the lid sealing region. An epoxy is formed in a configuration corresponding to the lid sealing region. The lid and the semiconductor device are aligned and heated to hermetically join them together.  
           [0011]    In a second alternative, a glass frit can be used. An optional second spacing material is formed in the lid sealing region. A glass frit is formed in a configuration corresponding to the lid sealing region. The lid and the semiconductor device are aligned and heated to hermetically join them together. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    [0012]FIG. 1 shows a simplified cross section view of the preferred embodiment.  
         [0013]    [0013]FIG. 2 shows a block diagram exemplary plan view of semiconductor device according to the present invention.  
         [0014]    [0014]FIG. 3 shows a simplified schematic cross section diagram of the lid and the semiconductor device prior to sealing the lid.  
         [0015]    [0015]FIG. 4 shows a simplified schematic cross section diagram of the lid sealed to the semiconductor device according to the present invention with somewhat more detail than FIG. 3.  
         [0016]    [0016]FIG. 5 shows a schematic cross section diagram of the lid according to the present invention with somewhat more detail than FIG. 3.  
         [0017]    [0017]FIG. 6 shows a schematic cross section diagram of an alternate embodiment of the lid according to the present invention with somewhat more detail than FIG. 3.  
         [0018]    [0018]FIG. 7 shows a schematic cross section diagram of the semiconductor device lid according to the present invention with somewhat more detail than FIG. 3.  
         [0019]    [0019]FIG. 8 shows a schematic cross section diagram of an alternate embodiment of the semiconductor device according to the present invention with somewhat more detail than FIG. 3.  
         [0020]    [0020]FIG. 9 shows a schematic cross section of an embodiment for generating a predetermined angle of tilt prior to sealing the lid to the semiconductor device.  
         [0021]    [0021]FIG. 10 shows an exaggerated schematic cross section of the embodiment of FIG. 9 tilted in place after the lid is sealed to the semiconductor device.  
         [0022]    [0022]FIG. 11 shows a plan view of a fixture for aligning the lid to the semiconductor device.  
         [0023]    [0023]FIG. 12 shows a side view of the fixture of FIG. 11.  
         [0024]    [0024]FIG. 13 shows a graph representing temperature versus time for a process of sealing a lid to a semiconductor device according to the present invention.  
         [0025]    [0025]FIG. 14 shows a graph representing pressure versus time for the process of sealing a lid to a semiconductor device according to the present invention.  
         [0026]    [0026]FIG. 15 shows a schematic cross sectional representation of a wafer saw concurrently separating lids and semiconductor devices.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0027]    The present invention was developed to hermetically seal the mechanically active portion of a MEM for display device. In particular, the MEM is a diffraction grating light valve (GLV). Examples of the GLV are found U.S. Pat. No. 5,311,360 and also in allowed U.S. patent application Ser. No. 08/482,188. The developers of this technology have learned that if ambient moisture becomes deposited upon the ribbon structures that surface charging occurs which prevents suitable operation of the GLV. To avoid this sort of problem, it is preferable that the mechanically active portion of the MEM structure is passivated in an hermetic package. In addition, it is important that seal the form of glass or other transparent material having suitable optical characteristics.  
         [0028]    In contrast to other prior art hermetically passivating technologies for a silicon semiconductor device, the hermetic lid of the present invention is sealed directly onto the surface of the silicon semiconductor device. It will be readily apparent to those is ordinary skill in the art that the passivating technology of the present invention can also be used for hermetically sealing other types of devices including non-silicon or non-semiconductor devices or for use with non-transparent lid structures.  
         [0029]    [0029]FIG. 1 shows a representative cross section view of the silicon semiconductor device to which the transparent lid is hermetically sealed. The silicon semiconductor device of preferred embodiment is a GLV for forming a display. The cross-section drawing FIG. 1 is not drawn to scale nor does it include all the elements necessarily found in an operational GLV. These omissions are not intended to be limiting but rather are made in this document to avoid obscuring the invention in unnecessary and extraneous details.  
         [0030]    A conductive ribbon  100  including a metallic conductive and reflective covering  102  is formed over the semiconductor substrate  104  with an air gap  106  between the ribbon  100  and the substrate  104 . A conductive electrode  108  is formed on the surface of the substrate  104  and is covered by an insulating layer  110 . The conductive electrode  108  is positioned underneath the ribbon  100  and also will be below the air gap  104 . The reflective covering  102  extends beyond the region of the mechanically active ribbon  100  and is configured as a conventional bond pad  112  and its distal end. The device is passivated with a conventional overlying insulating passivation layer  114 . The passivation layer  114  does not cover the bond pads  112  nor the ribbon structures  100 / 102 . Control and power signals are coupled to the semiconductor device using conventional wire bonding structures  116 .  
         [0031]    According to conventional semiconductor manufacturing techniques, devices are packed as densely onto the surface of the semiconductor substrate as possible. Here however, because the optical glass is hermetically sealed directly onto the semiconductor device, the bond pads  112  are removed a considerable distance from the ribbon structures  100 / 102  to provide a lid sealing region  118 . Solderable material  120  is formed onto the lid sealing regions  118  using conventional semiconductor processing techniques.  
         [0032]    Because the preferred application for the present invention is for hermetically sealing a GLV for use in a display application, the lid  122  is preferably formed of optical quality material. It will be understood by persons of ordinary skill in the art that the lid  122  can be coated with an optically sensitive material for any of a variety of purposes including but not limited to filtering unwanted radiation, enhancing reflectivity, or decreasing reflectivity. Additionally, the lid  122  can also be configured to have optical characteristics. In other words, the lid  122  can be a lens of any convenient type.  
         [0033]    Once the lid is formed to a size appropriate to fit come currently over the lid sealing regions  118  a solderable material  124  is formed in a ring surrounding the periphery of one face of the lid  122  using conventional semiconductor processing techniques. Next, a solder  126  is deposited onto the solderable material  124  so that the lid can be joined to the semiconductor device. Though not shown to scale, it is clear from the drawing of FIG. 1 that the lid  122  and the ribbon structures  100 / 102  are mounted away to avoid interfering with one another. In this way, the written structures  100 / 102  are free to move upwardly and downwardly.  
         [0034]    [0034]FIG. 2 shows a plan view of an exemplary device according to the present invention wherein the various regions are shown as blocks. It will be apparent to persons ordinary skill in the art that the precise dimensions and ratios between the various structures can be modified to significantly and still fall within the spirit and scope of these teachings. According to the preferred embodiment of the present invention to lid is in optical element intended for mounting over a GLV to be used as a display engine. The ribbon structures of the GLV comprise a mechanically active region  140 . Surrounding the mechanically active region  140  is located the lid sealing region  118 . Where appropriate, identical reference numerals will be used in the several drawings to identify the same elements. As previously described, the lid sealing region  118  is passivated and includes no mechanically active elements such as traditionally found in a MEM device. Similarly, the lid sealing region  118  also includes no bond pads were other off chip interface structures as the lid would interfere with the effective operation of such. It is possible that the lid sealing region  118  could include active electronic elements. However, in the event that the lid sealing region  118  did include active electronic elements effort must be taken to planarize that region in order to provide the surface to which the lid can properly mate.  
         [0035]    The bonding region  142  surrounds the lid sealing region  118 . The bonding region  142  includes the several bond pads necessary for making interconnection from the semiconductor device to off-chip circuits and systems. In the case of the display element such as the GLV of the present invention more than one thousand bond pads are required. Other types of semiconductor devices will require more or fewer bond pads depending upon their intended application.  
         [0036]    [0036]FIG. 3 shows a schematic cross-sectional representation of a first embodiment of present invention. As previously discussed a solderable material  150  is formed onto the lid sealing region  152  of the semiconductor device  154 . A solderable material  156  is also formed around the peripheral edges of the transparent lid  158 . A layer of solder  160  is formed over the layer of solderable material  156 . It will be apparent to one of ordinary skill in the art that the solder could also be applied to the first layer of solderable material. However, the inventors prefer applying the solder to the lid to avoid contaminating the wafer with solder.  
         [0037]    The transparent lid  158  is brought into contact with and aligned to the semiconductor device  154 . Heat is applied to the assembly allowing the solder  160  to flow. Surface tension of the solder  160 ′ after it has become a liquid causes it to remain between the solderable material  150  on the semiconductor device  154  and the solderable material  156  on the transparent lid  158 . The solder  160 ′ is identified with a prime (′) on the reference numeral to signify that the structure has changed because of flowing and resolidifying. The assembly is heated for a sufficient time to allow the solder  160  to flow and wet all solderable surfaces. Once the heat is removed the solder  160 ′ re-solidifies and the transparent lid  158  is hermetically sealed to the semiconductor device  154  as shown in the cross section view of FIG. 4.  
         [0038]    [0038]FIG. 5 shows a cross section view of the lid and the metallization layers. According to the preferred embodiment, the solderable material  156  actually comprises a sandwich of layers. In the preferred embodiment, the solderable layer  156  includes a first layer  156 A formed against the transparent lid  158 . A second layer  156 B is formed over the first layer  156 A and the layer of solder  160  is then formed over the second layer  156 B. In the preferred embodiment using these layers, the first layer  156 A user  300  angstrom layer of chrome and the second layer  156 B is a 10,000 angstrom layer of gold. The layer of solder  160  is and 80Au/20Sn solder 50 microns thick.  
         [0039]    According to the preferred embodiment, the transparent lid  158  is segmented prior to forming the metallization layers thereon. The inventors have learned through experimentation that the cost of masking the side edges of the transparent lid  158  exceeds the cost of the materials. Thus, in actual practice gold and chrome are also formed on the side edges of the transparent lid  158 . While this is not preferred, it causes no deleterious effects. As manufacturing processes develop, the golden chrome on the side edges of the transparent lid  158  may be deleted.  
         [0040]    [0040]FIG. 6 shows a cross-section view of another embodiment of the lid and metallization layers. In this embodiment, the solderable material  156  also comprises a sandwich of layers. Here, the solderable layer includes a first layer  156 C formed against the transparent lid  158 . A second layer  156 D is formed over the first layer  156 C and a third layer  156 E is formed over the second later  156 D. the layer of solder  160  is then formed over the third layer  156 E. In this embodiment the first layer  156 C is a 300 angstrom layer of chrome, the second layer  156 D is a him 500 angstrom layer of nickel and the third layer  156 E is a 10,000 angstrom layer of gold. The layer of solder  160  is an 80Au/20Sn solder 50 microns.  
         [0041]    [0041]FIG. 7 shows a cross-section view of an embodiment of the solderable region  152  of the semiconductor device  154 . For simplicity, the active portion of the semiconductor device  154  is not shown. The layer of solderable material is actually formed of a sandwich of layers. The sandwich of layers is formed using conventional lift-off semiconductor processing techniques. In other words, a layer of photo resist is deposited onto the surface of the semiconductor wafer. Using conventional masking techniques, openings are formed through the photo resist. The layers of solderable material are then deposited over the wafer including into the openings formed through the photo resist. Upon removal of the photo resist, the solderable material only remains on the surface of the semiconductor wafer in the lid sealing region  152 .  
         [0042]    A first layer  150 A is formed in the lid sealing region  152  of the semiconductor device  154 . A second layer  150 B is formed over the first layer  150 A. In this embodiment, the first layer  150 A is a 500 angstrom layer of chrome. The second layer  150 B is a 1000 angstrom layer of palladium.  
         [0043]    [0043]FIG. 8 shows they cross-section view of another embodiment of the solderable region  152 . In this embodiment, the solderable layer  150  comprises a three layer sandwich. A first layer  150 C is formed in the lid sealing region  152  of the semiconductor device  154 . A second layer  150 D is formed over the first layer  150 C and a third layer  150 E is formed over the second layer  150 D using conventional lift off techniques. In this embodiment, the first layer  150 C is a 300 angstrom layer of titanium, the second layer  150 D is a 1000 angstrom layer of nickel and the third layer  150 E is a 1000 angstrom layer of platinum.  
         [0044]    It will be apparent that the angle between the transparent lid  158  and the semiconductor device  154  can affect the optical characteristics of the assembly. For example, optical energy reflecting between the surface of the semiconductor device  154  and the bottom side of the transparent lid  158  can interfere constructively or destructively. There are applications which require the transparent lid  158  and semiconductor device  154  to be parallel and their applications which require a predetermined angle between these elements. The present invention also provides users of this technology and ability to control and select the pre-determined angle between the transparent lid  158  and semiconductor device  154 .  
         [0045]    Once melted, the solder  160  will flow to all wetted surfaces. However, the surface tension of the solder  160  will prevented from him flowing beyond the boundaries of the solderable layers  150  and  156 . Owing to the viscous properties of solder, the solder and cannot flow circumferentially around the periphery of a ringed structure such as described in this invention.  
         [0046]    Because all layers are concurrently formed using conventional semiconductor processing techniques, the thickness of each one of the several layers is uniform throughout each one of the entire layer. To control the relative angle between the transparent lid  158  and semiconductor device  154  the relative width of one side of the solderable layer  150  is adjusted. FIG. 9 shows a simplified cross-section of this embodiment. Recall that the lid ceiling region  152  of the semiconductor device  154  is essentially a rectangular ring. The mask for forming the solderable layer  150  is modified along one edge of the rectangular ring to form a wider layer  150 ′.  
         [0047]    [0047]FIG. 10 shows a cross-section of the embodiment of FIG. 9 once the lid  158  has aligned to the semiconductor device  154  and the assembly is heated to hermetically seal the construction. After the solder  168  heated beyond melting point it flows to all wetted surfaces. Because the layer  150 ′ is wider than the layer  150 , the solder  160 ″ must necessarily spread wider than the solder  160 ′″. Further, because the solder does not flow circumferentially around the periphery of the ringed structure, the transparent lid  158  is closer to the semiconductor device  154  over the wide solderable layer  150 ′ than over the conventional solderable layer  150 .  
         [0048]    It will be apparent to persons of ordinary skill in the art that the thickness of the resulting solder and hence the angle between the transparent lid  158  and semiconductor device  154  could also be adjusted by modifying the width of the solderable layer  156  which is coupled to the transparent lid  158 . The angle could also be adjusted by concurrently modifying the widths of both the solderable layer  150  and its corresponding solderable layer  156 . However, because the wafer of semiconductor devices  154  is made with the sequence of wafer masks, and because the lids are individually aligned to the wafer it is easier to adjust the angle by only adjusting the width of the solderable layer  150  as appropriate.  
         [0049]    [0049]FIG. 11 shows a plan view of a fixture  200  for aligning transparent lids to semiconductor devices on a wafer. FIG. 12 shows a side view partially in cross section of the same fixture  200 . Common reference numerals will be used to identify identical elements in the FIGS. 11 and 12. The fixture  200  includes a graphite base  202 . The base  202  includes a cut-out  204  appropriately sized to accept a semiconductor wafer. Four threaded locking elements  206  (screws) pass upwardly through the base  202  through a plurality of holes  208 .  
         [0050]    An intermediate plate  210  includes holes  214  aligned to accept the threaded locking elements  206 . The intermediate plate  210  also includes thirty-seven apertures  212  sized to accept the transparent lids  158  (FIG. 3). The intermediate plate  210  also includes three channels  216  positioned to allow moisture to escape from the semiconductor devices  154  (FIG. 3) during a subsequent heating operation. Alignment pins  218  are mounted to the base  202  and pass through the intermediate plate  210 . A pair of holding plates  220  also include holes  222  which are positioned to accept the threaded locking elements  206 .  
         [0051]    In use, a wafer is aligned and mounted within the cut-out  204  of the base  202  with the semiconductor devices  154  (FIG. 3) facing away from the base  202 . The intermediate plate  210  is then installed to the base  202  over the wafer. A transparent lid  158  is then inserted into each of the apertures  212 . It will be apparent that a test operation could be performed on the semiconductor devices  154  while still in the wafer form and bad devices could be marked so that no transparent lid  158  need be sealed to such bad devices. A weighted cap-panel  224  is rested over the transparent lids  158  to apply an appropriate amount of downward pressure owing to gravity.  
         [0052]    Once the assembly described relative to FIGS. 11 and 12 is fully constructed it is placed into an environmental chamber. FIG. 13 shows a graph representing temperature in ° C. versus time. FIG. 14 shows a graph representing atmospheric pressure in torr and/or atm versus time. Once the ambient atmosphere is removed, the assembly is exposed to a back fill gas comprising 10% He, 10% H and 80% N at less than 1 ppm water. The two graphs of FIGS. 13 and 14 are displayed in conjunction to a single time line and the process of forming the hermetic seal of the present invention is so described herein.  
         [0053]    The assembly is inserted into the environmental chamber with initial conditions of ambient temperature and atmosphere. Immediately, the atmosphere is evacuated to a vacuum pressure of 0.1 torr. This cycle lasts for approximately the first minute. Then the assembly is subjected to a pressure of 2 atm of the back fill gas for about 15 to 30 seconds and then the atmosphere is evacuated to a vacuum pressure of 0.0001 torr. This first evacuation continues and during the evacuation, at about five minutes, the chamber is heated to about 190° C. This is less than the melting point of the solder. This step of heating is to dry all residual moisture from the semiconductor devices  154  (FIG. 3) and also from the lids  158  (FIG. 3) and is known as a drying vacuum bake. During the drying vacuum bake, at about 7.5 minutes, the atmosphere is again evacuated to about 0.0001 torr for about one minute. Thereafter, at about 9.5 minutes, the pressure is increased to 2 atm with the back fill gas. Once the pressure reaches 2 atm, at about 10 minutes, the chamber is heated beyond the melting temperature of the solder and held at that temperature for about 3 minutes. The temperature is then allowed to return to room temperature. After the melting temperature is traversed, so that the solder solidifies and the semiconductor device is hermetic, the air pressure is returned to ambient. The heating steps are undertaken by a radiant heat source, though any other convenient means of heating will suffice.  
         [0054]    It will be recalled that layers of solderable material must first be formed so that the solder will appropriately adhere to both the lid and the semiconductor device. There are certain advantages to this. With a MEM, it is important that the lid does not interfere with the free movement of the mechanical MEM structure. The layers of solderable material can be used to increase the distance between the lid and the semiconductor device. However, materials other than solder can be used to seal the lids to the semiconductor devices. The materials for the structures can be appropriately substituted as described below.  
         [0055]    A polymetric epoxy ring can be formed in the lid sealing region or around the periphery of the lid, or both. The lid and the semiconductor device are then brought together, heated and cooled to passivate the semiconductor device. Depending upon the thickness of the epoxy layer(s) and its relative viscosity, the lid and the semiconductor device may be sufficiently far apart to avoid having the lid interfere with the operation of the MEM. If simple experimental results indicate otherwise, any suitable material can be first deposited in the lid sealing region, around the periphery of the lid, or both to increase the spacing between the lid and the semiconductor device. The spacing material can be SiO 2 , for example as that material is readily manufacturable in an conventional semiconductor manufacturing facility.  
         [0056]    Another material that can be used in place of the polymetric epoxy is glass frit. But for this substitution, the glass material can be used in the same way as the polymetric epoxy described above.  
         [0057]    It will be apparent to one of ordinary skill in the art that the lids and their respective rings of solderable layers and overlying layers of solder could be formed on a wafer of transparent material. Then the transparent wafer and the semiconductor wafer need merely be fixtured and aligned before subjecting that combination to the temperature cycling taught in FIGS. 13 and 14. To separate the devices into separate devices, one could simply use a narrow wafer saw blade and cut through the transparent wafer to only a predetermined depth to form individual lids and then in a second operation, use the same narrow blade to separate the semiconductor devices. In an alternate embodiment, a single narrow blade with a berm could be used to separate these devices in a single operation. As shown in FIG. 15, the lids  158  are separated by the berm  300  and the semiconductor devices  154  are concurrently separated by the tip of the saw blade  302 .  
         [0058]    When the lids  158  are all concurrently formed in a wafer and then brought together with a wafer of semiconductor devices  154 , it will be apparent to one of ordinary skill in the art that the semiconductor devices  154  and the lids  158  will necessarily be parallel to one another. To form a predetermined angle between the semiconductor devices  154  and the lids  158 , either one or both of the semiconductor devices  154  and the lids  158  can have a non-uniform peripheral region as previously described. Once the semiconductor devices  154  and the lids  158  are initially joined together using one of the techniques described above, the assembly is cut to form individual units. Thereafter, these units can be reheated to allow the seal to flow and provide the desired angle between the semiconductor devices  154  and the lids  158 .  
         [0059]    The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention.