Abstract:
A system and apparatus for startup and speed regulation of low-inertia capstan motors under circumstances where the capstan load during startup may vary widely. A stiction handler provides dynamic control of the motor drive voltage imposed to overcome stationary friction, minimizing the power consumption on startup independently of variations in drag load or motor inertia. A stepped speed-up signal is applied to the motor instead of a conventional constant current-limited signal or sawtooth ramp signal. Motor speed regulation is imposed at each step of a stepped speed-up drive signal. This invention is particularly useful, for example, in low-power magnetic tape drives that must efficiently adapt to variations in drag between one tape cassette or cartridge and another.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to precision motor speed regulation circuitry and, more specifically, to a system for optimizing power consumption and speed regulation in a low-inertia capstan motor. 
     2. Description of the Related Art 
     Magnetic tape drives provide a fast and efficient means for storing computer data in large blocks, such as for backing-up the contents of hard disk storage devices. These tape drives, with tape cartridges using 0.25 inch, 8 mm, and 4 mm tape widths, are available for storing data in capacity ranges that match the requirements of small to medium computer systems. For example, commercially available devices can store over 1500 megabytes of digital data on quarter-inch (6.35 mm) magnetic tape in standard cartridges. Such drives can be packaged in the same slot that provides for an industry-standard half-height floppy disk drive. 
     Streaming magnetic tape drives, also called streamers, are constant-speed tape transports intended for back-up storage of the contents of hard disk drives. Streaming drives usually record data bidirectionally, laying down as many parallel tracks as permitted by tape head technology. Current tape head technology permits about 30 parallel tracks on quarter-inch tape (˜5 tracks/mm). 
     Practitioners in the art have introduced the use of low-inertia motors in tape drives as a technique to reduce power consumption during the motor start-up sequence. These motors are smaller and more economical with power but have low inertia compared to the load. This relatively low inertia causes the motor acceleration to vary proportionally with motor load. Thus, the time required for the low-inertia motor to start up and reach operating speed also varies proportionally with the motor load. 
     In accordance with specifications generally established by groups such as the American National Standards Institute (ANSI) and the Quarter-Inch Cartridge Committee (QIC), the load on a capstan motor resulting from a QIC tape cartridge can vary from perhaps 0.25 newtons to 1.5 newtons. Therefore, tape cartridge drag varies from cartridge to cartridge over a 6 to 1 range. Also, drag forces can change with age and use of any particular cartridge, depending on frequency of use and operating temperatures. Moreover, the drag imposed on a capstan motor varies directly with tape speed. 
     Because the cartridge load varies over a 600% range, the motor startup time may vary also by 600% from cartridge to cartridge. This makes it difficult for the tape drive designer to meet the worst-case &#34;up to speed time delay&#34; of 300 milliseconds established in the QIC industry standard equipment specification. 
     Moreover, the industry standard tape cartridge is designed to withstand a maximum tape acceleration of only 1500 ips/sec (38 m/sec 2 ) . Thus, if a drive motor current limit is set to permit a high-drag cartridge to speed up within the worst-case time limit, a low-drag cartridge inserted in the same drive may be destroyed by the startup torque and acceleration of several times the necessary amount. On the other hand, if the motor current limit is set to control the acceleration of a low-drag cartridge, a high-drag cartridge in the same drive will require several times the specified worst-case speed-up time. 
     Practitioners in the art have suggested several solutions to this problem of optimizing startup-delay and tape acceleration with low-inertia capstan motors employed in streaming tape drives. One class of existing startup techniques applies a fixed drive to the motor in the hope that it will turn before the drive current exceeds the motor limit. Another such class merely starts with half-power, going to full power if the motor does not turn immediately. 
     Speed ramp-up control techniques in the prior art teach the use of a fixed drive current ramp from an initial value to a full speed value without adjustments for differences in motor responsiveness. Also, the effectiveness of motor speed regulation is limited to a 20-30% range of full speed in the present art. 
     In U.S. Pat. No. 4,963,810, A. D. Rojas et al disclose a variable load motor drive control circuit for making low inertia motors useful under circumstances where the load on the motor during startup acceleration may vary. Rojas et al employ a ramped drive current as opposed to the earlier, more conventional constant current limit signal. They first provide an initial fixed current to overcome the static friction of the motor and then ramp the current upward at a predetermined rate expected to bring the motor to operating speed without exceeding the desired acceleration. However, Rojas et al neither teach nor suggest means for adjusting the motor drive responsive to actual motor velocity. They merely apply the predetermined drive signal to the motor and wait for a predetermined time, without checking to see if the motor actually starts. Also, Rojas et al do not vary the initial drive level to accommodate differences in starting friction from motor to motor and cartridge to cartridge. Thus, their method is not adaptable to optimizing power consumption by reducing drive current to lightly loaded motors or increasing drive current to force a sticky motor to move within a desired time limit. 
     In U.S. Pat. No. 4,943,907, Kurt E. Godwin discloses a speed controller for a multi-speed peripheral disk or tape drive that automatically selects a drive speed from among a set of predetermined drive speeds. Godwin neither teaches nor considers drive level regulation responsive to motor load but merely teaches an automatic selection process involving an automated discovery of the maximum common data rate specification between a Central Processing Unit (CPU), its peripheral drive controller and a disk or tape drive. 
     Thus, there is still a clearly felt need in the art for a tape drive capstan motor controller that optimizes the motor startup power consumption and motor startup time delay for all combinations of motor inertia and tape cartridge drag. The related unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below. 
     SUMMARY OF THE INVENTION 
     This invention is a static friction handler and speed ramp-up system that solves several of the problems felt in the art. The static friction (stiction) handler employs feedback from Hall effect position sensors in the motor to actively adjust the motor drive signal as minimally necessary to overcome stiction. The speed regulation system of this invention is improved to permit speed regulation over the entire motor speed range. The ramping-up technique of this invention is dynamic in that the motor speed can be regulated at each step along the speed-up curve, as well as at full speed. 
     It is an objective of this invention that the stiction handler provide the minimum power necessary to overcome the static friction of any particular combination of motor inertia and tape cartridge drag. 
     It is another object of this invention to minimize power consumption and longitudinal tape stretching forces while maximizing tape acceleration. 
     It is an advantage of this invention that the stiction handler system limits capstan motor startup acceleration independently of the combined motor inertia and cartridge drag, which avoids tape stretching at startup. 
     It is another advantage of this invention that the combination of stiction handler and speed regulator systems provide the maximum possible ramp-up tape acceleration in all situations while also limiting motor forces on the tape, thereby avoiding tape stretching during speed-up. 
     It is an object of the bifurcated &#34;speed table&#34; of this invention that the desired speed regulation precision be specified independently of the desired speed value. It is a feature of the speed regulation system of this invention that each element in the table of predetermined motor speeds is bifurcated into two independent factors, one of which governs the precision of speed regulation and the other which governs the regulated speed value. 
     The foregoing, together with other objects, features and advantages of this invention will become more apparent when referring to the following specification, claims and the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     For a more complete understanding of this invention, reference is now made to the following detailed description of the embodiments as illustrated in the accompanying drawing, wherein: 
     FIG. 1 provides a general block diagram of the motor servo control system of this invention; 
     FIG. 2 provides a block diagram of the preferred embodiment of the tach comparator portion of this invention; 
     FIG. 3 provides a block diagram of the preferred embodiment of the math engine portion of this invention; 
     FIG. 4 provides a block diagram of an illustrative embodiment of the motor driver and motor-tachometer assembly suitable for use with this invention; and 
     FIG. 5 provides an illustrative embodiment of the stiction handler method of this invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 provides a block diagram of the capstan motor servo system of this invention. The motor and tachometer assembly 10 includes a low inertia three-phase DC motor coupled to an optical tachometer. A three-phase DC drive signal is provided on the bus 13 from a motor driver 14 responsive to the three-element commutation sense signals on the bus 17 from assembly 10. The optical tachometer provides a stream of tach pulses on line 18 in any useful manner known in the art for making the tach pulse repetition rate directly proportional to the rotational velocity of the motor in assembly 10. 
     Motor driver 14 provides the necessary DC levels responsive to an input signal on line 20. In the preferred embodiment of this invention, the signal on line 20 is a Pulse-Width Modulated (PWM) voltage that represents the desired drive voltage V or drive current I that is to be provided by motor driver 14. The duty cycle of the PWM signal on line 20 represents the desired motor drive level, which is proportional to the desired motor rotational velocity. 
     The PWM signal on line 20 is produced by a PWM generator 22 in response to a motor speed correction factor signal L i  on bus 24 and a stiction handler output signal on bus 26 from the stiction handler 28. Stiction handler 28, responsive to a start command at line 30, signals PWM generator 22 to set the minimal motor drive level necessary to overcome static friction in the capstan motor. After overcoming stiction, the capstan motor begins to turn, providing commutation sense output on bus 17, which is received by stiction handler 28. Responsive to this commutation sense output, stiction handler 28 provides a signal on line 32 that starts the speed ramp-up process from zero speed to a desired operating speed. At the same time, stiction handler 28 sets the output signal bus 26 to zero, leaving only the motor speed correction factor L i  on bus 24 as an input to PWM generator 22. 
     The purpose of L i  bus 24 is to ramp-up and regulate the capstan motor rotational velocity in accordance with the remainder of this invention. The first of these two features is the ramp-up method of this invention, which is initiated by the start ramp signal on line 32 when it is received by the speed table processor 34. 
     Speed table processor 34 contains a plurality of number tables, each element of which is associated with a desired rotational speed. Two numbers are used by this invention to signal the desired speed. The first of these numbers is a prescaler number P, which is used for switching speed levels. The second of these numbers is a reference interval number R, used for establishing the desired level of speed regulation precision and accuracy. In general terms, the product of these two numbers P*R is inversely proportional to the desired motor rotational velocity. During the ramp-up interval, new values for P and R are output on the P bus 36 and the R bus 38 responsive to the tach pulses on tach pulse line 18. 
     Thus, it will be readily appreciated that the preferred embodiment of this invention operates in three distinct phases. The first phase is the stiction handler phase wherein stiction handler 28 takes control of the motor drive until the first signs of physical rotation are received on sense bus 17. The second phase is the ramp-up phase where motor speed moves from zero to a desired operating speed. This is initiated by the start-ramp signal on line 32 and is carried out by speed table processor 34. The final phase is the motor speed regulation phase, which is accomplished by the tachometer comparator 40 and a math engine 42 in accordance with the speed control numbers P and R provided by speed table processor 34. 
     Tachometer comparator 40 compares the interval between tach pulses on line 18 to the reference interval number R on bus 38 to develop an instantaneous motor speed error E i , which is then transferred on an error bus 44 to math engine 42. Math engine 42 then scales the series of instantaneous speed errors to provide a motor speed correction factor L i  on bus 24 in accordance with the formula shown in FIG. 1 and more particularly described below in conjunction with FIG. 3. Finally, the entire system shown in FIG. 1 proceeds in accordance with the system clock on a clock line 46. 
     The internal operation of tachometer comparator 40 can be appreciated by referring to the detailed block diagram in FIG. 2. Comparator 40 receives the system clock on line 46, a 12-bit prescaler number on P bus 36, a 12-bit reference interval number on R bus 38, and the tach pulses on line 18. It then develops a series of 12-bit instantaneous motor speed errors E i  and provides these on error bus 44. This process is stepped along in response to the tach pulses on line 18. That is, a present (i) th  speed error E i  is updated to a next (i+1) th  speed error E i+1  in response to the next tach pulse on line 18. Otherwise, the internal operation of comparator 40 proceeds responsive to the pulses on system clock line 46. 
     The first step of this regulation process is the loading of prescaler number P in a register 48 and the negative of reference interval number R in another register 50. P and R are both retained in registers 48 and 50 until updated by signals from speed table processor 34 on busses 36 and 38. 
     The next step is the receipt of a tach pulse on line 18 by the tachometer latching register 52. A pulse on line 18 causes register 52 to store the tach count word from count bus 54 and reloads the negative reference interval number (-R) into the interval timing register 58 from register 50. The contents of register 52 are then presented on error bus 44 to math engine 42 (FIG. 1). 
     The contents of register 48 are initially loaded into the prescaler register 57. Register 57 then counts in response to the system clock signal on line 46, creating a tachometer clock signal F on a line 60. Tachometer clock signal F on line 60 increments the contents of register 58 and re-initializes prescaler register 57 by reloading the contents of P register 48. The rate of tachometer clock signal F is equal to the system clock rate divided by the value of prescaler P. Thus, the contents of register 58 are incremented from (-R) in response to each tachometer clock signal F on line 60. 
     The contents of register 58 are presented on tach count bus 54 to register 52 at all times. Thus, upon receipt of the next tach pulse on line 18, the present count of register 58 is stored in register 52, representing the difference between the desired number of tachometer clock pulses within a single tach interval and the actual number of tachometer clock pulses within that interval. It will be readily appreciated that the value of this error varies according to the value of prescaler P, reference interval number R and the actual tach interval T between tach pulses on line 18, which represents the reciprocal of actual motor rotational velocity. 
     The detailed preferred embodiment of math engine 42 is illustrated in FIG. 3. Math engine 42 converts the 12-bit instantaneous error signal E i  on error bus 44 to an 8-bit motor speed correction factor L i  on bus 24 in FIG. 3. Therefrom, generator 22 creates a corresponding PWM signal on line 20 representing the motor drive voltage V (or current I) necessary in view of the correction factor L i . Thus, it will be appreciated that the output of math engine 42 represents a large plurality of predetermined motor drive voltages (currents), each of which is represented by a PWM signal duty cycle percentage from zero to 100% on line 20. 
     The motor speed correction factor L i  on bus 24 represents the sum of an instantaneous error correction together with a long-term average error correction. These two elements are shown in FIG. 3 as the &#34;proportional path&#34; and the &#34;integral path&#34; in math engine 42. Considering the proportional path first, the i th  12-bit instantaneous motor speed error E i  is sign-extended to a 16-bit number and multiplied by a 4-bit proportional weighting factor K v  at a multiplier 62. The 16-bit product K v  E i  is stripped to the least significant 8-bit magnitude with sign (bit 9) on bus 64 and presented to a summer 66. If K v  E i  exceeds 8-bits in magnitude, the product on bus 64 is &#34;clipped&#34; to the maximum 8-bit magnitude. 
     Similarly, the i th  12-bit instantaneous motor speed error E i  is sign extended to 16 bits and added to a 16-bit once-delayed accumulation of all previous such errors ##EQU1## to create the i th  such accumulation ##EQU2## at a summer 68. This i th  16-bit sum is output on bus 70 and is multiplied by a second 4-bit weighting factor K q  at the multiplier 72. The 20-bit product from multiplier 72 is stripped to the least significant 8-bit magnitude with sign (bit 9) on a bus 74 and added to the 9-bit number on bus 64 at summer 66. The 10-bit sum is then stripped to the least significant 8-bit magnitude with sign (bit 9 ) representing the motor speed correction factor L i  on bus 24. The sign bit is used to control the direction of commutation. 
     Factor L i  is then converted to a stream of pulses having that one of a plurality of predetermined PWM duty cycles which corresponds to the value of L i  in the PWM generator 22. Because L i  is a signed 9-bit number, 255 such non-zero values may be accommodated. This conversion in generator 22 is accomplished by any useful means known in the art. 
     FIG. 4 presents an illustrative embodiment of motor driver 14 and motor/tachometer assembly 10. Motor driver 14 receives the (V, I) PWM pulses on line 20 as well as the commutation sense signals on bus 17, and generates the three-phase DC drive signals on bus 13. The motor commutation logic 76 combines the signals on three-wire bus 17 and line 20 to produce a 6-bit signal to the motor drivers 78. Motor drivers 78 provide three DC signals to the motor 80 in assembly 10. The three Hall-effect switches 82 provide signals representing the rotational location of each of the three DC motor circuits in a manner well-known in the art. Finally, the optical tachometer 84 is illustrated in FIG. 4 as a simple slotted disk that is directly coupled to the capstan (not shown), which may be belt-coupled to motor 80. Each mark or slot on such disk is sensed optically and converted to a series of tach pulses on line 18 in any useful manner known in the art. Direct capstan coupling of tachometer 84 avoids capstan-speed control error arising from undetected belt slippage. 
     FIG. 5 illustrates the procedure of this invention for overcoming static friction (stiction) in motor 80. Stiction handler 28 is initiated in a step 86 by a start command on line 30 in FIG. 1. Thereafter, a first of three or more predetermined motor drive voltages (or currents) is created in response to an output signal on bus 26 (FIG. 1) at the step 88 in FIG. 5. In a step 90, a predetermined time interval clock (not shown) is started and the commutation sense bus 17 is monitored for signs of motor rotation. Until the predetermined time interval expires at the step 92, bus 17 is repeatedly tested in a step 94. As soon as step 94 finds signs of motor rotation, control is returned to speed table processor 34 (FIG. 1). When the predetermined interval expires in step 92, the next in a plurality of predetermined drive voltages (or currents) is selected at a step 96 and the drive voltage (current) is tested against the maximum allowable motor voltage (current) limit in a step 98. If the motor voltage (current) has not exceeded a predetermined threshold corresponding to the safe limit at step 98, the procedure returns to step 90 and repeats. If, for some reason, motor 80 refuses to turn even at maximum drive voltage (current), the motor drive voltage V is set to zero, and an error condition is signaled at a step 100 and control is returned to speed table processor 34 for appropriate action. 
     Practitioners skilled in the art will appreciate from the above discussion that the capstan motor servo system of this invention includes (a) stiction handler 28 for overcoming static friction, (b) speed-up or ramp-up means in speed table processor 34 for speeding up the motor to a desired operating speed, and (c) speed regulation means for dynamic correction of motor speed errors detected in the tach pulses on line 18. In this invention, for a particular speed, the finest resolution control is achieved by loading the smallest prescaler P and the largest reference interval number R. If R is varied to control speed, a limited range of speed settings results because the larger size of R means that R approaches the maximum permitted word size, thus restricting changes in speed within the small headroom remaining between R and the word size limit. If the headroom is increased to improve the range of speed changes, the response resolution is accordingly reduced. This invention resolves this dilemma by using the prescaler P for speed control. That is, the speed regulation reference number is split into two separate digital words for the first time in this invention. This method permits a wide range of usable speeds without compromising the speed regulation precision at each desired speed value. 
     Clearly, other embodiments and modifications of this invention will occur readily to those of ordinary skill in the art in view of these teachings. Therefore, this invention is to be limited only by the following claims, which include all such embodiments and modifications when viewed in conjunction with the above specifications and accompanying drawing.