Abstract:
Read only memory (ROM) integrated circuit devices include one or more storage cells. A virtual ground line and a bit line are coupled to the storage cell. A precharge circuit independently controls timing of precharging of the virtual ground line and the bit line. The precharge circuit may be configured to deactivate precharging of the virtual ground line before deactivating precharging of the bit line. Precharging of the virtual ground line may be deactivated substantially concurrently with activation of discharging of the virtual ground line. Methods of operating such ROM integrated circuit devices are also provided.

Description:
RELATED APPLICATION  
       [0001]    This application claims priority to Korean Patent Application 2002-0041975, filed on Jul. 18, 2002, the contents of which are herein incorporated by reference in their entirety. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates to integrated circuit memory devices, and in particular to read only memory (ROM) devices having virtual ground and bit lines.  
           [0003]    A ROM integrated circuit device includes a ROM storage cell block including storage cells. Bits lines from the storage cells are used to output data from the storage cells during a read operations. Such devices may also include virtual ground lines that may be positioned adjacent the bit lines on the integrated circuit device. As integration density of the devices increases, the widths and lengths of lines formed in the integrated circuit device generally are reduced. As a result, electrical coupling may result between adjacent ones of the virtual ground lines and bit lines.  
           [0004]    A variety of approaches may be taken to reduce or prevent such an electrical coupling from adversely affecting performance of the device. For example, when the virtual ground lines and the bit lines are in a precharged state, the supply of the precharge voltage to the bit lines may be stopped when the virtual ground lines are being discharged to ground. As a result, the voltage of the bit lines may be affected by the virtual ground lines and drop to a predetermined level lower than the precharge voltage. To compensate for this drop, the supply of the precharge voltage to the bit lines is not stopped until a predetermined period of time after the virtual ground lines are grounded. Thus, the affect of the virtual ground lines on the bit lines may be reduced or eliminated.  
           [0005]    However, because the virtual ground lines and the bit lines are conventionally precharged at the same time, as described above, the precharge voltage is still applied for a predetermined period of time after the virtual ground lines are grounded. Thus, a short-circuit current may flow through the virtual ground lines and, as a result, the virtual ground lines may not be at a ground voltage level. This state may continue until the supply of the precharge voltage to the virtual ground lines stops. If the virtual ground lines are not fully grounded, the operational speed of the ROM integrated circuit device may decrease and its power consumption may increase.  
         SUMMARY OF THE INVENTION  
         [0006]    Embodiments of the present invention include read only memory (ROM) integrated circuit devices including one or more storage cells. A virtual ground line and a bit line are coupled to the storage cell. A precharge circuit independently controls timing of precharging of the virtual ground line and the bit line. More particularly, the precharge circuit may be configured to deactivate precharging of the virtual ground line before deactivating precharging of the bit line.  
           [0007]    In further embodiments of the present invention, the precharge circuit includes a virtual ground line precharge circuit that activates precharging of the virtual ground line responsive to a virtual ground line precharge signal and a bit line precharge circuit that activates precharging of the bit line responsive to a bit line precharge signal. The bit line precharge signal is deactivated after deactivation of the virtual ground line precharge signal.  
           [0008]    In other embodiments of the present invention, a virtual ground line discharge circuit is coupled to the virtual ground line. The virtual ground line precharge circuit deactivates precharging of the virtual ground line substantially concurrently with activation of the virtual ground line discharge circuit. The virtual ground line discharge circuit may couple the virtual ground line to ground and the virtual ground line precharge circuit may couple the virtual ground line to a precharge voltage. The bit line precharge signal may couple the bit line to the precharge voltage. The virtual ground line discharge circuit may activate discharging of the virtual ground line responsive to a discharge control signal.  
           [0009]    In further embodiments of the present invention, the virtual ground line precharge circuit is configured to activate precharging of the virtual ground line responsive to an address control signal and the virtual ground line discharge circuit is configured to activate discharging of the virtual ground line responsive to an address signal associated with the storage cell. The virtual ground line precharge circuit may include a virtual ground line precharge controller and a virtual ground line precharging unit. The virtual ground line precharge controller is configured to generate a virtual ground line precharge enable signal responsive to the address control signal and the virtual ground line precharge signal. The virtual ground le precharging unit includes a transistor having the virtual ground line precharge enable signal coupled to a gate thereof.  
           [0010]    In other embodiments of the present invention, the virtual ground line precharge controller is configured to generate the virtual ground line precharge enable signal as a Boolean NAND operation having the address control signal and the virtual ground line precharge signal as inputs. The bit line precharge circuit may include a bit line precharge controller and a bit line precharging unit. The bit line precharge controller is configured to generate a bit line precharge enable signal responsive to the bit line precharge signal. The bit line precharging unit includes a transistor having the bit line precharge enable signal coupled to a gate thereof.  
           [0011]    In further embodiments of the present invention, the virtual ground line discharge circuit includes a discharge controller that generates a discharge signal responsive to the discharge control signal and the address signal associated with the storage cell and a transistor having the discharge signal coupled to a gate thereof. The discharge controller may be configured to generate the discharge signal as a Boolean NAND operation having the discharge control signal and the address signal associated with the storage cell as inputs. The integrated circuit device may include a plurality of storage cells, each of the plurality of storage cells having an associated bit line and virtual ground line, precharging of the associated bit line and virtual ground line of each storage cell being independently controlled by the precharge circuit.  
           [0012]    In other embodiments of the present invention, methods are provided of controlling precharging of a read only memory (ROM) integrated circuit device including a storage cell and a virtual ground line and a bit line coupled to the storage cell. The methods include independently controlling timing of precharging of the virtual ground line and the bit line. Independently controlling timing of precharging may include deactivating precharging of the virtual ground line before deactivating precharging of the bit line. The methods may also include discharging the virtual ground line substantially concurrently with deactivating precharging of the virtual ground line.  
           [0013]    According to further embodiments of the present invention, a ROM integrated circuit device is provided including a ROM cell block, a virtual ground line, a virtual ground line precharging unit, a switch, a bit line, and a bit line precharging unit. The ROM cell block stores data. The virtual ground line is connected to the ROM cell block. The virtual ground line precharging unit precharges the virtual ground line in response to a virtual ground line precharge signal. The switch is connected to the virtual ground line and grounds the virtual ground line in response to a discharge signal. The bit line is connected to the ROM cell block. The bit line precharging unit precharges the bit line in response to a bit line precharge signal.  
           [0014]    In some embodiments of the present invention, the ROM integrated circuit device further includes a virtual ground line precharge controller that receives a virtual ground line precharge control signal and an address control signal and outputs the virtual ground line precharge signal. Here, if the virtual ground line precharge control signal and the address control signal are at a logic “high” level, the virtual ground line precharge signal is at a logic “low” level and if at least one of the virtual ground line precharge control signal and the address control signal is at a logic “low” level, the virtual ground line precharge signal is at a logic “high” level.  
           [0015]    In other embodiments of the present invention, if the virtual ground precharge signal is at a logic “low” level, the virtual ground line precharging unit is activated to precharge the virtual ground line and if the virtual ground line precharge signal is at a logic “high” level, the virtual ground line precharging unit is deactivated (inactivated). The ROM integrated circuit device may further include a bit line precharge controller that receives a bit line precharge control signal and outputs the bit line precharge signal. In such embodiments, if the bit line precharge control signal is at a logic “high” level, the bit line precharge signal is at a logic “low” level and if the bit line precharge control signal is at a logic “low” level the bit line precharge signal is at alogic “high” level.  
           [0016]    In further embodiments of the present invention, if the bit line precharge signal is at a logic “low” level the bit line precharging unit is activated to precharge the bit line and if the bit line precharge signal is at a logic “high” level the bit line precharging unit is deactivated (inactivated). The ROM integrated circuit device may further include a discharge controller that receives a discharge control signal and an address signal and outputs the discharge signal. In such embodiments, if at least one of the discharge control signal and the address signal is at a logic “low” level, the discharge signal is at a logic “high” level and if the discharge control signal and the address signal are at a logic “high” level, the discharge signal is at a logic “low” level. If the discharge signal is at a logic “high” level, the switch may be activated to ground the virtual ground line and, if the discharge signal is at a logic “low” level, the switch may be deactivated.  
           [0017]    In further embodiments of the present invention, a ROM integrated circuit device includes a ROM cell block, a plurality of virtual ground lines, a plurality of virtual ground line precharging units, a plurality of switches, a plurality of bit lines, and a plurality of bit line precharging units. The ROM cell block stores data. The plurality of virtual ground lines are connected to the ROM cell block. The plurality of virtual ground line precharging units precharge the plurality of virtual ground lines in response to a virtual ground line precharge signal. The plurality of switches are connected to one of the plurality of virtual ground lines and ground the virtual ground lines in response to a discharge signal. The plurality of bit lines are connected to the ROM cell block. The plurality of bit line precharging units precharge the plurality of bit lines in response to a bit line precharge signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIG. 1 is a block diagram illustrating a ROM integrated circuit device according to some embodiments of the present invention;  
         [0019]    [0019]FIG. 2 is a circuit diagram illustrating the virtual ground line precharge controller and the first virtual ground line precharging unit illustrated in FIG. 1 according to some embodiments of the present invention;  
         [0020]    [0020]FIG. 3 is a circuit diagram illustrating the bit line precharge controller and the first bit line precharging unit illustrated in FIG. 1 according to some embodiments of the present invention;  
         [0021]    [0021]FIG. 4 is a circuit diagram illustrating some embodiments of the first discharge controller and the first switch illustrated in FIG. 1 according to the present invention; and  
         [0022]    [0022]FIG. 5 is a timing diagram illustrating operations of the device illustrated in FIG. 1 according to some embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0023]    The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or “connected to” or “coupled to” another element, it can be directly on or connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly connected” or “directly coupled” to another element, there are no intervening elements present.  
         [0024]    Each embodiment described and illustrated herein includes its complementary conductivity type and/or complementary logic embodiment as well. References to source and drain of transistors herein are interchangeable and intended to encompass complementary conductivity type transistors or alternate technology type transistors except where a specific transistor type is referenced.  
         [0025]    The present invention will now be further described with reference to FIGS.  1 - 5 . FIG. 1 is a block diagram illustrating a read only memory (ROM) integrated circuit device according to some embodiments of the present invention. As shown in FIG. 1, a ROM integrated circuit device  101  includes a ROM cell block  111 , virtual ground lines VGL 1 , VGL 2 , etc., bit lines BL 1 , BL 2 , etc., a sense amplifier  181 , and a precharge circuit including a virtual ground line precharge controller  121 , a virtual ground line precharging units  131 ,  132 , etc., bit line precharge controller  141  and bit line precharging units  151 ,  151 , etc. The precharge circuit independently controls timing of precharging of the virtual ground lines VGL 1 , VGL 2 , etc. and the bit lines BL 1 , BL 2 , etc.  
         [0026]    The ROM cell block  111  further includes discharge controllers  161 ,  162 , etc. and switches  171 ,  172 , etc. The ROM cell block  111  stores data in one or more storage cells. In the ROM cell block  111 , writing of data is not supported due to its read only configuration. The virtual ground lines VGL 1 , VGL 2 , etc. and the bit lines BL 1 , BL 2 , etc. are coupled to the storage cell(s) of the ROM cell block  111 .  
         [0027]    Data stored in the ROM cell block  111  is transmitted to the sense amplifier  181  via the bit lines BL 1 , BL 2 , etc. As will be understood by those of skill in the art, respective bit lines BL 1 , BL 2 , etc. are associated with individual storage cell(s), such as a column of storage cells, of the ROM cell block  111 . The sense amplifier  181  amplifies the transmitted data and transmits the amplified data Dout to an external device.  
         [0028]    To simplify understanding of the present invention, operation of the circuit device  101  will be described with reference to a particular logic type and conductivity type of various components thereof. However, it is to be understood that such details are for purposes of understanding the present invention and those of skill in the art will understand that equivalent circuits may be used of the opposite logic and using different conductivity type components and that such equivalent circuits are within the scope of the present invention.  
         [0029]    As illustrated in FIG. 1, the virtual ground line precharge controller  121  receives a virtual ground line precharge control signal VPCON and an address control signal ACON and outputs a virtual ground line precharge signal VPRE. When the virtual ground line precharge control signal VPCON and the address control signal ACON are at a logic “high” activated level, the virtual ground line precharge controller  121  outputs the virtual ground line precharge signal VPRE at a logic “low” activated level. If either of the virtual ground line precharge control signal VPCON or the address control signal ACON is at a logic “low” level, the virtual ground line precharge controller  121  outputs the virtual ground line precharge signal VPRE at a logic “high” deactivated level.  
         [0030]    The virtual ground line precharging units  131 ,  132 , etc. precharge the virtual ground lines VGL 1 , VGL 2 , etc. responsive to activation of the virtual ground line precharge signal VPRE output from the virtual ground line precharge controller  121 . In other words, when the virtual ground line precharge signal VPRE is at a logic “low” level, the virtual ground line precharging units  131 ,  132 , etc. are activated to precharge the virtual ground lines VGL 1 , VGL 2 , etc. When the virtual ground line precharge signal VPRE is at a logic “high” level, the virtual ground line precharging units  131 ,  132 , etc. are deactivated and, thus, do not couple the virtual ground lines VGL 1 , VGL 2 , etc. to a precharge voltage.  
         [0031]    The bit line precharge controller  141  receives a bit line precharge control signal BPCON and outputs a bit line precharge signal BPRE. When the bit line precharge control signal BPCON is at a logic “high” level, the bit line precharge controller  141  outputs the bit line precharge signal BPRE at a logic “low” activated level. When the bit line precharge control signal BPCON is at a logic “low” level, the bit line precharge controller  141  outputs the bit line precharge signal BPRE at a logic “high” deactivated level.  
         [0032]    The bit line precharging units  151 ,  152 , etc. precharge the bit lines BL 1 , BL 2 , etc. responsive to the bit line precharge signal BPRE output from the bit line precharge controller  141 . In other words, when the bit line precharge signal BPRE is at a logic “low” level, the bit line precharging units  151 ,  152 , etc. are activated to couple the bit lines BL 1 , BL 2 , etc. to a precharge voltage. When the bit line precharge signal BPRE is at a logic “high” level, the bit line precharging units  151 ,  152 , etc. are deactivated and, thus, do not couple the bit lines BL 1 , BL 2 , etc. to the precharge voltage.  
         [0033]    The discharge controllers  161 ,  162 , etc. receive a discharge control signal DCON and address signals ADD 0 , ADD 1 , etc. and output discharge signals DIS 0 , DIS 1 , etc. In particular, for example, the discharge controller  161  receives the discharge signal DCON and the address signal ADD 0  and outputs the discharge signal DIS 0 . If either the discharge control signal DCON or the address signal ADD 0  is at a logic “low” level, the discharge controller  161  outputs the discharge signal DIS 0  at a logic “high” activated level. If the discharge control signal DCON and the address signal ADD 0  are both at a logic “high” level, the discharge controller  161  outputs the discharge signal DIS 0  at a logic “low” deactivated level.  
         [0034]    Similarly, the discharge controller  162  receives the discharge control signal DCON and the address signal ADD 1  and outputs the discharge signal DIS 1 . If either the discharge control signal DCON or the address signal ADD 1  is at a logic “low” level, the discharge controller  162  outputs the discharge signal DIS 1  at a logic “high” activated level. When the discharge control signal DCON and the address signal ADD 1  are both at a logic “high” level, the discharge controller  162  outputs the discharge signal DIS 1  at a logic “low” deactivated level. Thus, as described above, the discharge controllers  161 ,  162 , etc. are selectively activated responsive to the address signals ADD 0 , ADD 1 , etc.  
         [0035]    The switches  171 ,  172 , etc. selectively couple the virtual ground lines VGL 1 , VGL 2 , etc. to ground responsive to the discharge signals DIS 0 , DIS  1 , etc. In other words, when the discharge signal DIS 0  is at a logic “high” level, the switch  171  is activated to ground the virtual ground line VGL 1 . When the discharge signal DIS 0  is at a logic “low” level, the switch  171  is deactivated, and, thus, the virtual ground line VGL 1  is not grounded. Similarly, when the discharge signal DIS 1  is at a logic “high” level, the switch  172  is activated to ground the virtual ground line VGL 2 . When the discharge signal DIS 1  is at a logic low” level, the switch  172  is deactivated, and, thus, the virtual ground line VGL 2  is not grounded.  
         [0036]    [0036]FIG. 2 is a circuit diagram illustrating the virtual ground line precharge controller  121  and the virtual ground line precharging unit  131  of FIG. 1 according to some embodiments of the present invention. As shown in FIG. 2, the virtual ground line precharge controller  121  includes a NAND gate that receives the virtual ground line precharge control signal VPCON and the address control signal ACON as inputs and outputs the virtual ground line precharge signal VPRE (i.e., generates VPRE as a Boolean NAND operation of VPCON and ACON). The virtual ground line precharging unit  131 , as illustrated in the embodiments of FIG. 2, includes a PMOS transistor that has a source coupled to a power voltage VDD, a gate coupled to the virtual ground line precharge signal VPRE and a drain coupled to the virtual ground line VGL 1 .  
         [0037]    [0037]FIG. 3 is a circuit diagram illustrating the bit line precharge controller  141  and the bit line precharging unit  151  of FIG. 1 according to some embodiments of the present invention. As shown in FIG. 3, the bit line precharge controller  141  includes an inverter that receives the bit line precharge control signal BPCON as an input and outputs the bit line precharge signal BPRE. The bit line precharging unit  151 , as illustrated in the embodiments of FIG. 3, includes a PMOS transistor that has a source coupled to the power voltage VDD, a gate coupled to the bit line precharge signal BPRE and a drain coupled to the bit line BL 1 .  
         [0038]    [0038]FIG. 4 is a circuit diagram illustrating the discharge controller  161  and the switch  171  of FIG. 1 according to some embodiments of the present invention. As shown in FIG. 4, the discharge controller  161  includes a NAND gate that receives the discharge control signal DCON and the address signal ADD 0  as inputs and outputs the discharge signal DIS 0 . The switch  171  includes a NMOS transistor that has a drain coupled to the virtual ground line VGL 1 , a gate coupled to the discharge signal DIS 0  and a source coupled to ground.  
         [0039]    [0039]FIG. 5 is a timing diagram illustrating operations of the device  101  of FIG. 1. As shown in section (a) of FIG. 5, the virtual ground line precharge signal VPRE, the bit line precharge signal BPRE, and the discharge signal DISi are at a logic “low” level. The virtual ground lines VGLi and the bit lines Bli are precharged to a precharge voltage Vpre. As shown in section (b), the virtual ground line precharge signal VPRE and the discharge signal DISi are transitioned, substantially concurrently, to a logic “high” level and the virtual ground lines VGLi (VGL 1 , VGL 2 , etc. illustrated in FIG. 1) are grounded. The virtual ground lines VGLi are selectively grounded depending on whether their respective address signals (ADD 0 , ADD 1 , etc. illustrated in FIG. 1) are activated. However, as VPRE is deactivated (shown as a logic “high” level) the supply of the precharge voltage Vpre to the virtual ground lines VGLi stops at substantially the same time as when the virtual ground lines VGLi are selectively grounded. Thus, a short-circuit condition, in which current would flow from Vpre to the virtual ground lines VGLi, may be reduced or prevented.  
         [0040]    Even though the virtual ground lines VGLi are grounded and decoupled from the precharge voltage Vpre, the supply of the precharge voltage Vpre to the bit lines BLi (BL 1 , BL 2 , etc. illustrated in FIG. 1) is maintained. Thus, although the virtual ground lines VGLi may be adjacent to the bit lines BLi, the voltage of the bit lines Bli may not drop when the virtual ground lines VGLi are grounded. In other words any electronic coupling effect between the virtual ground and bit lines may be reduced.  
         [0041]    As shown at section (c) of FIG. 5, the bit line precharge signal BPRE is transitioned to a logic “high” deactivated level so the virtual ground line precharge signal VPRE, the bit line precharge signal BPRE and the discharge signal DISi are all at a logic “high” level. Thus, the virtual ground lines VGLi are still selectively grounded and the supply of the precharge voltage to the bit lines BLi stops. Therefore, in section (c), data stored in the ROM cell block  11  (illustrated in FIG. 1) may be read.  
         [0042]    As described above, the timing of precharging of the virtual ground lines (VGL 1 , VGL 2 , etc. illustrated in FIG. 1) and the bit lines (BL 1 , BL 2 , etc. illustrated in FIG. 1) are independently controlled. Thus, when the virtual ground lines (VGL 1 , VGL 2 , etc. illustrated in FIG. 1) are grounded, a short-circuit current may be reduced or prevented from flowing through the virtual ground lines. As a result, the operational speed of the ROM integrated circuit device  101  (illustrated in FIG. 1) may be increased and power consumption may be decreased. Furthermore, when the virtual ground lines (VGL 1 , VGL 2 , etc. illustrated in FIG. 1) are grounded, the supply of the precharge voltage Vpre to the bit lines (BL 1 , BL 2 , etc. illustrated in FIG. 1) may be continued. Thus, the precharge voltage Vpre of the bit lines may be reduced or prevented from dropping.  
         [0043]    In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.