Abstract:
Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Description:
RELATED APPLICATION 
     This non-provisional patent application is related to, and claims priority based upon, U.S. Provisional Patent Application Ser. No. 61/412,259, filed on Nov. 10, 2010, entitled “Methods and Systems for Production Testing of DCO Capacitors”, the disclosure of which is expressly incorporated here by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to capacitors and more specifically to testing systems and methods associated with production of DCO capacitors. 
     BACKGROUND 
     Ongoing technological developments have led to an increasing number of electronic and electrical devices, e.g., cell phones, which use and need the support of timing technologies. Phase locked loops (PLLs) found in integrated circuits are used in signal processing and synchronizing applications in support of these timing needs. A phase locked loop typically includes an oscillator and a phase detector for comparing the phases of two signals. Various forms of phase locked loops have been used over time for this purpose, including a digital phase locked loop (DPLL) which includes a digital controllable oscillator (DCO). 
     For transmitters with a polar and highly digitized architecture, a DCO can be used to generate the phase modulation (PM). To generate a transmitter (TX) signal with sufficient quality (e.g., low EVM and low spectral mask) the accuracy of the DCO frequency versus settings should be very good, e.g., the steps size should be approximately linear, e.g., for Bluetooth (BT) typically within a few percent. 
     The DCO can be tested on a production tester (ATE) to guarantee a good modulation quality before shipment to the customer. The area covered by the DCO including its quantity of capacitors is significant and therefore chances of structural errors are normally considered to be too high to leave it untested. The quality of the modulated signal can, for instance, be measured to test the quality of the DCO. However, there are at least two problems associated with this method. First, the measurement takes a relatively long time since many different sequences of test symbols are needed to get a good average of the signal quality (EVM). Secondly, the measurement is relatively complex to implement on a tester, since a complete demodulation algorithm needs to be build in the tester. 
     Alternatively the DCO can be tested with a simpler method, i.e., measuring of the frequency of the DCO over all settings. However, the change in frequency is relatively small (approx 40 ppm) so an even higher accuracy is normally needed to test the linearity of the steps, which requires relatively long measurement times. 
     Accordingly, it would be desirable to provide new testing systems and methods for DCO capacitors which avoid or reduce the above described drawbacks. 
     SUMMARY 
     Exemplary embodiments describe methods and systems for testing the capacitors within a digital controlled oscillator (DCO). By using the exemplary embodiments, the testing time can be reduced as compared to conventional testing methods. 
     According to an exemplary embodiment there is a test system for capacitors in a digitally controllable oscillator (DCO). The test system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; and a tone generator configured to generate a tone. The test system also includes a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off, to output an intermediate frequency signal having FM sidebands based on the modulation frequency; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands. 
     The modulation frequency of the test system can be generated by using a frequency source which is independent of the DCO. The selected one of the capacitors can be switched on and off when conditions of an XOR gate and an AND gate are met. Selecting of the first capacitor can be performed by a decoder. Additionally, the modulation frequency can be selected such that a measured FM sideband value is approximately −20 dBc. 
     According to another exemplary embodiment there is a method for testing a plurality of capacitors within a digital controllable oscillator (DCO). The method includes: selecting a first capacitor of the plurality of capacitors to be tested; and generating a carrier signal from the DCO while switching the first capacitor on and off at a modulation frequency. The method also includes mixing the carrier signal from the DCO with a test signal to generate an intermediate frequency (IF) signal; and determining a relative sideband level associated with a frequency modulated (FM) IF signal. 
     The method can also include generating the modulation frequency by dividing a frequency of the DCO by a divider, deselecting the first capacitor and selecting a second capacitor, wherein when the second capacitor has a different capacitance from the first capacitor the value of the divider can be changed such that the FM sideband level remains substantially unchanged. The method can also include generating the modulation frequency using a frequency source which can be independent of the DCO, wherein the selected first capacitor can be switched on and off when conditions of an XOR gate and an AND gate are met. Additionally, selecting of the first capacitor can be performed by a decoder and the modulation frequency can be selected such that a measured FM sideband value is approximately −20 dBc. 
     According to another exemplary embodiment there is a digital controllable oscillator (DCO) manufactured by the process including the steps of: selecting a first capacitor of the plurality of capacitors to be tested; generating an output signal from the DCO associated with the first capacitor; mixing the output signal from the DCO with a test signal; and evaluating a frequency deviation of a frequency modulated (FM) sideband of the first capacitor. 
     Wherein the process can also include: generating the modulation frequency by dividing a frequency of the DCO by a divider, deselecting the first capacitor; and selecting a second capacitor, wherein when the second capacitor has a different capacitance from the first capacitor the value of the divider can be changed such that the FM sideband level remains substantially unchanged. Wherein the process can also include: generating the modulation frequency using a frequency source which can be independent of the DCO. The selected first capacitor can be switched on and off when conditions of an XOR gate and an AND gate are met. Selecting of the first capacitor can be performed by a decoder. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings illustrate exemplary embodiments, wherein: 
         FIG. 1  illustrates a measurement setup according to an exemplary embodiment; 
         FIG. 2  is a block schematic of a capacitor bank and its control according to an exemplary embodiment; and 
         FIG. 3  is a flowchart illustrating a method according to exemplary embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description of the exemplary embodiments refers to the accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. Additionally, the drawings are not necessarily drawn to scale. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims. 
     Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
     As described in the background section various conventional methods for testing the capacitors of a digital controllable oscillator (DCO) can be relatively lengthy and complex. Exemplary systems and methods for testing DCOs according to embodiments of the present invention are described below. 
     According to exemplary embodiments, the DCO controls its frequency by switching in or out capacitors to the, frequency determining, inductor capacitor (LC) tank. The DCO can include, for example, multiple banks of different sized capacitors with a quantity of, for example, 100 capacitors. To measure the frequency step induced by one of those capacitors, the capacitor can be switched on and off, at a certain modulation frequency f m . Due to FM modulation, a sideband appears at the harmonics of f m . The level of the first sideband, relative to the main tone, is (A SB ): 
                         β   fm     =       Δ   ⁢           ⁢   f       2   ⁢           ⁢     f   m           ,     =   modulationindex       ⁢     
     ⁢       A   SB     =       β   fm     2               (   1   )               
where Δf is the amount of frequency deviation induced by the capacitor.
 
     The above formula is approximately correct under the condition of small band FM, which can be accomplished by selecting f m  larger than Δf. Exemplary embodiments operate under the assumption of small band FM since it simplifies matters, but this is not a requirement of exemplary embodiments. According to exemplary embodiments, by selecting the proper f m , the expected sideband can be made to be around −20 dBc, which sideband can be quickly and accurately measured with internal circuitry. 
     An exemplary configuration for measuring these FM sidebands is illustrated in  FIG. 1 . Therein, a receiver (RX)  100 , which can be a Bluetooth RX, a global system for mobile communications (GSM) RX, a wireless local area network (WLAN) RX, etc., is shown connected to test equipment (ATE)  102 , with the addition of a cross-correlator (CCR)  104  and a divider /R  106 . One of the capacitors in the capacitor bank  108  is toggled, for example, with the signal generated by the divider /R  106  (or another low frequency source) and switches  109 . Switch bank control  111  is discussed in more detail below with respect to  FIG. 2 . Toggling of the capacitor in bank  108  causes two sidebands to arise around the carrier frequency generated by the DCO  110 , (assuming relatively small band FM) as conceptually illustrated by graph  112 . This signal is mixed down to an intermediate frequency (IF) band  118  by means of the RX mixer  114  and the CW tone  116  coming from the ATE  102 . Normal signal processing of the IF band  118  by the receiver of interest, e.g., by filter  120  and the analog to digital converter (ADC)  122 , brings the signal to the CCR  104 . Here the levels of the main tone and one of the sidebands are measured. Note that this can be a relative measurement, as compared to an absolute measurement, such that RX  100  gain errors can be eliminated from the measurement. 
     Thus, according to exemplary embodiments, the ATE  102  generates a continuous wave (CW) tone  116 , which is down converted with the FM modulated signal from the DCO  110 . So at the IF there are three tones, i.e., the ATE  102  tone with the two sidebands coming from the FM modulation. In the CCR  104 , the level of the main tone and its side band are measured. The ratio between the two levels indicates the size of the capacitor in bank  108  which was toggled (switched). 
     Looking again at equation (1), it can be seen, according to exemplary embodiments, that the side band level does not directly depend on the DCO  110  frequency, only on the ratio between Δf and the modulation frequency f m . This characteristic of using FM sidebands to measure the capacitors, even a very small capacitor of a few aF that gives only a 10 kHz frequency deviation on 6 GHz, can result in a FM sideband of −18 dBc by selecting the modulation frequency f m =20 kHz. According to an exemplary embodiment, the modulation frequency f m  can be controlled by making the modulation frequency f m  a function of the DCO  110  frequency and the divider /R  106  as shown in equation 2.
 
 f   m   =DCO   freq /divider/ R   freq   (2)
 
For different sized capacitors, the frequency of divider /R  106  can be changed by logic associated with the divider /R  106 . Additionally, to reduce the time to test each capacitor, different f m  values can be used while still maintaining an acceptable FM sideband from a measurement point of view. The FM sideband level depends upon the following three items: (1) required accuracy of the capacitor measurement, (2) noise level in the measurement band, and (3) allowed measurement time. According to exemplary embodiments, a sideband level can approximately be in a range between −10 dBc and −50 dBc. This sideband level can comfortably be measured. With the above measurement, the frequency deviation that one capacitor introduces is measured, and not the absolute value of the capacitor. Alternatively, this absolute value could be calculated if the total capacitance value is known. However, the functionality of the DCO  110  and the DPLL  130  is assured when the frequency steps can be measured.
 
     Considering the sideband level and the three items which can affect it in more detail, noise level on the measurement provides an uncertainty on the measurement results. For an exemplary BT system, there can be a target accuracy which is better than 2% with a change of an erroneous measurement of 1 ppm. The measurement bandwidth is determined by the CCR  104  as shown in equation (2):
 
 N   bw =1 /T   meas   (2)
 
where T meas  is the integration time. A shortest integration time is one cycle of f m . The noise bandwidth cannot become larger than that of the IF strip of the receiver, e.g., 1 MHz. The amount of noise also depends upon the noise generation in the ATE  102 , the RX  100  and phase noise of the DPLL  130 .
 
     At a given capacitor with a certain Δf, selecting a higher f m  results in a shorter measurement time, assuming the CCR  104  integrates one cycle of Fm while decreasing the sideband level. The SNR becomes worse, i.e., the noise level goes up due to larger measurement bandwidth of the CCR  104  and the sideband level goes down. According to exemplary embodiments, if the SNR becomes too low to meet the desired accuracy requirements two things can be done to obtain a more desirable SNR. First the f m  can be decreased and secondly let the CCR integrate over multiple cycles of f m . Decreasing the f m  is typically more effective as both the sideband level goes up and the noise bandwidth of the CCR is reduced. Regarding the allowed measurement time, the measurement time is determined by the integration length of the CCR  104 , e.g., at least one cycle of FM or multiple cycles. 
     The toggling of one capacitor in the capacitor bank  108  is preferably performed such that the DPLL  130  remains in lock, ensuring a fixed frequency of the main tone out of the DCO  110 .  FIG. 2 , and the following paragraph describes how, for example, this can be accomplished. 
     On the right hand side of  FIG. 2 , the capacitor bank  108  is present; on the left hand side, the block controlling the capacitor bank is situated, which is part of the DPLL system  130 . To enable the toggling of one capacitor, the inputs to the capacitor bank  108  are preceded by digital logic including XORs  202 , which are driven by ANDs  204  and a decode block  206 . With the decode block  206  and the ANDs  204 , the capacitor to be enabled can be selected. Division by R of the DCO signal at block  106  derives a square wave modulation signal. This square wave modulation signal toggles the capacitors after the selected XOR  202  on/off. By making the modulation frequency high, compared to the loop bandwidth of the DPLL  130 , the behavior of the DPLL  130  is not disturbed and it remains in lock. Alternatively, if the sidebands of the DCO carrier fall outside the IF bandwidth, the ATE  102  generator can be adjusted so that the sidebands fall inside the IF bandwidth. 
     As a purely illustrative example, the following parameters can be selected or obtained, for operating the exemplary DCO test equipment as described above and illustrated in  FIGS. 1 and 2  as shown in Table 1. 
                                                     TABLE 1                   Smallest step of BT modulation bank   650   kHz       Choose f m     1.3   MHz            Measurement time of CCR   770 ns (one cycle of 1.3 MHz)            Sideband level   −18   dBc       DR of BT system in 1 MHz   76   dB       signal to noise ratio (SNR) of main tone   ≈70   dB       SNR of sideband   52   dB                    
This results in an inaccuracy for the main tone of 0.16% and for the side band of 1.3% assuming 0.1 ppm chance of higher value then measured. Also, the inaccuracy of the relative value of the sideband compared to the main tone is then 1.3%. By increasing the measurement time to 77us (100 cycles of 1.3 MHz) it reduces noise by 20 dB and inaccuracy becomes 0.13%. Therefore, with 0.1 ppm chance of a false escape, the measurement time and the inaccuracy of the frequency step are: (1) measurement time 770 ns, inaccuracy 1.3%, and (2) measurement time 77us, inaccuracy 0.13%.
 
     Exemplary embodiments provide for testing of DCOs  110  during a production test that is very quick as compared to conventional testing methods, with measurement accuracy that is high enough to verify linearity of the DCO  110 . Exemplary embodiments also provide for simple on-chip implementations that do not require much space. The divider /R  106  can be dedicated to this test with the CCR  104  being used for multiple measurements. Additionally, requirements on additional circuitry are relatively low, for example, divider /R  106  can be a divider from a general use digital library and the CCR  104  can be a digital circuit including two multipliers and two integrators. According to exemplary embodiments, only the frequency f m  needs to be accurate. Accurate frequency sources are readily available during production tests. 
     An exemplary method for testing a plurality of capacitors within a digital controllable oscillator is illustrated in  FIG. 3 . Therein, at step  302  selecting a first capacitor of the plurality of capacitors to be tested; at step  304  generating a carrier signal from the DCO while switching the first capacitor on and off at a modulation frequency; at step  306  mixing the carrier signal from the DCO with a test signal to generate an intermediate frequency (IF) signal; and at step  308 . determining a relative sideband level associated with a frequency modulated (FM) IF signal. 
     The above-described exemplary embodiments are intended to be illustrative in all respects, rather than restrictive, of the present invention. Thus the present invention is capable of many variations in detailed implementation that can be derived from the description contained herein by a person skilled in the art. No element, act, or instruction used in the description of the present application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items.