Abstract:
A method and apparatus for implementing a binary logarithm of most significant bit instruction that operates on an input signed binary number. The input signed binary number includes a fixed number of successive bits with an input most significant bit and a plurality of input lower significant bits. The method individually performs an exclusive-or operation on each of the input lower significant bits with the input most significant bit. The method then inputs an output unsigned binary number to an execute unsigned logarithm of most significant bit instruction, wherein the output unsigned binary number includes a fixed number of successive bits with a zero as an output most significant bit and the result of each of the exclusive-or operations as successive output lower significant bits. The apparatus includes a plurality of two input exclusive-or gates, each with the input most significant bit connected as a first input and one of the input lower significant bits connected as a second input, and an output connected to an input of an execute unsigned logarithm of most significant bit instruction.

Description:
This is a continuation of Provisional application Ser. No. 60/005,235, filed on Oct. 10, 1995, entitled EXTENDED POLYNOMIAL MATHEMATICS INSTRUCTIONS. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of computation involving unsigned binary numbers and signed (two&#39;s complement) binary numbers in a digital processor. 
     BACKGROUND OF THE INVENTION 
     Binary values are the paramount representation used in digital computation. Common forms of representing values are unsigned binary numbers and signed (or two&#39;s complement) binary numbers. 
     Unsigned binary numbers represent integer values from zero to a value which depends on the size of the operand: 2 size-  1. Each of the bits, labelled from zero at the least-significant bit position to (size-1) at the most-significant bit position, in such a number indicates a weight which is 2 position . The sum of each of the weights is the value of the unsigned binary number. It should be noted that the weight of the most significant bit is 2.sup.(size-1). 
     Signed binary numbers represent integer values from -2.sup.(size-1) to 2.sup.(size-1) -1. The value of the left-most bit (size-1) in these operands indicates the sign of the operand: 1 indicates a negative value, and 0 indicates a positive or zero value. The weight of the sign bit can be considered to be -2.sup.(size-1). The remaining bits, labelled from zero at the least-significant bit position to (size-2) at the most-significant bit position, in such a number indicates a weight which is 2 position . The sum of each of the weights is the value of the unsigned binary number. 
     Because unsigned and signed binary numbers differ only in the weight of the most-significant bit, certain operations, such as binary add or shift left, suffice for adding both signed and unsigned binary numbers. Other operations, such as shift right, are defined differently for unsigned and signed numbers. 
     Some binary computer systems include an instruction for returning the bit position of the first one (1), or most significant one (1) bit, of an unsigned binary number. Such an instruction has numerous uses, including normalizing unsigned binary numbers into a form where the most significant bit is shifted into a fixed location. Because the labelling of bits varies between computer systems, the definition of this instruction varies in turn. When the labelling of bits is in the little-endian bit order (where the least-significant bit of a binary number is labelled bit position zero and the most-significant bit is labelled bit position (size-1)), the result of such an instruction is not only the bit position, but also is the base-two logarithm of the most-significant one bit. A special condition results when the operand has a zero value (where no bits of any significance are set at all), in such a case it is appropriate to produce a value outside the normal range. 
     The existing binary computer systems, however, require three successive instructions for returning the bit position of the first one (1), or most significant one (1) bit, of a signed binary number. For example, in the case of 64-bit operands, an execute signed shift right immediate (&#34;E.SHR.I 63&#34;) instruction followed by an execute exclusive-or (&#34;E.XOR&#34;) instruction are required to modify the signed binary number prior to performing an execute unsigned logarithm of most significant bit (&#34;E.ULMSe&#34;) instruction to compute the desired bit position. Such instructions are known to those of ordinary skill in the art. The E.SHR.I 63 instruction generates a word of all ones or all zeros, depending on the sign of the operand, the E.XOR instruction exclusive-or&#39;s the value, and then the E.ULMS instruction computes the position of the most significant zero (0) bit in the event that the operand was negative. This succession of dependent instructions, relative to the operation cycle time of a 64-bit add instruction, therefore, requires three instruction cycles. It is therefore an object of the present invention to provide an instruction for computing the binary logarithm of most significant bit of a signed binary number in a single instruction cycle time. 
     Additionally, an operation or computation is said to overflow if the result is outside the range of values which the size of the result of the computation can represent. For example, if the result of a binary add is eight bits, an unsigned add of values 127 and 129 would produce an overflow. Some binary computer systems include instructions which check for overflow on certain computations. For example, the Hewlett-Packard PA-RISC processor includes an instruction &#34;ADD AND TRAP ON OVERFLOW&#34; which adds two 32-bit binary numbers and traps if a signed overflow occurs. 
     Execute shift left immediate and check unsigned overflow (&#34;E.SHL.I.UO&#34;) and execute shift left and check unsigned overflow (&#34;E.SHL.UO&#34;) instructions provide for the shifting of a value by a fixed or variable amount, respectively, while checking that the value has not shifted out a significant bit or overflow. Such an occurrence usually indicates a loss of precision by overflow of the fixed size of the operand. This shifting corresponds to a scaling of the value or a multiplication by a power of two. Such instructions are known to those of ordinary skill in the art. It is therefore a further object of the present invention to extend the foregoing instructions to signed arithmetic, in which the values represented are from -2.sup.(size-1) to 2.sup.(size-1) -1. 
     SUMMARY OF THE INVENTION 
     A method and apparatus for an improved signed binary logarithm system is provided by the present invention. The system implements a binary logarithm of most significant bit instruction that operates on an input signed binary number. The input signed binary number comprises a fixed number of successive bits with an input most significant bit and a plurality of input lower significant bits. The method of the present invention individually performs an exclusive-or operation on each of the input lower significant bits with the input most significant bit. The method then inputs an output unsigned binary number to an execute unsigned logarithm of most significant bit instruction, wherein the output unsigned binary number comprises a fixed number of successive bits with a zero as an output most significant bit and the result of each of the exclusive-or operations as successive output lower significant bits. 
     The present invention also provides an apparatus for implementing a binary logarithm of most significant bit instruction that operates on an input signed binary number. The apparatus comprises a plurality of two input exclusive-or gates, each with the input most significant bit connected as a first input and one of the input lower significant bits connected as a second input. The output of each of the exclusive-or gates connects to an input of an execute unsigned logarithm of most significant bit instruction. 
     Additionally, the present invention provides an alternative method for implementing a binary logarithm of most significant bit instruction that operates on an input signed binary number. This alternative method individually performs an exclusive-or operation on each of the input lower significant bits with the next successively lower input significant bit. The method then inputs an output unsigned binary number to an execute unsigned logarithm of most significant bit instruction. The output unsigned binary number comprises a fixed number of successive bits with a zero as an output most significant bit and the result of each of the exclusive-or operations as successive output lower significant bits. 
     An apparatus for implementing the alternative binary logarithm of most significant bit instruction comprises a plurality of successive two input exclusive-or gates, each with one of the lower significant bits connected as a first input and the next successively lower significant bit connected as a second input. The output of each of the exclusive-or gates connects to an input of an execute unsigned logarithm of most significant bit instruction. 
     The present invention provides advantages over the prior art by providing a method and apparatus for executing an instruction for computing the binary logarithm of most significant bit of a signed binary number in a single instruction cycle time. Moreover, the present invention also provides a method and apparatus for executing shift left immediate and check unsigned overflow, and executing shift left and check unsigned overflow, instructions, while checking that the value has not shifted out a significant bit or overflow, on signed binary numbers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block diagram of a first embodiment of the signed binary logarithm system of the present invention. 
     FIG. 2 illustrates a first circuit implementation of the Sign Bit Converter of FIG. 1. 
     FIG. 3 illustrates a second circuit implementation of the Sign Bit Converter of FIG. 1. 
     FIG. 4 illustrates a block diagram of a second embodiment of the signed binary logarithm system of the present invention. 
    
    
     DETAILED DESCRIPTION 
     A binary number processing system is described. In the following description, numerous specific details are set forth, such word size, address field size and bus widths etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known system structures have not been described in detail in order to avoid unnecessarily obscuring the present invention. 
     System Overview 
     The following disclosure employs several operations which perform functions as expressed by the following pseudo-code: 
     Execute Operations: 
     
         ______________________________________Operation codes______________________________________E.ADD     Execute addE.ADD.O   Execute add and check signed overflowE.ADD.UO  Execute add and check unsigned overflowE.AND     Execute andE.ANDN    Execute and notE.ASUM    Execute and summation of bitsE.LMS     Execute signed logarithm of most significant bitE.NAND    Execute not andE.NOR     Execute not orE.OR      Execute orE.ORN     Execute or notE.ROTL    Execute rotate leftE.ROTR    Execute rotate rightE.SELECT.8     Execute select bytesE.SHL     Execute shift leftE.SHL.O   Execute shift left and check signed overflowE.SHL.UO  Execute shift left and check unsigned overflowE.SHR     Execute signed shift rightE.ULMS    Execute unsigned logarithm of most significant bitE.USHR    Execute unsigned shift rightE.XNOR    Execute exclusive norE.XOR     Execute xor______________________________________ 
    
     Format: ##STR1## Description: 
     The operands in registers ra and rb are fetched and the specified operation is performed on these operands. 
     Definition: 
     
         __________________________________________________________________________def Execute(op,ra,rb,rc) asa ← RegRead(ra, 64)b ← RegRead(rb, 64)case op ofE.ROTL:    c ← a.sub.(63-b.sbsb.5..0.sub.)..0 ∥ a.sub.63.(64-b    .sbsb.5.0.sub.)E.ROTR:    c ← a.sub.(b.sbsb.5.0.sub.-1)..0 ∥ a.sub.63..b.sbsb    .5.0E.SHL:    c ← a.sub.(63-b.sbsb.5.0.sub.)..0 ∥ 0.sup.b.sbsp.5.    0E.SHL.O:    if a.sub.63.63-b.sbsb.5.0 ≠ a.sub.63.sup.b.spsb.5.0+    then       raise FixedPointArithmetic    endif    c ← a.sub.(63-b.sbsb.5.0.sub.)..0 ∥ 0.sup.b.sbsp.5.    0E.SHL.UO:    if a.sub.63.64-b.sbsb.5.0 ≠ 0 then       raise FixedPointArithmetic    endif    c ← a.sub.(63-b.sbsb.5.0.sub.)..0 ∥ 0.sup.b.sbsp.5.    0E.SHR:    c ← a.sub.63.sup.b.sbsp.5.0 ∥ a.sub.63.b.sbsb.5.0E.USHR:    c ← 0.sup.b.sbsp.5.0 ∥ a.sub.63.b.sbsb.5.0E.ADD:    c ← a + bE.ADD.O:    t ← (a.sub.63 ∥ a) + (b.sub.63 ∥ b)    if t.sub.64.sbsb.-- t.sub.63 then       raise FixedPointArithmetic    endif    c ← t.sub.63..0E.ADD.UO:    t ← (0.sup.1 ∥ a) + (0.sup.1 ∥ b)    if t.sub.64-- 0 then       raise FixedPointArithmetic    endif    c ← t.sub.63..0E.AND:    c ← a and bE.OR.:    c ← a or bE.XOR:    c ← a xor b:E.ANDN:    c ← a and not bE.NAND:    c ← not (a and b)E.NOR:    c ← not (a or b)E.XNOR:    c ← not (a xor b)E.ORN:    c ← a or not bE.LMS:    if (a=0) then       c ← -1    else       for i ← 0 to 63          if a.sub.63..i = (a.sub.63.sup.63-i ∥ not          a.sub.63) then             c ← i          endif       endfor    endifE.ULMS:    if (a=0) then       c ← -1    else       for i ← 0 to 63          if a.sub.63..i = (0.sup.63-i ∥ 1) then             c ← i          endif       endfor    endifE.ASUM:    t ← a &amp; b    u ← (t.sub.63..1 &amp;0x5555555555555555) + (t&amp;0x555555555555555    5)    v ← (u.sub.63..2 &amp;0x3333333333333333) + (u&amp;0x333333333333333    3)    w ← (v.sub.63..4 &amp;0x707070707070707) + (v&amp;0x0707070707070707    )    x ← (w.sub.63..8 &amp;0xf000f000f000f) + (w&amp;0x000f000f000f000f)    O    c ← x.sub.52..48 + x.sub.36..32 + x.sub.20..16    + x.sub.4..0E.SELECT.8:    for i ← 0 to 7       j ← b.sub.3*i+2..3*i       c.sub.8*i+7..8*i ← a.sub.8*j+7..8*j    endforendcaseRegWrite(rc, 64, c)enddef__________________________________________________________________________ 
    
     Execute Short Immediate operations: 
     
         ______________________________________Operation codes______________________________________E.ROTR.I Execute rotate right immediateE.SHL.I  Execute shift left immediateE.SHL.I.O    Execute shift left immediate and check signed overflowE.SHL.I.UO    Execute shift left immediate and check unsigned    overflowE.SHR.I  Execute signed shift right immediateE.SHUFFLE.I    Execute shuffle immediateE.USHR.I Execute unsigned shift right immediate______________________________________ 
    
     Format: ##STR2## Description: 
     The operand in register ra is fetched and a 6-bit immediate operand is fetched from the 6-bit simm field. The specified operation is performed on these operands and the result is placed in register rb. 
     Definition: 
     
         __________________________________________________________________________def ExecuteShortImmediate(op,ra,rb,simm) asa ← RegRead(ra, 64)case op ofE.SHUFFLE.I:case simm of   0:     b ← a   1..35:     for x ← 0 to 7; for y ← 0 to x-1; for z ← 1 to     x-y       if simm = ((x*x*x-3*x*x-4*x)/6-(z*z-z)/2+x*z+y+1) then         for i ← 0 to 63           b.sub.i ← a.sub.(i.sbsb.7.x .sub.∥ i.sbsb.y+           z-1..y .sub.∥ i.sbsb.x-1.y+z .sub.∥           i.sbsb.y-1..0.sub.)         end       endif     endfor; endfor; endfor   36..255:     raise ReservedInstructionendcaseE.ROTR.I:b ← a.sub.simm-1.0 ∥ a.sub.63.simmE.SHL.I:b ← a.sub.63-simm..0 ∥ 0.sup.simmE.SHL.I.O:if a.sub.63..63-simm-- a.sub.63.sup.simm+  then   raise FixedPointArithmeticendifb ← a.sub.63-simm..0 ∥ 0.sup.simmE.SHL.I.UO:if a.sub.63..64-simm-- 0 then   raise FixedPointArithmeticendifb ← a.sub.63-simm..0 ∥ 0.sup.simmE.SHR.I:b ← a.sub.63.sup.simm ∥ a.sub.63..simmE.USHR.I:b ← 0.sup.simm ∥ a.sub.63..simmendcaseRegWrite(rb, 64, b)enddef__________________________________________________________________________ 
    
     FIG. 1 illustrates a block diagram of a first embodiment of the signed binary logarithm system of the present invention. FIG. 1 shows instruction fetch and decoder control unit 101 coupled to register file 102, unsigned LMS (logarithm of most significant bit) 104, shifter 105, other data path elements 106 and shift overflow detect 107 via decoded instruction bus 108. The register file 102 is coupled via operand values buses 110 to signed bit converter 103, unsigned LMS 104, shifter 105, and other data path elements, and provides operands for each of the coupled units. The sign bit converter 103 is a central element of the present invention and is described in detail below. The sign bit converter 103 is coupled to the unsigned LMS unit 104 via converted value bus 111. The unsigned LMS unit 104 is coupled to the shift overflow detect unit 107 via logarithm bus 112. The unsigned LMS unit 104, shifter 105 and other data path elements 106 produce result values which are returned to the register file 102 via result value bus 109. 
     The present invention relates to the processing of unsigned binary values and signed (two&#39;s complement) binary values in a digital processor. Unsigned binary values represent numbers from zero to a value which depends on the size of the operand (2 size  -1). The instructions described here are implemented as 64-bit operands, however, it should be understood that the size may vary without departing from the spirit and scope of the invention. 
     The instruction E.ULMS computes the position of the most significant bit that has the value one (1) in the source operand, using little-endian bit numbering, and returns that position. If none of the bits are one (1), the source operand is zero, and a negative one value (with all result bits set) is returned. This instruction is known in the art, and is sometimes described as a find first one (&#34;FFO&#34;) instruction. 
     There are several uses for this instruction, one of which involves the normalization of fixed-point quantities into values in which the most-significant bit is in a known position by shifting the operand toward the left (toward the higher bit numbers). In such a case, the value computed by E.ULMS is subtracted from the desired bit position (e.g. with an E.SUB.I &#34;position&#34; instruction), and then the original operand is shifted (e.g. with an execute shift left (&#34;E.SHL&#34;) instruction). 
     The first embodiment of the present invention extends the foregoing instructions to signed arithmetic, in which the values represented are from -2.sup.(size-1) to 2.sup.(size-1) -1. The value of bit 63 (size-1) in these operands indicates the sign of the operand (1 indicates a negative value, and 0 indicates a positive or zero value). 
     The first embodiment provides an E.LMS instruction which computes the position of the most significant bit of a signed binary value that is a one (1) when the sign is positive or zero (bit 63 is a zero), or a zero (0) when the sign is negative (bit 63 is a one). The E.LMS instruction executes the sequence of three instructions (E.SHR.I 63, E.XOR, and E.ULMS, as described in the &#34;BACKGROUND OF THE INVENTION&#34; section, above) in a single instruction cycle time, as discussed above. The cascading of the E.SHR.I 63 and E.XOR instructions carried out by the E.LMS instruction of the present invention occurs in a fraction of a single instruction cycle time, and thus leaves enough of the instruction cycle for executing the E.ULMS instruction. Therefore, for example, using the E.LMS instruction of the present invention, followed by E.SUB.I and E.SHL instructions, as described above, a signed binary value can be normalized in a significantly quicker period of time. 
     The cascading of the E.SHR.I 63 and E.XOR instructions carried out by the E.LMS instruction of the present invention suggests a first hardware implementation as shown in FIG. 2. Operand value bus 110 is divided into individual bits by the divide bus to bits 204 (which contains no logic), producing 64 individual signals labeled bit 0 through bit 63. The first bit 207 is the least significant bit, or bit 0; the second bit 208 is bit 1; the last bit 206 is bit 62; and the sign bit 201 is bit 63. The sign bit 201 is coupled to a first input of each of 63 exclusive-or gates 202, which compute the exclusive-or of bit 63 with each of bits 62 through bit 0 of the operand value bus 110. These outputs are collected together, along with a single zero bit 203, by the collect bits to bus 205 (which contains no logic), producing the converted value 111. 
     The foregoing first hardware implementation, however, has the disadvantage that the sign bit must be driven across the entire data path (from bit 63 to bit 0), and thus necessitating a fan-out of 63. This is a general feature of the E.SHR.I instruction, but in this case it is desired to provide the sequence of three instructions (E.SHR.I 63, E.XOR, E.ULMS) in the same time as that of a single instruction. Therefore, the long path of the sign bit (bit 63) can limit performance. 
     A second hardware implementation of the cascading of the E.SHR.I 63 and E.XOR instructions carried out by the E.LMS instruction of the present invention, therefore, embodies an improvement in the performance of the configuration of the first hardware implementation, above. This second hardware implementation stems from the discovery that the E.LMS instruction can also be computed by E.SHR.I 1, E.XOR, E.ULMS. The E.SHR.I 1 instruction generates a value in which the bit in the position of the most significant bit has the value of the sign, and all higher bit positions also have the value of the sign. The remaining bit positions are less significant, both figuratively and literally. The E.XOR instruction then generates a value which has little mathematical meaning except that the leading one (1) bit is in the same position as previously computed with E.SHR.I 63 and E.XOR. 
     This leads to an implementation of E.LMS in which the E.SHR.I 1 and E.XOR instructions optionally precede the E.ULMS instruction, and now the sign bit has but a single fan-out, as shown in FIG. 3. Operand value bus 110 is divided into individual bits by the divide bus to bits 308 (which contains no logic), producing 64 individual signals, labeled bit 0 through bit 63. The first bit 301 is the least significant bit, or bit 0; the second bit 302 is bit 1; the third bit 303 is bit 2; the last bit 304 is bit 62; and the sign bit 305 is bit 63. The sign bit 305 and the last bit 304 are coupled to inputs of the last exclusive-or gate 312 of the 63 exclusive-or gates 307, but each of the remaining exclusive-or gates 307 are coupled differently from FIG. 2. The inputs of the first exclusive-or 310 are coupled to the first bit 301 and second bit 302, and the inputs of the second exclusive-or 311 are coupled to the second bit 302 and third bit 303. The remaining exclusive-or gates are coupled in similar fashion, with one input coupled to the operand bit of the same bit position as the output bit position, and the second input coupled to the operand bit in a bit position one greater than the output bit position. These outputs are collected together, along with a single zero bit 306, by the collect bits to bus 309 (which contains no logic), producing the converted value 111. 
     As shown in FIG. 1, the unsigned LMS unit 104 computes the E.ULMS result from either operand values bus 110 or converted value 111, depending upon the decoded instruction 108. An implementation of the unsigned LMS unit 104 can contain a multiplexor to select one of these two possible input values. The instructions described above (E.SHR.I 1 and E.XOR) implemented in sign bit converter 103 can be combined with the multiplexor from unsigned LMS unit 104 into a logic block grouping which may be implemented in a single logic stage (and-or-invert). It is also notable that the E.SHL.UO/E.SHL.I.UO and E.SHL.O/E.SHL.I.O instructions may use the E.ULMS/E.LMS data path (sign bit converter 103 and unsigned LMS unit 104) to determine whether the E.SHL instruction causes the value to overflow. The overflow condition occurs when the sum of the E.ULMS result and shift amount is greater than 63 for E.SHL.UO and E.SHL.I.UO instructions and the sum of the E.LMS result and shift amount is greater or equal to 63 for E.SHL.O and E.SHL.I.O instructions. This computation can proceed in parallel, implemented in the shift overflow detect unit 107, coupled to unsigned LMS unit 104, coupled to sign bit converter unit 103, with the operation of the shifter unit 105 which computes the E.SHL result. 
     A second embodiment of the present invention achieves further improvements in performance of the sequence of instructions required to, for example, normalize a value (as described above) can be accomplished as a sequence of instructions, E.LMS/E.ULMS, E.SUB.I, and E.SHL, implemented by a further cascade of data path elements. In particular, a cascade of data path elements producing the E.LMS or E.ULMS values with an adder/subtractor which can be controlled as a single instruction leads to a further improvement in performance by reducing the number of instructions without an inordinate increase in instruction latency. This improvement is particularly useful and practical as the size of the E.LMS/E.ULMS result is much smaller than the operand width, so an adder/subtractor which modifies the result need only produce a six or seven bit result for a 64-bit operand. Thus, an additional data path element may be dedicated to this purpose at much lower cost than the use of the general adder/subtractor unit which is part of other data path elements 106. It can also be noted that the shift overflow detect unit 107 may be implemented with just such an adder/subtractor and can be shared for this purpose, further reducing implementation cost. 
     FIG. 4 illustrates the system of the second embodiment, in which the result from an adder/subtractor within the adder/subtractor and shift overflow detect unit 407 may be coupled to the register file 102 via result value bus 109. This improved system is capable of executing single instructions E.LMS.SUB.I, E.ULMS.SUB.I, E.LMS.ADD.I, and E.LMS.SUB.I in a single flow of logic through the data path. Further, the logic blocks of the unsigned LMS 104 and the adder/subtractor and shift overflow detect 407 may be combined together for additional logic level optimization. 
     Although the elements of the present invention have been described in conjunction with certain embodiments, it is appreciated that the invention may be implemented in a variety of other ways. Consequently, it is to be understood that the particular embodiment shown and described by way of illustration are in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention.