Abstract:
Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

Description:
BACKGROUND 
     Data storage devices generally operate to store and retrieve data in a fast and efficient manner. Some storage devices take the form of a memory card that utilizes memory cells to provide various external functions. The Personal Computer Memory Card International Association (PCMCIA) was formed to standardize computer memory cards. The PCMCIA provides physical specifications for three types of cards, specifically differing in thickness. 
     As will be appreciated, a computer memory card has limited physical space and power availability. An increased variety of available computer memory technologies has created a need to improve the compatibilities of existing technology while not impeding the inherent physical space and power limitations of standardized PC Cards. Moreover, an ever expanding mobile technology culture has increased the need for faster and more reliable computer memory technologies that have various mobile compatibilities. 
     In these and other types of data storage devices, it is often desirable to improve efficiency and accuracy, particularly with regard to reading data from a computer memory device capable of broad compatibility. 
     SUMMARY 
     Various embodiments of the present invention are generally directed to a method and apparatus associated with a memory device with multiple interfaces and a status register. 
     In accordance with various embodiments, the first memory device has multiple interfaces configured to engage a host and at least a second memory device comprising a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material. The first memory device maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations. 
     These and various other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a generalized functional representation of an exemplary data storage device constructed and operated in accordance with various embodiments of the present invention. 
         FIG. 2  shows circuitry used to read data from and write data to a memory array of the device of  FIG. 1 . 
         FIG. 3  generally illustrates a manner in which data can be written to a memory cell of the memory array. 
         FIG. 4  generally illustrates a manner in which data can be read from the memory cell of  FIG. 3 . 
         FIG. 5  displays a memory cell structure operated in accordance with various embodiments of the present invention. 
         FIG. 6  generally illustrates an alternative memory cell structure operated in accordance with various embodiments of the present invention. 
         FIG. 7  shows the types of personal computer memory cards operated in accordance with various embodiments of the present invention. 
         FIG. 8  displays a host and multiple memory devices operated in accordance with various embodiments of the present invention. 
         FIG. 9  generally illustrates multiple memory devices with partial cutouts operated in accordance with various embodiments of the present invention. 
         FIG. 10  shows multiple memory devices with partial cutouts operated in accordance with various embodiments of the present invention. 
         FIG. 11  shows a flow diagram for a voltage reference characterization in accordance with various embodiments of the present invention. 
         FIG. 12  shows a flow diagram for a status registry operation in accordance with various embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  provides a functional block representation of a data storage device  100  constructed and operated in accordance with various embodiments of the present invention. The data storage device is contemplated as comprising a portable non-volatile memory storage device such as a PCMCIA card or USB-style external memory device. It will be appreciated, however, that such characterization of the device  100  is merely for purposes of illustrating a particular embodiment and is not limiting to the claimed subject matter. 
     Top level control of the device  100  is carried out by a suitable controller  102 , which may be a programmable or hardware based microcontroller. The controller  102  communicates with a host device via a controller interface (I/F) circuit  104  and a host I/F circuit  106 . Local storage of requisite commands, programming, operational data, etc. is provided via random access memory (RAM)  108  and read-only memory (ROM)  110 . A buffer  112  serves to temporarily store input write data from the host device and readback data pending transfer to the host device. 
     A memory space is shown at  114  to comprise a number of memory arrays  116  (denoted Array  0 -N), although it will be appreciated that a single array can be utilized as desired. Each array  116  comprises a block of semiconductor memory of selected storage capacity. Communications between the controller  102  and the memory space  114  are coordinated via a memory (MEM) I/F  118 . As desired, on-the-fly error detection and correction (EDC) encoding and decoding operations are carried out during data transfers by way of an EDC block  120 . 
     While not limiting, in some embodiments the various circuits depicted in  FIG. 1  are arranged as a single chip set formed on one or more semiconductor dies with suitable encapsulation, housing and interconnection features (not separately shown for purposes of clarity). Input power to operate the device is handled by a suitable power management circuit  122  and is supplied from a suitable source such as from a battery, AC power input, etc. Power can also be supplied to the device  100  directly from the host such as through the use of a USB-style interface, etc. 
     Any number of data storage and transfer protocols can be utilized, such as logical block addressing (LBAS) whereby data are arranged and stored in fixed-size blocks (such as 512 bytes of user data plus overhead bytes for ECC, sparing, header information, etc). Host commands can be issued in terms of LBAs, and the device  100  can carry out a corresponding LBA-to-PBA (physical block address) conversion to identify and service the associated locations at which the data are to be stored or retrieved. 
       FIG. 2  provides a generalized representation of selected aspects of the memory space  114  of  FIG. 1 . Data are stored as an arrangement of rows and columns of memory cells  124 , accessible by various row (word) and column (bit) lines, etc. In some embodiments, each of the array memory cells  124  has magnetic random access memory (MRAM) configuration, such as a spin-torque transfer random access memory (STTRAM or STRAM) configuration. 
     The actual configurations of the cells and the access lines thereto will depend on the requirements of a given application. Generally, however, it will be appreciated that the various control lines will generally include enable lines that selectively enable and disable the respective writing and reading of the value(s) of the individual cells. 
     Control logic  126  receives and transfers data, addressing information and control/status values along multi-line bus paths  128 ,  130  and  132 , respectively. X and Y decoding circuitry  134 ,  136  provide appropriate switching and other functions to access the appropriate cells  124 . A write circuit  138  represents circuitry elements that operate to carry out write operations to write data to the cells  124 , and a read circuit  140  correspondingly operates to obtain readback data from the cells  124 . Local buffering of transferred data and other values can be provided via one or more local registers  144 . At this point it will be appreciated that the circuitry of  FIG. 2  is merely exemplary in nature, and any number of alternative configurations can readily be employed as desired depending on the requirements of a given application. 
     Data are written to the respective memory cells  124  as generally depicted in  FIG. 3 . Generally, a write power source  146  applies the necessary input (such as in the form of current, voltage, magnetization, etc.) to configure the memory cell  124  to a desired state. It can be appreciated that  FIG. 3  is merely a representative illustration of a bit write operation. The configuration of the write power source  146 , memory cell  124 , and reference node  148  can be suitably manipulated to allow writing of a selected logic state to each cell. 
     As explained below, in some embodiments the memory cell  124  takes a modified STRAM configuration, in which case the write power source  146  is characterized as a current driver connected through a memory cell  124  to a suitable reference node  148 , such as ground. The write power source  146  provides a stream of power that is spin polarized by moving through a magnetic material in the memory cell  124 . The resulting rotation of the polarized spins creates a torque that changes the magnetic moment of the memory cell  124 . 
     Depending on the magnetic moment, the cell  124  may take either a relatively low resistance (R L ) or a relatively high resistance (R H ). While not limiting, exemplary R L  values may be in the range of about 100 ohms (Ω) or so, whereas exemplary R H  values may be in the range of about 100KΩ or so Other resistive memory type configurations (e.g., RRAMS) are supplied with a suitable voltage or other input to similarly provide respective R L  and R H  values. These values are retained by the respective cells until such time that the state is changed by a subsequent write operation. While not limiting, in the present example it is contemplated that a high resistance value (R H ) denotes storage of a logical 1 by the cell  124 , and a low resistance value (R L ) denotes storage of a logical 0. 
     The logical bit value(s) stored by each cell  124  can be determined in a manner such as illustrated by  FIG. 4 . A read power source  150  applies an appropriate input (e.g., a selected read voltage) to the memory cell  124 . The amount of read current I R  that flows through the cell  124  will be a function of the resistance of the cell (R L  or R H , respectively). The voltage drop across the memory cell (voltage V MC ) is sensed via path  152  by the positive (+) input of a comparator  154 . A suitable reference (such as voltage reference V REF ) is supplied to the negative (−) input of the comparator  154  from a reference source  156 . 
     The reference voltage V REF  can be selected from various embodiments such that the voltage drop V MC  across the memory cell  124  will be lower than the V REF  value when the resistance of the cell is set to R L , and will be higher than the V REF  value when the resistance of the cell is set to R H . In this way, the output voltage level of the comparator  154  will indicate the logical bit value (0 or 1) stored by the memory cell  124 . 
       FIG. 5  generally displays a memory cell structure operated in accordance with the various embodiments of the present invention. A magnetic tunneling junction (MTJ)  158  is shown coupled to multiple spin polarizing magnetic materials  160 . It can be appreciated that the MTJ  158  can be coupled to a single spin polarizing magnetic material  160 . Likewise, the spin polarizing material  160  can be a variety of materials. For example, a first spin polarizing material  160  can be coupled to one side of an MTJ  158  while a different substance can be used for another spin polarizing material  160 . 
     An alternate memory cell structure is shown in  FIG. 6  operated in accordance with the various embodiments of the present invention. A magnetic tunneling junction  158  is generally displayed with multiple spin polarizing materials  160  incorporated into the MTJ  158 . In some embodiments, the spin polarizing material  160  can be coupled to a pinned layer  162  as well as a free layer  164 . It should be noted that the spin polarizing material  160  can be located on a single side of the MTJ  158 . Similarly, the pinned layer  162  alternatively can be a second free layer  164  capable of opposing magnetic polarity phases. The pinned layer  162  and the free layer  164  are separated by a tunneling barrier  166  that allows unique magnetic phases to exist in the pinned layer  162  in relation to the free layer  164 . Further, the pinned layer  162  and tunnel barrier  166  are separated by a reference layer  168  that maintains the magnetization direction of the pinned layer  162 . 
       FIG. 7  illustrates an exemplary personal computer memory cards (PC Card) that can be utilized with various embodiments of the present invention. A Type I PC Card  168  is conventionally used for memory devices such as random access memory (RAM), Flash, Static random access memory (SRAM), and one-time programmable (OTP) circuits. A Type II PC Card  170  is generally used for input/output (I/O) operations such as data/fax modems and mass storage devices. Finally, a Type III PC Card  172  is conventionally used for devices whose components are thicker, such as rotating mass storage devices. Typically, the only variation in the types of PC cards is the physical thickness of the card. That is, the connector, physical length, and physical width are standardized to fit universally into PC card slots. 
     The operational relationship between multiple memory devices is generally shown in  FIG. 8 . In one embodiment of the present invention, a first memory device  176  having a first connector  178  capable of engaging a host interface  180  of a host device  182 . Furthermore, the first memory device  176  has at least a second interface  184  capable of engaging a second memory device  186  through a connector  188 . In some embodiments, the host interface  180  includes an allocation of memory used as for buffering purposes during the transaction of data between the host device  182  and the first memory device  176 . 
       FIG. 9  displays a first memory device  176  operationally engaging multiple second memory devices  186 . Each second memory device  186  has a connector  188  that allows engagement with a first interface  184 . It can be appreciated that the first memory device  176  can be configured to accept any number of second memory devices  186 . As shown, two second memory devices  186  are capable of engaging the first memory device  176  individually or together to connect a number of memory modules  190 . In some embodiments, the second memory devices  186  each comprise multiple memory modules  190  that contain a plurality of memory cells. 
     Further, the memory modules  190  can be operated individually or in conjunction with other modules to provide the first memory device  176  with a various amount of functional capacity. It should be noted that each of the second memory devices  186  can comprise memory modules  190  of different memory technologies. For example, one second memory device  186  can utilize spin-torque transfer random access memory technology while another second memory device  186  can utilize resistive random access memory technology. That is, each memory module  190  can be a single type of memory, such as STRAM, but memory modules of differing memories can be implemented into the same memory device. 
     The first memory device  176  includes, in various embodiments, control circuitry capable of controlling the functions of the device  176 . The control circuitry can comprise a number of microprocessors  192 , read only memory (ROM), and power converter. Alternatively, the ROM can be implemented into a processor as can be appreciated by one skilled in the art. 
     An operational interaction between the first memory device  176  and a second memory device  186  is generally illustrated in  FIG. 10 . An embodiment of the present invention has the first memory device  176  being comprised of a control circuitry  192  that accesses memory modules  190  of the second memory device  186 . The processing completed by the various components of the control circuitry communicate with a memory controller  194  in the second memory device  186  to provide the most efficient access to memory space. The components of the control circuitry such as the microprocessors  192  are capable of communicating with each memory module  190  and the memory controller  194  through a variety of signals  196 . The variety of signals  196  can include, but are not limited to, data, logical address, control signals, read/write operations, clock, data mask, and interrupt request, etc. 
     In some embodiments, the memory interface  184  of the first memory device  176  can be configured to include a non-volatile memory controller to aid in the efficiency and accuracy of memory device data management. In addition, the control circuitry of the first memory device  176  can comprise a controller that allows direct memory access (DMA) connection to a main memory. The main memory can comprise various memory technologies including, but not limited to, DRAM, SRAM, FLASH, ROM, STRAM, RRAM, and SSD. Likewise, the memory modules  190  of the second memory device  186  can utilize various memory technologies such as DRAM, SRAM, FLASH, ROM, STRAM, RRAM, and SSD. However, one embodiment of the present invention includes at least one memory module  190  utilizing spin polarizing material and an MTJ ( 158  and  160  of  FIGS. 5 and 6 ). 
     The flow diagram of  FIG. 11  displays a voltage reference characterization  200  that functions in one embodiment on initial power up. Upon a plurality of memory cells first receiving power, an embodiment of the present invention begins to characterize the array for reference values. First, all memory cells are treated as a single block and written to an initial logical state, such as a logic state of 0 in step  202 . A voltage reference is then optimized in step  204  by producing several distributions of resistance values through the application of a series of test signals for each memory cell. 
     In one embodiment, a resistance value distribution is produced by repetitively reading each cell in turn using different voltage reference values that successively change in magnitude, and monitoring the output of a sense amplifier. The resistance of the cell can be correlated to the reference voltage at which the output of the sense amplifier changes state. 
     For example, if the cell is initially written to a logic state of 0, the resistance of the cell will be relatively low (R L ), and the voltage drop thereacross will also be relatively low for a given sense current. Use of an initial, relatively high voltage reference value will provide an output of 0 from the sense amplifier. Incrementally decreasing the reference voltage will eventually provide a reference value below the voltage drop across the cell, at which point the output of the sense amplifier ( 154  of  FIG. 4 ) will switch to a logical 1. 
     This reference value can be used as an indication of the actual R L  resistance of the cell; that is, the resistance R L  will be substantially equal to the reference value divided by the sense current. Because of this proportionality, the resistance of the cell can be “read” merely by detecting the corresponding transition reference voltage, irrespective of whether the actual resistance of the cell is specifically calculated therefrom. 
     Once low resistance reference values have been obtained for all of the cells, the cells are written to a logic state of 1 and the foregoing process is repeated (the initial reference values and direction of sweeping may be the same, or may be different as desired). It will be appreciated that the foregoing example is merely illustrative and any number of sensing techniques can be used to determine the respective distributions through the optimization process of step  204 . 
     The optimization of the voltage reference in step  204  then proceeds to compare a low resistance maximum value obtained from the low resistance distribution to a high resistance minimum value obtained from the high resistance distribution. A differentiation between resistance distributions is indicated by having the high resistance minimum being greater than the low resistance maximum. An embodiment of the present invention stores the voltage reference for the block of memory in a table at step  206  if the high resistance minimum is greater than the low resistance maximum. However if the high resistance minimum is less than the low resistance maximum, there will be an overlap in the distributions, so the use of a single global reference value may not correctly identify the logic state of all cells. In such case, the memory block will be sub-divided in step  208 . 
     The sub-divide operation of step  208  creates extra table entries to accommodate the sub-division of blocks in step  208 . The sub-division of blocks divides the previous memory block into predetermined smaller block sizes. Once the memory blocks are divided, the optimization of the extra memory cells is entered and operated. 
     It should be noted that the sub-division of memory block in step  208  likely occurs in a high percentage of voltage reference characterization  200  due to the fact that a single voltage reference for a plurality of memory cells will often not provide accurate logical state reading. Therefore, the sub-division of memory cells  208  will cycle and continue to sub-divide the memory blocks until optimal differentiation of resistance distributions are obtained. Thus, it is recognized that the voltage reference characterization  200  can produce a single voltage reference or a voltage reference for every bit in a memory array as necessary. 
       FIG. 13  shows a flow chart of a status registry operation  210  performed in accordance with the various embodiments of the present invention. In some embodiments, the status registry operation  210  is carried out by a host computer microprocessor or a processor of the first memory device ( 186  of  FIGS. 8 ,  9 , and  10  in communication with the memory modules ( 190  of  FIGS. 9 and 10 ) of each second memory device of  FIGS. 8 ,  9 , and  10 . The status registry operation  210  first fetches a command from a command register in step  212  and sets the status registry to “busy” in step  214 . A check is conducted at step  216  to ensure a memory command is being requested. A bifurcation of the status registry operation  210  occurs at step  218  when the command is classified as a read or a write. For a memory read, the memory address is read at step  220 , the data located at the address is read and written to a buffer at step  222 , an error correction code (ECC) check and correction is performed at step  224 , and the data is transferred to the command host at step  226 . In contrast, a write command will have the memory address read at step  228  and the command data written to the address in step  230 . 
     At the conclusion of either the write or read command, any errors are written to the status register in step  232 . At step  234 , a “not busy” status is written to the status register once the command and error functions are completed. A “not busy” status is also written to the status register if a command received is not a memory command from step  216 . Finally, the status registry operation  210  is cycled at the completion of step  234  with the fetching of a new command. 
     Other advantages of the various embodiments presented herein will readily occur to the skilled artisan in view of the present disclosure. For example a variety of configurations of memory can be constructed and controlled to efficiently and accurately manage data. Moreover, computer memory devices can optimize performance by using voltage reference values. The voltage reference values can be assigned to groups of cells in any convenient manner, whether at the array level, individual block level, at the sector level, at the word line level, etc. It will further be appreciated that groups of cells for a given reference value can be physically discontinuous and hence non-adjacent to one another. These and other considerations can be readily implemented depending on the requirements of a given application. 
     It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.