Abstract:
A read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read includes a differential pair circuit, an input voltage offset compensation circuit, and an input current offset compensation circuit. The differential pair circuit is ac coupled to first and second input signal nodes and includes first and second transistors, first and second load resistors, and a current generator. The input voltage offset compensation circuit is coupled to the differential pair circuit and includes a switch network and a Gm stage. The input current offset compensation circuit is coupled to the differential pair circuit and includes an integrator circuit and first and second biasing resistors.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to a read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read. In particular, the present invention relates to a read/write system with reduced write-to-read transition recovery time and increased input impedance.  
           [0002]    A popular method of magnetic data storage utilizes magnetoresistive (MR) heads to store and recover data on a magnetic data storage medium such as a magnetic disk. An MR head employs an MR element that changes in resistivity with changing magnetic flux from data patterns on an adjacent magnetic disk surface. A bias current having a constant value is passed through the MR element, and the change in resistivity is measured by sensing the change in voltage across the MR head.  
           [0003]    Amplifier circuits that sense signals from MR heads commonly include differential inputs and differential outputs. While there are a wide variety of differential amplifier circuit topologies, most include an input stage with a current source, two load resistors, and symmetrical transistors for splitting the current between the load resistors. Usually, the output voltage is taken as the difference in the voltage drops across the load resistors; in this manner, large variations in output voltages may be achieved with extremely small input voltage differentials. Additionally, differential amplifier circuits commonly include an input stage that is capacitively (or ac) coupled to the MR head; in this manner, only changes in input voltage are sensed by the differential amplifier circuit, while dc voltages are ignored.  
           [0004]    For all differential amplifier read/write circuits there are associated therewith certain transition recovery time performance characteristics. These characteristics and others determine the usefulness of the read/write circuit in any given application. The write-to-read transition recovery time is the duration of time required for a differential amplifier read/write circuit to switch from write mode to read mode and reach steady state. For differential amplifier read/write circuits that are capacitively coupled to the MR head, the write-to-read transition recovery time is increased due to charging and discharging of the input capacitors. This is caused by the presence of input voltage and input current offset.  
           [0005]    Theoretically, if the transistors, as well as the load resistors, in a differential amplifier circuit were perfectly matched and the voltage across the differential inputs was zero, then current would split equally between the transistors and the output voltage would also be zero. Practical circuits, however, exhibit mismatches that result in a nonzero dc output voltage even when the voltage across the inputs is zero. As a result, in order to reduce the output voltage to zero, an input voltage offset must be present between the inputs of the differential amplifier circuit. In addition, in a perfectly matched differential amplifier circuit, the differential inputs carry equal dc currents, otherwise known as input bias currents. Practical circuits, however, exhibit mismatches, particularly in the P of the transistors, that make the input dc currents unequal. The resulting difference is the input current offset.  
           [0006]    One well-known modification to the differential amplifier read/write circuit is the addition of a Gm stage, or transconductance amplifier, that is coupled to the transistors of the input stage. The Gm stage provides negative shunt feedback which causes a shunting of the noise resistances of the input transistors and suppresses disturbances caused by the input voltage offset during the transition from write mode to read mode. However, the main disadvantage of this type of circuit is that the negative shunt feedback only compensates the input voltage offset and not the input current offset. Furthermore, because the Gm stage provides negative shunt feedback not only during the transition from write mode to read mode but at all times, the amount of feedback is a tradeoff between write-to-read transition recovery time and input impedance of the differential amplifier read/write circuit. An increase in the transconductance of the Gm stage suppresses disturbances caused by the input voltage offset more quickly and decreases the write-to-read transition recovery time. However, an increase in the transconductance of the Gm stage is equivalent to a decrease in the resistance of the Gm stage. Because the resistance of the Gm stage is directly in parallel to the small-signal model resistances of the input transistors, the input impedance of the differential amplifier circuit decreases, which in turn requires a significant increase in the size of the input capacitors.  
           [0007]    Accordingly, there is a need for a read/write system that compensates both input voltage offset and input current offset to reduce write-to-read transition recovery time, while increasing input impedance to reduce the size of the input capacitors.  
         BRIEF SUMMARY OF THE INVENTION  
         [0008]    The present invention is a read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read. A differential pair circuit is ac coupled to first and second input signal nodes and includes first and second transistors, first and second load resistors, and a current generator. An input voltage offset compensation circuit is coupled to the differential pair circuit and includes a switch network and a Gm stage. An input current offset compensation circuit is coupled to the differential pair circuit and includes an integrator circuit and first and second biasing resistors. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 shows a circuit schematic diagram of a first embodiment of the present invention.  
         [0010]    [0010]FIG. 2 shows a circuit schematic diagram of a second embodiment of the present invention.  
         [0011]    [0011]FIG. 3 shows a timing diagram of the second embodiment of the present invention.  
         [0012]    [0012]FIG. 4 shows a circuit schematic diagram of a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0013]    [0013]FIG. 1 is a circuit diagram of a first embodiment of a read/write system  10  of the present invention. Read/write system  10  includes a differential pair circuit  12 , a switching circuit  14 , an input voltage offset compensation circuit  16 , an input current offset compensation circuit  18 , input signal nodes VMR 1  and VMR 2 , capacitors C 1  and C 2 , output signal nodes VO 1  and VO 2 , and fixed potentials VCC and GND.  
         [0014]    Differential pair circuit  12  includes transistors Q 1  and Q 2 , load resistors RL 1 -RL 4 , and current generator I 1 . Transistors Q 1  and Q 2  are npn bipolar junction transistors each having a base, a collector, and an emitter. Load resistors RL 1  and RL 3  are connected in series between fixed potential VCC and the collector of transistor Q 1 . Load resistors RL 2  and RL 4  are connected in series between fixed potential VCC and the collector of transistor Q 2 . The base of transistor Q 1  is connected to input signal node VMR 1  through capacitor C 1 . The base of transistor Q 2  is connected to input signal node VMR 2  through capacitor C 2 . The emitter of transistor Q 1  is connected to the emitter of transistor Q 2 . Current generator I 1  is connected between the emitter of transistor Q 1  and fixed potential GND. Output signal nodes VO 1  and VO 2  are connected respectively to load resistors RL 1  and RL 2 .  
         [0015]    Switching circuit  14  includes transistors M 1  and M 2 , and control signal node VSWITCH. Transistors M 1  and M 2  are NMOS transistors each having a gate, a source, a drain, and a substrate. Control signal node VSWITCH is connected to the gates of transistors M 1  and M 2 . The drain of transistor M 1  and the source of transistor M 2  are each connected to the base of transistor Q 1 . The source of transistor M 1  and the drain of transistor M 2  are each connected to the base of transistor Q 2 . The substrates of transistors M 1  and M 2  are each connected to fixed potential GND.  
         [0016]    Input voltage offset compensation circuit  16  includes transistors M 3 -M 8 , Gm stage G 1 , current generators I 2 -I 4 , and control signal nodes VREVERSE and VNREVERSE. Transistors M 3 -M 8  are NMOS transistors each having a gate, a source, a drain, and a substrate, wherein the substrate is connected to the source. Transistors M 3 -M 6 , along with control signal nodes VREVERSE and VNREVERSE, form a switch network for selectively switching the configuration of input voltage offset compensation circuit  16  between positive shunt feedback and negative shunt feedback. Transistors M 7  and M 8 , along with control signal nodes VNSWITCH and VSWITCH, control the biasing current to Gm stage G 1  by selectively switching between current generators  13  and  14 . Gm stage G 1  is a transconductance amplifier having first and second input nodes, first and second output nodes, and first and second biasing current nodes. Gm stage G 1  not only provides resistances between its input nodes and output nodes, but it also provides a differential current at its output nodes that is proportional to the differential voltage at its input nodes. Control signal node VREVERSE is connected to the gates of transistors M 3  and M 5 . Control signal node VNREVERSE is connected to the gates of transistors M 4  and M 6 . Control signal node VNSWITCH is connected to the gate of transistor M 7 , and control signal node VSWITCH is connected to the gate of transistor M 8 . The drain of transistor M 3  and the source of transistor M 4  are each connected to the collector of transistor Q 1 . The drain of transistor M 5  and the source of transistor M 6  are each connected to the collector of transistor Q 2 . The source of transistor M 3  and the drain of transistor M 6  are each connected to the first input node of Gm stage G 1 . The drain of transistor M 4  and the source of transistor M 5  are each connected to the second input node of Gm stage G 1 . The first output node of Gm stage G 1  is connected to the base of transistor Q 1 , and the second output node of Gm stage G 1  is connected to the base of transistor Q 2 . Current generator  12  is connected between the first biasing current node of Gm stage G 1  and fixed potential GND. The drain of transistor M 7  and the source of transistor M 8  are each connected to the second biasing current node of Gm stage G 1 . Current generator I 4  provides a significantly greater current than current generator I 3 , and is connected between the source of transistor M 8  and fixed potential GND. Current generator  13  is connected between the drain of transistor M 7  and fixed potential GND.  
         [0017]    Input current offset compensation circuit  18  includes Gm stage G 2 , current generator  15 , operational amplifier A 1 , capacitors C 3  and C 4 , biasing resistors RB 1  and RB 2 , and reference voltage VREF. Gm stage G 2  is a transconductance amplifier having first and second input nodes, first and second output nodes, and first and second biasing current nodes. Operational amplifier A 1  has first and second input nodes, and an output node. The first and second input nodes of Gm stage G 2  are connected respectively to load resistors RL 2  and RL 1 . The first and second output nodes of Gm stage G 2  are connected respectively to the first and second input nodes of operational amplifier A 1 . The first biasing current node of Gm stage G 2  is connected to fixed potential VCC. Current generator  15  is connected between the second biasing current node of Gm stage G 2  and fixed potential GND. Capacitor C 3  is connected between the first input node of operational amplifier A 1  and fixed potential GND. Capacitor C 4  is connected between the second input node and the output node of operational amplifier A 1 . The output node of operational amplifier A 1  is connected to the base of transistor Q 2  through biasing resistor RB 2 . Reference voltage VREF is connected to the base of transistor Q 1  through biasing resistor RB 1 .  
         [0018]    In operation, the voltage across an MR head is the signal that is retrieved from a data pattern on an adjacent magnetic disk surface. This voltage across the MR head is represented in FIG. 1 at input signal nodes VMR 1  and VMR 2 . During read mode when the voltage at control signal node VSWITCH is low, the voltage difference between input signal nodes VMR 1  and VMR 2  is the input signal that is sensed by read/write system  10 . Variations in the voltage difference between input signal nodes VMR 1  and VMR 2  lead to variations in the currents through transistors Q 1  and Q 2 . These variations in currents lead to voltage variations across load resistors RL 1 -RL 4 , which in turn lead to variations in the voltage difference between output signal nodes VO 1  and VO 2 .  
         [0019]    Input voltage offset compensation circuit  16  is operable to reduce write-to-read transition recovery time by compensating for input voltage offset in the time period immediately following a write-to-read transition. This compensation is performed by connecting the read/write system in a negative shunt feedback configuration in the time period following the write-to-read transition to suppress disturbances caused by input voltage offset, while connecting the read/write system in a positive shunt feedback configuration at all other times so that the system has a desirable high input impedance. Input current offset compensation circuit  18  is operable to reduce write-to-read transition recovery time by compensating for input current offset in the currents conducted through differential pair circuit  12 . This compensation is performed by providing a negative dc feedback configuration utilizing an integrator to equalize the voltages at output signal nodes VO 1  and VO 2  of the read/write system.  
         [0020]    Although input voltage offset compensation circuit  16  and input current offset compensation circuit  18  operate simultaneously within read/write system  10 , each circuit operates independently from the other circuit, and each circuit can exist alone in a separate read/write system. Therefore, to more easily explain the operation of each circuit, input voltage offset compensation circuit  16  is isolated in a read/write system shown in FIG. 2, and input current offset compensation circuit  18  is isolated in a read/write system shown in FIG. 4.  
         [0021]    [0021]FIG. 2 is a circuit diagram of an input voltage offset compensation portion of read/write system  20  of the present invention. Read/write system  20  includes a differential pair circuit  12 , a switching circuit  14 , an input voltage offset compensation circuit  16 , input signal nodes VMR 1  and VMR 2 , capacitors C 1  and C 2 , output signal nodes VO 1  and VO 2 , and fixed potentials VCC and GND.  
         [0022]    When the voltage at control signal node VSWITCH is low, transistors M 1  and M 2  are turned off and read/write system  20  is in read mode. During the steady state in read mode, the voltage at control signal node VNREVERSE is high and the voltage at control signal node VREVERSE is low, causing transistors M 4  and M 6  to be turned on, and transistors M 3  and M 5  to be turned off. As a result, the collector of transistor Q 1  is connected to the second input node of Gm stage G 1  through active transistor M 4  and the collector of transistor Q 2  is connected to the first input node of Gm stage G 1  through active transistor M 6 . Since the voltage at control signal node VSWITCH is low and the voltage at control signal node VNSWITCH (which is the inverse of VSWITCH) is high, transistor M 7  is turned on and transistor M 8  is turned off, so that the second biasing current node of Gm stage G 1  is connected to current generator  13  through active transistor M 7 . In this configuration, input voltage offset compensation circuit  16  provides positive shunt feedback; resistances are provided by Gm stage G 1  between the collector of transistor Q 1  and the base of transistor Q 2 , and between the collector of transistor Q 2  and the base of transistor Q 1 . These resistances are large because the small biasing current provided by current generator  13  causes the transconductance of Gm stage G 1  to be low (transconductance is inversely proportional to resistance). The large resistances in this positive shunt feedback configuration provided by Gm stage G 1 , combined with the fact that these large resistances are not directly in parallel with the small-signal model resistances of transistors Q 1  and Q 2 , increase the input impedance of differential pair circuit  12 , and allows the size of capacitors C 1  and C 2  to be significantly reduced.  
         [0023]    When the voltage at control signal node VSWITCH is changed to high, read/write system  20  is in write mode and transistors M 1  and M 2  are turned on. As a result, the bases of transistors Q 1  and Q 2  are connected to each other through active transistors M 1  and M 2 . Because the bases of transistors Q 1  and Q 2  are shorted, differential pair circuit  12  is not affected by the noise pulses that are induced from input signal nodes VMR 1  and VMR 2  during write mode. The voltages at control signal nodes VNREVERSE and VREVERSE are unchanged during write mode, and remain high and low respectively. Since the voltage at control signal node VSWITCH is high and the voltage at control signal node VNSWITCH is low, transistor M 8  is turned on and transistor M 7  is turned off, so that the second biasing current node of Gm stage G 1  is connected to current generator  14  through active transistor M 7 . As a result, the biasing current through Gm stage G 1  gradually increases (due to the capacitance associated with Gm stage G 1 ) until the biasing current through Gm stage G 1  reaches the same level as the current supplied by current generator  14 . The resistance of Gm stage G 1  decreases in a corresponding manner, since resistance is inversely proportional to biasing current and transconductance.  
         [0024]    When the voltage at control signal node VSWITCH is again changed to low, transistors M 1  and M 2  are turned off and read/write system  20  is in read mode. At the same time the voltage at control signal node VSWITCH is changed to low, the voltage at control signal node VREVERSE is temporarily changed to high and the voltage at control signal node VNREVERSE is temporarily changed to low, causing transistors M 3  and M 5  to be turned on, and transistors M 4  and M 6  to be turned off. As a result, the collector of transistor Q 1  is connected to the first input node of Gm stage G 1  through active transistor M 3  and the collector of transistor Q 2  is connected to the second input node of Gm stage G 1  through active transistor M 5 . Since the voltage at control signal node VNSWITCH is high and the voltage at control signal node VSWITCH is low, transistor M 7  is turned on and transistor M 8  is turned off, so that the second biasing current node of Gm stage G 1  is connected to current generator I 3  through active transistor M 7 . In this configuration, input voltage offset compensation circuit  16  provides negative shunt feedback for the temporary time period while the voltage at control signal node VREVERSE is high; resistances are provided by Gm stage G 1  between the collector and base of transistor Q 1 , and between the collector and base of transistor Q 2 . The current through Gm stage G 1  gradually decays from the higher current value supplied by current generator I 4  to the lower current value supplied by current generator I 3 , which causes the transconductance of Gm stage G 1  to gradually decrease and the resistance of Gm stage G 1  to gradually increase (transconductance is inversely proportional to resistance). Although the resistance of Gm stage G 1  gradually increases from a low value to a steady state high value, the resistance of Gm stage G 1  is generally lower during the temporary time period while the voltage at control signal node VREVERSE is high (negative feedback) than during the remaining time periods when the voltage at control signal node VREVERSE is low. This negative shunt feedback provided by Gm stage G 1  provides small resistances directly in parallel to the small-signal model resistances of transistors Q 1  and Q 2 , which suppresses the disturbances caused by the input voltage offset and the noise from input signal nodes VMR 1  and VMR 2 . In addition, because Gm stage G 1  is a transconductance amplifier, it equalizes the variations in voltage at the collectors of transistors Q 1  and Q 2  (or respectively the first and second input nodes of Gm stage G 1 ) with changes in current at the bases of transistors Q 1  and Q 2  (or respectively the first and second output nodes of Gm stage G 1 ). Then after approximately 25 ns when the steady state is reached, the voltage at control signal node VNREVERSE is changed back to high and the voltage at control signal node VREVERSE is changed back to low, causing transistors M 4  and M 6  to be turned on, and transistors M 3  and M 5  to be turned off. As a result, input voltage offset compensation circuit  16  again provides positive shunt feedback. Because the resistances provided by Gm stage G 1  have gradually become large at this time, and not connected directly in parallel with the small-signal resistances of transistors Q 1  and Q 2 , the input impedance of differential pair circuit  12  is again significantly increased.  
         [0025]    Therefore, the input voltage offset compensation portion of the present invention provides a read/write system that reduces write-to-read transition recovery time by compensating input voltage offset during the write-to-read transition time, while increasing the input impedance of the differential amplifier circuit for the remainder of the time.  
         [0026]    [0026]FIG. 3 is a timing diagram of the input voltage offset compensation portion of read/write system  20  of the present invention. Waveform  30  illustrates the voltage at control signal node VSWITCH. Waveform  32  illustrates the voltage at control signal node VREVERSE, which is the inverse of the voltage at control signal node VNREVERSE. Waveform  34  illustrates the voltage disturbances and noise pulses at input signal nodes VMR 1  and VMR 2 . Waveform  36  illustrates the biasing current supplied to Gm stage G 1 , with curves  37 A and  37 B specifically illustrating the gradual increase and decrease of the biasing current through Gm stage G 1  as a result of switching of the biasing current supplied to Gm stage G 1 . Waveform  38  illustrates the resistance of Gm stage G 1 .  
         [0027]    Waveform  30  shows that when the voltage at VSWITCH is high, read/write system  20  is in write mode. When the voltage at VSWITCH is low, read/write system  20  is in read mode.  
         [0028]    Waveform  32  shows that when read/write system  20  is in write mode, the voltage at VREVERSE is low and input voltage offset compensation circuit  26  provides positive shunt feedback. At the instant read/write system  20  switches to read mode, the voltage at VREVERSE is temporarily high and input voltage offset compensation circuit  26  provides negative shunt feedback. After approximately 25 ns-30 ns, the voltage at VREVERSE is changed back to low and input voltage offset compensation circuit  26  provides positive shunt feedback for the remainder of the read mode.  
         [0029]    Waveform  34  shows that when read/write system  20  is in write mode, input signal nodes VMR 1  and VMR 2  experience voltage disturbances and write channel noise. When read/write system  20  switches to read mode, input voltage offset compensation circuit  26  eliminates any voltage disturbances and noise pulses at input signal nodes VMR 1  and VMR 2 .  
         [0030]    Waveform  36  illustrates the relative levels of biasing currents provided to Gm stage G 1  by current generators  13  and  14 . A small biasing current is supplied to Gm stage G 1  by current generator  13  when VSWITCH is low and read/write system  20  is in read mode, and a large biasing current is supplied to Gm stage G 1  by current generator I 4 when VSWTICH is high and read/write system  20  is in write mode. Due to the capacitance associated with Gm stage G 1 , the biasing current through Gm stage G 1  gradually increases when the biasing current supplied to Gm stage G 1  switches from the low current value supplied by current generator I 3  to the high current value supplied by current generator I 4 , as illustrated by curve  37 A. For the same reason, the biasing current through Gm stage G 1  also gradually decays when the biasing current supplied to Gm stage G 1  switches from the high current value supplied by current generator  14  to the low current value supplied by current generator  13 , as illustrated by curve  37 B.  
         [0031]    Waveform  38  illustrates the resistance of Gm stage G 1 , which is generally inversely proportional to the biasing current through Gm stage G 1 . As a result, the resistance of Gm stage G 1  is generally higher during the steady state period of the read mode when VREVERSE is low and read/write system  20  is connected in a positive feedback configuration than in the period of the read mode when VREVERSE is high and read/write system  20  is connected in a negative feedback configuration.  
         [0032]    [0032]FIG. 4 is a circuit diagram of an input current offset compensation portion of read/write system  40  of the present invention. Read/write system  40  includes a differential pair circuit  12 , a switching circuit  14 , an input current offset compensation circuit  18 , input signal nodes VMR 1  and VMR 2 , capacitors C 1  and C 2 , output signal nodes VO 1  and VO 2 , and fixed potentials VCC and GND.  
         [0033]    In an initial situation with the voltage at control signal node VSWITCH low and read/write system  40  in read mode, before the voltage at control signal node VSWITCH begins switching between low and high voltages causing read/write system  40  to switch between read and write modes, the voltages at output signal nodes VO 1  and VO 2  are equalized by input current offset compensation circuit  18 . Load resistors RL 2  and RL 1  are connected respectively to the first and second input nodes of Gm stage G 2  (load resistors RL 3  and RL 4  separate the first and second input nodes of Gm stage G 2  from output signal nodes VO 1  and VO 2  to eliminate influence from input current offset compensation circuit  18  on output frequency response of differential pair circuit  12 ). Gm stage G 2  has a relatively long time constant of approximately 1 ms, and thus it responds only to signals having frequencies below approximately 1 kHz. As a result, Gm stage G 2  effectively provides a dc path through which dc current can flow. Operational amplifier A 1  and capacitors C 3  and C 4  form an integrator circuit where the voltage at the output node of operational amplifier A 1  is the integral of the differential voltage at the input nodes of operational amplifier A 1 . This output voltage is applied to biasing resistor RB 2 , while reference voltage VREF is applied to biasing resistor RB 1  to provide a common mode reference for differential pair transistors Q 1  and Q 2 . Therefore, if a differential voltage is detected between the first and second input nodes of Gm stage G 2 , the integral of the differential voltage is continually applied to the base of transistor Q 2  through resistor RB 2  until there is no longer a differential voltage between the first and second input nodes of Gm stage G 2 . In this manner, input current offset compensation circuit  18  provides negative dc feedback and eventually equalizes the voltages at output signal nodes VO 1  and VO 2 . Due to this feedback, input current offset is compensated for and does not impact write-to-read transition recovery time.  
         [0034]    When the voltage at control signal node VSWITCH is subsequently switched between low and high voltages causing read/write system  40  to switch between read and write modes, input current offset compensation circuit  18  continues to maintain the same negative dc feedback prior to the switching. This is because the voltage signals at input signal nodes VMR 1  and VMR 2  during read mode are approximately in the frequency range 1 MHz to 1 GHz, well above the 1 kHz frequency response of Gm stage G 2 . Therefore, the operation of differential pair circuit  12  is not interfered with; input current offset compensation circuit  18  only compensates the internal current offset of differential pair circuit  12 .  
         [0035]    Therefore, the input current offset compensation portion of the present invention provides a read/write system that reduces write-to-read transition recovery time by compensating input current offset.  
         [0036]    Thus, the present invention provides a read/write system that compensates both input voltage offset and input current offset to reduce write-to-read transition recovery time, while increasing input impedance to reduce the size of the input capacitors.  
         [0037]    Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.