Abstract:
An algorithm that includes delay elements is used for echo cancellation. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. This algorithm can be advantageously implemented in FPGAs. Echo in over a thousand channels can be cancelled using a FPGA and an external memory device.

Description:
FIELD OF THE INVENTION 
   The present invention relates to telephone communications, and more specifically to echo cancellation in telephone communication systems. 
   BACKGROUND OF THE INVENTION 
   Recently, there are major developments in telephone communications. One example is the tremendous growth in digital cellular telephones. Another example is the use of packet-based data networks, such as those conforming to the Internet Protocol (IP), to carry voice communications (as opposed to using circuit-switched networks). This new technology is called voice-over IP (VoIP). In these applications, voice signals are digitized and travel on digital communication channels. The digital data is processed using digital signal processors (DSPs) and/or field programmable gate arrays (FPGAs). One important task performed by the DSP/FPGA is the elimination of echo. 
   In telephony applications, “echo” is defined as the reflection of the caller&#39;s voice back to the caller through the phone lines. Echo cancellation is the elimination of echo in telephone communications. There are several causes of echo. One cause, called “line” echo, is created when an electrical signal encounters an impedance mismatch at one end of the line, such as that caused by a 2 to 4 wire hybrid in an analog phone system. The echo is exacerbated by distance and by certain kinds of network equipment. Echo delayed by 30 ms or more is generally noticeable to the user, and delays greater than 50 ms affect the quality of the conversation. 
   SUMMARY OF THE INVENTION 
   The present invention involves a method for canceling echo in a telephone communication system. A telephone transmits electrical signals to a central station and receives electrical signals from the central stations. The electrical signals are modulated by audio information. The transmitting signals are digitized to generate m+n digitized transmitting data that correspond to a first time period (n and m are predetermined integer numbers and m&gt;=n). The receiving signals are digitized to generate n digitized receiving data that correspond to a second time period. The second time period is shorter than the first time period and has ending time the same as the first time period. A set of n weights data are calculated using the first n digitized transmitting data and the n digitized receiving data. The echo can be cancelled from the receiving signals at a third time period using the set of n weights data. The third time period follows the second time period and has the same length as the second time period. 
   The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram showing a telephone communication system that can use the echo canceller of the present invention. 
       FIG. 2  is a schematic diagram showing a portion of the communication system of  FIG. 1 . 
       FIG. 3  is a schematic diagram showing one embodiment of an echo canceller of the present invention 
       FIG. 4  is a block diagram showing an implementation of the present invention using a FPGA. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention relates to a new method for echo cancellation. In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features have not been described in detail in order to avoid obscuring the present invention. 
     FIG. 1  is a schematic diagram showing a telephone communication system  100  that can use the echo cancellation apparatus of the present invention. It contains a network “cloud”  102  that provides long distance connection and switching between a plurality of central stations (such as stations  104 – 106 ). Each central station can serve hundreds or thousands of subscribers (such as subscribers  112 – 116 ). 
   A portion  130  of communication system  100  is shown in a schematic diagram of  FIG. 2 . It shows a telephone  132  that sends electrical signals to a central office (not shown) through a line  134  and receives electrical signals from the central office through a line  136 . The electrical signals are modulated by audio sources (such as the voice of a caller). Portion  130  also contains an echo canceller  138  that performs echo cancellation operations. Echo canceller  138  contains an adaptive filter  140  and a node  142  that performs subtraction. Adaptive filter  140  models the returning echo, and cancels it by subtracting it from the returned signal. 
   One way to implement echo canceller  138  is to use digital circuit. The transmitting analog signals (indicated in  FIG. 2  by the symbol X(t)) and returning analog signals (indicated in  FIG. 2  by the symbol d(t)) are sampled and converted to digital data. Adaptive filter  140  and node  142  are modeled using digital computational means (such as DSPs and FPGAs), and they process digital data representing signals X(t) and d(t). 
   In the prior art system, the computation is performed on a sample-by-sample basis in real time. One problem with the prior art method is that very large memory bandwidth is required to handle the computation. One aspect of the present invention is to introduce appropriate delays at appropriate points in the signal paths. This has the effect of reducing memory bandwidth. 
     FIG. 3  is a schematic diagram showing one embodiment of an echo canceller  160  of the present invention. Echo canceller  160  can be roughly divided into two portions: a portion, shown as a dashed block  161 , used to compute the characteristics of an adaptive filter and a portion, shown as a dashed block  162 , used to cancel echo. In  FIG. 3 , the symbol k is used to represent sample numbers. For convenience, sampling is performed periodically. Thus, the time to sample a signal is determined by the product of the symbol k and the sampling period. The sampled data representing signals X(t) and d(t) are presented by X(k) and d(k), respectively. The sampled data X(k) is delayed by a first interval (shown as block  164 ). This set of data is used to remove echo (as explained in more details later in connection with block  162 ). Another delay is introduced (shown as block  166 ). The twice-delayed data is used to compute a set of weights W(k), shown as block  168 , that represents the characteristics of the adaptive filter. The sampled data representing received signal, d(k) is delayed once (shown as block  170 ) in the computation of W(k). 
   In a preferred embodiment, the delay intervals in blocks  166  and  170  are the same. 
   The set of formulas for the computation of W(k+1)
 
 y ( k )= X ( k −( m+n )) W ( k );  (1)
 
 e ( k )= d ( k−n )− y ( k );  (2)
 
 W ( k+ 1)= W ( k )+2μ e ( k ) X ( k −( m+n ));  (3)
 
where:
         m represents the delay interval of block  164  (i.e., delay-1);   n represents the delay intervals of blocks  166  and  170  (i.e., delay-2 and delay-3); and   m&gt;=n.       

   In the above equations, the symbol μ is called the “convergence factor.” A large value for μ leads to faster convergence and a larger asymptotic convergence error. In the present invention, μ can be in the range of 2^(−9) to 2^(−11). In  FIG. 3 , dashed block  161  is used to show the components that are used in the computation. 
   After n values of W(k) have been computed, they are used to compute the error estimates y(k)′ for X(k). These estimates are used to remove echo based on the following set of formulas:
 
 y ( k )= X ( k−m )′ W ( k );  (4)
 
 e ( k )′= d ( k )− y ( k )′.  (5)
 
   In  FIG. 3 , dashed block  162  is used to show the components that are used in the computation. A dashed line  172  connects weights block  168  and the multiplier inside block  162 , indicating that n values of the weights W(k) are updated at a time and then used in equations (4) and (5). 
   An example is used to illustrate the operation of the above equations. Delay-1 is used to set the minimum path length, which is preferably set at 25 ms. For a sample rate of 8 K per second, delay-1 (i.e., m) is 200 samples. In the calculation of the present invention, delay-1 moves the window of operation. 
   In the preferred embodiment, the maximum value of n is selected to give a total delay of less than 25 ms. In this example, n is selected to be 128, which will lag the coefficient update by 16 ms. 
   The weights, W(k) are initially set to zero and remain zero until 328 samples of X(k) have been received. The estimates, y(k)′, are also set to zero until sample  328 . As a result, e(k)′ is equal to d(k) for the first 328 samples. 
   After 328 (i.e., 200+128) samples of X(k) and d(k) have been received, all the delay paths are full and hence processing can begin. The weights, W(k), can be calculated using equation (1)–(3) based on X(k) samples  1  to  128  and d(k) samples  201  to  328 . Equation (4) is used to estimate y(k)′ for samples  329  to  456  based on X(k) samples  129  to  256 . These estimates are then used to cancel the echo on d(k) sample  329  to  456  using equation (5). 
   The method of the present invention is especially useful when implemented using an FPGA. Because of the relatively limited memory size in current FPGAs, digitized data is preferably stored in a memory chip outside of the FPGAs. 
     FIG. 4  is a block diagram showing an implementation  200  of the present invention using an FPGA  202 . An external memory  204  (such as a double data rate dynamic random access memory) is connected to FPGA  202 . In a preferred embodiment, only one memory device is used, although the present invention is independent of the number of memory devices. FPGA  202  accepts digital data from a telephonic data source  206 . Source  206  accepts many voice channels (such as channels  208  and  209 ) and combined them into a sequence of data for processing by FPGA  202 . Each channel may be similar to the portion of the telephone communication system shown in  FIG. 2 . Implementation  200  also contains a configuration memory  212  that configures FPGA  202  to perform the algorithm stated in equations 1–5. 
   Assuming that the FPGA is used to process 1,000 voice channels each has 128 ms of path delay and 8,000 sampling per second, the memory bandwidth requirement can be as high as 24.6 G words/second for a 1,024 tap adaptive filter. The present invention allows 128 or more consecutive samples to be burst processed for the same channel. As a result, the memory bandwidth is greatly reduced. 
   In one embodiment, the maximum value of n is selected to give a total delay of less than 25 ms. This selection allows compliance with the ITU-T G.168 specification, which states that an echo length of less than 25 ms need not be cancelled. In most applications n=128 is selected. This will lag the coefficient update by 16 ms and mean that the minimum echo path is 16 ms. The memory bandwidth in the system can be reduced by a factor of approximately 100. 
   The memory size requirement is determined by the length of the adaptive filter (i.e. number of taps). This length is determined by the minimum to maximum echo path that is being cancelled. For an echo path of 25 ms to 150 ms a 1000 tap filter is required. Typically an echo path of 64 ms or 128 ms is chosen, giving filter lengths of 512 taps and 1024 taps respectively. 
   Memory storage is required for the Tap Coefficients, the transmitted voice data, the received voice data and the echo estimates. The storage (Mem — size) can be calculated by:
 
Mem —   size=channels *(taps+(taps+3 n )+2 n+ 2 n )=channels*(2*taps+7 *n ).
 
   Hence as n increases the storage per channel increases by 7n (words). 
   Assuming taps=512, n=128, channels=1000 and words are 16 bits, the memory size is given by:
 
Mem — size=1000*(2*512+7*128)*16=30,720,000 MBits of storage.
 
   The memory bandwidth (Mem — bw) is calculated by:
 
Mem — bw=channels*sample — rate*(2*(taps/n)+((taps/n)+3)+2+2=channels*sample — rate*( 3 *taps/ n+ 7).
 
   Assuming taps=512, n=128, channels=1000, sample — rate=8000 and memory is word wide, the memory bandwidth is:
 
Mem — bw=1000*8000*(3*512/128+7)=152,000,000 words per second.
 
   This is significantly less than the 24.6 G words/second bandwidth required by using prior art methods. 
   It can be seen from the above description that a novel routing method has been disclosed. Those having skill in the relevant arts of the invention will now perceive various modifications and additions which may be made as a result of the disclosure herein. Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is to be limited only by the appended claims and their equivalents.