Abstract:
Provided is a transmission gate capable of adapting to various input voltages to attain high S/N characteristics. The transmission gate includes: a PMOS transistor ( 11 ) which includes a drain to which an input voltage (Vin) is input, is turned ON when a voltage (Vin−Vs 1 ) is input to a gate thereof, and includes a source from which the input voltage (Vin) is output as an output voltage (Vout); and an NMOS transistor ( 12 ) which has a gate length, a gate width, a gate oxide thickness, and an absolute value of a threshold voltage which are the same as those of the PMOS transistor ( 11 ), includes a drain to which the input voltage (Vin) is input, is turned ON when a voltage (Vin+Vs 1 ) is input to a gate thereof, and includes a source from which the input voltage (Vin) is output as the output voltage (Vout).

Description:
RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2010-026931 filed on Feb. 9, 2010, the entire content of which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a transmission gate and a semiconductor device. 
     2. Description of the Related Art 
     A conventional transmission gate is described.  FIG. 8  is a circuit diagram illustrating the conventional transmission gate. 
     The transmission gate includes a PMOS transistor  91  and an NMOS transistor  92 . In those transistors, gates thereof are controlled by complementary signals, and thus the transistors are turned ON/OFF simultaneously. When a low level voltage is input to the gate of the PMOS transistor  91 , and a high level voltage is input to the gate of the NMOS transistor  92 , electrical continuity of the transmission gate is established. Then, the transmission gate outputs an input voltage Vin as an output voltage Vout. 
     Here, a gate-to-source capacitance of the PMOS transistor  91  is represented by Cgsp, a gate-to-source capacitance of the NMOS transistor  92  is represented by Cgsn, a parasitic capacitance at an output terminal is represented by Ch, a threshold voltage of the PMOS transistor  91  is represented by −Vtp, and a threshold voltage of the NMOS transistor  92  is represented by Vtn. Further, a voltage magnitude applied to the gate of the PMOS transistor  91  is represented by V5, and a voltage magnitude applied to the gate of the NMOS transistor  92  is represented by V4. When the transmission gate is set so as to satisfy the following Expression (11), influence of clock feedthrough is reduced. Therefore, it is possible to attain high S/N characteristics (for example, see JP 07-169292 A).
 
( V 5 −V out− Vtp )· Cgsp /( Cgsp+Ch )=( V 4 −V out− Vtn )· Cgsn /( Cgsn+Ch )  (11)
 
     However, in the related art, Expression (11) is satisfied based on the presupposition that the input voltage Vin is a constant voltage (for example, (VDD+VSS)/2) and does not fluctuate. In other words, when the input voltage Vin fluctuates and therefore the output voltage Vout fluctuates, Expression (11) is not satisfied. Therefore, the S/N characteristics are degraded due to the influence of clock feedthrough. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of the above-mentioned problem, and an object of the present invention is therefore to provide a trans-mission gate capable of adapting to various input voltages to attain high S/N characteristics. 
     In order to solve the above-mentioned problem, according to the present invention, there is provided a transmission gate including: a PMOS transistor which includes a drain to which an input voltage is input, is turned ON when a first voltage obtained by subtracting a predetermined voltage from the input voltage is input to a gate of the PMOS transistor, and includes a source from which the input voltage is output as an output voltage; and an NMOS transistor which has a gate length, a gate width, a gate oxide thickness, and an absolute value of a threshold voltage which are the same as a gate length, a gate width, a gate oxide thickness, and an absolute value of a threshold voltage of the PMOS transistor, respectively, includes a drain to which the input voltage is input, is turned ON when a second voltage obtained by adding the predetermined voltage to the input voltage is input to a gate of the NMOS transistor, and includes a source from which the input voltage is output as the output voltage. 
     In the transmission gate according to the present invention, MOS transistors constituting the transmission gate have gate voltages controlled by voltages based on the input voltage, and hence it is possible to reduce influence of clock feedthrough, and adapt to various input voltages to attain high S/N characteristics. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the accompanying drawings: 
         FIG. 1  is a circuit diagram illustrating a transmission gate according to an embodiment of the present invention; 
         FIG. 2  is a circuit diagram illustrating a first level shifter; 
         FIG. 3  is a circuit diagram illustrating a second level shifter; 
         FIG. 4  is a circuit diagram illustrating a gate voltage selection circuit; 
         FIG. 5  is a circuit diagram illustrating another gate voltage selection circuit; 
         FIG. 6  is a circuit diagram illustrating the gate voltage selection circuit; 
         FIG. 7  is a circuit diagram illustrating another example of the level shifter; and 
         FIG. 8  is a circuit diagram illustrating a conventional transmission gate. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Hereinafter, an embodiment of the present invention is described with reference to the accompanying drawings. 
     First, a configuration of a transmission gate is described.  FIG. 1  is a circuit diagram illustrating the transmission gate according to this embodiment. 
     A transmission gate  10  includes a PMOS transistor  11 , an NMOS transistor  12 , a first level shifter  13 , a second level shifter  14 , and a gate voltage selection circuit  15 . Further, the transmission gate  10  includes an input terminal IN, an output terminal OUT, and a control terminal CNT. 
     The gate voltage selection circuit  15  includes an input terminal IN 1  connected to an output terminal of the first level shifter  13 , a second input terminal IN 2  connected to an output terminal of the second level shifter  14 , a control terminal CNT connected to the control terminal CNT of the transmission gate  10 , a first output terminal OUT 1  connected to a gate of the PMOS transistor  11 , and a second output terminal OUT 2  connected to a gate of the NMOS transistor  12 . Sources of the PMOS transistor  11  and the NMOS transistor  12  are respectively connected to the output terminal OUT of the transmission gate  10 , and drains of the PMOS transistor  11  and the NMOS transistor  12  are respectively connected to the input terminal IN of the transmission gate  10 . Input terminals of the first level shifter  13  and the second level shifter  14  are respectively connected to the input terminal IN of the transmission gate  10 . 
     Next, a configuration of the first level shifter  13  is described.  FIG. 2  is a circuit diagram illustrating the first level shifter. 
     The first level shifter  13  includes a current source  21  and a PMOS transistor  22 . The PMOS transistor  22  includes a gate connected to the input terminal of the first level shifter  13 , a source connected to the output terminal of the first level shifter  13 , and a drain connected to a ground terminal. The current source  21  is provided between a power supply terminal and the output terminal of the first level shifter  13 . 
     Next, a configuration of the second level shifter  14  is described.  FIG. 3  is a circuit diagram illustrating the second level shifter. 
     The second level shifter  14  includes a current source  31  and an NMOS transistor  32 . The NMOS transistor  32  includes a gate connected to the input terminal of the second level shifter  14 , a source connected to the output terminal of the second level shifter  14 , and a drain connected to the power supply terminal. The current source  31  is provided between the output terminal of the second level shifter  14  and the ground terminal. 
     Next, a configuration of the gate voltage selection circuit  15  is described.  FIG. 4  is a circuit diagram illustrating the gate voltage selection circuit. 
     The gate voltage selection circuit  15  includes switches  41  to  44  and an inverter  45 . Further, the gate voltage selection circuit  15  includes the first input terminal IN 1 , the second input terminal IN 2 , the control terminal CNT, the first output terminal OUT 1 , and the second output terminal OUT 2 . 
     The switch  41  is provided between the first input terminal IN 1  and the first output terminal OUT 1  of the gate voltage selection circuit  15 , and is controlled by a voltage /Vc. The switch  42  is provided between the second input terminal IN 2  and the first output terminal OUT 1  of the gate voltage selection circuit  15 , and is controlled by a voltage Vc. The switch  43  is provided between the first input terminal IN 1  and the second output terminal OUT 2  of the gate voltage selection circuit  15 , and is controlled by the voltage Vc. The switch  44  is provided between the second input terminal IN 2  and the second output terminal OUT 2  of the gate voltage selection circuit  15 , and is controlled by the voltage /Vc. An input terminal of the inverter  45  is connected to the control terminal CNT of the gate voltage selection circuit  15 . The inverter  45  receives the voltage Vc, and outputs the voltage /Vc. The switches  41  to  44  are constituted by, for example, MOS transistors  61  to  64  as illustrated in  FIG. 6 . 
     Next, an operation of the transmission gate  10  is described. 
     An input voltage Vin of the input terminal IN is input to the input terminal of the first level shifter  13  and the input terminal of the second level shifter  14 . 
     The first level shifter  13  is a source follower, and hence a source voltage of the PMOS transistor  22  becomes a voltage (Vin+Vs 1 ). The voltage Vs 1  is a total voltage of an absolute value of a threshold voltage (−Vtp) of the PMOS transistor  22  and an overdrive voltage Vo 1 . The first level shifter  13  outputs the voltage (Vin+Vs 1 ) from the output terminal thereof. 
     The second level shifter  14  is a source follower, and hence a source voltage of the NMOS transistor  32  becomes a voltage (Vin−Vs 2 ). The voltage Vs 2  is a total voltage of a threshold voltage Vtn of the NMOS transistor  32  and an overdrive voltage Vo 2 . The second level shifter  14  outputs the voltage (Vin−Vs 2 ) from the output terminal thereof. 
     The first level shifter  13  and the second level shifter  14  are designed to satisfy Expressions (1) to (3).
 
 Vtp=Vtn   (1)
 
 Vo 1 =Vo 2  (2)
 
 Vs 1 =Vtp+Vo 1 =Vs 2 =Vtn+Vo 2  (3)
 
     Here, when the voltage Vc input to the control terminal CNT is a high level voltage, the voltage /Vc is a low level voltage. Then, the switch  42  and the switch  43  are turned ON, and the switch  41  and the switch  44  are turned OFF. Therefore, the gate voltage selection circuit  15  outputs the voltage (Vin−Vs 2 ) of the second input terminal IN 2 , that is, the voltage (Vin−Vs 1 ) from the first output terminal OUT 1 . Further, the gate voltage selection circuit  15  outputs the voltage (Vin+Vs 1 ) of the first input terminal IN 1  from the second output terminal OUT 2 . 
     Therefore, a gate voltage of the PMOS transistor  11  becomes the voltage (Vin−Vs 1 ), and a gate-to-source voltage Vgsp of the PMOS transistor  11  is expressed by the following Expression (4).
 
 Vgsp=−Vs 1=−( Vtp+Vo 1)  (4)
 
The gate-to-source voltage Vgsp of the PMOS transistor  11  becomes lower than the threshold voltage (−Vtp) thereof, and hence the PMOS transistor  11  is turned ON.
 
     Further, a gate voltage of the NMOS transistor  12  becomes the voltage (Vin+Vs 1 ), and a gate-to-source voltage Vgsn of the NMOS transistor  12  is expressed by the following Expression (5).
 
 Vgsn=Vs 2 =Vtn+Vo 2 =Vs 1 =Vtp+Vo 1  (5)
 
The gate-to-source voltage Vgsn of the NMOS transistor  12  becomes higher than the threshold voltage Vtn thereof, and hence the NMOS transistor  12  is turned ON.
 
     Therefore, electrical continuity of the transmission gate  10  is established, and the input voltage Vin is output to the output terminal OUT as an output voltage Vout. 
     Next, when the voltage Vc input to the control terminal CNT is a low level voltage, the voltage /Vc is a high level voltage. Then, the switch  42  and the switch  43  are turned OFF, and the switch  41  and the switch  44  are turned ON. Therefore, the gate voltage selection circuit  15  outputs the voltage (Vin+Vs 1 ) of the first input terminal IN 1  from the first output terminal OUT 1 . Further, the gate voltage selection circuit  15  outputs the voltage (Vin−Vs 2 ) of the second input terminal IN 2 , that is, the voltage (Vin−Vs 1 ) from the second output terminal OUT 2 . 
     Therefore, the gate voltage of the PMOS transistor  11  becomes the voltage (Vin+Vs 1 ), and the gate-to-source voltage Vgsp of the PMOS transistor  11  is expressed by the following Expression (6).
 
 Vgsp=Vs 1 =Vtp+Vo 1  (6)
 
The gate-to-source voltage Vgsp of the PMOS transistor  11  becomes higher than the threshold voltage (−Vtp) thereof, and hence the PMOS transistor  11  is turned OFF.
 
     Further, the gate voltage of the NMOS transistor  12  becomes the voltage (Vin−Vs 1 ), and the gate-to-source voltage Vgsn of the NMOS transistor  12  is expressed by the following Expression (7).
 
 Vgsn=−Vs 2=−( Vtn+Vo 2)=− Vs 1=−( Vtp+Vo 1)  (7)
 
The gate-to-source voltage Vgsn of the NMOS transistor  12  becomes lower than the threshold voltage Vtn thereof, and hence the NMOS transistor  12  is turned OFF.
 
     Therefore, electrical continuity of the transmission gate  10  is broken, and the input voltage Vin is not output to the output terminal OUT as the output voltage Vout. 
     Here, in the transmission gate  10 , the gate length, the gate width, and the gate oxide thickness of the PMOS transistor  11  are set equal to the gate length, the gate width, and the gate oxide thickness of the NMOS transistor  12 , respectively. Then, a gate-to-source capacitance Cgsp of the PMOS transistor  11  and a gate-to-source capacitance Cgsn of the NMOS transistor  12  become equal to each other. Further, from Expression (1), the threshold voltage Vtp of the PMOS transistor  11  and the threshold voltage Vtn of the NMOS transistor  12  are equal to each other. Further, when the voltage Vc is a high level voltage, from Expressions (4) and (5), the absolute value of the gate-to-source voltage Vgsp of the PMOS transistor  11  and the gate-to-source voltage Vgsn of the NMOS transistor  12  are equal to each other.
         In the transmission gate  10  configured as described above, Expression (8), which is based on Expression (11) described in the related art, is satisfied, and hence the influence of clock feedthrough is reduced, and high S/N characteristics are attained.
 
(| Vgsp|−|Vtp |)· Cgsp /( Cgsp+Ch )=( Vgsn−Vtn )· Cgsn /( Cgsn+Ch )  (8)
 
Cgsp represents the gate-to-source capacitance of the PMOS transistor  11 , Cgsn represents the gate-to-source capacitance of the NMOS transistor  12 , and Ch represents a parasitic capacitance at the output terminal.
       

     Further, with reference to Expression (2), Expressions (4) and (5), and Expression (8), the following Expression (9) is satisfied.
 
 Cgsp /( Cgsp+Ch )= Cgsn /( Cgsn+Ch )  (9)
 
This Expression (9) does not depend on the input voltage Vin. That is, in the transmission gate  10 , the influence of clock feedthrough is reduced and the high S/N characteristics are attained irrespective of the voltage value of the input voltage Vin.
 
     When configured as described above, the MOS transistors constituting the transmission gate  10  have gate voltages which are based on the input voltage Vin, and hence even when the input voltage Vin fluctuates, the influence of clock feedthrough may be reduced and the high S/N characteristics may be attained. 
     Note that, the gate voltage selection circuit  15  is not limited to the circuit illustrated in  FIG. 4 , and for example, may be a circuit configured as illustrated in  FIG. 5 . 
     The gate voltage selection circuit illustrated in  FIG. 5  includes PMOS transistors  51  and  52  and NMOS transistors  53  and  54 . Further, the gate voltage selection circuit includes the first input terminal IN 1 , the second input terminal IN 2 , the control terminal CNT, the first output terminal OUT 1 , and the second output terminal OUT 2 . 
     The PMOS transistor  51  and the NMOS transistor  53  constitute a first inverter having the voltage (Vin+Vs 1 ) as a power supply voltage and the voltage (Vin−Vs 2 ) as a ground voltage. The PMOS transistor  52  and the NMOS transistor  54  constitute a second inverter having the voltage (Vin+Vs 1 ) as the power supply voltage and the voltage (Vin−Vs 2 ) as the ground voltage. The second inverter is provided in the later stage of the first inverter. The first inverter includes an input terminal connected to the control terminal CNT of the gate voltage selection circuit  15 , and an output terminal connected to the first output terminal OUT 1  of the gate voltage selection circuit  15 . The second inverter includes an input terminal connected to the first output terminal OUT 1  of the gate voltage selection circuit  15 , and an output terminal connected to the second output terminal OUT 2  of the gate voltage selection circuit  15 . 
     In addition, although not illustrated, the current source  21  and the current source  31 , which are used in the first level shifter  13  and the second level shifter  14 , respectively, may be replaced by resistors. 
     Further, the first level shifter  13  and the second level shifter  14  are exemplified as circuits illustrated in  FIG. 2  and  FIG. 3 , respectively. However, the first level shifter  13  and the second level shifter  14  may be any circuits which receive the input voltage Vin and output the output voltage Vin±Vs 1 . For example, the first level shifter  13  and the second level shifter  14  may be constituted by a buffer amplifier as illustrated in  FIG. 7 .