Abstract:
A radio frequency (RF) power generator includes a first switch-mode amplifier that generates a first RF signal in accordance with a first control signal and a second switch-mode amplifier that generates a second RF signal in accordance with a second control signal. The first and second control signals determine a phase difference between the first and second RF signals. An output signal envelope is based on the first and second RF signals and the phase difference. The first control and second control signals alternate phases of the first and second RF signals.

Description:
FIELD 
       [0001]    The present disclosure relates to modulating envelope power in radio frequency (RF) signal generators. 
       BACKGROUND 
       [0002]    The statements in this section merely provide background information related to the present disclosure and may not constitute prior art. 
         [0003]    Radio frequency power can be expressed in the time domain as a periodic signal that has particular peak-to-peak (P-P) amplitudes at corresponding times. The P-P amplitudes describe the envelope of the RF power. Amplitude modulation (AM) is an example of a RF mode that modulates the RF envelope. 
         [0004]    RF power can be used to generate plasma that can be used to fabricate semiconductors by using methods that are known in the art. In such applications it is increasingly important to precisely control the RF envelope as the size of semiconductor features decreases and/or as demands on production yield increase. Several methods are known in the art for controlling the RF envelope and are described below. 
         [0005]    A first group of methods provide RF on-off envelope pulsing by switching a RF power amplifier driver on and off and/or using on-off control circuits of a power supply that feeds the RF power amplifier to pulse a DC input rail voltage to the power amplifier. 
         [0006]    A second group of methods provide RF envelope pulsing by controlling the amplitude of the RF power amplifier driver. These methods are typically applicable to power amplifiers with Class A, AB, B and C circuit topologies and/or controlling the output voltage of a power supply that feeds the RF power amplifier to modulate the DC input rail voltage to the power amplifier. 
         [0007]    A third method is disclosed in U.S. Pat. No. 7,259,622, which provides a phase-controlled RF power amplifier design with a full-bridge topology to facilitate flexible RF envelope waveform generation. The bridge topology requires four power switches and a complex gate drive control scheme. Those design features increase parts count and cost and reduces reliability. 
         [0008]    The above methods also have some inherent operating limitations. In the methods that use the power supply control for RF envelope pulsing (on-off or multi-amplitude-level), the pulse rise and fall speeds are limited by the dynamic response of the DC rail voltage. RF pulse envelopes with fast rise and fall times, high pulsing frequencies, or pulses with small duty cycles are therefore not easily achievable. The above methods that use RF power amplifier drive on-off control will only facilitate RF envelope on-off pulsing. They are unable to provide an RF of varying non-zero amplitudes. The above methods that use the RF power amplifier drive control for RF multi-amplitude-level envelope pulsing are limited to linear power amplifiers (such as with Class A, AB, B &amp; C topologies), and not easily extendable to high efficiency switch-mode power amplifiers (such as with Class E topology). Linear power amplifiers also require designs and constructions with large power handling and thermal capacities to dissipate heat because large differential powers need to be dissipated from the power amplifier transistor devices during pulsing. 
         [0009]    With a combination of power supply control and RF power amplifier drive control, some limitations listed above can possibly be reduced. However, such reductions would be limited and require complex control circuits for RF envelope pulsing, as both the power supply control and the power amplifier drive control would need to be well coordinated while pulsing. 
       SUMMARY 
       [0010]    A radio frequency (RF) power generator includes a first switch-mode amplifier that generates a first RF signal in accordance with a first control signal and a second switch-mode amplifier that generates a second RF signal in accordance with a second control signal. The first and second control signals determine a phase difference between the first and second RF signals. An output signal envelope is based on the first and second RF signals and the phase difference. 
         [0011]    A method of operating a radio frequency (RF) power generator includes generating a first RF signal that includes a first phase in accordance with a first control signal, generating a second RF signal that includes a second phase in accordance with a second control signal, applying the first and second RF signals across a load, and varying the first and second control signals to control an RF envelope that is applied to the load via the first and second RF signals. 
         [0012]    A radio frequency (RF) power generator includes a first Class E amplifier that generates a first RF signal in accordance with a first control signal and a second Class E amplifier that generates a second RF signal in accordance with a second control signal. The first and second control signals alternate phases of the first and second RF signals while holding a constant phase difference between the first and RF signals during each phase alternation. An output signal envelope is based on the first and second RF signals and the phase difference. 
         [0013]    Further areas of applicability will become apparent from the description provided herein. It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. 
     
    
     
       DRAWINGS 
         [0014]    The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. 
           [0015]      FIG. 1  depicts a schematic diagram of a phase-switching switch-mode radio frequency (RF) power amplifier; 
           [0016]      FIG. 2  depicts waveforms of a switching device in the RF amplifier of  FIG. 1 ; 
           [0017]      FIG. 3A  is graph of an output power profile of the RF power amplifier of  FIG. 1 ; 
           [0018]      FIG. 3B  is a graph of DC input power of the RF power amplifier of  FIG. 1 ; 
           [0019]      FIG. 3C  is a graph of voltage across the switching device in the RF amplifier of  FIG. 1   
           [0020]      FIG. 3D  is a graph of current through the switching device in the RF amplifier of  FIG. 1 ; 
           [0021]      FIG. 4  depicts waveforms of phase control signals for RF envelope on/off pulsing and the corresponding RF output waveform; 
           [0022]      FIG. 5  depicts waveforms of phase control signals for RF envelope non-zero two-level pulsing and the corresponding RF output waveform; 
           [0023]      FIG. 6  depicts waveforms of phase control signals for RF envelope slow rise and fall time pulsing and the corresponding RF output waveform; 
           [0024]      FIG. 7  is an oscilloscope trace of RF envelope pulsing using an embodiment of the RF amplifier of  FIG. 1 ; 
           [0025]      FIG. 8  is an oscilloscope trace of RF non-zero two-level pulsing using an embodiment of the RF amplifier of  FIG. 1 ; and 
           [0026]      FIGS. 9A-9K  depict simulated waveforms of voltage and current of various components of the RF power amplifier of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure. 
         [0028]    As used herein, the term module refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. 
         [0029]    Referring now to  FIG. 1 , a schematic diagram is shown of a novel RF amplifier  10 . RF amplifier  10  employs a master switch-mode amplifier  12   a  and slave switch-mode amplifier  12   b,  which are collectively referred to as switch-mode amplifiers  12 . Switch-mode amplifiers  12  include respective switching transistors Q 1  and Q 2 . Transistors Q 1  and Q 2  receive respective switch control signals  14   a,    14   b  that establish a phase difference between RF output signals at amplifier outputs  16   a,    16   b.  The RF output signals are summed and applied to a load  20 . Load  20  can include a plasma chamber with any associated impedance match, voltage and/or current probes, power meters, and the like. A DC power supply  22  provides power to switch-mode amplifiers  12 . In some embodiments, switch-mode amplifiers  12  are implemented as Class D or Class E amplifiers. The following discussion assumes that Class E amplifiers are employed. 
         [0030]    Switch-mode amplifiers  12  are identical. The depicted embodiment of switch-mode amplifier  12   a  will now be described. It should be appreciated that switch-mode amplifier  12   b  has the same circuitry. DC power supply  22  provides a DC voltage V dc  to a first terminal of an RF choke  32 . A second terminal of RF choke  32  communicates with an input terminal of a filter network  34 . Filter network  34  may include a low-pass filter or a band-pass filter. An output of filter network  34  communicates with a drain of switching transistor Q 1 , a first terminal of a capacitor Cs, and first terminal of a resonant LC pair  36 . A second terminal of capacitor Cs and a source of switching transistor Q 1  communicate with ground  38 . Cs can be the internal drain-source capacitance of transistor Q 1 , or of an external capacitor, or a combination thereof. A second terminal of LC pair  36  communicates with a first terminal of an output filter  40 . In some embodiments, LC pair  36  can include a diode  52 . A cathode of diode  52  communicates with a tap of the inductor in LC pair  36 . An anode of diode  52  communicates with ground  38 . Diode  52  implements an embodiment of an inductive clamp. A second terminal of output filter  40  communicates with a primary winding of a coupling transformer  42 . Output filter  40  terminates oscillations across a predetermined bandwidth for all conditions of load  20 . 
         [0031]    A secondary winding of coupling transformer  42  communicates with a first terminal of load  20  and with the corresponding secondary winding that is associated with amplifier  12   b.  A second terminal of load  20  communicates with the secondary winding that is associated with amplifier  12   b.  A control module  44  generates switch control signals  14   a  and  14   b  based on respective phase control signals  50   a  and  50   b.    
         [0032]    It should be appreciated that when switch-mode amplifiers  12  are implemented with Class D power amplifiers, they employ a bridge configuration of the power switches. Class D amplifiers therefore have more complex drive circuit requirements and a higher cost base than Class E amplifiers. 
         [0033]    While using phase control techniques with Class D or Class E implementations of switch-mode amplifiers  12 , the current and voltage profiles on the master switch-mode amplifier  12   a  and the slave switch-mode amplifier  12   b  are typically imbalanced. The level of imbalance is dependent on the load  20  configuration and the power level being supplied by RF amplifier  10 . While pulsing through phase control, the prevailing imbalance may increase stresses in components of master switch-mode amplifier  12   a  compared to slave switch-mode amplifier  12   b  (or vice versa). Such component stress increases may be substantial for some load configurations, which in turn may negatively impact the thermal profile and the reliability of RF amplifier  10 . Alternatively, in order to maintain the thermal profile and the reliability expectations, components with higher voltage, current and thermal ratings may be used in the amplifier circuit design, which in turn may increase cost, size and packaging requirements. 
         [0034]    The voltages and currents of the master switch-mode amplifier  12   a  and slave switch-mode amplifier  12   b  are imbalanced when the phase difference between them is other than 180 or zero degrees. This imbalance is due to the difference in the impedances seen at the drains and/or collectors of the respective power switches Q 1 , Q 2  at these phase differences. The current and voltage imbalance between switch-mode amplifiers  12  may result in a thermal imbalance, which when not accounted for in the design, can result in increased current thermal stresses of one switch-mode amplifier  12  when compared to the other, and in the worst case, can result in the failure of heat-sensitive components such as the power switches due to high thermal stresses. 
         [0035]    A phase switching technique can be employed to eliminate the imbalance in the voltage and current profiles in the master and slave switch-mode amplifiers  12   a,    12   b.  By using phase control signals  50   a  and  50   b,  the phasing between switch-mode amplifiers  12  is swapped each RF pulse cycle. Therefore, in one pulse cycle slave switch-mode amplifier  12   b  is operated with phase-lag (or phase-lead) with reference to master switch-mode amplifier  12   a.  In the next pulse cycle, master switch-mode amplifier  12   a  is operated with phase-lag (phase-lead) with reference to the slave switch-mode amplifier  12   b.  This phase swapping method facilitates the switching transistors of switch-mode amplifiers  12  to “see” the same load impedance on average taken over any even number of RF pulses regardless of the load configuration (inductive or capacitive) and the power level. Hence, the voltage and current profiles, and hence the thermal profiles, of switch-mode amplifiers  12  get balanced on average. In essence, phase reversal exploits the fact that the roles of switch-mode amplifiers  12  can be swapped every pulse such that each switch-mode amplifier takes the role of the master (or the slave) every alternative pulse. This approach results in a lower overall device stress by distributing the high-dissipation operation evenly between the two sides, increasing the reliability of RF amplifier  10 . This technique can be applied for any arbitrary waveform pulsing when master and slave are phase controlled to obtain maximum, minimum or partial output power. 
         [0036]    An analysis of RF amplifier  10  will now be described with reference to  FIG. 2 . The feasibility of pulsing through phase-controlled Class-E power amplifiers is established through analytical means using standard simplifying assumptions, e.g. ideal DC power supply  22  with voltage V dc , an ideal power switch Q 1  or Q 2 , a fixed capacitance Cs, LC pair  36  and capacitor Cs chosen for maximum power efficiency for a standard reference load  20  (usually  50  ohms), and ideal coupling transformers  42 . The analysis is performed with arbitrary loads  20  to fully characterize the circuit variables for the full phasing control range. The circuit variables of interest include: the power switch current and voltage for each switch-mode amplifier  12   a  and  12   b,  combined output power that is applied to load  20 , power balance between switch-mode amplifiers  12   a  and  12   b,  power losses due to hard-switching, and the like. 
         [0037]    Under steady state operation, the instantaneous total current i sc  (within an RF cycle) through the power switch and capacitor Cs is written in terms of a current i 1  flowing through the output of filter network  34  and a current i 2  flowing through LC pair  36 . Using fundamental and harmonic phasor components, i.e., direct and quadrature axes coordinate values of i 1  and i 2 : 
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         [0000]    where, θ is an arbitrary angle in radians within an RF cycle, between δ and 2π+δ, where δ is a phase angle of switch control signal  14   a  with reference to an arbitrary reference; i dc  is the dc component of current i 1 ; h is the harmonic number ranging from 1 to an arbitrary number n; i 1d     h    and i 2d     h    are the direct axis components of the h-th harmonic of currents, respectively; i 1 , i 2 ; i 1qh , and i 2qh  are the quadrature axis components of the h-th harmonic of currents, respectively, i 1  and i 2 . 
         [0038]    During an RF cycle, the average of the current through the power switch Q 1 , which is turned on and conducts between angles δ and π+δ, is given by 
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         [0000]    Note that i s0  should equal the dc current drawn from the DC voltage V dc , and this fact may be used to verify the correctness of any solution that would be obtained through the analysis. 
         [0039]    The instantaneous voltage v s  across the power switch Q 1  at angle θ during an RF cycle is given by 
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         [0000]    where, ω is the RF frequency in radians per second, Cs is the capacitance in parallel with the power switch Q 1 , and angle φ is the variable for integration. The average voltage v s0  across the power switch Q 1  during an RF cycle is given by 
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         [0000]    where, ε≧0 is an angle such that at 2π+δ−ε the instantaneous voltage v s (θ) across the power switch Q 1  reaches zero, or at which the next RF next half cycle commences, if v s (θ) does not reach zero prior to 2π+δ, as depicted in  FIG. 2 . Note that in the latter case, ε=0. Note that v s0  should equal the DC source voltage V dc . 
         [0040]    The direct and quadrature axes components v sd     h    and v sq     h   , respectively, of the h-th harmonic of the voltage across the power switch Q 1  are given by 
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         [0041]    The equation relating the direct and quadrature harmonic components of current i 1 , the voltage v s  across the power switch Q 1 , and the voltage v i  at the input nodes is given by 
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         [0000]    where, scaling factors k ad     h    and k aa     h    and impedance factors Z ad     h    and Z aq     h    are constants determined by the filter network  101  and the DC choke L 1 . Note that with ideal DC voltage source disconnected at the input node, the direct and quadrature harmonic components v id     h   , and v iq     h    should be zero. 
         [0042]    The equations relating the direct and quadrature harmonic components of current i 2 , the voltage v s  across the power switch Q 1 , the output voltage v o , and the output current i o  are given by, 
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         [0000]    where, scaling factors k bd     h   , k bq     h   , k cd     h   , and k cq     h   , impedance factors z bd     h   , and z bq     h   , and admittance factors y cd     h   , and y cq     h    are constants determined by the resonant LC pair  36  and output filter  40 . 
         [0043]    A second set of expressions similar to Eqs. (1) to (9) can be written for slave switch-mode amplifier  12   b.  The phase angle δ can be chosen as zero for master switch-mode amplifier  12   a,  and a desired value δs for slave switch-mode amplifier  12   b.    
         [0044]    The equation relating the direct and quadrature harmonic components of the output current i o , and the output voltages v om  and v os  is given by, 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    where, z od     h    and z oq     h    are load impedance factors. 
         [0045]    An exact solution to the phase controlled power amplifier configuration is obtained by solving a system of simultaneous nonlinear equations encompassing Eqs. (4) to (9), with v id     h    and v iq     h    set to zero, and v s0  set to V dc  for both switch-mode amplifiers  12 . Eq. (10) describes the interconnection relationship between switch-mode amplifiers  12  with the output current i o  the same for both. The higher the number of harmonics (=n) considered, the higher the accuracy of the solution, however, the number of resulting simultaneous equations and the variables to be solved increases with n, increasing the computation complexity. For most practical power amplifier designs, constraining n to 2 provides ample solution accuracy with low computation complexity. 
         [0046]    As the resulting simultaneous equations are nonlinear, an iterative process may be used for their solution. Further analysis of Eqs. (4) through (9) reveals that for a fixed value of angle ε, the simultaneous equations degenerate and become linear. Hence, the iterative process may be started with an initial value of ε (typically zero). The set of resulting linear equations are then solved using matrix inversion to compute the various nodal voltage and branch current variables. Correspondingly the value of ε is updated and the process repeated until convergence. Equality of power input to power output may be used as a convergence criteria. 
         [0047]    The results of the iterative solution obtained for a typical phase-controlled RF amplifier  10  are depicted in  FIGS. 3A through 3D . 
         [0048]      FIG. 3A  depicts the output power profile (z-axis) as a function of the phase control angle (x-axis) with reference to variation in load  20  impedance through a constant VSWR circle (y-axis).  FIG. 3A  indicates that the output power is controllable in a near linear fashion through phase control. 
         [0049]      FIG. 3B  depicts the DC input power (z-axis) drawn by each switch-mode amplifier  12  as a function of the phase control angle (x-axis) with reference to variation in the load impedance through a constant VSWR circle (y-axis).  FIG. 3B  indicates that the DC input power imbalance between the master and slave switch-mode amplifiers  12  is minimum at the extremes of the phase angle range (i.e., near 180° and 0°), and in some range, part of the input power drawn by master switch-mode amplifier  12   a  is returned back to DC power supply  22  through slave switch-mode amplifier  12   b.    
         [0050]      FIG. 3C  depicts the RMS voltage across the power switch (z-axis) of each respective switch-mode amplifier  12  as a function of the phase control angle (x-axis) with reference to variation in the load-impedance through a constant VSWR circle (y-axis).  FIG. 3C  indicates that the power switch voltage in both switch-mode amplifiers  12  marginally increases as the phase approaches zero. 
         [0051]      FIG. 3D  depicts the RMS current flowing through the power switch (z-axis) of each switch-mode amplifier  12  as a function of the phase control angle (x-axis) with reference to variation in load  20  impedance through a constant VSWR circle (y-axis).  FIG. 3D  indicates that the imbalance in the power switch current between switch-mode amplifiers  12  is high at the non-extreme phase values, and that at zero phase the currents flowing through the power switches are substantially high, even though the output power is zero. 
         [0052]    The results shown in  FIGS. 3A to 3D  indicate pulsing capability can be provided with switch-mode amplifiers  12  through phasing. Imbalances between switch-mode amplifiers  12 , and the additional voltage and current stresses expected while phasing should be taken into consideration during design. The above analysis indicates that when phase control is used for pulsing in a master-slave configuration of switch-mode amplifiers  12 , the circuit components of the master and the slave switch-mode amplifiers  12  will be stressed unevenly. The level of imbalance will be dependent on load  20  configuration (inductive or capacitive) and the power level. 
         [0053]    While the above analysis is provided for Class E amplifier topology, a similar analysis can be carried out for Class D amplifier topology. Also, a similar analysis can be carried out for Class D and E circuit topologies with protection circuits, such as inductive clamp diode  52 . 
         [0054]      FIG. 4  shows a configuration of phase control signals  50   a,    50   b  of the master and the slave switch-mode amplifiers  12 .  FIG. 4  depicts phase switching for the case of on/off pulsing and the corresponding RF output waveform. 
         [0055]      FIG. 5  shows a configuration of phase control signals  50   a,    50   b  of the master and slave switch-mode amplifiers  12 .  FIG. 5  depicts phase switching for the case of non-zero two-level pulsing and the corresponding RF output waveform. 
         [0056]      FIG. 6  shows configuration of phase control signals  50   a,    50   b  of the master and the slave switch-mode amplifiers  12 .  FIG. 6  depicts phase reversal for slow rise and fall time pulsing and the corresponding RF output waveform. 
         [0057]      FIG. 7  shows an example RF output pulse trace from an embodiment of RF amplifier  10 . The embodiment includes Class-E switch-mode amplifiers  12 , 20 kHz pulse frequency, 50% duty cycle, 500 W peak power, and 50 ohms load  20 . 
         [0058]      FIG. 8  shows an RF output pulse trace for non-zero two-level pulsing at 20 KHz pulse frequency with 50% duty cycle, 50 ohms load  20  with high power at 700 W and low power at 175 W. 
         [0059]      FIGS. 9A-9K  show simulated voltage and current traces of RF amplifier  10 . The simulations include the phase switching technique that is shown in  FIGS. 4-6 .  FIGS. 9A and 9B  depict the RF power and voltage applied to load  20 .  FIG. 9C  depicts the switching current though power switch Q 1 .  FIG. 9D  depicts the current through clamping diode  52  of switch-mode amplifier  12   a.    FIG. 9E  depicts the switching current though power switch Q 2 .  FIG. 9F  depicts the current through clamping diode  52  of switch-mode amplifier  12   b.    FIG. 9G  depicts the switching voltage across power switch Q 1 .  FIG. 9H  depicts the voltage across clamping diode  52  of switch-mode amplifier  12   a.    FIG. 9K  depicts the voltage across clamping diode  52  of switch-mode amplifier  12   b.    
         [0060]    For the simulation that generated  FIGS. 9A-9K , the output power is pulsed with the low power about half of the high power, the imbalance between the switching transistor currents of the master and the slave power amplifiers during a single pulse cycle is approximately ±30% (which translates into an imbalance in the power dissipation of approximately ±55%). With the pulse switching, the current and power imbalances are eliminated when averaged over any even number of pulse cycles. 
         [0061]    RF amplifier  10  and the associated phase switching method that is shown in  FIGS. 4-6  provide several advantages over the prior art. The phase switching technique reduces component stress balances thermal profile resulting in increased reliability. Pulsing through Class D and E power amplifier topologies facilitates flexible pulsing with low power losses. RF amplifier  10  provides a wide range of flexible RF envelope pulse shapes and waveforms using the phase switching method. RF amplifier  10  provides high-speed pulsing capability that facilitates fast rise and fall times, high pulsing frequency, wide range of pulse duty cycles, high pulse power accuracy. The need for high-speed power supply control for pulsing is eliminated. RF amplifier  10  provides a single solution to various types of pulsing (on-off, non-zero two-level, multi-level, arbitrary waveform), which standardizes implementation and increases reliability. 
         [0062]    RF amplifier  10  and its associated phase switching method offers numerous benefits in plasma assisted semiconductor manufacturing. Some of the benefits for etching include: increased etch selectivity; improved vertical side-wall profile; reduction of trenching, notching &amp; charging damage; increased etch uniformity; reduction of aspect ratio dependent etch effects; reduction of heat flux to substrates. RF pulsing includes various parameters (frequency, duty cycle, shape etc.) that may be adjusted to maximize semiconductor-processing effectiveness. For example, with on off pulsing, the pulsing frequency may be high enough such that the plasma is never fully extinguished while using a low pulsing duty cycle so that ion-bombardment can be optimally channeled. Alternatively, with non-zero two-level pulsing, a minimum RF power level may be chosen that sustains plasma generation while using pulses with optimum duty-cycle superimposed on the chosen minimum RF power to harness one or more of the benefits discussed above. 
         [0063]    Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification, and the following claims.