Abstract:
Disclosed herein is an organic thin film transistor comprising a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer, source-drain electrodes and a protective layer wherein a buffer layer is interposed between the organic semiconductor layer and the protective layer. Such a transistor minimizes the deterioration in the performance of the transistor due to ambient air containing oxygen and moisture, and the degeneration in the performance of the transistor caused during mounting a display device.

Description:
BACKGROUND OF THE INVENTION 
     This non-provisional application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 2003-83584 filed on Nov. 24, 2003, which is herein incorporated by reference. 
     1. Field of the Invention 
     The present invention relates to an organic thin film transistor comprising a buffer layer, and more particularly to an organic thin film transistor comprising a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer, source-drain electrodes and a protective layer. A buffer layer is interposed between the organic semiconductor layer and the protective layer, thereby minimizing the deterioration in the performance of the transistor caused by ambient air containing oxygen and moisture, and mounting process of a display device thereto. 
     2. Description of the Related Art 
     Recently, polymers have been actively investigated as novel electrical and electronic materials in a wide variety of applications (e.g., functional electronic and optical devices). The investigations have focused on easy molding into the form of fibers and films, high flexibility, high conductivity and low manufacturing costs. Among devices fabricated from these conductive polymers, research on organic thin film transistors fabricated using organic materials as semiconductor layers has been conducted since the 1980&#39;s. In this connection, a number of studies are now being actively undertaken around the world. Organic thin film transistors are expected to be useful for driving devices of active displays and in plastic chips for use in smart cards and inventory tags. A device using an organic thin film transistor necessitates a protective layer for protecting the transistor from ambient air containing oxygen and moisture, and a supporting layer for mounting a display device, particularly in the case of a display application. There are currently no effective techniques for forming a protective layer or supporting layer in organic thin film transistors. Some attempts to form an inorganic film made of SiN x , SiO x , etc. on an organic thin film transistor by CVD or sputtering have been made, but the processes cause serious deterioration of the organic semiconductor layer due to active gases or plasma. This results in drastic reduction in the performance of the organic thin film transistor. 
     Several methods using an organic film made of a polyimide, BCB (benzocyclobutene) or photoacryl as a protective layer have been performed. However, these methods are not effective in forming a protective layer of an organic thin film transistor in that the organic active layer is drastically deteriorated at an annealing temperature higher than 150° C. The major problem caused in the film formation of a protective layer using an organic material is the direct contact between a material used to form the protective layer and an organic semiconductor layer. At this time, an organic solvent used in the formation of the protective layer deteriorates the performance of the organic semiconductor layer. Jackson, a professor at Penn. State University and his team tried to effectively form a protective layer using an organic film of PVA (polyvinyl alcohol). However, this method which used patterned pentacene as an organic semiconductor layer, has a problem in that the charge carrier mobility is decreased to ⅓ of its initial value after processing (Solid-State Electronics 47(2003) 297–301). 
     No approaches that can avoid a decrease in the performance of an organic thin film transistor caused upon forming an organic or inorganic film as a protective layer have been reported until now. Accordingly, development of novel protective layers and processes effective for forming the protective layers is necessitated to manufacture applied products using organic thin film transistors. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of the above problems in the prior art. A feature of the present invention is to provide an organic thin film transistor wherein a buffer layer is interposed between an organic semiconductor layer and a protective layer so that the buffer layer prevents the deterioration of the organic semiconductor layer by a material used to form the protective layer and minimizes the degeneration in the performance of the transistor after formation of the protective layer. 
     In accordance with a feature of the present invention, there is provided an organic thin film transistor comprising a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer, source-drain electrodes and a protective layer wherein a buffer layer is interposed between the organic semiconductor layer and the protective layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIGS. 1   a  and  1   b  are cross-sectional views showing structures of organic thin film transistors according to the present invention; 
         FIG. 2   a  is a graph showing the current transfer characteristics of an organic thin film transistor in an Example of the present invention, in which a buffer layer is formed and no protective layer is formed; 
         FIG. 2   b  is a graph showing the charge carrier mobility of an organic thin film transistor in an Example of the present invention, in which a buffer layer is formed and no protective layer is formed; 
         FIG. 3   a  is a graph showing the current transfer characteristics of an organic thin film transistor in an Example of the present invention, in which a buffer layer, a first protective layer and a second protective layer are formed; 
         FIG. 3   b  is a graph showing the charge carrier mobility of an organic thin film transistor in an Example of the present invention, in which a buffer layer, a first protective layer and a second protective layer are formed; 
         FIG. 4   a  is a graph showing the current transfer characteristics of an organic thin film transistor in a Comparative Example of the present invention, in which an active layer is formed and no protective layer is formed; 
         FIG. 4   b  is a graph showing the charge carrier mobility of an organic thin film transistor in a Comparative Example of the present invention, in which an active layer is formed and no protective layer is formed; 
         FIG. 5   a  is a graph showing the current transfer characteristics of an organic thin film transistor in a Comparative Example of the present invention, in which an active layer, a first protective layer and a second protective layer are formed; and 
         FIG. 5   b  is a graph showing the charge carrier mobility of an organic thin film transistor in a Comparative Example of the present invention, in which an active layer, a first protective layer and a second protective layer are formed. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, the present invention will be explained in more detail with reference to the accompanying drawings. 
       FIGS. 1   a  and  1   b  are cross-sectional views showing structures of organic thin film transistors according to the present invention. Referring to  FIGS. 1   a  and  1   b , the organic thin film transistor of the present invention comprises a substrate  1 , a gate electrode  2 , a gate insulating layer  3 , source-drain electrodes  4 , an organic semiconductor layer  5 , a buffer layer  6 , a first protective layer  7  and a second protective layer  8 , and the buffer layer  6  is interposed between the organic semiconductor layer  5  and the first protective layer  7 . The structures of the organic thin film transistor shown in  FIGS. 1   a  and  1   b  are simply preferred embodiments, and it is to be understood that various structures of the organic thin film transistor comprising the buffer layer and the protective layer are possible so far as they do not detract from the object of the present invention. 
     The buffer layer is made of an organic material having a resistance of 10 6  ohm-cm more. Specific examples of the organic material include, but are not limited to, Alq3 (tris(8-hydroxyquinoline)aluminum), BAlq3 (bis(2-methyl-8-quinolato) (p-phenyl-phenolato) aluminum), PTCDA (perylenetetra-carboxylicdianhydride), DPS (dicyano substituted diphenyl-sulfone), TCNQ (tetracyano-quinodimethane), DCAQ (2-tert-butyl-9,10-N,N′-dicyanoanthraquinonediimine) and the like. The buffer layer may be formed by a variety of techniques including vacuum deposition, dip coating, spin coating, printing, spray coating, roll coating, etc. 
     The protective layer preferably has a double-layer structure of a first protective layer and a second protective layer as shown in  FIGS. 1   a  and  1   b . The first protective layer is made of a water-soluble organic material such as PVA (polyvinyl alcohol), and the second protective layer is made of an organic material crosslinkable by UV light or heat such as a photoactive or thermoactive polyacrylate. The structure of the protective layer is not specifically limited to the structure described herein, and various structures are possible. 
     Materials for the gate insulating layer of the organic thin film transistor according to the present invention include, but are not limited to, polyolefins, polyvinyls, polyacrylates, polystyrenes, polyurethanes, polyimides and derivatives thereof. 
     As materials for the organic semiconductor layer, materials commonly used in the art can be used. Specific examples of the materials include, but are not limited to, pentacenes, copper phthalocyanines, polythiophenes, polyanilines, polyacetylenes, polypyrroles, polyphenylene vinylenes and derivatives thereof. 
     As materials for the gate electrode and source-drain electrodes, metals and conductive polymers commonly used in the art can be used. Specific examples of the materials include, but are not limited to, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), indium-tin oxides (ITOs), polythiophenes, polyanilines, polyacetylenes, polypyrroles, polyphenylene vinylenes, PEDOT(polyethylenedioxythiophene)/PSS(polystyrenesulfonate) mixtures and the like. 
     Specific Examples of materials for the substrate of the organic thin film transistor according to the present invention include, but are not limited to, glass, silicone, plastics and the like. 
     Hereinafter, the present invention will be described in more detail with reference to the following preferred examples. However, these examples are given for the purpose of illustration and are not to be construed as limiting the scope of the invention. 
     EXAMPLE 1 
     Fabrication of Organic Thin Film Transistor Comprising Buffer Layer and Protective Layer 
     In this example, an organic thin film transistor having the structure shown in  FIG. 1   a  was fabricated. First, Al was deposited on a washed glass substrate by a vacuum deposition technique to form a gate electrode with a thickness of 1,500 Å. A mixture of a polyimide-based material and a polyacrylate-based material was coated onto the gate electrode to a thickness of 7,000 Å by a spin coating at 2,000 rpm. The coating was baked at 100° C. for 10 minutes and 150° C. for 2 hours, sequentially, to form an organic gate insulating layer. Next, pentacene was deposited on the organic gate insulating layer by organic molecular beam deposition (OMBD) at a vacuum pressure of 2×10 −7  torr, a substrate temperature of 50° C. and a deposition rate of 0.85 Å/sec., to form an organic semiconductor layer with a thickness of 1,000 Å. Then gold was deposited on the organic semiconductor layer through a shadow mask having a channel length of 100 μm and a channel width of 0.5 mm to form source-drain electrodes with a thickness of 1,000 Å. In order to form a buffer layer, Alq3 was deposited to a thickness 1,000 Å at a substrate temperature of 30° C. and a deposition rate of 1 Å/sec. A first protective layer was formed by spin coating PVA on the buffer layer to a thickness of 300 Å by spin coating, followed by drying it in a convection oven at 100° C. for 10 minutes. Thereafter, a second protective layer was formed by spin coating PR (PC-403, JSR) to a thickness of 2 μm. The formed protective layer was soft-baked in a convection oven at 100° C. for 2 minutes, exposed to light for 20 seconds, and then hard-baked on a hot plate at 100° C. for 1 hour to fabricate an organic thin film transistor. 
     Curves showing the current transfer characteristics and the charge carrier mobility of the device before formation of the protective layer were plotted using a KEITHLEY semiconductor characterization system (4200-SCS), and are shown in  FIGS. 2   a  and  2   b , respectively. Curves showing the current transfer characteristics and the charge carrier mobility of the final device in which the protective layer was formed were plotted using the same system and are shown in  FIGS. 3   a  and  3   b , respectively. 
     A curve showing the current transfer characteristics of the final device was plotted using a KEITHLEY semiconductor characterization system (4200-SCS). From the curve, the electrical properties of the device were calculated by the following procedures, and the results are shown in Table 1 below.
         The charge carrier mobility of the devices was calculated by the following equation (4) from the slope of a graph representing the relationship between (I SD ) 1/2  and V G , wherein the graph was plotted according to the following current equations in saturation region (1) and (2) and the slope was calculated by the following equation (3):       

                     I   SD     =         WC   0       2   ⁢   L       ⁢       μ   ⁡     (       V   G     -     V   T       )       2               (   1   )                   I   SD       =           μ   ⁢           ⁢     C   0     ⁢   W       2   ⁢   L         ⁢     (       V   G     -     V   T       )               (   2   )               slope   =         μ   ⁢           ⁢     C   0     ⁢   W       2   ⁢   L                 (   3   )                 μ   FET     =         (   slope   )     2     ⁢       2   ⁢   L         C   0     ⁢   W                 (   4   )               
In the above equations (1)˜(4), I SD : source-drain current; μ or μ FET : charge carrier mobility; C o : capacitance of the insulating layer; W: channel width; L: channel length; V G : gate voltage; and V T : threshold voltage.
         Threshold voltage(V T ) was obtained from the intersection where the V G  axis intersects the extension of the linear portion of the graph representing the relationship between (I SD ) 1/2  and V G . As the absolute value of the threshold voltage approximates to zero, the consumption of electric power decreases.   Off-state leakage current(I off ) refers to the current flowing at the off-state and was determined by taking the minimum current at the off-state from the I on /I off  ratio.   I on /I off  ratio is represented by the following equation (5):       
                       I   on       I   off       =       (     μ   σ     )     ⁢       C   0   2         qN   A     ⁢     t   2         ⁢     V   D   2               (   5   )               
In the above equation (5), I on : maximum current; I off : off-state leakage current; μ: charge carrier mobility; δ: conductivity of the active layer; q: electric charge; N A : electric charge density; t: thickness of the insulating layer; C 0 : capacitance of the insulating layer; and V D : drain voltage. As can be seen from this equation, the larger the dielectric constant and the smaller the dielectric film thickness, the larger the obtained I on /I off  ratio. Therefore, the kind and thickness of the dielectric film are crucial factors for determining the I on /I off  ratio. The off-state leakage current is in inverse proportion to the I on /I off  ratio.
 
     As evident from the equation above, as the dielectric constant of a dielectric film increases and the thickness decreases, the current ratio I on /I off  decreases. Accordingly, the kind and the thickness of the dielectric film are important factors in determining the current ratio. In this case, the off-state leakage current becomes low. 
     COMPARATIVE EXAMPLE 
     Fabrication of Organic Thin Film Transistor Comprising Protective Layer Without Formation of Buffer Layer 
     An organic thin film transistor was fabricated in the same manner as in Example 1 above, except that a buffer layer was not formed. 
     Curves showing the current transfer characteristics and the charge carrier mobility of the device before formation of the protective layer are shown in  FIGS. 4   a  and  4   b , respectively. Curves showing the current transfer characteristics and the charge carrier mobility of the final device in which the protective layer was formed are shown in  FIGS. 5   a  and  5   b , respectively. 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Charge 
                 Thres- 
                   
                   
               
               
                   
                 carrier 
                 hold 
                 Off-state 
                   
               
               
                   
                 mobility 
                 voltage 
                 leakage 
                 I on /I off   
               
               
                   
                 (cm 2 /Vs) 
                 (V) 
                 current (A) 
                 Ratio 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Example 
                 Before 
                 1.2 
                 −7 
                 1.90 × 10 −10   
                 3.03 × 10 4   
               
               
                   
                 formation 
               
               
                   
                 of protective 
               
               
                   
                 layer 
               
               
                   
                 After 
                 1.2 
                 −6.5 
                 2.00 × 10 −10   
                 2.60 × 10 4   
               
               
                   
                 formation 
               
               
                   
                 of protective 
               
               
                   
                 layer 
               
               
                 Compar- 
                 Before 
                 0.48 
                 −8 
                 8.20 × 10 −11   
                 4.27 × 10 4   
               
               
                 ative 
                 formation 
               
               
                 Example 
                 of protective 
               
               
                   
                 layer 
               
               
                   
                 After 
                 0.13 
                 −8 
                 2.50 × 10 −10   
                 2.96 × 10 3   
               
               
                   
                 formation 
               
               
                   
                 of protective 
               
               
                   
                 layer 
               
               
                   
               
             
          
         
       
     
     As can be seen from Table 1, in the case of the device in which a protective layer was formed and a buffer layer was not formed, the performance of the device was decreased by about 70%. In contrast, the performance of the device in which a buffer layer was formed was decreased by 10% only, and nearly unchanged from the initial state. 
     Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.