Abstract:
A fiber optic transceiver or receiver having circuitry for detecting signal strength of a photo-diode therein is disclosed. In one embodiment, the photo-current generated by the photo-diode is provided to a pre-amplifier circuit. The pre-amplifier circuit generates differential signals including a positive differential signal and a negative differential signal whose difference is representative of the detected photo-current. The fiber optic receiver further includes a post-amplifier circuit that is coupled to the pre-amplifier circuit to receive the differential signals. In one embodiment, the post-amplifier circuit includes circuitry to accurately derive a signal strength of the photo-current from the differential signals.

Description:
[0001]    The present application claims priority to, under 35 U.S.C. 119(e), U.S. Provisional Patent Application bearing serial No. 60/357,608, filed Feb. 14, 2002, which is incorporated herein by reference. 
     
    
     
       BRIEF DESCRIPTION OF THE INVENTION  
         [0002]    The present invention relates generally to signal detectors, and particularly to optical signal strength detectors.  
         BACKGROUND OF THE INVENTION  
         [0003]    It is useful to measure the received optical power in fiber optic links in order to determine the integrity of the signal path and terminal devices. The photo-current in the photo-diode is proportional to the received power. Hence, one way of measuring received optical power is to measure the photo-current level.  
           [0004]    Typical optoelectronic receivers utilize a photo-detector which is integrated in the same TO (Transistor Outline) package as the pre-amplifier. Most TO packages have only four pins. Two of the pins are connected to receive a differential signal from the pre-amplifier, one of the pins receives a power supply voltage, and one of the pins is for ground. Since all four pins of the TO packages each have a defined function, there is no separate lead available to output the photo-current. A fifth pin would not be an ideal solution because space is at a premium in TO packages.  
           [0005]    Several prior art signal detectors measure the photo-current level without the use of a fifth pin. At low signal amplitudes (e.g., at 0.5mV or less), however, these signal detectors exhibit a significant loss of gain—and thus accuracy. This loss of gain at low signal amplitudes is caused by a breakdown of the switch-like behavior of these signal detectors.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention provides a more accurate method and apparatus for measuring the photo-current of a photo-diode in a fiber optic receiver or transceiver. In particular, the present invention does not require a “fifth pin” for outputting the photo-current signal. Rather, the photo-current level is derived from differential signal output.  
           [0007]    One aspect of the present invention includes a signal detector. The signal detector comprises a multiplier with a signal input terminal configured to receive a signal, a control input terminal configured to receive a control signal, and a modified signal output terminal configured to output a modified signal. The modified signal is a function of the control signal and the signal. The signal detector further comprises detector circuitry with a modified signal input terminal configured to receive the modified signal and an active signal output terminal configured to output an active signal. The detector circuitry has a set of known factors that define the detector circuitry and the active signal is a function of this set of known factors and the modified signal. Finally, the signal detector further comprises a comparator with an active signal input terminal configured to receive the active signal, a reference signal input terminal configured to receive a reference signal, and a control signal output terminal configured to output the control signal. The control signal is a function of a difference between the reference signal and the active signal. In operation, the multiplier, the detector circuitry, and the comparator form a feed-back loop that forces the active signal to approximate the reference signal and, in so doing, forces the modified signal to have a minimum peak-to-peak amplitude that corresponds to the signal. As a result, a peak-to-peak amplitude of the signal may be accurately computed by reference to the control signal and the set of known factors.  
           [0008]    Another aspect of the present invention also includes a signal detector. This signal detector comprises a multiplier with a differential signal input terminal configured to receive differential signals with a voltage differential from a first stage circuit, a control signal input terminal configured to receive a control signal with voltage V c , and an output terminal configured to output modified differential signals that are proportional to the differential signals and the control signal. This signal detector further comprises detection circuitry for receiving the modified differential signals and producing an active signal, with voltage V active , proportional to the voltage differential of the differential signals. Finally, this signal detector further comprises a comparator with a first comparator input terminal configured to receive the active signal from the crude signal detector, a second comparator input terminal configured to receive a reference voltage V ref , and a comparator output terminal configured to couple the control signal to the multiplier. In operation, V active  is driven to V ref  and when V active  is approximately equal to V ref , V c  is indicative of the voltage differential of the differential signals.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    Aspects of the present invention will be more readily apparent from the following description and appended claims when taken in conjunction with the accompanying drawings, in which:  
         [0010]    [0010]FIG. 1A is a block diagram of an optical communication system according to an embodiment of the present invention;  
         [0011]    [0011]FIG. 1B is a graph of the light intensity of an exemplary light signal sent by the transmitter over a period of time;  
         [0012]    [0012]FIG. 1C is a graph of the signal strength of an exemplary electrical signal produced by a photo-diode over a period of time;  
         [0013]    [0013]FIG. 1D is a graph of the signal strength of exemplary differential signals produced by a first stage circuit over a period of time;  
         [0014]    [0014]FIG. 2 is the general circuit layout for a signal strength detector consistent with a preferred embodiment of the present invention;  
         [0015]    [0015]FIG. 3A is the general circuit layout for a first exemplary signal strength detector consistent with an embodiment of the present invention;  
         [0016]    [0016]FIG. 3B is a graph of a voltage V out1 , and a voltage equal to I R1 *R1 present in the signal strength detector of FIG. 3A;  
         [0017]    [0017]FIG. 3C is a graph of a voltage V out2  and the voltage equal to I R1 *R1 present in the signal strength detector of FIG. 3A;  
         [0018]    [0018]FIG. 3D is a graph of the voltage equal to I R1 *R1 present in the signal strength detector of FIG. 3A;  
         [0019]    [0019]FIG. 3E is a graph of the voltage equal to V active  present in the signal strength detector of FIG. 3A;  
         [0020]    [0020]FIG. 4A is the general circuit layout for a second exemplary signal strength detector consistent with an embodiment of the present invention;  
         [0021]    [0021]FIG. 4B is a graph of a voltage V out  present in the signal strength detector of FIG. 4A;  
         [0022]    [0022]FIG. 4C is a graph of a voltage (V active −V offset ) present in the signal strength detector of FIG. 4A;  
         [0023]    [0023]FIG. 4D is a graph of a voltage V active  present in the signal strength detector of FIG. 4A; and  
         [0024]    [0024]FIG. 5A is the general circuit layout for a third exemplary signal strength detector consistent with an embodiment of the present invention; and  
         [0025]    [0025]FIG. 5B is a graph of a voltage V out  present in the signal strength detector of FIG. 5A. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0026]    Preferred embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described. It will be appreciated that in the development of any such embodiment, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.  
         [0027]    [0027]FIG. 1A shows a block diagram of an optical communication system  100  according to one embodiment of the present invention. The communication system  100  includes an optoelectronic transmitter/transceiver  102  that transmits a light signal  104  with an associated frequency and light intensity. The transmitter  102  typically includes a laser and optics (not illustrated) to transmit the light signal  104 . A light intensity graph  106  included in FIG. 1B shows the light intensity of an exemplary light signal  104  sent by the transmitter  102  over a period of time. The light intensity corresponds to the voltage of the light signal  104 . The peak-to-peak amplitude or signal strength of the light signal  104  is denoted on the light intensity graph  106  by the symbol 2Δ.  
         [0028]    The communication system  100  also includes an optoelectronic receiver/transceiver  110  that receives the light signal  104  from the transmitter  102 . The receiver  110  contains a photo-diode  112 , a first stage circuit  118  (e.g., a Pre-Amplifier Circuit), and a second stage circuit  124  (e.g., a Post-Amplifier Circuit). In an exemplary implementation, the photo-diode  112  and the first stage circuit  118  are integrated into a Transistor Outline (TO) package  119 , which is typically part of the optoelectronic receiver/transceiver  110 .  
         [0029]    The photo-diode  112  receives the light signal  104  from the transmitter  102  and converts it to an electrical signal  114 . The electrical signal  114  has an associated signal strength corresponding to the voltage of the electrical signal  114 . A signal intensity graph  116  included in FIG. 1C shows the signal strength of an exemplary electrical signal  114  produced by the photo-diode  112  over a period of time. The peak-to-peak amplitude or signal strength of the electrical signal  114  is denoted on the signal intensity graph  116  as 2Δ′. The signal strength 2Δ′ of the electrical signal  114  is proportional to the signal strength 2Δ of the light signal  104 . This proportionality is a function of the photo diode&#39;s  112  scaling or loss factors.  
         [0030]    The first stage circuit  118  receives the electrical signal  114  from the photodiode  112  and produces amplified differential signals  120 . The amplified differential signals  120  consist of a positive pre-amplifier output and a negative preamplifier output. The amplified differential signals  120  have a signal strength that corresponds to the voltage thereof. A signal intensity graph  122  included in FIG. 1D shows the signal strength of exemplary differential signals  120  produced by the first stage circuit  118  over a period of time. In FIG. 1D, the positive pre-amplifier output corresponds to the dashed line and the negative pre-amplifier output corresponds to the solid line. As shown by the signal intensity graph  122 , the voltage of the positive pre-amplifier output is at a maximum (e.g., at MΔ′) when the voltage of the negative pre-amplifier output is at a minimum (e.g., at −MΔ′) and vice versa. In other words, the amplified differential signals  120  are nominally equal in amplitude, but 180 degrees out of phase.  
         [0031]    The peak-to-peak amplitude or signal strength of the differential signals  120  is represented on the signal intensity graph  122  as 2MΔ′, where M corresponds to the amplification factor of the first stage circuit  118 . The signal strength 2Δ of the light signal  104  may be derived from the signal strength 2MΔ′ of the differential signals  120  by first determining the signal strength 2Δ′ of the electrical signal  114  using the amplification factor M of the first stage circuit  118  and then determining the signal strength 2Δ of the light signal  104  using the scaling or loss factors of the photo diode  112 .  
         [0032]    The second stage circuit  124  receives the differential signals  120  from the first stage circuit  118  for further processing. The present invention provides particular circuit designs for use as part of the second stage circuit  124  to determine the signal strength 2MΔ′ of the differential signals  120 .  
         [0033]    Signal Strength Detector  
         [0034]    [0034]FIG. 2 shows a preferred embodiment of a signal strength detector  200 . The signal strength detector  200  includes a feedback loop formed by a multiplier  204 , a comparator  214 , and detector circuitry  208 .  
         [0035]    The multiplier  204  includes an input terminal that receives input produced by the first stage circuit  118  (FIG. 1) via the multiplier input line  202 . Such input may be one or both of the differential signals  120 —represented by the voltage V in . In embodiments in which the input is just one of the differential signals  120 , the multiplier input line  202  is typically formed by one line. And in embodiments in which the input is both of the differential signals  120 , the multiplier input line  202  is typically formed by two separate lines.  
         [0036]    The multiplier  204  also includes an output terminal coupled to the detector circuitry  208  via the multiplier output line  206 . The output of the multiplier  204  is represented by the voltage V out . Like the input to the multiplier  204 , the output transmitted by the multiplier  204  to the detector circuitry  208  may be formed by one or two signals. The multiplier output line  206  may, therefore, be formed by one or two separate lines depending on the embodiment.  
         [0037]    The detector circuitry  208  enables the detection of either the average or peak amplitude of the differential signals  120 . As stated above, the detector circuitry  208  receives the voltage V out  as input. The output of the detector circuitry  208  preferably includes the voltage V active  and the voltage V ref , which is a target voltage for the voltage V active . V active  corresponds to the average or peak amplitude of the differential signals  120 . Numerous configurations may be used for the detector circuitry  208  without departing from the scope of the present invention. A number of embodiments with differing detector circuitry  208  configurations are described below in detail.  
         [0038]    The comparator  214  includes a first input terminal  210  coupled to the detector circuitry  208  and a second input terminal  212  coupled to the detector circuitry  208  to receive the voltage V ref  and the voltage V active , respectively.  
         [0039]    The comparator  214  also includes an output terminal coupled via a control signal line  216  to the multiplier  204 . The output of the comparator  214  is a voltage V c  that reflects a difference between the voltage V ref  and the voltage V active . As the difference between the voltage V ref  and the voltage V active  increases, so does the voltage V c  and vice versa. The sign of the voltage V c  depends upon which of the input terminals  210 ,  212  is the inverted input terminal of the comparator  214  and which of the voltage V ref  and the voltage V active  is greatest. As described in detail below, in some of the embodiments of the present invention, the inverted input terminal is set to V active , but in other embodiments, the non-inverted input terminal is set to V active .  
         [0040]    As indicated above, the multiplier  204  receives the voltage V c  through the control signal line  216 . The multiplier  204  is preferably configured to amplify the voltage V in  by a factor proportional to the voltage V c  and to bias the amplified voltage V in  with a DC voltage V bias  to produce the voltage V out . In preferred embodiments, the voltage V out  is approximately equal to V bias +(V in *V c ). The voltage V in  is, therefore, approximately equal to (V out −V bias )/V c .  
         [0041]    Operation of the Signal Strength Detector  
         [0042]    During the operation of the signal strength detector  200 , the voltage V ref  and the voltage V active  are applied to the comparator  214 . Again, the comparator  214  produces a voltage V c  that represents a difference between the voltage V active  and the voltage V ref .  
         [0043]    The multiplier  204  amplifies the voltage V in  by a factor proportional to the voltage V c  and then biases the resulting voltage with the DC voltage V bias  to ensure the desired minimum and maximum value of the voltage V out . The detector circuitry  208  then receives the voltage V out  as input. From this voltage, the detector circuitry  208  produces the voltage V active .  
         [0044]    The difference between the minimum and maximum value of the voltage V out  is preferably always great enough to prevent a loss of gain by the detector circuitry  208 . In other words, the maximum value of the voltage V out  is greater by a pre-defined amount than the minimum value of the voltage V out .  
         [0045]    And as stated above, the value of the voltage V active  corresponds to the voltage V out . So when the voltage V active  varies from the voltage V ref , the voltage V c , and thus the voltage V out , is adjusted so that the voltage V active  produced by the detector circuitry  208  may then vary little, if at all, from the voltage V ref .  
         [0046]    V ref  is calculated by reference to the configuration of the detector circuitry  208 . More specifically, the voltage V ref  is set to what the voltage V active  is when the difference between the minimum and maximum value of the voltage V out  input to the detector circuitry  208  is at an ideal level (e.g., a level at which the detector circuitry  208  does not exhibit a loss of gain).  
         [0047]    Because the relationship between the voltages V in  and V out  is known and the desired levels of the voltage V out  is known, the voltage V in , and thus the peak-to-peak amplitude of the differential signals  120 , can be determined by measuring the voltage V c .  
         [0048]    And as stated above, the voltage V in  is one or both of the differential signals  120  and thus equal in amplitude to 2MΔ′. The signal strength 2Δ of the light signal  104  may be derived from the voltage V in , which is equal to 2MΔ′ and (V out −V bias )/V c , by first determining the signal strength 2Δ′ of the electrical signal  114  using the amplification factor M of the first stage circuit  118 . The signal strength 2Δ of the light signal  104  may then be determined using the scaling or loss factors of the photo diode  112 .  
         [0049]    First Exemplary Embodiment of the Signal Strength Detector  
         [0050]    [0050]FIG. 3A illustrates a first exemplary embodiment of the signal strength detector  200 . In this embodiment, the multiplier input line  202  includes two separate leads in order to transmit both of the differential signals  120  (i.e., the voltages V in1  and V in2 , which together comprise the voltage V in  and separately vary between a minimum voltage of −MΔ′ and a maximum voltage of MΔ′) from the first stage circuit  118  to the multiplier  204 . Similarly, the multiplier output line  206  includes two separate leads in order to transmit the voltages V out1  and V out2 , which together comprise the voltage V out  and are the differential signals  120  following amplification and DC voltage offset by the multiplier  204 .  
         [0051]    Further, the detector circuitry  208  includes an active signal detector  300  and a dummy signal detector  301 . The active signal detector  300 , which receives the voltages V out1  and V out2 , produces the voltage V active  and the dummy signal detector  301 , which receives the voltage V bias  and the voltage V offset , produces the voltage V ref .  
         [0052]    As shown in FIG. 3A, the active signal detector  300  includes a first left transistor  302 , a first right transistor  304 , a first resistor  306  with resistance value R1, a second resistor  308  with resistance value R2, and a power supply V cc    310 .  
         [0053]    On the left side of the active signal detector  300 , the first resistor  306  is coupled to the emitter terminal of the first left transistor  302  and to circuit ground (or other fixed potential circuit node). The collector terminal of the first left transistor  302  is coupled to the second resistor  308 , which is also coupled to the power supply V cc    310 , and the second input terminal  212 , which is the inverted input terminal of the comparator  214  since V active  increases when V out  increases. The base terminal of the first left transistor  302  is coupled to the multiplier  204  and receives the voltage V out1 .  
         [0054]    On the right side of the active signal detector  300 , the first resistor  306  is coupled to the emitter terminal of the first right transistor  304 . The collector terminal of the first right transistor  304  is coupled to the second resistor  308 . The base terminal of the first right transistor  304  is coupled to the multiplier  204  and receives the voltage V out2 .  
         [0055]    As also shown in FIG. 3A, the dummy signal detector  301  includes a second left transistor  312 , a second right transistor  314 , a third resistor  316  with resistance value R1, a fourth resistor  318  with resistance value R2, a power supply V cc    320 , and a voltage source  322 .  
         [0056]    On the left side of the dummy signal detector  301 , the third resistor  316  is coupled to the emitter terminal of the second left transistor  312  and to circuit ground (or other fixed potential circuit node). The collector terminal of the second left transistor  312  is coupled to the fourth resistor  318 , which is also coupled to the power supply V cc    320 , and to the negative terminal of the voltage source  322 . The base terminal of the second left transistor  312  is set to the voltage V bias , which is the same voltage used to DC offset the voltages V in1  and V in 2  following amplification by the multiplier  204 .  
         [0057]    On the right side of the dummy signal detector  301 , the third resistor  316  is coupled to the emitter terminal of the second right transistor  314 . The collector terminal of the second right transistor  314  is coupled to the fourth resistor  318  and to the negative terminal of the voltage source  322 . The base terminal of the second right transistor  314  is also set to the voltage V bias .  
         [0058]    The positive terminal of the voltage source  322  is connected to the first input terminal  210  of the comparator  214 , which is the non-inverted input terminal of the comparator  214  in this embodiment of the present invention. The voltage source  322  is set to the voltage V offset . Setting the base terminals of the second left and right transistors  312 ,  314  to the voltage V bias  means that the voltage (V ref −V offset ) is equal to what the voltage V active  would be if the voltages V in1  and V in2  had an amplitude of zero volts. This means that the voltage V offset  ultimately controls the voltage V active . In other words, if the voltage V offset  is increased, the feedback loop formed by the signal strength detector  200  will operate to increase the voltage V active  so that it equals the voltage V offset  without making any other changes to the configuration of the signal strength detector  200 . Similarly, if the voltage V offset  is decreased, the feedback loop formed by the signal strength detector  200  will operate to decrease the voltage V active  so that it equals the voltage V offset  without making any other changes to the configuration of the signal strength detector  200 .  
         [0059]    So as shown in FIG. 3A and described in the preceding paragraphs, the active signal detector  300  and the dummy signal detector  301  preferably include an identical set of components—with the exception of the voltage source  322  included in the dummy signal detector. Another distinction is that the transistors  312 ,  314  of the dummy signal detector  301  receive just a bias voltage at their respective base terminals while the transistors  302 ,  304  of the active signal detector  300  receive this bias voltage adjusted by the voltages V in1 *V c  and V in2 *V c , respectively.  
         [0060]    Operation of the First Exemplary Embodiment of the Signal Strength Detector  
         [0061]    The voltage V out1  over time is shown in FIG. 3B as a solid line. As shown in FIG. 3B, the voltage V out1  fluctuates between a maximum voltage of (V bias +MΔ′* V c ) and a minimum voltage of (V bias −MΔ′*V c ). The voltage V out2  over time is shown in FIG. 3C as a solid line. As shown in FIG. 3C, the voltage V out2  fluctuates between a maximum voltage of (V bias +MΔ+*V c ) and a minimum voltage of (V bias −MΔ′* V c ). The voltages V out1  and V out2 , therefore, are nominally equal in amplitude, but 180 degrees out of phase.  
         [0062]    For the purpose of describing the present invention, the offset voltage V BE  of the first left and right transistors  302 ,  304  is assumed to be 0.7V, which is a typical offset voltage for a BJT transistor. Further, the two transistor configurations illustrated in FIG. 3A are emitter-coupled configurations. This means that for a given set of transistors, the voltage at the respective emitter terminals is approximately 0.7V less than the voltage at the base terminal of the transistor with the greatest base terminal voltage when little or no current flows through the other transistor.  
         [0063]    Consider the following example: V out1  and V out2  alternates between 3V and 1V. When V out1  equals 3V and V out2  equals 1V, the voltage at the emitter terminals of the first left and right transistors  302 ,  304  or across the first resistor  306  is approximately equal to 2.3V. This voltage is greater than the voltage V out2 , so the first right transistor  304  is turned off and effectively an open circuit. Conversely, when V out1  equals 1V and V out2  equals 3V, the voltage at the emitter terminals of the first left and right transistors  302 ,  304  or across the first resistor  306  is again approximately equal to 2.3V. This voltage is greater than the voltage V out1 , so the first left transistor  304  is turned off and effectively an open circuit. And because of the preferred speed of the feed-back loop formed by the signal strength detector  200 , one or the other of the voltages V out1  or V out2  is always approximately equal to 3V. As a result, the first left and right transistors exhibit the desired switch-like behavior.  
         [0064]    So as the voltage V out1  switches from a minimum voltage (V bias −MΔ′*V c ) to a maximum voltage (V bias +MΔ′*V c ), the first left transistor  302  turns on, and then the current that may flow through the collector and emitter terminals of the first left transistor  302  increases exponentially. Conversely, as the voltage V out1  switches from the maximum voltage (V bias +MΔ′*V c ) to the minimum voltage (V bias −MΔ′* V c ), the current that may flow through the collector and emitter terminals of the first left transistor  302  decreases exponentially, and then the first left transistor  302  turns off.  
         [0065]    Similarly, as the voltage V out2  switches from a minimum voltage (V bias −MΔ′* V c ) to a maximum voltage (V bias +MΔ′*V c ), the first right transistor  304  turns on, and then the current that may flow through the collector and emitter terminals of the first right transistor  304  increases exponentially. Conversely, as the voltage V out2  switches from the maximum voltage (V bias +MΔ′*V c ) to the minimum voltage (V bias −MΔ′*V c ), the current that may flow through the collector and emitter terminals of the first right transistor  304  decreases exponentially, and then the first right transistor  304  turns off.  
         [0066]    And as indicated above, when the voltages V out1  and V out2 , respectively, are at the maximum voltage (V bias +MΔ′*V c ), the voltage across the first resistor  306  (i.e., the voltage equal to I R1 *R1) is equal to (V bias +MΔ′*V c −V BE ). More specifically, when the voltages V out1  and V out2 , respectively, are at the maximum voltage (V bias +MΔ′*V c ), either the first left transistor  302  or the first right transistor  304  permits at least enough current to flow through the first resistor  306  so that the current I R1  is equal to (V bias +MΔ′*V c −V BE )/R1.  
         [0067]    The voltage across the first resistor  306  over time is shown in FIGS. 3B and 3C as a dashed line. Because one or the other of the voltages V out1  and V out2  are equal to (V bias +MΔ′*V c ), the voltage across the first resistor  306  is always approximately equal to (V bias +MΔ′*V c −V BE ) as illustrated in FIG. 3D.  
         [0068]    Another assumption made for the purpose of describing the present invention, is that the current I R1  is substantially equal to the current I R2 , which flows through the second resistor  308 . The current that flows through the respective emitter terminals of the first left and right transistors  302 ,  304 , therefore, is equal to the current that flows through the respective collector terminals of the first left and right transistors  302 ,  304 . In other words, the currents flowing through the base terminals of the first left and right transistors  302 ,  304 , respectively, is assumed to be zero amperes.  
         [0069]    So the current I R2  is also equal to (V bias +MΔ′*V c −V BE )/R1. The voltage V R2  across the second resistor  308  is, therefore, equal to ((V bias +MΔ′*V c −V BE )/R1)*R2. Therefore, the voltage V active  is equal to (V cc −V R2 ), which is equal to (V cc −((V bias +MΔ′*V c −V BE )/R1)*R2) as illustrated in FIG. 3E.  
         [0070]    As stated above, the dummy signal detector  301  preferably includes all of the components found in the active signal detector  300  plus the voltage source  322 . And in the course of operation, the respective base terminals of the second left and right transistors  312 ,  314  of the dummy signal detector  301  are set to the voltage V bias . The result is that the voltage at the collector terminals of the second left and right transistors  312 ,  314  is equal to (V ref −V offset ), which as noted above is what V active  would be equal to if the voltages V in1  and V in2  had a zero volt amplitude.  
         [0071]    And as also described above, the voltage V ref  is applied to the non-inverted input of the comparator  214  and the voltage V active  is applied to the inverted input of the comparator  214 , which produces a voltage V c  that represents a difference between the voltage V active  and the voltage V ref . This voltage V c  is transmitted through the control signal line  216  to the multiplier  204  to control the multiplication factor of the multiplier  204 . The multiplier  204  amplifies the voltages V in1  and V in2  by a factor proportional to the voltage V c .  
         [0072]    Second Exemplary Embodiment of the Signal Strength Detector  
         [0073]    [0073]FIG. 4A illustrates a second exemplary embodiment of the signal strength detector  200 . In this embodiment, the multiplier input line  202  includes one lead in order to transmit one of the differential signals  120  (i.e., the voltage V in ) from the first stage circuit  118  to the multiplier  204 . Similarly, the multiplier output line  206  includes one lead in order to transmit the voltage V out , which is one of the differential signals  120  following an amplitude adjustment and DC voltage offset by the multiplier  204 , to the detector circuitry  208 .  
         [0074]    Further, the detector circuitry  208  includes an active signal detector  400  and a dummy signal detector  401 . The active signal detector  400 , which receives the voltage V out , produces the voltage V active  and the dummy signal detector  401  produces the voltage V ref .  
         [0075]    As shown in FIG. 4A, the active signal detector  400 , includes a capacitor  402  with capacitance value C1, a diode  404 , a resistor  406  with resistance value R1, a direct power supply V cc    410 , and a voltage source  410 . The capacitor  402  is coupled to the multiplier  204  on one side and to the diode  404 , the resistor  406 , and the negative terminal of the voltage source  410  on the other side. The diode  404  is also coupled to circuit ground (or other fixed potential circuit node) and the resistor  406  is also coupled to the direct power supply V cc    410 . The positive terminal of the voltage source  410  is coupled to the second input terminal  212  of the comparator  214 , which is the non-inverted input terminal of the comparator  214  in this embodiment of the present invention since V active  decreases when V out  increases.  
         [0076]    The dummy signal detector  401 , includes a diode  414 , a resistor  416  with resistance value R1, and a direct power supply V cc    418 . And as shown in FIG. 4A, the configuration of the components is similar to that of the active signal detector  400 . The dummy signal detector  401 , however, does not include a capacitor or a voltage source so the diode  414  and the resistor  416  are connected to first input terminal  210  of the comparator  214 , which is the inverted input terminal of the comparator  214  in this embodiment of the present invention. Additionally, the dummy signal detector  414  does not receive an input voltage such as V bias  or V out .  
         [0077]    Operation of the Second Exemplary Embodiment of the Signal Strength Detector  
         [0078]    In the course of the operation of the active signal detector  400 , the capacitor  402  receives a charge from the voltage V out . The voltage V out  as illustrated in FIG. 4B fluctuates between a maximum voltage of (V bias +MΔ′*V c ) and a minimum voltage of (V bias −MΔ′*V c ). When the voltage V out  is at a maximum voltage of (V bias +MΔ′*V c ), the voltage across the diode  404  (i.e., V active −V offset ) is approximately equal to 0.6V, which is the approximate maximum voltage that can be held across a diode. The capacitor  402 , therefore, charges to approximately (V bias +MΔ′*V c −0.6V).  
         [0079]    Because a capacitor is able to hold a charge, the voltage across the capacitor remains at approximately (V bias +MΔ′*V c −0.6V) even while the voltage V out  falls to the minimum voltage (V bias −MΔ′*V c ). As such, the voltage across the diode  404  (i.e., V active −V offset ) correspondingly falls to approximately (0.6V−2*MΔ′*V c ). The voltage across the diode  404 , therefore, varies between 0.6V and (0.6V −2*MΔ′*V c ) as illustrated in FIG. 4C. And with the voltage source  410 , the voltage V active  varies between (V offset +0.6V) and (V offset +0.6V−2*MΔ′*V c ) as illustrated in FIG. 4D.  
         [0080]    The comparator  214 , however, is preferably not fast enough to keep up with the changes to the voltage V active . Instead, the effective value of the voltage V active  from the perspective of the comparator  214  is the average value of the actual voltage V active , which is (V offset +0.6V+V offset +0.6V−2*MΔ′*V c )/2 or (V offset +0.6V−MΔ′*V c ).  
         [0081]    In the course of the operation of the dummy signal detector  401 , the voltage V ref  is always equal to the maximum positive voltage across the diode  414 , which is approximately 0.6V. The comparator  214 , therefore, adjusts the voltage V c  to drive the voltage MΔ′*V c to be equal to the voltage V offset  so that the average value of the voltage V active  (i.e., V offset +0.6V−MΔ′*V c ) is equal to V ref  (i.e., 0.6V).  
         [0082]    And because the relationship between the voltages V in , V c , and V bias  is known, the voltage V offset  is known, and the voltage V c  is measurable, the voltage V in  can be determined by measuring the voltage V c . And as stated above, V in  is one of the differential signals  120  and thus equal in amplitude to 2MΔ′. The signal strength 2Δ of the light signal  104  may be derived from the voltage V in , by first determining the signal strength 2Δ′ of the electrical signal  114  using the amplification factor M of the first stage circuit  118  and then determining the signal strength 2Δ of the light signal  104  using the scaling or loss factors of the photo diode  112 .  
         [0083]    Third Exemplary Embodiment of the Signal Strength Detector  
         [0084]    [0084]FIG. 5A illustrates a third exemplary embodiment of the signal strength detector  200 . In this embodiment, the multiplier input line  202  includes one lead in order to transmit one of the differential signals  120  (i.e., the voltage V in ) from the first stage circuit  118  to the multiplier  204 . Similarly, the multiplier output line  206  includes one lead in order to transmit the voltage V out , which is one of the differential signals  120  following an amplitude adjustment by the multiplier  204 , to the detector circuitry  208 .  
         [0085]    Further, the detector circuitry  208  includes an active signal detector  500  and a dummy signal detector  501 . The active signal detector  500 , which receives the voltage V out , produces the voltage V active  and the dummy signal detector  401 , which receives the voltage V bias , produces the voltage V ref .  
         [0086]    As shown in FIG. 5A, the active signal detector  500 , includes a capacitor  502  with capacitance value C1, a diode  504 , and a resistor  506  with resistance value R1. The capacitor  502  and the resistor  506  are coupled in parallel to circuit ground at one junction and, at the other junction, to the cathode of the diode  504  and the second input terminal  212  of the comparator  214 , which is the inverted input terminal of the comparator  214  in this embodiment of the present invention since V active  increases when V out  increases. The anode of the diode  504  is coupled to the multiplier  204  via the multiplier output line  206 .  
         [0087]    As shown in FIG. 5A, the dummy signal detector  501 , includes a capacitor  512  with capacitance value C1, a diode  514 , a resistor  516  with resistance value R1, and a voltage source  518 . The capacitor  502  and the resistor  506  are coupled in parallel to circuit ground and to the cathode of the diode  504  and the negative terminal of the voltage source  518 . The anode of the diode  504  is set to the voltage V bias  and the positive terminal of the voltage source  518  is coupled to the first input terminal  210  of the comparator  214 , which is the non-inverted input terminal of the comparator  214 .  
         [0088]    The dummy signal detector  501  is identical to the active signal detector  500  in terms of components and layout with the following exceptions: the cathode of the diode  514  is set to V bias  instead of V out  and the voltage source  518  offsets the voltage across the capacitor  512  and the resistor  516  (i.e., V ref −V offset ) to produce the voltage V ref .  
         [0089]    Operation of the Third Exemplary Embodiment of the Signal Strength Detector  
         [0090]    In the course of the operation of the active signal detector  500 , the voltage V out  is equal to (V bias ±MΔ′*V c ) as illustrated in FIG. 5B. When the voltage V out  is at a maximum voltage (V bias +MΔ′*V c ), the voltage across the diode  504  is approximately equal to 0.6V, which is approximately the maximum voltage that can be held across a diode. The voltage across the capacitor  502 , V active , therefore, charges to approximately (V bias +MΔ′*V c −0.6V). And because the voltage across a capacitor can not change instantaneously, the voltage V active  remains at approximately (V bias +MΔ′*V c −0.6V), even while the voltage V out  falls to the minimum voltage (V bias −MΔ′*V c ). As such, the voltage across the diode  404  correspondingly falls to approximately (0.6V−2*MΔ′*V c ).  
         [0091]    In the course of the operation of the dummy signal detector  501 , the voltage (V ref −V offset ) (i.e., the voltage across the capacitor  512  and the resistor  516 ) is equal to the voltage V bias  minus the maximum positive voltage across the diode  414 , which is approximately 0.6V. So with the voltage source  518 , the voltage V ref  is equal to (V offset +V bias −0.6V).  
         [0092]    As noted above, the feed-back loop formed by the signal detector circuit  200  forces the voltage V active  to be substantially equal to the voltage V ref . And based on the equations derived in the two preceding paragraphs, the difference between the voltage V ref  (i.e., the voltage (V offset +V bias −0.6V)) and the voltage V active  (i.e., the voltage (V bias +MΔ′*V c −0.6V)) is V offset  and MΔ′*V c . So more specifically then, the feed-back loop formed by the signal detector circuit  200  forces the voltage MΔ′*V c  to be substantially equal the voltage V offset . The voltage V offset  is chosen so that the detector circuitry  208  does not exhibit a loss of gain—as it would without the voltage source  518 .  
         [0093]    Because the relationship between the voltages V in , V bias , and V c  is known, the voltage V offset  is known, the voltage V bias  is known, and the voltage V c  is measurable, the peak-to-peak amplitude of the voltage V in  can be determined by measuring the voltage V c . And as stated above, V in  is one of the differential signals  120  and thus equal in amplitude to 2MΔ′. The signal strength 2Δ of the light signal  104  may be derived from the voltage V in , by first determining the signal strength 2Δ′ of the electrical signal  114  using the amplification factor M of the first stage circuit  118  and then determining the signal strength 2Δ of the light signal  104  using the scaling or loss factors of the photo diode  112 .  
         [0094]    While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art having the benefit of this disclosure without departing from the inventive concepts described herein.