Abstract:
In the field of step-down voltage conversion, it is known to regulate an output of a DC-DC converter circuit with both a Pulse Wave Modulation voltage signal or a Pulse Frequency Modulation voltage signal, depending upon a current demand made upon the DC-DC converter circuit. Typically, circuits to generate both voltage signals are provided and selection of the appropriate regulation mode is achieved by means of a pin and decision software controlling the pin. However, the use of the pin and the software is an overhead that is desirably avoided. Consequently, the present invention provides a voltage conversion apparatus comprising a signal analyzer to analyze a load current signal and compare a characteristic of the load current signal to at least one predetermined criterion. Regulation by the PWM signal or the PFM signal is selected in response to the evaluation of the comparison with the at least one criterion.

Description:
FIELD OF THE INVENTION 
     This invention relates to a voltage converter apparatus of the type, for example, that converts an input voltage to an output voltage, the output voltage being lower than the input voltage. This invention also relates to a method of voltage conversion. 
     BACKGROUND OF THE INVENTION 
     It is known to equip electronic devices with so-called step-down voltage converters. Particularly, but not exclusively, in relation to portable electronic devices, the provision of the step-down converters serves to improve efficiency of an electronic system employed by the device, thereby increasing cycle time of a battery used by the device. 
     However, some electronic devices have a number of modes of operation, each mode having different power consumption requirements, for example, a radio-frequency communications apparatus can have an active mode and a standby mode, each mode having a distinctive loading regime. Also, it has been recognised that inefficiencies arise when a single voltage regulation scheme is employed to satisfy current demands associated with the different power consumption requirements. In this respect, a pulse frequency modulation scheme is preferable for low power demand modes and a pulse width modulation scheme is preferable for higher power demand modes to maintain maximum battery lifetime. Consequently, known step-down voltage conversion circuitry typically employs a first pulse frequency modulation circuit and a second pulse width modulation circuit to control an output power signal, the first circuit being selectable in preference to the second circuit and vice versa in response to a software-controlled “pin”, such as a terminal of an integrated circuit. The software determines the mode of operation of the device and sends a control signal to the pin to select the first or second circuit to control the output power signal. 
     However, the provision of the control pin and the software adds a level of complexity, and hence an overhead, to the step-down voltage converter that is desirable to be avoided. 
     STATEMENT OF INVENTION 
     According to the present invention, there is provided a voltage converter apparatus and a method of voltage conversion as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       At least one embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: 
         FIG. 1  is a schematic diagram of an apparatus constituting an embodiment of the invention; 
         FIG. 2  is a flow diagram of a method for use with the apparatus of  FIG. 1 ; 
         FIG. 3A  is a graph of regulation voltage signal against time generated by a first operational unit of the apparatus of  FIG. 1 ; 
         FIG. 3B  is a graph of a load current signal associated with the regulation voltage signal of  FIG. 3A ; 
         FIG. 4A  is a graphs of regulation voltage signal against time generated by a second operational unit of the apparatus of  FIG. 1 ; and 
         FIG. 4B  is a graph of a load current signal associated with the regulation voltage signal of  FIG. 4A . 
     
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Throughout the following description identical reference numerals will be used to identify like parts. 
     Referring to  FIG. 1 , a voltage converter apparatus  100  comprising a step-down voltage conversion circuit  102  coupled to a first power regulation circuit  104  having a first control output terminal  106  coupled to a first control input terminal  108  of the conversion circuit  102  via a first switching device  110 . A second control output  112  is coupled to a second control input  114  via a second switching device  116 . 
     A second power regulation circuit  118  is also provided and comprises a third control output terminal  120  coupled to the first control input terminal  108  of the conversion circuit  102  via the first switching device  110 . The second power regulation circuit  118  also comprises a fourth control output terminal  122  coupled to the second control input terminal  114  via the second switching device  116 . 
     The conversion circuit  102  is a so-called “Buck converter”, a DC-DC step-down voltage converter comprising an inductor, a capacitor, input terminals and output terminals, as well as a first switch and a second switch, such as a first Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a second MOSFET. Since the detailed structure of the Buck converter is known in the art, no further details will be described herein for the sake of conciseness and clarity of description. 
     In this example, the first power regulation circuit  104  is a Pulse Width Modulation (PWM) signal generation circuit capable of generating a first drive signal at the first control output terminal  108  and a second drive terminal at the second control output terminal  112 . The first and second drive signals serve to regulate an output signal at an output terminal  124  of the conversion circuit  102  in accordance with a PWM scheme. In this respect, the first and second drive signals constitute a PWM regulation signal. More specifically, the PWM signal generation circuit is in a Discontinuous Current Mode (DCM). To enable the first power regulation circuit  104  to control the output signal, the first power regulation circuit  104  comprises a number of input terminals  105  for receiving control signals. In contrast, the second power regulation circuit  118  is a Pulse Frequency Modulation (PFM) circuit capable of generating a third drive signal at the third control output terminal  120  and a fourth drive signal at a fourth control output terminal  122 . The third and fourth drive signals serve to regulate the output signal at the output terminal  124  in accordance with a PFM scheme. In this respect, the first and second drive signals constitute a PFM regulation signal. To enable the second power regulation circuit  118  to control the output signal, the second power regulation circuit  118  comprises a number of input terminals  119  for receiving control signals. Since circuits of these types are known in the art relating to regulation of DC-DC conversion circuits, the power regulation circuits  104 ,  118  will not be described in any further detail herein for the sake of conciseness and clarity of description. 
     In order to control the first and second switching devices  110 ,  116 , a control circuit  126  is provided. A fifth control output terminal  128  of the control circuit  126  is coupled to an input (not shown) of the first switching device  110  to control activation thereof and a sixth control output terminal  130  of the control circuit  126  is coupled to an input (not shown) of the second switching device  116  to control activation thereof. 
     In order to control application of the first and second drive signals and the third and fourth drive signals generated by the first and second power regulation circuits  104 ,  118 , the control circuit  126  comprises a number of input terminals  132 . 
     In operation ( FIG. 2 ), the control circuit  126  is arranged to analyse a load current signal with respect to other parameters in order to determine whether the converter apparatus  100  should be in a PWM regulation mode or a PFM regulation mode. In the PWM regulation mode, generation of the output signal by the conversion circuit  102  is controlled by the PWM regulation signal of the first power regulation circuit  104 , and in the PFM regulation mode, generation of the output signal by the conversion circuit  102  is controlled by the PFM regulation signal of the second power regulation circuit  104 . 
     Prior to making the above-described determination, the control circuit  126  first initialises (Step  200 ) the first and second switching devices  110 ,  116  into a state whereby the first and second control output terminals  106 ,  112  are respectively coupled to the first and second control input terminals  108 ,  114  of the conversion circuit  102 . Consequently, the PWM regulation signal, applied through the first and second drive signal, controls the output signal generated by the conversion circuit  102 . The control circuit  126  then, as a matter of course, determines (Step  202 ) whether the converter apparatus  100  is in a PWM regulation mode. 
     Since the converter apparatus  100  has just been initialised into the PWM regulation mode, the control circuit  126  proceeds to determine whether the demand on the load current is sufficiently low to merit PFM regulation of the output signal in place of PWM regulation thereof. Consequently, the control circuit  126  measures, as a proportion of an overall period of the load current signal, a first upwardly ramping part, D 1 , of the load current signal  302  ( FIG. 3A ). The load current signal can be obtained, for example, by calculating an average current flowing through the inductor (not shown) of the conversion circuit  102  using a priori knowledge of the average values of salient components forming the conversion circuit  102  and knowledge of the PWM regulation signal. In this respect, referring to  FIG. 3A , a switching point voltage, V SP , at a switching node of the conversion circuit  102  varies with time in accordance with the PWM regulation signal to form a switching point voltage signal  300 . Turning to  FIG. 3B , the calculated load current signal  302  is in synchronism with the switching point voltage signal  300 . 
     The control circuit  126  also measures, as a proportion of the overall period of the load current signal, a second and subsequent downwardly ramping part, D 2 , of the load current signal  302 , the upwardly and downwardly ramping parts of the load current signal  302  in practice being induced, in this example, through application of the PWM regulation signal. During a period of the PWM regulation signal, a remaining part of the load current signal  302  is substantially zero, corresponding to, for example, a depletion time  304  of the inductor mentioned above. In order to determine when, in the period of the load current signal  302 , i.e. in time, the second downwardly ramping part, D 2 , of the load current signal  302  terminates (and the depletion time begins), the sum of the measured proportions that the first and second parts, D 1  and D 2 , of the load current signal  302  constitute are multiplied by the period of the PWM voltage signal, Tpwm, to yield a load current pulse time (D 1 +D 2 )Tpwm. Thereafter, the load current pulse time is compared with a predetermined criterion, in this example, a threshold value. The threshold value is, in this example, a percentage of the period of the load current signal  300 , such as 75%. Consequently, the control circuit  126  determines (Step  204 ) whether the duration of the load current pulse time is less than the temporal equivalent of the 75% threshold value (Th 1 Tpwm). If the load current pulse time is greater than the 75% threshold, then a sufficiently large current demand is deemed to be being made by a load (not shown) to make operation of the converter apparatus  100  in the PWM regulation mode appropriate. Consequently, a debounce counter, C debounce , is reset (Step  206 ) and the control circuit  126  continues analysing the load current signal as already described above until the load current pulse time is found to be less than the 75% threshold value. When the load current pulse time is found to be less than the 75% threshold value, the debounce counter, C debounce , is incremented (Step  208 ) by unity and the control circuit  126  verifies whether or not (Step  210 ) the debounce counter, C debounce , has exceeded an overflow limit, for example, six. The debounce counter, C debounce , is provided as a way of verifying that the load current pulse time is consistently less than the threshold value. Therefore, the control circuit  126  continues analysing the load current signal  302  as already described above until the load current pulse time is found to be less than the 75% threshold value on six consecutive occasions. When the load current pulse time is found (Step  210 ) to be consistently less than the 75% threshold value, the debounce counter, C debounce , is reset (Step  212 ) and the control circuit  126  is set (Step  214 ) to the PFM regulation mode  214 . The control circuit  126  then sets the first and second switching devices  110 ,  116  so that the second power regulation circuit  118  is coupled to the conversion circuit  102 , thereby causing the output signal to be regulated by the third and fourth drive signals applying the PFM regulation signal. Thereafter, the control circuit  126  returns to determining (Step  202 ) whether the converter apparatus  100  is in the PWM regulation mode. 
     Since the control circuit  126  has now set the converter apparatus  126  to the PFM regulation mode, the control circuit  126  determines (Step  202 ) that the converter apparatus  100  is not in the PWM regulation mode and proceeds to determine whether the load current demand is sufficiently high to merit PWM regulation of the output signal in place of PFM regulation thereof. 
     Consequently, the control circuit  126  measures a PFM switching period, Tpfm, for the load current signal  302  ( FIG. 3B ) and compares the PFM switching period with another predetermined criterion, for example, a threshold value. In the present example, the threshold value is a predetermined time period, Th 2 , the PFM switching period being less than the predetermined time period being indicative that a sufficiently large load current demand is being made to merit the use of PWM regulation. In this respect, the PFM switching period is measured against the predetermined time period, Th 2 , such as 30 μs. If the control circuit  126  determines (Step  216 ) that the predetermined time period is less than the PFM switching period, Tpfm, the control circuit  126  resets (Step  206 ) the debounce counter, C debounce , and then continues to analyse the load current signal as already described above until the predetermined time period is found (Step  216 ) to be greater than the PFM switching period, Tpfm. When the predetermined time period is found to be greater than the PFM switching period, Tpfm, the debounce counter, C debounce , is incremented (Step  220 ) by unity and the control circuit  126  verifies whether or not (Step  222 ) the debounce counter, C debounce , has exceeded the overflow limit, for example, six. Again, the debounce counter, C debounce , is provided as a way of verifying that the predetermined time period is consistently greater than the PFM switching period, Tpfm. Therefore, the control circuit  126  continues analysing the load current signal  302  as already described above until the predetermined time period is found to be greater than the PFM switching period, Tpfm, on six consecutive occasions. When the predetermined time period is found (Step  210 ) to be consistently greater than the PFM switching period, Tpfm, the debounce counter, C debounce , is reset (Step  224 ) and the control circuit  126  is set (Step  226 ) to the PWM regulation mode  214 . The control circuit  126  then sets the first and second switching devices  110 ,  116  so that the first power regulation circuit  118  is coupled to the conversion circuit  102 , thereby causing the output signal to be regulated by the first and second drive signals applying the PWM regulation signal. Thereafter, the control circuit  126  returns to determining (Step  202 ) whether the converter apparatus  100  is in the PWM regulation mode. 
     Of course, the load current pulse time and the percentage threshold value respectively correspond to a first loading current threshold, I loadmin(pwm) , and a second loading current threshold, I loadmax(pfm) , associated with a need for the output signal to be regulated by the PWM regulation signal or the PFM regulation signal. The first loading current threshold, I loadmin(pwm) , and the second loading current threshold, I loadmax(pfm) , are respectively set so that they do not overlap, for different possible tolerances of the devices forming the conversion circuit  102  and possible variances in an input voltage to the conversion circuit  102 , in order to provide stable transitions between the PWM regulation mode and the PFM regulation mode in a hysteretic manner. 
     The above process is then repeated, the converter apparatus  100  switching between the PWM regulation mode and the PFM regulation mode in response to the demand for load current. In this example, the converter apparatus  100  is provided in a portable communications device, such as a cellular telephone handset. However, it should be appreciated that other electronic devices can also make use of the converter apparatus  100  descried herein. In any event, the switching of the converter apparatus  100  between PWM and PFM switching modes preserves the cycle time of a battery used by the portable communications device. 
     Since the above-described converter apparatus  100  is usually part of a highly sophisticated digital system, for example the portable communications device mentioned above, high-frequency clock signals are available for determining the above described inequalities (Steps  204 ,  216 ), although dedicated clock-generation circuits can be provided. The clock signals are several multiples of the PWM and PFM periods and so the clock signals can be used to trigger counters, evaluation of the above described inequalities (Steps  204 ,  216 ) being by way of a counter-based measurement system. 
     It is thus possible to provide a voltage converter apparatus and a method therefor capable of automatically selecting one of the regulation modes for a step-down converter in response to current load demand. The need for a control pin and associated control software, an overhead, is thereby obviated.