Abstract:
A photo-mask used for fabricating a photoresist pattern in process of fabricating an array substrate for a liquid crystal display device comprises a transmissive area having a first transmittance; a blocking area having a second transmittance; a first half-transmissive area including at least one coating layer and having a third transmittance; a second half-transmissive area including a plurality of bars and having a fourth transmittance, the bars having spaces therebetween, wherein the third and fourth transmittances are less than the first transmittance and greater than the second transmittance, respectively, and the third transmittance is greater than the fourth transmittance.

Description:
The present application claims the benefit of Korean Patent Application No. 2005-0126809 filed in Korea on Dec. 21, 2005, which is hereby incorporated by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to a liquid crystal display device, and more particularly, to a photo mask and a method of fabricating an array substrate for a liquid crystal display device using the same. 
     BACKGROUND 
     Since liquid crystal display (LCD) devices have low power consumption and a high mobility, they have been touted as the next generation display device. Among LCD devices, active matrix type LCD devices, which have high resolution and are effective at displaying moving images, are widely used. 
     In general, LCD devices are fabricated through an array substrate process, a color filter substrate process, and a cell process. In the array substrate process, a thin film transistor (TFT) and a pixel electrode may be formed on a first substrate. In the color filter substrate process, a color filter and a common electrode may be formed on a second substrate. In the cell process, a liquid crystal layer is formed between the first and second substrates. 
     An LCD device is shown in detail in  FIG. 1A .  FIG. 1A  is an exploded perspective view of a conventional LCD device. As shown, the first and, second substrates  12  and  22  face each other, and the liquid crystal layer  30  is interposed therebetween. The first substrate  12  includes a plurality of gate lines  14 , a plurality of data lines  16 , a plurality of TFTs (“Tr”), a plurality of pixel electrodes  18 , and so on. The gate line  14  and the data line  16  cross each other such that a region formed between the gate and data lines  14  and  16  is defined as a pixel region (“P”). The TFT “Tr” is formed at a crossing portion between the gate and data lines  14  and  16 , and the pixel electrode  18  is formed in the pixel region “P” and connected to the TFT “Tr.” 
     The second substrate  22  includes a black matrix  25 , the color filter  26 , and the common electrode  28 , and so on. The black matrix  25  has a lattice shape to cover a non-display region, such as the gate line  14 , the data line  16 , the TFT “Tr,” and so on. The color filter  26  is formed within the black matrix  25  and corresponds to the pixel region “P.” The color filter  26  includes red, green, and blue colors. The common electrode  28  is formed on the black matrix  25  and the color filter  26  over an entire surface of the second substrate  22 . The common electrode  28  may be made of transparent material. 
     Though not shown, a sealant is formed between edges of the first and second substrates  12  and  22 . First and second alignment layers may be formed between the first substrate  12  and the liquid crystal layer  30  and between the second substrate  22  and the liquid crystal layer  30 , and a polarizing plate may be formed on an outer surface of the first substrate  12  or the second substrate  22 . Also, a backlight assembly below the first substrate  12  supplies light into the liquid crystal layer  30 . The liquid crystal layer  30  is driven by an electric field between the pixel electrode  18  and the common electrode  28  such that the LCD device displays images. 
     In a conventional method of fabricating the LCD device, and more particularly, in a method of fabricating the array substrate, a mask process is used for patterning the data and gate lines, the pixel electrode, and so on. Since the mask process includes many steps, such as a step of coating a photoresist, a step of developing, a step of etching, a step of stripping, and so on, a production time increases and production yield decreases. Accordingly, a new method of fabricating the array substrate for the LCD device, referred to as  4  mask process, has been suggested to resolve these problems. The conventional method of fabricating the array substrate includes  5  mask processes. 
       FIGS. 2A to 2C  show cross-sectional views of processes of fabricating the pixel region of the array substrate using the  4  mask process. 
     As shown in  FIG. 2A , a gate electrode  55 , the gate line (not shown), a gate insulating layer  57 , the data line  65 , an active layer  60   a  of intrinsic amorphous silicon, an ohmic contact pattern  61  of impurity-doped amorphous silicon, a source-drain pattern  66 , a passivation layer  75 , and a transparent conductive material layer  78  are formed on the first substrate  50 . 
     The gate electrode  55  and the gate line (not shown) are formed on the first substrate  50  in the switching region TrA by depositing and patterning a first metal layer (not shown) using a first mask (not shown). The gate electrode  55  may be extended and may protrude from the gate line (not shown). The gate insulating layer  57  is formed on the first substrate including the gate electrode  55  and the gate line (not shown). Though not shown, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer, and a second metal layer are formed on the gate insulating layer  57 . And then, the active layer  60   a , the ohmic contact pattern  61 , and the source-drain pattern  66  are formed by sequentially patterning the intrinsic amorphous silicon layer, the impurity-doped amorphous silicon layer, and the second metal layer using a second mask (not shown). At the same time, the data line  65  is formed from the second metal layer. The gate insulating layer  57 , an intrinsic amorphous silicon pattern  62   a , and an impurity-doped amorphous silicon pattern  62   b  are formed between the data line  65  and the first substrate  50 . 
     Next, the passivation layer  75  having a drain contact hole  76  is formed on the source-drain pattern  66  by depositing and patterning an inorganic material layer (not shown) by using a third mask (not shown). The drain contact hole  76  partially exposes the source-drain pattern  66 . The transparent conductive material layer  78  is formed on the passivation layer  75  and contacts the source-drain pattern  66  through the drain contact hole  76 . Then, a photoresist (PR) layer  85  having a first height h 1  from the first substrate  50  is formed on the transparent conductive metal layer  78 , and a fourth mask  91  is disposed over the PR layer  85 . The fourth mask  91  has a transmissive area “TA,” a blocking area “BA,” and a half-transmissive area “HTA.” The half-transmissive area “HTA” has a transmittance less than the transmissive area TA and greater than the blocking area “BA.” Then, the PR layer  85  is exposed by light through the fourth mask  91 . 
     As shown in  FIG. 2B , first and second PR patterns  85   a  and  85   b  are formed on the transparent conductive metal pattern  78  by developing the PR layer  85 . The first PR pattern  85   a  corresponds to the blocking area BA to have the first height hi from the first substrate  50 , and the second PR pattern  85   b  corresponds to the half-transmissive area “HTA” to have the second height h 2  from the first substrate  50 , which is less than the first height h 1 . The PR layer  85  corresponding to the transmissive area TA is completely removed such that the transparent conductive material pattern  78  corresponding to the gate electrode  55  is exposed between the second PR patterns  85   b.    
     Since the transparent conductive material layer  78  has a step difference, the second PR pattern  85   b  has first, second, and third thicknesses t 1 , t 2 , and t 3  from the transparent conductive metal layer  78 . The second thickness t 2  is greater than the first thickness t 1  and less than the third thickness t 3 . The second PR pattern  85   b  in a first region A 1  has the first thickness t 1  due to the highest step from the gate electrode  55 , the active layer  60   a , the ohmic contact pattern  61 , and the source-drain pattern  66 . The second PR pattern  85   b  in a second region A 2  has the second thickness t 2  due to a middle step without the gate electrode  55 , and the second pattern  85   b  in a third region A 3  has the third thickness t 3  due to the lowest step without the gate electrode  55 , the active layer  60   a , the ohmic contact pattern  61 , and the source-drain pattern  66 . 
     As shown in  FIG. 2C , the transparent conductive material layer  78  exposed between the second PR patterns  85   b  is removed. Sequentially, the source-drain pattern  66  and the ohmic contact pattern  61  exposed by removing the transparent conductive material layer  78  are removed such that a source electrode  67 , a drain electrode  69 , and an ohmic contact layer  60   b  are formed. The ohmic contact layer  60   b  and the active layer  60   a  are as a semiconductor layer  60 . Next, the second PR pattern  85   b  is removed from the transparent conductive metal pattern  78  by ashing. At the same time, the first PR pattern  85   a  is partially removed. The ashing should be perfectly performed to expose the transparent conductive metal layer  78  until the second PR pattern  85   b  in the third region A 3  is perfectly removed. 
     In this case, before the ashing is finished, the second PR pattern  85   b  having the first thickness t 1  or/and the second thickness t 2  is exposed. Accordingly, since the ashing time increases as much as an ashing time of different thickness between the first and second thickness t 1  and t 2  or between the second and third thickness t 2  and t 3 , the production time of the array substrate increases. 
     BRIEF SUMMARY 
     Accordingly, the present disclosure is directed to a photo-mask and a method of fabricating an array substrate for an LCD device using the photo-mask that may substantially obviate one or more of the problems due to limitations and disadvantages of the related art. 
     The photo-mask used for fabricating a photoresist pattern in process of fabricating an array substrate for a liquid crystal display device comprises a transmissive area having a first transmittance; a blocking area having a second transmittance; a first half-transmissive area and having a third transmittance; a second half-transmissive area and having a fourth transmittance, wherein the third and fourth transmittances are less than the first transmittance and greater than the second transmittance, respectively, and the third transmittance is greater than the fourth transmittance. 
     In another aspect, a method of fabricating an array substrate for a liquid crystal display device comprises forming a gate line and a gate electrode on a substrate by depositing and patterning a first metal layer; forming a gate insulating layer on the gate line and the gate electrode; forming an active layer, an ohmic contact pattern, source-drain pattern, and a data line by sequentially depositing and patterning an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon pattern, a second metal layer, wherein the active layer, the ohmic contact pattern, and a source-drain pattern corresponds to the gate electrode; forming a passivation layer including a drain contact hole on the source-drain pattern, the drain contact hole exposing a part of the source-drain pattern; forming a transparent conductive metal layer on the passivation layer; forming a photoresist layer on the transparent conductive metal layer; disposing a photo-mask having a transmissive area, a blocking area and first and second half-transmissive areas over the photoresist layer, wherein the first and second half-transmissive areas has transmittances less than the transmissive area and greater than the blocking area, and the first half-transmissive area has the transmittance greater than the second half-transmissive area; forming first, second, and third photoresist patterns from the photoresist layer on the transparent conductive metal layer such that the transparent conductive metal layer corresponding to the gate electrode is exposed by the first, second, and third photoresist patterns,; removing the second and third photoresist patterns from the transparent conductive metal layer by ashing; removing the transparent conductive metal layer exposed by removing the second and third photoresist patterns. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is an exploded perspective view of a conventional LCD device; 
         FIGS. 2A and 2C  are cross-sectional views showing processes of fabricating an array substrate for an LCD device according to the related art; 
         FIG. 3  is a cross-sectional view of a photo-mask according to the present disclosure; and 
         FIGS. 4A to 4H  are cross-sectional views showing processes of fabricating an array substrate for an LCD device using a photo-mask according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the preferred embodiments, examples of which are illustrated in the accompanying drawings. 
       FIG. 3  is a cross-sectional view of a photo-mask that is used for fabricating an array substrate for an LCD device according to the present disclosure. As shown, the photo-mask includes a transmissive area “TA,” a blocking area “BA,” a first half-transmissive area “HTA 1 ,” and a second half-transmissive area “HTA 2 .” The transmissive area TA may have a transmittance of 100 percent, and the blocking area BA may have a transmittance of 0 percent. The first and second half-transmissive areas HTA 1  and HTA 2  each have a different transmittance from the transmissive area TA and the blocking area BA. 
     The first half-transmissive area HTA 1  may have a transmittance of between 50 percent and 60 percent and may be a half-tone type. Alternatively, the first half-transmissive area HTA 2  may be a multi-slit type. The second half-transmissive area HTA 2  may have a transmittance of between 20 percent and 40 percent and may be a multi-slit type. Alternatively, the second half-transmissive area HTA 2  may be a half-tone type. The half-tone type is formed by disposing at least one coating layer  193  on an upper surface or a lower surface of the photo-mask  191 . The coating layer  193  absorbs incident light such that the transmittance of light may be controlled. Accordingly, when the coating layer  193  includes several coating layers or has an increased thickness, the transmittance of, for example, the first half-transmissive area may be less than the first half-transmissive area having a single coating layer. The multi-slit type may be formed by a plurality of bars  195 . The bars  195  include gaps between the bars, and each gap between the bars  195  is defined as a space or slit  194 . Light passes through the slit  194 . preferably, each bar  195  perfectly blocks light and has a predetermined width. The light passing through the slit  194  is diffracted such that the light reaches a region corresponding to the bars  195 . Since the bars  195  absorb light, the transmittance becomes lower with the bars  195  than without the bars  195 . Also, as a distance between the slits  194  becomes more narrow or the bars are increased in width, the transmittance of, for example, the second half-transmissive area HTA 2 , may be reduced. 
     All of the first and second half-transmissive areas may be formed of the coating layer. However, in this case, it may be difficult to appropriately control the thickness of the coating layer. Also, when the first half-transmissive area has a single layer and the second half-transmissive area has multiple layers, the difference in transmission between the first and second half-transmissive areas may be too great. Alternatively, the first and second half-transmissive areas may be formed of the multi-slits by controlling gaps between slits or widths of the bars. In this case, however, the photo-mask may be useful for only the smaller size, not the bigger size. Moreover, when the first and second half-transmissive areas are located adjacent to each other, the slits at a border between the first and second half-transmissive area may be affected by each other. Accordingly, it is preferable that the first half-transmissive area HTA 1  in the present disclosure is made of the half-tone type, and the second half-transmissive area HTA 2  in the present disclosure is made of the multi-slit type. 
       FIGS. 4A to 4G  are cross-sectional views of a fabricating process of a pixel region of an array substrate using the above-mentioned photo-mask. 
     A gate electrode  115  is formed on a substrate  110  by a first mask process as shown in  FIG. 4A . The gate electrode  115  is formed on the substrate  110  in a switching region TrA by depositing and patterning a first metal layer (not shown) using a first mask (not shown). The substrate  110  includes a plurality of pixel regions “P” and a switching region TrA. In more detail, the first metal layer is formed on the substrate  110  by depositing a first metal or metal alloy. A first photoresist (PR) layer (not shown) is formed on the first metal layer, and the first mask having a transmissive area and a blocking area is disposed over the first PR layer. The first PR layer is exposed and developed to form a first PR pattern corresponding a center of the switching region TrA. The first metal layer exposed by the first PR pattern is removed such that the gate electrode  115  is formed on the substrate  110  in the switching region TrA. At the same time, a gate line (not shown) is formed on the substrate  110 . The gate electrode  115  extends from the gate line into a pixel region P. 
     A second mask process is described by  FIG. 4B . A gate insulating layer  124  is formed on the substrate  110  including the gate electrode  115  and the gate line by depositing an inorganic insulating material, such as silicon oxide or silicon nitride. Though not shown, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer, a second metal layer, and a second PR layer are sequentially formed on the gate insulating layer  124 . Then, a second PR pattern  181  is formed on the second metal layer (not shown) by exposing and developing the second PR layer using the second mask (not shown). The second mask has a transmissive area and a blocking area. The second PR pattern  181  corresponds to the switching region TrA and a region in which a data line will be formed. 
     The second metal layer exposed within the second PR pattern  181  is removed, and the impurity-doped amorphous silicon layer below the second metal layer and the intrinsic amorphous silicon layer below the impurity-doped amorphous silicon layer are removed. As a result, a data line  134 , a source-drain pattern  139 , an ohmic contact pattern  130  and an active layer  127  are formed. The intrinsic amorphous silicon pattern  128  has the same material as the active layer  127 , and the impurity-doped amorphous silicon pattern  131  has the same material as the ohmic contact pattern  130  between the substrate  110  and the data line  134 . The second PR pattern  181  is removed from the source-drain pattern  139  and the data line  134 . 
     As shown in  FIG. 4C , a passivation layer  145  is formed on the data line  134  and the source-drain pattern  139  by depositing an inorganic insulating material such as silicon oxide or silicon nitride. Though not shown, a third PR layer is formed on the passivation layer  145 , and a third mask having the transmissive area and the blocking area is disposed over the third PR layer. Then, a third PR pattern  183  is formed on the passivation layer  145  by exposing and developing the third PR layer using the third mask. Also, a drain contact hole  149  exposing a part of the source-drain pattern  139  is formed by removing the passivation layer  145  using the third PR pattern  183  as a mask. The third PR pattern  183  is removed from the passivation layer  145 . 
     As shown in  FIG. 4D , a transparent conductive material layer  158  is formed on the passivation layer  145  by depositing a transparent conductive material such as indium-tin oxide (ITO) or indium-zinc oxide (IZO). The transparent conductive material layer  158  contacts the source-drain pattern  139  through the drain contact hole  149 . A fourth PR layer  185  is formed on the transparent conductive metal layer  158 , and then the photo-mask  191  is disposed over the fourth PR layer  185 . The fourth mask  191  has the transmissive area TA, the blocking area BA, and the first and second half-transmissive areas HTA 1  and HTA 2  as mentioned above. The fourth PR layer  185  is exposed and developed using the photo-mask  191 . As mentioned above, the first and second half-transmissive areas HTA 1  and HTA 2  have transmittances less than the transmissive area TA and greater than the blocking area BA. The first half-transmissive area HTA 1  may have a transmittance of between 50 percent and 60 percent, and the second half-transmissive area HTA 2  may have a transmittance of between 20 percent and 40 percent. The first half-transmissive area HTA 1  is the half-tone type, and the second half-transmissive area HTA 2  is the multi-slit type. 
     The blocking area BA corresponds to the gate electrode  115 , and the transmissive area TA corresponds to a region in which a pixel electrode is to be formed. The first half-transmissive area HTA 1  corresponds to a region “D” and a region “E”. The region “D” corresponds to the source-drain patterns  139  at both sides of the gate electrode  115 . Accordingly, the first half-transmissive area HTA 1  is located at both sides of the blocking area BA. The region “E” corresponds to the data line  134 . The second half-transmissive area HTA 2  corresponds to a region “C” and a region “F”. The second half-transmissive area HTA 2  of the region “F” is located at both sides of the first half-transmissive area HTA 1  of the region “E”. The second half-transmissive area HTA 2  of the region “C” is located at a side of the first half-transmissive area HTA 1  of the region “D”. The second half-transmissive area HTA 2  of the region “C” corresponds to a step resulting from the source-drain pattern  139 . 
     As shown in  FIG. 4E , the fourth PR layer  185  is exposed and developed by using the photo-mask  191  such that three PR patterns, a fourth PR pattern  185   a , a fifth PR pattern  185   b , and a sixth PR pattern  185   c , are formed on the transparent conductive material layer  158 . The transparent conductive material layer  158  corresponding to the blocking area BA is exposed between the three PR patterns  185   a ,  185   b , and  185   c . The fourth PR pattern  185   a  corresponds to the transmissive area TA of the photo-mask  191  and has a first height h 11  from the substrate  110 . The fifth PR pattern  185   b  corresponds to the first half-transmissive area HTA 1  and has a second height h 12  from the substrate  110 . The sixth PR pattern  185   c  corresponds to the second half-transmissive area HTA 2  and has a third height h 13  from the substrate  110 . The fifth and sixth PR patterns  185   b ,  185   c  have different heights from the substrate  110 , and a third thickness t 13  in the region “E” is greater than a first thickness t 11  in the region “D” by an amount corresponding to a thickness of the gate electrode  115 . However, the third thickness t 13  in the region “E” is substantially same as a second thickness t 12  in the region “C” and a fourth thickness t 14  in the region “F”. Accordingly, the fifth and sixth PR patterns  185   b  and  185   c  may be removed at the same time by ashing such that the transparent conductive material layer  158  is exposed. As a result, the present method can decrease a process time of ashing to expose the transparent conductive material layer. 
     In the related art, the PR pattern in the region “C” or the region “F” has the same height as the PR pattern in the region “D” or the region “E”. Accordingly, compared to the related art, the present method requires less ashing time due to the difference between the second and third heights h 12  and h 13 . 
     The transparent conductive material layer  158  exposed between the fourth to sixth PR patterns  185   a ,  185   b ,  185   c  is removed. Sequentially, the passivation layer  145 , the source-drain pattern  139 , and the ohmic contact pattern  130  below the transparent conductive material layer  158  are removed. As a result, ohmic contact layers  130   a  are formed from the ohmic contact pattern  130  on the active layer. The ohmic contact layers  130   a  are spaced apart from each other. The ohmic contact layers  130   a  and the active layer  127  are referred to as a semiconductor layer  132 . Also, source and drain electrodes  136  and  138  spaced apart from each other are formed on the ohmic contact layers  130   a . Accordingly, a thin film transistor (TFT) “Tr” including the gate electrode  115 , the gate insulating layer  124 , the active layer  127 , the ohmic contact layers  130   a , the source electrode  136 , and the drain electrode  138 , is manufactured in the switching region TrA. 
     In this exemplary embodiment, the first half-transmissive area HTA 1  corresponds to the data line  134 . However, the second half-transmissive area HTA 2  may corresponds to the data line  134  in another exemplary embodiment. In this case, a PR pattern corresponding to the data line  134  may have a thickness less than the above-mentioned case. 
     Next, as shown in  FIG. 4F , the fifth and sixth PR patterns  185   b  and  185   c  are removed from the transparent conductive material layer  158  by ashing such that the transparent conductive material layer  158  corresponding to the fifth and sixth PR patterns  185   b  and  185   c  is exposed. Since the fourth PR pattern  185   a  is thicker than the fifth and sixth PR patterns  185   b  and  185   c , the fourth PR pattern  185   a  remains on the transparent conductive metal layer  158 . 
     As shown in  FIG. 4G , the transparent conductive material layer ( 158  of  FIG. 4F ) exposed by the fourth PR pattern  185   a  is removed from the passivation layer  145 . As a result, a pixel electrode  161  is formed from the transparent conductive material layer  158  ( 158  of  FIG. 4F ) on the passivation layer  145  in the pixel region P. The pixel electrode  161  contacts the drain electrode  138  of the TFT “Tr” through the drain contact hole  149 . 
     Next, as shown in  FIG. 4H , the fourth PR pattern  185   a  is removed from the pixel electrode  161  such that the array substrate according to the present disclosure is manufactured.