Abstract:
The present invention provides an improved method of ensuring the integrity of command instructions exchanged between a host and an ATA device of an array of one or more ATA devices. The invention discloses a method of error detection for transfers of both control information and command information. The invention broadly includes the steps of: writing control information to one or more locations on the selected ATA device; reading the information stored at the corresponding locations; and comparing the control information to the information stored. Other aspects of the invention include writing command information to the ATA device; reading the information stored at the location to which the command information is written; and comparing the command information to the information stored. Other aspects of the invention terminate the command instruction if any compared information is not equal; or if the command instruction is not completed within a preset time interval.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates generally to computer systems, and, more particularly, to command instructions exchanged between a host system or device (e.g, a microprocessor-based personal computer, workstation, server, array controller, etc.) and an ATA device array consisting of one or more ATA devices (e.g., disk drives, CD-ROM drives, CD recorders, DVD drives, tape drives, removable floppy disk drives, etc.).  
         BACKGROUND OF THE INVENTION  
         [0002]    The proliferation of data-intensive computing applications has created an ever increasing demand for peripheral devices to reliably store significant amounts of information and provide timely access to stored data. Peripheral devices, such as disk drives, CD-ROM drives, CD recorders, DVD drives, removable floppy disk drives, tape drives and the like, are used in millions of computer systems worldwide. An interface connects such peripheral devices to the computer system. The choice of an interface can be a major factor in system performance.  
           [0003]    The most common interface used to connect a disk drive to a host system is the ATA interface. An ATA interface is one which conforms to the industry-standard “AT Attachment” specification. An ATA device is a peripheral device connected to a host system or data bus through an ATA interface. The ATA interface is commonly referred to as an IDE (“Integrated Drive Electronics”) interface, and the terms are now used interchangeably. Many variations of the ATA interface have evolved during the last two decades including ATA/ATAPI, EIDE, ATA-2, Fast ATA, ATA-3, Ultra ATA, Ultra DMA, ATA-4, ATA-5, ATA/66 and others. While ATA interfaces have been used primarily in connection with disk drives, they are not so limited and are commonly used with each peripheral device listed above, and others.  
           [0004]    Principal alternatives to the ATA interface are SCSI (“Small Computer System Interface”) and Fibre Channel interfaces. While the speed, capacity and reliability of ATA devices have increased significantly since their introduction in the mid-1980&#39;s, speed, adaptability and reliability are generally improved with SCSI and Fibre Channel interfaces. SCSI interfaces permit attachment of many peripheral devices to a single SCSI port and Fibre Channel interfaces allow many servers and storage devices to be interconnected into what is often referred to as a “storage area network” or SAN.  
           [0005]    The principal disadvantage to such alternatives, however, is cost. The cost of SCSI and Fibre Channel devices and interfaces is often substantially greater. In addition, SCSI and Fibre Channel devices and interfaces produce significantly more heat and utilize more power. ATA devices can also provide higher density storage. Furthermore, various configurations of ATA devices, such as RAID (“Redundant Array of Inexpensive Disks”) arrays and JBOD (“Just a Bunch Of Disks”) arrays, have been developed to take advantage of the lower cost of ATA devices while providing high storage capacity and relatively fast data access. As used herein, an array of ATA devices means one or more ATA devices.  
           [0006]    These improvements in ATA technology provide ATA devices with characteristics making them suitable for large-capacity, high-performance applications. Without the introduction of additional intelligence in an ATA device or an array of ATA devices, however, the minimal error detection capabilities inherent in ATA devices are often determined to be unsuitable for computer applications requiring high performance and reliability. Thus, many buyers turn to more expensive SCSI or Fibre Channel devices and interfaces.  
           [0007]    The object of the present invention is to improve the reliability of ATA devices and ATA arrays. The method claimed ensures the integrity and reliability of command instructions exchanged between a host device or system and an array of one or more ATA devices by providing a method of detecting errors that may occur when control information is written to the registers of the ATA device.  
           [0008]    A command instruction includes both control information and command information, referred to herein as the control portion and the command portion, respectively, of the command instruction. Prior to execution of any command, the control information corresponding to the command instruction is written to one or more of a series of ATA device registers resident in all ATA devices. A table of ATA registers follows:  
                                                                                       LOCATION   WRITE REGISTER   READ REGISTER                                (CS0 = 0, CS1 = 1)   CONTROL BLOCK REGISTERS            6   ALTERNATE STATUS   DEVICE CONTROL       7   DEVICE ADDRESS   NOT USED            (CS0 = 1, CS1 = 0)   COMMAND BLOCK REGISTERS            0   DATA   DATA       1   FEATURES   ERROR       2   SECTOR COUNT   SECTOR COUNT       3   SECTOR NUMBER   SECTOR NUMBER       4   CYLINDER LOW   CYLINDER LOW       5   CYLINDER HIGH   CYLINDER HIGH       6   DEVICE/HEAD   DEVICE/HEAD       7   COMMAND   STATUS                  
 
           [0009]    The writing of such control information to the ATA device registers is often referred to as a control transfer. Control transfers include tasks such as DEVICE/HEAD register initialization (i.e., selection of the desired peripheral device if the system includes more than one), logical block address initialization (i.e. selection of the location on the selected device to be acted upon), block count initialization (i.e. selecting the number of bytes, at the selected location, to be acted upon), writing of command information, and checking status information.  
           [0010]    The particular control information that must be written for a given command instruction, and the register(s) to which that control information must be written, are defined in the standard AT Attachment specification. Each command instruction requires that one or more blocks of control information, referred to herein as control subportions, be written to one or more ATA device registers.  
           [0011]    For example, a “read DMA queued” command requires that the command tag value subportion be written to the SECTOR COUNT register, and that the sector count subportion be written to the FEATURES register. A “read DMA” command requires that the sector count subportion be written to the SECTOR COUNT register, and does not require any that control information be written to the FEATURES register. Other examples of command instructions and the corresponding control information (or subportions) follow:  
                                       COMMAND   CONTROL SUBPORTIONS   REGISTERS                   SLEEP   E6 (SLEEP COMMAND   COMMAND           OPERATION CODE)       IDLE   TIME PERIOD VALUE   SECTOR COUNT           E3 (IDLE COMMAND CODE)   COMMAND       SEEK   LOGICAL BLOCK ADDRESS BITS   SECTOR NUMBER           0-7           LOGICAL BLOCK ADDRESS BITS   CYLINDER LOW           8-15           LOGICAL BLOCK ADDRESS BITS   CYLINDER HIGH           16-23           DEVICE ADDRESS AND   DEVICE/HEAD           LOGICAL BLOCK ADDRESS BITS           24-27           70 h   COMMAND                  
 
           [0012]    ATA devices do not include error detection for control transfers. Other inventions disclose methods of error detection for data transfers to and from an ATA device. For example, U.S. Pat. No. 6,192,492 (Masiewicz et al.) discloses a method of implementing fast, reliable data transfers across a data bus between a host and a device in a computer system having a host processor, a peripheral device such as a hard disk drive and a data bus. Current ATA, SCSI and Fibre Channel technology provide error detection for data transfers, but only Fibre Channel and SCSI are believed to provide error detection for control transfers. Masiewicz et al. does not disclose a method of error detection for control transfers to ATA devices.  
           [0013]    Therefore, a need exists for a method of error detection in a computer system which ensures the integrity and reliability of information exchanged in a control transfer from a host device or system to an ATA device of an array of one or more ATA devices.  
         DISCLOSURE OF THE INVENTION  
         [0014]    With parenthetical reference to the corresponding elements or portions of the disclosed embodiment, merely for purposes of illustration and not by way of limitation, the present invention provides an improved method of ensuring the integrity of command instructions exchanged between a host system or device and an ATA device (e.g., a disk drive) of an array of one or more ATA devices. The command instruction includes a control information portion (i.e. a control portion) and a command information portion (i.e. a command portion). The control portion consists of one or more control subportions.  
           [0015]    The improved method broadly includes the following steps: writing a first control subportion to a first location on an ATA device; reading the information stored at the first location; and comparing the information read to the first control subportion.  
           [0016]    Another aspect of the invention includes, in addition to the foregoing steps, the following additional steps: writing a second control subportion to a second location on an ATA device; reading the information stored at the second location; and comparing the information read to the second control subportion.  
           [0017]    Yet another aspect of the invention includes, in addition to the foregoing steps, the following additional steps: writing a third control subportion to a third location on an ATA device; reading the information stored at the third location; and comparing the information read to the third control subportion.  
           [0018]    In one aspect of the present invention, the device array includes a single ATA device. In another aspect, the device array includes a plurality of ATA devices.  
           [0019]    The present invention in one aspect provides that the ATA device to be acted upon includes an ATA device register, and that the first location on the selected ATA device is an ATA device register. Other aspects of the invention are directed to an ATA device which includes a plurality of ATA device registers, where the locations written to and/or read from include a corresponding plurality of ATA device registers.  
           [0020]    In one aspect of the present invention, the ATA device to be acted upon includes a CYLINDER HIGH register, CYLINDER LOW register, SECTOR NUMBER register, FEATURES register and SECTOR COUNT register, and the first location on the selected ATA device is one of those registers.  
           [0021]    In other aspects of the invention, the ATA device to be acted upon includes a DEVICE/HEAD register, and the first location on the selected ATA device is the DEVICE/HEAD register.  
           [0022]    In another aspect of the invention, the ATA device to be acted upon includes a CYLINDER HIGH register, CYLINDER LOW register, SECTOR NUMBER register, FEATURES register and SECTOR COUNT register, and the second location on the selected ATA device is one of those registers. In yet another aspect of the invention, the third location on the selected ATA device is another of those registers.  
           [0023]    In other aspects of the present invention, the command portion of the command instruction is written to a second, third or fourth location on the selected ATA device, which begins execution of the command instruction. In another aspect, the ATA device to be acted upon includes a COMMAND register and the second location on the selected ATA device is the COMMAND register. In yet another aspect, the third location on the selected ATA device is the COMMAND register. In another, the fourth location on the selected ATA device is the COMMAND register.  
           [0024]    In one aspect of the present invention, information is stored in two additional locations on the ATA device to be acted upon, and the information stored at those two locations are read and compared. In one aspect of the invention, the two additional locations are the third and fourth locations on the ATA device. In another aspect, the two additional locations are the fourth and fifth locations on the ATA device. In yet another aspect, the two additional locations are the fifth and sixth locations on the ATA device. Another aspect of the invention terminates the command instruction exchange if the information stored at the two additional locations is not equal. In another aspect, the ATA device to be acted upon includes a STATUS and an ALTERNATE STATUS register, and one of the additional locations is the STATUS register. In another, the other additional location is the ALTERNATE STATUS register.  
           [0025]    In another aspect of the invention, the following steps are performed sequentially: the first control subportion is first written to the first location on the selected ATA device; then, the information stored at the first location is read; and then, the information read at the first location is compared with the first control subportion.  
           [0026]    In another aspect of the invention, the following steps are first performed sequentially: the first control subportion is first written to the first location on the selected ATA device; then, the information stored at the first location is read; then, the information read at the first location is compared with the first control subportion; then, the following steps are performed without regard to sequence: writing a second control subportion to a second location on an ATA device; reading the information stored at the second location; and comparing the information read to the second control subportion.  
           [0027]    In another aspect of the invention, the following steps are performed sequentially: the first control subportion is first written to the first location on the selected ATA device; then, the information stored at the first location is read; then, the information read at the first location is compared with the first control subportion; then, the second control subportion is written to the second location on the selected ATA device; then, the information stored at the second location is read; then, the information read at the second location is compared with the second control subportion.  
           [0028]    In another aspect of the invention, the following steps are first performed: writing a first control subportion to a first location on an ATA device; reading the information stored at the first location; and comparing the information read to the first control subportion; then, the following steps are performed: writing a second control subportion to a second location on an ATA device; writing a third control subportion to a third location on an ATA device; reading the information stored at the second location; comparing the information read to the second control subportion; reading the information stored at the third location; and comparing the information read to the third control subportion.  
           [0029]    In another aspect of the invention, the following steps are performed sequentially: the first control subportion is first written to the first location on the selected ATA device; then, the second control subportion is written to the second location on the selected ATA device; and then, the third control subportion is written to the third location on the selected ATA device; and wherein at least one of the first location and the second location is read before the third location is read.  
           [0030]    In another aspect of the invention, the following steps are first performed: writing a second control subportion to a second location on an ATA device, and writing a third control subportion to a third location on an ATA device; and then, the following steps are performed: reading the information stored at the second location, and reading the information stored at the third location.  
           [0031]    In one aspect of the invention, the location to which the last control subportion is written is not the first location read.  
           [0032]    Another aspect of the invention is directed to a queued command instruction. In that aspect of the invention, the ATA device to be acted upon includes a FEATURES register and a SECTOR COUNT register, and the second location on the selected ATA device is the FEATURES register and the third location on the selected ATA device is the SECTOR COUNT register.  
           [0033]    A further aspect of the present invention terminates the command instruction exchange if the first control subportion is not equal to the stored information with which it is compared. Another aspect of the present invention terminates the command instruction exchange if any control subportion is not equal to the corresponding stored information with which it is compared.  
           [0034]    Another aspect of the present invention terminates the command instruction exchange if the execution of the command instruction is not completed within a preset time interval.  
           [0035]    Other aspects of the present invention provide that the ATA device array includes one or more disk drives, CD-ROM drives, CD recorders, DVD drives, tape drives or removable floppy drives.  
           [0036]    The general object of the invention is to improve the reliability and integrity of command instructions exchanged between a host system or device and an ATA device of an array of one or more ATA devices.  
           [0037]    Another object of the invention is to provide error detection for transfers of control and command information from a host system or device to an ATA device of an array of one or more ATA devices.  
           [0038]    Another object of the invention is to provide a method of ensuring that a control transfer results in the selection of the desired ATA device of a device array.  
           [0039]    Another object of the invention is to provide a method of terminating a command instruction if any control information written to an ATA device register is actually or potentially unreliable.  
           [0040]    Another object of the invention is to provide a method of terminating a command instruction if any command information written to an ATA device register is actually or potentially unreliable.  
           [0041]    Another object of the invention is to provide a method of terminating a command instruction if execution of the command instruction is not completed within a preset time interval, thereby ensuring the integrity of the command instruction exchange.  
           [0042]    These and other objects and advantages will become apparent from the foregoing and ongoing written specification, the accompanying drawings and the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0043]    [0043]FIG. 1 is a block diagram depicting a computer system having a host device and an ATA device array.  
         [0044]    [0044]FIG. 2 is a flowchart illustrating the operation of a preferred embodiment of the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0045]    At the outset, it should be clearly understood that like reference numerals are intended to identify the same parts, elements or portions consistently throughout the several drawing figures, as such parts, elements or portions may be further described or explained by the entire written specification, of which this detailed description is an integral part. Unless otherwise indicated, the drawings are intended to be read together with the specification, and are to be considered a portion of the entire written description of this invention.  
         [0046]    The computer system in the example of FIG. 1 includes a microprocessor-based personal computer  10  with a microprocessor  12  and random access memory  11 , and an ATA device array  30  consisting of an array controller  20 , and a plurality of ATA interfaces  31  and disk drives  32 .  
         [0047]    [0047]FIG. 2 is a flow chart depicting one illustrative embodiment of the invention. FIG. 2 illustrates the invention as applied to read DMA/write DMA and read DMA queued/write DMA queued command instructions. The process starts at block  100  wherein the host device writes a first control subportion to the DEVICE/HEAD register in the ATA device. Block  100  depicts the selection of the desired device on the ATA interface which will respond to subsequent writes to and reads from other ATA device registers.  
         [0048]    Next, at block  102 , the content of the DEVICE/HEAD register written to at block  100  is read. The process then passes to block  104  which depicts a determination of whether the value read from the DEVICE/HEAD register  102  is equal to the value designated to be written  100 .  
         [0049]    If a determination is made that the compared values are not equal (i.e. the output of block  104  is “NO”), it is uncertain whether the desired ATA device has been selected. In that case, the process passes to block  106  and the command instruction is terminated.  
         [0050]    If a determination is made that the compared values are equal (i.e. the output of block  104  is “YES”), it is highly probable that the desired ATA device has been selected and that the desired device will respond to subsequent register reads and writes. In this case, the process passes to blocks  108 ,  110  and  112  where additional control subportions are written to the CYLINDER HIGH, CYLINDER LOW and SECTOR NUMBER registers in the selected ATA device.  
         [0051]    The process then passes to block  114  which depicts a determination of whether the command instruction is a queued command. Command queuing allows the host to issue concurrent commands to the same ATA device, which are then processed, i.e., written to the COMMAND register on a first-in-first-out basis or, in some ATA devices, reordered for efficient execution and then written to the COMMAND register. If a determination is made that the command instruction is queued—for example, the command instruction is “read DMA queued” or “write DMA queued”—the process passes to block  116  where the host device writes an additional control subportion to the FEATURES register in the selected ATA device, and then passes to block  118  where the host device writes another control subportion to the SECTOR COUNT register in the selected ATA device. The invention writes to the FEATURES register only if the command instruction is queued.  
         [0052]    If a determination is made at block  114  that the command instruction is not queued—for example, “read DMA” or “write DMA”—the process bypasses block  116  and passes directly to block  118 , described above.  
         [0053]    Not every step depicted at blocks  108  through  118  is performed for every command instruction. If the command instruction exchange is not terminated at block  106 , upon selection of the ATA device, at least one of the steps depicted at blocks  108 ,  110 ,  112 ,  114 ,  116  and  118  will be performed for every command instruction. For some command instructions, all steps will be taken. The number of steps to be taken is determined by the command instruction to be executed. The invention recognizes the command instruction to be executed and validates only the corresponding control subportions.  
         [0054]    In addition, the order of the steps depicted in blocks  108  through  118  is not significant. They may be performed in any order.  
         [0055]    After one or more of the steps depicted in blocks  108  through  118  are performed, the process passes to blocks  120  through  142 , where the contents of the registers written to in blocks  108  through  118  are read and compared. In block  120 , the content of the CYLINDER HIGH register in the selected ATA device is read. Next, the process passes to block  122  which depicts a determination of whether the value read from the CYLINDER HIGH register  120  is equal to the value designated to be written  108 .  
         [0056]    If a determination is made that the compared values are not equal (i.e. the output of block  122  is “NO”), the integrity of the command instruction exchange is uncertain. In that case, the process passes to block  124  and the command instruction is terminated.  
         [0057]    If a determination is made that the compared values are equal (i.e. the output of block  122  is “YES”), the process passes to block  126  where the content of the CYLINDER LOW register written at block  110  is read. Next, the process passes to block  128  which depicts a determination of whether the value read from the CYLINDER LOW register  126  is equal to the value designated to be written  110 .  
         [0058]    If a determination is made that the compared values are not equal (i.e. the output of block  128  is “NO”), the integrity of the command instruction exchange is uncertain. In that case, the process passes to block  130  and the command instruction is terminated.  
         [0059]    If a determination is made that the compared values are equal (i.e. the output of block  128  is “YES”), the process passes to block  132  where the content of the SECTOR NUMBER register written to at block  112  is read. The process then passes to block  134  which depicts a determination of whether the value read from the SECTOR NUMBER register  132  is equal to the value designated to be written  112 .  
         [0060]    If a determination is made that the compared values are not equal (i.e. the output of block  134  is “NO”), the integrity of the command instruction exchange is uncertain. In that case, the process passes to block  136  and the command instruction is terminated.  
         [0061]    If a determination is made that the compared values are equal (i.e. the output of block  134  is “YES”), the process passes to block  138  where the content of the SECTOR COUNT register written to at block  118  is read. The process then passes to block  140  which depicts a determination of whether the value read from the SECTOR COUNT register  138  is equal to the value designated to be written  118 .  
         [0062]    If a determination is made that the compared values are not equal (i.e. the output of block  140  is “NO”), the integrity of the command instruction exchange is uncertain. In that case, the process passes to block  142  and the command instruction is terminated.  
         [0063]    If a determination is made that the compared values are equal (i.e. the output of block  140  is “YES”), the process passes to block  144  where the host device writes the command portion of the command instruction to the COMMAND register in the selected ATA device.  
         [0064]    The order of the steps depicted at blocks  120  through  142  is not significant; provided, however, that the reads performed at blocks  120 ,  126 ,  132  or  138  must be performed before the corresponding comparisons are made at blocks  122 ,  128 ,  134  or  140 .  
         [0065]    Next, the process passes to block  146  which depicts the commencement of a preset time interval effectuated by a count-down timer. As reflected in block  160 , initialization and execution of the command instruction is thereafter terminated if execution of the command instruction is not completed within the preset time interval.  
         [0066]    Should the preset time interval commenced at block  146  not first expire, the process passes to block  148  which depicts the completion of the command execution process.  
         [0067]    Should the preset timer interval commenced at block  146  not first expire, the process passes to block  150  wherein the contents of the ALTERNATE STATUS register in the selected ATA device is read, and to block  152  wherein the contents of the STATUS register in the selected ATA device is read. Upon completion of the command execution process  148 , the STATUS register and ALTERNATE STATUS register each contain a one-bit error code. The one-bit error code in each register is set to “1” when execution of the command results in an error, and to “0” if the command instruction executes successfully. Both registers are read in this process to verify that the error code is read correctly, so as to avoid a false indication of successful completion of the command instruction.  
         [0068]    Next, the process passes to block  154  which depicts a determination of whether the value read from the STATUS register  152  is equal to the value read from the ALTERNATE STATUS register  154 . If a determination if made that the values are not equal (i.e. the output of block  154  is “NO”), the process passes to block  156  and the command instruction is terminated.  
         [0069]    If a determination if made that the compared values are equal (i.e. the output of block  154  is “YES”), the process passes to block  158  which depicts the completion of the command instruction exchange.  
         [0070]    While there has been described what is believed to be the preferred embodiment of the present invention, those skilled in the art will recognize that other and further changes and modifications may be made thereto without departing from the spirit of the invention. Therefore, the invention is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined and differentiated by the following claims.