Abstract:
A method for forming a silicide layer on a silicon surface is provided. First, inert gas ions are implanted into the silicon surface. Then, a metal layer is formed on the surface and subsequently converted into the suicide layer. Thereby the resistance of the silicide can be reduced and the uniformity can be raised without substantially altering the doping concentration of conductive component(s). Thus, the efficiency of the semiconductor device can be enhanced.

Description:
[0001]    This application claims priority to Taiwan Patent Application No. 095135976 filed on Sep. 28, 2006. 
       CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0002]    Not applicable. 
       BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The subject invention relates to a method for forming a silicide layer on a silicon surface. More specifically, the subject invention relates to a method for forming a silicide layer on the surface of a semiconductor device. 
         [0005]    2. Descriptions of the Related Art 
         [0006]    In the developing semiconductor industry, semiconductor devices have not only integrated circuits, but have also become increasingly smaller. The prior structure of a semiconductor device is no longer suitable for use and is in need of a readjustment and rearrangement for effective performance. Aside from the problematic short channel effect, another problem has resulted from the miniaturization of the device: parasitic resistance. Because resistance has an inversely proportional relationship with the cross section of the conductive line, parasitic resistance increases as the width of the structure decreases with the reduction of the device size. 
         [0007]    In general, to promote the performance of a semiconductor device, a silicide layer is usually adopted on a polysilicon layer. In the manufacturing process, parasitic resistance is primarily reduced by a polycide or salicide process (self-aligned silicidation). The salicide process can significantly reduce the contact resistance because a silicide layer can be formed on both the source area and the drain area. 
         [0008]    The salicide process consists of many steps. First, source/drain areas on a substrate with a gate structure are formed. Second, a metal layer is deposited using sputtering deposition, and then, a first rapid thermal process (RTP) is conducted to form a silicide layer from the reaction of the metal in the metal layer with the silicon in the substrate. Using an N-type transistor as an example, a substrate with a gate structure is doped with a high concentration of arsenic ions to form source/drain diffusion areas on predetermined source/drain positions. Then, a layer of metal selected from a group consisting of Ti, Co, and Ni is deposited using sputtering deposition. Thereafter, a first RTP is conducted to form a silicide layer from the reaction of the metal in the metal layer with the silicon in the substrate. Third, a selective wet etching process is performed to remove the non-reacted metal layer portion and to leave the silicide layer formed on the surfaces of the gate, the source and the drain. Along with doping the predetermined source/drain positions by a high concentration of arsenic ions, the arsenic ions are normally also doped on the gate as well. The high concentration of arsenic ions on the gate and the source/drain areas will easily lead to an increase of the resistance in the silicide formed afterward and will decrease the uniformity thereof that deteriorates the performance of the device. Therefore, a second RTP is normally performed after the formation of a silicide layer by the first RTP, to reduce the resistance of the silicide layer. 
         [0009]    In response to the above-mentioned problems, a method with an additional ion implant step has been disclosed. Taking an N-type transistor as an example, an ion implantation is conducted on the gate and the source/drain areas after the doping of a high concentration of arsenic ions and the anneal processing. The ion implantation may use arsenic ions. Then, the remaining steps of the aforementioned salicide process are conducted. However, this technology still has disadvantages. For example, the arsenic (As) ions are N-type impurities that will result in a decreased doping concentration of P-type transistors after they are implanted thereinto. This is harmful to the entire performance of the integrated circuits. 
         [0010]    Thus, it is essential to solve these above-mentioned problems by providing a method that not only reduces the resistance, but also increases the uniformity of the silicide layer without decreasing the doped concentration of the conductive materials. 
       SUMMARY OF THE INVENTION 
       [0011]    An objective of the subject invention is to provide a method for forming a silicide layer on a silicon surface and a surface of a semiconductor device to effectively reduce the resistance of the silicide layer and increase its uniformity without decreasing the concentration of the conductive materials doped thereinto. 
         [0012]    Another objective of the subject invention is to provide a method for forming a silicide layer on a silicon surface and a surface of a semiconductor device so that the silicide layer in a semiconductor wafer is thinner and has better uniformity to promote the process yield and the quality of final products. 
         [0013]    To achieve the above-mentioned objectives, the subject invention provides a method for forming a silicide layer on a silicon surface. The method comprises implanting inert gas ions into the silicon surface; forming a metal layer on the surface; and converting the metal layer into a suicide layer. 
         [0014]    The subject invention further provides a method for forming a silicide layer on a silicon surface. The method comprises providing a semiconductor device that comprises a gate structure with a silicon surface and a spacer neighboring the gate structure, both located on a silicon substrate; implanting inert gas ions into the silicon surface and the silicon substrate; forming a metal layer covering the silicon surface, the spacer, and the silicon substrate; and converting the metal layer on both the silicon surface and the silicon substrate into a silicide layer. 
         [0015]    The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended figures for people skilled in this field to well appreciate the features of the claimed invention. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1A  depicts a schematic drawing of implanting conductive materials into a silicon surface; 
           [0017]      FIG. 1B  depicts a schematic drawing of implanting ions into the silicon surface; 
           [0018]      FIG. 1C  depicts a schematic drawing of forming a metal layer on the silicon surface; 
           [0019]      FIG. 1D  depicts a schematic drawing of converting the metal layer into a silicide layer; 
           [0020]      FIG. 2A  depicts a schematic drawing of implanting conductive materials into a surface of a semiconductor device; 
           [0021]      FIG. 2B  depicts a schematic drawing of implanting ions into the surface of the semiconductor device; 
           [0022]      FIG. 2C  depicts a schematic drawing of forming a metal layer; 
           [0023]      FIG. 2D  depicts a schematic drawing of forming a silicide layer on the surface of the semiconductor device; and 
           [0024]      FIG. 2E  depicts a schematic drawing of removing a portion of the metal layer on the surface of the semiconductor device. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0025]    An embodiment of a manufacturing method will be disclosed in the following description to explain how the problems and the disadvantages of the prior technology are solved by this invention. 
         [0026]    An embodiment of the invention will be disclosed in  FIG. 1A  to FIG  1 D. Please refer to  FIG. 1A , where a silicon surface  10  is first provided, and then, conductive materials are implanted onto the silicon surface  10 . The conductive materials can be any proper metal materials. Preferably, the conductive materials are selected from a group consisting of As, P, and a combination thereof, or a group consisting of B, BF, and a combination thereof. Specifically, the group consisting of As, P, and a combination thereof is used for an N-type transistor, and the group consisting of B, BF, and a combination thereof is used for a P-type transistor. Taking the N-type transistor as an example, it is preferred that the conductive material is arsenic (As). Next, referring to  FIG. 1B , inert gas ions are implanted into the silicon surface  10 . Preferably, the inert gas is selected from a group consisting of He, Ne, Ar, Kr, and a combination thereof. More preferably, the inert gas is Ar. Then, referring to  FIG. 1C , a cleaning process is performed onto the silicon surface  10 , and afterward, titanium and/or titanium nitride is deposited on the silicon surface  10  to form a metal layer  12 . Referring to  FIG. 1D , a thermal process is performed to convert the metal layer  12  into a silicide layer  14 . Next, a wet etching process is performed to remove the non-reacted portion of the metal layer  12 . 
         [0027]      FIG. 2A  to  FIG. 2E  shows another embodiment of the present invention that is applied in a semiconductor device.  FIG. 2A  illustrates a semiconductor device  2 , comprising a gate structure  22  with a silicon surface  220  and a spacer  24  neighboring the gate structure  22 , wherein the gate structure  22  and the spacer  24  are formed on a silicon substrate  20 . As depicted by the arrow direction shown in  FIG. 2A , conductive materials are implanted into the silicon surface  220  and the silicon substrate  20 . Similarly, the conductive materials are selected from a group consisting of As, P, and a combination thereof, or a group consisting of B, BF, and a combination thereof. Specifically, for an N-type transistor, arsenic is preferred. Optionally, after the above-mentioned processes, an anneal process such as a RTA process is performed. 
         [0028]    Next, please refer to  FIG. 2B , inert gas ions are implanted into the silicon surface  220  and the silicon substrate  20  as the arrow direction shows in  FIG. 2B . The inert gas is selected from a group consisting of He, Ne, Ar, Kr, and a combination thereof. More preferably, the inert gas is Ar. 
         [0029]    Referring to  FIG. 2C , a cleaning process is optionally performed onto the silicon surface  220  and the silicon substrate  20 . Next, a metal layer  222  is formed to cover the silicon surface  220 , the spacer  24  and a portion of the silicon substrate  20 . In general, a sputtering deposition is adopted. In an embodiment, a DC (direct current) sputtering method, collimator method, long throw method, ionized PVD method, and etc., can be used to deposit titanium and/or titanium nitride to provide the metal layer  222 . 
         [0030]    Referring to  FIG. 2D , a thermal process is performed. In general, the thermal process is a rapid thermal process, such as a rapid thermal annealing (RTA) process, so that the metal in the portion of the metal layer  222  both on the silicon surface  220  and the silicon substrate  20  can react with silicon to generate silicide, that is, to convert the portion of the metal layer  222  into a silicide layer  224 . In view of the silicon substrate  20 , the silicide layer  224  is formed on a source/drain area. More specifically, the rapid thermal process increases the temperature quickly to a high level of about 600 to 700° C. and is conducted in the presence of nitrogen. 
         [0031]    Next, referring to  FIG. 2E , a wet etching process is performed to remove the portion of the metal layer  222  which covers the spacer  24  (i.e. the non-reacted portion of the metal layer  222 ). In general, an acid solution is often adopted for this wet etching process. The portion of the surface which has converted into TiN but not into TiSi 2  can be removed by for example, but not limited to, a mixture of NH 4 OH, H 2 O 2 , and H 2 O or a mixture of H 2 SO 4  and H 2 O 2 . Lastly, a rapid thermal process is performed again to further reduce the resistance of the silicide. Such second rapid thermal process can be performed under a temperature of such as, but not limited to, about 800 to 900° C. 
         [0032]    The method of adopting an inert gas process before the formation of a silicide layer in the subject invention can effectively reduce the resistance of the silicide layer. For example, in a real operation that As ions were dopted with an energy of 20 KeV and at a concentration of 3E15, it is found that the resistance of the silicide layer formed by the method of the subject invention is approximately 50% less than that formed by the prior art method without the aforementioned inert gas process. 
         [0033]    To sum up, the semiconductor device manufactured by the method according to the subject invention can effectively reduce the resistance of the silicide layer without any change in the concentration of the conductive materials doped thereinto. Moreover, it is noted from the optical measurement that the method of the subject invention can promote the resistance uniformity of the silicide layer. That is, the method of the subject invention can both increase the performance and the integration of semiconductor devices. 
         [0034]    The above examples are only intended to illustrate the principle and efficacy of the subject invention, not to limit the subject invention. Any people skilled in this field may proceed with modifications and changes to the above examples without departing from the technical principle and spirit of the subject invention. Therefore, the scope of protection of the subject invention is covered in the following claims as appended.