Abstract:
An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage, comprising: an inverter circuit receiving the first signal and being connected for its supply between said higher voltage and said lower voltage, one at least of these connections being performed via at least one diode, a conversion element supplied between said higher and lower voltages, and receiving the output of the inverter circuit and providing the second signal, a storage element capable of maintaining the output of the inverter circuit at said higher or lower voltage when the first signal is respectively equal to the low or high voltage.

Description:
PRIORITY 
   This application claims priority from French patent application No. 03/50414, filed Aug. 8, 2003, which is incorporated by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates generally to circuits for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage. 
   2. Discussion of the Related Art 
   Such circuits are for example used as interface circuits between circuits operating with different supply voltages. The circuits may belong to a same integrated circuit supplied between a higher voltage Vdd and a lower voltage Gnd, for example, 1.2V and 0V for a so-called “0.12-μm” CMOS technology. One of the circuits, for example, a memory, is supplied between a voltage Vmin, for example, 0.4V, and a voltage Vmax, for example, 0.8V, and provides signals varying between voltages Vmin and Vmax. Voltages Vmin and Vmax may be generated from voltage Vdd by DC/DC voltage converters. To make the signals originating from the memory compatible with the rest of the integrated circuit, an interface circuit transforms the signals varying between voltages Vmin and Vmax into signals varying between voltages Gnd and Vdd. 
   A known interface circuit of very simple design is an inverter transforming a first signal varying between 0.4V and 0.8V into a second signal varying between 0V and 1.2V. The inverter is for example formed of a PMOS transistor and of an NMOS transistor having their sources respectively connected to voltages 1.2V and 0V. The transistor gates receive the first signal. The transistor drains are connected to the output of the inverter providing the second signal. Whatever the voltage value of the first signal, the NMOS and PMOS transistors are always conductive since their gate-source voltage is greater than a threshold voltage, which is approximately 0.4V for the “0.12-μm” technology. Thus, in the described interface circuit, the inverter permanently exhibits a consumption of power. Further, the output levels are not exactly equal to 0V and 1.2V. 
     FIG. 1  shows another interface circuit known as a “Schmitt trigger”. The source of PMOS transistor  1  is connected to voltage Vdd, its drain is connected to the source of a PMOS transistor  2  having its drain connected to output S 1  of the Schmitt trigger. The source of an NMOS transistor  3  is connected to voltage Gnd, its drain is connected to the source of an NMOS transistor  4  having its drain connected to output S 1 . The gates of transistors  1 ,  2 ,  3 , and  4  receive on input E 1  of the Schmitt trigger a first signal varying between 0.4V and 0.8V. The gate of a PMOS transistor  5  is connected to output S 1 , its drain is connected to voltage Gnd and its source is connected to the drain of PMOS transistor  1 . The gate of an NMOS transistor  6  is connected to output S 1 , its drain is connected to voltage Vdd and its source is connected to the drain of NMOS transistor  3 . 
   The Schmitt trigger provides on its output S 1  a second signal which takes value 0V when the first signal increases and exceeds a first switching threshold, for example, 0.7V, and which takes value 1.2V when the first signal decreases and falls under a second switching threshold, for example, 0.5V. When the first signal is 0.4V, PMOS transistors  1  and  5  are conductive. When the first signal is 0.8V, transistors  3  and  6  are conductive. Accordingly, the Schmitt trigger exhibits a high static power consumption. 
   Thus, a common disadvantage of the two previously-described interface circuits is that their static power consumption is high. 
   SUMMARY OF THE INVENTION 
   An embodiment of the present invention provides an interface circuit having a very low static consumption. 
   Another embodiment of the present invention provides an interface circuit which outputs a signal effectively varying between higher and lower supply voltages Vdd and Gnd. 
   Another embodiment of the present invention provides such an interface circuit having a very simple structure. 
   Another embodiment of the present invention provides an interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage. The interface circuit includes an inverter circuit receiving the first signal and being connected between the higher voltage and the lower voltage, where at least one of these connections is performed via a diode. The interface circuit also includes a conversion and storage element formed of first and second inverters head-to-tail supplied between said higher and lower voltages, the first inverter receiving the output of the inverter circuit and providing the second signal, and wherein the difference between the low voltage and the lower voltage is smaller than or equal to the sum of the threshold voltages of a first one of the diodes and/or the difference between the higher voltage and the high voltage is smaller than or equal to the sum of the threshold voltages of a second one of the diodes. 
   According to an alternative embodiment of the above-mentioned interface circuit, the inverter circuit is formed of a PMOS transistor and of an NMOS transistor, the drains of which are interconnected and connected to the output of the inverter circuit, and the gates of which receive the first signal. 
   According to an alternative of the above-mentioned interface circuit, said low voltage is equal to said lower voltage and the inverter circuit is directly connected to the lower voltage. 
   According to an alternative embodiment of the above-mentioned interface circuit, the high voltage is equal to the higher voltage and the inverter circuit is directly connected to the higher voltage. 
   According to an alternative embodiment of the above-mentioned interface circuit, the diodes are formed with a diode-assembled NMOS or PMOS transistor. 
   According to alternative embodiment of the above-mentioned interface circuit, the inverter circuit is a Schmitt trigger having its higher supply terminal connected to the higher voltage and having its lower supply terminal directly connected to the lower voltage. 
   According to alternative embodiment of the above-mentioned interface circuit, the conversion and storage element includes a third inverter, the input of the third inverter being connected to the output of the first inverter, the output of the third inverter providing the second signal. 
   Features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic of a conventional Schmitt trigger; 
       FIG. 2  is a schematic of an embodiment of an interface circuit according to the present invention; 
       FIG. 3  is a schematic of a second embodiment of an interface circuit according to the present invention. 
       FIG. 4  is a schematic of a third embodiment of an interface circuit according to the present invention. 
       FIG. 5  is a schematic of a fourth embodiment of an interface circuit according to the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 2  illustrates an embodiment of an interface circuit formed for a “0.12-μm” technology. The interface circuit receives a first signal on its input E 2  and provides a second signal on its output S 2 . The first signal varies between 0.4V and 0.8V. The second signal varies between supply voltages Vdd and Gnd respectively equal to 1.2V and 0V. 
   An inverter circuit  10  is formed in this embodiment of a PMOS transistor  11  and of an NMOS transistor  12 . The gates of transistors  11  and  12  are connected to input E 2 . The source of PMOS transistor  11  is connected to supply voltage Vdd via a diode  13 , for example a diode-assembled PMOS transistor, having its anode connected to voltage Vdd and its cathode connected to the source of PMOS transistor  11 . The source of NMOS transistor  12  is connected to supply voltage Gnd via a diode  14 , for example, a diode-assembled NMOS transistor having its cathode connected to voltage Gnd and its anode connected to the source of NMOS transistor  12 . The output of inverter circuit  10  is connected to the input of an inverter  15  forming a conversion element. The output of inverter  15  is connected to the input of an inverter  16  and to output S 2  of the interface circuit. The output of inverter  16  is connected to the output of inverter circuit  10 . Inverters  15  and  16  altogether form a storage element. Inverters  15  and  16  are supplied by supply voltages Gnd and Vdd. 
   When the first signal settles at 0.4V, for example, after a switching from 0.8V to 0.4V, PMOS transistor  11  and diode  13  become conductive. The voltage across diode  13  is equal to 0.4V and the source gate voltage of PMOS transistor  11  is equal to 0.4V. The size of PMOS transistor  11  and the size of diode  13  are provided to be large enough with respect to the size of the NMOS transistor of inverter  16  for the output of inverter circuit  10  to increase to 0.8V corresponding to voltage Vdd minus the threshold voltage of diode  13 . Part of the current flowing through PMOS transistor  11  and diode  13  flows through NMOS transistor  12 , and the voltage across diode  14  is increasing. The gate-source voltage of NMOS transistor  12  decreases and becomes smaller than its threshold voltage. NMOS transistor  12  then becomes non-conductive. The switching threshold of inverter  15  is provided to be smaller than 0.8V so that inverter  15  switches, as well as inverter  16 . The second signal becomes zero and the voltage on the output of inverter circuit  10  rises up to 1.2V. PMOS transistor  11  is conductive and the voltage on the source of PMOS transistor  11  rises up to 1.2V. Diode  13  then is non-conductive. 
   The storage element formed of inverters  15  and  16  enables setting the output of inverter circuit  10  to a voltage strictly equal to 1.2V. Accordingly, the output of the conversion element, inverter  15 , is strictly equal to 0V. 
   Once the switching of the interface circuit is over, NMOS transistor  12  and diode  14  and PMOS transistor  13  are non-conductive. Since the output voltage of inverter circuit  10  is set (1.2V), PMOS transistor  11  and inverters  15  and  16  are in a steady state and their electric power consumption is almost zero. The static power consumption of the interface circuit is thus very small. 
   When the first signal settles at 0.8V, for example, after switching from 0.4V to 0.8V, the NMOS transistor  12  and diode  14  are turned on. The voltage across diode  14  is equal to 0.4V and the source-gate voltage of NMOS transistor  12  is equal to 0.4V. The size of NMOS transistor  12  and the size of diode  14  are provided to be sufficiently high with respect to the size of the PMOS transistor of inverter  16  so that the output of inverter circuit  10  decreases to 0.4V corresponding to the threshold voltage of diode  14 . Part of the current flowing through transistor  12  and diode  14  flows through transistor  11 , and the voltage on the source of PMOS transistor  11  decreases. The gate-source voltage of PMOS transistor  11  decreases and becomes smaller than its threshold voltage. PMOS transistor  11  then becomes non-conductive. The switching threshold of inverter  15  is provided to be greater than 0.4V so that inverter  15  switches, as well as inverter  16 . The second signal becomes equal to 1.2V and the voltage on the output of inverter circuit  10  becomes zero. NMOS transistor  12  is conductive and the voltage on the source of NMOS transistor  12  decreases and becomes zero. Diode  14  then is non-conductive. 
   As previously described, once the interface circuit switching is over, the static power consumption of the interface circuit is very low. 
     FIG. 3  is a diagram of another embodiment of an interface circuit according to the present invention. The interface circuit receives on its input E 3  a first signal which varies between 0V and 0.8V and provides on its output S 3  a second signal which varies between the supply voltages equal to 1.2V and 0V. 
   A Schmitt trigger  20 , identical to that previously described in relation with  FIG. 1 , receives the first signal. The higher supply terminal of the Schmitt trigger is connected to supply voltage 1.2V via a diode  21 , for example, a diode-assembled PMOS transistor. The anode of diode  21  is connected to supply voltage 1.2V, and its cathode is connected to the higher supply voltage of the Schmitt trigger. The lower supply terminal of the Schmitt trigger is directly connected to supply voltage 0V. The output of Schmitt trigger  20  is connected to the input of an inverter  23 . The output of inverter  23  is connected to the input of two inverters  24  and  25 . The output of inverter  25  is connected to the output of the Schmitt trigger. The output of inverter  24  is connected to output S 3  of the interface circuit and provides the second signal. Inverters  23 ,  24 , and  25  are supplied by supply voltages 1.2V and 0V. 
   When the first signal switches from 0.8V to 0V, diode  21  turns on and the two PMOS transistors of the Schmitt trigger controlled by the first signal turn on. The NMOS transistors of the Schmitt trigger controlled by the first signal become non-conductive. The voltage on the output of the Schmitt trigger increases. Inverter  23  switches, as well as inverters  24  and  25 . The voltage on output S 3  of the interface circuit increases up to 1.2V. 
   Similarly, when the first signal switches from 0V to 0.8V, the two NMOS transistors of the Schmitt trigger controlled by the first signal turn on. The PMOS transistors of the Schmitt trigger controlled by the first signal turn off. The voltage on the output of the Schmitt trigger decreases. Inverter  23  switches, as well as inverters  24  and  25 . The voltage on output S 3  of the interface circuit becomes zero. 
   Whatever the level of the first signal, 0.8V or 0V, the transistors of the Schmitt trigger and PMOS transistor  21  are conducting no current. In the same way as for the inverters of the interface circuit of  FIG. 2 , inverters  23 ,  24 , and  25  have a current consumption dose to zero. The static consumption of such an interface circuit is thus very low. 
   Inverters  23  and  25  form a storage element used to maintain the output of the Schmitt trigger at supply voltage 0V or 1.2V. Inverters  23  and  24  form an element of conversion of the output of the Schmitt trigger into a second signal having a value precisely equal to 0V or 1.2V. As compared to the interface circuit of  FIG. 2 , the addition of an inverter before the output of the interface circuit provides an inverting interface circuit. 
     FIG. 4  illustrates another embodiment of an interface circuit according to the present invention. The interface circuit in  FIG. 4  is similar to the interface circuit in  FIG. 2  except that the diode  13  has been removed so that the source of PMOS transistor  11  is directly connected to supply voltage Vdd. 
     FIG. 5  illustrates another embodiment of an interface circuit according to the present invention. The interface circuit in  FIG. 5  is similar to the interface circuit in  FIG. 2  except that the diode  13  is connected to supply voltage Vdd through at least another diode  17 , for example a diode-assembled PMOS transistor. Similarly, the diode  14  is connected to supply voltage Gnd through at least another diode  18 , for example a diode-assembled NMOS transistor. 
   It should further be noted that when one of the low or high voltages of the first signal is equal respectively to the lower or higher voltage, the inverter circuit receiving the first signal may directly be connected to the supply voltage equal to one of the low or high voltages. 
   Generally, an interface circuit according to an embodiment of the present invention includes a conventional inverter circuit connected to lower supply voltage Gnd directly or via at least one first diode and connected to higher voltage Vdd directly or via at least one second diode. This inverter circuit is followed with conversion and storage elements. For the static power consumption of the interface circuit to be as small as possible, the number of first diodes is chosen such that the difference between the low level of the first signal and lower voltage Gnd is smaller than the sum of the threshold voltages of the first diodes. Similarly, the number of second diodes is chosen to be such that the difference between higher supply voltage Vdd and the high level of the first signal received by the interface circuit is smaller than the sum of the threshold voltages of the second diodes. Alternatively, the number of first diodes is chosen such that the difference between the low level of the first signal and lower voltage GND is smaller than the sum of the threshold voltages of the inverter circuit and the first diodes. Similarly, the number of second diodes is chosen to be such that the difference between higher supply voltage Vdd and the high level of the first signal is smaller than the sum of the threshold voltages of the inverter circuits and the second diodes. 
   An advantage of the interface circuit according to an embodiment of the present invention is that its static power consumption is very low. 
   Another advantage of such an interface circuit is that it outputs a signal effectively varying between higher supply voltage Vdd and lower supply voltage Gnd. 
   Of course, the above-described embodiments and advantages of the present invention are likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the inverter circuit may be any circuit adapted to providing a voltage on its output inverse to that on its input, a Schmitt trigger being an example thereof. Further, it will be within the abilities of those skilled in the art to define the number of diodes to be inserted between the inverter circuit and lower supply voltage Gnd and higher supply voltage Vdd. Further, it will be within the abilities of those skilled in the art to choose the best adapted conversion and storage elements. It should further be noted that an interface circuit according to an embodiment of the present invention may transform a signal varying within a larger voltage range than that initially provided, the maximum voltage range being that defined by the interface circuit supply voltages. 
   Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.