Abstract:
The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Description:
CLAIM OF PRIORITY TO PROVISIONAL APPLICATION (35 U.S.C. § 119(e)) 
   This application claims priority under 35 U.S.C. § 119(e) from provisional patent Application No. 60/568,939, filed May 7, 2004. The 60/568,939 Application is incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to error correction systems for computer data. More specifically, the invention relates to the use of parity check codes such as a low density parity check code (“LDPC”). 
   BACKGROUND OF THE INVENTION 
   The transmission of binary computer data involves the introduction of errors, which must be detected and corrected, if possible. Although the difference between the two binary values, zero and one, seems clear, like the difference between black and white, in practice an electronic device may have difficulty distinguishing the difference. The difference between binary values may be detected as a voltage difference, but electronic noise in a circuit can interfere and render the difference less certain. This uncertainty must be dealt with. One option is to reject the data input and request retransmission. However, this is impossible with some fast flowing digital signals with substantial volume, such as digital TV, and is impractical in many situations. Accordingly, error correction systems have been developed to detect and correct errors. Communication systems often use forward error correction to correct errors induced by noise in the channel. In such systems, the error correction occurs at the receiver. One such system is parity check coding. One example of parity check coding is “low density parity check” coding (“LDPC”). 
   Forward error correction consists of adding redundancy to data. Block codes, such as the LDPC codes, segment the data into blocks. These blocks have additional bits added according to a specified algorithm, to create a codeword. This codeword is transmitted to the receiver over the channel. The data that is transmitted is binary in nature, meaning that it is either a logical “1” or a logical “0”. Noise is added by the channel, and the receiver detects each of the bits of the codeword and makes a best initial determination as to whether the bit is a logical 1 or 0. The receiver might also have the ability to assign a confidence in its guess. These guesses are called soft bits. 
   When a receiver gets a codeword, it is processed. The coding information added to original data is used to detect and correct errors in the received signal and thereby recover the original data. For received values with errors, the decoding system will attempt to recover or generate a best guess as to the original data. 
   As noted above, the receiver can reject data input containing errors. Retransmission may increase the reliability of the data being transmitted or stored, but such a system demands more transmission time or bandwidth or memory, and in some applications, such as digital TV signals, it may be impossible with current technology. Therefore, it is highly desirable to perfect error detection and correction of transmitted data. 
   LDPC systems use an iterative decoding process which is particularly suitable for long codewords. In general, LDPC codes offer greater coding gains than other, currently available codes. The object is to use parallel decoding in the LDPC&#39;s iterative process to increase speed. In order to accomplish this, the inherent parallelism of an LDPC code must be found and exploited. There is also a need to reduce the amount of memory accesses and total memory required per iteration. To make the LDPC coding work as efficiently and quickly as possible, careful attention must be drawn to the storage of data and routing the data to the storage during the iterations. 
   U.S. Pat. No. 6,633,856 to Richardson et al. (“Richardson”), discloses two LDPC decoder architectures, a fast architecture and a slower architecture. In the slow architecture, a single iteration consists of two cycles. There is an edge memory consisting of one location for each edge in the Tanner Graph or, equivalently, there is one location for each 1 in the H matrix. There is also an input buffer which requires a memory location for each input variable, or equivalently, there is a memory location for each column of the H matrix. The two memories do not require the same resolution, the high resolution memory is the edge memory, and the low resolution memory is the input buffer. In the fast architecture, a single iteration consists of a single memory cycle. There are two edge memories and a single input buffer required. 
   SUMMARY OF THE INVENTION 
   The current invention involves a parallel SISO structure that allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates to the stored differences for presentation to the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates. 
   The LDPC architecture of the present invention makes better use of memory and processing capacity during decoding. In the present invention, a single iteration consists of a single memory cycle. Two memories are disclosed. The first is a difference array which has a memory location for each of the ones in the H matrix, and the second is a current array which has a memory location for each of the columns in the H matrix. The current array may use high resolution memory, but the difference array requires only low resolution memory. 
   The LDPC architecture of the present invention requires the same number of memory cycles as the fast architecture of the Richardson architecture, but the present invention only requires the same number of memory locations as the slow architecture. Furthermore, the Richardson architectures require the larger memory to have higher resolution, while the present invention requires only the small memory as the higher resolution. The result is that, even with the same number of memory locations as the slow architecture of Richardson, the number of memory bits required by the present invention is less than required by even the slow architecture of Richardson. 
   Another significant difference between the present invention and the Richardson architectures is how permutations are handled. The Richardson architecture stores all the variable messages in their unpermuted form and the check messages in their permuted form. This requires a permutation block for each memory access. The architecture of the present invention represents the differences in their permuted form, and the variable nodes are stored in the same permutation as the last time they were accessed. They are permuted to the correct orientation each time they are used. The consequence is that only one permutation is required per iteration instead of the two required by the Richardson architecture. This is a significant savings, as the permuter is a fairly large function. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a representative parity check matrix (H-Matrix). 
       FIG. 2  shows a signed magnitude data structure. 
       FIG. 3   a  is a decoder architecture with no parallelism. 
       FIG. 3   b  is a decoder architecture for expanded codes which allows for parallel processing of data. 
       FIG. 4  shows all permutation transformations for 3 variables. 
       FIG. 5   a  shows an expanded H-Matrix with permuted sets. 
       FIG. 5   b  shows the H-Matrix of  FIG. 5   a  without the zero blocks, for greater clarity. 
       FIG. 6  is a matrix of permutations as an alternate representation for the H-matrix in  FIG. 5   a.    
       FIG. 7  is a third alternate representation for the H-matrix showing the equations as sums of the input sets linked with their permutation. 
       FIG. 8  is a table showing the result of two permutations. 
       FIG. 9  shows the contents of the CA for each iteration of the expanded code. 
       FIG. 10  shows the contents of the DA for the expanded code. 
       FIG. 11   a  shows a circuit that finds the minimum value in a sequential list of values, and passes all the non-minimums through. It also gives the sequence number in the list of the minimum value. 
       FIG. 11   b  shows the minimum function block. 
       FIG. 12   a  shows the sign bit path of the SISO circuit. 
       FIG. 12   b  shows the magnitude field path of the SISO circuit. 
       FIG. 13  shows sets of inputs. 
       FIG. 14  shows sets of Current estimates. 
       FIG. 15  is a decoder architecture for expanded codes with the additional feedback path for handling multiplicities. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   1. The Coding Process 
   Communication systems often use forward error correction to correct errors induced by noise in a transmission channel. In such forward error correction systems, the detection and correction of errors occur at the receiver. Bits received through the channel are detected at the receiver as “soft” values. A soft value represents the “best guess” that the receiver can make for the value of the bit that was sent and the confidence in that guess. In essence, data is sent as a single bit, and received as a multi-bit sample. During transmission, a single bit of data may pick up noise, so that it is necessary to use more than a single bit to identify the sampled data. For example, in a binary system, if a “1” is coded as 5 volts and a “0” as 0 volts, then each can be represented with a single bit. If a value of 4.2 volts is received, then this is close to representing a “1”, but the receiver will use multiple bits to represent how close to the 5 volts the sampled data resides. 
   A typical format for the received data is signed magnitude, where the first bit is a sign bit representing the hard decision data, and the remainder of the bits represent the confidence in the hard decision bit. A “hard decision” is a single bit. In the example set out immediately above, the receiver reads 4.2 volts, but could output a “1” as a hard decision, which would indicate 5 volts. This is shown in  FIG. 2  with the &lt;hd&gt; field  233  being a single bit hard decision, and the &lt;lvl&gt; field  234  being a multi-bit confidence level. The signed magnitude is positive if the &lt;hd&gt; bit  232  equals one, and is negative if the &lt;hd&gt; bit  235  equals zero. An example of the signed magnitude format may be illustrated as follows: 
   
     
       
             
             
             
             
           
             
             
             
             
             
           
         
             
                 
                 
             
             
                 
               sign 
               magnitude 
                 
             
             
                 
               &lt;hd&gt; 
               &lt;lvl&gt; 
             
             
                 
                 
             
           
           
             
                 
             
           
        
         
             
                 
               e.g. 
               1 
               00111 
               (representing a positive 7) 
             
             
                 
               e.g. 
               0 
               00111 
               (representing a negative 7) 
             
             
                 
                 
             
           
        
       
     
   
   A type of forward error correction is low density parity check codes (LDPC). Low Density Parity Check codes are codes that have a “sparse” H-Matrix. A sparse H-Matrix is one in which there are many more zeroes than ones in the H-Matrix. For illustration here, a representative (non-sparse) H-Matrix  201  is shown in  FIG. 1 . The associated input vector “I”  209 , representing the inputs i k    210 , and the current estimate of the sent data, vector “C”  220 , are shown in  FIG. 1  as well. Each row  202  of the matrix represents a parity equation. Each row is identified as the “ith” row, row i    202 . In  FIG. 1 , there are five rows  202 , row  0  through row  4 , in the exemplary H-Matrix. The number of inputs i  210  is equal to the number of columns in the H-matrix. In  FIG. 1 , there are ten columns in the exemplary H-Matrix; so, there are ten inputs i k    210 , i 0  through i 9 . The elements of the H-matrix are referred to as H i,k    200 , which is the element in row i and column k. 
   In practice, an H-matrix will be much larger than the exemplary matrix of  FIG. 1 , and will have many hundreds if not thousands of data bits. By way of background information, an LDPC code is defined as “regular” if the H-matrix has the same number of 1&#39;s in each column and the same number of 1&#39;s in each row, and is “irregular” if it does not have the same number of ones in either the rows, the columns, or both. LDPC decoders work on “soft” channel data and are iterative in nature. 
   2. The SISO 
   As noted above, inputs are received in a signed magnitude representation. The inputs are stored in an input buffer  251  in  FIG. 3   a.    
   In its basic operation, the “Soft-In-Soft-Out” (“SISO”) function of an LDPC decoder evaluates each of the parity equations row i    202 , represented by the rows  202  of the H-Matrix  201  using the current estimates C  220 , and if the parity equation is satisfied, will increase the confidence of the current estimates c k    221  for those current estimates c k    221  related to row i    202 . If the parity equation row i    202  is not satisfied, the confidence of each current estimate c k    221  related to row i    202  will be decreased. It is possible to decrease the confidence to the point that a current estimate&#39;s hard decision bit is actually flipped, producing a correction of erroneous data. 
   The parity equations that the SISO evaluates are determined by the multiplication of the H-Matrix  201  by the input vector I  210  and the multiplication of the H-Matrix  201  by the current estimate vector C  220 . This multiplication yields the parity equations
 
i 0 +1 1 +i 3 +i 5 +i 9 
 
i 1 +1 2 +i 4 +i 5 +i 6 
 
i 0 +1 2 +i 3 +i 6 +i 7 
 
i 0 +1 1 +i 4 +i 7 +i 8 
 
i 2 +1 3 +i 4 +i 8 +i 9 
 
for the inputs and the parity equations
 
c 0 +c 1 +c 3 +c 5 +c 9 
 
c 1 +c 2 +c 4 +c 5 +c 6 
 
c 0 +c 2 +c 3 +c 6 +c 7 
 
c 0 +c 1 +c 4 +c 7 +c 8 
 
c 2 +c 3 +c 4 +c 8 +c 9 
 
for the current estimates.
 
   For each evaluation of a parity equation, the SISO outputs a difference for each of the inputs. This value is the difference between the input to the SISO and the estimate that this particular equation provides for that data. Referring to  FIG. 3   a , this difference is stored in the Difference Array (“DA”) memory  257 , as it is needed in subsequent evaluations of the same equation. The difference is also sent to an adder  260 , where it is added to the data stored in the FIFO  259 . This data is stored in the Current Array, “CA”. Let c k  represent the current best estimate of the kth input to the decoder, and let d i,k  represent the change in confidence to c k  according to parity equation i. The estimate c k  is stored in CA  252  and estimate d i,k  is stored in DA  257 . 
   The SISO  258  takes as inputs all the inputs identified by a row in the H-Matrix. As an example, for row  0  of the matrix in  FIG. 1 , inputs  221  c 0 , c 1 , c 3 , c 5 , and c 9  are selected. The SISO  258  outputs a difference for each of the inputs; these are designated as d 0,0 , d 0,1 , d 0,3 , d 0,5  and d 0,9  respectively. These are both stored into the DA memory  257 , and added  260  to the original SISO inputs. The outputs of this adding operation are then stored back into the CA  252 , replacing the values that were used in the equation. 
   After one complete iteration cycle, each of the parity equations, row  0  through row  4 , will have been evaluated once, and the contents of the CA will be as follows:
 
 c   0   ′=c   0   +d   0,0   +d   0,2   +d   0,3 
 
 c   1   ′=c   1   +d   1,0   +d   1,2   +d   1,3 
 
 c   2   ′=c   2   +d   2,1   +d   2,2   +d   2,4 
 
 c   3   ′=c   3   +d   3,0   +d   3,2   +d   3,4 
 
 c   4   ′=c   4   +d   4,1   +d   4,3   +d   4,4 
 
 c   5   ′=c   5   +d   5,0   +d   5,2 
 
 c   6   ′=c   6   +d   6,1   +d   6,2 
 
 c   7   ′=c   7   +d   7,2   +d   7,3 
 
 c   8   ′=c   8   +d   8,3   +d   8,4 
 
 c   9   ′=c   9   +d   9,4   +d   9,0 
 
   The result c k ′ is the new value for c k  which is stored back in the CA  252  after the iteration. The old value of c k  is overwritten by the new value. 
   The CA  252  will contain n signed magnitude values and the DA  257  contains as many signed magnitude values as there are 1&#39;s in the H-Matrix  201 . In the above example, the DA  257  will have 25 entries, and the CA  252  will have 10. 
   a. SISO Inputs/Outputs 
   The data structure for c k  and d i,k  is shown in  FIG. 2 . The bit &lt;hd&gt;  233  is the hard decision value, and &lt;lvl&gt;  235  is a multi-bit confidence value where the higher the value, the higher the confidence. The function hd(c k ) returns the hard decision value of c k , i.e., a “1” or a “0”, and the function lvl(c k ) returns the confidence value of c k . 
   Sticky adder  256  is placed ahead of the SISO  258 . The sticky add function is defined as follows:
 
 A⊕B=A+B  if  A+B&lt; MaxVal
 
 A⊕B= MaxVal if  A+B≧ MaxVal
 
MaxVal⊕ B =MaxVal for all  B 
 
Where A and B are variables and MaxVal is the maximum value that can be handled. For example, if X and Y are 6 bit signed magnitude registers, then the lvl field is a 5 bit number and the hd field is a single bit. If X is a positive 20 and if Y is a positive 15, then the binary value of X is 110100 and the binary value of Y is 101111. Then, lvl(X)⊕lvl(Y)=31.
 
   There is an input i k    210  and a current estimate c k    221  associated with each column of the H-Matrix, and there is a difference associated with each non-zero entry in the H-Matrix; that is with every “1” entry. For example, when working on row  1  of the H-Matrix  201  in  FIG. 1 , the non-zero k&#39;s are {1,2,4,5,6}. Each row of the H matrix represents one parity equation. When evaluating the equation represented by row i    202 , the SISO takes as input t k  where
 
 t   k   =c   k ⊕(− d   i,k ) for all k where H i,k =1
 
The value t k  is the output of adder  256  in  FIG. 3   a . It has the data structure that is shown in  FIG. 2 . From the adder  256 , t k  is presented to the SISO  258 , as well as stored in the FIFO  259 .
 
   The purpose of the SISO is to generate the differences. The differences are the differences between each input and current estimate as identified by the particular row equation being worked. The differences are defined by the following sets of equations: 
   
     
       
         
           
             CORRECT 
           
           = 
           
             
               ∑ 
               k 
             
             ⁢ 
             
               
                 hd 
                 ⁡ 
                 
                   ( 
                   
                     t 
                     k 
                   
                   ) 
                 
               
               ⁢ 
               
                   
               
               ⁢ 
               
                 where  addition  is  over 
               
               ⁢ 
               
                   
               
               ⁢ 
               
                 
                   GF 
                   ⁡ 
                   
                     ( 
                     2 
                     ) 
                   
                 
                 . 
               
             
           
         
       
     
   
   MinVal 1 =min(lvl(t k )) for all k 
   v=k: lvl(t k )=MinVal 1    
   MinVal 2 =min(lvl(t k )) for all k≠v 
   hd(d i,k )=hd(t k )+CORRECT where addition is over GF(2) 
   lvl(d i,v )=MinVal 2    
   lvl(d i,k )=max(0, MinVal 1 −f(MinVal 2 −MinVal 1 )) for k≠v with the function f(MinVal 2 −MinVal 1 ) is defined such as: 
   
     
       
         
           
             f 
             ⁡ 
             
               ( 
               x 
               ) 
             
           
           = 
           
             
               f 
               ⁡ 
               
                 ( 
                 
                   
                     MinVal 
                     2 
                   
                   - 
                   
                     MinVal 
                     1 
                   
                 
                 ) 
               
             
             = 
             
               
                 
                   
                     3 
                   
                 
                 
                   
                     2 
                   
                 
                 
                   
                     1 
                   
                 
                 
                   
                     0 
                   
                 
               
               ⁢ 
               
                   
               
               ⁢ 
               for 
               ⁢ 
               
                   
               
               ⁢ 
               
                 
                   
                     
                       x 
                       &lt; 
                       2 
                     
                   
                 
                 
                   
                     
                       2 
                       ≤ 
                       x 
                       &lt; 
                       4 
                     
                   
                 
                 
                   
                     
                       4 
                       ≤ 
                       x 
                       &lt; 
                       8 
                     
                   
                 
                 
                   
                     
                       8 
                       ≤ 
                       x 
                     
                   
                 
               
             
           
         
       
     
   
   The output of the SISO is d i,k . This value of d i,k  replaces the value that was read from the DA. The value of c k  that was read from CA is replaced with t k ⊕d i,k  for all k. 
   b. The Minimum Function 
     FIGS. 11   a  and  11   b  are block diagrams showing the minimum function of the present invention.  FIG. 11   b  shows the input and outputs of the minimum function block  401 , and  FIG. 11   a  shows the details of the minimum function block  401 . The minimum function finds the minimum number in a list of numbers. The minimum number will be presented on the output MinVal  414  of the minimum function block  401 . The sequence number of the minimum number will be presented on the output MinLoc  421 . All other numbers in the sequence are passed through the minimum function block unchanged  422 . 
   The minimum function block is initialized by having the counter  416  set to zero and the Val register  413  set to the maximum possible value with a preset which initializes the Val register  413  to all ones. The numbers are input on the Data_in line  402 . This value is presented to the “a” input of the comparator  411 . The “b” input of the comparator  411  is the current minimum value. After initialization, this is the maximum possible number. If “a” is less than “b”, then Mux  1   403  passes the Val register value to the output Data_out  422 . Mux  2   407  passes the Data_in input  402  to the input of the Val register  413 , where it is saved. If “a” is not less than “b”, then Mux  1   403  passes Data_in to the output Data_out  422 . Mux  2   407  passes the contents of the Val register back to the Val register  413 , in effect, leaving it the same. 
   As noted above, the counter  416  is initially set to zero. Every time new input is brought in, the counter is incremented. If Data_in  402  is less than the value stored in the Val register  413 , the value of the counter  416  is latched into the Loc register  417 . This corresponds to a new minimum value being stored in the Val register  413 . 
   Once a sequence of numbers have passed through the minimum function block, the output MinVal  414  has the minimum value and the output MinLoc  421  has the location in the sequence of the minimum value. 
   By way of example, if the sequence {14,16,10,10} were passed through the circuit, the following would occur. The counter  416  is initialized to zero and the Val register  413  is initialized to a maximum value. The number 14 is input. 14 is less than a maximum value, so 14 gets placed in the Val register  413 , the number 0 is placed in Loc  417 , and the maximum value is passed to the output Data_out  422  and the counter  416  is incremented to 1. Then the number 16 is input 16 is larger than the 14 that is in Val  413  register, so the Val register  413  maintains its value of 14, the register Loc  417  maintains its value of 0, 16 is passed to the output Data_out  422  and the counter  416  is incremented to 2. Then the number 10 is input. 10 is less than the 14 that is in Val register  413 , so the Val register  413  is changed to 10, the number 2 is placed in Loc  417 , 14 is passed the out Data_out  422  and the counter  416  is incremented to 3. Then the second number 10 is input. The second 10 is not less than the first 10, so the 10 that is in Val register  413  stays the same, the value of Loc  417  does not change, the second 10 is passed out Data_out  422  and the counter  416  is incremented to 4. As this is the end of the sequence, the MinVal output  414  is 10 and the MinLoc output  421  is 2. 
   c. Details of the SISO 
   The SISO is shown in  FIGS. 12   a  and  12   b . It takes as its input the string of t k &#39;s. Each of the values is a signed magnitude number. These inputs are hd(t k )  452  in  FIG. 12   a , which is the sign bit, and lvl(t k )  502  in  FIG. 12   b , which is the magnitude portion of the number. The SISO deals with these portions separately, and they are recombined at the output. As such, they will be dealt with as separate data paths.  FIG. 12   a  is the sign bit data path and  FIG. 12   b  is the magnitude field data path. 
   First consider the sign bit data path in  FIG. 12   a . The flip flop  454  in  FIG. 12   a  is initialized to 0. As each sign bit is input, it is exclusive-or&#39;d with contents of the flip flop  454  and the result is placed in the flip flop  454 . After all the hd(t k )&#39;s  452  are input, the flip flop  454  contains the exclusive-or of all the sign bits. This is the signal named “CORRECT”  456 . Each of the sign bits are also stored in a FIFO  455 . Once all the hd(t k )&#39;s  452  have been input, the CORRECT bit  456  is fixed. This bit is exclusive-or&#39;d with each of the sign bits that has been stored in the FIFO. These become the sign bits for the new hd(d i,k )&#39;s  458  that are output from the FIFO  455 . Thus, if the parity of the inputs is even, each of the new hd(d i,k )&#39;s  458  will have the same sign as the respective hd(t k )  452 . If the parity of the inputs is odd, then each of the new hd(d i,k )&#39;s  458  will have the opposite sign as the respective hd(t k )  452 . 
   The magnitude or confidence data path is shown in  FIG. 12   b . The confidence values of the lvl(t k )&#39;s  502  are brought into the block c- 1  bits wide. They are converted to b- 1  bits wide in the resolution converter block RC  535 . If the most significant c-b bits are zero, then the least significant b- 1  bits are passed through unchanged. If any of the most significant bits are 1, then the least significant b- 1  bits are set to 1. In effect, if the input lvl(t k )  502  can be represented with b- 1  bits, then it is so represented, otherwise, it is set to the maximum value that can be represented with b- 1  bits. This output is input to a first minimum block  503  where both the minimum value, MinVal 1    507 , and it&#39;s location, “v”  529 , are found and stored for outputs. The Data_out  506  from the first minimum block  503  is the input  511  to the second minimum block  510 , where the second lowest value of the string of confidences is found. 
   The first sum block  517  takes MinVal 1    509  and MinVal 2    516  as inputs, with MinVal 1    509  as a negative input  519 . The output of the first sum block  517  is input to the f(x) block  520 . The f(x) block  520  has A function listed SUCH as 
             f   ⁡     (   x   )       =           3           2           1           0         ⁢           ⁢   for   ⁢           ⁢           x   &lt;   2               2   ≤   x   &lt;   4               4   ≤   x   &lt;   8               8   ≤   x                   
This output is input to the second sum block  521  as a negative input  522 . The other input is MinVal 1    509 . The output of this second sum block  521  is input to a comparator  523 , as well as input to a Mux  524 . The Mux  524  has a second input which is a zero value  527 . The comparator  523  tests to see if the input is greater than 0. The output of the comparator  523  is the select input of the Mux  524 . If the comparator  523  tests true, then the output of the second sum block  521  is passed to the output as the lvl(t k ) output  528 . If the comparator;  523  is false, then the zero input  527  is passed to the output as the lvl(t k ) output  528 . Finally, MinVal 2    516  is passed to the output as the MIN(lvl(t k )) output for k equal to v.
 
   In summary, referring to  FIG. 3   a , when a row is being evaluated, all the differences associated with that row are removed from the current best estimates prior to evaluating the new differences. This result is also stored in the FIFO  259 . The new differences are stored in DA  257  and also added  260  with the output of the FIFO  259  prior to being stored back into CA  252 . For any row operation, this amounts to a replacement of the current estimate or the current difference with the new estimate or the new difference. 
     FIG. 3   a  shows a circuit that performs this function. 
   3. Expanded Code 
   The H-Matrix in  FIG. 1  can be viewed as a mother code. Each of the 1&#39;s in that H-Matrix can be replaced with an m×m permutation matrix and each zero can be replaced with an m×m zero matrix. This will allow the decoder to operate on sets of inputs m at a time. The decoder will access differences m at a time, current estimates will be accessed m at a time, and there will be m SISO&#39;s. The parameter m is known as the set size of the decoder. 
   As an example, let m=3. In such a case, there are 6 possible permutations, any of which can be used. These permutations are shown in  FIG. 4 , which also illustrates the effect of a permutation. For example, with Permutation P 2 , the input of abc is permuted to acb. An example of an expanded H-matrix with each of the permutations included is shown in  FIG. 5   a . In  FIG. 5   b , the 3×3 zeros have been blanked out for clarity. 
     FIG. 8  shows the effect of a permutation on a set that is already permuted. The columns of “A” permutations  361  are mapped against the rows of “B” permutations  362 . Thus, for example, if A permutation  361  is permutation P 2 , the second column, is followed by permutation P 3 , the B permutation  362  in the third row, that has the same effect as permutation P 4 . As another example, permutation P 3  followed by permutation P 2  has the same effect of permutation P 5 . If a block is sitting in permutation P x  and needs to be mapped to permutation P y , the table in  FIG. 8  can be used to determine the necessary permutation to apply. For example, if a block is in permutation P 4 , and needs to end up in permutation P 2 , looking at the table, it will be seen that permutation P 3  will give the desired result. As a second example, if a block is in permutation P 5  and needs to end up in permutation P 1 , then permutation P 4  will accomplish that result. 
   Each of the equations, the differences, the inputs and current estimates will be grouped in sets of m. Looking at the Matrix in  FIG. 5   b , row i,j , is the jth row in set Row i . Input i k,l  is the lth input in set I k . This grouping is shown in  FIG. 13 , and is analogous to the current estimate, which is shown in  FIG. 14 . Thus, referring to  FIG. 13 , input i k,l    552  is the lth input in set I k    553 ; referring to  FIG. 14 , input c k,l    560  is the lth current estimate in set C k    563 . The differences are also grouped into sets of m. The individual differences have been referred to as d i,k . The set of differences associated with Row i  and C k  are referred to as D i,k . There are m differences, again associated with the ones in the H-Matrix. 
   Another exemplary representation for the H-matrix is shown in  FIG. 6 . Each zero represents a 3×3 zero matrix, e.g.  331 , and each number represents the 3×3 permutation matrix, e.g.  332 , from  FIG. 4 . Thus, the number in  FIG. 6  refers to one of the six possible permutations, P 1  through P 6 , identified in  FIG. 4 . For example, in the first row and first column of  FIG. 6 , permutation  2 , or P 2 , is identified. In permutation  2 , the input “abc” is permuted to the output “acb”. The 3×3 matrix for P 2  is: 
   
     
       
             
             
             
           
         
             
                 
             
           
           
             
               1 
               0 
               0 
             
             
               0 
               0 
               1 
             
             
               0 
               1 
               0 
             
             
                 
             
           
        
       
     
   
   Finally, a third representation is listed in  FIG. 7 . In this case, each row  342  represents three equations. Each equation has 5 terms  341 , where the term (k,m)  343  indicates that it is input set k with permutation m. 
   The purpose of the decoder architecture is to allow parallel solution of equations and allowing for a wider memory structure and reads that are more than one input wide. The decoder shown in  FIG. 3   b  will accomplish this. The data paths are each m-inputs wide. The exemplary parallel architecture shown in  FIG. 3   b  illustrates parallelism by showing three parallel paths. These three parallel paths lead to three parallel SISO&#39;s,  258   1 ,  258   2 , and  258   3 . However, the use of three parallel paths is merely illustrative, and the invention may, and usually will, employ many more paths. Thus, the use of three paths in this disclosure is not limiting, but exemplary. 
   The DA  257  is the memory that holds all the D i,k &#39;s. They are in groups of m, and stored in the “proper” order, where the “proper” order means the permutation indicated by that permutation matrix of  FIG. 6 . Anytime a current estimate is brought to an adder  256   1-3  to have the differences subtracted, the current estimate is permuted to the same permutation as D i,k . As an example, the contents of D 0,0  for the matrix in  FIG. 5   b  are stored in the order {1,3,2}, as indicated by the permutation P 2 . 
   An example working through two complete iterations for the code defined by the H-Matrix in  FIG. 5   b  and the decoder of  FIG. 3   b  is given below. The first time an input is used, a mux  253   1-3  selects the input  251 ; for subsequent uses of that “input”, a mux  253   1-3  selects the CA  252 . Each of the inputs  251  arrives in permutation order P 1 . Each of the C i &#39;s also need to be permuted to the proper order. An I 0  is permuted by P 2  and presented to a SISO  258   1-3  as well as stored in a FIFO  259   1-3 . No difference is removed, as this is the initial pass through the decoder and the differences are all zero. The next inputs are I 1  permuted by P 3 , I 3  permuted by P 5 , I 5  permuted by P 1 , and I 9  permuted by P 4 . 
   Referring to  FIG. 5   b , and looking at just the equation represented by row 0,0 , it requires inputs i 0,0 , i 1,1 , i 3,1 , i 5,0  and i 9,2 . By the same token, the equation represented by row 0,1  requires inputs i 0,2 , i 1,0 , i 3,2 , i 5,1  and i 9,0  and the equation represented by row 0,2  requires inputs i 0,1 , i 1,2 , i 3,0 , i 5,2  and i 9,1 . Each of these inputs is presented to a proper SISO  258   1-3 , by the permutations referenced in the paragraph above. 
   The differences calculated by a SISO  258   1-3  are stored in the DA  257  as D 0,0 , D 0,1 , D 0,3 , D 0,5  and D 0,9 . These differences are also added  260   1-3  to the inputs stored in the FIFO  259   1-3  and stored back in the CA  252 . Note that the inputs are now stored back in the original location, but in a permuted form. 
   This exemplary architecture allows three SISO&#39;s,  258   1 ,  258   2 , and  258   3 , to operate in parallel. The inputs are read three at a time. 
   As the equations for the remaining ROW i &#39;s are evaluated, there is always a choice in taking the input from C k  or I k . If I k  has been used, then select C k . If I k  has not been used, then select I k . This can be seen by examining ROW 1 . I 1  has been used, so C 1  is selected by a mux  253   1-3 . C 1  needs to be permuted to P 6 . However, it is already permuted by P 3 . Permutation P 4  accomplishes this. Therefore, C 1  is permuted by P 4 . I 2  has not been used, so it is selected by the mux  253   1-3 . I 2  is permuted by P 4 , By the same token, I 4  has not been used, so I 4  is permuted by P 3 , I 5  has already been used, so C 5  is selected by the mux  253   1-3  and permuted by P 1 . I 6  has not been used, so I 6  is selected by the mux  253   1-3  and permuted by P 6 . Note that inputs I 2 , I 4  and I 6  were in their initial states, as they had not yet been permuted. With respect to the three SISO&#39;s, SISO 0    258   1  gets i 1,2 , c 2,2 , i 4,1 , c 5,0  and i 6,0 ; SISO 1    258   2  gets i 1,1 , c 2,0 , i 4,0 , c 5,1 and i   6,1 ; SISO 2    258   3  gets i 1,0 , c 2,1 , i 4,2 , c 5,2  and i 6,2 . 
   The differences d 1,1 , d 1,2 , d 1,4 , d 1,5  and d 1,6  are all initially zero. The new differences are stored in the DA  257 . The differences are also added  260   1-6  into the output of a FIFO  259   1-3 , which are then stored in the CA  252  as C 1 , C 2 , C 4 , C 5  and C 6  respectively. This continues for ROW 2 , ROW 3 , and ROW 4 , at which point each of the equations has been solved once. At this point, the DA  257  is filled with non-zero values. 
   In general, the proper permutation to perform on any C j  can be determined by looking at the H-Matrix of  FIG. 5   b . Each C j  is stored in the permutation required by the equation that used the C j  previously. As an example, to determine the proper permutation for C 4  in ROW 3  equation, it can be observed the prior use of C 4  is in Row 1 . The permutation that C 4  is stored in is P 3 . Permutation P 6  is required, and P 4  is the permutation that accomplishes this. A second example would be C 4  in ROW 2 . Except for the very first iteration, which has already been dealt with, C 4  will be stored in permutation P 4 , which is seen by looking at C 4  in ROW 4 . Permutation P 6  accomplishes the required permutation. 
   This architecture keeps the differences D i,k  in the permutation that is seen in the H-Matrix of  FIG. 5   b . The inputs are originally in permutation P 1 , which is no permutation. However, the permutation changes during the iterations. This can be seen in  FIGS. 9 and 10 .  FIG. 9  identifies the permutation that each of the CA blocks is stored in after each of the 5 iteration steps.  FIG. 10  shows the permutations for the DA memory. The required permutation at each step can be determined from these two figures. These document the permutation that the C k  is stored in, and the permutation that is needed.  FIG. 8 , as seen earlier, can be used to determine the proper P x  that is needed. For example, referring to  FIG. 9 , when working on ROW 3  equation, C 0  is stored in the P 4  permutation, which can be seen from the ROW  2  column. From  FIG. 10  it may be seen that D 3,0  is stored in the P 5  permutation. Referring to  FIG. 8 , it can be seen that by applying permutation P 4  to C 0 , it will be in the proper P 5  permutation. When the new C 0  is calculated, it is stored in the P 5  permutation. 
   To get the required outputs, everything needs to be permuted back to P 1 . At the end of the last iteration, C 0  and C 2  are stored in permutation P 5 , C 1  and C 3  are stored in permutation P 2 , C 4  is stored in permutation P 4  and the rest are stored in permutation P 1 . C 0  and C 2  are permuted by P 4 , C 1  and C 3  are permuted by P 2 , C 4  is permuted by P 5  and the rest are permuted by P 1 . This gets all the outputs into the required P 1  permutation. 
   4. Multiplicity Architecture 
   One of the conditions that can occur in a code is when the same set of inputs is used more than once in the same set of equations. The input sets will occur with different permutations. An example would be to replace the second term in ROW 0  with (3,4). The equation becomes
 
Row  I =(0,2)+(3,4)+(3,5)+(5,1)+(9,4)
 
   This requires I 3  to be used twice in the first iteration, followed by C 3  being used twice in subsequent iterations. The terms (3,4) and (3,5) are called “multiplicities” and occur when the same set of inputs are used in the same equations more than once. When this occurs, the input set will always occur with different permutations. There is a difference stored in the DA for each of these permutations. In the above example, the first difference has permutation P 4 , and the second difference has permutation P 5 . D 4   0,3  will represent the difference set D 0,3  with permutation P 4  and D 5   0,3  will represent the difference set D 0,3  with permutation P 5 . In general, Dy i,k  will represent the set associated with the equation for ROW i  and the input set C k  in permutation P y . Each of these is a separate set of differences, and will be stored separately in the DA  257 . However, both differences require the same input, which is not permitted. In the first iteration, the input vector I  251  will be selected by the mux  253 , and in subsequent iterations the current estimates C will stored in the CA  252  will be selected by a mux  253   1-3 . The output of the mux  253  minus the first difference will be stored in a FIFO  259   1-3 , as well as the output of the mux  253   1-3  minus the second difference. After doing multiple operations on the same C k  in the same iteration, the decoder in  FIG. 3   b  is not capable of storing the proper value back in the CA  252 . This is remedied by adding a feedback path, which is shown in  FIG. 15 .  FIG. 15  shows an exemplary parallel system of width m. Thus, the system may use m parallel SISO&#39;s  258  to receive inputs from m paths. Similarly, the system may use m parallel mux&#39;s  253 , m parallel adders  611 , etc. In this way,  FIG. 15  illustrates the parallelism of the present architecture in a manner distinct from the parallelism illustrated in  FIG. 3   b.    
   When processing ROW 0  for the first time, the first input is I 0  with a permutation of P 2 . The second input is I 3  with a permutation of P 4 . The third input is I 3 , but with a permutation of P 5 . The fourth and fifth inputs are I 5  and I 9  with permutations of P 1  and P 4  respectively. The inputs to a FIFO  259  are also different when dealing with repetitive sets in the same equation. The first time a set element is seen, the FIFO  259  receives I 3 −D 4   0,3 . Recognize that D 4   0,3  is zero, as this is the first pass, and the differences are initialized originally to zero. The next input  251  to the FIFO  259  will be (−D 5   0,3 ). Again, D 5   0,3  is equal to zero. Also, D 5   0,3  is stored in a different location in the DA  257  than D 4   0,3 , which allows for the retention of both values. When I 3 −D 4   0,3  is output from the FIFO  259 , the other input to the adder  615  will be equal to zero. The output of adder  1   615  goes to adder  2   616 . The new D 4 ′ 0,3 , which is output from the SISO  258 , is added to the output of adder  1   615  using adder  2   616 . This goes to the second permutation block  617 , where it is permuted to P 5 . Referring to  FIG. 8 , it can be seen that this is accomplished with permutation P 4 . This is added  615  to the negative of the original difference −D 5   0,3  as it is output from the FIFO  259 , and added by adder  616  to the new difference D 5 ′ 0,3 . This result is stored into the CA  252  in location C 3 . The value that is stored is:
 
 C′   3   =C   3   −D 4 0,3   +D 4′ 0,3 +(− D 5 0,3 )+ D 5′ 0,3 
 
This shows that both differences have been updated with the new values.
 
   For subsequent iterations, C 3  will be stored in permutation P 2 . In that case, when ROW 0  is evaluated, C 3  will first be brought in with permutation P 3 , and second brought in with permutation P 6  to get the required permutations of P 4  and P 5  respectively. 
   In the multiplicity architecture shown in  FIG. 15 , the second permutation block  617  feeds a permuted version of the output of adder  2   616  back to be accumulated with the output of FIFO  259 . In an alternative embodiment, the second permutation block  617  includes a delay. This delay provides the ability to pick more precisely the time of the feedback. 
   5. Processor Architecture 
   The architecture disclosed here arranges components as discrete components, but this is illustrative and not intended to be limiting.  FIGS. 3   a ,  3   b  and  15  show the SISOs, FIFOs, DA, adders and CA, as separate blocks for illustrative purposes. This should not be construed as requiring a decoder with discrete components for these functions. For example, a decoder processor could integrate the SISO  258 , FIFO  259  and second adder  260  of  FIG. 3   a  into a single processor, or it could separate these functions into discrete components, and both arrangements would fall within the understanding of the invention disclosed and claimed here. Similarly, for example, the difference and new estimate functions of the SISO could be separated or integrated, and each arrangement would fall within the scope of the present invention. 
   The figures and description set forth here represent only some embodiments of the invention. After considering these, skilled persons will understand that there are many ways to make an LDPC decoder according to the principles disclosed. The inventors contemplate that the use of alternative structures or arrangements which result in an LDPC decoder according to the principles disclosed, will be within the scope of the invention.