Abstract:
In a master-slave type flip-flop circuit, a plurality of bipolar type transistors are used for master and slave flip-flop circuits, and transistors are connected such that glitch noise can be prevented under all input conditions.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a master-slave type flip-flop circuit, and more particularly, a master-slave type flip-flop circuit, with set and reset terminals, which is constituted by an emitter coupled logic circuit (hereinafter termed ECL). 
     The master slave type flip-flop circuit generally comprises a master flip-flop circuit and a slave flip-flop circuit. The output terminal of the master flip-flop circuit is connected to the input terminal of the slave flip-flop circuit. A data input signal is supplied to the input terminal of the master flip-flop circuit, while a data output signal is obtained at the output terminal of the slave flip-flop circuit. The master and slave flip-flop circuits are operated by a common clock signal so that when one of the flip-flop circuits is brought to a state in which the input signal can be written, the other flip-flop circuit becomes a state in which the present state can be maintained. 
     In the master-slave type flip-flop circuit which is constituted by ECL, when the clock pulse is at the low (&#34;L&#34;) or high (&#34;H&#34;) level the master flip-flop circuit is rendered to a write state in which data is written, and the slave flip-flop circuit is rendered to become a holding state, whereas when the clock pulse is at the &#34;H&#34; (or &#34;L&#34;) level the slave flip-flop circuit is rendered to a write state in which the output signal of the master flip-flop circuit is written. 
     In a master-slave type flip-flop circuit utilizing a set signal or a reset signal in addition to a clock signal, the set or reset signal is supplied to both the master and slave flip-flop circuits. When the set or reset input is enabled, irrespective of the state of the clock input, the slave flip-flop circuit would be forcibly turned to the write state. 
     As an example of the prior art circuit, FIG. 1 shows a circuit of a D type master-slave flip-flop circuit with a reset terminal and constituted by an ECL. FIG. 2 is a simplified block diagram of the circuit shown in FIG. 1 in which A designates a master flip-flop circuit, B a slave flip-flop circuit, and G an OR gate circuit. 
     In the circuit shown in FIGS. 1 and 2, a reference numeral 1 designates an input terminal of a clock signal CLK, 2 an input terminal of a reset signal RST, 3 an input terminal of a data signal D, 8 a high potential side source input terminal, 9 a low potential side source input terminal and 10 a reference voltage input terminal. 
     The master flip-flop circuit is constituted by transistors Q 3  through Q 11 , resistors R 1 , R 2 , R 6   and R 7  and a transformer 41, while the slave flip-flop circuit is constituted by transistors Q 13  -Q 21 , resistors R 3 , R 4 , R 9  and R 10  and transformer 42. 
     The master and slave flip-flop circuits have the same fundamental construction. In the following table, transistors of master and slave flip-flop circuits are shown with common transistor numbers. 
     
                       TABLE______________________________________      Master F/F               Slave F/F______________________________________Tr.sub.1     Q.sub.7    Q.sub.18Tr.sub.2     Q.sub.8    Q.sub.17Tr.sub.3     Q.sub.3    Q.sub.19Tr.sub.4     Q.sub.4    Q.sub.16Tr.sub.5     Q.sub.9    Q.sub.13Tr.sub.6     Q.sub.5    Q.sub.15Tr.sub.7     Q.sub.11   Q.sub.21Tr.sub.8     Q.sub.10   Q.sub.20Tr.sub.9     Q.sub.6    Q.sub.14______________________________________ 
    
     In FIG. 1, the connections among various transistors of the master and slave flip-flop circuits are as follows. 
     More particularly, transistors Tr 1  and Tr 2  are paired with their collector electrodes connected to the positive source terminal 8, and emitter electrodes connected to the negative source terminal 9 via resistors (in the master flip-flop circuit, resistors R 7  and R 6 , and in the slave flip-flop circuit, resistors R 9  and R 10 . The emitter electrodes of transistors Tr 1  and Tr 2  are connected to output terminals 4, 5, and 6, 7 of respective flip-flop circuits. The base electrodes of transistors Tr 1  and Tr 2  are connected to two current paths. Thus, the base electrode of transistors Tr 1  is connected to the positive source terminal 8 via resistor R 1  or R 4  and to the collector electrodes of transistors Tr 3  and Tr 4 . The base electrode of transistor Tr 2  is connected to the source terminal 8 via resistors R 2  or R 3 , and to the collector electrodes of transistors Tr 5  and Tr 6 . 
     The emitter electrode of transistor Tr 1  is connected to the base electrode of transistor Tr 6 , while the emitter electrode of transistor Tr 2  is connected to the base electrode of transistor Tr 4 . The emitter electrodes of transistors Tr 4  and Tr 6  are commonly connected to the collector electrode of transistor Tr 8 . The emitter electrodes of transistors Tr 3  and Tr 5  are commonly connected to the emitter electrodes of transistor Tr 7 . The emitter electrodes of transistors Tr 7  and Tr 8  are connected to the source terminal 9 via transformer 41 or 42. 
     The base electrode of transistor Tr 9  with its collector electrode connected to the collector electrode of transistor Tr 6  is connected to the reset signal input terminal 2. The emitter electrode of transistor Q 6 , that is the transistor Tr 9  of the master flip-flop circuit, is connected to the collector electrode of transistor Q 10  together with the emitter electrode of transistor Q 5 , that is transistor Tr 6 , while the emitter electrode of transistor Q 14 , that is transistor Tr 9  of the slave flip-flop circuit, is connected to the collector electrode of transistor Q 21  together with the emitter electrode of transistor Q 13 , that is transistor Tr 5 . 
     In the master and slave flip-flop circuits having constructions as above described, the output terminals 4 and 5 of the master flip-flop circuits are respectively connected to the base electrodes of transistors Q 19  and Q 13  at the input terminals of the slave flip-flop circuit. 
     The base electrode of transistor Q 3  at one input terminal of the master flip-flop circuit is connected to the data signal input terminal 3, and a reference voltage input terminal 10 is connected to the base electrode of transistor Q 9  at the other input terminal. 
     The reference voltage input terminal 10 is also connected to the base electrode of transistor Q 12 . The collector electrode of transistor Q 12  is connected to the positive source terminal 8, and the emitter electrode is connected to the base electrodes of transistors Q 11  and Q 20  and to the negative source terminal 9 via resistor R 8 . Transistor Q 12  is turned ON by the reference voltage so that the junction 12 between the emitter electrode of transistor Q 12  and resistor R 8  is at the &#34;H&#34; level with the result that transistor Q 11  and Q 20  are turned ON. When the transistor Tr 7  is turned ON as a result of the connection described above, the master flip-flop circuit or the slave flip-flop circuit is in a writable state, whereas when transistor Tr 7  is OFF, these flip-flop circuits do not accept an input signal. 
     Transistors Q 1  and Q 2  are connected in parallel with their collector electrodes connected to the source terminal 8, and the emitter electrodes connected to the source terminal 9 via resistor R 5 . The base electrode of transistor Q 1  is connected to the input terminal 1 receiving the clock signal CLK, and the base electrode of transistor Q 2  is connected to the input terminal 2 receiving a reset signal RST. With this connection, a signal S 11  corresponding to the logic sum of signals CLK and RST appears at a junction 11 between the emitter electrodes of transistors Q 1  and Q 2 . Thus this circuit constitutes the OR gate circuit G shown in FIG. 2. The output terminal of the OR gate circuit G, that is the junction 11 is connected to the base electrodes of transistors Q 10  and Q 21  of the master and slave flip-flop circuits respectively. 
     The master-slave type flip-flop circuit connected as described above operates as follows: 
     Signals Q M  and Q M  at output terminals of the master flip-flop circuit are complementary with each other. Signals Q and Q at the output terminals 6 and 7 of the slave flip-flop circuit are also complementary with each other. 
     FIG. 3A-3F are timing charts along the same time axis and show signals CLK, RST, D, S 11 , Q M  and Q at respective terminals 1, 2, 3, 11, 4 and 6. Before a time t A , clock signal CLK, reset signal RST, data signal D, signal S 11  at the junction 11, and the signal Q M  at the output terminal 4 of the master flip-flop circuit are all at the &#34;L&#34; level, while signal Q at the output terminal 6 is at the &#34;H&#34; or &#34;L&#34; level (shown by dotted lines). The signal REF applied to the base electrode of transistor Q 12  is at the &#34;H&#34; level so that transistors Q 11  and Q 20  with their base electrodes connected to junction 12 are turned ON. Since signals CLK and RST are both at the &#34;L&#34; level, the signal S 11  the junction 11 is at the &#34;L&#34; level, thus turning OFF transistors Q 10  and Q 21 . Since the signal RST is at the &#34;L&#34; level, the base electrodes of transistors Q 6  and Q 14  are at the &#34;L&#34; level so that these transistors are turned OFF. 
     When the data input signal D reaches the &#34;H&#34; level at time t A , transistor Q 3  is turned ON and then transistor Q 9  is turned OFF. Consequently, the base potential of transistor Q 8  becomes the &#34;H&#34; level so that transistor Q 8  is turned ON, whereby the level of the signal Q M  at terminal 4 becomes &#34;H&#34; (the level of signal Q M  at terminal 5 becomes &#34;L&#34;). At this time since the transistor Q 21  of the slave flip-flop circuit is OFF, irrespective of the variation of signal Q M , the conduction states of transistors Q 17  and Q 18  of the slave flip-flop circuit would not be changed. As a result, the levels of the output signals Q and Q are not changed (&#34;H&#34; or &#34;L&#34;). Thus, the slave flip-flop circuit is at the holding state. 
     Then when the reset signal RST reaches the &#34;H&#34; level at time t B  the output signal S 11  of the OR gate circuit G builds up for turning ON transistors Q 10  and Q 21  so that the state of the master flip-flop circuit changes to the holding state, while at the same time, the state of the slave flip-flop circuit changes to the writing state. At this time, since signal RST becomes the &#34;H&#34; level to turn ON transistor Q 6 , the level of signal Q M  changes to &#34;L&#34;. At this time, in a period before the output signal Q M  reaches the &#34;L&#34; level, both signals RST and Q M  become &#34;H&#34; level, whereby the transistors Q 14  and Q 19  of the slave flip-flop circuit become ON. As a consequence, the output signals Q and Q at the output terminals 6 and 7 momentarily change to a threshold level. Due to this variation of the output signals Q and Q, as shown in FIG. 3F, when the previous state of the output signal Q is at the &#34;H&#34; level, the operation is normal. However, if the previous state of the data output signal Q were &#34;L&#34; level, a glitch noise as shown by n 1  in FIG. 3F would be generated. The same is true for the data output signal Q. Consequently, if signal Q or Q were used as a clock input signal or a set input signal or a reset input signal for the circuit of a next stage, there would be a danger of causing the next stage circuit to malfunction. 
     Although the foregoing description concerns to the operation of a D type flip-flop circuit with a reset terminal, the same phenomenon occurs in a D type flip-flop circuit with a set terminal, and other type master-slave type flip-flop circuits with set or reset terminals. 
     As above described, in the prior art master-slave type flip-flop circuit with a set or reset terminal, under a certain input condition, glitch noise is formed in the output, the glitch noise reaching a threshold value. For this reason, the prior art master-slave type flip-flop circuit is subjected to a large limitation at the time of practical use. Especially, there is a problem that the output can not be used as a clock input signal, or a set input signal and a reset input signal for the circuit of the next stage. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide an improved master-slave type flip-flop circuit not forming a glitch noise in the output under all input conditions. 
     According to this invention there is provided a master slave type flip-flop circuit comprising a clock input terminal supplied with a clock signal; a data input terminal supplied with a data signal; a data output terminal outputting stored data; an output control terminal supplied with an output control data that determines the level of an output signal; a master flip-flop circuit with an input terminal connected to the data input terminal; a slave flip-flop circuit with an input terminal connected with an output terminal of the master flip-flop circuit and an output terminal connected with the data output terminal; a logic circuit inputted with the clock signal and the output control signal; each of the master and slave flip-flop circuits including a first control terminal supplied with an operating state control signal which brings the master and slave flip-flop circuits to a writable state or a holding state; a second control terminal supplied with the output control signal; means for connecting the output terminal of the logic circuit to the first control terminal of the master flip-flop circuit; means for connecting the clock terminal to the first control terminal of the slave flip-flop circuit; and means for connecting the output control terminal to the second control terminals of the master and slave flip-flop circuits. 
     The master-slave type flip-flop constituted as described above can prevent glitch noise under all input conditions. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIG. 1 is a connection diagram showing a prior art master-slave type flip-flop circuit; 
     FIG. 2 is a simplified block diagram of the prior art circuit shown in FIG. 1; 
     FIGS. 3A through 3G are timing charts showing the wave forms of the signals of important elements shown in FIG. 1; 
     FIG. 4 is connection diagram showing one embodiment of the master-slave type flip-flop circuit according to this invention; 
     FIG. 5 is a simplified block diagram of the circuit shown in FIG. 4, and 
     FIGS. 6A through 6G are timing charts showing the wave forms of the signals of important elements of the circuit shown in FIG. 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIGS. 4 and 5 elements identical to those shown in FIGS. 1 and 2 are designated by the same reference characters. The master flip-flop circuit and the slave flip-flop circuit have the same construction as those shown in FIG. 1 except the followings: In the circuit shown in FIG. 4, to the input terminal 1 of clock signal CLK are connected the base electrodes of transistors Q 1  and Q 2  and the base electrode of transistor Q 23 . The collector electrode of transistor Q 23  is connected to the positive source terminal 8 together with the collector electrodes of transistors Q 1  and Q 2 , while the emitter electrode is connected to the negative source terminal 9 via resistor R 11  and to the base electrode of transistor Q 21 . 
     The output terminal 11 of the OR gate circuit G made up of transistors Q 1  and Q 2  is connected to the base electrode of transistor Q 10 . The emitter electrode of transistor Q 14  of the slave flip-flop circuit is connected to the emitter electrodes of transistors Q 15  and Q 16  and to the collector electrode of transistor Q 20 . 
     The state transfer signal S 11  of the master flip-flop circuit is obtained at the output terminal 11 of the OR gate circuit G inputted with the clock signal CLK and the reset signal RST, while the state transfer signal S 12  of the slave flip-flop circuit is obtained from the emitter electrode of transistor Q 23 . Consequently transistor Q 21  is turned ON or OFF when the signal CLK is at the &#34;H&#34; or &#34;L&#34; level, and transistor Q 10  is turned ON except a time at which the levels of signals RST and CLK are both &#34;L&#34;. 
     The operation of the master flip-flop circuit shown in FIGS. 4 and 5 is as follows: FIGS. 6A-6F show examples of the wave forms of signals CLK, S 12 , RST, D, S 11 , Q M  and Q at terminals 1, 12, 2, 3, 11, 4 and 6 of the master flip-flop circuit, along the same time axis shown in FIG. 6G. These wave forms show a case wherein the clock signal CLK is at the &#34;L&#34; level, that is the signal S 12  is at &#34;L&#34; level so that the slave flip-flop circuit is in the holding state. 
     Before time t A , each of signals RST, D, S 11  and Q M  is at the &#34;L&#34; level and the output signal Q is at the &#34;H&#34; or &#34;L&#34; level. 
     When the data signal D becomes the &#34;H&#34; level at time t A , transistor Q 3  is turned ON with the result that a current path including source terminal 8, resistor R 1 , transistors Q 3  and Q 11 , transformer 41 and source terminal 9 would be established. As a consequence, the base voltage of transistor Q 7  decreases so that the level of the signal Q M  at the emitter electrode 5 changes to &#34;L&#34;. At the same time transistor Q 9  is turned OFF so that the level of the voltage Q M  at the emitter electrode 4 of transistor Q 8  becomes &#34;H&#34;. 
     As above described, since transistor Q 21  of the slave flip-flop circuit is in the OFF state, the slave flip-flop circuit is in the holding state irrespective whether terminals 4 and 5 are at the &#34;H&#34; or &#34;L&#34; level. Accordingly, the output signals Q and Q maintain their previous values. 
     Then at time t B  when the reset signal RST reaches the &#34;H&#34; level, signal S 11  builds up, thus turning ON transistor Q 6  and Q 10 , whereby a current path including source terminal 8, resistor R 2 , transistors Q 6  and Q 10 , transformer 41 and source terminal 9 is establisned. Consequently the base voltage of transistor Q 8  decreases so that the level of the signal Q M  at the emitter 4 changes to &#34;L&#34;. Following this, the level of the voltage QHD M becomes &#34;H&#34;. 
     However, since the slave flip-flop is in the holding state, the outputs Q M  and Q M  of the master flip-flop circuit would not be affected. 
     As the reset signal RST reaches the &#34;H&#34; level, transistor Q 14  of the slave flip-flop circuit is turned ON for establishing a current path including resistor R 3 , transistors Q 14  and Q 20  and transformer 42. 
     Consequently, where output signals Q and Q are at &#34;H&#34; and &#34;L&#34; levels respectively, that is when transistor Q 16  is ON and transistor Q 15  is OFF, upon turning ON of transistor Q 14 , the level of the signal Q at output terminal 6 becomes &#34;L&#34;. Concurrently therewith, transistor Q 16  is turned OFF and hence the base voltage of transistor Q 18  increases so that the level of signal Q at the output terminal becomes &#34;H&#34;. 
     Where the levels of signals Q and Q at output terminals 6 and 7 are at &#34;L&#34; and &#34;H&#34; respectively, in other words when transistor Q 16  OFF and when transistor Q 15  is ON, conduction of transistor Q 14  does not cause any influences so that output signals Q and Q maintain their voltage levels as they are. 
     For the reason described above, the glitch noise inevitable in the prior art circuit shown in FIG. 1, can be eliminated with the embodiment shown in FIG. 4. 
     Although in the foregoing, a case wherein the clock signal CLK is at the &#34;L&#34; level, and when the signal CLK is at the &#34;H&#34; level, transistor Q 21  becomes ON whereby the slave flip-flop circuit becomes the write state. Turning ON and OFF of transistors Q 17  and Q 18  are determined by the ON, OFF states of transistors Q 13  and Q 19 , in other words by the output signals Q M  and Q M  of the master flip-flop circuit applied to the base electrodes of transistors Q 13  and Q 19 . Accordingly, in this case, there is no problem of glitch noise. 
     Although the embodiment described above concerns a D type flip-flop circuit with a reset terminal, according to this invention even in a D type master-slave type flip-flop circuit with a set terminal and in other type master-slave type flip-flop circuits, the same advantageous effect can be obtained.