Abstract:
A finFET, a method of fabricating the finFET and a design structure of the finFET. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The finFET includes a body contact between the silicon body of the finFET and the substrate.

Description:
[0001]     This Application is a continuation-in-part and claims priority of copending U.S. patent application Ser. No. 11/427,486 filed on Jun. 29, 2006. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to the field of semiconductor devices; more specifically, it relates to finFETs, methods of fabricating finFETs and design structures for finFETs.  
       BACKGROUND OF THE INVENTION  
       [0003]     FinFET (fin field-effect-transistor) is an emerging technology, which allows smaller and higher performance devices. FinFET structures comprise narrow isolated bars of silicon (fins) with a gate(s) on the sides of the fin. Prior art finFET structures are formed on silicon-on-insulator (SOI) substrates. However, finFETs fabricated on SOI substrates suffer from floating body effects. The floating body of a finFET on an SOI substrate stores charge, which is a function of the history of the device. As such, floating body finFETs experience threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-Vt leakage and Vt mismatch among geometrically identical adjacent devices. FinFETs fabricated on bulk silicon substrates do not experience floating body effects, but they do experience greatly increased source/drain to substrate capacitance. Increased source-drain to substrate capacitance is a parasitic effect, which degrades performance (speed).  
         [0004]     Therefore, there is a need for finFET devices and methods of fabricating finFET devices without floating body effects and with reduced parasitic capacitance.  
       SUMMARY OF THE INVENTION  
       [0005]     A first aspect of the present invention is a structure comprising: a finFET having a silicon body formed on a bulk silicon substrate; a body contact between the silicon body and the substrate; and first and second source/drains formed in the silicon body and insulated from the substrate by a dielectric layer under the fins.  
         [0006]     A second aspect of the present invention is a structure, comprising: a single crystal silicon fin extending in a first direction parallel to a top surface of a bulk silicon substrate, the fin having a channel region between first and a second source/drains; an electrically conductive gate electrode extending in a second direction parallel to the top surface of the substrate and crossing over the channel region, the second direction different from the first direction; a gate dielectric between the gate electrode and the fin; at least a portion of the channel region of the fin in direct physical and electrical contact with the substrate; and a dielectric layer between at least a portion of the first source/drain and the substrate and between at least a portion of the second source/drain and the substrate.  
         [0007]     A third aspect of the present invention is a method, comprising: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0008]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0009]      FIGS. 1A through 1F  are cross-sectional views illustrating initial steps in the fabrication of finFETs according to embodiments of the present invention;  
         [0010]      FIG. 2  is a three dimensional isometric view of the structure illustrated in  FIG. 1F ;  
         [0011]      FIG. 3  is a three dimensional isometric view of the structure illustrated in  FIG. 2  after additional fabrication steps;  
         [0012]      FIG. 4  is a top view and  FIGS. 5A, 5B ,  5 C and  5 D are cross-sectional views through respective lines  5 A- 5 A,  5 B- 5 B,  5 C- 5 C and  5 D- 5 D of the structure illustrated in  FIG. 3 ;  
         [0013]      FIG. 6  is a top view and  FIGS. 7A, 7B ,  7 C and  7 D are cross-sectional views through respective lines  7 A- 7 A,  7 B- 7 B,  7 C- 7 C and  7 D- 7 D of the structure illustrated in respective  FIGS. 4, 5A ,  5 B,  5 C and  5 D after additional processing;  
         [0014]      FIG. 8  is a top view and  FIGS. 9A, 9B ,  9 C and  9 D are cross-sectional views through respective lines  9 A- 9 A,  9 B- 9 B,  9 C- 9 C and  9 D- 9 D of the structure illustrated in respective  FIGS. 6, 7A ,  7 B,  7 C and  7 D after additional processing;  
         [0015]      FIG. 10  is a top view and  FIGS. 11A, 11B ,  11 C and  11 D are cross-sectional views through respective lines  11 A- 11 A,  11 B- 11 B,  11 C- 11 C and  11 D- 11 D of the structure illustrated in respective  FIGS. 8, 9A ,  9 B,  9 C and  9 D after additional processing; and  
         [0016]      FIG. 12  is a flow diagram of a design process used in semiconductor design, manufacturing, and/or test. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]      FIGS. 1A through 1F  are cross-sectional views illustrating initial steps in the fabrication of finFETs according to embodiments of the present invention. In  FIG. 1A , formed on a bulk silicon substrate  100  is a pad silicon oxide layer  105  and formed on the pad oxide layer is a pad silicon nitride layer  110 . A bulk silicon substrate is defined as a monolithic block of single-crystal-silicon. Formed through pad silicon oxide layer  105  and pad silicon nitride layer  110  is a dielectric shallow trench isolation (STI)  115 . An optional dielectric liner  120  around the sides and bottom surfaces, but not the top surface, of STI  115  is shown. STI  115  may be formed, by photolithographically defining openings in the pad silicon oxide  105  and silicon nitride  110  layers, etching (for example, by reactive ion etch (RIE)) a trench into substrate  100  where the substrate is not protected by the pad layers, backfilling the trenches with dielectric and performing a chemical-mechanical-polish (CMP) so a top surface of the STI is co-planar with a top surface of the pad silicon nitride layer.  
         [0018]     In one example, pad oxide layer  105  is formed by thermal oxidation of substrate  100  and between about 5 nm and about 20 nm thick. In one example, pad silicon nitride layer  110  is formed by chemical-vapor-deposition (CVD) and is between about 50 nm and about 500 nm thick. In one example, STI  115  comprises a CVD oxide such as tetraethoxysilane (TEOS) or high-density-plasma (HDP) oxide. In one example, liner  120  comprises less than 50 nm of silicon oxide, silicon nitride or a dual layer of silicon oxide under silicon nitride. In one example, STI  115  is between about 50 nm and about 500 nm thick. Pad silicon nitride layer  110  is then stripped selective to oxide and STI  115  is planarized to be approximately flush with the top surface of pad oxide layer  105 .  
         [0019]     In  FIG. 1B , an etch stop layer  125  is deposited over pad silicon oxide  110 , STI  115  and exposed edges of liner  120  if present, and a mandrel layer  130  is deposited over the etch stop layer. In one example, etch stop layer comprises CVD silicon nitride and is between about 2 nm and about 10 nm thick. In one example, mandrel layer  130  is CVD oxide described supra, and is between about 100 nm and about 500 nm thick. The thickness of mandrel layer determines the height of the silicon fin (above the current bulk silicon  100 /pad silicon oxide layer  125  interface) that will be formed subsequently.  
         [0020]     In  FIG. 1C , a trench  135  is etched through mandrel layer  130  and etch stop layer  125  to expose substrate  100  in the bottom of the trench. In one example, trench  135  has a width “W” of between about 20 and about 100 nm wide. The width “W” defines the width of the silicon fin (less any subsequent sidewall oxidations, if any) to be subsequently formed.  
         [0021]     In  FIG. 1D , a single-crystal silicon fin  140  covered by a cap  145  is formed in trench  135 . Fin  140  may be formed by selective epitaxial growth to above the top surface of mandrel layer  130  followed by planarization and a recess RIE. In one example, the top of fin  140  is recessed between about 20 nm and about 100 nm below the top surface of mandrel layer  130 . In one example, cap  145  may be formed by CVD deposition of silicon nitride of sufficient thickness top overfill the recess followed by a CMP so a top surface of cap  145  is coplanar with a top surface of mandrel  130 . Alternatively, a polysilicon fin may be formed instead of a single-crystal silicon fin.  
         [0022]     In  FIG. 1E , mandrel  130  (see  FIG. 1D ) is removed. In one example, when mandrel layer  130  is oxide and cap  145  and etch stop layer  125  are silicon nitride, the mandrel is removed with an RIE selective to etch oxide faster than silicon nitride. Alternatively, mandrel layer  130  may be removed by a wet etching process (i.e. aqueous hydrofluoric acid when mandrel  130  is a silicon oxide). Then etch stop layer  125  is removed with a RIE selective to etch silicon nitride faster than silicon oxide, in which case cap  145  (see  FIG. 1D ) is thinned to form cap  145 A.  
         [0023]     In  FIG. 1F , a gate dielectric layer  150  is formed on the sidewalls of fin  140 . In the present example, gate dielectric  150  is a thermally grown silicon oxide, so a thin region of exposed substrate  100  is also oxidized. Alternatively, gate dielectric  150  may be deposited. In the example of a deposited gate dielectric, gate dielectric  150  may be a high K (dielectric constant) material, examples of which include but are not limited metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high K dielectric material has a relative permittivity above about 10. In one example, gate dielectric  150  is between about 0.5 nm and about 20 nm thick.  
         [0024]     Next a gate  155  is formed crossing over fin  140  and a capping layer  160  formed on the top (but not the sidewalls of the gate (see  FIG. 2 ). In one example, gate  155  comprises doped or undoped polysilicon or a highly silicided metal layer and is at least thick enough to cover the sidewalls of fin  140 . In one example, capping layer  160  is silicon nitride and is between about 100 nm and about 500 nm thick.  
         [0025]      FIG. 2  is a three dimensional isometric view of the structure illustrated in  FIG. 1F . In  FIG. 2 , gate  155  and capping layer cross fin  140 . In one example, fin  140  and gate  155  are orthogonal to each other. In one example, fin  140  and gate  155  may cross at an angle defined by a crystal plane of the fin. In one example, gate  155  and capping layer  160  are formed by blanket CVD deposition of the gate, followed by a CMP, followed by blanket CVD deposition of the capping layer followed by a photolithographic and etch process to define the gate and capping layer.  
         [0026]      FIG. 3  is a three dimensional isometric view of the structure illustrated in  FIG. 2  after additional fabrication steps. In  FIG. 3 , source/drains  180  are formed by ion implantation and then a first protective layer  165  is formed on the exposed sidewalls of fin  140  and gate  155 , a second protective layer  170  formed over first protective layer  165  on the sidewalls of gate  155  and a spacer  175  formed on top edges of first and second protective layers  165  and  170  adjacent to capping layer  160 . Formation of first and second protective layers  165  and  170  and spacer  175  may be accomplished, in one example by:  
         [0027]     performing a blanket CVD deposition of silicon nitride to form a blanket of layer first protective layer  165 ;  
         [0028]     (2) performing a blanket deposition of a CVD oxide (as described supra) to form a blanket layer of second protective layer  170  over the blanket of layer first protective layer  165 ;  
         [0029]     (3) performing a CMP of the CVD oxide to expose capping layer  160 ;  
         [0030]     (4) performing a RIE recess etch to recess the CVD oxide below the top surface of capping layer  160 ;  
         [0031]     (5) performing a blanket CVD silicon nitride deposition followed by a spacer RIE to form spacers  175 ; and  
         [0032]     (6) performing a RIE to remove all CVD oxide not protected by spacers  175 .  
         [0033]      FIG. 4  is a top view and  FIGS. 5A, 5B ,  5 C and  5 D are cross-sectional views through respective lines  5 A- 5 A,  5 B- 5 B,  5 C- 5 C and  5 D- 5 D of the structure illustrated in  FIG. 3 . It should be noted in  FIGS. 5B, 5C  and  5 D that the boundaries of source/drains  180  are indicated by the small-dash dashed lines. In  FIGS. 5A and 5D , the interface between substrate  100  and fin  140  is indicated by the large-dash dashed line even though this interface is not detectable since the fin was grown epitaxially. It is shown for reference purposes. Also in  FIGS. 5A and 5D , a channel region  185  exists under gate  155  in fin  140 .  
         [0034]      FIG. 6  is a top view and  FIGS. 7A, 7B ,  7 C and  7 D are cross-sectional views through respective lines  7 A- 7 A,  7 B- 7 B,  7 C- 7 C and  7 D- 7 D of the structure illustrated in respective  FIGS. 4, 5A ,  5 B,  5 C and  5 D after additional processing.  FIGS. 7A and 7D  are identical to respective  FIGS. 5A and 5D . In  FIGS. 6, 7B  and  7 C a trench  7 C has been etched into substrate  100  a depth “D” using, for example, an RIE selective to etch silicon faster than silicon dioxide and silicon nitride wherever the substrate is exposed (see  FIGS. 4, 5B  and  5 C). In one example “D:” is between about 50 nm and about 250 nm. In one example, “D” is about one half the thickness of STI  115  (or the thickness of STI  115  and liner  120 , if liner  1120  is present). Fin  140  is protected from etching by cap  145 A, gate dielectric  150  and protective layer  165  while gate  155  is protected from etching by first and second protective layers  165  and  170  as well as cap  160  and spacers  175 .  
         [0035]      FIG. 8  is a top view and  FIGS. 9A, 9B ,  9 C and  9 D are cross-sectional views through respective lines  9 A- 9 A,  9 B- 9 B,  9 C- 9 C and  9 D- 9 D of the structure illustrated in respective  FIGS. 6, 7A ,  7 B,  7 C and  7 D after additional processing.  FIG. 9A  is identical with  FIG. 7A . In  FIGS. 8, 9B ,  9 C and  9 D a wet etch of silicon has been performed to enlarge trench  190  (see,  FIGS. 7B and 7C ) to form trench  190 A and undercut fin  140  in source/drains  180  leaving a pedestal  195  of silicon connecting fin  140  to substrate  100  in channel region  185 . Pedestal  195  has an edge  200  indicated by the dashed line in  FIG. 8 . Depending upon the amount of undercutting, source/drain regions  180  may be completely or partially undercut and the cross-sectional area of pedestal  195  may vary. There may or may not be undercutting of channel region  185 . As an example, channel region  185  is partially undercut and the source/drains (not shown in  FIG. 9D ) are completely undercut and not present in  FIG. 9D . A portion of substrate  100  and fin  140  is removed in the undercutting process. The undercutting may be performed isotropically, for example, by wet etching in a mixture of nitric and hydrofluoric acids or by RIE using CF 4  or SF 4 . Alternatively, the undercutting may be performed an-isotropically by wet etching in an aqueous or alcoholic solution of a strong base such as potassium hydroxide or tetrametylammonium hydroxide which etches the [001] crystal plane of silicon faster than the [001] crystal plane. Pedestal  195  provides an electrically conductive body contact between channel region  185  and substrate  100 , effectively eliminating floating body effects.  
         [0036]      FIG. 10  is a top view and  FIGS. 11A, 11B ,  11 C and  11 D are cross-sectional views through respective lines  11 A- 11 A,  11 B- 11 B,  11 C- 11 C and  11 D- 1 D of the structure illustrated in respective  FIGS. 8, 9A ,  9 B,  9 C and  9 D after additional processing. In  FIGS. 10, 11A ,  11 B,  11 C and  11 D a dielectric layer  205  is deposited, filling (shown) or partially filling (not shown) the undercut regions of trench  190 A. A top surface of dielectric layer  205  is coplanar with a top surface of capping layer  160 . In one example, dielectric layer  205  is formed by conformal CVD oxide deposition (such as TEOS or HDP) followed by a CMP. It is permissible not to completely fill undercut regions  190 A and leave voids because the remainder of dielectric layer  205  will seal any voids. The distance “T” between fin  140  and substrate  100  under source/drains  180  (see  FIG. 11D ) whether completely filled or containing voids, greatly reduces parasitic capacitance between the fin and the substrate. In one example, “T” is between about  50  nm and about 250 nm.  
         [0037]     Contacts (not shown, but well known in the art) may be formed to the finFET by forming contact via holes through dielectric  205  and capping layers  145 A and  160  to source-drains  180  and gate  155 , filling the via holes with metal (e.g. barrier liner and tungsten) and performing a CMP. Next, standard processing including formation of levels of wiring and intervening dielectric layers are formed through completion of an integrated circuit chip containing finFET devices according to embodiments of the present invention.  
         [0038]      FIG. 12  is a flow diagram of a design process used in semiconductor design, manufacturing, and/or test. In  FIG. 12 , a design flow  300  may vary depending on the type of IC being designed. For example, a design flow  300  for building an application specific IC (ASIC) may differ from a design flow  300  for designing a standard component. Design structure  320  is preferably an input to a design process  310  and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure  320  comprises circuit  100  in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure  320  may be contained on one or more machine readable medium. For example, design structure  320  may be a text file or a graphical representation of circuit  100 . Design process  310  preferably synthesizes (or translates) circuit  100  into a netlist  380 , where netlist  380  is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist  380  is re-synthesized one or more times depending on design specifications and parameters for the circuit.  
         [0039]     Design process  310  may include using a variety of inputs; for example, inputs from library elements  330  which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 30 nm, etc.), design specifications  340 , characterization data  350 , verification data  360 , design rules  370 , and test data files  385  (which may include test patterns and other testing information). Design process  310  may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process  310  without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.  
         [0040]     Ultimately, design process  310  preferably translates the structure illustrated in  FIGS. 10, 11A ,  11 B,  11 C and  11 D, along with the rest of the integrated circuit design into a final design structure  330  (e.g., information stored in a GDS storage medium). Final design structure  330  may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test data, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce the finFET of  FIGS. 10, 11A ,  11 B,  11 C and  11 D. Final design structure  330  may then proceed to a stage  335  where, for example, final design structure  330 : proceeds to tape-out, is released to manufacturing, is sent to another design house or is sent back to the customer.  
         [0041]     Thus, the embodiments of the present invention provide finFET, a method of fabricating finFET and a design structure of a finFET without floating body effects and with reduced parasitic capacitance.  
         [0042]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.