Abstract:
System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/605,913, filed Aug. 31, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety, and commonly owned. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to SIMD parallel processing, and in particular, to executing instructions from an auxiliary data stream.  
       BACKGROUND OF THE INVENTION  
       [0003]     Parallel processing architectures, employing the highest degrees of parallelism, are those following the Single Instruction Multiple Data (SIMD) approach and employing the simplest feasible Processing Element (PE) structure: a single-bit arithmetic processor. While each PE has very low processing throughput, the simplicity of the PE logic supports the construction of processor arrays with a very large number of PEs. Very high processing throughput is achieved by the combination of such a large number of PEs into SIMD processor arrays.  
         [0004]     A variant of the bit-serial SIMD architecture is one for which the PEs are connected as a 2-D mesh, with each PE communicating with its 4 neighbors to the immediate north, south, east and west in the array. This 2-d structure is well suited, though not limited to, processing of data that has a 2-d structure, such as image pixel data.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention in one aspect provides a digital data processing system that may comprise a source of data, adapted to provide pixel data representing an image frame line segment, said line segment comprising at least one data block containing pixels arranged in a raster order; means for receiving the line segment and selecting pixel values from the line segment, wherein the selected pixels comprise a raster order pixel group; and means for constructing a subframe line from the raster order pixel group, said subframe line comprising at least one data word containing at least 2 pixels arranged in a raster order.  
         [0006]     In another aspect, the present invention provides a digital data processing system that may comprise a data client, adapted to receive pixel data representing an image frame line segment, said line segment comprising at least one data block containing pixels arranged in a raster order; means for receiving a subframe line comprising at least one data word containing at least 2 pixels arranged in a raster order, and selecting pixel values from the subframe line, wherein the selected pixels comprise a raster order pixel group; and means for constructing a line segment from the raster order pixel group and conveying the line segment to said data client.  
         [0007]     Various aspects and embodiments of the invention are revealed in the following description along with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     For a fuller understanding of the invention, reference is made to the following detailed description, taken in connection with the accompanying drawings illustrating various embodiments of the present invention, in which:  
         [0009]      FIG. 1A  is a schematic diagram of an image processing system built in accordance to the present invention;  
         [0010]      FIG. 1B  is a schematic diagram of a SIMD array processor built in accordance to the present invention;  
         [0011]      FIG. 2  is a graphical representation of the storage format for pixel data in the frame buffer;  
         [0012]      FIG. 3  is a table showing the definition of the packing code control signal;  
         [0013]      FIG. 4  is a graphical representation of the location and selection of a subframe within an image frame stored in the frame buffer;  
         [0014]      FIG. 5  is a graphical representation of overlapping subframes within an image frame;  
         [0015]      FIG. 6  is a table listing the terminology and composition describing the units of data stored in the frame buffer;  
         [0016]      FIG. 7  is a graphical representation of the data units listed in  FIG. 6 , showing frame buffer storage and bank sequence;  
         [0017]      FIG. 8  is a table showing the definition of the cache_cmd control signal;  
         [0018]      FIG. 9  is a graphical representation showing the use of the RMA SIMD cache to construct subframe lines;  
         [0019]      FIG. 10  is a graphical representation showing the use of the WMA SIMD cache to construct frame buffer burst pairs;  
         [0020]      FIG. 11  is a table showing the bank sequence for burst pairs associated with a subframe;  
         [0021]      FIG. 12  is a table showing the bank sequence for burst pairs associated with a subframe where swizzling is employed; and  
         [0022]      FIG. 13  is a table listing and defining the components of the subframe I/O command. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]     The present invention relates to parallel processing of digital data, and in particular, digital image pixel data. Although the embodiments disclosed herein relate to the particular case of image pixel data, it should be understood that pixel data could be replaced with any digital data without departing from the scope and spirit of this invention.  
         [0024]     The exemplary embodiment of the present invention is part of an image processing system used primarily for processing pixel data. Referring to  FIG. 1A , an exemplary system built in accordance with the present invention comprises SIMD array processor  2000 , SIMD wrapper  100 , memory controller  600  and frame buffer  900 . SIMD array processor  2000  provides processing of pixel data. SIMD wrapper  100  encapsulates the SIMD array processor, providing interfaces to other elements of the system. SIMD wrapper  100  also incorporates many of the functional aspects of the invention. Memory controller  600  provides direct control of data reads and writes between the system and frame buffer  900 . Frame buffer  900  provides storage of image frame data for processing by the image processing system.  
         [0025]     Referring now to  FIG. 1B , SIMD array processor  2000  provides the computation logic for performing operations on pixel data. Pixel operations are performed on a SIMD (Single Instruction Multiple Data) array of processing elements (PEs). To perform these operations, the PE array  1000  requires a source of instructions and support for moving pixel data in and out of the array.  
         [0026]     SIMD array processor  2000  includes a program sequencer  300  to provide the stream of instructions to PE array  1000 . Pixel I/O unit  800  is also provided for the purpose of controlling the movement of pixel data in and out of the PE array  1000 .  
         [0027]     The SIMD array processor  2000  may be employed to perform computations on array-sized image segments. The array dimensions for one exemplary embodiment are 64 columns by 48 rows. SIMD array processor  2000  is subordinate to a system control processor, referred to herein as the “CPU”. CPU I/F  120 , as shown in  FIG. 1A , interfaces between the SIMD array processor  2000  and the CPU and provides for initialization and control of the exemplary SIMD array processor  2000  by the CPU.  
         [0028]     The pixel I/O unit  800  provides control for moving pixel data between the PE array  1000  and external storage via an image buss called “lmg Bus”. The movement of pixel data is performed concurrently with PE array computations, thereby providing greater throughput for processing of pixel data. The pixel I/O unit  800  performs a conversion of image data between the packed frame buffer pixel form and the form required for processing by the PE array  1000 .  
         [0029]     The SIMD array processor  2000  processes image data in array-sized segments known as “subframes”. In a typical scenario, the image frame in frame buffer  900  is much larger than the dimensions of PE array  1000 . Processing of the image frame is accomplished by processing subframe image segments in turn until the image frame is fully processed.  
         [0030]     In an exemplary system employing the SIMD array processor  2000 , frame buffer  900  provides storage for image data external to the SIMD array processor  2000 . Frame buffer  900  communicates with the SIMD array processor  2000  via the lmg Bus interface within SIMD wrapper  100 . To meet bandwidth requirements, the width of the lmg Bus interface is 64-bits. Frame buffer  900  is organized such that data words are logically 64-bit in width.  
         [0031]     Pixel data is stored in 64-bit multi-pixel words, as shown in  FIG. 2 . Many packing formats are supported, for instance, 2 pixels per word (30- or 32-bit pixel data), 3 pixels per word (20-bit), and 4 pixels per word (16-bit). The packing format is represented by a packing code as shown in  FIG. 3 .  
         [0032]     Pixels are packed in consecutive horizontal scan order. Within the data word, earlier pixels are located toward the most significant end of the word. Pixels are aligned with bit  0 , the least significant end of the word, so any unused bits are at the most significant end.  
         [0033]     During input and output of subframe data, the data words are moved in horizontal scan line order. Therefore, a pixel at the least significant end of a data word is followed by the next pixel in the image frame, which is stored toward the most significant end of the next data word in the sequence.  
         [0034]     The first data word for each subframe line, as processed by SIMD array processor  2000 , is aligned so that the first pixel of the subframe line is the first pixel of the data word. That is, a subframe line does not begin in the middle of a data word. This alignment could be achieved by restricting the granularity of subframe boundaries to multiple-of-2, -3 or -4 pixels (depending on pixel packing) within frame buffer  900 . Alternatively, as in the exemplary embodiment, SIMD wrapper logic may perform a pixel re-packing function to ensure the alignment of each subframe line.  
         [0035]     Within frame buffer  900 , pixel packing is “justified” at the beginning of each image frame line, that is, the first pixel for each line is stored at the most significant end of the first data word for that frame line. Frame lines are also aligned at 32-byte (4 word) burst boundaries in this exemplary embodiment. Because of this alignment, some unused data may occur at the end of each frame line.  
         [0036]     The pixel packing method described here is the one followed for one exemplary embodiment. Other pixel orders and storage constraints might be applied within the overall data handling scheme described without departing from the scope of the present invention.  
         [0037]     An example of image frame storage is shown in  FIG. 4 . In this example, the image frame, shown by the shaded area, comprises 160×160 pixels. The packing code is 2 (explained above), specifying 20-bit pixels. A single 48×64 subframe, shown as a white rectangle with dashed perimeter, is arbitrarily located at an X Offset of 17 and a Y Offset of 40.  
         [0038]     In the figure, 64-bit word boundaries are shown by dashed vertical lines and bursts (consisting of 4 words each) are shown by solid vertical lines. Since there are 3 pixels per word in this example, a burst consists of 12 pixels. A frame line of 160 pixels therefore requires 14 bursts (160/12=13 ⅓). As shown by the shaded area, only ⅓ of the final burst is used for image frame data. The “pitch” for the frame is expressed as the number of bursts for each frame line, i.e. 14 in this example.  
         [0039]     For most purposes, the image frame is completely specified by the frame address, packing code and pitch values. The exemplary subframe is located at a Y offset of 40 and an X offset of 17. The X offset and Y offset values represent the position of the upper left corner of the subframe with respect to the start address (upper left corner) of the image frame. The offsets are in terms of pixels, with the X offset increasing from left to right and the Y offset increasing from top to bottom.  
         [0040]     The exemplary SIMD array processor  2000  processes 48×64 image segments known as subframes. All image data input and output is in terms of subframes. An image frame is therefore processed by processing subframe segments in turn until the entire image frame is completed.  
         [0041]     For the example of the 160×160 image frame, the subframing pattern shown in  FIG. 5  might be employed. It may be seen that the subframes overlap each other. This is a necessary consequence of the fact that the 64-wide subframes do not evenly span the 160-wide frame, nor do the 48-high subframes evenly span the 160-high frame. In practice, overlap of subframes is also necessary to remove pixels that are invalid due to edge effects introduced by processing.  
         [0042]     In the example of  FIG. 5 , the shaded subframe would be identified by an X Offset of 48 and a Y Offset of 38. Assuming raster order processing, the final 10 lines of this subframe will subsequently be overwritten by a later subframe. The writing of these 10 lines to frame buffer  900  is therefore redundant. To prevent these redundant writes, a “Y-lines” parameter of 38 may be specified. The parameter Y-lines determines the number of subframe lines to be written to frame buffer  900  during a subframe output. Any write of subframe lines beyond the Y-lines number is suppressed by SIMD wrapper  100 .  
         [0043]     Processing of interlaced subframes is sometimes necessary, where subframes for one field are composed of even frame lines only, and subframes for another field are composed of odd frame lines only. A “stride” parameter allows the programmer to specify an offset—in terms of image frame lines—between subframe lines. In one exemplary embodiment, the stride may be any value from 0 to 31, though 1 (non-interlaced) and 2 (interlaced) are the normal alternatives.  
         [0044]     A decimation feature provides increased throughput for subframe input. A “Dec_cmd” parameter determines whether decimation is active (1) or inactive (0). Decimation is applied to 20-bit pixel data only. The decimation method combines 3 pixel values, producing a single 20-bit pixel by the following formula: 
 
Pixel i  (word i [59:40]*20+word i [39:20]*24+word i [1 9:0]*20)/64 
 
         [0045]     Decimation is applied on a word basis, with the 3 pixels of each 64-bit word being combined to produce a single subframe pixel. The X Offset in frame buffer  900  must be at a word boundary. The subframe read from frame buffer  900  is effectively 48×192 pixels in size, while the subframe received by the SIMD array processor  2000  is a normal 48×64 subframe. No cache support is provided for decimated subframe input.  
         [0046]     A subframe is completely specified by an X Offset, a Y Offset, Y Lines, stride and the Dec_cmd parameter.  
         [0047]     Referring now to the exemplary embodiments of  FIG. 9  and  FIG. 10 , SIMD wrapper  100  provides control and temporary data storage for the purpose of transferring pixel data between frame buffer  900  and the SIMD array processor  2000  during subframe I/O. Read memory agent (RMA)  400  controls the transfer of data from frame buffer  900  to SIMD array processor  2000 , employing the RMA SIMD cache  420  if requested, and constructing a realigned subframe line for transfer via the lmg Bus. Write memory agent (WMA)  500  controls transfer of data from SIMD array processor  2000  to frame buffer  900 , employing the WMA SIMD cache  520  for stitching, and constructing a frame buffer-aligned data stream for write to frame buffer  900 .  
         [0048]     The exemplary embodiment employs a DDR (double data rate) memory for its frame buffer. The physical data path for the DDR is 128 bits wide. The physical addressing of the DDR memory is in terms of bursts. Each burst is a 32-byte data block, comprising 2 physical words (i.e. 2 data transfers as propagated on a data buss called “mem_dat”). Each physical word comprises 2 logical words, i.e. 64-bit data words as described in previous sections of this document. A summary of these data units is shown in  FIG. 6  and  FIG. 7 .  
         [0049]     The exemplary DDR memory is internally partitioned into 4 banks, labeled A, B, C and D. The bank structure is such that a sequence of addresses traverses a bank segment for each count of 2 in the sequence. In other words, address 0 and 1 refer to bank A, 2 and 3 refer to bank B, and so on as shown in  FIG. 7 .  
         [0050]     For optimal performance, a couple of rules are followed. The first is to access burst pairs that belong to the same bank in sequence. So, a read of address 0 should be followed by a read of address 1 and so on. The second rule is that access of a burst pair from one bank should be followed by an access of a burst pair from the next bank. In general, banks must be accessed in sequence for optimal performance. As long as addresses are accessed in sequence, optimal memory performance may be maintained. Accesses to addresses that are not in sequence may still be performed optimally as long as the banks are accessed in sequence. So, the burst pair of addresses 2, 3 (bank B) might be followed by burst pair of addresses 12, 13 (bank C) without incurring a performance penalty.  
         [0051]     Each of the memory agents employs a SIMD cache to reduce redundant frame buffer transfers and, in the case of the WMA, to provide for stitching of output data. In an exemplary embodiment, each SIMD cache may support up to 4 active subframe I/O processes. Each of these “logical caches” provides 3 k bytes of storage, for a total of 12 k bytes per cache. A logical cache stores 2 bursts for each of the 48 lines of a subframe. The exemplary RMA SIMD cache  420  is configured as a 128×768 RAM and the exemplary WMA SIMD cache  520  is configured as a 64×1536 RAM.  
         [0052]     During subframe I/O, a SIMD cache is written with the final 2 bursts for each subframe line. (This burst pair is constrained to being an even-odd pair, thereby belonging to the same DDR bank.) The data written to the SIMD cache during transfer of a given subframe is read and used by the cache during transfer of the next subframe for a given image frame. To make proper use of the cache, subframes must be transferred in raster sequence so that the data written to the cache from a given subframe may be read from the cache and employed for the transfer of the next subframe in sequence.  
         [0053]     Use of the WMA SIMD cache  520  is required for subframe output, in order to perform stitching. Use of the RMA SIMD cache  420  for subframe input is optional, though its use provides a performance benefit. For the first subframe of a given subframe row, no read of the SIMD cache is performed since there is no previous subframe within the row to provide data. For this subframe, only a cache write is performed. For the last subframe of a subframe row, there is no cache write, since there is no subsequent subframe to use the data. For this subframe, only a cache read is performed. For all “middle” subframes, both read and write of the SIMD cache is performed.  
         [0054]     Each subframe I/O task includes a cache_cmd control and a cache_select control. The cache_cmd determines whether to treat the subframe as a “first” subframe (1), a “middle” subframe (2), a “final” subframe (3) or to perform no caching at all (0). The cache_select determines which of the logical caches, 0 through 3, to employ for the subframe I/O task.  
         [0055]     RMA  400  encapsulates the data alignment logic, control, and RMA SIMD cache  420  required to transfer subframe data from frame buffer  900  to the SIMD array processor  2000 . The operation of RMA  400  is illustrated by an example shown in  FIG. 9 . This example illustrates the read of a subframe line for 20-bit data. The subframe is assumed to be a “middle” or normal subframe so that both read and write access of the SIMD cache is performed.  
         [0056]     The first subframe line for this subframe is shown at the specified X and Y offsets in frame buffer  900 . The shaded portion of the line represents the pixel data to be read. Since this is 20-bit data, it spans most of 3 burst pairs. The outer rectangle shown represents the 3 burst pairs, with dashed lines indicating the boundaries of each burst. It may be observed that the subframe line might span portions of 4 burst pairs if it were located differently with respect to the burst pairs.  
         [0057]     Since this is assumed to be a middle subframe, the first burst pair for each line resides in RMA SIMD cache  420  and need not be read from frame buffer  900 . In this example, therefore, only 2 burst pairs for each subframe line need be read.  
         [0058]     As each subframe line is read from frame buffer  900 , the corresponding entry in the SIMD cache is read and combined with frame buffer  900  data to provide all 3 burst pairs that contain the subframe line. When the final burst pair for the subframe line has been read from frame buffer  900 , it is written to the SIMD cache.  
         [0059]     The reconstructed subframe line is re-aligned so that 22 words of 64-bit packed pixels are created. The data is aligned so that the first pixel of the subframe line is justified at the most significant end of the first word as shown in  FIG. 9 . This is the alignment required by the SIMD array processor  2000 . The 22 words are sent to the pixel I/O unit  800  of the SIMD array processor  2000  in raster sequence.  
         [0060]     If the subframe line in this example were for a “first” subframe (or if cache_cmd=0 indicating no caching), there would be no cache data to combine with frame buffer data. It would be necessary to read all 3 burst pairs from frame buffer  900  and create the re-aligned subframe line to be sent to the pixel I/O unit  800 . If the subframe line were for a “final” subframe, the write of data to the SIMD cache would simply be omitted.  
         [0061]     It should be apparent that the SIMD cache address for the read and write accesses for a given subframe line will be the same, since the same logical cache and subframe line is indicated for each. The new cache (write) data replaces the old (read) data as the old data is being used to construct the subframe line. Since the read occurs at the beginning of the subframe line and the write occurs at the end of the line, there is no memory access conflict or read-write order violation.  
         [0062]     WMA  500  encapsulates the data alignment logic, control, and WMA SIMD cache  520  required to transfer subframe data to frame buffer  900  from the SIMD array processor  2000 . The operation of the WMA is illustrated by an example shown in  FIG. 10 . This example illustrates the write of a subframe line for 20-bit data. The subframe is assumed to be a “middle” or normal subframe so that both read and write of the SIMD cache is performed.  
         [0063]     The destination for the first subframe line is shown at the specified X and Y offsets in frame buffer  900 . The shaded portion of the line represents the pixel data to be written. Since this is 20-bit data, it spans most of 3 burst pairs. The outer rectangle shown represents the 3 burst pairs, with dashed lines indicating the boundaries of each burst.  
         [0064]     As each subframe line is received in raster sequence from the pixel I/O unit, the data is re-aligned so that the data is properly located within the burst pairs to be written to frame buffer  900 . This re-alignment may result in unused data in the final burst pair, which is zero-padded. The final burst pair of the re-aligned data is written to the WMA SIMD cache  520  for use by the next subframe. The final burst pair is not written to frame buffer  900  at this time.  
         [0065]     Data that makes up the first burst pair to be written to frame buffer  900  includes data that precedes the starting point of the current subframe line. In the absence of a cache, this data would have to be read from frame buffer  900  and “stitched” to the subframe line to create a valid first burst pair. However, WMA SIMD cache  520  uses the cached data from the previous subframe to provide this data. The burst pair is read from the SIMD cache and the portion of it preceding the subframe line start is extracted and joined (or stitched) to the subframe line data to produce the first burst pair. In the example, the first two burst pairs of the re-aligned data will be written to frame buffer  900 .  
         [0066]     In o respect, WMA  500  differs from RMA  400  in this example of the present invention, in the treatment of subframe overlap. The overlap of subframes to allow elimination of edge effects was described previously in this disclosure. For subframe input, the overlap is handled simply by specifying the X and Y offsets for the desired subframe to read, regardless the position of the previous subframe. For subframe output, however, it is necessary for the WMA  500  to know the overlap so that it can determine the portion of the current subframe that is valid.  
         [0067]     An output subframe must be positioned in frame buffer  900  so that the leading edge abuts the trailing edge of the previous subframe. The trailing edge of the previous subframe can only be determined if the overlap is known. For example, a subframe that starts at X offset of 100 and has an overlap of 10 will have a trailing edge at 100+64−10−1, or 153. The next subframe that is output must be written to an X offset of 100+64-10, or 154. Since the X offset is programmer supplied, the positioning of the next subframe is not a problem.  
         [0068]     However, WMA  500  has the explicit responsibility of stitching data to the leading edge of a subframe, whatever its X offset is. It can only do this if it has the correct data in the cache. WMA  500  must know the overlap to determine where the trailing edge of the current subframe is so that it will know which burst pair to write to cache for stitching the next subframe.  
         [0069]     In the example shown, the overlap does not affect the determination of which burst pair to write. However, in the general case it is possible that the trailing edge of the full subframe falls in a different burst pair from the trailing edge of the subframe after adjustment for overlap.  
         [0070]     If the subframe line in this example were for a “first” subframe (or if cache_cmd=0 indicates no caching), there would be no cache data to combine with the subframe line. Since the frame address and pitch for an image frame are constrained to be at burst pair boundaries, the first subframe of a subframe row is always burst-pair aligned, and therefore requires no stitching.  
         [0071]     If the subframe line were for a “final” subframe, the write of data to the SIMD cache would simply be omitted, since there are no further subframes in the row to require data for stitching. The final burst pair is written to frame buffer  900 .  
         [0072]     To perform this example with different pixel sizes, it is necessary only to observe that the number of words for each subframe line will change (16 words for 16-bit data, 32 words for 32-bit data), affecting the number of burst pairs per subframe line. The memory control logic and re-alignment functions must take pixel size into consideration to produce the correct re-aligned subframe line.  
         [0073]     Memory controller  600  provides direct control of frame buffer accesses by the image processing system in response to requests by clients within the system. SIMD wrapper  100  is one of several clients serviced by memory controller  600 .  
         [0074]     The frame buffer address provided by the RMA  400  or WMA  500  is computed based upon the subframe parameters as follows: 
 
FB Addr=floor(X_offset/(pixels_per_word*4))+(Y_offset*Pitch)+Frame Address WMA uses “even_floor” instead of “floor” to provide burst pair alignment 
 
         [0075]     As mentioned previously, optimal performance requires that frame buffer  900  be accessed in bank order. For most clients, a normal raster ordering for data storage insures that this will occur. For example, the first 8 lines of an image spanning 8 burst pairs per line are shown in  FIG. 11 . Access of this image will yield the desired A-B-C-D bank order.  
         [0076]     Use of this memory organization would produce less-than-optimal results for a SIMD array image, however. One reason is that the portion of a subframe line that is required for a sequence of accesses (i.e. the subframe line less the cached data) is often less than 4 burst pairs. If the gray portion of  FIG. 12  represents the first 8 lines of a SIMD array image, one can see that the sequence of accesses would be A-B-C-A-B-C instead of A-B-C-D. Since the C-A bank sequence is out of order, a wait state would be inserted for each occurrence of this sequence.  
         [0077]     To eliminate loss of performance due to wait states, a technique known as “swizzling” is employed. Swizzled data is data that is written to frame buffer  900  with a non-sequential ordering such that accesses by the SIMD array processor  2000  will result in sequential bank accesses. Due to requirements that are peculiar to the SIMD array processor  2000 , subframe lines are accessed in a pattern of multiple-of-8 lines. Given this requirement, a swizzle pattern that would result in the desired order of bank accesses for a stride of 1 is shown in  FIG. 12 . It may be seen that as the subframe lines are accessed in order (0, 8, 16, etc.), the bank sequence of A-B-C-D is maintained throughout.  
         [0078]     During an access by a client, the memory controller  600  is told whether the data to be accessed is swizzled. For the memory controller  600 , handling of swizzled data is an exercise in address generation. For normal (non-swizzled) data, the frame buffer address can be computed: 
 
ADR[27:0]=BASE_ADR+Y*PITCH+X 
 
         [0079]     where Y is the Y offset and X is the X offset in burst units For access of swizzled data, the address is computed as the following:  
                                                       ORIG_ADR = BASE_ADR + Y * PITCH + X           ORIG_BANK = ORIG_ADR[7:6]           if (BANK_SWIZZLE_EN=1) then              if (STRIDE=1) then                 Y_LINE = Y[4:3]              elsif (STRIDE=2) then                 Y_LINE = Y[5:4]              elsif (STRIDE=4) then                 Y_LINE = Y[6:5]              elsif (STRIDE=8) then                 Y_LINE = Y[7:6]              elsif (STRIDE=16) then                 Y_LINE = Y[8:7]              endif           else              Y_LINE = O           endif           if (Y LINE=1) then              BANK =ORIG_BANK+3           elsif (Y_LINE=2) then              BANK = ORIG_BANK+2           elsif (Y_LINE=3) then              BANK = ORIG_BANK+1           else              BANK = ORIG_BANK           endif           ADR[27:5] = ORIG_ADR[27:8] &amp; BANK &amp; ORIG_ADDR[5]                      
 
         [0080]     It may be seen that only power-of-2 Stride values are supported with swizzling.  
         [0081]     A subframe I/O task is described by a subframe I/O command as shown in  FIG. 13 . SIMD array processor  2000  dispatches a subframe I/O command to SIMD wrapper  100  to signify the beginning of a subframe input/output task. The I/O command provides information completely specifying the frame from which the subframe is to be taken, the subframe itself, and the cache controls to be employed.  
         [0082]     The I/O direction field (bit  66  in  FIG. 13 ) determines whether the task is for input (dir=1) or output (dir=0) of a subframe. Direction is with respect to the SIMD array processor  2000 .  
         [0083]     The image frame is specified by the frame address, pitch and pack code parameters. The frame address provides the base address for the image frame in frame buffer  900 . The pack code determines whether a word contains two 30/32-bit pixels (pack=1), three 20-bit pixels (pack=2) or four 16-bit pixels (pack=3). The storage required for a frame line is determined by the width of the frame (in pixels) and the packing of the pixels into words. The line width is expressed as the pitch for the image frame. Units for frame address and pitch are 32-byte bursts.  
         [0084]     The subframe is specified by the X offset, Y offset, Y lines, stride and Dec_cmd parameters. The X offset and Y offset determine the X (column) and Y (row) position of the subframe within the frame. The X and Y offsets are expressed in units of single pixels. Numbering within the image frame is from the upper left-hand corner (row 0, column 0). Where the task is an output, the Y Lines parameter may be used to specify the number of subframe lines to write. To support interleaved storage of subframe data, a stride parameter is provided to determine a Y offset between each subframe line in the image frame. Although Stride would normally be 1 (non-interleaved) or 2 (interleaved), valid stride values range from 0 to 31. It should be noted that a stride of 0 would support generation of a vertical stripe pattern from a single subframe line of data in frame buffer  900 . The Dec_Cmd determines whether decimation is to be employed during subframe input (0=no, 1=yes). Decimation is used for subframe input only, for 20-bit pixel data only and may only be applied at a word-aligned X offset.  
         [0085]     The cache_select parameter determines which of the 4 cache buffers to use for the subframe task. The cache_cmd determines whether to use no caching (0) or to treat the subframe as a “first” subframe (1), a middle or “normal” subframe (2) or a “last” subframe (3). The Overlap value expresses the number of pixels of horizontal overlap between the current subframe and the next subframe in the sequence.  
         [0086]     Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.