Abstract:
A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with a controlled amplitude. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference to provide a comparator output signal to a phase frequency comparator, the output of which controls a source of the variable feedback control current. A method includes controlling the amplitude of a sawtooth output signal by charging a capacitor in a sawtooth voltage generator with a variable feedback control current; comparing a version of the sawtooth output signal with a fixed reference voltage to provide a comparator output signal; processing the comparator output signal in a phase frequency comparator to provide up/down control signals; and controlling the variable feedback control current with the up/down control signals from the phase frequency comparator.

Description:
TECHNICAL FIELD 
       [0001]    This invention relates to a sawtooth signal generator providing a controlled sawtooth signal amplitude. 
       BACKGROUND 
       [0002]      FIG. 1  shows a waveform for a sawtooth signal that is generated by charging a capacitor with a constant current source. The magnitude (M) of the sawtooth signal generated by having a charging current (I) charge a capacitor (C) is given by: 
         [0000]    
       
         
           
             
               M 
               = 
               
                 
                   Vend 
                   - 
                   Vref 
                 
                 = 
                 
                   
                     I 
                     * 
                     Tclk 
                   
                   C 
                 
               
             
             , 
           
         
       
     
         [0000]    where Tclk is the period of the sawtooth signal, Vref is the starting voltage, and Vend is the ending voltage of the sawtooth signal. The charging current (I) can be provided by a band-gap voltage (Vbg) and a resistor (R). The charging current for charging the capacitor (C) is given by: I: Vbg/R so that the magnitude of the sawtooth can be written as 
         [0000]    
       
         
           
             M 
             = 
             
               
                 
                   Vbg 
                   * 
                   Tclk 
                 
                 
                   R 
                   * 
                   C 
                 
               
               . 
             
           
         
       
     
         [0000]    Variations in the values of fabricated resistors have a range of plus and minus 30 percent, while variations in fabricated capacitors have a range of plus and minus 20 percent, depending on fabrication process variations. Thus, the magnitude of a sawtooth signal can vary over a range of minus 36 percent to plus 78 percent. This range for the magnitude, or amplitude, of a sawtooth signal is not acceptable for a system requiring a high level of accuracy. Consequently, a simple charging circuit for a sawtooth generator requires trimming to adjust the magnitude of the sawtooth signal to a desired value. Consequently, a sawtooth generator is required which can provide a sawtooth output signal having a magnitude that is accurate in spite of process variations in component values. 
       SUMMARY OF THE INVENTION 
       [0003]    A sawtooth signal generator provides a sawtooth output signal having a controlled amplitude. A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with an amplitude controlled by the variable control current. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference and that provide a comparator output signal to a phase frequency comparator, the output of which controls a source of the variable feedback control current. 
         [0004]    A dual-capacitor sawtooth generation circuit includes a sawtooth generator control circuit that receives a reference clock signal and that provides a first sawtooth command signal and a second complementary sawtooth command signal to a sawtooth voltage generator circuit. The sawtooth voltage generator circuit includes a first sawtooth capacitor and a second sawtooth capacitor. The sawtooth voltage generator circuit receives: a low voltage reference voltage, the first sawtooth command signal, the second complementary sawtooth command signal, and a control current signal. The sawtooth voltage generator circuit has an output terminal at which is provided sawtooth output signal. The first sawtooth command signal and the second complementary sawtooth command signal alternatively connect one of the first and second sawtooth capacitors to the control current signal and to the output terminal for the sawtooth output signal while also connecting the other of the first and second sawtooth capacitors to the low voltage reference voltage so that each of the sawtooth capacitors alternately provides a sawtooth output signal that starts at the low voltage level to the output terminal. 
         [0005]    A sawtooth generator also includes a dual-capacitor sawtooth voltage generator circuit that includes a first sawtooth capacitor and a second sawtooth capacitor, that receives a low voltage reference voltage, that receives a first sawtooth command signal, that receives a second complementary sawtooth command signal, that receives a feedback current signal from a charge pump circuit, and that has a sawtooth output terminal at which is provided a sawtooth output signal. The first sawtooth command signal and the second complementary sawtooth command signal alternatively couple one of the first and second sawtooth capacitors to the feedback current signal and to the sawtooth output terminal while also coupling the other of the first and second sawtooth capacitors to the low voltage reference voltage so that each of the sawtooth capacitors alternately provides a sawtooth output signal that starts at the low voltage reference voltage. A comparator circuit compares a reference voltage level to a version of the sawtooth output signal and provides a comparator output signal. A phase frequency comparator receives the comparator output voltage and a clock signal and provides as outputs an UP signal and a DOWN signal. The UP signal indicates that the version of the sawtooth signal is greater than the reference voltage level and the DOWN signal indicates that the version of the sawtooth signal is less than the reference voltage level. A charge pump circuit receives the UP signal to provide an increase in the feedback current signal and receives the DOWN signal to provide a decrease in the feedback current signal. 
         [0006]    A method of generating a sawtooth signal is provided that has a controlled amplitude. The method includes the steps of: controlling the amplitude of a sawtooth output signal by charging a capacitor in a sawtooth voltage generator with a variable feedback control current; comparing a version of the sawtooth output signal with a fixed reference voltage to provide a comparator output signal; processing the comparator output signal in a phase frequency comparator to provide up/down control signals; and controlling a source of the variable feedback control current with the up/down control signals from the phase frequency comparator. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: 
           [0008]      FIG. 1  is a waveform for a sawtooth signal. 
           [0009]      FIG. 2  is a block diagram of one embodiment of an amplitude controlled sawtooth generator that is controlled using an average value of a sawtooth signal that is compared to a reference voltage. 
           [0010]      FIG. 3  is a waveform diagram showing a band gap voltage Vbg. 
           [0011]      FIG. 4  is a waveform diagram showing a target high voltage Vtarget level and a low voltage Vl level for the amplitude controlled sawtooth generator of  FIG. 2 . 
           [0012]      FIG. 5  is a waveform diagram showing a sawtooth voltage waveform for the amplitude controlled sawtooth generator of  FIG. 2 . 
           [0013]      FIG. 6  is a circuit diagram of a voltage reference block that provides a low voltage Vl for the amplitude controlled sawtooth generator of  FIG. 2 . 
           [0014]      FIG. 7  is a circuit diagram of a sawtooth voltage generator for the amplitude controlled sawtooth generator of  FIG. 2 . 
           [0015]      FIG. 8  is a timing diagram showing various voltage waveforms for the sawtooth voltage generator of  FIG. 7 . 
           [0016]      FIG. 9  is a state transition diagram for a phase frequency comparator for the amplitude controlled sawtooth generator of  FIG. 2 . 
           [0017]      FIG. 10  is a timing diagram illustrating various signals for the phase frequency comparator of  FIG. 8 . 
           [0018]      FIG. 11  is a circuit diagram for a charge pump for the amplitude controlled sawtooth generator of  FIG. 2 . 
           [0019]      FIG. 12  is a block diagram of another embodiment of an amplitude controlled sawtooth generator that is controlled with a fixed average reference voltage. 
           [0020]      FIG. 13  is a waveform diagram showing an average voltage Vm level for the amplitude controlled sawtooth generator of  FIG. 12 . 
           [0021]      FIG. 14  is a waveform diagram showing a low voltage Vl level, a Vm voltage level, and a Vtarget voltage level for the amplitude controlled sawtooth generator of  FIG. 12 . 
           [0022]      FIG. 15  is a waveform diagram showing a sawtooth voltage waveform for an output signal of the for the amplitude controlled sawtooth generator of  FIG. 12   
           [0023]      FIG. 16  is a circuit diagram of a voltage reference block that provides a low voltage Vl and an average voltage Vm for the amplitude controlled sawtooth generator of  FIG. 12 . 
           [0024]      FIG. 17  is a circuit diagram of a sawtooth voltage generator for the amplitude controlled sawtooth generator of  FIG. 12 . 
           [0025]      FIG. 18  is a timing diagram showing various voltage waveforms for sawtooth voltage generator of  FIG. 17 . 
           [0026]      FIG. 19  is a state transition diagram for a phase frequency comparator for the amplitude controlled sawtooth generator of  FIG. 12 . 
           [0027]      FIG. 20  is a timing diagram illustrating various signals for the phase frequency comparator of  FIG. 19 . 
           [0028]      FIG. 21  is a circuit diagram for a charge pump for the amplitude controlled sawtooth generator of  FIG. 12 . 
       
    
    
     DETAILED DESCRIPTION 
     An Amplitude Controlled Sawtooth Generator Based on the Average Magnitude of a Sawtooth Signal 
       [0029]      FIG. 2  illustrates one embodiment of a sawtooth signal generator system  100 . The sawtooth signal generator system  100  is controlled using a version of the sawtooth signal that is an average value of the magnitude of a sawtooth output signal and that is compared to a reference voltage. A voltage reference circuit  102 , such as a bandgap source, provides, for example, a bandgap voltage Vbg as an input bandgap reference voltage to a voltage reference circuit  104 . The voltage reference circuit  104  provides a low voltage Vl reference voltage to a sawtooth signal generator  106 . 
         [0030]    The sawtooth signal generator  106  receives a CLK signal and is controlled by a feedback current signal IregP. The sawtooth signal generator  106  provides an output sawtooth signal Vstp. A low pass filter  108  filters the Vstp signal to provide an average value signal Vavg representing the magnitude of the sawtooth signal Vstp from the sawtooth signal generator  106 . 
         [0031]    A positive input terminal of a voltage comparator  110  receives the Vavg signal. A negative input terminal of the comparator  110  receives the bandgap reference voltage Vbg. The voltage comparator  110  compares the Vavg signal of the sawtooth voltage Vstp to the band gap voltage Vbg of the band-gap circuit  102  and provides a comparator output signal Vcmp. 
         [0032]    If the magnitude of the average of the sawtooth (Vavg) signal is less than the bandgap voltage level (Vbg), the output voltage signal Vcmp of the voltage comparator  110  is LOW, or zero volts. If the magnitude of the average of the sawtooth Vavg is greater than Vbg, the output voltage signal Vcmp of the voltage comparator  110  is HIGH. 
         [0033]    A phase frequency comparator (PFC)  112  compares the comparator output signal Vcmp with the falling edge of a reference CLK output signal from a reference clock circuit  114 . As discussed herein below in connection with  FIG. 9 , an embodiment of the PFC  112  is implemented as a state machine. The clock circuit  114  includes final calibration bits for adjusting the CLK duty cycle. For each period of, the CLK signal, the PFC  112  provides either an UP output signal or a DOWN output signal to a charge pump circuit  116 . The charge pump circuit  116  provides the output current IregP to the sawtooth signal generator  106  on a signal line  118 . A current feedback loop is formed by the sawtooth signal generator  106 , the low pass filter  108 , the voltage comparator  110 , the PFC  112 , and the charge pump  116  that provides the IregP signal to the sawtooth generator  106  to regulate the amplitude of the sawtooth signal Vstp from the sawtooth generator  106 . 
         [0034]      FIG. 3  shows the band gap voltage (Vbg) level from the voltage reference circuit  102  for the amplitude controlled sawtooth generator of  FIG. 2 . Vm is the average or mean of the output sawtooth signal Vstp. 
         [0035]      FIG. 4  shows a Vtarget voltage level and a low voltage Vl level from the voltage references circuit  104  of  FIG. 2 . The starting point voltage level for the sawtooth signal waveform is the low voltage Vl level. The Vtarget voltage level is the targeted high voltage level of the sawtooth signal. 
         [0036]      FIG. 5  shows the output of the sawtooth signal generator  106  as a sawtooth signal Vstp that is centered on the average, or mean, value Vm. 
         [0037]      FIG. 6  is a diagram of the voltage reference circuit  120  for the voltage reference block  104  that provides a Vl voltage level. The bandgap voltage into the voltage reference block  104  (see  FIG. 2 ) generates the regulated voltage Vl. The Vm voltage may or may not be centered on the band-gap voltage value. As an example, let the band-gap voltage Vbg be 1.20 V. If a sawtooth voltage with a magnitude of 200 mV is desired, the voltage references block  104  generates a Vl voltage of 1.100 volts so that the magnitude of the sawtooth signal is 0.200 volts, or 200 mV. The voltage references circuit  102  can use voltage reference sources other than a band-gap source, as desired for various applications. 
         [0038]    The voltage references circuit  120  includes an op amp  122  that has an output terminal coupled to a gate terminal of a NMOS transistor  124 . The NMOS transistor  124  has a drain terminal coupled to a Vdd voltage reference and a source terminal coupled to a feedback node  126 . The feedback node  126  is coupled to an inverting input terminal of the op amp  122 . A non-inverting input terminal of the op amp  122  receives the Vbg reference voltage. The feedback node  126  is coupled to one end of a resistor  128 . The other end of the resistor  128  is coupled to a Vl node  130 , at which is provided the Vl reference signal. The Vl node  130  is coupled through a resistor  132  to a ground, or 0 volt, reference terminal  134 . 
         [0039]    The Vl voltage is a function of the resistors 128,132 and the bandgap voltage Vbg. For good matching of resistors, the magnitude of the sawtooth signal  2  (Vm−Vl) depends on accuracy of the bandgap voltage Vbg. 
         [0040]    With reference to  FIG. 7  and  FIG. 8  for a description of the structure and operation of one embodiment of the sawtooth generator circuit  306  of  FIG. 2 ,  FIG. 7  shows a more detailed circuit diagram and  FIG. 8  shows various voltage waveforms for the sawtooth generator circuit  106 . 
         [0041]    The circuit of  FIG. 7  generates the sawtooth signal Vstp as a sawtooth of increasing voltage that is started by a rising edge of the clock signal CLK and that is reset by the next rising edge of the clock signal CLK. The sawtooth generation circuit  106  includes an edge-triggered D flip-flop circuit  140  that has a clock terminal for receiving the CLK signal, which is substantially a square wave with a period of Tclk. 
         [0042]    An inverted Q-output terminal qn of the D flip-flop  140  is coupled to a D-input terminal d. The D flip-flop circuit  142  changes state at the rising edge of the CLK signal in every Tclk time period as shown in  FIG. 8 . The Q-output signal and the inverted Q-output signal of the D flip-flop  140  are passed through a signal conditioning circuit  142  that prevents the Q-output signal and the inverted Q-output signal from overlapping. The conditioned output signals of the signal conditioning circuit  142  are coupled to a sawtooth generator circuit  144 . These signals are a CmdP signal on a signal line  146  and an inverted CmdPb signal on a signal line  148  to the sawtooth generation circuit  144 .  FIG. 8  indicates that the signals CmdP and CmdPb are oppositely phased substantially square wave signal that each have a period of 2Tclk. The CmdP and CmdPb signals control operation of the sawtooth generation circuit  144 . 
         [0043]    The sawtooth generation circuit  144  includes a first CMOS inverter formed with a first PMOS pull-up transistor  156  and a first pull-down NMOS transistor  152 . The first PMOS pull-up transistor  156  has a source terminal coupled to an input terminal  153  that receives the feedback current IregP from the charge pump circuit  116 . The gate terminals of the transistors  156  and  152  are coupled together. The drain terminals of the transistors  156  and  152  are both coupled to a node  154 . A first sawtooth capacitor  156  is coupled between the node  154  and a ground terminal  158   a . The source terminal of the first pull-down NMOS transistor  152  is coupled to a terminal  160  at which is provided the low voltage Vl. The gate terminals of the transistors  156  and  152  are coupled to a first gate node  162  that receives the CmdP signal on the signal line  146 . 
         [0044]    The sawtooth generation circuit  144  also includes a second CMOS inverter formed with a second PMOS pull-up transistor  170  and a second pull-down NMOS transistor  172 . The second PMOS pull-up transistor  170  has a source terminal that is also coupled to the input terminal  153  that receives the feedback current IregP from the charge pump circuit  116 . The gate terminals and the drain terminals of the transistors  170  and  172  are coupled together. The drain terminals of the transistors  170  and  172  are both coupled to a node  174 . A second sawtooth capacitor  176  is coupled between the node  174  and a ground terminal  158   b . The source terminal of the second pull-down NMOS transistor  172  is coupled to the terminal  160  at which is provided the low voltage Vl. The gate terminals of the transistors  170  and  172  are coupled to a second gate node  182  that receives the CmdPb signal on the signal line  148 . 
         [0045]    A first NMOS coupling transistor  184  is coupled between the node  154  and a Vstp signal output node  186 . A gate terminal of the first NMOS coupling transistor  184  is coupled to the second gate node  182  that receives the CmdPb signal on the signal line  148 . Similarly, a second NMOS coupling transistor  188  is coupled between the node  174  and the Vstp signal output node  186 . A gate terminal of the second NMOS coupling transistor  188  is coupled to the first gate node  162  that receives the CmdP signal on the signal line  146 . 
         [0046]    In operation, the sawtooth generator circuit  106  has the oppositely phased timing signals CmdP and CmdPb alternately provided from the signal conditioning circuit  142 , as indicated in the timing diagram of  FIG. 8 . The sawtooth signal generator  106  receives the current signal IregP from the charge pump  116 . The sawtooth signal generator  106  alternately directs the current signal IregP to charge one of the sawtooth capacitors  156 ,  176 , while the other one of the sawtooth capacitors  176 ,  156  is discharged to the Vl voltage level at terminal  160 . 
         [0047]    A HIGH level of the CmdPb signal on signal line  148  turns on the second NMOS pull-down transistor  172  to couple the second sawtooth capacitor  176  to the Vl voltage at the Vl terminal  160  to discharge the second sawtooth capacitor  176  to the Vl voltage level. A HIGH level of the CmdPb signal on signal line  148  also turns on the first NMOS coupling transistor  184  to couple the NODE  154  and the sawtooth capacitor  156  to the Vstp output terminal  186 . A corresponding LOW level of the CmdP signal on line  146  turns on the first pull-up PMOS transistor  156 , which couples the IregP current at terminal  153  to node  154  to charge the first sawtooth capacitor  156  with the IregP current. 
         [0048]    Alternately, a HIGH level of the CmdP signal on signal line  146  turns on the first NMOS pull-down transistor  152  to couple the first sawtooth capacitor  156  to the Vl voltage at the Vl terminal  160  to discharge the first sawtooth capacitor  156  to the Vl voltage level. A HIGH level of the CmdP signal on signal line  146  also turns on the second NMOS coupling transistor  188  to couple the NODE  174  and the sawtooth capacitor  176  to the Vstp output terminal  186 . A corresponding LOW level of the CmdPb signal on line  148  turns on the second pull-up PMOS transistor  170 , which couples the IregP current at terminal  153  to node  174  to charge the second sawtooth capacitor  176  with the IregP current. 
         [0049]      FIG. 8  illustrates various voltage waveforms for the reference clock signal CLK. The Vclk signal is a square wave. The rising edge of Vclk triggers the oppositely phased CmdP and CmdPb signals. These two oppositely phased alternately charge and discharge the two sawtooth capacitors  156 ,  176  to produce the sawtooth voltage Vstp, which starts at the Vl voltage level. 
         [0050]      FIG. 9  is a state transition diagram  200  that describes operation of the phase frequency comparator (PFC)  112  of  FIG. 2 .  FIG. 10  is a timing diagram illustrating various signals for the phase frequency comparator of  FIG. 9 . The state machine of the PFC  112  has 3 states: a RESET state  202 , an UP state  204 , and a DOWN state  206 . The UP state  204  provides the UP output signal from the PFC  112  to the charge pump circuit  116  to increase the IregP current as indicated in  FIG. 2 . The Down state  206  provides the Down output signal from the PFC  112  to the charge pump circuit  116  to decrease the IregP current, also as indicated in  FIG. 2 . The RESET state holds the current IregP at the same value as previously directed. 
         [0051]    The phase frequency comparator (PFC)  112  changes from the DOWN state  206  to the RESET state  202  either at the rising edge of CLK or at the falling edge of the output signal Vcmp of the voltage comparator  110 . The phase frequency comparator (PFC)  112  changes from the UP state  204  to the RESET state  202  either at the rising edge of CLK or at the rising edge of the output signal Vcmp of the voltage comparator  110 . The phase frequency comparator (PFC)  112  changes from the RESET state  202  to the DOWN state  206  at the falling edge of CLK together with Vcmp being at a HIGH, or 1, state. The phase frequency comparator (PFC)  112  changes from the RESET state  202  to the UP state  204  at the falling edge of CLK together with Vcmp being at a LOW, or 0, state. 
         [0052]      FIG. 10  illustrates an example of the sawtooth signal generator system  100  starting up and not yet reaching a desired magnitude between Vl and Vtarget.  FIG. 10  shows the CLK signal with its rising and falling edges. The output sawtooth signal Vstp is shown in a startup mode in which the final desired magnitude of the sawtooth has not yet reached a desired magnitude. The Vstp signal starts at the Vl, or Vlow, level and rises toward the Vtarget level. The rising Vavg signal from the sawtooth generator  106  and the low pass filter  108  is shown along with the constant level of the band-gap voltage. At the point where the Vavg signal is greater than the Vbg voltage level, the output signal Vcmp of the comparator  110  transitions to a HIGH level. 
         [0053]      FIG. 10  illustrates the state of the phase frequency comparator PFC circuit  112 . A first RESET state  210  occurs at the rising edge of the CLK signal. A first UP state  212  occurs when the CLK has a falling edge and VCMP is also LOW, or 0 volts. A second RESET state  214  occurs again a rising edge of the CLK signal. Another falling edge of the CLK signal together with a LOW Vcmp signal provides a second UP state. The second UP state  216  is cut short and changed to a third RESET state  218  at rising edge of the Vcmp signal. THE third RESET state  218  continues at the rising edge of the CLK signal. At the falling edge of the CLK signal with Vcmp HIGH, or 1, a first DOWN state  220  is entered. 
         [0054]    If the desired magnitude of the sawtooth is not yet reached, for example, during the starting phase, the PFC  112  provides UP signals to the IregP current. 
         [0055]      FIG. 11  illustrates one example of a charge pump circuit  221  that generates the IregP current for the sawtooth generator  106  of the amplitude controlled sawtooth generator of  FIG. 2 . A first constant current source  222  is coupled to a Vdd voltage source and, through a switch  224 , to a capacitor reference node  226 . The capacitor reference node  226  has a capacitor  227  coupled between it and a ground terminal  228   a . The switch  224  is closed in response to an UP signal to provide an Iref current to the capacitor reference node  226  to charge the capacitor  227  with an Iref current. A constant current sink  230  is coupled to a ground terminal  228   b  and through a switch  232  to the capacitor reference node  226 . The switch  232  is closed in response to a DOWN signal to draw an Iref current from the capacitor reference node  226  to discharge the capacitor  227  with an Iref current. The voltage at the capacitor reference node  226  is coupled to a gate terminal of an NMOS transistor  240 . A source terminal of the NMOS transistor  240  is coupled through a resistor  242  to a ground terminal  228   c  to establish a current that passes from a diode-connected PMOS transistor  244  that has a gate terminal and a drain terminal coupled together to a drain terminal of the NMOS transistor  240 . A source terminal of the diode-connected PMOS transistor  244  is coupled to the Vdd voltage source. The diode-connected PMOS transistor  244  and a second PMOS transistor  246  have their gate terminals coupled together to form a current mirror circuit. The second PMOS transistor  246  has a source terminal coupled to the Vdd voltage source. The drain terminal of the second PMOS transistor  246  provides a current IregP that tracks the voltage at the capacitor reference node  226  across the capacitor  227 . When the UP signal and the DOWN signal are not active, the IregP current remains fixed. 
         [0056]    During an “UP” sequence (i.e. UP=1 and DOWN=O), the capacitor  227  is charging through the Iref current source. This increases the voltage across the capacitor  227 . The transistor  240  and the resistor  242  are used as a voltage-to-current converter. As voltage on capacitor  227  increases, the current through transistor  240  increases. The current is mirrored through transistors  244 ,  246  to generate the source current IregP. During a “DOWN” sequence (i.e. UP=0 and DOWN=1) the capacitor  227  is discharging through Iref current. This decreases the voltage across the capacitor  227 . As capacitor  227  voltage decreases, the current through transistor  240  decreases. The current is mirrored through transistors  244 ,  246  to generate the source current IregP. When no action occurs on UP and DOWN signal the voltage stored on capacitor  227  maintains the regulated output current for the feedback loop. 
         [0057]    The embodiment of the present invention illustrated in  FIG. 2  provides a sawtooth signal, the magnitude of which is based on the average magnitude of that sawtooth signal. A phase comparator and a charge pump are in a current regulated loop that controls the magnitude of the sawtooth wave. The present invention provides a sawtooth generator that provides a sawtooth signal that has a precise amplitude and that is relatively insensitive to process variations. For that reason, no trimming is needed to calibrate the magnitude of the sawtooth signal. The present invention is based on charge per unit time, or current, that is provided by a voltage-to-current charge pump stage and that is injected into a capacitor in the sawtooth generator. The charge is proportional to the instantaneous phase error between the sawtooth wave generated by the current regulated loop and the reference clock calibrated with a duty cycle of 50 percent. The amplitude of the sawtooth is adjustable by varying the duty cycle of the reference clock. 
       An Amplitude Controlled Sawtooth Generator based on a Fixed Voltage Vm 
       [0058]      FIG. 12  illustrates another embodiment of a sawtooth signal generator system  300 . The magnitude of the sawtooth signal is controlled using a version of the sawtooth signal that is the sawtooth signal itself and that is compared to a fixed reference voltage Vm. Components in this embodiment are similar to those in the previously discussed sawtooth signal generator system  100  of  FIG. 2 . In this embodiment a voltage reference circuit  302  provides a bandgap voltage Vbg as an input signal to a voltage reference circuit  304  that provides a low voltage Vl reference voltage to a sawtooth signal generator  306 . The voltage reference circuit  304  also provides a Vm reference voltage to a negative input terminal of a comparator  310 . 
         [0059]    The sawtooth signal generator  306  of  FIG. 12  receives a CLK signal and is controlled by a feedback current signal IregP. The sawtooth signal generator  306  provides an output sawtooth signal Vstp. A positive input terminal of a voltage comparator  310  receives the Vstp signal. A negative input terminal of the comparator  310  receives the Vm voltage. The Vm voltage is the average between a low point Vl and a high point Vh of the sawtooth signal. The voltage comparator  310  compares to every moment the magnitude of the Vstp signal to the Vm voltage and provides a corresponding comparator output signal Vcmp. If the level of the Vstp output signal is less than the Vm voltage level, the output voltage signal Vcmp of the voltage comparator  310  is a logic LOW. If the magnitude of the average of the sawtooth Vavg is greater than Vm, the output voltage signal Vcmp of the voltage comparator  310  is a logic HIGH. 
         [0060]      FIG. 13  shows the Vm voltage level from the voltage reference circuit  304 .  FIG. 14  shows a Vtarget voltage level, where Vtarget is the peak value of the sawtooth signal.  FIG. 14  also shows the low voltage Vl level and the Vm voltage level, where the starting point voltage level for the sawtooth signal waveform is the low voltage Vl level.  FIG. 15  shows the output Vstp signal of the sawtooth signal generator  306  as a sawtooth signal Vstp that is centered on the value Vm. 
         [0061]      FIG. 16  shows the voltage reference circuit  304  of  FIG. 12  that provides a low voltage Vl reference voltage to the sawtooth generator  306  and an average voltage reference Vm to an inverting input of a comparator  310 . The voltage references circuit  304  includes an op amp  322  that has an output terminal coupled to a gate terminal of a NMOS transistor  324 . The NMOS transistor  324  has a drain terminal coupled to a Vdd voltage reference and a source terminal coupled to a feedback node  326 , at which is provided the Vm voltage. The feedback node  326  is coupled to an inverting input terminal of the op amp  322 . A non-inverting input terminal of the op amp  322  receives the Vbg reference voltage. The feedback node  326  is coupled to one end of a resistor  328 . The other end of the resistor  328  is coupled to a Vl node  330 , at which is provided the Vl reference signal. The Vl node  330  is coupled through a resistor  332  to a ground, or 0 volt, reference terminal  334 . 
         [0062]      FIG. 17  shows a more detailed circuit diagram of the sawtooth generator circuit  306  and  FIG. 18  shows various voltage waveforms for the sawtooth generator circuit  306 . The circuit of  FIG. 17  generates the sawtooth signal Vstp as a sawtooth of increasing voltage that is started by a rising edge of the clock signal CLK and that is reset by the next rising edge of the clock signal CLK. The sawtooth generation circuit  306  includes an edge-triggered D flip-flop circuit  340  that has a clock terminal for receiving the CLK signal, which is substantially a square wave with a period of Tclk. 
         [0063]    An inverted Q-output terminal qn of the D flip-flop  340  is coupled to a D-input terminal d. The D flip-flop circuit  342  changes state at the rising edge of the CLK signal in every Tclk time period as shown in  FIG. 18 . The Q-output signal and the inverted Q-output signal of the D flip-flop  340  are passed through a signal conditioning circuit  342  that prevents the Q-output signal and the inverted Q-output signal from overlapping. The conditioned output signals of the signal conditioning circuit  342  are CmdP signal on a signal line  346  and an inverted CmdPb signal on a signal line  348  to a sawtooth generation circuit  344 .  FIG. 18  indicates that the signals CmdP and CmdPb are oppositely phased substantially square wave signal that each have a period of 2Tclk. The CmdP and CmdPb signals control operation of the sawtooth generation circuit  344 . 
         [0064]    The sawtooth generation circuit  344  includes a first CMOS inverter formed with a first PMOS pull-up transistor  350  and a first pull-down NMOS transistor  352 . The first PMOS pull-up transistor  350  has a source terminal coupled to an input terminal  353  that receives the feedback current IregP from the charge pump circuit  316 . The gate terminals of the transistors  350  and  352  are coupled together. The drain terminals of the transistors  350  and  352  are both coupled to a node  354 . A first sawtooth capacitor  356  is coupled between the node  354  and a ground terminal  358   a . The source terminal of the first pull-down NMOS transistor  352  is coupled to a terminal  360  at which is provided the low voltage Vl. The gate terminals of the transistors  350  and  352  are coupled to a first gate node  362  that receives the CmdP signal on the signal line  346 . 
         [0065]    The sawtooth generation circuit  344  also includes a second CMOS inverter formed with a second PMOS pull-up transistor  370  and a second pull-down NMOS transistor  376 . The second PMOS pull-up transistor  370  has a source terminal that is also coupled to the input terminal  353  that receives the feedback current IregP from the charge pump circuit  316 . The gate terminals and the drain terminals of the transistors  370  and  376  are coupled together. The drain terminals of the transistors  370  and  376  are both coupled to a node  374 . A second sawtooth capacitor  376  is coupled between the node  374  and a ground terminal  358   b . The source terminal of the second pull-down NMOS transistor  376  is coupled to the terminal  360  at which is provided the low voltage Vl. The gate terminals of the transistors  370  and  376  are coupled to a second gate node  382  that receives the CmdPb signal on the signal line  348 . 
         [0066]    A first NMOS coupling transistor  384  is coupled between the node  354  and a Vstp signal output node  386 . A gate terminal of the first NMOS coupling transistor  384  is coupled to the first gate node  382  that receives the CmdPb signal on the signal line  348 . Similarly, a second NMOS coupling transistor  388  is coupled between the node  374  and the Vstp signal output node  386 . A gate terminal of the second NMOS coupling transistor  388  is coupled to the first gate node  362  that receives the CmdP signal on the signal line  346 . 
         [0067]    In operation, the sawtooth generator circuit  306  has the oppositely phased timing signals CmdP and CmdPb alternately provided from the signal conditioning circuit  342 , as indicated in the timing diagram of  FIG. 8 . The sawtooth signal generator  306  receives the current signal IregP from the charge pump  316 . The sawtooth signal generator  306  alternately directs the current signal IregP to charge one of the sawtooth capacitors  356 ,  376  while the other one of the sawtooth capacitors  376 ,  356  is discharged to the Vl voltage level at terminal  360 . 
         [0068]    A HIGH level of the CmdPb signal on signal line  348  turns on the second NMOS pull-down transistor  376  to couple the second sawtooth capacitor  376  to the Vl voltage at the Vl terminal  360 . A HIGH level of the CmdP signal on signal line  348  also turns on the first NMOS coupling transistor  384  to couple the node  354  and the sawtooth capacitor  356  to the Vstp output terminal  386 . A corresponding LOW level of the CmdP signal on line  346  turns on the first pull-up PMOS transistor  350 , which couples the IregP current at terminal  353  to node  354  to charge the first sawtooth capacitor  356  with the IregP current. 
         [0069]    Alternately, a HIGH level of the CmdP signal on signal line  346  turns on the first NMOS pull-down transistor  352  to couple the first sawtooth capacitor  356  to the Vl voltage at the Vl terminal  360  to discharge the first sawtooth capacitor  356  to the Vl voltage level. A HIGH level of the CmdP signal on signal line  346  also turns on the second NMOS coupling transistor  388  to couple the node  374  and the sawtooth capacitor  376  to the Vstp output terminal  386 . A corresponding LOW level of the CmdPb signal on line  348  turns on the second pull-up PMOS transistor  370 , which couples the IregP current at terminal  353  to node  374  to charge the second sawtooth capacitor  376  with the IregP current. 
         [0070]      FIG. 18  illustrates various voltage waveforms for the reference clock signal CLK. The Vclk signal is a square wave. The rising edge of Vclk triggers the oppositely phased CmdP and CmdPb signals. These two oppositely phased alternately charge and discharge the two sawtooth capacitors  356 ,  376  to produce the sawtooth voltage Vstp, which starts at the Vl voltage level. 
         [0071]      FIG. 19  is a state transition diagram for the phase frequency comparator (PFC)  312  for the amplitude controlled sawtooth generator of  FIG. 12 . The phase frequency comparator  312  compares the comparator output signal Vcmp of the voltage comparator  310  with the falling edge of the reference CLK output signal from a reference clock circuit  314 . As discussed herein below, an embodiment of the pfc  312  is implemented as a state machine. The clock circuit  314  includes final calibration bits for adjusting the CLK duty cycle. For each period of the CLK signal at the falling edge of the CLK signal, the pfc  312  provides either an UP output signal or a DOWN output signal to a charge pump circuit  316 . The charge pump circuit  316  provides the output current IregP to the sawtooth signal generator  306  on a signal line  318 . A current feedback loop is formed by the sawtooth signal generator  306 , the voltage comparator  310 , the pfc  312 , and the charge pump  316  that provides the IregP signal to the sawtooth generator  306 . 
         [0072]      FIG. 20  is a timing diagram illustrating various signals for the phase frequency comparator of  FIG. 19 . 
         [0073]      FIG. 20  illustrates an example of the sawtooth signal generator system  300  starting up and not yet reaching a desired magnitude between Vlow, Vl, and Vhigh, Vh.  FIG. 20  shows the CLK signal with its rising and falling edges. The output sawtooth signal Vstp is shown in a startup mode in which the final desired magnitude of the sawtooth has not yet reached a desired magnitude. The Vstp signal starts at the Vl, or Vlow, level and rises toward the Vhigh level. At the point where the Vm signal is less than the Vstp voltage level, the output signal Vcmp of the comparator  310  transitions to a HIGH level. At the point where the Vm signal is greater than the Vm signal level, the output signal Vcmp of the comparator  310  transitions to a LOW level. 
         [0074]      FIG. 20  also illustrates the state of the phase frequency comparator PFC circuit  312 . A RESET state  410  occurs at the rising edge of the CLK signal. An UP state  412  occurs when the CLK has a falling edge and VCMP is also LOW, or 0 volts. When Vcmp goes HIGH, a second RESET state  414  occurs and remains after a rising edge of the CLK signal. Another falling edge of the CLK signal together with a LOW Vcmp signal provides a second UP state  416 . The second UP state  416  is cut short and changed to a third RESET state  418  at rising edge of the Vcmp signal. The third RESET state  418  continues at the rising edge of the CLK signal. If the desired magnitude of the sawtooth is not yet reached, for example, during the starting phase, the PFC  312  continues to provide UP signals to the IregP current. 
         [0075]      FIG. 21  illustrates one example of a charge pump circuit  420  that generates the IregP current for the sawtooth generator  306  of  FIG. 12 . A first constant current source  422  is coupled to a Vdd voltage source and, through a switch  424 , to a capacitor reference node  426 . The capacitor reference node  426  has a capacitor  447  coupled between it and a ground terminal  428   a . The switch  424  is closed in response to an UP signal to provide an Iref current to the capacitor reference node  426  to charge the capacitor  447  with an Iref current. 
         [0076]    A constant current sink  430  is coupled to a ground terminal  428   b  and through a switch  432  to the capacitor reference node  426 . The switch  432  is closed in response to a DOWN signal to draw an Iref current from the capacitor reference node  426  to discharge the capacitor  447  with an Iref current. 
         [0077]    The voltage at the capacitor reference node  426  is coupled to a gate terminal of an NMOS transistor  440 . A source terminal of the NMOS transistor  440  is coupled through a resistor  442  to a ground terminal  428   c  to establish a current that passes from a diode-connected PMOS transistor  444  that has a gate terminal and a drain terminal coupled together to a drain terminal of the NMOS transistor  440 . A source terminal of the diode-connected PMOS transistor  444  is coupled to the Vdd voltage source. The diode-connected PMOS transistor  444  and a second PMOS transistor  446  have their gate terminals coupled together to form a current mirror circuit. The second PMOS transistor  446  has a source terminal coupled to the Vdd voltage source. The drain terminal of the second PMOS transistor  446  provides a current IregP that tracks the voltage at the capacitor reference node  426  across the capacitor  447 . When the UP signal and the DOWN signal are not active, the IregP current remains fixed. 
         [0078]    During the “UP” sequence (i.e. UP=1 and Down=O), the capacitor  447  is charging through the Iref current source. This increases the voltage across the capacitor  447 . The transistor  440  and the resistor  442  are used as a voltage-to-current converter. As voltage on capacitor  447  increases, the current through transistor  440  increases. That current is mirrored through transistors  444 ,  446  to generate the source current IregP. During a “DOWN” sequence (i.e. UP=0 and DOWN=1) the capacitor  447  is discharging through the Iref current. This decreases the voltage across the capacitor  447 . As the capacitor  447  voltage decreases, the current through transistor  440  decreases. The current is mirrored through transistors  444 ,  446  to generate the source current IregP. When no action occurs on UP and DOWN signal the voltage stored on capacitor  447  maintains as the regulated output current for the feedback loop. 
         [0079]    The embodiment of the present invention of  FIG. 12  provides a sawtooth signal, the magnitude of which is based on the Vm voltage which is the average between Vh and Vl. A phase comparator and a charge pump are in a current regulated loop that controls the magnitude of the sawtooth wave. The present invention provides a sawtooth generator that provides a sawtooth signal with a precise amplitude and that is relatively insensitive to process variations. For that reason, no trimming is needed to calibrate the magnitude of the sawtooth signal. The present invention is based on charge per unit time, or current, that is provided by a voltage-to-current charge pump stage and that is injected into a capacitor in the sawtooth generator. The charge is proportional to the instantaneous phase error between the sawtooth wave generated by the current regulated loop and the reference clock calibrated with a duty cycle of 50 percent. The amplitude of the sawtooth is adjustable by varying the duty cycle of the reference clock. 
         [0080]    The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.