Abstract:
A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.

Description:
FIELD OF THE INVENTION 
     The invention pertains to delay circuits, in general, and to a digital delay circuit, in particular. 
     BACKGROUND OF THE INVENTION 
     One problem with prior art digital delay circuits is that the time delay produced by the circuit will vary in dependence on the threshold voltage of the logic circuit coupled to the time determining capacitor. 
     It is therefore desirable to provide a digital time delay circuit in which the logic threshold voltage does not influence the time delay. 
     SUMMARY OF THE INVENTION 
     In accordance with the principles of the invention, a digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the, timing circuits are substantially eliminated. 
     In accordance with the principles of the invention, a digital delay circuit for delaying a digital signal by a predetermined time delay, comprises first and second identical delay circuits. The first delay circuit has an input coupled to a first node. The second delay circuit has an output coupled to an output node. The first delay circuit is connected in cascade to the second delay circuit via an intermediate node. 
     The first delay circuit comprises a first capacitor, first and second switched current sources each coupled to the first capacitor and each having a control input coupled to the input node, the first switched current source sources current to the first capacitor when a signal at the input node is at a first level and said the switched current source sinks current from the first capacitor when the signal is at a second level. The source current and the sink current are each of the same magnitude. A first digital circuit has an input coupled to the capacitor and is coupled to an intermediate node. The first digital circuit has a first input threshold voltage level, and provides an output at the intermediate node that is at one level when the capacitor voltage is below the threshold voltage level and provides an output at the intermediate node that is at a second level when the capacitor voltage is above the threshold voltage level. 
     The second delay circuit comprises a second capacitor, third and fourth switched current sources each coupled to the second capacitor and each having a control input coupled to the intermediate node, the third switched current source sourcing current to the second capacitor when a signal at the intermediate node is at a first level and the second switched current source sinking current from the second capacitor when the signal at the intermediate node is at a second level, the sourcing current and the sinking current each being of the same magnitude; a second digital circuit having an input coupled to the second capacitor and having an output coupled to the output node, the second digital circuit having a second input threshold voltage level equal to the first input threshold voltage level, the digital circuit providing an output at the output node that is at one level when the second capacitor voltage is below the threshold voltage level and providing an output at the output node that is at a second level when the second capacitor voltage is above the input threshold voltage level; whereby the digital delay circuit provides a time delay that is independent of the threshold voltage level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The invention will be better understood from a reading of the following detailed description of the drawing in which like reference designators are used to identify like elements in the various drawing figures, and in which: 
         FIG. 1  is a representation of a prior art digital delay circuit; 
         FIG. 2  illustrates waveforms in the prior art digital delay circuit of  FIG. 1 ; 
         FIG. 3  is a diagram of a digital delay circuit in accordance with the principles of the invention; and 
         FIG. 4  illustrates waveforms of the circuit of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 and 2  illustrate the problem to which the present invention is directed. Delay circuit  1  utilizes an electronic switch  101  that responds to an input signal to provide a time delay. Switch  101  controls the charge and discharge of a capacitor C from a current source I. As can be seen from  FIG. 2 , when switch  101  opens, the voltage across capacitor C, voltage Vc, increases in accordance with the relationship of I/C=ΔV/Δt. As Vc increases from a first voltage level, zero volts, to a second voltage level, Vdd, it increases at a slope of I/C. 
     A digital circuit  103 , represented by an inverter, is coupled to the capacitor C and is responsive to the capacitor voltage Vc. Digital circuit  103  has a threshold voltage Vth at which the output voltage of digital circuit  103  changes state. 
     Turning now to  FIG. 2 , the state of switch  101  is shown by curve  201 , the voltage across capacitor C, Vc, is shown by curve  203 , and the output voltage of digital circuit  103  is shown by curve  205 . 
     When switch  101  is in a first or closed state, the output voltage Vo of digital circuit  103  is in a first or high state. When switch  101  changes state from its first or closed state to a second or open state, the voltage Vc begins to rise at a slope of I/C. The output voltage of digital circuit  103  initially remains in a first or high state. After a time delay Δt, voltage Vc reaches the switching threshold voltage Vth of the digital circuit  103  and the output voltage Vo of digital circuit  103  switches from its first or high state to its second or low output state. 
     The time delay Δt is dependent on the switching threshold voltage by the equation Δt=Vth (C/I). Unfortunately, the switching threshold voltage will vary with temperature and from device to device depending upon manufacturing process. 
       FIG. 3  shows an illustrative embodiment of a delay circuit  300  in accordance with the principles of the invention. Circuit  300  includes two identical delay stages  301 ,  303 . Delay circuit  300  is provided on an integrated circuit  302  that may or may not include other circuitry. 
     Each delay stage  301 ,  303  includes input inverter  3011 ,  3021  and an output inverter  3013 ,  3023 . Each inverter or digital circuit  3011 ,  3021 ,  3013 ,  3023  has the same input switching threshold voltage Vth and the input switching threshold voltages of the inverters or digital circuits  3011 ,  3021 ,  3013 ,  3023  all vary identically with temperature. 
     Input inverters  3011 ,  3021  are coupled to the control input of corresponding electronic switches  3015 ,  3025 . Electronic switches  3015 ,  3025  function as single pole double throw type switches and are used to selectively couple either a current source  3017 ,  3027  or a current sink  3019 ,  3029  to respective capacitors Cl, C 2 . Current sources  3017 ,  3027  and current sinks  3019 ,  3029  each source or sink the same level of current I. 
     Turning now to  FIG. 4 , waveforms are shown for the input voltage Vin, capacitor voltage V A , capacitor voltage V B , voltage V 1 , and output voltage Vout. The waveforms for capacitor voltage V A  and capacitor voltage V B  are superimposed on each other. 
     The time delay, Δtrise, between the rising edges of Vin and Vout as well as the time delay, Δtfall, between the falling edges of Vin and Vout are a function of the current I, the capacitance C of capacitors C 1 , C 2  and the supply voltage Vdd which are all independent of the threshold voltage of the inverters  3011 ,  3021 ,  3013 ,  3023 . More specifically Δtrise=Δtfall=Vdd(C/I). In addition, Δtrise is the sum of the time tar for the voltage V A  to rise from zero to Vth plus the time tbf for the voltage V B  to fall from Vdd to Vth; and Δtfall is the sum of the time taf for the voltage V A  to fall from Vdd to Vth plus the time tbr for the voltage V B  to rise from zero to Vth. 
     As the voltage Vth varies with temperature or because of process parameters, the effect of a variable Vth is eliminated by utilizing both rise and fall times from zero to Vth and from Vdd to Vth to determine the time delay. 
     The digital delay circuit  300  delays a digital signal by a predetermined time delay independent of the threshold voltage of the digital inverters or circuits utilized. Delay circuit  300  comprises an input node  3200 ; an output node  3300 ; a first delay circuit  301  coupled to the input node  3200 ; a second delay circuit  303  coupled in cascade to the first delay circuit  301  and coupled to the output node  3300 , The first delay circuit  301  comprises a first capacitor Cl, first and second switched current sources  3017 ,  3019  each coupled to the first capacitor Cl and each having a control input coupled to the input node  3200 . The first switched current source  3017  sourcing current to the first capacitor Cl when a signal at the input node  3200  is at a first level  0  volts. The second switched current source  3019  sinking current from the first capacitor Cl when the signal at node  3200  is at a second level. The sourcing current and the sinking current each being of the same magnitude I. The first digital circuit  3013  has an input coupled to capacitor C 1  and an output at an intermediate node  3400 . First digital circuit  3013  has a first input threshold voltage level Vth. First digital circuit  3013  provides an output at intermediate node  33400  that is at one level, zero, when the capacitor voltage V A  is below the threshold voltage level Vth and provides an output at intermediate node  3400  that is at a second level Vdd when the capacitor has a voltage above the threshold voltage level. A second delay circuit  303  comprises a second capacitor C 2 , third and fourth switched current sources  3027 ,  3029  each coupled to the second capacitor C 2  and each having a control input coupled to the intermediate node  3400 . Third switched current source  3027  sources current to the second capacitor C 2  when a signal at the intermediate node  3400  is at a first level and the fourth switched current source  3029  sinking current from the second capacitor C 2  when the signal at the intermediate node  3400  is at a second level. The sourcing current and the sinking current are each of the same magnitude I. 
     A second digital circuit  3023  has an input coupled to the second capacitor C 2  and has an output coupled to the output node  3300 . Second digital circuit  3023  has an input threshold voltage level equal to the first input threshold voltage level Vth. Second digital circuit  3023  provides an output at the output node  3300  that is at one level when the second capacitor voltage V B  is below the threshold voltage level Vth and provides an output at the output node  3300  that is at a second level when the second capacitor voltage V B  is above the input threshold voltage level Vth. Digital delay circuit  300  provides a time delay that is independent of the threshold voltage level Vth of the digital circuits or inverters  3011 ,  3021 ,  3013 ,  3023 . 
     The invention has been described in conjunction with a specific illustrative embodiment. It will be understood by those skilled in the art that various changes, substitutions and modifications may be made without departing from the spirit or scope of the invention. It is intended that all such changes, substitutions and modifications be included in the scope of the invention. It is not intended that the invention be limited to the illustrative embodiment shown and described herein. It is intended that the invention be limited only by the claims appended hereto, giving the claims the broadest possible scope and coverage permitted under the law.