Abstract:
To provide a power supply switching circuit which avoids an increase in current consumption. A power supply switching circuit includes MOS transistors provided between power supply input terminals and an output terminal, which have gates connected to each other and backgates connected to each other and are connected in series.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2015-023426 filed on Feb. 9, 2015, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a power supply switching circuit which is suitable for use in a semiconductor device supplied with power from a main power supply and a sub power supply, and which switches the supply of power from the main power supply to the sub power supply when the supply of the power from the main power supply is stopped. 
         [0004]    2. Background Art 
         [0005]      FIG. 3  is a circuit diagram illustrating a related art power supply switching circuit. 
         [0006]    The related art power supply switching circuit is equipped with a main power supply input terminal  200  supplied with a voltage V 0  of a main power supply, a sub power supply input terminal  201  supplied with a voltage V 1  of a sub power supply, PN junction elements  202  and  203 , and an output terminal  204  which outputs a voltage Vout. 
         [0007]      FIG. 4  is a sectional structure diagram of a PN junction element of a related art power supply switching circuit. 
         [0008]    The PN junction element is realized by defining an N-type region  208  provided in a P-type region  209  of a substrate as a cathode terminal  206  and defining a P-type region  207  provided in the N-type region  208  as an anode terminal  205 . Incidentally, the P-type region  209  of the substrate is supplied with the lowest voltage (VSS) to avoid the flow of an extra forward bias current between the P-type region  209  thereof and the N-type region adjacent to the P-type region  209 . 
         [0009]    The related art power supply switching circuit is intended to achieve the stable supply of power to a semiconductor device by supplying power from the sub power supply in a backup operating state in which power from the main power supply is stopped. 
         [0010]    [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-87994 
       SUMMARY OF THE INVENTION 
       [0011]    The related art power supply switching circuit is however accompanied by a problem that since a PN junction element forward-biased in a path supplied with power when the power is supplied exists, a collector current flows into a parasitic PNP type bipolar element, thereby increasing current consumption. 
         [0012]    The present invention has been invented to solve the foregoing problem and provides a power supply switching circuit low in current consumption. 
         [0013]    In order to solve the related art problem, the power supply switching circuit of the present invention is configured as follows: 
         [0014]    The power supply switching circuit is provided which switches power supplies of a semiconductor device supplied with power from a plurality of power supply input terminals and outputs the switched power supply to an output terminal, and which includes MOS transistors between the power supply input terminals and the output terminal, which have gates connected to each other and backgates connected to each other and are connected in series. 
         [0015]    According to the power supply switching circuit of the present invention, it is possible to provide a power supply switching circuit low in current consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a circuit diagram illustrating a power supply switching circuit of the present embodiment; 
           [0017]      FIG. 2  is a circuit diagram illustrating another example of the power supply switching circuit of the present embodiment; 
           [0018]      FIG. 3  is a circuit diagram illustrating a related art power supply switching circuit; and 
           [0019]      FIG. 4  is a sectional structure diagram of a PN junction element of a related art power supply switching circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    A power supply switching circuit of the present embodiment will hereinafter be described with reference to the accompanying drawings. 
         [0021]      FIG. 1  is a circuit diagram illustrating a power supply switching circuit of the present embodiment. 
         [0022]    The power supply switching circuit of the present embodiment is equipped with a main power supply input terminal  200  supplied with a voltage V 0  of a main power supply, a sub power supply input terminal  201  supplied with a voltage V 1  of a sub power supply, MOS transistors  100 ,  101 ,  110  and  111 , and an output terminal  204  which outputs a voltage Vout. 
         [0023]    The MOS transistor  100  has a drain connected to the main power supply input terminal  200 , and a source and a backgate connected to each other. The MOS transistor  101  has a gate and a drain connected to a gate of the MOS transistor  100  and the output terminal  204 , and a source and a backgate connected to the source and backgate of the MOS transistor  100 . The MOS transistor  110  has a drain connected to the sub power supply input terminal  201 , and a source and a backgate connected to each other. The MOS transistor  111  has a gate and a drain connected to a gate of the MOS transistor  110  and the output terminal  204 , and a source and a backgate connected to the source and backgate of the MOS transistor  110 . 
         [0024]    The operation of the power supply switching circuit of the present embodiment will next be described. 
         [0025]    Since the MOS transistor  100  is brought to an on state in a normal operating state in which the voltage V 0  is higher than the voltage V 1 , a drain voltage VA becomes substantially equal to the voltage V 0 . Since a source voltage (voltage VA) is substantially equal to the voltage V 0 , the MOS transistor  101  is brought to an on state, so that the voltage V 0  of the main power supply is supplied to the output terminal  204 . 
         [0026]    Here, since V 0 ≈VA, no forward bias voltage is applied to a PN junction element between the drain and backgate of the MOS transistor  100 . Thus, since a PNP type bipolar element in which the PN junction element between the drain and backgate of the MOS transistor  100  is assumed to be an emitter and a base, and a P region  209  of a substrate is assumed to be a collector, is not turned on, no collector current flows. Thus, an increase in current consumption of the power supply switching circuit does not occur. 
         [0027]    On the other hand, since in a path of the sub power supply, the MOS transistor  110  has a gate voltage being apparently higher than a source voltage, and a PN junction element between the drain and backgate of the MOS transistor  110  is apparently reverse-biased, no current flows into the MOS transistor  110 . Thus, it becomes possible to suppress inflow current into the sub power supply input terminal  201 , i.e., the sub power supply. 
         [0028]    Since the MOS transistor  110  is brought to an on state in a backup operating state in which the voltage V 0  is lower than the voltage V 1 , a drain voltage VB becomes substantially equal to the voltage V 1 . The MOS transistor  111  is brought to an on state because a source voltage (voltage VB) is substantially equal to the voltage V 1 , so that the output terminal  204  is supplied with the voltage V 1  of the sub power supply. 
         [0029]    Here, since V 0 ≈VA, no forward bias voltage is applied to the PN junction element between the drain and backgate of the MOS transistor  110 . Thus, since a PNP type bipolar element in which the PN junction element between the drain and backgate of the MOS transistor  110  is assumed to be an emitter and a base, and the P region  209  of the substrate is assumed to be a collector, is not turned on, no collector current flows. Thus, an increase in current consumption of the power supply switching circuit does not occur. 
         [0030]    On the other hand, since in a path of the main power supply, the MOS transistor  100  has a gate voltage being apparently higher than a source voltage, and the PN junction element between the drain and backgate of the MOS transistor  100  is apparently reverse-biased, no current flows into the MOS transistor  100 . Thus, it becomes possible to suppress inflow current into the main power supply input terminal  200 , i.e., the main power supply. 
         [0031]    According to the power supply switching circuit of the present embodiment, as described above, it is possible to provide a power supply switching circuit low in current consumption. Further, there is provided a power supply switching circuit which takes into consideration even the suppression of inflow current into each power supply. 
         [0032]    Incidentally, although the circuit of  FIG. 1  has been described in the above by way of example under the presumption that it is the power supply switching circuit for the main power supply and the sub power supply, it is possible to obtain an effect similarly even with respect to three or more power supplies. For example, as with the MOS transistors  100  and  101  for the main power supply, transistors may similarly be provided in other power supplies. 
         [0033]    Further, although the gate voltage of each transistor has been described as being supplied by the output terminal  204  of the power supply switching circuit, the gate of the transistor in the path which supplies power may be supplied with a voltage lower than the output of the power supply switching circuit, and the gate of the transistor in the path which does not supply power may be supplied with a voltage higher than the output of the power supply switching circuit. As illustrated in  FIG. 4 , for example, the gate of the transistor may be connected to the other input terminal.