Abstract:
In order to generate an output signal delayed compared to an input signal and with a defined mark-to-space ratio, it is useful to produce at least first and second intermediate signals delayed differently with respect to the input signal and to combine them to form the output signal so that a rising (or negative) edge of the first intermediate signal determines a rising edge of the output signal, and a rising (or negative) edge of the second intermediate signal determines a falling edge of the output signal. In particular a plurality of successive versions of an input timing signal delayed by an equal amount can be generated with a mark-to-space ratio of 50%.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This Utility Patent Application claims priority to German Patent Application No. DE 103 01 239.7, filed on Jan. 15, 2003, which is incorporated herein by reference. 
   BACKGROUND 
   The present invention relates to a method and a device for producing an output signal that is delayed compared to an input signal. In particular the invention relates to a method and a device for producing a plurality of output signals that are in each case delayed by a defined phase angle compared to an input signal, and that have a mark-to-space ratio of for example 50%. 
   For the purposes of data recovery by oversampling, many versions of an input timing signal delayed by identical times or phase angles are required, with which various sampling elements can be controlled. In order not to let the number of signals become too high, it is desirable to be able to initiate a sampling procedure with the rising edge as well as with the falling edge of each signal. For this purpose it is necessary that the signals have an accurately defined mark-to-space ratio, in particular a mark-to-space ratio of 50%. 
   In order to delay the input timing, delay elements are generally employed. On account of process-conditioned differences between the components in the delay elements, however, the mark-to-space ratio deviates from the desired value, however, for example by 50%. This deviation becomes increasingly larger in the course of a chain of delay elements since the errors to some extent add up. In addition, there is the deviation that arises if the input signal of the chain already deviates from the desired value, for example by 50%. 
   With a relatively large number of delay elements, the mark-to-space ratio at the end of the chain deviates to such an extent from the desired value that it is no longer possible to use the rising edge as well as the falling edge of the signal since the result would be too inaccurate. 
   In principle, it would be possible to regulate the mark-to-space ratio actively. This means, however, a high switching expenditure in the case of high frequencies in some cases above 1 GHz, as are required for oversampling at high data rates. 
   SUMMARY 
   One embodiment of the present invention provides a method and a device with which a signal that is delayed compared to an input signal can be generated with an accurate predetermined mark-to-space ratio. 
   According to one embodiment of the invention, it is proposed to form at least two intermediate signals that are delayed by different amounts compared to an input signal and then to combine a first intermediate signal and a second intermediate signal different therefrom, of these intermediate signals, to form an output signal, in such a way that a rising edge of the output signal corresponds to a rising or falling edge of the first intermediate signal and a falling edge of the output signal corresponds to a rising or falling edge of the second intermediate signal. The mark-to-space ratio of the output signal is thereby defined by the delay between the first and the second intermediate signal. 
   In one embodiment, the delayed intermediate signals are formed by a delay chain, that is, by successive delay of the input signal. In order to form a plurality of output signals delayed in each case by the same times with a mark-to-space of 50%, 2k(k=1, 2 . . . ) successive intermediate signals delayed substantially by 360°/(2k) compared to the input signal are formed. Those intermediate signals whose delay with respect to one another is substantially 180° are then combined to form an output signal. These signals may be combined, for example, by a multiplexer in such a way that the respective multiplexer forms, depending on a control signal, the first intermediate signal or the second intermediate signal in inverted form as the output signal. A further one of the intermediate signals may be used in this connection as control signal. For a mark-to-space ratio of 50% an intermediate signal may be used that has an absolute delay of substantially 90° with respect to the first as well as to the second intermediate signal, that is, lies exactly between the first and the second intermediate signal. In order to obtain a greater accuracy of the emitted output signal, one embodiment employs a regulation in the form of a delay regulation loop or delay-locked loop (DLL). In this connection the delay of the intermediate signal is regulated so that the intermediate signal with the greatest delay experiences a delay of substantially 360° with respect to the input signal. In this way, when the delay chain described above is used the overall delay remains constant and a process variability of the individual delay elements is partially compensated. 
   The method and device according to one embodiment of the invention have the advantage that the delay caused by delay elements reacts less sensitively to the process variability than does the mark-to-space ratio. Since the mark-to-space ratio of the output signal is defined in the present invention by the delays of the intermediate signals, the mark-to-space ratio can thus be accurately adjusted. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
       FIG. 1  illustrates a circuit diagram of an example of implementation of a device according to one embodiment of the invention. 
       FIG. 2  illustrates an enlarged section of the circuit diagram illustrated in  FIG. 1 . 
       FIG. 3  are examples of signal waveforms. 
       FIG. 4  illustrates a block diagram of a delay locked loop according to one embodiment of the invention. 
       FIG. 5  illustrates the waveform of regulating signals depending on the delay of the intermediate signals in the delay locked loop illustrated in  FIG. 4 . 
   

   DETAILED DESCRIPTION 
   The circuit diagram of a device according to one embodiment of the invention is illustrated in  FIG. 1 . 
   When the circuit is in operation an input timing signal is fed to a connection  34 . The timing signal is delayed by a chain of nominally identical delay elements  1  to  19 . For reasons of space, the chain of delay elements  1  to  19  is shown folded, whereas in one embodiment the actual implementation is realized in extended form, in which the lines corresponding to one another are as far as possible all be equally long and symmetrical. 
   Multiplexers  20  to  30  and buffers  33  are connected up to the delay elements  1  to  19  as illustrated in  FIG. 1 . The delayed output signals can be tapped at the outputs  35  of the multiplexers  23  to  30 . 
   The first two delay elements  1  and  2  of the delay chain serve to form pulses. So that the zero passages have regular interspacings at all outputs  35 , the signals within the chain should all have the same shape. Due to the combination of amplification and band limitation, in a chain of identical stages such a shape is already formed after a few stages, in the present case two stages, by the delay elements. So that all stages are actually identical, they must also be loaded identically. For this reason the multiplexers  20  and  21  and buffer stages  33  are also present when their output signals are not used. In the present example of implementation the loading due to these elements changes only slightly, however, when they are connected in a currentless manner. This is therefore effected in all elements, for example in the multiplexers  20  and  21 , whose output signals are not used in the circuit. The actual input signal for the production of the delayed output signals is present at the output of the delay element  2 . 
   The actual chain consists of the 16 delay elements  3  to  18 . So that the last delay element  18  of this actual chain experiences the same load as the remaining elements  3  to  17 , a delay element  19  is additionally present as load at the end of the chain. In the illustrated example of implementation the nominal delay of each delay element is 22.5° or 1/16 of a period, so that overall a delay of around 360° is achieved by the delay elements  3  to  18 . In order to produce the output signals that are to be tapped at the outputs  35 , in each case two delayed signals are combined by the multiplexers  23  to  30  to form a respective output signal. 
   The interconnection of the multiplexers  23  to  30  is illustrated on an enlarged scale in  FIG. 2  with the example of the multiplexer  24 . In the illustrated section the signal after the delay element  4  is present at a first input  37  and the signal after the delay element  12  is present at a second input  38 . In this connection the circuit connections are such that the signal after the delay element  12  is present inverted at the multiplexer  24 , which may be effected in this case with differential signals by simply transposing the lines. Eight delay elements, that is, half of the actual chain, thus lie between the two signals present at the inputs  37  and  38 . In the example discussed above, in which each delay element produces a delay of 22.5°, this means a delay of around 180° between the signal present at the input  37  and the signal present at the input  38 . 
   In addition, a control signal is fed to the multiplexer  24  at a control input  36 , which signal is tapped after the delay element  8 , that is, exactly halfway between the delay element  4  and the delay element  12 . 
   Possible signal waveforms at the inputs  36  to  38  and at the output  35  of the multiplexer  24  are illustrated in a time-dependent manner by way of example in  FIG. 3 . 
   In this connection, ZS 1  denotes the first intermediate signal tapped after the delay element  4 , which is fed to the multiplexer  24  at the input  37 . ZS 2  denotes the second intermediate signal tapped after the delay element  12 , which is then fed in inverted form to the second input  38  of the multiplexer. The intermediate signals ZS 1  and ZS 2  have a phase shift of 180° with respect to one another. 
   In addition, a control signal SS is formed, which is tapped after the delay element  8  and is fed to the multiplexer at its control input  36 . This is displaced by 90° with respect to the first intermediate signal ZS 1  and is in advance of the second intermediate signal ZS 2  by 90°. The multiplexer combines the first intermediate signal ZS 1  and the second intermediate signal ZS 2  now in such a way that, if the control signal has a logic value 0, the first intermediate signal ZS 1  produces the output signal, whereas if the control signal SS has a logic value 1, the second intermediate signal ZS 2  in inverted form forms the output signal. The waveform of the output signal is illustrated by AS in  FIG. 3 . 
   In the illustrated example the intermediate signals ZS 1  and ZS 2  that are formed from the input signal have a mark-to-space ratio that differs by 50%. The output signal AS has on the other hand a mark-to-space ratio of 50%. This is achieved by the delay of the intermediate signal ZS 2  compared to the intermediate signal ZS 1  of 180°, and of the control signal SS compared to the intermediate signal ZS 1  of 90°. The control signal SS controls the multiplexer  24  so that a rising edge of the intermediate signal ZS 1  results in a rising edge of the output signal AS, whereas a rising edge of the intermediate signal ZS 2  results in a falling edge of the output signal AS. 
   Other delays between the intermediate signals and the control signal are also conceivable in order to produce an output signal with a different desired mark-to-space ratio. In addition, the circuitry may also be designed so that in each case the falling edges of the intermediate signals ZS 1  and ZS 2  determine the position of the edges of the output signal AS. 
   It should also be noted in this connection that the frequency is not altered by the combination of the signals ZS 1  and ZS 2 , that is, the output signal AS has the same frequency as the intermediate signals ZS 1  and ZS 2  produced from the input signal. The mark-to-space ratio, however, can be adjusted due to the delay. 
     FIG. 1  additionally illustrates a phase detector  31  that controls a charge pump  32 . The charge pump in turn controls the delay of the delay elements  1  to  19 . The control lines required for this purpose are for reasons of clarity not shown in  FIG. 1 . This arrangement forms a delay regulation system (delay locked loop, DLL). In one embodiment, the regulation is performed in such a way that overall a delay of 360°, that is, a complete period is achieved through the delay elements  3  to  18 . In this way a rising edge of the input signal present at the delay element  3  of the actual delay chain covers a rising edge of the signal present after the delay element  18 . In the illustrated example of implementation the phase detector  31  receives as input signal the signal before the delay element  3 , that is, the input signal of the actual delay chain (which consists of the delay elements  3  to  18 ), an intermediate signal that is tapped after the delay element  6 , that is, after a quarter of the chain, and the intermediate signal after the delay element  18 , that is, at the end of the chain. These signals are fed to the phase detector  31 , in each case via buffers  33 . 
     FIG. 4  illustrates an example of implementation of a delay regulation system such as may be used for example in the example of implementation illustrated in  FIG. 1 . 
   In  FIG. 4  the delay chain of  FIG. 1  is illustrated in simplified form. For the simplified representation in each case four delay elements of the actual delay chain consisting of the delay elements  3  to  18  are shown combined as delay blocks  40 ,  41 ,  42  and  43 . Each of these delay blocks delays the signal nominally by a quarter period, or by 90°. An input signal  39  is fed to this delay chain, the signal corresponding in  FIG. 1  to the signal present before the delay element  3 . The phase detector  31  substantially comprises three logic elements, an NOT element  45  and two AND elements  46  and  47 . The input signal  39 , the intermediate signal at the end of the delay chain, that is, with the largest delay, after the delay block  43  and a further intermediate signal after the delay block  40  are fed to the phase detector. Two delay regulation signals are generated by the logic elements  45  to  47 . The AND element  46  emits a first delay regulation signal (“down signal”), which indicates that the overall delay should be corrected downwardly. The AND element  47  emits a second delay regulation signal (“up signal”), which specifies that the overall delay of the delay chain should be corrected upwardly. Depending on the supplied signals, the delay regulation signals appear as illustrated in the following table: 
   
     
       
             
             
             
             
             
           
         
             
                 
             
             
                 
               Further 
               Intermediate 
               First Delay 
               Second Delay 
             
             
               Input 
               Intermediate 
               Signal with 
               Regulation 
               Regulation 
             
             
               Signal 
               Signal 
               Greatest Delay 
               Signal 
               Signal 
             
             
                 
             
           
           
             
               0 
               0 
               0 
               0 
               0 
             
             
               1 
               0 
               0 
               1 
               0 
             
             
               0 
               1 
               0 
               0 
               0 
             
             
               0 
               0 
               1 
               0 
               1 
             
             
               1 
               1 
               0 
               0 
               0 
             
             
               1 
               0 
               1 
               1 
               1 
             
             
               0 
               1 
               1 
               0 
               0 
             
             
               1 
               1 
               1 
               0 
               0 
             
             
                 
             
           
        
       
     
   
   These delay regulation signals are passed on further by an element  48  to the charge pump  32 . The charge pump  32  in turn controls the delay blocks  40  to  43  and the delay elements  1  to  19 . This control and regulation is carried out in such a way that the overall delay of the delay elements  40  to  43  is 360°. Since the delay elements are nominally identical, the delay of each individual delay element  40  to  43  is substantially 90°, and of each individual delay element  1  to  19  is substantially 22.5°. 
   The characteristics of the phase detector are illustrated in  FIG. 5 . The waveforms of the delay regulation signals and of an overall or effective delay regulation signal resulting therefrom are shown as a function of the delay of a delay block. 
   In each case, the on period of the delay regulation signal is plotted in relation to the period duration over the phase delay of a delay block with four delay elements, in which the characteristic line (i) corresponds to the first delay regulation signal, the characteristic line (ii) corresponds to the second delay regulation signal and the characteristic line (iii) corresponds to the effective or overall delay regulation signal resulting therefrom. 
   It should be noted that the linear waveform of the overall delay regulation signal is around 90° or 0.25. This means a regulation to the value of 0.25 or 90° for the individual delay blocks. The phase detector delivers a signal of correct polarity up to at least approximately double the nominal delay. Due to production variations it could happen that the unstable operating point of the system in the case of double the nominal delay becomes a stable operating point. The output signal of the phase detector is proportional to the deviation as long as the delay deviates less than a third of the nominal value. 
   It should be noted that in principle other forms of embodiment of the delay locked loop are of course also conceivable. Due to the fact that the overall delay is regulated to 360°, process deviations of the individual delay elements are less strongly manifested in the output signal.