Abstract:
A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to semiconductor devices, and more particularly, to gated-diodes that includes capping dielectric layers within the active semiconductor structures. 
       BACKGROUND AND RELATED ART 
       [0002]    Semiconductor diodes, in particular gated-diodes, are often used in CMOS integrated circuits for important analog circuit functions including temperature sensing and bandgap reference voltage applications. For the analog applications to properly function, the forward-bias diode characteristics should be nearly ideal, as measured by the diode ideality factor (n) which should be nearly equal to a value of 1. In advanced CMOS technologies, achieving a gated-diode structure with good ideality near 1 can be challenging because of the widespread use of Reactive Ion Etching (RIE), which can damage then semiconductor structures. RIE related damage is known to degrade diode ideality. Thus, in order to achieve a good diode ideality, the RIE damage should be eliminated or minimized. 
         [0003]    Diodes in general are formed by creating abutting semiconducting regions of N-doped (excess electrons) and P-doped (excess holes). Preferably, one but not both regions is more heavily doped, creating either an N+/P diode or a P+/N diode. N-doped regions are typically formed by implanting or diffusing N-type donor dopant species, such as arsenic or phosphorus, into the semiconductor material such as silicon. Similarly, P-doped regions are formed by implanting or diffusing P-type acceptor dopant species, e.g., boron into a region adjacent to and contacting the N-type region. Typically, a dopant activation thermal cycle or heating is necessary to make the dopants electrically active. 
         [0004]    Gated-diodes formed as described, with the addition of a gate electrode and gate dielectric located at or near the location of the P-N junction. Often but not always, the gate electrode serves as a masking structure to allow creating a self-aligned P-N diode wherein the edge of the gate electrode defines the location of the P-N junction. Self-alignment can be achieved when the P-N junction is formed by ion implantation, and the gate electrode is sufficiently thick to block either the heavier P+ or N+ region implant from penetrating through to the underlying semiconductor substrate, and is wide enough laterally to allow a photolithography mask to consistently land on the gate even in the presence of loose manufacturing alignment tolerances. Generally, it can be advantageous to achieve good diode ideality by locating the P-N junction underneath the gate electrode and gate dielectric because this region is typically a high quality interface largely free of defects. Avoiding defects in and around the P-N junction region is important for achieving good ideality, as defects are known to create generation and/or recombination sites which degrade the diode ideality. 
         [0005]    Dielectric capping layers (such as nitride or oxide) on top of gates are commonly used in CMOS fabrication. Examples of the uses for these dielectric capping layers include use as a hard mask for gate electrode patterning and increasing the gate stack thickness for ion implantation blocking effectiveness. A gate electrode hard mask is a layer or layers patterned on top of a blanket gate electrode, which protects desired regions from RIE, thus forming patterned gate electrodes. This is in contrast to soft mask based patterning where the pattern is formed using photoresist. Oftentimes it is beneficial to keep the dielectric hard mask on top of the gate even after the gate electrode etching has been completed and during subsequent ion implantation steps required for building the gated-diode and Field Effect Transistors (FET). The additional dielectric layer contributes to blocking ion implantations, such as source/drain or halo implants from penetrating through the gate electrode into the channel. The dielectric layer is typically removed by RIE prior to a silicide formation, to enable the gate electrode region to be silicided. However, RIE can damage and introducing defects within and nearby the gated diode (P-N junction) region, resulting in a degraded ideality, that ultimately leads to poor circuit functionality in temperature sensor, bandgap reference voltage and other analog circuits that rely on good diode ideality. 
         [0006]    Generally, all the gates and diffusions of a sub 250 nm technology have silicide formed to minimize resistance, knowing that silicidation of silicon and polysilicon regions reduces the resistance which results in increased transistor and circuit performance. 
         [0007]      FIG. 1  is a perspective view of a prior art structure for a diode and a FET as part of integrated circuit. For simplicity, a single N-FET is shown, but it should be understood that N-FETs and P-FETs can be used together as part of CMOS integrated circuits. The fabrication sequence for the conventional structure shown in  FIG. 1  results in damage to the diode which degrades the diode ideality. Note that in this prior art structure and P+/N diode is shown, but it should be understood that an N+/P diode can also be used. 
         [0008]    Accordingly, there is a need for a structure that provides the benefits of a dielectric capping layer on top of the gate electrode of the gated-diode to avoid the diode ideality degradation of removing the capping layer that is desired for advanced CMOS integrated circuits. 
       SUMMARY 
       [0009]    In one aspect, an embodiment of the invention provides a chip having an FET with a silicided high-K gate stack, source, and drain on high performance devices, with an adjoining diode having a silicided cathode and anode regions and a non-silicided high-K gate stack structure, the use of silicide implying a gate first high-K metal gate process with polysilicon in the stack. 
         [0010]    In another aspect, an embodiment provides a polysilicon gate of the gated-diode that does not require silicidation as a gate terminal which is not intended to carry a significant current if the gate dielectric is sufficiently thick, such that the higher resistance of the non-silicided polysilicon is not a concern. The polysilicon gate of the gated-diode separates the cathode and anode implants, blocking the silicide between the anode and cathode. Because the gate electrode of the gated-diode does not require siliciding, it avoids the need to remove the cap from the gate over the device. By protecting the gated-diode with resist during a cap removal etching process, damage to the gated-diode due to etching can be avoided in view of etching a gate capping layer creates recess and damage in silicon regions near the diode P-N junction that degrades the diode ideality. By avoiding damage, an excellent diode ideality can be achieved. With the cap layer in place on top of the gate, silicide is not formed on the gate, but as described previously, the gate terminal of a gated-diode does not need to carry significant current. Hence, a higher resistance of non-silicided gate terminal is not a concern. 
         [0011]    In yet another aspect, a semiconductor structure is provided with a silicided high-K gate stack, source, and drain on high performance NFETs/PFETs and a gated-diode having a silicided anode and cathode regions and non-silicide HiK gate stack structure, the use of a silicide on the high-K gate stack of the FET implying a gate-first high-K metal gate process with polysilicon in the stack. 
         [0012]    In still another aspect, a semiconductor integrated circuit is provided with an n-FET and/or a p-FET having a silicided gate, source, drain, and a gated-diode with silicided anode and cathode regions, and a non-silicided gate. The NFETs/PFETs, gated-diodes and other active or passive devices are connected to metal wiring to form an integrated circuit. 
         [0013]    In a further aspect, an embodiment provides a semiconductor structure on a substrate that includes an FET having a silicided source, a silicided drain and a silicided gate stack; and a gated-diode adjacent to the FET having a silicided anode, a silicided cathode and a non-silicided gate stack, the non-silicided stack having a top surface covered by a layer of a material that inhibits silicide formation. 
         [0014]    In still another aspect, an embodiment provides a method of forming a semiconductor structure that includes forming on a semiconductor substrate an FET having a silicided source, a silicided drain and a silicided gate stack; and forming a gated-diode adjacent to the FET having a silicided anode, a silicided cathode and a non-silicided gate stack, the non-silicided gate stack having a top surface covered by a layer of material that inhibits silicide formation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The accompanying drawings, which are incorporated in and which constitute part of the specification, illustrate the presently preferred embodiments of the invention which, together with the general description given above and the detailed description of the preferred embodiments given below serve to explain the principles of embodiments of the invention, wherein like reference numerals denote like elements and parts, in which: 
           [0016]      FIG. 1  shows a perspective view of a prior art diode and an FET as part of integrated circuit illustrating the damage to the diode degrading the diode ideality. 
           [0017]      FIG. 2  illustrates a perspective view of the SOI substrate of  FIG. 1  following superimposing over a silicon substrate a buried oxide layer (BOX) followed by the SOI layer. 
           [0018]      FIG. 3  depicts a perspective view of the structure illustrated in  FIG. 2  wherein a shallow trench isolation (STI) is formed in the SOI layer isolating the n-well from the p-well, followed by planarization such as CMP. 
           [0019]      FIG. 4  shows ion implantation into different regions to form n-well and p-well regions. 
           [0020]      FIG. 5  shows a perspective view of the formation of the gate stack that includes a gate dielectric, a gate electrode, and a hardmask. 
           [0021]      FIG. 6  shows gate patterning using a photoresist. 
           [0022]      FIG. 7  illustrates the resulting structure after etching the hardmask, transferring the photoresist pattern. 
           [0023]      FIG. 8  is a perspective view of the structure after removing the photoresist, leaving the etched hardmask in the desired pattern. 
           [0024]      FIG. 9  shows the structure after etching the gate electrode and gate dielectric forming gates in the desired pattern. 
           [0025]      FIG. 10  shows the structure after a conformal spacer material is deposited. 
           [0026]      FIG. 11  shows the resulting structure after etching the spacer material, preferably by a directional Reactive Ion Etch (RIE) process that removes the spacer material from the horizontal surfaces while leaving it on the vertical sidewalls. 
           [0027]      FIG. 12  illustrates opening areas by way of the photoresist masking to receive N+ doping by ion implantation , the N+ region serving as source drain regions of an NFET or the N-well contact of the diode. 
           [0028]      FIG. 13  shows a photoresist masking step with open areas which are to receive P+ doping by ion implantation, the P-dopant species preferably including boron. The P+ region serves as the P+ portion of the diode or the source drain region of the PFET (not shown). 
           [0029]      FIG. 14  is a perspective view of the structure following the removal of the photoresist. 
           [0030]      FIG. 15  shows a photoresist covering and protecting the diode while exposing the FET region to an etch that removes the hardmask over the gate of the FET. 
           [0031]      FIG. 16  illustrates the structure following RIE, highlighting resulting damaged regions, wherein the photoresist covers the diode region, leaving the diode protected from the hardmask RIE, thus preserving the diode. 
           [0032]      FIG. 17  shows the structure following the removal of the photoresist. 
           [0033]      FIG. 18  depicts the structure after the formation of the silicide on the exposed N+ or P+ regions including the gate regions not covered by a spacer or by a hardmask, the diode gate remaining unsilicided while the hardmask is kept. 
           [0034]      FIG. 19  shows a planar view of the structure shown in  FIG. 18  including a gated-diode and a FET, in this example an NFET. 
           [0035]      FIG. 20  shows an embodiment with a gated-diode with a non-silicided gate formed with NFETs and PFETs provided with silicided gates. 
           [0036]      FIG. 21  illustrates a planar view of the structure shown in  FIG. 20 , including a gated-diode and a NFET and a PFET. 
           [0037]      FIG. 22  shows a plan view of an embodiment of an alternate diode structure illustrating additional plan-view designs of gated-diode, in an embodiment showing the gated-diode formed within the perimeter of the gate. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    Detailed embodiments of the methods and structures of the present disclosure are described herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the described methods and structures that can be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the disclosure is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features can be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures, as they are oriented in the drawings. 
         [0039]    Referring to  FIG. 2 , an illustrative structure and a method for forming semiconductor FET devices on a semiconductor-on-insulator (SOI) substrate are described. 
         [0040]      FIG. 2  shows a substrate [ 100 ], presently Silicon-on-Insulator (SOI). The SOI layer [ 102 ] is located above the buried-oxide layer (BOX) [ 101 ] and the substrate [ 100 ]. The buried oxide (BOX) layer [ 101 ] on the substrate [ 100 ] can be made as a silicon oxide, a nitride, a silicon nitride, and/or an oxynitride, e.g., silicon oxynitride, having a thickness ranging from 5 nm to 1000 nm, or preferably, from 10 nm to 200 nm, and still more preferably, from 10 nm to 25 nm. 
         [0041]    The semiconductor-on-insulator (SOI) substrate can be employed as the semiconductor substrate. When employed, the SOI substrate includes a handle substrate superimposed by a buried insulator layer located on an upper surface of the handle substrate, and a semiconductor device layer located on an upper surface of the buried insulator layer. The handle substrate and the semiconductor device layer of the SOI substrate can include the same or different semiconductor material. The term “semiconductor” as used herein in connection with the semiconductor material of the handle substrate and the semiconductor device layer denotes any semiconducting material including, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other like III/V compound semiconductors. Multilayers of these semiconductor materials can also be used as the semiconductor material of the handle substrate and a semiconductor device layer [ 102 ]. In one embodiment, the handle substrate [ 100 ] and the semiconductor device layer are both made of Si. 
         [0042]    The handle substrate and the semiconductor device layer can have the same or different crystal orientation. For example, the crystal orientation of the handle substrate and/or the semiconductor device layer can be {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used in the present disclosure. The handle substrate of the SOI substrate can be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. The semiconductor device layer of the SOI substrate is a single crystalline semiconductor material. A single crystalline semiconductor material (or monocrystalline semiconductor material) is a semiconductor material in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries. 
         [0043]    The buried insulator layer of the SOI substrate can be a crystalline or non-crystalline oxide or nitride. In one embodiment, the buried insulator layer is made of oxide. The buried insulator layer  101  can be continuous or it can be discontinuous. When a discontinuous buried insulator region is present, the buried insulator region exists as an isolated island that is surrounded by semiconductor material. 
         [0044]    The SOI substrate can be formed utilizing standard processes including for example, SIMOX (separation by ion implantation of oxygen) or layer transfer. When a layer transfer process is employed, an optional thinning step can follow the bonding of two semiconductor wafers together. The optional thinning step reduces the thickness of the semiconductor layer to a layer having a thickness that is more desirable. 
         [0045]    The thickness of the semiconductor device layer of the SOI substrate is typically from 100 Å to 1000 Å, with a thickness from 500 Å to 700 Å being more typical. In some embodiments, and when an ETSOI (extremely thin semiconductor-on-insulator) substrate is employed, the semiconductor device layer of the SOI has a thickness of less than 100 Å. If the thickness of the semiconductor device layer is not within one of the above mentioned ranges, a thinning step such as, for example, planarization or etching can be used to reduce the thickness of the semiconductor device layer to a value within one of the ranges mentioned above. 
         [0046]    Referring to  FIG. 3 , a shallow trench isolation (STI) [ 103 ] created by a fabrication sequence is shown including trench etching, dielectric deposition such as oxide, followed by planarization such as CMP. The isolation formed by the STI process includes patterning (e.g., deposition a sacrificial pad layer (e.g., pad oxide and pad nitride), patterning (e.g., by lithography) and etching STI trenches, preferably by reactive ion etch (RIE), filling the trenches with one or multiple insulators including but not limited to oxide, nitride, oxynitride, high-k dielectric, or any suitable combination of those materials. The planarization process, such as chemical-mechanical polishing (CMP), can be used to provide a planar structure. Besides STI [ 103 ] other isolation such as mesa isolation, local oxidation of silicon (LOCOS) can also be used. The sacrificial pad oxide and pad nitride can then be stripped. 
         [0047]      FIG. 4  shows ion implantation into different regions to form n-well [ 104 ] and p-well [ 105 ] regions. The n-well ion implantation can be n-type dopant elements including arsenic or phosphorus. The p-well ion implantation preferably uses a p-type dopant material, including boron or indium. 
         [0048]    Referring to  FIG. 5 , forming a gate stack is illustrated including a gate dielectric [ 106 ], a gate electrode [ 107 ], and a hardmask [ 108 ]. The gate dielectric [ 106 ] can be selected from silicon oxide, silicon oxynitride, nitride, high-K materials such as hafnium oxide or stacked combinations thereof. Gate electrode [ 107 ] is a conductor or semiconductor, e.g., polysilicon or metal, e.g., TiN, or stacked combinations thereof. The polysilicon layer can be doped by way of ion implantation or in-situ doped during the deposition. The hardmask [ 108 ] is typically a dielectric, e.g., silicon oxide, silicon nitride or a stacked combination thereof. 
         [0049]    Referring to  FIG. 6 , gate patterning is shown preferably using photoresist, a mask exposure using optical source, and photoresist development leaving the photoresist in desired areas [ 109 ]. 
         [0050]      FIG. 7  shows the resulting structure after etching the hardmask, preferably using a RIE process, and transferring the photoresist pattern into the hardmask. 
         [0051]    Referring to  FIG. 8 , the structure is shown following the removal of the photoresist by way of a stripping process, leaving the etched hardmask in the desired pattern. 
         [0052]      FIG. 9  shows the structure after etching the gate electrode [ 107 ] and gate dielectric [ 106 ], preferably using a directional RIE, forming gates in the desired pattern. 
         [0053]      FIG. 10  shows the structure following the deposition of a conformal spacer layer [ 110 ]. The spacer material is preferably a dielectric such as silicon nitride or silicon oxide that can be deposited by way of Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or Molecular Layer Deposition (MLD). 
         [0054]      FIG. 11  illustrates the resulting structure after etching the spacer material, preferably using a directional Reactive Ion Etch (RIE) tot remove the spacer material from the horizontal surfaces but keeping it on the vertical sidewalls. 
         [0055]      FIG. 12  shows a photoresist masking [ 111 ] that opens areas that are to receive N+ doping by ion implantation [ 112 ]. N-dopant materials preferably include arsenic or phosphorus. The N+ region serves as the source drain region of an NFET or as the N-well contact of the diode. Alternatively, the N+ region could be formed by etching a trench and filling it with epitaxially deposited semiconductor, such as N-doped SiC. 
         [0056]      FIG. 13  shows a photoresist masking step [ 113 ] that opens areas set to receive P+ doping by ion implantation [ 114 ]. P-dopant materials may include boron. The P+ region serves as the P+ portion of the diode or the source drain region of the PFET (not shown). The photoresist is then removed, resulting in the structure shown in  FIG. 14 . Alternatively, the P+ region can be formed by etching a trench and filling it with epitaxially deposited semiconductor, such as P-doped SiGe. 
         [0057]      FIG. 15  illustrates the photoresist step which covers and protects the diode, while exposing the FET region to etching that removes the hardmask [ 108 ] over the FET gate. The hardmask etch is preferably performed by RIE etching. The RIE etching can result in damaging the exposed regions as will be illustrated with reference to  FIG. 16 . 
         [0058]    Referring to  FIG. 16 , the structure is shown following RIE etching, illustrating the resulting damaged regions [ 116 ]. Because the photoresist [ 115 ] covers the diode region, it protects the diode from hardmask RIE damage, and preserves not only the diode, but it also avoids degradation of the diode ideality. 
         [0059]      FIG. 17  shows the structure following the removal of the photoresist. 
         [0060]      FIG. 18  shows a cross-section view of the structure after silicide [ 117 ] formation. The silicide can be selected from nickel silicide, titanium silicide, cobalt silicide, or any other silicide material. The nickel, titanium, cobalt or other similar metal is deposited on the entire structure. During at heating of the wafer, preferably by Rapid Thermal Annealing (RTA), the silicide forms as a reaction between the metal and the silicon on the exposed N+ or P+ regions including gate regions not covered by spacer [ 110 ] or the hardmask [ 108 ]. The FET gate is silicided leaving the diode gate unsilicided as a result of the hardmask still remaining in place. The unreacted metal on the spacer or the hardmask is etched away, preferably by aqueous chemistry. 
         [0061]    Still referring to  FIG. 18 , in one embodiment, the gated-diode shown is devoid of any damage resulting from the absence of siliciding the gate, and is further formed alongside the FET having a silicided gate that allows it to achieve a high-performance caused by the reduced gate resistance. 
         [0062]      FIG. 19  shows an embodiment wherein the gated-diode with its non-silicided gate is formed alongside the NFET and PFET having a silicided gate. It should be noted that while the gated-diode is shown as a P+/N diode, an embodiment of the inventive structure could be equally applicable to a N+/P diode. 
         [0063]      FIG. 20  shows a plan view of the structure illustrated in  FIG. 18  depicting additional details of the structure. The non-silicided gate [ 123 ] of the gated-diode is shown in the region on top of the active region of the device, leaving the cap layer in place within the active region, thereby avoiding RIE damage to the active region of the diode. The gate [ 121 ] of the gated-diode is silicided outside the active region to the diode, over the STI, by removing the cap layer in the stated region that allows silicide to form. The silicide within the region enables a good contact between the contact [ 120 ] and the gate [ 121 ] of the gated-diode. Removing the cap layer in the region outside of the active area of the gated-diode does not create damage near the active region of the diode. Shown in  FIG. 20 , the gate of the FET is silicided [ 122 ]. 
         [0064]      FIG. 21  shows a plan view of the structure from  FIG. 19 , illustrating an embodiment of the gated-diode with a non-silicided gate [ 124 ] and NFET [ 125 ] and PFET [ 126 ] with a silicided gate. The gate of the gated-diode is not silicided [ 124 ] in the region above the active region of the device, and leaving the cap layer in place within this region, making it possible to avoid RIE damage in the active region of the diode. The gate of the gated-diode is silicided outside the diode active region [ 122 ], over the STI, by removing the cap layer in this region, thus enabling silicide to be formed. The silicide in this region provides good contact between the contact [ 120 ] and the gate of the gated-diode. Removing the cap layer in the region outside of the active area of the gated-diode does not create damage near the active region of the diode. The gate of the FETs [ 125 ,  126 ] is silicided. 
         [0065]      FIG. 22  shows a plan view of an embodiment of an alternate diode structure illustrating other plan-view designs of the gated-diode (NFET and PFET not shown). In an embodiment, the diode is formed within the perimeter of the gate. As previously described, the gate of the gated-diode is not silicided [ 128 ] in the region located above the active region of the device by leaving the cap layer in place in this region, to avoid RIE damage within the active region of the diode. The gate of the gated-diode is silicided [ 127 ] in an area beyond the diode active region and spanning over the STI, and removing the cap layer from the region, thereby permitting the formation of silicide. 
         [0066]    While the present disclosure has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details can be made without departing from the spirit and scope of the present disclosure. In one therefore intended that the present disclosure not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.