Abstract:
A charge pump comprises a charge-up circuit connected to a voltage source, and a clock generator. A pull-up circuit is formed by an enhancement mode MOSFET and a time constant circuit. The MOSFET has its drain coupled to the charge-up circuit and its source connected to the output terminal of the charge pump. The clock generator produces first and second clock pulse sequences, with the duration of the first clock pulse sequence being greater than the pulse duration of the second clock pulse sequence. The time constant circuit has two capacitors and a resistor connected therebetween to respond to the first and second clock pulse sequences by successively applying voltages to the drain and gate of the MOSFET. The charge-up circuit is formed by a depletion mode or an enhancement mode MOSFET which is responsive to one or more clock pulse sequences with pulses preceding those of the first and second clock sequences.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to semiconductor circuits, and more specifically to a charge pump which is used in integrated circuits. 
     As shown in FIG. 1, a prior art charge pump comprises a charge-up circuit 1 and a pull-up circuit 2. Charge-up circuit 1 is formed by an N-channel enhancement mode MOSFET (field effect transistor) 1 whose drain and gate are coupled to a voltage supply 4 at voltage V CC  and whose source is coupled to the drain and gate of an N-channel enhancement mode MOSFET 5 of charge-up circuit 2 and hence to a clock source φ through a capacitor 6. The source of MOSFET 5 is coupled to an output terminal 7 which is in turn connected to a suitable utilization circuit. When clock sequence Φ switches to low level, the drain of MOSFET 5 is driven by MOSFET 3 and its potential increases as indicated by a dotted line in FIG. 2 to a level V CC  -V Te  (where V Te  is the threshold of MOSFET 3). On reaching this level, MOSFET 3 is turned off. When clock sequence goes high, the voltage at the drain of MOSFET 5 rises sharply to a level V CC  -V Te  +V.sub.φ is the voltage of the clock sequence) by the action of capacitor 6. This voltage is applied through MOSFET 5 to output terminal 7, producing an output voltage (V cc  -V Te )+(V.sub.φ -V Te ) which is indicated by a solid line curve in FIG. 2. To obtain a higher output voltage, pull-up circuits 2-1, 2-2 and 2-3 are cascaded as shown in FIG. 3 such that the second stage is supplied with clock sequence of opposite phase to those of clock sequences supplied to the odd-numbered stages. The voltage at the drain of MOSFET 5-2 is driven to a level equal to (V CC  -V Te )+(Vφ-V Te ) when the opposite phase clock is at low level. When the opposite-phase clock goes high, the drain of MOSFET 5-2 is driven to a level equal to (V CC  -V Te )+(Vφ-V Te )+V.sub.φ which is applied through MOSFET 5-2 to the drain of MOSFET 5-3, which, as a result, rises to a level (V CC  -V Te )+(Vφ-V Te )+(Vφ-V Te ). The output voltage of this multi-stage circuit is equal to (V cc  -V Te )+N(V.sub.φ -V Te ), where N represents the number of cascaded pull-up circuits 2. Usually V.sub.φ is set equal to V CC , and the output voltage is 2 V CC  -2 V Te . Since the threshold voltage V Te  is of a substantial value in comparison with V CC , the output voltage is too low for some applications. If source voltage V CC  is equal to or lower than the threshold voltage V Te , the charge-up circuit becomes inoperative, and if V.sub.φ ≦V Te  the pull-up circuit becomes inoperative. In either case, the charge pump is inoperative. In addition, a large number of pull-up circuits would be required. For example, if V CC  =V.sub.φ =1.5 volts, V Te  =1.0 volt, twenty-nine pull-up circuits are required to obtain an output voltage of 15 volts. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a charge pump capable of generating a high output voltage. 
     According to the present invention, there is provided a charge pump which comprises a charge-up circuit connected to a voltage source, a pull-up circuit connected to the charge-up circuit, and a clock generator. The pull-up circuit is formed by an enhancement mode field-effect transistor and a time constant circuit. The clock generator generates first and second clock pulse sequences respectively at first and second output terminals thereof. The field-effect transistor has a drain-source path coupled between the charge-up circuit and the output terminal of the charge pump. The time constant circuit is formed by two capacitors and a resistive element connected therebetween, the time constant circuit being connected across the first and second output terminals of the clock generator for successively applying voltages to one end of the drain-source path and gate of the field-effect transistor in response to the first and second clock pulse sequences. 
     Preferably, the first clock pulse sequence has a pulse duration greater than the pulse duration of the second clock pulse sequence. 
     In one preferred embodiment, the charge-up circuit comprises a depletion mode field-effect transistor having its drain coupled to the voltage source, and its source connected to the drain of the enhancement mode field-effect transistor of the pull-up circuit. The gate of this depletion mode field-effect transistor is responsive to a clock pulse which occurs prior to the first clock pulse sequence. In a second preferred form of this invention, the charge-up circuit comprises an enhancement mode field-effect transistor and a time constant circuit associated with this field-effect transistor. This enhancement mode field-effect transistor has its drain-source path connected between the voltage source and one end of the drain-source path of the field-effect transistor of the pull-up circuit. The clock generator additionally generates two clock pulse sequences with successive pulses preceding the clock sequences supplied to the pull-up circuit. The time constant circuit of the charge-up circuit is responsive to the additional clock pulse sequences to successively apply voltages to the gate of the associated enhancement mode field-effect transistor. 
     The present invention further provides a multi-stage charge pump which includes a charge-up circuit connected to a voltage source, a clock generator for generating first, second, third and fourth clock pulse sequences for pull-up operation. A first pull-up circuit comprises a first enhancement mode field-effect transistor having its drain coupled to the charge-up circuit, a first time constant circuit responds to the first and second clock sequences by successively applying voltages to one end of the drain-source path and gate of the first field-effect transistor. A second pull-up circuit comprises a second enhancement mode field-effect transistor having one end its drain-source path connected to the other end of the drain-source path of the first enhancement mode field-effect transistor, the other end of its drain-source path being coupled to an output terminal of the charge pump. A second time constant circuit responds to the third and fourth clock pulse sequences by successively applying voltages to one end of the drain-source path and gate of the second enhancement mode field-effect transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described in further detail with reference to the accompanying drawings, in which: 
     FIG. 1 is a circuit diagram of a prior art charge pump; 
     FIG. 2 is a waveform diagram associated with the prior art charge pump; 
     FIG. 3 is a circuit diagram of a prior art multi-stage charge pump; 
     FIG. 4 is a circuit diagram of a charge pump according to an embodiment of the present invention; 
     FIG. 5 is a waveform diagram associated with the embodiment of this invention; 
     FIG. 6 is a circuit diagram of a multi-stage charge pump of this invention; 
     FIG. 7 is a circuit diagram of a modification of this invention; and 
     FIG. 8 is a circuit diagram of a further modification of this invention. 
    
    
     DETAILED DESCRIPTION 
     Referring now to FIG. 4, there is shown a charge pump according to an embodiment of the present invention. The charge pump shown at 10 comprises a charge-up circuit 11 and a pull-up circuit 12. Charge-up circuit 11 comprises an N-channel enhancement mode MOSFET 13 having a gate G 1  coupled through a resistor 14 to a clock source 20 to receive a first clock pulse sequence φ 1  and through a capacitor 15 to receive a second clock sequence φ 2 . MOSFET 13 has its drain D 1  connected to a voltage supply 21 to receive source voltage V CC  and its source S 1  coupled to the drain D 2  of an N-channel enhancement mode MOSFET 16 of charge-up circuit 12. MOSFET 16 has its gate G 2  and drain D 2  coupled together by a resistor 17, with the drain D 2  being further coupled through a capacitor 18 to clock source 20 to receive a third clock sequence φ 3  and the gate G 2  being further coupled through a capacitor 19 to the clock source to receive a fourth clock sequence φ 4 . 
     Resistor 14 and capacitor 15 form a series circuit across terminals φ 1  and φ 2  of clock source 20 with a time constant value R 1  -C 1  (where R 1  and C 1  are the resistance and capacitance values of resistor 14 and capacitor 15, respectively). Likewise, resistor 17 and capacitor 19 present a series circuit between drain D 2  of MOSFET 16 and clock terminal φ 4  with a time constant value C 2  -R 2  (where C 2  is the capacitance of capacitor 19 and R 2  is the resistance of resistor 17). The source S 2  of MOSFET 16 is coupled to the output terminal 22 of the charge pump 10 to which a utilization circuit is connected. 
     The first to fourth clock sequences have the waveforms as shown in FIG. 5. The first and third clock sequences φ 1  and φ 3  are of opposite polarity of the same clock period which is twice the period of clock sequences φ 2  and φ 4  so that these clock sequences produce a unique combination of four different voltage levels respectively for periods T 1 , T 2 , T 3  and T 4 . Specifically, during period T 1 , clock sequence φ 1  is at high voltage V.sub.φ and all other clock sequences are at zero voltage. During period T 2 , clock sequences φ 1  and φ 2  are at voltage V.sub.φ and other sequences are at zero voltage. During period T 3 , only clock sequence φ 3  is at high level, and during the last period T 4 , φ 3  and φ 4  are at high level. Note that the time constant value C 1  -R 1  is much smaller than period T 1  or T 2  and the time constant value C 2  -R 2  is much smaller than period T 3  or T 4 . 
     Assume that the voltage V.sub.φ is equal to source voltage V CC . During period T 1 , a voltage difference V.sub.φ develops across terminals φ 1  and φ 2  and capacitor 15 is charged through resistor 14, generating a potential which rises exponentially at the gate G 1  of MOSFET 13, following a curve V.sub.φ =1 -e-t  /C 1  -R 1  as indicated by a dotted line 30 in FIG. 5. Since T 1  is much greater than time constant C 1  -R 1 , the voltage at gate G 1  will eventually reach V.sub.φ (=V CC ) within period T 1 . During period T 2 , clock terminal φ 2  is driven to the same potential as at terminal φ 1 . This voltage adds up to the voltage developed across capacitor 15, presenting a voltage 2 V.sub.φ to gate G 1 . This voltage decays exponentially following a curve V.sub.φ =1-e -t  /R 1  C 1  to the V.sub.φ level within period T 2  as illustrated. At the instant the voltage at gate G 1  rises to the level 2 V CC , the voltage at the drain D 2  of MOSFET 16 is driven to V CC  as shown at 31a if V CC  is equal to or lower than 2 V.sub.φ -V Te  (where V Te  is the threshold voltage of enhancement mode MOSFET 13), or driven to 2 V.sub.φ -V Te  if V CC  is higher than 2 V.sub.φ -V Te . 
     During period T 3  in which the third clock sequence φ 3  is the only one that is driven to high level, the voltage V.sub.φ of this clock sequence is supplied through capacitor 18 to the drain D 2  of MOSFET 16, so that the voltage at drain D 2  sharply rises to a level 2 V.sub.φ (=2 V CC ) as shown at 31b in FIG. 5, and capacitor 19 is charged through resistor 17. Since the time constant C 2  -R 2  is smaller than T 3 , the voltage at the gate G 2  of MOSFET 16 rises exponentially as shown at 32a to the same level as at the drain D 2  of MOSFET 16 within period T 3 . 
     During the successive periods T 1  through T 3 , the voltage at the output terminal 22 increases exponentially in a stepwise manner. Specifically, it exponentially increases to a level V.sub.φ -2 V Te  during T 1 , rises to a level V CC  -V Te  during T 2 , and jumps to a level V CC  +V.sub.φ -V Te  during T 3 . 
     During the next period T 4  in which the third and fourth clock sequences are at high level, the voltage at the gate G 2  of MOSFET 16 rapidly rises as shown at 32b to a level which is three times as high as the source voltage V CC . This voltage level is equal to the potential at the drain G 2  plus 2 V.sub.φ. Since the time constant C 2  -R 2  is much smaller than period T 4 , the voltage at gate G 2  decays exponentially to the same voltage level as at the drain D 2  during period T 4 . During period T 4 , the voltage at the output terminal 22 further increases to the level 2 V CC . 
     When the potential at gate G 2  increased to 3 V CC , the voltage V OUT  at the output terminal 22 increases from the level (V CC  +V.sub.φ -V Te ) to 2 V CC  (=voltage at drain D 2  +V.sub.φ) if V.sub.φ is equal to or higher than V Te , or increases to a level equal to the voltage at drain D 2  +2 V.sub.φ -V Te  if V.sub.φ is lower than V Te . 
     It is seen that the voltage obtained by the use of a single pull-up circuit of this invention is equal to V.sub.φ if V.sub.φ ≧V Te  or 2 V.sub.φ -V Te  if V.sub.φ &lt;V Te . 
     It is seen from the foregoing that as long as a relation V.sub.φ &gt;V Te  /2  holds both charge-up and pull-up circuits operate satisfactorily. Since the voltage V.sub.φ of the clock sequences for MOS integrated circuitry is usually equal to the source voltage V CC , the charge pump of this invention can operate satisfactorily even when the source voltage is at very low level. For example, if V Te  is 1.0 volt, the charge pump will operate at a source voltage of 0.5 volts. 
     A higher output voltage can be obtained by cascading pull-up circuits 12-1, 12-2 and 12-3 as shown in FIG. 6 such that the phases of clock sequences supplied to the even-numbered stage 12-2 are opposite to the phases of clock sequences supplied to the odd-numbered pull-up circuits 12-1, 12-3. Since the voltage at the drain D 2  of each pull-up circuit is either V.sub.φ or 2 V.sub.φ -V Te , the output voltage V OUT  is equal to the voltage at drain D 2  plus NV.sub.φ if V.sub.φ is equal to or higher than V Te , or equal to the voltage at drain D 2  plus N(2 V.sub.φ -V Te ) if V.sub.φ is lower than V Te  (where N is the number of cascaded pull-up circuits). 
     Therefore, the number of pull-up circuits necesary for a given application can be reduced in comparison with the prior art charge pump. For example, if V CC  =V.sub.φ =1.5 volts and V Te  =1.0 volt, nine pull-up circuits will be sufficient to obtain an output voltage of 15 volts. 
     To reduce the amount of space for implementing the charge pump, resistors 14 and 17 are preferably replaced with N-channel depletion mode MOSFETs 40 and 41, respectively, as shown in FIG. 7. Each of these MOSFETs has its gate and drain electrodes coupled together to form an equivalent resistance element. Alternatively, the gate and source electrodes may be coupled together to form a resistor. 
     A modified embodiment of this invention is shown in FIG. 8 which differs from the embodiment of FIG. 4 in that the charge-up circuit of FIG. 1 is replaced with an N-channel depletion mode MOSFET 43 having a threshold voltage -V Td . The gate of MOSFET 43 is coupled to the first clock terminal φ 1  with its drain D and source S being coupled respectively to terminal 21 and drain D 2  of MOSFET 16. When the first clock sequence φ 1  is at high voltage level, the voltage at drain D 2  of MOSFET 16 is equal to V CC  if V CC  is equal to or smaller than V.sub.φ +V Td , or V.sub.φ +V Td  if V CC  is higher than V.sub.φ +V Td . 
     If V CC  &gt;V.sub.φ +V Td , source voltage V CC  must also be higher than the absolute value of the threshold V Td  to ensure that MOSFET 43 turns off when the first clock sequence φ 1  is at low voltage. 
     The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.