Abstract:
For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of U.S. provisional patent application Ser. No. 60/691,529, filed Jun. 17, 2005 for a “Linear and High-Speed Signal Chain for Readout Integrated Circuits and CMOS Imagers” by Bedabrata Pain, Bruce Hancock, and Thomas J. Cunningham, the disclosure of which is incorporated herein by reference for all purposes permitted by law and regulation. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Subject matter disclosed in this specification was supported at least in part through the performance of work under a NASA contract, and is subject to the provisions of Public Law 96-517 (35 U.S.C. § 202) in which the Contractor has elected to retain title. 
     
    
     FIELD  
       [0003]     The present disclosure relates to image sensors. In particular, it relates to the architecture of circuits for readout integrated circuits and CMOS imagers and more particularly to analog bus drivers and multiplexers.  
       BACKGROUND  
       [0004]     The schematic block diagram of an image sensor  1  is shown in  FIG. 1 . The image sensor  1  may be an integrated visible CMOS imager or a readout integrated circuit (ROIC) for infrared (IR) or ultraviolet (UV) detectors. The particular image sensor  1  shown in  FIG. 1  is an integrated visible CMOS imager that comprises a two-dimensional (2-D) pixel array  10 , one-dimensional array of column sample and hold circuits  20 , and analog horizontal bus driver and multiplexer circuits  30 . The row decoder and logic circuit arrays  40  and the column decoder and logic circuit arrays  50  access the pixels  12  in the pixel array  10  for reading. If the image sensor  1  is an ROIC, a two-dimensional pixel readout/multiplexer takes the place of a 2-D pixel array, because the sensing elements are usually on a separate chip from the electronics described here, but the rest of the circuits remain the same. The current disclosure relates primarily to the analog horizontal bus driver and multiplexer.  
         [0005]      FIG. 2  shows the schematic for the CMOS imager/ROIC architecture with a source-follower per detector architecture. Individual pixels  12  of the 2-D pixel array consists of a photodiode  15  implemented with a reverse-biased p-n junction that is integrated on the same chip for a CMOS imager or hybridized to the ROIC; and a source follower is comprised of transistors M in    14  (SF input FET), M sel    16  (select FET), and M rst    18  (reset FET).  
         [0006]     The image sensor  1  operates in a column-parallel fashion (i.e., a row at a time). To begin exposure, the pixels  12  in a given row are reset by momentarily pulsing the line RST  11  high. Following exposure, the pixels  12  are readout in a row-at-a-time fashion. For readout, a row is selected by momentarily pulsing the line SEL  13  high. The source follower output from each pixel belonging to the row is available over the column buses  17 . The column-parallel outputs are sampled by an array of bottom-of-column capacitors (C S )  21  by pulsing the line SHS  23  high. The pixels  12  are then reset by momentarily pulsing the line RST  11  high, and the resultant outputs are again sampled on another array of bottom-of-the-column capacitors (C R )  25  by by pulsing the line SHR  27  high. The difference of the sampled voltages in each column  17  is the signal from each pixel  12 , and is proportional to the charge accumulation on each photodiode  15 .  
         [0007]     The sampled voltages in each column  17  (on the capacitors  21  (C S ) and  25  (C R )) are scanned out by using an analog horizontal bus driver/multiplexer circuit.  FIG. 3  shows a schematic of two analog bus driver/multiplexer circuits  31  and  33 . The capacitors  21  (C s ) and  25  (C R ) in each column  17  are buffered by the analog horizontal bus driver circuits  31  and  33 . The output of the analog horizontal bus driver circuits  31  and  33  in each column  17  drives the capacitance of the horizontal buses  35  and  37  which feed, respectively, output buffer amplifiers  38  and  39 . The analog bus driver circuits  31  occur in pairs in order to differentially readout sampled voltages from bottom-of-column capacitors  21  (C S ) and  25  (C R ) in each column  17 .  
         [0008]     For a large format array, the analog horizontal bus driver and multiplexer circuit  30  drives a large capacitance, and needs to have excellent linearity, large signal swing, high speed of operation, and near-ideal gain.  
         [0009]     Accordingly, the two-dimensional pixel array is readout as follows in a typical CMOS imager or a focal-plane readout integrated circuit (IC)  1 . First, the outputs of a row of pixels  12  are sampled in parallel at the bottom of the column  17 . The sampled values are then scanned out using electronic amplifiers  38  and  39 . The speed of column scanning determines the readout rate.  FIGS. 4 and 5  show the two most common column amplifier schemes for reading out the pixel values.  
         [0000]     Source-Follower Signal Chain  
         [0010]      FIG. 4  shows the schematic diagram of a conventional column source-follower signal chain. See R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E. R. Fossum, “256×256 CMOS active pixel sensor camera-on-a-chip,”  IEEE Journal of Solid - State Circuits , vol. 31, pp. 2046-2050, December 1996, the disclosure of which is incorporated by reference herein for all purposes allowed by law and regulation.  
         [0011]     As shown in  FIG. 4 , the pixel values sampled at the bottom of the column  17  are stored on column capacitors  111  (C s ). The reference capacitors (C R ), their associated FETs, and a horizontal bus are omitted for the sake of simplifying the diagram and discussion. The sampled values are then scanned using a switched source-follower circuit  100  consisting of M sf  as the input FET  105 , M sel , as the selection switch FET  110  controlled by a column-decoded digital signal, and M ld  as the load FET  115 . While M sf  and M sel  are present in each column cell buffering the sample-and-hold capacitor  21  (C s ), there is only one load FET  115  (M ld ), since only one column is activated at a time during the scanning in order to provide a signal to the horizontal bus  112 .  
         [0012]     The same structure is duplicated in order to readout the signal in a differential fashion using the sample and hold capacitors  25  (C R ) (not shown in  FIG. 4  but shown in  FIGS. 2 and 3 ). In that case, the bottom-of-the-column sample-and-hold capacitors  25  and  21  (C R  and C S ) consist of a pixel reference level (V R ) and a signal level (V S ) corresponding to pixel potentials before and after photo-generated charges have been accumulated.  
         [0013]     The output of a particular column n V out (n) depends on the voltage drops across the FETs  105  (M sf ) and  110  (M sel ). In turn, they depend on the bias current I bias , and the width and length ratio (W/L) of the respective FETs. For a given bias current, I bias , the output voltage for column of index n is given by:  
                       V   out     ⁡     (   n   )       ≡     V   out       =       V   Cs     +     V   to     +         2   ⁢           ⁢     I   bias         β   sf         +     Δ   ⁢           ⁢       V   drop     ⁡     (     V   Cs     )             ;     ⁢     
     ⁢       β   sf     =     μ   ·     C   ox     ·       [     W   L     ]     sf                 [   1   ]             
 
 where the index is dropped for simplicity, V Cs  is the sampled voltage on the capacitor C s , V to  is the threshold voltage of M sf , W/L is the transistor width to length ratio, ΔV drop  is the voltage drop across the drain and source of the switch FET M sel , β sf  is the transconductance factor for M sf , μ is the mobility of carriers in the channel, and C ox  is the oxide capacitance per unit area. Since I bias  flows through the select FET  110  (M sel ) as well, (assuming that FET  110  (M sel ) is biased in the linear region of FET operation), ΔV drop  can be computed from:  
               I   bias     =       β   sel     ·     [         (       V   out     -     V   tsel       )     ·     (       V   out     -     V   s       )       -       1   2     ·       (       V   out     -     V   s       )     2         ]               [   2   ]             
 
 where V s  is the voltage at the source of FET  105  (M sf ) and is given by:  
               V   s     =       V   Cs     +     V   to     +           2   ⁢           ⁢     I   bias         β   sf         ⁢     V   out       -     Δ   ⁢           ⁢       V   drop     ⁡     (     V   Cs     )                   [   3   ]             
 
         [0014]     Assuming that the effective threshold voltage V tsel  changes linearly with V SB  the source-to-body voltage (as shown in Equation 4—clearly an approximation introduced to simplify analysis), Equation 2 can be solved to yield (with γ being the FET body coefficient):  
                 V   out     =       1     1   -   γ       ·     [       V   to     -       γ   ⁢           ⁢     V   s       2     +         V   to   2     +         (     1   -     γ   2       )     2     ⁢     V   s   2       -       (     γ   +   2     )     ·     V   s     ·     V   to       +       2   ·     (     1   -   γ     )     ·     I   bias         β   sel             ]         ⁢     
     ⁢       V   tsel     =       V   to     +       γ   ⁢           ⁢     V   SB       2                 [   4   ]             
 
         [0015]     The response time is determined by the time required to charge the horizontal bus parasitic (C B ) and load capacitance (C L ), and depends on the bias current (I bias ) and the transconductance of the FET  105  (M sf ) and the channel resistance of the select FET  110  (M sel ). By adding the slewing and the settling time together (assuming single pole response), the dependence I bias  on the column readout time (Δt read ) is given by:  
                 I   bias     =       I   R     +         I   S     2     ⁡     [     1   +       1   +     4   ⁢           ⁢       I   R       I   S               ]           ⁢     
     ⁢         I   R     =           (       C   L     +     C   B       )     ·   Δ     ⁢           ⁢   V         ζ   ·   Δ     ⁢           ⁢     t   read           ;           ⁢       I   S     =           (       C   L     +     C   B       )     2     ·   χ       2   ⁢           ⁢       β   eff     ·   Δ     ⁢           ⁢     t   read   2           ;     ⁢     
     ⁢           ⁢       C   B     =       N   col     ·     (         W   sel     ·     C   edge       +     C   par       )         ⁢     
     ⁢       β   eff     =         β   sel     ⁡     (       β   sf         β   sf     +     β   sel         )       2               [   5   ]             
 
 where C L  is the fixed load capacitance, and C B  is the bus capacitance, with C edge  being the parasitic capacitance along the edge of of the select FET  110  (M sel ), and C par  is the parasitic capacitance independent of the select FET  110  (M sel ), N col  is the number of columns, ξ is the ratio of current between the output transient current and the bias current, W sel  is the width of the select capacitor  110  (M sel ), and χ is the setting factor, that is, the ratio of the settling time to the time constant (˜7 for 0.1% accuracy). 
 
         [0016]     As shown in Equations 4 and 5, both output voltage and readout time are strong functions of the bias current, as well as the size of the column FETs  105  and  110  (M sf  and M sel ). Equation 4 also shows that the transfer function is extremely non-linear, the non-linearity resulting from the ohmic voltage drop across the FET switch  110  (M sel ). This voltage drops also causes a drastic reduction in the signal swing. Finally, except in a handful of situations, for a given operating speed, an increase in the W/L ratio of the switch FET  110  (M sel ) produces undesirable results: increase in both the required bias current and non-linearity, and reduction in the output voltage swing.  
         [0000]     OPAMP Signal Chain  
         [0017]      FIG. 5  shows a representative schematic of an opamp signal chain  120 . The sample-and-hold capacitors  121  and  125  (C s  and C R ) are connected to the horizontal buses  135  and  137  through selection switches  128  (M sel ). Unlike the source-follower signal chain described above, the horizontal buses  135  and  137  are held at a virtual ground via opamp feedback from the operational amplifier  131 , and no dc current flows through the selection switches  128 . Once a particular set of column capacitors are selected, the charge in the capacitor is transferred to the corresponding feedback capacitor  136  (C f ) through the feedback action, producing an output:  
               V   out     =         V   out   +     -     V   out   -       =         C   s       C   f       ·       C   x       C   g       ·     [       V   R     -     V   S       ]                 [   6   ]               
 where V out   +(−)  are the outputs from the two sides of the differential signal chain, and V R  and V S  are the sampled pixel outputs corresponding to the reset level and the signal level respectively as discussed above in connection with  FIG. 2 . A big advantage of the opamp signal chain is its ability to provide accurate voltage gain, as shown in Equation 6, the voltage gain being defined as two capacitor ratios that are easy to implement using standard Very Large Scale Integration (VLSI) layout techniques. 
 
         [0018]     Since no dc current flows through the horizontal buses  135  and  137 , the resistive drop issues are no longer of concern. However, the bus capacitance (C B ) significantly impacts the setting time through the Miller effect, causing a drastic increase in the opamp bias current with an increase C B . The Miller effect refers to the multiplication of the capacitance between input and output of an amplifier by a factor of (1−A v ), in which A v  is the open-loop voltage gain of the operational amplifier. The capacitance will charge and discharge with a current multiplied by (1−A v ).  
         [0019]     Assuming that a single stage design is employed to implement the opamp, the dependence of the required bias current (I bias ) to the column readout time (Δt read ) is given by:  
                 I   bias     =     2   ·     {       I   R     +         I   S     2     ⁡     [     1   +       1   +     4   ⁢           ⁢       I   R       I   S               ]         }         ⁢     
     ⁢         I   R     =           (       C   L     +     C   B       )     ·   Δ     ⁢           ⁢   V         ζ   ·   Δ     ⁢           ⁢     t   read           ;           ⁢       I   S     =         C   x   2     ·   χ       2   ⁢           ⁢       β   op     ·   Δ     ⁢           ⁢     t   read   2           ;     ⁢     
     ⁢       C   B     =       N   col     ·     (         W   sel     ·     C   edge       +     C   par       )         ⁢     
     ⁢         β   op     =     μ   ⁢           ⁢         C   ox     ⁡     (     W   L     )       op         ;     ⁢           ⁢     
     ⁢       C   x     =         [       C   L     +         C   f     ·     (       C   B     +     C   s       )           C   f     +     C   B     +     C   s           ]     ·     [         C   f     +     C   B     +     C   s         C   f       ]       =       C   y     ·         C   f     +     C   B     +     C   s         C   f                     [   7   ]             
 
         [0020]     It can be seen from the above equation that the opamp signal chain does not suffer from any ohmic drop problems, but the bias current required for a given readout time increases rapidly with C B  (the horizontal bus parasitic capacitance) due to the Miller effect (captured in the expression for C x ). Note that a two-stage design will have qualitatively similar response.  
         [0000]     Design Problems  
         [0021]     Both signal chain implementations face serious design problems: the opamp chain suffering from the Miller effect from the horizontal bus capacitance, and the source-follower from M sel  sizing issues.  
         [0022]     For the source-follower signal chain described in connection with  FIG. 4 , the problem is as follows.  FIG. 6  shows that the transfer function of the column source-follower driving the horizontal bus has marked non-linearity. Reduction of non-linearity requires operation with reduced bias current and increased W/L ratio of the selection switch FET  110  (M sel ). However, even for W/L as large as 40/1, the transfer function continues to exhibit non-linearity at low input voltage levels.  
         [0023]     Increasing the M sel  size (thus increasing the W/L ratio) results in a number of undesirable effects. Increasing the width of M sel  increases the bus capacitance, because of the increase in the source capacitance of M sel  connected to the horizontal bus. For a fixed bias current, the readout rate and hence the frame rate falls rapidly, the rapid fall resulting from the fact that settling time is inversely proportional to the trans-conductance (g m ) of a FET (M sf  in this case), and the transcondutance is proportional to the square root of the product of I bias  and W/L ratio, as shown in Equation 8.  
               g   m     ∝         I   bias     ·     W   L                 [   8   ]             
 
         [0024]      FIG. 7  shows the simulated results of the effect of W/L ratio of M sel  on the frame rate and the output voltage swing of the source-follower. It shows that for small M sel  widths (W sel  in μm), the frame rate is high—reaching a maximum around W sel ˜2 μm. As W sel  is increased, the frame rate falls rapidly, due to (as explained above) an increase in the horizontal bus capacitance. On the other hand, the output voltage swing (and resultant non-linearity) shows an exactly opposite behavior: voltage swing is unacceptably small for small W sel .  
         [0025]      FIG. 8  demonstrates this contradictory behavior even more clearly—both voltage swing and gain reducing rapidly as the frame-rate is increased. The presence of the inverse relationship between frame rate and voltage swing (and gain) makes it very difficult to find a suitable operating point for this kind of source-follower circuit, especially as the number of imager pixels is increased.  
         [0026]     Therefore, for a conventional source-follower driving the horizontal bus, the voltage drop across M sel  precludes high speed operation with sufficient voltage swing and linearity.  
         [0027]     Although ohmic drops are not problems for the opamp signal chain, its main problem is a rapid reduction in frame rate for a fixed bias current, as W sel  size is increased. Since no dc current flows through M sel  (shown as switches  128  in  FIG. 2 ), the output voltage swing and the transfer gain remains unaffected by M sel  size. Therefore, the opamp signal chain can be designed with small W sel  to minimize the bus capacitance, and increase frame rate, without affecting the output voltage swing or transfer gain.  
         [0028]     However, an opamp signal chain has its limitations as well. First, the opamp signal chain suffers from a larger increase due to the Miller Effect from the horizontal bus capacitance. This effect appears as a capacitance multiplier (see Equation 7). Therefore, for the value of W sel , the effective bus capacitance seen by the opamp is larger than that seen by a source-follower circuit.  
         [0029]     Secondly, an opamp based signal chain may provide increased pixel fixed pattern noise, if the capacitors on the two sides of the opamp (shown in  FIG. 5 ) are not accurately matched. Thirdly, compared with that in a source follower circuit, noise in the opamp signal chain also increases as a result of the Miller Effect.  
         [0030]     Thus, the problems can be summarized as follows.  
         [0031]     1. For a source-follower signal chain, the ohmic drop in M sel  causes unacceptably small voltage swing, large non-linearity, and reduced small signal gain at a given bias current as the frame-rate is increased, especially for large format arrays.  
         [0032]     2. For an opamp signal chain, the output noise rises rapidly while frame rate drops rapidly (at a fixed bias current) with increasing the array format due to a rapid increase in the effective horizontal bus capacitance caused by the Miller effect.  
       SUMMARY  
       [0033]     A switched source-follower design that does not require direct current current flow through the selection switch M sel  solves the above-mentioned problems. It overcomes the limitations of existing opamp based or source-follower based circuits used in column multiplexers and data readout. The new signal chain circuit may be used to improve the performance of CMOS imagers or readout integrated circuits (ROIC) for infrared (IR) or ultraviolet (UV) detectors.  
         [0034]     In an aspect of the circuits and methods disclosed herein, an analog bus driver and multiplexer circuit for a detector comprising an array of pixels is provided, the pixels being read out by columns, the circuit comprising a switched source-follower in each column connected by a bus common to the columns.  
         [0035]     In another aspect of the circuits and methods disclosed herein, a detector of radiation is provided, comprising: an array of pixels, wherein the pixels are read out by columns; and at least one analog bus driver and multiplexer circuit for readout, the circuit comprising: a switched source-follower in each column connected to a bus common to the columns.  
         [0036]     In yet another aspect of the circuits and methods disclosed herein, a method is provided for readout of a detector comprising a focal plane array of pixels, wherein the pixels are read out by columns, comprising the steps of: providing a switched source-follower in each column followed by a switched-capacitor gain stage common to the columns; sequentially reading out each column by switching the source-follower in each column to connect the source-follower output to a bus common to the columns; passing the source-follower output through the bus to the switched-capacitor gain stage.  
         [0037]     In still another aspect of the circuits and methods disclosed herein, an analog bus driver and multiplexer circuit for an imager is provided, the circuit comprising: a plurality of columns, each column comprising a switched source-follower; and a switched capacitor gain stage common to the plurality of columns, each source follower being connected to the switched capacitor gain stage. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0038]     The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings. The drawings are described below.  
         [0039]      FIG. 1  is a schematic block diagram of an integrated visible CMOS imager or readout integrated circuit (ROIC)  1  for infrared (IR) or ultraviolet (UV) detectors.  
         [0040]      FIG. 2  is a schematic for the CMOS imager/ROIC architecture with a source-follower per detector architecture.  
         [0041]      FIG. 3  is a schematic of two analog bus driver/multiplexer circuits.  
         [0042]      FIG. 4  is a schematic of a column source follower signal chain architecture.  
         [0043]      FIG. 5  is a schematic of an opamp signal chain architecture.  
         [0044]      FIG. 6  is a graph that shows the dependence of a p-channel source-follower output voltage (solid lines) on bias current IB s  (dotted lines) on M sel  width.  
         [0045]      FIG. 7  is a graph that shows the dependence of frame rate and output voltage for a source-follower signal chain as a function of Msel (for minimum length of Msel) for three different bias currents 0.1, 0.5, and 2 mA.  
         [0046]      FIG. 8  is a graph that shows the dependence of output voltage and gain on frame rate for a conventional surce-follower driving a horizontal bus in which the bias currents are 0.1, 0.5, and 2 mA, respectively.  
         [0047]      FIG. 9  is a schematic of the architecture of a new column signal chain according to a preferred embodiment, namely a source-follower with access-switch based signal chain.  
         [0048]      FIG. 10  is a schematic circuit diagram of the source-follower horizontal bus driver circuit of the preferred embodiment according to  FIG. 9 .  
         [0049]      FIG. 11  is a schematic circuit diagram of the source-follower horizontal bus driver circuit of the preferred embodiment according to  FIG. 9 , in which the polarity of the transistors is reversed.  
         [0050]      FIG. 12  is a schematic circuit diagram of an alternative version of the source-follower horizontal bus driver circuit of the preferred embodiment according to  FIG. 9 .  
         [0051]      FIG. 13  is a graph that shows the dependence of the frame rate (FPS) and the signal chain gain (gain) for three different circuits: the conventional source-follower (sf), the conventional opamp (op), and the in-column switched source follower (sfa) according to the present disclosure, for a megapixel imager. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0052]     In accordance with the present disclosure, an analog bus driver and multiplexer comprising a switched source-follower circuit architecture is provided.  
         [0053]      FIG. 9  shows the architecture of a switched source-follower bus driver  200  with access switches  215  for multiplexing to the horizontal bus  213 . It consists of a new switched source-follower  210  in each column (called an in-column switched source to follower (“ICS2F”)) followed by a single switched capacitor gain stage  220 . The switched capacitor gain stages consists of gain setting capacitors  222  (C s ) and  224  (C f ) and a high gain operational amplifier  226 . This architecture overcomes the problems associated with the two signal chains (conventional source follower circuit and op-amp signal chain circuit) described earlier.  
         [0054]     First, in this implementation, no dc current flows through the selection switch  215  (M sel ), and therefore this circuit does not suffer from ohmic drop issues that affect conventional source-follower based signal chains. By eliminating the ohmic drop in the multiplexing access switch  215 , the output voltage swing is increased, non-linearity is eliminated, and the small signal gain will approach its ideal value—unity (see  FIG. 13 ).  
         [0055]     Secondly, since no dc current flows through the selection switch  215  (M sel ), its width can be reduced, minimizing the horizontal bus capacitance, and speeding up the circuit speed even with small bias currents.  
         [0056]     Thirdly, there is only one switched capacitor gain stage  220  situated at the end of the horizontal bus. The input to the switched capacitor gain stage  220  is a capacitor  222  and the virtual ground of the operational amplifier within the gain stage is not connected to the horizontal bus  213 . The horizontal bus  213  carries voltage as opposed to charge (as was the case with the conventional opamp signal chain discussed earlier). Hence the bus charging and discharging is not slowed down by the Miller effect, allowing high speed horizontal bus driver circuit (source follower in this case) operation even with small bias currents.  
         [0057]      FIG. 10  shows a preferred version of the schematic circuit diagram of the source-follower horizontal bus driver circuit. It consists of a switched source-follower  210  in each column formed by FETs  212  (M sf ),  214  (M out ), and  216  (M ld ). Unlike a conventional source-follower chain, the load FET  216  (M ld ) is in each column, and is selected by turning on the FET  214  (M out ). Since the load FET  216  is in every column, a power bus  211  runs across each column connecting to the sources of load FETs  216  in every column. The source of the FET  212  (M sf ) constitutes the output of the source-follower. Each column output is connected to the horizontal bus  213  through the composite access FET  218  (M sel ). Since the FETs  214  (M out ) and  218  (M sel ) are turned off when a column is not selected, the current draw is similar to that of a conventional source-follower signal chain, while the elimination of ohmic drop across the composite access FET  218  (M sel ) allows the width of the composite access FET (M sel ) to be reduced to a minimum, causing a significant reduction in the bus capacitance.  
         [0058]      FIG. 11  shows a reversed polarity version 210′ of the switched source-follower circuit shown in  FIG. 10 , in which each transistor is of opposite polarity to that shown in  FIG. 10 . Accordingly, the load FET  216 ′ is connected to the ground bus  219  and the source-follower FET  212 ′ connects to the power bus  211 .  
         [0059]     In an alternate arrangement, it is also possible to eliminate the power bus from running across all columns by moving the load FET out of the column and using a bias bus  217 , as shown in the switched source-follower  210 A shown in  FIG. 12 . In this case, the bus capacitance remains small like that in the circuit of  FIG. 10 , but the voltage drop across the FET  214  (M out ) causes a reduction in voltage swing. The transistors in this circuit may have reversed polarity as explained in connection with  FIG. 11 .  
         [0060]     The output of the source-follower circuit  210  is given by:  
               V   out     =       V   Cs     +     V   to     +         2   ⁢           ⁢     I   bias         β   sf                   [   9   ]             
 
         [0061]     The response time is determined by the time required to charge the horizontal bus parasitic (C B ) and load capacitance (C drvsf ) [equal to C s  in  FIG. 9 ], and depends on the bias current (I bias ) and the transconductance of the composite access FET  218  M sf . By adding the slewing and the settling time together (assuming single pole response), the dependence I bias  on the column readout time (Δt read ) is given by:  
                 I   bias     =       I   R     +         I   S     2     [     1   +       1   +     4   ⁢       I   R       I   S               ⁢           ]         ⁢     
     ⁢         I   R     =           (       C   drvsf     +     C   B       )     ·   Δ     ⁢           ⁢   V         ζ   ·   Δ     ⁢           ⁢     t   read           ;           ⁢       I   S     =           (       C   drvsf     +     C   B       )     2     ·   χ       2   ⁢           ⁢       β   sf     ·   Δ     ⁢           ⁢     t   read   2           ;     ⁢     
     ⁢           ⁢       C   B     =       N   col     ·     (         W   sel     ·     C   edge       +     C   par       )                 [   10   ]             
 
         [0062]     In the circuit shown in  FIG. 10 , the noise contribution from the composite access FET  218  (M sel ) is minimized as a result of elimination of dc current flow through it. Sampled noise in this circuit is determined by the load capacitance and transconductance of the input FET M sf . With the same sized input FET, noise in this circuit is smaller than that in the opamp signal chain by a factor F op , where  
               F   op     =           C   L     +     C   B           [       C   L     +         C   f     ·     (       C   B     +     C   s       )           C   f     +     C   B     +     C   s           ]     ·     [         C   f     +     C   B     +     C   s         C   f       ]                   [   11   ]             
 
         [0063]     The reduction in noise in the source follower signal chain is due to the absence of the Miller effect that increases opamp signal chain noise. Therefore, unlike that of opamp based signal chain, the Miller multiplier term is absent from both the bias current and noise, allowing the source-follower based signal chain to simultaneously run faster and have lower noise.  
         [0064]      FIG. 13  shows the simulated dependence of frame rate and signal chain gain on the size or width (“W sel ”) of the select FET that connects. It indicates that of the three circuits, the switched source-follower circuit architecture (ICS2F) circuit (“sfa”) can operate with the highest frame rate (frames per second or “FPS”) for small W sel , compared to the conventional source follower signal chain (“sf”), while providing unity gain at different W sel , as in the case of the conventional op amp signal chain circuit (“op”). As expected, the frame rate for the ICS2F circuit reduces as W sel  is increased. With increasing W sel , the gain of a conventional source follower signal chain (“sf”) increases (approaches unity), but at the cost of vastly reduced frame rates.  
         [0065]     In conclusion, the switched source-follower circuit architecture (ICS2F) circuit provides several advantages compared with the other two circuits.  
         [0066]     Compared with a conventional source follower circuit, the switched source-follower circuit architecture (ICS2F) circuit provides higher operating speed, higher gain, improved linearity, and lower noise.  
         [0067]     Similarly, compared with a opamp signal chain, the switched source-follower circuit architecture (ICS2F) circuit provides higher operating speed and lower noise.  
         [0068]     While illustrative embodiments of the circuits and methods disclosed herein have been shown and described in the above description, numerous variations and alternative embodiments will occur to those skilled in the art and it should be understood that, within the scope of the appended claims, the invention may be practised otherwise than as specifically described. Such variations and alternative embodiments are contemplated, and can be made, without departing from the scope of the invention as defined in the appended claims.