Abstract:
A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed.

Description:
BACKGROUND  
       [0001]     Some signals transferred within computer systems have very strict timing constraints. For example, specifications that define computer bus systems often require that the signals of the bus system arrive at each node of the bus system at the same time, or within an acceptable tolerance. The bus signals must be synchronized so they can be read at a receiving node at the same time. Otherwise, data transmitted over the bus system could be corrupted, and the computer would not work.  
         [0002]     A physical signal-transmission portion of the bus system commonly includes signal lines formed in a printed circuit board (PCB). The bus signals travel, or propagate, through conductive traces disposed in various layers of the PCB between the nodes of the bus system. Each conductive trace forms a segment of one bus signal line.  
         [0003]     In a common situation, the distance between one pair of nodes of the bus system is significantly different from the distance between another pair of nodes. If both conductive traces electrically connecting both pairs of nodes were routed through the PCB in the shortest manner possible, then the length of the conductive traces would potentially be significantly different. The difference in lengths of the conductive traces, if sufficiently large, would significantly impact the timing of the bus signals transmitted between each of the nodes. The specification for the bus system, however, requires that the timing of the bus signals be within an acceptable tolerance of each other.  
         [0004]     To ensure that the signal timing requirements are met, the shorter conductive trace is artificially made longer to have a length about the same as the length of the longer conductive trace. To lengthen the shorter conductive trace, the conductive trace is routed in a serpentine manner for a portion of its length. The bus signals, thus, propagate through the different conductive traces in about the same amount of time.  
         [0005]     The trace-lengthening technique for bus signal synchronization requires that there be sufficient space in the PCB for the added length of some of the conductive traces. However, as ICs become more complex, the number of nodes, and concurrently the number of conductive traces, increases. Additionally, as the PCBs are made smaller, the space available for the conductive traces decreases. The increasing number and density of the conductive traces is incompatible with the decreasing space in the PCBs and places severe constraints on the layout of the PCB.  
         [0006]     One solution to this problem has been to increase the number of layers in the PCB in which the conductive traces can be formed. However, this solution increases the thickness of the PCBs and increases the time, complexity and cost of manufacturing the PCBs. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  is a simplified block diagram of a computer system according to an embodiment of the present invention.  
         [0008]      FIG. 2  is a simplified cross section of the computer system shown in  FIG. 1  and of a PCB incorporated therein according to an embodiment of the present invention.  
         [0009]      FIG. 3  is a simplified schematic view of the PCB shown in  FIG. 2  according to an embodiment of the present invention.  
         [0010]      FIG. 4  is another simplified cross section of the PCB shown in  FIG. 2  according to an embodiment of the present invention.  
         [0011]      FIG. 5  is another simplified cross section of the PCB shown in  FIG. 2  according to an embodiment of the present invention.  
         [0012]      FIG. 6  is a simplified cross section of a PCB incorporated in the computer system shown in  FIG. 1  according to an alternative embodiment of the present invention.  
         [0013]      FIG. 7  is a simplified timing chart for propagation times of unadjusted exemplary signals propagating through a PCB.  
         [0014]      FIG. 8  is a simplified timing chart for propagation times of adjusted exemplary signals propagating through a PCB incorporated in the computer system shown in  FIG. 1  according to an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0015]     A computer system  200  incorporating an embodiment of the present invention is shown in  FIG. 1 . The computer system  200  generally includes user interface devices, such as a keyboard and pointing device  202  and a monitor  204 . The computer system  200  also generally includes various I/O devices  206  and various integrated circuits (ICs)  208 ,  210  and  212 . The components  202 - 212  are generally connected by a variety of signals and bus systems  214 . The ICs  208 - 212  are preferably any appropriate computer chips, such as processors and ASICs (application specific ICs), among others, mounted within a housing  215 . The bus systems  214  may include serial (i.e. having one or few signals) and/or parallel (i.e. having several signals) bus systems.  
         [0016]     The ICs  208 - 212  and the bus system  214  connecting the ICs  208 - 212  are preferably incorporated in a populated printed circuit board  216  mounted within the housing  215 , as shown in  FIG. 2 . In addition to the ICs  208 - 212 , the populated printed circuit board  216  preferably includes a board  218  on which the ICs  208 - 212  and any other components are mounted, e.g. by soldering. The ICs  208 - 212  generally include several I/O points  220 , e.g. pins, leads, solder balls, etc., connected to the board  218 . The board  218  preferably includes several layers  222  and  224 , several vias  226 ,  228  and  230  and several conductive traces  232  and  234 . The vias  226 ,  228  and  230  and the conductive traces  232  and  234  generally form signal paths through which electronic signals (e.g. bus signals, clock signals, control signals, etc.) are transferred within the board  218  between the components mounted thereon.  
         [0017]     To form the bus system  214 , the ICs  208 - 212  are connected together at corresponding I/O points  220  by the vias  226 - 230  and the conductive traces  232  and  234 . For example, corresponding I/O points (pin 1s)  220  of the ICs  208  and  210  are connected through the via  226 , the conductive trace  232  and the via  228 . Similarly, corresponding I/O points (pin 1s)  220  of the ICs  210  and  212  are connected through the via  228 , the conductive trace  234  and the via  230 . Each of the conductive traces  232  and  234 , thus, forms a segment of one signal of the bus system  214 . Additional conductive traces may form segments of any other signals between the components mounted on the board  218 . Since each IC  208 - 212  is connected to more than one other IC  208 - 212  through each signal of the bus system  214 , the bus system  214  is referred to as a “multi-drop bus.” Additional vias and conductive traces within the board  218  may connect other I/O points on the ICs  208 - 212  and/or other components on the populated printed circuit board  216  whether connected by the bus system  214  or by any other signal lines.  
         [0018]     As shown in  FIG. 3 , though not necessarily drawn to scale, each of the signal segments, or conductive traces  232  and  234 , is of a different length, which is preferably minimized so as to take up as little space in the board  218  as possible. In particular, conductive trace  232  is longer than conductive trace  234 . Bus specifications, however, typically require that the propagation time through each segment of the bus system  214  be about the same, within a tolerance (on the order of 10s to 100s of picoseconds) of each other or of a specified time period, or within a specified time range. To ensure that signals arrive at each I/O point  220  within a desired propagation time range, the material of each layer  222  and  224  ( FIG. 2 ) surrounding the conductive traces  232  and  234  is selected for its effect on the propagation speed (measured in picoseconds per inch) of the signals transmitted through the conductive traces  232  and  234 . Since electrical signals propagate faster through conductive traces surrounded by material having a lower dielectric constant, the material of the layer  222  surrounding the longer conductive trace  232  preferably has a lower dielectric constant than does the material of the layer  224  surrounding the shorter conductive trace  234 . In this manner, the signals transferred through the longer conductive trace  232  propagate within about the same amount of time as the signals transferred through the shorter conductive trace  234 . In other words, the “length ratio” of the longer conductive trace  232  to the shorter conductive trace  234  is preferably about the same as the “speed ratio” of the faster propagation speed to the slower propagation speed for the layers  222  and  224 . Thus, the speed ratio for the layers  222  and  224  may be used to determine a range of allowable lengths for the conductive traces  232  and  234 .  
         [0019]     Although the description herein relates to the bus system  214 , it is understood that the invention is not so limited, but may also apply to other situations having bus and/or non-bus signals that have preferred timing constraints and which may be selectively placed in the layers  222  and  224  in order to affect the timing of these signals as desired. For example, distributed clock signals can be synchronized in this manner across a printed circuit board, an integrated circuit or other appropriate type of circuit apparatus.  
         [0020]     Similarly, as shown in  FIG. 4 , corresponding I/O points (pin Ns)  220  of the ICs  208  and  210  are connected through a via  236 , a conductive trace  238  and a via  240 . Additionally, corresponding I/O points (pin Ns)  220  of the ICs  210  and  212  are connected through the via  240 , a conductive trace  242  and a via  244 . Each of the conductive traces  238  and  242 , thus, forms a bus segment of another signal of the bus system  214  ( FIG. 1 ). The conductive trace  242  is longer than the conductive trace  238 . Therefore, the longer conductive trace  242  is preferably placed in the layer  222  having the lower dielectric constant and, therefore, the faster propagation speed, and the shorter conductive trace  238  is preferably placed in the layer  224  having the higher dielectric constant and, therefore, the slower propagation speed. In this manner, the bus signals transferred through the longer conductive trace  242  propagate within about the same amount of time as the bus signals transferred through the shorter conductive trace  238 .  
         [0021]     Additionally, according to an embodiment shown in  FIG. 5 , bus segments connecting different pairs of corresponding I/O points  220  are placed in the layers  222  and  224  depending on the lengths of the conductive traces  232  and  238 . In this case, corresponding I/O points (pin 1s)  220  of the ICs  208  and  210  are connected through the via  226 , the conductive trace  232  and the via  228 , and corresponding I/O points (pin Ns)  220  of the ICs  208  and  210  are connected through the via  236 , the conductive trace  238  and the via  240 . In this manner, the bus signals transmitted through different bus segments between the same two ICs propagate within about the same amount of time.  
         [0022]     Although not necessarily drawn to scale, the longer conductive trace  232  in  FIGS. 2 and 5  is not necessarily the same length as the longer conductive trace  242  in  FIG. 4 , even though both conductive traces  232  and  242  are shown in the same layer  222 . Similarly, although not necessarily drawn to scale, the shorter conductive trace  238  in  FIGS. 4 and 5  is not necessarily the same length as the shorter conductive trace  234  in  FIG. 2 , even though both conductive traces  238  and  234  are shown in the same layer  224 . Conductive traces of different lengths may be placed within the same layer  222  or  224 , however, as long as the propagation times for each conductive trace is within the accepted propagation time range, or within an allowable tolerance of a specified time period.  
         [0023]     The embodiments shown in  FIGS. 2, 4  and  5  have, for simplicity, shown only two layers  222  and  224  in the board  218 . However, according to an embodiment of the present invention, as shown in  FIG. 6 , a populated printed circuit board  246  may include a board  248  having any appropriate number of layers  250   a ,  250   b  and  250   m  (layer  1 , layer  2  . . . layer M). The actual number in a given situation may depend on the size of the bus, i.e. a bus with few signals could more easily get by with few layers, but a bus with many signals (e.g. hundreds of signals) may require several layers, each with a different dielectric material with a different propagation speed. In the example shown, thus, the materials for each layer  250   a - 250   m  are selected to give some of the layers  250   a - 250   m  different propagation speeds. Conductive traces (e.g.  256 ,  258 ,  260  and  262 ) are, therefore, preferably distributed among the layers  250   a - 250   m  according to the lengths of the conductive traces  256 - 262 . For example, the longer conductive traces (e.g.  256 ) are preferably placed in the layer (e.g.  250   a ) having the fastest dielectric material, the shorter conductive traces (e.g.  262 ) are preferably placed in the layer (e.g.  250   m ) having the slowest dielectric material, and the intermediate-length conductive traces (e.g.  258  and  260 ) are preferably placed in the layer(s) (e.g.  250   b ) having intermediate-speed dielectric material(s).  
         [0024]     The effect of the different dielectric materials on the bus signals in the layers  250   a - 250   m  is illustrated by time charts  264  and  266  shown in  FIGS. 7 and 8 , respectively, for “unadjusted exemplary signals” and “adjusted exemplary signals.” The adjusted exemplary signals are preferably an exemplary set of bus signals propagating through the various layers  250   a - 250   m  of the board  248  ( FIG. 6 ) at different propagation speeds. The unadjusted exemplary signals, on the other hand, represent the same bus signals under a hypothetical condition in which the propagation speeds are not adjusted by having materials with different dielectric constants for the layers  250   a - 250   m  of the board  248 . In other words, the dielectric materials for the layers  250   a - 250   m  are the same for the unadjusted exemplary signals. Thus, the unadjusted exemplary signals have the same propagation speeds and, therefore, different propagation times.  
         [0025]     In this example, as shown by  FIG. 7 , the propagation times fall into three ranges  268 ,  270  and  272 , and the unadjusted exemplary signals fall into three corresponding groups of bus signals  274 ,  276  and  278 . The bus signals  274  with the shortest propagation times propagate through the shortest conductive traces in the board  248 , the bus signals  276  with the intermediate propagation times propagate through the intermediate-length conductive traces in the board  248 , and the bus signals  278  with the longest propagation times propagate through the longest conductive traces in the board  248 . The bus signals  274  and  276  that do not fall within the propagation time range  268  are to be adjusted according to an embodiment of the present invention, so the short and intermediate bus signals  274  and  276  will fall within the propagation time range  268 .  
         [0026]     The dielectric material for the layer (e.g.  250   m ,  FIG. 6 ), which contains the shortest conductive traces (e.g.  262 ), is selected to have the slowest propagation speed. The dielectric material for the layer (e.g.  250   a ,  FIG. 6 ), which contains the longest conductive traces (e.g.  256 ), is selected to have the fastest propagation speed. The dielectric material for the layer (e.g.  250   b ,  FIG. 6 ), which contains the intermediate-length conductive traces (e.g.  258  and  260 ), is selected to have an intermediate propagation speed. In this manner, the propagation times for the bus signals  274  and  276  are effectively “stretched” to fall within the same propagation time range  268  as for the bus signals  278 , as shown in  FIG. 8 . Thus, all of the bus signals  274 ,  276  and  278  propagate within the acceptable propagation time range  268 .  
         [0027]     One of the bus signals  280  is illustrated as an exception to the other bus signals in the groups of bus signals  274  and  276 . If the bus signal  280  were placed in the board  248  in the minimum-length, most-economical signal path possible and adjusted only by placing the conductive trace for the bus signal  280  in the layer  250   b  with the intermediate-speed dielectric material, then the propagation time for the bus signal  280  would fall at point  282 , outside of the acceptable propagation time range  268 . On the other hand, if the bus signal  280  were adjusted by placing the conductive trace for the bus signal  280  in the layer  250   m  with the slowest dielectric material, then the propagation time for the bus signal  280  would fall at point  284 , also outside of the acceptable propagation time range  268 . Therefore, the bus signal  280  is preferably placed in the layer  250   b  with the intermediate-speed dielectric material, and the serpentine technique described in the background is preferably incorporated to “stretch,” or lengthen, the bus signal  280  an additional amount of time  286 . In this manner, the propagation time point  288  at which the bus signal  280  falls is within the acceptable propagation time range  268 . By thus combining the serpentine technique with an embodiment of the present invention, only a minimal amount of lengthening of the conductive trace for the bus signal  280  is required, so the additional space in the board  248  taken up by the serpentine portion of the conductive trace for the bus signal  280  is minimized.  
         [0028]     The selection of the number of layers in the printed circuit board, the dielectric materials for each of the layers and the lengths and placements of each of the conductive traces for any given printed circuit board design may be determined by experiment or simulation. In this manner, timing problems and considerations may be identified for the design. The best placement of the conductive traces in the layers (to take into account such timing problems and considerations) may thus be determined by such methods. The most space-saving placement of the conductive traces typically minimizes the lengths of the conductive traces. Upon determining the minimum length for each conductive trace, the propagation time for a signal passing therethrough may be determined in order to identify timing problems between different signals, assuming initially that the layers are all made of the same dielectric material. If such timing problems exist, then different dielectric materials may be substituted in some or all of the layers, and the conductive traces placed in the appropriate layer. In this manner, the various characteristic propagation speeds of the available dielectric materials for the different layers may be taken into consideration in the design or simulation. A range of allowable lengths for the conductive traces may thus be determined from the ratio of the characteristic propagation speeds between any two layers in conjunction with the allowable propagation time constraints. Other parameters, such as the distance between a conductive trace and a ground plane as well as the thickness, width and resistance of the conductive traces, may also affect propagation speed and should be taken into consideration in designs and simulations. Additionally, when the propagation speeds of selected dielectric materials for different layers are insufficient to compensate for the differences in lengths of conductive traces within the layers, the shorter conductive trace may have to be lengthened accordingly from its minimum, most-direct-route length.  
         [0029]     A common dielectric material for the layers of a printed circuit board is known as FR4. Additional types of material that have lower dielectric constants and faster propagation speeds include SPEEDBOARD™ C High Performance Prepreg and MICROLAM™ Dielectrics from W. L. Gore &amp; Associates, Inc. The faster material is generally more expensive, so FR4 is more commonly used.  
         [0030]     Dielectric constants (Er) for some materials may range between 1 (e.g. for a vacuum) and about 80 (e.g. for water). FR4, for instance, has an Er of about 4.7 for a propagation time of about 183.7 ps/in. SPEEDBOARD™ C has an Er of about 2.6 for a propagation time of about 137 ps/in. Practical dielectric constants, however, typically range from about 2 to about 5.  
         [0031]     Additionally, it is known that the dielectric constant of, and the relative propagation speed through, the material may be affected by varying the construction techniques of the dielectric material. Thus, different processes, as well as different materials, may be used in construction of the printed circuit board to achieve the desired results of having a variety of propagation speeds in the printed circuit board.  
         [0032]     An exemplary procedure for manufacturing a printed circuit board according to the present invention will be described with reference to  FIG. 2 . Typically, construction starts with a core layer including a dielectric material  290  (e.g. FR4) with a return (ground) or power plane  292  on one side and a conductive trace pattern  294  (including the conductive trace  234 ) on the other side. Then a “prepreg” layer (a flexible uncured epoxy resin)  296  is placed on the core layer  290 / 292 / 294 . The dielectric material  290  and prepreg layer  296  are preferably of the same or similar dielectric constant, which forms the dielectric surrounding the conductive trace  234 . Another core layer, including another dielectric material  298  (e.g. SPEEDBOARD™), a return or power plane  300  and a conductive trace pattern  302  (including the conductive trace  232 ), is placed on the prepreg layer  296 . The prepreg layer  296  is then cured. Another prepreg layer (e.g. SPEEDBOARD™)  304  is placed on top of the core layer  298 / 300 / 302 . The dielectric material  298  and prepreg layer  304  are preferably of the same or similar dielectric constant, which forms the dielectric surrounding the conductive trace  232 . The process of placing core layers and prepreg layers together is repeated until the board  218  has the desired number of layers. Additionally, a final return or power plane  306  is typically placed on top of the last prepreg layer  304 .  
         [0033]     An alternative embodiment of the present invention may be incorporated within another type of circuit apparatus, such as an IC chip, as opposed to a printed circuit board (e.g.  218 ,  FIG. 2 ). IC chips generally include several routing layers that have conductive traces within dielectric materials. The dielectric material in each layer, similar to the discussion above, is selected for its dielectric constant and signal propagation speed characteristics. Conductive traces of different lengths, but which carry signals that must be synchronized, are selectively placed within the routing layers depending on the lengths of the conductive traces and the propagation speeds of the routing layers. Thus, the shorter conductive traces are formed in routing layers having slower dielectric materials, and the longer conductive traces are formed in routing layers having faster dielectric materials.