Abstract:
A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 97124750, filed on Jul. 1, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a shift register apparatus and a method thereof. More particularly, the present invention relates to a shift register apparatus and a method thereof which may improve a utilization reliability of NMOS transistors used for pulling down voltage levels of output scan signals within the shift register apparatus to a low level gate voltage, and may cope with an increasing demand of narrow frame panels. 
     2. Description of Related Art 
     Recently, with booming development of the semiconductor technology, portable electronic devices and flat panel displays are widely used. Among various kinds of panel displays, the liquid crystal displays (LCDs) having the features of low operation voltage, no radiation, light-weight, small-size, etc. become popular in the market recently. Accordingly, the LCDs developed by various manufacturers trend to be miniaturization and low cost. 
     To reduce a fabrication cost of the LCD, under a condition that the LCD panel is fabricated based on an amorphous silicon (a-Si) process, some manufacturers have developed a technique to directly disposed shift registers within a scan driving IC that originally disposed at a scan side of the LCD panel on a glass substrate of the LCD panel. Therefore, the scan driving IC originally disposed at the scan side of the LCD panel can be omitted, so as to save the fabrication cost of the LCD. 
       FIG. 1  is a circuit block diagram illustrating a conventional shift register  100  directly disposed on a glass substrate of an LCD panel.  FIG. 2  is an operation waveform diagram of the shift register  100  of  FIG. 1 . Referring to  FIG. 1  and  FIG. 2 , first, during a first period t 1  within a frame period, when a control unit  101  receives a start pulse STV provided by a timing controller (not shown), or receives a scan signal G(n−1) output from a previous shift register (not shown), the control unit  101  generates two control signals CS 1  and CS 2  to turn on the NMOS transistor T A  and turn off the NMOS transistor T B . Therefore, charges of a high level gate voltage V GH  can be stored in a capacitor C during the first period t 1 . 
     Next, during a second period t 2  within the same frame period, the control unit  101  still generates the two control signals CS 1  and CS 2  to turn on the NMOS transistor T A  and turn off the NMOS transistor T B . However, since the capacitor C has already stored the charges of the high level gate voltage V GH  during the first period t 1 , the voltage level of the control signal CS 1  generated by the control unit  101  during the second period t 2  can be increased to about twice the high level gate voltage V GH , so as to easily raise the voltage level of the scan signal Gn output from the shift register  100  to the high level gate voltage V GH . 
     Next, after the second period t 2  of the same frame period, the control signals CS 1  and CS 2  generated by the control unit  101  are respectively stabilized to the low level gate voltage V GL  and the high level gate voltage V GH , and are maintain unchanged until the first period t 1  and the second period t 2  of a next frame period. Therefore, according to the above description, the NMOS transistor T B  is only turned off during the first period t 1  and the second period t 2  of the frame period, and is turned on all the other time, so as to pull down the voltage level of the scan signal Gn output from the shift register  100  to the low level gate voltage V GL . 
     In such case, the NMOS transistor T B  may be aged quickly due to a long time turning on state thereof, and accordingly utilization reliability thereof is decreased. Moreover, a charge trapping effect of the NMOS transistor T B  is deteriorate, so that a threshold voltage Vth of the NMOS transistor T B  is accelerately increased due to the long time turning on state. Therefore, a capability that the NMOS transistor T B  pulls down the voltage level of the scan signal Gn output from the shift register to the low level gate voltage V GL  is decreased. 
     Accordingly, a pixel activated corresponding to the scan signal Gn is liable to be mistaken as a pixel activated corresponding to the scan signal G(n+1) output by a next stage shift register, so that images displayed on the LCD can be abnormal. 
     To resolve the aforementioned problem, number of the NMOS transistors used for pulling down the voltage level of the scan signal output from the shift register to the low level gate voltage is suggested to be increased, and each of the NMOS transistors is utilized together with a control unit, so that only one NMOS transistor pulls down the voltage level of the scan signal output from the shift register to the low level gate voltage at a same time, so as to resolve the above problem. 
       FIG. 3  is a circuit block diagram of a shift register  300  which may resolve the problem of the shift register  100  of  FIG. 1 . In which when the voltage level of the scan signal Gn output from the shift register  300  has to be pulled down to the low level gate voltage V GL , the control units  301   a  and  301   b  may work under a separated operation mode to control only one of the NMOS transistors T 2  and T 6  to pull down the voltage level of the scan signal On output from the shift register  300  to the low level gate voltage V GL  at the same time, so as to resolve the problem of the shift register  100 . 
       FIG. 4  is a stress testing diagram for the NMOS transistor T B  of the shift register  100  of  FIG. 1  and the NMOS transistors T 2  and T 6  of the shift register  300  of  FIG. 3 . Referring to  FIG. 4 , a horizontal axis thereof represents time (hour), a vertical axis thereof represents shifting amounts of the threshold voltages (Vth) of the NMOS transistors T B , T 2  and T 6  (voltage), wherein the horizontal axis and the vertical axis all apply a log scale. Moreover, a solid line  401  raised along with the time represents a shifting amount of the threshold voltage (Vth) of the NMOS transistor T B  of the shift register  100 , and a dot line  402  raised along with the time represents shifting amounts of the threshold voltages (Vth) of the NMOS transistors T 2  and T 6  of the shift register  300 . 
     According to the above description of  FIG. 4 , it is obvious that shifting amounts of the threshold voltages (Vth) of the NMOS transistors T 2  and T 6  of the shift register  300  flatly trend to the shifting amounts of the threshold voltages (Vth) of the NMOS transistors T B  of the shift register  100 . Therefore, the utilization reliability of the NMOS transistors T 2  and T 6  can be improved, and the capability that the NMOS transistors T 2  and T 6  pull down the voltage level of the scan signal On output from the shift register  300  to the low level gate voltage V GL  is increased accordingly. 
     Though the shift register  300  of  FIG. 3  can resolve the problem of the shift register  100 , the NMOS transistors T 2  and T 6  used for pulling down the voltage level of the scan signal Gn output from the shift register  300  to the low level gate voltage V GL  have to be respectively utilized together with the control units  301   a  and  301   b , so that an layout area of the shift register  300  is increased a lot, which is of no avail to the increasing demand of narrow frame panels. 
     SUMMARY OF THE INVENTION 
     Accordingly, to cope with increasing demand of narrow frame panels, and to improve a utilization reliability of NMOS transistors within a shift register that used for pulling down voltage levels of output scan signals thereof to a low level gate voltage, the present invention provides a shift register apparatus directly disposed on a glass substrate of an LCD panel. The shift register apparatus includes a plurality of shift registers connected in serial. Each of the shift registers includes a first transistor, a second transistor, a third transistor, an energy storage device and a control unit. 
     In an embodiment of the present invention, a first drain/source of the first transistor receives a first clock signal, a gate of the first transistor receives a first control signal, and a second drain/source of the first transistor is used for generating a scan signal. A first drain/source of the second transistor is electrically connected to the second drain/source of the first transistor, a gate of the second transistor receives a second clock signal, and a second drain/source of the second transistor receives the first clock signal, wherein a phase difference between the first clock signal and the second clock signal is 180 degrees. 
     A first drain/source of the third transistor is electrically connected to the second drain/source of the first transistor, a gate of the third transistor receives a second control signal, and a second drain/source of the third transistor receives a low level gate voltage. The energy storage device is electrically connected between the gate and the second drain/source of the first transistor. The control unit generates the first control signal and the second control signal according to the first clock signal, the second clock signal, the low level gate voltage and a start signal. 
     In an embodiment of the present invention, each shift register utilizes the first transistor to pull up a voltage level of the scan signal to a high level gate voltage, and separately utilizes the second transistor and the third transistor to pull down the voltage level of the scan signal to the low level gate voltage during a frame period. 
     In an embodiment of the present invention, the control unit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. Wherein, a first drain/source of the fourth transistor receives the start signal, a gate of the fourth transistor receives the second clock signal, and a second drain/source of the fourth transistor is electrically connected to the gate of the first transistor for generating the first control signal. A gate of the fifth transistor is electrically connected to the second drain/source of the fourth transistor, a first drain/source of the fifth transistor receives the low level gate voltage, and a second drain/source of the fifth transistor is electrically connected to the gate of the third transistor for generating the second control signal. 
     A gate of the sixth transistor is electrically connected to the second drain/source of the fifth transistor, a first drain/source of the sixth transistor is electrically connected to the second drain/source of the fourth transistor, and a second drain/source of the sixth transistor receives the low level gate voltage. A gate of the seventh transistor is electrically connected to a first drain/source thereof for receiving the first clock signal, and a second drain/source of the seventh transistor is electrically connected to the second drain/source of the fifth transistor. 
     In an embodiment of the present invention, the LCD panel is fabricated based on an amorphous silicon (a-Si) process. Therefore, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are NMOS transistors. 
     According to another aspect, the present invention provides an LCD panel including the aforementioned shift register, and an LCD including the LCD panel. 
     According to still another aspect, the present invention provides a shift registering method for the aforementioned shift register apparatus. The shift registering method includes following steps. First, during a first period of the frame period, when the start signal and the second clock signal are simultaneously enabled, the first control signal and the second control signal generated by the control unit are respectively enabled and disabled, so as to pull down the voltage level of the scan signal to the low level gate voltage via the second transistor. Next, during a second period of the frame period, when the start signal and the second clock signal are simultaneously disabled, the first control signal and the second control signal generated by the control unit are respectively enabled and disabled, so as to pull up the voltage level of the scan signal to the high level gate voltage via the first transistor. 
     Next, during a third period of the frame period, when the start signal and the second clock signal are respectively disabled and enabled, the first control signal and the second control signal generated by the control unit are simultaneously disabled, so as to pull down the voltage level of the scan signal to the low level gate voltage via the second transistor. Finally, during a fourth period of the frame period, when the start signal and the second clock signal are simultaneously disabled, the first control signal and the second control signal generated by the control unit are respectively disabled and enabled, so as to pull down the voltage level of the scan signal to the low level gate voltage via the third transistor. 
     According to the shift register apparatus and the method thereof provided by the present invention, number of the NMOS transistors used for pulling down the level of the scan signal outputted by the shift register to the low level gate voltage is increased to two, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. 
     Therefore, shifting amounts of the threshold voltages of the two NMOS transistors used for pulling down the level of the scan signal output from the shift register to the low level gate voltage trend to be flat, and accordingly utilization reliability of the NMOS transistors can be greatly improved. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of the whole shift register apparatus can be reduced, so as to cope with an increasing demand of narrow frame panels. 
     In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  is a circuit block diagram illustrating a conventional shift register  100  directly disposed on a glass substrate of an LCD panel. 
         FIG. 2  is an operation waveform diagram of the shift register  100  of  FIG. 1 . 
         FIG. 3  is a circuit block diagram of a shift register  300  which may resolve a problem of the shift register  100  of  FIG. 1 . 
         FIG. 4  is a stress testing diagram for an NMOS transistor T B  of the shift register  100  of  FIG. 1  and the NMOS transistors T 2  and T 6  of the shift register  300  of  FIG. 3 . 
         FIG. 5  is a circuit block diagram illustrating a shift register apparatus  500  according to an embodiment of the present invention. 
         FIG. 6  is a detailed circuit diagram of one of the registers SR 1 ˜SR 3  within the shift register apparatus  500 . 
         FIG. 7  is an operation timing diagram of the shift register apparatus  500  of  FIG. 5 . 
         FIG. 8  is a stress testing diagram for the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ of the shift registers SR 1 ˜SR 4  of  FIG. 6  when the second drains/sources thereof individually receiving the clock signal CKB/CK and the low level gate voltage V GL . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     The technical functions to be achieved by the present invention are mainly to improve a utilization reliability of NMOS transistors used for pulling down voltage levels of all scan signals output by the shift registers to a low level gate voltage, and to cope with an increasing demand of narrow frame panels. In the following content, technical characteristics of the present invention are described in detail for those skilled in the art. 
       FIG. 5  is a circuit block diagram illustrating a shift register apparatus  500  according to an embodiment of the present invention. Referring to  FIG. 5 , the shift register apparatus  500  of the present embodiment is directly disposed on a glass substrate of an LCD panel (not shown), and includes a plurality of shift registers (with a number thereof being equal to a number of scan lines of the LCD panel) for sequentially generating scan signals to the corresponding scan lines, so as to activate or deactivate pixels coupled to the scan lines. 
     Moreover, the LCD panel is fabricated based on an amorphous silicon (a-Si) process. To fully convey the spirit of the present invention, the LCD panel is assumed to have three scan lines, and accordingly, the shift register apparatus  500  has three shift registers SR 1 ˜SR 3 , though the present invention is not limited thereof. 
     In the present embodiment, the shift register SR 1  includes a control unit  501   a , transistors T 1 ′˜T 3 ′ and an energy storage device C 1 . The control unit  501   a  generates a control signal CS 1  and a control signal CS 2  according to a clock signal CKB, a clock signal CK, a low level gate voltage V GL , and a start pulse STV provided by a timing controller (not shown), wherein a phase difference between the clock signal CKB and the clock signal CK is 180 degree, which can also be provided by the timing controller. 
     Moreover, a first drain/source of the transistor T 1 ′ receives the clock signal CK, a gate of the transistor T 1 ′ receives the control signal CS 1 , and a second drain/source of the transistor T 1 ′ is used for generating a scan signal G 1 . A first drain/source of the transistor T 2 ′ is electrically connected to the second drain/source of the transistor T 1 ′, a gate of the transistor T 2 ′ receives the clock signal CKB, and a second drain/source of the transistor T 2 ′ receives the clock signal CK. A first drain/source of the transistor T 3 ′ is electrically connected to the second drain/source of the transistor T 1 ′, a gate of the transistor T 3 ′ receives the control signal CS 2 , and a second drain/source of the transistor T 3 ′ receives the low level gate voltage V GL . The energy storage device C 1  is electrically connected between the gate and the second drain/source of the transistor T 1 ′, which can be implemented by a capacitor. 
     Moreover, the shift register SR 1  utilizes the transistor T 1 ′ to pull up a voltage level of the scan signal G 1  to a high level gate voltage V GH , and separately utilizes the transistors T 2 ′ and T 3 ′ to pull down the voltage level of the scan signal G 1  to the low level gate voltage V GL  during a frame period. 
     In the present embodiment, the shift register SR 2  includes a control unit  501   b , transistors T 4 ′˜T 6 ′ and an energy storage device C 2 . Wherein, the control unit  501   b  generates a control signal CS 3  and a control signal CS 4  according to the clock signal CKB, the clock signal CK, the low level gate voltage V GL , and the scan signal G 1  output from the shift register SR 1 . 
     Moreover, a first drain/source of the transistor T 4 ′ receives the clock signal CKB, a gate of the transistor T 4 ′ receives the control signal CS 3 , and a second drain/source of the transistor T 4 ′ is used for generating a scan signal G 2 . A first drain/source of the transistor T 5 ′ is electrically connected to the second drain/source of the transistor T 4 ′, a gate of the transistor T 5 ′ receives the clock signal CK, and a second drain/source of the transistor T 5 ′ receives the clock signal CKB. A first drain/source of the transistor T 6 ′ is electrically connected to the second drain/source of the transistor T 4 ′, a gate of the transistor T 6 ′ receives the control signal CS 4 , and a second drain/source of the transistor T 6 ′ receives the low level gate voltage V GL . The energy storage device C 2  is electrically connected between the gate and the second drain/source of the transistor T 4 ′, which can also be implemented by a capacitor. 
     Moreover, the shift register SR 2  utilizes the transistor T 4 ′ to pull up a voltage level of the scan signal G 2  to the high level gate voltage V GH , and separately utilizes the transistors T 5 ′ and T 6 ′ to pull down the voltage level of the scan signal G 2  to the low level gate voltage V GL  during a frame period. 
     In the present embodiment, the shift register SR 3  includes a control unit  501   c , transistors T 7 ′˜T 6 ′ and an energy storage device C 3 . Wherein, the control unit  501   c  generates a control signal CS 5  and a control signal CS 6  according to the clock signal CKB, the clock signal CK, the low level gate voltage V GL , and the scan signal G 3  output from the shift register SR 2 . 
     Moreover, a first drain/source of the transistor T 7 ′ receives the clock signal CK, a gate of the transistor T 4 ′ receives the control signal CS 5 , and a second drain/source of the transistor T 7 ′ is used for generating a scan signal G 3 . A first drain/source of the transistor T 8 ′ is electrically connected to the second drain/source of the transistor T 7 ′, a gate of the transistor T 8 ′ receives the clock signal CKB, and a second drain/source of the transistor T 8 ′ receives the clock signal CK. A first drain/source of the transistor T 9 ′ is electrically connected to the second drain/source of the transistor T 7 ′, a gate of the transistor T 9 ′ receives the control signal CS 6 , and a second drain/source of the transistor T 9 ′ receives the low level gate voltage V GL . The energy storage device C 3  is electrically connected between the gate and the second drain/source of the transistor T 7 ′, which can also be implemented by a capacitor. 
     Moreover, the shift register SR 3  utilizes the transistor T 7 ′ to pull up a voltage level of the scan signal G 3  to the high level gate voltage V GH , and separately utilizes the transistors T 8 ′ and T 9 ′ to pull down the voltage level of the scan signal G 3  to the low level gate voltage V GL  during a frame period. 
       FIG. 6  is a detailed circuit diagram of one of the registers SR 1 ˜SR 3  within the shift register apparatus  500 . Referring to  FIG. 5  and  FIG. 6 , in the present embodiment, the control units  501   a ˜ 501   c  are formed by transistors T 10 ″˜T 13 ″. Wherein, a first drain/source of the transistor T 10 ″ correspondingly receives the start pulse STV/scan signal G 1 /scan signal G 2 , a gate of the transistor T 10 ″ correspondingly receives the clock signal CKB/CK, and a second drain/source of the transistor T 10 ″ is electrically connected to the gates of the transistors T 1 ′/T 4 ′/T 7 ′ for correspondingly generating the control signals CS 1 /CS 3 /CS 5 . 
     A gate of the transistor T 11 ″ is electrically connected to the second drain/source of the transistor T 10 ″, a first drain/source of the transistor T 11 ″ receives the low level gate voltage V GL , and a second drain/source of the transistor T 11 ″ is electrically connected to the gates of the transistors T 3 ′/T 6 ′/T 9 ′ for correspondingly generating the control signals CS 2 /CS 4 /CS 6 . A gate of the transistor T 12 ″ is electrically connected to the second drain/source of the transistor T 11 ″, a first drain/source of the transistor T 12 ″ is electrically connected to the second drain/source of the transistor T 10 ″, and a second drain/source of the transistor T 12 ″ receives the low level gate voltage V GL . A gate and a first drain/source of the transistor T 13 ″ are electrically connected for correspondingly receiving the clock signal CKB/CK, and a second drain/source of the transistor T 13 ″ is electrically connected to the second drain/source of the transistor T 11 ″. 
     It should be noted that since the LCD panel is fabricated based on the a-Si process, the aforementioned transistors T 1 ′˜T 9 ′ and T 10 ″˜T 13 ″ are all NMOS transistors. For describing the technical functions to be achieved by the shift register apparatus  500  of the present embodiment, an operation timing diagram of the shift register apparatus  500  is provided to fully convey the spirit of the present invention to those skilled in the art. 
       FIG. 7  is an operation timing diagram of the shift register apparatus  500  of  FIG. 5 . Referring to  FIG. 5  through  FIG. 7 , it should be noted that logic high levels of the clock signal CKB and the clock signal CK are set to the high level gate voltage V GH  that can activate the pixels, and logic low levels of the clock signal CKB and the clock signal CK are set to the low level gate voltage V GL  that can deactivate the pixels. 
     Therefore, during a first period t 1 ′ within a frame period F 1 , since the start pulse STV and the clock signal CKB received by the shift register SR 1  are simultaneously enabled, the control signal CS 1  and the control signal CS 2  generated by the control unit  501   a  within the shift register SR 1  are respectively enabled and disabled. Accordingly, the transistor T 2 ′ pulls down the voltage level of the scan signal G 1  to the low level gate voltage V GL , and the energy storage device C 1  first stores charges of the high level gate voltage V GH  during the first period t 1 ′. 
     Next, during a second period t 2 ′ of the same frame period F 1 , since the start pulse STV and the clock signal CKB received by the shift register SR 1  are simultaneously disabled, the control signal CS 1  and the control signal CS 2  generated by the control unit  501   a  within the shift register SR 1  are respectively enabled and disabled. However, since the energy storage device C 1  has already stored the charges of the high level gate voltage V GH  during the first period t 1 ′, the voltage level of the control signal CS 1  generated by the control unit  501   a  during the second period t 2 ′ is pulled up to about twice the high level gate voltage V GH  for being provided to the gate of the transistor T 1 ′. Accordingly, the transistor T 1 ′ pulls up the voltage level of the scan signal G 1  output from the shift register SR 1  to the high level gate voltage V GH . 
     Next, during a third period t 3 ′ within the same frame period F 1 , since the start pulse STV and the clock signal CKB received by the shift register SR 1  are respectively disabled and enabled, the control signal CS 1  and the control signal CS 2  generated by the control unit  501   a  within the shift register SR 1  are simultaneously disabled. Accordingly, the transistor T 2 ′ pulls down the voltage level of the scan signal G 1  to the low level gate voltage V GL . 
     Finally, during a fourth period t 4 ′ within the same frame period F 1 , since the start pulse STV and the clock signal CKB received by the shift register SR 1  are simultaneously disabled, the control signal CS 1  and the control signal CS 2  generated by the control unit  501   a  within the shift register SR 1  are respectively disabled and enabled. Accordingly, the transistor T 3 ′ pulls down the voltage level of the scan signal G 1  to the low level gate voltage V GL . 
     According to the above description, during the frame period F 1 , the devices in charge of pulling down the voltage level of the scan signal G 1  output from the shift register SR 1  to the low level gate voltage V GL  are assigned to the NMOS transistors T 2 ′ and T 3 ′. Therefore, as the operation time of the shift register SR 1  increases, shifting amounts of the threshold voltages of the NMOS transistors T 2 ′ and T 3 ′ trend to be flat. 
     Moreover, since the second drain/source of the NMOS transistor T 2 ′ receives the clock signal CK, a charge trapping effect of the NMOS transistor T 2 ′ is greatly mitigated, so that the shifting amount of the threshold voltage of the NMOS transistor T 2 ′ will not be accelerately increased along with a long time turning on state thereof, and accordingly the utilization reliability of the NMOS transistor T 2 ′ can be greatly improved. 
     Meanwhile, during the first period t 1 ′ within the same frame period F 1 , since the scan signal G 1  and the clock signal CK received by the shift register SR 2  are simultaneously disabled, the control signal CS 3  and the control signal CS 4  generated by the control unit  501   b  within the shift register SR 2  are respectively disabled and enabled. Accordingly, the transistor T 6 ′ pulls down the voltage level of the scan signal G 2  to the low level gate voltage V GL . 
     Next, during the second period t 2 ′ of the same frame period F 1 , since the scan signal G 1  and the clock signal CK received by the shift register SR 2  are simultaneously enabled, the control signal CS 3  and the control signal CS 4  generated by the control unit  501   b  within the shift register SR 2  are respectively enabled and disabled. Accordingly, the transistor T 5 ′ pulls up the voltage level of the scan signal G 2  to the high level gate voltage V GH , and the energy storage device C 2  first stores charges of the high level gate voltage V GH  during the second period t 2 ′. 
     Next, during the third period t 3 ′ within the same frame period F 1 , since the scan signal G 1  and the clock signal CK received by the shift register SR 1  are simultaneously disabled, the control signal CS 3  and the control signal CS 3  generated by the control unit  501   b  within the shift register SR 2  are respectively enabled and disabled. However, since the energy storage device C 2  has already stored the charges of the high level gate voltage V GH  during the second period t 2 ′, the voltage level of the control signal CS 3  generated by the control unit  501   b  during the third period t 3 ′ is pulled up to about twice the high level gate voltage V GH  for being provided to the gate of the transistor T 4 ′. Accordingly, the transistor T 4 ′ pulls up the voltage level of the scan signal G 2  to the high level gate voltage V GH . 
     Finally, during the fourth period t 4 ′ within the same frame period F 1 , since the scan signal G 1  and the clock signal CK received by the shift register SR 2  are respectively disabled and enabled, the control signal CS 3  and the control signal CS 4  generated by the control unit  501   b  within the shift register SR 2  are simultaneously disabled. Accordingly, the transistor T 5 ′ pulls down the voltage level of the scan signal G 2  to the low level gate voltage V GL . 
     According to the above description, during the frame period F 1 , the devices in charge of pulling down the voltage level of the scan signal G 2  output from the shift register SR 2  to the low level gate voltage V GL  are assigned to the NMOS transistors T 5 ′ and T 6 ′. Therefore, as the operation time of the shift register SR 2  increases, shifting amounts of the threshold voltages of the NMOS transistors T 5 ′ and T 6 ′ trend to be flat. 
     Moreover, since the second drain/source of the NMOS transistor T 5 ′ receives the clock signal CKB, a charge trapping effect of the NMOS transistor T 5 ′ is greatly mitigated, so that the shifting amount of the threshold voltage of the NMOS transistor T 5 ′ will not be accelerately increased along with a long time turning on state thereof, and accordingly the utilization reliability of the NMOS transistor T 5 ′ can be greatly improved. 
     Meanwhile, during the first period t 1 ′ within the same frame period F 1 , since the scan signal G 2  and the clock signal CKB received by the shift register SR 3  are respectively disabled and enabled, the control signal CS 5  and the control signal CS 6  generated by the control unit  501   c  within the shift register SR 3  are simultaneously disabled. Accordingly, the transistor T 8 ′ pulls down the voltage level of the scan signal G 3  to the low level gate voltage V GL . 
     Next, during the second period t 2 ′ of the same frame period F 1 , since the scan signal G 2  and the clock signal CKB received by the shift register SR 3  are simultaneously disabled, the control signal CS 5  and the control signal CS 6  generated by the control unit  501   c  within the shift register SR 3  are respectively disabled and enabled. Accordingly, the transistor T 9 ′ pulls down the voltage level of the scan signal G 3  to the low level gate voltage V GL . 
     Next, during the third period t 3 ′ within the same frame period F 1 , since the scan signal G 2  and the clock signal CKB received by the shift register SR 3  are simultaneously enabled, the control signal CS 5  and the control signal CS 6  generated by the control unit  501   c  within the shift register SR 4  are respectively enabled and disabled. Accordingly, the transistor T 8 ′ pulls down the voltage level of the scan signal G 3  to the low level gate voltage V GL , and the energy storage device C 3  first stores charges of the high level gate voltage V GH  during the third period t 3 ′. 
     Finally, during the fourth period t 4 ′ within the same frame period F 1 , since the scan signal G 2  and the clock signal CKB received by the shift register SR 3  are simultaneously disabled, the control signal CS 5  and the control signal CS 6  generated by the control unit  501   c  within the shift register SR 3  are respectively enabled and disabled. However, since the energy storage device C 3  has already stored the charges of the high level gate voltage V GH  during the third period t 3 ′, the voltage level of the control signal CS 5  generated by the control unit  501   c  during the fourth period t 4 ′ is pulled up to about twice the high level gate voltage V GH  for being provided to the gate of the transistor T 7 ′. Accordingly, the transistor T 7 ′ pulls up the voltage level of the scan signal G 3  to the high level gate voltage V GH . 
     According to the above description, during the frame period F 1 , the devices in charge of pulling down the voltage level of the scan signal G 3  output from the shift register SR 3  to the low level gate voltage V GL  are assigned to the NMOS transistors T 8 ′ and T 9 ′. Therefore, as the operation time of the shift register SR 3  increases, shifting amounts of the threshold voltages of the NMOS transistors T 8 ′ and T 9 ′ trend to be flat. 
     Moreover, since the second drain/source of the NMOS transistor T 8 ′ receives the clock signal CK, a charge trapping effect of the NMOS transistor T 8 ′ is greatly mitigated, so that the shifting amount of the threshold voltage of the NMOS transistor T 8 ′ will not be accelerately increased along with a long time turning on state thereof, and accordingly the utilization reliability of the NMOS transistor T 8 ′ can be greatly improved. 
     Besides, since the transistors T 13 ″ within the control units  501   a ˜ 501   c  is diode connected, so that the voltage levels of the control signals CS 2 , CS 4  and CS 6  are lower than the voltage level of the high level gate voltage V GH , an therefore lifespan of the NMOS transistors T 3 ′, T 6 ′ and T 9 ′ can be prolonged. 
     Moreover, it should be noted that according to the spirit of the present invention, the second drains/sources of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ are not limited to just receive the clock signal CKB/CK. Namely, the second drains/sources of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ can also receive the low level gate voltage V GL , while the shift register apparatus  550  can still achieve the same technical function. 
       FIG. 8  is a stress testing diagram for the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ of the shift registers SR 1 ˜SR 4  of  FIG. 6  when the second drains/sources thereof individually receiving the clock signal CKB/CK and the low level gate voltage V GL . Referring to  FIG. 8 , a horizontal axis of the stress testing diagram represents time (hour), and a vertical axis thereof represents shifting amounts of the threshold voltages Vth of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′. Wherein, a solid line  801  raised along with the time represents shifting amounts of the threshold voltages (Vth) measured under a condition that the second drains/sources of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ receive the clock signal CKB/CK, and a dot line  802  raised along with the time represents shifting amounts of the threshold voltages (Vth) measured under a condition that the second drains/sources of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ receive the low level gate voltage V GL . 
     According to the above description of  FIG. 8 , it is obvious that the shifting amount of the threshold voltage (Vth) measured under the condition that the second drains/sources of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ receive the clock signal CKB/CK is less than the shifting amount of the threshold voltage (Vth) measured under the condition that the second drains/sources of the NMOS transistors T 2 ′, T 5 ′ and T 8 ′ receive the low level gate voltage V GL . 
     Therefore, compared the shift register of the present invention to the shift register of the related art, the utilization reliability and lifespan of the shift register of the present invention is better and longer than that of the shift register of the related art. Moreover, since only one control unit is required within the shift register, a whole layout area of the shift register apparatus of the present invention is reduced, so as to cope with an increasing demand of narrow frame panels. Accordingly, if the shift register apparatus is directly disposed on the glass substrate of the LCD panel, the LCD panel and the LCD thereof are then considered to be within the scope of the present invention. 
     Besides the shift register apparatus of the aforementioned embodiment, the present invention further provides a shift registering method, and detail description of the shift registering method is included within the description of the shift register apparatus of the aforementioned embodiment. Therefore, those skilled in the art can deduce the shift registering method with reference of the aforementioned description, so that detailed description thereof will not be repeated. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.