Abstract:
Method for calculating model parameters for a capacitor to be modelled, the method comprising the following steps of: incorporating the capacitor to be modelled into a DC to DC converter with at least a first switching element; connecting a resistive load between the output terminals; applying an input voltage to the input terminals of the converter; controlling the first switching element in accordance with a frequency and duty cycle in order to obtain a current varying periodically in time through the capacitor to be modelled; measuring at least a first quantity representative of the current through the capacitor and at least a second quantity representative of the voltage across the capacitor; determining on the basis of the measured first and second quantities at least one current value for the current through the capacitor and at least one voltage value for the voltage across the capacitor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Belgian Patent Application No. 2014/5055, filed on Nov. 7, 2014, and entitled “Method and system for calculating model parameters for a capacitor to be modelled”, the full disclosure of which is incorporated herein by reference. 
       TECHNICAL FIELD 
       [0002]    The present invention relates to a method and a system for calculating model parameters for a capacitor to be modelled. 
       BACKGROUND 
       [0003]    The properties of a capacitor are dependent on the voltage applied across the capacitor and/or the current applied through the capacitor, and are particularly dependent on the amplitude, frequency and waveform of these signals. A known technique for measuring a capacitor uses a so-called LCR meter. Used as signal source in an LCR meter is a sine wave. 
         [0004]    When a capacitor is used in a circuit, the signals are often not sine waves, but rather block waves or sawtooth, and high currents and/or voltages can occur. Practice has shown that in such conditions an LCR meter does not produce good values for accurate modelling of the capacitor. 
         [0005]    WO 2013/110145 discloses a method for calculating model parameters for a coil, comprising of: incorporating the coil into a converter with a switching element; connecting a resistive load; applying an input voltage; controlling the switching element in order to obtain a periodically varying voltage across the coil; measuring at least a first and second quantity representative of respectively the voltage across and the current through the coil; determining at least one voltage value and at least one current value on the basis of the measured first and second quantity; calculating a loss resistance and/or a loss power of the coil on the basis of the at least one voltage value and the at least one current value. 
         [0006]    The model that is being used for modelling a coil in WO 2013/110145 comprises a series connection of an inductance L and a loss resistance R LS . Modelling a capacitor is more complex.  FIG. 3  of the present application illustrates a possible model for a capacitor comprising a parallel circuit of a loss resistance R leak  and of a series circuit of a capacitance C TEST , a parasitic inductance L ESL , a parasitic resistance R ESR . Because the parasitic inductance L ESL  needs to be determined, the skilled person needs to find a way to deal with parasitic inductance in the measurement circuit. This implies that a measurement circuit for modelling coils cannot be simply adapted to be used for modelling capacitors. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention has for its object to provide a system and method of the type stated in the preamble with which a capacitor can be modelled in a wide range in a manner which is accurate and can be readily implemented in practice, i.e. a system and method with which model parameters, such as the capacitance and the losses and non-linearities, of a capacitor can be modelled for a wide range of applications. 
         [0008]    According to a first aspect, the invention relates to a method for calculating model parameters for a capacitor to be modelled. The method comprises the following steps of: incorporating the capacitor to be modelled into a DC to DC converter with at least a first switching element; which DC to DC converter has input terminals and output terminals; connecting a resistive load between the output terminals of the DC to DC converter; applying an input voltage to the input terminals of the DC to DC converter; controlling the first switching element in accordance with a frequency and duty cycle in order to obtain a current varying periodically in time through the capacitor to be modelled, which current depends at least for a part of a period on the input voltage; measuring at least a first quantity representative of the current through the capacitor at successive points in time in at least said part of a period; measuring at least a second quantity representative of the voltage across the capacitor at successive points in time in at least said part of a period; determining on the basis of the measured first quantity at least one current value for the current through the capacitor; determining on the basis of the measured second quantity at least one voltage value for the voltage across the capacitor; repeating the above stated steps for at least one of: a different input voltage, a different frequency, a different duty cycle, a different resistive load; calculating model parameters of the capacitor on the basis of the measured quantities. The successive points in time preferably cover a substantially complete period. 
         [0009]    Incorporating a capacitor into a DC to DC converter creates a realistic operating environment of the capacitor. Such an operating environment further allows a number of input parameters, such as the input voltage, the frequency, the duty cycle and the resistance value of the load, to be varied in accordance with the operating range over which it is desired to characterize the capacitor. An accurate result can further be obtained by making use of successive measurements. 
         [0010]    The model parameters preferably comprise a capacitance and at least one of the following: a parasitic inductance intended for connection in series to the capacitance, a parasitic resistance intended for connection in series to the capacitance, and a loss power. In addition, the model parameters can also comprise a leakage resistance which is connected in parallel in the model to the series connection of the capacitance, the parasitic inductance and the parasitic resistance. 
         [0011]    The method preferably further comprises of: measuring a quantity representative of the current through the resistive load at successive points in time in at least said part of a period. 
         [0012]    In a preferred embodiment the DC to DC converter comprises a coil and a second switching element which are arranged such that in the coil the current builds up in the coil in a first position of the first switching element and that in the coil the current falls away in the coil in a second position of the first switching element. In such an embodiment it is possible, instead of or in addition to measuring the current through the resistive load, to also measure a quantity representative of the current through the coil at successive points in time in at least said part of the period. Providing a coil in the DC-DC converter causes current peaks during switching of the first switching element which make it possible to properly characterize particularly the parasitic resistance and the parasitic inductance. The coil is for instance a boost coil which is charged during discharge of the capacitor in the resistive load. 
         [0013]    In a preferred embodiment the capacitor is connected in parallel to the resistive load. The capacitor will in this way at least partially discharge in the resistive load in a first or second position of the switch, whereby characterizing of particularly the capacitance of the capacitor can take place in simple manner. The second switching element, for instance a diode, preferably switches substantially synchronously with the first switching element. 
         [0014]    The DC-DC converter is preferably configured to display at least one of a boost converter behaviour and a buck converter behaviour. The voltage across a coil of the DC to DC converter will in this way display substantially a block form (boost behaviour) or a substantially triangular progression (buck behaviour). Both voltage progressions allow a good characterizing of the capacitor. The DC to DC converter is for instance a classical boost converter with a boost coil, but can also be one of the following: a buck converter, buck-boost converter, non-inverting buck-boost converter, a sepic converter (single-ended primary-inductor converter), a reverse sepic converter, a cuk converter, a resonant converter, a push-pull converter, a fly-back converter, full bridge converter. 
         [0015]    According to an exemplary embodiment, the method comprises of: determining on the basis of the measured second quantity at least a first and second voltage value for the voltage across the capacitor at respectively a first and a second point in time (t 1 , t 2 ) of the successive points in time, which first and second points in time are preferably chosen during discharge of the capacitor in the resistive load; and calculating the capacitance of the capacitor on the basis of at least the first and second voltage value, the time difference between the first and second points in time (t 1 , t 2 ) and the resistance of the resistive load. 
         [0016]    According to an exemplary embodiment, the loss power is calculated as an integral of the product of the voltage across the capacitor and the current through the capacitor on the basis of the measurements of the first and second quantity at the successive points in time, wherein the successive points in time preferably cover a substantially complete period. 
         [0017]    According to an exemplary embodiment, the method comprises of: determining on the basis of the measured second quantity at least a third and fourth voltage value for the voltage across the capacitor at respectively a third and a fourth point in time (t 3 , t 4 ) of the successive points in time in said part of the period; which third and fourth points in time are located in a transition period during which the first switching element switches; calculating the parasitic inductance on the basis of at least the third and fourth voltage value. According to an exemplary embodiment the parasitic inductance (L ESL ) is calculated as 
         [0000]        L   ESL =abs( U   4   −U   3 ) t   trans /( I   out   +I   L ) 
         [0000]    wherein U 4  and U 3  are respectively the third and fourth voltage value, t trans  is the transition period, I OUT  is the average current through the resistive load during the transition period and I L  is the maximum or minimum input current in the DC-DC converter depending on whether the capacitor switches from discharge to charge or vice versa; wherein the third point in time (t 3 ) is chosen as a time at which the voltage value is maximal or minimal depending on whether the capacitor switches from discharge to charge or vice versa, and wherein the fourth point in time (t 4 ) corresponds to the end of the transition period. 
         [0018]    According to an exemplary embodiment, the method comprises of: determining on the basis of the measured second quantity at least two voltage values for the voltage across the capacitor at respectively a second and a fourth point in time (t 2 , t 4 ) of the successive points in time in said part of the period; which second and fourth point in time are located in a transition period during which the first switching element switches; and calculating the parasitic resistance on the basis of at least the two voltage values. According to an exemplary embodiment the parasitic resistance (R ESR ) is calculated as 
         [0000]        R   ESR =abs( U   4   −U   2 )/( I   OUT   +I   L ) 
         [0000]    wherein U 4  and U 2  are respectively the two voltage values at the fourth and second points in time (t 4 , t 2 ), I OUT  is the average current through the resistive load during the transition period and I L  is the maximum or minimum input current in the DC-DC converter depending on whether the capacitor switches from discharge to charge or vice versa; wherein the second point in time (t 2 ) corresponds to the beginning of the transition period, and wherein the fourth point in time (t 4 ) corresponds to the end of the transition period. 
         [0019]    In an alternative embodiment, which is particularly advantageous when the parasitic inductance (L ESL ) is small and the parasitic inductances of the measurement circuit itself and the parasitic capacitance of the non-ideal first and second switches are non negligible, the method may comprise determining on the basis of the measured second quantity an oscillation frequency for the voltage across the capacitor between respectively a third and a fourth point in time (t 3 , t 4 ) of the successive points in time in said part of the period; which third and fourth points in time are located in a transition period during which the first switching element switches; and calculating the parasitic inductance on the basis of the measured oscillation frequency. According to an exemplary embodiment the parasitic inductance (L ESL ) may be determined using the equation: 
         [0000]    
       
         
           
             
               f 
               osc 
             
             = 
             
               1 
               
                 2 
                  
                 π 
                  
                 
                   
                     
                       ( 
                       
                         
                           L 
                           par 
                         
                         + 
                         
                           L 
                           ESL 
                         
                       
                       ) 
                     
                     · 
                     
                       C 
                       par 
                     
                   
                 
               
             
           
         
       
     
         [0000]    wherein f osc  is the measured oscillation frequency, L par  is the parasitic inductance of a measurement circuit including the DC-DC convertor, and C par  the parasitic capacitance of the non-ideal first and second switches. The parasitic capacitance (C par ) of the non-ideal switches may be measured using any known technique, and the parasitic inductance (L par ) of the measurement circuit may be determined by measuring first a known reference capacitor using the same measurement circuit and measuring the oscillation frequency f oscref  to determine the parasitic inductance (L par ) using 
         [0000]    
       
         
           
             
               f 
               oscref 
             
             = 
             
               
                 1 
                 
                   2 
                    
                   π 
                    
                   
                     
                       
                         ( 
                         
                           
                             L 
                             par 
                           
                           + 
                           
                             L 
                             ESLref 
                           
                         
                         ) 
                       
                       · 
                       
                         C 
                         par 
                       
                     
                   
                 
               
               . 
             
           
         
       
     
         [0020]    On the basis of the determined values for the parasitic inductance (L par ) of the measurement circuit and the parasitic capacitance (C par ), the parasitic inductance (L ESL ) can be calculated using the equation above for f osc  and the measured value of the oscillation frequency f osc . In other words, by using the oscillation frequency f oscref  of a reference set-up and the oscillation frequency f osc  of the set-up with the capacitor under test, the parasitic inductance (L ESL ) can be determined. 
         [0021]    In a preferred embodiment said part of the period comprises a first part in which the capacitor is discharged in the resistive load, and a second part in which the capacitor is charged via the DC-DC converter. 
         [0022]    According to a second aspect of the invention, a computer program is provided which has computer instructions for performing at least the calculation steps of the method of any of the foregoing embodiments. According to yet another aspect, a storage medium is provided on which computer instructions are stored for performing at least the calculation steps of the method of any of the foregoing embodiments. 
         [0023]    According to a third aspect of the invention, a system is provided for calculating model parameters for at least one coil to be modelled, the system comprising: a DC to DC converter with at least a first switching element and a capacitor to be modelled incorporated therein; which DC to DC converter has input terminals and output terminals; a resistive load between the output terminals of the DC to DC converter; a voltage source connected for the purpose of providing an input voltage to the input terminals of the converter; control means for controlling the first switching element in accordance with a frequency and duty cycle in order to obtain a current varying periodically in time through the capacitor to be modelled, which current depends at least for a part of a period on the input voltage; first measuring means for measuring at least a first quantity representative of the current through the capacitor at successive points in time in at least said part of a period; second measuring means for measuring at least a second quantity representative of the voltage across the capacitor at successive points in time in at least said part of a period; computer means for determining on the basis of the measured first quantity at least one current value for the current through the capacitor; for determining on the basis of the measured second quantity at least one voltage value for the voltage across the capacitor; and for calculating model parameters of the capacitor on the basis of the determined voltage values. 
         [0024]    According to a preferred embodiment, the computer means are further configured to calculate a capacitance and at least one of the following: a parasitic inductance intended to be connected in series to the capacitance, a parasitic resistance intended to be connected in series to the capacitance, and a loss power. 
         [0025]    The system preferably further comprises: measuring means for measuring a quantity representative of the current through the resistive load at successive points in time in at least said part of a period. 
         [0026]    In a preferred embodiment of the system the DC to DC converter comprises a coil and a second switching element which are arranged such that in the coil the current builds up in the coil in a first position of the first switching element, and that in the coil the current falls away in the coil in a second position of the first switching element. In such an embodiment it is possible, instead of or in addition to the measuring means for measuring the current through the resistive load, to also provide measuring means for measuring a quantity representative of the current through the coil at successive points in time in at least said part of a period. The capacitor is preferably connected in parallel to the resistive load. The DC-DC converter of the system is preferably configured to display at least one of a boost converter behaviour and a buck converter behaviour. 
         [0027]    According to an exemplary embodiment, the computer means are configured: to determine on the basis of the measured second quantity at least a first and second voltage value for the voltage across the capacitor at respectively a first and a second point in time (t 1 , t 2 ) of the successive points in time, which first and second points in time are preferably chosen during discharge of the capacitor in the resistive load; and to calculate the capacitance of the capacitor on the basis of at least the first and second voltage value, the time difference between the first and second points in time (t 1 , t 2 ) and the resistance of the resistive load. According to a further exemplary embodiment, the computer means are configured to calculate the loss power as an integral of the product of the voltage across the capacitor and the current through the capacitor on the basis of the measurements of the first and second quantity at the successive points in time, wherein the successive points in time preferably cover a substantially complete period. 
         [0028]    According to an exemplary embodiment, the computer means are configured: to determine on the basis of the measured second quantity at least a third and fourth voltage value for the voltage across the capacitor at respectively a third and a fourth point in time (t 3 , t 4 ) of the successive points in time in said part of the period; which third and fourth points in time are located in a transition period during which the first switching element switches; to calculate the parasitic inductance on the basis of at least the third and fourth voltage value. According to an exemplary embodiment the parasitic inductance (L ESL ) is calculated as 
         [0000]        L   ESL =abs( U   4   −U   3 ) t   trans /( I   OUT   +I   L ) 
         [0000]    wherein U 4  and U 3  are respectively the third and fourth voltage value, t trans  is the transition period, I OUT  is the average current through the resistive load during the transition period and I L  is the maximum or minimum input current in the DC-DC converter depending on whether the capacitor switches from discharge to charge or vice versa; wherein the third point in time (t 3 ) is chosen as a time at which the voltage value is maximal or minimal depending on whether the capacitor switches from discharge to charge or vice versa, and wherein the fourth point in time (t 4 ) corresponds to the end of the transition period. 
         [0029]    According to an exemplary embodiment, the computer means are configured: to determine on the basis of the measured second quantity at least two voltage values for the voltage across the capacitor at respectively a second and a fourth point in time (t 2 , t 4 ) of the successive points in time in said part of the period; which second and fourth point in time are located in a transition period during which the first switching element switches; and to calculate the parasitic resistance on the basis of at least the two voltage values. According to an exemplary embodiment the parasitic resistance (R ESR ) is calculated as 
         [0000]        R   ESR =abs( U   4   −U   2 )/( I   OUT   +I   L ) 
         [0000]    wherein U 4  and U 2  are respectively the two voltage values at the fourth and second points in time (t 4 , t 2 ), I OUT  is the average current through the resistive load during the transition period and I L  is the maximum or minimum input current in the DC-DC converter depending on whether the capacitor switches from discharge to charge or vice versa; wherein the second point in time (t 2 ) corresponds to the beginning of the transition period, and wherein the fourth point in time (t 4 ) corresponds to the end of the transition period. 
         [0030]    According to a fourth aspect, the invention relates to a model for a capacitor calculated according to the method of any of the above described embodiments or making use of a system according to any of the above described embodiments. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0031]    The invention will be further elucidated on the basis of a number of by no means limitative exemplary embodiments of the method and the system according to the invention with reference to the accompanying drawings, in which: 
           [0032]      FIG. 1  is a schematic view of an embodiment of a system according to the invention; 
           [0033]      FIG. 2  is a flow diagram illustrating the measuring steps of an embodiment of the method according to the invention; 
           [0034]      FIG. 3  illustrates a model for a capacitor; 
           [0035]      FIG. 4  shows a first embodiment of a measurement setup according to the invention in which a boost converter is used as DC-DC converter; 
           [0036]      FIG. 5  is a graph showing schematically the current i L  (t) through the coil Lboost, the voltage u L  (t) across the coil Lboost, the current i C  (t) through the capacitor C and the voltage u C  (t) across the capacitor C for the embodiment of  FIG. 4 ; 
           [0037]      FIGS. 5A and 5B  show schematic detail views of the graph of  FIG. 5 ; 
           [0038]      FIGS. 6-21  show other possible embodiments of the measurement setup. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0039]    A first embodiment of a system and method according to the invention will now be illustrated with reference to  FIGS. 1 and 2 . The system comprises a DC to DC converter  1  with a first switching element  2 . Capacitor  3  for modelling is added to DC to DC converter  1 . Converter  1  has input terminals  4   a ,  4   b  and output terminals  5   a ,  5   b . Between output terminals  5   a ,  5   b  capacitor  3  is connected in parallel to a resistive load  9  with an adjustable resistance R L . An adjustable voltage source  7  is further provided for the purpose of supplying an input voltage U in  at input terminals  4   a ,  4   b  of the converter. Control means (not shown) are provided for the purpose of supplying a signal Φ for controlling first switching element  2  at a frequency f sw  and a duty cycle δ. Further provided are measuring means  8   a ,  8   b ,  8   c  for measuring the voltage u C  across the capacitor, the current i C  through the capacitor, the voltage u OUT  across the load R L  and the current i OUT  through the load R L . Note that it is not essential to measure u OUT  since in theory it is equal to u C . It is however advantageous for control purposes to measure u OUT . Measuring means  8   a ,  8   b  are preferably configured to measure the voltage across the capacitor u C (t) and the current through the capacitor i C (t) at successive points in time covering a number of periods T=1/f sw . Note that it is possible that measuring means  8   a ,  8   b  do not measure u C (t) and i C (t) directly, but measure other quantities representative of respectively u C  and i C . A computer means  19  is further provided for calculating model parameters of capacitor C, such as P LOSS , C TEST , L ESL , R ESR , R leak . 
         [0040]    Following assembly of the measurement setup of  FIG. 1  the limits have to be determined for input parameters U in , f sw , δ and R L  in order to define the measurement range, see step  20  of  FIG. 2 . In a subsequent step  21   a  value is set for U in , f sw  and δ on the basis of the defined measurement range, and in a second step  22  the resistance R L  of the load is set. Verification then takes place as to whether the DC-DC converter circuit is operating in a Discontinuous Current Mode (DCM) or in a Continuous Current Mode (CCM). In the embodiment illustrated in  FIG. 2  measurements are performed only in the CCM mode. If it is determined that the circuit is in a DCM mode, the input parameters are modified in steps  21  and/or  22 . Note however that it is also possible to apply the method according to the invention when the converter is in a DCM mode. 
         [0041]    Following the measurement of u L , i L , i OUT , u OUT  in step  24 , the input parameters are modified in steps  21  and/or  22 . The skilled person will appreciate that it is possible to proceed here in many different ways, and that for instance the input voltage U in  can first be varied while the other input parameters f sw , δ and R L  can be kept constant, after which f sw  and/or δ can be varied, and finally R L . Other sequences likewise fall within the scope of the invention. The measured values are employed in a step  25  to calculate model parameters of capacitor C, such as P LOSS , C TEST , L ESL , R ESR , R leak .  FIG. 3  illustrates a possible model for the capacitor assembled from a parallel circuit of a loss resistance R leak  and of a series circuit of a capacitance C TEST , a parasitic inductance L ESL , a parasitic resistance R ESR . 
         [0042]    According to the first variant as illustrated in  FIG. 4 , the DC to DC converter is a boost converter with a coil  10  (Lboost), an input capacitor  11  (Cdec), a first switching element  2  and a coupled second switching element  12  which is connected in series to coil  10 . Coil  10  is connected between a first input terminal  4   a  and the second switching element  12 . First switching element  2  is connected between a second input terminal  4   b  and the connection between coil  10  and second switching element  12 . The other terminal of second switching element  12  is connected to an output terminal  5   a . A capacitor  3  (C) to be modelled is inserted between output terminals  5   a  and  5   b  in parallel with a resistive load R L . 
         [0043]    The inductance of coil  10  is preferably larger than 500 μH (microH). In standard coils of this size the number of windings is very high, resulting in an interaction between the large number of windings on a magnetic core and the parasitic resistance and inter-winding capacitances thereof. In embodiments of the invention coil  10  is judiciously chosen in order to minimize the parasitic resistance and inter-winding capacitances. 
         [0044]    Provided for the purpose of measuring the current i C  through capacitor  3  are measuring means  8   a  which consist in the example of  FIG. 4  of a measuring transformer Tr with a primary winding which is connected in series to capacitor  3 , and an oscilloscope for measuring the current through the secondary winding of Tr. Measuring means  8   b  are provided for the purpose of measuring the voltage u C  across capacitor  3 . Measuring means  8   c ,  8   d  are further provided for measuring the current I OUT  (by means of a small resistance Rsen in series with resistive load  9  ) and the voltage U OUT . Resistive load  9  is preferably connected in series to a choke coil for blocking high-frequency AC currents, while low-frequency and DC currents are allowed through. According to a variant, measuring means (not shown) can also be provided, instead of or in addition to measuring means  8   d , for the purpose of measuring the current i L  through coil  10  and the voltage u L  across coil  10 . 
         [0045]      FIG. 5  illustrates schematically typical measuring results for i L , u L , i C  and u C  as a function of time. This schematic graph shows a linear current progression i L , while the skilled person will appreciate that this progression is typically exponential. The voltage progression u L  is further shown schematically as a block wave, and the skilled person will appreciate that the voltage across the coil Lboost is not wholly constant during charging (t on , switch SW 1  closed and SW 2  open) and discharging (t off , switch SW 1  open and SW 2  closed) of the coil. The current i L  through the coil Lboost varies between a minimum value I Lmin  and a maximum value I Lmax . During charging the voltage across the coil u L  is equal to U in  and during discharge u L  is equal to U in −u OUT , wherein u OUT  is the voltage across load  9 . 
         [0046]    For the embodiment of  FIG. 5  the loss power can be calculated on the basis of the following formula: 
         [0000]    
       
         
           
             
               P 
               loss 
             
             = 
             
               
                 1 
                 T 
               
               · 
               
                 
                   ∫ 
                   0 
                   T 
                 
                  
                 
                   
                     
                       
                         i 
                         C 
                       
                        
                       
                         ( 
                         t 
                         ) 
                       
                     
                     · 
                     
                       
                         u 
                         C 
                       
                        
                       
                         ( 
                         t 
                         ) 
                       
                     
                   
                    
                   
                       
                   
                    
                   
                      
                     t 
                   
                 
               
             
           
         
       
     
         [0000]    Wherein T is the period (T=t on +t off =1/f sw ), i C (t), i C (t) is the current measured through the capacitor and u C (t) is the voltage measured across the capacitor at successive points in time t. 
         [0047]    The capacitance C TEST  can be calculated on the basis of at least one first and second voltage value for the voltage u C  across the capacitor at respectively a first and a second point in time (t 1 , t 2 ), for instance at the beginning and the end of discharge of capacitor  3  in resistive load  9 , i.e. at the beginning and the end of t on (t on =t 2 −t 1 ), see  FIG. 5  and  FIG. 5A : 
         [0000]    
       
         
           
             
               C 
               TEST 
             
             = 
             
               
                 - 
                 
                   ( 
                   
                     
                       t 
                       2 
                     
                     - 
                     
                       t 
                       1 
                     
                   
                   ) 
                 
               
               
                 
                   R 
                   L 
                 
                  
                 
                   ln 
                    
                   
                     [ 
                     
                       
                         
                           u 
                           C 
                         
                          
                         
                           ( 
                           
                             t 
                             2 
                           
                           ) 
                         
                       
                       
                         
                           u 
                           C 
                         
                          
                         
                           ( 
                           
                             t 
                             1 
                           
                           ) 
                         
                       
                     
                     ] 
                   
                 
               
             
           
         
       
     
         [0048]    The parasitic inductance L ESL  can be calculated on the basis of at least a third and fourth voltage value for the voltage across the capacitor at respectively a third and a fourth point in time t 3 , t 4 . The third and fourth point in time are preferably chosen at the beginning and the end of a transition period following switching of first switch  2  (SW 1  ). If a transition period from t on  to t off  is used, t 3  then preferably coincides with the highest value for u C  during this transition period and t 4  with the minimum of u C  before the capacitor begins to recharge, see  FIG. 5A . The parasitic inductance (L ESL ) can then be calculated as 
         [0000]        L   ESL   =U   ESL   *t   trans /( I   OUT   +I   Lmax ) 
         [0000]    wherein t trans  is the duration of the switching transition period of a real switch SW 1  at the transition from t on  to t off , I Lmax  is the maximum value of the current i L  through boost coil  10  and I OUT  is the average value of the current i OUT  during the switching transition period. In the example of  FIG. 5A  t trans =t 4 −t 2 ), and U ESL =u C (t 3 )−u C (t 4 ). 
         [0049]    If a transition period from t off  to t on  is used, t 3 ′ then preferably coincides with the lowest value for u C  during this transition period and t 4 ′ with the maximum of u C  before the capacitor begins to discharge again, see  FIG. 5B . The parasitic inductance (L ESL ) can then be calculated as 
         [0000]        L   ESL   =U   ESL   *t   trans ′/( I   OUT   +I   Lmin )
 
         [0000]    wherein t trans ′ is the duration of the switching transition period of a real switch SW 1  at the transition from t on  to t off , I Lmin  is the minimum value of the current i L  through boost coil  10 , and I OUT  is the average value of the current i OUT  during the switching transition period t trans ′. In the example of  FIG. 5B  t trans ′=t 4 ′−t 2 ′), and U ESL =u C (t 4 ′)−u C (t 3 ′). 
         [0050]    In an alternative embodiment, which is particularly advantageous when the parasitic inductance (L ESL ) is small and the parasitic inductances of the measurement circuit itself and the parasitic capacitance of the non-ideal switches are non negligible, the parasitic inductance (L ESL ) may be determined as follows. First, a measurement is performed with a known reference capacitor having a negligible or known parasitic inductance (L ESLref ). Because of the presence of parasitic inductances (L par ) of the measurement circuit and the parasitic capacitance (C par ) of the non-ideal switches, the voltage u C (t) will oscillate between t 3  and t 4 , and possibly also after t 4  in  FIG. 5A . This oscillation frequency f oscref  is measured. Assuming that the parasitic inductance (L ESLref ) of the reference capacitor is negligible, the oscillation frequency will be equal to: 
         [0000]    
       
         
           
             
               f 
               oscref 
             
             = 
             
               1 
               
                 2 
                  
                 π 
                  
                 
                   
                     
                       L 
                       par 
                     
                     · 
                     
                       C 
                       par 
                     
                   
                 
               
             
           
         
       
     
         [0051]    The parasitic capacitance (C par ) of the non-ideal switches may be measured using any known technique, so that the equation above will allow one to calculate the parasitic inductance (L par ) of the measurement circuit. 
         [0052]    Next, a measurement is performed with the capacitor C under test having a parasitic inductance (L ESL ). Because of the presence of the parasitic inductance (L ESL ), the parasitic inductances (L par ) of the measurement circuit and the parasitic capacitance (C par ) of the non-ideal switches, the voltage u C (t) will oscillate between t 3  and t 4 , and possibly also after t 4  in  FIG. 5A . This oscillation frequency f osc  is measured. The oscillation frequency will be equal to: 
         [0000]    
       
         
           
             
               f 
               osc 
             
             = 
             
               1 
               
                 2 
                  
                 π 
                  
                 
                   
                     
                       ( 
                       
                         
                           L 
                           par 
                         
                         + 
                         
                           L 
                           ESL 
                         
                       
                       ) 
                     
                     · 
                     
                       C 
                       par 
                     
                   
                 
               
             
           
         
       
     
         [0053]    Since the parasitic inductances (L par ) of the measurement circuit and the parasitic capacitance (C par ) are known, see above, the parasitic inductance (L ESL ) can be calculated using the equation above and the value of the measured oscillation frequency f osc . In other words, by comparing the oscillation frequency f oscref  of a calibrated set-up with the oscillation frequency f osc  of the set-up with the capacitor under test, the parasitic inductance (L ESL ) can be determined. 
         [0054]    The parasitic resistance R ESR  can be calculated on the basis of at least the third and second voltage value for the voltage u C  across the capacitor at respectively the third and the second point in time t 3 , t 2 . If a transition period from t on  to t off  is used, t 3  then preferably coincides with the highest value for u C  during this transition period and t 2  with the minimum of u C  at the end of discharging, just before switching, see  FIG. 5A . The parasitic resistance (R ESR ) can then be calculated as 
         [0000]        R   ESR   =U   ESR /( I   OUT   +I   Lmax ) 
         [0000]    wherein I Lmax  is the maximum value of the current i L  through boost coil  10 , and I OUT  is the average value of the current i OUT  during the switching transition period t trans . In the example of  FIG. 5A  U ESR =u C (t 3 )−u C (t 2 ). 
         [0055]    If a transition period t trans ′ from t off  to t on  is used, t 3 ′ then preferably coincides with the lowest value for u C  during this transition period and t 2 ′ with the maximum of u C  at the end of charging, just before switching, see  FIG. 5B . The parasitic resistance (R ESR ) can then be calculated as 
         [0000]        R   ESR   =U   ESR /( I   OUT   +I   Lmin ) 
         [0000]    wherein I Lmin  is the minimum value of the current i L  through boost coil  10 , and I OUT  is the average value of the current i OUT  during the switching transition period t trans ′. In the example of  FIG. 5B  U ESR =u C (t 2 ′)−u C (t 3 ′). 
         [0056]    In order to determine the leakage resistance R leak  a third switching element (not shown) can be provided in series with capacitor  3 . This third switching element is normally closed and does not affect the above discussed measurements. In order to determine the leakage resistance the capacitor can be charged to a determined voltage, for instance a voltage u C (t 5 ) at point in time t 5 . At t 5  the third switching element is then opened for a period (t 6 −t 5 ) and at t 6  the voltage across capacitor u C (t 6 ) is measured again. The leakage resistance R leak  can then be determined on the basis of the following formula: 
         [0000]    
       
         
           
             
               R 
               leak 
             
             = 
             
               
                 - 
                 
                   ( 
                   
                     
                       t 
                       6 
                     
                     - 
                     
                       t 
                       5 
                     
                   
                   ) 
                 
               
               
                 
                   C 
                   TEST 
                 
                  
                 
                   ln 
                    
                   
                     [ 
                     
                       
                         
                           u 
                           C 
                         
                          
                         
                           ( 
                           
                             t 
                             6 
                           
                           ) 
                         
                       
                       
                         
                           u 
                           C 
                         
                          
                         
                           ( 
                           
                             t 
                             5 
                           
                           ) 
                         
                       
                     
                     ] 
                   
                 
               
             
           
         
       
     
         [0057]      FIGS. 6-12  illustrate other variants of DC-DC converters which can be used in embodiments of the invention.  FIG. 6  is a buck converter. In such a converter the current i C (t) through the capacitor has a substantially triangular progression. Depending on the type of capacitor to be modelled and/or the applications for which the capacitor is intended, such a buck converter will optionally be preferred to the use of a boost converter. 
         [0058]      FIG. 7  is a buck-boost converter. In such a converter the current i C (t) through the capacitor has a progression similar to the current i C (t) through the capacitor of a boost converter.  FIG. 8  is a non-inverting buck-boost converter. Such a converter will allow both a substantially block-shaped and a substantially triangular progression of the current i C (t) to be brought about through the capacitor, whereby the modelling can take place even more accurately. 
         [0059]      FIG. 9  is a series resonant converter. With such a converter two capacitors C 1  and C 2  can be modelled simultaneously. This converter allows very sharp discontinuous current peaks to be generated in C 2  and large sine amplitudes in C 1 , whereby capacitors can be modelled in a wide field of applications. 
         [0060]      FIG. 10  is a fly-back converter. The operation hereof is largely the same as the operation of a boost converter, with the difference that due to the presence of a transformer the turns ratio thereof can be selected such that high voltages are generated. Such a converter is particularly suitable for modelling high-voltage capacitors.  FIG. 11  is a full bridge converter. The operation of this converter is largely the same as the operation of a buck converter, with the difference that due to the presence of a transformer the turns ratio thereof can be selected such that high voltages are generated. Such a converter is particularly suitable for modelling high-voltage capacitors. 
         [0061]      FIG. 12  is a multi-boost converter.  FIG. 13  is a multi-buck converter. The converters of  FIGS. 12 and 13  allow very complex current and voltage progressions to be generated in capacitor C and high currents to be generated in capacitor C. Such a converter is particularly suitable for modelling high-power capacitors. 
         [0062]      FIG. 14  is a buck square converter. With such a converter two capacitors C 1  and C 2  can be modelled simultaneously, wherein C 1  is subject to a typical boost converter operation and C 2  to a typical buck converter operation.  FIG. 15  is a cuk converter. With such a converter two identical capacitors C can be modelled simultaneously, wherein the first C is subject to a typical boost converter operation and the second C to a typical buck converter operation. 
         [0063]      FIG. 16  is a sepic converter (single-ended primary-inductor converter). With such a converter two identical capacitors C can be modelled simultaneously, wherein the first C is subject to a typical buck converter operation and the second C to a typical boost converter operation.  FIG. 17  is a three level converter. With such a converter two capacitors C 1  and C 2  can be modelled simultaneously, wherein C 1  is subject to a typical boost converter operation and C 2  to a typical buck converter operation.  FIG. 18  is a reverse sepic converter. With such a converter two capacitors C 1  and C 2  can be modelled simultaneously, wherein C 1  is subject to a typical buck converter operation and C 2  to a typical boost converter operation. 
         [0064]      FIG. 19  is a push-pull converter. Due to the presence of a transformer the turns ratio hereof can be selected such that high voltages are generated. Such a converter is particularly suitable for modelling high-voltage capacitors. 
         [0065]      FIG. 20  is a bridge converter. This converter displays a behaviour more or less the same as the behaviour of a buck converter.  FIG. 21  is a current-fed bridge converter. This converter displays a behaviour more or less the same as the behaviour of a boost converter. 
         [0066]    Since the measurement and calculation principles are the same as those which have been described with reference to  FIGS. 1-5 , they will not be further elucidated. 
         [0067]    As example of the method according to the invention, a commercial capacitor was modelled using the method according to the invention. The manufacturer states as model parameters C TEST =10 uF@50V, R ESR =100 m Ohm. This capacitor was then measured using an embodiment of the method according to the invention. The results were as follows: C TEST =4.3 uF, R ESR =543 m Ohm, L ESS =16.4 nH@ 50V, 1 MHz, I ripple =I Cmax −I Cmin =0.5 A, duty-cycle=50%. This demonstrates that the existing models will not produce good results in circuit simulations, in contrast to capacitors modelled according to an embodiment of the method according to the invention. The capacitors are after all never used at 0 Hz (DC), but typically at significantly higher frequencies. 
         [0068]    The invention is not limited to the above described exemplary embodiments, and the skilled person will appreciate that many changes and modifications can be envisaged within the scope of the invention, which is defined solely by the following claims.