Abstract:
First and second transconductance amplifier input stages having first and second gain characteristics, respectively, are combined. The resulting combined input stage has a third gain characteristic with a linear range that is larger than a linear range of either of the first and second gain characteristics.

Description:
FIELD 
       [0001]    The present work relates generally to transconductance amplifiers and, more particularly, to the input stage of a transconductance amplifier. 
       BACKGROUND 
       [0002]    A transconductance (Gm) amplifier generates an output current as a function of the difference between two input voltages. An input stage, such as a differential transistor pair or a class AB circuit, produces a pair of currents in response to the input voltages. A second (output) stage, such as a current mirror, generates an output current equal (or proportional) to the difference between the pair of currents. 
         [0003]    The large signal gain of a transconductance amplifier with a differential pair input stage has a limited linear range, and flattens out substantially as the input voltage difference becomes large. The large signal gain with a class AB input stage has a limited linear range, and increases substantially as the input voltage difference becomes large. It is known that the linear range of either of the aforementioned amplifiers may be substantially increased by providing degeneration resistors in the input stage. However, the gain itself is reduced when the degeneration resistors are present. Other solutions use FETs instead of bipolar transistors in the differential pair or class AB circuit. This improves the linearity of the amplifier gain but, again, at the cost of reduced gain. 
         [0004]    It is desirable in view of the foregoing to provide for increasing the linear range of a transconductance amplifier without reducing its gain. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  diagrammatically illustrates a transconductance amplifier input stage according to example embodiments of the present work. 
           [0006]      FIGS. 2 and 3  illustrate gain characteristics of respective constituent components of the input stage of  FIG. 1 . 
           [0007]      FIG. 4  illustrates a gain characteristic of the input stage of  FIG. 1 . 
           [0008]      FIG. 5  diagrammatically illustrates a transconductance amplifier according to example embodiments of the present work. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The present work recognizes that the linear range of a transconductance amplifier may be increased, without suffering gain reduction, by providing an input stage that combines characteristics of the differential pair and class AB input stages.  FIG. 1  diagrammatically illustrates a transconductance amplifier input stage  15  according to example embodiments of the present work. In the example of  FIG. 1 , the input stage  15  includes a conventional differential pair input stage  11 , suitably coupled (as shown by broken line) to a conventional class AB input stage  13 . In the example of  FIG. 1 , the constituent input stages  11  and  13  are implemented with bipolar transistors. The input voltage nodes V 1  of the respective input stages  11  and  13  are connected. Likewise, the input voltage nodes V 2  are connected, the drains  16  and  17  are connected, the drains  18  and  19  are connected, and the negative power supply nodes V− are connected. The pair of currents produced by the combined input stage  15  are shown at I 1  and I 2 . Positive power supply nodes are shown at V+. 
         [0010]    The conventional differential pair  11  includes transistors  70  and  71  connected as shown to a current source  81 , and connected as shown to nodes  17  and  18 , respectively. The V 1  input is connected as shown to control transistor  70 , and the V 2  input is connected as shown to control transistor  71 . The current source  81  is connected as shown to V− and transistors  70  and  71 . 
         [0011]    The conventional class AB stage  13  includes transistors  72 - 79 . Transistors  72  and  77  are connected as shown in series between node  16  and V−. Transistors  73  and  76  are connected as shown in series between node  18  and V−. Transistors  74  and  75  are connected as shown in series between a current source  82  and V−. Transistors  78  and  79  are connected as shown in series between a current source  83  and V−. The V 1  input is connected as shown to control transistors  75  and  76 , and the V 2  input is connected as shown to control transistors  77  and  79 . The current source  82  is connected as shown to V+ and transistors  72  and  74 . The current source  83  is connected as shown to V+ and transistors  73  and  78 . 
         [0012]    Considering now the differential pair circuit  11  alone, its large signal equation is shown in  FIG. 2 . In  FIG. 2 , Iout is the difference between the pair of drain currents at nodes  17  and  19  in  FIG. 1  when the circuit  11  is considered alone. Also in  FIG. 2 , the current Ib is the bias current, ΔV IN =V 1 -V 2 , and V T  is thermal voltage (approximately 26 mV at room temperature). The gain of the differential pair circuit  11  alone, shown graphically at  21  in  FIG. 2 , has a linear range generally centered around ΔV IN =0, and flattens out substantially for larger ΔV IN , as previously described. That is, the gain  21  loses its linear characteristic for larger ΔV IN . 
         [0013]    Considering now the class AB circuit  13  alone, its large signal equation is shown in  FIG. 3 , together with its gain shown graphically at  31 . In  FIG. 3 , Iout is the difference between the pair of drain currents at nodes  16  and  18  in  FIG. 1  when the circuit  13  is considered alone. The gain  31  has a linear range generally centered around ΔV IN =0, and increases substantially for larger ΔV IN , as mentioned previously. That is, the gain  31  loses its linear characteristic for larger ΔV IN . 
         [0014]    The combined input stage  15  of  FIG. 1  combines characteristics of the circuits  11  and  13  to provide a substantial increase in the linear range of the gain (as compared to either circuit  11  or  13  alone) without gain reduction. The large signal equation for combined input stage  15  is shown in  FIG. 4 . In the equation of  FIG. 4 , Iout is I 1 -I 2  in  FIG. 1 , which is the sum of Iout from  FIG. 2  (described above) and Iout from  FIG. 3  (described above). The non-linear portions of the gain characteristics  21  and  31  combine to produce an extension of the linear range (as compared to either gain characteristic  21  or  31 ). The gain characteristic for the combined input stage  15  is shown graphically at  41  in  FIG. 4 . The gain characteristics at  21 ,  31  and  41  in  FIGS. 2-4  are simplified representations provided to illustrate pertinent attributes for purposes of comparison, and should not be understood to illustrate actual performance or simulation data. 
         [0015]    Considering again the differential pair  11  alone, each transistor is operated quiescently at Ib/2. Considering the class AB circuit  13  alone, each transistor is operated quiescently at Ib. In the combined input stage  15 , each transistor is operated quiescently at 3*Ib/2. If gain gm is defined as Iout/ΔV IN , it can be shown that, in the limit as Δ IN →0: 
         [0000]      for circuit  11 , gm=Ib/(2 V T )  (1)
 
         [0000]      for circuit  13 , gm=Ib/V T   (2)
 
         [0000]      for circuit  15 , gm=3*Ib/(2 V T )  (3)
 
         [0016]    Consider an example with a desired gm of 0.001=10 −3  mhos, V T =26 mV, and ΔV IN =V T /2=13 mV. Equations (1)-(3) above may be combined with the respectively corresponding equations of  FIGS. 2-4  to yield: 
         [0000]      for circuit  11 , Gm=Iout/ΔV IN =0.9796746496×10 −3  
 
         [0000]      for circuit  13 , Gm=1.010449367×10 −3  
 
         [0000]      for circuit  15 , Gm=1.00019106×10 −3 .
 
         [0017]    The differential pair  11 , considered alone, thus provides gain 2% below desired, while the class AB circuit  13 , considered alone, provides gain 1% above desired, and the combined input stage 15 provides gain 0.02% above desired. 
         [0018]      FIG. 5  diagrammatically illustrates a transconductance amplifier according to example embodiments of the present work, wherein the combined input stage  15  of  FIG. 1  is coupled, at nodes  16  and  18 , to a second (output) stage  51  that produces the output current Iout. In some embodiments, the stage  51  is a conventional current mirror. In some embodiments, Iout=I 1 -I 2  (see also  FIG. 1 ). 
         [0019]    Although example embodiments of the present work have been described above in detail, this does not limit the scope of the work, which can be practiced in a variety of embodiments.