Abstract:
The method and device include determining by removing N−N, rows from an original generator matrix (G) defining the LDPC code and having N rows and N−M columns for obtaining a generator sub-matrix (G 1 ) having N−M columns and N 1  rows. The method also includes delivering by receiving an input data vector of size N−M and multiplying the input vector with the generator sub-matrix for obtaining the punctured encoded code word.

Description:
FIELD OF THE INVENTION 
   The present invention relates to the field of data communication, and more specifically to the delivering of punctured code words encoded with a Low-Density Parity-Check (LDPC) code. The invention is more particularly, but not exclusively, directed to data communication systems utilizing Automatic Repeat Request (ARQ) systems and protocols, and to hybrid ARQ (HARQ) systems. 
   BACKGROUND OF THE INVENTION 
   Low-Density Parity-Check (LDPC) codes were introduced by Gallager in 1962 and rediscovered in 1996 by MacKay and Neal. LDPC codes are also described for example in U.S. Publication 2003/0126551. For a long time they had no practical impact due to their computational and implementation complexity. This changed with advances in microelectronics that led to more computational power at hand for simulation and which now enables implementation. Due to their excellent error correction performance they are considered for future telecommunication standards. 
   An LDPC code is a linear block code defined by its sparse×N parity check matrix H. It contains j ones per column and k ones per row, called row and column degree respectively. A (j,k)-regular LDPC code has row and column degree of uniform weight, otherwise the code is called irregular. A parity check code can be represented by a bipartite graph. The M check nodes correspond to the parity constraints, the N variable nodes represent the data symbols of the codeword. An edge in the graph corresponds to a one in the parity check matrix. 
   In the LDPC code encoder the packet to encode of size (N−M) is multiplied with a generator matrix G of size (N−M)×N. This multiplication leads to an encoded vector of length N. The generator matrix G and the parity check matrix H satisfy the relation GH t =0 where 0 is the null matrix. Generally, an LDPC code decoder comprises a decoding module which receives the encoded vector of length N and delivers an intermediate vector of length N by using the parity check H. Then a demapping module extracts from the intermediate vector the decoded vector of length (N−M). 
   More precisely, LDPC codes can be decoded using message passing processes or algorithms, either in hard or soft decision form. The decoding is then an iterative process, which exchanges messages between variable and check nodes. Typically a Belief Propagation (BP) algorithm is used, which exchanges soft-information iteratively between variable and check nodes. The code performance mainly depends on the randomness of the parity check matrix, the codeword size N and the code rate R=(N−M)/N. 
   Many publications describe LDPC decoders and the algorithm implemented therein. An example of such a publication is “VLSI Implementation-Oriented (3,k)-Regular Low-Density Check Codes”, Tong, IEEE Workshop on Signal Processing Systems (SiPs), September 2001. 
   The channel coding part is a very important component in wireless communication systems like UMTS, WLAN and WPAN. Especially in the domain of WLAN and WPAN the latency of the decoding is of a critical importance. Low Density Parity Check codes can be seen as a promising candidate for this kind of systems in the near future. These codes are being used in the future version of DVB-S and in some fiber optical communication systems. More applications will follow in the near future. 
   The codes have some very interesting properties, which make them a natural choice for latency critical application. In a typical wireless system the payload on the wireless channel is fixed by the modulation and the framing structure. To be able to use the wireless channel resources in the most efficient way the data stream needs to be adapted during the coding process to fit into the given constrains. A coding rate adaptation in the channel encoder does this. In existing systems, puncturing and repetition usually perform this adaptation. 
   U.S. Publication 2003/0126551 mentioned above proposes the LDPC codes for ARQ scheme, but in this publication a simple puncturing is used to generate the higher rate codes. The punctured bits are stored in the transmitter and only transmitted when needed. So, the complete codeword has to be generated each time leading to higher power consumption. 
   SUMMARY OF THE INVENTION 
   In view of the foregoing background, it is therefore an object of the present invention to reduce the complexity of an LDPC encoder. 
   Another object of the invention is to avoid modification of the conventional LDPC decoder. 
   Another object of the invention is to provide an additional degree of freedom to the adaptation of the wireless link to the existing link quality and the available wireless channel resources by the use of a rate adaptation of a Low Density Parity Check code. This rate adaptation should be done in a compatible way that means lower coding rates are used as the bases for higher coding rates. In this case only one low rate mother code needs to be used to generate a higher rate child code. The performance of these child codes is in general lower than the performance of the optimized codes for a given code rate but the implementation is much simpler since only one mother code for a set of child codes needs to be implemented. This is of major importance especially in the case of LDPC codes where the encoder is of a significant complexity. 
   Another object of the invention is to provide a method and a device allowing easy generation and implementation of such rate compatible codes. 
   The invention provides a method for delivering punctured code words encoded with a LDPC code. This method comprises: a determining step and a delivering step. In the determining step, N−N 1  rows are removed from an original generator matrix defining the LDPC code, the generator matrix having N rows and N−m columns. Thus, a generator sub-matrix having N−M columns and N 1  rows is obtained. In the delivering step, an input data vector of size N−M is received and the input vector is multiplied with the generator sub-matrix for obtaining the punctured encoded code words. 
   In other words, instead of generating a complete code word and then puncturing out bits to reach a specific target coding rate and thus number of bits, the properties of the LDPC code encoder can be used to generate only the needed bits and thus reducing the complexity of the encoder. More precisely, for a given generator matrix G with (N−M) columns and N rows the coding rate R is equal to (N−M)/N. To increase the coding rate R the number of rows has to be reduced leading to a coding rate R 1 =(N 1 −M)/N 1  where N 1  is smaller than N. By using this mechanism the complexity of the generator sub-matrix can be reduced depending on the needed coding rate. In the decoding process the missing samples are replaced by zero weight soft values. This is similar to the standard puncturing method. The decoder itself will not be changed. 
   According to an embodiment of the invention, the determining step comprises determining a set of generator sub-matrixes having respectively N−M columns and N 1  rows, i being a positive integer greater than or equal to 2. The determination of the generator sub-matrix of rank i+1 having N i+1  rows comprising removing N i −N i+1  rows from the generator sub-matrix of rank i. And the delivering comprises selecting one of the generator sub-matrixes and multiplying the input vector by the selected generator sub-matrix for obtaining the punctured encoded code word. 
   In other words, by removing the rows one by another from the generator matrix, rate compatibility can be guaranteed. The mother code stays unchanged and the resulting code rate can be adapted very easily to the requirements of the wireless channel and the transmission conditions. 
   The same method can be used to generate the needed code words for a hybrid ARQ scheme with incremental redundancy. In a first transmission step only a part of the generator matrix is being used to generate a code word with a given coding rate. In this step only the needed parts of the matrix are used. If it is not possible to decode the packet in the first step, an additional packet will be requested by the receiver. This additional packet will contain incremental information. This incremental information will be generated in the transmitter by using a generator matrix containing only the remaining rows of the overall matrix which have not been used in the first step. Thus additional information is sent to the receiver. This additional information is being combined in the receiver with the already existing soft values. The combined received vector is then used in the next decoding attempt. By splitting the matrix into more than two parts it is easily possible to implement more than two incremental ARQ steps. 
   In other words, according to another embodiment of the invention particularly adapted for delivering punctured code words encoded with a LDPC code for a hybrid ARQ scheme with incremental redundancy comprising successive transmission steps of successive punctured code words, the determining step comprises determining a set of i generator sub-matrixes having respectively N−M columns and N i  rows, i being a positive integer greater than or equal to 2. The N i+1  rows of the generator sub-matrix of rank i+1 are different from the rows of any generator sub-matrix having a rank smaller than I+1. And the delivering step comprises for some successive transmission steps, respectively selecting different generator sub-matrixes and respectively multiplying successive input vectors by the successively selected generator sub-matrixes for obtaining successive punctured encoded code words. 
   The invention also provides a device for delivering punctured code words encoded with a LDPC code, comprising: a generator or generation means for removing N−N 1 , rows from an original generator matrix defining the LDPC code and having N rows and N−M columns for obtaining a generator sub-matrix having N−M columns and N 1  rows; an input or input means for receiving an input data vector of size N−M; and a multiplier or multiplication means for multiplying the input vector with the generator sub-matrix for obtaining the punctured encoded code word. 
   According to an embodiment of the invention, the generation means are adapted to generate a set of i generator sub-matrixes having respectively N−M columns and N i  rows, i being a positive integer greater than or equal to 2. The generation means comprises removing means for removing N i −N i+1  rows from the generator sub-matrix of rank i to obtain the generator sub-matrix of rank i+1 having N i+1  rows. And the device further comprises selecting means for selecting one of the generator sub-matrixes, the multiplication means multiplying the input vector by the selected generator sub-matrix for obtaining the punctured encoded code word. 
   According to another embodiment of the invention adapted for delivering punctured code words encoded with an LDPC code for a hybrid ARQ scheme with incremental redundancy comprising successive transmission steps of successive punctured code words, the generation means are adapted to generate a set of i generator sub-matrixes having respectively N−M columns and N i  rows, i being a positive integer greater than or equal to 2. The N i+1  rows of the generator sub-matrix of rank i+1 are different from the rows of any generator having a rank smaller than i+1. The device further comprises selecting means adapted for some successive transmission steps, to respectively select different generator sub-matrixes. And the multiplication means are adapted to respectively multiply successive input vectors by the successively selected generator sub-matrixes for obtaining successive punctured encoded code words. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other advantages and features of the invention will appear on examining the detailed description of nonlimiting embodiments, and of the appended drawings in which: 
       FIG. 1  is a schematic diagram illustrating a conventional puncturing scheme according to the prior art; 
       FIG. 2  is a schematic diagram illustrating a first embodiment of a device according to the invention; and 
       FIG. 3  is a schematic diagram illustrating another embodiment of a device according to the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In  FIG. 1 , the conventional method of generating a punctured LDPC code is depicted. Here, a data source generates a data stream. This data stream is then multiplied by a generator matrix G defining the LDPC code and having N rows and N−M columns. The resulting code word has a coding rate R equal to (N−M)/N. In a hybrid ARQ scheme using LDPC codes and incremental redundancy a retransmission would only use a part of a punctured out needs from the first transmission. Thus, the punctured block would use a different puncturing sequence which would be orthogonal to the original puncturing sequence. 
   In  FIG. 2 , a first embodiment of a device according to the invention is depicted, and can be used for example in a hybrid ARQ scheme. Here, no separate punctured unit is used. The needed code rate is directly generated by using a sub-matrix of the original G matrix. More precisely, the device DV according to the invention comprises a generator or generation means GEN, a selector or selection means SLT and a multiplier or multiplication means MLT. These means can be for example realized by software within a microprocessor or by an ASIC. Input vectors are received from a data source by an input or input means INP. 
   A first sub-matrix G 1  is generated from the original G matrix by removing N−N 1  rows from the G matrix. During the first transmission period, the sub-matrix G, is selected by the selecting means SLT to be multiplied with an input vector for obtaining a punctured encoded code word. In the case of incremental redundancy, in the second transmission period (first repetition) another sub-matrix is selected to generate an additional set of information symbols. This new sub-matrix G 2 , generated by generation means from the G matrix, now contains N 2  rows and N−M columns, where the N 2  rows are not contained is the sub-matrix G 1 . The resulting code rate R 2  is thus equal to (N−M)/(N 1 +N 2 ) after soft combining in the receiver. 
   In a second repetition step (third-transmission), another sub-matrix would be used if necessary to generate the additional symbols. The sub-matrix G 3  contains N 3  rows and N−M columns, where the N 3  rows are neither contained in the sub-matrix G 1  nor in the sub-matrix G 2 . In the receiver, the different received values from the original transmission and the repetitions are combined and decoded in one process. In other words, the sub-matrix G 1 -G 3  are generated based on the matrix G. In the case of incremental redundancy the matrices G 1 -G 3  do not contain any common rows. 
   Another embodiment of the invention, allowing generation of rate compatible codes is now described with the reference to  FIG. 3 . The generation means GEN are adapted to generate a set of generator sub matrices. In the present example, i is equal to 3. And, the set of generator sub matrices G 1 -G 3  is stored in a memory. The generator sub matrix has N−M columns and rows. The first generator sub-matrix G 1  which has N 1  rows, is determined by removing N−N 1  rows from the mother generator matrix G having N rows. 
   More generally, the determination of the generator sub-matrix G i+1  of rank i+1 which has N i+1  rows, comprises removing N i −N i+1  rows from the generator sub-matrix G i  of rank i. In other words, a generator sub-matrix G i  of rank i contains all rows of the generator sub-matrix G i+1  of rank i+1 and a specific number of additional rows. The selection means SLT is adapted to select one of the generator sub-matrix stored in memory, to multiply the input vector by the selected generator sub-matrix. 
   It is thus possible for example to select one generator matrix and having thus a chosen coding rate R, depending on the transmission channel conditions. Whatever the embodiment of the invention ( FIG. 2  or  FIG. 3 ), although it would be possible to generate all the sub-matrixes and to store them totally in a memory together with the original G matrix, only the original G matrix is preferably stored in a memory of the device DV. And for each sub-matrix G i  the index of the first row and the index of the last row of the sub-matrix G i  within the G matrix are predetermined and stored in the memory or in another memory of the device and the generation means can address a sub-matrix from the G matrix by using the corresponding indexes. And these indexes are selected by the selection means depending on the rank of the repetition step ( FIG. 2 ) or on the transmission channel conditions for example ( FIG. 3 ).