Abstract:
A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to interface traps within MOSFETs, and in particular to a method for measuring interface traps in thin gate oxide MOSFETs. 
       BACKGROUND OF THE INVENTION 
       [0002]    As is known in the art, semiconductor wafers often contain material interfaces such as between silicon and silicon dioxide. Contaminants and other defects at the oxide silicon interface can cause problems in the manufacture and performance of integrated circuits that are fabricated over that interface. These defects, often referred to as interface traps, are capable of trapping and de-trapping charge carriers. Interface traps can have an adverse effect on device performance, for example, an interface trap can cause discrete switching in the source conductance, band-to-band tunneling (BBT) of hot carriers from the gate-to-drain which can result in gate-induced drain leakage current, drain current fluctuation, voltage drop in the gate area, threshold voltage shift in the MOS transistors, and the like. 
         [0003]    For example, impurities such as contaminants, metals, and the like, are often introduced at the oxide layer/semiconductor interface during oxidation processing, plasma deposition, etching or other processing steps. There is a need to determine the quality of these interfaces prior to or during the manufacture of semiconductor devices on the wafer. Interface trap charge pumping is a well-known transient recombination effect that is activated by cycling or pumping the Si—SiO 2  interface of the MOSFET between accumulation and inversion states. Charge-pumping measurements can then be used to extract or determine interface trap density, and the effect of gate leakage can be compensated for by measuring charge-pumping current at a low frequency, for example, and then subtracting it from measurement results at higher frequencies. 
         [0004]    Basic charge-pumping techniques involve measuring the substrate output current while applying input voltage pulses of fixed amplitude, rise time, fall time, and frequency to the gate of the transistor, with the source, drain, and body tied to ground, for example. The electrical pulse can be applied with a fixed amplitude, a voltage base sweep, a fixed base, a variable amplitude sweep, and the like. The charge pumping method can evaluate the surface states at the silicon (Si)—silicon dioxide (SiO 2 ) interface of MOSFET devices, for example. 
         [0005]    The traditional charge pumping technique for characterizing interface traps fails when tunneling current is comparable to or greater than the charge pumping current, as it is difficult to separate the two currents. A-priori estimation of the average gate tunneling current (which is a function of the gate voltage waveform) into the bulk or source/drain of the MOSFET during charge pumping leads to inaccuracies due to the exponential dependence of gate tunneling current on the gate voltage. 
         [0006]      FIG. 1  is a prior art technique setup at  100 , illustrating the application of a square or trapezoidal pulse wave, utilizing a pulse generator  102 , to a gate  104  of a metal oxide semiconductor field effect transistor (MOSFET)  106  that overlies a thin gate oxide  108 . It should be appreciated by one of ordinary skill in the art that the pulse wave can be square or trapezoidal or a linear combination of both. In addition, the pulse wave can be triangular, sinusoidal, rectangular, comb, and the like. As illustrated, a source  110  and drain  112  are both shorted and grounded while measuring the current output at a current measuring device  114 . As a positive or negative bias is applied to the gate  104 , the surface of the MOSFET accumulates or inverts, respectively, and if there are interface traps located at the gate oxide, bulk substrate interface, the traps will tend to go back to either the conduction band or the valence band, depending on the type of traps present. By pulsating the interface traps rapidly, the technique takes advantage of the fact that traps have only a finite response time, therefore only some of the traps will go back to the conduction or valence band. However, some of the traps will remain “trapped” and recombine with the inversion charge or the accumulation charge coming from the bulk. 
         [0007]    There is a substantial current measurement difference between devices, when evaluating an enhanced complementary metal oxide semiconductor (CMOS) as opposed to a MOSFET where they gate dielectric is very thin. Utilizing a thin gate dielectric, if there is an increase in the voltage beyond inversion, or if the device is taken to deep accumulation, that results in a significant amount of gate current. However, this gate current is small, when compared to a normal MOSFET operating current, which is the source/drain current. The current measured is a very small current, many orders of magnitude lower than the normal device current. In an advanced CMOS device, the magnitude of the tunneling current approaches and often exceeds the magnitude of the charge pumping current for the density of interface traps of interest. These values can range from tens to hundreds of picoamps per square micron. 
         [0008]    Thus, there is a need to provide a method for measuring interface traps in thin gate oxide MOSFETs that overcomes the previously mentioned problems. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention is directed to a method for determining charge pumping current to determine the number of interface traps present in a MOSFET. In accordance with one aspect of the present invention, the method comprises plotting charge pumping current versus frequency. The method further comprises determining the number of interface traps participating in the charge pumping current based upon the slope of the plot. In addition, the tunneling current can be determined based upon the y-intercept of the plot for a given duty cycle. 
         [0010]    Two key observations that were made according to an aspect of the invention are that the charge pumping current only occurs at V hi  to V lo  or V lo  to V hi  transitions. In addition, for example, the gate tunneling current to the source/drain or substrate depends only on the duty cycle and not the frequency of the gate pulses, to the first order. The method thus provides a way to separate charge pumping current from tunneling current when tunneling current for the MOSFET is greater than or equal to the charge pumping current. 
         [0011]    Additionally, according to another aspect of the invention, the method provides a way to determine the errors in those calculations and plots as well as to validation of those measurements. 
         [0012]    To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a block diagram of a prior art set up used for conventional charge pumping; 
           [0014]      FIG. 2  is a trapezoidal wave pulse utilized in the charge pumping, in accordance with one aspect of the present invention; 
           [0015]      FIG. 3A  illustrates a trapezoidal charge pumping wave in accordance with yet another aspect of the present invention; 
           [0016]      FIG. 3B  illustrates yet another trapezoidal charge pumping wave at a different frequency than in  FIG. 3A , in accordance with another aspect of the present invention; 
           [0017]      FIG. 4  is a graphical representation of substrate current versus frequency according to another aspect of the present invention; 
           [0018]      FIG. 5  illustrates an experimental result according to one aspect of the present invention; 
           [0019]      FIG. 6  illustrates another experimental result according to one aspect of the present invention; 
           [0020]      FIG. 7  illustrates measurements on various devices according to other aspects of the present invention; 
           [0021]      FIG. 8  illustrates experimental results of tunneling current versus duty cycle according to yet another aspect of the present invention; 
           [0022]      FIG. 9  shows substrate current versus duty cycle according to another aspect of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    The following description of the embodiment below is merely an example and is in no way intended to limit the invention or its application or uses. The present invention discloses a method for measuring interface traps in thin gate oxide MOSFET devices. 
         [0024]    As semiconductor devices get smaller, hot carrier induced degradation of those devices is apt to occur. In order to make the MOSFET devices or Ultra-Large-Scale Integration (ULSI) components more reliable, it is critical to understand and quantify this degradation condition. The technique mentioned supra to accomplish this utilizes a charge pumping method, which is a measurement technique that can evaluate the substrate surface conditions at the Si—SiO 2  interface, for example. 
         [0025]    Turning now to the figures,  FIG. 2  illustrates a trapezoidal wave pulse according to an aspect of the present invention. The interface traps between the Si and SiO 2  layers that recombine with inversion or accumulation charges will constitute a net DC current. In other words, every time that the gate is pulsed from high voltage  202  (V top  or V hi ) to low voltage  204  (V low  or V base ), an ultra short pulse of current will be obtained and can be measured. For example, by pulsing the gate at 100 kHz, or 100,000 times per second, a current is integrated to obtain a finite measured current. This technique is used widely throughout industry and academics to understand interface traps, and MOSFET characteristics, for example. 
         [0026]    In  FIG. 2  the pulse waveform is illustrated, showing at least one complete waveform  200 . The waveform  200  begins at point  206  which represents the leading edge of the waveform  200 , for example. The slope of the line continues traveling up and to the right from  206  until line reaches point  208  where the slope levels out, at the highest voltage  202  (V top  or V hi ). The pulse rise time (t RISE )  210  is often defined as the time it takes to go from the low level voltage  204  to a high-level voltage  202 . In this case the rise time is measured for the entire rise level, however, this value is often measured at  10 % above the low voltage level, at point  212  and at 90% of the high voltage level, at point  214 . The waveform continues along a horizontal path until it reaches point  216 , wherein the line begins to slope downward until it reaches point  218 . 
         [0027]    The slope of the line travels downward and to the right from point  216  until the line reaches point  218  where the slope levels out at the base voltage  204  (V base ). The fall time (t f )  220 , for example, is often defined as the time the pulse takes to go from the high voltage level  202  to the low voltage level  204 . In this case the pulse fall time is in measured for the entire fall distance; however this value can often be represented as the distance from 10% above the low voltage or point  212  to 90% of the high voltage at point  214 . The pulse width is the amount of time a pulse remains at a specific (normally “true”) logic state. This can either be measured from the time between the leading edge at 50% amplitude to the trailing edge at 50% amplitude or as the time from the beginning of the leading edge  206  to the beginning of the trailing edge  216 . The period is how long it takes the waveform measured in seconds to repeat and is also the inverse of the wave frequency. 
         [0028]      FIG. 3A  illustrates a trapezoidal charge pumping signal at  300 , wherein the various regions of the wave form will be described in detail below. A first region,  302  is shown where the voltage is high and represents the region, where tunneling current occurs from the gate into the source/drain. A second region,  304  represents an area where the voltage goes from high to low. The second region  304  is dominated by the charge pumping current from the electron traps. The third region,  306 , which goes from low to high voltage, is dominated by a charge pumping current created from hole traps. Finally, the fourth region,  308  is dominated by the gate tunneling current into the substrate. As clearly demonstrated in the illustration, utilizing only the traditional charge pumping technique, the tunneling current would totally obscure the charge pumping current. 
         [0029]    One aspect of the invention is a method where the gate tunneling current is subtracted out of the summation of the current. The tunneling current has an exponential dependence on the gate to source voltage. Therefore a small error in the estimation of the gate voltage will cause a large error in the tunneling current. What ends up happening is that two large numbers are subtracted in order to wind up with a small number which typically results in a large error (e.g., 100-200%). Ultimately this requires a prior knowledge of the device operation, which is normally not known to a great extent. However, this problem is solved in the present invention by looking at two aspects of the current, the tunneling current and the charge pumping current and understanding what controls or influences each of the two currents. The charge pumping current, as illustrated in  FIG. 3A , only occurs at the edge transitions of the pulse,  304  and  306 , and the tunneling current occurs when the pulse is not in transition,  302  and  308 . Looking at the pulse from a signal standpoint, the tunneling current is controlled by the duty cycle of the pulse and the charge pumping current is determined or influenced by the frequency of the pulse or how many times the pulse cycles from high to low or low to high (transitions). 
         [0030]      FIG. 3B  illustrates an additional trapezoidal charge pumping signal at  350 , where the frequency of the signal  300  in  FIG. 3B  is greater than the frequency of the signal  350  shown in  FIG. 3A . As  FIG. 3B  clearly demonstrates, the charge pumping current regions  324  and  326 , represent a larger percentage of the total current obtained. As seen in  FIG. 3B  the tunneling current regions  322  and  328 , are much smaller than the tunnel current regions,  302  and  308  in  FIG. 3B . This aspect of the present invention indicates that as the frequency of the charge pumping signal increases the charge pumping current increases. 
         [0031]    Accordingly, there are two different mechanisms to vary the charge pumping current and vary the tunneling current and the two mechanisms are uncoupled from each other, as one mechanism is varied the other does not vary to the first order. Therefore, turning to  FIG. 4 , is a graphical representation  400  of substrate current or I SUB  (Amps) plotted on the vertical or y-axis  402  versus frequency in cycles/sec (Hz) plotted on the horizontal or x-axis  404 . The slope of the curve  406  provides the total interface trapped charge, in this example, 5.08 E-15 Coulombs. The y-intercept provides the average tunneling current from the gate to the substrate, for example, 2.56 E-10 amps from EQ. 1. The equations for the linear curve  406  are shown below as EQS. 1 and 2. The parameter R 2 , called the correlation coefficient, is a measure of how closely the variables are correlated together. The closer R 2  approximates a value of 1, the “better the fit”. The R 2  value is actually a property of the data set and not of the line that is drawn by the least squares criterion, for example. In this case, the R 2  value is approximately 1 and there is a very good fit to the data. Consequently,  FIG. 4  shows that the charge pumping current is a function of the frequency of the pulse applied to the device. 
         [0000]        y =5.08  E -15 x +2.56  E -10   (EQ. 1) 
         [0000]      R 2 =9.98 E-01   (EQ. 2) 
       Where: 
       [0000]    
       
         
           
             t r =pulse rise time=100 nanoseconds (ns) 
             t f =pulse fall time=100 nanoseconds (ns) 
             V top =0.6 volts 
             V base =−0.9 volts 
             W/L=10/5 μm 
           
         
       
     
       In estimating D it  (the density of the interface traps) 
       [0037]      ΔE=−2 kT Ln[σ p  σ n    t   r    t   f ) 1/2    v   th    n   i  ( V   t    V   fb ) Va]   (EQ. 3) 
         [0000]      ( V   t   −V   fb )/ V   a ˜1   (EQ. 4) 
       Where: 
       [0000]    
       
         
           
             N it =6.35 E+10/cm 2  (number of interface traps) 
             (σ p  σ n ) 1/2 ˜10 −15  cm 2    
             n i =1.45×10 10  cm −3    
             V th =10 −7  cm/s (thermal velocity of carriers in the semiconductor) 
             t r =t f =10 −7  seconds (pulse rise time and pulse fall time) 
             ΔE˜0.58 eV (Electron Volts) 
             Dit˜Nit/ΔE˜1.1 E+11/eV/cm 2    
             σ p =hole-capture cross-section (cm 2 ) 
             σ n =hole-capture cross-section (cm 2 ) 
             k=Boltzmann&#39;s constant (Joules/Kelvin) 
             T=Absolute temperature (Kelvins) 
             V a =Amplitude (Vhi−Vlo) of the gate pulse (Volts) 
           
         
       
     
         [0050]      FIG. 5  illustrates graphical experiment results at  500  that was performed in order to further validate the present invention. Q CP  measured in Colombes is plotted on a y or vertical axis and voltage (V base ) is plotted on the x or horizontal axis. One of the characteristics of charge pumping current is that if the amplitude of the pulse is varied, the charge pumping pulse will disappear or go to zero. The amplitude of the pulse was varied as illustrated in box  502 , by adjusting V base    504 , while the V top    506  was kept constant at 0.6 V (always greater than the threshold voltage (V t )). The rise time (t r )  508  and the fall time (t f )  510  were both 100 ns. The charge pumping current started out relatively flat until the V base  reached approximately −1.2 V, and then curve progressed downward until it disappears at about −0.5 V. This is typical behavior of what would be seen in traditional charge pumping technique, when plotting this type of curve. Therefore, what is being measuring here utilizing this aspect of the claimed invention, is charge pumping current, and is not an artifact of tunneling current, for example. If this were measuring tunneling current, the tunneling current would not vary at all or only slightly over a given range. 
         [0051]    Another experimental result for the present invention is illustrated in  FIG. 6 , at  600 , for example. In this experiment result, the base voltage (V base )  602  is kept constant, while the voltage (V top )  604 , the voltage at the top of the pulse is adjusted or varied, for example. In this experiment it is expected that the Q CP    606  will saturate when the voltage V top    604  is greater than a threshold voltage, Vt  608 . In this test the voltage, V base    602  is kept at approximately −0.95 V, the rise time (t r )  610  and the fall time (t f )  612  are both set to 100 ns and the W/L ratio is 10/5 μm. Once the amplitude of the pulse (V top )  604  exceeds the threshold voltage (V t )  608  it was anticipated that the charge pumping current would approximately flatten out and referring to the graph in  FIG. 6 , this is clearly the case. 
         [0052]      FIG. 7  illustrates measurements for various devices (See index  702 ) and the number of interface traps (N it ) versus a base voltage (V base ). The devices under test (DUT) range in size from 1 μm to 10 μm. As illustrated in this graph, the number of interface traps is fairly independent of the base voltage. The rise time and the fall time was set at 100 ns and the voltage at the top amplitude (V top ) was set at a constant 0.6 V. 
         [0053]    In another aspect of the invention,  FIG. 8  shows experimental results of tunneling current (I tunneling )  802  plotted on the y-axis (vertical axis) vs. duty cycle  804  plotted on the x-axis (horizontal axis). The tunneling current  802  flowing into the substrate from the gate, for a given duty cycle, is estimated from the y-intercept of a line fitted to the tunneling current versus duty cycle plot at that duty cycle. It can be seen from the R 2  value of approximately one that represents a good linear fit exists which is consistent with the current theory relating to charge pumping. The estimate of tunneling current for this graph is approximately the slope of the line on the left which is 862 pA, for example in this case. 
         [0000]        y =−10 x+ 8.62 E   (EQ. 5) 
         [0000]      R 2 =9.93 E-01   (EQ. 6) 
       Where: 
       [0000]    
       
         
           
             t r =pulse rise time=100 nanoseconds (ns) 
             t f =pulse fall time=100 nanoseconds (ns) 
             V top =0.6 volts 
             V base =−0.9 volts 
             W/L=10/5 
           
         
       
     
         [0059]    Finally in  FIG. 9 , which illustrates charge pumping current versus duty cycle, experimental results are illustrated at  900  which demonstrate the effect of the duty cycle time charge pumping current. In this experiment the width to length ratio is equal to 10/5 (W=10 μm), the rise time and fall time are both set equal to 100 ns, V top  was set equal to 0.6 V and V base  was adjusted equal to −0.95 volts. At the very low duty cycles, less than 20%, the rise and fall times (t r  and t f ) are comparable to the pulse width, therefore the approximations break down at that level. As the duty cycle increases the graph flats out, as anticipated. The Q CP  remains substantially independent of the duty cycle, until the duty cycle exceeds 80%. 
         [0060]    The charge pumping current total charge equation is calculated as: 
         [0000]        Q   CP   =D   it (2)( q )( k )( T ) Ag Ln [(σ p  σ n    t   r    t   f ) 1/2    v   th    n   i   |V   t   −V   fb   |/V   a ]  (EQ. 7) 
       Where: 
       [0000]    
       
         
           
             D it =Density of interface traps 
             q=Electron charge 
             k=Boltzmann&#39;s constant 
             T=Absolute temperature (K) 
             Ag=Gate area of the MOSFET 
             Ln=Natural logarithm 
             σ p =Hole-capture cross-section 
             σ n =Electron-capture cross-section 
             t r =Pulse rise time 
             t f =Pulse fall time 
             v th =Thermal velocity 
             n i =The intrinsic carrier concentration at the temperature of measurement 
             V t =Threshold voltage 
             V fb =Flat-band voltage 
             V a =Amplitude (Vhi−Vlo) of the gate pulse 
           
         
       
     
         [0076]    The component of the gate tunneling current (I tunneling ) that enters or goes into the substrate has a linear frequency dependence and can be a source of error in the Q CP  measurement, for example. The following can be used as an approximation of the tunneling current into the substrate: 
         [0000]        I   tunnel, avg =(1/ T   period )(1 /K   f +1 /K   r )∫( V ) dV +{(1 −DC )−( t   r   +t   f )/2 T   period }|( V   lo )   (EQ. 8) 
       Where: 
       [0000]    
       
         
           
             f=1/T period =frequency of the pulses (cycles/sec); 
             T period =period=the time for one complete cycle (sec); 
             K f =t f /(V hi −-V lo ); 
             K r =t r /(V hi −V lo ); 
             DC=duty cycle=τ/T; 
             τ is the duration a operation (e.g., pulse) is non-zero; 
             I(V)=I substrate  with gate voltage V and source/drain grounded (0 V); 
             t r =pulse rise time; 
             t f =pulse fall time; 
             ∫ I(V) dV is the integral of the substrate current I(V), as function of gate voltage V, with, V ranging from V=V hi  to V=V lo ; 
           
         
       
     
         [0087]    The contribution from I(V hi ) can be ignored, for example, as it is very small (In inversion, the bulk of the gate tunneling current goes to the source/drain terminals and not the substrate). 
         [0088]    For example, the tunneling current has two frequency (f) dependent terms (term 1, [f (1/K f +1/K r )∫ I(V) dV] and term 2, [f l(V lo ) (t r +t f )/2]) and a duty cycle (DC) term. The DC term is the y-intercept of the substrate current (I sub ) versus frequency (f) plot and one of the frequency (f) dependent tunneling current (I tunneling ) terms, I(V lo ) (t r +t f )/2. Therefore, the duty cycle can be calculated using the y-intercept value and the rise and fall times of the trapezoidal pulse, for example. The second term, (1/K f +1/K r )∫I(V) dV, of EQ. 3, can be estimated from the DC I sub  versus gate voltage sweep. In table 1 shown below, the percentage error in Q CP , calculated utilizing the two T period  dependent tunneling current terms, can be calculated for a 5×10 um NMOS device employing 100 nS rise and fall times, a V hi  voltage set at 0.6V, a V lo  of −0.9V and an assumed 5 e 10/cm 2  interface traps (N it ), for example. The measured DC I sub  vs. V gate  data was used to compute ∫ I(V) dV. In this manner, both of the errors, mentioned supra, can be estimated and thus corrected for. 
         [0000]    
       
         
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Nit 
                 q(Nit)(W)(L) 
                 % Error (t r  + t f )/2 
                 % Error ∫ I(V) dV 
               
               
                   
               
             
             
               
                 5.00E+10 
                 4.00E−15 
                 −3.86 
                 0.64 
               
               
                   
               
             
          
         
       
     
         [0089]    Although the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The invention includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”