Abstract:
In a low voltage operation method of a PDP (plasma display panel) and an apparatus thereof capable of maintaining a picture quality and operation efficiency although a minimum operation voltage is applied to a PDP, the low voltage operation method of the plasma display panel includes operating one frame by dividing it into several sub-fields in order to obtain a gray level of a PDP, dividing the sub-field into a reset period, an address period, a sustain period and supplying a ramp waveform in the reset period, and applying a DC biasing voltage in order to reduce wall electric charge discharged in descending of the ramp waveform.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a low voltage operation method of a plasma display panel and an apparatus thereof, and in particular to a low voltage operation method of a plasma display panel and an apparatus thereof which are capable of reducing a voltage supplied to an address by decreasing wall electric charge inside a cell in address discharge by applying a direct-current biasing voltage.  
           [0003]    2. Description of the Prior Art  
           [0004]    In a PDP (Plasma Display Panel), inside a discharge cell separated from bulkheads, red/green/blue colors fluorescent materials formed at the bulkheads are excited by ultraviolet rays generated in discharge of inert mixture of gas such as He-Ne or Ne-Xe, a character or a graphic is displayed by visible rays generated when the state of the fluorescent materials is changed from the excitation state to a ground state.  
           [0005]    Because the PDP does not require an electron gun such as a cathode ray in order to display an image, it is thinner and lighter than a cathode ray tube and is favorable to high distinct and scale-up.  
           [0006]    In addition, because the PDP includes electrodes, a dielectric layer, and discharge gas, etc. and is operated by charge and discharge, it has a function as a capacitor charging electric charge. Accordingly, the PDP consumes lots of energy in charging/discharging, the more the size of PDP increases, the more energy consumption of the PDP increases.  
           [0007]    Accordingly, in order to consume energy more efficiently, three electrode AC surface discharge type PDP is used. In the three electrode AC surface discharge type PDP, because wall electric charge is accumulated at a surface, electrodes are prevented from sputtering occurred by discharge, therefore the three electrode AC surface discharge type PDP is favorable to a low voltage operation and having a long life span.  
           [0008]    [0008]FIG. 1 is a perspective view illustrating a structure of the conventional surface discharge type PDP, and FIG. 2 is a sectional view illustrating a cell of the PDP as shown at FIG. 1. Herein, the conventional surface discharge type PDP includes an upper substrate  10 , a scan electrode  20 Y and a sustain electrode  20 Z formed at the bottom surface of the upper substrate  10 , an upper dielectric layer  30  accumulating wall electric charge generated in discharge of the PDP, a protecting layer  30  preventing the upper dielectric layer  30  from sputtering occurred in discharge of the PDP and heightening the discharge effect of secondary electron, a lower substrate  90 , an address electrode  80 X formed at the upper surface of the lower substrate  90 , a lower dielectric layer  70  accumulating electric charge of the address electrodes  8 OX, a bulkhead  50  formed at the lower dielectric layer  70 , and a fluorescent material  60  coated onto the bulkhead  50  and the lower dielectric layer  70 .  
           [0009]    The scan electrode  20 Y and the sustain electrode  20 Z respectively include transparent electrodes  22 Y,  22 Z and metal bus electrodes  21 Y,  21 Z. The metal bus electrodes  21 Y,  21 Z have a smaller line width than the transparent electrodes  22 Y,  22 Z, are formed at the edge of the transparent electrodes  22 Y,  22 Z and reduce voltage drop due to high resistance of the transparent electrodes  22 Y,  22 Z.  
           [0010]    The upper dielectric layer  30  and the protecting later  40  are laminated onto the upper substrate  10  in which the scan electrode  20 Y and the sustain electrode  20 Z are formed. The upper dielectric layer  30  accumulates the wall electric charge generated in discharge of the PDP, the protecting layer  40  prevents the upper dielectric layer  30  from sputtering occurred in discharge of the PDP and improves the discharge efficiency of the secondary electron.  
           [0011]    The lower dielectric layer  70  and the bulkhead  50  are laminated onto the lower substrate  90 , and the fluorescent material  60  is coated onto the surface of the lower dielectric layer  70  and the bulkhead  50 .  
           [0012]    The address electrodes  80 X formed at the lower substrate  90  are placed so as to be crossed with the scan electrode  20 Y and the sustain electrode  20 Z, and the bulkhead  50  is placed so as to be crossed with the address electrodes  80 X in order to prevent ultraviolet and visible rays generated in discharge from leaking into an adjacent discharge cell.  
           [0013]    Because the fluorescent material  60  is excited by ultraviolet rays generated in discharge of the PDP, one visible ray of red/green/blue is generated and inert mixture of gas such as He-Ne or He-Xe for discharge is injected into a discharge space of the discharge cell formed between the upper/lower substrates  10 ,  90  and the bulkhead  50 .  
           [0014]    The above-described three electrode AC surface discharge type PDP operates one frame by dividing it into several sub-fields having different luminous times in order to obtain gray level of a picture.  
           [0015]    Each of the sub-fields is divided into a reset period for occurring discharge regularly, an address period for selecting a discharge cell and a sustain period for obtaining a gray level according to the discharge times.  
           [0016]    For example, in order to display a picture with 256 gray level, a frame period (16.67 ms) corresponded to {fraction (1/60)} second is divided into eight sub-fields (SF 1 ˜SF 8 ), the eight sub-fields (SF 1 ˜SF 8 ) are divided into a reset period, an address period and a sustain period. The reset period and the address period of each sub-field are same, however the sustain period increases as a rate of 2 n  (n=0, 1, 2, 3, 4, 5, 6, 7). Because the sustain period is different in each sub-field, the gray level of the picture can be obtained.  
           [0017]    In the above-described sub-field, an operation waveform supplied to the three electrode AC surface discharge type PDP will be described with reference to accompanying FIGS.  3 A- 3 C.  
           [0018]    FIGS.  3 A- 3 C are waveform diagrams illustrating an operation waveform supplied to the three-way AC surface discharge type PDP in a sub-field according to the conventional art, the PDP operates one sub-field by dividing it into the reset period, the address period and the sustain period.  
           [0019]    In the reset period, an ascending ramp waveform (ramp  1 ) and a descending ramp waveform (ramp  2 ) are supplied consecutively.  
           [0020]    When the ascending ramp waveform (ramp  1 ) is supplied, weak discharge occurs between the scan electrode  20 Y and the sustain electrode  20 Z, and wall electric charge is accumulated at the upper dielectric layer  30 . When the descending ramp waveform (ramp  2 ) is supplied, an operational margin of an operation circuit can be obtained sufficiently by removing the wall electric charge inside the cell appropriately.  
           [0021]    By supplying the ramp waveform to the scan electrode  20 Y for the reset period, a contrast ratio is increased by decreasing visible rays as many as possible for the reset period as a non-display period, and an operation voltage required for the address discharge is lowered by forming the wall electric charge at the whole panel uniformly.  
           [0022]    For the address period, an electrode negative data pulse is supplied to the address electrode  80 X, and an electrode positive scan pulse is sequentially supplied to the scan electrode  20 Y in order to synchronize with the data pulse. The cell supplied the data pulse is address-discharged by being added the voltage corresponded to the voltage difference between the data pulse and the scan pulse and the internal wall voltage accumulated by the wall electric charge inside the cell.  
           [0023]    For the sustain period, a sustain pulse is supplied to the scan electrode  20 Y and the sustain electrode  20 Z by turns, cells selected by the address discharge performs a sustain discharge whenever the sustain pulse is supplied. After all the sustain discharge according to a luminance relative ratio occurs, an erase signal having a chopping wave shape is supplied to the sustain electrode  20 Z.  
           [0024]    As described above, by discharging the wall electric charge inside the cell for the reset period, the voltage required for the address discharge is lowered.  
           [0025]    However, in order to perform the address discharge, because a voltage not less than 60W is required, power for operating the PDP is consumed a lot. And, because parts suitable for the high voltage operation are expensive, a fabrication cost is increased.  
           [0026]    In addition, because the number of wall electric charges is decreases in the high voltage, operation efficiency of the PDP is lowered.  
         SUMMARY OF THE INVENTION  
         [0027]    It is an object of the present invention to provide a low voltage operation method of a plasma display panel and an apparatus thereof which are capable of lowering a voltage supplied from outside as an optimum level in address discharge by applying a DC biasing voltage to a PDP (Plasma Display Panel).  
           [0028]    In order to achieve the above-mentioned object, a low voltage operation method of a plasma display panel in accordance with the present invention includes operating one frame by dividing it into several sub-fields in order to obtain a gray level of a PDP, dividing the sub-field into a reset period, an address period, a sustain period and supplying a ramp waveform in the reset period, and applying a DC biasing voltage in order to reduce wall electric charge discharged in descending of the ramp waveform.  
           [0029]    In order to achieve the above-mentioned object, a low voltage operation apparatus of a plasma display panel in accordance with the present invention includes a plasma display panel, a maintenance operation unit being supplied a sustain voltage, a biasing voltage supplying unit supplying a DC biasing voltage, a first switch controlling a voltage applied from the biasing voltage supplying unit, a second switch controlling the operation of a reset voltage, a third switch controlling a voltage supplied from the first switch and the second switch, a fourth switch controlling supply of a scan voltage, and an operation intergrated circuit connected to a scan electrode. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0030]    [0030]FIG. 1 is a perspective view illustrating a structure of a discharge type PDP (Plasma Display Panel) according to the prior art;  
         [0031]    [0031]FIG. 2 is a sectional view illustrating a cell of the PDP as shown at FIG. 1;  
         [0032]    FIGS.  3 A- 3 C are waveform diagrams illustrating an operation waveform supplied to a three electrode AC surface discharge type PDP in a sub-field according to the prior art;  
         [0033]    [0033]FIG. 4 is a circuit diagram illustrating a scan electrode operation unit of a PDP in accordance with the present invention;  
         [0034]    [0034]FIG. 5 is a detailed circuit diagram illustrating a voltage supplying unit as shown in FIG. 4;  
         [0035]    FIGS.  6 A- 6 H are waveform diagrams illustrating a low voltage address operation method of a plasma display panel according to the present invention; and  
         [0036]    FIGS.  7 A- 7 C are waveform diagrams illustrating a low voltage operation method of a plasma display panel according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0037]    [0037]FIG. 4 is a circuit diagram illustrating a scan electrode operation unit of a PDP in accordance with the present invention, a scan electrode operation unit of a PDP in accordance with the present invention includes a maintenance operation unit  100  being supplied a sustain voltage (Vsus), a biasing voltage supplying unit  200  being supplied a DC biasing voltage, a reset up switch (sw 3 ) controlling supply of a reset voltage (Vrst), a scan switch (sw 5 ) controlling supply of the scan voltage (Vscan), an operation intergrated circuit  300  connected to a scan electrode (Y), a reset up reverse switch (sw 2 ) connected between a first node (n 1 ) and a second node (n 2 ), and a scan reverse switch (sw 4 ) connected between the second node (n 2 ) and a third node (n 3 ).  
         [0038]    The biasing voltage supplying unit  200  is constructed with a reset down switch (sw 1 ) connected between a biasing voltage supplier and a first node (n 1 ) and a resistance  290  connected between a fourth node (n 4 ) and a ground voltage (GND). The resistance  290  stabilizes the biasing voltage (Vbias) supplied to the fourth node (n 4 ).  
         [0039]    The construction of the biasing voltage supplying unit  200  will be described in detail with reference to accompanying FIG. 5.  
         [0040]    [0040]FIG. 5 is a detailed circuit diagram illustrating the biasing voltage supplying unit as shown in FIG. 4. The biasing voltage supplying unit  200  includes a first diode  210  and a first resistance  220  being supplied a reset down control signal, a variable resistance  230  parallel-connected to the first diode  210  and the first resistance  220 , a reset down switch (sw 1 ) parallel-connected to the variable resistance  230 , a third diode  280  serial-connected to the reset down switch (sw 1 ), a second diode  260  and a fourth resistance  270  parallel-connected to the third diode  280 , the second diode  260  and the fourth resistance  270 , a third resistance  240  and a condenser  250  serial-connected to the first resistance  220 , and a fifth resistance  290  stabilizing the biasing voltage supplied to the reset down switch (sw 1 ).  
         [0041]    The diodes  210 ,  260 ,  280  prevent reverse currents of inputted currents, the third resistance  240  and the fourth resistance  270  stabilize a voltage inputted from the first node (n 1 ) through the third diode ( 280 ), and the first resistance stabilizes a voltage of a seventh node (n 7 ) as a cross point of the reset down switch (sw 1 ) and the condenser  220 .  
         [0042]    The variable resistance  280  and the condenser  250  determine descendent of a ramp waveform inputted to a scan electrode (Y) of the plasma display panel for the reset period by time constants.  
         [0043]    The reset down switch (sw 1 ) uses MOSFET of a N channel, it can use also a different kind of transistor capable of switching control.  
         [0044]    The operation method of the plasma display will be described in detail with reference to accompanying FIGS. 4, 5 and  6 A- 6 H.  
         [0045]    FIGS.  6 A- 6 H are waveform diagrams illustrating a low voltage address operation method of a plasma display panel according to the present invention, herein one sub-field operable the PDP is divided into a reset period, an address period and a sustain period.  
         [0046]    At the initial time point of the reset period, the reset up reverse switch (sw 2 ) and the scan reverse switch (sw 3 ) are turned on, the reset down switch (sw 1 ), the reset up switch (sw 3 ) and the scan switch (sw 5 ) are turned off, the sustain voltage (Vsus) generated in the maintenance operation unit (sw 3 ) is inputted to the operation intergrated circuit  300  and supplied to the scan electrode Y. When the sustain voltage (Vsus) is inputted, the voltage of the scan electrode (Y) rises same as the sustain voltage (Vsus).  
         [0047]    When the scan electrode (Y) rises so as to be same as the sustain voltage (Vsus), the reset up switch (sw 3 ) is turned on, the reset up reverse switch (sw 2 ) is turned off, and the voltage of the scan electrode (Y) rises same as the reset voltage.  
         [0048]    When the ascent ramp waveform (ramp  1 ) is supplied to the scan electrode (Y), weak discharge occurs between the scan electrode (Y) and the sustain electrode (Z), by the discharge, the wall electric charge accumulates at the scan electrode (Y) and the sustain electrode (Z).  
         [0049]    When the wall electric charge is accumulated uniformly, the reset up switch (sw 3 ) is turned off, the reset up reverse switch (sw 2 ) and the reset down switch (sw 1 ) are turned on, and the DC biasing voltage (Vbias) is supplied to the scan electrode (Y).  
         [0050]    By the DC biasing voltage, the scan electrode (Y) declines same as the DC biasing voltage (Vbais) as the slope of the descent ramp waveform (ramp  2 ) determined by the time constants of the variable resistance  280  and the condenser  250 .  
         [0051]    In the slope of the descent ramp waveform (ramp  2 ), it is favorable to have a threshold value as small as possible, when the slope is too big, the wall electric charge can not be uniformly accumulated at the scan electrode (Y) and the sustain electrode (Z), because the address discharge is performed irregularly, the waveform is unstable.  
         [0052]    The descent ramp waveform (ramp  2 ) does not decline to the ground voltage (GND) but to the electrode negative of the DC biasing voltage (Vbias), the voltage level is smaller than the ascent ramp waveform (ramp  1 ), and the minimum wall electric charge not required for the address discharge is removed.  
         [0053]    In more detail, because the voltage level of the descent ramp waveform (ramp  2 ) is small as the DC biasing voltage (Vbias), the wall electric charge is removed as small as the voltage, the wall electric charge remained inside the cell increases, and the wall voltage inside the cell is increased before the address discharge, accordingly the voltage of the data pulse and the scan pulse required for the address discharge can be decreased.  
         [0054]    For the address period, the electrode negative data pulse is supplied to the address electrode (X). The scan switch (sw 5 ) is turned on by synchronizing with the data pulse, when the scan reverse switch (sw 3 ) is turned off, the scan pulse is supplied to the scan electrode (Y) by synchronizing with the data pulse. The cell supplied the data pulse is address-discharged by being added the voltage corresponded to the voltage difference between the data pulse and the scan pulse and the wall voltage inside the cell.  
         [0055]    The more the value of the scan pulse and the data pulse are small, the more the external voltage applied to the PDP (Plasma Display Panel) for the address discharge are small.  
         [0056]    For the sustain period, the sustain pulse is supplied to the scan electrode (Y) and the sustain electrode (Z) by turns.  
         [0057]    The cells selected by the address discharge perform the sustain discharge whenever the sustain pulse is supplied, after all the all sustain discharge are performed, the small erase signal having the chopping wave is supplied to the common sustain electrode (Z).  
         [0058]    In the DC biasing voltage (Vbias), because the address operation margin is reduced as same as the erase quantity of the wall electric charge, the size of the DC biasing voltage is determined by considering the address operation margin.  
         [0059]    In other words, when the DC biasing voltage (Vbias) is set so as to be not less than a certain amount, because the wall voltage inside the cell not being supplied the data is big, the address discharge can occur in the un-requested cell.  
         [0060]    In order to solve the above-mentioned problems, the DC biasing voltage is applied for the address period.  
         [0061]    It will be described in more detail with reference to accompanying FIGS.  7 A- 7 C.  
         [0062]    FIGS.  7 A- 7 C are waveform diagrams illustrating a low voltage operation method of a plasma display panel according to the present invention. By applying the DC biasing voltage to the sustain electrode (Z), the voltage on the sustain electrode (Z) is adjusted so as to be smaller for the reset period, and the DC biasing voltage supplied to the descent ramp waveform (ramp  2 ) can be set so as to be more higher for the reset period, accordingly the voltage required for the address discharge can be lowered.  
         [0063]    As described above, in the low voltage operation method of the plasma display panel and the apparatus thereof in accordance with the present invention, by applying the DC biasing voltage to the scan electrode when the descent ramp waveform (ramp  2 ) is supplied to the scan electrode for the reset period, the voltage of the descent ramp waveform supplied to the scan electrode can be lowered, accordingly the wall electric charge removed for the reset period can be minimized. And, by increasing the wall voltage inside the cell in the address discharge, the external supply voltage required for the address discharge can be lowered, the power consumption can be reduced, and by using the low voltage parts, the fabrication cost can be reduced and it is favorable to miniaturization of the apparatus.  
         [0064]    In addition, by lowering the voltage of the sustain electrode for the address period, because errors in address discharge due to the DC biasing voltage supplied to the descent ramp waveform can be prevented, although a low voltage is supplied in the address discharge, the address can operate stably.  
         [0065]    In addition, because a low voltage operation circuit unit is obtained by using elements stabilizing the biasing voltage, a biasing voltage supplying unit can be easily obtained.