Abstract:
A receiver comprises an input circuit that receives an input signal. An error circuit generates an error signal based on the input signal. A first noise canceler generates a first noise cancellation signal based on the error signal. A second noise canceler generates a second noise cancellation signal based on the error signal. The input circuit is responsive to the second noise cancellation signal.

Description:
This application is a continuation of U.S. application Ser. No. 11/028,223, filed Jan. 4, 2005, which is a continuation of U.S. application Ser. No. 09/536,120, filed Mar. 27, 2000, the entire contents of which are incorporated by reference herein. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     This invention is related to noise reduction in communication systems such as Ethernet. More particularly, this invention is related to reduction of D.C. noise components in a signal received from a communication channel. 
     2. Background Information 
     The structures of digital communications such as Ethernet, as described in the Institute of Electrical and Electronic Engineers (IEEE) specification IEEE 802.3, are well known in the art. To improve reception of encoded signals from a communication channel, noise components must be determined and subtracted from the received signal. One of the noise components induced within the communication channel is referred to as D.C. noise. Refer to  FIGS. 2   a  and  2   b  to understand the definition and the effect of D.C. noise components on the received signal a i .  FIG. 2   a  shows an eye diagram of a received signal a i  of a five-level amplitude-modulated signal. Each voltage level represents one of the code values of the digital signal being transferred. In an ideal communication system, each “eye” of the eye diagram would be nearly rectangular. The more “closed” the “eye,” the more noise induced on the communication channel. Low frequency or D.C. noise components that are a result of the encoding of the digital data or that are induced on the communication channel may actually shift the D.C. voltage level as shown in  FIG. 2   b . In this example, the whole signal a i  is shifted by a D.C. voltage level Δ dc . The effect of the D.C. noise components is to degrade the performance of the circuitry that decoded the received signal a i  to recover the digital data. This implies a higher error rate of the data received, thus requiring more robust error recovery and slower data transmission. 
     Further, as can be seen in  FIG. 2   b , the receiver must have a wider dynamic range. That is the voltage range that the receiver recognizes, as the signal a i  must be larger. 
     Refer now to  FIG. 1  for a discussion of a receiver and a D.C. noise cancellation circuit of the prior art. The multiple level amplitude-modulated signal a i  is transferred to the communication channel. The received signal a irec  having D.C. noise components, as shown in  FIG. 2   b , is the input to the receiver. Typically, it is desirable to remove as much of the D.C. noise components as early as possible in the receiving of the signal a irec . Typically, a D.C. noise canceling signal is subtractively combined in a first summing circuit Σ 1  with the received signal a irec  to remove the D.C. noise components. The signal a inc  with the D.C. noise components removed is the input to the analog-to-digital converter. 
     The analog-to-digital converter creates a set of sampled digital data h k  indicating the amplitude of the received signal a inc  with the D.C. noise components removed. The sampled digital data is created at discrete periods of a sampling clock and is retained or buffered as needed in a memory or registers (not shown). 
     As is known in the art, the communication channel acts as a low pass filter causing what is termed intersymbol interference where noise components from adjacent symbols of the encoded data interfere with the current symbol. The feed-forward or feedback equalizer removes any of the intersymbol interference to create the equalized sampled digital data of the received signal f k . The equalized sampled digital data f k  is the input of the decision circuit that determines an estimate of the transmitted value of the signal â k . 
     An error signal ε k  is determined as the difference between the equalized sampled digital data f k  and the estimated value of the signal â k . The equalized sampled digital data f k  and the estimated values of the signal â k  are the inputs to the second summing circuit Σ 2 . The second summing circuit Σ 2  subtractively combines the equalized sampled digital data f k  and the estimated values of the signal â k  to form the error signal ε k . 
     The error signal ε k  is used to determine the level of the D.C. noise component that needs to be removed from the received signal. 
     The error signal ε k  is the input to the D.C. noise canceling circuit DCC. The error signal, further, is the input of the multiplier circuit M 1 . The second input of the multiplier circuit M 1  is a gain constant μ dc . The gain constant μ dc  is chosen to be sufficiently small to make the noise cancellation stable, but sufficiently large to track any slow variation in the D.C. voltage level of the received signal a irec . The range of the gain constant μ dc  is dependent on the condition of the communication channel. 
     The output of the multiplier circuit M 1  is one input of a third summing circuit Σ 3 . The second input of the third summing circuit Σ 3  is the value of the D.C. noise cancellation signal for the previous sample period, and the output of the third summing circuit Σ 3  is the D.C. noise cancellation signal for the previous sampling period of the received signal a irec . The output of the third summing circuit Σ 3  is the input of the delaying circuit τ d1 . The output of the delaying circuit τ d1  is the input to the first summing circuit Σ 1  to remove the D.C. noise component from the received signal a irec . 
     U.S. Pat. No. 4,486,740 (Seidel) describes a circuit for DC noise cancellation in ternary-coded data systems. An encoder processes an input signal to produce a ternary coded data stream having suppressed DC. The data stream is augmented with a compensating set of code symbols as determined by the number of positive and negative code symbols in the data stream as well as all prior compensating code symbols. A decoder processes the received signal to extract the symbols in the data stream corresponding to the input signal. In order to achieve a pre-selected end-to-end transmission rate with the encoder-decoder combination, the rate of the signal propagated between encoder and decoder is increased to compensate for the appended code symbols. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide a circuit to eliminate D.C. noise from a signal received from a communication channel. 
     Another object of this invention is to provide a circuit employing dual adaptive D.C. noise cancellation loops to eliminate D.C. noise from a signal received from a communication channel. 
     An additional object of this invention is to provide a circuit employing two adaptive D.C. noise cancellation loops that are decoupled to insured stability of the circuit while eliminating D.C. noise components from a signal received from a communication channel. 
     To accomplish these and other objects a circuit within a receiver of a communication system is provided for removing D.C. noise components from a signal acquired by the receiver. The circuit has a first D.C. noise canceler that generates a first D.C. noise cancellation signal. An input is connected within the receiver to an output of an error circuit, which determines an error signal that is an estimate of D.C. noise within the signal. The first D.C. noise canceler has an output connected within the receiver to an input of a decision circuit that subtractively combines the first D.C. noise cancellation signal with the signal to remove a first portion of the D.C. noise components. The circuit has a second D.C. noise canceler with an input to receive the first D.C. noise cancellation signal, a second input connected to the output of the error circuit to receive the error signal, and an output connected to the input of the receiver to subtractively combine the received signal acquired from the communication channel with the second D.C. noise cancellation signal to remove a second portion of the D.C. noise components. 
     The first D.C. noise canceler forms the first noise cancellation signal as a function of the error signal according to the formula:
 
DC1 n+1 =DC1 n +μ dc1 ×ε k  
 
     where:
         DC 1   n  is the first noise cancellation signal for the current sampling time of the received signal;   DC 1   +1  is the first noise cancellation signal for the next sampling time of the received signal;   μ dc1  is a first loop gain constant;   ε k  is the error signal determined by the formula:
 
ε k   =f   knc   −â   k  
       

     where:
         â k  is the estimated value of the transmitted signal;   f knc  is an equalized, noise cancelled received signal of the current sampling.       

     The second D.C. noise canceler forms the second noise cancellation signal as a function of the error signal according to the formula:
 
DC2 n+1 =DC2 n +μ dc1 ×(ε k +DC1 n )
 
     where:
         DC 2   n  is the second noise cancellation signal for the current sampling time of the received signal;   DC 2   +1  is the second noise cancellation signal for the next sampling time of the received signal;   μ dc2  is a second loop gain constant;   ε k  is the error signal determined by the formula:
 
ε k   =f   knc   −â   k  
       

     where:
         â k  is the estimated value of the transmitted signal;   f knc  is an equalized, noise cancelled received signal of the current sampling;   DC 1   n  is the first noise cancellation signal for the current sampling time of the input signal.       

     The first D.C. noise canceler includes a first multiplication circuit, which is connected to the input to receive the error signal and to multiply the error signal by a first loop gain constant to produce a first product. The first product is an input to a first additive combining circuit. The first additive combining circuits is additionally connected to the output of the first D.C. noise canceler to receive a current first D.C. noise cancellation signal. The first additive combining circuit additively combines the first product with the current first D.C. noise cancellation signal to produce a next first D.C. noise cancellation signal. A first unit delay circuit is connected to the first additive combining circuit to delay the first D.C. noise cancellation signal by one sampling time. 
     The second D.C. noise canceler has a second additive combining circuit connected to receive the error signal at the first input and to receive the first D.C. noise cancellation signal at the second input. The error signal and the first D.C. noise cancellation signal are additively combined to form a first sum, which restores the first D.C. noise cancellation signal to the error signal. A second multiplication circuit is connected to the second additive circuit to receive the first sum and to multiply the first sum by a gain constant to produce a second product. Connected to the second multiplication circuit is a third additive combining circuit to receive the second product and to the output of the second D.C. noise canceler to receive a current second D.C. noise cancellation signal. The third additive combining circuit additively combines the second product with the current second D.C. noise cancellation signal to produce a next second D.C. noise cancellation signal. Connected to the output of the third additive combining circuit is a second unit delay circuit to delay the second D.C. noise cancellation signal by one sampling time. 
     The first and second loop gain constants are chosen to have values that are sufficiently small to insure stable operation of the first and second noise cancelers. However, the first and second loop gain constants must be sufficiently large to track any slow variation in the level of the D.C. noise present in the received signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects and advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments, in conjunction with the accompanying drawings, wherein like reference numerals have been used to designate like elements, and wherein: 
         FIG. 1  is a system schematic diagram of a receiver of the prior art. 
         FIGS. 2   a  and  2   b  are eye diagrams of a signal received from a communication channel. 
         FIG. 3  is a system schematic diagram of a receiver having noise cancellation circuitry of this invention. 
         FIG. 4  is a process flow diagram of a method for noise canceling in a receiver of this invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A drawback of an adaptive loop created by the D.C. noise canceling circuit of  FIG. 1  is the large time latency from the analog-to-digital converter of  FIG. 1  to the decision circuit of  FIG. 1 . The long time latency results in less accuracy in the determination of the D.C. noise component and thus allowing a residual D.C. noise component to remain. 
     A solution to the long time latency of a single adaptive loop is a dual adaptive loop terminating at the input of the decision circuit of  FIG. 1 . A second potential problem in using two adaptive loops to cancel the D.C. noise is that the two loops are coupled together and can cause stability problems. 
     Refer now to  FIG. 3  for a discussion of a receiver within a communication circuit containing two D.C. noise cancellation circuits. The basic receiver structure is as described above in  FIG. 1  with a signal a i  traversing a communication channel to the input of the receiver. The analog-to-digital converter samples the received signal having D.C. noise components removed periodically and converts these samples to a sampling digital data h k  indicating the amplitude of the received signal a irec  at the sampling times. The sampled digital data h k  is transferred to the feed-forward/feedback equalization circuit for removal of intersymbol interference noise components to create an equalized sampled digital data f k . The equalized sampled digital data f k  is then conveyed to the decision circuit where it is decoded. The decision circuit is, as described above, a Viterbi trellis decoding circuit. The output of the decision circuit is an estimate of the original signal â k . 
     An error signal ε k  is generated as a difference between the estimated original signal â k  and the equalized sampled digital data f k . This is accomplished in the second summing circuit Σ 2 . The inputs of the second summing circuit Σ 2  are the estimated original signal â k  and the equalized sampled digital data that has had the D.C. noise removed f knc . The second summing circuit Σ 2  subtractively combines the estimated original signal â k  and the equalized sampled digital data with the D.C. noise removed f knc  to form the error signal ε k . 
     The first D.C. noise cancellation signal DC 1  is the D.C. noise cancellation signal that has the smallest time latency and is subtractively combined with the equalized sampled digital data f k  at the summing circuit Σ 6 . The first D.C. noise cancellation signal DC 1  is formed as a function of the error signal ε k  in the first noise cancellation circuit DCC 1 . The first D.C. noise cancellation circuit performs the function to create the D.C. noise cancellation signal DC 1  according to the formula:
 
DC1 n+1 =DC1 n +μ dc1 ×ε k  
 
     where:
         DC 1   n  is the first noise cancellation signal for the current sampling time of the received signal;   DC 1   n+1  is the first noise cancellation signal for the next sampling time of the received signal;   μ dc1  is a first loop gain constant;   ε k  is the error signal determined by the formula:
 
ε k   =f   knc   −â   k  
       

     where:
         â k  is the estimated value of the transmitted signal;   f knc  is an equalized, noise cancelled received signal of the current sampling.       

     To minimize the complexity of the design of the D.C. noise cancellation circuit, the second D.C. noise cancellation signal DC 2  is subtractively combined with the received signal a irec  to eliminate a portion of the D.C. noise from the received signal a irec . The second D.C. noise cancellation circuit DCC 2  forms the second D.C. noise cancellation signal as a function of the error signal ε k  in combination with the first D.C. noise cancellation signal to effectively decouple the first and second D.C. noise cancellation circuits DCC 1 , DCC 2 . The second D.C. noise cancellation circuit DCC 2  executes the formula:
 
DC2 n+1 =DC2 n +μ dc1 ×(ε k +DC1 n )
 
     where:
         DC 2   n  is the second noise cancellation signal for the current sampling time of the received signal;   DC 2   n+1  is the second noise cancellation signal for the next sampling time of the received signal;   μ dc2  is a second loop gain constant;   ε k  is the error signal determined by the formula:
 
ε k   =f   knc   −â   k  
       

     where:
         â k  is the estimated value of the transmitted signal;   f knc  is an equalized, noise cancelled received signal of the current sampling;   DC 1   n  is the first noise cancellation signal for the current sampling time of the received signal.       

     The first and second loop gain constants μ dc1  and μ dc2  are chosen to have value that is sufficiently small to insure stable operation of the first and second noise cancellation circuits DCC 1 , DCC 2 . However, the first and second loop gain constants μ dc1 , μ dc2  must be sufficiently large to track any slow variation in the level of the D.C. noise present in the received signal a irec . 
     The first D.C. noise cancellation circuit DCC 1  has a first multiplying circuit M 1 . The input of the multiplying circuit are the error signal ε k  and the first loop gain constant μ dc1 . The first multiplying circuit M 1  multiplies the error signal ε k  and the first loop gain constant μ dc1  to form a first product at the output of the first multiplying circuit M 1 . 
     The first product is an input of the third summing circuit Σ 3  where it is additively combined with the current level of the first D.C. noise cancellation signal DC 1   n  to form a next first D.C. noise cancellation signal DC 1   n+1 . The next first D.C. noise cancellation signal DC 1   n+1  is the input to the first delaying circuit τ d1  which delays the next first D.C. noise cancellation signal DC 1   n+1  by one sampling period. The output of the first delaying circuit τ d1  is the input to the sixth summing circuit Σ 6 , thus forming the adaptive loop at the decision circuit. 
     The fourth summing circuit Σ 4  additively combines its inputs, which are the error signal ε k  and the first D.C. noise cancellation signal DC 1  to form a first sum. The fourth summing circuit effectively returns the first D.C. noise cancellation signal DC 1  to the error signal ε k , thus decoupling the first and second D.C. noise cancellation circuits DCC 1  and DCC 2 . 
     The first sum of the error signal ε k  and the first D.C. noise cancellation signal DC 1  is multiplied in the second multiplying circuit M 2  by a second loop gain constant μ dc2  to form a second product at its output. The second product is additively combined with the current second D.C. noise cancellation signal DC 2   n  in the fifth summing circuit Σ 5  to form a next second D.C. noise cancellation signal DC 2   n+1 . The next second D.C. noise cancellation signal DC 2   n+1  is the input to the second delaying circuit τ d2 . The second delaying circuit τ d2  delays the next D.C. noise cancellation signal by one sampling time. The output of the delaying circuit is the input of the first combining circuit Σ 1  which subtractively combines the second D.C. noise cancellation signal DC 2  with the received signal a irec  at the next sampling time of the analog-to-digital converter. 
     It is well-known in the art that, while the above describes individual circuitry to implement an apparatus that removes the D.C. noise component of a received signal a irec , the apparatus may be implemented as a program code for execution on a computational processor. The program code maybe obtained from media such as storage nodes of an internal or external network or stored on a storage media such as read only memory (ROM) or a magnetic disk. Further, while complex and difficult to implement, the apparatus to remove the D.C. noise components of a received signal may be constructed as analog filter circuits using continuous time processing. 
     The program code executed by the computational processor executes a method for removing D.C. noise components from a received signal described as shown in  FIG. 4 . The method to remove D.C. noise components from a signal received from a communication channel begins by generating a first D.C. noise cancellation signal  100  as a function of an error signal. The error signal is an estimate of noise within the signal as described above. The first D.C. noise cancellation signal is subtractively combined  105  with an equalized received signal thus removing a first portion of the D.C. noise components from the signal. A second D.C. noise cancellation signal is generated  110  as a function of the error signal and the first D.C. noise cancellation signal. Then subtractively combined  115  with the signal as it is received from the communication channel thus removing a second portion of the D.C. noise components from the received signal. 
     The generating the first D.C. noise cancellation signal  100  is formed as the function of the error signal according to the formula:
 
DC1 n+1 =DC1 n +μ dc1 ×ε k  
 
     where:
         DC 1   n  is the first noise cancellation signal for the current sampling time of the received signal;   DC 1   n+1  is the first noise cancellation signal for the next sampling time of the received signal;   μ dc1  is a first loop gain constant;   ε k  is the error signal determined by the formula:
 
ε k   =f   knc   −â   k  
       

     where:
         â k  is the estimated value of the transmitted signal;   f knc  is an equalized, noise cancelled received signal of the current sampling.       

     The generating the second D.C. noise cancellation signal  110  is formed as a function of the error signal and the first D.C. noise cancellation signal according to the formula:
 
DC2 n+1 =DC2 n +μ dc1 ×(ε k +DC1 n )
 
     where:
         DC 2   n  is the second noise cancellation signal for the current sampling time of the received signal;   DC 2   n+1  is the second noise cancellation signal for the next sampling time of the received signal;   μ dc2  is a second loop gain constant;   ε k  is the error signal determined by the formula:
 
ε k   =f   knc   −â   k  
       

     where:
         â k  is the estimated value of the transmitted signal;   f knc  is an equalized, noise cancelled received signal of the current sampling;   DC 1   n  is the first noise cancellation signal for the current sampling time of the received signal.       

     Further, the generating the first D.C. noise cancellation signal  100  is a method that begins by multiplying the error signal by a first loop gain constant to produce a first product. The first product is additively combined with a current first D.C. noise cancellation signal to produce a next first D.C. noise cancellation signal. The next first noise cancellation signal is delayed by one sampling time the next first D.C. noise cancellation signal to align. 
     The generating the second D.C. noise cancellation signal  110  is a method that begins by additively combining the error signal and the first D.C. noise cancellation signal to form a first sum which adds the first D.C. noise cancellation signal back to the error signal to decouple the generating of the first noise cancellation signal from the generating of the second noise cancellation signal. The method continues by multiplying the first sum by a second loop gain constant to produce second product. The second product is additively combined with a current D.C. noise cancellation signal to produce a next second D.C. noise cancellation signal, which is then delayed by one sampling time. The first and second loop gain constants are chosen to have values that are sufficiently small to insure stable operation of the first and second noise cancellation circuits. However, the first and second loop gain constants must be sufficiently large to track any slow variation in the level of the D.C. noise present in the received signal. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.