Abstract:
One embodiment of the present invention provides a system that migrates a layout of a cell which is used in integrated circuit design. During operation, the system receives a layout for the cell, wherein one or more layers of the cell contain tracks for metal wires. The system then determines how many tracks are to be inserted into the cell. Next, the system inserts one or more extra tracks between the tracks in the cell. The system subsequently adjusts the widths of the inserted tracks and the original tracks to increase the total number of tracks within the cell while maintaining the metal wires at the center of their original tracks.

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to the process of designing integrated circuits. More specifically, the present invention relates to a method and an apparatus for inserting extra tracks in a library cell to facilitate migration of the cell to a different technology. 
   2. Related Art 
   As advances in deep-submicron fabrication technologies make it possible to achieve greater degrees of semiconductor integration, such integration makes the design of integrated-circuits (ICs) increasingly more challenging. By enabling multi-million-gate system-on-chip (SoC) designs, the latest generation of process technologies has widened the gap between manufacturing capabilities and designers&#39; abilities to quickly design these complex devices. Reuse of existing layouts helps close this gap and enables companies to meet tight time-to-market objectives. However, conventional optical shrink techniques no longer work on existing silicon-proven layouts, because at deep-submicron level, different process design rules shrink by different factors. 
   Fortunately, a new generation of compaction-based electronic design automation (EDA) tools has emerged. These EDA tools can re-size and re-place millions of polygon edges described in an existing layout to conform to particular design rules. Consequently, they can better enable designers to migrate proven layouts to new technologies. 
   In a layout which is based on a standard library architecture, modern EDA tools are presently able to compact existing library cells to ensure that the target cell layout obtained after migration meets with the latest design rules. However, even with automatic compaction, there are still challenges in migrating certain types of library cells. 
   One such challenge is to migrate a cell containing tracks for metal wires. A cell typically includes one or more metal layers containing “tracks” where a metal wire can be placed for routing purposes. During migration, a cell ideally follows not only a set of process design rules, but also a set of corresponding template or architectural rules. For example, an existing metal wire ideally remains at the center within a track after additional tracks are added to a cell. Unfortunately, current compaction tools typically cannot guarantee meeting with such architectural rules. 
   Hence, what is needed is a method and an apparatus for inserting tracks into a library cell during migration of the cell to a different technology without the above-described problems. 
   SUMMARY 
   One embodiment of the present invention provides a system that migrates a layout of a cell which is used in integrated circuit design. During operation, the system receives a layout for the cell, wherein one or more layers of the cell contain tracks for metal wires. The system then determines how many tracks are to be inserted into the cell. Next, the system inserts one or more extra tracks between the tracks in the cell. The system subsequently adjusts the widths of the inserted tracks and the original tracks to increase the total number of tracks within the cell while maintaining the metal wires at the center of their original tracks. 
   In a variation on this embodiment, each metal wire is located at the center of a track. 
   In a variation on this embodiment, the system sets the widths of the extra tracks to be infinitesimally narrow prior to insertion. 
   In a variation on this embodiment, the system inserts a metal wire into one of the extra tracks after adjusting the width of that extra track. 
   In a variation on this embodiment, the system allows a user to specify locations to insert the extra tracks. 
   In a variation on this embodiment, adjusting the widths of the inserted tracks and the original tracks involves adjusting the widths of the inserted tracks and the original tracks according to a set of process design rules. 
   In a further variation, adjusting the widths of the inserted tracks and the original tracks according to the set of process design rules involves using a compactor which enforces the set of process design rules. 
   In a further variation, adjusting the widths of the inserted tracks involves expanding the widths of the inserted tracks to a track width specified by the set of process design rules. 
   In a further variation, adjusting the widths of the original tracks involves reducing the widths of the original tracks to a track width specified by the set of process design rules. 
   In a variation on this embodiment, the system scales down the cell layout after adjusting the widths of the inserted tracks and the original tracks based on new process technologies. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
       FIG. 1  illustrates an exemplary library cell layout. 
       FIG. 2  illustrates the process of linearly dividing a cell to accommodate additional tracks, which results in undesirable shifting of metal wires. 
       FIG. 3  illustrates the process of adding tracks to a cell by inserting and expanding infinitesimally narrow tracks in accordance with an embodiment of the present invention. 
       FIG. 4  presents a flow chart illustrating the process of inserting and expanding infinitesimally narrow tracks in accordance with an embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
   The data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs) and DVDs (digital versatile discs or digital video discs), and computer instruction signals embodied in a transmission medium (with or without a carrier wave upon which the signals are modulated). For example, the transmission medium may include a communications network, such as the Internet. 
   Standard Library Cells 
     FIG. 1  illustrates an exemplary library cell layout. In this example, library cell  100  contains a number of metal wiring tracks, such as tracks  140  and  142 . These tracks define the location of metal wires in a metal layer, such as the metal2 layer. As shown in  FIG. 1 , metal wires  110 ,  112 , and  114  are located with tracks  2 ,  6 , and  13 , respectively. Note that a typical architectural rule is that a metal wire has to be fully accommodated within one track and has to be located at the center of that track. 
   Also shown in  FIG. 1  are power rails for high-voltage power supply (VDD  120 ) and low-voltage power supply (VSS  122 ). Both of the power-supply rails typically reside in the metal1 layer. In addition, there exist transistors, such as transistor  130 , which is located within a cell. Note that the locations of the tracks, metal wires, and transistors are constrained by process design rules. 
   In the past, layout migration was typically accomplished through a linear shrink process, where every feature of the layout is reduced with respect to scale, size, and spacing by a given factor. While such simple shrink processes have been reasonably successful in migrating to older process technologies, they have become ineffective for new nanometer process technologies. 
   In a library architecture, because of various physical effects associated with the manufacturing process, each layer and object scales differently, reflecting its specific manufacturing tolerances and sensitivities. In addition, the relationship between polygon size and the characteristics of the underlying elements, such as interconnect characteristics, threshold voltages, and corresponding transistor conductance, are dramatically nonlinear. Therefore, migration needs individual instances to be accurately and individually sized based on specific operating conditions. Particularly, the width and spacing of wires needs to be carefully analyzed, because interconnects significantly impact circuit performance. 
   Inserting Tracks into an Existing Cell 
   One challenge in cell-layout migration is to insert additional tracks into a cell when a new process technology allows a narrower track width. However, simply using a compactor with a new set of design rules does not always produce a target layout that meets with the symmetry requirements for some of the metal wires. 
     FIG. 2  illustrates the process of linearly dividing a cell to accommodate more tracks which results in undesirable shifting of metal wires. This example demonstrates how mechanically dividing an existing track layout into a larger number of tracks breaks the symmetry of metal wires with respect to their original tracks. 
   As shown in the top half of  FIG. 2 , before changing track widths a library cell layout  210  contains 10 tracks, each being 0.48 μm wide. Metal wires are placed within tracks  2 ,  6 , and  8 , respectively. Now assume that the new design rules require 12 tracks in a cell. This reduces track width from 0.48 μm to 0.40 μm ((0.48×10)/12=0.40). 
   The lower part of  FIG. 2  illustrates a cell layout  220  after changing the track width. Layout  220  now contains 12 tracks. However, the original metal wire positions have not changed, and hence, they are no longer at the center of their corresponding tracks. For example, the metal wire which is centered within the original 0.48 μm track  8 , is now located between the new 0.40 μm tracks  9  and  10 . This is undesirable because it violates the symmetry requirement for metal wires. 
   One goal of the present invention is to migrate a library cell to new design rules while preserving the original topology, and in doing so, to change the architecture of the cell so that the original track information is not lost. To achieve this goal, one embodiment of the present invention uses a “track insertion” technique in combination with the use of a compaction engine. This technique not only creates evenly distributed tracks after insertion, but also retains the topology and symmetry of the original metal wires within their original corresponding tracks. 
     FIG. 3  illustrates the process of adding tracks to a cell by inserting and expanding infinitesimally narrow tracks in accordance with an embodiment of the present invention. As shown in the top half of  FIG. 3 , cell layout before compaction  310  contains 10 tracks, each being 0.48 μm wide. Tracks  2 ,  6 , and  8  contains metal wires. During operation, the system inserts a number of tracks where additional tracks are needed. In this example, tracks  312  and  314  are inserted between tracks  1  and  2 , and tracks  9  and  10 , respectively. The width of the inserted tracks are set to be infinitesimally narrow, so that the insertion of these tracks does not change the original track width and the symmetry of metal wires. 
   Next, the system feeds this layout (with inserted infinitesimally narrow tracks) into a compactor. Assuming that the new design rules correspond to a track width of 0.26 μm, the compactor can automatically expand the width of the inserted track to 0.26 μm, and reduce the width of the original tracks from 0.48 μm to 0.26 μm while maintaining the same topology. Essentially, this insertion technique enables the user to feed a correct topology into a compactor, and allows the compactor to enforce the new design rules while maintaining the input topology. 
   The output cell layout is shown in the lower half of  FIG. 3 . The cell layout after compaction  320  now contains 12 tracks, each being 0.26 μm wide. The inserted tracks are tracks  322  and  324 . The metal wires remain at the center of their original corresponding tracks. 
   Note that although  FIG. 3  illustrates an example which involves scaling down to a new process technology, the same technique can also be used to modify a cell with the same process technology but with a different number of tracks per cell (i.e., scaling down is not necessary for this technique). The scaling down may occur after modification of the cell layout by a compactor. In addition, the system allows a user to specify preferred locations to insert the infinitesimally narrow tracks, which gives the user more flexibility in cell optimization. 
     FIG. 4  presents a flow chart illustrating the process of inserting and expanding infinitesimally narrow tracks in accordance with an embodiment of the present invention. During operation, the system starts by receiving an input cell layout (step  410 ). The system then sets the process design rules (step  412 ). Next, the system receives the preferred locations to insert one or more infinitesimally narrow tracks from a user (step  414 ). 
   After receiving the preferred locations, the system inserts the infinitesimally narrow tracks at these locations (step  416 ). The system then feeds the layout (with inserted tracks) into a compactor which expands the infinitesimally narrow tracks (step  418 ). Next, the system determines whether the cell layout compacts according to the process design rules (step  420 ). If not, the system allows the user to modify the preferred locations (step  422 ) and re-inserts the tracks into the original cell layout (step  416 ). If the cell compacts successfully, the system outputs the compacted layout (step  424 ). 
   The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.