Abstract:
A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection circuit is configured to generate a first error detection sequence in a first order. The system includes a second error detection circuit. The second error detection circuit is configured to receive the first error detection sequence and an error sequence. The error sequence is received in a second order that is different from the first order when there is data with errors. The second error detection circuit is configured to generate a second error detection sequence that indicates whether the error sequence is generated correctly.

Description:
This application is a continuation of U.S. patent application Ser. No. 10/118,504, filed Apr. 8, 2002 now U.S. Pat. No. 6,868,517, which claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application Ser. No. 60/290,683, filed May 15, 2001, the entire contents of each of which are incorporated by reference herein. 

   BACKGROUND 
   1. Field of the Invention 
   The present invention relates to method and apparatus for checking read errors using two CRC (Cyclic Redundancy Check) stages, and preferably to method and apparatus for detecting errors read from a magnetic disk storage medium in the read channel of a hard disk drive. The present invention also relates to method and apparatus for detecting and correcting such errors. 
   2. Background Information 
   In a data storage system (such as a computer hard disk drive), it is very important that the data read from the data storage system is accurate. One solution is to use an error-correcting code (ECC, such as Reed-Solomon code, etc.) to correct the errors in the data read out from the storage device. However, if the number of errors in the read out data is greater than the designed ECC correction power, there is a small probability that the ECC unit may add errors to the data; this is called miscorrection. A second error detection code, usually a cyclic redundancy check (CRC) code, may be used to detect such miscorrection. Each of U.S. Pat. Nos. 5,157,669; 5,671,237, and 5,909,334 describes circuitry and processes for detecting and correcting errors in digital data read from disk storage media. The contents of these three U.S. patents is incorporated herein by reference. 
   A disk drive data sector typically has 512 bytes of data, denoted B 0 , B 1 , . . . , B 511 . CRC bytes are calculated using all 512 bytes of data. In the following description, 4 CRC bytes will be used for simplicity. However, the techniques described can be easily used with other numbers of CRC bits/bytes, as needed. The techniques described below can be easily modified for other numbers of CRC bytes or other sector sizes. 
   Let C 0 , C 1 , C 2 , C 3  be the 4 CRC bytes. Each byte includes 8 bits. Bits b i,0 , . . . , b i,7  denote the 8 bits of the byte B i , and a similar notation is used for other bytes. Let: 
                   g   ⁡     (   x   )       =       ∑     i   =   0     32     ⁢           ⁢       g   i     ⁢     x   i                 (   1   )               
be the generator polynomial of the CRC code, where g i  is either 0 or 1.
 
   Now, let N I  be the number of interleaves and U i  be XOR sum of data bytes across the interleaves, that is:
 
 U   i   =B   N,xi   +B   N     I     xi+1    . . . +B   N     I     xi+N     I     −1 , and B i =0 if i≧s  (2)
 
where the “+” is a bitwise XOR operation, and s is the number of data bytes per sector. If other data (e.g., SPBA) needs to be protected by ECC and CRC, these data are treated as user data. (Example, U 0 =B 0 +B 1 +B 2  in three interleave case, and U 0 =B 0 +B 1 +B 2 +B 3  in four interleave case).
 
   Let k be the least integer that greater than or equal to the number of data bytes divide by the number of interleaves, that is,
 
 k=┌s÷N   I ┐.  (3)
 
   The CRC encoder calculates the remainder r(x) of the following polynomial: 
                   x   L     ×     (       ∑     i   =   0       k   -   1       ⁢           ⁢       ∑     j   =   0     7     ⁢           ⁢       u       (     k   -   1   -   i     )     ,   j       ·     x       8   ⁢   i     +   j             )             (   4   )               
divided by the generator polynomial of the CRC code, where L is the number of CRC bits. The 32 coefficients of r(x) form the 4 CRC bytes: C 0 =(r 24 , . . . , r 31 ), C 1 =(r 16 , . . . , r 23 ), C 2 =(r 8 , . . . , r 15 ), C 3 =(r 0 , . . . , r 7 ). Note that the bits order of the four CRC bytes does not matter as long as the CRC encoding and CRC checking units agree on the CRC bits order.
 
   In three interleave case, all data are arranged as follows: 
                                                                       First   B 0     B 3     . . .   B 507     B 510     C 1     D 0,0     D 0,1     . . .   D 0,2t−1         interleave       Second   B 1     B 4     . . .   B 508     B 511     C 2     D 1,0     D 1,1     . . .   D 1,2t−1         interleave       Third   B 2     B 5     . . .   B 509     C 0     C 3     D 2,0     D 2,1     . . .   D 2,2t−1         interleave                    
where D i,0 , . . . , D i,2t−1  are the ECC bytes for the ith interleave generated by a Reed-Solomon encoder, and 2t is the number of ECC bytes per interleave.
 
   In the four interleave case, the data arrangement would look like: 
   
     
       
             
             
             
             
             
             
             
             
             
             
           
         
             
                 
             
           
           
             
               First 
               B 0   
               B 4   
               . . . 
               B 508   
               C 0   
               D 0,0   
               D 0,1   
               . . . 
               D 0,2t−1   
             
             
               interleave 
             
             
               Second 
               B 1   
               B 5   
               . . . 
               B 509   
               C 1   
               D 1,0   
               D 1,1   
               . . . 
               D 1,2t−1   
             
             
               interleave 
             
             
               Third 
               B 2   
               B 6   
               . . . 
               B 510   
               C 2   
               D 2,0   
               D 2,1   
               . . . 
               D 2,2t−1   
             
             
               interleave 
             
             
               Fourth 
               B 3   
               B 7   
               . . . 
               B 511   
               C 3   
               D 3,0   
               D 3,1   
               . . . 
               D 3,2t−1   
             
             
               interleave 
             
             
                 
             
           
        
       
     
   
   The three interleave case will be described in the following. All the data are written on the disk in the following “normal” order:
         B 0 , B 1 , . . . , B 511 , C 0 , . . . , C 3 , Do 0 , D 1,0 , D 2,0 , . . . , D 0,2t−1 , D 1,2t−1 , D 2,2t−1          

   In  FIG. 1 , data to be written on a disk is supplied to a CRC encoder  12 , then to an ECC encoder  14 , for writing onto disk  18  with head  16 . When data is read back from the disk  18  with head  22 , the data is often corrupted with errors. After the data is stored in the buffer memory  50 , the ECC unit  24  computes the error values and the error locations. The buffer manager  48  (BM) takes the error values and error locations, and corrects the errors in the memory  50 . Because the CRC unit  26  does not have access to the data after ECC correction by the ECC unit  24 , the CRC unit  26  does the CRC check using the error vector and the data before ECC correction. 
   Another problem is that, the ECC unit  24  generates the error vector in a different order. 
   Instead of generating the error vector in the normal order shown below:
         EB 0 , EB 1 , . . . , EB 511 , EC 0 , EC 1 , EC 2 , EC 3 , ED 0,0 , . . . , ED 2,2t−1 ,
 
the ECC unit  24  generates the errors in a “reversed interleaved order”, shown below:
   ED 0,2t−1 , ED 0,2t−2 , . . . , ED 0,0 , EC 1 , EB 510 , EB 507 , . . . , EB 0  then   ED 1,2t−1 , ED 1,2t−2 , . . . , ED 1,0 , EC 2 , EB 511 , EB 508 , . . . , EB 1  and then   ED 2,2t−1 , ED 2,2t−2 , . . . , ED 2,0 , EC 3 , EC 0 , EB 509 , EB 506 , . . . , EB 2  
 
where the notation EB 0  means the error value at the position of B 0 , that is, data read back is actually RB 0 =(B 0 +EB 0 ). Note that most entries in the error sequence are zeros.
       

   Thus, what is needed is a error detection technique which reliably and accurately detects errors in read digital data. 
   SUMMARY OF THE INVENTION 
   The present invention provides apparatus and method which uses two CRC stages to detect and/or correct errors in read digital data. 
   According to a first aspect of the present invention, structure and/or steps are provided for detecting errors in data stored in a data storage medium, including a correction device or step which receives at least one of (i) data and (ii) data with errors, from the data storage medium, and outputs an error sequence in a first order in the case where data with errors is received. A first CRC device or step is provided which receives at least one of (i) data and (ii) data with errors from the data storage medium, and outputs a CRC checksum. A second CRC device or step then receives both the error sequence and the CRC checksum, and outputs another CRC checksum indicative of whether the correction device or step has generated a correct error sequence. 
   According to a second aspect of the present invention, structure and/or function for determining whether digital data read from a digital data storage device contains errors, includes decoder structure that receives the digital data read from the storage device, the data comprising data bytes and bytes with errors interleaved in a first order, said decoder structure outputting an error sequence in a reversed interleaved order. A first CRC circuit receives the digital data read from the storage device in the first interleaved order, and outputs a remainder. A second CRC circuit receives both the error sequence in reverse interleaved order (generated by the correction device) and the remainder, performs a mathematical operation on the first error sequence and the remainder, and outputs an error signal when the mathematical operation determines that the correction device did not generate the error sequence correctly. 
   According to yet another aspect of the present invention, a read channel for a disk storage medium reads digital data comprising data bytes and bytes with errors, and includes a head for reading the digital data from the disk storage medium. An error correction device is provided which receives the data bytes and the bytes with errors from the disk storage medium, performs an error correction operation on the received bytes and bytes with errors, and outputs a first error sequence in a first order. A first CRC device receives the data bytes and the bytes with errors from the disk storage medium, performs a cyclic redundancy check operation on the received bytes, and outputs a CRC checksum. A second CRC device receives both the error sequence and the CRC checksum, performs a cyclic redundancy check operation on the received error sequence and CRC checksum, and outputs a signal indicative of the presence or absence of an error in the error sequence. 
   In a further aspect of the present invention, read channel apparatus for determining whether digital data read from a digital data storage device is to be error-corrected or re-read includes an error correction decoder that receives the digital data read from the storage device, the data comprising data bytes and bytes with errors interleaved in a first order, said decoder outputting an error sequence in a reversed interleaved order. A first CRC circuit is provided that receives the digital data read from the storage device in the first interleaved order, and outputs a remainder. A second CRC circuit receives both the error sequence in reversed interleaved order (generated by the correction device) and the remainder, performs a mathematical operation on the error sequence and the remainder, and outputs an error signal when the mathematical operation determines that an error exists in the error sequence. Error correction circuitry may also be provided for error-correcting the received data bytes when said second CRC circuit does not output the error signal. Additionally, control circuitry may also be supplied for causing the digital data to be re-read from the digital data storage device when said second CRC circuit outputs the error signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments, in conjunction with the accompanying drawings, wherein like reference numerals have been used to designate like elements, and wherein: 
       FIG. 1  is a schematic block diagram of known circuitry for reading digital data from a disk medium. 
       FIG. 2  is a schematic block diagram of circuitry for reading digital data from a disk medium, according to the present invention. 
       FIG. 3  is a schematic block diagram of prior art circuitry for binary polynomial division. 
       FIG. 4  is a schematic block diagram of a binary division circuit which operates at a byte clock rate with look-forward structure, according the preferred embodiment. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   While the present invention will be described with respect to the read channel of a magnetic disk drive, it is to be understood that the invention has applicability in other storage media such as magnetic tape, optical, magneto-optical, integrated circuits, and the like. The present invention may also find use in other technical fields such as digital transmission error detection in communications systems such as telephony, satellite, Internet, LANs, and the like. Also, the present invention will be described in terms of integrated circuitry residing on a single chip in the read channel of a computer hard disk drive. However, the present invention may be embodied in software, as a series of processing steps, or as a combination of hardware and software, as will be understood by those of ordinary skill in the art. 
   The present invention provides a second CRC decoding stage, which receives outputs from both the ECC decoder and the first CRC stage, to determine whether the error sequence generated in the ECC decoder is correct or not. Referring to  FIG. 2 , the digital data read from the disk is stored in the buffer memory  50  and decoded by Reed-Soloman (R-S) decoder  40 . The error locations and the error values generated by the R-S decoder  40  are passed to FIFO  46 . The buffer manager  48  takes the error locations and error values, and corrects the errors contained in buffer memory  50 , as shown. The read data is also provided to a first CRC  42  where the remainder R g  is calculated. When R g  is zero and the syndromes calculated by the R-S decoder  40  are also zero, there is no error in the read data; where R g  is nonzero, an error exists in the read data. The output of CRC  42  is supplied to a second CRC  44 , as shown. The second CRC  44  receives error locations and error values in an order which is the reverse of the order received by the CRC  42 . The CRC  44  thus calculates R ghat [c hat (x)], where g hat  and c hat  represent the reversed generator polynomial X L g(x −1 ) and the modified reversed error sequence in bits, respectively. When R ghat  is zero, the R-S decoder  40  generated the error locations and error values correctly; where R ghat  is nonzero, the R-S decoder  40  failed to generate the error sequence correctly. 
   The present invention utilizes several additional techniques for accurately detecting errors in read data. First, the CRC- 1   42  and the CRC- 2   44  according to the present invention preferably use a binary code for the error detection rather than using a second Reed-Solomon code. (Both the CRC- 1   42  and the CRC- 2   44  use the same structure as shown in  FIG. 4 ; the difference is in the coefficients of the generated polynomial.) The use of binary code allows for more flexibility in sector length. For example, the disk drive industry is now discussing 4 KB sector size, which would require significant changes to support such long sectors. The binary CRC detector according to the present invention can support sector length roughly up to 64 MB. 
   Second, the “miscorrection detection” according to the preferred embodiment is based on (i) the raw data before ECC correction, and (ii) the error vector (error locations and error values). The CRC- 1  and the R-S decoder use the raw data, and the R-S decoder provides the error vector. This is in contrast to the use of error location and evaluation polynomials. 
   Third, while binary CRC code typically operates at bit clock, the preferred embodiment uses a look-forward technique for the binary CRC polynomial division circuits so that the binary polynomial division circuit operates at byte clock (or other clock rates depending on how many bits are being “looked forward”). Both the CRC- 1  and the CRC- 2  in  FIG. 2  preferably operate at a byte clock rate. 
   Now, the method of error detection with reversed bit sequence will be described. Suppose 
                   d   ⁡     (   x   )       =       ∑     i   =   0       n   -   1       ⁢           ⁢       d   i     ⁢     x   i                 (   5   )               
represents the data sequence in bits, and
   d ( x )= a ( x ) g ( x )+ r ( x )  (6) 
Suppose r(x) (calculated by CRC- 1 ,  42 ) is known, and the data sequence is in reverse order, i.e:
 
                     x     n   -   1       ⁢     d   ⁡     (     x     -   1       )         =       ∑     i   =   0       n   -   1       ⁢           ⁢       d     n   -   1   -     i     x   i           .               (   7   )               
It should be determined whether this “reversed bit sequence” is actually the reversed sequence (i.e., whether the ECC unit  40  generated the error sequence correctly, in reversed order). Note that
   x   n−1   d ( x   −1 )= x   n−1   [a (x −1 ) g ( x   −1 )]+ x   n−1   r ( x   −1 )=[ x   n−L−1   a ( x   −1 )][ x   L   g (x −1 )]+ x   n−1   r ( x   −1 )  (8) 
and therefore
   x   n−1   d ( x   −1 ) x n−1   r   (   x   −1 )=[x n−L−1   a ( x   −1 )][ x   L   g ( x   −1 )].  (9) 
   Thus, the “reversed sequence” is simply modified with the remainder calculated by CRC- 1 , ( 42  in  FIG. 2 ), and a remainder of modified sequence is calculated by dividing by the “reversed generator polynomial” defined as follows:
 
 ĝ ( x )= x   L   g ( x   −1 ),  (10)
 
This remainder should be zero as shown above if the “reversed sequence” is indeed the reversed sequence.
 
   Given the data sequence read back: 
   RB 0 , RB 1 , . . . , RB 511 , RC 0 , . . . , RC 3 , RD 0,0 , RD 1,0 , RD 2,0 , . . . , RD 0,2t−1 , RD 1,2t−1 , RD 2,2t−1    
   and the error sequences generated by the ECC unit  40 : 
   
       
       
         
           ED 0,2t−1 , ED 0,2t−2 , . . . , ED 0,0 , EC 1 , EB 510 , EB 507 , . . . EB 0    
           ED 1,2t−1 , ED 1,2t−2 , . . . , ED 1,0 , EC 2 , EB 511 , EB 508 , . . . , EB 1    
           ED 2,2t−1 , ED 2,2t−2 , . . . , ED 2,0 , EC 3 , EC 0 , EB 509 , EB 506, . . . , EB   2  
 
Notation: Let  B i   =(b i,7 , b i,6 , b i,5 , b i,4 , b i,3 , b i,2 , b i,1 , b i,0 ) be the “bits order reversed” byte of B i .
 
         
       
     
  
   Given the above, the “miscorrection detection” algorithm is described as follows:
         Step 1: CRC- 1 ,  42  calculates the reminder RM0, RM1, RM2, RM3 of the sequence: RB 0 +RB 1 +RB 2 , RB 3 +RB 4 +RB 5 , RB 6 +RB 7 +RB 8 , . . . , RB 510 +RB 511 , RC 0 , RC 1 , RC 2 , RC 3 , with respect to the generator polynomial g(x).   Step 2: CRC- 2  calculates the remainder of the following sequence: 0, 0, ( RM   1 + EC   1 ), 0,  EB   510 ,  EB   507 , . . . ,  EB   0  with respect to the “reversed generator polynomial” ĝ(x).   Step 3: CRC- 2  calculates the remainder of the following sequence: 0, ( EC   2 + RM   2 ), 0, 0,  EB   511 ,  EB   508 , . . . ,  EB   1  with respect to the “reversed generator polynomial” ĝ(x); and add this remainder with the remainder calculated in the Step 2.   Step 4: CRC- 2  calculates the remainder of the following sequence: ( RM3 + EC   3 ), 0, 0, ( RM   0 + EC0 ),  EB   509 ,  EB   506 , . . . ,  EB   2  with respect to the “reversed generator polynomial” ĝ(x); and adds this remainder with the remainder calculated in the Step 2.   If the summation (i.e.: bitwise XOR) of the three remainders calculated in Steps 2, 3, 4 is not all zero, a “miscorrection” is detected by CRC- 2 .       

   The circuitry for implementing the above algorithm ( FIG. 2 ) includes two binary polynomial division circuits ( FIG. 4 ) which operate at symbol clock rates with a look-forward technique which will be described next. The symbol clock rate could be a byte clock rate or another clock rate depending on the symbol size. A “symbol” is a group of bits, such as a byte (if it is a group of 8 bits); or a 10-bit symbol if it is a group of 10 bits. 
   Note that a variation of the above algorithm is also clear:
         Step 1: CRC- 1 ,  42  calculates the reminder RM0, RM1, RM2, RM3 of the sequence: RB 0 +RB 1 +RB 2 , RB 3 +RB 4 +RB 5 , RB 6 +RB 7 +RB 8 , . . . , RB 510 +RB 511 , RC 0 , RC 1 , RC 2 , RC 3 , 0, 0, 0, 0, with respect to the generator polynomial g(x).   Step 2: Calculates the reminder of the following sequence:  RM   3 ,  RM   2 ,  RM   1 ,  RM   0 , 0, 0,  EC   1 , 0,  EB   510 ,  EB   507 , . . . ,  EB   0  with respect to the “reversed generator polynomial” ĝ(x).   Step 3: Calculates the reminder of the following sequence: 0,  EC   2 , 0, 0,  EB   511 ,  EB   508 , . . . ,  EB   1  with respect to the “reversed generator polynomial” ĝ(x); and add this reminder with the reminder calculated in the Step 2.   Step 4: Calculates the reminder of the following sequence:  EC   3 , 0, 0,  EC   0 ,  EB   509 ,  EB   506 , . . . ,  EB   2  with respect to the “reversed generator polynomial” ĝ(x); and add this reminder with the reminder calculated in the Step 2.   If the summation (i.e.: bitwise XOR) of the three reminders calculated in Steps 2, 3, 4 is not all zero, a “miscorrection” is detected.       

   Let 
                   v   ⁡     (   x   )       =       ∑     i   =   0       k   -   1       ⁢           ⁢       v   i     ⁢     x   i                 (   11   )               
represent k bits of data, then the circuit depicted in  FIG. 3  calculates the remainder of:
 
   
     
       
         
           
             
               
                 
                   
                     x 
                     L 
                   
                   ⁢ 
                   
                     v 
                     ⁡ 
                     
                       ( 
                       x 
                       ) 
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   divided 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   by 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     g 
                     ⁡ 
                     
                       ( 
                       x 
                       ) 
                     
                   
                 
                 = 
                 
                   
                     ∑ 
                     
                       i 
                       = 
                       0 
                     
                     L 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       g 
                       i 
                     
                     ⁢ 
                     
                       
                         
                           x 
                           i 
                         
                         ⁡ 
                         
                           ( 
                           
                             
                               Note 
                               ⁢ 
                               
                                 : 
                               
                               ⁢ 
                               
                                 g 
                                 0 
                               
                             
                             = 
                             
                               
                                 g 
                                 L 
                               
                               = 
                               1 
                             
                           
                           ) 
                         
                       
                       . 
                     
                   
                 
               
             
             
               
                 ( 
                 12 
                 ) 
               
             
           
         
       
     
   
     FIG. 3  shows a known polynomial division circuit while  FIG. 4  shows the binary polynomial division circuit which operates at a byte clock rate with a look-forward structure, according to the present invention. In  FIG. 3 , after k bits of data is shifted into Mux  32  at a bit-clock rate, the calculation of the remainder is done and the remainder is stored in the registers  34  and is ready to be shifted out at the bit-clock rate. However, by investigating the polynomial division, it is discovered that, if at time i the content in the registers  34  are ro, r 1 , r 2 , . . . , r L−1 , then at time (i+8) (look-forward by an 8 bit-clock so that the circuit can operate at a byte clock rate) (of course, if the circuit of  FIG. 4  according to the present invention operates at a 10-bit symbol clock rate, then the look-forward can be at 10 bit-clock cycles), then the content of the registers  34  are the summation (implemented as bit-wise XORs) of the content of the registers and the following lines, each line is multiplied (implemented as AND circuits) by the feed-back bit q; therefore if the corresponding feed-back bit q is zero, that line is all zeros): 
   
     
       
             
             
             
             
             
             
             
             
             
             
             
           
         
             
                 
             
           
           
             
                 
                 
                 
                 
                 
                 
                 
               g 7   
               g 8   
               . . . 
               g L−8  × q i   
             
             
                 
                 
                 
                 
                 
                 
               g 6   
               g 7   
               g 8   
               . . . 
               g L−7  × q i+1   
             
             
                 
                 
                 
                 
                 
               g 5   
               g 6   
               g 7   
               g 8   
               . . . 
               g L−6  × q i+2   
             
             
                 
                 
                 
                 
               g 4   
               g 5   
               g 6   
               g 7   
               g 8   
               . . . 
               g L−5  × q i+3   
             
             
                 
                 
                 
               g 3   
               g 4   
               g 5   
               g 6   
               g 7   
               g 8   
               . . . 
               g L−4  × q i+4   
             
             
                 
                 
               g 2   
               g 3   
               g 4   
               g 5   
               g 6   
               g 7   
               g 8   
               . . . 
               g L−3  × q i+5   
             
             
                 
               g 1   
               g 2   
               g 3   
               g 4   
               g 5   
               g 6   
               g 7   
               g 8   
               . . . 
               g L−2  × q i+6   
             
             
               g 0   
               g 1   
               g 2   
               g 3   
               g 4   
               g 5   
               g 6   
               g 7   
               g 8   
               . . . 
               g L−1  × q i+7   
             
             
                 
             
           
        
       
     
   
   The binary polynomial division circuit of  FIG. 4  operates at a byte clock rate (as an example, note that this technique can be easily extended to other bit-widths, like a 10-bit symbol clock rate). The look-forward logic in  FIG. 4  contains logic  34 ′,  36 ′, and  72 ′ to calculate the feed-back bits q i , using the AND and XOR operation described above, i.e., the calculation of the feed-back bits is straightforward. The look-forward block  70 ′ calculates precisely what is shown in the above table. Given this architecture, note that only two such blocks are used, one for the generator polynomial and one for the “reverse generator” polynomial, i.e., one  FIG. 4  circuit would be included in each of the CRC- 1  and CRC- 2 . To reduce the complexity of this circuit, one may also search the following polynomial for 40-bit CRC operates at 10-bit symbol clock:
 
 g ( x )=1 +x   11   +x   25   +x   28   +x   29   +x   40   (13)
 
Note that this polynomial has the following advantages:
         1. Since g 1 = . . . =g 10 =g 30 = . . . =g 39 =0, the “look-forward” of the feed-back bits for both the generator polynomial and the “reverse generator polynomial” are extremely simple: they are simply the last 10 bits in the registers XOR with the current 10-bits of data.   2. Most coefficients are zeros, so the XOR of the lines in Table 1 is simple.       

   When CRC  44  of  FIG. 2  detects an error in the decoded data, it may generate an error signal S e  which may cause the data block to be reread in an attempt to correct the error. In the embodiment where CRC receives the output of CRC  42 , it can use logic to determine whether to output the error signal S e . For example, CRC  44  may output S e  when both R g  and R ghat  are nonzero, or when any (or a predetermined) one of them is nonzero. In a particularly preferred embodiment, CRC  44  takes 4 bytes from CRC  42 , adds 4 bytes to the R-S 40 decoder output, and calculates a remainder R. If R is zero, there is no error; if R is nonzero, an error may exist, and S e  is output. In this way, errors can be more accurately detected, since a CRC operation is performed on both the read data and the error vector generated by the R-S decoder (which generates the error sequence in the reverse interleaved order). With this technique, data errors may be detected approximately 10 9  more reliably, which is especially useful in high reliability applications. 
   Thus, what has been described is apparatus an method and apparatus for accurately detecting errors in received digital data. 
   The individual components shown in outline or designated by blocks in the attached drawings are all well-known in the error detection arts, and their specific construction and operation are not critical to the operation or best mode for carrying out the invention. 
   While the present invention has been described with respect to what is presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.