Abstract:
An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to a couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Description:
RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application No. 60/691,964 filed Jun. 16, 2005 and is related to application: “GAIN ERROR CORRECTION,” U.S. patent application Ser. No. 11/217,155; and application: “OFFSET ERROR CORRECTION,” U.S. patent application Ser. No. 11/217,156; filed concurrently herewith. 

   BACKGROUND 
   I. Field 
   The present disclosure generally relates to gain error correction. More particularly, the disclosure relates to gain error correction in a discrete time circuit, such as an Analog-to-Digital converter (ADC). 
   II. Description of Related Art 
   Normally, in any ADCs, there is a systematic offset error at zero-code and a systematic gain error at full-scale-code. Since these errors are systematic, they can be calibrated after the first round of testing before mass-production of the ADCs. 
   Such errors have in the past been corrected through use of a look-up table including correction codes or through the use of correlated double-sampling. These methods involve more circuitry and demand more power. With ADC&#39;s being utilized in smaller, battery-powered environments, such as a wireless phone, PDA or laptop computer, minimization of circuitry and power conservation to preserve battery life is more important. 
   Accordingly it would be advantageous to provide an improved system for correcting offset errors. 
   SUMMARY 
   In a particular embodiment, a system and method of correcting gain error can include shifting bottom plate voltage of capacitors. 
   In one particular embodiment, an error correction circuit for use with an analog-to-digital converter is provided comprising correction capacitance means and switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC 
   An advantage of one or more embodiments disclosed herein can include effective gain error correction without high power consumption. 
   Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein: 
       FIG. 1  is a general diagram of an exemplary Successive-Approximation-Register ADC (SAR-ADC) of the prior art; 
       FIG. 2  is a diagram illustrating an exemplary operation of an SAR-ADC of the prior art; 
       FIG. 3  is a diagram depicting exemplary offset error and gain error introduced by an SAR-ADC of the prior art; 
       FIG. 4  is diagram illustrating an exemplary embodiment of a gain error correction circuit; 
       FIG. 5  is diagram illustrating an exemplary embodiment of an ADC having a gain error correction circuit of  FIG. 4 . 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows an SAR-ADC  100  of the prior art. ADC  100  samples the analog input signal through the input mux  110  onto a sample-and-hold circuit  120 . Then a comparison is done between reference voltages (from the Digital-to-Analog converter (DAC)  170 ) and the sampled input signal by comparator  130 . The output of comparator  130  is passed onto latch  140  which provides a latched signal to successive approximation register  160  which may be a part of digital interface  150 . Digital interface  150  outputs the resulting digital bit. Based on the comparison result of comparator  130 , a new reference voltage is created by the DAC  170  and second-comparison is done to generate a second bit. This operation continues until all of the desired bits are obtained. Digital interface  150  controls this operation by providing a select signal  151  to input mux  110  and a hold signal  152  to sample-and-hold circuit  120 . Digital interface  150  also may comprise a successive approximation register  160  that generates a compare signal  161 , a comparator clock  162  and a latch clock  163 . Compare signal  161  is fed to DAC  170  (for providing the reference voltages to comparator  130 ). Comparator clock  162  is used to time comparator  130  and latch clock  163  is used to time latch  140 . 
   The input voltage and reference voltage generated by the SAR-ADC of  FIG. 1  is shown in  FIG. 2 . The sampled input voltage is represented by solid line  200 , while the dashed line  210  represents the reference voltages. As shown in  FIG. 2 , bits are extracted from the SAR-ADC of  FIG. 1  in the order starting from Most-Significant-Bit to Least-Significant-Bit until all the bits are obtained. As represented in this graph, VDD is the full-scale voltage and Vgnd is the zero-scale voltage. 
   Referring back to  FIG. 1 , there are various elements that can directly contribute to the offset and gain error, such as (comparator  130 , DAC  170 , and sample-and-hold circuit  120 ). The root-causes of the errors can be categorized as mismatches on the comparator  130 , charge-injection of the sample-and-hold circuit  120  switches, reference-coupling from DAC  170  to sample-and-hold circuit  120  (kickback noise), and parasitic-elements on DAC  170 . These errors are systematic and can be calibrated after system-characterization. 
   A graph depicting an example of the effects of offset and gain errors on the converted code is represented in  FIG. 3 . As can be seen, line  300  represents the ideal output of the ADC where the converted code matches the input signal. Offset error causes the ideal line to shift, represented by line  310 . Gain error causes a change in the slope of the line as represented by line  320 . One or both of these types of errors can exist. 
   Referring now to  FIG. 4 , an exemplary embodiment of a gain error correction circuit  430  is shown. The gain error correction circuit  430  of  FIG. 4  shifts the bottom-plate voltages of some capacitors to provide gain error correction. 
   Sample-and-hold circuit  420  comprises sample-and-hold phase switch  422  and sample-and-hold capacitor  425  (Csh). Other components of sample-and-hold circuit  420  are not shown. The output of sample-and-hold circuit  420  is fed to error correction circuit  430 . Sample-and-hold switch  422 , which may be a CMOS switch for example, controls the sampling operation. Basically, when Φ1 is active high, sample-and-hold phase switch  422  is active (closed) and input signal is passed to the top plate of sample-and-hold capacitor  425  and correction capacitor  435  of error correction circuit  430 . When phase switch  422  is opened, the sampling operation is completed and the hold operation starts. Sample-and-hold capacitor  425  may be comprised of a plurality of unit-sized capacitors (Cu), for instance, two hundred Cu&#39;s. 
   Gain error correction circuit  430  comprises a plurality of correction capacitors  435   a–c  (Ccorr), e.g. The lower plate of each of these correction capacitors  435   a–c  is electrically coupled to a corresponding arrangement of a first switch  440   a–c  coupled to ground and a series arrangement of a second switch  445   a–c  coupled to a third switch  450   a –c. Each of the third switches  450   a–c  is in turn coupled to resistor network  460  at different points so as to provide different reference voltages. For example, third switch  450   a  may be coupled between resistors  470   a  and  470   b  to provide a first reference voltage, Vref 1 . Third switch  450   b  may be coupled between resistors  470   b  and  470   c  to provide a second reference voltage, Vref 2 . Likewise, third switch  450   c  may be coupled between resistors  470   d  and  470   e  to provide a third reference voltage, Vref 3 . 
   In an exemplary embodiment, the reference voltages applied are binary coded and the third switches are activated based upon which bit is high so as to not deteriorate the linearity of the ADC. For example, the bottom plates of correction capacitors  435   a–c  are connected to Vgnd during the sample operation (when Φ1 is active high and first switch  440   a  is activated). During the hold operation (when φ2 is active high), second switches  445   a–c  are activated and one of third switches  450   a–c  is activated so as to shift the bottom plate voltage of the corresponding correction capacitor  435   a–c  to a corresponding reference voltage. 
   Assuming a 10 bit output from the ADC, the largest magnitude of error to be corrected is Ccorr*(Vref 3 +Vref 2 +Vref 1 )/(Csh+3*Ccorr). Obviously, Vref 3  is Vdd/2, Vref 2  is Vdd/4, and Vref 1  is Vdd/8. And also since there are third switches  450   a–c  between the bottom plate of correction capacitors  435   a–c  and the reference voltages Vref 1 – 3 , the shift amount can be easily controlled by the bits (b 10 , b 9 , and b 8 , e.g.) through these third switches  450   a–c . This allows for a higher degree of correction close to full-code. For example, 
   Vcorrection_maximum=Vdd*⅞*Cu/(203Cu)=11.2 mV when b 10 =b 9 =b 8 =1. 
   Vcorrection_minimum=Vdd*⅛*Cu/(203Cu)=1.6 mV when b 10 =b 9 =0 and b 8 =1. 
     FIG. 5  illustrates an exemplary embodiment of an ADC having an error correction circuit of  FIG. 4 . Elements of ADC  500  are similar to those of ADC  100  of  FIG. 1 , however, error correction circuit  430  is included between sample-and-hold circuit  120  and comparator  140 . 
   With the configuration of structure disclosed herein, the systems and methods described herein provides ways to correct gain error within an ADC. As such, the need for gain error correction is obviated. 
   The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to those embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features as defined by the following claims.