Abstract:
A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application 60/795,585 filed Apr. 28, 2006 by the inventors herein and in common assignment herewith. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to semiconductor devices and, more particularly, to the mitigation of thermally induced stress where the materials from which the semiconductor device is fabricated have differing coefficients of thermal expansion. 
         [0003]    Numerous techniques have been developed to fabricate semiconductor packages: in general, a semiconductor die is placed upon a leadframe at a selected location with bonding wires connected between bonding pads on the die and respective ones of the connection leads on the leadframe. Thereafter, the leadframe/die assembly is subject to an encapsulating or molding step by which the leadframe/die assembly is encapsulated with a suitable molding compound to form the chip package. In general, the most common molding compounds are plastic or epoxy-like materials developed to have a thermal coefficient of expansion (CTE) that is sufficiently close to that of the die so that expansion and contraction of the encapsulated structure consequent to varying temperatures does not induce stresses sufficient to cause reliability issues, including, for example, soldered-connection failures, ball-bond or nail-bond connection failures, delamination, lifting, and/or micro-cracking on or within the body of the semiconductor package. 
         [0004]    In general, molding compounds have been developed having coefficients of thermal expansion of appropriate value to reduce stress-induced issues to acceptable levels for most applications. However, molding compounds that are optically transmissive (for use in photo responsive devices) often have CTEs that are larger than usual, in part, because the optical transmissivity characteristic often necessitates larger than usual CTEs. For example, a clear molding compound sold under the NT-332H designation by Nitto Denko Corp. of Osaka, Japan has a CTE 8-40 times that of a conventional molding compound, such SumiKon EME-G700W sold by Sumitomo Bakelite Co. of Tokyo, Japan. As a consequence, chip structures utilizing these types of clear molding compounds are subject to thermal stress issues and have a somewhat higher than usual vulnerability to stress/strain induced problems. 
       SUMMARY OF THE INVENTION 
       [0005]    Leadframe structures for semiconductor dies and packages suitable for use with molding compounds having higher than usual coefficients of expansion are provided with connection leads or pads that effectively reinforce the resulting chip structure by having at least some of the connection leads or pads extend across one or both of the longitudinal and lateral axes of the semiconductor package to structurally “stiffen” the resulting package. In the chip-on-lead (COL) configuration, at least some of the connection pads or leads extend away from the periphery of the package toward one or both of the longitudinal and lateral axes of the package with at least some of the extended connection pads or leads intercepting or crossing the longitudinal and/or lateral axes of the package. As a consequence, those extended portions of the connection pads or leads function to constrain expansion of the molding compound in those medial areas of the package most vulnerable to stress-induced warpage. 
         [0006]    In the context of a split-die paddle configuration in which one or both sub-paddles are used as connection pads or leads, the paddle is divided or split in such as way that portions of sub-paddles extend to, cross-over, or extend beyond the axis separating the sub-paddles. 
     
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0007]      FIG. 1  is a pictorial plan view of a “chip-on-lead” (COL) semiconductor package showing an exemplary die overlying its connection pins with bonding wires connecting contact pads on the die and respective leadframe connection pads or leads; 
           [0008]      FIG. 2  is an example of a semiconductor package in accordance with the present invention with connection pads or leads of various configurations with some portion of some of the connection pads or leads extending across the x-axis and the y-axis; 
           [0009]      FIG. 2   a  is a cross-sectional view of  FIG. 2  taken along line  2   a - 2   a  of  FIG. 2 ; 
           [0010]      FIG. 2   b  is a cross-sectional view of  FIG. 2  taken along line  2   b - 2   b  of  FIG. 2 ; 
           [0011]      FIG. 2   c  is a variant of  FIG. 2  showing only the leadframe arrangement or organization thereof; 
           [0012]      FIG. 3  is an example of a semiconductor package having a split die-paddle; 
           [0013]      FIG. 3   a  is a cross-sectional view of  FIG. 3  taken along line  3   a - 3   a  of  FIG. 3 ; 
           [0014]      FIG. 4  is another example of a semiconductor package having a split die-paddle; 
           [0015]      FIG. 4   a  is a cross-sectional view of  FIG. 4  taken along line  4   a - 4   a  of  FIG. 4 ; and 
           [0016]      FIG. 5  is another variant of a semiconductor package not having a split die-paddle. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0017]      FIG. 1  is a pictorial representation of a typical chip-on-lead (COL) semiconductor package  10  in which the package outline is shown in dotted-line by rectangle  14  with eight leadframe pads or leads  16   a - 16   h  arranged into two leadframe lead-groups with one such lead-group arranged above the x-axis and the other such leadframe lead-group arranged below the x-axis. The leadframe pads lie in a common plane to define a surface for supporting a semiconductior die or chip. 
         [0018]    A semiconductor chip or die D is mount on or atop the plane defined by the various leadframe leads and can be attached thereto by an appropriate non-electrically conducting die-attach adhesive or cement. The die D is formed from a molded epoxy or similar material and includes an upper surface having conductive bonding pads  18  thereon that connect to circuitry on or within the die D. The lower surface of the die D defines a mounting surface for the die D. The bonding pads are typically connected to a respective leadframe pad or lead  16  by a bonding wire  20 . In general, the ends of the bonding wires  20  are attached to their conductive pads or surfaces by ball-bond or nail-bond techniques and the package formed by overmolding with an encapsulant. 
         [0019]    The above-described package is typically mounted on a printed circuit board, with or without an adhesive connection, and the underside of the leadframe leads  16  soldered to conductive pads on printed circuit board. 
         [0020]    In  FIG. 1 , the particular leadframe leads shown are of the “no-lead” type (i.e., there are no leads extending beyond the periphery of the package) and are of the “half-etch” type; the leadframe pins shown are exemplary only and many other types of pins can be used. The eight-pin arrangement of  FIG. 1  is illustrative only and, in practice, a semiconductor package can have many dozens of leadframe contacts. 
         [0021]    In those cases were the die D has optical devices formed in or on the die D and a clear (i.e., optically transmissive) over-molding compound is used as some or all of the encapsulant, the coefficient of thermal expansion of the encapsulant can be 8-40 times higher than the conventional “black” molding compounds. When semiconductor packages having these higher CTEs are subject to higher temperature environments, the relatively high CTE causes the package to “grow” about the x- and y-axis. This thermally induced growth can stress the solder joints between the leadframe contacts and the conductive pads on the printed circuit board and may affect the connection between the ends of the bonding wires  20  and their respective bonding pads  18  on the die D or the leadframe pad or lead. While the thermally induced stress can be a simple shear stress, the manner in which the package is fabricated and the use of components or materials with different CTEs can cause differential stresses that, in turn, cause bending stresses that can add a tensile stress and/or a torsional stress to the shear stress. As can be appreciated, repeated thermal cycling can, with time, cause the initiation and the growth of stress cracks at soldered connections, interfacial delamination, and internal faults within the package. More specifically and as shown in  FIG. 1 , there are several direct paths (i.e., cleave lines) directly across the thin crystalline silicon chip, where the chip is the only structural member with no reinforcement from any underlying portion of the leadframe. For example, each of the x and y axes represent potential cleave lines; potential cleave lines also exist between the leads  16   a - 16   b,    16   c - 16   d,    16   e - 16   f,  and  16   g - 16   h.  Any thermal distortions in the package will be aggravated across these cleave lines and may cause the silicon to crack at these weaker sections. 
         [0022]      FIGS. 2-5  illustrate representative leadframe configurations that address the stress issues discussed above with regard to  FIG. 1 ; in each of these figures the die D is shown in dotted-line illustration without its bonding wires. 
         [0023]      FIG. 2  show the leadframe leads  16   a ′- 16   h ′ having different shapes compared to those of  FIG. 1  with at least some of the leadframe leads crossing the longitudinally aligned x-axis (i.e.,  16   a ′,  16   h ′,  16   d ′, and  16   e ′) and other of the leadframe leads crossing the laterally aligned y-axis (i.e.,  16   c ′ and  16   f ′). As is apparent, the pseudo-random lead-frame edges shown do not align across the silicon chip, so that simple cleave lines are not possible or at least minimized, thus strengthening the overall chip/lead-frame structure. The cross-sectional view of  FIG. 2   a  taken along line  2   a - 2   a  of  FIG. 2  shows the extent of the metal portions (at  22 ,  24 ,  26 , and  28 ) of the leadframe leads crossing the x-axis while the cross-sectional view of  FIG. 2   b  taken along line  2   b - 2   b  of  FIG. 2  shows the extent of the metal portions (at  30 , and  32 ) of the leadframe pins crossing the y-axis. 
         [0024]      FIG. 2   c  is a variant of  FIG. 2  showing only the leadframe arrangement or organization thereof in which those portions of the leadframe pins  16   b ′ and  16   g ′ facing the x-axis have been elongated to cross-over the x-axis and provide additional surrport with the leadframe pins  16   c ′ and  16   f ′ being re-shaped to accomodate the elongated leadframe pins  16   b ′ and  16   g ′. 
         [0025]    The leadframe configuration of  FIG. 2  places a metallic “reinforcement” across the x- and y-axes to reduce, restrain, or constrain thermal growth during temperature cycling; as a consequence, a substantial portion of any induced stress is accommodated by the lead structures shown. In general, the configurations shown in  FIG. 2  and  FIG. 2   c  for the various leadframes pins is exemplary and other configurations are suitable as long as metal extends to, is present at, or crosses-over the principal axes. Additionally, any leadfame lead configuration should, where possible, have gently curved edges and rounded or radiused inside and exterior corners to reduce or eliminate any stress concentrations. 
         [0026]      FIG. 3  illustrates the application of the above-described concept to a chip structure that incorporates a split die paddle where each portion of the die paddle can also function as lead for connection to a contact on a die D (shown in dotted-line illustration and without its bonding wires). As shown in  FIG. 3 , a die paddle  36  is split into two sub-paddles,  34   a  and  34   b,  about the y-axis with portions of each sub-paddle,  36   a  and  36   b,  extending to and crossing over the y-axis; electrical contact with the sub-paddle  34   a  is available at contact  34   c  and with sub-paddle  34   b  at contact  34 d. The cross-sectional view of  FIG. 3   a  (taken along line  3   a - 3   a  of  FIG. 3 ) shows the extent of the metal portions (at  36   a  and  36   b ) of the leadframe leads crossing the y-axis. As shown, those portions of the sub-paddles facing each other at the y-axis have rounded or radius corners to reduce or eliminate any stress concentrations and can be viewed as having respective “L” configurations. 
         [0027]    As in the case of the leadframe configuration of  FIG. 2 , the configuration of  FIG. 3  places a metallic “reinforcement” across the y-axes to constrain thermal growth during temperature cycling to limit warpage in both the x- and the y-directions; as a consequence, a substantial portion of any thermally induced stress is accommodated by the leadframe configurations shown. It can also be seen that the dog-leg lead-frame separation of  FIG. 3  accomplishes the same effect of eliminating simple cleave lines in the silicon chip. 
         [0028]      FIG. 4  illustrates a variant of the split die paddle of  FIG. 3  in which the die paddle is split along a diagonal or oblique line L (e.g., at an angle of about 30° relative to the y-axis) where each portion of the die paddle can also function as lead for connection to a contact on a die. As shown in  FIG. 4 , a die paddle  38  is split into two sub-paddles,  38   a  and  38   b,  about the y-axis with portions of each sub-paddle,  38   a  and  38   b,  extending to and crossing over the y-axis; electrical contact with the sub-paddle  38   a  is available at contact  38   c  and with sub-paddle  38   b  at contact  38   d.  The cross-sectional view of  FIG. 4   a  (taken along line  4   a - 4   a  of  FIG. 4 ) shows the extent of the metal portions (at  40   a  and  40   b ) of the leadframe pins crossing the y-axis. As shown, those portions of the sub-paddles facing each other at the y-axis have rounded or radius corners to reduce or eliminate any stress concentrations. 
         [0029]    The split die-paddle configuration described above allow for each sub-paddle to also function as a contact lead; in the case of the embodiments of  FIGS. 3 and 4 , these sub-paddle contact leads are shows at the left and right ends of the structure. 
         [0030]      FIG. 5  provides for the same termination capabilities as in the previous figures (e.g., 8 pins); however, avoids the split die paddle, giving the silicon chip solid reinforcement throughout the package with no unsupported cleave lines. As shown, a die paddle  42  sub-tends a substantial area between the contact pins but is widened at its right end and also includes a “cut-out”  44  in which the contact lead  46  is placed. The cut-out  44  functions to define two rightwardly extending “legs”  50  and  52 . The die paddle  42  provides substantial metal across the x- and y-axis while, at the same time, accommodating a contact lead  46  on the right side thereof; electrical contact with the die paddle  42  can be made via the contact  54  on the left side thereof or the ends of the rightwardly extending “legs”  50  and  52 . One advantage of the arrangement of  FIG. 5  is that there is no need for a non-conductive die attach material as typically used in conventional chip-on-lead (COL) structures since pin  46  is isolated from the die paddle  42 . If conductive die attach material is used, then pin  54 , which is common to die paddle  42  must be chosen at the same DC potential as the back of die substrate, usually the negative power voltage. 
         [0031]    The “split-die-pad” variants of  FIGS. 3-5  assist in minimizing X and Y package dimensions and thus reduce overall stresses in the high CTE optical packages while also maintaining a requisite 8-pin connections at a reasonable 0.65 mm pad pitch in a conventional MFN/QFN package form-factor and process. 
         [0032]    As will be apparent to those skilled in the art, various changes and modifications may be made to the illustrated embodiment of the present invention without departing from the spirit and scope of the invention as determined in the appended claims and their legal equivalent.