Abstract:
Systems and methods that provide clock jitter compensation architectures that improve the performance of direct radio frequency (RF) receivers by injecting a calibration tone into the received radio frequency (RF) signals in order to help identify and then compensate for the clock jitter noise. After injecting the tone, the jitter noise going through the direct RF bandpass sampling receiver is estimated using a narrow bandwidth filter, and the received signals are further processed and demodulated depending on the Nyquist zone of the received signal. The relative modulation factor for the modulation is computed and then applied to the Nyquist zone to de jitter that particular Nyquist zone.

Description:
[0001]    The present application claims priority to co-pending U.S. provisional patent application Ser. No. 61/203,114 filed Dec. 18, 2008 and entitled “SYSTEM AND METHOD FOR CLOCK JITTER COMPENSATION IN DIRECT RF RECEIVER ARCHITECTURES”, by Fudge et al., the disclosure of which is incorporated herein by reference in its entirety. 
       RELATED APPLICATIONS 
       [0002]    The present provisional application is related in subject matter to concurrently filed patent application Ser. No. ______ entitled “SYSTEM AND METHOD FOR IMPROVED SPUR REDUCTION IN DIRECT RF RECEIVER ARCHITECTURES” by Fudge et al., which is incorporated herein by reference in its entirety, and to Provisional Patent Application Ser. No. 61/203,115 filed Dec. 18, 2008 and entitled “SYSTEM AND METHOD FOR IMPROVED SPUR REDUCTION IN DIRECT RF RECEIVER ARCHITECTURES”, by Fudge et al., which is also incorporated herein by reference in its entirety. 
     
    
     TECHNICAL FIELD OF THE INVENTION 
       [0003]    This invention relates to receiver and transmitter architectures for efficient wireless communications and, more particularly, to direct radio frequency (RF) receiver architectures. 
       BACKGROUND 
       [0004]    A wide variety of signals and related protocols exist for the use of radio frequency (RF) signals in communication systems and other devices, such as radar systems. Prior receiver architectures for such RF communication systems are described in U.S. Pat. No. 7,436,910, entitled “DIRECT BANDPASS SAMPLING RECEIVERS WITH ANALOG INTERPOLATION FILTERS AND RELATED METHODS,” and U.S. Pat. No. 7,436,912, entitled “NYQUIST FOLDED BANDPASS SAMPLING RECEIVERS AND RELATED METHODS,” each of which is hereby incorporated by reference in its entirety. 
         [0005]      FIG. 1  (Prior Art) shows an embodiment for a reconfigurable direct RF bandpass sampling receiver (RDRFBSR), such as those described in U.S. Pat. No. 7,436,910. As depicted, the radio frequency (RF) input signal  116  is first passed through a low noise amplifier (LNA)  102 . The output  130  of the LNA  102  is provided to a tunable/switchable bandpass filter  104 , which can be configured to have a tunable center frequency and a programmable bandwidth dependent upon one or more filter control signals  105 . The filtered output signal  132  is received by the non-quantizing sampler  204 , which samples the signals at times determined by the RF sample clock  212  resulting in a discrete time continuous voltage sampled signal. The sampled signal is then filtered by the interpolation filter, resulting in a continuous time continuous voltage signal, which is then sampled and quantized by the ADC  210  at sample rate determined by the ADC Sample Clock  214  after optional amplification by the IF amp  208 . The digital output signals from the ADC  210  are then further processed by digital signal processing (DSP) circuitry  114  to produce baseband in-phase path (I) and quadrature path (Q) signals. One limitation of this architecture, however, is that for very high RF input signals and operational conditions, the RF Sample Clock  212  jitter is amplified and may result in subsequent signal distortion in the form of signal spreading in the output signals, leading to significantly reduced SNR. 
         [0006]      FIG. 2  (Prior Art) shows an embodiment of a Nyquist folding receiver (NYFR), such as those described in U.S. Pat. No. 7,436,912. The NYFR is similar to the RDRFBSR. Starting with the RDRFBSR, the anti-alias filter is replaced with a wideband pre-select filter, and the constant RF sample clock is replaced with a frequency modulated sample clock that samples the RF input signal at the zero-crossing rising voltage of a frequency modulated clock. In  FIG. 2 , an ultra wideband (UWB) front end filter  302  is present in front of a non-quantizing RF sampler  204  to allow reception of multiple Nyquist zones. The non-quantizing RF sampler  204  uses modulated RF sample clock circuitry  304 , and is followed by an analog interpolation filter  206  and an analog to digital converter (ADC)  210 . The ADC  210  receives an ADC sampling clock signal  214  from ADC clock circuitry. The wideband filter  302  has a bandwidth that is wide enough to pass multiple Nyquist zones where the Nyquist zones are determined by the RF sampling clock frequency for the non-quantizing RF sampler  204 . The modulated sample clock circuitry  304  provides an RF sampling clock signal to the non-quantizing RF sampler  204  that is not constant and is adjusted or modulated during sampling. As with the RDRFBSR, the NYFR can suffer from clock jitter associated with the RF sampling. 
         [0007]      FIG. 3  (Prior Art) shows the input/output characteristics of the NYFR. In particular, an input signal has an induced modulation MΘ(t), where M depends on the Nyquist zone in which the signal originated. Thus, a broadband RF input can be sampled at far less than Nyquist, allowing individual signals from different Nyquist zones to alias (or fold) into the analog interpolation filter. The original RF frequency from which each signal aliased can then be determined without ambiguity by measuring M. 
         [0008]      FIG. 4  (Prior Art) illustrates the principles of the NYFR via a frequency domain example. The Fourier transform of the pulse train, shown in the right side of  FIG. 4  (Prior Art), is convolved with the input spectra after the wideband RF filter, which is shown at top left. It is noted that the Fourier transform of the pulse train consists of a series of impulse-like signals with increasing width. For example, the width at 0f s1  is 0; the width at 1f s1  is the modulation bandwidth; the width at 2f s1  is 2× the modulation bandwidth; etc. When these are convolved with the input spectra, the resulting spectra has modulation bandwidth corresponding to Nyquist zone of origin as shown in the lower left hand side of  FIG. 4  (Prior Art). It is noted that the numbers on the left side of  FIG. 4  (Prior Art) correlate to the numbers in  FIG. 2  (Prior Art) and show the positions within the circuitry where the signals in  FIG. 4  (Prior Art) are present. 
         [0009]    As indicated above, the RDRFBSR and NYFR architectures can suffer from clock jitter due to the direct RF sampling. Prior solutions to address clock jitter have attempted to provide model-based approximation techniques that assume the signal takes a known form and then applies a best fit of the data to the known form (e.g., linear least squares, polynomial least squares, etc.). Improved solutions, however, are needed, as these techniques are limited in applicability, difficult to implement, and are computationally expensive. 
       SUMMARY OF THE INVENTION 
       [0010]    The systems and methods disclosed herein provide clock jitter compensation architectures that improve the performance of direct radio frequency (RF) receivers. These disclosed clock jitter compensation architectures advantageously inject a high frequency tone into the received radio frequency (RF) signals in order to help identify and then compensate for the clock jitter noise. After injecting the tone, the jitter noise going through the direct RF bandpass sampling receiver is estimated using a narrow bandwidth filter. This estimation technique is possible because the jitter noise is not white noise, but is actually shaped, as described in more detail below, and because all signals have the same induced jitter phase modulation with only an integer scale factor on the jitter phase varying with Nyquist zone. After the jitter noise is estimated, the received signals are further processed and demodulated similar to the modulation/demodulation used for Nyquist folded receivers (NYFR), where the modulation/demodulation depends on the Nyquist zone of the received signal. With respect to the clock jitter compensation architectures, the relative modulation factor for the modulation is computed and then applied to the Nyquist zone to de jitter that particular Nyquist zone (i.e., to simultaneously de jitter all signals from a given Nyquist zone). Other features and variations can be implemented, as desired, and a related methods and systems can be utilized, as well. 
         [0011]    In one respect, disclosed herein is receive path circuitry, including: bandpass sampling receiver circuitry configured to receive a sampling clock and to sample a combined radio frequency (RF) signal using the sampling clock to produce a digital output signal, the combined RF signal including a RF input signal and an injected calibration tone, the calibration tone having known characteristics, and the sampling clock including associated source clock jitter phase modulation Θ(t) that induces jitter phase modulation M 1 Θ(t) on the calibration tone and jitter phase modulation M 2 Θ(t) on the RF input signal of the digital output signal from the bandpass sampling receiver circuitry; and processing circuitry coupled to receive and process the digital output signal from the bandpass sampling receiver circuitry by using the known characteristics of the calibration tone, to estimate the induced jitter phase modulation M 1  Θ(t) on the calibration tone and to identify and compensate for the source clock jitter phase modulation Θ(t) in the digital output signal from the bandpass sampling receiver circuitry based on the estimated induced jitter phase modulation M 1 Θ(t). 
         [0012]    In another respect, disclosed herein is a method for processing a radio frequency (RF) input signal, including: combining a radio frequency (RF) input signal with an injected calibration tone having known characteristics to produce a combined signal including the RF input signal and the calibration tone; bandpass sampling the combined signal according to a sampling clock to produce a bandpass sampled digital signal, the sampling clock including associated source clock jitter phase modulation Θ(t) that induces jitter phase modulation M 1 Θ(t) on the calibration tone and jitter phase modulation M 2 Θ(t) on the RF input signal of the digital signal; and using the known characteristics of the calibration tone to estimate the induced jitter phase modulation M 1  Θ(t) on the calibration tone and to identify and compensate for the source clock jitter phase modulation Θ(t) in the bandpass sampled digital signal based on the estimated induced jitter phase modulation M 1 Θ(t). 
         [0013]    In another respect, disclosed herein is receive path circuitry, comprising: combiner circuitry configured to combine a radio frequency (RF) input signal with an injected calibration tone having known characteristics to produce a combined output signal including the RF input signal and the calibration tone; bandpass sampling receiver circuitry coupled to receive the combined output signal from the combiner circuitry, the bandpass sampling receiver circuitry configured to receive a sampling clock and to sample the combined output signal using the sampling clock to produce a digital output signal, the sampling clock including associated source clock jitter phase modulation Θ(t) that induces jitter phase modulation M 1 Θ(t) on the calibration tone and jitter phase modulation M 2 Θ(t) on the RF input signal of the digital output signal from the bandpass sampling receiver circuitry; and processing circuitry coupled to receive and process the digital output signal from the bandpass sampling receiver circuitry by using the known characteristics of the calibration tone to estimate the induced jitter phase modulation M 1 Θ(t) on the calibration tone and to identify and compensate for the source clock jitter phase modulation Θ(t) in the digital output signal from the bandpass sampling receiver circuitry based on the estimated induced jitter phase modulation M 1 Θ(t). 
         [0014]    In another respect, disclosed herein is a method for processing a radio frequency (RF) input signal, including: combining a radio frequency (RF) input signal with an injected calibration tone having known characteristics to produce a combined signal including the RF input signal and the calibration tone; filtering the combined signal with a tunable bandpass filter to produce a filtered combined signal; bandpass sampling the filtered combined signal according to a sampling clock to produce a bandpass sampled digital signal, the sampling clock including associated source clock jitter phase modulation Θ(t) that induces jitter phase modulation M 1 Θ(t) on the calibration tone and jitter phase modulation M 2 Θ(t) on the RF input signal of the bandpass sampled digital signal; and using the known characteristics of the calibration tone to estimate the induced jitter phase modulation M 1 Θ(t) on the calibration tone and to identify and compensate for the source clock jitter phase modulation Θ(t) in the bandpass sampled digital output signal based on the estimated induced jitter phase modulation M 1 Θ(t). 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0015]    It is noted that the appended drawings illustrate only exemplary embodiments of the invention and are, therefore, not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
           [0016]      FIG. 1  (Prior Art) is a block diagram for a reconfigurable direct RF bandpass sampling receiver (RDRFBSR). 
           [0017]      FIG. 2  (Prior Art) is a block diagram for a Nyquist folding receiver (NYFR). 
           [0018]      FIG. 3  (Prior Art) provides an explanation of mathematical expressions associated with the NYFR signals. 
           [0019]      FIG. 4  (Prior Art) is a signal diagram for signal processing provided by the NYFR of  FIG. 2 . 
           [0020]      FIG. 5  is a block diagram for a receiver architecture including clock jitter compensation according to one exemplary embodiment. 
           [0021]      FIG. 6  is a block diagram for a receiver architecture including clock jitter compensation according to one exemplary embodiment. 
           [0022]      FIG. 7  is a block diagram of a bandpass sampling receiver according to one exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    The systems and methods disclosed herein provide clock jitter compensation architectures that improve the performance of direct radio frequency (RF) receivers. For these clock jitter compensation architectures, a high frequency tone is injected into the receive radio frequency (RF) signals to allow the clock jitter noise to be identified and compensated for in the output signals provided by the receiver. 
         [0024]    It is noted that the clock jitter compensation architectures described herein relate to spur reduction architectures described in U.S. Provisional Patent Application Ser. No. 61/203,115 filed Dec. 18, 2008 and in the concurrently filed U.S. patent application Ser. No. ______ entitled “SYSTEM AND METHOD FOR IMPROVED SPUR REDUCTION IN DIRECT RF RECEIVER ARCHITECTURES” by Fudge et al., each of which is hereby incorporated by reference in its entirety. As indicated above, the clock jitter compensation architectures described herein are also related to the receiver architectures described in U.S. Pat. No. 7,436,910, entitled “DIRECT BANDPASS SAMPLING RECEIVERS WITH ANALOG INTERPOLATION FILTERS AND RELATED METHODS,” and U.S. Pat. No. 7,436,912, entitled “NYQUIST FOLDED BANDPASS SAMPLING RECEIVERS AND RELATED METHODS,” each of which is hereby incorporated by reference in its entirety. 
         [0025]      FIG. 5  provides a block diagram of a clock jitter compensation embodiment of the present invention applied to the case of the RDRFBSR architectures, such as those described in U.S. Pat. No. 7,436,910. This clock jitter compensation is a unique application similar in some respects to the narrow-band modulation used in the NYFR architectures disclosed in U.S. Pat. No. 7,436,912. As such, the signal processing set forth in  FIG. 4  would be applicable to the clock jitter compensation architecture of  FIG. 5 . However, for  FIG. 5 , the narrow-band frequency modulation of the clock is not deliberate; rather, it is a result of clock jitter. In the NYFR architecture, a known modulation function is induced on the clock, and the modulation scale factor M is not known. With respect to  FIG. 5 , to de jitter the data, a calibration signal (i.e., pilot tone) is applied to a known Nyquist zone (hence M is known), and the unknown modulation function is then determined. Once the unknown modulation function is determined, the corresponding de-modulation function can be applied to remove the effects of jitter. If the signal band of interest is in a different Nyquist zone from the calibration tone, the estimated de-modulation function is then scaled by the ratio of the modulation scale factor for the Nyquist zone of interest divided by the modulation scale factor for the Nyquist zone of the modulation zone. 
         [0026]    Looking back to  FIG. 5 , embodiment  500  will now be described in more detail. An RF input signal is combined with the calibration tone  503  using combiner  502 . The combined output is then processed by a bandpass sampling receiver  504 , such as described in U.S. Pat. No. 7,436,910, which uses a bandpass sampling clock  506  to sample the RF input signals. As shown in  FIG. 5 , this bandpass sampling clock  506  is typically imperfect and has some clock jitter associated with it. The digital output  505  of the receiver  504  is then provided to further processing blocks to provide the jitter identification and compensation provided by the architectures described herein. It is also noted that the mathematical expressions for the signals being processed and utilized are provided in  FIG. 5 . 
         [0027]    In a first path, the digital output  505  is provided to processing block  508  that operates to estimate the induced jitter phase modulation M 1 Θ(t) on the calibration tone  503  that was injected into the RF input signal. Processing block  510  then processes the signals to estimate the source clock jitter phase modulation Θ(t). Next, processing block  512  processes the signals to estimate the induced jitter phase modulation M 2 Θ(t) on the RF input signals. Further, processing block  514  processes the signals to compute a de jitter phase modulation function that is provided to block  516 . 
         [0028]    It is noted that modulation scale factor M 1  for the calibration tone  503  will typically be equal to modulation scale factor M 2  for the RF input signals in embodiments such as  FIG. 5  in which an RF input signal is combined with the calibration tone  503  prior to bandpass filter circuitry of bandpass sampling receiver  504 , since the calibration tone  503  and RF input signals would be in the same Nyquist zone. However, it is not required that the calibration tone  503  and RF input signals be in the same Nyquist zone, e.g., a calibration tone  503  may be injected slightly out of band of bandpass filter circuitry of bandpass sampling receiver  504  and it might not be strongly attenuated. In such a case, M 1  may not be equal to M 2 . 
         [0029]    In a second path, the digital output  505  is provided to processing block  518  that operates to compute a complex baseband representation of the digitized RF input, which is provided to block  516 . 
         [0030]    Processing block  516  then applies the de jitter phase modulation function from processing block  514  to the complex baseband representation from block processing  518  to output a de jitter complex baseband representation of the RF input. In other words, processing block  516  provides an output for which the clock jitter noise due to the imperfect bandpass sampling clock  506  has been compensated. 
         [0031]    Although a calibration tone  503  may be injected prior to the tunable bandpass filter of a bandpass sampling receiver  504  as shown and described in relation to  FIG. 5 , it will be understood that the calibration tone may alternatively be injected after the tunable bandpass filter of bandpass sampling receiver  504  as shown in  FIGS. 6 and 7  so that a single calibration tone may be used, i.e., given that the calibration tone will not have to change each time the tunable bandpass filter is configured to receive a different band of interest. In this regard,  FIG. 7  is a block diagram of a bandpass sampling receiver  504  configured with components similar to components of  FIG. 1 . However, a calibration tone  503  is injected after tunable bandpas&#39;s filter  104  and before non-quantizing sampler  204 . In such an implementation, modulation scale factor M 1  for the calibration tone  503  is not equal to modulation scale factor M 2  for the RF input signals since the calibration tone  503  and RF input signals are in different Nyquist zones. 
         [0032]    Referring to  FIG. 7  in detail, a RF input signal  116  is first passed through a low noise amplifier (LNA)  102 . The output  130  of the LNA  102  is provided to a tunable/switchable bandpass filter  104 , which may be configured to have a tunable center frequency and a programmable bandwidth dependent upon one or more filter control signals  105 . Calibration tone  503  is injected as shown into the filtered output signal  132  from tunable bandpass filter  104 , which is then received by the non-quantizing sampler  204 . The non-quantizing sampler  204  samples the signals at times determined by the RF sample clock  212  resulting in a discrete time continuous voltage sampled signal. The sampled signal is then filtered by the interpolation filter, resulting in a continuous time continuous voltage signal, which is then sampled and quantized by the ADC  210  at sample rate determined by the ADC Sample Clock  214  after optional amplification by the IF amp  208 . The digital output signals from the ADC  210  are then further processed by digital signal processing (DSP) circuitry  114  to produce baseband in-phase path (I) and quadrature path (Q) signals of digital output  505 . 
         [0033]    As noted above, a Nyquist folded receiver, such as those described in U.S. Pat. No. 7,436,912, could also be used as the receiver  504 . The process to de jitter signals for a NYFR architecture, such as described in U.S. Pat. No. 7,436,912, is similar to that for the RDRFBSR architecture, such as described in U.S. Pat. No. 7,436,910. The only difference is that the modulation term for the calibration tone includes a known modulation component in addition to an unknown clock jitter modulation component. The known modulation component can be used to estimate the unknown clock jitter modulation component. Alternatively, because it is not necessary to separate clock jitter from deliberate modulation in the NYFR architecture, both can be lumped together, and the combined modulation can be treated as the NYFR modulation. This NYFR modulation can then be used to de-modulate signals from the other Nyquist zones and/or can be used to estimate the Nyquist zone for the signals by comparing total induced modulation function from a unknown Nyquist zone with known total induced modulation function from a known Nyquist zone. 
         [0034]    It is noted that the calibration tone  503  in either case (RDRFBSR or NYFR) is preferably set in a high enough Nyquist zone so as to have a measurable component of jitter modulation. The induced jitter modulation increases with Nyquist zone. If a low Nyquist zone calibration tone is used, the jitter modulation will be very small relative to other noise sources, and an accurate estimate of the jitter modulation may not be possible. It is further noted that the jitter compensation architecture also applies to any type of direct RF sampling architecture in which the jitter phase modulation function is the same for all signals to within an integer scale factor, including architectures that use any form of harmonic sampling (including pulse-based sampling) followed by a harmonic selection or isolation filter (including a low pass or bandpass filter). 
         [0035]    The clock jitter compensation architectures described above provide unique and advantageous features. Unique features include the use of jitter compensation as a companion technique to modulation and NYFR demodulation. Advantages include providing a simple approach for significantly removing the effects of jitter thereby increasing signal-to-noise-ratio (SNR) performance and improving performance in nearly all applications for direct RF receivers (e.g., communications, electronic intelligence, radar, etc.) and/or Nyquist folding receivers (e.g., electronic intelligences, electronic support systems, etc.). Further, it is noted that in an alternative embodiment, rather than convert to a complex baseband representation, as discussed above, a real representation could be utilized instead. 
         [0036]    Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the present invention is not limited by these example arrangements. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the implementations and architectures. For example, equivalent elements may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.