Abstract:
Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is related to the following U.S. Patent Applications, which are hereby incorporated by reference herein in their entirety: 
     United States patent application Ser. No. 12/101,441, filed herewith titled “Controlling Impedance and Thickness Variations for Multilayer Electronic Structures”. 
     United States patent application Ser. No. 12/101,455, filed herewith titled “Controlling Impedance and Thickness Variations for Multilayer Electronic Structures”. 
     BACKGROUND 
       FIGS. 1A-1C  illustrate the current state of the art in developing at least one type of multilayer electronic structure. A core consists of at least one layer of copper, a layer of bonding film (e.g., FR4, etc.), and a second layer of copper. Selected locations of the second layer of copper are removed (e.g., etched), leaving intact copper signal traces that provide for the internal circuitry of the electronic structure. Bonding film is laminated between a first core and a second core to provide a continuous multilayer electronic structure. When signal trace density changes (i.e., in a first location on the core there are numerous signal traces, and in a second location there are very few, if any, signal traces,) the distance from the signal traces to the reference ground layer varies across the PCB. This variation of distance results in variations in mechanical thickness, impedance, and electrical performance of the multilayer electronic structure. 
     For example see  FIG. 1A .  FIG. 1A  depicts a prior art multilayer electronic structure having a single isolated signal trace. For instance if the signal trace is 4 mils wide, 0.7 mils thick, and the bonding film is 4 mils thick, after lamination the distance from the top of the signal trace to the adjacent reference ground layer approaches 3.3 mils. 
     Alternatively see  FIG. 1B .  FIG. 1B  depicts a prior art multilayer electronic structure having a signal trace nestled between two wide traces (e.g., power signal trace, ground signal trace, etc.). For instance if the signal trace is 4 mils wide, 0.7 mils thick, and the bonding film is 4 mils thick, after lamination the distance from the top of the signal trace to the adjacent reference ground layer approaches 4.0 mils. 
     Alternatively see  FIG. 1C .  FIG. 1C  depicts a prior art multilayer electronic structure having a single trace nestled between two other signal traces. For instance if each signal trace is 4 mils wide, 0.7 mils thick, and the bonding film is 4 mils thick, after lamination the distance from the top of the signal traces to the adjacent reference ground layer approaches 3.65 mils. 
     In the examples depicted in  FIGS. 1A ,  1 B, and  1 C, the distance from the top of the signal traces to the adjacent reference ground layer by itself leads to impedance differences of 48-51-53 Ohms respectively. 
     In the current state of the art, impedance and mechanical (i.e., thickness) tolerance requirements are tight and may become tighter. Currently impedance tolerances of +/−10% are typical (e.g., 50 Ohms +/−5 Ohms). In the future, impedance tolerances of +/−7.5% or 5.0% may become more common. In the examples depicted in  FIGS. 1A ,  1 B, and  1 C, 50% of the +/−10.0% tolerance is taken up by the effect of the distance variations from the top of the signal trace to the adjacent reference ground layer. 
     SUMMARY 
     The present invention generally relates to multilayer electronic structures (i.e., printed circuit board (PCB), microstrip, coplanar PCB, stripline, etc., or any such equivalent multilayer electronic structures) and method(s) relating to the multilayer electronic structures. 
     Herein multilayer electronic structures may be referred to generally as electronic structures. In other words, the terms multilayer electronic structure, electronic structure, PCB, microstrip, etc. may be used interchangeably. 
     Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. 
     In an embodiment of the present invention characteristic impedance variations due to non uniformity in both signal density and dielectric bonding film thickness are improved. In other words, the cross section thickness across the entire electronic multilayer electronic structure is more uniform. 
     In another embodiment a method of multilayer electronic structure manufacture comprises providing a core layer with at least one signal trace thereupon; applying characterized fill to the core, adjacent to the at least one signal trace, and; laminating a dielectric layer to the core. In another embodiment the volume of characterized fill is approximately equal to the volume of signal trace material that is removed in the signal trace creation process. 
     In another embodiment the method of multilayer electronic structure manufacture further comprises determining an optimum impedance and adjusting the amount of characterized fill to be added based on the optimum impedance. In another embodiment the method of multilayer electronic structure manufacture further comprises determining an optimum via size or via density and adjusting the amount of characterized fill to be added based on the optimum via size or via density. In this embodiment the via size or via density relates to a via(s) electrically formed/connected to a signal trace. 
     In another embodiment a multilayer electronic structure comprises a dielectric layer, a core layer having at least a first location with at least one signal trace thereupon, and a second location with no signal traces thereupon, and a characterized fill layer applied upon the second location. In another embodiment the amount of characterized fill applied is inversely proportional to the volume of the at least one signal trace. In another embodiment the amount of characterized fill applied is approximately equal to a volume equal to the area of the second group multiplied by the height of the at least one signal trace. In another embodiment the amount of characterized fill applied is based on an optimum impedance. In another embodiment the optimum impedance at least in part relates to via geometry. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. 
       It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
         FIG. 1A  depicts a prior art multilayer electronic structure section having a single isolated signal trace. 
         FIG. 1B  depicts a prior art multilayer electronic structure section having a signal trace nestled between two wide signal traces. 
         FIG. 1C  depicts a prior art multilayer electronic structure section having a single trace nestled between two other signal traces. 
         FIG. 2A  depicts an exploded view of the components of a multilayer electronic structure, utilizing characterized fill, according to an embodiment of the present invention. 
         FIG. 2B  depicts the multilayer electronic structure of  FIG. 2A  according to an embodiment of the present invention. 
         FIG. 3A  depicts an exploded view of the components of a multilayer electronic structure, utilizing characterized fill, according to an embodiment of the present invention. 
         FIG. 3B  depicts the multilayer electronic structure of  FIG. 3A  according to an embodiment of the present invention. 
         FIG. 3C  depicts an isometric exploded view of various layers of a particular multilayer electronic structure. 
         FIG. 4  depicts a process of generating equalization data used to equalize thickness and/or impedance tolerances in multilayer printed circuit cards, according to an embodiment of the present invention. 
         FIG. 5A  depicts a top view of a section of a multilayer electronic structure having a signal trace thereupon wherein cells are utilized to determine the signal trace density. 
         FIG. 5B  depicts a side view a section of a multilayer electronic structure having three signal traces thereupon wherein cells are utilized to determine thickness and/or impedance. 
         FIG. 6  depicts a process of generating equalization data utilizing the signal trace density of particular layers of multilayer printed circuit card, according to an embodiment of the present invention. 
         FIG. 7  depicts a process of generating equalization data utilizing the thickness/impedance of a particular layer(s) of a multilayer printed circuit card, according to an embodiment of the present invention. 
         FIG. 8  depicts an alternative method of multilayer electronic structure manufacture according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings, wherein like numbers denote like parts throughout the several views. Please refer to  FIG. 2A .  FIG. 2A  depicts an exploded view of the components of a multilayer electronic structure, utilizing characterized fill  46 , according to an embodiment of the present invention. The multilayer electronic structure comprises a first layer (e.g., core  20 , etc.), a second layer (e.g., copper ground  15 , etc.), and characterized fill layer  46  utilized to bond the first and second layers together. For example, characterized fill layer may bond two different core  20  layers together, or may bond a single core  20  layer with a copper ground  15  layer. Other layer types may be bonded together without deviation from the scope of the present invention. The copper ground  15  layer may itself be a layer, or may be the bottom of a second core  20 . In certain embodiments additional characterized fill  46  is added so that the bonding film  21  layer may be removed or not utilized. In other words bonding film  21  is not necessary. 
     Core  20  comprises a copper ground  14  (may be used as a reference ground layer), a layer of bonding film  24  (e.g., FR4, etc.), and a second layer of copper. Selected locations of the second layer of copper are removed (e.g., etched), leaving intact copper signal traces that provide for the internal circuitry of the electronic structure. In the embodiment shown by  FIG. 2A , the second layer of copper is etched leaving a signal trace  18 . 
     In an alternate embodiment to produce a uniform distance from the top of the signal trace to the adjacent reference ground layer, utilizes a dispersal apparatus (e.g., printer, sputterer, etc.) to disperse upon core  20  characterized fill  46 . Characterized fill  46  is dielectric material similar to bonding film  21  and/or  24 . In certain embodiments characterized fill  46  may be partially cured epoxy. Characterized fill  46  is dispersed in locations effectively normalizing the distance variation from the top of bonding film  24  to the plane coincident to the top of signal trace  18 . 
     In a particular embodiment, characterized fill  46  is made from the same material as bonding film  21  and/or  24 , thus minimizing variations. In certain embodiments, characterized fill may be dispersed thermally, wherein small amounts of epoxy material are dispersed upon core  20  and thereby adhere to core  20 . In this embodiment, the characterized fill may be cured/reflowed with the standard lamination process after dispersal. 
     In another embodiment, the dispersal pattern is ‘inverse’ of the density of the signal traces upon the core. As the density of signal traces increase, the amount of characterized fill  46  dispersed upon core  20  decreases. In certain embodiments, no characterized fill is dispersed in the highest dense signal trace location upon core  20 . In certain other embodiments, the amount of characterized film  46  dispersed is approximately equal to the amount (by volume, etc.) of copper that was etched away (thereby leaving the various signal traces). 
     In certain other embodiments, as shown in  FIG. 3C , characterized fill  46  is only dispersed in characterized fill areas  47 . Characterized fill areas  47  are locations upon core  20  that have a low density of signal traces. In another embodiment, characterized fill areas  47  are locations upon core  20  not having signal traces. 
     The amount and location of the characterized fill  46  dispersal depends on the density and location of the various signal traces  18  on core  20 . The less signal traces upon core  20 , the more characterized fill  46 . In certain embodiments the volume of characterized fill  46  is approximately equal to the volume of removed copper (the remaining copper being the various signal traces). 
     By utilizing characterized fill  46 , a designer may calculate a desired distance between the top of a signal trace to the adjacent reference ground layer or a desired impedance. Via size and/or signal trace density may be determined in order to provide the desired distance and/or impedance. The designer may adjust the amount and location of dispersed characterized fill  46 , to achieve the desired distance/impedance. 
     Please refer to  FIG. 2B .  FIG. 2B  depicts the multilayer electronic structure of  FIG. 2A  after lamination, according to an embodiment of the present invention. By utilizing characterized film  46 , the effect of the distance variations from the top of signal trace  18  to the adjacent reference ground layer (i.e., copper ground  15 , etc.) is greatly reduced, if not eliminated. Please refer back to  FIG. 1A , wherein a similar core configuration resulted in a distance (the distance from the top of the signal trace to the adjacent reference ground layer) of 3.3 mils as compared to a distance of 4.0 mils when utilizing the characterized fill  46 . 
     Please refer to  FIG. 3A .  FIG. 3A  depicts an exploded multilayer electronic structure, according to an embodiment of the present invention. The exploded multilayer electronic structure comprises a first layer, a second layer, characterized fill  46  utilized to bond the first and second layers together. Characterized fill  46  may dispersed, as described above, in the spaces not filled by signal traces. 
       FIG. 3B  depicts the multilayer electronic structure of  FIG. 3A  after lamination, according to an embodiment of the present invention. By utilizing characterized fill  46 , the effect of the distance variations from the top of signal trace  18  to the adjacent reference ground layer (i.e., copper ground  15 ) is greatly reduced, if not eliminated. Please refer back to  FIG. 1C , wherein the similar core configuration resulted in a distance (the distance from the top of the signal trace to the adjacent reference ground layer) of 3.65 mils as compared to a distance of 4.0 mils when utilizing the characterized fill  46 . 
     By utilizing characterized fill  46  a constant distance from the top of the signal trace to the adjacent reference ground layer occurs in multiple signal trace configurations. This constant distance reduces the impedance tolerance across the multilayer circuit board. 
     Please refer to  FIG. 4 .  FIG. 4  depicts a process  60  of generating equalization data utilized to equalize thickness and/or impedance variations across a multilayer printed circuit card, according to an embodiment of the present invention. Process  60  begins at block  61 . In order to determine the geometrical and manufacturing properties (quantity, location, etc.) of characterized fill  46 , and/or alternatively characterized bonding film  22 , equalization data is created. Equalization data is utilized to equalize thickness and/or impedance variations across a multilayer printed circuit card. Equalization data represents the data data associated with characterized fill  46  (i.e., the locations of where to disperse, etc). An equalization data matrix is the equalization data of at least two locations of the multilayer printed circuit card. In an alternative embodiment, the equalization data matrix is the equalization data of the entire multilayer printed circuit card. Creating equalization data may be dependent on determining the signal trace density of a particular area (block  64 ) of the circuit card. In other embodiments, discussed infra, equalization data may be dependent on determining circuit board layer(s) thickness/impedance (block  64 ). The particular location of the printed circuit card considered is referred to as a cell. The cell may be a two dimensional area or a three dimensional volume. The area/volume of the cell is adjustable, however the smaller the area/volume of a cell, better equalization data may be created. When a generation of cells (block  62 ) in/from/to the computer aided design (CAD) data of the multilayer printed circuit card occurs, equalization data may be created for each cell. When there is more than one cell, the equalization data matrix is created (block  66 ). Once generated, the equalization data, or equalization data matrix, may be transferred (block  68 ), for example to a card manufacturer. Process  60  ends at block  69 . 
     Please refer to  FIG. 5A  and  FIG. 6  concurrently.  FIG. 5A  depicts a top view of a multilayer electronic structure layer having a signal trace thereupon, further depicting a baseline cell  150 , and cells  151 - 153 .  FIG. 6  depicts another process  70  of determining the signal trace density of each cell and the generating equalization data, according to an embodiment of the present invention. Process  70  starts at block  72 . Upon generating of cells in/from/to the CAD data (block  62  shown in  FIG. 4 ), a baseline cell  150  is identified (block  74 ). The baseline cell  150  has a corresponding baseline signal trace density (for instance the percentage of the cell filled by the signal traces). In a particular embodiment, shown in  FIG. 5A , the baseline cell  150  is a cell having no signal trace(s) within. In another embodiment, the baseline cell is completely filled by a signal trace. In other embodiments the baseline cell may have any percentage of the cell encapsulating a signal trace, however it is preferable that the baseline entirely encapsulates a signal trace, or does not encapsulate any signal trace. The base line cell  150  (and/or baseline cell signal trace density) is compared to another cell (and/or another cell signal trace density) (block  76 ). If the delta exceeds the maximum signal trace comparison value, equalization data is generated for the another cell (block  82 ). Take for example,  FIG. 5A . The baseline cell  150  encapsulates no signal trace(s), cell  153  also encapsulates no signal trace(s), cell  152  is 50% filled by a signal trace and 50% not filled by a signal trace, and finally cell  151  entirely encapsulates a signal trace(s). A preset maximum comparison signal trace density value (block  78 ) is set, for example at 0.10, meaning that equalization data is generated for the another cell if the another cell has a signal trace density of greater than 10% of the baseline cell. The maximum preset comparison signal trace density value may be adjustable by a user. Cell  152  (50% filled, 50% not filled) has a signal trace density of 0.5 because it is half filled by a signal trace. Cell  153  has a signal trace density of 0.0 because it does not encapsulate a signal trace. Cell  151  has a signal trace density of 1.0 because it does entirely encapsulate a signal trace. Because 1.0 and 0.5, respectively exceeds the maximum comparison signal trace density value of 0.1, equalization data is generated for cell  152  and  151  (block  82 ). If however the actual signal trace density value does not exceed the preset maximum signal trace density value of 0.1, such as cell  153 &#39;s value of 0.0, equalization data is not generated for cell  153  (block  80 ). In another embodiment equalization data is generated for cell  153  indicating that no characterization shall occur in the location of the characterized bonding film in the corresponding location. Process  70  ends at block  84 . 
     In another embodiment equalization data is generated for use relating to characterized fill  46  utilizing the cell structure exemplified in  FIG. 5A . In this particular embodiment the equalization data indicates the locations and quantity of characterized fill to be added upon core  20 . Please continue the example from above (i.e., baseline cell  150  encapsulates no signal trace(s), cell  153  also encapsulates no signal trace(s), cell  152  is 50% filled by a signal trace and 50% not filled by a signal trace, and finally cell  152  entirely encapsulates a signal trace(s)). Signal trace properties are determined or are known (i.e., height and width, etc.). The area of each cell is known or is determined. Each cell is analyzed whereby it is determined that 50% of the cell  152  is filled by a signal trace(s). Assume each cell&#39;s area is 0.5 mil square, and the thickness of the signal trace  18  is 1.4 mils. Therefore, 0.25 mil square of cell  152  is filled by the signal trace  18 , (50% of the cell area). Thus, 0.25 mil square×the signal trace  18  height (1.4 mils)=0.35 cubic mils. This volume therefore is the approximate volume of characterized fill  46  that is added upon core  20  in the particular location that corresponds with cell  152 . No characterized fill  46  would be added upon core  20  in the location corresponding to cell  151 . 0.7 cubic mills (0.5 square mills*1.4 mills) is the approximate volume of characterized fill  46  that would be added upon core  20  in the location corresponding cell  153 . 
     The geometry of the characterized fill  46  may be any such geometry without departing from the scope of the present invention. 
     Please refer to  FIG. 5B  and  FIG. 7  concurrently.  FIG. 5B  depicts a side view of a multilayer electronic structure core  20  having signal traces  18  thereupon, further depicting baseline cell  160 , and cells  161 - 163 .  FIG. 7  depicts yet another alternative process of determining the signal trace impedance/width of each cell and generating equalization data, according to an embodiment of the present invention. Process  90  starts at block  92 . Upon generating cells in/from/to the CAD data (block  62 , shown in  FIG. 4 ), a baseline cell  160  is identified (block  94 ). The cells (baseline and others), as contemplated in utilizing process  90 , are three dimensional volumes. The baseline cell  160  encapsulates a section of the at least one CAD circuit card layer. Therefore the baseline cell  160  has a particular first dimension, second dimension, and a third dimension that corresponds to the thickness of the at least one CAD circuit card layer. In a particular embodiment, the baseline cell is a cell encapsulating a section of core  20  and no signal trace(s) (not shown). In another embodiment the base line cell  160  encapsulates a section of core  20  and a signal trace (as shown in  FIG. 5B ). It may be preferred to create the baseline cell  160  such that the cell has the largest volume possible without empty space above and below the particular circuit board layer(s). In another embodiment the other cell (i.e., cells  161 - 163 ) volume equals the volume of baseline cell  160 . In other embodiments the volumes of the other cells do not equal the volume of the baseline cell. Further, the volume of cell  161  for instance, may not equal the volume of cell  162 . For example because there is empty space in cell  161 , cell  161  may be shortened such that the height would be similar to the height of the copper ground  14  and bonding film  24  stack. In another embodiment in an instance where there is empty space in a cell (i.e., cell  161  and  162 ) the height of those cells are shortened by a distance similar to the distance of the signal trace  18  height. 
     Baseline cell  160  has a baseline thickness/impedance. The baseline cell  160  thickness/impedance is compared to another cell&#39;s (cell  161 - 163 ) thickness/impedance (block  96 ). If the resultant of the comparison indicates that the delta exceeds the maximum signal trace comparison value (block  98 ), equalization data is generated for the another cell (block  102 ). In a new example, the baseline cell  160  encapsulates the at least one layer of a printed circuit card (e.g., copper ground  14  and bonding film  24 ) and at least part of a signal trace  18 . In the present embodiment, as shown in  FIG. 5B , the dimension of cells  161 - 163  are set similarly to the dimensions of the baseline cell  160 , however as indicated above the volumes of each cell need not be similar. Cell  163  similarly encapsulates the at least one layer of a printed circuit card and at least part of a signal trace  18 . Cell  162  encapsulates the at least one layer of a printed circuit card and at least part of a signal trace  18 , but also encapsulates empty space (i.e., space without a section of signal trace  18 ). Cell  161  encapsulates the at least one layer of a printed circuit card and does not encapsulate at least part of a signal trace  18  (i.e., cell  161  has more empty space than  162 ). Thus cells  161 - 163  demonstrate the transition from a location of a electronic structure layer going from at least one layer without a signal trace there upon (cell  161 ), to a location where part of the cell encapsulates a signal trace and part of the cell does not (cell  162 ), to a location of a layer with a signal trace there upon (cell  163 ). 
     A preset maximum comparison impedance/thickness value (block  98 ) is generated, meaning that equalization data is generated (block  102 ) for the another cell if the another cell has thickness/impedance greater than the baseline cell. The maximum preset comparison value may be adjustable. If however the actual impedance/thickness value does not exceed the preset maximum comparison value, equalization data is not generated for the another cell (block  100 ). Process  90  ends at block  104 . 
     In another embodiment equalization data is generated for use relating to characterized fill  46 , utilizing the cell structure exemplified in  FIG. 5B . In this particular embodiment the equalization data indicates the locations and quantity of characterized fill to be added upon core  20 . For example cell  164  is compared with cell  166 . The volume differential of cell  166  and  164  would represent the equalization data for cell  164 . The impedance/height of the cells may also be translated into a volume. This volume differential would be the volume of material that is to be added upon core  20  in the location that corresponds to cell  164 . For example cell  164  is compared with cell  166 . The volume differential of cell  166  and  164  would represent the equalization data for cell  166 . The impedance/height of the cells may also be translated into a volume. This volume differential would be for instance the volume of characterized fill in the location that corresponds to cell  166 . 
       FIG. 8  depicts a method of multilayer electronic structure manufacture according to an embodiment of the present invention. Method  130  begins at block  132  and may also be practiced, for example, by a card manufacturer. The equalization data matrix is read (block  134 ) to determine the particular areas upon core  20  that characterized fill  46  are to be added. Characterized fill is dispersed (block  136 ) upon core  20  in characterized fill areas  47 . Bonding film is then laminated (block  138 ) to the characterized core (core  20  having characterized fill  46  thereupon). Method  130  ends at block  140 . 
     The accompanying figures and this description depicted and described embodiments of the present invention, and features and components thereof. Those skilled in the art will appreciate that any particular program nomenclature used in this description was merely for convenience, and thus the invention should not be limited to use solely in any specific application identified and/or implied by such nomenclature.