Abstract:
A self-timed clock circuit and method of generating a self-timed clock circuit. The circuit includes means for charging a circuit node in response to an external reset signal; means for discharging the circuit node in response to a trigger signal generated by a photodiode; means for generating a first signal indicating a logic level of the circuit node; means for generating and delaying a second signal indicating the logic state of the circuit node; means for combining the first and second signals to generate a recharge signal; and means for recharging the circuit node in response to the recharge signal.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of integrated circuits; more specifically, it relates a method for and a circuit for generating a self-timed clock signal from an optical signal. 
       BACKGROUND OF THE INVENTION 
       [0002]    In current CMOS technology clock signals are generated by oscillators using phase-locked loop circuits. Current clock generators and distribution networks are prone to skew and jitter which limit the clock frequency. Additionally, current clock generators consume significant amount of integrated circuit chip real estate that could otherwise be used for combinational logic. As I/O frequencies increase, power consumption and power density become more critical there exists a need in the art for improved methods and circuits for generating clock signals. 
       SUMMARY OF THE INVENTION 
       [0003]    A first aspect of the present invention is a circuit, comprising: means for charging a circuit node in response to an external reset signal; means for discharging the circuit node in response to a trigger signal generated by a photodiode; means for generating a first signal indicating a logic level of the circuit node; means for generating and delaying a second signal indicating the logic state of the circuit node; means for combining the first and second signals to generate a recharge signal; and means for recharging the circuit node in response to the recharge signal. 
         [0004]    A second aspect of the present invention is a PFET and an NFET, drains of the PFET and NFET connected to a circuit node; a source of the NFET connected to ground, a source of the PFET coupled to a voltage source; a photodiode, a cathode of the photodiode connected to the voltage source and an anode of the photodiode connected to a gate of the NFET; first and second inverters, an input of the first inverter connected to the circuit node and an output of the first inverter connected to an input of the second inverter, an output of the second inverter connected to an input of a delay circuit and coupled to an output pin of the circuit; and an AND gate, a first input of the AND gate connected to the output of the first inverter, a second input of the AND gate connected to an output of the delay circuit, an output of the AND gate connected to a gate of the PFET. 
         [0005]    A third aspect of the present invention is a method of generating a clock signal, comprising: providing a circuit comprising a photodiode, a circuit node, a delay circuit and a clock output pin; discharging the circuit node in response to a trigger signal generated by the photodiode; generating a first signal indicating a logic level of the circuit node; generating and delaying a second signal indicating the logic state of the circuit node; coupling the second signal to the clock output pin; combining the first and second signals to generate a recharge signal; and recharging the circuit node in response to the recharge signal. 
         [0006]    A fourth aspect of the present invention is an electronic assembly, comprising: an integrated circuit chip including a circuit according to the first aspect; means for receiving an output of a pulsed laser; means for distributing the output of the pulsed laser to the photodiode of the circuits; and one or more clocked devices, clock inputs of the one or more clocked devices coupled to the output signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0008]      FIG. 1  is a schematic circuit diagram of a clock generation circuit according to embodiments of the present invention; 
           [0009]      FIG. 2  is a timing diagram for the clock generation circuit of  FIG. 2 ; 
           [0010]      FIG. 3  is a schematic circuit diagram of the inverter chain of the clock generation circuit of  FIG. 1 ; 
           [0011]      FIG. 4  is a cross-section of and exemplary photodiode that may be used in the clock generation circuit of  FIG. 1 ; 
           [0012]      FIG. 5  is cross-sectional drawing illustrating an exemplary structure for a shielded wire; 
           [0013]      FIG. 6A  is a diagram illustrating a first method of distributing clock signals through an integrated circuit; 
           [0014]      FIG. 6B  is a diagram illustrating a second method of distributing clock signals through an integrated circuit; and 
           [0015]      FIGS. 7A and 7B  are diagrams illustrating an exemplary device using clock generation circuits according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    A clock signal is defined as a signal that alternates between a high voltage value (e.g., a logical 1) and a low value voltage value (e.g., a logical zero) in a periodic manner. The time duration between adjacent rising edges of a clock signal is one clock cycle. Often the high time duration is equal to the low time duration. 
         [0017]    Skew is defined as the propagation delay of a clock signal along the distribution path of the clock signal. Skew causes different latches in an integrated circuit to receive a same edge of a clock signal at different times. 
         [0018]    Jitter is defined as the time variation around the rising and falling edges of a clock signal. 
         [0019]    A PFET is a p-channel field effect transistor and an NFET is an n-channel field effect transistor. PFETS and NFETs are the primary devices of complimentary metal-oxide-silicon (CMOS) technology. A CMOS compatible resistor may be formed, for example, by tying the gate of a PFET to VDD or the gate of an NFET to ground. Resistors may also be formed from by placing contacts at opposite ends of a polysilicon line (e.g., using an isolated gate electrode). CMOS compatible capacitors may take the form of trench capacitors or metal-insulator-metal (MIM) capacitors. 
         [0020]      FIG. 1  is a schematic circuit diagram of a clock generation circuit according to embodiments of the present invention. In  FIG. 1 , a clock generation circuit  100  includes first and second PFETs P 1  and P 2 , an NFET N 1 , a photodiode D 1 , first, second and third inventors I 1 , I 2  and I 3 , first, second and third capacitors C 1 , C 2  and C 3 , a delay circuit B 1 , an AND gate A 1  and first and second resistors R 1  and R 2 . First resistor R 1  is optional. In one example, capacitors C 1 , C 2  and C 3  represent parasitic wiring capacitances which may be taken into account when designing clock generation circuit  100 . Alternatively, one or more of capacitors C 1 , C 2  and C 3  may be added design elements of clock generation circuit  100 . Second resistor R 2  is optional. Third inventor I 3  and third capacitor C 3  are optional. Circuit  100  includes no pins for receiving an electronically generated clock signal. Circuit  100  does not require an external electrical timing signal to generate a clock signal. 
         [0021]    In  FIG. 1 , the cathode of photodiode P 1  is connected to VDD and the anode of photodiode P 1  is connected to the gate of NFET N 1 . The source of NFET N 1  is connected to ground and respective first plates of capacitors C 1 , C 2  and C 3 . The drain of NFET N 1  is connected to a circuit node N, as are the drains of PFETs P 1  and P 2 . The source of PFET P 1  is coupled to VDD through resistor R 1  and the source of PFET P 2  is coupled to VDD through resistor R 2 . Alternatively, R 2  may be eliminated and the source of PFET P 1  couple to VDD through resistor R 1 . Alternatively, both resistor R 1  and R 2  may be eliminated and the sources of PFETs P 1  and P 2  connected directly to VDD. Node N is connected to the input of first inverter I 1 . The output of first inverter I 1  is connected to a second plate of first capacitor C 1 , to an input of second inverter I 1 , and to a first input of AND gate A 1 . The output of second inverter I 2  is connected to a second plate of second capacitor C 2 , to an input of third inverter I 3 , and to an input of delay circuit B 1 . The output of third inverter I 3  is connected to a second plate of third capacitor C 2 , and is connected to an output pin. Alternatively, if third inverter I 3  and third capacitor C 3  are not present, then the output of inverter I 2  is connected to the output pin. The output of delay circuit B 1  is connected to a second input of AND gate A 1  and the output of AND gate A 1  is connected to the gate of PFET P 2 . The gate of PFET P 1  is connected to a reset input pin. 
         [0022]    Circuit  100 , when implemented in CMOS technology is takes up about 1000 times less integrated circuit chip real estate than a current art oscillator/phase lock loop clock generation circuit used to generate clock signals. 
         [0023]    The purpose of resistors R 1  (and R 2 ) are to provide power dissipation in the event of a momentary connection between VDD and ground through PFET P 1  and NFET N 1  or PFET P 2  and NFET N 1 . The primary input of circuit  100  is a trigger signal TRIG generated by photodiode D 1  when photodiode D 1  is struck by incident light. The output of circuit  100  is a clock signal CLK. A reset signal RESET on the reset input allows resetting node N to an initial logical 1 state (i.e., initial charging of node N 1 ). Node N discharges through NFET N 1  and recharges through PFET P 2  (or through PFET P 1  in case of a reset). The inverter chain comprised of invertors I 1 , I 2 , I 3  and capacitors C 1 , C 2 , and C 3  and provides signal amplification. The feedback loops from the output of inverter I 1  to AND gate A 1  and from the output of second inverter I 2  to delay circuit B 1  provide clock signal shaping as well as self-timing. In one example, the time delay through delay circuit B 1  may be a programmable delay. Delay circuit B 1  produces a delay signal DELAY and AND gate A 1  produces a charge recharge signal RC. 
         [0024]    The following conventions will be used in describing signal propagation or switching delays through circuit components: dN 1  is the delay through NFET N 1 , dP 1  is the delay through PFET P 1 , dP 2  is the delay through PFET P 2 , dI 1  is the delay through inverter I 1 , dI 2  is the delay through Inverter I 2 , dA 1  is the delay through AND gate A 1  and dB 1  is the delay through delay circuit. Circuit  100  is initialized by asserting reset high for a minimum time dP 1 , DI 1 , dI 2  dB 1 , dA 1 , dP 2 . When reset is asserted high, the output of inverter I 1  is low (e.g., logical zero) putting a low on the first input of AND gate A 1  and the output of inverter I 2  is high (e.g., logical one), putting a high on the second input of AND gate A 1  after a delay dB 1 . 
         [0025]    In operation, after node N is charged, a high pulse on the gate of NFET N 1 , causes node N to go low, causing CLK to go high, the first input of AND gate A 1  to go high (e.g., logical 1) and the second input of AND gate A 1  to go low after a delay of dI 2 +dB 1 . Because of the delay through delay circuit B 1 , there will be a window of time when the second input of AND gate is also high (from the previous cycle) before going low which turns on PFET P 2  and recharges node N. The TRIG signal is a high precision repeating pulse signal. It is generated by photodiode D 1  when photodiode D 1  is exposed to a precision pulsed-laser beam. In one example, the pulse frequency (as opposed to the frequency of laser light itself) of the pulsed laser beam is between about 1 GHz and about 20 GHz. The upper limit of the laser pulse frequency is determined by the delay through the internal feedback loop I 1 /I 2 /B 1 /A 1 . The frequency of the TRIG signal is the same as the pulse frequency of the pulsed laser. It is advantageous that the jitter of the pulsed laser be in the order of about less than about 2 femto-seconds or less allowing portions of conventional electrical clock distribution trees to be replaced by optical counterparts. 
         [0026]    In one example, delay circuit B 1  is implemented as a fixed delay. In one example, delay circuit B 1  is a programmable delay. The advantage of a programmable delay is that the clock shape (the ratio between clock high and clock low time durations in each clock cycle, often this ratio is 1 as illustrated in  FIG. 2 ) may be tuned. Delay circuit B 1  may be implemented, for example, as wire delay (e.g., longer then required wire lengths), electrically programmable fuses (e-fuses), a serial latch chain, multiplexer selectable latch chains, and even number serial buffer chains. E-fuses and latch chains (depending on how they are multiplexed) are examples of delay circuits in which the delay may be programmed after fabrication of circuit  100  (see  FIG. 1 ). 
         [0027]    In order to avoid noise on adjacent circuits causing jitter on circuit  100  it is advantageous that circuit  100  be shielded as shown by the dashed line in  FIG. 1 . Examples of shielding include, but is not limited to locating circuit  100  device structures away from structures of adjacent circuits, avoiding running wires of circuit  100  parallel to wires of adjacent circuits, using shielded wires in circuit  100  (see  FIG. 5 ), using a dedicated power supply for circuit  100  and combinations thereof. 
         [0028]    It should be understood that there may be more than three inverters in the inverter chain as long as there are an odd number of inverters between node N 1  and the second input of AND gate A 1  and an even number of inverters between node N 1  and the input of delay circuit B 1  or vice versa. 
         [0029]      FIG. 2  is a timing diagram for the clock generation circuit of  FIG. 2 . In  FIG. 2 , the rising edge of TRIG causes node N to fall and CLK to rise after a delay of dN 1 +dI 1 +dI 2 +dI 3 =A (or more generally, dN 1 +dI 1 +dI 2 + . . . +dIi). Node N stays low until a falling edge of DELAY causes node N to rise, which, causes CLK to fall at the top of rising edge of node N. The delay between rising CLK and falling CLK is dI 2 +dB 1 =B. The times between rising adjacent rising edges of CLK, between adjacent rising edges of TRIG, between adjacent falling edges of node N and between adjacent rising edges of DELAY are all the same. There is also a dependency between the discharge of node N and the falling edge of DELAY, dI 1 +dI 2 +dB 1 =C. 
         [0030]      FIG. 3  is a schematic circuit diagram of the inverter chain of the clock generation circuit of  FIG. 1 . It is advantageous that the delay through the inverter chain comprised of inverters I 1 , I 2  and I 3  be as short as possible. Inverter I 1  includes PFET P 3  and NFET N 2 , inverter I 2  includes PFET P 4  and NFET N 3  and inverter I 3  includes PFET P 5  and NFET N 4 . The gain β of an inverter is the output current divided by the input voltage V IN  minus the threshold voltage Vt. Tapering factor is defined as the ratio of the gains of adjacent inverters in a sequential chain of inverters. A minimum propagation delay possible through successive inverters (e.g., between I 1  and I 2  and between I 2  and I 3 ) is achieved when a tapering factor k is equal to e. So β I3 =eβ I2  and β I2 =eβ I1 . The β of a transistor is a function of the W/L ratio where W is the gate width and L is the gate length. Thus defining the β of inverter I 3  fixes the W/L ratio of PFET P 5  and NFET N 4 . By selecting a tapering factor, the W/L ratios of PFETs P 3  and P 4  and NFETs N 2  and N 3  can be calculated and an inverter chain with minimum propagation delay be designed based on the minimum image size of the fabricating CMOS technology. Table I gives some performance characteristics of an inverter chain as a function of tapering factor. dI/dt is the rate of charge of Node N (see  FIG. 1 ) in nA/ns and the propagation delay is given in ns. 
         [0000]    
       
         
               
               
             
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE I 
               
             
             
               
                   
                   
               
               
                   
                 Tapering Factor 
               
             
          
           
               
                   
                 e 
                 4.6 
                 10 
               
               
                   
                   
               
             
          
           
               
                   
                 Max dI/dt 
                 2.8E5 
                 1.8E5 
                 0.6E5 
               
               
                   
                 Propagation Delay 
                 0.92 
                 0.95 
                 0.99 
               
               
                   
                   
               
             
          
         
       
     
         [0031]    In one example, the tapering factor of the inverter chain comprised of invertors I 1 , I 2  and I 3  of  FIG. 1  is between about 8 and about 16. The ideal tapering factor would be e (where ln e=1). In one example, the tapering factor of the inverter chain comprised of invertors I 1 , I 2  and I 3  of  FIG. 1  is between about e and about 16. 
         [0032]      FIG. 4  is a cross-section of and exemplary photodiode that may be used in the clock generation circuit of  FIG. 1 . In  FIG. 4 , a PIN diode  105  includes a P doped silicon region  110  separated from an N doped region by an intrinsic silicon region  120 . Intrinsic region  120  may be lightly doped N or P type. Light striking the intrinsic region generates electron-hole pairs generating a conductive path between P doped region  110  and N-doped region  120 . 
         [0033]      FIG. 5  is cross-sectional drawing illustrating an exemplary structure for a shielded wire. In  FIG. 5 , a dielectric layers  125 A,  125 B  125 C and  125 D are formed over a substrate  130 . Formed in dielectric layer  125 A is a lower shield wire  135 . Formed in dielectric layer  125 B is a core wire  140  and first and second middle shield wires  145  and  150  formed on opposite sides of core wire  140 . Formed in dielectric  125 C is an upper shield wire  135 . Lower shield wire  135 , middle shield wires  145  and  150  and upper shield wire  155  are connected to ground, while core wire  140  is a signal/power supply wire of circuit  100  (see  FIG. 1 ). 
         [0034]      FIG. 6A  is a diagram illustrating a first method of distributing clock signals through an integrated circuit. In  FIG. 6A , clock signal CLK generated by circuit  100  (see  FIG. 1 ) is connected to the clock input of a latch  160 . More than one latch may be connected to the same clock signal line. 
         [0035]      FIG. 6B  is a diagram illustrating a second method of distributing clock signals through an integrated circuit. In  FIG. 6B , clock signal CLIK generated by circuit  100  (see  FIG. 1 ) is connected to a latch control block  165  where CLK is distributed to latches  170 A,  170 B and  170 C. There may be multiple latch control blocks on the same integrated circuit chip, each latch control block supplied a CLIK signal from a different instance of circuit  100  (see  FIG. 1 ). 
         [0036]      FIGS. 7A and 7B  are diagrams illustrating an exemplary device using clock generation circuits according to embodiments of the present invention. In  FIG. 7A , an integrated circuit chip  175  is attached to a module  180 . Wires in chip  175  are connected, for example, to wires in module  180  by wirebonds (not shown) or solder bumps (not shown). Integrated circuit chip  175  includes three instances of circuit  100  connected by optical transmission lines  185  to a distribution device  190 . Distribution device  190  is mounted on module  180  and connected to a pulsed laser by optical transmission lines  185 . In one example, optical transmission lines  185  are external to chip  175 . Alternatively, optical transmission lines  185  are waveguides fabricated as part of chip  175  and distribution device is mounted to chip  175  as in  FIG. 7B . 
         [0037]    Thus, the embodiments of the present invention provide methods of generating and distributing clock signals and circuits for generating clock signals having very low jitter and use a very small amount of integrated circuit real estate compared to conventional clock generators. 
         [0038]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.