Abstract:
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.

Description:
BACKGROUND 
     High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices by stacking dies vertically stacked and interconnecting the dies using through-silicon vias (TSVs) have been introduced. Benefits of the 3D memory devices include a plurality of core chips stacked with a large number of vertical vias between the plurality of core chips and an interface chip and the memory controller, which allow wide bandwidth buses with high transfer rates between functional blocks in the plurality of core chips and the interface chip, and a considerably smaller footprint. Thus, the 3D memory devices contribute to large memory capacity, higher memory access speed and chip size reduction. The 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM). 
     The large number of vertical vias may transfer a clock signal, memory cell data and command sequences for controlling the core chips simultaneously in a manner that the plurality of core chips can be operated independently and simultaneously at high transfer rates. Here, a plurality of input/output channels on the core chips are not necessarily synchronous to each other. To accommodate such operation, the 3D memory device may include a large number of circuits that may operate simultaneously, which causes simultaneous power consumption throughout the device. In particular, the 3D memory device may allow a plurality of memory core chips to operate similar operations throughout circuits on each memory core chip simultaneously at high transfer rates while allowing the interface chip in the 3D memory device to transfer data high rates simultaneously. Simultaneous power consumption throughout the 3D memory device may cause a considerable voltage drop at portions of the large number of circuits having high wiring resistance with respect to a power supply source. This voltage drop may cause unstable operations at the portions of the large number of circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a semiconductor device including an interface chip and a plurality of core chips in accordance with an embodiment of the present disclosure. 
         FIG. 2A  is a simplified layout diagram of a chip including through electrodes in a semiconductor device, in accordance with an embodiment of the present disclosure. 
         FIG. 2B  is a schematic diagram of a through electrode in a core chip of the semiconductor device, in accordance with an embodiment of the present disclosure. 
         FIG. 2C  is a schematic diagram of the semiconductor device including an interface chip and a plurality of core chips in  FIG. 2A . 
         FIG. 2D  is a schematic view of the power supply through electrodes and the power supply wirings in  FIGS. 2A and 2B . 
         FIG. 3A  is a simplified layout diagram of a chip including through electrodes in a semiconductor device, in accordance with an embodiment of the present disclosure. 
         FIG. 3B  is a schematic diagram of the semiconductor device including an interface chip and a plurality of core chips in  FIG. 3A . 
         FIG. 3C  is a schematic view of the power supply through electrodes and the power supply wirings in  FIGS. 3A and 3B . 
         FIG. 4A  is a schematic diagram of the semiconductor device including an interface chip and a plurality of core chips, in accordance with an embodiment of the present disclosure. 
         FIG. 4B  is a schematic view of the power supply through electrodes and the power supply wirings in  FIG. 4A . 
         FIG. 5A  is a simplified layout diagram of a chip including through electrodes in a semiconductor device, in accordance with an embodiment of the present disclosure. 
         FIG. 5B  is a schematic diagram of the semiconductor device including an interface chip and a plurality of core chips in  FIG. 5A . 
         FIG. 5C  is a schematic view of the power supply through electrodes and the power supply wirings in  FIGS. 5A and 5B . 
         FIG. 6A  is a simplified layout diagram of memory cell arrays of a chip in a semiconductor device, in accordance with an embodiment of the present disclosure. 
         FIG. 6B  is a layout diagram of the portion of the memory cell array of the chip of  FIG. 6A . 
         FIG. 7  is a schematic diagram of a semiconductor system including a semiconductor device that includes an interface chip and a plurality of core chips in accordance with an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. 
       FIG. 1  is a schematic diagram of a semiconductor device including an interface chip and a plurality of core chips in accordance with an embodiment of the present disclosure. As shown in  FIG. 1 , a semiconductor device  1  may include an interface (I/F) chip  3  and a plurality of core chips  4  stacked on the I/F chip  3 . The I/F chip  3  may be stacked on a substrate  2 . The semiconductor device  1  may include one or more external terminals  5  (e.g., one or more pads) which may receive external signals and provide the external signals to internal signal wirings  26  of the substrate  2 . 
     For example, each of the I/F chip  3  and the plurality of core chips  4  may extend on a plane defined by a first direction  100  and a second direction  110  that is perpendicular to the first direction  100 . The I/F chip  3  and the plurality of core chips  4  may be stacked in a third direction  120  that is perpendicular to the first direction  100  and the second direction  110 . The I/F chip  3  may include a substrate layer  31  and a wiring layer  32 . The I/F chip  3  includes a plurality of through wirings  36 . For example, each of the plurality of through wirings  36  includes a through electrode (TSV)  35  in the substrate layer  31 . For example, each of the plurality of through wirings  36  includes a substrate terminal  33  on a side of the substrate  2  which couples the substrate  2  to the TSV  35 . The I/F chip  3  may include an external input/output circuit (not shown) that is coupled to a plurality of substrate terminals  33 . The external input/output circuit transmits signals from/to the outside of the semiconductor device  1  through the substrate  2 . For example, each of the plurality of through wirings  36  includes an interface (IF) terminal  34  (e.g., surface bump) on a side of the plurality of core chips  4  which couples the TSV  35  to a corresponding interface (IF) terminal  43  of one of the plurality of core chips  4  facing the I/F chip  3 . The I/F chip  3  may also include an internal signal input/output circuit (not shown) that is coupled to a plurality of IF terminals  34 . The internal signal input/output circuit transmits data to/from the core chips  4 . 
     Each of the plurality of core chips  4  may include a substrate layer  41  and a wiring layer  42 . Each of the plurality of core chips  4  includes a large number of memory cells (not shown, e.g., dynamic random access memory). Each of the plurality of core chips  4  may include memory cell peripheral circuits (not shown, e.g., sense amplifiers and address decoders), timing control circuits for adjusting operation timings of the memory cell peripheral circuits, input/output circuits relative to the I/F chip  3 , test circuits for defect detection in a wafer test for core chips. Each of the plurality of core chips  4  may include a plurality of through wirings  46 . Each of the plurality of through wirings  46  may include one or more interface (IF) terminals  43  and a plurality of through electrodes  45 . 
     A power supply (e.g., a positive supply voltage V DD , a negative supply voltage V SS ) for operations of the plurality of core chips  4  is supplied to the I/F chip  3  from an external terminal  5  coupled to a power supply source (not shown), and further supplied to the plurality of core chips  4  through power supply through electrodes  35  and  45 .  FIG. 2A  is a simplified layout diagram of a chip  20  including through electrodes  25  in the semiconductor device  1 , in accordance with an embodiment of the present disclosure. The chip  20  may be the I/F chip  3  or the core chip  4 . When the chip  20  is the core chip  4 , memory cell arrays  23  represented by squares of dotted lines may be disposed on the chip  20 . The through electrodes  25  may be power supply through electrodes  35  or  45  on the I/F chip  3  or the core chip  4 , respectively. The chip  20  may include the through electrodes  25  disposed in an area  21  at the center of the chip  20 . In this example, the area  21  may be between the memory cell arrays  23  and aligned to the memory cell arrays  23  along a first direction  200 . The area  21  may extend in a second direction  210  perpendicular to the first direction  200 . Power supply wirings  22  are coupled to the through electrodes  25  on the chip  20 . The power supply wirings  22  may be represented by solid lines in horizontal and vertical directions on the chip  20 . 
       FIG. 2B  is a schematic diagram of a through electrode in a core chip of the semiconductor device, in accordance with an embodiment of the present disclosure. In particular,  FIG. 2B  shows a cross-sectional view of the through wiring  46  including the through electrode (TSV)  45  through a substrate layer  41 , an interlayer insulation film  201 , which is provided on a surface (e.g., a back surface) of the substrate layer  41 , and a passivation film  202 , which is provided on a surface (e.g., a top surface) of the substrate layer  41 , and surface bumps  47  and  48  that are provided at the same location as the through electrode  45  in planar view. For example, the through electrode  45  may be made of conductive material, such as copper or the like. The back surface of the substrate  41  will be a multi-level wiring structure  42  including wiring layers L 1  to L 4 . Around the through electrode  45 , insulation wall  451  is provided to insulate the through electrode  45  from a transistor region. The insulation wall  451  can be provided as an insulation ring or an insulation film such as silicon oxide film around the through electrode  45 . 
     An end portion of the through electrode  45  may be covered with the surface bump  47  that may be in contact with the other surface bump  48  of another core chip, respectively. For example, the surface bump  47  covers the surfaces of the through electrode  45 . The through wiring  46  may also include interconnection pads M 1  to M 4  provided at the wiring layers L 1  to L 4  respectively, and a plurality of through-hole conductors TH 1  to TH 3 , which couple the interconnection pads M 1  to M 4 . The surface bump  48  is connected to an end portion of the through electrode  45  via the interconnection pads M 1  to M 4  and the plurality of through-hole conductors TH 1  to TH 3 . For example, the surface bump  48  may include a pillar portion  49  made of conductive material which passes through a passivation film  203 . The connection to internal circuits not shown in  FIG. 2B  may be provided by interconnection lines (not shown), which couple the interconnection pads M 1  to M 3  to the internal circuits provided in the wiring layers L 1  to L 3 . Accordingly, input signals (command signals, address signals, and other signals) that are supplied from another chip (e.g., the interface chip IF) to the core chips via the through electrodes  45  that are provided to the core chips. Output signals (e.g., data signals) from the core chips may be provided via the through electrodes  45  to the interface chip IF. 
       FIG. 2C  is a schematic diagram of the semiconductor device including an interface chip and a plurality of core chips in  FIG. 2A .  FIG. 2C  is a cross-sectional view of a portion of the semiconductor device indicated by X-X′ of  FIG. 2A . A plurality of chips  20  (e.g., the I/F chip  3  and the plurality of core chips  4 ) may be stacked in a third direction  220  that is perpendicular to the first direction  200  and the second direction  210  in  FIG. 2A . The cross-sectional view includes cross sections of the power supply through electrodes  25  disposed in the area  21  of  FIG. 2A . The power supply through electrodes  25  may supply power supply voltage from the external terminals  5  through the substrate wirings  26  of the substrate  2  to the plurality of chips  20 . The plurality of power supply through electrodes  25  may be coupled by a plurality of terminals  27  in a series in a direction perpendicular to planes of the plurality of chips  20 . For example, the plurality of terminals  27  may be the IF terminals  34  and  43  coupling the plurality of power supply through electrodes  25 . The power supply through electrodes  25  may supply the power supply voltage to the plurality of chips  20  through the power supply wirings  22 . 
       FIG. 2D  is a schematic view of the power supply through electrodes  25  and the power supply wirings  22  in  FIGS. 2A and 2C . In  FIG. 2D , each of the power supply through electrodes  25  and the power supply wirings  22  may be modeled as a resistor. Each of the resistor groups  241  and  242  may include the plurality of power supply through electrodes  25  and a plurality of terminals  27  in the area  21 . The plurality of power supply through electrodes  25  are coupled in series along the third direction  220 . The power supply through electrodes  25  is made of conducting material (e.g., copper) and the resistance of the power supply through electrodes  25  is substantially low (e.g., approximately zero). The resistance of the power supply wirings  22  may also be extremely low (e.g., approximately 0.05 ohm). There may be low resistance at a connection point of the terminals  27  with the power supply wirings  22  on the chip  20 . The semiconductor device  1  may include a large number of the through electrodes  25 , where the resistance of each of the resistor groups  241  and  242  may be substantially low (e.g., approximately zero) due to high conductivity of the conductive material. Each of the power supply wirings  22  may be provided to have a width that minimizes the resistance inside the chip  20 , while supplying a sufficiently level of power supply voltage to circuits. 
       FIG. 3A  is a simplified layout diagram of a chip including through electrodes in a semiconductor device, in accordance with an embodiment of the present disclosure. Description of components corresponding to components included in  FIG. 2A  will not be repeated and changes from  FIG. 2A  including positional relationships between the components will be described. For example, the chip  20  may include the through electrodes  25   a  to  25   c  disposed in areas  21   a  to  21   c  on the chip  20 . The through electrodes  25   a  to  25   c  may be for power supply and coupled to the power supply wirings  22 . In this example, the chip  20  may include memory cell arrays  23   a  to  23   d  represented by squares of dotted lines, which are aligned along a first direction  300 . The area  21   a  may be disposed between the memory cell arrays  23   b  and  23   c , adjacent to the memory cell array  23   b  and aligned to the memory cell array  23   b  along the first direction  300 . The area  21   a  may be adjacent to the memory cell array  23   c  and aligned to the memory cell array  23   c  along a third direction  300 ′ which is substantially opposite to the first direction  300 . The area  21   b  may be disposed between the memory cell arrays  23   a  and  23   b , adjacent to the memory cell array  23   a  and aligned to the memory cell array  23   a  along the first direction  300 . The area  21   b  may be adjacent to the memory cell array  23   b  and aligned to the memory cell array  23   b  along the third direction  300 ′. The area  21   c  may be disposed between the memory cell arrays  23   c  and  23   d , adjacent to the memory cell array  23   c  and aligned to the memory cell array  23   c  along the first direction  300 . The area  21   c  may be adjacent to the memory cell array  23   d  and aligned to the memory cell array  23   d  along the third direction  300 ′. The areas  21   a  to  21   c  may extend in a second direction  310  perpendicular to the first direction  300 . It may be possible to have substantially the same resistance between circuitry portions in the area  21   b  and  21   c . For example, the areas  21   b  and  21   c  may be symmetrically spaced with respect to the area  21   a . A distance between the areas  21   a  and  21   b  and a distance between the areas  21   a  and  21   c  may be substantially the same. A number of the plurality of through electrodes  25   b  and a number of the plurality of through electrodes  25   c  may be substantially the same. 
       FIG. 3B  is a schematic diagram of the semiconductor device including an interface chip and a plurality of core chips in  FIG. 3A .  FIG. 3B  is a cross-sectional view of a portion of the semiconductor device indicated by X-X′ of  FIG. 3A . The cross-sectional view includes cross sections of the power supply through electrodes  25   a  to  25   c  disposed in the area  21   a  to  21   c  of  FIG. 3A . The power supply through electrodes  25   a  to  25   c  may supply power supply voltage from the external terminals  5  through the substrate wirings  26  of the substrate  2  to the plurality of chips  20  (e.g., the interface chip  3  and the plurality of core chips  4 , where a number of the plurality of core chips  4  is four). The plurality of power supply through electrodes  25   a  to  25   c  may be coupled by a plurality of terminals  27   a  to  27   c  in a series in a direction perpendicular to planes of the plurality of chips  20 . For example, the plurality of terminals  27   a  to  27   c  may be coupling the plurality of power supply through electrodes  25   a  to  25   c , respectively. The power supply through electrodes  25   a  to  25   c  in the areas  21   a  to  21   c  may supply the power supply voltage to the plurality of chips  20  through the power supply wirings  22 . 
       FIG. 3C  is a schematic view of the power supply through electrodes and the power supply wirings in  FIGS. 3A and 3B . In  FIG. 3C , each of the power supply through electrodes  25   a  to  25   c  and the power supply wirings  22  may be modeled as a resistor. Each of the resistor groups  24   a  to  24   c  may include the plurality of power supply through electrodes  25   a  to  25   c  and a plurality of terminals  27  in the area  21   a  to  21   c , respectively. The plurality of power supply through electrodes  25   a  are coupled by the plurality of terminals  27  in series along a fourth direction  320  that is perpendicular to the first direction  300  and the second direction  310 . Similarly, the plurality of power supply through electrodes  25   b  are coupled in series along the fourth direction  320  by the plurality of terminals  27 , and the plurality of power supply through electrodes  25   c  are coupled in series along the fourth direction  320  by the plurality of terminals  27 . Because the areas  21   a  to  21   c  for the through electrodes  25   a  to  25   c  for power supply are disposed between the memory cell arrays  23   a  to  23   d , a circuit (not shown) may be disposed between the through electrodes  25   a  and  25   b  or between the through electrodes  25   a  and  25   c . For example, the circuit may be a step-down power-supply circuit or the like. The circuit between the memory cell arrays may supply power efficiently to the memory cell array in the memory cell arrays  23   a  to  23   d.    
     As described above, the power supply through electrodes  25   a  to  25   c  may supply the power supply voltage to the plurality of chips  20  through the power supply wirings  22  disposed in a center area of each chip (e.g., the area  21   a ), but also through the power supply wirings  22  located in the areas  21   b  and  21   c  of  FIGS. 3B and 3C . In this case, a resistance between the external terminals  5  and a portion at an electrically farther end (e.g., a circuitry portion at the chip end) becomes smaller when the wiring resistance on an identical chip is substantially the same, because additional electrical paths for power supply are provided by the power supply wirings located in the areas  21   b  and  21   c . Thus, the additional electrical paths may reduce voltage drops due to power consumption in circuits on the plurality of chips  20  and therefore stabilize operations in the circuits. 
       FIG. 4A  is a schematic diagram of the semiconductor device including the interface chip and the plurality of core chips, in accordance with an embodiment of the present disclosure. A simplified layout view of each die of the semiconductor device may be similar to the simplified layout view of each die of the semiconductor device in  FIGS. 3A to 3   c  and description of components corresponding to components included in  FIGS. 2A and 3   a  to  3   c  will not be repeated and changes from  FIGS. 2A and 3A to 3C  including positional relationships between the components will be described.  FIG. 4A  is a cross-sectional view of a portion of the semiconductor device. The cross-sectional view includes cross sections of the power supply through electrodes  25   a  and  25   c  disposed in the area  21   a  and  21   c  of  FIG. 3A . The power supply through electrodes  25   a  and  25   c  may supply power supply voltage from the external terminals  5  through the substrate wirings  26  of the substrate  2  to the plurality of chips  20  (e.g., the interface chip  3  and the plurality of core chips  4 , where a number of the plurality of core chips  4  is eight). 
       FIG. 4B  is a schematic view of the power supply through electrodes and the power supply wirings in  FIG. 4A . In  FIG. 4B , each of the power supply through electrodes  25   a  to  25   c  and the power supply wirings  22  may be modeled as a resistor. Each of the resistor group  24   a  may include the plurality of power supply through electrodes  25   a  in the area  21   a , and each of the resistor groups  24   c  and  24   c ′ may include the plurality of power supply through electrodes  25   c  and  25   c ′ in the area  21   c , respectively. The plurality of power supply through electrodes  25   a  are coupled in series along the fourth direction  320  by the plurality of terminals  27 . Similarly, the plurality of power supply through electrodes  25   c  in the resistor groups  24   c  are coupled in series along the fourth direction  320  and the plurality of power supply through electrodes  25   c ′ in the resistor groups  24   c ′ are coupled in series along the fourth direction  320 . As described above, the power supply through electrodes  25   c  and  25   c ′ may supply the power supply voltage to the plurality of chips  20  through the through wirings disposed located in the area  21   c  of  FIGS. 4A and 4B . In this case, a resistance between the external terminals  5  and a portion at an electrically farther end, such as a circuitry portion at the chip end and or a circuitry portion on upper chips becomes smaller when the wiring resistance on an identical chip is substantially the same, because additional electrical paths for power supply may be provided by the power supply wirings located in the area  21   c  on additional chips due to an increased number of stacked layers. Thus, the additional electrical paths may reduce voltage drops due to power consumption in circuits on the plurality of chips  20  and therefore stabilize operations in the circuits. 
       FIG. 5A  is a schematic diagram of a layout of through electrodes on a chip in a semiconductor device, in accordance with an embodiment of the present disclosure. Description of components corresponding to components included in  FIGS. 2A and 3A  will not be repeated and changes from  FIGS. 2A and 3A  including positional relationships between the components will be described. For example, the chip  20  may further include the through electrodes  25   d  and  25   e  disposed in areas  21   d  and  21   e  on the chip  20 . The through electrodes  25   d  and  25   e  may be for power supply and coupled to the power supply wirings  22 . The area  21   d  may be disposed between an end  28   a  and the memory cell array  23   a , adjacent to the memory cell array  23   a  and aligned to the memory cell array  23   a  along the first direction  300 . The area  21   e  may be disposed between an end  28   b  and the memory cell array  23   d , adjacent to the memory cell array  23   d  and aligned to the memory cell array  23   d  along the third direction  300 ′. It may be possible to have substantially the same resistance between circuitry portions in the area  21   d  and  21   e . For example, the areas  21   d  and  21   e  may be symmetric with respect to the area  21   a . A distance between the areas  21   a  and  21   d  and a distance between the areas  21   a  and  21   e  may be substantially the same. A number of the plurality of through electrodes  25   d  and a number of the plurality of through electrodes  25   e  may be substantially the same. 
       FIG. 5B  is a schematic diagram of the semiconductor device including the interface chip and the plurality of core chips in  FIG. 5A .  FIG. 5B  is a cross-sectional view of a portion of the semiconductor device indicated by X-X′ of  FIG. 5A . The cross-sectional view includes cross sections of the power supply through electrodes  25   d  and  25   e  disposed in the area  21   d  and  21   e  of  FIG. 5A . The power supply through electrodes  25   d  and  25   e  may supply power supply voltage from the external terminals  5  through the substrate wirings  26  of the substrate  2  to the plurality of chips  20  (e.g., the interface chip  3  and the plurality of core chips  4 ). 
       FIG. 5C  is a schematic view of the power supply through electrodes and the power supply wirings in  FIGS. 5A and 5B . In  FIG. 5C , each of the power supply through electrodes  25   a  to  25   e  and the power supply wirings  22  may be modeled as a resistor. Each of the resistor group  24   d  may include the plurality of power supply through electrodes  25   d  in the area  21   d , and each of the resistor groups  24   e  and  24   e ′ may include the plurality of power supply through electrodes  25   e  and  25   e ′ in the area  21   e , respectively. The plurality of power supply through electrodes  25   d  are coupled in series along the fourth direction  320  by the plurality of terminals  27 . Similarly, the plurality of power supply through electrodes  25   e  in the resistor groups  24   e  are coupled in series along the fourth direction  320  and the plurality of power supply through electrodes  25   e ′ in the resistor groups  24   e ′ are coupled in series along the fourth direction  320 . As described above, the power supply through electrodes  25   e  and  25   e ′ may supply the power supply voltage to the plurality of chips  20  through the through wirings disposed located in the area  21   e  of  FIGS. 5A and 5B . In this case, a resistance between the external terminals  5  and a portion at an electrically farther end, such as a circuitry portion at the ends of the plurality of chips  20  and or a circuitry portion on upper chips becomes smaller because additional electrical paths for power supply may be provided by through electrodes  25   d ,  25   e , and  25   e ′ in proximity of the ends  28   a  and  28   b  of the plurality of chips  20  located in the areas  21   d  and  21   e . Thus, the additional electrical paths may reduce voltage drops due to power consumption in circuits on the plurality of chips  20  and therefore stabilize operations in the circuits. 
       FIG. 6A  is a simplified layout diagram of memory cell arrays of a chip in a semiconductor device, in accordance with an embodiment of the present disclosure. Description of components corresponding to components included above will not be repeated and wirings are not shown in  FIG. 6A . A memory cell array region  60  may include a plurality of banks  62 . For example, column decoders  64  and row decoders  65  may be provided for each bank. A plurality of row decoders  65  may be disposed at sides of a main amplifier  63  in one direction of each bank. For example, each of memory cell arrays  23   a  to  23   d  may include the plurality of banks  62  divided by the row decoders  65  and the column decoders  64 . The column decoders  64  may be disposed between the plurality of banks  62  in a direction substantially perpendicular to the one direction. The area  21   a  may include the power supply through electrodes  25   a  for power supply from the external terminals  5  and other through electrodes for communication via external terminals. The area  21   c  may include the power supply through electrodes  25   c  for power supply from the external terminals  5 . The area  21   a  may include peripheral circuit voltage (VPERI) generators  67  that provide a peripheral voltage VPERI. The area  21   c  may include array-system circuit voltage (VARY) generators  66  that provide an array-system circuit voltage (VARY) and the VPERI generators  67 . For example, the area  21   c  may include a portion  68  including the power supply through electrodes  25   c , the VARY generator  66  and one VPERI generator  67 . 
       FIG. 6B  is a layout diagram of the portion  68  of the memory cell array of the chip of  FIG. 6A . The portion  68  may be disposed between the plurality of banks  62  and may include the power supply through electrodes  25   c , the VARY generator  66  and the VPERI generator  67 . The VARY may be provided for sense amplifier circuits whereas the VPERI may be used among many circuits on the chip. For example, the VARY generator  66  and the VPERI generator  67  may provide the VARY and the VPERI that may be decoupled from each other. The VARY and the VPERI may be the same. The VARY and the VPERI may be different from each other. The VARY generator  66  and the VPERI generator  67  may be located adjacent to corresponding power supply through electrodes  25   c  supplied with an external power supply voltage V DD  (not shown, e.g., 1.2V) and a ground voltage V SS  (not shown, e.g., 0V). The VARY generator  66  may generate the VARY (e.g., about 1.0V) based on V DD  and V SS . The VPERI generator  67  may generate the VPERI (e.g., about 0.9V to 1.0V) based on V DD  and V SS . Thus, disposing the power supply through electrodes  25   c  in proximity to the VARY generators  66  and the VPERI generators  67  will reduce power consumption due to small resistance between the power supply through electrodes  25   c  and the VARY generators  66  or the VPERI generators  67  and therefore stabilize operations in circuits on the memory cell array. Similarly, the area  21   b  may include the VARY generator  66  and the VPERI generator  67  between a plurality of banks  62 . The area  21   b  may include the power supply through electrodes  25   b  disposed in proximity to the VARY generators  66  and the VPERI generators  67  to achieve the similar effect as the power supply through electrodes  25   c  in the area  21   c.    
       FIG. 7  is a schematic diagram of a semiconductor system including a semiconductor device that includes an interface chip and a plurality of core chips, in accordance with an embodiment of the present disclosure. For example, the semiconductor system  70  may include a semiconductor device  1 , which is a three-dimensional (3D) memory device, and a central processing unit (CPU) and memory controller  71 , which may be a controller chip, on an interposer  72  on a package substrate  73 . The interposer  72  may include one or more power lines  75  which supply power supply voltage from the package substrate  73 . The interposer  72  includes a plurality of channels  79  that may interconnect the CPU and memory controller  71  and the semiconductor device  1 . For example, the semiconductor device  1  may be an HBM, an HMC, a Wide-IO DRAM, etc. The semiconductor device  1  may include a plurality of chips  20  including an I/F chip  3  and core chips  4  stacked with each other. In this example, each core chip  4  may be a memory chip. Each of the memory chip  20  may include a plurality of memory cells and circuitries accessing the memory cells. For example, the memory cells may be DRAM memory cells. The semiconductor device  1  may include conductive vias TSVs  25  (e.g., through substrate electrodes) which couple the I/F chip  3  and core chips  4  by penetrating the I/F chip  3  and core chips  4 . The I/F chip  3  may be coupled to the interposer  72  via interconnects, such as bumps  74 . For example, the bumps  74  may be microbumps having bump pitches of less than about or less than one hundred micro meters and exposed on an outside of the I/F chip  3 . A portion of the bumps  74  may be coupled to the one or more power lines  75 . Another portion of the bumps  74  may be coupled to the plurality of channels  79 . 
     Logic levels of signals used in the embodiments described the above are merely examples. However, in other embodiments, combinations of the logic levels of signals other than those specifically described in the present disclosure may be used without departing from the scope of the present disclosure. 
     Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.