Abstract:
A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL apparatus. The synchronizing-edge detector detects a sample signal the frequency of which is the common divisor of the frequencies of the input and output signal. The PLL apparatus may be provided with a detection terminal connected with one of the input terminals of a pre-divider and loop divider for outputting the sample signal. Alternatively, the PLL system can comprise at least one additional divider coupled to the input and/or output signals of a PLL apparatus to generate the sample signal.

Description:
BACKGROUND  
       [0001]     The invention relates to distributed clock circuits and more particularly to a method and circuit of detecting synchronizing edges in a PLL system.  
         [0002]     Demands created by high-speed electronic equipment have generated a number of problems for circuit designers and manufacturers. For example, many applications require that two subsystems running at different frequencies communicate with each other. Generally, logic running at a given clock frequency is said to be operating in a clock domain.  
         [0003]     This synchronization problem has been previously addressed either by a single clock system architecture, which eliminates the number of clock domains, or by a multiple clock system architecture, which adds synchronization logic. Although utilizing a single clock system is simple, straightforward and low cost, each subsystem in the single clock system may not be optimized.to its fullest potential, downgrading overall system performance. Also, there are practical limitations as to how many components a single clock source may support. Thus, a single clock system is not always feasible in most situations.  
         [0004]     Alternatively, in multiple clock system architecture, dual ports or/and two port memories are required to transform blocks of information between different clock domains. This enables each subsystem to be optimized to its fullest potential, providing a robust solution. However, the dual port or/and tow port memories produce additional hardware cost. Additionally, the synchronization logic between different clock domains causes synchronization delay and meta-stability problems, adding latency. The disparity between the clock domains often includes different frequencies and/or phases, complicating the synchronization circuit design and adding significantly to the latency cost.  
         [0005]     U.S. application Ser. No. 6,836,521 discloses a distributed clock generator loop based on gear ratio and phase alignment techniques to address the synchronizing problem while minimizing any latency caused by the additional synchronization circuitry. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period to be phase aligned. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). Using the coloring technique, the appropriate clock edge for a data or control signal transfer can be identified. The edges are preferably chosen to minimize latency of the transfer. The distributed clock generator loop enables each subsystem to be optimized to its fullest potential, providing a robust solution at lower costs than a multiple clock system.  
         [0006]      FIG. 1  shows clock waveforms of an exemplary gear ratio wherein three cycles of clock CLK 1   10  equal two cycles of clock CLK 2   20 , or  3 * (cycle of CLK 1 )=2* (cycle of CLK 2 ). As shown, CLK 1  and CLK 2  are phase aligned at the end of the common period. Since gear ratio is defined as the ratio of the two clock frequencies, in this example the gear ratio of CLK 1 /CLK 2  is 3/2. If clock signals CLK 1   10  and CLK 2   20  are divided by 6 and 4, respectively, a clock signal  30  results which is equal to CLK 1 / 6  or CLK 2 / 4 .  
         [0007]      FIG. 2  shows a distributed generator loop  200  applied to a Memory Control Unit  206  with two clock domains operating in gear ratio fashion disclosed in U.S. application. Ser. No. 6,836,521. The architecture contains a clock source  202 , a distributed clock generator (DCG)  204 , and Memory Control Unit  206  with logic running in two clock domains, PCLK  208  and SCLK  210 . The clock source  202  generates PCLK  208  for Memory Control Unit  206  and a reference signal PEFCLK  240  for the distributed loop. DCG  204  receives PEFCLK  240 . PEFCLK  240  is multiplied utilizing clock dividers,  212  and  214 , and a phase-locked loop (PLL)  216  to generate LOOPCLK  218  of another frequency. The output of PLL  216  is a phase aligner  220 . The output frequency of the phase aligner  220  is equal to its input frequency, but the output phase is delayed from the input phase by an error signal Err  238  output from a phase detector  222 .  
         [0008]     The phase detector compares the relative phases of PCLK_M  224  and SCLK_N  226  from a gear ratio Logic  228  in Memory Control Unit  206  and outputs the error signal Err  238  to drive the phase aligner  220  until the phase of SCLK_N  226  matches the phase of PCLK_M  224 . When the output phase of the phase aligner  220  changes, the phase of SCLK  210  will have the same amount of phase change, and phase error between PCLK  208  and SCLK  210  is minimized.  
         [0009]      FIG. 2  shows two sub-blocks  230  and  232  in gear ratio Logic  228 . The sub-block  230  divides PCLK  208  by M to generate PCLK_M  224  and PCOLOR  234 ,; and the clock divider  232  divides SCLK  210  by N to generate SCLK_N  226  and SCOLOR  236 . The two divided clocks, PCLK_M  224  and SCLK_N  226 , as described, are output from Memory Control Unit  206  and passed back to DCG  204  as inputs to the phase detector  222 .  
         [0010]      FIG. 3  shows a timing diagram of signals associated with gear ratio Logic  228  with a 3/2 gear ratio. The cycle time of SCLK  210  is 3/2 times the cycle time of PCLK  208 . PCOLOR  234  is incremented from a value 000 through a value 010 (i.e., 000, 001, 010) on each edge of PCLK  208 . When PCOLOR  234  reaches a maximum value 010, PCOLOR  228  clears to 000 and in turn, toggles the value of PCLK/M  224 . Thus, PCLK/M  224  alternates from 0 to 1 every three cycles of PCLK  208 , or one cycle Tccyc  310 .  
         [0011]     On the other hand, SCOLOR  236  reaches a maximum value of 001 in this example, at which point the value of SCOLOR  236  clears to 000 and in turn, toggles the value of SCLK/N  226 . Thus, SCLK/N  226  alternates from 0 to 1 every two cycles of SCLK  210 , or one cycle TCCYC  310 .  
         [0012]     In a 3/2 configuration, PCOLOR  234  and SCOLOR  236  indicate the value of counts in progress for PCLK  208  and SCLK  210 , respectively. PCOLOR  234  is asserted for three cycles of PCLK  208  (as shown by encircled 1, 2, and 3) and SCOLOR  236  is asserted for two cycles of SCLK  210  (as shown by encircled 1 and 2). Thus, PCLK/M  224  and SCLK/N  226  measure the relative phase of PCLK  208  and SCLK  210 . Furthermore, as shown in  FIG. 2 , PCLK/M  224  and SCLK/N  226  are driven to a clock generator  220 . Hence, SCLK  210  becomes a phase-aligned clock signal.  
         [0013]     The value for PCOLOR  234  indicates when data read and write operations should take place to ensure data transfer at correct edges, referred to as color coding scheme.  
         [0014]     However, the complex logics are introduced due to the phase align logics, gear logics and so on. This may make the implementation uneasy and inefficient. Additionally, if M and N are not co-prime numbers, the synchronizing edges of PCLK  208  and SLK  210  within the longer Tccyc  310  are wasted and the performance are thus degraded.  
         [0015]     In view of this disadvantage, a new method and apparatus is disclosed to detect the synchronizing edges of the clocks in different domains which can be used to indicate when data read and write operations should take place in a digital system while having higher performance, speed and lower cost and also can be migrated into the new manufacturing process and conventional PLL easily.  
       SUMMARY  
       [0016]     The invention provides a method and system of detecting synchronizing edges of two clock signals having a gear relationship for generation of distributed clocks for a system with multiple clock domains.  
         [0017]     A detection terminal is added to a conventional PLL apparatus to form a new PLL apparatus. A sample signal at one of the input terminals of a phase comparator in the conventional PLL is accessed through the detection terminal, detecting the synchronizing edges of the input and output clock signals of the new PLL apparatus, since the sample signal has a frequency which is a common divisor of the input and output clock signals of the new PLL apparatus.  
         [0018]     Alternatively, at least one divider can be coupled to the input or/and output signal of a conventional PLL apparatus to generate a sample signal for the synchronizing edges of the input and output clock signals for the PLL apparatus.  
         [0019]     The invention also provides a synchronizing-edge detector to detect synchronizing edges of the input and output clock signals for a PLL apparatus using a sample signal obtained as described and a reference signal selected from the input and output clock signals of the PLL apparatus as long as the sample signal has a frequency of a common divisor of the input and output clock signals of the new PLL apparatus. The synchronizing-edge detector comprises a counter generating a counting signal incremented on each edge of the reference signal selected from one of the first and second clock signals, a global reset module generating a global signal asserted by the rising edges of the sample clock signal resetting the counting signal, a local reset module to generate a local signal resetting the counting signal together with the global signal, wherein the local signal is asserted by the counting signal when the counting signal reaches a first value. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings in which:  
         [0021]      FIG. 1  shows clock waveforms of an exemplary gear ratio relationship;  
         [0022]      FIG. 2  is a schematic diagram of a conventional distributed clock generator loop;  
         [0023]      FIG. 3  is a timing diagram of gear ratio Logic signals with a 3/2 gear ratio in the conventional distributed clock generator loop of  FIG. 2 ;  
         [0024]      FIG. 4  is a schematic diagram of aphase locked loop system in accordance with an embodiment of the invention;  
         [0025]      FIG. 5  is a schematic diagram of a synchronizing-edge detector in accordance with an embodiment of the invention;  
         [0026]      FIG. 6  is a timing diagram of signals associated with synchronizing-edge detector of  FIG. 5  with (MS,NS)=(6,4) for PLL system of  FIG. 4 ;  
         [0027]      FIG. 7  is a schematic diagram of a synchronizing-edge detector in accordance with another embodiment of the invention;  
         [0028]      FIGS. 8   a  and  8   b  are timing diagrams of signals associated with synchronizing-edge detector of  FIG. 5  with (MS,NS)=(6,4) and (3,2) respectively for PLL system of  FIG. 7 ;  
         [0029]      FIG. 9  is a schematic diagram of a synchronizing-edge detector in accordance with another embodiment of the invention;  
         [0030]      FIG. 10  is a schematic diagram of a synchronizing-edge detector in accordance with another embodiment of the invention;  
         [0031]      FIG. 11  is a schematic diagram of a synchronizing-edge detector in accordance with another embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0032]      FIG. 4  is a schematic diagram of a phase locked loop (PLL) system  400  in accordance with an embodiment of the invention. The PLL system  400  includes a PLL apparatus  402  and a synchronizing-edge detector  404 . The PLL apparatus  402  receives a first clock signal CLK 1  of frequency f 1  to provide a second clock signal CLK 2  of frequency f 2 , wherein f 2  has a gear relationship with f 1 . The synchronizing-edge detector  404  produces an output clock signal CLKO indicative of synchronizing edges of the first and second clock signals. The PLL apparatus  402  can be implemented as an integrated circuit alone or can be integrated with the synchronizing-edge detector  404  into a single integrated circuit.  
         [0033]     Typically, the PLL apparatus  402  comprises a pre-divider  406  dividing the first clock signal CLK 1  by an integer MS into a third clock signal CLK 3  of frequency f 3  (that is, f 3 =f 1 /MS), a loop-divider  408  dividing the second clock signal CLK 2  by an integer NS into a fourth clock signal CLK 4  of frequency f 4  (that is, f 4 =f 2 /NS), wherein f 3 =f 4  as the PLL apparatus  402  is in lock, a phase comparator  410  making a comparison between the third and fourth clock signal, a charge pump circuit  412  producing a control voltage in accordance with the output of the phase comparator  410 , a voltage-controlled oscillator  414 , the oscillation frequency of which is controlled by the control voltage of the charge pump circuit  412  to generate the second clock signal CLK 2 , and a detection terminal  416  connected to the third or fourth clock signal. The detection terminal  416  can be electrically connected outwards to provide a sample clock signal CLKS selected from the third and fourth clock signals for the detection of the synchronizing edges of the first and second clock signals. One unique portion of the invention is that the detection terminal  416  is added to a conventional PLL apparatus not limited to any specific type. The detection terminal  416  is carefully routed such that the sample clock signal CLKS at the detection terminal  416  and the output signal of the pre-divider  406  or the loop-divider  408  chosen to be the sample clock signal CLKS have the same latency and no time skew.  
         [0034]      FIG. 5  is a schematic diagram of a synchronizing-edge detector  404  in accordance with an embodiment of the invention. The synchronizing-edge detector  404  receives two signals, a sample clock signal CLKS selected from the third and fourth clock signals, and a reference signal CLKR selected from the first and second clock signals. Counter  502  generates a counting signal COUNT measuring the time after the rising edge of the sample clock signal CLKS. The counting signal COUNT is incremented on each edge of the reference signal CLKR and cleared by a global reset signal CLKG or a local reset signal CLKL. Global reset circuit  506  asserts the global reset signal CLKG when detecting each rising edge of the sample clock signal CLKS. Local reset circuit  508  asserts the local reset signal CLKL whenever the counting signal COUNT reaches a maximum value NMAX 1 , where 
   N MAX1=MAX( MS,NS )/ GCD ( MS,NS )−1,  
 such that the cycle time of the local reset signal CLKL is equal to that of the synchronizing edges of the first and second clock signals. Informing circuit  504  asserts output clock signal CLKO each time the counter  506  reaches a fixed value NMAX 2 . In one embodiment, the fixed value NMAX 1 =NMAX 2 . In such a process, the output clock signal CLKO is indicative of the synchronizing edges of the first and second clock signals and can be used to tell when data read and write operations should take place in adigital system with multiple clock domains. It is noted that the synchronizing-edge detector is skew tolerant. That is, the skew between the reference clock signal CLKR and the sample clock signal CLKS (shown as gray regions) is as tolerant as possible. Moreover, such configuration can achieve very high speed and performance. 
 
         [0035]      FIG. 6  is a timing diagram of signals associated with a synchronizing-edge detector  404  where MS=6 and NS=4 using the first clock signal CLK 1  as the reference clock signal CLKR for illustration. In such a case, the cycle time of the first clock signal CLK 1  is 6/4 times that of the second clock signal CLK 2 , that is, gear ratio is 6/4. The global reset signal CLKG is asserted at a fixed time after each rising edge of the sample clock signal CLKS. The counting signal COUNT as shown is incremented from 0 through 2 at a short time after each edge of the rising edge of the first clock signal CLK 1 . The counting signal COUNT is initially reset by the global reset signal CLKG, and when it reaches NMAX 1  (2), the local reset signal CLKL is asserted, which in turn resets the counting signal COUNT to zero. In response, the output signal CLKO is asserted to indicate the synchronizing edges of the first and second clock signals.  
         [0036]     In the embodiment, the cycle time of the global reset signal is equal to that of the synchronizing edges of the first and second clock signals. Therefore, in one period of the global reset, there occur twice the synchronizing edges of the first and second clock. One advantage of the invention over conventional edge-detecting, techniques is that even though MS and NS are not co-prime, every synchronizing edge of the first and second clock signals can be detected through the counting signal COUNT reset by the local reset signal CLKL.  
         [0037]     Those with ordinary skill in the art should recognize that cycle time of the counting signal needs not be the same as that of the reference clock signal CLKR, for example, it can be ½, ⅓ and etc. Also, the configuration of the synchronizing-edge detector in  FIG. 5  is illustrated only by way of example. Any other implementation capable of indicating the synchronizing edges by detecting the edges of the sample clock signal CLKS can be employed.  
         [0038]     The sample clock CLKS needs not to be the third or fourth clock signal. Third and fourth clock can be used as the sample clock CLKS because their frequency is a common divisor of the first and the second clocks and can therefore generate the global reset signal CLKG to reset the counting signal COUNT. With the aid of the local reset signal CLKL, every synchronizing edge of the first and second clock signals can be detected. Thus, any other clock signal originating from the PLL apparatus can be employed as the sample clock CLKS as long as its frequency is a common divisor of the first clock and the second clocks. As shown, this allows the PLL apparatus to be any conventional PLL apparatus without modification.  
         [0039]      FIG. 7  is a schematic diagram of aphase locked loop (PLL) system  700  in accordance with another embodiment of the invention. The PLL system  700  comprises a conventional PLL apparatus  702  receiving a first clock signal CLK 1  of frequency f 1  to provide a second clock signal CLK 2  of frequency f 2 , wherein the first and second clock signals have a gear ratio relationship and f 1 =f 2  when the PLL apparatus  702  is locked. The PLL system  700  further comprises a synchronizing-edge detector  404 , and a first divider  716  dividing the first clock signal CLK 1  by an integer MSa into a pre-reference clock signal CLKPR.  
         [0040]     The conventional PLL apparatus  702  is not limited to any specific type and has a configuration known in the art. Typically, it comprises a pre-divider  406  dividing the pre-reference clock signal CLKPR by an integer MSb into a third clock signal CLK 3  of frequency f 3  (that is, f 3 =fpr/MSb, where fpr is the frequency of the pre-reference clock signal CLKPR.), a loop-divider  408  dividing the second clock signal CLK 2  by an integer NS into a fourth clock signal CLK 4  of frequency f 4  (that is, f 4 =f 2 /NS), a phase comparator  410 , a charge pump circuit  412 , and a voltage-controlled oscillator  414 , as well shown in the art. When the PLL apparatus  202  is in lock, f 3 =f 4 . That is, 
 
 f 1 /f 2 =MS/NS   (1). 
 
         [0041]     The pre-reference clock signal CLKPR is fed into both a pre-divider  406  of the PLL apparatus  702  and the synchronizing-edge detector  404  as a sample clock signal CLKS. That is, 
 
 fpr=f 1 /MSa   (2), 
 
 where fpr is the frequency of the pre-reference clock signal CLKPR. 
 
         [0042]     Combining (2) with formula f 3 =fpr/Msb, we get f 3 =f 1 /(MSa*MSb). This means 
 
 MS=MSa*MSb   (3). 
 
         [0043]     In the embodiment, MSb is required to be a divisor of NS, that is, 
 
 LCM ( NS,MSb )= NS   (4), 
 
 where LCM(NS,MSb) is the least common multiple of NS and MSb. 
 
 Or in another expression, 
 
 NS=MSb*I   (4′), 
 
 where I is an integer. 
 
         [0044]     This requirement renders the frequency fpr of the pre-reference clock signal CLKPR a common divisor of the frequencies of the first and second clock signal, such that the pre-reference clock signal CLKPR can be used as the sample clock signal CLKS. By combining the formulas (1), (2), (3) and (4′) into 
 
 fpr/ 1 =f 2 /I   (5), 
 
 it can be seen clearly in (5) that fpr is a common divisor of the first and second clock signals. 
 
         [0045]      FIG. 8A  shows a timing diagram of signals associated with the synchronizing-edge detector  404  with MS=6 and NS=4 (gear ratio is 6/4) and the first clock signal CLK 1  as the sample clock signal CLKS for illustration. In such a case, MSb can be chosen as 2 to satisfy formula (4) and hence MSa=3.  FIG. 8A  is in all respects except one the same as  FIG. 6 . The difference is that the sample clock signal CLKS is the pre-reference clock signal CLKPR rather than the third or fourth clock signal. This causes the cycle time of the global reset signal CLKG to be half that in  FIG. 5 . However, this does not affect the timings of the local clock signal CLKL nor the counting clock signal COUNT. Resultingly, As shown in  FIG. 8A , the global reset signal CLKG is asserted at a fixed time after each rising edge of the sample clock signal CLKS. The counting signal COUNT is incremented from 0 through 2 a short time after each edge of the rising edge of the first clock signal CLK 1 . The counting signal COUNT is initially reset by the global reset signal CLKG, and when it reaches 2, the local reset signal CLKL is asserted, which in turn resets the counting signal COUNT to 0. In response, the output clock signal CLKO is asserted to indicate the synchronizing edges of the first and second clock signals.  
         [0046]      FIG. 8B  is another timing diagram of signals associated with the synchronizing-edge detector  404  with MS=3 and NS=2 (gear ratio is 3/2) and the first clock signal CLK 1  as the sample clock signal CLKS for illustration. In such a case, MSb can be chosen as 1 to satisfy formula (4) and hence MSa=3.  FIG. 8B  is in all respects except one the same as  FIG. 8B . The difference is that the cycle time of the third or fourth clock signal is half that in  FIG. 8B . However, this does not affect the timing of the global reset signal CLKG. Resultingly, the timing of the output clock signal CLKO does not change. As a result, the output signal CLKO accurately indicates the synchronizing edges of the first and second clock signals.  
         [0047]      FIG. 9  is a schematic diagram of a phase locked loop (PLL) system  900  in accordance with another embodiment of the invention.  FIG. 9  is in all respects except one the same as  FIG. 7  and formula (1) is still a target. The difference is that the first divider  716  dividing the first clock signal CLK 1  by an integer MSa is now replaced by a second divider  916  dividing the second clock signal CLK 2  by an integer NSa into a pre-reference clock signal CLKPR, that is, 
   fpr=f 2 /NSa   (6),  
 where fpr is the frequency of the pre-reference clock signal CLKPR. 
 
         [0048]     The pre-reference clock signal CLKPR is sequentially fed into the loop divider  408  and the synchronizing-edge detector  404  as the sample clock signal CLKs. THe loop-divider  408  divides the pre-reference clock signal CLKPR by NSb into the fourth clock signal CLK 4  of frequency f 4 . That is, 
 
 f 4 =fpr/NSb   (7). 
 
 Combining formula (6) with formula (7), we get f 4 =f 2 /NSa*NSb, which means 
 
 NS=NSa*NSb   (7′). 
 
         [0049]     In the embodiment, NSb is required to be a divisor of MS, that is, 
 
 LCM ( MS,NSb )= MS   (8), 
 
 where LCM(MS,NSb) is the least common multiple of MS and NSb. Or in another expression, 
 
 MS=NSb*I   (8′), 
 
 where I is an integer. 
 
 By combining the formulas (1), (6), (7) and (8′), formula 
 
 fpr/ 1 =f 1 /I   (9) 
 
 is obtained. Thus, referring to formulas (6) and (9), it can be seen clearly that fpr is a common divisor of the first and second clock signal. Thus, the pre-reference clock signal CLKPR can be used as the sample clock signal CLKS. 
 
         [0050]      FIG. 10  is a schematic diagram of a PLL system  1000  in accordance with another embodiment of the invention. The PLL system  1000  comprises a conventional PLL apparatus  702 , a synchronizing-edge detector  404 , a first divider  716  and a second divider  916 . As shown, The PLL system  400  is in all respects except one the same as PLL system  700  of  FIG. 7  and formula (1) is still a target. The difference is the addition of the second divider  916 . The first divider  716  divides the first clock signal CLK 1  by an integer MSa into a first pre-reference clock signal CLKPR 1 . The first pre-reference clock signal CLKPR 1  is then fed into the pre-divider  406  and into the synchronizing-edge detector  404  as the sample clock signal CLKS, that is, 
   fpr 1 =f 1 /MSa   (10),  
 where fpr 1  is the frequency of the first pre-reference clock signal CLKPR 1 . 
 
         [0051]     The first pre-reference clock signal is then divided by the pre-divider  406  by an integer MSb into the third clock signal CLK 3 , that is, 
 
 f 3 =fpr 1 /Msb   (11). 
 
 Combining (10) with (11), we get f 3 =f 1 /MSa*MSb, which means 
 
 MS=MSa*MSb   (11′). 
 
         [0052]     Similarly, the second divider  916  divides the second clock signal CLK 2  by an integer NSa into a second pre-reference clock signal CLKPR 2 , that is, 
 
 fpr 2= f 2 /NSa   (12). 
 
 where fpr 2  is the frequency of the second pre-reference clock signal CLKPR 2 . The second pre-reference clock signal CLKPR 2  is then divided by the loop-divider by an integer NSb into the fourth clock signal CLK 4 , that is, 
 
 f 4 =fpr 2 /Nsb   ( 13).  
 
 Combining (2) with (3), we get f 4 =f 2 /NSa*NSb, which means 
 
 NS=NSa*NSb   (13′). 
 
         [0053]     In the embodiment, MSb is required to be a divisor of NSb, that is, 
 
 LCM ( MSb,NSb )= NSb   (14), 
 
 where LCM(MSb,NSb) is the least common multiple of MSb and NSb. This requirement renders the frequency fpr 1  of the first pre-reference clock signal CLKPR 1  a common divisor of the frequencies of the first and second clock signal, such that the first pre-reference clock signal CLKPR 1  can be used as the sample clock signal CLKS for the detection of the synchronizing edges of the first and second clock signal. 
 
         [0054]      FIG. 11  is a schematic diagram of a phase locked loop (PLL) system  1100  in accordance with another embodiment of the invention. The PLL system  1100  comprises a conventional PLL apparatus  702 , a synchronizing-edge detector  404 , a first divider  716  and a second divider  916 . As shown, The PLL system  1100  is in all respects except one the same as PLL system  900  of  FIG. 9  and formula (1) is still a target. The difference is the addition of the first divider  716 .  
         [0055]     The first divider  716  divides the first clock signal CLK 1  by an integer MSa into a first pre-reference clock signal CLKPR 1 , that is, 
 
 fpr 1 =f 1 /MSa   (15), 
 
 where fpr 1  is the frequency of the first pre-reference clock signal CLKPR 1 . The first pre-reference clock signal CLKPR 1  is then divided by the pre-divider  716  by an integer MSb into the third clock signal CLK 3 , that is, 
 
 f 3 =fpr 1 /Msb   (16). 
 
 Combining (15) with (16), we get f 3 =f 1 /MSa*MSb, which means 
 
 MS=MSa*NSb   (16′). 
 
         [0056]     Similarly, the first divider  916  divides the second clock signal CLK 2  by an integer NSa into a second pre-reference clock signal CLKPR 2  which is also fed into the loop-divider  408  and into the synchronizing-edge detector  404  as the sample clock signal CLKS, that is, 
 
 fpr 2 =f 2 /NSa   (17). 
 
         [0057]     The second pre-reference clock signal CLKPR 2  is then divided by the loop-divider by an integer NSb into the fourth clock signal, that is, 
 
 f 4 =fpr 2 /Nsb   (18). 
 
 Combining (10) with (11), we get f 4 =f 2 /NSa*NSb, which means 
 
 NS=NSa*NSb   (18′). 
 
         [0058]     In the embodiment, NSb is required to be a divisor of MSb, that is, 
 
 LCM ( MSb,NSb )= MSb   (19), 
 
 where LCM(MSb,NSb) is the least common multiple of MSb and NSb. This requirement renders the frequency fpr 2  of the second pre-reference clock signal CLKPR 2  a common divisor of the frequencies of the first and second clock signal, such that the second pre-reference clock signal CLKPR 2  can be used as the sample clock signal CLKS for the detection of the synchronizing edges of the first and second clock signal. 
 
         [0059]     In conclusion, the invention can be migrated into the conventional PLL readily. The invention does not require the type of the conventional PLL apparatus to be added with the detection terminal or to be coupled to additional dividers for detection of the input and output clock signals of the new PLL apparatus. Further, the synchronizing detector provides high speed at lower costs.  
         [0060]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.