Abstract:
A voltage regulator includes a voltage regulation unit that regulates an external power supply voltage and outputs an internal voltage, and an optimization control unit that adjusts a bias current, drivability, and output capacitance of the voltage regulation unit in response to a training enable signal and optimizes the internal voltage to a predetermined value.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2015-0143914, filed on Oct. 15, 2015, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate generally to semiconductor design technology and more particularly, to a voltage regulator for a semiconductor device and an operating method thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    An integrated circuit such as a semiconductor memory device may be a functionally complex electronic device or system having a microstructure in which many electronic circuit elements are inseparably defined on a semiconductor substrate. Because the electronic circuit elements in such an integrated circuit may have a micro size, even very small fluctuations in a current or voltage supplied to the integrated circuit may cause the integrated circuit to malfunction. 
         [0006]    For maintaining a voltage supplied to the integrated circuit constant, a regulator circuit for constantly controlling the output of a voltage supply circuit is required. 
         [0007]    Generally, proper operation of a semiconductor memory device may require simultaneous generation of a plurality of operation voltages when programming data, including, for example, program and pass voltages. In this regard, one or more regulator circuits may be required for regulating the respective operation voltages. 
       SUMMARY 
       [0008]    Various embodiments of the present invention are directed to a voltage regulator capable of optimizing an output voltage and an operating method thereof. 
         [0009]    In an embodiment, a voltage regulator may include: a voltage regulation unit suitable for regulating an external power supply voltage and for outputting a constant internal voltage; and an optimization control unit suitable for adjusting a bias current, a drivability, and an output capacitance of the voltage regulation unit in response to a training enable signal and for optimizing the internal voltage to a predetermined value. 
         [0010]    The voltage regulation unit may include: a comparator suitable for comparing a reference voltage with a feedback voltage for outputting a driving signal and for operating using the bias current; a bias current adjustment section suitable for adjusting the bias current supplied to the comparator in response to a first control signal; a pass device adjustment section suitable for outputting the external power supply voltage to an output terminal as the Internal voltage according to the driving signal, and for adjusting the drivability in response to a second control signal; a capacitor adjustment section suitable for adjusting the output capacitance in response to a third control signal; and a voltage division section suitable for dividing the output voltage and for outputting a divided voltage to an Input terminal of the comparator as the feedback voltage. 
         [0011]    The optimization control unit may include: an average detecting section suitable for detecting an average value of the internal voltage corresponding to a first or a second mode in response to the training enable signal; and a control signal generation section suitable for comparing the average value of the internal voltage with a target value for generating the first to third control signals. 
         [0012]    The average detecting section may include: an undershoot detecting part suitable for detecting an undershoot peak voltage of the internal voltage; a mode selection part suitable for selectively outputting an output signal of the undershoot detecting part or the Internal voltage in response to a mode selection signal; an analog-to-digital converter suitable for converting an output signal of the mode selection part into digital code values; and an average calculating part suitable for outputting an average value of the digital code values outputted from the analog-to-digital converter. 
         [0013]    The mode selection part may select the internal voltage in the first mode and may select the output signal of the undershoot detecting part in the second mode. 
         [0014]    The control signal generation section may include: a register suitable for storing the target value; and an operation control part suitable for comparing the target value with the average value and for controlling each of the first to third control signals. 
         [0015]    Each of the first to third control signals may be provided in a plural number. 
         [0016]    The pass device adjustment section may include: a pass device selection part suitable for selecting one or more of a plurality of pass devices in response to the plurality of second control signals; and a pass device array part including the plurality of pass devices and suitable for driving the external power supply voltage in response to the driving signal. 
         [0017]    The pass device selection part may include a plurality of transfer elements suitable for transferring the driving signal to the pass device array part in response to the second control signals. 
         [0018]    The capacitor adjustment section may include: a capacitor transfer control part suitable for selecting one or more of a plurality of capacitors in response to the plurality of third control signals; and a capacitor array part including the plurality of capacitors and suitable for substantially maintaining the internal voltage to be constant. 
         [0019]    The capacitor transfer control part may include a plurality of transfer elements suitable for transferring the internal voltage to the capacitor array part. 
         [0020]    The voltage regulator may further include a frequency compensation section suitable for ensuring a phase margin of the Internal voltage. 
         [0021]    The average detecting section may include: an undershoot detecting part suitable for detecting an undershoot peak voltage of the internal voltage; a mode selection part suitable for selectively outputting an output signal of the undershoot detecting part or the internal voltage in response to a mode selection signal; a gain integrator suitable for integrating and outputting an output signal of the mode selection part; and an analog-to-digital converter suitable for converting an output signal of the gain integrator into a digital code value. 
         [0022]    The mode selection part may select the internal voltage in the first mode and may select the output signal of the undershoot detecting part in the second mode. 
         [0023]    In another embodiment, an operating method of a voltage regulator may include: detecting an undershoot of an output voltage of the voltage regulator; selecting the output voltage of the voltage regulator in a first mode and selecting the undershoot in a second mode in response to a mode selection signal; converting the output voltage or the undershoot into digital codes; calculating an average value of the digital codes; comparing the average value with a target value stored in a register and generating a control signal for controlling the voltage regulator; and performing a voltage regulating operation in response to the control signal. 
         [0024]    The generating of the control signal may include: comparing the target value with the average value and generating a first control signal for adjusting a current amount of a bias current of the voltage regulator; comparing the target value with the average value and generating a second control signal for adjusting the number of pass devices of the voltage regulator; and comparing the target value with the average value and generating a third control signal for adjusting output capacitance of the voltage regulator. 
         [0025]    Each of the first to third control signals may be provided in a plural number. 
         [0026]    The generating of the first control signal may include decreasing the number of activations of the plurality of first control signals when the target value is larger than the average value in the second mode; and increasing the number of activations of the plurality of first control signals when the target value is smaller than the average value in the second mode. 
         [0027]    The generating of the second control signal may include decreasing the number of activations of the plurality of second control signals when the target value is larger than the average value in the first mode; and increasing the number of activations of the plurality of second control signals when the target value is smaller than the average value in the first mode. 
         [0028]    The generating of the third control signal may include decreasing the number of activations of the plurality of third control signals when the target value is larger than the average value in the second mode; and increasing the number of activations of the plurality of third control signals when the target value is smaller than the average value in the second mode. 
         [0029]    According to the voltage regulator in accordance with embodiments of the present invention, an optimization operation of the voltage regulator can be performed in realtime in the circuit by itself, so that it is possible to reduce time and cost. 
         [0030]    Furthermore, since the voltage regulator provides digital output, digital measuring apparatuses are available instead of expensive analog measuring apparatuses, so that it is possible to easily evaluate undershoot and overshoot values very difficult to be measured. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIG. 1  is a configuration diagram illustrating a voltage regulator, according to an embodiment of the present invention. 
           [0032]      FIG. 2  is a circuit diagram illustrating an example of a bias current adjustment section of a voltage generator, according to an embodiment of the present invention. 
           [0033]      FIG. 3  is a circuit diagram illustrating an example of a pass device adjustment section of a voltage generator, according to an embodiment of the present invention. 
           [0034]      FIG. 4  is a circuit diagram illustrating an example of a capacitor adjustment section of a voltage generator, according to an embodiment of the present invention. 
           [0035]      FIG. 5  is a circuit diagram illustrating an example of an undershoot detecting part of a voltage generator, according to an embodiment of the present invention. 
           [0036]      FIG. 6  is a graph illustrating an example of an output signal of a mode selection part of a voltage generator, according to an embodiment of the present invention. 
           [0037]      FIG. 7  is a graph illustrating an example of an output signal of an analog-to-digital converter of a voltage generator, according to an embodiment of the present invention. 
           [0038]      FIG. 8  is a graph illustrating an example of an output signal of an average calculating part, according to an embodiment of the present invention. 
           [0039]      FIG. 9  is a configuration diagram illustrating a voltage regulator, according to another embodiment of the present invention. 
           [0040]      FIG. 10  is a graph illustrating an output signal of an example of a gain integrator of a voltage generator, according to another embodiment of the present invention. 
           [0041]      FIG. 11  is a graph illustrating an output signal of an example of an analog-to-digital converter of a voltage generator, according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0042]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0043]    Referring to  FIG. 1 , a voltage regulator, according to an embodiment of the present invention, may include a voltage regulation unit  10   a  and an optimization control unit  10   b . The voltage regulation unit  10   a  may include a comparator  110 , a bias current adjustment section  120 , a pass device adjustment section  130 , a frequency compensation section  140 , a voltage division section  150 , and a capacitor adjustment section  160 . 
         [0044]    The comparator  110  may compare a reference voltage VREF with a feedback voltage VFB to output a driving signal VDRV, and operate on the basis of a bias current ISS. 
         [0045]    The bias current adjustment section  120  may adjust a current amount of the bias current ISS supplied to the comparator  110 , in response to first control signals SEL 1 &lt;0:N&gt;. The first control signals SEL 1 &lt;0:N&gt; may be received from the optimization control unit  10   b  which will be described later. An operation of the bias current adjustment section  120  will be described in detail with reference to  FIG. 2 . 
         [0046]    The pass device adjustment section  130  may receive the driving signal VDRV from the comparator  110 , output an external power supply voltage VIN to an output terminal as an output voltage VOUT, and adjust drivability in response to second control signals SEL 2 &lt;0:N&gt;. The pass device adjustment section  130  may include a pass device selection part  131  and a pass device array part  132 . The output voltage VOUT may be an internal voltage for performing an internal operation. 
         [0047]    The pass device selection part  131  may control one or more of a plurality of pass devices to be driven in response to the second control signals SEL 2 &lt;0:N&gt;. The second control signals SEL 2 &lt;0:N&gt; may be received from the optimization control unit  10   b.    
         [0048]    The pass device array part  132  may drive a selected pass device in response to an output signal of the pass device selection part  131 . An operation of the pass device adjustment section  130  will be described in detail with reference to  FIG. 3 . 
         [0049]    The frequency compensation section  140  may ensure a phase margin for a frequency stability of a voltage regulation. The frequency compensation section  140  may, for example, include a miller capacitor (not illustrated). The frequency compensation section  140  may be disposed between the comparator  110  and the output terminal for a connection of the comparator to compensate for a frequency, thereby improving the phase margin. 
         [0050]    The voltage division section  150  may divide the output voltage VOUT and output the divided voltage to an input terminal of the comparator  110  as the feedback voltage VFB. The voltage division section  150  may, for example, include two resistors (not illustrated) for dividing the output voltage VOUT. 
         [0051]    The capacitor adjustment section  160  may adjust an output capacitance in response to third control signals SEL 3 &lt;0:N&gt;. The third control signals SEL 3 &lt;0:N&gt; may be received from the optimization control unit  10   b . An operation of the capacitor adjustment section  160  will be described in more detail with reference to  FIG. 4 . 
         [0052]    The optimization control unit  10   b  may evaluate a load or a transient regulation characteristic of the output voltage VOUT in response to a training enable signal EN_TRAINING, thereby optimizing a voltage regulation operation. A load regulation characteristic may indicate drivability, for example, a DC characteristic of the output voltage VOUT. A transient regulation characteristic may indicate a temporary voltage drop, for example, an AC characteristic of the output voltage VOUT. 
         [0053]    The optimization control unit  10   b  may include an average detecting section  11  and a control signal generation section  12 . The average detecting section  11  may include an undershoot detecting part  171 , a mode selection part  172 , an analog-to-digital converter  173 , and an average calculating part  174 . The control signal generation section  12  may include a register  176  and an operation control part  177 . The optimization control unit  10   b  may further include an output section  175 . 
         [0054]    The undershoot detecting part  171  may detect an undershoot i.e., a temporary drop in the output voltage VOUT. For example, the undershoot detecting part  171  may detect a peak voltage having the lowest voltage level when the output voltage VOUT drops. An operation of the undershoot detecting part  171  will be described in detail with reference to  FIG. 5 . 
         [0055]    The mode selection part  172  may selectively output an output voltage after having passed through the undershoot detecting part  171  or the output voltage VOUT without having passed through the undershoot detecting part  171 , in response to a mode selection signal MODE_SEL. The mode selection signal MODE_SEL may be inputted from an external device. The mode selection signal MODE_SEL may be controlled by the external device to optimize the load regulation characteristic of the output voltage VOUT, such as a DC characteristic. The mode selection signal MODE_SEL may be controlled by the external device to optimize the transient regulation characteristic of the output voltage VOUT, such as an AC characteristic. Hereinafter, for simplicity, an operation mode for optimizing a load regulation characteristic of the output voltage VOUT, such as a DC characteristic, may also be referred to as a first mode, whereas an operation mode for optimizing a transient regulation characteristic of the output voltage VOUT, such as an AC characteristic, may also be referred to as a second mode. 
         [0056]    The analog-to-digital converter  173  may convert analog code values of voltages outputted from the mode selection part  172  into digital code values D&lt;n&gt;. 
         [0057]    The average calculating part  174  may calculate an average value Q&lt;n&gt; of the digital code values D&lt;n&gt; outputted from the analog-to-digital converter  173 . The average calculating part  174  may, for example, calculate the average value Q&lt;n&gt; of the digital code values D&lt;n&gt; using the following Equation. 
         [0000]    
       
         
           
             
               Q 
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             = 
             
               
                 
                   
                     
                       Q 
                        
                       
                         ( 
                         
                           n 
                           - 
                           1 
                         
                         ) 
                       
                     
                     * 
                   
                    
                   
                     ( 
                     
                       n 
                       - 
                       1 
                     
                     ) 
                   
                 
                 + 
                 
                   D 
                    
                   
                     ( 
                     n 
                     ) 
                   
                 
               
               n 
             
           
         
       
     
         [0000]    wherein ‘n’ indicates the number of data outputted up to now. For example, when n=5, it is possible to calculate an average value Q&lt;5&gt; of five pieces of data. In case of the five pieces of data is inputted, an average value Q&lt;4&gt; up to four pieces of data may be multiplied by 4, a current value D&lt;5&gt; may be added to the multiplication resultant, and then the adding resultant may be divided by 5. 
         [0058]    Accordingly, using the above Equation, it is possible to calculate an average value Q&lt;n&gt; of data outputted up to now. 
         [0059]    The output section  175  may output the average value Q&lt;n&gt; from the average calculating part  174  to an output pad. 
         [0060]    The register  176  may store a target value T&lt;n&gt; for the optimization of voltage regulation. The target value T&lt;n&gt; for the optimization may be selected depending on the first mode or the second mode. In the first mode, the target value T&lt;n&gt; for the optimization may be a value obtainable when the output voltage VOUT may not pass through the undershoot detecting part  171 , such as, a value required for optimizing a DC characteristic of the output voltage VOUT. In the second mode, the target value T&lt;n&gt; for the optimization may be a value obtainable when the output voltage VOUT may pass through the undershoot detecting part  171 , such as, a peak voltage value required for optimizing an AC characteristic of the output voltage VOUT. 
         [0061]    The operation control part  177  may compare the average value Q&lt;n&gt; outputted from the average calculating part  174  with the target value T&lt;n&gt; stored in the register  176 , and output the first to third control signals SEL 1 &lt;0:N&gt; to SEL 3 &lt;0:N&gt;. The first control signals SEL 1 &lt;0:N&gt; may control the current of the bias current adjustment section  120 . The second control signals SEL 2 &lt;0:N&gt; may control the drivability of the pass device adjustment section  130 . The third control signals SEL 3 &lt;0:N&gt; may control the capacitance amount of the capacitor adjustment section  160 . The operation control part  177  may perform different operations according to the first mode and the second mode. 
         [0062]    Hereinafter, an operation of the voltage regulator according to an embodiment of the present invention will be described. 
         [0063]    In a first mode of operation, the mode selection part  172  may select the output voltage VOUT without passing through the undershoot detecting part  171  in response to the mode selection signal MODE_SEL. The analog-to-digital converter  173  may convert the output voltage VOUT outputted as an analog signal into digital code values. Then, the average calculating part  174  may calculate the average value Q&lt;n&gt; of the digital code values D&lt;n&gt; of the output voltage VOUT. The operation control part  177  may compare the target value T&lt;n&gt; stored in the register  176  with the average value Q&lt;n&gt; from the average calculating part  174  to generate the first to third control signals SEL 1 &lt;0:N&gt; to SEL 3 &lt;0:N&gt;. 
         [0064]    When the average value Q&lt;n&gt; is larger than the target value T&lt;n&gt;, for example, when the average value of the output voltage VOUT may be higher than the target value T&lt;n&gt;, since it may be determined that the supply ability of the voltage regulator is sufficient, it is possible to decrease the number of pass devices to be turned on by the pass device adjustment section  130  by adjusting the values of the second control signals SEL 2 &lt;0:N&gt;. Consequently, it is possible to lower the drivability of the voltage regulator. 
         [0065]    When the average value Q&lt;n&gt; is smaller than the target value T&lt;n&gt;, for example, when the average value of the output voltage VOUT may be lower than the target value T&lt;n&gt;, since it may be determined that the supply ability of the voltage regulator is not sufficient, it is possible to increase the number of pass devices to be turned on by the pass device adjustment section  130  by adjusting the values of the second control signals SEL 2 &lt;0:N&gt;. Consequently, it is possible to enhance the drivability of the voltage regulator. 
         [0066]    In the second mode, the mode selection part  172  may select an output voltage after having passed through the undershoot detecting part  171  in response to the mode selection signal MODE_SEL. The analog-to-digital converter  173  may convert the output voltage outputted as an analog signal including a peak voltage into digital code values. Then, the average calculating part  174  may calculate the average value Q&lt;n&gt; of the digital code values D&lt;n&gt;. The operation control part  177  may compare the target value T&lt;n&gt; stored in the register  176  with the average value Q&lt;n&gt; from the average calculating part  174  to generate the first to third control signals SEL 1 &lt;0:N&gt; to SEL 3 &lt;0:N&gt;. 
         [0067]    When the average value Q&lt;n&gt; is larger than the target value T&lt;n&gt;, for example, when a peak voltage value corresponding to an undershoot value of the output voltage VOUT may be higher than the target value T&lt;n&gt;, since it may be determined that a response time or a slew of the voltage regulator is sufficient, it is possible to decrease the amount of the bias current ISS flowing through the comparator  110  by adjusting the values of the first control signals SEL 1 &lt;0:N&gt; and to decrease an output capacitance by adjusting the values of the third control signals SEL 3 &lt;0:N&gt;. 
         [0068]    However, when the average value Q&lt;n&gt; is smaller than the target value T&lt;n&gt;, for example, when the peak voltage value of the output voltage VOUT may be lower than the target value T&lt;n&gt;, since it may be determined that the response time or the slew of the voltage regulator is not sufficient, it is possible to increase the amount of the bias current ISS flowing through the comparator  110  by adjusting the values of the first control signals SEL 1 &lt;0:N&gt; and to increase the output capacitance by adjusting the values of the third control signals SEL 3 &lt;0:N&gt;. 
         [0069]    As described above, the voltage regulator according to an embodiment of the present invention may perform a self-training operation, thereby detecting the DC and AC characteristics of the output voltage VOUT in the circuit by itself and thus adjusting and optimizing the bias current amount, the drivability, and the capacitance. 
         [0070]    Referring to  FIGS. 1 and 2 , a bias current adjustment section  120 , according to an embodiment of the present invention, may include first to eighth NMOS transistors N 1  to N 8 . A source of the first NMOS transistor N 1  is coupled to a bias current source ISS and a drain of the first NMOS transistor N 1  is coupled to a source of the second NMOS transistor N 2 . Gates of the first, third, fifth, and seventh NMOS transistors are respectively coupled to the bias current source ISS. Sources of the third, fifth, and seventh NMOS transistors N 3 , N 5 , and N 7  are coupled to a coupling node VCOMM of the comparator  110 . Drains of the second, fourth, sixth, and eighth NMOS transistors N 2 , N 4 , N 6 , and N 8  are coupled to a ground voltage terminal. A source of the fourth NMOS transistor N 4  is coupled to a drain of the third NMOS transistor N 3 . A source of the sixth NMOS transistor N 6  is coupled to a drain of the fifth NMOS transistor N 5 . A source of the eighth NMOS transistor N 8  is coupled to a drain of the seventh NMOS transistor N 7 . Furthermore, the second NMOS transistor N 2  may receive a fixed signal Tie having a value of ‘H’ through its gate. The fourth, sixth, and eighth NMOS transistors N 4 , N 6 , and N 8  may respectively receive the first control signals SEL 1 &lt;0:N&gt; through their gates. The first control signals SEL 1 &lt;0:N&gt; may be generated by the optimization control unit  10   b  depending on the first mode or the second mode, and may adjust the current amount of the bias current ISS flowing through the comparator  110  by driving a larger number of transistors or a smaller number of transistors. 
         [0071]    For example, in the second mode, when the average value Q&lt;n&gt; outputted from the average calculating part  174  is higher or lower than the target value T&lt;n&gt; for the optimization, since it may be determined as to whether the response time of the voltage regulator is sufficient or not, the number of the first control signals SEL 1 &lt;0:N&gt; may be adjusted to control the activation of transistors to be driven in response to the first control signals SEL 1 &lt;0:N&gt;, so that the current amount of the bias current flowing through the comparator  110  may be decreased or increased. 
         [0072]    Referring to  FIGS. 1 and 3 , a pass device adjustment section  130 , according to an embodiment of the present invention, may include the pass device selection part  131  and the pass device array part  132 . 
         [0073]    The pass device selection part  131  may include first to third transfer elements T 1 _ 1  to T 1 _ 3 . The pass device selection part  131  may transfer the driving signal VDRV from the comparator  110  to the pass device array part  132 , in response to the respective second control signals SEL 2 &lt;0:N&gt;. 
         [0074]    The pass device array part  132  may include first to third PMOS transistors P 1  to P 3 . The first to third PMOS transistors P 1  to P 3  may be coupled between an external power supply voltage VIN and an output terminal. The first to third PMOC transistors P 1  to P 3  may output the external power supply voltage VIN as the output voltage VOUT in response to the driving signal VDRV received from the first to third transfer elements T 1 _ 1  to T 1 _ 3  through their gates. 
         [0075]    The second control signals SEL 2 &lt;0:N&gt; may be generated by the optimization control unit  10   b  depending upon whether the first or the second mode of operation is employed, and may internally self-adjust the drivability of the voltage regulator by driving a larger or smaller number of PMOS transistors receiving the external power supply voltage VIN. 
         [0076]    For example, in the first mode, when the average value Q&lt;n&gt; outputted from the average calculating part  174  is higher or lower than the target value T&lt;n&gt; for the optimization, since it may be determined as to whether the drivability of the voltage regulator is sufficient or not, the number of the second control signals SEL 2 &lt;0:N&gt; may be adjusted as may be needed to decrease or increase the number of PMOS transistors to be turned-on in response to the second control signals SEL 2 &lt;0:N&gt;. For example, it is possible to increase or decrease a necessary drivability by comparing a current drivability with the drivability for the optimization. 
         [0077]    Referring now to  FIGS. 1 and 4 , a capacitor adjustment section  160 , according to an embodiment of the present invention, may include a capacitor transfer control part  161  and a capacitor array part  162 . 
         [0078]    The capacitor transfer control part  161  may include first to third transfer elements T 2 _ 1  to T 2 _ 3 . The capacitor transfer control part  161  may transfer the output voltage VOUT to the capacitor array part  162  in response to the respective third control signals SEL 3 &lt;0:N&gt;. 
         [0079]    The capacitor array part  162  may include first to third capacitors C 1  to C 3 . Each of the first to third capacitors C 1  to C 3  may substantially maintain the output voltage VOUT to be constant. The first to third capacitors C 1  to C 3  may be coupled to the output terminal of the voltage regulator depending on a transfer element activated among the first to third transfer elements T 2 _ 1  to T 2 _ 3  in response to the third control signals SEL 3 &lt;0:N&gt;, and, thus, the activated capacitor may constantly maintain the output voltage VOUT. 
         [0080]    The third control signals SEL 3 &lt;0:N&gt; may be generated by the optimization control unit  10   b  depending on whether the first mode or the second mode is employed, and may adjust the capacitance of the output voltage VOUT by activating a larger or smaller number of capacitors coupled to the output terminal of the voltage regulator in order to substantially maintain the output voltage VOUT to be constant. 
         [0081]    For example, in the second mode, when the average value Q&lt;n&gt; outputted from the average calculating part  174  is higher or lower than the target value T&lt;n&gt; for the optimization, since it may be determined as to whether the slew of the voltage regulator is sufficient or not, the number of the third control signals SEL 3 &lt;0:N&gt; may be adjusted to control the first to third transfer elements T 2 _ 1  to T 2 _ 3  to be activated in response to the third control signals SEL 3 &lt;0:N&gt;. Thus, it is possible to adjust the capacitance of the output voltage VOUT by decreasing or increasing the number of capacitors operating from coupling with the output terminal. 
         [0082]    Referring to  FIGS. 1 and 5 , an undershoot detecting part  171 , according to an embodiment of the present invention, may include a first amplifier  171 _ 1 , a diode D 1 , a capacitor C 4 , and a second amplifier  171 _ 2 . 
         [0083]    The first amplifier  171 _ 1  may be an operational trans-conductance amplifier (OTA). The first amplifier  171 _ 1  may receive the output voltage VOUT and a peak voltage VPEAK fed back from an output of the undershoot detecting part  171 . The first amplifier  171 _ 1  may sense the output voltage VOUT for outputting the sensed output voltage. The peak voltage VPEAK may be the lowest voltage among voltages previously outputted from the undershoot detecting part  171 . When the output voltage VOUT is reduced, allowing the voltage level of an output signal of the first amplifier  171 _ 1  to be lowered, the capacitor C 4  may be discharged via the diode D 1 . 
         [0084]    Then, the second amplifier  171 _ 2  may buffer and output the lowered voltage. The lowered voltage from the second amplifier  171 _ 2  for example, the peak voltage VPEAK may be inputted to the second amplifier  171 _ 2  again. 
         [0085]    In the case in which the output voltage VOUT is continuously reduced, only when a voltage value having a level lower than that of the current peak voltage VPEAK value is inputted as the output voltage VOUT, the output voltage of the first amplifier  171 _ 1  may be lowered. Similarly to the previous operation, the capacitor C 4  may be discharged via the diode. 
         [0086]    Since the discharge operation may be performed only when the output voltage VOUT newly inputted through such an operation is lower than the peak voltage VPEAK which is the previously lowest voltage level, the peak voltage VPEAK may be the lowest voltage level of the output voltage VOUT. 
         [0087]    However, when the voltage level of the output voltage VOUT is increased, since the diode D 1  may perform a rectifying action, it is not possible to discharge or charge the capacitor C 4 . Accordingly, even though the voltage level of the output voltage VOUT is increased, the undershoot detecting part  171  may substantially maintain the output voltage VOUT having a low previously inputted level. 
         [0088]    Referring to  FIGS. 1 and 6 , a mode selection part  172 , according to an embodiment of the present invention, may selectively output a signal ‘A’ indicating the output voltage VOUT not passing through the undershoot detecting part  171  and a signal ‘B’ indicating the output voltage passing through the undershoot detecting part  171  in response to the mode selection signal MODE_SEL. 
         [0089]    The mode selection part  172  may selectively output the signal ‘A’ in the first mode and the signal ‘B’ in the second mode. The signal ‘B’ may be obtained by outputting the peak voltage of the output voltage VOUT obtained by the undershoot detecting part  171 . For example, the signal ‘B’ may be kept unchanged after the lowest voltage of the signal ‘A’, indicating the output voltage VOUT not passing through the undershoot detecting part  171 , is outputted. 
         [0090]    Referring to  FIG. 1 ,  FIG. 7 , an analog-to-digital converter  173 , according to an embodiment of the present invention, may convert the analog signals ‘A’ or ‘B’ outputted from the mode selection part  172 , into digital codes for outputting the digital codes. The analog-to-digital converter  173  may convert the signal ‘A’ into the digital codes for outputting the digital codes in the first mode. The analog-to-digital converter  173  may convert the signal ‘B’ into the digital codes for outputting the digital codes in the second mode. 
         [0091]    Referring to  FIG. 1  and  FIG. 8 , an average calculating part  174 , according to an embodiment of the present invention, may calculate an average value of the digital code values D&lt;n&gt; of the signals ‘A’ or ‘B’ indicating the output signal of the analog-to-digital converter  173  for outputting the average value. The average calculating part  174  may output the average value of the signal ‘A’ in the first mode. The average calculating part  174  may output the average value of the signal ‘B’ in the second mode. 
         [0092]    The average calculating part  174  may calculate the average value of the signals ‘A’ or ‘B’ using the following Equation. 
         [0000]    
       
         
           
             
               Q 
                
               
                 ( 
                 n 
                 ) 
               
             
             = 
             
               
                 
                   
                     
                       Q 
                        
                       
                         ( 
                         
                           n 
                           - 
                           1 
                         
                         ) 
                       
                     
                     * 
                   
                    
                   
                     ( 
                     
                       n 
                       - 
                       1 
                     
                     ) 
                   
                 
                 + 
                 
                   D 
                    
                   
                     ( 
                     n 
                     ) 
                   
                 
               
               n 
             
           
         
       
     
         [0093]    Wherein ‘n’ indicates the number of data outputted up to now. For example, when n=5, it is possible to calculate an average value Q&lt;5&gt; of five pieces of data. In case of the five pieces of data is inputted, an average value Q&lt;4&gt; up to four pieces of data may be multiplied by 4, a current value D&lt;5&gt; may be added to the multiplication resultant, and then the adding resultant may be divided by 5. Accordingly, using the above Equation, it is possible to calculate an average value Q&lt;n&gt; of data outputted up to now. 
         [0094]    Referring to  FIG. 9 , a voltage regulator, according to another embodiment of the present invention, may include a voltage regulation unit  90   a  and an optimization control unit  90   b . The voltage regulation unit  90   a  may include a comparator  910 , a bias current adjustment section  920 , a pass device adjustment section  930 , a frequency compensation section  940 , a voltage division section  950 , and a capacitor adjustment section  960 . 
         [0095]    The comparator  910  may compare a reference voltage VREF with a feedback voltage VFB for outputting a driving signal VDRV, and operate on the basis of a bias current ISS. 
         [0096]    The bias current adjustment section  920  may adjust a current amount of the bias current ISS, which is supplied to the comparator  110 , in response to first control signals SEL 1 &lt;0:N&gt;. The first control signals SEL 1 &lt;0:N&gt; may be received from the optimization control unit  90   b  which will be described later. Since a configuration and an operation of the bias current adjustment section  920  are substantially the same to those of the bias current adjustment section  120  of  FIG. 1 , a detailed description thereof will now be omitted. 
         [0097]    The pass device adjustment section  930  may receive the driving signal VDRV from the comparator  910 , output an external power supply voltage VIN to an output terminal as an output voltage VOUT, and adjust drivability in response to second control signals SEL 2 &lt;0:N&gt;. The pass device adjustment section  930  may include a pass device selection part  931  and a pass device array part  932 . 
         [0098]    The pass device selection part  931  may control one or more of a plurality of pass devices to be driven in response to the second control signals SEL 2 &lt;0:N&gt;. The second control signals SEL 2 &lt;0:N&gt; may be received from the optimization control unit  90   b  which will be described later. 
         [0099]    The pass device array part  932  may drive a selected pass device in response to an output signal of the pass device selection part  931 . 
         [0100]    Furthermore, since a configuration and an operation of the pass device adjustment section  930  are substantially the same to those of the pass device adjustment section  130  of  FIG. 1 , a detailed description thereof will be omitted. 
         [0101]    The frequency compensation section  940  may ensure a phase margin for a frequency stability of a voltage regulation operation. The frequency compensation section  940  may include a miller capacitor (not illustrated) between the comparator  910  and an output terminal for a connection to compensate for a frequency, thereby improving the phase margin 
         [0102]    The voltage division section  950  may divide the output voltage VOUT and output the divided voltage to an input terminal of the comparator  910  as the feedback voltage VFB. Since a configuration and an operation of the voltage division section  950  are substantially the same to those of the voltage division section  150  of  FIG. 1 , a detailed description thereof will be omitted. 
         [0103]    The capacitor adjustment section  960  may adjust an capacitance of the output voltage VOUT in response to third control signals SEL 3 &lt;0:N&gt;. The third control signals SEL 3 &lt;0:N&gt; may be received from the optimization control unit  90   b  which will be described later. Since a configuration and an operation of the capacitor adjustment section  960  are substantially the same to those of the capacitor adjustment section  160  of  FIG. 1 , a detailed description thereof will be omitted. 
         [0104]    The optimization control unit  90   b  may evaluate a load regulation characteristic or transient regulation characteristic of the output voltage VOUT in response to a training enable signal EN_TRAINING, thereby optimizing the voltage regulation operation. The load regulation characteristic may indicate drivability, for example, DC characteristic of the output voltage VOUT. The transient regulation characteristic may indicate a voltage drop temporarily occurring, for example, AC characteristic of the output voltage VOUT. 
         [0105]    The optimization control unit  90   b  may include an average detecting section  91  and a control signal generation section  92 . The average detecting section  91  may include an undershoot detecting part  971 , a mode selection part  972 , a counter  973 , a gain integrator  974 , and an analog-to-digital converter  975 . The control signal generation section  92  may include a register  977  and an operation control part  978 . The optimization control unit  90   b  may further include an output section  976 . 
         [0106]    The undershoot detecting part  971  may detect an undershoot indicating a phenomenon that the output voltage VOUT temporarily drops. For example, the undershoot detecting part  971  may detect a peak voltage having the lowest voltage level when the output voltage VOUT drops. Since a configuration and an operation of the undershoot detecting part  971  are substantially the same to those of the undershoot detecting part  171  of  FIG. 1 , a detailed description thereof will be omitted. 
         [0107]    The mode selection part  972  may selectively output an output voltage passing through the undershoot detecting part  971  or the output voltage VOUT without passing through the undershoot detecting part  971 , in response to a mode selection signal MODE_SEL. The mode selection signal MODE_SEL may be inputted from an external device and may be arbitrarily controlled by the external device according to whether to optimize the load regulation characteristic of the output voltage VOUT, such as, the DC characteristic, or the transient regulation characteristic of the output voltage VOUT, such as, the AC characteristic. 
         [0108]    The gain integrator  974  may integrate an output voltage signal D&lt;t&gt; outputted from the mode selection part  972  on the basis of an output value of the counter  973  for outputting the integrated value. The gain integrator  974  may integrate the output voltage signal D&lt;t&gt;, which is an analog signal, using the following Equation. 
         [0000]    
       
         
           
             
               Q 
                
               
                 ( 
                 t 
                 ) 
               
             
             = 
             
               
                 
                   
                     Q 
                      
                     
                       ( 
                       
                         t 
                         - 
                         1 
                       
                       ) 
                     
                   
                   * 
                 
                  
                 
                   
                     
                       n 
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                         t 
                         ) 
                       
                     
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                     1 
                   
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                       t 
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                   N 
                 
               
             
           
         
       
     
         [0109]    The gain integrator  974  changes a gain from 1/N to N/N using the above Equation on the basis of the output value of the counter  973 . 
         [0110]    The counter  973  and the gain integrator  974  may perform operations substantially equal to those of the average calculating part  174  illustrated in  FIG. 1 . There is a difference in that the gain integrator  974  may calculate an average value Q&lt;t&gt; by integrating the output voltage signal D&lt;t&gt;, which is an analog signal, whereas the average calculating part  174  may calculate an average value of signals converted into digital code values. 
         [0111]    The analog-to-digital converter  975  may convert the average value Q&lt;t&gt;, which is the analog signal outputted from the gain integrator  974 , into a digital code value. 
         [0112]    The output section  976  may output the digital code value from the analog-to-digital converter  975 , to an output pad. 
         [0113]    The register  977  may store a target value T&lt;n&gt; for the optimization of the voltage regulation operation. The target value T&lt;n&gt; for the optimization may be selected depending on the first mode or the second mode. In the first mode, the target value T&lt;n&gt; for the optimization may be a value obtainable when the output voltage VOUT does not pass through the undershoot detecting part  971 , such as, a value required for optimizing the DC characteristic of the output voltage VOUT. In the second mode, the target value T&lt;n&gt; for the optimization may be a value obtainable when the output voltage VOUT passes through the undershoot detecting part  971 , such as, a peak voltage value required for optimizing the AC characteristic of the output voltage VOUT. 
         [0114]    The operation control part  978  may compare the signal outputted from the analog-to-digital converter  975  with the target value T&lt;n&gt; stored in the register  977 , and output the first to third control signals SEL 1 &lt;0:N&gt; to SEL 3 &lt;0:N&gt;. The first control signals SEL 1 &lt;0:N&gt; may control the bias current ISS amount of the bias current adjustment section  920 . The second control signals SEL 2 &lt;0:N&gt; may control the drivability of the pass device adjustment section  930 . The third control signals SEL 3 &lt;0:N&gt; may control the capacitance amount of the output voltage of the capacitor adjustment section  960 . Since a configuration and an operation of the operation control part  978  are substantially the same to those of the operation control part  177  of  FIG. 1 , a detailed description thereof will be omitted. 
         [0115]    Hereinafter, an operation of the voltage regulator according to another embodiment of the present invention will be described. 
         [0116]    In the first mode, the mode selection part  972  may select the output voltage VOUT not passing through the undershoot detecting part  971 . The gain integrator may calculate an average value of the output voltage VOUT. Since the average value is an analog signal, it may be converted into a digital value by the analog-to-digital converter  975 . Then, the operation control part  978  may compare the target value T&lt;n&gt; for the optimization stored in the register  977  with the average value of the output voltage VOUT, which has been converted into the digital value by the analog-to-digital converter  975  to generate the first to third control signals SEL 1 &lt;0:N&gt; to SEL 3 &lt;0:N&gt;. 
         [0117]    When the average value is larger than the target value T&lt;n&gt;, since it may be determined that the supply ability of the voltage regulator is sufficient, it is possible to decrease the number of activations of the second control signals SEL 2 &lt;0:N&gt; for adjusting the number of pass devices of the pass device adjustment section  930 . Consequently, it is possible to lower the drivability. 
         [0118]    However, when the average value is smaller than the target value T&lt;n&gt;, since it may be determined that the supply ability, for example, the drivability, of the voltage regulator is not sufficient, it is possible to increase the number of activations of the second control signals SEL 2 &lt;0:N&gt;. Consequently, it is possible to enhance the drivability of the voltage regulator. 
         [0119]    In the second mode, the mode selection part  972  may select an output voltage passing through the undershoot detecting part  971 . The gain integrator  974  may calculate an average value of the output voltage including a peak voltage. Since the average value is an analog signal, it may be converted into a digital value by the analog-to-digital converter  975 . Then, the operation control part  978  may compare the target value T&lt;n&gt; for the optimization stored in the register  977  with the average value converted into the digital value by the analog-to-digital converter  975  to generate the first to third control signals SEL 1 &lt;0:N&gt; to SEL 3 &lt;0:N&gt;. 
         [0120]    When the average value is larger than the target value T&lt;n&gt;, for example, when a peak voltage value corresponding to an undershoot value of the output voltage VOUT may be higher than the target value T&lt;n&gt;, since it may be determined that a response time or a slew of the voltage regulator is sufficient, it is possible to decrease the amount of activations of the first control signals SEL 1 &lt;0:N&gt; for adjusting the bias current ISS amount of the bias current adjustment section  920  and the amount of activations of the third control signals SEL 3 &lt;0:N&gt; for adjusting the capacitance of the capacitor adjustment section  960 . Consequently, it is possible to decrease the bias current amount and the capacitance of the output voltage VOUT. 
         [0121]    However, when the average value is smaller than the target value T&lt;n&gt;, for example, when the peak voltage value of the output voltage VOUT may be lower than the target value T&lt;n&gt;, since it may be determined that the response time or the slew of the voltage regulator is not sufficient, it is possible to increase the amount of activations of the first control signals SEL 1 &lt;0:N&gt; and the amount of activations of the third control signals SEL 3 &lt;0:N&gt;, so that the bias current ISS amount and the capacitance of the output voltage VOUT may be increased. 
         [0122]    As described above, the voltage regulator of  FIG. 9  may perform a self-training operation, thereby detecting the DC and AC characteristics of the output voltage VOUT in the circuit by itself and thus adjusting and optimizing the bias current amount, the drivability, and the capacitance. 
         [0123]      FIG. 10  is a graph illustrating an output signal of a gain integrator  974 , of the embodiment shown in  FIG. 9 . Referring to  FIGS. 9 and 10 , the gain integrator  974  may integrate a signal ‘A’ indicating the output voltage including a peak voltage inputted from the mode selection part  972  and passing through the undershoot detecting part  971 , or a signal ‘B’ indicating the output voltage VOUT not passing through the undershoot detecting part  971 , in response to the counter value n&lt;t&gt;. The gain integrator  974  may output an average value of each signal. 
         [0124]    The gain integrator  974  may integrate the signals ‘A’ or ‘B’ using the following equation. 
         [0000]    
       
         
           
             
               Q 
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                 ( 
                 t 
                 ) 
               
             
             = 
             
               
                 
                   
                     Q 
                      
                     
                       ( 
                       
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                         1 
                       
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                   * 
                 
                  
                 
                   
                     
                       n 
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                         ( 
                         t 
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                       ( 
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         [0125]    The gain integrator  974  may change a gain from 1/N to N/N using the above equation on the basis of the output value n&lt;t&gt; of the counter  973 , and calculate the average value Q&lt;t&gt; of data outputted up to now. 
         [0126]      FIG. 11  is a graph illustrating an output signal of an analog-to-digital converter  975  of  FIG. 9 . 
         [0127]    Referring to  FIGS. 9 and 11 , the analog-to-digital converter  975  may convert the analog signals ‘A’ or ‘B’, which are integrated by and outputted from the gain integrator  974 , into digital codes. The ADC converter  975  may convert the signal ‘A’ into digital codes for outputting the digital codes in the first mode. The ADC converter  975  may convert the signal ‘B’ into the digital codes for outputting the digital codes in the second mode. 
         [0128]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art to which this invention pertains after having read the present disclosure that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.