Abstract:
Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell.

Description:
[0001]    This application claims the benefit of priority to U.S. Provisional Patent Application No. 61/473,921 titled “Self-Contacting Bit Line to MRAM cell” filed Apr. 11 2011. 
     
    
     FIELD 
       [0002]    Embodiments of the invention relate to MRAM (Magnetic Random Access Memory) semiconductor devices. 
       BACKGROUND 
       [0003]    MRAM (Magnetic Random Access Memory) cells may be fabricated during BEOL (Back End Of Line) after a MOS FET device process. The minimum feature size of an MRAM cell is often 1.5× larger than that of FEOL (Front End of Line). It is therefore difficult to shrink memory size compared with other FEOL based memories. 
       SUMMARY 
       [0004]    Embodiments of the invention disclose a plurality of self-aligned structures that save the overlay margin. 
         [0005]    The first embodiment discloses a MTJ cell wherein the MTJ stack is directly coupled to the upper metal without the requirement of a via. Sidewalls of individual MTJ elements are protected with dielectric film spacer to prevent from PIN-Switch layer shorting 10 through the tunnel oxide layer. The top layer of MTJ is exposed to upper metal. Overlay margin in this embodiment is required only for upper metal coverage over MTJ. The upper metal width comes to f+2∂, saving 2∂ compared to previous art. Putting MTJ feature size equal to that of FEOL, the memory size becomes competitive to FEOL based memory. 
         [0006]    The second embodiment comprises an electrically conductive material such as Titanium Nitride, which is used as a hard mask. The hard mask is for MTJ stack etch and remains on top of MTJ pillar after the etching. Inter layer oxide is deposited over the MTJ pillar. The hard mask remained on MTJ is exposed with CMP. Metal like as Al/Cu is deposited and patterned with conventional lithography and Reactive Ion Etching. The same reduction in memory cell size as the first embodiment is provided by the second embodiment. 
         [0007]    The third embodiment discloses a self-aligned via which replaces the hard mask. Silicon nitride is used as hard mask as an example. The hard mask is for MTJ stack etch and remains on top of MTJ pillar after the etching. Inter layer oxide is deposited over the MTJ pillar. The hard mask remained on MTJ is exposed with CMP or Dual Damascene oxide trench etch. The exposed hard mask is removed by hot phosphoric acid followed by upper metal deposition. The same squeezing memory cell size as the first embodiment is expected on the structure. 
         [0008]    The fourth embodiment is of self-aligned etching. MTJ is to be etched twice along word line direction first and bit line direction 2 nd . Putting dielectric film, nitride preferred, spacer on MTJ pillar to prevent PIN layer—Fix layer short. Oxide is deposited and planerized by CMP. The oxide is recessed until MTJ appeared. Upper metal layer is deposited patterned. MTJ and bottom read lead is etched with the same mask as upper metal. The upper metal is wrapping around MTJ pillar. It works to help induce magnetic field. The upper metal width can be same size as MTJ pillar. It saves 4∂ compared with prior arts. 
         [0009]    The fifth embodiment is also of self-aligned patterning. It is different in read electrode connecting to top of MTJ instead of bottom of the pillar. MTJ is connected to lower metal (write word line). Top metal is electrically isolated from MTJ with a thin dielectric film. The upper metal also wraps around MTJ. It enhances magnetic field induction for switching. It saves cell footprint also by 4∂. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    While the appended claims set forth the features of the present invention with particularity, the invention, together with its objects and advantages, will be more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, wherein: 
           [0011]    FIG. A illustrates a cross-sectional view of prior arts. 
           [0012]    FIG. B illustrates a top view of prior arts. 
           [0013]      FIG. 1A  illustrates a cross-sectional view of 1 st  preferred embodiment 
           [0014]      FIG. 1B  illustrates a top view of 1 st  preferred embodiment. 
           [0015]      FIG. 1.1  to  FIG. 1.8  illustrate cross sectional views along bit line direction at individual process steps to the 1 st  embodiment 
           [0016]      FIG. 1.3   s  to  FIG. 1.8   s  illustrate cross sectional views along other direction of  FIG. 1.3   s  to  FIG. 1.8   s.    
           [0017]      FIG. 2A  illustrates a cross-sectional view of 2 nd  preferred embodiment. 
           [0018]      FIG. 2B  illustrates a top view 2″ d  preferred embodiment. 
           [0019]      FIG. 2.1  to  FIG. 2.6  illustrate cross sectional views along bit line direction at individual process steps to the 2 nd  embodiment. 
           [0020]      FIG. 2.3   s  to  FIG. 2.6   s  illustrate cross sectional views along other direction of  FIG. 2.3  to  FIG. 2.6 . 
           [0021]      FIG. 3A  illustrates a cross-sectional view of 3 rd  embodiment. 
           [0022]      FIG. 3B  illustrates a top view 3 rd  embodiment. 
           [0023]      FIG. 3.1  to  FIG. 3.8  illustrate cross sectional views along bit line direction at individual process steps to the 3 rd  embodiment. 
           [0024]      FIG. 3.5   s  to  FIG. 3.8   s  illustrate cross sectional views along other direction of  FIG. 3.5  to  FIG. 3.8 . 
           [0025]      FIG. 4A  illustrates a cross-sectional view of 4 th  embodiment. 
           [0026]      FIG. 4B  illustrates a top view 4 th  embodiment. 
           [0027]      FIG. 4.1  to  FIG. 4.8  illustrate cross sectional views along bit line direction at individual process steps to the 4 th  embodiment. 
           [0028]      FIG. 4.3   s  to  FIG. 4.8   s  illustrate cross sectional views along other direction of  FIG. 4.3  to  FIG. 4.8 . 
           [0029]      FIG. 5A  illustrates a cross-sectional view of 5 th  preferred embodiment. 
           [0030]      FIG. 5B  illustrates a top view 5 th  embodiment. 
           [0031]      FIG. 5.1  to  FIG. 5.5  illustrate cross sectional views along bit line direction at individual process steps to the 5 th  embodiment. 
           [0032]      FIG. 5.2   s  to  FIG. 5.5   s  illustrate cross sectional views along other direction of  FIG. 5.2  to  FIG. 5.5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form only in order to avoid obscuring the invention. 
         [0034]    Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearance of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments. 
         [0035]    Moreover, although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to said details are within the scope of the present invention. Similarly, although many of the features of the present invention are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the invention is set forth without any loss of generality to, and without imposing limitations upon, the invention. 
         [0036]    Prior Art FIG. A shows a cross-sectional view through a prior art MRAM cell, whereas Prior Art FIG. B shows a plan view of the MRAM cell. As can be seen the MRAM cell includes a MTJ (Magnetic Tunnel Junction) as a memory element. The MTJ is connected to upper and lower metals through via holes where overlay margin ∂ is required on the both edges of via hole landing area. The MTJ cell is designed to be bigger than the upper through hole to upper metal by 2∂. Since the upper metal should cover the MTJ, the upper metal becomes bigger than the MTJ by 2∂. The upper metal width consequently becomes 4∂ bigger than a feature size f of the via hole. Overlay margin is estimated to be 20% to 30% of the minimum 1−b. As will be seen, the upper metal  113  is directly connected feature size. The metal width would be twice bigger than minimum feature size. 
         [0037]      FIG. 1A  shows a cross sectional view of a first embodiment of an MRAM cell. A top view of the first embodiment is shown in  FIG. 1B . As will be seen, the upper metal  113  is directly connected to the top of MTJ. Overlay margin of MTJ to via is not necessary so that upper metal width becomes f+2∂ considering overlay margin of upper metal to MTJ. Thus, the first embodiments saves 2∂ compared to conventional structure showed in Prior Art FIG. A and Prior Art FIG. B. 
         [0038]    As shown in  FIG. 1.1 , a lower metal as write word line  101  and landing pad  102  to read device are patterned after the FEOL process is completed. The surface over write word line is planerized with CMP. Bottom read lead  104 , MTJ Pin layer  105 , tunnel oxide  106 , MTJ fixed layer  107  and hard mask layer are subsequently deposited as shown in  FIG. 1.2 . Patterning photo resist  108  with MTJ pillar mask in  FIGS. 1.3  and  1 . 3   s,  MTJ stack ( 107 ,  106 ,  105 ) is etched with ion milling or reactive ion etch with end point at read lead metal  104  surface. Read lead metal is patterned with photo resist mask  109  and etched also with ion milling or reactive ion etch as shown in  FIGS. 1.4  and  1 . 4   s.  A dielectric layer having enough etch selectivity to oxide such as nitride is deposited and vertically etched as shown in  FIGS. 1.5  and  1 . 5   s  to put dielectric spacer  110  on MTJ sidewall to protect the junction  106 . Oxide  111  as an inter dielectric layer is deposited and planerized as shown in  FIGS. 1.6  and  1 . 6   s.  Trench line  112  is formed in oxide  111  using conventional damascene process. The trench etch goes until top of MTJ surface completely appears as shown in  FIGS. 1.7  and  1 . 7   s.  Seed layer is deposited and copper  112  is plugged in trench with electro plating. Conventional copper CMP is used to remove excess copper out side of the trench as shown in  FIGS. 1.8  and  1 . 8   s.    
         [0039]    A cross sectional view of the 2 nd  embodiment is shown in  FIG. 2A . Top view is in  FIG. 2B . The MTJ pillar is coupled to the upper metal  213  without the need of a via. Overlay margin of MTJ to via is thus not necessary so that upper metal width becomes f+2∂ considering overlay margin of upper metal to MTJ as discussed in the first embodiment. This embodiment saves 2∂ compared to conventional structure shown in Prior Art FIG. A and FIG. B. 
         [0040]    As shown in  FIG. 2.1 , lower metal as write word line  201  and landing pad  202  to read device are patterned after FEOL process is completed. The surface over write word line is planerized with CMP. Bottom read lead  204 , MTJ Pin layer  205 , tunnel oxide  206 , MTJ fixed layer  207  and hard mask layer  208  consisting of oxide and Titanium nitride are subsequently deposited as shown in  FIG. 2.2 . Titanium Nitride layer and oxide layer  208  are patterned using conventional lithography and mask etch as shown in  FIGS. 2.3  and  2 . 3   s.  Vertical ion etching with Ion milling or reactive ion allows to transfer the hard mask patter into MTJ stack as in  FIGS. 2.4  and  2 . 4   s,  with end point at read lead metal  204  surface, followed by read lead metal patterning similar to the first embodiment. Oxide  210  as an inter dielectric layer is deposited as shown in  FIGS. 2.5  and  2 . 5 . s.  CMP is allowed until Titanium nitride appears on surface as shown in  FIGS. 2.6  and  2 . 6   s,  followed by conventional metal dry etch process. 
         [0041]    A cross-sectional view of the 3 rd  embodiment is shown in  FIG. 3A . A top view of the 3 rd  embodiment is shown in  FIG. 3B . A self-aligned via connects the MTJ pillar/stack to the upper metal. Overlay margin of MTJ to via is not necessary so that upper metal width becomes f+2∂ considering overlay margin of upper metal to MTJ as discussed in the first embodiment. It save 2∂ compared to conventional structure showed in Prior Art FIG. A. and FIG. B. 
         [0042]    As shown in  FIG. 3.1 , lower metal as write word line  301  and landing pad  302  to read device are patterned after FEOL process is completed. The surface over write word line is planerized with CMP. Bottom read lead  304 , MTJ Pin layer  305 , tunnel oxide  306 , MTJ fixed layer  307  and hard mask layer consisting of bottom oxide  308  and nitride  309  are subsequently deposited as shown in  FIG. 3.2 . Nitride layer and oxide layer are patterned using conventional lithography and mask etch as shown in  FIG. 3.3 . Vertical ion etching with Ion milling or reactive ion etch allows to transfer the hard mask patter into MTJ stack as in  FIG. 3.4 , with end point at read lead metal  304  surface, followed by read lead metal patterning similar to the first embodiment. Oxide  310  as an inter dielectric layer is deposited and planerized as shown in  FIGS. 3.5  and  3 . 5   s.  Trench line  311  is formed in oxide  310  using conventional damascene process. The trench etch goes until top of hard mask nitride surface completely appears as shown in  FIGS. 3.6  and  3 . 6   s.  Exposed nitride  309  is removed with hot phosphoric acid as shown in  FIGS. 3.7  and  3 . 7   s.  The self aligned via structure  312  delivered. Adding oxide etch, the oxide  308  over MTJ is etched and MTJ surface appears. Seed layer is deposited and copper  313  is plugged in trench with electro plating. Conventional copper CMP remove excess copper out side of the trench as shown in  FIGS. 3.8  and  3 . 8   s.    
         [0043]    A cross-sectional view of the 4 th  embodiment is shown in  FIG. 4A . A top view of the 4 th  embodiment is shown in  FIG. 4B . MTJ is patterned twice. Firstly along the word line direction and secondly along the bit line direction. At 2 nd  patterning, upper metal layer, MTJ and bottom read lead are patterned with one mask. No overlay margin is required so that upper metal width becomes same feature size as MTJ. This embodiment saves 4∂ compared to conventional structure showed in Prior Art FIG. A and FIG. B. The structure has other benefit than cell size. The upper metal wraps around the MTJ. The current flowing the metal induces stronger magnetic field than straight metal line. It works better to switch the pin layer direction. 
         [0044]    As shown in  FIG. 4.1 , lower metal as write word line  401  and landing pad  402  to read device are patterned after FEOL process is completed. The surface over write word line is planerized with CMP. Bottom read lead  404 , MTJ Pin layer  405 , tunnel oxide  406 , MTJ fixed layer  407  and hard mask layer are subsequently deposited as shown in  FIG. 4.2 . With the same process step as previous embodiments, MTJ stack  408  is patterned as a line along word line direction as shown in  FIGS. 4.3  and  FIG. 4.3   s.  Nitride spacer  409  is placed on side wall of MTJ line as shown in  FIGS. 4.4  and  4 . 4   s.  Oxide  410  is deposited and planerized as shown in  FIGS. 4.5  and  4 . 5   s.  The planerized oxide is recessed with vertical ion etching until top of MTJ line appears enough as shown in  FIGS. 4.6  and  4 . 6   s.  Remained oxide  411  in  FIG. 4.6  is to insulate upper metal from bottom read lead metal. Upper metal  412  like as aluminum/Cu alloy is deposited as shown in  FIGS. 4.7  and  4 . 7   s.  Patterning photoresist, the upper metal is etched with conventional metal etching process by reaching to insulation oxide  411 . Subsequent Ion milling etches oxide, MTJ and bottom read lead metal to get self-aligned structure  413  as shown in  FIGS. 4.8  and  4 . 8   s.    
         [0045]    A cross-sectional view of the 5 th  embodiment is shown in  FIG. 5A . A top view of the 5 th  embodiment is shown in  FIG. 5B . MTJ is connected lower metal line (write word line) instead of connecting upper metal as adapted in previous embodiments. Read lead is connected to top of MTJ different from previous 4 embodiments. Thin oxide separates upper metal and read lead/MTJ electrically. MTJ is also patterned twice along word line direction first and bit line direction 2 nd  as was the case with the 4 th  embodiment. At 2 nd  patterning, upper metal layer, MTJ and bottom read lead are patterned with one mask. No overlay margin is required so that upper metal width becomes same feature size as MTJ. It save 4∂ compared to conventional structure showed in Prior Art FIG. A and FIG. B. The structure has other benefit than cell size. The upper metal wraps around the MTJ. The current flowing the metal induces stronger magnetic field than straight metal line. It works better to switch the pin layer direction. 
         [0046]    As shown in  FIG. 5.1 , lower metal as write word line  501  and landing pad  502  to read device are patterned after FEOL process is completed. The vias  503  and  504  to be connected to MTJ and read lead metal are opened over  501  and  502 . 
         [0047]    Tungsten is deposited and allows CMP to make the surface smooth. MTJ Pin layer  505 , tunnel oxide  506 , MTJ fixed layer  507  and hard mask layer are subsequently deposited as previous embodiments. The stack is patterned as a line along the word line direction and followed by spacer oxide protect the MTJ sidewall as shown in  FIGS. 5.2  and  5 . 2   s.  Read metal  509  is deposited and patterned as shown in  FIGS. 5.3  and  5 . 3   s.  With the same process step as previous embodiments, Thin oxide  510  is deposited to insulate MTJ/Read Metal and upper metal (Bit line). Upper metal  511  like as aluminum/Cu alloy is deposited as shown in  FIGS. 5.4  and  5 . 4   s.  Patterning photoresist, the upper metal is etched with conventional metal etching process by reaching to insulation oxide  510 . Oxide  510  can be removed by wet etch. Subsequent Ion milling etches read lead metal, MTJ as shown in  FIGS. 5.5  and  5 . 5   s.    
         [0048]    Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader spirit of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense.