Abstract:
A sensor includes a Hall cell and a compensation circuit for subtracting a magnet background field from the Hall cell output to provide a signal corresponding to rotations of a toothed ferrous gear.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     Not Applicable. 
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH 
     Not Applicable. 
     FIELD OF THE INVENTION 
     The present invention relates generally to sensors and, more particularly, to sensors having Hall cells for detecting rotations of a ferrous gear. 
     BACKGROUND OF THE INVENTION 
     As is well known in the art, integrated gear tooth sensors using Hall cells and rotating targets are widely used in electronic automotive systems and many other such systems. In typical applications where an accurate detection of the tooth position is required, the Hall cell output is processed by relatively sophisticated electronics in order to cancel various distortive effects, such as offsets, temperature changes, airgap variations, production tolerances, and the like. 
     As shown in the prior art arrangement of FIG. 1, an integrated circuit sensor  10  can include a Hall cell  12  in proximity to a ferrous gear  14 . The Hall cell  12  is attached to one pole face, e.g., N, of a magnet  16 . The gear  14  rotates in close proximity to the Hall cell  12  such that the relatively strong field  18  of the magnet  16  or “background field” is weakly modulated by the airgap variations corresponding to the alternating tooth/valley perimeter of the rotating gear  14 . The resultant signal variations reflect the gear  14  rotations as the Hall cell  12  generates a relatively small alternating signal voltage v sg  embedded in the undesirable, relatively large direct current (DC) background signal V bf , as shown in FIG.  2 . 
     As is well known in the art, as much of the background signal V bf  as possible is removed for accurate processing of the signal v sg  generated by rotation of the ferrous gear  14 . Since the gear rotating frequency can vary within large limits including DC values, removing the background field signal V bf  by frequency discrimination is generally not practical. 
     FIGS. 3A-C show a common conventional sensor  20  arrangement for canceling the background field V bf . In general, the prior art sensor  20  includes first and second Hall cells  12   a ,  12   b  coupled in a differential arrangement as shown in FIG. 3B. A subtractor  22  receives signals from the first and second Hall cells  12   a,b  and outputs the difference signal V sg  between the two signals. If the Hall cells  12   a,b  are properly spaced as compared to the tooth spacing on the gear  14 , the difference voltage V sg  between the two Hall cells  12   a,b  produces the desired signal variations while the background field V bf  is cancelled for the most part. Due to assembly imbalances and Hall cell offsets, the signal at the subtractor  22  output includes a residual offset V roff  (FIG. 3C) that can reach five to ten percent or more of the background signal V bf . To further reduce the residual offset V roff , known sensors require additional sophisticated electronic processing or costly trimming techniques. 
     It would, therefore, be desirable to overcome the aforesaid and other disadvantages by providing a sensor having a Hall cell that eliminates the need to correct for assembly imbalances and associated offsets. It would further be desirable to provide a sensor that is more economical than conventional sensor arrangements. 
     SUMMARY OF THE INVENTION 
     The present invention provides a Hall sensor with a subtractor circuit that removes a magnetic background field from a signal that is modulated by airgap variations from a rotating ferrous gear. With this arrangement, the need for differential Hall cells is eliminated. While the invention is primarily shown and described in conjunction with a Hall cell detecting rotations of a toothed ferrous wheel, it is understood that the invention is applicable to Hall sensors in general in which it is desirable to remove a background signal. 
     In one aspect of the invention, a sensor includes a Hall cell and a compensation circuit providing respective inputs to a subtractor circuit. The Hall cell output signal provided to the subtractor circuit includes a first component corresponding to a background field and a second component corresponding to air gap variations detected by the Hall cell. The compensation circuit output signal to the subtractor circuit cancels the background field signal component in the Hall cell output signal. Thus, the remaining signal corresponds to the second component of the Hall cell output, i.e., the detected air gap variations, which can be generated by teeth on a rotating ferrous gear. 
     In one particular embodiment, the compensation circuit includes a comparator circuit receiving an amplified subtractor output signal and a threshold signal. The comparator output is gated with a clock signal and the output is provided to a counter having outputs coupled to a digital-to-analog converter (DAC), which outputs an analog signal to the subtractor. The counter increments until the comparator output stops the clock signal from changing the counter value. After initialization, the signal from the DAC to the subtractor increases until reaching a steady state corresponding to the background field as determined by the comparator. The subtractor then outputs the signal corresponding to gear rotation with the background field signal removed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a pictorial representation of a prior art Hall sensor for detecting rotations of a ferrous gear; 
     FIG. 2 is a graphical depiction of signal strength over time for the prior art Hall sensor of FIG. 1; 
     FIG. 3A is a pictorial representation of a prior art sensor having first and second Hall cells coupled in a differential arrangement; 
     FIG. 3B is a schematic representation of the prior art sensor of FIG. 3A; 
     FIG. 3C is a graphical depiction of signal strength over time for the prior art sensor of FIG. 3A; 
     FIG. 4 is a schematic representation of a Hall cell sensor in accordance with the present invention; 
     FIG. 5 is a graphical depiction of voltage over time for an exemplary sensor having background field cancellation in accordance with the present invention; 
     FIG. 6 is a schematic representation showing further details of an exemplary sensor having background field cancellation in accordance with the present invention; 
     FIG. 7 is a further schematic representation showing additional details of an exemplary sensor having background field cancellation in accordance with the present invention; and 
     FIGS. 8A-C are graphical snapshot representations of voltages over time for an exemplary sensor having background field cancellation in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 4 shows an exemplary Hall cell sensor  100  having a compensation circuit  102  for removing a background signal from a signal generated by a rotating ferrous gear  104  in accordance with the present invention. In general, the sensor  100  cancels, e.g., subtracts, the magnetic or background field generated by a magnet  106  within a Hall cell  108  from a signal containing the background signal and a signal detected by the Hall cell as the gear  104  rotates. The rotating gear  104 , by periodically varying the airgap between the magnet  106  and the gear with its tooth/valley perimeter, modulates the magnetic field of the magnet such that the Hall cell  108  outputs an alternating voltage superimposed on the relatively large DC voltage background field. 
     As shown in FIG. 5, the Hall cell output voltage V h  includes a relatively large DC voltage V bf  component due to the background field and a relatively small signal voltage v sg  component generated by the tooth/valley airgap variations. As described in detail below, after a compensation circuit signal V c  reaches a balance point BP, the background signal V bf  can be subtracted out leaving the small signal voltage v sg . 
     Referring again to the exemplary embodiment of FIG. 4, the compensation circuit  102  includes a subtractor  110  that receives at a first input  110   a  the output signal V h  from the Hall cell  106  and a compensation signal V c . The subtractor output signal V in  is amplified by an amplifier  112 , which provides an output voltage V o . In one particular embodiment, the amplifier output voltage signal V o  is provided to a first input  114   a  of a comparator  116 , which also receives a predetermined threshold voltage V th  at a second input  114   b . In one particular embodiment, the threshold voltage V th  at the second comparator input  114   b  is set to zero Volts. 
     A logic circuit  118 , here shown as a NOR gate, receives the comparator output signal and a clock signal  120 . The NOR output signal  122  is coupled to the clock signal input of a counter circuit  124 , which increments (or decrements) each clock cycle. A Digital-to-Analog Converter (DAC)  126  receives the digital value from the counter  124  and provides a converted analog compensation signal V c  to a second input  110   b  of the subtractor  110 . 
     In operation, the clock signal  120  initially passes through the NOR gate  118  and increments the counter  124  so as to increase the level of the compensation signal V c  to the second input of the subtractor  110 . When the subtractor output reaches a level sufficient to change the output state of the comparator  116 , the counter  124  stops increasing and the DAC  126  signal output V c  to the subtractor  110  reaches a steady state. 
     Looking now to FIG. 5 in conjunction with FIG. 4, the compensating voltage signal V c  from the DAC  126  is subtracted from the Hall cell output signal V h  after turn on, until full cancellation of the background signal V bf  is achieved after a time t c  leaving the small signal voltage v sg . At this time, the comparator  116  output changes state when the amplifier  112  output voltage V o  is no longer greater than zero. The change in output state blocks the clock signal  120  through the NOR gate  118  and, thereby stops the counter  124  from incrementing. The DAC/counter stores the latest compensating voltage V c  value until the next turn-on. With this arrangement, the DC background field voltage signal V bf  is removed using only one Hall cell. 
     As shown and described above, the amplifier input voltage v in  (subtractor output voltage) is the difference between the Hall cell output voltage v h  and the compensating voltage V c . In one embodiment, the compensating voltage V c , after turn on, ramps up steadily from a zero level until reaching the Hall cell output voltage V h . When the voltages are equal, i.e, v c =v h , the amplifier output v o  is zero, and the comparator  116 , which receives the amplifier output voltage v o  and a threshold voltage V th , changes output state so as to prevent clock pulses from reaching the counter  124 . The DAC  126  then maintains the last voltage level generated and provides this signal to the subtractor  110 . 
     EXAMPLE 
     In a typical gear tooth sensor using ferrous targets and operating at relatively low levels background fields of about 3 kG and signals of about 100 Gpp (peak-to-peak) are found. With Hall cells having a sensitivity of about 20 μV/G, the Hall cell produces a background dc voltage of about 60 mV plus a useful signal of 2 mVpp. In this example, once the compensation voltage V c  reaches about 60 mV, the comparator  116  changes output state, the data remains stored in the counter  124  and a steady state voltage of 60 mV is applied to the subtractor  110 . 
     FIG. 6 shows a further embodiment of a Hall cell sensor  200  that cancels a magnet background signal from a signal generated by Hall cell  202  proximate a rotating ferrous gear  204  in accordance with the present invention. A Hall cell  202  provides a differential signal to a first differential transconductor  206 , which includes a subtractor circuit  208 , such as the subtractor circuit  110  of FIG.  4 . First and second load resistances RL 1 , RL 2  can be coupled to the respective differential outputs  210   a, b , which provide the output voltage v o  to a comparator  212 . A flip flop circuit  214  is coupled to the comparator output  215  and a logic circuit  216 , such as a NOR gate, receives a clock signal  218  and the flip flop output signal Q. The logic circuit  216  output is coupled to a counter  220  to which a DAC  222  is connected. A second differential transconductor  224  receives the DAC output  222  and provides a differential current Ia, Ib to the first transconductor  206 . 
     The difference between the current signals Ia, Ib entering at first and second terminals T 1   a , T 1   b  of the first transconductor  206  produces a compensation voltage v c , which is subtracted by the subtractor circuit  208  from the input voltage v h , as described below. The DAC  222  output voltage controls the differential current Ia, Ib via the second differential transconductor  224 . 
     The comparator  212  detects the balance condition when the differential output voltage goes through zero, generating a hold signal that is stored in the flip flop  214 , which blocks the clock signal  218  from the counter  220 . It is understood that the differential transconductors  206 ,  224  provide enhanced linear amplification of relatively large input signals. 
     FIG. 7 shows an exemplary circuit implementation of the first and second differential transconductors  206 ,  224 . The first (amplifying) transconductor  206  operates with bias currents Ia, Ib, which are generated by the second (mirror) transconductor  224 . The differential bias current Ia-Ib from the second transconductor  224  corresponds to an output voltage V DAC  divided by the value of a resistor R 2  coupled across emitter terminals of first and second mirror transistors Q 1 , Q 2 , i.e., V DAC /R 2 . Straightforward circuit analysis at first and second nodes N1, N2 of the first transconductor  206  gives an amplifier gain equal to the load resistors RL divided by the value of the resistor coupled between emitter terminals of third and fourth transistors Q 3 , Q 4  of the first transconductor, i.e., 2RL/R 1  and the output compensation voltage becomes Vc=2(Ia−Ib)RL, which is equivalent to Vc=[2V DAC RL]/R 2 . 
     It is understood that the signal at the subtractor output, which is identical to the signal at the amplifier output v o  except for a gain factor, shows some residual offset due to the fact that the cancelled signal is not the true background voltage but rather the sum of the background voltage and the signal voltage. This offset depends on the instantaneous value of the Hall cell output voltage v h  at the time cancellation (v h =v c ) occurs, which triggers the flip-flop circuit FF. 
     FIG. 8A shows the case where the hall cell output signal v h  is equal to the background field V bf  at the balance point BP (v h =v c ) giving rise to a centered waveform at the subtractor output. FIG. 8B shows one extreme case where the subtractor output signal is maximum at the balance point BP, for example when a tooth is just facing the Hall cell. The subtractor output includes a negative offset voltage V off . FIG. 8C shows the converse extreme when the subtractor output signal is minimum for the case of a gear valley facing the Hall cell producing a positive offset voltage V off . 
     From the above it can be seen that the residual offset V off  after compensation can range between about −v sg (p−p)/2 to about +v sg (p−p)/2. This offset is relatively well behaved as the critical ratio |V roff |/v sg (p−p) can never be higher than 0.5. This is in contrast to ratios that are 5 to 10 times higher in prior art differential cancellation systems when operating at low levels. 
     It is understood that the background signal canceling technique of the present invention can be readily adapted for canceling negative or positive background fields by adjusting the DAC range such that the compensating voltage starts at the most negative value of V bf  and extends up to the most positive value of V bf . In addition, one of ordinary skill in the art will recognize that cancellation can be performed not only at startup when v sg  is approximately a dc voltage but under a running target. 
     As is well known to one of ordinary skill in the art, the sensitivity of Hall cells, particularly when fed from a constant voltage source, shows a well known temperature dependence. After compensation of the background field V bf , the temperature dependence can remain unchanged by providing the compensation voltage V c  with a similar temperature dependence. This can be readily achieved by properly controlling the temperance dependence of the DAC output voltage. 
     In contrast with prior art differential Hall cell sensors, such as that shown in FIG. 3, the inventive Hall sensor requires one Hall cell. One of ordinary skill in the art will readily appreciate the comparative advantages in chip area and current consumption, as well as the elimination of offsets for assembly imbalances. Further advantages accrue since the inventive sensor performance is immune to angle deviations in the gear rotating plane and to gear tooth to tooth spacing. 
     Various modifications and/or substitutions to the particular embodiments shown and described herein will be readily apparent to one of ordinary skill in the art. For example, while illustrative circuits, such as NOR gates and counters are used herein, a variety of other circuit arrangements well known to one of ordinary skill in the art can be used to meet the needs of a particular application. In addition, a range of analog and digital circuit configurations different from the illustrative embodiments described herein can be used without departing from the invention. 
     One skilled in the art will appreciate further features and advantages of the invention based on the above-described embodiments. Accordingly, the invention is not to be limited by what has been particularly shown and described, except as indicated by the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.