Abstract:
A data transmission system is provided for transmitting user data to and receiving data from a communication channel, comprising a first address generator to generate a first address in accordance with the user data. A linear block encoder encodes the user data in response to the first address from the first generator. A transmitter transmits an output of the linear block encoder to the communication channel, and a soft channel decoder to decode data. A second address generator generates a second address in accordance with the decoded data from the soft channel decoder, and a soft linear block code decoder decodes data decoded by the soft channel decoder in accordance with the second address from the second address generator.

Description:
This application is a divisional of U.S. patent application Ser. No. 09/730,597, filed Dec. 7, 2000, which claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application Ser. No. 60/214,781, filed Jun. 28, 2000, the entire contents of each of which are incorporated by reference herein. 
    
    
     The present application is related to the following commonly-assigned, co-pending applications: “Multi-Mode Iterative Detector”, assigned U.S. patent application Ser. No. 09/559,186, and filed on Apr. 27, 2000; “LDPC Encoder and Method Thereof”, assigned U.S. patent application Ser. No. 09/730,752, and filed on Dec. 7, 2000; “LDPC Decoder and Method Thereof”, assigned U.S. patent application Ser. No. 09/730,603, and filed on Dec. 7, 2000; and “Parity Check Matrix and Method of Forming Thereof”, assigned U.S. patent application Ser. No. 09/730,598, and filed on Dec. 7, 2000, the entire contents of each of which are incorporated by reference herein. 
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates generally to an address generator for providing addresses to a linear block encoder and decoder in a data transmission system. More particularly, the present invention relates to an address generator for providing addresses to a low density parity-check code (LDPC) encoder for a write channel and decoder for a read channel in a disk drive system. 
     2. Background Information 
       FIG. 1  illustrates a conventional digital data transmission system. As shown therein, a digital data transmission system comprises a transmitting section  300  for transmitting user data to receiver  500  via communication channel  401 . 
     The operation of transmission section  300  will now be explained. Prior to processing by transmitting section  300 , input or user data maybe encoded with an error correcting code, such as the Reed/Solomon code, or run length limited encoded (RLL) or a combination thereof by encoder  302 . The encoded output encoder  302  is then interleaved by deinterleaver  308  for input to linear block code encoder  304  which generates parity data in a known manner utilizing linear block codes. One example of a linear block code is a low-density parity-check code (LDPC) which is discussed by Robert G. Gallager in  Low - Density Parity - Check Codes,  1963, M.I.T. Press, and by Zining Wu in  Coding and Iterative Detection For Magnetic Recording Channels,  2000, Kluwer Academic Publishers, the entire contents of each of which are incorporated herein by reference. Deinterleaver  308  permutes the data so that the same data is reordered before encoding by linear block code encoder  304 . By permuting or redistributing the data, deinterleaver  308  attempts to reduce the number of nearest neighbors of small distance error events. User data at the output of encoder  302  is referred to as being in the channel domain; that is the order in which data is transmitted through the channel. The order of data processed by deinterleaver  308  is referred to as being in the linear block code domain. The parity data from linear block code encoder  304  is combined with the data encoded by encoder  302  by multiplexer  306  for input to channel transmitter  310 . 
     Transmitter  310  transmits the combined user and parity data from multiplexer  306  typically as an analog signal over communication channel  401  in the channel domain. Communication channel  401  may include any wireless, wire, optical and the like communication medium. Receiver  500  comprises an analog to digital converter  502  to convert the data transmitted on communication channel  401  to a digital signal. The digital signal is input to soft channel decoder  504 , which provides probability information of the detected data. Soft channel decoder  504  may be implemented by a Soft Viterbi Detector or the like. The output of the soft channel decoder  504 , which is in the channel domain, is converted into the linear block code domain by deinterleaver  510 . Deinterleaver  510  is constructed similarly to deinterleaver  308 . Soft linear block code decoder  506  utilizes this information and the parity bits to decode the received data. One output of soft linear block code decoder  506  is fed back to soft channel decoder  504  via interleaver  512 , which converts data in the linear block code domain to the channel domain. Interleaver  512  is constructed to perform the reverse operations of deinterleaver  510 . Soft channel decoder  504  and soft linear block code decoder  506  operate in an iterative manner to decode the detected data. 
     The other output of soft linear block code decoder  506  is converted from the linear block domain to the channel domain by interleaver  514 . Interleaver  514  is constructed similarly to interleaver  512 . The output of interleaver  514  is passed on for further processing to decoder  508 . Decoder  508  is implemented to perform the reverse operations of encoder  302 . 
       FIG. 9  is an example of deinterleaver  308  ( 510 ) and an example of interleaver  514  ( 512 ). As shown therein, a codeword comprising bits b 1 , b 2 , b 3 , b 4 , b 5  and b 6  are input in time order of the first bit b 1  to the last bit b 6  to deinterleaver  308  ( 510 ). Deinterleaver  308  reorders the bit in accordance with the table below and outputs bit b 3  first to the last bit b 5  as the reordered codeword. 
     
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Input bit order 
                 Output bit order 
               
               
                   
                   
               
             
             
               
                   
                 1 
                 3 
               
               
                   
                 2 
                 2 
               
               
                   
                 3 
                 4 
               
               
                   
                 4 
                 6 
               
               
                   
                 5 
                 1 
               
               
                   
                 6 
                 5 
               
               
                   
                   
               
             
          
         
       
     
     Interleaver  514  ( 512 ) performs the inverse operation of deinterleaver  308  ( 510 ). Interleaver  514  ( 512 ) takes, for example, the reordered codeword, bit b 3  being first and bit b 5  being last, and outputs a codeword in the original order, bit b 1  being first and bit b 6  being last, as shown in the table below. 
     
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Input bit order 
                 Output bit order 
               
               
                   
                   
               
             
             
               
                   
                 3 
                 1 
               
               
                   
                 2 
                 2 
               
               
                   
                 4 
                 3 
               
               
                   
                 6 
                 4 
               
               
                   
                 1 
                 5 
               
               
                   
                 5 
                 6 
               
               
                   
                   
               
             
          
         
       
     
     The implementation of the conventional interleaver described above is complicated, and these circuits are difficult to design, especially when processing data blocks of the size of thousands of bits. Moreover, an interleaver (or deinterleaver) for processing 5000 bits requires a large look-up table (LUT) for performing the interleaving (deinterleaving) operations. Such conventional implementation requires approximately thousands of cycles, which is inconsistent with the requirements of ever increasing high data transfer rates. The linear block code encoder must have access to all bits in the same equation at one time. Memory structures such as SRAM are not efficient for access data required by the linear block encoder, and more expensive memory structures (in terms of fabrication cost, size and power consumption), such as registers and flip flops may be employed. As can be seen from  FIG. 1 , the conventional system requires additional circuitry for the two deinterleavers. 
     Another example of an interleaver is shown in  FIG. 10 . The interleaver shown in  FIG. 10  comprises a swap circuit  810  for swapping bits in accordance with a predefined table to assure that parity bits are not placed in inappropriate positions. The data is then shifted by shifting circuit  820 , so that each of the code words is interleaved in a different manner. The output of which is then interleaved by interleave circuit  830 , in which the size of the codewords corresponds to the size of the LDPC codewords. As such, the interleaver is highly coupled to the parity-check matrix. As used herein, the deinterleaver performs the inverse function as the interleaver. As will be appreciated by one of ordinary skill in the art, the term deinterleaver may be used for the term interleaver, so long as the term interleaver is used for the term deinterleaver. 
     SUMMARY OF THE INVENTION 
     According to a first aspect of the invention, a data transmission system is provided for transmitting user data to and receiving data from a communication channel, comprising a first address generator to generate a first address in accordance with the user data. A linear block encoder encodes the user data in response to the first address from the first generator. A transmitter transmits an output of the linear block encoder to the communication channel, and a soft channel decoder to decode data. A second address generator generates a second address in accordance with the decoded data from the soft channel decoder, and a soft linear block code decoder decodes data decoded by the soft channel decoder in accordance with the second address from the second address generator. 
     According to a second aspect of the present invention, a decoder is provided for decoding data from a communication channel, comprising a soft channel decoder to decode data. A first address generator generates a first address in accordance with the decoded data from the soft channel decoder, and a soft linear block code decoder to decode data decoded by the soft channel decoder in accordance with the first address from the first address generator. 
     According to a third aspect of the present invention, an encoder is provided for encoding data from a communication channel, comprising a first address generator to generate a first address in accordance with the user data. A linear block encoder encodes the user data in response to the first address from the first generator, and a transmitter to transmit an output of the linear block encoder to the communication channel. 
     According to a fourth aspect of the present invention, a data transmission system is provided for transmitting user data to and receiving data from a communication channel, comprising first address generator means for generating a first address in accordance with the user data. Linear block encoding means encodes the user data in response to the first address from the first generator means, and transmitting means transmits an output of the linear block encoding means to the communication channel. Soft channel decoding means decodes data, and second address generator means generates a second address in accordance with the decoded data from the soft channel decoding means. Soft linear block code decoding means decodes data decoded by the soft channel decoding means in accordance with the second address from the second address generator means. 
     According to a fifth aspect of the present invention, a decoder is provided for decoding data from a communication channel, comprising soft channel decoding means for decoding data. First address generator means generates a first address in accordance with the decoded data from the soft channel decoding means, and soft linear block code decoding means decodes data decoded by the soft channel decoding means in accordance with the first address from the first address generator means. 
     According to a sixth aspect of the present invention, an encoder is provided for encoding data from a communication channel, comprising first address generator means for generating a first address in accordance with the user data. Linear block encoding means encodes the user data in response to the first address from the first generator means, and transmitting means transmits an output of the linear block encoding means to the communication channel. 
     According to a seventh aspect of the present invention, a method is provided for transmitting data to and receiving data from a communication channel, comprising the steps of (a) generating an address in accordance with the data to be transmitted to the communication channel; (b) linear block encoding the data in accordance with the address generated in step (a); (c) transmitting the data encoded in step (b) to the communication channel; (d) receiving the data from to the communication channel; (e) soft channel decoding the data read in step (d) in accordance with data decoded in step (g); (f) generating an address in accordance with the data soft linear block code decoding the data decoded in step (e); and (g) soft linear block code decoding data decoded by in step (e) in accordance with the address generated in step (f). 
     According to an eighth aspect of the present invention, a method is provided for decoding data received from a communication channel, comprising the steps of (a) soft channel decoding the data received in accordance with data decoded in step (c); (b) generating an address in accordance with the data soft linear block code decoding the data decoded in step (a); and (c) soft linear block code decoding data decoded by in step (a) in accordance with the address generated in step (b). 
     According to a ninth aspect of the present invention, a method is provided for encoding data transmitted to a communication channel, comprising the steps of: (a) generating an address in accordance with the data to be transmitted to the communication channel; (b) linear block encoding the data in accordance with the address generated in step (a); and (c) transmitting the data encoded in step (b) to the communication channel. 
     According to a tenth aspect of the present invention, a computer program embodied in a medium is provided for transmitting data to and receiving data from a communication channel, comprising the steps of: (a) generating an address in accordance with the data to be transmitted to the communication; (b) linear block encoding the data in accordance with the address generated in step (a); (c) transmitting the data encoded in step (b) to the communication channel; (d) receiving the data from to the communication channel; (e) soft channel decoding the data read in step (d) in accordance with data decoded in step (g); (f) generating an address in accordance with the data soft linear block code decoding the data decoded in step (e); and (g) soft linear block code decoding data decoded by in step (e) in accordance with the address generated in step (f). 
     According to a eleventh aspect of the present invention, a computer program embodied in a medium is provided for decoding data received from a communication channel, comprising the steps of: (a) soft channel decoding the data received in accordance with data decoded in step (c); (b) generating an address in accordance with the data soft linear block code decoding the data decoded in step (a); and (c) soft linear block code decoding data decoded by in step (a) in accordance with the address generated in step (b). 
     According to a twelfth aspect of the present invention, a computer program embodied in a medium is provided for encoding data transmitted to a communication channel, comprising the steps of: (a) generating an address in accordance with the data to be transmitted to the communication channel; (b) linear block encoding the data in accordance with the address generated in step (a); and (c) transmitting the data encoded in step (b) to the communication channel. 
     Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects and advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments, in conjunction with the accompanying drawings, wherein like reference numerals have been used to designate like elements, and wherein: 
         FIG. 1  is a block diagram of a conventional data transmission system. 
         FIG. 2  is a block diagram of a data transmission system in accordance with the present invention. 
         FIG. 3  is a diagram illustrating a block of user data and index thereof. 
         FIG. 4  is a block diagram of address generator in accordance with the present invention. 
         FIG. 5  is a block diagram of a read/write channel of disk drive incorporating the data transmission system of  FIG. 2 . 
         FIG. 6  is an example of a parity check matrix in accordance with the present invention. 
         FIG. 7  is a flow chart of the method embodied by the address generator of  FIG. 4 . 
         FIG. 8  is a diagram illustrating a block of user data and index thereof incorporating positions for parity bits. 
         FIG. 9  is a block diagram of deinterleaver and interleaver. 
         FIG. 10  is a block diagram of another interleaver. 
         FIG. 11  is an overview block diagram of the address generator of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference is now made to  FIG. 2 , which is a block diagram of a data transmission system in accordance with the present invention. In general as shown therein, a digital data transmission system comprises a transmitting section  300 ′ for transmitting user data to receiver  500 ′ via communication channel  401 . The inventors have observed that a linear block code encoder is not dependent on a position of a bit interleaved. Rather the linear block code encoder only requires a list of equations for a given bit. In other words, there is no need to process the data in the order defined by the interleaver, instead data may be processed in the same order as it is written to the channel. This can be accomplished by incorporating an address generator to provide an address of the appropriate equation of the linear block code encoder. This principle can be similarly applied to the soft linear block decoder. As a result, deinterleaver  308  of the conventional system is now replaced by address generator  328 , and deinterleaver  510  is now replaced by address generator  530 . Accordingly, there is no requirement for the physical interleaving of data in the receiver  500 ′, since the data remains in the same order as the order of bits of data in the channel throughout this system. The order of bits of data transmitted through the channel is referred to as the channel domain. 
     The operation of transmission section  300 ′ will now be explained. Prior to processing by transmitting section  300 ′, as in the conventional system, input or user data maybe encoded with an error correcting code, such as the Reed/Solomon code, or run length limited encoded (RLL) or a combination thereof by encoder  302 . Addresses for the parity equations of linear block code encoder  304  are generated by address generator  328  in accordance with an index of the bits of data, the index being determined by address generator  328 . Address generator  328  is responsive to counter  730  under the control of controller  740 . Controller  740  synchronizes counter  730  to the output of encoder  302  so that counter  730  can provide a count of the number of bits in a codeword output by encoder  302  and a count of the number of codewords. In the preferred embodiment, the data block size is 5000 bits. 
       FIG. 3  illustrates the relationship between the user data and its index. As shown therein, user data consists of sequential codewords of data, each codeword consisting of n+1 bits of data, namely bits B 0  through Bn, as input to transmission section  300 . Preferably, each codeword consists of 74 bits of data. However it is possible for the last codeword of a sequence to be incomplete. Associated with each bit of data is a respective index 0-n or 0-73 in the preferred embodiment and a codeword index. The index represents the location of a bit within the codeword. The size of the codeword is determined in accordance with the design of the parity matrix and deinterleaver  770 , as will be explained in detail herein below. 
     Turning back to  FIG. 2 , linear block code encoder  304  utilizes the user data and address from address generator  328  to provide the parity bits to multiplexer  306 . Linear block code encoder  304  is preferably implemented as a low-density parity-check code (LDPC) encoder as described in commonly assigned, co-pending patent application entitled “LDPC Encoder and Method Thereof,” assigned U.S. patent application Ser. No. 09/730,752, and filed on Dec. 7, 2000, the entire contents of which are incorporated herein by reference. The parity data from linear block code encoder  304  is combined with the data encoded by encoder  302  by multiplexer  306  for input to channel transmitter  310 . In the preferred embodiment, the combined data consists of series of a pair parity bits followed by 40 bits of user data. This constraint is established by encoder  302 . 
     Transmitter  310  transmits the combined user and parity data from multiplexer  306  typically as an analog signal over communication channel  401  in the channel domain. Communication channel  401  may include any wireless, wire, optical, magnetic and the like. 
     Receiver  500 ′ comprises an analog to digital converter  502  to convert the data transmitted on communication channel  401  to a digital signal. The digital signal is input to soft channel decoder  504 , which provides soft or probabilistic information of the detected data to soft linear block decoder  506 . Soft channel decoder may be implemented as a Soft Viterbi Detector or the like, and address generator  530  may be constructed similarly as address generator  328  in transmission section  300 ′. The soft information output by soft channel decoder  504  remains in the channel domain and is decoded by soft linear block code decoder  506 , in accordance with the address of the parity equations generated by address generator  530 . Address generator  530  is responsive to counter  735  under the control of controller  745 . Controller  745  synchronizes counter  735  to the output of soft channel decoder  504  so that counter  830  can provide a count of the number of bits in a codeword output by soft channel decoder  504  and a count of the number of codewords. 
     Soft linear block code decoder  506  operates in combination with soft channel decoder  504  and address generator  530  in an iterative fashion. Soft linear block code decoder is preferably implemented as a low-density parity-check code (LDPC) decoder as described in commonly assigned, copending patent application entitled “LDPC Decoder and Method Thereof,” assigned U.S. patent application Ser. No. 09/730,603, and filed on Dec. 7, 2000, the entire contents of which are incorporated herein by reference. It is noted that since the soft information from soft channel decoder  504  to soft linear block code decoder  506  are both in the channel domain, thus as noted above, there is no need for any interleavers or deinterleavers in receiver  500 ′. 
     After the iterative process has completed, the output of soft linear block code decoder  506  is passed on for further processing to decoder  508 . Decoder  508  is implemented to perform the reverse operations of encoder  302  or correct for any data errors. 
     Prior to discussing the construction and operation of the address generator, reference is now made to  FIG. 6  for an explanation of the parity check matrix. The preferred matrix is 222 rows (or equations) by 5402 columns, which comprises 220 linearly independent rows (where 5402=73*74). The matrix can be divided into three tiers of equations having 73, 74 and 75 equations, respectively. The set of independent rows can be obtained by canceling the last row of the second tier and third tier, namely the 147 th  row and the 222 nd  row. As shown in  FIG. 6 , the following table shows the values of the elements in the matrix: 
     
       
         
               
               
               
             
           
               
                   
               
               
                 Tier 
                 i th  position 
                 i th  position 
               
               
                   
               
             
             
               
                 1 
                 1 if r = i(mod 73) 
                 0 if r ≠ i(mod 73) 
               
               
                 2 
                 1 if r = i(mod 74) 
                 0 if r ≠ i(mod 74) 
               
               
                 3 
                 1 if r = i(mod 75) 
                 0 if r ≠ i(mod 75) 
               
               
                   
               
             
          
         
       
     
     A matrix having 5402 columns can process a maximum LDPC codeword of 5402 bits. Of course, as will be appreciated by one of ordinary skill in the art, the matrix may be truncated to accommodate a smaller block, however the matrix must be at least 222×4366 which is dependent on the constraint of encoder  302 . This constraint is for example a RLL constraint. The preferred matrix contains no cycles, since a matrix having cycles has degraded performance that degrades exponentially. With the first tier only, the parity check matrix has a D min =2; by adding the second tier, the parity check matrix has a D min =4; and by adding the third tier, the parity check matrix has a D min =6. A further description of the parity check matrix is provided in commonly assigned, co-pending application entitled “Parity Check Matrix and Method of Designing Thereof,” assigned U.S. patent application Ser. No. 09/730,598, and filed on Dec. 7, 2000, the entire contents of which are incorporated herein by reference. 
       FIG. 11  is an overview block diagram of address generator  328  ( 530 ),  FIG. 4  is a detailed block diagram thereof, and  FIG. 7  is a flow chart of the method embodied therein. Address generator is designed to perform the inverse of the interleaver shown in  FIG. 9 . The address generator in accordance with the present invention is highly coupled to the parity-check matrix. 
     As shown in  FIG. 4 , address generator  328  ( 530 ) comprises a deinterleaver  770  to deinterleave the indices of the codewords. In response to the deinterleaved codewords, equation locator  776  determines the corresponding party-check equation for either linear block code encoder  328  or soft linear block code decoder  506  to utilize. Referring to  FIG. 4 , deinterleaver  770  comprises inner deinterleaver  532 , shift circuit  534  and swap circuit  536 , and equation locator  776  comprises equation 1 circuit  538  equation 2 circuit  540 , and equation 3 circuit  542 . 
     Counter  730  ( 735 ), in response to controller  740  ( 745 ), counts the position of a bit within a codeword or value c from 0-n, where n=73 for a codeword having the size of 74 bits. Counter  730  ( 735 ), also counts the codeword or r=floor(c/74), where floor is defined as an integer operation (step s 815 ). As noted above the size of the codeword is determined in accordance with the design of the parity matrix and deinterleaver  770 . To simplify implementation, address generator  328  and address generator  530  are similarly constructed. It is noted that the data being counted by counter  730  ( 735 ), of address generator  328  does not include any parity bits since the parity bits are added after processing by the linear block decoder encoder  304 . On the other hand, the data being counted by counter  730  ( 735 ), of address generator  530  contains parity bits. Therefore, counter  730  ( 735 ), in address generator  328 , is arranged to count the data as if there were parity bits insert in the data.  FIG. 8  illustrates a block of data containing 40 bits B 0 -B 39 . Also shown therein are the index numbers 0-43, index numbers 0, 1, 42 and 43 being counted as if the data contained parity bits. 
     Referring back to  FIGS. 4 and 7 , inner deinterleaver  532  maps c to c′ in accordance with the Inner Deinterleaver Table below (step S 820 ). In other words each value c is replaced by its corresponding value c′. For example, for c=1, the value is replace by c′=9. As will be appreciated by one of ordinary skill in the art, both c and c′ can have values between 0 and 73. 
     
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                   
               
               
                 INNER DEINTERLEAVER TABLE 
               
             
          
           
               
                   
                 c 
                 c′ 
               
               
                   
                   
               
             
          
           
               
                   
                 0 
                 28 
               
               
                   
                 1 
                 9 
               
               
                   
                 2 
                 44 
               
               
                   
                 3 
                 58 
               
               
                   
                 4 
                 43 
               
               
                   
                 5 
                 45 
               
               
                   
                 6 
                 49 
               
               
                   
                 7 
                 21 
               
               
                   
                 8 
                 30 
               
               
                   
                 9 
                 61 
               
               
                   
                 10 
                 37 
               
               
                   
                 11 
                 53 
               
               
                   
                 12 
                 48 
               
               
                   
                 13 
                 62 
               
               
                   
                 14 
                 16 
               
               
                   
                 15 
                 47 
               
               
                   
                 16 
                 12 
               
               
                   
                 17 
                 65 
               
               
                   
                 18 
                 2 
               
               
                   
                 19 
                 14 
               
               
                   
                 20 
                 71 
               
               
                   
                 21 
                 11 
               
               
                   
                 22 
                 33 
               
               
                   
                 23 
                 60 
               
               
                   
                 24 
                 36 
               
               
                   
                 25 
                 42 
               
               
                   
                 26 
                 27 
               
               
                   
                 27 
                 46 
               
               
                   
                 28 
                 39 
               
               
                   
                 29 
                 38 
               
               
                   
                 30 
                 70 
               
               
                   
                 31 
                 18 
               
               
                   
                 32 
                 17 
               
               
                   
                 33 
                 32 
               
               
                   
                 34 
                 5 
               
               
                   
                 35 
                 10 
               
               
                   
                 36 
                 40 
               
               
                   
                 37 
                 4 
               
               
                   
                 38 
                 8 
               
               
                   
                 39 
                 55 
               
               
                   
                 40 
                 0 
               
               
                   
                 41 
                 72 
               
               
                   
                 42 
                 7 
               
               
                   
                 43 
                 26 
               
               
                   
                 44 
                 34 
               
               
                   
                 45 
                 57 
               
               
                   
                 46 
                 20 
               
               
                   
                 47 
                 69 
               
               
                   
                 48 
                 3 
               
               
                   
                 49 
                 6 
               
               
                   
                 50 
                 22 
               
               
                   
                 51 
                 24 
               
               
                   
                 52 
                 25 
               
               
                   
                 53 
                 31 
               
               
                   
                 54 
                 68 
               
               
                   
                 55 
                 23 
               
               
                   
                 56 
                 29 
               
               
                   
                 57 
                 51 
               
               
                   
                 58 
                 54 
               
               
                   
                 59 
                 64 
               
               
                   
                 60 
                 67 
               
               
                   
                 61 
                 1 
               
               
                   
                 62 
                 59 
               
               
                   
                 63 
                 13 
               
               
                   
                 64 
                 73 
               
               
                   
                 65 
                 52 
               
               
                   
                 66 
                 63 
               
               
                   
                 67 
                 56 
               
               
                   
                 68 
                 35 
               
               
                   
                 69 
                 41 
               
               
                   
                 70 
                 66 
               
               
                   
                 71 
                 19 
               
               
                   
                 72 
                 50 
               
               
                   
                 73 
                 15 
               
               
                   
                   
               
             
          
         
       
     
     In response to inner deinterleaver  532  and the value r from counter  730  ( 735 ), the codeword number, the shift circuit shifts c′ to c″ by (c′−(72−r))(mod 74), 0≦r&lt;72 (step S 825 ). More specifically, the first interleaved codeword is circularly shifted 72 bits and the last interleaved codeword is shifted zero bits (in effect the last group is not shifted). Finally, bits c″ are swapped into bits c′″ by swap circuit  536  in accordance with the Swapping Table below (step S 830 ). For example in interleaver codeword  39 , bit  46  is swapped with bit  0  and bit  51  is swapped with bit  3 . If a row or bit is not specified in the swapping table then there is no swapping in that row or there is no swapping of that bit. 
     
       
         
               
             
               
               
               
             
               
               
               
               
               
             
           
               
                   
               
               
                 SWAPPING TABLE 
               
             
          
           
               
                   
                 bit 
                 bit 
               
               
                   
                   
               
             
          
           
               
                   
                 interleaver codeword 
                 26 
                 68 
                 0 
               
               
                   
                 interleaver codeword 
                 33 
                 43 
                 2 
               
               
                   
                 interleaver codeword 
                 39 
                 46 
                 0 
               
               
                   
                   
                   
                 51 
                 3 
               
               
                   
                 interleaver codeword 
                 46 
                 14 
                 1 
               
               
                   
                   
                   
                 52 
                 11 
               
               
                   
                 interleaver codeword 
                 49 
                 24 
                 1 
               
               
                   
                 interleaver codeword 
                 53 
                 36 
                 28 
               
               
                   
                   
                   
                 63 
                 57 
               
               
                   
                 interleaver codeword 
                 55 
                 36 
                 0 
               
               
                   
                 interleaver codeword 
                 56 
                 35 
                 0 
               
               
                   
                 interleaver codeword 
                 57 
                 45 
                 0 
               
               
                   
                 interleaver codeword 
                 58 
                 24 
                 0 
               
               
                   
                   
                   
                 25 
                 1 
               
               
                   
                   
               
             
          
         
       
     
     The output, c′″, of swap circuit  536  and r of counter  730  ( 735 ), are processed by equation 1 circuit  538  (step S 840 ), equation 2 circuit  540  (step S 845 ), and equation 3 circuit  542  (step S 850 ) to determine the equations in each of three tiers, respectively. Linear block code encoder  304  and soft linear block code decoder  506  utilize the results of these circuits. Additionally, soft linear block code decoder utilizes the value r to determine which bit index with in a parity check equation. 
     More particularly, the equation for tier  1 =c′″+74r (mod 73), the equation for tier  2 =c′″+74r (mod 74) and the equation for tier  3 =c′″+74r (mod 75). As will be appreciated by one of ordinary skill in the art, since 74r is an integer multiple of 74, the equation for tier  2  is simply equal to c′″. The position bit for tier  1  is floor((c′″+74r)/73), the position bit for tier  2  is floor((c′″+74r)/74), or simply r, and the position bit for tier  3  is floor((c′″+74r)/75). Again, since the 74r is an integer multiple of 74 and 0≦c′″74, the bit position of tier  2  is simply r. 
     Reference is now made to  FIG. 5 . Shown therein is a block diagram of a read/write channel of disk drive incorporating the data transmission system of the preferred embodiment. Read/write channel comprises current generator  402  instead of transmitter  310  of  FIG. 2 . The channel comprises write head  404 , disk  406  and read head  408 . These components are well known and operate in a conventional manner. Therefore no further discussion is being presented. One characteristic of a read/write channel is that writing to and reading from the disk are performed at separate times. In view of this characteristic, in order to reduce circuit complexity and reduce power consumption, only one shared address generator need be provided. This can be accomplished by providing selector  560  to select either the user data from encoder  302  as input to address generator  510 ′ when writing to disk  406  or an output of Soft Viterbi decoder  504 ′ when reading from disk  406 . Additionally, the output of address generator  510 ′ is provided to an input of LDPC encoder  304 ′ by means of selector  565  when writing to disk  406  or to an input of LDPC decoder  506  by means of selector  565  when reading from disk  406 . 
     While the invention has been described in conjunction with several specific embodiments, it is evident to those skilled in the art that many further alternatives, modifications and variations will be apparent in light of the foregoing description. More specifically, while the present invention is preferably implemented as an integrated circuit, it is contemplated that the present invention may also be implemented as discrete components or a general-purpose processor operated in accordance with program code instructions or computer program or combination thereof. These program code instructions can be obtain from a medium, such as network, local area network, the Internet, or storage devices. Such storage devices include, by way of example, magnetic storage devices, optical storage devices, electronic storage devices, magneto-optical device and the like. Thus, the invention described herein is intended to embrace all such alternatives, modifications, applications and variations as may fall within the spirit and scope of the appended claims.