Abstract:
A protection device for protecting an electronic circuit against a fault is described. The electronic circuit includes an output stage for driving a load and a driving circuit for driving the output stage. The driving circuit is configured to produce a drive signal in response to at least one input signal. The protection device includes a gating circuit and control means. The gating circuit has a first input configured to receive the drive signal, a second input configured to receive a control signal, and an output configured to activate and deactivate the output stage based on the drive signal and control signal. The control means produce the control signal in response to a detection signal representative of detection of the fault either of the load or of the output stage.

Description:
BACKGROUND 
     1. Technical Field 
     The present invention relates to a device for protecting electric circuits against faults, specifically for switching power electronic circuits. 
     2. Description of the Related Art 
     Devices for protecting various types of integrated electronic circuits, specifically for integrated power circuits of the switching type, are known in the state of the art. Said devices control the turning off of the transistors of the integrated power circuits in response to a fault of the power circuit itself. For example, as shown in  FIG. 1 , the power stage of an integrated circuit may include a half-bridge with two power transistors, one high side HS and one low side LS, arranged between a power voltage Vdd and ground GND and appropriately driven by a driving circuit  1 . In turn, the two transistors drive a load  2  consisting, for example, of a motor. The driving circuit  1  normally supplies the signals to the transistors LS and HS to switch them on or off. 
     The power stage may suffer faults during its use, e.g., overcurrent, overvoltage, or excessive temperature. For such a reason, a protection circuit is normally inserted. Said protection circuit includes a fault detector  4  and a circuit which operates on the driving circuit of the power stage in response to the detection of the fault. The action operated by the protection circuit is normally that of causing the shutdown of the power stage by means of an input signal SD into the circuit  1 . 
     The protection circuit in  FIG. 1  normally includes a comparator  3  which is adapted to compare the signal CIN detected by the fault detector with a reference signal REF, and is adapted to drive a MOS transistor M arranged between the input terminal of the circuit  1 , at which the shutdown signal SD is present, and the ground GND. When the signal CIN is higher than the signal REF, the transistor M is switched on and the signal SD, i.e., the signal for turning off the transistors of the power stage, is taken to a low level, i.e., to ground GND. 
     A problem of such a protection circuit is due to the delay to take the SD signal to a low level. Indeed, an external network, including a resistor R connected to the power voltage Vdd and a capacitor C connected to ground GND, is connected to the drain terminal of the transistor M and thus the signal SD is switched to a low level according to the time constant Ron_M*C, wherein Ron_M is the switch-on resistance of the transistor M. In such a manner, the shutdown signal SD will be sent to the control circuit of the power stage with a certain delay from said time constant which depends on the external network. As a result, the selection of a high-value external capacitive component C is used but, on the other hand, the capacity of taking current of the transistor M limits the maximum obtainable value of the external capacitive component. Therefore, the protection circuit intervention always occurs with a certain delay after detecting the fault, and said delay may cause faults to the power stage. 
     BRIEF SUMMARY 
     In light of the state of the art, one embodiment provides a circuit for protecting electronic circuits against faults which overcomes the aforesaid drawback. 
     One embodiment is a device for protecting an electronic circuit against a fault, said electronic circuit including an output stage for driving a load and a driving circuit of said output stage adapted to drive the output stage in response to at least one input signal, said protection device being adapted to determine the shutdown of the output stage in response to a signal indicating the detection of a fault either of the load or of the output stage. The device includes digital means configured to minimize the time delay between the detection of the fault and the shutdown of the output stage. 
     One embodiment provides a device for protecting electronic circuits which immediately shuts down the output stage by preventing faults either to the same or to the applied load due to the delay in the protective action of the device, because the intervention time of the protection device does not depend on the applied external network. 
     Furthermore, the new circuit architecture of the protection device allows a protection time interval in accordance with a desired value, by modifying the value of the external network. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) 
       The features of embodiments of the present invention will be apparent from the following detailed description of a practical embodiment thereof, shown by way of non-limitative example in the accompanying drawings, in which: 
         FIG. 1  shows a scheme of an electronic circuitry with a protection device in accordance with the known art; 
         FIG. 2  shows a scheme of an electronic circuit provided with a protection device in accordance with a non-limiting embodiment of the present invention; 
         FIG. 3  shows the protection device in  FIG. 2  in more detail in accordance with a non-limiting embodiment of the present invention; 
         FIG. 4  shows an integrated electronic circuit with a power stage and a protection device with driving circuit which are integrated in accordance with a non-limiting embodiment of the present invention; 
         FIG. 5  shows time diagrams related to the signals used in the circuit of  FIG. 2  in accordance with a non-limiting embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows an electronic circuit including an output switching stage  10  arranged between a power voltage and a ground GND and adapted to drive a load  20  with a signal D 1 . The output stage  10  is driven by a driving circuit  30  having at least one input signal Vi and connected to the power voltage Vdd and to ground GND. The circuit  30  is adapted to control the output stage  10  in response to the at least one input signal Vi. The electronic circuit includes a circuit  40  for detecting a fault either of the output stage  10  or of the load  20 , and further includes a protection device  50  that protects the electronic circuit against a fault. Said protection device is adapted to determine the shutdown, or deactivation, of the output stage  10  in response to the detection of a fault by the detection circuit  40 . The output stage  10  is preferably a power stage of the switching type. Preferably, the power stage  10  includes a half-bridge or transistor bridge for driving the load  20 . A fault may be caused by an overcurrent, an overvoltage, or an excessive temperature either in the output stage  10  or in the load  20 . The circuit  40  may detect at least said types of faults. 
     The protection device  50  includes digital means  100 ,  101  configured to minimize the intervention time Tint between the detection of the fault and the shutdown of the output stage  10 , i.e., between the reception of a signal indicating the detection of a fault and the shutdown of the output stage  10 . The intervention time Tint by using the digital means  100 ,  101  is of the order of logic circuitry switching times (for example, a few tens of nanoseconds), and absolutely lower than a hundred of milliseconds. More precisely, the protection device has an input signal ML from the detector  40  and includes an AND gate  101  having the input signal Contr from the driving circuit  30  and a digital gate block  100  receiving the input signal ML and adapted to send a signal INT at a low logical level, i.e., at a substantially zero voltage or at ground GND, to the AND gate  101  in presence of a fault detected with a signal ML at a high logical level, i.e., at a voltage value substantially equal to the voltage Vdd. The value at the low logical level of the signal INT, which is normally at a high logical level, switches the input signal D at the output stage  10  to low logical level, thus shutting down the output stage  10 , specifically if the output stage is of the switching type, by disabling the transistors of the output switching stage. The detector  40  may include an overcurrent detector, e.g., a sensing resistor, and a comparator which compares the current value across said sensing resistor with a reference current value and which emits the signal ML at a high logical level, substantially at the power voltage value Vdd, when the value of the current across the sensing resistor exceeds the reference current value. 
     Preferably, the block  100  is adapted to send a signal Q at a high logical level opposite to the logical level of the signal INT to a transistor M 1 , preferably a MOS transistor, having its drain terminal connected to a terminal SD 1  and its source terminal connected to ground GND. The terminal SD 1  is the input terminal of a hysteresis comparator  102  connected to the voltage Vdd by means of a resistor Rsd and to a ground by means of a capacitor Csd. Both the resistor Rsd and the capacitor Csd belong to a network outside the protection device  50 , while both the transistor M 1  and the comparator  102  belong to the protection device  50 . The circuit part including the transistor M 1 , the external network with the resistor Rsd and the capacitor Csd. The hysteresis comparator  102  is able to, by sending a signal SDC to the AND gate  101 , maintain the shutdown of the output stage  10  for a time interval Td which can be fixed at will and according to the values of the resistor Rsd and of the capacitor Csd. 
     When the signal INT is present to shut down the output stage  10 , the signal Q switches the MOS transistor M 1  on. The signal SD 1 , which is a voltage signal, will start lowering proportionally according to a time constant t 1 =Ron_M 1 *Csd, wherein Ron_M 1  indicates the switch-on resistance of the transistor M 1 , as shown in  FIG. 5 , which also shows the time diagrams of the signals D 1 , Vi, D and SDC. The signal SD 1  will fall under the upper threshold HT of the hysteresis until it reaches the lower threshold LT. Once the lower threshold LT has been reached, the comparator  102  changes status by modifying the output signal SDC, from a high logical level, substantially the power voltage Vdd, to switch to a low logical level, substantially zero voltage or ground GND. 
     The signal SDC is also sent to the block  100  to change the status of the signal Q, from high to low, and consequently shut down the MOS transistor M 1 . In such a manner, the voltage signal SD 1  starts increasing proportionally according to a time constant t 2 =Rsd*Csd. When the signal SD 1  exceeds the upper threshold HT due to the increase, the comparator  102  changes the status thus modifying the output signal SDC, switching from the low logical level to the high logical level. In such a manner, even if the fault ceases with the consequent change of status of the signal INT, the signal D is maintained at the low logic level by the signal SDC. Furthermore, the shutdown time will last for the time interval Td, which may be varied at will by varying the components Rsd and Csd of the external network. 
       FIG. 3  shows more in detail a possible embodiment of the circuit block  100  in  FIG. 2 . The block  100  includes a set-reset flip-flop with dominating set. The block  100  includes a first NOR gate  111  having the input signal ML at the set terminal S and being adapted to provide the signal INT, a second NOR gate  113  having the input signal SDC at the reset terminal R and the input signal ML at another terminal, and a last NOR gate  112  having the input signal outputted by the NOR gate  113  and the input signal INT, and being adapted to provide the signal Q, which in turn is inputted to the NOR gate  111 . 
     With a circuit block  100  made according to this manner, the oscillations of the terminal on which the signal SD 1  insists are avoided when the signal ML remains stable at the high level. 
     Furthermore, the direct connection of the terminal on which the signal SD 1  insists to the AND gate  101  and to the AND gate consisting of the NOR gates  112  and  113  provides a terminal for driving the output stage  10 . 
     The protection device may be integrated with the driving circuit  30 , forming a circuit  300  having the input signals ML, Vi and SD 1  and providing the signal D for driving the output stage  10 , as shown in  FIG. 4 . 
     By means of the protection device  50 , it is possible to minimize the delay between the detection of the fault and the shutdown of the output stage  10 . Indeed, the intervention time period Tint between receiving the signal ML and sending the signal D is of the order of logic circuitry switching times. In contrast, by means of the device of the known art (see  FIG. 1 ) the time delay is of the order of tens of microseconds because such a device depends on the time constant t=Ron_M*C, wherein Ron_M is the switch-on resistance of the transistor M. In such a manner, it is possible to increase the time interval Td to the desired value by simply increasing the value of the capacitor Csd, without the occurrence of the problems disclosed above with regard to the device in  FIG. 1 . 
     Since it does not depend on a latch device, the terminal on which the signal SD 1  insists may be used to drive the output stage  10  and, in some systems where the fault detector  40  consists of a current detector, the faulting signal ML may be used as a current peak detector by setting a fixed shutdown period by means of the capacitor Csd on the terminal on which the signal SD 1  insists. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.