Abstract:
The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority of U.S. Provisional Patent Application Ser. No. 61/479,118, filed Apr. 26, 2011, which is incorporated herein by reference. This application is also related to U.S. Patent Application No. _________, entitled “IMAGE SENSOR ARRAY FOR THE BACK SIDE ILLUMINATION WITH THE JUNCTION GATE PHOTODIODE PIXELS”, filed on the same day. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates, in general, to a back side illuminated (BSI) image sensor that implements pixels having junction gate photo-diodes (JGP), charge clearing gates (CG), storage gates (SG) and pinned barriers (PB). The well potentials of the JGPs and the SGs are controllable to store accumulated charge which is beneficial when the CMOS imager is operating in a global shutter mode. The PBs have a potential that temporarily blocks charge from transferring between the SGs and the floating diffusion (FD). Also, the CGs implement a vertical charge clearing mechanism which transfers accumulated electrons from the wells of the JGPs to the gates of the JGPs. 
       BACKGROUND OF THE INVENTION 
       [0003]    In conventional CMOS sensors, the circuitry for several photo-diodes is shared. The pixels may include two photo-diodes located in neighboring rows that share the same circuitry. 
         [0004]    Shown in  FIG. 1  is a four transistor (4 T) pixel of the conventional CMOS sensor that has global shutter capabilities (i.e. all pixels perform charge integration simultaneously). After charge integration is completed in pinned photodiode  101 , the accumulated charge is transferred (via transfer gate transistor  103 ) into second pinned photodiode  102  where it is stored for readout. 
         [0005]    In this conventional system the second pinned photodiode has a higher pinning voltage, or transfer gate  103  has a potential barrier and a well incorporated in it to ensure proper charge transfer. Also, pinned diode  102  is shielded from the impinging photons  115  to prevent undesirable smear effects when the objects in the scene moves. The signal charge readout from second pinned diode  102  then proceeds by first resetting Floating Diffusion (FD) node  104  to the drain bias voltage by momentarily turning on reset transistor  106  followed by pulsing charge transfer transistor gate  105 . This sequence then proceeds in a sequential order row by row. 
         [0006]    The signal appearing on the FD is buffered by the source follower transistor  107  that is addressed by a row addressing transistor  108 . The signals controlling the charge transfer transistor gates, the reset transistor, and the addressing transistor are supplied by the row bus lines  111 ,  112 ,  113  and  114  respectively. The Vdd bias is supplied to the pixels by the column Vdd line  109  and the signal output appears on the column output line  110 . 
         [0007]    Using the pinned diodes for charge storage is advantageous since it is well known that these diodes have a low dark current generation. High dark current in the storage sites would add to noise and would also generate undesirable shading effects in the image. 
         [0008]    Unfortunately, the second pinned diode consumes a significant pixel area, thus increasing the size of the sensor and ultimately its cost. Another disadvantage of the pinned PD storage gate approach, is the higher, pinning voltage that is necessary for the storage diode. This utilizes a voltage swing that is determined by the maximum device operating voltage and therefore results in a restriction of charge storage capacity (reduced dynamic range (DR)). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is view of a row-shared pixel circuit schematic diagram with two pinned photo-diodes per circuit that is operating on the 4 T principle, according to an embodiment of the present invention. 
           [0010]      FIG. 2  is a cross-sectional view of the back side illuminated pixel with the junction gate photodiode, according to an embodiment of the present invention. 
           [0011]      FIG. 3  shows the potential profiles of the pixel corresponding to the cross-section shown in  FIG. 2  at various gate biasing conditions, according to an embodiment of the present invention. 
           [0012]      FIG. 4  is a view of a junction gate photodiode pixel circuit schematic diagram, according to an embodiment of the present invention. 
           [0013]      FIG. 5  is a view of the topology of one possible layout implementation of the 4-shared photodiode pixel structure, according to an embodiment of the present invention. 
           [0014]      FIG. 6  is a view of the topology of one possible layout implementation of the 4-shared photodiode pixel structure that includes metal wiring, according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    In general, the present invention provides a JGP pixel design with a storage gate, the vertical blooming control, and a vertical charge transfer MOS transistor used for clearing charge from the JGP, which can be used in back side illuminated image sensor arrays. The vertical JGP charge clearing to the gate and the vertical anti-blooming allow a reduction in pixel size thereby providing image senor arrays with high pixel density while preserving high well capacity, low dark current, high Dynamic Range, and low noise. 
         [0016]    Shown in  FIG. 2  is a cross-sectional view of the JGP pixel. The pixel is fabricated on a p+ type doped substrate  201 , using a silicon epitaxial layer region  202  deposited on it. The bottom surface of the array is exposed to the image illumination and may have color filters arrays (CFAs) (e.g. Bayer filter), micro-lenses, and various light shielding layers  217  deposited on it. The top surface of the structure is covered by a dielectric layer  203  that provides electrical isolation of the substrate from the charge storage gate (SG)  210  and the charge clearing gate (CG)  216 . 
         [0017]    When photons  208  enter the substrate they create electrons  207 , which then drift, under the influence of the electric field generated by the JGP pixel doping and bias, into the wells located in regions  206  where they are temporarily stored. The electrons that are generated in the un-depleted regions diffuse first into the depletion region boundaries from where they are again swept into the wells under the JGP. The JGP consists of a n+ type doped region  204  located close to the silicon-silicon dioxide interface, the p-type doped barrier  205 , and the n-type doped charge storage region  206 . The n+ type doped region is connected through a contact hole to a metal interconnect via that provides the bias to this region. In general, the bias can be changed to facilitate the charge transfer. 
         [0018]    When the charge collection is completed, the bias on the JGP is lowered and on the SG  210  it is increased. This cause electrons from the JGP region  206  to flow over the potential barrier under the SG to the potential well. The SG barrier is formed by the implant  211  and the SG charge storage well may be formed by the n-type doping  215 . 
         [0019]    The JGP can be also reset by applying high bias to the charge clearing gate (CG)  216 . This causes electrons stored in the region  206  to flow via the path  214  directly to the n+ doped JGP region  204  around the barrier formed by the doped region  205  and out to the gate driver that biases the JGP. The doping of the charge barrier  205  is selected such that the overflow charge from the JGP storage well can flow over it rather than to spread to neighboring pixel or to overflow to the charge storage well under the SG gate. 
         [0020]    Charge readout from the SG well is accomplished by lowering the bias on this gate, which forces charge to flow over the pinned barrier formed by the p+type doped region  212  and the n-type doped region  215  into the floating diffusion (FD) node  213 . The SG region is shielded from the impinging photons by a light shield  217  and from the stray electrons by a BTP p+ doped barrier  209 . 
         [0021]    Shown in  FIG. 3  is the potential diagram in the JGP pixel in different pixel regions and for different biasing conditions. The storage gate is biased to three different levels resulting in three different potential wells. Level  301  and level  302  corresponds to the SG barrier and SG well potentials when the SG is biased high thus having the capability to receive charge from the JGP. During this time the JGP is biased low resulting in the level  311  in the JGP charge storage well. During the integration period the JGP is biased high, which cusses the JGP charge well to be at the potential level  310 . When the CG gate is biased high, this results in the level  313  and charge is cleared from the JGP. 
         [0022]    During the integration interval, the SG is biased at a mid level with the potentials under the SG barrier and SG well at levels  303  and  304  respectively. When charge is read out from the SG, the gate is pulsed low, resulting in potential levels  305  and  306  respectively. In general, this causes charge to flow over the pinned (fixed) barrier  307  into the FD charge detection node. The potential of the FD node then changes from its reset level  308  to its signal level  309  depending on the amount of the transferred charge. 
         [0023]    The anti-blooming barrier at the level  312  is positioned such that charge can flow over it to the n+ doped JGP region and not over the barrier  303  into the SG well. The FD charge detection node is connected to the source follower SF transistor gate which buffers the signal that is then delivered to the analog to digital converters located at the periphery of the array. 
         [0024]    In general, when the potential of the wells are increased, the wells are lowered (i.e. deep wells), whereas when the potential of the wells are decreased, the wells are raised (i.e. shallow wells). Thus, the potential of the JGP well may be lowered and then raised to accumulate and then transfer charge to the SG. The potential of the SG barrier/well may be lowered to receive the transferred charge from the JGP, raised to temporarily store the charge, and then raised higher to transfer the charge over the barrier and into the FD. 
         [0025]    Shown in  FIG. 4 . are pixels that are connected in a  4 -PD shared configuration. The JGPs are the structures  401 ,  402 ,  403 , and  404  respectively. The junction gates of JGPs  401  and  402  are connected together to a single bus line  413 . Similarly, JGPs  403  and  404  are connected to a bus  414 . The charge clearing transistors are  405 ,  506 ,  407 , and  408  respectively. Their gates are connected to a single charge clearing bus  415 . The charge storage gates are indicated as transistors  409 ,  410 ,  411 , and  412  respectively, and are connected to a single FD charge detection node  423 . This node is also connected to the gate of the Source Follower (SF) transistor  417 . 
         [0026]    The reset of the FD is accomplished through reset transistor  416  that resets the FD to a reference voltage supplied by column bus line  421 . The SF drain is connected to the column power bus line  420  supplying drain voltage Vdd to the transistor. The row select transistor  418  then connects the output of the SF to the column signal output line  419 . The row bus line  427  controls the row select transistor and the row bus line  428  controls the gate of the reset transistor  416 . The remaining row bus lines  423 ,  424 ,  425 , and  428  supply the signal to the respective storage gates. 
         [0027]    The pixel can also have a ground column bus line  422 . Other connection alternatives are also possible. The particular circuit configuration is described here as an example of one possible embodiment. The possible layout implementation of the circuit in  FIG. 4  is shown in  FIG. 5  where the metal interconnects are omitted for clarity. 
         [0028]    Shown in  FIG. 5  is the top view of the pixel topology that describes the 4-shared JGP pixel configuration where metal vias  527  are shown as black dots. The regions  501 ,  502 ,  503 , and  504  are the JGP regions. The regions  505 ,  506 ,  507 , and  508  are storage gates with charge transfer barriers  509 ,  510 ,  511 , and  512  respectively interfacing with the JGPs. The pinned transfer barriers are regions  517 ,  518 ,  519 , and  520  that interface with floating diffusion regions  512  and  522 . The pixel isolation regions are regions  523  and the charge clearing CG transistors are structures  513  and  514  respectively. Also, the shared circuit components are reset transistor structure  525 , the SF transistor structure  526  and the addressing transistor structure  524 . 
         [0029]    The layout has a mirror symmetry in the y-pixel direction, that is compensated for by placing suitable electron barriers in the silicon bulk (not shown). Furthermore, the light shielding placed on the back-side of the sensor is placed in locations indicated by lines  528 . 
         [0030]    The wiring of the 4-shared JGP pixel layout from  FIG. 5 , is shown in  FIG. 6 . Metal line  601  is formed by a first metal layer M 1  and connects the floating diffusions  521  and  522  with the reset transistor  525  and with the gate of the source follower  526 . The reset gate row bus line  602  supplies the gate signal for the reset transistors, the line  603  for the junction gates  501  and  502 , the lines  604 , and  605  for the storage gates  507  and  508 . The clearing gate bus line is line  606 . Similarly lines  607  and  608  supply the signal to storage gates  503  and  504  respectively. Also, line  609  supplies the signal to JG  503  and  504 . 
         [0031]    The gates of the row select transistors are controlled by the signal supplied over line  610 . All the horizontal row lines are formed using the metal layer M 2 . The column metal lines are formed by the third metal layer M 3  and are as follows: line  611  is for the pixel output, line  612  is supplying the pixel ground bias, line  613  is supplying the pixel reference voltage, and line  614  is supplying the pixel drain bias. 
         [0032]    It is of course possible to use other wiring alternatives, the one shown in this embodiment is used as an example to illustrate the wiring complexity of the BSI image sensor with pixels that have global shutter capability. 
         [0033]    It is noted that in the global shutter mode, in general, all of the JGPs are simultaneously accumulating charge during an integration period. The charge is then transferred and stored under the SG during a storage period. The individual SGs may then pump the stored charge over the pinned barrier into the FD during a row by row readout period. 
         [0034]    It is also noted that various control voltages for controlling the CG, JGP, SG, and the imager in general, (e.g. reset control voltage, integration control voltage, storage control voltage, transfer control voltage, readout control voltage, etc.) may be generated and applied by a controller (e.g. Micro-processor) that is not shown in the figures. 
         [0035]    Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.