Abstract:
A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

Description:
FIELD  
         [0001]    The present disclosure relates generally to microprocessor systems, and more specifically to microprocessor systems capable of operating with a system bus at a different clock speed than the system memory.  
         BACKGROUND  
         [0002]    A common design consideration in modern digital systems is the use of clocks of differing clock frequencies in different portions of the system. One example of such a situation arises in microprocessor systems, where the system bus may utilize a clock at a different frequency than the clock utilized by system memory. Data read from memory at one clock frequency may need to be resynchronized to the clock frequency of the system bus. Data written into the memory, conversely, may need to be resynchronized from the clock frequency of the system bus to the clock frequency of the memory. The distinction may be made between source clock domains and destination clock domains. A source clock domain may describe the circuitry that generates a signal in accordance with a source clock, and a destination clock domain may describe the circuitry that receives that signal, but now in accordance with a destination clock. It is noteworthy that this distinction may change many times during the operation of the circuitry. A memory may be within the source clock domain during a data read transaction but may be within the destination clock domain during a data write transaction. Command pulses crossing the boundary from one domain to another may additionally change what is the source clock domain and destination clock domain. More generally, the process of resynchronizing a signal going from a source clock domain into a destination clock domain may be referred to as a clock-crossing scheme.  
           [0003]    Simple clock crossing schemes may utilize double synchronous flops in the destination clock domain to cross clock domains. Such methods may add unnecessary latency into the system timing. Therefore such a method may not be particularly attractive when used in higher speed systems, where any delays induced in clock crossing may impact various system latencies. An additional issue may arise with timing of events such as memory reads. If a time period before data signals are valid must be accounted for, when crossing over to the destination clock domain additional delays may be introduced by the clock crossing scheme.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]    The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:  
         [0005]    [0005]FIG. 1 is a schematic diagram of a multiprocessor system, according to one embodiment.  
         [0006]    [0006]FIG. 2 is a schematic diagram of a clock domain crossing circuit, according to one embodiment.  
         [0007]    [0007]FIG. 3 is a schematic diagram of a pulse accumulator, according to one embodiment of the present disclosure.  
         [0008]    [0008]FIG. 4 is a schematic diagram of a clock domain crossing circuit, according to one embodiment of the present disclosure.  
         [0009]    [0009]FIG. 5 is a timing diagram of the clock domain crossing circuit of FIG. 4, according to one embodiment of the present disclosure.  
         [0010]    [0010]FIG. 6 is a timing diagram of a dynamic read delay logic, according to one embodiment of the present disclosure.  
         [0011]    [0011]FIG. 7 is a schematic diagram of a dynamic read delay logic, according to one embodiment of the present disclosure.  
         [0012]    [0012]FIG. 8 is a schematic diagram of a clock domain crossing circuit, according to another embodiment of the present disclosure.  
         [0013]    [0013]FIG. 9 is a timing diagram of the clock domain crossing circuit of FIG. 8, according to one embodiment of the present disclosure.  
     
    
     DETAILED DESCRIPTION  
       [0014]    The following description describes techniques for resynchronizing signals crossing boundaries between source clock domains and destination clock domains. In the following description, numerous specific details such as logic implementations, software module allocation, bus signaling techniques, and details of operation are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation. The invention is disclosed in the form of a memory controller within a microprocessor system. However, the invention may be practiced in other forms of circuits that have multiple clock domains.  
         [0015]    Referring now to FIG. 1, a schematic diagram of a multiprocessor system  100  is shown, according to one embodiment. The FIG. 1 system may include several processors of which only two, processors  140 ,  160  are shown for clarity. Processors  140 ,  160  may include level one caches  142 ,  162 . The FIG. 1 multiprocessor system  100  may have several functions connected via bus interfaces  144 ,  164 ,  112 ,  108  with a system bus  106 . A general name for a function connected via a bus interface with a system bus is an “agent”. Examples of agents are processors  140 ,  160 , bus bridge  132 , and memory controller  134 .  
         [0016]    Memory controller  134  may permit processors  140 ,  160  to read and write from system memory  110  and from a basic input/output system BIOS erasable programmable read-only memory EPROM  136 . In some embodiments BIOS EPROM  136  may utilize flash memory. Memory controller  134  may include a bus interface  108  to permit memory read and write data to be carried to and from bus agents on system bus  106 . Memory controller  134  may also connect with a high-performance graphics circuit  138  across a high-performance graphics interface  139 . In certain embodiments the high-performance graphics interface  139  may be an advanced graphics port AGP interface, or an AGP interface operating at multiple speeds such as 4× AGP or 8× AGP. Memory controller  134  may direct read data from system memory  110  to the high-performance graphics circuit  138  across high-performance graphics interface  139 . It is noteworthy that bus interface  108 , system memory  110 , and high-performance graphics circuit  138  may each be in a different clock domain.  
         [0017]    Bus bridge  132  may permit data exchanges between system bus  106  and bus  116 , which may be a industry standard architecture ISA bus or a peripheral component interconnect PCI bus. There may be various input/output I/O devices  114  on the bus  116 , including low performance graphics controllers, video controllers, and networking controllers. Another bus bridge  118  may be used to permit data exchanges between bus  116  and bus  120 . Bus  120  may be a small computer system interface SCSI bus, an integrated drive electronics IDE bus, or a universal serial bus USB bus. Additional I/O devices may be connected with bus  120 . These may include keyboard and cursor control devices  122 , including mice, audio I/O  124 , communications devices  126 , including modems and network interfaces, and data storage devices  128 , including magnetic disk drives and optical disk drives. Software code  130  may be stored on data storage device  128 . In some embodiments memory controller  134  and bus bridge  132  may collectively be referred to as a chipset. In some embodiments, functions of a chipset may be divided among physical chips differently than as shown in the FIG. 1 embodiment.  
         [0018]    Referring now to FIG. 2, a schematic diagram of a clock domain crossing circuit  200  is shown, according to one embodiment. Clock domain crossing circuit  200  may be a portion of memory controller  134  of FIG. 1. Clock domain crossing circuit  200  may include a pulse generator  210 , an accumulator  220 , a clock domain crossing circuit  240 , a dynamic read delay logic  250 , a side queue  230 , and a demultiplexor logic  260 . The accumulator  220 , clock domain crossing circuit  240 , and dynamic read delay logic  250  are discussed in detail in connection with FIGS. 3, 4, and  7  below. FIG. 2 shows a memory clock Umclk domain and a databus clock Udclk domain. In this embodiment the Umclk domain is the source clock domain and the Udclk domain is the destination clock domain for read data coming from memory.  
         [0019]    Pulse generator  210  may generate read data pulses, responsive to a memory read command, that may indicate when to sample read data coming from memory. The data pulse generation for each read command that is launched may depend upon an input signal  212  that may in some embodiments include the read command pulse itself, the burst length, the cycle length, and on selective commands per clock CPC (if applicable). The data pulse generation may also depend upon a DRAM type signal input  214  that may in one embodiment identify the kind of dynamic random-access memory DRAM used as system memory  110 . The data pulse may have no knowledge of details of DRAM operation, such as the column access strobe CAS timing and the time until read data is valid T RD . Pulse generator  210  may generate pulses having a timing such that all chunks of data returned from the system memory  110  for a given cycle type and burst length will be valid a clock period after that pulse is sampled high. In one embodiment, if the read command is launched during clock K, then the read data pulse may be launched relative to K as given below in Table I.  
                           TABLE I                       CYCLE LEN.   DRAM   BURST LEN.   PULSE TIMING                   16 bits   SDK   4   K + 1       32 bits   SDR   4   K + 3       16 bits   DDK   4/8   K       32 bits   DDK   4/8   K + 1       64 bits   DDK   8   K + 1, K + 3                  
 
         [0020]    Here SDR is single data rate DRAM and DDR is dual data rate DRAM. An additional parameter that may affect the data pulse timing is selective CPC for 2×16 bits read commands, generally applicable to DDR. In one embodiment the effect of selective CPC on read data pulse timing-may be as given below in Table II.  
                               TABLE II                                   DRAM   SELECTIVE CPC   PULSE TIMING                           SDR   must be OFF   K + 3           DDK   set OFF   K + 2           DDR   set ON   K + 1                      
 
         [0021]    Side queue  230  may be used to convey portions of the input signal  212  to the demultiplexor logic  260 . In one embodiment, the portions send through side queue  230  may include cycle length, burst length, and destination device. Demultiplexor logic  260  may then use this information in conjunction with the clock-crossed data pulse to form a device-specific read data pulse. Examples of these may include a data bus read data pulse (DBdnput  262 ), a high-speed graphics read data pulse (DClhpdnput  264 ), and a low-speed graphics read data pulse (Dcllpdnput  266 ).  
         [0022]    Referring now to FIG. 3, a schematic diagram of a pulse accumulator  220  is shown, according to one embodiment of the present disclosure. Accumulator  220  may include an increment/decrement logic  310 , a wide latch  320 , a multiplexor  340 , an incrementor  360 , and a decrementor  350 . The wide latch  320  may in one embodiment be either 4 or 8 bits wide, with a common clock connection. Wide latch  320  may contain the current count of the number of outstanding data pulses that have not yet been crossed over from the source clock domain to the destination clock domain. Incrementor  360  may increment the number stored in wide latch  320  and present it to an input of multiplexor  340 . Similarly, decrementor  350  may decrement the number stored in wide latch  320  and present it to another input of multiplexor  340 .  
         [0023]    When a pulse enters increment/decrement logic  310  on pulse signal line  216 , the increment/decrement logic  310  may set a multiplexor select signal  342  to select the output from incrementor  360  to pass from multiplexor  340  and update the contents of wide latch  320 . When a pulse has been crossed over from the source clock domain to the destination clock domain, then a get signal on get signal line  224  may be sent to increment/decrement logic  310 . Increment/decrement logic  310  may then set a multiplexor select signal  342  to select the output from decrementor  350  to pass from multiplexor  340  and update the contents of wide latch  320 . A get signal on get signal line  224  may additionally permit the increment/decrement logic  310  to release a pulse as an available mclk pulse over available mclk pulse signal line  222 . When neither a pulse nor a get signal arrive at increment/decrement logic  310 , then the current contents of wide latch  320  are retained.  
         [0024]    Referring now to FIG. 4, a schematic diagram of a clock domain crossing circuit  240  is shown, according to one embodiment of the present disclosure. Available mclk pulses arrive over available mclk pulse signal line  222 . These available mclk pulses are routed to the data inputs of latch components  412 ,  414 ,  416 ,  418  of latch  410 . The clock crossing circuit  240  generally may require a quantity of latch components m when m is the number of destination clock phases available per source clock phase present in a given embodiment.  
         [0025]    The source clock clocking signals are presented in two components, the clock itself Umclk routed on Umclk signal line  444  and a phase indicator signal Umphase routed on Umphase signal line  440 . Umphase signal line  440  may be 1, 2, or more bits wide in various embodiments. In the FIG. 4 embodiment Umphase signal line  440  is 3 bits wide. The Umphase signal line  440  is presented to the selector inputs of multiplexors  420 ,  424 ,  428 ,  432 . The multiplexors  420 ,  424 ,  428 ,  432  are used as selectors in the FIG. 4 embodiment, but in other embodiments other circuit elements may be used as selectors. Each of multiplexors  420 ,  424 ,  428 ,  432  may have as inputs phase enable signals mphase en 0 , mphase en 1 , mphase en 2 , and mphase en 3 . In one embodiment these phase enable signals may be determined through an analysis taking into account differences in process variation, operating temperature, and operating voltage. In the FIG. 4 embodiment the phase enable signals mphase en 0 , mphase en 1 , mphase en 2 , and mphase en 3  may be read from a register that is loaded from a BIOS, but in other embodiments may be stored in differing ways including as software code on a data storage device.  
         [0026]    Each of the latch components  412 ,  414 ,  416 ,  418  of latch  410  corresponds to a particular phase of Udphase, as assigned by their connection to multiplexor  450 . Here multiplexor  450  is one example of a selector circuit. In other embodiments, the selector circuit used may be of another type. The inputs of multiplexor  450  are selected by phase indicator signal Udphase routed on Udphase signal line  542 . Hence the output Q of latch component  412  is connected to the “0” input of multiplexor  450 , selected when in phase “0” of Udphase. Similarly the Q outputs of latch components  414 ,  416 ,  418  correspond to the “1”, “2”, and “3” phases of Udphase, respectively.  
         [0027]    Therefore, the various mphase enx signals may relate the permissibility of available mclk pulses occurring within a particular Umphase to cross over to a corresponding Udphase of the destination clock, Udclk. Available mclk pulses crossing over to, for example, phase “0” of Udphase, generally go through latch component  412 . Therefore the combination of Umclk and the phase enable signal mphase en 0 , combined by gate  422 , determine whether or not a given available mclk pulse may be latched into latch component  412 . Similar considerations apply to latch components  414 ,  416 ,  418 .  
         [0028]    Referring now to FIG. 5, a timing diagram of the clock domain crossing circuit  240  of FIG. 4 is shown, according to one embodiment of the present disclosure. Here the ratio of frequencies of the source clock mclk to the destination clock dclk is 4 to 3. In other embodiments, other ratios could be used. Available mclk pulses arriving during Umphase “0” may be crossed over to an available dclk pulse during the next Udphase “1”. Available mclk pulses arriving during Umphase “1” may be crossed over to an available dclk pulse during the next Udphase “2”. Available mclk pulses arriving during Umphase “2” may be crossed over to an available dclk pulse during the next Udphase “0”. However, available mclk pulses arriving during Umphase “3” may not be crossed over to an available dclk pulse during the next Udphase “0”, and should be crossed over into a later phase of Udphase.  
         [0029]    Referring now to FIG. 6, a timing diagram of a dynamic read delay logic is shown, according to one embodiment of the present disclosure. A memory read transaction is initiated, in one example for a 32 bit read, by generating a pulse  610  on chip select CS# signal line. A corresponding read data pulse  614  in the Umclk domain is generated in response. By measurement or circuit simulation, and taking into account variations in process, voltage, and temperature, it may be determined that the read data from memory may be safely sampled after a delay time t 0  subsequent to the initial edge of pulse  610 .  
         [0030]    However, pulse  610  is in the Umclk domain. Upon crossing read data pulse  614  from Umclk domain to form read data pulse  618 , a different delay time t rd  should be determined. Here the delay time t rd  is the time subsequent to the rising edge of read data pulse  618  when the read data may be safely sampled. The delay time t rd  may be determined by counting forward N cycles of the Udclk, where 
           N (Φ)=greatest integer (( t 0 −tckxss (Φ))/(frequency of  Udclk ))+1. 
         [0031]    Here tckxss(Φ) may be dependent on the launch phase of Umclk and the aggressiveness of the clock crossing programming (e.g. the values of the mphase emx). In certain combinations of source clock and destination clock phases, where there is a larger time delay induced in the clock crossing, it may be possible to reduce the above value of N(Φ) by 1 or more.  
         [0032]    Using the above equation for calculating values of N(Φ), it is possible to calculate a set of values for various combinations of t rd  and the phases of Umclk in which the read transaction is initiated. This set of values may in one embodiment be stored in BIOS in a lookup table format. Based upon the destination clock to source clock ratio and the t rd  value, the BIOS stored values for N(Φ) and for any adjustments needed for t rd , called t rd-adjust , may be programmed into a register within the memory controller. A control logic implementation, for one embodiment as shown in FIG. 7 below, may ensure by utilizing the t rd-adjust  that there is no clobbering of previously valid data by unadjusted read data.  
         [0033]    Referring now to FIG. 7, a schematic diagram of a dynamic read delay logic  250  is shown, according to one embodiment of the present disclosure. Dynamic read delay logic  250  may ensure that the value of N(Φ), corresponding to a desired value of t rd  , may be adjusted down by 1 if two conditions are met. The first condition is that the programming values of t rd-adjust  permit the adjustment in the corresponding phase of Udphase. The second condition is that the available dclk pulse does not follow a previous dclk pulse that occurred in a cycle of Udclk immediately before the available dclk pulse. It should be noted that all clock inputs shown in FIG. 7 are connected to Udclk, with individual clock signals not shown for clarity.  
         [0034]    The value of N(Φ) to be used arrives at inputs to the multiple gates  710 . In one embodiment, the value of N(Φ) is 4 bits and there are a corresponding 4 gates  710 . When an available dclk pulse is latched into latch  712 , then the value of N(Φ) is presented to the four I 0  inputs of selector  714 , and decrementor  716  presents N(Φ)−1 to the four I 1  inputs of selector  714 . The value of the 4 bits wide output of gate  728  determines whether N(Φ) or N(Φ)−1 is used to count out dclk cycles to form t rd  in a given circumstance.  
         [0035]    The 2 bits of Udphase  452  may be clocked into the latch elements of latch set  720 . Thus the current value of Udphase  452  may select the appropriate value of t rd-adjust  to appear at the output of multiplexor  722  to determine whether or not it would be appropriate to permit the decrementing of N(Φ). If the output  732  of multiplexor  722  is true, this corresponds to the truth of the first condition: that the programming values of t rd-adjust  permit the adjustment in the corresponding phase of Udphase.  
         [0036]    Latch  726  generally contains the presence or absence of an available dclk pulse from the immediately preceding dclk cycle time period. If the output  730  of  726  is true, this corresponds to the truth of the second condition: that the available dclk pulse does not follow a previous dclk pulse that occurred in a cycle of Udclk immediately before the available dclk pulse.  
         [0037]    If both the outputs  730 ,  732  are true, then the 4 bits wide output of selector  714  is N(Φ)−1, otherwise the output of selector  714  is N(Φ). In either case, a value is placed into priority encoder  740 . The outputs of priority encoder  740  may be labeled LD 2  through LD 9 . If the input of priority encoder is 0000 binary, then none of the outputs are set low. However, if the input of the priority encoder is x binary, then output LDx is lowered. This causes a pulse to be initiated in the 8 latches  750  through  764 , that collectively form a shift register. The farther down the shift register the pulse is injected, the longer the delay t rd  will be, as t rd  will be either N(Φ) or N(Φ)−1 cycles of dclk in length.  
         [0038]    Referring now to FIG. 8, a schematic diagram of a clock domain crossing circuit  800  is shown, according to another embodiment of the present disclosure. The clock domain crossing circuit  800  is similar to that shown in 4, but crosses in the opposite direction. In the FIG. 8 embodiment, the dclk is the source clock and the mclk is the destination clock. In the FIG. 8 example, the ratio of mclk frequency to dclk frequency is 5 to 4.  
         [0039]    Multiplexor  840  may have 5 inputs, corresponding to the 5 phases of Umphase input on Umphase signal line  440 . This requires the 5 latch components  822 ,  824 ,  826 ,  828 ,  830  of latch  820 . The data inputs of latch components  822 ,  824 ,  826 ,  828 ,  830  are connected to the pulse coming from the dclk domain, event dclk on event dclk signal line  810 . In a similar manner to the phase enable signals of FIG. 4, the phase enable signals dphase en 0  through dphase en 4  may be determined by measurement or simulation, and stored in a BIOS. The BIOS values may then be loaded into a register within the memory controller.  
         [0040]    Again the latch components  822 ,  824 ,  826 ,  828 ,  830  correspond to specific phases of the destination clock Umphase  440 . The various dphase enx signals may relate the permissibility of available dclk pulses occurring within a particular Udphase to cross over to a corresponding Umphase of the destination clock, Umclk. Available dclk pulses crossing over to, for example, phase “0” of Umphase, generally go through latch component  822 . Therefore the phase enable signal dphase en 0 , clocked through latch  852  by Udclk  880 , determines whether or not a given available dclk pulse may be latched into latch component  822 . Similar considerations apply to latch components  824 ,  826 ,  828 ,  830 . The output of the latch corresponding to the current Umphase will exit the multiplexor  840  as a clock crossed event mclk pulse on event mclk signal line  814 .  
         [0041]    Referring now to FIG. 9, a timing diagram of the clock domain crossing circuit of FIG. 8 is shown, according to one embodiment of the present disclosure. The Umphase and Udphase signals are shown. If event A has a transition at  910 , then it may be crossed into Umphase “1” at  912 . If more conservative timing was selected, the event could be crossed into Umphase “2” at  914 . Then when event B has a transition at  920 , it may be crossed into Umphase “3” at  922 . Similarly event C with a transition at  930  could be crossed into Umphase “4” at  932 , and event D with a transition at  940  could be crossed into a next occurring Umphase “0” at  942 . The output event mclk is shown as having the 4 pulses  914 ,  924 ,  934 , and  944 .  
         [0042]    In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.