Abstract:
An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes-wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures. Performing chip testing with the substrate voltage level more positive than the normal negative voltage level facilitates detection of other margin failures and ion contamination.

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application is a division of U.S. application Ser. No. 09/065,139, filed on Apr. 23, 1998, now U.S. Pat. No. 6,304,094, which is a division of U.S. application Ser. No. 08/520,818, filed on Aug. 30, 1995, now issued as U.S. Pat. No. 5,880,593, the specifications of which are hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to on-chip testing circuits. More specifically, this invention relates to on-chip substrate voltage regulators for use during defect testing. 
     BACKGROUND OF THE INVENTION 
     During testing for margin defects in packaged semiconductor integrated circuit chips, it is desirable to vary the voltage level of the substrate from its normal negative operating level. One method is to set the substrate voltage level to ground. However, setting the substrate voltage level to ground during testing of some types of chips, such as 16-megabyte memory chips, may be an unrealistic testing condition because some chips that fail the testing process would operate satisfactorily with a negatively biased substrate. What is needed is an on-chip substrate regulator with the ability to vary the substrate voltage level during testing to be more positive or more negative than its normal negative operating level while maintaining the substrate voltage level below ground. 
     SUMMARY OF THE INVENTION 
     An on-chip circuit provides the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are coupled to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The chain is nominatively referred to as a diode chain The substrate is coupled to a second end of the diode chain. The substrate voltage level is equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate at the voltage level set by the diode chain. 
     A first plurality of MOSFETs in the diode chain are configured to be normally shorted. When these MOSFETs are controlled to change from a shorted condition to a condition of operating as diodes or resistive elements, the substrate level becomes more negative due to the added voltage drop. A second plurality of MOSFETs in the diode chain are configured to operate normally as diodes or resistive elements. When these MOSFETs are controlled to change from operating as diodes or resistive elements to a shorted condition, the substrate level becomes more positive due to the removed voltage drop. A third plurality of MOSFETs are coupled as switches to control whether the MOSFETs in the first and second pluralities of MOSFETs are shorted or are operating as diodes when it is desired to vary the substrate voltage level during testing. 
     Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures. Performing chip testing with the substrate voltage level more positive than the normal negative voltage level facilitates detection of other margin failures and ion contamination. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit diagram of the present invention having two control lines. 
     FIG. 2 shows a circuit diagram of the present invention having four control lines. 
     FIG. 3 shows a circuit diagram of the present invention having two unused MOSFETs. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In one embodiment of FIG. 1, a memory device  100  such as memory chip is shown having an array of memory cells  110 . The invention is, however not limited to embodiments that include a memory device. Referring to FIG. 1, Vcc is a supply voltage level. An n-channel MOSFET M 1 , has its gate coupled its drain. The drain of M 1  and the gate of M 1  are coupled to the supply voltage level Vcc. An n-channel MOSFET M 2 , has its gate coupled to its drain. The gate and drain of M 2  are coupled to the source of M 1 . An n-channel MOSFET M 3 , has its gate coupled to its drain. The gate of M 3  and the drain of M 3  are coupled to the source of M 2 . An n-channel MOSFET M 41  has its drain coupled to the drain of M 3 . The source of M 4  is coupled to the source of M 3 . The gate of M 4  is coupled to be controlled by a control voltage level EN 1 . An n-channel MOSFET M 5 , has its gate coupled to the gate of M 3 . The drain of M 5  is coupled to the source of M 3 . The source of M 5  is coupled to a substrate node Vbb. An n-channel MOSFET M 6 , has its drain coupled to the drain of M 5 . The source of M 6  is coupled to the source of M 5  and to the substrate node Vbb. The gate of M 6  is coupled to be controlled by a control voltage level EN 2 . The substrate node Vbb, is coupled to the substrate of a integrated circuit chip on which the substrate voltage regulator circuit is contained. 
     The MOSFETs M 1 , M 2 , M 3 , M 5  are coupled in a chain to operate as resistive elements having a non-linear resistance. As is well known, these elements can also be considered to be diodes. Each element in the chain may cause a voltage drop across the terminals of that element. Such a chain is referred to hereinafter as a diode chain. If appropriately configured, a portion of the supply voltage level Vcc, will be dropped across the drain and source of each of the MOSFETs M 1 , M 2 , M 3 , M 5 . The MOSFET M 4 , acts as a switch to insert the voltage drop across the drain and source of the MOSFET M 3  into the diode chain or to remove the voltage drop across the drain and source of MOSFET M 3  from the diode chain depending upon the control voltage level EN 1 . When the voltage EN 1  is at a logical high, the MOSFET M 4  is turned on and M 3  is essentially shorted out of the diode chain. Only the saturation voltage for the MOSFET M 4  will appear across the terminals of the MOSFET M 3 . When the voltage EN 1  is at a logical low, the MOSFET M 4  is turned off and MOSFET M 3  is in the diode chain. In this mode, the voltage drop across the MOSFET M 3  will add to the voltage drop in the chain. 
     The MOSFET M 6 , similarly acts as a switch to insert the voltage drop across the drain and source of MOSFET M 3  into the diode chain or to remove the voltage drop across the drain and source of MOSFET M 3  from the diode chain depending upon the control voltage level EN 2 . When EN 2  is at a logical high, the MOSFET M 6  is turned on and the MOSFET M 5  is essentially shorted out of the diode chain. When EN 2  is at a logical low, the MOSFET M 6  is turned off and the voltage drop across the MOSFET M 5  is included in the diode chain. 
     A charge pump circuit CP, has its input coupled to the source of the MOSFET M 1 , to the gate of the MOSFET M 2 , and to the drain of the MOSFET M 2 . The output of the charge pump CP is coupled to the substrate node Vbb. The charge pump CP maintains the voltage level of the substrate at the level set by the diode chain. The substrate voltage level is substantially equivalent to the supply voltage Vcc, less any voltage drops across the drain and source of each of the MOSFETs M 1 , M 2 , M 3  and M 5  which are not shorted out of the chain. 
     Under normal operating conditions, when the integrated circuit chip is not being tested, the substrate is usually maintained at a negative level. Depending on the requirements of the particular integrated circuit chip, the substrate level is typically in the range of 1.5 to 2.0 volts below ground level, but may be higher or lower. The substrate voltage level for normal operating conditions is determined by the presence of voltage drops across the drain and source of MOSFETs in the diode chain. In order to have the ability to set the substrate voltage to a level either more positive or more negative than the normal negative voltage level of the substrate, it is desirable to have the ability to add voltage drops into the diode chain or to remove voltage drops from the diode chain. 
     For example, in FIG. 1, the non-test condition of EN 1  may be at a logical low so that the MOSFET M 3  is in the diode chain because the MOSFET M 4  is off. The non-test condition of EN 2  may be at a logical high so that the MOSFET M 5  is essentially shorted out of the diode chain because the MOSFET M 6  is on. Therefore, the voltage level of the substrate at node Vbb, under non-test conditions, is substantially equivalent to the supply voltage level Vcc, less the voltage dropped by the three MOSFETs M 1 , M 2  and M 3 . Under test conditions, the voltage level at node Vbb can be made more positive by raising the control signal EN 1  to a logical high. Such an enabling of the control signal EN 1  turns on the MOSFET M 4  which essentially shorts the channel of the MOSFET M 3  thereby removing the MOSFET M 3  from the diode chain, so that the voltage level at Vbb is substantially equivalent to the supply voltage level Vcc, less the voltage dropped by only the MOSFETs M 1  and M 2 . The normal substrate voltage level at Vbb can then be restored by returning the control voltage EN 1  to a logical low. 
     As another test condition, the substrate voltage level Vbb, can be made more positive than its normal negative voltage level by lowering the control voltage EN 2  to a logical low. Such a disabling of the control signal EN 2  cuts off the MOSFET M 6  and includes the MOSFET M 5  in the diode chain. Under these conditions, Vbb is substantially equivalent to the supply voltage level Vcc, less the voltage dropped by the MOSFETs M 1 , M 2 , M 3  and M 5 . 
     There may be test conditions where it is desired to only be able to change the voltage level at Vbb to make Vbb more positive. Under such conditions, the control signals EN 1  and EN 2  can both have a non-test condition of a logical low. Then the substrate voltage level Vbb, can be made more positive by raising either the control signal EN 1  or the control signal EN 2 . To make Vbb even more positive, both the control signals EN 1  and EN 2  can both raised to a logical high. 
     Conversely, if it is desired to only be able to change the voltage level at Vbb to make Vbb more negative during a testing operation, both the control signals EN 1  and EN 2  can have a non-test condition of a logical high. Then the substrate voltage level Vbb, can be made more negative by lowering either the control signal EN 1  or the control signal EN 2 . To make Vbb even more negative, both the control signal EN 1  and the control signal EN 2  can be configured to a logical low. 
     FIG. 2 shows the invention as shown in FIG. 1 except as noted below. The diode chain of FIG. 2 has two additional n-channel MOSFETs M 7  and M 9  in the diode chain and two additional n-channel MOSFETs M 8  and M 10  operating as switches. Rather than being coupled to the substrate node Vbb, as in FIG. 1, the source of the MOSFET M 5  is coupled to the drain of the MOSFET M 7  in FIG.  2 . Rather than being coupled to the substrate node Vbb, as in FIG. 1, the source of the MOSFET M 6  is coupled to the drain of M 8  in FIG.  2 . The drain of the MOSFET M 7  is coupled to the drain of the MOSFET M 8 . The gate of the MOSFET M 8  is coupled to be controlled by a control voltage level EN 3 . The source of the MOSFET M 8  is coupled to the drain of the MOSFET M 10 . The source of the MOSFET M 10  is coupled to the substrate node Vbb. The gate of the MOSFET M 10  is coupled to be controlled by a control voltage level EN 4 . The source of the MOSFET M 7  is coupled to the drain of the MOSFET M 9 . The drain of the MOSFET M 9  is coupled to the drain of the MOSFET M 10 . The source of the MOSFET M 9  is coupled to the substrate node Vbb. The gate of the MOSFET M 7  and the gate of the MOSFET M 9  are coupled to the gate of the MOSFET M 5  and to the gate of the MOSFET M 3 . The MOSFET M 8 , operates as a switch to add the voltage drop across the drain and the source of the MOSFET M 7  to the diode chain or to remove the voltage drop across the drain and the source of the MOSFET M 7  from the diode chain. The MOSFET M 10 , operates as a switch to add the voltage drop across the drain and the source of the MOSFET M 9  to the diode chain or to remove the voltage drop across the drain and the source of the MOSFET M 9  from the diode chain. 
     The addition of the MOSFETs M 7 , M 8 , M 9  and M 10  to the circuit increases the adjustability of the substrate voltage level Vbb, beyond that of the circuit shown in FIG.  1 . For example, the non-test condition for the control signals EN 1  and EN 2  may be a logical low so that the MOSFETs M 3  and M 5  are in the diode chain. The non-test condition for the control signals EN 3  and EN 4  may be a logical high so that the MOSFETs M 7  and M 8  are essentially shorted out of the diode chain. Under test conditions, the substrate voltage level Vbb may be made more positive by raising the control signal EN 1  to a logical high and essentially shorting the MOSFET M 3  out of the diode chain. The substrate voltage level Vbb can then be made even more positive by raising the control signal EN 2  to a logical high and essentially shorting the MOSFET M 5  out of the diode chain, as well. The normal substrate voltage level at Vbb can then be restored by returning the control signals EN 1  And EN 2  to a logical low. The substrate voltage level Vbb, can be made more negative from its non-test condition by lowering the control signal EN 3  to a logical low and thereby adding the MOSFET M 7  to the diode chain. The substrate voltage level Vbb, can then be made even more negative by lowering the control signal EN 4  to a logical low and adding the MOSFET M 9  to the diode chain. 
     Alternatively, the normal, non-test substrate voltage level at Vbb can be set by raising or lowering the control voltage levels EN 1 , EN 2 , EN 3  and EN 4  in any combination. Then, under test conditions, the substrate voltage level Vbb, can be adjusted by controlling the control signals EN 1 , EN 2 , EN 3  and EN 4 . For example, the control signals EN 1  and EN 2  can be coupled together and the control signals EN 3  and EN 4  can be coupled together. The non-test substrate voltage level Vbb, may be set by raising the control signal pair of EN 1  and EN 2  to a logical high and by lowering the control signal pair EN 3  and EN 4  to a logical low. Then, under test conditions, the substrate voltage level Vbb, can be made more positive by raising the control signal pair EN 3  and EN 4  to a logical high or the substrate voltage level Vbb can be made more negative by lowering the control signal pair EN 1  and EN 2  to a logical low. 
     FIG. 3 shows another embodiment of the present invention wherein two n-channel MOSFETs M 7 , M 9  are hard wired to be shorted out of the diode chain. The circuit in FIG. 3 has the same structure as the circuit in FIG. 2, except as noted below. The drain of the MOSFET M 7 , the source of the MOSFET M 7 , the drain of MOSFET M 9 , the source of the MOSFET M 9 , the source of the MOSFET M 5  and the source of the MOSFET M 6  are coupled to the node Vbb. The gate of the MOSFET M 7  is coupled to the gate of the MOSFET M 9  and to the gate of the MOSFET M 3  and to the gate of the MOSFET M 5 . The MOSFETs M 8  and M 10  are absent. This circuit configuration operates as the circuit shown in FIG. 1, but can be conveniently modified to operate as the circuit shown in FIG. 2 by adding the MOSFETs M 8  and M 10  as shown in FIG.  2 . 
     The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention. Specifically, it will be apparent to one of ordinary skill in the art that the method of the present invention could be implemented in many different ways and the apparatus disclosed above is only illustrative of the preferred embodiment of the present invention. For example, a diode chain could be constructed having any number of MOSFETs as non-linear resistors and any number of MOSFETs as switches, other devices such as resistors or diodes may be used to drop voltages in the diode chain, or p-channel MOSFETs may be used in the circuit as diodes or switches, or the charge pump may be coupled to a different junction of elements in the diode chain.