Abstract:
Method, system and computer-executable code are disclosed for synthesizing a representation of a circuit into a new circuit representation having greater unateness. The invention includes partitioning a circuit representation to obtain a representation of at least one sub-circuit, recursively decomposing the representation of the at least one sub-circuit into a sum-of-products or product-of-sums representation having greater unateness than the representation of the at least one sub-circuit, merging the sum-of-products or product-of-sums representation into the circuit representation to form a new circuit representation, and repeating until a desired level of unateness for the new circuit representation is achieved. Algebraic division is implemented to merge common expressions of the sum-of-products or product-of-sums representations. A zero-suppressed binary decision diagram is implemented to recursively decompose the representation of the sub-circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application claims the benefit of U.S. provisional application Serial No. 60/226,103, filed Aug. 17, 2000 and entitled “Method and System for Synthesizing Digital Circuits with Unateness Properties.” 
     
    
     GOVERNMENT RIGHTS  
       [0002] This invention was made with government support under National Science Foundation Grant Nos. 9503463 and 9872066 and DARPA Grant No. DABT 63-96-C-0074. The government has certain rights in this invention. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0003]    1. Field of the Invention  
           [0004]    This invention relates to a method and system for synthesizing a circuit representation of a circuit into a new circuit representation having greater unateness.  
           [0005]    2. Background Art  
           [0006]    The number of transistors that can be fabricated in a single IC has been growing exponentially over the last three decades. A well-known example is the Intel series of microprocessors. Intel&#39;s first commercial microprocessor, the 4004, was built with 2,300 transistors in 1971, whereas a recent Intel microprocessor, the Pentium III, introduced in 1999 contains 9.5 million transistors. The clock frequency of the microprocessors also has dramatically increased from the 4004&#39;s 0.1 MHZ to the Pentium III&#39;s 550MHz. The 1998 International Technology Roadmap for Semiconductors developed by the Semiconductor Industry Association (SIA) predicts that the transistor count and the clock frequency of ICs will grow even faster in the next decade.  
           [0007]    It is thus becoming extremely difficult and time-consuming to design all the components in a complex IC from scratch, verify their functional and timing correctness, and ensure that overall performance requirements are met. To solve this challenging problem, a “design reuse” methodology is being widely introduced, which integrates large standardized circuit blocks into a single IC called a system on a chip (SOC). An SOC integrates a set of predesigned “off-the-shelf” blocks to build the entire system on a single chip, just as off-the-shelf IC&#39;s have been used to build a system on a board. The SOC methodology allows IC designers to focus on the interfaces linking the predesigned blocks. Thus it saves a tremendous amount of time that the designers would have spent creating all the blocks from scratch, and verifying their correctness. For this reason, the SOC design approach is becoming increasingly popular.  
           [0008]    A large portion of the reused blocks in an SOC are intellectual property (IP) circuits, which are also called cores or virtual components, and are often provided by third party vendors. The IP providers typically transfer their designs to SOC designers in a way that hides the key design details of the IP circuits and so protect the IP provider&#39;s investment in the IP designs. The IP circuits that have been developed so far cover numerous functions and support many different IC technologies. Additionally, the number and scope of the available IP circuits are rapidly growing.  
           [0009]    IP circuits are currently available in three different forms known as hard, soft, and firm. Hard IP circuits are provided in the form of complete layouts that are optimized and verified by the IP providers for a particular IC technology. Therefore, hard IP circuits can save time in all SOC design steps, but cannot be reoptimized by system designers for other technologies. The intellectual property of hard IP circuits includes all the implementation details and is protected by providing the system designers only with the circuit&#39;s high-level behavioral or functional specifications. Soft IP circuits are provided in the form of register-transfer level (RTL) descriptions, which define the circuit&#39;s behavior using a set of high-level blocks. These blocks can be converted by system designers to lower-level designs at the gate and physical levels. Thus soft IP circuits can be optimized for a variety of IC technologies and performance requirements, while they can save SOC design time in the high-level design and verification steps. Their RTL designs are considered to be the intellectual property contents of soft IP circuits. Finally, firm IP circuits are provided as netlists or gate-level descriptions. They allow the system designers to optimize the IP circuit&#39;s physical design such as cell placement and routing for various IC technologies. They provide the major advantages of both hard and soft IP circuits—they save system design time while allowing the flexibility of retargeting the IP circuits at various IC technologies. Both their RTL and gate-level designs are considered to be the intellectual property contents of firm IP circuits. While hard IP circuits are primarily aimed at ASIC designs, some soft and firm IP circuits are aimed at SOCs implemented using field programmable gate array (FPGA) technology.  
           [0010]    Although the advancement of IC technology allows extremely large designs to be integrated in a single chip, today&#39;s IC technology presents major challenges to the existing design and testing methodologies. For example, testing requirements for complex digital circuits are becoming increasingly tighter. Using traditional processes to synthesize the implementation of digital and other circuits often leads to circuits that are either inefficient in meeting testing requirements (i.e., unreasonably large test sets, etc.) or cannot satisfy design constraints (i.e., delay, area limits, etc.).  
           [0011]    The unateness of a circuit has a substantial impact on circuit testability and performance. Unate variables of a circuit representation z are variables that appear only in complemented or uncomplemented form in z&#39;s minimal two-level expressions such as sum of products (SOP) or product of sums (POS) expressions; binate variables are non-unate. For example, z 1 =a{overscore (b)}+a{overscore (c)}+bcd is a minimal SOP expression for the four-variable function z 1 , in which a and d are unate, and b and c are binate.  
           [0012]    The majority of circuit representations are, in nature, binate, and it is often difficult to synthesize these binate functions into a circuit implementation that can be efficiently tested for manufacturing defects and operate at very high speeds.  
           [0013]    For example, a high-speed circuit implementation known as “domino logic” requires that the circuit to be implemented be unate. Therefore, binate circuit functionality to be implemented in domino logic must be decomposed into unate circuit implementations. Similarly, static CMOS logic implementations become efficient if unate circuit implementations are extracted from an original binate circuit prior to implementation. Datapath logic circuits such as adders, subtractors, comparators, and ALUs are good examples of applications where carry generation functions (i.e., unate functions) are extracted from a larger (often binate) function and implemented in high-speed circuit structures.  
           [0014]    Another advantage of unate circuit implementations is their relatively small universal test set (i.e., the set of minimal true and maximal false test vectors for a function z). These test vectors have the useful property that they can detect all multiple stuck-at faults in any implementation of z. Universal test sets guarantee a very high coverage of manufacturing defects in a vast range of implementations for given circuit functionality. The universal test sets for binate circuit implementations tend to become excessively large. In addition, the unateness property enables the generation of test vectors from the behavioral functions of circuits before their implementations are actually executed.  
           [0015]    Existing functional decomposition processes are not suited to the goal of decomposing a binate circuit representation into a small set of unate subfunctions. One existing functional decomposition process called kernel extraction is aimed at multi-level logic synthesis. The kernels of a circuit representations are defined as f&#39;s cube-free primary divisors or quotients. For example, the kernels of f=(a+b+c)(d+e)f+bfg+h include d+e, d+e+g, and a+b+c. This decomposition process employs algebraic division operations with the kernels serving as divisors or quotients to f. Here algebraic division represents f by a logic expression of the form f=p·q+r. The kernels of f can be binate, so f&#39;s subfunctions p, q, and r can also be binate. In addition, kernel extraction often leads to an excessive number of subfunctions, and so is not practical for unate decomposition.  
           [0016]    Another existing decomposition process is Boole-Shannon expansion, which represents circuit implementation f by xf x +{overscore (x)}f {overscore (x)}  where f x  is the cofactor of f with respect to x. Cofactor f x  is defined as the subfunction of f obtained by assigning 1 to variable x in f Boole-Shannon expansion has been widely used for binary decision diagram (BDD) construction, technology mapping and field programmable gate array synthesis. Boole-Shannon expansion is unsuited to the goal of obtaining a small set of unate circuit implementations, however, since it may only make the child functions f x  and f {overscore (x)}  unate, while always expressing the parent function in a binate form. When applied repeatedly, Boole-Shannon expansion can also produce an unnecessarily large number of subfunctions, as each is created by eliminating only one binate variable at a time.  
           [0017]    Finally, a disjoint or disjunctive decomposition represents a boolean function f(X, Y) in the form h(g 1 (X 1 ), g 2 (X 2 ), . . . , g k (X k ), Y), where X 1 , X 2 , . . . , X k , and Y are disjoint (i.e., non-overlapping) variable sets. This decomposition is relatively easy to compute, and is sometimes used for logic synthesis problems where the interconnection cost dominates the circuit&#39;s overall cost. It has the drawback that many circuit representations cannot be disjointly decomposed, and, like Boole-Shannon expansion, it can make the parent function h binate. Thus, the disjoint decomposition technique is also not appropriate for our unate decomposition goal.  
         SUMMARY OF THE INVENTION  
         [0018]    One object of the present invention is to provide a method and system for efficiently synthesizing a circuit representation into a new circuit representation (i.e., circuit implementation) having greater unateness. Notably, those of ordinary skill in the relevant art will appreciate that the present invention may be implemented or applied in a variety of circumstances to synthesize circuits beyond those discussed, by way of example, in the preceding Background Art.  
           [0019]    One advantage of circuit implementations that possess unateness is their relatively small universal test set (i.e., the set of its minimal true and maximal false test vectors). Universal test sets guarantee a very high coverage of manufacturing defects in a vast range of implementations for a give function. Unlike universal test sets for highly unate circuit implementations, the universal test sets for largely binate circuits tend to become excessively large. In addition, the unateness property enables the generation of test vectors from the behavioral functions of circuits before their implementations are actually executed.  
           [0020]    Another advantage of unate circuit implementations is their low chip area. Yet another advantage of unate circuits is their ability to operate at very high speeds. For example, a low-area high-speed circuit implementation known as “domino logic” requires that the boolean function to be implemented be unate. Therefore, binate functions to be implemented in domino logic must be decomposed into unate functions prior to implementation. Similarly, static CMOS logic implementations become efficient if unate functions are extracted from an original binate function prior to implementation. Datapath logic circuits such as adders, subtractors, comparators, and ALUs are good examples of applications where carry generation functions (i.e., unate functions) are extracted from a larger (often binate) function and implemented in high-speed circuit structures.  
           [0021]    To meet these and other objects and advantages of the present invention, a method having preferred and alternate embodiments is provided for synthesizing a representation of a circuit into a new representation having greater unateness. The method includes (i) partitioning a circuit representation to obtain a representation of at least one sub-circuit, (ii) recursively decomposing the representation of the at least one sub-circuit into a sum-of-products or product-of-sums representation having greater unateness than the representation of the at least one sub-circuit, and (iii) merging the sum-of-products or product-of-sums representation into the circuit representation to form a new circuit representation.  
           [0022]    The invented method may additionally include repeating steps (i), (ii) and (iii) until a desired level of unateness for the new circuit representation has been achieved.  
           [0023]    The invented method may additionally include, for each decomposition, selecting the sum-of-products or product-of-sums representation having fewer binate variables.  
           [0024]    The invented method may additionally include merging common expressions of the sum-of-products or product-of-sums representations.  
           [0025]    The invented method may additionally include implementing algebraic division to merge common unate expressions.  
           [0026]    The invented method may additionally include partitioning the circuit representation to obtain a representation of at least one sub-circuit that is highly unate.  
           [0027]    The invented method may additionally include implementing a binary decision diagram to recursively decompose the representation of the at least one sub-circuit into the sum-of-products or product-of-sums representation. The binary decision diagram may be a zero-suppressed binary decision diagram.  
           [0028]    Additionally, a system having preferred and alternate embodiments is provided for synthesizing a circuit representation into a new circuit representation having greater unateness. The system comprises a computing device configured to (i) receive input defining a circuit representation, (ii) partition the circuit representation to obtain a representation of at least one sub-circuit, (iii) recursively decompose the representation of the at least one sub-circuit into a sum-of-products or product-of-sums representation having greater unateness than the representation of the at least one sub-circuit, (iv) merge the sum-of-products or product-of-sums representation into the circuit representation to form the new circuit representation, and (v) output the new circuit representation.  
           [0029]    The computing device may be further configured to receive input defining a desired level of unateness for the new circuit representation, and repeat steps (ii), (iii) and (iv) until the desired level of unateness is achieved.  
           [0030]    The computing device may be further configured for each decomposition, select the sum-of-products or product-of-sums representation having fewer binate variables.  
           [0031]    The computing device may be further configured to merge common expressions of the sum-of-products or product-of-sums representations.  
           [0032]    The computing device may be further configured to implement algebraic division to merge common expressions.  
           [0033]    The computing device may be additionally configured to partition the circuit representation to define a representation of at least one sub-circuit that is highly unate.  
           [0034]    The computing device may be additionally configured to implement a binary decision diagram to recursively decompose the representation of the at least one sub-circuit into a sum-of-products or product-of-sums representation. The binary decision diagram may be a zero-suppressed binary decision diagram.  
           [0035]    The circuit representation and the new circuit representation may be input to the computing device and output from the computing device, respectively, in a hardware description language such as Verilog or VHDL.  
           [0036]    Additionally, a preferred computer-readable storage embodiment of the present invention is provided. In accord with this embodiment, a computer-readable storage medium contains computer executable code for instructing one or more computers to (i) receive input defining a circuit representation, (ii) partition the circuit representation to obtain a representation of at least one sub-circuit, (iii) recursively decompose the representation of the at least one sub-circuit into a sum-of-products or product-of-sums representation having greater unateness than the representation of the at least one sub-circuit, (iv) merge the sum-of-products or product-of-sums representation into the circuit representation to form a new circuit representation, and (v) output the new circuit representation.  
           [0037]    The computer executable code may additionally instruct the computer(s) to receive input defining a desired level of unateness for the new circuit representation, and repeat steps (ii), (iii) and (iv) until the desired level of unateness is achieved.  
           [0038]    The computer executable code may additionally instruct the computer(s) to, for each decomposition, select the sum-of-products or product-of-sums representation having fewer binate variables.  
           [0039]    The computer executable code may additionally instruct the computer(s) to merge common expressions of the sum-of-products or product-of-sums representations.  
           [0040]    The computer executable code may additionally instruct the computer(s) to implement algebraic division to merge common expressions.  
           [0041]    The computer executable code may additionally instruct the computer(s) to employ a binary decision diagram to recursively decompose the representation of the at least one sub-circuit into the sum-of-products or product-of-sums representation.  
           [0042]    The above objects and advantages of the present invention are readily apparent from the following detailed description of the preferred and alternate embodiments, when taken in connection with the accompanying drawings.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0043]    [0043]FIGS. 1 a - 1   c  are functional circuit diagrams illustrating (a) a single binate block with three functions, (b) two unate blocks with six functions, and (c) three unate blocks with fifteen functions;  
         [0044]    [0044]FIG. 2 is a block representation corresponding to a decomposition of f(X)=h(g 1 (X), g 2 (X), . . . , g k (X)) in accordance with the present invention;  
         [0045]    [0045]FIGS. 3 a - 3   b  are (a) a binary tree representing an AND-OR decomposition in accordance with the present invention and (b) a corresponding block representation in accordance with the present invention;  
         [0046]    [0046]FIG. 4 is a block representation corresponding to a k-level AND/OR tree in accordance with the present invention;  
         [0047]    [0047]FIG. 5 is an example gate-level circuit to be decomposed by the computer-implemented process UDSYN in accordance with the present invention;  
         [0048]    [0048]FIGS. 6 a - 6   i  are (a) a circuit graph G C1  for the circuit of FIG. 5, (b) partition G p1  selected from G C1 , (c) unate decomposition performed on G P1 , (d) graph G C12  obtained by merging B 2  and G C1 , (e) partition G P2  selected from G C2 , (f) final unate decomposition of G P2 , (g) circuit graph G C3  obtained by merging B 3  and G C2 , (h) partition G P3  selected from G C3 , and (i) final block representation for the circuit of FIG. 5 in accordance with the present invention;  
         [0049]    [0049]FIGS. 7 a - 7   c  illustrate a zero-suppressed binary decision diagram (BDD) representing f 4   SOP =ab+{overscore (cb)}: (a) a path representing cube ab; (b) a path representing cube {overscore (cb)}; and (c) a zero-suppressed BDD representing f 4   POS =(a+{overscore (c)})(a+{overscore (b)})(b+{overscore (c)}) in accordance with the present invention; and  
         [0050]    [0050]FIGS. 8 a - 8   d  illustrate four steps in partitioning G C1  of FIG. 6 a : (a) start with a primary input node n10 and select n7; (b) select n14 and its transitive fanin nodes; (c) select n18 and its transitive fanin nodes; (d) final partition G P1  in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0051]    The present invention comprises a method and system having preferred and alternate embodiments for efficiently synthesizing a representation of a circuit into a new representation having greater unateness.  
         [0052]    For purposes of illustration, the present invention is described in the context of Bodean function-based digital circuitry. However, application of the present invention is not so limited. Notably, the present invention may be applied to a variety of circuit representations such as gate-level circuits, PLA representation, transistor-level representations, and HDL-based circuits.  
         [0053]    [0053]FIG. 1 a  defines a circuit representation  10  with three binate outputs (e.g., x, y and z). FIG. 1 b  shows a two-block representation for circuit  10 , and FIG. 1 c  a three-block representation. The block representations of (b) and (c) are obtained by decomposing the functions defining the original single-block circuit representation  10 . Circuit functionality for each block is represented in a sum-of-product (SOP) or product-of-sum (POS) form. Table 1 compares the test requirements for the three representations of FIG. 1.  
                                                               TABLE 1                                       Implementation Flexibility                Test Requirements       Area of                No. of Binate   Universal   No. of   an Example       Block   Variables for   Test Set   Block   Synthesized       Representation   all Functions   Size   Functions   Circuit                   7   64   3   28           0   33   6   29           0   47   12    50                  
 
         [0054]    In the case of FIG. 1 a,  function z is binate for all six variables, so its universal test set consists of all  64  possible test vectors. The decomposed designs of FIGS. 1 b  and  c  require smaller universal test sets ( 33  and  47 , respectively), since all their internal blocks are unate. Although the difference in test set size is minor in this small example, it tends to be significant for larger circuits.  
         [0055]    Circuits that do not have natural block representations are often implemented by logic synthesis systems, while those with natural block representations are often implemented manually. Although the present invention is not limited to the former case, we assume that the target circuit is of the former type in order to best describe the present invention.  
         [0056]    For a given circuit, the block representations created in accordance with the present invention can be considered as design constraints. In other words, the boundaries of the blocks serve as a high-level structural design constraint that must be satisfied by low-level implementations of the circuit such as gate-level or transistor-level implementations. Notably, these design constraints tend to restrict implementation flexibility.  
         [0057]    The outputs of any blocks in a circuit C&#39;s block representation S B  define the block functions. Circuit C&#39;s implementation flexibility can be roughly measured by the number of block functions that C employs. This follows from the fact that a large number of block functions in S B  implies that the functions themselves are small. Block functions in different blocks cannot be merged, so implementations of small block functions are generally less flexible than large ones. Thus the fewer the block functions in S B , the higher the implementation flexibility of C.  
         [0058]    For example, Table 1 compares the implementation flexibility of the block representations in FIG. 1. FIG. 1 b  has three more block functions than FIG. 1 a,  while FIG. 1 c  has 12 more. Whereas FIG. 1 a  has full implementation flexibility, the other block representations have limited flexibility. The last column of Table 1 compares the area of some example implementations synthesized by a commercial synthesis system Synopsys® Design Compiler with the goal of reducing area. The area is calculated from the relative gate areas defined in the Synopsys cell library; for example, inverter=1, AND2=2, AND4=3, OR2=2, and OR4=3. In summary, this example suggests that lower implementation flexibility often leads to poor implementations in terms of circuit area.  
         [0059]    To permit a broad range of implementation styles, the invented synthesis process attempts to decompose a binate function into as small a set of unate subfunctions as possible. In general, a decomposition of function f can be expressed as:  
         f(X)=h(g 1 (X),g 2 (X), . . . , g k (X)) 
         [0060]    Let f be the root function, subfunction h the parent function, and each subfunction g i  a child function. X={x 1 , x 2 , . . . , x n } denotes the support set of f and each g i . A decomposition is called a unate decomposition if all the subfunctions h and g 1.k  in f(X) are unate. A decomposition of the form f(X) transforms a single-block model of function f into a two-block model with h defining one block and g 1:k  the other; see FIGS.  2  and 3.  
         [0061]    In accordance with the present invention, a preferred method for synthesizing circuits utilizing unateness properties of boolean functions involves recursive OR and AND decompositions of a circuit output function f and its subfunctions. The OR and AND decompositions represent f(X) by h(g 1 (X), g 2 (X)), where h has the form g 1 +g 2  and g 1 g 2 , respectively. We obtain an OR decomposition off from an SOP form of f, and an AND decomposition from a POS form.  
         [0062]    For example, consider a binate function f 1  whose SOP form is a{overscore (b)}+{overscore (a)}c+{overscore (c)}a. A possible OR decomposition of f 1  is h=g 1 +g 2  with g 1 ={overscore (a)}c and g 2 =a{overscore (b)}+{overscore (c)}a. This decomposition makes all the subfunctions h, g 1 , and g 2  unate, and so is a unate decomposition. Now consider f 1 &#39;s POS form (a+c)({overscore (a)}+{overscore (b)}+{overscore (c)}). We can obtain directly from this form an AND decomposition with subfunctions h=g 1  g 2 , g 1 =a+c, and g 2 ={overscore (a)}+{overscore (b )}+{overscore (c)}. This is also a unate decomposition.  
         [0063]    A single OR or AND decomposition of a large binate function may not lead to a unate decomposition. However, a sequence of OR or AND decompositions applied to f recursively always produces a unate decomposition for any function f The general form of such a sequence with k levels is  
         f=h 1 (g 1   1 , g 2   1 ) 
         g i   1 =h 2 (g 1   2 , g 2   2 ) 
         g i   k−1 =h k (g 1   k , g 2   k ) 
         [0064]    where h j  and g i   j  denote a parent function and a subfunction, respectively, produced by the j-th level decomposition. Parent function h j  can be either AND or OR. A k-level sequence of AND and OR decompositions forms a binary AND-OR tree, where the internal nodes represent AND or OR operations, while the leaf nodes denote unate subfunctions that need no further decomposition.  
         [0065]    An arbitrary sequence of AND and OR decompositions can lead to an excessive number of subfunctions. To reduce this number, we restrict our attention to sequences of the following type, which we refer to as unate AND-OR decompositions.  
         f=h 1 (g u   1 , g b   1 ) 
         g b   1 =h 2 (g u   2 , g b   2 ) 
         g b   k−1 =h k (g u   k , g b   k ) 
         [0066]    As in the general case, h j  is either AND or OR, but the final g b   k  and every g u   j  are unate, while every gbf except the final one is either unate or binate. This decomposition can also be represented in the compact factored form  
         f=h 1 (g u   1 , h 2  (g u   2 , h 3 (g u   3 , . . . , h k−1 (g u   k−1 , h k (g u   k , g b   k ) . . . )))  (1) 
         [0067]    as well as the general form  
         f(X)=h(g u   1 , g u   2 , . . . , g u   k , g b   k )  (2) 
         [0068]    Comparing (1) with (2), we see that the parent function h in (2) is composed of the AND and OR subfunctions h 1 , h 2 , . . . , h k  only, and so is always unate.  
         [0069]    [0069]FIG. 3 a  shows a binary AND-OR tree corresponding to the unate decomposition  
           f =( g   u   1 ·( g   u   2 +( g   3 +( g   u   4 ·( g   u   5   ·g   b   5 ))))) 
         [0070]    obtained by a unate AND-OR decomposition with 5 levels. The internal nodes  30   a - 30   e  in FIG. 3 a  represent AND or OR operations, while the leaf nodes  32   a - 32   f  at the bottom represent unate subfunctions. FIG. 3 b  depicts the block representation corresponding to FIG. 3 a . B 1  defines an AND-OR tree network that implements the function h. B 2  is a network of undefined internal representation that implements the unate subfunctions g u   1 , g u   2 , g u   3 , g u   4 , g u   5 , and g b   5 .  
         [0071]    In general, we obtain the foregoing kind of unate AND-OR decomposition for f as follows: first decompose f into g u   1  and g b   1  using an AND or OR operation that makes g u   1  unate; then repeatedly decompose g b   j  into g u   j+1  and g b   j+1  in a similar way, until g b   j+1  becomes unate. This must eventually happen, because a g b   j  of a single product or sum term is unate. In practice, the AND-OR decomposition process often terminates with a final g b   j  consisting of a relatively large unate function.  
         [0072]    As noted above, the global parent function h(g u   1 , . . . , g u   k , g b   k ) in (2) is unate. Thus, the final result of a k-level AND-OR decomposition is a set of k+2 unate subfunctions g u   1:k , g b   k , and h(g u   1 , . . . , g u   k , g b   k )  
         [0073]    Notably, an important goal of the block synthesis method shown in FIG. 3 is to find an AND-OR decomposition of a given function f using as few subfunctions as possible. In addition, it is preferred that each g u   j  be selected in a manner that makes the resulting g b   j  highly unate. This selection often leads to a unate decomposition involving few subfunctions. Also such a g u   j  can be relatively easily derived from a standard SOP or POS form.  
         [0074]    Each level of a unate AND-OR decomposition is defined by either an AND or OR operation. How we select the operation at each level has a large impact on the final result, as we show with the following example.  
         [0075]    Consider f 2 =a⊕b⊕c whose SOP and POS forms are given below.  
           f   2   SOP   ={overscore (ab)}c+a{overscore (bc)}+{overscore (a)}b{overscore (c)}+abc   (3) 
           f   2   POS =( {overscore (a)}+b+c ( a+{overscore (b)}+c )( a+b+{overscore (c)} )( {overscore (a)}+{overscore (b)}+{overscore (c)} )  (4 ) 
         [0076]    OR decompositions are derived from (3), and AND decompositions are derived from (4). Suppose we select an OR operation in every level of the decomposition. A possible result is:  
           f   2   =g   u   1 +( g   u   2 +( g   u   3   +g   b   3 )) 
         [0077]    which involves five unate subfunctions:  
         g u   1 ={overscore (ab)}c; 
         g u   2 ={overscore (a)}b{overscore (c)}; 
         g u   3 =abc; 
         g b   3 =abc; and 
         h(g u   1 ,g u   2 ,g u   3 ,g b   3 ) 
         [0078]    Note that in this particular example, the unate decomposition is completed when the final g b   k  is a product term, and the resulting gi subfunctions correspond to each of the product terms in (3).  
         [0079]    Next, suppose we select an AND operation in every level. A possible result is the unate decompositions f 2 =g u   1 ·(g u   2 ·(g u   3 ·g b   3 )), which involves five subfunctions:  
         
       g 
       u 
       1 
       ={overscore (a)}+b+c; 
     
         
       g 
       u 
       2 
       =a+{overscore (b)}+c; 
     
         
       g 
       u 
       3 
       =a+b+{overscore (c)}; 
     
           g   b   3   ={overscore (a)}+{overscore (b)}+{overscore (c)} ; and 
           h ( g   u   1   ,g   u   2   ,g   u   3   ,g   b   3 ). 
         [0080]    Notably, a unate decomposition of f 2  can be obtained involving fewer subfunctions if AND and OR operations are mixed as follows. Suppose we select an OR operation in the first level and an AND operation in the second level. The OR operation decomposes (3) into f 2   1 =g u   1 +g b   1 , where g u   1 ={overscore (ab)}c and g b   1 =a{overscore (bc)}+{overscore (a)}b{overscore (c)}+abc. To apply an AND operation to g b   1 , we use g b   1 &#39;s POS form (a+b)(a+{overscore (c)})(b+{overscore (c)})({overscore (a)}+{overscore (b)}+c). Then an AND operation leads to g b   1 =g u   2 ·g b   2 , where for example, g u   2 =({overscore (a)}+{overscore (b)}+{overscore (c)}) and g b   2 =(a+b)(a+{overscore (c)})(b+{overscore (c)}). Since g b   2  is unate, the unate decomposition is complete. Note that unlike the previous cases, the final g b   k  here contains more than one term. The third unate decomposition of f 2  is  
           f   2   =g   u   1 +( g   u   2   ·g   b   2 )= {overscore (abc)}+ ({overscore (a)}+{overscore (b)}+{overscore (c)})·( a+b )( a+{overscore (c)} )( b+{overscore (c)} ) 
         [0081]    which involves only four subfunctions, one less than the first and second cases, where we selected three AND and three OR operations, respectively. This example shows that how we select the AND-OR operation in each level of the AND-OR decomposition is very important.  
         [0082]    Often, there are many possible AND and OR decompositions in each level. This implies the existence of a large number of possible unate AND-OR decompositions. For example, if an SOP form of g b   j  contains m product terms, we can partition these terms into two groups defining g u   j+1  and g b   j+1  in 2 m  different ways. At each level, either an AND or OR operation can be chosen, so the number of possible k-level unate AND-OR decompositions is  2   m+k . Thus, finding a unate AND-OR decomposition of a large function f involving a minimal number of subfunctions is often impractical. We therefore introduce Unate-Decomp, a heuristic process that systematically selects AND or OR decompositions at each recursion level, and produces a final unate AND-OR decomposition containing relatively few subfunctions.  
         [0083]    Unate-Decomp represents a function f and all its subfunctions in both SOP and POS forms. To produce an AND (OR) decomposition of f, it selects a set S of product terms (sum terms) from the SOP (POS) form of f, so that S constitutes a unate subfunction g u . The rest of the product terms (sum terms) of f define subfunction g b . Unate-Decomp then represents g b  by both SOP and POS forms, which it uses to produce an OR and AND decomposition at the next recursion level. To represent SOP and POS forms efficiently, binary decision diagrams can be employed.  
         [0084]    To decompose f into as few unate subfunctions as possible, Unate-Decomp produces each g u   j  in a way that reduces the number of binate variables in g b   j . In the case of multiple-function circuits, Unate-Decomp first decomposes each output function f i  using the method described above. It then merges common subfunctions of different functions f i  and f j  to reduce the total number of subfunctions.  
         [0085]    Notably, representing large circuits directly by two-level expressions is often inefficient. To handle such cases efficiently, a preferred process first partitions a given circuit, and then performs decomposition on each partition. For example, one partition is created for each process of Unate-Decomp parent function h. The resulting decomposition is then merged into the rest of the circuit. Then the next partition is created from the merged circuit, and the next process of Unate-Decomp is conducted. This process is repeated until no more partitioning is necessary.  
         [0086]    Preferably, each decomposition step and circuit partition are selected in a way that produces a small number of highly unate subfunctions. Consequently, the resulting block representations tend to have a high level of implementation flexibility.  
         [0087]    To decompose f into as few unate subfunctions as possible, Unate-Decomp produces each g u   j  in a way that reduces the number of binate variables in g b   j . For example, consider the following function f 3 :  
         
       f 
       3 
       ={overscore (a)}b{overscore (c)}+{overscore (a)}d+{overscore (ae)}+b{overscore (c)}f+bdf+b{overscore (e)}+{overscore (c)}df+{overscore (ce)}+a{overscore (b)}d{overscore (f)}+a{overscore (b)}e+acdf+c{overscore (d)}f+cd+{overscore (d)}e 
     
         [0088]    Suppose we decompose f 3  into g u+g   b . Table 2 shows some possible ways of doing this and the number of binate variables in the resulting g b .  
                       TABLE 2                               No. of               Binate               Variables in       g u     g b     g b                     cd + acdf + bdf   ad + abe + bcf + cdf + abc +   6           abdf + ae + de + cdf + be +           ce       abdf + ce   ad + abe + bcf + cdf + abc +   5           ae + de + cdf + be + cd +           acdf + bdf       bcf + bdf + cdf + be +   cd + acdf + abe + cdf +   3       ce + abc + ae   ad + abdf + de       abc + ad + ae + bcf + b   abdf + abe + acdf +   2       df + be + cdf + ce   cdf + cd + de                  
 
         [0089]    While the first OR decomposition produces g b  with six binate variables, the last OR decomposition produces g b  with only two binate variables, and so is selected.  
         [0090]    In each level of the decomposition process, Unate-Decomp produces a pair of AND and OR decompositions using a special form of cofactor operation called Subset. The Subset operation for a literal l i  extracts a subset S of product (sum) terms of a given SOP (POS) form by eliminating terms that contain l i . For example, applying Subset to the SOP form  
         {overscore (a)}bc+a{overscore (c)}d+a{overscore (b)}d 
         [0091]    for literal  
         {overscore (a)} 
         [0092]    yields  
         
       S=a{overscore (c)}d+a{overscore (b)}d 
     
         [0093]    Unate-Decomp systematically computes S for a set of binate literals {l 1 } so that S is unate and the set of other terms is highly unate. Then S defines g u   j , and the other product terms define g b   j .  
         [0094]    After a unate decomposition is formed, Unate-Decomp constructs two blocks from an AND-OR tree representing the decomposition; see FIG. 4. To ensure that all the block functions are unate, we place in block B 1  all the nodes representing the subfunctions g u   1:k  and g b   k , which correspond to the leaf nodes in the AND-OR decomposition tree. We place in block B 2  all the other nodes, which represent AND and OR operations and together form the function h.  
         [0095]    In the preceding description, we focused on decomposing a single function. In the case of multiple-function circuits, Unate-Decomp first decomposes each output function f i  using the method described above. It then merges common subfunctions of different functions f i  and f j  to reduce the total number of subfunctions. Algebraic division operations are often employed by logic synthesis techniques to efficiently combine common expressions. These operations can be easily applied to the results of our AND-OR decompositions, and often reduce the number of subfunctions significantly. Notably, Unate-Decomp incorporates algebraic division in such a manner that two different functions share the divisor of each division.  
         [0096]    Based on the unate decomposition concept described above, we introduce a computer-implemented synthesis program in accordance with the present invention called Unate Decomposition Synthesis (UDSYN). Representing large circuits directly by two-level expressions is often inefficient. To handle such cases efficiently, UDSYN first partitions the given circuit, and then performs decomposition on each partition, as generally described above.  
         [0097]    Table 3 contains one embodiment of a pseudocode representation of UDSYN in accordance with the present invention. Notably, it is understood by those of ordinary skill in the art that different computer programs and program arrangements can be implemented to support and execute the overall function of UDSYN.  
                         TABLE 3                       Embodiment of process UDSYN (Veritog-input)                                 1: G C : = Build-Circuit-Graph(Verilog-input);            2: while (G C  ≠ Ø) begin        3: G P : UD-Partition(G C );   /* G P  is a graph representing a partitioned block */        4: G C : = G C  − G P;     /* Remove nodes in G P  from G C  */        5: for each output node n R  in G P  begin        6: Build-ZSBDD(n R , G P );   /* Create SOP and its complement for n R  */        7: end;        8: (B i , B i+1 ): = Unate-Decomp(G P );   /* B i  and B i+1  correspond to B 1  and B 2  of FIG. 7 */        9: G C : = G c  ∪ B i+1 ; i: = i + 1;   /* Insert notes in B i+1  into G C  */       10: end;       11: Verilog-output: = Interconnect-Blocks({B i });   /* Verilog-output is the final block representation */       12: return Verilog-output;                  
 
         [0098]    UDSYN takes an input circuit in a form such as a Verilog specification whose internal elements can be either functional descriptions or gates. First, UDSYN builds a circuit graph G c  whose nodes represent the internal elements. It then creates a partition G p  of G c  using UD-Partition(G c ), and removes nodes in G p  from G c . The output functions of G p  are represented in SOP and POS forms. The process Unate-Decomp(G p ) performs unate AND-OR decompositions on the output nodes in G p , and constructs decomposed blocks B 1  and B 2  as in FIG. 4. Blocks B 1  and B 2  created from the i-th partition G Pi  are denoted by B 1  and B i+1 , respectively. Step 9 modifies G c  by inserting all nodes of B 2  into G c . UDSYN repeats the above steps until all nodes in G c  are removed. It then constructs a hardware description language (e.g. Verilog, VHDL, etc.) output file by specifying the interconnections among all blocks B i .  
         [0099]    We illustrate UDSYN using a gate-level circuit of FIG. 5 as input. FIGS. 6 a  to  i  show intermediate results of steps 2 to 10 in Table 3. FIG. 6 a  shows the circuit graph G C1  for the circuit of FIG. 5; each node in G C1  corresponds to a gate in the circuit. UD-Partition(G C ) creates a partition G P1  starting from the primary inputs of G C1 . The shading in G C1  indicates nodes that are selected by UD-Partition(G C ), and constitute G P1 . FIG. 6 b  represents G P1  by a rectangle. All nodes in G P1  are removed from G C1 , and are merged into SOP and POS forms by steps 5 to 8. These SOP and POS forms are decomposed by step 8 into unate subfunctions; these subfunctions are grouped into two blocks B 1  and B 2  as in FIG. 4. As FIG. 6 c  shows, B 1  consists of seven subfunctions and B 2  consists of three subfunctions. We create a new circuit graph G C2  by merging B 2  and G C1  as shown in FIG. 6 d.  Returning to step 3, UD-Partition(G C ) selects some nodes (shaded) in G C2  and creates a new partition G P2 , which is represented by a rectangle in FIG. 6 e.  Then step 8 decomposes G P2  into blocks B 2  and B 3  appearing in FIG. 6 f.  Step 9 merges B 3  into a new circuit graph G C3  as in the preceding steps; see FIG. 6 g.  FIG. 6 h  shows a new partition G P3  constructed from G C3 . By repeating this process, we finally obtain the decomposed block representation of FIG. 6 i  consisting of five blocks B 1.5 . The output functions of these blocks are described by Verilog code in equation form. If UD-Partition(G C ) constructs k partitions, UDSYN produces a total of k+1 blocks.  
         [0100]    Step 6 of Table 3 uses a type of binary decision diagram (BDD) called a zero-suppressed BDD (ZSBDD) to represent the SOP and POS forms of functions. Although other forms of BDD can be used, we limit our attention in this description to ZSBDDs for the sake of presentation. A ZSBDD of a function f is a graph whose paths denote the product terms (cubes) in an SOP form of f. UDSYN uses two ZSBDDs to represent a pair of SOP and POS forms for the internal function of each node in an AND-OR tree like that in FIG. 4. Thus an AND-OR tree with n nodes is represented by 2n individual ZSBDDs, each of which is linked to the corresponding node in the tree.  
         [0101]    For example, FIGS. 7 a  and  b  show a ZSBDD representing f 4   SOP =ab+{overscore (cb)}. The internal nodes (circles) in FIGS. 7 a  and  b  denote the literals appearing in f 4   SOP . The terminal or leaf nodes (rectangles) denote the output values that f 4   SOP  generates when its literals are set to the values specified on the edges. The name “zero-suppressed” stems from the property that all nodes in a ZSBDD whose 1-edge points to the 1-terminal node are eliminated. Every path from the root to the 1-terminal node represents a cube in f 4   SOP . For example, the path highlighted by the dashed line in FIG. 7 a  represents cube ab, while the one highlighted in FIG. 7 b  represents cube {overscore (cb)}. Although ZSBDDs can represent only SOP forms directly, POS forms can also be handled by their complemented form.  
         [0102]    For example, consider the POS expression  
           f   4   POS =( a+{overscore (c)} )( a+{overscore (b)} )( b+{overscore (c)} ) 
         [0103]    having the following complement  
         
       {overscore (f 4   POS )}= 
       {overscore (a)}c+{overscore (a)}b+{overscore (b)}c 
     
         [0104]    [0104]FIG. 7 c  shows a ZSBDD that represents {overscore (f 4   POS )}, where every path from the root to the 1-terminal node represents a sum term in f 4   POS  with their literals complemented. In this way, we can represent both SOP and POS forms using ZSBDDs.  
         [0105]    ZSBDDs have been shown to represent large functions efficiently. This is due to the fact that small ZSBDDs can contain a large number of paths, so a large number of cubes can be often represented by a compact ZSBDD. ZSBDDs also support fast manipulation of sets of cubes such as finding subsets, computing the intersection of cube sets, and performing a type of division operation on cube sets. Utilizing these features, we implement unate AND-OR decomposition and division processes that act directly on ZSBDDs.  
         [0106]    UD-Partition(G C ) creates a partition of the input circuit in a way that makes the functions defining the partition highly unate, while meeting a specified partition size limit. Partitions created in this way simplify the unate decomposition process. One pseudo-code embodiment of UD-Partition appears in Table 4. Notably, it is understood by those of ordinary skill in the art that a variety of different computer programs and program arrangements can be implemented to support and execute the inventive function of UD-Partition.  
                                                                                                                                                                                   TABLE 4                       Embodiment of process UD-Partition(G C )                                 1:   for each n c  in G C  on level order begin             2:   for each fan in node n i  of n c  begin             3:   if (n i  is a primary input of G C ) then             4:   S supp (n c ): = S supp (n c ) ∪ n i ;   /* S supp (n c ) is n c &#39;s support set */             5:   else             6:   S supp (n c ): = S supp (n c ) ∪ S supp (n i );             7:   Calculate-Path-Count(S supp )(n c ));   /* Add path count of fan-in nodes to n c  */             8:   end;                                     9:               N   BV          (     n   c     )       =       ∑     i   =   1     k          Binate                   (       s   i     ,     n   c       )                                   /* Binate(s i , n c ) = 1 if s i  is binate for n c  */                    10:   end;       11:   while (G C  = Ø) begin            12:   n m : = Select-Node-of-Min-N BV (G C );   /* n m  is to be included in the partition */       13:   S N : = nodes in n m &#39;s fan-in cone in G C ;       14:   if (I/O-count(G P  ∪ S N ) &lt; threshold) then   /* G P  is the graph for the partition */            15:   G P : = G P  ∪ S N ; G C : = : = G C  − G P ;   /* Add n m  and its transitive fan-in nodes to G P  */            16:   else break;   /* Discard the candidate node n m  */            17:   end;       18:   return (G C , G P );                  
 
         [0107]    Steps 1 to 10 compute the number of binate support variables of each node in the circuit graph G C . Steps 11 to 17 create the current partition G p  by selecting nodes in G C  that have a minimal number of binate variables.  
         [0108]    A node n c  in G C  is unate with respect to a primary input s i , if all paths between n c  and s i  have the same inversion parity; otherwise, n c  is binate with respect to s 1 . To determine the inversion parity of the paths, we calculate the number of paths from the primary inputs to each node n c  in G C . Let p even (s i , n c ) and p odd (s i , n c ) be the number of paths from a primary input s 1  to a node n c  whose inversion parity is even and odd, respectively. Steps 3 to 7 find the set S supp (n c ) of support variables for each node n c . For n c  and its fanin nodes n 1 , Calculate-Path-Count obtains p even (s i , n c ) and p odd (s i , n c ) by recursively computing  
           p   even ( s   i   , n   c )= p   even ( s   i   , n   c )+ p   even ( s   1   , n   1 ) 
           p   odd ( s   i   , n   c )= p   odd ( s   1   , n   c )+ p   odd ( s   i   , n   1 ) 
         [0109]    if the inversion parity from n i  to n c  is even; otherwise, it computes  
           p   even (s i   , n   c )= p   even ( s   1   , n   c )+ p   odd (s i   , n   1 ) 
           p   odd ( s   i   , n   c )= p   odd ( s   i   , n   c )+ p   even ( s   i   , n   1 ). 
         [0110]    The binary function Binate(s i , n c ) produces 1 (0), if a node n c  is binate (unate) with respect to its support variable s 1 , and is computed by  
         Binate(s i , n c )=0, if p even (s i , n c )=0 or p odd (s 1 , n c )=0 
         Binate(s i , n c )=1, otherwise 
         [0111]    The number N BV (n c ) of binate variables of node n c  with k variables is defined as  
           N   BV          (     n   c     )       =       ∑     i   =   1     k          Binate        (       s   i     ,     n   c       )                               
 
         [0112]    The intuition behind using N BV (n c ) to guide the partitioning stems from the fact that the more binate the node n c , the more difficult the decomposition process for n c  tends to be. Steps 1 to 10 traverse every node only once, which has complexity O(N). They propagate p even (s i , n c ) and p odd (s i , n c ) for every s i  for a n c  to the nodes in the transitive fanout of n c , which also accounts for complexity O(N). Hence the overall complexity of computing N BV (n c ) for all nodes in G C  is O( N ).  
         [0113]    For example, Table 5 shows the calculation of N BV (n c ) for every node in FIG. 6 a.   
                       TABLE 5                               No. of binate       Node   No. of paths from n C &#39;s support variable s i     variables       n C     s i , P even (S i ,n C ), P odd (s i ,n C ))   N BV (n C )                   n5   (a, 0, 1), (b, 0, 1)   0       n10   (b, 0, 1), (d, 0, 1)   0       n3   (f, 1, 0), (d, 1, 0)   0       n12   (g, 0, 1)   0       n13   (h, 1, 0), (i, 1, 0)   0       n8   (c, 0, 1), (b, 1, 0), (d, 1, 0)   0       n7   (g, 1, 0), (f, 0, 1), (d, 0, 1)   0       n14   (h, 1, 0), (i, 1, 0), (f, 1, 0), (d, 1, 0)   0       n9   (c, 1, 0), (b, 0, 1), (d, 0, 1)   0       n11   (b, 1, 1), (d, 1, 1), (c, 1, 0), (e, 0, 1)   2       n4   (c, 1, 1), (b, 1, 1), (d, 2, 2), (g, 1, 1), (f, 1, 1)   5       n2   (c, 0, 1), (b, 2, 0), (d, 1, 0), (a, 1, 0)   0       n6   (a, 1, 1), (b, 2, 2), (c, 1, 1), (d, 1, 1)   4       n18   (c, 1, 1), (b, 1, 1), (d, 3, 2), (g, 1, 1), (f, 2, 1),   5           (h, 1, 0), (i, 1, 1)       n15   (c, 2, 2), (b, 4, 4), (d, 3, 3), (a, 1, 1), (e, 1, 1)   5       n1   (f, 0, 1), (d, 1, 2), (a, 1, 1), (b, 2, 2), (c, 1, 1)   4       n16   (f, 3, 3), (d, 7, 7), (a, 2, 2), (b, 6, 6), (c, 4, 4),   6           (g, 2, 2)       n17   (g, 5, 5), (f, 7, 7), (d, 15, 15), (a, 4, 4), (b, 12, 12),   6           (c, 8, 8)                  
 
         [0114]    The second column lists p odd (s i , n c ) and p even (s 1 , n c ) computed for each node n c  and all its support variables. The last column gives N BV (n c ). For example, for n c =n11, Binate(b, n11)=1, Binate(d, n11)=1, Binate(c, n11)=0, and Binate(e, n11)=0. Thus N BV (n c )=1+1+0+0=2.  
         [0115]    After N BV (n c ) is computed for every n c  in G C , UD-Partition selects from G C  a node n m  of minimal N BV (n c ) starting from a primary input of G C . It then inserts into G p  all non-partitioned nodes in the transitive fanin region of n m . This process is repeated until the size of G p  exceeds a threshold equal to the maximum number of G p &#39;s I/O lines. By limiting the partition size in this way, we can prevent ZSBDDs from exploding for large circuits, while producing a partition with highly unate output functions.  
         [0116]    [0116]FIG. 8 illustrates how we partition G C  of FIG. 6 a.  Suppose we limit G p &#39;s I/O lines to seven inputs and six outputs, that is, we set the threshold to 7/6. The N BV (n c ) values calculated in Table 5 are shown next to each node n c  in FIG. 8. FIGS. 8 a  to  d  indicate the current G p  created in each iteration by shading, and newly selected nodes by thick circles. The first n m  is selected from the candidate nodes n3, n5, n8, n10, n11, n12, and n13, which are adjacent to the primary inputs. We select n3 whose N BV (n c ) has the minimum value 0, and add it to G p ; see FIG. 8 a.  The next search begins from n3 and selects n3&#39;s fanout node n7 whose N BV (n c )=0. We then select all nodes in the transitive fanin region of n7; FIG. 8 a  indicates these selected nodes by a dashed line. FIG. 8 b  shows the current G p  consisting of n3, n12, and n7. We then select n14 over n1, n14, and n17, and then select n14&#39;s fanin node n13; the newly selected nodes are again indicated by a dashed line in FIG. 8 b.  We next select n17 over n18, n1, n4, but n17 leads to a partition with seven outputs, one greater than the limit six. Hence we select n18 instead which has the next smallest N BV (n c ). We then select nodes in n18&#39;s transitive fanin region; see FIG. 8 c.  At this point, the number of I/O lines of G p  equals the threshold 7/6, so the partitioning is done. FIG. 8 d  indicates the final G p  by shading.  
         [0117]    Since UD-Partition selects nodes with fewer binate variables first, it often leads to a partition where many output functions are already unate and so require no further decomposition. For example, in G p  of FIG. 8 d,  four output functions at n3, n7, n8, and n10 are unate. FIG. 6 c  shows a unate decomposition of this G p,  where nodes g3, g7, g8, and g10 in DI correspond to these four unate functions, and so are not decomposed.  
         [0118]    Next we describe Unate-Decomp(G) which systematically applies unate AND-OR decomposition operations to a circuit partition. See Table 6 for one pseudo-code embodiment of Unate-Decomp(G).  
                         TABLE 6                       Embodiment of process Unate-Decomp(G)                                 1: S B : = G&#39;s binate function nodes;   /* S B  stores nodes of binate functions to be decomposed */        2: while (S B  ≠ Ø) begin        3: for each node n B  in S B  begin        4: (n u , n b ): = ANDOR-OneLevel(G, n B );   /* n u  (n b ) points to subfunction g u  (g b ) in (3.4) */        5: S D : = S D  ∪ {n u , n b };   /* S D  stores candidate divisor nodes */        6: end;        7: for each node n d  in S D  begin        8: for each node n f  in S B  − S D  begin   /* n f  is a candidate dividend node */        9: (n q , n r ): = Division(n f , n d );   /* n q  is the quotient and n r  is the remainder */       10: if (N BV (n f ) &lt; N BV (n q ) + N BV (n r )) then       11: Reverse the division;       12: end;       13: end;       14: S B : = Ø; S D : = Ø;       15: for each node n i  in G begin   /* Find new nodes to be decomposed */       16: if (N BV (n i ) &gt; threshold)       17: S B : = S B  ∪ n i ;   /* n i  exceeds the threshold */       18: end;       19: end;       20: return G;                  
 
         [0119]    Graph G initially contains the nodes in the current partition. Steps 3 to 6 perform a level of AND-OR decomposition on every binate node n B  in G. Then, steps 7 to 13 perform division operations on every binate node in G by treating as divisors child nodes created by the AND-OR decompositions. N BV (n i ) denotes the number of binate variables in the subfunction at node n 1  in G. If a division reduces N BV (n i ), it is accepted; otherwise, it is discarded. The above process is repeated until all nodes in G become unate. For some large binate functions, forcing all nodes to be unate leads to an excessive number of subfunctions. We therefore stop decomposing a node n i  if N BV (n i ) becomes less than a certain threshold. This threshold is chosen to yield a small set of subfunctions at the cost of lower unateness. Thus the threshold allows us to trade the level of unateness for a higher implementation flexibility of the block representation.  
         [0120]    Table 7 contains a pseudo-code embodiment of the computer-implemented process AND OR-OneLevel(G, n B ), which implements one level of the AND-OR decomposition technique described earlier.  
                         TABLE 7                       Embodiment of process ANDOR-OneLevel(G, n B )                                1: (g u   SOP , g b   SOP ): = Find-Unate-Cube-Set (SOP(n B ));   /* OR decomposition */       2: (g u   CPOS ,g b   CPOS ): = Find-Unate-Cube-Set (Inv(SOP(n B )));   /* AND decomposition */       3: if (N BV (g b   SOP ) ≦ N BV (g b   CPOS )) then       4: Replace-Node (n B , NewNodes (h SOP , g u   SOP , g b   SOP ));   /* Replace n B  in G by the new nodes */       5: return (Node(g u   SOP ), Node(g b   SOP ))       6: else       7: Replace-Node (n B , NewNodes(h POS , Inv(g u   CPOS ), Inv(g b   CPOS )));   /* Inv(g) complements g */       8: return (Node(Inv(g u   CPOS )), Node(Inv(g b   CPOS )));                  
 
         [0121]    The process Find-Unate-Cube-Set(SOP(n B )) finds a set of unate cubes (product terms) from an SOP representation SOP(n B ) for node n B . This operation forms an OR decomposition. An AND decomposition is obtained by complementing the input SOP(n B ) and the outputs of Find-Unate-Cube-Set, respectively. This enables ZSBDDs to handle both AND and OR decompositions, although ZSBDDs can only represent SOP forms directly.  
         [0122]    Table 8 contains a pseudo-code embodiment of the computer-implemented process Find-Unate-Cube-Set(ISOP).  
                                                                                             TABLE 8                           Embodiment of process Find-Unate-Cube-Set (ISOP)   /* ISOP is the initial SOP form */            1:   S best  := SOP := ISOP;       2:   while (N BV (SOP) &gt; threshold) begin            3:   for each literal l i  for binate variables in SOP repeat            4:   S i  := Subset(SOP, l i ;   /* Remove all cubes containing l i  */            5:   if (N BV (S i ) + N BV (ISOP − S i ) &lt; N BV (ISOP − S best )) then            6:   S best  := S i ;            7:   end;       8:   SOP := S best ;            9:   end;       10:   g u  := S best ;       11:   g b  := ISOP − S best ;       12:   return (g u , g b );                  
 
         [0123]    Find-Unate-Cube-Set(ISOP) derives a cube set S from f&#39;s initial SOP form ISOP so that S meets the threshold on N BV (S). As a result, S defines unate subfunction g u   k  in (1), while ISOP-S defines g b   k . As discussed earlier, an exact method to find an optimum AND-OR decomposition of an m-term ISOP must examine up to 2m possible AND decompositions. To avoid this and derive S efficiently, a type of cofactor operation is implemented which can simultaneously extract from ISOP multiple cubes (product terms) with a common property. This operation, denoted by Subset(SOP, l i ), removes from SOP all cubes that contain literal l i . Thus l i  does not appear in the resulting SOP form S i , while {overscore (l)} 1  may appear in S i ; hence S 1  is unate with respect to l i .  
         [0124]    For example, consider a function f 5  whose SOP form is  
         
       SOP=ab{overscore (c)}+a{overscore (c)}d+a{overscore (d)}+{overscore (bd)}a+ed 
     
         [0125]    Subset(SOP, d) removes cubes a{overscore (d)} and {overscore (bd)}a which contain literal {overscore (d)}, and yield  
         
       S 
       i 
       =ab{overscore (c)}+a{overscore (c)}d+ed 
     
         [0126]    The basic concept is to apply Subset(SOP, l i ) to a set of binate literals in a way that makes both S 1  and SOP−S i  highly unate. We found that for a binate l i , Subset(SOP, l i ) often eliminates from SOP not only l 1 , but also other binate literals. Hence we can often obtain a highly unate cube set S by repeating only a few steps of Subset(SOP, l 1 ). The inner loop (steps 3 to 8) of Table 8 performs Subset(SOP, l 1 ) for all binate literals l 1 , and selects S best , (i.e., the S 1  having the minimum N BV (S 1 )+N BV (ISOP−S i )). The outer loop (steps 2 to 9) repeats this process recursively with S best  in place of SOP until N BV (S best ) becomes less than threshold. The final S best  defines g u , while ISOP-S best  defines g b .  
         [0127]    To illustrate, consider an initial SOP form  
         
       ISOP=ab{overscore (c)}+a{overscore (c)}d+a{overscore (d)}+{overscore (bd)}a+ec+{overscore (a)}bde+ed 
     
         [0128]    Suppose that the threshold of N BV  is 0. Table 9 shows each step of the outer loop in its first iteration with ISOP assigned to SOP.  
                                 TABLE 9                           SOP = ISOP = abc + acd + ad + bda + ec + abde + ed            Binate           N BV (S i ) +       literal l i     S i     ISOP − S i     N BV (ISOP − S i )               a   bc + abde + ed   abc + acd + ad + bda   3       a   abc + acd + ad + bda +   abde   3           bc + ed       b   ad + bda + ed + bc   abc + acd + abde   2       b   abc + acd + ad + ed + abde   bda + bc   2       c   abc + acd + ad + bda + abde   bc   2       c   ad + bda + abde + bc   abc + acd   3       d   abc + ad + bda + bc   acd + abde   3       d   abc + acd + ed + abde + bc   ad + bda   3                  
 
         [0129]    Each row in Table 9 shows S i  and ISOP−S i  obtained by Subset(SOP, l i ) for binate literals l i =a,{overscore (a)},b,{overscore (b)},c,{overscore (c)},d and {overscore (d)} of ISOP. Row 3 (i.e. binate literal b) gives the minimum N BV (S 1 )+N BV (SOP−S i ) and so is selected. The selected S 1  is still binate, so the second iteration of the outer loop is performed with the S 1  assigned to SOP; see Table 10. Each row gives Subset(SOP, l 1 ) for binate literals l 1 =d and {overscore (d)}in SOP.  
                                 TABLE 10                           SOP = S best  = ad + bda + ed + bc            Binate           N BV (S i ) +       literal l i     S i     ISOP − S i     N BV (ISOP − S i )               d   ad + bda + bc   ed + abc + acd + abde   1       d   ed + bc   ad + bda + abc +   3               acd + abde                  
 
         [0130]    The first row (i.e. literal d) of Table 10 gives the lower N BV (S i )+N BV (SOP−S i ), and is selected. The selected S i  now is unate and so the process is done. We finally obtain g u =a{overscore (d)}+{overscore (bd)}a+{overscore (b)}c and g b =ed+ab{overscore (c)}+a{overscore (c)}d+{overscore (a)}bde. Since Find-Unate-Cube-Set(ISOP) aims to reduce both N BV (S i ) and N BV (SOP−S 1 ), it tends to make g b  highly unate as well. Observe that the g b  produced in this example is unate for all but one variable (a).  
         [0131]    The Subset(SOP, l 1 ) operation conducted using an M-node ZSBDD has a complexity of O(M). Find-Unate-Cube-Set(ISOP) for an ISOP with N binate variables repeats the inner loop N 2  times. Hence the worst case complexity of Find-Unate-Cube-Set(ISOP) is O(N 2 M). Compare this with the complexity 0(2 m ) of an exact method discussed above; m is usually significantly greater than N and M. Thus the presented AND-OR decomposition process can generate highly unate g u   j  and g b   j  quite efficiently.  
         [0132]    While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.