Abstract:
The present invention concerns a receiver circuit including an input terminal through which an input signal is received, said receiver circuit further including:
       a first amplifier stage connected via its input to the input terminal of said receiver circuit;   an envelope detector stage for detecting the incoming signal maxima to recover the signal envelope, said detector stage being connected to the output of the first stage.

Description:
[0001]    This application claims priority from European Patent application No. EP12190222.5 filed Oct. 26, 2012, the entire disclosure of which is incorporated herein by reference. 
         [0002]    The invention concerns the field of receiver systems and/or circuits including an input terminal through which an input signal is received, said receiver circuit further including:
       a first amplifier stage connected via its input to the input terminal of said receiver circuit;   an envelope detector stage for detecting the incoming signal maxima to recover the signal envelope, said detector stage being connected to the output of the first stage.       
 
       BACKGROUND OF THE INVENTION 
       [0005]    It is known that devices such as mobile telephones or satellites or various portable objects are provided with transceiver circuits including a transmission loop used to transmit a signal and a receiving loop used to receive a signal. Some devices such as radio tuners are only provided with an electronic receiver circuit, i.e. having a receiving loop as shown in  FIG. 1 . 
         [0006]    A receiving loop  10  includes an input terminal  4  through which an input signal is received, said receiver circuit further including:
       a first amplifier stage  6  connected via its input to the input terminal of said receiver circuit;   an envelope detector stage  8  for detecting the incoming signal maxima to recover the signal envelope, said detector stage being connected to the output of said first stage.   a peak detector stage  9  for detecting the peak value of the signal and adjusting the gain. This peak detector stage is also used for comparing the levels of the envelope detector stage.   a comparator stage  12  connected between the envelope detector stage output and the peak detector stage output. The comparator stage is provided with a hysteresis module. This stage is used for delivering a receiver circuit output signal namely a square signal.       
 
         [0011]    The receiver loop is also provided with a differential amplifier  11  whose negative input is connected to the peak detector stage output, the positive input allowing a reference signal to be compared to the peak detector stage output. This differential amplifier delivers a signal connected to the first amplifier stage in order to act thereon and modify the output thereof. 
         [0012]    One drawback of this circuit is that the envelope detector stage, the peak detector stage and the connection path between the differential amplifier output and the first amplifier stage are provided with high value capacitors. The first drawback of these high value capacitors is that they are expensive. Indeed, high value capacitors, i.e. capacitors whose value attain or exceed a microfarad are made in expensive technologies and a multiplicity thereof thus increases the cost of the circuit. 
         [0013]    Further, the size of these capacitors is generally greater, which results in a printed circuit board having a larger surface and also a higher price. 
         [0014]    Finally, another drawback of these capacitors is that it is possible for perturbations to appear. These perturbations take the form of oscillation in the signal. Consequently, the circuit no longer operates in an optimum manner. The more the number of capacitors increases, the more the risk of oscillation will increase. 
         [0015]    Finally, this receiver circuit has the drawback of being complex since it is not easy to combine an envelope detector stage with a peak detector stage. 
       SUMMARY OF THE INVENTION 
       [0016]    It is an object of the invention to overcome the drawbacks of the prior art by proposing to provide a less expensive receiver system with improved reliability and stability. 
         [0017]    The invention therefore concerns a receiver circuit including an input terminal through which an input signal is received, said receiver circuit further including:
       a first amplifier stage connected via one of its inputs to the input terminal of said receiver circuit and delivering an amplified signal;   an envelope detector stage, connected to the first stage output, for detecting maxima in the amplified incoming signal in order to recover the signal envelope and deliver a signal, characterized in that said receiver circuit further includes:   a second comparator stage including a negative input connected to the envelope detector stage output and a positive input through which a reference signal is received, said second comparator stage consisting in comparing the signal detected at the detector stage output with the reference signal to deliver a control signal sent to the first amplifier stage for varying the gain of the first amplifier stage;   and a comparator circuit connected via a positive input to the envelope detector stage output and via a negative input to the positive input of the second amplifier stage in order to compare the envelope detector stage output with the reference signal and to deliver a demodulated output signal.       
 
         [0022]    One advantage of this receiver circuit is that the number of components is limited since it is no longer necessary to use a peak detector. Consequently, the high value capacitor associated with the peak detector circuit is not used either. This results in a saving in the surface area of the printed circuit board and also a saving in terms of costs since the cost of these components is significant. 
         [0023]    Further, the fact of limiting the number of high value capacitors leads to improved sensitivity of the receiver circuit. Indeed, high value capacitors are known to cause the appearance of perturbations which damage sensitivity. 
         [0024]    In a first advantageous embodiment, the envelope detector stage further includes a protection capacitance. 
         [0025]    In a second advantageous embodiment, the comparator circuit includes a comparator unit distinguishing between the envelope detector stage output signal and the second amplifier stage output signal, and a hysteresis unit. 
         [0026]    In another advantageous embodiment, the hysteresis unit includes two pairs of transistors of the same type each including a first transistor and a second transistor, the transistors of the same pair being connected to earth, the gate of the first transistor of the first pair and the gate of the second transistor of the second pair being connected to each other so as to form a first connection point, whereas the gate of the second transistor of the first pair and the gate of the first transistor of the second pair are connected to each other so as to form a second connection point, said hysteresis unit further being arranged so that the drains of the first transistor of the first pair and of the second transistor of the second pair are connected to the comparator unit, the drains of the second transistor of the first pair and of the first transistor of the second pair being respectively connected to the drain of the second transistor of the second pair and to the drain of the first transistor of the first pair. 
         [0027]    In another advantageous embodiment, the hysteresis unit further includes a programmable part including two programming transistors each connected via its drain to the sources of the transistors of one of the two pairs of transistors of the hysteresis unit, the sources of these programming transistors being connected to earth and the gates of each transistor forming a connection point for a programming signal. 
         [0028]    In another advantageous embodiment, the comparator unit (BC) is connected to earth via a first regulating transistor traversed by a first regulating current, the hysteresis unit being connected to earth via a second regulating transistor traversed by a second regulating current, the hysteresis width being linked to the ratio between the second regulating current and the first regulating current. 
         [0029]    In another advantageous embodiment, the first regulating transistor and the second regulating transistor are each formed of a multitude of transistors in parallel each able to be selectively activated or deactivated and the ratio between the second regulating current and the first regulating current is regulated by modifying the number of transistors activated for the first regulating transistor and for the second regulating transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    The objects, advantages and features of the receiver system according to the present invention will appear more clearly in the following detailed description of at least one embodiment of the invention, given solely by way of non-limiting example and illustrated by the annexed drawings, in which: 
           [0031]      FIG. 1  is a schematic view of a prior art receiver system. 
           [0032]      FIG. 2  is a schematic view of a receiver system according to the invention. 
           [0033]      FIG. 3  is a schematic view of the comparator stage of the receiver system according to the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0034]      FIG. 2  shows a receiver circuit or system  100  according to the invention. This receiver circuit  100  includes an input  104  via which a signal is received. This signal Vin is a signal containing data which may equally be a high frequency signal or a low frequency signal. This signal Vin takes the form of an amplitude modulated signal. 
         [0035]    This input  104  is connected to a first input of a first amplifier stage  106 . First comparator stage  106  includes a low noise amplifier  107 . The purpose of low noise amplifier  107  is to amplify the incoming signal to deliver an amplified input signal Vout. 
         [0036]    The output of first amplifier  106  is connected to an envelope detector stage  108 . Envelope detector stage  108  is used to demodulate the amplified input signal Vout which is the amplified incoming signal Vin, i.e. to deliver a detected signal Vout 1  matching the contours of the amplified incoming signal. Envelope detector stage  108  is also used for extracting data concerning the amplitude of amplified input signal Vout. Stage  108  further includes a high value capacitor C 1  connecting said envelope detector stage to earth. Capacitor C 1  is used for envelope detection and for filtering high frequency signals. 
         [0037]    Advantageously according to the invention, the output of this envelope detector stage  108  is connected to a second amplifier stage  110  which may also be called the second comparator stage. Second comparator stage  110  includes an operational transconductance amplifier  111 . The detected signal Vout 1  from envelope detector stage  108  is connected to the negative input of said operational transconductance amplifier  111 . The positive input of said operational transconductance amplifier  111  is used so that a reference signal Vswref can be connected thereto. This reference signal Vswref takes the form of a continuous signal whose voltage value is predetermined. 
         [0038]    Operational transconductance amplifier  111  is used to deliver, at output, a control signal Vcom used as the setpoint. This control signal Vcom is connected to a second input of the first amplifier stage  106 , i.e. to a second input of low noise amplifier  107 . The purpose of control signal Vcom is to act on low noise amplifier  107  so as to modify its gain for optimum demodulation. 
         [0039]    To deliver control signal Vcom, operational transconductance amplifier  111  compares signal Vout 1  to a reference signal Vswref. Signal Vout 1  is transformed by operational transconductance amplifier  111 . In theory, operational transconductance amplifier  111  is configured to superpose the detected signal Vout 1  at the output of envelope detector stage  108  and reference signal Vswref and to calculate the area of signal Vout 1  above Vswref and below Vswref. Once these areas have been calculated by integration, they are compared to each other. In practice, this calculation consists in calculating the mean of detected signal Vout 1  and comparing this mean to the value of signal Vswref. Ideally, the mean value of detected signal Vout 1  should be equal to the value of signal Vswref. 
         [0040]    Thus, if output signal Vout 1  of envelope detector stage  108  has a lower mean value than the mean value of reference signal Vswref, the purpose of the outgoing control signal Vcom is to increase the gain of the first amplifier stage  106 . Conversely, if the detected output signal Vout 1  from envelope detector stage  108  has a higher mean value than the mean value of reference signal Vswref, then the purpose of the outgoing signal Vcom is to decrease the gain of said first amplifier stage  106 . However, if the detected output signal Vout 1  from envelope detector stage  108  has a mean value equal to the mean value of reference signal Vswref then the gain is not modified. 
         [0041]    This enables detected signal Vout 1  to be kept within an amplitude interval. Consequently, the gain of first amplifier stage  106  is adjusted solely with envelope detector  108  and operational transconductance amplifier  111 . The peak detector circuit is therefore no longer used and a more compact and less expensive circuit is obtained. Moreover, one less capacitor is used which increases the stability of the system. 
         [0042]    Operational transconductance amplifier  111  further includes a high value capacitor C 2  connected in parallel to the output of said operational transconductance amplifier  111 . This capacitor is connected to earth and is used as an integrator for stabilising the receiving loop. The error is stored in capacitor C 2  and the gain control loop only makes an adjustment to the desired value when the error is zero which means that capacitor C 2  will not be charged or discharged. 
         [0043]    Further, receiver circuit  100  also includes a comparator stage  112 . This comparator stage  112 , seen in  FIG. 3 , delivers the system output signal Vdout and includes a slider comparator circuit  113  which includes a comparator unit BC and a hysteresis unit BH and is powered by a voltage Vdd, the earth being called Vss. 
         [0044]    Comparator unit BC is the unit through which the input and output of comparator stage  112  are arranged. The input of said comparator stage  112  is formed by two input terminals Bin+ and Bin− including a pair of N type transistors called M 1  and M 2 . Terminal Bin+ is connected to transistor M 1  and terminal Bin− is connected to transistor M 2 . 
         [0045]    In the present case, terminal Bin+ is connected to the output of envelope detector circuit  108  whereas terminal Bin− is connected to the positive input terminal of operational transconductance amplifier  111 , i.e. to reference signal Swref. The gates of these transistors M 1  and M 2  form the input terminals of the comparator stage. The comparator unit further includes a pair of P type transistors called M 5  and M 6 . The drain of transistor M 5  is connected to the drain of transistor M 1 , whereas the drain of transistor M 6  is connected to the drain of transistor M 2 . The source of transistors M 5  and M 6  is connected to voltage Vdd, whereas the gates of these transistors M 5  and M 6  are connected to each other to form a connection point for applying a signal to activate the P type transistors. 
         [0046]    Between the drains of M 1  and M 5  and the drains of M 2  and M 6 , there are arranged two output connections Bm+ and Bm−. These connection points Bm+ and Bm− enter a circuit A 2  which amplifies the gain of comparator stage  112  to obtain two output terminals Bout+ and Bout− of comparator stage  112 . Output terminals Bout+ and Bout− deliver at output the output signal Vdout. 
         [0047]    The source of transistor M 1  and the source of transistor M 2  are connected together to the drain of a first regulating N type transistor called M 11 , the source of which is connected to earth Vss, with a first regulating current Icmp traversing said transistor M 11 . 
         [0048]    Hysteresis unit BH includes a first part formed of two pairs of transistors M 7 , M 8  and M 9 , M 10 . Each pair of transistors includes two N type transistors. It is clear that transistors M 7 , M 8  form a first pair, while transistors M 9 , M 10  form a second pair. The sources of the transistors of each pair are connected to each other and are also connected to the drain of transistor M 12 . 
         [0049]    This first part of hysteresis unit BH is also arranged to be respectively connected to connection point Bm−, i.e. the connection between the drain of M 1  and the drain and M 5  and to connection point Bm+, i.e. the connection between the drain of M 2  and the drain and M 6 . To achieve this, the drain of transistor M 7  and the drain of transistor M 10  are respectively connected to connection point Bm− and to connection point Bm+. The drains of transistors M 8  and M 9  are connected so that the drain of M 8  is connected to the drain of M 10  and so that the drain of M 9  is connected to the drain of M 7 . 
         [0050]    Further, the gates of the transistors are connected in pairs so that the gates of transistors M 7  and M 10  are connected to each other and the gates of transistors M 8  and M 9  are connected to each other. This arrangement forms two connection points which are connected to outputs Bout+ and Bout− of comparator stage  112 . 
         [0051]    The configuration of the first part of hysteresis unit BH provides a hysteresis function associated with comparator unit BC. There is therefore obtained a conventional comparator circuit provided with a hysteresis function. The operation of this circuit consists, in comparator unit BC, of making the comparison between the detected signal Vout 1  and the reference signal Vswref. Thus, hysteresis unit BH is used to complete this comparison by taking into account the output of said comparator stage  112  and the hysteresis signal. 
         [0052]    In an advantageous variant, the hysteresis unit includes a second programmable part. This second part includes a pair of N type transistors called M 3  and M 4  whose sources are connected to each other. The drains of transistors M 3  and M 4  are connected to a second part. Consequently, the source of transistor M 7  is connected to the source of transistor M 8  and to the drain of transistor M 3 , whereas the source of transistor M 9  is connected to the source of transistor M 10  and to the drain of transistor M 4 . The sources of transistors M 3  and M 4  are connected to the drain of a second regulating transistor M 12 , whose source is connected to earth Vss, the gate of said transistor M 12  being connected to the gate of transistor M 11 , a second regulating current Ihyst traversing said transistor M 12 . This configuration allows transistors M 11  and M 12  to form a connection point for applying a signal to activate the N type transistors. The gates of transistors M 3  and M 4  each form a connection terminal, respectively Bref+ and Bref−, used to modify the hysteresis. 
         [0053]    Indeed, the hysteresis width of this circuit is dependent on the ratio between the current Ihyst connected to M 12  and the current Icmp connected to M 11 . The hysteresis width may therefore be controlled by modifying this ratio Ihyst/Icmp. To achieve this, it should be considered that transistors M 11  and M 12  are each, in reality, formed of a multitude of transistors in parallel. This configuration allows the current to be distributed in the various transistors. Ideally, transistors M 11  and M 12  are each formed of the same number of transistors in parallel. When all the transistors for M 11  and M 12  are closed, a ratio is obtained between Ihyst and Icmp. To modify this ratio, the number of transistors that are closed simply needs to be modified. This causes an increase in the current flowing in each transistor. Consequently, the ratio between current Ihyst and current Icmp varies. For example, it is assumed that M 11  and M 12  each include  20  transistors in parallel so that Ihyst=Icmp. If the number of transistors M 12  decreases to 10, while the number of transistors M 11  remains constant at  20 , Ihyst= 0 . 5  Icmp is obtained and therefore a modified hysteresis width. It is consequently simple to modify the hysteresis width by switching more or fewer transistors. 
         [0054]    It is also possible to modify the hysteresis width by using connection terminals Bref+ and Bref−. The signal sent into each of these connection terminals Bref+ and Bref− enables the current to be modified and thus the hysteresis width to be modified, as seen in  FIG. 3 . More specifically, increasing the voltage applied to connection point Bref+ increases the hysteresis width, i.e. there is a delay in the switch to change from a low level to a high level and the switch to change from a high level to a low level. Conversely, decreasing the hysteresis width brings the switches closer together. The hysteresis decreases the effect of noise on the signals. Consequently, this capacity to programme the hysteresis width has the advantage of adapting the noise reduction according to the incoming signal or components used. 
         [0055]    Of course, it is possible to adjust the hysteresis width prior to manufacture by adapting, modifying the size of transistors M 11  and M 12 . 
         [0056]    It will be clear that various alterations and/or improvements and/or combinations evident to those skilled in the art may be made to the various embodiments of the invention set out above without departing from the scope of the invention defined by the annexed claims.