Abstract:
A method of attaching an integrated circuit chip to a module and a resultant structure. The method includes placing a solder bump tape between the chip and the module, the solder bump tape including an array of solder columns embedded in a dielectric sheet; aligning and contacting top surfaces of solder columns with respective chip pads of an array of chip pads of the chip and aligning and contacting bottom surfaces of the solder columns with respective module pads of an array of module pads; and reflowing the solder columns to form solder interconnections between chip pads and respective module pads.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of integrated circuit packaging; more specifically, it relates to a method and structure for electrically and mechanically connecting integrated circuit chips to modules. 
       BACKGROUND OF THE INVENTION 
       [0002]    A common technology for electrically attaching integrated circuit chips to modules is variously called flip-chip attachment, controlled collapse chip connection (C4) attachment and solder bump attachment. In this technology, solder columns are formed on pads on the integrated circuit chip and then the chip is placed on a module so the solder bumps are sitting on corresponding pads. The solder bumps are then heated so they melt (reflow) and physically and electrically connect the chip pads to the module pads. Then a dielectric underfill material is injected between the module and integrated circuit chip, filling the space between solder bumps. This technology has some limitations, which include, voids in the underfill, chip tilting during reflow and missing solder bumps (particularly with low-lead and non-lead solder) to name a few. These limitations can impact yield and reliability and require several testing and inspection steps be included in the manufacturing process adding to cost and turn-around time. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove. 
       SUMMARY OF THE INVENTION 
       [0003]    A first aspect of the present invention is a method of attaching an integrated circuit chip to a module, comprising: placing a solder bump tape between the integrated circuit chip and the module, the solder bump tape including an array of solder columns embedded in a dielectric sheet, top surfaces of the solder columns exposed at a top surface of the dielectric sheet and bottom surfaces of the solder columns exposed at a bottom surface of the dielectric sheet; aligning and contacting top surfaces of the solder columns with respective chip pads of an array of chip pads of the integrated circuit and aligning and contacting bottom surfaces of the solder columns with respective module pads of an array of module pads of the module; and reflowing the solder columns to form solder interconnections between chip pads of the array of chip pads and respective module pads of the array of module pads. 
         [0004]    A second aspect of the present invention is a structure, comprising: an underfill comprising a dielectric sheet between a dielectric top adhesive layer and a dielectric bottom adhesive layer; an integrated circuit chip having an array of chip pads disposed on a top surface thereof, the top adhesive layer bonded to the top surface of the integrated circuit chip between chip pads of the array of chip pads; a module having an array of module pads disposed on a top surface thereof, the bottom adhesive layer bonded to the top surface of the module between module pads of the array of module pads; and solder interconnections extending from chip pads of the array of chip pads through the top adhesive layer, the dielectric sheet and the bottom adhesive layer to corresponding module pads of the array of module pads. 
         [0005]    A third aspect of the present invention is a method of attaching an integrated circuit chip to a module, comprising: placing a solder bump tape between a top surface of the integrated circuit chip and a top surface of the module, the solder bump tape including an array of solder columns embedded in a dielectric sheet, a top surface of the dielectric sheet facing the top surface of the integrated circuit chip and a bottom surface of the dielectric sheet facing the top surface of the module, opposite top and bottom surfaces of the solder columns proximate respectively to the top and bottom surfaces of the dielectric sheet not covered by the dielectric sheet; aligning and contacting top surfaces of solder columns of the array of solder columns with respective chip pads of an array of chip pads disposed on the top surface of the integrated circuit and aligning and contacting bottom surfaces of solder columns of the array of solder columns with respective module pads of an array of module pads disposed on the top surface of the module; and reflowing the solder columns to form solder interconnections between chip pads of the array of chip pads and respective module pads of the array of module pads. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0007]      FIG. 1  is an exploded cross-sectional/side view of the components of a integrated circuit package according to embodiments of the present invention; 
           [0008]      FIG. 2  is a top view of a solder bump tape according to embodiments of the present invention; 
           [0009]      FIG. 3  is an exploded cross-sectional/side view of assembly of a integrated circuit package according to embodiments of the present invention; 
           [0010]      FIG. 4  is a top view of alternative solder bump tape(s) according to embodiments of the present invention; 
           [0011]      FIG. 5  is cross-sectional view of a first type of solder bump tape according to embodiments of the present invention; 
           [0012]      FIG. 6  is cross-sectional view of a second type of solder bump tape according to embodiments of the present invention; 
           [0013]      FIG. 7  is cross-sectional view of a third type of solder bump tape according to embodiments of the present invention; 
           [0014]      FIG. 8  is cross-sectional view of a fourth type of solder bump tape according to embodiments of the present invention; 
           [0015]      FIG. 9  is cross-sectional view of a fifth type of solder bump tape according to embodiments of the present invention; 
           [0016]      FIG. 10  is cross-sectional view of a sixth type of solder bump tape according to embodiments of the present invention; 
           [0017]      FIG. 11  is cross-sectional view of a seventh type of solder bump tape according to embodiments of the present invention; 
           [0018]      FIG. 12  is an exploded detailed cross-sectional/side view of the components of a integrated circuit package according to embodiments of the present utilizing solder bump tape having protruding solder columns; and 
           [0019]      FIG. 13  is an exploded detailed cross-sectional/side view of the components of a integrated circuit package according to embodiments of the present utilizing solder bump tape using recessed solder columns. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    An integrated circuit module is first level packaging element intermediate between an integrated circuit chip and a second level packaging element. Examples of module types include ceramic modules (wires on or embedded in a ceramic substrate), multilayer ceramic modules (multiple levels of wires on and/or embedded in multiple layers of ceramic material) and printed circuit modules. Examples of second level packages include but are not limited to printed circuit boards and cards. Printed circuit boards/card and printed circuit modules may include one or more wiring levels embedded in and/or on one or more surfaces of an organic based dielectric material (which may include non-organic materials like fiberglass). 
         [0021]    A lead-free interconnect is defined as metallurgical interconnect containing none to less than about 0.01% lead. A low lead interconnect is defined as a metallurgical interconnect containing less than about 5% lead. When heated, solder reacts with metallic pads to form electrically conductive alloy junctions that also serve to mechanically attach the solder to the metallic pad. 
         [0022]      FIG. 1  is an exploded cross-sectional/side view of the components of an integrated circuit package according to embodiments of the present invention. In  FIG. 1 , the components of a integrated circuit package include (i) and integrated circuit chip  100  having electrically conductive chip pads  105  disposed on a top surface  110  of the integrated circuit chip, (ii) a solder bump tape  115 , including solder columns  120  embedded in a dielectric sheet  125 , the solder columns exposed at top and bottom surfaces  120  and  135  of the dielectric sheet, and (iii) a module  140 , having module pads disposed on a top surface  150  of the module. Top surface  110  of integrated circuit chip is facing top surface  130  of dielectric sheet  125  and top surface  150  of module  140  is facing bottom surface  135  of dielectric sheet  125 . Integrated circuit chip  100 , solder bump tape  115  and module  140  are aligned along a vertical axis  155 , so solder columns  120  are aligned to corresponding chip pads  105  and module pads  155 . 
         [0023]    In one example, solder columns  120  comprise a lead free solder. In one example solder columns  120  comprise a low-lead solder. In one example, solder column  120  comprise a mixture of two or more metals selected from the group consisting of tin, copper, silver, bismuth, indium, zinc and antimony. In one example, solder columns  120  comprise a material selected from the group consisting of a mixture of lead and tin, a mixture of tin and silver, a mixture of tin and copper, a mixture of tin and bismuth, a mixture of tin and zinc, a mixture of tin and indium, a mixture of tin and antimony, and a mixture of tin, silver and copper. 
         [0024]    In one example dielectric sheet  125  comprises a material selected from the group consisting of epoxy, silica filled epoxy, silicone, acrylic resin, poly vinyl chloride resin, a thermosetting resin and a thermoplastic resin. 
         [0025]    While in  FIG. 1 , the perimeter of solder bump tape  115  aligns with the perimeter of integrated circuit chip  100 , it should be understood that the size (e.g., footprint) of solder bump tape  115  may be larger then that of integrated circuit chip  100  so the perimeter of solder bump tape  125  may extend past the perimeter of integrated circuit chip  100  on all or some of the sides of the integrated circuit chip as illustrated by the dashed lines. 
         [0026]      FIG. 2  is a top view of a solder bump tape according to embodiments of the present invention. In  FIG. 2 , solder columns  120  are arranged in an exemplary 10 by 10 array that would correspond. Optionally, one position of the array (indicated by the arrow) has no solder column as an orientation guide for orienting the tape, chip and module during assembly. Corresponding chip and module pads positions would also be empty (have no pad in that position). 
         [0027]      FIG. 3  is an exploded cross-sectional/side view of assembly of an integrated circuit package according to embodiments of the present invention. In  FIG. 3 , top surface  110  of integrated circuit chip  100  and top surface of  130  of dielectric sheet  125  are brought in contact, as are top surface  150  of module  140  and bottom surface  135  of dielectric sheet  125 . Simultaneously, the surfaces of solder columns  120  proximate to top surface  130  of dielectric sheet  125  are brought into contact with corresponding chip pads  105  and the surfaces of solder columns  120  proximate to bottom surface  135  of dielectric sheet  125  are brought into contact with corresponding module pads  145 . Then solder columns  120  are reflowed to form a solder connection, which is both an electrical connection and a physical connection, between chip pads  105  and module pads  145 . Reflow may be accomplished by thermal heating in a furnace in an inert atmosphere or by ultrasonic heating. At the same time, dielectric sheet  125  forms a bond to top surface  110  of integrated circuit chip  100  and a bond to top surface  150  of module  140 . Dielectric sheet, my further cure (e.g., cross-link) during the reflow process. 
         [0028]    As an aid to bonding a plate  156  may be placed on a bottom surface  157  of integrated circuit chip  100  to press the stack consisting of integrated circuit chip  100 , solder bump tape  115  and module  140  together during reflow. As an aid to alignment of chip pads  105 , module pads  145  and solder columns  125 , pins  158  that fit into holes  159  in module  140  may be employed. Either only plate  157  or pins  158  may be used, or both plate  158  and pins  159  may be used. Other alignment devices and methods of pressing the stack together may be used as well. In the event that the perimeter of solder bump tape  125  extends past the perimeter of integrated circuit chip  100 , notches may be provided so dielectric sheet  125  does not touch pins  158 . 
         [0029]      FIG. 4  is a top view of alternative solder bump tape(s) according to embodiments of the present invention. In  FIG. 4 , a central region  160  of dielectric sheet  125  either contains no solder bumps (in this example a 3 by 3 array is missing) or region  160  may comprise an opening in the dielectric sheet (i.e., a region where there are no solder bumps  120  or dielectric material). 
         [0030]      FIG. 5  is cross-sectional view of a first type of solder bump tape  115 A, according to embodiments of the present invention. In  FIG. 5 , top surface  130  of dielectric sheet  125  is essentially coplanar with top surfaces  165  of solder columns  120  and bottom surface  135  of dielectric sheet  125  is essentially coplanar with bottom surfaces  170  of solder columns  120 . 
         [0031]      FIG. 6  is cross-sectional view of a second type of solder bump tape  115 B according to embodiments of the present invention. In  FIG. 6 , a dielectric top adhesive layer  175  is formed on top surface  130  of dielectric sheet  125  and a dielectric bottom adhesive layer  180  is formed on bottom surface  135  of dielectric sheet  125 . An exposed surface  132  of top adhesive layer  175  is essentially coplanar with top surfaces  165  of solder columns  120  and an exposed surface  137  of bottom adhesive layer  180  is essentially coplanar with bottom surfaces  170  of solder columns  120 . In one example, adhesive layers  175  and are heat activated. In one example, dielectric sheet  125  comprises a fully cured material and adhesive layers  175  and  180  comprise a non-fully cured version of the same material as dielectric sheet  125 . In one example, dielectric sheet  125  comprises a fully cured material and adhesive layers  175  and  180  comprise a non-fully cured material different from the material of dielectric sheet  125 . 
         [0032]      FIG. 7  is cross-sectional view of a third type of solder bump tape  115 C according to embodiments of the present invention. In  FIG. 7 , top surfaces  165  of solder columns  120  extend past top surface  130  of dielectric sheet  125  and bottom surfaces  170  of solder columns  120  extend past bottom surface  135  of dielectric sheet  125 . 
         [0033]      FIG. 8  is cross-sectional view of a fourth type of solder bump tape  115 D according to embodiments of the present invention. In  FIG. 8 , top adhesive layer  175  is formed on top surface  130  of dielectric sheet  125  and bottom adhesive layer  180  is formed on bottom surface  135  of dielectric sheet  125 . Top surfaces  165  of solder columns  120  extend past exposed surface  132  of top adhesive layer  175  and bottom surfaces  170  of solder columns  120  extend past exposed surface  137  of bottom adhesive layer  180 . 
         [0034]      FIG. 9  is cross-sectional view of a fifth type of solder bump tape  115 E according to embodiments of the present invention. In  FIG. 9 , top surfaces  165  of solder columns  120  are recessed below top surface  130  of dielectric sheet  125  and bottom surfaces  170  of solder columns  120  are recessed below bottom surface  135  of dielectric sheet  125 . 
         [0035]      FIG. 10  is cross-sectional view of a sixth type of solder bump tape  115 F according to embodiments of the present invention. In  FIG. 10 , top adhesive layer  175  is formed on top surface  130  of dielectric sheet  125  and bottom adhesive layer  180  is formed on bottom surface  135  of dielectric sheet  125 . Top surfaces  165  of solder columns  120  are recessed below exposed surface  132  of top adhesive layer  175  and bottom surfaces  170  of solder columns  120  are recessed below exposed surface  137  of bottom adhesive layer  137 . 
         [0036]      FIG. 11  is cross-sectional view of a seventh type of solder bump tape  115 G according to embodiments of the present invention. In  FIG. 11 , top adhesive layer  175  is formed on top surface  130  of dielectric sheet  125  and bottom adhesive layer  180  is formed on bottom surface  135  of dielectric sheet  125 . Top surfaces  165  of solder columns  120  are recessed below exposed surface  132  of dielectric sheet  125  and bottom surfaces  170  of solder columns  120  are recessed below bottom surface  135  of dielectric sheet  125 . 
         [0037]    Solder bump tapes  115 A and  115 B are examples of solder bump tapes having flush solder columns. Solder bump tapes  115 C,  155 D are examples of solder bump tapes having protruding solder columns. Solder bump tapes  115 E,  115 F and  115 G are examples of solder bump tapes having recessed solder columns. 
         [0038]      FIG. 12  is an exploded detailed cross-sectional/side view of the components of an integrated circuit package according to embodiments of the present utilizing solder bump tape having protruding solder columns. While  FIG. 12  is illustrated with solder bump tape  115 C, it should be understood that solder tape  115 D of  FIG. 8  may be substituted for solder bump tape  115 C in  FIG. 12 . In  FIG. 12 , pads  105  of integrated circuit chip  100  include depressions  185  having a width W 1  (either a diameter W 1  or a square with sides W 1 ). The width of solder columns  120  is W 2  (either a diameter W 2  or a square with sides W 2 ), where W 2  is less than W 1 . Pads  145  of module  140  include depressions  190  having width W 1  (either a diameter W 1  or a square with sides W 1 ). When mechanically assembled, solder columns  125  fit into depressions  185  and  190  offering a degree of self alignment and also ensuring that there is sufficient solder in contact with pads  105  and  145  to ensure a low resistance solder joint after reflow. 
         [0039]      FIG. 13  is an exploded detailed cross-sectional/side view of the components of a integrated circuit package according to embodiments of the present utilizing solder bump tape using recessed solder columns. While  FIG. 13  is illustrated with solder bump tape  115 E, it should be understood that solder tape  115 F of  FIG. 9  or solder bump tape  116 G of  FIG. 11  may be substituted for solder bump tape  115 E in  FIG. 13 . In  FIG. 13 , pads  105  of integrated circuit chip  100  have a width W 3  (either a diameter W 3  or a square with sides W 3 ). The width of solder columns  120  is W 2  (either a diameter W 2  or a square with sides W 2 ), where W 3  is less than W 2 . Pads  145  of module  140  also have a width W 3  (either a diameter W 3  or a square with sides W 3 ). When mechanically assembled, pads  105  and  145  extend past top and bottom surfaces of dielectric sheet  125  to contact top and bottom surfaces  165  and  170  respectively of solder columns  120  offering a degree of self alignment and also ensuring that there is sufficient solder in contact with pads  105  and  145  to ensure a low resistance solder joint after reflow. 
         [0040]    Thus the embodiments of the present invention provide a one-step method of solder bump/underfill flip chip attachment of integrated circuit chips to modules that overcome the deficiencies and limitations described supra. 
         [0041]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example, alternative solder bump tapes could one surface having one of flush, protruding or recessed solder columns and one surface having one surface having flush, protruding or recessed solder column, with the surfaces being different. Similarly, various combinations of surfaces with and without adhesive layers are possible. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.