Abstract:
Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to an electronic circuit with a sample and hold circuit and an analog to digital converter. 
       BACKGROUND 
       [0002]    Time discrete analog to digital conversion of a time dependent analog signal involves sampling of the analog signal by a sample and hold circuit at substantially discrete time points and processing of the sampled analog signals by an analog to digital converter to convert them to digital values. 
         [0003]    Such a circuit may be optimized in various ways. High speed conversion may be realized by parallel conversion of samples for different time points. Because the time needed for conversion is longer than the minimal possible time between taking successive samples, this can be done by means of a demultiplexer between the sample and hold circuit and a plurality of analog to digital converters. Offset effects may be eliminated when using differential circuitry, among others by chopping the signal, i.e. conversion when the signal is applied with different polarity. Inter-sample interference may be eliminated by resetting voltages in the circuit between processing signals for different time points. 
         [0004]    The application of chopping and demultiplexing to time discrete digital to analog conversion is described in an article by Zwei-Mei Lee et al., titled “A CMOS 15-bit 125-MS/s Time Interleaved ADC With Digital Background Calibration”, published in the IEEE Journal of Solid State circuits, Vol 42, No 10, pages 2149-2160. This article discusses offset calibration of an analog to digital converter (ADC). A differential circuit is used, with a differential amplifier in the sample and hold circuit and ADCs with differential inputs. Switches connect the sample and hold circuit to alternate conversion channels. 
         [0005]    A chopper switches the polarity of the connection between the differential amplifier and the differential input of a channel. Each output of the differential amplifier is coupled to each of the differential inputs via first and second switches of the chopper. The first and second switches are alternately made conductive, to reverse the polarity of the coupling from the amplifier to the ADC circuit. Zwei-Mei Lee et al. propose to do this in a pseudo random way during normal operation, to make it possible to determine an offset value from the ADC output, which can be used to correct for the offset. Zwei-Mei Lee et al. combine this with time interleaved conversion by different ADC circuits in parallel, connecting the differential amplifier of the sample and hold circuit alternatively to different ADC conversion pipelines. 
         [0006]    In front of the digital output the circuit typically comprises one or more sampling capacitors to retain the analog voltage of the signal. The sample and hold circuit may comprise a differential amplifier to drive inputs of the analog to digital conversion circuits without affecting the sampled voltage on the sampling capacitors. An op amp may be used for example, which is activated in the hold phase of the sample and hold circuit, to copy charge from the sampling capacitors to further sampling capacitors of the conversion circuit. 
         [0007]    Amplifier reset is described for example in an article by Wenhua Yang et al., titled “a 3-V 340 mW 14-b 75 Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input”, published in the IEEE Journal of Solid State Circuits, Vol. 36 No 12 pages 1931-1936. Amplifier reset reduces inter sample interference and it improves control of the amplifier&#39;s output voltages. Switches connected to the inputs and the outputs of the differential amplifier of the sample and hold circuit are provided, which are made conductive to reset voltages in the circuit. This enables more predictable settling time in the hold phase of operation, and usually faster settling as well, when the voltages start from standard mid values. However, the differential amplifier forms one of the main contributors to power consumption of the circuit, because if has to supply new charging current to its capacitive load at a high rate, for every new sampling time point. The load of the differential amplifier slows down operation. 
       SUMMARY 
       [0008]    Among others, it is an object of the invention to speed up operation of an electronic circuit with an analog to digital converter. 
         [0009]    An electronic circuit according to claim  1  is provided, comprising a sample and hold circuit, an analog to digital converter and switches that enable selectable ones of the outputs of a differential amplifier in the sample and hold circuit to be coupled to a circuit node of the analog to digital converter, for performing analog to digital conversion with selectable polarity. The circuit node may be an internal circuit node of the analog to digital converter or an input circuit node. A control circuit is provided that controls the switches to provide for a passive phase and a transfer phase in which the control circuit makes none and a selected one of the switches conductive respectively. In addition the control circuit provides for a short circuit phase wherein the control circuit makes both switches from the outputs of the differential amplifier to a same circuit node of the analog to digital conversion circuit conductive simultaneously. In this way a reset of the output of the differential amplifier is possible without requiring a large switch directly between the outputs of the differential amplifier. 
         [0010]    In an embodiment wherein a plurality of analog to digital converters is used in parallel, outputs of the differential amplifier being connected with selected polarities to circuit nodes of alternate analog to digital converters, short circuit phases may be provided by making both switches from the outputs of the differential amplifier to the same circuit node of alternate ones of the analog to digital conversion circuit conductive simultaneously. By alternately using different switches to short circuit the outputs of the differential amplifier, a minimum disruption of analog to digital conversion is realized. 
         [0011]    In an embodiment wherein an analog to digital converter with differential circuit nodes for receiving a differential signal is used, short circuits may be realized in the short circuit phase via both differential circuit nodes in parallel. In this way the maximum possible operation speed is raised. 
         [0012]    In an embodiment wherein the sample and hold circuit comprises feedback switches coupled between the outputs of the differential amplifier and its inputs, the control circuit having outputs coupled to inputs of the feedback switches, the control circuit being configured to apply the short circuit phase while making the feedback switches non-conductive. Thus, inter sample interference is reduced. 
         [0013]    In an embodiment no switch is provided that directly couples the first and second outputs of the differential amplifier. Thus, capacitive loading of the differential amplifier is minimized. 
         [0014]    In an embodiment a method of performing analog to digital conversion is provided that comprises
       sampling an input voltage;   generating a differential amplifier output voltage between the first and second output of a differential amplifier in response to the sampled input voltage;   selecting a conversion polarity;   making a first switch from the first output of the differential amplifier or a second switch from the second output of the differential amplifier to a circuit node of an analog to digital conversion circuit conductive dependent on the selected conversion polarity;   making both the first and second switch conductive simultaneously, prior to making the selected one of the first and second switch conductive.       
 
         [0020]    In this way a short circuit current between the outputs of the differential amplifier can be realized using the switches that are provided for polarity reversal, without increasing capacitive load of the differential amplifier for the purpose of supporting this short circuit current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0021]    These and other objects and advantageous aspects will become apparent from a description of exemplary embodiments, using the following figures. 
           [0022]      FIG. 1  shows a time discrete analog to digital conversion circuit 
           [0023]      FIG. 2  shows a timing diagram of control signals 
           [0024]      FIG. 3  shows a control circuit 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0025]      FIG. 1  shows a time discrete analog to digital conversion circuit, comprising a sample and hold circuit  10 , a demultiplexing circuit  12 , a control circuit  14 , a first and second analog to digital conversion chain  16   a,b  and intermediate sampling capacitors  17   a - d . Typically, demultiplexing circuit  12  and intermediate sampling capacitors  17   a - d  are part of an analog to digital conversion chain. The circuit may contain a plurality of such chains in parallel. Sample and hold circuit  10  has inputs  11   a,b  for receiving an input signal to be sampled and an output coupled to an input of demultiplexing circuit  12 . First and second analog to digital conversion chain  16   a,b  have circuit nodes coupled to outputs of demultiplexing circuit  12 . Intermediate sampling capacitors  17   a - d  are coupled from the connections between the analog to digital conversion chain  16   a,b  and demultiplexing circuit  12  to a reference terminal. Control circuit  14  has outputs coupled to control inputs of sample and hold circuit  10 , demultiplexing circuit  12  and a first and second analog to digital conversion chain  16   a,b.    
         [0026]    In operation control circuit  14  controls sample and hold circuit  10  to sample signal voltages at inputs  11   a,b  and to transfer the sampled voltages to the output of sample and hold circuit  10 . Switches in demultiplexing circuit  12  may function as input switches of the first stage of the analog to digital conversion chain and the intermediate sampling capacitors  17   a - d  are sampling capacitors of the first stage. Control circuit  14  controls demultiplexing circuit  12  to feed the output voltages alternatingly to circuit nodes of first and second analog to digital conversion chain  16   a,b , with selectable polarity to realize chopping. First and second analog to digital conversion chains  16   a,b  convert the received signals to digital representations. 
         [0027]      FIG. 2  shows a timing diagram of control signals from control circuit  14 . A first trace  21  shows basic sampling clock timing, defining successive sampling periods wherein falling edges define the sampling time points. A second trace  22  defines alternation between first and second analog to digital conversion chain  16   a,b.    
         [0028]      FIG. 1  shows an embodiment of sample and hold circuit  10  wherein this circuit comprises a first and second sampling capacitor  100   a,b , a differential amplifier  102 , first and second input switches  104   a,b , first and second feedback switches  106   a,b  and first and second reference switches  108   a,b . Each of first and second sampling capacitor  100   a,b  has a first terminal and a second terminal. Control circuit  14  has outputs coupled to control inputs of input switches  104   a,b , feedback switches  106   a,b  and reference switches  108   a,b.    
         [0029]    First and second input switch  104   a,b  are coupled between the first terminal of first and second sampling capacitor  100   a,b  and corresponding ones of the inputs  11   a,b  of the sample and hold circuit  10  respectively. First and second feedback switch  106   a,b  are coupled between the first terminal of first and second sampling capacitor  100   a,b  and corresponding ones of the outputs of differential amplifier  102  respectively. A negative feedback is realized, differential amplifier  102  having negative gain from the ones of its inputs and outputs that are coupled via a sampling capacitor  100   a,b  and a feedback switch  106   a,b . First and second reference switches  108   a,b  are coupled between the second terminal of first and second sampling capacitor  100   a,b  and a reference node  109 . In addition, an optional further switch coupled directly between the second terminals of first and second sampling capacitor  100   a,b  and controlled by control circuit  14  may be provided. 
         [0030]    In operation sample and hold circuit  10  operates alternately in a first and second phase. In the first phase the first terminals of sampling capacitors  100   a,b  are conductively connected to inputs  11   a  by input switches  104   a,b  and the second terminals are conductively connected to reference node  109  by reference switches  108   a,b . Feedback switches  106   a,b  are made non-conductive. Thus, sampling capacitors  100   a,b  are charged dependent on the input signal. The switches may be implemented using conduction channels of transistors, with a control electrode of the transistor as a switch control input. As will be appreciated, in this context conductive and non-conductive refer to the degree of conductivity realized by such switching transistors. 
         [0031]    In the second phase the first terminals of sampling capacitors  100   a,b  are conductively connected to the outputs of differential amplifier  102  by feedback switches  106   a,b . Reference switches  108   a,b  and input switches  104   a,b  are made non conductive. As a result, in the second phase the voltages at the second terminals equal the voltages at the output nodes of the differential amplifier  102  plus the voltages across sampling capacitors  100   a,b , due to earlier charging by the input signal in the first phase. Differential amplifier  102  functions as an op amp that tends to make its differential input voltage zero, so that the voltage difference between its output nodes must equal the differences between the voltages across sampling capacitors  100   a,b.    
         [0032]      FIG. 2  shows the timing of control signals  23 ,  24  for input switches  104   a,b , and feedback switches  106   a,b . A break before make relation is realized between input switches  104   a,b  and feedback switches  106   a,b . Reference switches  108   a,b  are controlled substantially in phase with input switches  104   a,b , but they are preferably made non-conductive with a small lead time interval before input switches  104   a,b . Herein “small” means smaller than the duration between break and make input switches  104   a,b  and feedback switches  106   a,b.    
         [0033]      FIG. 1  shows an embodiment of demultiplexing circuit  12  coupled to a plurality of pairs of circuit nodes  120   a,b  at the output of demultiplexing circuit  12 , each pair of circuit nodes  120   a,b  connected to a respective one of the analog to digital conversion chains  16   a,b . Pairs of intermediate sampling capacitors  17   a,b ,  17   c,d  are provided each intermediate sampling capacitor  17   a - d  with a first terminal coupled to a respective one of the circuit nodes  120   a,b . Each pair of intermediate sampling capacitors  17   a,b  serves retain a sample voltage for a respective one of the analog to digital conversion chains  16   a,b.    
         [0034]    Demultiplexing circuit  12  comprises a plurality of groups  121   a,b  of switches  124 , each for a respective one of the analog to digital conversion chains  16   a,b . Each group  121   a,b  of switches comprises a first and second pair  122   a,b ,  122   c,d  of switches  124 . The switches  124  of the first pair  122   a  in the first group  121   a  are coupled between the outputs of sample and hold circuit  10  and a first and second circuit node  120   a,b  of demultiplexing circuit  12  for the first analog to digital conversion chain  16   a . The switches  124  of the second pair  122   b  of the first group  121   a  are coupled between the outputs of sample and hold circuit  10  and the second and first circuit node  120   a,b  of demultiplexing circuit  12  for the first analog to digital conversion chain  16   a , crosswise compared to the switches  124  of the first pair  122   a . Similar switch connections are provided in the second group  121   b , to the second analog to digital conversion chain  16   b.    
         [0035]    Control circuit  14  has outputs coupled to control inputs of the switches  124  in the groups  121   a,b  of pairs  122   a - d . Furthermore reference switches  126   a,b  are provided, coupling second terminals of the intermediate sampling capacitors  17   a - d  to a reference node. Further switches may be provided, coupled between the second terminals of the intermediate sampling capacitors  17   a,b  for the same analog to digital conversion chain  16   a,b.    
         [0036]    In operation the groups  121   a,b  of pairs  122   a - d  of switches  124  perform a number of functions. A first function involves providing connections in an alternating way to the first and second analog to digital conversion chains  16   a,b  and the intermediate sampling capacitors  17   a - d  at their inputs, by alternately activating switches in the first and second group  121   a,b . A second function involves inverting the polarity of these connections to realize chopping, by activating either the switches of the first pair  122   a ,  122   c  or the second pair  122   b ,  122   d  of the group  121   a,b . A third function involves a short circuit phase wherein switches to a same circuit node  120   a,b  from different pairs  122   a,b ,  122   c,d  in a same group  121   a,d  are made conductive simultaneously, so that in the short circuit phase the outputs of sample and hold circuit  10  are short circuited via a pair of circuit nodes  120   a,b  of de-multiplexing circuit  12 . 
         [0037]      FIG. 2  shows timing of control signals  26   a,b  from control circuit  14  for a group  121   a  of pairs  122   a,b  of switches  124  coupled to circuit nodes  120   a,b  to the first analog to digital conversion chains  16   a,b  and intermediate sampling capacitors  17   a,b . A short circuit phase, a transfer phase and a passive phase can be distinguished. In the short circuit phase, the control signals  26   a,b  are provided to make both pairs  122   a,b  in the group  121   a  conductive (control signals for both pairs  122   a,b  in the group  121   a  both high). In the transfer phase only one of the pairs  122   a,b  of the switches  124  in the group is made conductive, so that each sample and hold circuit  10  output is coupled to a different output node  10   a,b  of demultiplexing circuit  12 . Dependent on the desired polarity either the first pair  122   a  is made conductive and the second pair  122   b  is made non-conductive or the second pair  122   b  is made conductive and the first pair  122   a  is made non-conductive. In the passive phase both pairs  122   a,b  of switches  124  of the group  121   a . are made non-conductive. 
         [0038]    Control signals  27   a,b  similar to the control signals  26   a,b  for the first group  121   a  are provided for the second group  121   b , except that they are shifted in phase, so that the short circuit phase and the transfer phase of the second group occur during the passive phase of the first group and vice versa. 
         [0039]    As can be seen control circuit  14  provides for successions of a short circuit phase and a normal operation phase, by providing for a high control signal for a pair  122   a  of switches  124  of a group  121   a  during both the short circuit phase and the transfer phase and a high control signal for the other pair  122   b  of switches  124  of the group  121   a  only during the short circuit phase. Control circuit  14  makes the short circuit phase coincide with the operation phase of sample and hold circuit  10  wherein input switches  104   a,b  are conductive, and feedback switches  106   a,b  are non-conductive. Thus, the amplifier output voltages are equalized. 
         [0040]    When a reverse polarity connection between sample and hold circuit  10  and the circuit nodes  120   a,b  of demultiplexing circuit  12  for an analog to digital conversion chain is required, the roles of the pairs of switches in the group are exchanged. The pair of switches that was made conductive only in the short circuit phase for normal polarity is made conductive during both the short circuit phase and the transfer phase, and the other pair of switches, which was made conductive during both the short circuit phase and the transfer phase for normal polarity, is made conductive only in the short circuit phase. 
         [0041]    Control circuit  14  makes the transfer phase last during the phase wherein feedback switches  106   a,b  of sample and hold circuit are conductive. Thus, differential amplifier  102  charges intermediate sampling capacitors  17   a,b  in this phase. Control circuit  14  makes reference switches  126   a,b  conductive substantially during the succession of the short circuit phase and the transfer phase. Preferably control circuit  14  makes reference switches  126   a,b  non-conductive in advance of the succession by a small lead time interval, similar to the small lead time interval of the reference switches in sample and hold circuit  10 . 
         [0042]    Control circuit  14  alternates successions of a short circuit phase and a transfer phase for the circuit nodes  120   a  to the first and second analog to digital conversion chains  16   a,b . In this way, voltages in the other chain are not disturbed. 
         [0043]    Preferably, no switch is provided coupled directly between the outputs of differential amplifier  102 . When the outputs are short circuited, this is always done via at least one circuit node  120   a,b  through switches  124  to those output nodes. Thus, the capacitive load of the outputs of the differential amplifier is kept at a minimum, which improves maximum possible circuit speed. In another embodiment a small additional switch may be used between the output, for example to help the short circuit, the switches  124  taking care of at least half of the short circuit current via circuit nodes  120   a,b . Because the additional switch can be kept small, this also allows for improved maximum possible output speed. 
         [0044]      FIG. 3  shows an embodiment of control circuit  14 , comprising a first and second pulse shaping circuit  30   a,b , a divider  34 , third and fourth pulse shaping circuits  36   a,b  and AND gates  38   a - d . Control circuit  14  has a clock input  31  and a polarity selection input  39 . Clock input  31  is coupled to divider  34  and to first and second pulse shaping circuit  30   a,b , the latter after inversion. First pulse shaping circuit  30   a  has an output coupled to control inputs of input switches  104   a,b  (not shown) and reference switches  108   a,b  (not shown), the former via an optional delay circuit. Second pulse shaping circuit  30   b  has an output coupled to control inputs of feedback switches  106   a,b  (not shown). Pulse shaping circuits  30   a,b  are designed to provide for break before make behavior. A pulse shaping circuit may comprise an AND gate for example with one input coupled directly to the input of the pulse shaping circuits  30   a  and the other via a delay circuit, the output of the AND gate forming the output of the pulse shaping circuit. 
         [0045]    Divider  34  has opposite phase outputs coupled to control inputs of pairs of switches in different groups in demultiplexing circuit  12  via AND gates  38   a - d . Each divider output is coupled to a first input of a first and second one of the AND gates  38   a - d , which have outputs coupled to the control inputs of the switches  124  of the pairs  122   a - d  of switches in the groups  121   a,d . Second inputs of AND gates  38   a - d  are coupled to polarity selection input  39 , AND gates  38   a - d  for pairs of switches in the same group receiving polarity selection signals of mutually opposite logic level. The outputs of AND gates  38   a - d  are coupled to control inputs pairs of switches in of the groups of switches. Control circuit  10  may comprise further circuits (not shown) to generate control signals for analog to digital conversion chains  16   a,b  (not shown). 
         [0046]    In operation this embodiment control circuit  14  realizes the control signals shown in  FIG. 2 . However, it should be realized that many different embodiments can be used to realize similar signals. 
         [0047]    Although an embodiment with two analog to digital conversion chains  16   a,b  has been described, it should be appreciated that more chains may be used in parallel. Thus more time is made available for analog to digital conversion. In this case control circuit may be configured to provide successions of a short circuit phase and a transfer phase successively for each different analog to digital conversion chain in a cyclical manner. In an embodiment a single analog to digital conversion chain may be used, in which case demultiplexing circuit  12  need only provide for polarity reversal and not for switching to different chains. In this case the same group of pairs of switches is always made conductive in the short circuit phase. However, in this case the multiplexed output sample rate is limited to the conversion speed of the analog to digital conversion chain. 
         [0048]    Although an embodiment has been described wherein the analog to digital conversion chains  16   a,b  have differential inputs, alternatively analog to digital conversion chains  16   a,b  with single ended inputs may be used. In this case the pairs  122   a - d  of switches  124  may each be replaced by a single switch  124 , so that each group  121   a,d  comprises switches from the single ended input of an analog to digital conversion chain  16   a,b  to both outputs of differential amplifier  102 . 
         [0049]    In this embodiment, a short circuit between the outputs of the differential amplifier  102  is realized by the single switches in the group. In another embodiment, a similar short circuit may be applied also when the analog to digital conversion chains  16   a,b  have differential inputs. In this embodiment, only one of the switches  124  of each pair  122   a - d  of a group  121   a,b  needs to be made conductive in the short circuit phase, the other being made non-conductive, selecting the switches so that switches  124  to a same input of the corresponding analog to digital conversion chains  16   a  are made conductive simultaneously. 
         [0050]    However, the simultaneous conductivity of both switches in each pair of a group in the short circuit phase has the advantage that the charges on intermediate sampling capacitors are also equalized in the short circuit phase, which reduces the risk of inter sample interference without requiring additional switches. 
         [0051]    Although one possible embodiment of sample and hold circuit has been shown by way of example, it should be appreciated that other sample and hold circuits could be used. For example, a charge redistribution circuit as disclosed in  FIG. 2   a  of the article by Wenhua Yang may be used. Herein the sample and hold circuits has two series arrangements of capacitors, with interior nodes between the capacitors in the series arrangements coupled to the inputs of a differential amplifier. In the charge redistribution circuit the differential amplifier has feedback switches coupled from its output to the series arrangements and a control circuit to make the feedback switches in a hold phase. In the hold phase the differential amplifier drives the voltage at the intermediate sampling capacitors in parallel with the voltage across the series arrangements, to equalize the voltages at the interior nodes. In this embodiment a multiplexing circuit like demultiplexing circuit  12  may be used to provide for switching between connections to different conversion circuits, polarity reversal for chopping, and short circuiting the amplifier outputs in a time interval wherein the feedback switches are non-conductive. 
         [0052]    Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.