Abstract:
A method and apparatus for interconnecting multiple programmable logic devices. In a preferred embodiment of the invention, an interconnect chip couples one programmable logic device to another programmable logic device. The interface between devices takes place within the interconnect chip, which can be configured using available routing software, thereby sparing the user the task of routing the connections between devices on the board.

Description:
This application claims the benefit of a provisional application No. 60/022,131, filed Jul. 18, 1996, which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to the field of integrated circuits and their operation. More specifically, in one embodiment the invention provides an interconnect chip to couple a plurality of programmable logic devices to each other. 
     Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user. 
     Altera&#39;s FLEX® and MAX® lines of programmable logic are among the most advanced and successful programmable logic devices. In the FLEX® 8000 logic devices, for example, a large matrix of logic elements (LEs) is utilized. In one commercial embodiment of such devices, each LE includes a 4-input look-up table for performance of combinational logic (e.g., AND, OR, NOT, XOR, NAND, NOR, and many others) and a register that provides sequential logic features. 
     The LEs are arranged in groups of, for example, eight to form larger logic array blocks (LABs). The LABs contain, among other things, a common interconnection structure. The various LABs are arranged in a two-dimensional array, with the various LABs connectable to each other and to pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as row interconnect (GH) and column interconnect (GV) or “global” interconnect lines. 
     The MAX® 7000 logic devices by way of contrast utilize what are commonly referred to as “macrocells” (analogous to LEs) as a basic logic element. The macrocells are arranged in groups of, for example, sixteen to form larger logic array blocks (LABs). A programmable interconnect array (PIA) selectively links together the multiple LABs. The PIA is a global bus that is fed by all dedicated inputs, I/O pins, and the various macrocells. The PIA is analogous to global interconnect, GHs and GVs. For example, the PIA may be fed by signals that will be used as logic inputs, global controls for secondary register functions in the LABs, input paths from I/O pins to registers that are used for setup of the device, etc. 
     Inputs to the LABs include inputs from pins (via I/O control blocks), the PIA, and various control (e.g. clock) pins. Logic inputs are provided to one or more of five AND devices, the outputs of which are provided to a product term select matrix. The product term select matrix selects which inputs will be provided to an OR or XOR function, or as secondary inputs to registers in the macrocell. Product terms may be shared between macrocells for complex logic functions. Outputs from the LABs are provided to the I/O control block to the PIA and/or various output pins. 
     The FLEX® and MAX® programmable logic devices have met with substantial success and are considered pioneering in the area of programmable logic. In fact, designers are increasingly using multiple FLEX® and MAX® devices, or even an entire array of programmable logic devices, to implement functions that are too large to be supported by a single programmable logic device. For example, it would be quite typical for a hardware designer to emulate a complex system in an array of programmable logic devices as a prototype before implementing the tested design in an application specific integrated circuit (ASIC) for production. In order to use multiple devices, the designer must find ways to overcome several hurdles, including partitioning the design into smaller portions to be parceled out among the multiple devices, finding an optimum placement for the multiple devices on a circuit board, and routing the connections between devices. 
     These steps need to be repeated each time there is a change in the system design. Currently, there is partitioning software that breaks a design up into smaller pieces in a logical manner to divide the design among several programmable logic devices. However, the other tasks of placing and routing among devices are left to the user of the devices. When using a single programmable logic device, the user may simply leave the tasks of placing and routing logic cells to the appropriate routing software, such as, for example, Altera&#39;s MAXPlus+® software package. But on a system level, there is currently no such device or software to ease the job of the designer in a similar fashion. 
     Thus, a need clearly exists for a device to interconnect multiple programmable logic devices that does not place the entire burden on the user. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and apparatus for interconnecting multiple programmable logic devices. In a preferred embodiment of the invention, an interconnect chip couples one programmable logic device to another programmable logic device. The interface between devices takes place within the interconnect chip, which can be configured using available routing software, thereby sparing the user the task of routing the connections between devices on the board. 
     A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows an exemplary array of programmable logic devices connected by a plurality of interconnect chips according to the present invention. 
     FIG. 2 shows a detailed block-level diagram of an interconnect chip according to the present invention. 
     FIG. 3 shows the use of a PLD array and associated interconnect chips according to the present invention in an exemplary data processing system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows an exemplary array  100  of programmable logic devices connected by a plurality of interconnect chips according to the present invention. Merely by way of example, the programmable logic devices may be Altera&#39;s FLEX® 8000 or FLEX® 10000 devices, as shown in the figure, but clearly other programmable logic devices may be implemented with the present invention. In FIG. 1, programmable logic devices (PLD)  102  are arranged in an array and are coupled by horizontal conductors  104  and vertical conductors  106 . In the embodiment shown, each programmable logic device has a corresponding interconnect chip  108  coupling the device to conductors  104  and  106 . In alternate embodiments, there may be one interconnect chip  108  that couples multiple programmable logic devices  102  to the conductor network. The optimal number of conductors  104  and  106  needed to connect the array of programmable logic devices  102  may be calculated by Rent&#39;s Rule, which is the well-known rule used to predict wire counts. 
     In a preferred embodiment, interconnect chip  108  may be programmably coupled to horizontal conductors  104  by connectors  110 . Similarly, interconnect chip  108  may be programmably coupled to vertical conductors  106  by connectors  112 . Interconnect chip  108  then couples conductors  104  and  106  to programmable logic device  102  through connectors  114 . An optional diagnostic bus  116  may be added to directly couple all interconnect chips  108  serially. Interconnect chip  108  could also provide an interface to external memory, such as a RAM (not shown), if desired. Alternately, some other RAM interface could be employed in conjunction with the interconnect chip. 
     FIG. 2 shows a more detailed block-level diagram  200  of an interconnect chip  108 . As noted above, interconnect chip  108  is coupled to a programmable logic device  102  (such as a FLEX device) by connectors  114 . Connectors  110  couple interconnect chip  108  to the horizontal network of conductors (shown in FIG.  1 ), while connectors  112  couple interconnect chip  108  to the vertical network of conductors. 
     Input driver block  202  includes an interface to input signals from the horizontal and vertical conductors to programmable logic device  102 . Input driver block  202  will typically be implemented by a partially populated crossbar switch to allow for programmable interconnections. In a preferred embodiment, each global conductor  104  and  106  has two access paths to PLD  102  through the crossbar switch. Output driver block  204  is used to output signals from programmable logic device  102  to the network of horizontal and vertical conductors. In one embodiment, each output from PLD  102  can be sent to two horizontal conductors  104  and two vertical conductors  106  through output driver block  204 . The number of connections between conductors  104 ,  106  and PLD  102  may of course be changed in alternate embodiments. Additionally, horizontal conductors  104  are coupled to vertical conductors  106  through interface blocks  202  and  204 . 
     Interconnect chip  108  also may include a diagnostic interface block  206  that is coupled to diagnostic bus  116  (FIG. 1) through JTAG port  208  for testing purposes. Furthermore, a memory interface block  210  may be included to provide a high speed interface to an external memory block  212  that may be, for example, a large block of system RAM. 
     As noted above, when using a single programmable logic device, the user may simply leave the tasks of placing and routing logic cells to the appropriate routing software, such as, for example, Altera&#39;s MAXPlus+® software package. A key advantage of interconnect chip  108  of the present invention is that the user may employ the same (or very similar) routing software algorithms used for a single PLD to route the connections between PLDs  102  through interconnect chips  108 , even though the connections are being made on a system level. Interconnect chip  108  eliminates routing problems that might arise from random pin assignments in the PLDs, since the multiplexing structure in interconnect chip  108  is more fully populated than the multiplexing structure internal to a programmable logic device  102 . First, the design is partitioned into rows of PLDs  102 , based on the number of logic elements and number of pins required. The PLDs  102  are then arranged by rows to minimize the vertical interconnect. The multiplexer allocator completes the routing at the board level across the global horizontal and vertical conductors  104  and  106 . The overall utilization of each PLD  102  is improved because input/output resources of a PLD are not used for routing signals across the board. Instead, interconnect chip  108  handles this function, freeing up space in each PLD  102  for logic functions. This has the added benefit of possibly reducing the overall number of PLDs  102  required for any given design. 
     FIG. 3 illustrates the use of a PLD array  100  and associated interconnect chips  108  (shown in FIG. 31) of the present invention in an exemplary data processing system  300 . Data processing system  300  may include one or more of the following components: a processor  302 , memory  304 , I/O circuitry  306 , and peripheral devices  310 . These component are coupled together by a system bus  312  and are contained in an end-user system  314 . 
     Data processing system  300  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using reprogrammable logic is desirable. PLD array  100  may be used to implement a processor or controller that works in cooperation with processor  302 . PLD array  100  may also be used as an arbiter for arbitrating access to a shared resource in system  300 . In yet another example, PLD array  100  may be configured as an interface between processor  302  and one of the other components in system  300 . The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.