Abstract:
An integrated processor is provided having functional unit tracking and monitoring capabilities. The processor core is configured to read configuration data and provide it to a configuration register. The configuration register enables various functional units also integrated onto the integrated processor. A tracking register is further provided, wherein the tracking register maintains a copy of the configuration data and a copy of the integrated processor&#39;s version number. The version number and the configuration data are provided to an external pin for monitoring.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to integrated circuits and, particularly, to a system and method for enabling functional units. 
     2. Description of the Related Art 
     Integrated processors are data processing devices having both a processor core and peripheral devices, or functional units, of various types. The processor core and the functional units are typically interconnected via a common bus. Because both the processor core and the functional units are implemented on a single integrated circuit, integrated processors are useful for cost sensitive control functions. 
     Integrated processors frequently operate in a variety of modes but may be customized for individual applications. For example, one or more functional units may be selected to be active. Such integrated processors typically have their modes customized through bits stored in nonvolatile memory. These bits are collectively referred to as the configuration register. The configuration bits can be programmed at the same time the on-chip non-volatile memory is programmed and thus the integrated processor may be customized for the application. The configuration bits form signals which are continuously driven to various circuits to select the operating modes. 
     Much of the cost savings associated with integrated processors is the ability to fabricate a plurality of functional units onto a single chip. Frequently, however, such functional units implement features developed by third party vendors. As such, the integrated processor manufacturer must typically pay a royalty for each chip produced. Often, however, not all of the on-chip functional units are enabled. In this case, it is undesirable for the chip manufacturer to pay a royalty for an unused functional unit. At the same time, however, the third party vendor desires confirmation of whether its functional unit is implemented on a chip before agreeing to accept a lower royalty or no royalty at all on that chip. 
     As such, there is a need for monitoring which functional units on an integrated processor are implemented. 
     SUMMARY OF THE INVENTION 
     These and other drawbacks in the prior art are overcome in large part by a system and method according to the present invention. Briefly, an integrated processor is provided having an integrated processor core. The processor core is configured to read configuration data and provide it to a configuration register. The configuration register enables various functional units also integrated onto the integrated processor. A tracking register is further provided, wherein the tracking register maintains a copy of the configuration data and a copy of the integrated processor&#39;s version or serial number. The version number and the configuration data are provided to an external pin for monitoring. 
     Further, a checking circuit is provided to monitor that the external pin is not being externally overdriven. If it is, the functional units are all disabled. A CHECK control signal is provided to a tri-state output driver, which drives the check pin. When the tri-state output driver is active, the contents of the tracking register may be output via the pin. When the tri-state output driver is deactivated, a checking selection circuit monitors the condition of the pin. If the pin is being externally driven, a DISABLE control signal is generated. 
     A monitoring environment according to an embodiment of the present invention permits the collection of a database associating integrated processor serial numbers and activated or enabled functional units. The monitoring environment may further be used to check if particular integrated processors are, in practice, employing only the correct functional units. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A better understanding of the invention is obtained when the following detailed description is considered in conjunction with the following drawings in which: 
     FIG. 1 is a diagram illustrating an integrated processor according to an embodiment of the invention; 
     FIG. 2 is a diagram illustrating a checking circuit according to an embodiment of the invention; 
     FIG. 3 is a diagram of a monitoring environment according to an embodiment of the invention; 
     FIG. 4 is a flowchart illustrating a method according to an embodiment of the invention; and 
     FIG. 5 is a flowchart illustrating a method according to another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1-5 illustrate a functional unit tracking and enabling system and method for an integrated processor. The functional unit tracking and enabling method allows for specific functional units to be configured for operation, and to report which functional units are then active. Thus, the manufacturer can track use of third party vendors&#39; components. 
     Turning now to FIG. 1, an integrated processor according to an embodiment of the present invention is illustrated therein and generally identified by the reference numeral  100 . An exemplary integrated processor is the TriCore family of processors, available from Infineon Technologies Corporation. The integrated processor  100  may be coupled via an address and bidirectional data bus to a read only memory (ROM)  104  which stores configuration data  106 . For example, the configuration data  106  may include one or more bits to activate various of the functional units  110   a-   110   n , as will be explained in greater detail below. 
     The integrated processor  100  includes a processor core  102 . The processor core  102  may be any of a variety of microcontroller or digital signal processor cores, such as those available from Infineon Technologies Corporation. The processor core  102  is coupled to a configuration register  112 . 
     The configuration register  112  stores the configuration data from the ROM  106 . The configuration register  112  is coupled to provide enable signals to one or more functional units  110   a ,  110   b , . . . ,  110   n . In particular, the configuration data  106  stored in the configuration register  112  is used to derive enable signals to selectively enable one or more of the functional units  110   a , . . . ,  110   n.    
     The integrated processor  100  further includes a tracking register  114 . The tracking register  114  stores a chip version or serial number  116  and a copy of the configuration register data  118 . The chip version number  116  and the configuration register data  118  may be read out serially via a pin  122 . Thus, the enablement of particular functional units may be monitored. Non-active functional units need not necessarily have to have a royalty paid thereon, and the licensor can be assured that it is being paid a royalty whenever the functional unit is used. Further, a checking circuit  120  is provided to monitor that the pin  122  is not being externally over-driven. In this case, all functional units are automatically disabled. 
     For example, an exemplary checking circuit  120  is illustrated in greater detail in FIG.  2 . As shown, a pin  122  provides a node for connection between circuitry inside the chip and outside the chip. The checking circuit  120  further includes a tri-state output driver  124  and check selection circuit, such as an AND gate  126 . The tri-state output driver  124  receives as an input the tracking register output along line  127  and a CHECK signal along line  129 . The CHECK signal may be provided from the processor core  102 . 
     The tri-state output driver  124  is capable of providing an output on line  128  of one (1), zero (0) or high impedance. When the output is one (1), the output of pin  122  is one (1). When the output is zero (0), the output of pin  122  is zero (0). When the CHECK signal, available from the processor core (FIG. 1) causes the output to be high impedance, the AND gate  126  is provided with both the CHECK signal and whatever signal is present on the line  128 . Thus, if a signal is applied externally to the pin  122 , the AND gate  126  will provide a DISABLE signal to one or more functional units. 
     The integrated processor  100  is thus suited for use in a monitoring environment  1000 , as shown in FIG.  3 . The monitoring environment  1000  is configured to test various integrated processors  100  and read the contents of their tracking registers  114 . The monitoring environment  1000  then maintains a database of serial numbers and enabled functionality. As shown, the monitoring environment  1000  includes a computer  1002 . The computer  1002  may be any of a variety of computers, such as a PC or PC compatible computer. The computer  1002  includes a controller card  1004  which communicates via a bus  1006 , such as a serial bus, with a test board  1008 . The test board  1008  includes a fixture  1010  for receiving the integrated processor  100  (FIG.  1 ). The test board  1008  and the control card  1004  include any necessary circuitry to emulate a working environment for the integrated processor  100 . 
     The control card  1004  thus is configured to receive the output of pin  122  (FIG. 1) and store it in a database in memory  1012 . The memory  1012  is a hard disk or other memory. Such a control card  1004 , for example, may be a development card used to simulate a working environment for the integrated processor. In addition, the monitoring environment  1000  may be programmed to compare the read out serial number and configuration data with the data already stored in the database in memory  1012 . The monitoring environment  1000  can thus be employed to check the use of various functional units. 
     A flowchart illustrating operation of an embodiment of the present invention is shown in FIG.  4 . Upon reset, the processor core  102  loads configuration data from the ROM  104  to the configuration register  112 , in a step  302 . In addition, the processor core  102  may activate a timer (not shown) which controls the periodic reading out of the contents of the tracking register  114 . In a step  304 , the contents of the configuration register  112  are used to enable various of the functional units  110   a  . . .  110   n . In a step  306 , the check circuit  120  is activated. For example, the CHECK line  129  is activated so that the output of the tri-state driver  124  is high impedance. In a step  308 , the contents of the configuration register  112  are copied to the register  118 . If the timer expires, in a step  310 , then in a step  312 , the check circuit is deactivated; otherwise, the timer continues its countdown. Then, in a step  314 , the contents of the register  118  and the serial number  116  are read out the pin  122 . Once this has been accomplished, the check circuit  120  is reactivated, in a step  316 , and the timer is reset. 
     While the timer&#39;s count is ongoing, the check circuit detects whether the pin  122  is being externally driven, in a step  318 . If so, then in a step  320 , the check circuit sends a DISABLE signal to the processor core  102 . The processor core  102  then causes the functional unit(s) to be disabled, in a step  322 . 
     A flowchart illustrating operation of a monitoring environment according to an embodiment of the invention is shown in FIG.  5 . In a step  502 , serial numbers and corresponding data concerning enabled functional units are stored in a database, for example, by the manufacturer. In a step  504 , one or more of the integrated processor chips may be pulled from a product or production line and tested (i.e., have their tracking register read out) to determine whether the functional unit information is correct. In a step  506 , the read out information is compared with the information stored in the database in step  502 . If the information is determined to be correct, as determined in a step  508 , the information may be logged and the process ends. However, if the information does not check, then in a step  510 , the chip is flagged and the monitoring system alerts the operator.