Abstract:
A semiconductor device may include: a plurality of source-side half channels positioned in a first region and arranged in first to 2Nth rows, wherein N is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to Nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to Nth rows; a plurality of first pipe channels suitable for connecting the first to Nth rows of source-side half channels to the first to Nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting the (N+1)th to 2Nth rows of source-side half channels to the first to Nth rows of second drain-side half channels, respectively.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2015-0005911, filed on Jan. 13, 2015, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    This patent document relates to a semiconductor device, and more particularly, to a three-dimensional (3D) nonvolatile memory device. 
         [0004]    2. Description of the Related Art 
         [0005]    A nonvolatile memory device maintains its stored data even without a constant source of power. Recently, the improvement in integration of two-dimensional (2D) memory devices, which are fabricated in a single layer over a silicon substrate, has reached its limit. Thus, a 3D nonvolatile memory device has been proposed, including memory cells which are vertically stacked over a silicon substrate. 
         [0006]      FIG. 1  is a perspective view illustrating a conventional 3D nonvolatile memory device. To simplify the description, interlayer dielectric layers are not illustrated in  FIG. 1 . 
         [0007]    Referring to  FIG. 1 , the 3D nonvolatile memory device includes a pipe channel PCH, a source-side half channel SCH, and a drain-side half channel DCH. The pipe channel PCH is buried in a pipe gate PG, and the source-side half channel SCH and the drain-side half channel DCH are connected to the pipe channel PCH. The source-side half channel SCH, the pipe channel PCH, and the drain-side half channel DCH form one full channel CH. 
         [0008]    The memory device further includes source-side word lines S_WL and drain-side word lines D_WL. The source-side word lines S_WL are stacked while surrounding the source-side half channel SCH, and the drain-side word lines D_WL are stacked while surrounding the drain-side half channel DCH. The source-side word lines S_WL and the drain-side word lines D_WL are extended in parallel to a first direction I-I′. Furthermore, a source select line SSL is provided over the source-side word lines S_WL, and a drain select line DSL is provided over the drain-side word lines D_WL. 
         [0009]    At this time, source-side channels SCH of strings ST 0  and ST 1  adjacent in a second direction II-II′ are commonly connected to one source line SL, and drain-side channels DCH of the strings ST 0  and ST 1  are commonly connected to one bit line BL. 
         [0010]    According to the above-described structure, however, word lines S_WL and D_WL that are narrow in width are stacked high. Thus, the stacked structure of the word lines may tilt. Furthermore, when a memory device is fabricated, stacked interlayer dielectric layers and conductive layers must be etched to form slits between a pair of source-side channel SCH and drain-side channel DCH forming one channel CH that is between the respective channels CH. Thus, the slits have a narrow width, and the difficulty level of the etching process increases. Furthermore, as the integration of the memory device increases, the number of word lines that need to be stacked further increases. Thus, the stacked structure of the word lines may tilt more, increasing the difficult of the etching process. 
       SUMMARY 
       [0011]    Various embodiments are directed to a technology capable of reducing the numbers of slits and word lines in a 3D nonvolatile memory device, thereby improving stability, to avoiding tilting, and increasing integration. 
         [0012]    In an embodiment, a semiconductor device may include: a plurality of source-side half channels positioned in a first region and arranged in first to 2Nth rows, wherein N is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to Nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to Nth rows; a plurality of first pipe channels suitable for connecting the first to Nth rows of source-side half channels to the first to Nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting the (N+1)th to 2Nth rows of source-side half channels to the first to Nth rows of second drain-side half channels, respectively. 
         [0013]    Each of the source-side half channels may be offset from centers of the source-side half channels included in adjacent rows. Each of the first drain-side half channels may be offset from centers of the first drain-side half channels included in adjacent rows. Each of the second drain-side half channels may be offset from centers of the second drain-side half channels included in adjacent rows. 
         [0014]    The first to Nth rows of source-side half channels, the first drain-side half channels, and the first pipe channels may form first to Nth memory strings, respectively, and the (N+1)th to 2Nth rows of source-side half channels, the second drain-side half channels, and the second pipe channels may form (N+1)th to 2Nth memory strings, respectively. 
         [0015]    The plurality of source-side half channels may be controlled through a source select line, the plurality of first drain-side half channels may be controlled through a first drain select line, and the plurality of second drain-side half channels may be controlled through a second drain select line. 
         [0016]    The plurality of source-side half channels may share a plurality of first word lines, and the first drain-side half channels and the second drain-side half channels may share a plurality of second word lines. 
         [0017]    Each of the plurality of first pipe channels and the plurality of second pipe channels may be formed to have a different depth than adjacent pipe channels. 
         [0018]    The plurality of first pipe channels and the plurality of second pipe channels may have the same length. 
         [0019]    The plurality of first drain-side half channels and the first to Nth rows of source-side half channels may be formed at symmetric positions based on a boundary surface between the first and second regions, and the plurality of second drain-side half channels and the (N+1)th to 2Nth rows of source-side half channels may be formed at symmetrical positions based on a boundary surface between the first and third regions. 
         [0020]    The plurality of first drain-side half channels and the first to Nth rows of source-side half channels, which are formed at the symmetric positions based on the boundary surface between the first and second regions, may be connected through the plurality of first pipe channels, respectively, and the plurality of second drain-side half channels and the (N+1)th to 2Nth rows of source-side half channels, which are formed at the symmetric positions based on the boundary surface between the first and third regions, may be connected through the plurality of second pipe channels, respectively. 
         [0021]    Each of the plurality of first pipe channels and the plurality of second pipe channels may have a different depth than adjacent pipe channels. 
         [0022]    Each of the plurality of first pipe channels and the plurality of second pipe channels may have a different length than adjacent pipe channels. 
         [0023]    The semiconductor device may further comprise a plurality of bit lines each connected to a corresponding one of the first drain-side half channels and a corresponding one of the second drain-side half channels. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a perspective view illustrating a conventional 3D nonvolatile memory device. 
           [0025]      FIGS. 2A to 2E  are layout diagrams and perspective views illustrating a nonvolatile memory device in accordance with an embodiment of the present invention. 
           [0026]      FIG. 3  is a circuit diagram illustrating the nonvolatile memory device illustrated in  FIGS. 2A to 2E . 
           [0027]      FIGS. 4A to 4C  are layout diagrams illustrating a nonvolatile memory device in accordance with another embodiment of the present invention. 
           [0028]      FIGS. 5A to 5C  are layout diagrams illustrating a nonvolatile memory device in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0030]    The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to where the first layer is formed directly on the second layer or the substrate but also to where a third layer exists between the first layer and the second layer or the substrate. 
         [0031]      FIGS. 2A to 2E  are diagrams illustrating a structure of a nonvolatile memory device in accordance with an embodiment of the present invention. 
         [0032]      FIGS. 2A to 2C  are layout diagrams illustrating the nonvolatile memory device in accordance with an embodiment of the present invention.  FIGS. 2A to 2C  illustrate first drain-side half channels DCH 00  to DCH 11 , source-side half channels SCH 00  to SCH 23 , and second drain-side half channels DCH 12  to DCH 23 , which are arranged in first to eighth rows, respectively.  FIG. 2A  illustrates first pipe channels PCH 00  to PCH 11  and second pipe channels PCH 12  to PCH 23 .  FIG. 2B  illustrates a source select line SSL, a first drain select line DSL 0 , a second drain select line DSL 1 , and bit lines BL 0  to BL 11 .  FIG. 2C  illustrates first word lines WL 0  to WL 3  and second word lines WL 4  to WL 7 . 
         [0033]    Referring to  FIG. 2A , the source-side half channels SCH 00  to SCH 23  may be arranged in four rows, i.e., the third to sixth rows. Each of the source-side half channels SCH 00  to SCH 23  may be offset from centers of the source-side half channels included in the adjacent rows. For example, the source-side half channels SCH 00  to SCH 05  included in the third row may be at different positions than the source-side half channels SCH 06  to SCH 11  included in the fourth row, based on the first direction I-I′. Similarly, the source-side half channels SCH 12  to SCH 17  included in the fifth row may be arranged at different positions than the source-side half channels SCH 06  to SCH 11  included in the fourth row adjacent to the fifth row and the source-side half channels SCH 18  to SCH 23  included in the sixth row adjacent to the fifth row, based on the first direction I-I′. 
         [0034]    The first drain-side half channels DCH 00  to DCH 11  may be arranged in two rows, i.e., the first and second rows, at one side II′ of a region where the source-side half channels SCH 00  to SCH 23  are positioned, based on the second direction II-II′. Each of the first drain-side half channels DCH 00  to DCH 11  may be offset from centers of the first drain-side half channels included in the adjacent row. For example, the first drain-side half channels DCH 00  to DCH 05  included in the first row may be arranged at different positions than the first drain-side half channels DCH 06  to DCH 11  included in the second row, based on the first direction I-I′. 
         [0035]    The second drain-side half channels DCH 12  to DCH 23  may be arranged in two rows, i.e., the seventh and eighth rows, at the other side II of the region where the source-side half channels SCH 00  to SCH 23  are positioned, based on the second direction II-II′. Each of the second drain-side half channels DCH 12  to DCH 23  may be offset from centers of the second drain-side half channels included in the adjacent row. For example, the second drain-side half channels DCH 12  to DCH 17  included in the seventh row may be arranged at different positions than the second drain-side half channels DCH 18  to DCH 23  included in the eighth row, based on the first direction I-I′. 
         [0036]    The first pipe channels PCH 00  to PCH 11  may connect the source-side half channels SCH 00  to SCH 11  in the third and fourth rows to the first drain-side half channels DCH 00  to DCH 11  in the first and second rows, respectively. Each of the first pipe channels PCH 00  to PCH 11  may have a different depth than adjacent pipe channels. For example, the first pipe channel PCH 00  may have a depth shallower than the first pipe channels PCH 06  and PCH 07  adjacent to the first pipe channel PCH 00 . The first drain-side half channels DCH 00  to DCH 11  and the source-side half channels SCH 00  to SCH 11 , which are connected through the first pipe channels PCH 00  to PCH 11 , may form full channels, respectively. For example, the first drain-side half channel DCH 03 , the first pipe channel PCH 03 , and the source-side half channel SCH 03  may form one full channel or a string. 
         [0037]    The second pipe channels PCH 12  to PCH 23  may connect the source-side half channels SCH 12  to SCH 23  in the fifth and sixth rows to the second drain-side half channels DCH 12  to DCH 23  in the seventh and eighth rows, respectively. Each of the second pipe channels PCH 12  to PCH 23  may be formed to have a different depth than adjacent pipe channels. For example, the second pipe channel PCH 12  may be shallower than the second pipe channels PCH 18  and PCH 19  adjacent to the second pipe channel PCH 12 . The second drain-side half channels DCH 12  to DCH 23  and the source-side half channels SCH 12  to SCH 23 , which are connected through the second pipe channels PCH 12  to PCH 23 , may form full channels, respectively. For example, the second drain-side half channel DCH 20 , the second pipe channel PCH 200 , and the source-side half channel SCH 20  may form one full channel or a string. 
         [0038]    Referring to  FIG. 2B , the source-side half channels SCH 00  to SCH 23  may share the source select line SSL. The source select line SSL may be formed to surround the source-side half channels SCH 00  to SCH 23 . The electrical coupling between the source-side half channels SCH 00  to SCH 23  and a source line SL may be controlled through the source select line SSL. 
         [0039]    The first drain-side half channels DCH 00  to DCH 11  may share the first drain select line DSL 0 . The first drain select line DSL 0  may to surround the first drain-side half channels DCH 00  to DCH 11 . The electrical coupling between the first drain-side half channels DCH 00  to DCH 11  and the bit lines BL 0  to BL 11  may be controlled through the first drain select line DSL 0 . 
         [0040]    The second drain-side half channels DCH 12  to DCH 23  may share the second drain select line DSL 1 . The second drain select line DSL 1  may surround the second drain-side half channels DCH 12  to DCH 23 . The electrical coupling between the second drain-side half channels DCH 12  to DCH 23  and the bit lines BL 0  to BL 11  may be controlled through the second drain select line DSL 1 . 
         [0041]    The bit lines BL 0  to BL 11  may extend in the second direction II-II′. Each of the bit lines BL 0  to BL 11  may be connected to a corresponding one of the first drain-side half channels DCH 00  to DCH 11  and a corresponding one of the second drain-side half channels DCH 12  to DCH 23 . 
         [0042]    Referring to  FIG. 2C , the source-side half channels SCH 00  to SCH 23  may share first word lines WL 0  to WL 3 . The first word lines WL 0  to WL 3  may surround the source-side half channels SCH 00  to SCH 23 . Since the first word lines WL 0  to WL 3  are formed in different layers while having the same shape, when viewed from the top, the first word lines WL 0  to WL 3  are illustrated as one word line in  FIG. 2C . 
         [0043]    The first drain-side half channels DCH 00  to DCH 11  and the second drain-side half channels DCH 12  to DCH 23  may share second word lines WL 4  to WL 7 . The second word lines WL 4  to WL 7  may surround the first drain-side half channels DCH 00  to DCH 11  and the second drain-side half channels DCH 12  to DCH 23 . Since the second word lines WL 4  to WL 7  are formed in different layers while having the same shape, when viewed from the top, the second word lines WL 4  to WL 7  are illustrated as one word line in  FIG. 2C . 
         [0044]      FIGS. 2D and 2E  are perspective views illustrating the nonvolatile memory device in accordance with an embodiment of the present invention.  FIG. 2D  illustrates a cross-sectional view taken along line A in  FIGS. 2A and 2B , and  FIG. 2E  illustrates a cross-sectional view taken along line B in  FIGS. 2A and 2B . 
         [0045]    Referring to  FIGS. 2D and 2E , the first word lines WL 0  to WL 3 , the second word lines WL 4  to WL 7 , the bit lines BL 0  to BL 11 , the source select line SSL, the first drain select line DSL 0 , the second drain select line DSL 1 , the source line SL, and the pipe gate PG are illustrated. 
         [0046]      FIG. 2D  illustrates that the first pipe channel PCH 06  and the second pipe channel PCH 18  are formed deep within the pipe gate PG. Furthermore,  FIG. 2E  illustrates that the first pipe channel PCH 00  and the second pipe channel PCH 12  are formed to have a shallow depth within the pipe gate PG. 
         [0047]    In the nonvolatile memory device illustrated in  FIGS. 2A to 2E , since the first word lines WL 0  to WL 3  and the source select line SSL are shared by the source-side half channels SCH 00  to SCH 23 , the lines WL 0  to WL 3  and SSL may have a large width. Furthermore, since the second word lines WL 4  to WL 7  and the first drain select line DSL 0  are shared by the first drain-side half channels DCH 00  to DCH 11 , the lines WL 4  to WL 7  and DSL 0  may have a large width. Furthermore, since the second word lines WL 4  to WL 7  and the second drain select line DSL 1  are shared by the second drain-side half channels DCH 12  to DCH 23 , the lines WL 4  to WL 7  and DSL 1  may have a large width. Thus, since the lines WL 0  to WL 3 , WL 4  to WL 7 , SSL, DSL 0 , and DSL 1  may be formed with a large width, it is possible to prevent tilting of the stacked patterns. Furthermore, since the lines WL 0  to WL 3 , WL 4  to WL 7 , SSL, DSL 0 , and DSL 1  have a large width while being shared by more channels, the integration of the memory device may be further increased. 
         [0048]      FIG. 3  is a circuit diagram illustrating the nonvolatile memory device illustrated in  FIGS. 2A to 2E .  FIG. 3  illustrates two strings. One string includes the source-side half-channel SCH 06 , the first pipe channel PCH 06 , and the first drain-side half channel DCH 6 , and the other string includes the source-side half channel SCH 00 , the first pipe channel PCH 00 , and the first drain-side half channel DCH 00 . 
         [0049]    Referring to  FIG. 3 , the source-side half channel SCH 06  may include memory cells MO to M 3  and a source select transistor SST 0 . Each of the memory cells MO to M 3  may be implemented with a transistor including a floating gate. The first pipe channel PCH 06  may include a pipe transistor PT 0 . The first drain-side half channel DCH 06  may include memory cells M 4  to M 7  and a drain select transistor DST 0 . Each of the memory cells M 4  to M 7  may be implemented with a transistor including a floating gate. 
         [0050]    The source-side half channel SCH 00  may include memory cells M 8  to M 11  and a source select transistor SST 1 . Each of the memory cells M 8  to M 11  may be implemented with a transistor including a floating gate. The first pipe channel PCH 00  may include a pipe transistor PT 1 . The first drain-side half channel DCH 00  may include memory cells M 12  to M 15  and a drain select transistor DST 1 . Each of the memory cells M 12  to M 15  may be implemented with a transistor including a floating gate. 
         [0051]    In the above-described embodiment, the number of word lines WL 0  to WL 7  is set to 8, and the number of memory cells MO to M 7  included in one string is set to 8. However, this is only an example, and the number of word lines and the number of memory cells included in one string may be set to 32, 64 or the like. 
         [0052]      FIGS. 4A to 4C  are layout diagrams illustrating a nonvolatile memory device in accordance with another embodiment of the present invention. In the present embodiment, source-side half channels SCH 00  to SCH 23  may be arranged in six rows, and first drain-side half channels DCH 00  to DCH 11  and second drain-side half channels DCH 12  to DCH 23  may be arranged in three rows, respectively. 
         [0053]      FIGS. 4A to 4C  illustrate the first drain-side half channels DCH 00  to DCH 11 , the source-side half channels SCH 00  to SCH 23 , and the second drain-side half channels DCH 12  to DCH 23 , which are arranged in first to twelfth rows, respectively.  FIG. 4A  illustrates first pipe channels PCH 00  to PCH 11  and second pipe channels PCH 12  to PCH 23 .  FIG. 4B  illustrates a source select line SSL, a first drain select line DSL 0 , a second drain select line DSL 1 , and bit lines BL 0  to BL 11 .  FIG. 4C  illustrates first word lines WL 0  to WL 3  and second word lines WL 4  to WL 7 . 
         [0054]    Referring to  FIG. 4A , the source-side half channels SCH 00  to SCH 23  may be arranged in the fourth to ninth rows. Each of the source-side half channels SCH 00  to SCH 23  may be offset from centers of the source-side half channels included in the adjacent rows. For example, the source-side half channels SCH 00  to SCH 03  included in the fourth row may be arranged at different positions than the source-side half channels SCH 04  to SCH 07  included in the fifth row adjacent to the fourth row, based on the first direction I-I′. Similarly, the source-side half channels SCH 08  to SCH 11  included in the sixth row may be arranged at different positions than the source-side half channels SCH 04  to SCH 07  included in the fifth row adjacent to the sixth row, based on the first direction I-I′. 
         [0055]    The first drain-side half channels DCH 00  to DCH 11  may be arranged in the first to third rows at one side II′ of the region where the source-side half channels SCH 00  to SCH 23  are positioned, based on the second direction II-II′. Each of the first drain-side half channels DCH 00  to DCH 11  may be offset from centers of the first drain-side half channels included in the adjacent rows. For example, the first drain-side half channels DCH 00  to DCH 03  included in the first row may be arranged at different positions than the first drain-side half channels DCH 04  to DCH 07  included in the second row adjacent to the first row, based on the first direction I-I′. Similarly, the first drain-side half channels DCH 08  to DCH 11  included in the third row may be arranged at different positions than the first drain-side half channels DCH 04  to DCH 07  included in the second row, based on the first direction I-I′. 
         [0056]    The second drain-side half channels DCH 12  to DCH 23  may be arranged in tenth to twelfth rows at the other side II of the region where the source-side half channels SCH 00  to SCH 23  are positioned, based on the second direction II-II′. Each of the second drain-side half channels DCH 12  to DCH 23  may be offset from centers of the second drain-side half channels included in the adjacent rows. For example, the second drain-side half channels DCH 12  to DCH 15  included in the tenth row may be arranged at different positions than the second drain-side half channels DCH 16  to DCH 19  included in the eleventh row adjacent to the tenth row, based on the first direction I-I′. Similarly, the second drain-side half channels DCH 200  to DCH 23  included in the twelfth row may be arranged at different positions than the second drain-side half channels DCH 16  to DCH 19  included in the eleventh row adjacent to the twelfth row, based on the first direction I-I′. 
         [0057]    The first pipe channels PCH 00  to PCH 11  may connect the source-side half channels SCH 00  to SCH 11  in the fourth to sixth rows to the first drain-side half channels DCH 00  to DCH 11  in the first to third rows, respectively. Each of the first pipe channels PCH 00  to PCH 11  may have a different depth than adjacent pipe channels. For example, the first pipe channel PCH 04  may be shallower than the first pipe channels PCH 00  and PCH 08  adjacent to the first pipe channel PCH 04 . Furthermore, the first pipe channel PCH 09  adjacent to the first pipe channel PCH 00  may be shallower than the first pipe channel PCH 00 . The first drain-side half channels DCH 00  to DCH 11  and the source-side half channels SCH 00  to SCH 11 , which are connected through the first pipe channels PCH 00  to PCH 11 , may form full channels, respectively. For example, the first drain-side half channel DCH 03 , the first pipe channel PCH 03 , and the source-side half channel SCH 03  may form one full channel or a string. 
         [0058]    The second pipe channels PCH 12  to PCH 23  may connect the source-side half channels SCH 12  to SCH 23  in the seventh to ninth rows to the second drain-side half channels DCH 12  to DCH 23  in the tenth to twelfth rows. Each of the second pipe channels PCH 12  to PCH 23  may have a different depth than adjacent pipe channels. For example, the second pipe channel PCH 16  may be shallower than the second pipe channels PCH 12  and PCH 200  adjacent to the second pipe channel PCH 16 . Furthermore, the second pipe channel PCH 21  adjacent to the second pipe channel PCH 12  may be shallower than the second pipe channel PCH 12 . The second drain-side half channels DCH 12  to DCH 23  and the source-side half channels SCH 12  to SCH 23 , which are connected through the second pipe channels PCH 12  to PCH 23 , may form full channels, respectively. For example, the second drain-side half channel DCH 18 , the second pipe channel PCH 18 , and the source-side half channel SCH 18  may form one full channel or a string. 
         [0059]    Referring to  FIG. 4B , the source-side half channels SCH 00  to SCH 23  may share the source select line SSL. The source select line SSL may surround the source-side half channels SCH 00  to SCH 23 . The electrical coupling between the source-side half channels SCH 00  to SCH 23  and the source line SL (not shown) may be controlled through the source select line SSL. 
         [0060]    The first drain-side half channels DCH 00  to DCH 11  may share the first drain select line DSL 0 . The first drain select line DSL 0  may surround the first drain-side half channels DCH 00  to DCH 11 . The electrical coupling between the first drain-side half channels DCH 00  to DCH 11  and the bit lines BL 0  to BL 11  may be controlled through the first drain select line DSL 0 . 
         [0061]    The second drain-side half channels DCH 12  to DCH 23  may share the second drain select line DSL 1 . The second drain select line DSL 1  may surround the second drain-side half channels DCH 12  to DCH 23 . The electrical coupling between the second drain-side half channels DCH 12  to DCH 23  and the bit lines BL 0  to BL 11  may be controlled through the second drain select line DSL 1 . 
         [0062]    The bit lines BL 0  to BL 11  may be extended in the second direction II-II′. Each of the bit lines BL 0  to BL 11  may be connected to a corresponding one of the first drain-side half channels DCH 00  to DCH 11  and a corresponding one of the second drain-side half channels DCH 12  to DCH 23 . 
         [0063]    Referring to  FIG. 4C , the source-side half channels SCH 00  to SCH 23  may share the first word lines WL 0  to WL 3 . The first word lines WL 0  to WL 3  may surround the source-side half channels SCH 00  to SCH 23 . Since the first word lines WL 0  to WL 3  are formed in different layers while having the same shape, when viewed from the top, the first word lines WL 0  to WL 3  are illustrated as one word line in  FIG. 4C . 
         [0064]    The first drain-side half channels DCH 00  to DCH 11  and the second drain-side half channels DCH 12  to DCH 23  may share the second word lines WL 4  to WL 7 . The second word lines WL 4  to WL 7  may surround the first drain-side half channels DCH 00  to DCH 11  and the second drain-side half channels DCH 12  to DCH 23 . Since the second word lines WL 4  to WL 7  are formed in different layers while having the same shape, when viewed from the top, the second word lines WL 4  to WL 7  are illustrated as one word line in  FIG. 4C . 
         [0065]    The nonvolatile memory device illustrated in  FIGS. 4A to 4C  has a different plan arrangement than the nonvolatile memory device illustrated in  FIGS. 2A to 2E , but has substantially the same vertical structure as the nonvolatile memory device illustrated in  FIGS. 2A to 2E . Thus, the perspective views of the nonvolatile memory device illustrated in  FIGS. 4A to 4C  are omitted herein. 
         [0066]    The lines of the nonvolatile memory device illustrated in  FIGS. 4A to 4C  may be wider than the lines of the nonvolatile memory device illustrated in  FIGS. 2A to 2E . Thus, the stability of the stacked patterns may be further improved, and the integration of the memory device may be further increased. 
         [0067]    In the memory device illustrated in  FIGS. 2A to 2E , the source-side half channels are arranged in four rows, and the first drain-side half channels and the second drain-side half channels are arranged in two rows, respectively. In the memory device illustrated in  FIGS. 4A to 4C , the source-side half channels are arranged in six rows, and the first drain-side half channels and the second drain-side half channels are arranged in three rows, respectively. However, this is only an example. The source-side half channels may be arranged in 2N rows, and the first drain-side half channels and the second drain-side half channels may be arranged in N rows, where N is an integer equal to or greater than two. 
         [0068]      FIGS. 5A to 5C  are layout diagrams illustrating a nonvolatile memory device in accordance with another embodiment of the present invention. 
         [0069]      FIGS. 5A to 5C  illustrate first drain-side half channels DCH 00  to DCH 07 , source-side half channels SCH 00  to SCH 15 , and second drain-side half channels DCH 08  to DCH 15 , which are arranged in first to sixteenth rows, respectively.  FIG. 5A  illustrates first pipe channels PCH 00  to PCH 07  and second pipe channels PCH 08  to PCH 15 . FIG. SB illustrates a source select line SSL, a first drain select line DSL 0 , a second drain select line DSL 1 , and bit lines BL 0  to BL 7 .  FIG. 5C  illustrates first word lines WL 0  to WL 3  and second word lines WL 4  to WL 7 . 
         [0070]    Referring to  FIG. 5A , the source-side half channels SCH 00  to SCH 15  may be arranged in eight rows, i.e., the fifth to twelfth rows. Each of the source-side half channels SCH 00  to SCH 23  may be offset from centers of the source-side half channels included in the adjacent rows. For example, the source-side half channels SCH 00  and SCH 02  included in the fifth row may be arranged at different positions than the source-side half channels SCH 01  and SCH 03  included in the sixth row, which is adjacent to the fifth row, based on the first direction I-I′. 
         [0071]    The first drain-side half channels DCH 00  to DCH 7  may be arranged in four rows, i.e., the first to fourth rows, at one side II′ of the region where the source-side half channels SCH 00  to SCH 15  are positioned, based on the second direction II-II′. Each of the first drain-side half channels DCH 00  to DCH 07  may be offset from centers of the first drain-side half channels included in the adjacent rows. For example, the first drain-side half channels DCH 04  and DCH 06  in the second row may be arranged at different positions than the first drain-side half channels DCH 05  and DCH 07  in the first row and the third drain-side half channels DCH 01  and DCH 03  in the third row, based on the first direction I-I′. 
         [0072]    The first drain-side half channels DCH 00  to DCH 07  and the source-side half channels SCH 00  to SCH 07  in the fifth to eighth rows may be symmetrical, based on a boundary line  501  between a region in which the first drain-side half channels DCH 00  to DCH 07  are formed and a region in which the source-side half channels SCH 00  to SCH 15  are formed. That is, the first drain-side half channels DCH 00  to DCH 07  and the source-side half channels SCH 00  to SCH 07  in the fifth to eighth rows may be formed at the symmetrical positions based on the boundary line  501 . 
         [0073]    The second drain-side half channels DCH 08  to DCH 15  may be arranged in four rows, i.e., the thirteenth to sixteenth rows, at the other side II of the region where the source-side half channels SCH 00  to SCH 15  are positioned, based on the second direction II-II′. Each of the second drain-side half channels DCH 08  to DCH 15  may be offset from centers of the second drain-side half channels included in the adjacent rows. For example, the second drain-side half channels DCH 11  and DCH 09  in the fourteenth row may be arranged at different positions than the second drain-side half channels DCH 10  and DCH 08  in the thirteenth row and the second drain-side half channels DCH 14  and DCH 12  in the fifteenth row, based on the first direction I-I′. 
         [0074]    The second drain-side half channels DCH 08  to DCH 15  and the source-side half channels SCH 08  to SCH 15  in the ninth to twelfth rows may be symmetrical, based on a boundary line  502  between a region in which the second drain-side half channels DCH 08  to DCH 15  are formed and the region in which the source-side half channels SCH 00  to SCH 15  are formed. That is, the second drain-side half channels DCH 08  to DCH 15  and the source-side half channels SCH 08  to SCH 15  of the ninth to twelfth rows may be symmetrical based on the boundary line  502 . 
         [0075]    The first pipe channels PCH 00  to PCH 07  may connect the source-side half channels SCH 00  to SCH 07  in the fifth to eighth rows to the first drain-side half channels DCH 00  to DCH 07  in the first to fourth rows, respectively. Each of the first pipe channels PCH 00  to PCH 07  may have a different depth than adjacent pipe channels. For example, the first pipe channels PCH 00 , PCH 01 , PCH 02 , and PCH 03  may be shallower than the first pipe channels PCH 04 , PCH 05 , PCH 06 , and PCH 07 . The first drain-side half channels DCH 00  to DCH 07  and the source-side half channels SCH 00  to SCH 07 , which are connected through the first pipe channels PCH 00  to PCH 07 , may form full channels, respectively. For example, the first drain-side half channel DCH 03 , the first pipe channel PCH 03 , and the source-side half channel SCH 03  may form one full channel or a string. Since the first drain-side half channels DCH 00  to DCH 07  and the source-side half channels SCH 00  to SCH 07  are symmetrical based on the boundary line  501 , the first pipe channels PCH 00  to PCH 07  may have various lengths. For example, the first pipe channels PCH 05  and PCH 07  may be the longest, and the first pipe channels PCH 00  and PCH 02  may be the shortest. 
         [0076]    The second pipe channels PCH 08  to PCH 15  may connect the source-side half channels SCH 08  to SCH 15  in the ninth to twelfth rows to the second drain-side half channels DCH 08  to DCH 15  in the thirteenth to sixteenth rows, respectively. Each of the second pipe channels PCH 08  to PCH 15  may have a different depth than adjacent pipe channels. For example, the second pipe channels PCH 11 , PCH 10 , PCH 09 , and PCH 08  may be shallower than the second pipe channels PCH 15 , PCH 14 , PCH 13 , and PCH 12 . The second drain-side half channels DCH 08  to DCH 15  and the source-side half channels SCH 08  to SCH 15 , which are connected through the second pipe channels PCH 08  to PCH 15 , may form full channels, respectively. For example, the second drain-side half channel DCH 10 , the second pipe channel PCH 10 , and the source-side half channel SCH 10  may form one full channel or a string. Since the second drain-side half channels DCH 08  to DCH 15  and the source-side half channels SCH 08  to SCH 15  are symmetrical based on the boundary line  502 , the second pipe channels PCH 08  to PCH 15  may have various lengths. For example, the second pipe channels PCH 15  and PCH 13  may be the longest, and the first pipe channels PCH 10  and PCH 08  may be the shortest. 
         [0077]    Referring to  FIG. 5B , the source-side half channels SCH 00  to SCH 15  may share the source select line SSL. The source select line SSL may surround the source-side half channels SCH 00  to SCH 15 . The electrical coupling between the source-side half channels SCH 00  to SCH 15  and a source line SL (not shown) may be controlled through the source select line SSL. 
         [0078]    The first drain-side half channels DCH 00  to DCH 07  may share the first drain select line DSL 0 . The first drain select line DSL 0  may surround the first drain-side half channels DCH 00  to DCH 07 . The electrical coupling between the first drain-side half channels DCH 00  to DCH 07  and the bit lines BL 0  to BL 7  may be controlled through the first drain select line DSL 0 . 
         [0079]    The second drain-side half channels DCH 08  to DCH 15  may share the second drain select line DSL 1 . The second drain select line DSL 1  may surround the second drain-side half channels DCH 08  to DCH 15 . The electrical coupling between the second drain-side half channels DCH 08  to DCH 15  and the bit lines BL 0  to BL 7  may be controlled through the second drain select line DSL 1 . 
         [0080]    The bit lines BL 0  to BL 7  may be extended in the second direction II-II′. Each of the bit lines BL 0  to BL 07  may be connected to a corresponding one of the first drain-side half channels DCH 00  to DCH 07  and a corresponding one of the second drain-side half channels DCH 08  to DCH 15 . 
         [0081]    Referring to  FIG. 5C , the source-side half channels SCH 00  to SCH 15  may share the first word lines WL 0  to WL 3 . The first word lines WL 0  to WL 3  may surround the source-side half channels SCH 00  to SCH 15 . Since the first word lines WL 0  to WL 3  are formed in different layers while having the same shape, when viewed from the top, the first word lines WL 0  to WL 3  are illustrated as one word line in  FIG. 5C . 
         [0082]    The first drain-side half channels DCH 00  to DCH 07  and the second drain-side half channels DCH 08  to DCH 15  may share the second word lines WL 4  to WL 7 . The second word lines WL 4  to WL 7  may surround the first drain-side half channels DCH 00  to DCH 07  and the second drain-side half channels DCH 08  to DCH 15 . Since the second word lines WL 4  to WL 7  are formed in different layers while having the same shape, when viewed from the top, the second word lines WL 4  to WL 7  are illustrated as one word line in  FIG. 5C . 
         [0083]    The nonvolatile memory device illustrated in  FIGS. 5A to 5C  has a different plan arrangement than the nonvolatile memory device illustrated in  FIGS. 2A to 2E , but has substantially the same vertical structure as the nonvolatile memory device illustrated in  FIGS. 2A to 2E . Thus, the perspective views of the nonvolatile memory device illustrated in  FIGS. 5A to 5C  are omitted herein. 
         [0084]    In accordance with the embodiments of the present invention, the numbers of slits and word lines in the 3D nonvolatile memory device may be reduced to improve the integration and stability to avoiding tilting. 
         [0085]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.