Abstract:
A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.

Description:
[0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/026,718 for “Apparatus and Method for Detecting and Preventing Laser Interrogation of an FPGA Integrated Circuit” filed Jul. 21, 2014, the contents of which are incorporated in this disclosure by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to integrated circuits. More particularly, the present invention relates to programmable logic devices and to Field programmable Gate Array (FPGA) integrated circuits. 
         [0004]    Field Programmable Gate Arrays (FPGAs) are typically used in secure systems because the design is implemented by the user not the wafer manufacturer, making it more difficult for an attacker to understand the internal function programmed into the device. However, increasingly sophisticated techniques have been developed to determine the design that has been programmed into the FPGA. One of these techniques involves shining a laser through the backside of the die to sense the effect on the transistors. 
         [0005]    2. Description of Related Art 
         [0006]    Laser light stimulation of transistors has been used for many years to analyze integrated circuits. However, modern integrated circuits utilize very dense metal with as many as 12 metal layers. This prevents light from reaching the transistors from the top. As a result, techniques have been developed to shine light from the backside of the integrated circuit and therefore must use infrared light, as silicon is opaque to visible light, but transparent to infrared light. The infrared light must be reasonably intense to stimulate the transistor due to absorption by the bulk silicon and to be strong enough to cause a measureable effect on the transistor to analyze its function. 
         [0007]    There are two different phenomena that can be used in this analysis. First, the infrared light can be used to heat the transistor significantly (tens of degrees Celsius) thereby slowing it down which can be seen as a change in the power consumption at the specific time that it switches, thereby giving clues to an attacker concerning what is happening in the circuit. Second, infrared light can be used to switch the state of a register by inducing a photo current by double photon absorption, thereby altering the decision made by the circuit. The state change of the register can be sensed by the attacker. In the event that the register contains a bit of an encryption key, the attacker obtains one of the bits of the key. By repeating the process, an attacker can read many or all bits in the encryption key thus gaining access to the internal configuration information for the circuit. In other cases, flipping the state of a register may enable readout of otherwise unavailable information, thus potentially giving the attacker access to the configuration information for the integrated circuit. 
         [0008]    There is no prior art known to the inventor for dealing with this problem. 
       SUMMARY OF THE INVENTION 
       [0009]    This intense infrared laser light used to interrogate the circuit must first pass through the well isolating the transistor from the bulk silicon. This will induce a photocurrent in the well. Since the isolating well is not used in the circuit path, the current flowing between the well and the power supply rail (e.g., +2.5V) to which it is connected is normally in the picoampere range due to junction leakage. The induced photocurrents will increase the current in the well many thousands of times, making it easily detectable. In accordance with the present invention, current flowing from the power supply to the deep n-well is monitored. In one embodiment of the invention, the current is monitored by a resistor placed between the power supply and the deep n-well. Detection of this current at a level significantly higher than the quiescent current level is sensed and will trigger a logic signal. The logic signal is used to either disable at least one function of the integrated circuit or to erase the configuration memory defining the function of the integrated circuit. 
         [0010]    Further details and advantages of the invention will become clear upon reading the following detailed description in conjunction with the accompanying drawing figures, wherein like parts are designated with like reference numerals throughout. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram showing a cross-sectional view of a typical configuration memory cell utilized in one embodiment of an NVM FPGA integrated circuit. 
           [0012]      FIG. 2  is a diagram showing one aspect of preventing laser interrogation of an FPGA integrated circuit according to the present invention. 
           [0013]      FIG. 3  is a flow diagram illustrating a method for preventing laser interrogation of an FPGA integrated circuit according to the present invention. 
       
    
    
     DESCRIPTION OF THE INVENTION 
       [0014]    In the following description, numerous specific details are set forth in order to provide a more thorough description of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. Other embodiments of the invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. In some instances, well-known features have not been described in detail so as not to obscure the invention. 
         [0015]    Referring first to  FIG. 1 , diagram shows a cross-sectional view of a typical configuration memory cell  10  utilized in an FPGA integrated circuit. Configuration memory cell  10  is formed in a p-type semiconductor substrate  12 . A deep n-well  14  is formed in p-type substrate  12 , and the p-substrate  12  is connected to ground (0V), it being understood that any common potential may be utilized in place of ground, with the relative voltages to the common potential substituted for the ground relative voltages described herein. 
         [0016]    A p-channel non-volatile transistor is formed in the deep n-well  14  and includes a source  16 , a drain  18 , and a gate  20 . An n+ contact  22  is used to place a voltage bias on the deep n-well  14 . During normal operation of the memory cell  10 , the source  16  of the p-channel non-volatile transistor and the deep n-well  14  are both connected to a positive voltage (e.g., +2.5V). 
         [0017]    An n-channel non-volatile transistor is formed in a p-well  24 , with the p-well  24  formed within the deep n-well  14 , and includes a source  26 , a drain  28 , and a gate  30 . A p+ contact  32  is used to place a voltage bias on the p-well  24 . During normal operation of the memory cell  10 , the source  26  of the n-channel non-volatile transistor and the p-well  24  are connected to ground (0V). 
         [0018]    A switch transistor having a source  34 , a drain  36 , and a gate  38  is formed in a p-well  40  in the p-type substrate  12 . The drains  18  and  28  of the p-channel and n-channel non-volatile transistors are connected together and to the gate  38  of the switch transistor. The source  34  and drain  36  of the switch transistor are respectively connected to logic circuitry in the FPGA fabric as is known in the art, and respectively denoted as Logic Signal Out and Logic Signal In. 
         [0019]    During normal operation of the FPGA integrated circuit, the deep n-well  14  is reverse biased with respect to both the p-type substrate  12  and the p-well  24  contained within the deep n-well  14  and only a small leakage current on the order of a few picoamperes flows from the power supply to the deep n-well through contact  22 . In the event that a laser is used to attempt to discern the circuit programmed into the FPGA, large minority carrier photocurrents (on the order of several microamperes) will be induced in the deep n-well  14 , and will be collected in the power rail connected to the deep n-well  14  through contact  22 . 
         [0020]    Referring now to  FIG. 2 , a diagram shows an illustrative circuit  50  embodying one aspect of detecting and preventing laser interrogation of an FPGA integrated circuit according to the present invention. In the circuit of  FIG. 2 , the positive voltage of +2.5V is connected to the deep n-wells  14  though a sense resistor  52 . As previously noted, during normal circuit operation very little current flows through sense resistor  52 , dropping only a small voltage across the sense resistor  52 . A sense amplifier  54  monitors the voltage across the sense resistor  52 . When the voltage across sense resistor  52  reaches a value set to sense photocurrent generated by laser probing of the integrated circuit, sense amplifier  54  trips and sets latch  56 . The output of latch  56  is a tamper signal  58 . In an embodiment of the invention where the power supply is at a voltage of +2.5V, the resistor may have a value of between about 1K Ohms and about 100K Ohms, and the sense amplifier may trigger at voltage values of between about 0.01V and about 0.3V. 
         [0021]    As shown in  FIG. 2 , the tamper signal  58  can be used to disable at least one function of the integrated circuit, for example, stopping all of the clocks in the circuit, as shown at reference numeral  60 , or performing a function  62 , such as interrupting the voltage supply to some or all of the circuit. The tamper signal  58  can also be used to trigger an erase operation of the configuration memory, as shown at reference numeral  64 . In any of these cases, the would-be tamperer is rendered unable to discern the configuration information for the FPGA. 
         [0022]    The foregoing description of the invention is in the context of deep n-wells. As will be readily appreciated by persons of ordinary skill in the art, the present invention can be used on regular logic n-wells as well as any deep n-well used to isolate p-wells, or on isolated p-wells. 
         [0023]    Referring now to  FIG. 3 , a flow diagram shows an illustrative method  70  for detecting and preventing laser interrogation of an FPGA integrated circuit according to the present invention. 
         [0024]    The method starts at reference numeral  72 . At reference numeral  74 , operation of the integrated circuit begins. At reference numeral  76 , the method enters a current-sensing loop monitoring the current through the sense resistor  52  of  FIG. 2 . As long as the current through sense resistor  52  is below the threshold, the method remains in the current-sensing loop at reference numeral  76 . 
         [0025]    If the current through sense resistor  52  exceeds the threshold, the method proceeds to reference numeral  78 , where a tamper signal is generated by sense amplifier  54  tripping and setting latch  56  of  FIG. 2 . The method then proceeds to reference numeral  80  where the operation of the integrated circuit such as an FPGA, is disabled or the configuration memory is erased, depending on the intent of the designer. The integrated circuit may be disabled by stopping all of the clocks in the circuit, or by interrupting the voltage supply to some or all of the integrated circuit. The tamper signal  58  output by latch  56  of  FIG. 2 , thus may be utilized as a disable command for the integrated circuit or to instruct the programming intelligence on the integrated circuit to perform an erase operation on the configuration memory. The method ends at reference numeral  82 . The above is particularly described in relation to an FPGA, it being understood that the principles are equally applicable to any integrated circuit and are thus not limited to an FPGA. 
         [0026]    Although the above provides a full and complete disclosure of the preferred embodiments of the invention, various modifications, alternate constructions and equivalents will occur to those skilled in the art. Therefore, the above should not be construed as limiting the invention, which is defined by the claims.