Abstract:
The present invention relates to a high-frequency power amplifier having differential inputs, and more specifically to a high-frequency power amplifier having differential inputs, in which a structure of an output port of a communication system for 2.4 GHz ISM frequency band can be simplified by designing and producing the high-frequency power amplifier having differential inputs for 2.4 GHz ISM frequency band using a silicon germanium (SiGe) microwave monolithic integrated circuit (MMIC), thereby decreasing the number of components of a transmission unit and reducing a price of the communication system.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a high-frequency power amplifier having differential inputs, and more specifically to a high-frequency power amplifier having differential inputs, capable of simplifying a structure of an output port of a communication system for 2.4 GHz ISM frequency band by designing and producing a high-frequency power amplifier having differential inputs for 2.4 GHz ISM frequency band using a silicon germanium (SiGe) microwave monolithic integrated circuit (MMIC).  
         [0003]     2. Background of the Invention  
         [0004]      FIG. 1  is a constructional view showing an output port of a conventional communication system.  
         [0005]     As shown in  FIG. 1 , a high-frequency transmission unit  10  of a conventional communication system has two output terminals. The signals output from the two output terminals are have phases inverted each other, and this output is referred to as “a balance output”.  
         [0006]     On the other hand, a conventional power amplifier  30  for amplifying and sending a signal to an antenna  40  has one input terminal and one output terminal. Therefore, a signal, which can be received by the conventional power amplifier  30 , is so called “an unbalance signal”. The unbalance signal means a signal not having a phase inverted from other signals.  
         [0007]     Therefore, in order to amplify the signals output from a high-frequency transmission unit and send the amplified signals to the antenna, a signal conversion unit  20  for converting the balance signal into the unbalance signal and sending the unbalanced signal to an output amplifier is required. Generally, a balanced-to-unbalanced element (e.g. a BALUN element) which is a passive element is used as the signal conversion unit  20 .  
         [0008]     Accordingly, in the conventional power amplifier  30 , there is a problem that the input signal is attenuated due to a characteristic of the BALUN element used in signal conversion.  
         [0009]     Therefore, in the conventional power amplifier  30 , the signal attenuated due to the BALUN element must be compensated to satisfy an output power of the antenna  40  required for the communication system. In other word, there is a problem that a power gain required for the power amplifier is increased.  
       SUMMARY OF THE INVENTION  
       [0010]     The present invention is contrived to solve the above problems, and thus it is an object of the present invention to provide a high-frequency power amplifier having differential inputs, capable of obtaining an output power of an antenna required for a communication system without any attenuation by implementing an active element of a silicon germanium (SiGe) microwave monolithic integrated circuit (MMIC) as a conversion element for converting a balance signal into an unbalance signal.  
         [0011]     Furthermore, it is another object of the present invention to provide a high-frequency power amplifier having differential inputs, having functions of breaking and controlling a power implemented in an output port of a communication system as well as a function of amplifying an output signal of a high-frequency transmission unit and sending the amplified signal to an antenna by using a silicon germanium (SiGe) microwave monolithic integrated circuit (MMIC).  
         [0012]     Furthermore, it is still another object of the present invention to provide a high-frequency power amplifier having differential inputs, capable of reducing the number of elements in a transmission unit of a communication system and a cost for the communication system by simplifying a structure of an output port of the communication system for 2.4 GHz ISM frequency band.  
         [0013]     In order to achieve the above objects, a high-frequency power amplifier having differential inputs according to the present invention comprises: a power supply unit; a first amplification circuit unit for amplifying high-frequency differential input signals of differential input terminals INA, INB into outputting a single high-frequency signal; an intermediate impedance matching unit for impedance-matching the single high-frequency signal amplified by the first amplification circuit unit; a second amplification circuit unit for receiving and amplifying the impedance-matched single high-frequency signal from the intermediate impedance matching unit and outputting the amplified signal to an antenna through an output terminal thereof; a power control circuit unit for controlling a power output to the antenna through the output terminal of the second amplification circuit unit by varying a voltage of a power control terminal; a first bias circuit unit for determining an operation reference point of the first amplification circuit unit; and a second bias circuit unit for determining an operation reference point of the second amplification circuit unit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINS  
       [0014]     The above and other objects, advantages and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0015]      FIG. 1  is a constructional view showing an output port of a conventional communication system,  
         [0016]      FIG. 2  is a constructional view showing functional units of a conventional high-frequency power amplifier,  
         [0017]      FIG. 3  is a constructional view showing an output port of a communication system using a high-frequency power amplifier having differential inputs according to the present invention,  
         [0018]      FIG. 4  is a constructional view showing functional units of a high-frequency power amplifier having differential inputs according to the present invention, and  
         [0019]      FIG. 5  is a circuit diagram showing a high-frequency power amplifier having differential inputs according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]     Now, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.  
         [0021]      FIG. 3  is a constructional view showing an output port of a communication system using a high-frequency power amplifier  31  having differential inputs according to the present invention.  
         [0022]     As shown in  FIG. 3 , the output port of the communication system according to the present invention includes a high-frequency transmission unit  10  and a high-frequency power amplifier having differential inputs  31 . Two output signals OUTA, OUTB output from the high-frequency transmission unit  10  are input to the high-frequency power amplifier  31  having differential inputs, and the high-frequency power amplifier  31  outputs a single output signal amplified using a voltage difference between the two signals OUTA, OUTB to an antenna.  
         [0023]      FIG. 4  is a constructional view showing functional units of a high-frequency power amplifier having differential inputs according to the present invention. As shown in  FIG. 4 , the high-frequency power amplifier having differential inputs includes a first amplification circuit unit  60 , a second amplification circuit unit  80 , an intermediate impedance matching unit  50 , and a bias/control block  70 .  
         [0024]     The first amplification circuit unit  60  has difference inputs to perform a function as a signal conversion unit  20 , and the second amplification circuit unit  80  is a common emitter power amplifier of class AB.  
         [0025]     The intermediate impedance matching unit  50  matches an output impedance of the first amplification circuit unit  60  and an input impedance of the second amplification circuit unit  80  to minimize a reflection loss of a high-frequency signal, thereby to maximize a power of the high-frequency signal input to the second amplification circuit unit  80 .  
         [0026]     The bias/control block  70  includes bias circuit units of the first amplification circuit unit  60  and the second amplification circuit unit  80 , a power breaking circuit unit, a power controlling circuit unit.  
         [0027]     Now, a construction of a high-frequency power amplifier having differential inputs according to the present invention will be described in detail with reference to  FIG. 5 .  
         [0028]     As shown in  FIG. 5 , the first amplification circuit unit  60  includes a seventh transistor Q 7 , an eighth transistor Q 8 , a first inductor L 1 , and differential input terminals INA, INB. The first inductor L 1  serves as a negative feedback circuit for stabilizing the first amplification circuit unit  60 .  
         [0029]     The second amplification unit  80  is a class AB common emitter power amplifier including a twelfth transistor Q 12  and a fifth capacitor C 5 .  
         [0030]     The intermediate impedance matching unit  50  includes a third capacitor C 3 , a second capacitor C 2 , and a sixteenth resistor R 16 .  
         [0031]     The bias/control block  70  includes the bias circuit unit of the first amplification circuit  60 , the bias circuit unit of the second amplification unit  80 , a power breaking circuit unit, and a power controlling circuit unit.  
         [0032]     The bias circuit unit of the first amplification circuit unit  60  includes a fifth transistor Q 5 , a sixth transistor Q 6 , a plurality of resistors R 11 ˜R 15  and a first capacitor C 1 . The bias circuit unit of the first amplification circuit unit  60  comprises a bias current mirror circuit for compensating for variation in a current gain of the first amplification circuit unit. The bias circuit unit of the first amplification circuit unit  60  serves for determining an operation reference point of the first amplification circuit unit  60 .  
         [0033]     The bias circuit unit of the second amplification circuit unit  80  includes a tenth transistor Q 10 , an eleventh transistor Q 11 , a plurality of resistor R 18 ˜R 20  and a forth capacitor C 4 . The bias circuit unit of the second amplification circuit unit  80  comprises a bias current mirror circuit for compensating for variation in a current gain of the second amplification circuit unit. The bias circuit unit of the second amplification circuit unit  80  serves for determining an operation reference point of the second amplification circuit unit  80 .  
         [0034]     The resistors R 11 , R 13 ˜R 15 , R 18 ˜R 20  and the first and forth capacitors C 1 , C 4  are elements for stabilizing base voltages of the transistors.  
         [0035]     The power breaking circuit unit includes a plurality of resistors R 23 ˜R 25 , voltage-controlled current sources SRC 1 , SRC 2  and a fifth transistor Q 15 .  
         [0036]     The power controlling circuit unit includes a plurality of resistors R 1 ˜R 5 , R 10 , R 17 , and a plurality of capacitors Q 1 ˜Q 4 , Q 9 , Q 17 . The seventh transistor Q 17  serves as a protection diode for protecting inner circuits of the high-frequency power amplifier by absorbing a static electricity supplied to the power controlling terminal VCTRL  73 .  
         [0037]     Operations of the high-frequency power amplifier having differential inputs according to the present invention will be described in detail.  
         [0038]     First, in the first amplification circuit unit  60 , a voltage difference between two input signals input to two differential input terminals INA, INB is amplified, and the amplified voltage difference is output to the intermediate impedance matching unit  50  in the form of a single signal from a collector of the eighth transistor Q 8 .  
         [0039]     The intermediate impedance matching unit  50  matches an output impedance of the eighth transistor Q 8  and an input impedance of the twelfth transistor Q 12  using the third capacitor C 3  which is an intermediate impedance matching element to output the single signal output from the eighth transistor Q 8  to a base of the twelfth transistor Q 12 .  
         [0040]     Therefore, a reflection loss of the single high-frequency signal output from the eighth transistor Q 8  is minimized, whereby the power of the signal input to the twelfth transistor Q 12  is maximized.  
         [0041]     In the second amplification circuit unit  80 , the twelfth transistor Q 12  receives and amplifies the output signal of the eighth transistor Q 8  matched with the third capacitor C 3  which is an intermediate impedance matching element, and outputs the amplified high-frequency signal to an antenna  40  through an output terminal Vcc 2 _OUT of the second amplification circuit unit. The fifth capacitor C 5  is an element for reducing an output high-frequency component of the second amplification circuit unit.  
         [0042]     On the other hand, amplification factors of the first amplification circuit unit  60  and the second amplification circuit unit  80  are determined by bias currents supplied to collectors of the seventh, eighth and twelfth transistors, and procedures of supplying the bias current are as follows.  
         [0043]     First, when a supply voltage Vcc is supplied to a supply voltage terminal VCC 0   71  and a voltage which is the same as the supply voltage Vcc is supplied to the power control terminal VCTRL  73 , the bias states of the circuits are as follows.  
         [0044]     If a base current of the second transistor Q 2  is ignored, a collector current of the first transistor Q 1  is the same as a current L_c 1  supplied to a forth resistor R 4  as shown in Equation 1 as follows: 
 
I_c 1 ≈(V B1 −V BEONQ1 )/R 3    [Equation 1]
 
 where a collector-emitter saturation voltage is ignored, V B1  is a base voltage of the first transistor Q 1 , and V BEONQ1  is a base-emitter turn-on voltage of the first transistor Q 1 . 
 
         [0046]     A base voltage V B1  of the first transistor is determined by distributing a voltage V CTRL  of the power controlling terminal VCTRL  73  using a first resistor R 1  and a second resistor R 2  as follows: 
 
V B1 ≈V CTRL ·(R 2 /R 1 +R 2 ).   [Equation 2]
 
         [0047]     When the first transistor Q 1  is saturated, the collector voltage of the first transistor Q 1  is the same as the emitter voltage thereof as follows: 
 
V C1 ·I 13  c 1 ·R 3 .   [Equation 3]
 
         [0048]     A voltage V 1  is a node voltage distributed by a fourth resistor R 4  and a twelfth resistor R 12  as follows: 
 
 V   1 = V   c1   +I   —   c   1 · R   4 = I   —12   ·R   12 +2 ·V   BEON .   [Equation 4]
 
         [0049]     On the other hand, a reference current I_c 2  of the third transistor is as follows: 
 
I_c 2 ≈{(R 5 +R 7 )·V C1 −V BEONQ3 ·R 5 }/(R 5 +R 7 ).   [Equation 5]
 
         [0050]     In other word, the reference current I_c 2  of the third transistor is obtained by employing the voltage Vc 1  obtained in the Equation 3 in the equation 5.  
         [0051]     A collector current I_c 3  of the fourth transistor is determined by the reference current L_c 2  and emitter resistance ratio of the third transistor Q 3  due to a current mirror relationship between the third transistor Q 3  and the fourth transistor Q 4  as follows: 
 
I_c 3 ≈I_c 2 ·(R 5 /R 10 ).   [Equation 6]
 
         [0052]     In addition, assuming that the current I_ 12  is sufficiently lager than the current I_c 1  and the current I_c 3 , the current I_ 12  is the same as the current I_ref as follows:  
                     I_   ⁢   12     ≈       ⁢   I_ref               ≈       ⁢       {     Vcc   -     (     2   ·     V   BEON       )       }     /     (     R26   +   R12     )                   ≈       ⁢       {     Vcc   -     (     2   ·     V   BEON       )       }     /     (     R22   +   R21     )                   ≈       ⁢       {     Vcc   -     (     Vc1   +     I_c1   ·   R4       )       }     /     R26   .                     [     Equation   ⁢           ⁢   7     ]             
 
         [0053]     In addition, a fifth transistor Q 5 , a seventh transistor Q 7  and an eighth transistor Q 8  of the first amplification circuit unit  60  form a current mirror relationship, and a reference current of the current mirror is a current I_ 12 .  
         [0054]     In other word, bias currents I_ 1   b , I_ 1   a  of the seventh transistor Q 7  and the eighth transistor Q 8  in the first amplification circuit unit are determined based on a ratio of the current I_ 12 : the current I_ 1   b : the current I_ 1   a =1:6:6 in accordance with on an area ratio of the transistor.  
         [0055]     The bias current I_ 1   b , I_ 1   a  is supplied from the supply voltage terminals VCC 1 A, VCC 1 B of the first amplification circuit unit. A voltage of the supply voltage terminal VCC 1 A, VCC 1 B of the first amplification circuit unit is the same as a supply voltage Vcc of the supply voltage terminal VCCO  71 .  
         [0056]     In addition, a collector current I_c 4  of the ninth transistor Q 9  is determined by the reference current I_c 2  and emitter resistance ratio of the third transistor Q 3  due to a current mirror relationship between the third transistor Q 3  and the ninth transistor Q 9  as follows: 
 
I_c 4 ≈I_c 2 ·(R 5 /R 17 ).   [Equation 8]
 
         [0057]     In the equation 7, assuming that the current I_ref is sufficiently lager than the current I_c 4 , a reference current in the current mirror relationship between the tenth transistor Q 10  and the twelfth transistor Q 12  can be a current I_ref.  
         [0058]     In other word, a bias current I_ 2  of the twelfth transistor Q 12  in the second amplification circuit unit  80  is determined based on a ratio of the current I_ref:the current I_ 2 =1:16 in accordance with an area ratio of the transistor.  
         [0059]     The current I_ 2  is supplied from the supply voltage terminal Vcc 2 _OUT. A voltage of the supply voltage terminal Vcc 2 _OUT in the second amplification circuit unit is the same as a supply voltage Vcc of the supply voltage terminal VCCO  71 .  
         [0060]     Accordingly, the bias currents I_ 1   b , I_ 1   a , I_ 2  determined by the procedures become the collector currents of the seventh transistor, the eighth transistor, and the twelfth transistor to determine signal amplification factors of the first amplification circuit unit and the second amplification circuit unit.  
         [0061]     On the other hand, when producing an integrated circuit, the sixth transistor Q 6  and the eleventh transistor Q 11  compensate a change of a bias current due to a change rate of an current amplification factor of the transistor to safely maintain the bias current I_ 1   b , I_ 1   a , I_ 2 .  
         [0062]     In addition, the resistors R 6 ˜R 9  stabilize base voltages of the fourth transistor Q 4 , the third transistor Q 3 , and the ninth transistor Q 9 .  
         [0063]     On the other hand, procedures of controlling the power by the power controlling circuit unit are as follows.  
         [0064]     In the operation of the power controlling circuit unit, the voltage of the power controlling terminal VCTRL  73  is controlled within a range of 0˜Vcc [V] and bias currents of the first amplification circuit unit  60  and the second amplification circuit unit  80  are controlled, thereby controlling an output power of an antenna which is logarithmically proportional to the bias currents. Procedures of the operation will be described as follows below.  
         [0065]     First, according to Equation 1 and Equation 2, a base voltage V B1  of the first transistor Q 1  and a bias current I_c 1  of the first transistor Q 1  are decreased. Therefore, a base current of the second transistor Q 2  can not be ignored.  
         [0066]     Therefore, in a case of not including the first transistor Q 1 , a collector voltage V C1  of the first trnasister Q 1  is determined as follows: 
 
V C1 ≈V 1 −R L1 ·I_c 1    [Equation 9]
 
 where the voltage  1  is a node voltage distributed by a fourth resistor R 4  and a twelfth resistor R 12  as shown in the equation 4. R L1  is an equivalent load resistor of the first transistor. 
 
         [0068]     In other word, when a voltage of the power controlling terminal VCTRL  73  is decreased from the supply voltage to a ground voltage and the current I_c 1  is decreased as shown in the equation 1, the collector voltage V C1  of the first transistor Q 1  is increased as shown in the equation 9 and the collector current I_c 2  of the third transistor Q 3  as shown in the equation 5. Therefore, the current I_c 3  is increased due to the current mirror relationship between the third transistor Q 3  and the fourth transistor Q 4  as shown in the equation 6.  
         [0069]     In addition, according to Equation 10 and Equation 11 as follows below, when the current I_cl and the current I_c 3  are increased, reference currents I_ 12 , I_q 10  of the bias current I_ 1   b , I_ 1   a  of the first amplification circuit unit  60  are decreased, thereby decreasing the bias current I_ 1   a . I_ 1   b  of the first amplification circuit unit  60 . 
 
I_ 12 ≈I_ref−I_c 1    [Equation 10]
 
I_q 5 ≈I_ 12 −I_c 3    [Equation 11]
 
         [0070]     Furthermore, when a voltage of the power controlling terminal VCTRL  73  is decreased, a reference current I_ref of the second amplification circuit unit  80  is divided into a collector current I_q 10  of the tenth transistor Q 10  and a current I_c 4  as follows: 
 
I_q 10 ≈I_ref−I_c 4 .   [Equation 12]
 
         [0071]     Therefore, the collector current of the tenth transistor Q 10  is decreased proportionally to increment in the current I_c 4 , and the bias current of the second amplification circuit unit  80  is decreased due to the current mirror relationship between the tenth transistor Q 10  and the twelfth transistor Q 12 . A high-frequency power of the high-frequency power amplifier proportional to decrement in such a bias current is decreased.  
         [0072]     The decreased ratio is the same as a proportional constant determined by a ratio of the first resistor R 1  and the second resistor R 2  and a ratio of a tenth resistor R 10  and a seventeenth resistor R 17 . The bias currents I_ 1   a , I_ 1   b , I_ 2  of the first amplification unit and the second amplification circuit unit are exponentially decreased depending on the voltage of a power controlling terminal VCTRL  73 . Accordingly, a power mW of high-frequency power amplifier proportional to a square of the bias currents I_ 1   a , I_ 1   b , I_ 2  is decreased.  
         [0073]     Furthermore, converting the power mW into the power dBm, an output power of the antenna is controlled by a unit of dB/V proportionally to the voltage of the power controlling terminal VCTRL  73 .  
         [0074]     On the other hand, procedures of breaking a power in the power breaking circuit unit will be described as follows.  
         [0075]     In the power breaking circuit unit, a fifteenth transistor Q 15  is a protection diode for playing a role of protecting an inner circuit of the high-frequency power amplifier by absorbing a static electricity supplied to the power breaking terminal VRAMP  72 .  
         [0076]     When the voltage of the power breaking terminal VRAMP  72  is decreased into a ground voltage in order to breaking a power of a high-frequency signal output to the antenna, the current I_ref of voltage-controlled current sources SRC 1 , SRC 2  is broken off by means of a twenty-forth resistor R 24 , a twenty-fifth resistor R 25  and a twenty-third resistor R 23 .  
         [0077]     When the current I_ref is cut off, the bias current I_ 12  of the fifth transistor Q 5  and the bias current of the tenth transistor Q 10  is cut off. Therefore, the bias currents I_ 1   a , I_ 1   b  of the first amplification circuit unit forming a current mirror relationship with the fifth transistor Q 5  and the tenth transistor Q 10  and the bias current of the twelfth transistor Q 12  of the second amplification circuit unit are cut off.  
         [0078]     Accordingly, the current I_ref of the voltage-controlled current source SRC 1 , SRC 2  is broken off or not based on the voltage of the power breaking terminal VRAMP  72  which is a voltage between both sides of the resistor R 24 .  
         [0079]     As described above, according to the communication system employing a high-frequency power amplifier having differential inputs of the present invention, it is possible to maintain performance of the communication system with decreasing the number of components and to reduce production cost, because a signal conversion unit used in the conventional communication system employing a power amplifier having a single input and a single output is not used.