Abstract:
A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.

Description:
BACKGROUND OF INVENTION 
     1) Field of the Invention 
     This invention relates generally to fabrication of semiconductor memory devices and more particularly to the fabrication of a self aligned floating gate using Shallow trench isolation. 
     2) Description of the Prior Art 
     More efficient utilization of device area in VLSI technology is a prominent objective in order to increase the density and number of devices and memory cells on a semiconductor chip. This reduces cost and increase the speed of operation. A known technique is to place various elements, i.e., shallow trench isolation (STI), transistors, capacitors, etch in trenches to achieve greater element density. 
     A deficiency with current memory devices is the poor quality of the intergate dielectric layers between the floating gate (FG) and the control gate (CG) which causes low breakdown voltages. The inconsistent quality of the intergate dielectric layers worsens as the devices are further shrunk and the intergate dielectric layers are made thinner. 
     The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,382,534 (Sheu et al.) shows a method for forming a recessed SID regions. U.S. Pat. No. 5,554,550 (Yang) shows a method for forming a gate in a trench. 
     However there is still a need for an improved memory cell formation and isolation method. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method for fabricating a memory device with improved intergate dielectric performance and increased floating gate (FG) to control gate (CG) breakdown voltage. 
     It is an object of the present invention to provide a method for fabricating a memory device which separates any corners of the floating gate (FG) and control gate (CG) layers to improve the intergate dielectric performance and increase floating gate (FG) to control gate (CG) breakdown. 
     It is an object of the present invention to provide a method for fabricating a memory device that defines the floating gate (FG) using the shallow trench isolation (STI) trench etch thereby reducing the masking and etching steps and creates a self-aligned structure. 
     To accomplish the above objectives, the present invention provides a method for patterning the poly gate and etching a shallow trench isolation (STI) trench in one mask/etch step. 
     The invention patterns the floating gate (FG) with the trench etch. The shallow trench isolation (STI) is formed above the top surface of the floating gate (FG). The corners of the floating gate (FG) are adjacent to the sidewalls of the shallow trench isolation (STI). Also, the corner of the control gate (CG) and are separated away from the floating gate (FG) corner. This separation of floating gate (FG) and control gate (CG) corners improves the stability, performance and reliability of the intergate dielectric layer (especially formed of ONO). 
     In slightly more detail, a preferred embodiment includes: providing a substrate having a cell area and a peripheral area. We form an first dielectric layer (gate oxide) and a first conductive layer (polysilicon layer) over the substrate. Then, a masking layer having first openings is formed over the conductive layer. The first opening defining isolation areas in the substrate where isolation regions will be formed. Using the masking layer as an etch mask, we etch through the first dielectric oxide layer and the conductive layer and into the substrate to form a trench. The remaining first dielectric layer and conductive layer comprise a tunnel dielectric layer and a floating gate of a memory device. The trench defining active regions and the isolation areas in the substrate. We fill the trench with an isolation layer to form isolation regions. We remove the masking layer; We deposit an intergate dielectric layer over the floating gate and the isolation layer. We form a second conductive layer (control gate layer) on the intergate dielectric layer over the floating gate. We pattern the second conductive layer, the intergate dielectric layer, the floating gate and the first dielectric layer to form memory gate structures comprising a control gate; a intergate dielectric; the floating gate; and the tunnel dielectric layer. We form doped regions in the substrate adjacent to the memory gate structures; thereby completing memory devices. 
     The invention has the following benefits: 
     no poly wrap around effect 
     the shallow trench isolation (STI)  24  reduces the sharp corner effect of a LOCOS isolation method thereby improving the intergate dielectric (ONO)  30  layer performance. 
     reduce the probability of twin bit failure from the bottom gate by using the gap fill as isolation  24  due to no ONO fence formation. Usually Flash or EPROM are placed very close to use maximum silicon area. By a LOCOS method due to the ONO fence formed beside floating gate, the material of floating gate or controlled gate may get trapped and create an electrical short (Known as twin bit failure). 
     The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of a semiconductor device according to the present invention and further details of a process of fabricating such a semiconductor device in accordance with the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which: 
     FIG. 1 is a cross sectional view for illustrating a method for manufacturing a memory device according to a prior art method. 
     FIG. 1A is a top down view of a cell area on a substrate according to a preferred embodiment of the present invention. 
     FIGS. 2A,  3 A,  4 A,  5 A, and  6 A are taken along axis A/A′ in FIG.  1 B. 
     FIGS. 2B,  3 B,  4 B,  5 B, and  6 B are taken along axis B/B′ in FIG.  1 B. 
     FIGS. 2A,  3 A,  4 A,  5 A,  6 A and  7 A are cross sectional views of a cell area for illustrating a method for manufacturing a memory device according to the present invention. 
     FIGS. 2,  3 ,  4 ,  5 , and  6  are taken along axis A/A′ in FIG.  1 . 
     FIGS. 2B,  3 B,  4 B,  5 B,  6 B and  7 B are cross sectional views a cell area for illustrating a method for manufacturing a memory device according to the present invention. 
     FIGS. 2B,  3 B,  4 B,  5 B, and  6 B are taken along axis B/B′ in FIG.  1 B. 
     FIGS. 2C,  3 C,  4 C,  4 D,  5 C,  6 C and  7 C are cross sectional views in a peripheral area (non-cell area) of a semiconductor device for illustrating a method for manufacturing a memory device according to the present invention. 
     FIG. 8 is a top plan view for illustrating a method for manufacturing a semiconductor memory device according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be described in detail with reference to the accompanying drawings. The present invention provides a method for patterning the poly gate (FG) and etching a shallow trench isolation (STI) trench in one mask/etch step. See FIG.  3 . 
     Problem of Sharp Edge between the Floating Gate (FG) and Control Gate (CG) in LOCOS Processes 
     The inventors have found that current LOCOS isolation structures implemented on memory devices cause low breakdown voltage problems between the floating gate (FG) and control gate (CG). 
     FIG. 1A shows a LOCOS process as known by the inventors. FIG. 1A shows a gate oxide  118  on a substrate having LOCOS isolation regions  114 . A floating gate (FG)  120  is formed and patterned over the gate oxide and LOCOS regions. Note that the floating gate (FG) has a sharp corner  130  adjacent to the control gate (CG) over the LOCOS region  114 . 
     Next, intergate dielectric layer  124  preferably composed of silicon oxide/silicon nitride/silicon oxide (ONO) are then formed. Next, a control gate (CG) is formed thereover. 
     The inventors have found that the sharp corners  130  of the FG and overlying CG and the vertical sidewalls  120 A cause breakdown  130  and leakage problems for the intergate dielectric layer  124 , especially ONO layers. See FIG.  1 . 
     A purpose of the invention is to eliminate this sharp corner of the FG and control gate. The invention also eliminates the sharp corner of the FG and isolation area. 
     Another shortcoming of the LOCOS isolation process is that the bird&#39;s peaks (at the corners of the Field oxide  114 ) cause leakage problems and use up valuable space. 
     Invention&#39;s Trench  20  Eliminates the Sharp Corners of Floating Gate (FG)  14   
     In the following description numerous specific details are set forth such as flow rates, pressure settings, thicknesses, etc., in order to provide a more thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these details. In other instances, well known process have not been described in detail in order to not unnecessarily obscure the present invention. 
     FIG. 1A is a top down view of a substrate according to a preferred embodiment of the present invention. FIGS. 2A,  3 A,  4 A,  5 A,  6 A and  7 A are taken along axis A/A′ in FIG.  1 A. FIGS. 2B,  3 B,  4 B,  5 B,  6 B and  7 B are taken along axis B/B′ in FIG.  1 A. 
     FIGS. 2C,  3 C,  4 C,  5 C, and  6 C are cross sectional views in a peripheral area (non-cell area) of the semiconductor device. 
     FIG. 6 is a top plan view for illustrating a method for manufacturing a semiconductor memory device according to the present invention. FIG. 6A is taken along axis  6 A/ 6 A′ in FIG.  6 . FIG. B is taken along axis  6 B/ 6 B′ in FIG.  6 . 
     Overview of the Invention 
     A preferred embodiment of the invention forms memory devices in cell areas and fet devices in peripheral areas (non-cell areas). An overview of the process follows: 
     a) provide a substrate  10  having a cell area and a peripheral area; 
     b) FIGS.  2 A &amp;  2 B—form an first dielectric layer (gate oxide)  12  and a first conductive layer (polysilicon layer)  14  over the substrate  10 ; 
     c) form a masking Layer  16  having first openings  17  over the conductive layer  14 ; the first opening defining isolation areas in the substrate where isolation regions will be formed; 
     d) FIGS.  3 A &amp;  3 B—using the masking layer  16  as an etch mask, etching through the first dielectric oxide layer  12  and the conductive layer  14  and into the substrate to form a trench  20 ; the remaining first dielectric layer  12  and conductive layer  14  comprise a tunnel dielectric layer  12  and a floating gate  14  of a memory device; the trench  20  defining active regions and the isolation areas in the substrate; 
     e) FIGS.  4 A &amp;  4 B—fill the trench  20  with an isolation layer  24  to form isolation regions  24 ; 
     f) planarizing the isolation regions using a chemical-mechanical polish or etch back process; 
     g) FIGS.  5 A &amp; B—removing the masking layer  16 ; 
     h) removing the a tunnel dielectric layer  12  and a floating gate  14  in the peripheral areas; 
     i) FIGS.  5 A and  5 B—form an intergate dielectric layer  30  over the floating gate  14  and the isolation layer  24  in the cell area; 
     j) form a gate dielectric layer on the substrate in the peripheral areas; 
     k) form a second conductive layer (control gate layer)  34  on the intergate dielectric layer  30  over the floating gate in the cell area and over the gate dielectric layer  32  in the peripheral areas; 
     l) FIGS. 6A &amp; 6B pattern the second conductive layer (control gate (CG))  34 , the intergate dielectric layer  30 , the floating gate (FG) and the first dielectric layer  12  to form memory gate structures  12   14   30   34  in the cell area comprising a control gate (CG)  34 ; a intergate dielectric  30  ; the floating gate (FG); and the tunnel dielectric layer  12 ; and in the peripheral areas, patterning the second conductive layer and the gate dielectric layer to form gate structures  32   34 ; 
     m) FIGS.  7 A &amp;  7 B—form doped regions in the substrate adjacent to the memory gate structures; thereby completing memory devices and forming doped regions  43  adjacent to the gate structures to form FET devices in the peripheral areas. 
     First Dielectric Layer  12  and Conductive Layer  14   
     FIGS. 2A,  2 B and  2 C shows the step of forming an first dielectric layer (gate oxide)  12  and a polysilicon layer  14  (conductive layer ) over a substrate  10 . 
     Substrate  10  is understood to possibly include a semiconductor wafer, active and passive devices formed within the wafer and layers formed on the wafer surface. The term “substrate” is mean to include devices formed within a semiconductor wafer and the layers overlying the wafer. 
     The first dielectric layer  12  (also called gate oxide or tunnel oxide) is preferably composed of silicon oxide and preferably has a thickness of between about 50 and 200 Å. The first dielectric layer is not limited to oxides and can be formed of other materials. 
     The conductive layer  14  can be formed of amorphous silicon, polycide or polysilicon and is most preferably formed of polysilicon and preferably has a thickness of between about 800 and 2000 Å. 
     Masking Layer  18   
     As shown in FIGS. 2A and 2B, a masking layer  16  (etch mask or CMP mask) is formed on the polysilicon layer  14 . The masking layer is patterned using conventional photoresist and etching steps. The masking layer has first openings  17  over the polysilicon layer  14 . The first opening define isolation areas in the substrate where shallow trench isolation (STI) isolation regions will be formed. The substrate also contains active areas which comprise all other areas that are not isolation areas. 
     The masking layer can be composed of silicon nitride, Si x O y N z  (Silicon oxynitride) or a combination of silicon nitride and oxide, and is preferably composed of silicon nitride (SiN) having a thickness of between about 1000 and 2500 Å. 
     Trench  20   
     FIGS. 3A,  3 B and  3 C show the key step of forming a trench  20  that defines the floating gate  14 . Using the masking layer  16  as a etch mask, we etch through the first dielectric oxide layer  12  and the polysilicon layer  14  and into the substrate to form a trench  20 . The trench  20  preferably has a width in a range of between about 0.2 μm and 10 μm and preferably a depth in a range of between about 2000 and 4500 Å. 
     The remaining first dielectric layer  12  and polysilicon layer  14  forming a tunnel dielectric layer  12  and a floating gate  14 . The trench  20  defining active regions and the isolation areas. The active area  20  preferably has a width of between about 0.3 μm and &gt;10 μm and more preferably between 0.3 and 10 μm. 
     This novel trench etch step eliminates the sharp corners between the floating gate (FG)  14  and the subsequently formed control gate (CG). See FIG.  5 . 
     Isolation Layer  24 —FIGS. 4A &amp; 4B 
     FIGS. 4A,  4 B and  4 C shows the step of filling the trench  20  with an isolation layer  24 . The trench  20  is preferably filled with an isolation layer  24  composed of silicon oxide. The isolation layer can be formed using a deposition technique such as a SACVD, LPCVD, etc. 
     Next, the isolation layer is planarized preferably so that the top surface of the isolation layer  24  is even with the top surface of the (SiN) masking layer  16 . The isolation layer is preferably planarized by a chemical-mechanical polish (CMP) using the masking layer  16  as a CMP stop. The isolation layer can also be planarized by an etch back or other suitable planarization technique. 
     FIGS.  5 A&amp;  5 B—Remove the Masking Layer  16 . 
     FIGS. 5A &amp; 5B &amp;  5 C shows the step of removing the masking layer  16 . The masking layer is preferably removed using a selective etch. 
     FIGS.  5 A &amp;  5 B—Intergate Dielectric Layer  30   
     Next, we deposit an intergate dielectric layer  30  over the floating gate  14  and the isolation layer  24 . The intergate dielectric layer  30  is preferably composed of a three layers (ONO) of a lower oxide layer, a middle nitride layer; and a top oxide layer. 
     In a preferred embodiment, the lower Oxide and middle nitride layers are formed over the substrate in both the cell and peripheral areas. The cell area is masked and the lower Oxide and middle nitride are then removed from the peripheral areas along with the first dielectric layer  12  and the control gate (CG) layer  34 . See FIG.  5 C. 
     The top oxide layer can also be formed on the peripheral areas to serve as the gate oxide layer  32  (gate oxide—2) for the devices  32   34   43  in the peripheral areas. See FIG.  6 C. 
     The intergate dielectric layer  30  preferably has a total thickness of between about 100 and 400 Å. 
     Control Gate  34   
     Next, a control gate  34  is formed on the intergate dielectric layer  30  over the floating gate thereby forming a memory device. 
     The control gate  34  is preferably composed of polycide or polysilicon and is most preferably composed of polysilicon. The control gate preferably has a thickness of between about 1500 and 3500 Å. 
     The invention patterns the floating gate (FG)  14  with the trench etch. See FIG. 3A &amp; 3B. The shallow trench isolation (STI)  24  is formed above the top surface of the floating gate (FG)  14 . See FIGS. 5A &amp; 5B. The corners of the floating gate (FG)  14  are adjacent to the sidewalls of the shallow trench isolation (STI)  14 . Also, the corner  34 A of the control gate (CG)  34 A and  34 B are spaced away from the floating gate (FG) corner  14 A. See FIG.  5 . This separation of floating gate (FG) and control gate (CG) corners improves the stability, performance and reliability of the intergate dielectric layer  30  (especially formed of ONO). 
     The invention provides the following advantages: 
     no polysilicon wrap around at the STI edge 
     no overlap between the floating gate and isolation area 
     No ONO stringers beside the floating gate 
     FIG.  8 —Top View 
     FIG. 8 shows a top down view of the invention&#39;s memory cell after the control gates  34  are patterned. 
     FIG. 7B is a cross sectional view taken along axis  6 B/ 6 B′ in FIG. 8 showing the formation of doped regions  42  in the substrate adjacent to the gate structures and the formation of a dielectric layer  46  thereover. FIG. 7A is a cross sectional view taken along axis  6 B/ 6 B′ in FIG.  8 . 
     FIG. 7C is a cross sectional view in the peripheral area showing the formation of the S/D regions  43  and the dielectric layer  46 . 
     FIGS. 2C thru  7 C show Cross Sections in the Peripheral Areas 
     FIGS. 2 c  thru  7 C cross sectional views in the peripheral areas (non-cell area) showing the formation of devices. The formation processes shown in the  2 C correspond to the process shown in FIGS. 2A and 2B (cell areas). The formation processes shown in the  3 C correspond to the process shown in FIGS. 3A and 3B (cell areas). The formation steps shown in  4 C correspond to the process shown in FIGS. 4A and 4B (cell areas). 
     FIG. 4D shows the additional step to remove the FG material in the peripheral area. 
     FIG. 5C shows the formation of the gate oxide—2 in the peripheral areas, and the deposition of the control gate (CG)  34  thereover to form a FET device. The CG is patterned to form a gate structure. Next, source and drain regions are formed adjacent to the gate structures in the peripheral areas, preferably in the same process steps used in the cell areas. Next, a dielectric layer is formed over the entire substrate and contacts are formed to the source/drain regions and conductive structures (e.g., control gate (CG), gates and wordlines). 
     FIG. 6C shows the patterning of the gate  34  and gate oxide  32 . 
     FIG. 7C is a cross sectional view in the peripheral area showing the formation of the S/D regions  43  and the dielectric layer  46 . 
     It should be recognized that many publications describe the details of common techniques used in the fabrication process of integrated circuit components. Those techniques can be generally employed in the fabrication of the structure of the present invention. Moreover, the individual steps of such a process can be performed using commercially available integrated circuit fabrication machines. As specifically necessary to an understanding of the present invention, exemplary technical data are set forth based upon current technology. Future developments in the art may call for appropriate adjustments as would be obvious to one skilled in the art. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.