Abstract:
A temperature sensing circuit that detects a given temperature includes a first differential input circuit and a second differential input circuit connected to the first differential input circuit. The first differential input circuit is configured to provide a first offset voltage with no temperature coefficient. The second differential input circuit is configured to provide a second offset voltage with a non-zero temperature coefficient. The given temperature is detected based on the first offset voltage and the second offset voltage. An electronic device using such a temperature sensing circuit is also disclosed.

Description:
TECHNICAL FIELD 
     This disclosure relates to a temperature sensing circuit, and more particularly, to a temperature sensing circuit that detects temperature based on a difference in gate work function between multiple transistors, and electronic devices, such as voltage regulators, personal computers, portable devices, and home appliances, using such a temperature sensing circuit. 
     DISCUSSION OF THE BACKGROUND 
     Temperature sensing circuits are used in various electronic devices, such as voltage regulators, personal computers, and various kinds of portable devices and home appliances, where control is performed in response to changes in ambient temperature. 
       FIG. 1  is a diagram illustrating an example of a conventional temperature sensing circuit. 
     As shown in  FIG. 1 , the conventional circuit includes a comparator  30 , a reference voltage Vr, diodes D 1  and D 2 , and a constant current source I 1 . 
     In the temperature sensing circuit, the constant current source I 1  and the diodes D 1  and D 2  are connected in series between a voltage source Vdd and ground, forming a node N 1  between the current source I 1  and the diode D 1 . The comparator  30  has a non-inverting input connected to the node N 1 , an inverting input connected to the reference voltage Vr, and an output to provide a temperature detection signal Out. 
     During operation, the comparator  30  compares a voltage drop across the diodes D 1  and D 2  against the reference voltage Vr. The voltage Vr is generated by an appropriate source (e.g., a bandgap regulator) having a good temperature coefficient. The comparator output Out switches according to whether the voltage drop is above or below the reference voltage Vr. 
     The above temperature sensing circuit is designed to take advantage of the fact that the voltage drop across the series diodes D 1  and D 2  biased with the constant current I 1  has a temperature coefficient. However, such a conventional design involves various electronic components for implementing various functions, such as pn junction diodes for the series diodes D 1  and D 2 , a voltage regulator for the reference voltage source Vr, and other elements for the comparator  30 , leading to increased size and complexity of the temperature sensing circuit. 
     By contrast, instead of using a voltage drop across coupled diodes, some recent techniques provide temperature sensing capabilities through use of a difference in gate work function between metal-oxide-semiconductor field-effect transistors (MOSFETs) with a controlled temperature coefficient. 
       FIG. 2  is a block diagram schematically illustrating an example of such a temperature sensing circuit. 
     As shown in  FIG. 2 , the temperature sensing circuit includes a first voltage generator  101 , a second voltage generator  102 , a subtractor  103 , and a comparator  104 . 
     The first voltage generator  101  generates a voltage Svptat proportional to absolute temperature (PTAT) and hence having a linear temperature coefficient either positive or negative. The second voltage generator  102  generates a first reference voltage Vref, a second reference voltage Tvref, and a third reference voltage Svref, all having no temperature coefficient. 
     The subtractor  103  amplifies a difference between the voltage Svptat and the third reference voltage Svref to provide an output Tvptat to the comparator  104 . The comparator  104  then compares the signal Tvptat against the second reference voltage Tvref to output a temperature detection signal Tout. 
     In such a configuration, the second voltage generator  102  providing a voltage with no temperature coefficient operates based on a difference in gate work function between multiple FETs. 
       FIG. 3  is a diagram illustrating still another example of temperature sensing circuit. 
     As shown in  FIG. 3 , the temperature sensing circuit includes a first voltage generator  201 , a second voltage generator  202 , an impedance transformer  203 , and a subtractor  204 . 
     The first voltage generator  201  generates an output voltage VPN with a negative temperature coefficient based on a difference in gate work function between a pair of FETs. 
     The second voltage generator  202  generates a reference voltage VREF 1  with no temperature coefficient based on a difference in gate work function between multiple FETs. 
     The impedance transformer  203  includes first and second operational amplifiers (op-amps) AMP 1  and AMP 2 , and performs impedance transformation on the signals VPN and VREF 1  prior to transmission to the subtractor  204 . 
     In the impedance transformer  203 , the first and second op-amps AMP 1  and AMP 2  each forms a voltage follower with an output connected to an inverting input. The first op-amp AMP 1  receives the voltage VPN at a non-inverting input and provides a low-impedance output to one input terminal of the subtractor  204 . Similarly, the second op-amp AMP 2  receives the voltage VREF 1  at a non-inverting input and provides a low-impedance output to another input terminal of the subtractor  204 . 
     The subtractor  204  includes an op-amp AMP and resistors R 1  through R 4 , and provides a temperature detection signal VOUT at an output of the op-amp AMP. 
     In the subtractor  204 , the op-amp AMP receives the reference voltage VREF 1  at a non-inverting input via the resistor R 1  and the voltage VPN at an inverting input via the resistor R 3 , with the resistor R 2  connected between the non-inverting input and ground, and the resistor R 4  connected between the output and inverting input. The temperature detection signal VOUT is generated through subtraction between the input voltages VREF 1  and VPN. 
     In such a configuration, a voltage VREF 1 -VPN obtained by subtracting the negative-temperature-coefficient voltage VPN from the no-temperature-coefficient voltage VREF 1  has a positive temperature coefficient. Thus, the detection signal VOUT obtained by amplifying VRFF 1 -VPN also has a positive temperature coefficient greater than that of the difference voltage VRFF 1 -VPN, which provides good detection accuracy and low energy consumption of the temperature sensing circuit. 
     Although providing temperature sensing capabilities without using diodes, the MOSFET-based approaches illustrated in  FIGS. 2 and 3  do not provide a satisfactory reduction in circuit size, since these circuits require two voltage generators, one with a temperature coefficient and the other with no temperature coefficient, in addition to a comparator for comparing the outputs of the voltage generators. 
     Accordingly, there remains a need for a temperature sensing circuit that provides a good temperature detection performance in a simple and compact circuit configuration. Such a circuit will contribute to a size reduction of various electronic devices incorporating temperature sensing capabilities. 
     BRIEF SUMMARY 
     This disclosure describes a novel temperature sensing circuit based on a difference in gate work function between multiple transistors. 
     In one aspect of the disclosure, the novel temperature sensing circuit that detects a given temperature includes a first differential input circuit and a second differential input circuit connected to the first differential input circuit. The first differential input circuit is configured to provide a first offset voltage with no temperature coefficient. The second differential input circuit is configured to provide a second offset voltage with a non-zero temperature coefficient. The given temperature is detected based on the first offset voltage and the second offset voltage. 
     This disclosure also describes a novel electronic device incorporating the temperature sensing circuit described above. 
     In one aspect of the disclosure, the novel electronic device includes a temperature sensing circuit that detects a given temperature. The temperature sensing circuit includes a first differential input circuit and a second differential input circuit connected to the first differential input circuit. The first differential input circuit is configured to provide a first offset voltage with no temperature coefficient. The second differential input circuit is configured to provide a second offset voltage with a non-zero temperature coefficient. The given temperature is detected based on the first offset voltage and the second offset voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The aforementioned and other aspects, features and advantages would be better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIG. 1  is a diagram illustrating an example of a conventional temperature sensing circuit; 
         FIG. 2  is a block diagram schematically illustrating an example of another conventional temperature sensing circuit; 
         FIG. 3  is a diagram illustrating an example of still another conventional temperature sensing circuit; 
         FIG. 4A  is a diagram illustrating an embodiment of a temperature sensing circuit according to this patent specification; 
         FIGS. 4B and 4C  are circuit diagrams of an operational amplifier and a comparator, respectively, used in the temperature sensing circuit of  FIG. 4A ; 
         FIG. 5  shows voltage plotted against temperature, illustrating operation of the temperature sensing circuit of  FIG. 4A ; 
         FIG. 6  is a diagram illustrating another embodiment of the temperature sensing circuit; 
         FIG. 7  shows voltage plotted against temperature, illustrating operation of the temperature sensing circuit of  FIG. 6 ; 
         FIG. 8  is a diagram illustrating still another embodiment of the temperature sensing circuit; 
         FIG. 9  shows voltage plotted against temperature, illustrating operation of the temperature sensing circuit of  FIG. 8 ; 
         FIG. 10  is a diagram illustrating still another embodiment of the temperature sensing circuit; 
         FIG. 11  shows voltage plotted against temperature, illustrating operation of the temperature sensing circuit of  FIG. 10 ; 
         FIG. 12  is a diagram illustrating still another embodiment of the temperature sensing circuit; 
         FIG. 13  shows voltage plotted against temperature, illustrating operation of the temperature sensing circuit of  FIG. 12 ; 
         FIG. 14  is a diagram illustrating still another embodiment of the temperature sensing circuit; 
         FIG. 15  shows voltage plotted against temperature, illustrating operation of the temperature sensing circuit of  FIG. 14 ; and 
         FIG. 16  is a diagram illustrating in detail the temperature sensing circuit of  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     In describing exemplary embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner and achieve a similar result. Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, examples and exemplary embodiments of this disclosure are described. 
       FIG. 4A  is a diagram illustrating an embodiment of a temperature sensing circuit  1  according to this patent specification. 
     As shown in  FIG. 4A , the temperature sensing circuit  1  includes an operational amplifier or op-amp  10  and a comparator  20 . 
     The op-amp  10  includes a first differential input circuit Sd 1  in an input stage with an inverting input positive with respect to a non-inverting input. The first differential input circuit Sd 1  provides a first offset voltage Vo 1  having no temperature coefficient. 
     The op-amp  10  has an output connected to the inverting input to form a voltage follower. With the non-inverting input connected to ground, the output of the op-amp  10  is equal to the first offset voltage Vo 1 . 
     The comparator  20  includes a second differential input circuit Sd 2  in an input stage with an inverting input positive with respect to a non-inverting input. The second differential input circuit Sd 2  provides a second offset voltage Vo 2  having a negative temperature coefficient. 
     The comparator  20  has the inverting input connected to the output of the op-amp  10  and the non-inverting input connected to ground. Through comparison of the inverting and non-inverting inputs, the comparator  20  outputs a temperature detection signal Out indicating when temperature reaches a given set-point Ts. 
       FIGS. 4B and 4C  are circuit diagrams of the op-amp  10  and the comparator  20  used in the temperature sensing circuit  1  of  FIG. 4A . 
     As shown in  FIGS. 4B and 4C , the op-amp  10  and the comparator  20  both are built based on a combination of metal-oxide-semiconductor field-effect transistors (MOSFETs), a detailed description of which will be given with reference to  FIG. 16 . 
       FIG. 5  shows the voltages Vo 1  and Vo 2  plotted against temperature, illustrating operation of the temperature sensing circuit  1  of  FIG. 4A  near the set temperature Ts. 
     As shown in  FIG. 5 , the first offset voltage Vo 1  or the output of the op-amp  10  does not vary with temperature due to having no temperature coefficient, while the second offset voltage Vo 2  or the input stage voltage of the comparator  20  decreases with increasing temperature due to having a negative temperature coefficient. 
     Specifically, the voltage Vo 2  remains higher than the voltage Vo 1  at temperatures below the set-point Ts, matches Vo 1  at the set-point Ts, and falls below Vo 1  when temperature exceeds the set-point Ts. 
     Thus, the temperature detection signal Out output by the comparator  20 , which is high for Vo 2 &gt;Vo 1  and low for Vo 2 &lt;Vo 1 , switches at the set-point Ts. 
       FIG. 6  is a diagram illustrating another embodiment of the temperature sensing circuit  1 . 
     As shown in  FIG. 6 , this embodiment is similar to that depicted in  FIG. 4A , except that the temperature sensing circuit  1  includes resistors R 1  and R 2  forming a voltage divider to divide the op-amp output Vo 1  so that the comparator  20  receives a scaled voltage VA at the inverting input. 
       FIG. 7  shows the voltages Vo 1 , Vo 2 , and VA plotted against temperature, illustrating operation of the temperature sensing circuit  1  of  FIG. 6  near the set temperature Ts. 
     As shown in  FIG. 7 , the inverting input VA of the comparator, obtained from the temperature-independent voltage Vo 1 , does not vary with temperature, while the temperature-dependent voltage Vo 2  decreases with increasing temperature. The temperature detection signal Out output by the comparator  20  is high for Vo 2 &gt;VA and low for Vo 2 &lt;VA, switching at the set-point Ts. 
       FIG. 8  is a diagram illustrating still another embodiment of the temperature sensing circuit  1 . 
     As shown in  FIG. 8 , this embodiment is similar to that depicted in  FIG. 4A , except that the op-amp  10  is provided with a resistor R 3  interposed between its inverting input and output and a resistor R 4  between its inverting input and ground, so as to have a gain of 1+R 3 /R 4  instead of forming a voltage follower. 
       FIG. 9  shows the voltages Vo 1 , Vo 2 , and VA plotted against temperature, illustrating operation of the temperature sensing circuit  1  of  FIG. 8  near the set temperature Ts. 
     As shown in  FIG. 9 , the inverting input VA of the comparator, obtained from the temperature-independent voltage Vo 1 , does not vary with temperature, while the temperature-dependent voltage Vo 2  decreases with increasing temperature. The temperature detection signal Out output by the comparator  20  is high for Vo 2 &gt;VA and low for Vo 2 &lt;VA, switching at the set-point Ts. 
       FIG. 10  is a diagram illustrating still another embodiment of the temperature sensing circuit  1 . 
     As shown in  FIG. 10 , this embodiment is similar to that depicted in  FIG. 4A , except that the second differential input circuit Sd 2  with temperature coefficient is included in the input stage of the op-amp  10 , and the first differential input circuit Sd 1  with no temperature coefficient is included in the input stage of the comparator  20 . 
       FIG. 11  shows the voltages Vo 1 , Vo 2 , and VA plotted against temperature, illustrating operation of the temperature sensing circuit  1  of  FIG. 10  near the set temperature Ts. 
     As shown in  FIG. 11 , the first offset voltage Vo 1  or the input stage voltage of the comparator  20  does not vary with temperature due to having no temperature coefficient, while the second offset voltage Vo 2  or the output of the op-amp  10  decreases with increasing temperature due to having a negative temperature coefficient. 
     As a result, the temperature detection signal Out output by the comparator  20 , which is low for Vo 2 &gt;Vo 1  and high for Vo 2 &lt;Vo 1 , switches at the set-point Ts. 
       FIG. 12  is a diagram illustrating another embodiment of the temperature sensing circuit  1 . 
     As shown in  FIG. 12 , this embodiment is similar to that depicted in  FIG. 10 , except that the temperature sensing circuit  1  includes resistors R 1  and R 2  forming a voltage divider to divide the op-amp output Vo 1  so that the comparator  20  receives a scaled voltage VA at the inverting input. 
       FIG. 13  shows the voltages Vo 1 , Vo 2 , and VA plotted against temperature, illustrating operation of the temperature sensing circuit  1  of  FIG. 12  near the set temperature Ts. 
     As shown in  FIG. 13 , the inverting input VA of the comparator  20 , obtained from the temperature-dependent voltage Vo 2 , decreases with increasing temperature, while the temperature-independent voltage Vo 1  does not vary with temperature. The temperature detection signal Out output by the comparator  20  is low for VA&gt;Vo 1  and high for VA&lt;Vo 1 , switching at the set-point Ts. 
       FIG. 14  is a diagram illustrating still another embodiment of the temperature sensing circuit  1 . 
     As shown in  FIG. 14 , this embodiment is similar to that depicted in  FIG. 10 , except that the op-amp  10  is provided with a resistor R 3  interposed between its inverting input and output and a resistor R 4  between its inverting input and ground, so as to have a gain of 1+R 3 /R 4  instead of forming a voltage follower. 
       FIG. 15  shows the voltages Vo 1 , Vo 2 , and VA plotted against temperature, illustrating operation of the temperature sensing circuit  1  of  FIG. 14  near the set temperature Ts. 
     As shown in  FIG. 15 , the inverting input VA of the comparator  20 , obtained from the temperature-dependent voltage Vo 2 , decreases with increasing temperature, while the temperature-independent voltage Vo 1  does not vary with temperature. The temperature detection signal Out output by the comparator  20  is low for VA&gt;Vo 1  and high for VA&lt;Vo 1 , switching at the set-point Ts. 
     In the temperature sensing circuit  1  described above, the first differential input circuit Sd 1  providing the offset voltage Vo 1  with zero temperature coefficient and the second differential input circuit Sd 2  providing the offset voltage Vo 2  with temperature coefficient are included in the input stages of the op-amp  10  and the comparator  20 , respectively. As the comparator  20  incorporates the capabilities of a reference voltage generator and a temperature-dependent voltage source, which are required to construct a temperature sensing circuit, a compact circuit configuration is achieved without involving complicated electronic components. 
     Further, the zero-temperature coefficient circuit Sd 1  and the temperature-dependent circuit Sd 2  each can be used as the input stage of either the op-amp  10  or the comparator  20  as shown in the illustrated embodiments, where the temperature coefficient is present in the comparator  20  and not in the op-amp  10  for the embodiments of  FIGS. 4A ,  6 , and  8 , and vice versa for the embodiments of  FIGS. 10 ,  12 , and  14 . Such interchangeability of the differential input circuits Sd 1  and Sd 2  allows for wide variations in the design of the temperature sensing circuit  1 . 
     Still further, the temperature sensing circuit  1  can assume various configurations of the op-amp  10 , such as those having high gain or amplification, those having unity gain (i.e., the voltage follower), or those having resistors to divide the output voltage, which offers flexibility to respond to variations in the magnitude and/or temperature coefficient of the offset voltages Vo 1  and Vo 2 . 
     Additionally, although the non-inverting input of the op-amp  10  and the reference input of the comparator  20  are grounded in the illustrated embodiments, these terminals may be connected to an appropriate voltage other than ground potential. In the embodiments using a pair of resistors to amplify or divide the op-amp output, i.e., the voltage divider R 1  and R 2  or the gain resistors R 3  and R 4 , a higher accuracy in temperature detection may be obtained by tuning resistance of one or both of the paired resistors through trimming or the like. 
     Referring now to  FIG. 16 , a diagram illustrating in detail the temperature sensing circuit  1  according to the embodiment of  FIG. 6  is depicted. 
     As shown in  FIG. 16 , the op-amp  10  includes depletion-type n-channel MOS (NMOS) transistors M 11  and M 12 , NMOS transistors M 13  and M 17 , and p-channel MOS (PMOS) transistors M 14  through M 16 , each having MOSFET gate, source, and drain terminals. 
     The depletion-type NMOS transistors M 11  and M 12  form the first differential input circuit Sd 1  in the input stage of the op-amp  10 , where the gate of the NMOS transistor M 11  serves as the inverting input and the gate of the NMOS transistor M 12  serves as the non-inverting input. 
     The sources of the input transistors M 11  and M 12  are connected in common to the drain of the NMOS transistor M 13 . The NMOS transistor M 13  has its source connected to ground and its gate connected to a bias voltage Vbias. 
     The drain of the NMOS transistor M 11  is connected to the drain of the PMOS transistor M 14 , and the drain of the NMOS transistor M 12  is connected to the drain of the PMOS transistor M 15 . 
     The PMOS transistors M 14  and M 15  have their sources connected in common to a voltage source Vdd and their gates connected in common to the drain of the PMOS transistor M 14  to form a current mirror, which acts as a load in the differential input circuit Sd 1 . 
     The drain of the NMOS transistor M 12  is connected to the gate of the PMOS transistor M 16 . The PMOS transistor M 16  has its source connected to the voltage source Vdd and its drain connected to the drain of the NMOS transistor  17 . The NMOS transistor M 17  has its source connected to ground and its gate connected to the bias voltage Vbias in common with the gate of the NMOS transistor M 13 . 
     The op-amp  10  derives an output voltage from the drain of the PMOS transistor M 16 . As mentioned, the op-amp  10  forms a voltage follower with the inverting input, i.e., the gate of the NMOS transistor M 11 , connected to the output voltage. With its non-inverting input, i.e., the gate of the NMOS transistor M 12 , connected to ground, the op-amp  10  provides the output voltage equal to the offset voltage Vo 1  of the differential input circuit Sd 1 . 
     In such a configuration, the offset voltage Vo 1  results from a difference in threshold voltage between the input transistors M 11  and M 12 . 
     In general, threshold voltage of a MOS transistor may be adjusted by doping, i.e., by implanting impurities called dopants of a particular conductivity type, to change work function of the gate terminal, where a p-type doped (P+) gate has a relatively high threshold voltage and an n-type doped (N+) gate has a relatively low threshold voltage. 
     In the differential input circuit Sd 1 , the gate of the transistor M 11  is doped with p-type impurities and the gate of the transistor M 12  is doped with n-type impurities, so that the transistor M 11  has a higher threshold voltage than that of the transistor M 12 . Hence, the offset voltage Vo 1  is obtained with the input transistor M 11  having a positive gate potential relative to that of the input transistor M 12 . 
     The temperature coefficient of the offset voltage Vo 1  thus obtained is dependent on the ratio of size or gate length between the input transistors M 11  and M 12 . In the differential input circuit Sd 1 , the size ratio of the transistor M 11  to the transistor M 12  is set to approximately 2:1 to provide the offset voltage Vo 1  with zero temperature coefficient. 
     With further reference to  FIG. 16 , the output terminal of the op-amp  10  is connected to the inverting input of the comparator  20  via the voltage divider resistors R 1  and R 2 . 
     The comparator  20  includes depletion-type NMOS transistors M 21  and M 22 , an NMOS transistor M 23 , and PMOS transistors M 24  and M 25 , each having MOSFET gate, source, and drain terminals. 
     The depletion-type NMOS transistors M 21  and M 22  form the second differential input circuit Sd 2  in the input stage of the comparator  20 , where the gate of the NMOS transistor M 21  serves as the inverting input and the gate of the NMOS transistor M 22  serves as the non-inverting input. 
     The sources of the input transistors M 21  and M 22  are connected in common to the drain of the NMOS transistor M 23 . The NMOS transistor M 23  has its source connected to ground and its gate connected to a bias voltage Vbias. 
     The drain of the NMOS transistor M 21  is connected to the drain of the PMOS transistor M 24 , and the drain of the NMOS transistor M 22  is connected to the drain of the PMOS transistor M 25 . 
     The PMOS transistors M 24  and M 25  have their sources connected in common to a voltage source Vdd and their gates connected in common to the drain of the PMOS transistor M 25  to form a current mirror, which acts as a load in the differential input circuit Sd 2 . 
     The comparator  20  derives the output Out from the drain of the NMOS transistor M 21 , which switches when the offset voltage Vo 2  reaches the level of the inverting input. 
     In such a configuration, as in the case of the first offset voltage Vo 1 , the offset voltage Vo 2  results from a difference in threshold voltage between the input transistors M 21  and M 22 , obtained by creating a difference in gate work function. 
     Specifically, the gate of the transistor M 21  is doped with p-type impurities and the gate of the transistor M 22  is doped with n-type impurities, so that the transistor M 21  has a higher threshold voltage than that of the transistor M 22 . Hence, the offset voltage Vo 2  is obtained with the input transistor M 21  having a positive gate potential relative to that of the input transistor M 22 . 
     The offset voltage Vo 2  of the differential input circuit Sd 2  thus obtained has a negative temperature coefficient, which is created by setting the size ratio of the transistor M 21  to the transistor M 22  to approximately 1:10. 
     As described above, the differential input circuit according to this patent specification has an offset voltage controlled by a difference in gate work function between a pair of input transistors, one with a P+ doped gate and the other with an N+ doped gate. The size ratio of the input transistors is adjusted so as to set the temperature coefficient of the offset voltage to zero or any appropriate value positive or negative. 
     Through effective use of the differential input circuit, the temperature sensing circuit  1  according to this patent specification achieves precise temperature detection with a simple and compact circuit configuration. 
     The temperature sensing circuit  1  may be used in any type of electronic equipment, such as voltage regulators, personal computers, and various types of portable devices and home appliances, where temperature sensing capability is required to perform a given function in response to detection of a given set-point temperature, such as switching of power and/or control signals. 
     Numerous additional modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein. 
     This patent specification is based on Japanese patent application No. JP-A-2007-233788 filed on Sep. 10, 2007 in the Japanese Patent Office, the entire contents of which are hereby incorporated by reference herein.