Abstract:
A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain. The level shifter circuit is also coupled to receive a clock signal from a second voltage domain. On a first portion of the clock cycle, true and complementary output nodes of the level shifter circuit (which are in the second voltage domain) are pulled to a first voltage by activation of respective pull transistors. On a second portion of the clock cycle, one of the true or complementary output nodes is pulled to a second voltage on a second voltage node by enabling the supply to the latch. Data is captured by the keeper, outputting true and complementary versions of the data signal in the second phase of the clock.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates to electronic circuits, and more particularly, to level shifter circuits for shifting data from one voltage domain to another. 
         [0003]    2. Description of the Related Art 
         [0004]    In many electronic devices, data must be conveyed from a first voltage domain (having a first power supply voltage) to a second voltage domain (having a second power supply voltage). Circuits used to accomplish this task are known as level shifters. A level shifter circuit is configured to receive data in the first voltage domain and output the data into the second voltage domain. 
         [0005]      FIG. 1  is a schematic diagram of an exemplary level shifter. In the embodiment is shown, data from a first voltage domain having a supply voltage of 3.3 volts is input into the level shifter. Data is output from the level shifter into a voltage domain having a supply voltage of 1.6 volts. In general, level shifters may provide a downshift in voltage (as in the example here), or an upshift in voltage. 
         [0006]    Level shifter circuits typically include a pair of cross-coupled inverter circuits that are coupled to an input circuit. In order to cause the transistors of the cross-coupled inverters to change states (when the data similarly changes states), the transistors of the input circuits must provide sufficient drive strength. Providing a sufficient amount of drive strength typically requires the implementation of an input circuit that utilizes devices capable of providing the drive strength necessary to change the state of the keeper circuit. 
       SUMMARY OF THE INVENTION 
       [0007]    A level shifter circuit and method of operating therefor are provided. In one embodiment, a level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain. The level shifter circuit is also coupled to receive a clock signal from a second voltage domain. On a first portion of the clock cycle, true and complementary output nodes of the level shifter circuit (which are in the second voltage domain) are pulled to a first voltage by activation of respective pull transistors. On a second portion of the clock cycle, one of the true or complementary output nodes is pulled to a second voltage on a second voltage node by enabling the supply to the latch. Data is captured by the keeper, outputting true and complementary versions of the data signal in the second phase of the clock. 
         [0008]    In one embodiment, the level shifter circuit includes an input circuit and a keeper circuit. The keeper circuit includes a pair of cross-coupled inverter circuits. An output node of the first inverter is coupled to the true output node, and wherein an output node of the second inverter is coupled to the complementary output node. The keeper circuit is configured to hold a data state unless the data state is changed by new data received by the input circuit. 
         [0009]    Depending on the specific embodiment, the level shifter circuit may be configured to pre-charge or pre-discharge the output nodes on the first portion of the clock cycle. In embodiments wherein the voltage of the first voltage domain is less than the voltage of the second voltage domain, both the true and complementary nodes are pre-charged on a low portion of the clock cycle. On a high portion of the clock cycle, one of the true or complementary nodes is pulled down to a second voltage, wherein the second voltage is an intermediate voltage between the first voltage and a reference voltage. The pull-down during the high portion of the clock cycle may cause the keeper to change states, depending on the state of the input data signal (e.g. if the input data signal is a logic low and the true output node is a logic high prior to inputting the data signal, the state of the true output node, and thus the keeper circuit, will change to a logic low on the high portion of the clock signal). 
         [0010]    In another embodiment in which the voltage of the first voltage domain is greater than the voltage of the second voltage domain, both the true and complementary output nodes are pre-discharged during a high portion of a complementary (i.e. inverted) clock signal. The true and complementary outputs are pre-discharged by pulling them down to a reference voltage. During the low portion of the complementary clock cycle, one of the true or complementary outputs is pulled up to a second voltage, which is an intermediate voltage between the reference voltage and the supply voltage of the first voltage domain. The pull-up during the low portion of the complementary clock cycle will cause one of the true or complementary outputs, depending on the input data, to be pulled up to the second voltage, which is the supply voltage of the second voltage domain. With the use of a clock signal, the level shifter circuit functions as a latch. 
         [0011]    In various embodiments, the input circuit is configured to receive true and complementary values of the input data signal via pass transistors. Since the various embodiments of the circuit are configured to either precharge or pre-discharge the output nodes (which are also input nodes to the cross-coupled inverters of the keeper circuit), the pass transistors are not required to provide a drive strength sufficient to cause the state of the keeper circuit to change. Thus, these devices may be relatively small, thereby conserving area. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    Other aspects of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: 
           [0013]      FIG. 1  (prior art) is a diagram of an exemplary level shifter; 
           [0014]      FIG. 2  is a schematic diagram of one embodiment of a level shifter having a pre-discharge circuit; 
           [0015]      FIG. 3  is a timing diagram illustrating the operation of the circuit shown in  FIG. 2 ; 
           [0016]      FIG. 4  is a schematic diagram of an embodiment of a level shifter having a pre-charge circuit; and 
           [0017]      FIG. 5  is a timing diagram illustrating the operation of the circuit shown in  FIG. 4 . 
       
    
    
       [0018]    While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and description thereto are not intended to limit the invention to the particular form disclosed, but, on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling with the spirit and scope of the present invention as defined by the appended claims. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    Turning now to  FIG. 2 , a schematic diagram of one embodiment of a level shifter having a pre-discharge circuit is shown. In the embodiment shown, level shifter circuit  200  is configured to transfer data from a higher voltage domain to a lower voltage domain. That is, the power supply voltage for the higher voltage domain is greater than that of the lower voltage domain. 
         [0020]    Level shifter circuit  200  includes an input circuit comprising transistors I 2 , I 3 , I 10 , and I 11 . Input terminals In_H and its complement, In_X_H are coupled to the input circuit. Transistors I 10  and I 11  allow the input signal In_H to pass, while transistors I 2  and I 3  allow the complementary input signal In_X_H to pass. The transistors of the input circuit are arranged in a cascade configuration in order to latch the input data through to the output nodes (and thus to the keeper circuit). The transistors may be turned on or off depending on the voltages of the input signals (i.e. the states of the data) and their respective threshold voltages, as well as the voltages placed on the output nodes during the pre-discharge operation. 
         [0021]    Level shifter circuit  200  also includes a keeper circuit. The keeper circuit includes transistors I 4 , I 5 , I 7  and I 8  coupled together in a cross-coupled inverter configuration. Transistors I 4  and I 5  make up a first inverter, while transistors I 7  and I 8  make up a second inverter. The output of the first inverter is also coupled to an output node, Out_X_L, and is also coupled to the input of the second inverter. Similarly, the output of the second inverter is coupled to the other output node, Out_L, and is further coupled to the input of the first inverter. Furthermore, the input In_H is coupled to the input of the first inverter, while the input In_X_H is coupled to the input of the second inverter. 
         [0022]    In this particular embodiment, level shifter circuit  200  includes a pull-up transistor I 6  coupled to the keeper circuit. Level shifter circuit  200  also includes a pair of pull-down transistors I 12  and I 13 , which are coupled to output nodes Out_L and Out_X_L, respectively. The pull-down transistors and the pull up transistors are configured to be activated during opposite phases of a clock cycle. In this particular case, the clock signal, received by level shifter circuit  200 , clk_X_L, is a complement of a clock signal used in the lower voltage domain. 
         [0023]    During operation of level shifter circuit  200 , a logic high on the clk_X_L input will activate both pull-down transistors I 12  and I 13 , which are NMOS devices. When these devices are activated, both output nodes of level shifter circuit  200  are pulled down to a reference voltage, VSS in this case. Pulling down the output nodes thus results in a discharge of these nodes. This pre-discharge may be performed before data is input on the input nodes. 
         [0024]    After the pre-discharge operation is complete, data may be input into the input nodes. More particularly, a data signal may be input to the In_H input while a complement of the data signal may be input into the In_X_H input. When the clk_X_L signal falls low, transistors I 12  and I 13  will be de-activated, while transistor I 6  will be activated. When activated, I 6  will pull up one of the output nodes up to VDD/2, depending on the state of the input data. If In_H is a logic low, Out_X_L will be pulled up to VDD/2 (which is equivalent to a logic high in the voltage domain of the output node). Out_L will be pulled up to VDD/2 if In_X_H is a logic low. Thus, the input data is latched through level shifter circuit  200 . 
         [0025]    The combination of pre-discharging the output nodes on the high portion of the input clock cycle and pulling up one of the output nodes on the low portion of the clock cycle may help the “flip” the state of the keeper circuit if the input data state is different than the currently stored data state. Since the pre-discharge and pull-up operations are capable of causing the state of the keeper circuit to change, input circuit transistors I 2 , I 3 , I 10 , and I 11  may be kept relatively small, as they do not need to provide sufficient drive strength to override the state of the keeper circuit. 
         [0026]      FIG. 3  is a timing diagram illustrating the operation of the circuit shown in  FIG. 2 . In the example shown, the In_L input is initially a logic high, while its complement is initially a logic low. Similarly, the Out_L input is initially a logic high, while its complement is initially a logic low. When the clk_X_L signal transitions to a logic high, the Out_L output is pulled down (i.e. discharged) while the Out_X_L output remains a logic low. After the output nodes are pulled down, new data, which represents a change of state, is input into level shifter circuit  200 , as In_H falls low while its complement transitions to a logic high. Out_L remains low, but Out_X_L will attempt to go high, as there may be some contention between the input node and the output node. Once clk_X_L falls low again, Out_X_L will fully transition to a logic high, and thus the newly input data is latched to the outputs. 
         [0027]    A similar process occurs in the example shown on the next clock cycle. When the clk_X_L transitions high again, both output nodes are discharged to a logic low level. New data, in the form of a logic high for In_H and a logic low for its complement is then input into the level shifter circuit, while clk_X_L is high. When the clk_X_L signal falls low again, Out_L is correspondingly pulled up to a logic high state while Out_X_L remains low after having been discharged to that level. 
         [0028]      FIG. 4  is a schematic diagram of an embodiment of a level shifter having a pre-charge circuit. In this particular embodiment, level shifter circuit  400  is configured to transfer data from a lower voltage domain to a higher voltage domain. Furthermore, in this particular embodiment, level shifter circuit  400  is configured to precharge the output nodes, instead of pre-discharging them as is done with the circuit illustrated in  FIG. 2 . 
         [0029]    Level shifter circuit  400  is arranged in a manner similar to the circuit of  FIG. 2 , having both an input circuit and a keeper circuit. However, in level shifter circuit  400 , transistor I 12  and I 13  are pull-up transistors, while pull-down transistor I 6  is coupled to the NMOS devices of the keeper circuit instead of the PMOS devices. Furthermore, transistor I 6  is configured to, when activated, to pull one of the inputs of the cross-coupled inverters down to VDD/2 through a corresponding activated NMOS device. The PMOS devices of the keeper circuit are coupled to VDD, which causes one of the input nodes to be pulled up when a corresponding PMOS device is activated. 
         [0030]    The pull-up transistors and pull-down transistor are activated on opposite phases of a clock cycle provided from the higher voltage domain. When clk_H is in a low state, transistors I 12  and I 13  will be activated, thereby pulling up the output nodes out_H and out_X_H of level shifter circuit  400 . When clk_H is in a high state, transistor I 12  and I 13  will be deactivated, while transistor I 6  is activated. When transistor I 6  is activated, one of the inputs nodes of the cross-coupled inverters will be pulled down to VDD/2, depending on which one of transistor I 4  or I 7  is activated. 
         [0031]      FIG. 5  is a timing diagram illustrating the operation of the circuit shown in  FIG. 4 . Initially in the example shown, clk_H is in the high portion of its cycle, while In_L is a logic high and its complement is a logic low. When clk_H falls low, Out_X_H is pulled high, while Out_H remains high. After clk_H falls low and Out_X_H is pulled high, new data is input into the level shifter in the form of In_L being pulled down to a logic low in the higher voltage domain, with its complement transitioning to a logic high. When clk_H transitions high again, Out_H completes a transition to a logic low, while Out_X_H remains at a logic high after the precharge. 
         [0032]    The data states of the output nodes change again on the next cycle of operation due to changes in the input signals, as In_L transitions high (and thus results in Out_H transitioning high) while In_X_H falls low (with a corresponding fall of Out_X_H to a logic low), in accordance with the described operation of level shifter circuit  400 . 
         [0033]    While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited. Any variations, modifications, additions, and improvements to the embodiments described are possible. These variations, modifications, additions, and improvements may fall within the scope of the inventions as detailed within the following claims.