Abstract:
A light-emitting structure includes an epitaxial structure including a plurality of trenches; a conductive connecting layer, disposed under the epitaxial structure; a first isolation layer; a crossover metal layer, disposed under the first isolation layer and including a plurality of protruding portions protruding into the epitaxial structure through the plurality of trenches; a second isolation layer, disposed under the crossover metal layer; a bonding layer disposed under the second isolation layer; a substrate, disposed under the bonding layer; and an electrode, electrically connected to the conductive connecting layer and disposed adjacent to the epitaxial structure in a cross-sectional view.

Description:
REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation application of U.S. Ser. No. 15/401,850 entitled “LIGHT-EMITTING STRUCTURE”, filed on Jan. 9, 2017, now pending, which is a continuation application of U.S. Ser. No. 14/954,708 entitled “LED ARRAY”, filed on Nov. 30, 2015, now U.S. Pat. No. 9,553,127, which is a divisional application of U.S. Ser. No. 14/330,914, entitled “LED ARRAY”, filed on Jul. 14, 2014, now U.S. Pat. No. 9,202,981, which is a division of U.S. patent application Ser. No. 14/065,330, entitled “LED ARRAY”, filed on Oct. 28, 2013, now U.S. Pat. No. 8,779,449, which is a division of U.S. patent application Ser. No. 13/428,974, entitled “LED ARRAY”, filed on Mar. 23, 2012, now U.S. Pat. No. 8,569,775, which claims the right of priority based on Taiwan patent application Ser. No. 100110029, filed on Mar. 23, 2011, now Pat. No. TW I488331, the entireties of which are incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    The application relates to a light-emitting structure, and more particularly to a light-emitting structure having protrusion portion. 
       DESCRIPTION OF BACKGROUND ART 
       [0003]    Recently, based on the progress of epitaxy process technology, the light-emitting diode(LED) becomes one of the potential solid-state lighting (SSL) source. Due to the limitation of physics mechanism, LEDs can only be driven by DC power source. Thus the regulator circuit, buck circuit, and other electronic devices are necessary for every lighting device using LED as lighting source to convert AC power source into DC power source to drive LED. However, the addition of the regulator circuit, buck circuit, and other electronic device raises the cost of lighting device using LED as lighting source and causes the low AC/DC conversion efficiency and the huge lighting device package also affect the reliability and shorten the lifetime of LED in daily use. 
       SUMMARY OF THE DISCLOSURE 
       [0004]    The present application discloses a light-emitting structure including: an epitaxial structure including a plurality of trenches; a conductive connecting layer, disposed under the epitaxial structure; a first isolation layer; a crossover metal layer, disposed under the first isolation layer and including a plurality of protruding portions protruding into the epitaxial structure through the plurality of trenches; a second isolation layer, disposed under the crossover metal layer; a bonding layer disposed under the second isolation layer; a substrate, disposed under the bonding layer; and an electrode, electrically connected to the conductive connecting layer and disposed adjacent to the epitaxial structure in a cross-sectional view. 
         [0005]    The present application discloses a light-emitting structure including a first epitaxial unit; a second epitaxial unit disposed next to the first epitaxial unit; a crossover metal layer including a first protruding portion laterally overlapping the first epitaxial unit and the second epitaxial unit wherein the first protruding portion is electrically connected with the first epitaxial unit and the second epitaxial unit; a conductive connecting layer disposed below the first epitaxial unit and the second epitaxial unit and surrounding the first protruding portion; and an electrode arranged on the conductive connecting layer. 
         [0006]    The present application discloses a light-emitting structure including a light-emitting unit; a crossover metal layer including a protruding portion laterally overlapping the light-emitting unit, wherein the protruding portion is electrically connected with the light-emitting unit; a conductive connecting layer disposed below the light-emitting and surrounding the protruding portion; and an electrode arranged on the conductive connecting layer; wherein a top surface of the protruding portion contacts a surface of the light-emitting unit or the protruding portion is devoid of passing through the first epitaxial unit. 
         [0007]    The present application discloses an LED array including a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. 
         [0008]    The present application further discloses an LED array including a permanent substrate, a bonding layer on the permanent substrate, a first conductive layer on the bonding layer, a second isolation layer on the first conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, and an epitaxial structure on the conductive connecting layer. 
         [0009]    The present application further discloses an Led array having N light-emitting diode units (N≧3) and the light-emitting diode units are electrically connected with each other by the crossover metal layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIGS. 1A-1I  are the cross sectional views of the LED array in accordance of the first embodiment of present application. 
           [0011]      FIGS. 1A ′- 1 G′ are the top views of the first embodiment of LED array disclosed by present application. 
           [0012]      FIGS. 2A-2I  are the cross sectional views of the second embodiment of LED array disclosed by present application. 
           [0013]      FIGS. 2A ′- 2 G′ are the top views of the second embodiment of LED array disclosed by present application. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0014]    The present application discloses an LED array having N light-emitting diode units (N≧3) comprising a first light-emitting diode unit, a second light-emitting diode unit in sequence to the (N−1) th  light-emitting diode unit and an N th  light-emitting diode unit. The LED array further comprises a first area (I), the second area (II), and the third area (III). The first area (I) comprises the first light-emitting diode unit, the third area (III) comprises the N th  light-emitting diode unit, and the second area (II) locates between the first area (I) and the third area (III) and comprises the second light-emitting diode unit in sequence to the (N−1) th  diode units. 
         [0015]    The first embodiment discloses a first LED array  1  having three light-emitting diode units.  FIGS. 1A to 1I  illustrate the cross sectional views and the  FIGS. 1A ′ to  1 G′ illustrate the top views of the first embodiment of the first LED array  1 . The method for manufacturing the first LED array  1  comprises steps of:
       1. Providing a temporary substrate  11 , and forming an epitaxial structure thereon. The epitaxial structure comprises a first conductive semiconductor layer  12 , an active layer  13 , and a second conductive semiconductor layer  14  as illustrated in  FIGS. 1A and 1A ′.   2. Next, forming multiple trenches  15  by partially etching the epitaxial structure in the first area (I) and the second area (II), and the epitaxial structure not etched forms multiple flat planes  16 , and the epitaxial structure of the third area (III) is not etched as illustrated in  FIGS. 1B and 1B ′.   3. Forming a conductive connecting layer  17  on partial regions of the flat planes  16 , and the area of the flat planes  16  uncovered by the conductive connecting layer  17  forms multiple pathways  18  as illustrated in  FIGS. 1C and 1C ′.   4. Forming a first isolation layer  19  on part of the conductive connecting layer  17 , the multiple pathways  18 , and the side wall of the multiple trenches  15 , while the conductive connecting layer  17  in the third area (III) and part of the conductive connecting layer  17  in the first area (I) are not covered by the first isolation layer  19 . The conductive connecting layer  17  not covered by the first isolation layer  19  in the second area (II) is defined as a conductive region  20  as illustrated in  FIGS. 1D and 1D ′.   5. Forming a crossover metal layer  21  on the first isolation layer  19 , the conductive region  20 , in multiple trenches  15 , and on the conductive connecting layer  17  in the third area (III). A part of the conductive connecting layer  17  in the first area (I) is not covered by the crossover metal layer  21  in order to electrically connect the second conductive layer  23  with the second conductive semiconductor layer  14  in the following steps. The region which is not covered by the crossover metal layer  21  in the second area (II) nearby the conductive region  20  is used for electrical isolation as illustrated in the  FIGS. 1E and 1E ′. Part of the crossover metal layer  21  in the first area (I) extends to multiple trenches  15  and electrically connects to the first conductive semiconductor layer  12 . The crossover metal layer  21  on multiple flat planes  16  and the pathways  18  in the first area (I) is electrically isolated from the second conductive semiconductor layer  14  by the first isolation layer  19 . The crossover metal layer  21  on the conductive region  20  in the second area (II) electrically connects with the second conductive semiconductor layer  14  by the conductive connecting layer  17 . Part of the crossover metal layer  21  in the second area (II) extends to multiple trenches  15  and electrically connects to the first conductive semiconductor layer  12 . The crossover metal layer  21  on multiple flat planes  16  and the pathways  18  in the second area (II) is electrically isolated from the second conductive semiconductor layer  14  by the first isolation layer  19 . The crossover metal layer  21  in the third area (III) is electrically connected with the second conductive semiconductor layer  14  by the conductive connecting layer  17 .   6. Forming a second isolation layer  22  on the crossover metal layer  21  and the region a in the second area (II). But part of the conductive connecting layer  17  in the first area (I) is not covered by the second isolation layer  22  as illustrated in the  FIGS. 1F and 1F ′.   7. Forming the second conductive layer  23  on the second isolation layer  22  and part of the conductive connecting layer  17  as illustrated in the as illustrated in the  FIGS. 1G and 1G ′.   8. Forming a bonding layer  24  on the second conductive layer  23  which is bonded with a permanent substrate  25  by the bonding layer  24  as illustrated in the  FIG. 1H .   9. Removing the temporary substrate  11  to expose the first conductive semiconductor layer  12  and roughening the surface of the first conductive semiconductor layer  12 . Next, etching multiple pathways  18  from the first conductive semiconductor layer  12  until the first isolation layer  19  is revealed in order to form N light-emitting diode units. Among the N light-emitting diode units, the first light-emitting diode unit locates in the first area (I), the second to the (N−1) th  light-emitting diode units locate in the second area (II), and the N th  light-emitting diode unit locates in the third area (III). At last, forming a first electrode layer  27  on the roughed surface of the first conductive semiconductor layer  12  in the N th  light-emitting diode unit. Thus an LED array  1  having N light-emitting diode units electrically connected in serial by the crossover metal layer  21  is formed as illustrated in  FIG. 1I .       
 
         [0025]    The second embodiment discloses a second LED array  2  having three light-emitting diode units.  FIGS. 2A to 2I  illustrate the cross sectional views and the  FIGS. 2A ′ to  2 G′ illustrate the top views of the second embodiment of LED array  2 . The method for manufacturing the second LED array  2  comprises steps of:
       1. Providing a temporary substrate  11 , and forming an epitaxial structure thereon. The epitaxial structure comprises a first conductive semiconductor layer  12 , an active layer  13 , and a second conductive semiconductor layer  14  as illustrated in  FIGS. 2A and 2A ′.   2. Next, forming multiple trenches  15  by partially etching the epitaxial structure in the first area (I), the second area (II), and the third area (III), and the epitaxial structure not etched forms multiple flat planes  16  as illustrated in  FIGS. 2B and 2B ′.   3. Forming a conductive connecting layer  17  on partial regions of the flat planes  16 , and the area of the flat planes  16  uncovered by the conductive connecting layer  17  forms multiple pathways  18  as illustrated in  FIGS. 2C and 2C ′.   4. Forming a first isolation layer  19  on part of the conductive connecting layer  17 , the multiple pathways  18 , and the side wall of the multiple trenches  15 . The conductive connecting layer  17  in the second area (II) and the third area (III) which is not covered by the first isolation layer  19  are defined as a conductive region  20  as illustrated in  FIGS. 2D and 2D ′.   5. Forming a crossover metal layer  21  on the first isolation layer  19 , the conductive region  20 , and in the multiple trenches  15  except those in the third area (III). A part of the first isolation layer  19  in the first area (I) is not covered by the crossover metal layer  21  in order to electrically isolate the first conductive layer  26  from the second conductive semiconductor layer  14  in the following steps. The first isolation layer  19  in multiple trenches  15  and flat planes  16  is not covered by the crossover metal layer  21  in order to electrically isolate the first conductive layer  26  from the second conductive semiconductor layer  14  in the following steps as illustrated in the  FIGS. 2E  and  2 E′. A part of the crossover metal layer  21  in the first area (I) extends to multiple trenches  15  and electrically connects to the first conductive semiconductor layer  12 . The crossover metal layer  21  on multiple flat planes  16  and the pathways  18  in the first area (I) is electrically isolated from the second conductive semiconductor layer  14  by the first isolation layer  19 . The crossover metal layer  21  on the conductive region  20  in the second area (II) electrically connects with the second conductive semiconductor layer  14  by the conductive connecting layer  17 . A part of the crossover metal layer  21  in the second area (II) extends into the multiple trenches  15  and electrically connects to the first conductive semiconductor layer  12 . The crossover metal layer  21  on multiple flat planes  16  and the pathways  18  in the second area (II) is electrically isolated from the second conductive semiconductor layer  14  by the first isolation layer  19 . The crossover metal layer  21  on the conductive region  20  in the third area (III) electrically connects with the second conductive semiconductor layer  14  by the conductive connecting layer  17 . Besides, the region b in the second area (II) and the third area (III) adjacent to the conductive region  20  is not fully covered by the crossover metal layer  21  which is used for electrical isolation.   6. Forming a second isolation layer  22  on the crossover metal layer  21 , the part of the first isolation layer  19  in the first area (I), and on the region b which is not fully covered by the crossover metal layer  21  in the second area (II). The second isolation layer  22  does not cover the inner side of the trenches  15  in the third area (III), the first isolation layer  19  of the multiple flat planes  16 , and the region b which is not fully covered by the crossover metal layer  21  in the third area (III) as illustrated in the  FIGS. 2F and 2F ′.   7. Forming the first conductive layer  26  on the second isolation layer  22 , in the multiple trenches  15  in the third area (III), on the first isolation layer  19  of the flat planes  16 , and the region b which is not fully covered by the crossover metal layer  21  in the third area (III) as illustrated in the  FIGS. 2G and 2G ′.   8. Forming a bonding layer  24  on the first conductive layer  26  which is bonded with a permanent substrate  25  by the bonding layer  24  as illustrated in the  FIG. 2H .   9. Removing the temporary substrate  11  to expose the first conductive semiconductor layer  12  and roughs the surface of the first conductive semiconductor layer  12 . Next, etching multiple pathways  18  form the first conductive semiconductor layer  12  until the first isolation layer  19  is revealed in order to form N light-emitting diode units. Among the N light-emitting diode units, the first light-emitting diode unit locates in the first area (I), the second to the (N−1) th  light-emitting diode units locate in the second area (II), and the N th  light-emitting diode unit locates in the third area (III). Next, etching the first conductive semiconductor layer  12  in the first area (I) without the crossover metal layer  21  until the conductive connecting layer  17  is revealed, and forming a second electrode layer  28  on the conductive connecting layer  17 . Thus an LED array  2  having N light-emitting diode units electrically connected in series by the crossover metal layer  21  is formed as illustrated in  FIG. 2I .       
 
         [0035]    The temporary substrate  11  described in the above first and second embodiments is made of, for example, gallium arsenide (GaAs), gallium phosphide (GaP), sapphire, silicon carbide (SiC), gallium nitride (GaN), or aluminum nitride. The epitaxial structure is made of an III-V group semiconductor material which is the series of aluminum gallium indium phosphide (AlGaInP) or the series of aluminum gallium indium nitride (AlGaInN). The conductive connecting layer  17  comprises indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, aluminum zinc oxide, and zinc tin oxide. The first isolation layer  19  and the second isolation layer  22  can be made of an insulating material comprises silicon dioxide, titanium monoxide, titanium dioxide, trititanium pentoxide, titanium sesquioxide, cerium dioxide, zinc sulfide, and alumina. The first conductive layer  26  and the second conductive layer  23  can be made of silver or aluminum. The bonding layer  24  is an electrically conductive material made of metal or its alloys such as AuSn, PbSn, AuGe, AuBe, AuSi, Sn, In, Au, or PdIn. The permanent substrate  25  is a conductive material such as carbides, metals, metal alloys, metal oxides, metal composites, etc. The crossover metal layer  21  comprises metal, metal alloys, and metal oxides. 
         [0036]    Although the present application has been explained above, it is not the limitation of the range, the sequence in practice, the material in practice, or the method in practice. Any modification or decoration for present application is not detached from the spirit and the range of such.