Abstract:
A communications controller is provided that allows transfer of a large number of frames to each of the channels of an S 0  -type link to be handled simultaneously at a data transfer rate matched to that of the link. The communications controller is connected between a bus associated with at least one host computer and the terminals of a network connected by a time-multiplexed digital link. The communications controller includes a base unit connected to the bus for managing and effecting the transfer of frames for the link, and a peripheral unit connected to the base unit and to the network. The base unit has a first processor of commands for transferring frames from the host to the network and vice versa, the first processor being associated with a frame storage memory; a peripheral part comprising a coupler controlled by second processor for ensuring multiplexing or demultiplexing of the data; and a second processor, in communication with the first, for transferring frames from the frame storage memory to the peripheral part and vice versa.

Description:
FIELD OF THE INVENTION 
     The present invention relates to communications controllers, and particularly to a communications controller for use with an ISDN (integrated services digital network). 
     BACKGROUND OF THE INVENTION 
     Data transmission networks, also called telecommunications networks or communications networks, typically include a plurality of units, generally called data terminal equipment (DTE). The latter are also referred to as terminals or stations. A computer connected to such a network is considered to be a terminal. Terminals communicate with each other via a transmission line. An S 0  -type link, which is defined by Recommendation X431 of the CCITT (Consultative Committee on International Telegraphy and Telephony) is a transmission line that includes two pairs of telephone wires, one being dedicated to sending messages and the other being dedicated to receiving messages. 
     The various terminals of a network send information messages and receive those sent by others. A message is composed of a set of elementary blocks of binary information called frames. Each frame includes a structured array of data including data which defines its beginning and its end, the address of the intended receiving terminal, the address of the sending terminal, the data length, and other useful information. 
     A current technological trend in the field of data transmission networks is the digital transmission of both voice and data over a common infrastructure. This is due essentially to the progressive introduction of digital techniques into the field of telephony. The integrated service digital network (ISDN) has been introduced in response to this trend. 
     The ISDN is now used principally in Europe and more particularly in France. A communications link of the S 0  -type, also called an S 0  interface, is one of the standardized links within ISDN. It is used in particular for communications between computers and terminals. 
     An LS 0  link of this type has a data transfer rate of 288 kbps (144 kbps in each direction, send and receive) and has three separate channels, namely two B-type channels for transmitting data at a rate of 64 kbps and one D-type signalling channel at 16 kbps. The principle of the LS 0  link is time-multiplexing, as defined in the aforementioned Recommendation X431. 
     A computer typically includes at least one processing unit, an input/output processor, a random access memory, and a read only memory associated with the processor, an input/output controller, all of these elements forming a host system. There are commonly several peripherals cooperative with the host system, such as disk memories or input/output peripherals that facilitate communication of data with a user (such as screen terminals, printers, etc.), each of these peripherals being associated with corresponding peripheral controllers. 
     All the component parts listed above (aside from the peripherals) are disposed on a set of boards whose dimensions are standardized. These boards are generally connected to one bus of the parallel type which provides communications between the various processors and data transport between the various boards, as well as providing the electrical power supply thereto. 
     One bus commonly used in present-day practice is called MULTIBUS II, a registered trademark of the Intel Company. The architecture of such a bus is structured around a principal bus of the standardized parallel type according to IEEE 1296 Standard. This principal bus is designated PSB. 
     As computer networks become more common, the number of computer terminals increases accordingly. This has necessitated the development of programmed communications controllers for reducing the load on the computer&#39;s processing unit. Such controllers manage the messages sent by the various terminals to the telecommunications network to which the computer is connected, as well as managing the messages coming from terminals on the network. In current practice, such a communications controller is built around a microprocessor connected to one or more memories, which has a basic program (simpler than that of the central processing unit) containing specialized modules allowing the bus common to the various component elements of the computer and the network transmission line to be managed, and having facilities for constituting message queues (in the memory associated with the microprocessor). This program must also allow a large number of processes to be executed simultaneously and for this purpose must rapidly generate numerous interrupts, which involves high performance mechanisms for changing the microprocessor context, as well as multiple interrupt levels. Such a program, which can be called communications software, is for example the program called CNS used in the products in the Bull S.A. Company&#39;s DN-7XXX series and also in the CNS-A 0  and CNS-A 1  products in the DPS-7000 computer series made by the same company. 
     In the case where the computer has a MULTIBUS II type bus, the communications processor is connected to it. It is disposed on a board connected to the PSB bus through a coprocessor, for example, of the MPC 82309 type (manufactured by the Intel Company) communicating in message mode with the other functional component parts of the computer. 
     Since the S 0  -type interface is still relatively new, a communications controller which both connects to a Multibus II and manages one or more of these interfaces is practically nonexistent. 
     SUMMARY OF THE INVENTION 
     A communications controller is provided for use with at least one host system associated with a bus and a plurality of terminals, connected together through an S 0  -type link, that allows transfer of a large number of frames to each of the channels of the link to be handled simultaneously at a data transfer rate matched to that of the link. The communications controller is connected between a bus with at least one host system and a plurality of terminals of at least one network (RE 1  -RE 2 ) connected together through at least one time-multiplexed digital link comprising a plurality n of data channels managed according to protocols determined and supported by at least one transmission line. The communications controller includes: a base unit connected to the bus, which manages and effects the transfer of frames over all the channels in the link; and a peripheral unit connected to the base unit and to the transmission line, for providing time-multiplexing and demultiplexing of the various data channels, and for transmitting data to the network or receiving data from the network. The base unit includes: a first processor for frame transfer commands to transfer the frames from the host to the network and vice versa, the processor being conneoted to the bus and associated with a first memory for storing the frames before their transfer, and managing the transfer of frames to the various channels assigned thereto; and a second processor in communication with the first, for transferring each of the frames, channel by channel, from the first memory to the peripheral part, then the network, and vice versa, the peripheral part having a coupler for all the channels controlled by the second processor, connected to the transmission line and receiving the data from each frame, buffer by buffer, coming from or going to the first memory, providing multiplexing or demultiplexing of the data upon sending or upon receiving. 
    
    
     DESCRIPTION OF THE DRAWING 
     The invention will be more fully understood from the following detailed description, in conjunction with the accompanying figures, in which: 
     FIG. 1 is a highly simplified block diagram of a computer having the communications controller according to the invention; 
     FIG. 2 is a block diagram of the physical structure of the communication controller according to the invention; 
     FIG. 3 is a block diagram of the peripheral part of the communications controller according to the invention; 
     FIG. 4 is a block diagram of the structure of the program and microprogram assembly of the communications controller according to the invention; 
     FIG. 5a is a simplified flowchart of the operation of a microprogram module assigned to one data channel of the LS 0  link, allowing transfer of frames over this channel; 
     FIG. 5b is a diagram of the simplified structure of the microprogram module whose simplified flowchart is shown in FIG. 5a, 
     FIG. 6 is a block diagram of the mechanism whereby the program and each of the microprograms assigned to each of the channels communicate with each other; 
     FIGS. 7, 8, and 9 are memory map diagrams that illustrate the operation of the communications controller according to the invention when frames are sent or received, i.e. when frames are sent from the computer to the network using the LS 0  communications link and vice versa; 
     FIG. 10 is a time chart illustrating the various successive operations carried out by the communications controller according to the invention when frames are sent; and 
     FIG. 11 is a time chart illustrating the various successive operations carried out by the communications controller according to the invention when frames are received. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     With reference to FIG. 1, a data processing system ORD is connected to a set of k networks of different types, RE 1 , RE 2 , . . . , RE k  by a plurality of k links of different types. The structure of the system ORD is deliberately simplified and includes: the host system HOST constituting its central system; and a network link concentrator CONC managing and effecting the transfer of frames from the host to these networks RE 1 , RE 2 , . . . , RE k  and vice versa. This concentrator CONC is also called the network line concentrator. It should be noted that the concentrator CONC can also connect other hosts than HOST to networks RE 1  to RE k , for example to host HOSTB shown in dashed lines in FIG. 1. 
     The concentrator CONC includes: a central unit SCOM which administers and manages the concentrator CONC. In particular, it loads all the programs and microprograms associated with each of the boards constituting the concentrator CONC into this unit when they are initialized; a bus PSB, preferably of the Multibus II type; a communications controller assembly CCR allowing the concentrator CONC (and hence HOST) to be connected to the various networks RE k . It comprises the communications controller CCS according to the invention allowing it to be connected, in the embodiment described here, to two ISDN networks RE 1  -RE 2  each using an S 0  type communications link. 
     Concentrator CONC is here considered a terminal of the two networks RE 1  -RE 2 , communicating with the other terminals of the two networks RE 1  -RE 2 . 
     The host can be connected either directly to bus PSB through a coprocessor MPC 82309, or through a central communications coupler CCC, particularly in the case where several hosts are connected to the concentrator CONC (CCC is shown in dashed lines in FIG. 1). 
     The frames coming from the host HOST intended for networks RE 1  -RE 2  reach the communications controller CCS through the bus PSB. The communications controller CCS divides each of them into a plurality of data buffers, and manages and transfers this set of frames over the various data channels of the two S 0  type links. These data are time-multiplexed by the controller CCS. The controller CCS thus multiplexes the frames sent by host HOST for both the S 0  type links. From the functional standpoint, it will thus be considered in the remainder of the text that these two S 0  type links behave like a single link having B type channels B and B 2  and D type channels D 1  for the first link, and B type B 3  and B 4  and D type D 2  for the second. To simplify, channels B 1 , B 2 , D 1 , B 3 , B 4 , and D 2  will hereinafter be designated C 1  through C 6 , respectively. 
     With reference to FIGS. 2 and 3, the communications controller CCS according to the invention comprises a base unit BA and a peripheral unit PER as can be seen in FIG. 2. 
     Base unit BA includes: 
     an interface IF 1  with bus PSB, of the Multibus II type, defined by IEEE Standard P 1296, for example composed of MPC 82309 (see above); 
     a first microprocessor MP 1  of the 68030 type made by the Motorola Company, associated with a first random access memory MV 1  with a four megabyte capacity; 
     a second microprocessor MP 2  associated with a second random access memory MV 2  with 512 kilobytes of memory, operating in the master mode; and 
     an interface IF 2  allowing a dialogue between first and second microprocessors MP 1  and MP 2 , allowing physical matching of the signals transiting through internal bus BI 1  of first microprocessor MP 1  with those transiting through internal bus BI 2  of second microprocessor MP 2 . 
     Peripheral unit PER includes: 
     a coupler CO controlled by second microprocessor MP 2  of base unit BA; and 
     a first and a second physical connection device to first network RE 1  and second network RE 2 , respectively, namely ADS 1  and ADS 2 . 
     Coupler CO is in fact composed of two identical couplers CO 1  and CO 2  which, in the embodiment of the communications controller according to the invention, are formed by three serial communications controllers each belonging to the peripheral part of a 68302 microcontroller made by the Motorola Company. (It is known that a 68302 microcontroller is in fact formed by the combination of a 68000 microprocessor and a peripheral part formed of serial communications controllers). Thus, controller CO 2  is formed by the three serial communications controllers SCC 4 , SCC 5 , SCC 6  (see also FIG. 3) of a 68302 microcontroller whose 68000 microprocessor is none other than MP 2 , while controller CO 1  constitutes the peripheral part formed of three serial communications controllers SCC 1 , SCC 2 , SCC 3  of a second 68302 microcontroller whose 68000 microprocessor is not used. 
     As can be seen from FIG. 3, coupler CO 1  is connected to network RE 1 , namely to telephone lines LE 1  and LR 1  through physical connection device ADS 2  formed by transceiver circuit TC and transformer TR. The S 0  type transceiver is a circuit of the MC145474 type made by Motorola. 
     Coupler CO 1  is connected to transceiver TC via an interface known as IDL (interchip data link). 
     An outline of the operation of the communications controller CCS is as follows: 
     First processor MP 1  controls the transfer of the frames sent by the host HOST intended for either of networks RE 1  or RE 2  ; thus, it receives the frames from bus PSB and stores them in its random access memory MV 1  while they are being actually transferred to either of the two aforesaid networks. Conversely, it receives in its random access memory MV 1  the frames coming from either of these two networks before sending them via bus PSB to the host HOST. The first processor divides each of the frames into a plurality of buffers such as BF 1 , BF 2 , . . . , BF n . MP 1  assigns a totally random physical location to each of them in random access memory MV 1 . As soon as one of data channels C 1  to C 6  (see above) is available, the first processor asks the second processor MP 2  to transfer the frame in question from the random access memory MV 1  to the coupler CO 1  and then to the network RE 1  or RE z  through the internal buses BI 1 , BI 2  and the interface IF 2  in the appropriate channel, for example C 1 . It is clear that the first processor MP 1  proceeds in the same way with each of the frames, for each of the channels C 1  to C 6 . In other words, the first processor MP 1  manages transfer of each of the frames it receives from the PSB or from one of the two networks RE 1  -RE 2  through the various channels C 1  to C 6  assigned to each one, for both sending and receiving. It is clear that, in receiving, physical locations in MV 1  are assigned, also randomly by MP 1 , to the various buffers BF 116 , BF 12 , . . . , BF m  of each frame, these locations being different from those assigned to BF 1 . . . BF n . When sending, second processor MP 2 , having received the transfer request from the first processor MP 1 , transfers the frame in question, buffer by buffer, over the channel assigned to this frame, from the first memory MV 1  to the peripheral part PER. 
     When receiving, MP 2  transfers the frame coming from one of the two networks RE 1  -RE 2  in the appropriate channel, buffer by buffer, from the peripheral part to MV 1 . 
     The peripheral part PER, for example via first coupler CO 1 , looks for the buffers of the frame in question in MV 1  and transfers them to network RE 1  or RE 2  through the serial communications controller SCC 1  associated with the channel assigned to the frame sent. When receiving, MP 2  transfers, buffer by buffer, in the appropriate channel, from the peripheral part to MV 1 . In the preferred embodiment of the invention described here, serial communications controller SCC 1  can manage a maximum of 8 buffers simultaneously both when sending and when receiving. This controller receives the buffers in parallel if they are coming from memory MV 1  or serially if they are coming from network RE 1  -RE 2 . It serializes or deserializes them as the case may be. Coupler CO 1  multiplexes or demultiplexes the data received by the various serial communications controllers SCC 1  to SCC 6 . In fact, coupler CO 1  can receive several frames simultaneously at each of its controllers, or more precisely several sets of buffers corresponding to several frames. 
     First and second processors MP 1  and MP 2  carry out their work on instructions from a communications program CNS (see above) and a microprogram AML, respectively. 
     When communications controller CCS is switched on, communications program CNS and microprogram AML which are stored in disk memories MD of concentrator CONC, are loaded into each of random access memories MV 1  and MV 2 , respectively. This loading is done through bus PSB. Of course, this loading takes place once the board corresponding to communications controller CCS has been initialized. This initialization is done under the control of a microprogram stored in a PROM-type programmable memory installed in base unit BA and not shown in FIG. 1 or FIG. 2 for simplicity&#39;s sake. 
     The communications software is in fact the operating system of communications controller CCS. This software organizes the link between host HOST and microprogram AML which is more specifically responsible for transferring each of the frames to channels C 1  to C 6 . 
     We will now consider FIG. 4 which shows very schematically the links between the communications program CNS and the microprogram AML. 
     The microprogram AML has a nucleus NY, a communications interface IC for dialogues between communications program CNS and microprogram AML, as well as a plurality of microprogram modules, also called tasks, namely TC 0 , TC 1 , TC 2 , . . . , TC 7 . Microprogram modules TC 1  through TC 6  each correspond to channels C 1  through C 6  defined above. They are thus responsible for transferring the frames assigned to each of these channels from memory MV 1  to peripheral part PER and vice versa. Tasks TC 0  and TC 7  are specific to the board containing controller CCS. Thus, task TC 7  serves to configure ISDN channels C 1  to C 6 . This means that instead of, for example, using each of the two 64 kbps channels C 1  and C 2  handled respectively by SCC 1  and SCC 2 , it may be desirable to use only one 128 kbps channel C 1  +C 2  handled by the controller SCC 1  aIone, BCC 2  then being inactive. TC 7   is thus responsible for implementing such a configuration if necessary. The role of TC 6  will be explained below. 
     Each task corresponding to a channel is a task independent of the others. The sequence of tasks is organized in real time by nucleus NY. 
     Microprogram AML, which receives its commands from the communications software installed in memory MV 1 , is seen by this software as a set of 8 independent tasks. Nonetheless, tasks TC 0  to TC 7  can function simultaneously under the command of the nucleus NY. Each of these tasks hence has direct links with the nucleus NY but none with the others. 
     The microprogram module IC manages the interface with program CNS. It deals with the requests coming from the latter and switches them to the various tasks corresponding to the various channels so that they can be executed. Symmetrically, it is responsible for transferring states or data coming from the channels corresponding to each of the tasks intended for the CNS program. 
     Exchanges between base unit BA and peripheral unit PER are defined by command descriptors. A command descriptor corresponds to a given frame and defines the operations that must be accomplished on this frame (see below). 
     The command descriptors occupy, in memory MV 1 , random locations determined by communications program CNS. The physical addresses of these locations and the corresponding locations themselves are not released until the frames associated with these command descriptors have been released (have been sent in full in the case of a send or received in full in case of a receive). Thus, a command descriptor COM1 corresponds to a frame TR 1  (see FIG. 6), a command descriptor corresponds to a frame TR 2 , a command descriptor COM 3  corresponds to a frame TR 3 , etc. 
     For a given channel C 1  to C 6 , the command descriptors are chained through chaining pointers. In other words, command descriptor COM 1  is chained to descriptor COM 2  by a chaining pointer PC 1 , command descriptor COM 2  is chained to command descriptor COM 3  by a chaining pointer PC 2 . A chaining pointer is none other than the logic address occupied by the command descriptor following the descriptor containing the chaining pointer. Thus, chaining pointer PC 1  indicates the logic address of command descriptor COM 2  and chaining pointer PC 2  indicates the logic address of command descriptor COM 3 , etc. 
     It is known that a frame is composed of a plurality of data packets or buffers. In the embodiment described here, each buffer has a maximum of 200 8-bit bytes. For example, frame TR 1  has (see also FIG. 6) buffers BF 1 , BF 2 , . . . , BF n . Likewise, frame TR 1  is composed of buffers BF 11  to BF m . Each buffer is associated with a specific physical location in memory defined by a buffer descriptor. Thus, buffer descriptors DB 1  to DB n  correspond to buffers BF 1  to BF n . Likewise, buffer descriptors DB 11  to DB m  correspond to buffers BF 11  to BF m . Of course, the buffer descriptors occupy different physical locations in the memory MV 1  where they are located than the buffers with which they are associated. Thus, DB 1  occupies a different location in memory than buffer BF 1 , etc. 
     Moreover, by misuse of language, the individual skilled in the art assigns the same name to the buffers as to the physical locations assigned to them in memory MV 1 .Thus, for example, BF 1  designates both a buffer or data packet and the physical location where it is stored in memory MV 1 . Container and content thus have the same designation, and this applies also to the command descriptors and buffer descriptors. 
     Each command descriptor has a pointer to the descriptor of the first physical buffer corresponding to the first data packet of the frame. Thus, command descriptor COM 1  contains pointer PB 1  defining the address of buffer descriptor DB 1 , namely the address of the physical location occupied by this descriptor in memory MV 1 . Likewise, command descriptor COM 2  contains pointer PB 2  defining the physical location of buffer descriptor DB 11 . 
     Each buffer descriptor contains a pointer to the following buffer descriptor. Thus, buffer descriptor DB1 contains pointer PCB 1  defining the address, i.e., the physical location occupied by buffer descriptor DB 2 . This pointer is designated PCB 1 . 
     In conclusion, a command descriptor such as COM 1  to COM 3 , includes: 
     a chaining pointer to another command descriptor such as PC 1 , PC 2 , etc. This pointer is adapted to be used by communications interface IC and is at the head of the descriptor; 
     a pointer to the descriptor of the first physical buffer, such as PB 1 , PB 2 , etc.; 
     a total byte count of the useful data in the physical buffer chain, in other words the total number of bytes contained in the frame formed by buffer chain BF 1 , BF 2  to BF n , or BF 11  to BF m , etc.; 
     an index indicating the actual start of the data in the first physical buffer, i.e. for example the physical address of the beginning of the data in first physical buffer BF 1  in memory MV 1  ; 
     an indicator showing whether the command is an immediate command. The immediate commands are commands that do not involve the use of data packets designed to be transferred to the network or coming therefrom. These immediate commands can for example be a command to activate a channel with a view to receiving or a command to deactivate this same channel on reception, as soon as a frame has been fully received and transmitted to the CPU; 
     a status field indicating the result of executing the command, i.e. whether or not the command has been correctly executed; and 
     a command bit field including the command code; there are several types of commands which will be defined below, to which a particular code corresponds. 
     Other than the immediate commands (channel activation on reception and channel deactivation) defined above, there are two other types of commands, namely a data send command and a purge command relative to data sending when, for some reason or another, sending over a channel must be stopped. This purge command is an immediate command. 
     The format of the command descriptors is defined when the board carrying communications controller CCS is initialized and is defined by task TC 0 , namely the microprogram module corresponding to channel C 0 . Once this format has been defined upon initialization of communications controller CCS, the command descriptor format is immutable. 
     The format of the buffer descriptors such as DB 1  to DB n  or DB 11  to DB m  is defined by communications program CNS. It includes: 
     a chaining pointer to the next buffer descriptor, for example, chaining pointer PCB 1 . This pointer is a logic address that defines the memory location of the corresponding buffer descriptor, namely DB 2  ; and 
     a start index defining the physical location occupied in memory by the start of buffer BF 1 . Likewise, buffer descriptor DB 2  contains a start index defining the start of the physical location occupied in memory by buffer BF 2 . 
     A start index is obtained as follows: 
     The address defining the physical location occupied in memory MV 1  by buffer BF 2 , for example, (the same reasoning applies to the other buffers), which can also be defined as the physical address of buffer BF 2 , is obtained by adding to the logical address defined by pointer PBF 2  of this same buffer contained in the associated descriptor DB 2 , a logical magnitude Δ 1 . Thus, if I 2  is the start index of BF 2 , one can write I 2  =PBF 2  +Δ 1  : 
     the index defining the end of the physical location occupied by the corresponding physical buffer. Hence, DB 1  contains the index defining the physical location of the end of buffer BF 1  ; 
     the total size in number of bytes of the corresponding buffer. DB 1  thus contains the total number of data bytes contained in buffer BF 1 . 
     Just as in the case of the command descriptors and the buffer descriptors, any logic address is also a physical address. 
     First memory MV 1  also contains several memory zones operating according to the FIFO memory principle. These memory zones are defined by communications program CNS. MV 1  in fact contains three FIFO memory zones, namely FG, FREC, and FREP. Each of these FIFO memory zones contains a certain number p of elements. Each element contains the address of a command descriptor and the channel number corresponding to the command defined by this descriptor. The CNS program, for each FIFO memory zone, thus defines the address of the start of this memory zone, the index of the head element, namely the address of the head element, the index of the tail element, namely the address of the tail element, as well as the number of elements contained in this FIFO memory zone. Thus, for example, FIFO memory zone FG contains the p elements E 1 , E 2 , E 3 , . . . , E p  (see FIG. 8). Thus, the CNS program defines the address of the start DEB of FIFO zone FG, the index of head element E 1 , the index of tail element E p , and the number of elements p. The same obviously also applies to FIFO memory zones FREC and FREP which contain the same number of elements p. Element E 1  thus contains the address of command descriptor COM 1  as well as the channel corresponding to the command defined by this descriptor, for example channel C 1 . Element E 2  contains the address of command descriptor COM 2  and the address of the corresponding channel, in this case C 1  (see above). Element E 3  contains the address of command descriptor COM 3  and the corresponding channel, namely C 1 , . . . , and so forth for elements E 3  to E p . 
     Second memory MV 2  also contains, in addition to the set of microprograms defined above, a number of FIFO memory zones, equal in number to the number of data channels, namely C 1  to C 6 . Hence it contains 6 FIFO memory zones, namely FC 1 , FC 2 , . . . , FC 6  (see FIG. 8). 
     Each FIFO, FC 1  through FC 6 , contains the addresses of the command descriptors corresponding to the associated channel as well as the number of this channel. Thus, FIFO FC 1  contains the address of command descriptor COM 1  and the channel number corresponding to this command descriptor, i.e. channel C 1 , as well as the address of COM 2  and channel number C 1 , etc. 
     The information contained in each of FIFOs FC 1  to FC 6 , which information is defined above, is transferred thereto from FIFO memory FG of MV 1  under the conditions described below, in conjunction with the operation of communications controller CCS according to the invention. Moreover, the information contained in each of FIFOs FC 1  to FC 6  is transferred to serial communications controllers SCC 1  to SCC 6  under the conditions to be defined below. 
     With reference to FIGS. 5 and 6, FIG. 5 is a simplified flowchart of operations OP 1  through OP 5  implemented when each of tasks TC 1  to TC is executed. Operation OP 1  is an operation initializing the task effected by nucleus NY. Operation OP 2  which follows operation OP 1  allows each of the procedures that can be implemented by task TC 1  (TC 1  to TC 6 ) to be established, i.e. either a frame send procedure or a frame receive procedure or a procedure to activate or deactivate the corresponding channel. In this operation, the task will look for the addresses of the procedures for handling either the CNS program commands upon a send request or the addresses of the procedures handling the actions triggered by a processor MP 1  interrupt, when it is necessary to receive a frame from network RE 1  -RE 2 . 
     Upon operation OP 3 , the task waits for an event. This event can be either a CNS program command, for example when the program wants to send a frame to the network, or a microprocessor MP 2  interrupt for reception of a frame from the network. In the first case (CNS program command) one is dealing with event EV 0 . In the second case, one is dealing with event EV1 The way in which events EVe or EV1 occur is shown in detail below in the description associated with FIGS. 6, 7, 8, 9, 10, and 11. 
     Once either of operations OP 4  or OP 5  is terminated, operation OP 3  is returned to. 
     Memory MV 2  also contains a description table TDT describing each task TC 1  to TC 6 . This description table is created dynamically each time one of tasks TC 1  to TC 6  is launched, i.e. it is established whenever nucleus NY calls on one of tasks TC 1  to TC 6  TDT includes the following four major parts: 
     Part PRCH: this part defines the protocol used on the channel. It will be remembered that a communications protocol is composed of the access rules to the various terminals in a network, which rules govern dialogues between the terminals. A protocol sequences conversation between these terminals without hierarchizing it. Various types of protocols are known. The protocol in widest use is the HDLC protocol (high level data link control) standardized according to CCICC Recommendation X25, Yellow Book, Vol. XIII.2, November 80 and according to international standards defined by the International Standardization Organization (ISO) under the following designations: IS3309-2, IS4335, IS6159 and 6258. This HDLC protocol is more specifically used in networks RE 1  and RE 2 . 
     Part CEV 0  : this part contains the addresses of the procedures handling event EV 0 . It is created when procedure-establishing operation OP 2  occurs. 
     Part CEV 1  : this part contains the addresses of the procedures handling event EV 1 . It is created when operation OP 2  occurs. 
     Part PCA: this part contains the information necessary for task TC 1  for managing the buffers in a frame: it contains in particular the number of buffers that each of the serial communications controllers can send without interruption--eight in the embodiment described here. 
     Each serial communications controller SCC 1  to SCC 6  has buffer descriptors in the same number as the maximum number of buffers that can be sent without interruption, namely eight. Thus, serial communications controller SCC 1  has buffer descriptors DBC 1 , DBC 2  to DBC 8 . The same applies to the other serial communications controllers SCC 2  to SCC 6 . 
     Each of buffer descriptors DBC 1  to DBC 8  has the addresses of the buffer descriptors contained in MV 1  corresponding to the command descriptor which is handled by the task of the corresponding channel, namely TC 1  Buffer descriptor DBC 1  thus contains the address of the buffer descriptor DB 1  corresponding to command descriptor COM 1 , whose command is executed by task TC 1  associated with channel C 1 . Moreover, the first command descriptor of serial communications controller SCC 2  contains the address of the first buffer descriptor corresponding to the command descriptor whose command is handled by the task TC 2  corresponding to channel C 2 . 
     Each of the buffer descriptors of the various serial communications controllers also contains the number of bytes in the corresponding buffer. Thus, buffer descriptor DBC 1  contains the number of information bytes contained in buffer BF 1 . 
     The data contained in each buffer of memory MV 1  are transmitted, with each send, over line LE 1  (or LE 2 ) under the control of SCC 1  for channel C 1 , SCC 2  for C 2 , etc. 
     The functioning of communications controller CCS will be better understood in the light of the explanations furnished below in relation to FIGS. 6 through 11. 
     We will thus consider an event EV 0  and assume that it is desired to send from CCS a frame TR 1  composed of 10 buffers BF 1  to BF 10 , and that this frame is sent by communications controller C 1 , thanks to task TC 1 . Sending of the frame includes the following successive phases: 
     First Phase PH 1   
     First processor MP 1  prepares, under the instructions of communications program CNS, starting at time t 0  (FIG. 10), command descriptor COM 1 . The information contained in this command descriptor will occupy in memory MV 1  a physical location prepared for the purpose by the CNS program when the board containing communications controller according to the invention CCS is initialized. Thus, as stated above, to this command descriptor COM 1  there corresponds a plurality of buffer descriptors DB 1  to DB1e to which buffers BF 1  to BF 10  correspond. The buffer descriptors are thus prepared by first processor MP 1 . (The physical locations reserved for the buffer descriptors are prepared in the same way as the physical locations of the command descriptions when CCS is initialized.) Moreover, the bytes corresponding to the ten buffers in frame TR 1  are stored in each of the physical locations corresponding to buffers BF 1  to BF 10 . As soon as buffer descriptors DB 1  to DB 10  corresponding to command descriptor COM 1  are prepared, phase PH 2  ensues. 
     Phase PH 2   
     The CNS program puts into FIFO FG, in first element E 1 , the address of command descriptor COM 1  as well as the corresponding channel number, in this case the number of channel C 1 , namely one, for example. Once element E 1  is filled with this information, first processor MP sends an interrupt ITREQ to second processor MP 2 , at time t 1 . As far as the sending of frame TR 1  is concerned, communications program CNS has finished its job for the time being. Phase PH 3  then ensues. 
     Phase PH 3   
     In this phase, the instructions executed by processor MP 2  are those of communications interface IC. As soon as interrupt ITREQ has been received by MP 2 , microprocessor MP 2  transfers the information contained in element E 1  of FIFO FG to FIFO FC 1 . It is clear that the information contained in FIFO FG of MV 1  corresponding to command descriptors associated with any of channels C 1  to C 6  can be transferred from FIFO FG of MV 1  to any of the six MV 2  FIFOs. Indeed, processor MP 1 , under the control of the CNS program, can prepare several frames TR 2 , TR 3 , etc. simultaneously, with their associated command descriptors and buffer descriptors. Moreover, for a given channel, for example for channel C 1  (but it is obvious that the same applies to the others) several command descriptor addresses can be transferred simultaneously, as can the corresponding channel number in FIFO FC 1  corresponding to this channel C 1 . As soon as this information has been transferred to FIFOs FC 1  to FC 6 , phase PH 4  ensues. 
     Phase PH 4   
     Communications interface IC alerts corresponding task TC 1 . The instructions will then be carried out by second processor MP 2 , under the instructions of TC 1 . Task TC 1  will look for the address of command descriptor COM 1  in FC 1 , then analyze the command descriptor itself in memory MV 1  to examine the nature of the command, e.g., send or receive, or immediate or nonimmediate command. Task TC 1  finds in this command descriptor the address of buffer descriptor DB 1 , and looks in this buffer descriptor for the address of corresponding buffer BF 1 . It then places the address of the latter in buffer descriptor DBC 1  of SCC 1  It also places there the number of bytes corresponding to buffer BF 1 , which it finds in descriptor DB 1 . The task thus continues looking for the addresses of buffers BF 2  to BF 6  in buffer descriptors DB 2  to DB 6  and transfers this information to buffer descriptors DBC 2  to DBC 6  of SCC 1 . When DBC 6  is full, task TC 1  makes an interrupt request DITDMA of processor MP 1  (this interrupt request, which takes place once the sixth buffer descriptor is full, is provided in the microprogram corresponding to this task. It is arbitrary that the interrupt request takes place after the sixth buffer descriptor is full, and so the interrupt request could also take place after the fifth buffer descriptor is full, for example. Thus, it is clear that this interrupt request could take place after any other buffer descriptor of SCC 1  was full). 
     Although interrupt request DITDMA has taken place, task TC 1  continues to fill DBC 7  and DBC 8 . Since interrupt request DITDMA took place at time t 2 , as soon as DBC 8  is full, second processor MP 2 , under the control of TC 1  instructions, sends SCC 1  a send request DMAEM at time t 3 . Phase PH 5  then ensues. 
     Phase PH 5   
     SCC 1  looks for buffers BF 1  to BF 8  in MV 1  and sends them to network RE 1  -RE 2 . When sixth buffer BF 6  has all been sent, the interrupt corresponding to interrupt request DITDMA is sent, and is called ITDMA. It is sent at time t 4 . Starting at this time, while SCC 1  continues to send seventh and eighth buffers BF 7  and BF 8 , task TC 1  fills buffer descriptors DBC 1  and DBC 2  of SCC 1  with the addresses of buffers BF 9  and BF 10  which it finds in buffer descriptors DB 9  and DB 10  and with the corresponding number of bytes. When buffer descriptor DBC 2  has been filled in this way, task TC 1  requests an end-of-frame interrupt DITFIN at time t 5 . When last buffer BF 10  has been sent, then second processor MP 2  sends an end-of-send interrupt designated ITFIN, at time t n . Phase PH 6  then ensues. 
     Phase PH 6   
     Immediately after end-of-send interrupt ITFIN, task TC 1  sends the contents of FIFO FC 1 , namely the address of command descriptor COM 1  plus the corresponding channel number C 1 , to FIFO FREP of MV 1   In parallel, the task sends the send status of the frame to command descriptor COM 1  contained in MV 1 . Indeed, in the command descriptor there is a location provided for the purpose, and this location is empty at the beginning, namely at the time the CNS program is preparing COM 1  (see phase PH 1 ). 
     Once this is done, task TC 1  sends to first processor MP 1  a signal indicating that transmission of frame TR 1  is complete, this signal being called CPUREQ and being sent at time t n+1 . Phase PH 7  then ensues. 
     Phase PH 7   
     Task TC 1  then looks in FC 1  to see whether there is an address of another command descriptor and the corresponding channel number. If there is, phase PH 1  ensues for sending another frame, TR 2  for example. If there is not, operation OP 3  ensues, i.e. task TC 1  is placed in the event waiting position. 
     It is clear that the other tasks TC 2  to TC 6  can operate in parallel with task TC 1 . 
     We will now consider event EV 1  and assume that controller CCS receives a frame TR 11 , containing 10 buffers BF 11  to BF 20 , from network RE 1  -RE 2 .We will also assume that microprocessor MP 1 , on instruction from the CNS program, allows activation of channel C 1  in the receive mode. Reception of frame TR 11  proceeds according to the following successive phases: 
     Phase PH 11  (starting at time T 0 ) 
     The task corresponding to channel C 1 , namely TC 1 , has just assigned itself a free location in memory MV 1  for a command descriptor, then a free location for a buffer descriptor, and places in the command descriptor occupying this free location, which is designated COM 11 , the address of the physical location occupied by the first buffer descriptor, designated DB 11 , then assigns itself a total of eight buffer descriptors, namely DB 11  (already named) to DB 18 . Task TC 1  chains these buffer descriptors together in the same way as DB 1 , DB 2 , etc. were chained together. Task TC 1  also assigns itself eight buffers, each corresponding to the buffer descriptor, namely BF 11  to BF 18 . It will then place the addresses of each of buffers BF 11  to BF 18  in the eight buffer descriptors DBC 11  to DBC 18  of SCC 1 , with an interrupt request DITDMA 1  (time T 1 ) when the address of buffer BF 16  is written in buffer descriptor DBC 6 . When the buffer addresses are Written in all the buffer descriptors of SCC 1 , task TC 1  indicates to SCC 1  by interrupt PR (time T 2 ) that it is ready to receive frame TR 11 . The next phase PH 12  then ensues. 
     Phase pH 12   
     The information received from network RE 1  -RE 2  is transferred directly to the physical locations of buffers BF 11  to BF 18  as long as there are no end-of-frame interrupts sent by the terminal sending over the network, said end-of-frame interrupt being decoded by SCC 1 . When sixth buffer BF 16  corresponding to buffer descriptor DBC 6  has been filled, an interrupt ITDMA 1  is sent (time T 3 ). Buffer descriptors DBC 11  to DBC 16  are then reinitialized, and made to correspond to six new physical empty-buffer locations BF 19  to BF 24  in MV 1 . 
     Phase PH 13  then ensues. 
     Phase PH 13   
     During reception of the tenth buffer (BF 20 ), end-of-frame interrupt ITFTR occurs (time Tn). Task TC 1  places in command descriptor COM 11  the status of the frame received, i.e. indicates whether this frame was correctly received and whether or not it contains errors, as well as the total number of bytes it contains. The next phase PH 14  then ensues. 
     Phase PH 14   
     Task TC 1  places in FIFO FREC of first memory MV 1  the address of command descriptor COM 11  as well as the number of the channel corresponding to this descriptor, i.e., 1. Phase PH 15  then ensues. 
     Phase PH 15   
     Task TC 1  releases the buffer descriptors of serial communications controller SCC which are unused (BF 21  to BF 24 ) and which had been prepared following interrupt ITDMA 1 . As soon as they are released, processor MP 2  sends an interrupt CPUREQ to the first processor at time T n+1 , which signifies that the entire frame TR 11  has been transferred to the MV 1  buffers. Frame TR 11  is then at the disposal of the CNS program. 
     Other modifications and implementations will occur to those skilled in the art without departing from the spirit and the scope of the invention as claimed. Accordingly, the above description is not intended to limit the invention except as indicated in the following claims.