Abstract:
A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor memory device, particularly to a dynamic random access memory capable of performing refresh operation independently of input signals received from external sources (which will hereinbelow be referred to as a “complete-hidden-refresh-function-included DRAM”).  
           [0003]    2. Description of the Background Art  
           [0004]    In a field of portable terminals such as portable telephones, there is widely used an asynchronous general-purpose static random access memory (which will hereinbelow referred to as “SRAM”) for which external clocks need not be supplied. In the SRAM, since refresh operation need not be performed, complex control need not be performed. For example, the SRAM need not perform control access that is made to the memory in refresh operation by awaiting completion of a refresh cycle. In view of the above, the SRAMs are suitable for use with the portable terminals.  
           [0005]    Recently, since a portable terminal handles images, the function thereof has been significantly improved, and the portable terminal requires large scale memory functions. However, the SRAM has memory which is about 10 times that of a dynamic random access memory (which hereinbelow will be referred to as a “DRAM”). For a large-scale SRAM, the cost for the memory chip is significantly increased, and consequently, the price of the portable terminal is increased. To cope with the problem, a technical scheme has been conceived in which, instead of the SRAM, a DRAM of which memory cost per unit bit is lower is used with the portable terminal.  
           [0006]    However, the DRAM requires complex memory control relative to refresh operation. For portable-terminal manufacturers that hitherto have been engaged in design of systems using SRAMs as memories, it is not easy to use DRAMs as substitutive memories of SRAMs.  
           [0007]    Under these circumstances, many semiconductor manufacturers have begun the development of a new semiconductor memory device. The new memory device is formed of a DRAM, but it operates as a SRAM in terms of external functions. The new semiconductor memory device is introduced in “Kazuhiro Sawada, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.23, No.1, February 1998, (pp.12-19)”. Hereinbelow, the new semiconductor memory device is referred to as a “complete-hidden-refresh-function-included DRAM”.  
           [0008]    In the complete-hidden-refresh-function-included DRAM, the same memory cells as those used in the DRAM are used. On the other hand, external interfaces, such as control signals and address signals to be input to the complete-hidden-refresh-function-included DRAM, are the same as those to be input to the SRAM. However, different from refresh operation or self-refresh operation of the conventional DRAM, refresh operation of the complete-hidden-refresh-function-included DRAM is not controlled by signals externally supplied. In specific, the refresh operation is controlled by a refresh command signal /REFE that is cyclically output from a refresh circuit provided in the complete-hidden-refresh-function-included DRAM. The refresh circuit includes a ring oscillator as a timer circuit, and outputs refresh command signal /REFE in response to a cycle signal /Refcyc that is cyclically output from the timer circuit.  
           [0009]    [0009]FIG. 13 is a timing chart representing a case where refresh operation is executed in a conventional complete-hidden-refresh-function-included DRAM.  
           [0010]    In FIG. 13, a timer circuit in the complete-hidden-refresh-function-included DRAM cyclically activates cycle signal /Refcyc, and also activates refresh command signal /REFE in response to the activation of cycle signal /Refcyc. Thereby, the complete-hidden-refresh-function-included DRAM cyclically executes refresh operation either in an operation state where either read operation or write operation for data is readily executable or in a standby state where the data is retained.  
           [0011]    As described above, however, the complete-hidden-refresh-function-included DRAM executes refresh operation independently of input signals externally supplied. This causes a problem in that although attempt is made to perform testing for evaluation of refresh characteristics, the testing cannot be performed for observation and evaluation of refresh characteristics.  
         SUMMARY OF THE INVENTION  
         [0012]    An object of the present invention is to provide a semiconductor memory device including a complete hidden refresh function that enables testing to be performed for observation and evaluation of refresh characteristics.  
           [0013]    A semiconductor memory device of the present invention allows testing to be performed and includes a memory cell array including a plurality of memory cells arranged in a matrix, input-terminal group through which external signals are input, and a complete hidden refresh circuit capable of performing refreshing operation without being externally commanded for data stored in the plurality of memory cells. A function of the complete hidden refresh circuit is invalidated in response to a signal input through the input terminal group.  
           [0014]    Preferably, the complete hidden refresh circuit includes a refresh circuit for outputting a refresh command signal for commanding execution of the refresh operation, a control circuit for executing the refresh operation in response to the refresh command signal, in which the function of the refresh circuit is invalidated in response to a signal output from the input terminal group.  
           [0015]    In this case, the refresh operation can be forcedly terminated according to an externally input signal, and refresh characteristic evaluation testing can thereby be performed.  
           [0016]    In addition, the refresh circuit preferably includes a timer circuit for outputting a cycle signal at a time interval required to refresh the data stored in the plurality of memory cells, a command-signal activating circuit for activating the refresh command signal in response to the cycle signal, a determination circuit for determining as to whether or not the refresh command signal activated needs to be output.  
           [0017]    Furthermore, a function of the timer circuit is preferably invalidated in response to a signal input from the input terminal group.  
           [0018]    In this case, the refresh operation can be terminated by invalidating the cycle signal that is output from the timer circuit, and the refresh characteristic evaluation testing can therefore be performed.  
           [0019]    Still furthermore, a function of the command-signal activating circuit is preferably invalidated in response to a signal input through the input terminal group.  
           [0020]    Because of the above arrangement, the command-signal activating circuit is disabled to activate the refresh command signal, and consequently, the refresh operation terminates. Thereby, the refresh characteristic evaluation testing can be performed.  
           [0021]    Still furthermore, a function of the determination circuit is preferably invalidated in response to a signal input through the input terminal group.  
           [0022]    In this case, the refresh operation can be terminated by invalidating a determination signal that is output from the determination circuit, and the refresh characteristic evaluation testing can thereby be performed.  
           [0023]    According to the present invention described above, in the complete-hidden-refresh-function-included DRAM, an external signal is used to terminate the complete-hidden-refresh-function-included DRAM, thereby enabling refresh characteristic evaluation testing to be implemented.  
           [0024]    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    [0025]FIG. 1 is an overall configuration view of a complete-hidden-refresh-function-included DRAM according to a first embodiment of the present invention;  
         [0026]    [0026]FIG. 2 is an example circuit diagram of a refresh-stop-mode control circuit shown in FIG. 1;  
         [0027]    [0027]FIG. 3 is another example circuit diagram of refresh-stop-mode control circuit shown in FIG. 1;  
         [0028]    [0028]FIG. 4 is a timing chart representing operation of refresh-stop-mode control circuit shown in FIG. 3;  
         [0029]    [0029]FIG. 5 is a circuit diagram of a refresh circuit shown in FIG. 1;  
         [0030]    [0030]FIG. 6 is a circuit diagram of a command-signal activating circuit shown in FIG. 5;  
         [0031]    [0031]FIG. 7 is a circuit diagram of a determination circuit shown in FIG. 5;  
         [0032]    [0032]FIG. 8 is a timing chart representing operation of refresh circuit;  
         [0033]    [0033]FIG. 9 is a circuit diagram of a refresh circuit according to a second embodiment of the present invention;  
         [0034]    [0034]FIG. 10 is a timing chart representing operation of refresh circuit;  
         [0035]    [0035]FIG. 11 is a circuit diagram of a refresh circuit according to a third embodiment of the present invention;  
         [0036]    [0036]FIG. 12 is a timing chart representing operation of refresh circuit; and  
         [0037]    [0037]FIG. 13 is a timing chart in a case where refresh operation is executed in a conventional complete-hidden-refresh-function-included DRAM. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0038]    Hereinbelow, embodiments will be described in detail referring to the drawings. In the drawings, portions identical to or equivalent to each other are represented by identical numerals or symbols, and description of the portions will not be repeated.  
         [0039]    [First Embodiment] 
         [0040]    [0040]FIG. 1 is an overall configuration view of a complete-hidden-refresh-function-included DRAM according to the first embodiment of the present invention.  
         [0041]    Referring to FIG. 1, a complete-hidden-refresh-function-included DRAM  1  includes an input terminal group  10 , a terminal group  11 , a terminal group  12 , an input terminal group  15 , an input terminal group  16 , a power terminal  13 , and a ground terminal  14 . Input terminal group  10  receives control signals, namely, a chip enable signal /CE, an output enable signal /OE, a write enable signal /WE, a control signal /LB, and a control signal /UB. Terminal group  11  inputs data signals DQ 0  to DQ 7  and/or outputs them. Terminal group  12  inputs data signals DQ 8  to DQ 15  and/or outputs the same. Input terminal group  15  inputs address signals AO to A m  (“m” represents “1” or a larger natural number). Input terminal group  16  inputs address signals A m+1  to A n  (“n” represents “1” or a larger natural number). Power terminal  13  receives a power-supply voltage VCC. Ground terminal  14  is given a ground voltage GND.  
         [0042]    Chip enable signal /CE controls complete-hidden-refresh-function-included DRAM to be active. Output enable signal /OE sets complete-hidden-refresh-function-included DRAM to a read mode, and concurrently activates an output buffer. Write enable signal /WE sets complete-hidden-refresh-function-included DRAM  1  to a write mode. Control signal /LB selects the operation of inputting data to input terminal group  11  on a lower bit side and/or outputting data therefrom. Control signal /UB selects the operation of inputting data to input terminal group  12  on an upper bit side and/or outputting data therefrom.  
         [0043]    Complete-hidden-refresh-function-included DRAM further includes a control circuit  20 , a column address buffer  21 , and a row address buffer  22 . In response to the control signals that have been input from input terminal group  11 , control circuit  20  outputs to individual blocks control clocks corresponding to predetermined operation modes, such as the write mode and the read mode, of the complete-hidden-refresh-function-included DRAM. In response to outputs of control circuit  20 , column address buffer  21  receives address signals AO to Am and transfers them to the inside. In response to outputs of control circuit  20 , column address buffer  22  receives address signals A m+i  to A n  and transfers them to the inside.  
         [0044]    Complete-hidden-refresh-function-included DRAM further includes a column decoder  23 , a row decoder  24 , a memory cell array  26 , and a sense-amplifier-and-input/output-controller circuit  25 . In response to outputs of control circuit  20 , column decoder  23  receives internal address signals that have been output from column address buffer  21 , and specifies column addresses. In response to outputs of control circuit  20 , row address buffer  24  receives internal address signals that have been output from column address buffer  22 , and specifies row addresses. Memory cell array  26  includes memory cells arranged in a matrix. Sense-amplifier-and-input/output-controller circuit  25  amplifies outputs from memory cell array  26 , and performs read operation.  
         [0045]    Complete-hidden-refresh-function-included DRAM further includes a lower input buffer  27 , a lower output buffer  28 , an upper input buffer  29 , and an upper output buffer  30 . In response to outputs of control circuit  20 , the lower input buffer  27  receives data signals DQ 0  to DQ 7  from terminal group  11 , and transfers them to sense-amplifier-and-input/output-controller circuit  25 . In response to outputs of control circuit  20 , lower output buffer  28  receives signals from sense-amplifier-and-input/output-controller circuit  25 , and outputs data signals to terminal group  11 . In response to outputs of control circuit  20 , upper input buffer  29  receives data signals DQ 8  to DQ 15  from terminal group  12 , and transfers them to sense-amplifier-and-input/output-controller circuit  25 . In response to outputs of control circuit  20 , upper output buffer  30  receives signals from sense-amplifier-and-input/output-controller circuit  25 , and outputs data signals to terminal-group  12 .  
         [0046]    Complete-hidden-refresh-function-included DRAM further includes a refresh circuit  40 . Refresh circuit  40  outputs to control circuit  20  a signal that is cyclically activated, namely, a refresh command signal /REFE, to control circuit  20 . Upon receipt of refresh command signal /REFE, control circuit  20  outputs operation command signals to individual blocks for execution of refresh operation.  
         [0047]    Complete-hidden-refresh-function-included DRAM further includes a refresh-stop-mode control circuit  80 . Refresh-stop-mode control circuit  80  outputs a stop signal /RefSTOP to refresh circuit  40  in response to at least one of external signals that have been input to input terminal groups  10 ,  15 , and  16 .  
         [0048]    As shown in FIG. 2, refresh-stop-mode control circuit  80  may be formed of, for example, a buffer  81 , to output stop signal /RefSTOP in response to an external stop signal ext./RefSTOP that is input from an input terminal  150  which is one of input terminal groups  10 ,  15 , and  16 .  
         [0049]    Alternatively, as shown in FIG. 3, refresh-stop-mode control circuit  80  may be configured such that it inputs chip enable signal /CE and address signals A 0  to An, and outputs stop signal /RefSTOP in response to a combination thereof. For example, as shown in a timing chart of FIG. 4, during four cycles of chip enable signal /CE, address signal A 0  is controlled to be at a voltage level (SuperVIH level) which is higher than a normal level, and “all-H-level” and “all-L-level” are alternately applied in units of the cycle of chip enable signal /CE to thereby activate stop signal /RefSTOP.  
         [0050]    Hereinbelow, refresh circuit  40  will be described.  
         [0051]    [0051]FIG. 5 is a circuit diagram of refresh circuit  40  shown in FIG. 1.  
         [0052]    Referring to FIG. 5, refresh circuit  40  includes a command-signal activating circuit  50 , a determination circuit  60 , NAND gates  41  and  44 , an inverter  42 , a buffer  48 , delay circuits  43  and  49 , and a flip-flop  45 .  
         [0053]    Command-signal activating circuit  50  outputs a refresh flag signal Refflag that activates refresh command signal /REFE. Determination circuit  60  outputs a determination signal Refwin that determines as to whether or not refresh command signal /REFE activated by refresh flag signal Refflag needs to be output.  
         [0054]    NAND gate  41  receives refresh flag signal Refflag and determination signal Refwin and performs operations to generate a logical product of these signals. As a result, it outputs a signal obtained through inversion of the operation result as a signal /REFSF.  
         [0055]    Inverter  42  receives signal /REFSF, which has been output from NAND gate  41 , and reverses it. A delay circuit  43  receives signal /REFSF, and delays it by a specific period of time.  
         [0056]    NAND gate  44  receives an output signal of inverter  42  and an output signal of delay circuit  43 , and performs operations to generate a logical product of these signals. As a result, it outputs a signal obtained through inversion of the operation result as a signal /REFS.  
         [0057]    Flip-flop  45  is formed to include NAND gates  46  and  47 . NAND gate  46  receives signal /REFS and an output signal φA 3 , which has been output from NAND gate  47 , and performs operations to generate a logical product of these signals. As a result, it outputs a signal φA 2  obtained through inversion of the operation result. NAND gate  47  receives an output signal φA 2 , which has been output from NAND gate  46 , and a signal φA 4  output from delay circuit  49 , and performs operations to generate a logical product of these signals. As a result, it outputs a signal obtained through inversion of the operation result as a refresh command signal /REFE.  
         [0058]    Delay circuit  49  receives refresh command signal /REFE, which has been output from flip-flop  45 , and outputs signal φA 4  delayed by a specific period of time.  
         [0059]    Buffer  48  receives output signal φA 3  and outputs refresh command signal /REFE.  
         [0060]    [0060]FIG. 6 is a circuit diagram of command-signal activating circuit  50  shown in FIG. 5.  
         [0061]    Referring to FIG. 6, command-signal activating circuit  50  includes a timer circuit  51  that is formed of a ring oscillator and that outputs a cycle signal /Refcyc cyclically activated, a flip-flop  52 , inverters  56  and  57 , a delay circuit  58 , and an AND gate  59 .  
         [0062]    AND gate  59  receives cycle signal /Refcyc and stop signal /RefSTOP output from refresh-stop-mode control circuit  80 , and performs operations to generate a logical product of these signals, and outputs the operation result as a signal +A 0 .  
         [0063]    Flip-flop  52  is formed of NAND gates  53  and  54 . NAND gate  53  receives signal φA 0  and an output signal φA 11  of NAND gate  54 , performs operations to generate a logical product of these signals, and outputs a signal φA 10  through inversion of the operation result. NAND gate  54  receives output signal φA 10 , which has been output from NAND gate  53 . It also receives an output signal φA 12 , which has been output from a NAND gate  55 . Then, it performs operations to generate a logical product of output signal φA 10  and output signal φA 12 , and outputs output signal φA 11  obtained through inversion of the operation result.  
         [0064]    Inverter  56  receives output signal φA 11 , which has been output from flip-flop  52 , inverts it, and outputs the inverted signal as refresh flag signal Refflag.  
         [0065]    Inverter  57  receives refresh command signal /REFE and inverts it. Delay circuit  58  receives refresh command signal /REFE, which has been inverted by inverter  57 , and outputs a signal φA 13  obtained such that the inverted refresh command signal /REFE is delayed by a specific period of time.  
         [0066]    NAND gate  55  receives refresh command signal /REFE and signal φA 13 , which has been output from delay circuit  58 , performs operations to obtain a logical product of these signals, and outputs output signal φA 12 , which has been obtained through inversion of the operation result.  
         [0067]    [0067]FIG. 7 is a circuit diagram of determination circuit  60  shown in FIG. 5.  
         [0068]    Referring to FIG. 7, determination circuit  60  is formed of a buffer circuit  61 . Buffer circuit  61  receives an internal chip enable signal int/CE, and outputs determination signal Refwin. Control circuit  20 , after receiving chip enable signal /CE from input terminal group  10 , generates internal chip enable signal int/CE.  
         [0069]    Hereinbelow, operation of refresh circuit  40  having the above-described circuit configuration will be described.  
         [0070]    [0070]FIG. 8 is a timing chart representing operation of refresh circuit  40 .  
         [0071]    Referring to FIG. 8, when chip enable signal /CE input from input terminal group  10  is inactive, determination circuit  60  determines that refresh operation is executable. That is, determination circuit  60  determines that refresh circuit  40  has been enabled to output refresh command signal /REFE. Consequently, determination signal Refwin that is output from determination circuit  60  becomes active.  
         [0072]    A cycle signal /Refcyc that is output from timer circuit  51  is activated at a time t 1 . At this time, since stop signal /RefSTOP that is output from refresh-stop-mode control circuit  80  is inactive, refresh flag signal Refflag that is output from command-signal activating circuit  50  is activated.  
         [0073]    Consequently, NAND gate  41  in refresh circuit  40  receives determination signal Refwin and activated refresh flag signal Refflag, and activates signal /REFSF. NAND gate  44  receives activated signal /REFSF, and outputs signal /REFS activated within the specific period of time set by delay circuit  43 .  
         [0074]    Flip-flop  45  receives activated signal /REFS, and outputs output signal φA 3  activated within the specific period of time set by delay circuit  49 . Buffer  48  receives output signal φA 3 , and outputs refresh command signal /REFE activated within a specific period of time from time t 1 .  
         [0075]    As a result of the above-described operations, when refresh flag signal Refflag output from command-signal activating circuit  50  is activated at time t 1 , determination circuit  60  determines that refresh operation is executable. That is, at time t 1 , the determination circuit  60  determines that determination signal Refwin is active. Thereby, when complete-hidden-refresh-function-included DRAM  1  is in a standby state, refresh operation is executable.  
         [0076]    Refresh command signal /REFE that is output from refresh circuit  40  is deactivated at a time t 2 , which is a time point after passage of a specific period of time set by delay circuit  49 . At this time, since the level of output signal φA 12  that is output from NAND gate  55  in command-signal activating circuit  50  is shifted to an L level, refresh flag signal Refflag that is output from the command-signal activating circuit  50  is deactivated accordingly.  
         [0077]    Subsequently, at a time t 2 ′, chip enable signal /CE becomes active. In this case, determination circuit  60  determines that refresh operation is not executable, and therefore deactivates determination signal Refwin that is output therefrom.  
         [0078]    At a time t 3 , when cycle signal /Refcyc, which is cyclically activated, is activated, refresh flag signal Refflag that is output from command-signal activating circuit  50  is also activated.  
         [0079]    However, since determination signal Refwin that is output from determination circuit  60  remains inactive, signal /REFS that is output from NAND gate  44  also remains inactive. Consequently, refresh command signal /REFE that is output from refresh circuit  40  remains inactive.  
         [0080]    Since refresh command signal /REFE remains inactive, output signal +A 12  that is output from NAND gate  55  in command-signal activating circuit  50  is at an H level. Accordingly, output signal φA 11  that is output from flip-flop  52  remains at the L level. Consequently, refresh flag signal Refflag that is output from command-signal activating circuit  50  becomes active at time t 3  and thereafter.  
         [0081]    As described above, within a period for which chip enable signal /CE is active, determination circuit  60  determines that refresh operation is not to be executed. When refresh flag signal Refflag that is be output from command-signal activating circuit  50  to activate refresh command signal /REFE is activated within the period for which determination circuit  60  determines that refresh operation is not to be executed, the refresh flag signal Refflag remains active.  
         [0082]    Subsequently, chip enable signal /CE is deactivated at a time t 4 , and complete-hidden-refresh-function-included DRAM thereby enters a standby state. In this case, determination circuit  60  determines that refresh operation is executable, and consequently, determination signal Refwin that is output from determination circuit  60  is activated.  
         [0083]    In the above stage, since refresh flag signal Refflag is activated at time t 3  and thereafter, signal /REFS that is output from NAND gate  44  in refresh circuit  40  is activated at time t 4 , and is held active within the specific period of time set by delay circuit  43 . Consequently, refresh command signal /REFE that is output from refresh circuit  40  is held active within the specific period of time set by delay circuit  49 .  
         [0084]    At a time t 5 , which is a time point after passage of the specific period of time set by delay circuit  49  from time t 4 , refresh command signal /REFE is deactivated. In addition, in response to the deactivation of refresh command signal /REFE, refresh flag signal Refflag is also deactivated.  
         [0085]    Also at and after time t 5 , when refresh flag signal Refflag is activated within a period in which determination circuit  60  determines that refresh operation is executable, refresh circuit  40  activates refresh command signal /REFE in response to refresh flag signal Refflag.  
         [0086]    As a result of the above-described operations, in complete-hidden-refresh-function-included DRAM of the first embodiment, refresh operation is executed also in the standby state.  
         [0087]    Hereinbelow, a description will be made regarding a case where refresh characteristic testing is executed in complete-hidden-refresh-function-included DRAM of the first embodiment.  
         [0088]    At a time t 6  in FIG. 8, stop signal /RefSTOP that is output from refresh-stop-mode control circuit  80  becomes active. Subsequently, at a time t 7 , when cycle signal /Refcyc that is output from timer circuit  51  is activated, stop signal /RefSTOP is active. Consequently, the level of signal φA 0  that is output from AND gate  59  in command-signal activating circuit  50  becomes an L level. Consequently, refresh flag signal Refflag that is output from command-signal activating circuit  50  is not activated.  
         [0089]    According to the above operations, when stop signal /RefSTOP is activated at time t 6 , refresh command signal /REFE that is output from refresh circuit  40  becomes inactive at time t 6  and thereafter.  
         [0090]    Because of the above, when stop signal /RefSTOP is activated in response to an externally input signal, refresh cycle signal /Refcyc is invalidated. Refresh command signal /REFE is not therefore activated, and consequently, the refresh operation terminates. Thereby, the refresh operation is controlled to also terminate in complete-hidden-refresh-function-included DRAM. This enables refresh-characteristic evaluation testing to be implemented.  
         [0091]    [Second Embodiment] 
         [0092]    In the first embodiment, the refresh operation is terminated in the manner in which the externally input signal is used to thereby invalidate cycle signal /Refcyc. Refresh operation can similarly be terminated in another manner. In this manner, refresh flag signal Refflag that is output from command-signal activating circuit  50  is invalidated to terminate the refresh operation.  
         [0093]    [0093]FIG. 9 is a circuit diagram of a refresh circuit  90  according to the second embodiment of the present invention.  
         [0094]    Compared to refresh circuit  40  shown in FIG. 5, in a refresh circuit  90  referring to FIG. 9, an AND gate  91  is connected between command-signal activating circuit  50  and NAND gate  41 .  
         [0095]    AND gate  91  receives stop signal /RefSTOP and refresh flag signal Refflag output from command-signal activating circuit  50 , performs operations to generate a logical product of these signals, and outputs the operation result as a signal φA 91 .  
         [0096]    Other units in the circuit configuration are the same as those shown in FIG. 5. They are not therefore described to avoid repetition.  
         [0097]    Hereinbelow, a description will be given regarding operation of refresh circuit  90  that has the above-described circuit configuration.  
         [0098]    [0098]FIG. 10 is a timing chart representing operation of refresh circuit  90 .  
         [0099]    Referring to FIG. 10, operations within the period from times t 1  to t 5  are the same as those shown in FIG. 8. They are not therefore described to avoid repetition.  
         [0100]    At time t 6 , stop signal /RefSTOP that has been input from the outside of refresh circuit  90  becomes active. The method for activating stop signal /RefSTOP is the same as that in the first embodiment.  
         [0101]    When cycle signal /Refcyc that is output from timer circuit  51  is activated at a time t 7 , a refresh flag signal Refflag also becomes active in response to the activation of cycle signal /Refcyc. However, since signal φA 91  that is output from AND gate  91  while stop signal /RefSTOP is active becomes at an L level, signal /REFSF that is output from NAND gate  41  remains inactive. Consequently, signal /REFS that is output from NAND gate  44  is not activated, and refresh command signal /REFE remains inactive.  
         [0102]    In specific, although refresh flag signal Refflag is activated at time t 6  and thereafter in response to the activation of stop signal /RefSTOP at time t 6 , AND gate  91  invalidates refresh flag signal Refflag, and consequently, refresh command signal /REFE remains inactive. Thereby, at time t 6  and thereafter, refresh operation is terminated in complete-hidden-refresh-function-included DRAM.  
         [0103]    As described above, the refresh operation can be terminated also in the way in which a signal is externally input to thereby invalidate refresh flag signal Refflag that is output from command-signal activating circuit  50 .  
         [0104]    [Third Embodiment] 
         [0105]    In addition to the ways described above, in refresh circuit  40  in complete-hidden-refresh-function-included DRAM, the refresh operation can be terminated also by invalidating determination signal Refwin that is output from determination circuit  60 .  
         [0106]    [0106]FIG. 11 is a circuit diagram of a refresh circuit  100  according to the third embodiment of the present invention.  
         [0107]    Compared to refresh circuit  40  shown in FIG. 5, in refresh circuit  100  referring to FIG. 11, an AND gate  101  is connected between determination circuit  60  and NAND gate  41 .  
         [0108]    AND gate  101  receives stop signal /RefSTOP, which has been output from refresh-stop-mode control circuit  80 . Also, it receives determination signal Refwin, which has been output from command-signal activating circuit  50 , performs operations to generate a logical product of stop signal /RefSTOP and determination signal Refwin, and outputs the operation result as a signal φA 101 . Other units in the circuit configuration are the same as those shown in FIG. 5, and descriptions thereof are not therefore given to avoid repetition.  
         [0109]    Hereinbelow, operation of refresh circuit  100  will be described.  
         [0110]    [0110]FIG. 12 is a timing chart representing operation of refresh circuit  100 .  
         [0111]    Referring to FIG. 12, operations within the period from times t 1  to t 5  are substantially the same as those shown in FIG. 8. They are not therefore described to avoid repetition.  
         [0112]    When stop signal /RefSTOP that has been input from the outside of refresh circuit  100  becomes active at time  6 , and cycle signal /Refcyc that is output from timer circuit  51  is activated at time t 7 , a refresh flag signal Refflag also becomes active in response to the activation of cycle signal /Refcyc. On the other hand, since chip enable signal /CE is inactive, determination signal Refwin is activate. However, since stop signal /RefSTOP is active, the level of signal φA  101  that is output from refresh circuit  100  becomes an L level. In this case, since signal /REFSF that is output from NAND gate  41  remains inactive, signal /REFS that is output from NAND gate  44  is not activated. Consequently, refresh command signal /REFE remains inactive.  
         [0113]    In specific, in response to the activation of stop signal /RefSTOP at time t 6 , determination signal Refwin is invalidated, and consequently, refresh operation is terminated.  
         [0114]    As described above, the refresh operation can be terminated also in the way in which a signal is externally input to thereby invalidate determination signal Refwin. This enables testing to be performed by terminating the refresh operation.  
         [0115]    As above, in the first to third embodiments, description has been made in the respective configurations where stop signal /RefSTOP, that has been activated in response to the external signals is used to invalidate cycle signal /Refcyc, refresh flag signal Refflag, and determination signal Refwin. However, stop signal /RefSTOP may be used either to invalidate two of the aforementioned three signals, namely, cycle signal /Refcyc, refresh flag signal Refflag, and determination signal Refwin, or to invalidate all the signals. In addition, the above-described embodiments may be combined.  
         [0116]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.