Abstract:
The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This invention was made with government support under Contract No. F19628-00-C-0002 awarded by the Air Force. The government has certain rights in the invention. 

   STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH 
   Not Applicable. 
   FIELD OF THE INVENTION 
   The present invention relates generally to Charge Coupled Devices (CCDs) and in particular to an apparatus for subtracting or adding charge to charge packets in a CCD. 
   BACKGROUND OF THE INVENTION 
   Charge-Coupled Devices (CCDs) provide a basic function of storing and moving isolated packets of charge. Various operations can be performed on the packets: they can be added (merged), split into two or more pieces, conditionally steered, destructively or non-destructively sensed, etc. These operations make it possible to design CCD-based circuits to perform various discrete-time analog signal processing operations, with signals represented as charge packets or differential charge-packet pairs. 
   One operation that has proved difficult to implement, however, is subtraction. Various methods have been proposed for subtracting one charge packet from another, or removing a fixed or controllable charge from a packet. All of these methods suffer from various accuracy problems such as non-linearity and noise, or from slow operating speed. 
   SUMMARY OF THE INVENTION 
   The present invention provides a method and apparatus for adding charge to or subtracting charge from a charge packet in a Charge-Coupled Device (CCD). The method and apparatus utilize a CCD structure which includes elements to perform the addition or subtraction of charge during the charge packet&#39;s traversal across the device. The amount of charge to be added or subtracted is controlled by a voltage extrinsic to the CCD itself and is coupled into a CCD charge stream by a capacitor which in one embodiment is separate from the CCD. 
   The disclosed method has several advantages over the prior art: (1) it is very linear with respect to the subtracted or added value; (2) it can be made very linear with respect to the starting charge packet (from which subtraction occurs); (3) it operates at the same speed as the CCD in which it is embedded; (4) it introduces relatively little noise, and (5) it can transfer charge from one CCD segment to a non-adjacent CCD segment during the subtraction/addition process. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a schematic diagram of a prior-art charge coupled device (CCD); 
       FIG. 2  is a schematic of a CCD; 
       FIGS. 2A–2G  are a series of diagrams which illustrate the potentials and charge packets under various gates at different times during operation of a CCD of the type shown in  FIG. 1 ; 
       FIGS. 3A–3D  are a series of timing diagrams which illustrate how four control signals (clock voltages) vary with time over one full clock cycle to produce the CCD operation shown in  FIG. 2 ; 
       FIG. 4  is a schematic diagram of a CCD; 
       FIGS. 5A–5G  illustrate the potentials and charge packets under various gates of the CCD shown in  FIG. 4  at different times during a charge-subtraction operation; 
       FIGS. 6A–6G  are a series of timing diagrams which illustrate control (clock voltage) signals used to produce the CCD charge-subtraction operation shown in  FIG. 5 ; 
       FIG. 7  is a schematic diagram of a CCD; 
       FIGS. 8A–8G  illustrate the potentials and charge packets under various gates of the CCD shown in  FIG. 7  at different times during a charge-subtraction operation; 
       FIG. 9  is a schematic diagram of a charge subtraction device having a Faraday shield; and 
       FIGS. 10A–10G  illustrate the potentials and charge packets under various gates of the charge subtraction device shown in  FIG. 9  at different times during a charge-subtraction operation. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Charge Coupled Devices (CCDs) are well-known devices with a wide variety of scientific and commercial applications, such as image sensors in digital still cameras and video cameras. CCDs comprise linear shift registers formed by a series of Metal-Oxide-Semiconductor (MOS) gates resident on the surface of a semiconductor substrate. Clock voltages applied to the gates result in the formation of localized potential wells and barriers in the semiconductor substrate under the gates. Charge packets are confined in these potential wells by the potential barriers and are shifted along the surface of the substrate under the influence of appropriate clock voltage waveforms applied to the gates. Thus CCDs fundamentally provide the functions of storage and shifting of signals represented as charge packets. 
   Basic operation of a conventional CCD is explained with reference to  FIGS. 1 ,  2 , and  3 . In this discussion, a device of the type sometimes referred to as a “four-phase” CCD is used to illustrate device structures and operation. In this CCD type, each stage of the CCD has four gates, two used to create storage wells and two used to create barriers. Other CCD types, such as two-phase and three-phase, are also common. The four-phase type illustrated is convenient for explaining basic CCD operation as well as the operation of the present invention. The present invention is, however, applicable to any of these other types as well. Throughout this discussion it is further assumed that the charge packets being processed are made up of electrons. Hole-based CCDs are also possible, although unusual in practice. 
   Referring now to  FIG. 1 , a schematic representation of part of a prior art CCD is shown for explanation purposes only. In this example, a total of nine gates are shown, comprising two complete four-phase CCD stages plus one additional gate. Storage gates  2 ,  4 ,  6  and  8  are represented as long heavy horizontal lines; barrier gates  1 ,  3 ,  5 ,  7  and  9  are represented as shorter heavy horizontal lines. Gates  1 ,  2 ,  3  and  4  comprise the first CCD stage  20 ; gates  5 ,  6 ,  7  and  8  comprise the second stage  22 ; and gate  9  is the first barrier gate of a third stage  24 . Additional CCD stages are assumed to extend to the right and left of the stages shown. Each of the four gates comprising one stage of the device is connected to a separate clock voltage, identified as P 1 , P 2 , P 3  and P 4 . The same four clocks are re-used in each stage. 
     FIG. 3  is a timing diagram showing how the four clock voltages P 1  through P 4  vary with time over one full clock cycle. Seven instants t 0  through t 6  are identified. Time t 6  is the beginning of the next clock cycle, equivalent to time t 0 . These seven times are discussed in detail with reference to  FIGS. 5A–5G . 
   Referring now to  FIG. 2 , the schematic CCD representation from  FIG. 1  is repeated at the top for reference. The seven diagrams below this schematic represent potentials and charge quantities under each gate at seven successive instants during the operating cycle of the device. In these diagrams the potential and charge-quantity representation is of a type common in CCD literature. A low potential indicates a region attractive to charge (a “well”), and a high potential indicates a region that repels or excludes charge (a “barrier”). When two adjacent regions have differing potentials, any charge present flows to the region of lowest available potential. Because the charge packets consist of electrons, which are negatively charged, a higher (more positive) gate voltage produces a lower (more attractive) potential, and a lower gate voltage produces a higher (more repulsive) potential. The presence of charge under a gate raises the potential there (because it tends to repel similar charge). This effect is shown as shading in the diagrams; lack of shading indicates absence of charge. Vertical arrows in each diagram indicate changes of potential from the previous diagram. Horizontal arrows indicate charge movement. 
   The seven instants illustrated in  FIG. 2  are identified as t 0 , t 1  . . . t 6 . As will be seen, the overall effect of one full cycle of operation of the illustrated device is to shift a charge packet from one stage to the next stage of the CCD. The process of moving or coupling the charge from one gate to the next gives rise to the name “charge-coupled device”. 
   Initially, at time t 0 , clock voltage P 2  is high, forming wells under storage gates  2  and  6 , while clock voltages P 1 , P 3 , and P 4  are low, forming barriers under barrier gates  1 ,  3 ,  5 ,  7  and  9  and making storage gates  4  and  8  unattractive to charge. Charge packets  11  and  12  are held in the wells under storage gates  2  and  6  respectively, and prevented from moving by the barriers under gates  1  and  3 , and  5  and  7  respectively. 
   At time t 1 , clock voltage P 1  is made lower, raising the barriers under gates  1 ,  5 , and  9 . At approximately the same time, clock voltage P 3  is made somewhat higher, lowering the barriers under gates  3  and  7 . These barriers are still high enough, however, to continue the confinement of charge packets  11  and  12  under gates  2  and  6 . Also at approximately the same time, clock voltage P 4  is made high, so that wells form under storage gates  4  and  8 . No charge is yet able to flow into these wells, however. Changes in potential from time t 0  are indicated by arrows. 
   At time t 2 , clock voltage P 2  is lowered, thus raising the potentials under gates  2  and  6 , and consequently the potentials of charge packets  11  and  12 . When the potentials of these charge packets become high enough, the charge is able to flow over the lowered barriers under gates  3  and  7 , into the wells under storage gates  4  and  8  respectively. The higher barriers under gates  1  and  5  prevent charge flow in the reverse direction. Arrows in the figure indicate the direction of charge flow. 
   At time t 3 , clock voltage P 2  has reached its minimum value, and the flow of charge ceases, with packets  11  and  12  fully transferred to gates  4  and  8 . Note that the potentials and charges at this stage are similar to those at t 0 , except that the pattern is shifted two gates to the right. Thus a charge transfer by one-half of a full (four-gate) CCD stage has occurred. 
   At time t 4 , clock voltage P 3  is made lower, raising the barriers under gates  3  and  7 . At approximately the same time, clock voltage P 1  is made somewhat higher, lowering the barriers under gates  1 ,  5  and  9 . These barriers are still high enough, however, to continue the confinement of charge packets  111  and  12  under gates  4  and  8 . Also at approximately the same time, clock voltage P 2  is made high, so that wells form under storage gates  2  and  6 . No charge is yet able to flow into these wells. 
   At time t 5 , clock voltage P 4  is lowered, thus raising the potentials under gates  4  and  8 , and consequently the potentials of charge packets  11  and  12 . When the potentials of these charge packets become high enough the charge is able to flow over the lowered barriers under gates  5  and  9 . Charge packet  11  flows into the well under gate  6 ; charge packet  12  flows out of the figure, into the first storage well of the next stage. At the same time, a new charge packet,  13 , flows from the previous stage (not shown) into the well under gate  2 . The higher barriers under gates  3  and  7  prevent charge flow in the reverse direction. 
   At time t 6 , clock voltage P 4  has reached its minimum value, and the flow of charge ceases, with packets  11 ,  12  and  13  fully transferred. Note that the potentials at this time are identical to those at t 0 . The charge packets, however, have been shifted four gates to the right. Thus a charge transfer by one full CCD stage has occurred. t 6  is cyclically equivalent to t 0 ; further charge transfers occur as this cycle repeats. All the charge packets move across the device simultaneously. At all times a well containing a charge is bounded by barriers at each side in order to properly store the charge and maintain the integrity of the charge. While a right shifting operation has been described, the charges can be moved in a left shifting operation as well, simply by interchanging the timing of barrier clock voltages P 1  and P 3 . 
   Basic operation of a prior-art four-phase CCD shift register has been explained thus far, with the aid of  FIGS. 1 ,  2 , and  3 . In certain instances it may be desirable to subtract or add an amount of charge to a charge packet being transported in a CCD. The present invention provides this additional capability. The operation of charge subtraction is explained with reference to  FIGS. 4 ,  5 , and  6 . 
   Referring now to  FIG. 4 , a charge-subtraction device  100  includes barrier gates  101 ,  103 ,  105 ,  109 ,  111  and  113 ; storage gates  102 ,  110  and  112 ; and diffused regions  104 ,  106  and  108 . The drawing conventions used in  FIG. 4  are the same as those used in  FIG. 1 , with three additional features: diffused regions  104 ,  106 , and  108 ; a capacitor  114  (not part of the CCD itself); and a path  107  coupling diffused regions  104  and  108 . Path  107  may be comprised of metal or other material capable of providing an ohmic contact between the two diffused regions  104  and  108 . It is sometime referred to in the following text as a “wire.” 
   Diffused regions  104 ,  106 , and  108  are regions of opposite conductivity type to the device substrate, similar to the source/drain diffusions of ordinary MOSFETs. They are referred to hereafter as “diffusions.” A diffusion can be regarded as a source or sink for charge, having essentially unlimited quantities of charge carriers available. The potential of charge in the diffusion is related to the electrical voltage of an electrode connected to the diffusion, and may be set by external connection or by charge flows within a CCD. With electrons as charge carriers, a more positive electrode voltage corresponds to a more negative diffusion potential. Note that because of the connection through wire  107 , the potential of diffusions  104  and  108  are always equal. Any tendency towards imbalance is corrected by current flow through wire  107 . 
   Gates  101 ,  102 ,  103 , and  110  comprise the four gates of an ordinary four-phase CCD stage, as described with reference to  FIG. 1 ; these gates are driven by clock voltages P 1 , P 2 , P 3 , and P 4  respectively. Note, however, that whereas in a conventional CCD gates  103  and  110  would be adjacent, in the present circuit there are additional structures disposed between them. Gates  111 ,  112 , and  113  constitute the first three gates of an ordinary CCD stage (which continues to the right of the diagram), with the same clock voltages as gates  101 ,  102 , and  103 . Additional CCD stages are assumed to continue to the right and left of the region illustrated in  FIG. 4 . Barrier gate  105  is clocked by voltage P 5 , and barrier gate  109  is clocked by voltage P 6 . Capacitor  114  is driven by clock voltage P 7 . These three clock voltages differ from the basic CCD clock voltages shown in  FIGS. 1 ,  2 , and  3 , and will be described in detail below. Diffusion  106  is connected to a DC bias voltage V 1 . 
   In a CCD, charge flow is between adjacent gates, so the elements of a CCD must occupy contiguous portions of the semiconductor substrate. In contrast, the device shown has two sections (on the left, from gate  101  through diffusion  106 ; and on the right, from diffusion  108  through gate  113 ) which can be located on separate areas of the substrate. These sections are separable because charge flow between them occurs by ordinary conduction via wire  107 , rather than by CCD-type charge transfer. 
     FIGS. 6A–6G  are timing diagrams showing how the seven clock signals P 1  through P 7  (e.g. clock voltage) vary with time over one full clock cycle. The clock signals P 1 , P 2 , P 3  and P 4  are as shown in  FIG. 3 . Clock signal P 7  is similar in timing to signal P 4 , but with different maximum and minimum values (e.g. different maximum and minimum voltage values). Likewise, signals P 5  and P 6  are similar in timing to signals P 1  and P 3  respectively, but with different maximum and minimum values. Seven instants of time designated as t 0  through t 6 , are identified. An eighth instant of time, identified as (t 0 ), is the beginning of the next clock cycle, equivalent to time t 0  at the left of the figure. These seven times are discussed in detail with reference to  FIGS. 5A–5G . 
   Referring now to  FIGS. 5A–5G , potentials and charge quantities under each gate shown in  FIG. 4  and potentials of the three diffusions, at the seven successive instants identified in  FIGS. 6A–6G  are shown. The drawing conventions used in this figure are the same as conventions used in  FIG. 2 . As will be seen, the overall effect of one full cycle of operation of the device  100  ( FIG. 4 ) is to shift a charge packet from left to right in the figure (starting at gate  102  and ending at gate  112 ) while subtracting a defined quantity of charge from it. 
   Referring first to  FIG. 5A , initially, at time t 0 , clock voltage P 2  ( FIG. 6B ) is high, forming potential wells  126 ,  128  under gates  102  and  112  respectively. Clock voltages P 1  ( FIG. 6A ) and P 3  ( FIG. 6C ) are low, forming barriers  130 ,  132 ,  134 ,  136  under gates  101 ,  103 ,  111 , and  113  respectively. Clock voltage P 1  is slightly higher than P 2 , so the barriers  130 ,  134  under gates  101  and  111  are slightly lower than barriers  132 ,  136  under gates  103  and  113 . Clock voltage P 6  ( FIG. 6G ) is low, forming a barrier  138  under gate  109 . Clock voltage P 4  ( FIG. 6D ) is low, making storage gate  110  unattractive to charge. Charge packets  121  and  122  are held in potential wells  126  and  128  under storage gates  102  and  112  respectively, isolated by the barriers  130 ,  132 ,  134 ,  136  under gates  101 ,  103 ,  111 , and  113 . Packet  121  is an input charge to the device, and packet  122  is an output charge (from the previous subtraction operation). Clock voltage P 5  ( FIG. 6E ) is moderately high, forming a low barrier  140  under gate  105 . Clock voltage P 6  ( FIG. 6F ) is low, forming a barrier under gate  109 . 
   The potential of diffusions  104  and  108  has been established by allowing charge from diffusion  104  to flow over barrier  140  under gate  105  to diffusion  106 , which acts as a drain. This flow is identified as current  123 . Because of their connection via wire  107 , diffusions  104  and  108  are at the same potential. At time t 0 , current flow  123  has declined to a negligible value, and the potential of diffusions  104  and  108  has settled to equilibrium with the potential of barrier  140  under gate  105 , which is set by clock voltage P 5 . 
   Referring now to  FIG. 5B , at time t 1  clock voltage P 2  is lowered, making the barriers  130 ,  134  at gates  101  and  111  higher, and clock voltage P 3  is raised, making the barriers  132 ,  136  at gates  103  and  113  somewhat lower. All four barrier potentials remain high enough to confine charge packets  121  and  122  in their respective wells. Clock voltage P 5  is lowered, raising the potential of barrier  140  under gate  105 , thus preventing further charge flow from diffusion  104  to diffusion  106 . Clock voltage P 4  is made high, forming a potential well  142  under gate  110 . Clock voltage P 7  is raised by an amount ΔV 7 ; this voltage change is coupled via capacitor  114  and wire  107  to diffusions  104  and  108 , causing their potentials to be lowered. Clock voltage P 6  is raised to the level which P 5  had at t 0 , lowering barrier  138  under gate  109  to the same potential that barrier  140  under gate  105  had at t 0 . A path now exists for charge to flow from diffusion  108  over barrier  138  to well  142  under gate  110 , but the reduced diffusion potential due to the change in P 7  prevents such flow. 
   Referring now to  FIG. 5C , at time t 2  clock voltage P 2  is ramped to a lower voltage. This action raises the well potential under gates  102  and  112 , and consequently the potential of charge packets  121  and  122 , allowing them to flow over the barriers  132 ,  136  at gates  103  and  113  respectively. Charge packet  122  flows into the next storage gate (not shown) as in the basic CCD description given previously. Charge packet  121  flows onto diffusion  104  (as current  124 ), raising the potential of diffusion  104 . Some of this current, identified as  124   a , flows via wire  107  from diffusion  104  to diffusion  108 , maintaining the equal potential of diffusions  104  and  108 . At time t 2 , the potential of diffusions  104  and  108  has not yet risen enough to allow charge to flow over the barrier  138  at gate  109 . 
   Referring now to  FIG. 5D , at time t 3  clock voltage P 2  continues its negative ramp, causing the well potentials under gates  102  and  112  to continue to rise. Charge continues to flow over the barrier  132  at gate  103  (as current  124 ) and over the barrier  136  at gate  113 . Due to charge added by current  124 , the potential of diffusions  104  and  108  has risen high enough for charge to flow over the barrier  138  at gate  109 , resulting in current  125 . As at time t 2 , charge added to diffusion  104  by current  124  is conveyed to diffusion  108  by wire  107 . 
   Referring now to  FIG. 5E , at time t 4  the negative ramp of clock voltage P 2  which began at time t 2  is complete. In this state, the potential under gates  102  and  112  is sufficiently high that all charge from these gates has flowed over the adjacent barriers  132 ,  136  (at gates  103  and  113  respectively). Charge packet  122  is held by the next storage well to the right of gate  113 , which is not shown. Charge packet  121  has been fully transferred to diffusion  104 . Part of it has continued on via wire  107  to diffusion  108 , and part of that component has flowed (as current  125 , shown at t 3 ) over barrier  138  under gate  109  to the well under gate  110 . The resulting charge packet at gate  110  is identified as  126 . At t 4 , currents  124 ,  124   a , and  125  have all declined to a negligible value. 
   As mentioned in connection with the discussion of the circuit at time t 1 , the potential under gate  109  is equal to the potential which existed under gate  105  at t 0 ; this potential served to establish the potential of diffusions  104  and  108  at t 0 . Thus, at equilibrium, the potential of these diffusions and the voltage of wire  107  must be the same as they were at t 0 . For this to be true, capacitor  114  must have been charged by an amount ΔQ=C·ΔV 7 . This is the amount of charge subtracted in this operation. The charge packet  126  resulting under gate  110  is reduced in size from the original packet  121  by this amount ΔQ. 
   Referring now to  FIG. 5F , at time t 5  clock voltage P 3  is set low and P 1  is raised somewhat. As a result, barriers  130 ,  132 ,  134  and  136  under gates  101 ,  103 ,  111  and  113  respectively remain (with barriers  130  and  134  slightly lower.) Clock voltage P 2  is set high, forming (empty) wells under gates  102  and  112 . Clock voltage P 6  is set low, raising the potential of barrier  138  under gate  109 . Clock voltage P 5  is raised, lowering the potential of barrier  140  under gate  105  to its original value at t 0 . No current flows from diffusion  104  because it is already at equilibrium with this potential. 
   Referring now to  FIG. 5G , at time t 6 , clock voltages P 4  and P 7  are ramped negative. The negative ramp of P 4  results in positive ramps in potentials under gate  110  and the gate preceding gate  101  (not shown). This potential rise allows charge packet  126  to flow from gate  110  over the barrier  134  under gate  111  into the well under gate  112 . This flow is identified as current  129 . Charge from the CCD well to the left of gate  101  flows over the barrier  130  at gate  101  into the well under gate  102  as current  127 . Current flows  127  and  129  constitute normal CCD-type charge transfers, as described in conjunction with  FIG. 2 . 
   Also at time t 6 , clock voltage P 7  is ramped negative. This negative ramp causes a negative change in the voltage of wire  107 , with a corresponding positive ramp in the potential of diffusions  104  and  108 . This potential rise allows charge to flow as current  128  from diffusion  104 , over the barrier  140  at gate  105 , to the drain diffusion  106 . In order to maintain diffusion  108  at the same potential as diffusion  104 , current  128   a  also flows via wire  107  from diffusion  108  to diffusion  104 . Currents  128  and  128   a  constitute the disposal of the charge ΔQ which was earlier subtracted from charge packet  121  (resulting in packet  126 ). 
   At the conclusion of the voltage ramps described at t 6 , all voltages have returned exactly to the state shown at t 0 . Charge packet  126  now resides in the potential well under gate  112  (where packet  122  was located at t 0 ). Thus, the overall effects of the device&#39;s operation through a full cycle are, first, to shift a charge packet from gate  102  to gate  112 , and, second, to subtract an amount of charge ΔQ=C·ΔV 7  from it. In successive operating cycles, each charge packet passing through the device is similarly processed. 
   The device depicted in  FIG. 4  can also be used to add charge to a charge packet rather than subtracting it. The sequence of operations is similar to that shown in  FIG. 5 , except that the sign of ΔV 7  is reversed, and charge is supplied rather than drained via diffusion  106 . 
   Referring now to  FIG. 7 , another embodiment of a charge subtraction device  200  includes barrier gates  201 ,  203 ,  205 ,  209 ,  211  and  213 ; storage gates  202 ,  210  and  212 ; and diffused regions  216 ,  217  and  206 . Diffused regions  216 ,  217  are coupled via path  207 . Path  207  may be comprised of metal or other material which makes ohmic contact to the two diffused regions. This embodiment comprises a rearrangement of the same elements of the device described above in conjunction with  FIG. 4 . For example gate  201  in  FIG. 7  corresponds to gate  101  in  FIG. 4 , etc. The combined functions of diffusions  104  and  108  in  FIG. 4  are here carried out by diffusions  216  and  217 . The arrangement of  FIG. 7  is useful if the charge-subtraction operation is desired in the middle of an on-going CCD register, rather than with the output portion of the device in a separate substrate area as shown in  FIG. 4 . 
   In this embodiment, as in the embodiment shown in FIGS.  4  and  5 – 5 G, the incoming charge is transferred from a well under gate  202 , over a barrier under gate  203 , onto a diffusion ( 216  in this case); and thence (after charge subtraction) over a barrier under gate  209  to a well under gate  210 . Unlike the embodiment shown in  FIG. 4 , however, gate  209  is adjacent diffusion  216 , so the diminished charge packet continues along a contiguous path rather than being transferred to a remote location via wire  107 . The subtracted charge is disposed of by flow from diffusion  217  to diffusion  206  over a barrier under gate  205 . This arrangement does not materially change the function of the device from that of the embodiment described above in conjunction with FIGS.  4  and  5 – 5 G. 
   The clock voltages and bias voltage required to operate charge subtraction device  200  shown in  FIG. 7  are identical to those shown in  FIG. 6 . 
   Referring now to  FIGS. 8–8G , potentials and charge quantities under each gate shown in the device  200  of  FIG. 7  and potentials of the three diffusions, at the seven successive instants of time t 0 –t 6  identified in  FIGS. 6A–6G  are shown. The drawing conventions used in this figure are the same as conventions used in  FIG. 2 . As will be seen, the overall effect of one full cycle of operation of the device  200  ( FIG. 7 ) is to shift a charge packet from left to right in the figure (starting at gate  202  and ending at gate  212 ) while subtracting a defined quantity of charge from it. 
   Referring first to  FIG. 8A , initially, at time t 0 , clock voltage applied to terminal P 2  ( FIG. 7 ) is high, forming potential wells  221 ,  228  under gates  202  ( FIG. 7) and 212  ( FIG. 7 ) respectively. The clock voltages applied to terminals P 1  ( FIG. 7 ) and P 3  ( FIG. 7 ) of the device  200  are low, forming barriers  230 ,  232 ,  234 ,  236  under gates  201 ,  203 ,  211 , and  213  ( FIG. 7 ) respectively. The clock voltage applied to terminal P 1  is slightly higher than the voltage applied to terminal P 2 , so the barriers  230 ,  234  under gates  201  and  211  are slightly lower than barriers  232 ,  236  under gates  203  and  213 . The clock voltage applied to terminal P 6  ( FIG. 7 ) is low, forming a barrier  238  under gate  209  ( FIG. 7 ). The clock voltage applied to terminal P 4  ( FIG. 7 ) is low, making storage gate  210  unattractive to charge. Charge packets  221  and  222  are held in potential wells  226  and  228  under storage gates  202  and  212  respectively, isolated by the barriers  230 ,  232 ,  234 ,  236  under gates  201 ,  203 ,  211 , and  213 . Packet  221  is an input charge to the device, and packet  222  is an output charge (from the previous subtraction operation). The clock voltage applied to terminal P 5  ( FIG. 7 ) is moderately high, forming a low barrier  240  under gate  205  ( FIG. 7 ). The clock voltage applied to terminal P 6  is low, forming a barrier under gate  209  ( FIG. 7 ). 
   The potential of diffusions  216  ( FIG. 7) and 217  ( FIG. 7 ) has been established by allowing charge from diffusion  216  to flow over barrier  240  under gate  205  to diffusion  206  ( FIG. 7 ), which acts as a drain. This flow is identified as current  223 . Because of their connection via wire  207 , diffusions  216  and  217  are at the same potential. At time t 0 , current flow  223  has declined to a negligible value, and the potential of diffusions  216  and  217  has settled to equilibrium with the potential of barrier  240  under gate  205 , which is set by the clock voltage provided to terminal P 5 . 
   Referring now to  FIG. 8B , at time t 1  clock voltage P 2  is lowered, making the barriers  230 ,  234  at gates  201  and  211  higher, and clock voltage P 3  is raised, making the barriers  232 ,  236  at gates  203  and  213  somewhat lower. All four barrier potentials remain high enough to confine charge packets  221  and  222  in their respective wells. The clock voltage P 5  is lowered, raising the potential of barrier  240  under gate  205 , thus preventing further charge flow from diffusion  204  to diffusion  217 . Clock voltage P 4  is made high, forming a potential well  242  under gate  210 . Clock voltage P 7  is raised by an amount ΔV 7 ; this voltage change is coupled via capacitor  214  and wire  207  to diffusions  216  and  217 , causing their potentials to be lowered. Clock voltage P 6  is raised to the level which P 5  had at t 0 , lowering barrier  238  under gate  209  to the same potential that barrier  240  under gate  205  had at t 0 . A path now exists for charge to flow from diffusion  208  over barrier  238  to well  242  under gate  210 , but the reduced diffusion potential due to the change in P 7  prevents such flow. 
   Referring now to  FIG. 8C , at time t 2  clock voltage P 2  is ramped to a lower voltage. This action raises the well potential under gates  202  and  212 , and consequently the potential of charge packets  221  and  222 , allowing them to flow over the barriers  232 ,  236  at gates  203  and  213  respectively. Charge packet  222  flows into the next storage gate (not shown) as in the basic CCD description given previously. Charge packet  221  flows onto diffusion  216  (as current  224 ), raising the potential of diffusion  216 . Some of this current, identified as  224   a , flows via wire  207  from diffusion  216  to diffusion  217 , maintaining the equal potential of diffusions  216  and  217 . At time t 2 , the potential of diffusions  216  and  217  has not yet risen enough to allow charge to flow over the barrier  238  at gate  209 . 
   Referring now to  FIG. 8D , at time t 3  clock voltage P 2  continues its negative ramp, causing the well potentials under gates  202  and  212  to continue to rise. Charge continues to flow over the barrier  232  at gate  203  (as current  224 ) and over the barrier  236  at gate  213 . Due to charge added by current  224 , the potential of diffusions  216  and  217  has risen high enough for charge to flow over the barrier  238  at gate  209 , resulting in current  225 . As at time t 2 , charge added to diffusion  216  by current  224  is conveyed to diffusion  217  by wire  207 . 
   Referring now to  FIG. 8E , at time t 4  the negative ramp of clock voltage P 2  which began at time t 2  is complete. In this state, the potential under gates  202  and  212  is sufficiently high that all charge from these gates has flowed over the adjacent barriers  232 ,  236  (at gates  203  and  213  respectively). Charge packet  222  is held by the next storage well to the right of gate  213 , which is not shown. Charge packet  221  has been fully transferred to diffusion  216 . Part of it has continued on via wire  207  to diffusion  217 , and part of that component has flowed (as current  225 , shown at t 3 ) over barrier  238  under gate  209  to the well under gate  210 . The resulting charge packet at gate  210  is identified as  226 . At t 4 , currents  224 ,  224   a , and  225  have all declined to a negligible value. 
   As mentioned in connection with the discussion of the circuit at time t 1 , the potential under gate  209  is equal to the potential which existed under gate  205  at t 0 ; this potential served to establish the potential of diffusions  216  and  217  at t 0 . Thus, at equilibrium, the potential of these diffusions and the voltage of wire  207  must be the same as they were at t 0 . For this to be true, capacitor  214  must have been charged by an amount ΔQ=C·ΔV 7 . This is the amount of charge subtracted in this operation. The charge packet  226  resulting under gate  210  is reduced in size from the original packet  221  by this amount ΔQ. 
   Referring now to  FIG. 8F , at time t 5  clock voltage P 3  is set low and P 1  is raised somewhat. As a result, barriers  230 ,  232 ,  234  and  236  under gates  201 ,  203 ,  211  and  213  respectively remain (with barriers  230  and  234  slightly lower.) Clock voltage P 2  is set high, forming (empty) wells under gates  202  and  212 . Clock voltage P 6  is set low, raising the potential of barrier  238  under gate  209 . Clock voltage P 5  is raised, lowering the potential of barrier  240  under gate  205  to its original value at t 0 . No current flows from diffusion  216  because it is already at equilibrium with this potential. 
   Referring now to  FIG. 8G , at time t 6 , clock voltages P 4  and P 7  are ramped negative. The negative ramp of P 4  results in positive ramps in potentials under gate  210  and the gate preceding gate  201  (not shown). This potential rise allows charge packet  226  to flow from gate  210  over the barrier  234  under gate  211  into the well under gate  212 . This flow is identified as current  229 . Charge from the CCD well to the left of gate  201  flows over the barrier  230  at gate  201  into the well under gate  202  as current  227 . Current flows  227  and  229  constitute normal CCD-type charge transfers, as described in conjunction with  FIG. 2 . 
   Also at time t 6 , clock voltage P 7  is ramped negative. This negative ramp causes a negative change in the voltage of wire  207 , with a corresponding positive ramp in the potential of diffusions  216  and  217 . This potential rise allows charge to flow as current  228  from diffusion  216 , over the barrier  240  at gate  205 , to the drain diffusion  217 . In order to maintain diffusion  217  at the same potential as diffusion  216 , current  228   a  also flows via wire  207  from diffusion  217  to diffusion  216 . Currents  228  and  228   a  constitute the disposal of the charge ΔQ which was earlier subtracted from charge packet  221  (resulting in packet  126 ). 
   At the conclusion of the voltage ramps described at t 6 , all voltages have returned exactly to the state shown at t 0 . Charge packet  226  now resides in the potential well under gate  212  (where packet  222  was located at t 0 ). Thus, the overall effects of the device&#39;s operation through a full cycle are, first, to shift a charge packet from gate  202  to gate  212 , and, second, to subtract an amount of charge ΔQ=C·ΔV 7  from it. In successive operating cycles, each charge packet passing through the device is similarly processed. 
   Referring now to  FIG. 9 , a charge-subtraction device  300  includes barrier gates  301 ,  303 ,  305 ,  309 ,  311  and  313 ; storage gates  302 ,  310  and  312 ; and diffused regions  304 ,  306  and  308 . The drawing conventions used in  FIG. 9  are the same as those used in  FIGS. 1 ,  4  and  7 . 
   The device  300  also includes a capacitor  314  (not part of the CCD itself); and a path  307  which couples diffused regions  304  and  308 . Path  307  may be comprised of metal or other material capable of providing an ohmic contact between the two diffused regions  304  and  308 . It is sometime referred to herein as a “wire.” 
   Diffused regions  304 ,  306 , and  308  (or more simply “diffusions”) are regions of opposite conductivity type to the device substrate, similar to the source/drain diffusions of ordinary MOSFETs. As mentioned above, a diffusion can be regarded as a source or sink for charge, having essentially unlimited quantities of charge carriers available. The potential of charge in the diffusion is related to the electrical voltage of an electrode connected to the diffusion, and may be set by external connection or by charge flows within a CCD. With electrons as charge carriers, a more positive electrode voltage corresponds to a more negative diffusion potential. Note that because of the connection through wire  307 , the potential of diffusions  304  and  308  are always equal. Any tendency towards imbalance is corrected by current flow through wire  307 . 
   Gates  301 ,  302 ,  303 , and  310  comprise the four gates of an ordinary four-phase CCD stage, as described with reference to  FIG. 1 . These gates are driven by clock voltages P 1 , P 2 , P 3 , and P 4  respectively. It should be noted, however, that whereas in a conventional CCD gates  303  and  310  would be adjacent, in the present circuit there are additional structures disposed between them. Gates  311 ,  312 , and  313  constitute the first three gates of an ordinary CCD stage (which continues to the right of the diagram), with the same clock voltages as gates  301 ,  302 , and  303 . Additional CCD stages are assumed to continue to the right and left of the region illustrated in  FIG. 9 . Barrier gate  305  is clocked by voltage P 5 , and barrier gate  309  is clocked by voltage P 6 . The capacitor  314  is driven by clock voltage P 7 . 
   The charge subtraction device  300  further includes Faraday shields provided from gate  314 , biased at static voltage V 3 , and gates  315 , and  316  biased at static voltage V 2 . These added gates serve as Faraday shields between the clocked gates and diffusions  304  and  308 . This shielding reduces capacitive coupling from clocks to the diffusions, thereby improving accuracy of the device. 
   All clock voltages for this embodiment are as shown in  FIG. 6 . Bias voltage V 1  is the same as shown in FIGS.  4  and  5 A– 5 G. 
   Referring now to  FIGS. 10–10G , the schematic device representation from  FIG. 9  is repeated as  FIG. 10 . Potentials and currents are shown in  FIG. 10–10G . The operation of the device  300  is similar to that of device  100  shown in  FIG. 4 , except that the potential to which diffusions  304  and  308  equilibrates is set by the static bias V 2  rather than by the high voltage applied to terminals P 5  and P 6  respectively. In this embodiment, the voltages applied to terminals P 5  and P 6  serve only to control barriers. 
   In each of the charge-subtraction devices described above in conjunction with  FIGS. 1–5G , the charge subtracted in each full cycle of the disclosed device is ΔQ=C·ΔV 7 , wherein ΔV 7  is the change in voltage V 7  between t 0  and t 1  (V 7  undergoes the opposite change, −ΔV 7 , between t 5  and the next t 0 ). When this voltage change is constant, then the subtracted charge ΔQ is constant for successive packets as well. The result is the removal of a fixed amount of charge from all packets in a signal sequence. Charge subtraction is of interest, for example, for the removal of a portion of the ‘background charge’ when the signal charges of interest are only a fraction of the total packet size. For signals represented as differential charge packets (as described below), this constant subtraction would remove part of the common-mode charge. 
   The amount of such charge to be removed or added (proportional to ΔV 7 ) can be determined in various ways, including adjustment by feedback or feed-forward reference to the charge-packet stream itself This control signal can be applied to either the high level, the low level, or both levels of V 7 . 
   In some other applications, the charge to be subtracted or added may be a time-varying quantity representing a second signal. Such a signal can be applied to either the high or low level (or both) of V 7 , as long as ΔV 7  is appropriately controlled. 
   Referring now to  FIGS. 10A–10G , potentials and charge quantities under each gate shown in the device  300  of  FIG. 9  and potentials of the three diffusions, at the seven successive instants of time t 0 –t 6  (identified in  FIGS. 6A–6G ) are shown. The drawing conventions used in this figure are the same as conventions used in  FIG. 2 . As will be seen, the overall effect of one full cycle of operation of the device  300  ( FIG. 9 ) is to shift a charge packet from left to right in the figure (starting at gate  302  and ending at gate  312 ) while subtracting a defined quantity of charge from it. 
   Referring first to  FIG. 10A , initially, at time t 0 , clock voltage applied to terminal P 2  ( FIG. 9 ) is high, forming potential wells  321 ,  328  under gates  302  and  312  respectively. The clock voltages applied to terminals P 1  ( FIG. 9 ) and P 3  ( FIG. 9 ) of the device  300  are low, forming barriers  330 ,  332 ,  334 ,  336  under gates  301 ,  303 ,  311 , and  313  respectively. The clock voltage applied to terminal P 1  is slightly higher than the voltage applied to terminal P 2 , so the barriers  330 ,  334  under gates  301  and  311  are slightly lower than barriers  332 ,  336  under gates  303  and  313 . The clock voltage applied to terminal P 6  ( FIG. 7 ) is low, forming a barrier  338  under gate  309 . The clock voltage applied to terminal P 4  ( FIG. 7 ) is low, making storage gate  310  unattractive to charge. Charge packets  321  and  322  are held in potential wells  326  and  328  under storage gates  302  and  312  respectively, isolated by the barriers  330 ,  332 ,  334 ,  336  under gates  301 ,  303 ,  311 , and  313 . Packet  321  is an input charge to the device, and packet  322  is an output charge (from the previous subtraction operation). The clock voltage applied to terminal P 5  ( FIG. 9 ) is moderately high, forming a low barrier  340  under gate  305 . The clock voltage applied to terminal P 6  is low, forming a barrier under gate  309 . 
   The potential of diffusions  304  and  308  has been established by allowing charge from diffusion  304  to flow over barrier  340  under gate  305  to diffusion  306 , which acts as a drain. This flow is identified as current  323 . Because of their connection via wire  307 , diffusions  304  and  306  are at the same potential. At time t 0 , current flow  323  has declined to a negligible value, and the potential of diffusions  304  and  306  has settled to equilibrium with the potential of barrier  340  under gate  305 , which is set by the clock voltage provided to terminal P 5 . 
   Referring now to  FIG. 10B , at time t 1  clock voltage P 2  is lowered, making the barriers  330 ,  334  at gates  301  and  311  higher, and clock voltage P 3  is raised, making the barriers  332 ,  336  at gates  303  and  313  somewhat lower. All four barrier potentials remain high enough to confine charge packets  321  and  322  in their respective wells. The clock voltage P 5  is lowered, raising the potential of barrier  340  under gate  305 , thus preventing further charge flow from diffusion  304  to diffusion  317 . Clock voltage P 4  is made high, forming a potential well  342  under gate  310 . Clock voltage P 7  is raised by an amount ΔV 7 ; this voltage change is coupled via capacitor  314  and wire  307  to diffusions  304  and  306 , causing their potentials to be lowered. Clock voltage P 6  is raised to the level which P 5  had at t 0 , lowering barrier  338  under gate  309  to the same potential that barrier  340  under gate  305  had at t 0 . A path now exists for charge to flow from diffusion  308  over barrier  338  to well  342  under gate  310 , but the reduced diffusion potential due to the change in P 7  prevents such flow. 
   Referring now to  FIG. 10C , at time t 2  clock voltage P 2  is ramped to a lower voltage. This action raises the well potential under gates  302  and  312 , and consequently the potential of charge packets  321  and  322 , allowing them to flow over the barriers  332 ,  336  at gates  303  and  313  respectively. Charge packet  322  flows into the next storage gate (not shown) as in the basic CCD description given previously. Charge packet  321  flows onto diffusion  304  (as current  324 ), raising the potential of diffusion  304 . Some of this current, identified as  324   a , flows via wire  307  from diffusion  304  to diffusion  306 , maintaining the equal potential of diffusions  304  and  306 . At time t 2 , the potential of diffusions  304  and  306  has not yet risen enough to allow charge to flow over the barrier  338  at gate  309 . 
   Referring now to  FIG. 10D , at time t 3  clock voltage P 2  continues its negative ramp, causing the well potentials under gates  302  and  312  to continue to rise. Charge continues to flow over the barrier  332  at gate  303  (as current  324 ) and over the barrier  336  at gate  313 . Due to charge added by current  324 , the potential of diffusions  304  and  306  has risen high enough for charge to flow over the barrier  338  at gate  309 , resulting in current  325 . As at time t 2 , charge added to diffusion  304  by current  324  is conveyed to diffusion  306  by wire  307 . 
   Referring now to  FIG. 10E , at time t 4  the negative ramp of clock voltage P 2  which began at time t 2  is complete. In this state, the potential under gates  302  and  312  is sufficiently high that all charge from these gates has flowed over the adjacent barriers  332 ,  336  (at gates  303  and  313  respectively). Charge packet  322  is held by the next storage well to the right of gate  313 , which is not shown. Charge packet  321  has been fully transferred to diffusion  304 . Part of it has continued on via wire  307  to diffusion  308 , and part of that component has flowed (as current  325 , shown at t 3 ) over barrier  338  under gate  309  to the well under gate  310 . The resulting charge packet at gate  310  is identified as  326 . At t 4 , currents  324 ,  324   a , and  325  have all declined to a negligible value. 
   As mentioned in connection with the discussion of the circuit at time t 1 , the potential under gate  309  is equal to the potential which existed under gate  305  at t 0 ; this potential served to establish the potential of diffusions  304  and  308  at t 0 . Thus, at equilibrium, the potential of these diffusions and the voltage of wire  307  must be the same as they were at t 0 . For this to be true, capacitor  314  must have been charged by an amount ΔQ=C·ΔV 7 . This is the amount of charge subtracted in this operation. The charge packet  326  resulting under gate  310  is reduced in size from the original packet  321  by this amount ΔQ. 
   Referring now to  FIG. 10F , at time t 5  clock voltage P 3  is set low and P 1  is raised somewhat. As a result, barriers  330 ,  332 ,  334  and  336  under gates  301 ,  303 ,  311  and  313  respectively remain (with barriers  330  and  334  slightly lower.) Clock voltage P 2  is set high, forming (empty) wells under gates  302  and  312 . Clock voltage P 6  is set low, raising the potential of barrier  338  under gate  309 . Clock voltage P 5  is raised, lowering the potential of barrier  340  under gate  305  to its original value at t 0 . No current flows from diffusion  304  because it is already at equilibrium with this potential. 
   Referring now to  FIG. 10G , at time t 6 , clock voltages P 4  and P 7  are ramped negative. The negative ramp of P 4  results in positive ramps in potentials under gate  310  and the gate preceding gate  301  (not shown). This potential rise allows charge packet  326  to flow from gate  310  over the barrier  334  under gate  311  into the well under gate  312 . This flow is identified as current  329 . Charge from the CCD well to the left of gate  301  flows over the barrier  330  at gate  301  into the well under gate  302  as current  327 . Current flows  327  and  329  constitute normal CCD-type charge transfers, as described in conjunction with  FIG. 2 . 
   Also at time t 6 , clock voltage P 7  is ramped negative. This negative ramp causes a negative change in the voltage of wire  307 , with a corresponding positive ramp in the potential of diffusions  304  and  308 . This potential rise allows charge to flow as current  328  from diffusion  304 , over the barrier  340  at gate  305 , to the drain diffusion  306 . In order to maintain diffusion  308  at the same potential as diffusion  304 , current  328   a  also flows via wire  307  from diffusion  308  to diffusion  304 . Currents  328  and  328   a  constitute the disposal of the charge ΔQ which was earlier subtracted from charge packet  321  (resulting in packet  326 ). 
   At the conclusion of the voltage ramps described at t 6 , all voltages have returned exactly to the state shown at t 0 . Charge packet  326  now resides in the potential well under gate  312  (where packet  322  was located at t 0 ). Thus, the overall effects of the device&#39;s operation through a full cycle are, first, to shift a charge packet from gate  302  to gate  312 , and, second, to subtract an amount of charge ΔQ=CΔV 7  from it. In successive operating cycles, each charge packet passing through the device is similarly processed. 
   It should be noted that the circuit described above in conjunction with  FIG. 9  can be considered as the circuit of  FIG. 4  with the addition of Faraday shields. Thus, it should be appreciated that Faraday shields can be similarly added to the circuit embodiment described above in conjunction with  FIG. 7 . 
   The detailed description of this invention given above is based upon a single stream of signal charge packets. In many applications, paired charge packets are used: the signal is represented as the charge difference between the members of a pair of charge packets (this method allows, for example, the representation of signed signal values.) If the charge-packet pair is carried sequentially in a single CCD register, then the method disclosed here is directly applicable: by repeating ΔV 7 , the same ΔQ is removed from (or added to) each member of the pair. If the charge-packet pair is carried in a parallel pair of CCD registers, then the method disclosed here can also be used. The device structure shown in  FIG. 4  is duplicated, with one copy for each of the two CCD registers. V 7  is applied to the two registers via two capacitors equivalent to capacitor  114 . If the capacitors are equal then the subtracted or added charges ΔQ will also be equal. 
   Note that the representations of device elements, charges and potentials in  FIGS. 1–10  are in a conventional form familiar to persons accustomed to designing with CCDs. Note also that, although these figures and the accompanying explanations assume a surface-channel, N-channel CCD, the invention is equally applicable to other CCD types. Such other types include buried-channel CCDs, CCDs with other gate designs such as overlapping gates, P-channel CCDs and Schottky-barrier CCDs. More complex gate sequences, such as cascode designs, may also be used with this invention. In addition, other clocking schemes than the one shown can be used with this invention. 
   Having described preferred embodiments of the invention it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts may be used. Accordingly, it is submitted that that the invention should not be limited to the described embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.