Abstract:
For a bidirectional data transfer between a system bus (CPU-Bus) and a peripheral bus (PCI-Bus) the two busses are connected to each other via a coupling device (BRIDGE). The coupling device (BRIDGE) respectively has two (one per direction) means-specific temporary storage units (FIFO 1 , . . . , FIFOn) for all peripheral devices connected to the peripheral bus (PCI-Bus).

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method for controlling a data transmission. 
     In contemporary data transmission means, particularly in personal computers, what is known as a PCI bus (Peripheral Component Interconnect) is set up for a connection of peripheral means such as an LAN (Local Area Network). The peripheral means are connected to the PCI bus via defined interfaces which are controlled via what are known as I/O controllers. For a data transfer between the peripheral means and other units such as a processor unit or a main memory connected to the processor unit via a processor bus, for example, the PCI bus is connected to the processor bus via a coupling means frequently referred to as a bridge. 
     The data sheet “82439HX System Controller (TXC)” of the firm Intel (July 1996, order number 290551-001, p. 5 and 6 in particular) teaches such a bridge which connects a PCI bus to a processor bus (processor host bus) and a central memory (main memory). The bridge comprises two temporary storage units for a data transfer between the PCI bus and a processor unit, or respectively, the main memory. Those data which are transmitted from the processor unit to a peripheral means connected to the PCI bus, or vice versa, on the basis of an initiative of the processor unit are temporarily stored in a first temporary storage unit. Those data which are transmitted to the main memory from a peripheral means connected to the PCI bus, or vice versa, on the basis of an initiative of said means are temporarily stored in a second temporary storage unit. 
     The first and the second temporary storage units are respectively fashioned as FIFO (First In First Out) memories in which the data to be transmitted are stored together with an address identifying the respective peripheral means. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method by which the degree of effectivity of a data transfer between two system busses is increased. 
     For a better understanding of the functions and the operation of a bridge it seems necessary to initially elaborate on known principles with the aid of a PCI bus architecture realized in a personal computer. 
     If a processor unit requests data from a peripheral means, then the processor unit outputs a read request to the processor bus along with the address of an I/O controller allocated to the peripheral means. A first module with a first functional unit of the bridge recognizes the address of the peripheral means and transmits the read request to a second module of the first functional unit. This outputs the read request with the address of the I/O controller onto the PCI bus. The addressed I/O controller recognizes the read request directed thereto and outputs the requested data to the PCI bus. The second module of the first functional unit incorporates the requested data into a first submemory of the FIFO memory of the first functional unit. The first module of the first functional unit reads the data from the first submemory of the FIFO memory and outputs them to the processor bus, from which they are read by the processor unit. 
     When a processor unit transmits data to a peripheral means, the processor unit outputs a write request to the processor bus and subsequently outputs the data to be transmitted to the processor bus along with the address of an I/O controller allocated to the peripheral means. The first module of the first functional unit of the bridge recognizes the address of the peripheral means and transmits the write request to the second module of the first functional unit. The first module simultaneously writes the data to be transmitted into a second submemory of the FIFO memory of the first functional unit. The second module applies the write request to the PCI bus. The addressed I/O controller recognizes the write request directed thereto and signals its readiness to receive data to the bridge. The second module of the first functional unit then reads the data from the second submemory of the FIFO memory and outputs them to the PCI bus, the I/O controller taking them over from there. 
     If data of a peripheral means are to be stored in the main memory on the basis of a request of an I/O controller, the I/O controller writes these data to the PCI bus along with the address at which the data should be stored in the main memory. A first module of a second functional unit recognizes the address in the main memory and writes the data with the appertaining address into a first submemory of a FIFO memory of the second functional unit. A second module of the second functional unit reads the data from the first submemory of the FIFO memory and outputs them to the processor bus together with the address at which the data are to be stored in the main memory. The main memory recognizes the addresses and stores the data at the corresponding location in the main memory. 
     If data is to be read from the main memory on the basis of a request of an I/O controller, the I/O controller outputs a corresponding read request to the PCI bus with the address of the desired data in the main memory. The first module of the second functional unit recognizes the address in the main memory and transmits the read request to the second module of the second functional unit. This outputs the read request to the processor bus together with the address in the main memory. The main memory recognizes the read request and outputs the requested data to the processor bus. The second module of the second functional unit takes over the data from the processor bus and writes the requested data into a second submemory of the FIFO memory of the second functional unit. The first module of the second functional unit reads the data from the second submemory of the FIFO memory and outputs them to the PCI bus together with the address of the requested I/O controller, from which they are read by the I/O controller. 
     A distribution of free bus capacities, that is, the allocation of who can write data to a bus as “master”, ensues via an arbitration module specific to the bus. An arbitration module of the processor bus manages request messages released by the processor unit and by the second module of the second functional unit, for example, for an accessing of the processor bus. An arbitration module of the PCI bus manages request messages released by the I/O controllers and by the second module of the first functional unit, for example, for an accessing of the PCI bus. 
     Different priorities can be allocated to the individual request messages for a system bus; that is, given time-critical data a timely allocation of the master function for the system bus to the waiting unit ensues even given a high loading of the corresponding system bus. A higher priority is assigned to a request message for speech data to be transmitted than to a request for the transmission of non-time-critical security data, for example. 
     The data transfer between peripheral means, or respectively, units of the central computer system, and the bridge ensues by means of burst operations. In burst operations a plurality of data packets are transmitted in succession, whereby the appertaining destination address is not co-transmitted for every individual data packet. Only the address of a memory cell into which the first data packet is to be written is transmitted. The subsequent data packets are automatically written into the subsequent memory cells. 
     The length of a burst operation is individually adjustable for each unit transmitting data. The length is determined by a latency timer specific to the unit. The length of a burst operation is explicitly prescribed by the time set for the latency timer, that is, the time during which a unit may write data onto a system bus. By the prescription of how long a unit may occupy a system bus it is guaranteed that each unit connected to the system bus can transmit the requested data even given high loading of the system bus. 
     The inventive method offers the advantage that in a transmission of data between the system bus and the peripheral bus an intermediate storage of data allocated to a respective means in a temporary storage unit specific to the means is performed, whereby the data allocated to a means is collected and subsequently transmitted in a block. For a transmission of a plurality of data packets (data packets from a plurality of burst operations) only one accessing of a system bus is necessary, whereby a saving of the time necessary for the other bus accesses is achieved, and so a plurality of accesses onto one system bus can be realized at the same time. 
     Based on a respectively individual definition of a storage fill value upon the attainment of which an output of data onto a system bus is begun an optimal loading of the system bus is achieved according to the configuration of the means connected to a system bus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several Figures of which like reference numerals identify like elements, and in which: 
     FIG. 1 depicts a structural illustration for the schematic depiction of the functional units participating in the framework of a data transfer; 
     FIG. 2 depicts a structural illustration for the schematic depiction of the functional units of a coupling means according to FIG. 1; 
     FIG. 3 depicts a flow diagram for a data transfer from a peripheral means to the main memory, this being initiated by an I/O controller; 
     FIG. 4 a  depicts a flow diagram for a read request for a data transfer from the main memory to a peripheral means, this being initiated by an I/O controller; and 
     FIG. 4 b  depicts a flow diagram for a data transfer from the central computer system to a peripheral means, this being initiated by an I/O controller. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a schematic depiction of the functional units participating in a data transfer between a data processing means ZR and peripheral means LAN 1 , . . . , LANn. A processor CPU of the data processing means ZR is connected to a main memory MEM via a CPU bus. Programs for the processing by the processor CPU as well as appertaining data are stored in the main memory MEM. The peripheral means LAN 1 , . . . , LANn are connected to each other via a PCI bus. I/O controllers I/O 1 , . . . , I/On control the interface between the peripheral means LAN 1 , . . . , LANn and the PCI bus. Data which are transmitted from the peripheral means LAN 1 , . . . , LANn to units of the main computer system ZR, or from these to the peripheral means LAN 1 , . . . , LANn are temporarily stored in the I/O controllers I/O 1 , . . . , I/On. The CPU bus and the PCI bus are connected to each other for a data transfer via a coupling means BRIDGE. 
     FIG. 2 shows a schematic depiction of the functional units of the coupling means BRIDGE. The coupling means BRIDGE comprises two functional units A, B. The first functional unit A serves the transmission of data which are to be transmitted to a peripheral means LAN 1 , . . ., LANn or from this to the processor CPU on the basis of a request of the processor CPU. The second functional unit B serves the transmission of data which are to be transmitted from the appertaining peripheral means LAN 1 , . . . , LANn to the main memory MEM or from this to the peripheral means LAN 1  ,. . . ,LANn on the basis of a request of an I/O controller I/O 1 , . . . , I/On. 
     The first functional unit A of the coupling means BRIDGE comprises a temporary storage unit FIFO (First In First Out) which is connected to the CPU bus via a first module CPU-SLAVE and to the PCI bus via a second module PCI-MASTER. The temporary storage unit FIFO is arranged in two submemories R, W, whereby in the first submemory R data are written by the second module PCI-MASTER and read by the first module CPU-SLAVE. In the second submemory W of the temporary storage unit FIFO data are written by the first module CPU-SLAVE and read by the second module PCI-MASTER. 
     The second functional unit B of the coupling means BRIDGE comprises a temporary storage unit FIFO 1 , . . . , FIFOn for each peripheral means LAN 1 , . . . , LANn connected to the PCI bus, this storage unit being specific to each individual means. The means-specific temporary storage units FIFO 1 , . . . , FIFOn of the second functional unit B are connected to the CPU bus via a third module CPU-MASTER and to the PCI bus via a fourth module PCI-SLAVE. As in the first functional unit A, the means-specific temporary storage units FIFO 1 , . . . , FIFOn comprise a first submemory R in which data are written by the fourth module PCI-SLAVE and read by the third module CPU-MASTER. In a second submemory W of the means-specific temporary storage units FIFO 1 , . . . , FIFOn data are written by the third module CPU-MASTER and read by the fourth module PCI-SLAVE. 
     If the processor CPU requires data from a peripheral means LAN 1 , . . . , LANn it sends a corresponding message to an arbitration module (not depicted) for the CPU bus. If the arbitration module for the CPU bus allocates the master function for the CPU bus to the processor CPU, this outputs a read request to the CPU bus along with the address of the I/O controller I/O 1 , . . . , I/On allocated to the peripheral means LAN 1 , . . . ,LANn. The master function is assigned to the processor CPU by the arbitration module for the CPU bus until the requested data are readied on the CPU bus. The first module CPU-SLAVE of the first functional unit A recognizes the address of the I/O controller I/O 1 , . . . , I/On and transmits the read request to the second module PCI-MASTER. This subsequently transmits a message to an arbitration module (not depicted) for the PCI bus. If the master function for the PCI bus is allocated to the second module PCI-MASTER by the arbitration module for the PCI bus, this outputs the read request to the PCI bus along with the appertaining address of the I/O controller I/O 1  , . . . , I/On. The master function is assigned to the second module PCI-MASTER by the arbitration module for the PCI bus until the requested data are held ready on the PCI bus. 
     The addressed I/O controller I/O 1 , . . . , I/On recognizes the read request directed thereto and outputs the requested data onto the PCI bus. The second module PCI-MASTER takes over the data and writes them into the first submemory R of the temporary storage unit FIFO of the first functional unit A. The first module CPU-SLAVE reads the data from the first submemory R of the temporary storage unit FIFO and outputs them to the CPU bus. From there the data is read by the main memory and stored at the corresponding location in the main memory MEM. When the processor CPU transmits data to a peripheral means LAN 1 , . . . , LANn it transmits a corresponding message to the arbitration module for the CPU bus. If the arbitration module for the CPU bus allocates the master function for the CPU bus to the processor CPU, this applies a write request, and subsequently applies the data to be transmitted, along with the address of the I/O controller I/O 1 , . . . , I/On allocated to the peripheral means LAN 1 , . . . , LANn, at the CPU bus. The first module CPU-SLAVE of the first functional unit A recognizes the address of the I/O controller I/O 1 , . . . , I/On and transmits the write request to the second module PCI-MASTER. It simultaneously writes the data to be transmitted into the second submemory W of the temporary storage unit FIFO of the first functional unit A. The second module PCI-MASTER transmits a message to the arbitration module for the PCI bus. If the master function of the PCI bus is allocated to the second module PCI-MASTER by the arbitration module for the PCI bus, then this outputs the write request to the PCI bus along with the appertaining address of the I/O controller I/O 1 , . . . , I/On. 
     The addressed I/O controller I/O 1 , . . . , I/On recognizes the write request directed thereto and signals its readiness to receive data to the module PCI-MASTER. The module PCI master then reads the data from the second submemory W of the FIFO memory of the functional unit A and outputs these to the PCI bus, from which the addressed I/O controller I/O 1 , . . . , I/On takes them over. 
     FIG. 3 depicts a flow diagram for a data transfer between a first peripheral means LAN 1  and the main memory MEM, this being initiated by a first I/O controller I/O 1 . If on the basis of a request of a first I/O controller data are transmitted from the appertaining first peripheral means LAN 1  to the main memory MEM, the first I/O controller I/O 1  transmits a corresponding message to the arbitration module for the PCI bus. If the arbitration module for the PCI bus allocates the master function for the PCI bus to the first I/O controller I/O 1 , this outputs the data to the PCI bus along with the address at which the data are to be stored in the main memory MEM. The fourth module PCI-SLAVE of the second functional unit B recognizes the address in the main memory MEM and writes the data with this address into the first submemory R of the first temporary storage unit FIFO 1 , which is allocated to the first peripheral unit LAN 1 . 
     Data are written into the first submemory R of the first temporary storage unit FIFO 1  until an upper memory fill value is exceeded. Only then does the third module CPU-MASTER transmit a message to the arbitration module for the CPU bus. If the arbitration module for the CPU bus allocates the master function for the CPU bus to the third module CPU-MASTER, the third module CPU-MASTER reads the data from the first submemory R of the first temporary storage unit FIFO 1  and outputs them to the CPU bus along with the address at which the data are to be stored in the main memory MEM until the first submemory R of the first temporary storage unit FIFO 1  is emptied. The main memory MEM recognizes the address and stores the transmitted data at the corresponding location in the main memory MEM. 
     FIG. 4 a  depicts a flow diagram for a read request for a data transfer from the main memory MEM to a first peripheral means LAN 1 , this request being initiated by a first I/O controller I/O 1 . If data are to be read from the main memory MEM on the basis of a request of a first I/O controller I/O 1 , then the first I/O controller I/O 1  transmits a corresponding message to the arbitration module for the PCI bus. If the arbitration module for the PCI bus allocates the master function for the PCI bus to the first I/O controller I/O 1 , the first I/O controller I/O 1  outputs the corresponding read request onto the PCI bus along with the address of the requested data in the main memory MEM. The master function is allocated to the first I/O controller I/O 1  by the arbitration module for the PCI bus until the requested data are retrieved onto the PCI bus (continuation of the process, see FIG. 4 b , mark “II”). The fourth module PCI-SLAVE of the second functional unit B recognizes the address in the main memory MEM and transmits the read request to the third module CPU -MASTER along with the address of the requested data in the main memory MEM. 
     The third module CPU-MASTER then transmits a message to the arbitration module for the CPU bus. If the arbitration module for the CPU bus allocates the master function for the CPU bus to the third module CPU-MASTER, the third module CPU-MASTER outputs the read request onto the CPU bus along with the address of the requested data in the main memory MEM. The master function for the CPU bus is allocated to the third module CPU-MASTER until the requested data are held ready on the CPU bus along with the address of the first I/O controller I/O 1  (continuation of the process, see FIG. 4 b , mark “I”). In addition to the data requested by the first I/O controller I/O 1  the third module CPU-MASTER additionally requests data subsequently stored in the main memory MEM (data prefetching). 
     The main memory MEM recognizes the read request and outputs the data requested by the third module CPU-MASTER onto the CPU bus. The address up to which additional data from the main memory MEM are written onto the CPU bus is individually adjustable for each peripheral means LAN 1 , . . . , LANn. The amount of the data which are read out of the main memory MEM is limited by the size of the temporary storage units FIFO 1 , . . . , FIFOn, which is specific to the individual means. 
     FIG. 4 b  depicts a flow diagram for a data transfer from the main memory MEM to the first peripheral means LAN 1 , this being initiated by a first I/O controller I/O 1 . After the data requested by the first I/O controller I/O 1  and the other data from the main memory MEM has been outputted onto the CPU bus (continuation of marker “I” in FIG. 4 a ), the third module CPU-MASTER of the second functional unit B takes over the data from the CPU bus and writes the data, along with the address of the first temporary storage unit FIFO 1 , into the second submemory W of the first temporary storage unit FIFO 1 . The fourth module PCI-SLAVE recognizes the data requested by the first I/O controller I/O 1  and outputs these along with the address of the first I/O controller I/O 1  to the PCI bus. The first I/O controller I/O 1  reads the requested data from the PCI bus and forwards these to the first peripheral means LAN 1 . 
     If the first I/O controller I/O 1  requests the other data, then these are promptly written onto the PCI bus on the basis of a new read request by the fourth module PCI-SLAVE. But if the first I/O controller I/O 1  requests data which are not temporarily stored in the second submemory W of the first temporary storage unit FIFO 1  of the second functional unit B, then the other data are deleted from the second submemory W. 
     The invention is not limited to the particular details of the method depicted and other modifications and applications are contemplated. Certain other changes may be made in the above described method without departing from the true spirit and scope of the invention herein involved. It is intended, therefore, that the subject matter in the above depiction shall be interpreted as illustrative and not in a limiting sense.