Abstract:
A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate; mounting at least a first electronic component on the substrate; positioning a handle wafer above the first electronic component; attaching the first electronic component to the substrate via electrical connectors between the first electronic component and the substrate; and while attaching the first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the first electronic component, to manage planarity of the first electronic component during the attaching. In an embodiment, a joining process is used to attach the first electronic component to the substrate via the electrical connectors. For example, thermal compression bonding may be used to attach the first electronic component to the substrate via the electrical connectors.

Description:
BACKGROUND 
       [0001]    This invention generally relates to integrated devices, and more specifically, to integrated devices having die, chip, or other component stacks, and to method of manufacturing such integrated devices. 
         [0002]    As electronic devices, such as smart phones, tablets and laptop computers, get smaller, lighter and faster, they need smaller and more multifunctional semiconductor devices, components and functions. To achieve this, semiconductor devices may be provided with a stack of two or more semiconductor chips or dies mounted on a substrate and connected together using fine pitch electrical connectors such as solder bumps or balls. 
         [0003]    Semiconductor chip stack packages present many manufacturing challenges. A current approach for fine pitch assembly uses thermal compression bonding, which requires high cost tools, and has a relatively slow volume through-put. For instance, volume through-put is on the order of four to ten seconds per stack bond, and a nine high HMC stack could take, for example, thirty-six to ninety seconds to assemble. A second problem is wafer bow or die bow/planarity and handling for thin parts. 
       SUMMARY 
       [0004]    Embodiments of the invention provide methods of manufacturing or assembling integrated devices and stacked integrated devices. In an embodiment, the method comprises providing a substrate, mounting at least a first electronic component on the substrate, positioning a handle wafer above the at least a first electronic component, and attaching the at least a first electronic component to the substrate via electrical connectors between the at least a first electronic component and the substrate. The method further comprises while attaching the at least a first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the at least a first electronic component, to manage planarity of the at least a first electronic component during said attaching. 
         [0005]    In an embodiment, the attaching the at least a first IC die to the substrate includes using a thermal reflow process to attach the at least a first IC die to the substrate via the electrical connectors. 
         [0006]    In an embodiment, the attaching the at least a first electronic component to the substrate includes using a joining process to attach the at least a first electronic component to the substrate via the electrical connectors. 
         [0007]    In an embodiment, the attaching the at least a first electronic component to the substrate includes using thermal compression bonding to attach the at least a first electronic component to the substrate via the electrical connectors, and the using the handle wafer includes using the handle wafer during the thermal compression bonding to apply pressure to the electrical connectors. 
         [0008]    In an embodiment, the handle wafer is attached to the at least a first electronic component, and the method further comprises removing the handle wafer from the at least a first electronic component after the attaching the at least a first electronic component to the substrate. 
         [0009]    In an embodiment, the mounting at least a first electronic component on the substrate includes mounting a plurality of electronic components on the substrate, one of the electronic component at a time, to form a stack of the electronic components on the substrate, said plurality of electronic components including the first electronic component and one or more additional electronic components; the attaching the at least a first electronic component to the substrate includes attaching each of the one or more additional electronic components to one of the electronic components below said each additional electronic component in the stack; and the using the handle wafer to apply pressure includes, while attaching each of the one or more additional electronic components, using the handle wafer to apply pressure, toward the substrate, to said each additional electronic component to manage co-planarity of the plurality of the electronic components. 
         [0010]    In an embodiment, the at least a first electronic component is a first level electronic component; the handle wafer is attached to the first level electronic component; and the method further comprises, after the attaching the first level electronic component to the substrate, removing the handle wafer from the first level electronic component, mounting a plurality of second level electronic components on the first level electronic component, and attaching the second level electronic components to the first level electronic component via electrical connectors between the second level electronic components and the first level electronic component to form a plural level component stack on the substrate. 
         [0011]    In an embodiment, the method further comprises using a first adhesive process to fill a space underneath the first level electronic component with a first adhesive to further attach the first level electronic component to the substrate, and using a second adhesive process to fill a space underneath the second level electronic components with a second adhesive to further attach the second level electronic components to the first level electronic component. 
         [0012]    In an embodiment, the method further comprises, after the attaching the second level electronic components to the first level electronic component, removing the plural level component stack from the substrate, and transferring the plural level component stack onto another substrate. 
         [0013]    In an embodiment, the mounting at least a first electronic component on the substrate includes forming a plurality of separate stacks on the substrate, each of the stacks including a plurality of flat electronic components; the attaching includes, in each of the stacks, attaching the electronic components of said each stack in place in said each stack; and the using the handle wafer includes, while attaching the electronic components of each stack in place, using the handle wafer to apply pressure, toward the substrate, to all of the plurality of stacks to manage co-planarity of the electronic components of the stacks. 
         [0014]    In an embodiment, the method further comprises transferring the plurality of stacks from the substrate onto one or more other substrates. 
         [0015]    In an embodiment, the invention provides a stacked integrated circuit device comprising a substrate, one or more electronic components mounted on the substrate, and one or more groups of electrical connectors for attaching the one or more electronic components in place in a stack on the substrate and for attaching the stack to the substrate. The stacked integrated device further comprises a handle wafer on the stack of the electronic components to apply pressure on the stack, toward the substrate, as the electronic components are attached in place and the stack is attached to the substrate, to manage co-planarity of the electronic components while the electronic components are attached in place and the stack is attached to the substrate. 
         [0016]    In an embodiment, the handle wafer is attached to the stack of the one or more electronic components. 
         [0017]    In an embodiment, the one or more electronic components includes a first electronic component mounted on the substrate, and a second electronic component mounted on the first electronic component; and the one or more groups of electrical connectors includes a first group of electrical connectors attaching the first electronic component to the substrate, and a second group of electrical connectors attaching the second electronic component to the first electronic component. 
         [0018]    In an embodiment, the stacked integrated device further comprises a first adhesive filling a space beneath the first electronic component, between the first electronic component and the substrate, and a second adhesive filling a space beneath the second electronic component, between the second electronic component and the first electronic component. 
         [0019]    In an embodiment, the one or more electronic components mounted on the substrate includes a multitude of flat electronic components forming a plurality of separate stacks on the substrate, each of the stacks comprising a plurality of the flat electronic components; and the handle wafer extends over all of said stacks to apply pressure, toward the substrate, to all of the plurality of stacks to manage co-planarity of the electronic components of the stacks. 
         [0020]    As mentioned above, semiconductor chip stack packages present many manufacturing challenges or potential problems, including fine pitch assembly and wafer or die bow. Thermal compression bonding solution for fine pitch assembly exists but is too high cost for most high volume applications especially where one die is assembled per each cycle of the thermal compression bonding cycle. 
         [0021]    High volume manufacturing solution use thinned die on handle wafer for test/replace/wafer level joining. This includes reflow (vol. w/fixture)/formic acid/uPillar assembly. 
         [0022]    The high volume manufacturing solution using thinned die on a handle wafer also includes co-planarity management (handler) and stress management, solder to liquid transient metal (LTM)/intermetallic compound (IMC) for layer lock down (wafer-to-wafer (W2W) 1 st  stacking), die to wafer for low volume or lower yielding wafers, and wafer to wafer for high volume using self repair designed into the circuits directly or through test and repar in circuits. The solution also includes use of Known Good Die (KGD) and/or test with self repair of die stack or module, and rework of known good die stacks (underfilled die stacks) (Ni/Fe Ball Limiting Metallurgy (BLM) for multiple reflow to IP. 
         [0023]    Embodiments of the invention provide a number of advantages and features. For instance, embodiments of the invention provide  3 D volume manufacturing using wafer to wafer die stack assembly with one or more handle wafers for co-planarity management and multiple die or wafer joining using reflow (or thermal compression bonding), formic acid or alternate no clean flux, transient liquid phase solder to IMC joining with solder balls and/or micro Pillar structures comprised of solder and a rigid pillar such as Cu, CuNi, TiNiCuNi or alternate pillar structure. 
         [0024]    Embodiments of the invention, optionally, use reactive ion etch (RIE), deep reactive ion etch (DRIE) and/or Laser and/or mechanical saw sizing for singulation of die joining at wafer level. Embodiments of the invention, optionally, also can use known good die for assembly, use e-fuse or alternate self-test repair of die, die stack post assembly, and multiple reflow cycles to add one or more wafer levels per reflow toward ultimate systems micro-systems, sub systems or sub-micro-systems. 
         [0025]    Embodiments of the invention may use Si or glass handle wafers for temporary co-planarity management of thin die, wafers and joining process with adhesive and subsequent debonding of one or more handle wafers per bonding cycle. Similarly, glass panels could be deployed with proper planarization specifications consistent with targeted interconnection density and die or component integration specifications to support alternative to glass or silicon wafer handle solutions or alternate handle-like solutions to support multi-die or component handling, processing, assembly integration and/or testing. In the case of glass or silicon wafer handling or alternate form factors, holes in the handle wafer can be used for atmosphere access such as formic acid in joining cycles to reduce or eliminate surface oxides on solder or joining pads. Embodiments of the invention provide the option to use fixtures to hold top and bottom wafers during reflow with a targeted gravitational weight or targeted force which can act as a weight, a clamp for position accuracy of each wafer or wafer/group of components to be joined and/or to avoid movement unless desired such as in surface tension casing solder reflow during the handling and joining process or solder reflow process. Embodiments of the invention also may add one or more layers with handle wafer support on one or both sides of stacked wafer pairs in one or more parallel operations or in sequential operations or steps. 
         [0026]    Embodiments of the invention may optionally use capillary underfill for joining each layer up to all layers in the die stack or wafer stack in one or more steps, and may optionally use vacuum assisted underfill for joining each layer up to all layers in die stack or wafer stack in one or more steps. Embodiments of the invention also may optionally use pre-applied underfill to join each layer in the stack during bonding, and may optionally use laser or alternate dicing between die stacks to cut through adhesive of die stacks for singulation and for stress reduction. 
         [0027]    Embodiments of the invention may optionally use Cu/Ni/Au, NiFe Au or alternate BLM at the bottom of a die stack for die stack to package interconnection such that solder bump interconnections, solder pillar (such as but not limited to solders such as SnAgCu or SnAg or alternate solder and pillar such as Cu or NiCu) or alternate pillar structures along with or without solder barrier layers such as Ni and/or NiFe or Cr or Co are able to reduce the reaction of solder with the underlying pillar structure such as Cu and therefore support subsequent post bonding processing or rework operations and support testing of the integrated structures, circuits, stacked die, components and/or systems. 
         [0028]    Embodiments of the invention use stress management layers such as compressive or tensile layers to create improved coplanarity of die, wafer or bonded die or bonded wafers or bonded die or wafers with handle wafers during processing or for wafer stacks or die stacks post any handle wafer removal. Embodiments of the invention use die stack structures which may be comprised of one or more memory die, one or more logic die, one or more FPGA die, one or more network die, one or more antenna layers, one or more network or cross bar layers, one or more photonic layers as homogeneous or heterogeneous stacks, battery layers or sub-layers, packaging layers, capacitor layers, or other components, sub components, systems or sub-systems. 
         [0029]    Embodiments of the invention provide an option for wafer to wafer permanent bonding using oxide or polymer adhesive and post via, through-silicon-vias (TSV) or through-dielectric-vias (TDV) interconnection in one or more layers in the stack, and with use of silicon on wafer (SOI) wafers or standard wafers such as bulk Silicon, 3-5 compound materials such as but not limited to GaAs or GaN or alternate wafer materials and/or circuits and/or passive function. 
     
    
     
       DRAWINGS 
         [0030]      FIGS. 1A-1D  illustrate a method of manufacturing a wafer die stack assembly, and a wafer made by the method, in accordance with an embodiment of the invention. 
           [0031]      FIGS. 2A-2D  show another embodiment of the invention in which a wafer die stack is assembled on a handle wafer or temporary chip attach (TCA) carrier or substrate. 
           [0032]      FIGS. 3A-3C  depict a further embodiment of the invention in which a multi-chip stack is assembled on an organic or low temperature co-fixed ceramic (LTCC) substrate. 
           [0033]      FIGS. 4A-4D  show another embodiment of the invention in which a multi-chip stack is assembled between a pair of handle wafers or TCAs and then transferred to an organic or LTCC substrate. 
           [0034]      FIGS. 5A-5D  show a method similar to  FIGS. 1A-1D  and in which a thermal reflow is used to attach the die to the substrate. 
           [0035]      FIGS. 6A-6D  illustrate a further embodiment of this invention similar to the embodiment of  FIGS. 2A-2D  and in which thermal reflows are used to assemble the die stack. 
           [0036]      FIGS. 7A-7C  show an embodiment of the invention similar to the embodiment of  FIG. 3 , and in which a thermal reflow is used in one part of the embodiment. 
           [0037]      FIGS. 8A-8D  illustrate another embodiment of the invention, similar to the embodiment of  FIGS. 4A-4D , and in which multiple stacks are assembled between a pair of handle wafers or TCAs. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    Embodiments of the invention provide integrated devices and methods of manufacturing integrated components. A wide range of devices may be made using embodiments of the invention. For instance, embodiments of the invention may be used to make integrated circuits, electronic components, electronic sub-components, capacitors, resistors, batteries, antenna, or electronic micro-systems. 
         [0039]    Also, a wide variety of electronic components may be used in the manufacturing methods and processes disclosed herein. For example, the electronic components may be integrated circuit dies, which in turn may be processor circuits, memory circuits or a combination thereof. The memory circuits may be, for instance, double data rate type three (DDR3) synchronous dynamic random access memory (SDRAM) circuits. In other aspects, the dies may be other types of processor and/or memory circuits, communication circuits, and/or other function circuits. Other electronic components that may be used in this invention include battery components, resistor components, capacitor components, antenna components and other components that may form part of an electronic system, sub-system or microsystem. 
         [0040]      FIGS. 1A-1D  show a first embodiment of the invention.  FIG. 1A  shows organic or LTCC substrate  12 , an integrated circuit chip or die  14 , and handle wafer  16 . Chip  14  is connected to substrate  12  by solder bumps  21  and, in particular by thermal compression bonding. In this thermal compression bonding, solder bumps  20  are heated and pressure is applied to the solder bumps by applying pressure to handle wafer  16 . The handle wafer also prevents the chip  14  from bending in this process. 
         [0041]    After the chip  14  is connected to substrate  12 , handle  16  is removed, producing the device  22  shown in  FIG. 1B . As one example, handle  16  may be removed by laser ablation. In particular, handle  16  is attached to chip  14  by an adhesive, and a laser is used to heat the adhesive to dissolve the adhesive and loosen the handle from the chip. The back of the chip may then be cleaned, for example by a chemical process. 
         [0042]    As shown in  FIG. 1C ., a liquid glue underfill  24  is applied to device  22 , and this liquid underfill flows underneath chip  14 . Any suitable liquid glue underfill procedure may be used, and any suitable liquid glue or adhesive material may be used in this process. 
         [0043]    As illustrated in  FIG. 1D , one or more chips  26  are mounted on chip  14 , and chips  26  may be connected to chip  14  by solder bumps  30 . A liquid glue underfill  32  may also be applied in which a liquid glue or adhesive flows underneath chips  26 . 
         [0044]    With this embodiment, device  22 , as shown in  FIG. 1D , comprises a level-one IC die  14  (also referred to herein as “bottom IC die”) and two level-two IC dies  26 , all of which may be made of semiconductor materials, such as, but not limited to, silicone and/or germanium. The IC dies  14 ,  26  may be any type of IC, such as, but not limited to, processing circuits, memory circuits, or a combination thereof. In one aspect, the level-one IC die  14  is an IC that is substantially a processing circuit, and the level-two dies  26  are memory circuits, such as double data rate type three (DDR3) synchronous dynamic random access memory (SDRAM) circuits. In other aspects, the dies  14 ,  26  may be other types of processing and/or memory circuits. 
         [0045]    The level-one IC die  14  has an active surface side (e.g., front side surface) that includes a plurality of integrated circuit components (e.g., transistors, capacitors, inductors, resistors, etc.). Similarly, the level-two IC dies  26  each have an active surface side (e.g., front side surface) that includes a plurality of integrated circuit components (e.g., transistors, capacitors, inductors, resistors, etc.). The dies  14 ,  26  each have a back side surface as well. 
         [0046]    The active surface of the level-one IC die  14  may be electrically coupled to the substrate  12  that it faces via a plurality of smaller electrical conductors  20 , and the active surface of the level-two IC dies  26  may be electrically connected to the level-one IC die  14  via another plurality of electrical connectors  30 . In the illustrated example, the electrical conductors  20 ,  30  are soldering balls, and thus the IC die  14  may be electrically coupled to the substrate  12  and IC dies  26  may be electrically coupled to IC die  14  in a ball grid array (BGA) flip chip fashion. However, the electrical conductors  20 ,  30  are not limited to soldering balls, and may be any metal, metal alloy, or conductive element that is capable of readily transmitting an electrical signal. For example, the electrical conductors  20 ,  30  may be, but are not limited to, soldering bumps, pillars, pins, stud bumps, and/or stacks of stud bumps. 
         [0047]    In addition, in one aspect, the IC dies  14 ,  26  may electrically communicate with one another by transmitting and receiving electrical signals via interconnections within the multi-layer package. In another aspect, the level-one IC die  14  may be electrically coupled to the level-two IC dies  26  using through-silicon-vias (TSV) or alternate interconnections. For example, level-one IC die  14  may have both a front side and a back side. The front side of the level-one IC die  14  faces the smaller electrical conductors  20  and the back side of level-one IC die faces IC dies  26 . Thus, TSV elements (not shown) may pass through the back side surface of the level-one IC die  14  and electrically couple with the active surfaces of the level-two IC dies  26 . Consequently, the stacked IC dies may electrically communicate with each other through the substrate or through TSVs. 
         [0048]      FIGS. 2A-2D  illustrate a second embodiment, in which a chip stack is assembled on a handle wafer or a temporary chip attach (TCA) carrier or substrate and then transferred onto an organic or LTCC substrate. 
         [0049]      FIG. 2A  shows a handle wafer or TCE  42 , an integrated circuit chip or die  44  and handle wafer  46 . Chip  44  is connected to handle wafer or TCA  42  by solder bumps  50 . Similar to the procedure shown in  FIGS. 1A-1D , thermal compression bonding may be used to attached the chip  44  to the wafer or TCA  42 , with the pressure applied via the handle  46 . 
         [0050]    The handling substrate  42  may be made of semiconductor material, glass, ceramic, or other materials. The handling substrate  42  preferably has a coefficient of thermal expansion (“CTE”) less than 10*10 −6 /° C. or may be nearly matched to silicon with CTE of about 3 ppm. 
         [0051]    With reference to  FIGS. 2A and 2B , after the chip  44  is attached to the handle or TCA  42 , handle  46  is removed by using laser ablation to dissolve the adhesive attaching this handle to the chip. The chip may then be cleaned, for example by a chemical process. One or more chips  56  are then mounted on and attached to chip  44  by solder bumps  60 . A liquid glue underfill  62  is applied to device  52 , and the liquid adhesive, underfill or glue flows underneath chips  56 . 
         [0052]    With reference to  FIGS. 2B and 2C , chips  44 ,  56  are then detached from handle or TCA  42  and mounted on organic or LTCC substrate  64 . Solder bumps  66  may be used to attach the chips to the substrate. As shown in  FIG. 2D , a liquid glue underfill  70  is applied to device  52 , and the liquid glue flows underneath chip  44 . Any suitable liquid glue underfill procedure may be used. 
         [0053]      FIGS. 3A-3C  show another embodiment of the invention. In this embodiment, a stack of thin chips, such as less than about 20 to 200 um thickness each, is assembled on an organic or LTCC substrate. The process of  FIGS. 3A-3C  may be preferred for use with smaller x,y size dies such as but not limited to &lt;1 mm by &lt;1 mm, up to about 15 mm by 15 mm. 
         [0054]      FIG. 3A  shows a stack  102  of thin chips  104 ,  106  on organic or LTCC substrate  110 . The stack is assembled, one chip at a time, between the substrate and handle  112 . After each joining step or cycle, a chip is added to the stack, another chip, represented at  114 , can be added to the stack. 
         [0055]    To assemble the stack  102 , a first chip  104  is mounted on the substrate  110  and connected to the substrate by solder bumps  122  by thermal compression bonding. In this thermal compression bonding, solder bumps  122  are heated and pressure is applied to the solder bumps by applying pressure to handle wafer  112 . 
         [0056]    After the first chip  104  is attached, a second chip  106  is mounted on that first chip and connected to the first chip by solder bumps  126 . Again, thermal compression bonding may be used to connect the second chip  106  to the first chip  104  via solder bumps  126 . This process is repeated until the desired number of flat chips has been assembled, as shown in  FIG. 3B . 
         [0057]    After the desired number of chips has been assembled, a liquid adhesive or glue underfill process is applied to device  130  to fill the spaces between chips  104  and  106  and between the chip stack  102  and substrate  112 , as shown in  FIG. 3C . As an example, in this liquid glue underfill process, one glue  132  may be used to fill underneath chip  104 , between that chip and substrate  112 , and a second, different glue  134  may be used to fill underneath chip  106 , between that chip and chip  104 . 
         [0058]      FIGS. 4A-4D  show an embodiment of the invention similar to the embodiment shown in  FIGS. 3A-3C ; however, with the embodiment of  FIGS. 4A-4D , the chip stack is formed on a handle wafer or TCA and then transferred to an organic or LTCC substrate. The procedure of  FIGS. 4A-4D  may be preferred for use with larger x,y size dies such as but not limited to &gt;10 mm by 10 mm, to &gt;25 mm by &gt;30 mm. 
         [0059]      FIG. 4A  shows a stack  142  of thin chips  144 ,  146  on handle wafer or TCA wafer  150 . The stack is assembled, one chip at a time, between wafer  150  and handle  152 . After each time a chip is added to the stack, another chip, represented at  154 , can be added to the stack. 
         [0060]    To assemble the stack  142 , a first chip  144  is mounted on the handle wafer or TCA  150  and attached thereto by solder bumps  162  by thermal compression bonding. In this bonding process, solder bumps  162  are heated and pressure is applied to the solder bumps by applying pressure to handle wafer  152 . Handle wafer  152  also helps to keep the chips  144 ,  146  flat during this process. 
         [0061]    After the first chip  144  is attached, a second chip  146  is mounted on that first chip and attached to the first chip by solder bumps  166 . Thermal compression bonding may be used to attach the second chip  146  to the first chip  144  via solder bumps  166 . This process of adding chips to the stack is repeated until the desired number of flat chips has been assembled, as shown in  FIG. 4B . An adhesive or glue underfill  170  is applied to device  172 , and the liquid glue flows underneath handle  152  and chip  146 . Any suitable adhesive or glue underfill procedure may be used. 
         [0062]    When the desired number of flat chips has been assembled, the chip stack  142 , with upper handle  152 , is removed from handle wafer or TCA  150  and mounted on organic substrate or LTCC  174 , as shown in  FIG. 4C . Solder bumps  176  may be used to attach the chip stack  142  to the substrate  174 . With reference to  FIG. 4D , when chip stack  142  is mounted on substrate  174 , a liquid glue underfill  180  process is applied to device  172  to fill the space between the chip stack  142  and substrate  174 . 
         [0063]      FIGS. 5A-5D  illustrate a process similar to the method depicted in  FIGS. 1A-1D . With the process of  FIGS. 5A-5D , thermal reflow is used in place of thermal compression bonding. 
         [0064]      FIG. 5A  shows organic or LTCC substrate  212 , integrated circuit chip  214 , and handling wafer  216 . Chip  214  is connected to substrate  212  by solder bumps  220 , and, in particular, by a thermal reflow process. In this thermal reflow, solder bumps  220  are heated to attach chip  214  to substrate  212 . Handling wafer  216  is above chip  214 , and applies pressure to the chip to keep the chip flat. 
         [0065]    After the chip  214  is connected to substrate  212 , handle  216  is removed, producing the device  222  shown in  FIG. 5B . Handle  216  may be removed, for example, by laser ablation. More specifically, handle  216  is attached to chip  214  by an adhesive, and a laser it used to heat and to dissolve that adhesive. Handle  216  can then be removed from the chip  214 . The back of the chip may then be cleaned by, for example, a chemical process. 
         [0066]    As shown in  FIG. 5C , a liquid glue underfill  224  is applied to device  222 , and this liquid underfill flows underneath chip  214 . Any suitable liquid glue underfill procedure may be used. 
         [0067]    With reference to  FIG. 5D , one or more chips  226  are then mounted on flat chip  214 , and chips  226  may be connected to chip  214  by solder bumps  230 . A thermal reflow process may be used to heat the solder bumps  230  to attach chips  226  to chip  214 . A liquid glue underfill  232  may also be applied in which a liquid glue flows underneath chips  226 . 
         [0068]      FIGS. 6A-6D  show an embodiment of the invention similar to the embodiment illustrated in  FIGS. 2A-2D . In the embodiment of  FIGS. 6A-6D , thermal reflow is used rather than thermal compression boding to attach the IC dies to each other and to the substrate. 
         [0069]      FIG. 6A  shows a handle wafer or TCA  242 , an integrated circuit chip or die  244  and handle wafer  246 . Chip  244  is connected to handle wafer or TCA  242  by solder bumps  250 . Similar to the procedure shown in  FIG. 5A , thermal reflow may be used to attach the chip  244  to the wafer or TCA  242 . Pressure may be applied to upper handling wafer  246 , downward as shown in  FIG. 6A , to keep the chip  244  flat. 
         [0070]    With reference to  FIGS. 6A and 6B , after the chip  244  is attached to the handle or TCA  242 , upper handle  246  is removed by using laser ablation to dissolve the adhesive attaching the handle to the chip. The chip may then be cleaned, for example, by a chemical process. One or more chips  256  are mounted on chip  244 . Solder bumps  260  are used to attach chips  256  to chip  244 , and a thermal reflow may be used to heat the solder bumps  260  to attach chips  256  to chip  244 . An adhesive or glue underfill  262  is applied to device  252 , and the integrated adhesive or glue underfill flows underneath chips  256 . 
         [0071]    With reference to  FIGS. 6B and 6C , chips  244 ,  256  are then detached from handle or TCA  242  and mounted on organic or LTTC substrate  264 . Solder bumps  266  may be used to attaché the chips to this substrate, and a thermal reflow may be used to heat the solder bumps to attach the chips to substrate  264 . As shown in  FIG. 6D , a liquid glue underfill  266  is applied to device  252 , and the liquid glue flows underneath chip  244 . Any suitable liquid glue underfill procedure may be used. 
         [0072]      FIGS. 7A-7C  illustrate a further embodiment, similar to the embodiment shown in  FIGS. 3A-3C . With the embodiment of  FIGS. 7A-7C , thermal reflow is used to heat the solder bumps to attach the chips to each other. The process of  FIGS. 7A-7C , like the process of  FIGS. 3A-3C , is particularly well suited for assembling smaller x,y size dies. 
         [0073]    More specifically,  FIG. 7A  shows a stack  302  of chips  304 ,  306  on organic or LTCC substrate  310 . The stack is assembled, one chip at a time, between the substrate and handle  312 . After each time a chip is added to the stack, another chip, represented at  314 , can be added to the stack. 
         [0074]    To assemble the stack  302 , a first chip  304  is mounted on the substrate  310  and attached to the substrate by solder bumps  322  by thermal reflow. Pressure may be applied to the chip  304  via handle wafer  312  to keep the chip flat. 
         [0075]    After the first chip  304  is attached, a second chip  306  is mounted on that first chip and connected to the first chip by solder bumps  326 . A thermal reflow may be used to heat the solder bumps  326  to attach chip  306  to chip  304 . This process is repeated until the desired number of flat chips has been assembled, as shown in the device  330  in  FIG. 7B . 
         [0076]    After the chips have been assembled, an adhesive or glue underfill process is applied to fill the spaces between the chips  304  and  306  and between the chip stack  302  and substrate  312 , as shown in  FIG. 7C . In this liquid glue underfill process, one glue  332  may be used to fill underneath chip  304 , between that chip and substrate  312 , and a second, different glue  334  may be used to fill underneath chip  306 , between that chip and chip  304 . 
         [0077]      FIGS. 8A-8D  show another embodiment of the invention, and this embodiment is similar to the embodiment of  FIGS. 4A-4D . In the embodiment of  FIGS. 8A-8D , however, a plurality of chip stacks are formed on a substrate, and, in addition, thermal reflows, rather than thermal compression bonding, are used to attach the chips together. The procedure of  FIGS. 8A-8D , like the procedure of  FIGS. 4A-4D , is particularly well suited for forming stacks of larger x,y size dies. 
         [0078]      FIG. 8A  shows a plurality of stacks  342 A,  342 B,  342 C of flat chips formed on a bottom handle wafer  350 , and an upper handle wafer  352  is located on top of the chip stacks and extends over all the chip stacks. As shown in  FIG. 8A , stack  342 A is comprised of chips  344 A and  346 A, stack  342 B is comprised of chips  344 B and  346 B, and stack  432 C is comprised of chips  344 C and  346 C. In this embodiment, stacks  342 A,  342 B,  342 C are formed together, and each stack is formed one chip at a time. After each time a chip is added to a stack, another chip can be added to the stack. 
         [0079]    To assemble the stacks, a first chip in each stack is mounted on the handle wafer or TCA  350  and attached thereto by a group of the solder bumps  362  by a thermal reflow process. In this thermal reflow process, the group of the solder bumps  362  are heated and attach the chip to handle wafer or TCA  350 . Handle wafer  352  helps to keep these first chips flat during this process. 
         [0080]    After the first chip of each stack is attached to handle wafer or TCA  350 , a second chip of each stack is mounted on the first chip of each stack and attached to that first chip by a group of the solder bumps  366 . Thermal reflow is also used to attach these second chips to the first chips via these solder bumps, and as this is done, upper handle  352  helps to keep the chips flat. This process of adding chips to the stacks may be repeated until the desired number of flat chips has been assembled in each stack. 
         [0081]      FIG. 8B  shows one of the assembled stacks  342 A. With reference to  FIG. 8B , after the desired number of chips has been assembled in the stacks, a pre-applied solid adhesive or liquid glue underfill is applied to the stack, and the liquid glue  370  flows underneath handle wafer  352  and chip  346 A. Any suitable pre-applied adhesive or liquid glue underfill process or procedure may be used. 
         [0082]    With reference to  FIG. 8A-8C , the chip stack  342 A,  342 B and  342 C, with upper handle  352 , can be removed from handle wafer or TCA  350  and mounted on organic substrate or LTCC  374 . A thermal reflow process may be used to heat solder bumps  376  to use the solder bumps to attach the chip stacks to substrate  374 . With reference to  FIG. 8D , when each chip stack is mounted on substrate  374 , a liquid glue underfill  380  process is applied to the chip stack to fill the space between the chip stack and substrate  374 . 
         [0083]    The description of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or to limit the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to explain the principles and applications of the invention, and to enable others of ordinary skill in the art to understand the invention. The invention may be implemented in various embodiments with various modifications as are suited to a particular contemplated use.