Abstract:
A semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate electrode proximate the high-k dielectric layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is related to U.S. patent application Ser. No. 10/799,910, filed Mar. 12, 2004, which is incorporated herein by reference. 
     
    
     BACKGROUND  
       [0002]     As metal-oxide semiconductor field effect transistor (MOSFET) devices continue to advance, the thickness of the gate dielectric continues to decrease to maintain the desired control of the MOSFET devices. According to the International Technology Roadmap for Semiconductors (ITRS), an equivalent oxide thickness (EOT) of less than 15 Å is necessary to meet the requirement of sub-100 nm MOSFET devices. Using conventional SiO 2  as the gate material, it is difficult to keep scaling the thickness below 20 Å without having high tunneling leakage current through the gate. Thus, various other gate dielectric materials having a higher dielectric constant (k) than SiO 2  have been studied extensively. These materials are known as high-k materials. SiO 2  has a k value of 3.9 while the various other gate dielectric materials being studied have k values in the range of 10 to 80.  
         [0003]     The thickness of the gate dielectric required to control a MOSFET depends on the capacitance of the film. High-k material films and the thicknesses that would result may be compared to other high-k materials and SiO 2  using equivalent oxide thickness (EOT). For example, a high-k film with a k value of 20 may be about five times thicker than a SiO 2  film and still have the same control over a MOSFET. The thicker gate dielectric layer may reduce tunneling leakage current through the gate, enabling sub-100 nm MOSFET devices.  
       SUMMARY  
       [0004]     One embodiment of the present invention provides a semiconductor device. The semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate electrode proximate the high-k dielectric layer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.  
         [0006]      FIG. 1  is a diagram illustrating a cross-section of one embodiment of a metal-oxide semiconductor field effect transistor (MOSFET) cell, according to the present invention.  
         [0007]      FIG. 2  is a diagram illustrating a cross-section of one embodiment of a photoresist layer, a nitride layer, an oxide layer, and a substrate.  
         [0008]      FIG. 3  is a diagram illustrating a cross-section of one embodiment of a substrate including isolation regions.  
         [0009]      FIG. 4  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions and first material layer.  
         [0010]      FIG. 5  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions, first material layer, and second material layer.  
         [0011]      FIG. 6  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions, first material layer, second material layer, and third material layer.  
         [0012]      FIG. 7  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions, first material layer, second material layer, third material layer, and fourth material layer.  
         [0013]      FIG. 8   a  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions, first through fourth material layers, and a fifth material layer.  
         [0014]      FIG. 8   b  is a diagram illustrating a cross-section of one embodiment of multiple material layers.  
         [0015]      FIG. 9  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions, high-k dielectric layer, and a gate electrode layer.  
         [0016]      FIG. 10  is a diagram illustrating a cross-section of one embodiment of a substrate with isolation regions, high-k dielectric layer, and gate electrode layer after etching.  
         [0017]      FIG. 11  is a diagram illustrating one embodiment of implantation of a cross-section of the substrate to form source and drain extension regions.  
         [0018]      FIG. 12  is a diagram illustrating a cross-section of one embodiment of an oxide layer on a substrate with isolation regions, high-k dielectric layer, and gate electrode layer.  
         [0019]      FIG. 13  is a diagram illustrating a cross-section of one embodiment of an oxide layer on a substrate with isolation regions, high-k dielectric layer, and gate electrode layer after etching the oxide layer to form spacers.  
         [0020]      FIG. 14  is a diagram illustrating one embodiment of implantation of a cross-section of the substrate to form source and drain regions. 
     
    
     DETAILED DESCRIPTION  
       [0021]      FIG. 1  is a diagram illustrating a cross-section of one embodiment of a metal-oxide semiconductor field effect transistor (MOSFET) cell  40 , according to the present invention. Transistor cell  40  is one of a plurality of transistor cells in a MOSFET device. In one embodiment, transistor cell  40  is used in a memory device. Transistor cell  40  includes substrate  42 , isolation regions  44 , source  46 , channel  48 , and drain  50 . Transistor cell  40  also includes high-k dielectric layer  54 , gate electrode  60 , and spacers  52 . In one embodiment, high-k dielectric layer  54  is formed by annealing two or more materials or two or more layers of materials to form a single high-k dielectric layer comprising a mixture of the materials or material layers. In one embodiment, one or more of the materials includes a high-k material and one or more of the materials includes a metal. The annealing process, in one embodiment, results in a high-k dielectric layer incorporated with N and having a high-k value greater than the individual k values of each material in the mixture. Desired memory cell  40  characteristics, including equivalent oxide thickness (EOT) and N incorporation, are obtained by selecting the materials, number of layers, and thicknesses of each layer.  
         [0022]     Substrate  42  is a silicon substrate or other suitable substrate. Isolation regions  44  are trenches etched into substrate  42  that have been filled with an insulating material, such as SiO 2  or other suitable insulator with a dielectric constant less than four, to insulate transistor cell  40  from adjacent transistor cells. Source  46  and drain  50  are doped, for example, with arsenic, phosphorous, boron or other suitable material, depending upon the desired transistor cell characteristics, using a self-aligning ion implantation process in substrate  42  or other suitable process. Channel  48  is between source  46  and drain  50 .  
         [0023]     High-k dielectric layer  54  is centered over channel  48  and includes a mixture of two or more high-k dielectric materials and metals. The high-k dielectric materials include Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST (Ba (a-x) Sr x TiO 3 ), PST (PbSc x Ta (1-a) O 3 ), PZN (PbZn x Nb (1-x) O 3 ), PZT (PbZr x Ti (1-x) O 3 ), PMN (PbMg x Nb (1-x) O 3 ), or other suitable high-k materials. The metals include TiN, HfN, TaN, ZrN, LaN, or other suitable metals. High-k dielectric layer  54  is deposited on substrate  42 . High-k dielectric layer  54  provides the gate dielectric for transistor cell  40 .  
         [0024]     Gate electrode layer  60  is deposited on high-k dielectric layer  54  and includes aluminum, polysilicon, or other suitable conductive material (i.e., TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, TiSiN, etc). Gate electrode layer  60  provides the gate electrode for transistor cell  40 .  
         [0025]     Spacers  52  are deposited on the sides of gate electrode layer  60 , high-k dielectric layer  54 , and substrate  42  and include SiO 2 , Si 3 N 4 , TEOS or other suitable dielectric material. Spacers  52  isolate gate electrode  60  and high-k dielectric layer  54  from source  46  and drain  50 .  
         [0026]     Using a high-k dielectric layer  54  improves the high-k quality for the gate dielectric. High-k dielectric layer  54  provides an equivalent oxide thickness (EOT) that allows increased performance and reduced transistor cell size while not increasing tunneling leakage current through the gate. Tunneling leakage current through the gate is kept to a desired level as high-k materials improve control over transistor cell devices. The improved control comes without reducing the thickness of the gate dielectric, as required if using SiO 2  for the gate dielectric.  
         [0027]     Of the high-k materials, HfO 2  films are compatible with both polysilicon and metal gate electrodes. HfO 2 , however, has a low immunity to oxygen and boron diffusion. Incorporating N or another suitable species into HfO 2  films reduces impurity diffusion, increases crystallization temperature, improves thermal stability, etc.  
         [0028]      FIGS. 2-14  are diagrams illustrating an exemplary process for fabricating one embodiment of transistor cell  40 . In the exemplary process, transistor cell  40  is fabricated from substrate  42 , high-k dielectric layer  54 , gate electrode  60 , and spacers  52 .  
         [0029]      FIG. 2  is a diagram illustrating a cross-section of one embodiment of a photoresist layer  74 , a nitride layer  72 , an oxide layer  70 , and substrate  42 . Isolation regions  44  can be formed using a shallow trench isolation (STI) process. Oxide layer  70  is formed on substrate  42 . Nitride layer  72  is formed on oxide layer  70  and photoresist layer  74  is formed on nitride layer  72 .  
         [0030]     Oxide layer  70  is grown or deposited on silicon substrate layer  42 . Nitride layer  72  is deposited on oxide layer  70  using chemical vapor deposition (CVD) or other suitable deposition method. Photoresist layer  74  is spin-coated on nitride layer  72 . A mask is used to expose portions  74   a  of photoresist layer  74  and prevent portions  74   b  of photoresist layer  74  from being exposed. Photoresist layer  74  is exposed to high intensity ultra-violet (UV) light through the mask to expose portions  74   a  of photoresist layer  74 . Portions  74   a  of photoresist layer  74  define where isolation regions  44  will be formed in substrate  42 .  
         [0031]     The exposed portions  74   a  of photoresist are removed to leave unexposed portions  74   b  of photoresist on nitride layer  72 . The newly exposed nitride layer  72  portions, the oxide layer  70  portions beneath the newly exposed nitride layer  72  portions, and portions of substrate  42  beneath the newly exposed nitride layer  72  portions are etched away using wet etching, dry etching, or other suitable etching process. After etching, the newly formed trenches are filled with oxide using chemical vapor deposition (CVD) or other suitable deposition technique.  
         [0032]      FIG. 3  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44  formed in the substrate from the etching process previously described and illustrated in  FIG. 2 . In addition, the remaining nitride layer  72  and oxide layer  70  are removed from substrate  42 . Depending upon the desired characteristics for the transistor cell device, substrate  42  can be implanted to form n-wells and/or p-wells and V tn  and/or V tp  adjust implants can be performed.  
         [0033]      FIG. 4  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44  and a first material layer  54   a.  A pre-gate treatment is used to clean and treat the surface of substrate  42 . In one embodiment, the pre-gate treatment leaves a layer including SiO 2 , SiON, or other material based upon the pre-gate treatment used. In one embodiment, the pre-gate treatment of substrate  42  does not leave a pre-gate material layer on substrate  42 . In this case, first material layer  54   a  is deposited on substrate  42 . In one embodiment, first material layer  54   a  has a thickness within the range of 1 Å to 30 Å.  
         [0034]     First material layer  54   a  includes one or more of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, LaN, or other suitable high-k dielectric material or metal. First material layer  54   a  is deposited on substrate  42  using atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVD), or other suitable deposition technique. In one embodiment, where first material layer  54   a  includes more than one of the above listed materials, the materials are simultaneously deposited.  
         [0035]     For example, in one embodiment, HfO 2 , TiO 2 , Ta 2 O 5 , TaN, or TiN is deposited on substrate  42 . In another embodiment, HfO 2 , TiO 2 , and Ta 2 O 5 , or HfO 2 , TiN, and TaN are simultaneously deposited on substrate  42 . In another embodiment, TiO 2 , and Ta 2 O 5 , or TiN and TaN, are simultaneously deposited on substrate  42 . In another embodiment, HfO 2  and Ta 2 O 5 , TiO 2 , TiN, or TaN are simultaneously deposited on substrate  42 . In other embodiments, other combinations of materials for first material layer  54   a  are used.  
         [0036]      FIG. 5  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , first material layer  54   a,  and second material layer  54   b.  Second material layer  54   b  includes one or more of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, LaN, or other suitable high-k dielectric material or metal. Second material layer  54   b  is deposited on first material layer  54   a  using ALD, MOCVD, PVD, JVD, or other suitable deposition technique, as described with reference to first material layer  54   a.  In one embodiment, second material layer  54   b  has a thickness within the range of 1 Å to 30 Å.  
         [0037]     In one embodiment, first material layer  54   a  comprises HfO 2 , and second material layer  54   b  comprises Ta 2 O 5 , TiO 2  TiN, or TaN. In another embodiment, first material layer  54   a  comprises Ta 2 O 5 , TiO 2 , TiN, or TaN and second material layer  54   b  comprises HfO 2 . In other embodiments, other combinations of materials for first material layer  54   a  and second material layer  54   b  are used.  
         [0038]      FIG. 6  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , first material layer  54   a,  second material layer  54   b,  and third material layer  54   c.  Third material layer  54   c  includes one or more of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, LaN, or other suitable high-k dielectric material or metal. Third material layer  54   c  is deposited on second material layer  54   b  using ALD, MOCVD, PVD, JVD, or other suitable deposition technique, as described with reference to first material layer  54   a.  In one embodiment, third material layer  54   c  has a thickness within the range of 1 Å to 30 Å.  
         [0039]     In one embodiment, third material layer  54   c  comprises the material or materials included in first material layer  54   a.  In another embodiment, third material layer  54   c  comprises a different material or materials than the material or materials included in first material layer  54   a  and/or second material layer  54   b.  For example, in one embodiment, first material layer  54   a  comprises HfO 2 , second material layer  54   b  comprises Ta 2 O 5  or TaN, and third material layer  54   c  comprises TiO 2  or TiN. In other embodiments, other combinations of materials for first material layer  54   a,  second material layer  54   b,  and third material layer  54   c  are used.  
         [0040]      FIG. 7  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , first material layer  54   a,  second material layer  54   b,  third material layer  54   c,  and fourth material layer  54   d.  Fourth material layer  54   d  includes one or more of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, LaN, or other suitable high-k dielectric material or metal. Fourth material layer  54   d  is deposited on third material layer  54   c  using ALD, MOCVD, PVD, JVD, or other suitable deposition technique, as described with reference to first material layer  54   a.  In one embodiment, fourth material layer  54   d  has a thickness within the range of 1 Å to 30 Å.  
         [0041]     In one embodiment, fourth material layer  54   d  comprises the material or materials included in second material layer  54   b,  and third material layer  54   c  comprises the material or materials included in first material layer  54   a.  For example, in one embodiment, first material layer  54   a  and third material layer  54   c  comprise HfO 2 , and second material layer  54   b  and fourth material layer  54   d  comprise one or more of Ta 2 O 5 , TiO 2 , TaN, and TiN. In other embodiments, other combinations of materials for first material layer  54   a,  second material layer  54   b,  third material layer  54   c,  and fourth material layer  54   d  are used.  
         [0042]      FIG. 8   a  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , first material layer  54   a,  second material layer  54   b,  third material layer  54   c,  fourth material layer  54   d,  and fifth material layer  54   e.  Fifth material layer  54   e  includes one or more of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, LaN, or other suitable high-k dielectric material or metal. Fifth material layer  54   e  is deposited on fourth material layer  54   d  using ALD, MOCVD, PVD, JVD, or other suitable deposition technique, as described with reference to first material layer  54   a.  In one embodiment, fifth material layer  54   e  has a thickness within the range of 1 Å to 30 Å.  
         [0043]     In one embodiment, fifth material layer  54   e  comprises the material or materials included in first material layer  54   a  and third material layer  54   c,  and fourth material layer  54   d  comprises the material or materials included in second material layer  54   b.  In another embodiment, fifth material layer  54   e  comprises the material or materials included in second material layer  54   b,  and fourth material layer  54   d  comprises the material or materials included in first material layer  54   a.  For example, in one embodiment, first material layer  54   a,  third material layer  54   c,  and fifth material layer  54   e,  comprise HfO 2 , and second material layer  54   b  and fourth material layer  54   d  comprise one or more of Ta 2 O 5 , TiO 2 , TaN, and TiN. In other embodiments, other combinations of materials for first material layer  54   a,  second material layer  54   b,  third material layer  54   c,  fourth material layer  54   d,  and fifth material layer  54   e  are used.  
         [0044]      FIG. 8   b  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  42  and multiple material layers  54   a - 54 ( n ), where n is any number greater than one. Each material layer  54   a - 54 ( n ) includes one or more of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, LaN, or other suitable high-k dielectric material or metal. Each material layer  54   a - 54 ( n ) is deposited using ALD, MOCVD, PVD, JVD, or other suitable deposition technique. In one embodiment, the combined thickness of material layers  54   a - 54 ( n ) is within the range of 20 Å to 100 Å.  
         [0045]     In one embodiment, material layers  54 ( n - 1 ) and  54 ( n ) are repeating layers of materials deposited in first material layer  54   a  and second material layer  54   b,  respectively, or are part of any suitable repeating pattern of layers based on the desired characteristics for transistor cell  40 . In other embodiments, other combinations of materials for material layers  54   a - 54 ( n ) are used.  
         [0046]     With the desired layers and combinations of layers deposited on substrate  42 , layers  54   a - 54 ( n ) are annealed to form a single high-k dielectric layer  54 . Single high-k dielectric layer  54  comprises a mixture of all the materials deposited in material layers  54   a - 54 ( n ). In one embodiment, material layers  54   a - 54 ( n ) are annealed within the range of 400° C. to 900° C. Each material layer  54   a - 54 ( n ) is deposited in a thickness such that after the annealing process each material layer  54   a - 54 ( n ) is no longer distinct from the other material layers  54   a - 54 ( n ). Material layers  54   a - 54 ( n ) all blend and mix together to become a single layer. In the case of a metal layer, such as TiN, HfN, TaN, ZrN, or LaN, the layer is completely oxidized to incorporate the N into dielectric layer  54 . For example, in one embodiment, where one or more of material layers  54   a - 54 ( n ) include TiN, HfN, TaN, ZrN, or LaN, high-k dielectric layer  54  becomes incorporated with N when the TiN, HfN, TaN, ZrN, or LaN layer or layers are oxidized during the annealing process. Incorporation of N into high-k dielectric layer  54  improves the performance characteristics of memory cell  40 . In one embodiment, where material layers  54   a - 54 ( n ) comprise HfO 2 , TaN, and TiN, high-k dielectric layer  54  comprises HfTaTiO x  incorporated with N after annealing.  
         [0047]      FIG. 9  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , high-k dielectric layer  54  after annealing, and gate electrode layer  60 . Gate electrode layer  60  comprises aluminum, polysilicon, or other suitable conductive material. Gate electrode layer  60  is deposited on high-k dielectric layer  54  using CVD or other suitable deposition technique.  
         [0048]     High-k dielectric layer  54  after annealing is a single layer comprising a mixture of all the materials deposited in material layer  54   a  of  FIG. 4 , material layers  54   a  and  54   b  of  FIG. 5 , material layers  54   a - 54   c  of  FIG. 6 , material layers  54   a - 54   d  of  FIG. 7 , material layers  54   a - 54   e  of  FIG. 8   a,  or material layers  54   a - 54 ( n ) of  FIG. 8   b.  In one embodiment, high-k dielectric layer  54  has a k value greater than the individual k values of each of the materials deposited to form high-k dielectric layer  54 . In one embodiment, high-k dielectric layer  54  has a k value within the range of 20 to 70.  
         [0049]      FIG. 10  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , high-k dielectric layer  54 , and gate electrode layer  60  after portions of gate electrode layer  60  and high-k dielectric layer  54  have been etched away. A photoresist and etching process is used to remove the unwanted portions.  
         [0050]      FIG. 11  is a diagram illustrating a cross-section of one embodiment of ion implantation  10  in a self-aligned process to form source extension region  46  and drain extension region  50 . Substrate  42  is implanted with a species to form source extension region  46  and drain extension region  50 . The implant species includes arsenic, phosphorous, boron, or other suitable species based upon the desired characteristics of transistor cell  40 , such as whether transistor cell  40  is PMOS or NMOS.  
         [0051]      FIG. 12  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , high-k dielectric layer  54 , gate electrode layer  60 , and oxide layer  53 . Oxide layer  53  is deposited on gate electrode layer  60 , the sides of high-k dielectric layer  54 , and on substrate  42 . Oxide layer  53  includes SiO 2  or other suitable material. Oxide layer  53  is deposited using CVD or other suitable deposition technique.  
         [0052]      FIG. 13  is a diagram illustrating a cross-section of one embodiment of substrate  42  with isolation regions  44 , high-k dielectric layer  54 , gate electrode layer  60 , and oxide layer  53  after etching to form spacers  52 . A photoresist and etching process is used to remove unwanted portions of oxide layer  53  to form spacers  52 .  
         [0053]      FIG. 14  is a diagram illustrating one embodiment of ion implantation  120  of a cross-section of substrate  42  to form source  46  and drain  50 . Substrate  42  is implanted with a species to form source  46  and drain  50 . The implant species includes arsenic, phosphorous, boron, or other suitable species based upon the desired characteristics of transistor cell  40 , such as whether transistor cell  40  is a PMOS transistor cell or an NMOS transistor cell.