Abstract:
A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure. A first procedure is performed to determine if a first current flow exists between a first conductive layer formed on the first FET and a second conductive layer formed on the first FET. A second procedure is performed to determine if a second current flow exists between a third conductive layer formed the second FET and a fourth conductive layer formed on the second FET. A determination is made from combining results of the first procedure and results of the second procedure that the first FET and the second FET each comprise a specified type of defect.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a method for determining a defect type on a semiconductor device. 
   BACKGROUND OF THE INVENTION 
   Determining potential flaws on an electrical device is typically inaccurate. Inaccurate determinations may cause the semiconductor device to fail prematurely. Accordingly, there exists a need in the art to overcome at least one of the deficiencies and limitations described herein above. 
   SUMMARY OF THE INVENTION 
   The present invention provides a method comprising: 
   providing a semiconductor wafer comprising a first group of field effect transistors (FET) and a second group of FETS, said first group of FETS comprising a first FET, said second group of FETS comprising a second FET, said first FET comprising a first gate structure, a first source/drain structure, and a first sidewall spacer structure, said first gate structure comprising a first gate electrode formed over a first gate insulator, said first source/drain structure comprising a first source and a first drain, said first source extending laterally in a first direction such that said first gate electrode is located directly over a portion of said first source, said first drain extending laterally in a second direction opposite said first direction such that said first gate electrode is located directly over a portion of said first drain, said second FET comprising a second gate structure, a second source/drain structure, and a second sidewall spacer structure, said second gate structure comprising a second gate electrode formed over a second gate insulator, said second source/drain structure comprising a second source and a second drain, said second gate structure not located directly over any portion of said second source or any portion of said second drain; 
   performing a first procedure to determine if a first current flow exists between a first conductive layer formed over said first gate electrode and a second conductive layer formed over said first source or said first drain; 
   performing a second procedure to determine if a second current flow exists between a third conductive layer formed over said second gate electrode and a fourth conductive layer formed over said second source or said second drain; and 
   combining results of said first procedure and results of said second procedure to determine if said first FET and said second FET each comprise no defect, a gate insulator defect or a missing sidewall spacer defect. 
   The present invention provides a structure comprising: 
   a semiconductor wafer; 
   a first FET formed on said semiconductor wafer, said first FET comprising said first FET comprising a first gate structure, a first source/drain structure, and a first sidewall spacer structure, said first gate structure comprising a first gate electrode formed over a first gate insulator, said first source/drain structure comprising a first source and a first drain, said first source extending laterally in a first direction such that said first gate electrode is located directly over a portion of said first source, said first drain extending laterally in a second direction opposite said first direction such that said first gate electrode is located directly over a portion of said first drain; 
   a first conductive layer formed over said first gate electrode; 
   a second conductive layer formed over said first source; 
   a second FET formed on said semiconductor wafer, said second FET comprising a second gate structure, a second source/drain structure, and a second sidewall spacer structure, said second gate structure comprising a second gate electrode formed over a second gate insulator, said second source/drain structure comprising a second source and a second drain, said second gate structure not located directly over any portion of said second source or any portion of said second drain; 
   a third conductive layer formed over said second gate electrode; 
   a fourth conductive layer formed over said second source; 
   a first voltage source electrically connected to said first conductive layer, said first voltage source configured to generate a first voltage; 
   a first detection circuit electrically connected to said first voltage source and said second conductive layer, said first detection circuit configured to detect if a first current flow exists between said first conductive layer and said second conductive layer; 
   a second voltage source electrically connected to said third conductive layer, said second voltage source configured to generate a second voltage; and 
   a second detection circuit electrically connected to said second voltage source and said fourth conductive layer, said second detection circuit configured to detect if a second current flow exists between said third conductive layer and said fourth conductive layer. 
   The present invention provides a structure comprising: 
   a semiconductor wafer; 
   a first FET formed on said semiconductor wafer, said first FET comprising said first FET comprising a first gate structure, a first source/drain structure, and a first sidewall spacer structure, said first gate structure comprising a first gate electrode formed over a first gate insulator, said first source/drain structure comprising a first source and a first drain, said first source extending laterally in a first direction such that said first gate electrode is located directly over a portion of said first source, said first drain extending laterally in a second direction opposite said first direction such that said first gate electrode is located directly over a portion of said first drain; 
   a first conductive layer formed over said first gate electrode; 
   a second conductive layer formed over said first drain; 
   a second FET formed on said semiconductor wafer, said second FET comprising a second gate structure, a second source/drain structure, and a second sidewall spacer structure, said second gate structure comprising a second gate electrode formed over a second gate insulator, said second source/drain structure comprising a second source and a second drain, said second gate structure not located directly over any portion of said second source or any portion of said second drain; 
   a third conductive layer formed over said second gate electrode; 
   a fourth conductive layer formed over said second drain; 
   a first voltage source electrically connected to said first conductive layer, said first voltage source configured to generate a first voltage; 
   a first detection circuit electrically connected to said first voltage source and said second conductive layer, said first detection circuit configured to detect if a first current flow exists between said first conductive layer and said second conductive layer; 
   a second voltage source electrically connected to said third conductive layer, said second voltage source configured to generate a second voltage; and 
   a second detection circuit electrically connected to said second voltage source and said fourth conductive layer, said second detection circuit configured to detect if a second current flow exists between said third conductive layer and said fourth conductive layer. 
   The present invention advantageously provides a simple structure and associated method for determining potential flaws on an electrical device. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a cross sectional view of a test portion of a semiconductor structure, in accordance with embodiments of the present invention. 
       FIG. 2  depicts an alternative to  FIG. 1 , in accordance with embodiments of the present invention. 
       FIG. 3  depicts a first alternative to  FIG. 2 , in accordance with embodiments of the present invention. 
       FIG. 4  depicts a second alternative to  FIG. 2 , in accordance with embodiments of the present invention. 
       FIG. 5  illustrates a top view of a test portion of a semiconductor structure, in accordance with embodiments of the present invention. 
       FIG. 6  depicts an alternative to  FIG. 5 , in accordance with embodiments of the present invention. 
       FIG. 7  illustrates a flowchart describing an algorithm used to determine FET defect types for FETs, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  illustrates a cross sectional view of a test portion  4 A of a semiconductor structure  2 A, in accordance with embodiments of the present invention. Semiconductor structure  2 A may comprise any type of semiconductor structure including, inter alia, a semiconductor wafer, a semiconductor chip, etc. Semiconductor structure  2 A comprises a first field effect transistor (FET)  5 A and a second FET  5 B. 
   First FET  5 A comprises a semiconductor substrate  18 A, a source structure  14 A, a drain structure  14 B, a conductive layer  15 A, a conductive layer  15 B, a conductive layer  15 C, a gate oxide layer  12 A, a gate structure  10 A, a sidewall spacer  8 A, and a sidewall spacer  8 B. Source structure  14 A and drain structure  14 B may be referred to as a source/drain structure. Conductive layer  15 A,  15 B, and  15 C may comprise any type of conductive layer including, inter alia, a silicide layer, etc. Source structure  14 A extends laterally such that a portion  11 A of source structure  14 A is located below gate structure  10 A. Drain structure  14 B extends laterally such that a portion  11 B of drain structure  14 B is located below gate structure  10 A. 
   Second FET  5 B comprises a semiconductor substrate  18 B, a source structure  14 C, a drain structure  14 D, a conductive layer  15 D, a conductive layer  15 E, a conductive layer  15 F, a gate oxide layer  12 B, a gate structure  10 B, a sidewall spacer  8 A, and a sidewall spacer  8 B. Source structure  14 C and drain structure  14 D may be referred to as a source/drain structure. Conductive layer  15 D,  15 E, and  15 F may comprise any type of conductive layer including, inter alia, a silicide layer, etc. In contrast to FET  5 A, FET  5 B comprises a source structure  14 C that does not extend laterally and therefore no portion of source structure  14 C is located below gate structure  10 B. Additionally, drain structure  14 D does not extend laterally and therefore no portion of drain structure  14 D is located below gate structure  10 B. Semiconductor device  2 A comprises additional functional FETs (i.e., FETs used on a functional portion of semiconductor device  2 A and not used for test purposes) equivalent to FET  5 A and  5 B. FET  5 A and FET  5 B are used to determine FET defects (e.g., no defects, gate oxide defects, missing spacer defects, etc) for all of the FETs on semiconductor device  2 A during a manufacturing process as described, infra, with respect to  FIGS. 2 and 3 . 
     FIG. 2  depicts an alternative to  FIG. 1  illustrating a cross-sectional view of a test portion  4 B of a semiconductor structure  2 B, in accordance with embodiments of the present invention. Semiconductor structure  2 B comprises a FET  5 C and a FET  5 D. In contrast to semiconductor structure  2 A of  FIG. 1 , semiconductor structure  2 B of  FIG. 2  comprises FETs (i.e., FET  5 C,  5 D, and all FETs of semiconductor device  2 B) that each have a gate oxide defect  24 A (i.e., a defect extending through a gate oxide (e.g., gate oxide  12 A)). Gate oxide defect  24 A (i.e., in FET  5 C and all other similar FETS comprising a source/drain structure extending laterally below a gate structure on semiconductor structure  2 B) comprises a conductive material that causes an unwanted short circuit between gate structure  10 A and a source structure  14 A of FET  5 C. Although gate oxide defect  24 A in FET  5 C is located between gate structure  10 A and source structure  14 A, note that gate oxide defect  24 A could have alternatively formed between gate structure  10 A and a drain structure  14 B (and between all gate and drain structures on all FETs on semiconductor structure  2 B). Gate oxide defect  24 A may have been formed accidentally during a manufacturing process. Gate oxide defect  24 A in FET  5 D and all other similar FETS comprising a source/drain structure that does not extend laterally below a gate structure on semiconductor structure  2 B does not form a short between a gate structure  10 B and a source structure  14 C (or drain structure  14 D) because the source/drain structure does not extend laterally below a gate structure. Placing FET  5 C and  5 D (i.e., comprising different types of source/drain structures) on semiconductor device  2 B enables detection of different types of FET defects. Additionally, FET  5 C and  5 D (i.e., comprising different types of source/drain structures) enable distinguishing different types of FET defects from each other (e.g., gate oxide defects  24 A as opposed to another type of FET defect such as a missing spacer defect) as described, infra. 
   In order to distinguish different types of FET defects from each other, a voltage  20 A (e.g., from a voltage source such, inter alia, as a battery, a power supply, etc) is applied between conductive layer  15 A and  15 C on FET  5 C and a current measurement device  22 A (e.g., a voltage divider) is placed between a voltage source supplying voltage  20 A and conductive layer  15 A. Additionally, a voltage  20 B (e.g., from a voltage source such, inter alia, as a battery, a power supply, etc) is applied between conductive layer  15 D and  15 F on FET  5 D and a current measurement device  22 B (e.g., a voltage divider) is placed between a voltage source supplying voltage  20 B and conductive layer  15 D. When voltage  20 A is applied to FET  5 C, a closed circuit is formed by gate oxide defect  24 A and a current is measured by current measurement device  22 A (i.e., voltage  20 A is conducted from a voltage source through conductive layer  15 C, gate structure  10 A, gate defect  24 A, source structure  14 A, conductive layer  15 A, current measurement device  22 A, and back to the voltage source). Conversely, when voltage  20 B is applied to FET  5 D, source structure  14 C (i.e., without a lateral portion extending below drain structure  10 B) causes an open circuit (i.e., prevents a closed circuit formed by gate oxide defect  24 A because semiconductor substrate  15 B comprises a non-conductive material) and therefore a current is not measured by current measurement device  22 B. By applying the aforementioned voltages to FETS  5 C and  5 D and measuring a current value between conductive layers  15 A and  15 C (current flow existing) and between conductive layers  15 D and  15  F (no current flow existing), one is able to determine that FET  5 C, FET  5 D, and all of the other functional FETS located on semiconductor structure  2 B each comprise a gate oxide defect (i.e., current flow is measured on FET  5 C but not on FET  5 D). 
     FIG. 3  depicts a first alternative to  FIG. 2  illustrating a cross-sectional view of a test portion  4 C of a semiconductor structure  2 C, in accordance with embodiments of the present invention. Semiconductor structure  2 C comprises a FET  5 E and a FET  5 F. In contrast to semiconductor structure  2 B of  FIG. 2 , semiconductor structure  2 C of  FIG. 3  comprises FETs (i.e., FET  5 E,  5 F, and all FETs of semiconductor device  2 C) that do not comprise a gate oxide defect but that are each missing a sidewall spacer (i.e., spacer  8 A from  FIGS. 1 and 2  is missing). During a manufacturing process, the missing side wall spacer allows a single conductive layer  15 G (e.g., silicide) to form over and down a side surface of gate structure  10 A and over source structure  14 A. Additionally,  FIG. 3  illustrates a missing side wall spacer (i.e., spacer  8 A in  FIGS. 1 and 2 ) allowing a single conductive layer  15 G (e.g., silicide) to form over and down a side surface of gate structure  10 B and over source structure  14 C.  FIG. 3  could alternatively comprise a different missing sidewall spacer (e.g., sidewall spacer  8 B of  FIGS. 1 and 2 ) thereby allowing a single conductive layer (e.g., silicide) to form over and down a side surface of gate structure  10 A and over source structure  14 B and over and down a side surface of gate structure  10 B and over source structure  14 D. The missing sidewall spacer may have been caused accidentally during a manufacturing process. The single conductive layer  15 G (i.e., in FET  5 E and  5 F and all other similar FETS on semiconductor structure  2 C) causes a short circuit between each gate structure and each source structure. 
   Placing FET  5 E and  5 F (i.e., comprising different types of source/drain structures) on semiconductor device  2 C enables detection of different types of FET defects. Additionally, FET  5 E and  5 F (i.e., comprising different types of source/drain structures) enable distinguishing different types of FET defects from each other (e.g., a missing spacer defect as opposed to another type of FET defect such as gate oxide defects) as described, infra. 
   As with the procedure described with reference to  FIG. 2 , a voltage  20 A (e.g., from a voltage source such, inter alia, as a battery, a power supply, etc) is applied between portion  31 A and  31 B of conductive layer  15 G on FET  5 E and a current measurement device  22 A (e.g., a voltage divider) is placed between a voltage source supplying voltage  20 A and portion  31 B of conductive layer  15 G. Additionally, a voltage  20 B (e.g., from a voltage source such, inter alia, as a battery, a power supply, etc) is applied between portion  31 A and  31 B of conductive layer  15 G on FET  5 F and a current measurement device  22 B (e.g., a voltage divider) is placed between a voltage source supplying voltage  20 B and portion  31 B of conductive layer  15 G. When voltage  20 A is applied to FET  5 E, a closed circuit is formed by conductive layer  15 G and a current is measured by current measurement device  22 A (i.e., voltage  20 A is conducted from a voltage source through conductive layer  15 G, current measurement device  22 A, and back to the voltage source). Likewise, when voltage  20 B is applied to FET  5 F, a closed circuit is formed by conductive layer  15 G and a current is measured by current measurement device  22 B (i.e., voltage  20 B is conducted from a voltage source through conductive layer  15 G, current measurement device  22 B, and back to the voltage source). By applying the aforementioned voltages to FETS  5 E and  5 F and measuring a current value between conductive portions  31 A and  31 B of conductive layer  15   g  (i.e., current flow existing), one is able to determine that FET  5 E, FET  5 F, and all of the other functional FETS located on semiconductor structure  2 C each comprise a missing sidewall spacer. 
   Therefore, by placing two different style FETS (i.e., some FETS comprising source/drain structures extending laterally below a gate structure as illustrated by FETS  5 A,  5 C, and  5 E and some FETS comprising source/drain structures that do not extend laterally below a gate structure as illustrated by FETS  5 B,  5 D, and  5 F) one is able to determine if FETS on a semiconductor structure comprise a gate oxide defect (i.e., current flow only on one type of FET) or a missing sidewall spacer defect (i.e., current flow only on both types of FETS). 
     FIG. 4  depicts a second alternative to  FIG. 2  illustrating a cross-sectional view of a test portion  4 D of a semiconductor structure  2 D, in accordance with embodiments of the present invention. Semiconductor structure  2 D comprises a FET  5 G and a FET  5 H. In contrast to semiconductor structure  2 B of  FIG. 2 , semiconductor structure  2 D of  FIG. 4  does not comprise any defect. 
   As with the procedure described with reference to  FIG. 2 , a voltage  20 A (e.g., from a voltage source such, inter alia, as a battery, a power supply, etc) is applied between conductive layer  15 C on FET  5 G and a current measurement device  22 A (e.g., a voltage divider) is placed between a voltage source supplying voltage  20 A and conductive layer  15 A. Additionally, a voltage  20 B (e.g., from a voltage source such, inter alia, as a battery, a power supply, etc) is applied between conductive layer  15 F on FET  5 H and a current measurement device  22 B (e.g., a voltage divider) is placed between a voltage source supplying voltage  20 B and conductive layer  15 D. When voltage  20 A is applied to FET  5 G, an open circuit is detected and no current is measured by current measurement device  22 A. Likewise, when voltage  20 B is applied to FET  5 H, an open circuit is detected and no current is measured by current measurement device  22 B. By applying the aforementioned voltages to FETS  5 G and  5 H and measuring a current values between conductive layers, one is able to determine that FET  5 G, FET  5 H, and all of the other functional FETS located on semiconductor structure  2 D each comprise no defects. 
   Therefore, by placing two different style FETS (i.e., some FETS comprising source/drain structures extending laterally below a gate structure as illustrated by FET  5 G and some FETS comprising source/drain structures that do not extend laterally below a gate structure as illustrated by FETS  5 H) one is able to determine that FETS on a semiconductor structure do not comprise any defects. 
     FIG. 5  illustrates a top view of a test portion of a semiconductor structure, in accordance with embodiments of the present invention. The test portion illustrated in  FIG. 4  is applicable to any of semiconductor structures  2 A . . .  2 C. A circuit  34 A illustrated in  FIG. 4  comprises a plurality of FETS  5 A (i.e., source structures  14 A) electrically connected to a voltage source  21 A and a voltage divider circuit  35 A and a plurality of FETS  5 B (i.e., source structures  14 C) electrically connected to a voltage source  21 B and a voltage divider circuit  35 B. Circuit  34 A provides a means for identification of systematic defects that are preferential to one side of FETS  5 A and  5 B (i.e., a gate oxide or missing spacer defect causing a source to gate short circuit). In circuit  34 A, a voltage is applied by voltage source  21 A and  21 B and a current is sensed using voltage divider circuits  35 A and  35 B. If any of FETS  5 A comprise a gate oxide or missing spacer defect (i.e., gate to source short circuit), a current will flow and voltage divider circuit  35 A will register a voltage indicating current flow. Similarly, if any of FETS  5 B comprise a gate oxide or missing spacer defect (i.e., gate to source short circuit), a current will flow and voltage divider circuit  35 B will register a voltage indicating current flow. Based on the current flow indicated, it may be determined if FETS  5 A and  5 B comprise a gate oxide defect or a missing spacer defect as described, supra. 
     FIG. 6  illustrates a top view of a test portion of a semiconductor structure, in accordance with embodiments of the present invention. The test portion illustrated in  FIG. 5  is applicable to any of semiconductor structures  2 A . . .  2 C. Circuit  34 B illustrated in  FIG. 5  comprises an opposite configuration to circuit  34 A of  FIG. 4 . In circuit  34 B, a plurality of FETS  5 A (i.e., drain structures  14 B) are electrically connected to a voltage source  21 A and a voltage divider circuit  35 A and a plurality of FETS  5 B (i.e., drain structures  14 D) are electrically connected to a voltage source  21 B and a voltage divider circuit  35 B. Circuit  34 A provides a means for identification of systematic defects that are preferential to one side of FETS  5 A and  5 B (i.e., a gate oxide or missing spacer defect causing a drain to gate short circuit). In circuit  34 A, a voltage is applied by voltage source  21 A and  21 B and a current is sensed using voltage divider circuits  35 A and  35 B. If any of FETS  5 A comprise a gate oxide or missing spacer defect (i.e., gate to drain short circuit), a current will flow and voltage divider circuit  35 A will register a voltage indicating current flow. Similarly, if any of FETS  5 B comprise a gate oxide or missing spacer defect (i.e., gate to drain short circuit), a current will flow and voltage divider circuit  35 B will register a voltage indicating current flow. Based on the current flow indicated, it may be determined if FETS  5 A and  5 B comprise a gate oxide defect or a missing spacer defect as described, supra. 
     FIG. 7  illustrates a flowchart describing an algorithm used to determine FET defect types for FETs on semiconductor devices  2 A- 2 D of  FIGS. 1-6 , in accordance with embodiments of the present invention. In step  40 , a positive lead for a 1 st  voltage source is electrically connected to a gate contact (e.g., conductive layer  15 C) for a 1 st  FET(s) (e.g., FET  5 A of  FIG. 1  comprising a source/drain structure extending laterally below a gate structure). In step  44 , a negative lead for the 1 st  voltage source is electrically connected to a voltage divider circuit (e.g., current measurement device  22 A of  FIG. 2 ). In step  46 , the voltage divider circuit (e.g., current measurement device  22 A of  FIG. 2 ) is electrically connected to a source/drain gate contact (e.g., conductive layer  15 A or  15 B) for the 1 st  FET(s) (e.g., FET  5 A of  FIG. 1 ). In step  48 , it is determined if a current flow has been detected. 
   If in step  48 , it is determined that a current flow has not been detected then in step  50 , it is determined that none the FETS of the semiconductor device comprises a gate oxide or sidewall spacer defect and the process is terminated in step  64 . 
   If in step  48 , it is determined that a current flow has been detected then in step  52 , a positive lead for a 2 nd  voltage source is electrically connected to a gate contact (e.g., conductive layer  15 F) for a 2 nd  FET(s) (e.g., FET  5 B of  FIG. 1  comprising a source/drain structure that does not extend laterally below a gate structure). In step  54 , a negative lead for the 2 nd  voltage source is electrically connected to a voltage divider circuit (e.g., current measurement device  22 B of  FIG. 2 ). In step  56 , the voltage divider circuit (e.g., current measurement device  22 B of  FIG. 2 ) is electrically connected to a source/drain gate contact (e.g., conductive layer  15 D or  15 E) for the 2 nd  FET(s) (e.g., FET  5 B of  FIG. 1 ). In step  58 , it is determined if a current flow has been detected. 
   If in step  58 , it is determined that a current flow has been detected then in step  62 , it is determined that all the FETS of the semiconductor device comprises a sidewall spacer defect and the process is terminated in step  64 . 
   If in step  58 , it is determined that a current flow has not been detected then in step  60 , it is determined that all the FETS of the semiconductor device comprises a gate oxide defect and the process is terminated in step  64 . 
   While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.