Abstract:
Interruption of a reception signal is achieved by placing a first low noise amplifier into the sleep state, and short-circuiting a shunt switch provided between differential input terminals of a second low noise amplifier during a DC offset canceling period. Further, an antenna switch is switched to a circuit system where DC offset canceling is not performed for preventing the input of the reception signal to a circuit system where DC offset canceling is performed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a wireless communication receiver circuit of a direct conversion system. In particular, the present invention relates to a wireless communication receiver circuit which has a DC offset canceling function.  
         [0003]     2. Description of Related Art  
         [0004]     Conventional signal processing systems used in wireless communication for cellular phones or the like include a superheterodyne system. In such a superheterodyne system, a process of .downconverting of a reception signal to an intermediate frequency is temporarily required, and thus, the circuit scale is large.  
         [0005]     In recent years, as a solution of this problem, a direct conversion system has been developed wherein downconversion into the intermediate frequency is not necessary. However, in the direct conversion system, the output of the DC offset to the next stage is amplified undesirably when a DC offset is present in a reception signal path.  
         [0006]     A solution of this problem presents a DC offset canceling method. A receiver circuit carrying out this method has a structure, for example, as shown in  FIG. 3 . Specifically, the receiver circuit includes a duplexer  101 , a first low noise amplifier  102 , a band pass filter  103  comprising a SAW (surface acoustic wave) filter, a second low noise amplifier  104 , demodulators  105 _ 1 ,  105 _ 2  comprising mixers, a local oscillator  106 , a control logic circuit  107 , gain control amplifiers  108 _ 1 ,  108 _ 2 , DC offset canceling circuits  109 _ 1 ,  109 _ 2 , lowpass filters  110 _ 1 ,  110 _ 2 , and a base band block  111 . Posterior the demodulators  105 _ 1 ,  105 _ 2 , the circuit is separated into two signal paths for carrying out the signal processes of the in-phase component and the quadrature component separately.  
         [0007]     In the receiver circuit having the above structure, the DC offset canceling circuits  109 _ 1 ,  109 _ 2  respectively connect the input ends to the output ends of the gain control amplifiers  108 _ 1 ,  108 _ 2 . The DC offset canceling circuits  109 _ 1 ,  109 _ 2  calibrate the DC offset at the input portions of the gain control amplifiers  108 _ 1 ,  108 _ 2 .  
         [0008]     The control logic circuit  107 , being connected to a local oscillator  106 , outputs a frequency control signal for controlling the oscillating frequency. The frequency control signal, being inputted to the local oscillator  106 , defines the oscillating frequency in the local oscillator  106 . At the time of starting the DC offset canceling operation, the control logic circuit  107  outputs a DC offset canceling signal. The DC offset canceling signal is inputted to the DC offset canceling circuits  109 _ 1 ,  109 _ 2 , and the DC offset canceling operation by the DC offset canceling circuits  109 _ 1 ,  109 _ 2  starts.  
         [0009]      FIG. 4  shows a specific example of a DC offset canceling circuit disclosed in Japanese Laid-Open Patent Publication No. 2001-211098. As shown in  FIG. 4 , in the DC offset canceling circuit  109 _ 1 , the DC offset component at the output of the gain control amplifier  108 _ 1  is read and digitalized by an AD converter  401 , and inputted to a control circuit  402 . Thereafter, based on a digital signal corresponding to the inputted DC offset component, the control circuit  402  outputs a calibration signal to the DA converter  403  as a digital signal for canceling the DC offset. The DA converter  403  converts the inputted calibration signal to an analog signal and outputs to the gain control amplifier  108 _ 1 . Thus, the DC offset voltage at the output of the gain control amplifier  108 _ 1  is calibrated, and the DC offset is cancelled.  
         [0010]     As shown in  FIG. 4 , at the time of canceling the DC offset, the DC offset is detected at the output portion of the gain control amplifier  108 _ 1 . When a reception signal is present at the time of detecting the DC offset, an AC voltage is superimposed on the offset potion of the DC voltage. Therefore, during the DC offset canceling operation period, it is not possible to detect only the DC offset if the reception signal is present. Therefore, the accuracy in the DC offset canceling operation is low.  
       SUMMARY OF THE INVENTION  
       [0011]     An object of the present invention is to provide a receiver circuit that makes it possible to improve an accuracy in the DC offset canceling operation.  
         [0012]     To achieve the object, it needs either no reception signal present in a signal path during a period wherein the DC offset voltage value is detected or the amplitude is sufficiently small even if the reception signal is present in the signal path. According to the present invention, no reception signal is intend to present at the period of the DC offset canceling detection.  
         [0013]     In a receiver circuit of this invention, it adopts a structure that prevents an inputting of the reception signal to the DC offset canceling circuit that may cause a deterioration of the DC offset canceling accuracy. By this means, the accuracy in the DC offset canceling operation is improved.  
         [0014]     In the possible structure which prevents the input of reception signal to the DC offset canceling circuit, for example, a circuit such as an amplifier for amplifying the reception signal is in the sleep state only during the DC offset canceling operation period, or bypassing operation of the reception signal is carried out by short-circuiting the input end of the circuit such as the amplifier for amplifying the reception signal, which is not used at the time of canceling operation.  
         [0015]     According to the present invention, a receiver circuit comprises a demodulation means for converting a high frequency signal into a base band signal by means of a local oscillator signal, a gain control amplifier for amplifying an output signal from the demodulation means, a DC offset canceling means for calibrating an output DC offset of the gain control amplifier in response to a DC offset canceling signal, and a reception signal interrupt means to interrupt the high frequency signal to the demodulation means in response to the DC offset canceling signal.  
         [0016]     In the structure, at the time of starting the DC offset canceling operation, the input of the high frequency signal to the demodulation means is interrupted. Therefore, the accuracy in the DC offset canceling operation is improved free from any influence of the high frequency signal as the reception signal.  
         [0017]     In the receiver circuit of the above structure, for example, the reception signal interrupt means comprises an amplifier, having an active/sleep control terminal, amplifying a high frequency signal and inputting the amplified high frequency signal to the demodulation means. The amplifier is in a sleep state in response to the DC offset canceling signal.  
         [0018]     Further, in another example, the reception signal interrupt means comprises a differential amplifier, amplifying a high frequency signal for inputting the amplified high frequency signal to the demodulation means. The differential amplifier has a shunt switch for short-circuiting a pair of differential input terminals. The differential amplifier turns on the shunt switch in response to the DC offset canceling signal.  
         [0019]     In the receiver circuit, it may provide a plurality of circuit systems comprising a demodulation means; a gain control amplifier; a DC offset canceling means; and the reception signal interrupt means for receiving a plurality of frequency bands, and an antenna switch for selecting a circuit system using in correspondence with a frequency band between input portions of the circuit systems and the antenna. The antenna switch selects a supply destination of the input signal from the antenna in response to the DC canceling signal to a circuit system where DC offset canceling operation is not performed among the plurality of circuit systems.  
         [0020]     In the receiver circuit, the reception signal interrupt means comprises an amplifier having an active/sleep control terminal and amplifying a high frequency signal, and a differential amplifier for amplifying the high frequency signal outputted from the amplifier, and inputting the amplified high frequency signal to the demodulation means. The differential amplifier has a shunt switch for short-circuiting differential signal input terminals in its circuit. The demodulator directly converts the high frequency signal outputted from the differential amplifier into a base band signal using the local oscillator signal outputted from the local oscillator. The amplifier is in the sleep state in response to the DC offset canceling signal, and the sleep state continues during the DC offset canceling operation period. The differential amplifier turns on the shunt switch in response to the DC offset canceling signal, and the ON state of the shunt switch continues during the DC offset canceling operation period.  
         [0021]     Further, for example, the demodulation means comprises a local oscillator for generating a local oscillator signal and comprises a demodulator to which both the high frequency signal being outputted from the differential amplifier and the local oscillator signal being outputted from the local oscillator are inputted.  
         [0022]     A band pass filter is provided between the amplifier and the differential amplifier. Further, a lowpass filter is provided on the output side of the gain control amplifier.  
         [0023]     Next, solution means will be described with reference to  FIG. 1 . During the DC offset canceling operation period, a first low noise amplifier  102  is in the sleep state, and a second low noise amplifier  104  is not in the sleep state. A shunt switch  112  provided between a pair of differential signal input terminals is short-circuited to achieve interruption of the reception signal. The second low noise amplifier  104  is not in the sleep state, and the pair of differential signal terminals are short-circuited by the shunt switch  112  for the following reason.  
         [0024]     One possible factor of the DC offset is a self-mixing caused by a leakage of the output signal of a local oscillator  106  to an input end of the demodulators  105 _ 1 ,  105 _ 2 . Further, as a path of the leakage of the output of the local oscillator  106 , it may be possible that the output of the local oscillator  106  leaked through the output end of the second low noise amplifier  104  and the input end of the demodulators  105 _ 1 ,  105 _ 2 , is reflected at the output end of the second low noise amplifier  104 , and leaks into the input of the demodulators  105 _ 1 ,  105 _ 2 . Therefore, if those demodulators  105 _ 1 ,  105 _ 2 , the local oscillator  106 , and the second low noise amplifier  104  are put into the sleep state during the DC offset canceling operation period, the state of operation may differ from that of the actual operation environment, and the DC offset canceling operation may not be performed accurately. Thus, it is preferable that the demodulators  105 _ 1 ,  105 _ 2 , the local oscillator  106 , and the second low noise amplifier  104  are placed in the active state.  
         [0025]     Further, in order to receive a plurality of frequency bands in the presence of a plurality of circuit systems including full components from the first low noise amplifier  102  to the low pass filters  109 _ 1 ,  109 _ 2 , it is preferable to perform the process as state below. In addition to the interruption of the reception signal, the supply destination of the reception signal is preferably switched to a circuit system for another frequency band that is not subjected to DC offset canceling. In particular, the switch between the circuit systems and the antenna is selected. Thus, the reception signal is not supplied to the circuit system that is subjected to DC offset canceling. As a result, it is possible to cancel the DC offset by preventing the input of the reception signal to the circuit system that is subjected to the DC offset canceling. After the DC offset canceling for one of the circuit systems is performed, the subsequent DC offset canceling is performed for the other circuit systems successively.  
         [0026]     The receiver circuit according to the present invention achieves the highly accurate DC offset canceling operation by interrupting the high frequency signal as a reception signal at the time of DC offset canceling operation of the wireless communication receiver circuit in the direct conversion system having the DC offset canceling function. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIG. 1  is a block diagram showing a structure of a receiver circuit including a DC offset canceling circuit according to a first embodiment of the present invention.  
         [0028]      FIG. 2  is a block diagram showing a structure of a receiver circuit including a DC offset canceling circuit according to a second embodiment of the present invention.  
         [0029]      FIG. 3  is a block diagram showing a structure of a receiver circuit including a DC offset canceling circuit of a prior art.  
         [0030]      FIG. 4  is a block diagram showing a specific structure of the DC offset canceling circuit of the prior art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     First Embodiment  
       [0031]     Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.  FIG. 1  is a block diagram showing a structure according to the first embodiment of the present invention. In  FIG. 1 , a specific exemplary circuit of a second low noise amplifier  104  is also illustrated (see an arrow indicated by a broken line).  
         [0032]     In the receiver circuit according to this embodiment, the following structure is added to structure of the DC offset canceling circuit of the prior art shown in  FIG. 3 . Specifically, a shunt switch  112  is provided between a pair of differential signal input terminals of a second low noise amplifier  104  which works as a differential amplifier. Further, a first low noise amplifier  102  has an active/sleep control terminal for an external terminal. Further, a control terminal of the shunt switch  112  and the active/sleep control terminal of the first low noise amplifier  102  are connected to a control logic circuit  107 . The other structure is similar to that of the prior art.  
         [0033]     Next, operations of the receiver circuit will be described. When a DC offset canceling signal is outputted from the control logic circuit  107 , the DC offset canceling signal is inputted to DC offset canceling circuits  109 _ 1 ,  109 _ 2  to start the DC offset canceling operation. The DC offset canceling signal from the control logic circuit  107  switches the shunt switch  112  of the upstream second low noise amplifier  104 , i.e., turns on the shunt switch  112  to interrupt the reception signal. This state continues during the DC offset canceling operation period. At this time, the second low noise amplifier  104  is in the active state, and the downstream circuits are also in the active state.  
         [0034]     The DC offset canceling signal switches the state in the active/sleep control of the first low noise amplifier  102 , and sets the first low noise amplifier  102  in the sleep state. This state continues during the DC offset canceling operation period. Thus, during the DC offset canceling operation period, it is possible to prevent the input of the reception signal to the circuits posterior demodulators  105 _ 1 ,  105 _ 2 . As a result, improvement in the accuracy in the DC offset canceling operation is achieved. The other operations are similar to those of the prior art.  
       Second Embodiment  
       [0035]     Next, a second embodiment of the present invention will be described with reference to the drawings. In order to carry out processes in a plurality of frequency bands, the receiver circuit according to this embodiment is provided with a plurality of circuit systems each including a duplexer  101 , a first low noise amplifier  102 , a SAW filter  103 , a second low noise amplifier  104 , demodulators  105 _ 1 ,  105 _ 2 , a local oscillator  106 , gain control amplifiers  108 _ 1 ,  108 _ 2 , DC offset canceling circuits  109 _ 1 ,  109 _ 2 , and low pass filters  110 _ 1 ,  110 _ 2 . In  FIG. 2 , the receiver circuit includes two circuit systems having the above structure. In  FIG. 2 , reference numeral is labeled to each block of only the band A. The band B is same as the band A, and thus, illustration of reference numeral for the band B is omitted.  
         [0036]     In the embodiment, an antenna switch  201  is provided between an antenna  202  and the duplexer  101  of the circuit system of the band A, and the duplexer  101  of the circuit system of the band B.  
         [0037]     Next, operations will be described. As with the first embodiment, the DC offset canceling start signal from the control logic circuit  107  controls the DC offset canceling circuits  109 _ 1 ,  109 _ 2 , the second low noise amplifier  104 , and the first low noise amplifier  102 . At this time, the DC offset canceling start signal further controls the antenna switch  201 .  
         [0038]     At the time of canceling the DC offset of the gain control amplifiers  108 _ 1 ,  108 _ 2  of the circuit system of the band A, the antenna switch  201  selects the band B side. Likewise, at the time of canceling the DC offset in the circuit system of the band B, the antenna switch  201  selects the band A side. Then, the DC offset canceling operation is performed successively for each of the circuit systems of the band A and the band B.  
         [0039]     In this manner, by supplying the reception signal to the circuit system where the DC offset canceling operation is not performed, it is possible to prevent the input of the reception signal to the circuit system where the DC offset canceling operation is performed. As a result, improvement in the accuracy of the DC offset canceling operation is achieved. The other effects are same as those of the first embodiment.  
       INDUSTRIAL APPLICABILITY  
       [0040]     The receiver circuit according to the present invention interrupts the reception signal at the time of DC offset canceling operation to achieve the highly accurate DC offset canceling operation advantageously. Thus, the receiver circuit according to the present invention is useful as, e.g., the wireless communication receiver circuit of the direct conversion system.