Abstract:
A power-conversion apparatus includes active-semiconductor switches configured to transition between first and second states that result in corresponding first and second electrical interconnections between capacitors and at least one of first and second terminals configured to be coupled to first and second external circuits at corresponding first and second voltages, a pre-charge circuit coupled to at least one of the capacitors, and gate-driver circuits, each of which includes a control input, power connections, and a drive output. Each switch is coupled to and controlled by a drive output of one of the gate-driver circuits. Power for the gate-driver circuits comes from charge stored on at least one of the capacitors via the power connection of that gate-driver circuit.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. application Ser. No. 14/276,426, filed on May 13, 2014 which is a continuation of U.S. application Ser. No. 13/837,796, filed on Mar. 15, 2013, now U.S. Pat. No. 8,724,353, issued on May 13, 2014 the contents of which are hereby incorporated by reference in their entirety. 
     
    
     FIELD OF INVENTION 
       [0002]    This invention relates to switched capacitor converters, and more particularly to pre-charging such converters. 
       BACKGROUND 
       [0003]    A switch-mode power converter is a power converter that produces an output voltage by using a switch network to switch energy-storage elements into different electrical configurations. Examples of energy-storage elements include inductors and capacitors. A switched-capacitor power converter is a type of switch-mode power converter that primarily utilizes capacitors to transfer energy. In such converters, the number of capacitors and switches increases as the conversion gain increases. 
         [0004]    As used herein, “conversion gain” is either a voltage gain or a current gain. In those cases in which the switched-capacitor power converter produces an output voltage that is larger than its input voltage, the conversion gain is a voltage gain. On the other hand, in those cases in which the switched-capacitor power converter produces an output voltage that is smaller than the input voltage, the conversion gain is a current gain. 
         [0005]      FIGS. 1 and 2  show two examples of switched-capacitor power converters that receive an input voltage VI from a voltage source  16  and provide an output voltage VO to a load  18 . Both of the examples are also known as “cascade multipliers.” In  FIG. 2 , a number of the switching devices of the circuit in  FIG. 1  have been replaced with series of multiple devices. This reducing the maximum voltage across individual devices in the circuit. 
         [0006]    In normal operation, charging or discharging pump capacitors C 1 -C 3  pumps charge along a chain of diode-connected NMOS transistors M 0 -M 5 . The phase voltages VP 1 , VP 2  are one hundred and eighty degrees out of phase. Each of the NMOS transistors M 0 -M 5  is diode-connected, thereby only permitting boost operation (i.e., VO greater than VI). Additionally, the efficiency is severely impacted because a significant amount of voltage is dropped across each of the transistors M 0 -M 5  during normal operation. Therefore, there is a desire to operate the NMOS transistors M 0 -M 5  in their ohmic region. But due to difficulty and/or complexity of driving the transistors M 0 -M 5 , a combination of both PMOS transistors and high-voltage transistors is typically used. 
         [0007]    If the transistors in the switched capacitor power converter are integrated on a single substrate, it is desirable to use as few different types of devices as possible. This is because, for a given semiconductor process, cost is related to the number of mask layers. As the number of different types of devices in a semiconductor process increases so does the number of mask layers, and hence the cost. 
         [0008]    Furthermore, it is well-known that electrons have a higher mobility than holes in silicon. Consequently, an NMOS device with a given on-resistance has a smaller gate capacitance than a PMOS device with the same on-resistance. It is also true that an NMOS device with a given gate capacitance has a smaller on-resistance than a PMOS device with the same gate capacitance. In a power converter, it is therefore desirable to replace as many PMOS devices in the main power path with NMOS devices and also to replace as many high-voltage devices with low-voltage devices. 
       SUMMARY 
       [0009]    In one aspect, the invention features a power-conversion apparatus having active-semiconductor switches configured to transition between first and second states that result in corresponding first and second electrical interconnections between capacitors and at least one of first and second terminals configured to be coupled to first and second external circuits at corresponding first and second voltages, a pre-charge circuit coupled to at least one of the capacitors, and gate-driver circuits, each of which includes a control input, power connections, and a drive output. Each switch is coupled to and controlled by a drive output of one of the gate-driver circuits. Power for the gate-driver circuits comes from charge stored on at least one of the capacitors via the power connection of that gate-driver circuit. 
         [0010]    In some embodiments, the pre-charge circuit initializes voltages on capacitors in the switched-capacitor network prior to clocked operation of a switched-capacitor network defined by the capacitors and the switches. In others, it maintains source voltages across selected switches within a required limit during startup of operation of the apparatus. In yet others, it provides charge to one or more of the capacitors to be used to power the gate driving circuits upon beginning clocked operation of the apparatus. 
         [0011]    Among the embodiments are those in which the pre-charge circuit includes bias resistors that define a resistor divider that defines a pre-charge voltage for one or more of the capacitors during startup of operation of the apparatus. The resistances of these resistors avoids exposing the switches to voltages in excess of a threshold voltage, thereby avoiding damage to the switches during startup of operation of the apparatus. 
         [0012]    Some embodiments include terminals coupled to the switches for connecting to the capacitors. 
         [0013]    In other embodiments, the switches and the capacitors define a power converter that is configured to provide time-varying voltages to at least some of the gate-driver circuits. 
         [0014]    Also among the embodiments are those in which each of the switches has a maximum-voltage rating that is less than the first voltage and those in which the voltage across the power connections of the first gate-driver circuit is no greater than twice the second voltage and less than the first voltage. 
         [0015]    In some embodiments, each switch is driven by a corresponding one of the gate-driver circuits. These embodiments include a second gate-driver circuit that receives power via a power connection thereof from at least another of the capacitors that has a voltage across it that differs from that across the capacitor that drives the first gate-driver circuit. 
         [0016]    In other embodiments, the capacitors include first and second capacitors connected by at least one of the switches at corresponding high-voltage terminals thereof. Among these embodiments are those in which low-voltage terminals of the capacitors are connected to different phase voltages. 
         [0017]    In some embodiments, the first gate-driver circuit causes a voltage across the power connections thereof to be less than the first voltage. 
         [0018]    In another aspect, the invention features a voltage-conversion apparatus that has first and second terminals that are configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. A plurality of switches thereof includes switches that transition between successive states, each state being characterized by a switch-activation pattern that defines which switches are to be opened and which switches are to be closed during the state. These successive states define successive switched-capacitor networks. A transition from one successive state to the next results in dismantling of a switched-capacitor network and construction of a new switched-capacitor network. In operation, the successive switched-capacitor networks and the first and second terminals collectively define a switched-capacitor converter. At least some of the capacitors in the switched-capacitor networks connect to a pre-charge circuit. The switches are controlled by gate-driver circuits, each of which includes power connections, a control input, and a drive output coupled to and for control of at least one switch. Each gate-drive circuit is configured to be powered via its corresponding first and second power connections. 
         [0019]    Embodiments include those in which each switch has a maximum voltage rating that is less than the higher of the first and second voltages. 
         [0020]    In other embodiments, a voltage across first and second power connections of a first gate-driver circuit is less than or equal to twice the lower of the first and second voltages. 
         [0021]    In yet other embodiments, the first power connection is coupled to one of the capacitors such that a voltage difference between the first and second power connections is less than whichever of the first and second voltage has a higher magnitude. 
         [0022]    In still other embodiments, the switched-capacitor converter provides, to the gate-driver circuits, time-varying voltages relative to a lowest of the corresponding voltages. 
         [0023]    In another aspect, the invention features a voltage conversion apparatus that has terminals that are configured for coupling to corresponding external circuits at corresponding voltages and active semiconducting switches that electrically interconnect capacitors to form a switched-capacitor network that is configured to transition between successive states. The apparatus includes a pre-charge circuit configured to be coupled to at least one of the capacitors. When so coupled, the switches electrically interconnect the capacitors in the successive states to one another and to the terminals. The apparatus also includes gate-drive circuits, each of which has a drive output, power connections, and a control input. Each drive output is coupled to and controls one of the switches. Among the gate-driver circuits is a first gate-driver circuit that controls a switch. This first gate-driver circuit is powered via the power connections thereof by charge stored on at least one of the capacitors. The switches and the terminals are constituents of a switched-capacitor converter. 
         [0024]    In some embodiments, the terminals comprise capacitor terminals coupled to corresponding ones of the switches for connecting to the capacitors. 
         [0025]    In other embodiments, the switched-capacitor converter provides, to at least some of the gate-driver circuits, time-varying voltages relative to a lowest of the corresponding voltages. 
         [0026]    In yet other embodiments, each switch has a maximum voltage rating that is less than a highest of the corresponding voltages. Among these are embodiments in which the first gate-driver circuit includes first and second power connections. In operation, a voltage difference exists across the first and second power connections. This voltage difference arises at least in part from a capacitor that is connected to the first power connection. The voltage difference is less than or substantially equal to twice a lowest of the corresponding voltages. 
         [0027]    Other embodiments include a second gate-driver circuit. In these embodiments, the first switch-element is driven by the first gate-driver circuit, which is powered by a first capacitor that has a first voltage. Meanwhile, the second switch-element is driven by the second gate-driver circuit, which is powered by a second capacitor that has a second voltage that differs from the first voltage. 
         [0028]    Yet other embodiments include a phase generator having phase-generator switches. The phase generator provides a time-varying voltage level to one terminal of each of the capacitors. It also generates a voltage level for a capacitor in a first charge-transfer path using a voltage from a capacitor in a second charge-transfer path. 
         [0029]    Other embodiments include those that have first and second switches in series. In operation, these switches transition into a state in which they permit a steady flow of charge between capacitors. 
         [0030]    In some embodiments, each switch has a maximum voltage rating that is less than a highest of the corresponding voltages. 
         [0031]    Also among the embodiments are those in which the switched-capacitor converter includes a cascade-multiplier network and those in which it includes a series-parallel switched-capacitor network. 
         [0032]    Some embodiments include, among the gate-driver circuits, a first gate-driver circuit powered via power connections thereof from charge stored in a capacitor set such that a voltage across the power connections is substantially less than a highest of the corresponding voltages. 
         [0033]    Also among the embodiments are those in which the capacitors are coupled to the switches. In such embodiments, the switches control the connections between the capacitors. 
         [0034]    Another aspect of the invention features a method for converting a first voltage into a second voltage. Such a method includes connecting a first terminal of a switched-capacitor power converter to a first external circuit, the switched-capacitor power converter including a switched-capacitor network in which capacitors are selectively interconnected by active semiconductor-switches, connecting a second terminal of the switched-capacitor power converter to a second external circuit, before beginning normal operation of the switched-capacitor power converter, pre-charging at least one capacitor within the switched-capacitor power converter, providing first control-signals to control inputs of gate-driver circuitry of the power converter, wherein the first control-signals cause first drive-signals at corresponding drive-outputs of the gate-driver circuitry, with these first drive-signals causing active semiconductor-switches to execute a first switch-activation pattern, providing second control-signals to control inputs of the gate-driver circuitry, wherein the second control-signals cause second drive-signals at corresponding drive-outputs of the gate-driver circuitry, wherein the second drive-signals cause the active semiconductor-switches to execute a second switch-activation pattern, and providing power to the gate-driver circuitry through power connections thereof, the power being provided by capacitors from the switched-capacitor network, wherein, in the first switch-activation pattern, a first series of active semiconductor-switches connect first and second capacitors in the switched-capacitor network of the power converter so as to permit conduction current to flow between high-voltage terminals of first and second capacitors, and wherein providing the power includes causing a voltage across the power connections to be less than a highest of the first and second voltages. 
         [0035]    Other features and advantages of the invention are apparent from the following description, and from the claims. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0036]      FIG. 1  is a schematic of a single-phase step-up cascade multiplier; 
           [0037]      FIG. 2  is a schematic of a single-phase step-up cascade multiplier with cascoded switches; 
           [0038]      FIG. 3  is a schematic of a single-phase cascade multiplier with cascoded switches and corresponding gate drivers and a pre-charging circuit; 
           [0039]      FIGS. 4-5  are annotated schematics of the circuit of  FIG. 3  in first and second phases of operation, respectively; 
           [0040]      FIG. 6  is a schematic of a tapered gate driver; 
           [0041]      FIG. 7  is a schematic of a cascoded gate driver; 
           [0042]      FIG. 8  is a schematic of a dual-phase cascade multiplier with cascoded switches and corresponding gate drivers; 
           [0043]      FIG. 9  is an annotated schematic of the circuit of  FIG. 8  in one of two phases of operation; 
           [0044]      FIG. 10  is a schematic of a dual-phase cascade multiplier and corresponding gate drivers; 
           [0045]      FIGS. 11-12  are schematics of two alternative phase generators for use with the circuit of  FIG. 10 ; and 
           [0046]      FIG. 13  is a schematic of a dual-phase series-parallel switched capacitor converter and corresponding gate drivers. 
       
    
    
     DETAILED DESCRIPTION 
     1. Overview 
       [0047]    A number of approaches are described below for use in the context of active control of switched-capacitor power converters. The approaches described either increase converter efficiency by reducing the charge deposited and discharged from the gates of control transistors, or permit the use of low-voltage transistors for switching, or both. 
         [0048]    Generally, an approach to achieving these goals is by efficiently limiting the gate-to-source voltages though the design and powering of circuits driving the switching transistors during operation. A number of specific approaches, some of which are described below, use control circuitry for switching transistors, which couple the capacitors in the charge transfer path, that are themselves powered by capacitors in the same path, and/or by capacitors in different parallel paths in the case of multi-phase converters. 
       2. Single-Phase Cascade Multiplier 
       [0049]    Referring to  FIG. 3 , a single-phase cascade multiplier circuit  30  makes use of transistors M 0 -M 5  coupling to first, second, and third pump capacitors C 1 -C 3  on the charge transfer path between a high-voltage terminal (i.e., VO) and a low-voltage terminal (i.e., VI). In the embodiment illustrated in  FIG. 3 , cascoded transistor switches (e.g., M 1  and M 2  in series) couple the pump capacitors C 1 -C 3 . However, it is also possible to use single transistors while still achieving at least some of the advantages of the configuration shown. 
         [0050]    Each transistor is driven by a corresponding gate-driver circuit. As described in more detail below, at least some of the gate-driver circuits obtain power from the pump capacitors C 1 -C 3  in the charge-transfer path that extends between the high-voltage terminal and the low-voltage terminal. The voltage across each of the pump capacitors C 1 -C 3  is a fraction of the high voltage, thereby permitting efficient generation of gate-drive signals that maintain desired limits on the gate-to-source voltages of the transistors. 
         [0051]    A driver set  32  provides the gate signals to activate or de-activate each transistor in the cascade-multiplier circuit  30 . The driver set  32  includes four low-voltage gate-driver circuits  34 , two high-voltage gate-driver circuits  35 , and four voltage followers  36 A- 36 D. Each gate-drive circuit receives a drive signal with a label either beginning with an “A” or a “B.” The drive signals A 0 , B 0 , B 1 , A 1 , A 2 , B 2  control transistors M 0 , M 1 , M 2 , M 3 , M 4 , M 5 , respectively. Furthermore, the voltage followers  36 A- 36 D receive corresponding bias voltages V 1 -V 4 , respectively. A control circuit (not shown in  FIG. 3 ) generates the drive signals A 0 , B 0 , B 1 , A 1 , A 2 , B 2  and the bias voltages V 1 -V 4 . 
         [0052]    The low-voltage gate-driver circuits  34  are coupled to the transistors M 0 , M 2 , M 4 , M 5 , whereas, the high-voltage gate-driver circuits  35  are coupled to the transistors M 1 , M 3 . The high-voltage gate-driver circuits  35  support twice the supply voltage of the low-voltage gate-driver circuits  34 . Each of the voltage followers  36 A- 36 D receives a voltage from one of the pump capacitors C 1 -C 3  and provides a constant voltage to its corresponding gate-drive circuit (i.e., low-voltage gate-driver circuits  34  or high-voltage gate-driver circuits  35 ) that is equal to or lower in value. When the received voltage is equal to the provided voltage, the corresponding voltage follower (e.g., voltage follower  36 A) behaves like a switch. To achieve this behavior, the bias voltages V 1 -V 3  are at least a threshold voltage above the corresponding source voltage while the bias voltage V 4  is at least a threshold voltage below the corresponding source voltage. Furthermore, the voltage followers  36 A- 36 D experience the same voltage stress as the transistors M 0 -M 5  in the cascade-multiplier circuit  30 . 
         [0053]      FIG. 3  also shows an example of a pre-charge circuit  38  that is used to initialize the voltages on the pump capacitors C 1 -C 3  prior to clocked operation of the cascade multiplier circuit  30 . By pre-charging the pump capacitors C 1 -C 3 , the drain-to-source voltages across the transistors M 0 -M 5  within the cascade multiplier circuit  30  can be maintained within required limits during startup, and further. Additionally, the pre-charged pump capacitors C 1 -C 3  can provide power needed by the gate driving circuits to those circuits immediately upon the start of clocked operation of the cascade multiplier circuit  30 . Upon clocked operation, the pre-charge circuit  38  can be disabled. 
         [0054]    To facilitate the use of low-voltage transistors throughout the whole power converter, the pre-charge circuit  38  uses a combination of low-voltage transistors and bias resistors. A resistor divider sets up the pre-charge voltage for each of the pump capacitors C 1 -C 3  during startup. The source voltage of each transistor within the pre-charge circuit  38  is at least a threshold voltage below its corresponding gate voltage. As a result, none of the transistors within either the pre-charge circuit  38  or the cascade multiplier circuit  30  are exposed to voltage stresses that can damage the devices during startup or clocked operation. 
         [0055]    Operation of the cascade multiplier circuit  30  and the resulting voltage levels powering the gate driving circuits can be understood with reference to their two states of operation as shown in  FIGS. 4-5 . The cascade multiplier circuit  30  transfers energy from a source  16  to a load  18  by cycling between a first state and a second state at a specific frequency. All of the transistors coupled with the “A” signals are activated and de-activated at the same time; as is the case for all of the transistors coupled with the “B” signals. To ensure a clean transition between the first and second state, the “A” signals and “B” signals do not overlap in time. Furthermore, the first and second phase voltages VP 1 , VP 2  are synchronized with the “A” signals and “B” signals. 
         [0056]    Given an input voltage VI of five volts, the cascade multiplier circuit  30  produces an output voltage VO that is twenty volts. The maximum voltage across any transistor is five volts. Furthermore, the low-voltage gate driver circuits  34  support five volts while the high-voltage gate driver circuits  35  must support ten volts. 
         [0057]      FIG. 4  illustrates a first state of operation. In this first state, the first phase voltage VP 1  is at five volts while the second phase voltage VP 2  is at zero volts. The gate driver circuits that receive a “B” signal activate their corresponding transistors and the gate driver circuits that receive an “A” signal de-activate their corresponding transistors. Consequently, a gate voltage of fifteen volts activates the transistors M 1 , M 2 , M 5  while gate voltages of five volts, ten volts, and fifteen volts de-activate the transistors M 0 , M 3 , M 4 , respectively. 
         [0058]    In the second state, shown in  FIG. 5 , the first phase voltage VP 1  is at zero volts while the second phase voltage VP 2  is at five volts. The gate driver circuits that receive an “A” signal activate their corresponding transistors and the gate driver circuits that receive a “B” signal de-activate their corresponding transistors. Consequently, gate voltages of five volts, ten volts, and twenty volts de-activate the transistors M 1 , M 2 , M 5  respectively; while gate voltages of ten volts, twenty volts, and twenty volts activate the transistors M 0 , M 3 , M 4 , respectively. 
         [0059]    Unfortunately, the voltage followers  36 A- 36 D associated with the transistors M 0 , M 1 , M 2 , M 5  consume power. Each voltage follower drops five volts across its drain and source terminals while sinking or source current for its corresponding gate driver. In the case of the transistors M 1 , M 2 , M 5 , this occurs during the first state while for transistor M 0  this occurs during the second state. 
         [0060]    In the cascade multiplier circuit  30 , charge transfers to the load  18  from the source  16  at a rate dictated by the load  18 . Because this is a single-phase design, there is only one charge transfer path that a unit of charge can follow. For example, at the start of a first clock cycle, the unit of charge leaves the source  16  and flows into the first pump capacitor C 1 . After a state transition, the unit of charge moves to the second pump capacitor C 2 . When a second clock cycle begins, the unit of charge then moves from the second pump capacitor C 2  to the third pump capacitor C 3 . After one more state transition, the unit of charge finally reaches the load  18 . It therefore takes two full clock cycles (i.e. four consecutive states) for the initial charge to reach the load  18  from the source  16 . 
         [0061]    In general, as the conversion gain of a cascade multiplier increases, the number of pump capacitors increases. Consequently, it takes a longer time for a unit of charge from the source  16  to reach the load  18  because the unit of charge needs to bounce between more pump capacitors. The number of clock cycles in the charge transfer path is M−2, where M is equal to the conversion gain. In this example, M is equal to four; therefore, the number of clock cycles is two. 
         [0062]      FIGS. 6-7  illustrate two alternative gate driving circuits, both of which can be used for the high-voltage gate driver circuits  35  and the low-voltage gate driver circuits  34 . However, as will be made clear in the following description, the gate driver in  FIG. 6  is more suitable for the low-voltage gate driver  34  while the gate driver in  FIG. 7  is more suitable for the high-voltage gate driver  35 . 
         [0063]    As illustrated in  FIG. 6 , a tapered gate driver features an input terminal IN, an output terminal OUT, and supply terminals VDD, VSS. The input terminal IN couples with the output terminal OUT through first, second, third, and fourth inverters, in that order. The four inverters include high-side PMOS transistors MP 1 -MP 4  and low-side NMOS transistors MN 1 -MN 4 . Due to the difference in electron and hole mobilities, each of the PMOS transistors MP 1 -MP 4  is typically sized larger than its corresponding NMOS transistors MN 1 -MN 4 . 
         [0064]    Starting at the input terminal IN, each subsequent inverter is k times larger than the previous inverter. For example, if k is equal to five and the width of the first inverter is one micron, then the widths of the second, third, and fourth inverters are five microns, twenty-five microns, and one hundred and twenty-five microns, respectively. By tapering the inverters, a small logic gate coupled to the input terminal IN is able to drive a large power transistor coupled to the output terminal OUT. 
         [0065]    The maximum supply voltage of the tapered gate driver is equal to or less than the breakdown voltage of the transistors. Therefore, the tapered gate driver is a good choice for the low-voltage gate driver circuits  34  in the cascade multiplier circuit  30 . Unfortunately, due to the higher voltage requirements of the high-voltage gate driver circuit  35  in  FIGS. 3-5 , the tapered gate driver circuit requires transistors with twice the breakdown voltage. 
         [0066]    An alternative method of increasing the supply voltage without the need of higher voltage transistors is to use a cascoded gate driver. As illustrated in  FIG. 7 , a cascoded gate driver includes an input terminal IN, an output terminal OUT, and supply terminals VDD, VSS. The cascoded gate driver features an output stage that includes first and second high-side transistors MP 5 , MP 6  and first and second low-side transistors MN 5 , MN 6 . The output stage requires additional support circuitry, such as a level shifter, two gate drivers, a delay block, and a voltage regulator, all of which can be designed using transistors with the same breakdown voltage as that of the transistors in the output stage. 
         [0067]    During normal operation of the cascoded gate driver, the high-side transistors MP 5 , MP 6  are activated when the low-side transistors MN 5 , MN 6  are de-activated and vice-versa. Therefore, the cascoded gate driver can support twice the supply voltage because the differential voltage across the supply terminals VDD, VSS is always supported by two de-activated transistors. In general, a larger number of transistors can be cascoded to increase the supply voltage further. For example, if the output stage included three high-side transistors and three low-side transistors then the maximum supply voltage would be tripled and so on. Unfortunately, as the number of cascoded transistors increases, so does the complexity of the support circuitry. 
       3. Dual-Phase Cascade Multiplier 
       [0068]    In general, a single-phase cascade multiplier can be converted into a multi-phase cascade multiplier featuring multiple charge transfer paths that are shifted in time. As illustrated in  FIG. 8 , a dual-phase cascade-multiplier circuit  40  can be constructed by placing two copies, of the single-phase cascade-multiplier circuit  30  in parallel. Each copy is referred to as a phase (not to be confused with state). Therefore, the cascade-multiplier circuit  30  features a first phase and a second phase. The first phase includes capacitors C 1 A-C 3 A, transistors MOA-M 5 A, and phase voltages VP 1 , VP 2 . The second phase includes capacitors C 1 B-C 3 B, transistors MOB-M 5 B, and phase voltages VP 3 , VP 4 . Each of the transistors MOA-M 5 B has a corresponding gate driver circuit  34  that receives a driver signal with a label either beginning with an “A” or a “B.” The first phase includes driver signals A 0   a -B 2   a  while the second phase includes driver signals A 0   b -B 2   b.    
         [0069]    The control signals of the first phase and the second phase are shifted by one-hundred and eighty degrees. This can be achieved by swapping the “A” and “B” signals in one of the two phases and then inverting the corresponding phase voltages. For example, in normal operation, the phase voltages VP 1 , VP 3  are high when the phase voltages VP 2 , VP 4  are low and vice versa. Furthermore, the voltage followers in the first phase receive bias voltages V 1   a -V 4   a  while the voltage followers in the second phase receive bias voltage V 1   b -V 4   b . As in the previous single-phase example, a control circuit (not shown in  FIG. 8 ) can generate the drivers signals A 0   a -B 2   b  and the bias voltages V 1   a -V 4   b.    
         [0070]    Additionally, by having the source  16  and the load  18  trade places, a step-down power converter can be converted into a step-up converter and vice versa. Therefore, the cascade-multiplier circuit  40  is step-down power converter instead of a step-up power converter as in  FIG. 3 . 
         [0071]    There are several benefits of a dual-phase construction over a single-phase construction. The most obvious benefit is that there is always a charge transfer path between the source  16  and the load  18  regardless of the state of operation (first or second). A less obvious benefit is that the one phase can derive energy from an alternate phase to power circuitry and vice versa. Furthermore, this technique allows the cascade-multiplier circuit  40  to only use low-voltage gate driver circuits  34 . 
         [0072]    Since a dual-phase converter is essentially two single-phase converters operated in parallel, the cascade-multiplier circuit  40  operates as described in connection with  FIGS. 3-5 . Assuming the input voltage VI is twenty volts, the resulting voltage levels powering the gate driving circuits can be understood with reference to  FIG. 9  that show one state of operation. The other state of operation is not shown because it is simply a mirror image of the state shown in  FIG. 9 . 
         [0073]    In the cascade-multiplier circuit  40 , the transistors M 0 A-M 3 B derive power from opposing phases while the transistors M 4 A-M 5 B derive power from the input voltage VI. Powering the gate drivers from a parallel charge transfer path (i.e. opposing phase) results in one less voltage follower per phase. The voltage followers do not consume power. This is because the transistors M 0 A, M 2 A, M 5 A, M 0 B, M 2 B, M 5 B are de-activated while voltage is being dropped across their corresponding voltage followers. Because of the more efficient voltage followers and the lack of high-voltage gate driver circuits  35 , the energy required to drive the gates in a dual-phase design is less than that that would be required by a single-phase design. 
         [0074]    As in the single-phase construction of  FIG. 3 , it takes two full clock cycles for the initial charge into the cascade-multiplier circuit  40  to reach the load  18 . However, in the dual-phase construction, there are two charge transfer paths between the source  16  and the load  18 , instead of one, as in the single-phase construction. Furthermore, the two distinct charge transfer paths are shifted in time with respect to each other. 
         [0075]    For example, a first unit of charge from the source  16  enters a first charge transfer path at the input of the cascade-multiplier circuit  40 . During each state transition, the first unit of charge hops between the positive terminals of the capacitors C 3 B, C 2 B, C 1 B, in that order. As a result, the first unit of charge reaches the load  18  after four state transitions. Similarly, in a second charge transfer path, a second unit of charge leaves the source  16  and then hops between the positive terminals of the capacitors C 3 B, C 2 B, C 1 B with each state transition. The fourth state transition then delivers the second unit of charge to the load  18 . Shifting the first and second charge transfer paths one hundred and eighty out of phase thus ensures that charge path always exists between the source  16  and the load  18 . 
         [0076]    The above described dual-phase cascade-multiplier circuit  40  is one of many different implementations. 
         [0077]    For example,  FIG. 10  illustrates an alternative dual-phase cascade-multiplier circuit  50 , formed by removing the cascode switches M 2 A, M 4 A, M 2 B, M 4 B in the cascade-multiplier circuit  40 . This reduces control complexity and improves robustness. A disadvantage of this circuit is that, without the cascode switches, all of the inner switches M 1 A, M 3 A, M 1 B, M 3 B need to support twice the output voltage VO as well as their corresponding gate drivers  35 . 
         [0078]    Additionally, the pump capacitors C 3 A, C 3 B in the cascade-multiplier circuit  50  are pumped in series with their corresponding pump capacitors C 1 A, C 1 B, compared to being pumped in parallel as in the cascade-multiplier circuit  40 . The series arrangement reduces the voltage across the pump capacitors C 3 A, C 3 B. For example, if the output voltage VO is five volts, then the voltage across the capacitors C 3 A, C 3 B is ten volts in  FIG. 10  compared to fifteen volts in  FIG. 8 . Due to the similarity between the cascade-multiplier circuit s  40 ,  50 , the cascade-multiplier circuit  50  operates as described in connection with  FIG. 10   
       4. Phase Generation 
       [0079]    In addition to efficient generation of gate driving signals, the capacitor voltages can also be used to efficiently drive the phase signals that drive the capacitors. Two examples of the phase generator  110  are shown in  FIGS. 11-12 . These are suitable for using with the dual-phase cascade-multiplier circuit  50  shown in  FIG. 10 . 
         [0080]      FIG. 11  illustrates a phase generator  110  that receives an output voltage VO and produces first, second, third, and fourth phase voltages VP 1 -VP 4 . The first and second phase voltages VP 1 , VP 2  correspond to the first phase of the cascade-multiplier circuit  50  while the third and fourth phase voltages VP 3 , VP 4  correspond to the second phase of the cascade-multiplier circuit  50 . 
         [0081]    The phase generator  110  features four transistor pairs. Each transistor pair generates one of the phase voltages VP 1 -VP 4 . A first pair of transistors MH 1 , ML 1  generates the first phase voltage VP 1 ; a second pair of transistors MH 2 , ML 2  generates the second phase voltage VP 2 ; a third pair of transistors MH 3 , ML 3  generates the third phase voltage VP 3 ; and a fourth pair of transistors MH 4 , ML 4  generates the fourth phase voltage VP 4 . In each transistor pair, the high-side transistor (e.g. MH 1 ) is a PMOS device while the low-side transistor (e.g. ML 1 ) is an NMOS device. 
         [0082]    Separate gate driver circuits control each transistor in the phase generator  110 , thereby allowing tri-state operation of each transistor pair. The output voltage VO powers each gate-driver circuit. The gate-driver circuits can be implemented using numerous circuit topologies, such as the tapered gate driver illustrated in  FIG. 6 . Each gate driver circuit receives a driver signal with a label beginning with either an “A” or a “B.” The driver signals AL 1 , BL 1 , AL 2 , BL 2  control low-side transistors ML 1 , ML 2 , ML 3 , ML 4 , respectively while the driver signals BH 1 , AH 1 , BH 2 , AH 2  control high-side transistors MH 1 , MH 2 , MH 3 , MH 4 , respectively. 
         [0083]    In normal operation, the phase generator  110  cycles between a first state and a second state at a specific frequency. During the first state, the gate-driver circuits that receive a “B” signal activate their corresponding transistors and the gate-driver circuits that receive an “A” signal de-activate their corresponding transistors. Consequently, the first and third phase voltages VP 1 , VP 3  are equal to the output voltage VO while the second and fourth phase voltages VP 2 , VP 4  are equal to zero volts. 
         [0084]    In contrast, during the second state, the gate-driver circuits that receive a “B” signal de-activate their corresponding transistors and the gate-driver circuits that receive an “A” signal activate their corresponding transistors. Consequently, the first and third phase voltages VP 1 , VP 3  are equal to zero volts while the second and fourth phase voltages VP 2 , VP 4  are equal to the output voltage VO. 
         [0085]      FIG. 12  illustrates an alternative phase generator  110  that receives an output voltage VO and produces first, second, third, and fourth phase voltages VP 1 -VP 4 . In a dual-phase design, the first and third phase voltages VP 1 , VP 3  are in phase; and the second and fourth phase voltages VP 2 , VP 2  are in phase. Consequently, as illustrated in  FIG. 12 , the first and third phase voltages VP 1 , VP 3  can be shorted together and the second and fourth phase voltages VP 2 , VP 4  can be shorted together. 
         [0086]    Additionally, high-side transistors MH 1 , MH 2  can utilize NMOS transistors instead of PMOS transistors as in  FIG. 11 . The higher mobility of electrons in NMOS transistors allows the use of smaller high-side transistors MH 1 , MH 2 , thereby reducing the energy required to activate. Because NMOS transistors require a gate voltage higher than their source to activate, the high-side transistors MH 1 , MH 2  derive this boost voltage from the pump capacitors within the cascade multiplier that the phase generator  110  is driving. 
         [0087]    For example, if the phase generator  110  is coupled to the cascade-multiplier circuit  50 , then the gate driver of the high-side transistor MH 1  is coupled to the positive terminal of the pump capacitor CIA from the first phase. In contrast, the gate driver of the high-side transistor MH 2  is coupled to the positive terminal of the pump capacitor C 1 B from the second phase. Therefore, each gate driver and its corresponding high-side transistor is powered by a pump capacitor from a distinct parallel charge transfer path. 
         [0088]    Because of the similarity of the phase generators  110  in  FIGS. 11-12 , the phase generator  110  in  FIG. 12  operates as described in connection with  FIG. 11 . The differences mainly arise from the shorted phase voltages and boosted high-side transistors MH 1 , MH 2   
       5. Alternatives 
       [0089]    A number of alternatives to the switched-capacitor power-converter designs discussed make use of the approaches embodied in those designs. For example, the converter illustrated in  FIG. 13  is a dual-phase series-parallel switched capacitor circuit  60  that includes some gate drivers that are powered by capacitors in either the same charge transfer path or a parallel charge transfer path. 
         [0090]    The switched capacitor circuit  60  includes a pair of phases. A first phase includes capacitors C 1 C-C 3 C, odd-numbered transistors M 1 C-M 7 C, and even-numbered transistors M 2 C-M 12 C. Similarly, a second phase includes capacitors C 1 D-C 3 D, odd-numbered transistors M 1 D-M 7 D, and even-numbered transistors M 2 D-M 12 D. All of the transistors coupled with signals having an “A” prefix through corresponding gate drivers are activated and de-activated at the same time; as is the case for all of the transistors coupled with signals having a “B” prefix through corresponding gate drivers. 
         [0091]    The switched capacitor circuit  60  produces an output voltage VO that is four times lower than an input voltage VI. It does so by cycling between a first state and a second state at a specific frequency. During the first state, the first phase odd-numbered transistors M 1 C-M 7 C and the second phase even-numbered transistors M 2 D-M 12 D are activated while the first phase even-numbered transistors M 2 C-M 12 C and the second phase odd-numbered transistors M 1 D-M 7 D are de-activated. This switch activation pattern places the second phase capacitors C 1 D-C 3 D in parallel with the load  18  and places a series arrangement of the first phase capacitors C 1 C-C 3 C in between the source  16  and the load  18 . 
         [0092]    In contrast, during the second state, the first phase odd-numbered transistors M 1 C-M 7 C and the second phase even-numbered transistors M 2 D-M 12 D are de-activated while the first phase even-numbered transistors M 2 C-M 12 C and the second phase odd-numbered transistors M 1 D-M 7 D are activated. This switch activation pattern places the first phase capacitors C 1 C-C 3 C in parallel with the load  18  and places a series arrangement of the second phase capacitors C 1 D-C 3 D in between the source  16  and the load  18 . 
         [0093]    Unlike either of the dual-phase cascade-multiplier circuits  40  or  50 , within a single phase of the switched capacitor circuit  60 , the gate drivers derive their power from capacitors in both phases. For example, the gate drivers for the corresponding transistors M 1 C, M 3 C, M 5 C are powered from the capacitors C 1 C, C 2 C, C 3 C, respectively while the gate drivers for the corresponding transistors M 4 C, M 8 C, M 12 C are powered from the capacitor C 1 D. 
         [0094]    Furthermore, the voltage stress across the transistors in a series-parallel switched capacitor power converter can be higher than the corresponding voltage stresses in cascade multipliers. Assuming a twenty-volt input voltage VI, the maximum voltage across the transistors M 12 C, M 12 D will be fifteen volts. In this embodiment, the gate-to-source voltage is always five volts and the gate drivers for the top PMOS transistors require two series connected voltage followers that are biased using voltages V 1   c -V 2   d.    
         [0095]    Although described in the context of single-phase and dual-phase converters, it should be understood that other multi-phase converter configurations can be used. For example, a four-phase cascade multiplier can be constructed by placing two copies of the cascade-multiplier circuit  40  in parallel and shifting their respective clocks by ninety degrees. Adding an even number of phases is straightforward because every subsequent pair of phases can be run in isolation. 
         [0096]    However, if the switched capacitor power converter includes an odd number of phases, it is more difficult to power gate drivers from capacitors in different parallel charge transfer paths. In this case, each gate driver draws power from capacitors in multiple parallel charge-transfer path instead of from a single parallel charge transfer-path in the even-numbered phase case. 
         [0097]    In general, switched capacitor converters feature a large number of switches and capacitors. By necessity, at least a few of the switches float. This means that neither switch terminal is attached to a constant electric potential. Switched-capacitor converters that have at least one floating switch can benefit by deriving power from the same charge transfer path or a parallel charge transfer path. Examples of such switched capacitor converters include those having cascade multiplier, series-parallel, parallel-series, Fibonacci, and voltage-doubler topologies. 
       6. Implementations 
       [0098]    The switched capacitor power converters and the associated gate drivers illustrated herein can all be integrated on one or multiple semiconductor substrates. If all of the transistors are integrated on a single substrate and if any of those transistors float, then the transistors must be isolated from the substrate. For example, in a CMOS process, NMOS transistors are typically formed in a p-type substrate. These devices can only float if the bulk of the NMOS transistors is isolated from the substrate. If this were not the case, then an alternative possibility would be to use multiple semiconductor substrates. 
         [0099]    The capacitors in a switched capacitor power converter can either be integrated, discrete, or a combination thereof. The discrete capacitors are typically multi-layer ceramic capacitors. The integrated capacitors are typically planar or trench capacitors. If the capacitors are integrated, then they can be integrated on the same wafer with their switches, on a separate wafer, or on a combination thereof. Furthermore, if the capacitors and switches are on different wafers then there are various attachment methods, some of which remove the pin count limitation of the overall converter. 
         [0100]    The ability to re-purpose the pump capacitors is of benefit when the switched capacitor power converter uses either integrated capacitors or discrete capacitors. If discrete capacitors are used, then each capacitor uses at least one pin. Adding extra pins for the gate driver circuitry is quite painful because pins on an integrated circuit are of limited supply for a given die area. On the other hand, integrated capacitors do not eat into your pin count, but they are quite expensive and have a low capacitance per area so it is valuable to limit their use. 
         [0101]    Typically, a controller produces control signals for activating and de-activating the switches within a switched capacitor power converter. For example, in most of the embodiments described above, a controller could have generated the driver signals that are labeled with an “A” or a “B” prefix. By controlling the on and off time of the individual switches, a controller can provide many functions. A few such functions include the ability to regulate the output voltage, the ability to shut off the power converter in the event of a fault condition, and the ability to change the gain of the switched capacitor network. 
         [0102]    Various features, aspects, and embodiments of switched capacitor power converters have been described herein. The features, aspects, and numerous embodiments described are susceptible to combination with one another as well as to variation and modification, as will be understood by those having ordinary skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. Additionally, the terms and expressions which have been employed herein are used as terms of description and not of limitation. There is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents. 
         [0103]    It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims.