Abstract:
A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is generally directed to alignment of a scan dump for a scan chain or more generally any shift register. More specifically, the present invention is directed to such alignment by register and by clock cycle for the benefit of debugging scan-based microchip designs. 
     2. Background 
     A microchip chip may include a series of registers, with each register corresponding to a latch or flip-flop. Verification of a chip hardware design may include a procedure to perform a scan dump in which the contents of each register is shifted to an output scan pin in a concatenated sequence. The sequence of registers in combination with an input scan-in pin and an output scan-out pin may be referred to as a scan chain. 
     In a hardware test, a circuit may be stimulated for a specified number of clock cycles and stopped. The contents of each register may then be shifted to an output scan pin and compared to the predicted result based on the intended design of the microchip logic. If an error is determined, the test may be repeated starting at the beginning and stopped after the first clock cycle for scan chain examination to determine if the error begins at that time. If no error is found, the test may be restarted and stopped after the second clock cycle, and so forth. Alternatively, the test may be stopped and the scan chain examined a finite number of clock cycles prior to the determined error. 
     The scan chain output may be compared to a software simulation that may emulate the register behavior of the intended design. One difficulty in analyzing the scan chain output or comparing it with the software simulation chain may include uncertainty in whether the contents of a particular register are being compared to its appropriate software counterpart. This uncertainty presents a problem in spatial alignment. A second difficulty may include identifying at which clock cycle the scan output was obtained for comparison with the software simulation. This uncertainty presents a problem in temporal alignment. 
     Accordingly, there exists a need for an efficient, simple and inexpensive method for aligning the scan chain output by register and by clock cycle. 
     SUMMARY OF THE INVENTION 
     A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating a series of latches for spatial alignment in accordance with a preferred embodiment of the present invention. 
     FIG. 2 is a block diagram illustrating a series of latches for temporal alignment in accordance with a preferred embodiment of the present invention. 
     FIG. 3 is a line diagram illustrating signals for temporal alignment in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. 
     To enable scan operation in a chip design, a latch may include an input signal s i , a scan enable signal s e , a clock clk and an output signal s o . The input signal s i  may be the output signal s o  from an adjacent upstream register. The scan enable signal s e  can command the contents of the register to be shifted to output. The output signal s o  may be the input signal s i  to the next latch in the chain or feed the output scan pin. Depending on the latch or flip-flop design, additional inputs may be included. A series of latches may be concatenated to form a chain. The output of the chain when shifted out may be referred to as a scan dump of the shift register chain. 
     For the purposes of redundancy and to enable incremental design change, the scan chain often includes one or more latches or flip-flops that may be unused with respect to the logic circuitry designed for the microchip. A selected portion of these unused scan latches or flip-flops may be programmably defined by a constant value, such as a ground voltage V ss  or power voltage V dd . 
     FIG. 1 illustrates a series of latches  10  in accordance with a specific embodiment of the invention. The series  10  includes eight concatenated latches  12   a ,  12   b ,  12   c ,  12   d ,  12   e ,  12   f ,  12   g  and  12   h . The first latch  12   a  may receive a signal input s i1  as  14  and produce a signal output s o1  as  16 . The second latch  12   b  may receive the first latch&#39;s signal output  16  as its input s i2  to produce a second latch output s o2  as  18 . The input to output chain may continue through S o3  as  20 , S o4  as  22 , s o5  as  24 , s o6  as  26 , and s o7  as  28  until the eighth and final output S o8  as  30 . Each latch may receive a clock signal clk as  32  and a shift enable signal s e  as  34  to command the register contents be shifted out to create the scan dump  36 . 
     The design of the series  10  may include redundant latches with unspecified logic until correction of a design defect requires their definition. In this example, the second latch  12   b  and the fifth latch  12   e  are redundant, so the output of their registers  18  and  24  within the concatenated result may be irrelevant to the desired result from the series  10 . The second latch  12   b  may be shunted to power voltage  38  or V dd , so that its output  18  should always read V dd . Similarly, the fifth latch  12   e  may be shunted to ground  40  or V ss , so that its output  24  should always read V ss . Thus, whenever a test execution is stopped and the shift enable signal  34  is activated, the second register&#39;s output  18  may be expected to yield V dd  without variation, and the fifth register&#39;s output  24  may be expected to yield V ss  without variation. If either or both of these registers do not yield the expected output, this error condition may be indicative of a symptomatic flaw and the remainder of the output may be considered suspect, warranting further investigation. Thus, an analysis of the scan dump may accurately identify whether specific registers are reading correctly, producing spatial alignment by comparison to an absolute value for an established register. 
     FIG. 2 illustrates a series of latches  50  in accordance with a specific embodiment of the invention. The series  50  includes eight concatenated latches  52   a ,  52   b ,  52   c ,  52   d ,  52   e ,  52   f ,  52   g  and  52   h . The first latch  52   a  may receive a signal input s i1  as  54  and produce a signal output s o1  as  56 . The second latch  52   b  may receive the first latch&#39;s signal output  56  as its input s i2  to produce a second latch output s o2  as  58 . The input to output chain may continue through s o3  as  60 , s o4  as  62 , S o5  as  64 , s o6  as  66 , and s o7  as  68  until the eighth and final output s o8  as  70 . Each latch may receive a clock signal clk as  72  and a shift enable signal s e  as  74  to command the register contents be shifted into the scan dump  76 . 
     FIG. 3 shows the clock signal  72  represented by a square wave  78 , forming a series of clock cycles  80 . A trigger signal  82  indicating an event condition  84  may trigger the start of the functional test  86 , following an initialization procedure  88 . 
     The design of the series  50  in FIG. 2 may include redundant latches with unspecified logic until correction of a design defect requires their definition. In this example, the first latch  52   a  and the second latch  52   b  are redundant, so the output of their registers  56  and  58  within the concatenated result  70  may be irrelevant to the desired result from the series  50 . 
     The trigger signal  82  may be input to the first and second latches  52   a  and  52   b . The resulting signal from the outputs  56  and  58  from the first two latches may be depicted in FIG. 3 as  90 . The first and second latches  52   a  and  52   b  may be shunted to zero or ground  92  until the event condition  84  is provided from the input trigger signal  82 . Subsequent to the event condition  84  triggering the start of the test, the result  90  to the first and second latches  52   a  and  52   b  may be incremented by a particular constant  94  (such as unity) for each clock cycle  80  thereafter. With the first post-event clock cycle, the resulting signal  90  incremented by unity may be stepped to a first level  96  above ground  92 . With the second post-event clock cycle, the signal  90  may be stepped to a second level  98 . The third such clock cycle may correspond to third level  100 . For two latches, the fourth such clock cycle would reinitialize to ground  102 . The fifth such clock cycle may repeat the first level  104 , and so forth. 
     The particular clock cycle corresponding to when the scan dump is obtained may not necessarily correspond to the time of the enable signal  74 , due to a possible time lag. By providing an incremented value for each cycle from the first two latch outputs  56  and  58 , the event condition  84  signaling the beginning of the series test can be identified from the scan dump as a consequence of this invention. The number of latches concatenated into an incrementing clk echo specifies time period (or number of cycles) at which the scan dump is taken. Thus, an analysis of the scan dump may accurately identify which clock cycle the scan dump occurred producing temporal alignment with a comparison to an absolute event. 
     The combination of the spatial and temporal alignment with absolute values enables expeditious comparison of the scan dump to a software simulation or other hardware scan dumps from alternate cycle times. 
     While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this application that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.