Abstract:
A driving method for a flat panel display. First, an image signal is transformed to frame data. Next, characteristic data for the frame data is obtained. Next, a scanning order of the first electrodes is determining according to the characteristic data. Next, scanning electrodes are driven in the scanning order during the addressing period. Finally, the data electrodes corresponding to the first electrodes are driven to perform the addressing operation.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates in general to a driving device and a driving method for a flat panel display. In particular, the present invention relates to a driving device and a driving method to decrease the switching frequency of a data chip, which provides the addressing voltage of the data electrodes of a flat panel display, by changing the scanning order of the scanning electrodes.  
           [0003]    2. Description of the Related Art  
           [0004]    Flat panel display comprises liquid crystal display (LCD), organic light-emitting display (OLED), and plasma display panel (PDP), etc. The advantages of the plasma display panel are small size, good display performance, and high reliability. Thus, PDP is often used in current electric equipment.  
           [0005]    The current method of driving a plasma display panel is achieved through a plurality of subfield-display operations, which altogether constitute a full frame-display operation. For example, a picture frame in a plasma display panel with 256 gray levels may comprise eight subfields SF 0 ˜SF 7  as shown in FIG. 1A. Each subfield-display operation comprises steps of resetting, addressing, and sustaining the display signal. Specifically, a plasma display panel is driven by a driving signal which comprises an erasing period, a addressing period, and a sustaining period. During the erasing period, residual ions of each illuminant cell of a PDP are erased using a voltage pulse having a pulse width shorter than a sustaining pulse. During the addressing period, external data are input using a voltage pulse having a voltage higher than a sustaining pulse of the erasing period. During the sustaining period, an AC voltage of a constant frequency is applied to avoid an ignition miss or incorrect display and to obtain a correct power margin.  
           [0006]    [0006]FIG. 1B shows a cross section of a conventional PDP structure, and FIG. 1C shows a schematic top view of the data and scanning electrodes of the same PDP. As shown in FIG. 1B, a PDP is constructed by joining a front glass substrate  1  with a rear glass substrate  2 , wherein data electrodes  3  for inputting external data are formed on the surface of the front glass substrate  1  that opposes the rear glass substrate  1 . Furthermore, a plurality of ribs  4  is defined on the data electrodes  3  to form illuminant cells. A plurality of sustaining electrodes  7  and scanning electrodes  8  in parallel direction, on the other hand, are formed on the surface of the rear glass substrate  2  that opposes the front glass substrate  1 , wherein the above-mentioned data electrodes  3  are formed perpendicular to both the sustaining electrodes  7  and the scanning electrodes  8 .  
           [0007]    In addition, the surfaces of both the sustaining electrodes  7  and scanning electrodes  8  are coated with a dielectric layer  6  (such as a MgO layer) for protecting the surfaces of the electrodes. Furthermore, a fluorescent material  5  (such as phosphorous) is deposited between ribs (where the illuminant cells reside) for illumination to occur as soon as a voltage is applied. As shown in FIGS. 1C and 1D, a typical conventional plasma display panel comprises a plurality of row plasma display units (represented by L 1 ˜L N ). Each row display unit has one of the plurality sustaining electrodes  7  (represented by a corresponding X 1 ˜X N ), one of the plurality of parallel scanning electrodes  8  (Y 1 ˜Y N ); for example, the first row display unit L 1  comprises the first sustaining electrode X 1 , and the first scanning electrode Y 1 . The plurality of illuminant cells of the first row display unit L 1  is driven by the X 1 , Y 1  simultaneously during the sustaining period. The plurality of data electrodes  3  (A 1 ˜A M ) are disposed perpendicular to both the sustaining electrodes  7  (X 1 ˜X N ) and the scanning electrodes  8  (Y 1 ˜Y N ). Each of the sustaining electrodes  7  (X 1 ˜X N ) is connected to the others and thereby the electrodes can be driven synchronously. In contrast, each of the scanning electrodes  8  (Y 1 ˜Y N ) is separately connected from the other electrodes so as to actuate each of the electrodes independently. Thus, external data are input to each illuminant cell of the plasma display panel via the data electrodes  3  (D 1 ˜D M ) by controlling both the sustaining electrodes  7  (X 1 ˜XN) and the scanning electrodes  8  (Y 1 ˜Y N ).  
           [0008]    [0008]FIG. 2 is a driving signal diagram of various electrodes of the plasma display panel shown in FIGS. 1B, 1C, and ID, which are driven according to the method of a prior art. Accordingly, a plasma display panel is driven by a driving signal comprising an erasing period, an addressing period, and a sustaining period. During the erasing period, a very short pulse VW of a high voltage is applied to all of the sustaining electrodes  7  (including X 1 ˜X N ), and all of the scanning electrodes  8  (including Y 1 ˜Y N ) are connected to the ground Vg, so as to remove the remaining residual ions. At this point, no data electrodes  3  (including D 1 ˜D M ) are yet driven. During the addressing period, a bias V K  is applied to all of the sustaining electrodes  7  (including X 1 ˜X N ), so the scanning electrodes  8  (Y 1 ˜Y N ) can input external data sequentially via the data electrodes  3  (D 1 ˜D M ) based on an addressing signal VY. At this point, the scanning electrodes  8  (Y 1 ˜Y N ) are connected to a row address decoder (not shown in the figure) to receive an addressing signal, and the data electrodes  3  (D 1 ˜D M ) are connected to external data to precede write operations. During the sustaining period, a periodic voltage pulse Vs is alternately applied to the sustaining electrodes  7  (X 1 ˜X N ) and the scanning electrodes  8  (including Y 1 ˜Y N ) to maintain the luminance of the illuminant cells.  
           [0009]    During the addressing period, conventional method enables the scanning electrodes according to the subfield data in a fixed order, and the data chip provides the addressing voltage to the data electrodes corresponding to the driven scanning electrodes. However, the number of the switching cell of the data chip is directly proportional to the used power, because there is a parasitical capacitor Cd between the electrodes. When the voltage between the electrodes is raised to V dd , the consumed power is (½)C d V dd   2 . Moreover, when the voltage between the electrodes returns to a low level, the consumed power is (½)C d V dd   2  again. The consumed power increases the temperature of the data chip, especially when the subfield data is interleaved scanning, and the temperature may reaches 100° C., which wastes power and decreases the life of the data chip.  
         SUMMARY OF THE INVENTION  
         [0010]    The object of the present invention is to provide a driving device and a driving method for a flat panel display, which analyzes the characteristic of the subfield before addressing, and addresses the electrodes in a suitable order to decrease the voltage switching frequency of the data chip.  
           [0011]    Moreover, another object of the present invention is to provide a driving device and a driving method for a flat panel display, which detects the output current of the power supply to the flat panel display. When the output current exceeds a predetermined value, the scanning order of the flat panel display is changed to decrease the output current, such that the voltage switching frequency of the data chip is decreased.  
           [0012]    To achieve the above-mentioned object, the present invention provides a driving method for a flat panel display. First, an image signal is transformed to frame data. Next, a characteristic data of the frame data is obtained. Next, a scanning order of the first electrodes is determined according to the characteristic data. Next, scanning electrodes are driven in the scanning order during the addressing period. Finally, the data electrodes corresponding to the first electrodes are driven to perform the addressing operation.  
           [0013]    Moreover, the present invention provides a driving method for a flat panel display comprising a power supply, first electrodes, and second electrodes corresponding to the first electrodes. The driving method comprises the steps of driving the first electrodes and corresponding second electrodes in a first scanning order during the addressing period to perform the addressing operation, detecting the current output from the power supply, and driving the first electrodes and corresponding second electrodes in a second scanning order different from the first scanning order when the current output from the power supply is larger than a predetermined value for a predetermined time. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.  
         [0015]    [0015]FIG. 1A shows the subfields included in a picture frame in a plasma display panel with 256 gray levels.  
         [0016]    [0016]FIG. 1B shows a cross section of a conventional PDP structure.  
         [0017]    [0017]FIGS. 1C and 1D shows a schematic top view of the data and scanning electrodes of the same PDP.  
         [0018]    [0018]FIG. 2 is a driving signal diagram of various electrodes of the conventional plasma display panel.  
         [0019]    [0019]FIG. 3 shows the block diagram of the PDP and driving circuits according to the first embodiment of the present invention.  
         [0020]    [0020]FIG. 4 shows the block diagram of the PDP and driving circuits according to the second embodiment of the present invention.  
         [0021]    [0021]FIG. 5 shows a flowchart of the decision of the scanning order according to the second embodiment of the present invention.  
         [0022]    [0022]FIGS. 6A and 6B show another flowchart of the decision of the scanning order according to the second embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    According to the present invention, the controlling circuit controls the driving order of the scanning electrode driving circuit addressing the scanning electrodes. Thus, the numbers of the voltage switching is decreased when the corresponding data electrodes are driven.  
         [0024]    First Embodiment  
         [0025]    [0025]FIG. 3 shows the block diagram of the PDP and driving circuits according to the first embodiment of the present invention. The present embodiment dynamic selects the driving order according to the characteristic of the displayed frame. The scanning electrode driving circuit  32  provides scanning and sustain discharge pulses to the scanning electrodes Y 1 ˜Y n , the sustaining electrode driving circuit  31  provides sustain discharge pulses to the sustaining electrodes  7 , and the data electrode driving circuit  33  provides data pulses to the data electrodes D 1 ˜D m . The controlling circuit  34  controls the operation of the sustaining electrode driving circuit  31 , the scanning electrode driving circuit  32  and the data electrode driving circuit  33 .  
         [0026]    The controlling circuit  34  comprises an image data transforming device  341  and a characteristic selection device  343 . The image data transforming device  341  transforms the image data to a subfield data, and the characteristic selection device  343  analyzes the subfield data and obtains the characteristic information of the subfield data. The characteristic information of the subfield data is obtained by characteristic selection method or mask technology. The characteristic information records the intervals between the lighting cells in each frame. Thus, the controlling circuit  34  outputs a scanning order controlling signal representing a specific order to enable the scanning electrodes Y 1 ˜Y n  according to the analyzing result of the characteristic selection device  343 . Therefore, the scanning electrodes having the same voltage level are enabled in turn. When the scanning electrodes having the same voltage level are all enabled, then the scanning electrodes having other voltage levels are enabled.  
         [0027]    The scanning electrode driving circuit  32  drives the scanning electrodes Y 1 ˜Y n  in the corresponding order according to the scanning order controlling signal. For example, the scanning electrode driving circuit  32  drives the scanning electrodes of the lighting display cells first, then drives the scanning electrodes of the unlighted display cells later.  
         [0028]    The data electrode driving circuit  33  drives the data electrodes D 1 ˜D m  when corresponding scanning electrodes are driven. The driving voltage of each data electrode is provided by a data chip  36 . Because the driving order of the data electrode follows the driving order of the scanning electrode, the driving voltage of the data electrodes is the same when the corresponding scanning electrodes having the same driving voltage are driven. Therefore, the data chip provides one voltage level to the data electrodes having the same driving voltage first, then switches the output voltage level to provide another voltage level to the other data electrodes. Thus, the voltage switching times of the data chip are decreased, and the consumption of power is also decreased.  
         [0029]    Second Embodiment  
         [0030]    [0030]FIG. 4 shows the block diagram of the PDP and driving circuits according to the second embodiment of the present invention. The present embodiment determines the scanning order to be changed by detecting the power consumption of the PDP during the addressing period, and provides a suitable scanning order according to the detected result.  
         [0031]    The scanning electrode driving circuit  32  provides scanning and sustain discharge pulses to the scanning electrodes Y 1 ˜Y n , the sustaining electrode driving circuit  31  provides sustain discharge pulses to the sustaining electrodes  7 , and the data electrode driving circuit  33  provides data pulses to the data electrodes D 1 ˜D m . The controlling circuit  34  controls the operation of the sustaining electrode driving circuit  31 , the scanning electrode driving circuit  32  and the data electrode driving circuit  33 .  
         [0032]    The power supply  38  provides power to the PDP. During the addressing period, the controlling circuit  34  outputs a scanning order controlling signal representing a first scanning order during addressing, and detects the output current I d  of the power supply  38 . The controlling circuit  34  outputs another scanning order controlling signal representing a second scanning order different from the first scanning order when the output current I d  exceeds a predetermined value.  
         [0033]    In the present embodiment, three scanning orders are selected by the controlling circuit  34  to drive the scanning electrodes, namely sequential scanning, interleave scanning and interleave jump four scanning. Assuming there are sixteen scanning electrodes, the scanned order of the electrodes is [1, 2, 3, 4, . . . , 15, 16] when sequential scanning is performed, the scanned order of the electrodes is [1, 3, 5, 7, . . . , 2, 4, 6, 8, . . . ] when interleave scanning is performed, and the scanned order of the electrodes is [1, 5, 9, 13, . . . , 4, 8, 12, 16, . . . ] when interleave jump four scanning is performed. The scanning order controlling signal indicates a specific scanning order as described above.  
         [0034]    [0034]FIG. 5 shows a flowchart of the decision of the scanning order according to the second embodiment of the present invention. During the addressing period, the current detecting circuit  345  of the controlling circuit  34  detects the output current I d  of the power supply  38 . For example, the interleave scanning is performed first (S 11 ), then the current detecting circuit  345  detects the output current I d  (S 12 ). When the output current I d  is lower than the predetermined value, the performed scanning order is suitable for the present displayed frame, so the present scanning order continues (back to step S 11 ). When the output current I d  is higher than the predetermined value, the scanning order is changed to sequential scanning (S 13 ). Similarly, the current detecting circuit  345  detects the output current Id (S 14 ). When the output current I d  is lower than the predetermined value, the present scanning order continues (back to step S 13 ). When the output current I d  is higher than the predetermined value, the scanning order is changed to interleave jump four scanning (S 15 ). Similarly, the current detecting circuit  345  detects the output current I d  (S 16 ). When the output current I d  is lower than the predetermined value, the present scanning order continues (back to step S 15 ). When the output current I d  is higher than the predetermined value, the scanning order is changed to interleave scanning (S 11 ). Therefore, the performed scanning order used in the present frame decreases the voltage switching frequency of the data chip.  
         [0035]    When the scanning order is determined, the scanning electrode driving circuit  32  drives the scanning electrodes Y 1 ˜Y n  in the scanning order according to the scanning order controlling signal.  
         [0036]    The data electrode driving circuit  33  drives the data electrodes D 1 ˜D m  when corresponding scanning electrodes are driven. A data chip  36  provides the driving voltage of each data electrode.  
         [0037]    To prevent errors in detecting the output current I d , a verification step is added to another example of the present embodiment. FIGS. 6A and 6B show flowcharts of the decision of the scanning order according to the example of the second embodiment, wherein a verification step is added.  
         [0038]    During the addressing period, the current detecting circuit  345  of the controlling circuit  34  detects the output current I d  of the power supply  38 . For example, interleave scanning is performed first (S 21 ), then the current detecting circuit  345  detects the output current I d  (S 22 ). When the output current I d  is lower than the predetermined value, the performed scan is suitable for the present displayed frame, so the present scanning order continues (back to step S 21 ). When the current detecting circuit  345  detects output current I d  higher than the predetermined value, the counting value of the counter  347  is increased by one (S 23 ). Next, the counting value is detected by the controlling circuit (S 24 ). If the counting value reaches a predetermined number, the scanning order is changed to sequential scanning (S 25 ), and the counting value is reset. If not, the process goes back to step S 21 . Here, the predetermined number is designated by the user.  
         [0039]    After step S 25 , the current detecting circuit  345  detects the output current I d  (S 26 ). When the output current I d  is lower than the predetermined value, the present scanning order continues (back to step S 25 ). When the output current I d  is higher than the predetermined value, the counting value of the counter  347  is added (S 27 ). Next, the counting value is detected by the controlling circuit (S 28 ). If the counting value reaches the predetermined number, the scanning order is changed to interleave jump four scanning (S 29 ), and the counting value is reset. If not, the process goes back to step S 25 .  
         [0040]    After step S 29 , the current detecting circuit  345  detects the output current I d  (S 30 ). When the output current I d  is lower than the predetermined value, the present scanning order continues (back to step S 29 ). When the output current I d  is higher than the predetermined value, the counting value of the counter  347  is added (S 31 ). Next, the counting value is detected by the controlling circuit (S 32 ). If the counting value reaches the predetermined number, the scanning order is changed to interleave scanning (S 21 ), and the counting value is reset. If not, the process goes back to step S 29 .  
         [0041]    Therefore, the scanning order is determined by detecting the output current of the power supply. In addition, the process disclosed in FIGS. 6A and 6B prevents the determination of the selected scanning order from being influenced by the noise. Thus, the voltage switching times of the data chip is decreased, and the consumption of the power is also decreased.  
         [0042]    Accordingly, the scanning order of the scanning electrodes is adjusted to decrease the voltage switching frequency of the data chip. Therefore, the power consumption is also decreased. In addition, the life of the chip is increased, and the reliability of the circuit is increased because the decreasing voltage switching decreases electromagnetic interfering.  
         [0043]    The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.