Abstract:
A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.

Description:
This application is a divisional of co-pending application Ser. No. 08/855,363, filed on May 13, 1997 now U.S. Pat. No. 6,852,606, the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. §120; and this application claims priority of Application No. 49954/1996 filed in KOREA on Oct. 30, 1996 under 35 U.S.C. §119. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method for forming an isolation layer of a semiconductor device and, more particularly, to a method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. 
   2. Discussion of the Related Art 
   A conventional method for forming an isolation layer of a semiconductor device will be described with reference to the accompanying drawings. 
   Referring to  FIGS. 1   a  through  1   d,  there is illustrated a conventional method for forming an isolation layer of a semiconductor device. As shown in  FIG. 1   a,  a first insulating layer  2  is formed on a semiconductor substrate  1 , by a CVD process. In this case, the first insulating layer  2  has a thickness of 1 μm. The first insulating layer  2  is partially patterned by an RIE (reactive ion etching) process until a predetermined portion of the substrate  1  is exposed, thereby forming a contact hole. Next, a second insulating layer  3  of a thickness of 0.1 μm is formed on the entire surface inclusive of the exposed substrate  1  by the CVD process. 
   Subsequently, etch back is applied to the second insulating layer  3  so as to form a sidewall spacer  3   a  and then, the substrate  1  is etched by a predetermined depth with the first insulating layer  2  and the sidewall spacer  3   a  serving as masks, as shown in  FIG. 1   b.  In this case, the substrate is etched by a width of 0.1 μm and a depth of 0.5 μm. 
   Next, the first insulating layer  2  and the sidewall spacer  3   a,  as shown in  FIG. 1   c,  are removed to expose the surface of the substrate  1 . Also, the surface of the substrate  1  is annealed for recovering the damage of the substrate  1  caused by the removal of the first insulating layer  2  and the sidewall spacer  3   a,  and there is grown an oxide layer  4  of a width of 200 Angstroms is grown on the entire surface of the substrate  1 . After the growth, a third insulating layer  5  of a thickness of 3000 Angstroms is formed on the oxide layer  4  by the CVD process and then, a photoresist layer is coated on the third insulating layer  5 . Subjected to exposure and development, the photoresist layer is patterned to form a photoresist pattern  6 . 
   Referring to  FIG. 1   d,  with the photoresist pattern  6  serving as a mask, the third insulating layer  5  is partially removed by the RIE process. After this removal, boron ions are implanted into the substrate three times, and each time the boron ions have a different energy. In this case, the amount of boron ions is 3×10 12  ions/cm 2  and energies of the ions are 130 KeV, 180 KeV and 260 KeV. 
   The conventional method for forming an isolation layer of a semiconductor device has the following problems. 
   First, the semiconductor substrate  1  may be damaged due to the etching of an isolation region of the substrate  1 . Further, since the isolation region is etched at a very steep slope angle, a focus of charge currency is generated, thereby causing leakage current. 
   Second, when the isolation region is a large pattern, an etch width of the substrate  1  is increased so that the planarization of the surface of the isolation region becomes inferior. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention is directed to a method for forming an isolation layer of a semiconductor device that substantially obviates one or more of problems due to limitations and disadvantages of the related art. 
   An object of the invention is to provide a method for forming an isolation layer of a semiconductor device which has an excellent planarization regardless of a width of the isolation region. 
   Another object of the invention is to simplify the forming process steps by carrying out a photolithography process once for both first and second isolation regions at the same time. 
   Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
   To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for forming an isolation layer of a semiconductor device in which a substrate has a first isolation region and a second isolation region which is wider than the first isolation region includes the steps of: forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in center area of the first recess in the first isolation region; and filling the first, second and third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device in which the isolation regions have different widths, the first isolation region which is relatively narrower in width than the second isolation region. 
   Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: 
       FIGS. 1   a  through  1   d  are cross-sectional views showing a conventional method for forming an isolation layer of a semiconductor device; 
       FIG. 2  is a layout of a semiconductor device in accordance with a first embodiment of the present invention; 
       FIG. 3  is a cross-sectional view cut along line III-III′ showing a structure of  FIG. 2 ; 
       FIG. 4  is a cross-sectional view cut along line IV-IV′ showing a structure of  FIG. 2 ; 
       FIGS. 5   a - 5   g  are cross-sectional views showing a method for forming an isolation layer of a semiconductor device in accordance with line III-III′ and line V-IV′ of  FIG. 2 ; 
       FIG. 6  is a layout of a semiconductor device in accordance with a second embodiment of the present invention; 
       FIG. 7  is a cross-sectional view cut along line VII-VII′ of  FIG. 6 ; 
       FIG. 8  is a cross-sectional view cut along line VIII-VIII′ of  FIG. 6 ; and 
       FIGS. 9   a-   9   g  are cross-sectional views showing a method for forming an isolation layer of a semiconductor device in accordance with line VII-VII′ and line VIII-VIII′ of FIG.  6 . 
   

   Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
     FIG. 2  is a layout of a semiconductor device in accordance with a first embodiment of the present invention.  FIG. 3  is a cross section cut along line III-III′ showing a structure of  FIG. 2 ,  FIG. 4  is a cross section cut along line IV-IV′ showing a structure of  FIG. 2 , and  FIGS. 5   a  through  5   g  are cross sections showing a method for forming an isolation layer of a semiconductor device in accordance with line III-III′ and line IV-IV′. In this case, depending on the characteristics of the semiconductor device and its design, widths of the various isolation regions may vary.  FIG. 2  illustrates isolation regions of a semiconductor device with varying widths. 
   Referring to  FIGS. 3 and 4 , the isolation region  32  which is relatively narrow, when compared to isolation region  33 , and the isolation region  33  which is relatively wide, are etched by a predetermined depth and then, an insulating layer  36  fills the etched areas so that the insulating layer  36  in the isolation regions evenly planarizes the surface of the substrate. However, in the relatively narrow isolation region  32 , the substrate is etched deep to form a recess in a conventional manner. In contrast, in the relatively wide isolation region  33 , the substrate is partially etched to form a plurality of island regions thereon. 
   Referring to  FIGS. 5   a  through  5   f,  there is illustrated a method for making an isolation layer of a semiconductor device depending on a width of an isolation region according to a first embodiment of the present invention. These figures are cross-sectional views showing a method for forming an isolation layer corresponding to the  FIG. 2  cut along lines III-III′ and IV-IV′. 
   First, in order to make a semiconductor device having a relatively narrow isolation region  32  and a relatively wide isolation region  33 , a first insulating layer  31  is formed on a semiconductor substrate  30  and then, a photoresist layer (not shown) is coated on the first insulating layer  31 , as shown in  FIG. 5   a.  The photoresist layer is subjected to exposure and development and patterned, so as to form a photoresist pattern (not shown). 
   Subsequently, with the photoresist pattern serving as a mask, the first insulating layer  31  is partially etched so as to expose the surface of the substrate  30  thereunder, thereby forming a relatively narrow first isolating region  32  and a relatively wide second isolation region  33 . In this case, the first insulating layer  31  in the relatively narrow isolation region  32  is removed to expose the entire width of the substrate  30 . In contrast, the first insulating layer  31  in the relatively wide isolation region  33  is partially removed to make island regions  37  having a predetermined width and predetermined gaps between the island regions. Herein, the width of the first insulating layer  31  removed in the relatively wide second isolation region  33  is narrower than that in the relatively narrow first isolation region. 
   Referring to  FIG. 5   b,  the photoresist pattern is removed. With the first insulating layer  31  as a mask, the substrate exposed in both the first and second isolation regions  32 ,  33  is etched by a predetermined depth to form a first recess  32   a,  and a plurality of second recesses  33   a.  That is to say, there is formed only one first recess  32   a  in the first isolation region  32 , while there are formed a plurality of recesses  33   a  in the second isolation region  33 . For the first insulating layer  31 , either a silicon nitride layer or a silicon oxide layer is used. The first and second isolation regions  32 ,  33  are patterned at the same time. 
   In another embodiment, the RIE (reactive ion etching) process or the CDE (chemical dry etching) process is applied to the substrate  30  to form the first and second recesses  32   a,    33   a.  Further, the second recesses  33   a  are etched to have a narrower width than that of the first recess  32   a  and then, ion implantation of a channel stop is performed. 
   Next, the CVD process is applied to the substrate  30  inclusive of the first insulating layer  31  to form a protecting layer  34 , as shown in  FIG. 5   c.  In this case, either a silicon nitride layer or silicon oxide layer is used as the protecting layer  34 , which is formed to be thick enough to fill in the second recesses  33   a  between gaps of the first insulating layer  31 . 
   Referring to  FIG. 5   d,  etch back is applied to the protecting layer  34  thicker than the thickness of the protecting layer  34 , so as to form a protecting layer sidewall spacer  34   a  in the side of the first recess  32   a,  and so as to fill in the second recesses  33   a.  Since the second recesses  33   a  have a narrower width than the first recess  32   a  does, a predetermined portion of the substrate  30  is exposed surrounding the protecting layer sidewall spacers  34   a  on the side of the first recess  32   a,  whereas the second recesses  33   a  are filled in completely with the protecting layer  34 . 
   Thereafter, utilizing the protecting layer sidewall spacer  34   a  as a mask, the exposed area of the substrate  30  in the first recess  32   a  is etched by a predetermined depth to form a third recess  35  as shown in  FIG. 5   e.  In this case, with the first insulating layer  31  and the protecting layer  34  serving as masks, ion implantation of a channel stop may be performed, and then the protecting layer sidewall spacers  34   a  in the first recess  32   a  and the protecting layer  34  in the second recess are removed. 
   Referring to  FIG. 5   f,  using a CMP (chemical mechanical polishing) process, the first insulating layer  31  in the second isolation region  33  is removed and the island regions  37  of the substrate  30  thereunder are removed by a predetermined depth. With the first insulating layer  31  serving as a mask, ion implantation of a channel stop is carried out. 
   Finally, referring to  FIG. 5   g,  a second insulating layer  36  is formed on the entire surface of the substrate inclusive of the first, second, and third recesses  32   a,    33   a,    35 , and is subjected to etch back so that the first, second, and third recesses  32   a,    33   a,    35  are filled in with the second insulating layer  36 . The first insulating layer  31  is removed, thereby forming an isolation layer for isolating one device from another. In this case, the second insulating layer  36  must be thick enough to fill in the first, second, and third recesses  32   a,    33   a,    35  and then, is subjected to etch back. Herein, the second insulating layer  36  is an oxide layer. The CMP process used as the etch back is subjected to the second insulating layer, thereby planarizing the surface of the substrate  30 . In the CMP process, polishing particles such as Alumina or silica, and the polishing solvent such as ammonium fluoride and aqueous ammonia are used. 
     FIG. 6  is a layout of a semiconductor device according to a second embodiment of the invention,  FIG. 7  is a cross-sectional view cut along line VII-VII′ of  FIG. 6  showing a structure of the device, and  FIG. 8  is a cross-sectional view cut along line VIII-VIII′ of  FIG. 6  showing a structure of the device.  FIGS. 9   a  through  9   f  are cross-sectional views cut along line VII-VII′ and line VIII-VIII′ of  FIG. 6  showing a method for forming an isolation layer of the semiconductor device. 
   How wide an isolation layer is depends on performance of the device and its design. 
   Referring to  FIG. 6 , there is illustrated an isolation layer of a semiconductor device where widths between isolation regions are different. 
   Referring to FIG.  7  and  FIG. 8 , the relatively narrow isolation region  53  and the relatively wide isolation region  54  are etched by predetermined different depths respectively, and the isolation layer  57  is formed to protrude in a round shape from the substrate. 
   In the relatively narrow isolation region  53 , the recess is etched in a rounded shape, whereas, in the relatively wide isolation region  54 , the recesses are connected in a dumbbell shape. 
   Referring to  FIGS. 9   a  through  9   f,  there is illustrated another method for forming an isolation region for separating devices from one another according to line VII-VII′ and line VIII-VIII′ of FIG.  6 . 
   Referring to  FIG. 9   a,  in order to manufacture a semiconductor device having a relatively narrow first isolation region  53  and a relatively wide second isolation region  54 , a first insulating layer  51  and then a second insulating layer  52  are formed on a semiconductor substrate  50 , a mask layer for preventing oxidation is formed, and a photoresist layer (not shown) is coated on the second insulating layer  52 . Subjected to exposure and development, the photoresist layer is patterned to form a photoresist pattern (not shown) and then, the first and second insulating layers  51 ,  52  in the relatively narrow first isolation region  53  and the relatively wide second isolation region  54  respectively are partially removed. The first and second insulating layers  51 ,  52  in the first isolation region  53  are removed for the entire width to expose the entire substrate thereunder. In contrast, the first and second insulating layers  51 ,  52  in the relatively wide second isolation region  54  are partially removed so that only island regions  58  having a predetermined width remain. In this case, the first and second insulating layers  51 ,  52  removed in the relatively wide second isolation region  54  have a width at least narrower than the relatively narrow first isolation region  53 . 
   The first insulating layer  51  is an oxide layer and the second insulating layer  52  is a silicon nitride layer. The first and second insulating layers  51 ,  52  are mask layers for preventing oxidation. A stack of a silicon nitride layer and a silicon oxide layer is used instead of a stack of an oxide layer and a silicon nitride layer. 
   Referring to  FIG. 9   b,  with the first insulating layer  51  and the second insulating layer  52  serving as masks, the exposed area of the substrate  50  in the first and second isolation regions  53 ,  54  is etched by a predetermined depth to form first and second recesses  53   a,    54   a.  In a sectional view, there is one first recess  53   a  in the first isolation region  53 , and there are a plurality of second recesses  54   a  in the second isolation region  54 . The RIE process or the CDE process is applied to the substrate  50  to form first and second recesses  53   a,    54   a.  After the second recesses  54   a  are formed to have a width narrower than that of the first recess  53   a,  ion implantation of a channel stop is carried out with the photoresist layer and the first and second insulating layers  51 ,  52  serving as masks. 
   Referring to  FIG. 9   c,  the photoresist layer is removed, and the CVD process is applied to the substrate  50  inclusive of the second insulating layer  52 , thereby forming a protecting layer  55 , which is formed of a silicon oxide and has a thickness that fill in the second recesses  54   a.    
   Referring to  FIG. 9   d,  etch back is applied to the protecting layer  55  thicker than the thickness of the protecting layer  55  so that the protecting layer  55  forms a protecting layer sidewall spacer  55   a  in the first recess  53   a  and fills in the second recesses  54   a.  In other words, since the second recesses  54   a  have a narrower width than the first recess  53   a,  a predetermined portion of the substrate is exposed surrounded by the protecting layer sidewall spacer  55   a  formed in the first recess  53   a.  In contrast, the second recesses  54   a  are filled in with the protecting layer  55 . 
   Referring to  FIG. 9   e,  with the protecting layer sidewall spacer  55   a  serving as a mask, the etched area of the substrate  50  in the first recess  53   a  is etched by a predetermined depth to form a third recess  56 . In this case, with the first and second insulating layers  51 ,  52  and the protecting layer  55  serving as masks, ion implantation of a channel stop may be achieved, and the protecting layer sidewall spacer  55   a  in the first recess  53   a  and the protecting layer  55  in the second recesses  54   a  are removed. 
   Referring to  FIG. 9   f,  with the first and second insulating layers  51 ,  52  serving as masks, the first, second, and third recesses  53   a,    54   a,  and  56  are annealed in an oxide environment at a temperature not less than 800° C., thereby forming a third insulating layer  57  of a thickness of 3000-5000 Angstroms. At the same time, in the second isolation region  54 , the third insulating layer  57  and the first insulating layer  51  are interconnected to each by a “bird&#39;s beak”. Thereafter, a portion  58  of the first insulating layer  51  is thicker than a portion  59  of the first insulating layer  51 . 
   As shown in  FIG. 9   g,  the second insulating layer  52  and the first insulating layer  51  are selectively removed to leave the thicker portion  58  of the first insulating layer  51 . The third insulating layer  57  is an oxide layer. 
   The methods of the present invention have the following advantages. 
   First, since the isolation layer is formed vertically as well as laterally in the first and second isolation regions, insulation characteristics of the device are enhanced. 
   Second, since a mask is used to form the first and second isolation regions in the photolithography process at the same time, the process steps are simplified. 
   The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.