Abstract:
A multi-chips bumpless assembly package with a patterned conductive layer, a patterned dielectric layer and an insulation layer interposed between the chips is provided, which can shorten the distance of the electrical connection between the chips so as to upgrade the electrical performance of the assembly package and make the package thinner and thinner. Moreover, a manufacturing method thereof is also provided to form a package with high electrical performance.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of Invention  
         [0002]     This invention relates to a semiconductor assembly package. More particularly, the present invention is related to a multi-chips bumpless assembly package and a manufacturing method thereof.  
         [0003]     2. Related Art  
         [0004]     Integrated circuits (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.  
         [0005]     Originally, the electrical connections between the chips comprise wire bonding connection and flip chip connection. In wire bonding connection, a wire bonder is disposed above the first chip and then the tip of the conductive wire is melting to shape into a ball. Next, the conductive wire is bonded onto the bonding pad of the first chip. Then, the wire bonder is moved and disposed above the corresponding bonding pad of the second chip, and then the conductive wire will be bonded onto the corresponding bonding pad of the second chip to complete wire bonding the first chip and the second chip. In flip chip bonding, a plurality of bumps are formed on the bonding pads of the chip, and then flipped and bonded to another chip by a reflow process.  
         [0006]     However, as shown above, in the wire-bonding package, when the chips are stacked with each other to form a stacked package, the wires connecting the upper chip and the substrate are longer. In such a manner, said wires are easily to be damaged due to the molding flow attacking the wires. In addition, when the flip chip are stacked with each to form a stacked package, there are usually needed to form a redistributed layers on the back side of the chips and utilizing another wires for electrically connecting the chips to the substrate. Thus, the process will become more complex. Besides, as shown in  FIG. 1A , it illustrates a multi-chips stacked package patented in U.S. Pat. No. 5,399,898 to Michael D. Rostoker et al. entitled “Multi-Chip Semiconductor Arrangements Using Flip Chip Dies” and each of said chips  30  has bumps  20 A and  20 B formed on the double sides; and the bumps  20 B on the upper side are utilized to connect to an external devices, such as the same chip  30  as shown in  FIG. 1B , placed over the chip  30  and the bumps  20 A on the lower side are utilized to connect to an external device, such as the contact  10  of the substrate as shown in  FIG. 1B , disposed under the chip  30 . To be noted, the bumps  20 A and  20 B are electrically connected to each other through the electrical traces formed inside the chip  30 . However, the manufacturing method of such chip is more complex than conventional one. Besides, it is more difficult to control the collapse of the bumps  20 A and  20 B, when such chip is interposed between electronic devices, due to the bumps  20 A and  20 B formed on the double sides.  
         [0007]     Therefore, providing another semiconductor assembly package to solve the mentioned-above disadvantages is the most important task in this invention.  
       SUMMARY OF THE INVENTION  
       [0008]     In view of the above-mentioned problems, this invention is to provide a multi-chips bumpless assembly package with a conductive layer and a dielectric layer interposed between the chips, which can shorten the distance of the electrical connection between the chips so as to upgrade the electrical performance of said assembly package and make the package thinner and thinner.  
         [0009]     To achieve the above-mentioned, a multi-chips bumpless assembly package is provided, wherein the package comprises a first chip, a first encapsulation encompassing the first chip, a patterned first dielectric layer formed over the first chip and the first encapsulation, a patterned first conductive layer formed over the patterned first dielectric layer, an insulation layer formed over the patterned first dielectric layer, a second chip disposed over the insulation layer, a second encapsulation encompassing the second chip, a through hole penetrating the insulation layer and the second encapsulation and exposing the patterned first conductive layer, a conductive material filling in the through hole, a conductive trace disposing on the second chip and the second encapsulation and connecting the conductive material and the second bonding pads, a patterned second dielectric layer formed over the second chip, the second encapsulation and the conductive trace, a patterned second conductive layer formed over the patterned second dielectric layer, a patterned third dielectric with vias layer formed over the patterned second conductive layer and the patterned second dielectric layer, and a plurality of bumps formed in the vias and electrically connected to the patterned second conductive layer. Furthermore, therein, the first chip and the second chip are electrically connected with each other through the patterned first conductive layer, the conductive trace, the conductive material and the patterned second conductive layer.  
         [0010]     In addition, a manufacturing method of said package is provided to achieve the mentioned objective. The method mainly comprises the following steps. First, a first chip with a first encapsulation encompassed is provided, wherein first bonding pads of the first chip is exposed out of the encapsulation. Second, a patterned first dielectric layer is provided over the first chip and the first encapsulation except the first bonding pads so as to leave the bonding pads exposed through a plurality of first vias of the patterned first dielectric layer. Next, a patterned first conductive layer is provided over the patterned first dielectric layer and connected to the first bonding pads through the first vias. Then, an insulation layer is placed over the patterned first conductive layer. Afterwards, a second chip and a second encapsulation are disposed on the insulation layer and said second encapsulation encompasses the second chip. Next, a plurality of through holes penetrating the second encapsulation and the first insulation are formed and expose portions of the patterned first conductive layer. Then, a conductive material, such as conductive epoxy and plated conductive metal, is filled in the through holes and a conductive trace is disposed on the second chip and the second encapsulation and connects the conductive material and the second bonding pads. Next, a patterned second dielectric layer is provided over the second chip, the conductive trace and the second encapsulation except the second bonding pads so as to leave the second bonding pads exposed through a plurality of second vias of the patterned second dielectric layer. Then, a patterned second conductive layer is formed over the patterned second dielectric layer and electrically connects the second bonding pads through a second vias of the patterned second dielectric layer. Afterwards, a patterned third dielectric layer with a plurality of third vias is formed over the patented second conductive layer and the patterned second dielectric layer. Finally, a plurality of bumps are formed in the third vias and connect to the patented second conductive layer so as to electrically connect to the second bonding pads.  
         [0011]     According to this invention, the chips are electrically connected to each other through the patterned first conductive layer, the conductive material, and the conductive trace; and the chips are electrically connected to external electronic devices through the bumps and the patterned second conductive layer. Namely, the patterned first conductive layer, the conductive material, and the conductive trace serve as the electrical connections between the chips and the patterned second conductive layer and the bumps are taken as the electrical connection between the chips and external electronic devices. In such a manner, the distance of the electrical connection between the chips and the external devices is short. Thus, the characterization impedance can be lowered to prevent the signal from being attenuated. Furthermore, this invention can prevent the parasitics of the inductance and the capacitor from being induced so as to be suitable to the assembly package designed for performing high-circuits. Moreover, it makes the thickness of the package thinner and thinner. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The invention will become more fully understood from the detailed description given herein below illustrations only, and thus are not limitative of the present invention, and wherein:  
         [0013]      FIG. 1A  is a cross-sectional view of a conventional chip having double-sided bumps formed thereon;  
         [0014]      FIG. 1B  is a cross-sectional view of a conventional flip-chip package with the chip of FIG lA;  
         [0015]      FIGS. 2A  to  2 G are partially enlarged cross-sectional views showing the progression of steps for forming a multi-chips bumpless assembly package according to the first embodiment of the present invention;  
         [0016]      FIG. 2G  is a cross-sectional view of a multi-chips bumpless assembly package according to the first embodiment of the present invention;  
         [0017]      FIG. 2H  is a cross-sectional view of a multi-chips bumpless assembly package according to the second embodiment of the present invention; and  
         [0018]      FIG. 2I  is a cross-sectional view of a multi-chips bumpless assembly package according to the third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     The multi-chips bumpless assembly package according to the preferred embodiments of this invention will be described herein below with reference to the accompanying drawings, wherein the same reference numbers refer to the same elements.  
         [0020]      FIGS. 2A  to  2 G are partially enlarged cross-sectional views showing the progression of steps for forming a multi-chips bumpless assembly package according to the first preferred embodiment of this invention.  
         [0021]     As shown in  FIG. 2A , a plurality of first chips  100   a  with a plurality of first bonding pads  102   a  formed on a first active surfaces are placed on a first protection film  101  through attaching the first bonding pads  102   a  to the film  101 . Therein, the first chips  100   a  are separated from each other to form a plurality of first gaps. Next, a first encapsulation  103  is provided to be filled in the first gaps so as to encompass the first chips  100   a.  To be noted, the first encapsulation  103  can be made of dielectric materials. Then, optionally, a grinding process is performed to have the first back surfaces of the chips  100   a  exposed out of the encapsulation  103  and make said first back surfaces of the chips  100   a  more flat to ensure the reliability of forming conductive layers between the first chips  100   a  and the other chips.  
         [0022]     Next, the first chips  100   a  with the first encapsulation  103  encompassed are flipped over and placed on a carrier  105 , and then the first protective film  101  is removed to have the first bonding pads  102   a  exposed to the outside. Then, a first dielectric layer is formed over the first chips  100   a  and the first encapsulation  103 , and a photo-lithography process and an etching process are performed through disposing a photo-resist layer, serving as a mask, on the first dielectric layer to remove a portion of the first dielectric layer  104  to form a plurality of first vias  104   a  exposing the first bonding pads  102   a  so as to form a patterned first dielectric layer  104 , and finally the photo-resist layer is removed as shown in  FIG. 2B . In addition, the carrier  105  may be a metal plate  105 , serving as a heat spreader, wherein the carrier  105  is provided to place below the first back surfaces of the first chips  100   a,  and is attached to the first chips  100   a  and the first encapsulation  103  through an adhesive  106 .  
         [0023]     Moreover, as shown above, the first encapsulation  103  can be placed on the metal plate  105  before the first chips  100  are placed over the metal plate  105 . Namely, after a metal plate  105  is provided, the first encapsulation  103  is disposed on the metal plate  105  with a plurality of spaces therebetwen for accommodating the first chips  100 . Afterwards, the first chips  100  are placed in the spaces, and then a first dielectric layer is disposed on the first chips  100  and the first encapsulation  103 . And then the same steps are performed as shown above to form the patterned first dielectric layer  104  with a plurality of vias  104   a  therein. In addition, the first encapsulation can be made of a photosensitive material. In such a manner, when the photosensitive material is disposed to cover the first chips  100 , and then a photo-lithography process is performed to form first vias  107   a  in the first encapsulation, which expose the first bonding pads  102   a  as shown in  FIG. 2C . Thus, it is unnecessary to form additional photo-resist layer to remove the portions of the first encapsulation to form the first vias  107   a  to expose the first bonding pads  102   a.    
         [0024]     Moreover, as shown in  FIG. 2D  and referring to  FIG. 2B  again, a patterned first conductive layer  108  is formed on the first patterned dielectric layer  104  and the first bonding pads  102   a  through the first vias  104   a.  Said patterned first conductive  108  is formed according to the following steps. Firstly, a conductive layer, such as a metal layer, is formed on the patterned first dielectric layer, no matter said made of the photo-sensitive material as shown in  FIG. 2C  or the dielectric material as shown in  FIG. 2B , and the first bonding pads  102   a.  Then, a lithography process and an etching process are performed to remove a portion of the first conductive layer to form the patterned first conductive layer  108 .  
         [0025]     Next, referring to  FIG. 2E , before a plurality of second chips  100   b  are provided above the patterned first conductive layer  108 , there is an insulation layer  109  formed above the first chips  100   a  and over the patterned conductive layer  108  and the patterned first dielectric layer  104 . After the second chips  100   b  are placed on the insulation layer  109 , a second encapsulation  112  is formed between the second chips  100   b  so as to have the second encapsulation  112  encompassing the second chips  100   b.  Therein, the second encapsulation  112  can be made of a photo-sensitive material or a dielectric material. Then, the typical photolithography process and the etching process are performed to form a plurality of through holes  115 , penetrating the insulation layer  109  and the second encapsulation  112 , exposing the patterned first conductive layer  108 .  
         [0026]     Then, as shown in  FIG. 2F , a conductive material  118 , such as conductive epoxy and plated conductive metal, is filled in the through holes  115  and a conductive trace  120  is disposed on the second chip  100   b  and the second encapsulation  112  and connects the conductive material  118  and the second bonding pads  102   b.  Next, as shown in  FIG. 2G , a patterned second dielectric layer  125  is provided over the second chip  100   b  and the second encapsulation  112  except portions of the second bonding pads  102   b  so as to leave the portions of the second bonding pads  102   b  exposed through a plurality of second vias  125   a  of the patterned second dielectric layer  120 . Then, a patterned second conductive layer  130  is formed over the patterned second dielectric layer  125  and electrically connects the portions of the second bonding pads  102   b  through a second vias  125   a  of the patterned second dielectric layer  125 .  
         [0027]     Afterwards, referring to  FIG. 2G  again, a patterned third dielectric layer  135  with a plurality of third vias  135   a  is formed over the patented second conductive layer  130 . Finally, a plurality of bumps  150  are formed in the third vias  135   a  so as to electrically connect to the second bonding pads  102   b  and to serve as external terminals for connecting to external electronic devices. In addition, the bumps  150  are formed by solder ball placing, screen printing solder pastes and plating solder materials, and reflowing such solder bumps to secure to the patterned second conductive layer  130 . To be noted,  FIG. 2G  illustrates the multi-chips bumpless assembly package according to the first embodiment.  
         [0028]     Furthermore, the second chips  100   b  and the second encapsulation  112  can be made in advance. Namely, after the insulation layer  109  is formed above the first chips  100   a,  there are provided the second chips  100   b  with the second encapsulation  112  encompassing the second chips  100   b  to mount onto the insulation layer  109  through an adhesive  160  as shown in  FIG. 2H  which is the difference of this second embodiment from the first embodiment as shown above.  
         [0029]     In addition, referring to  FIG. 2I , which illustrates the multi-chips bumpless assembly package according to the third embodiment. Therein, there is further formed another metal layer  170 , serving as a bottom plate, on the patterned first dielectric layer  104 . And a dielectric material  165  is provided and disposed on the metal layer  170  and then another metal layer  172 , serving as a top plate, is formed on the top of the dielectric material  165 . In other words, the bottom plate, the dielectric material and the top plate form an embedded passive component in the package, and this is the difference of the third embodiment from the first embodiment as shown above.  
         [0030]     Although the invention has been described in considerable detail with reference to certain preferred embodiments, it will be appreciated and understood that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.