Abstract:
A ramp generator includes a resistance ladder ( 10 ) supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a ramp generator that can be used in an analog-to-digital converter (ADC), and to an ADC including a ramp generator. A field of application for the present invention is in solid-state image converters. 
   BACKGROUND OF THE INVENTION 
   In CMOS image sensors an ADC arrangement is used wherein a voltage of each pixel is compared with a ramp voltage. At the point where the ramp voltage equals the pixel voltage, a comparator latches a digital count value into a memory. In this architecture, the resolution of the ADC is directly related to the resolution and linearity of the ramp generation circuitry. 
   Known ramp generators using ADCs, switched capacitor integrators, charge pumps or the use of current into a capacitor suffer from a number of problems, such as the following: offsets, achieving the necessary gain within the time constants required for settling, area and power inefficiency, non-monotonicity, and process/temperature dependence. 
   Shift registers in combination with a resistance ladder, as shown in  FIG. 1 , have also been used as ramp generators. In this arrangement the ramp voltage Vramp is generated by sequentially closing each switch  102  on the resistance ladder  104 , thereby tapping the master voltage Vm at different intervals. The sequential closing of the switches is provided by a shift register  106  which has a number of shift register elements  108  corresponding to the number of resistive elements in the resistance ladder  104 . The shift register  106  is provided with a clock pulse signal and a token signal where the token signal has a single high pulse. This single high pulse is passed through the shift register elements  108 , and thereby closing the respective switches  102  on each clock pulse. 
   This type of ramp generator can pose a significant problem in terms of physical size since a 12 bit ramp generator requires 2048 shift register elements and 2048 resistive elements. In terms of integrated circuits (ICs), shift register elements are relatively large, requiring a minimum of 8 transistors. This can be prohibitive when IC space is at a premium and the quality of ramp generation is paramount. 
   Also, shift register elements have been used to control more than one switch, thereby reducing the number of shift register elements required. The methods used have not enabled a reduction in size of the overall ramp generator, but in fact have increased the overall size by using a digital control circuit to control the closing of the switches. This had advantages in other areas but significantly increases the complexity and the physical size of the ramp generator when integrated on an integrated circuit. 
   SUMMARY OF THE INVENTION 
   An object of the present invention is to provide a ramp generator that is suitable for inclusion in an ADC in an image sensor, and one that avoids or mitigates the above described problems. 
   The present invention provides a ramp generator comprising a resistance ladder formed by a number of resistance elements connected in series, a current source arranged to pass a controlled current through the resistance ladder, a voltage output, and a plurality of switches for connecting the voltage output to points on the resistance ladder between the resistance elements. Switch control means comprise a plurality of switch controls for closing the switches in a sequential manner. The ramp generator may be characterized in that it also comprises decoding means to determine the current switch that is being operated. The decoding means enables the plurality of switch controls to control a plurality of switches. 
   The switch control means may comprise a shift register, which comprises a number of shift register elements connected to receive a clock signal and a token signal from the decoding means. The decoding means may enable the shift register to receive the token signal more than once, thereby creating a looped shift register. 
   The decoding means may also enable the switch control means to operate a set of switches corresponding to a set of resistive elements proportional, in number, to half the number of switch controls. The decoding means may receive an indication that the token signal has passed through half the number of switch controls. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention will now be described, by way of example only, with reference to the drawings, in which: 
       FIG. 1  is a block diagram of a ramp generator based on a shift register architecture in accordance with the prior art; and 
       FIG. 2  is a block diagram of a ramp generator in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 2 , a resistance ladder  200  is formed by a series of resistors R 11  . . . R 44 . The resistance ladder  200  is supplied with a constant current I by a constant current source  202 . An output V Ramp  can be tapped from each point along the resistance ladder  200  by the operation of switches S 11 -S 44 . 
   By operating the switches S 11 -S 44  sequentially, with only one switch being closed at a time, a stepped ramp voltage will be obtained at V RAMP . If all the resistors R have the same value R UNIT , then
 
 V   RAMP   =N*R   UNIT   *I 
 
where N is the number of resistors in series when the respective switch is closed.
 
   The switches S 11 -S 44  are operated by a combination of a control logic block  204  and a shift register  206 . The control logic block  204  accepts a clock input  208  and a token input  210 . The clock input  208  is a regular clock pulse signal at a pre-determined frequency which ultimately governs the length of time a single voltage ramp takes to rise. 
   The token input  210  is a single high pulse which is placed initially at the shift register element SR 1  and moves one shift register element each time a clock pulse signal is received. The control logic block  204  initializes the shift register  206  by passing the clock input  208  and the token input  210 . At the same time, the control logic block  204  also initializes the switches S 11 -S 14  of the first row of the resistance ladder. When the token input  210  is at the shift register element SR 1 , the high signal is passed through the OR gate  212  and switch S 11  closes. The output ramp voltage V RAMP , in this case, is then equal to:
 
 V   RAMP =1 *I=V   m /16
 
As the token input  210  moves to the next shift register element on the next clock pulse signal, S 11  opens and S 12  closes. The output ramp voltage V RAMP  changes to:
 
V RAMP =2 *R   UNIT   *I =2 *V   m /16
 
This continues on each clock pulse signal for closing the next switch in sequence, and opening the previously closed switch until when the token input  210  passes between shift register elements SR 4  and SR 5 . At this point, the control logic block  204  receives a signal V turn  which deactivates the switches S 11 -S 14  on rowl and activates the switches S 21 -S 24  on row 2 .
 
   The token input  210  now at shift register element SR 5  passes through the common OR gate  212  and closes switch S 24  as the switches S 21 -S 24  in row 2  have been enabled by control logic block  204 . Switches S 23 , S 22  and S 21  are then closed in sequence by the token input  210  passing between the shift register elements SR 6 , SR 7  and SR 8 . 
   The token input  210  is then received by control logic block  204  which disables switches S 21 -S 24  and enables switches S 11 -S 34 . The token input  210  is then passed back to shift register element SR 1  and switch S 31  is closed. The process is then repeated as in the first loop, with the only difference being that the control logic block  204  disables row 3  of switches S 31 -S 34  and enables row 4  of switches S 41 -S 44  when the V TURN  signal is received. 
   Obviously,  FIG. 2  shows that a scaled down version of this architecture can be applied to obtain the required resolution. Typically, this is 12 bits and would correspond to 4096 resistors and the same number of shift register elements, and therefore rows of resistors and switches could be chosen dependent on the architecture required. 
   The physical space required on an integrated circuit (IC) by an embodiment of the present invention is significantly less compared with prior art shift register ramp generators. This is due to using less shift register elements, which are comparatively large on an IC, and which usually requires at least 8 transistors. In addition, the decoding means that allows the shift register elements to selectively operate more than one switch comprises logic circuits which do not require a significant amount of IC space in comparison to the amount of space saved by using less shift register elements. 
   The proportion of shift register elements to resistive elements is a matter of choice and any combination could be used. For example, it may be desirable to have 3 rows of shift register elements rather than two as described in the specific embodiment, and therefore having the number of rows of restive elements proportional to 3. 
   The ramp generator of the present invention is particularly useful in an ADC circuit but may be used in other applications. Moreover, the ADC circuit may form part of an image sensor chip, but is not limited to such use.