Abstract:
A peak detector for detecting a peak value of a burst signal in a burst mode optical receiver is disclosed, which comprises: an amplifying terminal configured to reduce an offset of a peak value in a received burst signal using feedback in the peak detector; a transistor that functions as a diode when a positive signal is received from the amplifying terminal; a peak hold capacitor for charging a peak value when the transistor received the positive signal; a signal amplitude detector to monitor the received burst signal amplitude; and a current source to drive a current responsive to the output signal amplitude detector.

Description:
CLAIM OF PRIORITY  
         [0001]    This application claims priority to an application entitled “Peak and bottom detectors in burst mode optical receiver,” filed in the Korean Intellectual Property Office on Jun. 11, 2003 and assigned Serial No. 2003-37557, the contents of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a burst mode optical receiver, and more particularly to peak and bottom detectors in a burst mode optical receiver.  
           [0004]    2. Description of the Related Art  
           [0005]    In order to more rapidly transmit more information to subscribers, next generation communication systems have required a fiber to the home (hereinafter, referred to as FTTH), in which an optical line is provided in each home. However, the FTTH has financial deployment limitations, in that the cost to replace existing subscriber copper wire networks are significant. To lower costs, passive optical networks (hereinafter, referred to as PONs) have been considered in constructing an FTTH.  
           [0006]    The PON includes an optical line termination (hereinafter, referred to as OLT) in a central office, an optical splitter and one or more optical network unit (hereinafter, referred to as ONU) corresponding to subscribers.  
           [0007]    When communication from one OLT to a plurality of ONUs is performed, data is transmitted downward simultaneously. When a plurality of ONUs transmit data to the OLT, a time division multiple access (TDMA) technique is used in order to avoid a collision between signals transmitted by each ONU. Further, since each ONU has a different distance from the OLT, each signal transmitted from the ONUs with the same optical output has different optical power in the angle of the receiver of the OLT. Consequently, the receiver of the OLT requires a burst mode optical receiver to process signals with the various optical powers.  
           [0008]    [0008]FIG. 1 is a circuit diagram of a burst mode optical receiver using a double feedback structure. Referring to FIG. 1, the burst mode optical receiver  60  with the double feedback structure includes a photodiode  62  for converting an optical signal into an electrical current signal proportional to the optical signal, a gain controllable amplifier (hereinafter, referred to as GCA)  64  for amplifying the current signal outputted from the photodiode  62  to a voltage signal, an automatic gain control loop  66  for adjusting an amplifier&#39;s gain from a differential output of the GCA  64  by means of a feedback loop and a DC offset control loop  68  for adjusting DC offsets of two differential output signals from the differential output of the GCA  64 . The burst mode optical receiver  60  with the feedback structure described above may obtain satisfactory performance/characteristics. However, the feedback structure generally requires quite a long time for feedback stability. Therefore, the feedback stability time may be limitation factor to rapid operation of the burst mode optical receiver. Further, the design of the feedback structure by nature requires a high degree of complexity.  
           [0009]    In order to improve such a burst mode optical receiver having the feedback structure, a feed-forward structure was proposed. The burst mode optical receiver with a feed-forward structure is further described in “an instantaneous response CMOS optical receiver IC with wide dynamic range and extremely high sensitivity using feed-forward auto-bias adjustment, IEEE J. Solid state circuit, VOL. 30, NO. 9, pp. 991˜997, September 1995”.  
           [0010]    [0010]FIG. 2 is a circuit diagram of a burst mode optical receiver having a feed-forward structure. Referring to FIG. 2, the burst mode optical receiver  70  with the feed-forward structure includes a photodiode  72  for converting an optical signal into an electrical current signal proportional to the optical signal, a gain controllable amplifier (hereinafter, referred to as GCA)  74  for amplifying the current signal outputted from the photodiode  72  to a voltage signal. An output of the GCA  74  is connected to a limiting amplifier  79  located behind of the burst mode optical receiver  70  in order to convert an analog signal into a signal with a digital level.  
           [0011]    In order for the limiting amplifier  79  with a differential input structure to reproduce a signal with a 50% duty cycle, the output of the GCA  74  and a reference voltage of the outputted signal are necessary. An automatic threshold controller (hereinafter, referred to as ATC)  80  finds a reference voltage. This reference voltage is an intermediate voltage value of an outputted signal, of the signal outputted from the GCA  74  and enables the reference voltage to be a reference voltage source of the limiting amplifier  79 . The ATC  80  finds a peak value and a bottom value of the signal from the signal outputted from the GCA  74 . Then, it outputs an intermediate value which is an average value of the peak value and the bottom value. Accordingly, a peak detector  76  and a bottom detector  78  are necessary for the ATC  80 . Further, the ATC  80  includes a pair of resistors R 1  and R 2  for distributing a voltage of a signal passed through the peak detector  76  and the bottom detector  78 . The resistors R 1  and R 2  have a resistance value for generating an intermediate voltage {Vref=(Vpeak+Vbottom)/2}, that is, a reference voltage (Vref), of the peak voltage and the bottom voltage.  
           [0012]    [0012]FIG. 3 is a circuit diagram of a peak detector used in a conventional burst mode optical receiver. FIG. 4 is a circuit diagram of a bottom detector. Referring to FIG. 3, the peak detector  90  includes an amplifying terminal  92  for reducing an offset of a peak value, a NPN transistor  94  for functioning as a diode and a peak hold capacitor  96  for charging a peak value. When a burst signal applied through the amplifying terminal  92  rises up to a peak value, the NPN transistor  94  is turned on and the peak hold capacitor  96  is charged up to a peak value.  
           [0013]    Further, referring to FIG. 4, a bottom detector  100  has a similar construction to the peak detector. It includes an amplifying terminal  102  for reducing an offset of a peak value, a PNP transistor  104  for functioning as a diode and a peak hold capacitor  106  for charging a bottom value. The bottom detector  100  has a different type of transistor for functioning as a diode in comparison with the peak detector  90  and a direction of diode changes according to the transistor type.  
           [0014]    In the operation of the bottom detector  100 , when a burst signal applied through the amplifying terminal  102  falls up to a bottom value, the PNP transistor  104  is turned off and the peak hold capacitor  106  is charged up to a bottom value.  
           [0015]    Charge time required for rising or falling up to the peak value and the bottom value becomes an important factor in detecting the burst signal, when the peak value and the bottom value of the burst signal are detected in the peak detector  90  and the bottom detector  100  in the burst mode optical receiver.  
           [0016]    Conventional peak detectors and bottom detectors have a relatively fast charge time with respect to a small input signal and a relatively slow charge time with respect to a signal with a large input size. Further, the charge time may be fast with respect to a small input signal. However, an overcharge may occur, and thus causing fluctuations. Accordingly, since charge time of an input signal is closely connected with performance of the peak detector and the bottom detector, adjustment of the charge time becomes a very important factor.  
         SUMMARY OF THE INVENTION  
         [0017]    Accordingly, the present invention has been made to reduce or overcome the above-mentioned limitations occurring in the prior art. One object of the present invention is to provide peak and bottom detector circuits in which the peak level and a bottom level current amount is automatically adjusted according to the signal amplitude. In particular, the peak level and a bottom level current is supplied to a peak hold capacitor for maintaining a peak level and a bottom level in a peak detector circuit. Thus, the peak and bottom detector circuits can be charged in very short time.  
           [0018]    In accordance with one embodiment of the present invention, a peak detector in a burst mode optical receiver is provided comprising: an amplifying terminal configured to reduce an offset of a peak value in a received burst signal using feedback in the peak detector; a transistor that functions as a diode when a positive signal is received from the amplifying terminal; a peak hold capacitor for charging a peak value when the transistor received the positive signal; a signal amplitude detector to monitor the received burst signal amplitude; and a current source to drive a current responsive to the output signal amplitude detector.  
           [0019]    In accordance with another embodiment of the present invention, a bottom detector in a burst mode optical receiver is provided comprising: an amplifying terminal configured to reduce an offset of a bottom value in a received burst signal using feedback in the bottom detector; a diode that is turned on when a negative signal is received from the amplifying terminal; a peak hold capacitor connected to the diode and a voltage source, wherein the peak hold capacitor charges a bottom value when the diode is turned on; a signal amplitude detector to monitor the received burst signal amplitude; and a current source connected in parallel to the peak hold capacitor to drive a current responsive to an output of the signal amplitude detector. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0021]    [0021]FIG. 1 is a circuit diagram of a burst mode optical receiver using a double feedback structure;  
         [0022]    [0022]FIG. 2 is a circuit diagram of a burst mode optical receiver having a feed-forward structure;  
         [0023]    [0023]FIG. 3 is a circuit diagram of a peak detector used in a conventional burst mode optical receiver;  
         [0024]    [0024]FIG. 4 is a circuit diagram of a bottom detector used in a conventional burst mode optical receiver;  
         [0025]    [0025]FIG. 5 is a circuit diagram of a peak detector in a burst mode optical receiver according to the present invention;  
         [0026]    [0026]FIG. 6 is a circuit diagram of a bottom detector in a burst mode optical receiver according to the present invention;  
         [0027]    [0027]FIG. 7 is a circuit diagram of a signal amplitude detector according to an embodiment of the present invention;  
         [0028]    [0028]FIGS. 8 and 9 are graphs of a signal input to the signal amplitude detector through a GCA in a burst mode optical receiver;  
         [0029]    [0029]FIGS. 10 and 11 are graphs of a signal detected from an input signal by the signal amplitude detector in the burst mode optical receiver;  
         [0030]    [0030]FIG. 12 is a graph showing the output of the peak detector and the bottom detector according to the present invention; and  
         [0031]    [0031]FIGS. 13 and 14 are graphs of the output of the peak detector and the bottom detector to a large input signal and a small input signal, respectively.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0032]    Hereinafter, a preferred embodiment according to the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.  
         [0033]    [0033]FIG. 5 is a circuit diagram of a peak detector in a burst mode optical receiver according to the present invention. Referring to FIG. 5, the peak detector  200  in the burst mode optical receiver includes an amplifying terminal  210  for reducing an offset of a peak value, a transistor  220 , which functions as a diode, a peak hold capacitor (hereinafter, referred to as Cp)  230  for charging a peak value, a signal amplitude detector  240  for monitoring signal amplitude and generating a control voltage corresponding to the signal amplitude and a current source  250  for driving an actual current according to the output of the signal amplitude detector  240 .  
         [0034]    A burst signal is applied to the positive input terminal of the amplifying terminal  210 . A feedback peak output is inputted to the negative input terminal of the amplifying terminal  210 . The amplifying terminal  210 &#39;s output terminal is connected to a base terminal of the transistor  220 . The positive input terminal of the amplifying terminal  210  is connected to an input terminal of the signal amplitude detector  240 . The burst signal is applied to the input terminal of the signal amplitude detector  240 . An output terminal of the signal amplitude detector  240  is connected to a gate terminal of the current source  250 , which is a MOS FET. The source terminal of the MOS FET  250  is connected to a voltage source Vcc. The drain terminal of the MOS FET  250  is connected to a collector terminal of the transistor  220 .  
         [0035]    Operationally, in the peak detector  200 , when a peak value is detected the amplifying terminal  210  reduces a voltage offset caused by a forward voltage of a diode. More particularly, the amplifying terminal  210  reduces the voltage offset as much as the gain of the amplifying terminal if an ultimate detected peak value is fedback. When an increasing positive signal is input through the amplifying terminal  210 , the transistor  220  is saturated and the Cp  230  is charged. The signal amplitude detector  240  detects the size of the signal applied to the peak detector  200 . It also controls the current amount of the current source  250  according to the detected signal amplitude. When the signal amplitude is small, the signal amplitude detector  240  reduces the current amount of the current source  250  to a very small value, thereby preventing the Cp  230  from being overcharged. In contrast, when the signal amplitude is large, the signal amplitude detector  240  increases the current amount of the current source  250  to a very large value, thereby reducing charge time of the Cp  230 . Accordingly, even if the intensity of a burst signal is large, the charge time becomes much shorter.  
         [0036]    In addition, the peak detector  200 , when a decreasing negative signal is applied, the transistor  220  is cutoff and the Cp  230  discharges the current, which as been charged. In this manner, the peak detector  200  maintains the peak value.  
         [0037]    As described above, the present invention controls the current amount of the current source  250  according to the size of the signal detected by the signal amplitude detector  240 . This enables a reduction of the charge time of the Cp  230 , even if the intensity of the burst signal is large, thereby shortening charge time. Accordingly, (1) when an input signal is small, the signal amplitude detector  240  makes the current amount of the current source  250  small and thus the Cp  230  is slowly charged; (2) when an input signal is large, the signal amplitude detector  240  makes the current amount of the current source  250  large and thus the Cp  230  is fast charged. This is based on the principle that, when a time constant of the Cp  230  is constant, charge time becomes shorter as the intensity of the input signal with respect to a constant time constant grows larger.  
         [0038]    [0038]FIG. 6 is a circuit diagram of a bottom detector in a burst mode optical receiver according to the present invention.  
         [0039]    Referring to FIG. 6, the peak detector  300  in the burst mode optical receiver includes an amplifying terminal  310  for reducing an offset of a bottom value, a diode  320 , a peak hold capacitor (hereinafter, referred to as Cp)  330  for charging a bottom value, a signal amplitude detector  340  for monitoring a signal amplitude and generating a control voltage corresponding to the signal amplitude and a current source  350  for driving an actual current according to an output of the signal amplitude detector  340 .  
         [0040]    A burst signal is applied to the positive input terminal of the amplifying terminal  310 . A bottom output is fedback to the negative input terminal of the amplifying terminal  310 . The amplifying terminal  310 &#39;s output terminal is connected to a negative terminal of the diode  320 . The positive input terminal of the amplifying terminal  310  is connected to an input terminal of the signal amplitude detector  340 . The burst signal is applied to the input terminal of the signal amplitude detector  340 . An output terminal of the signal amplitude detector  340  is connected to a gate terminal of the current source  350  which is a MOS FET. The source terminal of the MOS FET  350  is connected to a voltage source Vcc. The drain terminal of the MOS FET  350  is connected to a positive terminal of the diode  320 . The Cp  330  is connected in parallel to the source and drain terminal of the MOS FET  350 .  
         [0041]    In comparison with the bottom detector  300 , the bottom detector  300  has the polarity of the diode  320  is in a reverse state and the Cp  330  is connected to Vcc and not ground. In the peak detector  300 , when a signal decreases in a negative direction, the diode  320  becomes forward biased. Then a charge occurs through the Cp  330 . When the signal increases in a positively, the diode  320  becomes reverse biased. Then the Cp  330  discharges the current that has been charged. When the size of the signal detected by the signal amplitude detector  340  is small, the discharge path becomes open. In this manner, overcharge of the Cp  330  is prevented. When the size of the signal detected by the signal amplitude detector  340  is large, the discharge path becomes closed. Thus, the charge time is faster.  
         [0042]    [0042]FIG. 7 is a circuit diagram of a signal amplitude detector according to an embodiment of the present invention.  
         [0043]    As shown in FIG. 7, the signal amplitude detector according to the present invention includes a Heterojunction Bipolar Transistor (HBT) Q 1  in which an input is applied from a GCA to a base terminal. Further, the collector terminal of the Heterojunction Bipolar Transistor (HBT) Q 1  is connected to Vcc and one side of a resistor R 1 . The emitter terminal of the Heterojunction Bipolar Transistor (HBT) Q 1  is connected to a capacitor C 1 . The drain terminal and the source terminal of a MOS FET M 1  are connected in parallel to both sides of the capacitor C 1 . A resistor R 3  is connected in parallel to both sides of the capacitor C 1 . One side of the capacitor C 1  is grounded. A reset signal generated in the burst mode optical receiver is applied to a gate terminal of the MOS FET M 1 .  
         [0044]    The gate terminal of MOS FET M 2  is connected to the emitter terminal of the Heterojunction Bipolar Transistor (HBT) Q 1  and the capacitor C 1 . The drain terminal of the MOS FET M 2  is connected to the other side of the resistor R 1 . The drain terminal of the MOS FET M 2  and the other side of the resistor R 1  becomes an output terminal of the signal amplitude detector. Also, the drain and the source terminal of the MOS FET M 3  are connected in parallel to the drain and the source terminal of the MOS FET M 2 . The MOS FET M 2  and the MOS FET M 3  form a differential amplifier, as known to those skilled in the art. Further, one side of resistor R 2  is connected to the source terminal of the MOS FET M 3  and the source terminal of the MOS FET M 2 . The other side of a resistor R 2  is grounded. A reference voltage, for instance, 3V, is applied to the gate terminal of the MOS FET M 3  through resistor R 4 . The drain terminal of MOS FET M 4  is connected to the gate terminal of the MOS FET M 3  through a resistor R 5 . The drain terminal of a MOS FET M 4  is connected to a gate terminal of a MOS FET M 4 . The source terminal is grounded.  
         [0045]    The operation of the signal amplitude detector will be further described below. The input signal from the GCA is applied to the base terminal of the Heterojunction Bipolar Transistor (HBT) Q 1 . The reference voltage, e.g. of 3V, is applied to the gate terminal of the MOS FET M 3  in order to set a reference signal in a bottom level of an input signal. When a small input signal from the GCA is applied to the Heterojunction Bipolar Transistor (HBT) Q 1 , the signal is charged in the capacitor C 1  connected to the Heterojunction Bipolar Transistor (HBT) Q 1  and the charge voltage is smaller than 3V. Therefore, according to the principles of a differential amplifier, since the MOS FET M 3  is saturated and the MOS FET M 2  is not saturated, the voltage, which is close to a supply voltage, is output from the collector terminal of the MOS FET M 2 . The resulting output signal is shown in FIG. 10.  
         [0046]    In contrast, when a large input signal from the GCA is applied to the Heterojunction Bipolar Transistor (HBT) Q 1 , the signal is charged in the capacitor C 1  connected to the Heterojunction Bipolar Transistor (HBT) Q 1  and the charge voltage is actually more than 3V. Therefore, the MOS FET M 2  is saturated and then the current flows in the collector terminal of the MOS FET M 2 . Thus, it outputs the voltage, which has been dropped down, to the resistor R 1 . The resulting output signal is shown in FIG. 11.  
         [0047]    [0047]FIGS. 8 and 9 are graphs of a signal input to the signal amplitude detector through a GCA in a burst mode optical receiver. As shown in FIGS. 8 and 9, a signal with a peak value of 40 mV and a signal with a peak value of 1V may be input to the signal amplitude detector.  
         [0048]    [0048]FIGS. 10 and 11 are graphs showing a signal detected from an input signal by the signal amplitude detector in the burst mode optical receiver. As shown in FIGS. 10 and 11, when the input signal is small, the signal amplitude detector  240  makes the current amount of the current source  250  small. Further, when the input signal is large, the signal amplitude detector  240  makes the current amount of the current source  250  large.  
         [0049]    [0049]FIG. 12 is a graph showing the output of the peak detector and the bottom detector according to the present invention. FIGS. 13 and 14 are graphs showing the output of the peak detector and the bottom detector with respect to a large input signal and a small input signal, respectively. Referring to FIG. 12 to FIG. 14, the peak detector and the bottom detector can respectively detect a peak value and a bottom value of a burst signal. In this case, the peak detector and the bottom detector according to the present invention are employed in the burst mode optical receiver, thereby detecting a peak value and a bottom value rapidly.  
         [0050]    In the present invention, current amount supplied to a Cp for maintaining a peak level and a bottom level in a peak detector circuit can be automatically adjusted according to a signal amplitude. Thus, the burst mode optical receiver has a very rapid response time.  
         [0051]    While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.