Abstract:
An electronic circuit includes a first variable gain amplifier for amplifying a signal at an input to provide a first amplified signal; a filter receiving the first amplified signal to provide a filtered signal; a second variable gain amplifier for receiving and amplifying the filtered signal; a second gain control bock, to provide at least one gain control signal derived from the filtered signal, one of the at least one gain control signal to control the gain of the second variable gain amplifier; and a bounding block for receiving one of the at least one gain control signal from the second gain control block, and for generating therefrom a bounded gain control signal to control gain of the first variable gain amplifier.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to electronic circuits, and more particularly to electronic circuits including filters with pre and post filter automatic gain control (AGC). 
       BACKGROUND OF THE INVENTION 
       [0002]    AGC circuits are used in a variety of electronic devices and systems. AGC circuits are used to adjust the output of an amplifier to maintain its gain to an appropriate level for input signals within a range. 
         [0003]    Narrowband filter circuits use pre and post filter AGC. In this way, the filter input and filter output may be maintained within desired ranges. Pre and post filter AGC gain is typically controlled by the output of the narrowband filter, or independently by signals at the input and output. 
         [0004]    Unfortunately, conventional AGC pre and post filter arrangements may not distribute AGC gains pre and post filter optimally. 
         [0005]    Accordingly, there is a need for an improved filter AGC arrangement that may more effectively take into account pre filter signal characteristics. 
       SUMMARY OF THE INVENTION 
       [0006]    In accordance with an aspect of the present invention, an electronic circuit includes a first variable gain amplifier, for amplifying a signal at an input to provide a first amplified signal; a filter receiving the first amplified signal, to provide a filtered signal; a second variable gain amplifier, for receiving and amplifying the filtered signal; a second gain control bock, to provide at least one gain control signal derived from the filtered signal, one of the at least one gain control signal to control the gain of the second variable gain amplifier; and a bounding block for receiving one of the at least one gain control signal from the second gain control block, and for generating therefrom a bounded gain control signal to control gain of the first variable gain amplifier. 
         [0007]    In accordance with another aspect of the present invention, a method of processing an input signal comprises: amplifying the input signal by a first variable gain amplifier to provide a first amplified signal; filtering the first amplified signal by a filter to provide a filtered signal; amplifying the filtered signal by a second variable gain amplifier to provide an output signal; forming a gain control signal for the second variable gain amplifier, based on an output of the second variable gain amplifier, to provide a gain limited output signal from the second variable gain amplifier; forming a bounding control signal from a signal containing information in the input signal, removed by the filter; forming a first amplifier gain control signal to control gain of the first variable gain amplifier, the first amplifier gain control signal formed from an output of the second variable gain amplifier, but bounded by the bounding control signal to avoid clipping of the first amplifier. 
         [0008]    In accordance with yet another aspect of the present invention, an electronic circuit comprises: a plurality of cascaded filters, the first of the plurality of cascaded filters receiving the first amplified signal, and each subsequent one of the plurality of cascaded filters receiving an output of immediately previous one of the plurality of cascaded filters; a variable gain amplifier interposed between an output of each of the cascaded filters and an input of a subsequent one of the plurality of cascaded filters; a first gain control block to provide a gain control signal derived from the first amplified signal; a second gain control bock, to provide at least one gain control signal derived from the filtered signal, one of which controls the gain of the second variable gain amplifier; at least one intermediate gain control block to provide a gain control signal derived from an output of one of the plurality of cascaded filters; a selector for receiving the gain control signal from the first gain control block, the at least one intermediate gain control block, and the at least one gain control signal from the second gain control block, and for providing a selected one of the gain control signal from the first gain control block, at least one intermediate gain control block, and the at least one gain control signal from the second gain control block, to control gain of the first variable gain amplifier. 
         [0009]    In accordance with a further aspect of the present invention, there is provided an electronic circuit comprising: a plurality of cascaded filters, the first of the plurality of cascaded filters receiving the first amplified signal, and each subsequent one of the plurality of cascaded filters receiving an output of immediately previous one of the plurality of cascaded filters; a variable gain amplifier interposed between an output of each of the cascaded filters and an input of a subsequent one of the plurality of cascaded filters; a gain control bock and a bounding block, each associated with each one of the variable gain amplifiers, the gain control block to provide a gain control signal derived an output of a downstream one of the plurality of cascaded filters to control the gain of the associated variable gain amplifier, and each bounding block for receiving the gain control signal from its associated gain control block and for generating therefrom a bounded gain control signal to control gain of its associated variable gain amplifier. 
         [0010]    Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    In the figures which illustrate by way of example only, embodiments of the present invention, 
           [0012]      FIG. 1A  is a simplified schematic block diagram of an electronic circuit including a filter with pre and post filter AGC; 
           [0013]      FIG. 1B  is a graph that illustrates filtering of signals by the filter of  FIG. 1A ; 
           [0014]      FIG. 2A  is a simplified schematic block diagram of an electronic circuit including a filter with pre and post filter AGC; 
           [0015]      FIG. 2B  is a graph that illustrates filtering of signals by the filter of  FIG. 2A ; 
           [0016]      FIG. 3A  is a simplified schematic block diagram of an electronic circuit including a filter with pre and post filter AGC, exemplary of an embodiment of the present invention; 
           [0017]      FIG. 3B  is a graph that illustrates filtering of signals by the filter of  FIG. 3A ; and 
           [0018]      FIG. 4  is a simplified schematic diagram of an AGC block of the electronic circuit of  FIG. 3A ; 
           [0019]      FIG. 5  is a simplified schematic block diagram of an electronic circuit including a filter with pre and post filter AGC, exemplary of another embodiment of the present invention; and 
           [0020]      FIG. 6  is a simplified schematic block diagram of an electronic circuit including a filter with pre and post filter AGC, exemplary of another embodiment of the present invention; and 
           [0021]      FIG. 7  is a simplified schematic block diagram of an electronic circuit including multiple cascaded filters with pre and post filter AGC, exemplary of another embodiment of the present invention 
       
    
    
     DETAILED DESCRIPTION 
       [0022]      FIG. 1A  schematically illustrates an electronic circuit  10 , including a conventional filter  16  with pre and post filter AGC. As illustrated, a signal S in  at input  12  to a filter  16  is amplified by a variable gain amplifier  14 , whose gain is controlled by AGC block  18 . The output of filter  16  is similarly amplified by variable gain amplifier  20  under control of AGC block  22 , to provide an output S out . 
         [0023]    AGC block  18  is provided with the output of variable gain amplifier  14  and accordingly provides a control signal to adjust the gain of variable gain amplifier  14 , based on this output to provide a bounded input to filter  16 . Likewise AGC block  22  is provided with the output of variable gain amplifier  20  and accordingly adjusts the gain of amplifier  20  to provide a bounded output signal, S out  at output  24 . The overall amplitude of S out  is thus the result of gain of amplifier  14 , amplifier  20  and filter  16 . 
         [0024]    In the depicted embodiment, filter  16  is a narrowband band-pass filter. Amplifier  20  may similar be a narrow-band amplifier. Amplifier  14 , however, typically amplifies the narrowband, as well as adjacent channels. As will become apparent, filter  16  could alternatively be a low-pass, high-pass or other filter. 
         [0025]    AGC blocks  18 ,  22  may be formed as a combination of conventional passive and/or active components, arranged to produce control signals to maintain output of a controlled variable gain amplifier within a bounded range. AGC blocks  18 , 22  may, for example, be formed to exercise proportional-integral-derivative (PID) control over amplifiers  14  and  20 . Notably, AGC blocks  18  and  22  each provide an independent gain control output, controlling the gains of amplifiers  14  and  20 , respectively. This approach maximizes the dynamic range of amplifier  14 . However, amplifier  14  may be contributing too great a portion of the gain resulting in S out . Moreover, the gain of amplifier  14  will react to perturbations in the energy of adjacent channels in S in . This may be undesirable or unnecessary. 
         [0026]      FIG. 1B  illustrates filtering of a weak desired channel, flanked by strong adjacent channels, filtered by circuit  10 . Specifically, the input signal at input  12 , the output of amplifier  14 , the output of filter  16 , and the output of amplifier  20  are illustrated. As the gain of amplifier  14  is limited by AGC block  18  which receives an unfiltered amplified version of the signal S in , perturbations in the energy in the adjacent channels in S in  will affect the gain of amplifier  14 . 
         [0027]      FIG. 2A  similarly illustrates a further conventional filter  56  with pre and post filter AGC. As illustrated, a signal S in  at input  52  is amplified by variable gain amplifier  54 , and provided to a filter  56 . The output of filter  56  is similarly amplified by variable gain amplifier  60  to provide an output signal S out  at output  74 . 
         [0028]    A single AGC block  58  provides one or more gain control signals to control both variable gain amplifiers  54  and  60  Automatic gain control block  58  is provided with the output of variable gain amplifier  60  and accordingly adjusts the gains of both variable gain amplifiers  54  and  60  to provide a bounded output signal S out . Again, the overall amplitude S out  is thus the result of combined gains of amplifier  54  and amplifier  60 . 
         [0029]    Filter  56  (like filter  16 ) may be a narrow band-pass filter. Amplifier  60  amplifies the narrow band. Amplifier  54  amplifies the band, as well as adjacent channels. 
         [0030]    Notably, only a single AGC block  58  is used to provide a single gain control signal to control the gain of both amplifiers. Conveniently, this approach reduces or minimizes the gain of amplifier  54 .  FIG. 2B  illustrates filtering of a weak desired channel, flanked by strong adjacent channels, filtered by circuit  50 . Input signal at input  52 , the output of amplifier  54 , the output of filter  56 , and the output of amplifier  60  are illustrated. As should be apparent, AGC block  58  does not receive components of signal S in , filtered by filter  56 . As such, the gain of amplifier  54  is not affected by perturbations in the energy of adjacent channels in S in , as the adjacent channels are filtered. However, strong adjacent channels may cause clipping or distortion of amplifier  54  or filter  56 . 
         [0031]    To mitigate some of the disadvantages of circuits  10  and  50 ,  FIG. 3A  illustrates an electronic circuit  100  including a filter  116  with pre and post filter AGC, exemplary of an embodiment of the present invention. 
         [0032]    Circuit  100  may be a digital circuit, or a mixed analog/digital circuit, and may thus be formed using standard digital signal processing (DSP) techniques and/or analog circuit design techniques. Circuit  100  may be part of a larger circuit, such as a video or audio amplifier, a television or radio receiver or transmitter, or the like. 
         [0033]    As illustrated, a signal S in  at input  112  to a filter  116  is amplified by variable gain amplifier  114 , whose gain is controlled by a AGC block  122 . The output of filter  116  is similarly amplified by variable gain amplifier  120  under control of AGC block  122 , to provide an output S out  at output  124 . 
         [0034]    In the depicted embodiment, variable gain amplifier  114  is formed as analog circuits, while filter  116  and variable gain amplifier  120  is formed as a digital amplifier. The output of variable gain amplifier  114  is converted to a digital signal by analog to digital converter (ADC)  115 . The digital output of ADC  115  is passed to filter  116 . 
         [0035]    Filter  116  (like filters  16  and  56 ) is again a narrowband filter. Variable gain amplifier  114  amplifies the narrow band, as well as any adjacent channels. Variable gain amplifier  120  amplifies the narrowband. In alternate embodiments, filter  116  can take any suitable form: a low-pass filter, a high-pass filter, a band-pass filter, a notch filter, or the like. Typically, filter  116  filters energy in an input signal to generate its output. Filter  116  may be digital or analog. In the depicted embodiment, filter  116  is a digital filter, that may be formed as a FIR/IIR filter. Amplifier  120  may amplify the resulting band. 
         [0036]    AGC block  122  is provided with the output of variable gain amplifier  120  and forms at least one gain control signal. In the depicted embodiment, AGC block  122  is a digital AGC block, and provides two digital AGC control signals at its outputs, used to control the gain of amplifiers  120  and  114  as described below. 
         [0037]    Specifically, one of the gain control signals formed by AGC block  122  is used to control the gain of variable gain amplifier  120 . This signal accordingly controls the gain of variable gain amplifier  120  to provide a bounded output signal, S out . 
         [0038]    At least one of the gain control signals formed, G 2 , at AGC block  122  is provided to the input of selector  130  to control the gain of amplifier  114 , as further described below. AGC block  122  may provide the same signal to variable gain amplifier  120  and selector  130 . Alternatively, two different signals—one to control amplifier  114  and the other to control amplifier  120 , may be formed by second AGC block  122 . 
         [0039]    First AGC block  118  further forms an AGC control output G 1  from the output of variable gain amplifier  114 . Again, AGC block  118  may operate in the digital domain, producing a digital output signal from a digital input signal provided by ADC  115 . The AGC control signal from AGC control block  118  is provided to a second input of selector  130 . 
         [0040]    AGC blocks  118 ,  122  may be formed as a combination of conventional passive and/or active components, arranged to produce control signals to maintain output of a controlled variable gain amplifier within a bounded range. AGC blocks  118 ,  122  may, for example, be formed to exercise proportional-integral-derivative (PID) control over variable gain amplifiers  114  and  120 . As will be appreciated, AGC blocks  118 ,  122  may each have different characteristics. For example, and as will become apparent AGC block  122  may provide two distinct control outputs based on its input. AGC block  122  may react more quickly than block  118   
         [0041]    Depending upon the applications of the system, AGC block  118  and AGC block  122  may be formed in any number of ways, known to those of ordinary skill. As noted AGC blocks  118 ,  122  are digital AGC blocks. As will be appreciated, with minor modification either or both of AGC blocks  118  could be formed as analog blocks. 
         [0042]    In general, an AGC block, like AGC blocks  118 ,  122  may include a level detector  150 , a summer  152 , a filter  154 , a gain block  156 , and an accumulator  158  as depicted in  FIG. 4 . Level detector  150  may, for example, detect the peak signal level, average signal level, rms signal level or the like. Summer  152  subtracts the current signal level, as sampled at an input, from a target level. The target level may be provided externally from a digital input, contained for example in a register, dip switch or the like. Alternatively, the target level may be a static parameter of AGC block  118 / 122 . 
         [0043]    Level detector  150 , summer  152 , filter  154 , gain block  156  and accumulator  158  provide a proportional-integral-derivative (PID) control loop, so that the output of AGC blocks  118 , 120  provides a gain signal that causes the sampled input to approach the target level, or a multiple thereof. As AGC block  122  provides two distinct outputs, AGC block  122  may further include two detectors, summers, filters, gain blocks and accumulators as described. Alternatively, such components may be shared where appropriate across two signal paths to provide two separate gain control outputs. 
         [0044]    Now, selector  130  selects which of the provided gain control signals is used to control the gain of amplifier  114 —the gain control signal G 2  formed by AGC block  122 , or the gain control signal G 1  formed by AGC block  118 . In the depicted embodiment, selector  130  may select the minimum of the output of AGC block  118  and AGC block  122  to control the gain of amplifier  114 . 
         [0045]    As amplifier  114  is an analog amplifier, the output of selector  130  may further be converted from a digital signal to an analog signal by digital to analog converter  131 . 
         [0046]    By selecting the minimum of two gain control signals G 1  and G 2 , the gain of amplifier  114  is kept relatively low while providing a bounded output signal S out . Conveniently, this may avoid clipping of the input signal by variable gain amplifier  114 . Put another way—one gain control signal (G 2 ) primarily regulates the gain of variable gain amplifier  114 . Gain control signals G 1  derived from the output of variable gain amplifier  114 , acts as a bounding signal for G 2  and limits the gain of variable gain amplifier  114  based on information unseen by AGC block  122  (i.e. based on a signal containing information filtered by filters  116 ). Selector  130  effectively acts as a bounding block: selector  130  bounds G 2 , and provides a bounded gain control signal that is the lesser of G 1  and G 2  to amplifier  114 . 
         [0047]    That is, the gain control signal that controls the gain of amplifier  114  is bounded by a gain control signal G 1  derived from a signal pre-filter  116 , so as to (i) reduce the contribution of the gain of variable gain amplifier  114  to the output signal S out , while providing a bounded output by amplifier  120 , and (ii) avoid clipping of amplifier  114 . 
         [0048]    In yet another alternative embodiment, selector  130  may alternatively provide the minimum output of its input, or some further internal (or externally provided) minimum value to bound the provided gain control signal. In this way, the control signal provided amplifier  114  may be limited to some minimum value, regardless of the gain control values G 1 /G 2  that might otherwise be calculated by AGC blocks  118 , 122 . 
         [0049]    In one embodiment, circuit  100  can be formed as part of an RF television tuner. As such amplifier  114  may be a low noise amplifier in the RF tuner. AGC block  118  may be a low distortion, low noise gain control block designed for a television RF tuner. Filter  116  may be a SAW filter function (formed as a SAW board component or a digital FIR/IIR filter), and amplifier  120  may a post filter amplifier, to set the output level to a specified target. AGC block  122  may be a digital gain control block which regulates the level of desired channel energy (CVBS, Audio SIF/Mono/Stereo, Digital Modulated Signals). AGC block  122  can be implemented with a linear or a shaped non-linear gain transfer function. 
         [0050]      FIG. 3B  illustrates filtering of a weak desired channel, flanked by strong adjacent channels, filtered by circuit  100  of  FIG. 3A . Specifically, the input signal at  112 , the output of variable gain amplifier  114 , the output of filter  116 , and the output of amplifier  120  are illustrated. As the gain of amplifier  114  is limited by AGC block  118  by the lesser of the AGC control signal formed pre and post filter  116 , perturbations in the energy in the adjacent channels in S in  will affect the gain of amplifier  114 , to avoid clipping by variable gain amplifier  114 . In the absence of perturbations in the input signal, the gain of variable gain amplifier  114  is set by AGC block  122  at the minimum level to satisfy a desired output level of signal S out . 
         [0051]    In an alternate embodiment, depicted in  FIG. 5 , circuit  100 ′ is a slightly modified version of circuit  100 . For simplicity ADCs and DACs are not specifically illustrated. In this embodiment, two separate post filter values are formed—using sub blocks  122 A and  122 B of block  122 ′, in place of block  122  in  FIG. 3A . Sub-block  122 B calculates a post filter gain control signal from a signal at the output of amplifier  120  to control the gain of variable gain of amplifier  120 . Sub-block  122 A further provides a pre-filter gain control signal from the input to variable gain amplifier  120  to be provided to selector  130 . 
         [0052]    As will be appreciated, the pre-filter gain control signal calculated by AGC sub-block  122   a  could be formed from the post filter gain control signal generated by sub-block  122   b , simply by processing the signal post amplifier  120  to reduce or remove the effects of amplifier  120 . This would obviate the need for additionally sampling the input to amplifier  120 . 
         [0053]    As may now be appreciated, one or more signals containing information filtered by filter may be used to limit pre-filter gain. For example,  FIG. 6  illustrates a pre and post filter AGC circuit  100 ″ that employs signal taken pre-filter  116 ″, from within filter  116 ″ and post filter  116 ″ to limit the gain of a pre-filter variable gain amplifier  114 ″. 
         [0054]    As illustrated, an input signal S in  is provided to a variable gain amplifier  114 ″. The output of variable gain amplifier  114 ″ is provided to filter  116 ″, which may be modelled as two or more series filters  126 A and  126 B. The output of one of the filters  126 A is provided to filter  126 B. The output of filter  126 B is provided to a variable gain amplifier  120 ″. First and second AGC blocks  118 ″ and  122 ″ respectively form gain control signal from signal sampled pre and post filters  116 ″ ( 126 A/ 126 B). 
         [0055]    AGC block  118 ″ has a structure similar to AGC block  118  ( FIG. 3 ), and each provide a single gain control value at their output. AGC block  122 ″ may have a structure similar to AGC block  122 / 122 ′ ( FIGS. 3 ,  5 ), and provides two distinct gain control outputs from the output of variable gain amplifier  120 ″: one to control variable gain amplifier  120 ″, and the other to be provided to a bounding block, in the form of selector  130 ″. 
         [0056]    A third AGC block  124 ″ has a structure similar to AGC block  118 ″ and provides a further single gain control signal G 3  at its output, based on the output of the first of the series filters, filter  126 A. As will be appreciated, the signal at the output of filter  126 A contains information that will be filtered by filter  126 B, before forming an output signal. 
         [0057]    Now, one of the gain control signals formed by AGC block  122 ″ is used to control the gain of variable gain amplifier  120 ″. This signal accordingly controls the gain of variable gain amplifier  120 ″ to provide a bounded output signal, S out . 
         [0058]    At least one of the gain control signals G 2 , formed at AGC block  122 ″ is provided to an input of selector  130 ″ to control amplifier  114 ″, as further described below. 
         [0059]    AGC block  118 ″ further forms an AGC control output G 1  from the output of variable gain amplifier  114 ″. 
         [0060]    G 1 , G 2 , and G 3  are provided to separate inputs of selector  130 ″. 
         [0061]    Selector  130 ″ selects which of the three provided gain control signals is used to control the gain of amplifier  114 ″—the gain control signal G 1  formed by AGC block  118 ″, the gain control signal G 3  formed by AGC block  124 ″, or the gain control signal G 2  formed by AGC block  122 ″. 
         [0062]    In the depicted embodiment, circuit  100 ″ is again a mixed digital/analog circuit. Amplifier  114 ″ is analog, while filters  116 ″, amplifier  120 ″, and AGC blocks  118 ″, 122 ″ and  124 ″ and selector  130 ″ are digital. Again, DACs and ADCs are not illustrated for simplicity. And again, circuit  100 ″ could similarly be implemented using different combinations of analog and digital blocks, or entirely as digital or analog circuits. 
         [0063]    In the depicted embodiment, selector  130 ″ may select the minimum of the output of AGC block  118 ″, AGC block  122 ″, and AGC block  124 ″ to control the gain of amplifier  114 ″. 
         [0064]    Conveniently, by selecting the minimum of three gain control signals G 1 , G 2 , and G 3 , the gain of amplifier  114 ″ is again kept relatively low while providing a bounded output signal S out  at the output of amplifier  120 ″. Conveniently, this may avoid clipping of the input signal by variable gain amplifier  114 ″. Put another way—the gain control signal that controls the gain of amplifier  114 ″ is derived from the signal as filtered by filter  116 ″ and the output signal S out  as amplified by amplifier  120 ″, so as to (i) reduce the contribution of the gain of variable gain amplifier  114 ″ to the output signal S out , while providing a bounded output by amplifier  120 ″, and (ii) avoid clipping of amplifier  114 ″ and/or filter  116 ″. 
         [0065]    Selector  130 ″ again effectively acts as a bounding block: selector  130 ″ bounds post filter gain control signal G 2  and provides a bounded gain control signal that is the lesser of G 1 , G 2  and G 3  to control the gain of pre-filter variable gain amplifier  114 ″. 
         [0066]    As should now again be appreciated, in circuit  100 ″ of  FIG. 6 , one gain control signal (G 2 ) primarily regulates the gain of amplifier  114 ″. Gain control signals G 1 , G 3  derived from the outputs of amplifier  114 ″ and filter  126 A, respectively, bound the gain of amplifier  114 ″ based on information unseen by AGC block  122 ″ (i.e. from a signal containing information filtered by filters  126 A/ 126 B). 
         [0067]    As may now be appreciated, multiple filters including pre and post filter AGC as described above may also be cascaded. To this end,  FIG. 7  illustrates an electronic AGC circuit  200  including two cascaded filters having pre and post filter AGC substantially as described above. 
         [0068]    As illustrated, an input signal S in  is provided to a variable gain amplifier  214 . The output of variable gain amplifier  214  is provided to filter  216 . The output of filter  216  is provided to a variable gain amplifier  228 . The output of variable gain amplifier  228  is provided to filter  226 . The output of filter  226  is provided to a further variable gain amplifier  220 . AGC blocks  218 , and  222  respectively form gain control signal from signal sampled pre and post filters  216 / 226 . 
         [0069]    A further AGC block  224  forms a gain control signal, post filter  216  (and amplifier  228 ), but pre-filter  226 , from a signal containing information not seen by AGC block  222 . 
         [0070]    AGC block  218  has structure similar to AGC block  118  ( FIG. 3 ), and provides a single gain control value at its output. 
         [0071]    AGC block  222  may have structure similar to AGC block  122 / 122 ′ ( FIGS. 3 ,  5 ), and provides two distinct gain control outputs from the output of variable gain amplifier  220 : one to control variable gain amplifier  220 , and the other to be provided to an upstream selector  232 , acting as a bounding block. 
         [0072]    AGC block  224  also has structure similar to AGC block  122 / 122 ′ and provides two gain control signals: one to control variable gain amplifier  228 , and the other to be provided to an upstream selector  230 , acting as a bounding block. 
         [0073]    Now, one of the gain control signals formed by AGC block  222  is used to control the gain of variable gain amplifier  220 . This signal accordingly controls the gain of variable gain amplifier  220  to provide a bounded output signal, S out . At least one of the gain control signals, G 4 , formed at AGC block  222  is provided to the input of selector  232  to control amplifier  228 , as further described below. 
         [0074]    Similarly, one of the gain control signals, G 3 , formed by AGC block  224  is used to bound the gain of variable gain amplifier  228 , the other G 2 , is used to control the gain of amplifier  214 . This signal G 2  is thus provided to the input of selector  230  to control amplifier  214 . 
         [0075]    AGC block  218  further forms an AGC control output G 1  from the output of variable gain amplifier  214 . 
         [0076]    Selector  230  selects which of the two provided gain control signals is used to control the gain of amplifier  214 —the gain control signal G 1  formed by AGC block  218  or the gain control signal G 2  formed by AGC block  224 . 
         [0077]    Selector  232  likewise selects which of the two provided gain control signals, G 3 , G 4 , is used to control the gain of amplifier  228 —the gain control signal G 3  formed by AGC block  224  or the gain control signal G 4  formed by AGC block  222 . 
         [0078]    Selectors  230 / 232  again effectively act as a bounding blocks: selector  230  bounds G 2  and provides a bounded gain control signal that is the lesser of G 1 , and G 2  to control the gain of amplifier  214 ; selector  232  bounds G 4  and provides a bounded gain control signal that is the lesser of G 3 , and G 4  to control the gain of amplifier  228 . 
         [0079]    In the depicted embodiment, selector  230  may select the minimum of the output of AGC block  218  and AGC block  224  to control the gain of amplifier  214 . Likewise, selector  232  may select the minimum of the output of AGC block  222  and AGC block  224  to control the gain of amplifier  228 . 
         [0080]    Again, in the depicted embodiment, circuit  200  is a mixed digital/analog circuit. Amplifier  214  is analog, while filters  216 ,  226 , amplifier  220 , and AGC blocks  218 ,  222  and  224  and selectors  230  and  232  are digital. DACs and ADCs are not illustrated for simplicity. Again, circuit  200  could similarly be implemented using different combinations of analog and digital blocks, or entirely as digital or analog circuits. 
         [0081]    As should now again be appreciated, in circuit  200 , a downstream, post-filter gain control signal (G 2 /G 4 ) primarily regulates the gain of an upstream, pre-filter variable gain amplifier  214 / 228 . Gain control signals G 1 , G 3  derived from the outputs of amplifier  214 ,  228  respectively, bound the gain of amplifier  214 ,  228  based on information unseen by AGC blocks  224 ,  222  (i.e. from a signal containing information filtered by filters  216 , 226 ). 
         [0082]    Put another way—the gain control signal G 2 , G 4  that controls the gain of a variable gain amplifier  214 / 228  is derived from a downstream filtered signal, as filtered by filter  216 / 226 , while being bounded by an AGC signal G 1 , G 3 . AGC signal G 1 , G 3  is formed from a signal containing information that is filtered by one or more downstream filters. Conveniently this may avoid clipping/distortion of amplifiers  214 ,  228  and filters  216 ,  226 . 
         [0083]    As will be appreciated, circuit  200  could easily be modified to include more than two cascaded filters like filters  216 ,  226  with the input of each cascaded filter being provided by a previous one of the cascaded filters, amplified by an interposed amplifier (e.g. amplifier  228 ). Intermediate gain control signals may be formed from the output of one or more of the cascaded filters to limit gain the gain of up-stream amplifier(s) based on information unseen by downstream AGC blocks (i.e. information filtered by the cascaded filters). 
         [0084]    As will be appreciated, bounding blocks have been realized as selectors  130 , 130 ″, 230  and  232 . Bounding blocks, may however be formed in any number of ways. For example, a bounding block may formed as a control block that receives a signal to be bounded (e.g. G 2 ) and one or more control signals increases or decreases G 2  so that a controlled variable gain amplifier performs as required. The control signals could be derived in an AGC block like block  118 . Other suitable of forming a bounding block will be readily appreciated by those of ordinary skill. 
         [0085]    As will also be appreciated the circuits depicted herein may be formed as single integrated circuits using suitable application specific integrated circuit (ASIC) design and fabrication tools. To that end, circuits depicted herein may be described using a conventional hardware descriptor language (HDL), such as Verilog, VHDL, or the like stored on a computer readable medium. 
         [0086]    Of course, the above described embodiments are intended to be illustrative only and in no way limiting. The described embodiments of carrying out the invention are susceptible to many modifications of form, arrangement of parts, details and order of operation. The invention, rather, is intended to encompass all such modification within its scope, as defined by the claims.