Abstract:
A look-up table outputs an initial value, an inclination of a straight line and a correction value in response to an entry-of a high-order bit string of an operand. An offset circuit calculates an offset of the low-order bit string. A correction circuit outputs the initial value obtained by adding the correction value to at least one of the initial value and the inclination when the correction is necessary. A multiplier calculates a product of the inclination and the offset. An adder calculates the sum of the initial value and the product.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. P2004-13545, filed on Jan. 21, 2004; the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a function approximation arithmetic unit, which calculates function approximations using a look-up table (LUT).  
         [0004]     2. Description of the Related Art  
         [0005]     A calculation method using an arithmetic unit, which calculates function approximations using a conventional LUT, is described below. To begin with, an LUT is provided in advance. An operand is divided into a high-order bit string and a low-order bit string. An operand domain of a function is divided into multiple segments, which are associated with the high-order bit string. The function is approximated by a straight line having a reference value within a segment as an initial value. A LUT that outputs an initial value and the inclination value of a straight line in response to entry of the high-order bit string is prepared.  
         [0006]     When an operand is input to an arithmetic unit, an initial value and the inclination value corresponding to a segment to which the input operand belongs are output from the LUT, and a straight line to approximate that segment to which the input operand belongs is determined. A function approximation is calculated by using that straight line and that operand.  
         [0007]     An error between the function and the straight line tends to increase at the center and both ends of a segment. To reduce the error, the segment should be further subdivided. However, subdivision increases the number of segments, resulting in an increase in the number of bits of the high-order bit string. This increases the LUT size exponentially, resulting in an exponential increase in the circuit size of an arithmetic unit.  
       SUMMARY OF THE INVENTION  
       [0008]     According to an aspect of the present invention, an arithmetic unit for approximating a function is provided. The arithmetic unit includes a look-up table configured to output an initial value, an inclination of a straight line and at least one of relative correction values for the initial value and the inclination in response to an entry of a high-order bit string, an operand being divided into the high-order bit string and a low-order bit string, a domain of the function of the operand being divided into a plurality of segments associated with the high-order bit string, the function being approximated by the straight line indicating a value equal to the initial value at a reference value in one of the segments; an offset circuit configured to calculate an offset of the low-order bit string from the reference value; a determination circuit configured to determine whether a correction of the straight line is necessary by using high-order bits in the low-order bit string; a correction circuit configured to output the initial value obtained by adding an absolute correction value based on the relative correction values to at least one of the initial value and the inclination or by subtracting the absolute correction value from at least one of the initial value and the inclination, when the correction is necessary; a multiplier configured to calculate a product of the inclination and the offset; and an adder configured to calculate the sum of the initial value and the product.  
         [0009]     According to another aspect of the present invention, an arithmetic unit for approximating a function is provided. The arithmetic unit includes a look-up table configured to output an initial value, an inclination of a straight line and a relative correction value for the initial value in response to an entry of a high-order bit string, an operand being divided into the high-order bit string and a low-order bit string, a domain of the function of the operand being divided into a plurality of segments associated with the high-order bit string, the function being approximated by the straight line indicating a value equal to the initial value at a reference value in one of the segments; an offset circuit configured to calculate an offset of the low-order bit string from the reference value; a determination circuit configured to determine whether a correction of the straight line is necessary by using the high-order bits in the low-order bit string; a correction circuit configured to output the initial value obtained by adding an absolute correction value based on the relative correction values to the initial value or by subtracting the absolute correction value from the initial value, when the correction is necessary; a multiplier configured to calculate a product of the inclination and the offset; and an adder configured to calculate the sum of the initial value and the product.  
         [0010]     According to still another aspect of the present invention, an arithmetic unit for approximating a function is provided. The arithmetic unit includes a look-up table configured to output an initial value, an inclination of a straight line and a correction value for the inclination in response to an entry of a high-order bit string, an operand being divided into the high-order bit string and a low-order bit string, a domain of the function of the operand being divided into a plurality of segments associated with the high-order bit string, the function being approximated by the straight line indicating a value equal to the initial value at a reference value in one of the segments; an offset circuit configured to calculate an offset of the low-order bit string from the reference value; a determination circuit configured to determine whether a correction of the straight line is necessary by using high-order bits in the low-order bit string; a correction circuit configured to output the inclination obtained by adding the correction value to the inclination or by subtracting the correction value from the inclination, when the correction is necessary; a multiplier calculating a product of the inclination and the offset; and an adder calculating the sum of the initial value and the product. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a block diagram of an arithmetic unit of a comparative example;  
         [0012]      FIG. 2  is a block diagram of an LUT 0  in the arithmetic unit of the comparative example;  
         [0013]      FIG. 3  is a flowchart for a calculation method for the arithmetic unit of the comparative example;  
         [0014]      FIGS. 4 and 5  are graphs showing the relationship between input operands and corresponding calculation results;  
         [0015]      FIG. 6  is a graph showing the relationship between input operands X and corresponding calculation results Y using the calculation method for the arithmetic unit of the comparative example;  
         [0016]      FIG. 7  is a block diagram of an arithmetic unit according to a first embodiment;  
         [0017]      FIG. 8  is a block diagram of an LUT 0  in the arithmetic unit according to the first embodiment;  
         [0018]      FIG. 9  is a flowchart for a calculation method of the arithmetic unit according to the first embodiment;  
         [0019]      FIG. 10  is a graph showing the relationship between the input operands X 1  and X 2  and corresponding calculation results Y 1  and Y 2  using the calculation method for the arithmetic unit according to a working example of the first embodiment;  
         [0020]      FIG. 11  is a block diagram of an arithmetic unit according to a second embodiment;  
         [0021]      FIG. 12  is a flowchart for a calculation method for the arithmetic unit according to the second embodiment;  
         [0022]      FIG. 13  is a graph showing the relationship between the input operands X 1  and X 2  and corresponding calculation results Y 1  and Y 2  using the calculation method for the arithmetic unit according to a working example of the second embodiment;  
         [0023]      FIG. 14  is a block diagram of an arithmetic unit according to a third embodiment;  
         [0024]      FIG. 15  is a flowchart for a calculation method for the arithmetic unit according to the third embodiment;  
         [0025]      FIG. 16  is a graph showing the relationship between the input operands X 1  and X 2  and corresponding calculation results Y 1  and Y 2  using the calculation method for the arithmetic unit according to a working example of the third embodiment; and  
         [0026]      FIG. 17  is a block diagram of an arithmetic unit according to a fourth embodiment.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]     Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.  
       COMPARATIVE EXAMPLE  
       [0028]     As shown in  FIG. 1 , a function approximation arithmetic unit  8  of a comparative example includes an LUT, an offset circuit  9 , a multiplier  10 , and an adder  11 . The LUT includes an LUT 1  and an LUT 2 . As shown in  FIG. 2 , the LUT includes a decoder  2 , signal lines  3 , and a memory cell array  4 .  
         [0029]     As shown in  FIG. 3 , in step S 1 , an external register  5  of the arithmetic unit  8  receives an n-bit binary operand X. The operand X is divided into a high-order m-bit string U and a low-order (n-m)-bit string D. As shown in  FIG. 4 , a domain of the operand X of the function y=f(x) is divided into multiple segments C, which are associated with the high-order bit string U. The domain can be divided by the high-order m-bit string U into 2 m  segments C 0  to C 2   m-1  A function is approximated by a straight line for each of segments C 0  to C 2   m-1  A case where m=3 is described forthwith for facilitating comprehension. As shown in  FIG. 5 , the LUT 1  stores the values of the straight lines as initial values b 0  to b 7  for the respective high-order bit strings U 0  to U 7  corresponding to the segments C 0  to C 7  when the low-order bit string D of the operand X is the reference value DM. Similarly, the LUT 2  stores the inclinations of straight lines a 0  to a 7  for the respective high-order bit strings U 0  to U 7  corresponding to the segments C 0  to C 7 .  
         [0030]     In step S 2  of  FIG. 3 , the high-order bit string U is input to the LUT 1 , and the initial value b is output therefrom. In step S 3 , the high-order bit string U is input to the LUT 2 , and the inclination a is output therefrom.  
         [0031]     In step S 4 , the offset circuit  9  calculates an offset ΔX or the difference between the reference value DM and the low-order bit string D of the operand X. In other words, the offset ΔX is the difference between the operand X and a reference point.  
         [0032]     In step S 5 , the multiplier  10  calculates product aΔX of the offset ΔX and the inclination a.  
         [0033]     In step S 6 , the adder  11  provides the calculation result Y or the sum of the product aΔX and the initial value b, and outputs the result to the register  6 . In step S 7 , the calculation result Y is set to the register  6 .  
         [0034]     Next, a working example of the comparative example is described. As shown in  FIG. 5 , there is a one-to-one correspondence between the high-order bit strings U 0  to U 7  and the respective segments C 0  to C 7 . The same low-order bit string D as DO is arranged in the same order within the segments C 0  to C 7 . Therefore, it is apparent that the high-order bit string U indicates one of the segments C 0  to C 7  to which the operand X belongs, and that the operand X belongs to the segment C 3 . In addition, when substituting the operand X for the function y=f(x), it is understood that there is an exact solution Y 0 .  
         [0035]     The low-order bit string D indicates a position in the segments C 0  to C 7  to which the operand X belongs. As shown in  FIG. 6 , only the segment C 3  to which the operand X belongs should be considered for calculation result Y.  
         [0036]     A certain point within each of the segments C 0  to C 7 , for example, the midpoint M is selected as the reference value DM.  
         [0037]     In step S 2 , the high-order bit string U 3  of the operand X is input to the LUT 1 , and an initial value b 3  is output therefrom.  
         [0038]     In step S 3 , the high-order bit string U 3  is input to the LUT 2 , and an inclination a 3  is then output therefrom. A straight line represented by the initial value b 3  and the inclination a 3  is the straight line L 3 .  
         [0039]     In step S 4 , the offset ΔX or the difference between the reference value DM and the low-order bit string D of the operand X is calculated.  
         [0040]     In step S 5 , the product a 3 ΔX of the offset ΔX and the inclination a 3  is calculated.  
         [0041]     In step S 6 , the calculation result Y (=a 3 ΔX+b 3 ) or the sum of the product a 3 ΔX and the initial value b 3  is calculated, and the result is then output to the register  6 .  
       First Embodiment  
       [0042]     As shown in  FIG. 7 , an arithmetic unit  8  according to a first embodiment includes an LUT 0 , an offset circuit  9 , a multiplier  10 , an adder  11 , a determination circuit  13 , and a correction circuit  23 . As shown in  FIG. 8 , the LUT 0  includes a decoder  2 , signal lines  3 , and a memory cell array  4 . The high-order bit string U is input to the LUT 0 , and an initial value b, an inclination a, and a correction value α for the inclination a are then output therefrom.  
         [0043]     The LUT 0  includes an LUT 1  to which the high-order bit string U is input and from which the initial value b is output, an LUT 2  to which the high-order bit string U is input and from which the inclination a is output, and an LUT 3  to which the high-order bit string U is input and from which the correction value a for the inclination a is output.  
         [0044]     In step S 2  of  FIG. 9 , the high-order bit strings U 0  to U 7  are input to the LUT 1  and initial values b 10  to b 17  are then output therefrom. In step S 3 , the high-order bit strings U 0  to U 7  are input to the LUT 2  and inclinations a 10  to a 17  are then output therefrom. In step S 1 ., the high-order bit strings U 0  to U 7  are input to the LUT 3  and correction values α 10  to α 17  are then output therefrom. It is assumed that in the segment C, the correction value α for correction of the inclination a is smaller than the inclination a. This assumption allows reduction in the error between a function and a corresponding straight line without causing an exponential increase in the LUT 0  size.  
         [0045]     The determination circuit  13  includes a buffer  14  when each of the segments C 0  to C 7  is divided in half: the left half being a region not to be corrected, and the right half being a region to be corrected. Note that the buffer  14  is only a sample and; alternatively, the determination circuit  13  may include logic circuits corresponding to the divided regions to be corrected and not to be corrected, respectively, in each of the segments C 0  to C 7 . For example, in step S 12 , the most significant bit Xn-m of the low-order bit string D in the operand X is input to the buffer  14 , and a correction signal S is then output therefrom. If the most significant bit Xn-m of the low-order bit string D is 0, 0 is then output as the correction signal S to indicate that correction is unnecessary. Otherwise, if the most significant bit Xn-m is 1, 1 is then output as the correction signal S to indicate that correction is necessary.  
         [0046]     The correction signal S is input to the correction circuit  23 . If correction is necessary according to the correction signal S indicating that correction is necessary, the correction circuit  23  adds or subtracts the correction value α to or from the inclination a to correct the inclination a. The corrected inclination ac is output from the correction circuit  23 . Otherwise, if correction is unnecessary according to the correction signal S indicating that correction is unnecessary, the inclination a is output from the correction circuit  23  without correction. The correction circuit  23  includes an adder-subtracter  15  and a selector  16 . In step S 13 , the adder-subtracter  15  adds or subtracts the correction value α to or from the inclination a, and then outputs the corrected inclination ac. In step S 14 , if correction is necessary, the selector  16  selects and outputs the corrected inclination ac. Otherwise, if correction is unnecessary, the selector  16  selects and outputs the inclination a.  
         [0047]     In step S 4 , the offset circuit  9  calculates the offset ΔX for the low-order bit string D from the reference value DM.  
         [0048]     In step S 5 , the inclination a or the corrected inclination ac is input to the multiplier  10 . The multiplier  10  calculates the product aΔX of the inclination a and the offset ΔX, or product acΔX of the corrected inclination ac and the offset ΔX.  
         [0049]     In step S 6 , the adder  11  calculates the sum of the initial value b and the product aΔX or acΔX. The adder  11  outputs the sum aΔX+b or acΔX+b as the calculation result Y.  
         [0050]     Next, a working example of the first embodiment is described. A case is described where the number of bits m of the high-order bit string U is three. The operands XI and X 2  belong to certain segments, respectively. In the following description, it is assumed that the operand X 1  is an operand X that does not need correction. In the following description, it is assumed that the operand X 2  is an operand X that needs correction. As in  FIG. 5 , the domain of the operand X can be divided into 2 3  segments C 0  to C 7 . There is a one-to-one correspondence between the high-order bit strings U 0  to U 7  and the segments C 0  to C 7 . The same low-order bit string D as DO is arranged in the same order within the segments C 0  to C 7 . Therefore, it is apparent that the high-order bit string U indicates one of the segments C 0  to C 7  to which the operand X belongs, and the operands X 1  and X 2  belong to the segment C 3 . In addition, it is understood that when substituting the operands X 1  and X 2  for the function y=f(x), there is an exact solutions Y 01  and Y 02 .  
         [0051]     The low-order bit strings D 1  and D 2  indicate the positions in the segments C 0  to C 7  to which the operands X 1  and X 2  belong. As shown in  FIG. 10 , it is apparent that the operands X 1  and X 2  belong to the segment C 3 .  
         [0052]     A certain point within each of the segments C 0  to C 7 , for example, the midpoint M is selected as the reference value DM. Note that the low-order (n-m-1) bit of the operand X or the difference between half of the segment C width and the low-order (n-m-1) bit of the operand X may be considered as the offset ΔX.  
         [0053]     In step S 2  of  FIG. 9 , the high-order bit string U 3  ( 011 ) in each of the operands X 1  and X 2  is input to the LUT 1 , and the initial value b 13  is then output therefrom.  
         [0054]     In step S 3 , the high-order bit string U 3  ( 011 ) of each of the operands X 1  and X 2  is input to the LUT 2 , and the inclination a 13  is output therefrom. A straight line represented by the initial value b 13  and the inclination a 13  is a straight line L 31 .  
         [0055]     In step S 11 , the high-order bit string U 3  ( 011 ) of each of the operands X 1  and X 2  is input to the LUT 3 , and the correction value α 13  is then output therefrom. The inclination resulting from correcting the inclination a 13  with the correction value α 13  is inclination ac, and the corrected straight line is straight line L 3 r.  
         [0056]     In step S 12 , the most significant bit Xn-m of each of the low-order bit strings D 1  and D 2  in the operands X 1  and X 2  is input to the determination circuit  13 , and the correction signal S is then output therefrom. As shown in  FIG. 10 , since the most significant bit Xn-m of the low-order bit string D 1  in the operand X 1  is 0, 0 is output as the correction signal S to indicate that correction is unnecessary. On the other hand, since the most significant bit Xn-m of the low-order bit string D 2  of the operand X 2  is 1, 1 is output as the correction signal S to indicate that correction is necessary.  
         [0057]     In step S 13 , the adder-subtracter  15  adds or subtracts the correction value α 13  to or from the inclination a 13 , and then outputs the corrected inclination ac (=a 13 +α 13 ).  
         [0058]     In step S 14 , the selector  16  selects and outputs the inclination a 13  since the operand X 1  does not need to be corrected. On the other hand, the selector  16  selects and outputs the corrected inclination ac since the operand X 2  needs to be corrected.  
         [0059]     In step S 4 , the offset circuit  9  calculates an offset ΔX 1  or the difference between the reference value DM and the low-order bit string D 1  in the operand X 1 . The offset circuit  9  calculates an offset ΔX 2  or the difference between the reference value DM and the low-order bit string D 2  in the operand X 2 .  
         [0060]     In step S 5 , the multiplier  10  calculates the product a 13 ΔX 1  of the offset ΔX 1  and the inclination a 13  in the operand X 1 . The multiplier  10  calculates the product (a 13 +α 13 ) ΔX 2  of the offset ΔX 2  and the corrected inclination ac (=a 13 +α 13 ) in the operand X 2 .  
         [0061]     In step S 6 , the adder  11  calculates the calculation result Y 1  (=a 3 ΔX 1 +b 13 ) or the sum of the product a 13 ΔX 1  and the initial value b 13  of the operand X 1 , and then outputs the result to the register  6 . The adder  11  calculates the calculation result Y 2  (=(a 13 +α 13 )ΔX 2 +b 13 ) or the sum of the product (a 13 +α 13 )ΔX 2  and the initial value b 13  of the operand X 2 , and then outputs the result to the register  6 .  
         [0062]     In the first embodiment, whether correction is necessary is determined by using the high-order bit Xn-m of the low-order bit strings D 1  and D 2  in the operands X 1  and X 2 . If correction is necessary, the initial values b 10  to b 17  and the inclinations a 10  to a 17  are corrected. This allows provision of a highly accurate approximation without considerable increase in circuit size. In addition, the approximation accuracy can be improved by adding a simple circuit without increase in the number of entries 2 m  in the LUT 0 . On the other hand, the circuit area of the first embodiment can be reduced as long as enhancement of the approximation accuracy is unnecessary.  
         [0063]     Note that a straight line represented by the initial value b 13  and the inclination a 13  is straight line L 31 . The initial value b 13  and the inclination a 13  are predetermined so as to minimize the error between the straight line and the function f(x) in the left half region in the segment C 3 , which is divided in half at the midpoint M corresponding to the reference value DM. The determination circuit  13  determines that correction is necessary only when the high-order bit Xn-m of the low-order bit strings D 1  and D 2  in the operands X 1  and X 2  corresponds to the right half region in the segment C 3 , which is divided in half at the midpoint M corresponding to the reference value DM. The correction value α corrects the inclination a with the fixed initial value b, and the straight line is then corrected from the straight line L 31  into the straight line L 3 r. A correction value α 13  is preset to the correction value α so as to decrease the error between the corrected straight line representing the straight line L 3 r and the function f(x) in the right half region in the segment C 3 .  
         [0064]     In other words, the inclinations a 13  and ac, which allow a decrease in the error, are calculated, and the inclination a 13  is then stored in the LUT 2  for the respective right half and left half regions sandwiching the midpoint M. The difference between the inclinations ac and a 13  is stored in the LUT 3  as the correction value α. Depending on the target function f(x), typically, the difference between the inclinations of the adjacent regions is small; therefore, the number of digits of the correction value α can be decreased to less than the number of digits of the inclination a. The area in the LUT 3  occupied by the correction value α can be decreased to less than the area in the LUT 2  occupied by the inclination a.  
         [0065]     According to the first embodiment, a function approximation arithmetic unit, which decreases the error between a function and a corresponding straight line without an exponential increase in LUT size, can be provided.  
       Second Embodiment  
       [0066]     As shown in  FIG. 11 , an arithmetic unit  8  according to a second embodiment includes an LUT 0 , an offset circuit  9 , a multiplier  10 , an adder  11 , a determination circuit  13 , and a correction circuit  23 . The LUT 0  includes a LUT 1 , a LUT 2 , a LUT 3 , and a LUT 4 .  
         [0067]     In step S 2  of  FIG. 12 , high-order bit strings U 0  to U 7  are input to the LUT 1 , and initial values b 20  to b 27  are then output therefrom. In step S 3 , the high-order bit strings U 0  to U 7  are input to the LUT 2 , and inclinations a 20  to a 27  are then output therefrom. In step S 11 , the high-order bit strings U 0  to U 7  are input to the LUT 3 , and correction values (α 20  to α 27  are then output therefrom. In step S 15 , the high-order bit strings U 0  to U 7  are input to the LUT 4 , and correction values β 20  to β 27  are then output therefrom. The correction value β, which is used to correct an initial value b, is smaller than the initial value b. This decreases in the error between a function and a corresponding straight line without an exponential increase in LUT 0  size.  
         [0068]     The determination circuit  13  includes a buffer  14  when each of the segments C 0  to C 7  is divided into halves: the left half that is a region not to be corrected, and the right half that is to be corrected. Note that the buffer  14  is only an example; alternatively, the determination circuit  13  may include logic circuits corresponding to the divided regions to be corrected and not corrected in each of the segments C 0  to C 7 . For example, in step S 12 , the most significant bit Xn-m of the low-order bit string D in the operand X is input to the buffer  14 , and a correction signal S is then output therefrom. The determination circuit  13  functions in the same way as that of the first embodiment.  
         [0069]     The correction signal S is input to the correction circuit  23 . If correction is necessary, the correction circuit  23  adds or subtracts the correction value α to or from the inclination a to correct the inclination a. The corrected inclination ac is output from the correction circuit  23 . If correction is unnecessary, the correction circuit  23  outputs the inclination a without correction.  
         [0070]     If correction is necessary, the correction circuit  23  adds or subtracts the correction value β to or from the initial value b to correct the initial value b. The corrected initial value bc is output from the correction circuit  23 . If correction is unnecessary, the correction circuit  23  outputs the initial value b without correction. The correction circuit  23  includes adder-subtracters  15  and  17  and selectors  16  and  18 . In step S 13 , the adder-subtracter  15  adds or subtracts the correction value α to or from the inclination a, and then outputs the corrected inclination ac. If correction is necessary, in step S 14 , the selector  16  selects and outputs the corrected inclination ac. Otherwise, if correction is unnecessary, the selector  16  then selects and outputs the inclination a. In step S 16 , the adder-subtracter  17  adds or subtracts the correction value β to or from the initial value b, and then outputs the corrected initial value bc. If correction is necessary, in step S 17 , the selector  18  then selects and outputs the corrected initial value bc. Otherwise, if correction is unnecessary, the selector  18  then selects and outputs the initial value b.  
         [0071]     In step S 4 , the offset circuit  9  calculates the offset ΔX for the low-order bit string D from the reference value DM.  
         [0072]     In step S 5 , the inclination a or the corrected inclination ac is input to the multiplier  10 . The multiplier  10  calculates the product aΔX of the inclination a and the offset ΔX, or product acΔX of the corrected inclination ac and the offset ΔX.  
         [0073]     In step S 6 , the adder  11  calculates the sum of the initial value b and the product aΔX, or sum of the corrected initial value bc and the product acΔX. The adder  11  outputs the sum aΔX+b or acΔX+bc as the calculation result Y.  
         [0074]     Next, a working example of the second embodiment is described. A case is described where the number of bits m of the high-order bit string U is three. The operands X 1  and X 2  belong to certain segments, respectively. In the following description, it is assumed that the operand X 1  is an operand X that does not need to be corrected. In the following description, it is assumed that the operand X 2  is an operand X that needs to be corrected. As in  FIG. 5 , the domain of the operand X can be divided into 2 3  segments C 0  to C 7 . There is a one-to-one correspondence between the high-order bit strings U 0  to U 7  and the segments C 0  to C 7 . The same low-order bit string D as DO is arranged in the same order within the segments C 0  to C 7 . Therefore, it is apparent that the high-order bit string U indicates one of the segments C 0  to C 7  to which the operand X belongs, and, as shown in  FIG. 13 , the operands X 1  and X 2  belong to the segment C 3 . In addition, when substituting the operands X 1  and X 2  for the function y=f(x), it can be seen that there are exact solutions Y 01  and Y 02 .  
         [0075]     The low-order bit strings D 1  and D 2  indicate the positions in the segments C 0  to C 7  to which the operands X 1  and X 2  belong. As shown in  FIG. 13 , it is apparent that the operands X 1  and X 2  belong to the segment C 3 .  
         [0076]     A point within each of the segments C 0  to C 7 , for example, the midpoint M in each thereof is selected as the reference value DM.  
         [0077]     In step S 2  of  FIG. 12 , the high-order bit string U 3  ( 011 ) of each of the operands X 1  and X 2  is input to the LUT 1 , and initial value b 23  is then output therefrom.  
         [0078]     In step S 3 , the high-order bit string U 3  ( 011 ) of each of the operands X 1  and X 2  is input to the LUT 2 , and inclination a 23  is then output therefrom. A straight line represented by the initial value b 23  and the inclination a 23  is straight line L 31 .  
         [0079]     In step S 11 , the high-order bit string U 3  ( 011 ) of each of the operands X 1  and X 2  is input to the LUT 3 , and correction value α 23  is then output therefrom. The inclination resulting from correcting the inclination a 23  with the correction value α 23  is the corrected inclination ac.  
         [0080]     In step S 15 , the high-order bit string U 3  ( 011 ) of each of the operands X 1  and X 2  is input to the LUT 4 , and correction value β 23  is then output therefrom. The inclination resulting from correcting the initial value b 23  with the correction value β 23  is the corrected initial value bc. A corrected straight line represented by the corrected inclination ac and the corrected initial value bc is straight line L 3 r.  
         [0081]     In step S 12 , the most significant bit Xn-m of each of the low-order bit strings D 1  and D 2  of the operands X 1  and X 2  is input to the determination circuit  13 , and a correction signal S is then output therefrom. As shown in  FIG. 13 , since the most significant bit Xn-m of the low-order bit string D 1  in the operand X 1  is 0, 0 is output as the correction signal S indicating that correction is unnecessary. On the other hand, since the most significant bit Xn-m of the low-order bit string D 2  in the operand X 2  is 1, 1 is output as the correction signal S indicating that correction is necessary.  
         [0082]     In step S 13 , the adder-subtracter  15  adds or subtracts the correction value α 23  to or from the inclination a 23 , and then outputs the corrected inclination ac (=a 23 +α 23 ).  
         [0083]     In step S 14 , the selector  16  selects and outputs the inclination a 23  since the operand X 1  does not need to be corrected. On the other hand, the selector  16  selects and outputs the corrected inclination ac since the operand X 2  needs to be corrected.  
         [0084]     In step S 16 , the adder-subtracter  17  adds or subtracts the correction value β 23  to or from the initial value b 23 , and then outputs the corrected initial value bc (=b 23 +β 23 ).  
         [0085]     In step S 17 , the selector  18  selects and outputs the initial value b 23  since the operand X 1  does not need to be corrected. On the other hand, the selector  18  selects and outputs the corrected initial value bc since the operand X 2  needs to be corrected.  
         [0086]     In step S 4 , the offset circuit  9  calculates an offset ΔX 1  or the difference between the reference value DM and the low-order bit string D 1  of the operand X 1 . The offset circuit  9  calculates an offset ΔX 2  or the difference between the reference value DM and the low-order bit string D 2  of the operand X 2 .  
         [0087]     In step S 5 , the multiplier  10  calculates the product a 23 ΔX 1  of the offset ΔX 1  and the inclination a 23  of the operand X 1 . The multiplier  10  calculates the product (a 23 +α 23 ) ΔX 2  of the offset ΔX 2  and the corrected inclination ac (=a 23 +α 23 ) of the operand X 2 .  
         [0088]     In step S 6 , the adder  11  calculates the calculation result Y 1  (=a 23 ΔX 1 +b 23 ) or the sum of the product a 23 ΔX 1  and the initial value b 23  of the operand X 1 , and then outputs the resulting value to the register  6 . The adder  11  calculates the calculation result Y 2  (=(a 23 +α 23 ) ΔX 2 +(b 23 +β 23 )) or the sum of the product (a 23 +α 23 ) ΔX 2  and the corrected initial value bc (b 23 +β 23 ) of the operand X 2 , and then outputs the resulting value to the register  6 .  
         [0089]     In the second embodiment, whether or not correction is necessary is determined by using the high-order bit Xn-m of the low-order bit strings D 1  and D 2  in the operands X 1  and X 2 . If correction is necessary, the initial values b 20  to b 27  and the inclinations a 20  to a 27  are corrected. This provides a highly accurate approximation without considerable increase in circuit size. In addition, the approximation accuracy can be improved by adding a simple circuit without increasing in the number of entries in the LUT 0 . The circuit area of the second embodiment can be reduced compared to the prior arts as long as enhancement of the approximation accuracy is not required.  
         [0090]     Note that a straight line represented by the initial value b 23  and the inclination a 23  is straight line L 31 . The initial value b 23  and the inclination a 23  are predetermined so as to decrease the error between the straight line and the function f(x) in the left half region in the segment C 3 , which is divided in half at the midpoint M corresponding to the reference value DM. The determination circuit  13  determines that correction is necessary only when the high-order bit Xn-m of the low-order bit strings D 1  and D 2  in the operands X 1  and X 2  corresponds to the divided right half region in the segment C 3 . The correction values a and A are used to correct the inclination a and the initial value b, and the straight line L 31  is corrected to straight line L 3 r. The correction values α 23  and β 23  are predetermined so as to decrease the error between the corrected straight line indicating the straight line L 3 r and the function f~x) in the right half region in the segment C 3 .  
         [0091]     In other words, the inclinations a 23  and ac and the initial values b 23  and bc, which minimize the error, are calculated, and the initial value b 23  is stored in the LUT 1 , and the inclination a 23  is then stored in the LUT 2  for the right half and the left half region sandwiching the midpoint M. The difference between the inclinations ac and a 23  is stored in the LUT 3  as the correction value α 23 , and the difference between the initial values bc and b 23  is stored in the LUT 4  as the correction value β 23 . Since the difference of the inclinations a in the adjacent segments is small, the size of the LUT 3  for the correction value α can be smaller than the size of the LUT 2  for the inclination a. Similarly, since the difference of the initial values b in the adjacent regions is small, the size of the LUT 4  for the correction value β can be smaller than the size of the LUT 1  for the initial value b.  
         [0092]     According to the second embodiment, a function approximation arithmetic unit, which decreases in the error between a function and a corresponding straight line without an exponential increase in LUT size, can be provided.  
       Third Embodiment  
       [0093]     As shown in  FIG. 14 , an arithmetic unit  8  according to a third embodiment includes an LUT 0 , an offset circuit  9 , a multiplier  10 , an adder  11 , a determination circuit  13 , and a correction circuit  23 . The determination circuit  13  includes an addition-subtraction determination circuit  12 . The LUT 0  includes an LUT 1 , an LUT 2 , and an LUT 4 .  
         [0094]     In step S 2  of  FIG. 15 , the high-order bit strings U 0  to U 7  are input to the LUT 1 , and initial values b 40  to b 47  are then output therefrom. In step S 3 , the high-order bit strings U 0  to U 7  are input to the LUT 2  and inclinations a 40  to a 47  are then output therefrom. In step S 15 , the high-order bit strings U 0  to U 7  are input to the LUT 4 , and correction values β 40  to β 47  are then output therefrom.  
         [0095]     The determination circuit  13  includes an exclusive OR inverter  20  for the case of dividing each of the segments C 0  to C 7  into eight regions in which both ends and central regions are to be corrected, and the other regions are not to be corrected. Note that the exclusive OR inverter  20  is only an example; alternatively, the determination circuit  13  may include logic circuits corresponding to the divided regions to be corrected and not to be corrected, respectively, in each of segments C 0  to C 7 . For example, in step S 12 , the second high-order bit Xn-m- 1  and the third high-order bit Xn-m- 2  of the low-order bit string D in the operand X are input to the exclusive OR inverter  20 , and a correction signal S 1  is then output therefrom. When (Xn-m- 1 , Xn-m- 2 ) is (0, 1) and (1, 0), 0 is output as the correction signal S 1  indicating that correction is unnecessary. When (Xn-m- 1 , Xn-m- 2 ) is (0, 0) and (1, 1), 1 is output as the correction signal S 1  indicating that correction is necessary.  
         [0096]     The addition-subtraction determination circuit  12  includes an exclusive OR inverter  19  for dividing each of the segments C 0  to C 7  into eight regions in which both ends are to be corrected by addition, and the central region is to be corrected by subtraction. Note that the exclusive OR inverter  19  is only an example; alternatively, the addition-subtraction determination circuit  12  may include logic circuits corresponding to the divided regions to be corrected by addition and to be corrected by subtraction in each segment C 0  to C 7 . For example, in step S 18 , the most significant bit Xn-m and the second high-order bit Xn-m- 1  of the low-order bit string D in the operand X are input to the addition-subtraction determination circuit  12 , and an addition-subtraction signal S 2  is then output therefrom. When (Xn-m, Xn-m- 1 ) is (0, 1) and (1, 0), 0 is output as the addition-subtraction signal S 2  indicating subtraction. When (Xn-m, Xn-m- 1 ) is (0, 0) and (1, 1), 1 is output as the addition-subtraction signal S 2  indicating addition.  
         [0097]     The correction signal S 1  and the addition-subtraction signal S 2  are input to the correction circuit  23 . If the addition-subtraction signal S 2  indicates addition, the correction circuit  23  adds the correction value β to the initial value b to correct the initial value b. Otherwise, if the addition-subtraction signal S 2  indicates subtraction, the correction circuit  23  subtracts the correction value β from the initial value b to correct the initial value b. If the correction signal S 1  indicates that correction is necessary, the corrected initial value bc is output from the correction circuit  23 . Otherwise, if the correction signal S 1  indicates that correction is unnecessary, the correction circuit  23  outputs the initial value b without correction. The correction circuit  23  includes an adder-subtracter  17  and a selector  18 . In step S 16 , the adder-subtracter  17  adds or subtracts the correction value β¤ to or from the initial value b by using the addition-subtraction signal S 2 , and then outputs the corrected initial value bc. If correction is necessary, in step S 17 , the selector  18  then selects and outputs the corrected initial value bc. Otherwise, if correction is unnecessary, the selector  18  selects and outputs the initial value b.  
         [0098]     In step S 4 , the offset circuit  9  calculates the offset ΔX of the low-order bit string D from the reference value DM.  
         [0099]     In step S 5 , the inclination a is input to the multiplier  10 . The multiplier  10  calculates the product aΔX of the inclination a and the offset ΔX.  
         [0100]     In step S 6 , the adder  11  calculates the sum of the product aΔX and the initial value b or the corrected initial value bc. The adder  11  outputs the sum aΔX+b or aΔX+bc as the calculation result Y.  
         [0101]     Next, a working example of the third embodiment is described. A case is described where the number of bits m of the high-order bit string U is three. The operands X 3 , X 4 , and X 5  belong to certain segments, respectively. In the following description, it is assumed that the operand X 3  is operand X that does not need to be corrected. In the following description, it is assumed that the operand X 4  is operand X that needs to be corrected by subtraction. In the following description, it is assumed that the operand X 5  is operand X that needs to be corrected by addition. As in  FIG. 5 , the domain of the operand X can be divided into 2 3  segments C 0  to C 7 . There is a one-to-one correspondence between the high-order bit strings U 0  to U 7  and the segments C 0  to C 7 . The same low-order bit string D as D 0  is arranged in the same order within the segments C 0  to C 7 . Therefore, it is apparent that the high-order bit string U indicates one of the segments C 0  to C 7  to which the operand X belongs, and, as shown in  FIG. 16 , the operands X 3 , X 4 , and X 5  belong to the segment C 3 . In addition, when substituting the operands X 3 , X 4 , and X 5  for the function y=f(x), it can be seen that there are exact solutions Y 03 , Y 04 , and Y 05 .  
         [0102]     The low-order bit string D of the operand X indicates the positions in the segments C 0  to C 7  to which operands X 3  to X 5  belong. In  FIG. 16 , pay attention to the top three bits Xn-m, Xn-m- 1 , and Xn-m- 2  of the low-order bit string D. The segment C 3  can be subdivided by the top three bits Xn-m, Xn-m- 1 , and Xn-m- 2  into 2 3 or 8 regions Z 0  to Z 7 . There is a one-to-one correspondence between (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1),(1, 1, 0),and (1, 1, 1) of the top three bits (Xn-m, Xn-m- 1 , Xn-m- 2 ) and the regions Z 0  to Z 7 . Therefore, it is apparent that the top three bits (Xn-m, Xn-m- 1 , Xn-m- 2 ) indicate one of the regions Z 0  to Z 7  to which the operand X belongs, and the operands X 3 , X 4 , and X 5  belong to the regions Z 1 , Z 3 , and Z 7 , respectively. In addition, it is apparent that the operands X 3 , X 4 , and X 5  belong to the segment C 3 . A point within each of segments C 0  to C 7 , for example, the midpoint M in each thereof is selected as the reference value DM.  
         [0103]     In step S 2  of  FIG. 15 , the high-order bit string U 3  ( 011 ) of each of the operands X 3  through X 5  is input to the LUT 1 , and initial value b 43  is then output therefrom.  
         [0104]     In step S 3 , the high-order bit string U 3  ( 011 ) of each of the operands X 3  through X 5  is input to the LUT 2 , and inclination a 43  is then output therefrom. A straight line represented by the initial value b 43  and the inclination a 43  is straight line L 3 .  
         [0105]     In step S 15 , the high-order bit string U 3  ( 011 ) of each of the operands X 3  through X 5  is input to the LUT 4 , and correction value β 43  is then output therefrom. The initial value resulting from adding the initial value b 43  to the correction value β 43  or subtracting the initial value b 43  from the correction value β 43  is the corrected initial value bc. Corrected straight lines represented by the corrected initial value bc are straight lines L 3 + and L 3 .  
         [0106]     In step S 12 , the second high-order bit Xn-m- 1  and the third high-order bit Xn-m- 2  of the low-order bit string D in the operand X are input to the determination circuit  13 , and a correction signal S 1  is then output therefrom. As shown in  FIG. 16 , 1 indicating that correction is necessary is output as the correction signal S 1  only when the top three bits (Xn-m, Xn-m- 1 , Xn-m- 2 ) are (0, 0, 0), (0, 1, 1), (1, 0, 0), or (1, 1, 1). In addition, 1 indicating that correction is necessary is output as the correction signal S 1  only when the operand X belongs to a region Z 0 , Z 3 , Z 4 , or Z 7 . In this case, since the operand X 3  belongs to the region Z 1 , 0 is output as the correction signal S 1  indicating that correction is unnecessary. On the other hand, since the operands X 4  and X 5  belong to the regions Z 3  and Z 7 , respectively, 1 is output as the correction signal S 1  indicating that correction is necessary.  
         [0107]     In step S 18 , the most significant bit Xn-m and the second high-order bit Xn-m- 1  of the low-order bit string D in the operand X are input to the addition-subtraction determination circuit  12 , and an addition-subtraction signal S 2  is then output therefrom. As shown in  FIG. 16, 1  indicating addition is output as the addition-subtraction signal S 2  only when the top three bits (Xn-m, Xn-m- 1 , Xn-m- 2 ) are (0, 0, 0), (0, 0, 1), (1, 1, 0), or (1, 1, 1). In addition, 1 indicating addition is output as the addition-subtraction signal S 2  only when the operand X belongs to a region Z 0 , Z 1 , Z 6 , or Z 7 . In this case, since the operands X 3  and X 5  belong to the regions Z 1  and Z 7 , 1 is output as the addition-subtraction signal S 2  indicating addition. On the other hand, since the operand X 4  belongs to the region Z 3 , 0 is output as the addition-subtraction signal S 2  indicating subtraction.  
         [0108]     Note that whether or not correction is necessary, an indication for addition-subtraction of correction values for the regions Z 0  to Z 7  are shown. The regions Z 0  and Z 7  need correction, and a correction value is added. The regions Z 3  and Z 4  need correction, and a correction value is subtracted. On the other hand, the regions Z 1 , Z 2 , Z 5 , and Z 6  do not need correction. If correction is unnecessary, a correction value is not added or subtracted.  
         [0109]     In step S 16 , the adder-subtracter  17  adds the correction value β 43  to the initial value b 43  or subtracts the correction value β 43  from the initial value b 43 , by using the addition-subtraction signal S 2 , and then outputs the corrected initial value bc (=b 43 +β 43  or b 43 -β 43 ). In this case, since the operands X 3  and X 5  belong to the regions Z 1  and Z 7 , the corrected initial value bc (=b 43 +β 43 ) is output. On the other hand, since the operand X 4  belongs to the region Z 3 , the corrected initial value bc (=b 43 −β 43 ) is output.  
         [0110]     In step S 17 , the selector  18  selects and outputs the initial value b 43 , since the operand X 3  belongs to the region Z 1  and does not need correction. Since the operand X 4  belongs to the region Z 3  and needs correction, the selector  18  outputs the corrected initial value bc (=b 43 −β 43 ). Since the operand X 5  belongs to the region Z 7  and needs correction, the selector  18  outputs the corrected initial value bc (=b 43 +β 43 ).  
         [0111]     In step S 4 , the offset circuit  9  calculates the offsets ΔX 3  to ΔX 5  or the difference between the reference value DM and the low-order bit string D of each of the operands X 3  to X 5 .  
         [0112]     In step S 5 , the multiplier  10  calculates the products a 43 ΔX 3  to a 43 ΔX 5  of the inclination a 43  and each of the offsets ΔX 3  to ΔX 5  of the operands X 3  to X 5 .  
         [0113]     In step S 6 , the adder  11  calculates the calculation result Y 3  (=a 43 ΔX 3  +b 43 ) or the sum of the product a 43 ΔX 3  and the initial value b 43  of the operand X 3 , and then outputs the resulting value to the register  6 . The adder  11  calculates the calculation result Y 4  (=a 43 ΔX 4 +b 43 −β 43 ) or the sum of the product a 43 ΔX 4  and the corrected initial value bc (=b 43 −β 43 ) of the operand X 4 , and then outputs the result to the register  6 . The adder  11  calculates the calculation result Y 5  (=a 43 ΔX 5 +b 43 +β 43 ) or the sum of the product a 43 ΔX 5  and the corrected initial value bc (=b 43 +β 43 ) of the operand X 5 , and then outputs the resulting value to the register  6 .  
         [0114]     According to the third embodiment, whether or not correction is necessary is determined by using the high-order bits Xn-m- 1  and Xn-m- 2  of the low-order bit string D in the operand X. The correction value is added to the high-order bits Xn-m and Xn-m- 1  of the low-order bit string D or subtracted from the high-order bits Xn-m and Xn-m- 1  for correction. If correction is necessary, the correction value is added to the initial values b 40  to b 47  or subtracted from the initial values b 40  to b 47 . This provides a highly accurate approximation without a considerable increase in circuit size. In addition, the approximation accuracy can be improved by adding a simple circuit without an increase in the number of entries 2 m  in the LUT 0 . On the other hand, the circuit area of the third embodiment can be reduced to less than that of the prior art as long as enhancement of the approximation accuracy is not required.  
         [0115]     Note that a straight line represented by the initial value b 43  and the inclination a 43  is straight line L 3 . The initial value b 43  and the inclination a 43  are predetermined so as to decrease the error between the straight line L 3  and the function f(x) in the regions Z 1 , Z 2 , Z 5 , and Z 6 . The initial value bc is predetermined so as to decrease the error between the straight line L 3 +and the function f(x) in the regions Z 0  and Z 7 . The initial value bc is predetermined so as to decrease the error between the straight line L 3  and the function f(x) in the regions Z 3  and Z 4 . The correction value β 43  is predetermined by using the prescribed initial value bc. Since the difference of the initial values b in the adjacent regions Z 0  to Z 7  is small, the LUT 4  size for the correction value P can be decreased to less than the LUT 1  size for the initial value b.  
         [0116]     According to the third embodiment, a function approximation arithmetic unit, which decreases the error between a function and a corresponding straight line without a considerable increase in LUT size, can be provided.  
       Fourth Embodiment  
       [0117]     As shown in  FIG. 17 , an arithmetic unit  8  according to a fourth embodiment includes an LUT 0 , an offset circuit  9 , a multiplier  10 , an adder  11 , a determination circuit  13 , and a correction circuit  23 .  
         [0118]     The LUT 0  includes an LUT 1 , an LUT 2 , and an LUT 3 . The high-order m bits U (m&lt;n) of the n-bit input operand X are input to the LUT 1 , and an initial value b corresponding to the high-order m bits U is then output therefrom. An inclination a corresponding to the same high-order m bits U is output from the LUT 2 . The same high-order m bits U is input to the LUT 3 , and the correction shift amount e or the correction amount relative to the initial value b is then output therefrom. In the case of a straight line represented by the initial value b and the inclination a, the error from the target function f(x) tends to increase at the endpoint and the midpoint in the segment C. An inclination value that decreases the error in such a region where the error is large is calculated from the value 2 e  or the difference of 2 e  from the inclination a stored in the LUT 2 . The power e may be a positive number or a negative number. The power e is stored in the LUT 3  as the amount of correction shift.  
         [0119]     Several high-order bits Xn-m of the low-order (n-m) bit D in the input operand X are input to the determination circuit  13 , and whether or not correction is necessary is then determined. If the number of the high-order bits Xn-m is one bit, the determination circuit  13  determines whether or not correction is necessary as same as the first and the second embodiments. Otherwise, if the number is two or greater bits, the determination circuit  13  determines whether or not correction is necessary as same as the third embodiment.  
         [0120]     The offset circuit  9  calculates the offset ΔX between the input operand X and the reference value DM in the domain C specified by the high-order m bits U.  
         [0121]     The correction circuit  23  includes an inverter  22 , a selector  16 , a shifter  21 , and an adder-subtracter  15 . The selector  16  selects and outputs one of the three inputs of the offset value ΔX, an inverted value of the offset value ΔX, and 0 (zero), which are output from the offset circuit  9 , in conformity with the output from the determination circuit  13 . The shifter  21  shifts the output from the selector  16  in conformity with the correction shift amount e or the output from the LUT 3 . Shifting is considered as easy multiplication or division. The adder-subtracter  15  adds the output from the shifter  21  to the initial value b or subtracts the output from the shifter  21  from the initial value b, and then outputs the resulting value; alternatively, the adder-subtracter  15  just outputs the output from the shifter  21  as is.  
         [0122]     The multiplier  10  calculates the product aΔX of the inclination a and the offset ΔX.  
         [0123]     The adder  11  adds the product aΔX and the initial value b, which is not corrected and is output from the adder-subtracter  15  of the correction circuit  23 , or the corrected initial value bc+ or bc−.  
         [0124]     In the fourth embodiment, the inclination is corrected by adding the correction value 2 e  to the inclination a. As a result, Equation (1) before correction is modified as Equation (2) after correction. In addition, Equation (2) can be modified as Equation (3). 
 
 Y=aΔX+b . . .    (1) 
 
 Y= ( a+ 2 e )ΔX+ b    (2) 
 
 Y=aΔX+ (2 e   ΔX+b )   (3) 
 
         [0125]     From Equation (3), correction by adding correction value 2 e  to the inclination a is considered to be the same as correction by adding correction value 2 e ΔX to the initial value b. The correction value 2 e ΔX is the product of the offset value ΔX and the correction value 2 e  of the inclination a. In addition, if the inclination a is represented in a binary format, the product can be calculated by shifting the value of the inclination a by e digits of the power e.  
         [0126]     The actual calculation is carried out as follows. To begin with, the high-order m bits U are input to the LUT 101 , the LUT 102 , and the LUT 103 , and the initial value b, the inclination a, and the correction shift amount e corresponding to the high-order m bits U are output therefrom, respectively.  
         [0127]     At the same time, the low-order (n-m) bits D of the input operand X are input to the offset circuit  9 , and the offset ΔX from the midpoint M is then output therefrom.  
         [0128]     In addition, the most significant bit Xm-n of the low-order (n-m) bits D in the input operand X is input to the determination circuit  13  simultaneously. Whether or not the region needs correction is determined through observation of the low-order (n-m) bits D, and a correction signal is output in accordance with the determination results.  
         [0129]     The selector  16  selects one of the offset ΔX of the offset circuit  9 , an inverted value of the offset ΔX inverted by the inverter  22 , and 0 (zero) in conformity with the correction signal.  
         [0130]     The shifter  21  shifts the selected offset ΔX, the inverted value of the offset ΔX, or 0 (zero) by the correction shift amount e. This allows determination of the absolute correction amount.  
         [0131]     The adder-subtracter  15  adds the selected offset ΔX, an inverted value of the offset ΔX, or 0 (zero) to the initial value b or subtracts the selected offset ΔX, an inverted value of the offset ΔX, or 0 (zero) from the initial value b, and then outputs the resulting value.  
         [0132]     The multiplier  10  multiplies the inclination a by the offset ΔX and then outputs the resulting product concurrently with that addition or subtraction.  
         [0133]     The adder  11  adds the output from the adder-subtracter  15  and the output from the multiplier  10 . This provides a function approximation as the final result.  
         [0134]     According to the fourth embodiment, the approximation accuracy may be improved without considerable increase in either the number of entries in the LUT 0  and in the calculation time.  
         [0135]     According to the fourth embodiment, a function approximation arithmetic unit, which decreases the error between a function and a corresponding straight line without an exponential increase in LUT size, can be provided.  
         [0136]     The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the present invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.