Abstract:
An oscillating apparatus includes: a transfer gate including a P-channel transistor and a N-channel transistor; a first inverter for inverting an output signal of the transfer gate and outputting the inverted output signal of the transfer gate; a second inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a third inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a fourth inverter for inverting the output signal of the third inverter and outputting the inverted output signal of the third inverter to an input-terminal of the transfer gate; a first capacitor connected between an output-terminal of the transfer gate and an output-terminal of the second inverter; and a second capacitor connected between the output-terminal of the transfer gate and a reference potential node.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-293178 filed on Dec. 24, 2009, the entire contents of which are incorporated herein by reference. 
     FIELD 
     This embodiments discussed herein are related to an oscillating apparatus. 
     BACKGROUND 
     Some integrated circuits such as a micro-controller have a built-in CR oscillating circuit (or ring oscillator) on a chip, and a clock signal for the micro-controller is supplied from the built-in oscillating circuit. This is because in the case of an oscillating circuit using a crystal resonator or ceramic resonator, the start-up time which means the time from power is turned on until the output frequency of the oscillating circuit stabilizes is long, and it is sometimes desirable to use a CR oscillating circuit, a ring oscillator, or the like having a shorter start-up time as a clock source, even with a decrease in the accuracy of oscillation frequency. More specifically, for applications that frequently repeat starting and stopping of an oscillating circuit, a waiting time occurs at the start-up of the oscillating circuit, and it is sometimes desirable from the viewpoint of overall system performance improvement to reduce the power consumption during this waiting time. Also, an on-chip oscillating circuit is sometimes used for the purpose of cost reduction as well. 
       FIG. 1  is a circuit diagram of a CR oscillating circuit. In the CR oscillating circuit, IV 1 , IV 2 , and IV 3  each denote an inverter, C 1  and C 2  each denote a capacitor, R 1  denotes a resistor, ND 1  to ND 4  each denote a node within the oscillating circuit, and GND denotes a ground potential (0 V). The waveform of each of the nodes ND 1 , ND 2 , and ND 3  is the output waveform (rectangular wave) of a CMOS circuit. The waveform of the node ND 4  is such that owing to capacitive coupling between the nodes ND 2  and ND 4 , at the time of a potential change of the node ND 2 , the potential of the node ND 4  changes in the same direction as the node ND 2 , and is thereafter gradually charged/discharged by the potential of the node ND 3  and the resistor R 1 . 
       FIG. 2  is a circuit diagram of another oscillating circuit. In  FIG. 2 , IV 1  and IV 4  each denote an inverter, C 1  and C 2  each denote a capacitor, NMn (n is an integer) denotes an N-channel MOS transistor, and PMn (n is an integer) denotes a P-channel MOS transistor. In  FIG. 2 , Vdd denotes a positive power supply voltage (for example, 3 V), GND denotes a ground potential (0 V), NDn (n is an integer) denotes a node within the oscillating circuit, VBGR denotes a constant voltage (for example, 2 V) generated from a band gap circuit, PB denotes the bias potential of a P-channel MOS transistor PM 1 , and NB denotes the bias potential of an N-channel MOS transistor NM 2 . 
     In the circuit illustrated in  FIG. 2 , nodes and elements corresponding to those of the circuit illustrated in  FIG. 1  are assigned the same symbols to make their correspondence clear. In the circuit illustrated in  FIG. 2 , a node ND 5  at one end of the capacitor C 1  is driven by an inverter (transistors PM 3  and NM 3 ) with the constant voltage VBGR as the power supply, thereby controlling the signal amplitude of the node ND 5  to be constant irrespective of temperature. In order to achieve a design in which frequency is independent of temperature, the circuit is so configured as to make the current flowing through transistors PM 2  and NM 1  constant independent of temperature. The bias potentials PB and NB are such potentials that make the current flowing through the transistors PM 2  and NM 1  constant. 
     The bias generation circuitry for generating the bias potentials PB and NB is all integrated on a semiconductor chip, and the circuit configuration as described below is adopted to generate a temperature-independent current. To generate a constant current, the potential generated by flowing a current through a resistor, and a reference voltage are made to coincide with each other by feedback control. By taking the temperature dependence of an on-chip resistor into account, temperature dependence is imparted to the reference voltage. The circuit is designed so that by imparting a positive temperature dependence to the reference voltage such that as the resistance becomes larger with a rise in temperature, the reference voltage also becomes larger with temperature, the temperature dependence of the resistor is cancelled out by the temperature dependence of the reference voltage, thereby ensuring that current is independent of temperature. The above-mentioned circuit realizes an oscillating circuit whose oscillation frequency is constant with respect to temperature and power supply voltage. 
     Although the circuit illustrated in  FIG. 1  succeeds in achieving an oscillation frequency that is independent of power supply voltage by use of the capacitors C 1  and C 2  and the resistor R 1 , the circuit has a drawback in that if the resistor R 1  is dependent on temperature, it is difficult to suppress fluctuation of oscillation frequency. In the case where the resistor R 1  is integrated into a semiconductor chip, for example, it is practically difficult to reduce the temperature dependence of the resistor R 1  below a certain level. Also, when the values of the resistor R 1  and capacitors C 1  and C 2  fluctuate owing to manufacturing variations, so does oscillation frequency. That is, the circuit illustrated in  FIG. 1  has the following problems: when the values of the resistor R 1  and capacitors C 1  and C 2  fluctuate owing to manufacturing variations, oscillation frequency also fluctuates; and when the value of the resistor R 1  varies owing to temperature fluctuation, oscillation frequency fluctuates. 
     The circuit illustrated in  FIG. 2  aims to cancel out the temperature dependence of a resistor by the temperature dependence of a pre-designed built-in reference voltage, and generate the bias potentials PB and NB for charging/discharging the capacitors C 1  and C 2  at constant current, thereby mitigating temperature variation of oscillation frequency. However, an error is present in the actual output potential VBGR of a reference voltage generation circuit. This error also causes the temperature dependence of the potential VBGR to become slightly positive or negative depending on each individual circuit manufactured. Even more ideally, even when the circuit is configured so as to make the current flowing through the transistors PM 2  and NM 1  constant independent of temperature, because an error is also present in this portion, the temperature dependence of the charging/discharging current for the capacitors C 1  and C 2  does not become exactly the same as a designed value, either. Furthermore, the delay time of the inverters IV 1  and IV 4  is also dependent on temperature and each individual circuit manufactured, and thus becomes the cause of an error in the temperature characteristics of oscillation frequency. 
     In the circuit illustrated in  FIG. 2 , even if it is attempted to control the current that charges the capacitors C 1  and C 2  to be constant by means of the bias potentials PB and NB, when the node ND 4  changes from low level to high level, the transistor NM 1  turns OFF, so the drain potential of the transistor NM 2  becomes the ground potential GND. Since a parasitic capacitance is present at the drain of the transistor NM 2 , when the node ND 4  changes from high level to low level, the discharging current for the node ND 4  does not become exactly the same as the current set by the bias potential NB. An extra electrical charge equivalent to the parasitic capacitance at the drain of the transistor NM 2  being charged from the ground potential GND to a given potential is discharged from the node ND 4 . Likewise, the parasitic capacitance at the drain of the transistor PM 1  also becomes the cause of an error in the setting of current. 
     Japanese Laid-open Patent Publication No. 63-304702 discloses an oscillating circuit configured so that, in a ring oscillator in which a plurality of stages of gates are serially connected and the gate output of the last stage is fed back to the gate input of the first stage to thereby excite oscillation, a transfer gate is inserted in between adjacent gates, and the transfer gate is connected to a control potential that may be made variable in an analog manner. 
     SUMMARY 
     According to an aspect of the embodiment, an oscillating apparatus includes: a transfer gate including a P-channel transistor and a N-channel transistor; a first inverter for inverting an output signal of the transfer gate and outputting the inverted output signal of the transfer gate; a second inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a third inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter, the third inverter being connected to a power supply potential node wire different from a power supply potential node wire for the second inverter; a fourth inverter for inverting the output signal of the third inverter and outputting the inverted output signal of the third inverter to an input-terminal of the transfer gate; a first capacitor connected between an output-terminal of the transfer gate and an output-terminal of the second inverter; and a second capacitor connected between the output-terminal of the transfer gate and a reference potential node, wherein the transfer gate outputs a signal at the input-terminal from the output-terminal in accordance with a gate voltage of each of the P-channel transistor and the N-channel transistor. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a circuit diagram of a CR oscillating circuit; 
         FIG. 2  is a circuit diagram of another oscillating circuit; 
         FIG. 3  is a circuit diagram illustrating an example of the configuration of a CR oscillating circuit of an embodiment; 
         FIG. 4  is a diagram illustrating an example of waveforms in various parts of the circuit illustrated in  FIG. 3 ; 
         FIG. 5  is a diagram illustrating an example of the configuration of a micro-controller (oscillating apparatus) mounted with the CR oscillating circuit illustrated in  FIG. 3 ; 
         FIG. 6  is a circuit diagram illustrating an example of the configuration of the band gap circuit illustrated in  FIG. 5 ; 
         FIG. 7  is a block diagram illustrating an example of the configuration of the CR oscillating circuit illustrated in  FIG. 5 ; 
         FIG. 8  is a circuit diagram illustrating an example of the configuration of the reference current generation circuit illustrated in  FIG. 7 ; 
         FIG. 9  is a circuit diagram illustrating an example of the configuration of the variable resistor illustrated in  FIG. 8 ; 
         FIG. 10  is a circuit diagram illustrating an example of the configuration of each of the amplifier circuits illustrated in  FIG. 8  and of the circuit in its vicinity; 
         FIG. 11  is a circuit diagram illustrating an example of the configuration of the trimming current DAC circuit illustrated in  FIG. 7 ; 
         FIG. 12  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit illustrated in  FIG. 7 ; 
         FIG. 13  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit illustrated in  FIG. 7 ; 
         FIG. 14  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit illustrated in  FIG. 7 ; and 
         FIG. 15  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit illustrated in  FIG. 7 . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
       FIG. 3  is a circuit diagram illustrating an example of the configuration of a CR oscillating circuit of an embodiment.  FIG. 4  is a diagram illustrating an example of waveforms in various parts of the circuit illustrated in  FIG. 3 . The circuit illustrated in  FIG. 3  will be described with reference to  FIG. 4 . In  FIG. 3 , NMn (n is an integer) denotes an N-channel MOS transistor, PMn (n is an integer) denotes a P-channel MOS transistor, Vdd denotes a positive power supply potential (for example, 1.8 V), VR 18  denotes a positive power supply potential (for example, 1.8 V), and GND denotes a reference potential (ground potential: 0 V). In  FIG. 3 , NDn (n is an alphanumeric character) denotes a node within the oscillating circuit, IV 1 , IV 4 , and IV 5  each denote an inverter, C 1 , C 2 , CNB, and CPB each denote a capacitor, IBIASROSC denotes a bias current for the circuit illustrated in  FIG. 3 , PB denotes the gate bias potential of a transistor PM 5 , NB denotes the gate bias potential of a transistor NM 5 , CLK 1  denotes a clock signal, and VREG 1  denotes a circuit that generates the power supply potential VR 18 . The inverters IV 1 , IV 4 , and IV 5  each output a signal that is the logical inversion of an input signal. In  FIG. 3 , elements having the same functions as those in the circuits illustrated in  FIGS. 1 and 2 , and the corresponding nodes are assigned the same symbols to indicate their correspondence. The bias current IBIASROSC will be described with reference to the circuit illustrated in  FIG. 11  described later. 
     A transistor PM 7  has a source connected to the node of the power supply potential Vdd, and a gate connected to the node of the reference potential GND. A transistor PM 8  has a source connected to the drain of the transistor PM 7 , and a gate and a drain that are connected to each other. The bias current IBIASROSC is the drain current of each of the transistors PM 7  and PM 8 . A transistor PM 9  has a source connected to the node of the power supply potential Vdd, and a gate connected to the node of the reference potential GND. A transistor PM 10  has a source connected to the drain of the transistor PM 9 , and a gate connected to the drain of the transistor PM 8 . A transistor NM 7  has a drain and a gate that are connected to the drain of the transistor PM 10 . A transistor NM 8  has a drain connected to the source of the transistor NM 7 , a gate connected to the node of the power supply potential Vdd, and a source connected to the node of the reference potential GND. The capacitor CPB is connected between the node of the power supply potential Vdd and the drain of the transistor PM 8 . The capacitor CNB is connected between the drain of the transistor NM 7  and the node of the reference potential GND. 
     A transistor PM 4  has a source connected to the node of the power supply potential Vdd, and a gate connected to the output terminal of the inverter IV 4 . A transistor NM 4  has a drain connected to the drain of the transistor PM 4 , a gate connected to the output terminal of the inverter IV 4 , and a source connected to the node of the reference potential GND. The transistors PM 4  and NM 4  constitute an inverter. A transistor PM 5  has a source connected to the drain of the transistor PM 4 , a gate connected to the drain of the transistor PM 8 , and a drain connected to the input terminal of the inverter IV 1 . A transistor NM 5  has a source connected to the drain of the transistor PM 4 , a gate connected to the drain of the transistor NM 7 , and a drain connected to the input terminal of the inverter IV 1 . The transistors PM 5  and NM 5  constitute a transfer gate. The bias potential PB is the gate potential of the transistor PM 5 . The bias potential NB is the gate potential of the transistor NM 5 . For example, the bias potential PB is 1 V, and the bias potential NB is 0.8 V. 
     A node ND 4  is connected to the input terminal of the inverter IV 1 . The capacitor C 2  is connected between the node ND 4  and the node of the reference potential GND. A node ND 1  is connected to the output terminal of the inverter IV 1 . The inverter IV 5  performs logical inversion of the signal of the node ND 1 , and outputs the clock signal CLK 1 . The constant voltage generation circuit VREG 1  generates the power supply potential VR 18  (for example, 1.8 V). A transistor PM 6  has a source connected to the node of the power supply potential VR 18 , a gate connected to the node ND 1 , and a drain connected to a node ND 5 . A transistor NM 6  has a drain connected to the node ND 5 , a gate connected to the node ND 1 , and a source connected to the node of the reference potential GND. The transistors PM 6  and NM 6  constitute an inverter. The capacitor C 1  is connected between the nodes ND 4  and ND 5 . The inverter IV 4  has an input terminal connected to the node ND 1 , and an output terminal connected to a node ND 6 . 
     In the circuit illustrated in  FIG. 2 , even if it is attempted to control the current that charges the capacitors C 1  and C 2  to be constant by means of the bias potentials PB and NB, when the node ND 4  changes from low level to high level, a transistor NM 1  turns OFF, so the drain potential of a transistor NM 2  becomes the ground potential GND. Since a parasitic capacitance is present at the drain of the transistor NM 2 , when the node ND 4  changes from high level to low level, the discharging current for the node ND 4  does not become exactly the same as the current set by the bias potential NB. An extra electrical charge equivalent to the parasitic capacitance at the drain of the transistor NM 2  being charged from the ground potential GND to a given potential is discharged from the node ND 4 . Likewise, the parasitic capacitance at the drain of a transistor PM 1  also becomes the cause of an error in the setting of current. 
     On the other hand, in the circuit illustrated in  FIG. 3 , if the speed of the change in the output of each of the transistors PM 4  and NM 4  is sufficiently high, the charging current for the parasitic capacitance at the source (node connected to each of the transistors PM 4  and NM 4 ) of each of the transistors PM 5  and NM 5  is not supplied to the node ND 4 . By adopting the circuit configuration illustrated in  FIG. 3  in this way, the accuracy of setting of current by the bias potentials PB and NB may be improved. 
     As illustrated in  FIG. 3 , an element that restricts current supplied to a load serves as a CMOS transfer gate (transistors PM 5  and NM 5 ). For example, even in the state when the transistor PM 4  is ON and the transistor NM 4  is OFF, not only does the transistor PM 5  supply current to the node ND 4 , but depending on the potential of the node ND 4 , there is a possibility that the transistor NM 5  also turns ON. 
     The circuit illustrated in  FIG. 3  is configured so that when charging the node ND 4 , current is supplied from only the transistor PM 5 . By driving the node ND 5  at the constant potential VR 18 , the signal amplitude of the node ND 4  becomes constant independent of the power source potential Vdd. By setting C 2 :C 1  as 2:1, for example, the signal amplitude of the node ND 4  may be set to approximately ⅔ of the potential VR 18 . By making the signal amplitude of the node ND 4  small, the withstand voltage of the inverter IV 1  may be made low. 
     While the potentials Vdd and VR 18  are both constant at 1.8 V, as will be described later with reference to  FIG. 4 , the power supply potential supplied to the elements PM 4 , NM 4 , IV 1 , IV 5 , IV 4 , and the like is set to the potential Vdd, and only the power supply potential supplied to the transistors PM 6  and NM 6  is set as the potential VR 18 . 
     The reason for using separate power supply potentials in this way is to minimize fluctuation of the potential VR 18  caused by voltage fluctuation due to power supply current of the inverters IV 1 , IV 5 , and IV 4 , and the like. The intention is to suppress fluctuation of the potential VR 18  as much as possible by using separate wires for the potentials VR 18  and Vdd as illustrated in  FIG. 5 . 
     Supposing that the ratio between the capacitors C 1  and C 2  is 1:1, when the logic threshold of the inverter IV 1  is 0.9 V, as the node ND 1  changes from low level to high level, the potential of the node ND 5  changes from 1.8 V to 0V. The potential of the node ND 4  changes from 0.9 V to 0 V. The node ND 4  is charged at constant current in the range of 0 V to 0.9 V, and when the potential of the node ND 4  exceeds 0.9 V, and the potential of the node ND 1  changes from high level to low level, the potential of the node ND 4  changes from 0.9 V to 1.8 V. The node ND 4  is discharged at constant current from 1.8 V to 0.9 V, resulting in the waveform as illustrated in  FIG. 4 . Fluctuation of oscillation frequency may be thus prevented. 
     By setting the capacitors C 2 :C 1  not to 1:1 but, for example, 2:1, the low level of the node ND 4  may be set to a potential higher than 0 V. Also, the high level of the node ND 4  may be set to a potential lower than 1.8 V. Thus, the inverter IV 1  with a low withstand voltage may be used. 
     The bias potentials PB and NB in  FIG. 3  are each set to such a potential that a predetermined current flows when the source potential of each of the transistors PM 5  and NM 5  is substantially the power supply potential (1.8 V or 0 V). When the node ND 4  is charged, the potential of the node ND 4  may be made higher than 0 V. This allows a design such that when charging the node ND 4  by the transistor PM 5 , the transistor NM 5  remains OFF, thereby preventing the transistor NM 5  from affecting the charging current. 
     When discharging the node ND 4 , the transistor NM 4  turns ON, and discharges the node ND 4  at a current set by the transistor NM 5 . By designing the relationship between the capacitors C 1  and C 2  such that the high level of the node ND 4  is a potential lower than the power supply potential Vdd, the transistor PM 5  may be designed so as to remain OFF when discharging the node ND 4  by the transistor NM 5 . 
     The transfer gate including the P-channel transistor PM 5  and the N-channel transistor NM 5  outputs a signal at the input terminal from the output terminal in accordance with the gate voltage of each of the P-channel transistor PM 5  and the N-channel transistor NM 5 . The inverter IV 1  takes a signal from the output terminal of the transfer gate PM 5 , NM 5  as input, and outputs the logically inverted signal of the inputted signal. The inverter including the transistors PM 6  and NM 6  takes a signal from the output terminal of the inverter IV 1  as input, and outputs the logically inverted signal of the inputted signal. The inverter including the transistors PM 4  and NM 4  takes the logically inverted signal of the output signal of the inverter IV 1  as input, and outputs the logically inverted signal of the inputted signal to the input terminal of the transfer gate PM 5 , NM 5 . The capacitor C 1  is connected between the output terminal of the transfer gate PM 5 , NM 5  and the output terminal of the inverter PM 6 , NM 6 . The capacitor C 2  is connected between the output terminal of the transfer gate PM 5 , NM 5  and the reference potential node. The inverter IV 4  is connected to a power supply potential wire Vdd different from a power supply potential wire VR 18  for the inverter PM 6 , NM 6 . The inverter IV 4  takes a signal at the output terminal of the inverter IV 1  as input, and outputs the logically inverted signal of the inputted signal to the input terminal of the inverter PM 4 , NM 4 . As described above, the circuit illustrated in  FIG. 3  makes it possible to improve the accuracy of setting of charging/discharging current. 
       FIG. 5  is a diagram illustrating an example of the configuration of a micro-controller (oscillating apparatus) mounted with the CR oscillating circuit illustrated in  FIG. 3 . A CR oscillating circuit OSC 1  has the CR oscillating circuit illustrated in  FIG. 3 , and its details will be described later with reference to  FIG. 8 . MCU 1  denotes a micro-controller (oscillating apparatus) mounted with the CR oscillating circuit OSC 1 , VDP 5  denotes a positive power supply potential (for example, 5 V), Vdd denotes a positive power supply potential (for example, 1.8 V) generated by a regulator REG 1 , and GND denotes a reference potential (ground potential: 0 V). 
     BGR 1  denotes a band gap circuit, REG 1  denotes a regulator including an error amplifier EAMP 1 , an output transistor PMO 1 , and voltage divider resistors RR 1  and RR 2 , LVDH 1  denotes a low voltage detection circuit for monitoring the power supply potential VDP 5  of 5 V, and LVDL 1  denotes a low voltage detection circuit for monitoring the power supply potential Vdd of 1.8 V. OSC 1  denotes a CR oscillating circuit (for example, the circuit illustrated in  FIG. 3 ), LOGIC 1  denotes a logic circuit that operates at internal potential Vdd, EAMP 1  denotes an error amplifier of the regulator REG 1 , and PMO 1  denotes an output P-channel MOS transistor of the regulator REG 1 . RR 1  and RR 2  each denote a voltage divider resistor that divides the power supply potential Vdd, VDIV 1  denotes a voltage divided by the resistors RR 1  and RR 2 , RL 1  and RL 2  each denote a resistor that divides the power supply potential VDP 5 , and VDIV 2  denotes a voltage divided by the resistors RL 1  and RL 2 . LVDHOX 1  denotes the output voltage of the low voltage detection circuit LVDH 1 , RL 3  and RL 4  each denote a resistor that divides the power supply potential Vdd, VDIV 3  denotes a voltage divided by the resistors RL 3  and RL 4 , and LVDLOX 1  denotes the output voltage of the low voltage detection circuit LVDL 1 . VBGR denotes the output band gap voltage of the band gap circuit BGR 1 , CO 1  denotes a capacitor that stabilizes the power supply potential Vdd, CMP 1  and CMP 2  each denote a comparator circuit, CLK 1  denotes the output clock signal of the CR oscillating circuit OSC 1 , and VR 18  denotes the power supply potential of the CR oscillating circuit OSC 1 . The power supply potential Vdd of the CR oscillating circuit OSC 1  corresponds to the power supply potential Vdd illustrated in  FIG. 3 . In  FIG. 5 , elements having the same functions as those in the circuit illustrated in  FIG. 3 , and the corresponding nodes are assigned the same symbols to indicate their correspondence. 
     In the micro-controller MCU 1 , the power supply potential VDP 5  supplied from the outside is maintained at, for example, 5 V, and the internal potentials Vdd and VR 18  determined by the withstand voltages of internal transistors are generated by the built-in regulator REG 1 .  FIG. 5  illustrates an example in which the external power supply potential VDP 5  is 5 V, and the potentials Vdd and VR 18  generated by the built-in regulator REG 1  are 1.8 V. 
     In order to supply a constant potential Vdd of 1.8 V even when the power supply potential VDP 5  fluctuates, a reference voltage VBGR is generated by the band bap circuit BGR 1 . On the basis of the reference voltage VBGR, the regulator REG 1  generates the potentials Vdd and VR 18  of 1.8 V, and supplies the potentials to the internal circuits LVDL 1 , OSC 1 , and LOGIC 1 . The low voltage detection circuit LVDH 1  monitors the power supply potential VDP 5 , and when the power supply potential VDP 5  becomes lower than a predetermined potential, sets the output voltage LVDHOX 1  to low level. The low voltage detection circuit LVDL 1  monitors the power supply potential Vdd, and when the power supply potential Vdd becomes lower than a predetermined potential, sets the output voltage LVDLOX 1  to low level. 
     The logic circuit LOGIC 1  operates at the power supply potential Vdd, and is supplied with the clock signal CLK 1  from the CR oscillating circuit OSC 1 . The CR oscillating circuit OSC 1  determines a bias current on the basis of the output potential Vdd of the regulator REG 1  and, for example, the band gap voltage VBGR, and generates the clock signal CLK 1 . 
     It is desirable for the regulator REG 1 , the low voltage detection circuits LVDH 1  and LVDL 1 , and the CR oscillating circuit OSC 1  mounted to the micro-controller MCU 1  to use a band gap circuit or a circuit similar to a band gap circuit in order to generate a reference potential or reference current. In such a case, as illustrated in  FIG. 5 , by employing a circuit configuration in which functions that may be made common is implemented as a common band gap circuit BGR 1  in advance, and lacking functions are added on the basis of this, overlapping functions need not be provided as separate circuits. This enables a reduction in effective circuit area. 
     Next, operation of each of the circuits illustrated in  FIG. 5  will be briefly described. The description given below assumes that the band gap voltage VBGR is 1.2 V. The regulator REG 1  generates the power supply potential Vdd of 1.8 V from the voltage VBGR of 1.2 V. The error amplifier EAMP 1  and the transistor PMO 1  form a negative feedback circuit, and the power supply potential Vdd is determined so as to make the band gap voltage VBGR and the voltage VDIV 1  coincide with each other. For example, if the resistors RR 1  and RR 2  are designed so that the ratio between their resistances is 1:2, when the power supply potential Vdd is 1.8 V, the divided voltage VDIV 1  is 1.2 V, so the power supply potential Vdd may be set to 1.8 V on the basis of the band gap voltage VBGR. The capacitor CO 1  functions as a stabilizing capacitor for suppressing fluctuation of the power supply potential Vdd when the load current fluctuates abruptly. 
     The low voltage detection circuit LVDH 1  functions as a circuit for detecting a drop in the power supply potential VDP 5  when, for example, the power supply potential VDP 5  becomes lower than 2.4 V. By setting the ratio between the resistances of the resistors RL 1  and RL 2  to 1:1 in advance, when the power supply potential VDP 5  becomes lower than 2.4 V, the voltage VDIV 2  becomes lower than the band gap voltage VBGR. By detecting this by the comparator circuit CMP 1 , for example, the output voltage LVDHOX 1  may be set to low level. As described above, when the band gap circuit BGR 1  used by the regulator REG 1 , and the band gap circuit BGR 1  used by the low voltage detection circuit LVDH 1  are made common, this means that the circuits that need to be added to implement the low voltage detection circuit function are, for example, only the resistors RL 1  and RL 2  and the comparator circuit CMP 1 , thereby enabling a reduction in effective circuit area. 
     The low voltage detection circuit LVDL 1  functions as a circuit for detecting a drop in the power supply potential Vdd when, for example, the power supply potential Vdd becomes lower than 1.4 V. By setting the ratio between the resistances of the resistors RL 3  and RL 4  to 1:6 in advance, when the power supply potential Vdd becomes lower than 1.4 V, the voltage VDIV 3  becomes lower than the band gap voltage VBGR. By detecting this by the comparator circuit CMP 2 , for example, the output voltage LVDLOX 1  may be set to low level. When the band gap circuit BGR 1  used by the regulator REG 1  and the low voltage detection circuit LVDH 1 , and the band gap circuit BGR 1  used by the low voltage detection circuit LVDL 1  are made common, this means that the circuits that need to be added to implement the low voltage detection circuit function for the power supply potential Vdd are, for example, only the resistors RL 3  and RL 4  and the comparator circuit CMP 2 , thereby enabling a reduction in effective circuit area. 
     As in the case of the lower voltage detection circuits LVDH 1  and LVDL 1 , for the CR oscillating circuit OSC 1  as well, circuit function portions that are common to those of the regulator REG 1  or the like are shared, thereby enabling a reduction in effective area in the case when the CR oscillating circuit OSC 1  and the regulator REG 1  are mounted. 
       FIG. 5  illustrates a case in which the bias current for the CR oscillating circuit OSC 1  is generated on the basis of the band gap voltage VBGR. Details of the circuit will be described later with reference to other drawings. 
       FIG. 6  is a circuit diagram illustrating an example of the configuration of the band gap circuit BGR 1  illustrated in  FIG. 5 . NMBn (n is an integer) denotes an N-channel MOS transistor, PMBn (n is an integer) denotes a P-channel MOS transistor, VDP 5  denotes a positive power supply potential (for example, 5 V), and GND denotes a reference potential (ground potential: 0 V). CB 1  denotes a capacitor, RB 1 , RB 2 , RB 3 , and RB 4  each denote a resistor, Q 1  and Q 2  each denote a PNP transistor, BPB denotes a bias potential, IBLVDH denotes a bias current supplied to the low voltage detection circuit LVDH 1  illustrated in  FIG. 5 , IBLVDL denotes a bias current supplied to the low voltage detection circuit LVDL 1  illustrated in  FIG. 5 , and IBOSC denotes a bias current supplied to the CR oscillating circuit OSC 1  illustrated in  FIG. 5 . VBE 1  denotes the emitter potential of the transistor Q 1 , VBE 2  denotes the emitter potential of the transistor Q 2 , IP and IM each denote a node given for the purpose of explanation, and VGBR denotes an output band gap voltage. The emitter potential VBE 1  is used in circuits illustrated in  FIGS. 8 ,  10 ,  14 , and  15  described later. 
     In  FIG. 6 , nodes corresponding to those in the circuits illustrated in  FIGS. 3 and 5  are assigned the same symbols to indicate their correspondence. It is supposed that the numbers indicating multiplication factors attached to the transistors Q 1  and Q 2  in  FIG. 6  indicate the relationship between the relative sizes of the respective transistors Q 1  and Q 2 . In the following, likewise, it is supposed that the numbers indicating multiplication factors attached to PNP transistors indicate the relationship between the relative sizes of the respective transistors. 
     Since the power supply potential VDP 5  applied to the transistors PMB 1  to PMB 9  and the transistors NMB 1  to NMB 5  is 5 V, the withstand voltage of these transistors needs to be 5 V or more. Although these transistors are different from the transistors for the internal power supply potentials Vdd and VR 18  (1.8 V) used in the circuit illustrated in  FIG. 3  in gate length and gate oxide film thickness, for the sake of brevity, and because the correspondence is apparent from the power supply potential, the circuit is expressed using the same transistor symbols as the transistor symbols used in the circuit illustrated in  FIG. 3 . In the description that follows, unless otherwise specified, it is supposed that transistors corresponding to the power supply potential are used. 
     A circuit formed by the transistors PMB 1 , PMB 2 , NMB 1 , and NMB 2 , and the resistor RB 1  generates a bias current. Since the circuit in this portion is a general one, its detailed description is omitted. Also, for the simplicity of the drawing, elements such as a start-up circuit and a power-down element are not illustrated. By designing the transistors NMB 1  and NMB 2  to which the same gate voltage is applied in such a way that the size (gate width) of the transistor NMB 2  is large relative to that of the transistor NMB 1 , the bias current may be designed on the basis of the difference in gate voltage for flowing the same current, and the resistor RB 1 . The bias potential BPB is determined as a potential at which this bias current flows. 
     The transistors PMB 5 , PMB 6 , PMB 3 , NMB 3 , NMB 4 , NMB 5 , and PMB 4  function as an operational amplifier circuit for by performing feedback control so as to make the potential of the node IP and the potential of the node IM coincide with each other, thereby generating the bang gap voltage VBGR. The transistor PMB 3  functions as a current source for the operational amplifier circuit. The operational amplifier formed by the transistors PMB 5 , PMB 6 , PMB 3 , NMB 3 , NMB 4 , NMB 5 , and PMB 4  itself is configured as a general two-stage operational amplifier circuit. The capacitor CB 1  functions as a phase compensation capacitor for the operational amplifier. 
     When the potentials of the nodes IP and IM coincide with each other, equal potential differences are applied to the resistors RB 2  and RB 3 , so currents determined by the ratio between the resistors RB 2  and RB 3  flow through the transistors Q 1  and Q 2 . Since the ratio between the emitter sizes of the transistors Q 1  and Q 2  is designed to be, for example, 1:10, in accordance with the ratio between the resistors RB 2  and RB 3 , the current densities of the transistors Q 1  and Q 2  are determined. In accordance with the ratio between the current densities, the difference between the respective emitter potentials VBE 1  and VBE 2  of the transistors Q 1  and Q 2  is determined. The difference between the emitter potentials VBE 1  and VBE 2  is applied to the resistor RB 4 , and currents flowing through the transistors Q 1  and Q 2  are determined. The emitter potential VBE 1  exhibits a negative dependence on absolute temperature, and the currents flowing through the transistors Q 1  and Q 2  are positively proportional to absolute temperature. Herein below, CTAT denotes a negative dependence on absolute temperature, and PTAT denotes a positive dependence on absolute temperature. 
     By selecting the values of the resistors RB 2  and RB 3  in such a way that the band gap voltage VBGR is approximately 1.2 V, the band gap voltage VBGR becomes constant independent of temperature. The transistors PMB 7 , PMB 8 , and PMB 9  are provided so that simultaneously with generating the bias potential BPB by the bias circuit in order to determine the current of the current source for the band gap circuit BGR 1 , the bias potential BPB may be also used as the bias current for the low voltage detection circuits LVDH 1  and LVDL 1 , and the CR oscillating circuit OSC 1 . This eliminates the redundant need to provide a bias circuit formed by the transistors PMB 1 , PMB 2 , NMB 1 , and NMB 2 , and the resistor RB 1  in each of the low voltage detection circuits LVDH 1  and LVDL 1 , the CR oscillating circuit OSC 1 , and the like. 
     Also, as will be described later, when not only the band gap voltage VBGR but also the emitter potential VBE 1  of the transistor Q 1  is supplied to the CR oscillating circuit OSC 1  in advance, this is convenient in generating a reference current for the CR oscillating circuit OSC 1 . 
     The band gap circuit BGR 1  has the PNP transistor Q 1  whose base and collector are each connected to the reference potential node, the PNP transistor Q 2  whose base and collector are each connected to the reference potential node, and the resistor RB 4  whose one end is connected to the emitter of the PNP transistor Q 2 . The band gap circuit BGR 1  generates the band gap voltage VBGR by controlling the potential IM at the other end of the resistor RB 4  and the emitter potential VBE 1  of the PNP transistor Q 1  so as to be equal. 
       FIG. 7  is a block diagram illustrating an example of the configuration of the CR oscillating circuit OSC 1  illustrated in  FIG. 5 . IREF 1  denotes a reference current generation circuit of the CR oscillating circuit OSC 1 , IDAC 1  denotes a trimming current digital/analog conversion (DAC) circuit for regulating oscillation frequency, OSCCORE 1  denotes the oscillating circuit main body of the CR oscillating circuit OSC 1 , TCA [3:0] denotes, for example, a 4-bit signal for regulating the temperature dependence of frequency, and TRD [7:0] denotes, for example, an 8-bit signal for regulating oscillation frequency. IBIAS and IBIASTRIM each denote a reference current generated by the reference current generation circuit IREF 1 , IBIASROSC denotes a bias current for the CR oscillating circuit main body OSCCORE 1  supplied from the trimming current DAC circuit IDAC 1 , and CLK 1  denotes the output clock signal of the CR oscillating circuit OSC 1 . 
     The reference current generation circuit IREF 1  generates the reference currents IBIAS and IBIASTRIM on the basis of the band gap voltage VBGR, the emitter potential VBE 1 , and the like illustrated in  FIG. 6 . The trimming current DAC circuit IDAC 1  supplies the bias current IBIASROSC to the CR oscillating circuit main body OSCCORE 1  on the basis of the reference currents IBIAS and IBIASTRIM. The CR oscillating circuit main body OSCCORE 1  is configured like, for example, the CR oscillating circuit illustrated in  FIG. 3 . In  FIG. 7 , nodes corresponding to those in the circuits illustrated in  FIGS. 3 and 5  are assigned the same symbols to indicate their correspondence. 
     The temperature-dependence regulation signal TCA [3:0] functions as a signal for regulating the temperature dependence of the reference currents IBIAS and IBIASTRIM. The frequency regulation signal TRD [7:0] functions as a signal for regulating the absolute value of the bias current IBIASROSC in order to regulate the absolute value of frequency. 
       FIG. 8  is a circuit diagram illustrating an example of the configuration of the reference current generation circuit IREF 1  illustrated in  FIG. 7 . PMRn (n is an integer) denotes a P-channel MOS transistor, AMP 1  and AMP 2  each denote an amplifier circuit (operational amplifier), RR 1  denotes a resistor, RR 2  denotes a variable resistor, and Q 3  denotes a PNP transistor. BPTAT 1  denotes a PTAT current generation circuit, BCTAT 1  denotes a CTAT current generation circuit, VBGR generates a band gap voltage generated by the band gap circuit BGR 1  illustrated in  FIG. 6 , and PGO is a bias voltage generated by the PTAT current generation circuit BPTAT 1 . IPTAT 1  denotes a current flowing through the transistor Q 3 , RVBE 3  denotes a node within the PTAT current generation circuit BPTAT 1 , VBE 1  denotes a potential VBE 1  generated by the band gap circuit BGR 1  illustrated in  FIG. 6 , and PGO 2  denotes a bias voltage generated by the CTAT current generation circuit BCTAT 1 . ICTAT 1  denotes a current flowing through the variable resistor RR 2 , VFB denotes a node within the CTAT current generation circuit BCTAT 1 , IBIAS and IBIASTRIM respectively denote the currents IBIAS and IBIASTRIM illustrated in  FIG. 7 , VR 18  denotes a positive power supply potential (for example, 1.8 V) generated by the regulator REG 1  illustrated in  FIG. 5 , and GND denotes a reference potential (ground potential: 0 V). 
     In  FIG. 8 , nodes or elements corresponding to those in the circuits illustrated in  FIGS. 3 ,  5 , and  6  are assigned the same symbols to indicate their correspondence. It is supposed that the number indicating a multiplication factor attached to the transistor Q 3  in  FIG. 8  indicates the relationship between the relative sizes of the transistors Q 1 , Q 2 , and Q 3 . 
     Since the band gap circuit BGR 1  and the regulator REG 1  illustrated in  FIG. 5  are each a circuit that generates the power supply potential Vdd of 1.8 V from the power supply potential VDP 5  of 5 V, its power supply potential may be the potential VDP 5 . On the other hand, since the CR oscillating circuit OSC 1  is a circuit for supplying the clock signal CLK 1  to the logic circuit LOGIC 1  that operates at the power supply potential Vdd, its power supply potential may be the potential Vdd. When the potential Vdd is taken as the power supply potential, since the potential Vdd is a potential generated by the regulator REG 1 , there is an advantage in that the range of fluctuation of the power supply potential Vdd is small. In portions where current is constant, it is advantageous from the viewpoint of noise to perform wiring in such a way as to minimize the influence of the power supply potential of the logic circuit LOGIC 1 . Thus, in FIG.  8 , the potential VR 18  is used as the power supply potential in the sense that the power supply potential may be wired separately from the potential Vdd. 
     As is apparent from the configuration illustrated in  FIG. 3 , the signal amplitude of the CR oscillating circuit main body OSCCORE 1  illustrated in  FIGS. 3 and 7  is kept substantially constant independent of temperature by the regulator REG 1  ( FIG. 5 ). To keep oscillation frequency constant, it is necessary to keep the charging/discharging current for the capacitance of the CR oscillating circuit main body OSCCORE 1  constant irrespective of temperature and the power supply potential VDP 5 . For this purpose, a constant current that is independent of temperature is generated by the circuit illustrated in  FIG. 8 . 
     The principle for generating a constant current that is independent of temperature is substantially the same as that for the band gap circuit BGR 1 . The current IPTAT 1  that is positively proportional to absolute temperature and the current ICTAT 1  that has a negative dependence on absolute temperature are summed to generate each of the currents IBIAS and IBIASTRIM that are substantially independent of temperature. 
     The PTAT current generation circuit BPTAT 1  generates the current IPTAT 1  that is positively proportional to absolute temperature, and the CTAT current generation circuit BCTAT 1  generates the current ICTAT 1  that has a negative dependence on absolute temperature. A current that is positively proportional to absolute temperature flows through each of transistors PMR 2  and PMR 3  whose gate voltage PGO is the same as that of a transistor PMR 1 . A current that has a negative dependence on absolute temperature flows through each of transistors PMR 5  and PMR 6  whose gate voltage PGO 2  is the same as that of a transistor PMR 4 . Since the currents IBIAS and IBIASTRIM are each the sum of the current in the transistor PMR 2 , PMR 3  and the current in the transistor PMR 5 , PMR 6 , the reference currents IBIAS and IBIASTRIM become independent of temperature. 
     Next, the principle for generating the current PTAT 1  that is positively proportional to absolute temperature by the PTAT current generation circuit BPTAT 1  will be described. A forward voltage VBE 3  on the PNP transistor Q 3  exhibits a substantially negative proportionality to absolute temperature. For example, the forward voltage VBE 3  may be approximated by such a straight line that the voltage exhibits a value of about 1.2 V at absolute zero, and about 600 mV in the vicinity of room temperature. The band gap voltage VBGR generated by the band gap circuit BGR 1  illustrated in  FIG. 6  becomes a constant value at about 1.2 V independent of temperature. By performing feedback control by the amplifier circuit AMP 1  so that the band gap voltage VBGR and the voltage of the node RVBE 3  coincide with each other, the voltage of the node RVBE 3  becomes the same as the band gap voltage VBGR, and is constant at about 1.2 V independent of temperature. Incidentally, since the voltage VBE 3  exhibits a substantially negative proportionality to absolute temperature, the voltage applied to the resistor RR 1  is positively proportional to absolute temperature. Since the voltage applied to the resistor RR 1  is proportional to absolute temperature, the current IPTAT 1  flowing through the resistor RR 1  becomes proportional to absolute temperature. Since the current flowing through the transistor PMR 1  is the current IPTAT 1 , like the current IPTAT 1 , the current flowing through each of the transistors PMR 1 , PMR 2 , and PMR 3  whose gate voltage is the voltage PGO is also proportional to absolute temperature. 
     On the other hand, like the voltage VBE 3 , the potential VBE 1  supplied from the band gap circuit BGR 1  illustrated in  FIG. 6  exhibits a substantially negative proportionality to absolute temperature. By performing feedback control by the amplifier circuit AMP 2  so that the potential VBE 1  and the potential of the node VFB coincide with each other, the potential of the node VFB becomes the same as the potential VBE 1 , and exhibits a substantially negative proportionality to absolute temperature. The potential applied to the variable resistor RR 2  exhibits a substantially negative proportionality to absolute temperature. Since the voltage applied to the variable resistor RR 2  exhibits a negative proportionality to absolute temperature, the current ICTAT 1  flowing through the variable resistor RR 2  becomes negatively proportional to absolute temperature. Since the current flowing through the transistor PMR 4  is the current ICTAT 1 , like the current ICTAT 1 , the current flowing through each of the transistors PMR 4 , PMR 5 , and PMR 6  whose gate voltage is the voltage PGO 2  is also negatively proportional to absolute temperature. The resistor RR 2  is formed as a variable transistor in order to make the value of the current ICTAT 1  variable. The circuit of this portion will be described later in further detail. 
     The reference currents IBIAS and IBIASTRIM may be made independent of temperature by summing the currents flowing through the transistors PMR 2  and PMR 5 , and the currents flowing through the transistors PMR 3  and PMR 6 , respectively, at an appropriate ratio. By generating the reference currents IBIAS and IBIASTRIM that are independent of temperature in the circuit illustrated in  FIG. 8 , the number of PNP transistors may be advantageously reduced. 
     For example, in the band gap circuit BGR 1  illustrated in  FIG. 6 , by using the transistors Q 1  and Q 2  of different sizes, these transistors are biased at different current densities, and the difference between their forward voltages is used in order to generate a PTAT current. For this reason, a PNP transistor with a size equivalent to 11 times the size of the transistor Q 1  is used. On the other hand, in the circuit illustrated in  FIG. 8 , by keeping the potential of the resistor RR 1  connected in series with the transistor Q 3  constant irrespective of temperature, the PTAT current IPTAT 1  is generated by a single transistor Q 3  (a single PNP transistor) whose size is 1 time as large. That is, the use of the band gap voltage VBGR significantly reduces the area of PNP transistor necessary for generating the PTAT current IPTAT 1 . 
     The reference current generation circuit IREF 1  has a positive dependence (PTAT) current generation circuit BPTAT 1  that generates the positive dependence current IPTAT 1  having a positive dependence on absolute temperature, and a negative dependence (CTAT) current generation circuit BCTAT 1  that generates the negative dependence current ICTAT 1  having a negative dependence on absolute temperature. The reference current generation circuit IREF 1  generates each of the reference current IBIAS and IBIASTRIM by summing the positive dependence current IPTAT 1  and the negative dependence current ICTAT 1 . A voltage corresponding to each of the reference currents IBIAS and IBIASTRIM is applied to each of the gates of the P-channel transistor PM 5  and the N-channel transistor NM 5 . 
     The positive dependence current generation circuit BPTAT 1  has the PNP transistor Q 3  whose collector and base are each connected to the reference potential node, and the resistor RR 1  whose one end is connected to the emitter of the PNP transistor Q 3 , and a first control circuit that controls the positive dependence current IPTAT 1  flowing through the resistor RR 1  in such a way that the potential of the node RVBE 3  at the other end of the resistor RR 1  and a first potential (band gap voltage) VBGR become equal to each other. The first control circuit has the amplifier circuit AMP 1  and the transistor PMR 1 . The amplifier circuit AMP 1  takes the band gap voltage VBGR of the band gap circuit BGR 1  illustrated in  FIG. 6  as input. 
     The negative dependence current generation circuit BCTAT 1  has the resistor RR 2  whose one end is connected to the reference potential node, and a second control circuit that controls the negative dependence current ICTAT 1  flowing through the resistor RR 2  in such a way that the potential of the node VFB at the other end of the resistor RR 2  and a second potential VBE 1  become equal to each other. The second control circuit has the amplifier circuit AMP 2  and the transistor PMR 4 . The amplifier circuit AMP 2  takes the emitter potential VBE 1  of the PNP transistor Q 1  of the band gap circuit BGR 1  illustrated in  FIG. 6  as input. 
     As described above, by using the reference current generation circuit IREF 1  illustrated in  FIG. 8 , the element area may be advantageously reduced. 
       FIG. 9  is a circuit diagram illustrating an example of the configuration of the variable resistor RR 2  illustrated in  FIG. 8 . NMVn (n is an integer) denotes an N-channel MOS transistor, RVn (n is an integer) denotes a resistor, VFB denotes the node VFB illustrated in  FIG. 8 , and GND denotes a reference potential (ground potential: 0 V). 
     In  FIG. 9 , nodes or elements corresponding to those in the circuit illustrated in  FIG. 8  are assigned the same symbols to indicate their correspondence. The numbers from 0000 to 1110 attached to the respective gates of transistors NMV 1  to NMV 15  indicate an example of combination of the values of a 4-bit regulation signal TCA [3.0] with which the corresponding gates become high level, in the case when the variable resistor RP 2  in  FIG. 9  is controlled by the 4-bit regulation signal TCA [3:0] ( FIG. 7 ). By means of the 4-bit regulation signal TCA [3:0], it is possible to select 16 different temperature dependences of reference current. To regulate the temperature dependence of reference current, the value of the current ICTAT 1  is changed. To change the value of the current ICTAT 1 , the resistance of the variable resistor RR 2  is changed. In the circuit illustrated in  FIG. 9 , the value of the variable resistor RR 2  may be changed in accordance with the temperature dependence regulation signal TCA [3:0]. 
     When the regulation signal TCA [3:0] is 0000, the transistor NMV 1  turns ON, and the resistance (the value of the resistor RR 2 ) between the node VFB and the node of the reference potential GND becomes the value of a resistor RV 1 . When the regulation signal TCA [3:0] is 1111, the transistors NMV 1  to NMV 15  all turn OFF, and the value of the variable resistor RR 2  becomes the sum of the values of resistors RV 1  to RV 16 . When the regulation signal TCA [3:0] is 0011, the transistors NMV 1  to NMV 3  turn OFF, and the transistor NMV 4  turns OFF. The value of the variable resistor RR 2  becomes the sum of the resistors RV 1  to RV 4 . 
     In this way, the circuit illustrated in  FIG. 9  may be used as the variable resistor RR 2  illustrated in  FIG. 8 . By making the resistance of the variable resistor RR 2  variable, it is possible to change the temperature dependence of the reference currents IBIAS and IBIASTRIM by, for example, the regulation signal TCA [3:0] illustrated in  FIG. 7 . Since the reference currents IBIAS and IBIASTRIM are each generated by the sum of the currents IPTAT 1  and ICTAT 1 , by changing the value of the variable resistor RR 2 , the temperature dependence of the reference currents IBIAS and IBIASTRIM may be changed. 
     The reference current generation circuit IREF 1  generates each of the reference currents IBIAS and IBIASTRIM by summing the positive dependence current IPTAT 1  and the negative dependence current ICTAT 1  while changing their summation ratio in accordance with the temperature dependence regulation signal TCA [3:0]. The resistor RR 2  is a variable resistor whose resistance varies in accordance with the temperature dependence regulation signal TCA [3:0]. 
     An error is present in the actual output potential VBGR of the reference voltage generation circuit generated in  FIG. 6 . This error also causes the temperature dependence of the band gap voltage VBGR to become slightly positive or negative depending on each individual circuit manufactured. For this reason, the values of the potentials Vdd and VR 18  generated by the regulator REG 1  illustrated in  FIG. 5  also become slightly positive or negative depending on each individual circuit manufactured. 
     For this reason, even if the reference currents IBIAS and IBIASTRIM generated by the circuit illustrated in  FIG. 8  are perfectly ideal, the temperature dependence of oscillation frequency differs slightly for each individual circuit. Further, the temperature dependence of the reference currents IBIAS and IBIASTRIM generated by the circuit illustrated in  FIG. 8  itself also differs for each individual circuit. For this reason, to attain a desirable temperature dependence of oscillation frequency, it is necessary to regulate the temperature dependence for each individual circuit. By configuring the variable resistor RR 2  of the reference current generation circuit in  FIG. 8  as illustrated in  FIG. 9 , the temperature dependence of the reference currents IBIAS and IBIASTRIM in  FIG. 8  may be made electrically variable. 
     Thus, it is possible to regulate the temperature dependence of oscillation frequency for each individual circuit, thereby enabling setting of frequency with higher accuracy. 
       FIG. 10  is a circuit diagram illustrating an example of the configuration of each of the amplifier circuits AMP 1  and AMP 2  illustrated in  FIG. 8  and of the circuit in its vicinity. PMRn (n is an integer) denotes a P-channel MOS transistor, NMRn (n is an integer) denotes an N-channel MOS transistor, RR 1  and RR 3  each denote a resistor, RR 2  denotes a variable resistor, and Q 3  denotes a PNP transistor. VBGR denotes a bang gap voltage generated by the band gap circuit BGR 1  illustrated in  FIG. 6 , PGO denotes a generated bias voltage, RVBE 3  denotes an internal node, and VBE 1  denotes a potential VBE 1  generated by the band gap circuit BGR 1  illustrated in  FIG. 6 . PGO 2  denotes a generated bias voltage, VFB denotes an internal node, VR 18  denotes a positive power supply voltage (for example, 1.8 V) generated by the regulator REG 1  illustrated in  FIG. 5 , and GND denotes a reference potential (ground potential: 0 V). IBOSC denotes a bias current IBOSC supplied from the band gap circuit BGR 1  illustrated in  FIG. 6 , OPB, ONCB, and ONB each denote a bias potential generated from the current IBOSC, and CR 1  denotes a capacitor. 
     In  FIG. 10 , nodes or elements corresponding to those in the circuits illustrated in  FIGS. 3 ,  5 ,  6 ,  8 , and the like are assigned the same symbols to indicate their correspondence. It is supposed that the number indicating a multiplication factor attached to the transistor Q 3  in  FIG. 10  indicates the relationship between the relative sizes of the transistors Q 1 , Q 2 , and Q 3 . It is supposed that  FIG. 10  represents an example of the transistor-level circuit of each of the amplifier circuits AMP 1  and AMP 2  illustrated in  FIG. 8 , although a part of the circuit such as the transistors PMR 2 , PMR 3 , and the like illustrated in  FIG. 8  is omitted. 
     Transistors PMR 7 , PMR 8 , NMR 2 , NMR 3 , and NMR 4  illustrated in  FIG. 10  function as the amplifier circuit AMP 1  illustrated in  FIG. 8 . Since this is a general differential circuit, description of the operation of this portion is omitted. The differential circuit according to this example is such that since the band gap voltage VBGR is 1.2 V, and the power supply potential VR 18  is 1.8 V, the N-channel MOS transistors NMR 2  and NMR 3  are input transistors. In this regard, it is possible to modify the differential circuit so that P-channel MOS transistors are input transistors if the reference potential VBGR is closer to the reference potential GND. 
     In order for the transistors PMR 7 , PMR 8 , NMR 2 , NMR 3 , and NMR 4  to operate, the gate voltage of the transistor NMR 4  may be so biased that a predetermined current flows. For this purpose, the bias current IBOSC is received from the band gap circuit BGR 1  illustrated in  FIG. 6 , and converted by the transistor NMR 1  into a gate voltage for the transistor NMR 4 . 
     This configuration eliminates the need to provide an independent bias circuit on the amplifier circuit AMP 1  side, thereby making it advantageously possible to save circuit area. 
     Transistors PMR 11  to PMR 15  and transistors NMR 8  to NMR 11  illustrated in  FIG. 10  function as the amplifier circuit AMP 2  illustrated in  FIG. 8 . The capacitor CR 1  functions as a phase compensation capacitor. Since the amplifier circuits AMP 1  and AMP 2  are both used as feedback circuits, phase compensation is performed. Since the amplifier circuit AMP 2  illustrated in  FIG. 10  is a general folded cascode circuit, description of the operation of this portion is omitted. A folded cascode circuit in which the P-channel MOS transistors PMR 12  and PMR 13  are input transistors is used because the potential VBE 1  is close to the reference potential GND. 
     Like the amplifier circuit AMP 1  illustrated in  FIG. 10 , the amplifier circuit AMP 2  illustrated in  FIG. 10  also needs to be supplied with a bias potential. For example, as illustrated in  FIG. 10 , it is possible to generate the potentials OPB, ONB, and ONCB on the basis of the current IBOSC, and by supplying the bias current IBOSC from the circuit illustrated in  FIG. 6 , circuit area may be reduced. The current IBOSC in  FIG. 6  is provided for this purpose, and it is needless to mention that the currents IBLVDH and IBLVDL in  FIG. 6  may be also used in the same manner. 
     Since the configuration of the portion of the circuit for generating the potentials OPB, ONB, and ONCB from the current IBOSC is also a general one, description of the operation of this portion is also omitted. 
     As described above, the amplifier circuits AMP 1  and AMP 2  may be implemented by the circuits as illustrated in  FIG. 10 , for example, and by supplying the bias current IBOSC from the circuit illustrated in  FIG. 6 , the number of elements for generating the bias current may be reduced. 
       FIG. 11  is a circuit diagram illustrating an example of the configuration of the trimming current DAC circuit IDAC 1  illustrated in  FIG. 7 . NMDPn (n is an integer), NMDASn (n is an integer), NMDAn (n is an integer), NMDA, NMDB, and NMDB 1  each denote an N-channel MOS transistor. IBIASTRIM denotes the current IBIASTRIM illustrated in  FIG. 8 , IBIAS denotes the current IBIAS illustrated in  FIG. 8 , PD 18  denotes a power-down signal, and IBIASROSC denotes the bias current IBIASROSC illustrated in  FIG. 3 . GND denotes a reference potential (ground potential: 0 V), IBIASTRIMLSB denotes a current corresponding to 1 LSB (least significant bit) of the current DAC circuit IDAC 1 , and IBIASOFFSET denotes a current for an offset serving as the minimum current of the output current IBIASROSC. In  FIG. 11 , nodes or elements corresponding to those in the circuits illustrated in  FIGS. 3 ,  5 ,  7 ,  8 , and the like are assigned the same symbols to indicate their correspondence. 
     The circuit illustrated in  FIG. 11  functions as a current DAC circuit for controlling the absolute value of the bias current IBIASROSC by the 8-bit signal TRD [7:0] as illustrated in  FIG. 7 . N-channel MOS transistors NMDAS 1  to NMDAS 256  indicate that, for example, 256 N-channel MOS transistors of the same size are provided. Likewise, N-channel MOS transistors NMDA 1  to NMDA 256  also indicate that 256 N-channel MOS transistors of the same size are provided. 
     The node of the current IBIASTRIM is connected to the node of the current IBIASTRIM illustrated in  FIG. 8 , and converts the bias current IBIASTRIM into a gate voltage by the transistor NMDA. This gate voltage is supplied to the transistors NMDA 1  to NMDA 256 , so the same current may be made to flow through the transistors NMDA 1  to NMDA 256 . The current IBIASTRIMLSB illustrated in  FIG. 11  denotes a current that flows per one transistor NMDAn (n is 1 to 256). By appropriately designing the sizes of the transistor NMDA and transistors NMDA 1  to NMDA 256 , the current IBIASTRIMLSB of a value may be obtained on the basis of the current IBIASTRIM. For example, the transistor NMDA and the transistors NMDA 1  to NMDA 256  are all in the same size, and the current IBIASTRIMLSB of 1 μA may be made to flow through each of the transistors. 
     The transistors NMDA 1  to NMDA 256  and the transistors NMDAS 1  to NMDAS 256  are respectively connected in series. By controlling the number of gates to be set to high level among the respective gates of the 256 transistors NMDAS 1  to NMDAS 256 , the value of the bias current IBIASROSC supplied to the CR oscillating circuit main body OSCCORE 1  illustrated in each of  FIG. 3  and  FIG. 7  may be controlled. Each of the numbers 1 to 256 attached to the respective gates of the transistors NMDAS 1  to NMDAS 256  means a control signal for the corresponding gate. Since 256 different bias currents IBIASROSC may be controlled by the 8-bit digital signal TRD [7:0] as illustrated in  FIG. 7 , for example, the value of the bias current IBIASROSC may be regulated by the current DAC circuit illustrated in  FIG. 11 . 
     The minimum value of the bias current IBIASROSC is, for example, one IBIASTRIMLSB+IBIASOFFSET in  FIG. 11 . This current may be designed so as to be the minimum current for frequency regulation of the CR oscillating circuit main body OSCCORE 1  illustrated in  FIG. 7 . The current IBIASOFFSET may be designed to an arbitrary value by appropriately designing the size ratio between the transistors NMDB and NMDB 1  on the basis of the current IBIAS in advance. Also, by setting the gate voltage PD 18  of each of transistors NMDP 1  and NMDP 2  to high level, the gate voltage of each N-channel MOS transistor becomes 0, thus achieving a power-down state. 
     The current digital/analog conversion (DAC) circuit IDAC 1  converts a digital signal TRD [7:0] into an analog bias current IBIASROSC by using the reference current IBIASTRIM. A voltage corresponding to the bias current IBIASROSC is applied to each of the gates of the P-channel transistor PM 5  and N-channel transistor NM 5  illustrated in  FIG. 3 . 
     As described above, a mechanism that makes the bias current IBIASROSC for frequency regulation variable may be implemented by the circuit as illustrated in  FIG. 11 , on the basis of the current IBIASTRIM generated by the reference current generation circuit IREF 1  illustrated in  FIG. 8 . 
       FIG. 12  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit IREF 1  illustrated in  FIG. 7 . PMRBn (n is an integer) denotes a P-channel MOS transistor, AMP 3  and AMP 4  each denote an amplifier circuit (operational amplifier), RR 4  denotes a resistor, RR 5  denotes a variable resistor, and Q 4  and Q 5  each denote a PNP transistor. BPTAT 2  denotes a PTAT current generation circuit, BCTAT 2  denotes a CTAT current generation circuit, PGO 3  denotes a bias potential generated by the PTAT current generation circuit BPTAT 2 , and IPTAT 2  denotes a current flowing through the transistor Q 5 . RVBE 5  and VBE 4  each denote a node within the PTAT current generation circuit BPTAT 2 , PGO 4  denotes a bias potential generated by the CTAT current generation circuit BCTAT 2 , and ICTAT 2  denotes a current flowing through the variable resistor RR 5 . VFB denotes a node within the CTAT current generation circuit BCTAT 2 , IBIAS and IBIASTRIM respectively denote the currents IBIAS and IBIASTRIM illustrated in  FIG. 7 , VR 18  denotes a positive power supply voltage (for example, 1.8 V) generated by the regulator REG 1  illustrated in  FIG. 5 , and GND denotes a reference potential (ground potential: 0 V). In  FIG. 12 , nodes or elements corresponding to those in  FIG. 8  and the like are assigned the same symbols to indicate their correspondence, and thus repetitive description is omitted. 
     Herein below, the difference between the circuit illustrated in  FIG. 12  and the circuit illustrated in  FIG. 8  will be described. In  FIG. 12  as well, the PTAT current IPTAT 2  is generated by the PTAT current generation circuit BPTAT 2 , and the CTAT current ICTAT 2  is generated by the CTAT current generation circuit BCTAT 2 . These currents IPTAT 2  and ICTAT 2  are summed to generate each of the currents IBIAS and IBIASTRIM. The circuit illustrated in  FIG. 12  is also the same as the circuit illustrated in  FIG. 8  in that by changing the resistance of the variable resistor RR 5 , the value of the CTAT current ICTAT 2  may be changed, thereby making it possible to regulate the temperature dependence of reference current. 
     In the circuit illustrated in  FIG. 8 , the band gap voltage VBGR and the potential VBE 1  are supplied from the band gap circuit BGR 1  illustrated in  FIG. 6 , and the PTAT current IPTAT 1  and the CTAT current ICTAT 1  are generated on the basis of these. By using the potentials VGBR and VBE 1  from the band gap circuit BGR 1 , the number of elements for generating a reference current is reduced. 
     On the other hand, in  FIG. 12 , the PTAT current IPTAT 2  and the CTAT current ICTAT 2  are generated only within the reference current generation circuit IREF 1  on the basis of the transistors Q 4  and Q 5 . Although the number of elements increases, the configuration as illustrated in  FIG. 12  is also possible. When arranging these circuits in a location far from the band gap circuit BGR 1  of the regulator REG 1 , it is also possible to adopt the reference current generation circuit IREF 1  as illustrated in  FIG. 12 . 
     The circuit illustrated in  FIG. 12  is the same as the band gap circuit BGR 1  illustrated in  FIG. 6  in that the PTAT current IPTAT 2  that is proportional to absolute temperature may be generated by controlling the potential of the node RVBE 5  and the potential of the node VBE 4  so as to coincide with each other, and appropriately designing the ratio between the current densities of the transistors Q 4  and Q 5 . The circuit illustrated in  FIG. 12  is also the same as the circuit illustrated in  FIG. 8  in that the CTAT current ICTAT 2  may be generated by generating current on the basis of the voltage of the node VBE 4  which is the forward voltage of the PNP transistor Q 4 . 
     When the circuit illustrated in  FIG. 12  is adopted, although the advantage of area reduction as in the case of the circuit illustrated in  FIG. 8  is not obtained, the advantages described with reference to  FIG. 7 , such as enabling regulation of the temperature dependence of reference current, and enabling regulation of oscillation frequency, may be obtained. 
       FIG. 13  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit IREF 1  illustrated in  FIG. 7 . Since the only difference between the circuit illustrated in  FIG. 13  and the circuit illustrated in  FIG. 8  is the negative input of the amplifier circuit AMP 2 , only the difference in this respect will be described. The names of circuit elements, the names of nodes, and the like are also completely the same as those in  FIG. 8 , and thus repetitive description is omitted. 
     In the circuit illustrated in  FIG. 8 , the negative input of the amplifier circuit AMP 2  is the voltage VBE 1  of the band gap circuit BGR 1  ( FIG. 6 ). On the other hand, in the circuit illustrated in  FIG. 13 , the negative input of the amplifier circuit AMP 2  is the voltage VBE 3  of the PTAT current generation circuit BPTAT 1 . Since the PTAT current IPTAT 1  flows through the transistor Q 3  in  FIG. 13  as well, the voltage VBE 3  in  FIG. 13  becomes substantially the same node voltage as the voltage VBE 1  in  FIG. 6 , and its temperature characteristics also exhibit a negative proportionality to absolute temperature. Therefore, the connections as illustrated in  FIG. 13  also make it possible to generate the reference currents IBIAS and IBIASTRIM in the same manner as in the circuit illustrated in  FIG. 8 . 
     When the connections as illustrated in  FIG. 13  are adopted, only the band gap voltage VBGR and the current IBOSC suffice as the potential and bias current to be supplied to the reference current generation circuit IREF 1  ( FIG. 13 ) from the band gap circuit BGR 1  illustrated in  FIG. 6 , thereby advantageously reducing the number of signal lines. 
     On the other hand, in the configuration illustrated in  FIG. 8 , the reference potential (the negative input of the amplifier circuit AMP 2 ) VBE 1  of the CTAT current generation circuit BCTAT 1  is the potential VBE 1  that is already stable, which provides an advantage in that the stabilization time for the reference current when starting the CR oscillating circuit may be shortened. In the circuit illustrated in  FIG. 13 , after the potential VBE 3  of the PTAT current generation circuit BPTAT 1  stabilizes, the potential of the node VFB stabilizes on the basis of this, so the time until the reference current stabilizes is longer than that in the case of the circuit illustrated in  FIG. 8 . 
     The amplifier circuit AMP 1  takes the band gap voltage VBGR of the band gap circuit BGR 1  illustrated in  FIG. 6  as input, and controls the positive dependence current IPTAT 1  flowing through the resistor RR 1  in such a way that the band gap voltage VBGR and the potential of the node RVBE 3  at the other end of the resistor RR 1  become equal to each other. The amplifier circuit AMP 2  controls the negative dependence current ICTAT 1  flowing through the resistor RR 2  in such a way that the emitter potential VBE 3  of the PNP transistor Q 3  and the potential of the node VFB at the other end of the resistor RR 2  become equal to each other. 
       FIG. 14  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit IREF 1  illustrated in  FIG. 7 . PMRCn (n is an integer) denotes a P-channel MOS transistor, AMP 5  and AMP 6  each denote an amplifier circuit (operational amplifier), RR 4  denotes a resistor, RR 7  denotes a variable resistor, and Q 5  denotes a PNP transistor. BPTAT 3  denotes a PTAT current generation circuit, BCTAT 3  denotes a CTAT current generation circuit, PGO 5  denotes a bias potential generated by the PTAT current generation circuit BPTAT 3 , and IPTAT 3  denotes a current flowing through the transistor Q 5 . RVBE 5  denotes a node within the PTAT current generation circuit BPTAT 3 , PGO 6  denotes a bias potential generated by the CTAT current generation circuit BCTAT 3 , and ICTAT 3  denotes a current flowing through the variable resistor RR 7 . VFB denotes a node within the CTAT current generation circuit BCTAT 3 , IBIAS and IBIASTRIM respectively denote the currents IBIAS and IBIASTRIM in  FIG. 7 , VR 18  denotes a positive power supply potential (for example, 1.8 V) generated by a regulator REG 1 , GND denotes a reference potential (ground potential: 0 V), and VBE 1  denotes the potential VBE 1  generated in  FIG. 6 . In  FIG. 14 , nodes or elements corresponding to those in other drawings such as  FIG. 8  are assigned the same symbol to indicate their correspondence, and thus repetitive description is omitted. 
     In  FIG. 8 , the current IPTAT 1  that is proportional to absolute temperature is generated on the basis of the band gap voltage VBGR. On the other hand, in the circuit illustrated in  FIG. 14 , the PTAT current IPTAT 3  is generated on the basis of the potential VBE 1  of the band gap circuit BGR 1 . 
     In  FIG. 12 , the PTAT current IPTAT 2  may be generated by controlling the potentials of the nodes RVBE 5  and VBE 4  so as to coincide with each other. Since the potential of the node VBE 4  in  FIG. 12  and the potential VBE 1  in  FIG. 6  are substantially equal, a PTAT current may be generated also by substituting the potential of the node VBE 4  by the potential VBE 1 . In  FIG. 14 , the PTAT current IPTAT 3  is generated by controlling the potential of the node RVBE 5  and the potential VBE 1  so as to coincide with each other by the amplifier circuit AMP 5 . Adopting the configuration as illustrated in  FIG. 14  makes it possible to reduce the number of elements in comparison to the circuit illustrated in  FIG. 12 . 
     The amplifier circuit AMP 5  takes the emitter potential VBE 1  of the PNP transistor Q 1  of the band gap circuit BGR 1  illustrated in  FIG. 6  as input, and controls the positive dependence current IPTAT 3  flowing through the resistor RR 4  in such a way that the emitter potential VBE 1  and the potential of the node RVBE 5  at the other end of the resistor RR 4  become equal to each other. The amplifier circuit AMP 6  takes the emitter potential VBE 1  of the PNP transistor Q 1  of the band gap circuit BGR 1  illustrated in  FIG. 6  as input, and controls the negative dependence current ICTAT 3  flowing through the resistor RR 7  in such a way that the emitter potential VBE 1  and the potential of the node VFB at the other end of the resistor RR 7  become equal to each other. 
       FIG. 15  is a circuit diagram illustrating another example of the configuration of the reference current generation circuit IREF 1  illustrated in  FIG. 7 . PMRDn (n is an integer) denotes a P-channel MOS transistor, AMP 7  and AMP 8  each denote an amplifier circuit (operational amplifier), RR 1  denotes a resistor, RR 2  denotes a variable resistor, and Q 3  denotes a PNP transistor. BPTAT 4  denotes a PTAT current generation circuit, BCTAT 4  denotes a CTAT current generation circuit, PGO 7  denotes a bias potential generated by the PTAT current generation circuit BPTAT 4 , and IPTAT 4  denotes a current flowing through the transistor Q 3 . RVBE 3  denotes a node within the PTAT current generation circuit BPTAT 4 , PGO 8  denotes a bias potential generated by the CTAT current generation circuit BCTAT 4 , ICTAT 4  denotes a current flowing through the variable resistor RR 2 , and VFB denotes a node within the CTAT current generation circuit BCTAT 4 . IBIAS and IBIASTRIM respectively denote the currents IBIAS and IBIASTRIM illustrated in  FIG. 7 , VDP 5  denotes a positive power supply voltage (for example, 5 V), GND denotes a reference potential (ground potential: 0 V), VBE 1  and VBGR respectively denote the potentials VBE 1  and VBGR generated in  FIG. 6 , and OPCB denotes a bias potential for a cascode circuit. In  FIG. 15 , nodes or elements corresponding to those in other drawings such as  FIG. 8  are assigned the same symbol to indicate their correspondence, and thus repetitive description is omitted. 
     The configuration illustrated in  FIG. 15  is such that the power supply potential VR 18  in the circuit illustrated in  FIG. 8  is substituted by the power supply potential VDP 5 , and the current source is a cascode circuit. Since the basic operation principle is the same as that of the circuit illustrated in  FIG. 8 , detailed description of operation is omitted. 
     In the circuit illustrated in  FIG. 8 , the PTAT current IPTAT 1  is generated on the basis of the band gap voltage VBGR, and the positive-side power supply potential of its current source is the potential VR 18 . The circuit may be operated also when this power supply potential VR 18  is changed to the power supply potential VDP 5 , and  FIG. 15  illustrates such an example. The current source is a cascode circuit because there are cases when the drain voltages of current sources PMRD 3 , PMRD 4 , and the like are large and also the power supply potential VDP 5  fluctuates greatly. The bias potential OPCB serves as a bias potential for this purpose. The bias potential OPCB may be generated by the method as illustrated in  FIG. 10 . It is possible to adopt the configuration as illustrated in  FIG. 15  in cases where the absolute value of the power supply potential VR 18  or power supply potential Vdd is small, and it is more desirable to generate a reference current by using the power supply potential VDP 5 . While  FIG. 15  illustrates an example in which the power supply potential in the circuit illustrated in  FIG. 8  is substituted by the potential VDP 5 , it is needless to mention that in the case of other circuit examples as well, if it is necessary to substitute the power supply potential VR 18  by the power supply potential VDP 5 , the current source may be configured as a cascode circuit. 
     As described above, as illustrated in  FIG. 3 , the CR oscillating circuit according to this embodiment employs the inverter PM 4 , NM 4  in  FIG. 3  and the CMOS transfer gate (transistor) PM 5 , NM 5  connected in series to its output, as means for controlling the charging/discharging current for a load to be constant. The capacitor C 2  is provided to ensure a design such that the signal amplitude of the node ND 4  to be charged/discharged at constant current is smaller than the power supply potential Vdd. Also, as illustrated in  FIG. 7 , in the CR oscillating circuit, the signal TCA [3:0] is provided to regulate the temperature dependence of the reference current of the oscillating circuit from positive to negative. Also, as illustrated in  FIG. 5 , in the micro-controller MCU 1 , the band gap circuit BGR 1 , and the error amplifier EAMP 1  and the regulator output transistor PMO 1  that constitute the regulator REG 1  are provided. The internal voltage Vdd (for example, 1.8 V) is generated by using the output band gap voltage VBGR of the band gap circuit BGR 1 . This internal voltage Vdd (for example, 1.8 V) is supplied to the CR oscillating circuit OSC 1 . Also, as illustrated in  FIG. 5 , the band gap circuit BGR 1  supplies the band gap voltage VBGR to the low voltage detection circuits LVDH 1  and LVDL 1 . Also, the reference current generation circuit IREF 1  illustrated in  FIG. 8  generates the bias currents IBIAS and IBIASTRIM for the CR oscillating circuit OSC 1  on the basis of the band gap voltage VBGR. 
     As illustrated in  FIG. 3 , the CR oscillating circuit employs the inverter PM 4 , NM 4 , and the CMOS transfer gate (transistor) PM 5 , NM 5  connected in series to its output, and the capacitor C 2  is provided to ensure a design such that the signal amplitude of the node ND 4  to be charged/discharged at constant current is smaller than the power supply potential Vdd. Therefore, when switching from charging to discharging or from discharging to charging of a load, it is unnecessary to charge/discharge a parasitic capacitance for ON/OFF of the MOS transistor by the current supplied to the load itself, thereby making it possible to suppress the influence of the parasitic capacitance on the current supplied to the load. 
     Also, as illustrated in  FIG. 7 , by providing the signal TCA [3:0] for regulating the temperature dependence of the reference currents IBIAS and IBIASTRIM of the CR oscillating circuit from positive to negative, it is possible to regulate the temperature dependence of the oscillation frequency of the oscillating circuit for each individual circuit manufactured, thereby enabling an improvement in the accuracy of the oscillation frequency. 
     Also, as illustrated in  FIG. 5 , the band gap circuit BGR 1 , and the error amplifier EAMP 1  and the regulator output transistor PMO 1  that constitute the regulator REG 1  are provided, the internal voltage Vdd (for example, 1.8 V) is generated by using the output band gap voltage VBGR of the band gap circuit BGR 1 , the bias current IBIASROSC for the CR oscillating circuit OSC 1  is generated on the basis of the band gap voltage VBGR, the band gap voltage VBGR is supplied to each of the low voltage detection circuits LVDH 1  and LVDL 1 . Therefore, the band gap circuit BGR 1  may be shared by the regulator REG 1 , the low voltage detection circuits LVDH 1  and LVDL 1 , and the CR oscillating circuit OSC 1 , thereby enabling a reduction in circuit area as compared with a case where a band gap circuit is provided in each of these circuits. 
     According to this embodiment, fluctuation of oscillation frequency due to temperature variation of resistance may be prevented. Also, it is possible to prevent the parasitic capacitance at the drain of a transistor from introducing an error in the setting of current. In addition, it is possible to prevent a situation where the temperature dependence of reference voltage or the temperature dependence of reference current differs slightly for each individual circuit, and thus the temperature dependence of oscillation frequency differs for each individual circuit, introducing a large error in oscillation frequency. Moreover, the micro-controller MCU 1  may be mounted with another circuit such as the regulator circuit REG 1 . 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.