Abstract:
Conventional diode rectifiers usually suffer from a higher conduction loss. The present invention discloses a gate-controlled rectifier, which comprises a line voltage polarity detection circuit, a constant voltage source, a driving circuit and a gate-controlled transistor. The line voltage polarity detection circuit detects the polarity of the line voltage and controls the driving circuit to turn on or turn off the gate-controlled transistor. The gate-controlled transistor may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with a gate, a source and a drain or an Insulated Gate Bipolar Transistor (IGBT) with a gate, an emitter and a collector. The constant voltage source is provided or induced by external circuits and referred to the source of the MOSFET or the emitter of the IGBT. Thanks to a lower conduction loss, this gate-controlled rectifier can be applied to rectification circuits to increase the rectification efficiency.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention discloses a gate-controlled rectifier and applications to rectification circuits thereof for increasing the rectification efficiency. 
         [0003]    2. Description of the Prior Art 
         [0004]    Conventional rectification circuits utilize diodes, which have a unidirectional conduction property, to rectify an AC sinusoidal voltage to a DC pulsating voltage. For example,  FIG. 1  is a half-wave rectification circuit;  FIG. 2A ,  FIG. 2B ,  FIG. 3A  and  FIG. 3B  are full-wave rectification circuits; wherein L and N are respectively line and neutral; T 1  and T 2  are isolation transformers; D 0 , D 1 , D 2  and D 3  are rectification diodes; BD 1  and BD 2  are bridge diodes; R 0 &#39;s are resistive loads. 
         [0005]    Diode rectifiers usually suffer from a higher conduction loss. The present invention discloses a gate-controlled rectifier to reduce the conduction loss and increase the rectification efficiency. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention is directed to a gate-controlled rectifier comprising a line voltage polarity detection circuit, a constant voltage source, a driving circuit and a gate-controlled transistor. 
         [0007]    The gate-controlled transistor may include a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). If the load is resistive, the gate-controlled transistor may include a bidirectional MOSFET (BMOS), a unidirectional MOSFET (UMOS) or an IGBT. If the load is capacitive, the gate-controlled transistor must include a UMOS or an IGBT. The constant voltage source is provided or induced by external circuits and referred to the source of the MOSFET or the emitter of the IGBT. The line voltage polarity detection circuit detects the polarity of the line voltage relative to the neutral voltage and controls the driving circuit to turn on or turn off the gate-controlled transistor. 
         [0008]    The aforementioned gate-controlled transistor may be realized using discrete components or integrated circuits and applied to rectification circuits to reduce the conduction loss and increase the rectification efficiency. 
         [0009]    For better understanding of the present invention and advantages thereof, the following description accompanied with the attached drawings is used to illustrate the spirit of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a circuit diagram illustrating a conventional half-wave rectification circuit. 
           [0011]      FIG. 2A ,  FIG. 2B ,  FIG. 3A  and  FIG. 3B  are circuit diagrams illustrating conventional full-wave rectification circuits. 
           [0012]      FIG. 4 ,  FIG. 5A ,  FIG. 5B ,  FIG. 6A ,  FIG. 6B  and  FIG. 6C  are circuit diagrams of NMOS rectifiers according to the present invention. 
           [0013]      FIG. 7A  and  FIG. 7B  are circuit diagrams of NMOS driving circuits according to the first embodiment of the present invention. 
           [0014]      FIG. 8  is a circuit diagram of a NMOS driving circuit according to the second embodiment of the present invention. 
           [0015]      FIG. 9  is a circuit diagram of a NMOS driving circuit according to the third embodiment of the present invention. 
           [0016]      FIG. 10  is a circuit diagram of a NMOS driving circuit according to the fourth embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0017]    In general, conduction of a diode, a UMOS and an IGBT is unidirectional, and conduction of a BMOS (bidirectional MOSFET), such as a conventional MOSFET, is bidirectional. In  FIG. 6B  the load R 0  is resistive, the gate-controlled transistors Q 0 , Q 1 , Q 2  and Q 3  may be a BMOS, a UMOS or an IGBT. In  FIG. 6C  the load C 7  is capacitive, the gate-controlled transistors U 0 , U 1 , U 2 , and U 3  must be a UMOS or an IGBT. A gate-controlled transistor according to the present invention may be but not limited to an NMOS. For the purpose of description, it is assumed that the gate-controlled transistor is an NMOS and the line voltage source is single-phase herein. The gate-controlled transistor is controlled by the voltage between the gate and a reference, which is the source for NMOS or the emitter for IGBT, to turn on or off the channel between the drain and the source of the MOS or the channel between the collector and the emitter of the IGBT. Here the drain and the source as well as the collector and the emitter are respectively generally called a first channel and a second channel for both types of transistors. However, for clarity, the drain and source are mainly used herein. 
         [0018]    Replacing diodes in rectification circuits with NMOSs must satisfy two conditions: (1) The body diodes of the NMOSs should be in the same polarity orientation as the diodes, for example, the NMOSs in  FIG. 4 ,  FIG. 5A ,  FIG. 5B ,  FIG. 6A  and  FIG. 6B  respectively correspond to the diodes in  FIG. 1 ,  FIG. 2A ,  FIG. 2B ,  FIG. 3A  and  FIG. 3B . (2) Each NMOS should be correctly driven by a driving structure to perform the same conduction as the diodes do. The driving structures disclosed in the present invention are illustrated in  FIG. 7A ,  FIG. 7B ,  FIG. 8 ,  FIG. 9  and  FIG. 10 . 
         [0019]    It is emphatically noted that the application of the gate-controlled rectifier to rectification circuits may be but not limited to single-phase rectification circuits, as illustrated in  FIG. 4 ,  FIG. 5A ,  FIG. 5B ,  FIG. 6A ,  FIG. 6B  and  FIG. 6C , and may also be extended to two-phase or three-phase rectification circuits and so on. 
         [0020]      FIG. 7A  is a circuit diagram illustrating a NMOS driving circuit according to the first embodiment of the present invention, wherein a NMOS rectifier  35  comprises five external pins and four internal blocks. The five external pins are a line L, a neutral N, a DC constant voltage V CC , a reference REF and a drain D; the four internal blocks are a line voltage polarity detection circuit  40 , a constant voltage source  44   a,  a driving circuit  42   a  and a gate-controlled transistor  46   a.  The gate-controlled transistor  46   a  includes a NMOS Q 0  with a gate G, a source S (second channel terminal) and a drain D (first channel terminal). The constant voltage source  44   a  is supplied or induced by external circuits for supplying the DC constant voltage V cc  to the driving circuit  42   a.  The turn-on or turn-off of the NMOS Q 0  is determined by the relative potential difference between the gate G and the source S, so the DC constant voltage V CC  should be referred to the source S of the NMOS Q 0 , no matter what the electric potential of the source S is. It is emphatically noted that the communication between the line voltage polarity detection circuit  40  and the driving circuit  42   a  may be but not limited to optic coupling, magnetic coupling and so on. For the purpose of description, all embodiments according to the present invention are realized with optic coupling. An optodiode U 1 A in the line voltage polarity detection circuit  40  and an optotransistor U 1 B in the driving circuit  42   a  are respectively used as an optotransmitter and an optoreceiver. 
         [0021]    The line voltage polarity detection circuit  40  comprises a current limiting resistor R L  and an optodiode U 1 A for detecting the polarity of the line voltage and transmitting an optic control signal to the driving circuit  42   a.  During positive half cycles of the line voltage, the optodiode U 1 A is forward-biased and then turned on such that a line current flows through and excites the optodiode U 1 A to emit light. During negative half cycles of the line voltage, the optodiode U 1 A is reverse-biased and then turned off so that the optodiode U 1 A does not emit light because the line current can not flow through the optodiode U 1 A. 
         [0022]    The driving circuit  42   a  comprises an optotransistor U 1 B and a first resistor R 1  for receiving an optic control signal transmitted by the line voltage polarity detection circuit  40  and driving the NMOS Q 0 . During positive half cycles of the line voltage, the optotransistor U 1 B is excited and turned on by the optic control signal to conduct a driving current through the first resistor R 1  and generate a driving voltage between the gate and the source of the NMOS Q 0  to turn on the NMOS Q 0 . During negative half cycles of the line voltage, the optotransistor U 1 B is not excited by the optic control signal and then turned off; no driving current flows through the first resistor R 1 , that means the voltage between the gate and the source of the NMOS Q 0  is zero; the NMOS Q 0  is not excited by a driving voltage and then turned off. 
         [0023]    Because the optodiode U 2 A in  FIG. 7B  is in the opposite orientation to the optodiode U 1 A in  FIG. 7A , the NMOS Q 0  in  FIG. 7A  is turned on in positive half cycles and turned off in negative half cycles; the NMOS Q 1  in  FIG. 7B  is turned off in positive half cycles and turned on in negative half cycles. Any rectification circuits can be constructed using these two fundamental NMOS rectifiers. For example, the D 0  and D 1  in  FIG. 2A  can be respectively replaced by the structure in  FIG. 7A  and  FIG. 7B . The U 2 A may be first connected with U 1 A in anti-parallel, and then connected with R L  in series; the constant voltage source  44   a  and  44   b  are respectively referred to the source S of the NMOS Q 0  and Q 1 ; the NMOS Q 0  is driven by the driving circuit  42   a  and the NMOS Q 1  is driven by the driving circuit  42   b.    
         [0024]    The discharging time T dischg  of the NMOS Q 0  may be approximated as: 
         [0000]        T   dischg ≈5  R   i   C   iSS    
         [0000]    wherein C iSS  is the input capacitance of the NMOS Q 0 . The period T line  of the line voltage can be expressed as: 
         [0000]        T   line =1/ f   line    
         [0000]    wherein f line  is the line frequency. The safe operation of the NMOS Q 0  should fulfill the following condition: 
         [0000]      T dischg &lt;&lt;T line    
         [0000]    Assume typical values to be R 1 =10 kΩ and f line =60 Hz, then 
         [0000]        T   dischg ≈5  R   1   C   iSS =0.375 ms&lt;&lt; T   dischg   &lt;&lt;T   line =16.6667 ms 
         [0000]    which means that the discharging time of the NMOS Q 0  is typically far shorter than the period of the line voltage. A method for shortening the turn-off time of the NMOS Q 0  is illustrated in  FIG. 8 . 
         [0025]      FIG. 8  is a circuit diagram illustrating a NMOS driving circuit according to the second embodiment of the present invention. In contrast to the structure in  FIG. 7A , a totem-pole circuit  54   a  is introduced into the driving circuit  42   a  in  FIG. 8 . The totem-pole circuit  54   a  comprises a NPN bipolar transistor Q 4  and a PNP bipolar transistor Q 5 , each of which has a base B, an emitter E and a collector C. The two bases B are connected to the third terminal of the optotransistor U 1 B; the two emitters E are connected to the gate G of the NMOS Q 0 ; the collector C of the NPN bipolar transistor Q 4  and the collector C of the PNP bipolar transistor Q 5  are respectively connected to the forth terminal of the optotransistor U 1 B and the source S of the NMOS Q 0 . 
         [0026]    During positive half cycles of the line voltage, the optotransistor U 1 B is excited by the optic control signal and then turned on; the driving current flows through the first resistor R 1 ; the NPN bipolar transistor Q 4  is forward-biased and then turned on by the driving voltage, while the PNP bipolar transistor Q 5  is reverse-biased and then turned off by the driving voltage; the NMOS Q 0  is charged via the NPN bipolar transistor Q 4  and then turned on. During negative half cycles of the line voltage, the optotransistor U 1 B is not excited by the optic control signal and then turned off; the driving current can not flow through the first resistor R 1 ; the PNP bipolar transistor Q 5  is turned on because the gate charge previously stored on the input capacitor of the NMOS Q 0  causes the PNP bipolar transistor Q 5  to be forward-biased, while the NPN bipolar transistor Q 4  is turned off because the base-emitter junction of the NPN bipolar transistor Q 4  is reverse-biased by the forward-biased emitter-base junction of the PNP bipolar transistor Q 5 ; the NMOS Q 0  is discharged via the PNP bipolar transistor Q 5  and then turned off. 
         [0027]    The NMOS Q 0  in  FIG. 7A  is discharged via the first resistor R 1 , while the NMOS Q 0  in  FIG. 8  is discharged via the PNP bipolar transistor Q 5 ; therefore, the turn-off time of the NMOS Q 0  in  FIG. 8  is shorter than that of the NMOS Q 0  in  FIG. 7A . However, there are still two drawbacks of the driving voltage in  FIG. 7A ,  FIG. 7B  and  FIG. 8 : (1) the rising edges and falling edges are sinusoidal waves; (2) the amplitude of the plateau voltage varies with the amplitude of the line voltage. The aforementioned drawbacks are explained with  FIG. 7A  by taking positive half cycles of the line voltage for example. The forward current i F (t) of the optodiode U 1 A is expressed as: 
         [0000]        i   F ( t )=( v   L-N ( t )− V   F )/ R   L    
         [0000]    wherein v L-N (t) is the sinusoidal line voltage and V F  is the forward voltage drop of the optodiode U 1 A. The collector current i c (t) of the optotransistor U 1 B is expressed as: 
         [0000]        i   C ( t )=η i   F ( t )=[( v   L-N ( t ))− V   F   ]/R   L    
         [0000]    wherein η is the current transfer ratio (CTR) of the optotransistor U 1 B to the optodiode U 1 A. The driving voltage v D (t) of the NMOS Q 0  is expressed as: 
         [0000]        v   D ( t )=R 1   i   c ( t )=ηR 1 [( v   L-N ( t ))− V   F   ]/R   L    
         [0000]    According to the above equation, the driving voltage in  FIG. 7A ,  FIG. 7B  and  FIG. 8 , is a variable amplitude sinusoidal wave. 
         [0028]    In general, the channel threshold voltage V th  of an NMOS is equal to 3V. When v D (t)&lt;V th , the channel of the NMOS cannot be formed; the line current cannot flow through the channel; this time is called “dead time”. When v D (t)≧V th , the channel may be formed; the line current may flow through the channel; this time is called “conduction time”. The advantage of dead time is that it prevents cross conduction between NMOSs in the opposite phase, and its drawback is that the line current may only flow through the body diode of the NMOS during the dead time, resulting in a higher conduction loss. In the situation where there is no cross conduction, the dead time should be as short as possible to increase the rectification efficiency. As for driving a NMOS switch, a driving voltage with constant amplitude is more suitable than one with variable amplitude. Besides, a square wave has a shorter dead time than a sinusoidal wave does. Methods for generating a constant amplitude square wave are shown in  FIG. 9  and  FIG. 10 . 
         [0029]      FIG. 9  is a circuit diagram illustrating a NMOS driving circuit according to the third embodiment of the present invention. In contrast to  FIG. 7A , a switch circuit  64   a  is introduced into the driving circuit  42   a  in  FIG. 9 . The switch circuit  64   a  comprises a threshold switch U 4 , a PNP bipolar transistor Q 5 , a second resistor R 2 , a third resistor R 3  and a fourth resistor R 4 . 
         [0030]    The threshold switch U 4  is realized by a programmable regulator comprising a reference R, an anode A, a cathode K and having a threshold voltage V th . When the voltage difference between the reference R and the anode A is lower than the threshold voltage, v R-A (t)&lt;V th , there is no conduction between the cathode K and the anode A. When v R-A (t)≧V th , a conducting channel is formed between the cathode K and the anode A. 
         [0031]    During positive half cycles of the line voltage, the optotransistor U 1 B is excited by the optic control signal and then turned on; the driving current may flow through the first resistor R 1 . When v R-A (t)&lt;V th , there is no conduction between the cathode K and the anode A; the PNP bipolar transistor Q 5  is not forward-biased by the V CC  and then turned off; the NMOS Q 0  is discharged via the fourth resistor R 4  and then turned off. When v R-A (t)≧V th , a conducting channel is formed between the cathode K and the anode A; the PNP bipolar transistor Q 5  is forward-biased by the V CC  and then turned on; the NMOS Q 0  is charged via the PNP bipolar transistor Q 5  and then turned on. During negative half cycles of the line voltage, the optotransistor U 1 B is not excited by the optic control signal and then turned off; the driving current cannot flow through the first resistor R 1 ; v R-A (t)&lt;V th  so there is no conduction between the cathode K and the anode A; the PNP bipolar transistor Q 5  is not forward-biased by the V CC  and then turned off; the NMOS Q 0  is discharged via the fourth resistor R 4  and then turned off. 
         [0032]    During positive half cycles of the line voltage and when v R-A (t)V th , the PNP bipolar transistor Q 5  is forward-biased by the V CC  and then turned on; the gate-source voltage of the NMOS Q 0  is v GS (t)=V CC , while in other situations, v GS (t)=0. Accordingly, the driving voltage of the NMOS Q 0  is a constant amplitude square wave. Two typical values for the threshold voltage of the programmable regulator in  FIG. 9  are respectively V th =2.5V (for TL 431 ) and V th =1.25V (for TL 432 ). Therefore, the lower the threshold voltage is, the shorter the dead time is and the higher the rectification efficiency is. The threshold voltage can be further reduced via the driving structure in  FIG. 10 . 
         [0033]      FIG. 10  is a circuit diagram illustrating the fourth embodiment of the NMOS driving circuit according to the present invention. In contrast to  FIG. 7A , a switch circuit  74   a  is introduced into the driving circuit  42   a  as shown in  FIG. 10 . The switch circuit  74   a  comprises a threshold switch (a NPN bipolar transistor Q 4 ), a PNP bipolar transistor Q 5 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4  and a fifth resistor R 5 . The threshold switch is realized by a NPN bipolar transistor Q 4  with a base B, an emitter E, a collector C, and a threshold voltage V th &lt;1.25V. The operational principle of the circuit in  FIG. 10  is the same as that in  FIG. 9 , so the detailed descriptions are skipped herein. 
         [0034]    It is emphatically noted that the circuits realizing the aforementioned gate-controller rectifier may be but not limited to discrete components or integrated circuits. Besides, turning on or turning off the aforementioned gate-controlled rectifier should be equivalent to turning on or turning off a diode rectifier. If the load is resistive, the gate-controlled transistor may be a BMOS, a UMOS or an IGBT. If the load is capacitive, the gate-controlled transistor must be a UMOS or an IGBT. Detailed descriptions of the UMOS were given in U.S. patent application Ser. No. 12/554545 and are skipped herein. 
         [0035]    While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.