Abstract:
Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2012-0077408, filed on Jul. 16, 2012, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety as set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Embodiments of the present disclosure generally relates to electronic devices and, more particularly, to semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same. 
         [0004]    2. Related Art 
         [0005]    In the electronic industry, semiconductor packages are generally fabricated by encapsulating semiconductor chips having integrated circuits with resin material or ceramic material to protect the semiconductor chips from an external environment, and the semiconductor packages are mounted on boards of electronic systems. Recently, the semiconductor packages are also fabricated to improve the performance and/or quality of the electronic systems. That is, high performance semiconductor packages are increasingly in demand with the development of lighter, smaller, thinner, faster and multi-functional electronic systems. Accordingly, assembly technologies for making the semiconductor packages have been continuously developed to provide various high performance semiconductor packages. 
         [0006]    Recently, large capacity of memory modules have been more increasingly in demand with the development of lighter, smaller, faster, multi-functional, and higher performance electronic systems. In response to such a demand, multi-chip stacked packages have been proposed. The multi-chip stacked packages are fabricated by vertically stacking a plurality of semiconductor chips on a package substrate. However, the multi-chip stacked packages may be thicker than single-chip packages. Thus, a back grinding process may be applied to a backside surface of a semiconductor wafer including a plurality of semiconductor chips to reduce the thickness of the semiconductor chip, and the thinned semiconductor chips may then be separated from each other using a die sawing process. However, when the semiconductor chips are separated from each other after the backside surface of the semiconductor wafer is ground, cracks may be more readily generated in the thinned semiconductor chips or edges of the thinned semiconductor chips may be more readily broken away during the die sawing process or a subsequent die attaching process. This may be due to a low solidity of the thinned semiconductor chips. To solve this problem, after the semiconductor wafer is diced into two parts using a half cutting process, two separated parts of the semiconductor wafer may be ground. Nevertheless, there may be some limitations in improving the solidity of the thinned semiconductor chips. 
       SUMMARY 
       [0007]    Various embodiments are directed to semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same. 
         [0008]    According to various embodiments, a semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. 
         [0009]    In various embodiments, the non-conductive material pattern may be a material having a solidity which is greater than that of the semiconductor chip body. 
         [0010]    In various embodiments, the non-conductive material pattern may have an adhesive property. 
         [0011]    In various embodiments, the non-conductive material pattern may include an epoxy type polymer material or a silicon resin material. 
         [0012]    According to various embodiments, a semiconductor package includes a substrate, a semiconductor chip attached to the substrate and a mold resin material encapsulating the semiconductor chip. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. 
         [0013]    In various embodiments, the non-conductive material pattern may be a material having a solidity which is greater than that of the semiconductor chip body. 
         [0014]    In various embodiments, the non-conductive material pattern may have an adhesive property. 
         [0015]    In various embodiments, the non-conductive material pattern may include an epoxy type polymer material or a silicon resin material. 
         [0016]    In various embodiments, the non-conductive material pattern may be attached to the substrate. 
         [0017]    According to various embodiments, a method of fabricating a semiconductor chip includes forming a plurality of arch-shaped grooves in a backside of a semiconductor wafer having a plurality of semiconductor chips, forming a plurality of non-conductive material patterns in respective ones of the plurality of arch-shaped grooves, and separating the plurality of semiconductor chips including the non-conductive material patterns. 
         [0018]    In various embodiments, forming the plurality of arch-shaped grooves may include attaching a jig having a plurality of openings that expose respective ones of the semiconductor chips to a backside surface of the semiconductor wafer, etching a backside of the semiconductor wafer using the jig as an etch mask, and detaching the jig from the semiconductor wafer. 
         [0019]    In various embodiments, the backside of the semiconductor wafer may be etched using at least one of a physical etching process and a chemical etching process. 
         [0020]    In various embodiments, forming the plurality of non-conductive material patterns may include coating a non-conductive material layer on a backside surface of the semiconductor wafer to fill the arch-shaped grooves, and grinding the non-conductive material layer and the semiconductor wafer. 
         [0021]    According to various embodiments, a method of fabricating a semiconductor package includes forming a plurality of arch-shaped grooves in a backside of a semiconductor wafer having a plurality of semiconductor chips, forming a plurality of non-conductive material patterns in respective ones of the plurality of arch-shaped grooves, separating the plurality of semiconductor chips including the non-conductive material patterns, attaching one of the separated semiconductor chips to a substrate, electrically connecting the attached semiconductor chip to the substrate through wires, and forming a mold resin material encapsulating the attached semiconductor chip and the wires. 
         [0022]    In various embodiments, forming the plurality of arch-shaped grooves may include attaching a jig having a plurality of openings that expose respective ones of the semiconductor chips to a backside surface of the semiconductor wafer, etching a backside of the semiconductor wafer using the jig as an etch mask, and detaching the jig from the semiconductor wafer. 
         [0023]    In various embodiments, the backside of the semiconductor wafer may be etched using at least one of a physical etching process and a chemical etching process. 
         [0024]    In various embodiments, forming the plurality of non-conductive material patterns may include coating a non-conductive material layer on a backside surface of the semiconductor wafer to fill the arch-shaped grooves, and grinding the non-conductive material layer and the semiconductor wafer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]    Embodiments of the inventive concept will become more apparent in view of the attached drawings and accompanying detailed description, in which: 
           [0026]      FIG. 1  is a cross sectional view illustrating a semiconductor chip according to various embodiments; 
           [0027]      FIG. 2  is a plan view of a semiconductor wafer including a semiconductor chip of  FIG. 1 ; 
           [0028]      FIGS. 3 ,  4 ,  5  and  6  are cross sectional views taken along a line III-III′ of  FIG. 2  to illustrate a method of fabricating semiconductor chips according to various embodiments; and 
           [0029]      FIG. 7  is a cross sectional view illustrating a semiconductor package according to various embodiments and a method of fabricating the same. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]      FIG. 1  is a cross sectional view illustrating a semiconductor chip according to various embodiments. Referring to  FIG. 1 , a semiconductor chip  100  according to an embodiment may be configured to include a semiconductor chip body  110  and a non-conductive material pattern  118 , and the semiconductor chip body  110  may have a top surface  111  and a bottom surface  112 . The semiconductor chip body  110  may include a semiconductor material, for example, a silicon material. Although not shown in the figures, active elements such as transistors and/or passive elements such as capacitors or inductors may be disposed in the semiconductor chip body  110 . An arch-shaped groove  115  may be disposed to be adjacent to the bottom surface  112  of the semiconductor chip body  110 . The arch-shaped groove  115  may be filled with the non-conductive material pattern  118 . The non-conductive material pattern  118  may have a solidity which is greater or stronger than that of the semiconductor chip body  110 , for example, a silicon material. Further, the non-conductive material pattern  118  may have an adhesive property. In various embodiments, the non-conductive material pattern  118  may include an epoxy type polymer material or a silicon resin material. As described above, an interface between the non-conductive material pattern  118  and the semiconductor chip body  110  may have an arch-shaped configuration, and the non-conductive material pattern  118  may be stronger than the semiconductor chip body  110  in terms of the solidity. In particular, the non-conductive material pattern  118  may fill the arch-shaped groove  115 . Thus, the solidity of the semiconductor chip  100  may be remarkably improved. 
         [0031]      FIG. 2  is a plan view of a semiconductor wafer including a semiconductor chip of  FIG. 1 , and  FIGS. 3 ,  4 ,  5  and  6  are cross sectional views taken along a line III-III′ of  FIG. 2  to illustrate a method of fabricating semiconductor chips according to various embodiments. Referring to  FIGS. 2 and 3 , a semiconductor wafer  300  including a plurality of semiconductor chips  301 ,  302 ,  303 ,  304 ,  305 ,  306  and  307  may be provided, and the semiconductor wafer  300  may have a top surface  300 - 1  and a bottom or back surface  300 - 2 . The semiconductor wafer  300  may be flipped such that the bottom or back surface  300 - 2  is located at a higher level than the top surface  300 - 1 . The semiconductor wafer  300  may be flipped using a carrier wafer (not shown). Each of the semiconductor chips  301 ,  302 ,  303 ,  304 ,  305 ,  306  and  307  may include active elements and/or passive elements. 
         [0032]    A jig  310  may then be attached to the bottom or back surface  300 - 2  of the semiconductor wafer  300  using an adhesive agent. The adhesive agent used in attachment of the jig  310  may be a material that loses its adhesive property via a chemical reaction to easily detach the jig  310  from the semiconductor wafer  300  in a subsequent process. For example, the adhesive agent used in attachment of the jig  310  may be a material that loses its adhesive property when exposed to ultraviolet (UV) rays. In some embodiments, the jig  310  may be fixed to the semiconductor wafer  300  using another fixing means instead of the adhesive agent. 
         [0033]    The jig  310  may have a plurality of openings  311 ,  312 ,  313 ,  314 ,  315 ,  316  and  317  exposing the back or bottom surfaces  300 - 2  of the semiconductor chips  301 ,  302 ,  303 ,  304 ,  305 ,  306  and  307 . The number of the openings may be equal to the number of the semiconductor chips. That is, the openings may expose the corresponding semiconductor chips. Specifically, the opening  311  may expose the back or bottom surface  300 - 2  of the semiconductor chip  301 , and the opening  312  may expose the back or bottom surface  300 - 2  of the semiconductor chip  302 . Similarly, the other openings may expose the back or bottom surfaces  300 - 2  of the corresponding semiconductor chips, respectively. The jig  310  may be formed of a material having an etch selectivity with respect to the wafer  300 , for example, a silicon material. 
         [0034]    Referring to  FIG. 4 , the backside or bottom surfaces  300 - 2  of the semiconductor wafer  300  may be etched using the jig  310  as an etch mask to form a plurality of arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7  in respective ones of the semiconductor chips  301 ,  302 ,  303 ,  304 ,  305 ,  306  and  307 . In various embodiments, the etching process for forming the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7  may be performed using a physical etching process or a chemical etching process. Alternatively, the etching process for forming the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7  may be performed using both the physical etching process and the chemical etching process. A depth of the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7  may be appropriately controlled such that the active elements and/or the passive elements formed in the semiconductor chips  301 ,  302 ,  303 ,  304 ,  305 ,  306  and  307  are not damaged by the etching process. 
         [0035]    Referring  FIG. 5 , after formation of the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7 , the jig  310  may be detached or removed from the semiconductor wafer  300 . A non-conductive material layer  320  may be coated on the backside or bottom surface  300 - 2  of the substrate where the jig  310  is removed. The non-conductive material layer  320  may be formed of a material having a solidity which is greater or stronger than that of the semiconductor wafer  300 , for example, a silicon wafer. Further, the non-conductive material layer  320  may be formed of a material having an adhesive property. Moreover, the non-conductive material layer  320  may be formed of a material having substantially the same or similar grinding rate as the semiconductor wafer  300 , for example, a silicon wafer. In various embodiments, the non-conductive material layer  320  may be formed of an epoxy type polymer material or a silicon resin material. 
         [0036]    Referring to  FIG. 6 , the non-conductive material layer  320  may be ground to expose the backside or bottom surface  300 - 2  of the semiconductor wafer  300 . Subsequently, the semiconductor wafer  300  and the non-conductive material layer  320  remaining in the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7  may be continuously ground until the semiconductor wafer  300  has a desired thickness. Even after the semiconductor wafer  300  is ground to have a desired thickness, portions of the non-conductive material layer  320  may still remain in respective ones of the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7 . That is, non-conductive material patterns  318 - 1 ,  318 - 2 ,  318 - 3 ,  318 - 4 ,  318 - 5 ,  318 - 6  and  318 - 7  may be formed in respective ones of the arch-shaped grooves  315 - 1 ,  315 - 2 ,  315 - 3 ,  315 - 4 ,  315 - 5 ,  315 - 6  and  315 - 7  after the semiconductor wafer  300  is ground to have a desired thickness. The ground semiconductor wafer  300  may then be diced using a die sawing process to separate the semiconductor chips  301 ,  302 ,  303 ,  304 ,  305 ,  306  and  307  from each other. As a result, a plurality of semiconductor chips having the same structure as the semiconductor chip  100  illustrated in  FIG. 1  may be obtained. 
         [0037]    According to the above description, the grinding process may be followed by the die sawing process. However, in various embodiments, the grinding process may be preceded by a half cutting process. That is, the semiconductor wafer  300  including the non-conductive material layer  320  may be divided into a first half part and a second half part using the half cutting process, and the grinding process may be applied to the non-conductive material layers  320  of the first and second half parts of the semiconductor wafer  300 . 
         [0038]      FIG. 7  is a cross sectional view illustrating a semiconductor package according to various example embodiments and a method of fabricating the same. Referring to  FIG. 7 , a semiconductor package  500  according to an embodiment may be configured to include a substrate  510 , a semiconductor chip  100 , semiconductor chip body  110 , and a mold resin material  550 . The substrate  510  may be a package substrate, and solder balls  520  may be attached to a bottom surface of the substrate  510 . The semiconductor package  500  may be electrically connected to an external device through the solder balls  520 . The number of the solder balls  520  may be determined according to the number of input/output terminals of the semiconductor package  500 . 
         [0039]    The semiconductor chip  100  may be mounted on or attached to a top surface of the substrate  510  using an adhesive agent  530 . The semiconductor chip  100  may have substantially the same configuration as described with reference to  FIG. 1 . That is, the semiconductor chip  100  may include an arch-shaped groove in the backside thereof, and the arch-shaped groove may be filled with a non-conductive material pattern  118 . The non-conductive material pattern  118  and the backside surface of the semiconductor chip  100  may be attached to the top surface of the substrate  510  using the adhesive agent  530 , as described above. When the non-conductive material pattern  118  has an adhesive property, the non-conductive material pattern  118  may be directly attached to the top surface of the substrate  510  without use of the adhesive agent  530 . However, even though the non-conductive material pattern  118  has an adhesive property, the non-conductive material pattern  118  may be attached to the top surface of the substrate  510  using the adhesive agent  530 . In such a case, adhesion between the semiconductor chip  100  and the substrate  510  may be improved more. The semiconductor chip  100  may be electrically connected to the substrate  510  through wires  540 . The semiconductor chip  100  and the wires  540  may be encapsulated by a mold resin material  550 . 
         [0040]    To fabricate the semiconductor package  500 , the semiconductor chip  100  may be formed using the same manners as described with reference to  FIGS. 2 to 6 , and the semiconductor chip  100  may be attached to the top surface of the substrate  510  using an adhesive agent  530 . When the semiconductor chip  100  is attached to the top surface of the substrate  510 , the non-conductive material pattern  118  of the semiconductor chip  100  may be attached to the top surface of the substrate  510  using the adhesive agent  530 . Subsequently, the wires  540  may be formed to electrically connect the semiconductor chip  100  to the substrate  510 . Finally, the mold resin material  550  may be formed to encapsulate the semiconductor chip  100  and the wires  540 . 
         [0041]    According to the embodiments set forth above, a non-conductive material pattern may fill an arch-shaped groove formed in a bottom of a semiconductor chip. Thus, the solidity of the semiconductor chip may be improved because of the presence of the non-conductive material pattern. As a result, when the semiconductor chip including the non-conductive material pattern is attached to a package substrate or is diced using a die sawing process, the non-conductive material pattern may suppress or prevent the semiconductor chip from being damaged or broken. 
         [0042]    The embodiments have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.