Abstract:
An image sensing device includes a first read unit suitable for generating a first read signal by reading a first pixel signal, a first input line suitable for transmitting the first pixel signal, a first feedback line suitable for feeding back the first read signal, a second read unit disposed adjacent to the first read unit in a same row and suitable for generating a second read signal by reading a second pixel signal, a second input line suitable for transmitting the second pixel signal, and a second feedback line suitable for feeding back the second read signal wherein the first input line and the first feedback line are disposed symmetrically to the second input line and the second feedback line.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of Korean Patent Application No. 10-2013-0160394, filed on Dec. 20, 2013, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments of the present invention relate to semiconductor design technology, and, more particularly, to an image sensing device. 
     2. Description of the Related Art 
     In general, an image sensing device refers to a device that captures an image by using a semiconductor with properties that respond to incident light. Charge Coupled Device (CCD) technology has been widely used for image sensing devices. However, as Complementary Metal Oxide Semiconductor (CMOS) technology has rapidly progressed, an image sensing device using CMOS technology (which is referred to as a CMOS image sensing device, hereinafter) developed. Compared to typical Charge Coupled Device (CCD) technology, the CMOS image sensing device has an advantage in that analog and digital control circuits may be directly implemented as an integrated circuit (IC) on a single chip. 
     A CMOS image sensing device has as many comparators as the number of columns in its pixel array. The comparators convert pixel signals outputted from pixels arranged in each row into digital signals. The comparator compares the pixel signal with a ramp signal to output the digital signal that is stored as an image. 
       FIG. 1  is a block diagram illustrating a layout of a typical image sensing device. 
     Referring to  FIG. 1 , the image sensing device includes a pixel array AR having a plurality of pixels arranged in rows and columns. Using a simplified example for ease of explanation, the pixels of the pixel array AR are arranged in two rows ROW 0  to ROW 1  and four columns COL 0  to COL 3 . A structure corresponding to each of the columns COL 0  to COL 3  will be described. 
     A first column path corresponding to the first column COL 0  will be described next. 
     The first column path includes a first pixel storage unit MIMI 0 , a first transmission line CL 0 , a first comparison unit AMP 0 , a first input line IL 0 , a first feedback line FL 0 , a first amplification storage unit MIMO 0 , a first primary output line OTL 0 , and a first secondary output line OBL 0 . The first pixel storage unit MIMI 0  stores a first pixel signal outputted from pixels Gr 0  and B 0  of a first column COL 0 . The first transmission line CL 0  is extended in a column direction and transmits the first pixel signal outputted from the pixels Gr 0  and B 0  of the first column COL 0  to the first pixel storage unit MIMI 0 . The first comparison unit AMP 0  reads the first pixel signal stored in the first pixel storage unit MIMI 0  and generates first differential read signals, which are digital signals. The first input line IL 0  is extended in the column direction and transmits the first pixel signal stored in the first pixel storage unit MIMI 0  to the first comparison unit AMP 0 . The first feedback line FL 0  is extended in parallel with the first input line IL 0  and feeds back a first primary read signal of the first differential read signals. The first amplification storage unit MIMO 0  stores the first primary read signal. The first primary output line OTL 0  is extended in the column direction and transmits the first primary read signal to the first amplification storage unit MIMO 0 . The first secondary output line OBL 0  is extended in parallel with the first primary output line OTL 0  and transmits a first secondary read signal of the first differential read signals to an internal circuit (not shown). 
     The first pixel storage unit MIMI 0  is spaced apart from the pixels Gr 0  and B 0  of the first column COL 0  in the column direction. The first comparison unit AMP 0  is spaced apart from the first pixel storage unit MIMI 0  in the column direction. The first amplification storage unit MIMO 0  is spaced apart from the first comparison unit AMP 0  in the column direction. 
     A second column path corresponding to a second column COL 1  will be described next. 
     The second column path includes a second pixel storage unit MIMI 1 , a second transmission line CL 1 , a second comparison unit AMP 1 , a second input line IL 1 , a second feedback line FL 1 , a second amplification storage unit MIMO 1 , a second primary output line OTL 1 , and a second secondary output line OBL 1 . The second pixel storage unit MIMI 1  stores a second pixel signal outputted from pixels R 0  and Gb 0  of a second column COL 1 . The second transmission line CL 1  is extended in a column direction and transmits the second pixel signal outputted from the pixels R 0  and Gb 0  of the second column COL 1  to the second pixel storage unit MIMI 1 . The second comparison unit AMP 1  reads the second pixel signal stored in the second pixel storage unit MIMI 1  and generates second differential read signals, which are digital signals. The second input line IL 1  is extended in the column direction and transmits the second pixel signal stored in the second pixel storage unit MIMI 1  to the second comparison unit AMP 1 . The second feedback line FL 1  is extended in parallel with the second input line IL 1  and feeds back a second primary read signal of the second differential read signals. The second amplification storage unit MIMO 1  stores the second primary read signal. The second primary output line OTL 1  is extended in the column direction and transmits the second primary read signal to the second amplification storage unit MIMO 1 . The second secondary output line OBL 1  is extended in parallel with the second primary output line OTL 1  and transmits a second secondary read signal of the second differential read signals to an internal circuit (not shown). 
     The second pixel storage unit MIMI 1  is spaced apart from the pixels R 0  and Gb 0  of the second column COL 1  in the column direction. The second comparison unit AMP 1  is spaced apart from the second pixel storage unit MIMI 1  in the column direction. The second amplification storage unit MIMO 1  is spaced apart from the second comparison unit AMP 1  in the column direction. 
     The first pixel storage unit MIMI 0  and the second pixel storage unit MIMI 1  are disposed in the column direction. The first comparison unit AMP 0  and the second comparison unit AMP 1  are disposed in a row direction. The first amplification storage unit MIMO 0  and the second amplification storage unit MIMO 1  are disposed in the column direction. 
     The disposition order of the first input line IL 0  and the first feedback line FL 0  is asymmetrical to that of the second input line IL 1  and the second feedback line FL 1 . The disposition order of the first primary output line OTL 0  and the first secondary output line OBL 0  is asymmetrical to that of the second primary output line OTL 1  and the second secondary output line OBL 1 . For example, the input lines IL 0  and IL 1  and the corresponding feedback lines FL 0  and FL 1  are sequentially disposed from the left side of the CMOS image sensing device while the primary output lines OTL 0  and OTL 1  and the corresponding secondary output lines OBL 0  and OBL 1  are sequentially disposed from the left side of the CMOS image sensing device. 
     Next, a third column path corresponding to a third column COL 2  is described. 
     The third column path includes a third pixel storage unit MIMI 2 , a third transmission line CL 2 , a third comparison unit AMP 2 , a third input line IL 2 , a third feedback line FL 2 , a third amplification storage unit MIMO 2 , a third primary output line OTL 2 , and a third secondary output line OBL 2 . The third pixel storage unit MIMI 2  stores a third pixel signal outputted from pixels Gr 1  and B 1  of a third column COL 2 . The third transmission line CL 2  is extended in a column direction and transmits the third pixel signal outputted from the pixels Gr 1  and B 1  of the third column COL 2  to the third pixel storage unit MIMI 2 . The third comparison unit AMP 2  reads the third pixel signal stored in the third pixel storage unit MIMI 2  and generates third differential read signals which are digital signals. The third input line IL 2  is extended in the column direction and transmits the third pixel signal stored in the third pixel storage unit MIMI 2  to the third comparison unit AMP 2 . The third feedback line FL 2  is extended in parallel with the third input line IL 2  and feeds back a third primary read signal of the third differential read signals. The third amplification storage unit MIMO 2  stores the third primary read signal. The third primary output line OTL 2  is extended in the column direction and transmits the third primary read signal to the third amplification storage unit MIMO 2 . The third secondary output line OBL 2  is extended in parallel with the third primary output line OTL 2  and transmits a third secondary read signal of the third differential read signals to an internal circuit (not shown). 
     The third pixel storage unit MIMI 2  is spaced apart from the pixels Gr 1  and B 1  of the third column COL 2  in the column direction. The third comparison unit AMP 2  is spaced apart from the third pixel storage unit MIMI 2  in the column direction. The third amplification storage unit MIMO 2  is spaced apart from the third comparison unit AMP 2  in the column direction. 
     Hereafter, a fourth column path corresponding to a fourth column COL 3  is described. 
     The fourth column path includes a fourth pixel storage unit MIMI 3 , a fourth transmission line CL 3 , a fourth comparison unit AMP 3 , a fourth input line IL 3 , a fourth feedback line FL 3 , a fourth amplification storage unit MIMO 3 , a fourth primary output line OTL 3 , and a fourth secondary output line OBL 3 . The fourth pixel storage unit MIMI 3  stores a fourth pixel signal outputted from pixels R 1  and Gb 1  of a fourth column COL 3 . The fourth transmission line CL 3  is extended in a column direction and transmits the fourth pixel signal outputted from the pixels R 1  and Gb 1  of the fourth column COL 3  to the fourth pixel storage unit MIMI 3 . The fourth comparison unit AMP 3  reads the fourth pixel signal stored in the fourth pixel storage unit MIMI 3  and generates fourth differential read signals, which are digital signals. The fourth input line IL 3  is extended in the column direction and transmits the fourth pixel signal stored in the fourth pixel storage unit MIMI 3  to the fourth comparison unit AMP 3 . The fourth feedback line FL 3  is extended in parallel with the fourth input line IL 3  and feeds back a fourth primary read signal of the fourth differential read signals. The fourth amplification storage unit MIMO 3  stores the fourth primary read signal. The fourth primary output line OTL 3  is extended in the column direction and transmits the fourth primary read signal to the fourth amplification storage unit MIMO 3 . The fourth secondary output line OBL 3  is extended in parallel with the fourth primary output line OTL 3  and transmits a fourth secondary read signal of the fourth differential read signals to an internal circuit (not shown). 
     The fourth pixel storage unit MIMI 3  is disposed apart from the pixels R 1  and Gb 1  of the fourth column COL 3  in the column direction. The fourth comparison unit AMP 3  is disposed apart from the fourth pixel storage unit MIMI 3  in the column direction. The fourth amplification storage unit MIMO 3  is disposed apart from the fourth comparison unit AMP 3  in the column direction. 
     The third pixel storage unit MIMI 2  and the fourth pixel storage unit MIMI 3  are disposed in the column direction. The third comparison unit AMP 2  and the fourth comparison unit AMP 3  are disposed in a row direction. The third amplification storage unit MIMO 2  and the fourth amplification storage unit MIMO 3  are disposed in the column direction. 
     The disposition order of the third input line IL 2  and the third feedback line FL 2  is asymmetrical to that of the fourth input line IL 3  and the fourth feedback line FL 3 . The disposition order of the third primary output line OTL 2  and the third secondary output line OBL 2  is asymmetrical to that of the fourth primary output line OTL 3  and the fourth secondary output line OBL 3 . For example, the input lines IL 2  and IL 3  and the corresponding feedback lines FL 2  and FL 3  are sequentially disposed from the left side of the CMOS image sensing device, and the primary output lines OTL 2  and OTL 3  and the corresponding secondary output lines OBL 2  and OBL 3  are sequentially disposed from the left side of the CMOS image sensing device. 
     A shielding line SL is extended in the column direction at an interval of two column paths in the image sensing device. In other words, the image sensing device includes a first shielding line SL between the first column path and a column path adjacent to a left side of the first column path (not shown), a second shielding line SL between the second column path and the third column path, and a third shielding line SL between the fourth column path and a column path adjacent to a right side of the fourth column path (not shown). 
       FIG. 2  is a circuit diagram illustrating in detail the column path described above.  FIG. 2  illustrates only the first and second column paths corresponding to the first and second columns COL 0  and COL 1 , respectively. 
     Referring to  FIG. 2 , the first column path includes the first pixel storage unit MIMI 0 , the first comparison unit AMP 0 , and the first amplification storage unit MIMO 0 . The first pixel storage unit MIMI 0  includes a capacitor, and the first comparison unit AMP 0  includes a differential amplifier, while the first amplification storage unit MIMO 0  includes a capacitor. The first comparison unit AMP 0  outputs first differential read signals Voutp 0  and Voutn 0  after drawing a comparison between a first ramp signal Vramp 0  transmitted through a first standard line RL 0  and a first pixel signal Vin 0  transmitted through the first input line IL 0 . The first standard line RL 0  is mentioned for a better understanding of the first comparison unit AMP 0 , but it is not shown in  FIG. 1 . 
     The first column path further includes a first feedback unit SW 0 . The first feedback unit SW 0  is coupled between the first feedback line FL 0  and the first input line IL 0 , and the first feedback unit SW 0  applies the first primary read signal Voutp 0  to the first pixel signal Vin 0 . The first feedback unit SW 0  includes a switch for selectively connecting the first feedback line FL 0  to the first input line IL 0  in response to a control signal (not shown). The first feedback unit SW 0  is described for better understanding of the feedback path, although it is not shown in  FIG. 1 . 
     The second column path includes the second pixel storage unit MIMI 1 , the second comparison unit AMP 1 , and the second amplification storage unit MIMO 1 . A description on a structure of the second column path is omitted herein because the structure of the second column path is the same as that of the first column path. 
     The operation of the image sensing device having the above-described structure will now be described. 
     The rows of pixels of a pixel array AR are sequentially selected and first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  outputted from the pixels of the selected row are transmitted through the first to fourth column paths, respectively. For example, when the first row ROW 0  is selected, the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  are outputted from the respective pixels Gr 0 , R 0 , Gr 1  and R 1  of the first row ROW 0 , and the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  are transmitted through the first to fourth column paths, respectively. 
     The process of the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  being transmitted through the first to fourth column paths, respectively, is as follows. 
     The first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3  store the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  outputted from the pixel array AR. The first to fourth comparison units AMP 0 , AMP 1 , AMP 2  and AMP 3  generate the first to fourth differential read signals Voutp 0  and Voutn 0 , Voutp 1  and Voutn 1 , Voutp 2  and Voutn 2 , and Voutp 3  and Voutn 3  in response to the first to fourth pixel signals Vin 0 , Vin 1 , Vin 2  and Vin 3  stored in the first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3 . The first to fourth amplification storage units MIMO 0 , MIMO 1 , MIMO 2  and MIMO 3  store the first to fourth primary read signals Voutp 0 , Voutp 1 , Voutp 2  and Voutp 3 . The first to fourth feedback units SW 0 , SW 1 , SW 2  and SW 3  apply the first to fourth primary read signals Voutp 0 , Voutp 1 , Voutp 2  and Voutp 3  to the first to fourth pixel signals Vin 0 , Vin 1 , Vin 2  and Vin 3  in response to the control signal (not shown). 
     The first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  outputted from the pixel array AR are transmitted to the first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3  through the first to fourth transmission lines CL 0 , CL 1 , CL 2  and CL 3 . The first to fourth pixel signals Vin 0 , Vin 1 , Vin 2  and Vin 3  stored in the first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3  are transmitted to the first to fourth comparison units AMP 0 , AMP 1 , AMP 2  and AMP 3  through the first to fourth input lines IL 0 , IL 1 , IL 2  and IL 3 . The first to fourth primary read signals Voutp 0 , Voutp 1 , Voutp 2  and Voutp 3  are transmitted to the first to fourth amplification storage units MIMO 0 , MIMO 1 , MIMO 2  and MIMO 3  through the first to fourth primary output lines OTL 0 , OTL 1 , OTL 2  and OTL 3 , and simultaneously to the first to fourth feedback units SW 0 , SW 1 , SW 2  and SW 3  through the first to fourth feedback lines FL 0 , FL 1 , FL 2  and FL 3 . 
     However, the image sensing device having the above-described structure may have the following concerns. 
     As the size of pixels in a pixel array AR becomes smaller due to technological advances, the pitch between column paths and the pitch between signal lines becomes narrow. This forms a parasitic capacitor and interference between the signal lines, i.e., a coupling effect, occurs. For example, as the first primary read signal Voutp 0  and the second pixel signal Vin 1  having different dynamic ranges are transmitted through the first feedback line FL 0  and the second input line IL 1 , which are disposed adjacent to each other, a coupling effect occurs. As the first secondary read signal Voutn 0  and the second primary read signal Voutp 1 , having different dynamic ranges, are transmitted through the first secondary output line OBL 0  and the second primary output line OTL 1 , which are disposed adjacent to each other, the coupling effect occurs (refer to  FIG. 1 ). As the pitch between the column paths and the pitch between the signal lines becomes narrow, the extent of the coupling may gradually increase. 
     The surest way to prevent the signal line coupling is through the shielding line SL. However, there is a limitation in preventing coupling through the shielding line SL because the conditions for forming the shielding line SL are worse as the space becomes narrower. 
     SUMMARY 
     Exemplary embodiments of the present invention are directed to an image sensing device having a layout structure in which the interference between column paths is minimized. 
     In accordance with an embodiment of the present invention, the image sensing device includes a first read unit suitable for generating a first read signal by reading a first pixel signal, a first input line suitable for transmitting the first pixel signal, a first feedback line suitable for feeding back the first read signal, a second read unit disposed adjacent to the first read unit in a same row and suitable for generating a second read signal by reading a second pixel signal, a second input line suitable for transmitting the second pixel signal, and a second feedback line suitable for feeding back the second read signal wherein the first input line and the first feedback line are disposed symmetrically to the second input line and the second feedback line. 
     In accordance with another embodiment of the present invention, the image sensing device includes a first read unit suitable for generating first differential read signals by reading a first pixel signal, a first primary output line extended in a column direction and suitable for transmitting a first primary read signal of the first differential read signals, a first secondary output line extended in the column direction and suitable for transmitting a first secondary read signal of the first differential read signals, a second read unit disposed adjacent to the first read unit in a row direction and suitable for generating second differential read signals by reading a second pixel signal, a second primary output line extended in the column direction and suitable for transmitting a second primary read signal of the second differential read signals, and a second secondary output line extended in the column line and suitable for transmitting a second secondary read signal of the second differential read signals wherein the first primary output line and the first secondary output line are disposed symmetrically to the second primary output line and the second secondary output line. 
     In accordance with a further embodiment of the present invention, the image sensing device has a pixel array which includes a plurality of pixels arranged in rows and columns, a first read unit suitable for generating first differential read signals by reading a first pixel signal outputted from pixels of an N th  column where N is an integer equal to or greater than 1, a first input line extended in a column direction and suitable for transmitting the first pixel signal, a first feedback line extended in parallel with the first input line and suitable for feeding back a first primary read signal of the first differential read signals, a second read unit disposed adjacent to the first read unit in a row direction and suitable for generating second differential read signals by reading a second pixel signal outputted from pixels of an (N+2) th  column, a second input line extended in the column direction and suitable for transmitting the second pixel signal, a second feedback line extended in parallel with the second input line and suitable for feeding back a second primary read signal of the second differential read signals, a third read unit disposed adjacent to the second read unit in the row direction and suitable for generating third differential read signals by reading a third pixel signal outputted from pixels of an (N+1) th  column, a third input line extended in the column direction and suitable for transmitting the third pixel signal, a third feedback line extended in parallel with the third input line and suitable for feeding back a third primary read signal of the third differential read signals, a fourth read unit disposed adjacent to the third read unit in the row direction and suitable for generating fourth differential read signals by reading a fourth pixel signal outputted from pixels of an (N+ 3 ) th  column, a fourth input line extended in the column direction and suitable for transmitting the fourth pixel signal, and a fourth feedback line extended in parallel with the fourth input line and suitable for feeding back a fourth primary read signal of the fourth differential read signals wherein the first and second feedback lines are disposed highly adjacent to each other in proportion to the first and second input lines, and the third and fourth feedback lines are disposed highly adjacent to each other in proportion to the third and fourth input lines. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a layout of a typical image sensing device. 
         FIG. 2  is a circuit diagram illustrating in detail a first and a second column path shown in  FIG. 1 . 
         FIG. 3  is a block diagram illustrating a layout of an image sensing device in accordance with an embodiment of the present invention. 
         FIG. 4  is a circuit diagram illustrating in detail a first and a second column path shown in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. When describing the present invention, widely-known structures and components irrelevant to the substance of the present invention will be omitted. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
       FIG. 3  is a block diagram illustrating a layout of an image sensing device in accordance with an embodiment of the present invention. 
     Referring to  FIG. 3 , the image sensing device includes a pixel array AR having a plurality of pixels arranged in rows and columns. In a simplified example, pixels of the pixel array AR are arranged into two rows ROW 0  to ROW 1  and four columns COL 0  to COL 3 . A structure corresponding to each of the columns COL 0  to COL 3  will now be described. 
     A first column path corresponding to a first column COL 0  will be described first. 
     The first column path includes a first pixel storage unit MIMI 0 , a first transmission line CL 0 , a first comparison unit AMP 0 , a first input line IL 0 , a first feedback line FL 0 , a first amplification storage unit MIMO 0 , a first primary output line OTL 0 , and a first secondary output line OBL 0 . The first pixel storage unit MIMI 0  stores a first pixel signal outputted from pixels Gr 0  and B 0  of a first column COL 0 . The first transmission line CL 0  is extended in a column direction and transmits the first pixel signal outputted from the pixels Gr 0  and B 0  of the first column COL 0  to the first pixel storage unit MIMI 0 . The first comparison unit AMP 0  reads the first pixel signal stored in the first pixel storage unit MIMI 0  and generates first differential read signals. The first input line IL 0  is extended in the column direction and transmits the first pixel signal stored in the first pixel storage unit MIMI 0  to the first comparison unit AMP 0 . The first feedback line FL 0  is extended in parallel with the first input line IL 0  and feeds back a first primary read signal of the first differential read signals. The first amplification storage unit MIMO 0  stores the first primary read signal. The first primary output line OTL 0  is extended in the column direction and transmits the first primary read signal to the first amplification storage unit MIMO 0 . The first secondary output line OBL 0  is extended in parallel with the first primary output line OTL 0  and transmits a first secondary read signal of the first differential read signals to an internal circuit (not shown). 
     The first pixel storage unit MIMI 0  is disposed apart from the pixels Gr 0  and B 0  of the first column COL 0  in the column direction. The first comparison unit AMP 0  is disposed apart from the first pixel storage unit MIMI 0  in the column direction. The first amplification storage unit MIMO 0  is disposed apart from the first comparison unit AMP 0  in the column direction. 
     Prior to the description of a second column, a third column path corresponding to a third column COL 2  will now be described. 
     The third column path includes a third pixel storage unit MIMI 2 , a third transmission line CL 2 , a third comparison unit AMP 2 , a third input line IL 2 , a third feedback line FL 2 , a third amplification storage unit MIMO 2 , a third primary output line OTL 2 , and a third secondary output line OBL 2 . The third pixel storage unit MIMI 2  stores a third pixel signal outputted from pixels Gr 1  and B 1  of a third column COL 2 . The third transmission line CL 2  is extended in a column direction and transmits the third pixel signal outputted from the pixels Gr 1  and B 1  of the third column COL 2  to the third pixel storage unit MIMI 2 . The third comparison unit AMP 2 , disposed adjacent to the first comparison unit AMP 0  in the row direction, reads the third pixel signal stored in the third pixel storage unit MIMI 2  and generates third differential read signals, which are digital signals. The third input line IL 2  is extended in the column direction passing from the third column COL 2  to a second column COL 1  and transmits the third pixel signal stored in the third pixel storage unit MIMI 2  to the third comparison unit AMP 2 . The third feedback line FL 2  is extended in parallel with a part of the third input line IL 2  and feeds back a third primary read signal of the third differential read signals. The third amplification storage unit MIMO 2  is disposed adjacent to the first amplification storage unit MIMO 0  in the row direction and stores the third primary read signal. The third primary output line OTL 2  is extended in the column direction passing from the second column COL 1  to the third column COL 2  and transmits the third primary read signal to the third amplification storage unit MIMO 2 . The third secondary output line OBL 2  is extended in parallel with a part of the third primary output line OTL 2  and transmits a third secondary read signal of the third differential read signals to an internal circuit (not shown). 
     In other words, the third column path is extended along the third column COL 2  and is changed to the second column COL 1  after passing the third pixel storage unit MIMI 2 . Then, the third column path is extended along the second column COL 1  and is changed to the third column COL 2  again after passing the third comparison unit AMP 2 . Therefore, the third pixel storage unit MIMI 2  is disposed apart from the pixels Gr 1  and B 1  of the third column COL 2  in the column direction. The third comparison unit AMP 2  is disposed to be spaced apart from a second pixel storage unit MIMI 1 , which is described below, in the column direction. The third amplification storage unit MIMO 2  is disposed apart from a third comparison unit AMP 1 , which is described below, in the column direction. 
     The disposition order of the first input line IL 0  and the first feedback line FL 0  Is symmetrical to the disposition order of the third input line IL 2  and the third feedback line FL 2 . The disposition order of the first primary output line OTL 0  and the first secondary output line OBL 0  is symmetrical to the disposition order of the third primary output line OTL 2  and the third secondary output line OBL 2 . To be specific, the first and third feedback lines FL 0  and FL 2  are disposed closer to each other than the first and third input lines IL 0  and IL 2 , and the first and third secondary output lines OBL 0  and OBL 2  are disposed closer to each other than the first and third primary output lines OTL 0  and OTL 2 . 
     A second column path corresponding to a second column COL 1  will now be described. 
     The second column path includes a second pixel storage unit MIMI 1 , a second transmission line CL 1 , a second comparison unit AMP 1 , a second input line IL 1 , a second feedback line FL 1 , a second amplification storage unit MIMO 1 , a second primary output line OTL 1 , and a second secondary output line OBL 1 . The second pixel storage unit MIMI 1  stores a second pixel signal outputted from pixels R 0  and Gb 0  of a second column COL 1 . The second transmission line CL 1  is extended in a column direction and transmits the second pixel signal outputted from the pixels R 0  and Gb 0  of the second column COL 1  to the second pixel storage unit MIMI 1 . The second comparison unit AMP 1 , disposed adjacent to the third comparison unit AMP 2  in a row direction, reads the second pixel signal stored in the second pixel storage unit MIMI 1  and generates second differential read signals. The second input line IL 1  is extended in the column direction, passing from the second column COL 1  to a third column COL 2 , and transmits the second pixel signal stored in the second pixel storage unit MIMI 1  to the second comparison unit AMP 1 . The second feedback line FL 1  is extended in parallel with a part of the second input line IL 1  and feeds back a second primary read signal of the second differential read signals. The second amplification storage unit MIMO 1  is disposed adjacent to the first amplification storage unit MIMO 0  in the column direction and stores the second primary read signal. The second primary output line OTL 1  is extended in the column direction, passing from the third column COL 2  to the second column COL 1 , and transmits the second primary read signal to the second amplification storage unit MIMO 1 . The second secondary output line OBL 1  is extended in parallel with a part of the second primary output line OTL 1  and transmits a second secondary read signal of the second differential read signals to an internal circuit (not shown). 
     In other words, the second column path is extended along the second column COL 1  and is changed to the third column COL 2  after passing the second pixel storage unit MIMI 1 . Then, the third column path is extended along the third column COL 2  and is changed to the second column COL 1  again after passing the second comparison unit AMP 1 . Therefore, the second pixel storage unit MIMI 1  is disposed apart from the pixels R 0  and Gb 0  of the second column COL 1  in the column direction. The second comparison unit AMP 1  is disposed to be spaced apart from the third pixel storage unit MIMI 2  in the column direction. The second amplification storage unit MIMO 1  is disposed to be spaced apart from the third comparison unit AMP 2  in the column direction. 
     The second and third input lines IL 1  and IL 2  intersect once while being extended in parallel with each other, and the second and third output lines OTL 1  and OTL 2  intersect once while being extended in parallel with each other. 
     Finally, a fourth column path corresponding to a fourth column COL 3  will be described. 
     The fourth column path includes a fourth pixel storage unit MIMI 3 , a fourth transmission line CL 3 , a fourth comparison unit AMP 3 , a fourth input line IL 3 , a fourth feedback line FL 3 , a fourth amplification storage unit MIMO 3 , a fourth primary output line OTL 3 , and a fourth secondary output line OBL 3 . The fourth pixel storage unit MIMI 3  stores a fourth pixel signal outputted from pixels R 1  and Gb 1  of a fourth column COL 3 . The fourth transmission line CL 3  is extended in a column direction and transmits the fourth pixel signal outputted from the pixels R 1  and Gb 1  of the fourth column COL 3  to the fourth pixel storage unit MIMI 3 . The fourth comparison unit AMP 3 , disposed adjacent to the second comparison unit AMP 1  in a row direction, reads the fourth pixel signal stored in the fourth pixel storage unit MIMI 3  and generates fourth differential read signals. The fourth input line IL 3  is extended in the column direction and transmits the fourth pixel signal stored in the fourth pixel storage unit MIMI 3  to the fourth comparison unit AMP 3 . The fourth feedback line FL 3  is extended in parallel with the fourth input line IL 3  and feeds back a fourth primary read signal of the fourth differential read signals. The fourth amplification storage unit MIMO 3  is disposed adjacent to the second amplification storage unit MIMO 1  in the row direction and stores the fourth primary read signal. The fourth primary output line OTL 3  is extended in the column direction and transmits the fourth primary read signal to the fourth amplification storage unit MIMO 3 . The fourth secondary output line OBL 3  is extended in parallel with the fourth primary output line OTL 3  and transmits a fourth secondary read signal of the fourth differential read signals to an internal circuit (not shown). 
     The fourth pixel storage unit MIMI 3  is disposed apart from the pixels R 1  and Gb 1  of the fourth column COL 3  in the column direction. The fourth comparison unit AMP 3  is disposed apart from the fourth pixel storage unit MIMI 3  in the column direction. The fourth amplification storage unit MIMO 3  is disposed apart from the fourth comparison unit AMP 3  in the column direction. 
     The disposition order of the second input line IL 1  and the second feedback line FL 1  is symmetrical to the disposition order of the fourth input line IL 3  and the fourth feedback line FL 3 . The disposition order of the second primary output line OTL 1  and the second secondary output line OBL 1  is symmetrical to the disposition order of the fourth primary output line OTL 3  and the fourth secondary output line OBL 3 . To be specific, the second and fourth feedback lines FL 1  and FL 3  are disposed closer to each other than the second and fourth input lines IL 1  and IL 3 , and the second and fourth secondary output lines OBL 1  and OBL 3  are disposed closer to each other than the second and fourth primary output lines OTL 1  and OTL 3 . 
     Meanwhile, a shielding line SL is extended in the column direction at an interval of two column paths in the image sensing device. In other words, the image sensing device includes a first shielding line SL between the first column path and a column path adjacent to a left side of the first column path (not shown), a second shielding line SL between the second column path and the third column path, and a third shielding line SL between the fourth column path and a column path adjacent to a right side of the fourth column path (not shown). The second shielding line SL between the second column path and the third column path may be formed, corresponding to only a region where the second and third input lines IL 1  and IL 2  are extended in parallel with each other and a region where the second and third output lines OTL 1  and OTL 2  are extended in parallel with each other. 
       FIG. 4  is a circuit diagram illustrating in detail the column paths described above.  FIG. 4  illustrates only the first and third column paths corresponding to the first and third columns COL 0  and COL 2 , respectively. 
     Referring to  FIG. 4 , the first column path includes the first pixel storage unit MIMI 0 , the first comparison unit AMP 0 , and the first amplification storage unit MIMO 0 . The first pixel storage unit MIMI 0  includes a capacitor; the first comparison unit AMP 0  includes a differential amplifier; and the first amplification storage unit MIMO 0  includes a capacitor. The first comparison unit AMP 0  outputs first differential read signals Voutp 0  and Voutn 0  after drawing a comparison between a first ramp signal Vramp 0  transmitted through a first standard line RL 0  and a first pixel signal Vin 0  transmitted through the first input line IL 0 . The first standard line RL 0  is described for better understanding of the first comparison unit AMP 0  and is not shown in  FIG. 3 . 
     The first column path further includes a first feedback unit SW 0 . The first feedback unit SW 0  is coupled between the first feedback line FL 0  and the first input line IL 0  and applies the first primary read signal Voutp 0  to the first pixel signal Vin 0 . For example, the first feedback unit SW 0  includes a switch for selectively connecting the first feedback line FL 0  and the first input line IL 0  in response to a control signal (not shown). The first feedback unit SW 0  is described for better understanding of the feedback path and is not shown in  FIG. 3 . 
     As described above, the third column path includes the third pixel storage unit MIMI 2 , the third comparison unit AMP 2 , and the third amplification storage unit MIMO 2 . A description of the structure of the third column path is omitted since it is the same as that of the first column path. The order of signal lines may be symmetrical, and internal circuits may also be symmetrical in the first and third column paths. 
     The operation of the image sensing device having the above-described structure will now be described. 
     The rows of pixels of a pixel array AR are sequentially selected, and first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  outputted from the pixels of the selected row are transmitted through the first to fourth column paths, respectively. For example, when the first row ROW 0  is selected, the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  are outputted from the respective pixels Gr 0 , R 0 , Gr 1  and R 1  of the first row ROW 0 , and the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  are transmitted through the first to fourth column paths, respectively. 
     The process by which the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  are transmitted through the first to fourth column paths is as follows. 
     The first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3  store the first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  outputted from the pixel array AR. The first to fourth comparison units AMP 0 , AMP 1 , AMP 2  and AMP 3  generate the first to fourth differential read signals Voutp 0  and Voutn 0 , Voutp 1  and Voutn 1 , Voutp 2  and Voutn 2 , and Voutp 3  and Voutn 3  in response to the first to fourth pixel signals Vin 0 , Vin 1 , Vin 2  and Vin 3  stored in the first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3 . The first to fourth amplification storage units MIMO 0 , MIMO 1 , MIMO 2  and MIMO 3  store the first to fourth primary read signals Voutp 0 , Voutp 1 , Voutp 2  and Voutp 3 . The first to fourth feedback units SW 0 , SW 1 , SW 2  and SW 3  apply the first to fourth primary read signals Voutp 0 , Voutp 1 , Voutp 2  and Voutp 3  to the first to fourth pixel signals Vin 0 , Vin 1 , Vin 2  and Vin 3  in response to the control signal (not shown). 
     The first to fourth pixel signals Vpx 0 , Vpx 1 , Vpx 2  and Vpx 3  outputted from the pixel array AR are transmitted to the first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3  through the first to fourth transmission lines CL 0 , CL 1 , CL 2  and CL 3 . The first to fourth pixel signals Vin 0 , Vin 1 , Vin 2  and Vin 3  stored in the first to fourth pixel storage units MIMI 0 , MIMI 1 , MIMI 2  and MIMI 3  are transmitted to the first to fourth comparison units AMP 0 , AMP 1 , AMP 2  and AMP 3  through the first to fourth input lines IL 0 , IL 1 , IL 2  and IL 3 . The first to fourth primary read signals Voutp 0 , Voutp 1 , Voutp 2  and Voutp 3  are transmitted to the first to fourth amplification storage units MIMO 0 , MIMO 1 , MIMO 2  and MIMO 3  through the first to fourth primary output lines OTL 0 , OTL 1 , OTL 2  and OTL 3  and are transmitted simultaneously to the first to fourth feedback units SW 0 , SW 1 , SW 2  and SW 3  through the first to fourth feedback lines FL 0 , FL 1 , FL 2  and FL 3 . 
     The adjacent first and third feedback lines FL 0  and FL 2  may disable a parasitic capacitor incurred therebetween as the first and third primary read signals Voutp 0  and Voutp 2  that have similar characteristics are transmitted (refer to  FIG. 3 ). For example, a charge is not stored in a parasitic capacitor formed between the first and third feedback lines FL 0  and FL 2  as the first and third primary read signals Voutp 0  and Voutp 2 , which are generated from the pixel signals of the same color Gr 0  and Gr 1 , have the same dynamic range. Therefore, a coupling effect does not occur between the first and third feedback lines FL 0  and FL 2 . The coupling effect does not occur between the second and fourth feedback lines FL 1  and FL 3  because of the same reason as above. Furthermore, as the first and third secondary output lines OBL 0  and OBL 2  are disposed adjacent to each other, the coupling effect applied to the first and third primary output lines OTL 0  and OTL 2  is minimized. As the second and fourth secondary output lines OBL 1  and OBL 3  are disposed adjacent to each other, the coupling effect applied to the second and fourth primary output lines OTL 1  and OTL 3  is minimized. 
     In accordance with the embodiments of the present invention, the image sensing device has a structure where the coupling effect between signal lines is minimized and operational reliability of the image sensing device may be improved. 
     As signal lines having similar characteristics are disposed adjacent to each other, the interference, namely, the coupling effect between the signal lines may be minimized. 
     While the present invention has been described with respect to specific embodiments, it should be noted that the embodiments are for describing, not limiting, the present invention. Further, it should be noted that the present invention may be achieved in various ways through substitution, change, and modification by those skilled in the art without departing from the scope of the present invention as defined by the following claims.