Abstract:
Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device that includes a data input circuit that writes a plurality of write data sets that are supplied in serial to a memory cell array in parallel. 
         [0003]    2. Description of Related Art 
         [0004]    DRAM (Dynamic Random Access Memory) that is one of typical semiconductor storage devices generally includes a DLL (Delay Locked Loop) circuit to accurately perform high-speed data transfer with a memory controller. The DLL circuit generates a phase-controlled internal clock signal based on an external clock signal supplied from the memory controller. Because read data is output in synchronization with the phase-controlled internal clock signal, high-speed data transfer can be performed accurately. 
         [0005]    However, the DLL circuit consumes relatively large amounts of power. Therefore, especially DRAMs that are required to consume small amounts of power for use in mobile devices may not include a DLL circuit. In the DRAM of this type, read data that has been parallel-to-serial converted by using an internal clock signal not phase-controlled is output to outside without being phase-controlled. Even during a writing operation, write data that has been input in synchronization with a data strobe signal is serial-to-parallel converted by using an internal clock signal not phase-controlled (See Japanese Patent Application Laid-Open No. 2011-108300). 
         [0006]    Some of the DRAMs for mobile devices and the like adopt an edge-pad-type layout in which external terminals are arranged along two edges, that face each other, of a semiconductor chip. In this case, pads for command address signals are arranged along one edge of the two edges, and pads for data signals are arranged along the other edge of the two edges (See Japanese Patent Application Laid-Open No. 2011-108352). 
         [0007]    However, in a semiconductor device having an edge-pad-type layout, peripheral circuits that perform command address operations are disposed away from peripheral circuits that perform data transfer operations. As a result, the length of a signal line is very long to connect those peripheral circuits. Accordingly, the signal line has a relatively large parasitic capacitance. Therefore, a charge-and-discharge current to drive the signal line becomes larger, and the amount of current consumed is increased. 
       SUMMARY 
       [0008]    In one embodiment, there is provided a device that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other. 
         [0009]    In another embodiment, there is provided a device that includes: a first row of pads arranged in line and includes first and second pads that are configured to receive a first serial data signal and a first timing signal, respectively; a second row of pads arranged substantially in parallel to the first row of pads; an memory cell array being between the first and second rows of pads; a first control circuit configured to produce a plurality of second timing signals in response to the first timing signal; a first circuit configured to fetch the first serial data signal in response to the first timing signal and output a second serial data signal; and a second circuit configured to convert the second serial data signal to a parallel data signal in response to the second timing signals. 
         [0010]    In still another embodiment, there is provided a device that includes: a first terminal operatively receiving a first serial write data signal that includes first and second write data, each of the first and second write data being at least two bits; second and third terminals operatively receiving first and second data strobe signals, respectively, the first and second data strobe signals being complementary to each other; a control circuit operatively producing a plurality of internal data strobe signals in response to at least one of the first and second data strobe signals; a first data latch coupled to the first terminal at an input node thereof and including first and second latches that are connected in series between the input node thereof and an output node thereof, the first latch operatively responding to the first data strobe signal to fetch the first write data, and the second latch operatively responding to the second data strobe signal to produce a second serial write data signal at the output node of the first data latch, the second serial write data signal including the first write data; a second data latch coupled to the first terminal at an input node thereof and including a third latch coupled between the input node thereof and an output node thereof, the third latch operatively responding to the second data strobe signal to fetch the second write data and to produce the third serial write data signal at the output node of the second data latch, the third serial write data signal including the second write data; a first converter coupled to the output node of the first data latch and operatively responding to the internal data strobe signals to convert the second serial write data signal into a first parallel write data signal; and a second converter coupled to the output node of the second data latch and operatively responding to the internal data strobe signals to convert the third serial write data into a second parallel write data signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a schematic plane view illustrating a layout of a semiconductor device according to an embodiment of the present invention; 
           [0012]      FIG. 2  is a block diagram showing the circuit configuration of the semiconductor device shown in  FIG. 1 ; 
           [0013]      FIG. 3  is a diagram illustrating a signal path for an enable signal WEB and a timing signal WE 1 ; 
           [0014]      FIG. 4  is a circuit diagram showing major portions of a command decoder according to an embodiment of the invention; 
           [0015]      FIG. 5  is a circuit diagram showing a clock generating circuit according to an embodiment of the invention; 
           [0016]      FIG. 6  is a block diagram showing a part of a data input circuit and a part of a strobe control circuit according to an embodiment of the invention; 
           [0017]      FIG. 7  is a circuit diagram of a strobe input circuit according to an embodiment of the invention; 
           [0018]      FIG. 8  is a circuit diagram of a control signal generating circuit according to an embodiment of the invention; 
           [0019]      FIG. 9  is a circuit diagram of another control signal generating circuit according to an embodiment of the invention; 
           [0020]      FIG. 10  is a circuit diagram of a data input circuit according to an embodiment of the invention; 
           [0021]      FIG. 11  is a circuit diagram of a data latch circuit according to an embodiment of the invention; 
           [0022]      FIG. 12  is a circuit diagram of a serial-to-parallel conversion circuit according to an embodiment of the invention; 
           [0023]      FIG. 13  is a circuit diagram of a transfer circuit according to an embodiment of the invention; 
           [0024]      FIG. 14  is an operation waveform diagram for explaining the operation of the semiconductor device according to an embodiment, showing a case when a write command WRT is issued once; 
           [0025]      FIG. 15  is an operation waveform diagram for explaining the operation of the semiconductor device according to an embodiment, showing a case when two write commands WRT are successively issued; 
           [0026]      FIG. 16  is a circuit diagram of a prototype of a serial-to-parallel conversion circuit according to an embodiment of the invention; 
           [0027]      FIG. 17  is a circuit diagram of a write leveling circuit according to an embodiment of the invention that may be used with the serial-to-parallel conversion circuit shown in  FIG. 16 ; 
           [0028]      FIG. 18  is a circuit diagram of a control signal generating circuit according to an embodiment of the invention; and 
           [0029]      FIG. 19  is a circuit diagram of another control signal generating circuit according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0030]    Embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. 
         [0031]    Referring now to  FIG. 1 , an apparatus includes a semiconductor device  100  according to an embodiment of the present invention. As used herein, apparatus may refer to, for example, an integrated circuit, a memory device, a memory system, an electronic device or system, a smart phone, a tablet, a computer, a server, etc. The semiconductor device  10  may be integrated on a single silicon chip CP. A main surface of the silicon chip CP is in a quadrilateral shape; the main surface has a first side edge L 1  and a second side edge L 2  that are parallel to each other, and a third side edge L 3  and a fourth side edge L 4  that are perpendicular to the side edges L 1  and L 2  and are parallel to each other. The semiconductor device  10  of the present embodiment includes a first peripheral circuit region P 1  that is provided along the first side L 1 , and a second peripheral circuit region P 2  that is provided along the second side L 2 . A memory cell array MA is disposed between the first peripheral circuit region P 1  and the second peripheral circuit region P 2 . 
         [0032]    The first peripheral circuit region P 1  is a region in which a plurality of external terminals (Pads)  24  for command address signals shown in  FIG. 2 , and an access control circuit  20  that is related to the external terminals  24  are disposed. The external terminals  24  include clock terminals to which external clock signals CK_t and CK_c are supplied, command address terminals to which command address signals CA 0  to CA 9  are supplied, a chip select terminal to which a chip select signal CS is supplied, and a clock enable terminal to which a clock enable signal CKE is supplied. The access control circuit  20  includes an address latch circuit  21 , a command decoder  22 , and a clock generating circuit  23 . 
         [0033]    The second peripheral circuit region P 2  is a region in which a plurality of external terminals (Pads)  34  for data signals shown in  FIG. 2 , and a data control circuit  30  that is related to the external terminals  34  are disposed. The external terminals  34  include data terminals DQ 0  to DQ 31  which are used to output read data and input write data, and strobe terminals which are used to input and output strobe signals DQS 0   t  to DQS 3   t  and DQS 0   c  to DQS 3   c . The data control circuit  30  includes a data output circuit  31 , a data input circuit  32 , and a strobe control circuit  33 . 
         [0034]    The access control circuit  20  controls an operation of access to the memory cell array MA. For example, an address signal that is supplied from outside via the external terminals  24  is latched by the address latch circuit  21 , and is supplied to row decoders XDEC or column decoders YDEC shown in  FIG. 1 . As a result, a certain memory cell to be accessed in the memory cell array MA is specified. A command signal that is supplied from the outside via the external terminals  24  is decoded by the command decoder  22  to generate various internal signals. For example, if the command signal indicates a reading operation, the read data that is read out from a memory cell specified by the row decoders XDEC and column decoders YDEC is amplified by main amplifiers AMP, and is transferred to the data output circuit  31 . As a result, the read data that has been read out is output to the outside via the external terminals  34 . If the command signal indicates a writing operation, the write data that has been input from the outside via the external terminals  34  is supplied to the data input circuit  32 , and is transferred to the main amplifiers AMP. As a result, the write data is written into a memory cell specified by the row decoders XDEC and column decoders YDEC. 
         [0035]    As shown in  FIG. 1 , the first peripheral circuit region P 1  and the second peripheral circuit region P 2  are disposed along side edges L 1 , L 2  of the silicon chip CP that face each other. Therefore, a wiring distance of a signal line connecting the access control circuit  20  to the data control circuit  30  is very long.  FIG. 3  is a diagram illustrating this problem, showing a signal path for an enable signal WEB and a timing signal WE 1 , which are output from the command decoder  22 . As shown in  FIG. 3 , the enable signal WEB and the timing signal WE 1  are supplied to the data control circuit  30  via signal lines that are so disposed as to go across the memory cell array MA. The signal lines have a relatively large parasitic capacitance. Accordingly, there is a non-negligible time difference between when the command decoder  22  generates the enable signal WEB and the timing signal WE 1  and when the enable signal WEB and the timing signal WE 1  reach the data control circuit  30 . 
         [0036]      FIG. 4  illustrates a command decoder  22  according to an embodiment of the invention. The command decoder  22  includes a command signal generating circuit  40  that generates various internal signals based on the chip select signal CS and the command address signals CA 0  to CA 9 . Among the internal signals generated by the command signal generating circuit  40 ,  FIG. 4  shows an enable signal PWEB pertaining to the writing operation, a timing signal WE 1  and a write state signal WRITE, and a write leveling signal MDWLV pertaining to a write leveling operation. 
         [0037]    The operation of the command signal generating circuit  40  is performed in synchronization with internal clock signals PCLKR and PCLKF. The internal clock signals PCLKR and PCLKF are generated by the clock generating circuit  23  shown in  FIG. 2 .  FIG. 5  illustrates a clock generating circuit  23  according to an embodiment of the invention. As shown in  FIG. 5 , the clock generating circuit  23  includes a pair of receiver circuits  23   a  and  23   b  which receive complementary external clock signals CK_t and CK_c, and inverter circuits  23   c  and  23   d  which receive output signals of the receiver circuits  23   a  and  23   b . The output signals of the inverter circuits  23   c  and  23   d  are used as the internal clock signals PCLKR and PCLKF, respectively. The external clock signal CK_t is supplied to a non-inverting input node (+) of the receiver circuit  23   a , and the external clock signal CK_c is supplied to an inverting input node (−) of the receiver circuit  23   a . The external clock signal CK_c is supplied to a non-inverting input node (+) of the receiver circuit  23   b , and the external clock signal CK_t is supplied to an inverting input node (−) of the receiver circuit  23   b . Therefore, the waveform of the internal clock signal PCLKR is substantially identical to the waveform of the external clock signal CK_t. The waveform of the internal clock signal PCLKF is substantially identical to the waveform of the external clock signal CK_c. 
         [0038]    After a write command is issued, the command signal generating circuit  40  activates the write state signal WRITE to a high level, and, after a predetermined period of time has passed, the command signal generating circuit  40  changes the enable signal PWEB to a high level. According to the present embodiment, as shown in  FIG. 14 , if the write command WRT is issued in synchronization with an edge  0  of the internal clock signal PCLKR, the enable signal PWEB is activated to a high level during a period of time extending from next falling edge of an edge  3  of the internal clock signal PCLKR to next falling edge of an edge  5 . As shown in  FIG. 4 , the enable signal PWEB is supplied to a latch circuit  41 . The latch circuit  41  performs a latch operation in synchronization with a rising edge of the internal clock signal PCLKR. An output signal of the latch circuit  41  is supplied to one of the input nodes of a gate circuit G 1 . The other input node of the gate circuit G 1  is fixed to a high level except during the write leveling operation. Therefore, during a period of time when the enable signal PWEB is inactivated to a low level, the enable signal WEB is fixed to a high level. 
         [0039]    After the enable signal PWEB is activated to a high level, the enable signal WEB is changed to a low level in synchronization with a rising edge of the internal clock signal PCLKR. According to the present embodiment, as shown in  FIG. 14 , during a period of time from an edge  4  of the internal clock signal PCLKR to an edge  6 , the enable signal WEB is changed to a low level. Incidentally, the waveform of the enable signal WEB shown in  FIG. 14  is the waveform in the second peripheral circuit region P 2 . Since the signal is transmitted through the long signal line, there is a delay of Δt 1  relative to the waveform in the first peripheral circuit region P 1 . 
         [0040]    After the write command is issued, the command signal generating circuit  40  activates the timing signal WE 1  at a predetermined timing. According to the present embodiment, as shown in  FIG. 14 , the timing signal WE 1  is activated in synchronization with an edge  7  of the internal clock signal PCLKR. A delay circuit DLY 1  is inserted into a signal path of the timing signal WE 1 . Therefore, the activation timing of the timing signal WE 1  is slightly delayed relative to the edge  7  of the internal clock signal PCLKR. This configuration is intended to adjust the timing of a transfer operation in transfer circuit  100 R and  100 F, which will be described later. 
         [0041]      FIG. 6  is a block diagram showing a portion of the data input circuit  32  and a portion of the strobe control circuit  33  according to an embodiment of the invention.  FIG. 6  shows a portion of the data input circuit  32  that corresponds to the data terminals DQ 16  to DQ 23 , and a portion of the strobe control circuit  33  that corresponds to the strobe signals DQS 2   t  and DQS 2   c.    
         [0042]    As shown in  FIG. 6 , the timing signal WE 1 , the strobe signals DQS 2 , DQSB 2 , and DQSBD 0  to DQSBD 3  are supplied to the data input circuit  32  corresponding to the data terminals DQ 16  to DQ 23 . The strobe signals DQS 2 , DQSB 2 , and DQSBD 0  to DQSBD 3  are generated by the strobe control circuit  33 . As shown in  FIG. 6 , the strobe control circuit  33  includes a strobe input circuit  50  and control signal generating circuits  60  and  70 . The enable signal WEB is supplied to the strobe control circuit  33  via the long signal line. 
         [0043]    First, the circuit configuration of each of circuits constituting the strobe control circuit  33  will be described. 
         [0044]      FIG. 7  illustrates a strobe input circuit  50  according to an embodiment of the invention. As shown in  FIG. 7 , the strobe input circuit  50  has a circuit configuration similar to that of the clock generating circuit  23  shown in  FIG. 5 . That is, the strobe input circuit  50  includes a pair of receiver circuits  51  and  52  which receive data strobe signals DQS 2   —   t  and DQS 2   —   c , and inverter circuits  53  and  54  which receive outputs of the receiver circuits  51  and  52 . The output signals of the inverter circuits  53  and  54  are used as the strobe signals DQS 2  and DQSB 2 , respectively. The strobe signal DQS 2   —   t  is supplied to a non-inverting input node (+) of the receiver circuit  51 , and the strobe signal DQS 2   —   c  is supplied to an inverting input node (−) of the receiver circuit  51 . The strobe signal DQS 2   —   c  is supplied to a non-inverting input node (+) of the receiver circuit  52 , and the strobe signal DQS 2   —   t  is supplied to an inverting input node (−) of the receiver circuit  52 . Therefore, the waveform of the strobe signal DQS 2  is substantially identical to the waveform of the strobe signal DQS 2   —   t . The waveform of the strobe signal DQSB 2  is substantially identical to the waveform of the strobe signal DQS 2   —   c . Thus, the strobe signals DQS 2  and DQSB 2  can be considered the same as the strobe signals DQS 2   —   t  and DQS 2   —   c . Incidentally, the strobe signals DQS 2   —   t  and DQS 2   —   c  are assigned to the data terminals DQ 16  to DQ 23 . 
         [0045]      FIG. 8  illustrates a control signal generating circuit  60  according to an embodiment of the invention. As shown in  FIG. 8 , the control signal generating circuit  60  is a circuit in which either the strobe signal DQS 2  or DQSB 2  is delayed by a delay circuit DLY 2  and is output as a strobe signal DQSBD. During a normal operation except a write leveling operation, the strobe signal DQSB 2  is selected, and is delayed to generate the strobe signal DQSBD. During the write leveling operation, because a write leveling signal MDWLV is at a high level, the strobe signal DQS 2  is selected. An amount of delay by the delay circuit DLY 2  is Δt 2 . Accordingly, as shown in  FIG. 14 , the waveform of the strobe signal DQSBD is delayed by Δt 2  relative to the strobe signal DQSB 2 . The amount of delay Δt 2  by the delay circuit DLY 2  is designed based on the transmission delay amount Δt 1  of the enable signal WEB. 
         [0046]    The control signal generating circuit  70  receives the strobe signal DQSBD and the enable signal WEB to generate strobe signals DQSBD 0  to DQSBD 3 .  FIG. 9  illustrates control signal generating circuit  70  according to an embodiment of the invention. As shown in  FIG. 9 , the control signal generating circuit  70  includes a plurality of latch circuits  71  to  76 . Each of the latch circuits  71  to  76  performs a latch operation in synchronization with the strobe signal DQSBD. After the enable signal WEB is changed to a low level, an output signal of a gate circuit G 0  is sequentially transferred to the latch circuits  71 ,  73 ,  74 ,  75 , and  76  in that order. An output signal N 1  of the latch circuit  73  and an output signal N 2  of the latch circuit  75  are fed back to the latch circuit  71  as an output signal N 0  via the gate circuit G 2 , and are latched by the latch circuit  72 . The wiring shown in  FIG. 9  allows latch data of each of the latch circuits  71  to  76  to be supplied to a gate circuit G 3 . As a result, the strobe signals DQSBD 0  to DQSBD 3  are generated. The specific operation will be described with reference to  FIG. 14 . 
         [0047]    During the write leveling operation, the strobe signals DQSBD 1  to DQSBD 3  are fixed to a low level, and latch data of the latch circuit  73  is output through a gate circuit G 4  as write leveling data WLDATA. 
         [0048]    The above has described the circuit configuration of the strobe control circuit  33 . The following describes the circuit configuration of the data input circuit  32 . 
         [0049]      FIG. 10  is a circuit diagram of the data input circuit  32  according to an embodiment of the invention, showing one data input circuit  32  corresponding to the data terminals DQ 16  to DQ 23 . 
         [0050]    As shown in  FIG. 10 , the data input circuit  32  includes a data latch circuit  80 , serial-to-parallel conversion circuits  90 R and  90 F, and transfer circuits  100 R and  100 F. The data latch circuit  80  latches write data DQj (j=16 to 23) in synchronization with the strobe signals DQS 2  and DQSB 2 . Write data DQRj that is latched in synchronization with a rising edge of the strobe signal DQS 2  is transferred to the serial-to-parallel conversion circuit  90 R. Write data DQFj that is latched in synchronization with a rising edge of the strobe signal DQSB 2  (or a falling edge of the strobe signal DQS 2 ) is transferred to the serial-to-parallel conversion circuit  90 F. 
         [0051]    The serial-to-parallel conversion circuits  90 R and  90 F convert the serial write data DQRj and DQFj into parallel write data DQR 0  to DQRS and DQF 0  to DQF 3 , and transfer the parallel write data DQR 0  to DQRS and DQF 0  to DQF 3  to the transfer circuits  100 R and  100 F. In synchronization with the timing signal WE 1 , the transfer circuits  100 R and  100 F output the write data DQRA 0  to DQRA 3  and DQFA 0  to DQFA 3  to the memory cell array MA. Incidentally the serial-to-parallel conversion circuits  90 R and  90 F have the same circuit configuration. The transfer circuits  100 R and  100 F have the same circuit configuration. 
         [0052]      FIG. 11  illustrates data latch circuit  80  according to an embodiment of the invention. The data latch circuit  80  includes latch circuits  81  to  86  that transfer write data DQj, which are input in a serial manner via an input receiver RCV and a delay circuit DLY 3 . The input receiver RCV is a differential circuit that operates based on a difference in potential between the write data DQj and reference potential VREFDQ. An output signal of the input receiver RCV is supplied via the timing-adjusting delay circuit DLY 3  to the latch circuits  81  to  84  connected in series and to the latch circuits  85  and  86  connected in series. 
         [0053]    The latch circuit  81  captures an input signal during a period of time in which the strobe signal DQS 2  is at a low level, and keeps the captured input signal during a period of time in which the strobe signal DQS 2  is at a high level. The latch circuit  82  captures an input signal during a period of time in which the strobe signal DQS 2  is at a high level, and keeps the captured input signal during a period of time in which the strobe signal DQS 2  is at a low level. The latch circuits  83  and  85  capture an input signal during a period of time in which the strobe signal DQSB 2  is at a low level, and keep the captured input signal during a period of time in which the strobe signal DQSB 2  is at a high level. The latch circuits  84  and  86  capture an input signal during a period of time in which the strobe signal DQSB 2  is at a high level, and keep the captured input signal during a period of time in which the strobe signal DQSB 2  is at a low level. The write data DQRj and DQFj are respectively taken out from the latch circuits  84  and  86 . 
         [0054]    According to the above configuration, among the write data DQj that are input in a serial manner, those latched in synchronization with a rising edge of the strobe signal DQS 2  are output as write data DQRj; and those latched in synchronization with a rising edge of the strobe signal DQSB 2  are output as write data DQFj. Accordingly, the write data DQj having a data effective width of 0.5 clock cycle are converted into the write data DQRj and DQFj with a data effective width of 1 clock cycle. The write data DQRj and DQFj are supplied to the serial-to-parallel conversion circuits  90 R and  90 F shown in  FIG. 10 . 
         [0055]      FIG. 12  illustrates a serial-to-parallel conversion circuit  90 R according to an embodiment of the invention. The serial-to-parallel conversion circuit  90 R includes a delay circuit DLY 4  which delays the write data DQRj, and latch circuits  90 - 0  to  90 - 3  each of which performs a latch operation in synchronization with the strobe signals DQSBD 0  to DQSBD 3 . Furthermore, the serial-to-parallel conversion circuit  90 R includes a latch circuit  94  which latches an output signal of the delay circuit DLY 4  in synchronization with one of the strobe signals DQSBD 0  to DQSBD 2 . An output signal of the latch circuit  94  is supplied in common to the latch circuits  90 - 0  to  90 - 2 . The write data DQRj which do not pass through the latch circuit  94 , and output signals of the latch circuits  90 - 0  to  90 - 2  are supplied to the latch circuit  90 - 3  in a parallel manner. 
         [0056]    The latch circuit  90 - 3  includes first-stage latch circuits  91 - 0  to  91 - 3  and second-stage latch circuits  92 - 0  to  92 - 3 . The output signals of the latch circuits  90 - 0  to  90 - 2  are respectively supplied to the latch circuits  91 - 0  to  91 - 2 . The write data DQRj that does not pass through the latch circuit  94  is supplied to the latch circuit  91 - 3 . Moreover, the output signals of the latch circuits  91 - 0  to  91 - 3  are supplied to the latch circuits  93 - 0  to  93 - 3 . 
         [0057]    According to the above configuration, the write data DQRj that are input in a serial manner are sequentially latched by the different latch circuits in synchronization with the strobe signals DQSBD 0  to DQSBD 3 , and are output as parallel write data DQR 0  to DQR 3 . In this manner, the write data DQRj having a data effective width of one clock cycle are converted into parallel write data DQR 0  to DQR 3  having a data effective width of four clock cycles. The write data DQR 0  to DQR 3  are supplied to the transfer circuit  100 R shown in  FIG. 10 . 
         [0058]      FIG. 13  illustrates a transfer circuit  100 R according to an embodiment of the invention. The transfer circuit  100 R includes latch circuits  101  to  104  which perform a latch operation when the timing signal WE 1  is at a low level, and latch circuits  105  to  108  which perform a latch operation when the timing signal WE 1  is at a high level. The latch circuits  101  and  105  are connected in series, and capture the write data DQR 0  to output as write data DQRA 0 . Similarly, the latch circuits  102  and  106 ,  103  and  107 , and  104  and  108  are connected in series, and capture the write data DQR 1  to DQR 3  to output as write data DQRA 1  to DQRA 3 . According to this configuration, the parallel write data DQR 0  to DQR 3  are output as write data DQRA 0  to DQRA 3  in synchronization with a rising edge of the timing signal WE 1 , and the write data DQRA 0  to DQRA 3  are transferred to the memory cell array MA. As a result, an actual writing operation for the memory cell array MA will be performed. 
         [0059]    The above has described the circuit configuration of the semiconductor device  10  according to the present embodiment. The following describes operation of the semiconductor device  10  according to the present embodiment. 
         [0060]    In the example shown in  FIG. 14 , the write command WRT is issued in synchronization with an edge  0  of the clock signal PCLKR. After two clock cycles have passed, a clocking of the strobe signals DQS 2  and DQSB 2  starts. After a one-clock-cycle preamble period has passed, a burst inputting of the write data DQj starts. Accordingly, the data latch circuit  80  shown in  FIG. 11  separates the write data DQj into rise-side write data DQRj and fall-side write data DQFj. During this operation, the write data DQj having a data effective width of 0.5 clock cycle are converted into the write data DQRj and DQFj having a data effective width of 1 clock cycle. 
         [0061]    In response to the clocking of the strobe signal DQSB 2 , the control signal generating circuit  60  shown in  FIG. 8  generates the strobe signal DQSBD whose phase is delayed by the amount Δt 2  relative to the strobe signal DQSB 2 . The control signal generating circuit  60  supplies the strobe signal DQSBD to the control signal generating circuit  70 . 
         [0062]    The command decoder  22  shown in  FIG. 4  changes, in synchronization with an edge  4  of the clock signal PCLKR, the enable signal WEB to a low level. The change in the enable signal WEB is conveyed to the control signal generating circuit  70  via the long-distance wire that goes across the memory cell array MA. Therefore, the transmission delay time t 1  is required for the change to be conveyed to the control signal generating circuit  70  after the command decoder  22  has changed the enable signal WEB to a low level. 
         [0063]    After the enable signal WEB is changed to a low level, the clocking of the strobe signal DQSBD 0  is stopped. The strobe signals DQSBD 1 , DQSBD 2 , and DQSBD 3  become activated in that order at intervals of one clock cycle. In this manner, the serial write data DQRj having a data effective width of one clock cycle are converted by the serial-to-parallel conversion circuit  90 R into a parallel format or 4-bit-width parallel write data DQR 0  to DQR 3 . Although not shown in  FIG. 14 , the write data DQFj are converted by the serial-to-parallel conversion circuit  90 F into a parallel format or 4-bit-width parallel write data DQF 0  to DQF 3 . 
         [0064]    After that, the parallel write data DQR 0  to DQR 3  are transferred from the transfer circuit  100  R to the memory cell array MA in response to the activation of the timing signal WE 1 . Although not shown in  FIG. 14 , the parallel write data DQF 0  to DQF 3  are transferred by the transfer circuit  100 F to the memory cell array MA in response to the activation of the timing signal WE 1 . In that manner, the eight-bit write data DQj that are supplied from the outside in a serial manner are written into a memory cell specified by the address signal in a parallel manner. 
         [0065]    In the above-described writing operation, the clocking is performed just once for the enable signal WEB that should be supplied from the command decoder  22  to the data input circuit  32  via the long signal line. Therefore, an amount of current consumed by a change in the enable signal WEB can be significantly reduced. Moreover, the timing at which the enable signal WEB is changed to a low level may satisfy a standard value of setup time tDSS and a standard value of hold time tDSH as shown in  FIG. 14 . According to the present embodiment, if the delay time Δt 2  is appropriately designed with respect to the transmission delay time Δt 1 , it is possible to accurately adjust the setup time tDSS and the hold time tDSH. Thus, even if the frequency of the clock signal is high, the standard values can be satisfied. 
         [0066]    If the write commands are successively issued, as shown in  FIG. 15 , the above-described operation is repeatedly performed.  FIG. 15  also shows the waveform of the output signal NO shown in  FIG. 9 . As shown in  FIG. 15 , at the timing when edges T 2  and T 3  of the strobe signal DQSBD occur, the output signal N 0  is at a high level. Therefore, during this period, the timing of the enable signal WEB does not make any sense. The timing of the enable signal WEB makes sense during a period of time in which the output signal N 0  is at a low level. The above-described setup time tDSS and hold time tDSH are determined based on the timing of the enable signal WEB and strobe signal DQSBD during this period. 
         [0067]    The characteristics are actually affected by a time difference between the timing at which the changing of the enable signal WEB to a low level reaches the data input circuit and a rising edge of the strobe signal DQSBD. More specifically, based on a period of time from when the edge T 0  (T 4 ) of the strobe signal DQSBD emerges to when the enable signal WEB is changed to a low level, the setup time tDSS is defined. Based on a period of time from when the enable signal WEB is changed to a low level to when the edge T 1  (T 5 ) of the strobe signal DQSBD emerges, the hold time tDSH is defined. Meanwhile, a period of time from when the edge T 1  of the strobe signal DQSBD emerges to when the enable signal WEB is changed to a high level is defined as setup time tDSS′, a period of time from when the enable signal WEB is changed to a high level to when the edge T 4  of the strobe signal DQSBD emerges is defined as hold time tDSH′. As shown in  FIG. 15 , sufficient margins are given to those periods as shown in  FIG. 15 . As described above, it is unnecessary to care about the relationship between the edges T 2  and T 3  of the strobe signal DQSBD and the enable signal WEB. 
         [0068]    An embodiment of the serial-to-parallel conversion circuit  90 X shown in  FIG. 16  includes a delay circuit DLY 4  which delays write data DQRj, and latch circuits  95 ,  96 ,  97 - 0  to  97 - 3 , and  98 - 0  to  98 - 3 . The latch circuit  95  performs a latch operation when the strobe signal DQSBD is at a low level. The latch circuit  96  performs a latch operation when the strobe signal DQSBD is at a high level. Accordingly, the delayed write data DQRj is captured in synchronization with a rising edge of the strobe signal DQSBD. 
         [0069]    The write data DQRj that are output from the latch circuit  96  are supplied to the eight latch circuits  97 - 0  to  97 - 3  and  98 - 0  to  98 - 3  which are connected in cascade. The latch circuits  97 - 0  to  97 - 3  and  98 - 0  to  98 - 3  are circuits that operate in synchronization with the clock signal PCLKD supplied from the command decoder  22 . The latch circuits  97 - 0  to  97 - 3  perform a latch operation when the clock signal PCLKD is at a low level. The latch circuits  98 - 0  to  98 - 3  perform a latch operation when the clock signal PCLKD is at a high level. Therefore, output signals of the latch circuit  96  are sequentially latched in synchronization with a rising edge of the clock signal PCLKD. 
         [0070]    According to the above configuration, the first write data DQRj output from the latch circuit  96  pass through the eight latch circuits ( 97 - 3  to  98 - 0 ) before being output as write data DQR 0 . The second write data DQRj output from the latch circuit  96  pass through the six latch circuits ( 97 - 3  to  98 - 1 ) before being output as write data DQR 1 . The third write data DQRj output from the latch circuit  96  pass through the four latch circuits ( 97 - 3  to  98 - 2 ) before being output as write data DQR 2 . The last write data DQRj output from the latch circuit  96  pass through the two latch circuits ( 97 - 3  and  98 - 3 ) before being output as write data DQR 3 . In this manner, the serial-to-parallel conversion is carried out. 
         [0071]    When the above serial-to-parallel conversion circuit  90 X is used, the command decoder  22  may constantly carry out the clocking of the clock signal PCLKD during the writing operation. As in the case of the enable signal WEB, the clock signal PCLKD is a signal that is supplied from the command decoder  22  to the data input circuit  32  via the long-distance wire. Therefore, the constant clocking of the clock signal PCLKD leads to an increase in the amount of current consumed due to the charging and discharging of the long-distance wire. According to the semiconductor device  10  of the above-described present embodiment, there is no need to use a signal that requires a constant clocking during the writing operation. Therefore, the amount of current consumed by the charging and discharging of the long-distance wire therefore can be reduced according to the semiconductor device  10 . 
         [0072]    In the serial-to-parallel conversion circuit  90 X shown in  FIG. 16 , all the eight latch circuits  97 - 0  to  97 - 3  and  98 - 0  to  98 - 3  operate in response to the clock signal PCLKD, thereby consuming a relatively large amount of operation current. In the case of the serial-to-parallel conversion circuit  90 R shown in  FIG. 12 , latch circuits may operate in response to the strobe signals DQSBD 0  to DQSBD 3  that become sequentially activated. Therefore, the amount of current consumed by the latch circuits can be reduced, too. 
         [0073]    In the prototype of the serial-to-parallel conversion circuit  90 X shown in  FIG. 16 , even if the delay time Δt 2  is appropriately designed with respect to the transmission delay time Δt 1 , the setup margin and the hold margin are decreased by effects of variations in the characteristics of each latch circuit because there a large number of latch circuits  97 - 0  to  97 - 3  and  98 - 0  to  98 - 3  that operate in synchronization with the clock signal PCLKD. In the semiconductor device  10  of the above-described present embodiment, it is the latch circuit  71  shown in  FIG. 9  that receives the enable signal WEB. The strobe signals DQSBD 1  to DQSBD 3  which are sequentially activated in response to the receiving of the enable signal WEB are in synchronization with the strobe signal DQSBD. Therefore, the deterioration of the setup margin and hold margin associated with variations in the characteristics does not occur. 
         [0074]    Incidentally, in the prototype of the serial-to-parallel conversion circuit  90 X, the write data DQR 0  to DQR 3  that have been converted into a parallel format are in synchronization with the clock signal PCLKD. Meanwhile, in the serial-to-parallel conversion circuit  90 R of the present embodiment, the write data DQR 0  to DQR 3  that have been converted into a parallel format are not in synchronization with the clock signal PCLKD. Therefore, according to the present embodiment, the write data may be reloaded onto the clock signal from the strobe signal in the transfer circuit  100 R. However, the write data DQR 0  to DQR 3  that are supplied to the transfer circuit  100 R have an expanded data effective width of four clock cycles as a result of the parallel conversion. Thus, a sufficient operation margin can be secured for the reloading, and the deterioration of the characteristics therefore does not occur.  FIG. 15  shows the setup time tS and hold time tH of the transfer circuit  100 R, proving that a sufficient margin is secured. 
         [0075]      FIG. 17  illustrates a write leveling circuit  110  according to an embodiment of the invention. The write leveling circuit  110  is activated when the write leveling signal MDWLV is at a high level. The write leveling circuit  110  latches the clock signal PCLKD in synchronization with the strobe signal DQSBD to generate write leveling data WLDATA which represents a timing skew. The write leveling circuit  110  shown in  FIG. 17  is used to measure an operation timing of the serial-to-parallel conversion circuit  90 X shown in  FIG. 16 . However, the two circuits are different, and have different circuit configurations. As a result, it is difficult to accurately measure a timing skew, and a non-negligible error might occur. 
         [0076]    Meanwhile, according to the present embodiment, the serial-to-parallel conversion circuit  90 R includes a write leveling function, and can measure a timing skew by using an actual path. Therefore, very accurate measurement results can be obtained. 
         [0077]    Incidentally, once a series of writing operations is ended, levels of the strobe signals DQS 2  and DQSB 2  are not guaranteed by the specifications. Therefore, as indicated by reference symbol A in  FIG. 15 , a ringing might occur in the strobe signals DQS 2  and DQSB 2 . Even if the ringing occurs, it is desirable that the data input circuit  32  have a circuit configuration that does not malfunction. To realize this, control signal generating circuits  70 A and  70 B shown in  FIGS. 18 and 19  may be used. 
         [0078]    The control signal generating circuits  70 A and  70 B shown in  FIGS. 18 and 19  are different from the control signal generating circuit  70  shown in  FIG. 9  in that the control signal generating circuits  70 A and  70 B have a different circuitry portion that generates the strobe signal DQSBD 3 .  FIG. 18  illustrates a control signal generating circuit  70 A according to an embodiment of the invention. The control signal generating circuit  70 A shown in  FIG. 18  is made by removing the latch circuit  76  from the control signal generating circuit  70  shown in  FIG. 9 , and an output signal DQSBD 3 EB of the latch circuit  75  is supplied to the control signal generating circuit  70 B.  FIG. 19  illustrates a control signal generating circuit  70 B according to an embodiment of the invention. The control signal generating circuit  70 B includes a latch circuit  77  that latches the output signal DQSBD 3 EB in synchronization with the strobe signal DQSBD; an output signal thereof is supplied to a set terminal S of a SR latch circuit  78  via a gate circuit G 5 . Therefore, a strobe signal DQSBD 3  output from the SR latch circuit  78  is fixed to a high level. 
         [0079]    An output signal of a gate circuit G 6  that receives the enable signal WEB and the write state signal WRITE is supplied to a reset terminal R of the SR latch circuit  78 . Accordingly, until the write state signal WRITE becomes inactivated to a low level due to an issuing of a read command or like, or until the enable signal WEB is changed to a low level in the next writing operation, the logic level of the strobe signal DQSBD 3  is fixed to a high level. Therefore, even when a ringing occurs in the strobe signals DQS 2  and DQSB 2 , there is no change in the strobe signal DQSBD 3 . Thus, even if incorrect data is conveyed due to the ringing, the conveying is stopped by the latch circuit  90 - 3  shown in  FIG. 12 . Therefore, the malfunctioning does not occur. 
         [0080]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.