Abstract:
Machine-readable media, methods, and apparatus are described to monitor and throttle issuance of transactions. In some embodiments, transactions are monitored during a monitoring window based upon cycle type. In response to determining that a threshold has been exceeded during the monitoring window, issuance of transactions during a throttling window are limited to a budget. Further, transactions issued during the throttling window consume a portion of the budget that based upon their cycle type.

Description:
BACKGROUND  
         [0001]    Thermal specifications of computer system components may define the maximum temperature at which the component may break down, may slow down, or may fail. The temperature of a component may depend upon usage. For example, the temperature of a memory controller and/or a memory device may depend upon the rate at which the memory controller accesses the memory device. While a memory controller and a memory device may support for example a peak transfer rate of 800 MB/s, the memory controller and memory device in certain environments may be able to support a sustained transfer rate of only 500 MB/s without exceeding their thermal limits. In some computer systems, the memory controller may access the memory devices in bursts up to the peak transfer rate (e.g. 800 MB/s) but may limit or throttle accesses to the memory devices to maintain less than a supported sustained transfer rate (e.g. 500 MB/s) in order to guard against overheating.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0002]    The invention described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.  
         [0003]    [0003]FIG. 1 illustrates an embodiment of a computing device.  
         [0004]    [0004]FIG. 2 illustrates an embodiment of a memory controller of the computing device of FIG. 1.  
         [0005]    [0005]FIG. 3 illustrates monitoring periods and throttling periods of the memory controller of FIG. 2.  
         [0006]    [0006]FIG. 4 illustrates an embodiment of a method that may be used by the memory controller of FIG. 2 to maintain thermal specifications via transaction throttling.  
     
    
     DETAILED DESCRIPTION  
       [0007]    The following description describes techniques that attempt to satisfy thermal requirements of computer system components. In the following description, numerous specific details such as logic implementations, opcodes, means to specify operands, resource partitioning/sharing/duplication implementations, types and interrelationships of system components, and logic partitioning/integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.  
         [0008]    References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every-embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.  
         [0009]    Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.  
         [0010]    An example embodiment of a computing device  100  is shown in FIG. 1. The computing device  100  may comprise one or more processors  102 . The processors  102  may perform actions in response to executing instructions. For example, the processors  102  may issue transactions such as memory read transactions and memory write transactions on the processor bus  104 .  
         [0011]    The computing device  100  may further comprise a chipset  106 . The chipset  106  may comprise one or more integrated circuit packages or chips that couple the processors  102  to memory  108 , Basic Input/Output System (BIOS) firmware  110  and other components  112  (e.g. a mouse, keyboard, video controller, hard disk, floppy disk, etc.). The chipset  106  may comprise a processor bus interface  114  to receive transactions from the processors  102  and issue transactions to the processors  102  via the processor bus  104 . The chipset  106  may further comprise a memory controller  116  to issue read and write transactions to the memory  108  via a memory bus  118 . The chipset  106  may further comprise one or more component interfaces (not shown) to access the other components  112  via buses  120  such as, for example, peripheral component interconnect (PCI) buses, accelerated graphics port (AGP) buses, universal serial bus (USB) buses, low pin count (LPC) buses, and/or other I/O buses.  
         [0012]    In one embodiment, the BIOS firmware  110  may comprise routines which the computing device  100  executes during system startup in order to initialize the processors  102 , chipset  106 , and other components of the computing device  100 . Moreover, the BIOS firmware  110  may comprise routines or drivers which the computing device  100  may execute to communicate with one or more components of the computing device  100 .  
         [0013]    The memory  108  may comprise memory devices having addressable storage locations that the memory controller  1   16  may read data from and/or write data to. The memory  108  may comprise one or more different types of memory devices such as, for example, dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, double data rate (DDR) SDRAM devices, quad data rate (QDR) SDRAM devices, or other volatile or non-volatile memory devices.  
         [0014]    Moreover, the memory  108  may be arranged in a hierarchal manner. For example, the memory  108  may be arranged in channels, ranks, banks, pages, and columns. In particular, each channel may comprise one or more ranks, each rank may comprise one or more banks, and each bank may comprise one or more pages. Further, each page may comprise one or more columns. When accessing memory, the memory controller  116  may open a page of the memory  108  and then may access one or more columns of the opened page. For a page-hit access, the memory controller  116  may leave a page open after accessing a column of the page for a previous memory request and may access a different column of the open page. For a page-miss access, the memory controller  116  may close an open page of a bank, may open another page of the same bank, and may access a column of the newly opened page. A page-miss access generally consumes more power and therefore has a greater thermal impact than a page-hit access. For a page-empty access, the memory controller may open a closed page of a bank, and may access a column of the newly opened page for the memory transaction. A page-empty access generally consumes more power than a page-hit access but less power than a page-miss access. Accordingly, a page-empty generally has a greater thermal impact than a page-hit access but a lesser thermal impact than a page-miss access.  
         [0015]    As depicted in FIG. 2, the memory controller  116  may comprise a read buffer  200 , a write buffer  202 , an arbiter  204 , and a memory interface  206 . The read buffer  200  may buffer the address and data of a read transaction until the requested data is retrieved from the memory  108  and returned to the requester (e.g. processor  102 ). Similarly, the write buffer  202  may buffer the address and data of a write transaction until the data is written to the memory  108 . The read buffer  200  and write buffer  202  may each support buffering of one or more transactions.  
         [0016]    The arbiter  204  may select a transaction from the buffers  200 ,  202  based upon various criteria and may request the memory interface  206  to service the selected transaction. The memory interface  206  may issue one or more commands on the memory bus  118  in order to retrieve data from the memory  108  in response to servicing a read transaction. Similarly, the memory interface  206  may issue one or more commands on the memory bus  118  in order to store data to the memory  108  in response to servicing a write transaction. In particular, the memory interface  206  may decode an address of a transaction and may apply memory select signals to the memory in order to open pages of the memory  108  for reading and/or writing.  
         [0017]    The arbiter  204  may further comprise throttling logic  208 . The throttling logic  208  may monitor thermal specifications of the memory controller  116  and/or memory  108  based upon cycle types of transactions serviced by the memory interface  206 . In particular, as depicted in FIG. 3, the throttling logic  208  may monitor transactions during monitoring periods (e.g. MP 1 , MP 2 ) based upon a threshold T and may throttle transactions during throttling periods (e.g. TP 1 ) based upon a budget B. As depicted, each monitoring period may comprise one or more monitoring windows (e.g. MW 1 , MW 2 ). Similarly, each throttling period may comprise one or more throttling windows (e.g. TW 1 , TW 2  . . . TWN). In one embodiment, the throttling logic  208  may transition from a monitoring period to a throttling period in response to a threshold count exceeding a threshold. Further, the throttling logic  208  may transition from a throttling period to a monitoring period after a throttling period which may be defined by a timer, a number of throttling windows, or some other mechanism.  
         [0018]    In one embodiment, the throttling logic  208  may maintain a threshold count during each monitor window that is representative of the thermal effect of the transactions during the window. Transactions of different cycle types may have different thermal effects. The throttling logic  208 , therefore, may update the threshold count based upon cycle types of the transactions. For example, a read page hit may have less of a thermal impact than a read page miss. The throttling logic  208  accordingly may update the threshold count by a larger amount for a read page miss than a read page hit. Transactions of different cycle lengths may also have different thermal effects. For example, a 32 byte read may have less of a thermal impact than a 64 byte read. The throttling logic  208  may therefore update the threshold count by a larger amount for a 64 byte read than for a 32 byte read. Example count values are shown in following TABLE 1. It should be appreciated however that the count values are merely illustrative and that count values may differ from platform to platform. In particular, appropriate count values for a given platform may be determined from lab tests without undue experimentation.  
                           TABLE 1                       CYCLE LENGTH   CYCLE TYPE   POWER VALUE   COUNT VALUE                   32B   Read Page-Hit   Prd   Ox62H       64B   Read Page-Hit     2 * Prd   OxC4H       32B   Read Page-Empty   1.2 * Prd   Ox76H       64B   Read Page-Empty   2.2 * Prd   OxD8H       32B   Read Page-Miss   1.6 * Prd   Ox9DH       64B   Read Page-Miss   2.6 * Prd   OxFFH       32B   Write Page-Hit   Prd   Ox62H       64B   Write Page-Hit     2 * Prd   OxC4H       32B   Write Page-Empty   1.2 * Prd   Ox76H       64B   Write Page-Empty   2.2 * Prd   OxD8H       32B   Write Page-Miss   1.6 * Prd   Ox9DH       64B   Write Page-Miss   2.6 * Prd   OxFFH                  
 
         [0019]    In one embodiment, the BIOS firmware  110  or some other mechanism of the computing device such as, for example, an operating system may provide interfaces and routines for defining the count values for cycle type and cycle length combinations. Moreover, the BIOS firmware  110  may provide interfaces and routines for defining the threshold for the monitoring windows, the budget for the throttling windows, the duration of the monitoring windows, the duration of the throttling window, and the duration of the throttling period. Due to its programmability, the same or similar throttling logic  208  may be incorporated into a variety of different platforms to provide adequate transaction throttling.  
         [0020]    Referring now to FIG. 4, a method of throttling transactions based on cycle types is depicted. In block  300 , the throttling logic  208  may initialize a monitoring window duration and a threshold count for a new monitoring window. In one embodiment, the throttling logic  208  may initialize the threshold count by clearing a counter or setting a register equal to zero in response to entering the new monitoring window. In another embodiment, the throttling logic  208  may initialize the threshold count by loading a counter or a register with an initial value based upon the threshold T of the monitoring window.  
         [0021]    The arbiter  204  in block  302  may select a transaction from the buffers  200 ,  202  and provide the selected transaction to the memory interface  206  for servicing. In block  304 , the throttling logic  208  may determine a cycle type and a cycle length for the selected transaction. For example, the throttling logic  208  may determine whether the selected transaction is a read page-hit, read page-empty, a read page-miss, a write page-hit, write page-empty, or a write page-miss transaction based upon the address of the selected transaction and the addresses of one or more transactions previously serviced by the memory interface  206 . In block  306 , the throttling logic may update the threshold count for the monitoring window based upon the determined cycle type and cycle length of the selected transaction. In one embodiment, the throttling logic  208  may increment the threshold count with the count value associated with the cycle type and the cycle length of the selected transaction. In another embodiment, the throttling logic  208  may decrement the threshold count with the appropriate count value for the selected transaction.  
         [0022]    In block  308 , the throttling logic  208  may determine whether the monitoring window has expired based upon a monitoring window timer or some other mechanism used to track the monitoring window duration. For example, the throttling logic  208  may determine that the monitoring window has expired in response to a clock cycle counter overflowing, underflowing, or containing a count value having a predetermined relationship (e.g. greater than) to a cycle count that defines the monitor window duration. In response to determining that the monitoring window has not expired, the throttling logic  208  may return to block  302  in order to select another transaction for the memory interface  206  to service during the current monitoring window.  
         [0023]    Otherwise, in response to determining that the monitoring window has expired, the throttling logic  208  in block  310  may determine whether to exit the current monitoring period and enter a throttling period. In one embodiment, the throttling logic  208  may determine whether to enter a throttling period or to initiate a new monitoring window based upon whether the threshold count indicates the threshold T has been exceeded for the current monitoring window. In response to determining not to enter the throttling period, the throttling logic  208  may return to block  300  to initialize a new monitoring window. Otherwise, the throttling logic  208  may continue to block  312  to initialize a new throttling window.  
         [0024]    In block  312 , the throttling logic  208  may set the throttling window duration and may initialize a budget count for a new throttling window. In one embodiment, the throttling logic  208  may initialize the budget count by clearing a counter or setting a register equal to zero in response to entering the new throttling window. In another embodiment, the throttling logic  208  may initialize the budget count by loading a counter or a register with an initial value based upon the budget B of the throttling window.  
         [0025]    The arbiter  204  in block  314  may select a transaction from the buffers  200 ,  202  and provide the selected transaction to the memory interface  206  for servicing. In block  316 , the throttling logic  208  may determine a cycle type and a cycle length for the selected transaction. For example, the throttling logic  208  may determine whether the selected transaction is a read page-hit, read page-empty, a read page-miss, a write page-hit, write page-empty, or a write page-miss transaction based upon the address of the selected transaction and one or more transactions previously issued by the memory interface  206 . In block  318 , the throttling logic may update the budget count for the throttling window based upon the determined cycle type and cycle length of the selected transaction. In one embodiment, the throttling logic  208  may increment the budget, count with the count value associated with the determined cycle type and the cycle length of the selected transaction. In another embodiment, the throttling logic  208  may decrement the budget count with the appropriate count value for the selected transaction.  
         [0026]    In block  320 , the throttling logic  208  may determine whether the throttling window has expired based upon a throttling window timer or some other mechanism used to track the throttling window duration. For example, the throttling logic  208  may determine that the throttling window has expired in response to a clock cycle counter overflowing, underflowing, or containing a count value having a predetermined relationship (e.g. greater than) to a cycle count that defines the throttling window duration.  
         [0027]    In response to determining that the throttling window has not expired, the throttling logic  208  in block  322  may determine whether to allow the arbiter  204  to provide the memory interface  206  with further transactions during the remainder of the current throttling window. In one embodiment, the throttling logic  208  may determine to prevent further transactions during the throttling window in response to determining that a budget for the throttling window has been exhausted based upon the budget count having a predetermined relationship (e.g. greater than) to the budget. In response to determining that the arbiter  204  may select further transactions for the throttling window, the throttling logic  208  may return to block  314 . Otherwise, the throttling logic  208  may return to block  320  to determine whether the throttling window has expired.  
         [0028]    In response to determining that the throttling window has expired, the throttling logic  208  in block  324  may determine whether to exit the throttling period and enter a monitoring period. In block  324 , the throttling logic  208  may determine whether the throttling period has expired based upon a throttling period timer or some other mechanism used to track the throttling period duration. For example, the throttling logic  208  may determine that the throttling period has expired in response to a throttling window counter overflowing, underflowing, or containing a count value having a predetermined relationship (e.g. greater than) to a throttling window count that defines the throttling period duration.  
         [0029]    In response to determining that the throttling period has expired, the throttling logic  208  may return to block  300  to initiate another monitoring window. Otherwise, the throttling logic  208  in block  322  may return to block  312  to initiate another throttling window of the current throttling period.  
         [0030]    The example of FIG. 3 illustrates a monitoring period MP 1  that comprises two monitoring windows MW 1 , MW 2  and a throttling period TP 1  that comprises N throttling windows TW 1 , TW 2  . . . TWN. In one embodiment, the the monitoring windows MW 1 , MW 2  have a duration of about 1 second and the throttling windows TW 1 , Tw 2  . . . TWN each have a duration of 10 microseconds. In general, the duration of each throttling window TW 1 , TW 2  . . . TWN is kept relatively short to prevent long periods in which transactions are not serviced. Such long periods may result in what appears to be a non-responsive or sluggish system to a user of the computing device  100 .  
         [0031]    As shown, the threshold count in the example of FIG. 3 did not exceed the threshold T during the first monitoring window MW 1 . As a result, the throttling logic  208  initiated the second monitoring window MW 2 . During the second monitoring window MW 2 , the threshold count exceeded the threshold T. Therefore, the throttling logic  208  initiated a throttling period TP 1  having N throttling windows TW 1 , TW 2  . . . TWN. During throttling windows TW 1 , TW 4  and TWN, the budget count reached the budget B prior to the completion of the respective throttling window. The throttling logic  208  accordingly prevented servicing of transaction during the remainder of these throttling windows thereby ensuring that the sustained power consumption rate during each throttling windows TW 1 , TW 2  . . . TWN is below a level need to maintain thermal specifications for the memory controller  116  or the memory  108 .  
         [0032]    While certain features of the invention have been described with reference to example embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the example embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.