Abstract:
The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing ( 10 ) a VHDL description of the digital circuit design, performing ( 12 ) a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating ( 14 ) a netlist including the elements of the digital circuit design and the connections between said elements. Said method comprises the further steps of providing ( 28 ) a transformation script with at least one transparent storage element ( 40; 54 ), wherein said transparent storage element ( 40; 54 ) represents a path delay within the digital circuit design, creating ( 30 ) a new netlist with the at least one transparent storage elements ( 40; 54 ), running ( 20 ) a verification, and checking, if the new netlist is clean from a logical and timing point of view.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. 
         [0003]    2. Description of the Related Art 
         [0004]    In the development of a digital circuit design a simulation process is performed in order to verify the correct logical function and timing behavior. It is very important, that the model of the digital circuit design comprises correct runtimes of the signals. The simulation process may be performed by the support of an appropriate hardware and/or software. 
         [0005]    According to the prior art the principle for validating the correct logical function and timing behavior of a circuit design comprises substantially the three following parts. In a first part only the logical function of said digital circuit design is validated. In a second part the timing behavior of said digital circuit design is validated. A timing analysis is performed in a third part. The functional validation on the one hand and the timing validation on the other hand are completely independent from each other. 
         [0006]      FIG. 6  illustrates a flow chart diagram of a method for validating the logical function according to the prior art. The shown method refers to an RTL (Register Transfer Level) description, for example as a netlist description. In a first step  10  a model of a desired digital circuit design is provided. Said model is written in a Very High Speed Integrated Circuit hardware description language (VHDL). In a second step  12  a logic synthesis is performed. By this logic synthesis the abstract form of the digital circuit design is turned into a design implementation in terms of logic gates. The logic synthesis uses first assertions  24 . 
         [0007]    In a next step  14  a netlist is created. The netlist includes the elements of the digital circuit design and the connections between said elements. In particular, the netlist contains the information of those storage elements, which are provided for the real hardware. During a further step  16  a timing analysis is performed. The timing analysis uses second assertions  26 . The result is checked in a step  17 . If the result is not OK, then the method returns back to step  10  again. If the result is OK, then in a step  18  is shown that the netlist is clean from a timing point of view. 
         [0008]    The steps  10 ,  12 ,  14 ,  16 ,  17  and  18  are used for the timing driven synthesis, the timing analysis and the release. 
         [0009]    In a next step  20  a verification of the digital circuit design is performed. In the verification of step  20  the VHDL from the step  10  and the netlist from step  14  are used. The result is checked in a step  21 . If the result is OK, then in a step  22  is shown that the netlist is clean from a logical and timing point of view. 
         [0010]    The steps  10 ,  12 ,  14 ,  16 ,  17 ,  18 ,  20 ,  21  and  22  are used for the verification of RTL design description. 
         [0011]    The logical function of the digital circuit design is validated within a cycle based environment on the basis of the RTL design description. 
         [0012]    This approach according to the prior art has the disadvantage, that the timing assertions are not validated. Therefore timing problems could still exist and must be solved by a new release. 
       OBJECT OF THE INVENTION 
       [0013]    It is an object of the present invention to provide an improved method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. 
       SUMMARY OF THE INVENTION 
       [0014]    The above object is achieved by a method as laid out in the independent claims. Further advantageous embodiments of the present invention are described in the dependent claims and are taught in the description below. 
         [0015]    The advantages of the invention are achieved by inserting a number of transparent storage elements for the simulation process. Said transparent storage elements generate delays of the runtimes for the signals. The transparent storage elements are inserted only for the simulation process, but are not arranged in the real hardware. However, in the proper simulation process the inserted storage elements are not transparent and are recognized by the system. 
         [0016]    The transparent storage elements may represent a path delay between two or more storage elements and/or a path delay of a combinatorial logic circuit. 
         [0017]    The number of the inserted transparent storage elements depends on the timing assertions to be verified. The runtimes of the signals may be represented during the logic simulation. Thus, any corresponding violations of timing assertions may be recognized already in the simulation process. It is not required that the test cases have to be adapted for the verification of the timing assertions. 
         [0018]    The present invention allows validating timing constraints of a digital circuit design within a cycle based verification environment. 
         [0019]    In a preferred embodiment of the present invention a tools flow is provided in order to perform the transformation automatically. By the inventive method major timing assertions may be modeled and checked via verification. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above as well as additional objectives, features and advantages of the present invention will be apparent in the following detailed written description. 
           [0021]    The novel and inventive features believed characteristics of the invention are set forth in the appended claims. The invention itself, their preferred embodiments and advantages thereof will be best understood by reference to the following detailed description of preferred embodiments in conjunction with the accompanied drawings, wherein: 
           [0022]      FIG. 1  illustrates a flowchart diagram of a method according to a preferred embodiment of the present invention, 
           [0023]      FIG. 2  illustrates a schematic diagram of a netlist for a first example according to the preferred embodiment of the present invention, 
           [0024]      FIG. 3  illustrates a schematic diagram of a new netlist for the first example according to the preferred embodiment of the present invention, 
           [0025]      FIG. 4  illustrates a schematic diagram of a netlist for a second example according to the preferred embodiment of the present invention, 
           [0026]      FIG. 5  illustrates a schematic diagram of a new netlist for the second example according to the preferred embodiment of the present invention, and 
           [0027]      FIG. 6  illustrates a flowchart diagram of a method according to the prior art. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0028]      FIG. 1  illustrates a flowchart diagram of a method according to a preferred embodiment of the present invention. In a first step  10  a model of a desired digital circuit design is provided. Said model is written in a very high speed integrated circuit hardware description language (VHDL). In a second step  12  a logic synthesis is performed. By this logic synthesis the abstract form of the digital circuit design is turned into a design implementation in terms of logic gates. The logic synthesis uses first assertions  24 . In the logic synthesis an RTL design description is created. The logic synthesis uses assertions  24 . 
         [0029]    In a next step  14  a netlist is created. The netlist includes the elements of the digital circuit design and the connections between said elements. In particular, the netlist contains the information of those storage elements, which are provided for the real hardware. During a further step  16  a timing analysis is performed. The timing analysis uses second assertions  26 . The result is checked in a step  17 . If the result is not OK, then the method returns back to step  10  again. If the result is OK, then in a step  18  is shown that the netlist is clean from a timing point of view. 
         [0030]    The steps  10 ,  12 ,  14 ,  16 ,  17  and  18  are used for the timing driven synthesis, the timing analysis and the release. 
         [0031]    In a step  28  a transformation script is created on the basis of the netlist from the step  14  and the second assertions  26 . For example, the assertions “don&#39;t care”, “multi cycle” and “adjust” could be transformed. By the transformation transparent storage elements are introduced. The required number of said transparent storage elements depends on the multi cycle values, the adjust values, the cycle times and the best guesses. The transformation will be applied to internal paths between the storage elements. The transformation will be further applied to off-chip-nets. 
         [0032]    By the transformation script from the step  28  a new netlist is created in a step  30 . The new netlist contains the transparent storage elements. The transparent storage element delays the signal by one clock cycle. The delay of the transparent storage element corresponds with the path delay of a combinatorial logic circuit. 
         [0033]    In a next step  20  a verification of the digital circuit design is running. In the verification of step  20  the VHDL from the step  10  and the netlist from step  14  and from step  28  are used. The result is checked in a step  21 . If the result is OK, then in a step  22  is shown that the netlist is clean from a logical and timing point of view. 
         [0034]    The steps  10 ,  12 ,  14 ,  16 ,  17 ,  18 ,  20 ,  21  and  22  are used for the register transfer logic (RTL) verification. The steps  10 ,  12 ,  14 ,  20  and  22  are used for the netlist verification. 
         [0035]      FIG. 2  illustrates a schematic diagram of a netlist for a first example according to the preferred embodiment of the present invention. A combinatorial logic circuit  32  is interconnected between a first storage element  34  and a second storage element  36 . The first storage element  34  and the second storage element  36  are provided with a clock signal Clk. 
         [0036]    The signal from the first storage element  34  via the combinatorial logic circuit  32  to the second storage element  36  has a runtime of one and a half clock cycle times. This runtime is contained in the netlist as a corresponding path delay  38 . 
         [0037]    The following table illustrates the functional timing of the storage elements  34  and  36 . 
         [0000]    
       
         
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Clock cycle 
               
             
          
           
               
                   
                 0 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
               
               
                   
                   
               
             
          
           
               
                 First storage element 
                 x 
                 D1 
                 D1 
                 D2 
                 D2 
                 D3 
                 D3 
               
               
                 Second storage element 
                 x 
                 x 
                 x 
                 D1 
                 x 
                 D2 
                 x 
               
               
                   
               
             
          
         
       
     
         [0038]    The first line of the table contains the numbers of the clock cycles. In the second line of the table the state of the first storage element  34  is shown. The state of the second storage element  36  is shown in the third line. 
         [0039]      FIG. 3  illustrates a schematic diagram of a new netlist for the first example according to the preferred embodiment of the present invention. The new netlist includes the first storage element  34  and the second storage element  36 . The first storage element  34  and the second storage element  36  are interconnected via a transparent storage element  40 . The storage elements  34  and  36  as well as the transparent storage element  40  are provided with the clock signal Clk. The transparent storage element  40  is only in the new netlist for the simulation process, but not in any other netlist provided for realizing the hardware. 
         [0040]    The transparent storage element  40  causes a time delay, which corresponds with the path delay  38  of the combinatorial logic circuit  32 . In this example the transparent storage element  40  causes a time delay of one clock cycle. The transparent storage element  40  is only present in the new netlist, which is modified for the verification. However, the transparent storage element  40  is not present in a netlist distinct for a physical release process. 
         [0041]      FIG. 4  illustrates a schematic diagram of a netlist for a second example of the preferred embodiment of the present invention. The second example includes the first storage element  34  and the second storage element  36 . Further, the second example includes a third storage element  42  and a fourth storage element  44 . The first storage element  34  and the second storage element  36  are interconnected via the first combinatorial logic circuit  32 . The first storage element  34  and the third storage element  42  are interconnected via a second combinatorial logic circuit  46 . The first storage element  34  and the fourth storage element  44  are interconnected via a third combinatorial logic circuit  48 . 
         [0042]    The signals from the first storage element  34  via the combinatorial logic circuits  32 ,  46  and  48  to the further storage elements  36 ,  42  and  44  have generally different runtimes. The combinatorial logic circuits  32 ,  46  and  48  cause corresponding path delays  38 ,  50  and  52 , respectively. 
         [0043]      FIG. 5  illustrates a schematic diagram of a new netlist for the second example of the preferred embodiment of the present invention. The new netlist of the second example includes the storage elements  34 ,  36 ,  42 ,  44  and the combinatorial logic circuits  32 ,  46  and  48 . The storage elements  34 ,  36 ,  42 ,  44  and the combinatorial logic circuits  32 ,  46 ,  48  are connected together in the same way as in  FIG. 4 . Additionally, a transparent storage element  54  is interconnected between the first storage element  34  and the combinatorial logic circuits  32 ,  46  and  48 . 
         [0044]    If not all path delays are equal, then further transparent storage elements are inserted into the corresponding paths. 
         [0045]      FIG. 6  illustrates a flowchart diagram of a method according to the prior art. Similar or identical steps have the same numbers as in  FIG. 1 . In the first step  10  the model of the desired digital circuit design is provided. Said model is written in a very high speed integrated circuit hardware description language (VHDL). In the second step  12  the logic synthesis is performed. By this logic synthesis the abstract form of the digital circuit design is turned into the design implementation in terms of logic gates. The logic synthesis uses first assertions  24 . 
         [0046]    In the next step  14  the netlist is created. The netlist includes the elements of the digital circuit design and the connections between said elements. In particular, the netlist contains the information of those storage elements, which are provided for the real hardware. During the step  16  the timing analysis is performed. The timing analysis uses second assertions  26 . The result is checked in the step  17 . If the result is not OK, then the method returns back to step  10  again. If the result is OK, then in the step  18  is shown that the netlist is clean from a timing point of view. 
         [0047]    The steps  10 ,  12 ,  14 ,  16 ,  17  and  18  are used for the timing driven synthesis, the timing analysis and the release. 
         [0048]    In the next step  20  the verification of the digital circuit design is performed. In the verification of step  20  the VHDL from the step  10  and the netlist from step  14  are used. The result is checked in the step  21 . If the result is OK, then in the step  22  is shown that the netlist is clean from a logical point of view. 
         [0049]    The steps  10 ,  12 ,  14 ,  16 ,  17 ,  18 ,  20 ,  21  and  22  are used for the register transfer logic (RTL) and netlist verification. 
         [0050]    Unlike the method according to the present invention the new netlist with the transparent storage elements is not created. The path delays cannot be considered by this method according to the prior art. 
         [0051]    The present invention allows that major assertions may be modeled and checked via verification. The inventive method closes the loop between timing driven synthesis, timing analysis and fast cycle based logic verification. The cell count of the released netlist is not increased by the inventive method, since the updates are done only within that netlist used for verification. 
         [0052]    The transformation of the netlist may be automated in an easy way. On the bases of the assertion description a script generates a new verification netlist. 
         [0053]    The inventive method is a key saving factor, since the unchecked assertion cases are reduced and the quality is therefore improved. This implies a reduced overall turnaround time with less releases. 
         [0054]    The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein. Further, when loaded in computer system, said computer program product is able to carry out these methods. 
         [0055]    Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be performed therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims. 
       LIST OF REFERENCE NUMERALS 
       [0000]    
       
           10  step of providing a VHDL 
           12  step of logic synthesis 
           14  step of creating a netlist 
           16  step of timing analysis 
           17  step of checking a first result 
           18  step of showing the first result 
           20  step of running the verification 
           21  step of checking a second result 
           22  step of showing the second result 
           24  step of providing first assertions 
           26  step of providing second assertions 
           28  step of providing a transformation script 
           30  step of providing a new netlist 
           32  first combinatorial logic circuit 
           34  first storage element 
           36  second storage element 
           38  first path delay 
           40  transparent storage element 
           42  third storage element 
           44  fourth storage element 
           46  second combinatorial logic circuit 
           48  third combinatorial logic circuit 
           50  second path delay 
           52  third path delay 
         Clk clock signal