Abstract:
A semiconductor device includes a fin-shaped semiconductor layer on a surface of a semiconductor substrate having a longitudinal axis extending in a first direction parallel to the surface. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer. A pillar diameter of the bottom of the pillar-shaped semiconductor layer is equal to a fin width of the top of the fin-shaped semiconductor layer, the pillar diameter and the fin width parallel to the surface. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped semiconductor layer.

Description:
RELATED APPLICATIONS 
       [0001]    This application is continuation-in-part application of U.S. patent application Ser. No. 14/061,082 filed Oct. 23, 2013, which is a divisional application of U.S. patent application Ser. No. 13/666,445 filed Nov. 1, 2012, which, pursuant to 35 U.S.C. §119(e), claims the benefit of U.S. Provisional Application No. 61/557,501 filed Nov. 9, 2011. The entire disclosures of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are increasing in integration. With increases in integration, MOS transistors used in the integrated circuits are increasingly made finer up to a nano region. Finer MOS transistors have the problem of difficulty in suppressing leak currents and difficulty in decreasing the areas occupied by circuits because of the demand for securing necessary amounts of currents. In order to resolve the problem, there have been proposed surrounding gate transistors (SGT) having a structure in which a source, a gate, and a drain are disposed in a direction vertical to a substrate, and the gate surrounds a pillar-shaped semiconductor layer (for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761). 
         [0006]    By using a metal for a gate electrode instead of using polysilicon, depletion can be suppressed, and the resistance of the gate electrode can be decreased. However, a manufacturing process after a metal gate is formed must be one in which metal contamination by the metal gate is always taken into consideration. 
         [0007]    In addition, in order to satisfy both a metal gate process and a high-temperature process for usual MOS transistors, a metal gate last process is used for actual products, in which a metal gate is formed after a high-temperature process (IEDM 2007 K. Mistry, et. al., pp. 247-250). The gate is formed using polysilicon, and then an interlayer insulating film is deposited. Then, the polysilicon gate is exposed by chemical mechanical polishing and etched, followed by deposition of a metal. Therefore, in order to satisfy both the metal gate process and the high-temperature process, the metal gate last process must be used for SGT, in which a metal gate is formed after the high-temperature process. Since, in the SGT, the upper surface of the pillar-shaped semiconductor layer is higher than the gate, some consideration is required for using the metal gate last process. 
         [0008]    In addition, usual MOS transistors use a first insulating film in order to decrease a parasitic capacitance between gate wiring and a substrate. For example, in FINFET (IEDM 2010 CC. Wu, et. al., 27.1.1-27.1.4.), a first insulating film is formed around a fin-shaped semiconductor layer and then etched back to expose the fin-shaped semiconductor layer, thereby decreasing the parasitic capacitance between the gate wiring and the substrate. Also, in SGT, the first insulating film must be used for decreasing the parasitic capacitance between the gate wiring and the substrate. The SGT includes the pillar-shaped semiconductor layer in addition to the fin-shaped semiconductor layer, and thus some consideration is required for forming the pillar-shaped semiconductor layer. 
       SUMMARY 
       [0009]    Accordingly, an object is to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure. 
         [0010]    In one embodiment a semiconductor device includes a fin-shaped semiconductor layer on a surface of a semiconductor substrate, the fin-shaped semiconductor layer having a longitudinal axis extending in a first direction parallel to the surface; 
         [0011]    a first insulating film around the fin-shaped semiconductor layer; 
         [0012]    a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer, a pillar diameter of the bottom of the pillar-shaped semiconductor layer being equal to a fin width of the top of the fin-shaped semiconductor layer, the pillar diameter and the fin width parallel to the surface; 
         [0013]    a gate insulating film around the pillar-shaped semiconductor layer; 
         [0014]    a metal gate electrode around the gate insulating film; and 
         [0015]    a metal gate wiring connected to the metal gate electrode, the metal gate wiring having a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped semiconductor layer. 
         [0016]    A method for manufacturing a semiconductor device of the present invention includes: 
         [0017]    a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate, forming a first insulating film around the fin-shaped semiconductor layer, and forming a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer, the width of the pillar-shaped semiconductor layer being equal to the width of the fin-shaped semiconductor layer; 
         [0018]    a second step of, after the first step, forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped semiconductor layer, and a lower portion of the pillar-shaped silicon layer; 
         [0019]    a third step of, after the second step, forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring so that the gate insulating film covers the periphery and the top of the pillar-shaped silicon layer, the polysilicon gate electrode covers the gate insulating film, and after the polysilicon gate electrode and the polysilicon gate wiring are formed, the upper surface of polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer; 
         [0020]    a fourth step of, after the third step, forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped semiconductor layer; 
         [0021]    a fifth step of, after the fourth step, depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring, the metal gate wiring being connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped semiconductor layer; and 
         [0022]    a sixth step of, after the fifth step, forming a contact so as to make direct contact between the contact and the diffusion layer in the upper portion of the pillar-shaped silicon layer. 
         [0023]    The manufacturing method is also characterized in that a first resist is formed for forming the fin-shaped semiconductor layer on the semiconductor substrate; the semiconductor substrate is etched to form the fin-shaped semiconductor layer and the first resist is removed; the first insulating film is deposited around the fin-shaped semiconductor layer and then etched back to expose an upper portion of the fin-shaped semiconductor layer; a second resist is formed to be perpendicular to the fin-shaped semiconductor layer; the fin-shaped semiconductor layer is etched; and then the second resist is removed to form the pillar-shaped semiconductor layer so that a portion where the fin-shaped semiconductor layer and the second resist intersect at right angles becomes the pillar-shaped silicon layer. 
         [0024]    The manufacturing method is further characterized in that in a structure including the fin-shaped semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-shaped semiconductor layer, and the pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, a second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched to be left as a side wall, the diffusion layers are formed by impurity implantation in an upper portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer, and the first nitride film and the second oxide film are removed, followed by heat treatment. 
         [0025]    The manufacturing method is further characterized in that in a structure including the fin-shaped semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-shaped semiconductor layer, the pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, the diffusion layer formed in the upper portion of the fin-shaped semiconductor layer and in the lower portion of the pillar-shaped silicon layer, and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, the gate insulating film is formed, polysilicon is deposited and then planarized so that after planarization, the upper surface of the polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, a second nitride film is deposited, a third resist is formed for forming the polysilicon gate electrode and the polysilicon gate wiring, the second nitride film is etched, the polysilicon is etched to form the polysilicon gate electrode and the polysilicon gate wiring, the gate insulating film is etched, and the third resist is removed. 
         [0026]    The manufacturing method is further characterized in that a third nitride film is deposited and then etched to be left as a side wall, and a metal is deposited to form a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped semiconductor layer. 
         [0027]    The manufacturing method is further characterized in that a fourth nitride film is deposited, the interlayer insulating film is deposited and then planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, a metal is filled in a portion from which the polysilicon gate electrode and the polysilicon gate wiring have been removed, and the metal is etched to expose the gate insulating film on the diffusion layer in the upper portion of the pillar-shaped silicon layer, thereby forming the metal gate electrode and the metal gate wiring. 
         [0028]    A semiconductor device of the present invention includes: a fin-shaped semiconductor layer formed on a semiconductor substrate; a first insulating film formed around the fin-shaped semiconductor layer; a pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, the width of the pillar-shaped semiconductor layer being equal to the width of the fin-shaped semiconductor layer; a diffusion layer formed in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped silicon layer; a diffusion layer formed in an upper portion of the pillar-shaped silicon layer; a silicide formed in an upper portion of the diffusion layer in the upper portion of the fin-shaped semiconductor layer; a gate insulating film formed around the pillar-shaped silicon layer; a metal gate electrode formed around the gate insulating film: a metal gate wiring connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped semiconductor layer; and a contact formed on the diffusion layer formed in the upper portion of the pillar-shaped semiconductor layer so as to make direct contact between the contact and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer. 
         [0029]    According to the present invention, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure. 
         [0030]    The fin-shaped semiconductor layer, the first insulating film, and the pillar-shaped semiconductor layer are formed based on a conventional FINFET manufacturing method and thus can be easily formed. 
         [0031]    In addition, a silicide is generally formed in an upper portion of the pillar-shaped silicon layer, but the silicide must be formed after a polysilicon gate is formed because the deposition temperature of polysilicon is higher than the silicide formation temperature. 
         [0032]    Therefore, when the silicide is formed in an upper portion of a silicon column, a hole is formed on a polysilicon gate electrode after the polysilicon gate is formed, the silicide is formed after a side wall composed of an insulating film is formed on the side wall of the hole, and then the hole is filled with an insulating film, thereby causing the problem of increasing the number of manufacturing steps. Therefore, the diffusion layers are formed before the polysilicon gate electrode and the polysilicon gate wiring are formed, the pillar-shaped semiconductor layer is covered with the polysilicon gate electrode, and the silicide is formed only in an upper portion of the fin-shaped semiconductor layer. Therefore, a usual metal gate last manufacturing method can be used, in which a gate is formed using polysilicon, the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and then etched, and then a metal is deposited, thereby facilitating the formation of metal gate SGT. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0033]      FIG. 1A  is a plan view of a semiconductor device according to the present invention,  FIG. 1B  is a sectional view taken along line X-X′ in  FIG. 1A , and  FIG. 1C  is a sectional view taken along line Y-Y′ in  FIG. 1A . 
           [0034]      FIG. 2A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 2B  is a sectional view taken along line X-X′ in  FIG. 2A , and  FIG. 2C  is a sectional view taken along line Y-Y′ in  FIG. 2A . 
           [0035]      FIG. 3A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 3B  is a sectional view taken along line X-X′ in  FIG. 3A , and  FIG. 3C  is a sectional view taken along line Y-Y′ in  FIG. 3A . 
           [0036]      FIG. 4A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 4B  is a sectional view taken along line X-X′ in  FIG. 4A , and  FIG. 4C  is a sectional view taken along line Y-Y′ in  FIG. 4A . 
           [0037]      FIG. 5A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 5B  is a sectional view taken along line X-X′ in  FIG. 5A , and  FIG. 5C  is a sectional view taken along line Y-Y′ in  FIG. 5A . 
           [0038]      FIG. 6A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 6B  is a sectional view taken along line X-X′ in  FIG. 6A , and  FIG. 6C  is a sectional view taken along line Y-Y′ in  FIG. 6A . 
           [0039]      FIG. 7A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 7B  is a sectional view taken along line X-X′ in  FIG. 7A , and  FIG. 7C  is a sectional view taken along line Y-Y′ in  FIG. 7A . 
           [0040]      FIG. 8A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 8B  is a sectional view taken along line X-X′ in  FIG. 8A , and  FIG. 8C  is a sectional view taken along line Y-Y′ in  FIG. 8A . 
           [0041]      FIG. 9A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 9B  is a sectional view taken along line X-X′ in  FIG. 9A , and  FIG. 9C  is a sectional view taken along line Y-Y′ in  FIG. 9A . 
           [0042]      FIG. 10A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 10B  is a sectional view taken along line X-X′ in  FIG. 10A , and  FIG. 10C  is a sectional view taken along line Y-Y′ in  FIG. 10A . 
           [0043]      FIG. 11A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 11B  is a sectional view taken along line X-X′ in  FIG. 11A , and  FIG. 11C  is a sectional view taken along line Y-Y′ in  FIG. 11A . 
           [0044]      FIG. 12A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 12B  is a sectional view taken along line X-X′ in  FIG. 12A , and  FIG. 12C  is a sectional view taken along line Y-Y′ in  FIG. 12A . 
           [0045]      FIG. 13A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 13B  is a sectional view taken along line X-X′ in  FIG. 13A , and  FIG. 13C  is a sectional view taken along line Y-Y′ in  FIG. 13A . 
           [0046]      FIG. 14A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 14B  is a sectional view taken along line X-X′ in  FIG. 14A , and  FIG. 14C  is a sectional view taken along line Y-Y′ in  FIG. 14A . 
           [0047]      FIG. 15A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 15B  is a sectional view taken along line X-X′ in  FIG. 15A , and  FIG. 15C  is a sectional view taken along line Y-Y′ in  FIG. 15A . 
           [0048]      FIG. 16A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 16B  is a sectional view taken along line X-X′ in  FIG. 16A , and  FIG. 16C  is a sectional view taken along line Y-Y′ in  FIG. 16A . 
           [0049]      FIG. 17A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 17B  is a sectional view taken along line X-X′ in  FIG. 17A , and  FIG. 17C  is a sectional view taken along line Y-Y′ in  FIG. 17A . 
           [0050]      FIG. 18A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 18B  is a sectional view taken along line X-X′ in  FIG. 18A , and  FIG. 18C  is a sectional view taken along line Y-Y′ in  FIG. 18A . 
           [0051]      FIG. 19A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 19B  is a sectional view taken along line X-X′ in  FIG. 19A , and  FIG. 19C  is a sectional view taken along line Y-Y′ in  FIG. 19A . 
           [0052]      FIG. 20A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 20B  is a sectional view taken along line X-X′ in  FIG. 20A , and  FIG. 20C  is a sectional view taken along line Y-Y′ in  FIG. 20A . 
           [0053]      FIG. 21A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 21B  is a sectional view taken along line X-X′ in  FIG. 21A , and  FIG. 21C  is a sectional view taken along line Y-Y′ in  FIG. 21A . 
           [0054]      FIG. 22A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 22B  is a sectional view taken along line X-X′ in  FIG. 22A , and  FIG. 22C  is a sectional view taken along line Y-Y′ in  FIG. 22A . 
           [0055]      FIG. 23A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 23B  is a sectional view taken along line X-X′ in  FIG. 23A , and  FIG. 23C  is a sectional view taken along line Y-Y′ in  FIG. 23A . 
           [0056]      FIG. 24A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 24B  is a sectional view taken along line X-X′ in  FIG. 24A , and  FIG. 24C  is a sectional view taken along line Y-Y′ in  FIG. 24A . 
           [0057]      FIG. 25A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 25B  is a sectional view taken along line X-X′ in  FIG. 25A , and  FIG. 25C  is a sectional view taken along line Y-Y′ in  FIG. 25A . 
           [0058]      FIG. 26A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 26B  is a sectional view taken along line X-X′ in  FIG. 26A , and  FIG. 26C  is a sectional view taken along line Y-Y′ in  FIG. 26A . 
           [0059]      FIG. 27A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 27B  is a sectional view taken along line X-X′ in  FIG. 27A , and  FIG. 27C  is a sectional view taken along line Y-Y′ in  FIG. 27A . 
           [0060]      FIG. 28A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 28B  is a sectional view taken along line X-X′ in  FIG. 28A , and  FIG. 28C  is a sectional view taken along line Y-Y′ in  FIG. 28A . 
           [0061]      FIG. 29A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 29B  is a sectional view taken along line X-X′ in  FIG. 29A , and  FIG. 29C  is a sectional view taken along line Y-Y′ in  FIG. 29A . 
           [0062]      FIG. 30A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 30B  is a sectional view taken along line X-X′ in  FIG. 30A , and  FIG. 30C  is a sectional view taken along line Y-Y′ in  FIG. 30A . 
           [0063]      FIG. 31A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 31B  is a sectional view taken along line X-X′ in  FIG. 31A , and  FIG. 31C  is a sectional view taken along line Y-Y′ in  FIG. 31A . 
           [0064]      FIG. 32A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 32B  is a sectional view taken along line X-X′ in  FIG. 32A , and  FIG. 32C  is a sectional view taken along line Y-Y′ in  FIG. 32A . 
           [0065]      FIG. 33A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 33B  is a sectional view taken along line X-X′ in  FIG. 33A , and  FIG. 33C  is a sectional view taken along line Y-Y′ in  FIG. 33A . 
           [0066]      FIG. 34A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 34B  is a sectional view taken along line X-X′ in  FIG. 34A , and  FIG. 34C  is a sectional view taken along line Y-Y′ in  FIG. 34A . 
           [0067]      FIG. 35A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 35B  is a sectional view taken along line X-X′ in  FIG. 35A , and  FIG. 35C  is a sectional view taken along line Y-Y′ in  FIG. 35A . 
           [0068]      FIG. 36A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 36B  is a sectional view taken along line X-X′ in  FIG. 36A , and  FIG. 36C  is a sectional view taken along line Y-Y′ in  FIG. 36A . 
           [0069]      FIG. 37A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 37B  is a sectional view taken along line X-X′ in  FIG. 37A , and  FIG. 37C  is a sectional view taken along line Y-Y′ in  FIG. 37A . 
           [0070]      FIG. 38A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 38B  is a sectional view taken along line X-X′ in  FIG. 38A , and  FIG. 38C  is a sectional view taken along line Y-Y′ in  FIG. 38A . 
           [0071]      FIG. 39A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 39B  is a sectional view taken along line X-X′ in  FIG. 39A , and  FIG. 39C  is a sectional view taken along line Y-Y′ in  FIG. 39A . 
           [0072]      FIG. 40A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 40B  is a sectional view taken along line X-X′ in  FIG. 40A , and  FIG. 40C  is a sectional view taken along line Y-Y′ in  FIG. 40A . 
           [0073]      FIG. 41A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 41B  is a sectional view taken along line X-X′ in  FIG. 41A , and  FIG. 41C  is a sectional view taken along line Y-Y′ in  FIG. 41A . 
           [0074]      FIG. 42A  is a plan view of a method for manufacturing a semiconductor device according to the present invention,  FIG. 42B  is a sectional view taken along line X-X′ in  FIG. 42A , and  FIG. 42C  is a sectional view taken along line Y-Y′ in  FIG. 42A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0075]    A manufacturing process for forming a SGT structure according to an embodiment of the present invention is described below with reference to  FIGS. 2A-C  to  42 A-C. 
         [0076]    First, a manufacturing method for forming a fin-shaped semiconductor layer on a semiconductor substrate, forming a first insulating film around the fin-shaped semiconductor layer, and forming a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer is described. As shown in  FIG. 2 , a first resist  102  is formed for forming a fin-shaped semiconductor layer on a semiconductor substrate  101 . 
         [0077]    As shown in  FIGS. 3A-C , the semiconductor substrate  101  is etched to form a fin-shaped semiconductor layer  103 . Although, in this case, the fin-shaped semiconductor layer is formed using the resist as a mask, a hard mask such as an oxide film or a nitride film may be used. 
         [0078]    As shown in  FIGS. 4A-C , the first resist  102  is removed. 
         [0079]    As shown in  FIGS. 5A-C , a first insulating film  104  is deposited around the fin-shaped semiconductor layer  103 . As the first insulating film, an oxide film formed by high-density plasma, or an oxide film formed by low-pressure chemical vapor deposition may be used. 
         [0080]    As shown in  FIGS. 6A-C , the first insulating film  104  is etched back to expose an upper portion of the fin-shaped semiconductor layer  103 . The steps up to this step are the same as in the method for forming a fin-shaped semiconductor layer of Japanese Unexamined Patent Application Publication No. 2-188966. 
         [0081]    As shown in  FIGS. 7A-C , a second resist  105  is formed so as to be perpendicular to the fin-shaped semiconductor layer  103 . A portion where the fin-shaped semiconductor layer  103  and the second resist  105  intersect at right angles becomes a pillar-shaped silicon layer. Since a linear resist can be used, the resist is unlikely to fall after patterning, thereby realizing a stable process. 
         [0082]    As shown in  FIGS. 8A-C , the fin-shaped semiconductor layer  103  is etched. A portion where the fin-shaped semiconductor layer  103  and the second resist  105  intersect at right angles becomes the pillar-shaped semiconductor layer  106 . Therefore, the width of the pillar-shaped semiconductor layer  106  is equal to the width of the fin-shaped semiconductor layer. As a result, a structure is formed, in which the pillar-shaped semiconductor layer  106  is formed in an upper portion of the fin-shaped semiconductor layer  103 , and the first insulating film  104  is formed around the fin-shaped semiconductor layer  103 . 
         [0083]    As shown in  FIGS. 9A-C , the second resist  105  is removed. 
         [0084]    Next, a description is given of a manufacturing method for forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped semiconductor layer, and a lower portion of the pillar-shaped semiconductor layer in order to use a gate-last process. As shown in  FIGS. 10A-C , a second oxide film  107  is deposited, and a first nitride film  108  is formed. Since an upper portion of the pillar-shaped semiconductor layer is subsequently covered with a gate insulating film and a polysilicon gate electrode, a diffusion layer is formed in an upper portion of the pillar-shaped semiconductor layer before covering of the pillar-shaped silicon layer. 
         [0085]    As shown in  FIGS. 11A-C , the first nitride film  108  is etched to be left as a wide wall. 
         [0086]    As shown in  FIGS. 12A-C , impurities such as arsenic, phosphorus, or boron are implanted to form a diffusion layer  110  in an upper portion of the pillar-shaped silicon layer, and diffusion layers  109  and  111  in an upper portion of the fin-shaped semiconductor layer  103 . 
         [0087]    As shown in  FIGS. 13A-C , the first nitride film  108  and the second oxide film  107  are removed. 
         [0088]    As shown in  FIGS. 14A-C , heat treatment is performed. The diffusion layers  109  and  111  in an upper portion of the fin-shaped semiconductor layer  103  are brought into contact with each other to form a diffusion layer  112 . As described above, in order to use the gate-last process, the diffusion layers  110  and  112  are formed by impurity implantation in an upper portion of the pillar-shaped semiconductor layer and in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped silicon layer. 
         [0089]    Next, a description is given of a manufacturing method for forming a polysilicon gate electrode and a polysilicon gate wiring using polysilicon in order to use the gate-last process. In order to use the gate-last process, an interlayer insulating film is deposited, and then the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent an upper portion of the pillar-shaped semiconductor layer from being exposed by chemical mechanical polishing. 
         [0090]    As shown in  FIGS. 15A-C , a gate insulating film  113  is formed, and polysilicon  114  is deposited and then planarized. After planarization, the upper surface of the polysilicon is higher than the gate insulating film  113  disposed on the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 . As a result, when in order to use the gate-last process, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after the interlayer insulating film is deposited, the upper portion of the pillar-shaped semiconductor layer is not exposed by chemical mechanical polishing. 
         [0091]    In addition, a second nitride film  115  is deposited. The second nitride film is one which inhibits the formation of silicide in upper portions of the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed in an upper portion of the fin-shaped semiconductor layer. 
         [0092]    As shown in  FIGS. 16A-C , a third resist  116  is formed for forming the polysilicon gate electrode and the polysilicon gate wiring. A portion corresponding to gate wiring is preferably perpendicular to the fin-shaped semiconductor layer  103 . This is because a parasitic capacitance between the gate wiring and the substrate is decreased. 
         [0093]    As shown in  FIGS. 17A-C , the second nitride film  115  is etched. 
         [0094]    As shown in  FIGS. 18A-C , the polysilicon  114  is etched to form a polysilicon gate electrode  114   a  and a polysilicon gate wiring  114   b.    
         [0095]    As shown in  FIGS. 19A-C , the gate insulating film  113  is etched. 
         [0096]    As shown in  FIGS. 20A-C , the third resist  116  is removed. 
         [0097]    The manufacturing method for forming the polysilicon gate electrode and the polysilicon gate wiring using polysilicon in order to use the gate-last process is described above. After the polysilicon gate electrode  114   a  and the polysilicon gate wiring  114   b  are formed, the upper surface of polysilicon is higher than the gate insulating film  113  on the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 . 
         [0098]    Next, a manufacturing method for forming a silicide in an upper portion of the fin-shaped semiconductor layer is described. The silicide is not formed in upper portions of the polysilicon gate electrode  114   a  and the polysilicon gate wiring  114   b  and in the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 . When the silicide is formed in the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 , the manufacturing process is enlarged. 
         [0099]    As shown in  FIGS. 21A-C , a third nitride film  117  is deposited. 
         [0100]    As shown in  FIGS. 22A-C , the third nitride film  117  is etched to be left as a side wall. 
         [0101]    As shown in  FIGS. 23A-C , a metal such as nickel or cobalt is deposited to form silicide  118  in an upper portion of the diffusion layer  112  formed in an upper portion of the fin-shaped semiconductor layer  103 . At this time, the polysilicon gate electrode  114   a  and the polysilicon gate wiring  114   b  are covered with the third nitride film  117  and the second nitride film  115 , and the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106  is covered with the gate insulating film  113 , the polysilicon gate electrode  114   a , and the polysilicon gate wiring  114   b , and thus silicide is not formed in the polysilicon gate electrode  114   a , the polysilicon gate wiring  114   b , and the diffusion layer  110 . 
         [0102]    The manufacturing method for forming a silicide in an upper portion of the fin-shaped semiconductor layer is described above. 
         [0103]    Next, a gate-last manufacturing method is described, in which the polysilicon gate electrode and the polysilicon wiring are exposed by chemical mechanical polishing after an interlayer insulting film is deposited, the polysilicon gate electrode and the polysilicon wiring are etched, and then a metal is deposited. 
         [0104]    As shown in  FIGS. 24A-C , a fourth nitride film  140  is deposited for protecting the silicide  118 . 
         [0105]    As shown in  FIGS. 25A-C , an interlayer insulating film  119  is deposited and then planarized by chemical mechanical polishing. 
         [0106]    As shown in  FIGS. 26A-C , the polysilicon gate electrode  114   a  and the polysilicon gate wiring  114   b  are exposed by chemical mechanical polishing. 
         [0107]    As shown in  FIGS. 27A-C , the polysilicon gate electrode  114   a  and the polysilicon gate wiring  114   b  are etched. Wet etching is preferred. 
         [0108]    As shown in  FIGS. 28A-C , a metal  120  is deposited and then planarized to fill, with the metal  120 , a portion from which the polysilicon gate electrode  114   a  and the polysilicon gate wiring  114   b  have been removed. Atomic layer deposition is preferably used. 
         [0109]    As shown in  FIGS. 29A-C , the metal  120  is etched to expose the gate insulating film  113  formed on the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 . Consequently, a metal gate electrode  120   a  and a metal gate wiring  120   b  are formed. The gate-last manufacturing method is described above, in which after the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and then a metal is deposited. 
         [0110]    Next, a manufacturing method for forming a contact is described. Since a silicide is not formed in the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 , a contact is brought into direct contact with the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 . As shown in  FIGS. 30A-C , an interlayer insulating film  121  is deposited and then planarized. 
         [0111]    As shown in  FIGS. 31A-C , a fourth resist  122  is formed for forming a contact hole on the pillar-shaped semiconductor layer  106 . 
         [0112]    As shown in  FIGS. 32A-C , the interlayer insulating film  121  is etched to form a contact hole  123 . 
         [0113]    As shown in  FIGS. 33A-C , the fourth resist  122  is removed. 
         [0114]    As shown in  FIGS. 34A-C , a fifth resist  124  is formed for forming contact holes on the metal gate wiring  120   b  and on the fin-shaped semiconductor layer  103 . 
         [0115]    As shown in  FIGS. 35A-C , the interlayer insulating films  121  and  119  are etched to form contact holes  125  and  126 . 
         [0116]    As shown in  FIGS. 36A-C , the fifth resist  124  is removed. 
         [0117]    As shown in  FIGS. 37A-C , the nitride film  140  and the gate insulating film  113  is etched to expose the silicide  118  and the diffusion layer  110 . 
         [0118]    As shown in  FIGS. 38A-C , a metal is deposited to form contacts  143 ,  127 , and  128 . The manufacturing method for forming contacts is described above. Since a silicide is not formed in the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 , the contact  127  is brought into direct contact with the diffusion layer  110  in an upper portion of the pillar-shaped semiconductor layer  106 . 
         [0119]    Next, a manufacturing method for forming a metal wiring layer is described. 
         [0120]    As shown in  FIGS. 39A-C , a metal  129  is deposited. 
         [0121]    As shown in  FIGS. 40A-C , sixth resists  130 ,  131 , and  132  are formed for forming the metal wiring. 
         [0122]    As shown in  FIGS. 41A-C , the metal  129  is etched to metal wirings  133 ,  134 , and  135 . 
         [0123]    As shown in  FIGS. 42A-C , the sixth resists  130 ,  131 , and  132  are removed. 
         [0124]    The manufacturing method for forming metal wiring layers is described above. 
         [0125]    The result of the above-described manufacturing method is shown in  FIGS. 1A-C . 
         [0126]    The resulting structure includes: the fin-shaped semiconductor layer  103  formed on the substrate  101 ; the first insulating film  104  formed around the fin-shaped semiconductor layer  103 ; the pillar-shaped semiconductor layer  106  formed on the fin-shaped semiconductor layer  103 , the width of the pillar-shaped semiconductor layer  106  being equal to the width of the fin-shaped semiconductor layer  103 ; the diffusion layer  112  formed in an upper portion of the fin-shaped semiconductor layer  103  and a lower portion of the pillar-shaped semiconductor layer  106 ; the diffusion layer  110  formed in an upper portion of the pillar-shaped semiconductor layer  106 ; the silicide  118  formed in an upper portion of the diffusion layer  112  in an upper portion of the fin-shaped semiconductor layer  103 ; the gate insulating film  113  formed around the pillar-shaped semiconductor layer  106 ; the metal gate electrode  120   a  formed around the gate insulating film; the metal gate wiring  120   b  connected to the metal gate electrode  120   a  and extending in a direction perpendicular to the fin-shaped semiconductor layer  103 ; and the contact  127  formed on the diffusion layer  110 , the diffusion layer  110  and the contact  127  being in direct contact with each other. 
         [0127]    As described above, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate and provide a SGT manufacturing method using a gate-last process and a resulting SGT structure.