Abstract:
A method and apparatus for processing data packets in flow-aware network nodes is disclosed for storing flow data without altering transmission data throughput for a limited cost. The method and apparatus for processing data packets in flow-aware network nodes includes alternate usage of a fast access internal memory and a slower speed access external memory which provides low latency yet comprehensive flow-awareness. The method for processing data packets in flow-aware network nodes is particularly useful for overcoming requiring extensive usage of fast access memory of flow-aware network nodes known in the art.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to the field of communication networks and more precisely of data packet processing in packet routers. 
     Data packet routers are located in the network nodes. In the case of flow aware packet networks, said routers and particularly the ones corresponding to nodes located at the edges of the network have to keep a memory of the state information of the flows entering the system. Such recording has to be achieved for all the flows received by the network nodes. In the case of high speed channels (≧10 Gb/s), said flow state information associated with flow IDs needs to be available as fast as possible to prevent delays during packet processing.
 
Besides, the flow size may vary from a “mouse” flow comprising a few (a dozen for example) packets to “elephant” flows comprising hundreds of packets. The memory capacity needs therefore to be large enough to cover any situation.
 
Thus, flow-information storage needs to combine large capacity memory with reduced latency access of the stored data such that transmitted packets can be processed according to the data bitrate of the transmission. Moreover, the cost of such memory has to remain as low as possible to be widely used.
 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide equipment to store flow data without altering transmission data throughput for a limited cost. 
     Thus, the present invention refers to a method for managing the storage of flow data in a packet processing equipment wherein said equipment processes a packet stream that is a random aggregate of a large number of distinct flows of packets and comprises a fast access internal memory and a slower access external memory and wherein said method comprises the following steps:
         receiving a data packet at the input of the packet processing equipment,   extracting a flow ID from the data packet header and mapping it to an address at which corresponding flow data are stored in the slower access external memory,   determining if said received data packet corresponds to a new flow, if said received data packet is the first of its flow,
           creating a new flow data record, if at least one other packet of the flow has been received in the packet processing equipment,   determining if the flow data corresponding to said received packet is available in the fast access internal memory, if the corresponding flow data is available in the fast access internal memory,
               locating said flow data, if no corresponding flow data is available in the fast access internal memory,   retrieving said corresponding flow data from the slower access external memory and storing them in the fast access internal memory,   
               
           achieving packet processing using corresponding flow data from the fast access internal memory, when no more packet of a given flow are located in the packet processing equipment,   updating corresponding flow data in the slower access external memory from the flow data in the fast internal memory,   securing corresponding flow data update.       

     According to another aspect of the invention, the delay between the starting time of the step of extracting a flow ID and mapping it to the corresponding address and the starting time of the step of packet processing corresponds to a duration larger than the time of mapping a flow ID to the corresponding address plus the access latency of the slower access external memory. 
     According to a further aspect of the invention, the step of securing corresponding flow data update is achieved by holding the flow data in the fast access internal memory for a delay larger than the write-access latency of the slower access external memory after the ending time of the step of packet processing. 
     According to an additional aspect of the invention, the fast access internal memory corresponds to an on-chip static random access memory (SRAM) and the slower access external memory corresponds to an off-chip dynamic random access memory (DRAM). 
     According to another aspect of the invention, said method comprises an additional step corresponding to the freeing of the memory space of the fast access internal memory of the corresponding flow data, said additional step being achieved after the step of securing corresponding flow data update in order to ensure that up-to-date flow data will be used if a packet of said flow is received in the packet processing equipment. 
     According to a further aspect of the invention, the capacity of the fast access internal memory corresponds to the required capacity for recording flow data corresponding to the maximal possible number of packets in transit in the equipment. 
     According to an additional aspect of the invention, the step of extracting a flow ID and a memory address from the data packet header is achieved by organized data repositories. 
     According to another aspect of the invention, the organized data repositories are routing lookup tables. 
     According to a further aspect of the invention, the packet processing equipment comprises a packet pipeline and at least one process is applied sequentially on the packets transmitted in said packet pipeline. 
     According to an additional aspect of the invention, the fast access internal memory is partitioned into separately addressable sectors and is distributed in function of the different concurrent processes. 
     According to another embodiment of the invention, a fraction of the time slots of received packets, for accessing the slower access external memory, are reserved for internal service packets. 
     According to a further embodiment of the invention, at the reception of a data packet at the input of the packet processing equipment, the packet payload is separated from the packet header, said packet payload being stored in a memory and the step of achieving packet processing using corresponding flow data from the fast access internal memory is applied to the packet header, packet payload and packet header being joined together after packet header processing. 
     The present invention also refers to a packet processing equipment comprising a fast access internal memory and a slower access external memory wherein it also comprises means for:
         receiving a data packet at the input of the packet processing equipment,   extracting a flow ID and a memory address from the data packet header,   saving flow data corresponding to the extracted flow ID and address in the slower access external memory,   retrieving said flow data from the slower access external memory and storing them in the fast access internal memory,   achieving packet processing by using corresponding flow data from the fast access internal memory,   updating corresponding flow data of the slower access external memory when no more packet of a flow are located in the packet processing equipment,   holding corresponding flow data during a predetermined time in the fast access internal memory.       

     According to another aspect of the invention, the step of achieving packet processing comprises the modification of the flow data in the fast access internal memory according to the packet processing. 
     According to a further aspect of the invention, the fast access internal memory corresponds to an on-chip static random access memory (SRAM) and the slower access external memory corresponds to an off-chip dynamic random access memory (DRAM). 
     According to an additional aspect of the invention, said means are also configured for freeing the memory space of the fast access internal memory of the corresponding flow data. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a possible embodiment of the packet processing equipment; 
         FIG. 2  is a synoptic diagram representing the different steps of an embodiment of the present invention; 
         FIG. 3  is a diagram representing the implementation of equipment required for managing service packets; 
         FIG. 4  is a diagram of a possible embodiment of a packet header processing equipment; 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As used herein, the term “flow” refers to a plurality of data packets having common properties and in particular, a common flow ID. 
     As used herein, the term “flow ID” refers to an identification of a data flow, said identification comprising features or factors representative of the corresponding data flow. 
     As used herein, the term “access latency” refers to the time required between the triggering of a read request in a core device and the effective availability of the data in the core device or between a write request and the effective update of storage in the memory device. 
       FIG. 1  represents an example of embodiment of a packet processing equipment  1  according to the present invention. Said equipment comprises a packet processor unit  3  which can be for example a packet pipeline. Packets  4  are received at the input  5 , then put in transit as a packet stream along the packet processor unit  3  to the output  7  of said packet processor unit  3 . 
       FIG. 2  represents the different steps of an embodiment of the present invention based on the equipment described in  FIG. 1 . 
     At the reception at the input  5  of the packet processor unit (step  101 ), packet headers are read in order to extract the flow ID corresponding to the received packet (step  102 ). Indeed, packets  4  are received randomly from a plurality of flows, said flows having different origins and destinations. Moreover, the different flows may have different sizes (number of packets). Thus, the flow ID of the received packet is compared with the flow IDs for which there are flow data already recorded in an external slow access memory  9 . Said memory can be for example an off-chip dynamic random access memory (DRAM). 
     It has to be noted that for a DRAM, the access latency does not imply slow data transmission. Indeed the data transmission itself can be achieved by burst and can therefore reach high data rates. 
     Said comparison of flow IDs is achieved in an organized data repository  11 , for example, a routing lookup table or a ternary content addressable memory or multiple hash tables. It has also to be noted that Bloom filters can be used in said organized data repository  11 . As a result of matching a known flow ID, the flow ID is mapped to an address at which the corresponding flow data are stored in the external slow access memory  9 . 
     Furthermore, such comparison allows determining if the received packet is the first of a new flow (step  103 ). In such case, a new flow data record is created in the slow access external memory  9  in order to save the data comprised in the flow ID (step  104 ) and all subsequent data pertaining to the same flow. 
     An aspect of the invention is the combination of a fast access internal memory  13 , for example an on-chip static random access memory (SRAM) with the slower access external memory  9 . Such combination allows providing high capacity memory and reduced access latencies while limiting the cost of said memory. Thus, in step  104  a free memory space (also called free cache line of memory) of the fast access internal memory  13  is assigned to the packet. 
     In order to reduce the size (and therefore the cost) of the fast access internal memory  13 , only the flow data concerning the packets in transit in the packet processor unit  3  are placed in the fast access internal memory  13 . The capacity of the fast access internal memory  13  has therefore to be large enough to handle the worst case in term of memory requirement which corresponds to a packet stream having only single packets belonging to different flows along the entire packet processor unit  3 . In such case, a memory space is required for any of the packets  4  in transit. 
     When the first packet of a flow is received at the input of the packet processing equipment  1 , the corresponding initial flow data are saved in the slower access external memory  9 ; when a second or later packet of a flow is received, said flow data are retrieved from the external memory. In both cases, said data are copied into the assigned free memory space of the fast access internal memory  13  (step  105 ). 
     Then, during its transit in the packet processor unit  3 , the packet undergoes different processes  15  (step  106 ). Said processes  15  may be for example a header modification, a filtering process such as a shaping, a modification of the flow statistics (such as a packet or bit counter incrementation), an update of the congestion bit or a flow bitrate mean determination. 
     Thanks to the implementation described in  FIG. 1 , flow data required for the different processes are available in the fast access internal memory  13  so that latencies to access said data are reduced and do not prevent high bitrate transmission of the packets. 
     Besides, the different processes modify the flow data so that a fast access of the memory is also needed for updating the modified values of the flow data. When a packet of the flow reaches the output of the packet processor unit, different cases may occur in function of the presence or the absence of packets of the same flow in transit in the packet processor unit  3  which is determined in step  107 . 
     If another packet of the same flow is in transit in the packet processor unit  3 , then said new packet in transit will use the same flow data from the fast access internal memory  13  so that flow data remain in said fast access internal memory  13 . The packet process is then over (step  108 ). If no other packet is in transit in the packet processor unit  3 , then up-to-date flow data are copied into the slower access external memory  9  (step  109 ) and eventually the memory space corresponding to this flow data in the fast access internal memory is freed by erasing said data (step  110 ), said memory may then be reused for another packet. 
     Thus, at the reception at the input  5  of the packet processor unit  3  of a packet belonging to a flow having a previous packet transmitted through said packet processor unit  3 , no new flow data record needs to be created as said flow data already exists. However, a check is needed if a previous packet of the flow is still in transit in the packet processor unit  3  (step  111 ). 
     Two distinct cases may happen. If the previous packet of the flow is still in transit in the packet processor unit  3 , the flow data are still available in the fast access internal memory  13  and will be used for achieving processes on the newly received packet. In the case, the next step is the step  106 . 
     Otherwise, if the previous packet of the flow has already left the output  7  of the packet processor unit  3  which means that the corresponding flow data have been erased from the fast access internal memory  13 , corresponding flow data recorded in the slower access external memory  9  are copied into the fast access internal memory  13  (step  112 ). 
     Moreover, at the end of the flow, the slower access external memory  9  is also freed by deleting the corresponding flow data. The end of the flow can be determined for example by setting a maximum time between two packets of the same flow (for example 2 seconds). Thus after the timer (of 2 seconds) has elapsed, the flow is considered as over and corresponding data are erased from the memory  9 . 
     Besides, the fast access internal memory  13  can be partitioned into separately addressable sectors such that a given sector is used for a given process. In consequence, one addressable sector corresponds to one process. 
     According to another aspect of the invention, a timing has to be respected between steps described previously in order to ensure the correctness of the packet processing. A time axis is represented at the bottom of  FIG. 1 . Time T 1  corresponds to the reception of a packet at the input of the packet processor unit  3 . Time T 2  corresponds to the completion of the data transfer or data copy from the slower access external memory  9  towards the fast access internal memory  13 . 
     In order to ensure that the flow data have been transferred to the fast access internal memory  13 , the delay between T 1  and T 2  has to be equal or larger than the latency of the access to the external memory  9 . 
     Time T 3  corresponds to the beginning of the transfer of the up-to-date flow data from the fast access internal memory  13  to the slower access external memory  9 . Time T 4  corresponds to the erasing of the flow data in the fast access internal memory  13 . 
     In order to secure the data storage and insure the use of up-to-date data, the delay between T 3  and T 4  has to be equal or larger than the latency of the write-access to the external memory  9 , so that the storage of up-to-date data is complete at time T 4 . Indeed, such delay allows, in case of arrival of a new packet of the flow at the input  5  of the packet processor unit  3  during the delay between T 3  and T 4  of the preceding packet to still have up-to-date data in the fast access internal memory  13 . If the arrival of a new packet of the flow at the input  5  of the packet processor unit  3  occurs after time T 4  of the preceding packet of the same flow, data recorded in the slower access external memory  9  are up-to-date and will be retrieved. If the arrival occurs between times T 3  and T 4 , the flow data still present in fast internal memory is used, as the copy of the flow data into slow external memory is not yet complete. 
     According to another aspect of the invention, in order to insure proper functioning of the packet process equipments, service packets are used and are transmitted in the packet processor unit  3  among the data packets. 
       FIG. 3  represents the organization of these service packets. After analysis of the flow ID by the organized data repository  11 , data packets with their flow ID are transmitted to the input of a multiplexer  17 . The other inputs of the multiplexer are connected to a database clean-up generator  19  providing clean-up service packets and to a node control, management and knowledge-building unit  21  providing control/management service packets. 
     Thus, service packets are inserted in the data packet stream. This can be achieved for example by modifying the time slots. For example, with a 40 ns access instead of 50 ns, one additional time slot called internal service time slot can be added every four time slots (data packet time slots). Said internal service packets control the deletion of obsolete data in the memories and databases as well as exchange control, monitoring or management information with the other equipments of the node. 
     At the output of the packet processor unit  3 , packets are transmitted to a demultiplexer  23  wherein data packets are sent towards their destination  25  whereas service response packets are sent back to the database clean-up generator  19  in the case of clean-up service packets or to the node control/management unit  21  for the control/management packets, said packets carrying, for example, statistics information about the different flows that have been processed or created or deleted. 
     Moreover, statistics information are transmitted from the database clean-up generator to the control/management unit  21  (arrow  27 ). 
     Besides, it has to be noted that if it is required for correct functioning or in case of idle periods in the packet processor unit  3  and during the delay of large packets whose payload does not need any processing, the “unused” data packet time slots can be transformed into internal service time slots. 
     According to another embodiment of the present invention, only packet headers are processed while packet payloads remain unchanged which allows to accelerate processing when appropriate. 
     As shown in  FIG. 4 , at time T′ 1 , a packet is received. Only the header part is transmitted to the packet header processor unit  3 ′ while the packet payload is stored in a queue memory  9 ′ which is similar to a slower access external memory  9 . As previously, a flow ID is extracted from the header and mapped to an address on the slower access external memory  9 . At time T′ 2 , on one side, flow data are transferred from the slower access external memory  9  to the fast access internal memory  13  while, on the other side, a storage pointer of the memory space where the payload is stored is sent to the packet header processing unit  3 ′. Processes  15  are then applied to the packet headers. At time T′ 3 , on one side up-to-date flow data are sent from the fast access internal memory  13  to the slower access external memory  9  while, on the other side, the processor sends back the pointer and the processed packet header to the queue memory  9 ′. Depending on the state of the packet, either the full packet content is finally recovered from queue memory at time T′ 4  or the header is buffered with the payload for later forwarding. Said buffering is managed by a queue and traffic manager  27 . Packets which do not need any queueing can be sent immediately to the output through a cut-through multiplexer  29 ; otherwise the packet forwarding schedule is managed by the queue and traffic manager  27 .