Abstract:
A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates generally to refresh operations in a memory device such as a DRAM (dynamic random access memory) device, and more particularly, to preventing refresh starvation in a multi-port memory device. 
       BACKGROUND OF THE INVENTION 
       [0002]      FIG. 1  shows a block diagram of a multi-port memory device  100  which may be a multi-port DRAM (dynamic random access memory) device for example. The multi-port memory device  100  includes a first port  102 , a second port  104 , a first memory bank  106 , a second memory bank  108 , a third memory bank  110 , a fourth memory bank  112 , and an access controller  114 . 
         [0003]    The first memory bank  106  is dedicated for access just by a first data processor (not shown) via the first port  102 . The third and fourth memory banks  110  and  112  are dedicated for access just by a second data processor (not shown) via the second port  104 . The second memory bank  108  has shared access by the first and second data processors via the first and second ports  102  and  104 , respectively. 
         [0004]    Just one of the ports  102  and  104  has access to the shared memory bank  108  at any given time. The access controller  114  arbitrates access to the shared memory bank  108  between the ports  102  and  104 . On the other hand, the first port  102  has access to its dedicated bank, i.e., the first memory bank  106 , at any time. Similarly, the second port  104  has access to its dedicated banks, i.e., the third and fourth memory banks  110  and  112 , at any time. 
         [0005]      FIG. 2  illustrates how refresh starvation may result in the multi-port memory device  100  of  FIG. 1  with a timing diagram of signals. Referring to  FIGS. 1 and 2 , the authority controller  114  generates an authority signal that indicates which of the ports  102  and  104  is authorized for access to the shared memory bank  108 . In  FIG. 2 , each of the first and second ports  102  and  104  generates CBR (CAS (column address strobe) before RAS (row address strobe)) commands to the shared memory bank  108 . Each CBR command is issued for instructing the shared memory bank  108  to execute an auto-refresh command. 
         [0006]    In  FIG. 2 , CBR commands are issued by the ports  102  and  104  when the port does not have authority for access to the shared memory bank  108 . Thus, the auto-refresh command is not executed in the shared memory bank  108  resulting in refresh starvation in the shared memory bank  108 . 
         [0007]      FIG. 3  is a timing diagram for further illustrating such refresh starvation in the shared memory bank  108 . Referring to  FIGS. 2 and 3 , the first memory bank  106  executes all of the CBR commands from the first port  102 . Similarly, each of the third and fourth memory banks  110  and  112  executes all of the CBR commands from the second port  104 . 
         [0008]    The shared memory bank  108  executes a CBR command from the first or second port  102  or  104  when such a CBR command is issued with proper authority for access to the shared memory bank  108 . Thus, unauthorized CBR commands (outlined in dashed lines with an X in  FIG. 3 ) from the first and second ports  102  and  104  are not executed by the shared memory bank  108 . 
         [0009]    Thus in the example of  FIG. 3 , each of the dedicated banks  106 ,  110 , and  112  executes seven auto-refresh commands. However, the shared memory bank  108  executes only five auto-refresh commands. Such lower number of auto-refresh operations performed in the shared memory bank  108  may result in refresh starvation with the memory cells not having sufficient charge for proper operation. 
         [0010]      FIG. 4  shows a timing diagram of signals during operation of the memory device  100  of  FIG. 1  for preventing refresh starvation. Referring to  FIG. 4 , each of the data processors coupled to the ports  102  and  104  generates a respective CBR command immediately before transition of port authority. Thus, a refresh operation is performed in the shared memory bank  108  immediately around each transition of port authority. 
         [0011]    The timing diagram of  FIG. 5  is similar to  FIG. 3  but with the additional refresh operations  120  being performed in the shared memory bank  108  near each transition of port authority. In  FIG. 5 , a total of ten refresh operations are performed in the shared memory bank  108  compared to a total of five refresh operations in  FIG. 3 . Although refresh starvation is thus prevented in  FIG. 5 , execution of each refresh operation requires time and power consumption. Thus, performing a refresh operation in the shared memory bank  108  at each transition of port authority may result in slow operation and high power consumption in the memory device  100 . 
         [0012]    Thus, a mechanism for preventing refresh starvation with fewer refresh operations in a shared memory bank of a multi-port memory device is desired. 
       SUMMARY OF THE INVENTION 
       [0013]    Accordingly, in a general aspect of the present invention, a multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command from the plurality of ports. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register. 
         [0014]    In another embodiment of the present invention, the memory device further includes an authority controller for generating a port authority signal indicating the port authority between the ports. 
         [0015]    In an example embodiment of the present invention, the refresh register is set by the refresh controller when an unauthorized refresh command is generated. In addition, the refresh controller controls the shared memory unit to perform an internal refresh operation at a subsequent transition in port authority after the refresh register is set. Furthermore, the refresh controller resets the refresh register after such an internal refresh operation has been activated in the shared memory unit. In that case, the refresh controller controls the shared memory unit to not perform an internal refresh operation in the shared memory unit at another subsequent transition in port authority after the refresh register is reset. 
         [0016]    In a further embodiment of the present invention, the refresh controller sets the refresh register when another unauthorized refresh command is generated after the refresh register has been reset. In that case, the refresh controller controls the shared memory unit to perform an internal refresh operation at another subsequent transition in port authority after the refresh register is thus set. 
         [0017]    In another embodiment of the present invention, the refresh controller sets the refresh register when an unauthorized refresh command is generated from any of the plurality of ports. Alternatively, the refresh controller sets the refresh register when any type of refresh command is generated only from a predetermined one of the plurality of ports. 
         [0018]    In a further embodiment of the present invention, the refresh register stores a refresh count that is incremented by the refresh controller every time an unauthorized refresh command is generated. In that case, the refresh controller controls the shared memory unit to perform an internal refresh operation at a subsequent transition in port authority if the refresh count is greater than zero. Also in that case, the refresh controller decrements the refresh count after such an internal refresh operation in the shared memory unit is activated. Alternatively, the refresh controller further decrements the refresh count every time an authorized refresh command is executed in the shared memory unit. 
         [0019]    The present invention may be used to particular advantage when the memory device is a semiconductor DRAM (dynamic random access memory) device, and when the shared memory unit is a shared memory bank. However, the present invention may also be used for other types of multi-port memory devices having refresh operations. 
         [0020]    In this manner, the shared memory bank is controlled to execute more internal refresh operations to prevent refresh starvation in the multi-port memory device. In addition, the number of internal refresh operations is not excessive for maintaining operating speed and low power consumption. 
         [0021]    These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]      FIG. 1  shows a block diagram of a multi-port memory device having refresh starvation, according to the prior art; 
           [0023]      FIGS. 2 and 3  each show a timing diagram for illustrating refresh starvation in the memory device of  FIG. 1 , according to the prior art; 
           [0024]      FIGS. 4 and 5  each show a timing diagram for illustrating prevention of refresh starvation with internal refresh operations performed at each transition of port authority, according to the prior art; 
           [0025]      FIG. 6  shows a block diagram of a mobile device having a memory system with prevention of refresh starvation, according to an embodiment of the present invention; 
           [0026]      FIG. 7  shows a block diagram of a multi-port memory device with prevention of refresh starvation in the memory system of  FIG. 6 , according to an embodiment of the present invention; 
           [0027]      FIGS. 8 and 9  each show a timing diagram for illustrating prevention of refresh starvation by setting and resetting a refresh register, according to an embodiment of the present invention; 
           [0028]      FIGS. 10 and 11  each show a timing diagram for illustrating prevention of refresh starvation by tracking a count of internal refresh operations to be performed, according to another embodiment of the present invention; and 
           [0029]      FIGS. 12 and 13  each show a timing diagram illustrating a comparison of various embodiments of the present invention with the prior art for prevention of refresh starvation. 
       
    
    
       [0030]    The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number in  FIGS. 1 ,  2 ,  3 ,  4 ,  5 ,  6 ,  7 ,  8 ,  9 ,  10 ,  11 ,  12 , and  13  refer to elements having similar structure and/or function. 
       DETAILED DESCRIPTION 
       [0031]      FIG. 6  shows a block diagram of a mobile device  200  having a memory system  202  with prevention of refresh starvation according to an embodiment of the present invention. Such a mobile device  200  may be a cell phone for example with an antenna  204  for connecting with a wireless communication system. 
         [0032]    The mobile device  200  includes a modem chip  206  with a modem data processor  208  for providing communication functionality. The mobile device  200  also includes a LCD (liquid crystal display)  210  and an AP (application processor)/media chip  212  with an AP (application processor)/media data processor  214  for providing display functionality. 
         [0033]    The memory system  202  of the mobile device  200  includes a NOR flash memory device  216  accessed just by the modem data processor  208  for providing the communication functionality. The memory system  202  also includes a NAND flash memory device  218  accessed just by the AP/media data processor  214  for providing the display functionality. 
         [0034]    The memory system  202  also includes a multi-port memory device  220  that is shared for access by both the modem data processor  208  and the AP/media data processor  214 . The multi-port memory device  220  is a multi-port semiconductor DRAM (dynamic random access memory) device according to an embodiment of the present invention. 
         [0035]      FIG. 7  shows a block diagram of the multi-port shared memory device  220  of  FIG. 6  with prevention of refresh starvation, according to an example embodiment of the present invention. The multi-port shared memory device  220  includes a first port  222  for access by the modem data processor  208  to a core  224  having an array of memory cells fabricated therein. The multi-port shared memory device  220  also includes a second port  226  for access by the AP/media data processor  214  to the core  224 . 
         [0036]    The core  224  is organized into a first memory bank  228 , a second memory bank  230 , a third memory bank  232 , and a fourth memory bank  234 . The first memory bank  228  is dedicated to be accessed just by the modem data processor  208  via the first port  222 . The third and fourth memory banks  232  and  234  are dedicated to be accessed just by the AP/media data processor  214  via the second port  226 . The second memory bank  230  is shared for access by both the modem data processor  208  and the AP/media data processor  214  via the first and second ports  222  and  226 , respectively. 
         [0037]    The multi-port shared memory device  220  includes a first refresh counter  236  and a first row decoder  238  that are used for executing an auto-refresh command from the first port  222  in the first memory bank  228 . The multi-port shared memory device  220  also includes a second refresh counter  240  and a second row decoder  242  that are used for executing an auto-refresh command from the second port  226  in the third and fourth memory banks  232  and  234 . The multi-port shared memory device  220  further includes a third refresh counter  244  and a third row decoder  246  that are used for executing a refresh command from one of the first and second ports  222  and  226  or from a refresh controller  248 , in the shared memory bank  230  for preventing refresh starvation therein. 
         [0038]    In addition, the multi-port shared memory device  220  includes an authority controller  250  that generates a port authority signal indicating port authority for access to the shared memory bank  230  to one of the first and second ports  222  and  226  at any given time. The multi-port shared memory device  220  also includes a refresh command multiplexer  252  that selects a refresh command from one of the first and second ports  222  and  226  to be executed in the shared memory bank  230  according to the authority signal from the authority controller. 
         [0039]    Furthermore, the multi-port shared memory device  220  includes a refresh register  254  and the refresh controller  248  for generating internal refresh commands to be executed by the shared memory bank  230  for preventing refresh starvation therein. The term “internal refresh operation” refers to a refresh operation performed in the memory device  220  from activation by the refresh controller  248 . In contrast, the term “auto refresh operation” or “command refresh operation” refers to a refresh operation performed in the memory device  220  from execution of a refresh command generated from one of the ports  222  and  226 . 
         [0040]    The refresh controller  248  includes a data processor  256  and a memory device  258  having sequences of instructions (i.e., software) stored thereon. Execution of such sequences of instructions by the data processor  256  causes the data processor  256  to perform any functionality described herein with reference to  FIGS. 8 ,  9 ,  10 ,  11 ,  12 , and  13  for the refresh data processor  256  and/or the refresh controller  248 . However, the present invention may also be practiced with different types of implementations for the refresh controller  248  such as with logic circuitry for example. 
         [0041]    The multi-port shared memory device  220  further includes an OR-gate  260  that generates an output signal for controlling the third refresh counter  244  and the third row decoder  246 . The third refresh counter  244  and the third row decoder  246  are controlled by the OR-gate  260  such that a refresh operation is performed in the shared memory bank  230  if the refresh command multiplexer  252  indicates an authorized refresh command generated from one of the first and second ports  222  and  226  or if the refresh controller  248  activates an internal refresh operation. 
         [0042]    For example, the refresh command multiplexer  252  activates a Refresh by CMD (Command) signal to a logic high state when an authorized refresh command is generated from one of the first and second ports  222  and  226 . Similarly, the refresh controller  248  activates an Internal Refresh signal to the logic high state for indicating that the shared memory bank  230  is to execute an internal refresh operation. The OR-gate  230  inputs such a Refresh by CMD signal from the refresh command multiplexer  252  and such an Internal Refresh signal from the refresh controller  248 . 
         [0043]    The output of the OR-gate  230  is input by the third refresh counter  244  and the third row decoder  246 . When the output of the OR-gate  230  is activated to the logic high state, the third refresh counter  244  increments to a next address of the shared memory bank  230 . In that case, the third row decoder  246  decodes such an incremented address from the third refresh counter  244  and controls the shared memory bank  230  to perform a refresh operation on such an incremented address of the shared memory device  203  as indicated by the third refresh counter  244 . 
         [0044]    Operation of the memory device  220  of  FIG. 7  for preventing refresh starvation in the shared memory bank  230  is now described. 
         [0045]      FIG. 8  shows a timing diagram of signals during operation of the memory device  220  of  FIG. 7  when the refresh register  254  is a 1-bit register according to an embodiment of the present invention. The refresh register  254  of  FIG. 7  may be implemented with any type of data storage device storing at least such 1-bit. Referring to  FIGS. 7 and 8 , each of the ports  222  and  226  requests port authority for accessing the shared memory bank  230  to the authority controller  250 . The authority controller  250  generates a port Authority signal for indicating which one of the ports  222  and  226  has authority for access to the shared memory bank  230 . 
         [0046]    Further referring to  FIGS. 7 and 8 , the refresh data processor  256  sets the 1-bit data stored in the refresh register  254  to a logic high state whenever any of the ports  222  and  226  generates an unauthorized refresh (CBR) command. For example, the first port  222  generates an unauthorized CBR command while the port authority is for the second port  226 . Similarly, the second port  226  generates an unauthorized CBR command while the port authority is for the first port  222 . 
         [0047]    For example in  FIG. 8 , the refresh data processor  256  sets the 1-bit of the refresh register  254  to a logic high state at time point T 1  when the first port  222  issues an unauthorized CBR command. Any additional unauthorized CBR command generated before the subsequent transition of port authority maintains the 1-bit of the refresh register  254  to be set to the logic high state. Thereafter, upon subsequent transition of the port authority from the second port  226  to the first port  222  at time point T 2 , the refresh data processor  256  activates the Internal Refresh signal to the logic high state since the 1-bit of the refresh register  254  has been set to the logic high state. 
         [0048]    As a result of such activation of the Internal Refresh signal, the third refresh counter  244  increments an address, and the third row decoder  246  controls the shared memory bank  230  to perform a refresh operation at the incremented address as indicated by the third refresh counter  244 . After start of such a refresh operation such as at time point T 3  in  FIG. 8 , the refresh data processor  256  resets the 1-bit of the refresh register  254  to a logic low state and deactivates the Internal Refresh signal to the logic low state. 
         [0049]    Further referring to  FIG. 8 , subsequently at time point T 4 , the 1-bit of the refresh register  254  set again to the logic high state when the second port  226  issues an unauthorized CBR command. Thereafter, upon subsequent transition of the port authority from the first port  222  to the second port  226  at time point T 5 , the refresh data processor  256  activates the Internal Refresh signal to the logic high state since the 1-bit of the refresh register  254  has been set to the logic high state. 
         [0050]    As a result of such activation of the Internal Refresh signal, the third refresh counter  244  again increments the generated address, and the third row decoder  246  controls the shared memory bank  230  to perform a refresh operation at the incremented address as indicated by the third refresh counter  244 . After start of such a refresh operation such as at time point T 6  in  FIG. 8 , the refresh data processor  256  resets the 1-bit of the refresh register  254  to a logic low state and deactivates the Internal Refresh signal to the logic low state. 
         [0051]    The 1-bit of the refresh register  254  remains reset to the logic low state as long as no unauthorized CBR command is generated from any of the ports  222  and  226 . Thus, at any subsequent transition of port authority such as at time points T 7  and T 8  in  FIG. 8 , the refresh data processor  256  maintains the Internal Refresh signal to be deactivated at the logic low state. Consequently, no internal refresh operation is performed in the shared memory bank  230  at such subsequent transitions of port authority. 
         [0052]      FIG. 9  shows a timing diagram of signals during operation of the memory device  220  of  FIG. 7  when any type of CBR command from just a predetermined one of the ports  222  and  226  is used for setting the 1-bit refresh register  254 , according to another embodiment of the present invention. In the embodiment of  FIG. 9  for example, any type (authorized or unauthorized) of CBR command from just the first port  222  is used for setting the 1-bit of the refresh register  254 . 
         [0053]    For example in  FIG. 9 , the refresh data processor  256  sets the 1-bit of the refresh register  254  to the logic high state at time point T 11  when the first port  222  issues a CBR command (that is unauthorized). Any additional CBR command generated by the first port  222  before the subsequent transition of port authority maintains the 1-bit of the refresh register  254  to be set to the logic high state. Thereafter, upon subsequent transition of the port authority from the second port  226  to the first port  222  at time point T 12 , the refresh data processor  256  activates the Internal Refresh signal to the logic high state since the 1-bit of the refresh register  254  has been set to the logic high state. 
         [0054]    As a result of such activation of the Internal Refresh signal, the third refresh counter  244  increments its generated address, and the third row decoder  246  controls the shared memory bank  230  to perform a refresh operation at the incremented address as indicated by the third refresh counter  244 . After start of such a refresh operation such as at time point T 13  in  FIG. 9 , the refresh data processor  256  resets the 1-bit of the refresh register  254  to the logic low state and deactivates the Internal Refresh signal to the logic low state. 
         [0055]    Note that in  FIG. 9 , any CBR command from just the first port  222  is used for setting the 1-bit refresh register  254 . Thus, any CBR command from the second port  226  is ignored for purposes of setting the 1-bit refresh register  254 . For example in  FIG. 9 , the unauthorized CBR command generated by the second port  226  between time points T 14  and T 15  when the first port  222  has authority for access to the shared memory bank  230  does not set the 1-bit refresh register  254 . 
         [0056]    With the 1-bit refresh register  254  being reset after time point T 13  in  FIG. 9 , no internal refresh operation is performed in the shared memory device  230  with control from the refresh controller  248  at the subsequent transitions in port authority at time points T 15  and T 16 . The 1-bit refresh register  254  is set again to the logic high state at time point T 17  when the predetermined port  222  generates another CBR command (that is authorized). Thereafter, upon subsequent transition of the port authority from the first port  222  to the second port  226  at time point T 18 , the refresh data processor  256  activates the Internal Refresh signal to the logic high state since the 1-bit of the refresh register  254  has been set to the logic high state. 
         [0057]    As a result of such activation of the Internal Refresh signal, the third refresh counter  244  increments its generated address, and the third row decoder  246  controls the shared memory bank  230  to perform a refresh operation at the incremented address as indicated by the third refresh counter  244 . After start of such a refresh operation such as at time point T 19  in  FIG. 9 , the refresh data processor  256  resets the 1-bit of the refresh register  254  to the logic low state and deactivates the Internal Refresh signal to the logic low state. 
         [0058]    The 1-bit of the refresh register  254  remains reset to the logic low state as long as no CBR command is generated from the predetermined port  222 . Thus, no internal refresh operation is performed in the shared memory bank  230  at any subsequent transition of port authority until a CBR command is again generated from the predetermined port  222 . In this manner with the embodiment of  FIG. 9 , the number of refresh operations performed in the shared memory bank  230  is greater than or equal to the number of refresh operations performed in the memory bank  228  dedicated for access by the predetermined port  222 . 
         [0059]      FIG. 10  shows a timing diagram of signals during operation of the memory device  220  of  FIG. 7  when the refresh register  254  is a multi-bit register according to another embodiment of the present invention. In that case, the refresh register  254  of  FIG. 7  may be implemented with any type of data storage device storing at least such multi-bits. Further referring to  FIGS. 7 and 10 , the refresh data processor  256  controls the refresh register  254  to store a count of unauthorized CBR commands generated by any of the first and second ports  222  and  226 . Thus, the refresh data processor  256  controls the refresh register  254  to increment a count of unauthorized CRB commands when any of the ports  222  and  226  generates an unauthorized CBR command. 
         [0060]    Further in the embodiment of  FIG. 10 , upon any transition of port authority, the refresh data processor  256  sets the Internal Refresh signal to the logic high state if the count of unauthorized CBR commands as stored in the refresh register  254  is greater than zero. With the Internal Refresh signal becoming activated to the logic high state, the third refresh counter  244  increments an address, and the third row decoder  246  controls the shared memory bank  230  to perform a refresh operation at such an incremented address from the third refresh counter  244 . Additionally in the embodiment of  FIG. 10 , the refresh data processor  256  controls the refresh register  254  to decrement the count of unauthorized CRB commands when a refresh operation is performed at the transition of port authority. 
         [0061]    Referring to the example of  FIG. 10 , the refresh data processor  256  controls the refresh register  254  to increment its count to +1 with generation of an unauthorized CBR command from the first port  222  at time point T 21 . In addition, the refresh data processor  256  controls the refresh register  254  to increment its count to +2 with generation of another unauthorized CBR command from the first port  222  at time point T 22 . 
         [0062]    At a subsequent transition of port authority at time point T 23 , the refresh data processor  256  sets the Internal Refresh signal to the logic high state since the count of unauthorized CBR commands as stored in the refresh register  254  is greater than zero. With the Internal Refresh signal becoming activated to the logic high state, the third refresh counter  244  increments an address, and the third row decoder  246  controls the shared memory bank  230  to perform an internal refresh operation at such an incremented address from the third refresh counter  244 . 
         [0063]    Additionally in  FIG. 10 , the refresh data processor  256  controls the refresh register  254  to decrement the count from +2 to +1 at time point T 24  after such an internal refresh operation has been performed and deactivates the Internal Refresh signal to the logic low state. At a subsequent transition of port authority at time point T 25 , the refresh data processor  256  sets the Internal Refresh signal to the logic high state since the count of unauthorized CBR commands as stored in the refresh register  254  is still greater than zero. With the Internal Refresh signal becoming activated to the logic high state, the third refresh counter  244  increments its generated address, and the third row decoder  246  controls the shared memory bank  230  to perform another internal refresh operation at such an incremented address from the third refresh counter  244 . 
         [0064]    Additionally in  FIG. 10 , the refresh data processor  256  controls the refresh register  254  to decrement the count from +1 to +0 at time point T 26  after such an internal refresh operation has been performed and deactivates the Internal Refresh signal to the logic low state. Thereafter, at subsequent transitions of port authority at time points T 27  and T 28  for example, no internal refresh operation is performed in the shared memory bank  230  since the count in the refresh register  254  is now zero. Thus, no internal refresh operation is performed in the shared memory bank  230  at subsequent transitions of port authority until the refresh register  254  increments its count upon generation of another unauthorized CBR command. 
         [0065]    In this manner with the embodiment of  FIG. 10 , the number of refresh operations performed in the shared memory bank  230  is greater than or equal to the number of refresh operations performed in each of the memory banks  228 ,  232 , and  234  dedicated for access by one of the ports  222  and  226 . 
         [0066]      FIG. 11  shows a timing diagram of signals during operation of the memory device  220  when the refresh register  254  is a multi-bit register according to another embodiment of the present invention. The operation according to  FIG. 11  is similar to the embodiment  FIG. 10 , but in  FIG. 11 , the count from the refresh register  254  is further decremented when an authorized CBR command is generated from any of the ports  222  and  226 . 
         [0067]    Referring to the example of  FIG. 11 , the refresh data processor  256  controls the refresh register  254  to increment its count to +1 with generation of an unauthorized CBR command from the first port  222  at time point T 31 . Subsequently, the refresh data processor  256  controls the refresh register  254  to decrement its count from +1 to +0 with generation of an authorized CBR command from the second port  226  at time point T 32 . 
         [0068]    Thereafter in  FIG. 11 , the refresh data processor  256  controls the refresh register  254  to increment its count from +0 to +1 with generation of another unauthorized CBR command from the first port  222  at time point T 33 . At a subsequent transition of port authority at time point T 34 , the refresh data processor  256  sets the Internal Refresh signal to the logic high state since the count of unauthorized CBR commands as stored in the refresh register  254  is greater than zero. With the Internal Refresh signal becoming activated to the logic high state, the third refresh counter  244  increments an address, and the third row decoder  246  controls the shared memory bank  230  to perform an internal refresh operation at such an incremented address from the third refresh counter  244 . 
         [0069]    Additionally in  FIG. 11 , the refresh data processor  256  controls the refresh register  254  to decrement the count from +1 to +0 at time point T 35  after such an internal refresh operation has been performed and deactivates the Internal Refresh signal to the logic low state. Thereafter in  FIG. 1 , at subsequent transitions of port authority at time points T 36  and T 37  for example, no internal refresh operation is performed in the shared memory bank  230  since the count in the refresh register  254  is now zero. Thus, no internal refresh operation is performed in the shared memory bank  230  at subsequent transitions of port authority until the refresh register  254  increments its count upon generation of another unauthorized CBR command. 
         [0070]      FIG. 12  shows an example timing diagram illustrating a comparison of embodiments of the present invention as illustrated in  FIGS. 8 ,  10 , and  11  with the prior art embodiment of  FIG. 4  for prevention of refresh starvation. Referring to  FIG. 12 , a timing diagram  302  shows refresh operations performed in the shared memory bank  230  including a command (i.e., auto) refresh operation from an authorized CBR command  304  and internal refresh operations at each transition of port authority as described with reference to  FIG. 4 . 
         [0071]      FIG. 12  also shows a timing diagram  316  illustrating refresh operations performed in the shared memory bank  230  according to the embodiment of  FIG. 8 . Thus, the timing diagram  316  shows the command refresh operation from the authorized CBR command  304  and a respective internal refresh operation at each transition of port authority after each of the unauthorized CBR commands  310 ,  312 , and  314 . 
         [0072]      FIG. 12  further shows a timing diagram  318  illustrating refresh operations performed in the shared memory bank  230  according to the embodiment of  FIG. 10 . Thus, the timing diagram  318  shows the command refresh operation from the authorized CBR command  304  and three internal refresh operations at subsequent transitions of port authority after the three unauthorized CBR commands  306 ,  308 , and  310 . In addition, the timing diagram  318  shows a respective internal refresh operation at each transition of port authority after each of the unauthorized CBR commands  312  and  314 . 
         [0073]      FIG. 12  additionally shows a timing diagram  320  illustrating refresh operations performed in the shared memory bank  230  according to the embodiment of  FIG. 11 . Thus, the timing diagram  320  shows the command refresh operation from the authorized CBR command  304  and two internal refresh operations at subsequent transitions of port authority after the three unauthorized CBR commands  306 ,  308 , and  310  and the one authorized CBR command  304 . In addition, the timing diagram  320  shows a respective internal refresh operation at each transition of port authority after each of the unauthorized CBR commands  312  and  314 . 
         [0074]      FIG. 13  shows another example timing diagram illustrating a comparison of embodiments of the present invention as illustrated in  FIGS. 9 ,  10 , and  11  with the prior art embodiment of  FIG. 4  for prevention of refresh starvation. Referring to  FIG. 13 , a timing diagram  332  shows refresh operations performed in the shared memory bank  230  including command (i.e., auto) refresh operations from authorized CBR commands  304  and  330  and internal refresh operations at each transition of port authority as described with reference to  FIG. 4 . 
         [0075]      FIG. 13  also shows a timing diagram  334  illustrating refresh operations performed in the shared memory bank  230  according to the embodiment of  FIG. 9 . Thus, the timing diagram  334  shows the command refresh operations from the authorized CBR commands  304  and  330  and a respective internal refresh operation at each transition of port authority after each of the CBR commands  310  and  330  generated from the predetermined port  222 . 
         [0076]      FIG. 13  further shows a timing diagram  336  illustrating refresh operations performed in the shared memory bank  230  according to the embodiment of  FIG. 10 . Thus, the timing diagram  336  shows the command refresh operations from the authorized CBR commands  304  and  330  and three internal refresh operations at subsequent transitions of port authority after the three unauthorized CBR commands  306 ,  308 , and  310 . In addition, the timing diagram  336  shows a respective internal refresh operation at the transition of port authority after the unauthorized CBR command  312 . 
         [0077]      FIG. 13  additionally shows a timing diagram  338  illustrating refresh operations performed in the shared memory bank  230  according to the embodiment of  FIG. 11 . Thus, the timing diagram  338  shows the command refresh operations from the authorized CBR commands  304  and  330  and two internal refresh operations at subsequent transitions of port authority after the three unauthorized CBR commands  306 ,  308 , and  310  and the one authorized CBR command  304 . In addition, the timing diagram  338  shows a respective internal refresh operation at the transition of port authority after the unauthorized CBR command  312 . 
         [0078]    In this manner, sufficient refresh operations are performed in the shared memory bank  230  of the multi-port memory device  220  for prevention of refresh starvation therein. In addition, the number of refresh operations in the embodiments of  FIGS. 8 ,  9 ,  10 , and  11  are not excessive such that operating speed is enhanced and power consumption is minimized. 
         [0079]    The foregoing is by way of example only and is not intended to be limiting. Thus, any number of elements as illustrated and described herein is by way of example only. In addition, the present invention has been described for the multi-port semiconductor DRAM device  220 . However, the present invention may be practiced for any type of memory device having refresh operations. In addition, the present invention may be practiced with any type of memory unit for each of the dedicated memory banks and the shared memory bank. Furthermore, the present invention may be practiced for preventing refresh starvation in any number of shared memory banks. 
         [0080]    The present invention is limited only as defined in the following claims and equivalents thereof.