Abstract:
A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to the field of linewidth measurement; more specifically, it relates to a semiconductor damascene resistor and a method of forming and measuring the width of the resistor.  
         BACKGROUND OF THE INVENTION  
         [0002]    In the fabrication of semiconductor structures, the increasing density of devices (transistors, diodes, resistors and capacitors), including the isolation and interconnect structures between devices, has resulted in the devices, isolation, and interconnects becoming increasingly smaller. This, in turn, has produced the need for high-resolution photolithography. Devices utilizing sub-micron linewidths are now routinely fabricated.  
           [0003]    Accurate measurement of sub-micron linewidths to characterize the photolithography process is difficult. Linewidths have long since passed the practical optical linewidth measurement limit. Scanning electron microscopy (SEM) measurement is not always satisfactory because of charging effects and because an SEM measures linewidths over only a portion of an entire line. Further, this technique is slow, especially when there is a need to take hundreds of measurements across a single die or thousands across a wafer.  
           [0004]    A faster technique is to measure the linewidth electrically. In electrical linewidth measurement the sheet resistance of a conductive material is determined using a test structure, then a known current is passed along second test structure having a line fabricated from the same material. If the line is of known length and thickness, then the linewidth can be calculated from the sheet resistance and the voltage drop along the known length of line. Linewidth measurement of a line formed by subtractive means is well known. To measure a damascene line is more challenging. In a damascene process, a conductive line is formed by etching a trench in an insulator, depositing a layer of conductive material on the top surface of the insulator of a thickness sufficient to fill the trench and then chemical-mechanical-polishing (CMP) the excess conductive material until the top surface of the insulator is exposed again.  
           [0005]    [0005]FIG. 1 is a cross-section view through a conductive damascene line, illustrating an ideal cross-sectional profile. In FIG. 1, an insulator  100  is formed on top of a substrate  105 . Formed in insulator  100  is a damascene conductor  110 . Damascene conductor  110  has sidewalls  115 , a bottom  120  and a top surface  125 . Top surface  125  is co-planar with a top surface  130  of insulator  100 . In the idealized structure, the cross-section of conductor  110  is a perfect rectangle. Particularly, sidewalls  115  are perpendicular to top surface  125 , the top surface is perfectly flat and co-planar with top surface  130  of insulator  100 . Damascene conductor  110  is “W” wide by “T” thick, where “T” is a function only of the depth of the trench after CMP. The resistance R of damascene conductor  110  is given by the formula:  
             R=ρL/WT    (1)  
           [0006]    where ρ is the resistivity of damascene conductor  110  and L is the length (into the plane of the drawing sheet) of the damascene conductor. Electrical linewidth measurement relies on L and T being accurately known and ρ and R being accurately measured.  
           [0007]    However, because this linewidth measurement technique assumes the thickness of lines of the same linewidth do not vary from line to line, the technique is not accurate when sub-micron damascene structures need to be measured because the thickness does vary due to the nature of the damascene fabrication process. The CMP process is not uniform all over the die or wafer. Depending upon line density and linewidth, some lines will be dished, some lines will be eroded and some will be ideal, as in FIG. 1. Worse, lines of the same width may exhibit different amounts of dishing and erosion depending on the local line density.  
           [0008]    [0008]FIG. 2A a cross-section view through a conductive damascene line illustrating the effect of dishing on the cross-sectional profile of FIG. 1. In FIG. 2A, top surface  125 A of conductor  110  is concave instead of flat. The true cross-sectional area of conductor  110  is now a function of the depth of the trench after CMP and of the dishing profile. Dishing is caused by localized differences in pressure caused by localized differences in area ratio of harder line fill material to softer insulating layer material. Obviously, if test structure line profiles vary from ideal to different degrees of dished across the die or wafer, the measurement will not accurately reflect a true linewidth or a true linewidth variation across the die or wafer because the thickness term in equation (1) is no longer accurately known.  
           [0009]    [0009]FIG. 2B is a cross-section view through a conductive damascene line illustrating the effect of erosion on the cross-sectional profile of FIG. 1. In FIG. 2B, top surface  125 B of conductor  110  is recessed a distance “D” from top surface  130  of insulator  100 . The true thickness of conductor  110  is now a function of the depth of the trench after CMP and of the depth “D” of erosion. Erosion is caused by localized differences in pressure caused by localized differences in the number of line edges resulting in faster insulator layer removal in areas having more edges. Again, if test structure line profiles vary from ideal to different degrees of erosion across the die or wafer, the measurement will not accurately reflect a true linewidth or a true linewidth variation across the die or wafer because the thickness term in equation (1) is no longer accurately known.  
           [0010]    It would be desirable to provide an electrical linewidth measurement structure and method, not affected by thickness variation, especially those variations caused by the CMP process.  
         SUMMARY OF THE INVENTION  
         [0011]    A first aspect of the present invention is a linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator comprising: a damascene polysilicon line formed in the insulator, the polysilicon line having a doped region having a predetermined resistivity.  
           [0012]    A second aspect of the present invention is A method of fabricating a linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator comprising: forming a trench in the insulator; filling the trench with polysilicon; planarizing the polysilicon to form a polysilicon line; and ion implanting a dopant species and annealing to form within the polysilicon line a doped region having a predetermined resistivity.  
           [0013]    A third aspect of the present invention is a method of characterizing the photolithographic process for forming a damascened metal line in an insulating layer of a semiconductor device comprising: forming a trench in the insulating layer using the photolithographic process for forming damascened metal lines; filling and planarizing the trench with polysilicon to form a polysilicon line; forming a doped region in the polysilicon region, the doped region having a predetermined resistivity greater than a resistivity of the material of the damascened metal line; and measuring the effective width of the trench by measuring the resistance of the polysilicon line.  
           [0014]    A fourth aspect of the present invention is a resistor, comprising: a damascened polysilicon line formed in a first insulator, the polysilicon line having a first region having a first dopant concentration and a second region having a second dopant concentration, the first dopant concentration being greater than the second dopant concentration; a second insulator formed on a top surface of the first insulator; a first via formed in the second insulator, the first via electrically contacting the first region at a first end of the polysilicon line; and a second via formed in the second insulator, the second via electrically contacting the first region at a second end of the polysilicon line.  
           [0015]    A method of fabricating a resistor, comprising: forming a damascened polysilicon line in a first insulator, the polysilicon line having a first region having a first dopant concentration and a second region having a second dopant concentration, the first dopant concentration being greater than the second dopant concentration; forming a second insulator a top surface of the first insulator; forming a first via formed in the second insulator, the first via electrically contacting the first region at a first end of the polysilicon line; and forming a second via formed in the second insulator, the second via electrically contacting the first region at a second end of the polysilicon line. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0016]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0017]    [0017]FIG. 1 is a cross-section view through a conductive damascene line, illustrating an ideal cross-sectional profile;  
         [0018]    [0018]FIG. 2A is a cross-section view through a conductive damascene line illustrating the effect of dishing on the cross-sectional profile of FIG. 1;  
         [0019]    [0019]FIG. 2B is a cross-section view through a conductive damascene line illustrating the effect of erosion on the cross-sectional profile of FIG. 1;  
         [0020]    [0020]FIG. 3 is an illustrative plan view of a Van der Pauw structure for measuring sheet resistance;  
         [0021]    [0021]FIG. 4 is an illustrative plan view of a test structure for measuring linewidth;  
         [0022]    [0022]FIGS. 5 through 10C, are cross-sectional views illustrating a method of forming a damascene polysilicon line suitable for use in sheet resistance and linewidth measurement structures according to the present invention;  
         [0023]    [0023]FIGS. 11 and 12 are cross-sectional views illustrating a method of forming contact to the structure of FIG. 10 to form a high precision polysilicon resistor according to the present invention; and.  
         [0024]    [0024]FIG. 13 is a top view of a high precision polysilicon resistor according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0025]    [0025]FIG. 3 is an illustrative plan view of a Van der Pauw structure for measuring sheet resistance. In FIG. 3, a Van der Pauw sheet resistance structure  135  used to determine the sheet resistance of the conductive material that is used to fabricate the test structure illustrated in FIG. 4, and described below. Van der Pauw sheet resistance structure  135  comprises a plurality of pads  140 A,  140 B,  140 C and  140 D connected by conductive lines  145 A,  145 B,  145 C and  145 D to a hub  150 , the pads, conductive lines, and hub being integrally formed from the same material by a damascene process as illustrated in FIGS. 5 through 10 and described below. The sheet resistance R s  of the material is determined by first passing a known current I 1  through pads  140 B and  140 C while measuring the resulting voltage drop V 1  between pads  140 A and  140 D to obtain a first resistance value R 1 =V 1 /I 1  and then passing the same current I 1  through pads  140 C and  140 D while measuring the voltage drop V 2  between pads  140 A and  140 B to obtain a second resistance value R 2 =V 2 /I 1 . The sheet resistance R s  may then be calculated using the following formula:  
           R   s =4.532( R   1   +R   2 )/2   (2)  
         [0026]    [0026]FIG. 4 is an illustrative plan view of a test structure for measuring linewidth. In FIG. 4, a linewidth measurement structure  155  used to determine the linewidth “W1” of a conductive line  160  having a known length “L.” Line  160  electrically connects pads  165 A and  165 B. A third pad  165 C is electrically connected to pad  165 B by a conductive line  170  having a width “W2.” “W2” is much greater than “W1.” Pads  165 A,  165 B,  165 C and lines  160  and  170  are integrally formed from the same material by a damascene process as illustrated in FIGS. 5 through 10 and described below. To determine the width “W1” of line  160 , a known current I is forced through line  160  from pad  165 A to pad  165 C. The voltage drop V is then measured across pads  165 A and  165 C. Combining the known value of I, the measured value of V, with the known length “L” and the R s . value obtained from the Van der Pauw measurement discussed above, “W1” may be obtained from the following formula:  
           W 1=( L·R   s   ·I )/ V    (3)  
         [0027]    In one example, “L” is 10 microns or greater, “W2” is 3 microns or greater, and “W1” is about 0.05 to 1.0 microns.  
         [0028]    Van der Pauw sheet resistance structure  135  and linewidth measurement structure  155  may be fabricated simultaneously.  
         [0029]    Turning to the method of fabricating Van der Pauw sheet resistance structure  135  and linewidth measurement structure  155 , FIGS. 5 through 10C, are cross-sectional views illustrating a method of forming a damascene polysilicon line suitable for use in sheet resistance and linewidth measurement structures according to the present invention. In FIG. 5, an insulator  175  is formed on a substrate  180 . An optional, standard antireflective coating (ARC)  182  is formed on a top surface  185  of insulator  175 . Photoresist islands  190  are formed on top of ARC  182  by normal photolithographic processes. Photoresist islands define a first region  195 A and a second region  195 B. In one example insulator  175  is silicon oxide.  
         [0030]    In FIG. 6, a first trench  200 A is formed in insulator  175  in first region  195 A and a second trench  200 B is formed in the insulator in second regions  195 B by a reactive ion etch (RIE) process. Resist islands  190  and ARC  182  are removed wet or dry means. First trench  200 A is “W3” wide by “D1” deep. Second trench  200 A is “W4” wide by “D1” deep. In one example, “D1” is about 0.1 to 1 micron deep and “W3” and “W4” are about 0.05 to 1 micron wide. For illustrative purposes, “W4” is shown as greater than “W3.” 
         [0031]    In FIG. 7, an intrinsic polysilicon layer  205  is deposited on top surface  185  of insulator  175  and in first and second trenches  200 A and  200 B, completely filling the first and second trenches.  
         [0032]    In FIG. 8, a CMP process is performed, removing polysilicon layer down to top surface  185  and thus forming a first conductive line  210 A and a second conductor line  210 B. First conductive line  210 A has polished perfectly and a top surface  215 A of the first conductive line is flat and co-planar with top surface  185  of insulator  175 . Second conductive line  210 B has not polished perfectly and a top surface  215 B of the second conductive line is dished.  
         [0033]    In FIG. 9, an ion implant is performed to form an implanted region  220 A in conductive line  210 A and an implanted region  220 B in conductive line  210 B. The peak of the ion implant distribution in region  220 A is located a depth “D2” from top surface  215 A and the peak of the ion implant distribution in region  220 B is located a depth “D2” from top surface  215 B. Note, that the profile of implanted regions  220 A duplicates the profile of top surface  215 A and the profile of implanted region  220 B duplicate the profile of top surface  215 B. In one example, about 5E14 to 3E15 atm/cm 2  of phosphorus is implanted at about 20 to 40 Kev. “D2” is about 500 to 1000 Å. Arsenic and boron may be used as the implanted species as well.  
         [0034]    Depending on the amount of dopant implanted, the time a and temperature of anneal, cycles subsequent to the ion implantation step, three conductive line structures my be formed.  
         [0035]    A first conductive line structure is illustrated in FIG. 10A. In FIG. 10A, a rapid thermal anneal (RTA) is performed to diffuse and activate the implanted species to form a doped polysilicon region  225 A in first conductive line  210 A and a doped polysilicon region  225 B in second conductive line  210 B. In one example, an RTA is performed for 5 seconds at about 850 to 1050° C. under an inert atmosphere. Doped polysilicon region  225 A does not extend to a top surface  215 A of first conductive line  210 A leaving an upper region  227 A having no ion implant supplied dopant and doped region  225 A does not extend to a bottom  216 A of first conductive line  210 A leaving a lower region  228 A having no ion implant supplied dopant. Doped polysilicon region  225 B does not extend to top surface  215 B of first conductive line  210 B leaving an upper region  227 B having no ion implant supplied dopant and doped region  225 B does not extend to a bottom  216 B of first conductive line  210 B leaving a lower region  228 B having no ion implant supplied dopant. Upper regions  227 A and  227 B and lower regions  228 A and  228 B may be intrinsic or lightly doped. In one example, upper regions  227 A and  227 B and lower regions  228 A and  228 B are doped to a concentration of 1E14 atm/cm 3 .  
         [0036]    Doped polysilicon regions  225 A and  225 B may be either saturated or un-saturated polysilicon. If doped regions  225 A and  225 B are saturated then lower regions  228 A and  228 B must be un-saturated or contain no dopant species. Un-saturated polysilicon is polysilicon having an active dopant species (phosphorus, arsenic, boron) concentration less than the solid solubility of the particular dopant at the anneal temperature. For example, the solid solubility of arsenic at 1100° C. is about 1E21 atm/cm 3 , the solid solubility of boron at 1150° C. is about 4E20 atm/cm 3  and the solid solubility of phosphorus at 900° C. is about 2E20 atm/cm 3 .  
         [0037]    Doped polysilicon regions  225 A and  225 B extend a distance “D3” into first conductive line  210 A and second conductive line  210 B. In one example, the concentration of phosphorus in doped polysilicon regions  225 A and  225 B is about 1E19 to about 1E20 atm/cm 3  after the anneal step described above. Since a predetermined dose of phosphorus has been implanted, the resistivity of first and second lines  210 A and  210 B (being a function of the total amount of dopant implanted) is predetermined. Most of the current through first conductive line  210 A will be carried by doped polysilicon region  225 A. Most of the current forced through second conductive line  210 B will be carried by doped polysilicon region  225 B.  
         [0038]    A second conductive line structure is illustrated in FIG. 10B. In FIG. 10B, doped polysilicon region  225 A extends to top surface  215 A of first conductive line  210 A and doped polysilicon region  225 B extends to top surface  215 B of second conductive line  210 B. There is more contact resistance with the structure of FIG. 10 than the structure of FIG. 11. A probe applied to (or via formed to contact) first and second conductive lines  210 A and  210 B illustrated in FIG. 10, should penetrate into doped polysilicon region  225 A and  225 B to minimize contact resistance.  
         [0039]    A third conductive line structure is illustrated in FIG. 10C. In FIG. 10C, doped polysilicon region  225 A includes all of first conductive line  210 A and doped polysilicon region  225 B includes all of second conductive line  210 B. Conductive regions  225 A and  225 B must be un-saturated.  
         [0040]    First and second conductive lines  210 A and  210 B are illustrated to show insensitivity of the to the surface profile of a conductive line fabricated according to the present invention. The conductive line will behave, for the purpose of electrical measurements, as if it had a thickness equal to the thickness of its doped region. Further, that thickness will be the same for all lines within a die or across a wafer regardless of the line profiles caused by local CMP conditions.  
         [0041]    The resistivity of conductive line  160  of FIG. 4, and conductive lines  210 A and  210 B of FIG. 10A through 10C is higher than the resistivity of most common materials used to form conductive lines such as aluminum, tungsten and copper. This is necessary in a measurement structure to ensure accurate voltage measurement.  
         [0042]    [0042]FIGS. 11 and 12 are cross-sectional views illustrating a method of forming contact to the structure of FIG. 10A through 10C to form a high precision polysilicon resistor according to the present invention. Particularly, the structure illustrated in FIG. 10A is used as an example in FIGS. 11 and 12.  
         [0043]    In FIG. 11, a second insulating layer  230  is formed top surface  185  of insulating layer  175 , over top surface  215 A of first conductive line  210 A and over top surface  215 B of second conductive line  210 B. In FIG. 12, a first via  240 A integrally formed with a first conductive wire  245 A by a dual damascene process contacts doped polysilicon region  225 A of first conductive line  210 A. A second via  240 B integrally formed with a second conductive wire  245 B by a dual damascene process contacts doped polysilicon region  225 B of second conductive line  210 B.  
         [0044]    [0044]FIG. 13 is a top view of a high precision polysilicon resistor according to the present invention. In FIG. 13, resistor  250  is a damascene conductive line fabricated from intrinsic polysilicon having a doped upper region  255 . Vias  260 A and  260 B contact ends  265 A and  265 B of resistor  250  respectively. Conductive wires  270 A and  270 B contact vias  265 A and  265 B respectively.  
         [0045]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.