Abstract:
A commanded negative-sequence current is added to a commanded current so as to suppress double-frequency pulsation on the DC side. The commanded negative-sequence current is found from three values (i.e., the detected value of positive-sequence voltage vector on the power-supply side, the detected value of negative-sequence voltage vector, and a commanded positive-sequence current). Thus, the pulsations which occur on the DC side of a semiconductor power converter and which have a frequency double the power-supply frequency are suppressed even when the AC power supply is at fault while assuring stability of the current control system, thus permitting stable and continuous operation.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a semiconductor power converter adapted to be run continuously even when the AC system side is at fault. 
         [0002]    In recent years, semiconductor power converteres have been applied in increasing fields and thus the necessity of maintaining continuous operation even when the AC system side is at fault is increasing. To cope with such a problem, a method of enhancing the capability for controlling the AC current is proposed in “Development of a Large-Scale Solar Power Generation System”,  Hitachi Review,  2009 March, Vol. 91, No. 03, pp. 56-59. 
       SUMMARY OF THE INVENTION 
       [0003]    This method, however, suffers from the disadvantage that when the AC power supply side is at fault, power pulsations of double power frequency produced on the DC side of the converter cannot be suppressed however much the current controlling performance is enhanced. 
         [0004]    The present invention is intended to provide a semiconductor power converter which suppresses pulsations having double frequency of the power supply frequency and produced on the DC side of the semiconductor power converter and which can continue to be run stably even when the AC power supply side is at fault. 
         [0005]    The above-described object is achieved in accordance with the teachings of the invention by providing a semiconductor power converter having: a power converter including arms constituting three-phase bridge connections having AC-side terminals which are connected with a three-phase AC system via an inductance, the arms having self-extinguishing semiconductor devices connected thereto, the self-extinguishing semiconductor devices being IGBTs or combinations of MOSFETs and free-wheeling diodes; a voltage-measuring device for measuring an AC voltage developed across the three-phase AC system; a current-measuring device for measuring an AC current flowing through the power converter; a phase detector for detecting the phase θ of the AC voltage; and an AC current adjuster for outputting commanded pulses to the power converter based on a commanded active current value I qref  and a commanded reactive current value I dref  along two axes and on an output from the AC current-measuring device. The semiconductor power converter further includes a two-phase voltage vector calculator for receiving a measured value of voltage developed across the three-phase AC system and calculating a positive-sequence voltage vector V p  and a negative-sequence voltage vector V n  and a phase calculator for calculating and outputting a positive-sequence voltage phase θ p  from a reference phase θ for the two-phase voltage vector calculator and from the positive-sequence voltage vector V p . The AC current adjuster calculates a commanded positive-sequence current vector I pref  from the commanded two-axis current values I qref  and I dref  and calculates a commanded negative-sequence current vector I qref  using the relationship, I nref =−(V n /V p )×I pref . Also, the AC current adjuster calculates commanded three-phase current vectors I aref , I bref , and I cref  from the commanded positive-sequence current vector I pref  and from the commanded negative-sequence current vector I nref , calculates commanded three-phase current values from the commanded three-phase current vectors and from the positive-sequence voltage phase θ p , and outputs commanded pulses to bring the commanded three-phase current values and the measured AC current values into agreement. 
         [0006]    In one feature of this semiconductor power converter according to the invention, there are further provided a three-phase voltage vector calculator for receiving the measured value of voltage of the three-phase AC system and outputting three-phase voltage vectors (V a , V b , V c ) and a target voltage calculator for calculating a target voltage vector E 1   aref  of a first phase from the AC voltage vector V a , the commanded current vector I aref , and the impedance value of the inductance, calculating a target voltage value e 1   aref  from the target voltage vector E 1   aref  and from the reference phase θ, and similarly calculating and outputting a target voltage value e 1   bref  of a second phase and a target voltage value e 1   cref  of a third phase. The AC current adjuster calculates and outputs correcting three-phase voltage values (e 2   aref , e 2   bref , e 2   cref ) to bring the commanded three-phase current values (i aref , i bref , i cref ) into agreement with the measured AC current values. The correcting three-phase voltage values (e 2   aref , e 2   bref , e 2   cref ) are added to the target three-phase voltage values (e 1   aref , e 1   bref , e 1   cref ), respectively, for each individual phase and the results are taken as commanded three-phase voltage values. Commanded pulses are output to bring the three-phase output voltages from the power converter into agreement with the commanded three-phase voltage values. 
         [0007]    In a further feature of this semiconductor power converter according to the invention, there are further provided a DC voltage-measuring device for measuring the DC output voltage from the power converter, a DC voltage adjuster for outputting a commanded first-axis current I qref  to bring the measured DC output voltage and the commanded DC voltage value into coincidence, a current vector calculator for receiving the measured value of AC current and calculating a positive-sequence current vector I p , and a power factor adjuster for calculating a positive-sequence reactive power output Q p  from the positive-sequence current vector I p  and from the positive-sequence voltage vector V p  and outputting a commanded second-axis current value I dref  to bring the positive-sequence reactive power output Q p  and the commanded reactive power value into coincidence. The commanded positive-sequence current vector I pref  is calculated from the commanded two-axis current values I qref  and I dref . 
         [0008]    In the present invention, the commanded negative-sequence currents are added to commanded currents to suppress pulsations of the double frequency on the DC side. The commanded negative-sequence currents are found from the detected value of the positive-sequence voltage vector on the power-supply side, the detected value of the negative-sequence voltage vector, and the commanded positive-sequence current. Thus, the problem is solved while maintaining the stability of the current control system. 
         [0009]    According to the present invention, a semiconductor power converter can be accomplished which can continue to be operated stably even when the AC power supply is at fault while suppressing pulsations of the double frequency of the power-supply frequency that are produced on the DC side of the converter. 
         [0010]    Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram of a semiconductor power converter, showing its structure. 
           [0012]      FIG. 2  is an internal circuit diagram of a power converter. 
           [0013]      FIG. 3  is a graph showing the operation of a pulse width modulator. 
           [0014]      FIG. 4  is a circuit diagram of a conversion controller, showing its structure. 
           [0015]      FIG. 5  is a circuit diagram of a recursive calculator. 
           [0016]      FIG. 6  is a circuit diagram of another conversion controller. 
           [0017]      FIG. 7  is a circuit diagram of a system controller. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    A semiconductor power converter connected with a three-phase alternating-current (AC) system operates to convert an AC-side active power p ac =V a ×i a +v b ×i b +v c ×i c  and a DC-side power p dc =v ac ×i dc  bidirectionally. If the internal loss of the apparatus is neglected, it follows that p ac =p dc . 
         [0019]    The relationships between voltage values, current values, voltage vectors, and current vectors for plural phases are now given by Eqs. (1) and (2). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       v 
                       k 
                     
                     = 
                     
                       
                         1 
                         2 
                       
                        
                       
                         [ 
                         
                           
                             
                               V 
                               k 
                             
                             · 
                             
                                
                               
                                 j 
                                  
                                 
                                     
                                 
                                  
                                 ω 
                                  
                                 
                                     
                                 
                                  
                                 t 
                               
                             
                           
                           + 
                           
                             
                               V 
                               k 
                               * 
                             
                             · 
                             
                                
                               
                                 
                                   - 
                                   jω 
                                 
                                  
                                 
                                     
                                 
                                  
                                 t 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                   , 
                   
                     k 
                     = 
                     a 
                   
                   , 
                   b 
                   , 
                   c 
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       i 
                       k 
                     
                     = 
                     
                       
                         1 
                         2 
                       
                        
                       
                         [ 
                         
                           
                             
                               I 
                               k 
                             
                             · 
                             
                                
                               
                                 j 
                                  
                                 
                                     
                                 
                                  
                                 ω 
                                  
                                 
                                     
                                 
                                  
                                 t 
                               
                             
                           
                           + 
                           
                             
                               I 
                               k 
                               * 
                             
                             · 
                             
                                
                               
                                 
                                   - 
                                   jω 
                                 
                                  
                                 
                                     
                                 
                                  
                                 t 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                   , 
                   
                     k 
                     = 
                     a 
                   
                   , 
                   b 
                   , 
                   c 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where * is a conjugate complex and e jωt  is a reference phase for vector calculations. 
         [0020]    It is assumed that positive-sequence V p  of voltage, positive-sequence I p  of current, negative-sequence V n  of voltage, and negative-sequence I n  of current are given by Eqs. (3) and (4). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       [ 
                       
                         
                           
                             
                               V 
                               a 
                             
                           
                         
                         
                           
                             
                               V 
                               b 
                             
                           
                         
                         
                           
                             
                               V 
                               c 
                             
                           
                         
                       
                       ] 
                     
                     = 
                     
                       
                         [ 
                         
                           
                             
                               1 
                             
                             
                               1 
                             
                           
                           
                             
                               α 
                             
                             
                               
                                 α 
                                 2 
                               
                             
                           
                           
                             
                               
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                                 2 
                               
                             
                             
                               α 
                             
                           
                         
                         ] 
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 V 
                                 p 
                               
                             
                           
                           
                             
                               
                                 V 
                                 n 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                   , 
                   
                     
                       [ 
                       
                         
                           
                             
                               V 
                               p 
                             
                           
                         
                         
                           
                             
                               V 
                               n 
                             
                           
                         
                       
                       ] 
                     
                     = 
                     
                       
                         
                           1 
                           3 
                         
                          
                         
                           [ 
                           
                             
                               
                                 1 
                               
                               
                                 
                                   α 
                                   2 
                                 
                               
                               
                                 α 
                               
                             
                             
                               
                                 1 
                               
                               
                                 α 
                               
                               
                                 
                                   α 
                                   2 
                                 
                               
                             
                           
                           ] 
                         
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 V 
                                 a 
                               
                             
                           
                           
                             
                               
                                 V 
                                 b 
                               
                             
                           
                           
                             
                               
                                 V 
                                 c 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       [ 
                       
                         
                           
                             
                               I 
                               a 
                             
                           
                         
                         
                           
                             
                               I 
                               b 
                             
                           
                         
                         
                           
                             
                               I 
                               c 
                             
                           
                         
                       
                       ] 
                     
                     = 
                     
                       
                         [ 
                         
                           
                             
                               1 
                             
                             
                               1 
                             
                           
                           
                             
                               α 
                             
                             
                               
                                 α 
                                 2 
                               
                             
                           
                           
                             
                               
                                 α 
                                 2 
                               
                             
                             
                               α 
                             
                           
                         
                         ] 
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 I 
                                 p 
                               
                             
                           
                           
                             
                               
                                 I 
                                 n 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                   , 
                   
                     
                       [ 
                       
                         
                           
                             
                               I 
                               p 
                             
                           
                         
                         
                           
                             
                               I 
                               n 
                             
                           
                         
                       
                       ] 
                     
                     = 
                     
                       
                         
                           1 
                           3 
                         
                          
                         
                           [ 
                           
                             
                               
                                 1 
                               
                               
                                 
                                   α 
                                   2 
                                 
                               
                               
                                 α 
                               
                             
                             
                               
                                 1 
                               
                               
                                 α 
                               
                               
                                 
                                   α 
                                   2 
                                 
                               
                             
                           
                           ] 
                         
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 I 
                                 a 
                               
                             
                           
                           
                             
                               
                                 I 
                                 b 
                               
                             
                           
                           
                             
                               
                                 I 
                                 c 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where α is given by Eq. (5). 
         [0000]    
       
         
           
             
               
                 
                   α 
                   = 
                   
                      
                     
                       
                         - 
                         j 
                       
                        
                       
                         2 
                         3 
                       
                        
                       π 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0021]    From Eqs. (1), (2), (3), and (4), the AC-side active power p ac  is given by (6). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           p 
                           ac 
                         
                         = 
                           
                          
                         
                           
                             
                               v 
                               a 
                             
                              
                             
                               i 
                               a 
                             
                           
                           + 
                           
                             
                               v 
                               b 
                             
                              
                             
                               i 
                               b 
                             
                           
                           + 
                           
                             
                               v 
                               c 
                             
                              
                             
                               i 
                               c 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               1 
                               12 
                             
                              
                             
                               { 
                               
                                 
                                   [ 
                                   
                                     
                                       
                                         V 
                                         p 
                                       
                                        
                                       
                                         I 
                                         p 
                                         * 
                                       
                                     
                                     + 
                                     
                                       
                                         V 
                                         n 
                                       
                                        
                                       
                                         I 
                                         n 
                                         * 
                                       
                                     
                                   
                                   ] 
                                 
                                 + 
                                 
                                   [ 
                                   
                                     
                                       
                                         V 
                                         p 
                                         * 
                                       
                                        
                                       
                                         I 
                                         p 
                                       
                                     
                                     + 
                                     
                                       
                                         V 
                                         n 
                                         * 
                                       
                                        
                                       
                                         I 
                                         n 
                                       
                                     
                                   
                                   ] 
                                 
                               
                               } 
                             
                           
                           + 
                         
                       
                     
                   
                   
                     
                       
                           
                          
                         
                           
                             1 
                             12 
                           
                            
                           
                             { 
                             
                               
                                 
                                   [ 
                                   
                                     
                                       
                                         V 
                                         p 
                                       
                                        
                                       
                                         I 
                                         n 
                                       
                                     
                                     + 
                                     
                                       
                                         V 
                                         n 
                                       
                                        
                                       
                                         I 
                                         p 
                                       
                                     
                                   
                                   ] 
                                 
                                  
                                 
                                    
                                   
                                     2 
                                      
                                     j 
                                      
                                     
                                         
                                     
                                      
                                     ω 
                                      
                                     
                                         
                                     
                                      
                                     t 
                                   
                                 
                               
                               + 
                               
                                 
                                   [ 
                                   
                                     
                                       
                                         V 
                                         p 
                                         * 
                                       
                                        
                                       
                                         I 
                                         n 
                                         * 
                                       
                                     
                                     + 
                                     
                                       
                                         V 
                                         n 
                                         * 
                                       
                                        
                                       
                                         I 
                                         p 
                                         * 
                                       
                                     
                                   
                                   ] 
                                 
                                  
                                 
                                    
                                   
                                     
                                       - 
                                       2 
                                     
                                      
                                     jω 
                                      
                                     
                                         
                                     
                                      
                                     t 
                                   
                                 
                               
                             
                             } 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0022]    It can be seen from Eq. (6) above that a condition under which pulsations of the double-frequency components of the power supply disappear is given by (7). 
         [0000]        V   p   I   n   +V   n   I   p =0  (7)
 
         [0023]    In order to satisfy the equation given by Eq. (7), it is necessary to adopt a simple control method of securing high responsiveness without impairing the stability. 
         [0024]    In the present invention, positive-sequence and negative-sequence voltages are measured as disturbances not affected by the power converter for the sake of simplicity. Furthermore, a commanded two-axis positive-sequence current is divided into a q-axis component in phase with the positive-sequence voltage V p  and a d-axis component orthogonal to the positive-sequence voltage V p  as usual. 
         [0025]    Furthermore, for the sake of simplicity, it is assumed that the current control system shows a sufficiently high response and that Eq. (8) holds. 
         [0000]        I   pref   =I   p   (8)
 
         [0026]    Based on the assumption made thus far, the present invention is characterized in that a commanded negative-sequence current is calculated using Eq. (9). 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     nref 
                   
                   = 
                   
                     
                       - 
                       
                         
                           V 
                           n 
                         
                         
                           V 
                           p 
                         
                       
                     
                      
                     
                       I 
                       pref 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0027]    The commanded current I ref  is given by Eq. (10). 
         [0000]        I   ref   =I   pref   +I   nref   (10)
 
         [0028]    In accomplishing the relationship given by Eq. (9), it is necessary to select commanded two-axis positive-sequence currents such that the commanded positive-sequence current I pref  and the commanded negative-sequence current I nref  are prevented from interfering with each other; otherwise, instability would occur. 
         [0029]    In the past, the commanded q-axis current has been so controlled that the DC-side voltage v dc  matches the set value. Let C be the capacity of a capacitor on the DC side. The relationship of AC-side positive-sequence active power P p , negative-sequence active power P n , and DC-side power P dc  is given by Eq. (11). 
         [0000]    
       
         
           
             
               
                 
                   
                     C 
                      
                     
                        
                       
                          
                         t 
                       
                     
                      
                     
                       v 
                       dc 
                     
                   
                   = 
                   
                     
                       1 
                       
                         v 
                         dc 
                       
                     
                      
                     
                       ( 
                       
                         
                           P 
                           p 
                         
                         + 
                         
                           P 
                           n 
                         
                         - 
                         
                           P 
                           dc 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0030]    Only the positive-sequence active power P p  out of the three terms of the right side of Eq. (11) can be adjusted by the commanded q-axis current i qref . However, it is considered that the negative-sequence active power P n  and the DC-side power P dc  are independent of the positive-sequence active power P p  and that if the commanded q-axis current is controlled by the DC-side voltage v ac  in a conventional manner, neither stability nor responsiveness will be affected. 
         [0031]    On the other hand, the commanded d-axis current i dref  has been so controlled that the AC-side reactive power matches the commanded value, whether the commanded reactive power is computed from the commanded power factor or the commanded reactive power is directly used. 
         [0032]    In the present invention, the commanded negative-sequence current I nref  is added and, therefore, the commanded positive-sequence current I pref  and the commanded negative-sequence current I nref  interfere with each other via negative-sequence reactive power due to the negative-sequence voltage and negative-sequence current. To prevent this, positive-sequence reactive power Q p  owing to the positive-sequence voltage and positive-sequence current is used as a measured value of reactive power that is employed for control of the d-axis current, according to one feature of the invention. 
         [0033]    As described so far, in the present invention, the commanded negative-sequence current I nref  is used in addition to the commanded positive-sequence current I pref . In particular, commanded three-phase currents are computed using Eqs. (12) and (13) based on Eqs. (2) and (4). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       i 
                       kref 
                     
                     = 
                     
                       
                         1 
                         2 
                       
                        
                       
                         [ 
                         
                           
                             
                               I 
                               kref 
                             
                             · 
                             
                                
                               
                                 j 
                                  
                                 
                                     
                                 
                                  
                                 
                                   θ 
                                   p 
                                 
                               
                             
                           
                           + 
                           
                             
                               I 
                               kref 
                               * 
                             
                             · 
                             
                                
                               
                                 - 
                                 
                                   jθ 
                                   p 
                                 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                   , 
                   
                     k 
                     = 
                     a 
                   
                   , 
                   b 
                   , 
                   c 
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
             
               
                 
                   
                     [ 
                     
                       
                         
                           
                             I 
                             aref 
                           
                         
                       
                       
                         
                           
                             I 
                             bref 
                           
                         
                       
                       
                         
                           
                             I 
                             cref 
                           
                         
                       
                     
                     ] 
                   
                   = 
                   
                     
                       
                         [ 
                         
                           
                             
                               1 
                             
                             
                               1 
                             
                           
                           
                             
                               α 
                             
                             
                               
                                 α 
                                 2 
                               
                             
                           
                           
                             
                               
                                 α 
                                 2 
                               
                             
                             
                               α 
                             
                           
                         
                         ] 
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 I 
                                 pref 
                               
                             
                           
                           
                             
                               
                                 I 
                                 nref 
                               
                             
                           
                         
                         ] 
                       
                     
                     = 
                     
                       
                         [ 
                         
                           
                             
                               1 
                             
                             
                               1 
                             
                           
                           
                             
                               α 
                             
                             
                               
                                 α 
                                 2 
                               
                             
                           
                           
                             
                               
                                 α 
                                 2 
                               
                             
                             
                               α 
                             
                           
                         
                         ] 
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 
                                   I 
                                   qref 
                                 
                                 - 
                                 
                                   j 
                                   · 
                                   
                                     i 
                                     dref 
                                   
                                 
                               
                             
                           
                           
                             
                               
                                 I 
                                 nref 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0034]    Note that θ p  of Eq. (12) is the positive-sequence voltage phase varying at the positive-sequence voltage frequency. The commanded current of Eq. (12) varies at the power-supply frequency. Owing to improvement of microprocessor performance, the period at which the current control system performs calculations can be made shorter. Therefore, if the commanded value varies at the power-supply frequency, the problem of instability due to digitization can be avoided. 
         [0035]    However, as the frequency of the commanded current value goes higher, the output of the integrator constituting the control system varies over a wider range than where the command value is a DC, whether the current controlling and calculating means is analog or digital. Consequently, it is still difficult to afford sufficient latitude in providing control in the presence of external disturbances. 
         [0036]    To alleviate this problem, in another feature of the present invention, a target value of output voltage e 1   ref  is computed using Eqs. (14) and (15) by the use of the positive-sequence voltage vector V p , a measured value of negative-sequence voltage vector V n , a commanded positive-sequence current I pref , a commanded negative-sequence current I nref , and the impedance Z of the inductance of the AC power supply. The computed value is taken as a feedforward control command and added to the correcting voltage value e 2   ref  of the output from a feedback current control system. 
         [0000]    
       
         
           
             
               
                 
                   
                     [ 
                     
                       
                         
                           
                             E 
                              
                             
                                 
                             
                              
                             
                               1 
                               aref 
                             
                           
                         
                       
                       
                         
                           
                             E 
                              
                             
                                 
                             
                              
                             
                               1 
                               bref 
                             
                           
                         
                       
                       
                         
                           
                             E 
                              
                             
                                 
                             
                              
                             
                               1 
                               cref 
                             
                           
                         
                       
                     
                     ] 
                   
                   = 
                   
                     
                       [ 
                       
                         
                           
                             1 
                           
                           
                             1 
                           
                         
                         
                           
                             α 
                           
                           
                             
                               α 
                               2 
                             
                           
                         
                         
                           
                             
                               α 
                               2 
                             
                           
                           
                             α 
                           
                         
                       
                       ] 
                     
                      
                     
                       { 
                       
                         
                           [ 
                           
                             
                               
                                 
                                   V 
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       Embodiments 
       [0037]    An embodiment of the present invention is hereinafter described with reference to  FIGS. 1-4 . 
         [0038]    Referring to  FIG. 1 , a semiconductor power converter  1000  has an alternating-current (AC) system  10  that is connected with a filter circuit  18  for harmonic suppression via a transformer  11 , an instrument transformer  12 , an instrument current transformer  13 , a circuit breaker  14 , a contactor  15 , initial charging current limiting resistors  16  connected in parallel with the contactor  15 , and another contactor  17 . The filter circuit  18  is connected with the AC side of a power converter  30  via an inductance  19  for harmonic suppression. A capacitor  40  and a DC voltage-measuring instrument  41  are connected with the DC side of the power converter  30 . 
         [0039]    The power converter  30  has 6 arms (UP, VP, WP, UN, VN, and WN) arranged to form three-phase bridge connections. Each of the arms has a self-extinguishing semiconductor power conversion device and a diode (free-wheeling diode) connected anti-parallel with the conversion device. The converter  30  is controllably turned on and off by commanded pulse width modulations (M_U, M_V, and M_W). The internal configuration of the power converter  30  will be described later by referring to  FIG. 2 . 
         [0040]    A system controller  20  controls the semiconductor power converter  1000  constructed as described so far. Line voltage signals  21  (v a-b , v b-c , v c-a ) about the instrument transformer  12 , current signals  22  (i ga , i gb , i gc ) for the instrument current transformer, and a DC voltage signal  23  (v dc ) for the DC voltage-measuring instrument  41  are applied to the system controller  20 , which in turn outputs an open/close command signal  24  for the circuit breaker  14 , an open/close command  25  for the contactor  15 , and an open/close command  26  for the contactor  17 . Furthermore, the controller  20  delivers the line voltage signals  21  (v a-b , v b-c , v c-a ) and a commanded two-axis current  61  (I pref ) to a current converter controller  50 . In addition, the controller  20  outputs a gate block-canceling signal  65  (GDB) to the power converter  30 . 
         [0041]    The converter controller  50  receives input AC currents  63  (i a , i b , i c ) from an instrument current transformer  62  and outputs commanded pulse width modulations  64  (M_U, M_V, M_W) to the power converter  30  to bring the input currents into agreement with commanded three-phase current values (i aref , i bref , i cref ), corresponding to the commanded two-axis current  61  (I pref ). 
         [0042]    In the present embodiment, a second power converter  70  acts as a DC-side load for the semiconductor power converter  1000  and has DC-side terminals connected across the capacitor  40 . The second power converter  70  further includes an AC-side terminal connected with a permanent-magnet power generator  80  via an instrument current converter  71 , an instrument transformer  72 , and an AC inductance  81 . A phase detector  82  is directly coupled to the rotating shaft of the power generator. A drive control unit  73  receives a phase signal from the phase detector  82 , a current signal from the instrument current transformer  71 , and a voltage signal from the instrument transformer  72  and controls the second power converter  70  with a commanded pulse width modulations  74 . 
         [0043]    When the semiconductor power converter  1000  is set into operation by the structure constructed as described so far, the circuit breaker  14  is closed by the open/close command  24  from the system controller  20 . The contactor  15  is opened by the open/close command  25 . Under this condition, the contactor  17  is closed by manipulating the open/close command  26 . 
         [0044]    When electrical charging is completed, the contactor  17  is opened by the open/close command  26 . Subsequently, the contactor  15  is closed by the open/close command  25 . Thus, preparations for the operation are completed. 
         [0045]    The gate block canceling signal  65  (GDB) is set on (level 1) to enable operation of the power converter  30 . 
         [0046]    The commanded two-axis current  61  is so adjusted that charging is continued until the DC voltage  23  (V dc ) from the DC voltage detector  41  reaches a given value. 
         [0047]    When the power converter  30  is set into operation, the system controller  20  computes a commanded quadrature-axis current I qref  such that the DC voltage  23  (v dc ) becomes equal to the set value. Furthermore, the controller  20  calculates a commanded direct-axis current I dref  such that the power factor computed from the AC voltage signal  21  and from the system current signals  22  (I ga , I gb , I gc ) becomes unity. The controller  20  outputs the commanded two-axis current  61  (I pref =I qref −j×I dref ) to the converter controller  50 . 
         [0048]    The internal configuration of the first power converter  30  is described by referring to  FIG. 2 . Gate controllers  301 ,  302 , and  303  receive the commanded pulse width modulations (M_U, M_V, M_W) from the converter controller  50  and output gate signals G_UP, G_UN, G_VP, G_VN, G_WP, and G_WN to the self-extinguishing devices. Since the gate controllers  301 ,  302 , and  303  of the different phases are identical in configuration and operation, only the gate controller  301  of phase U is described below. 
         [0049]      FIG. 3  illustrates the operation of the gate controller  301 . The commanded pulse width modulation M_U is used as a modulating wave and compared in terms of magnitude with a carrier wave in the form of a triangular wave. Where the commanded pulse M_U is larger, the commanded pulse P_U is set ON (level 1). Where the commanded pulse M_U is equal to unity (M_U=1), the pulse P_U is kept ON. Where the pulse M_U=0, the pulse P_U is kept OFF (level 0). Where the pulse M_U=0.5, the ON period is equal to the OFF period. The commanded pulse P_U is branched and applied to a delay circuit  302  having a delay time of Td. The output and pulse P_U are applied to an AND logic circuit  303  to prevent simultaneous energization of the arms UP and UN; otherwise, the capacitor  40  would be shorted. 
         [0050]    On the other hand, the gate block-canceling signal GDB_U from the system controller  20  outputs an ON signal (level 1) at normal times. If any fault is detected, the controller outputs an OFF signal (level 0). The canceling signal GDB_U and the output from the AND logic circuit  303  are applied to an AND logic circuit  304 , which in turn outputs a gating signal G_UP to the self-extinguishing device on the arm UP. In consequence, the gating signal G_UP can be set OFF by setting OFF the canceling signal GDB_U from the system controller  20  irrespective of the signal from the AND logic circuit  303 . 
         [0051]    On the other hand, the gating signal P_N to the self-extinguishing device on the arm UN inverts (turns ON or OFF) the commanded pulse P_U through a NOT logic circuit  305  and is branched and applied to a delay circuit  306  with delay time Td. This output and the output from the NAND circuit  305  are applied to an AND logic circuit  307 . The gate block-canceling signal GDB_U from the system controller  20  and the output from the AND logic circuit  307  are applied to an AND logic circuit  308  whose output is applied as the gating signal G_UN to the self-extinguishing device on the arm UN. 
         [0052]      FIG. 4  shows the configuration of the current converter controller  50 . 
         [0053]    The line voltage signals  21  (v a-b , v b-c , v c-a ) from the instrument transformer  12  are converted into phase voltage signals  101  (v a ),  102  (v b ), and  103  (v c ) by means of subtractors  55  and coefficient multipliers  56  and applied to three recursive calculators  100 . The configuration of the recursive calculators  100  will be described by referring to  FIG. 5 . 
         [0054]    Each recursive calculator  100  is driven by timer pulses  120  from a timer circuit  110 . A first Fourier coefficient generator  200  is driven by the timer pulses  120 . A shift register  210  is stepped whenever one timer pulse  120  arrives. Data items in N constant memory cells  220  constituting a ring memory are output as the coefficient data  230  one by one in address order and input into the recursive calculators  100 . Each one recursive calculator  100  is provided for each of three-phase phase voltage signals. The recursive calculators  100  deliver phase voltage vector calculation results  241 ,  242 , and  243 . The recursive calculators  100  are so configured that the vector calculation results constitute the fundamental frequency component of a recursive discrete Fourier transform of period N. 
         [0055]    A positive-sequence voltage vector  51  (V p ) and a negative-sequence voltage vector  52  (V n ) are produced from the phase voltage vector calculation results  241 ,  242 , and  243  by means of coefficient multipliers  271 ,  272 ,  273  and adders  274 . 
         [0056]    A positive-sequence voltage vector  276  rotating at the positive-sequence voltage frequency is produced from the positive-sequence voltage vector  51  (V p ) by a vector reference phase  54  [exp(j·θ)] from a second Fourier coefficient generator  250  and by a multiplier  275 . A deflection angle calculator  450  delivers the positive-sequence voltage phase  277  [exp(j·θ p )]. 
         [0057]    The second Fourier coefficient generator  250  is driven by the timer pulses  140  from a timer circuit  130 . The timer circuit  130  produces pulses  131  of an m-times higher frequency (where m is a natural number) synchronized with the timer pulses  120 . The second Fourier coefficient generator  250  steps a shift register  260  in response to each timer pulse  140 . Data items in M (=m×N) constant memory cells  270  constituting a ring memory are output as the vector reference phase  54  [exp(j·θ)] one by one in address order. 
         [0058]    When the timer pulses  120  and timer pulses  140  overlap once per m times, the first Fourier coefficient generator  200  and the second Fourier coefficient generator  250  are so adjusted that the coefficient data  230  and the vector reference phase  54  [exp(j·θ)] have a conjugate relationship to one another. 
         [0059]    To calculate a commanded negative-sequence current  53  (I nref ) from the positive-sequence voltage vector  51  (V p ), the negative-sequence voltage vector  52  (V n ), and the commanded positive-sequence current  61  (I pref ) by the use of Eq. (9), a divider  401 , a multiplier  402 , and a coefficient multiplier  403  are connected. 
         [0060]    To calculate command current vectors  421  (I aref ),  422  (I bref ),  423  (I cref ) of various phases through the use of Eq. (13), coefficient multipliers  431 ,  432  and adders  434  are connected. 
         [0061]    To compute commanded current values  441  (i aref ),  442  (i bref ), and  443  (i cref ) of various phases using Eq. (12), they are multiplied by the positive-sequence voltage phase  277  [exp(j·θ p )] by means of their respective multipliers  452 . Selectors  460  for selecting the real part outputs are connected. 
         [0062]    The commanded current values  441  (i aref ),  442  (i bref ), and  443  (i cref ) of the various phases are combined with the input AC currents  63  (i a , i b , i c ) from the instrument current transformer  62  by means of subtractors  461  for each phase and applied to their respective current control circuits  470  each made of a proportional integrator circuit. The control circuits  470  deliver voltage correcting values  58  (e 2   aref ),  59  (e 2   bref ), and  60  (e 2   cref ), respectively. In the case of the present embodiment, the voltage correcting values  58  (e 2   aref ),  59  (e 2   bref ), and  60  (e 2   cref ) are output as the pulse width modulation commands  64  (M_U, M_V, and M_W). 
         [0063]    According to the embodiment of the present invention, the commanded current values  441  (i aref ),  442  (i bref ), and  443  (i cref ) of the various phases are updated whenever each timer pulse  140  arrives. Since these values provide a voltage frequency signal varying in finer steps than obtained by recursive discrete Fourier calculation results varying at the intervals of the timer pulses  120 , there is the advantage that the harmonics of the semiconductor power converter are reduced. 
         [0064]      FIG. 5  shows the configuration of each recursive calculator  100 . 
         [0065]    In the present embodiment, three recursive calculators of the configuration of  FIG. 5  are connected. Since the calculators of the phases are identical in configuration, the recursive calculator for phase voltage a is taken as an example below. 
         [0066]    The input voltage signal  101  (v a ) of phase voltage a is sampled by a sampler  151  synchronized with the timer pulses  120  delivered at regular intervals of T. The resulting data is digitized by a sample-and-hold circuit  152  and an A/D converter  153  and output to a data table  160 . 
         [0067]    The data table  160  is made up of (N+1) data memory cells  161  and N shift registers  162 . Input data items (x 0 , x 1 , x 2 , . . . , x N ) are recorded in the shift registers  162  in turn from address #(N) toward #(0) in synchronism with the timer pulses  120 . In particular, there is a method of shifting data from memory address #(N−1) to #(N) and then from #(N−2) to #(N−1) and finally from #(0) to #(1). The newest input data item  163  (x N ) and data item  164  (x 0 ) occurring N samples earlier are read from the data table. 
         [0068]    The difference between the newest input data item  163  (x N ) and the data item  164  (x 0 ) occurring N samples earlier is delivered from a subtractor  165  and multiplied by coefficient data  230  from the first Fourier coefficient generator  200  by means of a multiplier  166 . The resulting product is added to the previous value written at the memory address #(1) of a shift memory  167  for phase voltage vector calculation results by means of an adder  168 . Phase voltage vector calculation results  240  are output via a coefficient multiplier  170 . 
         [0069]    The shift memory  167  for phase voltage vector calculation results acts to shift data using a shift register  169  synchronized with the timer pulses  120 . 
         [0070]    Another embodiment of the present invention is next described by referring to  FIG. 6 . 
         [0071]    A converter controller  50 - 1  is identical with the counterpart shown in  FIG. 4  and thus its description is omitted for brevity. Target output voltage vectors of positive and negative-sequences are calculated from the positive-sequence voltage vector  51  (V p ), negative-sequence voltage vector  52  (V n ), commanded positive-sequence current  61  (I pref ), and commanded negative-sequence current  53  (I nref ) using Eq. (14). 
         [0072]    First, in order to rotate the commanded positive-sequence current  61  (I pref ) and the commanded negative-sequence current  53  (I nref ) through a deflection angle of the positive-sequence voltage vector  51  (V p ), the deflection angle of the positive-sequence voltage vector  51  (V p ) is output from a deflection angle calculator  681 . The commanded positive-sequence current  61  (I pref ) is rotated by a multiplier  682 . The commanded negative-sequence current  53  (I nref ) is rotated by a multiplier  683 . These are connected with multipliers  601  and subtractors  602 . The output from each constant generator  603  corresponds to the impedance of the AC inductance  19 . To calculate the target output voltage vectors of the various phases from a target positive-sequence voltage vector  604  and a target negative-sequence voltage vector  605 , coefficient multipliers  611 ,  612 ,  613  and adders  621 ,  622 ,  623  are connected. To calculate target phase-voltage values  631  (e 1   aref ),  632  (e 1   bref ), and  633  (e 1   cref ) using Eq. (15), the vector reference phase  54  [exp(j·θ)] from the second Fourier coefficient generator  250  is subjected to multiplications using multipliers  641 ,  642 , and  643 , respectively. Selectors  651 ,  652 , and  653  for selectively outputting the real parts are connected. 
         [0073]    In response to the correcting voltage values  58  (e 2   aref ),  59  (e 2   bref ), and  60  (e 2   cref ) that are feedback control outputs from the current control circuits  470 , the target phase-voltage values  631  (e 1   aref ),  632  (e 1   bref ), and  633  (e 1   cref ) are feedforward control outputs. These are summed up by adders  661 ,  662 , and  663  for each phase, producing results  671  (e aref ),  672  (e bref ), and  673  (e cref ) which are output as the pulse width modulation commands  64  (M_U, M_V, and M_W). 
         [0074]    According to the present embodiment, phase-voltage vectors of the various phases are computed from the positive-sequence voltage vector  51  (V p ) and the negative-sequence voltage vector  52  (V n ) without directly using the phase-voltage vector calculation results  241 ,  242 , and  243 . This produces the effect that oscillations due to errors of the vector calculation results when the voltage frequency deviates from the reference frequency are compressed. 
         [0075]    A further embodiment of the invention is next described by referring to  FIG. 7 . 
         [0076]    With respect to voltage signals, the line voltage signals  21  (v a-b , v b-c , and v c-a ) from the instrument transformer  12  are computationally processed by the subtractors  55  and the coefficient multipliers  56 , providing outputs of the phase-voltage signals  1010  (v a ),  1020  (v b ), and  1030  (v c ). With respect to current signals, the current signals  22  (i a , i b , and i c ) from the instrument current transformer  13  are input. 
         [0077]    A reference phase generator  700  is driven by a timer circuit  710 . Timer pulses  711  are in synchronism with the computational cycle of the system controller  20 . A shift register  712  is shifted whenever each timer pulse  711  arrives. Data items in K constant memory cells  701  constituting a ring memory are output as coefficient data items  731  one by one in address order. Similarly, coefficient data items  732  and  733  which are shifted in phase from the coefficient data items  731  by ±2π/3 are output. Two-axis converted voltage and current vectors  761  and  762  are calculated by an instantaneous value symmetrical component method using multipliers  741 ,  742 ,  743 ,  744 ,  745 ,  746  and adders  751 ,  752 . 
         [0078]    When the voltage vector  761  and the current vector  762  obtained by the instantaneous value symmetrical component method are applied to moving average calculation circuits  771  and  772 , respectively, which output the moving averages of K data items in synchronism with the timer pulses  711 , a positive-sequence voltage vector  782  (V p ) and a positive-sequence current vector  783  (I p ) are output. The results are equal to the fundamental wave component of a recursive discrete Fourier transform of period K. 
         [0079]    The moving average calculation circuits  771  and  772  are identical in configuration and so only the circuit  771  is described below. 
         [0080]    It is assumed that the moving average calculation circuit  771  is made up of (K+1) data memory cells  772  and K shift registers  774 . Input data items (x 0 , x 1 , x 2 , . . . , x K ) are recorded in the shift registers  774  in turn from address #(K) toward #(0) in synchronism with the timer pulses  711 . In particular, there is a method of shifting each data item from memory address #(K−1) to #(K) and then from #(K−2) to #(K−1) and finally from #(0) to #(1). The newest input data item  775  (x K ) and data item  776  (x 0 ) occurring N samples earlier are read from the data table. The difference between them is applied to a subtractor  777  and added to the memory address #(1) in a shift memory  778  by means of an adder  779 . The shift memory  778  is synchronized with a shift register  780 . The memory address #(1) is the previous value of the additive operation results. The output from the adder  779  is multiplied by a factor of (1/K) by a coefficient multiplier  781 , and the moving average calculation results  782  are output. The calculation results  782  give the positive-sequence voltage vector (V p ). 
         [0081]    The positive-sequence current vector  783  (I p ) is calculated by the moving average calculation circuit  772  in the same way as for the positive-sequence voltage vector  782  (V p ). In order to calculate a positive-sequence reactive power  790  from the positive-sequence voltage vector  782  (V p ) and from the positive-sequence current vector  783  (I p ), a conjugate complex calculator  791 , a multiplier  792 , and a selector  793  for selecting outputting the imaginary part are connected. 
         [0082]    Out of the commanded two-axis current  61  (I pref =I qref −j×I dref ), the quadrature-axis component  810  (I qref ) causes a commanded DC voltage  811  (v dcref ) to be compared with the DC voltage signal  23  (v dc ) by means of a subtractor  812 . The result is applied to a DC voltage adjuster (AVR)  813  and is output. 
         [0083]    A commanded direct-axis current  820  (I dref ) causes a commanded reactive power  821  and the positive-sequence reactive power  790  (Q p ) to be compared with each other by a subtractor  822 . The result is applied to a reactive power adjuster  823  (AQR) and is output. 
         [0084]    The commanded quadrature-axis current  810  (I qref ) and the commanded direct-axis current  820  (I dref ) are coupled to a coefficient multiplier  832  and a subtractor  833 , respectively, and the commanded positive-sequence current  61  (I pref ) is output. 
         [0085]    According to the embodiments of the present invention, the results of calculation performed by the instantaneous value symmetrical component method are moving-averaged. Then, positive-sequence vectors are calculated by discrete Fourier transform. This creates the advantage that the same calculational results can be obtained with a small amount of data memory. 
         [0086]    It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.