Abstract:
A circuit supplies a current (I) in which the current variations (I L ) having been equalized according to a given relationship. In order to obtain an equalization characteristic having at least two slopes, the circuit uses the switching of the current sources (xI o , yI o  and zI o ) by means of switching stages (T 1 , T 2 , T 14 ). The output current I passing through the current output stages T 3  and T 4  thus fluctuates between two levels according to the desired equalizing relationship.

Description:
BACKGROUND OF THE INVENTION 
     The present invention has for its object to provide an equalizing circuit intended for producing an output current which has a given current characteristic as a function of the value of an input current the current characteristic having a maximum and a minimum value, which circuit comprises a means for producing a first current which is proportional to the input current, connected in series with a first current source producing a second current which is proportional to a reference current, in order to produce a first resulting current which is positive when the first current is higher than the second current and zero in the opposite case, a first switching stage arranged for being non-conductive when the first resulting current is zero, and passed through thereby when it is positive a second switching stage arranged for being passed through by the same current as the first switching stage, a second current source arranged for supplying a third current which is proportional to the reference current and connected in series with the second switching stage, in a manner such as to generate a second resulting current which is positive when the third current is higher than the resulting first current, a third switching stage arranged for not conducting when the second resulting current is zero, and passed through thereby when it is positive a first current output stage arranged for supplying a current which is equal to the current passing through the third switching stage and a second current output stage connected in parallel with the first current output stage arranged for supplying a current which is equal to the reference current, whose value is thus the said minimum value of the output current characteristic. 
     Such a circuit has been used for effecting a gain control of a telephone receiver, which circuit is commercially available referenced as TEA 1061. 
     A circuit having the same object but having a different structure has also been described in the U.S. Pat. No. 3,810,032. 
     The two circuits enable obtaining a current which linearly depends on an input current, between a bottom and a top limit. Such circuits are used specifically in subscriber telephone sets which are fed with a given voltage, generally 48 volts, from an exchange, the current which the subscriber terminal disposes of being smaller the more remote from the exchange the terminal is situated. In order to make the sensitivity of the telephone set independent of the length of the subscriber line and thus homogenize the listening level among the subscribers the subscriber set comprises an amplifier stage whose gain ratio depends on the current supplied and the above supply current is provided by an equalizing circuit fed by the line current, the equalization being effected according to a linear relationship as near to the theoretical curve as possible. 
     However, if the lines are very long and/or when moderate lengths of line sections are used, the theoretical curve stretches out over a larger dynamic range and tends to become more curved. 
     The above linear equalization is thus no longer sufficiently precise, which is unfavorable for certain subscriber stations. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to eliminate this disadvantage by proposing a circuit which basically provides an equalization having at least two linear regions with different slopes, in order to approach such curves more particularly but not exclusively with sufficient precision, or to approach the more conventional curves with greater precision. 
     The arrangement according to the invention is characterized in that it comprises at least an equalizing circuit connected in parallel with one of the first and second switching circuits and comprising on the one hand a third current source arranged for supplying a fourth current which is proportional to the reference current, connected in series with a fourth current source arranged for supplying a current in proportion to the current supplied by a first switching stage and on the other a blocking circuit arranged for connecting the fourth current source in parallel with at least one of the first and second switching circuits when the current passing through the fourth current source is larger than the fourth current. 
     According to an embodiment of the invention, the first switching circuit comprises a first transistor whose collector-emitter path is connected in parallel with the first current source and a second transistor whose base-emitter path is connected in parallel with the collector-emitter path of the first transistor, and the second switching stage comprises a third transistor whose base is connected to that of the first transistor. The third switching circuit may comprise a fourth transistor whose collector-emitter path is connected in parallel with the second switching stage and a fifth transistor whose base-emitter path is connected in parallel with the collector-emitter path of the fourth transistor and the first output stage may comprise a sixth transistor whose base is connected to that of the fourth transistor. 
     Thus the desired result is achieved with a circuit which remains simple and the parameters of the circuit (slopes, slope changes) can be adjusted without any difficulty. 
     According to an advantageous embodiment at least one blocking circuit comprises a first diode connected in series with the said means for supplying the first current which is proportional to the input current, and second and third diodes connected in parallel with the fourth current source. An equalization curve is thus obtained having two slopes corresponding, more specifically, with the curves drawn for the subscriber stations. 
     According to an embodiment, at least one blocking circuit comprises a fourth diode connected in series with the second current source and fifth and sixth diodes connected in parallel with the fourth current source. 
     According to a preferred embodiment, corresponding with an equalization having three slopes corresponding, more specifically, with the case of the subscriber stations, two equalizing circuits are connected in parallel with the first switching circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be better understood when reading the following description given by way of non-limiting example, together with the drawing Figures, in which: 
     FIG. 1 shows a prior-art gain control circuit, 
     FIG. 2 shows a circuit for producing a current at a given ratio to the line current, 
     FIG. 3 shows a gain control circuit according to a first embodiment of the invention, 
     FIG. 4 shows the curves representing the gain characteristic plotted against the line current for a circuit arrangement shown in FIG. 3 and 
     FIG. 5 shows the curve comprising two sloping lines of the circuit as shown in FIG. 3 adapted to the profile of a given equalization curve, 
     FIG. 6 shows a gain control circuit according to a second embodiment of the invention, 
     FIG. 7 shows a curve representing the gain characteristic plotted against the line current for a circuit as shown in FIG. 6 and 
     FIG. 8 shows the curve comprising two sloping lines of the circuit of FIG. 6 adapted to a given equalization curve, 
     FIG. 9 shows a gain control circuit according to a preferred embodiment of the invention, 
     FIG. 10 shows a curve representing the gain characteristic for a circuit as shown in FIG. 9 and 
     FIG. 11 shows the curve comprising three sloping lines of the circuit of FIG. 9 adapted to the profile of a given equalization curve, 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A gain control circuit as shown in FIG. 1 (prior art) has for its object to supply a gain control current 1 whose value is I o  (minimum gain) when the line current attains a maximum value I o  +yI o  when the line current has a minimum nominal value, and which linearly varies between these two values when the line current ranges between these two nominal values. With y=1 a correction dynamic of 6 dB will be obtained and 9 dB with y=1.75. 
     The circuit of FIG. 1 comprises an npn transistor T 0  having at least one emitter which is connected to the common mode pole (ground), a base to which is applied a reference voltage V ref  so that its collector-emitter path is passed through by a current xI o  (x being the number of emitters of the transistor T 0  or rather the ratio between the surfaces of the emitters of the transistors T 4  (cf below) and T 0 ), and a collector which is connected to a current source having a strength of k o  I L . The line current received from a subscriber station and whose value depends on the remoteness of the subscriber relative to the exchange is represented by I L , and k o  represents a given ratio. 
     An npn transistor T 10  has its emitter connected to ground, its collector connected to that of T 0  and its base connected to that of an npn transistor T 1 . The npn transistor T&#39; 10  has its base connected to the collectors of the transistors T 0  and T 10 , its emitter to the bases of the transistors T 10  and T 1 , and its collector connected to supply a voltage source V. The transistor T 1  has its emitter connected to ground, its collector connected to that of an npn transistor T 2  and also to a current source having a strength of yI o , constituted in this case by a pnp transistor T 11  which has an emitter connected to the voltage source V, the base connected to the reference potential Vref, and at least one collector connected to those of the transistors T 1  and T 2 . An npn transistor T&#39; 2  has its base connected to the collectors of the transistors T 1  and T 2 , its emitter to the base of the transistor T 2  and its collector to the voltage source V. An npn transistor T 3  has its base connected to that of the transistor T 2 , its emitter to ground, and its collector to that of a transistor T 4  whose emitter is connected to ground and to whose base is applied the voltage Vref so to constitute as a current source I o . The common collector of the transistors T 3  and T 4  constitutes the output S of the circuit which forms a current source having the value I. It will be evident that the transistors T 10  and T&#39; 10  are equivalent to a forward direction diode in the base of T 1 , which induces a base-emitter voltage equal to V o  in this transistor as long as current is available. 
     The circuit has three operating zones. 
     (a) Low I L  : k o  I L  &lt;xI o   
     The transistor T 0  is saturated and the transistor T 1  is blocked, and thus T 2  is conductive and is passed through by the current yI o , as is the transistor T 3  with which it forms a current source. Thus, we have I=I o  (1+y) which corresponds with a maximum gain. 
     (b) Intermediate I L  : k o  I L  &gt;xI o   
     The transistor T 0  is conductive in the normal fashion. The transistor T 1  is thus conductive (k o  I L  ·xI o ) and the transistor T 2  thus conducts the current yI o  -(k o  I L  -xI o ), the same holds for transistor T 3 . 
     Thus we have I=I o  (1+y)-(k o  I L  -xI o ). 
     (c) High I L  : k o  I L  ≧(x+y)I o   
     The current in T 2  is canceled causing the transistor T 3  to block. 
     Thus we have I=I o  (minimum gain). 
     FIG. 2 shows a standard schematic of an arrangement diagram with which it is possible to generate a current k o  I L  and a supply voltage V from a subscriber station. The exchange supplies the subscriber lines with a voltage V s  of 48 V. The current I L  which the subscriber receives depends on the length of the line between the subscriber and the exchange (line resistance R L ), and on the value of the resistance of the exchange (generally 600 Ω). A Zener diode Z is arranged at the input of the subscriber station so as to protect this station against overvoltages, and a capacitor C o  of a high value (approximately 100 μf) is inserted between a terminal of an adapting resistor R a  and ground. This terminal of the resistor R a  provides the supply voltage V. 
     A resistor R 2  is inserted between the input of the subscriber station and the non-inverting input of an operational amplifier A. Between this input of the amplifier A and ground a capacitor C 2  is inserted having a high value (several μf) intended to filter out the a.c. residual component. The output of the amplifier A is connected to the base of a transistor T 20  whose collector is connected to the input of the subscriber station, and whose emitter forms a junction B with on one side a resistor R 1  connected to the junction B and the non-inverting input of the amplifier A, and on the other a resistor R inserted between the junction B and ground and finally connected to the cathode of one of the two diodes D 1  and D 2  connected in series between the inverting input of the amplifier A and junction B. 
     Assuming that V 1  is the voltage at junction B and V 2  the voltage at the non-inverting input of the amplifier A, and V D  the voltage across a diode, we have: 
     
         V.sub.2 -V.sub.1 =2V.sub.D 
    
     V 1  =RI L   
     V 2  =RI L  +2 V D   
     The non-inverting input of the amplifier A is connected to the base of an npn transistor T 33  whose emitter is connected to ground across a forward direction diode D 3  and a resistor R&#39;  respectively. The collector of the transistor T 33  is connected to the base of a transistor T 32  whose collector is connected to ground. A transistor T 30  has n 1  collectors connected to the base of the transistor T 32 . The transistor T 22  is used because V 2  is connected to ground. 
     The emitter of the transistor T 30  is connected to the voltage V through a resistor R 30  and its base is connected to the emitter of transistor T 32  and to the base of a transistor T 31  whose emitter is connected to the voltage source V through a resistor R 31  and which has n 2  collectors (with n 2  ≧1) which supply the current k o  I L . The resistor R&#39; terminal not connected to ground has a potential of V 3 . 
     We have: 
     
         V.sub.3 =V.sub.2 -2V.sub.D ≃V.sub.1 =RI.sub.L 
    
     The current I&#39; which passes through the resistor R&#39; has a value of: ##EQU1## The transistors T 30  and T 31  form a current source at a ratio of n 2  /n 1  (or more generally, at the ratio of the surfaces of their collectors). 
     We have: ##EQU2## 
     FIG. 2 also shows an arrangement for obtaining the voltage Vref for the pnp transistor current sources (and a voltage V&#39;ref for the pnp transistor current sources). This arrangement comprises a first branch using the collector-emitter paths connected in series of two transistors: pnp transistor T 10  and npn transistor T 41 . The emitter-base path of a pnp transistor T&#39; 40  whose collector is connected to ground being inserted between the base and the collector of the transistor T 40 . A resistor R 40  is inserted between the emitter(s) of the transistor T 41  and ground. The second branch comprises in a series connection the emitter-collector paths of a pnp transistor T 41  and an npn transistor T 43  whose emitters are connected to ground. The base-emitter path of an npn transistor T&#39; 43  is connected between the collector and the base of the transistor T 43 . The emitters of the transistors T 40  and T 41 , are brought to a value which is equal to three diode voltages (3 V D ). This voltage which is equal to 3 V D  is obtained on the basis of the voltage V which feeds a current source I o  which causes a current I o  to flow through three series-arranged diodes D 40 , D 41  and D 42 . The voltage Vref is available on the interconnected bases of the transistors T 40  and T 41 , and a voltage V&#39;ref on the interconnected bases of the transistors T 41  and T 43 . These values specifically depend on the value of resistor R 40 . 
     The circuit according to the invention (FIG. 3) is distinguished from that shown in FIG. 1 in that transistor T 12  and npn transistor T 14  and diodes D 10 , D 12  and D&#39; 12  are inserted. The transistor T 12  has its base connected to the reference voltage source Vref, its emitter connected to the supply voltage source V and it has one or various collectors connected to ground through two forward direction diodes D 12  and D&#39; 12 . The transistor T 12  constitutes a current source zI o , the emitter of the transistor T 14  is connected to ground and its collector is connected to that or those of the transistor T 12 . 
     A diode D 10  is inserted between the collectors of the transistors T 1  and T 14 , whilst its anode is connected to the collector of the transistor T 1 . So four operating zones are distinguished: 
     (a) Low I L  : k o  I L  &lt;xI o   
     The transistor T 0  is saturated, the transistor T 1  is blocked as is the transistor T 14 . The current zI o  passes through the diodes D 12  and D&#39; 12  and the value of the collector potential of T 12  is 2V D . 
     The transistor T 2  is conductive. Its collector potential value is the sum of the base-emitter voltages of the transistors T 2  and T&#39; 2 , that is, 2V D , which implies that the diode D 10  is blocked. The operation is thus the same as above and we have: 
     
         I=I.sub.o (1+y), which corresponds with a maximum gain. 
    
     (b) Lower intermediate I L  : k o  I L  &gt;xI o . 
     The transistor T 10  is passed through by the current K o  I L  -xI o . 
     The transistor T 14  which has w emitters (in the drawing w=3) is passed through by the current w(k o  I L  -xI o ). 
     The diodes D 12  and D&#39; 12  are passed through by the current zI o  -w(k o  I L  -xI o ), thus the voltage across the collector of T 14  has the value 2V D . The transistor T 2  is conductive, thus the voltage on the base of T&#39; 2  and thus on the collector of T 1  has also the value 2V D . Thus the diode D 10  is blocked. 
     So this is the same case as with item b) of FIG. 1 that is to say, that the transistor T 2  conducts the current yi o  -(k o  I L  -xI o ) as does the transistor T 3 . 
     
         Thus we have I=I.sub.o (1+y)-(k.sub.o I.sub.L -xI.sub.o). 
    
     
         The slope is equal to a-k.sub.o. 
    
     (c) Higher intermediate I L  : w (kI L  -3xI o )-zI o  &gt;0. 
     The transistor T 1  conducts the current k o  I L  -xI o , and T 14  conducts the current w(k o  I L  -xI o ), but seeing that this current is larger than zI o , the transistor T 14  tends to be saturated that is, its collector voltage tends towards V CE  =0. Once its collector voltage attains the potential V D , the diode D 10  can be conductive. 
     The result of this is that the transistors T 1  and T 14  each consume current supplied by the source yI o . 
     The transistor T 2  thus conducts the current: 
     
         yI.sub.o -(k.sub.o I.sub.L -xI.sub.o)[w(k.sub.o I.sub.L -xI.sub.o)-zI.sub.o ]. 
    
     So we have: 
     
         I=I.sub.o (1+y)-((w+1)k.sub.o I.sub.L +(w+1)xI.sub.o +zI.sub.o. 
    
     The slope, equal to -(w+1)k o  is larger than for item b). 
     (d) High I L  : w(k o  I L  -xI o )-zI o  +k o  I L  -xI o  ≧yI o   
     The transistors T 1  and T 14  completely consume the current yI o . 
     The result is that the transistor T 2  is blocked. 
     So we have I=I o . 
     According to FIG. 4 the two-slope curve of the circuit as depicted in FIG. 3 shows a first part I and a steeper second part II which enables the parts to follow more accurately a characteristic correction-curve running as indicated by way of a solid line in FIG. 5. The presence of this correction curve with two slopes permits to obtain a maximum difference between the theoretical and real curves which is much smaller than with a correction curve having a single slope. 
     Fractionary ratios x, y and z can be obtained with the reference voltage Vref when using to this effect a circuit of the dividing current mirror type similar to the one described with FIG. 2 for obtaining the current k o  I L  (transistors T 30 , T 31 , diode D 3 , resistor R&#39;), or more simply, by varying the surface of the emitters. In fact the numbers of the emitters have been mentioned for clarity. Evidently, the currents have the same ratios as the effective emitter surfaces. 
     The schematic diagram of FIG. 6 comprises the same elements as that of FIG. 3 arranged in the same fashion but for the fact that the anode of the diode D 10  is connected to the collector of the transistor T 10  instead of being connected to that of the transistor T 1 . As observed hereinbefore, four operating zones are obtained 
     (a) Low I L  : k o  I L  &lt;xI o   
     The transistor T o  is saturated. The transistor T 1  is blocked, as is transistor T 14 . The current zI o  passes completely through the diodes D 12  and D&#39; 12 . The diode D 10  is thus reversely biased. 
     We have 
     I=I o  (1+y) 
     (b) Lower intermediate I L  : k o  I L  &gt;xI o  and wI 1  &lt;zI o   
     As the current wI 1  passing through T 14 , with w=3 in the drawing (because T 14  has three emitters), is smaller than zI o , the diodes D 12  and D&#39; 12  are passed by a current which is sufficient for causing a polarization of the conductive diode. The cathode of D 10  is thus at a potential of 2V BE . The current passing through the transistor T 10 , and thus the transistor T 1 , is not zero. The collector potential of T 10  and thus the anode potential of D 10  is 2V BE . The diode D 10  does not pass any current. 
     We have 
     
         I.sub.1 =k.sub.o I.sub.L -xI.sub.o 
    
     
         αI.sub.1 =α(k.sub.o I.sub.L -xI.sub.o) 
    
     
         I=I.sub.o +yI.sub.o -α(k.sub.o I.sub.L -xI.sub.o) 
    
     The current I decreases as a function of the line current with a slope -αk o  I L  (zone I&#39; of FIG. 7). 
     (c) Higher intermediate I L  : k o  I L  &gt;xI o  and wI 1  &lt;zI o   
     The diodes D 12  and D&#39; 12  no longer receive current and the voltage of the cathode of D 10  begins to drop, thus causing the diode D 10  to be conductive. The subtracted current k o  I L  thus becomes: 
     
         xI.sub.o +(wI.sub.1 -zI.sub.o)+I.sub.1 
    
     We have: 
     
         I=I.sub.o +yI.sub.o -αI.sub.1 
    
     with 
     
         k.sub.o I.sub.L -αI.sub.o =I.sub.1 +(IwI.sub.1 -zI.sub.o) 
    
     from which: ##EQU3## 
     The current I decreases with a slope which is smaller than in the preceding case b) due to the current subtracted by the diode D 10 . 
     This slope has a value of ##EQU4## 
     (d) High I L  : αI 1  &gt;yI o   
     Transistor T 2  is blocked as is transistor T 3 . 
     We have 
     
         I=I.sub.0. 
    
     FIG. 8 shows in what way a gain curve which corresponds with the case of a subscriber telephone set specifically suitable for exchanges having very remote subscribers can be approached. 
     The schematic diagram of FIG. 9 produces a compensation curve, shown in FIGS. 10 and 11, having three successive slopes enabling a more refined compensation than in the preceding case. From the point of view of the schematic diagram it corresponds with the embodiment of FIG. 6, plus a parallel arrangement of a novel sub-set D 20 , D 22 , D&#39; 22 , T&#39; 14 . The anode of the diode D 20  is connected to the collector of the transistor T 10  and the cathode of the diode D 20  is connected to the collector-emitter path of the transistor T&#39; 14  whose emitter is connected to ground and also connected to series-connected forward direction diodes D&#39; 22  and D 22 , the cathode of D&#39; 22  being connected to ground. The base of the transistor T&#39; 14  is connected to those of the transistors T 1  and T 14 . 
     A transistor T&#39; 12  inserted at the current source supplies a current z&#39;I o  at the node of the collector T&#39; 14 , at the cathode of D 20  and at the anode of D 22 . Thus with the aid of these two parallel arrangements we have a curve showing three successive slopes with decreasing values ##EQU5## The transistor T 10  shows by way of hypothesis a single emitter, w and w&#39; referring to the number of emitters of the respective transistors T 14  and T&#39; 14  (or rather the ratio of the emitter surface of this transistor to that of the transistor T 10 ). The choice of w, w&#39;, z and z&#39; determines the slopes and the positions of the connecting points. The two sub-sets (D 10 , D 12 , D&#39; 12  and T 14 ) (D 20 , D 22 , D&#39; 22 , T&#39; 14 ) are driven consecutively and their effects added up in accordance with the same opening principle as used in the previous examples.