Abstract:
In one aspect, an assembly to provide thermal cooling includes a first member having a first channel configured to receive a cooling fluid, a second member having a second channel configured to receive the cooling fluid and a first plurality of hollow and flexible conduits connecting the first and second members. Each of the first plurality of hollow and flexible conduits is configured to provide a path for the cooling fluid to flow between the first and second channels.

Description:
BACKGROUND 
     As is known in the art, a phased array antenna includes a plurality of active circuits spaced apart from each other by known distances. Each of the active circuits is coupled through a plurality of phase shifter circuits, amplifier circuits and/or other circuits to either or both of a transmitter and receiver. In some cases, the phase shifter, amplifier circuits and other circuits (e.g., mixer circuits) are provided in a so-called transmit/receive (T/R) module and are considered to be part of the transmitter and/or receiver. 
     The phase shifters, amplifier and other circuits (e.g., T/R modules) often require an external power supply (e.g., a DC power supply) to operate correctly. Thus, the circuits are referred to as “active circuits” or “active components.” Accordingly, phased array antennas which include active circuits are often referred to as “active phased arrays.” 
     Active circuits dissipate power in the form of heat. High amounts of heat can cause active circuits to be inoperable. Thus, active phased arrays must be cooled. In one example heat-sink(s) are attached to each active circuit to dissipate the heat. 
     SUMMARY 
     In one aspect, an assembly to provide thermal cooling includes a first member having a first channel configured to receive a cooling fluid, a second member having a second channel configured to receive the cooling fluid and a first plurality of hollow and flexible conduits connecting the first and second members. Each of the first plurality of hollow and flexible conduits is configured to provide a path for the cooling fluid to flow between the first and second channels. 
     In another aspect, an active, electronically scanned array (AESA) panel architecture system includes a first daughter board that includes antenna elements; a first thermal spreader attached to the antenna elements; a circuit board assembly; and a cold plate assembly in contact with the first thermal spreader. The cold plate assembly includes a first cold plate having a first channel configured to receive a cooling fluid, a second cold plate having a second channel configured to receive the cooling fluid and a first plurality of hollow and flexible conduits connecting the first and second cold plates. Each of the first plurality of hollow and flexible conduits is configured to provide a path for the cooling fluid to flow between the first and second channels. 
     In a further aspect, a method to provide thermal cooling includes using a first plurality of hollow and flexible conduits to connect a first cold plate having a first channel configured to receive a cooling fluid and a second cold plate having a second channel configured to receive the cooling fluid. The method further includes configuring each of the first plurality of hollow and flexible conduits to provide a path for the cooling fluid to flow between the first and second channels. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of an array antenna formed from a plurality of tile sub-arrays. 
         FIG. 2A  is a partially exploded perspective view of an example of a tile sub-array. 
         FIG. 2B  is a cross-sectional view of the tile sub-array of  FIG. 2A  taken along lines  2 B- 2 B. 
         FIG. 3  is a cross-sectional view of the tile sub-array of  FIG. 2B  with one example of a cold plate assembly. 
         FIGS. 4A and 4B  are cross-sectional views of the tile sub-array with different examples of cold plate assemblies. 
     
    
    
     DETAILED DESCRIPTION 
     A “panel array” (or more simply “panel”) refers to a multilayer printed wiring board (PWB) which includes an array of active circuits (or more simply “radiating elements” or “radiators”), as well as RF, logic and DC distribution circuits configured into highly integrated PWB(s). A panel is also sometimes referred to herein as a tile array (or more simply, a “tile”). 
     An array antenna may be provided from a single panel (or tile) or from a plurality of panels. In the case where an array antenna is provided from a plurality of panels, a single one of the plurality of panels is sometimes referred to herein as a “panel sub-array” (or a “tile sub-array”). 
     Reference is sometimes made herein to an array antenna having a particular number of panels. It should of course, be appreciated that an array antenna may be comprised of any number of panels and that one of ordinary skill in the art will appreciate how to select the particular number of panels to use in any particular application. 
     It should also be noted that reference is sometimes made herein to a panel or an array antenna having a particular array shape and/or physical size or a particular number of active circuits. One of ordinary skill in the art will appreciate that the techniques described herein are applicable to various sizes and shapes of panels and/or array antennas and that any number of active circuits may be used. 
     Similarly, reference is sometimes made herein to panel or tile sub-arrays having a particular geometric shape (e.g., square, rectangular, round) and/or size (e.g., a particular number of active circuits) or a particular lattice type or spacing of active circuits. One of ordinary skill in the art will appreciate that the techniques described herein are applicable to various sizes and shapes of array antennas as well as to various sizes and shapes of panels (or tiles) and/or panel sub-arrays (or tile sub-arrays). 
     Thus, although the description provided herein below describes the inventive concepts in the context of an array antenna having a substantially square or rectangular shape and comprised of a plurality of tile sub-arrays having a substantially square or rectangular-shape, those of ordinary skill in the art will appreciate that the concepts equally apply to other sizes and shapes of array antennas and panels (or tile sub-arrays) having a variety of different sizes, shapes, and types of elements. Also, the panels (or tiles) may be arranged in a variety of different lattice arrangements including, but not limited to, periodic lattice arrangements or configurations (e.g., rectangular, circular, equilateral or isosceles triangular and spiral configurations) as well as non-periodic or other geometric arrangements including arbitrarily shaped array geometries. 
     Reference is also sometimes made herein to the array antenna including an antenna element (active circuit) of a particular type, size and/or shape. For example, one type of radiating element is a so-called patch antenna element having a square shape and a size compatible with operation at a particular frequency (e.g., 10 GHz) or range of frequencies (e.g., the X-band frequency range). Reference is also sometimes made herein to a so-called “stacked patch” antenna element. Those of ordinary skill in the art will recognize, of course, that other shapes and types of antenna elements (e.g., an antenna element other than a stacked patch antenna element) may also be used and that the size of one or more active circuits may be selected for operation at any frequency in the RF frequency range (e.g., any frequency in the range of about 1 GHz to about 100 GHz). The types of radiating elements which may be used in the antenna of the present invention include but are not limited to notch elements, dipoles, slots or any other antenna elements (regardless of whether the antenna element is a printed circuit element) known to those of ordinary skill in the art. 
     It should also be appreciated that the active circuits in each panel or tile sub-array can be provided having any one of a plurality of different antenna element lattice arrangements including periodic lattice arrangements (or configurations) such as rectangular, square, triangular (e.g., equilateral or isosceles triangular), and spiral configurations as well as non-periodic or arbitrary lattice arrangements. 
     Applications of at least some examples of the panel array (sometimes referred to as a “tile array”) architectures described herein include, but are not limited to, radar, electronic warfare (EW) and communication systems for a wide variety of applications including ship based, airborne, missile and satellite applications. It should thus be appreciated that the panel (or tile sub-array) described herein can be used as part of a radar system or a communications system. 
     At least some examples as described herein are applicable, but not limited to, military, airborne, shipborne, communications, unmanned aerial vehicles (UAV) and/or commercial wireless applications. 
     The tile sub-arrays to be described herein below can also utilize embedded circulators; a slot-coupled, polarized egg-crate radiator; a single integrated monolithic microwave integrated circuit (MMIC); and a passive radio frequency (RF) circuit architecture. For example, as described further herein, technology described in the following commonly assigned United States Patents can be used in whole or in part and/or adapted to be used with at least some embodiments of the tile subarrays described herein: U.S. Pat. No. 6,611,180, entitled “Embedded Planar Circulator”; U.S. Pat. No. 6,624,787, entitled “Slot Coupled, Polarized, Egg-Crate Radiator”; and/or U.S. Pat. No. 6,731,189, entitled “Multilayer stripline radio frequency circuits and interconnection methods.” Each of the above patents is hereby incorporated herein by reference in their entireties. 
     Referring now to  FIG. 1 , an array antenna  10  is comprised of a plurality of tile sub-arrays  12   a - 12 N. It should be appreciated that in this example, N total tile sub-arrays  12  include the entire array antenna  10 . In one particular example, the total number of tile sub-arrays is sixteen tile sub-arrays (i.e., N=16). The particular number of tile sub-arrays  12  used to provide a complete array antenna can be selected in accordance with a variety of factors including, but not limited to, the frequency of operation, array gain, the space available for the array antenna and the particular application for which the array antenna  10  is intended to be used. Those of ordinary skill in the art will appreciate how to select the number of tile sub-arrays  12  to use in providing a complete array antenna. 
     As illustrated in tiles  12   b  and  12   i , in the example of  FIG. 1 , each tile sub-array  12   a - 12 N includes eight rows  13   a - 13   h  of active circuits  15  (also known as antenna elements) with each row containing eight active circuits  15 . Each of the tile sub-arrays  12   a - 12 N is thus said to be an eight by eight (or 8×8) tile sub-array. It should be noted that each active circuit  15  is shown in phantom in  FIG. 1  since the active circuits  15  are not directly visible on the exposed surface (or front face) of the array antenna  10 . Thus, in this particular example, each tile sub-array  12   a - 12 N includes sixty-four (64) active circuits. In the case where the array  10  includes sixteen (16) such tiles, the array  10  includes a total of one-thousand and twenty-four (1,024) active circuits  15 . 
     In another example, each of the tile sub-arrays  12   a - 12 N includes  16  active circuits. Thus, in the case where the array  10  includes sixteen (16) such tiles and each tile includes sixteen (16) active circuits  15 , the array  10  includes a total of two-hundred and fifty-six (256) active circuits  15 . 
     In view of the above examples, it should thus be appreciated that each of the tile sub-arrays can include any desired number of active circuits  15 . The particular number of active circuits to include in each of the tile sub-arrays  12   a - 12 N can be selected in accordance with a variety of factors including but not limited to the desired frequency of operation, array gain, the space available for the antenna and the particular application for which the array antenna  10  is intended to be used and the size of each tile sub-array  12 . For any given application, those of ordinary skill in the art will appreciate how to select an appropriate number of radiating active circuits to include in each tile sub-array. The total number of active circuits  15  included in an antenna array such as antenna array  10  depends upon the number of tiles included in the antenna array and as well as the number of active circuits included in each tile. 
     Each tile sub-array is electrically autonomous (except any mutual coupling which occurs between active circuits  15  within a tile and on different tiles). Thus, the RF feed circuitry which couples RF energy to and from each radiator on a tile is incorporated entirely within that tile (i.e., all of the RF feed and beamforming circuitry which couples RF signals to and from active circuits  15  in tile  12   b  are contained within tile  12   b ). In one example, each tile includes one or more RF connectors and the RF signals are provided to the tile through the RF connector(s) provided on each tile sub-array. 
     Also, signal paths for logic signals and signal paths for power signals which couple signals to and from transmit/receive (T/R) circuits are contained within the tile in which the T/R circuits exist. RF signals are provided to the tile through one or more RF connectors provided on the tile sub-array. 
     The RF beam for the entire array  10  is formed by an external beamformer (i.e., external to each of the tile subarrays  12 ) that combines the RF outputs from each of the tile sub-arrays  12   a - 12 N. As is known to those of ordinary skill in the art, the beamformer may be conventionally implemented as a printed wiring board stripline circuit that combines N sub-arrays into M RF signal port(s) (and hence the beamformer may be referred to as a N:M beamformer). 
     It should be appreciated that the examples of the tile sub-arrays described herein (e.g., tile sub-arrays  12   a - 12 N) differ from conventional array architectures in that the microwave circuits of the tile sub-arrays are contained in circuit layers which are disposed in planes that are parallel to a plane defined by a face (or surface) of an array antenna (e.g., surface  10   a  of array antenna  10 ) made up from the tiles. In  FIG. 1 , for example, the circuits  15  provided on the layers of circuit boards from which the tiles  12   a - 12 N are provided are all parallel to the surface  10   a  of array antenna  10 . By utilizing circuit layers that are parallel to a plane defined by a face of an array antenna, the tile architecture approach results in an array antenna having a reduced profile (i.e., a thickness which is reduced compared with the thickness of conventional array antennas). 
     Advantageously, the tile sub-array embodiments described herein can be manufactured using standard printed wiring board (PWB) manufacturing processes to produce highly integrated, passive RF circuits, using commercial, off-the-shelf (COTS) microwave materials, and highly integrated, active monolithic microwave integrated circuits (MMIC&#39;s). This results in reduced manufacturing costs. Array antenna manufacturing costs can also be reduced since the tile sub-arrays can be provided from relatively large panels or sheets of PWBs using conventional PWB manufacturing techniques. 
     Referring to  FIGS. 2A and 2B , in one particular example of the tile sub-arrays  12   a - 12 N is a tile sub-array  12 ′. The tile sub-array  12 ′ includes a mother board  20 , an RF interface board  24 , eight daughter cards (e.g., a daughter card  32   a - 32   h ) with active circuits  15  on each daughter card and eight thermal spreaders (e.g., a thermal spreader  34   a - 34   h ) attached to active circuits  15  of a corresponding daughter card. In one example, the active circuits  15  are secured to the thermal spreaders  34   a - 34   h  using solder techniques described in U.S. patent application Ser. No. 12/580,356 entitled “Cooling Active Circuits” which is incorporated herein in it entirety. 
     In one example, each daughter card  32   a - 32   h  includes sixteen active circuits  15 . Instead of having one large daughter card with active circuits  15  connected to one thermal spreader, this configuration increases yield during manufacturing by reducing the size of the daughter card into smaller pieces. In addition, it is easier to rework problems with smaller daughter cards as opposed to larger one piece daughter cards. For example, it is more cost effective to throw away sixteen active circuits  15  because of an active circuit failure than one hundred twenty-eight active circuits. 
     Cooling a number of substantially coplanar active circuits  15  (e.g., integrated circuits) with a single cold plate in direct contact with top surfaces of the thermal spreaders  34   a - 34   h  is difficult because of the many tolerances that exist resulting from height variations (thicknesses). For example, the active circuits  15 , the thermal spreaders  34  and the daughter card  32  may have different thicknesses. For example, with respect to  FIG. 2B , the thickness, T h , which includes thicknesses of the thermal spreader  34   h  and the daughter card  32   h  is different from the thickness, T e , which includes thicknesses of the thermal spreader  34   e  and the daughter card  32   e . In one particular example, the daughter cards  32   a - 32   h  have a thickness tolerances of +/−0.015 inches and the thermal spreader  34   a - 34   h  have a thickness tolerances of +/−0.005 inches resulting in a total thickness tolerance of +/−0.020 inches. 
     As described herein, a cold plate assembly that includes a corresponding cold plate for each daughter card/active circuit/thermal subassembly and hollow and flexible conduits between these corresponding cold plates and a large cold plate may be used to compensate for varying thicknesses between the daughter card and thermal spreader subassemblies. While this disclosure describes cooling active circuits in an environment of an active, electronically scanned array (AESA) panel architecture system, the techniques described herein may be used in any environment to cool multiple objects of varying thicknesses and/or substantially coplanar. 
     Referring to  FIG. 3 , a cold plate assembly  40  may be used to cool the tile sub-array  12 ′. In one example, the cold plate assembly  40  is connected to the thermal spreaders  34   a - 34   h  with or without a thermal interface material (e.g., a thermal grease) between the cold plate assembly and the thermal spreaders. The cold plate assembly  40  includes a large cold plate  52 ; eight small cold plates (of which only cold plates  54   a - 54   d  are visible in  FIG. 3 ), one small cold plate  54  for each daughter card/active circuit/thermal spreader subassembly; eight bosses (of which only bosses  76   a - 76   d  are visible in  FIG. 3 ) and sixteen hollow and flexible conduits (of which only conduits  80   a - 80   h  are visible in  FIG. 3 ). The large cold plate  52  includes a channel  60  for receiving cooling fluid (coolant). In one example, the large cold plate  52  receives cooling fluid from a port  62  and discharges cooling fluid from the port  64 . Each of the small plates  54   a - 54   d  also include a channel for receiving cooling fluid from the large cold plate  52  (e.g., the small plate  54   a  includes a channel  70   a , the small plate  54   b  includes a channel  70   b , the small plate  54 c includes a channel  70   c  and the small plate  54   d  includes a channel  70   d ). 
     In one example, the boss  76   a  extends through the thermal spreader  34   e  and through the daughter card  32   e  and is secured at the RF interface card  24  either on or within the RF interface card as depicted by dotted line  78 . In other examples not shown, the boss  76   a  extends through the RF interface card  24  and is secured either on or in the motherboard  20 . 
     Though not shown in  FIG. 3 , the other bosses  76   b - 76   d  also extend into their respective thermal spreaders  34   f - 34   h  and daughter cards  32   f - 32   h  in a similar fashion as boss  76   a . The bosses  76   a - 76   d  provide a hard stop to maintain antenna panel-to-antenna panel co-planarity necessary for RF performance and RF ground plane continuity. In other examples, the bosses  76   b - 76   d  are secured to the motherboard  20  and the RF interface board  24  in a similar fashion as boss  76   a.    
     While bosses  76   a - 76   d  have been described one of ordinary skill in the art would recognize that the bosses may be replaced with fasteners (e.g., standoffs and so forth). Also, one of ordinary skill in the art would recognize other known methods or techniques to ensure contact between the cold plate assembly and the thermal spreaders (e.g., as shown in  FIGS. 4A and 4B ). 
     The hollow and flexible conduits  80   a - 80   h  connect the large cold plate  52  to each of the small cold plates  54   a - 54   d . In one example, the cold plate  54   a  is connected to the large plate  52  by conduits  80   a ,  80   b , the cold plate  54   b  is connected to the large cold plate  52  by conduits  80   c ,  80   d , the cold plate  54   c  is connected to the large cold plate  52  by conduit  80   e ,  80   f  and the cold plate  54   d  is connected to the large cold plate  52  by conduits  80   g ,  80   h . In one particular example, the conduits  80   a - 80   h  are configured to carry cooling fluid between the channel  60  and the channels  70   a - 70   d.    
     The conduits  80   a - 80   h  provide flexibility to ensure intimate contact between the cold plate and thermal spreader to maximize thermal performance regardless of tolerances such as, for example, thickness, coplanarity and parallelism. In one example, one or more of the conduits  80   a - 80   h  may be a bellow, a hose, a sliding rigid tube or any combination thereof or some other flexible structure capable of carrying fluid (e.g., coolant). 
     Referring to  FIGS. 4A and 4B , in other cold plate assembly examples other or additional methods for securing the cold plate assemblies to the daughter card/active circuit/thermal spreader subassemblies may be used. For example, in  FIG. 4A , a first set of fasteners, one for each daughter card/active circuit/thermal spreader subassembly, for example, may be used to secure the mother board  20 , the RF interface board  24  and the daughter card/active circuit/thermal spreader assembly to a cold plate assembly  40 ′. An example of one of the first set of fasteners is a fastener  102   a . The fastener  102   a  is used to secure the mother board  20  to the boss  76   a . In one example, the fastener  102   a  is a threaded screw that engages corresponding threads  110  of the boss  76   a . In other examples, other fasteners of the first set of fasteners (not shown in  FIG. 4A ) connect corresponding cold plates  54   b - 54   d  in a similar fashion as fastener  102   a.    
     In addition, a second set of fasteners may also be used to secure the mother board  20  to the cold plate assembly  40 ′. An example of one of the second set of fasteners is a fastener  104   a . The fastener  104   a  is used to secure the mother board  20  to the cold plate  54   a . In one example, the fastener  104   a  is a threaded screw that engages corresponding threads  112  of the cold plate  54   a.    
     In one example, the fastener  104   a  provides pressure (e.g., by pulling the layers together) on each of the thermal interfaces (e.g., the thermal interfaces between the cold plate  54   a - 54   d  and their respective thermal spreaders  34   e - 34   h ) to ensure efficient heat transfer away from the active circuits  15 . Other fasteners of the second set of fasteners (not shown in  FIG. 4A ) connect corresponding cold plates  54   b - 54   d  in a similar fashion as fastener  104   a.    
     Referring to  FIG. 4B , fasteners  302   a - 302   c  (e.g., shoulder screws) and springs  202   a - 202   h  may be used together in a cold plate assembly  40 ′″. For example, the fasteners  302   a - 302   c  may be used to secure the motherboard  20  to the large cold plate  52 . In one particular example, the fasteners  302   a - 302   c  are threaded and fastener  302   a  engages corresponding threads  312   a  of the cold plate  52 , the fastener  302   b  engages corresponding threads  312   b  of the cold plate  52  and the fastener  302   c  engages corresponding threads  312   c  of the cold plate  52 . 
     The processes described herein are not limited to the specific embodiments described. Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Other embodiments not specifically described herein are also within the scope of the following claims.