Abstract:
A wideband digital quadrature local oscillator (LO) generator ( 300 ) using clocked-CMOS (C 2 MOS) latches ( 302, 304 ) can operate at very high frequencies, while consuming less current and having lower phase noise as compared to prior art quadrature LO generators using Source-coupled logic (SCL) latches. In addition, the LO generator ( 300 ) has no low frequency limit and can output rail-to-rail square waves.

Description:
TECHNICAL FIELD  
         [0001]    This invention relates in general to the field of electronic circuits, and more specifically to a differential Complementary Metal Oxide Semiconductor (CMOS) latch and a digital quadrature generator using the CMOS latch.  
         BACKGROUND  
         [0002]    Quadrature Local Oscillator (LO) signal generators are important building blocks in digital wireless communication systems. They are used for example in, quadrature modulators, demodulators and image rejection mixers. A conventional quadrature LO generator is shown in FIG. 1. Several techniques for generating IP (In-phase) and QP (Quadrature-phase) LO signals exist, with the most commonly used technique for generating a pair of quadrature LO signals requiring the use of divide-by 2 circuits. An example of a conventional Source Coupled Logic (SCL) latch is shown in FIG. 2.  
           [0003]    Conventional quadrature Local Oscillator LO signal generators use SCL latches for generating the In-Phase and Quadrature-Phase LO signals. Such LO signal generators have low operating frequency limits, and they do not provide rail-to-rail (i.e., square wave) output signals, which are recommended, for RF CMOS mixers and other circuits. LO generators incorporating SCL latches also suffer from high noise and also consume a large amount of power. SCL latches also need to be followed by a source follower or driver before the signal is sent to the next stage, thereby increasing power consumption. A need thus exist in the art for a new latch and digital quadrature LO generator using this new latch which can provide power consumption improvements and avoid the low-frequency limits of prior art quadrature signal generators. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]    The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention, may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:  
         [0005]    [0005]FIG. 1 shows a block diagram of a prior art Quadrature LO generator using SCL latches.  
         [0006]    [0006]FIG. 2 shows a schematic of a prior art SCL latch.  
         [0007]    [0007]FIG. 3 shows a block diagram of a digital quadrature LO generator using CMOS latches in accordance with one embodiment of the present invention.  
         [0008]    [0008]FIG. 4 shows a schematic of a Clocked CMOS latch in accordance with the invention.  
         [0009]    [0009]FIG. 5 shows an output waveform for the digital quadrature LO generator of FIG. 3.  
         [0010]    [0010]FIG. 6 is a detailed schematic of the back-to-back inverter section found in FIG. 4. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0011]    While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures.  
         [0012]    Referring now to FIG. 3, there is shown a digital quadrature LO generator  300  in accordance with the preferred embodiment of the invention. Generator  300  includes two Clocked CMOS (also referred herein as C 2 MOS) latches  302  and  304 , which are triggered by the positive and negative edges of an input clock. A clock signal input port (CLK) and a complementary clock signal input port (CLKb, referring to CLK bar) are provided as part of each latch  302  and  304 . When the clock signal (CLOCK) presented to the CLK input port is a logic high, the clock signal (CLOCKb) presented to the CLKb port is a logic low and vice-versa. Since the quadrature generator  300  is a divide-by-2 circuit, the input frequency is twice the output frequency. Each latch  302  and  304  includes a pair of differential input ports D and Db and a pair of differential output ports Q and Qb. The latches  302  and  304  are connected together as shown in FIG. 3 in order to provide In-phase (IP  310  and IPb  312 ) and Quadrature-phase (QP  306  and QPb  308 ) output signals.  
         [0013]    In FIG. 4 there is shown a differential C 2 MOS latch  400  that can be used for latches  302  and  304  of LO generator  300  in accordance with the invention. This positive level sensitive latch passes the signals present at the D  402  and Db  404  input ports to the Q  406  and Qb  408  output ports when the clock signal (CLOCK) presented to the CLK clock input port is a logic high. When the CLOCK signal is a logic low, the input data is sampled on the falling edge of the CLOCK signal, and is held stable at the LO gnerator&#39;s output ports (QP  306 , QPb  308 ) for the entire phase due to the back-to-back inverter  410 ,  412  connections found in each latch  302 ,  304 . The back-to-back inverter section  420  is shown in schematic detail in FIG. 6.  
         [0014]    When two of these latches  300  are connected in a master-slave configuration as done in the LO generator  300 , one latch  302  acts as a positive latch and the other latch  304  acts as a negative latch. With the negative output (Qb) of the second latch  304  feedback to the positive input (D) of the first latch  302 , it will generate In-Phase and Quadrature-Phase signals at half the frequency of the input clock signal. The output waveforms for digital quadrature LO generator  300  is shown in FIG. 5. Note that the performance of generator  300  is power supply dependent.  
         [0015]    A simulation at 2 GHz input frequency and using a 1.5 volt power supply, yielded a power consumption of 259 μA for quadrature LO generator  300 . The phase noise at different relative offset frequencies is tabulated in Table 1 below. Quadrature LO generator  300  has the advantage of having no low frequency limit.  
                           TABLE 1                                   Offset Frequency   Phase Noise                            5 MHz   −150.25 dBc/Hz           10 MHz   −151.86 dBc/Hz           20 MHz    −153.0 dBc/Hz                      
 
         [0016]    While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.