Abstract:
A channel stop is provided for a semiconductor device that includes at least one active region. The channel stop is configured to surround the semiconductor device, to abut the at least one active region at a periphery of the semiconductor device, and to share an electrical connection with the at least one active region.

Description:
BACKGROUND 
       [0001]    The present invention relates to a semiconductor device configuration, and more particularly to a semiconductor device design in which the functionality of a channel stop and a body contact are realized by a single structure. 
         [0002]    Metal oxide semiconductor (MOS) transistor designs require a structure to prevent leakage currents between unrelated regions or devices in the circuit, and also require a structure to electrically contact the body of the MOS transistor. With respect to the former, high operational voltages of MOS transistors in current designs often require the use of high resistivity silicon. A consequence of using high resistivity silicon is that the metal and polysilicon interconnects used in the transistors can cause the surface of the silicon to invert polarity (change from N type to P type, or vice versa). This can cause unwanted communication between different nodes in a circuit. Operating voltages above the inversion voltage often occur in high voltage circuits and applications, creating a need to form isolation features that prevent inversion of the silicon. With respect to the latter, many MOS circuit designs require a connection of the source terminal of a MOS transistor to the body region of the MOS transistor in order to control the body potential so that stable and reliable operation can be ensured. 
         [0003]    Unwanted inversion and communication between different nodes in a circuit have been addressed in the prior art through the use of diffused or implanted channel stops, trench isolation or polysilicon field plates. 
       SUMMARY 
       [0004]    The present invention provides a channel stop for a semiconductor device that includes at least one active region. The channel stop is configured to surround the semiconductor device, to abut the at least one active region at a periphery of the semiconductor device, and to share an electrical connection with the at least one active region. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a top layout view of a semiconductor device according to an embodiment of the present invention. 
           [0006]      FIG. 2  is a cross-sectional view taken at line  2 - 2  in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0007]      FIG. 1  is a top layout view of semiconductor device  10  according to an embodiment of the present invention, and  FIG. 2  is a cross-sectional view taken at line  2 - 2  in  FIG. 1 . In the exemplary embodiment shown in  FIGS. 1 and 2 , semiconductor device is an NMOS transistor, although it will be understood by those skilled in the art that semiconductor device  10  may be a different type of device in other embodiments. Heavily doped P-type implanted channel stop region  12  encircles N-type source  14 , N-type drain  16  and polysilicon gate  18  of the NMOS transistor formed in lightly doped P-type body region  19 . Channel stop region  12  prevents the formation of a continuous inversion region  20  ( FIG. 2 ) between N-type drain  16  and unrelated N-type region  22  associated with an adjacent semiconductor device (not shown), which would otherwise have the potential to be formed by the action of metal interconnect layer  24 . In an exemplary embodiment, lightly-doped P-type body region  19  has a doping level in the range of 1×10 14  cm −3  to 5×10 17  cm −3 , while heavily doped P-type channel stop region  12  has a doping level in the range of 1×10 19  cm −3  to 1×10 20  cm −3 . 
         [0008]    In many applications implementing NMOS transistor semiconductor device  10 , the potentials of N-type source  14  and lightly doped P-type body region  19  need to be the same (in other forms of semiconductor device  10 , this is true for other active regions of the device). Implanted channel stop region  12  is configured to abut N-type source  14 , and is electrically connected to N-type source  14  by metal silicide layer  26  ( FIG. 2 ). In an exemplary embodiment, metal silicide layer  26  is composed of cobalt silicide, although other metal silicides such as titanium, platinum and nickel are also suitable. Contact is therefore made between channel stop  12 , N-type source  14 , and P-type body region  19 . 
         [0009]    As a result of this configuration, implanted channel stop  12  provides a mechanism to contact body region  19  along the periphery of NMOS transistor semiconductor device  10 . As is known in the art, a contact to body region  19  in near the periphery of device  10  is needed to draw holes away from body region  19  between N-type source  14  and N-type drain  16  underneath polysilicon gate  18 , to preserve the junction therebetween and minimize voltage variation in body region  19  under polysilicon gate  18 . With the configuration shown in  FIGS. 1 and 2 , no additional contact to channel stop region  12  needs to be formed, as metal silicide layer  26  provides this function. 
         [0010]    In an exemplary configuration, the distance “X” between channel stop  12  and N-type drain  16  is determined by the maximum operating voltage of semiconductor device  10 , and typically varies between 0.5 and 4.0 microns. The distance “Y” between polysilicon gate  18  and channel stop  12  is dictated by the fabrication tools employed, such as lithographic alignment accuracy and dimension control, and typically varies between 0.2 and 1.0 microns. These distances are given only to provide examples of the disclosed configuration, and it should be understood that the invention is not necessarily limited to these dimensions. 
         [0011]    As shown in  FIG. 2 , the silicon regions of channel stop  12 , N-type source  14 , N-type drain  16  and P-type body region  19  are covered by silicon dioxide dielectric  28  (or another suitable insulating material). In an exemplary embodiment, silicon dioxide dielectric  28  has a thickness of about 0.5 to 2.0 microns, although this dimension may vary in other embodiments. Metal interconnect layer  24  is located on top of silicon dioxide dielectric  28 , and may be formed of aluminum, cobalt, or another suitable metal material. 
         [0012]    In the example shown, metal interconnect layer  24  is located over semiconductor device  10  and unrelated N-type region  22 . N-type region  22  is electrically isolated from N-type drain  16  of semiconductor device  10  by channel stop  12  therebetween. When metal interconnect layer  24  is positively biased with respect to P-type body region  19  at a voltage that is high enough to exceed the field inversion voltage, the surface of P-type body region  19  can invert to N-type, as illustrated by inversion regions  20  ( FIG. 2 ). It may also be possible for field inversion to occur due to the redistribution of ionic charges from the integrated circuit packaging material, such as during sustained high temperature operation, which could also result in inversion of the surface of P-type body region  19  to N-type in inversion regions  20 . The placement of channel stop  12  between N-type region  22  and N-type drain  16  ensures that these N-type inversion regions cannot connect N-type region  22  to N-type drain  16 , which would affect the operation of semiconductor device  10 . 
         [0013]    While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.