Abstract:
An edge sensing circuit is implemented using MOS logic gates. The edge sense circuit detects either a positive transition or a negative transition of a first input signal, depending on the logic level of a second input signal, if an enable signal logical &#34;1&#34; is applied to the edge sense circuit. If the enable signal is at a logical &#34;0,&#34; however, a level, rather than a transition, of the input signal is detected.

Description:
BACKGROUND OF THE INVENTION 
     In certain electronic applications circuits have been utilized which sense a transition of a logic signal. A wide variety of bipolar and MOS circuits which accomplish sensing of a particular positive or negative transition, are know in the art. Some known edge sensing circuits detect positive transitions of an input signal, while others detect negative transitions thereof. Further, a wide variety of known logic circuits are utilized in the art which utilize capacitance circuitry to accomplish an edge sensing. Further, a wide variety of known logic circuits are capable of sensing either a positive or a negative logic level. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide an improved edge sensing circuit. 
     It is another object of this invention to provide an edge sensing circuit which detects a transition of predetermined polarity of an input signal conditioned upon the voltage level of the second input signal. 
     It is another object of this invention to provide a circuit which senses either an edge or a corresponding logic level of a first input signal depending upon the logic level of a second input signal. 
     Briefly described, the invention is a bit sensing circuit including flip-flop circuit means coupled to gating circuitry and output circuitry for storing a level indicating that a transition of predetermined polarity of an input signal has occurred. The gating circuitry includes gating circuitry coupled to input signal which controls whether a positive or negative transition of the first input signal is to be detected. Additional gating circuitry is included which determines whether the transition of the first input signal sent or whether the voltage level at the end of the transition is sent. The bit sensing surface is implemented using MOS circuitry. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a logic diagram of a preferred embodiment of the invention. 
     FIG. 2a is a circuit schematic diagram showing an MOS implementation of inverters which may be used in the embodiment of FIG. 1. 
     FIG. 2b is a MOS implementation of a NOR gate which may be used in the circuit of FIG. 1. 
     FIG. 2c is a MOS implementation of an AND/NOR gate which may be used in the circuit of FIG. 1. 
     FIG. 2d is a MOS implementation of another AND/NOR gate which may be utilized in the embodiment of FIG. 1. 
     FIG. 3a is a partial timing diagram which is useful in describing the operation of the invention. 
     FIG. 3b is another partial timing diagram which is useful in describing the operation of the invention. 
    
    
     DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, edge sensing circuit 10 includes output node 40 and input nodes 12, 20, 16, and 27. Inverter 13 has its input connected to node 12 and its output connected to node 14. Two-input NOR gate 15 has one input connected to node 16 and another input connected to the node 17 and has its output connected to node 18. Two-input NOR gate 19 has one input connected to node 20 and its other input connected to node 16 and has its output connected to node 21. NOR gate 22 has one input connected to node 14 and another input connected to node 18 and has its output connected to node 23. Two-input NOR gate 24 has one input connected to node 21 and another input connected to node 12 and has its output connected to node 25. Two-input AND gate 26 has one input connected to node 27 and another input connected to node 23. It should be noted that in an MOS implementation, for example, AND gate 26 and NOR gate 29 could be a combinational AND/NOR gate wherein the AND gate is not separable from the NOR sections. In such a circuit the AND function is implemented utilizing two series connected MOSFETs. Two-input AND gate 28 has one input connected to node 27 and one input connected to node 25. Two-input NOR gate 29 has one input connected to the output of AND gate 26 and the other input connected to node 30 and has its output connected to node 31. Two-input NOR gate 32 has one input connected to node 31 and another input connected to the output of AND gate 28 and has its output connected to node 30. Inverter 35 has its input connected to node 20 and its output connected to node 17. Three-input AND gate 35 has its inputs connected, respectively, to nodes 20, 31, and 12. Three-input AND gate 36 has its inputs connected respectively, to nodes 14, 30 and 17. Two-input NOR gate 37 has its inputs connected to the outputs, respectively, of AND gate 35 and AND gate 36, and has its output connected to node 38. Inverter 39 has its input connected to node 38 and its output connected to node 40. 
     FIGS. 2a-2d illustrate the MOS circuit inplementation of the logic elements in FIG. 1. 
     FIG. 2a is a schematic diagram of a typical MOS inverter and may be used to implement inverters 13, 35, and 39 in FIG. 1, and includes switching MOSFET 53 coupled between ground conductor 51 and output 54 and also includes load MOSFET 55 connected between V DD  supply conductor 56 and output 54. The gate of MOSFET 53 is connected to inverter input 52. 
     FIG. 2b is an MOS implementation of a two-input NOR gate and may be used to implement NOR gates 15, 19, 22, and 24 in FIG. 1. NOR gate 60 includes MOSFET 61 connected between V DD  supply conductor 56 and output node 62 and further includes input MOSFET 65 and 63 coupled in parallel between ground conductor 51 and output node 62. The two inputs 66 and 64 are connected to the gates, respectively, of MOSFETs 65 and 63. 
     FIG. 2c is a MOS implementation of the AND/NOR function and may be used to implement the combinational gates 28, 32 and 26, 29 in FIG. 1. Combinational AND/NOR gate 70 in FIG. 2c includes load MOSFET 78 connected between V DD  conductor 56 and output node 77 and further includes MOSFET 73 connected between output node 77 and ground conductor 51 and having its gate electrode connected to an input of combinational AND/NOR gate 70. Combinational gate 70 also includes MOSFETs 75 and 71 connected in a series between output node 77 and ground conductor 51, MOSFETs 75 and 71 having their gate electrodes connected, respectively, to the other two inputs of combinational gate 70. The AND function of the combinational gate is accomplished by means of MOSFETs 75 and 71. 
     FIG. 2d is a MOSFET implementation of the AND/NOR gate represented by AND gate 35 and 36 and NOR gate 37 in FIG. 1. Combinational AND/NOR gate 80 includes load MOSFET 81 connected between V DD  supply conductor 56 and output node 82 and further includes MOSFETs 86, 87, and 88 connected in series between output node 82 and ground conductor 51, each of the latter MOSFETs having the gate electrodes connected to a separate input. MOSFETs 86, 87 and 88 operate to provide one of the AND functions of combinational gate 80. MOSFETs 83, 84 and 85 are connected in series between output node 82 and ground conductor 51 to provide the other three input AND functions, the latter MOSFETs having their gate electrodes connected respectively, to the other three inputs of combinational gate 80. 
     The operation of the edge sensing circuit of FIG. 1 is best described with relation to the timing diagram of FIGS. 3a and 3b. Input conductor 27 has a signal designated E(Enable) applied thereto. Conductor 20 has signal ACl applied thereto. If AC1 is equal to a logical 1, circuit 10 senses a positive edge of input CA1 applied to conductor 12. If AC1 is a logical 0, sensing circuit 10 senses a negative edge of CA1. AC7 is, in one embodiment of the invention, the output of the register bit labeled 40 having a Q output connected to conductor 16 and a Set input connected to output Node 40. The signal on output node 40 sets a logical 1 in register bit 40, and the resulting signal on AC7 &#34;acknowledges&#34; that the edge (positive or negative, depending on the level of AC1 has been sensed. 
     Briefly, the operation of the circuit of FIG. 1 is that if E is at a logical 1 at the time that an edge of CA1 occurs that edge will be sensed. However, if E is equal to a logical 0 at the time that the edge of CA1 occurs, then the level rather than the edge CA1 is sensed. Referring to FIG. 3, it is seen that input CA1 undergoes negative transition A after E has already risen to a logical 1 level. In response to this node 14, which is CA1, goes to a logical 1. AC1, during this time, is at a logical ,. and therefore AC1, node 17, is at a logical 1. Therefore, the AC1, and the CA1 inputs of NAND gate 36 are at a logical 1. It is assumed that Q is at a logical 1 initially. Therefore, the result of transition A of CA1 is that NAND gate 36 is enabled, causing waveform F, node 38, to undergo transition B from a logical 1 to a logical 0. This causes signal &#34;Set AC7&#34; node 40 to undergo transition D from a logical 0 to a logical 1. This in turn sets register bit 40&#39; to a logical 1, so that its output, AC7, undergoes transition E from a logical 0 to a logical 1. Since AC7 is connected to input NOR gates 15 and 19, waveform A undergoes transition F from a logical 1 to a logical 0, waveform B is already to logical 0 and remains there. In response to the above events, waveform D at node 23 undergoes transition C from a logical 1 to a logical 0 and waveform C goes from a logical 0 to a logical 1 during transition G, since both inputs of NOR gate 24, that is, waveforms A and CA1, are at a logical 0. Since AND gates 26 and 28 are enabled by the logical 1 of waveform E, the latch including NOR gates 29 and 32 is reset causing Q, node 30 to undergo transition H from a logical 1 to a logical 0 and waveform Q, node 31, undergoes a corresponding logical transition I from a logical 0 to a logical 1. 
     This causes NAND gate 36 to be disabled (i.e., causes a logical 1 at its output), since Q is now at a logical 0, and therefore waveform F, node 38 undergoes positive transition J from a logical 0 to a logical 1, providing the desired signal which indicates that edge A of CA1 has been sensed. 
     It is assumed, for purposes of explanation, that register bit 40&#39; is reset to a logical 0 during transition L, which causes node A to undergo transition M from a logical 0 to a logical 1. Node D then undergoes transition P in response to positive transition O of CA1, and the latch including NOR gate 29 and 32 is reset as indicated by transitions R and Q&#39; of waveforms Q and Q, respectively. Transition O&#39; of CA1 is seen in FIG. 3 to occur when E is at a logical 0 as contrasted to the earlier negative transition A which occurred when E was a logical 1. Waveform Set AC7 undergoes a transition to level S in response to transition 0 as described above. Waveform AC7 goes from a logical 0 to a logical 1 in response to waveform Set AC7 as before. Since AC1 is still at a logical 0, nodes A, B, C, and D respond as previously described. However, since E is at a logical 0, NAND gates 26 and 28 are not enabled, and the signals of waveforms C and D cannot affect the latch including NOR gates 29 and 32 until transition T of waveform E, at which time waveform Q undergoes transition U from a logical 1 to a logical 0 and waveform Q undergoes transition V from a logical 0 to a logical 1. The transition W of waveform F can then be said to have sensed the &#34;level&#34; of CA1 rather than the &#34;edge&#34; thereof. In other words, for edge sensing, the edge to be sensed must occur while E is positive, otherwise &#34;level sensing&#34; is said to occur. The operation of circuit 10 for detecting the positive edge or level of CA1 is entirely similar to that described above, except that AC1 is at a logical 1 and NAND gate 35 is activated instead of NAND gate 36, the waveforms for this case are shown in FIG. 3B. 
     Note that in the description of the operation, the latch is initially in a &#34;sensing mode&#34;; transition L of waveform AC7 indicates when the latch is reset to its sensing mode. 
     The purpose of register bit 40&#39; is to provide on line AC7 a signal which acknowledges whether or not an edge or level of CA1 has been sensed. For example, if a &#34;dwarf&#34; pulse occurs on node 12 (CA1), which does not propagate through the gating circuitry and succeeds in setting the latch including NOR gates 29 and 32, then AC7 remains low and permits another edge or pulse of CA1 to propagate through the gating circuitry and switch flip-flop 29, 32. This in effect is an added margin of noise immunity to the edge sensing circuit 10. 
     An edge sensing circuit could have been implemented without the use of enable signal E and the associated NAND gates 26 and 28. However, including these NAND gates provide additional noise immunity and also provide a option of sensing either and edge or level or CA1. 
     The following table indicates exemplary values in mils of the drawn channel length and channel widths of the MOSFET&#39;s in FIG. 2a-2d. 
     
         ______________________________________MOSFET       CHANNEL WIDTH   CHANNEL LENGTH        (Mils)          (Mils)______________________________________65           1.0             .2563           1.0             0.2561           0.4             1.053           1.0             0.2555           0.4             1.077           2.0             0.2573           1.4             0.2578           0.4             0.988           3.0             0.2587           3.0             0.2586           3.0             0.2585           3.0             0.2584           3.0             0.2583           3.0             0.2581           0.4             0.6______________________________________ 
    
     While the invention has been described with reference to the preferred embodiment thereof, those skilled in the art will recognize that variations in form and placement of parts may be made to suit varying requirements within the scope of the present invention.