Abstract:
An integrated circuit includes a plurality of logic circuits and a scan chain for testing the plurality of logic circuits. The plurality of logic circuits include the first and second logic circuits. The scan chain includes the first and second scan chain portions. The first scan chain portion is configured to test the first logic circuit based on a scan input test pattern applied thereto and output the first output test pattern. The second scan chain portion is configured to test the second logic circuit based on the first output test pattern and output the second output test pattern. A switching unit is provided to select and output one of the first output test pattern and the second output test pattern as a scan output test.

Description:
CROSS REFERENCE TO PRIOR APPLICATIONS 
     This application is a Continuation Application of U.S. patent application Ser. No. 10/701,008 filed on Nov. 3, 2003 and issued as U.S. Pat. No. 7,539,915 on May 26, 2009, which claims priority to and the benefit thereof from U.S. Provisional Patent Application No. 60/438,645 titled “Dual Scan Length” filed Jan. 7, 2003, which are all hereby incorporated by reference for all purposes as if fully set forth herein. 
    
    
     BACKGROUND 
     The disclosure relates generally to testing integrated circuits. More particularly, the disclosure relates to scan testing of integrated circuits. 
     Modern integrated circuits generally comprise a large number of circuit elements. It is desirable to test these circuit elements in order to ensure the proper operation of the integrated circuit. However, the number of test points (that is, locations where signals can be measured) is limited by the number of terminals of the integrated circuit, which is far less than the number of circuit elements to be tested. 
     Consequently, designers of modern integrated circuits often employ a test technique referred to herein as “scan testing.”  FIG. 1  shows a conventional integrated circuit  100  designed to permit scan testing of logic circuits  102 . According to this technique, integrated circuit  100  includes a scan chain  104  comprising a number of storage elements such as scan flip-flops (SFF)  106 A through  106 N that can be loaded with a test vector. The test vector is a binary number that includes bits to be loaded into SFFs  106 . 
     Each SFF  106  has two inputs A, B and an output Q, and selects one of the inputs A, B based on a scan shift signal applied to a scan input S. Each A input is connected to logic circuits  102 . Each B input is connected to the output Q of a previous SFF  106  in the scan chain  104 , except for the input B of the first SFF  106  in the scan chain  104 , which is connected to a scan input node, such as a scan input terminal of integrated circuit  100 , that can receive a scan input signal such as a test vector. The Q output of each SFF  106  in scan chain  104  is connected both to logic circuits  102  and to the next SFF  106  in scan chain  104 , except for the output Q of the last SFF  106  in scan chain  104 , which is connected both to logic circuits  102  and to a scan output node, such as a scan output terminal of integrated circuit  100 , to provide a scan output signal. 
     When the scan shift signal is negated (for example, during normal operations), each SFF  106  in scan chain  104  gates signals to and from logic circuits  102  in response to a clock signal applied to a clock input of each SFF  106 . However, when the scan shift signal is asserted (for example, during scan testing), each SFF  106  gates signals from the previous SFF  106  in the scan chain  104  to the next SFF  106  in the scan chain  104  in response to the clock signal, thereby causing the SFFs  106  to interconnect serially, forming scan chain  104 . 
     During scan test, the scan shift signal is asserted, thereby forming the scan chain  104 . Then the test vector (also referred to as “scan data”) is shifted into scan chain  104  as the scan input signal through the first SFF  106 A in scan chain  104  in response to the clock signal. The scan shift signal is then negated, breaking scan chain  104  and restoring normal operational connections to SFF  106 . The clock signal is then toggled one or more times to simulate normal operation of the integrated circuit  100 . The scan shift signal is then asserted again, forming scan chain  104  again. Then the data in the SFFs  106  are shifted out of the scan chain as the scan output signal through the last SFF  106 N in the scan chain in response to the clock signal. The scan output signal is then compared to a predetermined result vector to obtain a test result. 
     However, as the number of logic circuits in modern integrated circuits has grown, so has the number of storage elements required to test these logic circuits. The number of scan chains is limited by the number of terminals of the integrated circuit. Therefore, the length of each scan chain (that is, the number of storage elements in a scan chain) has increased. In general, the test time is defined by the length of the scan chains because most of the test cycles are consumed by shifting scan data into, and out of, the scan chains. Thus modern integrated circuits require increasingly greater test times. 
     SUMMARY OF THE DISCLOSURE 
     In general, in one aspect, the disclosure features an integrated circuit comprising a first scan chain portion comprising a plurality of first storage elements to interconnect in series according to a signal applied to a scan shift node of the integrated circuit, an input in communication with a scan input node of the integrated circuit, and an output; a second scan chain portion comprising a plurality of second storage elements to interconnect in series according to the signal applied to the scan shift node of the integrated circuit, an input in communication with the output of the first scan chain portion, and an output; and a switch comprising a first input in communication with the output of the first scan chain portion, a second input in communication with the output of the second scan chain portion, and a switch output in communication with a scan output node of the integrated circuit, wherein the switch is to place one of the first and second inputs in communication with the switch output according to a signal applied to a scan mode node of the integrated circuit. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits; wherein the first circuits are in communication with further inputs of the first storage elements; and wherein the second circuits are in communication with further inputs of the second storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. Each of the first and second storage elements comprises a flip-flop. The first scan chain portion is further to receive a test vector when the first storage elements are interconnected in series. The first scan chain portion is further to transmit a results vector when the first storage elements are interconnected in series. 
     In general, in one aspect, the disclosure features a method and computer program for testing an integrated circuit comprising a scan chain having a first scan chain portion comprising a plurality of first storage elements followed by a second scan chain portion comprising a plurality of second storage elements. It comprises interconnecting the first storage elements in series; inserting a test vector into the first scan chain portion; disconnecting the first storage elements from each other; applying a clock signal to respective clock inputs of the first storage elements; interconnecting the first storage elements in series; bypassing the second scan chain portion; and extracting a results vector from the first scan chain portion. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits, wherein the first circuits are in communication with inputs of the first storage elements; and wherein the second circuits are in communication with inputs of the second storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. 
     In general, in one aspect, the disclosure features an integrated circuit comprising a first scan chain portion comprising a plurality of first storage elements to interconnect in series according to a signal applied to a scan shift node of the integrated circuit, an input in communication with a scan input node of the integrated circuit, and an output; a second scan chain portion comprising a plurality of second storage elements to interconnect in series according to the signal applied to the scan shift node of the integrated circuit, an input in communication with the output of the first scan chain portion, and an output in communication with a scan output node of the integrated circuit; and a switch comprising a first input in communication with the scan input node of the integrated circuit, a second input in communication with the output of the first scan chain portion, and a switch output in communication with the input of the second scan chain portion, wherein the switch is to place one of the first and second inputs in communication with the switch output according to a signal applied to a scan mode node of the integrated circuit. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits; wherein the first circuits are in communication with further inputs of the second storage elements; and wherein the second circuits are in communication with further inputs of the first storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. Each of the first and second storage elements comprises a flip-flop. The first scan chain portion is further to receive a test vector when the first storage elements are interconnected in series. The first scan chain portion is further to transmit a results vector when the first storage elements are interconnected in series. 
     In general, in one aspect, the disclosure features a method and computer program for testing an integrated circuit comprising a scan chain having a first scan chain portion comprising a plurality of first storage elements followed by a second scan chain portion comprising a plurality of second storage elements. It comprises interconnecting the second storage elements in series; disconnecting the first and second scan chain portions from each other; and inserting a test vector into the second scan chain portion; disconnecting the second storage elements from each other; applying a clock signal to respective clock inputs of the second storage elements; interconnecting the second storage elements in series; and extracting a results vector from the second scan chain portion. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits, wherein the first circuits are in communication with inputs of the first storage elements; and wherein the second circuits are in communication with inputs of the second storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. 
     In general, in one aspect, the disclosure features an integrated circuit comprising a first scan chain portion comprising a plurality of first storage elements to interconnect in series according to a signal applied to a scan shift node of the integrated circuit, an input in communication with a scan input node of the integrated circuit, and an output; a second scan chain portion comprising a plurality of second storage elements to interconnect in series according to the signal applied to the scan shift node of the integrated circuit, an input in communication with the output of the first scan chain portion, and an output; a third scan chain portion comprising a plurality of third storage elements to interconnect in series according to the signal applied to the scan shift node of the integrated circuit, an input in communication with the output of the second scan chain portion, and an output; and a first switch comprising a first input in communication with the scan input node of the integrated circuit, a second input in communication with the output of the first scan chain portion, and a switch output in communication with the input of the second scan chain portion, wherein the first switch is to place one of the first and second inputs of the first switch in communication with the switch output of the first switch according to a signal applied to a scan mode node of the integrated circuit; a second switch comprising a first input in communication with the output of the second scan chain portion, a second input in communication with the output of the third scan chain portion, and a switch output in communication with a scan output node of the integrated circuit; wherein the second switch is to place one of the first and second inputs of the second switch in communication with the switch output of the second switch according to the signal applied to the scan mode node of the integrated circuit. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits; wherein the first circuits are in communication with further inputs of the second storage elements; and wherein the second circuits are in communication with further inputs of the first or third storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. Each of the first, second, and third storage elements comprises a flip-flop. The second scan chain portion is further to receive a test vector when the second storage elements are interconnected in series. The second scan chain portion is further to transmit a results vector when the second storage elements are interconnected in series. 
     In general, in one aspect, the disclosure features a method and computer program for testing an integrated circuit comprising a scan chain having a first scan chain portion comprising a plurality of first storage elements followed by a second scan chain portion comprising a plurality of second storage elements followed by a third scan chain portion comprising a plurality of third storage elements. It comprises interconnecting the second storage elements in series; disconnecting the first and second scan chain portions from each other; inserting a test vector into the second scan chain portion; disconnecting the second storage elements from each other; applying a clock signal to respective clock inputs of the second storage elements; interconnecting the second storage elements in series; bypassing the third scan chain portion; and extracting a results vector from the second scan chain portion. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits wherein the first circuits are in communication with inputs of the first storage elements; and wherein the second circuits are in communication with inputs of the second storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. 
     In general, in one aspect, the disclosure features an integrated circuit comprising a first scan chain portion comprising a plurality of first storage elements to interconnect in series according to a signal applied to a scan shift node of the integrated circuit, an input in communication with a scan input node of the integrated circuit, and an output; a second scan chain portion comprising a plurality of second storage elements to interconnect in series according to the signal applied to the scan shift node of the integrated circuit, an input in communication with the scan input node of the integrated circuit, and an output; and a switch comprising a first input in communication with the output of the first scan chain portion, a second input in communication with the output of the second scan chain portion, and a switch output in communication with a scan output node of the integrated circuit, wherein the switch is to place one of the first and second inputs in communication with the switch output according to a signal applied to a scan mode node of the integrated circuit. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits; wherein the first circuits are in communication with further inputs of the first storage elements; and wherein the second circuits are in communication with further inputs of the second storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. Each of the first and second storage elements comprises a flip-flop. The first scan chain portion is further to receive a test vector when the first storage elements are interconnected in series. The first scan chain portion is further to transmit a results vector when the first storage elements are interconnected in series. 
     In general, in one aspect, the disclosure features a method and computer program for testing an integrated circuit comprising a scan chain having a first scan chain portion comprising a plurality of first storage elements and a second scan chain portion comprising a plurality of second storage elements, wherein the inputs of the first and second scan chain portions are in communication with a scan input node of the integrated circuit. It comprises interconnecting the first storage elements in series; inserting a test vector into the first scan chain portion; disconnecting the first storage elements from each other; applying a clock signal to respective clock inputs of the first storage elements; interconnecting the first storage elements in series; connecting the first scan chain portion to a scan output node of the integrated circuit; and extracting a results vector from the first scan chain portion. 
     Particular implementations can include one or more of the following features. The integrated circuit further comprises a plurality of circuits comprising first circuits and second circuits wherein the first circuits are in communication with inputs of the first storage elements; and wherein the second circuits are in communication with inputs of the second storage elements. The first circuits have a high complexity; and wherein the second circuits have a low complexity. The first circuits have a greater number than the second circuits of at least one of the group consisting of logic depth; gates; gate inputs; and gate outputs. 
     Additional features, advantages, and embodiments of the disclosure may be set forth or apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood that both the foregoing summary of the disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the disclosure as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the detailed description serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure in more detail than may be necessary for a fundamental understanding of the disclosure and the various ways in which it may be practiced. In the drawings: 
         FIG. 1  shows a conventional integrated circuit designed to permit scan testing of logic circuits; 
         FIG. 2  shows an integrated circuit according to a preferred embodiment of the disclosure; 
         FIG. 3  is a flowchart of a process for the integrated circuit of  FIG. 2 ; 
         FIG. 4  shows an integrated circuit according to a preferred embodiment of the disclosure; 
         FIG. 5  is a flowchart of a process for the integrated circuit of  FIG. 4 ; 
         FIG. 6  shows an integrated circuit according to a preferred embodiment of the disclosure; 
         FIG. 7  is a flowchart of a process for the integrated circuit of  FIG. 6 ; 
         FIG. 8  shows an integrated circuit according to a preferred embodiment of the disclosure; and 
         FIG. 9  is a flowchart of a process for the integrated circuit of  FIG. 8 . 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments of the disclosure and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments and examples that are described and/or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and features of one embodiment may be employed with other embodiments as the skilled artisan would recognize, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as to not unnecessarily obscure the embodiments of the disclosure. The examples used herein are intended merely to facilitate an understanding of ways in which the disclosure may be practiced and to further enable those of skill in the art to practice the embodiments of the disclosure. Accordingly, the examples and embodiments herein should not be construed as limiting the scope of the disclosure, which is defined solely by the appended claims and applicable law. Moreover, it is noted that like reference numerals represent similar parts throughout the several views of the drawings. 
     The inventor has recognized that most of the logic circuits requiring test in a typical integrated circuit are of low complexity, and therefore require few test patterns, while only a few of the logic circuits requiring test are of high complexity. However, the circuits of high complexity require many test patterns. When a single scan chain comprises circuits of high and low complexity, the entire scan chain must be tested with all of the test patterns. 
     Accordingly, embodiments of the disclosure comprise scan chains that are segmented in different ways so that one can test a portion of the scan chain. In some embodiments, the scan chains are segmented according to the complexity of the logic circuits tested by the scan chains, so that one portion of the scan chain tests logic circuits of high complexity, while another portion tests circuits of low complexity. In some embodiments, the portion of the scan chain that tests logic circuits of high complexity can be tested independently. In general, this portion is only a small fraction of the entire scan chain, so that far fewer test cycles are required to shift scan data into, and out of, the tested portion. 
     Preferably the complexity of a logic circuit is defined by its logic depth, which can be characterized for a given flip-flop in a scan chain by the maximum number of gates a signal can traverse through the logic circuit between the given flip-flop and another flip-flop in the scan chain. Of course, the complexity of a logic circuit can be defined by other measures, such as by the number of gates in the logic circuit, the number of gate inputs and/or outputs in the logic circuit, and the like. 
       FIG. 2  shows an integrated circuit  200  according to a preferred embodiment of the disclosure. Integrated circuit  200  comprises logic circuits  102  and a scan chain  204 . The logic circuits  102  may comprise a high complexity portion  102 A and a low complexity portion  102 B. The scan chain  204  may comprise a first portion  204 A, a second portion  204 B, and a switch such as multiplexer  208 . First scan chain portion  204 A comprises L storage elements such as scan flip-flops (SFF)  106 AA through  106 AL. Second scan chain portion  204 B comprises M storage elements such as SFF  106 BA through  106 BM. 
     Multiplexer  208  operates under the control of a scan mode select signal to isolate first scan chain portion  204 A by connecting the output of first scan chain portion  204 A (that is, the output Q of the last SFF  106 AL in first scan chain portion  204 A) to the scan output node of scan chain  204 . 
     In a preferred embodiment, the first scan chain portion  204 A is connected to the high complexity portion  102 A of the logic circuits  102  and the second scan chain portion  204 B is connected to the low complexity portion  102 B of the logic circuit  102  so that the test patterns for the logic circuits  102  need not be shifted through the entire scan chain  204 . In addition, the test patterns can be shorter, as they only need be as long as the scan chain portion being tested. For example, suppose that 20% of logic circuits  102  contain 80% of the complexity of logic circuits  102 , and that 80% of the test patterns are devoted to testing 20% of logic circuits  102 . According to this embodiment, those 80% of the test patterns now need be shifted through only 20% of scan chain  204 , resulting in substantial savings in test time. In the 80/20 example, test time can be reduced by 64%. In a 90/10 example, test time can be reduced by 74%. 
       FIG. 3  is a flowchart of a process  300  for integrated circuit  200 . Process  300  can be implemented, for example, as software executing on a tester in communication with integrated circuit  200 . Process  300  forms scan chain  204  (step  302 ) by asserting the scan shift signal to interconnect the SFFs  106  of the first and second scan chain portions in series. Process  300  then inserts a test vector into the first scan chain portion  204 A (step  304 ) by applying the test vector as the scan input signal to the input B of the first SFF  106 AA in scan chain  204  and toggling the clock signal L times. Process  300  then breaks the scan chain (step  306 ) by negating the scan shift signal to disconnect the first and second SFFs  106  from each other. 
     Process  300  then cycles integrated circuit  200  (step  308 ) by toggling the clock signal one or more times. Process  300  then forms scan chain  204  again (step  310 ) and bypasses the second scan chain portion  204 B (step  312 ) by asserting the scan mode select signal, which causes multiplexer  208  to connect the output Q of the last SFF  106 AL of the first scan chain portion  204 A to the scan output node. Process  300  then extracts a results vector (the data stored in SFFs  106 AA through  106 AL) from the first scan chain portion  204 A (step  314 ). Because the scan data need not be shifted through the second scan chain portion  204 B, significant test time is saved. 
     Process  300  can control the contents of second scan chain portion  204 B according to any number of schemes. For example, process  300  can shift a test vector through first scan chain portion  204 A into second scan chain portion  204 B, reset the flip-flops  106 B in second scan chain portion  204 B to a known value, or simply leave the contents of second scan chain portion  204 B as they are. 
       FIG. 4  shows an integrated circuit  400  according to a preferred embodiment of the disclosure. Integrated circuit  400  comprises logic circuits  102  and a scan chain  404  comprising a first portion  404 A, a second portion  404 B, and a switch such as multiplexer  408 . First scan chain portion  404 A comprises L storage elements such as scan flip-flops (SFF)  106 AA through  106 AL. Second scan chain portion  404 B comprises M storage elements such as SFF  106 BA through  106 BM. 
     Multiplexer  408  operates under the control of a scan mode select signal to isolate first scan chain portion  404 A by connecting the input of second scan chain portion  404 B (that is, the B input of the first SFF  106 BA in second scan chain portion  404 B) to the input of scan chain  404  (that is, the B input of the first SFF  106 AA in scan chain  404 ). 
     In a preferred embodiment, the second scan chain portion  404 B is connected to the logic circuits  102  of high complexity so that the test patterns for those circuits need not be shifted through the entire scan chain  404 . 
       FIG. 5  is a flowchart of a process  500  for integrated circuit  400 . Process  500  can be implemented, for example, as software executing on a tester in communication with integrated circuit  400 . Process  500  forms scan chain  404  (step  502 ) by interconnecting the SFFs  106  of the first and second scan chain portions  404  in series to form scan chain  404 , preferably by asserting the scan shift signal. Process  500  disconnects the first and second scan chain portions  404  from each other (step  504 ) by asserting the scan mode select signal, which causes multiplexer  408  to connect the B input of the first SFF  106 BA of the second scan chain portion  404 B to the scan input node. 
     Process  500  inserts a test vector into the second scan chain portion  404 B (step  506 ) by applying the test vector as the scan input signal and toggling the clock signal L times, which shifts the test vector through multiplexer  408  and into the input B of SFF  106 BA. Process  500  then breaks the scan chain (step  508 ) by disconnecting the first and second SFFs  106  from each other, preferably by negating the scan shift signal. 
     Process  500  cycles integrated circuit  400  (step  510 ) by toggling the clock signal one or more times. Process  500  then forms scan chain  404  again (step  512 ). 
     Process  500  then extracts a results vector (the data stored in SFFs  106 BA through  106 BM) from the second scan chain portion  404 B (step  514 ). Because the scan data need not be shifted through the first scan chain portion  404 A, significant test time is saved. 
     Process  500  can control the contents of first scan chain portion  404 A according to any number of schemes. For example, process  500  can shift a test vector into first scan chain portion  404 A, reset the flip-flops  106 A in first scan chain portion  404 A to a known value, or simply leave the contents of first scan chain portion  404 A as they are. 
       FIG. 6  shows an integrated circuit  600  according to a preferred embodiment of the disclosure. Integrated circuit  600  comprises logic circuits  102  and a scan chain  604  comprising a first portion  604 A, a second portion  604 B, a third portion  604 C, and two switches such as multiplexers  608 A and  608 B. First scan chain portion  604 A comprises L storage elements such as scan flip-flops (SFF)  106 M through  106 AL. Second scan chain portion  604 B comprises M storage elements such as SFF  106 BA through  106 BM. Third scan chain portion  604 C comprises N storage elements such as SFF  106 CA through  106 CN. 
     Multiplexers  608 A and  608 B operate under the control of a scan mode select signal to isolate second scan chain portion  604 B. When the scan mode select signal is asserted, multiplexer  608 A connects the input of second scan chain portion  604 B (that is, the B input of the first SFF  106 BA in second scan chain portion  604 B) to the scan input node of scan chain  604  (that is, the B input of the first SFF  106 AA in scan chain  604 ), and multiplexer  608 B connects the output of second scan chain portion  604 B (that is, the output Q of the last SFF  106 BM in second scan chain portion  604 B) to the scan output node of scan chain  604  (that is, the output Q of the last SFF  106 CN in scan chain  604 ). Of course, multiplexers  608  can be operated independently to isolate different parts of scan chain  604 . 
     In a preferred embodiment, the second scan chain portion  604 B is connected to the logic circuits  102  of high complexity so that the test patterns for those circuits need not be shifted through the entire scan chain  604 . 
       FIG. 7  is a flowchart of a process  700  for integrated circuit  600 . Process  700  can be implemented, for example, as software executing on a tester in communication with integrated circuit  600 . Process  700  forms scan chain  604  (step  702 ) by asserting the scan shift signal to interconnect the SFFs  106  of the first, second and third scan chain portions in series to form scan chain  604 . Process  700  disconnects the first and second scan chain portions from each other (step  704 ) by asserting the scan mode select signal, which causes multiplexer  608 A to connect the B input of the first SFF  106 BA of the second scan chain portion  604 B to the scan input node. 
     Process  700  then inserts a test vector into the second scan chain portion  604 B (step  706 ) by applying the test vector as the scan input signal and toggling the clock signal L times, which shifts the test vector through multiplexer  608 A and into the input B of SFF  106 BA. Process  700  then breaks the scan chain (step  708 ) by negating the scan shift signal to disconnect the first, second and third SFFs  106  from each other. 
     Process  700  cycles integrated circuit  600  (step  710 ) by toggling the clock signal one or more times. Process  700  then forms scan chain  604  again (step  712 ) and bypasses the third scan chain portion  604 C (step  714 ) by asserting the scan mode select signal, which causes multiplexer  608  to connect the output Q of the last SFF  106 BM of the second scan chain portion  604 B to the scan output node. 
     Process  700  then extracts a results vector (the data stored in SFFs  106 BA through  106 BM) from the second scan chain portion  604 B (step  716 ). Because the scan data need not be shifted through the first scan chain portion  604 A or the third scan chain portion  604 C, significant test time is saved. 
     Process  700  can control the contents of first and third scan chain portions  604 A and  604 C according to any number of schemes. For example, process  700  can shift a test vector through scan chain  604  into first and third scan chain portions  604 A and  604 C, reset the flip-flops  106 A and  106 C in first and third scan chain portions  604 A and  604 C to a known value, or simply leave the contents of first and third scan chain portions  604 A and  604 C as they are. 
       FIG. 8  shows an integrated circuit  800  according to a preferred embodiment of the disclosure. Integrated circuit  800  comprises logic circuits  102  and a parallel scan chain  804  comprising a first portion  804 A, a second portion  804 B, and a switch such as multiplexer  808 . First scan chain portion  804 A comprises L storage elements such as scan flip-flops (SFF)  106 AA through  106 AL. Second scan chain portion  804 B comprises M storage elements such as SFF  106 BA through  106 BM. 
     Scan chain portions  804 A and  804 B are connected in parallel to a single scan input node. Multiplexer  808  operates under the control of a scan mode select signal to select one of the scan chain portions by connecting either the output of first scan chain portion  804 A (that is, the output Q of the last SFF  106 AL in first scan chain portion  804 A) or the output of second scan chain portion  804 B (that is, the output Q of the last SFF  106 BM in second scan chain portion  804 B) to the scan output node of scan chain  804 . 
     In a preferred embodiment, only one of the scan chain portions is connected to the logic circuits  102  of high complexity so that the test patterns for those circuits need not be shifted through both scan chain portions. 
       FIG. 9  is a flowchart of a process  900  for integrated circuit  800 . Process  900  can be implemented, for example, as software executing on a tester in communication with integrated circuit  800 . Process  900  forms scan chain  804  (step  902 ) by asserting the scan shift signal to interconnect the SFFs  106  of the first and second scan chain portions  804  in series. However, in this embodiment, the scan chain portions are connected in parallel, rather than in series as with the above embodiments. Process  900  then inserts a test vector into the first scan chain portion  804 A (step  904 ) by applying the test vector as the scan input signal to the scan input node of scan chain  804  and toggling the clock signal L times. Process  900  then breaks the scan chain (step  906 ) by negating the scan shift signal to disconnect the first and second SFFs  106  from each other. 
     Process  900  then cycles integrated circuit  800  (step  908 ) by toggling the clock signal one or more times. Process  900  then forms scan chain  804  again (step  910 ) and connects the first scan chain portion  804 A to the scan output node (step  912 ) by asserting the scan mode select signal, which causes multiplexer  808  to connect the output Q of the last SFF  106 AL of the first scan chain portion  804 A to the scan output node. Process  900  then extracts a results vector (the data stored in SFFs  106 AA through  106 AL) from the first scan chain portion  804 A (step  914 ). Because the scan data need not be shifted through the second scan chain portion  804 B, significant test time is saved. 
     Process  900  can control the contents of second scan chain portion  804 B according to any number of schemes. For example, process  900  can shift the same test vector into both first scan chain portion  804 A into second scan chain portion  804 B, reset the flip-flops  106 B in second scan chain portion  804 B to a known value, or simply leave the contents of second scan chain portion  804 B as they are, for example by adding an additional multiplexer at the inputs to scan chain portions  804 A and  804 B. 
     The techniques presented above can be used to segment a scan chain into any number of portions, and to isolate any lesser number of those portions. The portions can be assigned to circuitry based on metrics other than complexity. 
     The disclosure can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the disclosure can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the disclosure can be performed by a programmable processor executing a program of instructions to perform functions of the disclosure by operating on input data and generating output. The disclosure can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits). 
     While the disclosure has been described in terms of exemplary embodiments, those skilled in the art will recognize that the disclosure can be practiced with modifications in the spirit and scope of the appended claims. These examples given above are merely illustrative and are not meant to be an exhaustive list of all possible designs, embodiments, applications or modifications of the disclosure.