Abstract:
A gate driving module drives a display device having a plurality of first switch units. The gate driving module includes a gate driving circuit, a switch controlling circuit, and a plurality of switch sets. The gate driving circuit includes a plurality of first output ends for outputting a plurality of gate driving signals. The switch controlling circuit includes a plurality of second output ends for outputting a plurality of switch controlling signals. Each switch set includes at least two second switch units. One end of each second switch unit is coupled to a corresponding first output end of the gate driving circuit, the other end of each second switch unit is coupled to the control end of a corresponding first switch unit, and the control end of each second switch unit is coupled to a corresponding second output end.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a gate driving module, and more particularly, to a gate driving module which saves number of gate driving circuits by employing a switching method. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional Liquid Crystal Display (LCD)  100 . As shown in  FIG. 1 , the LCD  100  comprises a gate driving circuit  110 , a data driving circuit  120 , and a pixel area  130 . The gate driving circuit  110  comprising M gate lines outputs M gate driving signals sequentially. The data driving circuit  120  comprising Q data lines outputs Q data signals. The pixel area  130  is constructed by the M gate driving lines of the gate driving circuit  110  and the Q data lines of the data driving circuit  120 . Thus, the pixel area  130  comprises Q(column)×M(row) pixels. That is, the resolution of the LCD  100  is Q×M. 
         [0005]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating another conventional LCD  200 . As shown in  FIG. 2 , the LCD  200  comprises gate driving circuits  211  and  212 , a data driving circuit  220 , and a pixel area  230 . The gate driving circuit  211  comprising M gate lines outputs M gate driving signals sequentially. The gate driving circuit  212  comprising M gate lines outputs M gate driving signals sequentially. The data driving circuit  220  comprising Q data lines outputs Q data signal. The pixel area  230  is constructed by the two M gate driving lines of the gate driving circuits  211  and  212  and the Q data lines of the data driving circuit  220 . Thus, the pixel area  230  comprises Q(column)×2M(row) pixels. That is, the resolution of the LCD  200  is Q×2M. It is shown that both the number of the gate lines and the amount of gate drive circuit are increase as the resolution of an LCD increases. Therefore, the price of the LCD would increase, when the resolution of the LCD is multiplied. 
       SUMMARY OF THE INVENTION  
       [0006]    The present invention provides a gate driving module for driving a display device. The display device has a plurality of first switch units. The gate driving module comprises a gate driving circuit, a switch controlling circuit, and a plurality of switch sets. The gate driving circuit comprises a plurality of first output ends for outputting a plurality of gate driving signals. The switch controlling circuit comprises a plurality of second output ends for outputting a plurality of switch controlling signals. Each of the plurality of the switch sets comprises at least two second switch units. One end of the each second switch unit is coupled to a corresponding first output end of the plurality of the first output ends of the gate driving circuit. Another end of the each second switch unit is coupled to a control end of a corresponding first switch unit of the plurality of the first switch units of the display device. A control end of each second switch unit is coupled to a corresponding second output end of the plurality of the second output end of the switch controlling circuit. Wherein the number of the first switch units of the display device is a multiple number of the first output ends of the gate driving circuit. 
         [0007]    The present invention further provides an LCD. The LCD comprises a plurality of first switch units, a gate driving module, a plurality of switch sets, and a data driving circuit. The gate driving module comprises a gate driving circuit and a switch controlling circuit. The gate driving circuit comprises a plurality of first output ends for outputting a plurality of gate driving signals. The switch controlling circuit comprises a plurality of second output ends for outputting a plurality of switch controlling signals. Each of the plurality of the switch sets comprises at least two second switch units. One end of the each second switch unit is coupled to a corresponding first output end of the plurality of the first output ends of the gate driving circuit. Another end of the each second switch unit is coupled to a control end of a corresponding first switch unit of the plurality of the first switch units. A control end of the each second switch unit is coupled to a corresponding second output end of the switch controlling circuit. The data driving circuit comprises a plurality of third output ends. Each third output end is corresponding coupled to the input end of the first switch for transmitting corresponding data. Wherein number of the first switch units of the display device is a multiple number of the first output ends of the gate driving circuit. 
         [0008]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0009]      FIG. 1  is a diagram illustrating a conventional LCD. 
           [0010]      FIG. 2  is a diagram illustrating another conventional LCD with higher resolution. 
           [0011]      FIG. 3  is an LCD according to a first embodiment of the present invention. 
           [0012]      FIG. 4  is a timing diagram illustrating the relation between the switch controlling signal and the gate driving signal. 
           [0013]      FIG. 5  is a diagram illustrating an LCD according to a second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0014]    Please refer to  FIG. 3 .  FIG. 3  is an LCD  300  according to a first embodiment of the present invention. As shown in  FIG. 3 , the LCD  300  comprises a gate driving module  340 , a data driving circuit  320 , and a pixel area  350 . The data driving circuit  320  comprising Q data lines (output ends) outputs Q data signals respectively. The pixel area  350  is constructed by Q(column)×(M×N)(row) pixels. That is, the highest resolution of the LCD  300  is Q×M×N. Each pixel of the pixel area  350  comprises a first switch unit SW P , a storing capacitor C ST , and a corresponding liquid crystal layer area LC. The first switch unit SW P  comprises a first end, a second end, and a control end. The first end of the first switch unit SW P  coupled to a corresponding data line of the data driving circuit  320  receives corresponding data signal. The second end of the first switch unit SW P  is coupled to the storing capacitor C ST  and the corresponding liquid crystal layer area LC. The control end of the first switch unit SW P  coupled to a corresponding gate line of the gate driving module  340  receives a corresponding gate driving signal. When the control end of the first switch unit SW P  receives the corresponding gate driving signal, the data signal of the corresponding data line is transmitted through the first switch unit to the storing capacitor C ST  and the corresponding liquid crystal layer area LC and thereby the LCD  300  displays an image. Thus, as shown in  FIG. 3 , when the number of the columns of the pixels of the pixel area  350  is M×N, (M×N) gate driving signals are required to display an image. In this embodiment, M, N, and Q are all integers. 
         [0015]    The gate driving module  340  comprises a gate driving circuit  311 , a switch controlling circuit  330 , and N switch sets SS 1 ˜SS N . The gate driving circuit  311  comprising M gate lines (output ends) outputs M gate driving signals G 1 ˜G M  sequentially. The switch controlling unit  330  comprising N output ends outputs N switch controlling signals S 1 ˜S N  sequentially. Each switch set of the switch sets SS 1 ˜SS N  comprises M second switch units (for example, SW 1 , SW 2 , SW M  . . . SW (M×(K−1)) , SW (M×(K−1)+1)  . . . SW (M×(N−1))  . . . SW (M×N) ). Each second switch unit comprises a first end, a second end, and a control end. The second switch unit can be realized with a Thin Film Transistor (TFT) and a diode. For example, the second switch unit SW 1  comprises a TFT T 1  and a diode D 1 . The positive end of the diode D 1  is coupled to the second end of the TFT T 1 , the negative end of the diode D 1  is coupled to the control end of the second switch unit SW 1 . The diode D 1  can be realized with a TFT, a Metal Oxide Semiconductor (MOS) transistor, or a Bipolar Junction Transistor (BJT) as desired. In this embodiment, the control end (gate) of the TFT is the control end of the second switch unit. The first end of the TFT is the first end of the second switch unit. The second end of the TFT is the second end of the second switch unit. 
         [0016]    In the switch set SS 1 , the control end of each second switch unit coupled to the first output end of the switch controlling circuit receives the switch controlling signal S 1 ; the first end of the second switch unit SW 1  is coupled to the first output end of the gate driving circuit  311 ; the second end of the second switch unit SW 1  is coupled to the first gate line of the pixel area  350 ; the first end of the second switch unit SW 2  is coupled to the second output end of the gate driving circuit  311 ; the second end of the second switch unit SW 2  is coupled to the second gate line of the pixel area  350 ; . . . ; the first end of the second switch unit SW M  is coupled to the M th  output end of the gate driving circuit  311 ; the second end of the second switch unit SW M  is coupled to the M th  gate line of the pixel area  350 . 
         [0017]    In the switch set SS 2  (not shown), the control end of each second switch unit coupled to the second output end of the switch controlling circuit receives the switch controlling signal S 2 ; the first end of the second switch unit SW (M+1)  is coupled to the first output end of the gate driving circuit  311 ; the second end of the second switch unit SW (M+1)  is coupled to the (M+1) th  gate line of the pixel area  350 ; the first end of the second switch unit SW (M+2)  is coupled to the second output end of the gate driving circuit  311 ; the second end of the second switch unit SW (M+2)  is coupled to the (M+2) th  gate line of the pixel area  350 ; . . . ; the first end of the second switch unit SW 2M  is coupled to the M th  output end of the gate driving circuit  311 ; the second end of the second switch unit SW 2M  is coupled to the 2M th  gate line of the pixel area  350 . 
         [0018]    In the switch set SS K , the control end of each second switch unit coupled to the K th  output end of the switch controlling circuit receives the switch controlling signal S K ; the first end of the second switch unit SW (M×(K−1))  is coupled to the first output end of the gate driving circuit  311 ; the second end of the second switch unit SW (M×(K−1))  is coupled to the (M×(K−1)) th  gate line of the pixel area  350 ; the first end of the second switch unit SW (M×(K−1)+1)  is coupled to the second output end of the gate driving circuit  311 ; the second end of the second switch unit SW (M×(K−1)+1)  is coupled to the (M×(K−1)+1) th  gate line of the pixel area  350 ; . . . ; the first end of the second switch unit SW M×K  is coupled to the M th  output end of the gate driving circuit  311 ; the second end of the second switch unit SW M×K  is coupled to the (M×K) th  gate line of the pixel area  350 . 
         [0019]    In the switch set SS N , the control end of each second switch unit coupled to the N th  output end of the switch controlling circuit receives the switch controlling signal S N ; the first end of the second switch unit SW (M×(N−1))  is coupled to the first output end of the gate driving circuit  311 ; the second end of the second switch unit SW (M×(N−1))  is coupled to the (M×(N−1)) th  gate line of the pixel area  350 ; the first end of the second switch unit SW (M×(N−1)+1)  is coupled to the second output end of the gate driving circuit  311 ; the second end of the second switch unit SW (M×(N−1)+1)  is coupled to the (M×(N−1)+1) th  gate line of the pixel area  350 ; . . . ; the first end of the second switch unit SW M×N  is coupled to the M th  output end of the gate driving circuit  311 ; the second end of the second switch unit SW M×N  is coupled to the (M×N) th  gate line of the pixel area  350 . 
         [0020]    According to the description above, the rules for coupling of the second switch units are described as follows: The first end of the Y th  second switch unit of the X th  switch set coupled to the Y th  output end of the gate driving circuit  310  receives the gate driving signal G Y , the control end of the Y th  second switch unit of the X th  switch set coupled to the X th  output end of the switch controlling circuit  330  receives the switch controlling signal S X , and the second end of the Y th  second switch unit of the X th  switch set is coupled to the (X×Y) th  gate line (namely, coupled to the control end of the first switch unit corresponding to the (X×Y) th  gate line.) 
         [0021]    In this way, the gate driving module  340  merely utilizes a gate driving circuit  330 , instead of N gate driving circuits to drive an M×N column pixel area  350 . The gate driving module  340  can switch the gate driving circuit  311  to output the gate driving signals G 1 ˜G M  sequentially for driving the (M×N) columns pixel area  350  by the gate driving circuit  330  and a plurality of switch sets SS 1 ˜SS N . 
         [0022]    Please refer to  FIG. 4 .  FIG. 4  is a timing diagram illustrating the relation between the switch controlling signal and the gate driving signal. As shown in  FIG. 4 , the switch controlling signals S 1 ˜S N  are generated sequentially. The period of a switch controlling signal is the sum of the periods of the M gate driving signals. More particularly, when the gate driving circuit  311  executes the first scanning to sequentially transmit the gate driving signals G 1 ˜G M , the switch controlling circuit  330  generates the switch controlling signal S 1  during the entire period for the first scanning. After the first scanning is done, the gate driving circuit  311  executes the second scanning to sequentially transmit the gate driving signals G 1 ˜G M , the switch controlling circuit  330  generates the switch controlling signal S 2  during the entire period for the second scanning. After the (K−1) th  scanning is done, the gate driving circuit  311  executes the K th  scanning to sequentially transmit the gate driving signals G 1 ˜G M , the switch controlling circuit  330  generates the switch controlling signal S K  during the entire period for the K th  scanning, and so on. In this way, the first to the M th  gate lines are driven by the gate driving signals G 1 ˜G M  (when the gate driving circuit  311  executes the first scanning) and the switch set SS 1 , the (M+1) th  to the (2M) th  gate lines are driven by the gate driving signal G 1 ˜G M  (when the gate driving circuit  311  executes the second scanning) and the switch set SS 2  . . . the [M×(K−1)] th  to the (M×K) th  gate lines are driven by the gate driving signal G 1 ˜G M  (when the gate driving circuit  311  executes the K th  scanning) and the switch set SS K  . . . the [M×(N−1)] th  to the (M×N) th  gate lines are driven by the gate driving signal G 1 ˜G M  (when the gate driving circuit  311  executes the N th  scanning) and the switch set SS N . Consequently, the LCD  300  can display a frame with the resolution of (M×N×Q) with only one gate driving circuit. 
         [0023]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating an LCD  500  according to a second embodiment of the present invention. The LCD  500  is similar to the LCD  300 . The only difference between the LCDs  500  and  300  is that an additional gate driving circuit  312  is added in the LCD  500 . The gate driving circuits  311  and  312  can be respectively disposed in the different areas of the LCD  500 , e.g. upper part of the LCD  500  and the lower part of the LCD  500 . The deployment of the gate driving circuit  311  and  312  reduces the degeneration and the delay of the gate driving signals caused by the lengths of the driving paths. In this way, even if the display size of the LCD  500  increases, the frames displayed thereon still have high quality. 
         [0024]    In the fabrication process of the LCD, since the first switch unit (for pixel) and the second switch unit (for switching gate driving signal) are fabricated in the same process, the overall cost of the LCD does not increase. Compared to the LCD of the present invention, the conventional LCD has to add gate driving circuits as the number of the columns of the pixels increases, which increases the overall cost as well. 
         [0025]    To sum up, the gate driving module of the present invention effectively utilizes the switch units for switching gate driving signals to the corresponding pixels so as to save the expense of the additional gate driving circuits, providing convenience to users. 
         [0026]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.