Abstract:
A modulator has a transparent substrate with a first surface. At least one interferometric modulator element resides on the first surface. At least one thin film circuit component electrically connected to the element resides on the surface. When more than one interferometric element resides on the first surface, there is at least one thin film circuit component corresponding to each element residing on the first surface.

Description:
BACKGROUND 
   Interferometric modulators, such as the iMoD™, modulate light by controlling the self-interference of light that strikes the front surface of the modulator. These types of modulators typically employ a cavity having at least one movable or deflectable wall. This deflectable wall moves through planes parallel to the front wall of the cavity—the wall that is first encountered by light striking the front surface of the modulator. As the movable wall, typically comprised at least partly of metal and highly reflective, moves towards the front surface of the cavity, self-interference of the light within the cavity occurs, and the varying distance between the front and movable wall affects the color of light that exits the cavity at the front surface. The front surface is typically the surface where the image seen by the viewer appears, as interferometric modulators are usually direct-view devices. 
   The movable wall moves in response to an actuation signal generated by addressing circuitry that sends the signal to the movable element. The addressing circuitry is generally manufactured off-chip from the array of movable elements. This is in part because the substrate upon which the interferometric modulators are manufactured is transparent, such as plastic or glass. 
   Thin film transistors may be manufactured on transparent substrates. Integrating thin film transistors with the interferometric modulator array may provide an interferometric modulator with extended functionality. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention may be best understood by reading the disclosure with reference to the drawings, wherein: 
       FIGS. 1   a  and  1   b  show embodiments of an interferometric modulator. 
       FIG. 2  shows a side view of an interferometric modulator having integrated thin film transistors. 
       FIGS. 3   a - 3   l  show embodiments of an integrated process flow for thin film transistors. 
       FIGS. 4   a - 4   h  show embodiments of an integrated process flow for an interferometric modulator with thin film transistors. 
       FIGS. 5   a - 5   r  show embodiments of an integrated process flow for an interferometric modulator having low-temperature polysilicon, top gate transistors. 
       FIGS. 6   a - 6   n  show embodiments of an integrated process flow for an interferometric modulator having low-temperature polysilicon, bottom gate transistors. 
       FIG. 7  shows a flowchart of an embodiment of a method to manufacture interferometric modulators in series with manufacture of polysilicon, top gate transistors. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
     FIGS. 1   a  and  1   b  show alternative embodiments of an interferometric modulator. As mentioned previously, interferometric modulators employ a cavity having at least one movable or deflectable wall. As the wall  20  of  FIG. 1   a,  typically comprised at least partly of metal, moves towards a front surface  12  of the cavity, interference occurs that affects the color of light viewed at the front surface. The front surface is typically the surface where the image seen by the viewer appears, as the iMoD is a direct-view device. The front surface  12  may have a stack of materials that form the optical stack  14 , also referred to as the first mirror. The movable wall  20  is offset from the optical stack by a post  16 . 
   In the embodiment of  FIG. 1   a,  the movable element  20  is part of a membrane that covers the posts  16 , with a slightly elevated portion of the membrane  18 . In an alternative embodiment, the movable element  24  is suspended over the cavity by the supports  22  that also form the posts. The embodiments of the invention as described herein apply to both of these architectures, as well as many other types of MEMS devices manufactured from thin film processes. 
   In a monochrome display, such as a display that switches between black and white, one iMoD element might correspond to one pixel. In a color display, three iMoD elements may make up each pixel, one each for red, green and blue. The individual iMoD elements are controlled separately to produce the desired pixel reflectivity. Typically, a voltage is applied to the movable wall, or element, of the cavity, causing it be to electrostatically attracted to the front surface that in turn affects the color of the pixel seen by the viewer. 
   Addressing circuitry and drivers determine which elements have a voltage applied to move them towards the front surface. The addressing circuitry will generally include transistors, with one or more transistors corresponding to each element on the modulator array. Currently, the transistors are manufactured off-chip from the modulator element. However, with the use of thin-film transistors, it is possible to manufacture the transistors on the substrate. In addition, as most MEMS devices may be manufactured from thin films, it is possible to integrate the manufacture of thin film transistors with the manufacture of MEMS devices. 
     FIG. 2  shows a side view of an interferometric modulator device. The modulator has an array of individually controlled, movable elements such as  30 , manufactured on the transparent substrate  10 . As part of the packaging process, the modulator array is enclosed with a back plate  28 . As can be seen here, there are several portions of the transparent substrate  10  that could be used for manufacture of thin film transistors that would not be seen by the viewer  26 . 
   Regions  32   a  and  32   d  are ‘outside’ the modulator, where the term ‘outside’ refers to being on the opposite side of the back plate or other packaging structure from the modulator array. This would not typically be where the transistors would go. The possibility of damaging the transistor leads between the modulator elements and the transistors with the back plate mounting processes may be too great. Typically, the transistors would be manufactured directly adjacent the modulator array, where directly adjacent means that they are manufactured on portions of the substrate not used for the modulator array, but inside the back plate. Regions  32   b  and  32   c  are examples of such a location. In addition, the transistors may be manufactured side by side with the modulator elements, such as one transistor next to each element. 
   As mentioned previously, it is possible to manufacture thin film transistors using materials and processes that are very compatible with the manufacture of MEMS devices, such as the interferometric modulators mentioned above. Looking at  FIG. 2 , it can be seen that the modulator array is manufacture on the ‘back’ of the transparent substrate  10 . In the process flow diagrams of  FIGS. 3   a - 3   l,  the transparent substrate is shown ‘upside down’ from the view of  FIG. 2 . The manufacture of the modulator will appear to be on top of the substrate. 
   In addition, it is possible to manufacture other semiconductor, thin film, circuit components may be manufactured integrated with the modulator manufacturing process flow, or in series with it. An example of a component other than a transistor would be thin film diodes. While the examples below discuss the manufacture of thin film transistors, any thin film semiconductor circuit component may be used. 
   In  FIG. 3   a,  a first material layer  42  has been deposited. This material may be used to form the gates for the thin film transistors and the optical stack of the interferometric modulator, as shown in  FIG. 4   a.  The first material may be metal. In  FIG. 3   b,  the first material has been patterned and etched to remove selected portions such as  44  of the material. This can form the gates of the transistors. The optical stack for the modulators may be formed into rows as shown in  FIG. 4   b.    
   In  FIG. 3   c,  a first oxide layer  46  has been deposited. The material used for the oxide may be the same material used to form the optical stack dielectric for the modulators and the gate oxide for the transistors, shown in  FIG. 4   c.  The selection of the material for the oxide can be adjusted for both the operation of the modulator and for compatibility with the further processes used to form the elements. For example, it is useful if the oxide material used is optically transparent for use in the modulator. 
   In  FIG. 3   d,  a first sacrificial layer is deposited for the modulators. This layer will be etched to form the cavity, after the formation of other parts of the modulator is completed. The sacrificial layer  48  of  FIG. 4   d  may actually be formed from two layers, a first layer of amorphous silicon and then a doped layer of amorphous silicon, as shown at  48   a  and  48   b  of  FIG. 3   d.  The use of amorphous silicon and doped amorphous silicon as the sacrificial layer is compatible with the processing of the modulator, and is used in the processing of the thin film transistors. As mentioned above the dielectric layer  46  may be selected to be compatible with further processing, so the dielectric/oxide would be selected to be compatible with amorphous silicon. 
   In  FIG. 3   e,  the sacrificial layer is patterned and etched to form post holes similar to  50  for the modulator elements, as shown in  FIG. 4   e.  Since the sacrificial layer is the amorphous silicon and doped amorphous silicon in one embodiment, this is also patterned and etched as part of the transistor formation process. Posts may be formed out of the same material used to planarize the thin film transistor structures such as polymer  52  in  FIGS. 3   f  and  4   f.  Currently, the posts of the modulators are formed from a metal layer, either the metal of the membrane of  FIG. 1   a  or the metal of the supports of  FIG. 1   b.  However, there is no requirement to use metal for the posts. Using a polymer allows the planarization of the transistors to be done in parallel with the formation of the posts. An example of a polymer would be polyimide. 
     FIG. 3   g  appears similar to  FIG. 3   f  because the processing performed is not seen by the side view. In  FIG. 3   g,  the planarization layer would be patterned and etched to clear the transistor leads. This clears the way for the metal contacts to be made with the deposition of the metal layer  54  in  FIGS. 3   h  and  4   g.  This metal forms the mirror layer  20  in  FIG. 1   a  and the mirror element  24  in  FIG. 1   b.  It will also form the sources and drain electrodes for the transistors. It must be noted that in the architecture of  FIG. 1   a,  the metal layer  54  is the mirror layer and the mechanical layer, the layer that moves. In the architecture of  FIG. 1   b,  the layer  54  is the mirror layer and the post layer  52  is the mechanical layer. 
   The metal layer  54  is patterned and etched to form the source and drain electrodes as well as form the individual movable elements for the modulator in  FIG. 3   i.  The gap  56  is formed by the etching process performed on the metal layer. The doped amorphous silicon layer  48   a  is then etched again in  FIG. 3   j,  using the source/drain electrode metal as a mask, to form the channel for the transistors. There is no equivalent process for the modulator element for this or the remaining transistor processes. 
   The final two processes for the transistor formation are show in  FIGS. 3   k  and  3   l.  In  3   k,  a passivation layer  60  is deposited for the transistors. In  FIG. 3   l,  the passivation layer is etched to clear leads, such as by the gap show at  62 . In one embodiment, the passivation layer is oxide. The transistor processing is then completed, upon which a release etch is performed to form gap  57  in  FIG. 4   h,  allowing the modulator elements to move freely. In this manner, the manufacture of thin film transistors is accomplished nearly in parallel with the manufacture of a thin film, interferometric spatial light modulator. 
   For the modulator architecture of  FIG. 1   b,  a second sacrificial layer would be deposited, followed by a second metal layer. The patterning and etching of the metal layer to form the support posts and then the etching of the sacrificial layer to free up the elements may be performed after the formation of the thin film transistors. The alteration of the processing for the architecture of  FIG. 1   b  is more clearly set out in U.S. patent application Ser. No. 10/644,312, filed Aug. 19, 2003, “Separable Modulator Architecture.” The process of manufacturing the thin film transistors is compatible with the manufacture of either architecture of the interferometric modulator array. 
   In addition, the manufacture of the transistors may use low-temperature polysilicon, either in a top gate or a bottom gate structure. These processes will be demonstrated with the separable modulator architecture of  FIG. 1   b,  but could also apply to the architecture of  FIG. 1   a.  The selection of the modulator architecture is independent of the selection of the type of transistors used, and the integration process is adaptable to the different, possible combinations. 
   FIGS  5   a - 5   r  show embodiments of a process flow for a top-gate, low-temperature, polysilicon transistor flow integrated with the process flow for an interferometric modulator. The transistor flow and the modulator flow are shown side-by-side on what appears to be the same portion of the substrate, but that is just for ease of demonstration and is not intended to imply any particular location for the modulator array relative to the transistor array. 
   In  FIG. 5   a,  the optical stack  42  is deposited on the substrate  40 . In  FIG. 5   b,  the oxide  46  and the first portion  48   a  of the first sacrificial layer  48  is deposited, masked and etched. If  FIG. 5   c,  the second portion  48   b  is deposited. In  FIG. 5   d,  the layers are patterned and etched to form the basic structures for the modulator as well as the transistors. The structure to the right of the diagram is one element of an interferometric modulator array, used to show the integration of the two process flows. 
   In  FIG. 5   d,  the n-channel mask for the transistor is deposited to allow for n-channel doping. A gate oxide  60  is then deposited. The oxide is then patterned and etched to obtain the resulting structures in  FIG. 5   f.  In  FIG. 5   g,  the second portion  48   b  of the sacrificial layer has been patterned and etched to form underlying structures for the modulator element. In  FIG. 5   h,  the gate molybdenum is deposited at  66 . This is patterned and etched to form the structures such as  66   a  and  66   b  in  FIG. 5   i.    
   In  FIG. 5   j,  the p source and drain are doped using a mask, resulting in doped p source and drain  68 . A similar process is performed for the n source and drain  70  in  FIG. 5   k.  In  FIG. 5   l,  the interlayer dielectric  72  is deposited over the transistor structures. No comparable processes are being performed on the modulator element at this point. 
   In  FIG. 5   m,  the mirror layer  54  is deposited to be used by the transistors as the source/drain contacts, and the modulator as the mirrors  54   a,    54   b  and  54   c.  This resumes the integrated processing flow. In  FIG. 5   n,  a sacrificial layer  74  is deposited, which will provide support for the mirror supports and then be removed to allow the mirror elements to move freely. The sacrificial layer  74  will not be used by any transistor processes, but the transistors may require that the material remain compatible with the processes in the transistor flow. 
   In  FIG. 5   o,  the sacrificial layer  74  has been cleared from the transistor region and has been patterned and etched to form post holes  50   a,    50   b  and  50   c.  A planarization layer  76  is deposited in  FIG. 5   p.  The mechanical layer  52  is then deposited in  FIG. 5   q  to form the support posts for the mirrors. The transistor region then received a passivation layer in  FIG. 5   r.    
     FIGS. 6   a - 6   n  show similar processes as  FIGS. 5   a - 5   r,  but for a bottom gate, low-temperature, polysilicon transistor array. Similar structures and layers use the same reference numbers between the two for easier comparison. In  FIG. 6   a,  the optical stack  42  for the modulator is deposited on the substrate  40 . The two portions of the first sacrificial layer  48  are deposited, patterned and etch in  FIG. 6   b  to form underlying structures for the modulator. In  FIG. 6   c,  the gate metal  80  is deposited, patterned and etch and then the oxidation layer  82  is formed. The gate oxide is deposited in  FIG. 6   d.    
   In  FIG. 6   e,  the mirror layer  54  is deposited, patterned and etched to form the mirrors form the modulator element, mirrors  54   a,    54   b  and  54   c.  In  FIG. 6   f,  the sacrificial layer  74  is deposited, and  FIG. 6   g,  the post holes such as  50   a  is formed, with sacrificial islands of layer  74  left on the transistor structures. In  FIG. 6   h,  an oxide layer is deposited and then patterned and etched to form oxide caps for the transistor structures. 
   In  FIG. 6   i,  the n-type source and drain are doped as shown by  70 , and the p-type source and drain are doped as shown by  68  in  FIG. 6   j.  In  FIG. 6   k,  the interlayer dielectric  72  is deposited. The planarization layer  76  is deposited in  FIG. 6   l.  In  FIG. 6   m,  the mechanical layer  52  is deposited that forms the posts in the post holes, and provides the source/drain contact metal for the transistors. In  FIG. 6   n,  the passivation layer  78  is deposited. 
   In this manner, a process flow may be provided that integrates the manufacturing of the transistors and the interferometric modulator on one substrate. This integrated process flow saves processing steps, thereby reducing costs, and allows for faster processing of the devices. Faster processing of the device increases the output of devices, thereby also reducing costs. 
   In addition, it may be desirable to perform the processing in series. In one example, the circuit component processing is performed first, then the processing for the interferometric modulator. In another example, the ordering is switched. An example of the circuit component being manufactured first is shown in  FIG. 7 . The process starts with the transparent substrate. 
   At  90 , the optical stack is formed by deposition, patterning and etching of the electrode layer, the optical layer and the dielectric. At  92 , the structures formed at covered with a protective oxide layer. At this point, the process flow concentrates on manufacture of the thin film circuit components. In this particular example, the component is a top gate, low-temperature, polysilicon transistor. 
   The amorphous silicon is deposited at  94 , with p-channel doping occurring at  96 , and n-channel doping at  98 . The gate oxide and metal are deposited at  100 , and the gate masked and etched at  102 . It must be noted that several processes have been compressed for ease of discussion. The more detailed descriptions of these processes can be found in the discussion with regard to  FIGS. 3-6 . The p-type source and drain are formed at  104 , and the corresponding n-type source and drain are formed at  106 . 
   The interlayer dielectric is deposited at  108 , and the contacts are masked and etched to clear them at  110 . The source and drain metal is deposited and etched. Passivation of the circuit component occurs at  122 , with the contacts being cleared of the passivation material at  124 . At this point, the circuit component processing has been substantially completed. At  126 , the protective oxide previously deposited is cleared and the interferometric modulator manufacture process begins. 
   As mentioned above, this is just one example of a serial process flow. The modulator could be manufactured first and then the circuit component. A similar flow would occur for the circuit component, regardless of whether it is top or bottom gate, low-temperature polysilicon, other types of thin film transistors, or thin film diodes. 
   Thus, although there has been described to this point a particular embodiment for a method and apparatus for manufacture of thin film circuit components on the same substrate as an interferometric modulator, it is not intended that such specific references be considered as limitations upon the scope of this invention except in-so-far as set forth in the following claims.