Abstract:
An active pixel sensor circuit comprising a photodiode, a storage node, and a transfer gate between the photodiode and storage node, where the potential barrier between the photodiode and the storage region is maintained during charge accumulation, thereby preventing charge tunneling between the photodiode and the storage region. This is achieved by electrically connecting the transfer gate, which controls charge transfer between the photodiode and the storage region, to the storage region. Connecting the transfer gate to the storage region maintains the potential barrier between the photodiode and the storage region at a threshold voltage during the charge integration period which prevents charge tunneling between the photodiode and the storage node. The threshold voltage is determined by the implant levels used to form the active pixel sensor and can be optimized by using optimum implant levels. This prevention of charge tunneling between the photodiode and the storage node eliminates image lag.

Description:
[0001]     This Patent Application claims priority to the following U.S. Provisional Patent Application, herein incorporated by reference: 
        60/579,929, filed Jun. 15, 2004.       
 
     
    
     BACKGROUND OF THE INVENTION  
       [0003]     (1) Field of the Invention  
         [0004]     This invention relates to an active pixel sensor, APS, having a transfer gate biased such that the potential barrier between the photodiode and the storage region is not affected by the charge accumulated by the photodiode.  
         [0005]     (2) Description of the Related Art  
         [0006]     U.S. Pat. No. 6,025,935 to Tseng describes a mechanism to pre-charge or inject a background charge into a storage node and allow the charge to reset through the same output base-to-emitter junction. This removes the residual image and improves the photo-response linearity.  
         [0007]     U.S. Pat. No. 5,900,623 to Tsang et al. describes an active pixel sensor using a plurality of photocells, each including a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode.  
         [0008]     U.S. Pat. No. 6,566,697 B1 to Fox et al. describes a transistor coupled between a pinned photodiode and a storage node.  
         [0009]     U.S. Pat. No. 6,501,109 B1 to Chi describes a pixel having a photodiode for light collection and a floating gated output diode for output of gate-induced-drain-leakage current to a sense amplifier. The structure is used to reduce blooming and improve image-lag performance.  
       SUMMARY OF THE INVENTION  
       [0010]     One type of active pixel sensor, APS, is shown in  FIG. 1 . In this configuration a first N well  12  of N −  type silicon is formed in a P type silicon epitaxial substrate  10 . The junction between the first N well  12  and the substrate  10  forms a photodiode for accumulating charge due to a light signal incident on the first N well  12 . A second N well  14  of N +  type silicon serves as a storage region. The charge accumulated by the photodiode is transferred to the storage region  14  under the control of the transfer gate  18 . The transfer gate is formed on a layer of oxide or other dielectric  16  and is located between the first N well  12  and the second N well  14 . The transfer gate is typically set to a global potential V TG1 . A reset and detection circuit comprising a first N channel field effect transistor, NFET,  22 , a second NFET  24 , and a third NFET  26  is used to reset the photodiode at the beginning of the charge accumulation period and to readout the charge that has been transferred to the storage region  14 . The source of the first NFET  22  and the source of the second NFET  24  are electrically connected to the supply voltage, V DD . The drain of the first NFET  22  and the gate of the second NFET  24  are electrically connected to the storage region  14 .  
         [0011]     One of the problems encountered with the above described APS is that as the photodiode accumulates charge the potential barrier between the photodiode and the storage region decreases and charge tunneling from the photodiode to the storage region will occur. This causes undesirable image lag.  
         [0012]     It is a principal objective of this invention to provide an active pixel sensor circuit where the potential barrier between the photodiode and the storage region is maintained during charge accumulation and charge tunneling between the photodiode and storage region is prevented.  
         [0013]     This objective is achieved by electrically connecting the transfer gate  18  to the storage region  14 . This maintains the potential barrier between the storage region  14  and the photodiode at V t , where V t , is a threshold voltage, during the charge integration period and charge tunneling between the photodiode and the storage node  14  is prevented. This threshold voltage, V t , is determined by the implant levels used to form the active pixel sensor. Optimum implant levels can be chosen to achieve an optimum threshold voltage. This prevention of charge tunneling between the photodiode and the storage node  14  eliminates image lag.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  shows a schematic diagram of a typical APS circuit with the transfer gate connected to a global potential.  
         [0015]      FIG. 2  shows a schematic diagram of the APS circuit of this invention using N type wells formed in a P type substrate and a single transfer gate.  
         [0016]      FIG. 3  shows a schematic diagram of the APS circuit of this invention using N type wells formed in a P type substrate, a first transfer gate connected to the storage region, and a second transfer gate to provide snapshot capability.  
         [0017]      FIG. 4  shows a schematic diagram of the APS circuit of this invention using P type wells formed in an N type substrate and a single transfer gate.  
         [0018]      FIG. 5  shows a schematic diagram of the APS circuit of this invention using P type wells formed in an N type substrate, a first transfer gate connected to the storage region, and a second transfer gate to provide snapshot capability.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]      FIG. 2  shows a schematic diagram of a first preferred embodiment of the active pixel sensor, APS, of this invention. As shown in  FIG. 2 a  first N well  12  of N −  type silicon is formed in a P type silicon epitaxial substrate  10 . The junction between the first N well  12  and the substrate  10  forms a photodiode for accumulating charge due to a light signal incident on the first N well  12 . A second N well  14  of N +  type silicon is also formed in the P type epitaxial substrate  10  and serves as a storage region. The charge accumulated by the photodiode is transferred to the storage region  14  under the control of a transfer gate  18 . The transfer gate  18  is formed of a conducting material, such as polysilicon, on a layer of dielectric  16 , such as silicon dioxide, and is located between the first N well  12  and the second N well  14 . The transfer gate  18  and the second N well  14  are electrically connected together so that the potential between the second N well and the photodiode is held at a threshold voltage V t , where the threshold voltage is determined by the implant levels used to form the active pixel sensor. Typically optimum implant levels are used to produce an optimum threshold voltage.  
         [0020]     A reset and detection circuit comprising a first N channel field effect transistor, NFET,  22 , a second NFET  24 , and a third NFET  26  is used to reset the photodiode at the beginning of the charge accumulation period and to readout the charge that has been transferred to the storage region  14 . The source of the first NFET  22  and the source of the second NFET  24  are electrically connected to the supply voltage, VDD, which is the highest potential in the circuit. The drain of the first NFET  22  and the gate of the second NFET  24  are electrically connected to the transfer gate and the storage region  14 . The gate of the first NFET  22  is connected to a reset signal voltage, V RST , which turns the first NFET  22  on during reset. The drain of the third NFET  26  is connected to an output signal terminal, V OUT . The gate of the third NFET  26  is connected to a row signal voltage, V ROW , which turns the third NFET  26  on during readout.  
         [0021]     A key element of this invention, as shown in  FIG. 2 , is that the transfer gate  18  is electrically connected to the storage region  14 , rather than to a global voltage supply. As charge is accumulated by the first N well  12  during the charge accumulation period the potential of the storage region  14  will be affected, however the potential under the transfer gate tracks the potential of the storage region  14 . This maintains the potential barrier between the first N well  12  and the storage region  14  at the threshold voltage, V t , during the charge integration period thereby preventing charge tunneling between the first N well and the storage region  14  until the charge is to be readout. An additional advantage is noise immunity since the transfer gate is not connected to a global voltage supply and is therefore not affected by power supply noise. During the reset period the amount of charge required to reset the pixel is the amount of charge accumulated by the first N well  12  during the charge integration period.  
         [0022]     A second preferred embodiment of this invention is shown in  FIG. 3 . As shown in  FIG. 3 a  first N well  12  of N −  type silicon is formed in a P type silicon epitaxial substrate  10 . The junction between the first N well  12  and the substrate  10  forms a photodiode for accumulating charge due to a light signal incident on the first N well  12 . A second N well  14  of N +  type silicon is also formed in the P type epitaxial substrate  10  and serves as a storage region. The charge accumulated by the photodiode is transferred to the storage region  14  under the control of a first transfer gate  19 . The first transfer gate  19  is formed of a conducting material, such as polysilicon, on a layer of dielectric  16 , such as silicon dioxide, and is located between the first N well  12  and the second N well  14 . As shown in  FIG. 3 , in this embodiment a second transfer gate  20 , formed of a conducting material such as polysilicon, is also formed on the layer of dielectric  16  in the region between the first N well  12  and the storage region  14 . A key part of this invention is that the first transfer gate  19  is electrically connected to the storage region  14 . Since the first transfer gate  19  and the second N well  14  are electrically connected together, the potential between the second N well  14  and the photodiode is held at a threshold voltage V t , where the threshold voltage is determined by the implant levels used to form the active pixel sensor. Typically optimum implant levels are used to produce an optimum threshold voltage. The second transfer gate  20  is connected to a global voltage supply, V TG2 , and provides a shutter which gives snapshot capability. The second transfer gate  20  is used only as a complete barrier to charge transfer or is completely on and is not part of the charge transfer mechanism, so the second transfer gate does not detract from the advantages of connecting the first transfer gate  16  to the storage region  14 .  
         [0023]     A reset and detection circuit comprising a first N channel field effect transistor, NFET,  22 , a second NFET  24 , and a third NFET  26  is used to reset the photodiode at the beginning of the charge accumulation period and to readout the charge that has been transferred to the storage region  14 . The source of the first NFET  22  and the source of the second NFET  24  are electrically connected to the supply voltage, V DD , which is the highest potential in the circuit. The drain of the first NFET  22  and the gate of the second NFET  24  are electrically connected to the transfer gate and the storage region  14 . The gate of the first NFET  22  is connected to a reset signal voltage, V RST , which turns the first NFET  22  on during reset. The drain of the third NFET  26  is connected to an output signal terminal, V OUT . The gate of the third NFET  26  is connected to a row signal voltage, V ROW , which turns the third NFET  26  on during readout.  
         [0024]     A key element of this second embodiment, as shown in  FIG. 3 , is that the first transfer gate  19  is electrically connected to the storage region  14 , rather than to a global voltage supply. As charge is accumulated by the first N well  12  during the charge accumulation period the potential of the storage region  14  will be affected, however the potential under the first transfer  19  gate tracks the potential of the storage region  14 . This maintains the potential barrier between the first N well  12  and the storage region  14  at the threshold voltage, V t , during the charge integration period thereby preventing charge tunneling between the first N well  12  and the storage region  14  until the charge is to be readout. An additional advantage is noise immunity since the transfer gate is not connected to a global voltage supply and is therefore not affected by power supply noise. During the reset period the amount of charge required to reset the pixel is the amount of charge accumulated by the first N well  12  during the charge integration period.  
         [0025]     In the following two embodiments the P type silicon substrate is replaced by an N type silicon substrate, N −  type silicon regions are replaced by P −  type silicon regions, N +  type silicon regions are replaced by P +  type silicon regions, N channel field effect transistors are replaced by P channel field effect transistors, and the highest potential in the circuit is replaced by the lowest potential in the circuit.  
         [0026]     A third preferred embodiment of the active pixel sensor, APS, of this invention is shown in  FIG. 4 . As shown in  FIG. 4 a  first P well  13  of P −  type silicon is formed in an N type silicon epitaxial substrate  11 . The junction between the first P well  13  and the substrate  11  forms a photodiode for accumulating charge due to a light signal incident on the first P well  13 . A second P well  15  of P +  type silicon is also formed in the N type epitaxial substrate  11  and serves as a storage region. The charge accumulated by the photodiode is transferred to the storage region  15  under the control of a transfer gate  18 . The transfer gate  18  is formed of a conducting material, such as polysilicon, on a layer of dielectric  16 , such as silicon dioxide, and is located between the first P well  13  and the second P well  15 . The transfer gate  18  and the second P well  15  are electrically connected together so that the potential between the second P well  15  and the photodiode is held at a threshold voltage V t , where the threshold voltage is determined by the implant levels used to form the active pixel sensor. Typically optimum implant levels are used to produce an optimum threshold voltage.  
         [0027]     A reset and detection circuit comprising a first P channel field effect transistor, PFET,  32 , a second PFET  34 , and a third PFET  36  is used to reset the photodiode at the beginning of the charge accumulation period and to readout the charge that has been transferred to the storage region  15 . The source of the first PFET  32  and the source of the second PFET  34  are electrically connected to the supply voltage, V DD , which is the lowest potential in the circuit. The drain of the first PFET  32  and the gate of the second PFET  34  are electrically connected to the transfer gate and the storage region  15 . The gate of the first PFET  32  is connected to a reset signal voltage, V RST , which turns the first PFET  32  on during reset. The drain of the third PFET  36  is connected to an output signal terminal, V OUT . The gate of the third PFET  36  is connected to a row signal voltage, V ROW , which turns the third PFET  36  on during readout.  
         [0028]     A key element of this third embodiment, as shown in  FIG. 4 , is that the transfer gate  18  is electrically connected to the storage region  15 , rather than to a global voltage supply. As charge is accumulated by the first P well  13  during the charge accumulation period the potential of the storage region  15  will be affected, however the potential under the transfer gate tracks the potential of the storage region  15 . This maintains the potential barrier between the first P well  13  and the storage region  15  at the threshold voltage, V t , during the charge integration period thereby preventing charge tunneling between the first P well  13  and the storage region  15  until the charge is to be readout. An additional advantage is noise immunity since the transfer gate is not connected to a global voltage supply and is therefore not affected by power supply noise. During the reset period the amount of charge required to reset the pixel is the amount of charge accumulated by the first P well  13  during the charge integration period.  
         [0029]     A fourth preferred embodiment of this invention is shown in  FIG. 5 . As shown in  FIG. 5 a  first P well  13  of P −  type silicon is formed in an N type silicon epitaxial substrate  11 . The junction between the first P well  13  and the substrate  11  forms a photodiode for accumulating charge due to a light signal incident on the first P well  13 . A second P well  15  of P +  type silicon is also formed in the N type epitaxial substrate  111  and serves as a storage region. The charge accumulated by the photodiode is transferred to the storage region  15  under the control of a first transfer gate  19 . The first transfer gate  19  is formed of a conducting material, such as polysilicon, on a layer of dielectric  16 , such as silicon dioxide, and is located between the first P well  13  and the second P well  15 . As shown in  FIG. 5 , in this embodiment a second transfer gate  20  is formed of a conducting material, such as polysilicon, on the dielectric layer  16  over the region between the first P well  13  and the storage region  15 . As in the third embodiment, the first transfer gate  19  is electrically connected to the storage region  15 . Since the first transfer gate  19  is electrically connected to the storage region  15  the potential between the storage region  15  and the photodiode is held at the threshold voltage, V t , where the threshold voltage is determined by the implant levels used to form the active pixel sensor. Typically optimum implant levels are used to produce an optimum threshold voltage. The second transfer gate  20  is connected to a global voltage supply, V TG2 , and provides a shutter which gives snapshot capability. The second transfer gate  20  is used only as a complete barrier to charge transfer or is completely on and is not part of the charge transfer mechanism, so the second transfer gate does not detract from the advantages of connecting the first transfer gate  16  to the storage region  15 .  
         [0030]     A reset and detection circuit comprising a first P channel field effect transistor, PFET,  32 , a second PFET  34 , and a third PFET  36  is used to reset the photodiode at the beginning of the charge accumulation period and to readout the charge that has been transferred to the storage region  15 . The source of the first PFET  32  and the source of the second PFET  34  are electrically connected to the supply voltage, V DD , which is the lowest potential in the circuit. The drain of the first PFET  32  and the gate of the second PFET  34  are electrically connected to the transfer gate and the storage region  15 . The gate of the first PFET  32  is connected to a reset signal voltage, V RST , which turns the first PFET  32  on during reset. The drain of the third PFET  36  is connected to an output signal terminal, V OUT . The gate of the third PFET  36  is connected to a row signal voltage, V ROW , which turns the third PFET  36  on during readout.  
         [0031]     A key element of this fourth embodiment, as shown in  FIG. 5 , is that the first transfer gate  19  is electrically connected to the storage region  15 , rather than to a global voltage supply. As charge is accumulated by the first P well  13  during the charge accumulation period the potential of the storage region  15  will be affected, however the potential under the transfer gate tracks the potential of the storage region  15 . This maintains the potential barrier between the first P well  13  and the storage region  15  at the threshold voltage, V t , during the charge integration period thereby preventing charge tunneling between the first P well  13  and the storage region  15  until the charge is to be readout. An additional advantage is noise immunity since the transfer gate is not connected to a global voltage supply and is therefore not affected by power supply noise. During the reset period the amount of charge required to reset the pixel is the amount of charge accumulated by the first P well  13  during the charge integration period.  
         [0032]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.