Abstract:
A high voltage CMOS switch circuit having an arrangement of device connections such that the individual transistor devices are substantially the same size, improving performance while reducing size and providing breakdown protection. The circuit switches a high voltage to the output based on a low voltage input. The circuit is ratio-less and self-biased, capable of operating a very low supply voltage compared to the state of the art.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated circuits, more particularly to complementary metal oxide semiconductor integrated circuit switching devices, and more specifically to a ratio-less, high voltage, CMOS, switch for non-volatile memory, address data decoding, integrated circuit devices. 
     2. Description of Related Art 
     Complementary metal oxide silicon (“CMOS”) technology is a preferred fabrication process for many integrated circuit (“IC”) devices, particularly those in which low power consumption and high component density are priorities. Many publications describe the details of common techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures; see e.g.,  Silicon Processes , Vol. 1-3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation (assignee herein), Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and common fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” The commonly used term “chip” is used to refer to an entire IC device. As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art. 
     In programmable non-volatile memory cells, such as row and column address decoder outputs, it is generally known to use a circuit that switches a relatively high voltage to the output based on a relatively low voltage input for an addressed cell. It will be recognized by those skilled in the art that such “switch” circuits (any electronic circuit that reverses and maintains a state, namely HIGH/LOW or 1/0, each time the input power changes) can have many other uses, such as signal level translators, output pad drivers, programming circuits, and the like. 
     FIG. 1 (Prior Art) is an electrical schematic of a typical IC, non-volatile memory, address decoder output, high voltage switching circuit  100 , “high V switch” for short. Four metal-oxide-silicon field effect transistors (“MOSFET”), N 1 , N 2 , P 1  (n-well device), P 2  (n-well device) and an inverter are used. [It will be recognized by those skilled in the art that all dopant types can be reversed]. The high V switch receives an input Enable signal, “En,” having a transition either from LOW-to-HIGH or HIGH-to-LOW (e.g., between a zero volt LOW and a two-and-a-half volt HIGH or other logic power supply voltage, “Vcc,” depending on the fabrication process design), and provides an output signal “OUT” that needs to be driven correspondingly (e.g., between a zero volt LOW and a thirteen volt HIGH or other generated fabrication process design level). The power supply to the circuit is a high voltage, “Vpp,” generated internally by other known manner circuitry of the IC (not shown), e.g., the desired output level, thirteen volts. In operation, when signal En is LOW, the inverter output, INV, is HIGH and transistor N 2  is ON, transistor P 1  is ON, transistors N 1  is OFF and P 2  are OFF (gate and source at Vpp), so OUTB is at Vpp and the signal OUT is switched to LOW. Note that N 1  and P 1  must be. designed in relative size to have a size ratio wherein N 1  is a much larger individual device than P 1 ; similarly the size of N 2 &gt;&gt;P 2 . Thus, when signal En goes HIGH/Vcc, the inverter output goes LOW and N 2  is OFF, N 1  being ON overcomes P 1 , OUTB is pulled LOW, turning ON P 2  which feeds back into P 1  also trying to shut P 1  OFF, P 2  being ON is passing Vpp to switch the OUT signal node (and at the same time also turning OFF P 1 ). In other words, to make the signal transition with this conventional circuit, the N 1  and N 2  devices have to overcome P 1  and P 2  devices so they must be much larger in design, using valuable IC chip space. Depending on the process and device parameters N 1  and N 2  may be as much as five times as large as P 1  and P 2 . Thus, this circuit is also relatively slow. Moreover, during this difficult transition, excessive power is used. Furthermore, the individual devices must be built to handle the high voltage without breakdowns (grounded gate (e.g, in FIG. 1 when N 1  is OFF, having the gate at LOW and the source grounded, yet the OUT node is at Vpp at the start of an En LOW and INV transition to 1), n-well (e.g., in the p-type devices, the n-well is tied to Vpp), n+/p+ junction breakdowns), such as by having relatively very thick (&gt;250 Angstroms) gate oxide to handle the high voltage levels, complicating fabrication process steps. 
     It is common to shorthand the system function via a logic table, such as Table 1, also provided for the remaining Figures discussed: 
     
       
         
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 En 
                 INV 
                 N1 
                 P1 
                 N2 
                 P2 
                 OUTB 
                 OUT 
               
               
                   
               
             
             
               
                 LOW 
                 1 
                 OFF 
                 ON 
                 ON 
                 OFF 
                 Vpp 
                 LOW 
               
               
                 HI/Vcc 
                 LOW 
                 ON 
                 OFF 
                 OFF 
                 ON 
                 LOW 
                 Vpp 
               
               
                   
               
             
          
         
       
     
     Another prior art high voltage switch circuit is shown in FIG. 2 (Prior Art). This circuit is designed to handle grounded gate problems via a cascode arrangement of MOSFET transistors. Cascoded N 3  and N 4  are connected at their respective gates to Vcc. The respective drain electrodes at N 1  and N 2  never reach Vpp but when the signal OUT node or the signal OUTB node is raised to Vpp, the drain electrodes are only at Vcc−Vtn, where Vt is the threshold voltage for the n-type MOSFETS, thus, the drain-source voltage, Vds, remains smaller than Vpp. Thus grounded gate breakdown is no longer a problem. Obviously, however, even more chip real estate is required than for the circuit of FIG.  1 . For the p-channel devices, cascoded P 3  and P 4  are tied to a gate bias voltage, GBIAS. That bias voltage is strategically selected according to design parameters to prevent grounded gate breakdown in the pull-up side of the circuit. However, to switch the switch, a timing sequence must be implemented, thus complicating design. In other words, initially to decode the correct En signal transition, GBIAS is held at zero volts until an En transition when signal OUTB is HIGH, then raise Vpp and GBIAS levels. Note also that the n-wells of the p-type devices P 1 - 4  are again tied to Vpp, but P 3  and P 4  are not source-tied to Vpp; therefore, separate n-wells are required, again adding design and fabrication complexity. Note also, the series-coupled extra transistors on both sides of the switch will be an inherently slower reacting circuit. Also this design still requires N-to-P size ratios because each N-stack must overcome the respective P-stack connected in series thereto to flip the switch between HIGH/LOW states. Thus, design and area complexity is a main drawback to this solution to the problems with high voltage CMOS switch circuits. 
     There is a need for a faster, small, simpler design for a high voltage CMOS switch. 
     SUMMARY OF THE INVENTION 
     In its basic aspects, the present invention provides a high voltage CMOS switch including: first devices for signal switching coupled to an input electrode, having a first logic state and a second logic state, and arranged as a parallel-connected, cascode input device and biased at a first electrical potential; and second devices for signal switching, coupled to said first devices and to a second electrical potential greater than said first electrical potential and to an output electrode, and arranged as a parallel-connected cascode output device coupled to said input electrode such that said second devices is pre-biased to said first electrical potential such that switching occurs at the output from said first electrical potential to said second electrical potential without said first devices being required to over-drive said second devices. 
     In another aspect, the present invention provides a high voltage switch circuit device, including: an input node; a first output node; a second output node; a first source of electrical potential level; a second source of electrical potential level greater than the first source of electrical potential; an inverter connected to the input node; a first cascode, biased by said first source of electrical potential level, connected to said input node; a second cascode biased by said first source of electrical potential, and connected in series via the inverter with the first cascode, the second cascode connected to said output node; a third cascode, biased by a signal on the input node, connected in series with the first cascode, and connecting said second source of electrical potential level to said first output node; a fourth cascode, biased by an output signal of the inverter, connected in series with the second cascode, and connecting said second source of electrical potential level to said second output node, wherein a transition of a signal level between a reference and a second state equal to said first source of electrical potential level on said input node causes a transition on said output node between said first source of electrical potential level and said second source of electrical potential level without said first cascode having to over-drive said third cascode and without said second cascode having to over-drive said fourth cascode. 
     In another aspect, the present invention provides a memory decoder circuit including a high voltage switch device comprising: first devices for signal switching coupled to an input electrode, having a first logic state and a second logic state, and arranged as a parallel-connected, cascode input device and biased at a first electrical potential; and second devices for signal switching, coupled to said first devices and to a second electrical potential greater than said first electrical potential and to an output electrode, and arranged as a parallel-connected cascode output device coupled to said input electrode such that said second devices is pre-biased to said first electrical potential such that switching occurs at the output from said first electrical potential to said second electrical potential without said first devices being required to over-drive said second devices. 
     Some of the advantages of the present invention are: 
     it is a ratio-less MOSFET design; 
     it has built-in grounded gate breakdown protection when required; 
     it minimizes chip real estate requirements; 
     it is a relatively faster switch; 
     it requires no external, global bias; 
     it is a self-biased cascode; 
     it operates a very low Vcc compared to state of the art devices; and 
     it has a plurality of uses. 
     The foregoing summary and list of advantages is not intended by the inventor(s) to be an inclusive list of all the aspects, objects, advantages and features of the present invention nor should any limitation on the scope of the invention be implied therefrom. This Summary is provided in accordance with the mandate of 37 C.F.R. 1.73 and M.P.E.P. 608.01(d) merely to apprise the public, and more especially those interested in the particular art to which the invention relates, of the nature of the invention in order to be of assistance in aiding ready understanding of the patent in future searches. Other objects, features and advantages of the present invention will become apparent upon consideration of the following explanation and the accompanying drawings, in which like reference designations represent like features throughout the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 (Prior Art) is an electrical schematic diagram for a first conventional high voltage CMOS switching circuit. 
     FIG. 2 (Prior Art) is an electrical schematic diagram for a second conventional high voltage CMOS switching circuit. 
     FIG. 3 is an electrical schematic diagram for the present invention. 
     FIG. 3A is an electrical schematic diagram and logic table for the present invention as shown in FIG. 3, demonstrating a specific implementation. 
     FIG. 3B is an electrical schematic diagram and logic table for the present invention as shown in FIG. 3, with n-well breakdown protection added. 
     FIG. 4 is an electrical schematic diagram and logic table for the present invention implemented in a row decoder. 
     FIG. 5 is an electrical schematic diagram and logic table for the present invention implemented in a column decoder. 
     FIG. 6 is an electrical schematic diagram and logic table for the present invention implemented in a tri-state-able switch. 
    
    
     The drawings referred to in this specification should be understood as not being drawn to scale except if specifically annotated. 
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Reference is made now in detail to a specific embodiment of the present invention, which illustrates the best mode presently contemplated by the inventors for practicing the invention. Alternative embodiments are also briefly described as applicable. 
     FIG. 3 is an electrical schematic diagram for the present invention. The layout consists of: 
     four n-well, thick gate, p-channel MOSFETS P 1 , P 2 , P 3 , P 4 , with P 1  in series with P 3  and P 2  connected in series with P 4 , and with the gate of input stage P 3  connected to the input signal En and the gate of input stage P 4  connected to an inverted input signal Enb (instead of having a GBIAS as shown in FIG.  2 ); 
     four thick gate, n-channel MOSFETS N 1 , N 2 , N 3 , N 4 , where N 3  and N 4  are series connected to N 1  and N 2 , respectively, as gate cascodes to prevent grounded gate breakdown of N 1  and N 2 ; and 
     a thin gate, low voltage CMOS inverter INV connecting input stage N 1  and output stage N 2 . 
     Switching is accomplished when Vpp=Vcc; in other words, at the high voltage input node, HV, whenever not programming, normally input signal En is at a LOW state, HV is at Vcc. Switching the input signal En to HIGH also triggers a known manner IC voltage pump (not shown) to raise HV to Vpp after the device has switched. That is, the circuit is first switched and then Vpp is pumped up to 13-volts (e.g.). Once switched the output node, HV, follows Vpp as it pumps up from Vcc to 13-volts. 
     As shown in FIG. 3A, an electrical schematic diagram and logic table, Table 3A, for the present invention high voltage CMOS switch  300  as shown in FIG. 3, demonstrating a specific implementation in standard design units wherein the MOSFET size is substantially ratio-less. 
     In operation, when input signal En is LOW, steady state, N 1  is OFF, and inverter INV output signal EnB is HIGH, so N 2  is ON. The output signal is at zero volts as N 2  source electrode is at ground potential. P 1  is ON and the gate P 3  is LOW because it is tied to En, so P 3  is ON and the node at OUTB is connected to Vpp. With its gate connected to inverter output signal EnB which is HIGH, P 4  is OFF; with its gate connected to signal OUTB which is at Vpp, P 2  is OFF. Thus, P 4  acts as a gate cascode, protecting P 2  from a grounded gate breakdown since its source electrode is coupled to the high voltage Vpp. Therefore, at this steady state condition with En LOW, there is essentially no power being drawn. Also, being coupled at its gate to logic bias Vcc, N 3  acts as a cascode to protect N 1  from gate breakdown due to the node at OUTB going to Vpp. 
     When input signal En goes to a logic HIGH, Vcc, inverter INV output signal EnB goes LOW and N 1  turns ON. In comparison to FIGS. 1 and 2, when N 1  turned ON, the node at OUTB was brought to LOW because having the ratio set where N 1  was stronger than P 1 , N 1  drove through P 1 ; now, however, the gate of P 3  being tied to input signal En also goes to Vcc, so P 3  is shut OFF. With N 2  now OFF because the output signal EnB of the inverter INV is LOW, the gate of P 4  is coupled to ground, so P 4  is ON and conducting. Since the node at OUTB is now LOW, without the need for a large N 1  to overcome P 3 , P 2  being coupled at its gate to the node at OUTB turns ON. Thus, with both P 2  and P 4  conducting, Vpp is coupled to the output node and signal OUT is at Vpp. The respective drain electrodes at N 1  and N 2  never reach Vpp but when the signal OUTB node or the signal OUT node is raised to Vpp, the drain electrodes are only at Vcc−Vtn, where Vt is the threshold voltage for the n-type MOSFETS and, thus, the voltage, Vds, remains smaller than Vpp. Table 3 represents this logic flow. 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 En 
                 EnB 
                 N1 
                 N2 
                 N3 
                 N4 
                 P1 
                 P2 
                 P3 
                 P4 
                 OutB 
                 OUT 
               
               
                   
               
             
             
               
                 Low 
                 Vcc 
                 Off 
                 On 
                 On 
                 Off 
                 On 
                 Off 
                 On 
                 Off 
                 Vpp 
                 Low 
               
               
                 Vcc 
                 Low 
                 On 
                 Off 
                 Off 
                 On 
                 Off 
                 On 
                 Off 
                 On 
                 Low 
                 Vpp 
               
               
                   
               
             
          
         
       
     
     Therefore, the functionality of a high voltage switch is accomplished in a substantially ratio-less design (channel width can be slightly adjusted for speed design considerations). Moreover, on the p-channel side of the circuit, grounded gate breakdown is accomplished without a gate bias and complicated timing (see FIG. 2 explanation above). That is, the gate cascode to Vcc (Vpp) for P 3  and P 4  happens on the side which needs it and not the other. The gate cascode voltage (=Vcc) comes conveniently from En or EnB nodes (i.e., the data) and does not have to be generated globally. Thus, it is switched. 
     FIG. 3B is an electrical schematic diagram and logic table, Table 3B, for an alternative embodiment of the present invention as shown in FIGS. 3 and 3A, a high voltage CMOS switch  300 ′ with n-well breakdown protection added to the p-channel devices. The operation is essentially the same as that for FIGS.  3  and  3 A. Separate n-wells are required. P 1  and P 2  are in the same n-well. This is used when Vpp is higher than the P+ to n-well junction breakdown; when (referring to FIG. 3A) when OUT is zero-volt and Vpp is greater than 13-volts. 
     FIG. 4 is an electrical schematic diagram and logic table, Table 4 (where “or” is represented by a slash “/” mark), for the present invention implemented in a row decoder  400  for a row and column matrix of memory cells, e.g., a conventional electrically erasable and programmable read only memory (EEPROM or E 2 PROM). The high voltage switch  300  is used between a known manner, row decoder, p-channel MOSFET input stage  401  and p-channel MOSFET output stage  403 . In this implementation, the output signal is the row select signal, PROW. A high voltage signal (corresponding to nodes for OUT and OUTB signals in FIGS. 1-3B) is represented by signals HV with the inverted signal being HVB. 
     The output stage  403  couples Vcc to the appropriate row during a steady state condition of a non-volatile memory conventional operation and whenever that row is deselected. Norma/Verify/Erase of Table 4. Only during programming is the high voltage Vpp channeled to a selected row. In other words, when the enable signal En goes HIGH, signal HV goes to Vpp, the decoder output stage  403  is shut OFF. Signal HVB is grounded, so the decoder input stage  401  passes Vpp through as signal PROW at a row decoder output node 405. When signal En is LOW, with Vpp at the high voltage level greater than Vcc, node HV is at zero volts (grounded through the switch  300 ) and signal HVB is at Vpp, so the decoder input stage  401  is OFF and the decoder output stage  403  is ON, putting Vcc at the node  405  as signal PROW. Thus the output is switched between Vcc and Vpp (rather than LOW=zero volts and Vpp as in FIG.  3 ). 
     FIG. 5 is an electrical schematic diagram and logic table, Table 5, for the present invention implemented in a column decoder  500 , generally used in conjunction with the row decoder  400  of FIG.  4 . The high voltage switch  300  is used between a known manner column decoder, p-channel device, input stage  501  and p-channel and n-channel (P 5  and N 5 ) device output stage  503 . In a non-volatile memory IC, a Bulk Erase, BE, mode is provided via the column decoding circuitry. As shown in Table 5, four output signals—zero volts/LOW, Vcc, Vpp, and a BIAS level are needed at the column decoder output node  505 , signal PPTG. 
     Turning ON the input stage  501  supplies Vpp to the output node  505  via the high voltage switch  300 ; HVB is at LOW, MOSFET N 5  and MOSFET P 5  are OFF, so that the path to the BIAS level is cut off; therefore HV is at Vpp and is passed on to column decoder output node  505 . 
     When the enable signal En is LOW, HVB is at Vpp, shutting OFF the input stage  501 . MOSFET N 5  is turned ON. HV is grounded to zero volts. Grounding the gate at MOSFET P 5  turns P 5  ON. Therefore output stage  503  is a full CMOS switch acting as a pass gate for the BIAS level, or Vcc, or LOW/zero volts to the output node  505 , seen as column decode signal PPTG. In other words, turning ON the output stage  503  supplies either the BIAS level or Vcc or zero-volts to the output node  505  depending upon current operation mode per known manner control circuitry. 
     FIG. 6 is an electrical schematic diagram and logic table, Table 6, for the present invention implemented in a tri-state-able switch  600  circuit. The high voltage CMOS switch  300  has four nodes  301  (En),  302  (OUT),  303  (OUTB),  304  (EnB) for coupling signal inputs to a circuit output stage  601 , which includes five stacked, p-channel MOSFETS I 4 , I 5 , I 6 , I 7 , I 8  (I 3  is a n-channel MOSFET). Table 5 provides the logic signal analysis for the available states. 
     The output “mcg” is used to bulk erase E 2 PROM cells. To bulk erase, Vpp of 13-volts is switched onto the mcg-node. When not in a bulk erase mode and in various other modes, other circuits can apply a bias voltage to the mcg-node via the “external” input. This circuit then acts as a high impedance circuit. 
     In essence, when the input signal En is LOW, output signal MCG on an output node  605  is Z-volts (also known in the art as “HIGH Z”). An externally supplied voltage, “external,” drives it to a bias voltage or zero-volts. Output stage  601  MOSFETS I 3 , I 4  and I 5  form a cascoded high voltage inverter, preventing leakage during margin testing when “mcg” is taken HIGH externally. In this condition, HV is LOW, turning I 3  OFF; therefore any HIGH voltage on mcg-node passes through on devices I 5  and I 4  to the gate of I 6  , shutting I 6  Off and making the circuit look like a high impedance, HIGH-Z state, applying the proper gate voltage to a HIGH voltage state, viz., when input signal En is HIGH. Output stage  601  MOSFETS I 7  and I 8  form a grounded gate breakdown voltage cascode when En is HIGH and the output of the tristate switch is tied to high voltage input level Vpp. Output stage  601  MOSFET I 6  prevents a forward bias during a slow MCG discharge compared to a Vpp discharge. 
     In operation then, when signal En is HIGH, Vcc, the high voltage CMOS switch reacts as explained with respect to FIGS. 3-3B, so therefore signal HV is HIGH and signal HVB is LOW. MOSFET I 7  is ON. Output signal MCG is at the Vpp voltage level. The gate of 18 is tied to EnB which is LOW, therefore I 8  is ON. Since HV is HIGH, MOSFET I 5  is OFF, but MOSFETS I 3  and I 6  are ON. Therefore, MCG is tied to the Vpp level. 
     When En is LOW, EnB is HIGH, so HV is LOW and HVB is HIGH, shutting OFF MOSFET I 7 . The gate of MOSFET I 8  is HIGH and is OFF. With MOSFETS I 7  and I 8  OFF, there is no path for voltage potential level Vpp to the output node  605 . Node  605  and the output MCG is only tied to an external voltage, Z/external. When En is LOW, EnB is HIGH, so HV is LOW and HVB is HIGH, shutting OFF MOSFET I 3  is OFF, MOSFET I 5  In ON, MOSFET I 4  is ON. MOSFETS I 3  and I 5  act as an inverter with MOSFET I 4  cascode connecting them for grounded gate breakdown events. The n-wells of MOSFET I 6 , MOSFET I 5  and MOSFET I 4  gates are all tied together to the mcg-node to prevent junction forward bias. 
     The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. Similarly, any process steps described might be interchangeable with other steps in order to achieve the same result. The embodiment was chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents. Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather means “one or more.” Moreover, no element, component, nor method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the following claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . .”