Abstract:
A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    The present application is related to the subject matter within commonly-assigned, copending patent applications entitled “HIGH LINEARITY, LOW POWER VOLTAGE CONTROLLED RESISTOR” (Docket 00-P-208) and “ENHANCED FOLDED CASCODE VOLTAGE GAIN CELL” (Docket 00-P-210). The content of the above-identified applications is incorporated herein by reference.  
         TECHNICAL FIELD OF THE INVENTION  
         [0002]    The present invention is directed, in general, to tuning circuits and, more specifically, to producing a stable, process independent RC time constant for use in automatic tuning of continuous time filters.  
         BACKGROUND OF THE INVENTION  
         [0003]    Continuous-time filters, such as intermediate frequency (IF) communications filters and video processors, generally require frequency tuning within the filter to match a specified frequency. Existing on-chip automatic tuning techniques typically employ a phase-lock loop (PLL), introducing poles in the feedback loop and therefore creating stability issues.  
           [0004]    Additionally, frequency response precision within continuous-time filters is often constrained by RC time constant variances from one circuit to another due to fabrication process tolerances, operating temperature variations, and aging.  
           [0005]    There is, therefore, a need in the art for a stable RC time constant within automatic tuning circuits.  
         SUMMARY OF THE INVENTION  
         [0006]    To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in on-chip automatic tuning, a stable, process independent RC time constant for precision frequency response, generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.  
           [0007]    The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.  
           [0008]    Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:  
         [0010]    [0010]FIG. 1 depicts an RC time constant circuit for use in automatic tuning according to one embodiment of the present invention; and  
         [0011]    [0011]FIG. 2 is a plot of the feedback loop voltage and corresponding input and output currents of a current peak detector within an RC time constant circuit according to one embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]    [0012]FIGS. 1 and 2, discussed below, and the embodiment used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged device.  
         [0013]    [0013]FIG. 1 depicts an RC time constant circuit for use in automatic tuning according to one embodiment of the present invention. The RC time constant circuit design of the present invention assumes that a stable timer (e.g., a crystal oscillator) and a stable current source are available. Circuit  100  includes a square wave generator  101  taking as an input a current from current source I 1  triggered by a stable clock signal CLK and connected between the input terminal I i  of square wave generator  101  and a ground voltage gnd. A resistor R 1  is connected between the input terminal R i  of square wave generator and the ground voltage gnd. Square wave generator  101  supplies a square wave having an amplitude equal to the input current from current source I 1  times the resistance of resistor R 1 . The signal at node NET 1  is therefore:  
           V   1   =I   i   R   i   =I   1 R 1 .  (1)  
         [0014]    The output of square wave generator  101  is connected to a pair of series-connected voltage-to-current converters  102  and  103 . Voltage-to-current converter  102  is connected to node NET 1  at an input terminal V i . A voltage-controlled resistor R 6  is connected between an input terminal R i  for voltage-to-current converter  102  and the ground voltage gnd. Voltage-controlled resistor R 6  is preferably implemented as described in the related application identified above entitled “HIGH LINEARITY, LOW POWER VOLTAGE CONTROLLED RESISTOR” or any kind of variable transconductor such as, for example, a GM-C filter.  
         [0015]    The output current from voltage-to-current converter  102  is equal to the input voltage V 1  at input terminal V i  divided by the resistance at input terminal R i  of the voltage-to-current converter  102 , which in the embodiment depicted is the resistance between terminals d and s of voltage-controlled resistor R 6 . However, the presence of capacitance C 0  connected between node NET 2  and the ground voltage gnd will result in a triangular wave voltage signal at node NET 2 . The peak voltage VP 2  of the triangular wave signal at node NET 2  is therefore  
                 VP   2     =         V   1     ·     T   /   2           C   0     ·     R   6           ,           (   2   )                               
 
         [0016]    where T is the period of the clock signal CLK.  
         [0017]    Voltage-to-current converter  103  is the same as voltage-to-current converter  102 , producing an ouput current at terminal I i  which is equal to the input voltage at terminal V i  divided by the resistance and input terminal R i . In the embodiment depicted, where the input terminal I i  for voltage-to-current converter  103  is connected to node NET 2  and a resistor R 3  is connected between terminal R i  and the ground voltage gnd, the peak current IP 3  at node NET 3  is therefore  
               IP   3     =         VP   2       R   3       .             (   3   )                               
 
         [0018]    Voltage-to-current converters  102  and  103  are preferably both implemented utilizing the folded cascode voltage gain cell described in the related application identified above entitled “ENHANCED FOLDED CASCODE VOLTAGE GAIN CELL”. Those skilled in the art will recognize that the folded cascode voltage gain cell does not comprise the entire voltage-to-current converter.  
         [0019]    Node NET 3  is connected to the input terminal IN of a current peak detector  104 , which is connected, in turn, at an output terminal IOUT to node NET 4 . Current peak detector  104  sinks current from node NET 4  at the output terminal IOUT which is equal to the current at the input terminal IN. The signal at node NET 4  may be taken as a voltage conversion of the signal at node NET 3  with a (negative, representing a current gain of −1) conversion factor K 4 :  
           V   4   =K   4   IP   3 .  (4)  
         [0020]    It should be noted that the resistance of voltage-controlled resistor R 6  is a function f(V 4 ) of the voltage V 4  at node NET 4 :  
           R   6   =f ( V   4 ),  
         [0021]    with the resistance decreasing monotonically as the voltage V 4  increases.  
         [0022]    By combining the above equations (1)-(4), the current sunk at the output terminal IOUT of current peak detector  104  may be expressed as:  
             IOUT   =           I   1     ·     R   1     ·     T   /   2           R   3     ·     R   6     ·     C   0         .             (   5   )                               
 
         [0023]    Since a stable time constant τ=R 6 CO is desired from RC time constant circuit  100 , equation (5) may be rewritten as:  
             τ   =         R   6     ·     C   0       =           I   1     ·     R   1     ·     T   /   2           R   3     ·   IOUT       =           I   1     ·     R   1     ·     T   /   2           R   3     ·     I   ref         .                 (   6   )                               
 
         [0024]    The time constant τ is therefore stable because the loop from node NET 4  through the voltage-controlled resistor R 6  to voltage-to-current converter  102  forces the current at the output terminal IOUT of current peak detector  104  to be the same as the current produced by current source I ref . Moreover, the RC time constant circuit  100  is fabrication process independent since process variations will have the same effect on both resistors R 1  and R 3 , which are the only two terms within equation (6) affected by process variations.  
         [0025]    The voltage at node NET 4  is employed to drive other voltage-controlled resistors implemented in the same manner as resistor R 6  in other part of an integrate circuit in order to keep all RC time constants consistent. In the embodiment depicted, a voltage buffer  105  is employed to receive the voltage at node NET 4  and drive that same voltage, through node NETS, to the control terminals of voltage-controlled resistors within a plurality of integrated circuit cells  106   a - 106   d . Each cell  106   a - 106   d  includes a capacitance used together with the voltage-controlled resistance to generate a time constant pole and/or zero.  
         [0026]    The feedback loop of the RC time constant circuit  100  in the present invention does not include a complex phase-locked loop. Because the open-loop transfer function contains only 1 pole (due to the capacitor C 1  connected to node NET 4 ), circuit  100  is intrinsically stable, such that no need exists to consider issues regarding instability of the feedback loop.  
         [0027]    [0027]FIG. 2 is a plot of the feedback loop voltage and corresponding input and output currents of a current peak detector within an RC time constant circuit according to one embodiment of the present invention. The upper plot depicted is the voltage at node NET 4  within circuit  100 , while the lower plot depicts the input current (triangular waveform trace) at terminal IN of current peak detector  104  and the output current (stepped/steady state trace) sunk at the output terminal IOUT of current peak detector  104 . After the initial transition, the circuit  100  reaches stable biasing without problem.  
         [0028]    Although the present invention has been described in detail, those skilled in the art will understand that various changes, substitutions, and alterations herein may be made without departing from the spirit and scope of the invention in its broadest form.