Abstract:
A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Description:
TECHNICAL FIELD 
     Embodiments of the present invention relate to structures of reliable packages. 
     DISCUSSION OF RELATED ART 
     Thin wafer handling in 2.5D and 3D technologies adds cost and complexity in assembly. In particular, wafer bow and cracking of thin wafers, including the interposer, can cause great difficulty during assembly. Current Chip-on-Wafer-on-Substrate (CoWoS) technologies also face challenges with wafer bow and interposer cracking during fabrication. Furthermore, thermal issues in 2.5D and 3D technologies may also lead to warpage and cracking of the components. 
     Therefore, there is a need for better management of the assembly of packages. 
     SUMMARY 
     In accordance with aspects of the present invention a method of forming a plurality of packages includes etching one or more cavities in a first side of a substrate device, the substrate device including conductive vias formed in a substrate; mounting chip devices to the first side of the substrate device to electrically contact the conductive vias; depositing an encapsulation layer over the chip devices and filling the crack arrest cavities; planarizing a second side to reveal the conductive vias on the second side; and singulating through the cavities to form said packages separated from each other, with each package having one or more of said chip devices mounted on a respective singulated substrate device. 
     In some embodiments, a method of forming a plurality of packages includes mounting a wafer to a first side of a first substrate device to electrically contact with first conducting vias formed in the substrate device; planarizing a second side of the first substrate device to reveal the first conducting vias on the second side; etching one or more cavities in the second side of the first substrate device; depositing an encapsulation layer on the second side of the first substrate device; and singulating through the cavities to form said packages separated from each other, with each package having one or more chip devices mounted on a respective singulated substrate device. 
     In some embodiments, a device can include a substrate device with conductive vias formed in a substrate, the conductive vias being exposed on a second side of the substrate; cavities formed in the substrate device; chip devices mounted to a first side of the substrate device in electrical contact with the conductive vias; and an encapsulation layer covering the chip devices and filling the cavities. 
     In some embodiments, a device can include a substrate device with conductive vias formed in a substrate, the conductive vias being exposed on a second side of the substrate; a wafer mounted on a first side; cavities formed in the substrate device; and an encapsulation layer covering the second side and filling the cavities. 
     These and other embodiments are further discussed below with respect to the following figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a process of assembly according to some embodiments of the present invention. 
         FIGS. 2A through 2M  illustrate further the process of assembly illustrated in  FIG. 1 . 
         FIG. 3  illustrates a process for stacking devices according to some embodiments. 
         FIGS. 4A through 4I  illustrate further the process of stacking illustrated in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, specific details are set forth describing some embodiments of the present invention. It will be apparent, however, to one skilled in the art that some embodiments may be practiced without some or all of these specific details. The specific embodiments disclosed herein are meant to be illustrative but not limiting. One skilled in the art may realize other elements that, although not specifically described here, are within the scope and the spirit of this disclosure. 
     This description and the accompanying drawings that illustrate inventive aspects and embodiments should not be taken as limiting—the claims define the protected invention. Various mechanical, compositional, structural, and operational changes may be made without departing from the spirit and scope of this description and the claims. In some instances, well-known structures and techniques have not been shown or described in detail in order not to obscure the invention. 
     Additionally, the drawings are not to scale. Relative sizes of components are for illustrative purposes only and do not reflect the actual sizes that may occur in any actual embodiment of the invention. Like numbers in two or more figures represent the same or similar elements. Further, descriptive elements such as “above” or “below” are relative to the other elements of the drawing on the drawing page and are not meant to denote absolute directionality. For example, a film described as being above a substrate may, when the substrate is turned over, actually be below the substrate. Therefore, terms such as “above” and ‘below” should not be interpreted as limiting but as providing only relative positioning. 
     Assembly according to some embodiments of the present invention can lead to encapsulation and isolation of devices throughout the assembly. In such cases, there can be little or no thin wafer handling concerns and thermal management can be enhanced. In some embodiments, crack propagation within the wafer or substrate can be arrested. Further, assembly processes according to some embodiments can be highly scalable to large devices or interposer structures. 
       FIG. 1  illustrates a process  100  for providing a package. As shown in  FIG. 1 , a substrate device is supplied in step  102 . As shown in  FIG. 2A , substrate device  200  includes a substrate  202  with through-vias  204  formed in substrate  202 . A redistribution layer (RDL) or back end-of-line layer (BEOL)  206  can be formed over substrate  202  and can be in contact with vias  204 . In some embodiments, substrate  202  can be silicon or glass. Vias  204  can be through-silicon-vias (TSV)s formed with metallization materials. 
     As shown in  FIG. 1 , a cavity etch step  104  is performed on device substrate  200 . As illustrated in  FIG. 2B , an etch mask  208  is formed over layer  206  and device substrate  200  is etched through mask  208  to form crack arrests  210 . In some embodiments, as shown in  FIG. 2B , crack arrests  210  are formed at least as deep into substrate  202  as are vias  204 . In some embodiments, crack arrests  210  are etched as deeply as are vias  204 . Mask  208  can then be removed from over layer  206 . 
     In step  106  of process  100 , as illustrated in  FIG. 2C , a chip device  212  is mounted over layer  206 . Layer  206  provides for interconnects between chip device  212  and vias  204 . In step  108 , as illustrated in  FIG. 2D , an encapsulation layer  214  is deposed over chip device  212  and layer  206  such that crack arrests  210  are filled and chip devices  212  are encapsulated between encapsulation layer  214  and layer  206 . In step  110  of process  100 , as illustrated in  FIG. 2E , encapsulation layer  214  can be planarized so that its thickness is reduced. Encapsulation layer  214 , however, still encapsulates chip devices  212 . Encapsulation material for layer  214  can be a low coefficient of thermal expansion (CTE) dielectric material. In some embodiments, crack arrests  210  can be coated with a thin insulating layer such as TaN or TiN and encapsulation material for layer  214  can be a hard material such as aluminum oxide or other such material. 
     In step  112  of process  100 , as illustrated in  FIG. 2F , substrate  202  (the backside of substrate device  200 ) is ground and planarized to expose vias  204 . In some embodiments, as is shown in  FIG. 2F , crack arrests  210  filled with encapsulation material of layer  214  are also exposed to form isolation bridges. Embodiments where crack arrests  210  are not exposed in step  112  are discussed starting with  FIG. 2J  below. 
     In step  114 , as illustrated in  FIG. 2G , an RDL layer  216  can be formed in contact with vias  204 . 
     As shown in step  116  and illustrated in  FIG. 2H , a singulation process is performed to split substrate device  200  along crack arrests  210 . As such, as is shown in  FIG. 2I , two devices  220  and  222  are separated by cut  218  through crack arrests  210 . Returning to step  112  of process  100 , in some embodiments crack arrests  210  are not exposed. As shown in  FIG. 2J , if crack arrests  210  are not formed as deeply into substrate  202  as is vias  204 , a substrate bridge  224  is formed during planarization. In such a case, crack arrests  210 , filled with encapsulation material of encapsulation layer  214 , are separated from the plane formed by the exposed vias  204  by a remainder of substrate material of substrate layer  202  to form the substrate bridge  224 . 
     In step  114 , as shown in  FIG. 2K , an RDL layer or bonding layer  226  can be formed. As shown in step  116  and illustrated in  FIG. 2L , a singulation process is performed to split substrate device  200  along crack arrests  210 . As such, as is shown in  FIG. 2M , a device  230  is formed by a cut  228  through crack arrests  210 . 
     Forming crack arrests  210  in device substrate  200  and then encapsulating chip devices  212  with encapsulation layer  214  protects chip devices  212  and substrate device  200  from cracking and warping throughout the assembly process. Further, such processes help to thermally manage the process so that thermal effects do not add to the warpage and cracking of the components. 
       FIG. 3  illustrates a process  300  that illustrates some further aspects of embodiments of the present invention. As shown in  FIG. 3 , process  300  starts at step  302  with substrate device  400 . As shown in  FIG. 4A , substrate device  400  may be the same as substrate device  200  shown in  FIG. 2A  and may include a substrate  202 , vias  204 , and an RDL layer  206 . 
     In step  304  a wafer or chip device may be mounted on RDL layer  206 .  FIG. 4B  illustrates a wafer  402  mounted on RDL layer  206 . However, one or more chip devices may be mounted as well. Wafer  402  may represent any combination of other vias and chips mounted on RDL layer  206 . 
     In step  306 , the backside of substrate device  400  may be ground to planarize the device and reveal vias  204 , as is shown in  FIG. 4C . As is illustrated in  FIG. 4C , substrate  202  is ground to reveal vias  204 . In step  308 , and as illustrated in  FIG. 4D , an RDL layer  404  may be deposited in contact with the exposed vias  204 . In some embodiments, RDL layer  404  may be omitted. 
     In step  310 , and as shown in  FIG. 4E , a mask  406  may be formed on RDL layer  404 . Mask  406  may be formed by patterning a resist deposited over RDL layer  404 . In step  312 , and as shown in  FIG. 4F , substrate device  400  is etched through mask  406  to form crack arrests  408 . Mask layer  406  can then be removed. In some embodiments, chip devices (not shown) can be mounted to RDL layer  404 . 
     In step  314 , and as shown in  FIG. 4G , an encapsulation layer  410  is deposited on RDL layer  404  and filling crack arrests  408 . If any chip devices are mounted on RDL layer  404 , then encapsulation layer  410  can encapsulated the mounted chip devices. 
     In step  316 , and as illustrated in  FIG. 4H , the encapsulation layer  410  can be removed to RDL layer  404 , or if any chip devices are mounted on RDL layer  404  to the chip devices, or if RDL layer  404  is absent to expose vias  204 . In step  318 , as shown in  FIG. 4I  another substrate device  412  can be stacked with substrate device  400 . As shown in  FIG. 4I , substrate device  412  can include a substrate  404  with RDL layers  412  and  424  and with vias  418  formed between RDL layers  412  and  424 . Further, crack arrests  420  filled with encapsulation material  422  are formed. Substrate device  412  is mounted to substrate device  400  such that RDL layer  424  contacts RDL layer  404 . As such, substrate device  412  can be formed similarly to substrate device  400  except that wafer  402  is absent. 
     As shown in process  300 , in some embodiments multiple layers can be stacked and backside etching can be performed. It should be noted that aspects of process  300  can be included in process  100  in order to stack multiple components. Further, the stacked combination of substrate device  412  with substrate device  400  can be separated by cutting through crack arrests  420  and crack arrest  410 . 
     In the preceding specification, various embodiments have been described with reference to the accompanying drawings. It will, however, be evident that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set for in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative rather than restrictive sense.