Abstract:
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. 
     The VLSI layouts presented are applicable to generalized multi-stage networks V(N 1 , N 2 , d, s), generalized folded multi-stage networks V fold (N 1 , N 2 , d, s), generalized butterfly fat tree networks V bft (N 1 , N 2 , d, s), generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s), generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s), generalized multi-link butterfly fat tree networks V mlink-bft (N 1 , N 2 , d, s), and generalized hypercube networks V hcube (N 1 , N 2 , d, s) for s=1, 2, 3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel &amp; distributed computing, and reconfigurable computing.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to and claims priority of the PCT Application Serial No. PCT/US08/64605 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 22, 2008, and the U.S. Provisional Patent Application Ser. No. 60/940,394 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007. 
         [0002]    This application is related to and incorporates by reference in its entirety the U.S. application Ser. No. 12/530,207 entitled “FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Sep. 6, 2009, the PCT Application Serial No. PCT/US08/56064 entitled “FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Mar. 6, 2008, the U.S. Provisional Patent Application Ser. No. 60/905,526 entitled “LARGE SCALE CROSSPOINT REDUCTION WITH NONBLOCKING UNICAST &amp; MULTICAST IN ARBITRARILY LARGE MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Mar. 6, 2007, and the U.S. Provisional Patent Application Ser. No. 60/940,383 entitled “FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007. 
         [0003]    This application is related to and incorporates by reference in its entirety the US Patent Application Docket No. V-0038US entitled “FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application filed concurrently, the PCT Application Serial No. PCT/US08/64603 entitled “FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 22, 2008, the U.S. Provisional Patent Application Ser. No. 60/940, 387 entitled “FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007, and the U.S. Provisional Patent Application Ser. No. 60/940, 390 entitled “FULLY CONNECTED GENERALIZED MULTI-LINK BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007. 
         [0004]    This application is related to and incorporates by reference in its entirety the US Patent Application Docket No. V-0039US entitled “FULLY CONNECTED GENERALIZED MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application filed concurrently, the PCT Application Serial No. PCT/US08/64604 entitled “FULLY CONNECTED GENERALIZED MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 22, 2008, the U.S. Provisional Patent Application Ser. No. 60/940, 389 entitled “FULLY CONNECTED GENERALIZED REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007, the U.S. Provisional Patent Application Ser. No. 60/940, 391 entitled “FULLY CONNECTED GENERALIZED FOLDED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007 and the U.S. Provisional Patent Application Ser. No. 60/940,392 entitled “FULLY CONNECTED GENERALIZED STRICTLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007. 
         [0005]    This application is related to and incorporates by reference in its entirety the U.S. Provisional Patent Application Ser. No. 61/252, 603 entitled “VLSI LAYOUTS OF FULLY CONNECTED NETWORKS WITH LOCALITY EXPLOITATION” by Venkat Konda assigned to the same assignee as the current application, filed Oct. 16, 2009. 
         [0006]    This application is related to and incorporates by reference in its entirety the U.S. Provisional Patent Application Ser. No. 61/252, 609 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Oct. 16, 2009. 
     
    
     BACKGROUND OF INVENTION 
       [0007]    Multi-stage interconnection networks such as Benes networks and butterfly fat tree networks are widely useful in telecommunications, parallel and distributed computing. However VLSI layouts, known in the prior art, of these interconnection networks in an integrated circuit are inefficient and complicated. 
         [0008]    Other multi-stage interconnection networks including butterfly fat tree networks, Banyan networks, Batcher-Banyan networks, Baseline networks, Delta networks, Omega networks and Flip networks have been widely studied particularly for self routing packet switching applications. Also Benes Networks with radix of two have been widely studied and it is known that Benes Networks of radix two are shown to be built with back to back baseline networks which are rearrangeably nonblocking for unicast connections. 
         [0009]    The most commonly used VLSI layout in an integrated circuit is based on a two-dimensional grid model comprising only horizontal and vertical tracks. An intuitive interconnection network that utilizes two-dimensional grid model is 2D Mesh Network and its variations such as segmented mesh networks. Hence routing networks used in VLSI layouts are typically 2D mesh networks and its variations. However Mesh Networks require large scale cross points typically with a growth rate of O(N 2 ) where N is the number of computing elements, ports, or logic elements depending on the application. 
         [0010]    Multi-stage interconnection with a growth rate of O(N×log N) requires significantly small number of cross points. U.S. Pat. No. 6,185,220 entitled “Grid Layouts of Switching and Sorting Networks” granted to Muthukrishnan et al. describes a VLSI layout using existing VLSI grid model for Benes and Butterfly networks. U.S. Pat. No. 6,940,308 entitled “Interconnection Network for a Field Programmable Gate Array” granted to Wong describes a VLSI layout where switches belonging to lower stage of Benes Network are layed out close to the logic cells and switches belonging to higher stages are layed out towards the center of the layout. 
         [0011]    Due to the inefficient and in some cases impractical VLSI layout of Benes and butterfly fat tree networks on a semiconductor chip, today mesh networks and segmented mesh networks are widely used in the practical applications such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), and parallel computing interconnects. The prior art VLSI layouts of Benes and butterfly fat tree networks and VLSI layouts of mesh networks and segmented mesh networks require large area to implement the switches on the chip, large number of wires, longer wires, with increased power consumption, increased latency of the signals which effect the maximum clock speed of operation. Some networks may not even be implemented practically on a chip due to the lack of efficient layouts. 
       SUMMARY OF INVENTION 
       [0012]    When large scale sub-integrated circuit blocks with inlet and outlet links are layed out in an integrated circuit device in a two-dimensional grid arrangement, (for example in an FPGA where the sub-integrated circuit blocks are Lookup Tables) the most intuitive routing network is a network that uses horizontal and vertical links only (the most often used such a network is one of the variations of a 2D Mesh network). A direct embedding of a generalized multi-stage network on to a 2D Mesh network is neither simple nor efficient. 
         [0013]    In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. 
         [0014]    The VLSI layouts presented are applicable to generalized multi-stage networks V(N 1 , N 2 , d, s), generalized folded multi-stage networks V fold (N 1 , N 2 , d, s), generalized butterfly fat tree networks V bft (N 1 , N 2 , d, s), generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s), generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s), generalized multi-link butterfly fat tree networks V mlink-bft (N 1 , N 2 , d, s), and generalized hypercube networks V hcube (N 1 , N 2 , d, s) for s=1, 2, 3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel &amp; distributed computing, and reconfigurable computing. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0015]      FIG. 1A  is a diagram  100 A of an exemplary symmetrical multi-link multi-stage network V fold-mlink (N, d, s) having inverse Benes connection topology of nine stages with N=32, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0016]      FIG. 1B  is a diagram  100 B of the equivalent symmetrical folded multi-link multi-stage network V fold-mlink (N, d, s) of the network  100 A shown in  FIG. 1A , having inverse Benes connection topology of five stages with N=32, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0017]      FIG. 1C  is a diagram  100 C layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links belonging with in each block only. 
           [0018]      FIG. 1D  is a diagram  100 D layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links ML( 1 ,i) for i=[1, 64] and ML( 8 ,i) for i=[1,64]. 
           [0019]      FIG. 1E  is a diagram  100 E layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links ML( 2 ,i) for i=[1, 64] and ML( 7 ,i) for i=[1,64]. 
           [0020]      FIG. 1F  is a diagram  100 F layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links ML( 3 ,i) for i=[1, 64] and ML( 6 ,i) for i=[1,64]. 
           [0021]      FIG. 1G  is a diagram  100 G layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links ML( 4 ,i) for i=[1, 64] and ML( 5 ,i) for i=[1,64]. 
           [0022]      FIG. 1H  is a diagram  100 H layout of a network V fold-mlink (N, d, s) where N=128, d=2, and s=2, in one embodiment, illustrating the connection links belonging with in each block only. 
           [0023]      FIG. 11  is a diagram  100 I detailed connections of BLOCK  1 _ 2  in the network layout  100 C in one embodiment, illustrating the connection links going in and coming out when the layout  100 C is implementing V(N, d, s) or V fold (N, d, s). 
           [0024]      FIG. 1J  is a diagram  100 J detailed connections of BLOCK  1 _ 2  in the network layout  100 C in one embodiment, illustrating the connection links going in and coming out when the layout  100 C is implementing V(N, d, s) or V fold (N, d, s). 
           [0025]      FIG. 1K  is a diagram  100 K detailed connections of BLOCK  1 _ 2  in the network layout  100 C in one embodiment, illustrating the connection links going in and coming out when the layout  100 C is implementing V(N, d, s) or V fold (N, d, s). 
           [0026]    FIG.  1 K 1  is a diagram  100 M 1  detailed connections of BLOCK  1 _ 2  in the network layout  100 C in one embodiment, illustrating the connection links going in and coming out when the layout  100 C is implementing V(N, d, s) or V fold (N, d, s) for s=1. 
           [0027]      FIG. 1L  is a diagram  100 L detailed connections of BLOCK  1 _ 2  in the network layout  100 C in one embodiment, illustrating the connection links going in and coming out when the layout  100 C is implementing V(N, d, s) or V fold (N, d, s). 
           [0028]    FIG.  1 L 1  is a diagram  100 L 1  detailed connections of BLOCK  1 _ 2  in the network layout  100 C in one embodiment, illustrating the connection links going in and coming out when the layout  100 C is implementing V(N, d, s) or V fold (N, d, s) for s=1. 
           [0029]    FIG.  2 A 1  is a diagram  200 A 1  of an exemplary symmetrical multi-link multi-stage network V fold-mlink (N, d, s) having inverse Benes connection topology of one stage with N=2, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG.  2 A 2  is a diagram  200 A 2  of the equivalent symmetrical folded multi-link multi-stage network V fold-mlink (N, d, s) of the network  200 A 1  shown in FIG.  2 A 1 , having inverse Benes connection topology of one stage with N=2, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG.  2 A 3  is a diagram  200 A 3  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 A 2 , in one embodiment, illustrating all the connection links. 
           [0030]    FIG.  2 B 1  is a diagram  200 B 1  of an exemplary symmetrical multi-link multi-stage network V fold-mlink (N, d, s) having inverse Benes connection topology of one stage with N=4, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG.  2 B 2  is a diagram  200 B 2  of the equivalent symmetrical folded multi-link multi-stage network V fold-mlink (N, d, s) of the network  200 B 1  shown in FIG.  2 B 1 , having inverse Benes connection topology of one stage with N=4, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG.  2 B 3  is a diagram  200 B 3  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 B 2 , in one embodiment, illustrating the connection links belonging with in each block only. FIG.  2 B 4  is a diagram  200 B 4  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 B 2 , in one embodiment, illustrating the connection links ML( 1 ,i) for i=[1, 8] and ML( 2 ,i) for i=[1,8]. 
           [0031]    FIG.  2 C 11  is a diagram  200 C 11  of an exemplary symmetrical multi-link multi-stage network V fold-mlink (N, d, s) having inverse Benes connection topology of one stage with N=8, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG.  2 C 12  is a diagram  200 C 12  of the equivalent symmetrical folded multi-link multi-stage network V fold-mlink (N, d, s) of the network  200 C 11  shown in FIG.  2 C 11 , having inverse Benes connection topology of one stage with N=8, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0032]    FIG.  2 C 21  is a diagram  200 C 21  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 C 12 , in one embodiment, illustrating the connection links belonging with in each block only. FIG.  2 C 22  is a diagram  200 C 22  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 C 12 , in one embodiment, illustrating the connection links ML( 1 ,i) for i=[1, 16] and ML( 4 ,i) for i=[1,16]. FIG.  2 C 23  is a diagram  200 C 23  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 C 12 , in one embodiment, illustrating the connection links ML( 2 ,i) for i=[1, 16] and ML( 3 ,i) for i=[1,16]. 
           [0033]    FIG.  2 D 1  is a diagram  200 D 1  of an exemplary symmetrical multi-link multi-stage network V fold-mlink (N, d, s) having inverse Benes connection topology of one stage with N=16, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0034]    FIG.  2 D 2  is a diagram  200 D 2  of the equivalent symmetrical folded multi-link multi-stage network V fold-mlink (N, d, s) of the network  200 D 1  shown in FIG.  2 D 1 , having inverse Benes connection topology of one stage with N=16, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0035]    FIG.  2 D 3  is a diagram  200 D 3  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 D 2 , in one embodiment, illustrating the connection links belonging with in each block only. 
           [0036]    FIG.  2 D 4  is a diagram  200 D 4  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 D 2 , in one embodiment, illustrating the connection links ML( 1 ,i) for i=[1, 32] and ML( 6 ,i) for i=[1,32]. 
           [0037]    FIG.  2 D 5  is a diagram  200 D 5  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 D 2 , in one embodiment, illustrating the connection links ML( 2 ,i) for i=[1, 32] and ML( 5 ,i) for i=[1,32]. 
           [0038]    FIG.  2 D 6  is a diagram  200 D 6  layout of the network V fold-mlink (N, d, s) shown in FIG.  2 D 2 , in one embodiment, illustrating the connection links ML( 3 ,i) for i=[1, 32] and ML( 4 ,i) for i=[1,32]. 
           [0039]      FIG. 3A  is a diagram  300 A of an exemplary symmetrical multi-link multi-stage network V hcube (N, d, s) having inverse Benes connection topology of nine stages with N=32, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0040]      FIG. 3B  is a diagram  300 B of the equivalent symmetrical folded multi-link multi-stage network V hcube (N, d, s) of the network  300 A shown in  FIG. 3A , having inverse Benes connection topology of five stages with N=32, d=2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. 
           [0041]      FIG. 3C  is a diagram  300 C layout of the network V hcube (N, d, s) shown in  FIG. 3B , in one embodiment, illustrating the connection links belonging with in each block only. 
           [0042]      FIG. 3D  is a diagram  100 D layout of the network V hcube (N, d, s) shown in  FIG. 3B , in one embodiment, illustrating the connection links ML( 1 ,i) for i=[1, 64] and ML( 8 ,i) for i=[1,64]. 
           [0043]      FIG. 3E  is a diagram  300 E layout of the network V hcube (N, d, s) shown in  FIG. 3B , in one embodiment, illustrating the connection links ML( 2 ,i) for i=[1, 64] and ML( 7 ,i) for i=[1,64]. 
           [0044]      FIG. 3F  is a diagram  300 F layout of the network V hcube (N, d, s) shown in  FIG. 3B , in one embodiment, illustrating the connection links ML( 3 ,i) for i=[1, 64] and ML( 6 ,i) for i=[1,64]. 
           [0045]      FIG. 3G  is a diagram  300 G layout of the network V hcube (N, d, s) shown in  FIG. 3B , in one embodiment, illustrating the connection links ML( 4 ,i) for i=[1, 64] and ML( 5 ,i) for i=[1,64]. 
           [0046]      FIG. 3H  is a diagram  300 H layout of a network V hcube (N, d, s) where N=128, d=2, and s=2, in one embodiment, illustrating the connection links belonging with in each block only. 
           [0047]      FIG. 4A  is a diagram  400 A layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links belonging with in each block only. 
           [0048]      FIG. 4B  is a diagram  400 B layout of the network V fold- mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links ML( 1 ,i) for i=[1, 64] and ML( 8 ,i) for i=[1,64]. 
           [0049]      FIG. 4C  is a diagram  400 C layout of the network V fold-mlink (N, d, s) shown in  FIG. 4C , in one embodiment, illustrating the connection links ML( 2 ,i) for i=[1, 64] and ML( 7 ,i) for i=[1,64]. 
           [0050]      FIG. 4D  is a diagram  400 D layout of the network V fold-mlink (N, d, s) shown in  FIG. 4D , in one embodiment, illustrating the connection links ML( 3 ,i) for i=[1, 64] and ML( 6 ,i) for i=[1,64]. 
           [0051]      FIG. 4E  is a diagram  400 E layout of the network V fold-mlink (N, d, s) shown in  FIG. 4E , in one embodiment, illustrating the connection links ML( 4 ,i) for i=[1, 64] and ML( 5 ,i) for i=[1,64]. 
           [0052]    FIG.  4 C 1  is a diagram  400 C 1  layout of the network V fold-mlink (N, d, s) shown in  FIG. 1B , in one embodiment, illustrating the connection links belonging with in each block only. 
           [0053]    FIG.  5 A 1  is a diagram  500 A 1  of an exemplary prior art implementation of a two by two switch; FIG.  5 A 2  is a diagram  500 A 2  for programmable integrated circuit prior art implementation of the diagram  500 A 1  of FIG.  5 A 1 ; FIG.  5 A 3  is a diagram  500 A 3  for one-time programmable integrated circuit prior art implementation of the diagram  500 A 1  of FIG.  5 A 1 ; FIG.  5 A 4  is a diagram  500 A 4  for integrated circuit placement and route implementation of the diagram  500 A 1  of FIG.  5 A 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0054]    The present invention is concerned with the VLSI layouts of arbitrarily large switching networks for broadcast, unicast and multicast connections. Particularly switching networks considered in the current invention include: generalized multi-stage networks V(N 1 , N 2 , d, s), generalized folded multi-stage networks V fold (N 1 , N 2 , d, s), generalized butterfly fat tree networks V bft (N 1 , N 2 , d, s), generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s), generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s), generalized multi-link butterfly fat tree networks V mlink-bft (N 1 , N 2 , d, s), and generalized hypercube networks V hcube (N 1 , N 2 , d, s) for s=1, 2, 3 or any number in general. 
         [0055]    Efficient VLSI layout of networks on a semiconductor chip are very important and greatly influence many important design parameters such as the area taken up by the network on the chip, total number of wires, length of the wires, latency of the signals, capacitance and hence the maximum clock speed of operation. Some networks may not even be implemented practically on a chip due to the lack of efficient layouts. The different varieties of multi-stage networks described above have not been implemented previously on the semiconductor chips efficiently. For example in Field Programmable Gate Array (FPGA) designs, multi-stage networks described in the current invention have not been successfully implemented primarily due to the lack of efficient VLSI layouts. Current commercial FPGA products such as Xilinx Vertex, Altera&#39;s Stratix implement island-style architecture using mesh and segmented mesh routing interconnects using either full crossbars or sparse crossbars. These routing interconnects consume large silicon area for crosspoints, long wires, large signal propagation delay and hence consume lot of power. 
         [0056]    The current invention discloses the VLSI layouts of numerous types of multi-stage networks which are very efficient. Moreover they can be embedded on to mesh and segmented mesh routing interconnects of current commercial FPGA products. The VLSI layouts disclosed in the current invention are applicable to including the numerous generalized multi-stage networks disclosed in the following patent applications, filed concurrently: 
         [0057]    1) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized multi-stage networks V(N 1 , N 2 , d, s) with numerous connection topologies and the scheduling methods are described in detail in the PCT Application Serial No. PCT/US08/56064 that is incorporated by reference above. 
         [0058]    2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized butterfly fat tree networks V bft (N 1 , N 2 , d, s) with numerous connection topologies and the scheduling methods are described in detail in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. 
         [0059]    3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and strictly nonblocking for unicast for generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s) and generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s) with numerous connection topologies and the scheduling methods are described in detail in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. 
         [0060]    4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized multi-link butterfly fat tree networks V mlink-bft (N 1 , N 2 , d, s) with numerous connection topologies and the scheduling methods are described in detail in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. 
         [0061]    5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized folded multi-stage networks V fold (N 1 , N 2 , d, s) with numerous connection topologies and the scheduling methods are described in detail in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. 
         [0062]    6) Strictly nonblocking for arbitrary fan-out multicast for generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s) and generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s) with numerous connection topologies and the scheduling methods are described in detail in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. 
         [0063]    7) VLSI layouts of numerous types of multi-stage networks with locality exploitation are described in U.S. Provisional Patent Application Ser. No. 61/252,603 that is incorporated by reference above. 
         [0064]    8) VLSI layouts of numerous types of multistage pyramid networks are described in U.S. Provisional Patent Application Ser. No. 61/252,609 that is incorporated by reference above. 
         [0065]    In addition the layouts of the current invention are also applicable to generalized multi-stage pyramid networks V p (N 1 , N 2 , d, s), generalized folded multi-stage pyramid networks V fold-p (N 1 , N 2 , d, s), generalized butterfly fat pyramid networks V bfp (N 1 , N 2  d, s), generalized multi-link multi-stage pyramid networks V mlink-p (N 1 , N 2 , d, s), generalized folded multi-link multi-stage pyramid networks V fold-mlink-p (N 1 , N 2 , d, s), generalized multi-link butterfly fat pyramid networks V mlink-bfp (N 1 , N 2 , d, s), and generalized hypercube networks V hcube (N 1 , N 2 , d, s) for s=1, 2, 3 or any number in general. 
       Symmetric RNB Generalized Multi-Link Multi-Stage Network V mlink (N 1 , N 2 , d, s): 
       [0066]    Referring to diagram  100 A in  FIG. 1A , in one embodiment, an exemplary generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages of one hundred and forty four switches for satisfying communication requests, such as setting up a telephone call or a data call, or a connection between configurable logic blocks, between an input stage  110  and output stage  120  via middle stages  130 ,  140 ,  150 ,  160 ,  170 ,  180  and  190  is shown where input stage  110  consists of sixteen, two by four switches IS 1 -IS 16  and output stage  120  consists of sixteen, four by two switches OS 1 -OS 16 . And all the middle stages namely the middle stage  130  consists of sixteen, four by four switches MS( 1 , 1 )-MS( 1 , 16 ), middle stage  140  consists of sixteen, four by four switches MS( 2 , 1 )-MS( 2 , 16 ), middle stage  150  consists of sixteen, four by four switches MS( 3 , 1 )-MS( 3 , 16 ), middle stage  160  consists of sixteen, four by four switches MS( 4 , 1 )-MS( 4 , 16 ), middle stage  170  consists of sixteen, four by four switches MS( 5 , 1 )-MS( 5 , 16 ), middle stage  180  consists of sixteen, four by four switches MS( 6 , 1 )-MS( 6 , 16 ), and middle stage  190  consists of sixteen, four by four switches MS( 7 , 1 )-MS( 7 , 16 ). 
         [0067]    As disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above, such a network can be operated in rearrangeably non-blocking manner for arbitrary fan-out multicast connections and also can be operated in strictly non-blocking manner for unicast connections. 
         [0068]    In one embodiment of this network each of the input switches IS 1 -IS 4  and output switches OS 1 -OS 4  are crossbar switches. The number of switches of input stage  110  and of output stage  120  can be denoted in general with the variable N/d, where N is the total number of inlet links or outlet links. The number of middle switches in each middle stage is denoted by N/d. The size of each input switch IS 1 -IS 4  can be denoted in general with the notation d*2d and each output switch OS 1 -OS 4  can be denoted in general with the notation 2d*d. Likewise, the size of each switch in any of the middle stages can be denoted as 2d*2d. A switch as used herein can be either a crossbar switch, or a network of switches each of which in turn may be a crossbar switch or a network of switches. A symmetric multi-stage network can be represented with the notation V mlink (N, d, s), where N represents the total number of inlet links of all input switches (for example the links IL 1 -IL 32 ), d represents the inlet links of each input switch or outlet links of each output switch, and s is the ratio of number of outgoing links from each input switch to the inlet links of each input switch. 
         [0069]    Each of the N/d input switches IS 1 -IS 16  are connected to exactly d switches in middle stage  130  through two links each for a total of 2×d links (for example input switch IS 1  is connected to middle switch MS( 1 , 1 ) through the links ML( 1 , 1 ), ML( 1 , 2 ), and also connected to middle switch MS( 1 , 2 ) through the links ML( 1 , 3 ) and ML( 1 , 4 )). The middle links which connect switches in the same row in two successive middle stages are called hereinafter straight middle links; and the middle links which connect switches in different rows in two successive middle stages are called hereinafter cross middle links. For example, the middle links ML( 1 , 1 ) and ML( 1 , 2 ) connect input switch IS 1  and middle switch MS( 1 , 1 ), so middle links ML( 1 , 1 ) and ML( 1 , 2 ) are straight middle links; where as the middle links ML( 1 , 3 ) and ML( 1 , 4 ) connect input switch IS 1  and middle switch MS( 1 , 2 ), since input switch IS 1  and middle switch MS( 1 , 2 ) belong to two different rows in diagram  100 A of  FIG. 1A , middle links ML( 1 , 3 ) and ML( 1 , 4 ) are cross middle links 
         [0070]    Each of the N/d middle switches MS( 1 , 1 )-MS( 1 , 16 ) in the middle stage  130  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 1 , 1 ) and ML( 1 , 2 ) are connected to the middle switch MS( 1 , 1 ) from input switch IS 1 , and the links ML( 1 , 7 ) and ML( 1 , 8 ) are connected to the middle switch MS( 1 , 1 ) from input switch IS 2 ) and also are connected to exactly d switches in middle stage  140  through two links each for a total of 2×d links (for example the links ML( 2 , 1 ) and ML( 2 , 2 ) are connected from middle switch MS( 1 , 1 ) to middle switch MS( 2 , 1 ), and the links ML( 2 , 3 ) and ML( 2 , 4 ) are connected from middle switch MS( 1 , 1 ) to middle switch MS( 2 , 3 )). 
         [0071]    Each of the N/d middle switches MS( 2 , 1 )-MS( 2 , 16 ) in the middle stage  140  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 2 , 1 ) and ML( 2 , 2 ) are connected to the middle switch MS( 2 , 1 ) from input switch MS( 1 , 1 ), and the links ML( 1 , 11 ) and ML( 1 , 12 ) are connected to the middle switch MS( 2 , 1 ) from input switch MS( 1 , 3 )) and also are connected to exactly d switches in middle stage  150  through two links each for a total of 2×d links (for example the links ML( 3 , 1 ) and ML( 3 , 2 ) are connected from middle switch MS( 2 , 1 ) to middle switch MS( 3 , 1 ), and the links ML( 3 , 3 ) and ML( 3 , 4 ) are connected from middle switch MS( 2 , 1 ) to middle switch MS( 3 , 5 )). 
         [0072]    Each of the N/d middle switches MS( 3 , 1 )-MS( 3 , 16 ) in the middle stage  150  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 3 , 1 ) and ML( 3 , 2 ) are connected to the middle switch MS( 3 , 1 ) from input switch MS( 2 , 1 ), and the links ML( 2 , 19 ) and ML( 2 , 20 ) are connected to the middle switch MS( 3 , 1 ) from input switch MS( 2 , 5 )) and also are connected to exactly d switches in middle stage  160  through two links each for a total of 2×d links (for example the links ML( 4 , 1 ) and ML( 4 , 2 ) are connected from middle switch MS( 3 , 1 ) to middle switch MS( 4 , 1 ), and the links ML( 4 , 3 ) and ML( 4 , 4 ) are connected from middle switch MS( 3 , 1 ) to middle switch MS( 4 , 9 )). 
         [0073]    Each of the N/d middle switches MS( 4 , 1 )-MS( 4 , 16 ) in the middle stage  160  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 4 , 1 ) and ML( 4 , 2 ) are connected to the middle switch MS( 4 , 1 ) from input switch MS( 3 , 1 ), and the links ML( 4 , 35 ) and ML( 4 , 36 ) are connected to the middle switch MS( 4 , 1 ) from input switch MS( 3 , 9 )) and also are connected to exactly d switches in middle stage  170  through two links each for a total of 2×d links (for example the links ML( 5 , 1 ) and ML( 5 , 2 ) are connected from middle switch MS( 4 , 1 ) to middle switch MS( 5 , 1 ), and the links ML( 5 , 3 ) and ML( 5 , 4 ) are connected from middle switch MS( 4 , 1 ) to middle switch MS( 5 , 9 )). 
         [0074]    Each of the N/d middle switches MS( 5 , 1 )-MS( 5 , 16 ) in the middle stage  170  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 5 , 1 ) and ML( 5 , 2 ) are connected to the middle switch MS( 5 , 1 ) from input switch MS( 4 , 1 ), and the links ML( 5 , 35 ) and ML( 5 , 36 ) are connected to the middle switch MS( 5 , 1 ) from input switch MS( 4 , 9 )) and also are connected to exactly d switches in middle stage  180  through two links each for a total of 2×d links (for example the links ML( 6 , 1 ) and ML( 6 , 2 ) are connected from middle switch MS( 5 , 1 ) to middle switch MS( 6 , 1 ), and the links ML( 6 , 3 ) and ML( 6 , 4 ) are connected from middle switch MS( 5 , 1 ) to middle switch MS( 6 , 5 )). 
         [0075]    Each of the N/d middle switches MS( 6 , 1 )-MS( 6 , 16 ) in the middle stage  180  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 6 , 1 ) and ML( 6 , 2 ) are connected to the middle switch MS( 6 , 1 ) from input switch MS( 5 , 1 ), and the links ML( 6 , 19 ) and ML( 6 , 20 ) are connected to the middle switch MS( 6 , 1 ) from input switch MS( 5 , 5 )) and also are connected to exactly d switches in middle stage  190  through two links each for a total of 2×d links (for example the links ML( 7 , 1 ) and ML( 7 , 2 ) are connected from middle switch MS( 6 , 1 ) to middle switch MS( 7 , 1 ), and the links ML( 7 , 3 ) and ML( 7 , 4 ) are connected from middle switch MS( 6 , 1 ) to middle switch MS( 7 , 3 )). 
         [0076]    Each of the N/d middle switches MS( 7 , 1 )-MS( 7 , 16 ) in the middle stage  190  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 7 , 1 ) and ML( 7 , 2 ) are connected to the middle switch MS( 7 , 1 ) from input switch MS( 6 , 1 ), and the links ML( 7 , 11 ) and ML( 7 , 12 ) are connected to the middle switch MS( 7 , 1 ) from input switch MS( 6 , 3 )) and also are connected to exactly d switches in middle stage  120  through two links each for a total of 2×d links (for example the links ML( 8 , 1 ) and ML( 8 , 2 ) are connected from middle switch MS( 7 , 1 ) to middle switch MS( 8 , 1 ), and the links ML( 8 , 3 ) and ML( 8 , 4 ) are connected from middle switch MS( 7 , 1 ) to middle switch OS 2 ). 
         [0077]    Each of the N/d middle switches OS 1 -OS 16  in the middle stage  120  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 8 , 1 ) and ML( 8 , 2 ) are connected to the output switch OS 1  from input switch MS( 7 , 1 ), and the links ML( 8 , 7 ) and ML( 7 , 8 ) are connected to the output switch OS 1  from input switch MS( 7 , 2 )). 
         [0078]    Finally the connection topology of the network  100 A shown in  FIG. 1A  is known to be back to back inverse Benes connection topology. 
         [0079]    Referring to diagram  100 B in  FIG. 1B , is a folded version of the multi-link multi-stage network  100 A shown in  FIG. 1A . The network  100 B in  FIG. 1B  shows input stage  110  and output stage  120  are placed together. That is input switch IS 1  and output switch OS 1  are placed together, input switch IS 2  and output switch OS 2  are placed together, and similarly input switch IS 16  and output switch OS 16  are placed together. All the right going middle links (hereinafter “forward connecting links”) {i.e., inlet links IL 1 -IL 32  and middle links ML( 1 , 1 )-ML( 1 , 64 )} correspond to input switches IS 1 -IS 16 , and all the left going middle links (hereinafter “backward connecting links”) {i.e., middle links ML( 8 , 1 )-ML( 8 , 64 ) and outlet links OL 1 -OL 32 } correspond to output switches OS 1 -OS 16 . 
         [0080]    Middle stage  130  and middle stage  190  are placed together. That is middle switches MS( 1 , 1 ) and MS( 7 , 1 ) are placed together, middle switches MS( 1 , 2 ) and MS( 7 , 2 ) are placed together, and similarly middle switches MS( 1 , 16 ) and MS( 7 , 16 ) are placed together. All the right going middle links {i.e., middle links ML( 1 , 1 )-ML( 1 , 64 ) and middle links ML( 2 , 1 )-ML( 2 , 64 )} correspond to middle switches MS( 1 , 1 )-MS( 1 , 16 ), and all the left going middle links {i.e., middle links ML( 7 , 1 )-ML( 7 , 64 ) and middle links ML( 8 , 1 ) and ML( 8 , 64 )} correspond to middle switches MS( 7 , 1 )-MS( 7 , 16 ). 
         [0081]    Middle stage  140  and middle stage  180  are placed together. That is middle switches MS( 2 , 1 ) and MS( 6 , 1 ) are placed together, middle switches MS( 2 , 2 ) and MS( 6 , 2 ) are placed together, and similarly middle switches MS( 2 , 16 ) and MS( 6 , 16 ) are placed together. All the right going middle links {i.e., middle links ML( 2 , 1 )-ML( 2 , 64 ) and middle links ML( 3 , 1 )-ML( 3 , 64 )} correspond to middle switches MS( 2 , 1 )-MS( 2 , 16 ), and all the left going middle links {i.e., middle links ML( 6 , 1 )-ML( 6 , 64 ) and middle links ML( 7 , 1 ) and ML( 7 , 64 )} correspond to middle switches MS( 6 , 1 )-MS( 6 , 16 ). 
         [0082]    Middle stage  150  and middle stage  170  are placed together. That is middle switches MS( 3 , 1 ) and MS( 5 , 1 ) are placed together, middle switches MS( 3 , 2 ) and MS( 5 , 2 ) are placed together, and similarly middle switches MS( 3 , 16 ) and MS( 5 , 16 ) are placed together. All the right going middle links {i.e., middle links ML( 3 , 1 )-ML( 3 , 64 ) and middle links ML( 4 , 1 )-ML( 4 , 64 )} correspond to middle switches MS( 3 , 1 )-MS( 3 , 16 ), and all the left going middle links {i.e., middle links ML( 5 , 1 )-ML( 5 , 64 ) and middle links ML( 6 , 1 ) and ML( 6 , 64 )} correspond to middle switches MS( 5 , 1 )-MS( 5 , 16 ). 
         [0083]    Middle stage  160  is placed alone. All the right going middle links are the middle links ML( 4 , 1 )-ML( 4 , 64 ) and all the left going middle links are middle links ML( 5 , 1 )-ML( 5 , 64 ). 
         [0084]    In one embodiment, in the network  100 B of  FIG. 1B , the switches that are placed together are implemented as separate switches then the network  100 B is the generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a two by four switch and a four by two switch. For example the switch input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  is implemented as two by four switch with the inlet links IL 1  and IL 2  being the inputs of the input switch IS 1  and middle links ML( 1 , 1 )-ML( 1 , 4 ) being the outputs of the input switch IS 1 ; and output switch OS 1  is implemented as four by two switch with the middle links ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs of the output switch OS 1  and outlet links OL 1 -OL 2  being the outputs of the output switch OS 1 . Similarly in this embodiment of network  100 B all the switches that are placed together in each middle stage are implemented as separate switches. 
       Hypercube Topology Layout Schemes: 
       [0085]    Referring to layout  100 C of  FIG. 1C , in one embodiment, there are sixteen blocks namely Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , Block  7 _ 8 , Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14 , Block  15 _ 16 , Block  17 _ 18 , Block  19 _ 20 , Block  21 _ 22 , Block  23 _ 24 , Block  25 _ 26 , Block  27 _ 28 , Block  29 _ 30 , and Block  31 _ 32 . Each block implements all the switches in one row of the network  100 B of  FIG. 1B , one of the key aspects of the current invention. For example Block  1 _ 2  implements the input switch IS 1 , output Switch OS 1 , middle switch MS( 1 , 1 ), middle switch MS( 7 , 1 ), middle switch MS( 2 , 1 ), middle switch MS( 6 , 1 ), middle switch MS( 3 , 1 ), middle switch MS( 5 , 1 ), and middle switch MS( 4 , 1 ). For the simplification of illustration, Input switch IS 1  and output switch OS 1  together are denoted as switch  1 ; Middle switch MS( 1 , 1 ) and middle switch MS( 7 , 1 ) together are denoted by switch  2 ; Middle switch MS( 2 , 1 ) and middle switch MS( 6 , 1 ) together are denoted by switch  3 ; Middle switch MS( 3 , 1 ) and middle switch MS( 5 , 1 ) together are denoted by switch  4 ; Middle switch MS( 4 , 1 ) is denoted by switch  5 . 
         [0086]    All the straight middle links are illustrated in layout  100 C of  FIG. 1C . For example in Block  1 _ 2 , inlet links IL 1 -IL 2 , outlet links OL 1 -OL 2 , middle link ML( 1 , 1 ), middle link ML( 1 , 2 ), middle link ML( 8 , 1 ), middle link ML( 8 , 2 ), middle link ML( 2 , 1 ), middle link ML( 2 , 2 ), middle link ML( 7 , 1 ), middle link ML( 7 , 2 ), middle link ML( 3 , 1 ), middle link ML( 3 , 2 ), middle link ML( 6 , 1 ), middle link ML( 6 , 2 ), middle link ML( 4 , 1 ), middle link ML( 4 , 2 ), middle link ML( 5 , 1 ) and middle link ML( 5 , 2 ) are illustrated in layout  100 C of  FIG. 1C . 
         [0087]    Even though it is not illustrated in layout  100 C of  FIG. 1C , in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit (hereinafter “sub-integrated circuit block”) depending on the applications in different embodiments. There are four quadrants in the layout  100 C of  FIG. 1C  namely top-left, bottom-left, top-right and bottom-right quadrants. Top-left quadrant implements Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , and Block  7 _ 8 . Bottom-left quadrant implements Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14 , and Block  15 _ 16 . Top-right quadrant implements Block  17 _ 18 , Block  19 _ 20 , Block  21 _ 22 , and Block  23 _ 24 . Bottom-right quadrant implements Block  25 _ 26 , Block  27 _ 28 , Block  29 _ 30 , and Block  31 _ 32 . There are two halves in layout  100 C of  FIG. 1C  namely left-half and right-half. Left-half consists of top-left and bottom-left quadrants. Right-half consists of top-right and bottom-right quadrants. 
         [0088]    Recursively in each quadrant there are four sub-quadrants. For example in top-left quadrant there are four sub-quadrants namely top-left sub-quadrant, bottom-left sub-quadrant, top-right sub-quadrant and bottom-right sub-quadrant. Top-left sub-quadrant of top-left quadrant implements Block  1 _ 2 . Bottom-left sub-quadrant of top-left quadrant implements Block  3 _ 4 . Top-right sub-quadrant of top-left quadrant implements Block  5 _ 6 . Finally bottom-right sub-quadrant of top-left quadrant implements Block  7 _ 8 . Similarly there are two sub-halves in each quadrant. For example in top-left quadrant there are two sub-halves namely left-sub-half and right-sub-half. Left-sub-half of top-left quadrant implements Block  1 _ 2  and Block  3 _ 4 . Right-sub-half of top-left quadrant implements Block  5 _ 6  and Block  7 _ 8  Finally applicant notes that in each quadrant or half the blocks are arranged as a general binary hypercube. Recursively in larger multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 &gt;32, the layout in this embodiment in accordance with the current invention, will be such that the super-quadrants will also be arranged in d-ary hypercube manner. (In the embodiment of the layout  100 C of  FIG. 1C , it is binary hypercube manner since d=2, in the network V fold-mlink (N 1 , N 2 , d, s)  100 B of  FIG. 1B ). 
         [0089]    Layout  100 D of  FIG. 1D  illustrates the inter-block links between switches  1  and  2  of each block. For example middle links ML( 1 , 3 ), ML( 1 , 4 ), ML( 8 , 7 ), and ML( 8 , 8 ) are connected between switch  1  of Block  1 _ 2  and switch  2  of Block  3 _ 4 . Similarly middle links ML( 1 , 7 ), ML( 1 , 8 ), ML( 8 , 3 ), and ML( 8 , 4 ) are connected between switch  2  of Block  1 _ 2  and switch  1  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  100 D of  FIG. 1D  can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 1 , 4 ) and ML( 8 , 8 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 1 , 4 ) and ML( 8 , 8 ) are implemented as a time division multiplexed single track). 
         [0090]    Layout  100 E of  FIG. 1E  illustrates the inter-block links between switches  2  and  3  of each block. For example middle links ML( 2 , 3 ), ML( 2 , 4 ), ML( 7 , 11 ), and ML( 7 , 12 ) are connected between switch  2  of Block  1 _ 2  and switch  3  of Block  3 _ 4 . Similarly middle links ML( 2 , 11 ), ML( 2 , 12 ), ML( 7 , 3 ), and ML( 7 , 4 ) are connected between switch  3  of Block  1 _ 2  and switch  2  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  100 E of  FIG. 1E  can be implemented as horizontal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 2 , 12 ) and ML( 7 , 4 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 2 , 12 ) and ML( 7 , 4 ) are implemented as a time division multiplexed single track). 
         [0091]    Layout  100 F of  FIG. 1F  illustrates the inter-block links between switches  3  and  4  of each block. For example middle links ML( 3 , 3 ), ML( 3 , 4 ), ML( 6 , 19 ), and ML( 6 , 20 ) are connected between switch  3  of Block  1 _ 2  and switch  4  of Block  3 _ 4 . Similarly middle links ML( 3 , 19 ), ML( 3 , 20 ), ML( 6 , 3 ), and ML( 6 , 4 ) are connected between switch  4  of Block  1 _ 2  and switch  3  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  100 F of  FIG. 1F  can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 3 , 4 ) and ML( 6 , 20 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 3 , 4 ) and ML( 6 , 20 ) are implemented as a time division multiplexed single track). 
         [0092]    Layout  100 G of  FIG. 1G  illustrates the inter-block links between switches  4  and  5  of each block. For example middle links ML( 4 , 3 ), ML( 4 , 4 ), ML( 5 , 35 ), and ML( 5 , 36 ) are connected between switch  4  of Block  1 _ 2  and switch  5  of Block  3 _ 4 . Similarly middle links ML( 4 , 35 ), ML( 4 , 36 ), ML( 5 , 3 ), and ML( 5 , 4 ) are connected between switch  5  of Block  1 _ 2  and switch  4  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  100 G of  FIG. 1G  can be implemented as horizontal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 4 , 4 ) and ML( 5 , 36 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 4 , 4 ) and ML( 5 , 36 ) are implemented as a time division multiplexed single track). 
         [0093]    The complete layout for the network  100 B of  FIG. 1B  is given by combining the links in layout diagrams of  100 C,  100 D,  100 E,  100 F, and  100 G. Applicant notes that in the layout  100 C of  FIG. 1C , the inter-block links between switch  1  and switch  2  of corresponding blocks are vertical tracks as shown in layout  100 D of  FIG. 1D ; the inter-block links between switch  2  and switch  3  of corresponding blocks are horizontal tracks as shown in layout  100 E of  FIG. 1E ; the inter-block links between switch  3  and switch  4  of corresponding blocks are vertical tracks as shown in layout  100 F of  FIG. 1F ; and finally the inter-block links between switch  4  and switch  5  of corresponding blocks are horizontal tracks as shown in layout  100 G of  FIG. 1G . The pattern is alternate vertical tracks and horizontal tracks. It continues recursively for larger networks of N&gt;32 as will be illustrated later. 
         [0094]    Some of the key aspects of the current invention are discussed. 1) All the switches in one row of the multi-stage network  100 B are implemented in a single block. 2) The blocks are placed in such a way that all the inter-block links are either horizontal tracks or vertical tracks; 3) Since all the inter-block links are either horizontal or vertical tracks, all the inter-block links can be mapped on to island-style architectures in current commercial FPGA&#39;s; 4) The length of the longest wire is about half of the width (or length) of the complete layout (For example middle link ML( 4 , 4 ) is about half the width of the complete layout). 
         [0095]    In accordance with the current invention, the layout  100 C in  FIG. 1C  can be recursively extended for any arbitrarily large generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) the sub-quadrants, quadrants, and super-quadrants are arranged in d-ary hypercube manner and also the inter-blocks are accordingly connected in d-ary hypercube topology. Even though all the embodiments in the current invention are illustrated for N 1 =N 2 , the embodiments can be extended for N 1 ≠N 2 . Referring to layout  100 H of  FIG. 1H , illustrates the extension of layout  100 C for the network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =128; d=2; and s=2. There are four super-quadrants in layout  100 H namely top-left super-quadrant, bottom-left super-quadrant, top-right super-quadrant, bottom-right super-quadrant. Total number of blocks in the layout  100 H is sixty four. Top-left super-quadrant implements the blocks from block  1 _ 2  to block  31 _ 32 . Each block in all the super-quadrants has two more switches namely switch  6  and switch  7  in addition to the switches [ 1 - 5 ] illustrated in layout  100 C of  FIG. 1C . The inter-block link connection topology is the exactly the same between the switches  1  and  2 ; switches  2  and  3 ; switches  3  and  4 ; switches  4  and  5  as it is shown in the layouts of  FIG. 1D ,  FIG. 1E ,  FIG. 1F , and  FIG. 1G  respectively. 
         [0096]    Bottom-left super-quadrant implements the blocks from block  33 _ 34  to block  63 _ 64 . Top-right super-quadrant implements the blocks from block  65 _ 66  to block  95 _ 96 . And bottom-right super-quadrant implements the blocks from block  97 _ 98  to block  127 _ 128 . In all these three super-quadrants also, the inter-block link connection topology is the exactly the same between the switches  1  and  2 ; switches  2  and  3 ; switches  3  and  4 ; switches  4  and  5  as that of the top-left super-quadrant. 
         [0097]    Recursively in accordance with the current invention, the inter-block links connecting the switch  5  and switch  6  will be vertical tracks between the corresponding switches of top-left super-quadrant and bottom-left super-quadrant. And similarly the inter-block links connecting the switch  5  and switch  6  will be vertical tracks between the corresponding switches of top-right super-quadrant and bottom-right super-quadrant. The inter-block links connecting the switch  6  and switch  7  will be horizontal tracks between the corresponding switches of top-left super-quadrant and top-right super-quadrant. And similarly the inter-block links connecting the switch  6  and switch  7  will be horizontal tracks between the corresponding switches of bottom-left super-quadrant and bottom-right super-quadrant. 
         [0098]    Referring to diagram  100 I of  FIG. 1I  illustrates a high-level implementation of Block  1 _ 2  (Each of the other blocks have similar implementation) of the layout  100 C of  FIG. 1C  which represents a generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2. Block  1 _ 2  in  100 I illustrates both the intra-block and inter-block links connected to Block  1 _ 2 . The layout diagram  100 I corresponds to the embodiment where the switches that are placed together are implemented as separate switches in the network  100 B of  FIG. 1B . As noted before then the network  100 B is the generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. 
         [0099]    That is the switches that are placed together in Block  1 _ 2  as shown in  FIG. 1I  are namely input switch IS 1  and output switch OS 1  belonging to switch  1 , illustrated by dotted lines, (as noted before switch  1  is for illustration purposes only, in practice the switches implemented are input switch IS 1  and output switch OS 1 ); middle switch MS( 1 , 1 ) and middle switch MS( 7 , 1 ) belonging to switch  2 ; middle switch MS( 2 , 1 ) and middle switch MS( 6 , 1 ) belonging to switch  3 ; middle switch MS( 3 , 1 ) and middle switch MS( 5 , 1 ) belonging to switch  4 ; And middle switch MS( 4 , 1 ) belonging to switch  5 . 
         [0100]    Input switch IS 1  is implemented as two by four switch with the inlet links IL 1  and IL 2  being the inputs of the input switch IS 1  and middle links ML( 1 , 1 )-ML( 1 , 4 ) being the outputs of the input switch IS 1 ; and output switch OS 1  is implemented as four by two switch with the middle links ML( 8 , 1 )-ML( 8 , 4 ) being the inputs of the output switch OS 1  and outlet links OL 1 -OL 2  being the outputs of the output switch OS 1 . 
         [0101]    Middle switch MS( 1 , 1 ) is implemented as four by four switch with the middle links ML( 1 , 1 ), ML( 1 , 2 ), ML( 1 , 7 ) and ML( 1 , 8 ) being the inputs and middle links ML( 2 , 1 )-ML( 2 , 4 ) being the outputs; and middle switch MS( 7 , 1 ) is implemented as four by four switch with the middle links ML( 7 , 1 ), ML( 7 , 2 ), ML( 7 , 11 ) and ML( 7 , 12 ) being the inputs and middle links ML( 8 , 1 )-ML( 8 , 4 ) being the outputs. Similarly all the other middle switches are also implemented as four by four switches as illustrated in  100 I of  FIG. 1I . 
         [0102]    Now the VLSI layouts of generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 &lt;32; d=2; s=2 and its corresponding version of folded generalized multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 &lt;32; d=2; s=2 are discussed. Referring to diagram  200 A 1  of FIG.  2 A 1  is generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 =2; d=2. Diagram  200 A 2  of FIG.  2 A 2  illustrates the corresponding folded generalized multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =2; d=2, version of the diagram  200 A 1  of FIG.  2 A 1 . Layout  200 A 3  of FIG.  2 A 3  illustrates the VLSI layout of the network  200 A 2  of FIG.  2 A 2 . There is only one block i.e., Block  1 _ 2  comprising switch  1 . Just like in the layout  100 C of  FIG. 1C , switch  1  consists of input switch IS 1  and output switch OS 1 . 
         [0103]    Referring to diagram  200 B 1  of FIG.  2 B 1  is generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 =4; d=2; s=2. Diagram  200 B 2  of FIG.  2 B 2  illustrates the corresponding folded generalized multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =4; d=2; s=2, version of the diagram  200 B 1  of FIG.  2 B 1 . Layout  200 B 3  of FIG.  2 B 3  illustrates the VLSI layout of the network  200 B 2  of FIG.  2 B 2 . There are two blocks i.e., Block  1 _ 2  and Block  3 _ 4  each comprising switch  1  and switch  2 . Switch  1  in each block consists of the corresponding input switch and output switch. For example switch  1  in Block  1 _ 2  consists of input switch IS 1  and output switch OS 1 . Similarly switch  2  in Block  1 _ 2  consists of middle switch ( 1 , 1 ). Layout  200 B 4  of FIG.  2 B 4  illustrates the inter-block links of the VLSI layout diagram  200 B 3  of FIG.  2 B 3 . For example middle links ML( 1 , 4 ) and ML( 2 , 8 ). It must be noted that all the inter-block links are vertical tracks in this layout. (Alternatively all the inter-blocks can also be implemented as horizontal tracks). 
         [0104]    Referring to diagram  200 C 11  of FIG.  2 C 11  is generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 =8; d=2; s=2. Diagram  200 C 12  of FIG.  2 C 12  illustrates the corresponding folded generalized multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =8; d=2; s=2, version of the diagram  200 C 11  of FIG.  2 C 11 . Layout  200 C 21  of FIG.  2 C 21  illustrates the VLSI layout of the network  200 C 12  of FIG.  2 C 12 . There are four blocks i.e., Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , and Block  7 _ 8  each comprising switch  1 , switch  2  and switch  3 . For example switch  1  in Block  1 _ 2  consists of input switch IS 1  and output switch OS 1 ; Switch  2  in Block  1 _ 2  consists of MS( 1 , 1 ) and MS( 3 , 1 ). Switch  3  in Block  1 _ 2  consists of MS( 2 , 1 ). 
         [0105]    Layout  200 C 22  of FIG.  2 C 22  illustrates the inter-block links between the switch  1  and switch  2  of the VLSI layout diagram  200 C 21  of FIG.  2 C 21 . For example middle links ML( 1 , 4 ) and ML( 4 , 8 ) are connected between Block  1 _ 2  and Block  3 _ 4 . It must be noted that all the inter-block links between switch  1  and switch  2  of all blocks are vertical tracks in this layout. Layout  200 C 23  of FIG.  2 C 23  illustrates the inter-block links between the switch  2  and switch  3  of the VLSI layout diagram  200 C 21  of FIG.  2 C 21 . For example middle links ML( 2 , 12 ) and ML( 3 , 4 ) are connected between Block  1 _ 2  and Block  5 _ 6 . It must be noted that all the inter-block links between switch  2  and switch  3  of all blocks are horizontal tracks in this layout 
         [0106]    Referring to diagram  200 D 1  of FIG.  2 D 1  is generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 =16; d=2; s=2. Diagram  200 D 2  of FIG.  2 D 2  illustrates the corresponding folded generalized multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =16; d=2; s=2, version of the diagram  200 D 1  of FIG.  2 D 1 . Layout  200 D 3  of FIG.  2 D 3  illustrates the VLSI layout of the network  200 D 2  of FIG.  2 D 2 . There are eight blocks i.e., Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , Block  7 _ 8 , Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14  and Block  15 _ 16  each comprising switch  1 , switch  2 , switch  3  and switch  4 . For example switch  1  in Block  1 _ 2  consists of input switch IS 1  and output switch OS 1 ; Switch  2  in Block  1 _ 2  consists of MS( 1 , 1 ) and MS( 5 , 1 ). Switch  3  in Block  1 _ 2  consists of MS( 2 , 1 ) and MS( 4 , 1 ), and switch  4  in Block  1 _ 2  consists of MS( 3 , 1 ). 
         [0107]    Layout  200 D 4  of FIG.  2 D 4  illustrates the inter-block links between the switch  1  and switch  2  of the VLSI layout diagram  200 D 3  of FIG.  2 D 3 . For example middle links ML( 1 , 4 ) and ML( 6 , 8 ) are connected between Block  1 _ 2  and Block  3 _ 4 . It must be noted that all the inter-block links between switch  1  and switch  2  of all blocks are vertical tracks in this layout. Layout  200 D 5  of FIG.  2 D 5  illustrates the inter-block links between the switch  2  and switch  3  of the VLSI layout diagram  200 D 3  of FIG.  2 D 3 . For example middle links ML( 2 , 12 ) and ML( 5 , 4 ) are connected between Block  1 _ 2  and Block  5 _ 6 . It must be noted that all the inter-block links between switch  2  and switch  3  of all blocks are horizontal tracks in this layout. Layout  200 D 6  of FIG.  2 D 6  illustrates the inter-block links between the switch  3  and switch  4  of the VLSI layout diagram  200 D 3  of FIG.  2 D 3 . For example middle links ML( 3 , 4 ) and ML( 4 , 20 ) are connected between Block  1 _ 2  and Block  9 _ 10 . It must be noted that all the inter-block links between switch  3  and switch  4  of all blocks are vertical tracks in this layout. 
       Generalized Multi-link Butterfly Fat Tree Network Embodiment 
       [0108]    In another embodiment in the network  100 B of  FIG. 1B , the switches that are placed together are implemented as combined switch then the network  100 B is the generalized multi-link butterfly fat tree network V mlink-bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with five stages as disclosed in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a six by six switch. For example the input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  and output OS 1  are implemented as a six by six switch with the inlet links IL 1 , IL 2 , ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs of the combined switch (denoted as IS 1 &amp;OS 1 ) and middle links ML( 1 , 1 ), ML( 1 , 2 ), ML( 1 , 3 ), ML( 1 , 4 ), OL 1  and OL 2  being the outputs of the combined switch IS 1 &amp;OS 1 . Similarly in this embodiment of network  100 B all the switches that are placed together are implemented as a combined switch. 
         [0109]    Layout diagrams  100 C in  FIG. 1C ,  100 D in  FIG. 1D ,  100 E in  FIG. 1E ,  100 F in  FIG. 1G  are also applicable to generalized multi-link butterfly fat tree network V mlink-bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with five stages. The layout  100 C in  FIG. 1C  can be recursively extended for any arbitrarily large generalized multi-link butterfly fat tree network V mlink-bft (N 1 , N 2 , d, s). Accordingly layout  100 H of  FIG. 1H  is also applicable to generalized multi-link butterfly fat tree network V mlink-bft (N 1 , N 2 , d, s). 
         [0110]    Referring to diagram  100 J of  FIG. 1J  illustrates a high-level implementation of Block  1 _ 2  (Each of the other blocks have similar implementation) of the layout  100 C of  FIG. 1C  which represents a generalized multi-link butterfly fat tree network V mlink-bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2. Block  1 _ 2  in  100 J illustrates both the intra-block and inter-block links. The layout diagram  100 J corresponds to the embodiment where the switches that are placed together are implemented as combined switch in the network  100 B of  FIG. 1B . As noted before then the network  100 B is the generalized multi-link butterfly fat tree network V mlink-bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with five stages as disclosed in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. 
         [0111]    That is the switches that are placed together in Block  1 _ 2  as shown in  FIG. 1J  are namely the combined input and output switch IS 1 &amp;OS 1  belonging to switch  1 , illustrated by dotted lines, (as noted before switch  1  is for illustration purposes only, in practice the switch implemented is combined input and output switch IS 1 &amp;OS 1 ); middle switch MS( 1 , 1 ) belonging to switch  2 ; middle switch MS( 2 , 1 ) belonging to switch  3 ; middle switch MS( 3 , 1 ) belonging to switch  4 ; And middle switch MS( 4 , 1 ) belonging to switch  5 . 
         [0112]    Combined input and output switch IS 1 &amp;OS 1  is implemented as six by six switch with the inlet links IL 1 , IL 2  and ML( 8 , 1 )-ML( 8 , 4 ) being the inputs and middle links ML( 1 , 1 )-ML( 1 , 4 ), and outlet links OL 1 -OL 2  being the outputs. 
         [0113]    Middle switch MS( 1 , 1 ) is implemented as eight by eight switch with the middle links ML( 1 , 1 ), ML( 1 , 2 ), ML( 1 , 7 ), ML( 1 , 8 ), ML( 7 , 1 ), ML( 7 , 2 ), ML( 7 , 11 ) and ML( 7 , 12 ) being the inputs and middle links ML( 2 , 1 )-ML( 2 , 4 ) and middle links ML( 8 , 1 )-ML( 8 , 4 ) being the outputs. Similarly all the other middle switches are also implemented as eight by eight switches as illustrated in  100 J of  FIG. 1J . Applicant observes that in middle switch MS( 1 , 1 ) any one of the right going middle links can be switched to any one of the left going middle links and hereinafter middle switch MS( 1 , 1 ) provides U-turn links. In general, in the network V mlink-bft (N 1 , N 2 , d, s) each input switch, each output switch and each middle switch provides U-turn links. 
         [0114]    In another embodiment, middle switch MS( 1 , 1 ) (or the middle switches in any of the middle stage excepting the root middle stage) of Block  1 _ 2  of V mlink-bft (N 1 , N 2 , d, s) can be implemented as a four by eight switch and a four by four switch to save cross points. This is because the left going middle links of these middle switches are never setup to the right going middle links For example, in middle switch MS( 1 , 1 ) of Block  1 _ 2  as shown  FIG. 1J , the left going middle links namely ML( 7 , 1 ), ML( 7 , 2 ), ML( 7 , 11 ), and ML( 7 , 12 ) are never switched to the right going middle links ML( 2 , 1 ), ML( 2 , 2 ), ML( 2 , 3 ), and ML( 2 , 4 ). And hence to implement MS( 1 , 1 ) two switches namely: 1) a four by eight switch with the middle links ML( 1 , 1 ), ML( 1 , 2 ), ML( 1 , 7 ), and ML( 1 , 8 ) as inputs and the middle links ML( 2 , 1 ), ML( 2 , 2 ), ML( 2 , 3 ), ML( 2 , 4 ), ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 3 ), and ML( 8 , 4 ) as outputs and 2) a four by four switch with the middle links ML( 7 , 1 ), ML( 7 , 2 ), ML( 7 , 11 ), and ML( 7 , 12 ) as inputs and the middle links ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 3 ), and ML( 8 , 4 ) as outputs are sufficient without loosing any connectivity of the embodiment of MS( 1 , 1 ) being implemented as an eight by eight switch as described before.) 
       Generalized Multi-Stage Network Embodiment 
       [0115]    In one embodiment, in the network  100 B of  FIG. 1B , the switches that are placed together are implemented as two separate switches in input stage  110  and output stage  120 ; and as four separate switches in all the middle stages, then the network  100 B is the generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a two by four switch and a four by two switch respectively. For example the switch input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  is implemented as two by four switch with the inlet links IL 1  and IL 2  being the inputs and middle links ML( 1 , 1 )-ML( 1 , 4 ) being the outputs; and output switch OS 1  is implemented as four by two switch with the middle links ML( 8 , 1 ), ML( 8 , 4 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs and outlet links OL 1 -OL 2  being the outputs. 
         [0116]    The switches, corresponding to the middle stages that are placed together are implemented as four two by two switches. For example middle switches MS( 1 , 1 ), MS( 1 , 17 ), MS( 7 , 1 ), and MS( 7 , 17 ) are placed together; so middle switch MS( 1 , 1 ) is implemented as two by two switch with middle links ML( 1 , 1 ) and ML( 1 , 7 ) being the inputs and middle links ML( 2 , 1 ) and ML( 2 , 3 ) being the outputs; middle switch MS( 1 , 17 ) is implemented as two by two switch with the middle links ML( 1 , 2 ) and ML( 1 , 8 ) being the inputs and middle links ML( 2 , 2 ) and ML( 2 , 4 ) being the outputs; middle switch MS( 7 , 1 ) is implemented as two by two switch with middle links ML( 7 , 1 ) and ML( 7 , 11 ) being the inputs and middle links ML( 8 , 1 ) and ML( 8 , 3 ) being the outputs; And middle switch MS( 7 , 17 ) is implemented as two by two switch with the middle links ML( 7 , 2 ) and ML( 7 , 12 ) being the inputs and middle links ML( 8 , 2 ) and ML( 8 , 4 ) being the outputs; Similarly in this embodiment of network  100 B all the switches that are placed together are implemented as separate switches. 
         [0117]    Layout diagrams  100 C in  FIG. 1C ,  100 D in  FIG. 1D ,  100 E in  FIG. 1E ,  100 F in  FIG. 1G  are also applicable to generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages. The layout  100 C in  FIG. 1C  can be recursively extended for any arbitrarily large generalized folded multi-stage network V fold (N 1 , N 2 , d, s). Accordingly layout  100 H of  FIG. 1H  is also applicable to generalized folded multi-stage network V fold (N 1 , N 2 , d, s). 
         [0118]    Referring to diagram  100 K of  FIG. 1K  illustrates a high-level implementation of Block  1 _ 2  (Each of the other blocks have similar implementation) of the layout  100 C of  FIG. 1C  which represents a generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2. Block  1 _ 2  in  100 K illustrates both the intra-block and inter-block links. The layout diagram  100 K corresponds to the embodiment where the switches that are placed together are implemented as separate switches in the network  100 B of  FIG. 1B . As noted before then the network  100 B is the generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. 
         [0119]    That is the switches that are placed together in Block  1 _ 2  as shown in  FIG. 1K  are namely the input switch IS 1  and output switch OS 1  belonging to switch  1 , illustrated by dotted lines, (as noted before switch  1  is for illustration purposes only, in practice the switches implemented are input switch IS 1  and output switch OS 1 ); middle switches MS( 1 , 1 ), MS( 1 , 17 ), MS( 7 , 1 ) and MS( 7 , 17 ) belonging to switch  2 ; middle switches MS( 2 , 1 ), MS( 2 , 17 ), MS( 6 , 1 ) and MS( 6 , 17 ) belonging to switch  3 ; middle switches MS( 3 , 1 ), MS( 3 , 17 ), MS( 5 , 1 ) and MS( 5 , 17 ) belonging to switch  4 ; And middle switches MS( 4 , 1 ), and MS( 4 , 17 ) belonging to switch  5 . 
         [0120]    Input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  is implemented as two by four switch with the inlet links IL 1  and IL 2  being the inputs and middle links ML( 1 , 1 )-ML( 1 , 4 ) being the outputs; and output switch OS 1  is implemented as four by two switch with the middle links ML( 8 , 1 ), ML( 8 , 4 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs and outlet links OL 1 -OL 2  being the outputs. 
         [0121]    Middle switches MS( 1 , 1 ), MS( 1 , 17 ), MS( 7 , 1 ), and MS( 7 , 17 ) are placed together; so middle switch MS( 1 , 1 ) is implemented as two by two switch with middle links ML( 1 , 1 ) and ML( 1 , 7 ) being the inputs and middle links ML( 2 , 1 ) and ML( 2 , 3 ) being the outputs; middle switch MS( 1 , 17 ) is implemented as two by two switch with the middle links ML( 1 , 2 ) and ML( 1 , 8 ) being the inputs and middle links ML( 2 , 2 ) and ML( 2 , 4 ) being the outputs; middle switch MS( 7 , 1 ) is implemented as two by two switch with middle links ML( 7 , 1 ) and ML( 7 , 11 ) being the inputs and middle links ML( 8 , 1 ) and ML( 8 , 3 ) being the outputs; And middle switch MS( 7 , 17 ) is implemented as two by two switch with the middle links ML( 7 , 2 ) and ML( 7 , 12 ) being the inputs and middle links ML( 8 , 2 ) and ML( 8 , 4 ) being the outputs Similarly all the other middle switches are also implemented as two by two switches as illustrated in  100 K of  FIG. 1K . 
       Generalized Multi-Stage Network Embodiment with S=1 
       [0122]    In one embodiment, in the network  100 B of  FIG. 1B  (where it is implemented with s=1), the switches that are placed together are implemented as two separate switches in input stage  110  and output stage  120 ; and as two separate switches in all the middle stages, then the network  100 B is the generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a two by two switch and a two by two switch. For example the switch input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  is implemented as two by two switch with the inlet links IL 1  and IL 2  being the inputs and middle links ML( 1 , 1 )-ML( 1 , 2 ) being the outputs; and output switch OS 1  is implemented as two by two switch with the middle links ML( 8 , 1 ) and ML( 8 , 3 ) being the inputs and outlet links OL 1 -OL 2  being the outputs. 
         [0123]    The switches, corresponding to the middle stages that are placed together are implemented as two, two by two switches. For example middle switches MS( 1 , 1 ) and MS( 7 , 1 ) are placed together; so middle switch MS( 1 , 1 ) is implemented as two by two switch with middle links ML( 1 , 1 ) and ML( 1 , 3 ) being the inputs and middle links ML( 2 , 1 ) and ML( 2 , 2 ) being the outputs; middle switch MS( 7 , 1 ) is implemented as two by two switch with middle links ML( 7 , 1 ) and ML( 7 , 5 ) being the inputs and middle links ML( 8 , 1 ) and ML( 8 , 2 ) being the outputs; Similarly in this embodiment of network  100 B all the switches that are placed together are implemented as two separate switches. 
         [0124]    Layout diagrams  100 C in  FIG. 1C ,  100 D in  FIG. 1D ,  100 E in  FIG. 1E ,  100 F in  FIG. 1G  are also applicable to generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 with nine stages. The layout  100 C in  FIG. 1C  can be recursively extended for any arbitrarily large generalized folded multi-stage network V fold (N 1 , N 2 , d, s). Accordingly layout  100 H of  FIG. 1H  is also applicable to generalized folded multi-stage network V fold (N 1 , N 2 , d, s). 
         [0125]    Referring to diagram  100 K 1  of FIG.  1 K 1  illustrates a high-level implementation of Block  1 _ 2  (Each of the other blocks have similar implementation) for the layout  100 C of  FIG. 1C  when s=1 which represents a generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 (All the double links are replaced by single links when s=1). Block  1 _ 2  in  100 K 1  illustrates both the intra-block and inter-block links. The layout diagram  100 K 1  corresponds to the embodiment where the switches that are placed together are implemented as separate switches in the network  100 B of  FIG. 1B  when s=1. As noted before then the network  100 B is the generalized folded multi-stage network V fold (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. 
         [0126]    That is the switches that are placed together in Block  1 _ 2  as shown in FIG.  1 K 1  are namely the input switch IS 1  and output switch OS 1  belonging to switch  1 , illustrated by dotted lines, (as noted before switch  1  is for illustration purposes only, in practice the switches implemented are input switch IS 1  and output switch OS 1 ); middle switches MS( 1 , 1 ) and MS( 7 , 1 ) belonging to switch  2 ; middle switches MS( 2 , 1 ) and MS( 6 , 1 ) belonging to switch  3 ; middle switches MS( 3 , 1 ) and MS( 5 , 1 ) belonging to switch  4 ; And middle switch MS( 4 , 1 ) belonging to switch  5 . 
         [0127]    Input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  is implemented as two by two switch with the inlet links IL 1  and IL 2  being the inputs and middle links ML( 1 , 1 )-ML( 1 , 2 ) being the outputs; and output switch OS 1  is implemented as two by two switch with the middle links ML( 8 , 1 ) and ML( 8 , 3 ) being the inputs and outlet links OL 1 -OL 2  being the outputs. 
         [0128]    Middle switches MS( 1 , 1 ) and MS( 7 , 1 ) are placed together; so middle switch MS( 1 , 1 ) is implemented as two by two switch with middle links ML( 1 , 1 ) and ML( 1 , 3 ) being the inputs and middle links ML( 2 , 1 ) and ML( 2 , 2 ) being the outputs; And middle switch MS( 7 , 1 ) is implemented as two by two switch with middle links ML( 7 , 1 ) and ML( 7 , 5 ) being the inputs and middle links ML( 8 , 1 ) and ML( 8 , 2 ) being the outputs. Similarly all the other middle switches are also implemented as two by two switches as illustrated in  100 K 1  of FIG.  1 K 1 . 
       Generalized Butterfly Fat Tree Network Embodiment 
       [0129]    In another embodiment in the network  100 B of  FIG. 1B , the switches that are placed together are implemented as two combined switches then the network  100 B is the generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with five stages as disclosed in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a six by six switch. For example the input switch IS 1  and output switch OS 1  are placed together; so input output switch IS 1 &amp;OS 1  are implemented as a six by six switch with the inlet links IL 1 , IL 2 , ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs of the combined switch (denoted as IS 1 &amp;OS 1 ) and middle links ML( 1 , 1 ), ML( 1 , 2 ), ML( 1 , 3 ), ML( 1 , 4 ), OL 1  and OL 2  being the outputs of the combined switch IS 1 &amp;OS 1 . 
         [0130]    The switches, corresponding to the middle stages that are placed together are implemented as two four by four switches. For example middle switches MS( 1 , 1 ) and MS( 1 , 17 ) are placed together; so middle switch MS( 1 , 1 ) is implemented as four by four switch with middle links ML( 1 , 1 ), ML( 1 , 7 ), ML( 7 , 1 ) and ML( 7 , 11 ) being the inputs and middle links ML( 2 , 1 ), ML( 2 , 3 ), ML( 8 , 1 ) and ML( 8 , 3 ) being the outputs; middle switch MS( 1 , 17 ) is implemented as four by four switch with the middle links ML( 1 , 2 ), ML( 1 , 8 ), ML( 7 , 2 ) and ML( 7 , 12 ) being the inputs and middle links ML( 2 , 2 ), ML( 2 , 4 ), ML( 8 , 2 ) and ML( 8 , 4 ) being the outputs. Similarly in this embodiment of network  100 B all the switches that are placed together are implemented as a two combined switches. 
         [0131]    Layout diagrams  100 C in  FIG. 1C ,  100 D in  FIG. 1D ,  100 E in  FIG. 1E ,  100 F in  FIG. 1G  are also applicable to generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with five stages. The layout  100 C in  FIG. 1C  can be recursively extended for any arbitrarily large generalized butterfly fat tree network V bft (N 1 , N 2 , d, s). Accordingly layout  100 H of  FIG. 1H  is also applicable to generalized butterfly fat tree network V bft (N 1 , N 2 , d, s). 
         [0132]    Referring to diagram  100 L of  FIG. 1L  illustrates a high-level implementation of Block  1 _ 2  (Each of the other blocks have similar implementation) of the layout  100 C of  FIG. 1C  which represents a generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2. Block  1 _ 2  in  100 L illustrates both the intra-block and inter-block links. The layout diagram  100 L corresponds to the embodiment where the switches that are placed together are implemented as two combined switches in the network  100 B of  FIG. 1B . As noted before then the network  100 B is the generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with five stages as disclosed in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. 
         [0133]    That is the switches that are placed together in Block  1 _ 2  as shown in  FIG. 1L  are namely the combined input and output switch IS 1 &amp;OS 1  belonging to switch  1 , illustrated by dotted lines, (as noted before switch  1  is for illustration purposes only, in practice the switch implemented is combined input and output switch IS 1 &amp;OS 1 ); middle switch MS( 1 , 1 ) and MS( 1 , 17 ) belonging to switch  2 ; middle switch MS( 2 , 1 ) and MS( 2 , 17 ) belonging to switch  3 ; middle switch MS( 3 , 1 ) and MS( 3 , 17 ) belonging to switch  4 ; And middle switch MS( 4 , 1 ) belonging to switch  5 . 
         [0134]    Combined input and output switch IS 1 &amp;OS 1  is implemented as six by six switch with the inlet links IL 1 , IL 2 , ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs and middle links ML( 1 , 1 )-ML( 1 , 4 ) and outlet links OL 1 -OL 2  being the outputs. 
         [0135]    Middle switch MS( 1 , 1 ) is implemented as four by four switch with middle links ML( 1 , 1 ), ML( 1 , 7 ), ML( 7 , 1 ) and ML( 7 , 11 ) being the inputs and middle links ML( 2 , 1 ), ML( 2 , 3 ), ML( 8 , 1 ) and ML( 8 , 3 ) being the outputs; And middle switch MS( 1 , 17 ) is implemented as four by four switch with the middle links ML( 1 , 2 ), ML( 1 , 8 ), ML( 7 , 2 ) and ML( 7 , 12 ) being the inputs and middle links ML( 2 , 2 ), ML( 2 , 4 ), ML( 8 , 2 ) and ML( 8 , 4 ) being the outputs. Similarly all the other middle switches are also implemented as two four by four switches as illustrated in  100 L of  FIG. 1L . Applicant observes that in middle switch MS( 1 , 1 ) any one of the right going middle links can be switched to any one of the left going middle links and hereinafter middle switch MS( 1 , 1 ) provides U-turn links. In general, in the network V bft (N 1 , N 2 , d, s) each input switch, each output switch and each middle switch provides U-turn links. 
         [0136]    In another embodiment, middle switch MS( 1 , 1 ) (or the middle switches in any of the middle stage excepting the root middle stage) of Block  1 _ 2  of V bft (N 1 , N 2 , d, s) can be implemented as a two by four switch and a two by two switch to save cross points. This is because the left going middle links of these middle switches are never setup to the right going middle links. For example, in middle switch MS( 1 , 1 ) of Block  1 _ 2  as shown  FIG. 1L , the left going middle links namely ML( 7 , 1 ) and ML( 7 , 11 ) are never switched to the right going middle links ML( 2 , 1 ) and ML( 2 , 3 ). And hence to implement MS( 1 , 1 ) two switches namely: 1) a two by four switch with the middle links ML( 1 , 1 ) and ML( 1 , 7 ) as inputs and the middle links ML( 2 , 1 ), ML( 2 , 3 ), ML( 8 , 1 ), and ML( 8 , 3 ) as outputs and 2) a two by two switch with the middle links ML( 7 , 1 ) and ML( 7 , 11 ) as inputs and the middle links ML( 8 , 1 ) and ML( 8 , 3 ) as outputs are sufficient without loosing any connectivity of the embodiment of MS( 1 , 1 ) being implemented as an eight by eight switch as described before.) 
       Generalized Butterfly Fat Tree Network Embodiment with S=1 
       [0137]    In one embodiment, in the network  100 B of  FIG. 1B  (where it is implemented with s=1), the switches that are placed together are implemented as a combined switch in input stage  110  and output stage  120 ; and as a combined switch in all the middle stages, then the network  100 B is the generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 with five stages as disclosed in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a four by four switch. For example the switch input switch IS 1  and output switch OS 1  are placed together; so input and output switch IS 1 &amp;OS 1  is implemented as four by four switch with the inlet links IL 1 , IL 2 , ML( 8 , 1 ) and ML( 8 , 3 ) being the inputs and middle links ML( 1 , 1 )-ML( 1 , 2 ) and outlet links OL 1 -OL 2  being the outputs 
         [0138]    The switches, corresponding to the middle stages that are placed together are implemented as a four by four switch. For example middle switches MS( 1 , 1 ) is implemented as four by four switch with middle links ML( 1 , 1 ), ML( 1 , 3 ), ML( 7 , 1 ) and ML( 7 , 5 ) being the inputs and middle links ML( 2 , 1 ), ML( 2 , 2 ), ML( 8 , 1 ) and ML( 8 , 2 ) being the outputs. 
         [0139]    Layout diagrams  100 C in  FIG. 1C ,  100 D in  FIG. 1D ,  100 E in  FIG. 1E ,  100 F in  FIG. 1G  are also applicable to generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 with five stages. The layout  100 C in  FIG. 1C  can be recursively extended for any arbitrarily large generalized butterfly fat tree network V bft (N 1 , N 2 , d, s). Accordingly layout  100 H of  FIG. 1H  is also applicable to generalized butterfly fat tree network V bft (N 1 , N 2 , d, s). 
         [0140]    Referring to diagram  100 L 1  of FIG.  1 L 1  illustrates a high-level implementation of Block  1 _ 2  (Each of the other blocks have similar implementation) for the layout  100 C of  FIG. 1C  when s=1 which represents a generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 (All the double links are replaced by single links when s=1). Block  1 _ 2  in  100 K 1  illustrates both the intra-block and inter-block links The layout diagram  100 L 1  corresponds to the embodiment where the switches that are placed together are implemented as a combined switch in the network  100 B of  FIG. 1B  when s=1. As noted before then the network  100 B is the generalized butterfly fat tree network V bft (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=1 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64603 that is incorporated by reference above. 
         [0141]    That is the switches that are placed together in Block  1 _ 2  as shown in FIG.  1 L 1  are namely the input and output switch IS 1 &amp;OS 1  belonging to switch  1 , illustrated by dotted lines, (as noted before switch  1  is for illustration purposes only, in practice the switches implemented are input switch IS 1  and output switch OS 1 ); middle switch MS( 1 , 1 ) belonging to switch  2 ; middle switch MS( 2 , 1 ) belonging to switch  3 ; middle switch MS( 3 , 1 ) belonging to switch  4 ; And middle switch MS( 4 , 1 ) belonging to switch  5 . 
         [0142]    Input and output switch IS 1 &amp;OS 1  are placed together; so input and output switch IS 1 &amp;OS 1  is implemented as four by four switch with the inlet links IL 1 , IL 2 , ML( 8 , 1 ) and ML( 8 , 3 ) being the inputs and middle links ML( 1 , 1 )-ML( 1 , 2 ) and outlet links OL 1 -OL 2  being the outputs. 
         [0143]    Middle switch MS( 1 , 1 ) is implemented as four by four switch with middle links ML( 1 , 1 ), ML( 1 , 3 ), ML( 7 , 1 ) and ML( 7 , 5 ) being the inputs and middle links ML( 2 , 1 ), ML( 2 , 2 ), ML( 8 , 1 ) and ML( 8 , 2 ) being the outputs. Similarly all the other middle switches are also implemented as four by four switches as illustrated in  100 L 1  of FIG.  1 L 1 . 
         [0144]    In another embodiment, middle switch MS( 1 , 1 ) (or the middle switches in any of the middle stage excepting the root middle stage) of Block  1 _ 2  of V mlink-bft (N 1 , N 2 , d, s) can be implemented as a two by four switch and a two by two switch to save cross points. This is because the left going middle links of these middle switches are never setup to the right going middle links For example, in middle switch MS( 1 , 1 ) of Block  1 _ 2  as shown FIG.  1 L 1 , the left going middle links namely ML( 7 , 1 ) and ML( 7 , 5 ) are never switched to the right going middle links ML( 2 , 1 ) and ML( 2 , 2 ). And hence to implement MS( 1 , 1 ) two switches namely: 1) a two by four switch with the middle links ML( 1 , 1 ) and ML( 1 , 3 ) as inputs and the middle links ML( 2 , 1 ), ML( 2 , 2 ), ML( 8 , 1 ), and ML( 8 , 2 ) as outputs and 2) a two by two switch with the middle links ML( 7 , 1 ) and ML( 7 , 5 ) as inputs and the middle links ML( 8 , 1 ) and ML( 8 , 2 ) as outputs are sufficient without loosing any connectivity of the embodiment of MS( 1 , 1 ) being implemented as an eight by eight switch as described before.) 
       Hypercube-Like Topology Layout Schemes: 
       [0145]    Referring to diagram  300 A in  FIG. 3A , in one embodiment, an exemplary generalized multi-link multi-stage network V mlink (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages of one hundred and forty four switches for satisfying communication requests, such as setting up a telephone call or a data call, or a connection between configurable logic blocks, between an input stage  110  and output stage  120  via middle stages  130 ,  140 ,  150 ,  170 ,  170 ,  180  and  190  is shown where input stage  110  consists of sixteen, two by four switches IS 1 -IS 16  and output stage  120  consists of sixteen, four by two switches OS 1 -OS 16 . 
         [0146]    As disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above, such a network can be operated in rearrangeably non-blocking manner for arbitrary fan-out multicast connections and also can be operated in strictly non-blocking manner for unicast connections. 
         [0147]    The diagram  300 A in  FIG. 3A  is exactly the same as the diagram  100 A in  FIG. 1A  excepting the connection links between middle stage  150  and middle stage  160  as well as between middle stage  160  and middle stage  170 . 
         [0148]    Each of the N/d middle switches are connected to exactly d switches in middle stage  160  through two links each for a total of 2×d links (for example the links ML( 4 , 1 ) and ML( 4 , 2 ) are connected from middle switch MS( 3 , 1 ) to middle switch MS( 4 , 1 ), and the links ML( 4 , 3 ) and ML( 4 , 4 ) are connected from middle switch MS( 3 , 1 ) to middle switch MS( 4 , 15 )). 
         [0149]    Each of the N/d middle switches MS( 4 , 1 )-MS( 4 , 16 ) in the middle stage  160  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 4 , 1 ) and ML( 4 , 2 ) are connected to the middle switch MS( 4 , 1 ) from input switch MS( 3 , 1 ), and the links ML( 4 , 59 ) and ML( 4 , 60 ) are connected to the middle switch MS( 4 , 1 ) from input switch MS( 3 , 15 )) and also are connected to exactly d switches in middle stage  170  through two links each for a total of 2×d links (for example the links ML( 5 , 1 ) and ML( 5 , 2 ) are connected from middle switch MS( 4 , 1 ) to middle switch MS( 5 , 1 ), and the links ML( 5 , 3 ) and ML( 5 , 4 ) are connected from middle switch MS( 4 , 1 ) to middle switch MS( 5 , 15 )). 
         [0150]    Each of the N/d middle switches MS( 5 , 1 )-MS( 5 , 16 ) in the middle stage  170  are connected from exactly d input switches through two links each for a total of 2×d links (for example the links ML( 5 , 1 ) and ML( 5 , 2 ) are connected to the middle switch MS( 5 , 1 ) from input switch MS( 4 , 1 ), and the links ML( 5 , 59 ) and ML( 5 , 60 ) are connected to the middle switch MS( 5 , 1 ) from input switch MS( 4 , 15 )). 
         [0151]    Finally the connection topology of the network  100 A shown in  FIG. 1A  is also basically back to back inverse Benes connection topology but with a slight variation. All the cross middle links from middle switches MS( 3 , 1 )-MS( 3 , 8 ) connect to middle switches MS( 4 , 9 )-MS( 4 , 16 ) and all the cross middle links from middle switches MS( 3 , 9 )-MS( 3 , 16 ) connect to middle switches MS( 4 , 1 )-MS( 4 , 8 ). Applicant makes a key observation that there are many combinations of connections possible using this property. The difference in the connection topology between diagram  100 A of  FIG. 1A  and diagram  300 A of  FIG. 3A  is that the connections formed by cross middle links between middle stage  150  and middle stage  160  are made of two different combinations otherwise both the diagrams  100 A and  300 A implement back to back inverse Benes connection topology. Since these networks implement back to back inverse Benes topologies since there is difference in the connections of cross middle links between middle stage  150  and middle stage  160 , the same difference in the connections of cross middle links between  160  and middle stage  170  occurs. 
         [0152]    Referring to diagram  300 B in  FIG. 3B , is a folded version of the multi-link multi-stage network  300 A shown in  FIG. 3A . The network  300 B in  FIG. 3B  shows input stage  110  and output stage  120  are placed together. That is input switch IS 1  and output switch OS 1  are placed together, input switch IS 2  and output switch OS 2  are placed together, and similarly input switch IS 16  and output switch OS 16  are placed together. All the right going middle links {i.e., inlet links IL 1 -IL 32  and middle links ML( 1 , 1 )-ML( 1 , 64 )} correspond to input switches IS 1 -IS 16 , and all the left going middle links {i.e., middle links ML( 7 , 1 )-ML( 7 , 64 ) and outlet links OL 1 -OL 32 } correspond to output switches OS 1 -OS 16 . 
         [0153]    Just the same way there is difference in the connection topology between diagram  100 A of  FIG. 1A  and diagram  300 A of  FIG. 3A  in the way the connections are formed by cross middle links between middle stage  150  and middle stage  160  and also between middle stage  160  and middle stage  170 , the exact similar difference is there between the diagram  100 B of  FIG. 1B  and the diagram  300 B of  FIG. 3B , i.e., in the way the connections are formed by cross middle links between middle stage  150  and middle stage  160  and also between middle stage  160  and middle stage  170 . 
         [0154]    In one embodiment, in the network  300 B of  FIG. 3B , the switches that are placed together are implemented as separate switches then the network  300 B is the generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =32; d=2; and s=2 with nine stages as disclosed in PCT Application Serial No. PCT/US08/64604 that is incorporated by reference above. That is the switches that are placed together in input stage  110  and output stage  120  are implemented as a two by four switch and a four by two switch. For example the switch input switch IS 1  and output switch OS 1  are placed together; so input switch IS 1  is implemented as two by four switch with the inlet links IL 1  and IL 2  being the inputs of the input switch IS 1  and middle links ML( 1 , 1 )-ML( 1 , 4 ) being the outputs of the input switch IS 1 ; and output switch OS 1  is implemented as four by two switch with the middle links ML( 8 , 1 ), ML( 8 , 2 ), ML( 8 , 7 ) and ML( 8 , 8 ) being the inputs of the output switch OS 1  and outlet links OL 1 -OL 2  being the outputs of the output switch OS 1 . Similarly in this embodiment of network  300 B all the switches that are placed together are implemented as separate switches. 
         [0155]    Referring to layout  300 C of  FIG. 3C , in one embodiment, there are sixteen blocks namely Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , Block  7 _ 8 , Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14 , Block  15 _ 16 , Block  17 _ 18 , Block  19 _ 20 , Block  21 _ 22 , Block  23 _ 24 , Block  25 _ 26 , Block  27 _ 28 , Block  29 _ 30 , and Block  31 _ 32 . Each block implements all the switches in one row of the network  300 B of  FIG. 3B , one of the key aspects of the current invention. For example Block  1 _ 2  implements the input switch IS 1 , output Switch OS 1 , middle switch MS( 1 , 1 ), middle switch MS( 7 , 1 ), middle switch MS( 2 , 1 ), middle switch MS( 6 , 1 ), middle switch MS( 3 , 1 ), middle switch MS( 5 , 1 ), and middle switch MS( 4 , 1 ). For the simplification of illustration, Input switch IS 1  and output switch OS 1  together are denoted as switch  1 ; Middle switch MS( 1 , 1 ) and middle switch MS( 7 , 1 ) together are denoted by switch  2 ; Middle switch MS( 2 , 1 ) and middle switch MS( 6 , 1 ) together are denoted by switch  3 ; Middle switch MS( 3 , 1 ) and middle switch MS( 5 , 1 ) together are denoted by switch  4 ; And middle switch MS( 4 , 1 ) is denoted by switch  5 . 
         [0156]    All the straight middle links are illustrated in layout  300 C of  FIG. 3C . For example in Block  1 _ 2 , inlet links IL 1 -IL 2 , outlet links OL 1 -OL 2 , middle link ML( 1 , 1 ), middle link ML( 1 , 2 ), middle link ML( 8 , 1 ), middle link ML( 8 , 2 ), middle link ML( 2 , 1 ), middle link ML( 2 , 2 ), middle link ML( 7 , 1 ), middle link ML( 7 , 2 ), middle link ML( 3 , 1 ), middle link ML( 3 , 2 ), middle link ML( 6 , 1 ), middle link ML( 6 , 2 ), middle link ML( 4 , 1 ), middle link ML( 4 , 2 ), middle link ML( 5 , 1 ) and middle link ML( 5 , 2 ) are illustrated in layout  300 C of  FIG. 3C . 
         [0157]    Even though it is not illustrated in layout  300 C of  FIG. 3C , in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit or sub-integrated circuit block depending on the applications in different embodiments. There are four quadrants in the layout  300 C of  FIG. 3C  namely top-left, bottom-left, top-right and bottom-right quadrants. Top-left quadrant implements Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , and Block  7 _ 8 . Bottom-left quadrant implements Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14 , and Block  15 _ 16 . Top-right quadrant implements Block  25 _ 26 , Block  27 _ 28 , Block  29 _ 30 , and Block  31 _ 32 . Bottom-right quadrant implements Block  17 _ 18 , Block  19 _ 20 , Block  21 _ 22 , and Block  23 _ 24 . There are two halves in layout  300 C of  FIG. 3C  namely left-half and right-half. Left-half consists of top-left and bottom-left quadrants. Right-half consists of top-right and bottom-right quadrants. 
         [0158]    Recursively in each quadrant there are four sub-quadrants. For example in top-left quadrant there are four sub-quadrants namely top-left sub-quadrant, bottom-left sub-quadrant, top-right sub-quadrant and bottom-right sub-quadrant. Top-left sub-quadrant of top-left quadrant implements Block  1 _ 2 . Bottom-left sub-quadrant of top-left quadrant implements Block  3 _ 4 . Top-right sub-quadrant of top-left quadrant implements Block  7 _ 8 . Finally bottom-right sub-quadrant of top-left quadrant implements Block  5 _ 6 . Similarly there are two sub-halves in each quadrant. For example in top-left quadrant there are two sub-halves namely left-sub-half and right-sub-half. Left-sub-half of top-left quadrant implements Block  1 _ 2  and Block  3 _ 4 . Right-sub-half of top-left quadrant implements Block  7 _ 8  and Block  5 _ 6 . Recursively in larger multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 &gt;32, the layout in this embodiment in accordance with the current invention, will be such that the super-quadrants will also be arranged in a similar manner. 
         [0159]    Layout  300 D of  FIG. 3D  illustrates the inter-block links (in the layout  300 C of  FIG. 3C  all the cross middle links are inter-block links) between switches  1  and  2  of each block. For example middle links ML( 1 , 3 ), ML( 1 , 4 ), ML( 8 , 7 ), and ML( 8 , 8 ) are connected between switch  1  of Block  1 _ 2  and switch  2  of Block  3 _ 4 . Similarly middle links ML( 1 , 7 ), ML( 1 , 8 ), ML( 8 , 3 ), and ML( 8 , 4 ) are connected between switch  2  of Block  1 _ 2  and switch  1  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  100 D of  FIG. 1D  can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 1 , 4 ) and ML( 8 , 8 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 1 , 4 ) and ML( 8 , 8 ) are implemented as a time division multiplexed single track). 
         [0160]    Layout  300 E of  FIG. 3E  illustrates the inter-block links between switches  2  and  3  of each block. For example middle links ML( 2 , 3 ), ML( 2 , 4 ), ML( 7 , 11 ), and ML( 7 , 12 ) are connected between switch  2  of Block  1 _ 2  and switch  3  of Block  3 _ 4 . Similarly middle links ML( 2 , 11 ), ML( 2 , 12 ), ML( 7 , 3 ), and ML( 7 , 4 ) are connected between switch  3  of Block  1 _ 2  and switch  2  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  300 E of  FIG. 3E  can be implemented as diagonal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 2 , 12 ) and ML( 7 , 4 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 2 , 12 ) and ML( 7 , 4 ) are implemented as a time division multiplexed single track). 
         [0161]    Layout  300 F of  FIG. 3F  illustrates the inter-block links between switches  3  and  4  of each block. For example middle links ML( 3 , 3 ), ML( 3 , 4 ), ML( 6 , 19 ), and ML( 6 , 20 ) are connected between switch  3  of Block  1 _ 2  and switch  4  of Block  3 _ 4 . Similarly middle links ML( 3 , 19 ), ML( 3 , 20 ), ML( 6 , 3 ), and ML( 6 , 4 ) are connected between switch  4  of Block  1 _ 2  and switch  3  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  300 F of  FIG. 3F  can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 3 , 4 ) and ML( 6 , 20 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 3 , 4 ) and ML( 6 , 20 ) are implemented as a time division multiplexed single track). 
         [0162]    Layout  300 G of  FIG. 3G  illustrates the inter-block links between switches  4  and  5  of each block. For example middle links ML( 4 , 3 ), ML( 4 , 4 ), ML( 5 , 35 ), and ML( 5 , 36 ) are connected between switch  4  of Block  1 _ 2  and switch  5  of Block  3 _ 4 . Similarly middle links ML( 4 , 35 ), ML( 4 , 36 ), ML( 5 , 3 ), and ML( 5 , 4 ) are connected between switch  5  of Block  1 _ 2  and switch  4  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  300 G of  FIG. 3G  can be implemented as horizontal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 4 , 4 ) and ML( 5 , 36 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 4 , 4 ) and ML( 5 , 36 ) are implemented as a time division multiplexed single track). 
         [0163]    The complete layout for the network  300 B of  FIG. 3B  is given by combining the links in layout diagrams of  300 C,  300 D,  300 E,  300 F, and  300 G. Applicant notes that in the layout  300 C of  FIG. 3C , the inter-block links between switch  1  and switch  2  are vertical tracks as shown in layout  300 D of  FIG. 3D ; the inter-block links between switch  2  and switch  3  are horizontal tracks as shown in layout  300 E of  FIG. 3E ; the inter-block links between switch  3  and switch  4  are vertical tracks as shown in layout  300 F of  FIG. 3F ; and finally the inter-block links between switch  4  and switch  5  are horizontal tracks as shown in layout  300 G of  FIG. 3G . The pattern is either vertical tracks, horizontal tracks or diagonal tracks. It continues recursively for larger networks of N&gt;32 as will be illustrated later. 
         [0164]    Some of the key aspects of the current invention related to layout diagram  300 C of  FIG. 3C  are noted. 1) All the switches in one row of the multi-stage network  300 B are implemented in a single block. 2) The blocks are placed in such a way that all the inter-block links are either horizontal tracks, vertical tracks or diagonal tracks; 3) The length of the longest wire is about half of the width (or length) of the complete layout (For example middle link ML( 4 , 4 ) is about half the width of the complete layout.); 
         [0165]    The layout  300 C in  FIG. 3C  can be recursively extended for any arbitrarily large generalized folded multi link multi-stage network V fold-mlink (N 1 , N 2 , d, s). Referring to layout  300 H of  FIG. 3H , illustrates the extension of layout  300 C for the network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 =128; d=2; and s=2. There are four super-quadrants in layout  300 H namely top-left super-quadrant, bottom-left super-quadrant, top-right super-quadrant, bottom-right super-quadrant. Total number of blocks in the layout  300 H is sixty four. Top-left super-quadrant implements the blocks from block  1 _ 2  to block  31 _ 32 . Each block in all the super-quadrants has two more switches namely switch  6  and switch  7  in addition to the switches [ 1 - 5 ] illustrated in layout  300 C of  FIG. 3C . The inter-block link connection topology is the exactly the same between the switches  1  and  2 ; switches  2  and  3 ; switches  3  and  4 ; switches  4  and  5  as it is shown in the layouts of  FIG. 3D ,  FIG. 3E ,  FIG. 3F , and  FIG. 3G  respectively. 
         [0166]    Bottom-left super-quadrant implements the blocks from block  33 _ 34  to block  63 _ 64 . Top-right super-quadrant implements the blocks from block  65 _ 66  to block  95 _ 96 . And bottom-right super-quadrant implements the blocks from block  97 _ 98  to block  127 _ 128 . In all these three super-quadrants also, the inter-block link connection topology is the exactly the same between the switches  1  and  2 ; switches  2  and  3 ; switches  3  and  4 ; switches  4  and  5  as that of the top-left super-quadrant. 
         [0167]    Recursively in accordance with the current invention, the inter-block links connecting the switch  5  and switch  6  will be vertical tracks between the corresponding switches of top-left super-quadrant and bottom-left super-quadrant. And similarly the inter-block links connecting the switch  5  and switch  6  will be vertical tracks between the corresponding switches of top-right super-quadrant and bottom-right super-quadrant. The inter-block links connecting the switch  6  and switch  7  will be horizontal tracks between the corresponding switches of top-left super-quadrant and top-right super-quadrant. And similarly the inter-block links connecting the switch  6  and switch  7  will be horizontal tracks between the corresponding switches of bottom-left super-quadrant and bottom-right super-quadrant. 
       Ring Topology Layout Schemes: 
       [0168]    Layout diagram  400 C of  FIG. 4C  is another embodiment for the generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) diagram  100 B in  FIG. 1B . 
         [0169]    Referring to layout  400 C of  FIG. 4C , there are sixteen blocks namely Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , Block  7 _ 8 , Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14 , Block  15 _ 16 , Block  17 _ 18 , Block  19 _ 20 , Block  21 _ 22 , Block  23 _ 24 , Block  25 _ 26 , Block  27 _ 28 , Block  29 _ 30 , and Block  31 _ 32 . Each block implements all the switches in one row of the network  100 B of  FIG. 1B , one of the key aspects of the current invention. For example Block  1 _ 2  implements the input switch IS 1 , output Switch OS 1 , middle switch MS( 1 , 1 ), middle switch MS( 7 , 1 ), middle switch MS( 2 , 1 ), middle switch MS( 6 , 1 ), middle switch MS( 3 , 1 ), middle switch MS( 5 , 1 ), and middle switch MS( 4 , 1 ). For the simplification of illustration, Input switch IS 1  and output switch OS 1  together are denoted as switch  1 ; Middle switch MS( 1 , 1 ) and middle switch MS( 7 , 1 ) together are denoted by switch  2 ; Middle switch MS( 2 , 1 ) and middle switch MS( 6 , 1 ) together are denoted by switch  3 ; Middle switch MS( 3 , 1 ) and middle switch MS( 5 , 1 ) together are denoted by switch  4 ; And middle switch MS( 4 , 1 ) is denoted by switch  5 . 
         [0170]    All the straight middle links are illustrated in layout  400 C of  FIG. 4C . For example in Block  1 _ 2 , inlet links IL 1 -IL 2 , outlet links OL 1 -OL 2 , middle link ML( 1 , 1 ), middle link ML( 1 , 2 ), middle link ML( 8 , 1 ), middle link ML( 8 , 2 ), middle link ML( 2 , 1 ), middle link ML( 2 , 2 ), middle link ML( 7 , 1 ), middle link ML( 7 , 2 ), middle link ML( 3 , 1 ), middle link ML( 3 , 2 ), middle link ML( 6 , 1 ), middle link ML( 6 , 2 ), middle link ML( 4 , 1 ), middle link ML( 4 , 2 ), middle link ML( 5 , 1 ) and middle link ML( 5 , 2 ) are illustrated in layout  400 C of  FIG. 4C . 
         [0171]    Even though it is not illustrated in layout  400 C of  FIG. 4C , in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit or sub-integrated circuit block depending on the applications in different embodiments. The topology of the layout  400 C in  FIG. 4C  is a ring. For each of the neighboring rows in diagram  100 B of  FIG. 1B  the corresponding blocks are also physically neighbors in layout diagram  400 C of  FIG. 4C . In addition the topmost row is also logically considered as neighbor to the bottommost row. For example Block  1 _ 2  (implementing the switches belonging to a row in diagram  100 B of  FIG. 1B ) has Block  3 _ 4  as neighbor since Block  3 _ 4  implements the switches in its neighboring row. Similarly Block  1 _ 2  also has Block  31 _ 32  as neighbor since Block  1 _ 2  implements topmost row of switches and Block  31 _ 32  implements bottommost row of switches in diagram  100 B of  FIG. 1B . The ring layout scheme illustrated in  400 C of  FIG. 4C  can be generalized for a large multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 &gt;32, in accordance with the current invention. 
         [0172]    Layout  400 B of  FIG. 4B  illustrates the inter-block links (in the layout  400 A of  FIG. 4A  all the cross middle links are inter-block links) between switches  1  and  2  of each block. For example middle links ML( 1 , 3 ), ML( 1 , 4 ), ML( 8 , 7 ), and ML( 8 , 8 ) are connected between switch  1  of Block  1 _ 2  and switch  2  of Block  3 _ 4 . Similarly middle links ML( 1 , 7 ), ML( 1 , 8 ), ML( 8 , 3 ), and ML( 8 , 4 ) are connected between switch  2  of Block  1 _ 2  and switch  1  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  400 B of  FIG. 4B  are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 1 , 4 ) and ML( 8 , 8 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 1 , 4 ) and ML( 8 , 8 ) are implemented as a time division multiplexed single track). 
         [0173]    Layout  400 C of  FIG. 4C  illustrates the inter-block links between switches  2  and  3  of each block. For example middle links ML( 2 , 3 ), ML( 2 , 4 ), ML( 7 , 11 ), and ML( 7 , 12 ) are connected between switch  2  of Block  1 _ 2  and switch  3  of Block  3 _ 4 . Similarly middle links ML( 2 , 11 ), ML( 2 , 12 ), ML( 7 , 3 ), and ML( 7 , 4 ) are connected between switch  3  of Block  1 _ 2  and switch  2  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  400 C of  FIG. 4C  are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 2 , 12 ) and ML( 7 , 4 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 2 , 12 ) and ML( 7 , 4 ) are implemented as a time division multiplexed single track). 
         [0174]    Layout  400 D of  FIG. 4D  illustrates the inter-block links between switches  3  and  4  of each block. For example middle links ML( 3 , 3 ), ML( 3 , 4 ), ML( 6 , 19 ), and ML( 6 , 20 ) are connected between switch  3  of Block  1 _ 2  and switch  4  of Block  3 _ 4 . Similarly middle links ML( 3 , 19 ), ML( 3 , 20 ), ML( 6 , 3 ), and ML( 6 , 4 ) are connected between switch  4  of Block  1 _ 2  and switch  3  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  400 D of  FIG. 4D  are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 3 , 4 ) and ML( 6 , 20 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 3 , 4 ) and ML( 6 , 20 ) are implemented as a time division multiplexed single track). 
         [0175]    Layout  400 E of  FIG. 4E  illustrates the inter-block links between switches  4  and  5  of each block. For example middle links ML( 4 , 3 ), ML( 4 , 4 ), ML( 5 , 35 ), and ML( 5 , 36 ) are connected between switch  4  of Block  1 _ 2  and switch  5  of Block  3 _ 4 . Similarly middle links ML( 4 , 35 ), ML( 4 , 36 ), ML( 5 , 3 ), and ML( 5 , 4 ) are connected between switch  5  of Block  1 _ 2  and switch  4  of Block  3 _ 4 . Applicant notes that the inter-block links illustrated in layout  400 E of  FIG. 4E  are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML( 4 , 4 ) and ML( 5 , 36 ) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML( 4 , 4 ) and ML( 5 , 36 ) are implemented as a time division multiplexed single track). 
         [0176]    The complete layout for the network  100 B of  FIG. 1B  is given by combining the links in layout diagrams of  400 A,  400 B,  400 C,  400 D, and  400 E. 
         [0177]    Some of the key aspects of the current invention related to layout diagram  400 A of  FIG. 4A  are noted. 1) All the switches in one row of the multi-stage network  100 B are implemented in a single block. 2) The blocks are placed in such a way that all the inter-block links are either horizontal tracks, vertical tracks or diagonal tracks; 3) Length of the different wires between the same two middle stages is not the same. However it gives an opportunity to implement the most connected circuits to place and route through the blocks which have shorter wires. 
         [0178]    Layout diagram  400 C 1  of FIG.  4 C 1  is another embodiment for the generalized folded multi-link multi-stage network V fold-mlink (N 1 , N 2 , d, s) diagram  100 B in  FIG. 1B . Referring to layout  400 C 1  of FIG.  4 C 1 , there are sixteen blocks namely Block  1 _ 2 , Block  3 _ 4 , Block  5 _ 6 , Block  7 _ 8 , Block  9 _ 10 , Block  11 _ 12 , Block  13 _ 14 , Block  15 _ 16 , Block  17 _ 18 , Block  19 _ 20 , Block  21 _ 22 , Block  23 _ 24 , Block  25 _ 26 , Block  27 _ 28 , Block  29 _ 30 , and Block  31 _ 32 . Each block implements all the switches in one row of the network  100 B of  FIG. 1B , one of the key aspects of the current invention. For example Block  1 _ 2  implements the input switch IS 1 , output Switch OS 1 , middle switch MS( 1 , 1 ), middle switch MS( 7 , 1 ), middle switch MS( 2 , 1 ), middle switch MS( 6 , 1 ), middle switch MS( 3 , 1 ), middle switch MS( 5 , 1 ), and middle switch MS( 4 , 1 ). For the simplification of illustration, Input switch IS 1  and output switch OS 1  together are denoted as switch  1 ; Middle switch MS( 1 , 1 ) and middle switch MS( 7 , 1 ) together are denoted by switch  2 ; Middle switch MS( 2 , 1 ) and middle switch MS( 6 , 1 ) together are denoted by switch  3 ; Middle switch MS( 3 , 1 ) and middle switch MS( 5 , 1 ) together are denoted by switch  4 ; And middle switch MS( 4 , 1 ) is denoted by switch  5 . 
         [0179]    All the straight middle links are illustrated in layout  400 C 1  of FIG.  4 C 1 . For example in Block  1 _ 2 , inlet links IL 1 -IL 2 , outlet links OL 1 -OL 2 , middle link ML( 1 , 1 ), middle link ML( 1 , 2 ), middle link ML( 8 , 1 ), middle link ML( 8 , 2 ), middle link ML( 2 , 1 ), middle link ML( 2 , 2 ), middle link ML( 7 , 1 ), middle link ML( 7 , 2 ), middle link ML( 3 , 1 ), middle link ML( 3 , 2 ), middle link ML( 6 , 1 ), middle link ML( 6 , 2 ), middle link ML( 4 , 1 ), middle link ML( 4 , 2 ), middle link ML( 5 , 1 ) and middle link ML( 5 , 2 ) are illustrated in layout  400 C 1  of FIG.  4 C 1 . 
         [0180]    Even though it is not illustrated in layout  400 C 1  of FIG.  4 C 1 , in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit or sub-integrated circuit block depending on the applications in different embodiments. The topology of the layout  400 C 1  in FIG.  4 C 1  is another embodiment of ring layout topology. For each of the neighboring rows in diagram  100 B of  FIG. 1B  the corresponding blocks are also physically neighbors in layout diagram  400 C of  FIG. 4C . In addition the topmost row is also logically considered as neighbor to the bottommost row. For example Block  1 _ 2  (implementing the switches belonging to a row in diagram  100 B of  FIG. 1B ) has Block  3 _ 4  as neighbor since Block  3 _ 4  implements the switches in its neighboring row. Similarly Block  1 _ 2  also has Block  31 _ 32  as neighbor since Block  1 _ 2  implements topmost row of switches and Block  31 _ 32  implements bottommost row of switches in diagram  100 B of  FIG. 1B . The ring layout scheme illustrated in  400 C of  FIG. 4C  can be generalized for a large multi-stage network V fold-mlink (N 1 , N 2 , d, s) where N 1 =N 2 &gt;32, in accordance with the current invention. 
         [0181]    All the layout embodiments disclosed in the current invention are applicable to generalized multi-stage networks V(N 1 , N 2 , d, s), generalized folded multi-stage networks V fold (N 1 , N 2 , d, s), generalized butterfly fat tree networks V bft (N 1 , N 2 , d, s), generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s), generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s), generalized multi-link butterfly fat tree networks V mlink-bft (N 1 , N 2 , d, s), and generalized hypercube networks V hcube (N 1 , N 2 , d, s) for s=1, 2, 3 or any number in general, and for both N 1 =N=N and N 1 ≠N 2 , and d is any integer. 
         [0182]    Conversely applicant makes another important observation that generalized hypercube networks V hcube (N 1 , N 2 , d, s) are implemented with the layout topology being the hypercube topology shown in layout  100 C of  FIG. 1C  with large scale cross point reduction as any one of the networks described in the current invention namely: generalized multi-stage networks V(N 1 , N 2 , d, s), generalized folded multi-stage networks V fold (N 1 , N 2 , d, s), generalized butterfly fat tree networks V bft (N 1 , N 2 , d, s), generalized multi-link multi-stage networks V mlink (N 1 , N 2 , d, s), generalized folded multi-link multi-stage networks V fold-mlink (N 1 , N 2 , d, s), generalized multi-link butterfly fat tree networks V mlink-bft (N 1 , N 2 , d, s) for s=1, 2, 3 or any number in general, and for both N 1 =N 2 =N and N 1 ≠N 2 , and d is any integer. 
       Applications Embodiments 
       [0183]    All the embodiments disclosed in the current invention are useful in many varieties of applications. FIG.  5 A 1  illustrates the diagram of  500 A 1  which is a typical two by two switch with two inlet links namely IL 1  and IL 2 , and two outlet links namely OL 1  and OL 2 . The two by two switch also implements four crosspoints namely CP( 1 , 1 ), CP( 1 , 2 ), CP( 2 , 1 ) and CP( 2 , 2 ) as illustrated in FIG.  5 A 1 . For example the diagram of  500 A 1  may the implementation of middle switch MS( 1 , 1 ) of the diagram  100 K of  FIG. 1K  where inlet link IL 1  of diagram  500 A 1  corresponds to middle link ML( 1 , 1 ) of diagram  100 K, inlet link IL 2  of diagram  500 A 1  corresponds to middle link ML( 1 , 7 ) of diagram  100 K, outlet link OL 1  of diagram  500 A 1  corresponds to middle link ML( 2 , 1 ) of diagram  100 K, outlet link OL 2  of diagram  500 A 1  corresponds to middle link ML( 2 , 3 ) of diagram  100 K. 
       1) Programmable Integrated Circuit Embodiments 
       [0184]    All the embodiments disclosed in the current invention are useful in programmable integrated circuit applications. FIG.  5 A 2  illustrates the detailed diagram  500 A 2  for the implementation of the diagram  500 A 1  in programmable integrated circuit embodiments. Each crosspoint is implemented by a transistor coupled between the corresponding inlet link and outlet link, and a programmable cell in programmable integrated circuit embodiments. Specifically crosspoint CP( 1 , 1 ) is implemented by transistor C( 1 , 1 ) coupled between inlet link IL 1  and outlet link OL 1 , and programmable cell P( 1 , 1 ); crosspoint CP( 1 , 2 ) is implemented by transistor C( 1 , 2 ) coupled between inlet link IL 1  and outlet link OL 2 , and programmable cell P( 1 , 2 ); crosspoint CP( 2 , 1 ) is implemented by transistor C( 2 , 1 ) coupled between inlet link IL 2  and outlet link OL 1 , and programmable cell P( 2 , 1 ); and crosspoint CP( 2 , 2 ) is implemented by transistor C( 2 , 2 ) coupled between inlet link IL 2  and outlet link OL 2 , and programmable cell P( 2 , 2 ). 
         [0185]    If the programmable cell is programmed ON, the corresponding transistor couples the corresponding inlet link and outlet link. If the programmable cell is programmed OFF, the corresponding inlet link and outlet link are not connected. For example if the programmable cell P( 1 , 1 ) is programmed ON, the corresponding transistor C( 1 , 1 ) couples the corresponding inlet link IL 1  and outlet link OL 1 . If the programmable cell P( 1 , 1 ) is programmed OFF, the corresponding inlet link IL 1  and outlet link OL 1  are not connected. In volatile programmable integrated circuit embodiments the programmable cell may be an SRAM (Static Random Address Memory) cell. In non-volatile programmable integrated circuit embodiments the programmable cell may be a Flash memory cell. Also the programmable integrated circuit embodiments may implement field programmable logic arrays (FPGA) devices, or programmable Logic devices (PLD), or Application Specific Integrated Circuits (ASIC) embedded with programmable logic circuits or 3D-FPGAs. 
         [0186]    FIG.  5 A 2  also illustrates a buffer B 1  on inlet link IL 2 . The signals driven along inlet link IL 2  are amplified by buffer B 1 . Buffer B 1  can be inverting or non-inverting buffer. Buffers such as B 1  are used to amplify the signal in links which are usually long. 
       2) One-Time Programmable Integrated Circuit Embodiments 
       [0187]    All the embodiments disclosed in the current invention are useful in one-time programmable integrated circuit applications. FIG.  5 A 3  illustrates the detailed diagram  500 A 3  for the implementation of the diagram  500 A 1  in one-time programmable integrated circuit embodiments. Each crosspoint is implemented by a via coupled between the corresponding inlet link and outlet link in one-time programmable integrated circuit embodiments. Specifically crosspoint CP( 1 , 1 ) is implemented by via V( 1 , 1 ) coupled between inlet link IL 1  and outlet link OL 1 ; crosspoint CP( 1 , 2 ) is implemented by via V( 1 , 2 ) coupled between inlet link IL 1  and outlet link OL 2 ; crosspoint CP( 2 , 1 ) is implemented by via V( 2 , 1 ) coupled between inlet link IL 2  and outlet link OL 1 ; and crosspoint CP( 2 , 2 ) is implemented by via V( 2 , 2 ) coupled between inlet link IL 2  and outlet link OL 2 . 
         [0188]    If the via is programmed ON, the corresponding inlet link and outlet link are permanently connected which is denoted by thick circle at the intersection of inlet link and outlet link. If the via is programmed OFF, the corresponding inlet link and outlet link are not connected which is denoted by the absence of thick circle at the intersection of inlet link and outlet link For example in the diagram  500 A 3  the via V( 1 , 1 ) is programmed ON, and the corresponding inlet link IL 1  and outlet link OL 1  are connected as denoted by thick circle at the intersection of inlet link IL 1  and outlet link OL 1 ; the via V( 2 , 2 ) is programmed ON, and the corresponding inlet link IL 2  and outlet link OL 2  are connected as denoted by thick circle at the intersection of inlet link IL 2  and outlet link OL 2 ; the via V( 1 , 2 ) is programmed OFF, and the corresponding inlet link IL 1  and outlet link OL 2  are not connected as denoted by the absence of thick circle at the intersection of inlet link IL 1  and outlet link OL 2 ; the via V( 2 , 1 ) is programmed OFF, and the corresponding inlet link IL 2  and outlet link OL 1  are not connected as denoted by the absence of thick circle at the intersection of inlet link IL 2  and outlet link OL 1 . One-time programmable integrated circuit embodiments may be anti-fuse based programmable integrated circuit devices or mask programmable structured ASIC devices. 
       3) Integrated Circuit Placement and Route Embodiments 
       [0189]    All the embodiments disclosed in the current invention are useful in Integrated Circuit Placement and Route applications, for example in ASIC backend Placement and Route tools. FIG.  5 A 4  illustrates the detailed diagram  500 A 4  for the implementation of the diagram  500 A 1  in Integrated Circuit Placement and Route embodiments. In an integrated circuit since the connections are known a-priori, the switch and crosspoints are actually virtual. However the concept of virtual switch and virtual crosspoint using the embodiments disclosed in the current invention reduces the number of required wires, wire length needed to connect the inputs and outputs of different netlists and the time required by the tool for placement and route of netlists in the integrated circuit. 
         [0190]    Each virtual crosspoint is used to either to hardwire or provide no connectivity between the corresponding inlet link and outlet link. Specifically crosspoint CP( 1 , 1 ) is implemented by direct connect point DCP( 1 , 1 ) to hardwire (i.e., to permanently connect) inlet link IL 1  and outlet link OL 1  which is denoted by the thick circle at the intersection of inlet link IL 1  and outlet link OL 1 ; crosspoint CP( 2 , 2 ) is implemented by direct connect point DCP( 2 , 2 ) to hardwire inlet link IL 2  and outlet link OL 2  which is denoted by the thick circle at the intersection of inlet link IL 2  and outlet link OL 2 . The diagram  500 A 4  does not show direct connect point DCP( 1 , 2 ) and direct connect point DCP( 1 , 3 ) since they are not needed and in the hardware implementation they are eliminated. Alternatively inlet link IL 1  needs to be connected to outlet link OL 1  and inlet link IL 1  does not need to be connected to outlet link OL 2 . Also inlet link IL 2  needs to be connected to outlet link OL 2  and inlet link IL 2  does not need to be connected to outlet link OL 1 . Furthermore in the example of the diagram  500 A 4 , there is no need to drive the signal of inlet link IL 1  horizontally beyond outlet link OL 1  and hence the inlet link IL 1  is not even extended horizontally until the outlet link OL 2 . Also the absence of direct connect point DCP( 2 , 1 ) illustrates there is no need to connect inlet link IL 2  and outlet link OL 1 . 
         [0191]    In summary in integrated circuit placement and route tools, the concept of virtual switches and virtual cross points is used during the implementation of the placement &amp; routing algorithmically in software, however during the hardware implementation cross points in the cross state are implemented as hardwired connections between the corresponding inlet link and outlet link, and in the bar state are implemented as no connection between inlet link and outlet link. 3) More Application Embodiments: 
         [0192]    All the embodiments disclosed in the current invention are also useful in the design of SoC interconnects, Field programmable interconnect chips, parallel computer systems and in time-space-time switches. 
         [0193]    Numerous modifications and adaptations of the embodiments, implementations, and examples described herein will be apparent to the skilled artisan in view of the disclosure.