Abstract:
The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.

Description:
TECHNICAL FIELD 
     The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable. 
     BACKGROUND OF THE INVENTION 
     Non-volatile memory cells are well known in the art. A first type of prior art non-volatile memory cell  110  is shown in  FIG. 1 . The memory cell  110  comprises a semiconductor substrate  112  of a first conductivity type, such as P type. The substrate  112  has a surface on which there is formed a first region  114  (also known as the source line SL) of a second conductivity type, such as N type. A second region  116  (also known as the drain line) also of N type is formed on the surface of the substrate  112 . Between the first region  114  and the second region  116  is a channel region  118 . A bit line BL  120  is connected to the second region  116 . A word line WL  122  is positioned above a first portion of the channel region  118  and is insulated therefrom. The word line  122  has little or no overlap with the second region  116 . A floating gate FG  124  is over another portion of the channel region  118 . The floating gate  124  is insulated therefrom, and is adjacent to the word line  122 . The floating gate  124  is also adjacent to the first region  114 . The floating gate  124  may overlap the first region  114  significantly to provide strong coupling from the region  114  into the floating gate  124 . 
     One exemplary operation for erase and program of prior art non-volatile memory cell  110  is as follows. The cell  110  is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line  122  and zero volts to the bit line and source line. Electrons tunnel from the floating gate  124  into the word line  122  causing the floating gate  124  to be positively charged, turning on the cell  110  in a read condition. The resulting cell erased state is known as ‘1’ state. The cell  110  is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the source line  114 , a small voltage on the word line  122 , and a programming current on the bit line  120 . A portion of electrons flowing across the gap between the word line  122  and the floating gate  124  acquire enough energy to inject into the floating gate  124  causing the floating gate  124  to be negatively charged, turning off the cell  110  in read condition. The resulting cell programmed state is known as ‘0’ state. 
     Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell  110  is shown below in Table 1: 
     
       
         
               
               
               
               
               
             
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Operation 
                 WL 
                 BL 
                 SL 
               
               
                   
                   
               
             
             
               
                   
                 Read 
                 Vwlrd 
                 Vblrd 
                 0 V 
               
               
                   
                 Program 
                 Vwlp 
                 Iprog/Vinh (unsel) 
                 Vslp 
               
               
                   
                 Erase 
                 Vwler 
                 0 V 
                 0 V 
               
               
                   
                 Standby 
                 0 V 
                 0 V 
                 0 V 
               
               
                   
                   
               
             
          
           
               
                   
                 Vwlrd ~2-3 V 
               
               
                   
                 Vblrd ~0.8-2 V 
               
               
                   
                 Vwlp ~1-2 V 
               
               
                   
                 Vwler ~11-13 V 
               
               
                   
                 Vslp ~9-10 V 
               
               
                   
                 Iprog ~1-3 ua 
               
               
                   
                 Vinh ~2 V 
               
               
                   
                   
               
             
          
         
       
     
     A second type of prior art non-volatile memory cell  210  is shown in  FIG. 2 . The memory cell  210  comprises a semiconductor substrate  212  of a first conductivity type, such as P type. The substrate  212  has a surface on which there is formed a first region  214  (also known as the source line SL) of a second conductivity type, such as N type. A second region  216  (also known as the drain line) also of N type is formed on the surface of the substrate  212 . Between the first region  214  and the second region  216  is a channel region  218 . A bit line BL  220  is connected to the second region  216 . A word line WL  222  is positioned above a first portion of the channel region  218  and is insulated therefrom. The word line  222  has little or no overlap with the second region  216 . A floating gate FG  224  is over another portion of the channel region  218 . The floating gate  224  is insulated therefrom, and is adjacent to the word line  222 . The floating gate  224  is also adjacent to the first region  214 . The floating gate  224  may overlap the first region  214  to provide coupling from the region  214  into the floating gate  224 . A coupling gate CG (also known as control gate)  226  is over the floating gate  224  and is insulated therefrom. 
     One exemplary operation for erase and program of prior art non-volatile memory cell  210  is as follows. The cell  210  is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line  222  with other terminals equal to zero volt. Electrons tunnel from the floating gate  224  into the word line  222  to be positively charged, turning on the cell  210  in a read condition. The resulting cell erased state is known as ‘1’ state. The cell  210  is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate  226 , a high voltage on the source line  214 , and a programming current on the bit line  220 . A portion of electrons flowing across the gap between the word line  222  and the floating gate  224  acquire enough energy to inject into the floating gate  224  causing the floating gate  224  to be negatively charged, turning off the cell  210  in read condition. The resulting cell programmed state is known as ‘0’ state. 
     Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell  210  is shown below in Table 2: 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG-un- 
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 select 
                   
                   
                   
               
               
                   
                   
                 WL-un- 
                   
                 BL-un- 
                   
                 same 
                 CG-un- 
                   
                 SL-un- 
               
               
                 Operation 
                 WL 
                 select 
                 BL 
                 select 
                 CG 
                 sector 
                 select 
                 SL 
                 select 
               
               
                   
               
             
             
               
                 Read 
                 1.0- 
                 0 V 
                 0.6- 
                 0 V 
                 0- 
                 0- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                 3 V 
                   
                 2 V 
                   
                 2.6 V 
                 2.6 V 
                 2.6 V 
                   
                   
               
               
                 Erase 
                 11- 
                 0 V 
                 0 V 
                 0 V  
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
               
               
                   
                 10 V 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 Program 
                 1 V 
                 0 V 
                 1 uA 
                 Vinh 
                 8- 
                 0- 
                 0- 
                 4.5- 
                 0-1 V 
               
               
                   
                   
                   
                   
                   
                 11 V 
                 2.6 V 
                 2.6 V 
                 5 V 
               
               
                   
               
             
          
         
       
     
     Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell  210  is shown below in Table 3: 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unselect 
                   
                   
                   
               
               
                   
                   
                 WL- 
                   
                 BL- 
                   
                 same 
                 CG- 
                   
                 SL- 
               
               
                 Operation 
                 WL 
                 unselect 
                 BL 
                 unselect 
                 CG 
                 sector 
                 unselect 
                 SL 
                 unselect 
               
               
                   
               
             
             
               
                 Read 
                 1.0- 
                 −0.5 V/ 
                 0.6- 
                 0 V 
                 0- 
                 0- 
                 0-2.6 V 
                 0 V 
                 0 V 
               
               
                   
                 2 V 
                 0 V 
                 2 V 
                   
                 2.6 V 
                 2.6 V 
                   
                   
                   
               
               
                 Erase 
                 11- 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
               
               
                   
                 10 V 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 Program 
                 1 V 
                 −0.5 V/ 
                 1 uA 
                 Vinh 
                 8- 
                 0- 
                 0- 
                 4.5- 
                 0-1 V 
               
               
                   
                   
                 0 V 
                   
                   
                 11 V 
                 2.6 V 
                 2.6 V 
                 5 V 
               
               
                   
               
             
          
         
       
     
     Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell  210  is shown below in Table 4: 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 4 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unselect 
                   
                   
                   
               
               
                   
                   
                 WL- 
                   
                 BL- 
                   
                 same 
                 CG- 
                   
                 SL- 
               
               
                 Operation 
                 WL 
                 unselect 
                 BL 
                 unselect 
                 CG 
                 sector 
                 unselect 
                 SL 
                 unselect 
               
               
                   
               
             
             
               
                 Read 
                 1.0- 
                 −0.5 V/ 
                 0.6- 
                 0 V 
                 0- 
                 0- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                 2 V 
                 0 V 
                 2 V 
                   
                 2.6 V 
                 2.6 V 
                 2.6 V 
                   
                   
               
               
                 Erase 
                 9- 
                 −0.5 V/ 
                 0 V 
                 0 V 
                 −(5- 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
               
               
                   
                 6 V 
                 0 V 
                   
                   
                 9) V 
                   
                   
                   
                   
               
               
                 Program 
                 1 V 
                 −0.5 V/ 
                 1 uA 
                 Vinh 
                 8- 
                 0- 
                 0- 
                 4.5- 
                 0- 
               
               
                   
                   
                 0 V 
                   
                   
                 9 V 
                 2.6 V 
                 2.6 V 
                 5 V 
                 1 V 
               
               
                   
               
             
          
         
       
     
     A third type of non-volatile memory cell  310  is shown in  FIG. 3 . The memory cell  310  comprises a semiconductor substrate  312  of a first conductivity type, such as P type. The substrate  312  has a surface on which there is formed a first region  314  (also known as the source line SL) of a second conductivity type, such as N type. A second region  316  (also known as the drain line) also of N type is formed on the surface of the substrate  312 . Between the first region  314  and the second region  316  is a channel region  318 . A bit line BL  320  is connected to the second region  316 . A word line WL  322  is positioned above a first portion of the channel region  318  and is insulated therefrom. The word line  322  has little or no overlap with the second region  316 . A floating gate FG  324  is over another portion of the channel region  318 . The floating gate  324  is insulated therefrom, and is adjacent to the word line  322 . The floating gate  324  is also adjacent to the first region  314 . The floating gate  324  may overlap the first region  314  to provide coupling from the region  314  into the floating gate  324 . A coupling gate CG (also known as control gate)  326  is over the floating gate  324  and is insulated therefrom. An erase gate EG  328  is over the first region  314  and is adjacent to the floating gate  324  and the coupling gate  326  and is insulated therefrom. The top corner of the floating gate  324  may point toward the inside corner of the T-shaped erase gate  328  to enhance erase efficiency. The erase gate  328  is also insulated from the first region  314 . The cell  310  is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety. 
     One exemplary operation for erase and program of prior art non-volatile memory cell  310  is as follows. The cell  310  is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate  328  with other terminals equal to zero volt. Electrons tunnel from the floating gate  324  into the erase gate  328  causing the floating gate  324  to be positively charged, turning on the cell  310  in a read condition. The resulting cell erased state is known as ‘1’ state. The cell  310  is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate  326 , a high voltage on the source line  314 , a medium voltage on the erase gate  328 , and a programming current on the bit line  320 . A portion of electrons flowing across the gap between the word line  322  and the floating gate  324  acquire enough energy to inject into the floating gate  324  causing the floating gate  324  to be negatively charged, turning off the cell  310  in read condition. The resulting cell programmed state is known as ‘0’ state. 
     Exemplary voltages that can be used for the read, program, and erase operations in memory cell  310  is shown below in Table 5: 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 5 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unsel 
                   
                   
                   
                   
                   
               
               
                   
                   
                 WL- 
                   
                 BL- 
                   
                 same 
                 CG- 
                   
                 EG- 
                   
                 SL- 
               
               
                 Operation 
                 WL 
                 unsel 
                 BL 
                 unsel 
                 CG 
                 sector 
                 unselect 
                 EG 
                 unsel 
                 SL 
                 unsel 
               
               
                   
               
             
             
               
                 Read 
                 1.0- 
                 0 V 
                 0.6- 
                 0 V 
                 0- 
                 0- 
                 0- 
                 0- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                 2 V 
                   
                 2 V 
                   
                 2.6 V 
                 2.6 V 
                 2.6 V 
                 2.6 V 
                 2.6 V 
                   
                   
               
               
                 Erase 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 11.5- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                   
                   
                   
                   
                   
                   
                   
                 12 V 
                 2.6 V 
                   
                   
               
               
                 Program 
                 1 V 
                 0 V 
                 1 uA 
                 Vinh 
                 10- 
                 0- 
                 0- 
                 4.5- 
                 0- 
                 4.5- 
                 0- 
               
               
                   
                   
                   
                   
                   
                 11 V 
                 5 V 
                 2.6 V 
                 8 V 
                 2.6 V 
                 5 V 
                 1 V 
               
               
                   
               
             
          
         
       
     
     For programming operation, the EG voltage can be applied much higher, e.g. 8V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 6V, to reduce unwanted erase effect of the adjacent memory cells sharing the same EG gate of the selected memory cells. 
     Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell  310  is shown below in Table 6: 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 6 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unsel 
                   
                   
                   
                   
                   
               
               
                   
                   
                 WL- 
                   
                 BL- 
                   
                 same 
                 CG- 
                   
                 EG- 
                   
                 SL- 
               
               
                 Operation 
                 WL 
                 unsel 
                 BL 
                 unsel 
                 CG 
                 sector 
                 unselect 
                 EG 
                 unsel 
                 SL 
                 unsel 
               
               
                   
               
             
             
               
                 Read 
                 1.0- 
                 −0.5 V/ 
                 0.6- 
                 0 V 
                 0- 
                 0- 
                 0- 
                 0- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                 2 V 
                 0 V 
                 2 V 
                   
                 2.6 V 
                 2.6 V 
                 2.6 V 
                 2.6 V 
                 2.6 V 
                   
                   
               
               
                 Erase 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 0 V 
                 11.5- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                   
                   
                   
                   
                   
                   
                   
                 12 V 
                 2.6 V 
                   
                   
               
               
                 Program 
                 1 V 
                 −0.5 V/ 
                 1 uA 
                 Vinh 
                 10- 
                 0- 
                 0- 
                 4.5- 
                 0- 
                 4.5- 
                 0- 
               
               
                   
                   
                 0 V 
                   
                   
                 11 V 
                 2.6 V 
                 2.6 V 
                 5 V 
                 2.6 V 
                 5 V 
                 1 V 
               
               
                   
               
             
          
         
       
     
     Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell  310  is shown below in Table 7: 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 7 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                 CG- 
                   
                   
                   
                   
                   
               
               
                   
                   
                   
                   
                   
                   
                 unsel 
                   
                   
                   
                   
                   
               
               
                   
                   
                 WL- 
                   
                 BL- 
                   
                 same 
                 CG- 
                   
                 EG- 
                   
                 SL- 
               
               
                 Operation 
                 WL 
                 unsel 
                 BL 
                 unsel 
                 CG 
                 sector 
                 unselect 
                 EG 
                 unsel 
                 SL 
                 unsel 
               
               
                   
               
             
             
               
                 Read 
                 1.0- 
                 −0.5 V/ 
                 0.6- 
                 0 V 
                 0- 
                 0- 
                 0- 
                 0- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                 2 V 
                 0 V 
                 2 V 
                   
                 2.6 V 
                 2.6 V 
                 2.6 V 
                 2.6 V 
                 2.6 V 
                   
                   
               
               
                 Erase 
                 0 V 
                 −0.5 V/ 
                 0 V 
                 0 V 
                 −(5- 
                 0 V 
                 0 V 
                 9- 
                 0- 
                 0 V 
                 0 V 
               
               
                   
                   
                 0 V 
                   
                   
                 9) V 
                   
                   
                 8 V 
                 2.6 V 
                   
                   
               
               
                 Program 
                 1 V 
                 −0.5 V/ 
                 1 uA 
                 Vinh 
                 8- 
                 0- 
                 0- 
                 8- 
                 0- 
                 4.5- 
                 0- 
               
               
                   
                   
                 0 V 
                   
                   
                 9 V 
                 5 V 
                 2.6 V 
                 9 V 
                 2.6 V 
                 5 V 
                 1 V 
               
               
                   
               
             
          
         
       
     
     For programming operation, the EG voltage is applied much higher, e.g. 8-9V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 5V, to reduce unwanted erase effects of the adjacent memory cells sharing the same EG gate of the selected memory cells. 
     Memory cells of the types shown in  FIGS. 1-3  typically are arranged into rows and columns to form an array. Erase operations are performed on entire rows or pairs of rows at one time, since word lines control entire rows of memory cells and erase gates (of the type shown in  FIG. 3 ), when present, are shared by pairs of rows of memory cells. Thus, in prior art memory systems using memory cells of the types shown in  FIGS. 1-3 , it has not been possible to erase only one byte of data or one byte pair of data at a time. 
     Also known in the prior art are electrically erasable programmable read only memory (EEPROM) devices. As with the flash memory cells of  FIGS. 1-3 , EEPROM devices are non-volatile memory devices. However, in an EEPROM device, cells can be erased one byte at a time, unlike in the systems utilizing the memory cells of  FIGS. 1-3 . EEPROM cell size is typically much larger than flash memory cell size. 
     What is needed is a flash memory device that can be erased on a byte-by-byte basis, similar to what is possible in EEPROM devices. Advantages includes flash memory functionality (such as high density memory with a sector erasable feature) and EEPROM functionality (low density memory with a byte erasable feature) exists on same process. 
     SUMMARY OF THE INVENTION 
     In the embodiments described below, flash memory arrays can be erased on a byte-by-byte basis. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a non-volatile memory cell of the prior art to which the method of the present invention can be applied. 
         FIG. 2  is a cross-sectional view of a non-volatile memory cell of the prior art to which the method of the present invention can be applied. 
         FIG. 3  is a cross-sectional view of a non-volatile memory cell of the prior art to which the method of the present invention can be applied. 
         FIG. 4  is a layout diagram of a memory device comprising non-volatile memory cells of the type shown in  FIGS. 1-3 . 
         FIG. 5  depicts an embodiment of a flash memory circuit. 
         FIG. 6  is a layout diagram of an embodiment of a flash memory circuit. 
         FIG. 7  depicts an embodiment of a flash memory circuit. 
         FIG. 8  depicts an embodiment of a flash memory circuit. 
         FIG. 9  depicts an embodiment of a flash memory circuit. 
         FIG. 10  depicts an embodiment of a flash memory circuit. 
         FIG. 11  depicts an embodiment of a flash memory circuit. 
         FIG. 12  depicts an embodiment of a flash memory circuit. 
         FIG. 13  depicts an embodiment of a flash memory circuit. 
         FIG. 14  depicts an embodiment of a flash memory circuit. 
         FIG. 15  depicts an embodiment of a flash memory circuit. 
         FIG. 16  depicts an embodiment of a flash memory circuit. 
         FIG. 17  is a layout diagram of an embodiment of a flash memory circuit. 
         FIG. 18  depicts an embodiment of a flash memory circuit. 
         FIG. 19  depicts an embodiment of a flash memory circuit. 
         FIG. 20  depicts an embodiment of a flash memory circuit. 
         FIG. 21  depicts an embodiment of a flash memory circuit. 
         FIG. 22  depicts an embodiment of a flash memory circuit. 
         FIG. 23  is a layout diagram of an embodiment of a flash memory circuit. 
         FIG. 24  depicts an embodiment of a flash memory circuit. 
         FIG. 25  depicts an embodiment of a flash memory circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       FIG. 4  depicts an embodiment of an architecture for a two-dimensional flash SFEE memory system. Die  400  comprises: memory array  15  and memory array  20  for storing data, the memory array optionally utilizing memory cell  110  as in  FIG. 1 , memory cell  210  as in  FIG. 2 , or memory cell  310  as in  FIG. 3 , pad  35  and pad  80  for enabling electrical communication between the other components of die  400  and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip or macro interface pins (not shown) for interconnecting to other macros on a SOC (system on chip); high voltage circuit  75  used to provide positive and negative voltage supplies for the system; control logic  70  for providing various control functions, such as redundancy and built-in self-testing; analog circuit  65 ; sensing circuits  60  and  61  used to read data from memory array  15  and memory array  20 , respectively; row decoder circuit  45  and row decoder circuit  46  used to access the row in memory array  15  and memory array  20 , respectively, to be read from or written to; byte select decoder  55  and byte select decoder  56  used to access bytes in memory array  15  and memory array  20 , respectively, to be read from or written to; charge pump circuit  50  and charge pump circuit  51 , used to provide increased voltages for program and erase operations for memory array  15  and memory array  20 , respectively; high voltage driver circuit  30  shared by memory array  15  and memory array  20  for read and write (erase/program) operations; high voltage driver circuit  25  used by memory array  15  during read and write operations and high voltage driver circuit  26  used by memory array  20  during read and write (erase/program) operations; and high voltage byte select decoder  40  and high voltage byte select decoder  41  used to select or un-select bitlines that are to be programmed during a write operation for memory array  15  and memory array  20 , respectively. As discussed in greater detail below, memory array  15  and memory array  20  are accessed in a manner that emulates traditional EEPROM functionality. 
     With reference to  FIG. 5 , an embodiment of a flash memory circuit  500  with EEPROM functionality is depicted (Disturb Free Super Flash EEPROM). In this embodiment, flash memory circuit  500  is used with flash memory cells of the type shown in  FIG. 1 . Description will be made of the operation of selected byte pair  510 . Selected byte pair  510  comprises two selected bytes of data—a first byte  511  corresponding to a first word line (WL 0 ) and eight bit lines (BL 0  to BL 7 ) and a second byte  512  corresponding to a second word line (WL 0 B) and eight bit lines (BL) to BL 7 ). It is to be understood that connections and circuitry similar to what is described below for selected byte pair  510  and first byte  511  and second byte  512  exist for all other bytes and byte pairs in flash memory circuit  500 . 
     Flash memory circuit  500  comprises a plurality of word lines, such as word line  520  (also labeled WL 0 ), a plurality of associated word lines, such as word line  521  (also labeled WL 0 B), and a plurality of bit lines, such as bit line  540  (also labeled BL 0 ). In prior art designs, memory cells connected to a word line and its associated word line would share a source line, meaning other unselected memory cells in a selected source line are disturbed in programming operation. 
     Flash memory circuit  500  also comprises word line select line  530  (also labeled WLSEL 0 ) coupled to transistor  532  and transistor  533 , word line deselect line  531  (also labeled WLDESEL 0 ), source line select program line  550  (also labeled SLSELP 0 ) coupled to transistor  551 , enable source line select read line  560  (also labeled EN_SLSELR 0 ) coupled to transistor  561 , and source line select read line  570  (also labeled SLSELR 0 ). In this example, bit line  540  is coupled to memory cell  541  (which, in this example, is of the type of memory cell depicted in  FIG. 1 ). The transistors  532 ,  533  are high voltage (HV) transistors, e.g., gate oxide 180-220 A (Angstrom), to be able to supply erase word line voltage, e.g., 10-15V. The transistor  551  is a high voltage (HV) transistors, e.g., gate oxide 180-220 A, or medium high voltage transistors, e.g., gate oxide 100-150 A, to be able to supply programming source line voltage, e.g., 10-15V. The transistor  561  is an IO transistor type, e.g, gate oxide 80 A, to be able to sustain programming source line voltage on its drain. One embodiment uses a FG transistor for the transistor  561 . Advantage of this approach includes process compatibility for FG transistor and transistor  561  in the memory array region. 
     Unlike in the prior art, selected byte pair  510  can be erased without any other byte or byte pair in memory circuit  500  being erased, and selected byte pair  510  can be programmed without any other byte or byte pair in memory circuit  500  being programmed. Thus, EEPROM functionality is achieved using flash memory cells. By contrast, in the prior art, the bytes corresponding to bit lines BL 8  to BL 15  and words line WL 0  and WL 0 B also would have been programmed at the same type as selected byte pair  510 . 
     Specifically, unlike in the prior art, each word line does not connect directly to each memory cell in its row and corresponding row. For example, word line  520  (WL 0 ) is connected to the gate of NMOS transistor  532 , and the source of NMOS transistor is connected to word line select line  530  (WLSEL 0 ) and the drain of NMOS transistor is connected to word lines of memory cell  541  and memory cell  542 . Thus, word line  520  only connects to word lines of memory cell  541  and memory cell  542  when word line select line  530  (WLSEL 0 ) is asserted. If selected byte pair  510  is not intended to be selected, then world line deselect line  531  can be used to pull the voltage of the word line terminals on the memory cells in selected byte pair  510  to 0V or a negative voltage. In this manner, a word line can access just one byte pair of memory cells instead of all memory cells in a row and associated row. 
     Similarly, each source line does not connect directly to each memory cell in its row. For example, SLBYTE 0  is connected only to memory cell  541  and memory cell  542  and other memory cells in selected byte pair  510  and not to other memory cells outside of selected byte pair  510 . In this manner, a source line can access just one byte pair of memory cells instead of all memory cells in a row and corresponding row. 
     An exemplary sets of parameters used to perform erase, program and read operations is shown in Tables 8A-8D below: 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 8A 
               
             
             
               
                   
               
               
                   
                 Selected Byte 
                   
                   
               
             
          
           
               
                   
                 WL 
                 WLB 
                 WL 
                 WLB 
               
               
                   
                 selected 
                 selected 
                 un-selected  
                 unselected 
               
               
                   
               
               
                 ERASE 
                 VWL-E 
                 OV/VWLB-Ebias 
                 VWL_Ebias/OV 
                 OV/Vdd 
               
               
                 PROGRAM 
                 VWL-P 
                 OV/VWLB-Pbias 
                 OV/VWL-Pbias 
                 Vdd/OV 
               
               
                 READ 
                 VWL-R 
                 OV 
                 OV 
                 Vdd 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 8B 
               
               
                   
               
               
                   
                 WLSEL 
                 WLSEL 
                 SLSELP 
                 SLSELP 
               
               
                   
                 selected 
                 un-selected 
                 selected 
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 VWLSEL_E 
                 OV(*) 
                 OV 
                 OV(*) 
               
               
                 PROGRAM  
                 VWLSEL_P 
                 OV(*) 
                 VSLSELP_P 
                 OV(*) 
               
               
                 READ 
                 VWLSEL_R 
                 OV 
                 OV 
                 OV 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 8C 
               
               
                   
               
               
                   
                 EN_SLSELR 
                 SLSELR 
                 EN_SLSELR 
                 SLSELR 
               
               
                   
                 selected 
                 selected 
                 un-selected 
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 Vdd 
                 OV 
                 Vdd 
                 OV(*) 
               
               
                 PROGRAM 
                 VSLSELR- 
                 VSLSELR- 
                 Vdd 
                 OV(*) 
               
               
                   
                 Pbias 
                 Pbias 
                   
                   
               
               
                 READ 
                 Vdd 
                 OV 
                 Vdd 
                 OV 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
             
               
               
               
               
             
               
             
           
               
                 TABLE 8D 
               
             
             
               
                   
               
               
                   
                 Selected Byte 
                   
               
             
          
           
               
                   
                 BL 
                 BL 
                 BL others 
               
               
                   
                 selected 
                 un-selected 
                 un-selected 
               
               
                   
               
               
                 ERASE 
                 OV 
                 OV 
                 OV(*) 
               
               
                 PROGRAM 
                 IPROG 
                 VINH 
                 OV(*) 
               
               
                 READ 
                 VBLR 
                 OV 
                 OV 
               
               
                   
               
             
          
           
               
                 0 V(*) = 0 V or an appropriate bias can be applied to reduce oxide stress 
               
               
                 Erase: 
               
               
                 VWL-E: ~12-13 V 
               
               
                 VWL_Ebias: ~1-3 V 
               
               
                 VWLB_Ebias: ~1-3 V 
               
               
                 VWLSEL_E: ~10-12 V 
               
               
                 WLDESELx = GND/VWLB-Ebias 
               
               
                 Read: 
               
               
                 VWLSEL_R: ~2.5 V 
               
               
                 VBLR: ~0.8-2 V 
               
               
                 VWL-R: ~3-4 V 
               
               
                 WLDESELx 0 V 
               
               
                 Program: 
               
               
                 VWL-P: ~12-13 V 
               
               
                 VWL-Pbias: ~1-3 V 
               
               
                 VWLB-Pbias: ~1-3 V 
               
               
                 VWLSEL_P: ~1-2 V 
               
               
                 VSLSELP-P: ~9-10 V 
               
               
                 VSLSELR-Pbias: ~2-3 V 
               
               
                 IPROG: ~0.1-3 uA 
               
               
                 VINH: ~Vdd V 
               
               
                 WLDESELx = GND/VWLB-Pbias 
               
               
                   
               
             
          
         
       
     
     With reference to  FIG. 6 , an embodiment of a physical layout  600  of the design shown in  FIG. 5  is depicted. Word lines (WLx) are done horizontally in metal 2 layer and select and de-select lines (WLSELx, WLDESELx, SLSELx, ENSLSELx) are done vertically in metal 1 layer. Source lines are done in salicided diffusion or silicided poly. 
     With reference to  FIG. 7 , an embodiment of flash memory circuit  700  that contains modifications to the flash memory circuit  500  of  FIG. 5  is depicted. Many structures in  FIG. 7  are identical to those of  FIG. 5  and will not be described again. The modifications comprise a shared enable source line select read line  610  (also labeled EN_SLSELR 01 ) coupled to transistor pair  611 , and source line select read line  620  (also labeled SLSELR 01 ) that are used to select for reading two byte pairs instead of one byte pair. Here, the two byte pairs correspond to bit lines BL 0  . . . BL 7  and BL 8  . . . BL 15  and word lines WL 0  and WL 0 B. The shared enable source line select read line  610  and source line select read line  620  can be used to read both byte pairs. 
     With reference to  FIG. 8 , an embodiment of flash memory circuit  800  that contains modifications to the flash memory circuit  700  of  FIG. 7  is depicted. Many structures in  FIG. 8  are identical to those of  FIG. 7  and will not be described again. The modifications comprise the use of a single word line for two rows of memory cells instead of two word lines. For example, the first two rows are accessed with word line bar line  810  (also labeled WL 0 B), instead of two words lines as in  FIGS. 5-6 . The plurality of word lines are coupled to the gates of a HV (high voltage) PMOS transistor and an HV NMOS transistor. For example, word line  810  is coupled to PMOS transistor  811  and NMOS transistor  812 . In this manner, the same functions in  FIG. 7  that are performed by a word line and its word bar line are performed by only a word bar line. One of skill in the art will appreciate that instead of word bar lines, word lines instead could be used, with the placement of PMOS and NMOS transistors being swapped. 
     With reference to  FIG. 9 , an embodiment of flash memory circuit  900  that contains modifications to the flash memory circuit  500  of  FIG. 5  is depicted. Many structures in  FIG. 8  are identical to those of  FIG. 5  and will not be described again. The modifications comprise the use of one word line and one NMOS transistor for selecting every two internal rows of memory cells, such as word line  910  (also labeled WL 0 ) and transistor  911  for two rows. The plurality of lines are coupled to the gate of an NMOS transistor  911 . For example, word line  910  is coupled to NMOS transistor  911  as shown. The word line  910  (associated with operating on byte with BL 0 - 7 ) is coupled to transistor  921  and transistor  931 . Source line program select line SLSELP 0   920  is connected to the transistor  921 . Source line read select line SLSELR 0   920  is connected to the transistor  931 . Word line  912  WL 1  functions similarly to the word line WL 0   910  for byte with bitlines BL 8 - 15 . In this manner, the same functions in  FIG. 5  that are performed by two word lines  520  and  521  and two transistors  532  and  533  are performed by only one word line  910  and one transistor  911 . In flash memory circuit  900 , the word line deselect line  531  (also labeled WLDESEL 0  in  FIG. 5 ) and enable source line select read line  560  (also labeled EN_SLSELR 1  in  FIG. 5 ) are not required. Word line WL 1   912  is for selecting next adjacent byte horizontally (with BL 8 - 15 ). In one embodiment, it can be implemented to be the same line as word line  910 . One bias operation embodiment requires all internal wordlines of memory cells pre-charged to ground before any operation. 
     With reference to  FIG. 10 , an embodiment of flash memory circuit  1000  that contains modifications to the flash memory circuit  900  of  FIG. 9  is depicted. Many structures in  FIG. 10  are identical to those of  FIG. 9  and will not be described again. The modifications comprise the use of a shared memory cell source line  1040  shared between two byes (with BL 0 - 7  and BL 8 - 15 ). It also comprises a source line select line  1010  (also labeled SLSEL 0 ) coupled to transistor  1011  and a source line select line  1020  (also labeled SLSEL 1 ) coupled to transistor  1021  used to select two byte pairs instead of one byte pair for programming and reading, respectively. Here, the two byte pairs correspond to bit lines BL 0  . . . BL 7  and BL 8  . . . BL 15 . The source line select line  1010  and source line select line  1020  can be used to program and read. 
     With reference to  FIG. 11 , an embodiment of flash memory circuit  1100  that contains modifications to the flash memory circuit of  FIG. 10  is depicted. Many structures in  FIG. 11  are identical to those of  FIG. 10  and will not be described again. The modifications comprise the use of source line select line  1110  coupled to NMOS transistor  1111  and source line select line  1120  coupled to NMOS transistor  1121 . The source line select line  1110  is used to program and read selected byte pair  510 , and source line select line  1120  is used to program and read the byte pair corresponding to bit lines BL 8  to BL 15  and word lines WL 0  and WL 1 . Thus, each byte pair can be independently programmed. The source line select line  1110  and the NMOS transistor  1111  are shared for program and read selection. 
     With reference to  FIG. 12 , an embodiment of flash memory circuit  1200  that contains modifications to the flash memory circuit of previous figures is depicted. Many structures in  FIG. 12  are identical to those of previous figures and will not be described again. Half of the rows of memory cells are not used in flash memory circuit  1200 . For example, the row containing memory cell  542  is not used, and the word lines for those memory cells are connected to ground bias  1210 . However, the other half of the memory rows, such as the one containing memory cell  541 , is used as described in previous figures. 
     With reference to  FIG. 13 , an embodiment of flash memory circuit  1300  that contains modifications to the flash memory circuit of previous figures is depicted. Many structures in  FIG. 13  are identical to those of previous figures and will not be described again. In flash memory circuit  1300 , each column of memory cells is coupled to two bit lines instead of just one. For example, the column containing memory cell  541  and memory cell  542  (to be called a unit cell pair) is coupled to bit line pair  1340  comprising bit line  540  (bitline BL 0 ) and bit line  1341  (bitline bar BL 0 B or called complementary bitline). A similar bit line pair exists for each column of memory cells. In the specific example of memory cell  541  and memory cell  542 , bit line  540  is coupled to memory cell  541  and bit line  1341  is coupled to memory cell  542 . Memory cell  542  (and other memory cells similarly situated in a pair or memory cells) is not actually used to store data. During a read operation, bit line  1341  will be connected to ground, and memory cell  542  will act as a pull-down transistor to bring the source line (SL 0 _BYTE) down to a low voltage. Thus, half of the rows of the memory array are not used to store data but are used for pull-downing the sourceline to a low voltage (i.e., ground decoding). The above embodiment of bitline and complementary bitline for a unit cell pair is applicable to the following embodiments associated with cell type two in  FIG. 3  and cell type three in  FIG. 4 . 
     With reference to  FIG. 14 , an embodiment of flash memory circuit  1400  that contains modifications to the flash memory circuit of previous figures is depicted. Many structures in  FIG. 14  are identical to those of previous figures and will not be described again. Word line select line  1410  (WLSEL) is coupled to NMOS transistor  1411  and NMOS transistor  1412 . The gate of NMOS transistor  1411  is controlled by word line  1421  (WL 0   a ) and the gate of NMOS transistor  1412  is controlled by word line  1422  (WL 0   b ), with one terminal of NMOS transistor  1411  and one terminal of NMOS transistor  1412  connected to word line select line  1410  (WLSEL) as shown. Each word line can select a row of memory cells. The memory cells share the source lines in pairs of rows as shown. For example, memory cell  541  and memory cell  542  share source line  1430  (SL 0 _BYTE). Source line select line  1440  is coupled to NMOS transistor  1441 , which in turn is coupled to the memory cell source line  1430 . In this embodiment, individual bytes can be read, erased, and programmed with one transistor and one word line select line for selecting a row of memory cells of a byte. 
     With reference to  FIG. 15 , an embodiment of flash memory circuit  1500  that contains modifications to the flash memory circuit of previous figures is depicted. Many structures in  FIG. 15  are identical to those of previous figures and will not be described again. In this embodiment, word line select line and transistor and source line select line and transistor are laid out on the same side of the memory byte. Flash memory circuit  1500  otherwise operates in the same manner as flash memory circuit  1400  in  FIG. 14 . 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , half of the rows (such as all odd rows or all even rows, or some combination of the two) can have its bitline terminal (e.g., bitline contact) removes, its floating gate removed, or its word line terminal tied to ground, such that those rows are not used to store data. 
     In another alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , the number of cells (bits) within a byte (i.e., 8 cells) that are the subject of a read or program operation can be configurable. In one embodiment a read operation is sequentially done 1 or 2 or 4 cells (bits) at a time until all cells in a byte is completed. In one embodiment a program operation is sequentially done 1 or 2 or 4 cells (bits) at a time until all cells in a byte is completed. 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , the transistors connected to the source line select lines (such as transistor  551  connected to source line select program line  550 ) is a native transistor (i.e., meaning its threshold voltage is close to zero volts). 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , the transistors connected to the source line select read lines (such as transistor  561  connected to source line select read line  570 ) is an HV OX (high voltage oxide) transistor. 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , the transistors connected to the source line select read lines (such as transistor  561  connected to source line select read line  570 ) can be removed, and the transistors connected to the source line select program lines (such as transistor  551  connected to source line select program line  550 ) is sized up to operate in read (replacing the transistor  561 ). 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , the transistors connected to the word line select line (such as transistor  532  connected to word line select line  530 ) and the transistors connected to the source line select line (such as transistor  551  connected to source line select program line  550 ) are PMOS transistors instead of NMOS transistors, with the control signals connected thereto being complementary signals to the ones described previously for use with NMOS transistors. 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , more than two bytes of memory cells connect to a common shared source line. In one embodiment, four bytes of memory cells connects to a common shared source line. 
     In an alternative embodiment of flash memory circuits  500 ,  700 ,  800 ,  900 ,  1000 ,  1100 ,  1200 ,  1300 , and  1400 , the word line and source line control signals (which can be connected through vertical metal lines, parallel to memory bitlines) are introduced through nodes that are physically located between individual memory cells or at the end of a byte of memory cells. 
     With reference to  FIG. 16 , an embodiment of a flash memory circuit  1600  with EEPROM functionality is depicted. In this embodiment, flash memory circuit  1600  is used with flash memory cells of the type shown in  FIG. 2 . Description will be made of the operation of selected byte pair  1610 . Selected byte pair  1610  comprises two selected bytes of data—a first byte  1611  corresponding to a first word line (WL 0 ) and eight bit lines (BL 0  to BL 7 ) and a second byte  1612  corresponding to a second word line (WL 0 B) and eight bit lines (BL) to BL 7 ). It is to be understood that similar connections and circuitry exist for all other bytes and similar byte pairs in flash memory circuit  1600 . Flash memory circuit  1600  comprises a plurality of word lines, such as word line  1620  (also labeled WL 0 ), a plurality of associated word lines, such as word line  1621  (also labeled WL 0 B), and a plurality of bit lines, such as bit line  1640  (also labeled BL 0 ). Word lines and associated word lines would have shared a source line in the prior art designs. 
     Flash memory circuit  1600  also comprises word line select line  1630  (also labeled WLSEL 0 ) coupled to transistor  1632  and transistor  1633 , word line deselect line  1631  (also labeled WLDESEL 0 ), source line select program line  1650  (also labeled SLSELP 0 ) coupled to transistor  1651 , enable source line select read line  1660  (also labeled EN_SLSELR 0 ) coupled to transistor  1661 , and source line select read line  1670  (also labeled SLSELR 0 ). In this example, bit line  1640  is coupled to memory cell  1641  (which, in this example, is of the type of memory cell depicted in  FIG. 2 ). Flash memory circuit also comprises control gate select line  1680  (also labeled CGSEL 0 ) coupled to transistor  1681 . 
     Unlike in the prior art, selected byte pair  1610  can be erased without any other byte or byte pair in memory circuit  1600  being erased, and selected byte pair  1610  can be programmed without any other byte or byte pair in memory circuit  1600  being programmed. Thus, EEPROM functionality is achieved using flash memory cells. By contrast, in the prior art, the bytes corresponding to bit lines BL 8  to BL 15  and words line WL 0  and WL 0 B also would have been programmed at the same type as selected byte pair  1610 . 
     Specifically, unlike in the prior art, each word line does not connect directly to each memory cell in its row and corresponding row. For example, word line  1620  (WL 0 ) is connected to the gate of NMOS transistor  1632 , and the source of NMOS transistor  1632  is connected to word line select line  1630  (WLSEL 0 ) and the drain of NMOS transistor  1632  is connected to memory cell  1641  and memory cell  1642 . Thus, word line  1620  only couples to memory cell  1641  and memory cell  1642  when word line select line  1630  (WLSEL 0 ) is asserted. Similarly, control gate select line  1680  (CGSEL 0 ) is connected to the source of transistor  1681 , and the gate of transistor  1681  is coupled to word line  1620  (WL 0 ), with the drain of transistor  1681  connected to the control gates of the memory cells of selected byte pair  1610  (including memory cells  1641  and  1642 ). In this manner, a word line can access just one byte pair of memory cells instead of all memory cells in a row and corresponding row. 
     Similarly, each source line does not connect directly to each memory cell in its row. For example, SLBYTE 0   1652  is connected only to memory cell  1641  and memory cell  1642  and other memory cells in selected byte pair  1610  and not to other memory cells outside of selected byte pair  1610 . In this manner, a source line can access just one byte pair of memory cells instead of all memory cells in a row and corresponding row. The transistors  1632 ,  1633  are high voltage (HV) transistors, e.g., gate oxide 180-220 A (Angstrom), to be able to supply erase word line voltage, e.g., 10-15V. The transistors  1681  is a high voltage (HV) transistor, e.g., gate oxide 180-220 A (Angstrom), to be able to supply control gate line voltage, e.g., 10-15V. The transistor  1651  is a high voltage (HV) transistor, e.g., gate oxide 180-220 A, or medium high voltage transistors, e.g., gate oxide 100-150 A, to be able to supply programming source line voltage, e.g., 4-5V. The transistor  1661  is an IO transistor type, e.g, gate oxide 80 A, to be able to sustain programming source line voltage on its drain. One embodiment uses a FG transistor for the transistor  1661 . An advantage of this approach includes process compatibility for FG transistor and transistor  561  in the memory array region. 
     A set of specific parameters used to perform erase, program and read operations is shown in Tables 9A-9D below: 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 9A 
               
             
             
               
                   
               
               
                   
                 Selected Byte 
                   
                   
               
             
          
           
               
                   
                 WL 
                 WLB 
                 WL 
                 WLB 
               
               
                   
                 selected 
                 selected 
                 un-selected 
                 unselected 
               
               
                   
               
               
                 ERASE 
                 VWL-E 
                 OV/VWLB-Ebias 
                 VWL Ebias/OV 
                 OV/Vdd 
               
               
                 PROGRAM 
                 VWL-P 
                 OV/VWLB-Pbias 
                 OV/VWL-Pbias 
                 Vdd/OV 
               
               
                 READ 
                 VWL-R 
                 OV 
                 OV 
                 Vdd 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
               
               
             
           
               
                 TABLE 9B 
               
               
                   
               
               
                   
                 WLSEL 
                 WLSEL 
                 CGSEL 
                 CGSEL 
                 SLSELP 
                 SLSELP 
               
               
                   
                 selected  
                 un-selected 
                 selected 
                 un-selected 
                 selected 
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 VWLSEL_ 
                 OV(*)  
                 OV/VCGSE 
                 OV(*) 
                 OV 
                 OV(*) 
               
               
                   
                 E 
                   
                 L_ENEG 
                   
                   
                   
               
               
                 PROGRAM  
                 VWLSEL_ 
                 OV(*)  
                 VCGSEL_P 
                 OV(*)  
                 VSL- 
                 OV(*) 
               
               
                   
                 P 
                   
                   
                   
                 SELP-P 
                   
               
               
                 READ 
                 VWLSEL_ 
                 OV 
                 VCGSEL_R 
                 VCGSEL_R 
                 OV 
                 OV 
               
               
                   
                 R 
                   
                   
                 bias 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 9C 
               
               
                   
               
               
                   
                 EN_SLSELR 
                 SLSELR 
                 EN_SLSELR 
                 SLSELR 
               
               
                   
                 selected 
                 selected 
                 un-selected  
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 Vdd 
                 OV 
                 Vdd 
                 OV(*) 
               
               
                 PROGRAM 
                 VSLSELR- 
                 VSLSELR- 
                 Vdd 
                 OV(*) 
               
               
                   
                 Pbias 
                 Pbias 
                   
                   
               
               
                 READ 
                 Vdd 
                 OV 
                 Vdd 
                 OV 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
             
               
               
               
               
             
               
             
           
               
                 TABLE 9D 
               
             
             
               
                   
               
               
                   
                 Selected Byte 
                   
               
             
          
           
               
                   
                 BL 
                 BL 
                 BL others 
               
               
                   
                 selected 
                 un-selected 
                 un-selected 
               
               
                   
               
               
                 ERASE 
                 OV 
                 OV 
                 OV(*) 
               
               
                 PROGRAM 
                 IPROG 
                 VINH 
                 OV(*) 
               
               
                 READ 
                 VBLR 
                 OV 
                 OV 
               
               
                   
               
             
          
           
               
                 ERASE 
               
               
                 VWL-E: ~12-13 V 
               
               
                 VWL_Ebias: ~1-3 V 
               
               
                 VWLB_Ebias: ~1-3 V 
               
               
                 VWLSEL_E: ~10-12 V 
               
               
                 VCGSEL_ENEG: ~−4 to −8V V 
               
               
                 WLDESELx = GND/VWLB-Ebias 
               
               
                 READ 
               
               
                 VWLSEL_R: ~2.5 V 
               
               
                 VBLR: ~0.8-2 V 
               
               
                 VWL-R: ~3-4 V 
               
               
                 VCGSEL_R: ~2-4 V 
               
               
                 VCGSEL_Rbias: ~0-4 V 
               
               
                 WLDESELx: = 0 V 
               
               
                 PROG 
               
               
                 VWL-P: ~12-13 V 
               
               
                 VWL-Pbias: ~1-3 V 
               
               
                 VWLB-Pbias: ~1-3 V 
               
               
                 VWLSEL_P: ~1-2 V 
               
               
                 VSLSELP-P: ~4-6 V 
               
               
                 VSLSELR-Pbias: ~2-3 V 
               
               
                 VCGSEL-P: ~8-10 V 
               
               
                 IPROG: ~0.1-3 uA 
               
               
                 VINH: ~Vcid V 
               
               
                 WLDESELx = GND/VWLB-Pbias 
               
               
                 OV(*) = OV or an appropriate bias can be applied to reduce oxide stress 
               
               
                   
               
             
          
         
       
     
     With reference to  FIG. 17 , an embodiment of a physical layout  1700  of the design shown in  FIG. 16  is depicted. Word lines (WLx) are done horizontally in metal 2 layer and select and de-select lines (WLSELx, WLDESELx, SLSELx, ENSLSELx, CGSELx) are done vertically in metal 1 layer or metal 3 layer. Source lines are done in salicided diffusion or silicided poly. 
     With reference to  FIG. 18 , an embodiment of flash memory circuit  1800  that contains modifications to the flash memory circuit of  FIG. 16  is depicted. Many structures in  FIG. 18  are identical to those of  FIG. 16  and will not be described again. Flash memory circuit  1800  comprises a control gate for each pair of rows, such as control gate line  1810  (CG 0 ) Control gate  1810  (CGO) connects to the gate of transistor  1681 , whose source is connected to control gate select line  1680  (CGSEL 0 ). Thus, unlike in  FIG. 16 , control gate  1810 , in conjunction with control gate select line  1680  (CGSEL 0 ), controls the voltage on the control gates of the memory cells in selected byte  1610 , including memory cells  1641  and  1642 . 
     A set of specific parameters used to perform erase, program and read operations in flash memory circuit  1800  is shown in Tables 10A-10D below: 
     
       
         
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 10A 
               
             
             
               
                   
               
               
                   
                 Selected Byte 
                   
                   
                   
                   
               
             
          
           
               
                   
                 WL 
                 WLB 
                 WL 
                 WLB 
                 CG 
                 CG 
               
               
                   
                 selected 
                 selected 
                 un-selected 
                 unselected 
                 selected 
                 unselected 
               
               
                   
               
               
                 ERASE 
                 VWL-E 
                 OV/VWLB- 
                 VWL_Ebias 
                 OV/Vdd 
                 VCG-E 
                 OV/VCG- 
               
               
                   
                   
                 Ebias 
                 /OV 
                   
                   
                 Ebias 
               
               
                 PROGRAM 
                 VWL-P 
                 OV/VWLB- 
                 OV/VWL- 
                 Vdd/OV 
                 VCG-P 
                 OVNCG_P 
               
               
                   
                   
                 Pbias 
                 Pbias 
                   
                   
                 bias 
               
               
                 READ 
                 VWL-R 
                 OV 
                 OV 
                 Vdd 
                 VCG-R 
                 VCG_Rbias 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
               
               
             
           
               
                 TABLE 10B 
               
               
                   
               
               
                   
                 WLSEL 
                 WLSEL 
                 CGSEL 
                 CGSEL 
                 SLSELP 
                 SLSELP 
               
               
                   
                 selected  
                 un-selected 
                 selected 
                 un-selected 
                 selected 
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 VWLSEL_ 
                 OV(*) 
                 OV/VCGSE 
                 OV(*) 
                 OV 
                 OV(*) 
               
               
                   
                 E 
                   
                 L_ENEG 
                   
                   
                   
               
               
                 PROGRAM  
                 VWLSEL_ 
                 OV(*)  
                 VCGSEL_P 
                 OV(*) 
                 VSLSELP-P 
                 OV(*) 
               
               
                   
                 P 
                   
                   
                   
                   
                   
               
               
                 READ 
                 VWLSEL_ 
                 OV 
                 VCGSEL_R 
                 VCGSEL_R 
                 OV 
                 OV 
               
               
                   
                 R 
                   
                   
                 bias 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 10C 
               
               
                   
               
               
                   
                 EN_SLSELR 
                 SLSELR 
                 EN_SLSELR 
                 SLSELR 
               
               
                   
                 selected 
                 selected 
                 un-selected  
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 Vdd 
                 OV 
                 Vdd 
                 OV(*) 
               
               
                 PROGRAM 
                 VSLSELR- 
                 VSLSELR- 
                 Vdd 
                 OV(*) 
               
               
                   
                 Pbias 
                 Pbias 
                   
                   
               
               
                 READ 
                 Vdd 
                 OV 
                 Vdd 
                 OV 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
             
               
               
               
               
               
             
               
               
             
           
               
                   
                 TABLE 10D 
               
             
             
               
                   
                   
               
               
                   
                   
                 Selected Byte 
                   
               
             
          
           
               
                   
                   
                 BL 
                 BL 
                 BL others 
               
               
                   
                   
                 selected 
                 un-selected 
                 un-selected 
               
               
                   
                   
               
               
                   
                 ERASE 
                 OV 
                 OV 
                 OV(*) 
               
               
                   
                 PROGRAM 
                 IPROG 
                 VINH 
                 OV(*) 
               
               
                   
                 READ 
                 VBLR 
                 OV 
                 OV 
               
               
                   
                   
               
             
          
           
               
                   
                 ERASE 
               
               
                   
                 VWL-E: ~12-13 V 
               
               
                   
                 VWL_Ebias: ~1-3 V 
               
               
                   
                 VWLB_Ebias: ~1-3 V 
               
               
                   
                 VCG-E: ~Vdd to 0 V 
               
               
                   
                 VCG-Ebias: ~0 to -8 V V 
               
               
                   
                 VWLSEL_E: ~10-12 V 
               
               
                   
                 VCGSEL_ENEG: ~-4 to -8 V V 
               
               
                   
                 WLDESELx = GND/VWLB-Ebias 
               
               
                   
                 READ 
               
               
                   
                 VWLSEL_R: ~2.5 V 
               
               
                   
                 VBLR: ~0.8-2 V 
               
               
                   
                 VWL-R: ~3-4 V 
               
               
                   
                 VCG-R: ~3-4 V 
               
               
                   
                 VCG-Rbias: ~0-4 V 
               
               
                   
                 VCGSEL_R: ~2-4 V 
               
               
                   
                 VCGSEL_Rbias: ~0-4 V 
               
               
                   
                 WLDESELx: = 0 V 
               
               
                   
                 PROG 
               
               
                   
                 VWL-P: ~3-4 V 
               
               
                   
                 VWL-Pbias: ~0 V 
               
               
                   
                 VWLB-Pbias: ~1-3 V 
               
               
                   
                 VCG-P: ~12-13 V 
               
               
                   
                 VCG-Pbias: ~1-3 V 
               
               
                   
                 VWLSEL_P: ~1-2 V 
               
               
                   
                 VSLSELP-P: ~4-6 V 
               
               
                   
                 VSLSELR-Pbias: ~2-3 V 
               
               
                   
                 VCGSEL-P: ~8-10 V 
               
               
                   
                 IPROG: ~0.1-3 uA 
               
               
                   
                 VINH: ~Vdd V 
               
               
                   
                 WLDESELx = GND/VWLB-Pbias 
               
               
                   
                   
               
             
          
         
       
     
     With reference to  FIG. 19 , an embodiment of flash memory circuit  1900  that contains modifications to the flash memory circuit of  FIG. 18  is depicted. Many structures in  FIG. 19  are identical to those of  FIG. 18  and will not be described again. Flash memory circuit  1900  comprises source line program line  1910  (SLSELP 0 ) connected to transistor  1911 , enable source line select read line  1920  (ENSLSELR 0 ) connected to transistor  1921 , and source line select read line  1930  (SLSELR 0 ) also connected to transistor  1921 , as shown in  FIG. 19 . Here, a common source line  1940  is shared across pairs of rows. For example, source line  1940  is connected to the memory cells of the byte pairs corresponding to bit lines BL 0  to BL 7  and BL 8  to BL 15 . Thus, both byte pairs can be programmed together with the same shared source line selection. 
     In the alternative, only one byte pair can be programmed if the other byte pair is unselected (inhibited) through a zero or negative voltage (program inhibit CG voltage) applied to its control gate select line. For example, applying a negative voltage such as −5V to control gate select line  1680  (CGSEL 0 ) would unselect (inhibit) byte pair  1610  during a programming operation. 
     With reference to  FIG. 20 , an embodiment of flash memory circuit  2000  that contains modifications to the flash memory circuit of  FIG. 19  is depicted. Many structures in  FIG. 20  are identical to those of  FIG. 10  and previous figures and will not be described again. Flash memory circuit  2000  comprises source select line  1910  (SLSEL 0 ) connected to transistor  1911 , source line select line  2010  (SLSEL 1 ) connected to transistor  2011 , and word line  2020  (W 10 ) and word line  2021  (WLB- 1 ) connected to transistor  2032  and transistor  2033  respectively as shown in  FIG. 20 . The transistor  2032  is for selecting and the transistor  2033  is for de-selecting an internal memory cell word line. Word line  2022  (WL 1 ) connected to transistor  2011  and other select transistor on byte with bitlines BL 7 - 15   2070  that shares source line  2040  with the byte with bitlines BL 0 - 7   2060 . Operating condition is more flexible such as for the byte with BL 7 - 15  in de-selected condition with selected shared source line with the separate word line  2022   
     With reference to  FIG. 21 , an embodiment of flash memory circuit  2100  that contains modifications to the flash memory circuit of  FIG. 20  is depicted. Many structures in  FIG. 21  are identical to those of  FIG. 20  and previous figures and will not be described again. Flash memory circuit  2100  comprises word line select line  2110  (WLSEL 0 ) coupled to transistor  2111 , and word line  2120 . In flash memory circuit  2100 , the word line  2021  and the de-select transistor  2033  of  FIG. 20  are not required. In this manner, the same functions in  FIG. 20  that are performed by two word lines  2020  and  2021  and two transistors  2032  and  2033  are performed by only one word line  2120  and one transistor  2111 . 
     With reference to  FIG. 22 , an embodiment of a flash memory circuit  2200  with EEPROM functionality is depicted. In this embodiment, flash memory circuit  2200  is used with flash memory cells of the type shown in  FIG. 3 . Description will be made of the operation of selected byte pair  2210 . Selected byte pair  2210  comprises two selected bytes of data—a first byte  2211  corresponding to a first word line  2220  (WL 0 ) and eight bit lines (BL 0  to BL 7 ) and a second byte  2212  corresponding to a second word line  2221  (WL 0 B) and eight bit lines (BL 0  to BL 7 ). It is to be understood that similar connections and circuitry exist for all other bytes and similar byte pairs in flash memory circuit  2200 . Flash memory circuit  2200  comprises a plurality of word lines, such as word line  2220  (also labeled WL 0 ), a plurality of associated word lines, such as word line  2221  (also labeled WL 0 B), and a plurality of bit lines, such as bit line  2240  (also labeled BL 0 ). Word lines and associated word lines would have shared a source line in the prior art designs. 
     Flash memory circuit  2200  also comprises word line select line  2230  (also labeled WLSEL 0 ) coupled to transistor  2232  and transistor  2233 , word line deselect line  2231  (also labeled WLDESEL 0 ), source line select program line  2250  (also labeled SLSELP 0 ) coupled to transistor  2251 , enable source line select read line  2260  (also labeled EN_SLSELR 0 ) coupled to transistor  2261 , and source line select read line  2270  (also labeled SLSELR 0 ). In this example, bit line  2240  is coupled to memory cell  2241  (which, in this example, is of the type of memory cell depicted in  FIG. 3 ). Flash memory circuit also comprises control gate select line  2280  (also labeled CGSEL 0 ) coupled to transistor  2281 . 
     Flash memory circuit  2200  also comprises erase gate select line  2290  (also labeled EGSEL 0 ) connected to transistor  2291 , which also is coupled to word line  2220  (WL 0 ) as shown. 
     Unlike in the prior art, selected byte pair  2210  can be erased without any other byte or byte pair in memory circuit  2200  being erased, and selected byte pair  2210  can be programmed without any other byte or byte pair in memory circuit  2200  being programmed. Thus, EEPROM functionality is achieved using flash memory cells. By contrast, in the prior art, the bytes corresponding to bit lines BL 8  to BL 15  and words line WL 0  and WL 0 B also would have been programmed at the same time as selected byte pair  2210 . 
     Specifically, unlike in the prior art, each word line does not connect directly to each memory cell in its row and corresponding row. For example, word line  2220  (WL 0 ) is connected to the gate of NMOS transistor  2232 , and the source of NMOS transistor  2232  is connected to word line select line  2230  (WLSEL 0 ) and the drain of NMOS transistor  2232  is connected to internal word line of memory cell  2241  and memory cell  2242 . Thus, word line  2220  only electrically connects to memory cell  2241  and memory cell  2242  when word line select line  2230  (WLSEL 0 ) is asserted. Similarly, control gate select line  2280  (CGSEL 0 ) is connected to the source of transistor  2281 , and the gate of transistor  2281  is coupled to word line  2220  (WL 0 ), with the drain of transistor  2281  connected to the control gates of the memory cells of selected byte pair  2210  (including memory cells  2241  and  2242 ). In this manner, a word line can access just one byte pair of memory cells instead of all memory cells in a row and corresponding row. 
     Similarly, each source line does not connect directly to each memory cell in its row. For example, SLBYTE 0   2252  (internal source line of memory cells) is connected only to memory cell  2241  and memory cell  2242  and other memory cells in selected byte pair  2210  and not to other memory cells outside of selected byte pair  2210 . In this manner, a source line can access just one byte pair of memory cells instead of all memory cells in a row and corresponding row. The transistor type (HV or IO or FG) and gate oxide of the select transistors are similar to that of  FIGS. 5 and 16 . 
     A set of specific parameters used to perform erase, program and read operations are shown in Tables 11A-11D below: 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 11A 
               
             
             
               
                   
               
               
                   
                 Selected Byte 
                   
                   
               
             
          
           
               
                   
                 WL 
                 WLB 
                 WL 
                 WLB 
               
               
                   
                 selected 
                 selected 
                 un-selected 
                 unselected 
               
               
                   
               
               
                 ERASE 
                 VWL-E 
                 OV/VWLB-Ebias 
                 VWL Ebias/OV 
                 OV/Vdd 
               
               
                 PROGRAM 
                 VWL-P 
                 OV/VWLB-Pbias 
                 OV/VWL-Pbias 
                 Vdd/OV 
               
               
                 READ 
                 VWL-R 
                 OV 
                 OV 
                 Vdd 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 11B 
               
               
                   
               
               
                   
                   
                 WLSEL 
                   
                 CGSEL 
                   
                 EGSEL 
                   
                 SLSELP 
               
               
                   
                 WLSEL 
                 un- 
                 CGSEL 
                 un- 
                 EGSEL 
                 Un- 
                 SLSELP 
                 un- 
               
               
                   
                 selected  
                 selected 
                 selected 
                 selected 
                 selected 
                 selected 
                 selected 
                 selected 
               
               
                   
               
             
             
               
                 ERASE 
                 VWLSEL_E 
                 OV(*) 
                 OV/VC 
                 OV(*) 
                 VSLSE 
                 OV(*) 
                 OV 
                 OV(*) 
               
               
                   
                   
                   
                 GSEL 
                   
                 LP-E 
                   
                   
                   
               
               
                   
                   
                   
                 ENEG 
                   
                   
                   
                   
                   
               
               
                 PROGRAM 
                 VWLSEL_P 
                 OV(*) 
                 VCGSE 
                 OV(*) 
                 VSLSE  
                 OV(*) 
                 VSLSEL  
                 OV(*) 
               
               
                   
                   
                   
                 L_P 
                   
                 LP-P 
                   
                 P-P 
                   
               
               
                 READ 
                 VWLSEL_R 
                 OV 
                 VCGSE  
                 VCGSE  
                 VSLSE  
                 VCG_R 
                 OV 
                 OV 
               
               
                   
                   
                   
                 L_R 
                 L_Rbias 
                 LP-R 
                 bias 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 11C 
               
               
                   
               
               
                   
                 EN_SLSELR 
                 SLSELR 
                 EN_SLSELR 
                 SLSELR 
               
               
                   
                 selected 
                 selected 
                 un-selected 
                 un-selected 
               
               
                   
               
             
             
               
                 ERASE 
                 Vdd 
                 OV 
                 Vdd 
                 OV(*) 
               
               
                 PROGRAM 
                 VSLSELR- 
                 VSLSELR- 
                 Vdd 
                 OV(*) 
               
               
                   
                 Pbias 
                 Pbias 
                   
                   
               
               
                 READ 
                 Vdd 
                 OV 
                 Vdd 
                 OV 
               
               
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
             
               
               
               
               
               
             
               
               
             
           
               
                   
                 TABLE 11D 
               
             
             
               
                   
                   
               
               
                   
                   
                 Selected Byte 
                   
               
             
          
           
               
                   
                   
                 BL 
                 BL 
                 BL others 
               
               
                   
                   
                 selected 
                 un-selected 
                 un-selected 
               
               
                   
                   
               
               
                   
                 ERASE 
                 OV 
                 OV 
                 OV(*) 
               
               
                   
                 PROGRAM 
                 IPROG 
                 VINR 
                 OV(*) 
               
               
                   
                 READ 
                 VBLR 
                 OV 
                 OV 
               
               
                   
                   
               
             
          
           
               
                   
                 ERASE 
               
               
                   
                 VWL-E: ~12-13 V 
               
               
                   
                 VWL_Ebias: ~1-3 V 
               
               
                   
                 VWLB_Ebias: ~1-3 V 
               
               
                   
                 VWLSEL_E: ~10-12 V 
               
               
                   
                 VCGSEL_ENEG: ~−4 to −8V V 
               
               
                   
                 WLDESELx = GND/VWLB-Ebias 
               
               
                   
                 VEGSEL_E: ~10-12 V 
               
               
                   
                 READ 
               
               
                   
                 VWLSEL_R: ~2.5 V 
               
               
                   
                 VBLR: ~0.8-2 V 
               
               
                   
                 VWL-R: ~3-4 V 
               
               
                   
                 VCGSEL_R: ~2-4 V 
               
               
                   
                 VCGSEL_Rbias: ~0-4 V 
               
               
                   
                 WLDESELx 0 V 
               
               
                   
                 VEGSEL_R: ~0-2 V 
               
               
                   
                 VEGSEL_Rbias: ~0-2 V 
               
               
                   
                 PROG 
               
               
                   
                 VWL-P: ~12-13 V 
               
               
                   
                 VWL-Pbias: ~1-3 V 
               
               
                   
                 VWLB-Pbias: ~1-3 V 
               
               
                   
                 VWLSEL_P: ~1-2 V 
               
               
                   
                 VSLSELP-P: ~4-6 V 
               
               
                   
                 VSLSELR-Pbias: ~2-3 V 
               
               
                   
                 VCGSEL-P: ~8-10 V 
               
               
                   
                 IPROG: ~0.1-3 uA 
               
               
                   
                 VINH: ~Vdd V 
               
               
                   
                 WLDESELx = GND/VWLB-Pbias 
               
               
                   
                 VEGSEL_P: ~4-6 V 
               
               
                   
                   
               
             
          
         
       
     
     With reference to  FIG. 23 , an embodiment of a physical layout  2300  of the design shown in  FIG. 22  is depicted. Word lines (WLx) are done horizontally in metal 2 layer and select and de-select lines (WLSELx, WLDESELx, SLSELx, ENSLSELx, CGSELx, EGSELx) are done vertically in metal 1 layer or metal 3 layer. Source lines are done in salicided diffusion or silicided poly. 
     With reference to  FIG. 24 , an embodiment of flash memory circuit  2400  that contains modifications to the flash memory circuit of  FIG. 22  is depicted. Many structures in  FIG. 24  are identical to those of  FIG. 22  and will not be described again. Flash memory circuit  2400  comprises a control gate for each pair of rows, such as control gate line  2410  (CG 0 ) Control gate  2410  (CGO) connects to the gate of transistor  2281 , whose source is connected to control gate select line  2280  (CGSEL 0 ). Thus, unlike in  FIG. 22 , control gate  2410 , in conjunction with control gate select line  2280  (CGSEL 0 ), controls the voltage on the control gates of the memory cells in selected byte  2210 , including memory cells  2241  and  2242 . The control gate line  2410  (CG 0 ) also connects to the gate of the transistor  2291 , whose source is connected to the erase gate select line  2290 . Thus, unlike in  FIG. 22 , control gate  2410 , in conjunction with erase gate select line  2280  (EGSEL 0 ), controls the voltage on the erase gates of the memory cells in selected byte  2210 , including memory cells  2241  and  2242 . In another embodiment, an erase gate line EGO instead of the control gate line CG 0   2410  is connected to the gate of the transistor  2291 . 
     With reference to  FIG. 25 , an embodiment of flash memory circuit  2500  that contains modifications to the flash memory circuit of  FIG. 24  is depicted. Many structures in  FIG. 25  are identical to those of  FIG. 24  and will not be described again. Flash memory circuit  2500  comprises source line program line  2510  (SLSELP 0 ) connected to transistor  2511 , enable source line select read line  2520  (ENSLSELR 0 ) connected to transistor  2521 , and source line select read line  2530  (SLSELR 0 ) also connected to transistor  2521 , as shown in  FIG. 25 . Here, a common source line is shared across pairs of rows. For example, source line  2540  is connected to the memory cells of the byte pairs corresponding to bit lines BL 0  to BL 7  and BL 8  to BL 15 . Thus, both byte pairs can be programmed together with the same shared source line. 
     In the alternative, only one byte pair can be programmed if the other byte pair is unselected (inhibited) through a negative voltage (program inhibit CG voltage) applied to its control gate select line. For example, applying a negative voltage such as −5V to control gate select line  1680  (CGSEL 0 ) would unselect (inhibit) byte pair  1610  during a programming operation. 
     In an alternative embodiment of flash memory circuits described above in  FIGS. 4-25 , a different type of metal can be used for horizontal lines and vertical lines. 
     In an alternative embodiment of flash memory circuits described above in  FIGS. 4-25 , a local pickup can be made of poly diffusion material and the middle level metal can be made of a type of metal. 
     In an alternative embodiment of flash memory circuits described above in  FIGS. 4-25 , a source line can be shared by more than two bytes of memory cells.