Abstract:
Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application&#39;s performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

Description:
FIELD OF THE DISCLOSURE 
     The present disclosure relates generally to the field of power control in integrated circuits and processing systems, and more specifically, to adaptive voltage scaling based on instruction usage. 
     BACKGROUND 
     Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) or the like, utilize a processor executing programs, such as, communication and multimedia programs. The processing system for such products includes a processor complex for processing instructions and data. The functional complexity of such portable products, other personal computers, and the like, requires high performance processors and memory. At the same time, portable products have a limited energy source in the form of batteries and are often required to provide high performance levels at reduced power levels to increase battery life. Many personal computers are also being developed to provide high performance at low power drain to reduce overall energy consumption. 
     Internal to a processor complex, signal paths and pipeline stages are designed to meet a worst case critical timing path corresponding to a desired clock frequency. Memory elements, logic gates, flip-flops, and wires interconnecting the elements introduce delays in the critical path timing limiting the number of functional elements in a pipeline stage dependent upon the clock frequency. As a consequence, many processors use a large number of pipeline stages to execute instructions of varying complexity and achieve gigahertz (GHz) clock frequencies required to meet a product&#39;s functional requirements. Since power is a function of frequency, switching capacitance, and the square of the supply voltage, reducing power requires the reduction of at least one of these three variables. Since gigahertz frequency operation is many times required by a product&#39;s functions, reducing frequency is limited to less demanding functions. Switching capacitance is a function of an implementation and the technology process used to manufacture a device and once a design is instantiated in silicon this variable cannot be changed. One consequence of reducing the supply voltage is that as the supply voltage is reduced the logic and memory elements slow down, increasing the difficulty in meeting frequency requirements. 
     In order to meet a worst case critical timing path in a processor complex, the worst case critical timing paths for all the signal paths within the processor complex are analyzed and the longest path among these becomes the critical timing path that governs the processor complex&#39;s highest possible clock frequency. To guarantee that this clock frequency is met, the supply voltage is specified to be greater than or equal to a worst case minimum voltage. For example, it may be determined that when executing a floating point instruction, a signal path through a floating point multiplier may be the longest critical timing path in the processor complex. The power supply voltage is determined such that the worst case timing path through the floating point multiplier meets the desired clock frequency. 
     Since any instruction may be selected from a processor&#39;s instruction set for execution at any time, the processor complex generally operates in preparation for the worst case timing path. As a consequence, power is wasted when executing instructions having a critical timing path less than the worst case timing path. Unfortunately, the supply voltage cannot be easily changed to match the instruction-by-instruction usage of gigahertz processors. Variable voltage regulators require microseconds or milliseconds to adjust a supply voltage. 
     SUMMARY 
     The present disclosure recognizes that reducing power requirements in a processor complex is important to portable applications and in general for reducing power use in processing systems. It is also recognized that different software applications may use a set of instructions having critical timing paths less than the worst case critical timing path of the processor complex. Further, it is recognized that a supply voltage may be reduced for such applications while still maintaining the clock frequency necessary to meet the application&#39;s performance which reduces power drain based on instruction set usage allowing battery life to be extended. 
     To such ends, an embodiment of the invention addresses a method for adaptive voltage scaling. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on-chip functional operations, wherein the selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. 
     Another embodiment addresses an adaptive voltage scaling (AVS) circuit having a timing path emulation circuit, programmable control logic, and a measurement circuit. The timing path emulation circuit emulates critical paths. The programmable control logic configures the programmable timing path emulation circuit to emulate at least one critical path based on instruction usage in a program to be operated on-chip. The emulated critical path is representative of the worst case critical path to be in operation during the program execution. The measurement circuit measures an attribute of the emulated critical path during on-chip functional operations and, in response to the measured attribute, controls an output voltage of a voltage regulator, wherein the voltage regulator supplies power to a power domain associated with the plurality of critical paths. 
     A further embodiment addresses a method for adaptive voltage scaling. A time delay is set in a programmable path delay circuit to emulate a critical path delay representing the longest critical path associated with a program to be operated on-chip, wherein different programs have different longest critical paths. During on-chip functional operations, a voltage is adjusted based on a measurement of the emulated critical path delay, wherein the voltage supplies power to a power domain associated with the emulated critical path. 
     It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a wireless communication system; 
         FIG. 2  shows a processing system organization for adaptively saving power based on instruction usage; 
         FIG. 3  is an exemplary first embodiment of an adaptive voltage scaling (AVS) circuit; 
         FIG. 4  is an exemplary second embodiment of an adaptive voltage scaling (AVS) circuit; 
         FIG. 5  illustrates an exemplary program selectable path delay circuit; 
         FIGS. 6A and 6B  illustrate timing diagrams for operation of an adaptive voltage scaling combiner included in the second embodiment of the adaptive voltage scaling circuit of  FIG. 4 ; 
         FIG. 7  shows a process for adjusting a voltage regulator based on instruction usage by determining a time margin associated with an instruction critical path delay; and 
         FIG. 8  is an exemplary third embodiment of an adaptive voltage scaling (AVS) circuit. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description set forth below in connection with the appended drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. 
       FIG. 1  illustrates an exemplary wireless communication system  100  in which an embodiment of the invention may be advantageously employed. For purposes of illustration,  FIG. 1  shows three remote units  120 ,  130 , and  150  and two base stations  140 . It will be recognized that common wireless communication systems may have many more remote units and base stations. Remote units  120 ,  130 , and  150  include hardware components, software components, or both as represented by components  125 A,  125 C, and  125 B, respectively, which have been adapted to embody the invention as discussed further below.  FIG. 1  shows forward link signals  180  from the base stations  140  to the remote units  120 ,  130 , and  150  and reverse link signals  190  from the remote units  120 ,  130 , and  150  to the base stations  140 . 
     In  FIG. 1 , remote unit  120  is shown as a mobile telephone, remote unit  130  is shown as a portable computer, and remote unit  150  is shown as a fixed location remote unit in a wireless local loop system. By way of example, the remote units may alternatively be cell phones, pagers, walkie talkies, handheld personal communication systems (PCS) units, portable data units such as personal data assistants, or fixed location data units such as meter reading equipment. Although  FIG. 1  illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the invention may be suitably employed in any device having an adjustable voltage regulator, such as may be used to supply power to a processor and its supporting peripheral devices. 
       FIG. 2  shows a processing system organization  200  for adaptively saving power based on instruction usage. The system  200  comprises a chip  202 , a system supply  204 , such as a battery or bulk supply voltage, and a variable voltage regulator  208 . The chip  202  includes, for example, a first power domain  206  and a second power domain  207 . Each power domain contains a subset of logic appropriately grouped for separate power control to meet the power and performance requirements of the system  200 . Each power domain may further receive a supply voltage from a separate voltage regulator. For example, the first power domain  206  may contain a processor complex having processor execution pipelines  210 , a level 1 cache (L1 Cache)  212 , which may suitably comprise an L1 instruction cache and an L1 data cache, a direct memory access (DMA) controller  214 , one or more hardware assists  216 , control logic  218 , a clock generation unit  220 , and an adaptive voltage scaling (AVS) circuit  222 . The AVS circuit  222  is designed to provide an adjust signal  224  to the variable voltage regulator  208  requesting the voltage Vdd  226  be raised or lowered based on instruction usage of the processor execution pipelines  210 . 
     Instruction usage is categorized by grouping instructions by their critical timing paths. For example, a first category of instructions, may operate with a critical timing path of the processor complex that is used to set the operating frequency of the processor. Such a critical timing path is generally associated with a worst case operating condition of the processor complex having a minimum acceptable operating voltage, highest expected temperature, and worst case process characteristics. At the same worst case operating condition, a second category of instructions may operate with a critical timing path that is less than the critical timing path of the first category of instructions. A third category of instructions may be identified that operate with an associated critical timing path that is less than the second category of instructions, and so on. Thereby, multiple distinct categories of instructions may be identified according to their critical timing path. By static analysis of a program or by monitoring the operating condition and category of instruction usage, the supply voltage for the processor complex in the power domain  206  may be adjusted to ensure the critical timing paths of the instructions meet a specified minimum clock frequency, considering the active or soon to be active categories of instructions. For example, when instruction usage indicates that the instructions in execution or to be executed have a timing margin at the present operating conditions, the voltage may be advantageously lowered to a voltage level appropriate for the corresponding instruction usage, thereby saving power and extending battery life in a mobile device. 
     As an example, in the processing system organization  200 , the processor may contain an integer (Int) unit  228  and a floating point (Fp) unit  230 . By static timing analysis, the critical timing path for floating point instructions may be categorized as category one instructions, for example, having the worst case timing path for the logic in the first power domain  206 . By further static timing analysis, the critical timing path for integer instructions may be categorized as category two instructions having a worst cast timing path that is less than the category one instructions. With the voltage Vdd  226  set at a high level based on execution of previous floating point instructions, for example, and an indication that the instruction usage has changed to category two, the AVS circuit  222  requests that the voltage Vdd  226  be adjusted lower. Depending upon an adjustment step size, the voltage Vdd  226  may be adjusted lower a number of times until a voltage level is reached appropriate for the category two instructions. 
     For example, a 65 nanometer (nm) technology may be used to implement the processing system organization  200  and in such technology a 2-input NAND gate may have a worst case delay of 70 picoseconds (ps) driving an average fan-out of four loads at the worst case operating conditions. Such a delay may increase for every drop in voltage. The critical timing path for a floating point execution stage may have ten similar type gates interconnected by relatively long wires between two storage elements having their own delay, set-up and hold requirements, and just meet a 1 nanosecond pipeline stage delay required for a gigahertz clock frequency at the worst case operating conditions. 
     By comparison, a critical timing path for an integer execution stage may have only five similar type gates interconnected by relatively long wires between two storage elements, and have a critical timing path of 700 picoseconds, well under the 1000 picoseconds of the gigahertz clock frequency at the worst case operating conditions. Consequently, when executing integer type instructions, the voltage Vdd  226  may be appropriately lowered, increasing the critical timing path for the integer instructions up to the 1000 picoseconds stage delay, still meeting the gigahertz clock frequency but with reduced power drain. The operation of the AVS circuit  222  is not dependent upon the number of stages in the processor execution pipelines or the processor clock speed. In general, the voltage can be raised or lowered by programming the AVS system appropriate for a desired frequency corresponding to the critical timing paths expected to be in operation. 
     Variable voltage regulators, such as variable voltage regulator  208 , operate with various voltage step sizes, such as 25 millivolts (mv), as specified by an input signal, such as the adjust signal  224 . Each adjustment of 25 millivolts may take, for example, 10 microseconds or longer. Such an adjustment time is taken into account in hardware or software according to the method for adaptive voltage scaling chosen. 
       FIG. 3  is an exemplary first embodiment of an adaptive voltage scaling (AVS) circuit  300 . The AVS circuit  300  comprises a critical path selection logic  302 , a programmable instruction usage control circuit  304 , and measurement logic  306 . The critical path selection logic  302  includes, for example, four critical paths A-D  308 - 311  providing delayed outputs  314 - 317  to a multiplexer  320 . Critical path A  308 , for example, is the worst case timing path in the first power domain  206  and is, also for example, associated with execution of floating point instructions. Critical path B  309  has a signal path delay less than critical path A  308  and is, for example, associated with integer instructions. Critical path C  310  has a delay less than critical path B  309  and critical path D  311  has a delay less than critical path C  310 . 
     The multiplexer  320  selects one of the critical paths based on a select signal  322  generated by selection logic  324  based on information from multiplexer  326 . The programmable instruction usage control circuit  304  comprises a configuration register  328 , an instruction decoder  330 , a controller  332  which includes one or more counters  334 . The instruction decoder  330  decodes instructions received from an instruction stream  336 , such as may be provided by processor execution pipelines  210  of  FIG. 2 . The decode information is sent to controller  332  where it may be used to load the configuration register  328  via a load path  338  and set static flags  340 , such as, compiler directed flags. The controller  332  may also use the decode information to determine dynamic flags  342  associated with dynamically determining instruction usage, for example, by using the counter  334  to count the number of times a particular type of instruction is decoded or the time between decoding instructions of a particular type. The multiplexer  326  selects either the static flags  340  or the dynamic flags  342  based on select bits loaded into the configuration register  328 . The measurement logic  306  measures the selected path and generates an adjust signal  344  that is used by the variable voltage regulator  208  of  FIG. 2 . 
     In more detail, each of the critical paths  308 - 311  may be emulated critical paths that use components in their associated signal path that are similar to the actual components used in the critical path they are emulating. In addition, each of the emulated critical paths is placed in close proximity to their associated actual critical path to make the implementation process and temperature conditions experienced by the emulated components similar to the conditions the actual critical path elements encounter. Since the selected actual critical paths and their associated emulated critical paths may be distributed across a chip, the multiplexer  320  and measurement logic  306  may also be suitably distributed across the chip, while still converging to a single adjust signal  344 . 
     The static flags  340  may be set by a compiler that accounts for the adaptive voltage scaling (AVS) circuit by monitoring static instruction usage in a program according to categories of instructions classified by their critical timing paths. For example, in compiling a video processing program, it may be determined that there is a very limited usage of category one instructions, such as, for example, floating point instructions. Based on the limited usage of floating point instructions, the compiler may select to emulate the floating point instructions, thereby removing category one instructions from the compiled video processing program. Based upon such an analysis, the compiler may set the static flags  340  to indicate selection of critical path B  309 , for example. Based on the measurement of critical path B  309 , adjust signal  344  may indicate the voltage Vdd  226  of  FIG. 2 , can be lowered. 
     With the configuration register setting the multiplexer  326  to select the dynamic flags  342 , the selection of one of the critical paths A-D  308 - 311  is determined by hardware usage information. For example, by monitoring the instruction stream  336  based on decoded information from the instruction decoder  330 , the controller  332  may determine that a particular instruction type, generally associated with video processing, is occurring frequently and no floating point instructions have been encountered for the last ten thousand instructions. Based on this determination, the controller  332  may set dynamic flags appropriate for the selection of critical path B  309 . After such a selection, if a category one instruction is encountered, a stall situation would be enforced and the adjust signal  344  set to indicate the voltage is to be raised to accommodate the category one instruction. 
       FIG. 4  shows an exemplary second embodiment of an adaptive voltage scaling (AVS) circuit  400  which may be suitably employed as the AVS circuit  222 . The AVS circuit  400  comprises critical path modeling circuit  402 , measurement logic  406 , and programmable configuration register  404 . The critical path modeling circuit  402  includes a flip-flop  408 , a NAND gate  410 , a program selectable path delay circuit  412 , and a clock reference delay unit  414 . The measurement logic  406  includes measurement flip-flops (Mflip-flops)  416 - 419 , a first delay element D 1   420 , a second delay element D 2   422 , and an AVS combiner  424 . 
     The flip-flop  408  and NAND gate  410  comprise a toggle flip-flop arrangement which when not held by the hold signal  428  and clocked by clock signal  430 , toggles the Q output  432  with each rising edge of the clock signal  430 . The hold signal  428  at a “1” level enables the measurement process. The Q output  432  is coupled to a data input of the Mflip-flop  416  and to the program selectable path delay circuit  412 . The program selectable path delay circuit  412  is configured for emulating a critical path delay based on a select input  434  from the programmable configuration register  404 . For example, when the Q output  432  rises to a “1” level, after a programmable delay period, a first delay output  436  from the program selectable path delay circuit  412  is received at a data input of the flip-flop  417  and at an input to the first delay element D 1   420 . A second delay output  438  of the first delay element D 1   420  is coupled to a data input of flip-flop  418  and to an input to the second delay element D 2   422 . A third delay output  440  of the second delay element D 2   422  is coupled to a data input to flip-flop  419 . 
     The clock signal  430  is delayed by the clock reference delay unit  414  to match the delay of the program selectable path delay circuit  412  when it is programmed for “no delay.” That is, even if 0 stages of delay are programmed in each and every section of the program selectable path delay circuit  412 , there will be some delay just from traversing the multiplexers as described in further detail below with respect to the program selectable path delay circuit  500  of  FIG. 5 . The clock reference delay unit  414  also includes the launch delay of the flip-flop  408 . Then, the arrival time delta between the delayed clock signal  442  and the first delay output  436  represents the delay of the programmed delay elements in the program selectable path delay circuit  412  plus the launch delay of the latch. The delayed clock signal  442  is used to clock each of the Mflip-flops  416 - 419  transferring the values of their data inputs to corresponding Q outputs  444 - 447 . The Q outputs  444 - 447  are coupled to the AVS combiner  424  which contains priority encoded logic to determine whether the critical path is being met. By measuring from the rising edge of Q output  432  to the Q outputs  444 - 447 , the critical path is being measured every other clock period. 
     For example, critical path B  309  of  FIG. 3  is emulated by the program selectable path delay circuit  412  by loading appropriate configuration input values associated with the critical path B  309 . For this example, the voltage Vdd  226  of  FIG. 2  at the start of the delay emulation is at its highest level. If the Q outputs  444 - 447  are at a “1” level at the end of the delay emulation, then the critical path B  309  as measured from rising edge of Q output  432  to rising edges of Q outputs  444 - 447  meets the clock frequency period with a timing margin of D 1   420  plus D 2   422 . In this situation, the voltage Vdd  226  would be considered too high and adjust signal  448  would indicate that the voltage Vdd  226  should be lowered. While such lowering of the voltage Vdd  226  is occurring, other operations on the chip may continue as normal. After a period of time required for the variable voltage regulator to reach the new lower voltage level, the timing of the modeled critical path B  309  may be redone. If the Q outputs  444 - 447  are still at a “1” level at the end of a delay emulation, the voltage would be lowered again. If, the Q outputs  444 - 446  are at a “1” level and the flip-flop  419  Q output  447  is at a “0” level, then the critical path B  309  makes its timing with a timing margin of D 1   420 . At this point, adequate timing margin may be considered to be present and no further adjustment to the voltage Vdd  226  is made. Alternatively, if the program selectable path delay circuit  412  included additional timing margin within its delay setting, then the timing margin of D 1  may still be excessive and the voltage Vdd  226  may be adjusted to a lower voltage. 
     With a timing margin of D 1   420  plus D 2   422 , a larger step size for adjusting the supply voltage may be made as compared to the step size used when only a margin of D 1  is detected. Falling edge to falling edge signal timing may also be measured with the AVS circuit  400 . The Mflip-flop  416  is provided as an indication that a delay emulation was executed and if none of the other Mflip-flops  417 - 419  are set then no timing margin exists or an error situation has been encountered. It is also noted that by use of a forced adjustment signal  450 , an adjustment may be forced to occur based on events occurring other than the measurement of emulated critical timing paths, such as may occur when processing an interrupt routine requiring the use of a category one instruction. 
       FIG. 5  is an exemplary program selectable path delay circuit  500  which may be suitably employed as program selectable path delay circuit  412 . A critical timing path may be emulated as a path through a static logic circuit  502 , a dynamic logic circuit  504 , models of interconnection wiring delays on different silicon layers, such as, a metal levels  2  and  3  (M 2 /M 3 ) circuit  506 , and a metal levels  4  and  5  (M 4 /M 5 ) circuit  508 . In reference to  FIG. 4 , the program selectable path delay circuit  412  comprises the static logic circuit  502 , the dynamic logic circuit  504 , the metal levels M 2 /M 3  circuit  506 , and the metal levels M 4 /M 5  circuit  508 . 
     To emulate a circuit&#39;s static logic, a static logic buffer  510 , with a minimum delay such as 20 picoseconds for example, is replicated in a serial chain of 32 buffers  512  which is tapped off at each buffer position and coupled to a 32 to 1 multiplexer  514 . The programmable configuration register  404  of  FIG. 4  couples select configuration A (ConfigA) signals  516  to the 32 to 1 multiplexer  514  to programmably select delays from 20 picoseconds up to a maximum of 640 picoseconds in 20 picosecond delay intervals on the output  518 . 
     To emulate a circuit&#39;s dynamic logic, a dynamic logic buffer  520 , with a minimum delay of 15 picoseconds for example, is replicated in a serial chain of eight dynamic logic buffers  522  which is tapped off at each dynamic buffer position and coupled to an 8 to 1 multiplexer  524 . The programmable configuration register  404  couples select configuration B (ConfigB) signals  526  to the 8 to 1 multiplexer  524  to programmably select delays from 15 picoseconds up to 120 picoseconds in 15 picosecond delay intervals on the output  528 . 
     To emulate a circuit&#39;s wire delays for metal layers M 2 /M 3 , a buffer resistor capacitor (RC) circuit  530  is used with a time constant delay, for example 8 picoseconds, chosen to match a minimum expected wire delay for the wiring levels M 2  and M 3 . The RC circuit  530  is replicated in a serial chain of, for example, four RC circuits  532  which is tapped off at each RC circuit position and coupled to a 4 to 1 multiplexer  534 . The programmable configuration register  404  couples select configuration C (ConfigC) signals  536  to the 4 to 1 multiplexer  534  to programmably select delays from 8 picoseconds up to 32 picoseconds in 8 picosecond intervals on the output  538 . 
     To emulate a circuit&#39;s wire delays for metal layers M 4 /M 5 , a buffer resistor capacitor (RC) circuit  540  is used with a time constant delay, for example 9 picoseconds, chosen to match a minimum expected wire delay for the wiring levels M 4  and M 5 . The RC circuit  540  is replicated in a serial chain of, for example, eight RC circuits  542  which is tapped off at each RC circuit position and coupled to an 8 to 1 multiplexer  544 . The programmable configuration register  404  couples select configuration D (ConfigD) signals  546  to the 8 to 1 multiplexer  544  to programmably select delays from 9 picoseconds up to 72 picoseconds in 9 picosecond intervals on the output  548 . 
     The program selectable path delay circuit  412  may be implemented with more or less emulated functions depending upon the implementation technology and critical timing paths being emulated. For example, with implementation and technology that does not use dynamic logic, the dynamic logic circuit  504  would not be required. In a further example, two more wiring metal layers M 6  and M 7  may be used in an implementation having a different delay model than the other wiring levels and requiring a metal layer M 6 /M 7  circuit be developed that models the timing delay for signals that travel the M 6  and M 7  layers. 
       FIGS. 6A and 6B  illustrate timing diagrams  600  and  625 , respectively, for operation of the adaptive voltage scaling combiner  424  included in the second embodiment of the adaptive voltage scaling circuit  400  of  FIG. 4 . Exemplary relationships between the timing events of  FIGS. 6A and 6B  and the elements of  FIG. 4  are indicated by referring to exemplary elements from the AVS circuit  400  which may suitably be employed to carry out the timing events of  FIGS. 6A and 6B . A timing event is considered to occur when a signal transition crosses the logic threshold of a device used in an implementation technology. 
     The circuits described herein are assumed to respond to input signals at a 30% above a ground level or 30% of a supply voltage level. For example, a “0” value would be considered anything less than or equal to 0.3 volts and a “1” value would be considered anything greater than or equal to 0.7 volts for a supply voltage of 1.0 volts. Depending upon technology, a different supply voltage may be used and a response tolerance different than 30% may also be used. For the timing diagram  600  a supply voltage of 1 volt is assumed. It is noted that the rising and falling edges of the clock  430 , delayed clock  442 , and other signals may vary with voltage, process technology, and other factors such as signal loading. These variations may be accounted for by appropriate signal analysis techniques such as the use of analog circuit simulation techniques. 
     In  FIG. 6A , at timing event  602 , the rising edge of clock  430  causes the Q output  432  of the flip-flop  408  to transition to a high level. At timing event  604 , the rising edge of the clock  430  causes the Q output  432  of the flip-flop  408  to transition to a low level. The Q output  432  flows through the program selectable path delay circuit  412  generating the first delay output  436  with a delay  608 . The second delay output  438  follows after a delay D 1   612  and the third delay output  440  follows after a delay D 2   614 . The Mflip-flops  416 - 419  are clocked by delayed clock  442  at timing event  616 . In this example, the Q outputs  444 - 447  are all at a “1” level at timing event  616  indicating that the voltage Vdd  226  of  FIG. 2  may be lowered. Once the voltage has been lowered to the desired voltage, the delay path is remeasured since all the delays will have increased due to the lower voltage. Depending upon the number of Mflip-flops  416 - 419  that are asserted further adjustments to the voltage Vdd may be made. It is appreciated that circuit analysis techniques are used, for example, to ensure correct operation within best-case to worst-case timing scenarios for a particular implementation. 
     In  FIG. 6B , the voltage Vdd  226  has been lowered and the delay of the emulated critical timing path has increased. The Q output  432  flows through the program selectable path delay circuit  412  generating the first delay output  436  but now with a delay  630 . The second delay output  438  follows after a delay D 1   632  and the third delay output  440  follows after a delay D 2   634 . The Mflip-flops  416 - 419  are clocked by delayed clock  442  at timing event  636 . In this example, three Q outputs  444 - 446  are at a “1” level and Q output  447  is at a “0” level at timing event  636  indicating that there still is adequate timing margin and no further downward adjustment of the voltage Vdd  226  should be performed. 
       FIG. 7  shows a proces  700  for adjusting a voltage regulator based on instruction usage by determining a time margin associated with an instruction critical path delay. The process  700  starts at block  702  with the loading of the programmable configuration register for a selected critical path. The selected critical path is determined from the instruction usage in a compiled program. At block  704 , the time delay of the selected critical timing path is measured. Such measurement, for example, is done by checking the status of the Mflip-flops  416 - 419 . The checking of the Mflip-flops  416 - 419  may be done at any time since the AVS circuits  300  and  400  operate every clock period while other on-chip functional operations are in process unless AVS is specifically disabled. At block  706 , a determination is made whether all measurement flip-flops (Mflip-flop) are set. If all Mflip-flops are set, the process  700  proceeds to block  708 . At block  708 , the time margin is greater than required so the voltage is considered too high and an adjustment signal is sent to the voltage regulator to lower the voltage. Block  708  is comparable to timing event  616  of  FIG. 6A . After the voltage is adjusted, the process  700  returns to block  704  and the measurement is repeated. 
     Returning to block  706 , if all the Mflip-flops are not set, the process  700  proceeds to block  710 . At block  710 , a determination is made whether three of the four Mflip-flops are set. If three of the four Mflip-flops are set, the process  700  proceeds to block  712 . At block  712 , the voltage is considered acceptable and no voltage adjustment is done. Block  712  is comparable to timing event  636  of  FIG. 6B . The process  700  returns to block  704  and the measurement is repeated. 
     Returning to block  710 , if three of the four Mflip-flops are not set, the process proceeds to block  714 . At block  714 , a determination is made whether one or two Mflip-flops are set. If one or two Mflip-flops are set, the process proceeds to block  716 . At block  716 , the time margin is less than required so the voltage is considered too low and an adjustment signal is sent to the voltage regulator to raise the voltage. After the voltage is adjusted, the process  700  returns to block  704  and the measurement is repeated. Returning to block  714 , if one or two Mflip-flops are not set, the process proceeds to block  718  where an error condition is indicated. 
       FIG. 8  shows an exemplary third embodiment of an adaptive voltage scaling (AVS) circuit  800 . The AVS circuit  800  comprises the critical path modeling circuit  402 , the programmable configuration register  404 , and a measurement logic circuit  806 . The critical path modeling circuit  402  includes the flip-flop  408 , the NAND gate  410 , the program selectable path delay circuit  412 , and the clock reference delay unit  414 . Measurement logic  806  includes the measurement flip-flops (Mflip-flops)  416  and  417  and an AVS combiner  824 . 
     The flip-flop  408  and NAND gate  410  comprise a toggle flip-flop arrangement which when not held by the hold signal  428  and clocked by clock signal  430 , toggles the Q output  432  with each rising edge of the clock signal  430 . The hold signal  428  at a “1” level enables the measurement process. The Q output  432  is coupled to the data input of the Mflip-flop  416  and to the program selectable path delay circuit  412 . The program selectable path delay circuit  412  is configured for emulating a critical path delay plus additional programmed delays D 1  and D 2  based on the select input  434  from the programmable configuration register  404 . For example, when the Q output  432  rises to a “1” level, after the specified programmable delay period, a first delay output  436  from the program selectable path delay circuit  412  is received at a data input of the flip-flop  417 . The clock signal  430  is delayed by the clock reference delay unit  414  to account for delays of clock distribution such as occurs with a clock tree, like clock tree  234  of  FIG. 2 . The delayed clock signal  442  is used to clock each of the Mflip-flops  416  and  417  transferring the values of their data inputs to corresponding Q outputs  444  and  445 . The Q outputs  444  and  445  are coupled to an AVS combiner  824  which contains priority encoded logic to determine whether the critical path is being met. 
     For example, the delay of the critical path B  309  of  FIG. 3  plus an additional programmed delay values of D 1  plus D 2  is emulated by the program selectable path delay circuit  412  by loading appropriate configuration input values. The programmed delay values of D 1  and D 2  may change depending on the critical path or depending on process or temperature variations encountered in the chip&#39;s operating condition. With the critical path lengthened by programmed delays D 1  plus D 2 , the two flip-flops, Mflip-flop  416  and Mflip-flop  417  are used to determine whether the time delay margin is such that the voltage can be lowered, kept the same, or raised. 
     For this example, the voltage Vdd  226  of  FIG. 2  is at its highest level. If the Q outputs  444  and  445  are at a “1” level at the end of an emulation delay, then the critical path B  309  as measured from rising edge of Q output  432  to rising edge Q outputs  444  and  445  meets the clock frequency period with a timing margin of D 1  plus D 2 . In this situation, the voltage Vdd  226  would be considered too high and the adjust signal  848  would indicate that the voltage Vdd  226  should be lowered. While such lowering of the voltage Vdd  226  is occurring, other operations on the chip may continue as normal. After a period of time required for the variable voltage regulator to reach the new lower voltage level, the timing of the modeled critical path may be redone. If the Q outputs  444  and  445  are still at a “1” level, the voltage would be lowered again. 
     If, the Q outputs  444  and  445  are not both at a “1” level, the delay of the critical path B  309  plus programmed delays D 1  plus D 2  did not meets the clock frequency period. To determine whether there is a sufficient timing margin for critical path B  309 , the configuration register is loaded with a delay model for critical path B  309  delay plus D 1  and the timing of the emulated path checked again. If both Mflip-flops  416  and  417  are set, then adequate timing margin is present and no further adjustment to the voltage Vdd  226  is made. If both of the Mflip-flops are not set, the critical path B  309  plus programmed delay D 1  did not make its timing, indicating the timing margin may be insufficient for the category two instructions. In this later situation, the adjust signal  848  would indicate the voltage Vdd should be raised. 
     Falling edge to falling edge signal timing may also be measured with the AVS circuit  800 . It is also noted that an adjustment signal  850  may convey information as to the type of delay being measured. For example, with a single adjustment signal  850  set to a “1” level, the combiner  824  would consider the Q output  417  being set to a “1” as indicating a critical path delay plus programmable delays D 1  plus D 2  is meeting timing with excessive time margin and the voltage may be lowered. The voltage is lowered until the Q output  417  at the end of a delay emulation is a “0”. Then the programmable configuration register  404  is loaded with critical path delay plus programmable delay D 1  and the adjustment signal  850  is set to a “0” indicating a second measurement with reduced time margin is being tested. The combiner  824  would interpret a Q output  417  of “1” and adjustment signal  850  of “0” as indicating an appropriate margin is present and the voltage regulator is not adjusted. Alternatively, the combiner would interpret a Q output  417  of “0” and adjustment signal  850  also of “0” as indicating the time margin is too small and the voltage needs to be raised. Upon changing to a new critical path emulation measurement with the loading of new configuration bits the adjustment signal may be set depending on the present operation condition of the processor and the newly selected critical path to be measured. 
     The various illustrative logical blocks, modules, circuits, elements, and/or components described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic components, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration appropriate for a desired application. 
     The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. 
     While the invention is disclosed in the context of an instruction set architecture for a processing system, it will be recognized that a wide variety of implementations, such as adjusting voltage according to categories of functions executed on hardware assist co-processing units may be employed using the techniques of the invention by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below.