Abstract:
A data recording apparatus comprises a plurality of recording media, data generating means for generating recording data, recording means for, whenever the recording data is generated from the data generating means, allocating and recording the recording data in the plurality of recording media, and data transfer means for integrating, into one recording medium, the plurality of recording data recorded in a distributed manner in the plurality of recording media, when the data generating means and the recording means are not in operation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. 2003-408699, filed Dec. 8, 2003; and No. 2003-408700, filed Dec. 8, 2003, the entire contents of both of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a technique to efficiently transfer data to a plurality of recording media, and relates to a digital camera in which this technique is applied.  
         [0004]     2. Description of the Related Art  
         [0005]     In personal computers, for example, a technique is employed in which when data is to be stored, the data is divided and stored in a plurality of hard disc drives (HDDs) to reduce write time of the data in order to enhance performance of a system.  
         [0006]     This technique for efficiency in data transfer time is also highly needed in digital cameras. For example, a digital camera has been proposed which allows two memory cards to be attached thereto and which allows a user to easily manage the attached memory cards without causing the user to be conscious of which memory card is inserted into which slot (Jpn. Pat. Appln. KOKAI Publication No. 2001-169225).  
       BRIEF SUMMARY OF THE INVENTION  
       [0007]     A data recording apparatus according to a first aspect of the present invention comprises: a plurality of recording media; data generating means for generating recording data; recording means for, whenever the recording data is generated from the data generating means, allocating and recording the recording data in the plurality of recording media; and data transfer means for integrating, into one recording medium, the plurality of recording data recorded in a distributed manner in the plurality of recording media, when the data generating means and the recording means are not in operation.  
         [0008]     A data recording apparatus according to a second aspect of the present invention comprises: a plurality of detachable recording means; data generating means for generating recording data; judging means for judging whether or not a combination of the plurality of recording means is proper; and recording means for recording the recording data generated by the data generating means in the plurality of recording means in a distributed manner when the combination of the plurality of recording means is judged to be proper.  
         [0009]     A digital camera according to the first aspect of the present invention comprises: a plurality of recording media; data generating means for generating recording data; recording means for, whenever the recording data is generated from the data generating means, allocating and recording the recording data in the plurality of recording media; and data transfer means for integrating, into one recording medium, the plurality of recording data recorded in a distributed manner in the plurality of recording media, when the data generating means and the recording means are not in operation.  
         [0010]     A digital camera according to the second aspect of the present invention comprises: a plurality of detachable recording means; data generating means for generating recording data; judging means for judging whether or not a combination of the plurality of recording means is proper; and recording means for recording the recording data generated by the data generating means in the plurality of recording means in a distributed manner when the combination of the plurality of recording means is judged to be proper.  
         [0011]     Advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.  
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0012]     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.  
         [0013]      FIG. 1  is a perspective view of a digital camera to which a data recording apparatus in a first embodiment of the present invention is applied;  
         [0014]      FIG. 2  is a perspective view looking obliquely from behind at an opened card cover of a grip portion;  
         [0015]      FIG. 3  is a diagram showing a system configuration of the digital camera;  
         [0016]      FIG. 4  is a diagram showing how to equip an adapter with memory cards;  
         [0017]      FIG. 5  is a diagram showing the backside of the adapter equipped with the memory cards;  
         [0018]      FIG. 6  is a diagram showing image data recorded in the memory cards;  
         [0019]      FIG. 7  is a diagram showing a memory card reader;  
         [0020]      FIG. 8  is a schematic flowchart showing transfer and recording operations of the image data;  
         [0021]      FIG. 9  is a schematic flowchart showing the transfer and recording operations of the image data;  
         [0022]      FIG. 10  is a schematic flowchart showing the transfer and recording operations of the image data;  
         [0023]      FIG. 11  is a schematic flowchart showing the transfer and recording operations of the image data;  
         [0024]      FIG. 12  is a diagram showing image data recorded in the memory cards;  
         [0025]      FIG. 13  is a diagram showing signal connection between recording media and an image processing controller;  
         [0026]      FIG. 14  is a flowchart showing a procedure in the image processing controller to exchange data with the recording medium;  
         [0027]      FIG. 15  is a diagram representing a timing chart of data exchange signals between the image processing controller and the recording medium;  
         [0028]      FIG. 16  is a diagram showing the signal connection between the recording media and the image processing controller;  
         [0029]      FIG. 17A  is a diagram explaining the operation of a latch circuit;  
         [0030]      FIG. 17B  is a diagram explaining the operation of the latch circuit;  
         [0031]      FIG. 18  is a diagram representing a timing chart of the data exchange signals between the image processing controller and the recording media;  
         [0032]      FIG. 19  is a diagram showing the signal connection between the image processing controller and a latch circuit which is a part of a data latch circuit;  
         [0033]      FIG. 20  is a flowchart showing a data output operation;  
         [0034]      FIG. 21  is a diagram representing a timing chart of the signals when the image processing controller exchanges data only with the recording medium;  
         [0035]      FIG. 22  is a diagram showing the signal connection between the recording media and the image processing controller;  
         [0036]      FIG. 23  is a diagram representing a timing chart of the data exchange signals between the image processing controller and the recording media;  
         [0037]      FIG. 24  is a diagram showing one embodiment associated with combination identification information;  
         [0038]      FIG. 25  is a diagram showing exclusive identification files;  
         [0039]      FIG. 26  is a diagram showing another embodiment associated with the combination identification information;  
         [0040]      FIG. 27  is a diagram showing another embodiment associated with the combination identification information;  
         [0041]      FIG. 28  is a schematic flowchart showing the transfer and recording operations of the image data;  
         [0042]      FIG. 29  is a schematic flowchart showing the transfer and recording operations of the image data; and  
         [0043]      FIG. 30  is a schematic flowchart showing the transfer and recording operations of the image data.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0044]      FIG. 1  is a perspective view of a digital camera to which a data recording apparatus in a first embodiment of the present invention is applied.  
         [0045]     The present digital camera comprises a body unit  100 , a lens unit  12  and a flash unit (not shown)  80 .  
         [0046]     Further, the body unit  100  comprises a camera operating switch  52 , an operation displaying LCD  57 , a flash attaching shoe  87  and a grip portion  110 .  
         [0047]     The camera operating switch  52  is provided with a release button  52   a , a setting dial  52   b , a mode dial  52   c  and a power switch  52   d.    
         [0048]     The release button  52   a  starts focusing and photographing operations. The setting dial  52   b  sets the shutter speed and aperture. The mode dial  52   c  sets exposure modes such as an aperture priority mode, a shutter priority mode and a manual mode. The power switch  52   d  is a switch to turn on/off a power supply.  
         [0049]     In the grip portion  110  for a photographer to grip the body unit  100 , there is provided a mechanism to store a memory card  120  which will be hereinafter described, a power supplying battery  54  and the like.  
         [0050]      FIG. 2  is a perspective view looking obliquely from behind at an opened card cover  111  of the grip portion  110 . In the grip portion  110 , there are provided insert portions  115   a ,  115   b , eject levers  116   a ,  116   b  and a packed state detection switch  118 .  
         [0051]     The insert portions  115   a ,  115   b  allow the memory card  120  to be inserted into slots of recording media (hereinafter described). The eject levers  116   a ,  116   b  eject the memory card  120  from the insert portions  115   a ,  115   b . The packed state detection switch  118  detects whether or not the memory card  120  is in an inserted state.  
         [0052]     Next, a system configuration of the present digital camera will be described referring to  FIG. 3 .  
         [0053]     The system of this digital camera comprises the body unit  100  as a camera main body, the exchangeable lens unit  12  which is an accessory device (hereinafter abbreviated to “accessory”), a recording medium  39  to record taken image data, the external flash unit  80 , and the like.  
         [0054]     The lens unit  12  desired by a user is detachably set via a lens mount (not shown) provided in front of the body unit  100 .  
         [0055]     The recording medium  39  is an external recording medium such as various memory cards or external HDDs, and a plurality of recording media  39   a ,  39   b  is prepared and they are attached, via communication connectors  35   a ,  35   b , to the camera main body in a manner to be able to communicate and to be exchanged.  
         [0056]     The flash unit  80  comprises a flashtube  81 , a DC/DC converter  82 , a flash control microcomputer  83  and a battery  84 , and can be attached to the camera main body in a manner to be able to communicate via a flash communication connector  85 .  
         [0057]     The lens unit  12  is controlled by a lens controlling microcomputer (hereinafter referred to as “Lucom”)  5 . The body unit  100  is controlled by a body controlling microcomputer (hereinafter referred to as “Bucom”)  50 . It is to be noted that the Lucom  5  and the Bucom  50 , when combined, are electrically connected in a manner to be able to communicate via a communication connector  6 . Thus, the Lucom  5  cooperates dependently with the Bucom  50  to operate as a camera system.  
         [0058]     A taking lens  12   a  and a diaphragm  3  are provided in the lens unit  12 . The taking lens  12   a  is driven by an unshown DC motor in a lens drive mechanism  2 . The diaphragm  3  is driven by an unshown stepping motor in a diaphragm drive mechanism  4 . The Lucom  5  controls each of these motors in accordance with an instruction of the Bucom  50 .  
         [0059]     The following components are provided in the body unit  100  as shown in the drawing. For example, there are provided single lens reflex system components as an optical system, a shutter  14 , and an AF sensor unit  30   a  to receive light flux reflected from a sub mirror  13   d  for ranging. As the single lens reflex system components as the optical system, there are provided a pentaprism  13   a , a quick-return mirror  13   b , an eyepiece  13   c  and the sub mirror  13   d . Subsequently to the focal plane type shutter  14 , a CCD  27  is provided via a dustproof filter  21 , for photoelectric transfer of a subject image which has passed through the optical system.  
         [0060]     Furthermore, the dustproof filter  21  is provided with a piezoelectric element  22 , and the piezoelectric element  22  is vibrated by a dustproof filter drive circuit  48  to remove dust sticking to the dustproof filter  21 . It is to be noted that because the piezoelectric element  22  changes its characteristics with temperature, the Bucom  50  supplies a proper drive signal to the dustproof filter drive circuit  48  in accordance with a temperature measured by a temperature measurement circuit  33 .  
         [0061]     In the body unit  100 , there are further provided an AF sensor drive circuit  30   b , a mirror drive mechanism  18 , a shutter charge mechanism  19 , a shutter control circuit  31  and a photometric circuit  32 .  
         [0062]     The AF sensor drive circuit  30   b  drives and controls this AF sensor unit  30   a . The mirror drive mechanism  18  drives and controls the quick-return mirror  13   b . The shutter charge mechanism  19  drives a first (front) curtain and a second (rear) curtain of the shutter  14 . The shutter control circuit  31  controls the motion of the first (front) curtain and the second (rear) curtain. The photometric circuit  32  performs photometric processing based on light flux from the pentaprism  13   a.    
         [0063]     Furthermore, the shutter charge mechanism  19  and the shutter control circuit  31  exchange with the Bucom  50  signals to control the open/close operation of the shutter.  
         [0064]     This camera system is also provided with an image processing controller  40  which performs image processing by use of a CCD interface circuit  34  connected to the CCD  27 , a liquid crystal monitor  36 , and a SDRAM  38   a , a flash memory  38   b , the recording media  39   a ,  39   b  and the like that are provided as storage areas. Further, this camera system is configured so that it can provide an electronic recording display function as well as an electronic image pickup function.  
         [0065]     The recording media  39   a ,  39   b  are connected to the image processing controller  40  via the communication connectors  35   a ,  35   b , respectively, to exchange image pickup data. The packed state detection switch  118  which detects whether or not the memory cards  120  as the recording media  39   a ,  39   b  are inserted as a pack is connected to the Bucom  50 .  
         [0066]     The Bucom  50  is provided with the operation displaying LCD  57  which notifies the user of the operation state of the camera through a display output, and the camera operating switch  52 . The camera operating switch  52  is a switch group including operation buttons necessary to operate the camera, such as the release button  52   a , the mode dial  52   c  and the power switch  52   d . There are further provided the battery  54  as a power supply, a power supply circuit  53   a  which supplies the voltage of the power supply after converting it to a voltage required by each circuit unit of the camera system, and a power supply detection circuit  53   b.    
         [0067]     Each part of the camera system configured as described above operates as follows.  
         [0068]     The mirror drive mechanism  18  is a mechanism to drive the quick-return mirror  13   b  to an up position and a down position. When this quick-return mirror  13   b  is at the down position, light flux from the taking lens  12   a  is split and led to the AF sensor unit  30   a  side and the pentaprism  13   a  side.  
         [0069]     An output from an AF sensor in the AF sensor unit  30   a  is fed to the Bucom  50  via the AF sensor drive circuit  30   b  for known ranging processing.  
         [0070]     Furthermore, the user can view a subject from the eyepiece  13   c  adjacent to the pentaprism  13   a . On the other hand, part of the light flux which has passed through this pentaprism  13   a  leads to a photosensor (not shown) within the photometric circuit  32 , and on the basis of a light volume detected therein, the known ranging processing is performed.  
         [0071]     The shutter control circuit  31  receives a signal to drive and control the shutter from the Bucom  50 , and controls the operation of the shutter  14  in accordance with the signal. Further, the shutter control circuit  31  outputs, to a Bucom  150  at a predetermined time, a flash timing signal to cause the flash to emit light. The Bucom  50  outputs a light emission command signal to the flash unit  80  via communication in accordance with this flash timing signal.  
         [0072]     The image processing controller  40  controls the CCD interface circuit  34  in accordance with the command of the Bucom  50  to load image data from the CCD  27 . This image data is converted to a video signal by the image processing controller  40 , and output to and displayed on the liquid crystal monitor  36 . The user can check a taken image from an image displayed on the liquid crystal monitor  36 .  
         [0073]     The SDRAM  38   a  is a memory to temporarily store image data, and is used as a work area or the like when the image data is converted. Further, this image data is set, after converted into JPEG data, to be stored in the recording media  39   a ,  39   b . When storing image data taken in a sequential shooting mode, the image processing controller  40  controls a data transfer operation so that the image data is efficiently stored.  
         [0074]      FIG. 4  is a diagram showing how to equip an adapter  125  with memory cards  120   a ,  120   b.    
         [0075]     The memory cards  120   a ,  120   b  are respectively inserted into insert portions  126   a ,  126   b  provided in the adapter  125  which is a binding member, and are fixed by use of fixing screws  127   a ,  127   b . Thus, the plurality of memory cards  102  loaded in the adapter  125  is integrally installed into the insert portions  115   a ,  115   b  of the body unit  100  described above.  
         [0076]     In the meantime, a protrusion  128  provided in the adapter  125  presses the packed state detection switch  118  shown in  FIG. 2 , thereby detecting that the adapter  125  is installed.  
         [0077]     It is to be noted that the adapter  125  can be equipped with a plurality of memory cards without limiting to two memory cards. In addition, the fixing screws may be adapted to be attached to side surfaces of the adapter  125 .  
         [0078]     Furthermore, the memory cards  120   a ,  120   b  may be fixed to the adapter  125  by friction rather than the fixing screws, and may also be fixed to the adapter  125  by use of a pinch mechanism. Integral molding is also conceived.  
         [0079]      FIG. 5  is a diagram showing a backside of the adapter  125  equipped with the memory cards  120   a ,  120   b . A label is provided on the back of the adapter  125 , on which information (e.g., title, theme, photographing date) on the image data stored in the memory cards  120   a ,  120   b  can be written down. This makes it easy to organize data and to check contents. Naturally, the two memory cards may be installed without using such an adapter.  
         [0080]      FIG. 6  is a diagram showing image data recorded in the memory cards  120   a ,  120   b . As shown in this drawing, the image data is generally recorded in a distributed manner in a plurality of memory cards and is not recorded in order. As a consequence, it may often be difficult to manage data separately on each of the memory cards  120   a ,  120   b . In particular, when the memory cards  120   a ,  120   b  are separately kept together with other memory cards, it is difficult to extract the memory cards belonging to the same group.  
         [0081]     In the present embodiment, as the memory cards  120   a ,  120   b  are kept and handled integrally with the adapter  125 , data can be easily managed. In addition, since the label is provided, it is easy to know the contents and to organize the data.  
         [0082]      FIG. 7  is a diagram showing a memory card reader  135  to read the data recorded in the memory cards  120   a ,  120   b  through other equipment such as a PC.  
         [0083]     The memory card reader  135  is provided with insert portions  136   a ,  136   b  to insert the memory cards  120   a ,  120   b , and a packed state detection switch  138  to detect whether or not the memory cards  120   a ,  120   b  are inserted together with the adapter  125 .  
         [0084]     Furthermore, data in the memory cards  120   a ,  120   b  is transferred to the PC (not shown) via a connection plug  137 . Conversely, data in the PC is transferred to the memory cards  120   a ,  120   b  via the connection plug  137 .  
         [0085]      FIG. 8 ,  FIG. 9 ,  FIG. 11  and  FIG. 10  are schematic flowcharts showing transfer and recording operations of the image data in the digital camera. These operations are generally controlled by the Bucom  50  shown in  FIG. 3 .  
         [0086]     When the battery of the digital camera is loaded in step S 01 , an internal data area is initialized in step S 02 . More specifically, work areas of the SDRAM  38   a  and the flash memory  38   b , and a communication port are initialized.  
         [0087]     The state of the power switch  52   d  is checked, and if Yes in step S 03 , that is, when the power switch  52   d  is turned on and power is supplied to each part of the digital camera leading to an operable state, the memory cards  120   a  (card  1 ),  120   b  (card  2 ) as the recording media  39   a ,  39   b  are checked to see whether or not they are connected, in steps S 04  and S 06 .  
         [0088]     If Yes in steps S 04  and S 06 , that is, if the memory cards  120   a ,  120   b  are connected, File Allocation Table (FAT) information in the connected memory cards  120   a ,  120   b  is read, and information on free space or the like is obtained and stored, in steps S 05  and S 07 .  
         [0089]     Next, in step S 08 , the state of the packed state detection switch  118  is checked. That is, whether or not the memory cards  120   a ,  120   b  loaded in the adapter  125  are connected is checked. When the packed state detection switch  118  is turned in the memory cards  120   a ,  120   b  are considered that they should be handled in pairs, and a packed state flag which is internal data is set to “1” in step S 09 . When the packed state detection switch  118  is turned off, the memory cards  120   a ,  120   b  are considered that they should be handled separately, and the packed state flag which is the internal data is set to “0” in step S 10 .  
         [0090]     Subsequently, in steps S 11  and S 12 , each of the connected memory cards  120   a ,  120   b  is checked to see whether or not it has free space on the basis of the FAT information and the like. Here, when it is possible to take one or more images in a currently used image quality mode, it is judged that there is free space. When the memory cards  120   a ,  120   b  do not have any free space, a warning notifying of the same is displayed on the operation displaying LCD  57  in step S 13 .  
         [0091]     Next, it is checked in step S 21  to see whether or not the mode dial  52   c  and the setting dial  52   b  of the camera operating switch  52  are operated to newly set an exposure mode or the like, and when the exposure mode or the like has been newly set, preparatory processing to perform image pickup at the set value is executed in step S 22 .  
         [0092]     Furthermore, if No in step S 23 , waiting takes place until the release button  52   a  is operated. If Yes in step S 24 , that is, if it is detected that the release button  52   a  is pressed halfway, photometry is performed for exposure calculation in step S 25 , and in steps S 26  and S 27 , driving of the taking lens  12   a  of the lens unit  12  is controlled on the basis of the output from the AF sensor unit  30   a  to perform the focusing operation.  
         [0093]     Subsequently, if Yes in step S 28 , that is, if it is detected that the release button  52   a  is totally pressed, an exposure operation is performed in step S 29 . That is, the quick-return mirror  13   b  and the sub mirror  13   d  are moved out of an optical path, and the first (front) curtain and the second (rear) curtain of the shutter  14  are controlled, and then an optical image is formed on the CCD  27  only for a predetermined time.  
         [0094]     Furthermore, in step S 30 , the image taken from the CCD  27  and processed by the image processing controller  40  is transferred to and recorded in the recording media  39   a ,  39   b.    
         [0095]      FIG. 11  is a schematic flowchart showing a procedure to record an image in the recording media  39   a ,  39   b.    
         [0096]     If Yes in steps T 01  and T 02 , that is, if the packed state flag is checked to find out that the packed state flag is “1” and the memory card  120   a  has free space, the image is alternately transferred to the memory cards  120   a ,  120   b . For example, if Yes in step T 03 , that is, if a frame number of the taken image is odd, the image is recorded in the memory card  120   a  in step T 04 . If No in step T 03 , that is, if the frame number of the taken image is even, the image is recorded in the memory card  120   b  in step T 05 .  
         [0097]     The image is thus recorded alternately to allow simultaneous recording of the image in the memory cards  120   a ,  120   b , thereby enabling a reduction in data transfer time.  
         [0098]     However, if No in step T 02 , that is, if the memory card  120   a  does not have any free space, the image cannot be transferred alternately. Therefore, steps after step T 12  hereinafter described are then executed so that the image is transferred to the memory card  120   b.    
         [0099]     If No in step T 01 , that is, if the packed state flag is checked to find out that the packed state flag is “0”, the image is recorded in one of the memory cards.  
         [0100]     Thus, if Yes in step T 10 , that is, if the memory card  120   a  has free space, the image is recorded in the memory card  120   a  in step T 11 . If, however, the memory card  120   a  does not have any free space, the memory card  120   b  is checked to see whether or not it has free space in step T 12 .  
         [0101]     If Yes in step T 12 , that is, if the memory card  120   b  has free space, the image is recorded in the memory card  120   b  in step T 13 . If, however, the memory card  120   b  does not have any free space, a warning notifying that the image cannot be recorded is displayed on the operation displaying LCD  57  in step S 14 . It is to be noted that this judgment on whether or not there is free space is performed on the basis of the size of the image actually taken.  
         [0102]     Furthermore, in the processing shown in  FIG. 11 , the processing shown in steps T 01  to T 05  in which the image is allocated to and recorded in the memory cards  120   a ,  120   b  may be performed when the digital camera is taking an image in the sequential taking mode. In the sequential taking mode, many images are produced in a short period of time, so that it is necessary to efficiently write them into the memory cards  120   a ,  120   b . However, if not in the sequential taking mode, images are produced at long intervals, so that the writing into the recording media matters less.  
         [0103]     After the processing in step S 39  in  FIG. 9  has been performed as described above, the image data is moved to a particular recording medium at free time when the photographing operation is not performed.  
         [0104]     That is, in  FIG. 10 , if No in step S 35  and step S 36 , that is, if the release button  52   a  is neither operated nor pressed halfway, it is checked in step S 37  to see whether or not the image data is remaining in a buffer.  
         [0105]     If Yes in step S 37 , that is, if the image data is remaining in the buffer, the data is still being transferred to the recording medium, so that this processing to displace data is not performed. If No in step S 37 , that is, if the image data is not remaining in the buffer, it is checked in step S 38  to see whether or not the image data to be displaced remains in the memory card  120   b.    
         [0106]     If No in step S 38 , that is, if the image data to be displaced does not remain in the memory card  120   b , the displacement has already completed, and thus a further displacement operation is not performed.  
         [0107]     Furthermore, if Yes in step S 38  and step S 39 , that is, if the image data to be displaced is remaining in the memory card  120   b  and the memory card  120   a  has free space, one frame of the image in the memory card  120   b  is displaced to the memory card  120   a  in step S 40 .  
         [0108]     After one frame of the image data is displaced, the above-described processing is repeated back to step S 03  in  FIG. 8 .  
         [0109]      FIG. 12  is a diagram showing image data recorded in the memory cards. The image data in the memory card  120   b  has been totally displaced to the memory card  120   a . According to this embodiment, a plurality of memory cards is used during data recording to reduce the transfer time, and then the free space is utilized to integrate the data into one memory card. The user can thus manage data easily.  
         [0110]     Next, a procedure for data exchange between the recording media  39   a ,  39   b  and the image processing controller  40  will be described.  
         [0111]      FIG. 13  is a diagram showing signal connection between the recording media  39   a ,  39   b  and the image processing controller  40 .  
         [0112]     The image processing controller  40  and the communication connector  35   a  of the recording medium  39   a  is connected by address signals (A 000  to A 009 ), data signals (D 000  to D 015 ), a Write signal (WR 0 ), a Wait signal (WAIT 0 ) and a Chip_enable signal (CE 0 ).  
         [0113]     The address signals (A 000  to A 009 ) are signals for the image processing controller  40  to specify an address with which to write the image data into the recording medium  39   a . The data signals (D 000  to D 015 ) are signals for the image processing controller  40  to represent data to be transferred to the recording medium  39   a.    
         [0114]     The Write signal (WR 0 ) is a signal for the image processing controller  40  to specify timing with which to read data from the recording medium  39   a . The Wait signal (WAIT 0 ) is a signal for the recording medium  39   a  to request the image processing controller  40  to temporarily stop transfer of data. The Chip_enable signal (CE 0 ) is a signal to indicate that the image processing controller  40  selects the recording medium  39   a  as a destination.  
         [0115]     In the same manner, the image processing controller  40  and the communication connector  35   b  of the recording medium  39   b  is connected by address signals (A 100  to A 109 ), data signals (D 100  to D 115 ), a Write signal (WR 1 ), a Wait signal (WAIT 1 ) and a Chip_enable signal (CE 1 ). The contents of these signals are the same as those of the signals between the image processing controller  40  and the communication connector  35   a  and will not be described in detail.  
         [0116]      FIG. 14  is a flowchart showing a procedure in the image processing controller  40  to exchange data with the recording medium  39   a .  FIG. 15  is a diagram representing a timing chart of data exchange signals between the image processing controller  40  and the recording medium  39   a . A data exchange operation will be described referring to  FIG. 14 ,  FIG. 15 .  
         [0117]     In step R 01 , the image processing controller  40  brings the Chip_enable signal (CE 0 ) to a “H” level to notify that the data will be transferred to the recording medium  39   a . The recording medium  39   a  prepares to receive data.  
         [0118]     Next, in step R 02 , the image processing controller  40  outputs to an address port the addresses (A 000  to A 009 ) to write the image data. Here, address information to write image data has been obtained by the image processing controller  40  through a communication (not shown) performed before the start of this data exchange operation.  
         [0119]     Subsequently, the image processing controller  40  divides the image data to be transferred into a plurality of data. Then, with each of the divided data as a unit for each transmission, transmission is repeated to transfer the image data to the recording medium  39   a.    
         [0120]     In steps R 03 , R 04 , the image processing controller  40  outputs the initial data (D 000  to D 015 ) to a data port. Then, at the time when the output is stabilized, the Write signal (WR 0 ) is output in a pulsed manner. Here, time t 1  which is the pulse width and time t 2  which is the pulse period are optimum values that differ depending on the kind of the recording medium  39   a . The recording medium  39   a  reads the data (D 000  to D 015 ) set at the time when the Write signal (WR 0 ) is input.  
         [0121]     In step R 05 , this processing is repeated for a predetermined number of times, and the data transmission of a first transfer unit is performed. Therefore, if a predetermined number of times is 32, 16 bits×32=512 bits, that is, 64 bytes are the amount of data that is transferred in one transmission.  
         [0122]     The recording medium  39   a  which has received the data for one transmission unit starts writing data received from the specified addresses (A 000  to A 009 ) of the memory card  120   a . Along with this, the Wait signal (WAIT 0 ) is brought to the “H” level.  
         [0123]     In step R 06 , the image processing controller  40  temporarily stops the data transfer until the Wait signal (WAIT 0 ) reaches the “L” level. When the Wait signal (WAIT 0 ) has reached the “L” level, the addresses (A 000  to A 009 ) to be written next are calculated and output to the address port, thus starting data transfer for the next transmission unit, in steps R 02  to R 05 .  
         [0124]     The above transmission procedure is repeated, and if Yes in step R 07 , that is, if all the image data has been output, the Chip_enable signal (CE 0 ) is brought to the “L” level to notify that the data transfer to the recording medium  39   a  has finished, in step R 08 . The image processing controller  40  also transmits the image data to the recording medium  39   b  in accordance with the similar procedure.  
         [0125]     According to this embodiment, the image processing controller  40  can transmit data independently to the recording medium  39   a  and the recording medium  39   b , thereby enabling a reduction in the data transfer time.  
         [0126]      FIG. 16  is a diagram showing another example of signal connection between the recording media  39   a ,  39   b  and the image processing controller  40 .  
         [0127]     In this example, only one system of address signals (A 00  to A 09 ) and data signals (D 00  to D 15 ) is provided in the output of the image processing controller  40 . Further, part of the data signals (D 00  to D 10 ) and the address signals (A 00  to A 09 ) are shared to reduce the number of output ports.  
         [0128]     Furthermore, address signal latch circuits  141   a ,  141   b  and data signal latch circuits  142   a ,  142   b  are newly provided so that the address signals (A 00  to A 09 ) and the data signals (D 00  to D 15 ) are interfaced with the recording media  39   a ,  39   b . Further, address latch signals (LATCH_A 0 , LATCH_A 1 ) and data latch signals (LATCH_D 0 , LATCH_D 1 ) are provided in the output of the image processing controller  40 .  
         [0129]      FIG. 17A, 17B  are diagrams explaining the operation of the latch circuit.  FIG. 17A  shows an internal configuration of the latch circuit.  FIG. 17B  shows a truth table for the input/output operation of a part of a latch circuit  144  used for the latch circuit.  
         [0130]     In  FIG. 17A , D 0 , D 1 , . . . represent input data, and Q 0 , Q 1 , . . . represent output data. Further, CK is a latch signal, and {overscore (OE)} is an output enable signal. It is to be noted that the output enable signal has a bar added on top of OE in the drawing.  
         [0131]     According to the truth table of  FIG. 17B , when the output enable signal ({overscore (OE)}) is at the “H” level, the output data (Q 0 ) is fixed in a high impedance state. That is, the output value of the latch circuit  144  is always in a reset state.  
         [0132]     On the other hand, when the output enable signal ({overscore (OE)}) is at the “L” level and the latch signal (CK) has changed from “L” to “H”, the state of the input data (D 0 ) is set in the output data (Q 0 ).  
         [0133]     Moreover, when the output enable signal ({overscore (OE)}) is at the “L” level and the latch signal (CK) has changed from “H” to “L”, the output data (Q 0 ) maintains its state. That is, the output data is in a latched state.  
         [0134]      FIG. 18  is a diagram representing a timing chart of the data exchange signals between the image processing controller  40  and the recording media  39   a ,  39   b.    
         [0135]     The image processing controller  40  brings the Chip_enable signals (CE 0 , CE 1 ) to the “H” level to notify that the data will be transferred to the recording media  39   a ,  39   b . The recording media  39   a ,  39   b  prepare to receive data.  
         [0136]     Next, the image processing controller  40  outputs to the address port the addresses (A 00  to A 09 ) to write the image data into the recording medium  39   a . Here, address information to write image data has been obtained by the image processing controller  40  through a communication (not shown) performed before the start of this data exchange operation.  
         [0137]     Furthermore, the image processing controller  40  outputs the address latch signal (LATCH_A 0 ) in a pulsed manner. As described above, at the time when the address latch signal (LATCH_A 0 ) changes from “H” to “L”, the output of the latch circuit  141   a  is retained, and an address is set in the recording medium  39   a.    
         [0138]     Therefore, the image processing controller  40  outputs to the address port the addresses (A 00  to A 09 ) to write the image data into the recording medium  39   b . Further, the image processing controller  40  outputs the address latch signal (LATCH_A 1 ) in a pulsed manner. As described above, at the time when the address latch signal (LATCH_A 1 ) changes from “H” to “L”, the output of the latch circuit  141   b  is retained, and an address is set in the recording medium  39   b.    
         [0139]     Subsequently, the image processing controller  40  divides the image data to be transferred into a plurality of data, and with each of the divided data as a unit for each transmission, transmission is repeated to transfer the image data to the recording medium  39   a  and the recording medium  39   b.    
         [0140]     The image processing controller  40  outputs, to the data ports (D 00  to D 15 ), initial data to be transferred to the recording medium  39   a , and outputs the data latch signal (LATCH D 0 ) in a pulsed manner. As described above, at the time when the data latch signal (LATCH_D 0 ) changes from “H” to “L”, the output of the latch circuit  142   a  is retained, and data is set in the recording medium  39   a . At the time when the output is stabilized, the image processing controller  40  outputs the Write signal (WR 0 ) in a pulsed manner. The recording medium  39   a  reads the data (D 000  to D 015 ) set at the time when the Write signal (WR 0 ) is input.  
         [0141]     The image processing controller  40  outputs, to the data ports (D 00  to D 15 ), initial data to be transferred to the recording medium  39   b , and outputs the data latch signal (LATCH_D 1 ) in a pulsed manner. As described above, at the time when the data latch signal (LATCH_D 1 ) changes from “H” to “L”, the output of the latch circuit  142   b  is retained, and data is set in the recording medium  39   b . At the time when the output is stabilized, the image processing controller  40  outputs the Write signal (WR 1 ) in a pulsed manner. The recording medium  39   b  reads the data (D 000  to D 015 ) set at the time when the Write signal (WR 1 ) is input.  
         [0142]     This processing is repeated for a predetermined number of times, and the data transmission of the first transfer unit to the recording media  39   a ,  39   b  is performed. The recording media  39   a ,  39   b  which have received the data for one transmission unit start writing data received from the specified addresses (A 000  to A 009 , A 100  to A 109 ) of the data memories  120   a ,  120   b . Along with this, the Wait signals (WAIT 0 , WAIT 1 ) are brought to the “H” level.  
         [0143]     The image processing controller  40  temporarily stops the data transfer until the Wait signals (WAIT 0 , WAIT 1 ) reach the “L” level. When the Wait signals (WAIT 0 , WAIT 1 ) have reached the “L” level, the addresses (A 000  to A 009 ) to be written next are calculated and output to the address port. Thus, data transfer for the next transmission unit is started.  
         [0144]     The above transmission procedure is repeated, and when all the image data has been output, the Chip_enable signals (CE 0 , CE 1 ) are brought to the “L” level to notify that the data transfer to the recording media  39   a ,  39   b  has finished.  
         [0145]     Such a circuit configuration enables a reduction in the number of output ports of the image processing controller  40 , in addition to effects of the circuit configuration described above.  
         [0146]      FIG. 19  is a diagram showing another example of signal connection between the image processing controller  40  and a latch circuit  145  which is a part of the data latch circuit  142   a . In this example, the image processing controller  40  controls the levels “H”, “L” of the output enable signal (OE) to enable switching; data is output after latched or without being latched.  
         [0147]     That is, when the output enable signal (OE) is at the “L” level, a signal retained by the latch signal (LATCH) is output as the output data of the part of the latch circuit  145 , as described with regard to the circuit shown in  FIG. 17A .  
         [0148]     On the other hand, when the output enable signal ({overscore (OE)}) is at the “H” level, the output data of the part of the latch circuit  145  is reset, as described with regard to the circuits shown in  FIG. 17 . In this case, data signals from circuits other than the part of the latch circuit  145  are output by the output enable signal ({overscore (OE)}).  
         [0149]     Using this latch circuit, data can be transferred as in the above-described embodiment when there is a plurality of recording media, or data can be transferred, when there is one recording medium, using the Write signal (WR 0 ) alone without using the latch signal because the data does not need to be latched.  
         [0150]     That is, as shown in  FIG. 20 , the output enable signal ({overscore (OE)}) is brought to the “H” level in the case of one medium, and the output enable signal ({overscore (OE)}) is brought to the “L” level in the case of a plurality of media, thereby enabling the above-described operation.  
         [0151]      FIG. 21  is a diagram representing a timing chart of the signals when the image processing controller  40  exchanges data only with the recording medium  39   a . That is, it represents an operation for data exchange with one recording medium.  
         [0152]     The image processing controller  40  brings the Chip_enable signal (CE 0 ) to the “H” level to notify that the data will be transferred to the recording media  39   a . The recording media  39   a  prepares to receive data.  
         [0153]     Next, the image processing controller  40  outputs to the address port the addresses (AD 0  to A 09 ) to write the image data into the recording medium  39   a . Here, address information to write image data has been obtained by the image processing controller  40  through a communication (not shown) performed before the start of this data exchange operation.  
         [0154]     The image processing controller  40  outputs the address latch signal (LATCH_A 0 ) in a pulsed manner. As described above, at the time when the address latch signal (LATCH_A 0 ) changes from “H” to “L”, the output of the latch circuit  141   a  is retained, and an address is set in the recording medium  39   a.    
         [0155]     Subsequently, the image processing controller  40  divides the image data to be transferred into a plurality of data, and with each of the divided data as a unit for each transmission, transmission is repeated to transfer the image data to the recording medium  39   a.    
         [0156]     Therefore, the image processing controller  40  brings the output enable signal ({overscore (OE)}) to the “H” level. Thus, the data goes through the latch circuit and is output to the recording medium  39   a  as described with regard to the circuit shown in  FIG. 19 .  
         [0157]     The image processing controller  40  outputs to the data port the initial data (D 00  to D 15 ) to be transferred to the recording medium  39   a . Then, at the time when the output is stabilized, the Write signal (WR 0 ) is output in a pulsed manner. The recording medium  39   a  reads the data (D 000  to D 015 ) set at the time when the Write signal (WR 0 ) is input.  
         [0158]     This processing is repeated for a predetermined number of times, and the data transmission of the first transfer unit to the recording media  39   a  is performed. The recording media  39   a  which has received the data for one transmission unit starts writing data received from the specified addresses (A 000  to A 009 ) of the data memory  120   a , and along with this, the Wait signal (WAIT 0 ) is brought to the “H” level.  
         [0159]     Subsequently, the operation similar to the operation in the above-described circuit example is performed. That is, the image processing controller  40  temporarily stops the data transfer until the Wait signal (WAIT 0 ) reaches the “L” level. When the Wait signal (WAIT 0 ) has reached the “L” level, the addresses (A 000  to A 009 ) to be written next are calculated and output to the address port, thus starting data transfer for the next transmission unit. The above transmission procedure is repeated, and when all the image data has been output, the Chip-enable signals (CE 0 , CE 1 ) are brought to the “L” level to notify that the data transfer to the recording medium  39   a  has finished.  
         [0160]     According to this circuit example, data transfer methods can be easily switched and used suitable for the number of recording media.  
         [0161]      FIG. 22  is a diagram showing another example of signal connection between the recording media  39   a ,  39   b  and the image processing controller  40 .  
         [0162]     In this example, only one system of the address signals (ADD to A 09 ) and the data signals (D 00  to D 15 ) is provided in the output port of the image processing controller  40 . Further, part of the data signals (D 00  to D 10 ) and the address signals (AD 0  to A 09 ) are shared to reduce the number of output ports.  
         [0163]     Furthermore, in order to interface the address signals (ADD to A 09 ) with the recording media  39   a ,  39   b , the address signal latch circuits  141   a ,  141   b  are provided, and the address latch signals (LATCH_ 0 , LATCH_ 1 ) are provided in the output of the image processing controller  40 .  
         [0164]     On the other hand, the data signals (D 0 D to D 15 ) are directly connected to the recording media  39   a ,  39   b  on a common signal line without the latch circuit in between.  
         [0165]      FIG. 23  is a diagram representing a timing chart of the data exchange signals between the image processing controller  40  and the recording media  39   a ,  39   b.    
         [0166]     The image processing controller  40  brings the Chip_enable signals (CE 0 , CE 1 ) to the “H” level to notify that the data will be transferred to the recording media  39   a ,  39   b . The recording media  39   a ,  39   b  prepare to receive data.  
         [0167]     Next, the image processing controller  40  outputs to the address port the addresses (A 00  to A 09 ) to write the image data into the recording medium  39   a . Here, address information to write image data has been obtained by the image processing controller  40  through a communication (not shown) performed before the start of this data exchange operation.  
         [0168]     Furthermore, the image processing controller  40  outputs the address latch signal (LATCH 0 ) in a pulsed manner. As described above, at the time when the address latch signal (LATCH 0 ) changes from “H” to “L”, the output of the latch circuit  141   a  is retained, and an address is set in the recording medium  39   a.    
         [0169]     Subsequently, the image processing controller  40  outputs to the address port the addresses (A 00  to A 09 ) to write the image data into the recording medium  39   b . Further, the image processing controller  40  outputs the address latch signal (LATCH 1 ) in a pulsed manner. As described above, at the time when the address latch signal (LATCH 1 ) changes from “H” to “L”, the output of the latch circuit  141   b  is retained, and an address is set in the recording medium  39   b.    
         [0170]     Subsequently, the image processing controller  40  divides the image data to be transferred into a plurality of data, and with each of the divided data as a unit for each transmission, transmission is repeated to transfer the image data to the recording medium.  
         [0171]     The image processing controller  40  outputs to the data port (D 00  to D 15 ) the initial data to be transferred to the recording medium  39   a . Then, at the time when the output is stabilized, the image processing controller  40  outputs the Write signal (WR 0 ) in a pulsed manner. The recording medium  39   a  reads the data (D 000  to D 015 ) set at the time when the Write signal (WR 0 ) is input.  
         [0172]     Next, the image processing controller  40  outputs to the data port (D 00  to D 15 ) the initial data to be transferred to the recording medium  39   b , and, at the time when the output is stabilized, outputs the Write signal (WR 1 ) in a pulsed manner. The recording medium  39   b  reads the data (D 100  to D 115 ) set at the time when the Write signal (WR 1 ) is input.  
         [0173]     The above processing is repeated for a predetermined number of times, and the data transmission of the first transfer unit to the recording media  39   a ,  39   b  is performed. The-recording media  39   a ,  39   b  which have received the data for one transmission unit start writing data received from the specified addresses (A 000  to A 009 , A 100  to A 109 ) of the data memories  120   a ,  120   b . Along with this, the Wait signals (WAIT 0 , WAIT 1 ) are brought to the “H” level.  
         [0174]     The image processing controller  40  temporarily stops the data transfer until the Wait signals (WAIT 0 , WAIT 1 ) reach the “L” level. When the Wait signals (WAIT 0 , WAIT 1 ) have reached the “L” level, the addresses (AD 0  to A 09 ) to be written next are calculated and output to the address port, thus starting data transfer for the next transmission unit.  
         [0175]     The above transmission procedure is repeated, and when all the image data has been output, the Chip_enable signals (CE 0 , CE 1 ) are brought to the “L” level to notify that the data transfer to the recording media  39   a ,  39   b  has finished.  
         [0176]     This makes it possible to further simplify the circuit configuration.  
         [0177]     Incidentally, when a plurality of recording media is used in combination, it is preferable that they can be identified as a pair. Therefore, a method will be described which verifies whether or not the memory cards  120  to be inserted into the recording media  39   a ,  39   b  are based on a particular combination. In the embodiment according to the present invention, combination identification information for identification of a predetermined combination is provided in the memory cards  120 .  
         [0178]      FIG. 24  is a diagram showing one embodiment associated with the combination identification information.  
         [0179]     In the memory cards  120   a ,  120   b , exclusive identification files  122   a ,  122   b  are stored together with image data  121   a ,  121   b  allocated by the image processing controller  40 . These exclusive identification files  122   a ,  122   b  have the combination identification information indicating that the memory card  120   a  and the memory card  120   b  are based on a predetermined combination.  
         [0180]     The exclusive identification files  122   a ,  122   b  shown in  FIG. 25  carry “date+segment code” as the combination identification information. That is, the exclusive identification file  122   a  shown in  FIG. 25  carries “2003jan251030” corresponding to the date and time when the file is made and “a” corresponding to the segment code, as the combination identification information. The exclusive identification file  122 b shown in  FIG. 25  carries “2003jan251030” corresponding to the date and time and “b” corresponding to the segment code, as the combination identification information. Therefore, in this example, it is possible to recognize that the memory cards storing the combination identification information in which the last characters alone are different are based on the predetermined combination.  
         [0181]      FIG. 26  is a diagram showing another embodiment associated with the combination identification information.  
         [0182]     In the memory cards  120   a ,  120   b , exclusive identification files  123   a ,  123   b  are stored together with the image data  121   a ,  121   b  allocated by the image processing controller  40 . For file names of these exclusive identification files  123   a ,  123   b , the combination identification information is used which indicates that the memory card  120   a  and the memory card  120   b  are based on a predetermined combination.  
         [0183]     In the exclusive identification files  123   a ,  123   b  shown in  FIG. 26 , “date+segment code” is defined as a file name based on the combination identification information. That is, the file name of the exclusive identification file  123   a  is “YYMMDDa” which is a combination of “YYMMDD” corresponding to the date and “a” corresponding to the segment code. The file name of the exclusive identification file  123   b  is “YYMMDDb” which is a combination of “YYMMDD” corresponding to the date and “b” corresponding to the segment code. Therefore, in this example, it is possible to recognize that the memory cards storing the combination identification information in which the last characters alone are different in the file names are based on the predetermined combination.  
         [0184]      FIG. 27  is a diagram showing another embodiment associated with the combination identification information.  
         [0185]     In the memory cards  120   a ,  120   b , the image data  121   a ,  121   b  allocated by the image processing controller  40  are stored. Further, their volume labels  124   a ,  124   b  carry the combination identification information indicating that the memory card  120   a  and the memory card  120   b  are based on a predetermined combination.  
         [0186]     In the volume labels  124   a ,  124   b  shown in  FIG. 27 , “date+segment code” is defined as label name based on the combination identification information. That is, the file name of the volume label  124   a  is “YYMMDDa” as in the embodiment described above. The file name of the volume label  124   b  is “YYMMDDb” as in the embodiment described above. Therefore, in this example, it is possible to recognize that the memory cards in which the last characters alone are different in the volume names are based on the predetermined combination.  
         [0187]     It is to be noted that the combination identification information is not limited to the date information in the embodiments described above, any combination identification information can be applied as long as it uses unified signs. For example, codes generated at random may be used. Moreover, codes generated in other methods can also be used as the combination identification information as long as they are mutually unified and are unique in practical use.  
         [0188]      FIG. 28 ,  FIG. 29  and  FIG. 30  are schematic flowcharts showing the transfer and recording operations of the image data in the digital camera. These operations are generally controlled by the Bucom  50  shown in  FIG. 3 .  
         [0189]     When the battery of the digital camera is loaded in step S 101 , the internal data area is initialized in step S 102 . More specifically, the work areas of the SDRAM  38   a  and the flash ROM  38   b , and the communication port are initialized.  
         [0190]     The state of the power switch  52   d  is checked, and if Yes in step S 103 , that is, when the power switch  52   d  is turned on and power is supplied to each part of the digital camera leading to an operable state, whether or not the memory cards  120   a  (card  1 ),  120   b  (card  2 ) are connected to the recording media  39   a ,  39   b  is checked, in steps S 104  and S 106 .  
         [0191]     If Yes in steps S 104  and S 106 , that is, if the memory cards  120   a ,  120   b  are connected, the file allocation table (FAT) information in the connected memory cards  120   a ,  120   b  is read, and information on free space or the like is obtained and stored, in steps S 105  and S 107 .  
         [0192]     Next, in step S 108 , whether or not the memory cards  120   a ,  120   b  have the combination identification information is checked.  
         [0193]     If No in step S 108  and Yes in step S 109 , that is, if the memory cards  120   a ,  120   b  do not have the combination identification information and the image data is stored in the memory cards  120   a ,  120   b , a warning is issued in steps S 110  and  111  that the incorrect memory cards  120   a ,  120   b  might be used, and an instruction is additionally displayed on the operation displaying LCD to require an input that indicates whether or not the operation should be continued, thus moving to a standby state.  
         [0194]     If the photographer discontinues the operation, he switches off the power switch  52 d, changes the memory cards, and starts again the processing from the beginning.  
         [0195]     On the other hand, if Yes in step S 111 , that is., if the photographer inputs to continue the operation, or if No in step S 109 , that is, if the image data is not stored in the memory cards  120   a ,  120   b , the combination identification information is newly generated in step S 112 .  
         [0196]     Subsequently, the combination identification information in the memory cards  120   a ,  120   b  is compared to check whether or not they are based on a predetermined combination, in steps S 113  and  114 .  
         [0197]     If Yes in step S 114 , that is, if they are based on the predetermined combination, a pair flag is set to “1”. If No in step S 114 , that is, if they are not based on the predetermined combination, a warning is displayed in steps S 116  and  117  that the incorrect combination of memory cards  120   a ,  120   b  is used, and the pair flag is set to “0”.  
         [0198]     Subsequently, each of the connected memory cards  120   a ,  120   b  is checked on the basis of the FAT information or the like in steps S 118  and  119  to see whether or not it has free space. Here, when it is possible to take one or more images in the currently used image quality mode, it is judged that there is free space. When the memory cards  120   a ,  120   b  do not have any free space, a warning notifying of the same is displayed on the operation displaying LCD  57  in step S 120 .  
         [0199]     Next, it is checked in step S 121  to see whether or not the mode dial  52   c  and the setting dial  52   b  of the camera operating switch  52  have been operated to newly set the exposure mode or the like. When the exposure mode or the like has been newly set, preparatory processing to perform image pickup at the set value is executed in step S 122 .  
         [0200]     Furthermore, if No in step S 123 , waiting takes place until the release button  52   a  is operated. If Yes in step S 124 , that is, if it is detected that the release button  52   a  is pressed halfway, photometry is performed for exposure calculation in step S 125 . Then, in steps S 126  and S 127 , the driving of the taking lens  12   a  of the lens unit  12  is controlled on the basis of the output from the AF sensor unit  30   a  to perform the focusing operation.  
         [0201]     Subsequently, if Yes in step S 128 , that is, if it is detected that the release button  52   a  is totally pressed, an exposure operation is performed in step S 129 . That is, the quick-return mirror  13   b  and the sub mirror  13   d  are moved out of the optical path, and the first (front) curtain and the second (rear) curtain of the shutter  14  are controlled, and then an optical image is formed on the CCD  27  only for a predetermined time.  
         [0202]     Furthermore, in step S 130 , the image taken from the CCD  27  and processed by the image processing controller  40  is transferred to and recorded in the recording media  39   a ,  39   b.    
         [0203]      FIG. 30  is a schematic flowchart showing a procedure to record an image in the recording media  39   a ,  39   b.    
         [0204]     If Yes in step T 101 , that is, if the pair flag is checked to find out that the pair flag is “1”, the image is alternately transferred to the recording media  39   a ,  39   b . For example, if Yes in step T 102 , that is, if the frame number of the taken image is odd, the image is recorded in the memory card  120   a  in step T 103 . If No in step T 102 , that is, if the frame number of the taken image is even, the image is recorded in the memory card  120   b  in step T 104 .  
         [0205]     The image is thus recorded alternately to allow simultaneous recording of the image in the memory cards  120   a ,  120   b . Thereby, the data transfer time can be reduced.  
         [0206]     If No in step T 101 , that is, if the pair flag is checked to find out that the pair flag is “0”, the image is recorded in one of the memory cards.  
         [0207]     Thus, if Yes in step T 110 , that is, if the memory card  120   a  has free space, the image is transferred to the recording medium  39   a  and recorded in the memory card  120   a  in step T 111 . However, If No in step T 110 , that is, if the memory card  120   a  does not have any free space, the memory card  120   b  is checked to see whether or not it has free space in step T 112 .  
         [0208]     If Yes in step T 112 , that is, if the memory card  120   b  has free space, the image is transferred to the recording medium  39   b  and recorded in the memory card  120   b  in step T 113 . However, If No in step T 112 , that is, if the memory card  120   b  does not have any free space, a warning notifying that the image cannot be recorded is displayed on the operation displaying LCD  57  in step S 114 . It is to be noted that this judgment on whether or not there is free space is performed on the basis of the size of the image actually taken.  
         [0209]     Furthermore, in the processing shown in  FIG. 30  where the image is recorded in the recording media  39   a ,  39   b , the processing shown in steps T 101  to T 104  in which the image is allocated to and recorded in the memory cards  120   a ,  120   b  may be performed when the digital camera is taking the image in the sequential taking mode. In the sequential taking mode, many images are produced in a short period, so that it is necessary to efficiently write them into the recording media  39   a ,  39   b . However, if not in the sequential taking mode, images are produced at long intervals, so that the writing into the recording media matters less.  
         [0210]     After the processing in step S 129  in  FIG. 29  has been performed as described above, the above-described processing is repeated back to step S 103  in  FIG. 28 .  
         [0211]     It is to be noted that the combination identification information may be folder names instead of file names.  
         [0212]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general invention concept as defined by the appended claims and their equivalents.