Abstract:
A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    The priority of Korean patent application number 10-2007-0050788, filed on May 25, 2007, which is incorporated by reference in its entirety, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor comprising a fin-transistor and a method for fabricating the same. 
         [0003]    In a fin-channel-array-transistor (“FCAT”), a channel width of fine channel transistors is determined by a short width of an active region mask. That is, since a width of a gate is equal to the short width of the active region mask in a semiconductor device [e.g., Dynamic Random Access Memory (“DRAM”)], the fine channel transistor should not be smaller than a length between source/drains adjacent to a channel width. The fin channel transistor can reduce the short channel effects (“SCE”) as the channel width becomes smaller, by increasing the effective channel width. However, there is a limit to how much the channel width of the fin channel transistor can be reduced because it is necessary to secure an area for the source/drain contact regions. 
         [0004]    Since a recess gate mask for forming a fin channel transistor has a line/space type pattern, a gate electrode formed over a device isolation structure is separated from a storage node junction region by a gate insulating film, thereby increasing a parasitic capacitance of the gate electrode. The parasitic capacitance of the gate electrode degrades the operation speed of the cell transistor. Also, leakage current is increased in the storage node junction region due to a gate induced drain leakage (“GIDL”) effect, thereby degrading refresh characteristics of the DRAM. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    Embodiments of the invention are directed to a fin gate in a semiconductor device. According to one embodiment, the fin gate is formed in a fin-type active region of a semiconductor device where the line width is smaller than the width of source/drains, thereby reducing short channel effects. 
         [0006]    According to one embodiment, a semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The second active area is formed as a portion of a fin gate, and the first active area is formed growing a semiconductor substrate between the neighboring gates as a seed layer. In a longitudinal direction of the gate, a line width of the first active area is greater than the width of the second active area. 
         [0007]    According to another embodiment, a method for fabricating a semiconductor device comprises: forming a device isolation structure over a semiconductor substrate to define an active region including a first active area and a second active area, wherein the second active area is formed as a portion of a fin gate, and the first active region is formed growing the semiconductor substrate between two neighboring gates as a seed layer, wherein a line width of the first active region is greater than the width of the second active region; etching a portion of the device isolation structure overlapping the gate by using a recess mask to form a recess; and forming the fin gate including a gate conductive layer to fill the recess. 
         [0008]    In one embodiment, a method of fabricating a semiconductor device having a fin gate includes forming first and second trenches on a semiconductor substrate to define a protruding portion between the first and second trenches; etching a portion of the protruding portion to define first, second, and third recesses, the first recess being adjacent to the first trench, the second recess being adjacent to the second trench, the third recess being defined between the first and second recesses; and performing a selective epitaxial process on the semiconductor substrate to grow semiconductor material at the first, second, and third recess to form a first active region. 
         [0009]    In another embodiment, the method further includes forming a first insulation layer within the first and second trenches, the first insulation layer having an upper surface that is provided below an upper surface of the protruding portion. The semiconductor material grown by the epitaxial process extends partly over the first insulation layer provided at the first and second trenches. The protruding portion is used to define the fin gate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a layout illustrating a semiconductor device according to an embodiment of the invention; 
           [0011]      FIG. 2  is a cross-sectional view illustrating a semiconductor device according to an embodiment of the invention; 
           [0012]      FIGS. 3   a  through  3   h  are cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention; 
           [0013]      FIG. 4  is a cross-sectional view illustrating a method for fabricating a semiconductor device according to another embodiment of the invention; and 
           [0014]      FIG. 5  is a layout illustrating a semiconductor device according to another embodiment of the invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0015]      FIG. 1  is a layout illustrating a semiconductor device according to an embodiment of the invention. The semiconductor device comprises of an active region  100  defined by a device isolation region  120 , a fin gate region  102 , and a gate region  104 . A fin transistor is formed in fin gate region  102 . Active region  100  includes a first active region  106  that is to become source/drains and a second active region  108  overlapping with a gate region  104 . A longitudinal direction of gate region  104  is defined as a “vertical direction”, and a longitudinal direction of active region  100  is defined as a “horizontal direction”. Fin gate region  102  is formed in a line type, and overlaps with second active region  108 . In the vertical direction, the line width of first active region  106  is F, and the line width of second region  108  is G (where 7F/20&lt;G&lt;19F/20 and F is a distance between the neighboring two gate regions). Gate region  102  is not limited to a line type. In another embodiment of the invention, a fin gate region  502  as shown in  FIG. 5  is formed in an island type. 
         [0016]      FIG. 2  is a cross-sectional view illustrating a semiconductor device according to an embodiment of the invention.  FIG. 2  (i) is a cross-sectional view taken along I-I′ of  FIG. 1 .  FIG. 2  (ii) is a cross-sectional view taken along II-II′ of  FIG. 1 .  FIG. 2  (iii) is a cross-sectional view taken along III-III′ of  FIG. 1 . The semiconductor device comprises a device isolation structure  220 , a silicon epitaxial growth layer  230 , a fin-type active region  238 , and a fin gate structure  280 . Device isolation structure  220  defines an active region including silicon epitaxial growth layer  230 . Fin gate structure  280  is disposed over fin-type active region  238 . 
         [0017]    A portion of a semiconductor substrate  210  of a first active region  106  of  FIG. 1  is selectively etched. A thermal treatment process is performed on the selectively etched semiconductor substrate  210  as a seed layer, to form silicon epitaxial growth layer  230 . A depth of the etched semiconductor substrate  210  is in a range of about 10 nm to 100 nm. The thermal treatment process is performed under a H 2  atmosphere at a temperature in a range of about 500° C. to 1,000° C. A plasma cleaning process including SF 6 /H 2  is performed on the etched semiconductor substrate  210 . The plasma cleaning process and the thermal treatment process are performed by an in-situ method. 
         [0018]    Device isolation structure  220  is formed to have a stacked structure having a first device isolation insulating film  216  and a second device isolation insulating film  218 . Fin gate structure  280  is formed to have a stacked structure having a lower gate electrode  252 , an upper gate electrode  262 , and a gate hard mask layer  272  over a gate insulating film  240 . 
         [0019]      FIGS. 3   a  to  3   h  are cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention.  FIGS. 3   a  (i) to  3   h  (i) are cross-sectional views taken along I-I′ of  FIG. 1 .  FIGS. 3   a  (ii) to  3   h  (ii) are cross-sectional views taken along II-II′ of  FIG. 1 .  FIG. 3   a  (iii) to  3   h  (iii) are cross-sectional views taken along III-III′ of  FIG. 1 . 
         [0020]    A pad insulating film  312  is formed over a semiconductor substrate  310 . A portion of pad insulating film  312  and semiconductor substrate  310  are selectively etched using a device isolation mask (not shown) as an etching mask, to form a trench  314  that defines active region  100  of  FIG. 1 . A first insulating film for device isolation  316  is formed to fill a portion of trench  314 . In the vertical direction, a width of the device isolation mask becomes smaller so that a distance between neighboring active regions  100  becomes broader. As a result, a deposition margin of first insulating film for device isolation  316  can be increased. 
         [0021]    Referring to  FIGS. 3   c  and  3   d , pad insulating film  312  and a portion of underlying semiconductor substrate  310  in first active region  106  of  FIG. 1  are selectively etched to form a recess  322 . A selective epitaxial process is performed on a surface of semiconductor substrate  310  as a seed layer in the recess  322  to form a silicon epitaxial growth layer  330 . Pad insulating film  312  is disposed over semiconductor substrate  310  in second active region  108  of  FIG. 1 , so that silicon epitaxial growth layer  330  is not formed in second active region  108 . Silicon epitaxial growth layer  330  is grown toward the upper surface and the side surface of semiconductor substrate  310 , so that, in the vertical direction, a width of first active region  106  may be substantially equal to the distance F between the two neighboring gates. 
         [0022]    A depth of semiconductor substrate  310  exposed in recess  322  is in a range of about 10 to 100 nm. Silicon epitaxial growth layer  330  includes an undoped silicon layer. The selective epitaxial process for forming silicon epitaxial silicon growth layer  330  is performed by a thermal treatment process. The thermal treatment process is performed under a H 2  atmosphere at a temperature in a range of about 500° C. to 1,000° C. A plasma cleaning process including SF 6 /H 2  is performed on the etched semiconductor substrate  310 . The plasma cleaning process and the thermal treatment process are performed by an in-situ method. 
         [0023]    In one embodiment, in the vertical direction, the line width of silicon epitaxial growth layer  330  is F, and the line width of semiconductor substrate  310  in second active region  108  is G (where 7F/20&lt;G&lt;19F/20 and F is a distance between the neighboring two gates). 
         [0024]    Referring to  FIG. 3   e , a second insulating film for device isolation  318  is formed over semiconductor substrate  310  to fill trench  314 . Second insulating film for device isolation  318  is polished (or removed) until silicon epitaxial growth layer  330  is exposed, to form a device isolation structure  320 . Device isolation structure  320  has a stacked structure including first insulating film for device isolation  316  and second insulating film for device isolation  318 . 
         [0025]    Referring to  FIG. 3   f , a hard mask layer  332  is formed over semiconductor substrate  310 . A photoresist film (not shown) is formed over hard mask layer  332 . The photoresist film is exposed and developed using a mask (not shown) that defines fin gate region  102  of  FIG. 1 , to form a photoresist pattern  334 . Hard mask layer  332  and a portion of device isolation structure  320  are selectively etched using photoresist pattern  334  as a mask, to form a fin gate recess  336  that exposes a fin type active region  338 . 
         [0026]    Referring to  FIGS. 3   g  and  3   h , hard mask layer  332  and photoresist pattern  334  are removed to expose semiconductor substrate  310  and a surface of fin type active region  338 . A gate insulating film  340  is formed over semiconductor substrate  310  and a surface of fin type active region  338 . A lower gate conductive layer  350  is formed over gate insulating film  340  to fill fin gate recess  336 . An upper gate conductive layer  360  and a gate hard mask layer  370  are formed over lower gate conductive layer  350 . Gate hard mask layer  370 , upper gate conductive layer  360  and lower gate conductive layer  350  are patterned using a gate mask (not shown) to form a fin gate structure  380  having a stacked structure including a gate hard mask pattern  372 , an upper gate electrode  362  and a lower gate electrode  352 . 
         [0027]      FIG. 4  is a cross-sectional view illustrating a method for fabricating a semiconductor device according to an embodiment of the invention. A selective epitaxial process is performed on a semiconductor substrate  410  exposed in recess  322  of  FIG. 3   c  as a seed layer, to form a silicon epitaxial growth layer  430 . A pad insulating film  412  is disposed over semiconductor substrate  410  in second active region  108  of  FIG. 1 , so that silicon epitaxial growth layer  430  is not formed. 
         [0028]    Silicon epitaxial growth layer  430  is formed of an impurity doped silicon layer. In one implementation, the impurity of silicon epitaxial growth layer  430  is selected from the group of consisting of B, BF 2 , As, P, and combinations thereof. In other implementations, the impurity of silicon epitaxial growth layer  430  may be selected from other groups. Impurity doping concentration is in a range of about 1E18 ions/cm 2  to 5E20 ions/cm 2 . The impurity doping concentration required for silicon epitaxial growth layer  430  is not limited. 
         [0029]    As described above, in a semiconductor device and a method for fabricating the same according to an embodiment of the invention, a second active region (or source/drains) is formed of a silicon epitaxial growth layer. In the vertical direction, a line width of a first active region (or a gate region) is formed to be smaller than the width of a second active region, thereby improving short channel effects such as DIBL. In a device isolation structure, an initial interval between the active regions becomes broader to increase a gap-fill margin. 
         [0030]    The above embodiments of the invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.