Abstract:
An apparatus and methodology for operating an automatic darkening filter (ADF) eye protection device alternately applies an operating voltage to a pair of control terminals of an ADF device circuit in a continuing sequence, where a first polarity voltage is applied to the pair of terminals and then reversed. A delay period is provided between application of the alternating polarities. In some embodiments ground potential is applied to both terminals of the pair of terminals during the delay period.

Description:
FIELD OF THE INVENTION 
     The present subject matter relates generally to automatic darkening filter (ADF) eye protection devices, and more particularly to ADF devices having an improved drive circuit. 
     BACKGROUND OF THE INVENTION 
     Automatic darkening filter (ADF) eye protection devices are employed in a number of fields. One such field is welding where ADF technology provides protection for welders&#39; eyes from the intense light levels generated in the welding process. Eye protection devices may also be used in other areas where bright light may be generated such as from lasers, explosives, etc. 
     ADF systems often include a liquid crystal device (LCD) that is generally driven with shade voltages applied across the filter corresponding to an alternating current (AC) square wave, To provide this square wave voltage, the voltage polarity across the filter is constantly being reversed. According to current technology, when the polarity of the voltage across the filter is switched from positive to negative or negative to positive, it is switched very close to instantaneously. Such near instantaneous switching causes high peak currents that stress electronic components and produce high battery drain. 
     In view of these known disadvantages, it would be advantageous to provide a mechanism for ADF circuitry that eliminates, or at least significantly reduces, the previously experienced high battery drain and component stress. 
     SUMMARY OF THE INVENTION 
     Aspects and advantages of the invention will be set forth in part in the following description, or may be obvious from the description, or may be learned through practice of the invention. 
     In view of the recognized disadvantages encountered in the prior art and addressed by the present subject matter, an improved circuit is provided for operating an automatic darkening filter (ADF) comprising a liquid crystal device (LCD) filter having first and second control terminals to which are coupled first through fourth driver circuits. First through fourth time delay circuits are associated with each of the first through fourth driver circuits. The timer circuits, under control of a switch control circuit, operate to delay application of control voltages to the LCD filter control terminals so that the polarity of an applied control voltage is sequentially reversed periodically based on the time delay produced by the time delay circuits and the operating frequency of a signal applied to a switch control circuit. 
     In certain embodiments, a ground reference voltage is applied to both control terminals of the liquid crystal device (LCD) filter during the delay periods produced by the time delay circuits. 
     In accordance with further aspects of the present subject matter, methodologies have been developed for operating an automatic darkening filter (ADF) circuit comprising alternately reversing the polarity of a voltage supply applied to a pair of control terminals for the ADF circuit. In certain embodiments, the method provides for delaying application of the voltage supply in a first polarity for a predetermined time following removal of the voltage applied at a second polarity. 
     In some embodiments, the method also provides for delaying application of the voltage supply to the pair of control terminals at a second polarity for a predetermined time following removal of the supply applied at the first polarity. In certain other embodiments, the predetermined time is determined based on the time required to charge a capacitor through a resistor to a predetermined voltage level. In still further embodiments, a reference potential is applied to both control terminals during the predetermined time. 
     Additional objects and advantages of the present subject matter are set forth in, or will be apparent to, those of ordinary skill in the art from the following detailed description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A full and enabling disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in the specification, which makes reference to the appended figures, in which: 
         FIG. 1  is a perspective view of an ADF weld helmet that may utilize the improved driver circuitry according to aspects of the present invention; 
         FIG. 2  is a schematic block diagram of a circuit for use as an automatic darkening filter driver circuit in accordance with present technology; and 
         FIG. 3  is a group of waveforms illustrating voltage levels at various points of the circuit diagram of  FIG. 2  useful in understanding the operation of the circuit. 
     
    
    
     Repeat use of reference characters throughout the present specification and appended drawings is intended to represent same or analogous features or elements of the invention. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference now will be made in detail to embodiments of the invention, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the invention, not limitation of the invention. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For instance, features illustrated or described as part of one embodiment can be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present invention include such modifications and variations as come within the scope of the appended claims and their equivalents. 
     As discussed in the Summary of the Invention section, the present subject matter is particularly concerned with automatic darkening filter (ADF) devices and systems having improved driver circuits. The present invention is not limited to any particular type of ADF system or device. As mentioned, a well-known use of ADF systems is in weld helmets and, in this regard, an ADF weld helmet  100  is depicted in  FIG. 1  for illustrative purposes only. The weld helmet  100  includes, among other features, an LCD lens  102  on its front side or face. LCD lens  102  is positioned directly in front of the eyes of the wearer, thereby functioning as the viewing window. 
     Referring now to  FIG. 2 , there is illustrated a schematic block diagram of a circuit  200  for use as an ADF driver circuit usable with weld helmet  100  in accordance with aspects of the invention. As is understood by those of ordinary skill in the art, ADF devices generally include a liquid crystal device (LCD) filter  202  that is configured to be placed between a user&#39;s eyes and an intense light source for protection of the user&#39;s eyes. LCD filter  202  is configured to be pulsed by four drivers corresponding to left upper driver  204 , left lower driver  206 , right upper driver  214 , and right lower driver  216  by application of alternating polarity pulses across terminals  222 ,  242  of LCD filter  202 . Drivers  204 ,  206 ,  214 ,  216  are turned on and off in pairs to form an H-bridge. In such a configuration, left upper driver  204  and right lower driver  216  are on at the same time while left lower driver  206  and right upper driver  214  are off. In alternating fashion, right upper driver  214  and left lower driver  206  are on at the same time while right lower driver  216  and left upper driver  204  are off. 
     Each driver includes a control pin  224 ,  226 ,  234 ,  236  configured to receive a control voltage that, if of sufficient magnitude, that is, if above a predetermined threshold voltage level, will turn the driver on; otherwise the driver will be turned off. The predetermined threshold level may be established by a comparator or threshold circuit that is a part of the driver circuit. 
     The four drivers  204 ,  206 ,  214 ,  216  are controlled by two control switches S 1  and S 2 . Switch S 1  is configured to control the left upper driver  204  and right lower driver  216  as schematically illustrated by designations S 1   a  and Si b , respectively. Switch S 2  is configured to control the lower left driver  206  and upper right driver  214  as schematically illustrated by designations S 2   a  and S 2   b , respectively. 
     In operation, an electrical input signal is applied to Signal In line  240  to provide control signals to both control switches S 1  and S 2 . The signal applied to line  240  may correspond to a square wave with amplitudes corresponding to logic high and logic low voltages. Switches S 1  and S 2  are configured such that during logic high, S 1  is on and S 2  is off while during logic low, S 1  is off and S 2  is on. 
     In accordance with the present technology, a delay component has been added so as to delay the operations of the switch S 1   a , Si b , S 2   a  and S 2   b.  The delay insures that there is no overlap of conduction states between the left and right side drivers that would result in a momentary shunting of the Shade Voltage supply to the lower drive voltage which may be at ground potential or anther suitable voltage level, accompanied by a resultant spike in current drawn from the Shade Voltage supply. The Shade Voltage supply, along with other operating voltages including the On Voltage and Off Voltage may be derived from an unillustrated relatively low voltage battery power supply. 
     As may be seen from a further inspection of  FIG. 2 , each drive circuit includes a series connected resistor and capacitor, generally indicated as R n  and C n  (where n ranges from 1 to 4), at whose junction a ramp voltage is produced depending on the values of the resistor and capacitor and the applied voltages. Thus, for example, resistor R 1  and capacitor C 1  are included in the input circuit to left upper driver  204 . Resistor R 1  is connected at one end to control pin  224  of left upper driver  204  and at the other end to an On Voltage power source. Capacitor C 1  is connected at one end to control pin  224  and at the other end to a ground potential connection point. 
     In similar fashion, resistor-capacitor series pairs R 2 ,C 2  are coupled between an On Voltage supply and ground and at their junction to control pin  226 ; R 3 ,C 3  are coupled between an On Voltage supply and ground and at their junction to control pin  234 ; and R 4 ,C 4  are coupled between an On Voltage supply and ground and at their junction to control pin  236 . 
     Each of the switches S 1   a , S 1   b , S 2   a,  and S 2   b  includes an off terminal coupled to an Off Voltage source. In an exemplary configuration, the Off Voltage source may correspond to a ground potential, although any other voltage level less than threshold levels  306 ,  314  ( FIG. 3 ) may be used. One purpose of the Off Voltage level is to reset the timing function provided by the series resistor-capacitor circuit, thus the choice of a relatively zero voltage, that is ground potential, would be convenient, but not specifically required. 
     Referring to  FIG. 2  and the waveforms diagram  300  of  FIG. 3 , when logic high is seen at the S 1  Control from the signal on line  240  as illustrated in waveform  302 , switches S 1   a  and S 1   b  connect one end of capacitors C 1  and C 4  through resistors R 1  and R 4  respectively to the On Voltage supply. This provides a charging voltage to capacitors C 1  and C 4  resulting in a ramp up  304  of the voltage to the left upper driver  204  and lower right drive  216 . When this ramp up  304  voltage reaches threshold voltage  306  of the drivers, the drivers turn on. 
     Simultaneously, when this logic high is seen at the S 2  control, switches S 2   a  and S 2   b  turn off. This causes the threshold voltages  226  and  234 , respectively, of the left lower driver  206  and right upper drive  214  to switch to the off voltage substantially instantaneously, which causes the left lower and right upper drives to turn off immediately. The Off Voltage level is represented as Off Voltage  308  in  FIG. 3 . After a delay produced by the time delay function of resistor-capacitor series circuits R 1 C 1  and R 4 C 4 , the left upper driver  204  and right lower drive  216  are turned on. The same off-delay-on operation occurs when the left upper driver  204  and right lower drive  216  turn off and the right upper driver  214  and left lower drive  206  turn on as a result of the time delay function of resistor-capacitor series circuits R 3 C 3  and R 2 C 2 . 
     As a result of this operational sequence, a voltage waveform  310  is impressed across LCD filter  202 . From an overall view of waveforms  300 , it will be seen that when Signal In as seen at waveform  302  is applied to Signal In line  240 , as the signal goes to a high logic level a ramp voltage  304  begins to be produced based on the RC time constants of timing circuits R 1 C 1  and R 4 C 4 . When the ramp voltage reaches a threshold level  306 , drivers  204  and  216  turn on. When the Signal In voltage on line  240  goes to a low logic level, drivers  204  and  216  substantially immediately turn off and another timing operation is conducted based on the time constants of timing circuits R 2 C 2  and R 3 C 3 . This time period is represented in the shaded area  312 . When the ramp voltage  314  for these timing circuits reach a threshold level  316 , drivers  206  and  214  turn on until the Signal In line  240  again goes to a logic high level where drivers  206  and  214  substantially immediately turn off and the cycle repeats itself so long as Signal In on line  240  continues to repeat. 
     Those of ordinary skill in the art will appreciate that while the present disclosure has illustrated the use of RC timing circuits to provide switching delay for the driver circuits, other types of delay producing circuitry may be employed including, without limitation, digital circuitry. 
     In this manner, the waveform applied to LCD filter  202  alternates such that there is no period during which either the left drivers  204 ,  206  or the right drivers  214 ,  216  are simultaneously on so as to avoid shunting of the Shade Voltage supply to ground. Such operation avoids the previously encountered electrical component stress and high battery drain. 
     While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is by way of example rather than by way of limitation, and the subject disclosure does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.