Abstract:
The present application relates to apparatus and methods for burn-in and other diagnostics performed on integrated circuits. In one embodiment, the invention includes a plurality of sockets, each to hold an integrated circuit (IC), and coupling power to the respective IC from a remote power supply, a plurality of voltage detectors, each coupled to a socket to sense the voltage of the power coupled to the respective IC, and a plurality of remote voltage regulators, each coupled between the power supply and a respective socket, to receive the sensed voltage from the respective voltage detector and to adjust the voltage of the respective coupled power in accordance therewith.

Description:
BACKGROUND  
       [0001]     1. Field  
         [0002]     The present application describes test and burn-in equipment for integrated circuit diagnostics and manufacture and in particular, a system for handling multiple integrated circuits with tight control of operational parameters and instruction execution.  
         [0003]     2. Background  
         [0004]     Many IC (Integrated circuit) chips, including CPU&#39;s (Central Processing Units) and other processors are subjected to diagnostic tests and burn-in before they are put into regular use. The diagnostic and burn-in processes vary with different chips and different manufacturers. Burn-in may involve driving the chip at low clock speeds and elevated temperatures and voltages through a series of test sequences. For complex chips, burn-in can take many hours before the chips are sufficiently tested and conditioned for commercial use. Special equipment is required to maintain the appropriate clock rates, temperatures, voltages and sequences. This equipment may be different for different IC&#39;s.  
         [0005]     Burn-in equipment technology changes rapidly to keep up with increases in power, speed and density for the IC&#39;s upon which they operate. Some new CPU&#39;s include multiple cores and caches and need separate voltage supplies for different sections of the chip. Accordingly, burn-in steadily increases in cost and complexity.  
         [0006]     In addition, burn-in equipment is replaced or upgraded to meet the demands of new chip designs. In order to reuse existing equipment, some existing burn-in tools can be upgraded by depopulation, i.e. using the same equipment to test a smaller number of CPU&#39;s. This can allow multiple clock rate and power supply demands to be serviced without replacing the equipment. However, factory throughput is greatly reduced, or the amount of floor space required to burn-in the same number of CPU&#39;s is increased.  
         [0007]     Accurate and frequent measurement of the operating physical parameters of the IC&#39;s allows for more precise control of these parameters. For example, during burn-in testing, a very small increase in voltage or temperature can significantly reduce the time required to complete a burn-in cycle and therefore increase factory throughput. On the other hand, too high a voltage or temperature can destroy the IC. In addition, with semiconductor chips, as the temperature increases, resistance drops, increasing the current for a fixed voltage. The increased current increases the temperature inducing a nonlinear feedback effect. Operation near the temperature and voltage limits, therefore requires an increased precision in measurements of the chips&#39; physical parameters and a faster response time. As the geometry of chip architecture grows smaller and smaller, the chips become more susceptible to gate oxide breakdown, requiring further increases in precision and speed.  
         [0008]     In order to regulate the voltage on a chip during burn-in, typically, the voltage at the output of the voltage regulator module that powers the chips is sensed. This voltage may be different than at the chip and it may change more slowly than the voltage at the chip. In addition, due to variations in signal path, chip temperature, and chip constitution, the voltages differences may differ at different chips. As a result, chip voltage cannot be accurately determined at a voltage regulator module output.  
         [0009]     As burn-in currents are increased, so are voltage drops along the power path and the corresponding amount of heat that must be dissipated. The increased voltage drops increase the difference between the voltage regulator module voltage and that of each chip. In order to prevent the chips from being overstressed during burn-in, the set point voltage is lowered at the voltage regulator module. However, this increases the burn-in time. As a result more burn-in chambers are required to achieve the same production volume.  
         [0010]     During diagnostic and burn-in processes a single test signal generator can be used to send instruction sequences to a group of IC&#39;s at the same time, or in quick succession. Many IC&#39;s require these signals in a gunning transceiver logic (GTL) level and the signals are often transmitted as low voltage transistor-to-transistor logic (LVTTL). While LVTTL signaling may work well over the short, low power, protected distances typical in operational components, in a system designed to test a group of IC&#39;s these signals must run longer distances across spaces with higher amounts of interference. As speed, power and heat increase, LVTTL signals are more frequently distorted or changed, increasing communication error rates. Such errors require that sequences be repeated, increasing the amount of time required for execution.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     Embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to be limiting, but are for explanation and understanding only.  
         [0012]      FIG. 1  is a block diagram of a burn-in and diagnostic system according to an embodiment of the invention;  
         [0013]      FIG. 2  is a block diagram of the power distribution board and burn-in board components of the system of  FIG. 1 ;  
         [0014]      FIG. 3  is a diagram of an unpopulated power distribution board and chassis according to an embodiment of the invention;  
         [0015]      FIG. 4  is a diagram of an unpopulated burn-in board and chassis according to an embodiment of the invention;  
         [0016]      FIG. 5  is a process flow diagram of a voltage control process according to an embodiment of the invention; and  
         [0017]      FIG. 6  is a process flow diagram of a burn-in system process according to an embodiment of the invention.  
     
    
     DETAILED DESCRIPTION  
       [0018]     Several abbreviations are used in the text that follows. They are spelled out as they occur. For the reader&#39;s convenient reference, a few of the abbreviations are listed below. This list of abbreviations is not complete. All abbreviations are intended to simplify reading, not to suggest that any particular structure or process is required.  
         [0019]     ADC Analog-to-Digital Converter  
         [0020]     BIB Burn-In Board  
         [0021]     BID Burn-in Driver  
         [0022]     DUT Device Under Test  
         [0023]     EEPROM Electrically Erasable Programmable Read Only Memory  
         [0024]     GTL Gunning Transceiver Logic  
         [0025]     LVDS Low Voltage Differential Signaling  
         [0026]     LVTTL Low Voltage Transistor to Transistor Logic  
         [0027]     PCD PDB Card Daughter  
         [0028]     PDB Power Distribution Board  
         [0029]     VCD VRM Card Daughter  
         [0030]     VRM Voltage Regulator Module  
         [0031]      FIG. 1  shows a high level block diagram of an example of a system that may be used to burn-in and perform diagnostic testing on CPU&#39;s or other IC&#39;s. The present example will be described in the context of CPU burn-in, however, the apparatus and processes described may also be used to perform any of a variety of other tests and analyses of any of a variety of different IC&#39;s. The DUT&#39;s (Device Under Test), which may be any type of IC chip, are placed in sockets  49  of a Burn-in Board  15 . The Burn-In Board carries the DUT&#39;s in their sockets and measures their parameters, such as temperature and voltage. A Power Distribution Board  13  receives these measurements and controls the temperature and voltages at blocks  33 ,  35 , and  37 . It also generates instruction sequences in a burn-in driver  31  for the IC&#39;s to execute during the process. The instruction sequences may be used to test or condition the intended portions of the DUT. Connectors (see  FIGS. 3 and 4 ) carry the data  43 ,  44 ,  47  signals and power  41  between the Burn-in Board and the Power Distribution Board. The connectors also allow power distribution and burn-in boards to be interchangeably connected and disconnected so that the two components may be serviced independently of each other or connected to other components.  
         [0032]     Referring to  FIG. 1  in more detail, the illustrated burn-in system features a test manager  11  coupled to a PDB (Power Distribution Board)  13  that is, in turn, coupled to a BIB (Burn-in Board)  15 . As shown in the example of  FIG. 1 , the test manager may drive many PDB&#39;s and BIB&#39;s. In the illustrated example, the test manager is coupled to 32 PDB&#39;s  13 - 1 ,  13 - 2 ,  13 - 3 , . . .  13 - 32 , which are each coupled, respectively to one of 32 BIB&#39;s  15 - 1 ,  15 - 2 ,  15 - 3 , . . .  15 - 32 . More or fewer PDB&#39;s may be coupled to the test manager depending on the particular application. In addition, a PDB may be coupled to more or less than one BIB, depending also on the particular application. The configuration of  FIG. 1  is provided as an example of one of many different possible configurations.  
         [0033]     The test manager provides overall high level supervision and control of the burn-in process and provides any necessary software revisions or replacements for the PDB&#39;s and BIB&#39;s. The test manager may be based on many different hardware architectures. It may be constructed, for example, using conventional personal computer architecture with a CPU, mass storage and bus interfaces. In the example of  FIG. 1 , the test manager communicates with the PDB using conventional Ethernet  17  and RS (Recommended Standard adopted by the Electrical Industries Association)-485 19 personal computer network protocol connectors. Accordingly, the test manager includes a motherboard or adapter card based Ethernet driver  21  and a motherboard or adapter card based RS-485 driver  23 .  
         [0034]     The Ethernet driver may be used not only to communicate with the PDB but also with other remote network devices  25  over a system-wide Ethernet network  27 . The system-wide Ethernet network may be used to allow the test manager to be remotely accessed or updated. Accordingly, a large quantity of test managers may be managed or supervised from a central location. Ethernet and RS-485 are shown in  FIG. 1  as examples of reliable, and well-developed communications protocols, however, any desired protocol may be used. The communications channels may be wired, or wireless, electrical, electromagnetic, or optical.  
         [0035]     In the illustrated embodiment, a single bulk power supply  29  is used for each PDB. Each bulk power supply is coupled to a PDB using high power cables  39  that connect to a power bus (not shown) inside the PDB. In the illustrated example using  32  PDB&#39;s, there are accordingly 32 bulk power supplies  29 - 1 ,  29 - 2 ,  29 - 3 , . . .  29 - 32 . A high current (400 A), low voltage (12 VDC) bulk power supply may be used that operates from a conventional 480 VAC facility power mains input. The particular specifications for the bulk power supply may be selected to suit a particular application.  
         [0036]     For a slot-based design the bulk power supply, PDB and BIB may be the main electrical slot-level subassemblies. Each subassembly may be constructed in a separate independent chassis that may be carried in a slot of a standard production rack. In one embodiment, a PDB and BIB are connected together and carried in a single slot of the industrial electrical rack, while the bulk power supply is carried in another slot. Such a burn-in chamber rack may also have slots to accommodate a factory control system and a thermal cooling and heating system (not shown). In one embodiment, each of the slot-level subassemblies are independent from the others, which allows burn-in to continue with some subassemblies while other subassemblies are being serviced, repaired, or restocked. In the illustrated example, three racks of 32 slots each may be used to carry 32 of each of the subassemblies, while the test manager may be located in a nearby or remote location.  
         [0037]     The PDB and BIB are constructed as two different sub-assemblies in the example of  FIG. 1 . The BIB holds the DUT&#39;s in sockets and has all the supporting electronics to interface with the PDB. The PDB uses three simple networks and two power buses to provide efficient data transmission and significantly reduce signal connections between the two sub-assemblies. This reduction in signal connections, may be used to greatly reduce the size and the complexity of the interface between the PDB and the BIB. In the illustrated example, an SPI (Serial Peripheral Interface, a master/slave interface defined by Motorola) bus  43 , an I 2 C (Inter-Integrated Circuit, a type of bus designed by Phillips Semiconductors to connect integrated circuits) bus  45 , and a IEEE (Institute of Electrical and Electronics Engineers) 1149.1/P 1149.4 JTAG (Joint Test Action Group) TAP (Test Access Port) and Boundary-Scan Architecture Test Bus were chosen. An SMBus (System Management Bus) variant of the SPI bus may be used to accommodate standard chip designs. While many other simple or complex network interfaces may be used instead, these interfaces are readily available on commercial microcontrollers and peripheral components. The particular interconnections and operation of these buses will be described further with reference to  FIG. 2 .  
         [0038]     The PDB&#39;s  13  each include a BID (Burn-in Driver)  31 , a group of VRM&#39;s (Voltage Regulator Module)  37  to supply power to the DUT&#39;s, a PCD (PDB Card Daughter)  33  to control temperatures and voltages during burn-in, and a group of VCD&#39;s (VRM Card Daughter)  35  to control the VRM&#39;s. These components are described in more detail with reference to  FIG. 2 . In the illustrated example, there are 18 DUT&#39;s on the BIB to be supported by each PDB. The PDB has 18 VCD&#39;s, one per DUT and 36 VRM&#39;s, or two per DUT. Each VCD controls two VRM&#39;s using two separate control circuits. The number DUT&#39;s is provided as an example, 24 or more DUT&#39;s may be accommodated on a single BIB.  
         [0039]     In the present example, two VRM&#39;s are used to power each DUT. This allows the total amount of power per DUT to be doubled. This may also be used to accommodate two different voltages on each DUT. Alternatively, the BIB may be designed to connect four VRM&#39;s to each DUT in order to increase power or increase the number of different voltages. For lower power DUT&#39;s or higher power VRM&#39;s the 36 VRM&#39;s may be used to drive 36 or more DUT&#39;s. These variations may be effected using a single PDB configuration by changing the power lines in the BIB and the software voltage set points for the VRM&#39;s. The particular choice of and number of different components may depend on the particular application.  
         [0040]     Accordingly, in the example of  FIG. 1 , two connected burn-in slots, one slot carrying a bulk power supply, and the other slot carrying the PDB and BIB, may test or burn-in 18 DUT&#39;s at 200 Watts or more each (3,600 Watts/Slot) with two Vcc inputs per DUT. The PDB may serve as a main power and signal subassembly. The PDB provides the BIB with burn-in power from the VRM&#39;s over its power connector  41 . In the present example, this may be at 200 Watts or more for each CPU for a total of 3,600 Watts per rack slot.  
         [0041]     The BIB  15 , as mentioned above, carries the sockets  49  for the DUT&#39;s. In the illustrated example, there are 18 sockets. For each socket there is a voltage ADC (Analog-to-Digital Converter)  51  and a temperature ADC  53  which will be described more fully below. Each BIB also carries a readable memory register, such as an EEPROM (Electrically Erasable Programmable Read Only Memory) for identification purposes. The information in the EEPROM may depend on the particular application, however, it may include serial numbers, a service hour counter, a cycle counter, and a build type.  
         [0042]      FIG. 2  shows a single PDB and BIB such as those of  FIG. 1  in more detail. The Ethernet connection  17  to the test manager  11  is coupled directly to the BID (Burn-in Driver)  31 . This connection may be used to load instruction sequences for the DUT&#39;s into the BID that may be operated by the DUT&#39;s during burn-in or any other test or diagnostic process. The BID may also send results from the instruction sequences from each DUT over the Ethernet connection back to the test manager. This may allow the test manager to compile a report on the status and condition of each DUT. For example, the BID may report back to the test manager which DUT&#39;s test out as operational and which DUT&#39;s have failed certain tests. Depending on the nature of the DUT and the instruction sequences, the BID may be able to report on exactly which portions of each DUT have passed and which ones have failed.  
         [0043]     In the illustrated embodiment, the DUT&#39;s and BID are IEEE 1149.1/P1149.4 JTAG TAP and Boundary-Scan Architecture compatible. This JTAG protocol is widely used and is designed to test and interface with IC&#39;s. However, any other type of signaling may be used and the choice may depend on the nature of a particular DUT. The BID sends the instructions and receives results to each DUT through a JTAG/Test connection  47 . This connection is carried from the BID to a buffer  61  on the BIB and then to each of the sockets  49  on the BIB. In the illustrated embodiment, a subset of JTAG diagnostic signaling is used to send and receive test signals to the DUT&#39;s.  
         [0044]     The BID is microcontroller based and interfaces to the PDB via a conventional socket edge connector. This connector may be similar to a PCI (Peripheral Component Interconnect) socket and interface or any other well-established edge connector interface. This allows the BID to easily be replaced or upgraded. It also allows the rest of the PDB to be put back into service if the BID fails by quickly replacing the defective BID. Diagnostics for the failed BID may be performed independently of the PDB. A single BID may be used to provide the necessary test signals for all 18 DUT&#39;s. The BID may operate independently or under the control of the test manager or the PCD.  
         [0045]     The voltage and temperature conditions of each DUT are monitored by the PCD  33  and its microcontrollers. The voltage supplied to each DUT is controlled through microcontrollers on the PCD. These microcontrollers include a main controller and voltage transponder  65 , a temperature transponder  67  and a telemetry transponder  69 . In one embodiment, these microcontrollers are low power eight-bit reduced instruction set microcontrollers with system programmable flash memory and integrated I 2 C, SPI, and RS-485 interfaces. External chips for bus communications, such as an external RS-485 interface chip may also be used. Suitable microcontrollers for use in the PCD include the ATmega line of microcontrollers from Atmel Corporation. The main controller may communicate with the test manager using the RS-485 bus  19  or any other type of communication path. Commands and data may be passed down to the other microcontrollers of the PCD and to the EEPROM  55  on the BIB over the SPI bus  44 , or any other type of bus. In one embodiment, the main controller of the PCD is the master of the SPI bus. The main controller may also monitor DUT voltages on the SPI bus and then pass this information to other microcontrollers over the I 2 C bus. Status signals may also be made available to other microcontrollers and to the test manager.  
         [0046]     The temperature transponder microcontroller  67  monitors the DUT temperatures from the BIB via the I 2 C bus. The precise nature of this temperature depends on the design of the BIB. In one embodiment, this temperature is a junction temperature (Tj) made available across two external pins of the DUT. The temperature transponder microcontroller may also be used to monitor several BIB and PDB supply voltages, BIB over-current, and local PDB temperatures. Using this information, it may provide a temperature telemetry data stream to a thermal controller  71  via a second SPI bus  73 . The thermal controller drives fans, heaters, air conditioners, liquid coolers, or other thermal devices (not shown) to regulate the temperatures of the DUT&#39;s and other components of the system.  
         [0047]     The telemetry transponder microcontroller  69  may be used to monitor voltages, currents, and temperatures from any connected microcontrollers via the I 2 C and SPI bus and to produce a telemetry stream that may be sent to the BID, to the test manager upon command via the RS-485 bus or any other bus and to any other networked devices. It may also serve as a bus master for any of the network buses that are used. By providing these communications and bus mastering functions, it relieves the other microcontrollers of any related interrupts and processing demands. The telemetry data streams to and from the telemetry transponder may include the status of any desired functions and systems.  
         [0048]     The PDB also contains VCD&#39;s or VRM controllers  35  and the VRM&#39;s  37 . The VCD&#39;s may be implemented as swappable daughter cards that are installed into slots in the main power distribution board, as described in more detail with respect to  FIG. 3 . Similarly the VRM&#39;s may be implemented as swappable cards so that the VCD&#39;s and VRM&#39;s may be quickly replaced and diagnosed off-line. The VCD&#39;s are coupled to the voltage controller  65  over an SPI bus  64  In the illustrated example, one VRM controller is used for every two VRM cards or 18 total. There are two VRM&#39;s per card. The VRM controllers are coupled to the VRM&#39;s over a set of 36 discrete voltage control signal lines  63 . Alternatively, one microcontroller may be used per VRM or thirty-six total. Increasing the number of VRM microcontrollers may support flexible ganging and multiple voltage supplies per CPU.  
         [0049]     The VCD&#39;s and VRM&#39;s may be low-cost, off-the-shelf VCD&#39;s and VRM&#39;s that may be carried in a conventional edge connector socket, and configured to power the 18 DUT&#39;s with multiple voltages and power requirements. More DUT&#39;s may be powered if only one power supply is required for each DUT. Off-the-shelf VCD&#39;s and specially designed VCD&#39;s may be obtained from Celestica, Inc. of Toronto Canada. One current off-the shelf VRM is a VRM 9.1 from Celestica. It supplies 1.1-1.85 VDC up to 80 Amps. The VRM 9.1 has 5 Voltage Identification (VID) codes or signals to provide programmable 25 mV resolution steps. The VRM  10  from Celestica supplies 0.8-1.6 VDC up to 100 Amps and uses 6 VID signals to provide programmable 12.5 mV resolution steps. Both VRM&#39;s are gang-able through hardware and firmware designs to supply the DUT&#39;s with higher currents and multiple voltage sources.  
         [0050]     The VRM controllers get their unit numbers and master/slave assignments from the PDB main controller via the SPI bus  64 . Depending upon their assignments, each VRM controller may be set up to originate, pass along, or terminate its VRM signals such that the VRM&#39;s will act in groups for current sharing. VRM controllers may apply algorithms for “Soft Start”, current foldback, and temperature fold back and may close the loop for the desired programmed voltage commanded by main controller.  
         [0051]      FIG. 3  shows a diagram of an example of a PDB (Power Distribution Board)  13  with all of the slot-mounted cards removed. As described above, the PDB may be a multi-layer printed circuit board designed to carry multiple power lines (not shown) on some planes and multiple data buses (not shown) on other planes between the various microcontrollers and power supplies. The board is mounted into a protective chassis  111 , which may be fabricated of aluminum or any other durable, heat conductive material. The chassis is designed to house and protect the mounted components and also to fit into a slot in a conventional industrial electrical processing rack. However, the particular form factor, shape and configuration for the chassis and the PDB may be adapted to suit a variety of different applications.  
         [0052]     The chassis includes a left side bulk power connector  113 - 1  to couple power from the bulk power supply into the PDB. It has a right telemetry and control connector  113 - 2  to couple the PDB to the test manager, thermal control and other equipment. It also includes a set of six high flow cooling fans  123 - 1 ,  123 - 2 , . . .  123 - 6  along one side and between the two bulk power connectors. The fans may be run constantly or controlled by the thermal controller  71  or any other thermal control system. The fans are positioned so that when a BIB is coupled to a PDB, the six high flow fans force air across both the PDB and the BIB.  
         [0053]     The PDB also includes a connector  115  to couple power and data from the PDB to the BIB. The connector of the illustrated embodiment has a left side power coupling section  117 , a right side power coupling section  119 , and a central data coupling section  121 . This connector mates with a matching connector on the BIB to carry all data and power, however, any of a variety of other coupling devices may also be used. The PDB also has Ethernet, RS-485 or other network and power connections to other external components (not shown).  
         [0054]     In the illustrated embodiment, the top surface of the PDB is populated with sockets or slots to carry the components described above. A socket  133  for the PCD (Power Distribution Board Card Daughter) is positioned along the center column of the card near the bulk power supply connectors. A socket  131  for the BID (Burn-In Driver)  31  is positioned along the center column near the BIB connector. The two center column sockets define a left hand and right hand side of the PDB for the 18 VRM (Voltage Regulator Module) controllers and the 36 VRM&#39;s. The sockets for the VRM controllers or VCD&#39;s (VRM card daughter) and the VRM&#39;s are placed in eighteen groups of three with one VCD socket and two VRM sockets in each group. As shown in  FIG. 3 , a matrix of three columns and three rows of three-card groups are placed on each side of the PDB. In the top left of the PDB as shown in  FIG. 4 , is a VCD socket  135 - 1 , with a VRM socket  137 - 1 ,  137 - 2  on either side. Two more groups are below this first group and two further groups are to the right side of this first group. The pattern is repeated on the right hand side of the cards.  
         [0055]     In the illustrated embodiment of the invention, the sockets of the PDB are arranged parallel to each other and aligned in rows. The parallel design allows a large number of cards to be carried in a very small space. By aligning the cards in rows, airflow from the cooling fans is eased. Using sockets to carry independent cards or daughtercards allows all of the microcontrollers and VRM&#39;s to be quickly replaced for servicing or repair. However, the particular arrangement and number of sockets may be modified to suit any particular application. In addition, it may be preferred to mount all components directly to a single printed circuit board or to several different printed circuit boards to suit the needs of a particular application.  
         [0056]      FIG. 4  is a diagram of a BIB (Burn-In Board)  15  with all of the DUT&#39;s removed. In one embodiment of the invention, the BIB is a multi-layer printed circuit board with separate planes for DUT power, board-level component power and data. The board is mounted in a protective aluminum chassis  151  adapted to be carried in a slot or an equipment rack and also to be manipulated by an automated material handler.  
         [0057]     As shown in  FIG. 4 , the BIB (Burn-In Board) carries eighteen sockets  49 - 1 ,  49 - 2 , . . .  49 - 18 , one for each of the IC&#39;s that are to be tested. In one embodiment, the DUT&#39;s are microprocessors and the sockets are similar to or the same as conventional motherboard sockets such as type 478, 603, or 604 sockets. In the illustrated embodiment, the sockets are arranged in two matrices of three columns and three rows, one matrix on each side, left and right, on the BIB. The sockets are spaced out over most of the surface of the BIB to maximize packing density and cooling. However, the particular arrangement of the sockets may be adapted to suit different applications. There may be more or fewer sockets depending upon the relative size and thermal characteristics of the DUT&#39;s and the sockets.  
         [0058]     The BIB also includes a connector  153  to couple power and data from the PDB to the BIB. The connector of the illustrated embodiment has a left side power coupling section  155 , a right side power coupling section  157 , and a central data coupling section  159 . This connector mates with the matching connector  115  on the PDB to carry all data and power, however, any of a variety of other coupling devices may also be used. The BIB may also have other network or power connections to other external components (not shown).  
         [0059]     The DUT&#39;s to be burned in are placed in the BIB&#39;s sockets, which provide all electrical connections. The embodiment of the BIB shown in  FIG. 4  provides clock, data signaling, and power to 18 DUT&#39;s. In one embodiment, the power for each DUT is supplied by two VRM&#39;s (Voltage Regulator Modules)  37  at 200 Watts or more each. The physical layout may be adapted to enable direct contact with a specialized thermal cooling system.  
         [0060]     In one embodiment, a high-density sixteen-layer BIB may be made from a 24″×14″ standard PCB (Printed Circuit Board) to support the power and signal requirements of the 18 CPUs. Ten of the layers may be dedicated to high-power conduction in order to maximize current flow. Using between 2 to 4-ounce copper in each power layer allows upwards of 100 Amps per voltage source to be carried with low voltage (or IR) drop. Low power path voltage drops help to minimize losses and heat. The ten power layers allow 200 Watts or more to be delivered to each of the 18 CPU&#39;s.  
         [0061]     The BIB also includes an EEPROM  55  that stores information about the BIB and the DUT sockets together with any other desired information. The BIB EEPROM may reside on the SPI bus so that the data in the BIB EEPROM is independently available to all of the connected controllers on the PDB. For example, the EEPROM may be used to store a BIB identification number, a total cycle count, a last PM (Preventative Maintenance) date and the number of cycles since the last PM. A BIB identification number may be used to allow the PDB to configure itself to match the product type being tested. The BIB EEPROM may also be used for power up and power down sequences. For example, a BIB present signal may be used to tell the PDB main controller and BID that the BIB is ready to start a burn-in process  
         [0062]     The BIB may be designed as a flexible sub-assembly capable of interfacing with a variety of different PDB&#39;s. It may also be designed to accommodate a variety of different DUT&#39;s. To accommodate other DUT&#39;s, signal and power pin modifications may be made, multiple voltage sources or high current needs may be accommodated. The BIB may also be adapted to work with an automated material handling system using, for example, metal rails to transport the BIB to and from a burn-in chamber rack and then to a DUT loading and unloading section. The DUT loading and unloading section allows the material handling section to populate and depopulate the sockets with the CPU&#39;s or other IC&#39;s that are to be burned in.  
         [0063]     As further shown in  FIG. 4 , from the central data section  159  of the connector, the JTAG standard TAP (Test Access Port) test signals  47  from the BID (Burn-In Driver) are coupled to the buffer  61 , which in turn, transmits the JTAG test signals to the socket for each DUT. The signals may travel along two branches  161 ,  162  from the buffer to reach each of the sockets. In one embodiment, the BID generates a single set of signals which is sensed by a decoder  163 - 1 ,  163 - 2 ,  163 - 3 ,  163 - 18  at each socket. One example of a suitable encoder is a SN75LVDT390D decoder available from Texas Instruments, however any suitable decoder may be used. The DUT transistors may be toggled via the TDI (Test Data In) JTAG signal provided by the BID. TDI may be connected in parallel to the DUT&#39;s and 18 TDO (Test Data Out) signals may be returned to the BID on 18 discrete signal paths  165 - 1 ,  165 - 2 ,  165 - 3 , . . .  165 - 18  (only four are shown) to determine if each DUT is operating properly.  
         [0064]     Due to the different locations for each DUT socket, the JTAG TAP signals travel different lengths to and from the BID. The BID may compensate for the total delay in the TDO signal differences. The variations in delay may also be reduced by the design of the signal paths. As shown in  FIG. 4 , the DUT sockets are divided into a left-hand and a right-hand group and the TDI signals are routed from each DUT to its nearest neighbor. This tends to shorten the overall path and reduce the maximum delay from the buffer to the furthest DUT. For the example of  FIG. 4 , the maximum signal delay variance is less than 10 nanoseconds. For reference, a typical TCK (test clock) rate is approximately 1 to 10 MHz or one pulse every 100 to 1000 nanoseconds. Accordingly such a delay will not interfere with signal communications.  
         [0065]     Signal fidelity may be further enhanced from the BID to the DUT&#39;s using LVDS (Low Voltage Differential Signaling) transmission circuitry. LVDS signaling may be used to provide low noise and high edge rates suitable for backplane driving. As a result, the pin count of the connector between the BID and the PDB may be lowered. Rather than provide separate channel routing for each DUT, with LVDS, the input pins may successfully be shared among all of the DUT&#39;s. The signal distribution and routing on the BIB may be designed to go through several signal translations starting from the LVTTL (Low Voltage Transistor to Transistor Logic) signal from the BID (Burn-In Driver) to a LVDS signal at the buffer and ending with a GTL (Gunning transceiver Logic) signal at the decoder at each socket.  
         [0066]     The signals from the BID on the PDB are received through the data portion of the PDB connector  159  as LVTTL signals at the BIB buffer  61 . In one embodiment, the BID and the BIB buffer are placed very close to each other on opposite sides of the data portion of the PDB-BIB connector. This reduces degradation of the LVTTL signals along this path. The buffer acts in part as an LVDS encoder and level shifts these signals to LVDS. They are then routed in the serpentine format shown in  FIG. 4  to each DUT socket  49 . At every DUT location, the signal bus is translated by the corresponding encoder to GTL signals and subsequently goes through a GTL to open drain buffer (not shown) where pull-up termination is used to provide signals with the right level to the DUT. In order to service all of the desired test pins on each socket, more than one decoder may be used. In one embodiment, the sockets are a 478 type and three decoders are used at each socket in order to send the TDI signals to each pin.  
         [0067]     As shown in  FIGS. 2 and 4 , in the illustrated embodiment, voltage ADC&#39;s  51 - 1 ,  51 - 2 ,  51 - 3 , . . . ,  51 - 18  are networked to a serial bus through an SPI decoder  52  which transmits the voltage sense data back to the PDB main controller and voltage transponder  65  over an SPI bus on an on-going basis as telemetry data. In the illustrated embodiment, up to 36 voltage readings, two readings for each DUT may be monitored on a single SPI bus line. In one embodiment, this voltage reading is taken by connecting to the Vcc and Vss pins of the IC and converting the difference between these analog voltages to a digital voltage measurement value.  
         [0068]     The network bus-based voltage sense architecture reduces the number of channels required for the PDB controller to monitor all of the 36 voltage sense points coming from the BIB. This simplifies the interconnection between the PDB and BIB, as well as reducing the number of signal paths on the PDB and BIB. Converting the analog voltage signal to a digital signal near the DUT also eliminates the voltage sense inaccuracies caused by changes in the analog levels in voltage signal lines. The accurate measurements allow each chip to be independently driven at its optimum burn-in voltage.  
         [0069]     The SPI network bus, based in the PCD&#39;s main controller  65  on the PDB  13 , connects to the voltage ADC&#39;s  51  on the BIB  15 . In one embodiment, The PCD main controller sequentially polls each ADC on the BIB through the SPI address lines (SPI_A 0  to SPI_A 3 ) and chip select decoding circuitry. These four SPI address lines provide the address decoding logic. In one embodiment, the ADC&#39;s are capable of reading eighteen CPUs with dual Vcc inputs, such as VccSense and VssSense. Each data stream from each voltage sense point is transmitted back to the PDB controller over the SPI bus with a unique address.  
         [0070]     The VccSense and VssSense inputs may be read as analog connections to a CPU&#39;s internal voltage reference points. These reference points are provided on external pins of each CPU. Alternatively, the voltage may be sensed at the socket or at some other location on the BIB. The analog voltage levels are sampled, converted to digital data, and made available to the microcontroller via the SPI network bus.  
         [0071]     The illustrated voltage sense architecture design is flexible enough to support DUT&#39;s with any number of voltage sense points and voltage input requirements. Using an SPI bus shared between 18 ADC&#39;s, the design provides a high sampling rate fast enough for the voltage regulator modules (VRM) on the PDB to regulate the voltage to the DUT even during high current draw. With eighteen ADC&#39;s in the illustrated embodiment, each complete polling cycle takes about 250 ms to sample all eighteen ADC&#39;s (addresses CS 0  to CS 17 ). Thus the voltage to each DUT may be adjusted every 250 ms.  
         [0072]     According to one embodiment of the invention, DUT voltage is measured right at the DUT and immediately converted from an analog reading to a digital data stream to preserve its accuracy. The analog conversion may use 10-bit successive approximation for each DUT Vcc supply. With 10-bit accuracy, a sensing voltage from less than 1 V up to 2.5 V with 7 mV resolution may be accommodated.  
         [0073]     Once the PDB main controller and voltage transponder  65  receives the data stream, it may compensate by calculating the difference between the measured voltage and the desired voltage or the DUT voltage set point. The main controller then transmits the compensation data to the corresponding VCD  18 . It may adjust the voltage identification (VID) bits on the corresponding voltage regulator or VCD  35  to either increase or reduce the output set point. The VCD microcontroller then increments or decrements the VRM VID (Voltage Identification) signals to adjust the VRM  37  voltage output. The VID lines  63  are the voltage control signals from the VCD&#39;s to the VRM&#39;s to set the VRM output voltages. This technique ensures that the voltage at the DUT pin is accurate to within the resolution of its set point value and is independent of current loading and voltage drop. The accuracy that can be achieved may depend upon the VCD and VRM combination. An accuracy to within 12.5 mV to 25 mV is available with currently available equipment.  
         [0074]     VRM&#39;s are typically configured to sense their output voltage only at their output connection point. Extending the voltage sense point out to the DUT socket and adding a VRM controller with an active feedback system greatly improves the accuracy of the sensed voltage.  
         [0075]     As also shown in  FIGS. 2 and 4 , in the illustrated embodiment, temperature ADC&#39;s  53 - 1 ,  53 - 2 ,  53 - 3 , . . . ,  53 - 18  are networked to a serial bus through an I 2 C interface  54  which transmits the temperature sense data back to the temperature transponder  67  over an I 2 C bus on an on-going basis as telemetry data. In the illustrated embodiment, up to 18 temperature readings, one reading for each DUT can be monitored on a single I 2 C bus line.  
         [0076]     A conventional temperature sensor and converter, such as a G781 from Global Mixed Mode Technology, Inc. of Taiwan offers a stabilized source and detector to be coupled to external temperature junction diode connector pins of an IC. It also provides a local temperature measurement and an integrated SMBus interface. Accordingly, such a device may be used to provide two temperature measurements, a DUT temperature and a local BIB temperature on the I 2 C bus for use by the temperature transponder.  
         [0077]     The network bus-based temperature sense architecture reduces the number of channels required for the temperature transponder to monitor all of the 18 DUT temperatures coming from the BIB. This simplifies the interconnection between the PDB and BIB, and reduces the number of signal paths on the PDB and BIB. Converting the analog voltage signal to a digital signal near the DUT also eliminates the temperature sense inaccuracies caused by changes in the analog levels in voltage signal lines. The accurate measurements allow each chip to be independently driven at its optimum diagnostic or burn-in temperature. The interaction between high temperature and voltage in silicon can also be accommodated using precise and timely information about both parameters.  
         [0078]     The I 2 C network bus, based in the PCD&#39;s main controller  65  on the PDB  13  connects to the temperature ADC&#39;s  53  on the BIB  15 . The temperature transponder  67  sequentially polls each ADC on the BIB through the I 2 C bus and each data stream for each DUT temperature sense point is transmitted back to the temperature transponder over the I 2 C bus with a unique address.  
         [0079]     The DUT temperature inputs may be read as analog connections to a CPU&#39;s internal temperature sensing diode. Access to these diodes are provided on external pins of each CPU. Alternatively, the temperature may be sensed at the package, socket or at some other location on the BIB. The analog voltage levels are sampled, converted to digital data and are available to the microcontroller via the I 2 C network bus. The illustrated temperature sense architecture design is flexible enough to support DUT&#39;s with any number of temperature sense points and may transmit each measured value or a calculated combination value back to the temperature transponder.  
         [0080]     Once the PDB temperature transponder  67  receives the data stream, it may compensate by sending control data to the thermal controller  71 . It may also send temperature data to the PCD main controller  65 , so that the main controller may make adjustments to the voltage supplied to specific DUT&#39;s. At high power and temperature, the operating voltage becomes very closely related to operating temperature.  
         [0081]     Referring to  FIG. 5 , a process flow diagram indicates one technique for maintaining IC voltages during burn-in or diagnostics. There are many different possible techniques for maintaining voltages and more or fewer inputs than suggested by  FIG. 5  may be used. In addition, there may be other control outputs to adjust other than voltage. For example, the thermal controller  71  may be used to respond to temperature or voltage changes in addition to or instead of the DUT input voltage.  
         [0082]     In  FIG. 5 , at block  511 , the temperature is polled for a particular DUT. As mentioned above, in one embodiment, there is a temperature transponder on a network bus with temperature ADC&#39;s. This transponder repeatedly polls the ADC&#39;s and then buffers the responses. These buffered responses may be made accessible to the  FIG. 5  process through readable registers in a memory array. The temperatures may reflect temperature near a DUT, on a DUT package or on the semiconductor substrate of the DUT in one or more locations, or any combination of these and other temperature measurements.  
         [0083]     At block  513 , the resulting temperature is compared to a set point. The set point may correspond to a fail safe point beyond which IC failure becomes likely. If the temperature is not above the set point, then the process goes to block  515  at which the DUT voltage is polled.  
         [0084]     As with the temperature, in one embodiment a voltage controller repeatedly polls voltage ADC&#39;s on a network bus and buffers the responses so that the values are available when needed. The voltages may correspond to an on-chip voltage, an input voltage or some combination of measured voltage signals. At block  517 , this voltage is compared to a first voltage set point and if the voltage is not below the set point then the process goes to block  519 .  
         [0085]     At block  519 , the voltage is compared to a second voltage set point. If the voltage is not above this second set point, then the DUT is operating within acceptable norms and the process goes to check the next DUT. The same process is repeated for all DUT&#39;s then repeated continuously until the test or burn-in has ended. The first and second voltage set points may be the same or they may be different. Providing some difference between the high and low voltage set points may stabilize the control loop. The specific values for temperature and voltage may depend on the type of DUT and the tests being performed.  
         [0086]     When the temperature exceeds the temperature set point value, the process may then move to decrement the VID at block  523  and then check the temperature at block  519 . The VID is the voltage control signal that is passed between the VCD and the VRM to set the VRM output voltage for a particular DUT. In the described embodiment of  FIG. 2 , the temperature transponder  67  will generate a decrement command for a particular DUT and send it on the SPI bus that connects it to the VCD&#39;s. The two VCD&#39;s responsible for the DUT in question will pick up the command and adjust their VID signals. This will be sent to the corresponding VRM&#39;s which in turn will reduce their output voltages to respond to the new VID number. By reducing the voltage at the DUT, the amount of power will also be reduced which will reduce the amount of heat generated by the DUT. Other measures may also be taken in response to a high temperature by thermal and other control systems. These measures may be a part of this process or an unrelated process.  
         [0087]     When the voltage is below the voltage set point, then at block  525 , the VID is similarly incremented and the process then goes to the next DUT. When the voltage is above the set point at block  519 , the process then decrements the VID at block  527 . The process may then proceed to the next DUT. As shown in  FIG. 5 , if the temperature is too high, but the voltage is low, the voltage will nevertheless be decremented because the low voltage decision block  517  is skipped. On the other hand if the both the temperature and the voltage are high, then the VID will be decremented twice in one cycle.  
         [0088]     Many variations are possible for the process shown in  FIG. 5 . Many different possible interactions between temperature and voltage may be accommodated or the two physical parameters may be treated independent of each other. For a DUT with more than one voltage input all of the voltage levels may be checked independently of each other. In such a case, the process may treat each temperature level as if it were another DUT or it may handle each voltage level within the context of a single DUT.  
         [0089]      FIG. 6  shows an example of a burn-in process that can be implemented using the system described above. In  FIG. 6 , the burn-in process begins at block  605  by populating the Burn-In Board with the DUT&#39;s. As mentioned above this may be performed with an automated handler. At block  609 , the Burn-In Board is installed in the equipment rack. This may also be performed by an automated handler. However, in less automated plants, these tasks may also be performed by hand. At block  611 , the Burn-In Board is connected to the Power Distribution Board using, for example, the multiple pin connectors  115 ,  153  shown in  FIGS. 3 and 4 . At block  613 , the PCD Controller engages and enables the thermal control system. The system is now mechanically assembled and ready to be configured.  
         [0090]     Before the burn-in test sequences begin, the system may be configured. While, a flexible reconfigurable BIB and PDB have been described, the system may also be constructed as a dedicated system, in which case all of the necessary instruction sequences and test parameters may already be resident in the appropriate microcontrollers. At block  615 , the Power Distribution Board powers up the Burn-In Board. The ADC&#39;s, encoders, decoders, EEPROM and any other components are now active, but the DUT&#39;s are not.  
         [0091]     At block  617 , the PCD Controller may then poll the EEPROM on the BIB. This transfers the information about the DUT type and other parameters about the BIB. At block  619 , the PCD Controller reports the EEPROM data to the Test Manager. The Test Manager may use this data to log specific details about the DUT&#39;s, to track BIB usage and for many other purposes. The test manager may also increment the EEPROM cycle counter or any other system counters and store the updated values back in the EEPROM. In one embodiment, the Test Manager checks a library of test drivers and parameters for the DUT&#39;s in the BIB and then checks to ensure that the latest versions are resident on the PDB. At block  621 , if the PDB does not have the appropriate drivers and parameters or if there are any required upgrades or corrections, then the Test Manager downloads test drivers and parameters to the Power Distribution Board.  
         [0092]     Having confirmed that it has the appropriate parameters and drivers, at block  623 , the PCD Controller configures the other Power Distribution Board Controllers and components. In one embodiment, the PCD controller serves as a bus master and loads the appropriate parameters and drivers over the SPI bus that connects them. With configuration established, the burn-in cycle, or other test or diagnostic cycle may be initiated.  
         [0093]     At block  627 , the PCD Controller initiates power up for the DUT&#39;s. The power up cycle for the DUT&#39;s may be performed by establishing a power-on low voltage that is slowly increased based on a timed schedule or it may be performed in some other way. At block  629 , the Voltage Controller starts polling the Voltage ADC&#39;s and when the DUT&#39;s have reached the set point voltage, the Voltage Controller indicates a READY signal to the main controller. In the embodiments, described above, the Voltage Controller and the Main Controller are the same physical hardware. Similarly, at block  631 , the Temperature Controller starts to poll the Temperature ADC&#39;s and when the temperature has reached the desired set point also indicates READY to the main controller. At this stage, the instruction sequences may be sent to the DUT&#39;s. Accordingly, at block  633 , the PCD main controller initiates the Burn-In Driver. The BID then initiates the burn-in instruction sequences. However, any other type of test or diagnostic sequence may be initiated depending on the particular application.  
         [0094]     As the instruction sequences from the BID are executed by the DUT&#39;s, at block  635 , the Voltage Controller continues to poll the Voltage ADC&#39;s and maintain the temperature set point. At block  637 , the Temperature Controller continues to poll the Temperature ADC&#39;s, the temperature information is provided to the voltage controller and may also be provided to a thermal controller. As mentioned above, a variety of different algorithms may be applied to the voltage and temperature data to maintain the set points. Thermal, voltage, current, clock speed and other conditions may be adjusted to maintain the set points. As the test sequences are continued, the telemetry controller may also continue to provide telemetry streams to different devices as appropriate to the design of the system.  
         [0095]     After the test sequences have been executed, at block  639 , the Burn-In Driver indicates that the tests have been completed. It may also provide the test results to the Test Manager, to the PCD Controller and to any other appropriate components. Upon completion of the test, at block  641 , the PCD Controller depowers the DUT&#39;s, disengages and disables the thermal controller at block  643 , and powers down the Burn-In Board at block  645 . At block  647 , the Burn-in Board may be disconnected from the Power Distribution Board and the equipment rack. Finally, at block  649 , the Devices may be depopulated from the Burn-In Board. Using data collected by the Test Manager from the Burn-In Driver, the devices may be tagged as functional, defective, repairable, etc.  
         [0096]     A lesser or more equipped power distribution board, burn-in board, control system, burn-in cycle and test cycle than the examples described above may be preferred for certain implementations. Therefore, the configurations may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Embodiments of the invention may also be applied to other types of production processes that use components and device parameters than that shown in the Figures.  
         [0097]     In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.  
         [0098]     Embodiments of the present invention may include various operations. The operations of embodiments of the present invention may be performed by hardware components, such as those shown in the Figures, or may be embodied in machine-executable instructions, which may be used to cause general-purpose or special-purpose processor, microcontroller, or logic circuits programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software.  
         [0099]     Embodiments of the present invention may be provided as a computer program product which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices, such as microcontrollers) to perform a process according to embodiments of the present invention. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. Moreover, embodiments of the present invention may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).  
         [0100]     Many of the methods and apparatus are described in their most basic form but operations may be added to or deleted from any of the methods and components may be added or subtracted from any of the described apparatus without departing from the basic scope of the present claims. It will be apparent to those skilled in the art that many further modifications and adaptations may be made. The particular embodiments are not provided as limitations but as illustrations. The scope of the claims is not to be determined by the specific examples provided above but only by the claims below.