Abstract:
A switched current resistor (SCR) PGA for constant-bandwidth gain control includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and a switched current resistor (SCR) array connected in parallel to the feedback resistor, and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly to deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant.

Description:
BACKGROUND OF INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to a switched-current resistor (SCR) programmable gain array (PGA) targeted for wireless local area network (WLAN) applications. More specifically, embodiments of the present invention relate to an SCR PGA, where an SCR array may be employed in parallel with a feedback resistor to achieve constant bandwidth transient-free gain control. 
         [0003]    2. Background Art 
         [0004]    The rapid evolution of CMOS technology has accelerated the integration of mixed-signal systems, such as the wireless transceiver on a single chip. In the case of a zero intermediate-frequency (IF) or low IF receiver architecture targeted toward IEEE 802.11 a/b/g WLAN applications, signal levels arriving at the baseband are scaled to around a 0 dBm range for analog-to-digital conversion. With technology scaling, capacitive coupling in a zero IF receiver would increase enough to contribute to the de-offset problem. The dc-offset problem may be mitigated through the employment of a low-IF receiver, which also allows for increased integration. However, appropriate design of constituent circuits is vital under low voltage (LV) constraints. 
         [0005]      FIG. 1  shows the block diagram of a low-IF receiver  100  in a dual-receive conversion configuration. The receiver  100  may include a Radio Frequency (RF) input  105 , a Low Noise Amplifier (LNA)  110  followed by a mixer  115  with a Local Oscillator Reference Frequency (LO RF ) in the RF range. Due to the difference in the “in-phase” I and the “quadrature” Q signal, mixers  120  and  125  may have different IF reference frequencies (LO IF  (I) and LO IF  (Q)). Baseband channel selection filters  130  and  135 , and the PGAs  140  and  145 , complete the typical low IF receiver block diagram. PGAs are usually standard inverting amplifiers employing a switched-resistor bank for gain control. Terminals  150  and  155  constitute the output. A single synthesizer may synthesize both the IF and RF Local Oscillator (LO) frequencies. 
         [0006]    The dynamic-range requirement from the antenna (input terminal  105 ) to the baseband may approximately equal 0 to 80 dB, with the majority of the gain achieved in the baseband. If the radio front-end offers a 0 to 30 dB range, the baseband channel selection filters  130  and  135 , along with the PGAs  140  and  145  have to offer another 0 to 50 dB of controllable gain. Although cascading multiple PGAs may lead to such high gain ranges, excess bandwidths are required of the PGAs, sometimes equal to ten times the bandwidth of the channel-selection filters, to ensure stable selectivity against gain. 
         [0007]    Technology scaling within submicron scales, when accompanied with a standard power supply, may not necessitate a significant change in the design of analog blocks.  FIG. 2(   a ) shows a standard inverting amplifier  250  employing a switched-resistor bank R fb    220  for gain control, which serves as a PGA  200 . However, in tune with the burgeoning sub-volt nanoscale processes, the classic switched-resistor PGA  200  shown in  FIG. 2(   a ) may be rendered ineffectual because of insufficient LV headroom. 
         [0008]    One way to render an inverting amplifier  250  suitable for a minimum drain supply voltage (V DD ) is to use a level shifter. As shown in  FIG. 2(   a ), an extra input common-mode feedback (I-CMFB)  270  may explicitly bias the virtual ground V vg+  and V vg−  to a common-mode voltage V cm,in , which is the minimum saturation voltage V DSsat  (typically 0.1 V) necessary for the transistor to act as a current sink I b    260 . The lowest possible V DD  may be estimated by taking into account the voltage requirement into the input stage  252  (see the p-MOS differential pair  252  in  FIG. 2(   b )), and may be expressed as: 
         [0000]      V DD &gt;|V T,p +|2V SDsat +2V DSsat ,  (1) 
         [0000]    where V T,p  is the p-channel transistor threshold voltage, and V SDsat  is the source-drain saturation voltage.  FIG. 2(   b ) shows the input  252  and output  254  stages of the inverting amplifier  250  of the PGA  200 . 
         [0009]    For a V T,p  of −0.65 V, the lowest possible V DD  is approximately 1V. The output  254  stage of the inverting amplifier  250  may be a typical class-A amplifier  254  (see  FIG. 2(   b )), which delivers a high swing output by locking the output-common mode voltage (V cm,out ) to V DD /2. SS in  FIG. 2(   b ) refers to signal swing. However, a large output swing may require an output common-mode feedback (O-CMFB)  290 . For example, a resistive detector may be required to extract V cm,out  for conversion into a current signal for the back-end current amplifier. Gain tuning may be accomplished by varying either the feed-forward resistor R ff    215  or the feedback resistor R fb    220  via a switched-resistor bank comprising n-MOS transistor switches and associated resistors. Resistor  215  may also be included in the non-inverting terminal and resistor  220  in the feedback loop thereof. Therefore, the resistors in the non-inverting terminal and the feedback loop thereof are intentionally left unlabeled. The switches may be placed at V vg+  and V vg−  to gain enough overdrive voltage (V OD ) of roughly 0.3V. V OD  may be expressed as: 
         [0000]      V OD =V DD −V T,n −V DS,sat ,  (2) 
         [0000]    where V T,n  is the n-channel transistor threshold voltage. 
         [0010]    Additionally, two distinct reference voltages, V ref,in    272  of 0.1 V and V ref,out    285  of 0.5 V may be required (see  FIG. 2(   a )). Resistors  255  and  275  refer to R cm,in  and R cm,out  respectively, and resistors  265  and  280  appropriately refer to R cm,in /2 and R cm,out /2 respectively. Terminals  205  and  210  constitute the input (V in+  and V in− ) of the PGA  200 , and terminals  292  and  294  constitute the output (V out+  and V out− ). Amplifiers  267  and  268  are constituent elements of I-CMFB  270  and O-CMFB  290  respectively. V ref,out    285  should be buffered in order to be able to drive the O-CMFB  290  that drains static current. 
       SUMMARY OF INVENTION 
       [0011]    According to one aspect of one or more embodiments of the present invention, an SCR PGA for constant bandwidth gain control includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and an SCR array connected in parallel to the feedback resistor, and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. A constituent switched resistor of the plurality of switched resistors is connected to another switched resistor in parallel. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly such that the plurality of switched current sources deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant. 
         [0012]    According to one aspect of one or more embodiments of the present invention, a receiver for use in wireless local area networks includes a low noise amplifier, a first mixer with a first local oscillator reference frequency in an RF range, a second mixer with a second local oscillator reference frequency in an IF range, a channel selection filter, and an SCR PGA. The SCR PGA includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and an SCR array connected in parallel to the feedback resistor and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. A constituent switched resistor of the plurality of switched resistors is connected to another switched resistor in parallel. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly such that the plurality of switched current sources deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant. 
         [0013]    According to one aspect of one or more embodiments of the present invention, a method for realizing a constant bandwidth transient-free gain control in a PGA includes connecting a feedback resistor across an input side and an output side of the inverting amplifier, connecting an SCR array in parallel to the feedback resistor, the SCR array being configured to tune a gain range between a maximum and a minimum and including a plurality of switched resistors, each comprising a switch in series with a resistor, and switching the plurality of switched resistors by a gain-control logic such that a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly to deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant. A constituent switch resistor of the plurality of switched resistors is connected to another switched resistor in parallel. 
         [0014]    Other aspects and advantages of the invention will be apparent from the following description and the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0015]      FIG. 1  shows a block diagram of a receiver in accordance with one or more embodiments of the invention. 
           [0016]      FIG. 2(   a ) shows a typical low voltage (LV) switched-resistor PGA circuit. 
           [0017]      FIG. 2(   b ) shows the input and output stages of the inverting amplifier of the PGA  200 . 
           [0018]      FIG. 3  shows an SCR PGA in accordance with one or more embodiments of the invention. 
           [0019]      FIG. 4  shows an R-to-I conversion circuit for reference voltage and switched-current-sources generation in accordance with one or more embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Although the aforereferenced PGA structure of  FIG. 2  may be LV compliant, gain tuning through either R ff    215  or R fb    220  may vary the feedback factor independently of V DD , resulting in a gain-dependent output bandwidth. Secondly, as the input impedance of the PGA is mainly governed by R ff    215 , varying R ff    215  without adopting a preceding buffer of high impedance may draw a gain-dependent current from the previous stage. The previous stage may be a mixer or a passive filter in a receiver. In order to avoid high impedance buffers and mitigate the effects of loading in a multistage PGA, R fb    220  may be tuned instead. However, tuning of R fb    220  may induce another gain-dependent dc current I fb,dc  in the feedback loop due to the unequal common-mode levels of V cm,out  and V cm,in . This gain-dependent dc current may be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     
                       fb 
                       , 
                       dc 
                     
                   
                   = 
                   
                     ( 
                     
                       
                         
                           V 
                           
                             cm 
                             , 
                             out 
                           
                         
                         - 
                         
                           V 
                           
                             cm 
                             , 
                             in 
                           
                         
                       
                       
                         R 
                         fb 
                       
                     
                     ) 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    These unequal common-model levels and the associated gain-dependent dc current may entail a long settling time to re-stabilize the input-output (I/O) CMFBs and the opamp at a new quiescent operating point. 
         [0021]    Specific embodiments of the invention will now be described in detail with reference to the accompanying figures. Like elements in the various figures are denoted by like reference numerals for consistency. 
         [0022]    In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description. 
         [0023]    In general, embodiments of the present invention describe an SCR PGA that provides for gain-independent output bandwidths, sinks out the unwanted gain-dependent dc current, and dispels the need for buffers. In one or more embodiments, such an SCR PGA may be operational underneath a very low-voltage (LV) V DD  of 1V or less. For simplicity sake, a V DD  of 1V is assumed in the detailed description below. One of ordinary skill in the art will recognize that other V DD  values may be used in accordance with one or more embodiments of the present invention. 
         [0024]      FIG. 3  shows an SCR PGA  300  in accordance with one or more embodiments of the invention Analogous to  FIG. 2(   a ), amplifier  350  is the inverting amplifier, resistor R ff    315  is the feed forward resistor, and resistor R fb    320  is the feedback resistor. In one or more embodiments, as resistor  315  may also be included in the non-inverting terminal of amplifier  350 , the resistor in the non-inverting terminal is intentionally left unlabeled. Terminals  305  and  310  constitute the input (V in ), CMFB circuits  370  and  390  are the I-CMFB and O-CMFB respectively, and terminals  392  and  394  constitute the output (V out ). Current sink  360  is the current sink I b , resistors  355  and  375  refer to R cm,in  and R cm,out  respectively, and resistors  365  and  380  appropriately refer to R cm,in  and R cm,out /2 respectively. Amplifiers  367  and  368  are constituent elements of I-CMFB  370  and O-CMFB  390  respectively. 
         [0025]    In one or more embodiments, a set of switched resistors  322 , 1  to  322 ,n (i.e. R fb,1  . . . R fb,n ) may be added in parallel with R fb    320  to achieve a tunable gain range between a maximum of 
         [0000]    
       
         
           
             - 
             
               
                 R 
                 fb 
               
               
                 R 
                 ff 
               
             
           
         
       
     
         [0000]    and a minimum of 
         [0000]    
       
         
           
             - 
             
               
                 ( 
                 
                   
                     R 
                     fb 
                   
                    
                   
                      
                     
                       
                         R 
                         
                           fb 
                           , 
                           1 
                         
                       
                        
                       … 
                     
                      
                   
                    
                   
                     R 
                     
                       fb 
                       , 
                       n 
                     
                   
                 
                 ) 
               
               
                 R 
                 ff 
               
             
           
         
       
     
         [0000]    In one embodiment, when  322 , 1  . . .  322 ,n (R fb,1  . . . R fb,n ) are switched by the gain-control logic  323 , 1  . . .  323 ,n (b c,1  . . . b c,n ) of the switches in the SCR bank, a set of switched current sources  326 , 1  . . .  326 ,n (I fb,1  . . . I fb,n ) and grounded resistors  324 , 1  . . .  324 ,n (R x,1  . . . R x,n ) may be switched correspondingly such that  326 , 1  . . .  326 ,n (I fb,1  . . . I fb,n ) may replace the opamp to deliver the transient current, while  324 , 1  . . .  324 ,n (R x,1  . . . R x,n ) may sink the same current out from V vg−  as given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         fb 
                         , 
                         n 
                       
                     
                     = 
                     
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 
                                   c 
                                    
                                   
                                       
                                   
                                    
                                   m 
                                 
                                 , 
                                 
                                   out 
                                   - 
                                 
                               
                             
                              
                             
                               V 
                               
                                 
                                   c 
                                    
                                   
                                       
                                   
                                    
                                   m 
                                 
                                 , 
                                 
                                   i 
                                    
                                   
                                       
                                   
                                    
                                   n 
                                 
                               
                             
                           
                           
                             R 
                             
                               fb 
                               , 
                               n 
                             
                           
                         
                         ) 
                       
                       = 
                       
                         
                           V 
                           
                             
                               c 
                                
                               
                                   
                               
                                
                               m 
                             
                             , 
                             
                               i 
                                
                               
                                   
                               
                                
                               n 
                             
                           
                         
                         
                           R 
                           
                             x 
                             , 
                             n 
                           
                         
                       
                     
                   
                   , 
                   
                     
                       for 
                        
                       
                           
                       
                        
                       n 
                     
                     = 
                     1 
                   
                   , 
                   2 
                   , 
                   
                     3 
                      
                     
                         
                     
                      
                     … 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0026]    In one or more embodiments, equalizing the last two terms of Equation (4) over process, voltage, and temperature (PVT) variation is not complicated because V cm,out  and V cm,in  (see  FIG. 2(   b )) are mirrors of V ref,out    385  and V ref,in    372  respectively. In one or more embodiments, V ref,out    385  and V ref,in    372  may be generated underneath one master V DD  (for e.g., V ref,out =V DD /2, and V ref,in =V DD /10), while R fb,n    322 ,n and R x,n    324 ,n may be synthesized using the same unit resistor R u  (for e.g., R fb,n =α n R u =4R x,n , for n=1,2,3 . . . . Here α n  is a positive integer representing a resistive ratio). Any PVT variation may result in a common-mode disturbance in the last two terms of Equation (4). In one or more embodiments, matching the first term of Equation (4) to the rest may involve an extra signal conversion such that the newly generated switched current sources (I′ fb,1  . . . I′ fb,n ) may track the PVT variations of  322 , 1  . . .  322 ,n (R fb,1  . . . R fb,n ),  324 , 1  . . .  324 ,n (R x,1  . . . R x,n ) V ref,out    385 , and V ref,in    372 . In one or more embodiments, the SCR bank may be driven by two potential levels, V DD  and V SS . 
         [0027]      FIG. 4  shows a LV resistor-current (R-to-I) conversion circuit  400  for generating V ref,out , V ref,in  and I′ fb,1  . . . I′ fb,n , as discussed above, in accordance with one or more embodiments of the invention. Such a circuit may approach the ideal I fb, 1  . . . I fb, n , as governed by Equation (4). In one or more embodiments, the R-to-I conversion circuit  400  may include a reference-voltage generation section  460 , an R-to-I conversion section  470 , and a switched current source section  480 . In one or more embodiments, an error amplifier A error    425  in a feedback loop may track the absolute value of P 3    420  underneath a fixed voltage V z . Therefore, the corresponding reference current I fb,ref  is proportional to 
         [0000]    
       
         
           
             
               1 
               
                 R 
                 3 
               
             
             . 
           
         
       
     
         [0000]    In one embodiment, V z  may be a mirror of V x  that may be set to 0.1 V (V DD /10), thereby enabling A error    425  to be realized via a p-channel differential pair. Resistors  405 ,  410 ,  415  are resistors R 1 , R 2 , R 4  respectively, and transistor  430  is a dummy transistor M d . I fb,ref  may be mirrored afterward to the switched current sources I′ fb,1  . . . I′ fb,n  through transistors M 1    435  to M b,1 , . . . M b,n , which may feature the same ratios of R fb,1  to R fb,1  . . . R fb,n . I′ fb,n  may be related to the normalized R fb,1  through example Equation (5) as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         fb 
                         , 
                         n 
                       
                       l 
                     
                     = 
                     
                       
                         
                           V 
                           z 
                         
                         
                           R 
                           3 
                         
                       
                        
                       
                         ( 
                         
                           
                             R 
                             
                               fb 
                               , 
                               1 
                             
                           
                           
                             R 
                             
                               fb 
                               , 
                               n 
                             
                           
                         
                         ) 
                       
                     
                   
                   , 
                   
                     
                       for 
                        
                       
                           
                       
                        
                       n 
                     
                     = 
                     1 
                   
                   , 
                   2 
                   , 
                   
                     3 
                      
                     
                         
                     
                      
                     … 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0028]    Making I′ fb,n  proportional to just 
         [0000]    
       
         
           
             
               V 
               z 
             
             
               R 
               
                 fb 
                 , 
                 n 
               
             
           
         
       
     
         [0000]    may be done by substituting R 3    420  with 
         [0000]    
       
         
           
             
               
                 R 
                 
                   fb 
                   , 
                   1 
                 
               
               4 
             
             . 
           
         
       
     
         [0000]    This may equalize the numerator of Equation (5) to the second term of Equation (4), (i.e., 4V z =V cm,out −V cm,in ), resulting in example Equation (6) 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         fb 
                         , 
                         n 
                       
                       l 
                     
                     = 
                     
                       
                         4 
                          
                         
                           V 
                           z 
                         
                       
                       
                         R 
                         
                           fb 
                           , 
                           n 
                         
                       
                     
                   
                   , 
                   
                     
                       for 
                        
                       
                           
                       
                        
                       n 
                     
                     = 
                     1 
                   
                   , 
                   2 
                   , 
                   
                     3 
                      
                     
                         
                     
                      
                     … 
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0029]    Substituting Equation (6) back into the first term of Equation (4), and replacing R fb,n  and R x,n  in accordance with α n R u =R fb,n =4R x,n  may lead to example Equation (7) as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         4 
                          
                         
                           V 
                           z 
                         
                       
                       
                         
                           α 
                           n 
                         
                          
                         
                           R 
                           u 
                         
                       
                     
                     = 
                     
                       
                         
                           
                             V 
                             
                               
                                 c 
                                  
                                 
                                     
                                 
                                  
                                 m 
                               
                               , 
                               out 
                             
                           
                           - 
                           
                             V 
                             
                               
                                 c 
                                  
                                 
                                     
                                 
                                  
                                 m 
                               
                               , 
                               
                                 i 
                                  
                                 
                                     
                                 
                                  
                                 n 
                               
                             
                           
                         
                         
                           
                             α 
                             n 
                           
                            
                           
                             R 
                             u 
                           
                         
                       
                       = 
                       
                         
                           V 
                           
                             
                               c 
                                
                               
                                   
                               
                                
                               m 
                             
                             , 
                             
                               i 
                                
                               
                                   
                               
                                
                               n 
                             
                           
                         
                         
                           
                             
                               α 
                               n 
                             
                             4 
                           
                            
                           
                             R 
                             u 
                           
                         
                       
                     
                   
                   , 
                   
                     
                       for 
                        
                       
                           
                       
                        
                       n 
                     
                     = 
                     1 
                   
                   , 
                   2 
                   , 
                   
                     3 
                      
                     
                         
                     
                      
                     … 
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0030]    In one or more embodiments, as V z , V cm,out , and V cm,in  (see  FIG. 2(   b ) and  FIG. 4)  are mirrors of V x =V DD /10, V ref,out =V DD /2, and V ref,in =V   DD /10, the error voltage (V δ ) associated with V DD , and the error resistance (R δ ) associated with R u  may have no effect on the balancing of Equation (7). This may be expressed as example Equation (8): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           
                             4 
                              
                             
                               
                                 ( 
                                 
                                   
                                     V 
                                     DD 
                                   
                                   ± 
                                   
                                     V 
                                     δ 
                                   
                                 
                                 ) 
                               
                               10 
                             
                           
                           
                             
                               α 
                               n 
                             
                              
                             
                               ( 
                               
                                 
                                   R 
                                   u 
                                 
                                 ± 
                                 
                                   R 
                                   δ 
                                 
                               
                               ) 
                             
                           
                         
                         = 
                           
                          
                         
                           
                             
                               
                                 ( 
                                 
                                   
                                     V 
                                     DD 
                                   
                                   ± 
                                   
                                     V 
                                     δ 
                                   
                                 
                                 ) 
                               
                               2 
                             
                             - 
                             
                               
                                 ( 
                                 
                                   
                                     V 
                                     DD 
                                   
                                   ± 
                                   
                                     V 
                                     δ 
                                   
                                 
                                 ) 
                               
                               10 
                             
                           
                           
                             
                               α 
                               n 
                             
                              
                             
                               ( 
                               
                                 
                                   R 
                                   u 
                                 
                                 ± 
                                 
                                   R 
                                   δ 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             
                               ( 
                               
                                 
                                   V 
                                   DD 
                                 
                                 ± 
                                 
                                   V 
                                   δ 
                                 
                               
                               ) 
                             
                             10 
                           
                           
                             
                               
                                 α 
                                 n 
                               
                               4 
                             
                              
                             
                               ( 
                               
                                 
                                   R 
                                   u 
                                 
                                 ± 
                                 
                                   R 
                                   δ 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0031]    In one or more embodiments, as seen from example Equation (8), the R-to-I conversion circuit may yield an overall PVT-insensitive operation, whose employment may further the static and dynamic performances of the SCR PGA. 
         [0032]    In one or more embodiments, the current mirror M 1  to M b,1  . . . M b,n  may raise the precision by adding 
         [0000]    
       
         
           
             
               
                 R 
                 4 
               
               = 
               
                 
                   
                     R 
                     3 
                   
                    
                   
                     ( 
                     
                       
                         V 
                         D 
                       
                       - 
                       
                         V 
                         z 
                       
                     
                     ) 
                   
                 
                 
                   V 
                   z 
                 
               
             
             , 
           
         
       
     
         [0000]    thereby level shifting the drain voltage V D  of M 1  to match that of M b,1  . . . M b,n . 
         [0033]    In one or more embodiments, the overall resistor matching, and the ground-noise rejection of A error    425  and A ref    440  may be enhanced by selecting, for example, 
         [0000]    
       
         
           
             
               
                 R 
                 1 
               
               = 
               
                 
                   
                     R 
                     2 
                   
                   9 
                 
                 = 
                 
                   
                     R 
                     3 
                   
                   = 
                   
                     
                       
                         R 
                         4 
                       
                       4 
                     
                     = 
                     
                       
                         R 
                         5 
                       
                       = 
                       
                         
                           R 
                           6 
                         
                         4 
                       
                     
                   
                 
               
             
             , 
           
         
       
     
         [0000]    thereby resulting in a resistor spread of just 9. Here, A ref    440  may form a non-inverting amplifier for buffering V ref,out . In  FIG. 4 , resistors  445  and  450  refer to resistors R 5 , one side of which is driven at V SS , and R 6  respectively. 
         [0034]    In one or more embodiments, I′ fb,1  . . . I′ fb,n  may be switched through transistors M s,1  . . . M s,n  rather than M b,1  . . . M b,n  such that M s,1  . . . M s,n  may attain the maximum overdrive voltage, leading to reduced device sizes and lower charge injection values. In one embodiment, as only the current paths are opened, the gate-to-source capacitance of M b,1  . . . M b,n  may be kept charged for a faster turn-on time. 
         [0035]    In one or more embodiments, connecting M b,1  . . . M b,n  to V DD  may prevent charge injection of M s,1  . . . M s,n  from coupling to the gates thereof through a body-to-gate parasitic capacitance thereof, thereby theoretically yielding 200% to 300% shorter transients depending on the gain step. 
         [0036]    In one or more embodiments, the feedback factor β PGA  may be expressed as example Equation (9): 
         [0000]    
       
         
           
             
               
                 
                   
                     β 
                     PGA 
                   
                   = 
                   
                     1 
                     
                       ( 
                       
                         1 
                         + 
                         
                           ( 
                           
                             
                               
                                 R 
                                 fh 
                               
                                
                               
                                  
                                 
                                   
                                     R 
                                     
                                       fh 
                                       , 
                                       t 
                                     
                                   
                                    
                                   
                                       
                                   
                                    
                                   … 
                                 
                                  
                               
                                
                               
                                 R 
                                 
                                   fb 
                                   , 
                                   n 
                                 
                               
                             
                             
                               
                                 R 
                                 ff 
                               
                                
                               
                                  
                                 
                                   
                                     R 
                                     
                                       x 
                                       , 
                                       1 
                                     
                                   
                                    
                                   
                                       
                                   
                                    
                                   … 
                                 
                                  
                               
                                
                               
                                 R 
                                 
                                   x 
                                   , 
                                   n 
                                 
                               
                             
                           
                           ) 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0037]    In one or more embodiments, β PGA  may be stabilized when the two conditions ((10) and (11)) specified below are satisfied concurrently. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           R 
                           fb 
                         
                         
                           R 
                           ff 
                         
                       
                       = 
                       
                         
                           
                             R 
                             fb 
                           
                           
                             R 
                             
                               x 
                               , 
                               n 
                             
                           
                         
                         ≤ 
                         
                           
                             
                               V 
                               
                                 
                                   c 
                                    
                                   
                                       
                                   
                                    
                                   m 
                                 
                                 , 
                                 out 
                               
                             
                             - 
                             
                               V 
                               
                                 
                                   c 
                                    
                                   
                                       
                                   
                                    
                                   m 
                                 
                                 , 
                                 
                                   i 
                                    
                                   
                                       
                                   
                                    
                                   n 
                                 
                               
                             
                           
                           
                             V 
                             
                               
                                 c 
                                  
                                 
                                     
                                 
                                  
                                 m 
                               
                               , 
                               
                                 i 
                                  
                                 
                                     
                                 
                                  
                                 n 
                               
                             
                           
                         
                       
                     
                     , 
                     
                       
                         for 
                          
                         
                             
                         
                          
                         n 
                       
                       = 
                       1 
                     
                     , 
                     2 
                     , 
                     
                       3 
                        
                       
                           
                       
                        
                       … 
                     
                   
                    
                   
                     
 
                   
                    
                   and 
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
             
               
                 
                   
                     β 
                     PGA 
                   
                   ≤ 
                   
                     
                       V 
                       
                         
                           c 
                            
                           
                               
                           
                            
                           m 
                         
                         , 
                         
                           i 
                            
                           
                               
                           
                            
                           n 
                         
                       
                     
                     
                       V 
                       
                         
                           c 
                            
                           
                               
                           
                            
                           m 
                         
                         , 
                         out 
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0038]    As conditions (10) and (11) depend on relative ratio rather than absolute values, β PGA  may be robustly stabilized against gain over PVT. Advantages of a constant β PGA  may include unvarying settling time and constant stopband rejection. 
         [0039]    In one or more embodiments, the constancy of PGA may practically depend on the ratio of resistances of R cm,in  to R ff  of and R x,1  . . . R x,n . Even with a large R cm,in  in comparison to R ff ∥R x,1  . . . ∥R x,n , β PGA  may only vary in very small quantities, leading to only a small bandwidth variation. In one or more embodiments, identical PGAs may be cascaded to attain required gain range. Although identical cascaded PGAs reduce bandwidth, which is multiplied by a factor of 
         [0000]    
       
         
           
             
               
                 2 
                 
                   1 
                   N 
                 
               
               - 
               1 
             
           
         
       
     
         [0000]    (N being the number of cascaded stages), a large β PGA  may result in a net bandwidth enlargement, with an obvious increase in power due to increase in the number of PGAs. 
         [0040]    It will be obvious to one of ordinary skill in the art that the abovementioned SCR circuit details, transistor types and choices, R-to-I conversion circuit elements, R-to-I conversion choice parameters, input and output sections of the SCR PGA all are explained for clarity purposes and any variations in them would not depart from the scope of the invention. Modifications in the aforementioned are well within the scope of the invention. 
         [0041]    In one or more embodiments, dc-offset cancellation may be incorporated for a fully differential circuit implementation, whereby the even-harmonic distortion may be suppressed effectively such that only the odd harmonics are dominant. In one embodiment, an example determination of the third-harmonic distortion (HD3) of a highly linear resistor in series with a nonlinear n-MOS switch would require an assumption of reception of the sinusoidal signal by the terminal in the resistor side, with the terminal in the switch side being grounded. HD3 may then be expressed in the form of example Equation (12) as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       HD 
                        
                       
                           
                       
                        
                       3 
                     
                     ≈ 
                     
                       
                         3 
                         32 
                       
                        
                       
                         
                           
                             ( 
                             
                               
                                 V 
                                 
                                   
                                     out 
                                     - 
                                   
                                   , 
                                   p 
                                 
                               
                               
                                 
                                   V 
                                   g 
                                 
                                 - 
                                 
                                   V 
                                   
                                     
                                       c 
                                        
                                       
                                           
                                       
                                        
                                       m 
                                     
                                     , 
                                     
                                       i 
                                        
                                       
                                           
                                       
                                        
                                       n 
                                     
                                   
                                 
                                 - 
                                 
                                   V 
                                   
                                     T 
                                     , 
                                     n 
                                   
                                 
                               
                             
                             ) 
                           
                           2 
                         
                         · 
                         
                           
                             ( 
                             
                               
                                 r 
                                 on 
                               
                               
                                 R 
                                 fb 
                               
                             
                             ) 
                           
                           3 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where V g  is the transistor gate voltage, V out−,p  is the peak value of the output voltage, and r on  is the transistor on-resistance. For example, for a HD3 of a very low level, r on  may be a small fraction, albeit sizeable, of R fb . This indicates that explicitly biasing V cm,in  to a value close to one of the supply rails may help improve the linearity due to an increase in V OD . 
         [0042]    In one or more embodiments, the squared output thermal noise of the PGA may be lowered by keeping the resistor spread small and increasing the level of V cm,in . 
         [0043]    As discussed above, one or more embodiments of the SCR PGA offers advantages, not limited to a stable feedback factor, transient-free gain control, and elimination of loading effects in a multi-stage PGA. In one or more embodiments, stable selectivity against gain is ensured as the bandwidth requirement of the PGA may be relaxed. In one such embodiment, the bandwidth requirement of the PGA may be relaxed to less than 20 MHz. In one or more embodiments, reduction of the settling times in gain change may be achieved, and one or more embodiments may offer enhanced stopband rejection. 
         [0044]    While the invention has been described with respect to an exemplary embodiment of an SCR PGA for achieving a constant bandwidth transient-free gain control, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.