Abstract:
An apparatus for providing programmable hysteresis control using an enable pin of a device is disclosed. An enable pin is configured to receive an input signal to enable and disable an associated device responsive to the input signal. A current sink is attached to the enable pin and is responsive to circuitry that disables the current sink responsive to application of the input signal at a first voltage level and enables the current sink responsive to application of the input signal at a second voltage level.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 10/917,628, filed Aug. 13, 2004, entitled ENABLE PIN USING PROGRAMMABLE HYSTERESIS IMPROVEMENT (Atty. Dkt. No. INTS-26,792) which claims benefit of U.S. Provisional Application No. 60/553,923, filed Mar. 17, 2004, entitled PROGRAMMABLE HYSTERESIS IMPROVEMENT (Atty. Dkt. No. INTS-26,694), the specifications of which are incorporated herein in their entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to DC-DC converters, and more particularly, to an enable pin of a DC-DC converter or similar device. 
       BACKGROUND 
       [0003]    The enable pin of a DC-DC converter or other type of device may be used for voltage monitoring in some applications. Existing designs establish a precision threshold with which to enable a DC-DC converter or similar device given a particular application requirement. Prior art designs use a current source that sources current into the enable pin after logical assertion of the enable signal to the enable pin to provide hysteresis control. However, in certain applications, a current source may not be used because the enable pin is being multiplexed to perform other functions. In one example, the enable pin may be utilized to activate a test/trim mode. If a positive current source were applied to the enable pin in these circumstances, a parasitic diode would result that would prevent the enable pin from being used to activate the test/trim mode. Thus, there is a need to establish some other manner for establishing a hysteresis magnitude that does not require the application of a current source to the enable pin. 
       SUMMARY 
       [0004]    The present invention disclosed and claimed herein, in one aspect thereof, comprises an apparatus for providing programmable hysteresis control within a device. An enable pin of the device is configured to receive an input signal that enables or disables the associated device responsive to the input signal. A current source is attached to the enable pin as the current sink. The current source is responsive to control circuitry that disables the current sink responsive to application of the input signal at a first voltage level to the enable pin and enables the current sink responsive to application of the input voltage at a second level to the enable pin. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which: 
           [0006]      FIG. 1  is a block diagram of a DC-DC converter in which the enable pin design of the present disclosure may be implemented; 
           [0007]      FIG. 2  is a schematic diagram of a circuit for providing hysteresis control according to the present invention; and 
           [0008]      FIG. 3  is a flow diagram illustrating the operation of the circuit of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    Referring now to the drawings, and more particularly to  FIG. 1 , wherein there is illustrated the general circuit configuration of a conventional DC-DC voltage converter as comprising a DC-DC controller, which fully controls the turn on and turn off of a pair of electronic switching devices, respectively, shown as an upper FET pass element  120  and a lower FET pass element  130 . These FET switching devices have their drain/source paths coupled in between first and second reference voltages V DD  and ground (GND). Each pass element contains a controllable switch shown as an upper switch  122  and a lower switch  132 . The upper pass element contains a body diode  121  in parallel with the drain/source path such that the reverse current flows through the diode body toward V DD . A lower pass element  130  contains a body diode  131  in parallel with the drain/source path such that the reverse current flows through the body diode from ground. A common or phase voltage  125  between the two power FETs  120 / 130  is coupled through an inductor  140  to a capacitor  150  coupled to a reference voltage (GND). The connection  145  between the inductor  140  and the capacitor  150  serves as an output node from which the output voltage VOUT is derived. 
         [0010]    The DC-DC converter&#39;s controller  110  includes a gate driver circuit  111 , that is operative to turn the two switching devices  120  and  130  on and off, in accordance with a periodic pulse wave form (typically, a pulse width modulation (PWM) switching wave form generated by a PWM logic circuit  112 ). The upper circuit  122  is turned on and off by an upper gate switch signal UG applied by the gate driver  111  to the gate of the pass element  120 , and the lower switch  132  is turned on and off by a lower gate signal LG applied to the gate driver  111  to the gate of the pass element  130 . 
         [0011]      FIG. 2  illustrates the manner in which an enable pin  202  associated with the DC-DC converter  102  of  FIG. 1  may be configured to enable operation of the DC-DC converter  102  and provide hysteresis control. While the present description is made with respect to an enable pin of a DC-DC converter, any device having an enable pin may find this configuration useful. The enable pin  202  provides a SYS_ENABLE signal  203  to enable the DC-DC voltage converter  102 . The enable pin  202 , in addition to enabling the DC-DC voltage converter  102 , may be used for other functions. These functions include voltage monitoring within the DC-DC converter  102  and activation of test/trim modes within the DC-DC converter  102 . As discussed herein above, previous implementations have utilized a current source sourcing to the enable pin to set hysteresis magnitude and provide hysteresis control. However, this can create an undesired parasitic diode in certain applications. 
         [0012]    The present embodiment includes a first resistor R UP    204  connected between an input voltage V IN  and a node  208  connected to the enable pin  202 . A second resistor R DOWN    206  is connected between node  208  and ground. The resistor pair R UP    204  and R DOWN    206  form a resistor divider network. The enable pin  202  is connected to a positive input of a comparator  210 . The negative input of the comparator  210  is connected to a reference voltage V REF  which enables comparison of the input voltage applied to the enable pin  202  to the reference voltage V REF . A current source  212  is connected between the enable pin  102  and ground to act as a current sink. The current source  212  is responsive to the SYS_ENABLE signal  203  and is active when the enable pin is receiving a logical level for a disable signal that disables the DC-DC converter  102  and is inactive when the enable pin  102  is receiving a logical level for an enable signal for the DC-DC converter  102 . This configuration enables the enable pin  202  to be used for controlling a programmable hysteresis when the enable pin  202  is being used for voltage monitoring. 
         [0013]    While the input voltage V IN  is ramping up to a targeted threshold voltage V REF , the resistor divider network, consisting of resistor  104  and resistor  106 , scales V IN  to match the internal reference voltage V REF  being applied to the negative input of the comparator  110 . At the same time, the current source  112  is acting as a current sink and actively pulling down on the enable pin  102  to provide an additional voltage offset which is compensated for in the selection of the values R UP  and R DOWN  for resistors  104  and  106 . The values of R UP  and R DOWN  may be determined according to the following equations 
         [0000]    
       
         
           
             
               R 
               UP 
             
             = 
             
               
                 V 
                 EN_HYS 
               
               
                 I 
                 EN_HYS 
               
             
           
         
       
       
         
           
             
               R 
               DOWN 
             
             = 
             
               
                 
                   R 
                   UP 
                 
                 * 
                 
                   V 
                   EN_REF 
                 
               
               
                 
                   V 
                   EN_FTH 
                 
                 - 
                 
                   V 
                   EN_REF 
                 
               
             
           
         
       
       
         
           
             
               V 
               EN_FTH 
             
             = 
             
               
                 V 
                 EN_RTH 
               
               - 
               
                 V 
                 EN_HYS 
               
             
           
         
       
       
         
           
             wherein: V EN     —     HYS =a desired magnitude of hysteresis;
           V EN     —     FTH =a desired falling voltage trip point;   V EN     —     RTH =an enable rising threshold; and   I EN     —     HYS =the value of the current provided by current source  112 .   
         
           
         
       
     
         [0018]    When the input voltage V IN  causes the voltage applied to the enable pin  202  to exceed the reference voltage V REF , the comparator  210  provides a logic signal at a first level that deactivates the current source  212  and enables the DC-DC voltage regulator. The deactivation of the current source  212  causes the voltage on the enable pin  202  to increase, thus adding positive feedback hysteresis to the DC-DC voltage converter  102  and improves input noise immunity. 
         [0019]    When the input voltage V IN  causes the voltage applied to the enable pin  202  to decrease to a voltage level lower than the reference voltage V REF  threshold, the comparator  210  provides a logic signal at a second level that activates the current source  212 . Provision of the logic signal at the second level by the comparator  210  will also deactivate the associated DC-DC voltage converter  102 . When the current source  212  activates, the voltage level on the enable pin  102  is pulled even lower and adds positive feedback hysteresis to the system. 
         [0020]    Referring now to  FIG. 3 , there is illustrated a flow diagram describing the manner in which the circuit of  FIG. 2  operates. Initially, the enable pin  202  is provided with a logical disable signal at a selected voltage level, and the output of comparator  210  will provide a false signal, causing the current source  212  to be activated at step  300 . Inquiry step  302  determines whether the voltage applied at the enable pin  202  exceeds the reference voltage V REF . If the reference voltage V REF  is greater than the voltage on the enable pin  202 , the comparator  210  continues to provide a logical false signal at step  304 . When the enable pin voltage exceeds the reference voltage V REF , the comparator  210  asserts a logical true signal at step  306 . Assertion of the logical true signal at step  306  causes the current source  212  to be deactivated at step  308 . 
         [0021]    Once the current source  212  has been deactivated, inquiry step  310  determines if the enable pin voltage is less than the reference voltage V REF  at the comparator  210 . If the enable pin voltage is not less than the reference voltage V REF , the comparator  210  output continues asserting a logical true signal at step  312 . When the enable pin voltage drops below the reference voltage V IN , the comparator  210  will assert a logical false signal at step  314 . The logical false signal asserted by the comparator  210  causes the current source  212  to be activated at step  316 . Once the current source  212  is activated at step  316 , control returns to step  302 . 
         [0022]    Using the above-described configuration, the enable pin  202  may be used for additional purposes, such as multiplexing the enable pin  202  functionality to activate a test/trim mode. This configuration is distinct from existing designs which have the current source initially on and deactivate the current source after assertion of the enable pin to provide a programmable hysteresis functionality. 
         [0023]    Although the preferred embodiment has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.