Abstract:
According to the present invention, there is provided a method of routing a semiconductor integrated circuit by using a routing apparatus having an input unit, a storage unit, and an arithmetic unit, comprising: receiving, by the input unit, for respective terminals of a plurality of elements contained in the semiconductor integrated circuit, wiring enable/disable information which sets a region where connection of a wiring line is enabled and a region where connection of a wiring line is disabled, and storing, by the storage unit, the wiring enable/disable information; and determining, by the arithmetic unit, by using the wiring enable/disable information stored in the storage unit, whether connection of a wiring line to a predetermined portion of the terminal of the element is enabled, and when the arithmetic unit determines that connection of the wiring line is enabled, execute connection.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims benefit of priority under 35 USC § 119 from the Japanese Patent Application No. 2005-37503, filed on Feb. 15, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a semiconductor integrated circuit routing method and a recording medium which stores routing software.  
         [0003]     To perform automatic place &amp; routing using elements such as a standard cell in a semiconductor integrated circuit, it is necessary to place a plurality of elements and then connect the terminals of the elements by wiring lines.  
         [0004]     A conventional routing process uses only rectangle information on the outer shapes of the terminal and wiring line. A notch may be formed in connecting a wiring line to an element. As micropatterning in the process progresses, the presence of a circuit pattern containing a notch poses a problem in a patterning process.  
         [0005]     If, however, the wiring shape is so changed as to bury the notch, the wiring width becomes larger, and the wiring interval must be widened, undesirably increasing the circuit area.  
         [0006]     In some cases, the interval must be designed larger than a wiring interval permitted by the design rule depending on the longitudinal directions of a terminal and wiring line, a wiring enable region where connection of a wiring line to a terminal is enabled, or a wiring disable region where connection of a wiring line is disabled. The conventional routing process is, however, performed on the basis of simple rectangle information of a terminal, as described above. The process cannot be done in consideration of the directions of a terminal and wiring line and the wiring enable region and wiring disable region of a terminal, decreasing the process efficiency or unnecessarily increasing the circuit area.  
         [0007]     A reference concerning a conventional routing method is as follows.  
         [0008]     Japanese Patent Laid-Open No. 2002-313921  
       SUMMARY OF THE INVENTION  
       [0009]     According to one aspect of the invention, there is provided a method of routing a semiconductor integrated circuit by using a routing apparatus having an input unit, a storage unit, and an arithmetic unit, comprising:  
         [0010]     receiving, by the input unit, for respective terminals of a plurality of elements contained in the semiconductor integrated circuit, wiring enable/disable information which sets a region where connection of a wiring line is enabled and a region where connection of a wiring line is disabled, and storing, by the storage unit, the wiring enable/disable information; and  
         [0011]     determining, by the arithmetic unit, by using the wiring enable/disable information stored in the storage unit, whether connection of a wiring line to a predetermined portion of the terminal of the element is enabled, and when the arithmetic unit determines that connection of the wiring line is enabled, execute connection.  
         [0012]     According to one aspect of the invention, there is provided a computer-readable recording medium which stores software for executing routing of a semiconductor integrated circuit, wherein the routing software causes a computer to execute a routing method comprising,  
         [0013]     setting, for respective terminals of a plurality of elements contained in the semiconductor integrated circuit, a region where connection of a wiring line is enabled and a region where connection of a wiring line is disabled, and setting wiring enable/disable information, and  
         [0014]     determining on the basis of the wiring enable/disable information whether connection of a wiring line to a predetermined portion of the terminal of the element is enabled, and when connection of the wiring line is determined to be enabled, executing connection.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  is an explanatory view showing contents defined in information used in a routing method according to a comparative example;  
         [0016]      FIG. 2  is an explanatory view showing a wiring enable region and wiring disable region which are defined in information used in a routing method according to the first embodiment;  
         [0017]      FIG. 3  is an explanatory view showing an example of routing on the basis of the information according to the first embodiment;  
         [0018]      FIG. 4  is a flowchart showing a sequence from determination of the specifications of a semiconductor integrated circuit to fabrication of the semiconductor integrated circuit;  
         [0019]      FIG. 5  is a flowchart showing the sequence of the routing method according to the first embodiment;  
         [0020]      FIG. 6  is a block diagram showing the arrangement of a routing apparatus implemented by software which causes a computer to execute the routing method;  
         [0021]      FIG. 7  is an explanatory view showing an example of the description format of information on a terminal that is used in the comparative example;  
         [0022]      FIG. 8  is an explanatory view showing an example of the description format of information on a terminal that is used in the routing method according to the first embodiment;  
         [0023]      FIG. 9  is a flowchart showing the sequence of a routing method according to the second embodiment of the present invention;  
         [0024]      FIG. 10  is an explanatory view showing the definition of a wiring line according to the second embodiment;  
         [0025]      FIG. 11  is an explanatory view showing one step in the routing method according to the second embodiment;  
         [0026]      FIG. 12  is an explanatory view showing one step in the routing method according to the second embodiment;  
         [0027]      FIG. 13  is an explanatory view showing the definition of a signal transfer direction in a routing method according to the third embodiment of the present invention;  
         [0028]      FIG. 14  is an explanatory view showing interference between different signals in accordance with the signal transfer direction in the routing method according to the third embodiment; and  
         [0029]      FIG. 15  is a flowchart showing the sequence of a process in the routing method according to the third embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]     Embodiments of the present invention will be described below with reference to the accompanying drawings.  
       (1) First Embodiment  
       [0031]     Contents defined in information used in a routing method according to a comparative example will be described.  
         [0032]     In a semiconductor integrated circuit  10  shown in  FIG. 1 , a notch  101   a  may be formed when a wiring line W 102  in the X direction is connected to a terminal P 101  at a distance X 1  in accordance with the design rule in connecting the terminal P 101  whose longitudinal direction is the Y direction to a wiring line W 101  whose longitudinal direction is also the Y direction. The information defines that formation of the notch  101   a  must be avoided.  
         [0033]     When a terminal P 102  and wiring line W 103  having different longitudinal directions are placed close to each other, the information defines that the distance between them must be an interval Y 1  larger than an interval defined by a general design rule.  
         [0034]     To the contrary, contents defined in information used in a routing method according to the first embodiment will be explained with reference to  FIG. 2 .  
         [0035]     For example, regions A 1  and A 3  on the side surface of the upper end portion of a terminal P 1  having a longitudinal direction in the Y direction correspond to wiring enable regions (hatched regions) where a wiring line can be connected in the X direction. A region A 2  on the end face of the upper end portion corresponds to a wiring enable region where a wiring line can be connected in the Y direction.  
         [0036]     Similarly, regions A 4  and A 6  on the side surface of the lower end portion correspond to wiring enable regions where a wiring line can be connected in the X direction. A region A 5  on the end face of the lower end portion corresponds to a wiring enable region where a wiring line can be connected in the Y direction.  
         [0037]     Assume that the regions A 1 , A 3 , A 4 , and A 6  each have a length Y 2 . The length Y 2  is equal to the width of wiring lines connected to the regions A 1 , A 3 , A 4 , and A 6 , and this avoids formation of a notch.  
         [0038]     A notch is formed at the upper or lower end when wiring lines are connected in the X direction to regions A 7  and A 8  defined at the center except the two end portions. Hence, the regions A 7  and A 8  correspond to wiring disable regions (dotted regions) where connection of a wiring line is disabled. In this case, assume that the regions A 7  and A 8  each have a length Y 3 .  
         [0039]     The range of the distance Y 1  from the upper end and the range of the distance Y 1  from the lower end correspond to wiring disable regions where a wiring line having a longitudinal direction in the X direction cannot exist.  
         [0040]     Consequently, for the terminal P 1  having a longitudinal direction in the Y direction, wiring enable regions where a wiring line can be connected in the X direction exist at a total of four portions at the upper and lower end portions, and wiring enable regions where a wiring line can be connected in the Y direction exist at a total of two portions on the upper and lower end faces. Similarly, for a terminal (not shown) having a longitudinal direction in the X direction, wiring enable regions where a wiring line can be connected in the Y direction exist at a total of four portions at the upper and lower end portions, and wiring enable regions where a wiring line can be connected in the X direction exist at a total of two portions on the upper and lower end faces.  
         [0041]     Information on wiring enable regions and wiring disable regions is created using X- and Y-coordinates for each terminal.  
         [0042]     An example of connecting a wiring line to a terminal on the basis of this information will be explained with reference to  FIG. 3 . A wiring line W 2  having a longitudinal direction in the X direction and a wiring width Y 2  is connected to the wiring enable region A 3  at the upper end portion of the terminal P 1  having a longitudinal direction in the Y direction so as not to form any notch. Connection of the wiring line W 2  is permitted.  
         [0043]     However, it is not permitted to connect a wiring line W 3  to the wiring disable region A 7  of a terminal P 2 .  
         [0044]     It is permitted to place a wiring line W 1  having a longitudinal direction in the X direction at the distance Y 2  apart equal to or larger than the distance Y 1  from the upper end of the terminal P 2 .  
         [0045]     It is not permitted to place a wiring line W 4  having a longitudinal direction in the X direction at a distance Y 12  closer than the distance Y 1  to the lower end of the terminal P 2 .  
         [0046]     A sequence from determination of the specifications of a semiconductor integrated circuit to fabrication of the semiconductor integrated circuit will be described with reference to the flowchart of  FIG. 4 .  
         [0047]     In step S 1 , the specifications of a chip (semiconductor integrated circuit) are determined.  
         [0048]     In step S 2 , a design is determined using the RTL language.  
         [0049]     In step S 3 , logical synthesis is performed on the basis of the created design.  
         [0050]     In step S 4 , net information which defines connection between elements such as a standard cell is created at the gate level on the basis of the created logical synthesis.  
         [0051]     In step S 5 , elements are placed on the chip.  
         [0052]     In step S 6 , the terminals of the placed elements are connected by wiring lines, and layout information is created.  
         [0053]     In step S 7 , the created layout information is output.  
         [0054]     In step S 8 , a chip is fabricated using the layout information.  
         [0055]     The semiconductor integrated circuit routing method according to the first embodiment is applied to the element placement process in step S 5  and the inter-terminal routing process in step S 6  in the above sequence. This sequence is shown in the flowchart of  FIG. 5 .  
         [0056]     A routing apparatus used to execute the routing method according to the first embodiment has an arrangement as shown in  FIG. 6 , i.e., an input unit  101 , arithmetic unit  102 , storage unit  103 , and output unit  104 . The routing apparatus is implemented by causing a computer to read routing software according to the first embodiment that is stored in a computer-readable recording medium, and execute the routing process.  
         [0057]     In step S 11 , net information  11  of the gate level and element information  12  on the outer shape of an element are input to the input unit  101 , sent to the storage unit  103  via the arithmetic unit  102 , and stored in the storage unit  103 .  
         [0058]     Further, wiring enable/disable information  13  representing that wiring connection to the terminal of each element is enabled or disabled is input to the input unit  101 , sent to the storage unit  103  via the arithmetic unit  102 , and stored in the storage unit  103 .  
         [0059]     The wiring enable/disable information  13  concerns wiring enable regions where wiring connection is enabled at two end portions of a terminal having a longitudinal direction in the X or Y direction, as shown in  FIG. 2 , wiring disable regions where wiring connection is disabled at a central portion except the two end portions, a wiring line different in longitudinal direction from the terminal, and a necessary interval from the end face of the terminal.  
         [0060]     If necessary, the arithmetic unit  102  reads out the net information  11  and element information  12  which are stored in the storage unit  103 , and executes a routing process for each element on the chip.  
         [0061]     In step  512 , the arithmetic unit  102  sets connection of a wiring line to a predetermined portion of the terminal of each element or placement of a wiring line.  
         [0062]     In step S 13 , the arithmetic unit  102  determines on the basis of the wiring enable/disable information  13  whether connection or placement of the wiring line is enabled.  
         [0063]     If connection or placement is disabled, the flow returns to step S 12  to set new connection or placement of the wiring line other than the current connection or placement of the wiring line.  
         [0064]     If connection or placement is enabled, the flow shifts to step S 14  to connect or place the wiring line.  
         [0065]     In step S 15 , it is determined whether routing between all terminals has ended. If NO in step S 15 , the flow returns to step S 12 ; if YES, shifts to step S 7  in  FIG. 4  to output created layout information.  
         [0066]     In this manner, in steps S 12  to S 14 , a target terminal is connected while a connectable region is searched for. When a wiring line runs through a region near the terminal, the wiring line is laid out while a runnable region is searched for. As a result, routing between terminals is executed.  
         [0067]      FIG. 7  shows an example of a description format which describes information on the outer shape of a terminal according to the comparative example.  
         [0068]     A part PC 1  surrounded by a dotted line defines that the outer shape of a terminal M 2  is rectangular, and also defines vertex information (0.90, 0.70, 1.10, 1.50) at four corners.  
         [0069]     The comparative example defines only vertex information of each rectangular terminal.  
         [0070]     To the contrary, the first embodiment adopts information represented by a part PC 2  surrounded by a dotted line in  FIG. 8 .  
         [0071]     Regions where connection of a wiring line having a longitudinal direction in the X direction to the terminal M 2  is permitted are set at the following four portions.  
         [0072]     (1) The range of Y-coordinates (0.70 to 0.90) at an X-coordinate (0.90)  
         [0073]     (2) The range of Y-coordinates (1.30 to 1.50) at an X-coordinate (0.90)  
         [0074]     (3) The range of Y-coordinates (0.70 to 0.90) at an X-coordinate (1.10)  
         [0075]     (4) The range of Y-coordinates (1.30 to 1.50) at an X-coordinate (1.10)  
         [0076]     Also, regions where connection of a wiring line having a longitudinal direction in the Y direction to the terminal M 2  is permitted are set at the following two portions.  
         [0077]     (1) The range of X-coordinates (0.90 to 1.10) at a Y-coordinate (0.70)  
         [0078]     (2) The range of Y-coordinates (0.90 to 1.10) at a Y-coordinate (1.50)  
         [0079]     A region where connection of a wiring layer located on an upper layer to the terminal M 2  is permitted is set at one portion given by vertex information (0.90, 0.70, 1.10, 1.50) at four corners.  
         [0080]     As described above, according to the first embodiment, information on a wiring enable region, a wiring disable region, and the interval between the end face of a terminal and a wiring line different in longitudinal direction from the terminal is set for each terminal in addition to information on the outer shape of the terminal. Using this information, routing between terminals is executed. This can implement a more flexible, more appropriate routing process, increase the process efficiency, and prevent an increase in circuit area.  
       (2) Second Embodiment  
       [0081]     The second embodiment of the present invention will be described below.  
         [0082]     When the longitudinal directions of wiring lines are different in placing the wiring lines, a so-called collision or interference phenomenon occurs. To avoid this phenomenon, the second embodiment performs routing in accordance with a sequence shown in the flowchart of  FIG. 9 . This routing process is applied to inter-terminal routing of step S 6  in the whole process shown in  FIG. 9 .  
         [0083]     A routing method according to the second embodiment can also employ the routing apparatus shown in  FIG. 6  in executing the routing process, similar to the first embodiment. The routing apparatus is implemented by causing a computer to read routing software according to the second embodiment that is stored in a computer-readable recording medium, and execute the routing process.  
         [0084]     In step S 21 , information on the longitudinal direction of a wiring line, i.e., the X or Y direction is set in an input unit  101  for each wiring line. The set information is stored in a storage unit  103 .  
         [0085]     A concrete example of defining a wiring line by defining the longitudinal direction of the wiring line will be explained with reference to  FIG. 10 . If a wiring line W 21  having two bent portions is defined using the coordinates of the outer shape, the data amount increases because the wiring line W 21  has eight vertexes.  
         [0086]     To the contrary, according to the second embodiment, the wiring line W 21  is defined by vectors V 1 , V 2 , and V 3  representing the longitudinal direction of the wiring line. That is, the wiring line W 21  is defined by the vector V 1  from a start point T 1  to an end point T 2 , the vector V 2  from a start point T 2  to an end point T 3 , and the vector V 3  from a start point T 3  to an end point T 4 .  
         [0087]     This definition can decrease the number of vertexes from eight to four, and reduce the data amount.  
         [0088]     In step S 22 , as shown in  FIG. 11 , another wiring line W 12  closest to an end portion W 11   a  of a wiring line W 11  is detected by an arithmetic unit  102  on the basis of information stored in the storage unit  103 .  
         [0089]     In step S 23 , the arithmetic unit  102  detects whether the longitudinal direction (X direction) of the wiring line W 11  that is represented by the vector is parallel or perpendicular to the longitudinal direction (Y direction) of the wiring line W 12  that is represented by the vector.  
         [0090]     If these longitudinal directions are parallel to each other in step S 24 , the flow ends; if they are perpendicular to each other, shifts to step S 25 . As shown in  FIG. 12 , the arithmetic unit  102  performs a process of connecting an extending portion W 13  to the end portion W 11   a  (end point of the vector) of the wiring line W 11  in a direction parallel to the wiring line W 12 , and then the flow ends.  
         [0091]     Accordingly, the second embodiment prevents the collision or interference phenomenon generated when wiring lines having different longitudinal directions run close to each other. The second embodiment can increase the routing efficiency, and suppress an increase in circuit area.  
       (3) Third Embodiment  
       [0092]     The third embodiment of the present invention will be explained below.  
         [0093]     The third embodiment uses information which defines the signal transfer direction of each wiring line by using the vector.  
         [0094]     For example, as shown in  FIG. 13 , of three wiring lines W 31  to W 33  placed parallel to each other, the wiring lines W 31  and W 32  transfer signals to the left in  FIG. 13 , and are represented by vectors V 11  and V 12 . The wiring line W 33  transfers a signal to the right in  FIG. 13 , and is represented by a vector V 13 .  
         [0095]     When signals are transferred in the same direction, like the wiring lines W 31  and W 32 , timings when signals are transferred are often considered to be the same.  
         [0096]     As shown in  FIG. 14 , the wiring line W 31  has resistances R 1  and R 2 , and the wiring line W 32  has resistances R 3  and R 4 . A parasitic resistance C 1  exists between the wiring lines W 31  and W 32 .  
         [0097]     For this reason, the wiring lines W 31  and W 32  are preferably placed at a predetermined interval equal to or larger than a minimum interval defined by the design rule so as to prevent noise generated by interference between signals.  
         [0098]     In  FIG. 14 , the wiring line W 32  has the resistances R 3  and R 4 , and the wiring line W 33  has resistances R 5  and R 6 . A parasitic resistance C 2  exists between the wiring lines W 32  and W 33 .  
         [0099]     However, the mutual influence of signals is considered to be small because the wiring lines W 32  and W 33  transfer signals in different directions and timings when the signals are transferred are different. The interval between the wiring lines W 32  and W 33 , therefore, suffices to satisfy at least a minimum interval defined by the design rule.  
         [0100]     The sequence of a process by a routing method according to the third embodiment will be explained with reference to  FIG. 15 .  
         [0101]     The routing method according to the third embodiment can also adopt the routing apparatus shown in  FIG. 6  in executing the routing process, similar to the first and second embodiments. The routing apparatus is implemented by causing a computer to read routing software according to the third embodiment that is stored in a computer-readable recording medium, and execute the routing process.  
         [0102]     In step S 31 , a signal transfer direction is set by the vector in an input unit  101  for each wiring line. The set information is stored in a storage unit  103 .  
         [0103]     In step S 32 , an arithmetic unit  102  determines whether the transfer directions of two adjacent signal lines out of signal lines placed parallel to each other coincide with each other.  
         [0104]     If the transfer directions of the two signal lines coincide with each other, signals may interfere with each other, so the arithmetic unit  102  places in step S 33  the signal lines at a predetermined interval equal to or larger than a minimum interval defined by the design rule. If the transfer directions of the two signal lines are different from each other, the mutual influence of signals is considered to be small, so the arithmetic unit  102  places the signal lines in accordance with the design rule in step S 34 .  
         [0105]     The third embodiment executes routing by using information which defines a signal transfer direction by the vector, and can perform the routing process in consideration of mutual interference between signals without consuming a wasteful area.  
         [0106]     As has been described above, the semiconductor integrated circuit routing method according to the third embodiment and the recording medium which stores routing software can increase the routing efficiency.  
         [0107]     The above-described embodiments are merely examples and do not limit the present invention. The present invention can be variously modified within the technical scope of the invention.