Abstract:
A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a divisional application of U.S. patent application Ser. No. 11/160,449, filed Jun. 24, 2005, which claims priority from U.S. provisional application No. 60/521,892 by Yang et al., filed Jul. 18, 2004, entitled “Method for integrating dual metal gate electrodes with high dielectric constant material,” the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates generally to the field of semiconductor fabrication. More particularly, this invention relates to a metal-gate complementary metal-oxide-semiconductor (CMOS) device and fabrication method of making same.  
         [0004]     2. Description of the Prior Art  
         [0005]     The continued scaling of CMOS devices into sub-70 nm technology will rely on a fundamental change in transistor gate stack materials. Over the past few years, research in this area has focused on identifying candidate materials to replace poly-silicon and SiO2 as the gate electrode and gate dielectric, respectively. Critical requirements for novel gate electrode materials include thermal stability with the gate dielectric and suitable values for the interfacial work function (˜4.0 eV and ˜5.0 eV for bulk-Si NMOS and PMOS devices respectively). The latter requirement of obtaining complementary gate work functions on a single wafer is being perceived as a major process integration challenge.  
         [0006]     Metal-gate electrodes bring about several advantages compared to traditional polysilicon gates as CMOS technology continues to scale beyond the 100 nm node. These include reduction in poly-depletion effect, reduction in sheet resistance, and potentially better thermal stability on high-K gate dielectrics. The main challenge is that, unlike with polysilicon, one would have to use two metallic materials (bi-layer metal) with different work functions in order to achieve the right threshold voltages for both NMOS and PMOS. A straightforward way to implement dual metal CMOS is to etch away the first metal from either NMOS or PMOS side, and then deposit a second metal with a different work function.  
         [0007]     Unfortunately, this would entail exposing the gate dielectric to the metal etchant, leading to undesirable dielectric thinning and likely reliability problems. Further, the prior art methods of making metal-gate CMOS devices are complex and have process integration issues.  
       SUMMARY OF THE INVENTION  
       [0008]     It is a primary object of the claimed invention to provide a semiconductor manufacturing method that is able to eliminate the above-mentioned problems.  
         [0009]     The invention achieves the above-identified and other objects by providing a method of fabricating a metal-gate complementary metal-oxide-semiconductor (CMOS) device. A semiconductor substrate having a first region and a second region is provided. A first dielectric layer is then deposited over the semiconductor substrate. A first metal layer is formed over the first dielectric layer. A capping layer is deposited over the first metal layer. The first region is masked while exposing the second region. The capping layer, the first metal layer and the first dielectric layer are etched away from the second region. A second dielectric layer is then deposited over the semiconductor substrate. The second dielectric layer covers the capping layer. A second metal layer is formed over the second dielectric layer. The second region is masked while exposing the first region. The second metal layer, the second dielectric layer and the capping layer are etched away from the first region. A conductive layer is deposited on the first metal layer and on the second metal layer. Lithographic and etching processes are performed to form a first gate stack comprising the first dielectric layer, the first metal layer and the conductive layer within the first region, and a second gate stack comprising the second dielectric layer, the second metal layer and the conductive layer within the second region.  
         [0010]     From one aspect of this invention, a metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device comprises a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor comprises a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor comprises a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.  
         [0011]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:  
         [0013]      FIG. 1  is a cross-sectional view of a metal-gate CMOS device according to the preferred embodiment of this invention; and  
         [0014]      FIG. 2  to  FIG. 7  are schematic diagrams showing a method of forming a metal-gate CMOS device according to the preferred embodiment of this invention. 
     
    
     DETAILED DESCRIPTION  
       [0015]     Please refer to  FIG. 1 .  FIG. 1  is a cross-sectional view of a metal-gate CMOS device  100  according to the preferred embodiment of this invention. As shown in  FIG. 1 , the metal-gate CMOS device  100  comprises a PMOS transistor  101  and an NMOS transistor  102  coupled to the PMOS transistor  101 . The PMOS transistor  101  and the NMOS transistor  102  are formed on a N-type substrate (N-well)  10   a  and a P-type substrate (P-well)  10   b , respectively. The PMOS transistor  101  comprises a gate stack  201  and the NMOS transistor  102  comprises a gate stack  202 .  
         [0016]     The gate stack  201  of the PMOS transistor  101  consists of a dielectric layer  212 , a single-layer metal  214  directly stacked on the dielectric layer  212 , and a conductive capping layer  216  directly stacked on the single-layer metal  214 . The gate stack  202  of the NMOS transistor  102  consists of dielectric layer  222 , a single-layer metal  224  directly stacked on the dielectric layer  222 , and a conductive capping layer  226  directly stacked on the single-layer metal  214 . The single-layer metal  214  has a first work function tuned for the PMOS, while the single-layer metal  224  has a second work function tuned for the NMOS. For the sake of simplicity, some devices such as shallow trench isolation or diffusion source/drain are not explicitly shown in this and following figures.  
         [0017]     The single-layer metal  214  is a layer of single metal material having a work function of about 4 eV. For example, the single-layer metal  214  may be composed of amorphous TaN x  or TiN. The thickness of the single-layer metal  214  is less than 500 angstroms, preferably less than 400 angstroms. The single-layer metal  224  is a layer of single metal material having a higher work function of about 5 eV. For example, the single-layer metal  224  may be composed of TaRu alloys such as TaRu x N y  (x=1.2˜1.3,y=0.4˜0.6). The thickness of the single-layer metal  224  is less than 500 angstroms, preferably less than 400 angstroms.  
         [0018]     According to the preferred embodiment of this invention, the dielectric layer  12  is composed of materials having a relatively higher dielectric constant than that of silicon dioxide. For example, the dielectric layer  12  may be composed of ZrO 2 , HfO 2 , Zr silicates, Hf silicates, or Al doped Zr silicates. Preferably, the dielectric layer  12  is composed of ZrO 2 , HfO2, (ZrO 2 ) x (SiO 2 ) y , (HfO 2 ) x (SiO 2 ) y  or (ZrO 2 )(Al 2 O 3 ) x (SiO 2 ) y .  
         [0019]     The conductive capping layer  216  that is directly stacked on the single-layer metal  214  may comprise polysilicon, doped polysilicon, tungsten and silicide. The conductive capping layer  226  that is directly stacked on the single-layer metal  224  may comprise polysilicon, doped polysilicon and silicide. The thickness of the conductive capping layers  216  and  226  ranges from 2000 angstroms to 6000 angstroms.  
         [0020]     Please refer to  FIG. 2  to  FIG. 7 .  FIG. 2  to  FIG. 7  are schematic diagrams showing an exemplary method of forming a metal-gate CMOS device according to this invention. First, as shown in  FIG. 2 , a semiconductor substrate  10  is provided. On the substrate  10  there are provided an N-well  10   a  and a P-well  10   b  within a PMOS region  301  and a NMOS region  302  respectively. Generally, shallow trench isolation (STI) regions or field oxide regions and active regions are previously defined on the substrate  10 , but are not shown in the figures for the sake of simplicity.  
         [0021]     Typically, the surface of the substrate  10  is washed by using HF solution with a concentration of 100:1 (H2O: HF) in volume. Thereafter, a conventional nitridation process is carried out by using RTP methods. Details of these surface pre-treatment steps are known in the art and are therefore omitted. After the above-mentioned surface pre-treatment steps, a high-K dielectric layer  12  is deposited onto the surface of the semiconductor substrate  10  in the PMOS region  301  and NMOS region  302 . According to the preferred embodiment of this invention, the high-K dielectric layer  12  is composed of materials having a high dielectric constant. For example, the dielectric layer  12  may be composed of ZrO2, HfO2, Zr silicates, Hf silicates, or Al doped Zr silicates. Preferably, the dielectric layer  12  is composed of ZrO 2 , HfO 2 , (ZrO 2 ) x SiO 2 ) y , (HfO 2 ) x (SiO 2 ) y  or (ZrO 2 )(Al 2 O 3 ) x (SiO 2 ) y .  
         [0022]     After the deposition of the high-K dielectric layer  12 , a layer of metal material  14  having a first work function tuned for the PMOS is formed on the high-K dielectric layer  12 . For example, the metal material layer  14  may comprise amorphous TaN x  or TiN. Preferably, the metal material layer  14  has a thickness of about 100-300 angstroms. Subsequently, a silicon nitride cap layer  16  is formed on the metal material layer  14 .  
         [0023]     As shown in  FIG. 3 , the PMOS region  301  is masked by a photoresist layer  20 , while the NMOS region  302  is exposed. The silicon nitride cap layer  16 , the metal material layer  14  and the high-K dielectric layer  12  within the exposed NMOS region  302  are etched away. The photoresist layer  20  is then stripped.  
         [0024]     As shown in  FIG. 4 , another high-K dielectric layer  22  is deposited over the semiconductor substrate  10 . The high-K dielectric layer  22 , which covers the silicon nitride cap layer  16  within the PMOS region  301  and covers the semiconductor substrate within the NMOS region  302 , may comprise ZrO 2 , HfO 2 , Zr silicates, Hf silicates, or Al doped Zr silicates. Preferably, the dielectric layer  12  is composed of ZrO 2 , HfO 2 , (ZrO 2 ) x (SiO 2 ) y , (HfO 2 ) x (SiO 2 ) y  or (ZrO 2 )(Al 2 O 3 ) x (SiO 2 ) y . After the deposition of the high-K dielectric layer  22 , another layer of metal material  24  having a second work function tuned for the NMOS is formed on the high-K dielectric layer  22 . For example, the metal material layer  24  may comprise TaRu alloys such as TaRu x N y  (x=1.2˜1.3,y=0.4˜0.6) or PVD deposited TaN. Preferably, the metal material layer  24  has a thickness of about 100-300 angstroms.  
         [0025]     As shown in  FIG. 5 , the NMOS region  302  is masked by a photoresist layer  30 , while the PMOS region  301  is now exposed. The metal material layer  24 , the high-K dielectric layer  22  and the silicon nitride cap layer  16  within the exposed PMOS region  301  is then etched away using methods known in the art. For example, the silicon nitride cap layer  16  may be etched away using wet etchant such as heated phosphoric acid solution. The photoresist layer  30  is then stripped.  
         [0026]     As shown in  FIG. 6 , a chemical vapor deposition (CVD) process is performed to deposit a doped polysilicon layer  40  over the semiconductor substrate  10 . The doped polysilicon layer  40  covers regions  301  and  302 . Preferably, the doped polysilicon layer  40  has a thickness of about 2000 angstroms to 6000 angstroms, but not limited thereto. Optionally, a silicide process or self-aligned silicide process may be carried out to convert an upper portion of the doped polysilicon layer  40  into a silicide layer. Alternatively, the salicide process may be performed at a later stage. For example, the salicide process may be carried out simultaneously with the source/drain salicide process.  
         [0027]     As shown in  FIG. 7 , a lithographic process and a dry etching process are performed to form gate stack  201  and gate stack  202 . The gate stack  201  of the PMOS transistor  101  consists of a dielectric layer  212 , a single-layer metal  214  directly stacked on the dielectric layer  212 , and a conductive capping layer  216  directly stacked on the single-layer metal  214 . The gate stack  202  of the NMOS transistor  102  consists of dielectric layer  222 , a single-layer metal  224  directly stacked on the dielectric layer  222 , and a conductive capping layer  226  directly stacked on the single-layer metal  214 . To complete the PMOS transistor  101  and the NMOS transistor  102 , gate sidewall spacers (not shown) are formed and source/drain regions (not shown) are implanted into the substrate.  
         [0028]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.