Abstract:
In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Description:
[0001]    This application is a continuation of U.S. patent application Ser. No. 12/841,889, filed Jul. 22, 2010, which is a continuation of U.S. patent application Ser. No. 12/080,076, filed Mar. 31, 2008, now U.S. Pat. No. 7,783,819, the content of which is hereby incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    Certain semiconductor architectures such as advanced extensible interface (AXI) and open core protocol (OCP)-based architectures are modular and allow for rapid proliferation by quickly adding or deleting intellectual property (IP) blocks from an existing design. The key elements that make this possible are an interconnect fabric that can be automatically generated for a given configuration, and a large ecosystem of IP blocks that all implement the same standard interface and can be seamlessly plugged into these fabrics. 
         [0003]    Though these IP blocks (also referred to as IPs) offer a rich set of functionality, they cannot be used in a personal computer (PC) system, as they lack some key features required for peripheral component interconnect (PCI) compatibility. For example, these IPs operate at fixed addresses, precluding plug-and-play; there is no mechanism for discovery and enumeration; PCI-style ordering is not implemented; and PCI-style power management features are missing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a block diagram of a processor in accordance with one embodiment of the present invention. 
           [0005]      FIG. 2  is a block diagram of a system in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0006]    Embodiments use a technique that enables use of heterogeneous resources, such as AXI/OCP technologies, in a PC-based system such as a PCI-based system without making any changes to the IP resources themselves. Embodiments provide two very thin hardware blocks, referred to herein as a Yunit and a shim, that can be used to plug AXI/OCP IP into an auto-generated interconnect fabric to create PCI-compatible systems. As will be described below, in one embodiment a first (e.g., a north) interface of the Yunit connects to an adapter block that interfaces to a PCI-compatible bus such as a direct media interface (DMI) bus, a PCI bus, or a Peripheral Component Interconnect Express (PCIe) bus. A second (e.g., south) interface connects directly to a non-PC interconnect, such as an AXI/OCP interconnect. In various implementations, this bus may be an OCP bus. 
         [0007]    The Yunit implements PCI enumeration by translating PCI configuration cycles into transactions that the target IP can understand. This unit also performs address translation from re-locatable PCI addresses into fixed AXI/OCP addresses and vice versa. The Yunit may further implement an ordering mechanism to satisfy a producer-consumer model (e.g., a PCI producer-consumer model). 
         [0008]    In turn, individual IPs are connected to the interconnect via dedicated PCI shims. Each shim may implement the entire PCI header for the corresponding IP. The Yunit routes all accesses to the PCI header and the device memory space to the shim. The shim consumes all header read/write transactions and passes on other transactions to the IP. In some embodiments, the shim also implements all power management related features for the IP. 
         [0009]    Referring now to  FIG. 1 , shown is a block diagram of a processor in accordance with one embodiment of the present invention. As shown in  FIG. 1 , processor  10  may be a system on a chip (SoC) or other integrated circuit that can be formed on a single semiconductor die. In the embodiment of  FIG. 1 , processor  10  may include various heterogeneous resources that can be coupled to an interface to provide the ability to communicate and control these various heterogeneous resources using standard PC signaling mechanisms, such as a PCI protocol, although the scope of the present invention is not limited in this regard. 
         [0010]    As shown in  FIG. 1 , processor  10  may include an adapter  20  which, in one embodiment may be a DMI adapter having a first interface that can communicate according to a given protocol, e.g., a DMI protocol. However in other implementations adapter  20  may communicate using this first interface according to a PCI, PCIe or other such PC-based communication protocol. Accordingly, communications with an upstream component, which may be another part of the SoC, or a different component such as a chipset component of a PC, e.g., an input/output controller hub (ICH) may occur according to the given PC protocol, e.g., the DMI protocol shown in  FIG. 1 . 
         [0011]    In turn, downstream communications can occur according to a non-PC communication protocol such as the OCP protocol shown in  FIG. 1 , although other implementations are certainly possible. 
         [0012]    Adapter  20  communicates with a Yunit  30 , which as described above may handle various PCI or other such PC-based operations. On its downstream side Yunit  30  may be coupled to an interconnect  40 , which may provide interconnection and routing of communications between Yunit  30  and a plurality of different heterogeneous resources. In the embodiment shown in  FIG. 1 , such resources include a first resource  50 , a second resource  60 , and a third resource  70 , each of which may represent a given heterogeneous resource such as a given IP block of one or more third parties. Each heterogeneous resource may be configured differently to perform one or more specialized functions. 
         [0013]    Still referring to  FIG. 1 , interconnect  40  may be coupled to each resource via an interconnect, e.g., an OCP interconnect. Each resource includes a shim to connect the resource to interconnect  40 . The shims may be used to perform all PCI-related operations, such that communication between the shim and the respective IP block of the resource can be by the underlying protocol of the IP block. Thus as shown in  FIG. 1 , resource  50  includes a shim  55  coupled to an IP block  58  by an interconnect such as an OCP-based interconnect. Similarly, resource  60  includes a shim  65  coupled to an IP block  68  by a OCP interconnect. Also shown in  FIG. 1  is a resource  70  that includes a shim  75  coupled to an IP block  78  by an OCP interconnect. While shown with this particular implementation in the embodiment of  FIG. 1 , the scope of the present invention is not limited in this regard. 
         [0014]    Thus, rather than being a monolithic compatibility block, embodiments that implement a Yunit take a distributed approach. Functionality that is common across all IPs, e.g., address translation and ordering, is implemented in the Yunit, while IP-specific functionality such as power management, error handling, and so forth, is implemented in the shims that are tailored to that IP. 
         [0015]    In this way, a new IP can be added with minimal changes to the Yunit. For example, in one implementation the changes may occur by adding a new entry in an address redirection table. While the shims are IP-specific, in some implementations a large amount of the functionality (e.g., more than 90%) is common across all IPs. This enables a rapid reconfiguration of an existing shim for a new IP. 
         [0016]    Embodiments thus also enable use of auto-generated interconnect fabrics without modification. In a point-to-point bus architecture, designing interconnect fabrics can be a challenging task. The Yunit approach described above leverages an industry ecosystem into a PCI system with minimal effort and without requiring any modifications to industry-standard tools. 
         [0017]      FIG. 2  is a block diagram of a system in accordance with one embodiment of the present invention. System  100  may be a PC-based system, such as a PCI-based system that can be implemented in different form factors, from a desktop system to a laptop to an ultra-mobile PC. As shown in  FIG. 2 , system  100  includes a processor  105  coupled to a host interface  110 , which in turn is coupled to a memory  115 , such as a dynamic random access memory (DRAM), and in turn to DMI adapter  120 , e.g., via a DMI bus. Processor  105  may be, in some embodiments, a low power processor that can execute a PC-based operating system (OS) such as a WINDOWS™ or LINUX™ OS that uses a PCI or other such PC protocol, although certain components of the system may be of another protocol, e.g., AXI or OCP. 
         [0018]    Adapter  120  communicates with a Yunit  130 , which as described above may handle various PCI or other such PC-based operations. On its downstream side Yunit  130  may be coupled to an interconnect  140  to provide interconnection and routing of communications between Yunit  130  and different heterogeneous resources. In the embodiment shown in  FIG. 2 , such resources include a first resource  150 , a second resource  160 , and a third resource  170 , each of which may represent a given heterogeneous resource such as a given IP block of one or more third parties. 
         [0019]    Still referring to  FIG. 2 , interconnect  140  may be coupled to each resource via an OCP interconnect. Each resource includes a shim to connect the resource to interconnect  140 . The shims may be used to perform all PCI-related operations, such that communication between the shim and the respective IP block of the resource can be by the underlying protocol of the IP block. Thus as shown in  FIG. 2 , resource  150  includes a shim  155  coupled to an IP block  158  by an OCP-based interconnect. Similarly, resource  160  includes a shim  165  coupled to an IP block  168  by an OCP interconnect. Also shown in  FIG. 2  is a resource  170  that includes a shim  175  coupled to an IP block  178  by an OCP interconnect. While shown with this particular implementation in the embodiment of  FIG. 2 , the scope of the present invention is not limited in this regard. 
         [0020]    Embodiments may be implemented in code and may be stored on a storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions. 
         [0021]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.