Abstract:
This is a method of manufacturing a DRAM cell of a highly integrated semiconductor device increased in the capacity of its capacitor as several cylinder-shaped storage electrodes with first and second polysilicon layers are formed. In order to form several cylinder-shaped electrodes, a polysilicon layer of hemisphere grain structures is used as a mask during the etching process.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a method of manufacturing a highly integrated semiconductor device, and more particularly to a method of manufacturing a Dynamic Random Access Memory(DRAM) cell of a highly integrated semiconductor device with the surface area increased by forming several cylinder-shaped storage electrodes through an etching process employing a polysilicon layer of hemisphere grain structures as a mask. 
     2. Information Disclosure Statement 
     Following the conventional manufacturing method of a highly integrated semiconductor device, since a semiconductor device is structurally reduced in the capacity of its capacitor due to high integration, it is absolutely necessary to realize a capacitor having a sufficiently large capacity even if the size of its memory cells is made small. 
     However, the disadvantages of the conventional method are that the surface area of the storage electrode is reduced as the size of the cells is decreased. Therefore, it is difficult to manufacture a DRAM cell of a highly integrated semiconductor device with a sufficiently large capacity of its capacitor. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a method of manufacturing a highly integrated semiconductor device self-aligning a contact region of the storage electrode on a silicon substrate and forming several cylinder-shaped storage electrodes in order to increase the capacity of capacitors. 
     To achieve the above mentioned objective, a field oxide layer is formed on the predetermined part of a silicon substrate and a word line, mask oxide layer, and spacer oxide layer are formed on the silicon substrate and field oxide layer. Thereafter, a first polysilicon layer is deposited and a photoresist pattern with the shape of a window is formed. 
     After forming an oxide layer over the entire surface, the oxide layer is etched through the etchback process until the photoresist pattern is exposed and then, the photoresist pattern is removed so that a cylinder-shaped oxide layer is formed. 
     Thereafter, a polysilicon layer of hemisphere grain structures is formed on the surface of the cylinder-shaped oxide layer and first polysilicon layer, and several cylinder-shaped oxide patterns are formed by etching the exposed part of the cylinder-shaped oxide layer through the etching process employing the polysilicon layer of the hemisphere grain structures as a mask and removing the polysilicon layer of the hemisphere grain structures. 
     Finally, a second polysilicon layer is deposited on the cylinder-shaped oxide patterns and the exposed surface of the first polysilicon layer and the first and second polysilicon layers are etched through the etching process using a mask for forming storage electrodes so that the several cylinder-shaped storage electrodes having the first and second polysilicon layers are formed. 
     Accordingly, several cylinder-shaped storage electrodes with the large surface area can be formed by using the manufacturing method of a highly integrated semiconductor device according to the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1a through FIG. 1f are cross-sectional views illustrating a manufacturing process of a DRAM cell of a highly integrated semiconductor device according to the first embodiment of the present invention. 
     FIG. 2a through FIG. 2b are cross-sectional views illustrating a manufacturing process of a DRAM cell of a highly integrated semiconductor device according to the second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The embodiments of the present invention will be explained in detail by referring to the accompanying drawings. 
     FIG. 1a through 1f are cross-sectional views that illustrate a manufacturing process of a DRAM cell of a highly integrated semiconductor device according to the first embodiment of the present invention. 
     As shown in FIG. 1a, a field oxide layer 3 is formed on the predetermined part of silicon substrate 1 and a word line 5, a mask oxide layer 7, and a spacer oxide layer 9 are formed on the silicon substrate 1 and field oxide layer 3. Thereafter, a first polysilicon layer 11 is deposited and a first photoresist pattern 13 with the shape of a window is formed. 
     FIG. 1b is a cross-sectional view illustrating the formation of an oxide layer 15, comprising a Spin On Glass (SOG) layer or a Plasma Enhanced Chemical Vapor Deposition (PECVD) layer formed at low temperature. As shown in FIG. 1b, an oxide layer 15 is formed over the entire surface and the oxide layer 15 is etched through the etchback process until the photoresist pattern 13 is exposed. 
     FIG. 1c is a cross-sectional view illustrating the cylinder-shaped oxide layer 15 formed by removing the photoresist pattern 13 after completing the process mentioned in FIG. 1b. 
     FIG. 1d is a cross-sectional view illustrating a polysilicon layer 17 of hemisphere grain structures on the surface of the cylinder-shaped oxide layer 15 and first polysilicon layer 11 using the well-known manufacturing method. 
     FIG. 1e is a cross-sectional view that illustrates several cylinder-shaped oxide patterns 19 formed by etching the exposed part of the oxide layer 15 through the etching process employing the polysilicon layer 17 of the hemisphere grain structures as a mask and removing the remaining polysilicon layer 17 of the hemisphere grain structures. As shown in FIG. 1e, since the oxide layer 15, on which the polysilicon layer 17 of the hemisphere grain structures is not formed, is exposed, the exposed oxide layer is etched through the etching process. However, the oxide layer 15 on which the polysilicon layer 17 of the hemisphere grain structures is formed is not etched because the polysilicon layer 17 of the hemisphere grain structures prevents the oxide layer 15 from being etched through the etching process in case the etch ratio of the polysilicon layer to the oxide layer is more than 20:1. Therefore, several cylinder-shaped oxide patterns 19 are formed. 
     FIG. 1f is a cross-sectional view illustrating the formation of storage electrodes after depositing a second polysilicon layer used for the storage electrode. As shown in FIG. 1f, a second polysilicon 21 is deposited on the cylinder-shaped oxide patterns and exposed surface of the first polysilicon layer, and the first polysilicon layer 11 and second polysilicon layer 21 are etched by the etching process using a mask for forming the storage electrodes so that the storage electrodes 30 having the first polysilicon layer 11 and second polysilicon layer 21, are formed. 
     FIG. 2a and FIG. 2b are cross-sectional views that illustrate a manufacturing process of a DRAM cell of a highly integrated semiconductor device according to the second embodiment of the present invention. In the second embodiment, the manufacturing process shown in FIG. 1a through FIG. 1e is carried out in the same manner as the first embodiment of the present invention. 
     As shown in FIG. 2a, after completing the processes described in FIG. 1e, a second polysilicon layer 21 is deposited on the cylinder-shaped oxide patterns 19 and first polysilicon layer 11, and a photoresist layer 25 is coated on the second polysilicon layer 21. Thereafter, the photoresist layer 25 is etched out by the etchback process until the second polysilicon layer 21 is exposed and then, the exposed second polysilicon layer 21 formed on top of the cylinder-shaped oxide patterns is etched out. 
     FIG. 2b is a cross-sectional view that illustrates the formation of storage electrodes 35 having the first polysilicon layer 11 and second polysilicon layer 21. As shown in FIG. 2b, the remaining photoresist layer 25 is removed and the cylinder-shaped oxide patterns 19 are etched out. Thereafter, the first polysilicon layer 11 and second polysilicon layer 21 are etched out by the etching process using a mask for forming the storage electrode so that the storage electrodes 35 having the first polysilicon layer 11 and second polysilicon layer 21 are formed. In such case, the surface area of the storage electrodes 35 formed according to the second embodiment of the present invention is larger than that of the storage electrodes 30 formed according to the first embodiment of the present invention. 
     While the invention has been described with respect to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in detail may be made therein without departing from the spirit, scope and teaching of the invention.