Abstract:
A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. application Ser. No. 12/965,192, filed on Dec. 10, 2010, the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present disclosure relates to interconnect structures used in packaged microelectronic assemblies. In particular it relates to interconnect structures used in the connection of microelectronic chips and dies to substrates, such as in flip-chip bonding, or between substrates, such as in the formation of stacked packages. The structures described herein can be used to reduce failure of interconnect bonds due to void formation caused by electromigration between components of prior structures. 
         [0003]    Electromigration is a main cause of interconnect failure, especially in high-performance devices where the current density in the interconnect and the device operating temperatures are high. In general, electromigration is caused by the different diffusion rates of materials used in interconnect assemblies. For example, an interconnect assembly can include a contact pad made of copper formed on each of two substrates and a solder mass bonded between the contact pads. The solder mechanically secures the two contact pads, and thus, the substrates on which they are formed, and also electronically connects the two pads so that a signal carried by an electric current can pass between the two pads through the solder mass. In this example, the diffusion rates between the solder and the copper of the pads can be different. The diffusion rates are the rates of molecular movement within the metallic structures over time, and in particular, when subjected to a current or to the heat caused by operation of the devices. 
         [0004]    Voids formed in interconnect structures can decrease the reliability of the microelectronic assemblies in which they are used. Further, the presence of voids increases the current density within the materials in the areas surrounding the voids. This can, in turn, further exacerbate the difference in diffusion rate, leading to acceleration of void formation, leading eventually, to both electrical and mechanical failure of the interconnect element. 
         [0005]    Present means of decreasing electromigration include using barrier metals or dopants in the solder. These means, however, present their own reliability issues and can lead to cost increases that outweigh their effectiveness. Accordingly, further means for reducing electromigration are needed. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    An embodiment of the present invention relates to a microelectronic assembly. The microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection such that the first surface of the first face is oriented toward the second surface. The first mass extends along an edge of the first projection towards the first dielectric material layer. In a further embodiment, the first fusible metal mass can contact the first dielectric material layer. 
         [0007]    The microelectronic assembly can be configured such that the first surface is formed on a substrate and the second surface is formed on a microelectronic element. Additionally or alternatively, the first surface can be formed on a substrate further having a microelectronic element affixed thereon, and the second surface can be formed on a second substrate. In a further embodiment, the microelectronic assembly includes a plurality of interconnect structures each including a first conductive element, a first conductive projections, a second conductive projection, and a first metal mass. Each interconnect structure is connected between the first region of the first face and the second face and has a structure similar to that described above wherein the first dielectric material layer covers the second regions of the thin elements. 
         [0008]    The first opening in the first dielectric material layer can define an inside surface such that the inside surface extends along a portion of the first projection in substantial contact therewith. Accordingly, the first dielectric material layer can have a thickness extending in a direction perpendicular to the first face of the first thin element. The thickness can be about 20% to 50% of a height of the first conductive projection. 
         [0009]    The base of the first conductive projection can have a periphery such that the second region of the first face is exposed outside of the periphery of the base of the first projection. This arrangement can further form a corner between the first face of the first thin element and the side wall of the first conductive element. The corner can be located along the outer periphery of the base of the first conductive element, and the first dielectric material layer can substantially cover the corner. 
         [0010]    In a further embodiment, a second thin conductive element can be exposed on the second surface and can have a second face consisting of first and second regions. The second projection can further have a base that is connected to and covers the first region of the second thin element and defines a periphery and an end portion remote from the base. A second dielectric material layer can cover the second region of the second thin element. Further, the first mass can extend over a portion of the second conductive projection toward the second dielectric material layer. 
         [0011]    A further embodiment of the present invention relates to a microelectronic assembly that includes a first surface and a first thin conductive element that is exposed on the first surface and has a face consisting of first and second regions. A first conductive projection is connected to and covers the first region of the first face and extends to an end remote therefrom. The conductive projection has a barrier formed along a portion thereof that has a first edge remote from the first thin conductive element. The assembly further includes a second face having a second conductive projection extending away therefrom. A first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier, the barrier being disposed between the first thin element and the first metal mass. The barrier can be a surface-treatment layer formed in the first conductive projection. The surface-treatment layer can be formed by oxidation or can be a coating applied on a surface of the first conductive projection. 
         [0012]    In a still further embodiment, the microelectronic assembly includes a first substrate having a first surface and a first thin conductive element exposed on the first surface and having a first face. A first conductive projection having a base connected to the first face extends to an end remote from the first face and defines a side wall between the base and the end. A dielectric material layer extends along the first surface of the first substrate and has a second surface and a third surface remote from the second surface. The dielectric material layer further has a first opening defining a periphery formed therein. A metal plating layer having a first portion extends along the end and at least a portion of the side wall of the first conductive projection. A second portion of the metal plating layer extends outwardly along a portion of the dielectric material layer and away from the first conductive projection. A first solder mass is formed over at least the first portion of the plating layer and extends toward the third surface. 
         [0013]    A still further embodiment relates to microelectronic assembly including a substrate having a first surface, a plurality of first conductive pads exposed on the first surface and defining a face, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to a respective one of the first conductive pads. Each metal post extends along a side wall from the base to ends remote from the first conductive pad. The assembly further includes a dielectric material layer having an inner surface, an outer surface, and a plurality of openings. The inner surface extends along the first surface of the substrate, the outer surface being remote from the substrate. Respective ones of the first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries of the first metal posts. A plurality of fusible metal masses contact the ends of at least some of first metal posts and extend along side walls of the first metal posts towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically connected to at least some of the first conductive pads. 
         [0014]    A still further embodiment relates to a microelectronic assembly including a first substrate having a first surface and a first thin conductive element having a first face and being exposed on the first surface. A first conductive projection having a base is connected to the first face and extends to an end remote from the first face. A side wall is defined between the base and the end. The assembly further includes a dielectric material layer having a second surface and a third surface remote from the second surface. The second surface extends along the first surface of the first substrate, and the dielectric material layer has a first opening with a periphery formed therein. A first solder mass is formed on the first conductive projection that extends along the end and a portion of the side wall to a location disposed between the base and the end. The first conductive projection extends through the first opening such that the periphery thereof contacts a portion of the side wall. The solder mass extends towards the third surface of the dielectric material layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  shows a stacked assembly of packaged microelectronic elements including an interconnect structure according to an embodiment of the present invention; 
           [0016]      FIG. 2  shows a stacked assembly of packaged microelectronic elements including an interconnect structure according to another embodiment of the present invention; 
           [0017]      FIG. 3  shows a chart illustrating characteristics of an interconnect structure according to the embodiment of  FIG. 1  under a first condition; 
           [0018]      FIG. 4  shows a chart illustrating characteristics of an interconnect structure according to the embodiment of  FIG. 1  under a second condition; 
           [0019]      FIG. 5  shows a chart illustrating characteristics of a prior-art interconnect structure under a first condition; 
           [0020]      FIG. 6  shows a chart illustrating characteristics of the prior-art interconnect structure of  FIG. 5  under a second condition; 
           [0021]      FIG. 7  shows a component of an interconnect structure according to an alternative embodiment; 
           [0022]      FIG. 8  shows a component of an interconnect structure according to a further alternative embodiment; 
           [0023]      FIG. 9  shows a component of an interconnect structure according to an alternative embodiment; 
           [0024]      FIG. 10  shows a component of an interconnect structure according to a further alternative; and 
           [0025]      FIG. 11  shows a component of an interconnect structure including a deposited metal layer. 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    Turning now to the figures, where like numeric references are used for similar features,  FIGS. 1 and 2  show stacked packages  10  of microelectronic subassemblies  12 ,  14 . The microelectronic subassemblies are electronically and mechanically joined to each other by one or more interconnect structures  50  that include components that will be discussed further herein. 
         [0027]    The stacked package  10  of  FIG. 1  includes a lower assembly  12  and an upper assembly  14 . It is noted that, as used herein, the terms upper and lower, along with any other terms that refer to direction or position such as horizontal or vertical, left or right, and the like, are made with reference to the Figures and to an exemplary mode of use. These terms are used for purposes of clarity in this description and are not limiting, as other positions and orientations would be understood by a person of ordinary skill in the art. Each of the lower  16  and upper  18  substrates have respective lower  20 , 24  and upper  22 , 26  surfaces. The upper surfaces  22 , 26  are generally parallel to their respective lower surfaces  20 , 24 , and all surfaces  20 , 22 , 24 , 26  are generally planar. A thickness for each of the upper  14  and lower  12  substrates is defined between the respective upper  22 , 26  and lower  20 , 24  surfaces. This thickness can be substantially equal between upper  14  and lower  12  substrates or can vary. The thickness is generally less than the length and width of the substrates  12 , 14  by a factor sufficient to give the substrates  12 , 14  a substantially thin, wafer-like structure and falls within a range that is generally understood by those of ordinary skill in the art. 
         [0028]    Each assembly  12 , 14  also includes a respective microelectronic element  30 , 32 . Microelectronic element  30  is shown affixed to lower substrate  16  by flip-chip bonding, in which microelectronic element  30  is inverted such that its conductive contacts (not shown) face toward upper surface  22 . The microelectronic element is then affixed to substrate  16  using conductive projections  34  that extend from its contacts and are bonded using solder masses  36  or another conductive bonding material to second conductive projections  38  formed on substrate  16 . Other arrangements are possible for connecting microelectronic element  30  to substrate  16  including face-up mounting, in which the contacts on microelectronic element  30  face away from upper surface  26 , adhesive is used to bond microelectronic element  30  to upper surface  26 , and wire leads are used to electronically connect the contacts of microelectronic element  30  to conductive features, such as traces or pads, formed on substrate  16 . Microelectronic element  32  is shown affixed to substrate  18  in a similar fashion, and can alternatively be attached as described above. 
         [0029]    The interconnect structure  50  shown in  FIG. 1  includes a conductive pad  52  having a face  54  exposed on upper surface  22  of substrate  16 . The term “exposed at”, as used herein does not refer to any specific means of attachment for pad  52  onto substrate  16  or any relative position therebetween. Rather, it indicates that the electrically conductive structure is available for contact with a theoretical point moving in a direction perpendicular to the surface of the dielectric structure toward the surface of the dielectric structure from outside the dielectric structure. Thus, a terminal or other conductive structure which is exposed at a surface of a dielectric structure may project from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or depression in the dielectric. Pad  52  can be affixed to substrate  16  by forming pad by deposition or the like directly on surface  22 , or it can be embedded within substrate  16  such that face  54  is flush with surface  22  or disposed at a height above or below the surface  22  so long as face  54  remains exposed on surface  22 . In alternative embodiments, interconnect structure  50  can include a conductive trace or a portion of a conductive trace in addition to or substitution for a conductive pad  52 . 
         [0030]    A conductive pillar  56  is formed over a portion of face  54  of conductive pad  52 . As can be seen in  FIG. 1 , the base  58  of pillar  56  covers a portion of face  54  and leaves another portion thereof, extending from the periphery of base  58 , exposed on surface  22 . Pillar  56  also defines an edge surface  60  extending away from base  58  to end  62  of pillar  56 . Although a conductive pillar is shown in  FIG. 1 , alternative structures forming a conductive projection can be used, including a pin, a post or the like, as would be understood by a person of ordinary skill in the art. 
         [0031]    Interconnect structure  50  further includes a contact pad  64  having a face  66  exposed on lower surface  24  of substrate  18 . As with contact pad  52 , pad  64  can be embedded in substrate  18  such that face  66  is flush with, above or beneath lower surface  24  so long as face  66  remains exposed thereon. Pad  64  can be connected to conductive features, such as traces or wires, formed on upper surface  26  of substrate  18  using a conductive via  68  formed through substrate  18 . In an alternative embodiment, interconnect structure  50  can include a trace or a part of a trace exposed on lower surface  24  in place of pad  64 . 
         [0032]    A solder mass  70  is used to mechanically and electronically bond pillar  56  to pad  64 . During formation and assembly of package  10  solder mass  70  can be formed initially on either pillar  56  or pad  64  and then reflowed when the assemblies  12 ,  14  are aligned together to allow solder mass  70  to affix to the other of pillar  56  or pad  64 . Once in place in package  10 , solder mass  70  forms an upper edge  72  and a lower edge  74 . Each of upper edge  72  and lower edge  74  can form into a single line or point or a surface. As shown in  FIG. 1 , upper edge  72  is a surface that extends along a portion of surface  24  surrounding pad  64 . Upper edge  72  can also form a surface that contacts pad  64  or a circular line that surrounds pad either in contact with surface  24  or remote therefrom, depending on the geometry of pad  64 . 
         [0033]    The structures and techniques disclosed herein can help reduce electromigration at an interface between pads and a solder mass connecting the pads. Electromigration can pose problems in areas where two or more metallic elements that are in contact with each other exhibit different diffusion rates. In such case, voids formation can occur in the bonding interface. That is, one metal can pull away from the other, forming a gap or opening therebetween. 
         [0034]    The use of pillar  56 , or another conductive projection, in interconnect structure  50  reduces the distance between the end  62  of pillar  56  and pad  64  along a line of electronic current traveling therebetween when compared to a structure including a solder mass connecting two opposite pads. Accordingly, the structure of  FIG. 1 , in which pillar  56  and pad  64  are both formed from copper, has been shown to be effective in reducing electromigration leading to void formation in a copper-solder-copper interconnect structure. When like metals are used in an electronic interconnect structure in which they are separated by a second metal, an inner-metallic compound, including the like metal, forms within the second metal. This inner-metallic compound will extend from one like metal structure toward the other like metal structure. Inner-metallic compound formation is a factor in reducing void formation due to electromigration because inter-metallic compounds have a slower rate of electromigration than solder. By decreasing the like-metal to like-metal distance within the structure, the inter-metallic compound can be formed extending from one like metal structure to the other like metal structure. In the example of  FIG. 1 , where pad  64  and pillar  56  are formed from copper and solder mass  70  includes tin, the inter-metallic compound can vary in ratio from, for example Cu 3 Sn to Cu 3 Sn 5 . Further, the interconnect structures shown herein can reduce the concentration gradient of the like metal throughout the interconnect structure, which has been shown to be a driving factor for reducing electromigration. The concentration gradient within a structure is the rate at which the concentration of, for example, the like metal changes spatially within a structure. The extension of post  56  into solder mass  70  increases the surface area of copper within the structure, which further increases the presence of inter-metallic compounds within the solder mass  70 . The extension of this increased amount of inter-metallic compound can lower the rate of change in presence of copper within the structure, further reducing electromigration. 
         [0035]    The graphs shown in  FIGS. 3-6  illustrate the phenomenon described above.  FIGS. 3 and 4  show the varying concentration of copper at a horizontal location in an interconnect structure similar to that of  FIG. 1  throughout its vertical distance. The graph shown corresponds to an interconnect structure  50  in which pads  52 , 64  and pillar  56  are made from copper and solder mass  70  is made from a solder compound containing tin.  FIG. 3  shows the concentration of copper when the structure is at a temperature (T 0 ) that occurs in absence of a current passing therethrough, which indicates an absence of copper within solder mass  70  under that temperature condition.  FIG. 4  shows the concentration of copper throughout the same structure at an equilibrium temperature of the structure in presence of an electronic current. The graph of  FIG. 4  shows the presence of a copper concentration within the solder mass  70  that is present due to inter-metallic compound formation. The inter-metallic compound is shown to extend from end  62  of pillar  56  to face  54  of pad  52 . The concentration of copper along both the end and the face  54  also shows a substantial lack of void formation therealong. Further, the graph of  FIG. 4  shows that the presence of pillar  56  can lower the rate of change in concentration of copper through the interconnect  50 . The line representing concentration of copper changes direction abruptly, for example, in the area immediately within solder mass  70  just adjacent pad  64 . Conversely, the change in direction of the line representing concentration of copper is much less drastic in the area of solder mass  70  adjacent pillar  56 . It is noted that the graphs are merely exemplary of and, while illustrative of the behavior discussed herein, may not be to scale or exactly representative of the behavior of the specific structures shown in the Figures. 
         [0036]    The graphs shown in  FIGS. 5 and 6  show the concentration of copper through a prior interconnect structure having a solder mass  170  disposed between two contact pads  152  and  164 , in which the distance  190  between the pads  152 , 164  is substantially the same as the distance  90  between the pads  52 , 64  of  FIGS. 3 and 4 .  FIG. 5  shows the concentration of copper within the structure at T 0 , indicating an absence of copper within solder mass  170  at that condition.  FIG. 6  shows the concentration of copper within the structure at the equilibrium temperature and shows some copper concentration within solder mass  170  due to inter-metallic compound formation, but the concentration does not extend through solder mass  170 . This results in formation of voids  186  resulting in facture. 
         [0037]    Accordingly, the presence of a pillar  56  having an end  62  that extends into the solder mass  70  toward a like-metal structure on the other side of the solder mass, such as pad  64  can decrease the likelihood of void formation due to electromigration. This is particularly true in structures that extend through an overall distance  90  that is greater than the distance through which an inter-metallic compound can be expected to extend. In an embodiment where pillar  56  and pad  64  are formed from copper and the solder mass  70  includes tin, the distance  92  between end  62  and face  66  can be between about 10% and 50% of the distance  90 . It is noted that while in  FIG. 3 , distance  90  is defined between lower surface  24  of substrate  18  and outer surface of dielectric layer  40 , distance  90  is defined between the major surface of whatever type of structure surrounds pads  52 , 64 . 
         [0038]    In an embodiment, lower edge  74  forms a circular line or annular surface around a portion of the edge surface  60  of pillar  56 , which extends into solder mass  70 . Further, lower edge  74  is spaced apart from pad  52  such that solder mass  70  does not directly contact any portion of pad  52 , including the portion that remains exposed around base  58  of pillar  56 . A treatment can be applied to pillar  56 , specifically to edge surface  60 , near base  58  that can prevent solder mass  70  from wicking along edge surface  60  into contact with face  54  or pad  52 . Such treatments can include oxidation or the like. Similarly a layer of material can be applied around edge surface  60  that is resistant to solder flow. 
         [0039]    In a further embodiment, lower edge  74  of solder mass  70  is held away from face  54  of pad  52  by a dielectric layer  40  that extends over face  54  and into contact with at least a portion of edge surface  68  adjacent to base  58 . In this embodiment, solder mass  70  is allowed to flow into contact with dielectric layer  40 , including surface  42 , such that lower edge  74  can extend therealong in a spaced-apart relationship with pad  52 . 
         [0040]    By keeping solder mass  70  away from pad  52 , the likelihood of void formation due to electromigration can also be reduced. An interconnect structure of this type reduced electromigration by lowering the concentration of electronic current within solder mass  70 . As shown in  FIGS. 7 and 8 , a current traveling through interconnect structure  50  moves diagonally along lines from a point on one end of the structure to a point on the other end of the structure that is substantially laterally opposite the point of origin. This means that current traveling from pad  252  in  FIG. 7  will move along a path represented by line  296  that passes through solder mass  270  and back into pillar  256 . The current then leaves pillar  256  and re-enters solder mass  270  before reaching pad  264 . This path results in a current concentration in the portion of solder mass  270  near base  258  of pillar  256 . Current concentration is another driving force behind electromigration that can cause void formation resulting in interconnect failure. 
         [0041]    As shown in  FIG. 8 , by interposing dielectric layer  40  between lower edge  74  of solder mass  70  and the exposed pad  52 , no current will travel out of pad  52 . Rather the current will travel along a line  96  that only enters solder mass  70  once, shown in the interface between end  62  and solder mass  70 . This can reduce the current concentration gradient by a factor of between about 1.25 and 1.75, which can, in turn reduce the likelihood of void formation. A similar path would be observed in a structure wherein solder mass  70  extends outwardly along a portion of dielectric layer  40  so long as solder mass  70  is held away from pad  52  by dielectric layer  40 . 
         [0042]    Dielectric layer  40  is shown in  FIG. 1  as extending along a major portion of upper surface  22  of substrate  16 . This portion includes all of upper surface  22  that is not penetrated by other contact elements. Alternatively, dielectric layer  40  can be formed in portions surrounding any pillars  56  used in interconnect structure  50 , extending away therefrom through a distance sufficient to keep solder masses away from associated contact pads  52 . In such an embodiment dielectric layer portions can be substantially the same size and shape as the contact pads or slightly larger, so as to reliably cover any otherwise exposed portions of the pads. 
         [0043]    In an embodiment, dielectric layer  40  has a thickness  42  in the areas covering pads  52  such that the lower end  74  of solder mass  70  is kept spaced apart at a distance therefrom. This distance can include compensation for any tolerance in overall material thickness to ensure that no holes or gaps are present that lead to unintended exposure of face  54  of pad  52 . The thickness  42  can be between about 10 μm and 30 μm. In such an embodiment, dielectric layer  40  will have a hole  44  or a plurality of holes  44  through which any interconnect pillars  56  extend. Holes  44  form an inner surface  46  that can contact a portion of edge surface  60  extending upwardly from base  58 . 
         [0044]    As shown in  FIG. 11 , a plating layer  488  can be applied over pillar  456  including end  462  and a portion of edge surface  460  exposed over dielectric layer  440 . Plating layer  488  can help ensure a reliable interconnection between pillar  456  and solder mass  470 . 
         [0045]      FIG. 2  shows a stacked assembly  10  including a plurality of microelectronic subassemblies  12 , 14  having interconnect structures  50 . The package  10  shown in  FIG. 2  is substantially similar to that shown in  FIG. 1 , except that the interconnect structure  50  in the package  10  of  FIG. 2  includes a conductive post  76  extending from face  66  of pad  64 . Post includes base  78 , affixed on face  66 , and an edge surface  80  extending to an end  82  remote from face  66 . A second dielectric layer  41  can be formed along lower surface  24  of substrate  18  covering any portion of face  66  and pad  64  exposed outside the periphery of base  78 . As with dielectric layer  40 , dielectric layer  41  keeps upper edge  72  of solder mass  70  from contacting pad  64 , which reduces the current concentration of solder mass  70  near upper edge  72 . This further reduces the likelihood of void formation within interconnect structure  50 , as described above with respect to dielectric layer  40 . 
         [0046]      FIGS. 9 and 10  illustrate the reduction in current concentration within a solder mass included in an interconnect structure that results by keeping the solder mass out of contact with an associated conductive pad.  FIG. 9  shows an interconnect structure  350  that includes a pad  352  with a pillar  356  formed thereon. A solder mass  370  attaches pillar  356  and pad  552  to an upper pad  364  and a post  376  formed thereon. Current flow, represented by line  396 , passes out of contact pad  352  and into solder mass  370 , then passes back into pillar  356  and then back out into solder mass  370 . The current flow (line  396 ) then passes into post  376  before passing back into solder mass  370  and, finally, into pad  364 . This current path  396  results in increased current concentration within the solder mass  370  in the area of the upper edge  372  and lower edge  374  of solder mass  570 . As shown in  FIG. 10 , inclusion of dielectric layers  40 , 41 , prevents the current (line  96 ) from passing through solder mass  70  near the upper  72  or lower  74  edges thereof, reducing the current concentration gradient in each area by a factor of between about 1.25 and 1.75. This can lead to a reduced likelihood of interconnect failure due to void formation in the interface on each end of solder mass  70 . 
         [0047]    Additionally, the inclusion of post  76  in assembly  14  can further decrease the like-metal to like-metal distance within the interconnect structure  70 , as described above with respect to  FIG. 1 . In the structure of  FIG. 2 , this distance is represented by the end-to-end distance  94 . Distance  94  can lead to formation of an inter-metallic compound that extends from end  62  to end  82  when distance  94  is between about 10% and 30% of distance  90 . Post  76  can, alternatively, be any conductive projection, such as a pillar, a pin, or the like. By including conductive projections on both assemblies  12 , 14 , it is possible to achieve a connection that produces a reliable inter-metallic compound while achieving a finer pitch between adjacent interconnect structure  50  than would be possible using a pillar-to-pad arrangement, as shown in  FIG. 1 , while covering a greater overall distance  90 . Further, by forming a dielectric layer  41  over pad  64 , a lower current concentration is possible than with simply a pad  64  to which solder mass  70  is formed. By including post  76  in interconnect structure  50 , the contribution of concentration gradient to electromigration can also be reduced further. In such a structure, the reduction in the rate of change of copper concentration interconnect  50  in the area of pillar  56  can also be achieved in the area of post  76 , thereby removing any abrupt changes in copper concentration at both ends of solder mass  70 . 
         [0048]    The interconnect structures  50  shown in  FIGS. 1 and 2 , including dielectric layers  40 , 41  and their related structures can be used for other connection types beyond the stacked subassembly arrangement shown in  FIGS. 1 and 2 . For example, they can be used in flip-chip bonding (such as shown between microelectronic element  30  and substrate  16  in  FIGS. 1 and 2 ), and in connecting a microelectronic subassembly, such as microelectronic subassembly  12 , to another substrate, either in face-up or flip-chip bonding. Further, an assembly such as assembly  14  can further include an additional contact pad on upper surface  26  of substrate  18  having a pillar and dielectric layer formed thereon in the manner of pillar  56  and dielectric layer  40  to connect to an additional microelectronic assembly using an interconnect structure such as that shown in  FIG. 1  or  2 . This arrangement can be continued to attach further assemblies within a stacked package. 
         [0049]    Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.