Abstract:
In connection with a thermal printer, a method of changeably correcting current dot printing data comprising storing a dot history of dot printing data used previously to print dots, and supplying a signal pattern from a list of signal patterns based on the current dot printing data and the dot history, where the list of signal patterns is based on configuration data which is adjustable.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a divisional of, and claims priority under 35 U.S.C. §120 on, application Ser. No. 11/463,253 filed on Aug. 8, 2006, the content of which is incorporated by reference herein in its entirety. Japanese patent application no. 2005-239171 is also incorporated by reference herein in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to thermal printers, a control method and a control program for thermal printers, in which current dot printing data is corrected. 
         [0004]    2. Description of the Related Art 
         [0005]    Thermal printers such as line thermal printers have numerous independently drivable heating elements arrayed in a row, and print by selectively driving the heating elements to emit heat and thereby cause the dot on the opposing thermal paper to change color. 
         [0006]    The color change produced in the thermal paper depends upon the amount of heat energy applied to the thermal paper or other recording medium by the heating element. In order to print with consistent quality, the heat energy actually applied from the heating element to the recording medium must be stable. 
         [0007]    Printing technologies that consider the recent dot history, and printing technologies that change the heat energy applied by the heating elements to thermal paper having different color layers to produce a particular desired color are also known from the literature. See, for example, Japanese Patent 2,836,584. 
         [0008]    Printers of this type increase the pulse width of the heating element drive circuit to apply heat energy of a HIGH level to print one color, and shorten the pulse width to apply heat energy of a LOW level in order to print another color. 
         [0009]    Printing gray scale content of just one color also requires varying the pulse width according to the density of the color to be printed. 
         [0010]    Understanding this background, a thermal printer that can switch between what is known as a hysteresis (or dot history) control mode enabling high quality monochrome printing by referencing the recent dot history, and a print mode for printing multiple colors, is still desirable. 
         [0011]    Plural types of logic circuits that can provide the control needed for each print mode must be provided in order to achieve this type of thermal printer, but the logic cannot be changed after manufacturing if the logic circuits for each print mode are hard wired. As a result, if an improved control method is developed after a printer is manufactured, the improved control method cannot be implemented by printers that have already been manufactured. In addition, a separate logic circuit must be provided for each print mode, and this increases the size of the printer. 
       SUMMARY OF THE INVENTION 
       [0012]    In one aspect, the invention entails a method of changeably correcting current dot printing data. The method comprises storing a dot history of dot printing data used previously to print dots; and supplying a signal pattern from a list of signal patterns based on the current dot printing data and the dot history, wherein the list of signal patterns is based on configuration data which is adjustable. 
         [0013]    The method may be performed by an integrated circuit or a printer, the latter of which may be a thermal or a line printer. 
         [0014]    In another aspect of the invention, the signal pattern is divided into a series of time periods, and during each time period the signal pattern is dependent upon the current dot printing data the dot history and the configuration data. 
         [0015]    The method may be implemented by way of a processor-executable control program contained on a tangible device- or computer-readable medium. 
         [0016]    Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a schematic diagram of a line thermal printer according to a preferred embodiment of the invention; 
           [0018]      FIG. 2  is a schematic diagram of the print head unit; 
           [0019]      FIG. 3  is a schematic diagram of the printing control unit; 
           [0020]      FIG. 4  is a schematic diagram of the printing control unit; 
           [0021]      FIG. 5  is a logic circuit block diagram of the first through fourth logic circuits; 
           [0022]      FIG. 6  describes the meaning of each bit in a register used for three-stage hysteresis control of monochrome printing; 
           [0023]      FIG. 7  describes the meaning of each bit in a register used for two-color control; 
           [0024]      FIG. 8  is a schematic diagram of the main parts used for single-stage hysteresis control of monochrome printing; 
           [0025]      FIG. 9  is a timing chart of single-stage hysteresis control of monochrome printing; 
           [0026]      FIG. 10  is an equivalent circuit diagram of the first logic circuit; 
           [0027]      FIG. 11  describes the register settings of the first logic circuit during single-stage hysteresis control of monochrome printing; 
           [0028]      FIG. 12  describes the operating states of the first logic circuit; 
           [0029]      FIG. 13  is an equivalent circuit diagram of the second logic circuit; 
           [0030]      FIG. 14  describes the register settings of the second logic circuit during single-stage hysteresis control of monochrome printing; 
           [0031]      FIG. 15  describes the operating states of the second logic circuit; 
           [0032]      FIG. 16  is a schematic diagram of two-color printing control; 
           [0033]      FIG. 17  describes the energizing pattern for two-color printing control; 
           [0034]      FIG. 18  is an equivalent circuit diagram of the first logic circuit during two-color printing control; 
           [0035]      FIG. 19  describes the register settings of the first logic circuit during two-color printing control; 
           [0036]      FIG. 20  is an equivalent circuit diagram of the second logic circuit during two-color printing control; 
           [0037]      FIG. 21  describes the register settings of the second logic circuit during two-color printing control; 
           [0038]      FIG. 22  is an equivalent circuit diagram of the third logic circuit during two-color printing control; 
           [0039]      FIG. 23  describes the register settings of the third logic circuit during two-color printing control; 
           [0040]      FIG. 24  describes the energizing pattern for another example of two-color printing control; 
           [0041]      FIG. 25  describes a specific energizing pattern for another example of two-color printing control; 
           [0042]      FIG. 26  describes the register settings of the first logic circuit in another example of two-color printing control; 
           [0043]      FIG. 27  describes the register settings of the second logic circuit in another example of two-color printing control; 
           [0044]      FIG. 28  describes the register settings of the third logic circuit in another example of two-color printing control; 
           [0045]      FIG. 29  describes the register settings of the fourth logic circuit in another example of two-color printing control; 
           [0046]      FIG. 30  describes the energizing pulse periods; 
           [0047]      FIG. 31  describes single-stage hysteresis control of gray scale printing; 
           [0048]      FIG. 32  describes the register settings of the first logic circuit during single-stage hysteresis control of gray scale printing; 
           [0049]      FIG. 33  describes the register settings of the second logic circuit during single-stage hysteresis control of gray scale printing; 
           [0050]      FIG. 34  describes the register settings of the third logic circuit during single-stage hysteresis control of gray scale printing; 
           [0051]      FIG. 35  describes the register settings of the fourth logic circuit during single-stage hysteresis control of gray scale printing; 
           [0052]      FIG. 36  describes thirteen-level gray scale control of gray scale printing; 
           [0053]      FIG. 37  describes the register settings of the first logic circuit during thirteen-level gray scale control of gray scale printing; 
           [0054]      FIG. 38  describes the register settings of the second logic circuit during thirteen-level gray scale control of gray scale printing; 
           [0055]      FIG. 39  describes the register settings of the third logic circuit during thirteen-level gray scale control of gray scale printing; and 
           [0056]      FIG. 40  describes the register settings of the fourth logic circuit during thirteen-level gray scale control of gray scale printing. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0057]    Preferred embodiments of the present invention are described below with reference to the accompanying figures. 
         [0058]      FIG. 1  is a schematic diagram of a line thermal printer according to a preferred embodiment of the invention. 
         [0059]    This line thermal printer  10  has a controller  11  for controlling the line thermal printer  10 , a print head unit  12  that does the actual printing and a printing control unit  13  that is controlled by the controller  11  and controls the print head unit  12 . 
         [0060]    The controller  11  is a microcomputer comprising an MPU not shown, ROM not shown for storing control programs, and RAM not shown for temporarily storing data. 
         [0061]      FIG. 2  is a schematic block diagram of the print head unit. 
         [0062]    The print head unit  12  has a large number of heating elements (resistances)  21  for simultaneously printing one line of print data (dots). The heating elements  21  are arrayed on the distal edge of the print head unit  12 , which is rendered across the width of the thermal paper used as the recording medium, and simultaneously print one line of pixels on the thermosensitive recording medium (the thermal paper) by selectively driving the heating elements  21  to heat. Numerous drive circuits  22  for independently thermally driving the heating elements  21  are connected to the controller  21 . 
         [0063]    The drive circuits  22  can be bipolar transistors (pnp or npn) or MOS transistors (n-channel MOS or p-channel MOS), but are not so limited. Selectively driving a particular drive circuit  22  causes the corresponding drive circuit  22  to heat, thereby causing the dot at the corresponding position on the thermal paper to change color. 
         [0064]    The drive circuits  22  are shown as NAND devices in  FIG. 2  in order to describe the logic operation of the drive circuits  22 . More specifically, when the inverted strobe signal /STB is inactive (HIGH), operation of the corresponding drive circuit  22  is prohibited. This drive circuit  22  can be easily rendered by connecting a data signal DATA and the inverted strobe signal /STB (positive logic) to the base of a pnp transistor in a wired OR arrangement. 
         [0065]    An inverter  27  inverts the inverted strobe signal /STB (negative logic) so that strobe signal STB and the print data DATA (positive logic) signal are input to the drive circuits  22 , which are thus driven based on the level of each signal. 
         [0066]    More specifically, when a “1” meaning to print the dot is applied as the print dot data, the inverted strobe signal /STB is inverted from HIGH to LOW, thus enabling driving and causing the NAND drive circuit  22  to output LOW. This produces a potential difference to the head voltage in the corresponding heating element, thereby causing the heating element to heat and change the color of the dot at the corresponding position on the thermal paper. The pulse width of the inverted strobe signal /STB supplied in one pulse period may be one of four different pulse widths  1  to  4 . 
         [0067]    To temporarily store the printing data for one printing line, the print head unit  12  rendered in the line thermal printer  10  according to this embodiment of the invention has a shift register  23  and a latch register  24 . 
         [0068]    The print data DATA for one line is input to the shift register  23  synchronized to the clock signal CLK and held. This print data DATA is the data corresponding to each pixel (dot) on one line, but more accurately is data indicating whether each dot is energized or not in the period corresponding to a particular line, and is therefore a bit train wherein “1” means “energize” (drive) and “0” means “do not energize” (do not drive). As further described below, the result of a specific operation executed using the current print dot data and the previous print data DATA is input every predetermined energize (drive) period to the shift register  23  in this embodiment of the invention. 
         [0069]    The latch register  24  is parallel connected to the shift register  23 , and each data bit in the shift register  23  is simultaneously parallel transferred to the corresponding storage area and held. As a result, the print data DATA for the next drive period can be input to the shift register  23  while the drive circuits  22  are driven to print in one energize period. 
         [0070]    The transfer timing of the print data DATA from the shift register  23  to the latch register  24  is controlled according to the input timing of the latch signal /LAT output from the printing control unit  13  to the latch register  24 . The input timing of this latch signal /LAT is after one drive period and before the next drive period, and is also after the print data DATA for the next drive period is written to the shift register  23 . 
         [0071]    As further described below, each storage area in the latch register  24  is connected to one input pin of the drive circuit  22 . When the latch signal /LAT input triggers the latch register  24  to fetch new data, the input data to the drive circuit  22  immediately changes accordingly. When the inverted strobe signal /STB applied to a particular drive circuit  22  is LOW (active), the drive circuit  22  is energized and drives the corresponding heating element  21  based on the print data DATA in the latch register  24 . 
         [0072]    The print head unit  12  also has a thermistor  25  for measuring the temperature of the print head unit  12 , thus enabling knowing the temperature of the print head, which is one factor determining the pulse width, and enabling control preventing the temperature of the print head unit  12  from rising higher than needed (not only for control when a problem occurs). 
         [0073]      FIG. 3  is a schematic block diagram of the printing control unit. 
         [0074]    The printing control unit  13  basically corrects the print dot data received from the host based on the recent dot history, and applies the corrected print dot data to the print head unit  12 . 
         [0075]    The printing control unit  13  has a line buffer unit  31  for storing the print dot data, a shift register unit  32 , a logic circuit unit  34 , a node control circuit unit  35 , a configuration register  36 , and a sequencer unit  37  for cooperatively controlling the operating timing of the shift register unit  32 , logic circuit unit  34 , node control circuit unit  35 , and print head unit  12 . 
         [0076]    The shift register unit  32  fetches dot history data including the print dot data for the current line locally from the line buffer unit  31 , and passes the dot history data to the logic circuit unit  34 . 
         [0077]    The logic circuit unit  34  comprises the same number of logic circuits as there are energize levels, and based on the operating mode each logic circuit can dynamically set the data logic used to actually drive the print head unit  12  based on the output from the shift register unit  32 . 
         [0078]    The node control circuit unit  35  changes the circuits of the logic circuit unit  34 , that is, the data output to the head, every drive period according to the sequence specified by the sequencer unit  37 . 
         [0079]    The configuration register  36  stores settings data, including the data for dynamically setting the data logic of the logic circuit unit  34 . 
         [0080]    The actual circuitry can be rendered in various ways, including as a thermal print head circuit enabling input on plural data lines, a segmented control circuit that prints by dividing one line into multiple blocks to afford compatibility with a low capacitance power supply, and circuits affording various other additional functions. Describing the design of such circuits is even more complex and not essential to the present invention, and further description thereof is therefore omitted. 
         [0081]    This line thermal printer  10  can be driven to operate as a monochrome printer that prints black, or a two-color printer that prints black and red or black and blue, for example, by changing the operating mode configuration. Details of this printer control are described below with reference to the accompanying figures. 
         [0082]      FIG. 4  is a detailed block diagram of the printing control unit. 
         [0083]    As shown in the figure, the line buffer unit  31  of the printing control unit  13  is logically divided into separate storage areas identified as four line buffers B 1  to B 4 . These line buffers can be rendered using one or a plurality of RAM devices. To simplify address control, this embodiment of the invention uses four physically discrete SRAM (static RAM) devices. 
         [0084]    The print dot data train received by a reception circuit not shown from a host device (such as an external personal computer) passes through the controller  11  and is temporarily stored in one of the first to fourth line buffers B 1 -B 4 . 
         [0085]    The line thermal printer  10  has two print modes, a single-color print mode that prints black (the “monochrome mode” below) and a two-color printing mode that prints black and red (the “two-color mode” below). The two-color mode expresses intermediate energy levels and can therefore also be used for gray scale printing of a single color, but is described below as printing black and red. Which print mode is active can be set using a physical configuration means such as a DIP switch disposed to the printer, or by a command sent from the host device. 
         [0086]    The print mode can also be set according to a control command received from the host device. In this case, the print mode setting is stored at a predetermined address in RAM, nonvolatile memory, or other storage device, and is read from this address when a printing process is called. 
         [0087]    When the print mode of the line thermal printer  10  is set to the monochrome mode, the first line buffer B 1  stores the data train for the dots to be printed next (such as the dot data for one line), and the other three line buffers B 2  to B 4  store the print dot data trains for the last three lines printed (the hysteresis data). 
         [0088]    For example, the print dot data for the current line d 0  is stored to line buffer B 1 , the print dot data for the previous line d 1  is stored to line buffer B 2 , the dot data d 2  for the line before the previous line (i.e., two lines before the current line) is stored to line buffer B 3 , and the dot data d 3  for the line before the line before the previous line (i.e., three lines before the current line) is stored in line buffer B 4 . 
         [0089]    When printing the current line ends, dot data d 3  is deleted, and dot data d 2  is logically transferred from line buffer B 3  to line buffer B 4  and used as dot data d 3  in the next printing process. Physically transferring the data is not practical due to time considerations, and logically transferring the data here means that the address lines are controlled so that the buffers are read in the order the data would be read if the data was physically transferred. 
         [0090]    After printing one line ends, dot data d 1  is likewise logically transferred from line buffer B 2  to line buffer B 3  and handled as dot data d 2  in the next printing process, and dot data d 0  is logically transferred from line buffer B 1  to line buffer B 2  and handled as dot data d 1  in the next printing process. 
         [0091]    When the print mode of the line thermal printer  10  is set to the two-color mode, a print dot data train for black dots and a print dot data train for red dots are sequentially sent from the host. More specifically, signals controlling whether black or red prints are stored to separate buffers. In this embodiment of the invention line buffers B 1  and B 2  are used for black dots with line buffer B 1  storing the current black print dot data and line buffer B 2  storing the black print dot data for the previous line. Likewise, line buffers B 3  and B 4  are used for red dots with line buffer B 3  storing the current red print dot data and line buffer B 4  storing the red print dot data for the previous line. 
         [0092]    More specifically, if dot data d 0  is the black print dot data for the current line, dot data d 1  is the black dot data for the previous line, dot data d 2  is the red dot data for the current line, and dot data d 3  is the red dot data for the previous line, the current black dot data d 0  is stored to line buffer B 1 , the previous black dot data d 1  is stored to line buffer B 2 , the current red dot data d 2  is stored to line buffer B 3 , and the previous red dot data d 3  is stored to line buffer B 4 . 
         [0093]    The controller  11  handles storing the dot data to line buffers B 1  to B 4 . More specifically, the controller  11  executes a control program stored in ROM not shown to function as a memory allocation circuit, and controls storing the dot data to the line buffers as described above according to the currently set print mode. The line buffer unit  31  controls data transfers between the line buffers B 1  to B 4  according to the mode setting. 
         [0094]    The shift register unit  32  comprises a first shift register  41  for first line buffer B 1 , a second shift register  42  for second line buffer B 2 , a third shift register  43  for third line buffer B 3 , and a fourth shift register  44  for fourth line buffer B 4 . 
         [0095]    The first shift register  41  to fourth shift register  44  store the dot data d 1  to d 4  described above. Operationally, the data stored in the line buffer unit  31  is read in address blocks (a 16 dot unit because the address is 16 bits wide in this embodiment of the invention) and the shift registers shift synchronized to the print head transfer clock generated by the sequencer unit  37 . When transferring the 16 dots ends, this operation repeats to read and shift the 16 dots of data at the next address in the line buffer. 
         [0096]    The logic circuit unit  34  of the printing control unit  13  comprises the first logic circuit  71  to fourth logic circuit  74  used for monochrome printing and two-color printing. 
         [0097]    The first logic circuit  71  to fourth logic circuit  74  are identically configured, and first logic circuit  71  is therefore described by way of example below. 
         [0098]      FIG. 5  is a block diagram of a logic circuit used as the first logic circuit  71  to the fourth logic circuit  74 . 
         [0099]    This first logic circuit  71  has four inverters  81 - 1  to  81 - 4 , sixteen five-input AND circuits  82 - 0  to  82 - 15  corresponding to the 16 bits, and a 16-input OR circuit  83 . 
         [0100]    Registers PCn 0  to PCnF are connected to one input node of each of the AND circuits  82 - 0  to  82 - 15 . 
         [0101]    The output of first shift register  41  is connected to AND circuits  82 - 15 ,  82 - 7 ,  82 - 11 ,  82 - 3 ,  82 - 13 ,  82 - 5 ,  82 - 9 ,  82 - 1 , and inverter  81 - 1 . 
         [0102]    The output of second shift register  42  is connected to AND circuits  82 - 15 ,  82 - 7 ,  82 - 11 ,  82 - 3 ,  82 - 14 ,  82 - 6 ,  82 - 10 ,  82 - 1 , and inverter  81 - 2 . 
         [0103]    The output of third shift register  43  is connected to AND circuits  82 - 15 ,  82 - 7 ,  82 - 13 ,  82 - 5 ,  82 - 14 ,  82 - 6 ,  82 - 12 ,  82 - 4 , and inverter  81 - 3 . 
         [0104]    The output of fourth shift register  44  is connected to AND circuits  82 - 15 ,  82 - 11 ,  82 - 13 ,  82 - 9 ,  82 - 14 ,  82 - 10 ,  82 - 12 ,  82 - 8 , and inverter  81 - 4 . 
         [0105]    The output of inverter  81 - 1  is connected to AND circuits  82 - 0 ,  82 - 2 ,  82 - 4 ,  82 - 6 ,  82 - 8 ,  82 - 10 ,  82 - 12 ,  82 - 14 . 
         [0106]    The output of inverter  81 - 2  is connected to AND circuits  82 - 0 ,  82 - 1 ,  82 - 4 ,  82 - 5 ,  82 - 8 ,  82 - 9 ,  82 - 12 ,  82 - 13 . 
         [0107]    The output of inverter  81 - 3  is connected to AND circuits  82 - 1 ,  82 - 2 ,  82 - 3 ,  82 - 4 ,  82 - 8 ,  82 - 9 ,  82 - 10 ,  82 - 11 . 
         [0108]    The output of inverter  81 - 4  is connected to AND circuits  82 - 0 ,  82 - 1 ,  82 - 2 ,  82 - 3 ,  82 - 4 ,  82 - 5 ,  82 - 6 ,  82 - 7 . 
         [0109]    The configuration register  36  comprises 16 registers PCn 0  to PCnF for each of the first to fourth drive periods, and thus has a total 64 registers. More specifically, the configuration register  36  has 64 registers including registers PC 30  to PC 3 F for the first drive period, registers PC 20  to PC 2 F for the second drive period, registers PC 10  to PC 1 F for the third drive period, and registers PC 00  to PC 0 F for the fourth drive period. 
         [0110]    The logic output Sn of the first to fourth logic circuits  71 - 74  is expressed using dot data d 0  to d 3  as shown in equation 1. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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                   Eq 
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                   .1 
                 
               
             
           
         
       
     
         [0111]    As will be known from equation 1, any value of 0 in registers PCn 0  to PCnF is 0 regardless of the corresponding logic value (d 0  to d 3  and the inverted /d 0  to /d 3 ), and has no effect on the logic output Sn. 
         [0112]    The meaning of the logic output Sn (n=1 to 4) and each bit (16 bits) in register PCn is described below for three-stage hysteresis control of monochrome printing and two-color printing. 
         [0113]      FIG. 6  describes the meaning of each bit in the registers for three-stage hysteresis control of monochrome printing. 
         [0114]    In  FIG. 6  bX (where X=0−Fh (h denotes hexadecimal)) is one bit in registers PCn 0  to PCnF. 
         [0115]    For example, in equation 1 the logic values corresponding to bit b 0  are the four values /d 0  to /d 3 . The logic values corresponding to bit b 8  are the four values /d 0  to /d 2  and d 3 . The logic values corresponding to bit b 15  are the four values d 0  to d 3 . 
         [0116]    The meaning of each bit (16 bits) in register PCn and logic output Sn (n=1 to 4) in three-stage hysteresis control of monochrome printing is described below. 
         [0117]      FIG. 7  describes the meaning of each bit in the register during two-color printing. 
         [0118]    Logic values d 0  and d 1  denote black, logic values /d 0  and /d 1  denote red or non-printing, logic values d 2  and d 3  denote red (black), and logic values /d 2  and /d 3  denote black or non-printing. 
         [0119]    In  FIG. 7  bX (where X=0−Fh (h denotes hexadecimal)) is one bit in registers PCn 0  to PCnF. 
         [0120]    For example, in equation 1 the logic values corresponding to bit b 0  are the four values /d 0  to /d 3 . The logic values corresponding to bit b 8  are the four values /d 0  to /d 2  and d 3 . The logic values corresponding to bit b 15  are the four values d 0  to d 3 . 
         [0121]    The operation of this embodiment of the invention is described next. 
       (1) Control in One-Stage Hysteresis Control of Monochrome Printing 
       [0122]    Control in one-stage hysteresis control of monochrome printing is described first below. 
         [0123]    One-stage hysteresis control of monochrome printing refers to controlling monochrome printing with reference only to the print data for the previous line (one-stage hysteresis control). 
         [0124]    For simplicity below, the energize (drive) period is not segmented and there is only one output to the print head unit  12 . 
         [0125]      FIG. 8  is a schematic block diagram of the arrangement used for single-stage hysteresis control of monochrome printing. 
         [0126]    For single-stage hysteresis control of monochrome printing the line buffer unit  31  uses the first line buffer B 1  (to store the current dot data d 0 ) and second line buffer B 2  (to store the previous dot data d 1 ), and dot data d 0  is transferred to the first shift register  41  and dot data d 1  is transferred to the second shift register  42 . 
         [0127]      FIG. 9  is a timing chart of single-stage hysteresis control for monochrome printing. 
         [0128]    The dot data d 0  stored in first shift register  41  and the dot data d 1  stored in second shift register  42  is sequentially transferred to the first logic circuit  71  and second logic circuit  72 , respectively, based on the clock signal CLK output by the sequencer unit  37  as shown in  FIG. 9 . 
         [0129]    The first logic circuit  71  uses a logic operation to generate hysteresis data for driving the print head (hysteresis drive) based on the dot history of the last line, that is, based on dot data d 1 , and outputs the hysteresis data through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0130]    When the latch signal /LAT then goes LOW, the hysteresis data stored in shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the hysteresis data drives the heating element  21  to print. 
         [0131]    Parallel to this operation the second logic circuit  72  applies a logic operation to generate the current drive data for the current line based on the current dot data d 0 , and transfers the drive data through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0132]    When the latch signal /LAT then goes LOW, the current drive data stored in shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the hysteresis data drives the heating element  21  to print. 
         [0133]      FIG. 10  is an equivalent circuit diagram of the first logic circuit. 
         [0134]    When dot data d 0  and dot data d 1  are input, the logical product of the logic value of dot data d 0  and the logic value of the inverted dot data /d 1 , which is the logic of dot data d 1  inverted by the inverter circuit  71 A (NOT circuit), is acquired by AND circuit  71 B, and output as output logic S 1 . 
         [0135]      FIG. 11  describes the register settings of the first logic circuit during single-stage hysteresis control of monochrome printing. 
         [0136]    During single-stage hysteresis control for monochrome printing, register PC 3 D, register PC 35 , register PC 39 , and register PC 31  in first logic circuit  71  are set to 1, and the other registers are set to 0, as shown in  FIG. 11 . 
         [0137]      FIG. 12  describes the operating states of the first logic circuit. 
         [0138]    As indicated by the bold lines in  FIG. 12 , the only elements of the first logic circuit  71  that actually operate at this time are inverter  81 - 1  and AND circuits  82 - 13 ,  82 - 5 ,  82 - 9 , and  82 - 1 . 
         [0139]      FIG. 13  is an equivalent circuit diagram of the second logic circuit. 
         [0140]    When dot data d 0  and dot data d 1  are input, the logic value of dot data d 0  is output as output logic S 2 . 
         [0141]      FIG. 14  describes the register settings of the second logic circuit during single-stage hysteresis control of monochrome printing. 
         [0142]    During single-stage hysteresis control for monochrome printing, register PC 2 F, register PC 27 , register PC 2 B, register PC 23 , register PC 2 D, register PC 25 , register PC 29 , and register PC 21  in second logic circuit  72  are set to 1, and the other registers are set to 0, as shown in  FIG. 14 . 
         [0143]      FIG. 15  describes the operating states of the second logic circuit. 
         [0144]    As indicated by the bold lines in  FIG. 15 , the only elements of the second logic circuit  72  that actually operate at this time are AND circuits  82 - 15 ,  82 - 7 ,  82 - 11 ,  82 - 3 ,  82 - 13 ,  82 - 5 ,  82 - 9 , and  82 - 1 . 
       (2) Two-Color Printing Control 
       [0145]    Two-color printing control is described next. It is assumed below that red is printed when the energize (drive) time is short, that is, the temperature of the thermal paper is low, and black is printed after passing through a red print stage when the energize (drive) time is long, that is, the temperature of the thermal paper is high. 
         [0146]      FIG. 16  is a schematic diagram of two-color printing control. 
         [0147]    When operating in the two-color printing mode, the first line buffer B 1  (for storing the current black dot data d 0 ), the second line buffer B 2  (for storing the previous black dot data d 1 ), the third line buffer B 3  (for storing the current red dot data d 2 ), and the fourth line buffer B 4  (for storing the previous red dot data d 3 ) of the line buffer unit  31  are used. In addition, dot data d 0  is transferred to the first shift register  41 , dot data d 1  is transferred to the second shift register  42 , dot data d 2  is transferred to the third shift register  43 , and dot data d 3  is transferred to the fourth shift register  44 . 
         [0148]    As shown in  FIG. 16 , the dot data d 0  stored in first shift register  41 , the dot data d 1  stored in second shift register  42 , the dot data d 2  stored in third shift register  43 , and the dot data d 3  stored in fourth shift register  44  is sequentially transferred to first logic circuit  71 , second logic circuit  72 , and third logic circuit  73 , respectively, based on the clock signal CLK output by the sequencer unit  37 . 
         [0149]    The first logic circuit  71  therefore generates the first drive data I as print data DATA for the first drive period from a logic operation based on the current black dot data d 0 , the current red dot data d 2 , and the previous red dot data d 3 , and transfers the first drive data I through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0150]    When the latch signal /LAT then goes LOW, the first drive data I stored in shift register  23  is transferred to latch register  24 , and when the inverted strobe signal /STB goes LOW, the drive circuit  22  corresponding to the first drive data I drives the heating element  21  to print. 
         [0151]    Parallel to printing the first drive data I, the second logic circuit  72  generates the second drive data II for the second drive period from a logic operation on the current black dot data d 0 , the previous black dot data d 1 , and the current red dot data d 2 , and transfers the second drive data II through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0152]    When the latch signal /LAT then goes LOW, the second drive data II stored in the shift register  23  is transferred to the latch register  24 , and when the inverted strobe signal /STB goes LOW, the drive circuit  22  corresponding to the second drive data II drives the heating element  21  to print. 
         [0153]    Parallel to printing the second drive data II, the third logic circuit  73  generates the third drive data III for the third drive period based on the current black dot data d 0 , and transfers the third drive data III through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0154]    When the latch signal /LAT then goes LOW, the third drive data III stored in the shift register  23  is transferred to the latch register  24 , and when the inverted strobe signal /STB goes LOW, the drive circuit  22  corresponding to the third drive data III drives the heating element  21  to print. 
         [0155]    A specific drive pattern is described next. 
         [0156]      FIG. 17  describes the energizing pattern for two-color printing control. 
         [0157]    If the previously color printed by a particular dot was black and the current color is red, the heating element is energized only during the first drive period. That is, the drive period is the shortest drive period. 
         [0158]    If the previously color printed was red and the current color is also red, the heating element is energized only during the second drive period. 
         [0159]    If the previously color printed was blank (i.e., the dot did not print) and the current color is red, the heating element is energized during the first drive period and the second drive period. 
         [0160]    If the previously color printed was black and the current color is black, the heating element is energized during the first drive period and the third drive period. 
         [0161]    If the previously color printed was red and the current color is black, the heating element is energized during the second drive period and the third drive period. 
         [0162]    If the previously color printed was blank (i.e., the dot did not print) and the current color is black, the heating element is energized during the first drive period, the second drive period, and the third drive period. That is, the drive period is the longest. 
         [0163]      FIG. 18  is an equivalent circuit diagram of the first logic circuit during two-color printing control. 
         [0164]    When dot data d 0 , dot data d 1 , and dot data d 3  are input to first logic circuit  71 , an OR circuit outputs the logical sum of the logic values of dot data d 0  and dot data d 1 , an inverter (NOT gate) inverts dot data d 3  and outputs inverted dot data /d 3 , and an AND outputs the logical product of the logical sum output by the OR gate and the logical value of the inverted /dot data d 3 . The AND gate outputs logic value I. 
         [0165]      FIG. 19  describes the register settings of the first logic circuit during two-color printing control. 
         [0166]    To implement the operation described above, register PC 27 , register PC 23 , register PC 25 , register PC 21 , register PC 24 , and register PC 26  in the first logic circuit  71  are set to “1” and the other registers are set to 0 as shown in  FIG. 19 . 
         [0167]      FIG. 20  is an equivalent circuit diagram of the second logic circuit during two-color printing control. 
         [0168]    When dot data d 0 , dot data d 1 , and dot data d 2  are input to the second logic circuit  72 , OR gate  72 A outputs the logical sum of the logic values of dot data d 0  and dot data d 2 , inverter (NOT gate)  72 B inverts the dot data d 1  and outputs inverted dot data /d 1 , and AND gate  72 C obtains the logical product of inverted dot data /d 1  and the output of OR gate  72 A and outputs logic value II. 
         [0169]      FIG. 21  describes the register settings of the second logic circuit during two-color printing control. 
         [0170]    To implement the operation described above, register PC 1 D, register PC 13 , register PC 11 , register PC 19 , register PC 1 C, and register PC 14  in the second logic circuit  72  are set to “1” and the other registers are set to “0” as shown in  FIG. 21 . 
         [0171]      FIG. 22  is an equivalent circuit diagram of the third logic circuit during two-color printing control. 
         [0172]    When dot data d 0  is input, dot data d 0  is output directly as logic value III. 
         [0173]      FIG. 23  describes the register settings of the third logic circuit during two-color printing control. 
         [0174]    To implement the operation described above, register PC 0 F, register PC 07 , register PC 03 , register PC 0 B, register PC 0 D, register PC 05 , register PC 01 , and register PC 09  in the third logic circuit  73  are set to “1” and the other registers are set to “0.” 
       (3) Another Method of Two-Color Printing Control 
       [0175]    Another method of two-color printing control is described next. This two-color printing control method differs from the above method in that the energize period is divided into four parts, that is, first to fourth drive periods, and the settings are configured to emphasize printing red. 
         [0176]      FIG. 24  describes the energizing pattern in this example of two-color printing control. 
         [0177]    The ratio of the lengths of these first to fourth drive periods is 15%, 45%, 20%, and 20%, respectively, in this embodiment of the invention, but the invention is obviously not so limited. 
         [0178]    This embodiment of the invention uses the first line buffer B 1  (for storing the current black dot data d 0 ), the second line buffer B 2  (for storing the previous black dot data d 1 ), the third line buffer B 3  (for storing the current red dot data d 2 ), and the fourth line buffer B 4  (for storing the previous red dot data d 3 ) of the line buffer unit  31 . In addition, dot data d 0  is transferred to the first shift register  41 , dot data d 1  is transferred to the second shift register  42 , dot data d 2  is transferred to the third shift register  43 , and dot data d 3  is transferred to the fourth shift register  44 . 
         [0179]    As shown in  FIG. 16 , the dot data d 0  stored in first shift register  41 , the dot data d 1  stored in second shift register  42 , the dot data d 2  stored in third shift register  43 , and the dot data d 3  stored in fourth shift register  44  is sequentially transferred to first logic circuit  71 , second logic circuit  72 , and third logic circuit  73 , respectively, based on the clock signal CLK output by the sequencer unit  37 . 
         [0180]    The first logic circuit  71  therefore generates the first drive data I as print data DATA for the first drive period from a logic operation based on the current black dot data d 0 , the current red dot data d 2 , and the previous red dot data d 3  as the print data DATA, and transfers the first drive data I through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0181]    When the latch signal /LAT then goes LOW, the first drive data I stored in shift register  23  is transferred to latch register  24 , and when the inverted strobe signal /STB goes LOW, the drive circuit  22  corresponding to the first drive data I drives the heating element  21  to print. 
         [0182]    Parallel to printing the first drive data I, the second logic circuit  72  generates the second drive data II for the second drive period from a logic operation on the current black dot data d 0 , the previous black dot data d 1 , and the current red dot data d 2 , and transfers the second drive data II through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0183]    When the latch signal /LAT then goes LOW, the second drive data II stored in the shift register  23  is transferred to the latch register  24 , and when the inverted strobe signal /STB goes LOW, the drive circuit  22  corresponding to the second drive data II drives the heating element  21  to print. 
         [0184]    Parallel to printing the second drive data II, the third logic circuit  73  generates the third drive data III for the third drive period from a logic operation based on the current black dot data d 0 , and transfers the third drive data III through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0185]    When the latch signal /LAT then goes LOW, the third drive data III stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the third drive data III drives the heating element  21  to print. 
         [0186]    Parallel to printing the third drive data III, the fourth logic circuit  74  generates fourth drive data IV for the third drive period from a logic operation based on the current black dot data d 0 , and transfers the fourth drive data IV through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0187]    When the latch signal /LAT then goes LOW, the fourth drive data IV stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the fourth drive data IV drives the heating element  21  to print. 
         [0188]    A specific drive pattern is described next. 
         [0189]      FIG. 25  describes a specific energizing pattern for this example of two-color printing control. 
         [0190]    If the previously color printed by a particular dot was black and the current color is red, the heating element is energized only during the fourth drive period. That is, the drive period is the shortest total energizing time. 
         [0191]    If the previously color printed was red and the current color is also red, the heating element is energized during the first and fourth drive periods as shown in  FIG. 25 . 
         [0192]    If the previously color printed was blank (nothing printed) and the current color is red, the heating element is energized during the third and fourth drive periods as shown in  FIG. 25 . 
         [0193]    If the previously color printed was black and the current color is black, the heating element is energized during the second drive period, the third drive period, and the fourth drive period as shown in  FIG. 25 . 
         [0194]    If the previously color printed was red and the current color is black, the heating element is energized during the second drive period, the third drive period, and the fourth drive period as shown in  FIG. 25 . 
         [0195]    If the previously color printed was blank (nothing printed) and the current color is black, the heating element is energized during the first drive period, the second drive period, the third drive period, and the fourth drive period as shown in  FIG. 25 . The total energizing time of the drive period is the longest in this case. 
         [0196]      FIG. 26  describes the register settings of the first logic circuit in this example of two-color printing control. 
         [0197]    For the operation described in this example, register PC 35 , register PC 31 , and register PC 3 C in the first logic circuit  71  are set to “1” as shown in  FIG. 26 , and the other registers are set to “0.” 
         [0198]      FIG. 27  describes the register settings of the second logic circuit in this example of two-color printing control. 
         [0199]    As shown in  FIG. 27 , register PC 2 F, register PC 27 , register PC 23 , register PC 21 , register PC 2 D, register PC 25 , register PC 21 , and register PC 29  of the second logic circuit  72  are set to “1”, and the other registers are set to “0.” 
         [0200]      FIG. 28  describes the register settings of the third logic circuit in this example of two-color printing control. 
         [0201]    As shown in  FIG. 28 , register PC 2 F, register PC 27 , register PC 23 , register PC 11 , register PC 1 D, register PC 15 , register PC 11 , register PC 19 , and register PC 14  of the third logic circuit  73  are set to “1”, and the other registers are set to “0.” 
         [0202]      FIG. 29  describes the register settings of the fourth logic circuit in this example of two-color printing control. 
         [0203]    As shown in  FIG. 29 , register PC 0 F, register PC 07 , register PC 03 , register PC 01 , register PC 0 D, register PC 05 , register PC 01 , register PC 09 , register PC 0 C, register PC 04 , register PC 0 E, and register PC 06  of the fourth logic circuit  74  are set to “1”, and the other registers are set to “0.” 
       (4) Single-Stage Hysteresis Control of Gray Scale Printing 
       [0204]    Single-stage hysteresis control of gray scale printing is described next. 
         [0205]      FIG. 30  describes the energizing pulse periods. 
         [0206]    If the length of a standard energizing pulse period is 1, the length of a first pulse period is 8/15, the length of a second pulse period is 4/15, the length of a third pulse period is 2/15, and the length of a fourth pulse period is 1/15 as shown in  FIG. 30 . 
         [0207]      FIG. 31  describes single-stage hysteresis control of gray scale printing. 
         [0208]    This embodiment of the invention prints in four level gray scale ranging from density 0 to density 3 based on the recent dot history. 
         [0209]    This embodiment of the invention uses the first line buffer B 1  of the line buffer unit  31  (to store dot data d 0  when the current print density is level 1 or level 3), the second line buffer B 2  (to store dot data d 1  when the current print density is level 2 or level 3), the third line buffer B 3  (to store dot data d 2  when the previous print density was level 1 or level 3), and the fourth line buffer B 4  (to store dot data d 3  when the previous print density was level 2 or level 3). In addition, dot data d 0  is transferred to first shift register  41 , dot data d 1  is transferred to second shift register  42 , dot data d 2  is transferred to third shift register  43 , and dot data d 3  is transferred to fourth shift register  44 . 
         [0210]    As shown in  FIG. 16 , the dot data d 0  stored in first shift register  41 , the dot data d 1  stored in second shift register  42 , the dot data d 2  stored in third shift register  43 , and the dot data d 3  stored in fourth shift register  44  is sequentially transferred to first logic circuit  71 , second logic circuit  72 , and third logic circuit  73 , respectively, based on the clock signal CLK output by the sequencer unit  37 . 
         [0211]    The first logic circuit  71  therefore generates the first drive data I as print data DATA for the first drive period from a logic operation based on dot data d 2  when the previous print density was level 1 or level 3, and transfers the first drive data I through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0212]    When the latch signal /LAT then goes LOW, the first drive data I stored in shift register  23  is transferred to latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the first drive data I drives the heating element  21  to print. 
         [0213]    Parallel to printing the first drive data I, the second logic circuit  72  generates the second drive data II for the second drive period from a logic operation based on the dot data d 0  when the current print density is level 1 or level 3, and transfers the second drive data II through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0214]    When the latch signal /LAT then goes LOW, the second drive data II stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the second drive data II drives the heating element  21  to print. 
         [0215]    Parallel to printing the second drive data II, the third logic circuit  73  generates the third drive data III for the third drive period from a logic operation based on dot data d 0  when the current print density is level 1 or 3, dot data d 2  when the previous print density was level 1 or level 3, and dot data d 3  when the previous print density was level 2 or level 3, and transfers the third drive data III through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0216]    When the latch signal /LAT then goes LOW, the third drive data III stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the third drive data III drives the heating element  21  to print. 
         [0217]    Parallel to printing the third drive data III, the fourth logic circuit  74  generates fourth drive data IV for the third drive period from a logic operation based on dot data d 0  when the current print density is level 1 or 3, dot data d 1  when the current print density is level 2 or level 3, and dot data d 2  when the previous print density was level 1 or level 3, and transfers the fourth drive data IV through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0218]    When the latch signal /LAT then goes LOW, the fourth drive data IV stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the fourth drive data IV drives the heating element  21  to print. 
         [0219]      FIG. 32  describes the register settings of the first logic circuit during single-stage hysteresis control of gray scale printing. 
         [0220]    As shown in  FIG. 32 , during single-stage hysteresis control of gray scale printing, register PC 3 E, register PC 3 C, register PC 3 B, register PC 3 D, register PC 37 , register PC 35 , register PC 34 , and register PC 36  in the first logic circuit  71  are set to “1”, and the other registers are set to “0.” 
         [0221]      FIG. 33  describes the register settings of the second logic circuit during single-stage hysteresis control of gray scale printing. 
         [0222]    As shown in  FIG. 33 , register PC 2 F, register PC 27 , register PC 23 , register PC 2 B, register PC 2 D, register PC 25 , register PC 21 , and register PC 29  in the second logic circuit  72  are set to “1”, and the other registers are set to “0.” 
         [0223]      FIG. 34  describes the register settings of the third logic circuit during single-stage hysteresis control of gray scale printing. 
         [0224]    As shown in  FIG. 34 , register PC 13 , register PC 1 B, register PC 11 , register PC 19 , register PC 10 , register PC 18 , register PC 12 , and register PC 1 A in the third logic circuit  73  are set to “1”, and the other registers are set to “0.” 
         [0225]      FIG. 35  describes the register settings of the fourth logic circuit during single-stage hysteresis control of gray scale printing. 
         [0226]    As shown in  FIG. 35 , register PC 05 , register PC 01 , register PC 09 , register PC 0 C, register PC 00 , and register PC 08  in the fourth logic circuit  74  are set to “1”, and the other registers are set to “0.” 
         [0227]    As described above, this embodiment of the invention uses a logic circuit to provide single-stage hysteresis control of gray scale printing. 
       (5) Thirteen-Level Gray Scale Control of Gray Scale Printing 
       [0228]    Thirteen-level gray scale control of gray scale printing is described next. 
         [0229]    As described in  FIG. 30 , if the length of a standard energizing pulse period is 1, the length of a first pulse period is 8/15, the length of a second pulse period is 4/15, the length of a third pulse period is 2/15, and the length of a fourth pulse period is 1/15. 
         [0230]    This embodiment of the invention prints in thirteen level gray scale ranging from density 0 to density 12. 
         [0231]      FIG. 36  describes thirteen-level gray scale control of gray scale printing. 
         [0232]    This embodiment of the invention uses the first line buffer B 1  of the line buffer unit  31  (to store dot data d 0  for print density level 5 and higher), the second line buffer B 2  (to store dot data d 1  for print density levels 1 to 4 and density levels 9 to 12), the third line buffer B 3  (to store dot data d 2  for print density levels 3, 4, 7, 8, 11, 12), and the fourth line buffer B 4  (to store dot data d 3  for print density levels 2, 4, 6, 8, 10, 12). In addition, dot data d 0  is transferred to first shift register  41 , dot data d 1  is transferred to second shift register  42 , dot data d 2  is transferred to third shift register  43 , and dot data d 3  is transferred to fourth shift register  44 . 
         [0233]    As shown in  FIG. 16 , the dot data d 0  stored in first shift register  41 , the dot data d 1  stored in second shift register  42 , the dot data d 2  stored in third shift register  43 , and the dot data d 3  stored in fourth shift register  44  is sequentially transferred to first logic circuit  71 , second logic circuit  72 , and third logic circuit  73 , respectively, based on the clock signal CLK output by the sequencer unit  37 . 
         [0234]    The first logic circuit  71  therefore generates the first drive data I as print data DATA for the first drive period from a logic operation based on dot data d 0  when the print density level is 5 or higher, and transfers the first drive data I through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0235]    When the latch signal /LAT then goes LOW, the first drive data I stored in shift register  23  is transferred to latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the first drive data I drives the heating element  21  to print. 
         [0236]    Parallel to printing the first drive data I, the second logic circuit  72  generates the second drive data II for the second drive period from a logic operation based on the dot data d 1  for print density levels 1 to 4, and transfers the second drive data II through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0237]    When the latch signal /LAT then goes LOW, the second drive data II stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the second drive data II drives the heating element  21  to print. 
         [0238]    Parallel to printing the second drive data II, the third logic circuit  73  generates the third drive data III for the third drive period from a logic operation based on dot data d 2  for print density levels 3, 4, 7, 8, 11, 12, and transfers the third drive data III through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0239]    When the latch signal /LAT then goes LOW, the third drive data III stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the third drive data III drives the heating element  21  to print. 
         [0240]    Parallel to printing the third drive data III, the fourth logic circuit  74  generates fourth drive data IV for the third drive period from a logic operation based on dot data d 3  when the print density level is 2, 4, 6, 8, 10, or 12, and transfers the fourth drive data IV through the node control circuit unit  35  to the shift register  23  of the print head unit  12 . 
         [0241]    When the latch signal /LAT then goes LOW, the fourth drive data IV stored in the shift register  23  is transferred to the latch register  24 , and when the strobe signal /STB goes LOW, the drive circuit  22  corresponding to the fourth drive data IV drives the heating element  21  to print. 
         [0242]      FIG. 37  describes the register settings of the first logic circuit during thirteen-level gray scale control of gray scale printing. 
         [0243]    To implement this operation, register PC 3 F, register PC 37 , register PC 33 , register PC 3 B, register PC 3 D, register PC 35 , register PC 31 , and register PC 39  in the first logic circuit  71  are set to “1”, and the other registers store 0 as shown in  FIG. 37 . 
         [0244]      FIG. 38  describes the register settings of the second logic circuit during thirteen-level gray scale control of gray scale printing. 
         [0245]    As shown in  FIG. 38 , register PC 2 F, register PC 27 , register PC 23 , register PC 2 B, register PC 2 E, register PC 26 , register PC 22 , and register PC 2 A of the second logic circuit  72  are set to “1”, and the other registers are set to “0.” 
         [0246]      FIG. 39  describes the register settings of the third logic circuit during thirteen-level gray scale control of gray scale printing. 
         [0247]    As shown in  FIG. 39 , register PC 1 F, register PC 17 , register PC 1 C, register PC 15 , register PC 1 C, register PC 14 , register PC 1 E, and register PC 16  of the third logic circuit  73  are set to “1”, and the other registers are set to “0.” 
         [0248]      FIG. 40  describes the register settings of the fourth logic circuit during thirteen-level gray scale control of gray scale printing. 
         [0249]    As shown in  FIG. 40 , register PC 0 F, register PC 0 B, register PC 0 D, register PC 09 , register PC 0 C, register PC 08 , register PC 0 E, and register PC 0 A of the fourth logic circuit  74  are set to “1”, and the other registers are set to “0.” 
         [0250]    As described above, this embodiment of the invention uses a logic circuit to provide gray scale printing control in thirteen levels. 
         [0251]    It will thus be obvious that the present invention enables using a single logic circuit arrangement to control plural print modes, and the control logic can be easily dynamically changed to afford high quality printing in each print mode. 
         [0252]    The logic can also be easily changed while printing is in progress, thus affording compatibility with a wide range of printing needs. 
         [0253]    Although the present invention has been described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. For example, four logical buffers B 1  to B 4  are used in this embodiment of the invention, but as few as two logical buffers can be used depending on the print modes. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom.