Abstract:
A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a substrate of semiconductor device, and more particularly, to a hybrid-orientation substrate. 
         [0003]    2. Description of the Prior Art 
         [0004]    Through the decades, ever-increasing silicon CMOS performance has been relying on device scaling, i.e., reducing channel length, gate oxide, and threshold voltage. Today, as very large scale integration (VLSI) technology enters the 65-nm node and beyond, power consumption has become a limiting factor. To circumvent this limitation, novel device structures and materials are widely pursued, such as FinFETs, vertical MOSFETs, high-k dielectric and/or metal gate, and most of all, various approaches for carrier-mobility enhancement. Process-strained silicon channels engineering by film deposition, trench isolation, silicidation and source/drain materials have been introduced in 90-nm technology. Higher carrier mobility from a new channel material, such as Ge, is also under study. Above all, a novel approach commonly referred to as hybrid-orientation technology (HOT) has been derived to improve carrier mobility through wafer and channel orientation optimization. 
         [0005]    Despite the fact that HOT has received considerable attention because its fabrication processes are fully compatible with current VLSI technology without additional new materials, there are still many issues of device design and process integration for this new structure. These include device isolation, epitaxial quality and scalability, mixture of silicon-on-insulator (SOI) and bulk devices. 
       SUMMARY OF THE INVENTION 
       [0006]    It is therefore an objective of the present invention to provide a hybrid-orientation substrate and fabrication method thereof for optimizing the carrier mobility of the device. 
         [0007]    According to a preferred embodiment of the present invention, a method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation. 
         [0008]    Another aspect of the present invention provides a substrate of semiconductor device, which includes: a first silicon layer having a first region and a second region defined thereon; an epitaxial layer on the first region; a dielectric on the second region; and a second silicon layer on the dielectric layer, in which the second silicon layer and the epitaxial layer comprise same crystalline orientation. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIGS. 1-4  illustrate a method for fabricating substrate of a semiconductor device according to a preferred embodiment of the present invention. 
           [0011]      FIG. 5  illustrates a perspective view of a substrate of semiconductor device according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Referring to  FIGS. 1-4 ,  FIGS. 1-4  illustrate a method for fabricating substrate of a semiconductor device according to a preferred embodiment of the present invention. As shown in  FIG. 1 , a first silicon layer  12  is provided, a dielectric layer  14  is then formed on the first silicon layer  12 , and then a second silicon layer  16  is bonded to the dielectric layer  14  to forma silicon-on-insulator (SOI) structure. In this embodiment, the dielectric layer  14  is composed of silicon dioxide, aluminum oxide, or silicon nitride, and each one of the first silicon layer  12  and the second silicon layer  16  is preferably composed single crystal silicon. Preferably, both the first silicon layer  12  and the second silicon layer  16  includes a (100) crystalline orientation and a &lt;100&gt; channel direction before the second silicon layer  16  is bonded to the dielectric layer  14 . 
         [0013]    According to a preferred embodiment of the present invention, the second silicon layer  16  is rotated by 45 degrees before bonding to the dielectric layer  14 , and as a result of the rotation, it is to be noted while the crystalline orientation of the first silicon layer  12  and the second silicon layer  16  both remain at ( 100 ) after the rotation, the channel direction of the second silicon layer  16  is changed from &lt;100&gt; to &lt;110&gt;. In other words, as shown in  FIG. 2 , after bonding the second silicon layer  16  to the dielectric layer  14  and the first silicon layer  12 , the SOI structure preferably consisted of a first silicon layer  12  having crystalline orientation of (100) and channel direction of &lt;100&gt; while the second silicon layer  16  atop having crystalline orientation of (100) and channel direction of &lt;110&gt;. 
         [0014]    Next, as shown in  FIG. 3 , a patterned hard mask  18  is formed on the second silicon layer  16 , and an etching process is conducted by using the patterned hard mask  18  as etching mask to remove part of the second silicon layer  16  and part of the dielectric layer  14  to define a first region  20  and a second region  22  on the first silicon layer  12 , in which the remaining of the second silicon layer  16  after the etching process is on the second region  22 . In this embodiment, the patterned hard mask  18  is preferably composed of silicon nitride or silicon oxide, but not limited thereto. 
         [0015]    After part of the second silicon layer  16  and dielectric layer  14  are removed from the first region  20 , an epitaxial layer  24  is grown in the first region  20  of the first silicon layer  12  while the patterned hard mask  18  is still disposed on the second silicon layer  16 . The growth of the epitaxial layer  24  in the first region  20  is preferably controlled so that the top surface of the epitaxial layer  24  is substantially equal with the top surface of the second silicon layer  16 , and as the epitaxial layer  24  is grown from the first silicon layer  12  having crystalline orientation of (100) and channel direction of &lt;100&gt;, the epitaxial layer  24  would also have the same crystalline orientation and channel direction as the first silicon layer  12 , such as a crystalline orientation of (100) and channel direction of &lt;100&gt;. According to an embodiment of the present invention, the material of the epitaxial layer  24  could be single crystal silicon, or could be selected to accommodate the type of device which will be fabricated afterwards. For instance, if an NMOS device were to be fabricated in the first region  20 , the epitaxial lay  24  is preferably composed of SiC, whereas if a PMOS device were to be fabricated in the first region  20 , the epitaxial layer  24  is preferably composed of SiGe. 
         [0016]    After stripping the patterned hard mask  18 , as shown in  FIG. 4 , a FinFET process could be conducted to first define a plurality of fin-shapes structures  46  in the first silicon layer  12 , the dielectric layer  14 , and the second silicon layer  16  through spacer-image-transfer (SIT) process or other photo-etching processes, and then form elements such as a shallow trench isolations (STIs)  26  around the fin-shaped structures and a plurality of gate structures  28  with spacers  30  on each first region  20  and second region  22 . As the FinFET process is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. 
         [0017]    It should be noted that according to an embodiment of the present invention, in addition to prepare a substrate in the aforementioned embodiment, it would also be desirable to reverse the channel direction of two silicon layers to grow epitaxial layer with reversed channel direction. 
         [0018]    For instance, instead of preparing a substrate with first silicon layer  12  having crystalline orientation of (100) and channel direction of &lt;100&gt; and second silicon layer  16  atop having crystalline orientation of (100) and channel direction of &lt;110&gt; as shown in  FIG. 2 , it would also be desirable to reverse the position of the two silicon layers  12  and  16  by preparing a first silicon layer having crystalline orientation of (100) and channel direction of &lt;110&gt; and a second silicon layer atop having crystalline orientation of (100) and channel direction of &lt;100&gt;, which is also within the scope of the present invention. 
         [0019]    As shown in  FIG. 5 , after a substrate with first silicon layer  32  having crystalline orientation of (100) and channel direction of &lt;110&gt;, a dielectric layer  34 , and a second silicon layer  36  atop having crystalline orientation of (100) and channel direction of &lt;100&gt; is prepared, part of the second silicon layer  36  and dielectric layer  34  is removed from a second region  40  by using a patterned hard mask (not shown) as mask and then an epitaxial layer  42  is grown in the second region  40  in the manner as disclosed in  FIG. 3 . In this embodiment, since the epitaxial layer  42  is grown from the first silicon layer  32  having crystalline orientation of (100) and channel direction of &lt;110&gt;, the epitaxial layer  42  would also have the same crystalline orientation and channel direction as the first silicon layer  32 , such as a crystalline orientation of (100) and channel direction of &lt;110&gt; while the remaining second silicon layer  36  in the first region  38  would have crystalline orientation of (100) and channel direction of &lt;100&gt;. 
         [0020]    Referring again to  FIG. 3 , which further illustrates a substrate of semiconductor device according to a preferred embodiment of the present invention. The substrate includes a first silicon layer  12  having a first region  20  and a second region  22  defined thereon, an epitaxial layer  24  on the first region  20 , a dielectric layer  14  on the second region  22 , and a second silicon layer  16  on the dielectric layer  14 . Preferably, the second silicon layer  16 , the epitaxial layer  24 , and the first silicon layer  12  all have same crystalline orientation, and the epitaxial layer  24  and the second silicon layer  16  have different channel direction while the epitaxial layer  24  and the first silicon layer  12  have same channel direction. For instance, all of the second silicon layer  16 , the epitaxial layer  24 , and the first silicon layer  12  of the preferred embodiment were to have crystalline orientation of (100), and if the epitaxial layer  24  and the first silicon layer  12  were to have channel direction of &lt;100&gt;, the second silicon layer  16  would have channel direction of &lt;110&gt; whereas if the epitaxial layer  24  and the first silicon layer  12  were to have channel direction of &lt;110&gt;, the second silicon layer  16  would have channel direction of &lt;100&gt;. 
         [0021]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.