Abstract:
An internal data processing apparatus and method in a mobile station. A NOR flash memory is replaced with a NAND flash memory as a memory for storing internal data, and a modem is interfaced with the NAND flash memory.

Description:
PRIORITY  
         [0001]    This application claims priority to an application entitled “Apparatus and Method for Interfacing between Modem and Memory in Mobile Station” filed in the Korean Industrial Property Office on Aug. 20, 2001 and assigned Serial No. 2001-50012, and to an application entitled “Apparatus and Method for Interfacing between Modem and Memory in Mobile Station” filed in the Korean Industrial Property Office on Jun. 17, 2002 and assigned Serial No. 2002-33697, the contents of both of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates generally to an apparatus and method for processing internal data in a mobile station (MS), and in particular, to an apparatus and method for interfacing between a modem and a memory.  
           [0004]    2. Description of the Related Art  
           [0005]    An MS serviced only voice calls in its earlier stage of development and now supports a variety of services including data service along with users&#39; growing demands and the advance of communication technology. The various services are a text service, a graphic service, E-mail, voice mail, navigation, transmission of moving pictures, etc.  
           [0006]    The MS is provided with a modem to process data received and data to be transmitted over a wireless network. The modem is usually implemented in the form of a chip and the modem chip is essential to driving the MS. The MS is also provided with a memory for storing data from the above services and information required to operate the MS. Therefore, the MS needs an apparatus for interfacing the modem and the memory to provide the above services.  
           [0007]    A conventional MS uses a NOR flash memory for storing application programs and OS (Operating System) codes. An interfacing structure between interfacing data between a modem and a memory in an MS using a NOR Flash memory is illustrated in FIG. 1.  
           [0008]    Referring to FIG. 1, a chip select signal ROM_CSB, a read enable signal RDB, a write enable signal WRB, an address signal A, and a data signal D are used to interface data between a modem  110  and a NOR flash memory  112 . A chip select signal (RAM_CSB) is additionally used to interface between the modem  110  and a working memory  114 .  
           [0009]    Referring to FIG. 1, the modem  110  processes data received or data to be transmitted over a wireless network. Upon generation of data for data transmission/reception over the wireless network, the modem  110  also stores the data in a NOR flash memory  112 . The modem  110  reads data for transmission over the wireless network from the NOR flash memory  112 . When the MS is powered-on, the modem  110  accesses basic codes required for initialization, such as boot codes, a vector table, and load codes through the NOR flash memory  112 . The NOR flash memory  112  stores application programs and OS codes needed in the MS. The working memory  114  temporarily stores application programs required for the modem  110  to process predetermined data and provide a particular service, and can be accessed when necessary. The working memory  114  can be, for example, an SRAM or an UtRAM. For example, after the initialization of the MS, the modem  110  reads the OS codes and a call software from the NOR flash memory  112  and copies them in the working memory  114 . Then the modem  110  accesses the working memory  114 . The reason for copying data from the NOR flash memory  112  to the working memory  114  is that data can be accessed more rapidly in the working memory  114  due to a short access time of the SRAM used as the working memory  114 . The modem  110  reads or writes application data directly from or into the NOR flash memory  112 . When necessary, the modem  110  copies the application data in the working memory  114 .  
           [0010]    To write data in the NOR flash memory  112 , the modem  110  enables the NOR flash memory  112  by the chip select signal ROM_CSB, designates a predetermined address by the address signal A during enabling the write enable signal WRB, and provides data to the NOR flash memory  112  by the data signal D at the same time. The NOR flash memory  112  is enabled by the chip select signal ROM_CSB and upon receipt of the address signal A and the data signal D for the period of enabling the write enable signal WRB, it stores the data represented by the data signal D in an area designated by the address signal A.  
           [0011]    To read data from the NOR flash memory  112 , the modem  110  enables the NOR flash memory  112  by the chip select signal ROM_CSB and receives the data signal D from the NOR flash memory  112  by the address signal A during enabling of the read enable signal RDB. The NOR flash memory  112  is enabled by the chip select signal ROM_CSB, reads data from a memory area designated by the address signal A received from the modem  110  during enabling of the read enable signal RDB, and transmits the data signal D to the modem  110 .  
           [0012]    To write data in the working memory  114 , the modem  110  enables the working memory  114  by the chip select signal RAM_CSB and upon receipt of the address signal A and the data signal D during enabling the write enable signal WRB, it stores the data signal D representing data in a memory area designated by the address signal A.  
           [0013]    To read data from the working memory  114 , the modem  110  enables the working memory  114  by the chip select signal RAM_CSB and receives the data signal D from the working memory  114  by the address signal A during enabling the read enable signal RDB. The working memory  114  is enabled by the chip select signal RAM_CSB, reads data from a memory area designated by the address signal A during enabling of the read enable signal RDB, and transmits the data signal D to the modem  110 .  
           [0014]    A memory capacity of 16 or 32 Mbit is sufficient for services provided from an MS at present. However, considering the rapid growth of the communications market, various MS services, advanced functions, high capacity, and the resulting increase in data file size, a memory capacity requirement is 64/128 Mbit or larger.  
           [0015]    It is impossible to provide inexpensive NOR flash memories with an increased memory speed requirement in view of its structure. Moreover, the drastically growing demands for NOR flash memories add to the difficulty with supplying parts for manufacture of NOR flash memories. In this context, NAND flash memories may become more widely used as memories for MSs because they can be provided at cheap prices.  
           [0016]    In a comparison between a NOR flash memory and a NAND flash memory with the same capacity, the former is 3.56 dollars per mega byte and the latter is 0.83 dollars per mega byte. It is expected that the NOR flash memory and the NAND flash memory will be 3.06 and 0.6 dollars, respectively in 2002.  
           [0017]    In terms of density, a NAND flash memory of 512 Mbit corresponds to a 64-Mbit NOR flash memory is. In 2002, a NAND flash memory of 1024 Mbit will correspond to a 128-Mbit NOR flash memory.  
           [0018]    It can therefore be concluded that the NAND flash memory is better than the NOR flash memory in terms of cost and density. Therefore, NOR flash memories have reached their limits of use in MSs.  
         SUMMARY OF THE INVENTION  
         [0019]    It is, therefore, an object of the present invention to provide an MS using a NAND flash memory.  
           [0020]    It is another object of the present invention to provide an apparatus and method for interfacing data between a modem and a NAND flash memory in an MS.  
           [0021]    To achieve the above and other objects, there are provided an apparatus and method for interfacing data between a modem and a NAND flash memory in an MS. In an interface circuit between the NAND flash memory and the modem, a working memory has a capacity smaller than the capacity of the NAND flash memory, copies part of the information stored in the NAND flash memory therein, has second addresses different from the first addresses of the NAND flash memory. A programmable memory has basic codes required to copy the part of the information stored in the NAND flash memory to the working memory. A controller is connected to the programmable memory, for controlling random reading of the information stored in the working memory using the second addresses.  
           [0022]    To write data in the NAND flash memory, a write command is transmitted to the NAND flash memory by enabling a second chip select signal for activating the NAND flash memory and a command latch enable signal when the modem enables a first chip select signal and the write command. A write address is transmitted to the NAND flash memory by disabling the command latch enable signal and enabling an address latch enable signal and writing data from the modem in the NAND flash memory. An error correction code for the data is generated in an error correction code generator by disabling the address latch enable signal and a third chip select signal. The error correction code is transmitted to the NAND flash memory by disabling the third chip select signal and enabling the second chip select signal for activating the NAND flash memory, and written in the NAND flash memory. Then, the second chip select signal is disabled.  
           [0023]    To read data from the NAND flash memory, a read command is transmitted to the NAND flash memory by enabling a second chip select signal for activating the NAND flash memory and a command latch enable signal when the modem enables a first chip select signal and the read command. A read address is transmitted to the NAND flash memory by disabling the command latch enable signal and enabling an address latch enable signal, and data at the read address and an error correction code for the data is read. An error correction code for the data is generated in the error correction code generator by disabling the address latch enable signal and a third chip select signal. When the third chip select signal is disabled, it is determined whether the read data has errors by comparing the read error correction code with the generated error correction code. If it is determined that the read data has errors, the errors are corrected. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:  
         [0025]    [0025]FIG. 1 is a block diagram of a conventional apparatus for interfacing between a modem and memories in an MS;  
         [0026]    [0026]FIG. 2 is a block diagram of an apparatus for interfacing between a modem and a memory unit in an MS according to an embodiment of the present invention;  
         [0027]    [0027]FIG. 3 is a block diagram of an NFC (NAND Flash Controller) illustrated in FIG. 2;  
         [0028]    [0028]FIG. 4 is a flowchart illustrating data writing from the modem to the memory unit in the MS according to the embodiment of the present invention;  
         [0029]    [0029]FIG. 5 is a flowchart illustrating data reading from the memory unit to the modem in the MS according to the embodiment of the present invention;  
         [0030]    [0030]FIG. 6 illustrates part of a combination logic illustrated in FIG. 3;  
         [0031]    [0031]FIG. 7 is a timing diagram for an interfacing apparatus having the combination logic illustrated in FIG. 6;  
         [0032]    [0032]FIG. 8 is a detailed circuit diagram of another embodiment of the combination logic; and  
         [0033]    [0033]FIG. 9 is a timing diagram for signals input to an ECC (Error Correction Code) generator when the combination logic illustrated in FIG. 8 is used. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0034]    Preferred embodiments of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.  
         [0035]    In order to replace a NOR flash memory with a NAND flash memory according to the present invention, the following aspects are generally addressed.  
         [0036]    (1) When an MS is initially power-on, a modem randomly accesses basic codes including a vector table, boot codes, and load codes for initialization. In the case of a conventional NOR flash memory, it does not matter that the basic codes are in the NOR flash memory allowing random access. However, since a NAND flash memory according to the present invention does not allow random access, a device for allowing random access to the basic codes is required (2) A NAND flash memory controller is required, which controls the NAND flash memory according to a command from the modem and reports the control status of the NAND flash memory to thereby enable the modem to access the NAND flash memory.  
         [0037]    [0037]FIG. 2 illustrates an apparatus for interfacing between a modem and a memory unit according to an embodiment of the present invention, which satisfies the above aspects. As illustrated, the interfacing apparatus is comprised of a modem  210 , a memory unit  230 , and an interface  220  for interfacing between the modem  210  and the memory unit  230 .  
         [0038]    Referring to FIG. 2, the interface  220  includes an NFC  222 , a mask ROM (Read Only Memory)  224 , and an error correction code (ECC) generator  226 . The modem  210  can access the mask ROM  224  randomly. Therefore, the mask ROM  224  stores basic data required for initialization, such as a vector table, boot codes, and load codes, thereby obviating the need for a NOR flash memory or refresh. The basic data of mask ROM  224  is program data by which data is copied from a NAND flash memory  232  to a working memory  234 .  
         [0039]    The ECC generator  226  receives data transmitted between the modem  210  and the memory unit  230  and generates a parity code ECCDATAL[7:0], ECCDATAH[7:0], and ECCDATAX[7:0] for the input data. The parity code is used for bit error check and correction in the modem  210 . The mask ROM  224  is enabled by a chip select signal ROM 1 _CSB from the modem  210  and outputs data D[15:0] to the modem  210  according to an address signal A[13:1]. The NFC  222  controls the memory unit  230  so that the modem  210  can write or read data in or from the memory unit  230 . That is, the NFC  220  controls the memory unit  230  by signals NFROM_CSB, CLE, ALE, NAND_WRB, and NAND_RDB according to commands ROM 2 _CSB, GP_CSB, WRB and RDB received from the modem  210 . These signals and commands are described further below. The NFC  220  also reports the current control status of the memory unit  230  to the modem  210  and transmits a parity code generated from the ECC generator  226  to the modem  210 .  
         [0040]    The memory unit  230  includes the NAND flash memory  232  and the working memory  234 . The NAND flash memory  232  writes or reads data under the control of the NFC  222 . The working memory  234  temporarily stores data received from the modem  210  to allow fast data access for the modem  210 .  
         [0041]    Now, signals related with the interface  220  will be defined below.  
         [0042]    With regard to signals input to the interface  220 , ROML_CSB is a chip select signal that enables the mask ROM  224 . ROM 2 _CSB is a chip select signal input to the NFC  222  that is enabled when the NFC  222  accesses the ECC generator  226 , the NAND flash memory  232 , or the working memory  234 . GP_CSB is a chip select signal input to the NFC  222  and enabled when the NFC  222  accesses the ECC generator  226  or the NAND flash memory  232 . A[13:1] is an address bus signal. RDB is enabled for the modem  210  to read data from the NAND flash memory  230 , the working memory  234 , the ECC generator  226 , or the NFC  222 . WRB is enabled for the modem  210  to write data in the NAND flash memory  230 , the working memory  234 , the ECC generator  226 , or the NFC  222 . D[15:0] is a data bus signal.  
         [0043]    With regard to signals output from the interface  220 , ALE (Address Latch Enable Signal) is enabled to write an address in a data bus when the NAND flash memory  232  is accessed. CLE (Command Latch Enable Signal) is enabled to write a command in the data bus when the NAND flash memory  232  is accessed. The command can be defined according to the NAND flash memory  232 . NFROM_CSB is a chip select signal enabled for the NFC  222  to access the NAND flash memory  232 . NAND_WRB is enabled when the NFC  222  writes data in the NAND flash memory  232 . NAND_RDB is enabled when the NFC  222  reads data from the NAND flash memory  232 .  
         [0044]    With regard to internal signals in the interface  220 , the NFC  222  enables the ECC generator  226  by ECC_START to generate a parity code. ECC_RCE is a chip select signal enabled to read a parity code upon request from the NFC  222 . ECCDATAL[7:0], ECCDATAH[7:0], and ECCDTAX[7:0] are signals representing a parity code generated from the ECC generator  226  upon request from the NFC  222 .  
         [0045]    Aside from the above signals, RBB is a signal representing the status of the NAND flash memory, that is, a ready state or a busy state. The modem  210  is not allowed to access data when the NAND flash memory  232  is busy. In other words, data access is available only when the NAND flash memory  232  is ready. The modem  210  determines the current status of the NAND flash memory  232  by the signal RBB received through a general purpose inputloutput pin GPIO_INT for interfacing the modem  210  with external devices. RAM_CSB is a chip select signal enabled when the modem  210  accesses the working memory  234 . When the NFC  222  does not access the NAND flash memory  232 , the signal ROM 2 _CSB can be connected to RAM_CSB.  
         [0046]    Since basic codes for initialization are stored in the mask ROM  224 , the modem  210  boots up using the basic codes read from the mask ROM  224  at initial power-on. After initialization, the modem  210  reads OS codes and a call software from the NAND flash memory  232  and copies them in the working memory  234 . Then, the modem  210  accesses the working memory  234 . The reason for copying data from the NAND flash memory  232  to the working memory  234  is the short access time of an SRAM or UTRAM used as the working memory  234 . While the modem  210  directly reads or writes application data from or in the NAND flash memory  232 , it can copy the application data in the working memory  234  when necessary.  
         [0047]    [0047]FIG. 3 is a detailed block diagram of the NFC  222  illustrated in FIG. 2. Referring to FIG. 3, when the chip select signal GP_CSB and the write enable signal WRB received from the modem  210  are enabled and a particular address and data are written in the address bus signal A and the data bus signal D, respectively, they control signals output through terminals Q 0  to Q 4  in a first register group. Mux_Select is output through the terminal Q 3 . If Mux_Select is set to 0, the signals CLE, ALE, NFROM_CSB, NAND_WRB, and NAND_RDB related with the NAND flash memory  232  and the signal ECC_RCE related with the ECC generator  226  are controlled by a first combination logic and the first register group. On the other hand, if Mux_Select is set to 1, the signals CLE, ALE, NFROM_CSB, NAND_WRB, NAND_RDB, and ECC_RCE are controlled by a second combination logic and a second register group. That is, the NAND flash memory  232  and the ECC generator  226  are controlled by the use of the first combination logic and the first register group, or the second combination logic and the second register group.  
         [0048]    A description will be made below of the operation of the interfacing apparatus according to the embodiment of the present invention. The operation can be considered in terms of data writing and data reading in and from the NAND flash memory  232 .  
         [0049]    [0049]FIGS. 4 and 5 are flowcharts illustrating control operations in the NFC  222  for reading and writing data from and into the NAND flash memory  232 , respectively.  
         [0050]    Referring to FIG. 4, the NFC  222  receives a data write request from the modem  210  in step  410 . The modem  210  requests data writing using the address bus signal A, the data bus signal D, the write enable signal WRB, and the chip select signal GP_CSB or ROM 2 _CSB.  
         [0051]    In step  412 , the NFC  222  enables the chip select signal NFROM_CSB for accessing the NAND flash memory  232  and the signal CLE for transmitting a data write command to the NAND flash memory  232 . The NAND flash memory  232  is enabled by the NFROM_CSB and prepares for receiving a command from the NFC  222  in response to the signal CLE. The NFC  222  transmits to the NAND flash memory  232  a write command ( 80 H) by the data bus signal D[7:0] in step  414 . The NAND flash memory  232  then awaits receipt of an address and data to write. Meanwhile, the NFC  222  disables the signal CLE and enables the signals NFROM_CSB and ALE for accessing the NAND flash memory  232  and transmitting the address, respectively, in step  416 .  
         [0052]    In step  418 , the NFC  222  transmits the address at which data is to be written by the data bus signal D[7:0]. The NFC  222  then disables the signal ALE and enables the signal ECC_START for generating a parity code in the ECC generator  226  in step  420 .  
         [0053]    The modem  210  transmits intended write data by the data bus signal D[15:0]. The data is written at the designated address in the NAND flash memory  232 . The data is also fed to the ECC generator  226  and the ECC generator  226  generates a parity code ECDATAL[7:0], ECDATAH[7:0], and ECDATAX[7:0] for the received data.  
         [0054]    The modem  210  enables the signal ECC_RCE through the NFC  222  to read the parity code ECDATAL[7:0], ECDATAH[7:0], and ECDATAX[7:0] in step  422 . The NFC  222  disables the signal ECC_START and enables the signal NFROM_CSB to write the parity code in the NAND flash memory  232  in step  424 . Subsequently, the modem  210  transmits the parity code by the data bus signal D[7:0] in step  426 . The parity code is stored in a predetermined area of the NAND flash memory  232 .  
         [0055]    The NFC  222  enables the signal CLE in step  428  and transmits a check command ( 10 H) for determining whether the data writing is successful by the data bus signal D[7:0] in step  430 . The NFC  222  disables the signal CLE in step  432 .  
         [0056]    Upon receipt of the check command, the NAND flash memory  232  transmits information about its current status by a data bus signal D[6]. The current status is a busy state or an idle state. Even though it does not receive the check command, the NAND flash memory  232  always reports its current status to the modem  210  by the signal RBB. The NAND flash memory  232  notifies the NFC  222  whether the data writing is successful by a data bus signal D[0].  
         [0057]    The modem  210  determines the status of the NAND flash memory  232  by the data bus signal D[6] or RBB in step  434 . If the NAND flash memory  232  is in an idle state, the modem  210  determines whether errors have been generated during the data writing by the data bus signal D[0] in step  436 . If the data writing is successful, the NFC  222  disables the signal NFROM_CSB and ends the data writing. On the other hand, in the case of a data writing failure, the NFC  222  disables the signal NFROM_CSB and returns to step  410 .  
         [0058]    Referring to FIG. 5, the NFC  222  receives a data read request from the modem  210  in step  510 . The modem  210  requests data reading using the address bus signal A, the data bus signal D, the read enable signal RDB, and the chip select signal GP_CSB or ROM 2 _CSB.  
         [0059]    In step  512 , the NFC  222  enables the chip select signal NFROM_CSB for accessing the NAND flash memory  232  and the signal CLE for transmitting a data read command to the NAND flash memory  232 . The NAND flash memory  232  is enabled by the NFROM_CSB and prepares for receiving a command from the NFC  222  in response to the signal CLE. The NFC  222  transmits to the NAND flash memory  232  a data read command (00H) by the data bus signal D[7:0] in step  514 . The NAND flash memory  232  then awaits receipt of an address. Meanwhile, the NFC  222  disables the signal CLE and enables the signal ALE for transmitting the address in step  516 .  
         [0060]    In step  518 , the NFC  222  transmits the address from which data is to be read by the data bus signal D[7:0]. The NFC  222  then disables the signal ALE in step  520 . Upon receipt of the data read command and the address, the NAND flash memory  232  transmits information about its current status by a data bus signal D[6] or the signal RBB. The current status is a busy state or an idle state. In the idle state, the NAND flash memory  232  reads data from the address and transmits it by the data bus signal D[7:0].  
         [0061]    The modem  210  determines the status of the NAND flash memory  232  by the data bus signal D[6] or the signal RBB in step  524 . If the NAND flash memory  232  is in an idle state, the modem  210  enables the signal ECC_START for generating a parity code for the read data in step  524 . The ECC generator  226  generates a parity code ECCDATAL[7:0], ECCDATAH[7:0], and ECCDATAX[7:0] for the read data.  
         [0062]    The modem  210  reads the parity code from the ECC generator  226  by enabling the signal ECC_RCE through the NFC  222  in step  526  and disables the signal ECC_START through the NFC  222  in step  528 . In step  530 , the modem  210  reads a parity code corresponding to the read data from the NAND flash memory  232 . Then the modem −210  disables the signal NFROM_CSB in step  532 .  
         [0063]    The modem  210  compares the generated parity code with the read parity code in step  534  and determines whether the read data has errors according to the comparison result in step  536 . If the parity codes are different, the modem  210  determines that the read data has errors. If they are identical, the modem  210  determines that no errors are in the read data.  
         [0064]    If the modem  210  determines that the read data has no errors in step  536 , it ends the data reading operation, and otherwise, it corrects errors in step  538  and ends the data reading operation.  
         [0065]    As described above, data is written in a data area of the NAND flash memory  232 . For the data writing, the ECC generator  226  generates a parity code for the data. The modem  210  writes the parity code in the NAND flash memory  232 . In a data reading operation, data read from the NAND flash memory  232  is fed to the ECC generator  226 . The ECC generator  226  generates a new parity code for the read data. The modem  210  compares the new parity code with a parity code corresponding to the read data, as stored in the NAND flash memory  232 . According to the comparison result, the modem  210  determines whether the read data has errors. If it does, the errors are corrected.  
         [0066]    Meanwhile, when power is initially on, the modem  210  reads the basic codes from the mask ROM  224  to perform initialization. The initialization operation will be described with reference to FIG. 2.  
         [0067]    At initial power-on, the modem  210  enables the chip select signal ROM 1 _CSB to access the mask ROM  224 . The mask ROM  224  is enabled by ROM 1 _CSB and awaits a command from the modem  210 . The modem  210  provides the mask ROM  224  with an address at which the basic data is stored by the address bus signal A[13:1]. Then the mask ROM  224  reads the-basic codes at the address and transmits them by the data bus signal D[15:0]. The modem  210  performs initialization according to the basic codes.  
         [0068]    As stated before, the modem  210  copies data read from the NAND flash memory  232  in the working memory  234 , for fast access.  
         [0069]    To do so, the modem  210  enables the chip select signal RAM_CSB to access the working memory  234  via terminal CE 1 . If the modem  210  does not access the NAND flash memory  232 , the signal ROM 2 _CSB can be used instead of the signal RAM_CSB. The working memory  234  is activated by the signal RAM_CSB and awaits receipt of a command from the modem  210 . When the modem  210  intends to copy OS codes and a call software read from the NAND flash memory  232  in the working memory  234 , it enables the write enable signal WRB. On the contrary, to read the OS codes and the call software from the working memory  234 , the modem  210  enables the read enable signal RDB. The signal WRB is fed to the working memory  234  through a terminal OE and the signal RDB, to the working memory  234  through a terminal WE. When the terminal OE is enabled, the working memory  234  awaits receipt of an address and data such as OS codes, a call software, etc. from the modem  210 . The working memory  234  receives the address by an address bus signal[21:1] and data by the data bus signal[15:0], and writes the data at the address.  
         [0070]    If the working memory  234  is activated and then the terminal WE is enabled, the working memory  234  awaits receipt of an address from the modem  210 . Upon receipt of the address by the address bus signal[21:1], it reads data at the address and transmits it to the modem  210  by the data bus signal D[15:0].  
         [0071]    Referring back to FIG. 3, for the input of signals from the modem  210 , A[13:1], D[15:0], GP_CSB, WRB, RDB, and ROM 2 _CSB, the NFC  222  outputs signals required for data writing or data reading in or from the NAND flash memory  232 , CLE, ALE, ECC_RCE, NFROM_CSB, GP_CSB_OUT, NAND_WRB, and NAND_RDB.  
         [0072]    The signals GP_CSB and WRB are fed to a terminal CK of the first register group through an AND gate. The first register group outputs the signal Mux_Select through the terminal Q 3  as an enable signal for multiplexers (MUXes) that multiplex the signals CLE, ALE, ECC_RCE, NFROM_CSB, GP_CSB_OUT, NAND_WRB, and NAND_RDB. The first register group controls the signals CLE, ALE, ECC_RCE, and NFROM_CSB according to the signals A[13:0] and D[15:0] using the first combination logic. Signals A[12], and A[13] and the chip select signal GP_CSB are applied to the input of a second combination logic. The second combination logic generates the signals CLE, ALE, ECC_RCE, and NFROM_CSB. The signal GP_CSB_OUT is used as an interface signal for the NAND flash memory  232  or an LCD module (not shown). When the signal GP_CSB is enabled and both signals A[10] and A[13] are 1, the signal GP_CSB_OUT is enabled and used as a chip select signal.  
         [0073]    [0073]FIG. 6 illustrates the second combination logic illustrated in FIG. 3. Referring to FIG. 6, the combination logic is constructed in the form of a flip-flop (F/F). A first inverter NOT 1  inverts an address signal A[12]. A first OR gate OR 10 R-gates the output of the first inverter NOT 1  and the chip select signal GP_CSB. A third OR gate OR 30 R-gates the output of the first OR gate OR 1  and the write enable signal WRB. The output of the third OR gate OR 3  is fed as a clock signal MSM_CLK to the register group.  
         [0074]    A second inverter NOT 2  inverts an address signal A[13]. A second OR gate OR 20 R-gates the output of the second inverter NOT 2  and the chip select signal GP_CSB. A fourth OR gate OR 40 R-gates the output of the second OR gate OR 2  and the write enable signal WRB. A fifth OR gate OR 5  OR-gates the output of the second OR gate OR 2  and the read enable signal RDB. The outputs of the fourth and fifth OR gates OR 4  and OR 5  become a NAND flash memory write signal NAND_WRB and a NAND flash memory read signal NAND_RDB, respectively.  
         [0075]    [0075]FIG. 7 is a timing diagram for the NFC  222  having the combination logic illustrated in FIGS. 3 and 6. With reference to FIG. 7, the timings of read and write signals will be described.  
         [0076]    When data writing is requested, the chip select signal GP_CSB is enabled low at time t0. The signal WRB is enabled low for one clock period from the falling edge of time t1. This corresponds to transition from step  410  to step  412  in FIG. 4, or from step  510  to step  512  in FIG. 5. That is, step  410  or  510  is satisfied since the signals GP_CSB and WRB are enabled. At time t2, the signal CLE is enabled high and the signal NFROM_CSB is transitioned to be low. That is, step  412  or  512  is performed. Then between the falling edge of time t1 and the falling edge of time t7, a read command or a write command is output as an interface output I/O, as in step  414  or  514 . After the read command or the write command is output, the signals CLE and ALE for enabling transmission of the commands are both disabled at the falling edge of time t7.  
         [0077]    Then, a read address or a write address is output. The ECC generator  226  must be activated before writing data or reading data because of high error rate during data writing or data reading in or from the NAND flash memory.  
         [0078]    To transmit a start command to the ECC generator  226 , the signal GP_CSB is enabled at the rising edge of time t8 and the signal WRB is enabled at the falling edge of time t19. Therefore, at the falling edge of time t19, the signal NFROM_CSB transitions from low to high and the signal ECC_RCE transitions from high to low. Thus from time t20 to time t25, the start command is delivered to the ECC generator  226 . Then, a data read command or a data write command is executed.  
         [0079]    As noted from FIG. 7, two clock pulses are lost before and after delivering a command signal, respectively. It is because after the write clock signal MSM_CLK is generated using the address signal A[12] and the signal GP_CSB, it acts as a flipflop clock signal and thus produces the signals ALE, CLE, NFROM_CSB, and ECC_RCE according to input data. In addition, with the address signal A[13] and the signal GP_CSB, the signals NAND_WRB and NAND_RDB are generated. Thus, the two-clock pulse loss occurs before and after transmission of each command.  
         [0080]    [0080]FIG. 8 is a detailed circuit diagram of another embodiment of the combination logic according to the present invention. Referring to FIG. 8, the chip select signal GP_CSB is fed to a first OR gate OR 1 , a second OR gate OR 2 , and a second inverter NOT 2 . The second inverter NOT 2  inverts the signal GP_CSB. A first AND gate AND 1  AND-gates the address signal A[12] and the output of the second inverter NOT 2  and outputs a signal NAND_CLE. A second AND gate AND 2  AND-gates the address signal A[11] and the output of the second inverter NOT 2  and outputs a signal NAND_ALE.  
         [0081]    Meanwhile, a first inverter NOT 1  inverts the address signal A[13]. The first OR gate OR 1  OR-gates the signal GP_CSB and the output of the first inverter NOT 1  and outputs a signal NAND_CSB. The second OR gate OR 2  OR-gates the signal GP_CSB and the address signal A[10] inverted in a third inverter NOT 3  and outputs a signal ECC_RCE.  
         [0082]    [0082]FIG. 9 is a timing diagram for signals input to the ECC generator  226  in the interface  220  having the combination logic illustrated in FIG. 8.  
         [0083]    As compared to the signal timings illustrated in FIG. 7, no two-clock delay occurs before and after delivery of a command signal utilizing the property of the signal GP_CSB. That is, it is because the signals ECC_RCE, ALE, CLE, and NFROM_CSB are generated using signal pairs of GP_CSB and A[12], and GP_CSB and A[13], and this combination logic does not utilize a flip-flop.  
         [0084]    In accordance with the present invention as described above, a high-capacity, cheap NAND flash memory substitutes for a NOR flash memory that imposes constraints in terms of cost, capacity, and supply in an MS. Therefore, the MS is improved in cost and performance.  
         [0085]    While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.