Abstract:
A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. Thus, resolution is better than that provided by digital elements alone. This circuit also automatically cancels errors due to capacitance variations and unit current variation of the DAC introduced during the manufacturing process. In another embodiment a single capacitor is used in combination with two current DACs and a comparator to provide a controllable time delay.

Description:
This application is a continuation of application Ser. No. 08/536,982, filed Sep. 29, 1995, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a time delay circuit and method and more particularly to a circuit for creating a controllable time delay used in phase shifting a digital signal. 
     Data phase alignment circuitry, digital phase locked loops (PLL) and other digital circuits utilize variable time delay circuitry to achieve digital signal phase alignment, phase offset or sampling timing. One approach used for variable time delay is digital variable time delay circuitry that contains a programmable counter. The resolution of such circuits is generally limited by the clock speed. Increasing the frequency of the clock increases resolution, but the clock frequency is limited by the speed of the digital circuits. Also, the high frequency clock generally increases power consumption. 
     Another approach used for variable time delay utilizes an analog PLL with a ring oscillator containing M stages. Such an approach is illustrated in FIG. 1. Referring to FIG. 1, the analog PLL 10 locks to the reference signal 11 or data rate signal. The analog PLL 10 maintains the frequency as N* the data rate and generates M*N phases from the outputs of ring oscillator 12. Thus, the resolution is M*N using N* the data rate clock frequency. Increasing the number of stages M, increases the resolution since the resolution of this approach is limited by stage number M and the speed of phase selector 13. Typically, the delay of each path of phase selector 13 must be the same and increasing M makes the path matching difficult. When using the analog PLL approach, phase selector 13 can make narrow pulses when making large phase changes. Because the phase selector 13 and a divider 14 condition these pulses, the phase selector 13 and the divider 14 must work at much higher frequency than the N* data rate frequency. The speed limits of the phase selector 13 and divider 14 thus limit the resolution in this typical digital variable phase shift circuitry approach. 
     Thus, previous techniques have resolution limited by digital element speed and it would be desirable to have a variable time delay that achieves high resolution beyond the speed limitations described above. 
     SUMMARY OF THE INVENTION 
     A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. To begin, the current DAC, which is set to provide current M, is used to charge up the threshold level capacitor for one clock time interval T to provide a desired threshold level. After charging, the voltage of the threshold level capacitor will be proportional to the DAC value M and charging time T. Then, the current DAC is set to another value F to charge up the ramping capacitor. During charging, the voltage of the ramping capacitor is ramping at a rate determined by DAC value F and charging time t. The comparator transitions when both capacitance voltages are the same. The delay time from the start time of the charging of the ramping capacitor will be determined by the equation M/F*T. The phase shift resolution is defined by the resolution of the current DAC times the clock period T divided by the reference signal cycle. If F is full scale and N is the clock multiplier of the reference clock, then the phase shift resolution is F*N. Clock speed T is limited by digital element speed, but the full scale value F is not limited by digital element speed. Thus, the resolution of the present invention is better than that provided by digital elements alone. 
     The circuitry of the present invention also automatically cancels errors due to capacitance voltage coefficient and full scale current variation of the DAC introduced during the manufacturing process. 
     Thus, the present invention provides a time delay free from the deleterious effects of capacitance absolute value and capacitance voltage coefficient, and free from the deleterious effects of low frequency variation or drift in the current DAC, as well as the effects of DAC current variation and capacitor value variation resulting from the manufacturing process. 
     In accordance with another embodiment of the invention, a single capacitor is used in combination with a pair of current DACs and a comparator to provide a controllable time delay. In this embodiment, one DAC is controlled to charge the capacitor at a controllable rate, and the other DAC is used to discharge the capacitor at a controllable rate. The resultant capacitor voltage is a saw-tooth waveform that is then compared to a predetermined threshold voltage by the comparator to produce the desired time delay. 
     The invention includes three basic elements (capacitor, current DAC and comparator) that are used to determine a desired time delay in such a way that the absolute values of the charging currents and capacitance do not affect the resolution or value of the desired time delay. The comparator delay is rendered consistent by using the full scale value of the DAC to charge the ramping capacitor, and the DAC and capacitance variations are canceled by using similar construction, or by using a single element. The circuit configuration of the present invention eliminates the need for calibration, and renders the determination of time delay insensitive to variations in power supply, temperature, manufacturing process, and low frequency drifts in DAC current. 
     In general, the variable-time delay circuit of the present invention, comprises: a first controllable current source; a first capacitor, connected to the first controllable current source, to provide a ramping voltage as a function of the first controllable current source; a comparator connected to the first capacitor, for comparing the ramping voltage with a threshold voltage, and for providing an output signal indicative of a desired time delay; and a control block, connected to the controllable current source and the first capacitor, for controlling the desired time delay by varying an amount of current applied by the controllable current source, and by controlling an initiation time for the charging of the first capacitor. 
     The invention may further comprise, a second capacitor, connected to the controllable current source and to the comparator, for providing a threshold voltage to the comparator, the control block additionally controlling the controllable current source to charge the second capacitor to provide a desired threshold voltage to the comparator. 
     The controllable current source preferably comprises, a current digital-to-analog converter. 
     The invention may further comprise, controllable switch means, controlled by the control block, for selectively connecting the controllable current source to the first capacitor to initiate charging of the first capacitor. When two capacitors are used, the controllable switch means is also controlled by the control block to selectively connect the controllable current source first to one capacitor to establish the threshold voltage, and then to the other capacitor to initiate the ramping voltage. 
     In accordance with an alternate embodiment of the invention a second controllable current source is connected to the first capacitor and is controlled by the control block, for controllably discharging the first capacitor after it has been charged by the first controllable current source. In this case, the ramping voltage is a saw-tooth waveform. 
     The method of the present invention comprises: establishing a threshold voltage; controllably charging a capacitor to produce a ramp voltage beginning at a charging initiation time; and comparing the ramp voltage to the threshold voltage to produce a controllable time delay between the ramp initiation time, at a time when the ramp voltage and the threshold voltage substantially equal one another. 
     The method may further comprise establishing the threshold by controllably charging a second capacitor to produce the threshold voltage. 
     These and other features and advantages of the present invention will become apparent to those of skill in this technology with reference to the following detailed description and appended drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a prior art time delay circuit. 
     FIG. 2A is a high resolution time delay circuit in accordance with a first embodiment of the present invention. 
     FIG. 2B is a timing chart illustrating the coarse time delay control of the present invention. 
     FIG. 3 is a set of signal timing charts illustrating one mode of operation of the circuit of FIG. 2A. 
     FIG. 4 is a set of signal timing charts illustrating another mode of operation of the circuit of FIG. 2A. 
     FIGS. 5A and 5B illustrate another embodiment of the present invention. 
     FIGS. 6A and 6B illustrate yet another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     An embodiment of a high resolution variable time delay circuit according to the present invention is illustrated in FIG. 2A. The time delay circuit includes a current DAC 21, switches 22, 23, 24 and 25, capacitors 26 and 27, comparator 28 and control block 29. Current DAC 21 is connected to switches 22, 23 which control DAC current flow to threshold level capacitor 26 or ramping capacitor 27. Threshold level capacitor 26 has a first terminal 30 connected to switch 22 and a second terminal connected to ground line 32. It should be noted that the second terminal of threshold level capacitor 26 may be connected to a constant voltage line, other than ground, if desired. Switch 24 is connected between the first terminal 30 of capacitor 26 and constant voltage line 33. It should be noted that constant voltage line 33 may be at ground or may be at a constant voltage other than ground, the voltage of the constant voltage line 33 being the desired initial voltage condition of capacitor 26. Ramping capacitor 27 has a first terminal 31 connected to switch 23 and a second terminal connected to ground line 32. It should be noted that the second terminal of ramping capacitor 27 may be connected to a constant voltage line other than ground if desired. Switch 25 is connected between first terminal 31 of capacitor 27 and constant voltage 33. Once again, it is noted that constant voltage line 33 may be at ground or may be at a constant voltage other than ground, the voltage of the constant voltage line 33 being determined by the desired initial voltage condition of capacitor 27. 
     Although the second terminals of capacitors 26, 27 are shown connected to a common voltage line 32, and switches 24, 25 are shown connected to a common voltage line 33, these may all be connected to a single voltage line or may all be connected to separate voltage lines, without departing from the scope of the invention. 
     Comparator 28 compares the voltages appearing on terminals 30 and 31 to produce a delayed pulse. Control block 29 controls DAC 21 and all switches 22, 23, 24, 25 to produce a delayed pulse according to the time delay command applied to command block 29. 
     Control block 29 receives a phase shift command which is generated in a known manner and which comprises up and down (advance and delay) phase shift information derived from two signals that are phase shifted relative to one another. Control block 29 accumulates the phase shift information in a known manner by, for example, incrementing or decrementing a value stored in an accumulator register depending upon whether the phase shift command indicates a phase advance or delay. 
     Control block 29 then outputs the appropriate value for DAC 21 (for example, the value stored in the accumulator), and outputs the control signals for switches 22, 23, 24, 25, in accordance with predetermined timing, illustrated, for example, in FIGS. 3 and 4. 
     If the accumulator within control block 29 reaches a minimum value, control block 29 shifts the start time of the ramping capacitor 27 (corresponding to the closure of switch 23), from the previous start time to one T cycle ahead. Conversely, if the accumulator within control block 29 reaches a maximum value, control block 29 shifts the start time of the ramping capacitor 27 (corresponding to the closure of switch 23), from the previous start time to one T cycle delayed. This coarse control of delay time is illustrated by the timing charts shown in FIG. 2B. By this method, control block 29, in combination with the rest of the time delay circuitry shown in FIG. 2A, coarse adjusts time delay by shifting one (or more) T cycles ahead or behind, and makes a fine time delay adjustment using DAC 21, switches 22, 23, 24, 25 capacitors 26, 27 and comparator 28. 
     The rate at which the time delay circuit responds to desired phase changes may be adjusted by altering the characteristics of the accumulator within control block 29. 
     The invention includes three basic elements (capacitor, current DAC and comparator) that are used to determine a desired time delay in such a way that the absolute values of the charging currents and capacitance do not affect the resolution or value of the desired time delay. The comparator delay is rendered consistent by using the full scale value of the DAC to charge the ramping capacitor, and the DAC and capacitance variations are canceled by using similar construction, or by using a single element. The circuit configuration of the present invention eliminates the need for calibration, and renders the determination of time delay insensitive to variations in power supply, temperature, manufacturing process, and low frequency drifts in DAC current. 
     As explained in more detail below, the present invention provides a time delay free from the deleterious effects of capacitance absolute value and capacitance voltage coefficient, and free from the deleterious effects of low frequency variation or drift in the current DAC, as well as the effects of DAC current variation and capacitor value variation resulting from the manufacturing process. 
     In the following explanation of the operation of the illustrative embodiment shown in FIG. 2A, the voltages are relative to constant voltage line 32 (in this case, ground). Initially, both capacitors 26, 27 are charged at initial voltage X from node 33 through switches 24, 25. Then, current DAC 21 is set by control block 29 to provide a current of M*i (i being a unit current of DAC 21 and M being a digital number provided by control block 29). Control block 29 then closes switch 22 to charge up reference level capacitor 26 (having a value of value Ca) for a certain interval T to produce a desired threshold level on capacitor 26. After charging, voltage Vref of capacitor 26 will be ##EQU1## Where T is the unit time or 1/ (master clock) to be interpolated. After charging capacitor 26, current DAC 21 is set by control block 29 to provide a current of F*i (F being a digital number provided by control block 29). Control block 29 then closes switch 23 to charge up capacitor 27 (having a value of Cb). The voltage Vramp of terminal 31 at time t measured from the closure of switch 23 is given by the equation: ##EQU2## Comparator 28 will transition at time td when Vramp becomes equal to Vref. Time td is a controllable delay time measured from the closure of switch 23 and is given by the equation: ##EQU3## If Ca is equal to Cb, time td is: ##EQU4## This formula shows that delay time td is set by DAC 21 and charging time T of threshold level capacitor 26. Also, this equation shows that, by changing the ratio of DAC values M and F, delay time td will change. This provides a variable time delay which can be used as part of a variable phase shifter. The minimum time delay is: ##EQU5## 
     If the DAC value F is set at full scale for DAC 21, tdmin will be at its minimum and time delay resolution will be at its maximum. If charging time T is N times shorter than target signal cycle U, the minimum time delay tdmin is ##EQU6## 
     The resolution of the time delay is ##EQU7## 
     N is limited by the speed of the digital elements. This circuit has a resolution limitation by F times digital element speed limitation. Thus the resolution of the present invention is many times better than the digital element speed. 
     FIG. 3 is an example of control timing of switches 22, 23, 24, 25 and DAC 21 shown in FIG. 2A, in accordance with the illustrated embodiment. The top trace indicates the timing of the application of either M or F to DAC 21 by control block 29, and the bottom four traces indicate the timing of the activation of switches 22, 23, 24 and 25 by control block 29. 
     One of the advantages of the present invention is the insensitivity to process variation effects on the capacitance values for capacitors 26 and 27 and on the unit current i of DAC 21. This is because the threshold level voltage is a function of the relative values of capacitors 26 and 24 and the value of unit current i of DAC 21 multiplied by an integer number. 
     It is not required that DAC 21 charge capacitors 26 and 27. Alternatively, discharging capacitors 26 and 27 from an initial voltage is also acceptable to accomplish the same function. 
     Capacitors 26 and 27 may be replaced by MOS transistors. In this case the gate terminals of the MOS transistors would be connected to switches 22 and 24 or 23 and 25, respectively, and the drain and source terminals would be connected together and to constant voltage line 32. The non-linear gate capacitance of a MOS transistor is canceled out by the present invention. To provide an example, assume that when the voltage of nodes 30 and 31 is under threshold Vt, the MOS gate capacitance is Cx, and when the voltage of nodes 30 and 31 above Vt the MOS gate capacitance is Cy. If the charging of the threshold level capacitor is stopped before the voltage reaches Vt, the reference voltage is: ##EQU8## 
     In addition, the voltage on the ramping capacitor is ##EQU9## In this instance, the threshold level capacitor and the ramping capacitor have the same capacitance Cx. Time td from the closure of switch 23 until Vramp is equal to Vref is ##EQU10## 
     When the voltage on nodes 30 and 31 is above Vt, each capacitor has a value of Cy, and the reference voltage Vref may be expressed as: ##EQU11## Here, T=T1+T2, where T1 is the time required for the MOS gate capacitance of the threshold level capacitor to charge to Vt and T2 is the charging time of this capacitance after Vt has been exceeded. Thus: ##EQU12## 
     In this case the ramp voltage Vramp may be expressed as: ##EQU13## Here, t=t1+t2, where t1 is the time required for the MOS gate capacitance of the ramping capacitor to charge to Vt, and t2 is the charging time of this capacitance after Vt has been exceeded. Thus: ##EQU14## Time td from the closure of switch 23 until Vramp is equal to Vref may be expressed as: ##EQU15## 
     These formulas show that regardless of whether the voltages on the gate capacitances of the ramping and threshold level capacitors are above or below Vt, the present invention maintains constant resolution. If the capacitors 26 and 27 used for setting the threshold level and ramp are of similar construction (whether they are conventional capacitors or MOS gate capacitances), the linearity of capacitance as a function of voltage does not matter. Both capacitors can be thought of as integrating charge from the current DAC 21. The capacitor voltage will be the same when the charge on the two capacitors are the same. Thus, the present invention is independent of the linearity of the capacitors. 
     Switches 22, 23, 24 and 25 may also be MOS transistors. If the charge injection from the MOS switches is large, the threshold voltage level will be larger. By changing the DAC value M to compensate for the charge injection, erroneous transition of comparator 28 may be avoided. Including the effects of charge injection c, the reference voltage Vref may be expressed as: ##EQU16## and the ramping voltage Vramp may be expressed as: ##EQU17## Here, capacitance Ca and Cb have the same value. Time t from the closure of switch 25 for the ramping capacitor is: ##EQU18## If c is constant, ##EQU19## Thus, time t will have an offset, but resolution remains the same as before. 
     If the ratio of capacitance Ca and Cb is A, the resolution may be expressed as: ##EQU20## This formula shows increasing capacitance ratio A increases resolution. This relationship is also true when using MOS capacitance. 
     If F is at full scale, in order to make a delay more than T, the start time of the charging of ramping capacitor 27 (corresponding to the closure of switch 23) must be delayed by one T cycle delayed start time. If DAC 21 is set at m, this delay may be expressed as: 
     
         M=F+m 
    
     To provide a time delay ahead of the start time actually a time advance), the charging of the ramping capacitor is begun one (or more) T cycles ahead of the start time. If DAC 21 is set at m, this delay may be expressed as: 
     
         M=-F+m 
    
     By this method, the present invention maintains the same resolution continuously over the clock cycle. 
     It is not necessary for control block 29 to activate switches 22 and 23 with different timing signals because the inverses of the timing signals are also available. FIG. 4 provides an example of the use of complementary signals to control switches 22 and 23. The meaning of the traces are the same as those of FIG. 3. While switch 24 is setting initial voltage of threshold level capacitor 26, DAC current flows into voltage line 33. After switch 24 is opened, DAC 21 starts charging the threshold level capacitor 26. While switch 25 is setting the initial voltage of the ramping capacitor 27, DAC current also flows into voltage line 33. After switch 25 is open, DAC 21 starts charging the ramping capacitor 27. 
     Time interval T is defined as the time between the end time of setting the initial voltage of the threshold level capacitor 26, and the end time of charging the threshold level capacitor. It is also the period of the master clock used to control time delay. T is 1/N of the period of the data signal that is being synchronized. In one embodiment of the invention N=16 resulting in a master clock having a frequency 16 times that of the data signal. 
     Alternative embodiments of the present invention are illustrated in FIGS. 5A and 5B, and FIGS. 6A and 6B. Both alternative embodiments use a single capacitor and two DACs, rather than the two capacitors 26, 27 and one DAC 21 of the embodiment of FIG. 2A. 
     Referring to FIGS. 5A and 5B, controlled current is pulled into and out of node 54 under control of current DACs 52, 53 to generate a sawtooth waveform on node 55. Node 55 is compared to a predetermined threshold (possibly ground) by comparator 56 to generate a pulse on node 57 that has a controlled time delay. 
     Referring to FIGS. 6A and 6B, DACs 62 and 63 are controlled to push current into and out of capacitor 61 thus creating a sawtooth waveform on node 64. Node 64 is compared to a predetermined reference by comparator 65 to generate a pulse on node 66 that has a controlled time delay. 
     The embodiments of FIGS. 5 and 6 avoid any deleterious effects of mismatched capacitors in the two capacitor embodiment of FIG. 2A. However, by using two DACs, the embodiments of FIGS. 5 and 6 are sensitive to the effects of mismatches between the unit currents of the DACS, a sensitivity that would not be present in the single-DAC embodiment of FIG. 2A. 
     While the present invention has been described with reference to several illustrative embodiments, it will be understood by those of ordinary skill in this technology that changes, additions or deletions may be made to the illustrated embodiments without departing from the scope of the invention.