Abstract:
In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output.

Description:
RELATED APPLICATION 
     This application is the U.S. National Stage of International Application No. PCT/US2011/058785, filed Nov. 1, 2011, which designates the U.S., published in English, and claims the benefit of U.S. Provisional Application No. 61/408,797, filed on Nov. 1, 2010. The entire teachings of the above applications are incorporated herein by reference. 
    
    
     BACKGROUND 
     A significant shortcoming of RF power amplifiers is the degree of nonlinear distortion they introduce into the amplified signal. This occurs when the amplifier operates outside of its linear region and limits the power efficiency of the amplifier. 
     SUMMARY 
     Embodiments of the present invention include a circuit and corresponding method for linearizing the output of a power amplifier using feedback. Typically, the power amplifier operates on one copy of a wideband input signal. A variable group delay block delays another copy of the wideband input signal to obtain a delayed input signal, which is coupled to the non-inverting input of a wideband operational amplifier (op-amp). The op-amp is coupled in a feedback loop to determine an error signal based on a difference between the delayed input signal and the (linearized) power amplifier output. A feedback amplifier amplifies the error signal to obtain an amplified error signal, which is combined with the power amplifier output to obtain a linearized power amplifier output using a directional combiner. 
     In some examples, the feedback amplifier may include or be coupled to an additional linearization circuit (e.g., in recursive fashion). The additional linearization circuit includes another variable group delay block, which delays the error signal from the wideband op-amp to obtain a delayed error signal. A second wideband op-amp determines a second error signal based on a difference between the delayed error signal and the amplified error signal (i.e., the output of the feedback amplifier). A second feedback amplifier amplifies the second error signal to obtain a second amplified error signal, which is combined with the output of the first feedback amplifier to obtain the amplified error signal using another directional combiner. 
     Example circuits can be integrated circuits fabricated using deep sub-micron CMOS technology, including 130 nm, 65 nm, and 45 nm CMOS technology. 
     In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention. 
         FIG. 1A  is a block diagram of a linearization circuit for a power amplifier. 
         FIG. 1B  is a block diagram of the feedback power amplifier shown in  FIG. 1A . 
         FIG. 2  shows plots of Cadence® simulations of linearization of a power amplifier using the circuit depicted in  FIGS. 1A and 1B . 
         FIG. 3  is a circuit diagram of a wideband op-amp suitable for use in the circuits shown in  FIGS. 1A and 1B . 
         FIG. 4  is a block diagram of a wideband signal processor that can be provisioned to act as the variable group delays shown in  FIGS. 1A and 1B . 
         FIGS. 5A ,  5 B, and  5 C are block diagrams of second-order state variable structures that can be used to implement the biquad structures within the wideband signal processor of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     A description of example embodiments of the invention follows. 
       FIG. 1A  is a block diagram of an integrated circuit (IC)  100  that linearizes a wideband power amplifier  108 . The circuit output is an amplified output signal P OUT  that may be distorted due to the power amplifier&#39;s nonlinear behavior. For example, the power amplifier&#39;s nonlinear behavior may cause the output signal P OUT  to spill out the spectrum skirt of the input signal P IN , as shown in  FIG. 2  (described below). 
     A splitter  102  at the input to the IC  100  splits an input signal P IN  evenly between a top path  104  and a bottom path  106 , causing a loss of (3 dB+I L ) where I L  is the insertion loss of the splitter  102 . The top path  104 , which includes the power amplifier  108 , has a group delay of gd 1 (f), and the bottom path  106  has a group delay of gd 2 (f). The top path  104  also includes two directional couplers  110  and  112  with coupling values of C 1  and C 2  dB. The first directional coupler  110  combines the power amplifier output with the output of a feedback power amplifier  118  in the second path  106 , and the second directional coupler  112  couples a fraction of the output signal P OUT  to the inverting input of a wideband op-amp  116  in the bottom path  106 . The insertion losses of the directional couplers  110  and  112  are I C1  and I C2  dB respectively. 
     The bottom path  106  serves to generate a compensation (feedback) term for the distortion (nonlinearities) introduced by the power amplifier  108  into the output signal P OUT . As stated above, the group delay of the signal through the power amplifier  108  and directional couplers  110  and  112  is gd 1 (f), whereas gd 2 (f) is the group delay of the amplified signal coupled from the second directional coupler  112 . The bottom path  106  feeds the input signal P IN  from the splitter  102  into a tunable group delay gd 3 (f)  114 , which is dynamically adjusted such that gd 2 (f) is equal to gd 1 (f). The group delay gd 3 (f) has an insertion loss of I GD3  dB. 
     The output from the tunable group delay  114  is fed to the non-inverting input of the wideband op-amp  116 . The inverting input of the op-amp  116  is the coupled output power (P PA −I C1 −C 2 ) dB from the power amplifier  108 . The output of the op-amp is an error signal P OPAMP  equal to the difference between the two input signals. A feedback power amplifier (PA′−C 1 ) dB  118  amplifies the error signal P OPAMP  such that the amplified error signal P PA′  is equal to the power level of the distorted output signal from the power amplifier  108  less the insertion loss of the first directional coupler  110 . The first directional coupler  110  combines the amplified signal from the power amplifier  108  with the amplified error signal P PA′  from the feedback amplifier  118  to cancel the distortion from the output of the power amplifier  108 . The output signal P OUT =P PA −I C1 −I C2 , where P PA =P IN −3 dB−I L +G PA  and G PA  is the gain of the power amplifier  108  in dB. 
       FIG. 1B  shows a circuit  158  that can be used instead of the feedback power amplifier  118  shown in  FIG. 1A  for situations requiring greater amplification of the error signal P OPAMP . In essence, the circuit  158  shown in  FIG. 1B  linearizes a power amplifier  122  that amplifies the error signal P OPAMP  as described above. A splitter  120  directs part of the error signal P OPAMP  to the power amplifier  122  and another part to a variable group delay  128 , which compensates for changes in the group delay of the power amplifier  122  and its associated directional couplers  124  and  126 . A wideband op-amp  130  subtracts the output of the second directional coupler  126  from the output of the variable group delay  128  to produce an error signal P OPAMP 1 , which is amplified with another feedback amplifier  132 . Generally speaking, the amplified error signal P PA′1  is at a power level that is sufficiently low (e.g., 4 dBm) to be well within the other feedback amplifier&#39;s linear range. If not, then the other feedback amplifier  132  can be linearized using a circuit similar to circuits  100  and  158 . 
       FIG. 2  shows a set of Cadence® simulation results for three integrated circuits for linearizing power amplifiers fabricated 130 nm (left), 65 nm (middle), and 45 nm (right) CMOS technology. The pink spectrum is the input signal (in this case, a binary phase shift key (BPSK), 100 Mbps, 1000 random bits, raised cosine pulse with 20% roll-off). Without feedback linearization, the power amplifier output is shown in red, only 20 dB down from the input signal. With feedback linearization, the power amplifier output is 44, 48, and 55 dB down for the 130, 65, and 45 nm nodes respectively. 
       FIG. 3  shows a wideband (e.g., up to 200 GHz) op-amp  300  suitable for use in the linearization circuits  100  and  158  shown in  FIGS. 1A and 1B . The op-amp includes a differential, feedforward integrator  302  that includes three pairs of field-effect transistors (FETs) connected in series between a voltage supply and ground. The gates of the lower pair of FETs act as the inverting and non-inverting inputs  304 ,  306  of the op-amp  300 . A node between the top and middle FETs above the inverting input  304  provides an output that is filtered with a capacitor C and buffered with a buffer  308 . The FETs in the middle of the op-amp  300  act as voltage-variable resistors and are controlled by a voltage Y R  in the linear region. Changing Y R  to about 1 V causes the gain to shift to almost 140 dB and the phase to shift to −90° at a few hundred kilohertz before dropping off at over 100 GHz. The field accuracy can be maintained all the way from a few hundred kilohertz out to 10 GHz. 
       FIG. 4  shows a wideband (analog) signal processor (WiSP)  400  that can be provisioned to act as a variable group delay block suitable for use in the linearization circuits  100  and  158  shown in  FIGS. 1A and 1B . The WiSP  400  includes N biquad processors  402  that operate in series on an analog input to produce a delayed analog output. The provisioning is done digitally. Each biquad  402  may be implemented in the form of a second-order state variable filter, such the filters described in U.S. application Ser. No. 12/921,987 to Dev V. Gupta and Divi Gupta, incorporated herein by reference in its entirety. Additionally, the biquads of  402  may be implemented in the forms of  FIGS. 5A ,  5 B, and  5 C. 
     A serial peripheral interface or serial RapidIO interconnect  404  controls the biquads  402  to achieve the desired group delay. The interface/interconnect  404  may also respond to outside signals, e.g., signals that adjust the desired group delay based on mismatch between arms of the linearization circuits described above. For more on serial RapidIO, see www.rapidio.org/home, which is incorporated herein by reference in its entirety. 
     The WiSP  400  implements a variable group delay by changing attenuator, integrator, or tunable loss pad values within the biquad circuits  402 , which make up a group delay network. Changes in the attenuator, integrator, or tunable loss pad values vary the WiSP&#39;s transfer function by changing the pole locations. This then varies the phase response, which has the effect of varying the group delay. 
       FIG. 5A  shows a second-order state variable structure  510  that comprises two integration/gain stages, with variable gain attenuators operating within each stage. A combined signal based on a wideband input u(t) is fed to the first integration/gain stage, which, in turn, provides an input to the second integration/gain stage. Variable gain attenuators feeds signals forward (b&#39;s)  516 ,  518 ,  522  and backward (a&#39;s)  512 ,  514  from the input and output of each of the two integrators  506 ,  508 . These signals terminate in a first summing block  502  that combines feedback signals and second summing block  504  that combines feed-forward signals. Example second-order state variable filters may also include fractional gain blocks and additional summers. Varying gains of the variable gain blocks changes a center frequency of the embodiment second-order state variable filters. The transfer function coefficients of a wideband signal processing filter constructed from the structure of  FIG. 5A  are determined by the variable attenuator values. 
       FIG. 5B  shows a second-order state variable structure  520  that comprise two integration/gain stages, each of which includes three variable gain integrators  524 ,  526 ,  528 ,  534 ,  536 ,  538 , two of which are operably coupled to a summing block  532 ,  542 . A combined signal based on a wideband input u(t) is fed to the first integration/gain stage, which, in turn, provides an input to the second integration/gain stage. Each gain stage consists of an upper and lower path, with two variable integrators in the lower path and one in the upper path. A switch  544  operably couples a third, binary-valued signal to the second stage summing block  542 . Example second-order state variable filters may also include fractional gain blocks and additional summers. Varying gains of the variable gain blocks changes a center frequency of the embodiment second-order state variable filters. The transfer function coefficients of a wideband signal processing filter constructed from the structure of  FIG. 5B  are determined by the integrator gain values. 
       FIG. 5C  shows a second-order state variable structure  530  that comprise two integration/gain stages, each of which includes one tunable loss pad  548 ,  558  and two integrators  544 ,  546 ,  554 ,  556 , one of which is operably coupled to a summing block  552 ,  562 . A combined signal based on a wideband input u(t) is fed to the first integration/gain stage, which, in turn, provides an input to the second integration/gain stage. Each gain stage consists of an upper and lower path, with two integrators in the lower path and one tunable loss pad in the upper path. A switch  564  operably couples a third, binary-valued signal to the second stage summing block  562 . Example second-order state variable filters may also include fractional gain blocks and additional summers. Varying gains of the variable gain blocks changes a center frequency of the embodiment second-order state variable filters. The transfer function coefficients of a wideband signal processing filter constructed from the structure of  FIG. 5C  are determined by the tunable loss pads and integrator gain values. 
     While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.