Abstract:
A method and system is described for several embodiments of a communication system. In a first embodiment, a method and system is described wherein a signal is received and down-converted and wherein power consumption can be characterized as “ultra-low.” In a second embodiment, a method and system is described wherein undesirable images are rejected in a down-conversion system. In a third embodiment, a method and system is described wherein a signal is transmitted in a highly efficient manner. In one implementation the present invention is used in a family radio system.

Description:
CROSS-REFERENCE TO OTHER APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/116,850, filed Jan. 22, 1999, which is herein incorporated by reference in its entirety. 
     The following applications of common assignee are related to the present application, and are herein incorporated by reference in their entireties: 
     “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed on Oct. 21, 1998. 
     “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed on Oct. 21, 1998. 
     “Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed on Oct. 21, 1998. 
     “Integrated Frequency Translation and Selectivity,” Ser. No. 09/175,966, filed on Oct. 21, 1998. 
     “Analog Zero IF FM Decoder and Embodiments Thereof, Such as the Family Radio Service,” Ser. No. 09/476,093, filed Jan. 3, 2000. 
     “Communication System With Multi-Mode and Multi-Band Functionality and Embodiments Thereof, Such as the Family Radio Service,” Ser. No. 09/476,093, filed Jan. 3, 2000. 
     “Multi-Mode, Multi-Band Communication System,” Ser. No. 09/476,330, filed Jan. 3, 2000. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is generally directed toward receiver-transmitter systems referred to as Family Radio Service (FRS) units, although the invention is not limited to this embodiment. The Family Radio Service is one of the Citizens Band Radio Services. It is intended for the use of family, friends, and associates to communicate among themselves within a neighborhood or while on group outings. There are fourteen discreet FRS channels available for use on a “take turns” basis. The FRS unit channel frequencies are: 
     
       
         
               
               
               
             
               
               
               
             
           
               
                   
                   
               
               
                   
                 Channel No. 
                 (MHz) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 1 
                 462.5625 
               
               
                   
                 2 
                 462.5875 
               
               
                   
                 3 
                 462.6125 
               
               
                   
                 4 
                 462.6375 
               
               
                   
                 5 
                 462.6625 
               
               
                   
                 6 
                 462.6875 
               
               
                   
                 7 
                 462.7125 
               
               
                   
                 8 
                 467.5625 
               
               
                   
                 9 
                 467.5875 
               
               
                   
                 10 
                 467.6125 
               
               
                   
                 11 
                 467.6375 
               
               
                   
                 12 
                 467.6625 
               
               
                   
                 13 
                 467.6875 
               
               
                   
                 14 
                 467.7125 
               
               
                   
                   
               
             
          
         
       
     
     Other selected technical specifications are: 
     (a) Frequency modulation (although phase modulation is allowed); 
     (b) Frequency tolerance of each FRS unit must be maintained within 0.00025%; 
     (c) The authorized bandwidth for an FRS unit is 12.5 kHz; and 
     (d) Effective radiated power (ERP) shall not, under any condition of modulation, exceed 0.500 W. 
     The operating rules for the FRS are found at 47 C.F.R. 95.191-95.194. For additional technical information, see 47 C.F.R. 95.601-95.669. 
     2. Related Art 
     Modern day communication systems employ components such as transmitters and receivers to transmit information from a source to a destination. To accomplish this transmission, information is imparted on a carrier signal and the carrier signal is then transmitted. Typically, the carrier signal is at a frequency higher than the baseband frequency of the information signal. Typical ways that the information is imparted on the carrier signal are called modulation. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a communications system with an image-reject down-converter. The invention has a number of aspects, including a ultra-low power down-converter, an image-reject down-converter, and a high-efficiency transmitter. In an embodiment, the present invention is used in a family radio system. It is to be understood, however, that the invention is not limited to this particular embodiment. Other implementations in communications-related environments are within the scope and spirit of the invention. 
     The present invention has a number of advantages, including power reduction, tuning reduction, parts reduction, price reduction, size reduction, performance increase, greater efficiency, and increased integration possibilities. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1 illustrates an exemplary block diagram of the ultra-low power down-converter system; 
     FIG. 2 illustrates a detailed schematic drawing of the exemplary block diagram of FIG. 1; 
     FIG. 3 illustrates an exemplary block diagram of the universal frequency translator module being used in the ultra-low power down-converter embodiment of the present invention; 
     FIG. 4 illustrates an exemplary block diagram of the transmitter embodiment of the present invention; 
     FIG. 5 a  illustrates an exemplary mixer circuit; 
     FIG. 5 b  illustrates an exemplary frequency domain plot corresponding to the mixed circuit of FIG. 5 a;    
     FIG. 6 illustrates an exemplary block diagram of the universal frequency translator module being used in the transmitter embodiment of the present invention; 
     FIG. 7 a  illustrates an exemplary block diagram of the image-reject down-converter embodiment of the present invention; 
     FIG. 7 b  illustrates a frequency domain plot of waveforms associated with the exemplary block diagram of FIG. 7 a;    
     FIG. 7 c  illustrates a phase relationship table for waveforms associated with the exemplary block diagram of FIG. 7 a;    
     FIG. 8 illustrates a detailed schematic drawing of the exemplary block diagram of FIG. 4; 
     FIG. 9 illustrates an exemplary implementation of a switch in the universal frequency translator module of FIG. 6; and 
     FIGS. 10 a  through  10   d  illustrate a detailed schematic drawing of the exemplary block diagram of FIG. 7 a.   
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following sections describe methods related to an ultra-low power down-converter, an image-reject down-converter, and a high-efficiency transmitter. Structural exemplary embodiments for achieving these methods are also described. It should be understood that the invention is not limited to the particular embodiments described below. Equivalents, extensions, variations, deviations, etc., of the following will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such equivalents, extensions, variations, deviations, etc., are within the scope and spirit of the present invention. 
     Ultra-Low Power Down-Converter 
     The present invention can be implemented with an aliasing system as disclosed in U.S. patent application Ser. No. 09/176,022, titled,“Method and System for Down-Converting Electromagnetic Signals,” incorporated herein by reference in its entirety. 
     FIG. 1 illustrates an exemplary aliasing system  100  for down-converting electromagnetic (EM) signals, such as an RF input (RF in ) signal  102 . The aliasing system  100  is an exemplary embodiment of an optimized aliasing system, referred to herein as an ultra low power down-converter. 
     The exemplary aliasing system  100  includes an aliasing module  110  that aliases an EM signal  112 , using an aliasing signal  114 , and outputs a down-converted signal  116 , as disclosed in U.S. patent application Ser. No. 09/176,022, titled,“Method and System for Down-Converting Electromagnetic Signals,” incorporated herein by reference in its entirety. The aliasing module  110  is also referred to herein as a universal frequency translator (UFT) module. 
     Aliasing system  100  optionally includes one or more of an input impedance match module  118 , a parallel resonant tank module  120 , and an output impedance match module  122 , as disclosed in the &#39;022 application. 
     Aliasing system  100  optionally includes a local oscillator (LO) impedance match module  124  for impedance matching a local oscillator input (LO in ) signal  126 , generated by a local oscillator  128 , to the aliasing module  110 . The LO impedance match module  124  can be designed to increase the voltage of the LO in  signal  126 , as illustrated by a higher voltage LO in  signal  130 . The LO impedance match module  124  permits the aliasing system  100  to efficiently operate with a relatively low voltage LO in  signal  126 , without the use of power consuming amplifiers that would otherwise be necessary to increase the amplitude of the LO in  signal  126 . 
     Unless otherwise noted, the aliasing signal  114  is used interchangeably herein to refer to the LO in  signal  126  and/or the higher voltage LO in  signal  130 . 
     The aliasing system  100  optionally includes a DC block  132  that substantially blocks DC while passing substantially all non-DC. In the exemplary embodiment, the DC block  132  is a capacitor  133 . A variety of implementations of the DC block  132  suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein. 
     The aliasing system  100  optionally includes a bias module  134  for biasing the aliasing signal  114 . A variety of implementations of the biasing module  134  suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein. 
     FIG. 2 illustrates an exemplary schematic diagram  202  that can be used to implement the aliasing system  100 . The exemplary schematic diagram  202  provides exemplary circuit elements that can be used within the optional input impedance match module  118 , the optional parallel resonant tank  120 , the optional output impedance match module  122 , the optional LO impedance match module, the optional DC block  132 , and the optional bias module  134 . The invention is not limited to the exemplary embodiment of FIG.  2 . 
     The exemplary schematic diagram  202  includes a storage module  210  for storing energy transferred from the EM signal  112 , as disclosed in the &#39;022 application. 
     In the schematic diagram  202 , the aliasing module  110  of FIG. 1 is illustrated as an application specific integrated circuit (ASIC)  212 . In an embodiment, the ASIC is implemented in complementary metal oxide semiconductor (CMOS). 
     The ASIC  212  is coupled to a first voltage source  218  for supplying power circuits within the ASIC  212 . The circuits within the ASIC  212  are described below with reference to FIG.  3 . An optional first bypass module  220  is optionally disposed as illustrated to substantially eliminate unwanted frequencies from the first power supply  218  and from the ASIC  212 . 
     The ASIC  212  includes a substrate (not shown) which is optionally coupled to a second voltage source  214 . An advantage of coupling the substrate to the second voltage source  214  is described below with reference to FIG.  3 . When the substrate is coupled to the second voltage source  214 , an optional second bypass module  216  is optionally disposed as illustrated to substantially eliminate unwanted frequencies from the substrate and the second voltage source  214 . 
     FIG. 3 illustrates an aliasing module  302 , which is an exemplary embodiment of the aliasing module  110  and the ASIC  212 . The aliasing module  302  includes a sine wave to square wave converter module  310 , a pulse shaper module  312  and a switch module  314 . The sine wave to square wave converter module  310  converts a sine wave  114  from the local oscillator  128  to a square wave  311 . The pulse shaper module  312  receives the square wave  311  and generates energy transfer pulses  313  therefrom. Energy transfer pulses are discussed in greater detail in the &#39;022 application. 
     In an embodiment, the pulse shaper module  312  is implemented as a mono-stable multi-state vibrator. A variety of implementations of the pulse shaper module  312  suitable for the present invention are available as will be apparent to persons skilled in the relevant art, based on the teachings herein. 
     Generally, the frequency of the energy transfer pulses  311  is determined by the frequency of the aliasing signal  114  and the width or aperture of the energy transfer pulses is determined by the pulse shaper module  312 . 
     In the illustrated embodiment, where the sine wave to square wave converter module  310  and the pulse shaper module  312  are provided on-chip, the ASIC substrate (not shown) is optionally coupled to the second power supply  214 . The second power supply  214  can be varied to affect the performance of the circuits on the ASIC  212 , with a result of effectively adjusting the pulse width of the energy transfer pulses  313 . 
     In an alternative embodiment, the sine wave to square wave converter module  310  and/or the pulse shaper module  312  are provided off-chip. 
     An advantage of the ultra-low power down-converter aliasing system  100  is its low power consumption. For example, in an actual implementation, the aliasing module  302  required an average of approximately 1 mA and consumed approximately 3 to 5 mWatt. This is significantly greater performance than conventional down converter systems. 
     Other advantages of the ultra-low power down-converter aliasing system  100  include tuning reduction, parts reduction, price reduction, size reduction, performance increase, low frequency and power LO, and excellent linearity. Another advantage of the ultra-low power down-converter aliasing system is that it can down-convert EM signals as high as 3.5 GHZ when implemented in CMOS. Higher frequencies can be down-converted using other materials such as gallium arsenide (GaAs), for example. 
     In an embodiment, an ultra-low power down-converter as described above is implemented in an FRS. 
     Image-Reject Down-Converter 
     The present invention is directed toward an image reject mixer using a universal frequency translation (UFT) module. The image reject mixer down-converts an input signal to an intermediate frequency signal, but rejects or attenuates the associated image frequency signal. As compared with conventional mixers, the present invention down-converts an input signal to a lower frequency with lower front-end attention, lower component count, lower cost, and lower overall power requirements when compared with conventional frequency mixers. 
     Referring to FIGS. 5A-5B, a conventional mixer  506  generates an intermediate frequency (IF) signal  510  at frequency (f IF ) using a local oscillator (LO) signal  508  at frequency f LO  and at least one input signal. For a given LO frequency (f LO ) and IF frequency (f IF ), IF signal  510  contains a down-converted representation of input signals located at frequencies f 1 =f LO +f IF , and f 2 =f LO −f IF . FIGS. 5A-5B, illustrate input signal  502  at frequency (f 1 ) and input signal  504  at frequency (f 2 ) being down-converted to IF signal  510  at f IF . For example, if f 1  is 901 MHZ, f 2  is 899 MHZ, and f LO  is 900 MHZ, then both the input signal  502  and input signal  504  are down-converted to the desired f IF  of 1 MHz. 
     Typically, it is desired that the IF signal  510  contain a down-converted representation of only one of the first or second input signals. Herein, the input signal that is desired to be down-converted is called the desired input signal, and the other input signal is called the undesired input signal. Alternatively, it is desired that the representation of the undesired signal in the IF signal be significantly attenuated compared with the desired signal. For example, if input signals  502 ,  504  represent independent voice messages, then the simultaneous down-conversion of both input signals  502 ,  504  to f IF  using a conventional mixer may result in neither message being clearly recovered. 
     The undesired input signal and it&#39;s down-converted representation are often referred to as an image signal. For example, referring to FIG. 5B, if it is desired that only the input signal  502  be represented by the IF signal  510 , then the input signal  504  may be referred to as the image signal of the desired input signal  502 . Furthermore, f 2  is referred to the “image frequency”, even when no signal is currently present at this frequency. This illustration is for example only, the input signal  504  could be chosen as the desired input signal. In which case, input signal  502  would be the image signal and f 1  would be the image frequency, as will be understood by those skilled in the arts based on the discussion herein. 
     FIG. 7A illustrates a block diagram of an image rejection mixer  701  according to the present invention. Image rejection mixer  701  down-converts a desired input signal but significantly attenuates the down-conversion of the image input signal. FIG. 7A illustrates an antenna  704  and a the image reject mixer  701 . Image rejection mixer  701  comprises: input signal splitter  708 , path  710 , path  724 , and summer  738 . Path  710  comprises: UFT module  714 , and phase shifter  718 . Path  724  comprises: phase shifter  728 , UFT module  726 , and gain balance module  727 . 
     Antenna  704  receives an input signal  702 . Input signal  702  may contain a desired input signal F D  and an image signal F I , as illustrated by F D    744  and F I    746  in FIG.  7 B. Preferably, F D  and F I  are separated by 2f IF , where f IF  is the frequency of the IF signal  742  generated by image reject mixer  701 . 
     The operation of image reject mixer  701  is as follows. Splitter  708  receives input signal  702  from antenna  704 . Splitter  708  splits the input signal  702  into two signals that are routed to two paths, path  710  and path  724 . Preferably, the splitter output signals are approximately equal amplitude and equal phase to each other. A variety of equal-amplitude and equal-phase power splitters are readily available as will be understood by those skilled in the relevant arts. As stated above, input signal  702  contains a desired signal F D  and image signal F I . Therefore, splitter  708  generates a desired signal F D1  and a image signal F I1  that exist at node  712 , and a desired signal F D2  and image signal F I2  that exist at node  723 . 
     Splitter  734  receives a control signal F C    748 . FC is preferably a sinewave with frequency f C =(f D +f I )/(2·N), where N is an integer ( 1 , 2 , 3  . . . ). Splitter  734  generates control signals F C1  and F C2  at nodes  732  and  730 , respectively. Splitter  734  is preferably equal amplitude and equal phase splitter; a variety of which are available as will be apparent to those skilled in the arts based on the discussion herein. F C1  will be used by UFT module  714  to down-convert F D1  and F I1 , and F C2  will be used by UFT module  726  to down-convert F D2  and F I2  as will be described below. The down-conversion by UFT modules  714 , 726  is fully described in pending U.S. patent application Ser. No. 09/176,022, titled,“Method and System for Down-Converting Electromagnetic Signals.” 
     The operation of path  710  will now be described in detail, after which path  724  will be described. Finally, summer  738  will be described. 
     As illustrated in FIG. 7A, path  710  contains UFT module  714  and phase shifter  718 . UFT module  714  accepts desired signal F D1 , image signal F I1 , and control signal F C1 . UFT module  714  down-converts the F D1  and F I1  to the lower intermediate frequency (f IF ). The down-conversion of an input signal to an IF signal is fully described in pending U.S. patent application Ser. No. 09/176,022, titled, “Method and System for Down-Converting Electromagnetic Signals,” which is incorporated by reference in its entirety. As such, F D1  and F I1  are down-converted to a lower frequency, f IF . 
     A summary of the above mentioned U.S. patent application Ser. No. 09/176,022 follows. In an embodiment, the universal frequency translator (UFT) down-converts an input signal. The UFT may down-convert the input signal to an IF signal, or to a demodulated baseband signal. In particular, the rate of a control signal determines whether the input signal is down-converted to an IF signal, or down-converted to a demodulated baseband signal. Other down-conversion options are also possible using the UFT  118 . Generally, relationships between the input signal, the rate of the control signal, and the down-converted output signal are illustrated below: 
     
       
         (Freq. of input signal)= N ·(Freq. of control signal)±(Freq. of down-converted output signal) 
       
     
     For the examples contained herein, for illustrative purposes only and without limitation, only the “+” condition will be discussed. The value of N represents a sub-harmonic or harmonic of the input signal (e.g.,N=0.5, 1, 2, 3, . . . ). 
     The UFT is further described in U.S. patent applications “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, “Analog Zero IF FM Decoder and Embodiments Thereof, Such as the Family Radio Service,” Ser. No. 09/476,092, “Communication System With Multi-Mode and Multi-Band Functionality and Embodiments Thereof, Such as the Family Radio Service,” Ser. No. 09/476,093, and “Multi-Mode, Multi-Band Communication System,” Ser. No. 09/476,330, which are incorporated herein by reference in their entireties. 
     The operation of path  710  will now be described in detail, after which path  724  will be described. Finally, summer  738  will be described. 
     Phase shifter  718  receives the down-converted signals F D1  and F I1 , and phase shifts F D1  and F I1  by approximately 90 degrees. A variety of 90 degree phase shifters are readily available as will be apparent to those skilled the relevant arts. 
     Path  724  will now be described. As discussed above, Path  724  comprises UFT module  726 , phase shifter  728 , and gain balance module  727 . Phase shifter  728  accepts control signal F C2  from splitter  734 . As discussed above, F C  preferably comprises a sinewave with frequency f C =(f D +f I )/(2·N), where N is an integer. For a selected value of N, phase shifter  728  shifts the phase of control signal F C2  by an amount of 90.M/N degrees, where M is an odd integer (M=1, 3, 5 . . . ). 
     UFT module  726  accepts desired signal F D2 , image signal F I2 , and phase shifted control signal F C2 . UFT module  726  down-converts the F D2  and F I2  to the lower intermediate frequency (f IF ) using the phase shifted control signal from phase shifter  728 . The down-conversion of an input signal to an IF signal is fully described in pending U.S. patent application Ser. No. 09/176,022, titled,“Method and System for Down-Converting Electromagnetic Signals”, which is incorporated by reference in its entirety. As such, F D2  and F I2  are down-converted to a lower frequency, f IF . 
     Gain Balance module  727  accepts the down-converted signals F D2  and F I2  and adjusts the power level of F D2  and F I2  such that the power of F D2  and F I2  at node  737  is approximately equal to that of F D1  and F I1  at node  720 . This improves the cancellation of F I1  and F I2  by summer  738 . In one embodiment, gain balance module is an attenuator with an attenuation that is similar to the attenuation caused by phase shifter  718 . In an alternate embodiment, gain balance module  727  is an inverter amplifier that can be used change the selected signal that adds in-phase at summer  738 . 
     The operation of summer  738  will now be described. Summer  738  receives down-converted signals F D1  and F I1  from path  710 , and down-converted signals F D2  and F I2  from path  724 . Summer  738  sums these four signal to generate F IF    742 . Because of the relative phase relationship of the four signals, F D1  and F D2  substantially add in-phase, and F I1  and F I2  substantially cancel. Therefore, F IF    742  substantially comprises the desired signal F D , and the undesired image signal F I  is substantially attenuated when compared with that of F D . 
     The relative phase relationships between F D1 , F D2 , F I1 , F I2  will now be described using FIG.  7 C. FIG. 7C lists the phase relationship for the above mentioned signals at various nodes in image reject mixer  701  relative to the phase of F D1  at node  712 . This is done for illustrative purposes only, as any phase reference could be chosen. 
     At node  712 , F D1  and F I1  are shifted by 0 degrees. Likewise at node  723 , F D2  and F I2  are phase shifted by 0 degrees. This occurs because splitter  708  is preferably an equal phase splitter that causes negligible phase shift. 
     At node  716 , down-converted F D1  and down-converted F I1  are phase shifted by 0 degrees. At node  725 , down-converted F D2  and down-converted F I2  are phase shifted by −90 degrees, and +90 degrees, respectively. This occurs because the control signal F C2  is phase shifted by the amount of (90·M/N), where N is associated with the control signal F C  as described above. This phase shifted control signal operates UFT module  726 , which down-converts F D2  and F I2  and implements the described phase shift. 
     At node  720 , down-converted F D1  and down-converted F I1  are phase shifted by −90 degrees, and −90 degrees respectively by phase shifter  718 . 
     At node  737 , down-converted F D2  and down-converted F I2  maintain the phase relationship of −90 degrees and +90 degrees. 
     The reason for the cancellation of down-converted F D1  and down-converted F I2  in summer  738  can now be seen. At node  720 , down-converted F I1  has a relative phase shift of −90 degrees. In contrast, down-converted F I2  at node  737  has a relative phase shift of +90 degrees. Therefore, when down-converted F I1  and down-converted F I2  are combined in summer  738  there is signal cancellation because down-converted F I1  and down-converted F I2  are 180 degrees out of phase. 
     In contrast, summer  738  combines down-converted F D1  and down-converted F D2  in an additive manner because down-converted F D1  at node  720  and down-converted F D2  at node  737  have approximately the same relative phase shift of −90 degrees. Therefore, F IF    742  substantially contains the down-converted representation of the desired signal F D , only. The level of signal rejection of the image signal F I  is theoretically infinite and only limited by component mismatches. 
     FIGS. 10A-10D illustrate a detailed schematic diagram that further describes one embodiment of image rejection mixer  701 . Splitter  1002  is one embodiment of splitter  708 . UFTs  1002  and  1004  are one embodiment of UFT  714  and UFT  726 , respectively. In one embodiment, UFT  1002  comprises a CMOS chip  1003 , and UFT  1004  comprises a CMOS chip  1005 . Signals  1014  and  1016  connect FIGS. 10A through 10D for illustration purposes. Signal  1020  comprises down-converted F D1  and down-converted F I1  at node  716  in FIG.  7 A,and down-converted signal  1022  comprises down-converted F D2  and down-converted F I2  at node  725 . In one embodiment, amplifier  1010  is included in path  710 , and amplifier  1012  is included in path  724 . Amplifiers  1010  and  1012  are optional to improve the signal strength and are not necessary to practice the present invention. In one embodiment, phase shifter  718  comprises phase shifter  1014 . In one embodiment, gain balance module  727  comprises gain balance module  1016 . 
     High-Efficiency Transmitter 
     This section describes the high-efficiency transmitter embodiment of a frequency up-converter for use in the family radio system. It describes methods and systems related to a transmitter. Structural exemplary embodiments for achieving these methods and systems are also described. It should be understood that the invention is not limited to the particular embodiments described below. Equivalents, extensions, variations, deviations, etc., of the following will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such equivalents, extensions, variations, deviations, etc., are within the scope and spirit of the present invention. 
     The present invention has significant advantages over conventional transmitters. These advantages include, but are not limited to, a reduction in the number of parts to accomplish the transmitter function, a reduction in the power requirements for the circuit, and a reduction of cost and complexity by permitting the use of circuits designed for lower frequency applications, including, but not limited to, lower frequency oscillators. 
     An embodiment for transmitting a voice signal is shown in FIG.  4 . The voice signal is input to a microphone  402 . The output of microphone  402  is an analog voice signal  424  which is connected to an audio amplifier  404 . The output of audio amplifier  404  is an amplified signal  426  which is filtered by an audio buffer amplifier  406 . Audio buffer amplifier  406  acts as a low pass filter to eliminate unwanted higher frequency signals. The output of audio buffer amplifier  406  is a signal  428  which is accepted by crystal oscillator  408 . Crystal oscillator  408  operates as a voltage controlled oscillator and outputs a frequency modulated (FM) signal  430  that is a sinusoidal signal biased substantially around zero volts. 
     At a node  440 , a bias voltage  410  combines with FM signal  430 . For the implementation wherein bias voltage  410  is a positive voltage, the bias point of FM signal  430  is raised such that substantially the entire waveform is above zero. In an alternate implementation wherein bias voltage  410  is negative, the bias point of FM signal  430  is lowered such that substantially all of the waveform is below zero. This combination of FM signal  430  and bias voltage  410  results in an FM control signal  432 . Substantially all of FM control signal  432  is above zero (or below zero if bias voltage  410  is negative). FM control signal  432  is then input to a universal frequency translator (UFT) module  412 . 
     UFT module  412  is comprised of a pulse shaping circuit and a switch, and is described in detail below in FIG.  6 . The output of UFT module  412  is a rectangular waveform  434  that contains a plurality of harmonics. Rectangular waveform  434  is accepted by a filter  416  which filters out the undesired harmonic frequencies and outputs a desired output signal  436 . Desired output signal  436  is the frequency modulated signal at the desired output frequency. Desired output signal  436  goes to a driver  418  and then to a power amplifier  420 . The output of power amplifier  420  is an amplified output signal  430 . Amplified output signal  430  is ready for transmission and is routed to an antenna  422 . 
     The design of UFT module  412  is shown in FIG.  6 . FM control signal  432  is accepted by a “square-up” circuit  602  to create a frequency modulated square wave  608  from the sinusoidal waveform of FM control signal  432 . FM square wave  608  is then routed to a pulse shaper  604  to create a string of pulses  610 . In one embodiment, pulse shaper  604  is a mono-stable multivibrator. The string of pulses  610  operates a switch  606  which creates rectangular waveform  434 . Typically, pulse shaper  604  is designed such that each pulse in string of pulses  610  has a pulse width “τ” that is substantially equal to (n/2)·T, where “T” is the period of desired output signal  436 , and “n” is any odd number. As stated previously, switch  606  outputs rectangular waveform  434 , which is then routed to filter  416  of FIG.  4 . Another input to UFT module  412  is bias signal  414 , which, in this embodiment, is connected to the opposite terminal of switch  606  from rectangular waveform  434 . 
     In one implementation of the invention, switch  606  is a field effect transistor (FET). A specific implementation wherein the FET is a complementary metal oxide semiconductor (CMOS) FET is shown is FIG. 9. A CMOS FET has three terminals: a gate  902 , a source  904 , and a drain  906 . String of pulses  610  is shown at gate  902 , bias signal  414  is shown at source  904 , and rectangular waveform  434  is shown at drain  906 . Those skilled in the relevant art(s) will appreciate that the source and drain of a FET are interchangeable, and that bias signal  414  could be at the drain  906 , with rectangular waveform  434  being at the source  904 . Numerous circuit designs are available to eliminate any possible asymmetry, and an example of such a circuit may be found in co-pending U.S. patent application entitled “Method and System for Frequency Up-Conversion,” application No. 09/176,154, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference. 
     FIG. 8 is a detailed schematic drawing of the embodiment described above. Those skilled in the relevant art(s) will appreciated that numerous circuit designs can be used, and that FIG. 8 is shown for illustrative purposes only, and is not limiting. In addition, there are a variety of commercially available components and assemblies suitable for use in the present invention (e.g., audio amplifiers, audio buffer amplifiers, crystal oscillators, drivers, and power amplifiers) as will be apparent to those skilled in the relevant art(s) based on the teachings contained herein. 
     Microphone  402  of FIG. 4 is shown as a microphone  802 . The output of microphone  802  is a voice signal which is routed to an audio amplifier  804  and then to an audio buffer amplifier  806 . A crystal oscillator  808  is driven by the output of audio buffer amplifier  806  to create the FM signal  430 . A bias voltage  810  combines with FM signal  430  to create the FM control signal  432 . FM control signal  432  is routed to a UFT module  812  which creates rectangular signal  434 . Also connected to UFT  812  is a bias signal  812 . Rectangular signal  434  is filtered by a filter  816  to remove the unwanted harmonics and results in desired output signal  436 . Desired output signal  436  goes to a driver  818  and then to a power amplifier  820 . The output of power amplifier  820  is amplified output signal  438 . Amplified output signal  438  is ready for transmission and is routed to an antenna  822 . 
     In the above implementation, looking back to FIG. 4, the frequency of FM control signal  432  is a sub-harmonic of the frequency of desired output signal  436 . It will be understood by those skilled in the relevant art(s) that the selection of the frequencies will have an impact on the amplitude of the desired output signal  436 , and will be a determinative factor as to whether or not driver  418  and/or power amplifier  420  will be needed. Similarly, those skilled in the relevant art(s)will understand that the selection of microphone  402  will have an effect on analog voice signal  424 , and will be a determinative factor as to whether or not audio amplifier  404  and/or audio buffer amplifier  406  will be needed. Additionally, those skilled in the relevant art(s) will understand that the specific design of UFT  412  will be a determinative factor as to whether or not bias voltage  410  is needed. 
     The invention described above is for an embodiment wherein the output of the microphone is described as an analog voice signal. Those skilled in the relevant art(s) will understand that the invention applies equally to a digital signal, either digital data or a voice signal that has been digitized. 
     Integrated Communication System 
     Additionally, it will be apparent to those skilled in the relevant art(s) based on the teachings contained herein that an integrated communication system will result by combining any two of the embodiments described above, or by combining all three of the embodiments described above. This integrated communication system can be employed, for example, in a transceiver used in a family radio system.