Abstract:
A Network-on-Chip (NoC) system employing an Advanced extensible Interface (AXI) protocol is provided. The NoC includes an NoC router which classifies data transmitted from a plurality of AXI Intellectual Properties (IPs) according to a destination AXI IP, and a network interface (NI) which processes data from the NoC router and provides the processed data to the destination IP. One of the NoC router and the NI includes a plurality of buffers which store data provided from each of the AXI IPs and classified according to each of the AXI IPs, and an interleaving manager which selects buffers, from which data is retrieved, among the plurality of buffers according to an interleaving acceptance capability which is a number of interleaving data that can be accepted by the destination AXI IP.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Korean Patent Application No. 10-2005-0097582, filed Oct. 17, 2005 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     Systems and methods consistent with the present invention relate to a Network-on-Chip (NoC) system employing the Advanced extensible Interface (AXI) protocol and an interleaving method thereof, and more particularly, to an NoC system employing the AXI protocol and an interleaving method thereof, capable of smoothly transmitting data according to the interleaving acceptance capability of an Intellectual Property (IP) when the AXI protocol is applied to the NoC.  
         [0004]     2. Description of the Related Art  
         [0005]     Coping with the convergence which gradually integrates computers, communications, and broadcast, demands on conventional Application Specific Integrated Circuit (ASIC) and Application Specific Standard Product (ASSP) have tended to move to System on Chip (SoC) designs. In addition, the light-weight, thin, and high-performance trends of information technology (IT) devices have become a factor accelerating SoC industry growth.  
         [0006]     The Soc is a technology-intensive semiconductor technology that implements a complicated system having several conventional functions in one chip. Various technologies are under study for SoC implementations, and, specifically, a method of connecting several Intellectual Properties (IPs) embedded in a chip is emerging as an important topic. Here, IP refers intellectual property cores which may be embedded on a chip. These IPs are reusable virtual components which may include both digital and analog circuitry, which perform specific functions (e.g. controllers, digital signal processing, graphics).  
         [0007]     A connection method based on a bus is typical of the technology for connecting IPs. However, in a bus structure, if a specific IP uses the bus, the other IP&#39;s cannot use the bus. Therefore, as the integration density of a chip becomes higher and the amount of information traffic between IPs is abruptly increased, the SoC using a bus structure without extensibility support encounters certain structural limitations thereof.  
         [0008]     As an approach for overcoming such structural limitations of the SoC using a bus structure, a NoC technology was newly proposed, which applies general network technologies within a chip to connect the IPs  
         [0009]     Further, there is an Advanced Microcontroller Bus Architecture (AMBA) by ARM which is a standard bus specification for connecting and managing the IPs in a SoC. The bus types of the AMBA include an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), and an AXI. Of the above, the AXI is an IP interface protocol, having advanced functions such as a multiple outstanding address function, a data interleaving function, and the like.  
         [0010]     When information is provided through address lines and data lines of a bus, a multiple outstanding address function is a function capable of transmitting an address for next data transmission before data is completely transmitted. When several masters transmit data to one slave, the data interleaving function allows the data to be interleaved with each other at the slave, thus allowing the more efficient utilization of a bandwidth as well as providing an advantage in respect of latency.  
         [0011]     When the AXI having such functions is implemented in the NoC as an interface protocol between each IP and a switch of an NoC, the structural limitations occurring at the SoC due to the characteristics of the bus can be overcome, so the speed and reusability upon data transmissions between IPs are expected to be increased.  
         [0012]     A paper entitled “An Efficient On-Chip NI Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration”, published January 2005 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and System by Philips proposes a network interface (NI) and packet formats for an NoC employing the AXI.  
         [0013]     However, the paper of Phillips only conceptually explains the devices for supporting the AXI, and focuses on the point that the AXI is used for connections between the NoC and the IP. Further, one burst is converted into one packet and then transmitted, so it is impossible to support not only diverse AXI functions such as a multiple outstanding address function, a data interleaving function, and a data reordering function but also Write strobes (WSTRB). Furthermore, when one burst is converted into one packet, the bandwidth utilization capability becomes lowered since the larger a burst size is, the longer the waiting time for converting the burst into the packet becomes.  
         [0014]     Meantime, if the AXI is applied to the NoC system, the master or slave can receive a data stream of one or more interleaved bursts or packets, according to a predetermined Interleaving Acceptance Capability (IAC).  
         [0015]     The interleaving acceptance capability is determined according to the performance of each slave or master, and the greater the interleaving acceptance capability, the more excellent the performance and the higher the price of the slave or master. Accordingly, the interleaving acceptance capability of each master or slave is limited depending on the performance of a device.  
         [0016]      FIG. 1A  is a view illustrating a process of interleaving the data transmitted by plural AXI masters and transmitting the interleaved data to an AXI slave  30  having interleaving acceptance capability of “2”.  
         [0017]     As shown in  FIG. 1A , the data transmitted by the AXI masters through an NoC router are transferred to an AXI slave  30  through an NI  20 . Since the interleaving acceptance capability of the AXI slave  30  is “2”, as shown in the first line, when the data packets from the AXI master M 1  and the AXI master M 2  are allowed to be transmitted in the interleaved manner, data are allowed to be transmitted. However, as shown in the second line, when three kinds of data packets transmitted from the AXI master M 1 , AXI master M 2 , and AXI master M 3  are interleaved, data transmission is not allowed. That is, when the AXI master and the AXI slave  30  transmit data to each other, the number of interleaved data packets or bursts must be smaller than or equal to the interleaving acceptance capability of the AXI master and the AXI slave  30 .  
         [0018]     As shown in  FIG. 1B , when the interleaving acceptance capability of the AXI slave  30  is “1”, there is a method, as a simplest method, of transmitting data from each AXI master in a the burst unit. However, as shown in  FIG. 1C , when a different kind of data is inserted between data packets transmitted from one AXI master, a deadlock occurs since it has the same effect as two kinds of data are interleaved.  
         [0019]     Accordingly, when the AXI is applied to an NoC system, a method is needed to be sought which can smoothly transmit data according to the interleaving acceptance capability.  
       SUMMARY OF THE INVENTION  
       [0020]     Exemplary embodiments of the present invention overcome the above disadvantages and other disadvantages not described above. Also, the present invention is not required to overcome the disadvantages described above, and an exemplary embodiment of the present invention may not overcome any of the problems described above.  
         [0021]     The present invention provides an NoC system employing AXI and an interleaving method thereof, capable of smoothly transmitting data according to the interleaving acceptance capability of an IP when the AXI protocol is applied to the NoC.  
         [0022]     According to an aspect of the present invention, there is provided an NoC system having an NoC router for classifying data transmitted from plural AXI IPs according to a destination AXI IP and an NI for processing data from the NoC router and providing the processed data to the destination IP, the NoC system employing AXI comprising, on one side of any of the NoC router and the NI, plural buffers for storing data provided from each AXI IP and classified according to each AXI IP; and an interleaving manager for selecting buffers, from which data is retrieved, out of the plural buffers according to interleaving acceptance capability which is the number of interleaving data that can be accepted by the destination AXI IP.  
         [0023]     During transmitting data by selecting at least one buffer according to the interleaving acceptance capability of the destination AXI IP, if all data stored in at least one of the selected buffers are completely transmitted, the interleaving manager can select another buffer containing data.  
         [0024]     If the number of data-containing buffers of the buffers is smaller than the interleaving acceptance capability of the destination AXI IP, the interleaving manager can decrease the number of buffers to be interleaved.  
         [0025]     The NoC system may further comprise a classifier installed at a front stage of the buffers for classifying data provided from the AXI IP according to the AXI IP. The classifier can be implemented with a demultiplexer.  
         [0026]     The NoC system may further comprise an output unit installed at a rear stage of the buffers for retrieving data from at least one of the buffers selected by the interleaving manager and providing the data to the destination AXI IP. The output unit can be implemented with a multiplexer.  
         [0027]     The number of buffers may be determined to be the same as the number of AXI IPs accessible to the destination AXI IP, so that the buffers match the AXI IPs in a one-to-one manner.  
         [0028]     A size of each buffer can be determined to be the same as a maximum value of a transmission unit that the AXI IP can transmit in one burst.  
         [0029]     A size of each buffer can be determined to be in a one-to-one match according to transmission capacity set for each AXI IP.  
         [0030]     According to another aspect of the present invention, there is provided an interleaving method for an NoC system employing AXI, comprising storing data transmitted from plural AXI IPs by classifying the data according to the plural AXI IP; selecting at least one buffer according to interleaving acceptance capability which is the number of interleaving data that can be accepted by a destination AXI IP; and retrieving data from the selected buffers, interleaving the retrieved data, and transmitting the interleaved data to a destination AXI IP. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]     The above and other aspects of the present invention will be more apparent by describing certain exemplary embodiments of the present invention with reference to the accompanying drawings, in which:  
         [0032]      FIG. 1A  is a view illustrating a process of interleaving data transmitted from plural AXI masters and transmitting the interleaved data to an AXI slave having interleaving acceptance capability of “2”;  
         [0033]      FIGS. 1B and 1C  are views illustrating the process of interleaving data transmitted from plural AXI masters and transmitting the interleaved data to an AXI slave having interleaving acceptance capability of “1”;  
         [0034]      FIG. 2  is a block diagram illustrating a configuration of an NoC router having an interleaving device therein according to an exemplary embodiment of the present invention;  
         [0035]      FIG. 3  is a block diagram illustrating a configuration of an NI having an interleaving device therein according to an exemplary embodiment of the present invention; and  
         [0036]      FIG. 4  is a block diagram illustrating a configuration of an interleaving device according to another exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0037]     Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.  
         [0038]     The interleaving device temporarily stores data received from each AXI master or AXI slave, which is an AXI IP, in a buffer, interleaves the data according to the interleaving acceptance capability of each AXI master and each AXI slave, and transmits the interleaved data. The interleaving device can be provided in either an NoC router or an NI of an NoC system. In the exemplary embodiments, description will be made on the interleaving device provided in the NoC router and on the interleaving device provided in the NI.  
         [0039]      FIG. 2  is a block diagram illustrating a configuration of an NoC router having an interleaving device therein according to an exemplary embodiment of the present invention.  
         [0040]     As shown in  FIG. 2 , an NoC router  110  includes a switch  113 , arbiter  111 , and interleaving device  140 , the NoC router switches and transmits plural data transmitted from plural AXI masters to an AXI slave  130  through an NI  120 .  
         [0041]     The switch  113  switches plural data input to the NoC router  110  and sequentially transfers the data to the interleaving device  140  one by one.  
         [0042]     The arbiter  111  controls the switch  113  on the basis of a predetermined certain reference so as to determine switching order for passing plural data received at the switch  113  from the plural AXI masters. The certain references that the arbiter  111  has include a priority method, a time-sequence method, and the like. The priority method refers to a method of assigning a priority to the plural AXI masters, and, if plural AXI masters input data, switching first the data received from the AXI master having the high priority. The time-sequence method refers to a method of unconditionally switching data in the first-come-first-serve manner, and can be combined with the priority method or the like if plural data are entered at the same time.  
         [0043]     The interleaving device  140  includes a classifier  141 , plural buffers  143 , output unit  145 , and interleaving manager  147 .  
         [0044]     The plural buffers  143  temporarily store data transmitted from the AXI masters, and can be implemented in as a First In First Out (FIFO) queue. The number of buffers  143  is determined by the number of AXI masters capable of accessing the AXI slave  130  connected to the NoC router  140  and transmitting data to the AXI slave. For example, if the AXI masters accessible to the AXI slave  130  are M 1 , M 2 , M 3 , M 4 , and M 5 , the number of buffers  143  becomes five. The length of such a buffer  143  can be arbitrarily determined by a designer, but may preferably be longer than a length of one burst or packet which is the minimum transmission unit.  
         [0045]     The classifier  141  classifies data entered through the switch  113 , and transfers the data to one of the plural buffers  143 . In here, the classifier  141  classifies the entered data by the AXI master that has transmitted the data, and transfers the data to a buffer  143  corresponding to the AXI master. The classifier  141  can be implemented with a demultiplexer.  
         [0046]     The output unit  145  retrieves burst or packet unit data from one or more buffers  143  selected according to the control of the interleaving manager  147 , and outputs the retrieved data so as to be interleaved. The output unit  145  can be implemented with a multiplexer.  
         [0047]     The interleaving manager  147  receives information on the interleaving acceptance capability from the AXI slave  130 , and controls the output device  145  to interleave and provide as many data as corresponding to the interleaving acceptance capability to the AXI slave  130 . The interleaving manager  147  decides whether data remains in each buffer  143  by detecting the remaining capacity of each buffer  143 , and selects as many buffers  143  as corresponding to the interleaving acceptance capability among the buffers  143  in which data remain. The reference for selecting buffers  143  can be set to a priority, a time sequence, and the like, as in the arbiter  111 . If all the data in any of the selected buffers  143  is transmitted to the AXI slave  130 , the interleaving manager  147  selects another buffer  143  in order for data therein to be interleaved.  
         [0048]     For example, if the interleaving acceptance capability of the AXI slave  130  is “2”, the interleaving manager  147  can select a maximum of two buffers  143 . If the interleaving manager  147  selects the buffers B 1  and B 2  of the buffers  143 , the output unit  145  interleaves and provides the data of the buffers B 1  and B 2  to the NI  120 . The buffer B 1  stores two data packets corresponding to one burst, and the buffer B 2  stores one data packet corresponding to one burst, so that the output unit  145  interleaves the two data packets of the buffer B 1  with one data packet of the buffer B 2  for an output. If the data are output, the buffer B 2  has no data therein, so the interleaving manager  147  has to select another buffer  143 . If the interleaving manager  147  selects the buffer B 4 , the output unit  145  interleaves and outputs the remaining data packets of the buffer B 1  with the data packets of the buffer B 4  to the NI  120 .  
         [0049]     The interleaving manager  147  decreases the number of buffers to be interleaved, if the number of buffers  143  containing data is smaller than the interleaving acceptance capability. For example, if the interleaving acceptance capability is “2” and the number of buffers  143  containing data is one, the interleaving manager  147  transmits the data of the corresponding buffer  143  to the AXI slave  130 . Further, if the interleaving acceptance capability is “3” and the number of buffers  143  containing data is two, the interleaving manager  147  interleaves and transmits only the data of the two buffers  143 .  
         [0050]      FIG. 3  is a block diagram illustrating a configuration of an NI having an interleaving device  140  according to an exemplary embodiment of the present invention. As shown in  FIG. 3 , the interleaving device  140  installed in the NI  120  is formed in the same configuration as that mounted in the NoC router  110 . Since the NI  120  is provided with data switched by the switch  113  of the NoC router  110 , the NI  120  does not need a separate switch  113  unlike the NoC router  110 .  
         [0051]     That is, the classifier  141  of the interleaving device  140  of the NI  120  classifies data provided from the NoC router  110  by AXI master, and provides the classified data to the buffer  143 . Then, the output unit  145  retrieves data from plural buffers  143  selected according to the control of the interleaving manager  147 , interleaves the retrieved data, and provides the interleaved data to the AXI slave  130 .  
         [0052]      FIG. 4  is a block diagram illustrating a configuration of an interleaving device according to another exemplary embodiment of the present invention. The interleaving device  140  of the present exemplary embodiment has buffers  143  which are different in size, unlike the interleaving device  140  shown in  FIGS. 2 and 3 .  
         [0053]     In general, the AXI master can implement a multiple outstanding address function, and the number of multiple outstanding bursts or packets is predetermined according to the AXI master&#39;s performance or characteristics. In the above, since data of plural bursts or packets can be transmitted at one time, it may be preferable to appropriately adjust the size of the buffer  143  of the interleaving device  140 .  
         [0054]     Accordingly, the size of each buffer  143  is determined according to the number of multiple outstanding bursts or packets of the AXI master corresponding to each buffer  143 . For example, if the numbers of multiple outstanding bursts or packets are 3, 2, 1, 2, and 1 as to the AXI masters M 1 , M 2 , M 3 , M 4 , and M 5  respectively, as shown in  FIG. 4 , the sizes of the buffers B 1 , B 2 , B 3 , B 4 , and B 5  corresponding to the AXI masters M 1 , M 2 , M 3 , M 4 , and M 5  are determined as 3, 2, 1, 2, and 1 burst or packet size.  
         [0055]     The process of determining the size of the buffer  143  as above can be performed in a software manner at the time when the interleaving device  140  is designed. For example, AXI masters accessible to one AXI slave  130  are identified, and the number of multiple outstanding bursts or packets of the identified AXI masters are detected. Next, each buffer  143  size is determined according to the detected number of multiple outstanding bursts or packets.  
         [0056]     Description will be made as below on the process of data transmission in an NoC system provided with the interleaving device  140  configured as above, with reference to  FIG. 2 .  
         [0057]     When data bursts or packets are input from the plural AXI masters to the NoC router  110 , the switch  113  of the NoC router  110  provides the classifier  141  of the interleaving device  140  with the data bursts or packets according to the control of the arbiter  111 .  
         [0058]     The classifier  141  transfers the data to the buffer  143  corresponding to the AXI master that has transmitted the data so that the buffer  143  stores the data. The interleaving manager  147  detects the interleaving acceptance capability of the AXI slave  130  and the remaining capacity of each buffer  143 , determines the number of buffers  143  to be interleaved according to the interleaving acceptance capability, and selects as many buffers  143  to be interleaved as the number of the determined buffers  143 .  
         [0059]     If the interleaving manager  147  selects the buffers  143 , the output unit  145  retrieves, interleaves, and transmits data packets or bursts from the selected buffers  143  to the NI  120 . If all the data stored in at least one of the buffers  143  selected during the transmissions of such data as the buffers  143  to be interleaved are transmitted, the interleaving manager  147  additionally selects another buffer  143 . Next, the output unit  145  interleaves the data of the selected buffers  143  with the data of the previously selected buffers  143 , and transmits the interleaved data to the NI  120 .  
         [0060]     For example, if the interleaving acceptance capability of the AXI slave  130  is “3”, the interleaving manager  147  selects three buffers  143 . If the interleaving manager  147  selects M 1 , M 3 , and M 5  of the buffers  143  in  FIG. 2 , the output unit  145  retrieves and transmits data from the corresponding buffers  143  to the NI  120 , so the data from the three buffers  143  are interleaved and provided to the NI  120 .  
         [0061]     The buffer M 1  stores two data packets corresponding to one burst, and the buffers M 3  and M 5  store one data packet corresponding to one burst respectively, so that, if the output unit retrieves and transmits one data packet from each of the buffers M 1 , M 2 , and M 3 , no data exist in the buffers M 3  and M 5 . Next, the interleaving manager  147  selects the buffers M 2  and M 4  instead of buffers M 3  and M 5 , and thus the output unit  145  interleaves the data packets of the buffers M 2  and M 4  with the data packet of the buffer M 1  and transmits the interleaved data.  
         [0062]     If the number of buffers  143  containing data becomes smaller than the interleaving acceptance capability during the data transmission as above, the interleaving manager  147  decreases the number of buffers to be selected.  
         [0063]     As above, if the interleaving device  140  is installed in either the NoC router  110  or the NI  120  of the NoC system, the data to be interleaved can be selected so as to meet the interleaving acceptance capability of the AXI master or AXI slave  130 . Accordingly, a deadlock can be prevented, which occurs when data transmissions are attempted from as many AXI masters or AXI slaves  130  as exceeding the interleaving acceptance capability when data are interleaved  
         [0064]     As aforementioned, the NoC system employing AXI protocol according to the exemplary embodiments of the present invention can select data to be transmitted to meet the interleaving acceptance capability of the IP and smoothly transmit the data, thereby enhancing the performance of the system.  
         [0065]     Further, the foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present invention can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments of the present invention is intended to be illustrative, and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.