Abstract:
A device and method capable of changing codes of a micro-controller comprises a micro-controller, an address latch, a flash memory, a static random access memory (SRAM), and a logic circuit. The flash memory has a renovation program and a general program recorded therein. The logic circuit can be a logic gate circuit, a programmable logic array, or a field programmable gate array. During a period of changing code, the renovation program of the flash memory controls the micro-controller to copy the renovation program itself into the SRAM and then makes the renovation program recorded in the SRAM control the micro-controller to replace the general program of the flash memory with a new program. Thereby, codes can be renewed without the need of replacing the original flash memory.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation-in-part of U.S. application Ser. No. 09/695970, filed on Oct. 26, 2000 and entitled “Device capable of changing codes of micro-controller”. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates to a device and a method capable of changing codes of a micro-controller and, more particularly, to a device and a method which can change the codes of an 8031 micro-controller via an additional circuit and a built-in renovation program without replacing the original flash memory.  
         BACKGROUND OF THE INVENTION  
         [0003]    As shown in FIG. 1, a conventional 8031 micro-controller system generally comprises an 8031 micro-controller  1 , an address latch  2 , a flash memory  3 , and a static random access memory (SRAM)  4 .  
           [0004]    The multiplex bus (AD 0 -AD 7 ) and the address latch enable (ALE) pin of the 8031 micro-controller  1  are respectively connected to the address latch  2  for storing address signals in the registers so as to facilitate the execution of reading and writing actions of the 8031 micro-controller  1 . The output of the address latch  2  is connected to both the flash memory  3  and the SRAM  4 . The outputs of the flash memory  3  and the SRAM  4  are connected to the multiplex bus (AD 0 -AD 7 ). The address bus (A 8 -A 15 ) of the 8031 micro-controller  1  is connected to both the flash memory  3  and the SRAM  4 . The write enable (WE) pin and the output enable (OE) pin of the SRAM  4  are respectively connected to the read (RD) pin and the write (WR) pin of the 8031 micro-controller  1 . The write enable (WE) pin and the output enable (OE) pin of the flash memory  3  are respectively connected to 5V and the program store enable (PSEN) pin of the 8031 micro-controller  1 .  
           [0005]    Due to property of the flash memory  3 , the flash memory  3  is used as a read only memory (ROM) for storing machine codes of the 8031 micro-controller  1 . It means that the flash memory  3  generally only can be read out but can&#39;t be written in when the 8031 micro-controller  1  fetches and executes machine codes. The SRAM  4  is the only place that the 8031 micro-controller  1  can write and retrieve data. Thus, the 8031 micro-controller  1  successively executes machine codes fetching from the flash memory  3 , and stores the operation results to the SRAM. If it is necessary to renew the content of the flash memory  3 , the only way is to replace the original flash memory with a new flash memory. Therefore, the cost will be relatively high.  
         SUMMARY OF THE INVENTION  
         [0006]    Accordingly, one object of the present invention is to provide a device and a method capable of changing codes of an 8031 micro-controller by using a renovation program and a logic circuit (a programmable logic array (PAL) or an field programmable gate array (FPGA)). The logic circuit is connected between the 8031 micro-controller, the flash memory, and the static random access memory (SRAM) of the 8031 micro-controller system. The codes recorded in the flash memory can be renewed via the cooperation of the renovation program and the logic circuit so that it is not necessary to replace the original memory.  
           [0007]    The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1 is a block diagram of a prior art 8031 micro-controller system.  
         [0009]    [0009]FIG. 2 is a block diagram of an 8031 micro-controller system of the present invention.  
         [0010]    [0010]FIG. 3 is a logic circuit of the present invention.  
         [0011]    [0011]FIG. 4 is an arrangement of the programs recorded in a flash memory complied with the present invention before the codes are updated.  
         [0012]    [0012]FIG. 5 is pseudo codes of the renovation program.  
         [0013]    [0013]FIG. 6 is an arrangement of the programs recorded in a SRAM complied with the present invention while the code updating is processed.  
         [0014]    [0014]FIG. 7 is an operation flow chart for upgrading the general program of the flash memory complied with the present invention.  
         [0015]    [0015]FIG. 8 is a schematic diagram of the running of the instruction pointer complied with the present invention.  
         [0016]    [0016]FIG. 9 is an arrangement of the programs recorded in a flash memory complied with the present invention after the codes are updated.  
         [0017]    [0017]FIG. 10 is also a schematic diagram of the running of the instruction pointer complied with the present invention.  
         [0018]    [0018]FIG. 11 is still a schematic diagram of the running of the instruction pointer complied with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]    As shown in FIGS. 2, a device capable of changing codes of a micro-controller according to the present invention comprises an 8031 micro-controller  1 , an address latch  2 , a flash memory  3 , a static random access memory (SRAM)  4 , and a logic circuit  5 .  
         [0020]    The multiplex bus (AD 0 -AD 7 ) and the address latch enable (ALE) pin of the 8031 micro-controller  1  are respectively connected to the address latch  2  for storing address signals in the registers so as to facilitate the execution of reading and writing actions of the 8031 micro-controller  1 . The output of the address latch  2  is connected to both the flash memory  3  and the SRAM  4 . The outputs of the flash memory  3  and the SRAM  4  are connected to the multiplex bus (AD 0 -AD 7 ). The address bus (A 8 -A 15 ) of the 8031 micro-controller  1  is connected to both the flash memory  3  and the SRAM  4 .  
         [0021]    The input terminals of the logic circuit  5  are respectively connected to the program store enable (PSEN) pin, the read (RD) pin, the write (WR) pin, and the seventh pin of port  1  (P1.7) of the 8031 micro-controller  1 , i.e., an output port pin of the 8031 micro-controller  1 . The output terminals (FWE, FOE, SWE, and SOE) of the logic circuit  5  are respectively connected to the write enable (WE) pin and the output enable (OE) pin of the flash memory  3  and the write enable (WE) pin and the output enable (OE) pin of the SRAM  4 .  
         [0022]    As shown in FIG. 3, the logic circuit  5  comprises a plurality of AND gates (AND  1 ˜AND  4 ), a plurality of OR gates (OR  1 ˜OR  4 ), and a plurality of inverters (NOT  1 ˜NOT  3 ). Also, the Boolean equations of the output terminals (FWE, FOE, SWE, and SOE) can be represented as following.  
           FEW=P 1.7 +WR    
           FOE=PSEN·P 1.7 +RD·{overscore (P1.7)}   
         
       SWE=WR+{overscore (P1.7)} 
     
           SOE=RD·P 1.7 +PSEN·{overscore (P1.7)}   
         [0023]    When the voltage of the P1.7 pin of the 8031 micro-controller  1  is high, i.e., P1.7=1, the outputs of the logic circuit  5  are: FWE=1, FOE=PSEN, SWE=WR, and SOE=RD. In this state, the device of the present invention operates at a general mode, which is the same as the operation of the conventional system.  
         [0024]    When the voltage of the P1.7 pin of the 8031 micro-controller  1  is low, i.e. P1.7=0, the outputs of the logic circuit  5  are: FWE=WR, FOE=RD, SWE=1, and SOE=PSEN. In this state, the device of the present invention operates at a renovation mode so as to upgrade the flash memory  3 . While P1.7=0, the 8031 micro-controller  1  fetches the machine codes from SRAM  4  and write operation results into the flash memory  3 . It means that in renovation mode, the role of the flash memory  3  is exchanged with that of the SRAM  4  so that the flash memory  3  is rewritable and the SRAM  4  is only readable.  
         [0025]    As shown in FIG. 4, the flash memory  3  stores a general program  31  and a renovation program  32 . The general program  31  and renovation program  32  are recorded within the address A˜B and Y˜Z of the flash memory  3 , respectively. In general mode, machine codes of the general program  31  are fetched and executed by the 8031 micro-controller  1 . The renovation program  32  is used when the general program  31  needs to be upgraded.  
         [0026]    As shown in FIG. 5, the pseudo codes of the renovation program is described. According to the invention, the first procedure is to copy a new program from outside interface (not shown) to the location between the address C and D of the SRAM. The second procedure is to copy the renovation program located between the address Y and Z of the flash memory to the location between the address Y and Z of the SRAM. The third procedure is to set the P1.7 pin to low. The fourth procedure is to copy the new program located between the address C and D of the SRAM to the flash memory starting at address A. The fifth procedure is to set the P1.7 pin to high. The sixth procedure is to jump to address A.  
         [0027]    [0027]FIG. 6 shows the content of the SRAM when the execution of the first and second procedures is completed. The new program  41  is stored within the address C-D of the SRAM  4 , and the renovation program  42  is stored within the address Y-Z of the SRAM  4 .  
         [0028]    Please refer to FIG. 7, which is the operation flow chart for upgrading the general program  31  of the flash memory  3  complied with the present invention. The operation steps are described as following:  
         [0029]    Step  610 : At the beginning of the upgrading process, the 8031 micro-controller  1  will be activated to execute the renovation program  32  recorded in the flash memory  3 .  
         [0030]    Step  620 : Then, the renovation program  32  will control the 8031 micro-controller  1  to copy a new program  41  from outside interface (not shown) to the SRAM  4 . In this embodiment, the new program  41  is recorded within the address C-D of the SDRM  4 .  
         [0031]    Step  630 : While the new program  31  is completely copied to the SRAM  4 , the renovation program  32  will control the 8031 micro-controller  1  to copy itself to the SRAM  4 . According to the present invention, the address space of the renovation program  42  in the SRAM  4  is identical to the address space of the renovation program  32  in the flash memory  3 , i.e., the renovation program  42  will be recorded within the address Y-Z of the SRAM  4 .  
         [0032]    Step  640 : After the renovation program  42  is written into the SRAM  4  completely, the renovation program  32  of the flash memory  3  will control the 8031 micro-controller  1  to change the P1.7 pin to low, i.e., P1.7=0. Therefore, the mode is changed to the renovation mode. As well, since the addresses of renovation program  32  of the flash memory  3  and the renovation program  42  of the SRAM  4  are the same and the instruction pointer of the 8031 micro-controller  1  always points to the next machine code, the 8031 micro-controller  1  will fetch and execute the next machine code stored in the renovation program  42  of the SRAM  4  instead of the next machine stored in renovation program  32  of the flash memory  3 . As shown in FIG. 8, it means that the instruction pointer of the 8031 micro-controller  1  will point to the next machine code recorded in the SRAM  4  after the P1.7 pin is changed to low.  
         [0033]    Step  650 : Then, the renovation program  42  recorded in the SRAM  4  will control the 8031 micro-controller  1  to copy the new program  41  from the SRAM  4  to the flash memory  3  for replacing the general program  31 . Please refer to FIG. 9. While the copying operation is completed, the new program  31 ′ will be recorded within the address A-B′.  
         [0034]    Step  660 : When the new program  41  is written to the flash memory  3  completely, the renovation program  42  recorded in the SRAM  4  will control the 8031 micro-controller  1  to change the P1.7 pin to high, i.e., P1.7=1. It means that the mode is changed to the general mode. As well, the 8031 micro-controller  1  will execute the renovation program  32  recorded in the flash memory  3  instead of the renovation program  42  recorded in the SRAM  4  to perform the next machine code. As shown in FIG. 10, it means that the instruction pointer of the 8031 micro-controller  1  will point to the next machine code of the renovation program  32  recorded in the flash memory  3  after the P1.7 pin is changed to high.  
         [0035]    Step  670 : Then, the renovation program  32  recorded in the flash memory  3  will make the 8031 micro-controller  1  operate with the new program  31 ′ recorded in the flash memory  3 . As shown in FIG. 11, the 8031 micro-controller  1  executes the last instruction “jump to address A”, then the instruction pointer return to the beginning point of the new program  31 ′ after this step is performed.  
         [0036]    To sum up, the machine codes of the 8031 micro-controller can be changed through the design of the present invention. Thereby, codes can be renewed without the need of replacing the original flash memory.  
         [0037]    Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.