Abstract:
A single phase three-level power converter can include a first half bridge and a second half bridge. A half bridge operation is implemented in either the first half bridge or second half bridge when outputting a single phase alternating current voltage having an amplitude a half or less than that of a direct current input voltage, and also, by alternately switching between the bridges carrying out the half bridge operation. In certain configurations, the power converter can convert a direct current input voltage into alternating current phase voltages having three levels of potential, which are positive, negative, and intermediate voltages, by controlling on-off conditions of a plurality of switch elements, and a controller that, by supplying gate signals to the switch elements configuring the first half bridge and second half bridge, controls the related on-off conditions.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to power conversion devices that convert direct current voltage to alternating current voltage, and in particular, to such devices that reduce loss in a single phase three-level power conversion device. 
     2. Related Art 
     With a view to reducing waveform distortion in an inverter device that converts direct current power to alternating current power, a three-level inverter type has been proposed (see, for example, Japanese Patent Publication Nos. JP-A-2008-178284 and JP-A-2007-28860). Hereafter, the configurations and actions of circuits disclosed in Japanese Patent Publication Nos. JP-A-2008-178284 and JP-A-2007-28860 will be described with reference to  FIGS. 9 to 11  as heretofore known examples of a single phase three-level inverter. 
       FIG. 9  is a circuit configuration diagram of the single phase three-level inverter disclosed in JP-A-2008-178284. The single phase three-level inverter, with a controller (CN)  6   a  controlling an on-off condition of switch elements configuring an inverter circuit (IC)  3   a , converts a direct current voltage 2E of a power source  1  into a single phase alternating current voltage, and supplies the single phase alternating current voltage to a load  5 . 
     In  FIG. 9 , a capacitor C 1  and capacitor C 2  are connected in series to either end of a power source  1 . The capacitor C 1  and capacitor C 2  configure a first direct current power source and second direct current power source. When the voltage of the power source  1  is 2E, the voltages of the capacitor C 1  and capacitor C 2  are each E. Also, a voltage detector (VD)  2  is connected to both ends of the power source  1 , and the voltage 2E of the power source  1  is detected by the voltage detector  2 . 
     Next, a series circuit in which switch elements  1   u  to  4   u  are connected in series is connected to both ends of a series circuit formed of the capacitor C 1  and capacitor C 2 . Diodes  1   x  to  4   x  are respectively connected in inverse parallel to the switch elements  1   u  to  4   u  configuring the series circuit. Also, diodes  5   x  and  6   x  are connected in series between the connection point of the switch elements  1   u  and  2   u  and the connection point of the switch elements  3   u  and  4   u . Furthermore, the connection point of the diodes  5   x  and  6   x  is connected to a connection point of the capacitors C 1  and C 2 . 
     Also, a series circuit in which switch elements  1   v  to  4   v  are connected in series is connected to both ends of the series circuit formed of the capacitor C 1  and capacitor C 2 . Diodes  1   y  to  4   y  are respectively connected in inverse parallel to the switch elements  1   v  to  4   v  configuring the series circuit. Also, diodes  5   y  and  6   y  are connected in series between the connection point of the switch elements  1   v  and  2   v  and the connection point of the switch elements  3   v  and  4   v . Furthermore, the connection point of the diodes  5   y  and  6   y  is connected to a connection point of the capacitors C 1  and C 2 . 
     Herein, the switch elements  1   u  to  4   u  and diodes  1   x  to  6   x  configure a first half bridge. The switch elements  1   v  to  4   v  and diodes  1   y  to  6   y  configure a second half bridge. Furthermore, the first half bridge and second half bridge configure the inverter circuit  3   a.    
     The connection point of the switch elements  2   u  and  3   u  is a U terminal, and the connection point of the switch elements  2   v  and  3   v  is a V terminal. The U terminal and V terminal are alternating current output terminals of the inverter circuit  3   a . A voltage detector (VD)  4  and the load  5  are connected in parallel between the U terminal and V terminal. 
     Next, the controller  6   a  outputs gate signals of the switch elements  1   u  to  4   u  and  1   v  to  4   v . In order to do this, the controller  6   a  includes an output voltage command unit  61 , a control computation unit  62 , and a first PWM controller  63   a.    
     Hereafter, a description will be given of actions of the controller  6   a . Firstly, the output voltage command unit  61  outputs the command value of a voltage to be applied by the inverter circuit  3   a  to the load. 
     The control computation unit  62  carries out an AVR computation with a PI regulator, or the like, so that an alternating current output voltage detected by the voltage detector  4  and the output voltage command output by the output voltage command unit  61  match. Furthermore, the control computation unit  62  computes a modulation signal for a PWM control by dividing the result of the AVR computation by a direct current input voltage detected by the voltage detector  2 . 
     The first PWM controller  63   a  carries out a size comparison of an internally generated carrier signal and the modulation signal output by the control computation unit  62 , and generates the gate signals of the switch elements  1   u  to  4   u  and  1   v  to  4   v . The gate signals are output to the inverter circuit  3   a.    
     The switch elements  1   u  to  4   u  and  1   v  to  4   v  are on-off controlled by the gate signals. As a result of this, a desired alternating current voltage is output between the U and V terminals of the inverter circuit  3   a.    
       FIG. 10  is a diagram showing an example of an output voltage waveform generated between the U and V terminals of the inverter circuit  3   a  shown in  FIG. 9 . As a single phase three-level inverter generally acts on a carrier frequency in the region of 10 kHz, the output voltage has a waveform more nearly sinusoidal. 
     Table 1 is a table showing voltages output between the U and V terminals of the inverter circuit  3   a  corresponding to combinations of on-off conditions of the switch elements  1   u  to  4   u  and  1   v  to  4   v . By repeating mode  1  to mode  8  shown in Table 1, a voltage with the waveform shown in  FIG. 10  is output between the U and V terminals of the inverter circuit  3   a . As shown in  FIG. 10  and Table 1, the output voltage of the inverter circuit  3   a  is of five levels, 0, E, 2E, −E, and −2E. 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                   
                   
                 Voltage 
               
               
                   
                 First Half Bridge 
                 Second Half Bridge 
                 Between U 
               
             
          
           
               
                   
                   
                   
                   
                   
                 U Terminal 
                   
                   
                   
                   
                 V Terminal 
                 and V 
               
               
                   
                 1u 
                 2u 
                 3u 
                 4u 
                 Voltage 
                 1v 
                 2v 
                 3v 
                 4v 
                 Voltage 
                 Terminals 
               
               
                   
                   
               
             
          
           
               
                 Mode 1 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 0 
               
               
                 Mode 2 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 E 
               
               
                 Mode 3 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 2E 
               
               
                 Mode 4 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 E 
               
               
                 Mode 5 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 0 
               
               
                 Mode 6 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 −E 
               
               
                 Mode 7 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 −2E 
               
               
                 Mode 8 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 −E 
               
               
                   
               
             
          
         
       
     
       FIG. 11  is a circuit configuration diagram of the single phase three-level inverter disclosed in Japanese Patent Publication No. JP-A-2007-28860. The single phase three-level inverter of  FIG. 11 , with a controller (CN)  6   b  controlling an on-off condition of switch elements configuring an inverter circuit (IC)  3   b , converts a direct current voltage 2E of a power source  1  into a single phase alternating current voltage, and supplies the single phase alternating current voltage to a load  5 . 
     A power source  1 , and a first direct current power source and second direct current power source formed of capacitors C 1  and C 2 , are the same as in the heretofore known example shown in  FIG. 9 . A voltage detector  2  is connected to both ends of the power source  1 , and a voltage 2E of the power source  1  is detected by the voltage detector  2 . 
     Next, switch elements  1   u  and  4   u  are connected in series to both ends of a series circuit formed of the capacitor C 1  and capacitor C 2 , and a circuit in which switch elements  2   u  and  3   u  having reverse withstand voltage are connected in inverse parallel is connected between a connection point of the switch elements  1   u  and  4   u  and a connection point of the capacitors C 1  and C 2 . Diodes  1   x  and  4   x  are connected in inverse parallel to the switch elements  1   u  and  4   u  respectively. 
     Also, switch elements  1   v  and  4   v  are connected in series to both ends of a series circuit formed of the capacitor C 1  and capacitor C 2 , and a circuit in which switch elements  2   v  and  3   v  having reverse withstand voltage are connected in inverse parallel is connected between a connection point of the switch elements  1   v  and  4   v  and a connection point of the capacitors C 1  and C 2 . Diodes  1   y  and  4   y  are connected in inverse parallel to the switch elements  1   v  and  4   v  respectively. 
     Herein, the switch elements  1   u  to  4   u  and diodes  1   x  and  4   x  configure a first half bridge. Also, the switch elements  1   v  to  4   v  and diodes  1   y  and  4   y  configure a second half bridge. Furthermore, the first half bridge and second half bridge configure the inverter circuit  3   b.    
     The connection point of the switch elements  1   u  and  4   u  is a U terminal, and the connection point of the switch elements  1   v  and  4   v  is a V terminal. The U terminal and V terminal are alternating current output terminals of the inverter circuit  3   b . A voltage detector  4  and the load  5  are connected in parallel between the U terminal and V terminal. 
     Next, the controller  6   b  outputs gate signals of the switch elements  1   u  to  4   u  and  1   v  to  4   v . In order to do this, the controller  6   b  includes an output voltage command unit  61 , a control computation unit  62 , and a first PWM controller  63   b.    
     Hereafter, a description will be given of actions of the controller  6   b . Of the components of the controller  6   b , the output voltage command unit  61  and control computation unit  62  are the same as in the single phase three-level inverter shown in  FIG. 9 . 
     The first PWM controller  63   b  carries out a size comparison of an internally generated carrier signal and a modulation signal output by the control computation unit  62 , and generates the gate signals of the switch elements  1   u  to  4   u  and  1   v  to  4   v . The on-off conditions of the switch elements  1   u  to  4   u  and  1   v  to  4   v  are controlled by the gate signals, and a desired alternating current voltage is output between the U and V terminals of the inverter circuit  3   b.    
     Table 2 is a table showing voltages output between the U and V terminals of the inverter circuit  3   b  corresponding to combinations of the on-off conditions of the switch elements  1   u  to  4   u  and  1   v  to  4   v  configuring the inverter circuit  3   b . By repeating mode  1  to mode  8  shown in Table 2, a voltage with a waveform the same as the waveform shown in  FIG. 10  is output between the U and V terminals of the inverter circuit  3   b . As shown in  FIG. 10  and Table 2, the output voltage of the inverter circuit  3   b  shown in  FIG. 11  is also of five levels, 0, E, 2E, −E, and −2E. 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
             
             
               
                   
                   
               
               
                   
                   
                   
                 Voltage 
               
               
                   
                 First Half Bridge 
                 Second Half Bridge 
                 Between U 
               
             
          
           
               
                   
                   
                   
                   
                   
                 U Terminal 
                   
                   
                   
                   
                 V Terminal 
                 and V 
               
               
                   
                 1u 
                 2u 
                 3u 
                 4u 
                 Voltage 
                 1v 
                 2v 
                 3v 
                 4v 
                 Voltage 
                 Terminals 
               
               
                   
                   
               
             
          
           
               
                 Mode 1 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 0 
               
               
                 Mode 2 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 E 
               
               
                 Mode 3 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 2E 
               
               
                 Mode 4 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 E 
               
               
                 Mode 5 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 0 
               
               
                 Mode 6 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 −E 
               
               
                 Mode 7 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 −2E 
               
               
                 Mode 8 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 −E 
               
               
                   
               
             
          
         
       
     
     However, in the heretofore known examples, the single phase three-level inverter carries out a switching action in full bridge mode regardless of the size of the alternating current output voltage. That is, as shown in Table 1 and Table 2, all the switch elements ( 1   u  to  4   u  and  1   v  to  4   v ) configuring the first half bridge and second half bridge alternate on and off conditions. Because of this, there is a problem in that conduction loss and switching loss occur in all the switch elements, and conduction loss and reverse recovery loss occur in all the diodes. 
     SUMMARY OF THE INVENTION 
     Therefore, embodiments of the invention, having been contrived in order to address one or more of the heretofore described problem, have an object of reducing loss occurring in an inverter circuit by causing a single phase three-level inverter that normally acts in full bridge mode to act in half bridge mode when the amplitude of a fundamental wave of an alternating current output voltage is lower than a voltage E of a first direct current power source and a second direct current power source. 
     A power conversion device of one aspect of the invention includes an inverter circuit formed of a first half bridge and a second half bridge, and a controller that generates gate signals of switch elements configuring the first and second half bridges, wherein the controller includes a first PWM controller that generates gate signals for causing the inverter circuit to act in full bridge mode, a second PWM controller that generates gate signals for causing the inverter circuit to act in half bridge mode, and a gate signal switching unit that switches between the output of the first PWM controller and the output of the second PWM controller. 
     Then, the controller outputs the output of the second PWM controller as the gate signals of the inverter circuit when the amplitude of the fundamental wave of the alternating current output voltage is lower than the voltage E of the first direct current power source and second direct current power source. 
     Also, the controller includes a bridge switching unit. The bridge switching unit outputs a signal for switching to the bridge to be caused to carry out a switching action. The signal output by the bridge switching unit is used in the second PWM controller in a process of interchanging the gate signals of the first half bridge and second half bridge. 
     According to embodiments of the invention, it is possible to obtain a desired alternating current output voltage by causing a single phase three-level inverter to act in half bridge mode when the amplitude of a fundamental wave of an alternating current output voltage is lower than a voltage E of a first direct current power source and a second direct current power source. Furthermore, as the single phase three-level inverter is caused to act in half bridge mode, it is possible to reduce by half the number of switch elements carrying out a switching action compared with when causing the inverter to act in full bridge mode. Because of this, it is possible to reduce loss occurring in the inverter circuit. 
     In particular, it is possible to effectively utilize the above benefit in a single phase three-level inverter used in an application variably controlling output voltage between 0V and a rated voltage, or an application in which direct current input voltage fluctuates considerably. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit configuration diagram of a power conversion device according to a first embodiment of the invention; 
         FIG. 2  is an output voltage waveform of a three-level inverter according to the first embodiment; 
         FIG. 3  is a diagram illustrating an action of mode  1  in the first embodiment; 
         FIG. 4  is a diagram illustrating an action of mode  3  in the first embodiment; 
         FIG. 5  is a circuit configuration diagram of a power conversion device according to a second embodiment of the invention; 
         FIG. 6  is a diagram illustrating an action of mode  1  in the second embodiment; 
         FIG. 7  is a diagram illustrating an action of mode  3  in the second embodiment; 
         FIG. 8  is a block diagram showing another embodiment of a controller according to the invention; 
         FIG. 9  is a circuit configuration diagram showing an example of a heretofore known power conversion device; 
         FIG. 10  is a diagram showing an output voltage waveform of the heretofore known power conversion device; and 
         FIG. 11  is a circuit configuration diagram showing another example of a heretofore known power conversion device. 
     
    
    
     DETAILED DESCRIPTION 
     Hereafter, a detailed description will be given of certain embodiments of the invention, based on  FIGS. 1 to 8 . Components in  FIGS. 1 to 8  the same as components shown in  FIGS. 9 and 11 , which are examples of embodiments of a heretofore known power conversion device, are given the same reference numerals and characters, and a description thereof is omitted. 
       FIG. 1  is a circuit diagram showing the configuration of a single phase three-level inverter according to a first embodiment of the invention. A feature of the first embodiment is that, of components of a heretofore known single phase three-level inverter shown in  FIG. 9 , a controller  6   a  is made a controller  6   a ′, while other components are the same. 
     Hereafter, a description will be given of the configuration and actions of the controller  6   a ′. The controller  6   a ′ includes an output voltage command unit  61 , a control computation unit  62 , and a first PWM controller  63   a , in the same way as the controller  6   a , and furthermore, includes a second PWM controller  64   a  and a gate signal selector (GS)  65 . 
     Herein, the first PWM controller  63   a , with a modulation signal output by the control computation unit  62  as an input, generates gate signals for on-off controlling switch elements  1   u  to  4   u  and  1   v  to  4   v  configuring an inverter circuit  3   a  in full bridge mode, in the same way as in the heretofore known single phase three-level inverter shown in  FIG. 9 . 
     Also, the second PWM controller  64   a , with a modulation signal output by the control computation unit  62  as an input, generates gate signals for on-off controlling the switch elements  1   u  to  4   u  and  1   v  to  4   v  configuring the inverter circuit (IC)  3   a  in half bridge mode. 
     The gate signal selector  65  selects either the output signal of the first PWM controller  63   a  or the output signal of the second PWM controller  64   a , and outputs the selected signal as the gate signals of the inverter circuit  3   a.    
     When determining which of the output signal of the first PWM controller  63   a  and the output signal of the second PWM controller  64   a  to select, the voltage of a power source  1  detected by a voltage detector  2  and an output voltage command output by the output voltage command unit  61  are referred to. 
     For example, when the amplitude of a fundamental wave of an alternating current output voltage is higher than a voltage E of a first direct current power source and second direct current power source, the gate signal selector  65  outputs the output of the first PWM controller  63   a  as the gate signals. Meanwhile, when the amplitude of the fundamental wave of the alternating current output voltage is lower than the voltage E of the first direct current power source and second direct current power source, the gate signal selector  65  outputs the output of the second PWM controller  64   a  as the gate signals. 
     The inverter circuit  3   a  acts in full bridge mode when the output of the first PWM controller  63   a  is output as the gate signals from the gate signal selector  65 , and acts in half bridge mode when the output of the second PWM controller  64   a  is output as the gate signals. 
       FIG. 2  is a diagram showing an example of an output voltage waveform generated between U and V terminals when the inverter circuit  3   a  shown in  FIG. 1  acts in half bridge mode. Table 3 is an example showing output voltages corresponding to combinations of on-off conditions of the switch elements  1   u  to  4   u  and  1   v  to  4   v  when the inverter circuit  3   a  acts in half bridge mode in a first half bridge. As shown in  FIG. 2  and Table 3, the voltage output between the U and V terminals of the inverter circuit  3   a  is of three levels, 0, E, and −E. 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
             
             
               
                   
                   
               
               
                   
                   
                   
                 Voltage 
               
               
                   
                 First Half Bridge 
                 Second Half Bridge 
                 Between U 
               
             
          
           
               
                   
                   
                   
                   
                   
                 U Terminal 
                   
                   
                   
                   
                 V Terminal 
                 and V 
               
               
                   
                 1u 
                 2u 
                 3u 
                 4u 
                 Voltage 
                 1v 
                 2v 
                 3v 
                 4v 
                 Voltage 
                 Terminals 
               
               
                   
                   
               
             
          
           
               
                 Mode 1 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 E 
               
               
                 Mode 2 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 0 
               
               
                 Mode 3 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 −E 
               
               
                 Mode 4 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
       FIG. 3  is a diagram illustrating, of the half bridge actions of the inverter circuit  3   a  shown in  FIG. 1 , the action of mode  1  shown in  FIG. 2  and Table 3. Mode  1  is a mode in which the voltage between the U and V terminals of the inverter circuit  3   a  becomes E. 
     As shown in Table 3, the second half bridge switch elements  1   v  and  4   v  are always in an off condition, and the switch elements  2   v  and  3   v  are always in an on condition. Consequently, when the first half bridge switch elements  1   u  and  2   u  are simultaneously in an on condition ( 3   u  and  4   u  are in an off condition), the voltage E of the first direct current power source (a capacitor C 1 ) is applied to a load  5  along a path from the capacitor C 1  through the switch elements  1   u  and  2   u , load  5 , switch element  3   v , and a diode  6   y , to the capacitor C 1  ( FIG. 3 ). 
       FIG. 4  is a diagram illustrating, of the half bridge actions of the inverter circuit  3   a  shown in  FIG. 1 , the action of mode  3  shown in  FIG. 2  and Table 3. Mode  3  is a mode in which the voltage between the U and V terminals of the inverter circuit  3   a  becomes −E. 
     As shown in Table 3, the second half bridge switch elements  1   v  and  4   v  are always in an off condition, and the switch elements  2   v  and  3   v  are always in an on condition. Consequently, when the first half bridge switch elements  3   u  and  4   u  are simultaneously in an on condition ( 1   u  and  2   u  are in an off condition), the voltage E of the second direct current power source (a capacitor C 2 ) is applied to the load  5  along a path from the capacitor C 2  through a diode  5   y , the switch element  2   v , load  5 , and switch elements  3   u  and  4   u , to the capacitor C 2  ( FIG. 4 ). 
     When in mode  2  and mode  4 , the first half bridge and second half bridge switch elements  2   u ,  3   u ,  2   v , and  3   v  are in an on condition, and the switch elements  1   u ,  4   u ,  1   v , and  4   v  are in an off condition. Consequently, the voltage between the U and V terminals of the inverter circuit  3   a  becomes 0V. 
     The controller  6   a ′, by causing the inverter circuit  3   a  to act in half bridge mode based on pulse width modulated gate signals in this way, can output an alternating current voltage between the U and V terminals. 
     According to the above, when causing the inverter circuit  3   a  to act in half bridge mode in the first half bridge, a conduction loss occurs only in the switch elements  2   v  and  3   v  in the second half bridge, and no conduction loss occurs in the switch elements  1   v  and  4   v . Also, no switching loss occurs in any of the switch elements  1   v  to  4   v  configuring the second half bridge. 
     Consequently, compared with when causing the inverter circuit  3   a  to act in full bridge mode in the first half bridge and second half bridge, it is possible to reduce the loss of the inverter circuit  3   a . As a result of this, it is possible to improve the efficiency of the inverter circuit  3   a.    
       FIG. 5  is a circuit diagram showing the configuration of a single phase three-level inverter according to a second embodiment of the invention. A feature of the second embodiment is that, of components of a heretofore known single phase three-level inverter shown in  FIG. 11 , a controller  6   b  is made a controller  6   b ′, while other components are the same. 
     Hereafter, a description will be given of the configuration and actions of the controller  6   b ′. The controller  6   b ′ includes an output voltage command unit  61 , a control computation unit  62 , and a first PWM controller  63   b , in the same way as the controller  6   b , and furthermore, includes a second PWM controller  64   b  and a gate signal selector  65 . 
     Herein, the first PWM controller  63   b , with a modulation signal output by the control computation unit  62  as an input, generates gate signals for on-off controlling switch elements  1   u  to  4   u  and  1   v  to  4   v  configuring an inverter circuit  3   b  in full bridge mode, in the same way as in the heretofore known single phase three-level inverter shown in  FIG. 11 . 
     Also, the second PWM controller  64   b , with a modulation signal output by the control computation unit  62  as an input, generates gate signals for on-off controlling the switch elements  1   u  to  4   u  and  1   v  to  4   v  configuring the inverter circuit  3   b  in half bridge mode. 
     The gate signal selector  65  selects either the output signal of the first PWM controller  63   b  or the output signal of the second PWM controller  64   b , and outputs the selected signal as the gate signals of the inverter circuit  3   b.    
     When determining which of the output signal of the first PWM controller  63   b  and the output signal of the second PWM controller  64   b  to select, the voltage of a power source  1  detected by a voltage detector  2  and an output voltage command output by the output voltage command unit  61  are referred to. 
     For example, when the amplitude of a fundamental wave of an alternating current output voltage is higher than a voltage E of a first direct current power source and second direct current power source, the gate signal selector  65  outputs the output of the first PWM controller  63   b  as the gate signals. Meanwhile, when the amplitude of the fundamental wave of the alternating current output voltage is lower than the voltage E of the first direct current power source and second direct current power source, the gate signal selector  65  outputs the output of the second PWM controller  64   b  as the gate signals. 
     The inverter circuit  3   b  acts in full bridge mode when the output of the first PWM controller  63   b  is output as the gate signals from the gate signal selector  65 , and acts in half bridge mode when the output of the second PWM controller  64   b  is output as the gate signals. 
     When the inverter circuit  3   b  acts in half bridge mode, the waveform of an output voltage generated between U and V terminals is the same as that in  FIG. 2 . Table 4 is an example showing output voltages corresponding to combinations of on-off conditions of the switch elements  1   u  to  4   u  and  1   v  to  4   v  when the inverter circuit  3   b  acts in half bridge mode in a first half bridge. As shown in  FIG. 2  and Table 4, the voltage output between the U and V terminals of the inverter circuit  3   b  is of three levels, 0, E, and −E. 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 4 
               
             
             
               
                   
                   
               
               
                   
                   
                   
                 Voltage 
               
               
                   
                 First Half Bridge 
                 Second Half Bridge 
                 Between U 
               
             
          
           
               
                   
                   
                   
                   
                   
                 U Terminal 
                   
                   
                   
                   
                 V Terminal 
                 and V 
               
               
                   
                 1u 
                 2u 
                 3u 
                 4u 
                 Voltage 
                 1v 
                 2v 
                 3v 
                 4v 
                 Voltage 
                 Terminals 
               
               
                   
                   
               
             
          
           
               
                 Mode 1 
                 On 
                 On 
                 Off 
                 Off 
                 E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 E 
               
               
                 Mode 2 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 0 
               
               
                 Mode 3 
                 Off 
                 Off 
                 On 
                 On 
                 −E 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 −E 
               
               
                 Mode 4 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
       FIG. 6  is a diagram illustrating, of the half bridge actions of the inverter circuit  3   b  shown in  FIG. 5 , the action of mode  1  shown in  FIG. 2  and Table 4. Mode  1  is a mode in which the voltage between the U and V terminals of the inverter circuit  3   b  becomes E. 
     As shown in Table 4, the second half bridge switch elements  1   v  and  4   v  are always in an off condition, and the switch elements  2   v  and  3   v  are always in an on condition. Consequently, when the first half bridge switch element  1   u  is in an on condition ( 4   u  is in an off condition), the voltage E of the first direct current power source is applied to a load  5  along a path from a capacitor C 1  through the switch element  1   u , load  5 , and switch element  3   v , to the capacitor C 1  ( FIG. 6 ). 
       FIG. 7  is a diagram illustrating, of the half bridge actions of the inverter circuit  3   b  shown in  FIG. 5 , the action of mode  3  shown in  FIG. 2  and Table 4. Mode  3  is a mode in which the voltage between the U and V terminals of the inverter circuit  3   b  becomes −E. 
     As shown in Table 4, the second half bridge switch elements  1   v  and  4   v  are always in an off condition, and the switch elements  2   v  and  3   v  are always in an on condition. Consequently, when the first half bridge switch element  4   u  is in an on condition ( 1   u  is in an off condition), the voltage E of the second direct current power source is applied to the load  5  along a path from a capacitor C 2  through the switch element  2   v , load  5 , and switch element  4   u , to the capacitor C 2  ( FIG. 7 ). 
     When in mode  2  and mode  4 , the first half bridge and second half bridge switch elements  2   u ,  3   u ,  2   v , and  3   v  are in an on condition, and the switch elements  1   u ,  4   u ,  1   v , and  4   v  are in an off condition. Consequently, the voltage between the U and V terminals of the inverter circuit  3   b  becomes 0V. 
     The controller  6   b ′, by causing the inverter circuit  3   a  to act in half bridge mode based on pulse width modulated gate signals in this way, can output an alternating current voltage between the U and V terminals. 
     According to the above, when causing the inverter circuit  3   b  to act in half bridge mode in the first half bridge, a conduction loss occurs only in the switch elements  2   v  and  3   v  in the second half bridge, and no conduction loss occurs in the switch elements  1   v  and  4   v . Also, no switching loss occurs in any of the switch elements  1   v  to  4   v  configuring the second half bridge. 
     Consequently, compared with when causing the inverter circuit  3   b  to act in full bridge mode in the first half bridge and second half bridge, it is possible to reduce the loss of the inverter circuit  3   b . As a result of this, it is possible to improve the efficiency of the inverter circuit  3   b.    
     Even when replacing each of the switch elements  2   u ,  3   u ,  2   v , and  3   v  in  FIG. 5  with a circuit in which a switch element and diode are connected in series, it is possible to cause the inverter circuit  3   b  to act in half bridge mode, and it is possible to reduce loss. 
     Also, even when replacing each of the circuit in which the switch elements  2   u  and  3   u  are connected in inverse parallel and the circuit in which the switch elements  2   v  and  3   v  are connected in inverse parallel in  FIG. 5  with a circuit in which circuits in which a switch element and diode are connected in inverse parallel are connected in anti-series, it is possible to cause the inverter circuit  3   b  to act in half bridge mode, and it is possible to reduce loss. 
     Also, in the first embodiment and second embodiment, a description has been given using as an example a case in which a desired output voltage is obtained between the U and V terminals of the inverter circuits  3   a  and  3   b  by causing the inverter circuit to act in half bridge mode in the first half bridge, but it is also possible to reduce the loss of the inverter circuits  3   a  and  3   b  in the same way by causing the inverter circuit to act in half bridge mode in the second half bridge. 
     As a more preferred embodiment, it is possible, when causing the inverter circuits  3   a  and  3   b  to act in half bridge mode, to cause the first half bridge and second half bridge to act in half bridge mode alternately, for example, every half cycle of the alternating current output voltage.  FIG. 8  shows the configuration of a controller (CN)  6   c  as a third embodiment for enabling this kind of action. To describe using the first embodiment as an example, a feature of the controller  6   c  is that a bridge switching unit  66  is further provided in the configuration of the controller  6   a ′ of  FIG. 1 . 
     The bridge switching unit  66 , based on an output voltage command output by the output voltage command unit  61 , outputs a signal specifying the bridge to be caused to act in half bridge mode. For example, the bridge switching unit  66  outputs a signal specifying the first half bridge when the polarity of the output voltage command is positive, and outputs a signal specifying the second half bridge when the polarity of the output voltage command is negative. 
     The second PWM controller  64   a , based on the bridge specification signal output by the bridge switching unit  66 , outputs gate signals for causing either the first half bridge or second half bridge to act in half bridge mode. 
     Specifically, when the bridge specification signal specifies the first half bridge, the second PWM controller  64   a  outputs gate signals corresponding to the on-off condition of the switch elements  1   u  to  4   u  and  1   v  to  4   v  corresponding to mode  1  to mode  4  shown in Table 3 as the gate signals of the first half bridge and second half bridge. 
     Meanwhile, when the bridge specification signal specifies the second half bridge, the second PWM controller  64   a  transposes the gate signals corresponding to the on-off condition of the switch elements  1   u  to  4   u  and  1   v  to  4   v  corresponding to mode  1  to mode  4  shown in Table 3, and outputs them as the gate signals of the first half bridge and second half bridge. 
     By switching the actions of the first half bridge and second half bridge in this way, loss occurs evenly in the switch elements and diodes of the first half bridge and second half bridge, and it is possible to average heat duty between the bridges. 
     As a result of this, it is possible to standardize the cooling design of the first half bridge and second half bridge, and it is also possible to reduce the price by standardizing the cooling member. 
     The controller  6   c  can also be applied to the second embodiment, and it is possible to obtain the same advantage as that heretofore described. 
     Examples of specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the above description, specific details are set forth in order to provide a thorough understanding of embodiments of the invention. Embodiments of the invention may be practiced without some or all of these specific details. Further, portions of different embodiments can be combined, as would be understood by one of skill in the art. 
     This application is based on, and claims priority to, Japanese Patent Application No. 2010-164735, filed on Jul. 22, 2010. The disclosure of the priority application, in its entirety, including the drawings, claims, and the specification thereof, is incorporated herein by reference.