Abstract:
A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.

Description:
[0001]    The present application claims priority to U.S. Provisional Patent Application Ser. No. 60/296,617 filed Jun. 7, 2001. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The present invention generally relates to the fabrication of semiconductor devices from substrates, and relates in particular to the use of strained silicon (Si) heterostructure substrates in forming devices such as transistors for example for high-performance CMOS integrated circuit products.  
           [0003]    As microelectronic devices require faster operating speeds and increased computing power, the need exists for transistor circuits to provide a greater complexity of transistors in a smaller amount of circuit real estate. Such microelectronic devices include, for example, microprocessors, ASICs, embedded controllers, and FPGAs. Each microelectronic device consists of millions of transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), that are designed to provide control over both the directional flow of electrons and the speed at which the electrons move through the circuits.  
           [0004]    MOSFETs are conventionally fabricated on Si substrates, which are the basic starting substrates on which semiconductor circuits are built. In order to create a MOSFET device on a Si substrate, a very thin layer of insulator is thermally grown or deposited on the Si substrate followed by a polysilicon gate electrode definition to create a MOSFET device. Typically this insulator is SiO 2 , or SiO 2  with a significant fraction of nitrogen, and so the insulator is typically referred to as the gate oxide. The thickness of the gate oxide can determine the threshold voltage that must be applied to the gate of a MOSFET to turn on the MOSFET device. The gate oxide thickness is used to define the MOSFET application. For example, high-performance microprocessors have core logic devices with ultra-thin (e.g., 10-20 Å) gate oxides and input/output devices with thicker gate oxides (e.g., 20-100 Å). As the operational speed of electrical systems has increased, it has become necessary to have MOSFET devices with different gate oxide thicknesses on the same chip.  
           [0005]    Conventional oxidation techniques for thermally growing oxide layers on a Si substrate typically involve the consumption of a significant portion of the Si substrate. For example, the amount of Si substrate that is lost in the oxidation process may be approximately one half of the thickness of the resulting thermally grown oxide layer.  
           [0006]    Strained silicon heterostructures provide semiconductor devices with enhanced electron mobility and therefore speed. For example, see U.S. Pat. No. 5,442,205. Strained silicon heterostructure substrates typically include a relatively thin (e.g., less than 250Å) strained silicon layer that may be used as the channel in a MOSFET device. If the layer of strained silicon is grown too thick, misfit dislocation defects will occur in the layer, compromising the yield (percentage of functional devices) when MOSFET circuits are fabricated on the substrate. In particular, at a critical thickness, dislocations are favored for strain relief of the epitaxial film over continued accumulation of strain energy. The critical thickness is a function of the lattice mismatch between the epitaxial film and substrate, as well as the materials properties of both the epitaxial layer and the substrate. It is this critical thickness that may limit the useful strained silicon film thickness to less than, e.g., 250Å.  
           [0007]    If too much of the strained silicon layer is consumed in the oxidation process, then the layer will be too thin to obtain the benefits of the enhanced electron mobility. The minimum strained silicon film thickness required for significant mobility enhancement is approximately 50Å. Conventional methods of forming multiple gate oxides do not work well on a strained Si substrate since the strained Si cap layer may be too thin to support the formation of both thick and thin gate oxides. This is particularly the case since during a typical MOSFET fabrication process, there is much additional strained Si consumption due to various processing steps (cleans, thermal oxidations, anneals).  
           [0008]    There is a need, therefore, for a method of forming strained silicon heterostructure substrates having a plurality of gate oxide thicknesses without sacrificing the enhance electron mobility of the substrates.  
         SUMMARY OF THE INVENTION  
         [0009]    The invention provides a method for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulator on the strained semiconductor heterostructure, removing at least a portion of the first insulator from the strained semiconductor heterostructure, and thermally growing or depositing a second insulator on the strained semiconductor heterostructure.  
           [0010]    In an embodiment, the method of forming multiple gate insulators on a strained silicon heterostructure includes the steps of depositing a first insulator on the strained silicon heterostructure, applying a first photoresist mask to at least a portion of the strained silicon heterostructure, removing at least a first portion of the first insulator from the strained silicon heterostructure, and thermally growing or depositing a second insulator on the strained semiconductor heterostructure. In further embodiments, the method further includes the steps of applying a second photoresist mask to at least a portion of the strained silicon heterostructure, removing at least a second portion of the second insulator from the strained silicon heterostructure, and thermally growing or depositing a third insulator on the strained silicon heterostructure. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The following description may be further understood with reference to the accompanying drawing in which  
         [0012]    FIGS.  1 - 4  show diagrammatic views of a heterostructure substrate during a method of providing a plurality of gate insulator thicknesses in accordance with an embodiment of the invention;  
         [0013]    [0013]FIG. 5 shows a pair of FET devices formed on the substrate of FIG. 4 where each device includes a different gate insulator thickness;  
         [0014]    [0014]FIG. 6 shows the pair of FET devices of FIG. 5 coupled to a circuit;  
         [0015]    FIGS.  7 - 11  show diagrammatic views of a heterostructure substrate during a method of providing a plurality of gate insulator thicknesses in accordance with a further embodiment of the invention; and  
         [0016]    [0016]FIG. 12 shows three FET devices formed on the substrate of FIG. 11 where each device includes a different gate insulator thickness; and  
         [0017]    [0017]FIG. 13 shows the three FET devices of FIG. 12 coupled to a circuit.  
         [0018]    The drawings are shown for illustrative purposes and are not to scale. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    A strained Si substrate is generally formed by providing a relaxed SiGe layer on bulk Si through either eptitaxial deposition or wafer bonding, and then providing a Si layer on the relaxed SiGe layer. Because SiGe has a different lattice constant than Si, the Si layer becomes “strained” and results in enhanced mobilities (and hence improved device speeds) compared with bulk Si. The percentage of Ge in the SiGe can have a dramatic effect on the characteristics of the strained Si layer.  
         [0020]    The invention provides a method of forming multiple gate insulators on a substrate that includes strained semiconductor layers (e.g., strained silicon), where the thin and thick gate insulators are used for MOSFET transistors with different functionality. The resulting substrate allows the integration of MOSFETs with varying gate insulator thicknesses, using strained semiconductor layers to increase speed and mobility of devices built on the substrate. An illustrative example of such a substrate comprises a strained Si layer on a relaxed SiGe layer. FIG. 1 shows a cross-sectional view of a substrate  10 , comprising a Si layer  12 , a relaxed SiGe layer  14 , and a strained Si surface layer  16 . The strained Si layer  16  may be between 100Å and 300Å, and is preferably less than 250Å in thickness. The substrate  10  forms the base structure for the present invention. In developing this layered heterostructure substrate  10 , epitaxial growth techniques and polishing techniques (for example, chemical mechanical polishing) or wafer bonding techniques, which are known in the art, are applied. Methods of fabricating various strained silicon heterostructures are disclosed in U.S. patent application Ser. No. 09/906,551 filed Jul. 16, 2001 and U.S. patent application Ser. No. 09/928,126 filed Aug. 10, 2001, the disclosures of which are hereby incorporated by reference.  
         [0021]    As shown in FIG. 2, an insulator layer  18  (e.g., SiO 2 ) is deposited on the strained Si layer  16 , for example via Chemical Vapor Deposition (CVD) or other methods to a thickness of e.g., 50 Å. Insulator layer  18  may include a thin (approx. 10 Å) thermal oxide layer at the interface with strained Si layer  16 , which may be grown before or after the deposition of insulator layer  18 .  
         [0022]    A photoresist masking layer  20  is then applied to a portion of the insulator layer  18  using photolithography techniques known in the art. The exposed portion of the insulator layer  18  is then removed using, e.g., an HF acid or a CF 4 /O 2  step, leaving photoresist masking layer  20  and insulator layer  18  as shown in FIG. 3. The photoresist masking layer  20  is subsequently removed via wet etch (e.g., H 2 SO 4 +H 2 O 2 ) or dry etch (e.g., oxygen plasma).  
         [0023]    A second insulator layer  22  is then formed on the substrate by, e.g., thermal oxidation or deposition to a thickness of e.g., 10-20 Å as shown at part B in FIG. 4. When the second insulator layer  22  is formed, an oxide layer may be formed at the interface between the strained silicon layer  16  and the insulator layer  18  as shown at  26 . Although the portion of the second insulator layer  26  in area designated part A may be thinner then the portion of second insulator layer  22  in area designated part B, the combined thickness of the insulator layer  18  and the insulator region  26  provide a composite insulator layer  24  as shown that is thicker than the thickness of the insulator layer  22 . In particular, the composite insulator layer  24  may be greater than e.g., 70Å in thickness and the insulator layer  22  may be 10-20 Å. The substrate may be used, therefore, to form MOSFETs having multiple gate insulator thicknesses.  
         [0024]    As shown in FIG. 5, a pair of FET devices  30  and  32  may be formed on the parts A and B respectively of the structure of FIG. 4. The FET device  30  will include a gate insulator layer that is comprised of the composite insulator layer  24 , and the FET device  32  will include a gate insulator layer that is comprised of the insulator layer  22 . The devices each include strained silicon channel  16  of a sufficient thickness that the mobility of the electrons is not compromised. The devices may be isolated from one another as disclosed in U.S. Provisional Patent Application Ser. No. 60/296,976 filed Jun. 8, 2001 and U.S. patent application Ser. No. 10/___,___ filed Jun. 7, 2002, the disclosures of which are both hereby incorporated by reference. The devices  30  and  32  may be coupled to a circuit as shown in FIG. 6 in which the gate, source and drain of each FET are coupled to conductive paths of a circuit as generally shown at  34 .  
         [0025]    As shown in FIGS.  7 - 9  a heterostructure substrate  50  may again be formed of a silicon substrate  52 , a relaxed layer  54  of SiGe and a strained silicon layer  56  in accordance with another embodiment of the invention similar to the above disclosed embodiment shown in FIGS.  1 - 3 . An insulator layer  58  of e.g., SiO 2  is then deposited on the strained Si layer  56  via CVD, as shown in FIG. 8, to a thickness of e.g., 30Å. A photoresist masking layer  60  is then applied to a portion of the insulator layer  58  using photolithography techniques known in the art. The exposed portion of the insulator layer  58  is then removed using HF acid or a CF 4 /O 2  step, leaving photoresist masking layer  60  and insulator layer  58  as shown in FIG. 9. The photoresist masking layer  60  is subsequently removed via wet etch (e.g., H 2 SO 4 +H 2 O 2 ) or dry etch (e.g., oxygen plasma).  
         [0026]    As shown in FIG. 10, a second insulator layer  62  is then deposited via CVD on the substrate on both the insulator layer  58  and the exposed portion of the strained silicon layer  56 . The thickness of the second insulator layer  62  is, e.g., 30Å. A second photoresist mask  68  is then applied to a portion of the substrate and the exposed portion of the insulator layer  62  is then removed using HF acid or a CF 4 /O 2  step, leaving photoresist masking layer  68  and insulator layers  62  and  58  as shown in FIG. 11. The photoresist masking layer  68  is subsequently removed via wet etch (e.g., H 2 SO 4 +H 2 O 2 ) or dry etch (e.g., oxygen plasma).  
         [0027]    A third insulator layer  70  is then formed on the substrate e.g., by thermal oxidation or deposition to a thickness of e.g., 10-20Å as shown at part E in FIG. 12. When the third insulator layer  70  is formed, the insulator layer  66  may also be grown at the interface between the strained silicon layer  56  and the insulator layer  58  as shown at part C, and an insulator layer  72  is formed at the interface with the strained silicon layer  56  as shown at part D. The combined thickness of the insulator layer  58 , the insulator region  66  and the second insulator layer  62  provide a composite insulator layer  74  as shown that is larger than the thickness of the composite insulator layer  72  formed by the insulator layer  62  and the insulator layer  72 . Each of these composite insulator layers  74  and  72  is thicker than the insulator layer  70  as shown at part E in FIG. 12. The substrate may be used, therefore, to form MOSFETs having three different gate insulator thicknesses.  
         [0028]    As shown in FIG. 13, three FET devices  80 ,  82  and  84  may be formed on the parts C, D and E respectively of the structure of FIG. 12. The FET device  80  will include a gate insulator layer that is comprised of the composite insulator layer  74 , the FET device  82  will include a gate insulator layer that is comprised of the composite insulator layer  72 , and the FET device  84  will include a gate insulator layer that is comprised of the insulator layer  70 . The devices each include strained silicon channel  56  of a sufficient thickness that the mobility of the electrons is not compromised. The devices maybe isolated from one another as disclosed in U.S. Provisional Patent Application Ser. No. 60/296,976 filed Jun. 8, 2001 and U.S. patent application Ser. No. 10/___,___ filed Jun. 7, 2002. The devices may be coupled to a circuit as shown in FIG. 13 in which the gate, source and drain of each FET are coupled to conductive paths of a circuit as generally shown at  90 . The substrate may be used, therefore, to form MOSFETs having more than two multiple gate insulator thicknesses.  
         [0029]    The invention may also include one or more of the following elements: relaxed SiGe layer  14  may comprise stained or relaxed semiconductor layers other than SiGe, for example Ge or GaAs; strained Si surface layer  16  may comprise strained SiGe or Ge layers; strained Si layer  16  may be above the critical thickness; and the substrate  10  may comprise an insulating layer such as SiO 2 , thus making the relaxed SiGe layer  14  optional. Those skilled in the art will appreciate that numerous modifications and variations may be made to the above disclosed embodiments without departing from the spirit and scope of the invention.