Abstract:
An integrated memory circuit includes a memory loop which comprises two gates which are controlled by a clock signal. The circuit is susceptible to a race condition so that correct operation cannot always be ensured. The &#34;race&#34; problem is solved by choosing the switching thresholds of the gate inputs receiving the clock signal so that the gates respond successively instead of (sustantially) simultaneously to the clock signal. The correct switching sequence of the gates and the correct operation of the memory circuit can thus be ensured.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an integrated memory circuit including a clock input for receiving a clock signal, a data input for receiving a data bit under the control of the clock signal, and a data output, the memory circuit also including a memory loop comprising a first and a second gate. 
     A memory circuit of this kind is known from the Philips Data Handbook &#34;Integrated Circuits&#34;, book IC06N, new series 1985, showing a logic diagram of a flip-flop circuit in the integrated circuit HCT74 on page 188. This flipflop circuit includes two memory circuits, each of which includes a memory loop with two NAND-gates and a transfer gate. In addition, each memory loop is provided with a second transfer gate which is connected to its input. The use of transfer gates has the drawback that they must be driven by the clock signal and by the inverted clock signal. Consequently, at high clock frequencies unavoidable phase differences will occur between these clock signals so that the reliability of the memory loops can no longer be ensured. 
     However, it is alternatively possible to omit the transfer gates from the memory loops and to replace the transfer gates at the inputs of the memory loops by logic input gates which conduct a data bit to the memory loops under the control of the clock signal. Memory circuits of this kind have the drawback that correct storage of a data bit may be dependent on the signal propagation through the individual gates. The operation cannot be predicted or ensured in all circumstances, which makes such a memory circuit unsuitable for practical use in, for example, integrated circuits. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide an integrated memory circuit in which no inverted clock signal need be formed and in which the operation can be predicted and ensured. 
     To this end, an integrated memory circuit in accordance with the invention is characterized in that both gates can be switched by the clock signal, the switching threshold of the first gate deviating substantially from the switching threshold of the second gate. As a result of the use of different switching thresholds, one of the two gates will always react sooner to a clock signal transition, so that the switching sequence of the gates is defined and the operation of the memory circuit can be predicted and ensured. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be described in detail hereinafter with reference to embodiments shown in the accompanying drawing; in which: 
     FIG. 1 shows a logic diagram of an embodiment of the memory circuit in accordance with the invention, 
     FIG. 2 shows a logic diagram of a second embodiment of a memory circuit in accordance with the invention, and 
     FIG. 3 shows a transistor diagram of the embodiment shown in FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a logic diagram of a memory circuit in accordance with the invention in which the memory loop includes a first NAND-gate (1) and a second NAND-gate (2), the output (4) of the NAND-gate (1) being connected to a first input of the second NAND-gate (2) and vice versa. 
     A second input of the first gate (1) is connected to the clock input (CLK) and the second input (5) of the second gate (2) is connected to the output of an OR-gate (3), a first input of which is connected to the clock input (CLK) and a second input of which is connected to a data input (D). This memory circuit has two states: the write state in the case of a &#34;low&#34; clock signal, and the hold state in the case of a &#34;high&#34; clock signal on the clock input (CLK). In the hold state, the memory circuit saves the data in the memory loop; in the write state a data bit on the data input (D) is written into the memory loop. 
     This circuit is susceptible to a so-called &#34;race-condition&#34; which occurs when the circuit changes over from the write state to the hold state under the control of the clock signal and the data bit on the data input (D) is 0 (or &#34;low&#34;). Briefly before this transition, the clock signal on the clock input is &#34;low&#34;, so that point 4 is &#34;high&#34; (or 1). Because the data bit is 0, the second input (5) of the second gate (2) will be &#34;low&#34;, so that the output (QB) of the circuit is &#34;high&#34;. When the clock signal changes over from &#34;low&#34; to &#34;high&#34;, the output signals of the first NAND-gate (1) and the OR-gate (3) will change. This means that the first (4) and the second (5) input of the second NAND-gate (2) substantially simultaneously receive a changing input signal. If the output (5) of the OR-gate (3) reacts faster than the output (4) of the first NAND-gate (1), the second input of the second NAND-gate will become &#34;1&#34; while its first input is &#34;high&#34; and its output (QB) will change from &#34;high&#34; to &#34;low&#34;. The first NAND-gate (1) receive this &#34;low&#34; signal on its first input, so that its output (4) can no longer switch from &#34;1&#34; to &#34;0&#34;. Due to the fast reaction of the gate combination (6) formed by the second NAND-gate (2) and the OR-gate (3), incorrect data will be stored in the hold state. 
     This adverse effect is avoided by ensuring that the output (QB) of the gate combination (6) reacts comparatively slowly to the transition of the clock signal from &#34;low&#34; to &#34;high&#34;. The first gate (1) must then react comparatively quickly to the clock signal transition. This effect is realized by making the switching threshold of the first gate (1) lower than the switching threshold of the gate combination (6). 
     FIG. 2 shows a logic diagram of a second embodiment of a memory circuit in accordance with the invention. The memory loop includes a first NOR-gate (11) and a second NOR-gate (12), the output (14) of the first NOR-gate (11) being connected to a first input of the second NOR-gate (12) and vice versa. 
     A second input of the first gate (11) is connected to the clock input (CLK) and the second input (15) of the second gate (12) is connected to an output of an AND-gate (13), a first input of which is connected to the clock input (CLK) and second input of which is connected to the data input (D). In the hold state, the clock signal is &#34;low&#34;; it is &#34;high&#34; in the write state. A race condition occurs when the clock signal changes over from &#34;high&#34; to &#34;low&#34; while the data bit on the data input (D) is 1 (&#34;high&#34;). Analogous to the description that the gate combination (16) must react more slowly to a clock signal transition than the first gate (11). Because the clock signal now changes from &#34;high&#34; to &#34;low&#34;, the switching threshold of the first gate (11) must be higher than that of the gate combination (16). 
     FIG. 3 shows a transistor diagram of the logic diagram of the memory circuit shown in FIG. 2. The Figure is a known translation of the first NOR-gate into a transistor diagram (11) which can be realized as a complementary MOS circuit (CMOS). The gate combination of an AND-gate and a NOR-gate is also translated into a transistor diagram (16) in known manner. 
     Between the first supply terminal (V DD ) and the output (QB) the gate combination includes a branch with P-MOS transistors, parallel connected channels of a first P-MOS transistor (P1) and a second P-MOS transistor (P2) being connected on one side to the first supply terminal (V DD ) and on the other side, via the channel of a third P-MOS transistor (P3), to the output (QB). 
     Between the output (QB) and a second supply terminal (V SS ) the gate combination includes a branch with N-MOS transistors, a series connection of a first N-MOS transistor (N1) and a second N-MOS transistor (N2) being connected on one side to the output (QB) and on the other side to the second supply terminal (V SS ). The output (QB) is also connected, via the channel of a third N-MOS transistor (N3), to the second supply terminal (V SS ). The gate electrodes of the first P-MOS and N-MOS transistors (P1, N1) are connected to the clock input (CLK), the gate electrodes of the second P-MOS and N-MOS transistors (P2, N2) being connected to the data input (D) while the gate electrodes of the third P-MOS and N-MOS-transistors (P3, N3) are connected to the output (14) of the first NOR-gate (11). Between the first supply terminal (V DD ) and its output (14), the NOR-gate (11) includes series-connected channels of a fourth P-MOS-transistor (P4) and a fifth P-MOS-transistor (P5), the output (14) being connected, via parallel-connected channels of a fourth N-MOS-transistor (N4) and a fifth N-MOS-transistor (N5), to the second supply terminal (V SS ). The gate electrode of the fourth P-MOS transistor and the fourth N-MOS transistor (P4, N4) are connected to the output (QB) of the gate combination (16); the gate electrodes of the fifth P-MOS transistor and the fifth N-MOS transistor (P5, N5) are connected to the clock input (CLK). 
     The condition previous formulated for this memory circuit implies that the output (14) of the NOR-gate (11) must react faster to a clock signal transistion from &#34;high&#34; to &#34;low&#34; than the output (QB) of the gate combination (16). Therefore, the switching threshold of the NOR-gate (11) must be higher than that of the gate combination (16). The switching threshold of the NOR-gate (11) is raised by choosing a comparatively high ratio of the conductivity factors of the fourth P-MOS transistor (P4) and the fourth N-MOS transistor (N4). For a supply voltage of 5 volts, a ratio of four introduces a switching threshold shift of approximately 0.5 volts, so that the switching threshold corresponds to an input voltage of 2.5 V+0.5 V=3 volts. 
     When the conductivity factors of the first P-MOS and N-MOS transistors (P1, N1) are equal, the switching threshold of the gate combination (16) will be equal to half the supply voltage (2.5 volts), so that it will switch over only after the NOR-gate (12). In order to ensure reliable operation of the memory circuit, the difference between the switching thresholds should amount to at least 10% of the supply voltage (in this case 0.5 V). This is because the output of the CMOS gate which switches first will then be fully driven to one of the two supply voltage levels, so that the CMOS gate which subsequently switches over will receive a stable input signal. 
     In practical designs a difference of approximately 20% of the supply voltage preferably exists between the two switching thresholds. This choice offers an adequate margin for neutralizing unavoidable process spreads and temperature fluctuations. 
     A memory circuit as shown in FIG. 1 can also be translated into a transistor diagram in known manner. Mutatis mutandis, all of the above remarks are applicable again to such a transistor diagram. The memory circuits of the FIGS. 1 and 2 can be simply combined so as to form a so-called master-slave flipflop. Because of the fact that one memory circuit is in the hold state in the case of a high clock signal while the other circuit is in the hold state in the case of a low clock signal, a master-slave flipflop circuit which is controlled by only one clock signal can thus be realized. Using a cascade connection of the described flipflop circuits, a shift register which is controlled by only one clock signal can be simply implemented.