Abstract:
A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for fabricating a through-silicon via structure, and more particularly, to a method of removing excess water vapor from a liner oxide before the formation of a through-silicon via electrode. 
     2. Description of the Prior Art 
     The through-silicon via (TSV) technique is a novel semiconductor technique. The through-silicon via technique mainly servers to solve the problem of electrical interconnection between chips and belongs to a new 3D packing field. The through-silicon via technique produces products that meet the market trends of “light, thin, short and small” through the 3D stacking technique and also provides wafer-level packages utilized in micro electronic mechanic system (MEMS), and photoelectronics and electronic devices. 
     The through-silicon via technique drills holes in the wafer by etching or laser then fills the holes with conductive materials, such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. The wafer or the dice is then thinned to be stacked or bonded together to form a 3D stack IC. By using this approach, the wire bonding procedure could be omitted. Using etching or laser to form conductive vias not only omits the wire bonding but also shrinks the occupied area on the circuit board and the volume for packing. The inner connection distance of the package created by using the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, is much shorter compared with the conventional stack package of wire bonding type. The performance of the 3D stack IC would therefore be much better in many ways, including faster transmission, and lower noise. The advantage of the shorter inner connection distance of the through-silicon via technique becomes much more pronounced in CPU, flash memory and memory card. As the 3D stack IC could be fabricated to equate the size of the dice, the utilization of through-silicon via technique becomes much more valuable in the portable electronic device industry. 
     Conventional approach of fabricating a TSV electrode typically forms a metal-oxide semiconductor (MOS) transistor, such as a CMOS transistor on a semiconductor substrate, forms a TSV in the interlayer dielectric layer and the semiconductor substrate, covers a liner on the sidewall of the TSV, and then fills the TSV with material such as copper for forming a TSV electrode. Unfortunately, the liner deposited in the TSV typically adsorbs water vapor during the fabrication. As a result, barrier layer and seed layer deposited thereafter could not adhere onto the surface of the liner effectively and result in issue such as copper crack. 
     SUMMARY OF THE INVENTION 
     It is an objective of the present invention to provide a method for fabricating a TSV electrode for resolving the aforementioned issue caused by conventional approach. 
     According to a preferred embodiment of the present invention, a method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; and forming a through-silicon via electrode in the through-silicon via. 
     According to another aspect of the present invention, a method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate, wherein the semiconductor substrate comprises at least a semiconductor device thereon; forming a dielectric layer on the semiconductor device; forming a through-silicon via in the dielectric layer and the semiconductor substrate; covering a liner on the sidewall and bottom of the through-silicon via; performing a baking process on the liner; forming a barrier layer, a seed layer, and a metal layer on the liner to fill the through-silicon via; and performing a planarizing process to partially remove the metal layer, the seed layer, the barrier layer, and the liner until reaching the dielectric layer for forming a through-silicon via electrode in the through-silicon via. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-4  illustrate a method for fabricating a through-silicon via structure according to a preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1-4 ,  FIGS. 1-4  illustrate a method for fabricating a through-silicon via structure according to a preferred embodiment of the present invention. As shown in  FIG. 1 , a semiconductor substrate  12 , such as a substrate composed of monocrystalline silicon, gallium arsenide (GaAs) or other known semiconductor material is provided. A standard metal-oxide semiconductor (MOS) transistor fabrication is performed to form at least one MOS transistor  14  or other semiconductor device on the semiconductor substrate  12 . The MOS transistor  14  could be a PMOS transistor, a NMOS transistor, or a CMOS transistor, and the MOS transistor  14  could also include typical transistor structures including gate, spacer, lightly doped drains, source/drain regions and/or salicides. 
     An interlayer dielectric layer  16  with a depth of several thousand angstroms, preferably at 3000 angstroms is deposited on the MOS transistor  14 . The interlayer dielectric layer  16  is preferably a composite layer consisted of tetraethylorthosilicate (TEOS) and phosphosilicate glass (PSG), but not limited thereto. The interlayer dielectric layer  16  could also be composed of BPSG or low-k dielectric material, and a stress material layer, such as a tensile or compressive stress layer composed of silicon nitride, an etch stop layer composed of silicon nitride, a thin oxide cap layer, or combination thereof could be inserted between the interlayer dielectric layer  16  and the MOS transistor  14 . A contact plug fabrication could then be conducted to form a plurality of contact plugs (not shown) in the interlayer dielectric layer  16  for electrically connecting the MOS transistors. 
     As shown in  FIG. 2 , a pattern transfer process is conducted thereafter by forming a patterned resist (not shown) on the interlayer dielectric layer  16  and then using this patterned resist as mask to form a through-silicon via  22  in the interlayer dielectric layer  16  and the semiconductor substrate  12  through single or multiple etching processes. 
     Next, as shown in  FIG. 3 , a liner  24  is formed on the sidewall and bottom of the through-silicon via  22  and on the surface of the interlayer dielectric layer  16 . The liner  24  is preferably used as an isolation between the through-silicon via electrode afterwards and the semiconductor substrate  12 , such that the through-silicon via electrode and the semiconductor substrate  12  would not contact directly. In this embodiment, the liner  24  could be composed of insulating material such as oxides or nitrides, or could be a single layer or composite layer material. 
     Next, a baking process is performed to remove excess water vapor from the liner  24  so that the materials deposited on the liner  24  afterwards could be adhered onto the liner  24  effectively. In this embodiment, the baking process preferably includes a furnace anneal process, in which the fabrication time of the baking process is substantially greater than 10 minutes, and the fabrication temperature of the process is between 200° C. to 500° C., and preferably at 410° C. 
     A chemical vapor deposition (CVD) is conducted to form a barrier layer  26  and a seed layer  28  on surface of the line  24 , and a metal layer  30  composed of copper is electroplated on surface of the seed layer  28  until filling the entire through-silicon via  22 . The barrier layer  26  is preferably selected from a group consisting of Ta, TaN, Ti, and TiN, which could be used to prevent copper ions of the metal layer  30  from migrating to the surrounding liner  24 . The seed layer  28  is preferably used to adhere copper ions of the metal layer  30  onto the liner  24  for facilitating the copper electroplating process thereafter. It should be noted that the metal layer  30  could also be composed of conductive materials other than copper, and the seed layer  28  is formed selectively and the material of the seed layer  28  could be adjusted according to the material of the metal layer  30 . An anneal process could be carried out thereafter by using a temperature between 350° C. to 400° C. to improve the stability of the metal layer  30 . 
     Next, as shown in  FIG. 4 , a planarizing process, such as a chemical mechanical polishing is conducted by using the interlayer dielectric layer  16  as a stop layer to remove a portion of the metal layer  30 , the seed layer  28 , the barrier layer  26 , and the liner  24  such that the surface of the metal layer  30  filled within the through-silicon via  22  is even with the interlayer dielectric layer  16 . This forms a through-silicon via electrode  32  in the interlayer dielectric layer  16 . 
     Next, a back-end-of-the-line (BEOL) process for the semiconductor chip fabrication is performed. For instance, a plurality of dielectric layers (not shown) is formed on top of the interlayer dielectric layer  16  and the through-silicon via electrode  32  and associating metal interconnect fabrication and contact plug fabrication are also carried out to form metal interconnects and contact pads connecting the plugs of MOS transistor  14 . 
     Moreover, the aforementioned embodiment could also be applied to different stage of TSV fabrication, such as during a via-first stage where a TSV filled with oxide is first formed before the formation of CMOS transistor and TSV electrode is formed on the back of the wafer thereafter, or during a via-last stage where TSV is formed after fabrication of metal interconnects is completed, which are all within the scope of the present invention. 
     Overall, as water vapor typically enters the liner deposited in the through-silicon via thereby creating difficulty for the seed layer and barrier layer to be adhered onto the liner as found in conventional art, the present invention specifically conducts a baking process after the formation of the liner to remove excess water vapor from the liner and reduce the stress of the entire wafer. By doing so, issues such as copper crack could be prevented effectively. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.