Abstract:
A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

Description:
This application is a divisional of U.S. application Ser. No. 10/640,100, filed Aug. 13, 2003 now U.S. Pat. No. 6,969,881. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to a memory cell, and more particularly to a partial vertical memory cell of a DRAM and a method of fabricating the same. 
   2. Description of the Related Art 
   There is much interest in reducing the size of individual semiconductor devices to increase their density on an integrated circuit (IC) chip. This reduces size and power consumption of the chip, and allows faster operation. In order to achieve a memory cell of minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length results in higher leakage current that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the charges stored on a storage capacitor, thus requiring a larger capacitance to ensure that stored charges are detected accurately. 
     FIGS. 1   a  to  1   e  are cross-sections of the conventional method of forming a horizontal memory cell. 
   In  FIG. 1   a , a silicon substrate  101  is provided. A gate dielectric layer  102 , such as gate oxide layer, a conducting layer  103 , such as doped poly layer or doped epi-silicon layer, and a patterned mask layer  104 , such as nitride layer or photoresist layer, are sequentially formed on the silicon substrate  101 . 
   In  FIG. 1   b , the conducting layer  103  and gate dielectric layer  102  are anisotropically etched using the patterned mask layer  104  to form a conducting layer  103   a  acting as a gate and a gate dielectric layer  102   a.    
   In  FIG. 1   c , a liner layer  105 , such as oxide layer, and an insulating layer  106 , such as nitride layer, are conformally formed on the silicon substrate  101 , the conducting layer  103   a , and the exposed gate dielectric layer  102   a.    
   In  FIG. 1   d , the liner layer  105  and the insulating layer  106  are anisotropically etched to form a spacer  106   a  and a liner layer  105   a.    
   In  FIG. 1   e , the silicon substrate  101  is doped to form a Source/Drain (S/D) region beside the conducting layer  103   a . A silicide layer  107  is formed on the conducting layer  103   a  and the S/D respectively. 
   As the gate size of the MOSFET decreases, a drive current and effect of the gate are difficult to keep high at a low operating voltage. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to partial vertical memory cell and a method for forming the same. 
   Accordingly, the present invention provides a method for forming a partial vertical memory cell. A semiconductor substrate having two deep trenches with capacitors is provided, and the capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor substrate outside the deep trenches is removed to form a pillared active area between the deep trenches. The active area is ion implanted to form an ion-doped area in a corner of the active area acting as an S/D. A gate dielectric layer and a conducting layer are conformally formed on the active area. An isolation is formed beside the conducting layer. The conducting layer is defined to form a first gate and a second gate. 
   Accordingly, the present invention also provides another method for forming a partial vertical memory cell. A semiconductor substrate having two deep trenches with capacitors formed therein is provided, and the capacitors are lower than a top surface of the semiconductor substrate. An isolating layer is formed on each capacitor. Each deep trench is filled with a mask layer. A first patterned mask layer is formed on the semiconductor substrate between the deep trenches, and the first patterned mask layer partially covers the mask layer. The semiconductor substrate is etched using the first patterned mask layer and the mask layers as etching masks to further below its surface than the isolating layer, thereby forming a pillared active area between the deep trenches. The first patterned mask layer and the mask layers are removed. The active area beside the insulating layer is ion implanted to form an ion-doped area acting as a S/D. A gate dielectric layer and a conducting layer are conformally formed on the semiconductor substrate. A second patterned mask layer corresponding to the active area and the portion of the mask layers is formed to cover the conducting layer. The conducting layer is etched using the second patterned mask layer as an etching mask so that the conducting layer covering the active area remains. The second patterned mask layer is removed. A dielectric layer is formed on the semiconductor substrate to isolate the active area, and a height of the dielectric layer is equal to the conducting layer. A third patterned mask layer, having an opening partially exposing the conducting layer, is formed on the conducting layer and the dielectric. The conducting layer is etched using the third patterned mask layer as an etching mask until the gate dielectric layer is exposed to form a trench, and the conducting layer is insulated by the trench to form a first gate and a second gate. 
   Accordingly, the present invention also provides another method for forming a partial vertical memory cell. A semiconductor substrate having two deep trenches with capacitors is provided, the capacitors are lower than a top surface of the semiconductor substrate, and a collar insulating layer is formed on a top sidewall of each deep trench. An isolating layer is formed on each deep trench capacitor. Each deep trench is filled with a mask layer. A first patterned mask layer is formed on the semiconductor substrate between the deep trenches, and the first patterned mask layer partially covers the mask layer. The semiconductor substrate is etched using the first patterned mask layer and the mask layers as etching masks to further below its surface than the isolating layer, thereby forming a pillared active area between the deep trenches. The first patterned mask layer and the mask layers are removed. A sacrificial layer is conformally formed on the semiconductor substrate outside the active area. A first dielectric layer is formed on the sacrificial layer. The first dielectric layer and the sacrificial layer are planarized until the active area is exposed to further below their surfaces than the active area by a predetermined depth. The active area is etched using the first dielectric layer and the sacrificial layer as etching masks to round corners of the active area. The first dielectric layer is removed. The active area beside the insulating layer is ion implanted to form an ion-doped area acting as an S/D. The sacrificial layer is removed. The semiconductor substrate is oxidized to form a gate dielectric layer. A conducting layer is conformally formed on the gate dielectric layer. A second patterned mask layer corresponding to the active area and the portion of the mask layers is formed to cover the conducting layer. The conducting layer is etched using the second patterned mask layer as an etching mask to form a gate. The second patterned mask layer is removed. A second dielectric layer is formed on the semiconductor substrate. The second dielectric layer is planarized until the gate is exposed to form an isolation for isolating the active area. A third patterned mask layer, having an opening partially exposing the conducting layer, is formed on the conducting layer and the dielectric. The conducting layer is etched using the third patterned mask layer as an etching mask until the gate dielectric layer is exposed to form a trench, and the gate is insulated by the trench to form a first gate and a second gate. The third patterned mask layer is removed. A spacer is formed on a sidewall of the trench to avoid electrical connection of the first gate and the second gate. 
   Accordingly, the present invention also provides a partial vertical memory cell comprising a semiconductor substrate with a pillared active area, two deep trench capacitors formed in the semiconductor substrate beside the active area, two S/D regions formed in the active area beside the deep trench capacitors, a gate dielectric layer formed on a surface of the active area, and two gates conformally formed on the gate dielectric layer around two top corners of the active area. The two gates are independent from one another. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which: 
       FIGS. 1   a  to  1   e  are cross-sections of the conventional method for forming a horizontal memory cell; 
       FIGS. 2   a  to  2   t  are cross-sections of the method for forming a partial vertical memory cell of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 2   a  to  2   t  are cross-sections of the method for forming a partial vertical memory cell of the present invention. 
   In  FIG. 2   a , a semiconductor substrate  201  is provided, n which a pad layer  202 , such as pad oxide layer or pad nitride layer, is formed. Two deep trenches  201   a  with capacitors are formed in the semiconductor substrate  201  separately by a predetermined distance of about 1200 to 1400 Å from each other. The semiconductor substrate  201  between the deep trenches  201   a  is an active area as follows. A conducting layer, such as poly layer, is formed on each capacitor acting as a capacitor conducting wire  203  below the semiconductor substrate  201 . A length between the semiconductor substrate  201  and the capacitor conducting wire  203  is equal to a channel length of a gate as follows. A collar insulating layer  204 , such as a collar oxide layer, is formed in a top sidewall of each deep trench  201   a  to isolate the gate. 
   In  FIG. 2   b , an isolating layer is conformally formed on the semiconductor substrate  201 , the deep trenches  201   a , and the capacitor conducting wires  203 . The isolating layer on the sidewall of the deep trenches  201   a  is etched to leave the isolating layer  205 , such as top trench oxide (TTO) layer, on each capacitor conducting wire  203 . The ratio of the isolating layer on the deep trench  201   a  sidewall to the isolating layer on the capacitor conducting wire  203  surface is less than 1:8. The thickness of the isolating layer on the capacitor conducting wire  203  surface is not much affected when the isolating layer on the deep trench sidewall is etched away. 
   In  FIG. 2   c , a mask layer  206 , such as organic anti-reflection coating layer, is formed on the pad layer  202 , and the deep trenches  201   a  are filled with the mask layer  206 . The organic anti-reflection coating layer is a SiON layer. 
   In  FIG. 2   d , the mask layer  206  is planarized by CMP or etching to expose the pad layer  202  and leave the mask layer  206   a  in each deep trench  201   a.    
   In  FIG. 2   e , a photoresist layer  207  is formed on the semiconductor substrate  201  between the deep trenches  201   a , such that the mask layer  206   a  is partially covered. 
   In  FIG. 2   f , the semiconductor substrate  201  is anisotropically etched by plasma etching or reactive ion etching using the photoresist layer  207  and the mask layer  206   a  as etching masks until the exposed semiconductor substrate  201  is lower than the isolating layer  205  by a predetermined depth of about 2600 to 3300 Å. Plasma or reactive ion etching is carried out using a gas mixture containing HBr and oxygen. 
   In  FIG. 2   g , the photoresist layer  207  and the mask layer  206   a  are removed. The semiconductor substrate  201   b  between the deep trenches  201   a  is a pillar. The pad layer is removed. The pillared semiconductor substrate  201   b  between the deep trenches  201   a  is the active area for forming a MOS. 
   In  FIG. 2   h , a sacrificial layer  208  and a dielectric layer  209  are conformally formed on the semiconductor substrate  201 . The thickness of the sacrificial layer  208 , such as nitride layer, is about 120 to 200 Å. The dielectric layer  209 , such as HDP oxide layer, covers the semiconductor substrate  201  and the whole active area  201   b.    
   In  FIG. 2   i , the dielectric layer  209  is planarized to expose the active area  201   b  by CMP or etching, the dielectric layer  209   a  approximately level with the active area  201   b . The sacrificial layer  208  is lower than the dielectric layer  209   a , and top corners of the active area  201   b  are exposed. The dielectric layer  209  is etched back using the active area  201   b  and the sacrificial layer  208   a  as etching masks to level with the sacrificial layer  208   a.    
   In  FIG. 2   j , the active area  201   b  is etched using the dielectric layer  209   a  and sacrificial layer  208   a  as etching masks to round the top corners to avoid leakage. 
   In  FIG. 2   k , the dielectric layer  209   a  is removed. 
   In  FIG. 2   l , bottom corners of the active area  201   b  are ion implanted by n+ type ions, and the sacrificial layer  208   a  prevents the ions from damaging the surface of the active area  201   b.    
   In  FIG. 2   m , after ion implantation, ion-doped areas  210  acting as S/D regions are formed in the active area  201   b  beside the isolating layer  205 . The sacrificial layer  208   a  is removed. 
   In  FIG. 2   n , the semiconductor substrate  201  is thermally oxidized to form an oxide layer acting as a gate dielectric layer  211  on the exposed semiconductor substrate  201   a  and  201   b.    
   A conducting layer  212   a  and a hard mask layer  212   b , such as a nitride layer, are conformally formed on the semiconductor substrate  201 . In this case, the conducting layer  212   a  comprises a poly layer and a silicide layer. 
   A patterned mask layer  213 , such as photoresist layer, is formed corresponding to the active area  212   b  and a portion of the isolating layer  205  to cover the conducting layer  212   a  and the hard mask layer  212   b.    
   In  FIG. 2   o , the conducting layer  212   a  and the hard mask layer  212   b  are sequentially etched using the patterned mask layer  203  as an etching mask to expose the gate dielectric layer  211  and the isolating layer  205 , such that a conducting layer  212   c  and a hard mask layer  212   d  surrounding the active area  201   b  are formed. 
   In  FIG. 2   p , the patterned mask layer  203  is removed. A dielectric layer  214  is formed on the semiconductor substrate  201 , and planarized to level with to the dielectric layer  210 , the conducting layer  212   c , and the hard mask layer  212   d . The dielectric layer  214 , such as HDP oxide layer, is formed to isolate the active area  201   b.    
   In  FIG. 2   q , a patterned mask layer  215 , such as photoresist layer, is formed on the dielectric layer  214 , the conducting layer  212   c , and the hard mask layer  212   d . The patterned mask layer  215  has an opening  216 , and the conducting layer  212   c  and hard mask layer  212   d  are exposed by the opening  216 . 
   In  FIG. 2   r , the conducting layer  212   c  and the hard mask layer  212   d  are etched using the patterned mask layer  215  as an etching mask to expose the gate dielectric layer  211 , thereby forming a trench  217 . The conducting layer  212   c  and the hard mask layer  212   d  are equally distributed to two partial vertical gates  212   e  and hard masks  212   f . The patterned mask layer  215  is removed. 
   In  FIG. 2   s , an insulating layer  218 , such as nitride layer, is conformally formed on the dielectric layer  214 , the conducting layer  212   e , the hard mask layer  212   f , and the trench  217 . 
   In  FIG. 2   t , the insulating layer  218  is anisotropically etched by plasma etching or reactive ion etching to expose the gate dielectric layer  211  in the trench, thereby forming a spacer  218   a . The spacer  218   a  is formed to avoid electrical connection of the partial vertical gates  212   e.    
   The partial vertical memory of the present invention comprises the semiconductor substrate  201 , the pillared active area  201   b , the deep trench capacitors  204 , the ion-doped areas  210  acting as S/D, the gate dielectric layer  214 , the partial vertical gates  212   e  conformally formed on the gate dielectric layer around two top corners of the active area, and the hard mask layer  212   f.    
   A channel of each partial vertical gate  212   e  is combined with a horizontal channel on the top and a vertical channel on the sidewall, a superficial area of the horizontal surface is reduced to ½ time, and a congregation of the memory cell is increased. 
   While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.