Abstract:
An improved portable data entry machine is disclosed, wherein data may be keyed, viewed for accuracy, recorded on magnetic tape, recalled from magnetic tape, and telephonically transmitted for data processing. Improvements include a search feature to locate previously recorded data, an automatically controlled power switching unit to prolong the times that batteries may be used prior to recharging, microcomputer controlled circuitry to prevent attempted data entry under low-battery conditions, an electronic shutdown to prevent cell reversal, a voltage reference technique to minimize the power drain from the batteries, a unique mechanism and circuitry to preclude the inadvertent destruction of data, a low cost modem for communicating entered data to a remote location, an automatic interlock for the tape compartment, a highly effective display technique, a novel high voltage power supply, and an out-of-sequence detector.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to improvements in portable data devices of the type wherein data may be keyed, viewed for accuracy, recorded on magnetic tape, recalled from magnetic tape, and telephonically transmitted for processing. 
     2. Description of the Prior Art 
     At the present time there are various types of data collection systems in use for collecting and recording various types of data. Data that is collected by these systems is usually transmitted by conventional means to a central computer for further processing. These data collection systems are especially useful to supermarkets and drug stores as a means of ordering merchandise. 
     One type of data collection system developed to date generally uses a modified adding machine as an input device to a recording medium. These types of systems are usually cumbersome to use, since carts are required to transport them. Furthermore, these systems require conventional 110 volt electricity for operation, leading to awkward power cords and limited mobility. 
     Portable data entry devices have been developed to alleviate some of the problems associated with the above devices. These portable devices have not, however, provided total flexibility. Moreover, they have not provided sufficient safeguards against un-noticed operator error, e.g., inadvertent deletion of data, and they have been too complicated for many users to operate correctly and consistently, especially untrained persons. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the shortcomings of the prior art without sacrificing light weight or portability. 
     The system provides for recording data on a tape cassette in a portable case, which also includes a microcomputer set and batteries. A hand-held keyboard input unit, including a display, is connected by a cable to the case. In one aspect of the invention, circuitry is provided for generating a signal when the battery voltage is below one predetermined level. The signal is inputted to the microcomputer set, which generates a signal sequence to the display, indicating the low-battery condition. 
     In another aspect of the invention, the batteries are automatically electronically disconnected when battery voltage drops below a second predetermined level. This feature is part of the &#34;data integrity&#34; theme of the invention. 
     Various components are powered and shut down as functionally required, thereby prolonging battery life. 
     An important aspect of the present invention is that it permits, upon operator key command, a re-winding of the tape and an automatic search for a signal pattern corresponding to a coded item chosen by the operator, or, if the operator so elects, an item-by-item scan of all previous entries. Additionally, the three previous entries at any given time are stored in memory, and may accordingly be reviewed without moving the tape at all. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIG. 1 is a perspective view of the portable apparatus of this invention. 
     FIG. 1a is a more detailed view of the keyboard unit 90 of FIG. 1. 
     FIG. 2 is a block diagram illustrating the electrical arrangement of the system of this invention. 
     FIG. 3 is a schematic diagram of the power supply circuitry of the system of FIG. 2. 
     FIG. 4 is a schematic diagram of the power-switching circuitry of the system of FIG. 2. 
     FIG. 5 is a schematic circuit diagram of a microcomputer set of the system of FIG. 2. 
     FIG. 6 is a schematic diagram of clock generation circuitry of the system of FIG. 2. 
     FIG. 7 is a schematic diagram of the port selector circuitry of the system of FIG. 2. 
     FIG. 8 is a schematic diagram of the input port circuitry of the system of FIG. 2. 
     FIG. 9 is a schematic diagram of the output port circuitry of the system of FIG. 2. 
     FIG. 10 is a schematic diagram of the read-write circuitry of the system of FIG. 2. 
     FIG. 11 is a schematic diagram of the deck-motion-control circuitry of the system of FIG. 2. 
     FIG. 12 is a schematic diagram of the alarm clock circuitry of the system of FIG. 2. 
     FIG. 13 is a schematic diagram of the alarm circuitry of the system of FIG. 2. 
     FIG. 14 is a schematic diagram of the bit cell timer circuitry of the system of FIG. 2. 
     FIG. 15 is a schematic diagram of the emitter detector circuitry of the system of FIG. 2. 
     FIG. 16 is a schematic diagram of the delay circuitry of the system of FIG. 2. 
     FIG. 17 is a schematic diagram of the segment selector circuitry of the system of FIG. 2. 
     FIG. 18 is a schematic diagram of the digit selector circuitry of the system of FIG. 2. 
     FIG. 19 is a schematic diagram of the keyboard switch and interrogation circuitry of the system of FIG. 2. 
     FIG. 20 is a schematic diagram of the high voltage power supply of the system of FIG. 2. 
     FIG. 20a graphically shows the output waveform of one component of the high voltage per supply of FIG. 20. 
     FIG. 20b is a simplified schematic diagram of the high voltage power supply of FIG. 20. 
     FIG. 21 is a schematic diagram of the power saving circuitry that is used in conjunction with the high voltage power supply of FIG. 20. 
     FIG. 22 is a schematic diagram of portion of the modem circuitry of the system of FIG. 2. 
     FIG. 23 is a schematic diagram of the portion of the modem circuitry of the system of FIG. 2 which interfaces an acoustical coupler. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     It will be appreciated that the present invention can take many forms and embodiments. The true essence and spirit of this invention are defined in the appended claims, and it is not intended that the embodiment of the invention presented herein should limit the scope thereof. 
     Referring now to FIG. 1, the external configuration of the portable data entry apparatus of this invention is shown. This apparatus is comprised of a keyboard input-display unit 90, a housing 91 in which a tape deck mechanism and a majority of the electronics embodying this invention are located and into which a magnetic cassette tape cartridge 94 may be inserted, and the cable 92 which connects housing 91 and keyboard-display unit 90. A specific function, e.g., the entry of data, to be performed by the portable data entry apparatus is selected by the operator. This is accomplished by utilization of the keyboard input-display unit 90. The electronics which reside in housing 91 detect the function to be performed, and, in the case of data entry, generate proper electrical signals to cause the data to be written on the tape in the tape cartridge 94. Also the electronics position the tape such that it is ready accept new data. 
     Referring now to FIG. 2, there is shown a block diagram of the portable data entry apparatus of this invention. It is comprised of microcomputer set 100, clock 102, port selector 103, input port 104, output port 105, deck motion control 106, read-write circuitry 107, bit cell timer 108, display 109, high voltage power supply 110, keyboard switch and interrogation assembly 111, alarm 112, delay 113, modem 114, power supply 115, power switching 116, alarm circuitry 117, emitter detector 118, segment selector 119, and digit selector 120. It will be appreciated that the block diagram is presented to give a general understanding of interrelation of the above interrelated elements. It should also be appreciated that the detailed interconnection of the various devices is not given at this point for ease of presentation of the block diagram. The detailed interconnection of these devices will be set forth later in the specification. 
     The operation of the apparatus of this invention begins, with reference to FIG. 2, by assuming that no previous data have been recorded on tape and that the operator is just beginning to use the apparatus. Tape cartridge 94, is, therefore, inserted in the housing 91, and the power switch on. Keyboard input-display unit 90 is engaged in the &#34;on&#34; position. This switch is schematically shown in FIG. 19, and its being engaged on causes power supply 115 to be activated. 
     Since the source of power for the portable data entry apparatus of this invention is batteries, it is desirable to minimize the consumption of battery power. Power switching unit 116 (FIG. 2) accomplishes this by supplying power to certain component parts only when power to those parts is required for proper operation. For example, power is supplied to the modem 121 only when the operator puts the unit in the &#34;send&#34; mode as described below, an power is supplied to the tape deck only when the operator puts the unit in either the SEND or RECORD modes. 
     Furthermore, battery power is conserved when in other modes by switching the power to component parts by the apparatus at periodic intervals. The length of time that power is available to these components is referred to as the &#34;awake&#34; time, and the length of time that it is not available is referred to as the &#34;asleep&#34; time. In the preferred embodiment of this invention the maximum awake time is approximately 2.5 milliseconds, and the asleep time is approximately 7.5 milliseconds. 
     Power supply 115, when activated, supplies power directly to the microcomputer set 100, and the microcomputer set 100 begins to execute a series of predetermined instructions, as later illustrated. Since at this point in the operation only the power switch has been turned on, the microcomputer set 100 is interrogating the keyboard switch (FIG. 19) and interrogation circuitry 111 via the segment selector circuitry 119 to determine if a mode has been selected by the operator. Since no previous data has been recorded on tape and the operator was just beginning to utilize the apparatus, assume now that the operator desires to enter the RECORD mode. 
     To enter the RECORD mode for a new tape the operator must press first the [&#34;*&#34; of FIG. 1] key (FIG. 19) and then must depress the CLEAR key (FIG. 19) for approximately 5 seconds. The microcomputer set 100 first detects that the MODE key had been depressed and then that the CLEAR key had been depressed for the required five seconds. After five seconds the microcomputer set generates commands via the output port 105 (FIG. 2) to the deck motion control 124 to cause the tape of the cartridge 94 to be rewound. After the tape has been rewound, the deck motor mechanism is enabled by deck motion control 124 to start the tape moving in the forward direction until the beginning of the tape is found. The beginning of tape is found by utilizing emitter detector 118. The operator is now ready to begin entry of data. 
     Data may be entered by depressing the appropriate keys of the keyboard input-display unit 90 (FIG. 1) which are shown schematically in the keyboard switch and interrogation circuitry 111 of FIG. 19. Suppose, for example, that the data &#34;12345&#34; were desired to be written onto tape. The operator would depress the 1 switch, followed by the 2 switch, etc. until the five switches have been depressed. The data are then displayed in the display unit 109. 
     If the operator had attempted to enter data into the date entry apparatus prior to entering the RECORD mode, it would not have been accepted since the apparatus is in a no mode or idle status. The microcomputer set 100 at this time generates signals to the alarm circuitry 112, and the alarm circuitry 112 detects these signals and drive a speaker for a specified period of time. The operator is, therefore, given an audible indication that the data apparatus is not in the proper mode to accept data entry. The above described alarm is present anytime that the portable data entry apparatus is in a no mode or idle status. 
     In a manner to be later set forth in detail, when the portable data entry apparatus was placed in the RECORD mode, the microcomputer set 100 started scanning the keyboard switch and interrogation circuitry 111 during the awake time to determine if a key has been depressed. As each key in the above example was depressed, it would be detected by the microcomputer set 100 during this scan and the information corresponding to that key would be detected and would be temporarily stored in the microcomputer set 100. This stored information is then outputted to the display 109 via the segment selector 119 and the digit selector 120 during the awake time of power switching unit 116, thereby giving the operator a visual indication of the entered data. In the preferred embodiment of this invention up to 12 digits may be displayed for any one entry. 
     A primary use of the portable data entry apparatus of this invention is to enable merchandisers, e.g., supermarket chains, to employ it for ordering information. Each type of goods that is to be ordered will have a reference designation symbol, and it is common for this reference designator to be five digits in length. The operator would enter the reference designator of the product to be ordered. Following this entry, he would enter the number of cases of that product to be ordered. For example, if the reference designator was 12345 and six cases were desired to be ordered, the operator&#39;s data input would be 1234506+. Conversely, if in the above example only five cases need to be ordered instead of six, the operator could correct this mistake on his next entry by entering 1234501-. 
     When the operator of the apparatus depresses either the plus or the minus key of the keyboard 90, the microcomputer set 100 detects that fact and begins to prepare the stored information to be written onto the tape. It transmits this information in serial fashion via the output ports 105 to the read-write circuitry 107 which writes the information on the tape. The tape would then contain digitized coded signals corresponding to the data entry. Also during this write time the microcomputer set 100 has generated commands to the deck motion control 106 via the ouput ports 105 so that the tape may be properly positioned to accept the data. When the information is being written onto tape power switching unit 116 supplies power to the deck motion control 106 and the read-write circuitry 107. 
     At this point it is appropriate to point out that the portable data entry apparatus of this invention has several optical features. These include case total, auto header, and check digit verification. Check digit verification and case total are features which may be manually disabled, and auto header, if selected, becomes a permanent feature of the portable data entry apparatus. 
     If the auto header feature is selected, a command will be generated by microcomputer set 100 to write a reference designator and a number designator as the first entry on tape. This occurs when the beginning of tape is found by the emitter detector 118 as described above. In the preferred embodiment of this invention, the auto header reference designator is &#34;ACEO&#34;, and the number designator is comprised of four numbers, e.g., 1234. The reference designator is permanently stored in microcomputer set 100 and the number designator (corresponding to unit serial number), is diode programmed (944a -- FIG. 19) by inserting diodes corresponding to the binary coded decimal representation of the serial number. The reference designator and the number designator are always written onto the tape as the first entry if the option is installed. 
     The case total option is selected by engaging the case total switch of keybaord input-display unit 90 into the on position. This switch is shown schematically in FIG. 19. The microcomputer set 100 detects that this option has been selected and for all the data entries keeps a running total of the number of cases of merchandise that have been ordered. This information is usable to the operator for freight and shipping information, because from case total he can estimate how many trucks are required to transport the total order to his location. The case total switch must be engaged in the on position during the entire time the data entry is being made in order to have an accurate case total. 
     Check digit verification is enabled by engaging the check digit verification switch on the keyboard input-display unit 90. This switch is shown schematically in FIG. 19. When engaged, the microcomputer set 100 manipulates entered data by either 10 (double-add-double) or modulus 11 (IBM standard) check digit schemes, which are known to those skilled in the art. The data entry must be 5, 6, 7, or 8 digits for check digit verification to operate properly. 
     Another feature of the microcomputer set 100 is that it is capable of storing the three data entries previous to the data entry in progress. When the operator is in the record mode, the last entry on tape may be reviewed by depressing the scan key once, the second to last entry may be reviewed by depressing the scan key a second time, and the third from last entry may be displayed by depressing the scan key a third time. A fourth depression of the scan returns the operator to his entry in process, and if he had not selected an entry, the display entry wil be blank. When the operator depresses the &#34;plus&#34; or &#34;minus&#34; key for the present entry, the data entry that was previously third entry back is no longer stored in the microcomputer set 100. 
     Another feature of the portable data entry apparatus of this invention is the end-of-data mark which is written onto the tape whenever the operator exits the record mode. The microcomputer set 100, upon detection of a mode change, automatically generates the sequence of bit signals to the read-write circuitry 107 via the output port 105. In the preferred embodiment of this invention, this entry would be displayed as &#34;END&#34;. 
     Having entered data on the tape, the operator may now desire to enter the READ mode. This may be accomplished by depressing the MODE key (FIG. 19) followed by the READ key (FIG. 19). When entering the READ mode from the RECORD mode, the display will show END. This is because the next entry on tape is the end of data mark as discussed above. When END is displayed, the portable data entry apparatus reverts to a no mode or idle status. At this time the microcomputer set 100 will generate a signal to the alarm circuitry 112 via the output ports 100. This signal will be used by the alarm circuitry 112 to drive a speaker, thereby informing the operator that a mode request needs to be made. 
     An alternative method of entering the READ mode is to depress the MODE key (FIG. 19) followed by the BACK key (FIG. 19). If the &#34;MODE&#34; and the &#34;BACK&#34; keys are depressed when in the RECORD mode, the portable data entry apparatus will back up and display the 10th entry back. This operation can be executed at any point on the tape. The apparatus displays the 10th entry back, and then automatically enters the read mode. 
     Yet another method of entering the READ mode is to depress the MODE key followed by the RWD key (FIG. 19). The microcomputer set 100 (FIG. 2) detects the depression of the MODE and RWD keys and generates signals to the deck motion control 106 which cause the tape to be rewound. The happening of tape is then found with the emitter detector 118, and data may be read from the tape. 
     After the read mode has been entered the operator has two methods for scanning or reviewing the data. He can &#34;SCAN&#34; his data by successively displaying each entry, or he can &#34;SEARCH&#34; for a particular entry or series of entries on tape. 
     If the operator desires to scan the data, he does so by depressing the scan key when in the READ mode. The entry at a given tape position is then displayed until the scan key is again depressed, at which time the next entry is displayed. This process can be repeated until the end of data is reached at which time END is displayed. 
     If, on the other hand, the operator desires to search for a particular entry or series of entries he may initiate a search request. This is accomplished by depressing a data key when in the READ mode. The microcomputer set 100 detects the depression automatically as an intention to do a search operation. The operator would then enter a mask into the display. The mask is the reference designator of the type of entry that he desires to display. For example, if he desired to know the number of cases of goods of type 12345 that had been ordered, he would enter the mask 12345. The search feature is enabled by then depressing the SCAN key (FIG. 19) after the entry of the mask. Read-write circuitry 107 then begins to read the information that is recorded on tape in a forward direction from the point on the tape where the search is initiated. The information that is read is presented to microcomputer set 100 via the bit cell timer 108 and the input ports 104. 
     When a match is made, the portable data entry apparatus will terminate the search and display the complete entry from tape. A match is made when each character in the mask compares to each character of the reference designator in the entry for as many characters as were entered in the mask. If the scan key is depressed again after the first match was found, the search operation will continue with the previous mask, thereby locating all entries on the tape with that reference designators. To change the mask after a match, the operator must depress the &#34;CLEAR&#34; key and then enter a mask and depress the SCAN key again. If, however, he desires to review entries one at a time after a match, the operator depresses the CLEAR key followed by the SCAN key. 
     It will be recalled from the above description of the RECORD mode that the entry into the RECORD mode was only described for a tape which contained no data. In the case that an operator desires to enter data onto a tape on which there is previously recorded data and in the case of returning to the RECORD mode after a search has been completed, the RECORD mode is entered by depressing first the MODE and then the RECORD keys. The microcomputer set 100 in its keyboard scan detects that these two keys have been depressed and generates signals to the deck motion control 106 to start the tape moving in the forward direction until the end of data mark is found. It will be recalled that any time that the portable data entry apparatus exited the RECORD mode the microcomputer set 100 generated signals to cause an end of data mark to be written onto the tape. During the time that the tape is moving in the forward direction, information is being read from the tape by read-write circuitry 107, and this information is presented to microcomputer set 100 via the bit cell timer 108 and the input ports 104. When that the end of data mark is detected by the microcomputer set 100, signals are generated to the deck motion control 106 to stop the forward motion of the tape. The operator would then be at the proper place on the tape to begin additional data entries. 
     Having completed the data entry onto tape and, if desired, having reviewed the entered data, the operator would now or at some convenient time desire to transmit the entered data to a central location where his order would be processed. In order to transmit the information, the operator must put the portable data entry apparatus into the SEND mode, and this is accomplished by depressing first the MODE key and then the SEN key. The microcomputer set 100 detects that the send mode has been selected and enabled the power switching unit 116 to supply power to the modem 114. When the distant receiving end is connected to the modem the microcomputer set 100 generates commands which cause the data to be read from the tape by the read-write circuitry 107. This information is presented to the modem 114, and modem 114 translates the digital information into audio tones suitable for transmission over telephone wires. When the end of data mark is found on the tape the transmission is complete and the microcomputer set 100 generates signals which cause the tape to be rewound and then moved to the beginning of tape position. The portable data entry system is then ready to retransmit the data if required, and the display 109 will display the symbol &#34;POLL&#34;, which indicates to the operator that the data has been transmitted. 
     Having now set forth the functional interrelationship of the component parts of an embodiment of this invention, it is now appropriate to describe details of the structure which accomplishes the above enumerated functions. Interconnections between the various components will be indicated in the drawings. 
     In the detailed description of the circuitry, the values of resistance and potentiometers are given in ohms, and, unless otherwise noted these values have a tolerance factor of ± 5% and a power rating of one-quarter watt. The symbols &#34;K&#34; and &#34;M&#34; are used for one thousand and one million, respectively. Unless otherwise noted, values of capacitance less than 1000 pfd will have a tolerance factor of ± 10%, values of capacitance greater than 1000 pfd will have a tolerance factor of + 80%, - 20% and the working DC voltage rating of the capacitor will be 20 volts. The identification of transistors and diodes is given in their EIA-registration number wherever possible. Transistors and diodes not having EIA-registered numbers, and operational amplifiers are identified by a Motorola Semiconductor Products, Inc. designation known to persons skilled in the art. The circuitry of this invention also utilizes digital integrated circuits to perform certain functions. The integrated circuits utilized are from the series 54LS/74LS, and the series 54C/74C, and identification of components is made by utilizing these designators. These series and the individual integrated circuits are described in &#34;The TTL Book for Design Engineers,&#34; published by Texas Instruments, Inc. (1973). 
     Referring now to FIG. 3, there is shown a schematic diagram of power supply 115 which is utilized in the preferred embodiment of this invention. The circuitry is comprised of potentiometers 125 through 127, resistors 192 and 128 through 160, capacitors 193 and 161 through 172, transistors 173 through 183, diodes 194 and 181 through 185, operational amplifiers 186 through 189, voltage regulator 190, and inductor 191, all connected as shown. Transistor 177 is mounted on heatsink 195. 
     The function of power supply 115 is to supply power to the apparatus, and it derives its source of power from high quality nickel cadmium batteries. As used in the claims, the term &#34;battery&#34; should be understood to include either a single cell or a plurality of cells, connected in either series or parallel, to achieve the desire volt-amp rating required for proper operation of the portable data entry apparatus. The positive and negative sides of the battery are connected to the points v bat   +  and v bat   -  respectively. Signal POWSW becomes active the power is turned on and causes voltage regulator 190 to be turned on. One of the outputs of the voltage regulator 190 is a signal designated as GND. This signal is ground for the system, and when present, provides a flow path for current from v ccs  and v dds  to the respective components of the portable data entry apparatus. 
     Since batteries provide the source of power for the apparatus of this invention, it is desirable for the operator of this apparatus to know when the battery power is becoming low. This can be accomplished by the circuitry of power supply 115 by adjusting 125 until the voltage at the positive input to operational amplifier 188 is equal to 2.4 volts with a battery potential of 17 volts. When the battery potential difference is less than 17 volts (i.e., through use has decreased to 17 volts) the outputs of operational amplifier 188 will become active, thereby turning off transistor 180. The signal LOWBATT will then be active and inform the microcomputer set 100 (FIG. 5) of the low battery condition. Due to the programming of the microcomputer as hereinafter set forth, when the LOWBATT signal is received by the microcomputer, it proceeds to inform the operator of the low battery condition by generating appropriate signals to the digit selector 120 and to the segment selector 119. These in turn activate the display 109 with a suitable pattern, e.g., &#34;LO.&#34; The microcomputer set 100 also commands an end of data mark to be written on the tape to insure proper termination of the data record and generates signals to the deck motion control 106 to cause the tape to be rewound approximately sixteen entries. 
     When the potential difference across the batteries is less than 15.5 volts the output of operational amplifier 187 becomes active, thereby causing an electronic shut down of the unit by electronically disconnecting the batteries by removing substantially all the load from the batteries. This electronic shut down protects the batteries and prevents cell reversal. Cell reversal requires replacement of the batteries, since they can no longer be recharged. The electronic shut down feature of the apparatus of this invention protects, therefore, the user&#39;s investment in the batteries. 
     In the preferred embodiment of this invention the values of types of the various components of FIG. 3 are: 
     Potentiometer 125 has a maximum resistance of 10K, potentiometer 126 has a maximum resistance of 6K, and potentiometer 127 has a maximum resistance of 4K. 
     The values and types of the other components utilized in FIG. 3 are: 
     resistors 128, 130, 132, 133, 134, and 136: 20K; 
     resistor 129:110K; 
     resistor 131:75K; 
     resistor 135:120K; 
     resistors 137, 142, 156, and 158:10K; 
     resistors 138, 151, and 152:3.9K; 
     resistor 139:2.49 K, 1%, 1 watt; 
     resistors 140 and 153:24K; 
     resistor 141:10M; 
     resistor 143:47K; 
     resistor 144:1K; 
     resistor 145:220; 
     resistor 146:200; 
     resistor 147:100; 
     resistors 148 and 150, and 192:27K; 
     resistor 149:2K; 
     resistors 154 and 157:150K; 
     resistor 155:2.4K; 
     resistors 159 and 160:470; 
     capacitors 161 and 162:47mfd; 
     capacitor 163:100pfd; 
     capacitor 164, 168, 169 and 172:.1mfd; 
     capacitor 193:0.25mfd; 
     capacitor 165:0.01mfd; 
     capacitor 166:33pfd; 
     capacitor 167:47mfd; 
     capacitors 170 and 171:0.001mfd; 
     transistor 173:MPS 3707; 
     transistors 174, 175, and 180:2N4125; 
     transistor 176:MPS 404; 
     transistor 177 and 178:MJE 200; 
     transistor 179:MPS 5172; 
     diodes 181, 182, 184, and 185 and 195:1N914; 
     diode 183:UCD329; 
     operational amplifier 186,197, and 188:MC3302 
     operational amplifier 189:LM301 (National Semiconductor Corp); 
     voltage regulator 190:LM304 (National Semiconductor Corp); 
     inductor 191:1 millihenry. 
     Referring now to FIG. 4, there is shown the detailed schematic diagram of the proper switching unit 116 which is utilized in the preferred embodiment of this invention. It is comprised of resistors 200 through 218, inverter elements 219 through 224, transistors 225 through 232, and diodes 233 through 236, and the devices are connected as shown. 
     Since the source of power for the portable data entry apparatus of this invention is batteries, it is desirable to prolong the length of time that useful battery power is available. Power switching unit 116 accomplishes this by supplying power to certain component parts only when power to those parts is required for proper operations. For example, power is supplied to the modem 121 only when the unit is in the SEND mode and the tape is moving, and power is supplied to the tape deck only when the tape is to be moved. 
     Furthermore, battery power is conserved in the portable data entry apparatus by switching the power (V cca  and V dda ) to certain component parts of the apparatus of periodic intervals. The length of time that v cca  and v dda  are active is referred to as the &#34;awake&#34; time, and the length of time that v cca  and v dda  are inactive is referred to as the asleep time. In the preferred embodiment of this invention the maximum awake time is approximately 2.5 milliseconds, and the asleep time is approximately 7.5 milliseconds. 
     In the preferred embodiment of the portable data entry apparatus of this invention, the values and types of the components utilized in the power switching unit 116 are: 
     resistors 200 and 201:6.2K; 
     resistor 202:20K; 
     resistors 203, 205, 207, and 209:4.7K; 
     resistors 204, 206, 208, 210, 212, 213, 216 and 218:1K; 
     resistors 211 and 217:2.4K; 
     resistors 214 and 215:3.6K; 
     transistors 225 and 228:2N4403; 
     transistors 226 and 229:2N4125; 
     transistors 227, and 233, and 230:2N4401; 
     transistor 231:MJE210; 
     transistor 232:MPS5172; 
     inverters elements 219 through 224:74L04; and 
     diodes 234 through 237:1N914. 
     Referring now to FIG. 5, there is shown a portion of the microcomputer set 100 that is utilized in the preferred embodiment of this invention. It is comprised of a central processing unit (CPU) 300, a random access memory (RAM) 301, a standard memory interface set comprised of devices 302 and 305, read-only-memories (ROM) 303 and 304, decoder 306, diode 307 and 308, resistors 309, 310, and 311, diodes 312, inverter element 313, capacitors 314 through 316, and trasistors 317 and 318, and the devices are connected as shown. 
     Central processing unit 300, RAM 301, the standard memory interface set comprised of devices 302 and 303, and ROM&#39;s 303 and 304 comprise a MCS-4 microcomputer set which is vended by Intel Corp. of Santa Clara, California. Its operation is described in their Users Manual of February 1974. For ease of presentation only two ROM&#39;s 303 and 304 are shown in FIG. 5, but in the preferred embodiment of this invention, seven ROM&#39;s are utilized in the microcomputer set 100. The ROM&#39;s not shown are connected in the same fashion as the two ROM&#39;s that are shown. 
     As discussed in the Intel Corp. Users Manual for the microcomputer set, CPU 300 is preferably an Intel 4004, RAM 301 is preferably an Intel 4002-1, device 302 is preferably an Intel 4008, device 305 is preferably an Intel 4009, and the ROM&#39;s are preferably Intel 1702A&#39;s. 
     Decoder 306 is a 74L42, and it is utilized to decode the binary values assumed by the control lines which are outputs of device 302. The output corresponding to the decoded input is used to select a particular ROM which is to be accessed. Therefore, since seven ROM&#39;s are used in the preferred embodiment of this invention, seven output lines (binary values 0-6) of decoder 306 are utilized to select the appropriate ROM. Resistors 309 are pullup resistors for the outputs of the ROM&#39;s, and in the preferred embodiment of this invention are 20K in value. 
     The contents of each address of each ROM are programmed to contain a particular bit configuration. When a ROM is addressed by the CPU 300, this bit configuration is available at the output of the ROM for use by the CPU 300. The particular bit configuration is, of course, dependent upon the function that is to be performed. The preferred programming of the contents of each address of each ROM is given below. Each ROM contains 256 addresses, and the contents of each address is given in the decimal equivalent of its binary value. Those skilled in the art will realize that in order to program the ROM, a conversion from decimal to binary must be accomplished. 
     
                                           ROM Number 1__________________________________________________________________________Addresses 0 to 127AddressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    216 32   161 64   231 96   371    81  33   46  65   216 97   202    72  34   48  66   228 98   1123    84  35   47  67   82  99   2424    23  36   228 68   189 100  285    81  37   220 69   26  101  1066    77  38   81  70   73  102  817    32  39   72  71   82  103  728    48  40   85  72   163 104  649    33  41   209 73   82  105  10410   236 42   68  74   219 106  8211   177 43   229 75   46  107  3612   85  44   65  76   13  108  2013   23  45   49  77   47  109  3714   33  46   67  78   224 110  6615   48  47   223 79   126 111  7416   49  48   17  80   77  112  23717   28  49   60  81   81  113  17718   245 50   27  82   252 114  20819   82  51   142 83   20  115  22920   36  52   140 84   89  116  6421   20  53   44  85   81  117  3022   37  54   213 86   64  118  21623   18  55   46  87   64  119  22824   30  56   138 88   245 120  8425   68  57   241 89   218 121  23526   231 58   97  90   143 122  20927   84  59   118 91   26  123  22628   235 60   28  92   81  124  8229   177 61   245 93   85  125  16330   85  62   230 94   209 126  8231   173 63   209 95   64  127  235ROM Number 1Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  85  160  227 192  168 224  82129  156 161  46  193  246 225  137130  46  162  255 194  246 226  64131  93  163  47  195  18  227  37132  82  164  227 196  209 228  113133  196 165  82  197  33  229  157134  26  166  219 198  233 230  85135  209 167  81  199  96  231  178136  70  168  252 200  33  232  64137  130 169  28  201  232 233  37138  69  170  85  202  28  234  0139  37  171  218 203  167 235  82140  65  172  143 204  176 236  36141  17  173  18  205  241 237  18142  28  174  40  206  97  238  30143  245 175  43  207  127 239  68144  230 176  209 208  197 240  60145  214 177  231 209  81  241  20146  228 178  32  210  64  242  235147  85  179  12  211  64  243  213148  178 180  33  212  0   244  229149  82  181  208 213  28  245  46150  189 182  224 214  245 246  44151  26  183  97  215  82  247  82152  157 184  33  216  36  248  196153  84  185  177 217  20  249  26154  235 186  233 218  37  250  253155  82  187  20  219  18  251  65156  163 188  209 220  30  252  7157  46  189  244 221  242 253  44158  128 190  242 222  28  254  64159  47  191  191 223  228 255  85__________________________________________________________________________ 
    
     
                                           ROM Number 2__________________________________________________________________________Addresses 0 to 127AddressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    211 32   37  64   212 96   1751    26  33   233 65   83  97   2452    5   34   186 66   218 98   2453    84  35   185 67   82  99   1794    235 36   184 68   235 100  2475    82  37   183 69   83  101  1786    203 38   182 70   218 102  1717    46  39   35  71   216 103  208    86  40   224 72   46  104  1659    210 41   164 73   0   105  24610   85  42   248 74   47  106  9911   3   43   180 75   225 107  2612   83  44   99  76   192 108  10513   245 45   123 77   32  109  18714   218 46   32  78   11  110  3315   64  47   64  79   181 111  24116   33  48   37  80   240 112  23717   208 49   217 81   183 113  14718   228 50   228 82   46  114  2819   85  51   44  83   255 115  12120   173 52   50  84   44  116  23621   179 53   46  85   255 117  14622   217 54   16  86   111 118  24623   224 55   212 87   47  119  1824   36  56   85  88   227 120  13325   63  57   3   89   45  121  24126   38  58   84  90   227 122  23927   238 59   235 91   33  123  14728   40  60   82  92   234 124  2829   238 61   163 93   20  125  15230   42  62   64  94   165 126  23831   231 63   209 95   187 127  146ROM Number 2Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  246 160  241 192  235 224  203129  26  161  20  193  81  225  214130  152 162  102 194  233 226  184131  238 163  67  195  117 227  250132  16  164  245 196  220 228  125133  236 165  113 197  35  229  208134  184 166  86  198  233 230  0135  219 167  33  199  36  231  0136  136 168  164 200  203 232  0137  18  169  228 201  115 233  0138  154 170  165 202  204 234  0139  185 171  229 203  171 235  0140  209 172  166 204  246 236  0141  186 173  230 205  187 237  211142  43  174  167 206  26  238  190143  236 175  231 207  246 239  241144  20  176  192 208  81  240  216145  150 177  36  209  232 241  136146  208 178  15  210  82  242  184147  228 179  40  211  194 243  47148  105 180  224 212  26  244  226149  105 181  37  213  218 245  192150  185 182  209 214  223 246  219151  16  183  226 215  182 247  190152  162 184  82  216  65  248  126153  16  185  219 217  193 249  248154  168 186  179 218  65  250  65155  180 187  244 219  216 251  210156  182 188  189 220  0   252  83157  163 189  83  221  0   253  217158  181 190  217 222  0   254  82159  183 191  82  223  116 255  214__________________________________________________________________________ 
    
     
                                           ROM Number 3__________________________________________________________________________Addresses 0 to 127AddrressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    46  32   25  64   18  96   1931    64  33   25  65   97  97   2462    47  34   68  66   246 98   1613    216 35   229 67   114 99   204    226 36   46  68   78  100  1135    36  37   8   69   46  101  186    15  38   47  70   16  102  1167    40  39   236 71   47  103  2488    1   40   241 72   223 104  1149    42  41   143 73   229 105  10810   59  42   26  74   83  106  2811   83  43   49  75   245 107  6912   32  44   228 76   64  108  24413   20  45   176 77   37  109  17714   11  46   237 78   18  110  24015   139 47   66  79   81  111  22916   20  48   56  80   207 112  19317   32  49   238 81   209 113  24818   168 50   143 82   129 114  22819   246 51   26  83   18  115  19220   246 52   115 84   74  116  24821   18  53   230 85   242 117  3222   25  54   176 86   242 118  18723   83  55   239 87   20  119  2824   59  56   248 88   74  120  7425   101 57   177 89   217 121  8326   221 58   110 90   129 122  24527   181 59   47  91   26  123  11228   37  60   237 92   74  124  12629   224 61   178 93   242 125  19330   69  62   160 94   177 126  4631   23  63   246 95   250 127  15ROM Number 3Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  82  160  161 192  82  224  245129  237 161  224 193  235 225  26130  46  162  192 194  46  226  222131  14  163  82  195  47  227  208132  82  164  219 196  47  228  226133  196 165  83  197  234 229  218134  18  166  217 198  246 230  81135  121 167  85  199  127 231  72136  192 168  23  200  198 232  212137  85  169  28  201  191 233  83138  166 170  183 202  192 234  218139  35  171  82  203  208 235  46140  233 172  194 204  83  236  47141  99  173  18  205  218 237  210142  28  174  167 206  212 238  190143  149 175  82  207  82  239  47144  242 176  194 208  214 240  226145  224 177  18  209  234 241  190146  240 178  185 210  245 242  212147  35  179  85  211  26  243  190148  224 180  23  212  209 244  47149  35  181  20  213  208 245  190150  211 182  175 214  46  246  216151  235 183  64  215  32  247  226152  18  184  245 216  47  248  226153  69  185  46  217  226 249  0154  233 186  43  218  192 250  0155  179 187  66  219  216 251  25156  233 188  237 220  82  252  251157  242 189  218 221  214 253  127158  224 190  81  222  234 254  237159  35  191  72  223  245 255  192__________________________________________________________________________ 
    
     
                                           ROM Number 4__________________________________________________________________________Addresses 0 to 127AddressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    176 32   169 64   71  96   2461    49  33   20  65   100 97   1892    50  34   89  66   212 98   2403    179 35   43  67   148 99   1824    52  36   234 68   28  100  1925    181 37   20  69   71  101  476    182 38   82  70   180 102  2347    55  39   123 71   37  103  2458    56  40   91  72   173 104  269    185 41   250 73   248 105  13810   186 42   135 74   224 106  16011   59  43   246 75   223 107  24612   188 44   125 76   185 108  17613   61  45   50  77   38  109  16114   62  46   18  78   0   110  24615   174 47   50  79   42  111  17716   240 48   127 80   59  112  24717   225 49   75  81   192 113  22618   226 50   168 82   17  114  12419   243 51   246 83   89  115  13820   228 52   246 84   118 116  23921   245 53   18  85   100 117  18822   246 54   75  86   209 118  23823   231 55   245 87   121 119  17624   232 56   245 88   76  120  8325   249 57   26  89   241 121  3226   250 58   63  90   197 122  4727   235 59   104 91   246 123  23428   252 60   104 92   26  124  24529   237 61   208 93   95  125  2630   238 62   189 94   103 126  12031   255 63   117 95   173 127  247ROM Number 4Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  226 160  176 192  197 224  228129  168 161  85  193  242 225  44130  246 162  156 194  242 226  69131  26  163  85  195  28  227  85132  139 164  166 196  198 228  211133  241 165  160 197  184 229  26134  245 166  20  198  233 230  243135  184 167  202 199  177 231  83136  32  168  64  200  48  232  245137  255 169  241 201  192 233  82138  192 170  241 202  46  234  219139  83  171  115 203  110 235  83140  32  172  179 204  82  236  217141  163 173  98  205  196 237  46142  241 174  212 206  46  238  43143  149 175  146 207  84  239  82144  28  176  28  208  44  240  237145  170 177  179 209  102 241  81146  241 178  178 210  210 242  64147  162 179  83  211  18  243  64148  148 180  32  212  215 244  37149  28  181  47  213  64  245  216150  170 182  234 214  33  246  83151  143 183  245 215  65  247  252152  26  184  26  216  55  248  46153  136 185  179 217  214 249  41154  209 186  240 218  46  250  82155  226 187  226 219  48  251  237156  46  188  35  220  47  252  46157  12  189  210 221  226 253  16158  82  190      222  192 254  47159  237 191  18  223  211 255  226__________________________________________________________________________ 
    
     
                                           ROM Number 5__________________________________________________________________________Addresses 0 to 127AddressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    192 32   35  64   26  96   871    249 33   240 65   112 97   2172    164 34   232 66   175 98   813    176 35   20  67   246 99   724    153 36   59  68   26  100  2205    146 37   187 69   74  101  2266    131 38   208 70   85  102  1107    248 39   179 71   173 103  858    128 40   46  72   68  104  239    152 41   128 73   231 105  2810   136 42   185 74   46  106  23111   198 43   35  75   29  107  4712   143 44   233 76   82  108  23413   134 45   177 77   196 109  24614   191 46   56  78   176 110  1815   226 47   47  79   26  111  10316   146 48   227 80   87  112  21717   134 49   41  81   175 113  8118   171 50   227 82   245 114  7219   161 51   99  83   26  115  22220   140 52   111 84   97  116  22621   192 53   221 85   64  117  4622   199 54   177 86   37  118  823   34  55   113 87   85  119  8224   45  56   55  88   23  120  23725   35  57   123 89   28  121  4726   239 58   43  90   231 122  22027   176 59   192 91   46  123  22628   98  60   46  92   29  124  20929   35  61   110 93   82  125  8330   239 62   82  94   196 126  25231   178 63   196 95   26  127  219ROM Number 5Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  82  160  83  192  197 224  23129  230 161  101 193  242 225  20130  46  162  250 194  245 226  160131  14  163  43  195  245 227  67132  82  164  191 196  16  228  160133  237 165  154 197  242 229  84134  34  166  26  198  212 230  254135  0   167  172 199  180 231  83136  36  168  223 200  37  232  245137  0   169  191 201  180 233  64138  32  170  68  202  216 234  33139  255 171  198 203  226 235  82140  46  172  168 204  212 236  203141  111 173  246 205  18  237  212142  82  174  246 206  209 238  83143  196 175  18  207  105 239  252144  46  176  156 208  214 240  82145  16  177  219 209  43  241  189146  47  178  155 210  226 242  26147  26  179  20  211  38  243  240148  151 180  185 212  160 244  83149  216 181  83  213  83  245  252150  16  182  61  214  101 246  82151  219 183  68  215  83  247  185152  231 184  156 216  32  248  82153  243 185  241 217  20  249  189154  247 186  165 218  213 250  26155  230 187  147 219  17  251  237156  40  188  243 220  229 252  65157  16  189  164 221  83  253  71158  42  190  146 222  101 254  211159  59  191  26  223  85  255  44__________________________________________________________________________ 
    
     
                                           ROM Number 6__________________________________________________________________________Addresses 0 to 127AddressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    3   32   246 64   37  96   2421    46  33   26  65   82  97   2302    33  34   36  66   137 98   1313    180 35   206 67   210 99   184    209 36   192 68   129 100  975    85  37   32  69   20  101  856    174 38   0   70   75  102  1787    179 39   28  71   242 103  818    164 40   144 72   242 104  649    224 41   82  73   26  105  11810   244 42   36  74   63  106  14211   242 43   20  75   46  107  22612   180 44   63  76   79  108  8313   188 45   18  77   82  109  24514   189 46   144 78   196 110  8515   190 47   242 79   26  111  20916   191 48   20  80   83  112  8517   35  49   65  81   86  113  16618   224 50   46  82   76  114  17719   99  51   63  83   46  115  20920   116 52   47  84   77  116  23021   13  53   239 85   82  117  8422   192 54   248 86   196 118  25423   38  55   18  87   26  119  3424   80  56   58  88   91  120  1525   39  57   211 89   85  121  4426   234 58   231 90   250 122  127   245 59   113 91   81  123  22328   18  60   63  92   177 124  9929   31  61   85  93   85  125  3530   207 62   178 94   166 126  22431   246 63   64  95   238 127  125ROM Number 6Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  124 160  224 192  43  224  17129  81  161  126 193  227 225  248130  177 162  159 194  40  226  250131  221 163  127 195  4   227  234132  179 164  159 196  41  228  20133  82  165  192 197  240 229  224134  185 166  34  198  187 230  127135  35  167  60  199  234 231  224136  224 168  35  200  245 232  46137  226 169  238 201  245 233  11138  85  170  231 202  241 234  234139  209 171  178 203  246 235  28140  64  172  192 204  241 236  232141  32  173  208 205  246 237  126142  64  174  34  206  137 238  234143  0   175  32  207  185 239  127144  85  176  35  208  192 240  234145  173 177  231 209  44  241  125146  161 178  85  210  79  242  218147  248 179  166 211  82  243  46148  20  180  35  212  219 244  63149  61  181  224 213  82  245  82150  213 182  99  214  214 246  237151  145 183  35  215  213 247  241152  28  184  224 216  83  248  65153  119 185  192 217  218 249  64154  65  186  40  218  45  250  85155  19  187  137 219  216 251  186156  46  188  42  220  226 252  147157  12  189  255 221  46  253  184158  208 190  41  222  59  254  162159  47  191  227 223  47  255  186__________________________________________________________________________ 
    
     
                                           ROM Number 7__________________________________________________________________________Addresses 0 to 127AddressValue    Address         Value             Address                  Value                      Address                           Value__________________________________________________________________________0    46  32   38  64   191 96   261    0   33   248 65   190 97   1662    234 34   28  66   189 98   1853    245 35   75  67   188 99   414    18  36   44  68   43  100  2335    225 37   16  69   235 101  2416    245 38   189 70   251 102  2517    26  39   241 71   224 103  188    13  40   172 72   106 104  2179    44  41   141 73   127 105  12510   16  42   28  74   65  106  11311   70  43   46  75   192 107  13912   60  44   26  76   175 108  25113   43  45   75  77   246 109  2014   233 46   97  78   26  110  12715   251 47   113 79   128 111  6616   18  48   60  80   85  112  6917   75  49   241 81   186 113  10518   107 50   46  82   180 114  16919   188 51   153 83   169 115  24620   189 52   218 84   147 116  23321   120 53   156 85   18  117  2622   13  54   241 86   217 118  12123   211 55   251 87   131 119  24124   137 56   188 88   244 120  24525   147 57   249 89   189 121  25126   26  58   157 90   162 122  13927   75  59   189 91   184 123  25128   20  60   42  92   175 124  18729   39  61   15  93   245 125  7030   248 62   241 94   245 126  9931   20  63   220 95   208 127  192ROM Number 7Addresses 128 to 255AddressValue    Address         Value             Address                  Value                      Address                           Value128  67  160  123 192  251 224  111129  245 161  146 193  18  225  192130  85  162  220 194  196 226  163131  178 163  224 195  242 227  20132  179 164  69  196  180 228  225133  217 165  91  197  241 229  240134  224 166  147 198  118 230  43135  38  167  18  199  190 231  233136  171 168  217 200  218 232  251137  40  169  41  201  133 233  18138  208 170  233 202  18  234  247139  42  171  189 203  172 235  107140  7   172  209 204  117 236  120141  46  173  181 205  175 237  230142  133 174  241 206  173 238  210143  36  175  169 207  251 239  43144  255 176  20  208  18  240  235145  16  177  206 209  217 241  20146  99  178  248 210  132 242  36147  47  179  185 211  251 243  242148  227 180  241 212  26  244  242149  37  181  41  213  215 245  20150  227 182  233 214  248 246  36151  43  183  251 215  20  247  28152  234 184  18  216  225 248  225153  185 185  217 217  240 249  171154  184 186  244 218  179 250  185155  183 187  182 219  35  251  240156  182 188  70  220  179 252  70157  35  189  197 221  233 253  18158  224 190  164 222  251 254159  111 191  133 223  26  255__________________________________________________________________________ 
    
     Referring now to FIG. 6, there is shown the detail schematic diagram of the clock 102 which is used in the preferred embodiment of this invention. The circuitry is comprised of capacitors 350, 351, 355, 356, 359, 375, 376, and 378, crystal 354, resistors 352, 353, 358, 379, 380, and 384, transistor 357, inverter elements 360, 361, 365, 373, 374, 381, 382, and 385, NAND gates 364 and 367 through 370, NAND gates 369 and 370, flip flops 362, 363, 366, 371, and 372, MOS driver 367, and diode 383, connected as shown. 
     Reference to the Intel Corp. User&#39;s Manual for the MCS-4 microcomputer set reveals that the microcomputer has an instruction cycle time of 10.8 microseconds. During this instruction cycle two clocks must each have active states eight times. These clock pules are provided by the clock circuitry shown in FIG. 6. 
     In the preferred embodiment of this invention, crystal 354 has a frequency of 5.185 MHz. This frequency is counted down by the divide by seven counter comprised of flip-flops 362, 363, and 366. The frequency of the outputs of NAND gates 369 and 370 are, therefore, one-seventh of 5.185 Mhz. The inverter outputs of these NAND gates furnish the two clocks required by the microcomputer set 100. 
     The values and types of the various enumerated components should be: 
     capacitor 350:0.01mfd; 
     capacitor 351:10mfd; 
     capacitors 355 and 356:68pfd; 
     capacitor 359:33 pfd; 
     capacitor 378:05 mfd; 
     capacitors 375 and 376:0.001 mfd; 
     transistor 357:MPS 5172; 
     resistor 352:2.2K; 
     resistor 353:24K; 
     resistor 358:51; 
     resistors 379 and 380:10; 
     resistor 384:6.2K; 
     Nand gates 364, 367, and 368:74LS00 
     inverter element 360, 361, 365, 373, 374, 381, and 382:74LS04; 
     inverter element 385:74L04; 
     Nand gates 369 and 370:74LS10; 
     flip flops 362, 363, 366, 371, and 372:74LS73; 
     Mos driver 377:MH0026CN (National Semiconductor Inc.); and 
     diode 383:1N914. 
     Referring now to FIG. 7, there is shown a detailed schematic diagram of the port selector 103 that is used in the portable data entry apparatus of this invention. The circuitry is comprised of decoders 390 and 391, inverter elements 392 through 395, NOR gate 396, and diode 397 and is connected as shown. 
     As shown, the inputs to decoder 390 are the control signals C0, C1, and C2 from the microcomputer set 100 and the signal CPURST from the output port 105. The binary value of these inputs is decoded by decoder 390, and depending on the value of the inputs, one and only one of decoder 390&#39;s outputs will be active at any one time. The active output is used to select the appropriate output port to which the microcomputer set will output information via the input/output lines of device 305 (FIG. 5). 
     The inputs to decoder 391 are the control signals C1, C2, C3, and NIN from the microcomputer set. The decoder 391 decodes the binary value of these inputs, and one of the outputs NIN01, NIN23, NIN45, or NIN67 will be active depending upon the value of the input. The active output is used to select the input port from which data will be entered into device 305 via the input/output lines shown in FIG. 5. 
     In the preferred embodiment of the invention, the type of each element in the port selector circuitry is: 
     decoders 390 and 391:74L42; 
     inverter element 392 through 395:74L04; 
     Nor gate 396:74L02; and 
     diode 397:1N914. 
     Referring now to FIG. 8, there is shown the input port circuitry 104 which is utilized in the preferred embodiment of this invention. As shown it is comprised of data selectors 400 through 403. The data selectors are preferably 81L23&#39;s which are manufactured by National Semiconductor Corporation. 
     Referring now to FIG. 9, there is shown the output port circuitry 105 of FIG. 5 that is utilized in the portable data entry apparatus of this invention. It is comprised of storage devices 448 through 451, inverter elements 452 through 465, NAND gates 366 through 368, NOR gates 369 through 371, and resistor 372 and is connected as shown. 
     The data inputs to the output port 105 are the bidirectional input/output lines from devices 305 as shown in FIG. 5. One of the other input signals, ENOT0 through ENOT4 from the port selector 103, selects a storage element (448, 449, 450, and 451) into which data on the input/output lines is to be loaded. The data present at the output of the device selected has the same logical value as the input. 
     The types of the devices utilized in the preferred embodiment of this invention for implementation of the output port 105 are: 
     storage devices 448 through 451:74L95; 
     inverting elements 452 through 465:74L04; 
     Nand gates 466 through 468:74L00; 
     Nor gates 469 through 471:74L02; and 
     resistor 472:4.7K. 
     Referring now to FIG. 10, there is shown the read-write circuitry 107 of FIG. 2 which is utilized in the preferred embodiment of this invention. The circuitry is comprised of NAND gates 500 through 503, transistors 504 through 508, resistors 509 through 535, capacitors 538 through 544, operational amplifiers 546 and 547, comparators 549 through 551, and diodes 552 through 554, all connected as shown. 
     The function of the circuitry shown in FIG. 10 is to write digitized information onto tape and to read digitized information from tape upon command. Data is written onto tape when the command WRITE is a logical one, and while data from the tape is always available at the output of read-write circuitry 107, it is utilized only upon command from the microcomputer set 100. 
     In the preferred embodiment of this invention the values and types of the components utilized in FIG. 10 are: 
     Nand gates 500 through 503:74L00; 
     transistor 504:2N4403; 
     transistors 505 and 506:2N4125; 
     transistors 507 and 508:2N5172; 
     resistors 509 and 510:1K; 
     resistor 511:3.3K; 
     resistors 512 through 515 and 530:2.7K; 
     resistor 516 and 517:10K; 
     resistor 518 and 519:20K; 
     resistor 520 and 531:3M; 
     resistor 521:82; 
     resistor 522:4.7K; 
     resistors 523, 525, and 527:47K; 
     resistors 524 and 528:91K; 
     resistor 526:2K; 
     resistor 529:2.2K; 
     resistor 532 and 533:15K; 
     resistors 534 and 535:10K; 
     capacitor 538:150pfd; 
     capacitors 539 and 540:10pfd; 
     capacitor 541:0.01mfd; 
     capacitor 542:33pfd; 
     capacitor 543:500pfd; 
     capacitor 544:0.01mfd; 
     operational amplifiers 546 and 547:LM301 (National Semiconductor Corp); 
     comparators 549 through 5551:LM339 (National Semiconductor Corp); and 
     diodes 552 through 554:1N914. 
     Referring now to FIG. 11, there is shown the schematic diagram of the deck motion control 106 which is utilized in the portable data entry apparatus of this invention. It is comprised of transistors 1100 through 1120, operational amplifiers 1125 and 1126, resistors 1131 through 1168, capacitors 1170 through 1176, diodes 1177 through 1178 and potentiometers 1179 and 1180 and is connected as shown. In the preferred embodiment of this invention the values and types of the components shown in FIG. 11 are: 
     transistor 1100:MPS404A; 
     transistor 1101:2N4125; 
     transistor 1102:MPS5172; 
     transistors 1103 and 1104:2N4410; 
     transistor 1105:MPS404; 
     transistor 1106:2N4403; 
     transistors 1107 and 1108:2N4125; 
     transistors 1109 and 1110:MPS5172; 
     transistor 1111:MJE200; 
     transistor 1112:MJE210; 
     transistor 1113:MJE200; 
     transistor 1114:MJE210; 
     transistor 1115:MJE200; 
     transistors 1116 and 1117 and 1118:2N4403; 
     transistors 1119 and 1122:2N4401; 
     operational amplifiers 1125 and 1126:LM301 (National Semiconductor); 
     resistor 1130:1K; 
     resistor 1131:2.2K; 
     resistor 1132:1K; 
     resistor 1133:22; 
     resistor 1134:56; 
     resistor 1135:430; 
     resistor 1136:10K; 
     resistors 1137 through 1140:4.7K; 
     resistor 1141:1K; 
     resistor 1142:2.7K; 
     resistors 1143 through 1146:4.7K; 
     resistors 1147-1149:2.2K; 
     resistors 1150 and 1151:2K; 
     resistors 1152 and 1153:10K; 
     resistors 1154 and 1155:3.3K; 
     resistor 1156:22; 
     resistor 1157 and 1158:10K; 
     resistor 1159:510 
     resistor 1160:2.2K; 
     resistor 1161:2.2K; 
     resistor 1162:247K; 
     resistor 1163:2.2K; 
     resistor 1164 and 1165:82; 
     resistor 1167:1K; 
     resistor 1168:680; 
     capacitor 1170:1mfd; 
     capacitor 1171:33pfd 
     capacitor 1172:0.1mfd 
     capacitor 1173:0.1mfd; 
     capacitor 1174:33pfd; 
     capacitors 1175 and 1176:0.47mfd; and 
     diodes 1176 through 1178:1N914. 
     Referring now to FIG. 12, there is shown the schematic diagram of the alarm clock circuitry 117 of FIG. 2 which is utilized in the preferred embodiment of this invention. It is comprised of inverter elements 600 and 607, NAND gates 608 through 610, operational amplifiers 111 through 614, resistors 615 through 633, capacitors 634 through 641, diodes 642 through 645, and flip flop 646, all connected as shown. Alarm circuitry 117 receives inputs from microcomputer set 100 (FIG. 5), and generates the signal MSLEEP which is utilized to switch between the awake and asleep times. 
     In the preferred embodiment of this invention, the values and types of the components utilized are: 
     inverter element 600 through 605:74CO4; 
     inverter elements 606 and 607:74L04; 
     Nand gates 608 through 610:74C10; 
     operational amplifiers 611 through 614:LM3900 (National Semiconductor Corp); 
     resistor 615:150K; 
     resistor 616, 617, 623, and 625:510K; 
     resistor 618:5.1 M; 
     resistors 619 and 627:1.5 M; 
     resistor 620:1M; 
     resistor 621, 630, 631, and 633:1M; 
     resistor 622:330K; 
     resistor 624:5.1M; 
     resistor 626:330K; 
     resistor 628:10K; 
     resistor 629:6.2K; 
     resistor 632:10M; 
     capacitor 634:0.05mfd; 
     capacitor 635:0.002mfd; 
     capacitor 637:750pfd; 
     capacitors 638 and 639:100pfd; 
     capacitor 640:0.001mfd; 
     capacitor 641:100pfd; 
     diodes 642 through 645:1N914; and 
     flip flops 646:74C7. 
     Referring now to FIG. 13, there is shown the alarm circuitry 112 which is utilized in the preferred embodiment of this invention. The signal NALM, from output port 105, when active signifies an alarm condition. This signal turns on transistor 752 which triggers timer 753. The output of timer 753 then drives speaker 754 for a time, and this speaker can be heard by the operator of the portable data entry apparatus. 
     In the preferred embodiment of this invention the values and types of the components of the alarm circuitry are: 
     resistors 750 and 751:2.7K; 
     transistor 752:2N125&#39;s; 
     timer 753:NE555N (Signetics Corp.); and 
     capacitor 755:1mfd. 
     It should be observed that while an NE555N is the preferred type of device for timer 753, any compatible monostable multivibrator may be used in place of it. 
     Referring now to FIG. 14, there is shown bit cell timer 108 that is used in the preferred embodiment of this invention. It is comprised of flip flops 800 and 806, counters 807 and 808, decoders 809 and 810, exclusive OR gates 811 through 813, NAND gates 814 through 821, NOR gates 822 through 825, and inverter gates 826 through 830. The function of the bit cell timer is to determine the binary value of the information read from the magnetic tape. 
     In the preferred embodiment of this invention the various types of devices utilized are: 
     flip flops 800 through 806:74L73; 
     counters 807 and 808:74L93; 
     decoders 809 and 810:74L42; 
     exclusive OR gates 811 and 812:74L86; 
     Nand gates 814 through 821:74L00; 
     Nor gates 822 through 825:74L02; and 
     inverter elements 826 through 830:74L04. 
     While the foregoing schematic diagram illustrates the preferred exemplification of the bit cell timer, it should be evident to those skilled in the art of logic design that the above described circuitry could be implemented using a wide variety of devices as substitutes for those enumerated above. Any equivalents of the above enumerated circuitry should, therefore, be so construed. 
     Referring now to FIG. 15, there is shown a schematic diagram of the emitter detector 118 used in the portable data entry apparatus of this invention. The function of the emitter detector circuitry is to detect the presence of information upon the tape and to give an indication to the microcomputer set 100 via the input port circuitry when the digit is detected. The emitter detector circuitry is comprised of timers 760 and 761, transistors 762-764, resistors 765-773, capacitors 774-778, and diodes 779-784. The values and types of components utilized are: 
     timers 760 and 761:NE555N (Signetics Corp.); 
     transistor 762:MJE200; 
     transistors 763 and 764:NPS5172; 
     resistor 765:812; 
     resistor 766:1K; 
     resistor 767:470; 
     resistor 768:200K; 
     resistor 769:47K; 
     resistor 770:3M; 
     resistor 771:20K; 
     resistor 727:470; 
     resistor 773:150K; 
     capacitors 774 and 775:0.47mfd; 
     capacitor 776:0.002mfd; 
     capacitors 777 and 778:0.01mfd; and 
     diodes 779 through 784:1N914. 
     Referring now to FIG. 16, there is shown the detailed schematic diagram of the delay 113 circuitry which is utilized in the portable data entry apparatus of this invention. It is comprised of timer 850, transistors 815 through 854, resistors 855 through 864, potentiometer 865, and capacitors 866 through 868. 
     In the preferred embodiment of this invention the values and types of the components utilized in the delay circuitry of this invention are: 
     timer 850:NE555N (Signetics Corp.); 
     transistors 851, 852, and 854:MPS3702; 
     transistor 852:2N4125; 
     resistors 855, 856, and 863:1K; 
     resistors 857, 858, 862, and 864:4.7K; 
     resistor 859:30K; 
     resistor 860:10K; 
     resistor 861:1M; 
     potentiometer 865:20K (Maximum resistance); 
     capacitor 866:0.47mfd; 
     capacitor 867:0.01mfd; and 
     capacitor 868:0.05mfd. 
     Referring now to FIG. 17, there is shown the segment selector 119 that is utilized to select the appropriate segment or segments of the display 109 of FIG. 2, to be displayed. The circuitry is comprised of NAND gates 880 through 887, inverting elements 888 through 894, storage device 895, transistors 896 through 902, resistors 903 through 911, resistor packages 912 and 913, capacitors 914 through 920, and diodes 922 and is connected as shown. 
     During the period of time that inverter 894 is a logical one, NAND gates 880 through 886 are enabled and a logical one present on any of the input lines NDA0-NDA6 from the microcomputer set will cause the respective transistors 896 through 902 to be forward biased, and voltage v ccs  will be present at the collector of any forward biased transistor. The collectors of transistors 896 through 902 are connected directly to the segment inputs of display 109 (FIG. 2). 
     During the period of time that the pulse NLDSTB is active, signals NDA0 through NDA3 are loaded into storage device 895 and appear at the outputs of storage device 895. These outputs are decoded by both the digit selector 120 and the keyboard switch and interrogation assembly 121. 
     Referring still to FIG. 17, the values and types of the components in the preferred embodiment of this invention are: 
     Nand gates 880 through 887:74L00; 
     inverting elements 888 through 891, 893, and 894:74L04; 
     inverting element 892:74C04; 
     storage device 895:DM85L51 (National Semiconductor Corp.); 
     transistors 896 through 902:2N6223; 
     resistors 903 through 909:1K; 
     resistor 911:10K; 
     resistor package 912:A54504-02 (manufacturer is; 
     resistor package 913:A54505-03; 
     capacitors 914 through 920:0.001mfd (1KV, 10%); and 
     diodes 922:1N914. 
     Referring now to FIG. 18, there is shown the digit selector 120 that is utilized in a preferred embodiment of the portable data entry apparatus of this invention. It is comprised of transistors 922 through 933, decoder 934, zener diode 935, and resistor packages 936 and 937 and is connected as shown. 
     The binary value of inputs S1-S4 is decoded by decoder 934. When decoding occurs, one and only one of the outputs of the decoder 934 will be active, thereby providing a forward bias for one and only one of the transistors 922 through 933. The collectors of transistors 922 through 933 are connected to the digit inputs of display 109 (FIG. 2) and are used by display to select the proper digit which is to be displayed. 
     In the preferred embodiment of this invention the values and types of the components utilized are: 
     decoder 934:DM74L154AN (National Semiconductor); 
     transistor 922 through 933:2N6223; 
     zener diodes 935:1N746; and 
     resistor packages 936 and 937:AS4504-04-330K 
     Referring now to FIG. 19, there is shown the schematic representation of the keyboard switch and interrogation assembly 111 that is utilized in a preferred embodiment of this invention. It is comprises of decoder 938, inverting elements 939 through 942, keyboard input switch unit 943, and diodes 944 and is connected as shown. 
     Periodically inputs S1-S4 from the segment selector will be activated. During the activation, binary values of 0-9 will be assumed by the four inputs. If one of the switches from keyboard input switch unit 943 have been depressed, that fact will be detected during the scan of binary values 0 to binary value 4. Outputs KERO0-KERO3 will be active and this value will be read by the microcomputer set 100 through the input ports. 
     The values and types of the components utilized in FIG. 19 are: 
     decoder 938:DM74L42AN (National Semiconductor Corp.); 
     inverters 939 through 942:74L04; 
     keyboard input switch 943: 
     diodes 944:1N914; and 
     resistors 945:10K. 
     Referring now to FIG. 20, there is shown the high voltage power supply 110 of FIG. 2 which is utilized in the preferred embodiment of this invention. It is comprised of NAND gates 950 through 953, transistor 954 through 956, resistors 957 through 964, capacitors 965 through 967, diodes 968 through 970, inductor 971, and capacitor 990, all connected as shown. The function of this circuitry is to convert the battery voltage to a high voltage which can be utilized by a display of the gas discharge or plasma type such as display 109 of FIG. 2. Power supply 110 functions, therefore, as a power converter. 
     FIG. 20b is a simplified schematic diagram of the high voltage supply 110 which is shown in FIG. 20. It is basically a four terminal device which has four output contact points 2000, 2001, 2002, and 2003. A d-c voltage source is connected between the first contact point 2000 and the third contact point 2002. Inductor 971 is connected between second contact point 2001 and third contact point 2002. Capacitor 990 is connected between third contact point 2002 and fourth (output) contact point 2003. A diode 2004 is connected between second contact point 2001 and fourth (output) point 2003, with the cathode of diode 2004 connected to second contact point 2001. A switch 2005 is connected between first contact point 2000 and second contact point 2001. The switch 2005 of FIG. 20b is comprised of transistors 955 and 956 of FIG. 20. Oscillator 2007 periodically closes switch 2005, and it is comprised of NAND gates 950 through 953, resistors 958 through 961, and capacitor 965 in FIG. 20. The sensing circuit 2006 is connected between fourth (output) contact point 2003 and oscillator 2007. 
     When D-C power is supplied to the portable data entry apparatus, oscillator 2007 periodically closes the switch 2005 (on time -- FIG. 20a), and energy storage begins in inductor 971. When switch 2005 is open (&#34;off&#34; time -- FIG. 20a), current flows through the loop comprised of inductor 971, capacitor 990, and diode 2004. Diode 2004 operates, therefore, as a free wheeling or flyback diode. In the preferred embodiment of this invention, the duty cycle of the output of the oscillator 2007, i.e., the ratio of the off time to the on time shown in FIG. 20b, is equal to the ratio of the input voltage to the output voltage and is adjusted for efficiency. During the time switch 2005 is open, current is extracted from capacitor 990 by inductor 971. The voltage at fourth (output) contact 2003 begins to increase negatively during openings of switch 2005. If this voltage were not controlled, it would approach -400 volts in value. 
     Sensing circuit 2006 operates as a control device for the voltage at the fourth (output) contact point 2003 and prevents the voltage at that point from significantly going more negatively than -170 volts. Sensing circuit 2006 is comprised of resistors 957 and 964, capacitor 966, and transistor 954 in FIG. 20. When the signal at fourth (output) contact point 2003 reaches approximately -170 volts, sensing circuit 2006 detects this voltage. It then inhibits oscillator 2007 from making further closures of switch 2005 until the output voltage HV-170 becomes sufficiently more positive than -170 volts. Sensing circuit 2006 detects this rise in output voltage and enables oscillator 2007. Sensing circuit 2006 functions, therefore, to stop power conversions by the power supply 110 when the output voltage is significantly more negative than -170 volts and to permit power conversion when the output voltage is significantly more positive than -170 volts. The signal HV-170 (FIG. 20) is presented to display unit 109 (FIG. 2), and it is the voltage that is used to activate display 109 when a character is to be displayed. 
     The various types and values of the components in the preferred embodiment of FIG. 20 are: 
     Nand gates 950 through 953:74L03; 
     transistor 954:2N4125; 
     transistor 955:MPSA92; 
     transistor 956:NPSA42; 
     resistor 957:270K; 
     resistor 958:2K; 
     resistors 959 and 960:20K 
     resistor 961:2.2K; 
     resistor 962:680; 
     resistor 963:68; 
     resistor 964:10M; 
     capacitor 965:0.01mfd; 
     capacitor 966:150pfd; 
     resistor 967:0.47mfd; 
     diodes 968-970:1N914; 
     inductor 971:5 millihenrys; and 
     capacitor 990:0.1mfd (200v). 
     Referring now to FIG. 21, there is shown the circuitry that is utilized in conjunction with the high voltage power supply 110 in the preferred embodiment of this invention. It is comprised of transistors 975 through 977, zener diodes 978 and 979, capacitors 986 through 989, and diode 991, all connected as shown. 
     The function of the power-saving circuitry of FIG. 21 is to maintain appropriate voltages on display 109 for optimum display performance. 
     The values and types of the components of the powersaving circuitry of FIG. 21 are: 
     transistors 975 and 977:2N4888; 
     transistor 976:MPSA42; 
     zener diode 978:1N5275; 
     zener diode 979:1N5257; 
     resistor 980:39K; 
     resistor 981:3.9M; 
     resistor 982:2K; 
     resistor 983:1K; 
     resistor 984:20K; 
     resistor 985:10M; 
     capacitor 986:0.47 mfd; 
     capacitor 987:1mfd (WDCV=50v); 
     capacitor 988:150pfd (WDCV=1000); 
     capacitors 989:0.1mfd (WDCV=200); and 
     diode 991:1N914. 
     Referring now to FIG. 22, there is shown a portion of the modem circuitry 114 that is utilized in the portable data entry apparatus of this invention. It is comprised of transistors 1000 through 1005, diodes 1006 through 1009, resistors 1010 through 1020, and capacitor 1021. This circuitry is utilized to interface with a Data Access Arrangement. 
     The values and types of the components utilized in this portion of the modem circuitry 114 are: 
     transistors 1000, 1002, 1003 and 1005:MPS3702; 
     transistors 1001 and 1004: MPS5172; 
     diodes 1006 through 1009:1N914; 
     resistors 1010, 1013, 1016, and 1020:4.7K; 
     resistors 1011 and 1018:62; 
     resistors 1012 and 1017:1K; 
     resistors 1014 and 1019:220; and 
     capacitor 1021:0.04mfd. 
     Referring now to FIG. 23, there is shown another portion of the modem circuitry 114 that it utilized in the preferred embodiment of this invention. It is comprised of flip flops 1025 through 1027, timer 1028 NAND gates 1029 and 1030, inverter elements 1031 through 1035, transistors 1036 through 1038, voltage controlled oscillator 1039, operational amplifiers 1040 and 1041, potentiometers 1042, 1060, and 1061, capacitors 1062 through 1070, and resistors 1043 through 1059, all of which are connected as shown in the Figure. 
     The values and types of the components utilized in this portion of the modem circuitry 114 are: 
     flip flops 1025 through 1027:74L73; 
     timer 1028:NE555 (Signetics Corp); 
     Nand gates 1029 and 1030:74L00; 
     inverter elements 1031 through 1035:74L04; 
     transistor 1036:2N4125; 
     transistor 1037:MPS404; 
     transistor 1038:MPS3707; 
     voltage controlled oscillator 1039:8038EC (Intersil Corp); 
     operational amplifiers 1040 and 1041:LM301 (National Semiconductor Corp.); 
     potentiometer 1042:20K (maximum resistance); 
     resistor 1043:220K; 
     resistor 1044:15K; 
     resistor 1045:22K; 
     resistor 1046:1K; 
     resistor 1047:1K; 
     resistor 1048:30K; 
     resistor 1049:3.92K (1% metal film); 
     resistor 1050:3.74K (1% metal film); 
     resistor 1052:26.7K (1% metal film); 
     resistor 1052:127.0K (1% metal film); 
     resistor 1053:14.7k (1% metal film); 
     resistor 1054:1K; 
     resistor 1055:82K; 
     resistor 1056:27K; 
     resistors 1057 and 1058:1k; 
     resistors 1059:510; 
     potentiometer 1060:4002-P-1-402 (4K maximum rating); 
     potentiometer 1061:4002-P-163 (maximum rating 8K); 
     capacitor 1062:0.05mfd; 
     capacitor 1063:4700pfd; 
     capacitor 1064:0.01mfd; 
     capacitor 1065:0.05mfd; 
     capacitor 1066:4700pfd; 
     capacitors 1067 and 1070:100pfd; 
     capacitors 1068:0.05mfd; and 
     capacitor 1069:200mfd.