Abstract:
An apparatus and method for storing data in a semiconductor memory. In accordance with some embodiments, the semiconductor memory has a continuous storage layer of soft ferromagnetic material having opposing top and bottom surfaces with overall length and width dimensions and an overall thickness dimension between the opposing top and bottom surfaces. A plurality of spaced apart, discrete reference layers are adjacent a selected one of the opposing top or bottom surfaces of the continuous storage layer with each having a fixed magnetic orientation. A plurality of spaced apart, discrete barrier layers are disposed in contacting relation between the discrete reference layers and the continuous storage layer.

Description:
RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 12/938,424 filed Nov. 3, 2010 (issuing on Jul. 9, 2013 as U.S. Pat. No. 8,482,967) 
    
    
     SUMMARY 
     Various embodiments of the present invention are generally directed to an apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. 
     In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. In some embodiments, a thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation. 
     These and various other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  provides a functional block representation of a data storage device. 
         FIG. 2  depicts a portion of a memory module of  FIG. 1 . 
         FIG. 3  shows an exemplary construction for a magnetic memory element of  FIG. 2 . 
         FIG. 4  illustrates a write sequence used to transition the memory element of  FIG. 3  from a first resistive state to a second resistive state. 
         FIG. 5  shows a top plan view representation of the storage layer of  FIG. 4  in the second resistive state. 
         FIG. 6  depicts a plurality of adjacent memory elements that share a continuous storage layer. 
         FIG. 7  represents different regions of the continuous storage layer of  FIG. 6  with transitioned magnetic domains in accordance with  FIGS. 4-5 . 
         FIG. 8  shows an alternative configuration for a memory element in accordance with various embodiments. 
         FIG. 9  is a top plan view of the storage layer and reference layer of  FIG. 8 . 
         FIG. 10  illustrates a write sequence used to transition the memory element of  FIG. 8  from a first resistive state to a second resistive state. 
         FIGS. 11A-11D  show further alternative configurations for a memory element in accordance with various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure is generally directed to improvements in the manner in which data are written to and retained by a magnetic memory cell. Some types of storage devices utilize a solid-state data storage array of memory cells, with each cell being individually programmable to a selected programmed state. The cells may be volatile or non-volatile, and can take a write-once or write-many configuration. 
     Of particular interest are magnetic memory data storage cells that utilize magnetic tunneling to establish a selected programmed state, such as in the case of spin-torque transfer random access memory (STRAM) cells. A magnetic memory cell can include an antiferromagnetic reference layer with a selected magnetic orientation, and a free layer with a selectively programmable magnetic orientation. The relative orientation of the free layer with respect to the reference layer determines an overall electrical resistance of the cell. 
     Generally, a parallel orientation will provide a first electrical resistance through the cell, and an anti-parallel orientation will provide a second electrical resistance through the cell. The programmed state of a given cell can be determined by sensing a voltage drop across the cell responsive to the application of a low magnitude read current. 
     While operable, a limitation associated with many types of magnetic memory elements relate to the write effort required to establish different programmed states. Significant amounts of write current and/or write current pulse duration may be required to transition the cell to a selected state, particularly when the cell is switched to the antiparallel orientation. 
     Accordingly, various embodiments of the present invention are generally directed to an apparatus and method for enhancing the ability to write data to and retain the written data in a magnetic memory data storage cell. As explained below, a free layer is sized relative to a reference layer within a magnetic memory element so that the free layer has multiple magnetic domains in at least one programmed state. In some embodiments, a thermal assist layer is incorporated into the cell structure to assist in the writing process. The cell structure is particularly suitable for use as a write-once memory as an alternative to fuse-based random access memories (ROMs). The cell structure can also be configured as a write-many memory as an alternative to flash and electrically erasable and programmable read only memories (EEPROMs). 
       FIG. 1  provides a simplified block representation of a data storage device  100  to illustrate an exemplary environment in which various embodiments of the present invention can be advantageously practiced. The device  100  includes a top level controller  102  and a memory module  104 . The controller  102  may be programmable or hardware based and provides top level control of I/O operations with a host device (not shown). The controller  102  may be a separate component or may be incorporated directly into the memory module  104 . 
     The memory module  104  includes an array of non-volatile memory cells  106  as set forth in  FIG. 2 . Each memory cell  106  includes a magnetic memory data storage element  108  and a switching device  110 . While not limiting, it is contemplated that the memory cells  106  are spin-torque transfer random access memory (STRAM) cells. The memory elements  108  incorporate magnetic tunneling junctions (MTJs) and the switching devices  110  are n-channel metal oxide semiconductor field effect transistors (nMOSFETs). Other configurations can be used. 
     The memory elements  108  are depicted as variable resistors selectively programmable to different resistive states. In some embodiments, single level cells (SLCs) are used with a low resistance R L  corresponding to a first stored data state of logical 0, and a high resistance R H  corresponding to a second stored data state of logical 1. The cells may alternatively be configured as multiple level cells (MLCs) to store multiple bits per cell, such as the use of four different programmed resistances to store two bits per cell. 
     Data access operations are carried out via bit lines (BL)  112 , source lines (SL)  114  and word lines (WL)  116 . The source lines  114  may be connected to a common source plane. The memory module  104  may be arranged into addressable blocks of fixed-size storage, with each block being separately allocated as needed. The blocks may further be arranged as a plurality of pages which are concurrently written or read during data access operations, with each page constituting all of the cells  106  coupled to a common word line  116 . In this way, the module  104  can be configured and operated in a manner similar to a flash array. It will be appreciated that other configurations can be used, such as cross-point arrays with diodes or other suitable mechanisms to direct access currents through the cells. 
       FIG. 3  provides a schematic representation of an exemplary configuration for the memory elements  108  of  FIG. 2 . Each memory element  108  includes top and bottom electrodes  118 ,  120  (TE and BE, respectively). A reference layer (RL)  122  is provided with a fixed magnetic orientation in a selected direction. The reference layer  122  can take a number of forms, such as an antiferromagnetic pinned layer  124  with the fixed magnetic orientation established by an adjacent pinning layer  126 . A barrier layer  128  separates the reference layer  122  from a soft ferromagnetic free layer  130 , also referred to herein as a storage layer. 
     The storage layer  130  has a selectively programmable magnetic orientation that is established responsive to the application of write current to the element  108 . The orientation of the storage layer  130  may be in the same direction as the orientation of the reference layer  122  (parallel), or may be in the opposing direction as the orientation of the reference layer  122  (antiparallel). Parallel orientation provides a lower resistance R L  through the memory cell, and antiparallel orientation provides a higher resistance R H  through the cell. It is contemplated that the magnetization direction will be perpendicular (i.e., in the vertical direction with respect to the drawing) but this is not necessarily required. 
     The storage layer  130  is shown to have a greater areal extent than the areal extent of the reference layer  122 . This allows the storage layer to establish and maintain multiple opposing magnetic domains during programming. The respective reference and storage layers  122 ,  130  may be circular (disc shaped), with the storage layers having a larger diameter than the reference layers. Other shapes for the reference and/or storage layers may be used, however, such as rectilinear. The storage layers may be discrete layers within each memory cell, or may be formed from a single layer that continuously extends across the array. 
       FIG. 4  shows an exemplary write sequence for the storage layer  130  of  FIG. 3 . Four successive steps are identified as (A) through (D). At step (A), the storage layer  130  is shown to have an initial magnetic orientation, as represented by upwardly extending arrows  132 . This initial magnetic orientation is parallel to the magnetic orientation of the reference layer  122 , and places the element  108  in the low resistive state R L  (e.g., logical 0). 
     It will be noted that the magnetic orientation of the storage layer  130  in step (A) is arranged as a single magnetic domain, in that the entire storage layer  130  is uniformly magnetized so as to be parallel with the magnetization of the reference layer. To establish the initial state of step (A), the magnetic stack can be saturated in a strong magnetic perpendicular field so the magnetizations of the pinned layer and the data storage layer are pointing in the same direction. 
     To write the element  108  to the high resistive state R H  (e.g. logical 1), a suitable write current is applied through the element, as shown beginning at step (B). This write current does not pass through all of the storage layer  130 , but rather passes substantially through that portion of the storage layer  130  that is aligned with the reference layer  122 . This middle region of the storage layer is denoted as  134 , and undergoes a localized change in magnetization responsive to the current and the associated heating provided by I 2 R heat dissipation through the storage layer. As the write current passes through the middle of the storage layer  130 , an outer annular region  136  of the storage layer retains its initial magnetic orientation  132 . 
     During initial application of the write current, the magnetization of region  134  remains parallel to the magnetization of the reference layer  122  ( FIG. 3 ), but is reduced in magnitude as shown at step (B). Due to the non-uniform magnetization of the middle region  134 , a demagnetizing field  138  will be generated. As the write current continues to be applied, the demagnetizing field acts to reverse the magnetization of the middle region, as indicated at step (C). 
     Once the write current has been removed and the data storage layer  130  returns to ambient temperature, the magnetization of the middle region  134  will have been reversed, as shown at step (D). A circumferentially extending domain wall  140  will be established between the antiparallel middle region  134  and the surrounding, parallel outer region  136 . Magnetic coupling across the domain wall  140  is represented by dashed arrows  142 , and this magnetic coupling helps to retain the antiparallel magnetization of the middle region  134 . 
     The magnetic dipole coupling between the respective magnetic domains of regions  134 ,  136  will compete with the domain wall  140  for a short time until a steady-state condition is reached. Once the cell is stabilized, the central domain size (diameter of the domain wall  140 ) will be determined by a number of properties associated with the data storage layer. These properties may include intrinsic characteristics such as saturation magnetization, exchange coupling, and magnetic anisotropy, as well as extrinsic characteristics such as the thickness and surface roughness of the data storage layer. 
     The size of the central domain may further be established in relation to the amount of heating experienced by the storage layer, and other current induced effects such as the magnitude, direction, duration and current pulse shape. Any number of suitable ferromagnetic films can be used for the storage layer  130 , such as Cobalt-Nickel (CoNi) and Platinum (Pt) based films. Different films may provide different domain sizes responsive to a given write current.  FIG. 5  shows exemplary sizes of the respective regions  134 ,  136  at the conclusion of the write sequence of  FIG. 4 . 
       FIG. 6  is an elevational representation of a number of the memory elements  108  (denoted ME1-ME4) that share a continuous data storage layer  150 . Empirical analysis has indicated that localized magnetization reversal of some types of magnetic films as set forth by  FIG. 6  can be carried out by the application of write current pulses on the order of about +5 volts, V in amplitude and about 500 nanoseconds, ns in duration. The magnitude of write current can be on the order of about 100 microamps, μA. Other suitable values can be used. 
       FIG. 7  is a top plan representation of the continuous storage layer  150  of  FIG. 6  to which write pulses have been applied to provide localized circular regions  152  of antiparallel magnetization. For reference, regions  154  represent middle portions of memory cells which retain the initial parallel magnetization. The average size of the programmed regions may be on the order of about 100 nanometers, nm, although programmed regions as small as about 70 nm were also observed. The coercivity of the magnetic films can be as high as 5,000 Oe. Magnetization reversal by heating may be easier to achieve in lower coercivity films, and the domains may be larger on magnetic films with lower coercivity. In addition, the diameter of the domains may be dependent on the pulse amplitude and duration. 
     The memory array can be used as a write-once read-many magnetic memory array with all of the cells  108  initially programmed to the low resistance (logical 0) state. To write data, logical ls can be written in the appropriate locations as set forth by  FIG. 4 . 
     To subsequently read back the stored data, the word lines  116  can be activated to place the switching device  110  of each selected cell in turn into a source-drain conductive state, a low magnitude read current can be passed from the associated bit line  112  to the associated source line  114 , and the magnitude of the voltage drop across the cell can be sensed using a sense amplifier or other suitable detection mechanism. Since the read current will tend to select the shortest path through the cell, it is contemplated that a majority of the read current will pass through the middle region  134  ( FIG. 4 ) of the data storage layer. The resistance of the magnetic stack will thus vary in relation to the magnetization orientation of the middle region with respect to the magnetization of the pinned layer. 
     An alternative construction for a memory element in accordance with various embodiments is shown at  160  in  FIG. 8 . The memory element  160  includes top and bottom electrodes  162 ,  164 , a reference layer (RL)  166  with pinned and pinning layers  168 ,  170 , a barrier layer  172 , and free layer (FL)  174 . The free layer (storage layer)  174  is offset in relation to the reference layer  166 , such as shown by  FIG. 9  which provides exemplary rectilinear areal shapes of these respective layers. Other configurations are contemplated, such as a strip of storage layer material that is offset to span multiple adjacent cells along a selected row or column in an array. 
     A write sequence for the storage layer  174  is depicted by  FIG. 10 . The write sequence is generally similar to that previously discussed in  FIG. 4  except that the domain wall  140  extends across the storage layer  174  so that the parallel region  136  extends adjacent to, but does not fully encircle, the antiparallel region  134 . 
       FIGS. 11A-11D  show further alternative memory element configurations.  FIG. 11A  illustrates a memory element  180  with top and bottom electrodes  182 ,  184 , pinned layer  186 , pinning layer  188 , barrier layer  190  and storage layer  192 . These layers are generally similar to the layers set forth in  FIG. 3 . A thermal assist layer  194  is additionally incorporated into the element  180 . The thermal assist layer  194  is in contacting engagement with the storage layer  192  opposite the tunnel barrier  190 . 
     The thermal assist layer  194  is formed of a thermally resistive material which operates to enhance the heating effect during writing. This generally allows higher localized temperatures to be established in the middle region  134  with a lower current pulse and/or duration. The thermal assist layer  194  can take a variety of forms, such as a relatively thin dielectric layer (e.g., MgO) or electrically conductive materials such as Tantalum (Ta), Bismuth-Tellurium (BiTe) or Chromium-Platinum-Manganese-Boron (CrPtMnB) alloys. As before, the storage layer  192  can be a continuous layer or a discrete region within each memory element. 
       FIG. 11B  shows a memory element  200  with a reversed stack orientation that may provide certain manufacturing efficiencies. Top and bottom electrodes are shown at  202 ,  204 . A storage layer  206  is formed on the bottom electrode  204 , followed by a tunnel barrier  208  and pinned/pinning layers  210 ,  212 . A layer of thermal assist material  214  can be incorporated into the memory element  200  as depicted in  FIG. 11C . 
       FIG. 11D  shows another memory element  220  with top and bottom electrodes  222 ,  224 , pinned/pinning layers  226 ,  228 , tunnel barrier  230  and a segmented storage layer  232 . During manufacturing the storage layer  232  can be etched to provide an annular groove  234  that extends fully or partially through the thickness of the storage layer  232 , thereby physically separating a middle antiparallel region  236  and a surrounding parallel region  238 . The groove  234  can be filled with a suitable oxide or other material to enhance domain wall location and stability. As before, thermal assist material can be incorporated into the stack to enhance writing efficiency. 
     Other configurations will readily occur to the skilled artisan in view of the present disclosure, such as cell stack structures with multiple free layers including multiple continuous storage layers that span the memory cells in an array, or structures that have one continuous storage layer that spans the memory cells in an array and at least one additional localized free layer in each cell. Multiple reference layers may also be provided in each cell, including reference layers that span multiple memory cells in an array. 
     It will now be appreciated that the various embodiments disclosed herein can provide a number of benefits. Establishing multiple magnetic domains within a continuously extending storage layer can enhance the ability to write and retain data within the memory cell. The non-transitioned portion(s) of the storage layer can assist in the magnetic switching of the transitioned portion(s) of the layer during the writing operation, and the non-transitioned portion(s) can further help to maintain the transitioned portion(s) in the desired orientation after the writing operation has completed. The use of thermal assist material can enhance the localized writing of the transitioned domains, allowing the use of reduced write current magnitudes and/or durations. 
     The various embodiments disclosed herein are suitable for use in a write-once memory. The initial orientations of the reference and free (storage) layers can be induced during manufacturing from an external magnetic source, and then the local areas of reversed magnetization within the storage layer can be generated as desired to write data to the memory. However, it is contemplated that the various memory elements disclosed herein can be readily rewritten to the initial state by the application of appropriate write current and duration to reverse the process and provide the storage layer with a single domain. 
     It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.