Abstract:
In an analog-to-digital conversion system, the system includes: a voltage conversion circuit selectively obtaining at least three kinds of conversion voltages, i.e., a first conversion voltage which is double the input voltage, a second conversion voltage which subtracts a reference voltage from the first conversion voltage, and a third conversion voltage which adds the reference voltage to the first conversion voltage; a comparison circuit using at least two decision level voltages and comparing the input voltage with each of the decision level voltages, then outputting the command signal as a result of a comparisons to the voltage conversion circuit so that the voltage conversion circuit outputs one of the conversion voltages in response to the command signal; and a control circuit for changing the connections of switch contacts provided in the voltage conversion circuit in response to the result of the comparisons by the comparison circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an analog-to-digital conversion system. 
     2. Description of the Related Art 
     Conversion of an analog value, for example, an analog voltage, to digital codes is usually performed in the field of measurements. In general, it is necessary that the requirements of the conversion method comprise such characteristics as a high conversion speed, high resolution, small power consumption, and small quantizing errors. A well known technique is that a cyclic analog-to-digital (A/D) conversion method is used in the analog-to-digital conversion circuit. This circuit is usually constituted by an integrated circuit (IC). In the conventional cyclic A/D conversion method, only one decision level voltage is applied to a comparator from an external circuit. An analog input voltage is sequentially compared with this decision level voltage, then code conversions are performed based on the generated digits obtained from resultant data of the comparison. 
     There are however, problems regarding the decision level voltage which is applied from the external circuit. That is, it is difficult to set the decision level voltage within the predetermined range of the offset value caused by, for example, characteristic fluctuations of circuit elements. The larger the offset value, the more errors in the generated digit. These problems will be explained in detail hereinafter. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide an analog-to-digital conversion method enabling high speed conversion, high resolution and small quantizing errors regardless of the offset value of the decision level voltage when an analog value is converted to digital codes. 
     In accordance with the present invention, there is provided an analog-to-digital conversion system including: a voltage conversion circuit selectively obtaining at least three kinds of conversion voltages, i.e., a first conversion voltage which doubles the input voltage, a second conversion voltage which subtracts a reference voltage from the first conversion voltage, and a third conversion voltage which adds the reference voltage to the first conversion voltage; a comparison circuit setting at least two decision level voltages and comparing the input voltage with each of those decision level voltages, then outputting a command signal as a result of the comparison to the voltage conversion circuit so that the voltage conversion circuit outputs one of the conversion voltages in response to the command signal; and a control circuit for changing the connections of switch contacts provided in the voltage conversion circuit in response to the result of the comparison by the comparison circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a partial block diagram of a conventional analog-to-digital conversion system, 
     FIG. 2 is a partial block diagram of an another conventional analog-to-digital conversion system, 
     FIG. 3 is a characteristic diagram of an input/output voltage of the circuit shown in FIG. 1, 
     FIG. 4 is an another characteristic diagram of an input/output voltage of the circuit shown in FIG. 2, 
     FIG. 5 is a partial block diagram of an analog-to-digital conversion system according to an embodiment of the present invention, 
     FIG. 6 is a characteristic diagram of input/output voltage of the circuit shown in FIG. 5, 
     FIGS. 7A to 7D and detailed circuits of the conversion circuit according to an embodiment of the present invention, 
     FIG. 8 is a schematic block diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention, 
     FIG. 9 is a chart for explaining the operation of circuits shown in FIG. 8, 
     FIG. 10 is a view for explaining operation of the shift registers and an adder, 
     FIG. 11 is a partial circuit diagram of a conventional adder, 
     FIG. 12 is a function chart of the circuit shown in FIG. 11, 
     FIG. 13 is a schematic block diagram of an analog-to-digital conversion circuit according to another embodiment of the present invention, 
     FIG. 14 is a timing chart of each voltage in the circuit shown in FIG. 13, 
     FIG. 15 is a chart for explaining patterns of the voltages of FIG. 14, and 
     FIG. 16 is a chart for explaining a conversion range and output codes of the A/D conversion in the best mode. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing the preferred embodiments, an explanation will be given of a conventional analog-to-digital conversion system. Referring to FIG. 1, reference numeral 1 represents a voltage conversion circuit for converting an input voltage V i  to an output voltage V o  based on a predetermined formula. Reference number 2 represents a comparator for comparing the output voltage V o  with a decision level voltage. The decision level voltage, for example, 0 V, is input to the comparator 2 from an external circuit (not shown). V R  represents a reference voltage for converting the input voltage V i  to the output voltage V o . A command signal generated from the comparator 2 to the conversion circuit 1 is represented by a. The signal a takes two states (0, +1) or (0, -1) based on the decision level voltage 0 V. The control method using these two values is called &#34;two states control&#34;. 
     In the conversion circuit, the output voltage V o  is calculated by the predetermined formula, i.e., V o  =2V i  -a·V R . In this case, as explained in detail hereinafter, although the input voltage V i  is an external voltage in the first stage of the calculation, the resultant data V o  is used as the V i  in the next stage of the calculation. This calculation is continued until the resultant data V o  becomes zero. In each stage of the calculation, the resultant data V o  is compared with the decision level voltage (for example, 0 V). 
     This method is called a cyclic A/D conversion method. As is obvious from the above explanation, only one decision level voltage (for example 0 V) is used as a judgement reference level. 
     Referring to FIG. 2, the decision level voltage is also set to 0 V. Moreover, the input voltage V i  is compared with this decision level voltage in the input side by the comparator 2. In this case, the same formula (V o  =2V i  -a·V R ) as the first conventional circuit is used as the conversion formula, and only one decision level voltage (for example, 0 V) is also used as the judgement reference level. That is, when the voltage V i  is larger than the 0 V, the command signal a is &#34;+1&#34;. Conversely, when the voltage V i  is smaller than the 0 V, the command signal a is &#34;-1&#34;. In this case, the same cyclic A/D conversion method as explained in FIG. 1 is used for obtaining the conversion voltage. 
     Referring to FIG. 3, in practice the first quadrant area is used for conversion (i.e., a positive analog voltage is converted to digital codes). In this case, the range of the input voltage V i  is 0 to V R  (V) and the range of the quantizing error is 0 to 1LSB. The quantizing error is a bit error always occurring when the voltage value is converted to the digital value. &#34;LSB&#34; is the least significant bit. The turning over voltage is set to V R  /2, and when V i  is larger than V R  /2, the signal a is &#34;+1&#34;. Conversely, when V i  is smaller than V R  /2, the signal a is &#34;0&#34;. Accordingly, in this area, the output voltage V o  is shown by 2V i  (a=0) or by 2V i  -V R  (a=+1). 
     However, since there is an offset ΔV of the turning over voltage V R  /2, the range in which it is impossible to convert from the input voltage to the output voltage occurs in the range of the output voltage V o , as shown by dotted line. This will be explained in detail with reference to FIG. 4. 
     Referring to FIG. 4, two input/output characteristic lines represent V o  =2V i  -V R  (a=1) and V o  =2V i  +V R  (a=-1). In this case, the range of the input voltage V i  is -V R  to +V R  and the range of quantizing error is -1 to +1LSB. The command signal a is &#34;-1&#34; or &#34;+1&#34; in the two states control. This type of conversion is used for both positive and negative analog voltages. 
     As explained above, since there is the offset voltage ΔV of the decision level voltage 0 V, the range in which it is impossible to convert from the input voltage to the output voltage occurs in the range of the output voltage V o  as an &#34;over range&#34;. That is, the output voltage V o  in the range of 0 to ΔV of the input voltage V i  exceeds the reference voltage V R , as shown by dotted line. This is because the command signal a is &#34;-1&#34; in this range although a is &#34;1&#34; if no offset voltage ΔV is found. 
     The offset of the decision level voltage is always brought about by fluctuations of electrical values of the circuit elements and by the conditions of the circuit arrangement in the comparator. Meanwhile, the smaller the offset voltage, the better the condition of the decision level voltage in the use of the comparator. there is, however, a limitation to the offset voltage caused by the above explained fluctuations and conditions. 
     Another problem lies in the larger quantizing error. The smaller the quantizing error, the better the conversion to digital codes. However, in this input voltage range, the quantizing error lies in the range of -1 to 1LSB. 
     An analog-to-digital conversion method according to the present invention will be explained in detail hereinafter. Referring to FIG. 5, reference number 11 represents a conversion circuit, and 12 a comparator. In the comparator 12, two decision level voltages, for example, V R  /4 and -V R  /4, are applied as the judgement reference levels. This type corresponds to the circuit shown in FIG. 2. Accordingly, when the input voltage V i  is larger than V R  /4, the command signal a is &#34;+1&#34;, when the input voltage V i  is in the range of V R  /4 to -V R  /4, the signal a is &#34;0&#34;, and when the input voltage V i  is smaller than -V R  /4, the signal a is &#34;-1&#34;. The control method of this type is called &#34;three states control&#34;. 
     The same conventional formula is applied to the conversion circuit 11. That is, the conversion formula from the input voltage to the output voltage is shown by the formula V o  =2V i  -a·V R . Since the same cyclic A/D conversion method as the conventional one is used, the same calculations are performed in the conversion circuit 11. Accordingly, three formulae, i.e., V o  =2V i  -V R , V o  =2V i , and V o  =2V i  +V R , are given in correspondence with a=+1, 0, and -1 as the &#34;three state control&#34;. 
     Referring to FIG. 6, three characteristic lines are shown by the formula V o  =2V i  -V R  (when a=1), V o  =2V i  (when a=0), and V o  =2V i  +V R  (when a=-1). The decision level voltage V 1  is set to, for example, approximately V R  /4 and the decision level voltage V 2  is set to, for example, approximately -V R  /4. As is obvious from the diagram, the input/output characteristic line is divided into three lines based on two decision level voltages. Conventionally, the input/output characteristic line is divided into two lines as shown in FIGS. 3 and 4, based on only one decision level voltage. 
     As is obvious from the graph, the input voltage V i  is in the following range. That is, ##EQU1## Accordingly, the decision level voltages V 1  and V 2  can be set to the following range. That is, 
     
         0≦V.sub.1 ≦V.sub.R /2 
    
     
         -V.sub.R /2≦V.sub.2 ≦0 
    
     Therefore, the decision level voltages V 1  and V 2  may be set to approximately central values in the above ranges. That is, 
     
         V.sub.1 ≈V.sub.R /4 
    
     
         V.sub.2 ≈-V.sub.R /4 
    
     In this case, the fluctuation values ±V R  /4 can be allowed as margin of the above decision level voltages because the output voltage V o  does not exceed the possible conversion range (V R  to -V R ) in the range of the decision level voltages V 1  and V 2  (0≦V 1  ≦V R  /2 and -V R  /2≦V 2  ≦0). Therefore, an offset voltages can be allowed in the range of ±V R  /4. These values are sufficiently large to cope with fluctuations by the elements. 
     Next, the effect of the quantizing error will be explained below. 
     Regarding the decision level voltage V 1 , the input voltage V i  is given by, ##EQU2## where, Δ 1  is a fluctuation rate of V 1 . 
     Accordingly, the converted output voltages V o  when the signal a is &#34;0&#34; and &#34;1&#34; are shown by following formula. ##EQU3## 
     Regarding the decision level voltage V 2 , the input voltage V 1  is given by, ##EQU4## where, Δ 2  is a fluctuation rate of V 2 . 
     Accordingly, the converted output voltage V o  when the signal a is &#34;0&#34; and &#34;-1&#34; is shown by the following formulas. ##EQU5## Therefore, the maximum value of the quantizing error (absolute value) is given by the following formula. 
     
         LSB/2×(1+max[|Δ.sub.1 |, |Δ.sub.2 |]) 
    
     Accordingly, if the fluctuation rate is &#34;x&#34;%, the quantizing error becomes 1/2LSB(1+x/100). 
     Next, the explanation will be given regarding the quantizing error in the vicinity of the voltage ±V R . In this case, the following formula is given in the vicinity of the voltage ±V R . 
     
         V.sub.i =V.sub.R -ΔV.sub.x 
    
     where, ΔV x  is the fluctuation rate from the end value V R . The normalized above formula is given as follows. 
     
         X.sub.0 =1-ΔX 
    
     where, X 0  is the normalized V i  by V R , and ΔX is the normalized ΔV x  by V R . Accordingly, since a=1, X 0  ≈1, the formula is given as follows. ##EQU6## This formula is equivalent to the quantizing error when n bits conversions are completed. 
     As the conditions of X n  ≦1/2, in the following formula is given, ##EQU7## Therefore, in the vicinity of the voltage ±V R , the quantizing error always becomes less than the value 1/2LSB. 
     The effect of the present invention will be explained by using actual data in comparison with the conventional art. 
     In the cyclic A/D conversion, the reference voltage V R  is given by 1 (V) and the input voltage V i  is given by 7/16 (V). 
     (1). In the case of a non-fluctuation rate of the decision level voltage. 
     A. In the conventional art (see: FIGS. 2, 4) 
     The decision level voltage: 0 (V) 
     The conventional formula: ##EQU8## 
     Accordingly, the generated digits are obtained as follows. 
     Generated digits: 1 -1 1 1 
     Plus/minus code conversions of this data are performed as follows. ##EQU9## 
     B. In the present invention (see: FIGS. 5, 6) 
     Two decision level voltages: -V R  /4, V R  /4 
     The conversion formula: ##EQU10## 
     Accordingly, the generated digits are obtained as follows. 
     Generated digits: 1 0 0 -1 / 
     Plus/minus code conversion of this data are performed as follows. ##EQU11## 
     (2). In the case of a fluctuation rate ΔV=1/8 of the decision level voltage. 
     A. In the conventional art (see: FIGS. 2, 4) 
     The decision level voltage is changed from 0 (V) to -1/8 (V). ##EQU12## 
     This value (-5/4) means &#34;over range&#34;, as shown by the dotted line in FIG. 4. ##EQU13## 
     Accordingly, the generated digits are obtained as follows. 
     Generated digits: 1 1 -1 -1 
     Plus/minus code conversions of generated digits are performed as follows. ##EQU14## 
     This data is an error and should become 7/16, as explained above. 
     B. In the present invention (see: FIGS. 5, 6) 
     Two decision level voltages: -V R  /8, V R  /8 ##EQU15## 
     Accordingly, the generated digits are obtained as follows. 
     Generated digits: 1 0 -1 1 
     Plus/minus code conversions of this data are performed as follows. ##EQU16## 
     This data is correct. 
     As explained above, regardless of fluctuations of the decision level voltage, the conversion can be correctly performed. 
     Referring to FIGS. 7A to 7D, each circuit comprises an operational amplifier OP, three capacitors C0 to C2 and four switches S1 to S4. The differences between these figures lie in the connections of the switches S1 to S4. Each of the capacitors C0 to C2 has an approximately equal capacitance. The circuit shown in FIG. 7A is used as the sampling operation of the input voltage V i . The circuits shown in FIGS. 7B to 7D and used as the conversion from the input voltage to the output voltage. By changing the connections of these switches, the following output voltages V o  can be obtained in the output terminal OT. that is, 
     
         V.sub.o =2V.sub.i -V.sub.R                                 (1) 
    
     
         V.sub.o =2V.sub.i                                          (2) 
    
     
         V.sub.o =2V.sub.i +V.sub.R                                 (3) 
    
     A. In FIG. 7A, the sampling of the input voltage V i  is performed as follows. 
     switch S1: ON 
     switch S2: to V i   
     switch S3: to V i   
     switch S4: to V R   
     capacitor C0: charged by V R   
     capacitor C1: charged by V i   
     capacitor C2: charged by V i   
     B. In FIG. 7B, the conversion of &#34;-V R  &#34; is performed as follows. 
     switch S1: OFF 
     switch S2: to terminal OT 
     switch S3: to V R   
     switch S4: to V R   
     capacitor C0: charged by V R   
     capacitor C1: charged by V R   
     capacitor C2: charged by 2V i  -V R   
     In this case, the electric charge quantity of the capacitor C2 is given by 2V i  -V R , based on &#34;the principle of conservation of the electric charge&#34;. That is, although the electric charge quantity of the capacitor C0 is not charged, that of the capacitor C1 is changed to V R . Accordingly, the charge quantity V i  -V R  in the capacitor C1 is migrated to the capacitor C2, based on the above &#34;principle&#34;. Therefore, the electric charge quantity of the capacitor C2 is given by, 
     
         V.sub.i +V.sub.i -V.sub.R =2V.sub.i -V.sub.R 
    
     In this case, although each electric charge quantity is given by multiplying the capacitance by the voltage, i.e., C×V, these capacitances are omitted in the descriptions since the capacitances of each of the capacitors C0, C1 and C2 are equal. 
     C. In FIG. 7C, the conversion of &#34;0&#34; is performed as follows. 
     switch S1: OFF 
     switch S2: to terminal OT 
     switch S3: to ground 
     switch S4: to V R   
     capacitor C0: charged by V R   
     capacitor C1: to ground 
     capacitor C2: charged by 2V i   
     In this case, the electric charged quantity of the capacitor C2 is given by 2V i , based on the above &#34;principle&#34;. That is, although the charge quantity of the capacitor C0 is held, that of the capacitor C1 is migrated to the capacitor C2, based on the above &#34;principle&#34;. Therefore, the electric charged quantity of C2 is given by, 
     
         V.sub.i +V.sub.i =2V.sub.i 
    
     D. In FIG. 7D, the conversion of &#34;+V R  &#34; is performed as follows. 
     switch S1: OFF 
     switch S2: to terminal OT 
     switch S3: to ground 
     switch S4: to ground 
     capacitor C0: to ground 
     capacitor C1: to ground 
     capacitor C2: charged by 2V i  +V R   
     In this case, as explained above, the electric charge quantities of the capacitors C0 and C1 and migrated to the capacitor C2. Accordingly, the electric charge quantity of the capacitor C2 is given by, 
     
         V.sub.i +V.sub.i +V.sub.R =2V.sub.i +V.sub.R 
    
     As explained in items B to D, three kinds of output voltages V o  can be obtained by changing the connections of the switches S3 and S4. The feature of the present invention lies in the control of the switches S3 and S4. 
     Referring to FIG. 8, two of the circuits shown in FIGS. 7A to 7D are used as the voltage conversion block. That is, reference number 11a is the same as circuit 11b, AlN is an analog input signal, and CLK1 and CLK2 are clock signals. These signals are input from an external circuit (not shown). Switches SA and SB are input changing switches, S1A to S7A and S1B to S7B are also circuit changing switches, and S8A and S8B are mode changing switches. C0A to C2A and C0B to C2B are capacitors for conversion, and OPA and OPB are operational amplifiers. These elements correspond to those of FIGS. 7A to 7D. That is, switches S8A and S8B correspond to the switch S1; S1A, S2A and S1B, S2B correspond to the switch S2; S3A to S5A and S3B to S5B correspond to the switch S3, and S6A; S7A and S6B, S7B correspond to the switch S4. 
     Reference letters CPR1 and CPR2 are comparators, SR1 and SR2 are shift registers for series-to-parallel conversion and plus/minus code conversion, and CT is an adder. F1 and F2 are flip-flop circuits for latching output from the comparators, and SGT is a gate circuit constituted by AND gates A and NOR gates N. The switches shown in the circuit 11a and 11b are controlled by the outputs of these AND gates and NOR gates. When the output is high level, the corresponding switch is turned ON, and when the output is low level, the corresponding switch is turned OFF. 
     The operation of these circuits will be explained in detail with reference to FIG. 9. 
     In FIG. 9, section (A) represents waveforms of the clock signals CLK1 and CLK2 and the ON/OFF timing of the switches SA and SB. Section (B) represents the status of each switch and various signals. Reference numbers 1 to 4 in section (B) represent operation steps of the circuit shown in FIG. 8. Asterisks in the chart represent a value determined by depending on an input voltage AlN. 
     In step 1; 
     The connection configurations of the switches S1A to S8A are the same as that of FIG. 7A. That is, in this step, an input analog voltage AlN is taken into the circuit 11a through the switch SA. Accordingly, the sampling operation of the input analog voltage can be performed by this step. In this state, the capacitor C0A is charged by the reference voltage V R , and the capacitors C1A and C2A are charged by the input voltage AlN (the same as V i  mentioned before). Since the switch S2A is turned ON, the input voltage AlN is input to the comparators CPR1 and CPR2 as the voltage V CMP . The voltage V CMP  is compared with the decision level voltages +V R  /4 (in the comparator CPR1) and -V R  /4 (in the comparator CPR2). 
     Assuming that the input voltage AlN is 3/8 (V), this voltage is larger than both decision level voltages +1/4 (V) and -1/4 (V) (in this case, the reference voltage V R  is 1 (V). Accordingly, the comparator outputs CP and CN are high (H) level. The asterisks attached to both &#34;H&#34; levels of the CP and CN mean that these levels are decided when the input voltage is 3/8 (V). 
     In Step 2; 
     The circuit 11a corresponds to FIG. 7B, and the circuit 11b corresponds to FIG. 7A in this step. When the switches S1A to S8A and S1B to S8B are connected as shown in the chart, the comparator output voltages CP and CN are output to the shift registers SR1, SR2 and the flip-flop circuits F1, F2. In this case, the output CP is input to the shift register SR1 and the flip-flop F1, and the output CN is input to the shift register SR2 and the flip-flop F2. The clock signal CLK2 is &#34;H&#34; level, and accordingly, the switches S2B, S3B, S8B and S1A are turned ON. Moreover, the clock signal CLK2 is input to each of the AND gates and NOR gates, then each of the switches is turned ON/OFF in correspondence with the &#34;H&#34; or &#34;L&#34; level of the gate output. 
     Accordingly, in this circuit 11a, the output voltage V 0A  of the operational amplifier OPA is obtained based on the formula V o  =2V i  -V R  as follows. 
     
         V.sub.0A =2×3/8-1=-1/4 (V) 
    
     where, AlN (V i )=3/8 (V) 
     In the circuit 11b, the capacitor C0B is charged up by the reference voltage V R , and the capacitors C1B and C2B are charged up by the output voltage V 0A  (-1/4 V) of the operational amplifier OPA. The output voltage V 0A  is input to both the comparators CPR1 and CPR2 as the input voltage V CMP  through the switch S1A. 
     The voltage V CMP  is compared with the decision level voltages +V R  /4 and -V R  /4. Since the reference voltage V R  is 1 V, the decision level voltage become +1/4 and -1/4 (V). Therefore, 
     
         +1/4&gt;V.sub.CMP =-1/4≧-1/4 
    
     Accordingly, the output voltage CP is &#34;L&#34; level and the output voltage CN is &#34;H&#34; level. In this case, since the input voltage V i  =3/8 (V), the generated digit is given by &#34;1&#34;. 
     In step 3; 
     The circuit 11a corresponds to FIG. 7A and the circuit 11b corresponds to FIG. 7C. When the switches S1A to S8A and S1B to S8B are connected as shown in the chart, the output voltages CP and CN which are obtained in step 2 are taken in to the shift registers SR1, SR2 and the flip-flops F1, F2, and processed as new voltages DP and DN. 
     In the circuit 11b, the output voltage V 0B  of the operational amplifier OPB is given as follows, based on the formula V o  =2V i . 
     
         V.sub.0B =2×(-1/4)=-1/2(V) 
    
     where, V i  (-1/4) is given by the previous output voltage V 0A  in step 2. The voltage V 0B  (=V CMP ) is compared with the decision level voltages +1/4 and -1/4. As is obvious, both output voltages CP and CN become &#34;L&#34; level. Since the previous input voltage V i  is -1/4 (V), the generated digit is given by &#34;0&#34;. 
     In step 4; 
     The circuit 11a corresponds to FIG. 7D and the circuit 11b corresponds to FIG. 7A. When the switches S1A to S8A and S1B and S8B are connected as shown in the chart, the output voltages CP and CN, which are obtained in step 3, are taken in to the shift registers SR1, SR2 and the flip-flops F1, F2, and processed as new voltages DP and DN. 
     In the circuit 11a, the output voltage V 0A  of the operational amplifier OPA is given as follows, based on the formula V o  =2V i  +V R . 
     
         V.sub.0A =2×(-1/2)+1=0 (V) 
    
     where, V i  (-1/2) is given by the previous output voltage V 0B  in step 3. The voltage V 0A  (=V CMP ) is compared with the decision level voltages. As a result, 
     
         1/4&gt;0&gt;-11/4 
    
     Then, the output voltage CP is &#34;L&#34; level and the output voltage CN is &#34;H&#34; level. Since the previous input voltage V i  is -1/2 (V), the generated digit is given by &#34;-1&#34;. As is obvious from the next step, the generated digit in step 1 is obtained in the next conversion. That is, since V i  is 0 (V), the generated digit is given by &#34;0&#34;. 
     Consequently, the analog input voltage 3/8 (V) is converted to the digits 1, 0, -1, 0. These digits are divided into two binary numbers by plus/minus code conversion as explained below. 
     Referring to FIG. 10, the generated digits are shown by 1, 0, -1, 0. In the shift register SR1, plus code converted binary numbers 1, 0, 0, 0 are stored, and in the shift register SR2, minus code converted binary numbers 1, 1, 0, 1 are stored. In this case, the 2&#39;s complement binary code 0, 0, 1, 0 are applied to the shift register SR2. This is because both binary numbers stored in the SR1 and SR2 can be only added in the adder CT as explained below. 
     In the shift registers SR1 and SR2, the least significant bit (LSB) is on the right side, and the most significant bit (MSB) is on the left side. These values are added by the adder CT. The operation of the adder is explained in FIGS. 11 and 12. As is obvious from FIG. 10, although the digits stored in the SR1 and SR2 are given by four digits, five digits have occurred due to the carry of the MSB in the shift register SR1 and SR2. Accordingly, the fifth bit (=1) of the MSB is inverted to &#34;0&#34; by using the inverter INV. Consequently, a binary number 0 1 1 0 is obtained from the output of the adder CT as digital codes. This binary number is, of course, equal to the analog number 3/8. 
     Referring to FIGS. 11 and 12, these circuit and function charts are of a well-known adder. This adder is the 4 bits binary full adder MODEL MB74LS283 made by Fujitsu Limited. For example, when the inputs A1, A2 are &#34;H&#34; level and the inputs B1, B2 are &#34;L&#34; level, outputs Σ1, Σ2 are &#34;L&#34; level when an input C0 is &#34;H&#34; level. When inputs A3, B3 are &#34;L&#34; level and inputs A4 and B4 are &#34;H&#34; level, outputs Σ3, Σ4 are &#34;H&#34; and &#34;L&#34; level when an input C0 is &#34;H&#34; level. 
     Referring to FIG. 13, A 1  and A 2  are operational amplifiers. Capacitors C 1 , C 2 , C 3 , and C 4  have equal capacitances and the capacitor C 5  has double the capacitance of the capacitor C 1 . The control section is constituted by two comparators CPR1 and CPR2, two flip-flop circuits Fa and Fb, and gate circuits having two AND gates A and two NOR gates N. In this case, two operational amplifiers A 1  and A 2  and their peripheral circuit, except for the control section, are as in the conventional circuit. As explained below, a &#34;three states control&#34; is also possible by using a combination of the present and the conventional circuits. 
     The operations of this circuit will be explained with reference to FIG. 14. Referring to FIG. 14, the input voltage V IN  is 2.72 (V) and the reference voltage V REF  is 3.14 (V). In this case, the two kinds of decision level voltages are set to V REF  /4 and -V REF  /4. Accordingly, the voltage V x  is compared with these decision level voltages in the comparators OPR1 and OPR2. Three patterns of the outputs V 3  and V 5  of the control circuit are decided as shown in FIG. 15. That is, when the comparators OPR1 and OPR2 are &#34;L&#34; level, the voltage V 3  is changed from &#34;H&#34; level to &#34;L&#34; level and the voltage V 5  is changed from &#34;L&#34; level to &#34;H&#34; level. When the comparator OPR1 is &#34;L&#34; level and the comparator OPR2 is &#34;H&#34; level, the voltage V 3  is &#34;H&#34; level and the voltage V 5  is &#34;L&#34; level. When the comparators OPR1 and OPR2 are &#34;H&#34; level, the voltage V 3  is changed from &#34;L&#34; level to &#34;H&#34; level and the voltage V 5  is changed from &#34;H&#34; level to &#34;L&#34; level. 
     In FIG. 13, after the capacitor C 1  is charged by the input voltage V IN , when the voltage V 5  becomes &#34;H&#34; level, the electric charge of the capacitor C 1  is transferred to the capacitor C 2 . Consequently, the voltage V x  becomes 2.71 (V) and this voltage V x  is compared by the comparators CPR1 and CPR2. Moreover, the capacitor C 3  is also charged by the voltage V x  since the voltage V 2  is &#34;H&#34; level. 
     When the voltage V 1  is &#34;H&#34; level and the voltage V 2  is &#34;L&#34; level, the electric charge of the capacitor C 2  is cleared and the electric charge of the capacitor C 3  is transferred to the capacitor C 4 . Accordingly, the voltage V y  is equal to the voltage V x  mentioned above. since the capacitance of the capacitor C 5  is set to double the capacitance of the capacitor C 1 , a double capacitance of the capacitor C 2  is charged to the capacitor C 5 . Moreover, when the voltage V 5  is &#34;H&#34; level, the capacitor C 1  is connected to the ground based on the positive value of the resultant data of the voltage V x . Next, when the voltage V 1  is &#34;L&#34; level and the voltage V 2  is &#34;H&#34; level, the voltage V 5  is &#34;L&#34; level and the voltage V 3  is &#34;H&#34; level. Moreover, when the electric charge of the capacitor C 5  is transferred to the capacitor C 2 , the electric charge of the capacitor C 1  based on the voltage V R  is subtracted from the capacitor C 2 . 
     After this control, the generated digits are obtained as shown in FIG. 14. These digits are processed by plus/minus code conversion so that a binary number is obtained as shown in FIG. 14. 
     Referring to FIG. 16, these charts represent conversion range and output codes of the A/D and D/A changeable converter constituted by an integrated circuit (IC). Since the resolution rate is 16 bits, 1LSB becomes V R  /2 15 . In FIG. 16, when the analog input voltage V i  is zero volt, the output digital code is given by &#34;0000-0000&#34;. When the analog input voltage V i  is V R  /2 (V R  is reference voltage as explained above), the output digital codes are given by &#34;0100-0000&#34;. When the input voltage V i  is (+V R  -1LSB) or is larger than +V R , the output codes are given by &#34;0111-1111&#34;.