Abstract:
A system and methodology for laser mass customization of integrated circuits including a mask exposure subsystem operative to configure at least one conductive layer forming part of an integrated circuit and a laser customization subsystem operative to individually customize the at least one conductive layer.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to laser customization of integrated circuits generally.  
         BACKGROUND OF THE INVENTION  
         [0002]    The following U.S. patents are considered to represent the current state of the art: U.S. Pat. No.  5,985,518; 5,861,641; 5,818,728; 5,679,967; 5,619,062; 5,565,758; 5,545,904; 5,541,814; 5,260,597; 5,128,601; 5,111,273; 5,049,969); 5,027,027.    
         SUMMARY OF THE INVENTION  
         [0003]    The present invention seeks to provide improved systems and methodologies for laser customization of integrated circuits.  
           [0004]    There is thus provided in accordance with a preferred embodiment of the present invention a methodology for laser mass customization of integrated circuits including:  
           [0005]    providing a substrate;  
           [0006]    forming at least one semiconductor layer over the substrate; and  
           [0007]    forming a plurality of conductive layers over the semiconductor layer, wherein at least one of the plurality of conductive layers is individually customized by employing a laser.  
           [0008]    Preferably, the forming includes:  
           [0009]    defining at least one of the plurality of conductive layers by exposing photoresist to light; and  
           [0010]    individually customizing at least a portion of at least one of the plurality of conductive layers by causing laser light to impinge on the photoresist.  
           [0011]    In accordance with a preferred embodiment of the present invention, the defining and the individually customizing each include exposing an area of the photoresist layer.  
           [0012]    Preferably, an area exposed by the individually customizing is substantially smaller than an area exposed by the defining.  
           [0013]    In accordance with a preferred embodiment of the present invention, the individually customizing has an overall duration which is substantially smaller than the overall duration of the defining.  
           [0014]    Preferably, the individually customizing employs a beam having an intensity which is substantially greater than the intensity of light employed in the defining.  
           [0015]    In accordance with a preferred embodiment of the present invention, exposure by the individually customizing is effected on the fly.  
           [0016]    Preferably, the exposing which provides the individually customizing takes place generally concurrently with the exposing which provides the defining.  
           [0017]    In accordance with a preferred embodiment of the present invention, the substrate includes a silicon wafer including a plurality of integrated circuit dies and wherein each of the plurality of integrated circuit dies is individually customized by employing the laser.  
           [0018]    There is also provided in accoordance with a preferred embodiment of the present invention a system for laser mass customization of integrated circuits including:  
           [0019]    mask exposure subsystem operative to configure at least one conductive layer forming part of an integrated circuit; and  
           [0020]    a laser customization subsystem operative to individually customize the at least one conductive layer.  
           [0021]    Preferably, the mask exposure subsystem and the laser customization subsystem are both operative waferwise on a substrate containing a plurality of integrated circuit dies.  
           [0022]    In accordance, with a preferred embodiment of the present invention, the mask exposure subsystem and the laser customization subsystem operate at at least partially overlapping times on a given conductive layer.  
           [0023]    Preferably, the mask customization subsystem is operative to configure the at least one conductive layer by exposing photoresist to light and the laser customization subsystem is operative to further configure the at least one conductive layer by causing laser light to impinge on the photoresist.  
           [0024]    In accordance with a preferred embodiment of the present invention, the mask customization subsystem employs light having an intensity which is substantially less than the intensity of a beam of light employed by the laser customization subsystem.  
           [0025]    Preferably, the laser customization subsystem is operative on the fly.  
           [0026]    In accordance with a preferred embodiment of the present invention, the laser customization subsystem includes a customization engine providing customization outputs to a laser for making individual customization markings on each of a plurality of integrated circuit dies.  
           [0027]    Preferably, the laser customization subsystem customizes at least one conductive layer. Additionally or alternatively, th, the laser customization subsystem customizes at least one interconnect layer.  
           [0028]    Preferably, the mask customization subsystem employs light having an intensity which is substantially less than the intensity of a beam employed by laser customization subsystem. dr  
         BRIEF DESCRIPTION OF THE DRAWINGS  
         [0029]    The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:  
           [0030]    [0030]FIG. 1 is a simplified pictorial illustration of a system and methodology for laser mass customization of integrated circuits in accordance with a preferred embodiment of the present invention;  
           [0031]    [0031]FIGS. 2A, 2B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H and  2 I are simplified pictorial illustrations illustrating alternative embodiments of laser mass customization of integrated circuits in accordance with preferred embodiments of the present invention; and  
           [0032]    [0032]FIGS. 3A, 3B,  3 C,  3 D,  3 E,  3 F,  3 G,  3 H,  3 I and  3 J are simplified pictorial illustrations illustrating alternative embodiments of laser mass customization of integrated circuits in accordance with preferred embodiments of the present invention.  
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0033]    Reference is now made to FIG. 1, which a simplified pictorial illustration of a system and methodology for laser mass customization of integrated circuits in accordance with a preferred embodiment of the present invention. As seen in FIG. 1, a silicon substrate  10 , including a multiplicity of integrated circuit dies  12  undergoes a photolithography process employing at least one mask  14  and a light source  16  to form an integrated circuit  18  on each die.  
         [0034]    In accordance with a preferred embodiment of the present invention, each integrated circuit is individually customized with one or more individual customization markings  20 . Preferably such individual customization is carried out using a laser  22  and associated laser optics  24  in conjunction with a standard substrate displacement mechanism (not shown), such as an X-Y stepper, used in conventional mask photolithography methodologies, which supports substrate  10 . It is appreciated that the laser optics  24  may employ some or all of the optics employed for the standard photolithography process.  
         [0035]    The laser  22  may be driven by a customization engine  26 , such as a computer, which may generate identification or other customization codes, which are preferably encrypted, for providing unambiguous identification of each integrated circuit.  
         [0036]    It is a particular feature of the present invention that the laser customization may be carried out as part of the standard fabrication process for integrated circuits on a waferwise basis. More specifically, it is a particular feature of the present invention that individual customization is carried out at the same stage that mask exposure is carried out. Both mask exposure and individual customization may be carried out simultaneously.  
         [0037]    Reference is now made to FIGS. 2A, 2B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H &amp;  2 I which are simplified pictorial illustration illustrating various stages in laser mass customization of integrated circuits in accordance with preferred embodiments of the present invention.  
         [0038]    [0038]FIG. 2A illustrates in initial stage wherein a layer  30  of photoresist is formed over a water  32  having semiconductor elements formed thereon. FIG. 2B shows exposure of layer  30  by light from a light source  34  via a mask  36  to form photoresist patterns  38  corresponding to conductive patterns in a die  40  on wafer  32 .  
         [0039]    [0039]FIG. 2C shows laser customization of layer  30  at die  40 , which defines customization markings  42  at each die. Preferably, each die may be distinguished from every other die by the nature and/or location of the customization markings  42  thereon. Following the mask exposure step of FIG. 2B and the laser exposure step of FIG. 2C, the layer  30  may be developed in a conventional manner, as shown in FIG. 2D. It is a particular feature of the invention that the laser customization need not require a separate or additional development step.  
         [0040]    Reference is now made to FIG. 2E, which shows wafer  32  following the development step of FIG. 2D. It is noted that the laser customization step of FIG. 2C results, in the illustrated example, in customized breaks  44  in the photoresist patterns  38  corresponding to customized breaks in the conductive patterns. Thus it may be appreciated that each integrated circuit produced by the methodology described hereinabove may be not only visually distinct from every other integrated circuit but may also be electrically different, such that its identity may be ascertained electrically, as by electrical interconnection with pads thereof.  
         [0041]    Following the conventional development step of FIG. 2D, the wafer  32  is subjected to a conventional etching step shown in FIG. 2F. The results of this conventional etching step are shown in FIG. 2G, where it is seen that conductive pattern  46  are formed corresponding to and underlying photoresist patterns  38  and are formed with customized breaks  48  therein corresponding to the customized breaks  44  in the photoresist patterns  38  (FIG. 2E).  
         [0042]    Following the conventional etching step shown in FIG. 2F, the wafer  32  is subjected to a conventional photoresist removal step shown in FIG. 2H which removes the photoresist patterns  30 , leaving the conductive patterns  46  intact, as seen in FIG. 2I. The customized breaks  48  in conductive patterns  46  enable each die to have a customized identity and/or electrical function.  
         [0043]    Reference is now made to FIGS. 3A, 3B,  3 C,  3 D,  3 E,  3 F,  3 G,  3 H,  3 I and  3 J, which are simplified pictorial illustrations illustrating various stages in laser mass customization of integrated circuits in accordance with another preferred embodiment of the present invention. Briefly stated, the difference between the methodology of FIGS.  2 A- 2 I and that of FIGS.  3 A- 3 J is that the customization in the embodiment of FIGS.  2 A- 2 I is effected in one or more conductive layers, while in the embodiment of FIGS.  3 A- 3 J, the customization is effected in one or more interconnect layer interconnecting conductive layers.  
         [0044]    [0044]FIG. 3A illustrates an initial stage wherein a layer  50  of photoresist is formed on a wafer  52  not only having semiconductor elements formed thereon but also having at least one conductive layer  53  formed thereon over which a non-conductive layer  54  is formed. The photoresist layer  50  is formed over the non-conductive layer  54 . FIG. 3B shows exposure of layer  50  by light from light source  55  via a mask  56  to form photoresist patterns  58  corresponding to vias in a die  60  on wafer  52 .  
         [0045]    [0045]FIG. 3C shows laser customization of layer  50  at die  60 , which defines customization markings  62  at each die. Preferably, each die may be distinguished from every other die by the nature an/or location of the customization marking  62  thereon. In the embodiment of the invention described herein with reference to FIGS.  3 A- 3 J, the customization markings  62  may be vias indistinguishable from conventional via markings  58  produced by the mask exposure of the photoresist layer described with reference to FIG. 3B, other than by their location.  
         [0046]    Following the mask exposure step of FIG. 3B and the laser exposure step of FIG. 3C, the layer  50  may be developed in a conventional manner, as shown in FIG  3 D. It is a particular feature of the invention that the laser customization need not require a separate or additional development step.  
         [0047]    Reference is now made to FIG. 3E, which shows wafer  52  following the development step of FIG. 3D. It is noted that the laser customization step of FIG. 3C results, in the illustrated example, in customized via holes  64  in the photoresist layer  50  corresponding to customized vias in the interconnect layer, while the mask exposure of FIG. 3B results, in conventional via holes  65  in the photoresist layer  50 .  
         [0048]    Thus it may be appreciated that, similarly to the embodiment of FIGS.  2 A- 2 I, each integrated circuit produced by the methodology described hereinabove may be not only visually distinct from every other integrated circuit but may also be electrically different, such that its identity may be ascertained electrically, as by electrical interconnection with pads thereof.  
         [0049]    Following the conventional development step of FIG. 3D, the wafer  52  is subjected to a conventional etching step shown in FIG. 3F. The results of this conventional etching step are shown in FIG. 3G, where it is seen that via holes  64  and  65  are formed in non-conductive layer  54  in registration with the respective patterns  65  and  64 , produced by the mask exposure stage of FIG. 3B and by the laser customization stage of FIG. 3C.  
         [0050]    Following the conventional etching step shown in FIG. 3F, the wafer  52  is subjected to a conventional photoresist removal step shown in FIG. 3H which removes the photoresist layer  50 , leaving the customized via holes  64  as well as via holes  65  defined by the mask exposure stage of FIG. 3B intact, as seen in FIG. 3I.  
         [0051]    [0051]FIG. 3J illustrates a further step wherein a conductive layer  66  is formed over the non-conductive layer  54 , by any suitable technique, such as sputtering. This step fills in the via holes  64  and  65 , thus defining corresponding vias  70  and  72  in an interconnect layer  74 , interconnecting conductive patterns in layers  53  and  66 . It is understood that conductive layer  66  may be suitably patterned as by conventional photolithographic techniques.  
         [0052]    The resulting interconnect layer  74  is thus seen to contain inter alia customized vias  70  and  72 , in at least one interconnect layer, which enable each die to have a customized identity and/or electrical function.  
         [0053]    It is appreciated that either or both of the functionalities of FIGS.  2 A- 2 I and  3 A- 3 J may be applied to one or more metal layer of a given wafer.  
         [0054]    It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of tho various features described hereinabove as well as variations and modifications which would occur to persons skilled in the art upon reading the specification and which are not in the prior art.