Abstract:
An embodiment of the present inventions is a method for encoding/decoding data of variable length format and is used to omit unnecessary pieces of data for the purpose of improving processing performance, reducing the size of data on communication paths and efficiently using limited physical memory. As examples of such variable length encoding, BER compression and UTF-8 encoding of UNICODE text, etc., are cited. While the amount of data can be reduced through encoding, before the data is actually used, it is necessary to restore (decode) it to the original data, which requires a great deal of processing time. One aspect of the present invention is improving decoding by reducing the processing time required to decode the encoded data.

Description:
TRADEMARKS 
       [0001]    IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to a method for encoding/decoding data of a variable length format and in particular to using the method to omit unnecessary pieces of data for the purpose of improved processing performance, reducing the size of data on communication paths, and efficiently using limited physical memory. 
         [0004]    2. Description of Background 
         [0005]    Before our invention encoding data is commonly utilized as a way in which to compress and reduce the physical size of the data while maintaining the data integrity. As such, a variety of encoding and decoding algorithms are available and many have been optimized for particular types and or kinds of data. 
         [0006]    A problem with current encoding schemes is that data is encoded with no consideration given to efficiently encoding the data such that decode processing time is minimized. In this regard, existing decoding/encoding programs are inefficient and require lots of processing time to decode the data. 
         [0007]    As such, current encoding and decoding routines are inefficient, and typically process unnecessary data. All of which consumes valuable processing time, and increases the size of data on communication paths. As such, eliminating unnecessary data by way of an improved encoding and decoding method resulting in a method of speeding up decoding processing time significantly improves processing performance and in part gives rise to the present invention. 
       SUMMARY OF THE INVENTION 
       [0008]    The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method of simultaneous processing data elements in decoding operation of variable length encoded data, said method comprising: collecting a plurality of data to be decoded; determining an encoded data length for each of the plurality of data; obtaining a plurality of parameters based on the determination of the encoded data length of each of the plurality of data; and performing operations on each of the plurality of data. 
         [0009]    System and computer program products corresponding to the above-summarized methods are also described and claimed herein. 
         [0010]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
       TECHNICAL EFFECTS 
       [0011]    As a result of the summarized invention, technically we have achieved a solution, which is a method of speeding up the decoding of encoded data. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0013]      FIG. 1  illustrates one example of a program restoration processing; 
           [0014]      FIG. 2  illustrates one example of permute instruction of VMX; 
           [0015]      FIG. 3  illustrates one example of a method of simultaneous processing of a plurality of elements in decoding operations of variable length encoding data routine  1000 ; 
           [0016]      FIG. 4  illustrates one example of a program for restoration processing by way of routine  1000 ; 
           [0017]      FIG. 5  illustrates one example of a decoding operation; 
           [0018]      FIG. 6  illustrates one example of obtaining parameters and performing operations of routine  1000  specific to BER compression decoding; 
           [0019]      FIG. 7  illustrates one example of obtaining parameters and performing operations of routine  1000  specific to UTF-8 decoding; 
           [0020]      FIG. 8  illustrates one example of the performance of decoding of simple encoding of Table 1; 
           [0021]      FIG. 9  illustrates one example of the performance of decoding of BER compression; and 
           [0022]      FIG. 10  illustrates one example of the performance of UTF-8 decoding. 
       
    
    
       [0023]    The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    Turning now to the drawings in greater detail, in an exemplary embodiment of the present invention a method of variable length encoding/decoding of a plurality of data simultaneously is utilized to reduce the number of conditional branching instructions and arithmetic instructions, which cause a lowering of execution efficiency, and as such a realization of higher speed processing, mainly through a permute instruction. 
         [0025]    To explain the decoding of variable length encoding, an example of simplified encoding rule is shown in Table 1 below. In the encoding, integer type data of up to 30 bits in length is expressed by a data format of 1 to 4 bytes, with a 2-bit prefix being added. 
         [0000]    
       
         
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Encoded 
                   
                 Format 
               
               
                 Input data 
                 data 
                 2-bit 
                 [first byte] [second byte] . . . X: 
               
               
                 length 
                 length 
                 prefix 
                 data bit 
               
               
                   
               
             
             
               
                  1 to 6 bits 
                 1 byte     
                 0 (00b) 
                 [00xxxxxx] 
               
               
                  7 to 14 bits 
                 2 bytes 
                 1 (01b) 
                 [01xxxxxx] [xxxxxxxx] 
               
               
                 15 to 22 bits 
                 3 bytes 
                 2 (10b) 
                 [10xxxxxx] [xxxxxxxx] [xxxxxxxx] 
               
               
                 23 to 30 bits 
                 4 bytes 
                 3 (11b) 
                 [11xxxxxx] [xxxxxxxx] [xxxxxxxx] 
               
               
                   
                   
                   
                 [xxxxxxxx] 
               
               
                   
               
             
          
         
       
     
         [0026]    In the encoding, if the ratio of data having a short input data length is higher, the amount of data will be reduced. One example of a program for performing restoration of the encoded data according to this rule is illustrated in  FIG. 1 . 
         [0027]    As illustrated in  FIG. 1 , since the restoration operation of the variable length data generally includes a number of conditional branches and the decoding of each element concurrently depends on the decoding of the previous element, there is the problem that the parallelism of the instruction level is lowered. 
         [0028]    As a premise of the present invention, an explanation will be given regarding the permute instruction (as example see IBM Corp. PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual). A permute (or shuffle) instruction is an instruction for rearranging the content of the input register in an arbitrary order. To give an example of the permute instruction of the VMX, which is an SIMD instruction set of the PowerPC, three 16-byte vector registers are treated as input, one vector register as output, and the data of the vector register as sixteen 1-byte rows, respectively. In this instruction, the first and second arguments are first of all combined in this order to make thirty-two 1-byte rows. Based on this, the byte value at the position indicated by the location of the value of the lower 5 bits of each element of the third argument is returned as a return value of the position corresponding to the element. Thus, it becomes possible to rearrange the input data in units of bytes in an arbitrary order. An example of the operation of the permute instruction of the VMX one example of which is illustrate in  FIG. 2 . 
         [0029]    Explanations will be given regarding the method of the present invention, using the format shown above in the table as an example. That is to say, an arrangement expressed by variable length encoding of 1 to 4 bytes is decoded in order to be output as an arrangement of a 32-bit integer. According to the method of the present invention, a plurality of data is processed simultaneously. However, explanations will be given on the basis of 4 pieces of data being processed simultaneously. This corresponds to a case where, by using a register of 16-byte length, a 32-bit integer is processed. However, the present method is not limited to this parallelism; 8 pieces of data (8 characters) will be decoded simultaneously in the decoding of the UTF-8 to be described later. Furthermore, the present invention is mainly intended for the decoding of encoded data, however, the object is not limited to this use. For example, it is possible apply it in encoding, using the rules illustrated in the table above. 
         [0030]    Referring to  FIG. 3  there is illustrated one example of a method of simultaneous processing of a plurality of elements in decoding operations of variable length encoding data routine  1000 . In an exemplary embodiment, the present method collects the data length of the plurality of data to be processed, obtains the necessary parameters by looking up a table or performing operations, and performs operations using the obtained parameters, simultaneously processing the plurality of data. The method begins in block  1002 . 
         [0031]    In block  1002  the data length of the plurality of data to be processed is collected. Processing then moves to block  1004 . 
         [0032]    In block  1004  the parameters by looking up a table or performing operations is obtained. In this regard,  FIGS. 6 and 7  further illustrate the process of obtaining in block  1004  and performing in block  1006 . Processing then moves to block  1006 . 
         [0033]    In block  1006  operations using the obtained parameters are performed simultaneously processing the plurality of data. The routine in then exited. 
         [0034]    Referring to  FIG. 4  there is illustrated one example of such processing. In the example in  FIG. 4 , the prefixes of 4 pieces of input data are collected (functionality of block  1004 ). Two parameters are loaded, which are vpattern for rearranging data through the permute instruction and vmask for masking prefix bits (functionality of block  1004 ). After the encoded data is loaded, processing is actually performed by using two parameters (functionality of block  1006 ). 
         [0035]    Here, if the prefix of the 4 pieces of input data is, for example, in an order of [0, 1, 2, 1], a constant number table is prepared, in order for the values of the two parameters to become as follows. 
         [0000]        v pattern={*, *, *, 0×00, *, *, 0×01 , 0×02, *, 0×03, 0×04, 0×05, *, *, 0×06, 0×07} 
         [0000]        v mask={0, 0, 0, 0×3 F,  0, 0, 0×3 F,  0× FF,  0, 0×3 F,  0× FF,  0× FF,  0, 0, 0×3 F,  0× FF }   
         [0036]    Additionally, ‘*’ denotes an arbitrary value. One example of processing in this case is illustrated in  FIG. 5 . Advantages of this program are, as compared with the code of  FIG. 1  that four pieces of data can be processed at one time and, since conditional branching is not used, there are no penalties from branching mis-predictions. Furthermore, the processing of block  1002  does not depend on that of block  1004  and block  1006  in the previous iteration; therefore, it can be executed in parallel, having the parallelism of a high instruction level, as compared to the code in  FIG. 1 . In addition, in  FIG. 4 , for the purpose of explanation, block  1002  functionality is described through scalar instructions; however, this part can be processed through SIMD instructions as well. 
         [0037]    Conversely, the problem is that a table lookup in block  1004  functionality or operation costs become necessary. In an exemplary embodiment, referred to as embodiment 1 in  FIG. 6 , using the program in  FIG. 4  can perform decoding of the simple encoding of the Table 1 shown above. 
         [0038]    In another exemplary embodiment, referred to as embodiment 2 in  FIG. 6 , decoding of BER (Basic Encoding Rules) compression can be effectuated. In this regard, a variable length encoding format that is included in ITU-T recommendation X.690 (ITU-T Recommendation X.690, Information technology—ASN.1 encoding rules: Specification of Basic Encoding Rules (BER), Canonical Encoding Rules (CER) and Distinguished Encoding Rules (DER)), and it is widely employed not only in the communication field but also in various fields of application. BER compression is variable length encoding, which shows that in 1 byte of data, the first bit is a flag and the remaining 7 bits are data, and when the flag bit is 1, the byte continues to the following byte. While this encoding rule is more complicated it is possible to perform processing in nearly the same fashion as decoding in embodiment 1. 
         [0039]    Referring to  FIG. 6  there is illustrated logic for making some decisions and applying rules. An example is illustrated in  FIG. 6 , which can be implemented by the VMX. In  FIG. 6 , the Select is the select instruction of the VMX, using the value of the register as a mask, which is the third argument, and it is the instruction to output the corresponding bit of the first argument when the mask bit is ‘0’ and to output the corresponding bit of the second argument when the mask bit is ‘1’. 
         [0040]    Referring to  FIG. 7  there is illustrated one example of example of Steps 2 and 3 of UTF-8 decoding. In an exemplary embodiment, referred to as embodiment 3 in  FIG. 7 , a more complicated example is shown that decodes text of the UTF-8 encoded UNICODE (UCS-2). In the decoding of UTF-8, data transfer has to be conducted by bit as well. In UTF-8, when expressing the character code of UCS-2, it is encoded into any one of three kinds of encoding; one byte (ASCII character, 0×00-0×7F), two bytes (Latin character, etc., 0×80-0×7FF), or three bytes (Japanese, etc., 0×800-0×FFFF). As an example, when it is encoded into three-byte length data, three-byte UTF-8 data of [1110xxxx], [10yyyyyy], and [10zzzzzz] has to be transformed into two-byte UNICODE characters of [xxxxyyyy] and [yyzzzzzz], which cannot be realized through sorting only in units of bytes. 
         [0041]    Even in such a case, although the number of parameters and operations to be performed may increase, routine  1000  of the present invention is applicable. Various alternative methods are conceivable for performing operations; however, as an example, the VMX can perform operations as shown in  FIG. 7 . An instruction set having more flexible instructions, such as the permute instruction in units of bits can perform more efficient operations. 
         [0042]    Routine  1000  of the present invention has been implemented and evaluated. The results of performance evaluations of Embodiments 1 and 2, conducted on the PowerPC970 and the SPE of the Cell BE processor, are illustrated in  FIGS. 8 and 9 . In either example, great improvements in performance are obtained by using the present invention in each design. 
         [0043]    The performance of decoding the UTF-8 of embodiment 2, implemented on the PowerPC970, is shown in  FIG. 10 . The label of the x-axis is the type of document, input size (KB)→output size (KB). The three on the left, among the input data used in the test, are artificial data, and they are input in the form of all 1-byte characters (ASCII text), all 3 byte characters (Japanese text), and repetitions of 1, 2, and 3 bytes. Others are text files in real world (mainly HTML), in which the characters to be encoded into all 1-byte characters and into 2 or 3 bytes are intermingled. The graph shown is the relative performance of the implementation compared to a tuned implementation without the method of the present invention. When using the method of the present invention, higher performance is obtained for all documents. 
         [0044]    The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof. 
         [0045]    As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately. 
         [0046]    Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided. 
         [0047]    The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0048]    While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.