Abstract:
BUR920020148US13 A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to the field of integrated circuits; more specifically, it relates to an integrated circuit with performance characteristics that are tunable based on drain current at saturation (I DSAT ) measurements of representative field effect transistors (FET).  
         [0003]     2. Background of the Invention  
         [0004]     When integrated circuits are fabricated the physical properties of FETs on every integrated circuit chip on a wafer or even every FET on a single integrated circuit chip can vary enough from process nominal to produce varying electrical parametrics and thus cause variation from nominal in performance characteristics of integrated circuits. Such variation can lead to yield loss, especially if a particular chips parametric and performance specifications are tight.  
       SUMMARY OF INVENTION  
       [0005]     A first aspect of the present invention is a method of tuning an integrated circuit on an integrated circuit chip comprising: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.  
         [0006]     A second aspect of the present invention is an electronic device comprising: a drain current at saturation measurement circuit; a corresponding bank of fuses; and means for tuning an output of an integrated circuit to be tuned based upon drain current at saturation measurements encoded in a pattern of blown and un-blown fuses in the fuse bank.  
         [0007]     A third aspect of the present invention is a method of tuning an integrated circuit on an integrated circuit chip comprising: providing a drain current at saturation measurement circuit on the integrated circuit chip; providing a corresponding bank of fuses on the integrated circuit chip; and tuning an output of the integrated circuit based upon the drain current at saturation measurements made using the drain current at saturation measurement circuit encoded in a pattern of blown and un-blown fuses in the fuse bank. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0008]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0009]      FIG. 1  is schematic diagram of a set of an I DSAT  measurement circuit according to the present invention;  
         [0010]      FIG. 2A  is plan view of an integrated circuit chip, illustrating placement of I DSAT  measurement circuits according to a first embodiment of the present invention;  
         [0011]      FIG. 2B  is plan view of an integrated circuit chip, illustrating placement of I DSAT  measurement circuits according to a second embodiment of the present invention;  
         [0012]      FIG. 3  is a block diagram illustrating generation of fuse blow data based on I DSAT  measurements according to the present invention;  
         [0013]      FIG. 4  is an exemplary fuse blow pattern lookup table according to the present invention.  
         [0014]      FIG. 5  is an exemplary fuse bank circuit for encoding on chip I DSAT  measurements according to the present invention;  
         [0015]      FIGS. 6A and 6B  illustrate respectively, an exemplary tunable off chip driver (OCD) circuit and lookup table according to the present invention;  
         [0016]      FIGS. 7A  is a timing diagram illustrating the relationship between noise and speed (dl/dt) of an OCD;  
         [0017]      FIG. 7B  is a schematic diagram of an exemplary time rate of change of current (dl/dt) tunable OCD circuit according to the present invention;  
         [0018]      FIG. 8A  is a schematic diagram of a related art data-generating circuit;  
         [0019]      FIG. 8B  is a timing diagram of the circuit of  FIG. 8A ;  
         [0020]      FIG. 8C  is a schematic diagram of an exemplary data-generating circuit with a tunable data window circuit according to the present invention  
         [0021]      FIG. 9A  is a timing diagram for a random access memory (RAM) core; and  
         [0022]      FIG. 9B  is an exemplary tunable circuit for controlling turn-on of sense amplifiers of the RAM core of  FIG. 9A  according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0023]     The current through the drain of a FET saturates or reaches a maximum value versus the voltage applied to the drain VD of a FET as a function of the voltages applied to the gate and V G  and the threshold voltage V T  of device of the FET. It is caused by pinch-off of the channel in the vicinity of the gate. Equation ( 1 ) defines I DSAT :I DSAT =(Zμ- n C i /2L)(V G -V T )2(1)where: Z=channel width; μ n =mobility of majority carrier; Ci=gate capacitance per unit area; L=channel length; V G =voltage on the gate; and V D =voltage on the drain.  
         [0024]     There are three attributes of FETs that can cause changes in I DSAT  measurements. The first is L EFF  (the effective length of the channel), which, is generally caused by photolithography. Across chip linewidth variation (ACLV) or across wafer linewidth variation (AWCV) can cause substantial L EFF  variations. The second is V T  (the threshold voltage of FETs), which is generally caused by source/drain dopant variations. The third is t OX  (the electrical thickness of the gate dielectric of FETs), which, is primarily related to physical thickness, dielectric constant and structure of the gate dielectric  FIG. 1  is schematic diagram of a set of an I DSAT  measurement circuit according to the present invention. In  FIG. 1 , an integrated circuit chip  100  includes a multiplicity of I DSAT  measurement circuits  105 A to  105 N. I DSAT  measurement circuit  105 A includes a set of P-channel field effect transistor (PFET)s P 1 A, P 2 A, P 3 A, P 4 A and P 5 A and a set of N-channel field effect transistor (NFET)s N 1 A, N 2 A, N 3 A, N 4 A and NSA, a PFET enable logic  110 A and an NFET enable logic  115 A. The drains of PFETs P 1 A, P 2 A, P 3 A, P 4 A and P 5 A and NFETs N 1 A, N 2 A, N 3 A, N 4 A and NSA are coupled to an input/output (I/O) pad  120 A. The sources of PFETs P 1 A, P 2 A, P 3 A, P 4 A and P 5 A are coupled to VDD and the sources of NFETS N 1 A, N 2 A, N 3 A, N 4 A and N 5 A are coupled to ground. The gates of PFETs P 1 A, P 2 A, P 3 A, P 4 A and P 5 A are coupled to PFET enable logic  110 A and the gates of NFETS N 1 A, N 2 A, N 3 A, N 4 A and N 5 A are coupled to NFET enable logic  115 A. PFET enable logic  110 A is responsive to a select signal on bus  125 A generated by a select circuit  130 . NFET enable logic  115 A is responsive to a select signal on bus  135 A generated by select circuit  130 . Select circuit  130  is responsive to control signals sent on bus  140  and generated by an off-chip tester  145 .  
         [0025]     In the present example, there are five test PFET devices and five test NFET devices in each I DSAT  measurement circuit  105 A to  105 N. There may be less than five or more than five PFETs and PFETS, the number being a function of the different types of NFETs and PFETs used by critical circuits on integrated circuit chip that are to be tuned. For example, PFETs P 1 A to P 1 N and NFETs N 1 A to N 1 N may be nominal devices (nominal devices are PFETs and NFETs having nominal technology groundrules for threshold voltage, gate length and gate dielectric thickness), PFETs P 2 A to P 2 N and NFETs N 2 A to N 2 N may be long or short channel length devices, PFETs P 3 A to P 3 N and NFETs N 3 A to N 3 N may be high threshold or low threshold voltage devices, PFETs P 4 A to P 4 N and NFETs N 4 A to N 4 N may be thick or thin gate oxide devices and PFETs P 5 A to P 5 N and NFETs N 5 A to N 5 N may be devices of a combination of nominal, high or low threshold voltage, nominal short or long channel devices and nominal, thin or thick oxide gate devices. The devices are selected to match the devices in the circuit to be tuned.  
         [0026]     Note, not all I DSAT  measurement circuits  105 A to  105 N need have the same number of devices, the same mix of device types, or even the same number of test PFETs and test NFETS since the PFET enable logic  110 A to  110 N and the NFET enable logic  115 A to  115 N can be custom designed based on the type and mix of test NFETs and test PFETs in each I DSAT  measurement circuit.  
         [0027]     In the example of  FIG. 1 , I DSAT  measurement circuit  105 N is similar to I DSAT  measurement circuit  105 A, PFETS P 1 N, P 2 N, P 3 N, P 4 N and P 5 N corresponding to PFETS P 1 A, P 2 A, P 3 A, P 4 A and P 5 A and NFETS N 1 N, N 2 N, N 3 N, N 4 N and N 5 N corresponding to NFETS N 1 A, N 2 A, N 3 A, N 4 A and N 5 A. PFET enable logic  110 N and NFET enable logic  115 N have respective corresponding functions to PFET enable logic  110 A and NFET enable logic  115 A.  
         [0028]     Since I DSAT  measurement circuits  105 A to  105 N are similar, only the operation of I DSAT  measurement circuit  105 A will be described in detail. In operation, a select signal is sent to PFET enable logic  110 A from select circuit  130 . PFET enable logic  110 A connects the gate of the “selected” test PFET (one of PFETs P 1 A, P 2 A, P 3 A, P 4 A or P 5 A) to of one of voltage sources V 1  to Vn. The gates of the “unselected” PFETs are coupled to VDD. An I DSAT  measurement of the “selected” PFET can now be made. The I DSAT  measurement is described infra in reference to  FIG. 3 . In turn, each of the previously “unselected” test PFETs is “selected” and I DSAT  of the “selected” test PFET measured.  
         [0029]     Similarly for the test NFETs, a select signal is sent to NFET enable logic  115 A from select circuit  130 . NFET enable logic  115 A connects the gate of the “selected” test NFET (one of NFETs N 1 A, N 2 A, N 3 A, N 4 A or N 5 A) to of one of voltage sources V 1  to Vn. The gates of the “unselected” NFETs are coupled to ground. An I DSAT  measurement of the “selected” NFET can now be made. In turn, each of the previously “unselected” test NFETs is “selected: and I DSAT  of the “selected” test NFET measured. In an I DSAT  measurement of a PFET the I/O pad is forced to GND and the current flow between VDD and the I/O pad is measured. In an I DSAT  measurement of an NFET the I/O pad is forced to VDD and the current flow between GND and the I/O pad is measured.  
         [0030]     Several voltage sources V 1  to Vn are provided because different test PFETs and test NFETs may require different gate voltages and/or to enable testing of the same test PFET or test NFET at several different voltages. These options are either “hardwired” into PFET enable logic  110 A and NFET enable logic  115 A or PFET enable logic  110 A and NFET enable logic  115 A themselves may be programmable, responsive to additional control signals (not shown in  FIG. 1 ) from select circuit  130 . Select circuit  130  optionally may be responsive to Joint Test Action Group (TAG) modes (part of IEEE standard 1149.1) sent by tester  145  via control signal bus  140 .  
         [0031]     Depending upon the channel capacity of tester  145 , all I DSAT  measurement circuits  105 A to  105 N may be measured simultaneously or sequentially. It is possible to have multiple I/O pads  120 A, each coupled to subsets of test NFETs and PFETs. Also, I/O pads  120 A to  120 N may be shared (switchable) with other integrated chip I/O functions, though the impedance of a switching network could distort the I DSAT  measurement.  
         [0032]      FIG. 2A  is plan view of an integrated circuit chip, illustrating placement of I DSAT  measurement circuits according to a first embodiment of the present invention. In  FIG. 2A , four I DSAT  measurement circuits  105 A,  105 B,  105 C and  105 D are placed in proximity to four corners  150 A,  150 B,  150 C and  150 D respectively of integrated circuit chip  100 A. This placement is especially useful for picking up changes in PFET and NFET parametrics caused by ACLV. I DSAT  measurement circuits  105 A,  105 B,  105 C and  105 D are also placed close to I/O pads  120 A,  120 B,  120 C and  120 D respectively, in order to minimize impedance in wires  155 A,  155 B,  155 C and  155 D between the I DSAT  measurement circuits and the I/O pads effecting the I DSAT  measurements themselves. A peripheral pad layout is illustrated in  FIG. 2A  for clarity, however the present invention is applicable to any arrangement of pads  FIG. 2B  is plan view of an integrated circuit chip, illustrating placement of I DSAT  measurement circuits according to a second embodiment of the present invention. In  FIG. 2B , two I DSAT  measurement circuits  105 A and  105 B are placed in within (or in proximity) to two cores  160 A and  160 B respectively of integrated circuit chip  100 B. This placement is especially useful tuning FET parametrics specific to a given core. A core is a pre-designed circuit function selected from a library of designs and integrated into a chip design. One examples of a core is an embedded memory. I DSAT  measurement circuits  105 A and  105 B are also placed close to I/O pads  120 A and  120 B respectively, in order to minimize impedance in wires  155 A and  155 B between the I DSAT  measurement circuits and the I/O pads effecting the I DSAT  measurements themselves. A peripheral pad layout is illustrated in  FIG. 2B  for clarity, however the present invention is applicable to any arrangement of pads  FIG. 3  is a block diagram illustrating generation of fuse blow data based on I DSAT  measurements according to the present invention. In  FIG. 3 , I/O pads  110 A to  110 N of integrated circuit chip  100  are electrically connected to a parametric measurement unit (PMU)  165  of tester  145 , which performs the I DSAT  measurements as described supra. Based on the value of the I DSAT  measurement obtained, tester  145  finds the closest value of the I DSAT  measurement on a lookup table  170  (see  FIG. 3 ) and generates fuse blow data  175 . The fuse blow data is a multi-bit word indicating which fuses to blow (programming a fuses is defined as blowing the fuse) on integrated circuit chip  100  in order to encode the I DSAT  measurements on the integrated circuit chip. The fuse circuits are illustrated in  FIG. 5  and described infra.  
         [0033]      FIG. 4  is an exemplary fuse blow pattern lookup table according to the present invention. Lookup table  170  includes a multiplicity of technology type pages  180 A to  180 M, there being one page for each technology type. A technology type is defined by physical groundrules and operating voltages. Each technology type page  180 A to  180 M includes a multiplicity of NFET tables  185 A to  185 I and PFET tables  190 A to  190 I, there being one table for each PFET and NFET type to be I DSAT  measured. Each NFET table  185 A to  185 I and PFET table  190 A to  190 I includes a list of I DSAT  measurement values  190  and corresponding fuse blow patterns  195 . In the example of  FIG. 4 , the fuse blow patterns are 8-bits (for eight fuses) and a zero indicates do not blow the fuse corresponding to that bit position and a one indicates do blow the fuse corresponding to that bit position. The number of lines of I DSAT  and corresponding fuse blow pattern on each page is a function of the granularity of I DSAT  measurement and the number of fuses per fuse bank.  
         [0034]      FIG. 5  is an exemplary fuse bank circuit for encoding on chip I DSAT  measurements according to the present invention. In  FIG. 5 , integrated circuit chip  100  includes a multiplicity of PFET fuse registers  200 A to  200 N store the state (0 not blown, 1 blown) of corresponding PFET fuse banks  205 A to  205 N. There is one set of PFET fuse registers  200 A to  200 N and fuse banks  205 A to  200 N for each I DSAT  measurement circuit  105 A to  105 N illustrated in  FIG. 1  and described supra. Further, integrated circuit chip  100  includes a multiplicity of NFET fuse registers  210 A to  210 N store the state (0 not blown, 1 blown) of corresponding NFET fuse banks  215 A to  215 N. There is one set of PFET fuse registers  210 A to  210 N and fuse banks  215 A to  210 N for each I DSAT  measurement circuit  105 A to  105 N illustrated in  FIG. 1  and described supra.  
         [0035]     Fuses in fuse banks  205 A to  205 N and  215 A to  215 N may be laser blow fuses, electrical blow fuses or electrical blow antifuses. In the example of  FIG. 5 , there are eight fuses per bank and the registers are eight bit registers. However, any number of fuses sufficient to encode the granularity of the I DSAT  measurements may be used. As an example, the outputs of PFET registers  200 A to  200 N may be averaged together by a PFET averaging circuit  220  to produce a PBITs signal  225  and the outputs of NFET registers  205 A to  205 N may be averaged together by an NFET averaging circuit  230  to produce an NBITs signal  235 .  
         [0036]      FIGS. 6A and 6B  illustrate respectively, an exemplary tunable off chip driver (OCD) circuit and lookup table according to the present invention. In  FIG. 6A , integrated circuit chip  100  includes a tunable OCD  250  includes eight driver circuits  255  receiving a data signal  260  and driving currents Z 0  to Z 7  to an output pad  265 . There are eight driver circuits  255  because PBITs signal  225  (see  FIG. 5 ) and NBITs signal  235  (see  FIG. 5 ) are, in the present example, 8-bit wide signals.  
         [0037]     Each driver circuit  255  includes first and second NAND gates  265  and  270 , first and second inverters  275  and  280 , a PFET  285  and an NFET  290 . One bit (P 0  to P 7 ) of PBITs signal  225  is coupled to a first input of first NAND gate  265  and data signal  260  is coupled a second input of first NAND gate  265 . The output of first NAND gate  265  is coupled to the gate of PFET  285 . One bit (N 0  to N 7 ) of NBITs signal  235  is coupled to a first input of second NAND gate  270  and data signal  260  is coupled through first inverter  275  to a second input of second NAND gate  270 . The output of second NAND gate  265  is coupled through second inverter  280  to the gate of NFET  290 . The source of PFET  285  is coupled to VDD and the source of NFET  290  is coupled to GND. The drains of PFET  285  and NFET  290  are coupled to output pad  265 .  
         [0038]     Whenever a bit P 0  to P 7  of PBITs signal  225  and a corresponding bit NO to N 7  of NBITs signal  235  is a one, then the corresponding driver circuit  255  will supply current to output pad  265  in response to a high data signal  260 .  
         [0039]      FIG. 6B  illustrates how nominal, worst case.(WC) process and best case (BC) process may be encoded in fuse registers which would result in PBITs signals  225  and NBITs signals  235  producing on output pad  265  the impedances listed at the exemplary operating temperatures of 25° C., 55° C. and 85° C.  
         [0040]      FIGS. 7A  is a timing diagram illustrating the relationship between noise and speed (dl/dt) of an OCD. In  FIG. 7A , a typical timing diagram for an OCD is shown. Three NFET gate voltage curves (N), three output voltage curves (Q) and three noise levels on the power supply of the PFET source (V SS ) and hence the output of the OCD are illustrated for fast, medium, and slow switching speeds. As may be seen from  FIG. 7A , as the speed of an OCD increases, so does the noise on the Vss terminal of the OCD.  FIG. 7B  illustrates an OCD that may be tuned, according to the present invention) to control the switching speed of an OCD and hence the noise on the output pad of the OCD.  
         [0041]      FIG. 7B  is a schematic diagram of an exemplary dl/dt tunable OCD circuit according to the present invention. In  FIG. 7B , only three bits of PBITs signal  225  (the P 2 , P 4  and P 7  bits) and the corresponding three bits of NBITs signal  235  (the N 2 , N 4  and N 7  bits) are used. In  FIG. 7B , OCD  300  on integrated circuit chip  100  includes a PFET gate delay circuit  305 A and an NFET gate delay circuit  305 B. PFET delay circuit  305 A includes an NFET  310 A and first, second, third and fourth PFETs  315 A,  320 A,  325 A and  330 A and first, second, and third resistors  335 A,  340 A and  345 A and in inverter  350 A. The P 7  bit of PBITs signal  225  is coupled to the gate of first PFET  315 A and through inverter  350 A to the gate of NFET  310 A. The P 2  bit of PBITs signal  225  is coupled to the gate of second PFET  320 A and P 4  bit of PBITs signal  225  is coupled to the gate of third PFET  325 A. First, second and third resistor  335 A,  340 A and  345 A are coupled in series with second resistor  340 A between first resistor  335 A and third resistor  345 A. The source/drains of NFET  310 A and the source drains of first PFET  315 A is coupled across the series resistor comprising first, second and third resistors  335 A,  340 A and  345 A. The source/drains of second PFET  320 A are coupled across first resistor  335 A and the source/drains of third PFET  325 A are coupled across third resistor  345 A.  
         [0042]     NFET delay circuit  305 B includes a PFET  310 B and first, second, third and fourth NFETs  315 B,  320 B,  325 B and  330 B and first, second, and third resistors  335 B,  340 B and  345 B and in inverter  350 B. The N 7  bit of NBITs signal  235  is coupled to the gate of first NFET  315 B and through inverter  350 B to the gate of PFET  310 B. The N 2  bit of NBITs signal  235  is coupled to the gate of second NFET  315 B and N 4  bit of NBITs signal  235  is coupled to the gate of third NFET  325 B. Fourth, fifth and sixth resister  335 B,  340 B and  345 B are coupled in series with fifth resistor  340 B between fourth resistor  335 B and sixth resistor  345 B. The source/drains of PFET  310 B and the source drains of first NFET  315 B is coupled across the series resistor comprising fourth, fifth and sixth resistors  335 B,  340 B and  345 B. The source/rains of second NFET  320 B are coupled across fourth resistor  335 B and the source/drains of fifth NFET  325 B are coupled across sixth resistor  345 B.  
         [0043]     A data signal  350  is coupled through an inverter  355  to a first end of the series resistor formed by first, second and third resistors  335 A,  340 A and  345 A and to a first end of the series resistor formed by fourth, fifth and sixth s  335 B,  340 B and  345 B.  
         [0044]     The gate of fourth PFET  330 A is coupled to a second end of the series resistor formed by first, second and third resistors  335 A,  340 A and  345 A. The gate of fourth NFET  330 B is coupled to a second end of the series resistor formed by fourth, fifth and sixth resistors  335 B,  340 B and  345 B. The drains of fourth PFET  330 A and fourth NFET  330 B are coupled to an output pad  360 . The source of fourth PFET  330 A is coupled to V SS  and the source of fourth NFET  330 B is coupled to GND.  
         [0045]     OCD driver  300  can be tuned to eight (2 3 ) different delays based on the combinations of bit values of PBITs P 2 , P 4  and P 7  and the bit values of NBITs N 2 , N 4  and N 7 . In one example, if P 2  and P 4  are one, N 2  and N 4  are zero, and P 7  is zero and N 7  is one, then all resistors are bypassed and there is no delay added to the data path. In a second example, if P 2  is zero, N 2  is one, P 4  is one, N 4  is zero, P 7  is one and N 7  is zero then the data path includes the delays caused by the combination of second and third resistors  340 A and  345 A and by the delays caused by the combination of fifth and sixth resistors  340 B and  345 B.  
         [0046]     Note, that the P 7  and N 7  bits are illustrated as inputs to complementary pass gates (NFET/PFET  310 A/ 315 A and NFET/PFET  315 B/ 310 B respectively) and the P 2 , N 2 , P 4  and N 4  bits are illustrated as inputs to single pass gates (PFET  320 A, NFET  320 B, PFET  325 A and NFET  325 B respectively). However, one of ordinary skill in the art would know that the PFET  320 A, NFET  320 B, PFET  325 A and NFET  325 B could be replaced with complementary pass gates and vice versa.  
         [0047]      FIG. 8A  is a schematic diagram of a related art data-generating circuit (DGC). In  FIG. 8A  DGC  400  includes an on chip receiver (OCR)  410 , an input of OCR  410  coupled to a clock signal  405  and an output of OCR  410  coupled to an input of a clock driver  415  and coupled to a clock input of a first register  420 . An input of first register  410  is coupled to an address signal  425  and an output of first register  420  is coupled to a memory array  430 . An output of memory array  430  is coupled to an input of a second register  435  and an output of clock driver  415  is coupled to a clock input of second register  435 . The output of second register  435  is coupled to an output pad  440  through an off-chip driver (OCD)  445 . The signal on output pad  440  is a data out (DQ) signal which is gated by clock driver  415 , second register  435 , and OCD  445 .  
         [0048]      FIG. 8B  is a timing diagram of the circuit of  FIG. 8A . In a nominal DGC  400  the DQ signal lags the CLOCK pulse by a time period LN. In a slow DGC  400  the DQ signal lags the CLOCK pulse by a time period LS&gt;LN. In a fast DGC  400  the DQ signal lags the CLOCK pulse by a time period LF&lt;LN. The window for valid data is defined as the time from the slowest possible DQ in to the time of the fastest DQ out. Thus, as the process variations increase, the valid data window decreases.  
         [0049]      FIG. 8C  is a schematic diagram of an exemplary output driver with a tunable data window circuit according to the present invention. In  FIG. 8C , integrated circuit chip  100  includes an DGC  450 . The difference between DGC  450  and DGC  400  of  FIG. 8A  is the addition of eight delays  455 A to  455 G, multiplexer  460  and averaging circuit  465 . The output of clock driver  415  is coupled to the inputs of delays  455 A to  455 G, each having a different delay. There are eight delays  455 A to  455 G because PBITs and NBITs are 8-bit words as described supra in reference to the example circuit of  FIG. 5 . The outputs of delays  455 A to  455 G are coupled to multiplexer  460 , the output of multiplexer is coupled to the clock input of second register  435 . A select line  490  couples the output of averaging circuit  465  to select input of multiplexer  460 . The inputs of averaging circuit  465  are PBITs signal  225  and NBITs signal  235  (see  FIG. 5 ). Thus based on I DSAT  measurement data encoded on fuse banks  205 A to  205 N and  215 A to  215 N (see  FIG. 5 ), a delay may be selected that delays a “fast” DGC  450  relative to the slowest specification so the valid data window increases.  
         [0050]      FIG. 9A  is a timing diagram for an embedded random access memory (RAM) core. In  FIG. 9A , a wordline (WL) on enables the sense amplifier (SA) set signal, which in turns gates the DATA signal and in turn gates the WL off. A fast core will have an early SA set signal and a slow core will have a late SA set signal. One consequence of variable SA set signal timing is a variation in the voltage separation between a bitline (BL) signal and a bitline not (BLN) signal when the SAs set. For example, a core is designed with a nominal 150 mv separation between BL and BLN. In a fast core, the separation is only 75 mv, while in a slow core it is 200 mv.  FIG. 9B  is a tunable circuit for controlling turn-on of sense amplifiers of the RAM core of  FIG. 9A  according to the present invention.  
         [0051]      FIG. 9B  is an exemplary tunable circuit for controlling turn-on of sense amplifiers of the RAM core of  FIG. 9A  and is exemplary of core timing tuning according to the present invention. In  FIG. 9B , integrated circuit chip  100  includes a delay circuit  500  for delaying SA set signal  505 . A dummy wordline signal  510  is coupled to the input of eight delay circuits  515 A to  515 G, each having a different delay. There are eight delays  515 A to  515 G because PBITs and NBITs are 8-bit words as described supra in reference to the example circuit of  FIG. 5 . The outputs of delays  515 A to  515 G are coupled to a multiplexer  520 . The output of de-multiplexer is delayed SA set signal  505 . A select line  525  couples the output of an inverting averaging circuit  530  to the select input of multiplexer  520 . The inputs of averaging circuit  530  are PBITs signal  225  and NBITs signal  235  (see  FIG. 5 ). Thus based on I DSAT  measurement data encoded on fuse banks  205 A to  205 N and  215 A to  215 N (see  FIG. 5 ), a delay may be selected that delays dummy wordline signal  510  so an optimal voltage separation between BL and BLN can develop.  
         [0052]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example the present invention may be applied to control delayed lock loop (DLL) jitter. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.