Abstract:
The invention describes a method for fabricating silicon semiconductor wafers with the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafers are used, the active semiconductor layer of which has the III-V semiconductor layers ( 24 ) of the HEMT design ( 2 ) placed on it stretching over two mutually insulated regions ( 24   a,    24   b ) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The application is a U.S. National Stage Application of International Application of PCT/EP2010/066656 filed Nov. 2, 2010, which claims benefit of German Patent Application No. 10 2009 051 521.6 filed Oct. 31, 2009, the disclosures of which are herein incorporated by reference in their entireties. 
     FIELD OF THE DISCLOSURE 
     The invention relates to semiconductor wafers comprising silicon layers and comprising structured III-V semiconductor layers, specifically group III nitride layers (for example GaN, AlN or InN), and thus to monolithic integration of silicon components comprising high electron mobility transistors (HEMTs) as III-V semiconductor components, there being the possibility of combining Si-based logic with individual specific III-V semiconductor components. 
     BACKGROUND OF THE DISCLOUSRE 
     Pure deposition or layer production of group III nitride layers on silicon wafers, in particular in a (111) orientation using buffer layers, is disclosed in DE 102 06 750 A1, DE 102 19 223 A1 and WO 2008/132204 A2. This involves deposition over the whole surface, without any structuring and without exposing the original Si surface. The major challenge of the method is to minimise the layer interlocking, based on the different lattice constants and lattice structure, by using adapted buffer layers, in such a way that there are no tears in the layers and no increase in lattice defects. 
     In WO 2006/138378 A1, US 2006/0284247 A1 and US 7,420,226 B2, a bonded multi-layer wafer is used to integrate the silicon CMOS technology having III-V semiconductors on a wafer. The multi-layer wafer consists of a substrate wafer of a material having high thermal conductivity (for example SiC or diamond) having continuous layers provided thereon: a monocrystalline layer (for example (111)-orientated silicon), the III-V layer thereon (for example AlGaN/GaN), a passivation layer thereon (for example of nitride), and a silicon layer thereon. In a first region CMOS transistors are provided in the silicon layer, in a second region the silicon layer is etched away, and in the lower, exposed III-V layer a high electron mobility transistor (HEMT), for example, is provided. 
     US 2007 0105274 A1 (or US 2007 0105335 A1 and US 2007 0105256 A1) discloses the application of further monocrystalline semiconductor layers and insulator layers to a silicon substrate wafer. This multi-layer wafer is produced by bonding. Structures are also disclosed in which different semiconductor materials are located in different regions on the surface. An example is shown in FIG. 8 thereof, in which a multi-layer wafer on the surface consists of silicon regions and of monocrystalline semiconductor regions, which are mutually separated by insulator layers or shallow trench isolations. FIG. 9 thereof illustrates a fabrication method which initially takes a multi-layer wafer as a basis for a starting wafer, subsequently provides silicon components in a front region (but only by front-end steps, i.e. process steps up to the contact plane without metallisation), subsequently etches down to a crystalline semiconductor layer in a second region, and fills the resulting depression with an epitactically grown monocrystalline semiconductor layer. The front-end process steps for structures in the monocrystalline semiconductor layer and the back-end steps (i.e. fabrication and metallisation) are carried out in succession. 
     FIG. 8 of US 2007 0105274 A1 discloses a prior art which is incorporated herein as FIG. 1. In terms of structure, the disclosed semiconductor arrangement consists of two regions 18 and 19 and uses a multi-layer wafer as the starting material. The first region 18 consists of a monocrystalline silicon layer 14, which is deposited over an insulation layer 13. Below the insulation layer 13 there are a monocrystalline semiconductor layer 12, consisting of a germanium and/or silicon/germanium layer, and a silicon substrate layer 11. The second region 19 consists of a second monocrystalline semiconductor layer sequence 16 and 17, which is positioned at least on part of the monocrystalline semiconductor layer 12. The two regions 18 and 19 are laterally mutually insulated by an insulation layer 15 or by shallow trench isolations (oxide, nitride or a combination thereof). 
     Continuous layers on substrates, for example substrates consisting of monocrystalline silicon, having different expansion coefficients or structures from the substrate, such as are used in the known method, lead to difficulties in fabricating the layer arrangement, involving the resilient interlocking of the layer arrangement and the risk of structural defects occurring in the active monocrystalline semiconductor layers, and this leads to degradation of the characteristic data, to a yield reduction and to a reduction in the reliability of the components constructed in the damaged layers, quite apart from the increased process and material cost. 
     SUMMARY OF THE INVENTION 
     There is a need to provide a method for fabricating semiconductor wafers comprising III-V layer structures for integrating HEMTs based on III-V semiconductor layers and having silicon semiconductor components and to provide appropriate layer structures, in such a way that there are advantages as regards the operation of the HEMTs, and drawbacks of the known methods are also overcome. 
     In a first aspect a method for fabricating at least one semiconductor wafer comprising an active silicon layer and having a structure of group III-V layers. The wafer is adapted for the integration of silicon components comprising HEMTs, which are based on group III-V layer structures. For this purpose, a substrate wafer is provided by means of which the active silicon layer is fabricated, the active silicon layer comprising a first region and a second region which are mutually electrically insulated, at least laterally, by a shallow trench isolation. A structured layer stack is further fabricated with an intermediate layer for lattice parameter adaptation, said intermediate layer being positioned on the active silicon layer of part of the first and second region and on a part between them of the shallow trench isolation, with a III-V semiconductor layer positioned above and a III x III 1-x -V semiconductor layer which ends the layer stack. Finally, an electrode is formed over part of the III x III 1-x -V semiconductor layer. 
     The method provides fabrication of layers on a semiconductor wafer for specific III-V semiconductor components such as HEMTs which are to be integrated, making relatively defect-free growth of a III-V semiconductor material possible on specific sub-regions of the semiconductor wafer, for example a CMOS silicon wafer. This makes possible a surface which is as planar as possible and makes electric insulation of the III-V semiconductor component from the rest of the wafer possible, at least in the lateral direction. Also, an effect or damage resulting from the silicon process steps, for example the CMOS technology or other silicon technologies, can be prevented or at least considerably reduced, both in terms of the III-V layers and in terms of damage to the silicon structures as a result of the III-V process steps. 
     Cost-effective fabrication can be provided with this method when wafer diameters conventional for CMOS are processed, for example 6 inches and greater. In this way, modern fabrication systems available for these wafer diameters can also be used for the fabrication process. 
     In a further embodiment, a source region and drain region are fabricated, also known as a source and drain. The source region is positioned over the first region of the active silicon layer and the drain region is positioned over the second region of the active silicon layer. In this way, the corresponding layers for an HEMT can be selected to be very small, since even with power transistors, part of the voltage drop may be across the semiconductor material of the first and second region, in particular on the drain side. The lateral isolation of the first and second region thus provides the desired electric strength, even in the region of the active silicon. 
     In a further embodiment, an electrode is formed as a gate, in such a way as to be positioned over the first region of the active silicon layer, over which the source region is also positioned. By selecting the position of the gate electrode in an adapted manner, the transistor properties, such as threshold voltage, leakage current and the like, can be set as desired, the position selected in this way being particularly adapted for relatively high-power transistors. 
     In a further embodiment, the active silicon layer is fabricated in such a way that a region in which silicon-based semiconductor components are fabricated is laterally delimited by isolation trenches. In this way, a desired delimitation between the III-V elements and the silicon components can be provided, and also protects the integrity of both types of component to a significant extent throughout the fabrication process. 
     In an advantageous embodiment, the substrate wafer is prepared in such a way that a buried insulation layer is formed below the active silicon layer, in such a way that the first and second region are delimited by the buried insulation layer and the shallow trench isolation. In this way, the III-V semiconductor elements are completely electrically isolated from the rest of the semiconductor wafer, in such a way that in this case, the advantages of III-V transistors, for example very high operating voltages, can be exploited without significantly influencing the remaining silicon regions. 
     In an advantageous embodiment, the layer stack is fabricated in such a way that the III x III 1-x -V semiconductor layer comprises aluminium, gallium and nitrogen, and the III-V semiconductor layer is a GaN layer. With this material combination, transistors in particular can be fabricated with a high power and high thermal stability. 
     In a further aspect, a semiconductor arrangement for monolithic integration of HEMTs is based on group III-V semiconductor layer structures and having silicon components. In this context, the semiconductor layer arrangement comprises an active silicon layer, which is formed over a substrate wafer and has a first region and a second region which is at least laterally electrically insulated therefrom. A layer stack is further provided, is formed on the surface of the active silicon layer over the first and the second region, and comprises an intermediate layer, which is positioned on the active silicon layer, a III-V semiconductor layer positioned above, and a III x III 1-x -V semiconductor layer thereon. An electrode is further formed on or over part of the III x III 1-x -V semiconductor layer. 
     The semiconductor layer arrangement according to the invention provides the same advantages, in terms of the fabrication and in terms of the transistor properties of the transistors fabricated from this layer structure, as were described above for the method according to the invention. 
     Further illustrative embodiments of the claimed invention are explained in the followed detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will now be explained in greater detail by way of embodiments, with reference to the schematic, sectional drawings, in which: 
         FIG. 1  is a cross-section of a layer arrangement of a semiconductor wafer according to the prior art, and 
         FIG. 2  is a cross-section of a layer arrangement of a first example of the semiconductor wafer according to the invention for fabricating an HEMT, based on a III-V semiconductor structure, adjacent to mutually electrically insulated regions of an active silicon layer. This also discloses an example of a method. 
         FIG. 2  is a schematic cross-section of a semiconductor arrangement  1  comprising a semiconductor substrate wafer  20  which in the example shown is provided in the form of a silicon carrier wafer  20 . Further, a buried oxide layer  22  is formed on the substrate wafer  20  and an active silicon layer  24  is arranged thereover, in such a way that these components produce an SOI silicon wafer. 
     
    
    
     In other embodiments (not shown), a bulk architecture may also be used, i.e. a construction in which the “vertical” insulation is provided by corresponding doping instead of the buried layer  22 . 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     In the active layer  24 , individual mutually electrically insulated regions are produced in the active layer  24  by introducing a shallow trench isolation structure  26 , which is to be understood as a combination of a plurality of isolation trenches  26   a ,  26   b ,  26   c , some of which are interconnected. 
     In the example shown, a region  24   c  is marked in which for example silicon semiconductor elements, such as diodes and transistors, are fabricated or are to be fabricated, this being carried out using adapted technology. Processes and materials based on well-known CMOS technology can be used for this purpose, as can other silicon processing technologies. 
     In the embodiment of  FIG. 2 , the region  24   c  is completely electrically insulated from other regions, i.e. the regions  24   a  and  24   b , by corresponding regions of the shallow trench isolation  26  and by the buried insulation layer  22 . In combination, the regions  24   a  and  24   b  form a region in and over which III-V semiconductor components are fabricated. However, the first region  24   a  is also electrically insulated from the second region  24   b , in the lateral direction by a part  24   c  of the shallow trench isolation  26  and in the vertical direction by the buried insulation layer  22 . 
     If appropriate, lateral and/or vertical insulation of the regions  24   a ,  24   b  may also be provided using adapted doping regions, if this is compatible with the desired transistor properties of one or more transistors which are to be fabricated in and over the regions  24   a ,  24   b.    
     A layer stack  2  is produced so as to form an intermediate layer  60  for lattice parameter adaptation, a III-V semiconductor layer  30  and a III x III 1-x -V semiconductor layer  62  over the regions  24   a ,  24   b  and also over the part  26   c  of the shallow trench isolation  26 , and at least one HEMT may be fabricated from this layer stack  2 . 
     The layer stack  2  may be applied by adapted deposition and structuring methods, such as MOCVD (metalorganic chemical vapour deposition), the process parameters and the precursor gases being selected in such a way that the respective layers are obtained with the desired thickness and material composition. For example, the intermediate layer  60  is deposited as an AlGaN layer, so as to reduce the lattice differences between the silicon of the layer  24  and the following III-V semiconductor, which in an advantageous configuration is applied as GaN having a thickness of approximately (substantially) 1 μm or less, the thickness also depending on the desired properties of the transistor to be formed, which is to be fabricated from the layer stack  2 . 
     Because the silicon material is provided in the regions  24   a ,  24   b , the thickness of the layer  30  at a desired operating voltage for the HEMT can be reduced by comparison with conventional GaN-based HEMTs. 
     The “barrier layer”  62  is adjacent to the layer  30 , is typically of a lower thickness than the layer  30 , and is provided for example as an AlGaN layer having suitably high doping, for example n-doping. 
     Other layer sequences may also be used in the stack  2  if other electronic properties are required. The basic construction remains the same in terms of the position and orientation relative to the regions  24   a ,  24   b.    
     In the manufacturing phase shown, the stack  2  is modified in such a way that an HEMT is fabricated therefrom. A source region S of the HEMT is positioned vertically above the insulated region  24   a , and a drain region D is positioned vertically above the region  24   b . The (horizontal) length of the HEMT is determined inter alia by the required breakdown voltage, i.e. by the length of the depletion region between the source S and the drain D. 
     As explained above, the vertical height of the III-V semiconductor layer  30  can be made very thin, since the III-V semiconductor  30  does not have to receive the entire drain voltage in the vertical direction, but the active layer  24 , i.e. in particular the region  24   b  and to some extent also the region  24   a , can take over part of the voltage stability. Further, the stack  2  comprises an electrode G which—based on adapted structuring—acts as a gate electrode for the HEMT. The electrode thus has an adapted shape for the transistor operation, in such a way that in particular a desired gate length is defined. The electrode G can be applied directly to the layer  62 , or a thin insulator layer (not shown) may be provided between the electrode G and the layer  62  so as to reduce the gate leakage currents. 
     The gate electrode G and the drain region D and source region S can be fabricated by known methods as a Schottky contact or an ohmic contact, by applying metallisation and by heating or the like. 
     Because of the reduced thickness of the semiconductor layer  30 , the step height of the III-V semiconductor layers, i.e. of the stack  2 , is reduced considerably, and an almost planar surface can be achieved. 
     In an advantageous variant of the method for manufacturing silicon semiconductor wafers having group III-V layer structures for integrating silicon components having high electron mobility transistors (HEMTs) based on group III-V layer structures, the following steps are used: 
     An SOI silicon wafer is used having regions of the active silicon layer  24  which are mutually insulated by insulation layers  22 ,  26 . A structured layer stack  2 , formed from an intermediate layer  60  for lattice parameter adaptation, which is positioned on the active silicon layer  24 , a III-V semiconductor layer  30  positioned thereover and a III x III 1-x -V semiconductor layer  62  (which preferably terminates the stack), is applied in such a way that this stack is positioned in an expanse according to the component size on two regions which are mutually electrically insulated by an isolation trench  26 , i.e. the regions  24   a ,  24   b , of the active semiconductor layer  24 , the source and drain being formed in such a way that the source is positioned over one, the region  24   a , and the drain is positioned over the other, the region  24   b , of the two mutually electrically insulated regions of the active silicon layer  24 . A gate is formed in such a way as to be located over the electrically insulated region of the active silicon wafer  24 , over which the source is also positioned. This is all considered in a vertically aligned manner. 
     In an advantageous variant of the semiconductor layer arrangement for monolithic integration of HEMTs based on group III-V semiconductor layer structures and having silicon components, a layer stack  2  is provided. The layer stack  2  is formed on the surface of the active silicon layer  24  of an SOI wafer and consists of: an intermediate layer  60 , which is positioned on the active silicon layer  24 , a III-V semiconductor layer  30  positioned above and a III x III 1-x -V semiconductor layer  62 . The layer stack  2  is positioned, in terms of component size, on two regions of the active semiconductor layer  24  which are mutually electrically insulated by an isolation trench  26   c , for example the regions  24   a ,  24   b . Further, the source and drain are formed in the layer stack in such a way that the source is positioned on one and the drain is positioned on the other of the two mutually electrically insulated regions of the active semiconductor layer  24 , and the gate is positioned over the electrically insulated region  24   a  of the active silicon layer  24 , over which the source S is also positioned.