Abstract:
A Single-switched Resonant DC Link (SRDCL) converter is presented for a parallel resonant network with a single auxiliary power device for low conduction loss in single or poly-phase inverter and converter applications. The resonant network with an auxiliary power device is activated when the status of power devices coupled to the DC link changes. The resonant network forces the DC link voltage to drop to zero before any of the power devices coupled to the DC link are turned on. The auxiliary switch is also turned on with a Zero-Voltage Switching condition. Therefore, the switching losses caused in all power devices can be effectively eliminated. There is no severe conduction loss in the auxiliary power device because the resonant circuit is not activated if there is no change of status in the power devices coupled to the DC link.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims priority from provisional U.S. application 60/420,839: “Zero-voltage-switching SRDCL (single-switched resonant DC link) inverter with minimized conduction loss” by In-Hwan Oh, filed Oct. 23, 2002. 
     
    
     
       BACKGROUND OF INVENTION  
         [0002]    1. Field of Invention  
           [0003]    The present invention relates to DC-to-DC or DC-to-AC poly-phase converters, and more particularly to Single-switched Resonant DC Link (SRDCL) converters, employing power devices, which switch with zero voltage switching condition.  
           [0004]    2. Description of Prior Art  
           [0005]    Power devices can experience considerable loss during switching losses. A cause of this loss is that during the switching process the current and the voltage of the device can be simultaneously non-zero. This problem was addressed in U.S. Pat. No. 4,730,242 issued on May 8, 1988, describing a Resonant DC Link (RDCL) converter. A related actively clamped RDCL converter is shown in U.S. Pat. Nos. 4,864,483 and 5,038,267. A corresponding method for detecting zero voltage conditions is described in U.S. Pat. No. 5,166,549 issued on Nov. 24, 1992.  
           [0006]    However, an aspect of the actively clamped RDCL converters is the high voltage stress on the main converter switches, because the voltage stress by the natural resonance can be 2-3 times higher than the input DC source voltage, as described by In-Hwan, et al. in “Simple Soft-Switched PWM Inverter Using Source Voltage Clamped Resonant Circuit,” IEEE Tran. on Industrial Electronics Vol. 46, pp. 468-471, April 1999]. To relieve this high voltage stress problem, alternative parallel resonant circuits and DC rail soft-switched resonant circuits are described in U.S. Pat. No. 5,111,374 issued on May 5, 1992; U.S. Pat. No. 5,172,309 issued on Dec. 15, 1992; U.S. Pat. No. 5,412,557, issued on May 2, 1995, and U.S. Pat. No. 5,559,685 issued on Sep. 24, 1996. However, these schemes require two or three more switches and hence are still quite expensive and complex approaches. The clamped RDCL converter disclosed in U.S. Pat. No. 5,617,308 uses only one switch to achieve the soft switching. But the resonant link voltage in this patent may be significantly increased because the clamping capacitor is charged by a reactive energy of the inductive load.  
           [0007]    The link voltage can be clamped by a synchronized resonant DC link converter for the soft-switched PWM using a simple implementation and easy control, as described by D. M. Divan, et al. in: “Design Methodologies for Soft Switched Inverters,” IEEE Trans. on Ind. Appl., Vol. 29, No. 1, pp. 126-135, January/February, 1993]. This SRDCL scheme can clamp the peak voltage stress, but the peak voltage of the SRDCL converter is still higher than Vdc. In addition, the DC link voltage may be greatly increased, when the load current changes because the load current charges the clamping capacitor. Moreover, the current stress on the resonant switch may be large, since the load current overlaps with the resonant current, as can be seen from the experimental results shown in FIGS. 6A and 6B, as discussed by In-Hwan Oh et al in, “A Source Voltage Clamped Resonant Link Inverter for a PMSM using a Predictive Current Control Technique”, IEEE Transactions on Power Electronics, Vol. 14, No. 6, pp. 1122-1132, November 1999].  
           [0008]    A particular feature of the above-described converters is that the auxiliary power device of the resonance of DC link is placed into the power line. Such topologies cause a power loss by the load current, while the DC link voltage is at a nominal voltage level.  
         SUMMARY  
         [0009]    Briefly and generally, embodiments of the invention include a converter circuit, which includes an AC-to-DC converter, which can be a simple bridge rectifier or contains a group of first power devices, a resonant DC link, including an auxiliary power device, a DC-to-AC converter, which includes a group of second power devices, and DC link lines, coupling the AC-to-DC converter, the resonant DC link, and the DC-to-AC converter, wherein the auxiliary power device is coupled between the DC link lines.  
           [0010]    Additional embodiments include a converter, which includes an AC-to-DC converter, a resonant DC link, a DC-to-AC converter, and DC link lines. The DC-to-AC converter includes a resonant capacitor, an equivalent power diode, and an equivalent switch, wherein the resonant capacitor, the equivalent power diode, and the equivalent switch are coupled between the DC link lines and parallel with each other. The resonant DC link includes an auxiliary power device. The DC link lines couple the AC-to-DC converter, the resonant DC link, and the DC-to-AC converter. The auxiliary power device is coupled between the DC link lines.  
           [0011]    Embodiments of the invention can be operated with a zero voltage switching condition. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0012]    For a more complete understanding of the present invention and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings.  
         [0013]    [0013]FIG. 1 illustrates a converter topology, according to an embodiment of the invention.  
         [0014]    [0014]FIG. 2 is an equivalent circuit of the converter topology, according to an embodiment of the invention.  
         [0015]    FIGS.  3 A-H illustrate steps of a method of operating the converter circuit, according to an embodiment of the invention.  
         [0016]    [0016]FIG. 4 illustrates various currents and voltages during the different steps of the method of FIGS.  3 A-H, according to an embodiment of the invention.  
         [0017]    [0017]FIG. 5 illustrates various currents and voltages during the different steps of the method of FIGS.  3 A-H, according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0018]    Embodiments of the present invention and their advantages are best understood by referring to FIGS.  1 - 5  of the drawings. Like numerals are used for like and corresponding parts of the various drawings.  
         [0019]    [0019]FIG. 1 illustrates an embodiment of the invention. A converter circuit  100  includes an AC-to-DC converter  110 . AC-to-DC converter  110  includes a group of power devices  112 - 1  . . .  112 -n. Converter  100  also includes a resonant DC link  120 , which includes at least one auxiliary power device  122 . Converter  100  further includes a DC-to-AC converter  130 , which includes a group of second power devices  132 - 1  . . .  132 -n′, and DC link lines  150 . DC link lines  150  couple AC-to-DC converter  110 , resonant DC link  120 , and DC-to-AC converter  130 . Auxiliary power device  122  is coupled between DC link lines  150 .  
         [0020]    In AC-to-DC converter  110  the number of power devices  112 , n, can be between two or more depending on output phases. For example, n can be six in embodiments, which receive a three-phase AC power. Power devices  112  can contain power transistors  113 - 1  . . .  113 -n, of the MOS-FET type or NPN bipolar transistors. In some embodiments power diodes  114 - 1  . . .  114 -n are coupled across power transistors  112 . In some embodiments, power diodes  114  are not formed explicitly, they are parasitic diodes, formed as a byproduct of forming power transistors  113 . In embodiments, where power devices  112  are MOS-FETs, power diodes  114  are coupled between the source and the drain of the corresponding power MOS-FET.  
         [0021]    In AC-to-DC converter  110  power devices  112  are coupled pair wise in series,  112 - 1  and  112 - 2  forming a first arm  117 - 1 ,  112 - 3  and  112 - 4  forming a second arm  117 - 2 , and  112 - 5  and  112 - 6  forming a third arm  117 - 3 . In other embodiments the number of arms can be between about 1 and about 6.  
         [0022]    In some embodiments terminals  115 - 1  . . .  115 - 3  are coupled to arms  117 - 1  . . .  117 - 3  between the power transistors of the corresponding arm. Terminals  115  can be coupled to an external AC power source to receive an AC current.  
         [0023]    In DC-to-AC converter  130  the number of power devices  132 , n′, can be two or more depending on the AC output phase, for example, six for three-phase systems. Power devices  132  can include power transistors  133 - 1  . . .  133 -n′. Power transistors  133  can be, for example, MOS-FET devices. In some embodiments power diodes  134 - 1  . . .  134 -n′ are coupled across power transistors  133 - 1  . . .  133 -n′. In other embodiments, power diodes  134  can be formed as a byproduct of forming power transistors  133 . In embodiments, where power devices  132  are MOS-FETs, power diodes  134  are coupled between the source and the drain of the corresponding power MOS-FETs.  
         [0024]    In AC-to-DC converter  130  power devices  132  are coupled pair wise in series,  132 - 1  and  132 - 2  forming a first arm  137 - 1 ,  132 - 3  and  132 - 4  forming a second arm  137 - 2 , and  132 - 5  and  132 - 6  forming a third arm  137 - 3 . In other embodiments the number of arms can be between 1 and 6.  
         [0025]    In some embodiments terminals  135 - 1  . . .  135 - 3  are coupled to arms  137 - 1  . . .  137 - 3  between the power transistors of the corresponding arm. Terminals  135  can be coupled to an external load  144  to deliver an AC current. External load  144  can be, for example, a motor, denoted by M.  
         [0026]    Auxiliary power device  122  of resonant DC link  120  includes an auxiliary power transistor  123 , which can be of the MOS-FET or npn bipolar power transistor type. An auxiliary power diode  124  is coupled across auxiliary power transistor  123 . In embodiments, where auxiliary power transistor  123  is a MOS-FET, auxiliary power diode  124  can be coupled between the drain and the source of the MOS-FET. In other embodiments, auxiliary power diode  124  can be formed as a byproduct of forming auxiliary power transistor  123 .  
         [0027]    Further elements of resonant DC-link include a first capacitor C 1 , coupled in series with auxiliary power device  122 , an inductance L r , coupled in parallel with auxiliary power device  122  and first capacitor C 1 . In some embodiments capacitors C 1  and C 2  have large capacitances, for example, in comparison to the parasitic capacitances of the rest of converter  100 . In these embodiments the characteristic time associated with capacitors C 1  and C 2  is much longer than other characteristic times of converter  100 . Therefore, capacitors C 1  and C 2  can be considered as voltage sources since the voltages of capacitors C 1  and C 2  change much slower than the voltages in the rest of the circuit.  
         [0028]    [0028]FIG. 2 illustrates another embodiment of the invention. This embodiment is essentially equivalent to the converter of FIG. 1. The functions of AC-to-DC converter  110  can be performed by a simplified input circuit, which includes a voltage source V dc  coupled in series with an inductor L i .  
         [0029]    In DC-to-AC converter  130  an equivalent switch Q x  can replace power devices  132 . Anti-parallel diode D x  represents all power diodes  114  and  134 . The current, drawn by load  144  can be considered as a current source I o  for the rest of the circuit, because in some embodiments the load inductance can be up to 10 times or more bigger than the resonant inductance L r . Capacitor Cr in DC-to-AC converter  130  represents all parasite capacitors between resonant DC link  120  and all parallel- and series-connected output capacitors of power devices  112  and  132 . The closed/conducting/turned on state of equivalent switch Q x  corresponds to a situation when both power transistors of a given arm are in a closed/conducting/turned on state.  
         [0030]    During the operation of converter  100  inductor L r  and capacitor C r  form a resonant circuit with the fastest characteristic time of the circuit: T 2 ≡2π{square root}{square root over (L r C r )}. T 2  will be also referred to as the resonant cycle or resonant time.  
         [0031]    In resonant DC link  120  resonant switch Q r  and power diode D r  represent auxiliary power device  122 . The V c1  and V c2  voltages represent the essentially constant voltages of capacitors C 1  and C 2 .  
         [0032]    Straightforward circuit analysis shows that the embodiment of FIG. 2 performs essentially analogously to the converter  100  of FIG. 1. Next, the operation of converter  100  will be described.  
         [0033]    In some embodiments the operation can be divided into five steps or phases based on the switching time of the power devices and the resonant cycle. The number of steps or phases depends on the various characteristic time constants of the circuit. These time constants include the switching times of the power devices and the period of the resonant cycle of L r  and C r . The analysis will disregard the non-ideal aspects of switches Q x  and Q r  and the core saturation of inductance L r .  
         [0034]    FIGS.  3 A-H illustrate the steps of the operation of the converters  100  of FIGS. 1 and 2. In these drawings thick lines indicate electrical couplings, where a major portion of the current is flowing.  
         [0035]    Converter  100  can have at least two initial states for t&lt;t 0 : State 0 and State 1, as shown in FIGS. 3A and B.  
         [0036]    [0036]FIG. 3A illustrates that in State 0 switches Q x  and Q r  are open and a major portion of the current is flowing in DC link lines  150  and load  144 .  
         [0037]    [0037]FIG. 3B illustrates that in State 1 switches Q x  and Q r  are also open. A major portion of the current is flowing through DC link lines  150  and load  144 . In addition, current is flowing through L r  and C r  and power diode D x .  
         [0038]    We consider the steps of the method starting with State 0, in which equivalent switch Q x  is open/turned off.  
         [0039]    [0039]FIG. 3C illustrates Step 1. In Step 1 (t 0 ≦t&lt;t 1 ) resonant switch Q r  is turned on at t=t 0 . The inductor current i L (t) flows through C 1 , Q r , and L r . The current i L (t) flowing through inductor L r  is given by:  
                 i   Lr          (   t   )       =         V   c1       L   r          t             (   1   )                               
 
         [0040]    The current i L (t) reaches a maximum value at time t 1 :  
                 I   1     ≡       i   Lr          (     t   1     )         =         V   c1       L   r            (       t   1     -     t   0       )               (   2   )                               
 
         [0041]    The voltage across equivalent switch Q x  also will be referred to as the DC link voltage: ν Qx (t)=ν dc (t). The value of the DC link voltage is given as:  
         ν Qx ( t   0   ˜t   1 )= V   c1   +V   c2   (3) 
         [0042]    [0042]FIG. 3D illustrates Step  2 . In Step  2  (t 1 ≦t&lt;t 2 ) resonant switch Q r  is turned off. At this time a major portion of the current flows through the circuit containing L r  and C r . The voltage across C 2  can be approximately considered as a voltage source V c2  as described above. The voltage across equivalent switch Q x  is given by:  
         ν Qx ( t )=( V   c1   +V   c2 )cos ω r ( t−t   1 )  (4) 
         [0043]    The resonant time T 2  corresponding to the setting of Step  2  can be calculated as  
           T   2 =2π{square root}{square root over ( L   r   C   r )}  (5) 
         [0044]    The settings of Step  2  are maintained for a time period t 2 −t 1 , whose length is chosen as t 2 −t 1 =T 2 , so that at the end of Step  2  voltage v dc (t) drops to zero at t=t 2 .  
         [0045]    [0045]FIG. 3E illustrates the first period of Step  3 . In the first period of Step  3  (t 2 ≦t&lt;t 3 ), the anti-parallel diode, D x , will be conducting/closed, because the inductor current i L (t) is positive (it flows towards capacitor C 2 ). Q x  is turned on when D x  is conducting and thus the voltage across Q x  is zero. This feature of the present embodiment avoids power loss, a condition referred to as “Zero-Voltage-Switching” (ZVS) condition.  
         [0046]    [0046]FIG. 3F illustrates the second period of Step  3 . In the second period of Step  3  (t 3 ≦t&lt;t 4 ) equivalent switch Q x  is still turned on. However, the polarity of inductor current i L (t) changed to negative. In this period inductor current i L (t) decreases linearly with voltage V c2  of second capacitor C 2 . At the end of the second period of Step  3  at t=t 4  equivalent switch Q x  is turned off. The current across equivalent switch Q x  can be written as:  
                 i   Qx          (   t   )       =         V   c2       L   r            (     t   -     t   3       )               (   6   )                               
 
         [0047]    reaching the maximum value at t 4 :  
                 I   4     ≡       i   Qx          (     t   4     )         =         V   c2       L   r            (       t   4     -     t   3       )               (   7   )                               
 
         [0048]    [0048]FIG. 3G illustrates Step  4 . In Step  4  (t 4 ≦t&lt;t 5 ) the polarity of inductor current i L (t) is negative and Q x  is turned off. Therefore, in Step  4  DC link voltage v Qx (t) increases due to the resonance between L r  and C r .  
         [0049]    [0049]FIG. 3H illustrates Step  5 . In Step  5  (t 5 ≦t&lt;t 6 ), when DC link voltage v Qx (t) reaches a value (V c1 +V c2 ) at t=t 5 , the extra resonant inductor current can be directed through L r , D r , and C 1 . The DC link voltage v Qx (t) can be written as:  
         ν Qx ( t )=( V   c1   +V   c2  )sin ω r ( t−t   4 )  (8) 
         [0050]    [0050]FIGS. 4, 5A, and  5 B illustrate the currents and voltages corresponding to the Steps of FIGS.  3 A-H.  
         [0051]    [0051]FIGS. 4, 5A, and  5 B illustrate the zero voltage switching (ZVS) feature of converter  100 . The turn-on signal of Q x  is applied after the voltage v Qx (t)=v dc (t) reaches zero. Further, the turn-on signal of resonant switch Q r  can be applied between (t 5 ≦t&lt;t 6 ), in which time period the voltage v Qr (t) is zero. Therefore, both switches Q x  and Q r  are turned on with zero-voltage switching (ZVS) condition, avoiding switching loss. In these embodiments, the switching cycle starts over with converter  100  in State 1, avoiding the State 0 condition.  
         [0052]    In some embodiments of the method the switching time is extended. These embodiments can provide pulse width modulation (PWM), depending on the load requirement. In these embodiments Q r  is turned on at some later time t=t 7 . The delay time period t 7 −t 6  is sometimes referred to as a time slot T 7 =t 7 −t 6 . At t=t 7  the voltage, v Qr (t) is essentially V c1 , a value greater than zero. Therefore, Q r  will not be turned on with zero voltage condition at t=t 7 . However, since the typical voltage level of V c1  is very low compared to V c2  and the current flowing into Q r  starts from zero, the switching loss caused by voltage and current crossing is almost zero. In these embodiments the switching cycle starts over with converter  100  in State 0.  
         [0053]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, the discussion included in this application is intended to serve as a basic description. It should be understood that the specific discussion may not explicitly describe all embodiments possible; many alternatives are implicit. It also may not fully explain the generic nature of the invention and may not explicitly show how each feature or element can actually be representative of a broader function or of a great variety of alternative or equivalent elements. Again, these are implicitly included in this disclosure. Where the invention is described in device-oriented terminology, each element of the device implicitly performs a function. Neither the description nor the terminology is intended to limit the scope of the claims.