Abstract:
A variable gain amplifying circuit incorporates an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has an output terminal providing an amplified difference output signal. The input device has a first terminal receiving a first input signal, and a second terminal coupled to a first input terminal of the operational amplifier. The feedback device is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The dynamic biasing circuit generates a bias current to according to a set value. The transconductance circuit converts the difference between the first input signal and a second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to variable gain amplifying circuits. 
         [0003]    2. Description of the Related Art 
         [0004]    A variable gain amplifying circuit is used to amplify or attenuate an input signal according to a gain controlled by a gain controller.  FIG. 1  illustrates a prior art variable gain amplifying circuit  100 . Referring to  FIG. 1 , the variable gain amplifying circuit  100  includes a differential operational amplifier  12 , fixed resistors R 1 A and R 1 B, and variable resistors R 2 A and R 2 B. 
         [0005]    Referring to  FIG. 1 , each of the variable resistors R 2 A and R 2 B has a plurality of circuits, each having a fixed resistor and a MOSFET serving as a switch connected in series, are connected in parallel. A gain controller  14  generates several logic signals to input into the MOSFETs in the variable resistors R 2 A and a gain controller  16  generates several logic signals to input into the MOSFETs in the variable resistors R 2 B, respectively. A combined resistance of the variable resistor R 2 A or R 2 B is determined by turning on or turning off the respective MOSFETs, so that the resistances of the resistors R 2 A and R 2 B are determined. In this manner, the total gain of the variable gain amplifying circuit  100  is determined. 
         [0006]    As known, the gain of the variable gain amplifying circuit  100  is determined according to the ratio of the feedback resistance to the input resistance. Therefore, if N gain steps are required, each of the variable resistors R 2 A and R 2 B requires N MOSFETs connected to N fixed resistors. As a result, the chip area of the variable gain amplifying circuit  100  increases as the increase of the number of N. 
       SUMMARY OF THE INVENTION 
       [0007]    An aspect of the present invention is to provide a variable gain amplifying circuit for amplifying a difference between a first input signal and a second input signal to generate an amplified difference output signal. According to one embodiment of the present invention, the variable gain amplifying circuit comprises an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has a first input terminal, a second input terminal, and an output terminal providing the amplified difference output signal. The input device has a first terminal receiving the first input signal, and a second terminal coupled to the first input terminal of the operational amplifier. The feedback device has a first terminal coupled to the first input terminal of the operational amplifier, and has a second terminal coupled to the output terminal is of the operational amplifier. The dynamic biasing circuit generates a bias current according to a set value. The transconductance circuit converts the difference between the first input signal and the second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The invention will be described according to the appended drawings in which: 
           [0009]      FIG. 1  illustrates a prior art variable gain amplifying circuit; 
           [0010]      FIG. 2  shows a block diagram of a variable gain amplifying circuit according to one embodiment of the present invention; 
           [0011]      FIG. 3  illustrates a detailed circuit diagram of the variable gain amplifying circuit shown in  FIG. 2  according to one embodiment of the present invention; according to another embodiment of the present invention; 
           [0012]      FIG. 5  illustrates a detailed circuit diagram of the variable gain amplifying circuit shown in  FIG. 4  according to one embodiment of the present invention; 
           [0013]      FIG. 6  shows a block diagram of a variable gain amplifying circuit; 
           [0014]      FIG. 7  shows the operation of the variable gain amplifying circuit; 
           [0015]      FIG. 8  shows a block diagram of a variable gain amplifying circuit according to yet another embodiment of the present invention; and 
           [0016]      FIG. 9  illustrates a detailed circuit diagram of the variable gain amplifying circuit shown in  FIG. 8 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]      FIG. 2  shows a block diagram of a variable gain amplifying circuit  200  according to one embodiment of the present invention. Referring to  FIG. 2 , the variable gain amplifying circuit  200  includes a gain amplifier  22 , a transconductance circuit  24 , and a dynamic biasing circuit  26 . 
         [0018]    The gain amplifier  22  receives an analog input signal VI to generate an analog output signal VO. In one embodiment of the present invention, the gain amplifier  22  is composed of a single-input single-output amplifier  224 , a fixed input resistor R 1 , and a fixed feedback resistor R 2 . An initial gain G of the gain amplifier  22  shown in  FIG. 2  without externally injecting current from the transconductance circuit  24  can be expresses as: 
         [0000]        G=R 2 /R 1  (1)
 
         [0019]    However, a new gain G′ of the gain amplifier  22  can be obtained by varying the net current flowing through the feedback resistor R 2 . Referring to  FIG. 2 , the transconductance circuit  24  is configured to convert the difference between an input signal VI and a reference voltage VREF into an analog output current IGM. Thereafter, the transconductance circuit  24  provides the current IGM to the gain amplifier  22  to adjust the gain G′ of the gain amplifier  22 . Note that a bias current IDYN of the transconductance circuit  24  comes from the dynamic biasing circuit  26 . The bias current IDYN of the transconductance circuit  24  can be varied according to an input signal VLEL. 
         [0020]      FIG. 3  illustrates a detailed circuit diagram of the variable gain amplifying circuit  200  shown in  FIG. 2  according to one embodiment of the present invention. Referring to  FIG. 3 , the dynamic biasing circuit  26  includes a current generator  262  and a current mirror  264 . In this embodiment, the current generator  262  is composed of an operational amplifier  2622 , a NMOS transistor N 1 , and a resistor RLEL. The operational amplifier  2622  has a positive input terminal receiving the input signal VLEL, a negative input terminal coupled to the resistor RLEL, and an output terminal coupled to a gate of the NMOS transistor N 1 . In this manner, the current flowing through the NMOS transistor N 1  is equal to the value of the input signal VLEL divided by the resistance of the resistor RLEL. 
         [0021]    Referring to  FIG. 3 , the current mirror  264  is formed by three PMOS transistors P 1 , P 2 , and P 3 . The PMOS transistor P 1  receives the current flowing through the NMOS transistor N 1 , and the PMOS transistors P 2  and P 3  generate currents which are proportional to the W/L ratio of the transistors. The current flowing through the PMOS transistor P 3  is sent to the transconductance circuit  24  as an upper bias current source. The current flowing through the PMOS transistor P 2  is sent to a NMOS transistor N 2 . The current flowing through the NMOS transistor N 3  mirrors the current flowing through the NMOS transistor N 2 . Then, the current flowing through the NMOS transistor N 3  is sent to the transconductance circuit  24  as a down bias current source. 
         [0022]    Referring to  FIG. 3 , the transconductance circuit  24  includes a parallel input transistor pair including PMOS transistors P 4  and P 5 , and NMOS transistors N 4  and N 5 , wherein the PMOS transistor P 4  and the NMOS transistor N 4  are coupled in series between the upper bias current source and the down bias current source, and the PMOS transistor P 5  and the NMOS transistor N 5  are coupled in series between the upper bias current source and the down bias current source. 
         [0023]    Referring to  FIG. 3 , the gates of the PMOS transistor P 4  and the NMOS transistor N 4  receive the analog input signal VI, and the gates of the PMOS transistor P 5  and the NMOS transistor N 5  receive the reference voltage VREF. Therefore, the output current IGM of the transconductance circuit  24  responds to the difference between the input signal VI and the reference voltage VREF. In addition, the gain of the transconductance circuit  24  is in response to variations in a magnitude of the bias current source. 
         [0024]    The detailed operation of the variable gain amplifying circuit  200  will be described below with respect to  FIG. 3 . As the value of the input signal VLEL increases, the current flowing through the resistor RLEL increases. Because the current mirror  264  functions to produce a copy of the current flowing through the resistor RLEL, the current flowing through the PMOS transistor P 3  and the current flowing through the NMOS transistor N 3  increases as the value of the input signal VLEL increases. Since the magnitude of the bias current source of the transconductance circuit  24  increases, the output current IGM of the transconductance circuit  24  increases. As a result, the net current flowing through the feedback resistor R 2  decreases since the transconductance circuit  24  takes the current flowing through the feedback resistor R 2  away when the input signal VI is larger than the reference voltage VREF. In this manner, the gain of the gain amplifier  22  decreases. 
         [0025]      FIG. 2  shows an implementation of the variable gain amplifying circuit  200 . A single-input single-output amplifier is shown as an example. However, the present invention is not limited to this configuration and many alternative configurations can be used, such as differential input amplifier architecture.  FIG. 4  shows a block diagram of a variable gain amplifying circuit  400  according to another embodiment of the present invention. Referring to  FIG. 4 , the variable gain amplifying circuit  400  includes a gain amplifier  42 , a transconductance circuit  24 ′, a dynamic biasing circuit  26 ′, a detecting circuit  48 , and a charge pump  49 . 
         [0026]    The gain amplifier  42  in this embodiment is a differential-input differential-output amplifier. Referring to  FIG. 4 , the gain amplifier  42  receives complementary analog input signals VIP and VIN to generate complementary analog output signals VOP and VON. In one embodiment of the present invention, the gain amplifier  42  is composed of a differential operational amplifier  424 , and four fixed resistors R 1 , R 2 , R 3 , and R 4 . If the resistance of the resistor R 1  is equal to that of the resistor R 2 , and the resistance of the resistor R 3  is equal to that of the resistor R 4 , a gain G of the gain amplifier  42  shown in  FIG. 4  without externally injecting current can be expressed as: 
         [0000]        G=R 3 /R 1  (2)
 
         [0027]    In this condition, when the input signal VIP is larger than the input signal VIN, the current flowing through the resistor R 3  is from left to right and the current flowing through the resistor R 4  is from right to left as indicated by solid lines. As the difference between the input signal VIP and the input signal VIN increases, the current flowing through the feedback resistors R 3  and R 4  also increases. 
         [0028]    Referring to  FIG. 4 , the gain of the gain amplifier  42  can be adjusted when the detecting circuit  48  detects whether the output signals of the gain amplifier  42  are not within a predetermined output range.  FIG. 5  illustrates a detailed circuit diagram of the variable gain amplifying circuit  400  shown in  FIG. 4  according to one embodiment of the present invention. Circuits having similar functions to those in  FIG. 2  are denoted by the same reference numerals and detailed descriptions thereof will be omitted. 
         [0029]    The detailed operation of the variable gain amplifying circuit  400  will be described below with respect to  FIG. 5 . Referring to  FIG. 5 , if the detecting circuit  48  detects whether the analog output signals VOP and VON of the gain amplifier  42  are not within the predetermined output range, complementary control signals UP and DN are generated and sent to the charge pump  49 . The Charge pump  49  is configured to generate the voltage VLEL in response to the status of the complementary control signals DN and UP. Referring to  FIG. 5 , the charge pump  49  includes an upper current source I 1 , a down current source I 2 , two switches SW 1  and SW 2  coupled in series between the upper current source I 1  and the down current source I 2 , and a capacitor C 1 . 
         [0030]    In response to the control signal UP, the charge pump  49  charges the capacitor C 1  to increase the voltage VLEL, and, in response to the control signal DN, the charge pump  49  discharges the capacitor C 1  to decrease the voltage VLEL. When the output signals VOP and VON of the gain amplifier  42  are not within the predetermined output range, the charge pump  49  charges the capacitor C 1  to increase the voltage VLEL. As the voltage VLEL increases, the PMOS transistor P 3  generates larger bias current to the transconductance circuit  24 , and thus the currents IJ 1  and IJ 2  increase. As a result, the net currents flowing through the feedback resistors R 3  and R 4  decrease. In this manner, the gain of the gain amplifier  42  decreases. Note that the analog output currents currents IJ 1  and IJ 2  of the transconductance circuit  24 ′ flow in opposite directions. With the decreased gain of the gain amplifier  42 , the output signals VOP and VON of the gain amplifier  42  are finally within the predetermined output range, and the voltage VLEL continues to maintains its value. 
         [0031]    Referring to  FIG. 2  and  FIG. 4 , the variable gain amplifying circuits  200  and  400  can be used in many communication and signal processing applications. For example, the variable gain amplifying circuit can be used as a volume controller for amplifying or attenuating an audio input signal.  FIG. 6  shows a block diagram of a variable gain amplifying circuit  600  in which the gain of the gain amplifying circuit  600  can be dynamically increased and decreased. Circuits having similar functions to those in  FIG. 4  are denoted by the same reference numerals and detailed descriptions thereof will be omitted. 
         [0032]    Referring to  FIG. 6 , the variable gain amplifying circuit  600  includes a gain amplifier  42 , a transconductance circuit  24 ′, a switch unit  64 , a switch unit  66 , a dynamic biasing circuit  26 ′, a detecting circuit  68 , and a charge pump  49 . The operation of the variable gain amplifying circuit  600  is described below. If the detecting circuit  68  detects whether the analog output signals VOP and VON of the gain amplifier  42  are not within a higher output range (e.g. 4V), the switches in the switch unit  64  turn on and the switches in the switch unit  66  turn off. Therefore, the transconductance circuit  24 ′ provides output currents IJ 1  and IJ 2  to the gain amplifier  42  in response to the difference between the input signal VIP and the input signal VIN. Thereafter, the charge pump  49  charges the capacitor C 1  to increase the voltage VLEL since the output signals VOP and VON of the gain amplifier  42  are not within the first preset output range. As the voltage VLEL increases, the net currents flowing through the feedback resistors R 3  and R 4  decrease. In this manner, the gain of the gain amplifying circuit  600  decreases. 
         [0033]    On the contrary, if the detecting circuit  68  detects whether the analog output signals VOP and VON of the gain amplifier  42  are within a lower output range (e.g. 0.5V), the switches in the switch unit  64  turn off and the switches in the switch unit  66  turn on. Therefore, the transconductance circuit  24 ′ provides output currents IJ 1  and IJ 2  to the gain amplifier  42  in response to the difference between the input signal VIN and the input signal VIP. In this condition, the voltage VLEL increases, so that the net currents flowing is through the feedback resistors R 3  and R 4  increase as shown in  FIG. 7 . Therefore, the gain of the gain amplifying circuit  600  increases. 
         [0034]      FIG. 8  shows a block diagram of a variable gain amplifying circuit  800  according to yet another embodiment of the present invention. Referring to  FIG. 8 , the variable gain amplifying circuit  800  includes a gain amplifier  42 , a transconductance circuit  24 ′, a dynamic biasing circuit  26 ′, a detecting circuit  72 , a switch SW, and a capacitor CH. The variable gain amplifying circuit  200  shown in  FIG. 2  and the variable gain amplifying circuit  400  shown in  FIG. 4  do not allow gain changes to be constrained to zero-crossings. Therefore, even though gain changes are ramped in small steps by injecting the small current IGM to the gain amplifier  22  or by injecting the small currents IJ 1  and IJ 2  to the gain amplifier  42 , such gain changes can occur during the analog input signal peaks, which results in audible transients. The audible transients are unacceptable in high quality audio circuits. To eliminate this problem, the variable gain amplifying circuit  800  further includes a detecting circuit to detect a zero crossing of the analog input signal or the analog output signal. 
         [0035]      FIG. 9  illustrates a detailed circuit diagram of the variable gain amplifying circuit  800  shown in  FIG. 8  according to one embodiment of the present invention. Circuits having similar functions to those in  FIG. 5  are denoted by the same reference numerals and detailed descriptions thereof will be omitted. Referring to  FIG. 9 , in this embodiment, the variable gain amplifying circuit  800  includes the detecting circuit  82  which receives the complementary analog output signals VOP and VON and generates a zero crossing output ZC upon detection of zero crossings of the output signals VOP and VON, i.e., the signal waveform changing from a positive to negative value or vice versa. Therefore, the switch SW closes only when the zero crossings of the output signals VOP and VON are detected, which causes a voltage VD generated at the capacitor CH is substantially equal to the input signal VLEL. Then, the dynamic biasing circuit  26 ′ generates the bias current to the transconductance circuit  24 ′ according to the voltage VD. As a result, the gain amplifier  42  amplifies the difference between the analog input signals VIP and VIN after the zero crossing point is detected, so that the audible transients can be limited to an acceptable range. 
         [0036]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention as recited in the following claims.