Abstract:
A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.

Description:
[0001]    This application is a division of U.S. application Ser. No. 14/715,730 filed May 19, 2015, the disclosure of which is incorporated by referenced herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to fin field effect transistor (finFET) devices, and more specifically, to silicide formation on replacement metal gate (RMG) finFET devices. 
         [0003]    Salicide (self-aligned silicide) refers to the formation of electrical contacts between the semiconductor device (finFET) and supporting interconnect structure. Typically, a thin refractive metal film reacts with silicon in active regions of the device to form a metal silicide (metal silicon alloy), and does not react with other materials such as insulators. The contact is regarded as self-aligned because it does not require lithographic patterning. The silicide between the contact and the semiconductor material (specifically, the source-drain region) lowers the resistance. 
       SUMMARY 
       [0004]    According to one embodiment of the present invention, a method of fabricating a fin field effect transistor (finFET) device includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers; epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers; forming a silicide above the RSD and along the outside walls of the sidewall spacers; and depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack. 
         [0005]    According to another embodiment, fin field effect transistor (finFET) device includes a gate stack between inner walls of sidewall spacers formed on a substrate, the gate stack comprising a high-k dielectric and a gate metal; an epitaxially grown raised source drain (RSD) on the substrate, the RSD adjacent to outer walls of the sidewall spacers; a silicide on a surface of the RSD and along a surface of the outer walls of the sidewall spacers above the RSD; and a contact metal above portions of the gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the gate stack. 
         [0006]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0008]      FIGS. 1-12  illustrate cross-sectional views of intermediate structures involved in finFET fabrication, in which: 
           [0009]      FIG. 1  shows an initial structure in a replacement gate process; 
           [0010]      FIG. 2  shows the result of epitaxially growing the raised source drain (RSD) and depositing a liner on the resulting structure; 
           [0011]      FIG. 3  is an intermediate structure resulting from the deposition of a flowable oxide over the liner; 
           [0012]      FIG. 4  shows the result of opening up the gate region using a CMP process; 
           [0013]      FIG. 5  illustrates the intermediate structure resulting from removal of the dummy gate stack; 
           [0014]      FIG. 6  shows the structure including the gate metal; 
           [0015]      FIG. 7  illustrates deposition of a dielectric cap over the gate metal; 
           [0016]      FIG. 8  shows the result of polishing the dielectric cap material; 
           [0017]      FIG. 9  illustrates the resulting structure when the flowable oxide is removed; 
           [0018]      FIG. 10  shows deposition of an HfO 2  layer conformally over the liner; 
           [0019]      FIG. 11  shows the structure that results from re-deposition of an oxide interlayer dielectric (ILD) followed by SAC RIE; and 
           [0020]      FIG. 12  is the structure that results from deposition of the contact metal and formation of silicide from the liner; 
           [0021]      FIGS. 13 and 14  illustrate additional processes that are specific to the pFET region of the finFET device, in which: 
           [0022]      FIG. 13  shows the structure that results from removal of the contact metal from the structure shown in  FIG. 12 , followed by deposition of a nickel-platinum alloy (NiPt); and 
           [0023]      FIG. 14  shows the structure in the pFET region resulting from re-deposition of the contact metal. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    As noted above, silicide or a metal silicon alloy between the contact and the source-drain region of a finFET device acts to lower resistance. When the PC pitch is scaled beyond 64 nanometers (nm), a self-aligned contact (SAC) is needed to avoid potential gate (PC) to contact (CA) shorts. However, because of the limitation in overlay control at sub 64 nm contacted poly pitch (CPP), the contact may land partially at the top of the epitaxially grown raised source drain (RSD), causing a further reduced contact area even for a given pitch scaling. Embodiments of the systems and methods detailed herein relate to silicide formation that increases the conductivity path and thereby further reduces resistance when compared with conventional finFET fabrication. Specifically, a pseudo-silicide silicide process uses a metal (e.g., titanium (Ti)) liner to form a u-shaped silicide (the silicide is on the side of the gate as well as on top of the RSD. This extends the contact area toward the top of the gate as further discussed below (e.g., on the order of 5 times) and alleviates the contact resistance increase that occurs due to scaling. 
         [0025]      FIGS. 1-12  illustrate cross-sectional views of intermediate structures involved in the finFET fabrication.  FIG. 1  illustrates an initial structure in the replacement gate process. A replacement gate stack comprising a dummy oxide  115 , dummy gate  120 , and hard mask  125  is patterned above a substrate  110 . Sidewall spacers  130  are formed through a nitride spacer deposition (e.g., silicon nitride (SiN)) and reactive ion etch (RIE) process. The fin cap or dummy oxide  115  is deposited by molecular layer deposition (MLD) followed by deposition of silicon (dummy gate  120 ).  FIG. 2  shows the result of completing two processes. A known process of epitaxially growing dual raised source drain (RSD)  135  is performed for fin merge. A liner  140  (e.g., Ti) is then conformally deposited, as shown in  FIG. 2 . This liner  140  may be 10 to 15 nanometers (nm) in thickness, for example, and serves as the material that forms a salicide, as described in further detail below (see e.g.,  FIG. 12 ). A flowable oxide  145  is deposited over the liner  140  to result in the structure shown in  FIG. 3 . A high density plasma (HDP) oxide and nitride may be deposited followed by a chemical mechanical planarization (CMP) to open up the gate region and result in the structure shown in  FIG. 4 . The nitride may be deposited using an in-situ radical assisted deposition (iRAD) tool, for example. The CMP process may be a known poly-open CMP process. 
         [0026]      FIG. 5  illustrates the intermediate structure resulting from removal of the dummy gate stack ( 115 ,  120 ,  125 ). A poly-silicon RIE is performed to remove the dummy gate  120  followed by chemical oxide removal (COR) to remove the dummy oxide  115 . A high-k preclean may then be performed.  FIG. 6  shows the structure that results from a replacement metal gate fill process as known in the art, including the formation of an interfacial oxide layer (not specifically shown), the deposition of a high-k dielectric layer  155  (e.g., hafnium oxide (HfO 2 )), one or more workfunction metals and barrier layers (not specifically shown), and a gate metal layer  150  (e.g., tungsten W). The high-k dielectric layer  155  may alternately cover the sidewalls (inside of sidewall spacers  130 ), as well. As shown in  FIG. 6 , additional etch may be used to remove the high-k dielectric layer  155  from the sidewalls prior to deposition of the gate metal layer  150 . The gate metal  150  is etched back and a cap material  160  (e.g., silicon nitride (SiN)) is deposited as shown in  FIG. 7 . The cap material  160  forms a dielectric cap for the self-aligned contact (SAC) process. The dielectric cap material  160  is then polished to result in the structure shown in  FIG. 8 . An oxide deglaze process is used to remove the flowable oxide  145  (the interlayer dielectric between the gates) and expose the Ti liner  140  to result in the structure shown in  FIG. 9 . An HfO 2  layer  165  is then deposited conformally over the liner  140  in the structure of  FIG. 10  to act as a self-aligned contact etch stop layer. 
         [0027]      FIG. 11  shows the structure that results from re-deposition of an oxide interlayer dielectric (ILD)  170  followed by SAC RIE to define the contact openings. This RIE process removes exposed portions of the HfO 2  layer  165  while leaving the liner  140 .  FIG. 12  is the structure that results from deposition of the contact metal  180  (e.g., W) in the etched portions of the ILD  170 . A high-pressure deuterium anneal (HPD2) at, for example, approximately 400 degrees Celsius for approximately 30 minutes may be performed following the contact metal  180  deposition. This forms silicide  175  (e.g., Ti silicide) from the liner  140  (e.g., Ti). Specifically, based on the silicon in the RSD  135  below the liner  140  and the silicon in the sidewall spacers  130 , silicide  175  is formed above the RSD  135  as well as along portions of the sidewall spacers  130  that are above the RSD  135 , as shown in  FIG. 12 . Because of the processes discussed herein that facilitate retaining the liner  140  at both the sidewall of the gate as well as the bottom of the contact, the subsequently formed silicide  175  contact area with the contact metal  180  is increased and contact resistance is further decreased from that of conventional devices. 
         [0028]    A complimentary metal-oxide-semiconductor (CMOS) device includes complementary and symmetrical pairs of n-type and p-type metal-oxide-semiconductor field effect transistors (MOSFETs). Thus, the finFET device may include pFET and nFET regions. The nFET and pFET regions may be processed in the same way (and as shown in  FIGS. 1-12 ).  FIGS. 13 and 14  illustrate additional processes that are specific to the pFET region of the finFET device.  FIG. 13  shows the structure that results from removal of the contact metal  180  from the structure shown in  FIG. 12 , followed by deposition of a nickel-platinum alloy (NiPt)  185 . The NiPt  185  is formed as shown in  FIG. 13  according to known processes of patterning using a hard mask layer. The NiPt  185  has a lower contact barrier than the liner  140  (e.g., Ti) and, thus, provides lower resistance in the pFET region. The contact metal  180  is then re-deposited on the NiPt  185 . Thus, the finFET device includes an nFET region according to  FIG. 12  and a pFET region according to  FIG. 14 . In an alternate embodiment, rather than as additional processes, the processes of  FIGS. 13 and 14  may be performed as alternate processes to those shown in  FIGS. 11 and 12  in the pFET region. 
         [0029]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0030]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
         [0031]    The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0032]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described. 
         [0033]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.