Abstract:
An information handling system includes a buck converter, having a synchronous switch, to supply power to an electrical load. A first inductor is placed in series with the synchronous switch, and a second inductor is inductively coupled to the first inductor. A switched path recovers energy stored in the first inductor, via the second inductor, when the synchronous switch is open.

Description:
BACKGROUND  
       [0001]     The description herein relates to information handling systems and power converters for such systems.  
         [0002]     As the value and use of information continue to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system (“IHS”) generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.  
         [0003]     Most information handling systems include one or more power converters to convert power at a supply voltage (AC or DC) to power at a voltage expected by a particular electronic system component or by a group of such components.  
       SUMMARY  
       [0004]     A power converter for an information handling system includes a buck converter comprising a synchronous switch. A first inductor is inserted in series with the synchronous switch. A second inductor is inductively coupled to the first inductor. A switched path is provided to recover energy stored in the first inductor via the second inductor when the synchronous switch is open.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  is a block diagram illustrating an embodiment of an information handling system.  
         [0006]      FIGS. 2-5  are circuit diagrams of buck power converters according to illustrative embodiments, e.g., for use in the information handling system of  FIG. 1 .  
     
    
     DETAILED DESCRIPTION  
       [0007]     For purposes of this disclosure, an information handling system (“IHS”) includes any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.  
         [0008]      FIG. 1  is a block diagram of an information handling system (“IHS”), according to an illustrative embodiment. The IHS  100  includes a system board  102 . The system board  102  includes a processor  105  such as an Intel Pentium series processor or one of many other processors currently available. An Intel Hub Architecture (IHA) chipset  110  provides the IHS system  100  with graphics/memory controller hub functions and I/O functions. More specifically, the IHA chipset  110  acts as a host controller that communicates with a graphics controller  115  coupled thereto. A display  120  is coupled to the graphics controller  115 . The chipset  110  further acts as a controller for a main memory  125 , which is coupled thereto. The chipset  110  also acts as an I/O controller hub (ICH) which performs I/O functions. A super input/output (I/O) controller  130  is coupled to the chipset  110  to provide communications between the chipset  110  and input devices  135  such as a mouse, keyboard, and tablet, for example. A universal serial bus (USB)  140  is coupled to the chipset  110  to facilitate the connection of peripheral devices to system  100 . System basic input-output system (BIOS)  145  is coupled to the chipset  110  as shown. The BIOS  145  is stored in CMOS or FLASH memory so that it is nonvolatile.  
         [0009]     A local area network (LAN) controller  150 , alternatively called a network interface controller (NIC), is coupled to the chipset  110  to facilitate connection of the system  100  to other IHSs. Media drive controller  155  is coupled to the chipset  110  so that devices such as media drives  160  can be connected to the chipset  110  and the processor  105 . Devices that can be coupled to the media drive controller  155  include CD-ROM drives, DVD drives, hard disk drives, and other fixed or removable media drives. An expansion bus  170 , such as a peripheral component interconnect (PCI) bus, PCI express bus, serial advanced technology attachment (SATA) bus or other bus is coupled to the chipset  110  as shown. The expansion bus  170  includes one or more expansion slots (not shown) for receiving expansion cards which provide the IHS  100  with additional functionality.  
         [0010]     Not all information handling systems include each of the components shown in  FIG. 1 , and other components not shown may exist. As can be appreciated, however, many systems are expandable, and include or can include a variety of components. Information handling systems generally provide one or more DC power sources to serve the needs of the various components at one or more supply voltages. Power sources generally comprise a power converter that accepts AC and/or DC input power at a first voltage, and supplies DC output power at a second voltage required by its load.  
         [0011]     Power converters range in size. Large converters may supply standard voltages to bus-mounted components, drives, circuit boards, etc. Small power converters may power a single device package and be integral to that package or placed in close proximity to that package.  
         [0012]      FIG. 2  illustrates a buck power converter  200  coupled between a power supply  210  and a load comprising a resistive load R L  and a parallel capacitance C L . The power supply supplies power at a nominal voltage V IN . The load requires power supplied at a component supply voltage V OUT    
         [0013]     The power converter comprises an output inductor L OUT , a control MOSFET switch M 1 , a synchronous MOSFET switch M 2 , a control circuit  220 , two coupled reverse recovery inductors L RR1  and L RR2 , and a diode rectifier D 1 . Inductor L OUT  and switches M 1 , M 2  are arranged in a buck converter configuration, with inductor L RR1  added to the configuration. Inductor L OUT  is coupled between the power converter output and a node V 1 . The drain/source current path of control switch M 1  is coupled between power supply  210  and node V 1 . The drain/source current path of synchronous switch M 2 , in series with inductor L RR1 , is coupled between node V 1  and ground. The control circuit senses the voltage V OUT , and supplies alternating signals to the gates of M 1  and M 2 .  
         [0014]     Inductor L RR2  and diode rectifier D 1  are connected in series between the power supply input V IN  and ground.  
         [0015]     Control circuit  220  varies the average current I OUT  passing through L OUT , and thereby controls V OUT , by adjusting a duty cycle (the ratio of the time M 1  is on to the time period between successive M 1  activations). Control circuit  220  alternates gate signals V G1  and V G2  at a design frequency, varying the relative time each gate signal is asserted, to achieve this control. During a first portion of each cycle, gate signal V G1  is driven high and gate signal V G2  is driven low, turning on M 1  and turning off M 2 . This allows node V 1  to approach V IN , and a current I 1  flows from power supply  210  through M 1 , and then through inductor L OUT  as power converter output current I OUT . For the second portion of each cycle, gate signal V G1  is driven low and gate signal V G2  is driven high, turning off M 1  and turning on M 2 . This allows node V 1  to approach ground potential, as a current I 2  flows from ground through M 2  and L RR1 , and then through inductor L OUT  as power converter output current I OUT  Note that I OUT  ramps upward during the first portion of each cycle, and downward during the second portion of each cycle, but cannot change instantaneously due to the inductance of L OUT .  
         [0016]     Were inductor L RR1  not present, several potential problems could exist. First, should the control switch M 1  be turned on while the synchronous switch M 2  is still conducting, a short circuit path from power supply  210  to ground would be momentarily present, with the potential to cause damage to the switches. Second, the reverse recovery current observed in the synchronous switch M 2  during turn-off can also damage M 1  should the reverse recovery current spike sufficiently.  
         [0017]     In one embodiment, L RR1  is much smaller than L OUT , and sized to protect M 1  and M 2  from brief but large transient currents at the switchover times of the converter. Should M 1  be turned on while M 2  is still conducting, L RR1  initially resists a rapid rate of change in current I 2 , thus preventing a potentially large short-circuit current during switchover. Inductor L RR1  also reduces the rate of change in current I 2  during the reverse recovery time of switch M 2 , thereby reducing the potential for damage to M 1  due to a high reverse recovery peak current. In one potential mode of operation, V G1  can thus be timed to turn on M 1  earlier with reduced potential for circuit damage.  
         [0018]     Inductor L RR2  and diode rectifier D 1  recover energy from inductor L RR1  back to power supply  210  during the off time of synchronous switch M 2 . During the on time of switch M 2 , rectifier D 1  is reverse biased, blocking current I 3 . As M 1  turns on and drives node V 1  to a voltage V IN , and M 2  turns off, energy remains in L RR1  due to current I 2 . Under these conditions, the voltage developed across L RR2  can rise high enough to forward bias D 1  momentarily, allowing L RR2  to remove the energy stored in L RR1  back to the power supply. As the energy stored in the coupled inductors is removed, D 1  once more becomes reverse biased.  
         [0019]      FIG. 3  shows another buck power converter  300 . Instead of connecting the cathode of D 1  back to voltage V IN , converter  300  connects the cathode of D 1  to a dissipation circuit comprising a resistance R D  and a capacitance C D  connected in parallel. When M 2  turns off, energy remaining in L RR1  can forward bias D 1 , allowing L RR2  to remove the energy stored in L RR1 .  
         [0020]      FIG. 4  shows another buck power converter  400 . Instead of connecting the cathode of D 1  back to voltage V IN  or to a dissipation circuit, converter  400  connects the cathode of D 1  to V OUT . When M 2  turns off, energy remaining in L RR1  can forward bias D 1 , allowing L RR2  to remove the energy stored in L RR1  to the load.  
         [0021]      FIG. 5  shows another buck power converter  500 . Instead of connecting the cathode of D 1  back to voltage V IN  or to a dissipation circuit or to the load, converter  500  connects the cathode of D 1  to another power supply  510  at a voltage V P . When M 2  turns off, energy remaining in L RR1  can forward bias D 1 , allowing L RR2  to remove the energy stored in L RR1  to the power supply  510 . In systems using more than one power supply, power supply  510  can advantageously be selected as a power supply less sensitive to fluctuation due to size or the type of load it supports.  
         [0022]     Those skilled in the art will recognize that a variety of circuit designs are available to implement a power converter using the teachings described herein. For instance, although a buck converter design is shown, similar principles can be applied to a boost power converter or buck/boost power converter. The synchronous switch can be a simple rectifier in some designs; in general, MOSFETs are but one example of the possible switch types.  
         [0023]     Although illustrative embodiments have been shown and described, a wide range of other modification, change and substitution is contemplated in the foregoing disclosure. Also, in some instances, some features of the embodiments may be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be constructed broadly and in manner consistent with the scope of the embodiments disclosed herein.