Abstract:
Owing to the property of bidirectional conduction under the saturation mode, synchronous rectifiers in conventional power converters usually suffer from a reverse current under light loads or a shoot-through current under heavy loads. The reverse current may degrade the converter efficiency and the shoot-through current may damage synchronous rectifiers. The present invention discloses a unidirectional metal oxide semiconductor field effect transistor (UMOS), which comprises a metal oxide semiconductor field effect transistor (MOS), a current detection circuit and a fast turn-off circuit. The current detection circuit detects the direction of the current flowing through the MOS. When a forward current is detected, the fast turn-off circuit is disabled and the channel of the MOS can be formed. When a reverse current is detected, the fast turn-off circuit is enabled and the channel of the MOS cannot be formed. This UMOS can be applied, but not limited, to synchronous rectifiers to detect the occurrence of a reverse current or a shoot-through current and fast turn off the channel of the MOSFET.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention discloses a unidirectional MOSFET and applications thereof. 
         [0003]    2. Description of the Related Art 
         [0004]    The N-channel MOSFET (NMOS) is often used as self-driven synchronous rectifiers to realize power converters with low cost and high efficiency. When used as a power switch, an NMOS has two operation modes: (1) cutoff mode: when v GS (t)&lt;V GS(th) , the channel cannot be formed; i D (t) cannot flow through the channel; (2) saturation mode: when v GS (t)&gt;V GS(th) , the channel can be formed; i D (t) can flow from drain to source or from source to drain through the channel, where v GS (t) is the gate-source voltage; V GS(th)  is the gate-source threshold voltage; and i D (t) is the drain current. 
         [0005]    Due to the property of bidirectional conduction under the saturation mode, a synchronous rectifier realized with an NMOS usually suffers from a reverse current under light loads or a shoot-through current under heavy loads. The reverse current may degrade the converter efficiency and the shoot-through current may damage the synchronous rectifier. To illustrate the cause and effect of the shoot-through current, a flyback converter with a self-driven synchronous rectifier is taken as an example. If the flyback converter operates under the continuous conduction mode (CCM), and a cross conduction exists between the primary power switch and the secondary self-driven synchronous rectifier, the drain-source voltage divided by the small channel resistance will lead to a huge shoot-through current, which may damage the synchronous rectifier. 
         [0006]    To solve the above problems, the present invention discloses a unidirectional MOSFET and its applications in synchronous rectifiers to detect the occurrence of a reverse current or a shoot-through current and fast turn off the channel of the MOSFET. 
       SUMMARY OF THE INVENTION 
       [0007]    A unidirectional MOSFET includes a MOSFET, a current detection circuit and a fast turn-off circuit. The MOSFET may be an N-channel MOSFET or a P-channel MOSFET. The current detection circuit detects the direction of the current flowing through the MOSFET. When a forward current is detected, the fast turn-off circuit is disabled so that the channel of the MOSFET can be formed. When a reverse current is detected, the fast turn-off circuit is enabled so that the channel of the MOSFET cannot be formed. Such a unidirectional MOSFET may be but not limited to applications in synchronous rectifiers to detect the occurrence of a reverse current or a shoot-through current and fast turn off the channel of the MOSFET. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The objectives, technical contents and characteristics of the present invention can be more fully understood by reading the detailed description of the preferred embodiments in company with the attached drawings, wherein: 
           [0009]      FIG. 1A  and  FIG. 1B  are the functional block diagrams of unidirectional MOSFETs. 
           [0010]      FIG. 2A  and  FIG. 2B  are respectively the actual circuit diagrams corresponding to  FIG. 1A  and  FIG. 1B . 
           [0011]      FIG. 3  is the equivalent circuit symbol of the unidirectional MOSFET. 
           [0012]      FIG. 4A  and  FIG. 4B  are circuit diagrams of flyback converters with a self-driven synchronous rectifier realized with a unidirectional MOSFET. 
           [0013]      FIG. 5A  and  FIG. 5B  are respectively circuit diagrams of a forward converter with a self-driven forward synchronous rectifier and a self-driven freewheeling synchronous rectifier, each of which is realized with a unidirectional MOSFET. 
           [0014]      FIG. 6  is the circuit diagram of a half-bridge LLC resonant converter with self-driven synchronous rectifiers, each of which is realized with a unidirectional MOSFET. 
           [0015]      FIG. 7  and  FIG. 8  are respectively the timing diagrams of the gate-source voltage of the primary switch transistor, the primary current, the secondary current and the gate-source voltage of the secondary self-driven synchronous rectifier under the discontinuous conduction mode and under the continuous conduction mode. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    As shown in  FIG. 1A  and  FIG. 1B , a unidirectional MOSFET (UMOS) includes a pan-gate G, a pan-drain D, a pan-source S, a MOSFET M, a current detection circuit  200 , and a fast turn-off circuit  100 . The MOSFET M includes a gate, a drain and a source. The current detection circuit  200  includes a first input, a second input and an output. The fast turn-off circuit  100  includes a first input, a second input, a first output and a second output. 
         [0017]    The MOSFET M may be an N-channel MOSFET (NMOS) or a P-channel MOSFET (PMOS). For the convenience of illustration, the MOSEFT M is assumed to be an NMOS herein. However, it is emphatically noted that the MOSFET M in the present invention can be but not limited to an NMOS. 
         [0018]    The current detection circuit  200  is used for detecting the direction of the current flowing through the MOSFET M. The detection method may be a pan-source detection ( FIG. 1A ) or a pan-drain detection ( FIG. 1B ). In  FIG. 1A , the first input and the second input of the current detection circuit  200  are respectively connected to the pan-source S and the source of the MOSFET M. In  FIG. 1B , the first input and the second input of the current detection circuit  200  are respectively connected to the drain of the MOSFET M and the pan-drain D. 
         [0019]    The fast turn-off circuit  100  receives an output signal from the current detection circuit  200  and a control signal from an external driving circuit to turn on or turn off the channel of the MOSFET M. The first input, the second input, the first output and the second output of the fast turn-off circuit  100  are respectively connected to the output of the current detection circuit  200 , the pan-gate G, the gate and the source of the MOSFET M. 
         [0020]    The channel between the drain and the source of the MOSFET M is controlled by the voltage difference between the pan-gate G and the pan-source S, the output signal of the current detection circuit  200  and the output signal of the fast turn-off circuit  100 . When a forward current (from the pan-source S to the pan-drain D) is detected, the fast turn-off circuit  100  is disabled; the channel of the MOSFET M can be formed. When a reverse current (from the pan-drain D to the pan-source S) is detected, the fast turn-off circuit  100  is enabled; the channel of the MOSFET M cannot be formed. 
         [0021]    Moreover, an enhanced UMOS (e-UMOS), which includes a UMOS and an extra diode D* U  with a lower forward voltage drop, whose anode and cathode are respectively connected to the pan-source S and the pan-drain D (NMOS) or the pan-drain D and the pan-source S (PMOS), can further reduce the body diode conduction loss of the MOSFET M in specific applications. 
         [0022]      FIG. 2A  and  FIG. 2B , where an NMOS is used for the MOSFET M, are two embodiments respectively corresponding to  FIG. 1A  and  FIG. 1B . The current detection circuit  200  is realized by a current transformer CT and a diode D CT . The current transformer CT includes a primary winding N P  and a secondary winding N S ; black dots denote that the dotted terminals are of the same polarity. For the convenience of illustration, the black-dotted terminal and the other terminal are respectively called a positive pole and a negative pole. The first input, the second input and the output of the current detection circuit  200  are respectively the positive pole of the primary winding N P , the negative pole of the primary winding N P  and the negative pole of the secondary winding N S . The primary winding N P  and the MOSFET M are connected in series to detect the direction of the current flowing through the MOSFET M. In  FIG. 2A , the positive and negative poles of the primary winding N P  are respectively connected to the pan-source S and the source of the MOSFET M. In  FIG. 2B , the positive and negative poles of the primary winding N P  are respectively connected to the drain of the MOSFET M and the pan-drain D. The secondary winding N S  and the diode D CT  are connected in parallel to disable or enable the fast turn-off circuit  100 . The positive and negative poles of the secondary winding N S  are respectively connected to the anode and cathode of the diode D CT . 
         [0023]    The fast turn-off circuit  100  includes a Darlington transistor DL, a resistor R B  and a resistor R C . The Darlington transistor DL is equivalent to two NPN bipolar junction transistors in cascade. The base B of the Darlington transistor DL is connected to one terminal of the base resistor R B . The collector C of the Darlington transistor DL is connected to one terminal of the collector resistor R C  and the gate of the MOSFET M. The emitter E of the Darlington transistor DL is connected to the anode of the diode D CT , the positive pole of the secondary winding N S  and the source of the MOSFET M. The other terminal of the base resistor R B  is connected to the cathode of the diode D CT  and the negative pole of the secondary winding N S . The other terminal of the collector resistor R C  is connected to the pan-gate G. The first input, the second input, the first output, and the second output of the fast turn-off circuit  100  are respectively the other terminal of the base resistor R B , the other terminal of the collector resistor R C , the collector C of the Darlington transistor DL and the emitter E of the Darlington transistor DL. 
         [0024]    If the current detected by the current transformer CT is i D (t), the discharging current of the Darlington transistor DL is 
         [0000]    
       
         
           
             
               
                 
                   h 
                   FE 
                 
                  
                 
                   
                     i 
                     D 
                   
                    
                   
                     ( 
                     t 
                     ) 
                   
                 
               
               n 
             
             , 
           
         
       
     
         [0000]    where h FE =βp 2 , with β being the current gain of an individual NPN bipolar junction transistor, is the current gain of the Darlington transistor DL, and 
         [0000]    
       
         
           
             n 
             = 
             
               
                 N 
                 S 
               
               
                 N 
                 P 
               
             
           
         
       
     
         [0000]    is the secondary-to-primary turns ratio of the current transformer CT. Assuming thatn=50, i B(sat) =0.1 mA and h FE =10000, the maximum allowable reverse current or shoot-through current is i D(st),max =0.5 μA. In other words, a very small reverse current is enough to saturate the Darlington transistor DL and cut off the channel of the MOSFET M. 
         [0025]    When a forward current i D (t) flows into the positive pole of the primary winding N P , a current 
         [0000]    
       
         
           
             
               
                 i 
                 D 
               
                
               
                 ( 
                 t 
                 ) 
               
             
             n 
           
         
       
     
         [0000]    induced by the secondary winding N S  flows out of the positive pole of the secondary winding N S  and conducts the diode D CT ; the Darlington transistor DL is reverse-biased and turned off; the channel of the MOSFET M can be formed by v GS (t)≧V GS(th ); i D (t) can flow from source to drain through the channel of the MOSFET M. 
         [0026]    When a reverse current i D (t) flows out of the positive pole of 
         [0000]    the primary winding N P , a current 
         [0000]    
       
         
           
             
               
                 i 
                 D 
               
                
               
                 ( 
                 t 
                 ) 
               
             
             n 
           
         
       
     
         [0000]    induced by the secondary winding N S  flows into the positive pole of the secondary winding N S  and saturates the Darlington transistor DL; the diode D CT  is reverse-biased and turned off; the gate-source voltage of the MOSFET M is equal to the collector-emitter saturation voltage of the Darlington transistor DL and is less than the gate-source threshold voltage of the MOSFET M, i.e. v GS =V CE(sat) &lt;V GS(th) ; the channel of the MOSFET M cannot be formed; i D (t) cannot flow from drain to source through the channel of the MOSFET M. 
         [0027]    To simplify the following circuit diagrams, the UMOS is denoted by an equivalent circuit symbol shown in  FIG. 3 . The equivalent circuit symbol includes the symbols of a MOSFET M and a virtual diode VD. The symbol of the MOSFET M represents that the channel of the UMOS is controlled by a voltage difference between the pan-gate G and the pan-source S; the symbol of the virtual diode VD symbolizes that the direction of the drain current is limited by the polarity of the virtual diode VD. In other words, the UMOS has the property of unidirectional conduction and may be but not limited to applications in synchronous rectifiers to detect the occurrence of a reverse current or a shoot-through current and fast turn off the channel of the MOSFET M. 
         [0028]    Below, some conventional power converters are taken as examples to illustrate the applications of a UMOS in synchronous rectifiers.  FIG. 4A  and  FIG. 4B  are the circuit diagrams of flyback converters with a self-driven synchronous rectifier U R  realized with a UMOS.  FIG. 5A  and  FIG. 5B  are respectively the circuit diagrams of a forward converter with a self-driven forward synchronous rectifier U f  and a self-driven freewheeling synchronous rectifier U w , each of which is realized with a UMOS. 
         [0029]      FIG. 6  is the circuit diagram of a half-bridge LLC resonant converter with self-driven synchronous rectifiers U u  and U d , each of which is realized with a UMOS. Because the UMOS can detect the occurrence of a reverse current or a shoot-through current and fast turn off the channel of the MOSFET, the half-bridge LLC resonant converter with self-driven synchronous rectifiers realized with a UMOS does not need the constraint of the switching frequency being higher than the resonant frequency. In other words, the switching frequency may be lower than, equal to or higher than the resonant frequency. 
         [0030]    For simplification, the virtue of a UMOS on self-driven synchronous rectifiers is illustrated in detail with  FIG. 4B , where the flyback converter may operate under Discontinuous Conduction Mode (DCM) or Continuous Conduction Mode (CCM). 
       Discontinuous Conduction Mode (DCM) 
       [0031]    A timing diagram is shown in  FIG. 7 , where a switching period can be divided into three intervals: on-interval 0≦t≦T on , reset-interval T o ≦t&lt;T on +T reset  and dead-interval T on +T reset ≦t&lt;T s ; v GS   M     p   (t) and v GS   U     R   (t) are respectively the gate-source voltage of the primary switch transistor and the secondary synchronous rectifier; i p (t) and i s (t) are respectively the primary and the secondary currents. 
         [0032]    Table I lists the on and off states of the primary switch transistor M P , diodes D 1  and D 2 , PNP bipolar transistor Q 1  as well as the secondary synchronous rectifier U R . 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                 TABLE I 
               
               
                   
               
               
                 Interval 
                 M p   
                 D 1   
                 D 2   
                 Q 1   
                 U R   
               
               
                   
               
             
             
               
                 0 ≦ t &lt; T on   
                 off→on 
                 off 
                 off 
                 off 
                 off 
               
               
                 T on  ≦ t &lt; T on  + T reset   
                 on→off 
                 on 
                 on 
                 off 
                 off→on 
               
               
                 T on  + T reset  ≦ t &lt; T s   
                 off 
                 off 
                 off 
                 on→off 
                 on→off 
               
               
                   
               
             
          
         
       
     
         [0033]    The second row in Table I shows that at t=T on  a cross conduction may exist between the primary switch transistor M p  and the secondary synchronous rectifier U R , a possibility to be discussed further. When the primary switch transistor M p  transits from on to off, the secondary synchronous rectifier U R  is still off. After the secondary current i s (t) flows through the body diode of the secondary synchronous rectifier U R , the diodes D 1  and D 2 , and the secondary synchronous rectifier U R  begin to conduct. Because the secondary synchronous rectifier U R  transits from off to on after the primary switch transistor M p  turns off, at t=T on  no cross conduction exists between the primary switch transistor M p  and the secondary synchronous rectifier U R . 
       Continuous Conduction Mode (CCM) 
       [0034]    A timing diagram is shown in  FIG. 8 , where a switching period can be divided into two intervals: on-interval 0≦t≦T on  and off-interval T on ≦t&lt;T on +T s . 
         [0035]    Table II lists the on and off states of the primary switch transistor M p , the diodes D 1  and D 2 , the PNP bipolar junction transistor Q 1  as well as the secondary synchronous rectifier U R . 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                 TABLE II 
               
               
                   
               
               
                 Interval 
                 M p   
                 D 1   
                 D 2   
                 Q 1   
                 U R   
               
               
                   
               
             
             
               
                 0 ≦ t &lt; T on   
                 off→on 
                 off 
                 off 
                 on→off 
                 on→off 
               
               
                 T on  ≦ t &lt; T on  + T s   
                 on→off 
                 on 
                 on 
                 off 
                 off→on 
               
               
                   
               
             
          
         
       
     
         [0036]    Because the second row in Table II is similar to the second row in Table I, at t=T on  no cross conduction exists between the primary switch transistor M p  and the secondary synchronous rectifier U R . However, the first row in Table II shows that at t=0 a cross conduction may exist between the primary switch transistor M p  and the secondary synchronous rectifier U R , a possibility to be discussed further. When the primary switch transistor M p  transits from off to on, the secondary synchronous rectifier U R  is still on. After the diodes D 1  and D 2  turn off, the secondary synchronous rectifier U R  transits from on to off. Because the secondary synchronous rectifier U R  transits from on to off after the primary switch transistor M p  turns on, at t=0 a cross conduction exists between the primary switch transistor M p  and the secondary synchronous rectifier U R . If a common NMOS is used as the self-driven synchronous rectifier, a huge shoot-through current 
         [0000]    
       
         
           
             
               i 
               
                 D 
                  
                 
                   ( 
                   st 
                   ) 
                 
               
             
             = 
             
               
                 
                   
                     
                       V 
                       i 
                     
                      
                     
                       N 
                       s 
                     
                   
                   
                     N 
                     p 
                   
                 
                 + 
                 
                   V 
                   o 
                 
               
               
                 R 
                 
                   DS 
                    
                   
                     ( 
                     on 
                     ) 
                   
                 
               
             
           
         
       
     
         [0000]    will flow from drain to source through the channel, where V i  is the input voltage; N p  is the number of turns of the primary winding; N s  is the number of turns of the secondary winding; V o  is the output voltage; and R DS(on)  is the small channel resistance. As a result, a shoot-through power dissipation 
         [0000]    
       
         
           
             
               P 
               
                 d 
                  
                 
                   ( 
                   st 
                   ) 
                 
               
             
             = 
             
               
                 
                   i 
                   
                     D 
                      
                     
                       ( 
                       st 
                       ) 
                     
                   
                   2 
                 
                  
                 
                   R 
                   
                     DS 
                      
                     
                       ( 
                       on 
                       ) 
                     
                   
                 
                  
                 
                   T 
                   CC 
                 
               
               
                 T 
                 s 
               
             
           
         
       
     
         [0000]    may damage the NMOS, where T CC  is the cross conduction interval and T S  is the switching period. In view of this, the present invention proposes a UMOS to be used as the self-driven synchronous rectifier. Since the current detection circuit of a UMOS can immediately detect the occurrence of a tiny shoot-through current and turn off the channel to stop the shoot-through current, the UMOS can exempt itself from being damaged by a large shoot-through current. 
         [0037]    During the delay interval T delay  when the primary switch transistor M p  transits from on to off and the secondary synchronous rectifier U R  transits from off to on, the secondary current i s (t) flows through the body diode of the MOSFET M. Since the body diode has a higher forward voltage drop and the secondary current i s (t) approaches its peak value, the UMOS has a larger body diode conduction loss in this specific application. If the UMOS is replaced with an e-UMOS, the diode D* U  can bypass the body diode to further reduce the body diode conduction loss. 
         [0038]    It is emphatically noted that applications of a UMOS/e-UMOS in synchronous rectifiers can be but not limited to flyback converters, forward converters and half-bridge LLC resonant converters. 
         [0039]    While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.