Abstract:
A biasing circuit is used to provide low distortion and high efficiency operation of a microwave power amplifier. The biasing circuit utilizes the nonlinear rectified current of a microwave diode or transistor for biasing the amplifying transistor self-adaptively. The biasing current not only reduces the DC bias power during low-power operation and increases self-adaptively during high-power operation, but also manipulates the intermodulation distortion minimum dynamically. Meanwhile, the biasing circuit distorts the input signals with positive gain and negative phase deviations. Therefore, the average power efficiency of the operation is enhanced, the linearity of the input-output characteristic is improved and the radiated level of adjacent channel power is suppressed.

Description:
FIELD OF THE INVENTION 
     This invention relates to a novel bias network for a microwave power amplifier, and to methods and circuits for enhancing the average power efficiency and improving the linearity of the Class A microwave power amplifier. 
     BACKGROUND TO THE INVENTION 
     Microwave power amplifiers, boosting the radio signal to a sufficient power level for transmission through the air interface from the transmitter to the receiver, are important components in wireless communications systems. They are the circuits that convert DC power into RF/microwave output power and in addition power amplifiers consume a significant amount of power, especially in portable devices. Inherently, the microwave transistors of the power amplifiers are nonlinear. Intermodulation distortion (IMD) is a common problem suffered from high-efficiency amplification since the amplifier is operating within its nonlinear region. Its products cause both in-band distortion and out-of-band emission. To keep the adjacent channel interference tightly within the specification of the systems, backing-off the output power of the amplifier is the simplest solution. However, this results in degradation of efficiency. Therefore, linearity and efficiency are highly desirable objectives of power amplifier designs. 
     In future wireless communications systems, non-constant envelope modulation schemes, such as M-PSK (Multiple Phase Shift Keying) and QAM (Quadrature Amplitude Modulation), are anticipated to accommodate higher channel capacity and better bandwidth efficiency in wireless transmission. The information is carried in such digital modulations by both amplitude and phase of the RF signals, therefore, highly linear amplification is desirable to meet the stringent requirements on both transmitted spectrum emission and received signal-to-noise ratio. Class A and Class AB power amplifiers are potential candidates, but they suffer the problem of low average power efficiency. Therefore, low distortion and high average power efficiency are the key issues for the next-generation power amplifier design. 
     In view of compensating the tradeoffs between linearity and efficiency of power amplifiers, various linearizing and bias controlling circuitries have been explored. 
     System-level linearization techniques, like feedforward, digital predistortion and even-order signals injection, provide excellent suppressions of spectral regrowth. However, these techniques require complicated and expensive circuitry, additional power consumption and large occupation of printed circuit broad area. As a result, only base station applications can benefit from these techniques. 
     Circuit-level techniques utilize the nonlinear characteristic of microwave diodes or transistors, which compensate for the nonlinear variation of the internal components of the amplifying transistors or distort the signals before or after the amplifying transistors, provide a compact and low-cost approach for the handset applications. Examples of such prior art, utilizing a single microwave diode, are shown in  FIG. 1 ,  FIG. 2  and  FIG. 3 . 
     The methodology of the approach in  FIG. 1  is to compensate for the nonlinear capacitor, typically the base-collector capacitor (C BC ) of bipolar transistors and the gate-source capacitor (C GS ) of field-effect transistors for compensating the phase distortion (amplitude modulation to phase modulation distortion) of the amplifier. The methodology utilizes the nonlinear capacitor of a reverse-biased microwave diode (i.e. V L  is positive) to provide a substantially constant of resultant capacitance at the input terminal of the amplifying transistor. 
     The methodology of the approach in  FIG. 2  is to compensate the nonlinear transconductance (g m ) of bipolar transistors for compensating the gain compression of the amplifier. A nonlinear rectified current is present when there is RF signal passing through the diode (Q L ). Consequently, this rectified current increases with the increase of the input power. As a result, the junction voltage (V L ) drops which leads to an increase of the base-emitter voltage (V BE ) of the amplifying transistor. 
     The methodology of the approach in  FIG. 3  is to distort the input signal with positive gain and negative phase deviations for compensating both the gain compression and phase distortion of the amplifier. A nonlinear rectified current is present when there is RF signal passing through the diode (Q L ). Consequently, this rectified current increases with the increase of the input power. As a result, the junction voltage (V L ) drops which leads to the increase of the internal resistance of Q L  and the magnitude and the phase of the transfer function from RF input port (RF IN ) to power amplifier input port (PA IN ) are increased and decreased, respectively. 
     Inevitably, the nonlinearity matching between diode linearizers and amplifying transistors is rigid, and hence, the linearity improvement is limited. 
     SUMMARY OF THE INVENTION 
     According to the present invention there is provided a microwave power amplifier comprising a bias network located between a radio frequency signal input port and the input port of a microwave transistor, wherein said bias network comprises a baseband part and a microwave part, both said baseband part and said microwave part being connected to a node located between the said radio frequency signal input port and said microwave transistor input port. 
     In preferred embodiments of the invention the baseband part comprises a forward-biased diode connected to the node via an RF choking inductor, and a decoupling capacitor connected to ground. The baseband part provides a short-circuit termination for low frequency intermodulation products at the input port of the microwave transistor. 
     The microwave part may comprise a forward-biased diode connected to said node, and a coupling capacitor. 
     The power amplifier may comprise either a bipolar transistor or a field effect transistor. 
     When the microwave transistor comprises a bipolar transistor, the bias network provides a substantially constant voltage that stabilizes the base-emitter voltage of the bipolar transistor. Furthermore, the bias network provides an increased base current for the bipolar transistor with increased input power. The increased base current may be provided by a rectified current generated by the forward-biased diode in the microwave part. 
     In a preferred embodiment of the invention, the microwave transistor comprises a bipolar transistor, and the bias network provides a substantially constant voltage that stabilizes the base-emitter voltage of the bipolar transistor, and an increased base current for the bipolar transistor with increased input power, with the stabilized base-emitter voltage and the increased base current providing an increased collector current with increased power. 
     When the microwave transistor comprises a field-effect transistor the bias network provides an increased gate-source voltage with increased input power. The increased gate-source voltage may be provided by a rectified current generated by the forward-biased diode in the microwave part. The increased gate-source voltage provides an increased drain current. 
     In preferred embodiments of the invention the microwave part of the bias network provides predistortion compensation by providing a positive gain deviation and a negative phase deviation to an input RF signal prior to being input to said microwave transistor. 
     In preferred embodiments of the invention the bias network provides a dynamic third order intermodulation distortion minimum, that the location of the minimum may be controlled by the collector current when the microwave transistor comprises a bipolar transistor or the drain current when the microwave transistor comprises a field-effect transistor 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings, in which: 
         FIG. 1  is a schematic diagram of a first example of the prior art, 
         FIG. 2  is a schematic diagram of a second example of the prior art, 
         FIG. 3  is a schematic diagram of a third example of the prior art, 
         FIG. 4  is a schematic diagram of the general form of an embodiment of the present invention, 
         FIGS. 5(   a )-( b ) show two examples of a forward-biased diode being directly connected to the RF path, 
         FIG. 6  shows the I-V characteristic curve of a forward-biased diode, 
         FIG. 7  shows a schematic diagram of a power amplifier topology for a bipolar transistor according to an embodiment of the present invention, 
         FIG. 8  shows the DC equivalent circuit of  FIG. 7  illustrating the stabilization of base-emitter voltage of the bipolar transistor, 
         FIG. 9  shows a comparison of the DC bias base-emitter voltage with varying the current-limiting resistance, 
         FIG. 10  shows a comparison of the DC bias base current with varying the coupling capacitance, 
         FIG. 11  shows a schematic diagram of a power amplifier topology for a field-effect transistor according to an embodiment of the present invention, 
         FIG. 12  shows the DC equivalent circuit of  FIG. 11  illustrating the self-adaptive gate-source voltage biasing of the field-effect transistor, 
         FIG. 13  shows a comparison of the DC bias gain-source voltage with varying the coupling capacitance, 
         FIG. 14  shows an equivalent circuit of an embodiment of the present invention operating as a predistorter, 
         FIG. 15  shows the movement of the IMD3 minimum, and 
         FIG. 16  shows a comparison of the IMD3 minimum between a conventional amplifier and an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       FIG. 4  shows the general structure of an embodiment of the self-adaptive bias network. The network is connected at a node located between the port of input RF signal (RF IN ) and the input port of the microwave transistor (PA IN ). The network can be divided into two parts: baseband and microwave parts. The baseband part includes an RF choking inductor L D , a decoupling capacitor C D  and a forward-biased diode Q D . L D  is used to isolate the RF signals, bypass low frequency components and provide a DC path to Q D . C D  is used to bypass all AC signals, including the leakage of RF signals and the low frequency intermodulation products, to ground. Q D  acts as a voltage stabilizer and a current source. The microwave part includes a forward-biased diode Q L  and a coupling capacitor C C . Q L  acts as a rectifier and a predistorter. C C  serves to control the coupling effect of the input RF signals to Q L . It should also be understood that the forward-based diodes Q D  and Q L  can be implemented either by microwave diodes or by junction diodes of a microwave transistor (eg the base-emitter junction or base-collector junction of a bipolar transistor). 
     To complete the review of the components in  FIG. 4 , V S1  and V S2  are the DC supply voltage sources for both the self-adaptive bias network and the amplifying transistor, R 1  is a bias resistor that provides a path for DC feed but an open circuit for RF signals, R 2  is a bias resistor that provides certain bias voltage for PA IN , and C DCB  is a DC-blocking capacitor that prevents DC signal passing through the RF port. 
     L D  should have a high inductance or a reactance that is higher than 250Ω at the carrier frequency. C D  should have a high capacitance or a reactance that is lower than 10Ω at the baseband frequency. R 1  should have a resistance higher than 250Ω. Q D  can be a low frequency component. Q L  is a microwave diode. 
     Both Q L  and Q D  operate in the forward-biased region, but the main difference between them is the movement of their quiescent point. When the diode is directly connected to the RF signal path as shown in the configurations of  FIG. 5  ( a ) or ( b ), the forward bias current I F  and the forward bias voltage V F  can be expressed as:
 
 I   F   =I   F0   +I   RECT  
 
 V   F   =V   SS   −I   F   R  
 
where I F0  is the forward bias current at zero RF input, I RECT  is the rectified current, V SS  is the supply voltage, and R is the bias resistor. When there is no RF signals, I RECT  is equal to zero such that I F  is equal to I F0 , while I RECT  increases with the increase of RF power. To further demonstrate the influence of I RECT , the movement of the quiescent point is illustrated in I-V characteristic curve as shown  FIG. 6 . If there is RF signals passing through the diode (the condition of Q L ), the quiescent point of the diode moves from the point S to point L as the voltage drop across R increases with the influence of I RECT . Or more generally, the presence of I RECT  contributes to the delta increase of I F  and the delta drop of V F . When the diode is well-isolated from RF signals (the condition of Q D  in  FIG. 4 ), the quiescent point stays at the point S steadily.
 
     Three objectives of embodiments of the present invention are to provide: (1) adaptive power management, (2) predistortion, and (3) dynamic third-order intermodulation distortion minimum for the power amplifier. 
     In the case of a power amplifier comprising a bipolar transistor, the self-adaptive bias network serves to (1) stabilize the base-emitter voltage V BE , and (2) bias the self-adaptive base current I B  for the self-adaptive collector current I C . 
     One embodiment of the topology for a bipolar transistor is shown in  FIG. 7 . The bipolar transistor can be any form of bipolar transistor, for example, a bipolar junction transistor (BJT), or a heterojunction bipolar transistor (HBT). The self-adaptive bias network is connected at a node between the port of the input RF signals (RF IN ) and the base junction of the bipolar transistor Q PA . V BB  is the base bias voltage, R BB  is the base bias resistor, and R CL  is the current-limiting resistor. 
     The baseband part of the self-adaptive bias network serves to stabilize V BE . For simplicity, the microwave part is replaced by a short circuit and the power amplifier is simplified as the DC equivalent circuit as shown in  FIG. 8 . The voltage at node X V X  and the total base bias current I BT  can be expressed as:
 
 V   X   =V   D   +I   SAB   R   CL  
 
 I   BT   =I   SAB   +I   B  
 
where V D  is the forward bias voltage of Q D , and I SAB  is the current passing through R CL . It can be seen that V BE  is forced to be biased as V X . Since Q D  is well-isolated from RF, by means of the choke L D  ( FIG. 7 ) so V D  remains constant. If I SAB  is much higher than I B  such that the rectified current (I RECT ) generated by base-emitter junction diode of Q PA  is comparatively negligible, then V BE  only depends on the voltage drop across R CL . Q D  acts as a current source, which supplies current for compensating the influence of I RECT . If I RECT  is comparatively negligible, I SAB  drops slightly. Thus, V BE  is stabilized as it keeps substantially constant. As a result, the nonlinear effect of the transconductance gain (g m ) of the bipolar transistor is compensated, and hence, the DC current gain is stabilized.
 
     The main function of R CL  is to limit I SAB , and hence, the power consumption of the self-adaptive bias network. Therefore, the effect of V BE  stabilization is directly affected by the choice of R CL . The comparison of V BE  with varying R CL  is depicted in  FIG. 9 .  FIG. 9  shows a more stable V BE  is provided by a lower R CL  with a higher I SAB . Moreover, the resultant resistance at node X in  FIG. 8  is affected by the resistance of R CL . So V BE  in the embodiment of the invention is slightly lower than that of the conventional one in low input power region. 
     I B  is self-adaptive as it changes with the input power. However, the self-adaptive I B  is mainly contributed by I RECT . Or more generally, it depends on the portion of the input power rectified by the base-emitter junction diode of Q PA . The microwave part of the self-adaptive bias network in  FIG. 7  serves to control the self-adaptive I B . I RECT  is further enhanced when RF signals pass through Q L . Since C C  of the invention is in the order of 10 −12 , which is comparatively lower than the junction capacitance of Q L , then the overall capacitance is dominated by C C  as they are in series connection. The main purpose of C C  is to control the coupling of the input signals from RF IN  to Q L . To study the effect of C C  on the self-adaptive I B , the comparison of I B  with varying C C  is depicted in  FIG. 10 .  FIG. 10  shows that a greater increase of I B  is achieved by a higher C C  as it provides lower impedance for more RF power couples to Q L . 
     With DC current gain stabilized self-adaptive I B  is biased by the self-adaptive bias network, and I C  is self-adaptive as it is equal to the product of I B  and DC current gain. 
     When the power amplifier comprises a field-effect transistor, the self-adaptive bias network serves to bias the self-adaptive gain-source voltage V GS  for the self-adaptive drain current I D . 
     One possible configuration of the topology for the field-effect transistor is shown in  FIG. 11 . The field-effect transistor can be any form of field-effect transistor, for example, a junction field-effect transistor (JFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-semiconductor field-effect transistor (MESFET), laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS), or a high electron mobility transistor (HEMT). The self-adaptive bias network is connected at a node between the port of the input RF signals (RF IN ) and the gate junction of the field-effect transistor Q PA . V GG  is the gate bias voltage, R G1  and R G2  are the gate bias resistors. 
     The microwave part of the self-adaptive bias network serves to bias the self-adaptive V GS . For simplicity, the baseband part can be replaced by a short circuit and then the power amplifier is simplified as the DC equivalent circuit shown in  FIG. 12 . The voltage at node X V X  and the total gate bias current I GT  can be expressed as:
 
 V   X =−( V   L   +I   GT   R   G1 )= I   SAB   R   G2   +V   GG  
 
 I   GT   =I   SAB   +I   G  
 
where V L  is the voltage drop across Q L , I SAB  is the current passing through R G2 , and I G  is the gate current. In general, I G  is nearly equal to zero. It can be seen that V GS  is forced to be biased as V X , which is directly affected by I SAB . Similarly, Q L  provides I RECT  such that I SAB  and V X  increase with the increase of input power.
 
     Q D  of the baseband part of the self-adaptive bias network provides a voltage drop such that R G2  can be realized with a smaller resistance. The combination of R G1  and R G2  is a voltage divider. Since R G1  is higher than 250Ω for providing an open-circuit for RF signals, R G2  should not be too low for a reasonable V GG  if Q D  is absent. 
     V GS  is self-adaptive as it changes with the input power. However, the self-adaptive V GS  is mainly contributed by I RECT . Since C C  of the invention is in the order of 10 −12 , which is comparatively lower than the junction capacitance of Q L , then the overall capacitance is dominated by it as they are in series connection. The main purpose of C C  is to control the coupling of the input signals from RF IN  to Q L . To study the effect of C C  on the self-adaptive V GS , the comparison of V GS  with varying C C  is depicted in  FIG. 13 . This shows that a greater increase of V GS  is achieved by a higher C C  as it provides lower impedance as more RF power couples to Q L . 
     Though the transconductance gain (g m ) of the field-effect transistor is decreased with the increase of input power, the increase of V GS  is more significant. With self-adaptive V GS  biased by the self-adaptive bias network, I D  is self-adaptive as it is equal to the product of V GS  and g m . 
     The DC power consumption of the amplifying transistor is equal to the product of DC bias voltage (collector-emitter voltage for bipolar transistor and drain-source voltage for field-effect transistor) and DC bias current (I C  for bipolar transistor and I D  for field-effect transistor). In general, the bias voltage always remains unchanged. The topologies described bias a self-adaptive current such that a lower current is supplied for amplifying a lower input power while the power handling is increased with a higher current for larger input signals. This phenomenon is regarded as an adaptive management that enhances the average power efficiency of the power amplifier. 
     The microwave part of the topologies described distorts the input signals with positive gain and negative phase deviation. Since the baseband part is well-isolated from RF signals, the topology can be simplified to the equivalent circuit of a predistorter shown in FIG.  14 . Q L  may in turn be modeled as a junction capacitor C j  in parallel with a dynamic resistor r D . Then, the admittance of the predistorter Y PD  can be expressed as: 
     
       
         
           
             
               
                 
                   
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     In general, the reactances of C j  and C C  are in the order of 10 0  for the operating frequency while R 1  is higher than 250Ω. Therefore, Y PD  can be approximated to: 
                     Y   PD     ≈       ⁢           -     ω   2       ⁢     R   1     ⁢     C   j     ⁢     C   C       +     jω   ⁡     (       C   j     +         R   1     ⁢     C   C         r   D         )           jω   ⁢           ⁢       R   1     ⁡     (       C   j     +     C   C       )                       =       ⁢         (         C   j       R   1       +       C   C       r   D         )     +     jω   ⁢           ⁢     C   j     ⁢     C   C             C   j     +     C   C                     
Let RF IN  and PA IN  be port 1 and 2 respectively. For simplicity, the port impedance is assumed to be Z 0 . The transmission coefficient from port 1 to port 2, S 21  can be expressed as:
 
                     S   21     =       ⁢     2     2   +       Z   0     ⁢     Y   PD                       =       ⁢       2   ⁢     (       C   j     +     C   C       )           2   ⁢     (       C   j     +     C   C       )       +       Z   0     ⁡     [       (         C   j       R   1       +       C   C       r   D         )     +     jω   ⁢           ⁢     C   j     ⁢     C   C         ]                       =       ⁢       2   ⁢     (       C   j     +     C   C       )             Z   0     ⁡     (         2   ⁢     (       C   j     +     C   C       )         Z   0       +       C   j       R   1       +       C   C       r   D         )       +     jω   ⁢           ⁢     Z   0     ⁢     C   j     ⁢     C   C                                    S   21          =       2   ⁢     (       C   j     +     C   C       )           Z   0     ⁢           (         2   ⁢     (       C   j     +     C   C       )         Z   0       +       C   j       R   1       +       C   C       r   D         )     2     +       ω   2     ⁢     C   j   2     ⁢     C   C   2                             ∠   ⁢           ⁢     S   21       =     -       tan     -   1       (       ω   ⁢           ⁢     C   j     ⁢     C   C             2   ⁢     (       C   j     +     C   C       )         Z   0       +       C   j       R   1       +       C   C       r   D           )             
where |S 21 | is the magnitude and ∠S 21  is the phase of S 21 . From the diode equation, r D  can be expressed as:
 
               r   D     =         (       ∂     I   L         ∂     V   L         )       -   1       =       kT     qI   S       ⁢     ⅇ       -     q   kT       ⁢     V   L                   
where I L  is the forward bias current and V L  is the forward bias voltage of Q L , kT/q is the thermal voltage (k is the Boltzmann constant, T is the temperature, and q is the electronic charge), and I S  is the saturation current. Since input signals are partially coupled to Q L , V L  decreases with the influence of I RECT . Thus, r D  is increased with the increase of input power. As a result, |S 21 | is increased to provide a positive gain and ∠S 21  is decreased to perform a negative phase deviation to the input signals. Since Y PD , S 21  and ∠S 21  are the functions of C C , C C  is to control the effect of coupling as well as the maximum deviation of both gain expansion and negative phase distortion.
 
     In the conventional power amplifiers, gain is compressed by the decrease of the transconductance gain and phase is distorted by the variation of the nonlinear capacitor when the amplifying transistor operates over its load line. The linearity of the input-output characteristic of the power amplifier is improved by the predistortion provided by the described topologies. 
     The combination of L D  and C D  provides a baseband short-circuit for the existence of the third-order intermodulation distortion (IMD3) minimum (proven in N. B De Carvalho and J. C. Pedro, “Large- and small-signal IMD behavior of microwave power amplifiers” IEEE Trans. Microwave Theory Tech., Vol. 47, No. 12, pp. 2364-2374, December 1999, which is hereby incorporated by reference herein in its entirety). Assuming the power amplifier is a weakly nonlinear device, by using the Volterra series with Taylor expansion, the output RF current i OUT (t) can be expressed as 
                 i   OUT     ⁡     (   t   )       =         1   2     ⁢     H   1     ⁢       ∑     q   =     -   Q       Q     ⁢       V   q     ⁢     ⅇ       jω   q     ⁢   t             +       1   4     ⁢     H   2     ⁢       ∑       q   1     =     -   Q       Q     ⁢       ∑       q   2     =     -   Q       Q     ⁢       V     q   1       ⁢     V     q   2       ⁢     ⅇ       j   ⁡     (       ω     q   1       +     ω     q   2         )       ⁢   t               +       1   8     ⁢     H   3     ⁢       ∑       q   1     =     -   Q       Q     ⁢       ∑       q   2     =     -   Q       Q     ⁢       ∑       q   3     =     -   Q       Q     ⁢       V     q   1       ⁢     V     q   2       ⁢     V     q   3       ⁢     ⅇ       j   ⁡     (       ω     q   1       +     ω     q   2       +     ω     q   3         )       ⁢   t                 +       1   16     ⁢     H   4     ⁢       ∑       q   1     =     -   Q       Q     ⁢       ∑       q   2     =     -   Q       Q     ⁢       ∑       q   3     =     -   Q       Q     ⁢       ∑       q   4     =     -   Q       Q     ⁢       V     q   1       ⁢     V     q   2       ⁢     V     q   3       ⁢     V     q   4       ⁢     ⅇ     j   ⁡     (       ω     q   1       +     ω     q   2       +     ω     q   3       +     ω     q   4         )                     +       1   32     ⁢     H   5     ⁢       ∑       q   1     =     -   Q       Q     ⁢       ∑       q   2     =     -   Q       Q     ⁢       ∑       q   3     =     -   Q       Q     ⁢       ∑       q   4     =     -   Q       Q     ⁢       ∑       q   5     =     -   Q       Q     ⁢       V     q   1       ⁢     V     q   2       ⁢     V     q   3       ⁢     V     q   4       ⁢     V     q   5       ⁢     ⅇ       j   ⁡     (       ω     q   1       +     ω     q   2       +     ω     q   3       +     ω   4     +     ω   5       )       ⁢   t                     +   …           
With two sinusoidal input signals, the input voltage can be expressed as
 
                       v   IN     ⁡     (   t   )       =       ⁢     A   ⁡     [       cos   ⁡     (         ω   1     ⁢   t     +     θ   1       )       +     cos   ⁡     (         ω   2     ⁢   t     +     θ   2       )         ]                   =       ⁢       A   2     ⁡     [       ⅇ     -     j   ⁡     (         ω   1     ⁢   t     +     θ   1       )           +     ⅇ     j   ⁡     (         ω   1     ⁢   t     +     θ   1       )         +     ⅇ     -     j   ⁡     (         ω   2     ⁢   t     +     θ   2       )           +     ⅇ     j   ⁡     (         ω   2     ⁢   t     +     θ   2       )           ]                   
When analyzed practically up to the fifth-order terms, IMD3 can be expressed as
 
                 i   OUT     ⁡     (       2   ⁢     ω   2       -     ω   1       )       =           3   ⁢     A   3       8     ⁢       H   3     ⁡     (       ω   2     ,     ω   2     ,     -     ω   1         )       ⁢     ⅇ     j   ⁡     [         (       2   ⁢     ω   2       -     ω   1       )     ⁢   t     +     (       2   ⁢     θ   2       -     θ   1       )       ]           +         50   ⁢     A   5       32     ⁢       H   5     ⁡     (       ω   2     ,     ω   2     ,     -     ω   1       ,   ω   ,   ω     )       ⁢     ⅇ     j   ⁡     [         (       2   ⁢     ω   2       -     ω   1       )     ⁢   t     +     (       2   ⁢     θ   2       -     θ   1       )       ]                   
If H 3 (•) and H 5 (•) are 180° out of phase, an IMD3 minimum exists.
 
     The topologies described provide a dynamic IMD3 minimum. H i (•) is a function of source/load impedances of the matching networks as well as the nonlinear internal components of the amplifying transistor which depend on the quiescent point. Then, the IMD3 minimum can be tuned by any combination of them such that H 3 (•) and H 5 (•) are 180° out of phase. The topologies described provide a baseband short-circuit and tune the IMD3 minimum dynamically by the self-adaptive bias current while the source/load impedances and bias voltage are kept constant. To further demonstrate the idea of dynamic IMD3 minimum, the movement of the IMD3 minimum is illustrated in  FIG. 15 . If a lower current is biased, the IMD3 minimum moves from point M to point L. In contrast, while if a higher current is biased, the IMD3 minimum move to point H. Therefore, IMD3 minimum dynamic as the self-adaptive bias current changes with input power. 
     Intermodulation distortion is a common problem when the power amplifiers are operated within the nonlinear region. Though IMD3 minimum can exist in the conventional power amplifiers, it is too narrow that only covers few dB range of the output power. Therefore, the dynamic IMD3 minimum technique serves to reduce the adjacent channel power (the power of IMD3 when the power amplifier is under two-tone test) for a wider dynamic range as shown in  FIG. 16 . As a result, the output power can be further utilized with the adjacent channel power is still kept below the required specification of the mobile systems.