Abstract:
A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This is a continuation of U.S. application Ser. No. 10/748,156, filed Dec. 31, 2003, which is a continuation of U.S. application Ser. No. 09/750,707, filed Jan. 2, 2001 (now U.S. Pat. No. 6,701,471), which is a continuation of U.S. application Ser. No. 09/544,609, filed Apr. 6, 2000 (now U.S. Pat. No. 6,199,187), which is a division of U.S. application Ser. No. 09/046,705, filed Mar. 24, 1998, which is a continuation of U.S. application Ser. No. 08/679,960, filed Jul. 15, 1996 (now U.S. Pat. No. 5,732,208). This application relates to and claims priority from Japanese Patent Application No. 07-179075, filed on Jul. 14, 1995. The entirety of the contents and subject matter of all of the above is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an external storage device of a computer using, for example, a static storage device, and more particularly relates to an external storage device for processing error detection and error correction of sector data at a high speed when sector data having an arbitrary byte width are accessed continuously according to a size of a sector unit.  
         [0004]     2. Description of Related Art  
         [0005]     With regard to background art, in order to simultaneously realize an improvement in reliability and high speed access in memory control, as disclosed in Japanese Patent Laid-Open No. Hei 6-105443 (1994), there is a system where data of an x-byte width outputted from a memory are divided into an odd number part (x/2 byte width) and an even number part (x/2 byte width), and regarding each of the odd number part and the even number part, error detection and error correction are performed using error correcting codes, and data of an x/2 byte width as outputted from the odd number part and the even number part are continuously outputted to a system bus of an x/2 byte width by an interleave control method.  
         [0006]     In order to perform the error detection and the error correction for sector data having an m-byte (e.g., 512 byte) width, the sector data of an m-byte width must be divided into an n-byte (e.g., one byte) unit for m/n times (m is a multiple of n) and then inputted to error correcting means.  
         [0007]     However, since error detection and error correction in the background art as described above are performed for data having a same byte width as that of the system bus, a differing byte arrangement cannot be applied as it is to error detection and error correction for sector data having an m-byte width larger than the byte width of the system bus. Moreover, as a further disadvantage in the background art as above described, both the odd number part and the even number part require individual error correcting means.  
         [0008]     The teachings of each of any above- or below-listed art are herein incorporated by reference.  
       SUMMARY OF THE INVENTION  
       [0009]     An object of the present invention is to provide an external storage device where a time required for error detection and error correction is reduced when error detection and error correction are performed for sector data having an m-byte width larger than the byte width of the system bus, and to realize a memory access at a high speed.  
         [0010]     Another object of the present invention is to provide an external storage device where a time required for error detection and error correction is reduced using a single error correcting means, and to realize a memory access at a high speed.  
         [0011]     In order to attain the foregoing objects, the present invention provides an external storage device comprising: a system interface section for conducting an interface with a host computer; error correcting means for performing error detection and error correction for sector data constituted by data having a byte number larger than that of a bus width of a system bus connecting the system interface section and the host computer; a first memory and a second memory as static storage devices each having a memory bus with a same bus width as that of the system bus for storing sector data; and control means for controlling a reading and writing operation of sector data from the host computer to the first memory and the second memory, wherein in response to a write command from the host computer, the control means stores a plurality of sector data attendant on the write command in the size of a sector unit alternately in the first memory and the second memory, and in response to read command from the host computer, the control means reads out the first sector data among a plurality of sector data required by the read command from the first memory and supplies the read-out sector data to the error correcting means, and then the control means reads out the sector data of the first memory and the second memory simultaneously, so that while the N-th (where N is a natural number) sector data from one of the first memory and the second memory are transferred to the system interface section, the (N+1)th sector data from the other are transferred to the error correcting means.  
         [0012]     In this preferred external storage device, data changing means selectively connects the memory bus of the first memory to one of the system interface section and the error correcting means, and also selectively connects the memory bus of the second memory to the other, and during the read access from the host computer, the control means alternately controls the data changing means so as to selectively and alternately read out the sector data of the first memory and the second memory.  
         [0013]     In a write access of sector data from the host computer to the first and second memories, a write buffer for temporarily storing the sector data may be provided to effect storage of the sector data in the first and second memories through the write buffer.  
         [0014]     In another embodiment, in place of the first memory and the second memory, a memory having a memory bus width of twice that of the system bus for storing sector data may be used. In this case, in response to write command from the host computer, the control means stores odd-numbered sector data (among a plurality of sector data) attendant on the write command using, for example, an upper side of the memory bus and memory, and also stores even-numbered sector data using, for example, a lower side of the memory bus and memory. In response to a read command from the host computer, the control means reads out the first sector data among a plurality of sector data required by the read command from the upper side of the memory and supplies the readout sector data to the error correcting means, and then the control means reads out the sector data at the upper side and the lower side of a memory address simultaneously, so that while the N-th (where N is a natural number) sector data from one of the upper side and the lower side of the memory address are transferred to the system interface section, the (N+1)th sector data from the other are transferred to the error correcting means.  
         [0015]     Also in a memory access control method of an external storage device according to the present invention, the external storage device having a static storage device storing sector data and comprising a first memory storing odd-numbered sector data of sectors of a plurality of continuous sectors of an access object and a second memory storing even-numbered sector data of sectors as the static storage device and error correcting means performing error detection and error correction for the sector data are used. When write access is performed from a host computer to the plurality of continuous sectors, odd-numbered sector data together with error correcting codes are stored in the first memory and also even-numbered sector data together with error correcting codes are stored in the second memory alternately in a size of a sector unit. When a read access is performed from the host computer to the plurality of continuous sectors, the first sector data are read out from the memory and error detection and error correction are performed by the error correcting means and while the first sector data having the error detection and error correction finished are transferred from the first memory to the host computer, the second data are simultaneously read out from the second memory and transferred to the error correcting means. Subsequently, while the second data having the error detection and error correction finished are transferred from the second memory to the host computer, third sector data are simultaneously read out from the first memory and transferred to the error correcting means. In a similar manner, while the N-th sector data having the error detection and error correction finished are transferred to the host computer, the (N+1)th sector data are simultaneously read out and transferred to the error correcting means.  
         [0016]     According to the present invention, control means (e.g., a microprocessor) can store a plurality of sector data of a write object in a memory so that the N-th sector data and the (N+1)th sector data can be read out simultaneously. Thereby, at any time, the N-th sector data can be outputted to a system bus by data changing means, and (N+1)th sector data can be simultaneously outputted to error correcting means. Consequently, since a time required for the error detection and error correction for the (N+1)th data can be performed simultaneously during the time the Nth data are outputted to the system bus, the time (as experienced by the external storage arrangement) required for the error detection and error correction for the sector data can be reduced apparently (i.e., made transparent to a host computer).  
         [0017]     Also since the error detection and error correction are always executed only for singular sector data which is subsequent to the sector data currently being transferred to the host computer, a single error correcting means may be used well.  
         [0018]     The foregoing and other objects, advantages, manner of operation, novel features and a better understanding of the present invention will become apparent from the following detailed description of the preferred embodiments and claims when read in connection with the accompanying drawings, all forming a part of the disclosure hereof this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing embodiments of the invention which are considered preferred embodiments at the time the patent application was filed in order to teach one skilled in the art to make and use the invention, and to otherwise satisfy the best mode disclosure requirements under U.S. patent law, it should be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The following represents brief descriptions of the drawings, wherein:  
         [0020]      FIG. 1  is a block diagram showing a system configuration of an external storage device of the invention.  
         [0021]      FIG. 2  is a block diagram showing a configuration of a system interface section  13 .  
         [0022]      FIG. 3  is a block diagram showing a configuration of data changing means  11 .  
         [0023]      FIG. 4  is a diagram showing a truth table of a read data selecting circuit  116 .  
         [0024]      FIG. 5  is a diagram showing a truth table of an error correcting means input data selecting circuit  117 .  
         [0025]      FIGS. 6-11  are flow charts showing operation of a host computer  2 .  
         [0026]      FIG. 12  is a block diagram showing a system configuration of another embodiment of an external storage device of the invention.  
         [0027]      FIG. 13  is a block diagram showing a configuration of data changing means.  
         [0028]      FIG. 14  is a block diagram showing a system configuration of still another embodiment of an external storage device of the invention.  
         [0029]      FIG. 15  is a block diagram showing a configuration of data changing means  93 .  
         [0030]      FIG. 16  is a timing chart showing an operation example of a write processing in an embodiment of the present invention.  
         [0031]      FIG. 17  is an explanation diagram of a first memory  4  and a second memory  5 .  
         [0032]      FIG. 18  is a timing chart showing an operation example of a read processing in an embodiment of the present invention.  
         [0033]      FIG. 19  is a timing chart subsequent to the timing chart in  FIG. 18 .  
         [0034]      FIG. 20  are views of a memory card containing an external storage device of the invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0035]     Before beginning a detailed description of the subject invention, mention of the following is in order:  
         [0036]     When appropriate, like reference numerals and characters are used to designate identical, corresponding or similar components in differing figure drawings.  
         [0037]     Embodiments of the present invention will be described using the accompanying drawings as follows. More particularly,  FIG. 1  is a block diagram showing a system configuration of a first embodiment of an external storage device  1000  according to the present invention. A memory control unit  1  writes or reads sector data to a first memory  4  and a second memory  5  according to a command from a host computer  2 , such memory control unit receiving the command of the host computer  2  by a control signal  22  and an external bus  32 .  
         [0038]     The host computer  2  is connected to a system bus  3  by a host computer bus  31 , and performs read and write operations of the sector data to the memory control unit  1  using the control signal  22  and the system bus  3 .  
         [0039]     The first memory  4  and the second memory  5  are storage means storing the sector data respectively, and a flash memory is used in a preferable embodiment although use of the present invention is not limited thereto. The flash memory is a known non-volatile semiconductor memory where electric erase and rewrite of data are possible in the size of a sector unit of a predetermined byte number (e.g., 512 bytes). However, the present invention can be applied also to other memory device and arrangement, and especially static storage devices.  
         [0040]     A local bus  6  is a bus connecting the memory control unit  1 , a write buffer  7  and a microprocessor  8 . The write buffer  7  is a storage means for temporarily storing the sector data written by the host computer  2 , and is connected to the local bus  6  by a write buffer bus  61 . The microprocessor  8  is connected to the local bus  6  by a microprocessor bus  62 , analyzes the command set to the memory control unit  1  by the host computer  2  and sets the operation to be performed by the memory control unit  1 . In this preferred embodiment, when a bus width of the system bus  3  is, for example, M bytes, a bus width of the local bus  6  is also M bytes to match that of the system bus  3 , and also, a bus width of each of a first memory bus  111  and a second bus  112  is M bytes to match that of the system bus  3 .  
         [0041]     Data changing means  11  selectively directs the sector data from the first memory bus  111  and the second memory bus  112  onto an ECC bus  113  and an internal data bus  114 . Error correcting means  12  generates error correcting codes for sector data for output to the internal data bus  114 , also performs error detection and error correction of sector data input from the ECC bus  113 , and informs the microprocessor  8  of the results of the error detection and error correction using a signal line  19 . A system interface section  13  receives any command for memory access from the host computer  2  along the control signal  22  and the external bus  32 . In response to such memory access command, the system interface section  13  outputs an interrupt signal  131  to the microprocessor  8 . Also the system interface section  13  generates an appropriate read signal  132 , a write signal  133 , a transfer finishing signal  134  and a timing signal  135  to control read/write of sector data by the control signal  22 .  
         [0042]     When the host computer  2  instructs writing of sector data, the write signal  133  is outputted and the sector data from the host computer  2  are stored from the internal data bus  114  into the write buffer  7  in accordance with a timing of the timing signal  135 . Also when the host computer  2  instructs reading of sector data, the read signal  132  is outputted and the sector data of the first memory bus  111  or the second memory bus  112  are read out in accordance with a timing of the timing signal  135  and directed to the internal data bus  114  by the data changing means  11  and outputted from the system interface section  13  to the computer  2 . Further the sector data are outputted to the host computer  2 , and at the same time the sector data (e.g., next sequential sector data) of the first memory bus  111  or the second memory bus  112  are directed into the ECC bus  113  by the data changing means  11  (under control of a signal from the microprocessor  8  along a signal line  18 ) and error detection and error correction are performed in the error correcting means  12 .  
         [0043]     In a preferred embodiment, components along a lower side of the system interface section  13 , or contained within the outline designated by  1000  (in  FIG. 1 ) can be contained within a memory card (e.g., flash memory card), views of which are shown in  FIG. 20 .  
         [0044]      FIG. 2  is a block diagram showing a configuration of the system interface section  13 . A data buffer  136  performs buffering of sector data from the external bus  32  and sector data from the internal data bus  114 . The command from the host computer  2  is set to an access setting register  137  along the line  22 . The command indicates the front address of the sector data to be accessed, a type of access (read or write) and the number of sectors (e.g., range of sector numbers or addresses) to be accessed. When the host computer  2  sets the command to the access setting register  137 , the access setting register  137  outputs an interrupt signal  131 . Also the access setting register  137  outputs a read signal  132  or a write signal  133  responsive to the set command. A control signal decoding section  138  outputs a transfer finishing signal  134  and a timing signal  135  from a control signal  22 . The transfer finishing signal  134  is outputted when the access to data of one sector is finished. The timing signal  135  is generated from the control signal  22  when the host computer  2  reads or writes the sector data. A status register  139  stores data indicating the state of the memory control unit  1 . When the interrupt signal  131  is outputted and when the transfer finishing signal  134  is outputted, the status register  139  is set to the busy state. Also the status register  139  is set to the ready state by the microprocessor  8 . When the status register  139  is in the busy state, the host computer does not read and write the sector data.  
         [0045]      FIG. 3  is a block diagram showing configuration of the data changing means  11 . A data selection setting register  115  is a storage means set by the microprocessor  8  using, for example, a signal along a signal line  18 , where information to select the data to be outputted to the ECC bus  113  and the internal data bus  114  from the first memory bus  111  or the second memory bus  112  is set. A read data selecting circuit  116  selects data to be outputted to the internal data bus  114  from the first memory bus  111  or the second memory bus  112  according to a content of the data selection setting register  115 . An error correcting means input data selecting circuit  117  selects data to be outputted to the ECC bus  113  from the first memory bus  111  or the second memory bus  112  according to a content of the data selection setting register  115 .  
         [0046]      FIG. 4  shows a truth table of the read data selecting circuit  116 . Data to be outputted to the internal data bus  114  are selected from the first memory bus  111  or the second memory bus  112  according to a content of the data selection setting register  115 .  FIG. 5  shows a truth table of the error correcting means input data selecting circuit  117 . Data to be outputted to the ECC bus  113  are selected from the first memory bus  111  or the second memory bus  112  according to content of the data selection setting register  115 .  
         [0047]     When a bus width of the system bus  3  is one byte, operation of the host computer  2  with regard to reading or writing of the sector data will be described using a flow chart as follows. More particularly,  FIG. 6  is a flow chart when the host computer  2  reads or writes the sector data. First, in step S 001 , a command is set to the access setting register  137  within the system interface section  13 . The command includes the sector number of the access start sector and the number of sectors to be accessed continuously. And then the status register  139  is supervised (step S 002 ) by the host computer  2 . If the status register  139  is set in the ready state, the host computer  2  reads or writes the data buffer  136  in the size of a one byte unit (step S 003 ). Operation of step S 003  is repeated for data of one sector until a read or write operation is finished (step S 004 ). If a read or write operation for all sector data is not finished (“No” branch of step S 005 ), the operations from steps S 002  to S 004  are repeated, and when a read or write operation for all sector data is finished, the read or write operation of the host computer  2  is finished.  
         [0048]      FIG. 7  to  FIG. 11  are flow charts showing operation of the microprocessor  8 . First, in step S 101 , the microprocessor  8  supervises the outputting of an interrupt signal  131  indicating that the host computer  2  has set a command to the access setting register  137 . If the interrupt signal  131  is outputted, the microprocessor  8  reads out the access setting register  137  and analyzes the command set by the host computer  2  (step S 102 ). Subsequently in step S 103 , if a type of access requested is a “write” operation, step S 104  is executed, and if a “read” operation is requested, operation of a flow chart shown in  FIG. 9  is executed.  
         [0049]     When command of the access setting register  137  indicates a “write” operation, in order that the sector data to be written by the host computer  2  are stored in the write buffer  7 , the microprocessor  8  outputs an address  81  to the write buffer  7  (step S 104 ), and sets a ready state to the status register  139  (step S 105 ). Subsequently, if data of one sector are stored from the host computer  2  to the write buffer  7 , a transfer finishing signal  134  is outputted from the control signal decoding section  138 . If the microprocessor  8  detects that the transfer finishing signal  134  is outputted in step S 106 , error correcting codes stored in the error correcting means  12  are read out (step S 107 ). Subsequently, the microprocessor  8  executes operation of a flow chart shown in  FIG. 8 .  
         [0050]     More particularly, turning now to  FIG. 8 , if the sector data stored in the write buffer  7  are the (2N−1)th (that is, odd-numbered) sector data, the first memory address  82  for the first memory  4  is outputted (step S 109 ), and sector data are transferred from the write buffer  7  to the first memory  4  and further the error correcting codes are stored in the first memory  4  (step S 110 ). Conversely, if the sector data stored in the write buffer  7  are the 2N-th (that is, even-numbered) sector data, the second memory address  83  for the second memory  5  is outputted (step S 111 ), and sector data are transferred from the write buffer  7  to the second memory  5  and further the error correcting codes are stored in the second memory  5  (step S 112 ).  
         [0051]      FIG. 17  shows a state of data stored in the first memory  4  and the second memory  5 . As clearly seen from  FIG. 17 , data of one sector (here 512 bytes) and error correcting codes generated therefore are stored in each address of the first and second memories. Error correcting codes in this preferred embodiment consist of one code (here 3 bytes) given to the data of one sector.  
         [0052]     When a writing operation of all sector data from the host computer  2  is finished, the microprocessor  8  repeats operations from step S 101 . When it is not finished, operations from step S 104  to step S 112  as above described are repeated (S 113 ).  
         [0053]     If the command of the access setting register  137  indicates a “read” operation, operation of a flow chart shown in  FIG. 9  is executed. More particularly, turning now to  FIG. 9 , first, the host computer  2  performs error detection and error correction for sector data to be read first. Since (2N−1)th (i.e., odd-numbered) sector data are stored in the first memory  4 , in order to input the first sector data to the error correcting means  12 , the microprocessor  8  sets a ‘1’ to the data selection setting register  115  (step S 114 ). Thereby in the memory control unit  1 , sector data read from the first memory  4  are directed within the data changing means  11  into the ECC bus  113  and are then outputted, and error detection and error correction for the sector data read from the first memory  4  are performed in the error correcting means  12 . Here, from the first memory  4 , the sector data and the error correcting codes subsequent thereto are outputted and the error correcting codes are inputted to the error correcting means  12 . Thereby in the error correcting means  12 , the sector data read from the first memory  4  are decoded and any error therein can be detected. Also in the memory control unit  1 , if outputting of the sector data read from the first memory  4  are finished for the error correcting means  12 , the transfer finishing signal  134  is outputted to the microprocessor  8 . If the microprocessor  8  detects that the transfer finishing signal  134  is outputted (step S 115 ), the decoding results stored in the error correcting means  12  are read out (step S 116 ), and a decision is effected regarding whether any error is generated (i.e., detected) or not (step S 117 ). If an error is generated, the microprocessor  8  makes the error correcting means  12  start the error correction processing thereby to determine an error position and correction pattern, and returns and writes correction results to the sector data having error generated and stored in the first memory  4  (step S 118 ). If no error is generated, process is advanced to step S 119  in  FIG. 10 .  
         [0054]     More particularly, in turning to  FIG. 10 , in step S 119 , the microprocessor  8  confirms whether the sector data to be outputted to the host computer  2  are the (2N−1)th (i.e., odd-numbered) data or not. Instep S 120 , the microprocessor  8  sets ‘0’ to the data selection setting register  115 , so that the (2N−1)th sector data are outputted to the host computer  2  and also the 2N-th sector data are inputted to the error correcting means  12 . In a next step S 121 , an address of sector data to be outputted to the host computer  2  is outputted to the first memory address  82 , and an address of the sector data performing error detection and error correction is outputted to the second memory address  83 .  
         [0055]     In step S 122 , the microprocessor  8  sets “1” to the data selection setting register  115 , so that the 2N-th sector data are outputted to the host computer  2  and also the (2N+1)th sector data are inputted to the error correcting means  12 . In step S 123 , an address of the sector data performing error detection and error correction is outputted to the first memory address  82 , and address of the sector data to be outputted to the host computer  2  is outputted to the second memory address  83 . Then, the microprocessor  8  sets the status register  139  to the ready state (step S 124 ).  
         [0056]     More particularly, the status register  139  is set to the ready state, thereby the host computer  2  reads the sector data for the memory control unit  1 . In step S 125 , a decision is effected regarding whether the transfer finishing signal  134  is outputted or not. If a reading operation for data of one sector is finished, a transfer finishing signal  134  is outputted from the control signal decoding section  138  of the memory control unit  1 . More particularly, the transfer finishing signal  134  is outputted, thereby the microprocessor  8  reads out the decoding results stored in the error correcting means  12  (step S 126 ), and a decision (step S 127 ;  FIG. 11 ) is effected regarding whether an error is generated (i.e., detected) or not. If an error is generated, the microprocessor  8  makes the error correcting means  12  start an error correction processing to thereby determine an error position and correction pattern, and the correction results are returned and written to the sector data in the first memory  4  or the second memory  5  (step S 128 ) having such error therein. If no error is generated, the process is advanced to step S 129 . When the host computer  2  finishes reading of all sector data, the microprocessor  8  repeats operations from step S 101 , and when it is not finished, operations are repeated from steps S 119  to S 128  as above described (step S 129 ).  
         [0057]     Next, a specific processing example of the device of  FIG. 1  will be described using the timing charts shown in  FIG. 16 ,  FIG. 18  and  FIG. 19 . More particularly,  FIG. 16  shows a write operation writing a sector data from the host computer  2  to the memories  4 ,  5 . At the time “t0,” if a write command is set from the host computer  2  to the access setting register  137 , at the time “t1,” an interrupt signal  131  is generated and such interrupt is applied to the microprocessor  8 . Also at the time “t1,” the status register  139  is changed to indicate a busy signal. Then, at the time “t2,” the status register  139  is changed to indicate a ready signal and the microprocessor  8  generates an address  81  to the write buffer  7 . At the time “t3” or later, data  1  to  512  representing 512 bytes are written in sequence one byte at a time into the assigned address positions of the write buffer  7  according to the timing signal  135 . Also the data  1  to  512  representing 512 bytes are inputted from the internal data bus  114  to the error correcting means  12  according to the timing signal  135 , and the error correcting means  12  generates error correcting codes. If the final data of 512 bytes are written at the time “t4,” a transfer finishing signal  134  is outputted at the time “t5.” Then, the sector data stored in the write buffer  7  in such manner are written in the first memory  4  or the second memory  5  as described in  FIG. 8 . The storage results stored within the memories  4 ,  5  become as shown in  FIG. 17 .  
         [0058]      FIG. 18  and  FIG. 19  show a read operation reading the sector data of the memories  4 ,  5  as requested from the host computer  2 . First in  FIG. 18 , at the time “t6,” a read command is set from the host computer  2  to the access setting register  137 , and then at the next time “t7,” an interrupt signal  131  is generated and the interrupt is applied to the microprocessor  8 . In this example, data of plural sectors at the address “100” or later shall be read out continuously. At a time “t8,” the address “100” of the first sector to be read out is given to the first memory address  82 , and at a time “t8” or later, the data of 512 bytes and the accompanying error correcting codes of 3 bytes are read out from the first memory bus  111  in sequence one byte at a time according to the timing signal  135 . These data are outputted to the ECC bus  113  and then inputted to the error correcting means  12 .  
         [0059]     Next, referring to  FIG. 19 , in order that the data of the first sector with the error check finished are outputted in turn to the internal data bus  114  (that is, to the side of the host computer  2 ), a directing state of the data changing means  11  is reversed. At a time “t9,” the address of the first memory address  82  remains “100” and the address of the second memory address  83  is made “101.” At a time “t10” or later, the sector data of the address “100” are read out again from the first memory  4 . The sector data are outputted to the internal data bus  114 . Simultaneous with outputting of the “100” address sector data, the data of 512 bytes of the second sector and the accompanying error correcting codes of 3 bytes are read out in sequence one byte at a time from the address “101” of the second memory  5 , and are then outputted to the ECC bus  113  communicating with the error correcting means  12 . After the reading of both sector data are finished, at the time “t1,” in turn, the address “101” of the second memory  5  having an error check finished is outputted to the memory address  82  of the first memory  4  and the second memory address  5  remains at the address “101.” The directing state of the data changing means  11  is then reversed. Thereby at the time “t12” or later, the sector data of the address “101” are outputted to the internal data bus  114 , and at the same time the sector data of the address “102” corresponding to a next sector are outputted to the side of the ECC bus  113 . Thus during reading of data of continuous sectors, the sector data are obtained continuously on the internal data bus  114 . As a result, it appears to the host computer  2  as if the time for error check processing by the error correcting means  12  did not exist.  
         [0060]     As above described, according to this embodiment, the microprocessor  8  stores odd-numbered sector data stored in the write buffer  7  to the first memory  4  and also stores even-numbered sector data to the second memory  5 . Accordingly, since the host computer  2  can read the N-th sector data and simultaneously can output the (N+1)th sector data to the error correcting means  12 , the time required for error detection and error correction to the (N+1)th sector data can be reduced apparently (i.e., made transparent to the host computer).  
         [0061]      FIG. 12  is a block diagram showing a system configuration of another embodiment of an external storage device according to the present invention. More particularly, except for a memory  9 , a memory bus  91  and data changing means  92 , this embodiment has the same configuration as that of  FIG. 1  and performs a same operation. A memory  9  has a bus width which is twice as large as that possessed by each of the first memory  4  and the second memory  5  in  FIG. 1 , and is connected by a memory bus  91  to data changing means  92  of a memory control unit  1  and a local bus  6 . The data changing means  92  selectively directs upper data and lower data from the memory bus  91  into an internal data bus  114  and an ECC bus  113 .  
         [0062]      FIG. 13  is a block diagram showing a configuration of the data changing means  92 . A data selection setting register  115 , a read data selecting circuit  116  and an error correcting means input data selecting circuit  117  perform the same operation as that shown and described with respect to the block diagram of  FIG. 3 . Data from the memory bus  91  are inputted as upper data  911  and lower data  912  to a read data selecting register  116  and an error correcting means input data selecting circuit  117 . The read data selecting register  116  outputs the upper data  911  or the lower data  912  to the internal data bus  114  according to a content of the data selection setting register  115 . Also the error correcting means input data selecting circuit  117  outputs the upper data  911  or the lower data  912  to the ECC bus  113  also according to a content of the data selection setting register  115 .  
         [0063]     That is, also for the memory  9  having the bus width twice as large as that of the system bus  3 , since the microprocessor  8  stores the (2N−1)th (odd-numbered) sector data stored in the write buffer  7  to upper bit memory positions and stores the 2N-th (even-numbered) sector data to lower bit memory positions on the same memory bus, the host computer  2  can simultaneously output the N-th sector data to the internal data bus  114  and can output the (N+1)th sector data to the error correcting means  12 . Consequently, a time required for the error detection and the error correction to the (N+1)th sector data can be reduced apparently (i.e., made transparent to a host computer  2 ).  
         [0064]      FIG. 14  is a block diagram showing a system configuration of another embodiment of an external storage device according to the present invention. In the configuration of  FIG. 14 , the write buffer  7  shown in the block diagram of  FIG. 1  is not used. That is, the sector data written by a host computer  2  are not stored temporarily to the write buffer, but are written directly to a first memory  4  or a second memory  5 . Therefore when the host computer  2  writes the sector data, data changing means  93  outputs data by directing the same from an internal data bus  114  to a first memory bus  111  or a second memory bus  112 .  
         [0065]     More particularly,  FIG. 15  is a block diagram showing a configuration of the data changing means  93 . A data selection setting register. 115 , a read data selecting circuit  116  and an error correcting means input data selecting circuit  117  perform the same operation as that shown and described with respect to the block diagram of  FIG. 3 . A write data selecting circuit  118  outputs data of an internal data bus  114  by directing the same to a first memory bus  111  or a second memory bus  112  according to a content of the data selection setting register  115 . When the data selection setting register  115  is ‘0’, the sector data of the internal data bus  114  are outputted to the first memory bus  111 , and when the data selection setting register  115  is ‘1’, the sector data of the internal data bus  114  are outputted to the second memory bus  112 .  
         [0066]     That is, since the write data selecting circuit  118  of the data changing means  11  outputs the (2N−1)th (odd-numbered) sector data to the first memory bus  111  and outputs the 2N-th (even-numbered) sector data to the second memory bus  112 , the (2N−1)th sector data can be stored in the first memory  4  and the 2N-th sector data can be stored in the second memory  5 . Thereby since the host computer  2  can read the N-th sector data and simultaneously can output the (N+1)th sector data to the error correcting means  12 , the time required for the error detection and the error correction to the (N+1)th sector data can be reduced apparently (i.e., made invisible to the host computer  2 ).  
         [0067]     This concludes the description of the preferred embodiments.  
         [0068]     Although the present invention has been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject data changing means arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention, e.g., the following represents a non-exhaustive list of modifications which might readily be apparent to one skilled in the art to which the present invention is directed: data obtained from the first memory or second memory may be temporarily stored in buffer memories before outputting to the internal data bus or error correcting means; and, the data within the error correcting means which has been subjected to error detection and correction may be outputted onto the internal data bus rather than performing a redundant reading from the memory.  
         [0069]     In addition to variations and modifications in the component parts and/or arrangements, uses with alternative non-static memories or with internal memories will also be apparent to those skilled in the art. More particularly, while the above disclosure has discussed applications of the subject combination arrangement with respect to static memories, it will be apparent to those skilled in the art that each of the subject combination arrangements are not so limited to such usage, but instead, could find application in a tremendous number of other uses, e.g., the combination arrangement disclosed above might have application with respect to dynamic memories.