Abstract:
A method of encoding a first stream of digital signal data words is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words is received and memorized. The most recent and the previous values of the stream of digital data words are combined to create a second data stream. The words are converted in the second data stream into a serial representation. The serial representation is transmitted on a single wire interface.

Description:
PRIORITY CLAIM  
       [0001]    This application claims priority of U.S. Provisional Patent Application No. 60/318,229 filed on Sep. 7, 2001, entitled “Serial Data Interface,” and U.S. Provisional Patent Application No. 60/318,457 filed on Sep. 10, 2001, entitled “Serial Data Interface”, the teachings are incorporated herein by reference. 
     
    
     
       TECHNICAL FIELD  
         [0002]    The present invention relates to electrical circuit interfaces and, more specifically, to encoding signals for low-power serial transmission over a single-wire interface.  
         BACKGROUND OF THE INVENTION  
         [0003]    Digital data is transmitted via serial interfaces in a great number of applications, for example, an Ethernet, a digital telephone system, and various digital audio systems. Power consumption is typically a very important parameter in portable applications, such as, for example, hearing aids. FIG. 1 shows the main components of a digital hearing aid  50 . In this example, microphone  52  receives an acoustic wave and transforms the acoustic wave into an analog electrical signal. Analog-to-digital converter (ADC)  54  converts the analog electrical signal into digital form. Digital signal processor (DSP)  56  processes the digital signal according an audiologist&#39;s prescription. Then digital driver  58  converts the processed digital signal into an acoustic wave directed toward a patient&#39;s ear. Microphone  52 , shown in FIG. 2, is generally a capacitive type microphone. Small metal container  62  is sealed on one side (not necessarily an air-tight seal) by conductive membrane  60  which is deflected when an acoustic wave applies force upon the conductive membrane. Conductive membrane  60  and metal container  62  are electrically isolated from one another, and the two-terminal system represents a capacitive structure. An electrical field exists between the two capacitive plates, i.e., between conductive membrane  60  and metal container  62 , and a time varying electrical voltage signal is thus created between the two plates when conductive membrane  60  vibrates. This produced electrical signal can provide only a small amount of power, and is therefore sensitive to electrical noise and other disturbances. The metal container is generally connected electrically to the system&#39;s ground, for example, a battery&#39;s negative terminal. A cavity inside metal container  62  is thereby, to a large extent, shielded from interference from unwanted electrical fields that may surround microphone  52 . A small integrated circuit (not shown) located inside metal container  62  amplifies the signal before the signal leaves the shielded environment. In advanced products, the signal is not only amplified, but also analog-to-digital (A/D) converted inside metal container  62 . The advantage of this procedure is that digital signals are virtually immune to noise interference, and hence can be routed outside metal container  62  without any loss of performance. Subsequent digital signal processing implemented by DSP circuit  56  should preferably be located outside metal container  62 , i.e., the digital signal processing should be separated from noise sensitive circuits near microphone  52 .  
           [0004]    [0004]FIG. 3 shows a system-level electrical schematic of a digital hearing aid where the ADC  54  is placed inside the microphone&#39;s metal container  62 . The microphone is electrically represented by voltage source  64  with a capacitive output impedance. Inside the shielding metal container are buffer circuit  66 , A/D converter  54 , and transmitter  68 . The system in FIG. 3 further comprises receiver  72 , DPS circuit  56 , digital driver  58 , clock generator  78 , and battery  74 .  
           [0005]    However, such a system suffers various shortcomings which are associated with such data interfaces. Specifically, the small physical size of metal container  62  limits the number of wires that can be used to connect the metal container to other elements in the hearing aid. A typical requirement is that the information-carrying signal be transmitted over single wire interface  76 . The physical dimensions of interface  76 , however, are far greater than those characteristic of interconnections between circuit blocks on a monolithic integrated circuit Hence, the interface is subject to a substantial capacitive load  70  to ground. Capacitive load  70  is highly undesirable because this substantial capacitive load will cause the transmitter to drain a substantial amount of energy from battery  74  every time interface  76  is charged from a low voltage to a higher voltage. Transmitter  68  will thus consume a significant amount of power if interface  76  is carrying a high bit rate. Therefore, it would be advantageous to have a method and system to substantially reduce the power consumption of the transmitter that will substantially reduce the power consumption without any loss of data.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention achieves technical advantages as an encoding/decoding system that substantially reduces the power required to communicate digital data over a serial interface with an appreciable capacitive load. A novel and improved way to design and operate a transmitter and receiver is disclosed.  
           [0007]    According to one aspect of the present invention, a serial interface is provided with a reduced power consumption.  
           [0008]    According to another aspect of the present invention, a serial interface is provided for use in portable applications, such as, for example, hearing aids.  
           [0009]    According to a further aspect of the present invention, a serial interface is provided that is optimized for data being transmitted.  
           [0010]    According to a further aspect of the present invention, a serial interface is provided that automatically synchronizes during normal operation.  
           [0011]    According to a further aspect of the present invention, a serial interface is provided which does not require a phase locked loop (PLL) for clock synchronization.  
           [0012]    Further advantages will become apparent from a consideration of the ensuing description, drawings and claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    For a better understanding of the invention including its features, advantages and specific embodiments, reference is made to the following detailed description along with accompanying drawings in which:  
         [0014]    [0014]FIG. 1 is an illustration of the main components of a digital hearing aid;  
         [0015]    [0015]FIG. 2 is an illustration of a microphone in greater detail;  
         [0016]    [0016]FIG. 3 is an illustration of a system-level schematic of a digital hearing aid where an ADC is placed inside the microphone&#39;s metal container;  
         [0017]    [0017]FIG. 4 is a an illustration of how codes are deciphered from a voltage signal applied to the interface by the transmitter in accordance with the present invention;  
         [0018]    [0018]FIG. 5 illustrates the operation of a transmitter in accordance with the present invention,  
         [0019]    [0019]FIG. 6 is an illustration of the operation of a state machine implementing the receiver  72  in accordance with the present invention;  
         [0020]    [0020]FIG. 7 is an illustration of a gate-level implementation of a transmitter in accordance with the present invention;  
         [0021]    [0021]FIG. 8 illustrates a timing diagram for a serial data interface in accordance with the present invention; and  
         [0022]    [0022]FIG. 9 illustrates a gate level implementation of a receiver in accordance with the present invention. 
     
    
       [0023]    References in the detailed description correspond to like references in the figures unless otherwise noted.  
       DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0024]    While the making and use of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides applicable inventive concepts which can be embodied in a wide variety of specific contexts.  
         [0025]    One embodiment of the present invention is a serial interface that encodes data according to a specific application, such as the application shown in FIG. 3. A/D converter  54  is based on a delta-sigma principle. The A/ID converter produces a stream of low resolution words, i.e., a sequence of codes each representing a numerical value, at a rate which is substantially higher than the Nyquist rate, ie., twice the signal&#39;s bandwidth. In this embodiment, the digital word rate (sampling frequency) is 2 MHz although the signal bandwidth is only 10 kHz. In other words, the over sampling ratio (OSR) may be expressed as:  
       OSR   =         2                 MHz       2   ×   10                 kHz       =   100                           
 
         [0026]    Delta-Sigma A/D converters generally produce digital words of very low resolution. Sometimes the resolution of the words is only one bit i.e., each word has one of only two possible numerical values, in which case transmitter  68  in FIG. 3 could be a simple digital buffer circuit. Transmitter  68  may consume significant power in charging and discharging capacitive load  70  if such a single-bit data stream were to be transmitted directly on the interface  76 . In this embodiment, however, delta-sigma ADC  54  advantageously produces digital words each with a resolution of two bits. In other words, ADC  54  produces a stream of data words in which each data word may have one of four predefined numerical values. Hence, in each clock cycle, one of four codes (code-0, code-1, code-2, or code-3) may be transmitted over interface  76  while the signal has only two valid voltage levels.  
         [0027]    [0027]FIG. 4 shows how the codes are deciphered from a voltage signal w(t) applied to interface  76  by the transmitter  68  in accordance with the present invention. Receiver  72  detects a logical value (high/low voltage levels are respectively interpreted as logical values 1/0) of w(t) at both a rising and falling edge of a clock signal c(t). For example, if w(t) is low at the rising edge of c(t) and w(t) is high at the falling edge of c(t), the receiver interprets the data as a message corresponding to code-1 (code “01”). The table below lists how the four codes are represented and interpreted.  
                                       Value of w(t) at the rising   Value of w(t) at the faing           edge of the clock signal   edge of the clock signal           c(t)   c(t)   Interpreted as                   low or “0”   low or “0”   code-0 or “00”       low or “0”   high or “1”   code-1 or “01”       high or “1”   low or “0”   code-2 or “10”       high or “1”   high or “1”   code-3 or “11”                  
 
         [0028]    In this conventionally designed interface, the four codes represent each one of the four numerical values that the digital signal d(k) is composed of. Receiver  72  then simply translates the received codes to the corresponding numerical values and communicates that translation to DSP circuit  56 . This conventional approach, however, implies that transmitter&#39;s  68  power consumption will be relatively high. This implication is a consequence of the nature of the signal d(k) produced by delta-sigma ADC  54 : even for constant input signals, d(k) will constantly fluctuate between two or more numerical values. The corresponding frequent fluctuation between codes implies that interface  76 , with the interface&#39;s  76  capacitive load  70 , will be charged and discharged frequently. This frequent charging and discharging of the interface&#39;s capacitive load  70  is associated with a relatively high power consumption.  
         [0029]    To reduce the power consumption, the present invention advantageously encodes d(k) in a different manner, such as to reduce the frequency at which the interface  76  is charged and discharged.  
         [0030]    ADC  54  produces a data stream d(k) which may be composed exclusively of the following numerical values: (+8), (+1), (−1), and (−8). It is particularly important to note at this point that the power consumption is small when the input signal is small, i.e., when the hearing aid, for example, is used in a relatively quiet environment. This type of use for the hearing aid is generally the case for more than 90% of the time the hearing aid is in operation. For such small signals, conventional delta-sigma ADCs tend to produce signals d(k) which quantitatively maybe of the type:  
         [0031]    d(k)= . . . , (+1), (−1), (+1), (−1), (+1), (−1), (−1), (+1), (−1), (+1), (−1), (+1) (−1), . . .  
         [0032]    In other words, the signal d(k) primarily alternates between the numerical values of (+1) and (−1) in between short sequences of constant (+1) or (−1). The sequences of identical values are rarely more than 2 or 3 samples long. Based on this observation, to reduce the power consumption, the present invention advantageously includes transmitter  68  designed to generate a code “00” every time the signal transitions either from (+1) to (−1) or from (−1) to (+1). If a (+1) follows a (+1), or a (−1) follows a (−1), transmitter  68  produces the code “11”. Hence, for the above data sequence, the transmitter produces the following sequence of codes:  
         [0033]    . . . , ??, 00, 00, 00, 00, 00, 11, 00, 00, 00, 00, 00, 00, 11, 00, . . .  
         [0034]    Interface  76  is charged and discharged much less frequently than if conventional encoding (where each code represents a specific numerical value) was used. As a result, the power consumption is reduced substantially.  
         [0035]    Receiver  72  is able to reconstruct the signal d*(k)=d(k). Observe that two different signals:  
         [0036]    d 1 (k)= . . . , (+1), (−1), (+1), (−1), (+1), (−1), (−1), (+1), (−1), (+1), (−1), (+1) (−1), (−1), . . . and  
         [0037]    d 2 (k)= . . . , (−1), (+1), (−1), (+1), (−1), (+1), (+1), (−1), (+1), (−1), (+1), (−1), (+1), (+1), . . .  
         [0038]    will produce the same sequence of codes mentioned above. In other words, receiver  72  will not inherently be able to detect the polarity of the signal, the receiver  72  would only be able to guarantee d*(k)=±d(k). In some applications, the absolute phase is arbitrary (in which case this encoding scheme would be splendid), whereas it is of crucial importance in other applications, such as in directional hearing aids, for example.  
         [0039]    Correct phase can be guaranteed if transmitter  68  and receiver  72  are synchronized by some sort of reset event. According to the present invention, such a reset event advantageously occurs relatively frequently to assure satisfactory performance in the very rare event that a bit error should occur. In this embodiment, synchronization is guaranteed every time d(k) attains a numerical value of either (+8) or (−8).  
         [0040]    In practice, transmitter  68  may be implemented as a digital state machine with four possible states: (−8), (−1), (+1), and (+8). The state machine is clocked once every clock cycle. The state machine always transitions to the state that corresponds to the value of d(k) (for simplicity the four states are named according to the value of d(k)). The state machine&#39;s operation is described in Table 1, which effectively defines the operation of transmitter  68 .  
                                   TABLE 1                                   Input value   Previous state   Now state   Code Generated           D(k)   d(k − 1)   d(k)   w(t)                           (−8)   (−8)   (−8)   “01”           (−8)   (−1)   (−8)   “01”           (−8)   (+8)   (−8)   “01”           (−1)   (+8)   (−1)   “01”           (−1)   (−8)   (−1)   “00”           (−1)   (−1)   (−1)   “11”           (−1)   (+1)   (−1)   “00”           (−1)   (+8)   (−1)   “00”           (+1)   (−8)   (+1)   “11”           (+1)   (−1)   (+1)   “00”           (+1)   (+1)   (+1)   “11”           (+1)   (+8)   (+1)   “11”           (+8)   (−8)   (+8)   “10”           (+8)   (−1)   (+8)   “10”           (+8)   (+1)   (+8)   “10”           (+8)   (+8)   (+8)   “10”           (+8)   (+8)   (+8)   “10”                      
 
         [0041]    The operation of transmitter  68  is illustrated in FIG. 5. In this example, each of the four states are represented by an oval. Each arc represents a transition from one state to the next, i.e., starting from d(k−1) and leading to d(k). The annotation of each arc identifies the code that is transmitted. Note that for each state, the transitions to each of the four possible states, new states are associated with each a unique code. Note also that all transitions to the state (−8) will produce the unique code “01”, and similarly that all transactions to the state (+8) will produce the unique code “10”. The combination of these two properties facilitates robust reconstruction of d(k) on the basis of the transmitted codes.  
         [0042]    Receiver  72  is implemented as a state machine. This state machine also has four possible states: (−8), (−1), (+1), and (+8). These states are named according to the corresponding numerical values of the output signal d*(k), which is the anticipated value of d(k). The state machine&#39;s operation is described in Table 2, which effectively defines receiver&#39;s  72  operation.  
                                   TABLE 2                                   Code Received   Previous State   New State   Output Value           w(t)   d*(k − 1)   d*(k)   d*(k)                           “01”   (−8)   (−8)   (−8)           “01”   (−1)   (−8)   (−8)           “01”   (+1)   (−8)   (−8)           “01”   (+8)   (−8)   (−8)           “00”   (−8)   (−1)   (−1)           “00”   (−1)   (+1)   (+1)           “00”   (+1)   (−1)   (−1)           “00”   (+8)   (−1)   (−1)           “11”   (−8)   (+1)   (+1)           “11”   (−1)   (−1)   (−1)           “11”   (+1)   (+1)   (+1)           “11”   (+8)   (+1)   (+1)           “10”   (−8)   (+8)   (+8)           “10”   (−1)   (+8)   (+8)           “10”   (+1)   (+8)   (+8)           “10”   (+8)   (+8)   (+8)                      
 
         [0043]    [0043]FIG. 6 is an illustration of the operation of a state machine implementing the receiver  72  in accordance with the present invention. In this example, each of the four states are represented by an oval. Each arc represents a transition from one state to the next, i.e., starting from d*(k−1) and leading to d*(k). The annotation of each arc identifies the received code. Note that when receiving code “01”, the state machine will always transition to state (−8), i.e., regardless of what the previous state was. Likewise, note that when receiving code “10”, the state machine will always transition to state (+8).  
         [0044]    Advantageously, according to Table 1 above, transmitter  68  will only generate code “01” when it transitions to state (+8), and likewise, transmitter  68  will only generate code “10” when it transitions to state (−8). Hence, the two state machines implementing respectively transmitter  68  and receiver  72 , will synchronize every time d(k) attains a numerical value of either (−8) or (+8). Synchronization will thus take place relatively frequently (which makes the system tolerant to bit errors) without disrupting the normal operation. To obtain immediate synchronization in a power-up situation, it is preferable that the first numerical value of d(k) is forced to be either (+8) or (−8). Once the two state machines are synchronized, they will remain synchronized (which can be seen from Tables 1 and 2).  
         [0045]    Gate Level Implementation (Transmitter)  
         [0046]    [0046]FIG. 7 is an illustration of a gate-level implementation of a transmitter  68  in accordance with the present invention. In this example, the digital input signal d(k) provided by ADC  54  is encoded in a “one-of” fashion, where only one line in the 4-bit bus is logically high at any time. A digital code representing d(k) is clocked into a first set of flip-flop circuits  80  slightly after (eg., 6 gate delays) the clock signal&#39;s c(t) rising edge. The digital codes “11”, “10, “01”, and “00” are used to represent the following numerical values for d(k): (+8), (+1), (−1), and (−8). The outputs from the first set of flip-flop circuits  80  are connected directly to the inputs of a second set of flip-flop circuits  82 A and  82 B which are clocked simultaneously with the first set of flip-flop circuits  80 .  
         [0047]    The two sets of flip-flop circuits  80 ,  82 A and  82 B store 2×2 bit codes representing respectively d(k) and d(k−1). According to Table 1, these four bits of information are sufficient to determine which digital code that should be transmitted on interface  76 . The actual encoding is performed by a small network of logic gates  84 . Two logical signals WR and WF attain the logical values that the receiver should detect at respectively rising and falling edges of the clock signal c(t). A single bit flip-flop circuit  86  produces the actual output signal waveform w(t). The flip-flop circuit  86  is clocked at every rising and falling edge of c(t). A small edge detecting circuit  88  produces a short duration pulse at each edge of c(t), which is used to clock the flip-flop circuit  86 . The output flip-flop circuit  86  will, at the rising edge of c(t), clock in and apply to interface  76  the value generated when c(t) is low, i.e., WF. Similarly, at the falling edge of c(t), the flip-flop circuit  86  will clock in the value generated when c(t) is high, i.e., WR.  
         [0048]    [0048]FIG. 8 illustrates a timing diagram for a serial data interface in accordance with the present invention. To assure a sufficiently long hold time for the output flip-flop circuit  86 , the preceding network of flip-flop circuits  80 ,  82 A, and  82 B and logic gates  84  are driven by the delayed clock signals, clk and {overscore (clk)}. Receiver  72  evaluates the voltage w(t) on interface  76  at the rising and falling edges of c(t). Notice that receiver  72  at any rising edge of c(t) detects the first bit WR(k) in the code representing the sample d(k) that was clocked into the first set of flip-flop circuits  80  one clock cycle earlier. Similarly, receiver  72  will at any falling edge of c(t), detect the second bit WF(k) in the code representing the sample that was clocked into the first set of flip-flop circuits  80  one and one-half clock cycles earlier. A few clock cycles of latency is quite acceptable in an interface for this type of application.  
         [0049]    Gate Level Implementation (Receiver)  
         [0050]    [0050]FIG. 9 illustrates a gate level implementation of a receiver in accordance with the present invention. In this example, a third set of flip-flop circuits  90 A and  90 B detect and store the logical values of w(t) at respectively the rising and falling edges of c(t). It is important that the third set of flip-flop circuits  90 A and  90 B are clocked directly by c(t) or by induced clock signals that have a minimum of delay with respect thereto. The inputs of a fourth set of flip-flop circuits  92 A and  92 B are connected directly to the outputs of the third set of flip-flop circuits  90 A and  90 B. Accordingly, the two logical signals DR and DF represent the detected logical values of w(t) at respectively the rising and falling edges of c(t). The timing of these signals is shown in FIG. 8. A fifth set of flip-flop circuits  94  stores the output signal, i.e. the expected value d*(k) of d(k). The encoding scheme used for d*(k) is shown in Table 3.  
                       TABLE 3                       Dx   Dy   d*(k)                   “0”   “0”   (−8)       “0”   “1”   (−1)       “1”   “0”   (+1)       “1”   “1”   (+8)                  
 
         [0051]    According to Table 2, the state machine&#39;s next state and output value d*(k) is a function of the received code and the previous state d*(k−1). These four bits of information are stored in the flip-flop circuits  92 A,  92 B and  94 . A small network of logic gates  96  perform the necessary decoding, as described by Table 2, and the new state and output value d*(k) is clocked into the flip-flop circuits  94  at the rising edges of c(t). FIG. 8 shows the overall timing diagram.  
         [0052]    Performance Evaluation  
         [0053]    The described embodiment of the present invention has been designed and simulated extensively. This embodiment&#39;s operation is very robust and no errors were detected.  
         [0054]    To evaluate the encoding scheme&#39;s efficiency, a comparison was made to a traditional serial interface where each of the possible values of d(k) are assigned a specific code transmitted on the interface. The results are summarized in Table 4.  
                       TABLE 4                       Signal Level Relative to   Transitions Standard   Transitions New       Full Scale   Interface   Interface                   −100 Db    1448/ms   608/ms       −80 Db   1429/ms   574/ms       −60 Db   1401/ms   569/ms       −40 Db   1451/ms   598/ms       −20 Db   1456/ms   599/m              0 Db    701/ms   1350/ms                   
 
         [0055]    As expected, the power consumption depends on the input signal level. Table 4 lists the number of transitions that occurred on interface  76  in a millisecond using a 2 MHz clock signal. The standard interface is characterized by, on average, approximately 0.7 transitions per clock cycle. This is representative for conventional delta-sigma modulators since these modulators constantly alternate between the available codes. Using the new interface, the average number of transitions per clock cycle on interface  76  are reduced to approximately 0.3, in other words, for typical signal levels (the signal level will only occasionally exceed −20 Db of full scale), the number of transitions are advantageously reduced by a factor of approximately 2.5.  
         [0056]    For the used technology, the present invention requires approximately 20 uA/MHz to drive interface wire  76  with a 5 pF capacitive load  70 . Hence, without the encoding, transmitter&#39;s  68  current consumption would be in the order of 28 uA. When the encoding scheme is used, transmitter&#39;s  68  current consumption is reduced to approximately 14 uA, including the power needed to operate the described circuitry. The saved 14 uA constitutes more than 10% of the total current consumed by buffer  66 , ADC  54 , and transmitter  68 . The new serial interface, therefore, represents a substantial overall improvement of the system.  
         [0057]    Therefore, from the foregoing description of the present invention, this invention substantially reduces the power consumption of a serial interface. The transmitter&#39;s  68  power consumption may be reduced by as much as a factor of two. The savings are a substantial fraction of the system&#39;s overall power consumption. The reduced power consumption translates into longer battery life, which is a substantial advantage for hearing aids and other portable applications. The interface is self-synchronizing, which makes it robust to bit errors and easy to use.  
         [0058]    While the above description contains many specificities, these should not be construed as limitations of the scope of the present invention, but rather as an exemplification of preferred embodiments thereof. Many other variations are possible. For example, a different set of codes may be used to represent transitions in the state machines, the delta-sigma modulator may have more or less than 4 quantization levels, the delta-sigma modulator&#39;s quantization levels may have a different set of values, for example, ±1 and ±3, ±1 and ±32, and the like, the interface may be used in other medical applications with other types of transducers, in cellular phones, for audio and non-audio equipment, with or without a shielding environment, and in many other applications such as, for example, electronic tape measures. Those who are skilled in the art will understand that the state machines used to illustrate a preferred embodiment of this invention is merely and example of such systems, they can be designed in a great number of ways. The underlying technology can be, for example, CMOS, BJT, BiCMOS or any other current or future technology suitable for the implementation of integrated circuits. In fact, this invention should not be construed as limited to electric circuit, future signal processing platforms, possibly biochemical, may take advantage of such encoding schemes for data communications. Accordingly, the scope of the invention should be determined not by the described embodiments, but by the appended claims and their legal equivalents.