Abstract:
An output buffer includes an output stage that includes a transconductance device configured to drive a capacitive load, and a first capacitor coupled to an input of the transconductance device. A converter converts an input clock signal into a current that is provided to charge the first capacitor during a specified interval. The converter includes a feedback loop to adjust the current so as to produce a specified logic level at the specified interval. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to the field of integrated circuitry; more particularly, to circuits that drive large capacitances, such as interface circuits useful for outputting signals from an integrated circuit (IC) to an external bus, circuit or system.  
         BACKGROUND OF THE INVENTION  
         [0002]    Numerous output driver circuits have been developed for integrated circuits and systems. In many cases, these driver circuit structures are designed to minimize noise for digital applications where the number of outputs is large, e.g., a 32-bit or 64-bit data bus or address bus. One source of noise in high performance logic circuits is a phenomenon known as “ground bounce”, which typically occurs when a transient current passes through the package inductance, producing a voltage glitch or spike that can cause a logic error. Digital circuits normally produce transient noise when the output switches from one logic level to the complementary logic level. According to fundamental laws of physics, this type of transient noise increases whenever the package inductance increases, the transient time decreases, the capacitive load increases, or the number of drivers increases.  
           [0003]    To combat the problem of ground bounce noise, circuit designers have tried a variety of different approaches, which include alteration of the package inductance, and circuit designs constrained to produce the smallest transient current possible. This latter approach to reducing noise involves controlling the transient current waveform of the output driver. An example of this design approach is disclosed in U.S. Pat. No. 4,947,063, which teaches reducing noise in an output driver by utilizing a ramp-shaped current pulse to change the output voltage. By way of further example, U.S. Pat. Nos. 4,947,063; 4,783,601; 5,510,744; 5,517,130; 6,127,746; and 6,329,866 disclose various structures and methods of output drivers exhibiting low noise performance.  
           [0004]    The basic problem with past output driver circuit designs is that the magnitude of the ramped current pulse is often difficult to control precisely. This limitation on device performance is often due to variations that exist in manufacturing process parameters and device operating conditions (i.e., supply voltage, temperature, etc.). For instance, many prior art implementations still suffer from problems associated with process variation of resistance values, in which process fluctuations in sheet resistance value lead to significant variations (e.g., 25% to 50%) in current references of the output driver.  
           [0005]    Variations across process or operating conditions in the magnitude of the ramped shaped current from an optimal value cause an increase in either the transient noise or transition delay. An increase in transition delay reduces timing margin, causes an increase in the error rate, or requires a reduction in the maximum data rate. Conversely, an increase in the transient noise voltage produces digital errors, which can cause a loss of data, or even produce catastrophic failure by way of latch-up in CMOS circuits. As process variations produce a wider variance in specific process parameters, the performance of the entire digital system thus decreases.  
           [0006]    Therefore, what is needed is a new circuit topology and method that minimizes transient noise from digital switching by reducing sensitivity to process parameters.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:  
         [0008]    [0008]FIG. 1 is a block diagram of an output driver circuit according to one embodiment of the present invention.  
         [0009]    [0009]FIG. 2 is a block diagram of an output driver circuit according to another embodiment of the present invention.  
         [0010]    [0010]FIG. 3 is a detailed schematic diagram of a frequency-to-current converter circuit utilized in accordance with one embodiment of the present invention.  
         [0011]    [0011]FIG. 4 is a circuit schematic diagram of an output driver stage utilized in accordance with one embodiment of the present invention.  
         [0012]    [0012]FIG. 5 is a timing waveform diagram illustrating the operation of the circuitry shown in FIG. 3.  
         [0013]    [0013]FIG. 6 is a schematic diagram of a circuit that incorporates a frequency-to-current converter and a current mirror array in accordance with another embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0014]    An adaptive, self-calibrating, low noise output driver is described. In the following description, specific details are set forth, such as device types, sizes, voltage levels, etc., in order to provide a thorough understanding of the present invention. Practitioners having ordinary skill in the integrated circuit arts will understand that the invention may be practiced without many of these details. In other instances, well-known elements, device structures, and processing steps have not been described in detail to avoid obscuring the invention.  
         [0015]    Referring to FIG. 1, there is shown a block diagram of an output driver  20  according to one embodiment of the present invention. Output driver  20  comprises a frequency-to-current converter circuit  21  coupled with an output driver circuit stage  23 . Output driver stage  23  drives an output node (V OUT ) having an associated capacitance (C OUT ). In a typical application, driver  20  is utilized in an integrated circuit to drive an output node coupled to external circuitry, e.g., an address or data bus. In this particular embodiment, output driver stage  23  provides a signal at V OUT  that is the complement of an input logic signal, labeled V IN .  
         [0016]    In operation, a ramp-shaped voltage is applied to the input of a transconductance device, such as a MOS transistor, in output driver stage  23 . The ramp-shaped voltage is produced by charging an internal capacitor from a current source. In the embodiment of FIG. 1 the current source is frequency-to-current converter  21 , which produces currents I CMP  and I CMN  coupled to the inputs of respective p-channel (i.e., PMOS) and n-channel (i.e., NMOS) field-effect transistors in output driver stage  23 .  
         [0017]    According to the present invention, the transfer ratio of frequency-to-current converter  21  and the input capacitance of the output driver stage  23  are designed to produce a specified minimum transition delay for a specified maximum value of transient noise contribution. These specific transition delay and noise values are established using the input frequency, F IN , applied to frequency-to-current converter  21 . This input frequency may be obtained from the operating clock frequency of the integrated circuit (IC), the clock frequency of an external device or bus, or some multiple (or fraction) thereof. As such, the transition delay is calibrated or adjusted to the input frequency. Output driver  20  thus adapts to the input frequency applied to frequency-to-current converter  21 . That is, as input frequency decreases (e.g., when the system clock frequency decreases) the transient noise voltage decreases to maintain optimum noise reduction for the new operating condition.  
         [0018]    [0018]FIG. 2 shows a block diagram of an output driver  30  according to another embodiment of the present invention. In this embodiment, frequency-to-current converter  21  is coupled to output driver stage  23  through a current mirror array  22 . Current mirror array  22  mirrors the currents I CMP  and I CMN  of converter  21  to charge the input capacitor of one or more output driver stages  23  (i.e., coupled to IN 1 /IP 1 , IN 2 /IP 2 , IN 3 /IP 3 , etc.). The embodiment of FIG. 2 is therefore useful for driving the multiple output driver stages needed to drive a full 32-bit bus, a large memory array, or other similar external devices. Current mirror  22  may comprise any one of a variety of precision current mirror arrays, such as that disclosed in U.S. Pat. No. 6,166,670, which is herein incorporated by reference.  
         [0019]    The equations included in FIG. 2 express the currents I CMP  and I CMN  as a function of the output capacitance, C OUT , the respective internal charging capacitances of the output driver stage (C 1  &amp; C 2 ), the transconductances (G MN  &amp; G MP ) of the n-channel and p-channel transistors (e.g., transistors  61  &amp;  60 , respectively, in FIG. 4), and the difference between the logic “1” and logic “0” voltage levels. In the case of CMOS circuitry, the term V 1  in the equation for I CMN  is equal to Vdd, and V 0  represents the maximum logic zero voltage level. Conversely, in the equation for I CMN , V 0  is equal to Vss and V 1  represents the minimum logic one voltage level. Practitioners in the art will understand that in the two noise equations shown in FIG. 2, L denotes the IC package inductance.  
         [0020]    Referring now to FIG. 3, a detailed circuit schematic diagram of one embodiment of frequency-to-current converter  21  is shown. (Actually, only the circuitry utilized to generate current source I CMN  is illustrated. The circuitry for generating I CMP  is a complement of the circuitry shown in FIG. 3, configured to generate an appropriate current provided to the p-channel output driver stage device.) The operation of converter  21  is best understood in conjunction with the timing waveform shown in FIG. 5.  
         [0021]    As shown in FIG. 3, a binary counter  31  is coupled to receive input frequency signal F IN . Counter  31  has its outputs coupled to decode logic circuit  32 . Decode logic circuit  32  utilizes the clock signals output by counter  31  (i.e., CLK/ 2 , CLK/ 4 , etc.) to generate the timing interval signals RAMPT, INIT, PUMP, and HOLDT, as well as their respective complementary logic signals RAMPF, INIF, and HOLDF. These timing signals are applied to various nodes in the circuit of FIG. 3 to produce the specified logic level at the specified delay interval. The delay interval is established from the rising edge of RAMPT to the rising edge of HOLDT (i.e., from t 0  to t 1  in FIG. 5). It is appreciated that in certain applications, decode logic circuit  32  may be omitted from converter  21 , and the timing interval signals obtained directly from the outputs of counter  31 .  
         [0022]    Frequency-to-current converter  21  also includes a charge pump circuit  46 , which produces an output voltage V PUMP  that is coupled to the gates of p-channel transistors  33  and  34  at node  48 . Transistors  33  and  34  are configured as a current mirror. The magnitude of current I CMN , which flows through transistors  33  &amp;  34 , is determined by V PUMP  and adjusted by feedback so that the output driver stage produces the specified logic level V OUT  at the specified delay. The current I CMN  through transistor  34  is switched either through p-channel transistor  35 , or p-channel transistor  36 , depending on the logical value of signal RAMPF and its complement signal, RAMPT, coupled to the gates of transistors  35  &amp;  36 , respectively. For instance, during a ramp interval when RAMPF is low (RAMPT is high) and INIT is low, the current I CMN  is used to charge capacitor C 1  connected at node  38 , producing a triangular shaped voltage waveform applied to the gate of n-channel transistor  41 . At the end of a ramp interval, RAMPF transitions high and RAMPT transitions low, so that the current is switched to Vss through transistor  36 . Transistor  37 , which has its gate coupled to receive the INIT signal, is used to initialize capacitor C 1 .  
         [0023]    In FIG. 3, transistor  41  is coupled in series with p-channel transistor  40  between Vdd and Vss. Transistors  40  &amp;  41  basically form a CMOS driver stage used to drive capacitor C OUT  to a logic one and logic zero output voltage. Capacitor C OUT  is shown connected to the negative input terminal of comparator  44 . The gate of transistor  40  in coupled to timing signal INIF, such that when C 1  is charging (i.e., INIT low), INIF is high and transistor  40  is off. Capacitor C 1  discharges when INIT transitions high.  
         [0024]    Continuing with the description of FIG. 3, the drain of transistor  41  is coupled to node  42 , which is coupled through a CMOS transmission gate  47  to the negative input of comparator  44 . Transmission gate  47  responds to the signals HOLDT and HOLDT to track and hold the waveform of the CMOS driver stage formed by transistors  40  &amp;  41 . Capacitor C OUT is also shown connected to the negative input terminal of comparator 44. Comparator 44 compares the voltage of C   OUT  to the logic zero voltage reference, V 0REF .  
         [0025]    The discrete time feedback loop is completed by the connection of the output of comparator  44  to the UP input of pump circuit  46 . In FIG. 3, pump circuit  46  is triggered by the PUMP input signal. The output of comparator  44  depends on the value of the residual voltage, VHOLD, present on COUT. When V HOLD  is higher than V 0REF , the comparator output CMPOUT transitions low, which, in turn, causes V PUMP  to pump to a successively lower voltage level. A lower V PUMP  value increases the current I CMN  flowing through the current mirror formed by transistors  33  &amp;  34 . This larger current causes capacitor C, to be charged to a slightly larger voltage, which causes transistor  41  to discharge slightly more current out of C OUT  during the timing interval, thereby lowering V HOLD . In the opposite situation when V HOLD  is lower than V 0REF , the current I CMN  decreases so as to increase V HOLD  until it matches V 0REF .  
         [0026]    With specific reference now to the timing diagram of FIG. 5, the clock frequency F IN (=CLK) is divided using binary counter  31  to produce the signal CLK/ 2 , as well as the other signals used by decode logic  32  to produce the digital waveforms that control frequency-to-current converter  21 . For example, in FIG. 5, the RAMPT signal has a frequency of CLK/ 4 , and the INIT signal has a frequency of CLK/ 8 .  
         [0027]    At the start of a calibration cycle the voltage V G  (on C 1 ) is zero, and the voltage V HOLD  (on C OUT ) is Vdd. At time t 0 , RAMPT transitions high, INIT transitions low, and HOLDT remains low. The drain current of transistor  34  flows through the differential current switch formed by transistors  35  &amp;  36  to charge capacitor C 1 . This causes the gate voltage, V G , of transistor  41  to increase as shown in FIG. 5. NMOS transistor  41  responds by conducting current to discharge C OUT  (lowering V HOLD ). This charge is passed from C OUT  to the drain of transistor  41  through transmission gate  47 , which remains conductive.  
         [0028]    The voltage V G  increases until RAMPT transitions low. Meanwhile, the voltages V HOLD  and V D  decrease until HOLDT transitions high at time t 1 , at which time transmission gate  47  stops conducting and V HOLD  is held constant. At this point, comparator  44  compares the voltage V HOLD  voltage to the logic zero reference voltage V 0REF . Since, in this example, V HOLD  is held at a lower voltage than V 0REF , the comparison causes CMPOUT to transition to a logic one. In the event that V HOLD  is higher than V 0REF , as shown by dashed line  70 , CMPOUT would remain at (or transition to) the logic zero level, as shown by dashed line  71  in FIG. 5.  
         [0029]    Another way of understanding the operation of the feedback loop is that if I CMN  has sufficient magnitude, then waveform V G  rises to a gate voltage that provides sufficient drive to transistor  41  to discharge C OUT  to the specified voltage V 0REF . This results in a logic one output from comparator  44 . Conversely, if I CMN  has insufficient magnitude then waveform V G  rises to a gate voltage that provides insufficient drive to transistor  41  to discharge C OUT  to the specified voltage V 0REF . This condition causes comparator  44  to output a logic zero voltage.  
         [0030]    Note that in FIG. 5 the signal PUMP is shown transitioning from logic zero to logic one at the end of the third clock cycle of F IN . This insures that comparator  44  has adequate time to respond to the input voltage V HOLD .  
         [0031]    At the end of the calibration interval, PUMP transitions low and INIT transitions high. This starts the discharge of capacitor C 1  and turns transistor  41  off. Simultaneously, INIF transitions low to turn on transistor  41 , which, in turn, charges C OUT  to Vdd. At time t 3 , RAMPT transitions low, and the drain current I CMN  of transistor  34  is conducted by the differential switch to Vss. This results in a further decrease in the voltage V G  across C 1 . This small offset voltage improves the accuracy of subsequent calibration cycles. In the example of FIG. 5, the calibration cycle is repeated, starting at time t 4 .  
         [0032]    [0032]FIG. 4 is a detailed circuit schematic diagram of output driver stage  23 , which includes p-channel output transistor  60  coupled in series with n-channel output transistor  61  between Vdd and Vss. The package inductances L P  and L N  are shown included in the respective paths between the on-chip supply lines Vdd and Vss and the off-chip, external power supply lines V DD  and V SS .  
         [0033]    Beginning with a description of the lower half of the output driver stage, the n-channel drive current I CMN  is switched through p-channel transistor  54  by the input logic voltage V IN . That is, when is V IN  transitions from a logic high to a logic low, n-channel transistor  57  turns off, transistor  54  turns on. The current I CMN  then flows into node  58  to charge capacitor C 1 , which is coupled between the gate of n-channel output transistor  61  and Vss. This results in a ramp-shaped charging voltage being produced at the gate of output transistor  61 , which becomes conductive to discharge external capacitor C OUT  (coupled to the drains of output transistors  60  &amp;  61  at node  63 ) to V SS .  
         [0034]    Note that when V IN  is low, transistor  55  is off and transistor  56  is turned on, causing capacitor C 2  coupled to node  59  to charge to Vdd. The presence of a high voltage level at node  59  means that p-channel output transistor  60  is off.  
         [0035]    When V IN  transitions logically high, transistors  54  &amp;  56  turn off, and transistors  55  and  57  begin conducting. This causes capacitor C 2  to charge to a low voltage by means of p-channel drive current I CMP . At the same time, capacitor C, discharges through transistor  57 . The result is a ramp-shaped discharging voltage produced at the gate of output transistor  60 , which becomes conductive to charge external capacitor C OUT  to V DD .  
         [0036]    Practitioners in the art will understand that the upper and lower circuit structures of the output driver stage  23  are replicated in the circuitry of frequency-to-current converter  21  that produces the respective p-channel and n-channel currents. For instance, the configuration of n-channel transistors  57  &amp;  61  and capacitors C 1  and C OUT  in FIG. 4 is replicated in FIG. 3 by the same configuration of transistors  37  &amp;  41  and capacitors C 1  and C OUT .  
         [0037]    Note, however, that in the embodiment of FIG. 4, C OUT  is an off-chip, external capacitance, whereas in the circuit of FIG. 3, C OUT  may either be replicated as an on-chip capacitance, or comprise an off-chip, external capacitance. In the latter case, an additional package pin may be needed for connection to this replicated capacitance. The capacitors C 1  and C 2  are on-chip devices in the embodiments described above.  
         [0038]    It is further appreciated that in other embodiments, the frequency-to-current converter circuitry may be made operate at a lower frequency, e.g., some fraction of the system clock or data rate. In such embodiments, the capacitances C 1 , C 2 , and C OUT  of converter  23  are appropriately scaled along with the device sizes of the associated transistors. Other circuit and device configurations are also possible.  
         [0039]    [0039]FIG. 6 illustrates a schematic diagram of a circuit that incorporates a frequency-to-current converter and a current mirror array in accordance with another embodiment of the present invention. Note that the frequency-to-converter portion includes the same basic circuit structure shown previously in FIG. 3. In the circuit of FIG. 6, however, comparator  44  is coupled to the UP input of three separate pump circuits  46   a - 46   c , each of which provides an output voltage, V PUMP1-3 , to produce the currents, I CMN1-3 , of the current mirror array portion of the circuit. Each of the pump circuits  46  is triggered by a corresponding PUMP 1-3  input timing signal. The feedback voltage signal V PUMP1  is coupled to the gate of p-channel transistor  91 , V PUMP2  is coupled to the gate of p-channel transistor  92 , and V PUMP3  is coupled to the gate of p-channel transistor  93 .  
         [0040]    Each of the transistors  91 - 93  is coupled in series between Vdd and a differential pair of switching transistors. For instance, the drain of transistor  91  is connected to the commonly coupled sources of transistors  95  &amp;  96 . Complementary switching signals S 1 T and S 1 F are shown connected to the respective gates of transistors  96  and  95  to control the current flow direction. When S 1 T is low, S 1 F is high, transistor  96  conducts, and transistor  95  is nonconductive. This results in current I CMN1  flowing through transistor  96  to the corresponding output driver stage. The opposite switching state (S 1 T high, S 1 F low) causes the current from transistor  91  to be directed to the differential switching pair of transistors  35  &amp;  36  of the frequency-to-current converter portion of the circuit.  
         [0041]    Transistor pairs  97  &amp;  98  and  99  &amp;  100  function in the same manner as described above to direct the mirrored currents either to the corresponding output driver stages or back through transistors  35  &amp;  36  of the frequency-to-current converter circuitry. Note that the example of FIG. 6, the switching signals S 1 T/S 1 F, S 2 T/S 2 F, and S 3 T/S 3 F are generated by decode logic block  82 , which is driven by binary counter  31 .  
         [0042]    It should be understood that although the present invention has been described in conjunction with specific embodiments, numerous modifications and alterations are well within the scope of the present invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense