Abstract:
The method is for producing a hard mask on a substrate, and in particular, on a primary area of a semiconductor substrate. The method includes the following steps: forming a first hard mask layer on the substrate; forming at least one additional hard mask layer on the first hard mask layer; structuring the additional hard mask layer in such a way that an area of the first hard mask layer is exposed; and structuring the first hard mask layer while using the additional hard mask layer as a mask so that an area of the substrate is exposed. Additional hard mask layers can be formed on the first hard mask layer. These hard mask layers are successively structured while using at least one overlying hard mask layer as a mask, until the area of the substrate is exposed.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of copending International Application No. PCT/DE00/04188, filed Nov. 24, 2000, which designated the United States and was not published in English. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a method for fabricating a hard mask on a substrate, and in particular to a method for fabricating a hard mask on a main area of a semiconductor substrate. 
     Although applicable, in principle, to a wide variety of substrate structures, the present invention and the problems on which it is based will be described using a semiconductor substrate. 
     Hitherto, only a hard mask layer that has been opened directly using a photolithographically patterned resist mask has been used for etching semiconductor substrates. 
     This mask can no longer be used to etch semiconductor substrates with an extremely high aspect ratio or to pattern materials that are difficult to etch if the mask requires a hard mask thickness that can no longer be opened at all in a single etching step with a photoresist mask. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the invention to provide a method for fabricating a hard mask on a substrate which overcomes the above-mentioned disadvantages of the prior art methods of this general type. 
     Therefore, it is an object of the present invention to provide an improved method for fabricating a hard mask having a larger thickness or an increased etching resistance. The method makes it possible to realize etchings that are no longer possible by the application of a simple customary hard mask. 
     Compared with the known solution approaches, the method has the advantage that etchings of semiconductor substrates with an extremely high aspect ratio or the patterning of materials that are difficult to etch can readily be realized using this hard mask. 
     The attractiveness of the method described should equally increase as the photoresist thickness decreases further (as the feature size decreases). 
     The idea underlying the present invention consists in using an n-layered hard mask layer system, where n is a natural number greater than or equal to 2, in order to be able to pattern the target layer or the target layer assembly n+1 by using an etching process, e.g. a dry etching process. In this case, the target layer-is defined as a constituent part of the substrate or may also be the latter itself. 
     A suitable cascading of hard masks will have to be designed in accordance with the application. 
     In accordance with one preferred development, the patterning of adjacent hard mask layers is carried out by using two different etching processes which make it possible to etch a further hard mask layer with a specific selectivity with respect to the first hard mask layer and also to etch the first hard mask layer with high selectivity with respect to the further hard mask layer. 
     In accordance with a further preferred development, the patterning of the further hard mask layer is carried out using a photoresist mask. 
     In accordance with a further preferred development, the photoresist mask is removed after the patterning of the further hard mask layer. 
     In accordance with a further preferred development, after the substrate has been uncovered, a remainder of the further hard mask layer remains on the first hard mask layer. 
     In accordance with a further preferred development, a plurality of further hard mask layers are formed on the first hard mask layer, which are patterned progressively using at least one overlying hard mask layer as mask until the region of the substrate is uncovered. 
     In accordance with a further preferred development, the patterning of adjacent hard mask layers is carried out by using two different etching processes that make it possible to etch the upper hard mask layer with a specific selectivity with respect to the lower hard mask layer and also to etch the lower hard mask layer with a high selectivity (i.e. preferentially) with respect to the upper hard mask layer. 
     In accordance with a further preferred development, the patterning of the topmost hard mask layer is carried out using a photoresist mask. 
     In accordance with a further preferred development, the photoresist mask is removed after the patterning of the topmost hard mask layer. 
     In accordance with a further preferred development, after the substrate has been uncovered, a remainder of the second-lowest hard mask layer remains on the bottommost hard mask layer. 
     In accordance with a further preferred development, hard mask layers of two different types are formed alternately. 
     In accordance with a further preferred development, at least two underlying hard mask layers are simultaneously opened with at least one hard mask layer. 
     In accordance with a further preferred development, the two materials of the hard mask layers are selected from the following pairs: Si—SiO 2 ; Si—SiN; SiO 2 —SiN; SiO 2 —Al. 
     In accordance with a further preferred development, the materials of the hard mask layers are selected from the following: silicon, in particular α-Si, poly-Si; silicon oxides, in particular SiO, SiO 2 ; borosilicate glass BSG, borophosphorus silicate glass BPSG; flowable oxide FOX, . . . ; SiN; SiO x N y ; W; WSi; Ti; TiN; TiSi; Al; Cu; Ta; TaN; polyimides; photoresists; and metal oxides, in particular Al 2 O 3 , TiO 2 , Ta 2 O 5 . 
     In accordance with a further preferred development, a thin barrier layer is formed between two adjacent hard mask layers and/or between the substrate and the first hard mask layer (typically ≦10% of the thickness of the hard mask layer), which barrier layers are likewise patterned during etching. 
     In accordance with a further preferred development, the method is applied during contact hole etching or during deep trench etching or during etching of nonvolatile materials, such as e.g. Pt, Ir or the like. 
     In accordance with a further preferred development, in this application, the hard mask layers are constructed as follows: oxide-X-oxide-X . . . , in particular oxide-X or oxide-X-oxide, where X=silicon, in particular α-Si, poly-Si; SiN; Al; Al 2 O 3 ; or oxide-X where X=A-B=Si—SiO 2 ; Si—SiN; Si—Al 2 O 3 ; SiN—SiO 2 ; Al—SiO 2 ; Al—SiN; Al—SiON (first-mentioned material in each case at the very bottom). 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a hard mask on a substrate. The method includes steps of:
     a) forming a first hard mask layer on the substrate;   b) creating a stack by forming a plurality of further hard mask layers on the first hard mask layer, the stack having a property that increases toward the substrate, the property selected from the group consisting of a thickness and an etching resistance;   c) progressively patterning all, except a top one, of the plurality of the further hard mask layers using at least one overlying one of the further hard mask layers as a mask; and   d) patterning the first hard mask layer using at least one of the plurality of the further hard mask layers as a mask such that a region of the substrate is uncovered.   

     In accordance with an added feature of the invention, the hard mask is used for etching a target layer, multiple target layers, or the substrate. 
     In accordance with an additional feature of the invention, the hard mask is used for performing a contact hole etching, a deep trench etching, or an etching of a nonvolatile material. 
     In accordance with another feature of the invention, the hard mask is used for patterning an electrode structure required for a stacked capacitor when etching with a high aspect ratio in either polysilicon or SiO 2 . 
     Exemplary embodiments of the present invention are represented in the drawings and explained in more detail in the description below. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in a method for fabricating a hard mask, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagrammatic representation of a semiconductor substrate with a stack including n hard mask layers for illustrating an embodiment of the method; and 
         FIGS. 2A-2E  show the essential method steps of a further embodiment of the method with a stack including two hard mask layers. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the figures, identical reference symbols designate identical or functionally identical elements. Referring now to the figures of the drawing in detail and first, particularly, to  FIG. 1  thereof, there is shown a diagrammatic representation of a semiconductor substrate with a stack including n hard mask layers with downwardly increasing thickness or etching resistance for illustrating one embodiment of the inventive method. 
     In  FIG. 1 , reference symbol  10  designates a semiconductor substrate with a layer n+1 to be etched using the hard mask. This layer, by definition, belongs to the substrate  10  or is the substrate itself. Provided above that are hard mask layers n, n−1, . . . , 3, 2, 1 having a respective thickness d i  (i=1, . . . , n) and also an already patterned photoresist layer 0 having the thickness d 0 . The photoresist layer  0  is applied to the topmost hard mask layer  1  having the thickness d 1 . 
     Using a suitable etching method, the hard mask layer  1  is opened and then the photoresist is preferably, but not necessarily, removed. The hard mask layer  1  then serves as a hard mask during the etching of the hard mask layer  2 , in which case a remainder of the hard mask layer  1  preferably, but not necessarily, remains on the hard mask layer  2 . The hard mask layer  3  is then patterned using the hard mask layer  2  and so on and so forth. 
     Given a choice of suitable hard mask materials and thicknesses and corresponding etching processes with suitable etching selectivities, it is possible, by using a thin photoresist mask and a relatively thin hard mask layer  1 , to produce a hard mask layer n having any desired thickness or any desired etching resistance. This hard mask layer n can then ultimately serve, together with a hard mask layer n−1 that may be present and that has not been entirely used up, as a hard mask for etching the target layer n+1 or the substrate. 
     The following symbols are used for the quantitative consideration:
     d i  the initial thickness of the layer I;   ER p,i  the etching rate of the material of the layer i during the etching of the layer p (etching process p);   S p,ij =ER p,i /ER p,j  the selectivity of layer i with respect to layer j during etching of the mask layer p;   f ue,i  the proportion of the layer i that remains as a remainder of the layer i after opening the layer i+1; and   f oe, i  the overetching contribution relative to layer thickness d i  during etching of the layer I;   

     For given etching rates ER p,i  and selectivities S p,ij  and for specific required overetching factors f oe,i  and residual layer thickness factors f ue,i , it is possible to derive the following formulae between the layer thicknesses of the hard mask films. Using these formulae, the obtainable mask thicknesses d i  and hence d n  and also the achievable etching depth d n+1  in the target layer n+1 can be calculated iteratively for given starting thicknesses d 0 , d 1 . For given thicknesses d n  and/or d n+1  it is possible to determine the required initial thicknesses of the topmost hard mask d 1  or of the photoresist mask d 0 .
 
 d   i+1   =S   i+1, i+1 i    F   i    d   i   +S   i+1, i+1 i−1    G   i−1    d   i−1   (1) 
 
where
 
       F   1 =[1− f   ue,i +( S   i, i+1 i   /S   i+1, i+1 i ) f   oe,i ]/[1+ f   oe, i+1 ]
   G   i−1   =f   ue, i−1 /[1+ f   oe, i+1 ] 
     If the overetching factors f oe,i  and residual layer thickness factors f ue,i  are disregarded, then the following simple expression is produced for the etching depth d n+1  of the target layer:
 
 d   n+1   =S   n+1, n+1 n    S   n, n n−1   , S   n−1, n−1 n−2    . . . S   2, 21    S   1, 10    d   0   (2) 
 
     Appropriate mask materials are, in particular, all customary materials used in the semiconductor industry, such as Si (α-Si, poly-Si), silicon oxides (SiO, SiO 2 , BSG, BPSG, FOX, . . . ), SiN SiO x N y , W, WSi, Ti, TiN, TiSi, Al, Cu, Ta, TaN, polyimides and photoresists, but also oxides, such as, for instance, Al 2 O 3 , TiO 2 , Ta 2 O 5 , etc. 
       FIGS. 2   a-e  show a stack including two hard mask layers in order to illustrate the essential method steps of a further embodiment of the inventive method. 
     If, by way of example, the remainder of the photoresist mask is removed after etching the layer  1 , the required layer thickness d 1  that is obtained using the above formula (1) in the case of such a two-layered hard mask for a given d 2  is as follows:
 
 d   1   =[d   2   /S   2, 21 ]×[1+ f   oe, 2 ]/[1− f   ue, 1 +( S   1, 21   /S   2, 21 ) f   oe, 1 ]. 
 
     In accordance with  FIG. 2   a , first a stack of the hard mask layers  1 ,  2  and the lithographically patterned photoresist layer  0  is provided on the substrate  10  having the layer  3  to be etched. In this case the layer  3  may be defined as belonging to the substrate  10  or may embody the substrate itself. 
     The photoresist layer  0  is then patterned in accordance with  FIG. 2   b  to form a mask that is used, in turn, to pattern the hard mask layer  1  in such a way that a region of the lower hard mask layer  2  is uncovered. The hard mask layer  2 , as indicated in  FIG. 2   b , is only slightly incipiently etched. 
     The photoresist mask  0  is subsequently removed in accordance with  FIG. 2   c.    
     In a further step in accordance with  FIG. 2   d , the lower hard mask layer  2  is patterned using the upper hard mask layer  1  as a mask such that a region of the substrate  10  is uncovered. 
     In this case, the patterning of the lower hard mask layer  2  is carried out by an etching process that has a high selectivity with respect to the upper hard mask layer  1 . Finally, the substrate  10  is etched using a hard mask formed by the hard mask layer  2  and the hard mask layer  1 , which has only partly been used up or etched away, in order thus to form a deep trench, for example. 
     During the etching of the substrate  10 , depending on the choice of the mask material  1  and/or in a manner dependent on the substrate etching process, the remainder of the hard mask layer  1  can function as a hard mask only during part of the substrate etching (e.g. when penetrating through a target layer  3  before the rest of the substrate is etched using the hard mask layer  2  as hard mask). Alternatively, during the etching of the substrate  10 , depending on the choice of the mask material  1  and/or in a manner dependent on the substrate etching process, the remainder of the hard mask layer  1  can generally function only briefly as a hard mask (until the remainder of the hard mask layer  1  has been used up and the hard mask layer  2  takes over the function of the hard mask for the substantial part of the substrate etching). Alternatively, during the etching of the substrate  10 , depending on the choice of the mask material  1  and/or in a manner dependent on the substrate etching process, the remainder of the hard mask layer  1  will not function explicitly as a hard mask at all (if the substrate etching process does not have an increased selectivity with respect to the hard mask material  1  and only hard mask layer  2  is intended to serve as hard mask). 
     A few further embodiments will additionally be mentioned by way of example below. 
     It is particularly expedient to effect the alternate deposition of two complementary materials X and Y to form a layer assembly with the sequence . . . XYXYXY . . . (at least XY in accordance with FIG.  2 ). For X and Y, at least two etching processes exist which make it possible both to etch the layer X selectively with respect to the layer Y and to etch the layer Y selectively with respect to the layer X. The following pairings are conceivable, for example: silicon oxide-SiN (where SiO is an example of various silicon oxides: thus, BSG-SiN would also be conceivable), silicon-SiO 2  and silicon-SiN, where silicon here represents α-Si and poly-Si. This would then give a multilayer hard mask of the form SiN —SiO 2 —SiN—. . . (or SiO 2 —SiN—. . . ) or of the form . . . —Si—SiO 2 — . . . or of the form Si—SiN—. . . . 
     By the alternate application of selective etchings, using thin photoresist masks, it is possible to pattern relatively thick hard masks and thus to realize high aspect ratios in the target layer or in the substrate. 
     A conceivable application is e.g. deep trench etching during DRAM (Dynamic Random Access Memory) fabrication. Hitherto, a simple oxide mask has been used in this case, often a pad nitride and an oxidized Si surface additionally lies between the oxide mask and substrate. 
     In this case, using a hard mask cascade including at least 2 hard mask layers XY, it would be possible to obtain an increase in the etching depth in silicon and thus an increase in the capacitor capacitance. By way of example, an SiN or Si or alternatively, for instance, an Al or Al 2 O 3  mask layer could thus be positioned above the oxide mask already present. This mask layer would make it possible to open the thick oxide mask required for achieving high trench aspect ratios. 
     A multilayer hard mask would likewise be attractive also for patterning materials that are difficult to etch, such as e.g. Pt or Ir, as are required for the electrodes of a stacked capacitor. In a Pt etching process that is currently undergoing intensive investigation, the selectivity of Pt:SiO 2  is about 1:3. Consequently, 750 nm of SiO 2  are necessary in order to etch only 250 nm of Pt. It can be seen that Pt electrode heights of 400-700 nm are required for a minimum feature size of 100 nm. SiO 2  hard mask heights of between 1200 nm and 2100 nm would then be necessary. The use of the hard mask cascade described above can provide a remedy here, too. There might possibly also be required a further ARC layer (ARC stands for Anti Reflection Coating) between the photoresist mask and the topmost hard mask layer and/or an additional barrier layer (e.g. TiN, TaSiN, etc.) between Pt and the bottommost hard mask layer. 
     In certain cases, it may also be necessary to position additional thin barrier layers between the hard mask layers X and Y. The combination Al—SiO 2  shall be mentioned as an example. Al can be etched excellently e.g. in chlorine-containing plasmas, while it can be removed only at a low rate in fluorine-containing plasmas. The situation is exactly reversed in the case of SiO 2 . Hard mask cascades including . . . Al—SiO 2 —Al—SiO 2  . . . are thus possible. However, it may be expedient to deposit thin TiN and/or Ti layers between SiO 2  and Al. 
     Although the present invention has been described above using preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways.