Abstract:
A family of Power Factor Corrected switching type AC-DC power converters of multi-channel configuration and a method of efficient AC-DC power conversion are proposed. The overall power conversion process used in the traditional single-channel AC-DC power converter configuration designed for high power applications is subdivided into N&gt;1 number of sub-processes of proportionally lower performance such that each power conversion channel delivers its 1/N-portion of power from the AC primary power source to the system load. Avoiding the high loss continuous current mode inherent in the usual single-channel configurations in traditional high power applications, the discontinuous or critical current mode is used within each power conversion channel. A power factor value, an efficiency of the power conversion process and a total amount of converted power increase proportionally to the number of power conversion channels combined. A multi-phase operation arrangement provides high quality continuous currents from the primary AC power source and to the system load. Utilizing the discontinuous current mode within each power conversion channel results in reduction of the voltage spikes and peak currents to which the switching devices are subjected to within conventional AC-DC power converters. Actively developing soft-switching zero-voltage-across/zero-current-through conditions while operating the power switching devices eliminates the power losses occurring during switching transitions. To provide efficient, power factor corrected operation of any number of power conversion channels combined, a single conventional PFC-controller is employed within a system control circuit. This may be of any existing design aimed to provide discontinuous, or continuous, or critical current mode within the traditional single-channel AC-DC power converter.

Description:
RELATED APPLICATIONS AND/OR PRIORITY CLAIMS  
       [0001]    This application is continuation-in-part and incorporates herein in its entirety U.S. patent application Ser. No. 09/578,180 filed May 23, 2000 entitled METHOD FOR CLUSTERIZED POWER SHARING CONVERSION AND REGULATION OF A PRIMARY POWER SOURCE WITHINA CONVERTING AND REGULATING POWER SUPPLY, AND SYSTEM, and U.S. patent application Ser. No. 09/677,717 filed Sep. 30, 2000 entitled LOSS REDUCTION CIRCUIT FOR SWITCHING POWER CONVERTERS, and claims any and all benefits and priorities of said earlier filings to which it is entitled therefrom. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates to electrical power conversion techniques, and, more specifically, to AC-DC power converters provided with active power factor correction circuits.  
           [0003]    More particularly, the present invention relates to switching-mode AC-DC power converters which convert the power supplied by the alternating-current primary source to an output direct-current power with close-to-unity power factor.  
         BACKGROUND OF THE INVENTION  
         [0004]    It is well known in the power industry that for maximum efficiency any AC powered device should draw an AC current waveform that is strictly in phase with the supplied AC voltage. The AC power consuming loads should appear as a resistive impedance to the primary AC power source, i.e. the power factor should be equal to unity.  
           [0005]    However, most AC power consuming loads depart from the ideal resistive impedance.  
           [0006]    Instead, these loads exhibit reactive, i.e. inductive or capacitive, properties such that the AC current may be substantially out of phase with the AC voltage , thereby decreasing the power factor to less than unity.  
           [0007]    In addition, most AC power consuming loads exhibit non-linear electrical properties which bring the non-linear and harmonic distortion of the AC current, such that both the AC current and AC voltage waveforms may substantially depart from pure sine-wave.  
           [0008]    At higher power conversion frequencies, the problem of harmonic distortion becomes even more severe. The considerable EMI noise affects the electric devices connected into the power distribution system and causes undesirable heat dissipation within the metal parts, therefore, decreasing the overall power conversion efficiency, i.e. the power factor.  
           [0009]    In general, for the AC systems, assuming that voltage and current are purely sinusoidal, the power factor value K PF  is defined as:  
             K   PF   =P   AC   /SAC ,  [1] 
           [0010]    where: P AC  is true power  
           [0011]    S AC  is apparent power  
           [0012]    True power is defined as:  
             P   AC   =U   AC   I   AC1  cos φ 1 ,  [2] 
           [0013]    where: U AC  is a RMS (root-mean-square) value for voltage produced by the AC primary source,  
           [0014]    I A1  is a RMS value for first harmonic of current consumed,  
           [0015]    φ 1  is a value for an angle of the phase-shift between the waveforms of the voltage supplied by the AC primary source and of the first harmonic of current consumed.  
           [0016]    An absolute power consumed may be defined as:  
                 S     A                 C       =         U     A                 C       ·     I     A                 C         =       U     A                 C                I     A                 C     2     +       ∑     n   =   1     ∞          I   ACn   2                 ,           [   3   ]                               
 
           [0017]    where: I AC  is a RMS value for the current consumed,  
           [0018]    I ACn  is a RMS value for an n-th harmonic of the current consumed.  
           [0019]    Therefore, the power factor value may be defined as:  
               K   PF     =         I   AC1     ·   cos                       ϕ   1     /           I   AC1   2     +       ∑     n   =   1     ∞          ·     I   ACn   2             .                 [   4   ]                               
 
           [0020]    The sine-wave conformity of the current consumed may be evaluated by the distortion factor value K HF  that may be defined as:  
               K     H                 F       =       I   AC1   2     /           I   AC1   2     +       ∑     n   =   1     ∞          I   ACn   2           .               [   5   ]                               
 
           [0021]    Traditionally, AC power consuming devices were commonly designed to provide high values of power factor, i.e. the current consumed should not be substantially phase-shifted with respect to the voltage applied.  
           [0022]    For example, in a device exhibiting inductive properties, a capacitor was added such that inductive and capacitive current components would compensate for each other.  
           [0023]    However, the size and weight of the passive components traditionally employed for the correction of the power factor are proportional to the amount of power consumed.  
           [0024]    Therefore, recently, a number of active techniques for Power Factor Correction have been proposed to eliminate the limits inherent in traditional approaches.  
           [0025]    According to these techniques, a switching-mode AC-DC power converter including active power factor correction (APFC) should be incorporated into AC consuming devices.  
           [0026]    However, in terms of total efficiency, the benefits gained by power factor improvement are negated by the core drawbacks inherent in conventional AC-DC power converters, i.e. substantial high frequency input and output ripple, and power losses caused by the switching transitions within the solid-state components.  
           [0027]    These drawbacks increase proportionally to the amount of power drawn from the primary AC source. Therefore, in high power applications, losses caused by the AC-DC power converter may exceed the losses prevented by the improved power factor correction.  
           [0028]    This is due to the fact, that the amount of power processed (as well as lost!) by the AC-DC power converter is proportional to its operational frequency.  
           [0029]    Most common AC-DC power converter designs are based on a primary power storage inductor or transformer, at least one controllable power switch, at least one power blocking rectifier, and an output smoothing filter capacitor. However, these prior art designs appear with large numbers of parts of a substantial size, weight, volume and power loss, and with a limited power conversion density, i.e. ratio of the number of watts per cubic inch or in regards to the overall cost.  
           [0030]    Attempts to increase the power conversion density by increasing the operational frequency have been ineffective. Primarily, because the proportional increase in power loss results in extensive heat dissipation which undermines component reliability.  
           [0031]    Therefore, present state-of-the-art AC-DC power conversion techniques still exhibit the unavoidable constraints placed on efficient high power application development.  
           [0032]    However, these are to be eliminated by the present invention in accordance with the following considerations. These are to be described with the Boost Converter Topology being chosen as an example to demonstrate the advantages of the present invention, although it is applicable equally to many other existing AC-DC power converter topologies.  
           [0033]    Our first consideration concerns the reduction of the inherent power losses within the present state-of-the-art AC-DC converters comprising the switching-mode AC-DC power conversion channels.  
           [0034]    It is known that increasing the operational frequency of AC-DC power conversion results in reduction of total weight, size and cost as well as an increase of the converted power density, i.e. number of watts per cubic inch.  
           [0035]    However, the solid-state switches of the AC-DC power converters are subjected to high power losses as a result of being changed from one state to another (i.e. when the switch turns on or off). This is due to the simultaneous current-through it and voltage-across it. This results in excessive heat dissipation within the switch during the switching transitions.  
           [0036]    For “off-on” transition the switching losses may be defined as:  
             W   on =0.5 V   sm I sm t on ;  [6] 
           [0037]    for “on-off” transition the switching losses may be defined as:  
             W   off =0.5 V   sm   I   sm   t   off ;  [7] 
           [0038]    where: V sm  is a voltage-across maximum value during the transition,  
           [0039]    I sm  is a current-through maximum value during the transition,  
           [0040]    t on  is a time-duration of the “off-on” transition,  
           [0041]    t off  is a time-duration of the “on-off” transition.  
           [0042]    The switching transition losses place substantial constraints on the potentially available performance rate of the existing AC-DC power converters where the bipolar junction transistors (BJT), the insulated gate bipolar transistors (IGBT) and the metal-oxide-semiconductor field-effect transistors (MOSFET) are used as the controllable power switches.  
           [0043]    Fast switching speeds, low power gate drive and low on-state resistance of the MOSFETs have made them a popular choice. However, the MOSFETs exhibit a large drain-to-source capacitance C oss . It reduces the dV/dt factor on turn-off and minimizes the power loss at this transition, but increases power loss at the turn-on transition since the power stored in C oss  is fully dissipated as heat within the MOSFET, which may be defined as:  
             P   on =0.5 C   oss   V   2   f   PS ,  [8] 
           [0044]    where: f PS  is a controllable power switch operation frequency value.  
           [0045]    The output voltage of the boost converter is always higher than the peak value of the AC primary voltage, and would be typically between 300 and 400 volts. At these high voltage levels the switching transition losses are unavoidably great, and the voltage transients and the current spikes may well damage the solid-state semiconductor devices. For this reason, a fast-recovery blocking power rectifier is required. At a high operational frequency, a fast-recovery rectifier is subjected to substantial reverse-recovery current and, therefore, produces a significant reverse-recovery loss when operated under “hard-switching” conditions, i.e. when simultaneous overlapping of non-zero-voltage-across with non-zero-current-through during the switching transition.  
           [0046]    Besides being galvanically non-isolated from the primary power source, the boost converters are quite sensitive to the reverse-recovery transients, which may destroy internal components. . As a result, the “hard-switched” AC-DC power converters are operated at relatively low switching frequencies.  
           [0047]    To reduce switching transition losses while increasing the switching frequency and, therefore, to improve the efficiency of the AC-DC power conversion, a number of “soft-switching” techniques have been proposed within the prior art.  
           [0048]    A “soft-switching” condition occurs when no voltage appears across the solid-state device and/or no current flows through it during the switching transition.  
           [0049]    Turning the solid-state device into a conducting state at zero-voltage-across it (ZVS=Zero-Voltage-Switching) results in the elimination of two kinds of switching transition losses: the first is caused by the blocking power rectifier reverse-recovery loss as defined in [7] and the second is caused by the controllable power switch stray capacitance discharge as defined in [8].  
           [0050]    Turning the solid-state device into a non-conducting state at zero-current-through it (ZCS=Zero-Current-Switching) results in an elimination of an inductively stored power loss which may be defined as:  
             P   off =0.5 LI   sm   f   PS ,  [9] 
           [0051]    where: L is the inductance value of the power storage inductor.  
           [0052]    To reduce switching transition power losses within AC-DC power converters, the prior art utilized numerous passive, i.e. inductive and capacitive components only, and active, i.e. solid-state semiconductor devices and snubber circuits.  
           [0053]    These optimally shape the operating point trajectories of the switching devices, i.e. adjust the shape-of-change of the voltage-across and of the current-through to minimize their overlap during the switching transition.  
           [0054]    Passive snubbers are hardly attractive since the power absorbed within their passive components is dissipated as heat. Active snubbers are more efficient since the absorbed power may be re-circulated back to the primary source or forwarded to the load.  
           [0055]    Shaping the operating point trajectories of the solid-state devices becomes extremely important with the increase of operational frequency, operational voltages and overall power conversion output.  
           [0056]    As well as the power switches of the AC-DC power converters, the switching devices within prior art active snubbers are also subjected to power losses described in [6] and [7].  
           [0057]    Minimizing these “snubber” losses is no less important a function both for the high and the low rates of power conversion since in the latter case the “snubber” losses may be of the same magnitude as the power conversion Output.  
           [0058]    Our second consideration concerns increasing the total power conversion output.  
           [0059]    To increase the power conversion density and the overall power conversion performance, a number of multiple converter topologies have been developed. These are power-sharing techniques utilizing the multiple arranged in-parallel AC-DC power converting units that are of a relatively small size. Each AC-DC converting unit delivers only a portion of the overall power. Moreover, it is cost effective to design and manufacture the standardized individual power converting units that may be combined into an array to feed a particular load, rather than to design and manufacture the specific AC-DC power converters to fit each application.  
           [0060]    The power-sharing AC-DC power conversion system includes at least one primary AC power source, a multi-channel AC-DC power converter and a load. The multi-channel AC-DC power converters may be of any existing topology provided that it contains N&gt;1 number of internal switching-mode power conversion channels. The early prior art designs provide a simultaneous operation of the paralleled power converting units. For a multi-channel AC-DC power converter this means that each internal channel delivers its 1/N-portion of power from the primary AC power source to a load in a synchronously coincidental (syn-phase) mode of operation, provided that all power conversion channels have a common operating frequency to trigger the power-on cycles.  
           [0061]    In a syn-phase mode of power conversion, all internal channels operate synchronously and simultaneously to each other. This synchronous operation creates large current pulses. These current pulses create additional problems by introducing substantial input and output ripple. The ripple is caused by the simultaneous overlay of similar non-linear responses within corresponding circuits due to the non-linearity of any power conversion process.  
           [0062]    Different multi-channel converter configurations introduce different ripple components. In the case of parallel combined inputs and outputs, the input and output currents are summed within the respective input and output circuits. The amplitude of the resultant primary source voltage drop increases proportionally to the N&gt;1 number of combined inputs. The resulting input and output currents have N&gt;1 times multiplied direct and ripple components as compared to the single power conversion channel.  
           [0063]    In the case of series combined input and/or output power conversion channels circuits, the amplitude of the primary source voltage drop increases proportionally to the number of combined inputs. The resultant delivery voltage has N&gt;1 times multiplied direct and ripple components as compared to the same single power conversion channel.  
           [0064]    Another disadvantage of the syn-phased power conversion is very slow response to the changes in the load. The time required to respond to a change in the load is limited to no less than one switching frequency period. In addition, the rate of response of the feedback circuit used to control the power-on cycle interval is severely limited to avoid oscillations.  
           [0065]    Therefore our third consideration concerns the quality of the totally processed power.  
           [0066]    Since all power conversion channels of the system have a common operating frequency, it was considered reasonable to operate the individual channels with staggered timing their power-on cycles, i.e. in a multi-phase mode. In this way a power demand is also staggered over the time thus reducing the large input current pulses.  
           [0067]    In a multi-phase mode all channels operate with their power-on cycles time-staggered such that there is a time displacement Δt dspl  interval between the start-on points of the sequential cycles.  
           [0068]    Provided that all power conversion channels have the same operational frequency, the resultant input and output currents show substantial reduction of input and output ripple. Due to the non-coincidental overlap of similar non-linearities, summing the time-staggered 1/N-portions of converted power produces a filtering effect within the input and output circuits of the combined power conversion channels.  
           [0069]    Since all power conversion channels are driven out-of-phase in respect to each other, their non-linear responses are superimposed in a non-simultaneous and non-coincidental order. The result is a staggered inter-related compensation of overlapped portions of non-linear responses. Such kind of overlay decreases the non-linearity of the summed current.  
           [0070]    It is therefore considered inappropriate to increase the output power by increasing the number of parallel syn-phased power conversion channels since it produces a proportional increase of the input and output ripple components. However, increasing the number of multi-phased power conversion channels produces a substantial decrease of the input and output ripple components as compared with a single power conversion channel.  
           [0071]    Our fourth consideration concerns the fact that recently a variety of specialized PFC-aimed controllers have been designed and manufactured to satisfy the need of the low-capacity AC-DC power conversion applications. According to the present invention, these may be used for the high power applications as well, thus eliminating the need to employ any nonstandard or custom-made devices.  
           [0072]    In view of the discussed considerations, the present invention aims to eliminate the drawbacks and constraints persistent in the present state-of-the-art.  
         SUMMARY AND ADVANTAGES OF THE INVENTION  
         [0073]    The benefits of the proposed invention may be better disclosed through the appraisal of the present state-of-the-art power factor correction circuits.  
           [0074]    [0074]FIG. 1 illustrates the circuit diagram of the prior art traditional full-bridge AC-DC rectifier.  
           [0075]    The indexed structures to be considered are listed below:  
           [0076]    [0076] 10 : a primary AC power source;  
           [0077]    [0077] 11 : an input AC-DC rectifier;  
           [0078]    [0078] 14 : a load;  
           [0079]    [0079] 17 : an output smoothing filter.  
           [0080]    The cited device operates in the following fashion:  
           [0081]    The primary AC power source  10  supplies the u AC (t) voltage of sine-wave shape to the input of the full-bridge AC-DC rectifier  11 . The rectified voltage is then applied to the output smoothing filter  17  and the load  14 , thus being transformed into the resulting output voltage u OUT (t).  
           [0082]    The shapes of the output voltage u OUT (t) waveform and, most significantly, of the waveform of the i AC (t) current consumed from the primary AC power source  10 , substantially depend on the circuit design and the properties of the output smoothing filter  17  and the load  14 , i.e. on the circuit impedance which is substantially capacitive in the discussed case.  
           [0083]    Both the circuit design and the nature of the impedance involve non-linear electric phenomena within the circuit, thus producing its non-linear response to the AC power source together with a non-linear impact upon the AC power source.  
           [0084]    As shown in FIG. 2, due to the non-linear response exhibited by the circuit design and its capacitive impedance, the shape of the time-scaled waveform of the i AC (t) current differs drastically from the shape of the waveform of the u AC (t) voltage.  
           [0085]    Accordingly, the power factor is considerably less than 100%, i.e. considerably less than unity value.  
           [0086]    Another prior art circuit design for the AC-DC power conversion is shown in FIG. 3 which illustrates the circuit diagram of single-channel switching-mode AC-DC power converter  100  of conventional boost topology comprising the means for an active power factor correction (APFC). Although many other existing converter topologies may be equally usable, the boost topology is the most applicable due to the simplicity of the design and better efficiency as compared with other topologies.  
           [0087]    The indexed structures to be considered are listed below:  
           [0088]    [0088] 10 : a primary AC power source;  
           [0089]    [0089] 11 : an input AC-DC rectifier;  
           [0090]    [0090] 12 : a single-channel DC-DC power converter;  
           [0091]    [0091] 14 : a load;  
           [0092]    [0092] 17 : an output smoothing filter;  
           [0093]    [0093] 20 : an input noise inhibiting filter;  
           [0094]    [0094] 21 : a current sensor;  
           [0095]    [0095] 22 : a power storage inductor;  
           [0096]    [0096] 23 : a controllable power switch;  
           [0097]    [0097] 24 : a power blocking rectifier;  
           [0098]    [0098] 26 : an active soft-switching conditioner;  
           [0099]    [0099] 27 : a shunting rectifier;  
           [0100]    [0100] 28 : a slope-shaping capacitor;  
           [0101]    [0101] 29 : a damp/resonant choke;  
           [0102]    [0102] 30 : a controllable commutating switch;  
           [0103]    [0103] 31 : a separating rectifier;  
           [0104]    [0104] 100 : an AC-DC power converter;  
           [0105]    [0105] 200 : a control circuit;  
           [0106]    [0106] 201 : an active power factor correction (APFC) controller.  
           [0107]    The cited device operates in the following fashion.  
           [0108]    The primary AC power source  10  supplies u AC (t) voltage of sine-wave shape to the input of the full-bridge AC-DC rectifier  11  producing a rectified voltage u IN (t) of half-sine-wave shape. The rectified voltage is then applied to the input of a single-channel DC-DC power converter  12 .  
           [0109]    The control circuit  200  operates the controllable power switch  23  by providing ON-OFF control signals for turning the switch into alternating closed/conducting and open/non-conducting states.  
           [0110]    FIGS.  6 ( a,b ) illustrate the nature of the operational cycle within the single-channel DC-DC power converter  12 . It should be noted that the following illustration, in general, concerns a “continuous current mode” to be discussed in the later paragraphs.  
           [0111]    In the quasi-steady state at some reference time, for example to, as shown in FIGS.  6 ( a,b ), the controllable power switch  23  is closed/conducting, the power storage inductor  22  is connected across the input AC-DC rectifier  11 , the power blocking rectifier  24  is non-conducting while being reverse-biased by the voltage stored across the output smoothing filter  17 , therefore the load  14  is disconnected from the input AC-DC rectifier  11  and is powered by the energy stored within the output smoothing filter  17 .  
           [0112]    While the input voltage u IN (t) of the input AC-DC rectifier  11  is applied across the power storage inductor  22 , the current i 22 (t) through it increases in a linear fashion and, thus accumulating the magnetically stored energy within the power storage inductor  22 , reaches its maximum value i 22max  at time t 01 . Therefore, the power storage inductor  22  absorbs the input current during the absorption time interval t ABS =t 01 −t 0 .  
           [0113]    Then the controllable power switch  23  is turned into open/non-conducting state, the power blocking rectifier  24  turns into forward-biased/conducting state, and the energy magnetically stored within the power storage inductor  22  is transferred via the power blocking rectifier  24  to the output smoothing filter  17  and to the load  14 . The current i 22 (t) through the power storage inductor  22  starts decreasing in a linear fashion and reaches its minimum value i 22min  by the end of operational cycle at time t 02 . Therefore, the power storage inductor  22  releases the magnetically stored energy during the release time interval t RLS =t 02 −t 01 .  
           [0114]    Subsequently the operational cycle is re-started.  
           [0115]    To start the next operational cycle the controllabe power switch  23  is turned into closed/conducting state again thus reverse-biasing the power blocking rectifier  24 .  
           [0116]    The controllable power switch operating frequency f PS  of the single-channel DC-DC power converter  12  is many times higher than the frequency f AC  of the AC voltage provided by the AC primary source  10 .  
           [0117]    Therefore, during the interval 0.5T AC  attributed to the half-sine-wave of the rectified voltage u IN (t) the single-channel DC-DC power converter  12  performs a series of operating cycles.  
           [0118]    FIGS.  4 ( a,b,c ) illustrate the time-scaled waveforms of the discussed phenomena, thus illustrating the nature of the high-frequency AC-DC conversion process performed by the cited device.  
           [0119]    During every operational cycle the single-channel DC-DC power converter  12  absorbs a portion of current i ABS (t) from the primary AC power source  10  via the input AC-DC rectifier  11 , and then releases an accumulated portion of energy as a release current i RLS (t) delivered to the load  14 . Both the i ABS (t) and i RLS (t) currents sequentially follow through the power storage inductor  22  thus producing a resultant waveform of the current i 22 (t).  
           [0120]    During the interval 0.5T AC  attributed to the half-sine-wave of the rectified voltage u IN (t) the summed portions of currents i ABS (t) and i RLS (t) produce an integrated waveform of the average value of i ACav (t) current consumed from the primary AC power source  10 .  
           [0121]    To provide a high power factor value, the control circuit  200  incorporates an active power factor correction (APFC) controller  201  producing a u 201 (t) ON-OFF control signal, shown in FIGS.  4 ( a,b,c ), to operate the controllable power switch  23 .  
           [0122]    An ON-state duration of the u 201 (t) ON-OFF control signal is equal to t ABS  absorption time interval corresponding to the conducting state of the controllable power switch  23  while the power storage inductor  22  accumulates the power absorbed from the AC primary power source  10  via the input AC-DC rectifier  11 .  
           [0123]    The time interval T PS , i.e. the controllable power switch operating period, between the leading edges of the sequential ON-state pulses of the u 201 (t) ON-OFF control signal is a period of the controllable power switch operation frequency f PS , i.e. T PS  is the operating cycle period.  
           [0124]    According to the teaching of the art, there may be three main modes of the current flow within the power storage inductor  22 .  
           [0125]    A discontinuous current mode is illustrated in FIG. 4( a ).  
           [0126]    Its emphasis is that the current i 22 (t) within the power storage inductor  22  is equal to zero-value in the quasi-steady state prior to any reference time t 0  corresponding to the leading edge of any u 201 (t) sequential pulse, as shown in FIG. 4( a ), and reaches its zero-value at any reference time t 02  prior to any reference time t′ 0  of the next operational cycle, i.e. prior to the leading edge of the u 201 (t) successive ON-state pulse.  
           [0127]    Therefore, in the discontinuous current mode, a pause interval t PAU =t′ 0 −t 02  of zero-current exists.  
           [0128]    During the absorption time interval t ABS =t 01 −t 0  the power storage inductor  22  absorbs the input current i IN (t) from the input AC-DC rectifier  11 , thus the current i 22 (t) increases.  
           [0129]    According to the teaching of the art, such a state is ascribed with an “absorption factor” K ABS :  
             K   ABS   =t   ABS   /T   PS .  [10] 
           [0130]    During the release time interval t RLS =t 02 −t 01  the power storage inductor  22  releases its magnetically stored energy, thus the current i 22 (t) decreases.  
           [0131]    According to the teaching of the art, such a state is ascribed with a “release factor” K RLS :  
             K   RLS   =t   RLS   /T   PS .  [11] 
           [0132]    During the pause time interval t PAU =t′ 0 −t 02  the power storage inductor  22  is current-free.  
           [0133]    According to the teaching of the art, such a state is ascribed with a “pause factor” K PAU :  
             K   PAU   =t   PAU   /T   PS ,  
           0&lt;K PAU &lt;1.  [12] 
           [0134]    Referring to FIG. 4( a ), it is evident that:  
             t   ABS   +t   RLS   +t   PAU   =T   PS ,  [13] 
           [0135]    and:  
             K   ABS   +K   RLS   +K   PAU =1.  [14] 
           [0136]    A critical conduction mode is illustrated in FIG. 4( b ).  
           [0137]    Its distinguishing feature is that the current i 22 (t) within the power storage inductor  22  is equal to zero-value in the quasi-steady state at any reference time t 0 , as shown in FIG. 4( b ), and reaches its zero-value at any reference time t 02  coincidental to the reference time t′ 0  of the next operating cycle such that no pause time interval t PAU  of zero-current exists.  
           [0138]    Therefore, at time t 02 =t′ 0  the current i 22 (t) starts to increase again. A continuous current mode is illustrated in FIG. 4( c ).  
           [0139]    Its distinguishing feature is that the current i 22 (t) within the power storage inductor  22  may not be equal to zero-value in the quasi-steady state prior or at any reference time t 0 , as shown in FIG. 4( c ), and may not reach its zero-value at any reference time t 02  coincidental to the reference time t′ 0  of the next operating cycle such that a non-zero current i 22 (t) may exist during the sequential operating cycles, i.e. during the sequential T PS  periods.  
           [0140]    Referring to FIGS.  4 ( b,c ), it is evident that there is no pause interval t PAU  both in the critical and the continuous current modes, i.e.:  
           t PAU =0, K PAU =0,  
           [0141]    therefore:  
             K   ABS   +K   RLS =1  
           [0142]    The illustrations provided in FIGS.  4 ( a,b,c ) propose a conclusion that, to the distinction of the circuit design shown in FIG. 1, in the latter case the power factor and the shape of the integrated waveform of the average value of i ACav (t) current consumed from the primary AC power source  10  do not depend substantially on the properties of the output smoothing filter  17  and the load  14 . These depend mostly on the AC input properties of the AC-DC power converter  100  as related to the AC primary power source  10 .  
           [0143]    It is evident that monitoring the duration of the T PS , t ABS , t RLS  and t PAU  intervals, i.e. operating the controllable power switch  23  in an appropriate fashion provides an opportunity to shape the integrated waveform of the average value of i ACav (t) current proportionally and synchronously to the u AC (t) voltage provided by the AC primary power source  10 , thus bringing the power factor very close to the unity value.  
           [0144]    However, the switching-mode process of power conversion results in substantial input and output ripple reducing the value of the power factor. To inhibit the ripple sufficiently, the filtering components must be of a substantial size and weight.  
           [0145]    It is evident that an increase of the controllable power switch operation frequency f PS  may result in reduction of the ripple and, therefore, in reduction of the filtering components size and weight.  
           [0146]    However, an increase of the controllable power switch operating frequency f PS  results in an increase of the switching transition power losses in accordance with [6] and [7].  
           [0147]    The previous discussion may be true for an ideal case only when the on/off-turn transition time of the controllable power switch  23  and of the power blocking rectifier  24  may be considered negligibly short in comparison with the operating cycle duration.  
           [0148]    Under real circumstances, the semiconductor devices exhibit inertia properties as a result of the residual stored charge, parasitic capacitance, etc.  
           [0149]    As an example, the excessive carriers within the base of the power blocking rectifier  24  cannot dissipate immediately after the power blocking rectifier  24  having been reverse-biased thus resulting in a short-time loss of its rectifying properties.  
           [0150]    This leads to an excessive reverse current and an excessive heat dissipation within the power blocking rectifier  24  due to a large reverse voltage drop across it, and to an excessive current stress through the controllable power switch  23  during its turn-on transition due to discharging the capacitor within the output smoothing filter  17  through the effective short-circuit of rectifier  24 .  
           [0151]    Power blocking rectifier  24  regains its reverse blocking capability only after the excess carriers in its base have dissipated.  
           [0152]    Therefore the amount of switching losses within the controllable power switch  23  and the power-blocking rectifier  24  substantially depends on the excessive carriers dissipation time.  
           [0153]    The fact that the switching power losses restrict the maximum operating frequency and power factor improvement, constitutes the first substantial drawback of the prior art to be eliminated by the present invention.  
           [0154]    To minimize switching transition power losses, a variety of the “soft-switching” conditioning or “snubber” circuitry has been proposed within the prior art, such as one of them shown in FIG. 3 with an index  26 .  
           [0155]    The purpose of incorporating an active soft-switching conditioner  26  into the DC-DC power converter  12  is to provide the zero-voltage-across condition to the controllable power switch  23  during its transition into the conducting state, and to limit the rate-of-change of the current through the blocking power rectifier  24  during its transition into the non-conducting state.  
           [0156]    To secure the reliable soft-switching conditioning, the APFC controller  201  produces a ZV(t) (zero-voltage-condition) ON-OFF control signal to operate the controllable commutating switch  30  in an appropriate fashion.  
           [0157]    As a result, incorporating the active soft-switching conditioner  26  into conventional boost converter configuration substantially improves its efficiency due to the reduction of the switching transition power losses within the controllable power switch  23  and the power-blocking rectifier  24 .  
           [0158]    However, when the continuous current mode is secured within the power storage inductor  22 , the controllable commutating switch  30  operates under hard-switching condition since it is turned-off into the non-conducting state while carrying a current greater than the input current, and subsequently turned-on into conducting state while the voltage across it is equal to the output voltage. Since, to satisfy the zero-voltage soft-switching condition for the controllable power switch  23 , the peak resonant current within the damp/resonant choke  29  may be twice greater as within the power storage inductor  22 , then tuning-off the controllable commutating switch  30  into the non-conducting state is accomplished with a considerable power loss.  
           [0159]    It should be emphasized that the damp/resonant choke  29  and the controllable commutating switch  30  are the main components of the active soft-switching conditioner  26 . These are common to every soft-switching conditioning circuit.  
           [0160]    The nodes of the active soft-switching conditioner  26 , as shown in FIG. 3, are connected across the controllable power switch  23  and across the power-blocking rectifier  24 .  
           [0161]    With the active soft-switching conditioner  26  being incorporated into the DC-DC power converter  12  maintaining the continuous current mode within the power storage inductor  22  its operation is as follows being accompanied with the illustrations shown in FIG. 4( d ).  
           [0162]    In the quasi-steady state prior to time t 1  the controllable power switch  23  is open/non-conducting; the power blocking rectifier  24  is forward-biased/conducting thus providing the power path from the AC primary power source  10  and from the power storage inductor  22  to the output smoothing filter  17  and the load  14 . The controllable commutating switch  30  within the active soft-switching conditioner  26  is open/non-conducting.  
           [0163]    The regulated output DC voltage U OUT  is applied across the controllable power switch  23  shunted with the slope-shaping capacitor  28 .  
           [0164]    At time t 1  the leading edge of the U ZVT-201 (t) ON-state pulse triggers the controllable commutating switch  30  into the closed/conducting state, and now the regulated output DC voltage U OUT  is applied across the network of series-connected power blocking rectifier  24  and a damp/resonant choke  29 .  
           [0165]    Now the power blocking rectifier  24  is still forward-biased/conducting, the controllable commutating switch  30  is also conducting since being closed, and, with assumption that forward voltage drops across each of them may be neglected, the regulated output DC voltage U OUT  is therefore applied across the damp/resonant choke  29  ascribed with a current i 29 (t).  
           [0166]    The current i 29 (t) through the damp/resonant choke  29  starts increasing at the rate of:  
             di   29   dt=−U   OUT   /L   29   [15] 
           [0167]    where: L 29  is an inductance value of the damp/resonant choke  29 .  
           [0168]    The rate of current i 29 (t) increase defines the rate of the simultaneous decrease of the current i 24(   t ) carried by power blocking rectifier  24 , thus resulting in dissipation of the excessive carriers within its base. Therefore, the damp/resonant choke  29  performs a damping function while defining the rate of dissipation of the excessive carriers within the base of the power rectifier  24 .  
           [0169]    With an appropriate choice of the inductance value L 29 , it is possible to decrease the power losses associated with switching the power blocking rectifier  24  into the reverse-biased/non-conducting state.  
           [0170]    The current i 29 (t) would proceed undergoing its own way according to [15] well past the current i 24 (t) falling down to zero at time t 2 , i.e. i 24 (t 2 )=0.  
           [0171]    The time interval t diss24  of the excessive carriers dissipation within the base of the power rectifier  24  may be defined as:  
             t   diss24   =i   22max   L   29   /U   OUT ,  [16] 
           [0172]    When the excess carriers within the base of the power rectifier  24  have dissipated, its reverse blocking capability is restored. During the reverse resistance recovery process the power rectifier  24  carries a reverse recovery current.  
           [0173]    After that, at time t 3  the power blocking rectifier  24  becomes reverse-biased/non-conducting and disconnects the load  14  from the power storage inductor  22  and the primary AC power source  10 .  
           [0174]    Since prior to time t 3  the power blocking rectifier  24  has been conducting, the voltage across the controllable power switch  23  and across the slope-shaping capacitor  28  within the active soft-switching conditioner  26  is still very close to the U OUT  level.  
           [0175]    Past time t 3  the on-going process is defined by the LC-resonant tank consisting of parallel-connected damp/resonant choke  29  and the slope-shaping capacitor  28  within the active soft-switching conditioner  26 . Current i 29 (t) continues to increase which results in decrease of the voltage applied across the controllable power switch  23  and across the slope-shaping capacitor  28 :  
             i   29 ( t )=i 22 ( t   3 )+ i   24 ( t   3 )− C   28   dU   28   /dt,    
             u   23 ( t )= u   28 ( t )= L   29   di   29   /dt,   [17] 
           [0176]    where: i 22 (t 3 ) is the value of current carried by the power storage inductor  22  at time t 3 ;  
           [0177]    i 24 (t 3 ) is the value of current carried by the power rectifier  24  at time t 3  of its tum-off/non-conducting.  
           [0178]    Respecting the component parameters of the active soft-switching conditioner  26  the equation [17] may be regarded as:  
             i   29 ( t )= i   22 ( t   3 )+ i   24 ( t   3 )− U   OUT  sin ω 0   t /( L   29   /C   28 ) 0.5 ,  
             u   28 ( t )= U   OUT  cos ω 0   t,   [18] 
           [0179]    where: ω 0 =(L 29 C 28 ) 0.5  is a natural resonant frequency of the LC-tank consisting of the damp/resonant choke  29  coupled to the slope-shaping capacitor  28 ;  
           [0180]    C 28  is a capacitance value of the slope-shaping capacitor  28 .  
           [0181]    The sine waveform of the current through the damp/resonant choke  29  and the cosine waveform of the voltage across the slope-shaping capacitor  28  would last until time t 4 , when the voltage u 23 (t))=u 28 (t) across this capacitor and across the controllable power switch  23  reaches zero and the shunting rectifier  27  becomes forward-biased/conducting.  
           [0182]    Therefore during the interval between time t 3  and time t 4  the damp/resonant choke  29  performs a resonant inductor function within the L 29 C 28  resonant tank. During this interval the cosinusoidal fashion of discharging the capacitor  28  within the active soft-switching conditioner  26  is provided as a preparation for switching the controllable power switch  23  into closed/conducting state under zero-voltage-across condition past time t 4 .  
           [0183]    The duration of the preparation time interval is defined with a quarter of the period of the natural resonant frequency of LC-tank consisting of the damp/resonant choke  29  coupled to the slope-shaping capacitor  28 , i.e.:  
             t   4   −t   3 =0.5 π( L   29   C   29 ) 0.5   [19] 
           [0184]    Starting from time t 4 , the controllable power switch  23  may be turned into the closed/conducting state under zero-voltage-across condition at any time prior to the controllable commutating switch  30  being turned into the open/non-conducting state.  
           [0185]    Therefore, the favorable condition of soft-switching is provided to the controllable power switch  23  by time t 5  when it is triggered into the closed/conducting state with a leading edge of the u 201 (t) ON-state pulse, and the absorption time interval t ABS  starts. Thus, an advance time interval t A =t 5 −t 1  should be provided for turning the controllable commutating switch  30  into the closed/conducting state prior to the controllable power switch  23  being turned into the closed/conducting state.  
           [0186]    The absorption time interval t ABS  lasts till time t 7  when the controllable power switch  23  is triggered into the open/non-conducting state.  
           [0187]    Since being previously discharged to zero, the slope-shaping capacitor  28  pulls the voltage stress off the controllable power switch  23  thus providing the soft-switching zero-voltage-across condition.  
           [0188]    Meanwhile, turning the controllable commutating switch  30  into open/non-conducting state at time t 6  produces substantial switching losses.  
           [0189]    At time t 6  the current through the controllable commutating switch  30  reaches its maximum value defined as:  
             i   29max ( t   6 )= i   30max ( t   6 )= i   22max ( t   6 )+ i   24 ( t   6 )+ u   28max ( t   6 )/( L   29   /C   28 ) −0.5 ,  [20] 
           [0190]    where: u 28max =U OUT  is a maximum value of the voltage across the slope-shaping capacitor  28 .  
           [0191]    Therefore, the maximum values of currents flowing through the components of the active soft-switching conditioner  26  exceed the maximum value of current i 22max  flowing through the power storage inductor  22 .  
           [0192]    The fact that in the continuous current mode within the power storage inductor  22  the components of any active soft-switching conditioner are subjected to substantial electric stress and power losses exhibits second substantial drawback of the prior art to be eliminated by the present invention.  
           [0193]    Moreover, the choice of the inductance value L 29  depends on the properties of the power-blocking rectifier  24  and on its reverse recovery time. Employing the low-frequency, i.e. so-called “slow” rectifiers would result in increase of the inductance value L 29 , therefore, in increase of the stored (and lost!) energy within the damp/resonant choke  29 , in increase of the duration of the closed/conducting state of the controllable commutating switch  30 .  
           [0194]    Further, in a continuous current mode the duration of the switching transitions within the power-blocking rectifier  24  depends on the carried current.  
           [0195]    Therefore, to reduce the impact of the carried current variations upon the switching transition losses, the control circuit should comprise the means to monitor and control the zero-voltage-switching conditions.  
           [0196]    The current mode chosen for the power carrying components of the AC-DC converter depends on the output power draw demand.  
           [0197]    The discontinuous current mode is chosen usually for the low output power applications.  
           [0198]    Nevertheless, due to the pause interval t PAU  it features some important advantages as compared with the continuous current mode. These are as follows:  
           [0199]    the controllable power switch  23  may be turned into the closed/conducting state under the zero-current-through condition since the power storage inductor  22  is current-free during the pause interval tPAU;  
           [0200]    the power blocking rectifier  24  recovers its reverse resistance under the low rate-of-change of the current through it;  
           [0201]    the components of the active soft-switching conditioner  26  are subjected to less switching transition stresses;  
           [0202]    the total switching transition power losses are relatively low.  
           [0203]    Setting the discontinuous current mode within the unitary DC-DC power converter  16  provides zero-current-through condition to the power storage inductor  22  and the power blocking rectifier  24  by the time of turning the controllable power switch  23  into closed/conducting state.  
           [0204]    As a result, the maximum values of currents flowing through the components of the active soft-switching conditioner  26 , i.e. through the damp/resonant choke  29  and the controllable commutating switch  30  are defined only by the properties of the LC-tank L 29  C 28 :  
             i   29max   =i   30max   =u   28max /( L   29   /C   28 ) −0.5 .  [21] 
           [0205]    Besides, due to the fact that in the discontinuous current mode the reverse recovery loss is expired, the “discontinuous” circuit is less sensitive to the impact of the carried current variations.  
           [0206]    Thus, the need to monitor and control the zero-voltage-switching conditions is expired, and the overall control circuitry is substantially simplified.  
           [0207]    The listed above important advantages of the discontinuous current mode are employed by the present invention.  
           [0208]    However, increasing the output power draw in the discontinuous current mode results in substantial increase of the ripple and, therefore, decrease of the power factor.  
           [0209]    The critical current mode features the same drawbacks as the discontinuous current mode.  
           [0210]    These facts exhibit third and fourth substantial drawbacks of the prior art to be eliminated by the present invention.  
           [0211]    For the high output applications the continuous current mode is used by the prior art designs.  
           [0212]    It may provide substantially higher quality of the converted power draw, i.e. the close-to-zero ripple and the close-to-unity power factor.  
           [0213]    However, in this case the prior art AC-DC converter feature all the switching transition drawbacks as above described.  
           [0214]    Besides, operating the AC-DC converter in the continuous current mode needs more complicated and expensive control circuit  200  as well as a high value of inductance for the power storage inductor  22 .  
           [0215]    This fact exhibits fifth substantial drawback of the prior art to be eliminated by the present invention.  
           [0216]    The main, i.e. sixth substantial drawback of the prior art to be eliminated by the present invention is exhibited by the fact that all listed above drawbacks joined in common unbreakably limit an increase of the converted power draw.  
           [0217]    To increase the output power draw the multiple converter topology may be proposed.  
           [0218]    [0218]FIG. 5 illustrates a schematic circuit diagram of a switching-mode AC-DC converter of the modular multi-channel architecture.  
           [0219]    The structures to be considered are listed below:  
           [0220]    [0220] 10 : a primary AC power source;  
           [0221]    [0221] 11 : an input AC-DC rectifier;  
           [0222]    [0222] 12 : a multi-channel DC-DC power converter;  
           [0223]    [0223] 14 : a system load;  
           [0224]    [0224] 16 : a unitary DC-DC power conversion channel;  
           [0225]    [0225] 17 : a system output smoothing filter;  
           [0226]    [0226] 20 : a channel input noise inhibiting filter;  
           [0227]    [0227] 22 : a power storage inductor;  
           [0228]    [0228] 23 : a controllable power switch;  
           [0229]    [0229] 24 : a power blocking rectifier;  
           [0230]    While discussing the operation of the cited device, the further advantage employed by the present invention will be discussed through a comparative appraisal of the syn-phased versus multi-phased modular power conversion systems.  
           [0231]    As shown in FIG. 5, the multi-channel DC-DC power converter  12  contains N&gt;1 number of unitary DC-DC power conversion channels  16 , which are sequentially indexed as  16 ( 1 ), . . . , 16 ( k ), . . . , 16 (N). Each unitary DC-DC power conversion channel  16 ( k ) consumes and delivers only a 1/N-portion of the overall power draw.  
           [0232]    FIGS.  6 ( a,b ) illustrate the nature of the power conversion process within the DC-DC power converter  12  containing N=1 number of unitary DC-DC power conversion channels  16 . It is the same as above described for the single-channel DC-DC power converter  12 .  
           [0233]    It is evident that for satisfying the overall power draw demand in case of N=1, the components of the unitary DC-DC power conversion channel  16  should be performed of a considerably big size, weight and current carrying capability. The current commutating devices should withstand the maximum values of current delivered to the system load  14  as well as the huge electrical stresses.  
           [0234]    In case of N&gt;1 number of the unitary DC-DC power conversion channels  16 ( k ) the components of each may be performed of a relatively small size, weight and of less current carrying capability.  
           [0235]    The maximum values of currents delivered via the commutation devices as well as the degree of electrical stresses are also correspondingly reduced.  
           [0236]    Accordingly, the overall power draw conversion process should be subdivided into N&gt;1 number of unitary sub-processes of the proportionally less performance each, i.e. 1/N-portion, and of the same nature as illustrated in FIGS.  6 ( a,b ).  
           [0237]    In FIG. 5 the unitary DC-DC power conversion sub-processes are ascribed with the input currents i 22(k) (t) being absorbed by power storage inductors  22 ( k ) within the corresponding unitary DC-DC power conversion channels  16 ( k ), and with output currents i 24(k) (t) being delivered to the system load  14  via the corresponding power blocking rectifiers  24 ( k ).  
           [0238]    In a syn-phased system all unitary DC-DC power conversion channels  16 ( k ) operate synchronously and simultaneously to each other, i.e. each unitary DC-DC power conversion channel  16 ( k ) delivers its 1/N-portion of power from the AC primary power source  10  and the input AC-DC rectifier  11  to a system load  14  in a synchronously coincidental (syn-phase) fashion. The syn-phased operation also assumes that all unitary DC-DC power conversion channels  16 ( k ) have common operating frequency of the power-on cycles.  
           [0239]    In the case of in-parallel combined inputs and outputs, as shown at FIG. 5, the input i 22(k) (t) and output i 24(k) (t) currents are summed within respective input and output circuits, i.e. the total i Σ22 (t) amount of current consumed from the primary AC power source  10  may be regarded as:  
                   i     ∑   22            (   t   )       =       ∑     k   =   1     N            i     22        (   k   )              (   t   )           ,           [   22   ]                               
 
           [0240]    and the total i Σ24 (t) amount of current delivered to the system load  14  may be regarded as:  
                 i     ∑   24            (   t   )       =       ∑     k   =   1     N            i     24        (   k   )              (   t   )                 [   23   ]                               
 
           [0241]    As shown in FIG. 6( a,b ), the resultant consumption i Σ22 (t) and delivery i Σ22 (t) currents have N&gt;1 times multiplied direct I Σ22 , I Σ24  and ripple ΔI Σ22 , ΔI Σ24  constituents as compared with those of the single unitary DC-DC power conversion channel, i.e. indexed as i 1/N .  
           [0242]    As related to the primary AC power source  10  and to the system load  14 , the syn-phased multi-channel DC-DC power converter  12  features the same electrical properties as the single-channel DC-DC converter of an equal performance but made of components of a large size, weight and power carrying capacity.  
           [0243]    The main drawback of the syn-phased power conversion systems is that the coincidental operation of the unitary channels creates large instantaneous power draws and large drops in the voltage of the primary power source with the substantial input and output ripple. The amplitude of the resultant primary source voltage drops increases proportionally to the number of the combined inputs. The ripple is caused by the simultaneous overlay of similar non-linear responses from all conversion channels. This is due to the non-linearity of any power conversion process.  
           [0244]    Therefore, this drawback would be eliminated by the present invention.  
           [0245]    In a multi-phase mode of power conversion all channels operate with their power-on cycles time-staggered such that there is a time displacement Δt dspl  interval between the start-on points of the sequential power-on cycles such that:  
           Δ t   dspl   =T   PS   /N .  [24] 
           [0246]    Provided that all unitary DC-DC power conversion channels have similar operating frequency, the resultant summed input and output currents S show substantial improvement from the standpoint of the primary power stress and output ripple constituents. Summing the time-staggered portions of the converted power produces a filtering effect within the input and output circuits of the combined power conversion channels. This is due to the time-staggered overlay of the similar non-linear responses from all conversion channels.  
           [0247]    Therefore, an advantageous low-loss discontinuous current mode may be beneficially employed within the multiple unitary DC-DC power conversion channels combined into a multi-phase AC-DC power conversion system to provide the high quality power draw.  
           [0248]    The important advantage of the multi-phase mode to be employed into the present invention is best illustrated in FIGS. 6, 7 with the comparative appraisal of the nature and features of the power conversion processes performed by the multi-phased DC-DC power converters  12  of equal performance but comprising the different N numbers of unitary DC-DC power conversion channels  16 ( k ).  
           [0249]    The common equal conditions are as follows: The value of the input AC voltage supplied by the primary AC power source  10  is:  
           U AC =120 volts;  
           [0250]    the value of the output power supplied by the DC-DC power converter  12  is:  
           P OUT =1200 watts.  
           [0251]    For better comparison, FIGS.  6 ( a,b ) illustrate the nature and features of the power conversion process within the single-channel DC-DC power converter  12  containing N=1 number of unitary DC-DC power conversion channel  16 . To secure the continuous current mode of operation, the inductance value of the power storage inductor  22  is chosen as:  
             L   22(N=1) =180 μH.  
           [0252]    FIGS.  6 ( c,d ) illustrate the nature and features of the power conversion process within the multi-channel DC-DC power converter  12  containing N=2 number of unitary DC-DC power conversion channels  16 ( k ), i.e. k=1, 2. To insure a discontinuous current mode of operation, the inductance value of the power storage inductors  22 ( k ) is chosen as:  
           L 22(k) =55 μH.  
           [0253]    FIGs.  6 ( e,f ) illustrate the nature and features of the power conversion process within the multi-channel DC-DC power converter  12  containing N=4 number of unitary DC-DC power conversion channels  16 ( k ), i.e. k=1, 2, . . . , 4. To insure the discontinuous current mode of operation, the inductance value of the power storage inductors  22 ( k ) is chosen as:  
           L 22(k) =110 μH.  
           [0254]    FIGS.  6 ( g,h ) illustrate the nature and features of the power conversion process within the multi-channel DC-DC power converter  12  containing N=8 number of unitary DC-DC power conversion channels  16 ( k ), i.e. k=1, 2, . . . , 8. To insure the discontinuous current mode of operation, the inductance value of the power storage inductors  22 ( k ) is chosen as:  
           L 22(k) =180 μH.  
           [0255]    As may be evident in FIGS.  6 ( a,b ), while employing the single-channel DC-DC power converter  12 , it is possible to secure the continuous current i 22 (t) mode at its input only, but not at the output, where the discontinuous i 24 (t) current mode is persistent at any inductance value of the power storage inductor  22 .  
           [0256]    Conversely, as may be evident in FIGS.  6 ( c,d, e,f, g,h ), due to the employment of the multi-phased multi-channel DC-DC power converters  12  it is possible to provide the continuous i Σ22 (t) current mode at the system input and the continuous i Σ24 (t) current mode at the system output while securing the low-loss discontinuous currents i 22(k) (t), i 24(k) (t) modes within each of the separate unitary DC-DC power conversion channels  16 ( k ).  
           [0257]    Besides, referring to FIGS.  6 ( a,b ), it is evident that increasing the output power draw by increasing the number of parallel syn-phased power conversion channels produces a proportional increase of the input and output ripple constituents.  
           [0258]    Referring to FIGS.  6 ( c,d, e,f, g,h ), it is evident that, conversely, an increase of the number of multi-phased power conversion channels produces a substantial decrease of the input and output ripple constituents as compared with a single unitary power conversion channel of the same row.  
           [0259]    [0259]FIG. 7 illustrates the comparative factorized ripple spectrum analysis attributed to the above described power conversion processes performed by the multi-phased DC-DC power converters  12  of an equal performance but of the different N numbers of unitary DC-DC power conversion channels  16 ( k ).  
           [0260]    The values of ripple factor K RPL  are defined as follows:  
                 K     RPL        ∑   22              (   n   )       =         ∑     k   =   1     N            I   .       22        (   k   )        n           I   INDC               [   25   ]                   K     RPL        ∑   24              (   n   )       =         ∑     k   =   1     N            I   .       24        (   k   )        n           I   OUTDC               [   26   ]                               
 
           [0261]    where: n is a harnonic number;  
           [0262]    K RPLΣ22 (n) is a value for the input ripple factor of an n-th harmonic;  
           [0263]    K RPLΣ24 (n) is a value for the output ripple factor of an n-th harnonic;  
           [0264]    I 22(k)n  is an amplitude of an n-th harmonic constituent of the i 22(K) (t) current of the power storage inductor  22 ( k ) within the k-th unitary power conversion channel  16 ( k );  
           [0265]    I 24(k)  is an amplitude of an n-th harmonic constituent of the i 24(K) (t) current of the power blocking rectifier  24  within the k-th unitary power conversion channel  16 ( k );  
           [0266]    I INDC  is a value of the direct current constituent of the current consumed by the DC-DC power converter  12 ;  
           [0267]    I OUTDC  is a value of the direct current constituent of the current delivered by the DC-DC power converter  12 .  
           [0268]    Referring to FIG. 7 it is evident that the discontinuous-mode multi-channel multi-phased AC-DC conversion systems exhibit the substantially reduced values of the input and output ripple factors as compared with a continuous-mode single-channel systems performance.  
           [0269]    Moreover, the comparison of the factorized ripple spectrums corresponding to different N numbers of multi-phased AC-DC conversion channels, as shown in FIGS.  7 ( c,d, e,f, g,h ), exposes the substantial reduction of the amount of the ripple harmonics, i.e. EMI noise within the input and output spectrums correspondingly to the increase of N number.  
           [0270]    It is evident that correspondingly to the N number increase the overall system power factor increases.  
           [0271]    Therefore, securing the discontinuous current mode within each of the multiple unitary AC-DC power conversion channels and arranging their operation in a multi-phase fashion provides the substantial reduction of ripple constituents within the input and output power draws as compared with the continuous-mode single-channel system of the same overall performance. The degree of such a reduction is also corresponding to the N number of channels combined.  
           [0272]    Besides, the important advantages of the low-loss discontinuous current mode, as described above, may be exploited in a full scale.  
           [0273]    The further important advantages of the multi-channel multi-phase system design are as follows:  
           [0274]    a provision of an opportunity to develop the systems of a substantially increased overall performance;  
           [0275]    an increase of the current carrying capability of the commutating components;  
           [0276]    an employment of the components of a less power carrying capability;  
           [0277]    a reduction of the overall power losses;  
           [0278]    a provision of an even dissipation of residual power losses;  
           [0279]    a provision of an even dissipation of heat dissipating localities;  
           [0280]    an elimination of the local over-heat spots;  
           [0281]    a reduction of the components temperature;  
           [0282]    an elimination of the need to employ the complex cooling systems;  
           [0283]    an increase of the overall system efficiency;  
           [0284]    an increase of the overall system reliability;  
           [0285]    a simplicity of increasing the overall system performance by purely connecting the additional modules;  
           [0286]    a simplicity of maintenance and repair by purely replacing the faulty module;  
           [0287]    a reduction of the system failure factor;  
           [0288]    a reduction of the complexity of manufacture;  
           [0289]    a reduction of the design and manufacture costs due to the enhanced standardization of the routine procedures.  
           [0290]    Therefore, what is needed in the art is a circuit concept and a method of the AC-DC power conversion to embrace all above described advantages in a beneficially synergetic fashion.  
           [0291]    It is, therefore, an object of the present invention to provide a multi-channel multi-phase AC-DC power conversion system of the enhanced performance in sense of the overall capacity and efficiency increase.  
           [0292]    Implementations of the present invention may feature the following beneficial properties: an increase of the power factor up to the unity value; the degree of the increase is proportional to the quantity of the power conversion channels combined; a boundless increase of the overall system capacity proportionally to the quantity of the power conversion channels combined; an expiration of all sorts of constraints upon the system capacity increase; a reduction of the harmonic and non-linear distortions regardless of the discontinuous current mode within the unitary AC-DC power conversion channels; the degree of the reduction is proportional to the amount of the power conversion channels combined; an additional reduction of the output ripple due to the opportunity to increase the value of the auto-transformation factor assigned to the power storage inductors within the unitary AC-DC power conversion channels; a reduction of the EMI noise;  
           [0293]    an improvement of the filtering efficiency;  
           [0294]    a provision of the soft-switching conditions for the current commutating components within the power conversion channels combined;  
           [0295]    a reduction of the complexity of the soft-switching conditioning circuitry due to the expiration of a need to monitor the zero-voltage-across conditions;  
           [0296]    an increase of the overall efficiency due to the low-loss discontinuous current mode within each of the unitary AC-DC power conversion channels; the degree of the increase is proportional to the quantity of the power conversion channels combined;  
           [0297]    an increase of the power conversion operating frequency assigned for the separate unitary power conversion channels due to the low-loss discontinuous current mode within each of them;  
           [0298]    1) a reduction of the filtering components volume;  
           [0299]    a reduction of other components size, weight and power carrying capacity;  
           [0300]    a better employment of the components properties due to the reduction and even distribution of the heat dissipation;  
           [0301]    a better employment of the components capacities resulted of their electric parameters due to reduction of the electrical stress upon the current carrying components;  
           [0302]    a employment of the conventional off-the-shelf micro-chip APFC-controllers designed for the single-channel AC-DC power converters.  
           [0303]    In general, in one aspect of the present invention, the listed advantages may be achieved through the following approaches.  
           [0304]    As compared with a traditional single-channel AC-DC power converter employing the continuous current mode within the power storage inductor, the corresponding single power draw conversion process of the desired capacity should be subdivided into N&gt;1 number of the unitary sub-processes of the proportionally (1/N-portion) less performance each.  
           [0305]    Further, each unitary sub-process should be assigned to a separate unitary AC-DC power conversion channel designed of the less capacitive components as compared with a traditional single-channel AC-DC power converter.  
           [0306]    This is to eliminate the constraints produced by the components power carrying capacity upon the operating frequency and overall power draw increase, which are persistent to the prior art. Moreover, this is to resolve the opportunity of employing the components though of the less power carrying capacity but of the better specific properties.  
           [0307]    Besides, these components may be of a substantially smaller size, and, due to the modern micro-technologies, and regardless of their quantity increase, may be enclosed into the substantially smaller package.  
           [0308]    Each unitary power conversion channel should incorporate a power storage inductor of a tapped auto-transformatory choke design. This is to reduce the degree of the electrical stress upon the power carrying components, therefore, to provide a better use of the components capacities resulted of their electric parameters. Besides, this is to reduce all sorts of high frequency output ripple due to the fact that the auto-transformatory choke design of the power storage inductor provides an increase of the release factor value [11], i.e. better release of the magnetically stored energy.  
           [0309]    Each unitary power conversion channel should incorporate a soft-switching conditioning circuit.  
           [0310]    Further, the multiple unitary power conversion channels should be combined into a resultant AC-DC power conversion system of the desired capacity, i.e. equal to that of the traditional single-channel AC-DC power converter.  
           [0311]    Further, the discontinuous current mode should be provided to each of the multiple unitary power conversion channels. This is to reduce the electrical stress upon the power carrying components and the switching transition losses within the soft-switching conditioning circuits. The components of these circuits may be, therefore, of a less power carrying capacity.  
           [0312]    Further, the multi-phase mode of operating the unitary channels should be provided to the resultant AC-DC power conversion system. This is to increase the power factor value and the system efficiency.  
           [0313]    Further, the soft-switching conditions should be provided to the current commutating components within the unitary channels. This is to eliminate the switching transition losses within these components.  
           [0314]    The further, i.e. a synergetic advantage of the present invention is that the discontinuous current mode within each of the unitary DC-DC power conversion channels naturally provides an optimal distribution of the overall power draw.  
           [0315]    Conversely to the continuous current mode, the discontinuous one eliminates the need to employ the additional feedback loops and corresponding complex circuitry.  
           [0316]    The amount of power delivered by each unitary DC-DC power conversion channel depends on the inductance value of the power storage inductor and on the power absorption time-interval.  
           [0317]    Naturally, provided that all power storage inductors are of the same inductance value and power absorption time-intervals are of the same duration, the overall power draw is evenly distributed among the unitary power conversion channels.  
           [0318]    In general, in another aspect of the present invention, the modified AC-DC power converters should comprise at least:  
           [0319]    an input means for being connected to the primary AC power source;  
           [0320]    an output means for being connected to the system load;  
           [0321]    a common return bus for being connected between the AC-DC power converter and a system load;  
           [0322]    an input AC-DC rectifier to transform the sine-wave of the AC primary power source voltage into a half-sine-wave of the rectified voltage;  
           [0323]    a multi-channel DC-DC converter;  
           [0324]    a system output smoothing filter;  
           [0325]    a system control means;  
           [0326]    a system synchronization means;  
           [0327]    a multi-channel DC-DC converter should comprise an N&gt;1 number of the unitary DC-DC power conversion channels;  
           [0328]    the input nodes of the unitary DC-DC power conversion channels should be parallel-connected to the output node of the input AC-DC rectifier;  
           [0329]    the output nodes of the unitary DC-DC power conversion channels should be parallel-connected to the input node of the system output smoothing filter;  
           [0330]    a unitary DC-DC power converter should comprise at least:  
           [0331]    a channel noise inhibiting filter;  
           [0332]    a power storage inductor to accumulate the power absorbed from the primary AC power source and to release the magnetically stored energy to the system load;  
           [0333]    an inductance value L of the power storage inductor should be chosen definitely for securing the discontinuous current mode of operation within each unitary DC-DC power conversion channel, and, therefore, for minimizing the switching transition losses within the current commutating devices;  
           [0334]    a controllable power switch operated in an ON-OFF fashion and alternatively turned into conducting state to provide the power absorption from the primary AC power source into the power storage inductor, and turned into non-conducting state to provide th of the magnetically stored energy from the power storage inductor to the system load;  
           [0335]    a power blocking rectifier to disconnect the system load from the power storage inductor and from the primary AC power source while the controllable power switch is conducting, and to provide a power release path from the power storage inductor to the system load while the controllable power switch is non-conducting;  
           [0336]    a channel output smoothing filter to store the power delivered to the system load and to absorb the ripple component of the delivered power;  
           [0337]    an active soft-switching conditioner connected via its nodes across both the controllable power switch and the power blocking rectifier to provide an active shaping their operating points trajectories through an active development of the soft-switching zero-voltage-across/zero-current-through conditions during the time intervals of the alternative transitions between the conducting and non-conducting states;  
           [0338]    an active soft-switching conditioner should comprise at least:  
           [0339]    a slope-shaping capacitor;  
           [0340]    a damp-resonant choke;  
           [0341]    a controllable commutating switch;  
           [0342]    a shunting rectifier;  
           [0343]    a separating rectifier;  
           [0344]    a system control means should comprise at least:  
           [0345]    an active power factor correction (APFC) controller to accept the functional input signals and to provide the AC-DC power conversion system with an output ON-OFF control signal such that each unitary DC-DC power conversion channel should maintain its proper performance to secure the overall system output quality, i.e. high power factor value and output voltage stability;  
           [0346]    an ON-state pulse duration of the ON-OFF control signal should be equal to the absorption time interval t ABS , i.e. to correspond to the close/conducting state of the time-staggered operated controllable power switches, and the period of the ON-state pulses of the ON-OFF control signal should be equal to the controllable power switch operation period T PS , i.e. to the period of the common operating frequency;  
           [0347]    this ON-OFF control signal should be further applied to the system synchronization means;  
           [0348]    the system synchronization means should conformly reproduce N times the ON-OFF control signal produced by the APFC-controller, and should timely stagger its conformable copies for being distributed to all unitary DC-DC power conversion channels of the system; these copies should form a first set of the synchronizing signals, i.e. the set of the ON-OFF t ABS -signals which are timely staggered such that a time-displacement interval Δt dspl =T PS /N should exist between the leading edges of the ON-state pulses of the sequential time-staggered copies;  
           [0349]    the system synchronization means should conformly produce the second set of the synchronizing ON-OFF signals; the second set should contain N number of the ON-OFF signals; these signals should be evenly time-staggered such that a time-displacement interval Δt dspl =T PS /N should exist between the leading edges of the ON-state pulses of the sequential time-staggered signals; the ON-state pulse duration of such a signal should be equal to the soft-switching time interval t SS , i.e. to correspond to the closed/conducting state of the controllable commutating switch within the active soft-switching conditioner, and the period of the ON-state pulses of these t SS -signals should be also equal to T PS ;  
           [0350]    the system synchronization means should provide the AC-DC power conversion system with two sets of the ON-OFF synchronizing signals for operating the unitary DC-DC power conversion channels in a time-staggered fashion; each set should contain N number of signals;  
           [0351]    the synchronizing signals of the first set should operate the controllable power switches within the corresponding unitary DC-DC power conversion channels; as a result, the unitary power conversion processes within the sequential unitary DC-DC power conversion channels should be timely staggered such that a time-displacement interval Δtspl=T PS /N should exist between the start-points of the power-on cycles within the sequential channels in the row;  
           [0352]    the synchronizing signals of the second set should operate the controllable commutating switches within the active soft-switching conditioners within the corresponding unitary DC-DC power conversion channels;  
           [0353]    the system synchronization means should distribute the synchronizing signals across the AC-DC power conversion system such that one Δt ABS -signal of the first set and one t SS -signal of the second set should be provided to each unitary DC-DC power conversion channel;  
           [0354]    each pair of one t ABS -signal and one t SS -signal should be timely arranged such that a leading edge of the ON-state pulse of the t SS -signal should precede the leading edge of the ON-state pulse of the t ABS -signal for an advance time interval t A  as a result, the controllable commutating switch of the active soft-switching conditioner should be turned into the close/conducting state prior to the controllable power switch being turned into the closed/conducting state;  
           [0355]    therefore, within the advance time interval t A  the slope-shaping capacitor within the active soft-switching conditioner should discharge in a resonant fashion thus providing a zero-voltage-across condition to the controllable power switch during its transition from the open/non-conducting to the closed/conducting state;  
           [0356]    the ON-state pulse of the t SS -signal should cease past the ON-state pulse of the t ABS -signal having started, i.e. the controllable commutating switch of the active soft-switching conditioner should be turned into open/non-conducting state past the controllable power switch having been reliably turned into the closed/conducting state;  
           [0357]    therefore, the trailing edge of the ON-state pulse of the t SS -signal should recede the leading edge of the ON-state pulse of the t ABS -signal in a lag time interval t L ;  
           [0358]    the control means of the AC-DC power conversion system should comprise the means for preventing the operation of all controllable switches within all unitary DC-DC power conversion channels, i.e. for inhibiting the power conversion process in case the value of the system output voltage incidentally exceeds the preset maximum threshold,  
           [0359]    and for encouraging the operation of all controllable switches within all unitary DC-DC power conversion channels as soon as the system output voltage recovers the operating value, i.e. for restoring the power conversion process as soon as the system output voltage falls below the preset minimum threshold in a hysteresis fashion.  
           [0360]    In general, according to the discussed aspect of the present invention, the power storage inductors within all unitary DC-DC power conversion channels may be of a tapless choke design. This may be appropriate for the cheapest embodiments of the present invention. Due to the multi-phased operation and the discontinuous current mode secured within the multiple power conversion channels, the bulk of the discussed advantages will be also provided.  
           [0361]    In general, in another aspect of the present invention, the power storage inductors within all unitary DC-DC power conversion channels may be of a tapped auto-transformatory choke design ascribed with the auto-transformation factor n 2/1 &gt;1;  
           [0362]    an inductance value L 1  of the primary power carrying winding within the power storage inductor should be chosen definitely for securing the discontinuous current mode of operation within each unitary DC-DC power conversion channel, therefore, for minimizing the switching transition losses within the current commutating devices, and for reducing the electrical stress upon the power carrying components, and for employing the components with less power carrying capability, and for enhancing the employment of components capacities resulted of their electric parameters, and for reducing the output ripple due to the opportunity to increase the value of the auto-transformation factor n 2/1 .  
           [0363]    In general, in another aspect of the present invention, to secure the low-loss discontinuous current mode, each unitary DC-DC power conversion channel should comprise a means to detect the non-zero i RLS (t) release current flow within the power storage inductor during the release time interval t RLS  of releasing the magnetically stored energy to the system load; the synchronization means of the AC-DC power conversion system should comprise the means to postpone the successive operating cycle for indefinite postponement time interval t pp , i.e. to eliminate turning the controllable switches within any unitary DC-DC power conversion channel into conducting state, prior to the i RLS (t) release current flow within the corresponding power storage inductor reaches zero.  
           [0364]    In general, due to the fact that various APFC-controllers have been designed to satisfy the special applications needs, these may be successfully employed within the embodiments of the present invention, therefore, expiring the need to design the specialized control circuitry for any special embodiment of the present invention.  
           [0365]    According to the primary application aim, there are several main types of the APFC-controllers.  
           [0366]    Each type is designed to secure the corresponding mode of the current conduction within the single monitored power conversion channel, i.e. the discontinuous current mode, or critical current mode, or continuous current mode, or any combination of these.  
           [0367]    All types of the existing APFC-controllers may be easily accommodated to the embodiments of the present invention.  
           [0368]    To employ the APFC-controller available or preferred for any special reason, the control means of the AC-DC power converter may be simply modified according to the special case.  
           [0369]    Therefore, in another aspect of the present invention, the control means may comprise a conventional “off-the-shelf” APFC-controller designed to secure the discontinuous current mode within the traditional single-channel AC-DC power converter; to provide such a conventional “discontinuous current mode” APFC-controller with appropriate feed-back signals, the first-in-the-row appointed unitary DC-DC power conversion channel should comprise a current-sensing means to monitor the current flow within its power storage inductor through monitoring the current flows within both its controllable power switch and power blocking rectifier; further, the ON-OFF control signal produced by such a conventional “discontinuous current mode” APFC-controller should be conformly reproduced N times and its conformable copies should be timely staggered and distributed to all other unitary DC-DC power converters of the row.  
           [0370]    In another aspect of the present invention, the control means may comprise a conventional “off-the-shelf” APFC-controller designed to secure the continuous current mode within the traditional single-channel AC-DC power converter;  
           [0371]    to provide such a conventional “continuous current mode” APFC-controller with appropriate feed-back signals, the first-in-the-row appointed unitary DC-DC power conversion channel should comprise a current-sensing means to monitor the current flow within its power storage inductor through monitoring the current flows within both its controllable power switch and power blocking rectifier, a current sensing means to monitor the total current consumed by the multi-channel DC-DC converter, and a current signals summator to produce a resultant feed-back signal conformable to that of the single-channel AC-DC converter of the equal capacity; further, the ON-OFF control signal produced by such a conventional “continuous current mode” APFC-controller should be conformly reproduced N times and its conformable copies should be timely staggered and distributed to all other unitary DC-DC power converters in the row.  
           [0372]    In another aspect of the present invention, concerning the special applications, the multi-channel multi-phase AC-DC power converter may be particularly designed to maintain the critical current mode and a variable operating frequency within its unitary DC-DC power conversion channels;  
           [0373]    accordingly, the control means of the AC-DC power conversion system should comprise a conventional “off-the-shelf” APFC-controller designed to secure the critical current mode within the traditional single-channel AC-DC power converter;  
           [0374]    the system synchronization means should additionally comprise a voltage controlled oscillator (VCO), a frequency divider-by-M, a phase comparator and an integrating filter;  
           [0375]    the latter should be connected in a phase-locked loop to produce a VCO output clocking signal of an M-times higher frequency than that of the ON-OFF control signal produced by the APFC-controller;  
           [0376]    further, the ON-OFF control signal produced by such a conventional “critical current mode” APFC-controller should be conformly reproduced N times and its conformable copies should be timely staggered and distributed to all other unitary DC-DC power converters of the row.  
           [0377]    It is evident, that there is no need to design any specialized “multi-phase” APFC-controller to embody the present invention.  
           [0378]    Concerning the quantity, i.e. N number of the unitary DC-DC power conversion channels combined within the multi-phase DC-DC converter, it may only depend on the qualitative considerations such as an amount of power to be processed, a power factor value to be secured and a total efficiency to be provided.  
           [0379]    Within each unitary DC-DC power conversion channel the controllable power switch and the controllable commutating switch may be performed as the solid-state semiconductor switches like MOSFETs.  
           [0380]    The body diode of the solid-state semiconductor switch may be used as the shunting rectifier connected across the controllable commutating switch within the active soft-switching conditioner of the unitary DC-DC power conversion channel.  
           [0381]    The high-power pulse diode may be used as the power blocking rectifier and the separating rectifier within the active soft-switching conditioners of the unitary DC-DC power conversion channels.  
           [0382]    It is a further object of the present invention to provide an improved method of the AC-DC power conversion with an active power factor correction; the method comprises the following steps:  
           [0383]    a) defining the overall AC-DC power conversion system configuration;  
           [0384]    b) defining the optimal N&gt;1 number of unitary DC-DC power conversion channels to be included into the AC-DC power conversion system;  
           [0385]    c) defining the current mode within the unitary DC-DC power conversion channels;  
           [0386]    d) defining the proper type and design of the APFC-controller;  
           [0387]    defining the control means configuration;  
           [0388]    defining the synchronization means configuration;  
           [0389]    providing the APFC-controller with the appropriate functional input signals to provide the AC-DC power conversion system with a resultant, i.e. APFC-controller produced, ON-OFF control signal such that each unitary DC-DC power conversion channel should maintain its proper performance to secure the overall system output quality, i.e. high power factor and output voltage stability; the ON-state pulse duration of the ON-OFF control signal should be equal to the absorption time interval t ABS , i.e. to correspond to the close/conducting state of the time-staggered controllable power switches, and the period of the ON-state pulses of the ON-OFF control signal should be equal to the controllable power switch operation period T PS , i.e. to the period of the common operating frequency; this ON-OFF control signal should be further applied to the system synchronization means;  
           [0390]    conformly reproducing N times the ON-OFF control signal produced by the APFC-controller and timely staggering its conformable copies to be distributed to all other unitary DC-DC power conversion channels of the system; these copies should form a first set of synchronizing signals, i.e. the set of the ON-OFF t ABS -signals which are timely staggered such that a time-displacement interval Δt dspl =T PS /N should exist between the leading edges of the ON-state pulses of the sequential time-staggered copies; this is to be performed by the system synchronization means;  
           [0391]    conformly producing the second set of the synchronizing ON-OFF signals; the second set should contain N number of the ON-OFF signals; these signals should be evenly time-staggered such that a time-displacement interval Δt dspl =T PS /N should exist between the leading edges of th ON-state pulses of the sequential time-staggered signals; the ON-state pulse duration of such a signal should be equal to the soft-switching time interval t SS , i.e. to correspond to the closed/conducting state of the controllable commutating switch within the active soft-switching conditioner, and the period of the ON-state pulses of these t SS -signals should be also equal to T PS ;  
           [0392]    providing the power conversion system with two sets of the ON-OFF synchronizing signals produced by the system synchronization means to operate the unitary DC-DC power conversion channels in a time-staggered fashion; each set should contain N number of signals operating the controllable power switches within the corresponding unitary power conversion channels with the synchronizing signals of the first set; as a result, the power conversion processes within the sequential unitary DC-DC power conversion channels should be timely staggered such that a time-displacement interval Δt dspl =T PS /N should exist between the start-points of the power-on cycles within the sequential channels in the row;  
           [0393]    operating the controllable commutating switches of the active soft-switching conditioners within the corresponding unitary power conversion channels with the synchronizing signals of the second set;  
           [0394]    m) distributing the synchronizing signals across the AC-DC power conversion system such that one t ABS -signal of the first set and one t SS -signal of the second set should be provided to each corresponding unitary DC-DC power conversion channel;  
           [0395]    arranging timely each pair of one t ABS -signal and one t SS -signal such that a leading edge of the ON-state pulse of the t SS -signal should precede the leading edge of the ON-state pulse of the t ABS -signal for an advance time interval t A ; as a result, the controllable commutating switch of the active soft-switching conditioner should be turned into the close/conducting state prior to the controllable power switch being turned into the closed/conducting state; therefore, within the advance time interval t A  the slope-shaping capacitor of the active soft-switching conditioner should discharge in a resonant fashion thus providing a zero-voltage-across condition to the controllable power switch during its transition from the open/non-conducting state to the closed/conducting state;  
           [0396]    ceasing the ON-state pulse of the t SS -signal past the ON-state pulse of the t ABS -signal having started, i.e. the controllable commutating switch of the active soft-switching conditioner should be turned into the open/non-conducting state past the controllable power switch having been reliably turned into closed/conducting state;  
           [0397]    as a result of the above described steps, the individual power conversion processes within the multiple unitary power conversion channels should be evenly time-staggered across the period of the common operating frequency; therefore, while securing the discontinuous or critical current mode within the individual channels, the continuous current mode should be provided both to the primary AC power source and to the system load; the waveform of the resultant AC current consumed by the novel AC-DC power conversion system should be substantially conformable and synchronous to the sinusoidal waveform of the AC voltage provided by the primary power source; securing the discontinuous or critical current mode within the individual power conversion channels should result in minimizing the switching transition losses, i.e. the overall system efficiency is substantially high; the power carrying components may, therefore, be of a less size, weight and power carrying capacity; an effective, i.e. “virtual” power conversion frequency of the system is, therefore, N times higher than the common operating one of the separate unitary power conversion channels; the ripple should substantially low; the resultant quality of the overall power draw should be substantially high; the filtering components may be of a substantially less size and weight;  
           [0398]    detecting the non-zero i RLS (t) release current flow within the power storage inductor during the release time interval t RLS  of releasing the magnetically stored energy;  
           [0399]    postponing the successive operating cycle for indefinite postponement time interval t pp  to eliminate turning the controllable switches within any unitary DC-DC power conversion channel into the closed/conducting state prior to the i RLS (t) release current flow within the corresponding power storage inductor reaches zero, therefore, to secure the low-loss discontinuous current mode;  
           [0400]    preventing the operation of all controllable switches within all unitary DC-DC power conversion channels, i.e. inhibiting the power conversion process in case the value of the system output voltage incidentally exceeds the preset maximum threshold, and encouraging the operation of all controllable switches within all unitary DC-DC power conversion channels, i.e. restoring the power conversion process as soon as the system output voltage falls below the preset minimum threshold in a hysteresis fashion.  
           [0401]    An advantage of the present invention is that it provides both an improved method and a circuit concept to provide a novel multi-channel AC-DC power conversion system of the enhanced capacity, efficiency and performance.  
           [0402]    Due to the fact that securing the discontinuous or critical current mode within the individual power conversion channels results in minimizing the switching transition losses, the overall system efficiency is substantially high. The power carrying components may, therefore, be of a less size, weight and power carrying capacity.  
           [0403]    Due to the fact that individual power conversion processes within the multiple unitary power conversion channels are evenly time-staggered across the period of the common operating frequency while securing the discontinuous or critical current mode within the individual channels, the continuous current mode is provided both to the primary AC power source and to the system load; the waveform of the resultant AC current consumed by the novel AC-DC power conversion system is substantially conformable and synchronous to the sinusoidal waveform of the AC voltage provided by the primary AC power source. Therefore, the resultant quality of the overall power draw is substantially high.  
           [0404]    Due to the fact that an effective, i.e. “virtual” power conversion frequency of the system is, therefore, N times higher than that of the separate unitary power conversion channel, the ripple is substantially low and the filtering components may be of a substantially less size and weight.  
           [0405]    The foregoing and other objects, features and advantages of the present invention will become more readily apparent to those skilled in the art from the following detailed description of the preferred embodiments of the present invention which proceeds with the reference to the accompanying drawings.  
           [0406]    Additional features of the invention will be described hereinafter that form the subject of the claims of the present invention.  
           [0407]    Those skilled in the art should appreciate that they can readily use the disclosed concepts and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent designs and constructions do not depart from the spirit and scope of the present invention in its broadest form.  
           [0408]    In view of the discussed considerations, the present invention aims to eliminate the drawbacks and constraints persistent in the present state-of-the-art.  
           [0409]    The foregoing and other objects, features and advantages of the present invention will become more readily apparent to those skilled in the art from the following detailed description of the preferred embodiments of the present invention which proceeds with the reference to the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0410]    [0410]FIG. 1 illustrates the circuit diagram of the prior art traditional full-bridge AC-DC rectifier.  
         [0411]    [0411]FIG. 2 illustrates the time-scaled waveforms of current and voltages attributed to the prior art traditional full-bridge AC-DC rectifier.  
         [0412]    [0412]FIG. 3 illustrates the circuit diagram of the prior art switching-mode pulse-width-modulated AC-DC power converter incorporating a means for active power factor correction and soft-switching conditioning.  
         [0413]    [0413]FIG. 4 illustrates the time-scaled waveforms of currents and voltages attributed to the prior art switching-mode pulse-width-modulated AC-DC power converter incorporating a means for active power factor correction and soft-switching conditioning.  
         [0414]    [0414]FIG. 5 illustrates the circuit block-diagram of the prior art switching-mode pulse-width-modulated AC-DC power converter of the modular multi-channel architecture.  
         [0415]    [0415]FIG. 6 illustrates the time-scaled waveforms of currents and voltages attributed to the prior art switching-mode pulse-width-modulated AC-DC power converter of the modular multi-phase architecture.  
         [0416]    [0416]FIG. 7 illustrates the factorized ripple spectrum attributed to the switching-mode pulse-width-modulated AC-DC power converter of the modular multi-phase architecture.  
         [0417]    [0417]FIG. 8 illustrates the circuit diagrams of the various embodiments of the switching-mode pulse-width-modulated AC-DC power converter according to the present invention.  
         [0418]    [0418]FIG. 9 illustrates the timing diagrams describing the nature of the AC-DC power conversion process performed by the embodiments of the switching-mode pulse-width-modulated AC-DC power converter according to the present invention.  
         [0419]    [0419]FIG. 10 illustrates the timing diagrams describing the operation of the synchronization circuit incorporated into the embodiments of the switching-mode pulse-width-modulated AC-DC power converter according to the present invention.  
         [0420]    [0420]FIG. 11 illustrates the time-scaled waveforms of currents and voltages attributed to the power conversion processes within the embodiments of the switching-mode AC-DC power converter according to the present invention.  
         [0421]    [0421]FIG. 12 illustrates the principle of operating the multiple unitary power conversion channels within the embodiments of the switching-mode AC-DC power converter according to the present invention.  
         [0422]    [0422]FIG. 13 illustrates the principle of providing the high quality continuous current mode to the primary AC power source while securing the discontinuous current mode within the separate unitary DC-DC power conversion channels. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0423]    In the embodiments of the proposed invention shown in FIG. 8 the indexed structures to be considered are as follows:  
         [0424]    [0424] 10 : a primary AC power source;  
         [0425]    [0425] 11 : an input AC-DC rectifier;  
         [0426]    [0426] 12 : a multi-channel DC-DC power converter;  
         [0427]    [0427] 14 : a system load;  
         [0428]    [0428] 16 : a DC-DC power conversion channel;  
         [0429]    [0429] 17 : a system output smoothing filter;  
         [0430]    [0430] 20 : a channel input noise inhibiting filter;  
         [0431]    [0431] 22 : a power storage inductor;  
         [0432]    [0432] 23 : a controllable power switch;  
         [0433]    [0433] 24 : a power blocking rectifier;  
         [0434]    [0434] 25 : a channel output smoothing filter;  
         [0435]    [0435] 26 : an active soft-switching conditioner;  
         [0436]    [0436] 27 : a shunting rectifier;  
         [0437]    [0437] 28 : a slope-shaping capacitor;  
         [0438]    [0438] 29 : a damp/resonant choke;  
         [0439]    [0439] 30 : a controllable commutating switch;  
         [0440]    [0440] 31 : a separating rectifier;  
         [0441]    [0441] 32 : a zero-current detector;  
         [0442]    [0442] 33 : a non-zero-current detector;  
         [0443]    [0443] 34 : a current-sensing transformer;  
         [0444]    [0444] 40 : a total consumption current sensor;  
         [0445]    [0445] 41 : a current signal summing device  
         [0446]    [0446] 42 : first summing resistor;  
         [0447]    [0447] 43 : second summing resistor;  
         [0448]    [0448] 44 : a DC inhibiting capacitor;  
         [0449]    [0449] 100 : an AC-DC power converter;  
         [0450]    [0450] 200 : a control circuit;  
         [0451]    [0451] 201 : an active power factor correction (APFC) controller;  
         [0452]    [0452] 202 : a signal conditioning resistor;  
         [0453]    [0453] 203 : a signal conditioning resistive divider;  
         [0454]    [0454] 204 : an over-voltage detector;  
         [0455]    [0455] 300 : a synchronization circuit;  
         [0456]    [0456] 301 : a clock pulse oscillator;  
         [0457]    [0457] 302 : a primary shift register;  
         [0458]    [0458] 303 : a primary logic gate;  
         [0459]    [0459] 304 : a secondary shift register;  
         [0460]    [0460] 305 : a secondary logic gate.  
         [0461]    [0461] 306 : a voltage controlled oscillator (VCO);  
         [0462]    [0462] 307 : a frequency divider;  
         [0463]    [0463] 308 : a phase comparator;  
         [0464]    [0464] 309 : an integrating filter.  
         [0465]    According to the first Embodiment of the present invention, FIG. 8( a ) illustrates a circuit diagram of a multi-channel AC-DC converter  100  comprising a conventional APFC controller  201  designed to implement the discontinuous current mode within a conventional single-channel AC-DC power converter of a pulse width modulation type.  
         [0466]    Prior to the detailed description of the system design and operation, the key structures will be identified.  
         [0467]    Referring to FIG. 8( a ), the AC-DC power converter  100  includes input AC-DC rectifier  11 , a multi-channel DC-DC power converter  12 , a system output smoothing filter  17 , a control circuit  200  and a synchronization circuit  300 . The multi-channel DC-DC power converter  12  includes N&gt;1 number of DC-DC power conversion channels  16 , which are sequentially indexed as  16 ( 1 ), . . . ,  16 ( k ), . . . ,  16 (N) such that k=1, 2, . . . , N.  
         [0468]    Each DC-DC power conversion channel  16 ( k ) includes a channel input noise inhibiting filter  20 ( k ), a power storage inductor  22 ( k ), a controllable power switch  23 ( k ), a power blocking rectifier  24 ( k ), a channel output smoothing filter  25 ( k ), an active soft-switching conditioner  26 ( k ) and a zero-current detector  32 ( k ).  
         [0469]    In addition, power channel  16 ( 1 ) includes a non-zero-current detector  33 .  
         [0470]    The control circuit  200  consists of an active power factor correction (APFC) controller  201 , a signal conditioning resistor  202 , a signal conditioning resistive divider  203  and an over-voltage detector  204 .  
         [0471]    The synchronization circuit  300  consists of a clock pulse oscillator (CPO)  301 , a primary shift register  302 , N number of primary logic gates  303 , which are sequentially indexed as  303 ( 1 ), . . . ,  303 ( k ), . . . ,  303 (N), N number of secondary shift registers  304  which are sequentially indexed as  304 ( 1 ), . . .  304 ( k ),  304 (N), and N number of secondary logic gates  305  which are sequentially indexed as  305 ( 1 ), . . .  305 ( k ), . . . ,  305 (N).  
         [0472]    The input AC-DC rectifier  11 , the multi-channel DC-DC converter  12  with DC-DC power conversion channels  16 ( k ), the system output filter  17  and the system load  14  are connected each by their common return nodes to a common return bus.  
         [0473]    The input nodes of the input AC-DC rectifier  11  are connected to a primary AC power source  10  such as AC mains.  
         [0474]    The input nodes of the DC-DC power conversion channels  16 ( k ) are parallel-connected to an output node of the input AC-DC rectifier  11 .  
         [0475]    The output nodes of the DC-DC power conversion channels  16 ( k ) are parallel-connected to the system output filter  17 .  
         [0476]    The output node of the system output filter  17  is connected to the input node of the system load  14 .  
         [0477]    The components of each DC-DC power conversion channel  16 ( k ) are configured in a boost converter topology featuring the following distinctions in comparison with a conventional configuration shown in FIG. 3: a power carrying coil of the power storage inductor  22 ( k ) is of the tapped auto-transformer type consisting of two coils such that the coil W′ provides a primary auto-transformer winding and both series-connected coils W′ and W″ provide a secondary auto-transformer winding; the numbers of turns on each of the coils W′ and W″ define the auto-transformation factor n 2/1  such that:  
           n   2/1 =( w′+w″ )/ w′=w   2   /w   1 ,  [27] 
         [0478]    where: w′ is the number of turns of coil W′;  
         [0479]    w″ is the number of turns of coil W″;  
         [0480]    w 1 =w′;  
         [0481]    w 2 =w′+w″;  
         [0482]    an inductance value L 1  of the primary power carrying winding w 1  within each power storage inductor  22 ( k ) is chosen such that the low loss discontinuous current mode is assured within each power storage inductor over the full range of operational current variation; the method of selecting the value for L 1  will be discussed in later paragraphs;  
         [0483]    c) Regarding auto-transformer operation, coil W′ defines an inductance value L 1  of the primary auto-transformer winding, and both series-connected coils W′ and W″ define an inductance value L 2  of the secondary auto-transformer winding such that:  
           L   2   =n   2/1   2   L   1 ;  [28] 
         [0484]    the power storage inductor  22 ( k ) includes a supplementary coil W 3  which provides a current sensing function and is connected to a zero-current detector  32 ( k );  
         [0485]    an input terminal of the primary power carrying winding of the power storage inductor  22 ( k ) is connected to the input node of the DC-DC power conversion channel  16 ( k );  
         [0486]    an output terminal of the primary power carrying winding of the power storage inductor  22 ( k ) is connected to an input terminal of the power blocking rectifier  24 ( k );  
         [0487]    an output terminal of the power blocking rectifier  24 ( k ) is connected to the channel output smoothing filter  25 ( k );  
         [0488]    the controllable power switch  23 ( k ) is connected between a tap of the power carrying coil, i.e. the common junction point of both the coils W′ and W″, of the power storage inductor  22 ( k ) and a common return node;  
         [0489]    switch-shunting terminals of the active soft-switching conditioner  26 ( k ) are connected across the controllable power switch  23 ( k );  
         [0490]    rectifier-shunting terminals of the active soft-switching conditioner  26 ( k ) are connected across the power blocking rectifier  24 ( k );  
         [0491]    In addition, DC-DC power conversion channel  16 ( 1 ) contains a non-zero-current detector  33  with a current-sensing transformer  34 :  
         [0492]    an input-current-sensing coil  1  of the current-sensing transformer  34  is connected between a tap coils W′ and W″, on the power storage inductor  22 ( 1 ), and the controllable power switch  23 ( 1 );  
         [0493]    output-current-sensing coil  2  of the current-sensing transformer  34  is connected between the output terminal of the primary power carrying winding of the power storage inductor  22 ( 1 ) and the input terminal of the power blocking rectifier  24 ( 1 ).  
         [0494]    The control circuit  200 , is of conventional design.  
         [0495]    The active power factor correction (APFC) controller  201  may be provided by any conventional off-the-shelf PFC controller microchip supplied with the resistive components  202 ,  203  attached for input signals conditioning.  
         [0496]    The I AC  (alternative current sensing) port of the APFC controller  201  is connected to the output node of the input AC-DC rectifier  11  via signal conditioning resistor  202 .  
         [0497]    The I SNS  (current feedback sensing) port of the APFC controller  201  is connected to the output of the non-zero-current detector  33  within DC-DC power conversion channel  16 ( 1 ).  
         [0498]    The VFB (voltage feed-back sensing) port of the APFC controller  201  is connected to the system output of the multi-channel DC-DC converter  12  via signal conditioning resistive divider  203 .  
         [0499]    The V OUT  (output) port of the APFC controller  201  is connected to the DATA port of the primary shift register  302  which is part of synchronization circuit  300 .  
         [0500]    The over-voltage detector  204  may be provided by a conventional electronic circuit designed to develop a logic signal resulting from a comparison between the input voltage level and the reference level.  
         [0501]    The sensing input of the over-voltage detector  204  is connected to the system output of the multi-channel DC-DC converter  12  via the FEED-BACK input of the control circuit  200 .  
         [0502]    The output of the over-voltage detector  204  provides a RESET output of the control circuit  200  and is connected to the RESET ports of the shift registers  302 ,  304 ( k ) within the synchronization circuit  300 .  
         [0503]    The synchronization circuit  300  provides time-staggered ON-OFF control signals to the controllable power switches  23 ( k ) and to the controllable commutating switches  30 ( k ) within the corresponding DC-DC power conversion channels  16 ( k ).  
         [0504]    The synchronization circuit  300  includes N number of PS(k) (power switch) outputs which are sequentially indexed as PS( 1 ), . . . , PS(k), . . . PS(N), being the Q PS(k)  outputs of the corresponding secondary shift registers  304 ( 1 ), . . . ,  304 ( k ), . . . ,  304 (N) respectively.  
         [0505]    Each PS(k) output is connected to the gate of the corresponding controllable power switch  23 ( k ) within the corresponding DC-DC power conversion channel  16 ( k ).  
         [0506]    The synchronization circuit  300  includes N number of SS(k) (soft switching) outputs which are sequentially indexed as SS( 1 ), . . . , SS(k), . . . SS(N), being the outputs of the corresponding secondary 2-input AND logic gates  305 ( 1 ), . . .  305 ( k ), . . . ,  305 (N) respectively.  
         [0507]    Each SS(k) output is connected to the gate of the corresponding controllable commutating switch  30 ( k ) within the corresponding DC-DC power conversion channel  16 ( k ).  
         [0508]    The clocking within the synchronization circuit  300  is provided by the clock pulse oscillator (CPO)  301  whose output is connected to the CLOCK ports of the shift registers  302 ,  304 ( k ).  
         [0509]    The primary shift register  302  initially includes at least D 302  quantity (where: D 302 =1, 2, . . . ) of the internal flip-flop cells q sequentially combined in chain to provide sequential loading, storing and shifting the data along the flip-flop cell chain, i.e. along the shift register.  
         [0510]    Consequently, all internal flip-flop cells q within the primary shift register  302  may be sequentially numbered according to the shift register specification, and their quantity D 302  should be regarded as a “digital” length of the prirnary shift register  302  indexed hereafter as D 302 .  
         [0511]    Along the sequential chain of the flip-flop cells q, certain outputs should be used to provide control signals for operating the DC-DC power conversion channels  16 ( k ) in a time-staggered fashion.  
         [0512]    Therefore, according to N number of DC-DC power conversion channels  16 ( k ) the corresponding N number of Q C  (channel control) outputs are selected within the primary shift register  302  and are sequentially indexed as Q C(1) , . . . , Q C(k) , . . . , Q C(N) . Each Q C(k)  output is connected to the first input of the corresponding primary logic gate  303 ( k ).  
         [0513]    The way to determine the “digital” length D 302  of the primary shift register  302  and to select the appropriate outputs Q C(k)  will be discussed in later paragraphs.  
         [0514]    The second input of each primary 2-input AND logic gate  303 ) k ) is connected to the output of the corresponding zero-current detector  32 ( k ) within the corresponding DC-DC power conversion channel  16 ( k ).  
         [0515]    The output of each primary 2-input AND logic gate  303 ( k ) is connected to the DATA input of the corresponding secondary shift register  304 ( k ), and to the first input of the corresponding secondary logic gate  305 ( k ).  
         [0516]    Each secondary shift register  304 ( k ) initially includes at least D 304(k)  number (where: D 304(k) =1, 2, . . . ) of internal flip-flop cells q sequentially combined in chain to provide sequential loading, storing and shifting the data along the flip-flop cell chain, i.e. along the shift register.  
         [0517]    Consequently, all internal flip-flop cells q within each shift register  304 ( k ) may be sequentially numbered according to the shift register specification, and their quantity D 304(k)  should be regarded as a “digital” length of the secondary shift register  304 ( k ) indexed hereafter as D 304(k) .  
         [0518]    The way to determine the “digital” length D 304(k)  of the secondary shift registers  304 ( k ) will be discussed in later paragraphs.  
         [0519]    Along the sequential chain of the flip-flop cells q, certain outputs should be used to provide control signals for operating the corresponding controllable switches within the DC-DC power conversion channels  16 ( k ) in an appropriately time-staggered fashion.  
         [0520]    Therefore, according to N number of the DC-DC power conversion channels  16 ( k ) the corresponding N number of Q PS  (power switch control) and N number of Q CS  (commutating switch control) outputs are selected and are sequentially indexed as Q PS(1) , . . . , Q PS(k) , . . . , Q PS(N)  and Q CS(1) , . . . , Q CS(k) , . . . , Q CS(N)  respectively.  
         [0521]    Each corresponding Q PS(k)  output is connected to the gate of the corresponding controllable power switch  23 ( k ) within the corresponding DC-DC power conversion channel  16 ( k ).  
         [0522]    Each corresponding Q CSk)  output is connected to the second input of each corresponding secondary 2-input AND logic gate  305 ( k ).  
         [0523]    The output of each corresponding secondary 2-input AND logic gate  305 ( k ) is connected to the gate of the corresponding controllable commutating switch  30 ( k ) within the corresponding DC-DC power conversion channel  16 ( k ).  
         [0524]    The way to select the appropriate outputs Q PS(k)  and Q CSk)  will be discussed in later paragraphs.  
         [0525]    The APFC controller  201  monitors two control loops.  
         [0526]    First control loop aims to insure a sinusoidal waveform of the current i AC (t) consumed from the AC primary power source  10 , and also to minimize phase shift between the waveforms of current i AC (t) and AC voltage u AC (t) provided by the AC primary power source  10 , as shown in FIG. 4( a ):  
           i   AC ( t )= I   ACmax  sin(2 πf   AC   t ),  [29] 
           I   ACax   =P   OUT   /ηU   AC ,  [30] 
           f   AC =1 /T   AC ,  [31] 
           u   AC ( t )= U   ACmax  sin(2 πf   AC   t ),  [32] 
         U ACmax =U AC   [33] 
         [0527]    where: I ACmax  is a value for a maximal amplitude of the current consumed from the AC primary power source  10 ,  
         [0528]    f AC  is a value for a frequency of the AC voltage provided by the AC primary power source  10 ,  
         [0529]    T AC  is a value for a period of the AC voltage provided by the AC primary power source  10 ,  
         [0530]    U AC  is a RMS value for the AC voltage provided by the AC primary power source  10 ,  
         [0531]    P OUT  is a value for the power consumed by the system load  14 , is a value for the power factor of the AC-DC converter  100   
         [0532]    U ACmax  is a value for a maximal amplitude of the AC voltage provided by the AC primary power source  10 .  
         [0533]    For this purpose the sinusoidal-shape reference current waveform i REF (t) is developed by applying the rectified voltage u IN (t)≈|u AC (t)| to the I AC  input port of the APFC controller  201  via the signal conditioning resistor  202 .  
         [0534]    Second control loop aims to provide a stable regulated DC output voltage U OUT  across the system load  14 , i.e. at the output of the AC-DC converter  100 .  
         [0535]    For this purpose the feed-back signal u FB (t) is developed by applying the output voltage U OUT  to the V FB  input port of the APFC controller  201  via the signal conditioning resistive divider  203 .  
         [0536]    To secure both a sinusoidal waveform of the current i AC (t) consumed from the AC primary power source  10 , and a stable regulated DC output voltage U OUT  across the system load  14 , the system output current i OUT (t) of the AC-DC converter  100  should be regulated in coordination with a waveform of the instantaneous AC power p AC (t) consumed from the primary AC power source  10 , as shown in FIG. 4( b ), such that:  
           i   OUT ( t )= p   AC ( t )/ U   OUT ,  [34] 
           p   AC ( t )= i   AC ( t ) u   AC ( t ).  [35] 
         [0537]    In a discontinuous current mode of operating the DC power conversion channel  16 ( k ), the APFC controller  201  should develop the pulse-width-modulated (PWM) control signal u 201 (t) with a time-controlled duty factor K D (t), as shown in FIG. 9( c ), such that:  
                 K   D          (   t   )       =           2        P   OUT          L     1        (   K   )              U   OUT       -           u   IN          (   t   )       /     T   PS            U   OUT           /       u   IN          (   t   )                 [   36   ]                               
 
         [0538]    where: L 1(k)  is an inductance value of the primary auto-transformer winding of the power storage inductor  22 ( k ) within the DC power conversion channel  16 ( k );  
         [0539]    T PS  is a value for a period of the controllable power switch operating frequency provided to all DC power conversion channels  16 ( k ).  
         [0540]    To insure discontinuous current mode for every DC power conversion channel  16 ( k ), the value for L I(k)  should be defined such that:  
           L   1(k)   ≦NT   PS   U   2   Acmin ( U   OUT   −U   Acmin )/4 P   OUTmax   U   OUT ,  [37] 
         [0541]    where: U ACmin  is a minimal RMS value for the AC voltage provided by the AC primary power source  10 ,  
         [0542]    P OUTmax  is a maximal value for the power consumed by the system load  14 .  
         [0543]    In case of the tapless choke design chosen for the power storage inductors  22 ( k ) for the cheapest embodiments of the present invention, the choke inductance value L (k)  should be as defined in [37] considering that L (k) =L 1(k) .  
         [0544]    FIGS.  9 ( a,b ) illustrate the time-scaled waveforms of electric parameters attributed to the discussed embodiment of the proposed invention wherein the multi-channel DC-DC power converter  12  comprises N=4 DC-DC power conversion channels  16 ( k ).  
         [0545]    [0545]FIG. 9( c ) illustrates the time-scaled diagram of the K D (t) duty factor value regulation within the discussed embodiment of the proposed invention wherein the multi-channel DC-DC power converter  12  comprises N=4 DC-DC power conversion channels  16 ( k ).  
         [0546]    The operation of the synchronization circuit  300  will be discussed next.  
         [0547]    [0547]FIG. 10 illustrates the timing diagrams describing the operation of the synchronization circuit  300  incorporated into the various embodiments of the switching-mode AC-DC power converters according to the present invention.  
         [0548]    [0548]FIG. 10( a ) illustrates the time-scaled interrelationship between the ON-OFF control signal u 201 (t) and the clocking signal u 301 (t).  
         [0549]    The ON-OFF control signal u 201(   t ) produced by the V OUT  port of the APFC controller  201  is applied to the DATA port of the primary shift register  302  in the synchronization circuit  300 .  
         [0550]    Time t 0  is assigned for a leading edge of the high logic level ON-state pulse of the ON-OFF control signal u 201 (t).  
         [0551]    Time t 4  is assigned for the trailing edge of the high logic level ON-state pulse of the ON-OFF control signal u 201 (t)  
         [0552]    The time interval t 4 −t 0 =t ABS  is an absorption time interval corresponding to the conducting state of any one of the time-staggered controllable power switches  23 ( k ) while the corresponding power storage inductor  22 ( k ) accumulates the power absorbed from the primary AC power source  10  via the input AC-DC rectifier  11 .  
         [0553]    The time interval t′ 0 −t 4 =t RLX  is a relaxation time interval corresponding to the non-conducting state of any one of the time-staggered controllable power switches  23 ( k ) while the corresponding power storage inductor  22 ( k ) releases the magnetically stored energy to the system load  14  via the corresponding power blocking rectifier  24 ( k ).  
         [0554]    The time interval t 0 −t′ 0 =T PS  is the controllable power switch operation period of the high logic level ON-state pulses of the ON-OFF control signal u 201 (t) corresponding to the duration of operational cycle within any one of the time-staggered DC-DC power conversion channels  16 ( k ).  
         [0555]    The clock pulse oscillator  301  produces a clocking signal u 301 (t) shown in FIG. 10( a ) to be applied to the CLOCK port of the primary shift register  302 . The time interval t CPO  is the period of the clocking signal u 301 (t), i.e. the period of the clocking frequency.  
         [0556]    Time t 1  is assigned for a first-in-the-row appointed front edge of the high logic level ON-state pulse of the clocking signal u 301 (t).  
         [0557]    The value for the period T CPO  of the high logic level ON-state pulses of the clocking signal u 301 (t) should be defined by the acceptable tolerance δ (in %) with which the duration t PS  of the high logic level ON-state pulse of the ON-OFF control signal u 201 (t) should be repetitively reproduced, such that:  
           T   CPO ≦0.01 T   PS .  [38] 
         [0558]    At the leading edge of every u 301 (t) high logic level ON-state clocking pulse the primary shift register  302  periodically latches the logic level of the ON-OFF control signal u 201 (t) applied to its DATA port.  
         [0559]    Since the internal clocking oscillator of the APFC controller  201  and the CPO  301  operate asynchronously with respect to each other, therefore, as shown in FIG. 10( a ), the leading edge of the high logic level ON-state pulse of the ON-OFF control signal u 201 (t) may be produced at time t 0 , but only at time t 1  the leading edge of the consecutive u 301 (t) high logic level ON-state pulse causes latching the high logic level within the internal first-bit flip-flop cell q (1)  of the primary shift register  302  such that the high logic level of signal u Q(1) (t) appears at its output Q (1) . When the logic level of the ON-OFF control signal u 201 (t) goes low at time t 4 , the subsequent leading edge of the high logic level pulse of the u 301 (t) signal at time t 5  causes latching the low logic level within the internal first-bit cell q (1)  of the primary shift register  302  such that the low logic level of signal u Q(1) (t) appears at its output Q (1) .  
         [0560]    The maximum error time interval t E =Δt 01  between the leading edges of the high logic level ON-state pulses of the u 201 (t) and u Q(1) (t) signals should not exceed the duration of the period T CPO  of the high logic level ON-state pulses of the clocking signal u 301 (t):  
         0≦ t   E   =Δt   01   ≦T   CPO ,  
           t   E   =Δt   01   =t   1   −t   0 .  [39] 
         [0561]    Further, regardless of the logic state at the DATA port of the primary shift register  302  and coincidentally with the front edge of each consecutive u 301 (t) pulse, the logic state of every internal flip-flop cell q is shifted to the next cell in the chain.  
         [0562]    As a result, the flip-flop cells q of the primary shift register  302  provide D 302  number of time-staggered high logic level ON-state pulses which are progressively delayed replicas of the high logic level ON-state pulse of the u 201 (t) signal.  
         [0563]    Further, the “channel” clocking signals should be related to those provided by the primary shift register  302  such that the time displacement interval Δt dspl =T PS /N according to [24] should be secured between the leading edges of the high logic level ON-state pulses of the sequential “channel” pulses.  
         [0564]    Naturally, there should be N number of the “channel” clocking signals each assigned to the corresponding DC-DC power conversion channel  16 ( k ).  
         [0565]    The “channel” clocking signals are provided by the corresponding Q C(k)  outputs of the primary shift register  302 .  
         [0566]    Therefore, the “channel” Q C(k)  outputs of the primary shift register  302  produce N number of u QC(k) (t) signals which conform to the u 201 (t) signal and are time staggered such that the time displacement interval Δt dspl =T PS /N is maintained between the leading edges of the high logic level ON-state pulses of the sequential “channel” pulses.  
         [0567]    Accordingly, the “channel” clocking signals should be indexed as u QC(1) (t), . . . , u QC(k) (t), . . . , u QC(N) (t) respectively.  
         [0568]    FIGS.  10 ( b,c,d,e ) illustrate the time-scaled waveforms of the synchronization signals produced within a synchronization circuit comprising N=4 DC-DC power conversion channels (k=1, 2, 3, 4), where k is an index of the sequential channel.  
         [0569]    As can be seen, the same-indexed signals within the sequential channels are time staggered such that the time displacement interval Δt dspl =T PS /N interval between their corresponding edges is constant. Therefore, the operational cycles and power conversion processes within the corresponding DC-DC power conversion channels  16 ( k ) are sequentially time-staggered with equal time displacement intervals Δt dspl =T PS /N.  
         [0570]    To provide the “channel” clocking signals u QC(k) (t), the corresponding “channel” flip-flop cells q of the primary shift register  302  may be selected of those “physical” such that:  
           Q   C(k)   =T   PS ( k− 1)/ T   CPO   N+ 1,( k= 1,2, . . . , N ),  [40] 
         [0571]    where: Q C(k)  is a sequential number of the flip-flop cell q providing its output signal to clock the k-th channel;  
         [0572]    and the time displacement interval Δt dspl(k)  between the leading edge of the high logic level ON-state pulse of the first-in-the-row appointed “channel” signal u QC(1) (t) and the leading edge of the high logic level ON-state pulse of any other “channel” signal u QC(k) (t) may be defined as:  
         Δ t   dspl(K)   =T   PS ( k− 1)/ N ,( k= 1,2, . . . , N ),  [41] 
         [0573]    The leading edge of the high logic level ON-state pulse of the last-in-the-row appointed “channel” signal u QC(N) (t) is shifted in respect to the leading edge of the high logic level ON-state pulse of the u 201 (t) signal for a maximum time-delay interval Δt Smax  such that:  
         Δ t   Dmax   =T   PS ( N− 1)/ N+T   CPO ,  [42] 
         [0574]    Therefore, the “digital” length D 302 , i.e. the quantity of internal flip-flop cells q within the primary shift register  302  should be defined as:  
           D   302   =Δt   Dmax   /T   CPO ,  [43] 
         [0575]    or, according to [38], as:  
           D   302 =( N− 1)/0.01 δN +1.  [44] 
         [0576]    Further, the corresponding u QC(k) (t) time-staggered signals are applied to first inputs of the corresponding primary 2-input AND logic gates  303 ( 1 ), . . . ,  303 ( k ), . . . ,  303 (N) respectively.  
         [0577]    [0577]FIG. 10( b ) illustrates the timing diagrams describing the logic signals developed within the first DC-DC power conversion channel, i.e. k=1, and thereafter the indexed time-points and events assigned to each subsequent channel will be reproduced for all other channels with equal time displacement interval Δt dspl(k)  according to [41] being maintained.  
         [0578]    The second inputs of corresponding primary 2-input AND logic gates  303 ( k ) are connected to the outputs of corresponding zero-current detectors  32 ( k ) within the corresponding DC-DC power conversion channels  16 ( k ), i.e. to the outputs of the  32 ( 1 ), . . . ,  32 ( k ), . . . ,  32 (N) respectively. Therefore, the corresponding u 32(k) (t) signals are applied to the second inputs of the corresponding primary 2-input AND logic gates  303 ( 1 ), . . . ,  303 ( k ), . . . ,  303 (N) respectively.  
         [0579]    During the time interval t 5 −t 1 ≈t ABS  while both inputs of the corresponding primary 2-input AND logic gate  303 ( k ) are subjected to high logic level, its output produces a high logic level ON-state pulse of the u 303(k) (t) signal.  
         [0580]    Naturally, the duration of the high logic level ON-state pulse of the corresponding u 303(k) (t) signal is equal to t 5 −t 1 ≈t ABS  time interval, i.e. equal to that of the corresponding u QC(k) (t) signal and to that of the ON-OFF control signal u 201 (t).  
         [0581]    Therefore, as shown in FIG. 10, in the quasi-steady state the primary logic gates  303 ( k ) produce N number of high logic level ON-state pulses of the u 303(k) (t) output signals which conform (within limits imposed by the quantizing error caused by the period of  301 ) to the high logic level ON-state pulse of the U QC(k) (t) output signals of the primary shift register  302 .  
         [0582]    Their duration is also equal to t ABS  absorption time interval, their period is also equal to T PS  controllable power switch operation period, and their leading edges are also sequentially shifted for a Δt dspl =T PS /N time interval.  
         [0583]    Further, the corresponding u 303(k) (t) signals are applied to the DATA ports of the corresponding secondary shift registers  304 ( 1 ), . . . ,  304 ( k ), . . . ,  304 (N) respectively, and to the first inputs of the corresponding secondary logic gates  305 ( 1 ), . . . ,  305 ( k ), . . . ,  305 (N) respectively.  
         [0584]    The clock pulse oscillator  301  produces a clocking signal u 301 (t) shown in FIG. 10( a ) to be applied to the CLOCK ports of the secondary shift registers  304 ( k ).  
         [0585]    Coincidentally to the leading of every u 301 (t) pulse each secondary shift register  304 ( k ) periodically latches the data loaded to its DATA port and shifts them along the chain of its internal flip-flop cells q.  
         [0586]    The outputs Q PS(k)  and Q CS(k)  of each secondary shift register  304 ( k ) produce the logic pulses of the u PS (t) and u CS (t) output signals respectively, and the respective leading edges are time-shifted in respect to the leading edge of the high logic level ON-state pulse of the corresponding u 303 (t) output signal such that:  
           t   2   −t   1   =t   A ,  
           t   3   −t   2   =t   L ,  
           t   A   +t   L   =t   SS ,  [45] 
         [0587]    where:  
         [0588]    t 1  is a time assigned to the leading edge of the high logic level u 303 (t) pulse produced at the output of corresponding primary logic gate  303 ( k ),  
         [0589]    t 2  is a time assigned to the leading edge of the high logic level u PS (t) pulse produced at the Q PS  output of the corresponding secondary shift register  304 ( k ),  
         [0590]    t 3  is a time assigned to the leading edge of the low logic level u CS (t) pulse produced at the Q CS  output of corresponding secondary shift register  304 ( k ),  
         [0591]    t A  is an advance time interval of turning on the corresponding controllable commutating switch  30 ( k ) into conducting state prior to corresponding controllable power switch  23 ( k ) being turned into conducting state (the reason for this will be discussed in later paragraphs);  
         [0592]    t L  is a lag time interval of turning the corresponding controllable commutating switch  30 ( k ) into non-conducting state after the corresponding controllable power switch  23 ( k ) being turned into conducting state (the reason for this will be discussed in later paragraphs);  
         [0593]    t SS  is a soft-switching time interval of corresponding controllable commutating switch  30 ( k ) being turned into conducting state (to be discussed in later paragraphs).  
         [0594]    The “digital” length D 304(k) , i.e. the quantity of internal flip-flop cells q within each secondary shift register  304 ( k ) should be defined as:  
           D   304(k)   ≧t   SS /0.01 δT   CPO +1.  [46] 
         [0595]    To provide the “channel” control signals u PS(k) (t) and u CS(k) (t) the corresponding “channel” flip-flop cells q of the primary shift register  304  may be selected such that:  
           Q   PS(k)   =t   A   /T   CPO +1,  [47] 
         [0596]    and:  
           Q   CS(k)   =t   SS   /T   CPO +1,  [48  
         [0597]    where: Q PS(k)  and Q CS(k)  are the sequential numbers of the flip-flop cells q providing their output signals u PS(k) (t) and u CS(k) (t) respectively.  
         [0598]    Therefore, as shown in FIG. 10, in a quasi-steady state the Q PS(k)  outputs of the secondary shift registers  304 ( k ) produce N number of high logic level ON-state pulses of the u PS(k) (t) signals which conform (within limits imposed by the quantizing error caused by the period of  301 ) to the high logic level ON-state pulses of the u QC(k) (t) output signals of the primary shift register  302  Their duration is also equal to the t ABS  absorption time interval, their period is also equal to T PS  controllable power switch operation period of the operational cycle, and their leading edges are also sequentially shifted for a time displacement Δt dspl =T PS /N interval.  
         [0599]    Consequently, as shown in FIG. 10, in a quasi-steady state the Q CS(k)  outputs of the secondary shift registers  304 ( k ) produce N number of the low logic level pulses of the u CS(k) (t) signals which are conform (within limits imposed by the quantizing error caused by the period of  301 ) to the high logic ON-state pulses (when being inversed) of the u QC(k) (t) output signals of the primary shift register  302 . Their duration is also quite equal to t ABS  absorption time interval, their period is equal to T PS  controllable power switch operation period of the operational cycle, and their leading edges are also sequentially shifted for a time displacement Δt dspl =T PS /N interval.  
         [0600]    During the time when both inputs of the corresponding secondary 2-input AND logic gate  305 ( k ) are subjected to high logic level, its output produces a high level logic ON-state pulse of an u 305(k) (t) signal.  
         [0601]    The duration of the high logic level ON-state pulse of the corresponding u 305(k) (t) signal is quite equal to t SS  soft-switching time interval of corresponding controllable commutating switch  30 ( k ) being turned into conducting state.  
         [0602]    Consequently, as shown in FIG. 10, in a quasi-steady state the outputs of the secondary 2-input AND logic gates  305 ( k ) produce N number of high logic level ON-state pulses of the corresponding u 305(k) (t) signals which conform to each other (within limits imposed by the quantizing error caused by the period of  301 ). Their duration is equal to tss soft-switching time interval of corresponding controllable commutating switch  30 ( k ) being turned into conducting state, their period is equal to T PS  controllable power switch operation period of the operational cycle, and their leading edges are also sequentially shifted for a Δt dspl =T PS /N time displacement interval.  
         [0603]    The Q PS(k)  outputs of the corresponding secondary shift registers  304 ( 1 ), . . . ,  304 ( k ), . . . ,  304 (N) are connected to the gates of the controllable power switches  23 ( k ) within the corresponding DC-DC power conversion channels  16 ( 1 ), . . . ,  16 ( k ), . . . ,  16 (N) respectively via the corresponding PS(k) (power switch) outputs of the synchronization circuit  300 , i.e. PS( 1 ), . . . , PS(k), . . . PS(N) respectively.  
         [0604]    The outputs of the secondary 2-input AND logic gates  305 ( 1 ), . . . ,  305 ( k ), . . . ,  305 (N) are connected to the gates of the controllable commutating switches  30 ( k ) within the corresponding DC-DC power conversion channels  16 ( 1 ), . . . ,  16 ( k ), . . . ,  16 (N) respectively via the corresponding SS(k) (soft switching) outputs of the synchronization circuit  300 , i.e. SS( 1 ), . . . , SS(k), . . . SS(N) respectively.  
         [0605]    The t A  advance time interval should be defined such that by the time t 2  the corresponding active soft-switching conditioner  26 ( k ) should produce a zero-voltage condition across the corresponding controllable power switch  23 ( k ).  
         [0606]    The t L  lag time interval should be defined such that by the time t 3  the corresponding controllable power switch  23 ( k ) should be in a reliably conducting state, i.e. t SS &gt;t A .  
         [0607]    Since the Q PS(k)  outputs of the corresponding secondary shift registers  304 ( 1 ), . . . ,  304 ( k ), . . . ,  304 (N) drive the gates of the controllable power switches  23 ( k ) within the corresponding DC-DC power conversion channels  16 ( 1 ), . . . ,  16 ( k ), . . . ,  16 (N) respectively in a uniformly time-staggered fashion, then the main electric processes within the DC-DC power conversion channels  16 ( k ) conform to each other and are sequentially time-staggered with respect to each other with a time displacement Δt dspl =T PS /N interval.  
         [0608]    [0608]FIG. 4( a ) illustrates the nature of the operational cycle within the DC-DC power conversion channel  16 ( k ).  
         [0609]    In the quasi-steady state at some reference time, for example t 0 , as shown in FIG. 4( a ), the controllable power switch  23 ( k ) is closed/conducting, the power storage inductor  22 ( k ) is connected across the input AC-DC rectifier  11 , the power blocking rectifier  24 ( k ) is non-conducting while being reverse-biased by the voltage stored across the system output smoothing filter  17 , therefore the system load  14  is disconnected from the input AC-DC rectifier  11  and is powered by the energy stored in the system output smoothing filter  17 .  
         [0610]    While the rectified input voltage u IN (t) produced by the input AC-DC rectifier  11  is applied across the power storage inductor  22 ( k ), the current i 22 (t) through it increases in a linear fashion and, thus accumulating the magnetically stored energy within the power storage inductor  22 , reaches its maximum value at time t 01 .  
         [0611]    Now the controllable power switch  23 ( k ) is turned into open/non-conducting state, the power blocking rectifier  24 ( k ) turns into forward-biased/conducting state, and the energy magnetically stored within the power storage inductor  22 ( k ) is transferred through the power blocking rectifier  24 ( k ) to the system output smoothing filter  17  and to the system load  14 . The current i 22 (t) through the power storage inductor  22 ( k ) starts decreasing in a linear fashion and reaches its minimum value by the end of the operational cycle at time t 02 . Then the operational cycle may be re-started.  
         [0612]    To start the next operational cycle the controllable commutating switch  30 ( k ) is turned into closed/conducting state again.  
         [0613]    Further operation will be discussed referring to FIG. 10.  
         [0614]    To secure the low-loss discontinuous current mode, each DC-DC power conversion channel  16 ( k ) comprises a current sensing coil W 3 (k) within each power storage inductor  22 ( k ) and a zero-current detector  32 ( k ) to detect the non-zero i RLS(k) (t) release current flow within the power storage inductor  22 ( k ) during the t RLS  release time interval of releasing the magnetically stored energy.  
         [0615]    While the corresponding current sensing coil W 3 (k) senses the non-zero i RLS(k) (t) release current within its power storage inductor  22 ( k ), the corresponding zero-current detector  32 ( k ) produces a low logic level at its output thus preventing the corresponding primary 2-input AND gate  303 ( k ) from loading the high logic level to the DATA port of the corresponding secondary shift register  304 ( k ) and to the first input of the corresponding secondary 2-input AND gate  305 ( k ).  
         [0616]    Therefore, no high logic level is produced at the corresponding PS(k) and SS(k) outputs of the synchronization system  300  until the i RLS(k) (t) release current flow within the corresponding power storage inductor  22 ( k ) reaches zero.  
         [0617]    At this moment the corresponding zero-current detector  32 ( k ) produces a high logic level at its output thus enabling the corresponding primary 2-input AND gate  303 ( k ) to load the high logic level to the DATA port of the corresponding secondary shift register  304 ( k ) and to the first input of the corresponding secondary 2-input AND gate  305 ( k ) provided that the corresponding “channel” output Q C(K)  of the primary shift register  302  also applies the high logic level to the second input of the corresponding primary 2-input AND gate  303 ( k ).  
         [0618]    Therefore, the synchronization circuit  300  postpones the successive operational cycle for indefinite time by preventing the controllable switches within any corresponding DC-DC power conversion channel  16 ( k ) from being turned into conducting state prior to the i RLS(k) (t) release current flow within the corresponding power storage inductor  22 ( k ) reaching zero.  
         [0619]    In this method, the indispensable condition of low-loss discontinuous current mode within each DC-DC power conversion channel  16 ( k ) is insured: the i RLS(k) (t) release current flow within the corresponding power storage inductor  22 ( k ) should be equal to zero prior to the start of the next operational cycle.  
         [0620]    [0620]FIG. 10( b,c ) illustrate the u 32(1) (t) and u 32(2) (t) signals produced by the corresponding zero-current detectors  32 ( 1 ) and  32 ( 2 ) within the corresponding DC-DC power conversion channels  16 ( 1 ) and  16 ( 2 ).  
         [0621]    Time t 8  is assigned for the leading edge of the high logic level pulse of the u 32(1) (t) signal of the zero-current detector  32 ( 1 ).  
         [0622]    To secure the low-loss discontinuous current mode within each DC-DC power conversion channel  16 ( 1 ), the leading edge of the high logic level pulse of the u 32(1) (t) signal precedes the leading edge of the high logic level pulse of the corresponding U QC(1) (t) signal for a time interval t F =t′ 1 −t 8 . The forward time interval t F  insures the t PAU  pause interval according to [12] while the corresponding power storage inductor  22 ( 1 ) is current-free.  
         [0623]    The same is equally applicable to all other channels in the row, and each zero-current detector  32 ( k ) within the corresponding DC-DC power conversion channel  16 ( k ) detects the non-zero i RLS(k) (t) release current flow within the power storage inductor during the release time interval t RLS(k)  of releasing the magnetically stored energy to the load.  
         [0624]    The release time interval t RLS(1)  starts at time t 6  and lasts until time t′ 2  of the successive operational cycle.  
         [0625]    Starting from time t 7  the zero-current detector  32 ( 1 ) outputs a low logic level till time t 8  when the i RLS(1) (t) release current flow within the power storage inductor  22 ( 1 ) reaches zero.  
         [0626]    This low logic level prevents producing the high logic level pulse u PS(1) (t), i.e. triggering the controllable power switch  23 ( 1 ) into the conducting state.  
         [0627]    This is to provide a t PAU =t′ 2 −t 8  pause interval before the start of the subsequent operational cycle thus insuring the discontinuous current mode within the power storage inductor  22 ( 1 ).  
         [0628]    During the switch operation allowance time interval t SOA  after time t 8  till time t′ 6  of the sequential operational cycle the zero-current detector  32 ( 1 ) outputs a high logic level thus enabling the high logic level pulse u PS(1) (t), i.e. triggering the controllable power switch  23 ( 1 ) into the conducting state.  
         [0629]    FIGS.  10 ( f, g, h, i, j ) illustrate the time-scaled waveforms of the synchronization signals within the same 4-channel AC-DC power converter provided that a i RLS(1) (t) release current flow within the power storage inductor  22 ( 1 ) does not reach zero at time t 8 . In this case the zero-current detector  32 ( 1 ) outputs a low logic level from time t 6  till time t 9  when the i RLS(1) (t) release current flow within the power storage inductor  22 ( 1 ) reaches zero, thus delaying the start of the next operational cycle for a time interval t pp =t 10 −t′ 2 . Therefore, the switch operation allowance time interval for the successive operational cycle is decreased to a t SOA-DCR  value, and the cycle lasts during the decreased absorption time interval t ABS-DCR . The ON-state pulse of the corresponding soft-switching synchronization signal u 305(1) (t) is also postponed for the same postponement time interval t pp : it starts at time t 9  and ceases at time t 11 .  
         [0630]    Monitoring the non-zero-current i RLS(k) (t) within each DC-DC power conversion channel  16 ( k ) provides an independent initiation of the successive operational cycles thus providing the sufficient reliability of securing the low-loss discontinuous current mode regardless of all other conditions.  
         [0631]    To prevent possible damage, the control circuit  200  includes an over-voltage detector  204  to prevent the operation of all controllable switches within all DC-DC power conversion channels  16 ( k ), i.e. to inhibit the power conversion process in case the value of the regulated output DC voltage of the AC-DC power converter  100  exceeds the preset maximum threshold, and to enable the operation of all controllable switches within all DC-DC power conversion channels  16 ( k ) as soon as the regulated output DC voltage recovers the correct value, i.e. to restore the power conversion process as soon as the regulated output DC voltage falls below the preset minimum threshold in a hysteretic fashion.  
         [0632]    For this reason the over-voltage detector  204  monitors the regulated output DC voltage of the AC-DC power converter  100 .  
         [0633]    Normally, the over-voltage detector  204  outputs the low logic level to the RESET inputs of the shift registers  302 ,  304 ( k ), thus enabling normal operation of the DC-DC power conversion channels  16 ( k ).  
         [0634]    In case the value of the regulated output DC voltage exceeds the maximum preset threshold, the over-voltage detector  204  outputs a high logic level to the RESET inputs of the shift registers  302 ,  304 ( k ). This results in immediately bringing to a low logic level all PS(k) and SS(k) outputs of the synchronization circuit  300  and, therefore, in immediate turning all controllable switches within all DC-DC power conversion channels  16 ( k ) into the non-conducting state.  
         [0635]    As a result, the overall power conversion process is inhibited for indefinite time.  
         [0636]    As soon as the regulated output DC voltage falls below the minimum preset threshold, the over-voltage detector  204  outputs the low logic level to the RESET inputs of the shift registers  302 ,  304 ( k ), thus enabling the operation of all controllable switches within all DC-DC power conversion channels  16 ( k ), i.e. restoring the overall power conversion process.  
         [0637]    The hysteretic fashion of operation is provided by the corresponding design of the over-voltage detector  204 .  
         [0638]    Next, the operation of the active soft-switching conditioner  26 ( k ) will be discussed with the reference to the time-scaled waveforms illustrated in FIGS.  10 ( a,b ).  
         [0639]    As for example, in the quasi-steady state prior to time t 1  the controllable power switch  23 ( 1 ) is open/non-conducting, the power blocking rectifier  24 ( 1 ) is reverse-biased/non-conducting thus providing no current path from the AC primary power source  10  to the power storage inductor  22 ( 1 ) and to the output smoothing filters  25 ( 1 ),  17  and to the load  14 .  
         [0640]    The power storage inductor  22 ( 1 ) is current-free and energy-free.  
         [0641]    The components of the active soft-switching conditioner  26 ( 1 ) are current-free.  
         [0642]    The controllable commutating switch  30 ( 1 ) within the active soft-switching conditioner  26 ( 1 ) is open/non-conducting.  
         [0643]    The voltage across the slope-shaping capacitor  28 ( 1 ) and across the controllable commutating switch  30 ( 1 ) is equal to u IN (t) produced by the input AC-DC rectifier  11 . This is due to the chosen discontinuous current mode of operation. In case of continuous current mode the value of the voltage across the slope shaping capacitor  28 ( 1 ) and across the controllable commutating switch  30 ( 1 ) would be equal to much higher level of U OUT .  
         [0644]    The output smoothing filters  25 ( 1 ),  17  and the system load  14  are powered by those DC-DC power conversion channels  16 ( k ) currently releasing the magnetically stored energy from corresponding power storage inductors  22 ( k ).  
         [0645]    At time t 1  the high logic level pulse outputted by the corresponding secondary 2-input AND logic gate  305 ( 1 ) triggers the controllable commutating switch  30 ( 1 ) into the closed/conducting state, and now the u IN (t) voltage produced by the input AC-DC rectifier  11  is applied to the network of series-connected power blocking rectifier  24 ( 1 ) and a damp/resonant choke  29 ( 1 ).  
         [0646]    Past this time the process is defined by the LC resonant tank consisting of parallel-connected damp/resonant choke  29 ( 1 ) and the slope-shaping capacitor  28 ( 1 ) within the active soft-switching conditioner  26 ( 1 ).  
         [0647]    The current i 29 (t) through the damp/resonant choke  29 ( 1 ) starts increasing and the voltage across the slope-shaping capacitor  28 ( 1 ) starts decreasing in accordance with [18].  
         [0648]    Since the power storage inductors  22 ( 1 ) and the power blocking rectifier  24 ( 1 ) are current-free, then the maximum current i 29max  defined in accordance with [21] is substantially less than that corresponding to the continuous current mode.  
         [0649]    The sine waveform of the current through the damp/resonant choke  29 ( 1 ) and the sine waveform of the voltage across the slope-shaping capacitor  28 ( 1 ) would last until time t ON(27) , when the voltage u 28 (t) across this capacitor and across the controllable power switch  23 ( 1 ) reaches zero and the shunting rectifier  27 ( 1 ) becomes forward-biased/conducting. The components values are definitely chosen to secure the condition that t ON(27) &lt;t 2 , i.e. the zero-voltage-across condition for the controllable power switch  23 ( 1 ) should be provided prior to time t 2 .  
         [0650]    Therefore, during the interval between time t 1  and time t 2  the damp/resonant choke  29 ( 1 ) performs a resonant inductor function within the L 29 C 28  resonant tank. Within this interval the sinusoidal fashion of discharging the capacitor  28 ( 1 ) within the active soft-switching conditioner  26 ( 1 ) is provided as preparation for switching the controllable power switch  23 ( 1 ) into closed/conducting state under zero-voltage-across condition at time t 2 .  
         [0651]    The duration of the advance time interval t A =t 2 −t 1  is defined at least with a quarter of the period of the natural resonant frequency of the LC-tank consisting of the damp/resonant choke  29 ( 1 ) coupled to the slope-shaping capacitor  28 ( 1 ).  
         [0652]    Starting from the time t 2 , the controllable power switch  23 ( 1 ) may be turned into closed/conducting state under zero-voltage-across conditions at any time prior to controllable commutating switch  30 ( 1 ) being turned into open/non-conducting state.  
         [0653]    Therefore, the favorable soft-switching condition, i.e. zero-voltage-across/zero-current-through is provided for the controllable power switch  23 ( 1 ) during its transition to closed/conducting state which results in zero switching losses.  
         [0654]    Starting from the time t ON(27) &lt;t 2  the damp/resonant choke  29 ( 1 ) is short-shunted by the forward-biased/conducting shunting rectifier  27 ( 1 ) and the closed/conducting controllable commutating switch  30 ( 1 ).  
         [0655]    Such a state would last till the time t 3  when the controllable commutating switch  30 ( 1 ) is turned into open/non-conducting state by the u 305(1) (t) signal.  
         [0656]    At time t 3  the separating rectifier  31 ( 1 ) becomes forward-biased/conducting to provide the release of the magnetically stored energy from the damp/resonant choke  29 ( 1 ) to the system load  14  up to the time when the i 29 (t) current reaches zero.  
         [0657]    Starting from the time t ON(27)  the power storage inductor  22 ( 1 ) is subjected to the voltage u IN (t) produced by the input AC-DC rectifier  11 .  
         [0658]    At time t 2  the controllable power switch  23 ( 1 ) is turned to closed/conducting state, and the power storage inductor  22 ( 1 ) starts absorbing the current from the input AC-DC rectifier  11  and accumulating the magnetically stored energy.  
         [0659]    Within the absorption interval t ABS =t 6 −t 2  the i 22(1) (t) current increases up to reaching its maximum value i 22(1)max =ΔI 22(1) .  
         [0660]    At time t 6  the controllable power switch  23 ( 1 ) is turned to open/non-conducting state, and the cycle of absorbing the energy through it ends. The i 22(1) (t) current starts flowing through the slope-shaping capacitor  28 ( 1 ), therefore, charging it up to a voltage that exceeds the regulated output DC voltage for a voltage drop across the forward-biased/conducting power blocking rectifier  24 ( 1 ).  
         [0661]    The duration of the time interval between the controllable power switch  23 ( 1 ) transition to the open/non-conducting state and the power blocking rectifier  24 ( 1 ) transition to forward-biased/conducting state depends on the capacitance value of the slope-shaping capacitor  28 ( 1 ) and on the value of i 22(1)max , and is chosen to provide the loss-less conditions for the controllable power switch  23 ( 1 ) during its transition to open/non-conducting state.  
         [0662]    Starting from time t 6  and during the t RLS =t 8 −t 6  release time interval the power storage inductor  22 ( 1 ) releases the magnetically stored energy to the system load  14  up to the time t 8  when i 22(1) (t) current reaches zero.  
         [0663]    During the t RLS  release time interval the i 22(1) (t) current flows through the power blocking rectifier 24(1)  This current, i 24(1) (t), decreases slowly to zero. This fact results in nearly loss-less reverse resistance recovery, i.e. elimination of the switching transition losses inherent in the power blocking rectifiers subjected to the continuous current mode.  
         [0664]    As soon as the i 22(1) (t) current reaches zero at time t 8 , the zero-current detector  32 ( 1 ) produces an output high logic level lasting during the t′ 6 −t 8 =t OCA  operational cycle allowance interval to enable the next operational cycle.  
         [0665]    Employing the tapped auto-transformer choke design for the power storage inductors  22 ( k ) provides the additional benefits to the proposed embodiment of the present invention.  
         [0666]    If each power storage inductor  22 ( k ) is ascribed with an auto-transformation factor n 2/1 =w 2 /w 1  such that n 2/1 &gt;1, then the maximum voltage u 23(k)max  across the open/non-conducting controllable power switch  23 ( k ) and, accordingly, across the slope-shaping capacitor  28 ( k ) is reduced proportionally to the n 2/1  value:  
           u   23(k)max   =u   28(k)   =u   IN ( t )+( U   OUT   −u   IN ( t ))/ n   2/1 ,  [49] 
         [0667]    Reducing the voltage across the slope-shaping capacitor  28 ( k ) results in reduction of losses occurring due to re-charging process, and in reduction of currents i 29(k)max , i 30(k)max  flowing through the components of the active soft-switching conditioner  26 ( k ).  
         [0668]    The maximum value of i 24(k)max  current though the power blocking rectifier  24 ( k ) is also reduced with increasing the value of n 2/1 :  
           i   24(k)max   =i   24(k)max   /n   2/1 ,  [50] 
         [0669]    Therefore, the reduction of electrical stress upon the current carrying components, provides an opportunity to utilize components with less power carrying capability, and to enhance the utilization of component capabilities.  
         [0670]    Besides, the fact that increasing the n 2/1  results in reduction of i 24(k)max  current and in increasing the release factor K RLS  defined as:  
           i   24(k)max   =i   24(k)max   /n   2/1 ,  [50] 
         [0671]    results in reduction of output ripple as defined in [22] and [23].  
         [0672]    FIGS.  11 ( a,b ) illustrate the time—scaled waveforms of currents and voltages attributed to the power conversion processes within the first embodiment of the switching-mode AC-DC power converter according to the present invention.  
         [0673]    The value of the auto-transformation factor n 2/1 =1 corresponds to the tapless choke design of the power storage inductor  22 ( k ). As can be seen, regardless of the discontinuous current mode within the separate DC-DC power conversion channels, a high quality continuous current is maintained within the input and output circuitries of the AC-DC power converter.  
         [0674]    According to the second embodiment of the present invention, FIG. 8( b ) illustrates a circuit diagram of a multi-channel AC-DC converter  100  comprising a conventional APFC controller  201  designed to secure the continuous current mode within a conventional single-channel AC-DC power converter of a pulse width modulation type.  
         [0675]    In this case a multi-channel AC-DC converter  100  additionally comprises a total consumption current sensor  40  and a current signals summator  41  including first summing resistor  42 , second summing resistor  43  and a DC inhibiting capacitor  44 .  
         [0676]    The output signal of the non-zero-current detector  33 ( 1 ) of the first-in-the-row DC-DC power conversion channel  16 ( 1 ) monitors the value of the current flow within the power storage inductor  22 ( 1 ) to produce an output signal proportional to the sum of the current flows within both the controllable power switch  23 ( 1 ) and the power blocking rectifier  24 ( 1 ).  
         [0677]    This output signal is further applied to the second summing resistor  43  via the DC inhibiting capacitor  44 , both of the current signals summator  41 .  
         [0678]    The total consumption current sensor  40  monitors the total input current consumed by the AC-DC power converter  100  to produce an output signal proportional to the total input current consumed by all DC-DC power conversion channels  16 ( k ).  
         [0679]    This output signal is further applied to the first summing resistor  42  of the current signals summator  41 .  
         [0680]    The resistance values of the summing resistors  41 ,  42  are chosen in proportion to the values of the summed signals such that the resultant signal at their common junction simulates a current feedback signal conforming to that of the single-channel AC-DC power converter of the same capacity as of the multi-channel AC-DC power converter  100 .  
         [0681]    This simulated current feedback signal is further applied to the current feedback input of the conventional APFC controller  201  for securing the predetermined quality of the converted power ascribed with power factor and regulated output DC voltage stability.  
         [0682]    [0682]FIG. 11( c,d ) illustrate the time—scaled waveforms of currents and voltages attributed to the power conversion processes within the second embodiment of the switching-mode AC-DC power converter according to the present invention.  
         [0683]    The value of the auto-transformation factor n 2/1 =1,3 corresponds to the tapped auto-transformatory choke design of the power storage inductor  22 ( k ). As can be seen, regardless of the discontinuous current mode within the separate DC-DC power conversion channels, the high quality continuous current mode is secured within the input and output circuitries of the AC-DC power converter.  
         [0684]    According to the third embodiment of the present invention, FIG. 8( c ) illustrates a circuit diagram of a multi-channel AC-DC converter  100  comprising a conventional APFC controller  201  designed to insure the critical current mode and a variable operational frequency within a conventional single-channel AC-DC power converter.  
         [0685]    In this case the synchronization circuit  300  additionally comprises a voltage controlled oscillator (VCO)  306 , a frequency divider-by-M  307 , a phase comparator  308  and an integrating filter  309  which are combined in a phase locked loop for producing a VCO  306  output signal of an M times higher frequency than that of the ON-OFF control signal produced by the APFC controller  201 .  
         [0686]    The VCO  306  output signal is further applied to the input of the frequency divider-by-M  307  for producing an output chain of pulses of an M times lower frequency than that of the VCO  306  output signal.  
         [0687]    Both the ON-OFF control signal produced by the APFC controller  201  and the output signal of the frequency divider-by-M  307  are applied to the inputs of the phase comparator  308 .  
         [0688]    The output voltage of the phase comparator  308  is proportional to the difference between the frequencies of the signals applied to its inputs. This “error” signal is further smoothed by the integrating filter  309  to produce an “error” voltage for adjusting the VCO  306  such that the frequency of the output pulses of the frequency divider-by-M  307  will be equal to that of the ON-OFF control signal produced by the APFC controller  201 .  
         [0689]    Therefore, the frequency of the VCO  306  output pulses is automatically adjusted in accordance with that of the ON-OFF control signal produced by the APFC controller  201 .  
         [0690]    The output signal of the VCO  306  is further applied to the CLOCK input of the shift register  302 .  
         [0691]    The minimum value for the period T VCO  of the clocking signal u 306 (t) should be defined by the acceptable tolerance δ (in %) with which the minimum operational period T PSmin  of the ON-OFF control signal u 201 (t) should be repetitively reproduced, such that:  
         [0692]    [0692] T   VCOmin ≦0.01 T   PSmin δ.  [51] 
         [0693]    An M-division factor should be defined as:  
           M=T   PSmin   /T   VCOmin =100/δ.  [52] 
         [0694]    To operate all DC-DC power conversion channels  16 ( k ) in a critical current mode, the APFC controller  201  produces an ON-OFF control signal of a variable operational frequency such that its period T PS =var depends on the RMS and instantaneous values of the primary AC voltage, on the output current, etc.  
         [0695]    Normally, the maximum operational period T PSmax  corresponds to the maximum output capacity and to the minimum value of the primary AC voltage, and the minimum operational period T PSmin  corresponds to zero output capacity and to the maximum value of the primary AC voltage, or to the instantaneous value of the primary AC voltage reaching zero.  
         [0696]    An ON-OFF control signal u 201 (t) is applied to the DATA input of the primary shift register  302 .  
         [0697]    Since being clocked by the VCO  306  output pulses of the M times proportional frequency, regardless of the initial frequency of the u 201 (t) signal, the primary shift register  302  provides a set of evenly time-staggered output signals conformable to the u 201 (t).  
         [0698]    The leading edge of the high logic level ON-state pulse of the last-in-the-row-appointed “channel” signal u QC(N) (t) is shifted in respect to the leading edge of the high logic level ON-state pulse of the u 201 (t) signal for a maximum time-delay interval Δt Dmax  such that:  
         Δ t   Dmax   =T   PSmin ( N− 1)/ N+T   VCOmin ,  [53] 
         [0699]    Therefore, the “digital” length D 302 , i.e. the quantity of the flip-flop cell q should be defined as:  
           D   302   =Δt   Dmax   /T   VCOmin ,  [54] 
         [0700]    To provide the “channel” clocking signals u QC(k) (t), the corresponding “channel” flip-flop cells q of the primary shift register  302  may be selected of those such that:  
         Q C(k)   =T   PSmin ( k− 1)/ T   VCOmin   N+ 1,( k= 1,2, . . . ,  N )  [55] 
         [0701]    Therefore, all DC-DC power conversion channels are operated in an evenly time-staggered fashion.  
         [0702]    To secure the constant t A  and t SS  intervals provided by the secondary shift register  304 ( k ), it is clocked by the constant frequency signal outputted by the CPO  301 .  
         [0703]    The “digital” length D 304 , i.e.the number of flip-flop cells q should be defined in accordance with [46].  
         [0704]    The corresponding “channel” outputs of the secondary shift register  304 ( k ) may be selected in accordance with [47] and [48].  
         [0705]    Therefore, the t A  and t SS  intervals do not depend on the variable frequency of the u 201 (t) signal.  
         [0706]    This results in securing the provision of soft-switching conditions to all controllable switches regardless of the variations of the initial operational frequency.  
         [0707]    To prevent the occurrence of continuous current mode within any power storage inductor  22 ( k ), the zero-current detectors  32 ( k ) postpone the starts of the successive operational cycles within the corresponding DC-DC power conversion channels  16 ( k ).  
         [0708]    An inductance value L 1  of the primary power carrying winding w 1  within each power storage inductor  22 ( k ) should be chosen such that the critical current mode will be maintained over a full range of operational current variation, i.e. at least, for the minimum operational frequency, for the minimum AC input voltage and for the maximum output capacity.  
         [0709]    [0709]FIG. 11( e,f ) illustrate the time—scaled waveforms of currents and voltages attributed to the power conversion processes within the third embodiment of the switching-mode AC-DC power converter according to the present invention.  
         [0710]    As can be seen, regardless of the critical current mode within the separate DC-DC power conversion channels, a high quality continuous current is maintained within the input and output circuitries of the AC-DC power converter.  
         [0711]    [0711]FIG. 12 illustrates the main principle of producing and arranging the time-staggered ON-OFF control signals for operating the multiple power conversion channels within the embodiments of the switching-mode AC-DC power converter according to the present invention.  
         [0712]    [0712]FIG. 13 illustrates the principle of providing the high quality continuous current mode to the primary AC power source while securing the discontinuous current mode within the separate DC-DC power conversion channels. The resultant input current waveform i Σ (t) shown in FIG. 13( a ) is produced by simultaneous summing the time-staggered input current waveforms i 22(K) (t) produced by the DC-DC power conversion channels.  
         [0713]    Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Although any methods and materials similar or equivalent to those described can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications and patent documents referenced in the present invention are incorporated herein by reference.  
         [0714]    While the principles of the invention have been made clear in illustrative embodiments, there will be immediately obvious to those skilled in the art many modifications of structure, arrangement, proportions, the elements, materials, and components used in the practice of the invention, and otherwise, which are particularly adapted to specific environments and operative requirements without departing from those principles. The appended claims are intended to cover and embrace any and all such modifications, with the limits only of the true purview, spirit and scope of the invention.