Abstract:
A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly within a the storage area of the memory device, so that the parasitic capacitance inherent within the address and control lines can be advantageously employed for introducing delay. The parasitic delay enables the clock, address, and control lines to be synchronized, yet does not require introducing delay blocks and so the overall speed of the memory device is improved.

Description:
FIELD OF THE INVENTION  
         [0001]    The invention relates to a memory device which uses the parasitic delay inherent within signal lines to compensate for an inherently slower clock signal.  
         BACKGROUND OF THE INVENTION  
         [0002]    It is well known for memory devices to latch address, data and command information before they are processed to a memory core, i.e. memory banks, blocks, or other type of storage areas. However, a problem with such latching is that the separate clock, address data, and control paths often have differing lengths and inherent delays. For example, FIG. 2 illustrates the an exemplary address signal line a clock signal XCLK used to latch in address data bit at latch  220 . It is important that the address at the output of address buffer  208  be valid when the clock causes the transistor  216  to turn on and latch in the address data.  
           [0003]    [0003]FIG. 1 shows the two important portions of the clock signal XCLK which are the setup time t SETUP  which occurs right before the transistor  216  is turned on, and the hold time t HOLD  which is the time during which the transistor  216  is on. The address, command, and data information on their associated signal lines has to be present and stable during the hold time t HOLD , which allows for a small amount of variation in the shape of the rising edge of the clock signal. The rising edge of the XCLK signal should ideally occur during the middle of the time address, command, or data signal is present and available for latching.  
           [0004]    Referring back to FIG. 2, the clock XCLK and ADDRESS signal lines typically have different signal propagation delay times. This is because the clock signal goes through a buffer  204  having a delay t d1 , a clock regenerator device  212  having an additional delay t d2 , and then the inherent delay t d3  of the clock line before arriving at transistor  216 . The clock regenerator  212  reduces noise and instability in a clock signal, but has the disadvantage of introducing delay in doing so. The transistor  216  controls the loading of the latch  220 . The address lines, only one of which is shown in FIG. 2 (as well as the data and command signal lines) only goes through the input buffer  208 , which imposes the delay t IB  which also includes a delay between buffer  208  and transistor  216 . Ideally, t d1 , t d2 , and t d3  should equal t IB . Unfortunately, this is seldom true, so that the signals on the address, command, and data lines arrive at different times than the clock signals, with the clock signal generally lagging behind the address, data, and control signals. In acute situations these time differences produce errors in the latching of the addresses, commands, and data.  
           [0005]    One known way of compensating for the differing signal delays includes adding delay in the fastest signal path to balance against the slowest signal path. Thus, FIG. 3 shows a conventional approach where an additional delay  316  is positioned between the input buffer  208  and transistor  216  in the address line of FIG. 2. The delay  316  can be achieved with serial inverters (FIG. 4), or serial inverters with a capacitor  512  located between them (FIG. 5). The added delays adjust the timing of an address, data or control signal in a measurable, predictable way. However, it is desired to get the address, command, and data signals to the memory core as quickly as possible. Introducing delay at the input buffer, though necessary for proper signal latching synchronization, reduces the overall speed of the memory device. Also, once the delay  316  is introduced into a circuit there is no way to remove or make adjustments to it.  
         BRIEF SUMMARY OF THE INVENTION  
         [0006]    In one aspect, the invention provides a memory device having an input buffer; a core memory storage area connected to the input buffer through a plurality of address, control, data and clock signal lines; a latch located within the core memory storage area and respectively associated with each address data, control line, whereby the parasitic capacitance of the address, data and control lines introduces sufficient delay to synchronize the arriving address, data, and command signals with clock signals transmitted along the clock lines. The memory device also has an optional delay associated with the input to each latch for adding a specific amount of delay if necessary, where the delay is adjustable. These and other features and advantages of the invention will be more clearly seen from the following detailed description of the invention which is provided in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 is a timing diagram for a memory device;  
         [0008]    [0008]FIG. 2 is a block diagram of a conventional memory device;  
         [0009]    [0009]FIG. 3 is a block diagram of another conventional memory device;  
         [0010]    [0010]FIG. 4 is a block diagram of a conventional delay circuit;  
         [0011]    [0011]FIG. 5 is a block diagram of another conventional delay circuit;  
         [0012]    [0012]FIG. 6 is a block diagram of a memory device of the present invention;  
         [0013]    [0013]FIG. 7 is a block diagram of a delay circuit which may be used with the memory device of the present invention;  
         [0014]    [0014]FIG. 8 is a block diagram of the memory device of the present invention showing command and address decoding; and  
         [0015]    [0015]FIG. 9 shows a processor circuit incorporating the memory device of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    [0016]FIG. 6 illustrates an embodiment of the present invention. Address, command, and data latches are located inside the memory banks  0 - 3 , instead of input buffers, as in the circuits of FIGS. 2 and 3. As stated, clock signals tend to take longer to arrive than address, command, and data signals. Thus, the parasitic capacitance inherent in the signal lines of FIG. 6 between the input buffers and the banks  0 - 3  of the memory core supplies the necessary delay.  
         [0017]    Although FIG. 6 shows only one of each type of address, command, and data latch within each bank, it is understood that there is one latch for every address, command, and data line. Because the FIG. 6 circuit latches data locally at the memory banks, it reduces the clock timing mismatches which could occur in the FIG. 2 arrangement. Nonetheless, there still may be instances where it is still necessary to introduce specific, quantifiable delay into the address, command, and data lines leading to the memory banks  0 - 3 . Such delays may be necessary because of process variations during fabrication of the memory device. Accordingly, in a second embodiment the present invention also provides for adjustable delays which compensate, if needed, for variations in signal line propagation time.  
         [0018]    [0018]FIG. 7 shows an adjustable delay circuit  704  which may be provided for this purpose. FIG. 7 illustrates a delay circuit provided in the signal line of an address bit, but it should be understood that the illustrated delay circuit may be provided in each of the signal lines for the address, data, and command signals. Elements A, B, and C are switches which can be selectively opened and closed. Closing switch A with switch B and C open introduce no delay. Opening switch A and closing switch B introduces delay from the two inverters I B1 , I B2  plus the capacitor C B . Closing switch C by itself while leaving switches A and B open introduces delay from the two inverters I C1 , I C2  plus the capacitor C c , which has a different capacitance from the capacitor C B . Finally, closing both switches B and C while leaving switch A open would achieve yet another delay because of the inverter pairs in parallel, combined with the separate capacitors C B  and C c . After memory device fabrication, the length and inherent delay of the address, data and control signal lines can be determined using digital sampling techniques. Consequently, delays in the address, command, and data signal lines can be introduced or adjusted by including suitable programmable delays in different lines to permit the address, data and control signals to arrive at the latches at the memory banks in a timely fashion.  
         [0019]    [0019]FIG. 8 shows a more detailed block diagram of an embodiment of the present invention employing the adjustable delay circuit of FIG. 7, which for brevity shows only banks  0  and  2 . Three sets of delay circuits  704  (address),  708  (control), and  712  (data) are shown, where each delay circuit is connected in a respective one of the address, command, and data signal lines which connect with the memory banks. The delay introduced by the delay circuits  704 ,  708 , and  712  can be programmed by closing various combinations of switches A, B, and C (FIG. 7) for each delay circuit associated with each signal line. The invention may be used with many different types of devices including but not limited to DRAM, SRAM, SDRAM, FLASH, DDRRAM, etc.  
         [0020]    [0020]FIG. 9 illustrates an exemplary processing system  900  which may utilize an electronic device comprising a memory device  610  constructed in accordance with any of the embodiments of the present invention disclosed above in connection with FIGS.  6 - 8 . The processing system  900  includes one or more processors  901  coupled to a local bus  904 . A memory controller  902  and a primary bus bridge  903  are also coupled the local bus  904 . The processing system  900  may include multiple memory controllers  902  and/or multiple primary bus bridges  903 . The memory controller  902  and the primary bus bridge  903  may be integrated as a single device  906 .  
         [0021]    The memory controller  902  is also coupled to one or more memory buses  907 . Each memory bus accepts memory components  908  which include at least one memory device  610  of the present invention. The memory components  908  may be a memory card or a memory module. Examples of memory modules include single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). The memory components  908  may include one or more additional devices  909 . For example, in a SIMM or DIMM, the additional device  909  might be a configuration memory, such as a serial presence detect (SPD) memory. The memory controller  902  may also be coupled to a cache memory  905 . The cache memory  905  may be the only cache memory in the processing system. Alternatively, other devices, for example, processors  901  may also include cache memories, which may form a cache hierarchy with cache memory  905 . If the processing system  900  include peripherals or controllers which are bus masters or which support direct memory access (DMA), the memory controller  902  may implement a cache coherency protocol. If the memory controller  902  is coupled to a plurality of memory buses  916 , each memory bus  916  may be operated in parallel, or different address ranges may be mapped to different memory buses  907 .  
         [0022]    The primary bus bridge  903  is coupled to at least one peripheral bus  910 . Various devices, such as peripherals or additional bus bridges may be coupled to the peripheral bus  910 . These devices may include a storage controller  911 , an miscellaneous I/O device  914 , a secondary bus bridge  915 , a multimedia processor  918 , and an legacy device interface  920 . The primary bus bridge  903  may also coupled to one or more special purpose high speed ports  922 . In a personal computer, for example, the special purpose port might be the Accelerated Graphics Port (AGP), used to couple a high performance video card to the processing system  900 . In addition to memory device  931  which may contain a buffer device of the present invention, any other data input device of FIG. 9 may also utilize a buffer device of the present invention including the CPU  901 .  
         [0023]    The storage controller  911  couples one or more storage devices  913 , via a storage bus  912 , to the peripheral bus  910 . For example, the storage controller  911  may be a SCSI controller and storage devices  913  may be SCSI discs. The I/O device  914  may be any sort of peripheral. For example, the I/O device  914  may be an local area network interface, such as an Ethernet card. The secondary bus bridge may be used to interface additional devices via another bus to the processing system. For example, the secondary bus bridge may be an universal serial port (USB) controller used to couple USB devices  917  via to the processing system  900 . The multimedia processor  918  may be a sound card, a video capture card, or any other type of media interface, which may also be coupled to one additional devices such as speakers  919 . The legacy device interface  920  is used to couple legacy devices, for example, older styled keyboards and mice, to the processing system  900 . In addition to memory device  931  which may contain a buffer device of the invention, any other data input device of FIG. 9 may also utilize a buffer device of the invention, including a CPU  901 .  
         [0024]    The processing system  900  illustrated in FIG. 9 is only an exemplary processing system with which the invention may be used. While FIG. 9 illustrates a processing architecture especially suitable for a general purpose computer, such as a personal computer or a workstation, it should be recognized that well known modifications can be made to configure the processing system  900  to become more suitable for use in a variety of applications. For example, many electronic devices which require processing may be implemented using a simpler architecture which relies on a CPU  901  coupled to memory components  908  and/or memory buffer devices  304 . These electronic devices may include, but are not limited to audio/video processors and recorders, gaming consoles, digital television sets, wired or wireless telephones, navigation devices (including system based on the global positioning system (GPS) and/or inertial navigation), and digital cameras and/or recorders. The modifications may include, for example, elimination of unnecessary components, addition of specialized devices or circuits, and/or integration of a plurality of devices.