Abstract:
A phase shifter that may be used in a quadrature modulator or an image suppression mixer. The phase shifter includes a low pass filter that receives an input signal and generates a first carrier signal. A high pass filter also receives the input signal and generates a second carrier signal. A phase difference detection circuit connected to the high and low pass filters receives the first and second carrier signals and generates a control signal based on the phase difference between the carrier signals. The control signal is fed back to at least one of the low pass filter and the high pass filter to compensate for phase errors caused by parasitic capacitance. The phase shifter has a small circuit area and is very accurate, allowing it to be used in communications devices.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to a phase shifter, and, more particularly, to a quadrature modulator and an image suppression mixer each of which includes the phase shifter. 
     FIG. 1 is a circuit diagram of a conventional phase shifter  11 . The phase shifter  11  comprises a low pass filter (LPF)  12  and a high pass filter (HPF)  13 . The LPF  12  is an integrating circuit including a resistor R 1  and a capacitor C 1 . The HPF  13  is a differential circuit including the capacitor C 2  and the resistor R 2 . 
     FIG. 2 is a graph showing the relationship between the frequency and phase in the LPF  12  and the HPF  13 . The LPF  12  receives an input signal LOin and generates a first carrier signal LO 1  having a phase of −45 degrees at a cutoff frequency fc. The HPF  13  receives the input signal LOin and generates a second carrier signal LO 2  having a phase of +45 degrees at the cutoff frequency fc. Accordingly, the phase difference between the output signals LO 1  and LO 2  is substantially 90 degrees. 
     However, the phase shifter  11  of FIG. 1 is a theoretical circuit, a real circuit therefor being shown in FIG.  3 . The capacitors C 1 , C 2  each has a parasitic resistor Rs. Therefore, the LPF  12  generates a first carrier signal LO 3  having a phase of (−45−Δ) degrees, and the HPF  13  generates a second carrier LO 4  having a phase of (+45+Δ) degrees. Accordingly, the phase difference between the two signals is not exactly 90 degrees. As a result, a circuit for compensating for the phase errors generated by the parasitic resistors Rs is required. This increases the circuit area of the phase shifter  11 . 
     Another conventional digital phase shifter comprises a frequency divider consisting of a flip-flop. The frequency divider divides the frequency of an input signal in half. The phase shifter generates two output signals in which the phase difference between the signals is substantially 90 degrees using a frequency division signal. However, to divide the frequency of the input signal in half, a frequency multiplier for supplying the input signal in which the frequency is multiplied by two to the frequency divider is required. The provision of the frequency multiplier increases the circuit area of the phase shifter. 
     A quadrature modulator used in digital mobile communications includes a phase shifter. It is preferable for the quadrature modulator to have a small circuit area and perform modulation with high accuracy. Therefore, a phase shifter having high phase accuracy and small circuit area is necessary. 
     FIG. 4 is a block diagram of a conventional image suppression mixer circuit (hereinafter referred to as mixer circuit)  211 . The mixer circuit removes an image component contained in the output signal. The mixer circuit  211  includes first and second phase shifters  212  and  213  and an image suppression circuit  214 . The image suppression circuit  214  includes first and second mixers  215  and  216  and a adder  217 . 
     The first phase shifter  212  receives an intermediate frequency signal IFin and generates first and second intermediate frequency signals IF 0  and IF 90  in which the phase difference between the signals is substantially 90 degrees. The phase difference of the second intermediate frequency signal IF 90  for a first intermediate frequency signal LO 0  is 90 degrees. The second phase shifter  213  receives a local signal LOin having a local oscillation frequency and generates first and second local signals LO 0  and LO- 90  in which the phase difference between the signals is substantially 90 degrees. The phase difference of the second local signal LO- 90  from the first local signal LO 0  is −90 degrees. 
     The first mixer  215  multiplies the first intermediate frequency signal IF 0  by the first local signal LO 0  and generates a first modulation signal V 1 . The first modulation signal V 1  is obtained in accordance with the following equation (1).              V1   =       cos        (     2      π                   f   LO        t     )       ×     cos        (     2      π                   f   IF        t     )                     =       1   2          [       cos        {     2        π        (       f   LO     +     f   IF       )          t     }       +     cos        {     2        π        (       f   LO     -     f   IF       )          t     }         ]                                    
     The second mixer  216  multiplies the second intermediate frequency signal IF 90  by the second local signal LO- 90  and generates a second modulation signal V 2 . The second modulation signal V 2  is obtained in accordance with the following equation (2).              V2   =       cos        (       2      π                   f   LO        t     +     90      °       )       ×     cos        (       2      π                   f   IF        t     -     90      °       )                     =       1   2          [       cos        {     2        π        (       f   LO     +     f   IF       )          t     }       -     cos        {     2        π        (       f   LO     -     f   IF       )          t     }         ]                                    
     The adder  217  receives the first and second modulation signals V 1  and V 2  from the first and second mixers  215  and  216  and generates an output signal RFout by combining the first and second modulation signals V 1  and V 2 . The output signal RFout is obtained in accordance with the following equation (3).              RFout   =     V1   +   V2                 =     cos        {     2        π        (       f   LO     +     f   IF       )          t     }                                    
     The output signal RFout includes only the (fL 0 +fIF) component. In Equations (1) and (2), the (fL 0 −fIF) component is an image frequency signal component. Thus, the mixer circuit  11  suppresses or rejects the image frequency component. 
     The mixer circuit  211  can also be used as a down-converter that reduces the frequency of an input signal. In this case, the first phase shifter  212  receives a high frequency input signal RFin that is a receiving signal for communication devices. The mixer circuit  211  combines the input signal RFin and the local signal LOin having the local oscillation frequency and generates an output signal IFout having an intermediate frequency that is lower than that of the input signal RFin. The output signal IFout is obtained in accordance with the following equation (4). 
     
       
         IFout=V 1 +V 2 =cos{2π(f L0 +f IF ) t}   
       
     
     The mixer circuit  211  implements highly accurate image suppression by accurately maintaining the phase difference among the output signals IF 0 , IF 90 , LO 0 , and LO- 90  of the first and second phase shifters  212  and  213  at 90 degrees. However, if the phase shifters  212  and  213  are not manufactured evenly, the phase difference of the output signal is not accurately maintained at 90 degrees. This makes it difficult to fully suppress the image frequency component. 
     To solve the aforementioned problems, Japanese Unexamined Patent Publication No. 8-125447 discloses an improved image suppression mixer circuit. The image suppression mixer circuit comprises two unit mixers that output direct current (DC) signals and a comparator that receives the DC signals output from the two unit mixers via a variable phase shifter and a phase shifter and calculates the phase difference of the first and second IF signals based on the level difference of the DC signals. The image suppression mixer circuit further includes a driver that controls the variable shifter so that a phase error is zero. Thus, a relative phase error is corrected and an image frequency component is suppressed. However, because the variable phase shifter is connected to the input of a adder, the mixer circuit is used only for the application of down-conversion. Further, the mixer circuit includes a coupler. Neither the mixer nor the coupler is integrated on a semiconductor substrate. This impedes miniaturization of the mixer circuit. 
     It is an object of the present invention to provide a phase shifter that obtains the two output signals in which the phase difference between the signals is substantially 90 degrees and has a small circuit area. 
     It is the second object of the present invention to provide an image suppression mixer that reduces differences due to uneven manufacturing. 
     SUMMARY OF THE INVENTION 
     Briefly stated, the present invention provides a phase shifter. The phase shifter includes a low pass filter for receiving an input signal and generating a first carrier signal and a high pass filter for receiving the input signal and generating a second carrier signal. A phase difference detection circuit is connected to the low pass filter and the high pass filter and generates a control signal based on a phase difference between the first and second carrier signals. At least one of the low pass filter and the high pass filter includes a variable element that changes its own characteristics in accordance with the control signal. 
     The present invention further provides a quadrature modulator including a phase shifter for receiving an input signal and generating first and second carrier signals. The phase shifter includes a low pass filter for receiving the input signal and generating the first carrier signal and a high pass filter for receiving the input signal and generating the second carrier signal. A phase difference detection circuit is connected to the low pass filter and the high pass filter and generates a control signal based on a phase difference between the first and second carrier signals. At least one of the low pass filter and the high pass filter includes a variable element for changing its own characteristics in accordance with the control signal. A quadrature modulation circuit is connected to the phase shifter and receives the first and second carrier signals and first and second base band signals and generating a modulation signal. 
     The present invention provides an image suppression mixer including first to fourth phase shifters. The first phase shifter receives a first input signal and generates first and second signals having a phase difference of a predetermined degree. The second phase shifter receives a second input signal and generates third and fourth signals having a phase difference between of a predetermined degree. The third phase shifter is connected to the first phase shifter and receives the second signal from the first shifter to shift the phase of the second signal in accordance with a first control signal. The fourth phase shifter is connected to the second phase shifter and receives the fourth signal from the second phase shifter to shift the phase of the fourth signal in accordance with a second control signal. A first phase difference detection circuit is connected to the first and third phase shifters and detects the phase difference between the first and second signals to generate a first detection signal indicating the phase difference. A second phase difference detection circuit is connected to the second and third phase shifters and detects the phase difference between the third and fourth signals to generate a second detection signal indicating the phase difference. A differential circuit is connected to the third and fourth phase shifters and the first and second phase difference detection circuits and receives the first and second detection signals and generating the first and second control signals. The first control signal originates from the difference between the first and second detection signals, and the second control signal is an inverse of the first control signal. An image suppression circuit is connected to the first to fourth phase shifters, receives the first to fourth signals, generates a first mixing signal by mixing the first and third signals, generates a second mixing signal by mixing the second and fourth signals, and generates a modulation output signal by combining the first and second mixing signals. 
     The present invention further provides an image suppression mixer including a first phase shifter for receiving a first input signal and generating first and second signals having a phase difference of a predetermined degree and a second phase shifter for receiving a second input signal and generating third and fourth signals having a phase difference of a predetermined degree. A first phase difference detection circuit is connected to the first phase shifter and detects the phase difference between the first and second signals to generate a first detection signal indicating the phase difference. A second phase difference detection circuit is connected to the second phase shifter and detects the phase difference between the third and fourth signals to generate a second detection signal indicating the phase difference. A third phase shifter is connected between the first and second phase difference detection circuits and one of the first and second phase shifters and receives one of the second signal and the fourth signal from the connected one of the first phase shifter and the second phase shifter to shift the phase of the received signal in accordance with a control signal. A differential circuit is connected to the third phase shifter and the first and second phase difference detection circuits and receives the first and second detection signals to generate the control signal originating from the difference between the first and second detection signals. An image suppression circuit is connected to the first to third phase shifters, receives the first to fourth signals, generates a first mixing signal by mixing the first and third signals, generates a second mixing signal by mixing the second and fourth signals, and generates a modulation output signal by combining the first and second mixing signals. 
     The present invention provides an image suppression mixer including a first phase shifter for receiving a first input signal and generating first and second signals having a phase difference of a predetermined degree. The first phase shifter shifts the phase of the second signal in accordance with a first control signal. The image suppression mixer further includes a second phase shifter for receiving a second input signal and generating third and fourth signals having a phase difference of a predetermined degree. The second phase shifter shifts the phase of the fourth signal in accordance with a second control signal. A first phase difference detection circuit is connected to the first phase shifter and detects the phase difference between the first and second signals to generate a first detection signal indicating the phase difference. A second phase difference detection circuit is connected to the second phase shifter and detects the phase difference between the third and fourth signals to generate a second detection signal indicating the phase difference. A differential circuit is connected to the first and second phase shifters and the first and phase difference detection circuits and receives the first and second detection signals and generating the first and second control signals. Each of the control signals originating from the difference between the first and second detection signals. The second control signal is an inverse of the first control signal. An image suppression circuit is connected to the first and second phase shifters, receives the first to fourth signals, generates a first mixing signal by mixing the first and third signals, generates a second mixing signal by mixing the second and fourth signals, and generates a modulation output signal by combining the first and second mixing signals. 
     Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
     FIG. 1 is a circuit diagram of a conventional phase shifter; 
     FIG. 2 is a graph showing the relationship between the frequency and phase of the phase shifter of FIG. 1; 
     FIG. 3 is an equivalent circuit diagram of a conventional phase shifter; 
     FIG. 4 is a schematic block diagram of a conventional mixer; 
     FIG. 5 is a schematic block diagram of a quadrature modulator including a phase shifter according to a first embodiment of the present invention; 
     FIG. 6 is a circuit diagram of the phase shifter of FIG.  5 . 
     FIG. 7 is a graph showing the relationship between the voltage and junction capacitance of a transistor of the phase shifter of FIG. 5; 
     FIG. 8 is a circuit diagram of a first modified phase shifter according to the first embodiment; 
     FIG. 9 is a circuit diagram of a second modified phase shifter according to the first embodiment; 
     FIG. 10 is a circuit diagram of a third modified phase shifter according to the first embodiment; 
     FIG. 11 is a circuit diagram of a fourth modified phase shifter according to the first embodiment; 
     FIG. 12 is a circuit diagram of a phase shifter according to a second embodiment of the present invention; 
     FIG. 13 is a circuit diagram of a phase shifter according to a third embodiment of the present invention; 
     FIG. 14 is a circuit diagram of a modified phase shifter according to the third embodiment; 
     FIG. 15 is a circuit diagram of a phase shifter according to a fourth embodiment of the present invention; 
     FIG. 16 is a circuit diagram of a phase shifter according to a fifth embodiment of the present invention; 
     FIG. 17 is a circuit diagram of a modified phase shifter according to the fifth embodiment; 
     FIG. 18 is a schematic bock diagram of a quadrature modulator according to a sixth embodiment of the present invention; 
     FIG. 19 is a block circuit diagram of an image suppression mixer according to a seventh embodiment of the present invention; 
     FIG. 20 is a circuit diagram of a phase difference detection circuit of the image suppression mixer of FIG. 19; 
     FIG. 21 is a circuit diagram of a differential circuit of the image suppression mixer of FIG. 19; 
     FIG. 22 is a circuit diagram of a phase shifter of the image suppression mixer of FIG. 19; 
     FIG. 23 is a block circuit diagram of a first modified image suppression mixer according to the seventh embodiment; 
     FIG. 24 is a block circuit diagram of a second modified image suppression mixer according to the seventh embodiment; 
     FIG. 25 is a block circuit diagram of an image suppression mixer according to an eighth embodiment of the present invention; 
     FIG. 26 is a block circuit diagram of a first modified image suppression mixer according to the eighth embodiment; 
     FIG. 27 is a block circuit diagram of a second modified image suppression mixer according to the eighth embodiment; 
     FIG. 28 is a block circuit diagram of an image suppression mixer according to a ninth embodiment of the present invention; and 
     FIG. 29 is a circuit diagram of a phase shifter of the image suppression mixer of FIG.  28 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the drawings, like numerals are used for like elements throughout. 
     (First Embodiment) 
     FIG. 5 is a schematic block diagram of a quadrature modulator  21  used in a digital mobile communication device. The quadrature modulator  21  includes a phase shifter  22  and a quadrature modulation unit  23 , all of which is preferably formed on a single semiconductor substrate. The quadrature modulation unit  23  includes first and second modulation mixers  24  and  25  and an adder  26 . 
     The phase shifter  22  receives a carrier signal LOin and generates first and second carrier signals LO 1  and LO 2  in which the phase difference between the signals is substantially 90 degrees. The first modulation mixer  24  receives a first base band signal I and the first carrier signal LO 0  from the phase shifter  22  and generates a first modulation signal V 1  by mixing the first base band signal I and the first carrier signal LO 1 . The second modulation mixer  25  receives a second base band signal Q and the second carrier signal LO 2  from the phase shifter  22  and generates the second modulation signal V 2  by mixing the second base band signal Q and the second carrier signal LO 2 . 
     The adder  26  receives the first and second modulation signals V 1  and V 2  from the modulation mixers  24  and  25  and generates the output signal RFout by adding the first and second modulation signals V 1  and V 2 . 
     FIG. 6 is a circuit diagram of the phase shifter  22  according to a first embodiment of the present invention. The phase shifter  22  includes a CR phase shifter  31 . The CR phase shifter  31  includes a low pass filter (LPF)  32  and a high pass filter (HPF)  33 . 
     The LPF  32  includes the resistor R 1  and an NPN transistor Tr 1  as a variable element. The input signal LOin is supplied to the first terminal of the resistor R 1  and the second terminal of the resistor R 1  is connected to the emitter of the transistor Tr 1 . The collector of the transistor Tr 1  is connected to a low potential power supply VSS and the base of the transistor Tr 1  is connected to its own collector. This allows the transistor Tr 1  to have a junction capacitance CJ according to the pn junction between the base and emitter. The junction capacitance CJ corresponds to the difference between the voltage of the power supply VSS and the voltage of a node N 1  between the resistor R 1  and the emitter. The LPF  32  operates as an integrating circuit. The LPF  32  receives the input signal LOin and outputs an output signal from the node N 1 . The output signal has a phase that corresponds to the resistance of the resistor R 1  and the junction capacitance CJ of the transistor Tr 1 . 
     The HPF  33  is a differential circuit including a capacitor C 1  and a resistor R 2 . The input signal LOin is supplied to the first terminal of the capacitor C 1  and the second terminal of the capacitor C 1  is connected to the first terminal of the resistor R 2 . The second terminal of the resistor R 2  is connected to the low potential power supply VSS. The capacitor C 1  has a parasitic resistor Rs. The parasitic resistor Rs, shown in FIG. 6, is a resistance generated by providing the capacitor C 1 , and it is well known to one skilled in the art that no such actual resistor is connected to a practical circuit. 
     The HPF  33  receives the input signal LOin and outputs an output signal from a node N 2  between the capacitor C 1  and the resistor R 2 . The output signal has a phase that corresponds to the resistance of the resistor R 2 , the resistance of the parasitic resistor Rs, and the capacitance of the capacitor C 1 . 
     The node N 1  is connected to the first terminal of a capacitor C 11 , and the second terminal of the capacitor C 11  is connected to a phase difference detection circuit  34 . The node N 2  is connected to the first terminal of a capacitor C 12 , and the second terminal of the capacitor C 12  is connected to the phase difference detection circuit  34 . 
     The capacitors C 11  and C 12  remove the DC component from the output signal of the LPF  32  and the HPF  33  by means of AC coupling, respectively, which allows the first and second carrier signals LO 1  and LO 2  having an AC component to be supplied to the phase difference detection signal  34 . 
     The phase difference detection circuit  34  is preferably a frequency mixer (frequency converter). The phase difference detection circuit  34  detects the phase difference of the first and second carrier signals LO 1  and LO 2  and generates an output signal S 1  that corresponds to their detected phase differences. The signal S 1  includes a DC component. The output signal S 1  (MIXout) is obtained in accordance with the following equation (5).              MIXout   =       cos        (       2      π                 ft     +     φ      1       )       ×     cos   (       2      π                 ft     +     φ      2       )                   =       1   2          [       cos        {       2        π        (     2      f     )          t     +     φ      1     +     φ      2       }       +     cos        (       φ      1     -     φ      2       )         ]                                    
     φ1 is the phase of the first carrier signal LO 1  and φ2 is the phase of the second carrier signal LO 2 . The second term in the aforementioned equation is the DC component. 
     A second LPF  35  receives the signal S 1  generated by the phase difference detection circuit  34  and provides a control signal S 2  that is the DC component of the complementary signal to the node N 1 . Thus, the control signal S 2  originating from the phase difference of the first and second carrier signals LO 1  and LO 2  is fed back to the transistor Tr 1 . The feedback of the control signal S 2  changes the junction capacitance CJ that corresponds to the voltage difference between the voltage of the node N 1  and the voltage of the low potential power supply VSS. Subsequently, the junction capacitance CJ is controlled so that the first and second phase difference signals LO 1  and LO 2  in which the phase difference between the signals is substantially 90 degrees is generated. Hereupon, because the capacitor C 11  allows only the AC component to pass through, the control signal S 2  is not supplied to the phase difference detection circuit  34  via the capacitor C 11 . 
     For example, if a voltage VJ of the node N 1  is two (2) volts and the phase difference of the first and second carrier signals LO 0  and LO 2  is 92 degrees, the phase difference detection circuit  34  outputs the control signal S 2  having a voltage Vs (2−cos(φ1-φ2)=2−cos 92=2.035 (volts)). When the voltage Vs is applied to the node N 1 , the junction capacitance CJ of the transistor Tr 1  is reduced (see FIG.  7 ). This allows the cutoff frequency fc of the LPF  32  to increase and the phase φ1 of the first carrier signal LO 0  to increase. As a result, the phase difference of the first and second carrier signals LO 1  and LO 2  approaches 90 degrees. In FIG. 7, the forward voltage is negative. 
     As another example, the case where the voltage VJ of the node N 1  is two (2) volts and the phase difference of the first and second carrier signals LO 0  and LO 2  is 89 degrees is described. In this case, the phase difference is overshot by the feedback. The phase difference detection circuit  34  outputs the control signal S 2  having a voltage Vs (2−cos 89 =1.983 volts). When the voltage Vs is applied to the node N 1 , the junction capacitance CJ of the transistor Tr 1  increases. This allows the cutoff frequency fc of the LPF  32  to decrease and the phase φ1 of the first carrier signal LO 1  to decrease. As a result, the phase difference of the first and second signals LO 1  and LO 2  approaches 90 degrees. 
     As described above, for the first embodiment, the junction capacitance of the transistor Tr 1  is changed by feedback control. This prevents having to increase the circuit area and allows the first and second carrier signals LO 1  and LO 2  in which the phase difference between the signals is substantially 90 degrees to be accurately obtained. The quadrature modulator  21  performs highly accurate modulation using the phase shifter  22  that generates those first and second carrier signals LO 1  and LO 2 . 
     FIG. 8 shows a first modification example of the first embodiment. A phase shifter  22   a  includes a CR phase shifter  31   a , the phase difference detection circuit  34 , an LPF  37 , and the capacitors C 11  and C 12 . The CR phase shifter  31   a  includes the LPF  12  and an HPF  36 . The HPF  36  includes a resistor R 2  and an NPN transistor Tr 2  as a variable element (variable-capacitance element). The input signal LOin is supplied to the emitter of the transistor Tr 2 , and the base and collector of the transistor Tr 2  are connected to the low potential power supply VSS via the resistor R 2 . The node N 2  between the collector of the transistor Tr 2  and the resistor R 2  is connected to the second LPF  37 . The second LPF  37  receives an inverse signal S 3  of the output signal S 1  (not shown) generated by the phase difference detection circuit  34  and supplies a control signal S 4  to the node N 2 . The control signal S 4  is an inverse signal of the control signal S 2  (FIG.  6 ). The phase shifter  22   a  cancels the phase shift originating from the parasitic resistor Rs of the capacitor C 1  of the LPF  12  by feedback-controlling the junction capacitance of the transistor Tr 2 . 
     FIG. 9 shows a second modification example according to the first embodiment. A phase shifter  22   b  includes a CR phase shifter  31   b , the phase difference detection circuit  34 , the LPF  35  and the LPF  37 , and the capacitors C 11  and C 12 . The CR phase shifter  31   b  includes the LPF  32  and the LPF  36 . The LPF  32  includes the resistor R 1  and the first NPN transistor Tr 1 , and the HPF  36  includes a second NPN transistor Tr 2  and the resistor R 2 . The control signal S 2  is supplied to the node N 1  via the second LPF  35 . The control signal S 4  is supplied to the node N 2  via the third LPF  37 . The phase shifter  22   b  outputs the first and second carrier signals LO 1  and LO 2  having a phase difference of 90 degrees by feedback-controlling the junction capacitance of each of the transistors Tr 1  and Tr 2 . 
     FIG. 10 is a circuit diagram of a phase shifter  22   c  that uses a diode D 1  instead of the transistor Tr 1 . An LPF  32   a  of the phase shifter  22   c  includes the resistor R 1  and the diode D 1  connected in series. 
     FIG. 11 is a circuit diagram of a phase shifter  22   d  that uses the diode D 1  instead of the transistor Tr 2  in an HPF  36   a . The HPF  36   a  includes the resistor R 2  and the diode D 1  connected in series. The phase shifters  22   c  (FIG. 10) and  22   d  (FIG. 11) generate the first and second carrier signals LO 1  and LO 2  having a phase difference of 90 degrees by feedback-controlling the junction capacitance of the diode D 1 . 
     (Second Embodiment) 
     FIG. 12 is a circuit diagram of a phase shifter  41  according to a second embodiment of the present invention. The phase shifter  41  includes a CR phase shifter  42 , the phase difference detection circuit  34 , the second LPF  35 , and the capacitors C 11  and C 12 . The CR phase shifter  42  includes the LPF  12  and an HPF  43 . The HPF  43  includes the capacitor C 2  and a P-channel MOS transistor Tr 11  as a variable resistor element. An N-channel MOS transistor may be used instead of the P-channel MOS transistor. 
     The input signal LOin is supplied to the first terminal of the capacitor C 2  and the second terminal of the capacitor C 2  is connected to the drain of the MOS transistor Tr 11 . The capacitor C 2  includes the parasitic resistance Rs connected in series. The source of the MOS transistor Tr 11  is connected to the low potential power supply VSS and the gate is connected to the LPF  35 . 
     The phase difference detection circuit  34  generates the signal S 1  having a voltage that corresponds to the phase difference of the first and second carrier signals LO 1  and LO 2 . The LPF  35  receives the signal S 1  from the phase difference detection circuit  34  and supplies the control signal S 2  to the gate of the MOS transistor Tr 11 . When the N-channel MOS transistor is used, the inverse signal of the control signal S 2  is supplied to the gate of the N-channel MOS transistor. 
     The MOS transistor Tr 11  has an ‘on’ resistance that corresponds to the voltage of the control signal S 2  supplied to the gate. Accordingly, the phase difference of the first and second carrier signals LO 1  and LO 2  approaches 90 degrees by feedback-controlling the ‘on’ resistance. 
     As another alternative example of the second embodiment, the MOS transistor Tr 11  may also be used instead of the resistor R 1  in the LPF  12 . 
     (Third Embodiment) 
     FIG. 13 is a circuit diagram of a phase shifter  51  according to a third embodiment of the present invention. The phase shifter  51  includes a CR phase shifter  52 , the phase difference detection circuit  34 , the second LPF  35 , and the capacitors C 11  and C 12 . The CR phase shifter  52  includes an LPF  53  and the HPF  33 . 
     The LPF  53  includes the diode D 1  as a variable-capacitance element connected in parallel to the capacitor C 1  and the parasitic resistor Rs connected in series. Alternatively, the NPN transistor Tr 1  may be connected in parallel to the capacitor C 1  and the parasitic resistor Rs instead of the diode D 1 . 
     The diode D 1  has a junction capacitance according to the control signal S 2  output from the LPF  35 . Accordingly, the cutoff frequency of the LPF  53  is determined depending on the combined capacitance of the capacitor C 1  and the diode D 1  and the combined resistance of the resistor R 1  and the parasitic resistor Rs. Also, the capacitance of the LPF  53  is finely adjusted by feedback control. In other words, the cutoff frequency of the LPF  53  is changed by the control signal S 2  according to the phase difference of the first and second carrier signals LO 1  and LO 2 . This allows the first and second carrier signals LO 0  and LO 2  having a phase difference of 90 degrees to be generated. 
     As an alternative example of the third embodiment, a diode may be connected in parallel to the capacitor C 2  of the HPF  33 . In this case, as in FIGS. 8 and 11, the control signal S 4  is supplied from the phase difference detection circuit  34  to the node N 2  via the third LPF  37 . Further, diodes may be connected in parallel to both the capacitor C 1  of the LPF  12  and the capacitor C 2  of the HPF  33 . 
     FIG. 14 shows a modification example of the third embodiment. An HPF  54  of a phase shifter  51   a  includes the MOS transistor Tr 11  connected in parallel to the resistor R 2 . The control signal S 2  is supplied to the gate of the MOS transistor Tr 11 . The ‘on’ resistance of the MOS transistor Tr 11  is controlled using the control signal S 2 . This allows the phase shifter  51   a  to generate the first and second carrier signals LO 1  and LO 2  having a phase difference of 90 degrees. As an alternative example, the MOS transistor Tr 11  may be connected in parallel to the resistor R 1  of the LPF  12 . In this case, the control signal S 4  is supplied to the gate of the MOS transistor Tr 11 . 
     (Fourth Embodiment) 
     FIG. 15 is a circuit diagram of a phase shifter  61  according to a fourth embodiment of the present invention. The phase shifter  61  includes the CR phase shifter  31  including the LPF  32  and the HPF  33 , the phase difference detection circuit  34 , the second LPF  35 , capacitors C 11  and C 12 , a capacitor C 21 , and a resistor R 11 . Any one of the CR phase shifters  31   a  to  31   d  (FIGS.  8 - 11 ), and  52  (FIG. 13) may also be used instead of the CR phase shifter  31 . 
     The input signal LOin is applied to the first terminal of the capacitor C 21  and the second terminal of the capacitor C 21  is connected to the LPF  32  and the HPF  33 . This allows the LPF  32  and the HPF  33  to receive the input signal LOin via the capacitor C 21 . 
     The first terminal of the resistor R 11  is connected to the LPF  35 , and the second terminal of the resistor R 11  is connected to a node N 3  between the HPF  33  and the capacitor C 21 . The LPF  32  is connected to the node N 3 . 
     The signal S 1  of the phase difference detection circuit  34  is supplied to the LPF  32  and the control signal S 2  from the second LPF  35  is supplied to the LPF  32  and the HPF  33  via the resistor R 11 . The control signal S 2  is applied to the node N 1  via the resistor R 1  of the LPF  32 . Thus, the junction capacitance of the transistor Tr 1  varies according to the voltage of the control signal S 2 . Thus, the junction capacitance of the transistor Tr 1  is feedback-controlled by the control signal S 2  generated based on the phase difference of the first and second carrier signals LO 1  and LO 2 . This allows the phase shifter  61  to generate the first and second carrier signals LO 1  and LO 2  having a phase difference of 90 degrees. 
     The capacitor C 21  connects the input terminal of the phase shifter  61  and the LPF  32  and HPF  33  by AC coupling. The AC input signal LOin passes through the capacitor C 21  and is supplied to the LPF  32  and the HPF  33 . However, the DC control signal S 2  does not pass through the capacitor C 21 . Accordingly, the capacitor C 21  prevents the control signal S 2  from being supplied to the input terminal. 
     (Fifth Embodiment) 
     FIG. 16 is a circuit diagram of a phase shifter  71  according to a fifth embodiment of the present invention. The phase shifter  71  includes a CR phase shifter  72 , the capacitors C 11  and C 12 , and a phase difference detection circuit  73 . 
     The CR phase shifter  72  includes an LPF  74  and the HPF  33 . The LPF  74  includes the resistor R 1 . The first terminal of the resistor R 1  is connected to the input terminal of the phase shifter  71  and the capacitor C 1  of the HPF  33 , and the second terminal of the resistor R 1  is connected to the phase difference detection circuit  73  via the capacitor C 11 . The LPF  74  receives the input signal LOin and supplies the first carrier signal LO 1  to the phase difference detection circuit  73  via the capacitor C 11 . 
     The HPF  33  is a differential circuit including the capacitor C 1  and the resistor R 2 . The first terminal of the capacitor C 1  is connected to the input terminal, and the second terminal of the capacitor C 1  is connected to the low potential power supply VSS via the resistor R 2 . The capacitor C 1  has the parasitic resistor Rs. The node N 2  between the capacitor C 1  and the resistor R 2  is connected to the phase difference detection circuit  73  via the capacitor C 12 . The HPF  33  receives the input signal Loin and supplies the second carrier signal LO 2  to the phase difference detection circuit  73  via the capacitor C 12 . 
     The phase difference detection circuit  73  is preferably a double balanced mixer (DBM). The phase difference detection circuit  73  includes NPN transistors Tr 21  to Tr 26  and Tr 31 , resistors R 21  to R 26 , capacitors C 31  and C 32 , and a constant current source  78 . 
     The first and second transistors Tr 21  and Tr 22  have their emitters connected together to form a first differential amplifier  75 . The collectors of the first and second transistors Tr 21  and Tr 22  are connected to a high potential power supply Vcc via the resistors R 21  and R 22 . A first bias voltage VB 1  is supplied to the bases of the first and second transistors Tr 21  and Tr 22  via the resistors R 23  and R 24 , respectively. The first carrier signal LO 0  is further supplied to the base of the first transistor Tr 21 . The base of the second transistor Tr 22  is connected to the low potential power supply VSS via the capacitor C 31 . 
     The third and fourth transistors Tr 23  and Tr 24  have their emitters connected together to form a second differential amplifier  76 . The collectors of the third and fourth transistors Tr 23  and Tr 24  are connected to the high potential power supply Vcc via the resistors R 21  and R 22 . A first bias voltage VB 1  is supplied to the bases of the third and fourth transistors Tr 23  and Tr 24  via the resistors R 23  and R 24 . The base of the third transistor Tr 23  is connected to the low potential power supply VSS via the capacitor C 31 . The first carrier signal LO 1  is supplied to the base of the fourth transistor Tr 24 . 
     The fifth and sixth transistors Tr 25  and Tr 26  have their emitters connected together to form a third differential amplifier  77 . The emitters of the fifth and sixth transistors Tr 25  and Tr 26  are further connected to the low potential power supply VSS via the constant current source  78 . The collector of the fifth transistor Tr 25  is connected to the emitters of the first and second transistors Tr 21  and Tr 22 . The collector of the sixth transistor Tr 26  is connected to the emitters of the third and fourth transistors Tr 23  and Tr 24 . A second bias voltage VB 2  is supplied to the bases of the fifth and sixth transistors Tr 25  and Tr 26  via the resistors R 25  and R 26 , respectively. The second carrier signal LO 2  is further supplied to the base of the fifth transistor Tr 25 . The base of the sixth transistor Tr 26  is connected to the low potential power supply VSS via the capacitor C 32 . 
     The node N 3  between the first transistor Tr 21  and the resistor R 21  is the output terminal of the phase difference detection circuit  73 . A control signal S 5  based on the phase difference of the first and second carrier signals LO 1  and LO 2  is applied to the node between the resistor R 1  and capacitor C 11  of the LPF  74  from the output terminal. 
     An NPN transistor Tr 31  has a collector connected to the node N 3 , an emitter connected to the high potential power Vcc, and a base connected to its own collector. The transistor Tr 31  has a junction capacitance that corresponds to the difference between the voltage of the high potential power Vcc and the voltage of the node N 3  (i.e., the voltage of the control signal S 5 ). Connecting the transistor Tr 31  between the high potential power Vcc and the node N 3  is equivalent to connecting a transistor between the node N 3  and the low potential power supply VSS in the AC region. Accordingly, the junction capacitance of the transistor Tr 31  is equivalent to the capacitance of the LPF  74  (i.e., the junction capacitance of the transistor Tr 1  of FIG.  6 ). Hence, the phase difference detection circuit  73  outputs the control signal S 5  using the transistor Tr 31  as a load. Thus, the phase of the first carrier signal LO 0  of the LPF  74  varies in accordance with the control signal S 5 . Such feedback control allows the phase shifter  71  to generate the first and second carrier signals LO 1  and LO 2  having a phase difference of 90 degrees. 
     FIG. 17 shows the modification example according to the fifth embodiment. A phase difference detection circuit  73   a  is a circuit in which a seventh transistor Tr 27  as an output transistor and a second constant current source  79  are appended to the phase difference detection circuit  73 . The seventh transistor Tr 27  has a collector connected to the high potential power supply Vcc, an emitter connected to the low potential power supply VSS via the second constant current source  79 , and a base connected to the node N 3 . The transistor Tr 31  is connected between the high potential power supply Vcc and the node N 4  located between the transistor Tr 27  and the second constant current source  79 . The node N 4  is the output terminal of the phase difference detection circuit. The control signal S 4  from the output terminal is supplied to the node between the resistor R 1  and the capacitor C 11  of the LPF  74 . 
     The transistor Tr 31  has a junction capacitance according to the voltage difference between the high potential power supply Vcc and the voltage of the node N 4  and operates as the load of the phase difference detection circuit  73   a . Connecting the transistor Tr 31  between the high potential power supply Vcc and the node N 4  is equivalent to connecting a transistor between the node N 4  and the low potential power supply VSS in the AC region. By outputting a control signal S 6  using the transistor Tr 31  as a load, the first and second carrier signals LO 1  and LO 2  having a phase difference of 90 degrees are generated. 
     FIG. 18 is a schematic block diagram of a quadrature modulator  81  used in a digital mobile communication device. The quadrature modulator  81  includes a phase shifter  82  and the quadrature modulation unit  23 , all of which may be integrated on a single semiconductor substrate. The quadrature modulation unit  23  includes the first and second modulation mixers  24  and  25  and the adder  26 . The phase shifter  82  includes the CR phase shifter  31 , the phase difference detection circuit  34 , the second LPF  35 , and limiter amps  83  and  84 . The CR phase shifter  31 , the phase difference detection circuit  34 , and the second LPF  35  have the same configuration as the phase shifter  22  of FIG.  6 . Accordingly, the phase shifters  22   a  to  22   d ,  41 ,  51 ,  51   a ,  61 ,  71 , and  71   a  may also be used instead of the phase shifter  22 . 
     The first and second limiter amps  83  and  84  receive signals generated by the CR phase shifter and amplify the signals at a predetermined upper limit amplitude and a predetermined lower limit amplitude. The first and second limiter amps  83  and  84  allow the first and second carrier signals LO 0  and LO 2  having substantially the same amplitude to be supplied to the phase difference detection circuit  34 . The phase difference detection circuit  34  supplies the control signal S 1  based on the phase difference of the first and second carrier signals LO 0  and LO 2  to the CR phase shifter  31  via the LPF  35 . 
     In the sixth embodiment, the quadrature modulator  81  modulates the first and second base band signals I and Q at the same amplitude by providing the first and second limiter amps  83  and  84  that generate the first and second carrier signals LO 1  and LO 2  having the same amplitude. 
     (Seventh Embodiment) 
     FIG. 19 is a schematic block circuit diagram of an image suppression mixer (hereinafter referred to as mixer circuit)  221  according to a seventh embodiment of the present invention. The mixer circuit  221  includes first and second phase shifters  212  and  213 , third and fourth phase shifters  222  and  223 , first and second phase difference detection circuits  224  and  225 , a differential circuit  226 , and the image suppression circuit  214  (FIG. 4) all of which are preferably formed on a single semiconductor substrate. The image suppression circuit  214  includes the first and second mixers  215  and  216  and the adder  217 . 
     The first phase shifter  212  is preferably a phase shifter according to the flip-flop method. A phase shifter that complies with the CR method may also be used instead of the flip-flop method. The first phase shifter  212  receives an intermediate frequency signal IFin and generates the first intermediate frequency signal IF 0  having the same phase as the intermediate frequency signal IFin and the second intermediate frequency signal IF 90  having a phase of +90 degrees against the first intermediate frequency signal IF 0 . 
     The second phase shifter  213  is preferably a phase shifter according to the flip-flop method. A phase shifter according to the CR method may also be used. The second phase shifter  213  receives the local signal LOin and generates the first local signal LO 0  having the same phase as the local signal LOin and the second local signal LO- 90  having a phase of −90 degrees against the first local signal LO 0 . 
     The third phase shifter  222  receives the second intermediate frequency signal IF 90  from the first phase shifter  212  and shifts the phase of the second intermediate frequency signal IF 90  to the extent of a predetermined amount in accordance with a first control signal CS 3  from the differential circuit  226 . In other words, the amount of the shift in the phase of the second intermediate frequency signal IF 90  is determined by the first control signal CS 3 . 
     The fourth phase shifter  223  receives the second local signal LO- 90  from the second phase shifter  213  and shifts the phase of the second local signal LO- 90  to the extent of a predetermined amount in accordance with a second control signal CS 4  from the differential circuit  226 . In other words, the amount of the shift in the phase of the second local signal LO- 90  is determined by the second control signal CS 4 . 
     The first phase difference detection circuit  224  is preferably a frequency mixer (frequency converter). The first phase difference detection circuit  224  receives the first intermediate frequency signal IF 0  from the first shifter  212  and the second intermediate frequency signal IF 90  from the third phase shifter  222  and detects the phase difference between the signals IF 0  and IF 90  to generate a first detection signal CS 1  having a DC component according to the detected phase difference. 
     The second phase difference detection circuit  225  is preferably a frequency mixer (frequency converter). The second phase difference detection circuit  225  receives the first local signal LO 0  from the second phase shifter  213  and the second local signal LO- 90  from the fourth phase shifter  223  and detects the phase difference between the signals LO 0  and LO- 90  to generate the second detection signal CS 2  having a DC component according to the detected phase difference. 
     The differential circuit  226  receives the first and second detection signals CS 1  and CS 2  from the first and second phase difference detection circuits  224  and  225  and calculates the difference between the first and second detection signals CS 1  and CS 2 . The differential circuit  226  generates the first and second control signals CS 3  and CS 4  for reducing the differences of the first and second detection signals. The second control signal CS 4  is an inverse of the first control signal CS 3 . Accordingly, the phase difference of the first and second local signals LO 0  and LO- 90  is compensated for by shifting the phase of the second intermediate frequency signal IF 90  in accordance with the first control signal CS 3  by the third phase shifter  222 . In the same manner, the phase differences of the first and second intermediate frequency signals IF 0  and IF 90  are compensated for by shifting the phase of the second local signal LO- 90  in accordance with the second control CS 4  by the fourth phase shifter  223 . Thus, the phase difference between the first and second intermediate frequency signals IF 0  and IF 90  and the phase difference between the first and second local signals LO 0  and LO- 90  are maintained at 90 degrees and effects due to uneven manufacturing in the first and second phase shifters  212  and  213  are reduced. The areas of the circuits  222  to  226  are smaller than the area of the conventional circuit used increase the phase difference accuracy of the output signals of the first and second phase shifters  212  and  213 . Accordingly, increase of the circuit area is prevented. Further, since the mixer circuit  221  does not require a coupler, it can be integrated on a single semiconductor substrate. 
     The first mixer  215  receives the first intermediate frequency signal IF 0  from the first phase shifter  212  and the local signal LO 0  from the third phase shifter  213  and generates a first modulation signal V 1  by mixing the intermediate frequency signal IF 0  and the first local signal LO 0 . 
     The second mixer  216  receives the second intermediate frequency signal IF 90  from the third phase shifter  222  and the second local signal LO- 90  from the fourth phase shifter  223  and generates a second modulation signal V 2  by mixing the second intermediate frequency signal IF 90  and the second local signal LO- 90 . 
     The adder  217  receives the first and second modulation signals V 1  and V 2  from the first and second mixers  215  and  216  and generates the output signal RFout by adding the first and second modulation signals V 1  and V 2 . 
     FIG. 22 is a circuit diagram of the third phase shifter  222 . Since the fourth phase shifter  223  preferably has the same configuration as the third phase shifter  222 , an illustration and detailed description thereof are omitted. The third phase shifter  222  includes a low pass filter (LPF)  231  and a capacitor C 211 . The LPF  231  is an integrating circuit that includes a resistor R 211  and an NPN transistor Tr 211  as a variable element (variable-capacitance element). The first terminal of the resistor R 211  is connected to an input terminal that receives the input signal IN of the third phase shifter  222 , and the second terminal of the resistor R 211  is connected to the emitter of the transistor Tr 211 . Alternatively, the capacitance element may also be connected in parallel to the transistor Tr 211 . 
     The collector of the transistor Tr 211  is connected to the low potential power supply VSS, and the base of the transistor Tr 211  is connected to its own connector. This allows the transistor Tr 211  to have a junction capacitance CJ of the pn junction between the base and emitter. The junction capacitance CJ corresponds to the difference in voltage between the voltage of the low potential power supply VSS and the voltage of a node N 11  between the transistor Tr 211  and the resistor R 211 . Accordingly, the junction capacitance of the transistor Tr 211  is determined depending on the voltages of the input signal IN and the first control signal CS 3 . The LPF  231  receives the second intermediate frequency signal IF 90 , changes the cutoff frequency that is determined depending on the resistance of the resistor R 211  and the junction capacitance of the transistor Tr 211  in accordance with the voltage of the first control signal CS 3 , and shifts the phase of the second intermediate frequency signal IF 90 . In other words, the cutoff frequency is changed by changing the junction capacitance of the transistor Tr 211  in accordance with the voltage of the first control signal CS 3 . Accordingly, the amount of shift of the phase of the second intermediate frequency signal IF 90  is determined depending on the voltage of the first control signal CS 3 . 
     The capacitor C 211  prevents the first control signal CS 3  from being included in the second intermediate frequency signal IF 90 . In other words, the capacitor C 211  allows the second intermediate frequency signal IF 90  having only the AC component to pass through by AC coupling and interrupts the DC control signal CS 2 . 
     FIG. 20 is a circuit diagram of the first phase difference detection circuit  224 . Since the second phase difference detection circuit  225  preferably has the same configuration as the first phase difference detection circuit  224 , a drawing and detailed description thereof are omitted. 
     The first phase difference detection circuit  224  includes a double balanced mixer (DBM) and a low pass filter (LPF)  234 . The double balanced mixer comprises NPN transistors Tr 221  to Tr 226 , resistors R 221  to R 227 , capacitors C 221  and C 222 , constant current sources  232  and  233 , and reference power supplies E 1  and E 2 . 
     The first and second transistors Tr 221  and Tr 222  have their emitters connected together and form a first differential amplifier  235 . The collectors of the first and second transistors Tr 221  and Tr 222  are connected to the high potential power supply Vcc via the resistors R 221  and R 222 . The bases of the first and second transistors Tr 221  and Tr 222  are connected to the first reference power supply E 1 , which generates a first bias voltage VBB 1 , via the resistors  223  and R 224 . The first local signal LO 1  is supplied to the base of the first transistor Tr 221 . The base of the second transistor Tr 222  is connected to the low potential power supply VSS via the capacitor C 221 . 
     The third and fourth transistors Tr 223  and Tr 224  have their emitters connected together and form a second differential amplifier  236 . The collectors of the third and fourth transistors Tr 223  and Tr 224  are connected to the high potential power supply Vcc via the resistors R 221  and R 222 . The bases of the third and fourth transistors Tr 223  and Tr 224  receive the first bias voltage VBB 1  via the resistors R 223  and R 224 . The base of the third transistor Tr 223  is connected to the low potential power supply VSS via the capacitor C 221 . The base of the fourth transistor Tr 224  receives the first local signal LO 0 . 
     The fifth and sixth transistors Tr 225  and Tr 226  have their emitters connected together via the resistor R 225  and form a third differential amplifier  237 . The emitters of the fifth and sixth transistors Tr 225  and Tr 226  are connected to the low potential power supply VSS via the constant current sources  232  and  233 . 
     The collector of the fifth transistor Tr 225  is connected to the emitters of the first and second transistors Tr 221  and Tr 222 . The collector of the sixth transistor Tr 226  is connected to the emitters of the third and fourth transistors Tr 223  and Tr 224 . The bases of the fifth and sixth transistors Tr 225  and Tr 226  receive a second bias power supply VBB 2  via the resistors R 225  and R 226 . The base of the fifth transistor Tr 225  further receives the second local signal LO 2 . The base of the sixth transistor Tr 226  is connected to the low potential power supply VSS via the capacitor C 222 . 
     The node N 21  between the second transistor Tr 222  and the second resistor R 222  is connected to the LPF  234 . The LPF  234  is an integrating circuit that includes the resistor R 228  and the capacitor C 223  connected in series. The first terminal of the resistor R 228  is connected to the node N 21  and the second terminal of the resistor R 228  is connected to the first terminal of the capacitor C 223 . The second terminal of the capacitor C 228  is connected to the low potential power supply VSS. 
     The LPF  234  outputs a first detection signal CS 1  from the node N 21  between the resistor R 228  and the capacitor C 223 . The first detection signal CS 1  is generated by smoothing the voltage of the node N 21  and has a DC component. 
     The signal S (N 21 ) at the node N 21  of the phase difference detection circuit  224  is obtained in accordance with the following equation (6).                S        (   N21   )       =       cos        (       2      π                   f   IN        t     +     φ      1       )       ×     cos        (       2      π                   f   IN        t     +     φ      2       )                     =       1   2          [       cos        {       2        π        (     2        f   IN       )          t     +     φ      1     +     φ      2       }       +     cos        (       φ      1     -     φ      2       )         ]                                    
     The LPF  234  removes the high frequency component (first term of Equation (6)) of the signal S (N 21 ). The first detection signal CS 1  includes the DC component ({cos(φ1−φ2)}/2) of the signal of the node N 21 . This DC component corresponds to the phase differences of the first and second intermediate frequency signals IF 0  and IF 90 . 
     FIG. 21 is a circuit diagram of the differential circuit  226 . The differential circuit  226  includes NPN transistors Tr 231  and Tr 232 , resistors R 231  and R 232 , and a constant current source  238 . 
     The first and second transistors Tr 231  and Tr 232  have their emitters connected together and form a differential amplifier  239 . The emitters of the first and second transistors Tr 231  and Tr 232  are also connected to the low potential power supply VSS via the constant current source  238 . The collectors of the first and second transistors Tr 231  and Tr 232  are connected to the high potential power supply Vcc via the resistors R 221  and R 222 . The base of the first transistor Tr 231  receives the first detection signal CS 1  and the base of the second transistor Tr 232  receives the second detection signal CS 2 . 
     The differential circuit  226  outputs the first control signal CS 3  from the node N 31  (first output terminal) between the resistor R 231  and the transistor Tr 231 . The differential circuit  226  further outputs the second control signal CS 4  that is an inverse signal of the first control signal CS 3  from the node N 32  (second output terminal) between the resistor R 232  and the transistor Tr 232 . 
     When the first and second phase shifters  212  and  213  have no uneven manufacturing and generate the output signal having a phase difference of substantially 90 degrees, it is preferable that the first and second bias voltages VBB 1  and VBB 2  of the phase difference detection circuits  224  and  225  and the voltages of the first and second control signals CS 3  and CS 4  correspond to one another. Thus, the first and second intermediate frequency signals IF 0  and IF 90  and the first and second local signals LO 0  and LO- 90  having an accurate phase difference of 90 degrees are obtained by a feedback loop including the first and second phase difference detection circuits  224  and  225 , the differential circuit  226 , and the third and fourth phase shifters  222  and  223 . 
     Next, the operation of the mixer circuit  221  is described. In this example, the phase difference of the first and second intermediate signals IF 0  and IF 90  is 93 degrees and the phase difference of the first and second local signals LO 0  and LO- 90  is −88 degrees. 
     The first phase difference detection circuit  224  outputs the first detection signal CS 1  of the phase difference of the first and second intermediate frequency signals IF 0  and IF 90 . The second phase difference detection circuit  225  outputs the second detection signal CS 2  of the phase difference between the first and second local signals LO 0  and LO- 90 . The differential circuit  226  outputs the first and second control signals CS 3  and CS 4  in accordance with the first and second detection signals CS 1  and CS 2 . 
     The third phase shifter  222  shifts the phase of the second intermediate frequency signal IF 90  in accordance with the first control signal CS 3  so that the phase difference between the first and second intermediate frequency signals IF 0  and IF 90  is 90 degrees. The fourth phase shifter  223  shifts the phase of the second local signal LO- 90  in accordance with the second control signal CS 4  so that the phase difference of the first and second local signals LO 0  and LO- 90  is 90 degrees. 
     The image suppression circuit  214  receives the first and second intermediate frequency signals IF 0  and IF 90  and the first and second local signals LO 0  and LO- 90  and outputs the modulation output signal RFout. 
     When the mixer circuit  221  is used as a down-converter, the first phase shifter  212  receives the high frequency input signal RFin. The input signal RFin may be a signal received by a communication device. The mixer circuit  11  outputs the output signal IFout having a lower intermediate frequency than the input signal RFin by mixing the input signal RFin and the local signal LOin having a local oscillation frequency. 
     FIG. 23 is a block diagram of a mixer circuit  241  in a first modification example of the mixer circuit  221  of FIG.  19 . The mixer circuit  241  comprises the third phase shifter  222  connected between the first phase shifter  212  and the first phase difference detection circuit  224 , but does not include the fourth phase shifter  223 . In this case, the differential circuit  226  supplies the first control signal CS 1  to the third phase shifter  222 . Even with this configuration, effects due to uneven manufacturing of the first and second phase shifters  212  and  213  are reduced by the third phase shifter  222 . Specifically, when the phase difference of the first and second intermediate frequency signals IF 0  and IF 90  is 93 degrees and the phase difference of the first and second local signals LO 0  and LO- 90  is −88 degrees, the phase of the second intermediate frequency signal IF 90  for the phase of the first intermediate frequency signal IF 0  is corrected to 92 degrees by the third phase shifter  222 . This correction allows the phase difference of the first and second local signals LO 0  and LO- 90  to be canceled. 
     FIG. 24 is a block diagram of a mixer circuit  251  in a second modification example. The mixer circuit  251  comprises the phase shifter  223  connected between the second phase shifter  213  and the second phase difference detection circuit  225 . For example, when the phase difference of the first and second intermediate frequency signals IF 0  and IF 90  is 93 degrees and the phase difference of the first and second local signals LO 0  and LO- 90  is −88 degrees, the phase of the second local signal LO- 90  for the phase of the first local signal LO 0  is corrected to −87 degrees by the phase shifter  223 . This correction allows the phase difference of the first and second intermediate frequency signals IF 0  and IF 90  to be canceled. 
     As another modification example, a phase shifter may also be provided so that the phase of the first intermediate frequency signal IF 0  and the phase of the first local signal IF 0  are shifted. 
     (Eighth Embodiment) 
     FIG. 25 is a block diagram of a mixer circuit  261  according to an eighth embodiment of the present invention. The mixer circuit  261  is similar to the mixer circuit  222  (FIG. 19) and further comprises first to fourth limiter amps  262  to  265 . 
     The first amp  222  is connected between the first phase shifter  212  and the first mixer  215  and receives the first intermediate frequency signal IF 0  from the first phase shifter  212  to generate the amplified first intermediate frequency signal IF 0  having the predetermined amplitude. 
     The second amp  263  is connected between the third phase shifter  222  and the second mixer  216  and receives the second intermediate frequency signal IF 90  from the third phase shifter  222  to generate the amplified second intermediate frequency signal IF 90  having the predetermined amplitude. 
     The third amp  264  is connected between the second phase shifter  213  and the first mixer  215  and receives the first local signal LO 0  from the second phase shifter  213  to generate the amplified first local signal LO 0  having the predetermined amplitude. 
     The fourth amp  265  is connected between the fourth phase shifter  223  and the second mixer  216  and receives the second local signal LO- 90  from the fourth phase shifter  223  to generate the amplified second local signal LO- 90  having the predetermined amplitude. 
     The first and second intermediate frequency signals IF 0  and IF 90  having the same amplitude are obtained by the first and second amps  262  and  263 , and the first and second local signals LO 0  and LO- 90  having the same amplitude are obtained by the third and fourth amps  264  and  265 . Accordingly, the image suppression circuit  214  performs accurate and sure image suppression. 
     FIG. 26 is a block diagram of a mixer circuit  271  in a first modification example of the mixer circuit  261 . The mixer circuit  271  includes the first amp  262  connected between the first phase shifter  212  and the first mixer  215  and the second amp  263  connected between the third phase shifter  222  and the second mixer  216 . 
     FIG. 27 is a block diagram of a mixer circuit  281  in a second modification example of the mixer circuit  261 . The mixer circuit  281  includes the first amp  264  connected between the second phase shifter  213  and the first mixer  215  and the second amp  265  connected between the fourth phase shifter  223  and the second mixer  216 . 
     (Ninth Embodiment) 
     FIG. 28 is a block circuit diagram of an image suppression mixer  291  according to a ninth embodiment of the present invention. The mixer circuit  291  includes first and second phase shifters  292  and  293 , the first and second phase difference detection circuits  224  and  225 , the differential circuit  226 , and the image suppression circuit  214 . 
     The first phase shifter  292  is preferably a phase shifter according to the CR method. The first phase shifter  292  receives the intermediate frequency signal IFin and generates the first intermediate frequency signal IF 0  having the same phase as the intermediate frequency signal IFin and the second intermediate frequency signal IF 90  having a phase of +90 degrees from the first intermediate frequency signal IF 0 . The first phase shifter  292  further receives the first control signal CS 3  from the differential circuit  226  and shifts the phase of the second intermediate frequency signal IF 90  in accordance with the first control signal CS 3 . 
     The second phase shifter  293  is also preferably a phase shifter according to the CR method. The second phase shifter  293  receives the local signal LOin and generates the first local signal LO 0  having the same phase as the local signal LOin and the second local signal LO- 90  having a phase of −90 degrees from the first local signal LO 0 . The second phase shifter  293  further receives the second control signal CS 4  from the differential circuit  226  and shifts the phase of the second local signal LO- 90  in accordance with the second control signal CS 4 . 
     FIG. 29 is a circuit diagram of the first phase shifter  292 . The first phase shifter  292  includes the low pass filter (LPF)  231 , a high pass filter (HPF)  294 , and the capacitors C 211  and C 242 . The HPF  294  is a differential circuit that includes a capacitor C 241  and a resistor R 241  connected in series between the low potential power supply Vss and the input terminal of the first phase shifter  292 . The HPF  294  outputs the first intermediate frequency signal IF 0  from a node N 41  (output terminal) between the capacitor C 241  and the resistor R 241 . 
     Since the phase of the second intermediate frequency signal IF 90  and the phase of the second local signal LO- 90  are shifted by the first and second phase shifters  292  and  293 , the circuit area of the mixer circuit  291  is reduced. 
     As a modification, the mixer circuit  291  may also comprise the first to fourth amps  262  to  265  as shown in FIG.  25 . Further, as shown in FIG. 26 or FIG. 27, an amp may also be provided for either of the intermediate frequency signal and the local signal. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many specific forms without departing from the sprit or scope of the invention. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.