Abstract:
A driver circuit comprises a driver portion, differential voltage input terminals, feedback circuitry, and differential voltage output terminals. The feedback circuitry connects a sample portion of the driver portion to a mixer portion of the driver portion. The sample portion may comprise an internal connection to the driver portion, for example, at a midpoint between differential outputs by the driver portion before regulation of the same differential voltages.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     N/A  
       STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     N/A  
       BACKGROUND OF THE INVENTION  
       [0003]     The present invention is related to systems involved in high speed data transmission. In some aspects, the invention is related to low voltage differential signaling (LVDS) systems, including fully differential multi-channel repeaters, and drivers therefor.  
         [0004]     LVDS is becoming a common choice for high speed data transmission. In many cases, high speed data transmission systems use fully differential multi-channel LVDS repeaters. These repeaters are presented with challenging requirements for both skew and speed, similar to the requirements presented to a clock distribution network. These devices are capable of high speed data transmission, yet they may still encounter difficulties if they become subject to capacitive loads much higher than a typical AC load.  
         [0005]      FIG. 1  is a block diagram illustrating a common fully differential LVDS repeater  10 . Repeater  10  comprises a receiver  14  connected to a driver  16 . Receiver  14  senses an input signal V in  and drives the driver  16 , which produces a differential output voltage V out  across a resistive load R load .  
         [0006]      FIG. 2  is a schematic diagram of a background driver circuit  20  of a fully differential LVDS repeater  10  as shown in  FIG. 1 . In the illustrated circuit  20 , a differential amplifier  22  is provided which comprises input terminals A and B for receiving an input voltage V in ′. The illustrated differential amplifier  22  comprises a symmetrical emitter-coupled differential amplifier, comprising a first transistor Q 8  (an NPN bipolar junction transistor in the illustrated embodiment) and a second transistor element Q 7  (also an NPN bipolar junction transistor).  
         [0007]     The collectors of the first and second transistor elements Q 8  and Q 7  are connected to respective pull-up resistors R 6  and R 7 . Pull-up resistors R 6  and R 7  are connected at their opposite ends to a common drain of a third transistor element MP 2 . In the illustrated embodiment, third transistor element MP 2  comprises a p-type MOSFET transistor. The source of third transistor element MP 2  is connected to a reference voltage Vcc. In the illustrated circuit, third transistor element MP 2  serves as a comparator or mixer input for a feedback loop of the illustrated driver.  
         [0008]     The respective outputs of differential amplifier  22  are connected to the bases of fourth and fifth transistor elements Q 5  and Q 6 . Fourth and fifth transistor elements Q 5  and Q 6  serve as voltage drivers  30  and  32 , for common mode regulation. The resulting differentially amplified output signal V out , is across these Z and Y terminals. The output signal is sampled at the common node  34  of resistors R 4  and R 5 , by a sixth transistor element MN 1 .  
         [0009]     A first constant current source  24  is connected between the common emitter coupling of differential amplifier  22  and ground via a resistor R 0 . A second constant current source  26  is connected between the first output terminal Z and ground via a resistor R 2 . A third constant current source  28  is connected between the second output terminal Y and ground via a resistor R 3 . Each of the constant current sources  24 ,  26 , and  28  comprises an NPN bipolar junction transistor configured as a common-emitter, comprising an input direct current bias voltage Vbbias coupled to the base of each transistor element.  
         [0010]     Output resistors R 4  and R 5  are connected in series across output terminals Z and Y. The common connection between output resistors R 4  and R 5  may be referred to as a sampling node  34 . Feedback circuitry  40  is provided, coupled between sampling node  34 , which serves as a feedback sensing point, and a mixing point  36 , which is a common connection between pull up resistors R 6  and R 7  of differential amplifier  22 . In the illustrated embodiment, feedback circuitry  40  comprises a resistor R 8  and capacitor C 8  connected in series between sampling node  34  and ground, and further comprises a number of transistor elements MN 0 , MN 1 , MN 2 , MP 0 , MP 1 , and MP 2 . In the illustrated circuit, transistor elements MN 1 , MN 0 , and MN 2  comprise n-type MOSFET transistors, and transistor elements MP 0 , MP 1 , and MP 2  comprise p-type MOSFET transistors.  
         [0011]     When the driver illustrated in  FIG. 2  is loaded with a single ended capacitance from either output node Z or Y to ground in excess of 10 pF, the illustrated driver&#39;s output common mode feedback may become unstable. The illustrated common feedback loop  40  will have essentially two dominant poles, one between MP 1  and MN 2 , and the other between MP 2  and resistors R 6  and R 7 . For circuit stability, it is desirable that the poles from the output followers Q 5  and Q 6  are high enough in the frequency domain, so that they do not interact with the noted pair of dominant poles. This only holds true if the capacitance of the driver load is relatively low.  
         [0012]     As the load capacitance is increased, the available bandwidth of the followers Q 5  and Q 6  will be reduced, bringing the poles of those followers closer in frequency so that they interact with the poles of MP 1  and MP 2 . This can create problems in certain applications, where the capacitance at the output can be difficult to predict.  
         [0013]      FIG. 3  shows waveforms representing the magnitude and phase of the closed loop AC voltage response at output sample node  34  of the circuit shown in  FIG. 2 . The illustrated waveforms show excessive peaking when a 50 pF capacitor is tied between one of the outputs Z and Y of the illustrated circuit and ground. The upper waveform in  FIG. 3  illustrates the magnitude in dBs in relation to frequency. The lower waveform shows the phase in degrees in relation to frequency.  
       SUMMARY OF THE INVENTION  
       [0014]     There is a need for improved common mode feedback approaches in high speed differential outputs circuits, such as drivers used in low voltage differential signaling (LVDS) systems. For example, a driver for an LVDS repeater may become unstable when its load capacitance increases beyond a given level. To alleviate this problem, the sensing point for the driver&#39;s feedback loop is moved to a point internal to the driver circuitry.  
         [0015]     In accordance with one embodiment of the present invention, a driver circuit is provided for an LVDS repeater. The driver comprises differential voltage input terminals, a driver portion to produce initial differential output voltages, and differential voltage output terminals. The driver portion comprises a differential amplifier. Feedback circuitry connects a sample portion of the driver portion to a mixer portion of the driver portion. The sample portion comprises a connection at a midpoint between the initial differential output of the driver portion. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The invention will be more fully understood with reference to the following Detailed Description of the Invention in conjunction with the drawings, of which:  
         [0017]      FIG. 1  is a block diagram of a background low voltage differential signaling (LVDS) repeater;  
         [0018]      FIG. 2  is a schematic diagram of a background driver circuit;  
         [0019]      FIG. 3  shows waveforms representing the closed loop AC response of the feedback loop of the circuit shown in  FIG. 2 ;  
         [0020]      FIG. 4  is a schematic diagram of a driver circuit in accordance with one embodiment of the invention;  
         [0021]      FIG. 5  shows waveforms representing the closed loop AC response of the feedback loop of the circuit shown in  FIG. 4 ; and  
         [0022]      FIG. 6  is a schematic diagram of a driver circuit in accordance with another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0023]      FIG. 4  is a schematic diagram of a driver circuit  50  in accordance with one embodiment of the present invention. In the illustrated driver circuit  50 , various elements of the circuit with the same alphanumeric references are the same as the corresponding elements shown in the circuit of  FIG. 2 , except as follows. Sampling string resistive elements R 4 ′ and R 5 ′ are now connected across the collectors of the first and second transistor elements of the differential amplifier  22 ′. A sampling node  34 ′ is formed between the connections of the sampling string of resistive elements R 4 ′ and R 5 ′. The resistor and capacitor R 8  and C 8  are now coupled between the relocated sampling node  34 ′ and ground. The base of an additional transistor element Q 4  is connected to sampling node  34 ′. Its collector is connected to the reference voltage Vcc, and its emitter is connected to an additional constant current source  29 . Additional constant current source  29  comprises a transistor element Q 1 , the base of which is connected to the bias DC voltage Vbbias. The collector of transistor Q 1  is connected to the emitter of transistor Q 4 . The emitter of transistor Q 1  is connected to a resistor R 1 , the other end of which is connected to ground. The connection between the emitter of transistor Q 4  and the collector of transistor Q 1  is the output node  61 , which is connected to the drain of the first transistor element MN 1  of the feedback circuitry  60 .  
         [0024]     Feedback circuitry  60  is substantially the same as feedback circuitry  40  in the circuit illustrated in  FIG. 2 . Specifically, it comprises MOSFETs MN 0 , MN 1 , MN 2 , MP 0 , MP 1 , and MP 2 . Transistors MN 0 , MN 1 , and MN 2  comprise n type MOSFETs. Transistors MP 0 , MP 1 , and MP 2  comprise p type MOSFETs. As is the case in the circuit illustrated in  FIG. 2 , the drain of the first transistor MN 0  of the feedback circuitry is connected to a DC bias voltage vnbias. The drain of a second transistor element of the illustrated feedback circuitry MN 2  is connected to a band gap reference voltage. In the illustrated embodiment, the band gap reference voltage Vbg is equal to 1.2V.  
         [0025]     In the driver circuit  50  shown in  FIG. 4 , feedback circuitry  60  serves as a common mode feedback loop. The sensing point of the loop originates at sampling node  34 ′ resulting in a feedback voltage voc input to transistor element MN 1 . This movement of the sensing point to a position internal to the driver greatly improves the stability of the output voltage across terminals Z and Y. When large capacitances are applied between those output terminals and ground, the output feedback response remains essentially the same. This is demonstrated in the waveforms shown in  FIG. 5 , which represent the magnitude and phase of the voltage at output node  61  in relation to frequency.  
         [0026]     For better performance in common mode regulation, it is beneficial to have transistor Q 4  with the same current density as that of transistor elements Q 5  and Q 6 , so the voltage from the base to the emitter of each of these transistor elements (Vbe) will better track over a PVT (performance verification test).  
         [0027]     Switching performance will be improved if the driver sampling string resistors R 4  and R 5  are carefully chosen so as to minimize any parasitic capacitance effect caused thereby. Accordingly, a modified driver circuit may be provided, as shown in  FIG. 6 .  FIG. 6  is a schematic diagram of a driver circuit  70 , comprising feedback circuitry  80 . Each of the elements of the circuit shown in  FIG. 6  are as shown and described above in the circuit of  FIG. 4 , with the exception of the following. Specifically, driver circuit  70  of  FIG. 6  includes an additional pull-up resistor R 9 , a drive transistor element Q 9 , a constant current source transistor element Q 10 , and a resistor element R 10 . Transistor Q 9  is connected at its collector to resistor R 9 , and at its emitter to transistor Q 10 . The base of transistor Q 9  is connected to sampling node  34 ″. The sampling node  34 ″ is formed at the intersection of resistors R 4  and R 5  which are across the input nodes A and B of differential amplifier  22 ″.  
         [0028]     The value of resistor R 9  is equal to the value of resistor R 7 , which is equal to the value of resistor R 6 . The collector current of transistor Q 10  is half the collector current of transistor Q 0 . This provides for good tracking and matching over PVT. This implementation also results in a reduced slowdown of the output driver switching speed.  
         [0029]     It will also be appreciated by those of ordinary skill in the art that modifications to and variations of the above-described system and method may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except as by the scope and spirit of the appended claims.