Abstract:
PLL integrated circuits include a charge pump having first and second input terminals that are configured to receive UP and DOWN control signals, respectively. A phase detector is also provided. The phase detector is configured to generate the UP and DOWN control signals at active levels during a dead zone compensation time interval using a control circuit that is responsive to at least one signal generated by the charge pump. The control circuit is further configured to support reference clock signal and/or feedback clock signal updates to the phase detector during the dead zone compensation time interval.

Description:
REFERENCE TO PRIORITY APPLICATION 
   This application claims priority to Korean Application Ser. No. 2003-15864, filed Mar. 13, 2003, the disclosure of which is hereby incorporated herein by reference. 
   FIELD OF THE INVENTION 
   The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices that utilize phase detectors when generating periodic signals. 
   BACKGROUND OF THE INVENTION 
   Phase-locked loop (PLL) integrated circuits are frequently used to generate highly accurate internal clock signals on an integrated circuit substrate. As illustrated by  FIG. 1 , a conventional PLL integrated circuit  10  may include a phase detector  12 , a charge pump  14 , a loop filter  16 , a voltage controlled oscillator (VCO)  18 , a clock decoder and buffer  20 , and a frequency divider  22 . The phase detector  12  may be configured to generate UP and DOWN control signals in response to a reference clock signal (CKREF) and a feedback clock signal (CKVCO). In particular, the phase detector  12  may be configured to compare the phases of the clock signals and generate an active UP signal or an active DOWN signal when the feedback clock signal CKVCO lags or leads the reference clock signal CKREF. As will be understood by those skilled in the art, the reference clock signal (CKREF) may be a buffered version of an external clock signal (not shown) that is received by an integrated circuit chip. The charge pump  14  may be operative to convert the digitally encoded UP and DOWN control signals into an analog output (POUT) that sources current to or sinks current from the loop filter  16 . The loop filter  16  is illustrated as generating a control voltage (Vcontrol), which is provided as an input to the VCO  18 . The VCO  18  may generate a plurality of outputs, which are provided to the clock decoder and buffer  20 . One of the outputs of the clock decoder and buffer  20  (shown as clock signal φ 1 ) may be provided as an input to the frequency divider  22 , which generates the feedback clock signal CKVCO. An active UP signal operates to increase the value of Vcontrol, which speeds up the VCO  18  and causes the feedback clock signal CKVCO to catch up with the reference clock signal CKREF. On the other hand, an active DOWN signal slows down the VCO  18  and eliminates the phase lead of the feedback clock signal CKVCO. These and other aspects of the PLL  10  of  FIG. 1  are more fully illustrated and described at section 9.5.2 of a textbook by Jan M. Rabaey, entitled Digital Integrated Circuits: A Design Perspective, Prentice-Hall, ISBN 0-13-178609-1, pp. 540-542. 
     FIG. 2  illustrates a conventional charge pump  14  having both pull-up and pull-down sections. The pull-up section includes an NMOS pull-down transistor N 1  in series with a resistor R 1 . A pull-up current mirror is provided by PMOS transistors P 1  and P 2 . The NMOS pull-down transistor N 1  is responsive to the UP control signal. When the UP control signal is active at a logic 1 level, the NMOS pull-down transistor N 1  turns on and pulls-down the drain and gate of PMOS transistor P 1 . The feedback signal line NMOS_ON is also switched high-to-low. This causes both PMOS transistors P 1  and P 2  to turn on and provide a sourcing current (I source ) to the output terminal (POUT) of the charge pump  14 . The pull-down section includes a PMOS pull-up transistor P 3  in series with a resistor R 2 . A pull-down current mirror is provided by NMOS transistors N 2  and N 3 . The gate of the PMOS pull-up transistor P 3  is connected to an output of an inverter I 1 , which receives the DOWN control signal. When the DOWN control signal is active at a logic 1 level, the PMOS pull-up transistor P 3  turns on and pulls-up the drain and gate of NMOS transistor N 2 . The feedback signal line PMOS_ON is also switched low-to-high. This causes both NMOS transistors N 2  and N 3  to turn on and withdraw a sinking current (I sink ) from the output terminal POUT. When the control signals UP and DOWN are both active at logic 1 levels, the pull-up and pull-down sections are simultaneously active. The pull-up and pull-down sections of the charge pump may be balanced so that I source  equals I sink  and no net current is provided to or withdrawn from the output terminal POUT. A similar charge pump is illustrated at  FIG. 4  of commonly assigned U.S. Pat. No. 6,430,244 to Rhu, entitled “Digital Phase-Locked Loop Apparatus With Enhanced Phase Error Compensating Circuit,” the disclosure of which is hereby incorporated by reference. 
     FIG. 3A  illustrates a conventional phase detector  12  that utilizes a delay device D 1  to provide a dead zone compensation time interval during which both the UP and DOWN control signals are temporarily active. Maintaining the UP and DOWN control signals at active levels during an overlapping time interval prevents a “dead zone” from occurring when the phases of the reference clock signal CKREF and the feedback clock signal CKVCO are so closely aligned that the generation of any active UP control signal would otherwise be immediately canceled by the generation of any active DOWN control signal and vice versa. As described in U.S. Pat. No. 4,322,643 to Prescar and U.S. Pat. No. 6,192,094 to Herrmann et al., and in an article by X. Zhang entitled “Analysis and Verification on Side Effect of Anti-Backlash Delay in Phase-Frequency Detector,” Microwave Theory and Techniques Society (MTT-S) Digest, IEEE International Microwave Symposium, pp. 17-20, Jun. 8-13, 2003, the delay device D 1  may also be referred to as an “anti-backlash” delay unit. The phase detector  12  is illustrated as including a pair of D-type flip-flops (DFF 1  and DFF 2 ), a NAND gate ND 1 , an inverter I 2  and a delay device D 1 . The D-type flip-flops are synchronized with the reference and feedback clock signals CKREF and CKVCO. A rising edge of the reference clock signal CKREF will cause the true output Q 1  of DFF 1  to switch high and a rising edge of the feedback clock signal CKVCO will cause the true output Q 2  of DFF 2  to switch high. To prevent dead zone operation, the UP and DOWN control signals remain active whenever a rising edge of the reference clock signal CKREF is registered (by DFF 1 ) while the DOWN control signal is active or whenever a rising edge of the feedback clock signal CKVCO is registered (by DFF 2 ) while the UP control signal is active. Setting the UP and DOWN control signals to logic 1 levels causes the output of the NAND gate ND 1  to switch high-to-low and the output of the inverter I 2  to switch low-to-high. This low-to-high switching at the output of inverter I 2  is delayed by a fixed time amount equal to T 1 , by the delay device D 1 . The delay T 1  may be about 5 nanoseconds in some cases. The reset signal RST at the output of the delay device D 1  will switch low-to-high some time after the output of the inverter I 2  switches low-to-high in response to simultaneously active UP and DOWN control signals. When active, the reset signal RST operates to reset the flip-flops DFF 1  and DFF 2  (Q 1 =Q 2 =0). Upon reset, the UP and DOWN control signals will switch to inactive levels and the output POUT of the charge pump  14  of  FIG. 2  will be disposed in a high impedance state. Operation of the phase detector  12  of  FIG. 3A  will now be described more fully with respect to  FIGS. 3B-3C . 
   In  FIG. 3B , a first rising edge of the reference clock signal CKREF causes the UP control signal at the true output Q 1  of DFF 1  to switch low-to-high. Following this, a first rising edge of the feedback clock signal CKVCO causes the DOWN control signal at the true output Q 2  of DFF 2  to switch low-to-high. This initial overlap of the active UP and DOWN control signals causes the input of the delay device D 1  to switch high. Then, the reset signal RST switches low-to-high after a time period equal to about T 1  (or equal to T 1  if the delays associated with the logic elements ND 1  and  12  are ignored). This time period T 1  represents the duration of the dead zone compensation time interval during which both of the control signals UP and DOWN remain at active levels to prevent dead zone operation when the phases of the CKREF and CKVCO are closely aligned. In response to the low-to-high transition of the reset signal RST, the true outputs Q 1  and Q 2  are switched high-to-low and the output of inverter I 2  then switches high-to-low. The high-to-low transition at the output of the inverter I 2  is reflected in a high-to-low transition of the reset signal RST after a time period equal to T 1 . Unfortunately, the overlap between the active UP and DOWN control signals (i.e., true outputs Q 1  and Q 2 ) for a duration of about T 1  causes the phase detector  12  of  FIG. 3A  to miss a rising edge of an incoming reference clock signal CKREF during the overlap time period. This missed edge is highlighted in FIG.  3 B. As will be understood by those skilled in the art, this failure to recognize a rising edge of the incoming reference clock signal CKREF can cause gain inversion and reduce the lock time of the phase detector  12 . Gain inversion takes place when the phase detector  12  outputs the wrong control signals and causes the phase differences between the reference clock signal CKREF and feedback clock signal CKVCO to increase rather than decrease. This is reflected in  FIG. 3B  by the failure to maintain an active UP control signal during the time period extending between the first and second rising edges of the feedback clock signal CKVCO. Accordingly, when the second rising edge of the feedback clock signal CKVCO is received, the DOWN control signal becomes active (thereby causing gain inversion) while the UP control signal remains inactive (when it should have been active in response to the missed clock signal update). 
   This gain inversion problem may also occur outside the dead zone compensation time interval. In particular,  FIG. 3C  illustrates how a clock signal update may be missed during the period when the reset signal RST is high and the true outputs Q 1  and Q 2  are held low. Thus, as illustrated by  FIG. 3C , a time interval having a duration of about 2T 1  represents a period during which clock signal updates are not possible within the phase detector of FIG.  3 A. 
   SUMMARY OF THE INVENTION 
   Phase-locked loop (PLL) integrated circuits according to first embodiments of the present invention include a phase detector that is configured to generate overlapping UP and DOWN control signals at active levels during a dead zone compensation time interval. To prevent the occurrence of gain inversion events, a control circuit is provided that supports reference clock signal and feedback clock signal updates to the phase detector during the dead zone compensation time interval. The PLL integrated circuit also includes a charge pump that is configured to receive the UP and DOWN control signals generated by the phase detector. In some embodiments, the control circuit includes a sensor that is electrically coupled to the charge pump. This sensor is configured to generate a dead zone termination signal (END) in response to detecting receipt of overlapping UP and DOWN control signals by the charge pump. In alternative embodiments, the sensor may be configured to generate a dead zone termination signal in response to detecting generation of overlapping UP and DOWN control signals at outputs of the phase detector. 
   PLL integrated circuits according to other embodiments of the invention include a charge pump that is responsive to UP and DOWN control signals and a phase detector that is configured to generate the UP and DOWN control signals at active levels during a dead zone compensation time interval. The phase detector includes a control circuit that supports reference clock signal and/or feedback clock signal updates to the phase detector during the dead zone compensation time interval. The control circuit includes means, responsive to the reference clock signal and the feedback clock signal, for generating a reset signal having a leading edge that triggers a start of the dead zone compensation time interval and a delayed version of the reset signal having a leading edge that triggers termination of the dead zone compensation time interval. 
   According to further embodiments of the present invention, a PLL integrated circuit is provided that includes a charge pump having first and second input terminals that are configured to receive UP and DOWN control signals, respectively, and first and second control terminals that are configured to generate first and second feedback signals (e.g., NMOS_ON and PMOS_ON). These feedback signals indicate when the UP and DOWN control signals are active. A phase detector is provided. This phase detector is configured to generate the UP and DOWN control signals at active levels during a dead zone compensation time interval using a control circuit that is responsive to the first and second feedback signals generated by the charge pump. The control circuit is configured to support reference clock signal and/or feedback clock signal updates to the phase detector during the dead zone compensation time interval. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a conventional phase-locked loop. 
       FIG. 2  is an electrical schematic of a conventional charge pump that may be used in the phase-locked loop of FIG.  1 . 
       FIG. 3A  is an electrical schematic of a conventional phase detector that may be used in the phase-locked loop of FIG.  1 . 
       FIG. 3B  is a timing diagram that illustrates operation of the phase detector of  FIG. 3A  under first timing conditions. 
       FIG. 3C  is a timing diagram that illustrates operation of the phase detector of  FIG. 3A  under second timing conditions. 
       FIG. 4A  is an electrical schematic of a phase detector according to a first embodiment of the present invention. 
       FIG. 4B  is a timing diagram that illustrates operation of the phase detector of FIG.  4 A and the acceptance of clock signal updates during a dead zone compensation time interval. 
       FIG. 5  is an electrical schematic of a phase detector according to a second embodiment of the present invention. 
       FIG. 6  is an electrical schematic of a phase detector according to a third embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters. Signals may also be synchronized and/or undergo minor boolean operations (e.g., inversion) without being considered different signals. The suffix B (or prefix symbol “/”) to a signal name may also denote a complementary data or information signal or an active low control signal, for example. 
   Referring now to  FIG. 4A , a phase detector  40  according to a first embodiment of the present invention includes an input stage that recognizes receipt of leading edges of a pair of clock signals. These clock signals are illustrated as a reference clock signal CKREF and a feedback clock signal CKVCO. Other clock signals may also be provided. This input stage is illustrated as including a pair of D-type flip-flops, shown as DFF 1  and DFF 2 . The true output Q 1  of the first flip-flop DFF 1  is latched high in response to a low-to-high edge of the reference clock signal CKREF. The true output Q 2  of the second flip-flop DFF 2  is latched high in response to a low-to-high edge of the feedback clock signal CKVCO. The true outputs Q 1  and Q 2  of the flip-flops are coupled to a control circuit  42  that provides dead zone compensation and enhanced dead zone operation that precludes gain inversion behavior. An embodiment of this control circuit  42  will now be described. An inverter  13  generates a complementary signal Q 1 B that is provided as an input to a NAND gate ND 2  and an input to a NOR gate NR 1 . An inverter  14  generates a complementary signal Q 2 B that is provided as an input to a NAND gate ND 3  and an input to the NOR gate NR 1 . When the true outputs Q 1  and Q 2  are both set to high levels, the “reset” output RST of the NOR gate NR 1  switches low-to-high and operates to automatically reset both of the flip-flops DFF 1  and DFF 2 . Thus, switching Q 1  low-to-high when Q 2  is already high or switching Q 2  low-to-high when Q 1  is already high will result in an almost immediate reset of both flip-flops DFF 1  and DFF 2 , which means the output of the NOR gate NR 1  generates a logic 1 pulse of relatively short duration. Upon reset, the first flip-flop DFF 1  will be capable of recognizing any subsequent leading edge of the reference clock signal CKREF. Similarly, upon reset, the second flip-flop DFF 2  will be capable of recognizing any subsequent leading edge of the feedback clock signal CKVCO. This “immediate” reset feature, which is described more fully with respect to the timing diagram of  FIG. 4B , enables the control circuit  42  to support the reference clock signal CKREF and feedback clock signal CKVCO updates to the phase detector  40  during a dead zone compensation time interval. By supporting clock signal updates during the dead zone compensation time interval, gain inversion behavior of the type described above with respect to  FIGS. 3A-3B  can be eliminated. 
   Setting the complementary signal Q 1 B low causes the output of the NAND gate ND 2  to switch high and generate an active UP control signal. Similarly, setting the complementary signal Q 2 B low causes the output of the NAND gate ND 3  to switch high and generate an active DOWN control signal. These control signals remain active during a dead zone compensation time interval notwithstanding the “immediate” reset feature. In particular, a latch, provided by inverters I 5  and I 6 , operates to maintain the dead zone compensation time interval after the reset signal line RST is switched high (and then low) in response to the condition that Q 1 =Q 2 =1. The output node X of the latch defined by inverters I 5  and I 6  is pulled low (and held low) by an NMOS transistor N 4  when the reset signal line RST transitions from low-to-high. Accordingly, a leading edge of the reset pulse RST causes the NAND gates ND 2  and ND 3  to continue to generate overlapping UP and DOWN control signals at active levels notwithstanding the fact that the true outputs Q 1  and Q 2  of the flip-flops are reset to logic 0 levels in response to a low-to-high transition of the reset signal line RST. A low-to-high transition of the reset signal line RST is delayed by a delay device D 2  (delay=T 2 ). The output of the delay device D 2  generates a logic 1 pulse (shown as signal END) a predetermined amount of time after the reset signal RST switches low-to-high and then high-to-low. The duration of the time interval from a rising edge of the reset signal RST to the rising edge of the END signal represents the effective duration of the dead zone compensation time interval. When the END signal switches low-to-high, the NMOS transistor N 5  turns on and the output node X switches low-to-high (XB switches high-to-low), and the dead zone compensation time interval is terminated. Once the dead zone compensation time interval is terminated, the control signal UP will reflect the value of the true output Q 1  of the first flip-flop and the control signal DOWN will reflect the value of the true output Q 2  of the second flip-flop. 
   The phase detector  40  of  FIG. 4A  precludes gain inversion events by providing essentially immediate reset of the flip-flops DFF 1  and DFF 2  once a dead zone compensation time interval has commenced. This is further illustrated by the timing diagram of  FIG. 4B , which shows the signals: CKREF, CKVCO, Q 1 , Q 2 , RST, X, END, UP and DOWN. In  FIG. 4B , the high-to-low and low-to-high transitions of the output signal X (from the output node X of the latch defined by inverters I 5  and I 6  in  FIG. 4A ) identify the commencement and termination of a dead zone compensation time interval. During this time interval, any rising edge of the reference clock signal CKREF (or feedback clock signal CKVCO) will be recognized by the first flip-flop DFF 1  (or second flip-flop DFF 2 ), which means that clock signal updates will be accepted by the phase detector  40 . As described above with respect to  FIG. 4A , the reset pulses RST are triggered when the following condition is met: Q 1 =Q 2 =1 and the END pulses are delayed relative to the reset pulses RST by an amount equal to T 2 , the effective duration of the dead zone compensation time interval. In response to a rising edge of the reset pulses RST, the output node X is pulled low and held low until a rising edge of a respective end pulse END is generated. The UP and DOWN control signals are both active at high levels during the dead zone compensation time interval (when X=0) and are not influenced by changes in the values of Q 1  and Q 2  (i.e., by the reset of DFF 1  and DFF 2 ). 
     FIG. 5  illustrates a phase detector  50  according to a second embodiment of the present invention. This phase detector  50  is similar to the phase detector of  FIG. 4A , however, the end pulse END is a much wider pulse that is generated by a delay device D 3 . As illustrated, a control circuit  52  includes an inverter I 7  and a NAND gate ND 4  that collectively perform a boolean “AND” operation. The delay device D 3 , inverter I 7  and NAND gate ND 4  collectively form a sensor  54  that generates the END pulse in response to detecting a presence of overlapping UP and DOWN control signals at outputs of the phase detector  50 . Here, the END pulse represents a signal that specifies a termination of the dead zone compensation time interval. Based on this configuration of the sensor  54 , the output of the inverter I 7  is switched low-to-high (and held high) when the following condition is met: UP=DOWN=1. A leading edge of an END pulse causes the NMOS transistor N 5  to turn on and the node XB to switch low. The output node X also switches high so that the levels of the signal lines Q 1 B and Q 2 B can be reflected (in inverted form) at the outputs UP and DOWN of the phase detector  50 . The operation of the phase detector  50  is otherwise equivalent to the operation of the phase detector  40  illustrated by  FIGS. 4A-4B . In  FIG. 6 , a phase detector  60  according to a third embodiment of the present invention has a control circuit  62  that does not require a delay device. Instead, a sensor  64  is provided to monitor feedback signals (NMOS_ON and PMOS_ON) generated by a charge pump  14  (see, e.g., FIG.  2 ). This sensor  64  includes an inverter  18 , a NAND gate ND 4  and an inverter I 7 . When the feedback signal NMOS_ON is switched low and the feedback signal PMOS_ON is switched high in response to active UP and DOWN control signals, the END signal will be switched low-to-high and the output node X of the latch will be switched and held high. Accordingly, the termination of each dead zone compensation time interval is controlled by internal operation within a charge pump  14 . This internal operation provides an inherent amount of delay which supports a sufficiently long time interval to prevent dead zone operation. 
   In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.