Abstract:
A semiconductor device comprises a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to said substrate top surface, and electrically insulated from said semiconductor substrate by a gate insulating film, a trench formed through said gate electrode into said semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of said substrate top surface, a first boundary end portion, which is defined between a substrate side surface of said semiconductor substrate forming a part of the side surface of said trench and said substrate top surface, and a second boundary end portion, which is defined between a gate side surface of said gate electrode forming another part of the side surface of said trench and said opposed surface, wherein said first boundary end portion and said second boundary end portion have spherical shapes having a curvature radius not smaller than 30 angstrom.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-198571, filed on Jun. 29, 2001, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having device isolation by STI and its manufacturing method.  
         [0004]     2. Related Background Art  
         [0005]     For the purpose of downsizing semiconductor devices, the method of isolating devices by STI (Shallow Trench Isolation) has been used for years in lieu of the technique using selective oxidation for isolating devices. STI is a technique for electrically insulating device regions forming devices from other regions in a semiconductor device by making trenches. In STI, trenches are formed in device isolating regions instead of selective oxidation thereof.  
         [0006]      FIG. 8  is an enlarged cross-sectional view of a semiconductor device  700  having conventional STI under a process of its manufacturing. A gate insulating film  20  is formed on the top surface of a semiconductor substrate  10 . A gate electrode  30  in form of an amorphous silicon film overlies the gate insulating film  20 . A silicon nitride film  40  is deposited on the gate electrode  30 . A silicon oxide film  50  is deposited on the silicon nitride film  40 .  
         [0007]     The silicon nitride film  40  and the silicon oxide film  50  are selectively removed by etching into a predetermined pattern by photolithography. After that, using the silicon oxide film  50  as a mask, the gate electrode  30 , the gate insulating film  20  and the semiconductor substrate  10  are selectively removed by etching. In this etching, the trench  60  is formed to dig into the semiconductor substrate  10 .  
         [0008]     Subsequently, the side and bottom surface portions of the trench  60  are oxidized by RTO (rapid thermal oxidation) in an oxygen O 2  atmosphere held at 1000° C. In  FIG. 8 , the trench  60  and the surrounding structure after RTO treatment are shown in an enlarged scale.  
         [0009]     On the side surface and the bottom surface of the trench  60 , a silicon oxide film  70  is formed by RTO. The silicon oxide film  70  protects the semiconductor substrate  10 , etc.  
         [0010]     In general, the diffusion coefficient of an oxidation seed is smaller when diffusing into silicon single crystal used as a semiconductor substrate exhibit than when diffusion into amorphous silicon.  
         [0011]     Therefore, in the oxidation process by RTO, thickness T 2  of the silicon oxide film  70   b  formed on silicon single crystal used as the semiconductor substrate  10  is thinner than the thickness T 1  of the silicon oxide film  70   a  formed on the gate electrode  30 .  
         [0012]     Either in silicon single crystal or amorphous silicon, end portions like sides or corners located at boundaries of two planes receive a larger stress than flat surface portions as the oxidation progresses. To such end portions of silicon single crystal or amorphous silicon, the oxide seed is difficult to diffuse. Therefore, there occurs the phenomenon in which planar surfaces of silicon single crystal or amorphous silicon are more easily oxidized whereas end portions of that are difficult to oxidize.  
         [0013]      FIG. 2B  is an enlarged cross-sectional view of an end portion of a semiconductor substrate and an end portion of a gate electrode that are encircled by a broken line circle in  FIG. 8 . Since the end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30  are more difficult to oxidize than flat surfaces, the oxide film formed on the semiconductor substrate  10  and the gate electrode  30  become thinner and thinner toward their end portions than the thickness on their flat surfaces. As a result, the end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30  are sharpened (see the inside of the broken line circle of  FIG. 2B ). The shaper the end portions of the semiconductor substrate  10  and the gate electrode  30 , the larger the stress applied thereto. Thus the electric field is liable to concentrate at the end portions.  
         [0014]     In addition, since the silicon oxide film  70   b  is thinner than the silicon oxide film  70   a , the end portion of the gate electrode  30  overlaps a flat portion of the substrate top surface  12  when viewed from a vertical direction relative to the substrate top surface  12  of the semiconductor substrate  10  (see the dot-and-dash line in  FIG. 2B ).  
         [0015]     As the stress to the gate electrode  30  and the gate insulating film  20  becomes larger, electrons trapped in the gate insulating film  20  increase (hereinafter called trapped electrons). The increase of the trapped electrons causes fluctuation of the threshold voltage (see  FIG. 6 ).  
         [0016]     Fluctuation of the threshold voltage prevents normal operation of the semiconductor device  700 . In case the gate electrode  30  is used as the floating gate electrode of a memory, those defects often decreases the possible frequency of write and erase operation (hereinafter called W/E endurance characteristics) (see  FIG. 7 ).  
         [0017]     Furthermore, when viewed from a direction vertical to the substrate top surface  12  of the semiconductor substrate  10 , since the end portion of the gate electrode  30  liable to gather the electric field overlaps a flat portion of the substrate top surface  12 , the resistance voltage of the gate in the semiconductor device  700  undesirably decreases.  
       SUMMARY OF THE INVENTION  
       [0018]     According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor substrate having a substrate top surface on which a device should be formed, a gate electrode having an opposed surface opposed to the substrate top surface, and electrically insulated from the semiconductor substrate by a gate insulating film, a trench formed through the gate electrode into the semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of the substrate top surface, a first boundary end portion, which is defined between a substrate side surface of the semiconductor substrate forming a part of the side surface of the trench and the substrate top surface, and a second boundary end portion, which is defined between a gate side surface of the gate electrode forming another part of the side surface of the trench and the opposed surface, wherein said first boundary end portion and said second boundary end portion have spherical shapes having a curvature radius not smaller than 30 angstrom.  
         [0019]     According to a further embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to the substrate top surface, and electrically insulated from the semiconductor substrate by a gate insulating film, a trench formed through the gate electrode into the semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of the substrate top surface, a first boundary end portion, which is defined between a substrate side surface of the semiconductor substrate forming a part of the side surface of the trench and the substrate top surface, and a second boundary end portion, which is defined between a gate side surface of the gate electrode forming another part of the side surface of the trench and the opposed surface, wherein said first boundary end portion overlaps said second boundary end portion when they are viewed from a direction vertical to the substrate top surface.  
         [0020]     According to a still further embodiment of the invention, there is provided a semiconductor device manufacturing method comprising: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, the gate insulting film and the semiconductor substrate to form a trench which electrically isolate a device region for forming a device from the remainder region on the substrate top surface; and oxidizing a substrate side surface of the semiconductor substrate, which forms a part of the side surface of the trench, and a gate side surface of the gate electrode, which forms another part of the side surface of the trench, in a hydrogen H 2  and oxygen O 2  atmosphere.  
         [0021]     According to a yet further embodiment of the invention, there is provided a semiconductor device manufacturing method comprising: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, the gate insulting film and the semiconductor substrate to form a trench which electrically isolate a device region for forming a device from the remainder region on the substrate top surface; and oxidizing a substrate side surface of the semiconductor substrate, which forms a part of the side surface of the trench, and a gate side surface of the gate electrode, which forms another part of the side surface of the trench, in an ozone O 3  atmosphere. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]      FIG. 1A  is an enlarged cross-sectional view of a trench and its surrounding structure in a semiconductor device  100  having STI according to an embodiment of the invention;  
         [0023]      FIG. 1B  is an enlarged cross-sectional view of the trench and its surrounding structure in the semiconductor device  100  after the manufacturing process of  FIG. 1A ;  
         [0024]      FIG. 1C  is an enlarged cross-sectional view of the trench and its surrounding structure in the semiconductor device  100  after the manufacturing process of  FIG. 1B ;  
         [0025]      FIG. 2A  is an enlarged cross-sectional view of an end portion of a semiconductor substrate and an end portion of a gate electrode before oxidation processing by RTO;  
         [0026]      FIG. 2B  is an enlarged cross-sectional view of an end portion of a semiconductor substrate and an end portion of a gate electrode in a conventional semiconductor device after oxidation processing by RTO;  
         [0027]      FIG. 2C  is an enlarged cross-sectional view of an end portion of the semiconductor substrate and an end portion of the gate electrode in the semiconductor device according to the embodiment of the invention after oxidation processing by RTO;  
         [0028]      FIG. 3  is a diagram showing a graph that illustrates a relation between the curvature radius of boundary end portions  15 ,  35  and the variation of trapped electrons (ΔVge);  
         [0029]      FIG. 4  is a diagram showing a graph that illustrates a relation between the stress in a gate insulating film and the variation of trapped electrons;  
         [0030]      FIG. 5  is a diagram showing a graph that illustrates a relation between the duration of time of the supply of a constant current to the gate insulating film  20  and the variation of traped electrons (ΔVge);  
         [0031]      FIG. 6  is a diagram showing a graph that illustrates a relation between the threshold voltage (Vt) of the semiconductor device and the variation of the trapped electrons (ΔVge) in the gate insulating film  20 ;  
         [0032]      FIG. 7  is a diagram showing a graph that illustrates a relation between the W/E endurance characteristics in a memory of the semiconductor device and the threshold voltage of the semiconductor device; and  
         [0033]      FIG. 8  is an enlarged cross-sectional view of a conventional semiconductor device  700  having STI under a manufacturing process thereof. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     An embodiment of the invention will be explained below with reference to the drawings. The embodiment, however, should not be construed to limit the invention.  
         [0035]      FIGS. 1A, 1B  and  1 C are enlarged cross-sectional views of a trench and its surrounding structure in a semiconductor device  100  having STI according to an embodiment of the invention. The semiconductor device  100  is manufactured in the order of  FIG. 1A ,  FIG. 1B  and  FIG. 1C .  
         [0036]     First referring to  FIG. 1A , formed on the top surface of a semiconductor substrate  10  is a gate insulating film  20  in form of a silicon oxide film, approximately 10 nm thick, for example. Formed on the gate insulating film  20  is a gate electrode  30  in form of an amorphous silicon film, approximately 60 nm thick, for example. Deposited on the gate electrode  30  is a silicon nitride film  40 . Deposited on the silicon nitride film  40  is a silicon oxide film  50 .  
         [0037]     The silicon nitride film  40  and the silicon oxide film  50  are selectively etched into a predetermined pattern by using photolithography. After that, using the silicon oxide film  50  as a mask, the gate electrode  30 , gate insulating film  20  and semiconductor substrate  10  are selectively removed by etching. In this etching, a trench  60  is formed to pass through the gate electrode  30  and the gate insulating film  20  and reach to the semiconductor substrate  10 .  
         [0038]     Subsequently, as shown in  FIG. 1B , the side and bottom surface portions of the trench  60  are oxidized by RTO in an atmosphere containing hydrogen H 2  and oxygen O 2  held at approximately 1000° C.  FIG. 1B  shows the trench  60  and its surrounding structure after oxidation in the hydrogen H 2  and oxygen O 2  atmosphere in an enlarged cross-sectional view. Thickness T 3  of the oxide film formed along the side surface of the semiconductor substrate  10  and thickness T 4  of the oxide film formed along the side surface of the gate electrode  30  are substantially equal. In case of this embodiment, thickness T 3  and thickness T 4  were approximately 6 nm.  
         [0039]     After that, as shown in  FIG. 1C , a silicon oxide material  80  is deposited to bury the trench  60  by using the HDP (high density plasma) technique. Then the silicon oxide material  80  is smoothed by CMP, and the semiconductor substrate  10  is thereafter heated in a nitrogen atmosphere held at approximately 900° C. After the semiconductor substrate  10  is next exposed to NH 4 F solution, the silicon nitride film  40  is removed by phosphation at approximately 150° C. Thereafter, doped polysilicon  90  containing phosphor is deposited on the silicon oxide material  80  and the gate electrode  30  by low-pressure CVD.  
         [0040]     Through some further steps, the semiconductor device  100  having device isolation by the trench  60  is completed.  
         [0041]      FIG. 2A  is an enlarged cross-sectional view of an end portion of the semiconductor substrate  10  and an end portion of the gate electrode  30  in the semiconductor device  100  or  700  before oxidation processing by RTO.  FIG. 2B  is an enlarged cross-sectional view of an end portion of the semiconductor substrate  10  and an end portion of the gate electrode  30  in the conventional semiconductor device  700  after oxidation processing by RTO.  FIG. 2C  is an enlarged cross-sectional view of an end portion of the semiconductor substrate  10  and an end portion of the gate electrode  30  in the semiconductor device  100  according to the embodiment of the invention after oxidation processing by RTO.  
         [0042]     The end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30  encircled by broken line circles in  FIG. 1B  appear in  FIG. 2C  in an enlarged scale.  
         [0043]     As shown in  FIG. 2C , the semiconductor device  100  according to the embodiment is electrically insulated from the semiconductor substrate, and includes the gate electrode  30  having an opposed surface  32  facing to the substrate surface  12  of the semiconductor substrate  10 , and the trench  60  penetrating the gate electrode  30  and extending into the semiconductor substrate  10 . The gate insulating film  20  is formed between the semiconductor substrate  10  and the gate electrode  30  to electrically insulate them.  
         [0044]     The semiconductor substrate  10  is made of, for example, silicon single crystal. The gate insulating film  20  may be, for example, a silicon oxide film formed by oxidizing the semiconductor substrate  10 . The gate electrode  30  is formed by depositing amorphous silicon, for example.  
         [0045]     A silicon oxide film  70   a  is formed on the substrate side surface  14  of the semiconductor substrate  10  by RTO, and a silicon oxide film  70   b  is formed on the gate side surface  34  of the gate electrode  30 . In this embodiment, thickness T 3  of the silicon oxide film  70   a  and thickness T 4  of the silicon oxide film  70   b  are approximately equal.  
         [0046]     In case the oxidation of the side surface and the bottom surface of the trench  60  is carried out in an oxygen O 2  (dry oxygen) atmosphere as the conventional technique did, the diffusion coefficient of the oxidation seed is relatively small. Especially, the oxidation seed exhibits a smaller diffusion coefficient when diffusing into silicon single crystal than when diffusing into amorphous silicon. Therefore, as shown in  FIG. 2B , thickness T 2  of the silicon oxide film  70   b  becomes thinner than thickness T 1  of the silicon oxide film  70   a.    
         [0047]     In the embodiment of the invention, oxidation of the side surface and the bottom surface of the trench  60  is carried out in a hydrogen H 2  plus oxygen O 2  atmosphere. In this case, the oxidation seed exhibits a larger diffusion coefficient than conventional one. The increase of the diffusion coefficient for diffusion into silicon single crystal is especially great as compared with the increase of the diffusion coefficient for diffusion into amorphous silicon. Therefore, the difference in oxidation speed between silicon single crystal and amorphous silicon is diminished, and it results in substantially equalizing the thickness T 3  of the silicon oxide film  70   a  and the thickness. T 4  of the silicon oxide film  70   b.    
         [0048]     In the instant embodiment, oxygen radicals are generated by inviting interaction of hydrogen H 2  and oxygen O 2  by RTO under a high temperature, and the oxygen radicals serve as the oxidation seed. However, also when using O 3  (ozone) in lieu of hydrogen H 2  and oxygen O 2  for oxidation, the same configuration as the semiconductor device  100  according to the instant embodiment can be obtained.  
         [0049]     In this embodiment, since the diffusion coefficient of the oxidation seed becomes relatively larger, oxidation is promoted at the end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30  that are subjected to a stress. Therefore, in the semiconductor device  100  according to the instant embodiment, the end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30  are not sharp or beveled unlike those of the conventional device.  
         [0050]     In the semiconductor device  100  according to the instant embodiment, the boundary end portion  15  of the semiconductor substrate  10  defined between the substrate side surface  14  forming a part of the side surface of the trench  60  and the substrate top surface  12 , and the boundary end portion  35  of the gate electrode  30  defined between the gate side surface  34  forming a part of the trench  60  and the opposed surface  12 , are rounded into a spherical form having a curvature radius not smaller than 30 angstrom. In case of the conventional semiconductor device  700 , since the boundary end portion of the semiconductor substrate  10  and the boundary end portion of the gate electrode  30  are not clearly defined, they were named here the end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30 . Therefore, in the semiconductor device  100  according to the instant embodiment, the boundary end portion  15  and the boundary end portion  35  substantially correspond to the end portion of the semiconductor substrate  10  and the end portion of the gate electrode  30 , respectively.  
         [0051]     Once the boundary end portions  15 ,  30  are shaped spherical with a curvature radius not smaller than a certain value, concentration of the stress to the boundary end portions  15 ,  30  can be alleviated. Simultaneously, local concentration of the electric field to the boundary end portions  15 ,  35  is alleviated.  
         [0052]     In the semiconductor device  100  according to the instant embodiment, since the thickness T 3  of the silicon oxide film  70   a  and the thickness T 4  of the silicon oxide film  70   b  are approximately equal, the substrate top surface  12  and the boundary end portion  35  do not overlap, and the opposed surface  12  and the boundary end portion  15  do not overlap, when they are viewed from a direction vertical to the substrate top surface  12 . In other words, in a view from a direction vertical to the substrate top surface  12 , the boundary end portions  35 ,  15  appear to overlap.  
         [0053]     Because of this configuration, even if the electric field concentrates to the boundary end portions  15 ,  35 , the gate insulating film  20  is unlikely to break, and this feature contributes to improving the production yield of semiconductor devices.  
         [0054]      FIG. 3  is a diagram showing a graph that illustrates a relation between the curvature radius of boundary end portions  15 ,  30  and the variation of trapped electrons (ΔVge). ΔVge is the variation of the gate voltage for representation of the variation of the electrons trapped in the gate insulating film  20 . This graph shows in actual measurement value the variation of the trapped electrons after applying a constant current stress of 0.1 A/cm 2  from the gate electrode  30  to the gate insulating film  20  for 20 seconds and injecting electric charges of approximately 2 C/cm 2 .  
         [0055]     When the boundary end portions  15 ,  35  have a curvature radius smaller than approximately 30 angstrom, ΔVge is large, and the amount of the trapped electrons is great. When the curvature radius of the boundary end portions  15 ,  35  is larger than approximately 30 angstrom, ΔVge is small, and the amount of the trapped electrons is small. When the curvature radius exceeds approximately 30 angstrom, the rate of the decrease of ΔVge decelerates. Therefore, when the curvature radius of the boundary end portions  15 ,  35  are adjusted to be approximately 30 angstrom or more, concentration of the stress and the electric field to the boundary end portions  15 ,  35  is effectively alleviated.  
         [0056]      FIG. 4  is a diagram showing a graph that illustrates a relation between the stress in a gate insulating film and the amount of the trapped electrons. The abscissa of the graph shown in  FIG. 4  represents the stress in the gate insulating film  20  whereas the ordinate represents the variation of the trapped electrons (ΔVge). This graph shows in simulation value the variation of the trapped electrons in each of the conventional semiconductor device  700  and the semiconductor device  100  according to the instant embodiment after applying a constant current stress of 0.1 A/cm 2  from the gate electrode  30  to the gate insulating film  20  for 20 seconds, and injecting electric charges of approximately 2 C/cm 2 . In  FIG. 4 , as the stress in the gate electrode  30  decreases, the value ΔVge decreases  
         [0057]     As the difference in thickness between the silicon oxide film  70   a  and the silicon oxide film  70   b  increases, the stress of the gate insulting film  20  increases. Further, as the stress to the boundary end portions  15 ,  35  increases, the stress in the gate insulating film  20  increases. It can therefore be understood that the amount of the trapped electrons in the gate insulating film  20  of the semiconductor device  100  according to the instant embodiment is less than the amount of the trapped electrons in the gate insulating film  20  of the conventional semiconductor device  700 .  
         [0058]     ΔVge is different in value and sign between  FIG. 3  and  FIG. 4 . This is because  FIG. 3  shows ΔVge in experimental value and absolute value but  FIG. 4  shows it in simulation value with the plus or minus sign.  
         [0059]      FIG. 5  is a diagram showing a graph that illustrates a typical relation between the duration of time of the supply of a constant current to the gate insulating film  20  and the variation of the trapped electrons in the gate insulating film  20  (ΔVge).  FIG. 5  teaches that the amount of the trapped electrons increases as the duration of time of the supply of a constant current to the gate insulating film  20  becomes longer.  
         [0060]      FIG. 6  is a diagram showing a graph that illustrates a typical relation between the threshold voltage (Vt) of the semiconductor device and the variation of the trapped electrons (ΔVge) in the gate insulating film  20 .  FIG. 6  teaches that the threshold voltage of the semiconductor device changes in proportion to the amount of the trapped electrons.  
         [0061]     As compared with the conventional semiconductor device  700 , the semiconductor device  100  according to the instant embodiment is less in the amount of electrons (Δvge) trapped in the gate insulating film  20  (see  FIGS. 4 and 5 ), and therefore smaller in fluctuation of the threshold voltage (see  FIG. 6 ). This means that the semiconductor device  100  is stronger against electrical stress and has a longer lifetime than the semiconductor device  700 .  
         [0062]      FIG. 7  is a diagram showing a graph that illustrates a typical relation between the W/E endurance characteristics in a memory of the semiconductor device and the threshold voltage of the semiconductor device.  FIG. 7  teaches that, as the Write/Erase frequency increases, the amount of electrons trapped in the gate insulating film  20  increases, and the threshold voltage of the semiconductor device results in fluctuation.  
         [0063]     From  FIGS. 4 through 6 , it is understood that the semiconductor device  100  according to the instant embodiment exhibits a smaller variation of the trapped electrons (ΔVge) relative to the constant current stress than that of the conventional semiconductor device  700 . Therefore, in a nonvolatile semiconductor storage device using the gate electrode  30  as its floating gate electrode, the semiconductor device  100  according to the instant embodiment will operate with a smaller variation of the trapped electrons (Δvge) and smaller fluctuation of the threshold voltage even over more frequent Write/Erase actions than the conventional semiconductor device  700 . Furthermore, even if operated for Write/Erase more frequently, the semiconductor device  100  can hold electric charges in the gate electrode  30  as the floating gate electrode for a longer period of time than the semiconductor device  700 .  
         [0064]     Although the explanation with reference to  FIGS. 4 through 7  has been made in conjunction with the trapped electrons, it is similarly applicable also to the trapped holes.  
         [0065]     The semiconductor device according to the instant embodiment as explained above ensures that since the stress and the electric field do not concentrate at end portions of the semiconductor substrate and the amorphous silicon film, the trapped electrons are fewer and the resistance to voltage of the gate is relatively higher than the conventional semiconductor device.  
         [0066]     The manufacturing method of a semiconductor device according to an embodiment the invention can manufacture a semiconductor device in which since a stress and an electric field do not concentrate at the end portions of the semiconductor substrate and the amorphous silicon film, the trapped electrons are fewer and the resistance to voltage of the gate is relatively higher than the conventional method.