Abstract:
An integrated circuit includes an embedded memory device and an on-chip test circuit. The on-chip test circuit includes a multiplexer and one or more I/O circuits. The multiplexer allows the I/O circuits to interface with a plurality of inputs and outputs associated with the embedded memory device. As a result, the embedded memory device in the integrated circuit may be tested or repaired after the embedded memory array portion of the integrated circuit is formed, yet prior to fabrication of dedicated input/output circuitry. This allows evaluation of the embedded memory device in the integrated circuit prior to committing resources to complete fabrication of the entire integrated circuit.

Description:
TECHNICAL FIELD 
     The present invention relates generally to testing of integrated circuits, and more specifically to a method and apparatus that permits accessing of memory arrays embedded in the integrated circuits independent of any embedded logic arrays associated with the integrated circuits. 
     BACKGROUND OF THE INVENTION 
     FIG. 1 is a simplified block diagram of an integrated circuit  10  according to the prior art. The integrated circuit  10  includes an embedded memory device  12 , also known as a matrix memory device  12 , together with spare or redundant memory cells  12 ′. The embedded memory device  12  is coupled through an internal bus  14  to an embedded logic array  16  that is also coupled to I/O circuitry  18  dedicated to the embedded logic array  16 . As used herein, the term “embedded,” as applied to circuitry contained on the integrated circuit  10 , refers to a circuit having one or more associated busses that are not normally directly accessible from outside of the integrated circuit  10 . 
     In operation, the I/O circuitry  18  couples control and data signals from external circuitry (not illustrated) to the embedded logic array  16 . The embedded logic array  16  operates on the data signals in accordance with the control signals and generates intermediate or final results. These results are coupled from the embedded logic array  16  through the internal bus  14  and are stored in the embedded memory device  12 . The embedded logic aray  16  recalls these results at a later time and uses them to generate output signals that are then coupled from the integrated circuit  10  to the external circuitry through the embedded logic array  16  and the I/O circuitry  18 . While the above-described arrangement provides great advantages in achieving high data transfer rates between the memory device  12  and the logic circuitry  16 , it only permits the embedded memory device  12  to be externally accessed through the embedded logic array  16 . In other words, unless the embedded logic array  16  is operational, the embedded memory device  12  cannot be easily accessed for purposes such as testing. Further, the embedded memory device  12  may only be tested with those tests that are pre-programmed into the embedded logic array  16  or through the I/O circuitry  18  of the embedded logic array  16 . 
     The internal bus  14  includes ‘N’ data lines, where N may be large, e.g., the internal bus  14  may be 64, 128, 256 or 512 bits wide or may be even wider. When the internal bus  14  is wide or very wide, it is impractical to provide I/O pads dedicated to each bit or data line of the internal bus  14 . Furthermore, if the I/O pads  24  are to be connected to externally accessible terminals, then buffers, electrostatic discharge protection and other circuitry (not illustrated) must be provided for each data line of the internal bus  14 . Yet this additional circuitry for each data line would consume unacceptably large portions of the integrated circuit  10  in order to provide external access to all of the data lines of the internal bus  14 . 
     In many applications, the embedded memory device  12  is formed prior to forming the embedded logic array  16  for several different reasons. Many memory circuits, such as the embedded memory device  12 , require smaller linewidths (i.e., minimum feature sizes) than are necessary for the embedded logic array  16 , in order for the embedded memory device  12  to provide data storage densities consistent with economical fabrication of the integrated circuit  10 . Also, the processing steps required to fabricate the embedded memory device  12  may be different than those required to fabricate the embedded logic array  16 . These reasons, particularly in combination, often favor fabricating the embedded memory device  12  prior to fabricating the embedded logic array  16 . 
     A typical embedded memory device  12  in an integrated circuit  10  includes at least one array of memory cells (not illustrated) arranged in rows and columns. Each memory cell must be tested to ensure that it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) are written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a “0”) are typically written to and read from the memory cells. The data written to the memory cells are known as “write” data, and the data read from the memory cells are known as “read” data. The read data are compared to a corresponding set of expect data. The expect data correspond to read data that would be provided by the integrated circuit  10  if its embedded memory device  12  was operating properly. A memory cell is considered to be defective when the read data and the corresponding expect data do not agree. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern, e.g., 101010, . . . , written to the memory cells in each row of the memory device  12 . 
     Defective memory cells that are identified by testing are replaced with non-defective memory cells from rows or columns of spare or redundant memory cells  12 ′. In one conventional method for replacing defective memory cells, fuses on the integrated circuit  10  are blown in a pattern corresponding to the addresses of defective memory cells. The pattern is then compared to incoming addresses to select the rows or columns of redundant memory cells  12 ′ to replace rows or columns in the memory device  12  containing the defective memory cells. 
     However, it is desirable to be able to test the embedded memory device  12  before the embedded logic array  16  has been formed. When fabrication yields for the embedded memory device  12  are poor, or when fabrication yields decrease, it may be undesirable to fabricate the embedded logic array  16  and combine it with the memory device  12  prior to testing the memory device  12 . Further, discovering fabrication problems early in forming the integrated circuit  10  allows corrective steps to be taken early, reducing the number of integrated circuits  10  affected by a particular fabrication problem. Early detection of fabrication problems favors increased yields and reduced waste. 
     Accordingly, there is a need for an on-chip test circuit to permit testing of embedded memory devices in integrated circuits prior to fabrication of dedicated logic circuits for the integrated circuits. 
     SUMMARY OF THE INVENTION 
     In one aspect of the present invention, an integrated circuit includes an embedded memory device coupled to an internal bus having a first number of data lines, a multiplexer and an I/O port having a second number of data lines that is less than the first number of data lines. The multiplexer allows the I/O port to be coupled to a portion of the data lines of the internal bus and thus to at least a portion of the embedded memory device. As a result, the embedded memory device may be tested or repaired before an embedded logic function associated with dedicated I/O pins or pads is added to the integrated circuit. This promotes improved economic efficiency by allowing a manufacturer to cull integrated circuits that do not have acceptable fabrication yields prior to fabrication of the embedded logic array. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of an integrated circuit according to the prior art. 
     FIG. 2 is a simplified block diagram of an integrated circuit including an on-chip testing circuit in accordance with an embodiment of the present invention. 
     FIG. 3 is a flow chart of a process for forming the integrated circuit of FIG. 2 in accordance with an embodiment of the present invention. 
     FIG. 4 is a simplified block diagram of a computer system including the integrated circuit of FIG. 2 in accordance with an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 is a simplified block diagram of an integrated circuit  20  including an on-chip testing circuit  22  in accordance with an embodiment of the present invention. The integrated circuit  20  includes the embedded memory device  12  coupled to the on-chip testing circuit  22  and may include the embedded logic array  16  as described above in association with FIG.  1 . In one embodiment, the embedded memory device  12  includes a memory circuit such as a dynamic random access memory (“DRAM”). The on-chip testing circuit  22  includes I/O pins or pads  24  and a multiplexer (“MUX”)  26 . The on-chip testing circuit  22  includes a bus  27  that couples a bi-directional buffer  28  to a first set of data ports of the MUX  26  and to the I/O pins or pads  24 . 
     In one embodiment, the I/O pads  24  are shared by the testing circuit  22  and the I/O circuitry  18 , i.e., the I/O pads  24  are a subset of the I/O circuitry  18 . As a result, the same I/O pads  24  and/or pins can be used for testing and for normal operations. 
     The I/O pins or pads  24 , the bus  27 , the bi-directional buffer  28  and the first set of data ports of the MUX  26  each include ‘M’ digital data lines, which is substantially fewer than the ‘N’ data lines of the internal bus  14 . In one embodiment, M may be related to N as in M=N/2 n . For example, M might be  16  while N might be  512 , i.e., n=five, however, M may be any number greater than or equal to one, but typically will be less than thirty-two. The on-chip test circuit  22  also includes a test mode logic circuit  30  having inputs coupled to the I/O circuitry  18  and having outputs coupled to the MUX  26 . The test mode logic circuit  30  provides control signals to the MUX  26  to select a subset of the N data lines of the internal data bus  14  to be coupled to the M I/O pins or pads  24 . In one embodiment, a subset of M of N second data ports of the MUX  26  is coupled to a corresponding subset of M of the N data lines of the internal bus  14 . In another embodiment, a subset of M data ports of the MUX  26  is coupled to a multiple of M of the N data lines of the internal bus  14  through optional compression circuitry  32 . 
     In some applications, the I/O pins or pads  24  are accessed through probes by an automated tester  34  prior to completion of packaging of the integrated circuit  20 , allowing testing of the embedded memory device  12  while the integrated circuit  20  is still in wafer form. The embedded memory device  12  may be repaired, as discussed above, and the repair of the embedded memory device  12  may precede fabrication of the embedded logic array  16 . In other embodiments, the I/O pins or pads  24  may be bonded to pins in the completed, packaged integrated circuit  20 , providing external access to the embedded memory device  12  even in the event that the embedded logic array  16  is not functional. Bonding the I/O pads  24  to package pins also permits a broader range of tests than those tests that are pre-programmed into the embedded logic array  16  to be applied to the embedded memory device  12 . 
     FIG. 3 is a flow chart of a process  40  for forming the integrated circuit  20  of FIG. 2 according to an embodiment of the present invention. The process  40  begins after the embedded memory device  12  has already been formed. In a step  42 , a test port on a tester, such as the automated tester  34 , is coupled to the I/O pads  24 . In one embodiment, a probe card having a number of probes is used to make temporary connections to the I/O pads  24 . Any other temporary connections (power supply, control signals for the MUX  26  etc.) required to be able to test the embedded memory device  12  are also made to the integrated circuit  20 . In a step  44 , a group of index variables m are selected that correspond to addresses for a first group of rows (0:N/2 n −1) that form a portion of the embedded memory device  12  selected for testing. In a step  46 , the MUX  26  is programmed to couple the selected rows to the I/O pads  24 . In a step  48 , background data are supplied to the selected rows of the embedded memory device  12 . In a step  50 , read data are extracted from the selected portion of the embedded memory device  12  through the I/O pads  24 . In a query task  52 , the automated tester  34  determines if the read data and the corresponding expect data agree. 
     When the query task  52  determines that the read data and the corresponding expect data do not agree, data describing the failed memory cell (e.g., the cell address) are written to a memory in the automated tester in a step  54 . When the query task  52  determines that the read data and the corresponding expect data do agree, control passes to a query task  56 . 
     The query task  56  determines if all of the columns in the embedded memory device  12  have been tested. When the query task  56  determines that not all of the columns in the embedded memory device  12  have been tested, control passes to a step  58 . In the step  58 , a column counter is incremented and control then returns to the step  48 . When the query task  56  determines that all of the columns in the embedded memory device  12  have been tested, control passes to a query task  60 . 
     The query task  60  determines if all of the rows in the embedded memory device  12  have been tested. When not all of the rows in the embedded memory device  12  have been tested, control passes to a step  62 . In the step  62 , the control signals to the MUX  26  are incremented. In one embodiment, the control signals to the MUX  26  are incremented to test the rows adjacent to the rows that have just been tested. Since M=N/2 n , the index variables m corresponding to the rows being addressed are incremented by N/2 n  in this embodiment. When all of the rows in the embedded memory device  12  have been tested, control passes to a step  64 . 
     In the step  64 , the embedded memory device  12  is repaired. In one embodiment, the defective memory cells in the embedded memory device  12  are replaced in a conventional manner by blowing fuses or antifuses in a pattern corresponding to addresses of rows or columns including the defective memory cells that were identified in the query task  52 . Antifuses are devices that are initially nonconductive but which may be stressed or “blown” by an appropriate bias to become permanently conductive. 
     In a step  66 , the embedded logic array  16  and the remainder of the integrated circuit  20  are formed through conventional fabrication procedures. The process  40  then ends. 
     In a different embodiment of the process  40 , some data compression is employed in testing the embedded memory device  12 . For example, in the step  46 , not only are M many rows selected by the MUX  26 , but an additional group of rows is also selected by the optional compression circuitry  32 . The additional group of rows might include, e.g., another M many rows, or it might include, e.g., another  3 M many rows. In the step  48 , background data are supplied to all of the selected rows via the optional compression circuitry  32 . In the step  50 , combinatorial logic in the optional compression circuitry  32  combines the read data from all of the selected rows such that the query task  52  is able to determine that one of the several rows corresponding to one of the M I/O pads  24  includes a defective memory cell. In one embodiment, the several rows associated with the I/O pad  24  carrying the data indicative of a memory cell failure are replaced with a group of rows from the redundant memory cells  12 ′ to repair the embedded memory device  12 . This embodiment provides some speed advantages in testing of the embedded memory device  12 . 
     It will be appreciated that variations in the process  40  are possible. For example, the steps relating to rows could be steps relating to columns and vice versa. 
     FIG. 4 is a simplified block diagram of a portion of a computer system  80  including the memory integrated circuit  20  of FIG. 2 in accordance with an embodiment of the present invention. The computer system  80  includes a central processing unit  82  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The central processing unit  82  is coupled via a bus  84  to a memory  86 , a user input interface  88 , such as a keyboard or a mouse, function circuitry  90  and a display  92 . The memory  86  may or may not include a memory management module (not illustrated). The memory  86  does include ROM for storing instructions providing an operating system and also includes read-write memory for temporary storage of data. The processor  82  operates on data from the memory  86  in response to input data from the user input interface  88  and displays results on the display  92 . The processor  82  also stores data in the read-write portion of the memory  86 . 
     The function circuitry  90  is an example where the integrated circuit  20  of FIG. 2 may be particularly effective. For example, when the function circuitry  90  includes an encryption engine, a digital signal processing chip (e.g., video processor, vocoder,  3 -dimensional computer graphics, image processing or the like) or provides some other dedicated or programmable complex function, as described, for example, in “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAMs,” by K. Ayukawa et al.,  IEEE Journal of Solid State Circuits  33 (5):800-806, 1998, the integrated circuit  20  will include both read-write memory functions and logic functions, such as those provided by the embedded memory device  12  and the embedded logic array  16 , respectively (see FIGS.  1  and  2 ). In turn, these functions may be realized least expensively when the embedded memory device  12  can be evaluated prior to completing fabrication of the embedded logic array  16 . 
     Examples of systems where the computer system  80  finds application include personal/portable computers, camcorders, televisions, automobile electronic systems, microwave ovens and other home and industrial appliances. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.