Abstract:
An oscillator includes a comparison means suitable for generating a comparison signal by comparing an internal voltage of an internal node with a reference voltage; an inverting unit suitable for inverting the comparison signal and transmitting the inverted comparison signal to an output node; a pull-up driving unit suitable for pull-up driving the internal node in response to the voltage of the output node; a discharge unit suitable for discharging the internal node; and a gate coupled between the internal node and the discharge unit, and turned on/off in response to the voltage of the output node, wherein at least part of a capacitive load included in the oscillator is electrically coupled to the internal node.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Applications No. 10-2014-0074188, filed on Jun. 18, 2014, and No. 10-2014-0105651, filed on Aug. 14, 2014, which are incorporated herein by reference in their entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    This patent document relates to an oscillator and a memory device including the same. 
         [0004]    2. Description of the Related Art 
         [0005]    Circuits such as memory devices, integrated-circuit (IC) chips, micro-controllers, and pump circuits use periodic signals for internal circuit operations. These periodic signals are generated by an oscillator and allow for synchronization of memory device operations. 
         [0006]    The periodic signal of an oscillator has a period that varies according to the operating environment of the oscillator. Operating environments may change due to changes in temperature or operating voltages. To respond to these changes and optimize performance, the periodic signal may be adjusted to suit the given operating environment. 
         [0007]    A memory device refresh operation is an example in which adjusting the oscillators periodic signal may improve performance. Memory cells of a memory device include a transistor serving as a switch and a capacitor for storing a charge (data). Whether a charge is stored in the capacitor of the memory cell, that is, whether the terminal voltage of the capacitor is high or low, indicates if the data point being stored is high (logic 1) or low (logic 2). 
         [0008]    Since data is stored as an electric charge in a capacitor, no power is consumed in principle. However, since the initial electric charge stored in the capacitor diminishes due to leakage current caused by the PN Junction of an MOS transistor, or the like, data may be lost. In order to prevent such data loss, data stored in the memory cells must be read before the data is lost, and the capacitor must be recharged according to the information that was read. This recharging operation must be periodically repeated to retain stored data in a process that is known as a refresh operation. 
         [0009]    Refresh operations include self-refresh operations that are performed in the memory device itself. Self-refresh operations may have optimized period signals that are adjusted according to charge retention time. For example, when the retention time is long (low temperature), the refresh period may be lengthened to reduce current consumption, and when the retention time is short (high temperature), the refresh period may be shortened to minimize the possibility of data loss. 
         [0010]    The oscillator may be used to adjust the refresh period of the memory device. The oscillator may generate periodic signals that vary according to temperature. In order to prevent data loss and minimize power consumption, the period of the periodic signals needs to be precisely adjusted to suit the temperature in which the memory device is operating. 
       SUMMARY 
       [0011]    Various embodiments are directed to an oscillator capable of blocking capacitance generated by internal components of a circuit, and generating a periodic signal precisely oscillating at a period according to temperature. 
         [0012]    Also, various embodiments are directed to a memory device capable of minimizing power consumption while optimizing a self-refresh period according to temperature by using the above-described oscillator. 
         [0013]    In an embodiment, an oscillator may include: a comparison means suitable for generating a comparison signal by comparing an internal voltage of an internal node with a reference voltage; an inverting unit suitable for inverting the comparison signal and transmitting the inverted comparison signal to an output node; a pull-up driving unit suitable for pull-up driving the internal node in response to the voltage of the output node; a discharge unit suitable for discharging the internal node; and a gate coupled between the internal node and the discharge unit, and turned on/off in response to the voltage of the output node wherein at least part of a capacitive load included in the oscillator is electrically coupled to the internal node. 
         [0014]    In an embodiment, an oscillator may include: a comparison means suitable for generating a comparison signal by comparing an internal voltage of an internal node with a reference voltage; an inverting unit suitable for inverting the comparison signal and transmitting the inverted comparison signal to an output node; a pull-up driving unit suitable for pull-up driving the internal node in response to the voltage of the output node; a selecting unit suitable for generating a control signal in response to select information and the voltage of the output node; a plurality of discharge units each operative in response to the control signal, and suitable for discharging the internal node; and a plurality of gate units coupled between the internal node and corresponding discharge unit among the plurality of discharge units, and turned on/off in response to the control signal wherein at least part of a capacitive load included in the oscillator is electrically coupled to the internal node. 
         [0015]    In an embodiment, a memory device may include: a cell array comprising a plurality of memory cells; a first signal generation unit suitable for generating a first signal having a fixed period; a second signal generation unit suitable for generating a second signal having a variable period; and a control unit suitable for refreshing the memory cells according to a shorter one between the fixed and variable periods in a self-refresh mode. The second signal generation unit may include: a plurality of discharge units suitable for discharging an internal node; and a plurality of gate units electrically coupled between the internal node and the plurality of discharge units, respectively, and each operative according to the second signal when a corresponding one among the plurality of discharge units is selected, wherein the variable period corresponds to a speed at which the internal node is discharged by the selected one among the plurality of discharge units, wherein at least part of a capacitive load included in the oscillator is electrically coupled to the internal node. 
         [0016]    In an embodiment, an oscillator may include: a comparison means suitable for generating a comparison signal by comparing an internal voltage of an internal node with a reference voltage; an inverting unit suitable for inverting the comparison signal and transmitting the inverted comparison signal to an output node; a pull-up driving unit suitable for pull-up driving the internal node in response to the voltage of the output node; and a plurality of discharge units suitable for discharging the internal node when selected, wherein at least part of a capacitive load included in the oscillator is electrically coupled to the internal node. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a circuit diagram illustrating an oscillator. 
           [0018]      FIG. 2  is a circuit diagram illustrating a transistor included in an oscillator shown in  FIG. 1 . 
           [0019]      FIG. 3  is a circuit diagram illustrating an oscillator in accordance with an exemplary embodiment of the present invention. 
           [0020]      FIG. 4  is a circuit diagram illustrating an oscillator in accordance with an exemplary embodiment of the present invention. 
           [0021]      FIG. 5  is a time vs. internal voltage graph illustrating the behavior of oscillators shown in  FIGS. 1 and 4 . 
           [0022]      FIG. 6  is a block diagram illustrating a memory device in accordance with an exemplary embodiment of the present invention. 
           [0023]      FIG. 7  is a temperature vs. refresh period graph Illustrating a memory device using oscillators shown in  FIGS. 1 and 4 . 
           [0024]      FIG. 8  is a circuit diagram illustrating an oscillator in accordance with an exemplary embodiment of the present invention. 
           [0025]      FIGS. 9A to 9C  are circuit diagrams illustrating oscillators in accordance with exemplary embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0027]      FIG. 1  is a circuit diagram illustrating an oscillator. 
         [0028]    As illustrated in  FIG. 1 , the oscillator includes a comparison unit  110 , an inverting unit  120 , a pull-up driving unit  130 , a capacitor  140 , a plurality of discharge units  150 - 1  to  150 -N, a plurality of coupling units  160 _ 1  to  160 _N, and a control unit  170 . 
         [0029]    The comparison unit  110  compares a reference voltage VREF and the voltage of an internal node IN (hereafter, referred to as an internal voltage VIN), and outputs the comparison result A. The comparison result A is a signal having a high level when the level of the reference voltage VREF is higher than the level of the internal voltage VIN, and is a signal having a low level when the level of the internal voltage VIN is higher than the level of the reference voltage VREF. 
         [0030]    The inverting unit  120  inverts, delays, and outputs the comparison result A of the comparison unit  110  to an output node OUT. The inverting unit  120  includes an odd number of inverters INV_to INV_M coupled in series. The inverting unit  120  has a delay value which is adjusted according to the number of inverters INV_ 1  to INV_M. When the number of inverters INV_ 1  to INV_M is increased, the delay value of the inverting unit  120  is also increased, and when the number of inverters INV_ 1  to INV_M is decreased, the delay value of the inverting unit  120  is also decreased. The voltage of the output node OUT has the opposite value of the output signal of the comparison unit  110 . When the comparison result A of the comparison unit  110  transitions from the low level to the high level, the voltage of the output node OUT transitions from the high level to the low level after a time elapse corresponding to the delay value of the inverting unit  120 . Furthermore, when the comparison result A of the comparison unit  110  transitions from the high level to the low level, the voltage of the output node OUT transitions from the low level to the high level after a time elapse corresponding to the delay value of the inverting unit  120 . 
         [0031]    The pull-up driving unit  130  pull-up drives the internal node IN to a power supply voltage VDD in response to the voltage of the output node OUT. The pull-up driving unit  130  includes a PMOS transistor P coupled to the internal node IN at one end thereof and to the power supply voltage VDD at the other end thereof, and is turned on/off in response to the voltage of the output node OUT. The pull-up driving unit  130  is turned off when the voltage of the output node OUT is at the high level, and is turned on when the voltage of the output node OUT is at the low level and pull-up drives the internal node IN to the power supply voltage VDD. 
         [0032]    The capacitor  140  is coupled to the Internal node IN, and stores electric charges transferred from the pull-up driving unit  130 . The capacitor  140  represents the sum of capacitance comprising designed and parasitic capacitance electrically coupled to the internal node IN. 
         [0033]    The plurality of discharge units  150 _ 1  to  150 _N is coupled to the internal node IN. When one of the discharge units  150 _ 1  to  150 _N is selected, the selected one of the discharge units  150 _ 1  to  150 _N discharges the capacitor  140  through the internal node IN. Each of the discharge units  150 _ 1  to  150 _N includes one or more transistors N_ 1 &lt; 1 : 3 &gt; to N_N&lt; 1 : 3 &gt; coupled in series. Each of the transistors N_ 1 &lt; 1 : 3 &gt; to N_N&lt; 1 : 3 &gt; is a NMOS transistor serving as a diode having a drain and a gate coupled to each other. 
         [0034]    The discharge units  150 _ 1  to  150 N are coupled to the plurality of coupling units  160 _ 1  to  160 _N, respectively. The coupling units  160 _ 1  to  160 _N are coupled to a ground voltage VSS, and turned on/off in response to a plurality of select signals SEL&lt; 1 :N&gt;, respectively. The plurality of coupling units  160 _ 1  to  160 _N includes NMOS transistors N_ 1 &lt; 4 &gt; to N_N&lt; 4 &gt; coupled to corresponding discharge units  150 _ 1  to  150 _N at one end and to the ground voltage VSS, respectively. The NMOS transistors N_ 1 &lt; 4 &gt; to N_N&lt; 4 &gt; are turned on/off in response to the plurality of select signals SEL&lt; 1 :N&gt;, respectively. 
         [0035]    The control unit  170  selects all or part of the plurality of discharge units  150 _ 1  to  150 _N in response to select information SEL_INF, and generates the plurality of select signals SEL&lt; 1 :N&gt; to turn on/off the plurality of coupling units  160 _ 1  to  160 _N, respectively, in response to the voltage of the output node OUT. For example, when the voltage of the output node OUT is at the low level, the control unit  170  generates the select signals SEL&lt; 1 :N&gt; to turn off all of the coupling units  160 _ 1  to  160 _N, regardless of whether a corresponding one of the plurality of discharge units  150 _ 1  to  150 _N is selected. That is, the control unit  170  disables all of the select signals SEL&lt; 1 :N&gt;. Furthermore, when the voltage of the output node OUT is at the high level, the control unit  170  generates the select signals SEL&lt; 1 :N&gt; to turn on one or more of the plurality of coupling units  160 _ 1  to  160 _N corresponding to the selected one or more of the plurality of discharge units  150 _ 1  to  150 _N. That is, the control unit  170  enables the select signal SEL&lt; 1 &gt; and disables the select signals SEL&lt; 2 :N&gt;. 
         [0036]    Based on the above-described configuration, the operation of the oscillator to generate a periodic signal OSC will be described. The oscillator generates a periodic signal OSC having a predetermined period at the output node OUT. Hereafter, the case in which one discharge unit  150   — 1 among the plurality of discharge units  150 _ 1  to  150 _N is selected will be taken as an example. 
         [0037]    When the reference voltage VREF is higher than the internal voltage VIN, the comparison unit  110  outputs a signal having a high level as the comparison result A, and the voltage of the output node OUT becomes a low level. Since the period signal OSC is at the low level, the pull-up driving unit  130  is turned on, and the control unit  170  disables all the select signals SEL&lt; 1 :N&gt; to the low level to turn off all of the coupling units  160 _ 1  to  160 _N. Since all of the discharge units  150 _ 1  to  150 _N are deactivated, the internal voltage VIN gradually increases as the capacitor  140  is charged by the pull-up driving unit  130 . 
         [0038]    When the internal voltage VIN becomes higher than the reference voltage VREF, the output signal of the comparison unit  110  transitions from the high level to the low level and the periodic signal OSC transitions from the low level to the high level after a predetermined time has elapsed. Thus, the pull-up driving unit  130  is turned off, and the control unit  170  enables the select signal SEL&lt; 1 &gt; to the high level to turn on the coupling unit  160 _ 1  corresponding to the selected discharge unit  150 _ 1 , and disables the other select signals SEL&lt; 2 :N&gt;. Then, while the capacitor  140  is discharged through the selected discharge unit  150 _ 1  and the selected coupling unit  160 _ 1 , the internal voltage VIN gradually decreases. 
         [0039]    When the internal voltage VIN becomes lower than the reference voltage VREF, the output signal of the comparison unit  110  transitions from the low level to the high level and the periodic signal OSC transitions from the high level to the low level after a predetermined time has elapsed. Thus, the pull-up driving unit  130  is turned on, and the level of the internal voltage VIN increases in the same manner as described above. As such, the level of the periodic signal OSC oscillates according to the magnitude relation between the internal voltage VIN and the reference voltage VREF. The period of the periodic signal OSC varies depending on the delay value of the inverting unit  120 , the charge speed of the capacitor  140 , and the discharge speed of the discharge units  150 _ 1  to  150 _N. 
         [0040]    In particular, the period of the periodic signal OSC becomes shorter as the discharge speed of the discharge units  150 _ 1  to  150 _N increases, and becomes longer as the discharge speed of the discharge units  150 _ 1  to  150 _N decreases. The discharge ability of the discharge units  150 _ 1  to  150 _N is improved as the temperature increases, and degraded as the temperature decreases. Thus, the period of the periodic signal OSC generated by the oscillator of  FIG. 1  is adjusted according to the temperature. 
         [0041]    Furthermore, since the discharge speed of the capacitor  140  varies depending on the number of selected ones among the plurality of discharge units  150 _ 1  to  150 _N, the period of the periodic signal OSC is adjusted according to the number of selected discharge units. For example, when the number of selected discharge units is increased, the period of the periodic signal OSC becomes shorter, and when the number of selected discharge units is decreased, the period of the periodic signal OSC becomes longer. 
         [0042]      FIG. 2  is a circuit diagram illustrating a transistor included in an oscillator shown in  FIG. 1 . 
         [0043]    As illustrated in  FIG. 2 , parasitic capacitances C DS  and C GS  exist between the drain D and the source S and between the gate G and the source S in each of the transistors N_ 1 &lt; 1 : 3 &gt; to N_N&lt; 1 : 3 &gt; included in each of the discharge units  150 _ 1  to  150 _N. The parasitic capacitances C DS  and C GS  delay the charging of the capacitor  140 . Furthermore, the parasitic capacitances C DS  and C GS  of an unselected one among the plurality of discharge units  150 _ 1  to  150 _N delays the discharging of the capacitor  140 , which is performed by a selected one among the plurality of discharge units  150 _ 1  to  150 _N. That is, the charging and discharging of the capacitor  140  are delayed by the parasitic capacitances C DS  and C GS  existing in the discharge units  150 _ 1  to  150 _N, and the period of the periodic signal OSC due to the parasitic capacitances C DS  and C GS  becomes longer than the expected or intended period. 
         [0044]      FIG. 3  is a circuit diagram illustrating an oscillator in accordance with an exemplary embodiment of the present invention. 
         [0045]    As illustrated in  FIG. 3 , the oscillator may include a comparison unit  310 , an inverting unit  320 , a pull-up driving unit  330 , a capacitor  340 , a discharge unit  350 , a coupling unit  360 , and a pass gate  370 . 
         [0046]    The oscillator shown in  FIG. 3  may be the same as the oscillator described above with reference to  FIG. 1  except for the pass gate  370 . 
         [0047]    The oscillator of  FIG. 3  may include only one discharge unit  350  and the pass gate  370  coupled between the discharge unit  350  and an internal node IN. The pass gate  370  may electrically isolate the discharge unit  350  from the internal node IN when the discharge unit  350  does not discharge the capacitor  340 . The pass gate  370  may include an NMOS transistor NT and a PMOS transistor PT. The PMOS transistor PT and the NMOS transistor NT may be electrically coupled in parallel between the internal node IN and the discharge unit  350 . 
         [0048]    The coupling unit  360  and the pass gate  370  may be turned off when the voltage of the output node OUT is at the low level, and turned on when the voltage of the output node OUT is at the high level. For reference, a periodic signal OSC may be generated at the output node OUT. When the pass gate  370  is turned off, the pass gate  370  may electrically isolate the discharge unit  350  such that electric current does not flow into the discharge unit  350 , thereby preventing the influence of parasitic capacitances of transistors N&lt; 1 : 3 &gt;, which are included in the discharge unit  350 , on the period of the periodic signal OSC. 
         [0049]    When the pass gate  370  includes both of the NMOS and PMOS transistors as Illustrated in  FIG. 3 , it is more effective than when the pass gate  370  includes only one of the NMOS and PMOS transistors. The internal voltage VIN may toggle between the low level and the high level. Therefore, the internal node IN and the discharge unit  350  are effectively isolated from each other by the NMOS transistor NT when the internal voltage VIN is at the low level, or by the PMOS transistor when the internal voltage VIN is at the high level. 
         [0050]    The oscillator of  FIG. 3  may effectively block the influence of the parasitic capacitance of the discharge unit  350  on the period of the periodic signal OSC such that the periodic signal OSC has a precise period according to the temperature change as intended. In particular, the periodic signal OSC may have a shorter period at a specific temperature. 
         [0051]      FIG. 4  is a circuit diagram illustrating an oscillator in accordance with an exemplary embodiment of the present invention. 
         [0052]    As illustrated in  FIG. 4 , the oscillator may include a comparison unit  410 , an inverting unit  420 , a pull-up driving unit  430 , a capacitor  440 , a plurality of discharge units  450 _ 1  to  450 _N, a plurality of coupling units  460 _ 1  to  460 _N, a plurality of pass gates  470 _ 1  to  470 _N, and a control unit  480 . 
         [0053]    The oscillator of  FIG. 4  may be the same as the oscillator described with reference to  FIG. 1  except for the plurality of pass gates  470 _ 1  to  470 _N coupled between an internal node IN and the plurality of discharge units  450 _ 1  to  450 _N, respectively. 
         [0054]    Each of the plurality of pass gates  470 _ 1  to  470 _N may be the same as the pass gate  370  described above with reference to  FIG. 3  except for the control signal thereof. The pass gates  470 _ 1  to  470 _N may be turned on/off by select signals SEL&lt; 1 :N&gt;, respectively. The select signals SEL&lt; 1 :N&gt; may also control turn-on/off of the coupling units  460 _ 1  to  460 _N, respectively. The pass gates  470 _ 1  to  470 _N may include N number of pairs of NMOS transistors NT_ 1  to NT_N and PMOS transistors PT_ 1  to PT_N, respectively. Each pair of the PMOS transistors PT_ 1  to PT_N and the NMOS transistors NT_ 1  to NT_N may be electrically coupled in parallel between the internal node IN and a corresponding one of the plurality of discharge units  450 _ 1  to  450 _N. 
         [0055]    The pass gates  470 _ 1  to  470 _N may isolate unselected ones among the plurality of discharge units  450 _ 1  to  450 _N such that no electric current flows into the unselected discharge unit. Thus, when the capacitor  440  is charged or discharged through a selected one among the plurality of discharge units  450 _ 1  to  450 _N, the parasitic capacitance included in the plurality of discharge units  450 _ 1  to  450 _N may not affect the charge/discharge speed. Without the plurality of pass gates  470 _ 1  to  470 _N, when the capacitor  440  is charged, the parasitic capacitances of all the discharge units  450 _ 1  to  450 _N may affect the charge speed, and when the capacitor  440  is discharged, the parasitic capacitances of unselected discharge units may affect the discharge speed. 
         [0056]    The oscillator of  FIG. 4  may effectively block the influence of the parasitic capacitances of the discharge units  450 _ 1  to  450 _N on the period of the periodic signal OSC such that the periodic signal OSC has a precise period according to the temperature change as intended. In particular, the periodic signal OSC may have a shorter period at a specific temperature. 
         [0057]      FIG. 5  is a time vs. internal voltage graph Illustrating oscillators respectively shown in  FIGS. 1 and 4 .  FIG. 5  illustrates the internal voltage VIN depending on time (t) at a specific temperature. As an example, the number of discharge units selected in the oscillators of  FIGS. 1 and 4  are the same. 
         [0058]    Referring to  FIG. 5 , to represents the time at which a discharging operation of the discharge unit starts, and V INT  represents the internal voltage VIN at the start time to of the discharging operation. As illustrated in  FIG. 5 , the internal voltage VIN 1  of the oscillator described above with reference to  FIG. 1  is always higher than the internal voltage VIN 2  of the oscillator described above with reference to  FIG. 4 . 
         [0059]    It takes time (t 2 −t 0 ) for the oscillator of  FIG. 1  to drop the internal voltage from V INT  to VREF 1 , which is longer than the time (t 1 −t 0 ) for the oscillator of  FIG. 4  to drop the internal voltage from V NT  to VREF 1 . Therefore, the periodic signal generated by the oscillator of  FIG. 1  has a longer period than a periodic signal generated by the oscillator of  FIG. 4  under the same conditions of the reference voltage and the temperature. 
         [0060]    Furthermore, during time (t 1 −t 0 ), the internal voltages of the oscillators of  FIGS. 1 and 4  reach the levels of VREF 1  and VREF 2  (VREF 2 &gt;VREF 1 ), respectively. Therefore, the reference voltage of the oscillator of  FIG. 1  should use a reference voltage higher than that of the oscillator of  FIG. 4  for the same period of the periodic signals under the same temperature conditions. 
         [0061]    The higher the reference voltage is, the worse the temperature-period change characteristics of the transistors included in the discharge unit become. The higher the reference voltage is, the less sensitive the period of the periodic signal becomes to changes in temperature. Thus, the oscillator of  FIG. 4  may effectively generate periodic signal that are more responsive to changes in temperature. 
         [0062]      FIG. 6  is a block diagram illustrating a memory device in accordance with an exemplary embodiment of the present invention. 
         [0063]    As illustrated in  FIG. 6 , the memory device may include a command input unit  610 , a command decoder  620 , a mode setting unit  630 , a first periodic signal generation unit  640 , a second periodic signal generation unit  650 , an address counting unit  660 , a control unit  670 , and a cell array  680 . The cell array  680  may include a plurality of word lines WL each coupled to one or more memory cells MC. 
         [0064]    Referring to  FIG. 6 , the memory device will be described. 
         [0065]    The command Input unit  610  may receive command signals CMDs. The command signals CMDs may include multi-bit signals. The command decoder  620  may decode the command signals CMDs received through the command input unit  610 , and generate a refresh command REF, a self-refresh entry command ENTRY, and a self-refresh exit command EXIT. The command decoder  620  may enable a command indicated by a combination of the input command signals CMDs, among the refresh command REF, the self-refresh entry command ENTRY, and the self-refresh exit command EXIT. 
         [0066]    The mode setting unit  630  may set a self-refresh mode of the memory device. The mode setting unit  630  may control the memory device to enter the self-refresh mode in response to the self-refresh entry command ENTRY, and control the memory device to exit from the self-refresh mode in response to the self-refresh exit command EXIT. For this operation, the mode setting unit  630  may enable a self-refresh mode signal SELF_MODE indicating the self-refresh mode in response to the self-refresh entry command ENTRY, and disable the self-refresh mode signal SELF_MODE in response to the self-refresh exit command EXIT. 
         [0067]    The first periodic signal generation unit  640  may generate a first periodic signal OSC 1  having a fixed period when the self-refresh mode signal SELF_MODE is enabled. The fixed period may be constant regardless of temperature changes in the memory device. 
         [0068]    The second periodic signal generation unit  650  may generate a second periodic signal OSC 1  having a period varying according to the temperature when the self-refresh mode signal SELF_MODE is enabled. The second periodic signal generation unit  640  may include the oscillator of  FIG. 3  or  4 . The self-refresh period may be determined according to the temperature, and the oscillator of  FIG. 3  or  4  may adjust the self-refresh period thereof with more precision according to the temperature, thereby improving the characteristics of the self-refresh period of the memory device according to the temperature. The period of the second periodic signal OSC 2  may become shorter as the temperature increases, or become longer as the temperature decreases. Although not illustrated in  FIGS. 3 and 4 , the comparison units  310  and  410  and the control unit  470  may receive the self-refresh mode signal SELF_MODE. The comparison units  310  and  410  and the control unit  470  may be activated to perform the above-described operations in response to the enabled self-refresh mode signal SELF_MODE, or may be deactivated in response to the disabled self-refresh mode signal SELF_MODE. 
         [0069]    The control unit  670  may refresh the cell array  680  in response to the refresh command REF. In this case, the control unit  670  may refresh the cell array  680  according to the shorter period between the first and second periodic signals OSC 1  and OSC 2  in the self-refresh mode, when the self-refresh mode signal SELF_MODE is enabled. 
         [0070]    For the above-described operations, the control unit  670  may include a self-refresh signal generator  671 , a refresh signal generator  672 , and a word line controller  673 . When the self-refresh mode signal SELF_MODE is enabled, the self-refresh signal generator  671  may compare the first and second periodic signals OSC 1  and OSC 2 , and enable a self-refresh signal SELF at the period corresponding to the periodic signal having a shorter period. For reference, the period of the self-refresh signal SELF may be equal to or divided from the shorter period between the first and second periodic signals OSC 1  and OSC 2 . The refresh signal generator  672  may enable a refresh signal REFP in response to the refresh command REF. When the self-refresh mode signal SELF_MODE is enabled, the refresh signal generator  672  may enable the refresh signal REFP in response to the self-refresh signal SELF. When the refresh signal REFP is enabled, the word line controller  673  may refresh a word line WL corresponding to a counting address CNT_ADD. 
         [0071]    The address counting unit  660  may generate the counting address CNT_ADD, and change the value of the counting address CNT_ADD whenever the refresh signal REFP is enabled. The address counting unit  660  may increase the value of the counting address CNT_ADD by 1 whenever the refresh signal REFP is enabled. When the value of the counting address CNT is increased by 1, it may indicate that the counting information is changed so that when a Kth word line WLK was selected at the previous time, a (K+1)th word line is selected this time. 
         [0072]    When the memory device in not in the self-refresh mode, the memory device may sequentially refresh the plurality of word lines WL included in the cell array  380  in response to the refresh command REF. In the self-refresh mode, the memory device may sequentially refresh the plurality of word lines WL in response to the self-refresh signal SELF. 
         [0073]      FIG. 7  is a temperature vs. refresh period graph illustrating a memory device using oscillators respectively shown in  FIGS. 1 and 4 .  FIG. 7  shows the self-refresh period (t) of the memory device depending on the temperature T. 
         [0074]    Referring to  FIG. 7 , a first graph L 1  Illustrates the self-refresh period according to the oscillator of  FIG. 1 , and a second graph L 2  illustrates the self-refresh period according to the oscillator of  FIG. 2 . 
         [0075]    The self-refresh period may be determined according to the period of the periodic signal having a shorter period between the first and second periodic signals OSC 1  and OSC 2  of  FIG. 6 . Thus, when the temperature of the memory device corresponds to a predetermined temperature T 1  or T 2 , the self-refresh period may be determined by the first period signal OSC 1 . Thus, as indicated by t max , the self-refresh period is constant below the predetermined temperature T 1  or T 2 . However, when the temperature of the memory device becomes equal to or more than the predetermined time T 1  or T 2 , the self-refresh period may be determined by the second periodic signal OSC 2 . Thus, the self-refresh period may decrease as the temperature increases. 
         [0076]    In the case of the dotted line L 1 , the period change of the periodic signal OSC generated by the oscillator is relatively insensitive to temperature, that is, the slope of the period change is small. Thus, the period of the periodic signal OSC may be determined by the second periodic signal OSC 2  from the relatively low temperature T 1 . Therefore, the self-refresh period starts to become shorter from the relatively low temperature T 1 . 
         [0077]    In the case of the solid line L 2 , the period change of the periodic signal OSC generated by the oscillator is relatively sensitive to temperature, that is, the slope of the period change is large. Thus, the period of the periodic signal OSC may be determined by the second periodic signal OSC 2  from the relatively high temperature T 2 . Therefore, the self-refresh period starts to become shorter from the relatively low temperature T 2 . 
         [0078]    When the self-refresh period becomes shorter, current consumption and power consumption of the memory device, required to perform a refresh operation, may increase. Furthermore, when the self-refresh period is not sufficiently responsive to temperature, changes in retention time of the memory cell MC may not be compensated according to temperature and data may be lost. The memory device using the oscillator of  FIG. 3  or  4  may properly change the self-refresh period according to temperature, thereby properly compensating for changes in retention time of the memory cell MC depending on the temperature change of the memory device, while at the same time minimizing current and power consumption. 
         [0079]      FIG. 8  is a circuit diagram illustrating an oscillator in accordance with an exemplary embodiment of the present invention. 
         [0080]    As illustrated in  FIG. 8 , the oscillator may include a comparison unit  810 , an inverting unit  820 , a pull-up driving unit  830 , a capacitor  840 , a plurality of discharge units  850 _ 1  to  850 _N, a plurality of selecting elements  860 _ 1  to  860 _N, and a control unit  870 . 
         [0081]    The comparison unit  810 , the inverting unit  820 , the pull-up driving unit  830 , and the capacitor  840  may be configured and operated in the same manner as the comparison unit  110 , the inverting unit  120 , the pull-up driving unit  130 , and the capacitor  140 , which have been described with reference to  FIG. 1 . 
         [0082]    The plurality of discharge units  850 _ 1  to  850 _N may be coupled to an internal node N. When each of the discharge units  850 _ 1  to  850 _N is selected, the discharge unit may discharge the capacitor  840  when the voltage of the internal node IN becomes higher than a predetermined voltage. Each of the discharge units  850 _ 1  to  850 _N may include one or more diodes DIODE coupled in series. At this time, each of the diodes DIODE may include the NMOS transistor NT of which the drain D and the gate G are coupled to each other. That is, each of the discharge units  850 _ 1  to  850 _N may be configured in such a manner as indicated by TYPE 1  or TYPE 2 . The discharges of the discharge units  850 _ 1  to  850 _N to discharge the internal node IN may differ depending on the temperature. The plurality of discharge units  850 _ 1  to  850 _N may have the same relation between temperature and discharge, or one or more of the discharge units  850 _ 1  to  850 _N may have a different relation between temperature and discharge. 
         [0083]    The plurality of selecting elements  860 _ 1  to  860 _N may be turned on when the corresponding discharge units  850 _ 1  to  850 _N are selected, and coupled between the corresponding discharge units  850 _ 1  to  850 _N and the internal node IN or coupled between the corresponding discharge units  850 _ 1  to  850 _N and a discharge terminal  801 .  FIG. 8  illustrates the case in which the plurality of selecting elements  860 _ 1  to  860 _N are NMOS transistors NT_ 1  to NT_N coupled between the corresponding discharge units  850 _ 1  to  850 _N and the internal node IN. 
         [0084]      FIGS. 9A to 9C  are circuit diagrams illustrating oscillators in accordance with exemplary embodiments of the present invention. The plurality of selecting elements  860 _ 1  to  860 _N may include pass gates PG_ 1  to PG_N coupled between the internal node IN and the corresponding discharge units  850 _ 1  to  850 _N as illustrated in  FIG. 9A , NMOS transistors NT_ 1  to NT_N coupled between the discharge terminal  801  and the corresponding discharge units  850 _ 1  to  850 _N as illustrated in  FIG. 9B , or pass gates PG_ 1  to PG_N coupled between the discharge terminal  801  and the corresponding discharge units  850 _ 1  to  850 _N as illustrated in  FIG. 9C , respectively, depending on design. Alternatively, the plurality of selecting elements  860 _ 1  to  860 _N may include PMOS transistors coupled between the internal node IN and the corresponding discharge units  850 _ 1  to  850 _N or PMOS transistors coupled between the discharge terminal  801  and the corresponding discharge units  850 _ 1  to  850 _N, respectively. As such, the positions and types of the plurality of selecting elements may be designed in various manners. 
         [0085]    The plurality of selecting elements  860 _ 1  to  860 _N may be turned on when the corresponding select signals among the plurality of select signals SEL&lt; 0 :N&gt; are enabled to the high level. When the plurality of selecting elements  860 _ 1  to  860 _N are turned on, the internal node IN may be discharged when the voltage of the internal node IN increases to a predetermined level or more. In  FIGS. 9A and 9C , the select signals corresponding to the pass gates PG_ 1  to PG_N may include the select signals SEL&lt; 0 :N&gt; and select signals SELB&lt; 0 :N&gt; obtained by inverting the select signals SEL&lt; 0 :N&gt;. 
         [0086]    When the select signals SEL&lt; 0 :N&gt; are enabled, the select signals SEL&lt; 0 :N&gt; may have the high level, and when the select signals SELB&lt; 0 :N&gt; are enabled, the select signals SELB&lt; 0 :N&gt; may have the low level. 
         [0087]    The control unit  870  may select one or more discharge units among the plurality of discharge units  850 _ 1  to  850 _N in response to temperature information TEMP_INF. The control unit  870  may enable select signals corresponding to discharge units selected among the plurality of discharge units  850 _ 1  to  850 _N. The control unit  870  may select a larger number of discharge units as the temperature increases or select a smaller number of discharge units as the temperature decreases, according to the temperature information TEMP_INF. For example, suppose that the oscillator includes three discharge units and reference temperatures are represented by T 1  and T 2  (T 2 &gt;T 1 ). Referring to the temperature information TEMP_INF, the control unit  870  may select only one discharge unit  850 _ 1  when the current temperature is lower than the reference temperature T 1 , select two discharge units  850 _ 1  and  850 _ 2  when the current temperature is higher than the reference temperature T 1  and lower than the reference temperature T 2 , or select three discharge units  850 _ 1  to  850 _ 3  when the current temperature is higher than the reference temperature T 2 . 
         [0088]    Since the discharge ability of the diode DIODE differs depending on the temperature, the period of the periodic signal OSC outputted to the output node OUT may be changed according to the temperature. In particular, since the number of selected discharge units differs on the basis of the reference temperatures T 1  and T 2 , the functional relation between the temperature and the period of the periodic signal OSC may differ at the left and right of the reference temperatures T 1  and T 2 . For example, suppose that the oscillator includes three discharge units and the number of discharge units selected among three discharge units differs at the left and right of the reference temperatures T 1  and T 2 . Therefore, the temperature-period function when the current temperature T is lower than the reference temperature T 1  (T&lt;T 1 ), the temperature-period function when the current temperature is higher than the reference temperature T 1  and lower than the reference temperature T 2  (T 2 &gt;T&gt;T 1 ), and the temperature-period function when the current temperature T is higher than the reference temperature (T&gt;T 2 ), may differ. 
         [0089]    Through the above-described configuration and operation, the oscillator may adjust the period according to the temperature. The second periodic signal generation unit  640  of the memory device of  FIG. 6  may include the oscillator of  FIG. 8 ,  9 A,  9 B, or  9 C. Using the oscillator, the memory device may divide the entire section into a plurality of sections (for example, section of T&gt;T 1 , section of T 2 &gt;T&gt;T 1 , and section of T 2 &lt;T), and properly adjust the self-refresh period in each section, according to the temperature. 
         [0090]    In accordance with the embodiments of the present invention, the oscillator may effectively isolate capacitance generated by the internal components of the circuit, and generate a periodic signal which precisely oscillates at a period determined according to temperature. 
         [0091]    Furthermore, the memory device may minimize power consumption while optimizing the self-refresh period according to temperature, using the above-described oscillator. 
         [0092]    Although various embodiments have been described for Illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.