Abstract:
The method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using an exposure mask having the corrected mask pattern.

Description:
BACKGROUND 
       [0001]    In a process technique of a semiconductor integrated circuit, with the advancement in microfabrication, a mask technique has become significant, in addition to an exposure technique, in order to form a pattern with a width not more than a wavelength of light. When a Numerical Aperture (NA) is increased for forming a micropattern, a Depth Of Field (DOF) is reduced, so that the affect of a base is non-negligible when forming a pattern. For example, the variation in the width of a gate electrode, which is caused by a step of the base, significantly appears in an operation speed of a transistor or leak current, which affects the transistor performance. Therefore, a pattern that is to be actually formed is generally simulated and evaluated with the use of a mask pattern, in order to form a desired width of a gate electrode. 
         [0002]    As semiconductor devices have been using finer patterns due to higher integration these days, the influence of an optical proximity effect appears greatly in an exposure process, making it difficult to manufacture semiconductor devices according to the design data. To prevent this from occurring, Optical Proximity Correction (OPC) technique for correcting a circuit pattern in design data has been generally employed by obtaining the influence of the optical proximity effect in order to obtain dimensions as designed. 
         [0003]    When acquiring data for OPC, a substrate having no step of a Shallow Trench Isolation (STI) is generally employed. The substrate has no active region or no device isolation. An oxide film, polysilicon film and insulating film based hard mask material are laminated on a flat substrate, a reflection preventing film and a resist are applied thereon, and the resultant is transferred and etched with a mask having a test pattern according to various sizes such as line/space. Then, the size data after the processing is measured. A model equation is derived over the basis of this measured data and the optical simulation so as to perform a correction of a mask pattern. Specifically, the same correction is executed, regardless of a type of a transistor, and further, the difference in the size of an active region is not considered. 
         [0004]    As represented by a transistor having different power supply voltage, a difference is produced in a retreat amount of the oxide film, for example High Density Plasma (HDP) oxide film, embedded into the STI region due to the difference in the type of ion of implanted impurity, the dosage, or the number of times of wet process. The same problem arises in the process of forming multi-gate oxide transistors. Further, the step varies depending upon the size of the active region even in transistors of the same type. As a result, there is a difference between an actual product and the result of the simulation. 
         [0005]    Specifically, suppose the case in which an active region is formed so as to project from an STI region. The STI region has a buried insulating film  102  as shown in  FIG. 1B . When the gate width (W width) or source-drain width (SD width) of the active region  110  on a silicon substrate  101  is different, as shown in  FIG. 1B , in the active region  110  divided by the W width and the SD width over a source (S) region and a drain (D) region shown in  FIG. 1A , the thickness of a gate oxide film  103  or a sacrificial oxide film that is to be formed varies. The reason for this is because, when the oxide film is formed, the oxidation rate in the direction of the side wall is faster, and hence, the thicker oxide film is formed in the active region with the narrow W width, compared to the active region with the wide W width, for example. 
         [0006]    As shown in  FIG. 2 , the following wet process, for example hydrofluoric acid treatment process, makes a sinking amount of the active region  110  different due to the difference in the W width or the SD width of the active region  110 , so that the variation of the step increases. As shown in  FIGS. 3A and 3B , this step affects the application state of a reflection preventing film  105  on a gate electrode film  104  in the next gate forming process, with the result that the thickness of the reflection preventing film  105  or, depending on the situation, the thickness of the resist  106  becomes non-uniform. As a result, the DOF or reflectivity varies, whereby the non-uniform size depending upon the width of the active region is produced in the patterning for forming the gate electrode  108 . 
         [0007]    A trimming technique has recently been used in an etching in order to process a gate electrode having a smaller size than the size of the patterning. The difference in the thickness of the reflection preventing film  105  affects an etching shift amount by the trimming of the reflection preventing film  105 . When the thickness of the reflection preventing film  105  differs according to the step, the etching shift of the gate electrode  108  in the processing is very likely to differ at various parts. 
         [0008]    It is difficult, from the viewpoint of a process flow, to improve the step between the device isolation region and the active region for every type of transistor. Therefore, the influence by this step becomes a significant subject. 
       SUMMARY 
       [0009]    According to an aspect of the invention, the method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using an exposure mask having the corrected mask pattern. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIGS. 1A and 1B  are views showing an example of a step due to a difference in a W width of an active region; 
           [0011]      FIG. 2  is a view showing another example of a step due to a difference in a W width of an active region; 
           [0012]      FIGS. 3A and 3B  are schematic views showing a variation in a patterning width caused by a difference in a thickness of a reflection preventing film, which is caused by a step; 
           [0013]      FIG. 4  is a flowchart showing a correction of a mask pattern in a manufacturing process of a semiconductor device according to one embodiment of the present invention; 
           [0014]      FIG. 5  is a flowchart showing an example of acquiring correction data in a correction data acquiring step in  FIG. 4 ; 
           [0015]      FIG. 6  is one example of an L/S monitor pattern table that specifies a correction value for every L/S monitor pattern; 
           [0016]      FIG. 7  is one example of correction table considering the variation in a size of an active region used for correcting input design data; 
           [0017]      FIG. 8  is a view showing a difference of a step caused by a difference of a type of a transistor; 
           [0018]      FIG. 9  is a flowchart showing a correction of a mask pattern when fabricating a semiconductor device having transistors of different types mixedly mounted thereto; and 
           [0019]      FIG. 10  is a flowchart showing a correction for executing only a model-based OPC using the correction data considering the size of the active region. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    Considering the situation in which transistors of different types are mixedly mounted or the diversification of the size of the active region, the design of the step of the STI becomes more significant, and two points described below may be considered as new subjects. First, the step between the active region and the STI region differs for every type of transistor mixedly mounted. Second, even in the transistors of the same type, variation in the oxidation amount according to the change of the size in the active region is produced in an oxide film formation process depending on the design of the step between the active region and the STI, so that the step also differs. 
         [0021]    In the present embodiment, correction data on which at least one of several types of transistors mixedly mounted to a wafer and a difference in a size of an active region is reflected is acquired and generated, so as to perform an OPC to a mask pattern. A size of a pattern actually formed is made uniform by using the correction data that considers a variation in a step due to a difference in types of transistors or the difference in the size of the active region. 
         [0022]    The correction data is acquired in such a manner that various patterns, for example line and space patterns, for a size of the active region are formed, and the difference from the design value is measured. Alternatively, the correction data is acquired by repeating this process for a type of transistor. 
         [0023]    The OPC data correction is performed for the type of the transistor or the size of the active region, whereby the correction of a mask pattern can be carried out that considers the variation in the size of the gate electrode in the patterning caused by the variation in the thickness of the reflection preventing film, caused by the step or the variation in an etching shift amount. 
         [0024]    By using the photomask whose pattern is thus corrected, the difference between the size of the gate electrode actually formed and the design value is absorbed, whereby a highly-precise gate size can be obtained under an environment where a step amount exists.  FIG. 4  is a flowchart showing a correction of a mask pattern in a fabrication process of a semiconductor device according to the embodiment. 
         [0025]    Firstly, design data of a mask pattern is input to a data processing apparatus at step S 11 . This design data is, for example, layout data of each layer of a semiconductor device having different types of transistors mixedly mounted thereto. 
         [0026]    At step S 12 , first correction data considering an etching shift and a size of an active region is acquired, and at step S 13 , a rule-based OPC is performed by using this correction data. The method of acquiring the first correction data will be described in detail with reference to  FIG. 5 . At step S 14 , second correction data considering that the lithography is acquired, and at step S 15 , a model-based OPC is performed using this correction data. At step S 16 , exposure data is created from the design data after the OPC processing so as to produce a photomask based upon the exposure data. At step S 17 , a pattern exposure is actually carried out by using the produced photomask to form a pattern of the semiconductor device on a wafer. 
         [0027]    In the example of the correction of the mask pattern, the rule-based OPC in the step S 13  and model-based OPC in the step S 15  are carried out. A general rule-based OPC is a method of correcting the input design data on the basis of a correction amount according to a line width (L) of a circuit pattern or a distance (S) to the adjacent circuit pattern. The model-based OPC is a method of correcting the mask pattern by using an optical-intensity simulation, and it is suitable for the correction of a circuit pattern having a complicated shape for which the correction by the rule-based OPC is difficult. 
         [0028]    In the rule-based OPC in the present embodiment, not only the correction amount according to only the change in the circuit pattern is used as the correction data, but also the correction amount considering the change in the size of the active region is acquired and used as the correction data. 
         [0029]      FIG. 5  is a flowchart showing a process of acquiring the first correction data executed at step S 12  in  FIG. 4 . Firstly, at step S 21 , line-width data of the lithography is acquired for each of various combinations referred to as L/S monitor pattern of the line width and the distance (S). At step S 22 , the line width after the actual etching processing is measured for each of the L/S monitor patterns. At step S 23 , the difference between the line-width data and the measured value after the etching is obtained for each of the L/S monitor patterns, and the obtained difference is defined as an etching shift amount. 
         [0030]    At this stage, an L/S monitor pattern table  41  shown in  FIG. 6  is created. In each entry of the L/S monitor pattern table  41  in  FIG. 6 , the measured value, measured at step S 22 , of the gate line width after the etching may be recorded as a correction value instead of the etching shift amount calculated at step S 23  or together with the etching shift amount. In the rule-based OPC, when the adjacent circuit patterns are separated from each other by a fixed distance, for example, the width of the circuit pattern is increased, or when the adjacent circuit patterns are close to each other, the width of the circuit pattern is reduced, according to the correction value specified on the L/S monitor pattern table  41 . 
         [0031]    Subsequently, in the present embodiment, a monitoring in which active regions, hereinafter referred to as SD/W pattern, whose SD width and W width are changed in various ways are arranged immediately below the gate in order to employ the size, for example W width or SD width, of the active region, which is the base, as a parameter of the correction. 
         [0032]    At step S 24  in  FIG. 5 , a wafer is prepared in which STI is formed such that active regions having various sizes used for monitoring are sectioned, the processing at steps S 21  to S 23  is performed for each of the active regions having different sizes so as to form a monitor pattern and perform a pattern measurement, whereby a correction table  42  shown in  FIG. 7  is created. The correction table  42  is formed such that the L/S monitor pattern table  41  shown in  FIG. 6  is taken into each entry of an SD/W matrix in order to reflect the affect of the base on the correction of the L/S monitor patterns. Since the change in the size of the active region is reflected on each gate pattern, the correction data considering the affect of the step due to the size of the active region can be obtained. 
         [0033]    In the present embodiment, steps S 21  to S 24  are repeated for each of different types of transistors at step S 25  in order to correct the step for each of different types of transistors mixedly mounted to the wafer, thereby creating the correction table  42  for every type of transistors. The table in  FIG. 8  illustrates the step of the STI. In the case of a core transistor, an oxide film embedded into a device isolation trench is recessed lower than the active region, so that when the active region is defined as a reference, a negative step S is produced. In the case of a high breakdown voltage transistor, a positive step S that protrudes from the active region appears. The step amount is different depending upon NMOS or PMOS, even in the same core transistor or the same high breakdown voltage transistor. In view of this, the correction table  42  shown in  FIG. 7  is created for every type of transistor including a conductive type, so as to correct the design data input on the basis of the correction data. It is to be noted that, when the degrees of the steps of the STI are the same or when there is little difference in the steps of the STI, the correction table  42  may be shared between two or more types of transistors. 
         [0034]    In  FIG. 4 , a model-based OPC is carried out subsequent to the rule-based OPC using the correction table  42  in the embodiment. In this example, the model-based OPC uses the correction data considering only the lithography. The reason for this is because, since the model-based correction is the correction on the basis of the optical-intensity simulation, it becomes difficult to perform the correction to the process factor other than the lithography, for example etching shift amount indicating the influence by the etching. 
         [0035]      FIG. 9  is a modification of a flow of the pattern correction in  FIG. 4 , wherein the process flow in  FIG. 4  is applied to the correction of a mask pattern for a wafer having different types of transistors mixedly mounted thereto. At step S 31 , design data is input to a data processing apparatus, and at step S 32 , the type of the transistor that is the subject of the correction is detected. At step S 33 , a correction table  42  according to the detected type of the transistor is read out. At step S 34 , the rule-based OPC is performed using the correction table  42 . Since the correction amount for each of the SD/W patterns according to the size of the active region of the base is specified in the correction table  42  in addition to the correction amount for each of the L/S monitor patterns as described above, the type of the transistor, the size of the active region, and the etching shift amount are all reflected on the rule-based OPC performed at step S 34 . 
         [0036]    Thereafter, at step S 35 , the model-based OPC is performed using the correction data considering the lithography, for example. Exposure data is generated at step S 36  for creating a photomask. Finally, an exposure is carried out using the created photomask so as to form a pattern of a semiconductor device on the wafer at step S 37 . 
         [0037]      FIG. 10  is another modification of a flow of the pattern correction in  FIG. 4 . In this modification, only the model-based OPC is carried out. When performing the model-based OPC, the correction data considering the lithography, etching shift, and the size of the active region is used. Specifically, the correction data acquired at step S 42  is used to the design data of the mask pattern input at step S 41  for performing the model-based OPC at step S 45 . The correction data acquired at step S 42  is, for example, the one in which the line-width data of the lithography for each of the L/S patterns obtained at step S 21  in  FIG. 5  and the etching shift amount for each of the L/S patterns obtained at step S 23  are taken into each box of the correction table  42  in  FIG. 7 . 
         [0038]    Subsequently, exposure data is generated at step S 46  from the design data after the model-based OPC processing so as to create a photomask. At step S 47 , an exposure is carried out using the created photomask, thereby forming a pattern composing a semiconductor device on the wafer. 
         [0039]    This correction method is advantageous because it can cope with the correction of a micropattern with one OPC processing. When this correction is performed to the mask pattern of a wafer having different types of transistors mixedly mounted thereto, the type of the transistor, which is the subject of the correction at this time, is detected, and the correction table according to the detected type is read so as to perform the model-based OPC as illustrated in steps S 32  and S 33  in  FIG. 9 . 
         [0040]    Finally, the formation of the monitor pattern for acquiring the correction data in the aforesaid pattern correction method will be explained. The correction data can be acquired by mounting a monitor for acquiring the correction data to a real device evaluation mask. On the other hand, one type of the mixedly mounted transistors is manufactured on the whole surface of each wafer with the test mask for the L/S monitor pattern, in order to acquire data. Alternatively, a full-process mask set for a test evaluation may be prepared so as to acquire the correction data. Further, a series of pattern sets are arranged for every possible type of mixedly mounted transistors, and the pattern sets may be transferred and subject to an etching processing so as to acquire the correction data. 
         [0041]    The monitor pattern for acquiring the correction data is mounted to the device evaluation mask for every type of mixedly mounted transistors. The measuring monitor to be used is the combination of those shown in  FIGS. 6 and 7  on which all types of the mixedly mounted transistors are reflected. 
         [0042]    In the test mask for acquiring the OPC data, a mask pattern whose data is corrected in accordance with the size of the active region is formed for every type of transistor, and the monitor pattern of one of the types of the mixedly mounted transistors is processed and formed for every wafer to measure the etching shift. Only the combination of  FIGS. 6 and 7  is considered in each wafer. In this case, the number of measured wafers becomes the number of types of the mixedly mounted transistors, whereby the number of the masks is reduced, although the number of the processed wafers is increased. 
         [0043]    In the test mask for acquiring the OPC data, a reticle for ion implantation is also formed, and the correction data for every type of mixedly mounted transistor is acquired with the full-process mask set whose number is the same as the number of the device samples. The measuring monitor to be used is the combination of those shown in  FIGS. 6 and 7  on which all types of the mixedly mounted transistors are reflected. 
         [0044]    According to the technique described above, the correction of the OPC data for every type of mixedly mounted transistor and every size of an active region, which have not been considered in a conventional correction technique, can be performed. As a result, a pattern correction considering the variation in the patterning size due to the variation in thickness of a reflection preventing film caused by a step or a variation in an etching shift amount can be executed.