Abstract:
A data driver circuit which enables the square measure of the non-display areas of image display devices to be reduced is to be provided. The driver circuit has two DA converters which convert the digital signals, in accordance with more significant bits thereof, into analog voltages; a voltage divider which divides the output voltages of the two DA converters in accordance with less significant bits of the signals; and a shift register which generates trigger signals in synchronism with the digital signals. The voltage divider, arranged in the gap between the two DA converters, comprises memory elements arrayed in two-dimensional matrixes, and a plurality of resistive wirings. The memory elements store decoded signals generated by the decoders in synchronism with the trigger signals, and selectively supply, in accordance with the decoded signals stored by the memory elements, the divided voltages which derive from the two DA converters and are generated on the resistive wirings.

Description:
CLAIM OF PRIORITY  
       [0001]     The present application claims priority from Japanese application JP 2004-336950, filed on Nov. 22, 2004, the content of which is hereby incorporated by reference into this application.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to an image display device and the driver circuit thereof, and more particularly to an image display device wherein the square measure of a non-display area is reduced by narrowing the width of a data driver circuit arranged in the non-display area of the image display device, and the driver circuit thereof.  
       BACKGROUND OF THE INVENTION  
       [0003]     In an active matrix type display, typically an active matrix type liquid crystal display, a thin film transistor (TFT) is formed in each pixel, and display information is stored on a pixel-by-pixel basis to display images. A TFT formed by using a polysilicon film which is fabricated by polycrystallization of an amorphous silicon film by laser annealing, with its mobility being raised to about 100 cm2/V·S is called a polysilicon TFT. Since a circuit configured of such polysilicon TFTs operates with signals of a few MHz to dozens of MHz, not only pixels but also a data driver circuit generating image signals and a driver circuit which has the scanning function of a gate driver circuit can be formed on the substrate of a liquid crystal display device or the like in the same process as the formation of the TFTs constituting the pixels.  
         [0004]     The data driver circuit supplies an analog-signal voltage containing image signal information to a plurality of data lines. The data lines in this context are wires running in the vertical direction within the display screen of the image display device, and supply each pixel with an analog signal voltage.  
         [0005]     The data driver circuit requires the following functions.  
         [0006]     (1) A function to convert digital signals into analog voltages, namely the function of a DA converter. Where input image signals supplied from outside the image display device include many digital signals, it is preferable to build this function into the device.  
         [0007]     (2) A function to distribute analog signal voltages. This is required because there are a plurality of data lines (usually as many as pixels in the horizontal direction of the frame).  
         [0008]      FIG. 11  shows an example of configuration of a conventional data driver circuit. The data driver circuit comprises a decoder (DEC)  81 , a shift register (SREG)  82  and a switch matrix  83 . In the switch matrix  83 , memory elements  84  each consisting of N-channel TFTs  85  and  86  and one capacitor  87  are arranged in a matrix form, and connected to one another by a plurality of decoded signal lines  88 , a plurality of trigger lines  89 , a plurality of reference voltage lines  90  and a plurality of output lines  91 . The decoded signal lines  88  are connected to the output of the decoder  81 , the trigger lines  89  to the shift register  82 , the reference voltage lines  90  to external reference voltage lines Vref 1  through Vrefx, and the output lines  91 , to the data lines of the image display device.  
         [0009]     The operation of the data driver circuit shown in  FIG. 11  will be briefly described below. Digital image signals DSIG supplied from outside are decoded by the decoder  81 , and supplied to the decoded signal lines  88 . One of the decoded signal lines  88  relates to the entered digital image signal DSIG and takes on a sufficiently high voltage (hereinafter abbreviated to the H level) to turn ON the N-channel TFT, and the remaining ones take on a sufficiently low voltage (hereinafter abbreviated to the L level) to turn OFF the N-channel TFT. The shift register  82  successively raises one or another of the trigger lines  89  to the H level in synchronism with the input timings of the digital image signals DSIG.  
         [0010]     On one column of the memory elements  84  connected to a trigger line  89  at the H level, as the TFT  85  is turned ON, the decoded signal on a decoded signal line  88  is latched into the capacitor  87 . Out of the decoded signal lines  88 , only one corresponding to the digital image signal DSIG is at the H level, and accordingly the capacitor  87  connected to that decode line samples the H level. Then, the TFT  86  to be connected to the capacitor  87  having sampled the H level is turned ON, and that TFT  86  selects one of the reference voltages Vref 1  through Vrefx of the reference voltage lines  90  to be connected and outputs it to the output line  91 . The reference voltage supplied to the output lines  91  is further fed to a data line of the image display device (not shown).  
         [0011]     The operation described above causes the circuit of  FIG. 11  (1) to convert digital image signals into corresponding voltage signals and (2) to distribute the voltage signals among the plurality of data lines, and is thereby enabled to perform its above-stated functions as a data driver circuit.  
         [0012]     Examples of the circuit shown in  FIG. 11  are also described in detail in Patent Document 1 and Patent Document 2. One of the features of the circuit shown in  FIG. 11  is that, since the configuration requires merely the wiring of two lines per output in the longitudinal direction of the drawing, the circuit width per output can be narrowed, enabling the circuit to be applied to finer image display devices.  
         [0013]     Patent Document 1: Japanese Patent Laid-Open No. 2003-005716  
         [0014]     Patent Document 2: Japanese Patent Laid-Open No. 2004-085666  
       SUMMARY OF THE INVENTION  
       [0015]     The conventional data driver circuit shown in  FIG. 11  requires as many stages of the memory elements  84  constituting the switch matrix  83  in the longitudinal direction of the drawing as the number of display gradations. Therefore, when the number of bits of each digital image DSIG entered from outside is four, 16 stages, when the number of bits is six, 64 stages, or when the number of bits is eight, 256 stages are required. Thus, the required number of stages increases in proportion to the power of 2 by the number of bits, with a corresponding increase in the circuit width W 1  of the switch matrix.  
         [0016]     Especially where the number of gradations is eight or more, if the pitch of the memory elements  84  in the longitudinal direction of the drawing is 30 μm, the circuit width W of the switch matrix  83  by itself will occupy 7.68 mm. Since the circuit width W 1  has to be accommodated in the non-display area of the image display device, a greater width W 1  would invite an increase in the non-display area of the image display device, and this means a constraint to the freedom of designing the shape of products to be mounted on the image display device or an obstruction to achieving compactness because it occupies a large space in the device.  
         [0017]     An object of the present invention, therefore, is to provide an image display device which enables the width of the data driver circuit arranged in its non-display area to be reduced to keep the non-display area smaller, and the driver circuit (data driver circuit) thereof.  
         [0018]     Typical aspects of the present invention disclosed in this specification are summarized below.  
         [0019]     (1) A driver circuit according to the invention, which is to be arranged in the peripheral part of an image display device, supplies in parallel a plurality of analog voltages corresponding to digital signals entered serially, and comprises first and second DA converters which convert the digital signals, in accordance with more significant bits thereof, into analog voltages; a voltage divider which, arranged in the gap between the first and second DA converters, divides the output voltages of the first and second DA converters in accordance with less significant bits of the digital signals; and a shift register which generates trigger signals in synchronism with the digital signals, wherein the voltage divider comprises decoders, memory elements arrayed in two-dimensional matrixes, and a plurality of resistive wirings; and the memory elements are so configured as to store decoded signals generated by the decoders in synchronism with the trigger signals, and selectively supply, in accordance with the decoded signals stored by the memory elements, the divided voltages which derive from the first and second DA converters and are generated on the resistive wirings.  
         [0020]     (2) In an image display device according to the invention, the driver circuit according to (1) above, an image display unit comprising a plurality of pixel circuits and a plurality of data lines arranged in the image display unit to enter display signals into the pixel circuits are formed over one of paired substrates, and a liquid crystal is held between this substrate and the other of the paired substrates, the outputs of the driver circuit being fed to the data lines.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]      FIG. 1  shows a data driver circuit, which is a preferred embodiment of the present invention.  
         [0022]      FIG. 2  is a chart of operational waveforms of the data driver circuit shown in  FIG. 1 .  
         [0023]      FIG. 3  is a truth table of a decoder  1 .  
         [0024]      FIG. 4  is a truth table of a decoder DEC 2 .  
         [0025]      FIG. 5  is a truth table of a decoder DEC 3 .  
         [0026]      FIG. 6A  is a split diagram showing the former half of the relationship between the outputs of the decoders DEC 1  through DEC 3  and output voltages of Y 1  through Yn regarding digital input signals DSIG.  
         [0027]      FIG. 6B  is a split diagram showing the latter half of the relationship shown in  FIG. 6A .  
         [0028]      FIG. 7  shows an example of layout of memory elements.  
         [0029]      FIG. 8  shows a case in which a switch matrix  7  is arranged elsewhere than between switch matrixes  4  and  5 .  
         [0030]      FIG. 9  shows an embodiment of light-emitting type image display device using the data driver circuit of  FIG. 1 .  
         [0031]      FIG. 10  shows an embodiment of liquid crystal image display device using the data driver circuit of  FIG. 1 .  
         [0032]      FIG. 11  shows an example of configuration of a conventional data driver circuit. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]     Preferred embodiments of the image display device according to the present invention will be described in detail below with reference to accompanying drawings.  
       Embodiment 1  
       [0034]      FIG. 1  shows the configuration of a data driver circuit according to the present invention. This embodiment of the invention is a data driver circuit having a resolution of eight bits. The data driver circuit of this embodiment comprises decoders DEC 1  through DEC 3 , switch matrixes  4  and  5 , a shift register (SREG)  6 A and a switch matrix  7 . The switch matrix  4  is configured by arranging memory elements  8  each composed of N-channel TFTs  21  and  22  and a capacitor  23  in a matrix of nine circuits in the longitudinal direction of the drawing by n circuits in the horizontal direction of the same, the elements being connected to one another by nine decoded signal lines  11 , n trigger lines  12 , nine reference voltage lines  13  and n output lines  14 .  
         [0035]     Similarly, the switch matrix  5  is configured by arranging memory elements  9  each composed of N-channel TFTs  24  and  25  and a capacitor  26  in a matrix of eight circuits in the longitudinal direction of the drawing by n circuits in the horizontal direction of the same, the elements being connected to one another by eight decoded signal lines  15 , n trigger lines  12 , eight reference voltage lines  16  and n output lines  17 . The switch matrix  7  is configured by arranging memory elements  10  each composed of N-channel TFTs  27  and  28  and a capacitor  29  in a matrix of 17 circuits in the longitudinal direction of the drawing by n circuits in the horizontal direction of the same, the elements being connected to one another by 17 decoded signal lines  18 , n trigger lines  12 , n resistive wirings  19 , n output lines  20  and a grounding line  30 . The each number n of the memory elements  8  through  10  in the lateral direction of the drawing is variable in proportion to the resolution in the horizontal direction of the image display device to which the data driver circuit of this embodiment is applied.  
         [0036]     Digital image signals DSIG (eight-bit binary signals: b 7  through b 0 ) are entered into the decoders DEC 1  through DEC 3  from outside. Four bits b 7  through b 4  are entered into the decoder DEC 1 , three bits b 7  through b 5  into the decoder DEC 2 , and five bits b 4  through b 0  into the decoder DEC 3 . Incidentally, b 7  is the MSB and b 0 , the LSB. The nine decoded signal lines  11  connect outputs D 0  through D 8  of DEC 1  to the switch matrix  4 . The eight decoded signal lines  15  connect outputs E 0  through E 7  of DEC 2  to the switch matrix  5 . The 17 decoded signal lines  18  connect outputs F 0  through F 16  of DEC 3  to the switch matrix  7 .  
         [0037]     The n trigger lines  12  connect outputs Q 1  through Qn of the shift register  6  to the switch matrixes  4 ,  5  and  7 . Seventeen different voltages consecutive from the reference voltages V 0  through V 16  are supplied to the reference voltage lines  13  and  16 . Even-numbered voltages V 0 , V 2 , V 4 , V 6 , V 8 , V 10 , V 12 , V 14  and V 16  are supplied to the nine reference voltage lines  13 , and odd-numbered voltages V 1 , V 3 , V 5 , V 7 , V 9 , V 11 , V 13  and V 15 , to the eight reference voltage lines  16 . The n output lines  14  and the n output lines  17  are connected to the two ends each of the n resistive wirings  19 . The source electrodes of the TFTs  28  constituting one column of memory elements  10  connect one end of one resistive wiring  19  to the other end at equal intervals. The n output lines  20  connect the drain electrodes of the TFTs  28  constituting one column of memory elements  10 , and at the same time wired to outside the data driver circuit, their farther ends being connected to data lines of an image display device (not shown).  
         [0038]      FIG. 2  is a chart of operational waveforms of the data driver circuit show in  FIG. 1 . The number of digital signals DSIG entered in one round of operation in which the data driver circuit supplies analog voltages to all the outputs Y 1  through Yn is n. In synchronism with the input timings of the digital signals DSIG, the shift register  6  successively generates trigger pulses of an H (high) level at the outputs Q 1  through Qn.  FIG. 2  illustrates, by way of example for describing the operation, a case in which the first digital image signal is “00000001”, the second is “11110001”, the third is “00011111” and then-this “00110000”, all eight-bit binary numbers. DEC 1  decodes digital image signals DSIG in accordance with a truth table shown in  FIG. 3 . DEC 2  decodes digital image signals DSIG in accordance with another truth table shown in  FIG. 4 . Further, DEC 3  decodes digital image signals DSIG in accordance with still another truth table shown in  FIG. 5 .  
         [0039]     When the first digital image signal “00000001” is decoded by the decoders DEC 1  through DEC 3  in accordance with the respective truth tables, the decoded signal lines connected to the outputs D 0 , E 0  and F 1  take on the H level and the rest of the decoded signal lines, an L (low) level.  
         [0040]     Generation of a trigger pulse of the H level at the output Q 1  by the shift register  6  at a point of time t 1  in synchronism with the first digital image signal causes the TFTs  21 ,  24  and  27  built into one column of memory elements  8  through  10 , connected to the output Q 1  of the shift register through the trigger lines  12 , to be turned ON, and the voltages of the decoded signal lines  11 ,  15  and  18  are sampled into the capacitors  23 ,  26  and  29 .  
         [0041]     As the decoded signal lines connected to the outputs D 0 , E 0  and F 1  are at the H level then, the H level is sampled only for the capacitor  23  built into the memory element  8  positioned at the intersection of the trigger line  12  connected to the output Q 1  and the decoded signal line  11  connected to the decoded output D 0 , the capacitor  26  built into the memory element  9  positioned at the intersection of the trigger line  12  connected to Q 1  and the decoded signal line  15  connected to E 0 , and the capacitor  29  built into the memory element  10  positioned at the intersection of the trigger line  12  connected to Q 1  and the decoded signal line  18  connected to F 1 , while the L level is sampled for all the rest. And only the TFTs  22 ,  25  and  28  connected to these three capacitors for which the H level is sampled are turned ON.  
         [0042]     Then, the reference voltage V 0  is supplied onto a node a 1  on an output line  14 , and the reference voltage V 1 , to a node b 1  on an output line  17 . The voltage V 0  of the node a 1  and the voltage V 1  of the node b 1  are divided by a resistive wiring  19 . Connection of one column of memory elements  10  uniformly from one end of the resistive wiring  19  to the other end causes voltages equally divided by 16, including the voltage V 0 , ( 15/16)V0+( 1/16)V1, . . . , ( 1/16)V0+( 15/16)V1 and V1, to be supplied from the resistive wiring  19 .  
         [0043]     Since only the TFT  28  built into the memory element  10  positioned at the intersection of the trigger line  12  connected to the output Q 1  of the shift register and the decoded signal line  18  connected to the output F 1  of the decoder DEC 3  is ON, the voltage of ( 15/16) V0+( 1/16) V1 is selected and supplied to the output line  20  (Y 1 ). A similar operation is repeated thereafter.  
         [0044]     The second digital image signals “11110001” is entered and, in synchronism with it, the shift register  6  generates at the output Q 2  a trigger pulse of the H level at a point of time t 2 . Then, the outputs D 8 , E 7  and F 15  of the decoders DEC 1  through DEC 3  take on the H level, and the H level is sampled only for the trigger line  12  connected to the output Q 2  and memory elements  8  through  10  in positions intersecting it to turn ON the TFTs  22 ,  25  and  28 . This causes the voltage V 16  to be supplied to a node a 2 , the voltage V 15  to a node b 2 , and the divided voltage ( 15/16)V15+( 1/16)V16 of V16 to Y2.  
         [0045]     After that, the third digital image signal “00011111” is entered and, in synchronism with it, the shift register  6  generates at the output Q 3  a trigger pulse of the H level at a point of time t 3 . Then, the outputs D 1 , E 0  and F 15  of DEC 1  through DEC 3  take on the H level, and the H level is sampled only for the trigger line  12  connected to the output Q 2  and the TFTs  22 ,  25  and  28  of the memory elements  8  through  10  in positions intersecting it to turn ON. This causes the voltage V 2  to be supplied to a node a 3 , the voltage V 1  to a node b 3 , and the divided voltage ( 1/16)V1+( 15/16)V2 of V1 and V2 to Y2.  
         [0046]     Finally, the n-th digital image signal “00010000” is entered and, in synchronism with it, the shift register  6  generates at the output Q 3  a trigger pulse of the H level at a point of time tn. Then, the outputs D 1 , E 1  and F 16  of DEC 1  through DEC 3  take on the H level, and the H level is sampled only for the trigger line  12  connected to the output Qn and the TFTs  22 ,  25  and  28  of the memory elements  8  through  10  in positions intersecting it to turn ON. This causes the voltage V 2  to be supplied to a node an, and the voltage V 3  to a node bn.  
         [0047]     Incidentally, while voltage division is accomplished by a resistive wiring  19 , when the output F 0  of F 16  of the decoder DEC 3  is at the H level, the voltage at an end of the resistive wiring  19  is selected with the result that the voltage of either the node an or the node bn is directly supplied to Yn. In this case, since F 16  is at the H level, the voltage of the node bn is directly supplied, and the voltage V 3  is supplied to Yn.  
         [0048]     The operation described above provides all the predetermined output voltages Vout for Y 1  through Yn from the point of time tn onward, and they are fed to the data lines of the image display device.  FIG. 6A  and  FIG. 6B  show together the relationship between the outputs of the decoders DEC 1  through DEC 3  and the output voltages of Y 1  through Yn regarding the digital input signals DSIG. The data of DSIG are stated in hexadecimal numbers. The data driver circuit of this embodiment can supply  256  levels of voltage to data  00  through FF of the eight-bit digital input signals DSIG. Incidentally,  FIG. 6A  shows data  00  through  1 F of the digital input signals DSIG and  FIG. 6B , data  20  through FF of DSIG. Further, “REP. #1” and “REP. #2” in  FIG. 6B  respectively indicate repetitions of the same H and L output patterns, namely “#1” and “#2”, in  FIG. 6A .  
         [0049]      FIG. 7  shows an example of layout of the memory elements  8  through  10 . In this example of layout, the memory element  8  of the bottom level in the switch matrix  4 , the memory element  10  of the top level of the switch matrix  7 , a memory element  10  near the center, the memory element  10  of the bottom level and the memory element  9  of the top level of the switch matrix  5  are shown in that order.  
         [0050]     The areas surrounded by broken lines represent the pattern of the silicon thin film layer (SI) of TFT, the areas surrounded by thin solid lines, that of the gate-metal layer (GT) of TFT, the small square pattern containing x, a contact hole (CT), and the areas surrounded by thick solid lines, the pattern of a metal wiring layer (MW). The TFTs  21 ,  22 ,  24 ,  25 ,  27  and  28  are formed at the intersections between the broken-line pattern of the silicon thin film layer and the thin solid-line pattern of the gate-metal layer. The silicon thin film layer is doped with phosphorus except in the vicinities of the intersection with the gate-metal layer, and each TFT is an N-channel TFT.  
         [0051]     Further, the silicon thin film layer is long extended from the memory element  10  of the top level to the memory element  10  of the bottom level in the switch matrix  7  to form the resistive wirings  19 . The gate-metal layer is used for the trigger lines  12  and the output lines  14 ,  17  and  20 , all arranged in the longitudinal direction of the drawing.  
         [0052]     The metal wiring layer is used for connecting the wirings around the source electrodes and drain electrodes of TFTs. The metal wiring layer is also used for the decoded signal lines  11 ,  15  and  18 , the reference voltage lines  13  and  17 , and the grounding line  30  arranged in the lateral direction of the drawing. Further, the metal wiring layer forms the capacitors  23 ,  26  and  29  by overlapping the gate-metal layer with an interlayer insulating film in-between.  
         [0053]     Although all the TFTs referred to in  FIG. 1  and  FIG. 7  are N-channel TFTs, P-channel TFTs can be used instead in this configuration. In this case, the silicon thin film layer should be doped with boron, in place of phosphorus, except in its intersections with the gate-metal layer. Further, the H level should be rewritten to mean a low enough voltage to turn the P-channel TFTs ON and the L level, to mean a high enough voltage to turn the P-channel TFTs OFF.  
         [0054]     The summation W of the widths of the switch matrixes constituting the data driver circuit of this embodiment corresponds to about 13.3% of the width W 1  of the switch matrix constituting the conventional data driver circuit shown in  FIG. 11 , a factor contributing to realizing a more compact data driver circuit. The summation W of the widths of the switch matrixes is reduced to about 13% of W 1  for the following two reasons.  
         [0055]     (1) While the number of revolutions of the memory elements  84  constituting the switch matrix  83  is 256 in the longitudinal direction of the drawing in the example of conventional data driver circuit shown in  FIG. 11 , the summation of the numbers of the memory elements  8  through  10  constituting the switch matrixes  4 ,  5  and  7  in the data driver circuit, which is this embodiment of the invention shown in  FIG. 1 , is 9+8+17=34 in the longitudinal direction of the drawing, and the ratio between these numbers is 34/256≈13.3.  
         [0056]     (2) The memory elements  84  included in the conventional data driver circuit and the memory elements  8  through  10  included in the data driver circuit of this embodiment are substantially equal in layout pattern size. As shown in  FIG. 7 , the memory elements  8  through  10  are substantially equal in size between the lateral direction of the drawing and the longitudinal direction of the drawing, because each of the memory elements  8  through  10  is composed of two TFTs, one capacitor and wirings, which are connected to the TFTs and the capacitor, in the longitudinal direction and the lateral direction and accordingly the elements take on similar layout patterns. Further, since the memory elements  84  have the same circuit configuration as the memory elements  8 , the memory elements  84  can be configured in the same layout pattern as the memory elements  8 .  
         [0057]     Regarding the number of lines per output of wiring in the longitudinal direction of the drawing on the other hand, while it is two in the conventional data driver circuit, it is at most three including resistive wiring in the data driver circuit of this embodiment, and this is a disadvantage compared with the conventional circuit in terms of making the circuitry finer because the spacing between output lines is expanded as much as the width of the layout pattern constituting one wiring. However, the number of lines of wiring in the longitudinal direction is minimized to three where the switch matrix  7  is arranged between the switch matrixes  4  and  5  as in this embodiment, and the number of lines of wiring in the longitudinal direction of the drawing is four or more in all other arrangements.  
         [0058]      FIG. 8  shows a case in which a switch matrix  7  is arranged elsewhere than between switch matrixes  4  and  5 . To the two ends of each of the resistive wirings  19  contained in the switch matrix  7 , the output lines  14  of the switch matrix  4  and the output line  17  of the switch matrix  5  are connected. Then in this arrangement, it is absolutely necessary for either the output line  14  or the output line  17  to cross the memory elements  10 . Therefore, the wirings in the vicinities of any memory element  10  comprise a trigger line  12 , an output line  20 , a resistive wiring  19  and either an output line  14  or an output line  17 , the number of lines is four. Accordingly, it is desirable to arrange the switch matrix  7  between the switch matrixes  4  and  5  as in the embodiment shown in  FIG. 1 .  
       Embodiment 2  
       [0059]      FIG. 9  shows an embodiment of light-emitting type image display device using the data driver circuit of  FIG. 1 . Over a glass substrate  41 , a data driver circuit  42  of the configuration shown in  FIG. 1 , a gate driver circuit  43  and a display area  44  are formed. The data driver circuit  42  comprises switch matrixes  4 ,  5  and  7 , which are arranged in the same directions, both longitudinal and lateral, as in  FIG. 1 . In the display area  44 , a plurality of data lines  47  and a plurality of gate lines  46  are arranged in the longitudinal and lateral directions, respectively, and a pixel circuit  45  is arranged at each of their intersections. Although the example shown in  FIG. 9  is supposed to have only three data lines, two gate lines and 3×2=6 pixel circuits  45  for the sake of brevity of description, an actual image display device has hundreds each of them. For instance a color image display device of VGA resolution has 640×3(RGB)=1920 data lines  47 , 480 gate lines  46  and 640×3×480±921600 pixel circuits  45 . Each of the pixel circuits  45  comprises N-channel TFTs  51  and  53 , a capacitor  52 , a light-emitting diode element  54 , an anode power supply  55  and a cathode power supply  56 .  
         [0060]     The image display device of  FIG. 9  displays an image by the operation to be described below. The data driver circuit  42 , to which externally supplied digital image signals DSIG are entered, supplies analog voltages corresponding to the digital image signals DSIG at outputs Y 1  through Y 3  and data lines  47  connected to them. The gate driver circuit  43  successively generates trigger pulses at G 1  and G 2  in synchronism with the converting operation of the data driver circuit  42 . The gate electrode of the TFT  51  built into each pixel circuit  45  is connected to the output G 1  or G 2  of the gate driver circuit  43  through a gate line  46 , and the TFT  51  samples the voltage of the data line  47  into the capacitor  52  in response to a trigger pulse generated by the gate driver circuit  43 .  
         [0061]     In the first round of converting operation by the data driver circuit  42 , the generation of a trigger pulse by the gate driver circuit  43  at the output G 1  causes the analog voltage supplied to Y 1  through Y 3  to be sampled into the capacitor  52  built into the pixel circuit  45  on the first row. In the second round of converting operation by the data driver circuit  42 , the generation of a trigger pulse by the gate driver circuit  43  at the output G 2  causes the analog voltage supplied to Y 1  through Y 3  to be sampled into the capacitor  52  built into the pixel circuit  45  on the second row.  
         [0062]     As the sampled voltage is applied between the gate electrode and the source electrode of the TFT  53 , the TFT  53  controls the current flowing to the light-emitting diode element  54  in accordance with the voltage sampled into the capacitor  52 . The luminescence intensity of the light-emitting diode element  54  varies in proportion to that current. As a light-emitting diode element whose luminescence intensity is proportional to the current, an organic electroluminescence element can be used.  
         [0063]     Since the luminescence intensity of the light-emitting diode element  54  built into every pixel circuit  45  can be controlled in accordance with the digital image input signal DSIG, the image display device of  FIG. 9  can display images.  
         [0064]     In the embodiment of  FIG. 9 , the data driver circuit  42  is arranged outside the display area  44 , namely in a non-display area. As the summation W of the circuit widths of the switch matrixes  4 ,  5  and  7  is therefore reduced to 13.3% of the circuit width W 1  of the switch matrix of the conventional data driver circuit, the square measure of the non-display area of this embodiment can be made smaller than where the conventional data driver circuit is used.  
       Embodiment 3  
       [0065]      FIG. 10  shows an embodiment of liquid crystal image display device using the data driver circuit of  FIG. 1 . Over a glass substrate  61 , data driver circuits  62  and  63  of  FIG. 1 , a gate driver circuit  64 , a display area  65 , and demultiplexers  69  and  70  are formed. The data driver circuit  62  comprises the switch matrixes  4 ,  5  and  7 , which are arranged in the same directions, both longitudinal and lateral, as in  FIG. 1 . The data driver circuit  63  also comprises the switch matrixes  4 ,  5  and  7 , but they are arranged in directions inverted longitudinally from the corresponding directions in FIG. In the display area  65 , a plurality of data lines  67  and a plurality of gate lines  66  are arranged in the longitudinal and lateral directions, respectively, and a pixel circuit  68  is arranged at each of their intersections.  
         [0066]     Although the example shown in  FIG. 10  is supposed to have only four data lines, two gate lines and 4×2=8 pixel circuits  68  for the sake of brevity of description, an actual image display device has hundreds each of them. For instance a color image display device of VGA resolution has 640×3(RGB)=1920 data lines  67 , 480 gate lines  66  and 640×3×480=921600 pixel circuits  68 . Each of the pixel circuits  68  comprises an N-channel TFT  71 , a capacitor  72 , and a liquid crystal element  73 .  
         [0067]     Though not shown in the drawing, another glass substrate over which a transparent common electrode  74  is superposed over the glass substrate  61  and, by having a liquid crystal material held between them, the liquid crystal element  73  is formed. Onto the external surface of each of these two glass substrates, a polarizing film is stuck. According to the voltage applied to the liquid crystal element  73 , the orientation of the liquid crystal molecules in the liquid crystal element  73  varies to control the intensity of the light transmitted by the liquid crystal element  73  and the two polarizing films.  
         [0068]     The liquid crystal image display device shown in  FIG. 10  displays images by the operation to be described below. The data driver circuits  62  and  63 , to which externally supplied digital image signals DSIG are entered, supply analog voltages corresponding to the digital image signals DSIG to the demultiplexers  69  and  70  connected to the outputs Y 1  and Y 2 .  
         [0069]     For the purpose of causing the voltage applied to the liquid crystal element  73  to alternate, the reference voltage supplied to the data driver circuit  62  is higher than the potential of a common electrode  74  formed over the other superposed glass substrate and opposed to the glass substrate  61  (hereinafter referred to as the opposed electrode  74 ), while the reference voltage supplied to the data driver circuit  63  is lower than the potential of the opposed electrode  74 . The output voltages of these data driver circuits  62  and  63  are distributed by the demultiplexers  69  and  70  to odd-numbered and even-numbered data lines  67 .  
         [0070]     The gate driver circuit  64  successively generates trigger pulses at G 1  and G 2  in synchronism with the converting operation of the data driver circuits  62  and  63 . The gate electrode of the TFT  71  built into each pixel circuit  68  is connected to the output G 1  or G 2  of the gate driver circuit  64  through a gate line  66 , and the TFT  71  samples into the capacitor  72  the voltage of the data line  67  in response to a trigger pulse generated by the gate driver circuit  64 .  
         [0071]     In the first round of converting operation by the data driver circuits  62  and  63 , the generation of a trigger pulse by the gate driver circuit  64  at the output G 1  causes the analog voltage supplied to Y 1  and Y 2  to be sampled into the capacitor  72  built into the pixel circuit  68  on the first row. In the second round of converting operation by the data driver circuits  62  and  63 , the generation of a trigger pulse by the gate driver circuit  64  at the output G 2  causes the analog voltage supplied to Y 1  and Y 2  and to be sampled into the capacitor  72  built into the pixel circuit  68  on the second row.  
         [0072]     The sampled voltage is applied to the liquid crystal element  73  to control the intensity of the light transmitted by the liquid crystal element  73 . By switching between the demultiplexers  69  and  70 , the voltage applied to the liquid crystal element  73  built into each pixel circuit  68  can be caused to alternate. It is preferable for the timing of switching to match the horizontal blanking period or the vertical blanking period of the entered digital image signals DSIG.  
         [0073]     Since the intensity of the light transmitted by the liquid crystal element  73  built into every pixel circuit  68  can be controlled in accordance with the digital image signals, the liquid crystal image display device shown in  FIG. 10  can display images.  
         [0074]     In the embodiment shown in  FIG. 10 , the data driver circuits  62  and  63  are arranged outside the display area  65 , namely in a non-display area. As the summation W of the circuit widths of the switch matrixes  4 ,  5  and  7  is therefore reduced to 13.3% of the circuit width W 1  of the switch matrix of the conventional data driver circuit, the square measure of the non-display area of this embodiment can be made smaller than where the conventional data driver circuit is used.  
         [0075]     According to the present invention, since the non-display area of the image display device can be kept smaller in spite of an increase in the number of display gradations, the freedom of designing the shape of products to be mounted on the image display device is increased and, as the space occupied in the product is reduced, the product can be made more compact.