Abstract:
A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to output the amplified signal; and a biasing circuit, for providing a biasing current to the amplifying circuit, and providing the second biasing current to the latching unit. The biasing circuit includes: a first biasing module for providing a third biasing circuit to the amplifying circuit in the first state; and a second biasing module, for providing a fourth biasing current to the amplified circuit; wherein the first biasing circuit is equal to a sum of the third biasing current and the fourth biasing current.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a latch, and more particularly, to a latch capable of being operated in a high frequency. 
   2. Description of the Related Art 
   In an integrated circuit, clock signals having different frequencies are often utilized to perform different operations. As is known, the phase locked loop (PLL)/synthesizer is widely used for generating the above-mentioned clock signals having different frequencies. 
   As known by those skilled in the art, the PLL/synthesizer comprises a frequency divider, which is utilized to divide the frequency generated by the inner VCO (voltage controlled oscillator). Through the above-mentioned mechanism, the PLL can output a clock signal having a wanted frequency. 
   In general, the frequency divider is often implemented by D-type flip-flops. Please refer to  FIG. 1 , which is a diagram of a frequency divider  100  having a divisor  2  according to the prior art. As shown in  FIG. 1 , the frequency divider  100  is implemented by a D-type flip-flop  200 . The input end Q′ and the input end D of the D-type flip-flop  200  are coupled to each other. In this way, as shown in  FIG. 1 , the frequency of the output signal outputted from the output end Q′ is twice of that of the clock signal CK inputted into the clock input end. Since the operation and function of the D-type flip-flop are well known, and thus omitted here. 
   In addition, the frequency divider is often operated in a high frequency. Therefore, in the actual implementation, the D-type flip-flop is often implemented by a current mode logic (CML) circuit, which comprises two latches. Please note, the related theory and the conventional circuit structure can be referred to the page 290 of RF Microelectronics (ISBN: 0-13-887571-5) written by Behzad Razavi, and further illustration is omitted here. 
   However, if the function of the above-mentioned frequency divider  100  should be achieved, the input end and the output end of the above-mentioned D-type flip-flop are coupled together such that the feedback loop (it is equivalent to the feedback loop from the output end Q to the input end D shown in  FIG. 1 ) is established. As mentioned previously, the CML D-type flip-flop is more appropriate for the high-frequency operation, but it still has many restrictions. 
   For example, if the circuit designer wants to design a frequency divider having a devisor  4 , the most frequently-used method is to connect two frequency divider having a devisor  2  (that is, to connect two D-type flip-flops). 
   But, if the frequency divider having the devisor  4  should be operated in a high frequency, a conventional solution is to reduce the inner load (it could be a resistor or passive device) of the D-type flip-flops such that the RC constant is also reduced. However, a larger biasing current is needed such that enough signal amplitude is provided to the following D-type flip-flop. 
   Please note, the operation of raising the biasing current often encounters following problems: 
   The first solution is to raise the biasing current without adjusting the W/L ratio of inner transistors. But this reduces the voltage difference V DS  of the biasing current source (such as a current mirror), and may further make the biasing current source be in the triode region such that the current cannot be increased more, and the operational frequency cannot be raised, either. 
   The second solution is to raise the biasing current with adjusting the W/L ratio of inner transistors. However, this makes the parasitic capacitor of the gate of the inner transistors larger. Unfortunately, the increasing parasitic capacitor becomes the load of the previous D-type flip-flop such that the RC delay of the previous D-type flip-flop increases accordingly. This also limits the operational frequency of the entire circuit. 
   SUMMARY OF THE INVENTION 
   In view of the above-mentioned problems, an object of the invention is to provide a latch capable of being operated in a high frequency, to further solve the above-mentioned problems. 
   According to an embodiment of the present invention, a latch is disclosed. The latch comprises: an amplifying circuit, for receiving a first biasing current in a first state to amplify an input signal to generate an amplified signal; a latching unit, coupled to the amplifying circuit, for latching the amplified signal and for receiving a second biasing current in a second state to output the amplified signal; and a biasing circuit, coupled to the amplifying circuit and the latching unit, for providing the first biasing current to the amplified circuit in the first state and for providing the second biasing current to the latching unit, the biasing circuit comprising: a first biasing module, coupled to the amplifying circuit, for providing a third biasing current to the amplifying circuit in the first state; and a second biasing module, coupled to the amplified circuit, for providing a fourth biasing current to the amplifying circuit; wherein the first biasing current is equal to a sum of the third biasing current and the fourth biasing current. 
   According to another embodiment of the present invention, a latch is disclosed. The latch comprises: an input circuit, for receiving an input signal and generating an output signal according to the input signal and an input reference current; an output circuit, coupled to the input circuit, for receiving the output signal and outputting the output signal according to an output reference current; and a current generating circuit, coupled to the input circuit and the output circuit, for generating the output reference current to the input circuit according to a clock signal, and for generating the output reference current to the output circuit, the current generating circuit comprising: a first current generating unit, for providing a first current to the input circuit when the clock signal corresponds to a first logic level, wherein the first current is a part of the input reference current; and a second current generating unit, for providing a second current to the input circuit when the clock signal corresponds to the first logic level, and for providing the second current to the output circuit when the clock signal corresponds to a second logic level, wherein the second current is a part of the input reference current, and the second current is equal to the output reference current or is a part of the output reference current. 
   The present invention does not need to adjust the W/L ratio of the inner transistors or to increase V GS  of the inner transistors in order to increase the biasing current. Therefore, the present invention latch can prevent from the parasitic capacitor problem and can be operated in a high frequency. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram of a frequency divider having a divisor  2  according to the prior art. 
       FIG. 2  is a diagram of a latch of a first embodiment according to the present invention. 
       FIG. 3  is a diagram showing the control clock CK and the inversed control clock CKN. 
       FIG. 4  is a diagram of a latch of a first embodiment according to the present invention. 
       FIG. 5  is a diagram of a latch of a third embodiment according to the present invention. 
       FIG. 6  is a diagram of a latch of a fourth embodiment according to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The “TITLE” of the invention will be described with reference to the accompanying drawings. 
   Please refer to  FIG. 2 , which is a diagram of a latch  400  of a first embodiment according to the present invention. As shown in  FIG. 2 , the latch  200  comprises a preamplifier  410 , a latching unit  420 , and a biasing circuit  430 . 
   The latching unit  420  comprises two cross-coupled transistors M 5  and M 6 . Because the gate of the transistor M 5  is coupled to the drain of the transistor M 6  and the gate of transistor M 6  is coupled to the drain of the transistor M 5  (cross-coupling structure), the signals Von and Vop can be utilized to control the conducting conditions of the transistors M 5  and M 6  such that the voltage level of the signals Von and Vop can be maintained. 
   Please note, the biasing circuit  430  in the latch  400  is different from the conventional biasing circuit. In this embodiment, the biasing circuit  430  comprises four transistors M 1 ˜M 4 . In addition, the gates of the transistors M 2  and M 3  are coupled to a common mode voltage level V CM , the gates of the transistors M 1  and M 4  are respectively coupled to the control clock CK and inversed control clock CKN. Here, please refer to  FIG. 3 , which is a diagram showing the control clock CK and the inversed control clock CKN. 
   Furthermore, the transistors M 1  and M 2  can be regarded as a differential circuit (or can be regarded as a sub-biasing module), where the sources of the transistors M 1  and M 2  are both coupled to a biasing current source  430 , the drain of the transistor M 1  is coupled to the preamplifier  410 , and the drain of the transistor M 2  is coupled to the external voltage source V DD . 
   On the other hand, the transistors M 3  and M 4  can be regarded as another differential circuit (or can be regarded as another sub-biasing module), where the sources of the transistors M 1  and M 2  are both coupled to a biasing current source  432 , the drain of the transistor M 3  is coupled to the preamplifier  410 , and the drain of the transistor M 4  is coupled to the latching unit  420 . 
   In addition, in order to make the entire circuit work correctly, the voltage levels of the control clock CK, the inversed control clock CKN, and the common mode voltage level V CM  should be appropriately set. In this embodiment, when the control clock CK corresponds to a high logic level (e.g: rising edge), the voltage level of the control clock CK is higher than the common mode voltage level V CM . Furthermore, the control clock CK corresponds to a low logic level (e.g: falling edge), the voltage level of the control clock CK is lower than the common mode voltage level V CM . 
   For example, the high logic level of the control clock CK can be set as a voltage level 3.5V, the common mode voltage level V CM  can be set as 0V, and the high logic level of the control clock CK can be set as a voltage level −3.5V. However, the above-mentioned voltage levels 3.5V, 0V, and −3.5V are only utilized as an embodiment, not a limitation of the present invention. 
   In the following disclosure, the operations of the latch  400  will be illustrated. 
   First of all, when the control clock CK corresponds to a high logic level (such as at rising edge), for the differential circuit composed of two transistors M 1  and M 2 , almost all of the current I 3  provided by the biasing current source  431  is transferred to the preamplifier  410  via the transistor M 1  because the control clock CK is much higher than the common mode voltage level V CM . 
   On the other hand, for the differential circuit composed of two transistors M 3  and M 4 , almost all of the current I 4  provided by the biasing current source  432  is transferred to the preamplifier  410  via the transistor M 3  because the common mode voltage level V CM  is much higher than the inversed control clock CKN. 
   In this embodiment, the preamplifier  410  comprises a transistor pair M 7  and M 8  and two corresponding loads. After the current I 3 +I 4  is inputted into the transistor pair M 7  and M 8 , the transistor pair M 7  and M 8  starts to operate with the loads such that the preamplifier  410  performs an amplifying operation on the input signals Vin and Vip and then outputs the amplified signals to the latching unit  420 . 
   And then, when the control clock CK corresponds to a low logic level (e.g: falling edge), for the differential circuit composed of two transistors M 3  and M 4 , almost all of the current I 4  provided by the biasing current source  432  is transferred to the latching unit  420  via the transistor M 4  because the common mode voltage level V CM  is much higher than the inversed control clock CKN. Therefore, the latching unit  420  operates to latch the signals transferred from the preamplifier  410  and then outputs the latched signals. 
   From the above disclosure, it can be seen that the total biasing current inputted into the preamplifier  410  is the sum of the two biasing currents I 3 +I 4 . In other words, if the currents I 3  and I 4  are the same (for example, they are both equal to the current I), the present invention biasing circuit  430  can provide the current  21  to the preamplifier  410 . In this way, the current can be double (it can have an equivalent effect of increasing the W/L ratio of the transistor). Furthermore, because the gate of the transistor M 2  is coupled to the common mode voltage level V CM  such that it does not influence the parasitic capacitor of the transistor M 1 . This means that the parasitic capacitor of the transistor M 1  does not become larger. In other words, the load of the previous stage in not increased and the operational frequency of the latch  400  is not limited. 
   In other words, if the latch  400  needs to work in a high frequency and an additional biasing current is needed, the present invention can utilize the biasing current I 4  as the additional biasing current (where the biasing current I 3  can be the same). In this way, the W/L ratio of the transistor M 1  does not need to be increased (this means that the parasitic capacitor is not increased, either). From the above disclosure, it can be seen that the present invention can achieve the purpose of increasing the biasing current without increasing the parasitic capacitor. Therefore, the present invention  400  can no doubt work in a higher frequency. 
   Please note that, in this embodiment, because the drain of the transistor M 2  is coupled to the external voltage source, when the control clock CK corresponds to a low logic level (when the latching unit  420  is working), only the biasing current I 4  is transferred to the latching unit  420  to use. 
   Please note that, the present invention does not limit the W/L ratios of the transistors M 1 ˜M 4  and the currents provided by the biasing current sources  431  and  432 . The circuit designer can adjust the W/L ratios of the transistors M 1 ˜M 4  and the currents provided by the biasing current sources  431  and  432  according to his demands to allow the entire latch  400  to work more efficiently. For example, when the latch  400  works in a lower frequency, it means that the latching unit  420  needs to latch the signal for a longer time. Obviously, the latching unit  420  needs a larger current. Therefore, the circuit designer can correspondingly design the current I 4  as a larger current. 
   From the above disclosure, the operations and functions of the latch  400  can be understood by those skilled in the art. In addition, those skilled in the art can easily utilize the latch  400  in a D-type flip-flop, a frequency divider, or a PLL. As mentioned previously, the D-type flip-flop can be implemented by connecting two latches  400 . Furthermore, the frequency divider having the devisor  2  can be implemented by connecting the output Q′ to the input end D. Moreover, a frequency divider having a larger divisor can be implemented by connecting several frequency dividers. 
   Please refer to  FIG. 4 , which is a diagram of a latch  500  of a first embodiment according to the present invention. As shown in  FIG. 4 , in this embodiment, the latch  500  is similar to the above-mentioned latch  400 . The difference between them is: in the biasing circuit  530 , the drain of the transistor M 2  is coupled to the latching unit  520  instead of the external voltage source V DD . 
   Therefore, in this embodiment, when the inversed control clock CKN corresponds to a high logic level (the control clock CK corresponds to a low logic level), for the differential circuit composed of two transistors M 1  and M 2 , almost all of the current I 3  provided by the biasing current source  531  is transferred to the latching unit  520  via the transistor M 2  because the common mode voltage level V CM  is much higher than the control clock CK. 
   On the other hand, for the differential circuit composed of two transistors M 3  and M 4 , almost all of the current I 4  provided by the biasing current source  532  is transferred to the latching unit  520  via the transistor M 4  because the inversed control clock CKN is much higher than the common mode voltage level V CM . 
   Therefore, the latching unit  520  starts to work to latch the signals and then output the latched signals. 
   From the above, it can be seen that when the latching unit  520  works, the current passing through the transistor M 2  is transferred to the latching unit  520 . In other words, in this embodiment, the total biasing current inputted to the preamplifier  510  and the latching unit  520  is equal to the sum of the currents I 3  and I 4 . 
   Similarly, the present invention does not limit the W/L ratios of the transistors M 1 ˜M 4  and the currents provided by the biasing current sources  531  and  532 . The circuit designer can adjust the W/L ratios of the transistors M 1 ˜M 4  and the currents provided by the biasing current sources  531  and  532  according to his demands (for example, the frequency which the latch  500  work at) to allow the entire latch  400  to work more efficiently. 
   Please refer to  FIG. 5 , which is a diagram of a latch  600  of a third embodiment according to the present invention. As shown in  FIG. 5 , the latch  600  adds two AC couple circuits  640  and  650 . The AC couple circuit  640  is coupled between the control clock CK and the preamplifier  610 . The AC couple circuit  650  is coupled between the inversed clock CKN and the latching unit  620 . 
   Each of the AC couple circuits  640  and  650  comprises a resistor and a capacitor, which is parallel to the resistor as shown in  FIG. 5 . In this embodiment, the AC couple circuits  640  and  650  are utilized to make the entire circuit work at a best operational point. The operations and the functions of the AC couple circuits  640  and  650  are well known, and thus omitted here. 
   Please refer to  FIG. 6 , which is a diagram of a latch  700  of a fourth embodiment according to the present invention. As shown in  FIG. 6 , in the biasing circuit  730 , adjustable current sources  731  and  732  are utilized instead of the above-mentioned fixed current sources. In this way, the circuit designer can easily change the currents provided by the adjustable current sources  731  and  732  such that the latch  700  can have better performance when it works at different frequencies. 
   In contrast to the prior art, the present invention does not need to adjust the W/L ratio of the inner transistors or to increase V GS  of the inner transistors in order to increase the biasing current. Therefore, the present invention latch can prevent from the parasitic capacitor problem and can be operated in a high frequency. 
   While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.