Abstract:
A clearance inspection apparatus for inspecting clearance of a wiring line passing between vias on a substrate comprises: first determining means for determining vias adjacent on both sides of a reference via as first adjacent vias, the reference via and the first adjacent vias belonging to a first via row, wherein the reference via serves as a reference in clearance inspection; second determining means for determining vias adjacent to the first adjacent vias as second adjacent vias, the second adjacent vias belonging to a second via row which is adjacent to the first via row; and third determining means for determining a via located between the second adjacent vias as an inspection target via, wherein the clearance inspection apparatus inspects the clearance of the wiring line passing between the reference via and the inspection target via.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a clearance inspection apparatus and method for inspecting the clearance of wiring lines passing between vias on a substrate.  
         [0003]     2. Description of the Related Art  
         [0004]     In a semiconductor package such as a PBGA or EBGA package, a wiring pattern is designed so as to connect the pads (for example, bonding pads or flip chip pads), to be electrically connected to electrode terminals on a semiconductor chip, to the vias (lands) provided along the periphery thereof, or to connect between the vias.  
         [0005]     As one example of a wiring pattern design method, there is disclosed in Japanese Unexamined Patent Publication No. 2002-083006 a method in which only wiring routes are determined in advance in a rough wiring step, and then, in a wiring forming step, the wiring lines are laid automatically and uniformly by considering clearances (lines and spaces) while checking them against the actual design rules.  
         [0006]     Further, in Japanese Unexamined Patent Publication No. 10-214898, there is disclosed an automatic wiring method that employs an any-angle wiring technique to make effective use of wiring areas, while allowing wiring line spacing and wiring line width to be increased where space permits.  
         [0007]     The result of automatic wiring differs depending on setting conditions. To address this, one possible design method is to determine which condition yields what wiring result, by changing the setting conditions for the nets between pads and vias or between vias in various ways, and to select the optimum setting conditions. Another possible design method is to change the positions of vias based on the result of the automatic wiring. In either case, the wiring lines passing between various kinds of obstacles, in particular, vias, must be inspected for wiring line spacing, i.e., the clearance (line and space). Usually, in a wiring line clearance inspection process, the clearance is inspected for every possible combination of vias.  
         [0008]      FIG. 13  is a diagram showing one example of the inspection pattern illustrating the directions along which the wiring lines are to be inspected for clearance. In the figure, reference characters V 1  to V 10  are the identification numbers of the vias, and reference characters N 1  to N 13  are the identification numbers of the wiring lines. In the specification of the present invention, the direction along which a wiring line is inspected for clearance will be referred to as the “clearance inspection direction”, and the line showing the clearance inspection direction as the “inspection line”.  
         [0009]     When the wiring lines N 1  to N 13  are routed in accordance with design data on a substrate where the vias V 1  to V 10  are formed, the wiring lines N 1  to N 13  must be inspected for clearance along the clearance inspection directions indicated by the inspection lines shown by dashed lines in the figure. Here, as the clearance inspection is performed for every possible combination of vias, there are as many clearance inspection directions as there are possible combinations of the vias. For example, as shown in  FIG. 13 , there are very many inspection lines (each shown by a dashed line in the figure).  
         [0010]      FIGS. 14   a  and  14   b  are diagrams showing another example of the inspection pattern illustrating the directions along which the wiring lines are to be inspected for clearance. In the figure, reference characters V 1  to V 11  are the identification numbers of the vias, reference characters N 1  to N 8  are the identification numbers of the wiring lines, and reference characters A 1  and A 2  are the identification numbers of auxiliary lines (indicated by semi-dashed lines in the figure).  
         [0011]     When the wiring lines N 1  to N 8  are routed passing between the vias V 1  to V 11  as shown in  FIG. 14   a , the wiring lines N 1  to N 8  are inspected for clearance along the clearance inspection directions indicated by the inspection lines shown by dashed lines in the figure.  
         [0012]     As earlier described, the clearance inspection directions are determined by the possible combinations of the vias V 1  to V 11 . However, between the vias V 8  and V 11 , for example, there is no wiring line passing between them and, in actuality, there is no need to inspect the wiring line clearance between these vias V 8  and V 11 . Further, in the space between the vias V 10  and V 3  and between the vias V 10  and V 4 ; while the wiring lines N 4  to N 8  are routed passing through the space, there is no wiring line passing between the vias V 3  and V 4 . Accordingly, once the clearance inspection is performed between the vias V 10  and V 4 , the clearance inspection need not necessarily be performed between the vias V 10  and V 3 .  
         [0013]     While, in automatic wiring, it is desirable to be able to obtain the result of the clearance inspection instantly, if the clearance inspection is to be performed for every possible combination of vias, the amount of computation will become enormous, leading to the problem that it takes considerable time to complete the inspection. Here, if the clearance inspection is performed only for those combinations of vias between which the wiring lines pass, unnecessary clearance inspection can be eliminated, and it should become possible to reduce the amount of the computation to be performed by a computer.  FIG. 14   b  shows one example of the inspection pattern after the number of clearance inspection directions has been reduced.  
         [0014]     Accordingly, in view of the above problem, it is an object of the present invention to provide a clearance inspection method and apparatus that can efficiently inspect the clearance of wiring lines passing between vias on a substrate.  
       SUMMARY OF THE INVENTION  
       [0015]     To achieve the above object, according to the present invention, when wiring lines are routed passing between vias (obstacles), those vias between which the wiring lines pass are extracted, and the clearance inspection is performed only for such vias, thereby reducing the amount of the computation to be performed by computer.  
         [0016]      FIG. 1  is a block diagram showing the basic principle of a clearance inspection apparatus according to a first mode of the present invention.  
         [0017]     The clearance inspection apparatus  1  for inspecting the clearance of a wiring line passing between vias on a substrate, comprises: 
        first determining means  11  for determining vias, adjacent to and on both sides of a reference via, as first adjacent vias, the reference via and the first adjacent vias belonging to a first via row, wherein the reference via serves as a reference in clearance inspection;     second determining means  12  for determining vias adjacent to the first adjacent vias as second adjacent vias, the second adjacent vias belonging to a second via row which is adjacent to the first via row; and     third determining means  13  for determining a via located between the second adjacent vias as an inspection target via, wherein     the clearance inspection apparatus inspects the clearance of the wiring line passing between the reference via and the inspection target via.        
 
         [0022]      FIG. 2  is a block diagram showing the basic principle of a clearance inspection apparatus according to a second mode of the present invention.  
         [0023]     The clearance inspection apparatus  2  for inspecting the clearance of a wiring line passing between vias on a substrate, comprises: 
        first determining means  21  for determining vias adjacent on both sides of a reference via as first adjacent vias, the reference via and the first adjacent vias belonging to a first via row, wherein the reference via serves as a reference in clearance inspection;     second determining means  22  for determining vias adjacent to the first adjacent vias as second adjacent vias, the second adjacent vias belonging to a second via row which is adjacent to the first via row;     third determining means  23  for determining a via located between the second adjacent vias as an inspection candidate via;     judging means  24  for judging whether or not an inspection line joining the reference via to the inspection candidate via and a wiring line crossing the inspection line cross each other in such a manner as to point in substantially the same tending direction on a virtual plane in which a direction along which the via row containing the reference via extends is taken as a coordinate axis of the virtual plane; and     fourth determining means  25  for determining the inspection candidate via as an inspection target via if the judging means  24  has judged that the inspection line associated with the inspection candidate via does not cross the wiring line in such a manner as to point in substantially approximately the same direction as the wiring line, wherein     the clearance inspection apparatus inspects the clearance of the wiring line passing between the reference via and the inspection target via.        
 
         [0030]     The means  11  to  13  and  21  to  25  in the clearance inspection apparatuses  1  and  2  can each be implemented in the form of a software program executable by a processing unit such as a computer. The apparatus for implementing the above process and the creation of a program for causing a computer to execute the above process can be readily implemented by those skilled in the art upon understanding the following detailed description. It will also obvious to those skilled in the art that the program for causing a computer to execute the above process is stored on a recording medium.  
         [0031]     According to the present invention, as the clearance inspection is performed only for those vias between which the wiring lines pass, the amount of computation necessary for the clearance inspection can be drastically reduced, compared with the prior art which requires performing the clearance inspection for all the vias. As a result, the manufacturing cost of semiconductor packages can be reduced. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]     The present invention will be more clearly understood from the description as set below with reference to the accompanying drawings, wherein:  
         [0033]      FIG. 1  is a block diagram showing the basic principle of a clearance inspection apparatus according to a first mode of the present invention;  
         [0034]      FIG. 2  is a block diagram showing the basic principle of a clearance inspection apparatus according to a second mode of the present invention;  
         [0035]      FIG. 3  is a flowchart showing the operation flow of a clearance inspection apparatus according to a first embodiment of the present invention;  
         [0036]      FIG. 4  is a diagram for explaining, by way of a specific example, the process performed by the clearance inspection apparatus according to the first embodiment of the present invention;  
         [0037]      FIGS. 5   a  to  5   c  are conceptual diagrams for explaining the operation of the clearance inspection apparatus according to a second embodiment of the present invention;  
         [0038]      FIGS. 6   a  to  6   d  are diagrams for explaining one specific example of how the crossing of an inspection line and a wiring line is judged in the clearance inspection apparatus according to the second embodiment of the present invention;  
         [0039]      FIG. 7  is a flowchart showing the operation flow of the clearance inspection apparatus according to the second embodiment of the present invention;  
         [0040]      FIGS. 8   a  to  8   d  are diagrams (part 1) for explaining, by way of a specific example, the process performed by the clearance inspection apparatus according to the second embodiment of the present invention;  
         [0041]      FIGS. 9   a  and  9   b  are diagrams (part 2) for explaining, by way of a specific example, the process performed by the clearance inspection apparatus according to the second embodiment of the present invention;  
         [0042]      FIGS. 10   a  to  10   c  are diagrams (part 3) for explaining, by way of a specific example, the process performed by the clearance inspection apparatus according to the second embodiment of the present invention;  
         [0043]      FIG. 11  is a diagram showing one specific example of an inspection pattern illustrating the clearance inspection directions obtained by the clearance inspection apparatus according to the second embodiment of the present invention;  
         [0044]      FIG. 12  is a diagram showing a table defining the combinations of reference vias and their associated inspection target vias in the specific example shown in  FIG. 11 ;  
         [0045]      FIG. 13  is a diagram showing one example of an inspection pattern illustrating the directions along which wiring lines are to be inspected for clearance; and  
         [0046]      FIGS. 14   a  and  14   b  are diagrams showing another example of the inspection pattern illustrating the directions along which wiring lines are to be inspected for clearance. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0047]      FIG. 3  is a flowchart showing the operation flow of a clearance inspection apparatus according to a first embodiment of the present invention. The first embodiment of the present invention corresponds to the first mode of the present invention described with reference to  FIG. 1 .  
         [0048]     First, in step S 101 , a reference via that serves as a reference in the clearance inspection is determined. Next, in step S 102 , a second via row adjacent to the first via row to which the reference via belongs is determined. Next, in step S 103 , vias belonging to the first via row and adjacent on both sides of the reference via are determined as first adjacent vias. Next, in step S 104 , vias belonging to the second via row and adjacent to the respective first adjacent vias are determined as second adjacent vias. Then, in step S 105 , a via belonging to the second via row and located between the second adjacent vias is determined as an inspection target via. In the present embodiment, the clearance inspection need only be performed only on the wiring line or lines passing between the reference via and the inspection target via. In step S 106 , it is determined whether the above process has been completed on all the vias. That is, each via on the substrate is sequentially determined as the reference via and, thus, the clearance inspection is performed over the entire surface of the substrate. In the above process, the order of the steps S 102  and S 103  may be interchanged.  
         [0049]     The above steps S 101  to S 106  according to the present embodiment are executed by a processing unit such as a computer. Here, it is preferable that design data, rules concerning clearances, and other data such as the coordinates, shape, size, and orientation of each via, substrate information, etc. be entered into the processing unit prior to the execution of step S 101 . By using the thus entered data, the processing unit initiates processing in step S 101 .  
         [0050]      FIG. 4  is a diagram for explaining, by way of a specific example, the process performed by the clearance inspection apparatus according to the first embodiment of the present invention. In the figure, reference characters V 1  to V 11  are the identification numbers of the vias, and reference characters A 1  to A 3  are the identification numbers of via rows (indicated by semi-dashed lines in the figure). The via rows A 1  to A 3  show an array of vias arranged in rows.  
         [0051]     The specific example here deals with the case where the via V 3  is selected as the reference via.  
         [0052]     The reference via V 3 , together with the vias V 1 , V 2 , and V 4 , belongs to the via row A 1 . The via row adjacent to the via row A 1  to which the reference via V 3  belongs is the via row A 2 . In each via row, the vias need not necessarily be arranged in a straight line, but need only be arranged in a successive manner that just enables the vias to be grouped together as a row.  
         [0053]     The vias belonging to the via row A 1  and adjacent on both sides of the reference via V 3  are the vias V 2  and V 4 . Therefore, these vias V 2  and V 4  are determined as the first adjacent vias in step S 103  of  FIG. 3  described above.  
         [0054]     Further, the vias belonging to the via row A 2  and adjacent to the respective vias V 2  and V 4  are the vias V 6  and V 8 . Therefore, these vias V 6  and V 8  are determined as the second adjacent vias in step S 104  of  FIG. 3  described above.  
         [0055]     Then, the vias V 6 , V 7 , and V 8  belonging to the via row A 2  and located between the vias V 6  and V 8  are determined as the inspection target vias.  
         [0056]     There is, therefore, no need to perform the clearance inspection along all the directions formed between the reference via V 3  and the respective vias V 1 , V 2 , and V 4  to V 11 , but the clearance inspection directions can be limited to those formed between the reference via V 3  and the respective target vias V 6 , V 7 , and V 8 . For example, clearance inspection directions need not be set between the reference via V 3  and the vias V 9 , V 10 , and V 11 .  
         [0057]     As described above, in the first embodiment of the present invention, each via on the substrate is sequentially set as the reference via, and the above process is repeated to perform the clearance inspection over the entire surface of the substrate. The second embodiment of the present invention hereinafter described aims to further reduce the amount of computation by further limiting the number of clearance inspection directions than the foregoing first embodiment. The second embodiment of the present invention corresponds to the second mode of the present invention described with reference to  FIG. 2 .  
         [0058]      FIGS. 5   a  to  5   c  are conceptual diagrams for explaining the operation of the clearance inspection apparatus according to the second embodiment of the present invention. In the figure, reference characters V 1  to V 7  are the identification numbers of the vias, reference characters N 1  to N 11  are the identification numbers of the wiring lines, and reference characters A 1  and A 2  are the identification numbers of the via rows (indicated by semi-dashed lines in the figure).  
         [0059]     Here, in the case where, in the foregoing first embodiment, the vias V 2  to V 7  have been determined as the inspection target vias associated with the reference via V 1 , and the vias V 1  and V 3  to V 7  as the inspection target vias associated with the reference via V 2 , as shown in  FIG. 5   a , clearance inspection directions such as shown in  FIG. 5   b  (inspection lines shown by dashed lines in the figure) are obtained. As can be seen, by merely applying the first embodiment of the present invention to the clearance inspection, the amount of the computation to be performed by computer can be reduced compared with the prior art, as already described.  
         [0060]     In the second embodiment of the present invention, of the inspection target vias in  FIG. 5   b , the vias to be used for the clearance inspection are further limited to those vias between which the wiring lines pass, in order to further reduce the amount of computation and thereby enhance the efficiency of the process.  
         [0061]     Here, an explanation will be given by taking as a specific example the case where the wiring lines N 1  to N 11  are routed as shown in  FIG. 5   c.    
         [0062]     First, the inspection target vias determined in accordance with the first embodiment are regarded as inspection candidate vias in the second embodiment.  
         [0063]     In this case, on a virtual plane in which the direction along which the via row containing the reference via extends is taken as a reference coordinate axis, if the inspection line formed by joining the reference via to an inspection candidate via crosses a wiring line in such a manner as to point in approximately the same direction as the wiring line on the virtual plane, the clearance inspection is not performed along the clearance inspection direction defined by that inspection line. On the other hand, if the inspection line does not cross the wiring line in such a manner as to point in approximately the same direction as the wiring line on the virtual plane, that is, if the inspection line crosses the wiring line in such a manner as to face it, the clearance inspection is performed along the clearance inspection direction defined by that inspection line.  
         [0064]     For example, for the reference via V 1 , the inspection candidate vias are the vias V 2  to V 7 . Of these, the inspection line joining the via V 1  to the via V 3  crosses the wiring lines N 1  and N 2  in such a manner as to face them, and the inspection line joining the via V 1  to the via V 4  crosses the wiring line N 2  in such a manner as to face it. However, the inspection line joining the via V 1  to the via V 7 , for example, crosses the wiring lines N 7  and N 8  in such a manner as to point in approximately the same direction as the wiring lines. Accordingly, for the reference via V 1 , of the inspection candidate vias V 2  to V 7  the vias V 3  and V 4  are determined as the inspection target vias.  
         [0065]     Further, for the reference via V 2 , for example, the inspection candidate vias are the vias V 1  and V 3  to V 7 . Of these, the inspection line joining the via V 2  to the via V 4  crosses the wiring lines N 2  to N 11  in such a manner as to oppose them, the inspection line joining the via V 2  to the via V 5  crosses the wiring lines N 5  to N 11  in such a manner as to face them, and the inspection line joining the via V 2  to the via V 6  crosses the wiring lines N 8  to N 11  in such a manner as to face them. Accordingly, for the reference via V 2 , of the inspection candidate vias V 1  and V 3  to V 7  the vias V 4  to V 6  are determined as the inspection target vias.  
         [0066]     As described above, in the present embodiment, each inspection line is classified according to whether the inspection line crosses a wiring line in such a manner as to point in approximately the same direction as the wiring line or in such a manner as to face it, on the virtual plane in which the direction along which the via row containing the reference via extends is taken as the reference coordinate axis; the reason for this is that, by performing the inspection along the clearance inspection direction defined by the inspection line that crosses the wiring line in such a manner as to face it, the clearance which provides a measure of wiring density can be captured more accurately than by performing the inspection along the clearance inspection direction defined by the inspection line that crosses the wiring line in such a manner as to point in approximetely the same direction as the wiring line. Here, an explanation will be given of a specific example of how the crossing of the inspection line and the wiring line is judged.  
         [0067]      FIGS. 6   a  to  6   d  are diagrams for explaining one specific example of how the crossing of the inspection line and the wiring line is judged in the clearance inspection apparatus according to the second embodiment of the present invention. Here, an xy coordinate plane, where the direction along which the via row containing the reference via extends is taken as the x-coordinate axis of the virtual plane, is defined as shown. In the figure, a thick line or a thin line indicates either the wiring line or the inspection line; for example, when the thick line is the wiring line, then the thin line is the inspection line, and conversely, when the thick line is the inspection line, then the thin line is the wiring line.  
         [0068]     In the present invention, on the virtual coordinate plane in which the via row containing the reference via is taken as the reference coordinate axis, if the slope of the inspection line and the slope of the wiring line that crosses the inspection line are equal in sign, it is judged that the inspection line crosses the wiring line in such a manner as to point in approximately the same direction as the wiring line on the virtual plane, but if they are opposite in sign, it is judged that the inspection line does not cross the wiring line in such a manner as to point in approximately the same direction as the wiring line on the virtual plane, that is, the inspection line crosses the wiring line in such a manner as to face it.  
         [0069]     Whether the slope of the inspection line and the slope of the wiring line are equal in sign or opposite in sign can be easily determined by calculating the product of the slopes or the quotient of one divided by the other. For example, when the product of the slope of the inspection line and the slope of the wiring line is calculated, if the sign of the product is positive which means that the slopes have the same sign, it is judged that the inspection line crosses the wiring line in such a manner as to point in the same tending direction as the wiring line on the virtual plane, but if the sign of the product is negative which means that the slopes have different signs, it is judged that the inspection line does not cross the wiring line in such a manner as to point in the same tending direction as the wiring line on the virtual plane, that is, the inspection line crosses the wiring line in such a manner as to oppose it. The same applies to the case where the quotient between the slopes is calculated.  
         [0070]     In the examples shown in  FIGS. 6   a  and  6   d , as the product of the slope of the inspection line and the slope of the wiring line that crosses it is positive in sign, it is judged that the inspection line crosses the wiring line in such a manner as to point in the same tending direction as the wiring line on the virtual plane. In the examples shown in  FIGS. 6   b  and  6   c , as the product of the slope of the inspection line and the slope of the wiring line that crosses it is negative in sign, it is judged that the inspection line does not cross the wiring line in such a manner as to point in the same tending direction as the wiring line on the virtual plane, that is, the inspection line crosses the wiring line in such a manner as to oppose it.  
         [0071]      FIG. 7  is a flowchart showing the operation flow of the clearance inspection apparatus according to the second embodiment of the present invention.  
         [0072]     First, in step S 201 , the reference via that serves as the reference in the clearance inspection is determined. Next, in step S 202 , a second via row adjacent to the first via row to which the reference via belongs is determined. Next, in step S 203 , vias belonging to the first via row and adjacent and on both sides of the reference via are determined as first adjacent vias. Next, in step S 204 , vias belonging to the second via row and adjacent to the respective first adjacent vias are determined as second adjacent vias. Then, in step S 205 , each via that belongs to the second via row and that is located between the second adjacent vias is determined as an inspection candidate via. Next, in step S 206 , for each candidate via, the inspection line joining the reference via to the candidate via is set. Next, in step S 207 , on the virtual plane in which the direction along which the via row containing the reference via extends is taken as the reference coordinate axis, it is judged whether the wiring line that crosses the inspection line joining the reference via to the inspection candidate via crosses the inspection line in such a manner as to point in the same tending direction as the inspection line on the virtual plane. If it is judged in step S 207  that the wiring line does not cross the inspection line in such a manner as to point in the same tending direction as the inspection line on the virtual plane, then in step S 208  the inspection candidate via associated with the inspection line is determined as the inspection target via. In step S 209 , it is determined whether the above process has been completed on all the vias. The clearance inspection need only be performed only on the wiring line or lines passing between the reference via and the inspection target via. Each via on the substrate is sequentially determined as the reference via, and thus the clearance inspection is performed over the entire surface of the substrate.  
         [0073]     Here, the principle of operation in steps S 201  to S 205  is the same as that in steps S 101  to S 105  in  FIG. 3 , and the inspection candidate vias determined in step S 205  corresponds to the inspection target vias determined in step S 105 . In the above process, the order of the steps S 202  and S 203  may be interchanged.  
         [0074]     The above steps S 201  to S 209  according to the present embodiment are executed by a processing unit such as a computer. Here, it is preferable that design data, rules concerning clearances, and other data such as the coordinates, shape, size, and orientation of each via, substrate information, etc. be entered into the processing unit prior to the execution of step S 201 . By using the thus entered data, the processing unit initiates processing in step S 201 .  
         [0075]      FIGS. 8   a  to  8   d  are diagrams (part  1 ) for explaining, by way of a specific example, the process performed by the clearance inspection apparatus according to the second embodiment of the present invention. In the figure, reference characters V 1  to V 5  are the identification numbers of the vias, reference characters N 1  to N 9  are the identification numbers of the wiring lines, and reference characters A 1  and A 2  are the identification numbers of the via rows (indicated by semi-dashed lines in the figure).  
         [0076]     This specific example considers the case where the vias V 3  to V 5  are designated as the inspection candidate vias associated with the reference vias V 1  and V 2 , and the wiring lines N 1  to N 9  are routed between the vias, as shown in  FIG. 8   a.    
         [0077]     For the reference via V 1 , there are a total of three possible inspection lines from the reference via V 1  to the respective inspection candidate vias V 3 , V 4 , and V 5 . Of these, the inspection line joining the reference via V 1  to the inspection candidate via V 3  does not cross any wiring line, as shown in  FIG. 8   b ; therefore, there is no need to perform the clearance inspection along the clearance inspection direction defined by this inspection line. On the other hand, the inspection line joining the reference via V 1  to the inspection candidate via V 4  crosses the wiring lines N 1  to N 4  in such a manner as to oppose them, as shown in  FIG. 8   b ; therefore, the clearance inspection direction defined by this inspection line is taken as a clearance inspection target. That is, the inspection candidate via V 4  is determined as the inspection target via for the reference via V 1 . Further, as shown in  FIG. 8   c , the inspection line joining the reference via V 1  to the inspection candidate via V 5  crosses the wiring lines N 1  to N 4  in such a manner as to oppose them, but crosses the wiring lines N 6  to N 8  in such a manner as to point in the same tending direction as the wiring lines; therefore, the clearance inspection direction defined by this inspection line is not taken as a clearance inspection target.  
         [0078]     For the reference via V 2 , there are a total of three possible inspection lines from the reference via V 2  to the respective inspection candidate vias V 3 , V 4 , and V 5 . Of these, the inspection line joining the reference via V 2  to the inspection candidate via V 5  does not cross any wiring line, as shown in  FIG. 8   b ; therefore, there is no need to perform the clearance inspection along the clearance inspection direction defined by this inspection line. On the other hand, the inspection line joining the reference via V 2  to the inspection candidate via V 4  crosses the wiring lines N 6  to N 9  in such a manner as to oppose them, as shown in  FIG. 8   b ; therefore, the clearance inspection direction defined by this inspection line is taken as a clearance inspection target. That is, the inspection candidate via V 4  is determined as the inspection target via for the reference via V 2 . Further, as shown in  FIG. 8   d , the inspection line joining the reference via V 2  to the inspection candidate via V 3  crosses the wiring lines N 6  to N 9  in such a manner as to oppose them, but crosses the wiring lines N 2  to N 4  in such a manner as to point in the same tending direction as the wiring lines; therefore, the clearance inspection direction defined by this inspection line is not taken as a clearance inspection target.  
         [0079]     For the wiring lines passing between the vias V 1  and V 2 , the clearance inspection should be performed as usual.  
         [0080]      FIGS. 9   a  and  9   b  are diagrams (part 2) for explaining, by way of specific example, the process performed by the clearance inspection apparatus according to the second embodiment of the present invention. In the figure, reference characters V 1  to V 5  are the identification numbers of the vias, reference characters N 1  to N 4  are the identification numbers of the wiring lines, and reference characters A 1  and A 2  are the identification numbers of the via rows (indicated by semi-dashed lines in the figure).  
         [0081]     This specific example considers the case where the vias V 3  to V 5  are designated as the inspection candidate vias associated with the reference vias V 1  and V 2 , and the wiring lines N 1  to N 4  are routed passing between the vias, as shown in  FIG. 9   a.    
         [0082]     For the reference via V 1 , the inspection line joining the reference via V 1  to the inspection candidate via V 4  crosses the wiring lines N 1  and N 2  in such a manner as to oppose them, as shown in  FIG. 9   b ; therefore, the clearance inspection direction defined by this inspection line is taken as a clearance inspection target. That is, the inspection candidate via V 4  is determined as the inspection target via for the reference via V 1 , and the clearance inspection directions associated with the other vias are excluded from the clearance inspection targets.  
         [0083]     On the other hand, for reference via V 2 , as shown in  FIG. 9   b , the inspection line joining the reference via V 2  to the inspection candidate via V 4  crosses the wiring lines N 3  and N 4  in such a manner as to oppose them, and the inspection line joining the reference via V 2  to the inspection candidate via V 5  crosses the wiring line N 4  in such a manner as to oppose it; therefore, the clearance inspection directions defined by these inspection lines are taken as clearance inspection targets. That is, the inspection candidate vias V 4  and V 5  are determined as the inspection targets via for the reference via V 2 , and the clearance inspection directions associated with the other vias are excluded from the clearance inspection targets.  
         [0084]      FIGS. 10   a  to  10   c  are diagrams (part  3 ) for explaining, by way of specific example, the process performed by the clearance inspection apparatus according to the second embodiment of the present invention. In the figure, reference characters V 1  to V 4  are the identification numbers of the vias, reference characters N 1  to N 8  are the identification numbers of the wiring lines, and reference characters A 1  and A 2  are the identification numbers of the via rows (indicated by semi-dashed lines in the figure).  
         [0085]     In this specific example, the wiring lines N 2  to N 7  are routed passing between the vias V 1  and V 2 , but only the wiring lines N 4  and N 5  are routed passing between the vias V 3  and V 4 , as shown in  FIG. 10   a ; that is, the wiring lines N 1  to N 4  and the wiring lines N 5  to N 8  are routed in such a manner as to spread in respectively different directions. In this case, as shown in  FIG. 10   b , the inspection line joining the reference via V 1  to the inspection candidate via V 4  crosses the wiring lines N 2  to N 4  in such a manner as to oppose them, but crosses the wiring line N 5  in such a manner as to point in the same tending direction as the wiring line N 5 ; therefore, the clearance inspection direction defined by this inspection line is not taken as a clearance inspection target. Likewise, as shown in  FIG. 10   c , the inspection line joining the reference via V 2  to the inspection candidate via V 3  crosses the wiring lines N 5  to N 7  in such a manner as to oppose them, but crosses the wiring line N 4  in such a manner as to point in the same tending direction as the wiring line N 4 ; therefore, the clearance inspection direction defined by this inspection line is not taken as a clearance inspection target. That is, in the case of  FIG. 10   a , it is sufficient to perform the clearance inspection on the wiring lines N 2  to N 7  passing between the vias V 1  and V 2  and on the wiring lines N 4  and N 5  passing between the vias V 3  and V 4 .  
         [0086]     As described above, according to the second embodiment of the present invention, and as, of the inspection target vias designated in the first embodiment, the vias to be used for the clearance inspection are further limited to those vias between which the wiring lines pass, the amount of computation performed by computer can be further reduced.  
         [0087]      FIG. 11  is a diagram showing one specific example of the inspection pattern illustrating the clearance inspection directions obtained by the clearance inspection apparatus according to the second embodiment of the present invention. In the figure, reference characters V 1  to V 11  are the identification numbers of the vias, reference characters N 1  to N 7  are the identification numbers of the wiring lines, and reference characters A 1  to A 3  are the identification numbers of the via rows (indicated by semi-dashed lines in the figure). When the clearance inspection method of the present embodiment is applied to the substrate on which the vias are formed as shown in the figure, the clearance inspection directions along which the wiring lines passing between the vias are to be inspected for clearance are those defined along the inspection lines indicated by dashed lines.  
         [0088]      FIG. 12  is a diagram showing a table defining the combinations of the reference vias and their associated inspection target vias. The clearance inspection directions obtained by the clearance inspection apparatus of the present embodiment can be expressed in the form of a table defining the combinations of the reference vias and their associated inspection target vias. For example, this table shows that when the via V 10  in the via row A 1  is the reference via, the vias V 11  and V 7  are the inspection target vias. In this way, when the data concerning the table in which the reference vias are stored along with their associated inspection target vias is created using a computer, it becomes easier to implement the clearance inspection by using the created data. Such a table may be constructed in the first embodiment as well.  
         [0089]     The present invention may be carried out in combination with the invention disclosed in Japanese Unexamined Patent Publication No. 2002-083006. In the invention disclosed in this Patent Document 1, only wiring routes are determined in advance in a rough wiring step, and then, in a wiring forming step, the wiring lines are laid automatically and uniformly by considering clearances (lines and spaces) while checking them against the actual design rules. In the invention disclosed in the above Patent Document 1, clearances in the circumferential direction along which the via rows are arranged (hereinafter called the “horizontal direction”) have been inspected during the automatic wiring process, but clearances in the direction directed from the innermost circumference toward the outermost circumference (hereinafter called the “vertical direction”) or in oblique directions have not been inspected. Accordingly, when the present invention is used in combination, it also becomes possible to efficiently perform the clearance inspection along the vertical and oblique directions in the invention disclosed in Patent Document 1, and this offers an enormous effect. When carrying out the present invention in combination with the invention disclosed in the above Patent Document 1, the auxiliary lines used to determine the wiring routes in the invention disclosed in Patent Document 1 should be used by regarding each of them as a “via row” which is one of the parameters used in the present invention.  
         [0090]     According to the present invention, as the clearance inspection is performed only for those vias between which the wiring lines pass, the amount of computation necessary for the clearance inspection can be drastically reduced, compared with the prior art which requires performing the clearance inspection for all the vias. As a result, the manufacturing cost of semiconductor packages can be reduced.  
         [0091]     For example, the present invention can drastically reduce the amount of the computation to be performed by computer in the clearance inspection when designing wiring for a semiconductor package such as a PBGA or an EBGA package. Accordingly, as the time required for the clearance inspection is reduced and the designer can obtain the inspection results quickly, the designer whose burden is alleviated can further concentrate his effort on the design work, and a further improvement in design quality can thus be expected.  
         [0092]     Further, when the present invention is carried out in combination with the invention disclosed in Japanese Unexamined Patent Publication No. 2002-083006, more efficient automatic wiring design can be achieved.