Abstract:
The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench- isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention. In addition, the contacts are implemented over the trench-isolation regions, the effective area per device is much reduced by using the present invention as compared to existing device structure and its implementation. As a consequence, the present invention offers a semiconductor device structure for high-density and high-performance integrated-circuits implementation.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to semiconductor integrated-circuits manufacturing and more particularly to a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits.  
           [0003]    2. Description of Related Art  
           [0004]    The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a major device for existing very high-density integrated-circuits manufacturing. Basically, there are two kinds of regions for integrated-circuits implementation in a semiconductor substrate: one is the active area and the other is the isolation area. The active area is the exposed semiconductor surface for device fabrication, which is surrounded by the isolation regions having thicker dielectric oxides over the semiconductor surface. The isolation area can be formed by the local oxidation of silicon (LOCOS) as shown in FIG. 1 or by the shallow-trench-isolation (STI) as shown in FIG. 2. In general, the LOCOS isolation needs higher temperature to grow the desired field oxides (FOX)  202   a  and the bird&#39;s beak having a width ΔW in each side is formed in the designated active area. Moreover, the doping impurities of the field-encroachment implant  201   a  used to increase the field threshold-voltage may diffuse into the active area and further decreases the active area, resulting in the so-called narrow-width effects. In addition, the structure surface after forming LOCOS isolation is not planarized, which becomes difficult for fine-line lithography. For the minimum-feature-size smaller than 0.25 μm, the shallow-trench-isolation as shown in FIG. 2 becomes a major trend for deep-submicrometer devices and their integrated-circuits fabrication. Comparing FIG. 1 to FIG. 2, it is clearly seen that the isolation area of using LOCOS is much larger than that of using STI due to the bird&#39;s beak formation and the doping-impurity diffusion of the field-encroachment implant. However, the device structure fabricated in the active area is still the same although the device dimension can be scaled according to the scaling rule based on device physics. For a semiconductor device in the channel-length direction (A-A′) as shown in FIG. 2B, there are a thin gate-oxide layer  302  formed on a semiconductor substrate  100 , a highly-conductive gate layer  303   a  on a thin gate-oxide layer  302 , a capped dielectric layer  304   a  over the highly-conductive gate layer  303   a , two dielectric spacers  306   a  formed along the sidewalls of the formed gate structure, two lightly-doped source and drain regions  305   a , two heavily-doped source and drain regions  307   a , two silicided regions  308   a  for source and drain contacts, two barrier-metal layers  310   a , two plug-metal films  311   a  and two metal layers  312   a  for interconnect. As shown in FIG. 2C for the channel-width direction (B-B′), it is quite clear that the shallow-trench-isolation reduces largely the isolation area without sacrificing too much active area for capping the trench comers using the capping-oxide layer  301   b . However, it is apparently seen from FIG. 1B and FIG. 2B that the heavily-doped source and drain regions occupy almost 70% of the active area and most of them are prepared for contacts. As a consequence, the source and drain junction capacitances which may limit the switching speed or the operating frequency of devices can not be easily scaled according to the scaling rule and the generation/recombination currents due to the depletion regions of the source and drain junctions become one of the major sources of device leakage currents. Moreover, the shallow source and drain junctions which are needed to reduce the short-cannel effects become a challenge for contact technology without producing the contact-induced defects.  
           [0005]    It is therefore a first objective of the present invention to substantially reduce the area of the heavily-doped source and drain regions of a device in the active region, so that the junction capacitances of the heavily-doped source and drain regions with respect to the semiconductor substrate in the active region are reduced accordingly. As a result, high-speed and high-frequency operations of devices of the present invention for manufacturing integrated-circuits can be expected. Since the reduced heavily-doped source and drain regions are resided on the trench-isolation regions, it is therefore a second objective of the present invention to substantially reduce the generation/recombination currents in the depletion regions of the heavily-doped source and drain junctions. Moreover, the heavily-doped source and drain regions resided on the trench-isolation regions are the silicided conductive semiconductor layers for contacts or interconnections, it is a third objective of the present invention to eliminate the contact-induced source and drain junction failure or leakage currents. In addition, the effective area of a device is much reduced, it is therefore a fourth objective of the present invention to offer high-density devices for manufacturing high-density integrated-circuits.  
         SUMMARY OF THE INVENTION  
         [0006]    Methods of fabricating a semiconductor device structure having low source and drain junction capacitances and low junction leakage currents are disclosed by the present invention, in which the major portions of the heavily-doped source and drain regions of a device in the active region are implemented in a self-aligned manner over the trench-isolation region by using highly-conductive silicided polycrystalline or amorphous-semiconductor layers. The device structure of the present invention exhibits several remarkable features as compared to those of existing device structure. The first feature of the present invention is very low source and drain junction capacitances, so much higher switching speed or operating frequency can be obtained by using a device structure of the present invention for manufacturing high-density integrated-circuits. The second feature of the present invention is very small area for the depletion regions of the heavily-doped source and drain junctions, the generation/recombination currents in the depletion regions of the source and drain junctions and the conventional diffusion current can be much reduced, so ultra-low standby leakage current can be obtained for manufacturing high-density integrated-circuits. The third feature of the present invention is that the contacts of the source and drain regions of a device are resided on the trench-isolation region, the contact-induced defects or spikings for shallow source and drain junctions can be eliminated, the elaborate contact technologies are not required and the yield problems of integrated-circuits manufacturing due to the excess leakage current or junction failures are eliminated. The fourth feature of the present invention is that the effective area occupied by each device of the present invention is much smaller as compared to that of existing devices, integrated-circuits of much higher density can be manufactured by the present invention. As a consequence, the present invention can be used to manufacture integrated-circuits with high-density, high-speed and ultra-low standby leakage current. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1A through FIG. 1C show a top view and the schematic cross-sectional views of a device fabricated by using conventional LOCOS isolation;  
         [0008]    [0008]FIG. 2A through FIG. 2C show a top view and the schematic cross-sectional views of a device fabricated by using existing shallow-trench-isolation;  
         [0009]    [0009]FIG. 3A through FIG. 3C show a top view and the schematic cross-sectional views of a device fabricated by the present invention using advance shallow-trench-isolation; and  
         [0010]    [0010]FIG. 4A through FIG. 4K show the schematic cross-sectional views of the process steps and the structures of devices fabricated by the present invention using advance shallow-trench-isolation. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0011]    Referring now to FIG. 3A through FIG. 3C, there are shown a top view and the cross-sectional views of the present invention. FIG. 3A shows a top view of a device fabricated in an active region  118  isolated by using new shallow-trench-isolation techniques having the capping-oxide spacers  103   a  formed in the trench-isolation regions  106  (FOX) and the thin-oxide layers  105   a  and the trench-surface encroachment implant regions  102   b . The source and drain contact cuts  119   a  are formed on the heavily-doped source and drain regions  112   b  made by using a highly-conductive polycrystalline-silicon or amorphous-silicon film capped by a silicide layer  113   a . The conductive gate layer  108   a  is a doped ploycrystalline-silicon or amorphous-silicon layer capped by a silicide layer. The metal layers  117   a  are used to form the first-level interconnections of the source and the drain of the present device to the source and the drain of other devices. FIG. 3B shows a cross-sectional view in the channel-length direction (A-A′), in which the gate insulator layer  107   a  is formed on a retrograde-well  101   a  over the semiconductor substrate  100 , the conductive gate layer  108   a  is formed on the gate insulator layer  107   a , a capping-oxide layer  109   a  is formed on the conductive gate layer  108   a , a masking dielectric layer  109   b  preferably made of silicon-nitrides is formed on the capping-oxide layer  109   a . The silicon-nitride spacers  111   a  are formed on the sidewalls of the gate region and over the gate insulator layer  107   a . The lightly-doped source/drain regions  110   a  and the heavily doped source/drain regions  112   a  are formed in a retrograde-well  101   a  over the semiconductor substrate  100 . The major portions of the heavily-doped source/drain regions are formed on the trench field-oxide (FOX) layers  106  using highly-conductive polycrystalline-silicon or amorphous-silicon layer linked with the heavily-doped source/drain regions  112   a  formed in a retrograde-well  101   a  over the semiconductor substrate  100  directly and further capped by the silicide layers  113   a . The contact cuts  119   a  through the planarized dielectric layer  114   a  are filled with the barrier-metal layers  115   a  and the plug-metal films  116   a . FIG. 3C shows a cross-sectional view in the channel-width direction (B-B′), in which the capping-oxide spacers  103   a  formed in the trench-isolation region are surrounding the corners of the active region  118  to eliminate the field emission from the corners of the active region without sacrificing the active area  118 . Moreover, the trenched surface is oxidized to form the thin-oxide layers  105   a  and is properly implanted to form the field-encroachment implant regions  102   b , the leakage current due to the generation/recombination current from the depletion regions and the interface traps of the trench surfaces can be much reduced or eliminated.  
         [0012]    Apparently, a device structure of the present invention shown in FIG. 3A through FIG. 3C exhibits the following features: very small source/drain junction capacitances; very small source/drain junction leakage currents; very small device area occupied including the active area and the isolation area. The detailed process steps of manufacturing a device structure of the present invention shown in FIG. 3A through FIG. 3C are described below, as shown in FIG. 4A through 4K.  
         [0013]    Referring now to FIG. 4A, it is shown a cross-sectional view in the channel-length direction (A-A′ shown in FIG. 3B) in which the shallow-trench-isolation (STI) technique is used to form the trench-isolation regions  106   a  and  106   b  as marked by FOX. The trench surfaces are oxidized to have a thin-oxide layer  105   a  formed in order to eliminate the trench etching-induced defects and followed by the field-encroachment implant to form the implanted regions  102   b  using rotated large-tilt-angle implantation. As shown in FIG. 4A, the thin-oxide layer  105   a  and the implanted regions  102   b  at the top surface are located under the capping-oxide spacers  103   a  formed in the trench-isolation regions and formed on the sidewalls of the patterned multilayer masking structure using the masking photoresist PR 1  (not shown). The capping-oxide spacers  103   a  are very important to eliminate the field emission from the trench corners to the conductive gate layer  108  as shown in FIG. 3C. After forming a thin gate-dielectric layer  107  in the active regions, a conductive gate layer  108  is deposited. The conductive gate layer  108  can be a doped polycrystalline-silicon or doped amorphous-silicon layer further capped with a silicide layer. A masking dielectric layer  109  is then formed over the conductive gate layer  108  and can be a silicon-nitride layer or a composite layer having a masking silicon-nitride layer  109   b  on a silicon-oxide layer  109   a . The masking photoresist PR 3  is formed on the whole structure and then is patterned to define the gate-lengths (L G ) of devices and the gate interconnections using the conductive gate layer  108  as shown in FIG. 3A for a single device and FIG. 4A for multiple devices. It is noted that two trench-isolation widths are demonstrated in FIG. 4A for two-kinds of device interconnection, in which the narrow one in the left-hand side is used for common-source/ common-drain contact and the wider one in the right-hand side is used for separate source/drain contacts.  
         [0014]    It should be emphasized that the semiconductor substrate  100  shown in FIG. 3 and FIG. 4 can be a p-type semiconductor substrate or an n-type semiconductor substrate. For simplicity, the retrograde p-wells  101   a  are formed over the semiconductor substrate  100  using the masking photoresist PR 2 A (not shown) and the devices shown are n-channel MOSFETs. Moreover, the shallow-trench-isolation structure shown is only for demonstration, other shallow-trench-isolation structure or isolation techniques can also be used to fabricate the device structure of the present invention.  
         [0015]    The patterned masking photoresist PR 3  shown in FIG. 4A is used as a mask to form the gate structures shown in FIG. 4B through the selective etchings of the masking dielectric layer  109  and the conductive gate layer  108  using anisotropic dry etchings and the patterned masking photoresist PR 3  is then stripped. The ion-implantation is performed in a self-aligned manner to form the lightly-doped source/drain regions  110  of the devices using a patterned masking photoresist PR 4 A (not shown) and then stripping the patterned masking photoresist PR 4 A, as shown in FIG. 4B.  
         [0016]    [0016]FIG. 4C shows that the dielectric spacers  111   a  are formed on the sidewalls of the formed conductive gate regions. The dielectric spacers  111   a  can be formed by depositing a conformable dielectric layer over the formed gate structure followed by etching back using anisotropic dry etching. The conformable dielectric layer is preferably deposited by low-pressure chemical-vapor-deposition (LPCVD) and is preferably made of silicon-nitrides. The halo-implant using a patterned masking photoresist PR 5 A (not shown) can be performed by using large-tilt-angle implantation to improve the punch-through voltage of devices and then stripping the patterned masking photoresist PR 5 A. However, the junction depth of the heavily-doped source/drain junctions in the active regions can be very shallow because the major portions of the heavily-doped source/drain regions are located in the trench-isolation regions using highly-conductive semiconductor layer  112   b  and are also used as the contact regions, the punch-through voltage of devices would be larger for devices of the present invention as compared to that of traditional devices.  
         [0017]    [0017]FIG. 4D shows the oxides including a thin gate dielectric layer  107 , the capping-oxide spacers  103   a , the thin-oxide layer  105   a  and the trench field-oxide  106   a  and  106   b  outside of the dielectric spacers  111   a  as shown in FIG. 4C are selectively etched in a self-aligned manner to a depth approximately equal to or slightly larger than the junction depth of the lightly-doped source and drain regions  110 .  
         [0018]    [0018]FIG. 4E shows that the formed structure shown in FIG. 4D is filled with a conformable thick conductive semiconductor film  112   b  to a level over the top level of the masking dielectric layer  109   a  and the planarization of the filled thick conductive semiconductor film  112   b  is performed preferably by chemical-mechanical polishing (CMP) using the masking dielectric layer  109   a  as a polishing stop. The conformable thick conductive semiconductor film can be a doped polycrystalline-silicon or doped amorphous-silicon film deposited by LPCVD. The masking photoresist PR 6  is formed and patterned to define the source/drain interconnect and the contact area of devices, as shown in a top view of FIG. 3A. As shown in FIG. 4F, the patterned masking photoresist PR 6  is used as a mask to perform the etching of the planarized conductive semiconductor film  112   b  and then the patterned masking photoresist PR 6  is stripped.  
         [0019]    As shown in FIG. 4G, the remained conductive semiconductor films  112   b  shown in FIG. 4F are anisotropically etched back in a self-aligned manner to a depth approximately equal to the top level of the thin gate-dielectric layer  107  or slightly higher than the top level of the thin gate-dielectric layer  107  using anisotropic dry etching. The ion-implantation is then performed to form the heavily-doped source and drain regions  112   a  in the retrograde-wells  101   a  over the semiconductor substrate  100  and the remained conductive semiconductor layer  112   b  using a patterned masking photoresist PR 7 A (not shown), as shown in FIG. 4G.  
         [0020]    [0020]FIG. 4H shows a refractory metal layer  113  is deposited, followed by annealing in a N 2  ambient to form the silicide layer over the heavily-doped source/drain regions  112   a  formed in the retrograde-wells  101   a  over the semiconductor substrate  100  and the polycrystalline-silicon or amorphous-silicon layers  112   b  on the trench-isolation regions  106   a  and  106   b  and the metal-nitride layer over the silicide layer and the dielectric layer such as silicon-nitride or silicon-oxide. The preferred refractory metal is titanium or cobalt, so the silicide layer is titanium-disilicide (TiSi 2 ) or cobalt-disilicide (CoSi 2 ) and the metal-nitride layer is titanium-nitride (TiN) or cobalt-nitride (CoN). Using a wet-chemical solution of NH 4 OH:H 2 O 2 :H 2 O (1:1:5), the titanium-nitride or cobalt-nitride layers are removed and the titanium-disilicide or cobalt-disilicide layers  113   a  over silicon (mono- or poly- or amorphous-silicon) are remained, as shown in FIG. 4I. A thick interlayer dielectric film  114  is then deposited, followed by planarizing the deposited thick interlayer dielectric film  114  using CMP. The thick interlayer dielectric film  114  is preferably made of silicon-oxides doped with boron and phosphorous impurities (BP glass) and is preferably deposited by high-density plasma CVD. The masking photoresist PR 8  is formed on the planarized thick interlayer dielectric layer  114  and is then patterned as shown in FIG. 4I to open the contact holes.  
         [0021]    [0021]FIG. 4J shows that the contact holes are filled with the barrier-metal layers  115   a  and the plug-metal films  116   a , followed by planarizing the structure surface using CMP to remove the excess barrier-metal and plug-metal films over the planarized thick interlayer dielectric film  114 . The barrier-metal layer  115   a  is preferably a titanium-nitride layer deposited by sputtering or CVD and the plug-metal film  116   a  is preferably a tungsten film deposited by sputtering or CVD. The first-level interconnection metal layer  117  is deposited as shown in FIG. 4J and is then patterned and etched by the patterned masking photoresist PR 9  as shown in FIG. 4J to form the first-level interconnection metal layer  117   a , followed by stripping the patterned masking photoresist PR 9 . The first-level interconnection metal layer  117  can be a composite metal layer consisting of a AlCu alloy film over a TiN layer or a copper layer over a barrier-metal layer. The finished structure is shown in FIG. 4K. The multi-level interconnection can be easily formed by using the well-known arts.  
         [0022]    The embodiments shown in FIG. 3 through FIG. 4 use retrograde p-wells formed over a semiconductor substrate  100  for demonstration only. It should be well understood by those skilled in the art that the opposite doping type of the retrograde-wells can also be used to simultaneously fabricate the opposite conductivity type of devices for integrated-circuits implementation by using the methods as disclosed by the present invention with only modification of the implant doping type using the additional patterned masking photoresist having a mask of the reverse tone.  
         [0023]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the true spirit and scope of the invention.