Abstract:
A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional and claims priority to U.S. application Ser. No. 11/495,649, filed Jul. 31, 2006 now U.S. Pat. No. 7,768,116, which in turn claims the benefit of Korean Patent Application 10-2005-0090019 filed with the Korean Intellectual Property Office on Sep. 27, 2005, the disclosures of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     1. Field 
     The present invention relates to a semiconductor package substrate and a method for fabricating the same. More particularly, the present invention relates to a semiconductor package in which a circuit layer formed on the wire bonding pad side is different in thickness from a half-etched circuit layer formed on the ball pad side and which has a connection through hole through which the plating lead lines of the wire bonding pad side and the ball pad side are electrically connected, so that electrical disconnection is prevented when the plating lead line of the wire bonding pad is cut, and a method for fabricating the same. 
     2. Description of the Related Art 
     With the evolution of electronics towards slimness, lightness and high performance, a great advance in technology for fine circuit patterns has been recently achieved on BGA package substrates. 
     Particularly, fine circuit patterns are extensively required in CSP (chip-sized package) products, which have semiconductor chips mounted on BGA package substrates. 
     In order to better understand the background of the invention, a conventional method of fabricating a semiconductor package substrate will be described with reference to  FIGS. 1A to 1H . 
     As shown in  FIG. 1A , a copper clad laminate (CCL)  100  comprising an insulation layer  102  covered with a copper foil  101 , which is provided as a base substrate, is drilled to form therein via holes for electric communication between circuit layers. There are a variety of CCLs including glass/epoxy CCLs, heat resistant CCLs, paper/phenol CCLs, CCLs for use in radio frequencies, flexible CCLs (polyimide film) and composite CCLs, which are used according to purpose. For example, glass/epoxy CCLs are suitable for the fabrication of double-sided PCBs and multilayer PCBs. 
     Then, the opposite sides of the CCL  100  and the inner walls of the via holes are subjected to electroless plating and then to electroplating, as shown in  FIG. 1B . Requiring electricity, electroplating cannot be conducted on the insulation layer  102 . Usually, an insulator is electroless plated prior to being electroplated. Thus, copper is electroless plated and then electroplated on the insulation layer  102 . 
     Next, a filler is charged in the via holes  103 , followed by the formation of an etching resist pattern  105  as shown in  FIG. 1C . In regard to the etching resist pattern  105 , it is formed using a dry film (D/F) and a circuit pattern printed film (artwork film) on the copper-electroplated substrate. 
     There are various techniques available for the formation of the resist pattern  105 , with a dry film technique prevailing. 
     A dry film for use in forming the resist pattern, abbreviated to D/F, is usually comprised of a cover film, a photoresist film and a Mylar film. The photoresist film actually serves as a resist. 
     While being stripped of the cover film, the dry film is applied to a bare PCB. A circuit pattern-printed artwork film is stuck fast onto the dry film, followed by UV irradiation. UV light cannot penetrate through the dry film at the dark portion of the pattern of the artwork film, but penetrates through otherwise portions to cure the exposed portion of the dry film. Then, the substrate is immersed in a developing solution to remove the uncured portions of the dry film while the cured portions remain to form a resist pattern. A 1% sodium carbonate (Na 2 CO 3 ) or potassium carbonate (K 2 CO 3 ) solution is suitable as a developing solution. 
     Afterwards, as shown in  FIG. 10 , the CCL  100  is treated with an etchant while the etching resist pattern  105  serves as a mask, so as to form a circuit pattern. 
     Subsequently, the etching resist  105  is removed with a peeling solution such as an NaOH or KOH solution, as shown in  FIG. 1E . 
     All portions of the resulting CCL, except for a wire bonding pad  107 , a solder ball pad  108 , and the other portions connected to external substrates or chips, are coated with a photo solder resist  106  so as to protect the circuit, as shown in  FIG. 1F . 
     Using a plating lead line, thereafter, the CCL is plated with Ni/Au, with the photo solder resist serving as a plating resist, to form an Ni/Au layer  109 ,  109 ′ on the uncoated portions, that is, the wire bonding pad  107 , the solder ball pad  108  and the other connection portions, as shown in  FIG. 1G . Plating is conducted with Ni and then with Au. 
     Finally,  FIG. 1H  shows a package product obtained after the circuit pattern  110  serving as a plating lead line is cut using a router or a dicing process. 
     In CSP products, ball pitches have continued to decrease from 0.8 through 0.65 and 0.5 then to 0.4 mm. In addition, the balls require an OSP (organic solderability preservative) treatment so as to have a drop resistance the same level as that of substrates for mobile phones. However, the requirement causes contrast techniques to be performed on the substrate, as will be described below. 
     With reference to  FIG. 2 , a conventional semiconductor package substrate  210  is shown in a perspective view. As seen, the conventional semiconductor package substrate  210  is divided into a unit region, comprising a semiconductor device mounting portion  211   a  and an outer circuit pattern  211   b , and a dummy region  212 . 
     This conventional semiconductor package substrate requires contrast techniques which are used to keep the circuit layer at a small thickness so as to realize a fine pattern at the side of the wire bonding, but at a large thickness at the side of the balls so as to enable application of OSP and deep etching processes to the balls. 
     SUMMARY 
     Therefore, it is an object of the present invention to provide a semiconductor package device in which a circuit layer formed on a wire bonding pad side differs in thickness from a circuit layer formed on a ball pad side, and a method for fabricating the same. 
     It is another object of the present invention to provide a semiconductor package substrate which prevents electrical disconnection when a plating lead line of a wire bonding pad side is cut as a circuit layer is formed to a small thickness on the wire bonding pad side. 
     In accordance with an aspect of the present invention, provided is a semiconductor package substrate, comprising: an insulation layer; a first circuit layer, formed on one side of the insulation layer, for providing a ball pad; and a second circuit layer, formed on the other side of the insulation layer, for providing a wire bonding pad, said second circuit layer being thinner than said first circuit layer. 
     In accordance with another aspect of the present invention, provided is a method for fabricating a semiconductor package substrate, comprising: Step 1 of preparing a copper clad laminate and half-etching a copper foil on a wire bonding pad side of the copper clad laminate; Step 2 of depositing a first etching resist on the opposite sides of the copper clad laminate; Step 3 of forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; Step 4 of applying a solder resist to the copper clad laminate in such a way as to expose the wire bonding pad and the ball pad; and Step 5 of plating the wire bonding pad with gold and subjecting the ball pad to surface treatment. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The application of the preferred embodiments of the present invention is best understood with reference to the accompanying drawings, in which like reference numerals are used for like and corresponding parts, wherein: 
         FIGS. 1A to 1H  are schematic views showing processes of fabricating a conventional semiconductor package substrate; 
         FIG. 2  is a perspective view showing the conventional semiconductor package substrate; 
         FIG. 3  is a cross sectional view showing a semiconductor package substrate according to an embodiment of the present invention, in which a circuit layer formed on a wire bonding pad side differs in thickness from a circuit layer formed on a ball pad side; 
         FIGS. 4A to 4G  are cross sectional views showing processes of fabricating a semiconductor package substrate according to an embodiment of the present invention, in which a circuit layer formed on a wire bonding pad side differs in thickness from a circuit layer formed on a ball pad side; 
         FIGS. 5A to 5H  are cross sectional views showing processes of fabricating a semiconductor package substrate according to another embodiment of the present invention, in which a circuit layer formed on a wire bonding pad side differs in thickness from a circuit layer formed on a ball pad side; and 
         FIG. 6  is a perspective view showing a semiconductor package substrate in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Below, a detailed description is given of an embodiment of the present invention with reference to the accompanying drawings. 
       FIG. 3  is a cross sectional view showing a semiconductor package substrate according to an embodiment of the present invention, in which a circuit layer  304   a  on the side of a wire bonding pad differs in thickness from a circuit layer  304   b  on the side of a ball pad within a unit region. The circuit layer  304   a  of the wire bonding pad side is thinner than the circuit layer  304   b  of the ball pad side. 
     Within a dummy region, however, the thickness is identical between a circuit layer  304   ab  on the wide bonding pad side and a circuit layer bb on the ball pad side. 
     Thereby, when the circuit layer  304   a  on the wire bonding pad side in the unit region is thinner than the circuit layer  304   ab  on the wire bonding pad side in the dummy region and than the circuit layer  304   b  on the ball pad side in the unit region, a fine circuit pattern can be designed because the thickness of the circuit layer  304   a  has a great influence on the fineness of a circuit pattern. 
     On the wire pad side, the larger thickness of the circuit layer  304   ab  on the wire bonding pad side in the dummy region than that of the circuit layer  304   a  in the unit region prevents the distortion of substrate. 
     Additionally, the larger thickness of the circuit layer  304   b  on the ball pad side than that of the circuit layer  304   a  on the wire bonding pad side in the unit region allows OSP and deep etching processes to be applied to the ball pad side. In  FIG. 3 , reference numeral  302  refers to an insulation layer,  306   a  and  306   b  to photo solder resists,  304   aa  particularly to a wire bonding pad out of circular layer  304   a ,  304   ac  to a gold coat,  304   ba  to a ball pad, and  304   bc  to an OSP-treated surface. 
     A through-hole  307  serves to electrically connect a plating lead line (not shown) of the wire bonding pad side with that of the ball pad side. If the circuit layer  304   a  on the bonding pad side becomes thin, the thin plating lead line may be cut because it is contained in the circuit layer  304   a . When the cutting occurs, the through-hole  307  allows electric connection to the outside through a plating lead line (not shown) on the ball pad side. 
     Alternatively, the circuit layer  304   ab  on the wire bonding pad side in the dummy region may be as thick as the circuit layer  304   a  on the wire bonding pad side in the unit region, but differs in thickness from the circuit layer  304   b  on the ball pad side in the unit region. 
     With reference to  FIGS. 4A to 4G , a method for fabricating a semiconductor package substrate in which a circuit layer on a wire bonding side is different in thickness from that on a ball pad side are shown in a stepwise manner in accordance with an embodiment of the present invention. 
       FIG. 4A  is a cross sectional view of a CCL  400  comprising an insulation layer  402 , made from, for example, epoxy, with copper foil  401   a  and  401   b  bonded through an adhesive to the respective sides of the insulation layer. 
     Then, as shown in  FIG. 4B , a dry film  403   a  which is open at a portion corresponding to the unit region of the base substrate CCL is deposited on the copper foil  401   a  of the wire bonding pad side. While the dry film  403   a  serves as a mask, the unit region, exposed through the open portion of the dry film  403   a , is half etched so that the copper foil  401   a  has different thicknesses at the unit region and at the dummy region. 
     Because there is no need to half etch the copper foil  401   b  on the solder ball pad side, a blanket of the dry film  403   b  is deposited over the copper foil  401   b  on the ball pad side. Alternatively, in the case where the copper foil  401   a  in the unit region has the same thickness as that of the copper foil  401   b  in the dummy region, a half etching process can be conducted without use of the dry film  403   a , which is open at a portion corresponding to the unit region of the CCL. 
       FIG. 4C  is a cross sectional view after a half etching process is conducted to remove the copper foil  401   a  from the bonding pad side to a predetermined depth in the unit region while the copper foil  401   b  on the ball pad side is protected by the dry film  403   b.    
     Following the removal of the copper foil  401   a  on the bonding pad side in the unit region to a predetermined thickness by half etching, the dry films  403   a  and  403   b  respectively deposited on the copper foil  401   a  of the wire bonding pad side and the copper foil  401   b  of the ball pad side are removed, as shown in  FIG. 4D . 
     Since the copper foil  401   a  on the wire bonding side in the unit region becomes thin, there is possibility that a circuit pattern formed thereon might be cut. Particularly, when the plating lead line is cut, a plating process for a wire bonding pad may be not conducted. 
     For this reason, as shown in  FIG. 4E , a through hole  405  is drilled and plated to form a connection through hole  406  for connecting the copper foil  401   a  on the wire bonding pad side and the copper foil  401   b  on the ball pad side. The connection through hole  406  serves as an electric bridge between the lower foil  401   b  and the upper foil  401   a  so that the plating lead line (not shown) formed in the lower copper foil  401   b  is electrically connected with the plating lead line (not shown) formed in the upper copper foil  401   a . Even if the plating lead line of the upper copper foil  401   a  is cut, as will be described later, a gold plating process can be conducted to form a gold coat  408   b  on a wire bonding pad  408   a  ( FIG. 4G ) using the plating lead line of the lower copper foil  401   b , which is connected through the connection through hole  406  to the bonding pad  408 . 
     Preferably, the connection through hole  406  is formed at four corners  613  of the unit region  611 , as shown in  FIG. 6 . The reason is that a main plating lead line (not shown) usually passes through the four corners  613 . That is, when the main plating lead line is cut, the gold plating cannot assure the thickness of the plated gold coat  408   b . Thus, even if the main plating lead line of the upper copper foil  401   a  is cut, the presence of the connection through hole  406  at the four corners  613  allows an electric current to be provided through the main plating lead line of the lower copper foil  401   b , thus assuring the thickness of the gold coat.  FIG. 6  shows a semiconductor package substrate  610  in accordance with an embodiment of the present invention, which is divided into a unit region  611  comprising a semiconductor device mounting portion  611   a  and an outer circuit pattern  611   b , and a dummy region  612  around the unit region  611 . 
     Returning to  FIG. 4E , patterned dry films  404   a  and  404   b  for the formation of circuit patterns on the wire bonding pad side and the ball pad side are deposited over the copper foils  401   a  and  401   b , respectively. 
       FIG. 4F  is a cross sectional view after the copper foils  401   a  and  401   b  are selectively etched using an etchant, with the patterned dry films  404   a  and  404   b  serving as etching resists, followed by removing the dry films  404   a  and  404   b  with a peeling solution. Upon the pattern etching, a plating lead line to be used for gold plating is concurrently formed in the same manner. 
     Afterwards, the resulting CCL structure is coated with solder resists  407   a  and  407   b  which are then exposed to light, developed, and dried, as shown in  FIG. 4G . 
     In order to plate only the wire bonding pad  408   a  with gold, a dry film (not shown) is applied on the solder pad side of the substrate, exposed to light, and developed. Using a plating lead line, the bonding pad  406  is plated with gold  408   b  with the dry film serving as a plating resist. In detail, electrolytic Au plating is usually conducted for metal finishing the package substrate on which semiconductor devices are to be mounted. The reason is that electrolytic Au plating is superior to electroless Au plating in view of reliability. As mentioned above, it may occur that the plating lead line formed in the upper copper foil is cut. At this time, the gold coat  408  can be formed to a preferred thickness with electric power supplied through the connection through hole  406  from the plating lead line of the lower copper foil  401   b.    
     Following the electrolytic Au plating, the dry film used as the plating resist is removed with a peeling solution and the plating lead line is cut using a router or a dicing process. 
     Then, the solder ball pad  409   a  is coated with OSP to form an OSP-treated surface  409   b.    
     With reference to  FIGS. 5A to 5H , a method for fabricating a semiconductor package substrate in which a circuit layer on a wire bonding side is different in thickness from that on a ball pad side are shown in a stepwise manner in accordance with another embodiment of the present invention. 
       FIG. 5A  is a cross sectional view of a CCL  500  comprising an insulation layer  502 , made from, for example, epoxy, with copper foil  501   a  and  501   b  bonded using an adhesive to respective opposite sides of the insulation layer. 
     Then, as shown in  FIG. 5B , a dry film  503  is deposited on the copper foil  501   b  of the ball pad side in order to be used as a mask in half etching the copper foil  501   a  of the wire bonding pad side. 
       FIG. 5C  is a cross sectional view after the entire copper foil  501   a  of the wire bonding pad side is half etched to a predetermined thickness, with the dry film  503  protecting the copper foil  501   b  of the solder ball pad side, followed by removing the dry film  503  from the copper foil  501   b  of the solder ball pad side. 
     There is a need for reinforcing the copper foil  501   a  in the dummy region of the wire bonding pad side in order to prevent the CCL from curling. For this, as shown in  FIG. 5D , the copper foil  501   a  of the wire bonding pad side is coated with a dry film  504   a  which is open at a portion corresponding to the dummy region of the wire bonding pad side while a blanket of a dry film  504   b  is deposited as a mask over the ball pad side. 
     Afterwards, the exposed copper foil  501   a  is plated with copper  505  to increase the thickness of the copper foil in the dummy region of the wire bonding pad side, thereby preventing the CCL from curling, as shown in  FIG. 5E . Following the formation of the copper coat  505 , the dry films  504   a  and  504   b  respectively deposited over the copper foil  501   a  of the wire bonding pad side and the copper foil  501   b  of the ball pad side are removed. 
     Since the copper foil  501   a  on the wire bonding side in the unit region becomes thin, there is possibility that a circuit pattern formed thereon might be cut. Particularly, when the plating lead line is cut, a plating process for a wire bonding pad may not be conducted. 
     For this reason, as shown in  FIG. 5F , a through hole  506  is drilled and plated to form a connection through hole  507  for connecting the copper foil  501   a  on the wire bonding pad side and the copper foil  501   b  on the ball pad side. The connection through hole  507  serves as an electric bridge between the lower foil  501   b  and the upper foil  501   a  so that the plating lead line (not shown) formed in the lower copper foil  501   b  is electrically connected with the plating lead line (not shown) formed in the upper copper foil  501   a . Even if the plating lead line of the upper copper foil  501   a  is cut, as will be described later, a gold plating process can be conducted to form a gold coat  509   b  ( FIG. 5H ) on a wire bonding pad  509   a  ( FIG. 5H ) using the plating lead line of the lower copper foil  501   b , which is connected through the connection through hole  507  to the wire bonding pad  509   a.    
     Preferably, the connection through hole  507  is formed at four corners  613  of the unit region  611 , as shown in  FIG. 6 . The reason is that a main plating lead line (not shown) usually passes through the four corners  613 . That is, when the main plating lead line is cut, the gold plating cannot assure the thickness of the plated gold coat  509   b . Thus, even if the main plating lead line of the upper copper foil  501   a  is cut, the presence of the connection through hole  507  at the four corners  613  allows an electric current to be provided through the main plating lead line of the lower copper foil  501   b , thus assuring the thickness of the gold coat.  FIG. 6  shows a semiconductor package substrate  610  in accordance with an embodiment of the present invention, which is divided into a unit region  611  comprising a semiconductor device mounting portion  611   a  and an outer circuit pattern  611   b , and a dummy region  612  around the unit region  611 . 
     Returning to  FIG. 5F , patterned dry films  508   a  and  508   b  for the formation of circuit patterns on the wire bonding pad side and the ball pad side are deposited over the copper foils  501   a  and  501   b , respectively. 
       FIG. 5G  is a cross sectional view after the copper foils  501   a  and  501   b  are selectively etched using an etchant, with the patterned dry films  508   a  and  508   b  serving as etching resists, followed by removing the dry films  508   a  and  508   b  with a peeling solution. Upon this pattern etching, a plating lead line to be used for gold plating is concurrently formed in the same manner. 
     Afterwards, the resulting CCL structure is coated with solder resists  511   a  and  511   b  which are then exposed to light, developed, and dried, as shown in  FIG. 5H . 
     In order to plate only the wire bonding pad  509   a  with gold, a dry film (not shown) is applied on the solder pad side of the substrate, exposed to light and developed. Using a plating lead line, the wire bonding pad  509   a  is plated with gold  509   b , with the dry film serving as a plating resist. As mentioned above, it might occur that the plating lead line formed in the upper copper foil is cut. At this time, the gold coat  509   b  can be formed to a preferred thickness with electric power supplied through the connection through hole  507  from the plating lead line of the lower copper foil  501   b.    
     Following the electrolytic Au plating, the dry film used as the plating resist is removed with a peeling solution and the plating lead line is cut using a router or a dicing process. 
     Then, the solder ball pad  510   a  is coated with OSP to form an OSP-treated surface  510   b.    
     As described hereinbefore, the unit region of the wire bonding pad side can be formed to a small thickness in accordance with the present invention, thereby realizing fine patterns on the semiconductor package substrate according to the present invention. 
     In addition, the CCL of the present invention can be prevented from curling by maintaining the dummy region of the wire bonding pad side at a predetermined thickness. 
     Examples are described in terms of the preferred embodiment of present invention. However, it should be understood that such disclosure is not limited to the explicit description of the present invention. The description and the claims of the present invention are to be interpreted as covering all alterations and modifications within the true scope of this invention.