Abstract:
A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to magnetic random access memory (MRAM) devices, and more particularly, the present invention relates to MRAM devices having multi-laminated free magnetic layers, and to methods of fabricating MRAM devices having multi-laminated free magnetic layers.  
         [0003]     2. Description of the Related Art  
         [0004]     A magnetic random access memory (MRAM) device is a non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ). The MTJ is capable of selectively transitioning between two magnetic orientations. The differing resistance values of the two orientations are used to distinguish logic values of the memory cells.  
         [0005]      FIG. 1  is a simplified schematic view of an MTJ in each of a low resistance logic “0” magnetic state and a high resistance logic “1” magnetic state. In the figure, reference number  101  denotes a free magnetic layer made of a ferromagnetic material, reference number  102  denotes a tunneling barrier layer, reference number  103  denotes a pinned magnetic layer made of a ferromagnetic material, and reference number  104  denotes a pinning layer made of an anti-ferromagnetic material.  
         [0006]     As depicted by the arrows of  FIG. 1 , the magnetic orientation of the ferromagnetic pinned layer  103  is fixed. This condition may be achieved during manufacture by contacting the anti-ferromagnetic pinning layer  104  with the pinned layer  103  and conducting a heat treatment (at about 200° C. to 300° C.). By application of the magnetic field of the pinning layer  104  during heat treatment, the magnetic spins of the pinned layer  103  become fixed and do not rotate upon later exposure to an external magnetic field. As such, as shown in  FIG. 1 , the magnetic moment of the pinned layer  103  is fixed in one direction (to the right in  FIG. 1 ). In contrast, with the tunnel barrier layer  102  sandwiched between the pinned magnetic layer  103  and the free magnetic layer  101 , the magnetic orientation of the free magnetic layer  101  remains unfixed. As such, the magnetic spins of the free magnetic layer  103  are free to rotate upon later exposure to an external magnetic field. In the MTJ of an MRAM, the free magnetic layer  103  may be stably oriented in one of two directions, i.e., one with its moment parallel to that of the pinned magnetic layer  103 , and the other with its moment opposite that of the pinned magnetic layer  103 .  
         [0007]     As shown in  FIG. 1 , when the moments of the pinned layer  103  and the free magnetic layer  101  are parallel to one another, the MTJ exhibits a low resistance which may be designated a logic “0” state. In contrast, when the moments extend in opposite directions, the MTJ has a high resistance which may be designated a logic “1” state.  
         [0008]      FIG. 2  is a more detailed view of the conventional MTJ. In this cross-sectional view, reference number  1  denotes the pinning layer, reference number  8  denotes the pinned magnetic layer, reference number  9  denotes the tunneling barrier layer, and reference number  14  denotes the free magnetic layer.  
         [0009]     As mentioned above, the pinning layer  1  is formed of an anti-ferromagnetic material. Examples include PtMn, IrMn and FeMn.  
         [0010]     The pinned magnetic layer  8  is constituted by three layers, i.e., a lower ferromagnetic layer  3 , a metal layer  5 , and an upper ferromagnetic layer  7 . An example of the upper and lower ferromagnetic layers  3  and  7  is CoFe, and an example of the metal layer  5  is Ru.  
         [0011]     The tunneling barrier layer  9  is an insulator, and an example thereof is Al 2 O 3 .  
         [0012]     The free magnetic layer  14  is a two layer structure consisting of a thin lower ferromagnetic layer  11  and a thick upper ferromagnetic layer  13 . An example of the thin lower ferromagnetic layer  11  is CoFe, and an example of the thick upper ferromagnetic layer is NiFe.  
         [0013]     FIGS.  3 (A) and  3 (B) illustrate a conventional MRAM memory cell, where  FIG. 3 (B) is a cross-sectional view taken along line I-I′ of  FIG. 3 (A).  
         [0014]     Referring first to  FIG. 3 (B), the memory cell includes an MTJ  36 , such as that shown in  FIG. 2 , sandwiched between upper and lower electrodes  37  and  27 . The MTJ  36  includes a pinning layer  29  contacting the lower electrode  27 , a pinned magnetic layer  31 , a tunneling barrier layer  33 , and a free magnetic layer  35  contacting the upper electrode  37 . The MTJ  36 , the upper electrode  37  and the lower electrode  27  together define a programmable magneto-resistive element MR.  
         [0015]     The upper electrode  37  contacts a bit line BL extending orthogonally relative to the magnetic orientations of the MTJ  36 . In this example, the bit line BL extends into and out of the plane of  FIG. 3 (B).  
         [0016]     A digit line DL is spaced from the bottom of the bottom electrode  27  with an inter-layer dielectric  25  interposed there between. The digit line DL extends parallel to the magnetic orientations of the MTJ  36 , and in this example, the digit line DL extends left to right in the diagram of  FIG. 3 (B).  
         [0017]     The digit line DL may be formed over an inter-layer dielectric  23 , which in turn may be formed over a substrate  21 .  
         [0018]      FIG. 3 (A) is a top view showing the configuration of the bit line BL and the digit line DL, as well as an outline of the periphery of the magneto-resistive element MR. As shown, the top profile of the magneto-resistive element MR is substantially rectangular, with a length L exceeding a width W. The bit line BL carries a bit line current IBL, and extends length-wise along the width W of the magneto-resistive element MR. Further, the bit line BL is wide enough to substantially overlap the length L of the magneto-resistive element MR. The digit line DL extends orthogonally to the bit line BL, along the length L of the magneto-resistive element MR. Further, the digit line DL is wide enough to substantially overlap the width W of the magneto-resistive element MR.  
         [0019]     As shown in  FIG. 3 (A), a hard magnetic axis Hhard extends in the direction of the shorter width W, and an easy magnetic axis Heasy extends in the direction of the longer length L.  
         [0020]      FIG. 4  illustrates a conventional MRAM array which includes a plurality of intersecting bit lines BL 1 , BL 2 , . . . , BLn, and digit lines DL 1 , DL 2 , . . . , DLn. Write current ID is applied to each digit line, and write current IB is applied to each bit line. Magneto-resistive elements MR 12 , MR 22 , . . . , MRn 2  are located along the bit lines at the intersections with the digit lines.  
         [0021]      FIG. 5 (A) is a cross-sectional schematic view of an MRAM cell including a transistor for reading a logic state of the cell, and  FIG. 5 (B) is a circuit representation of the same. A magneto-resistive element MR 1  is configured like that shown in  FIG. 3 (B) and includes an upper electrode  77 , a lower electrode  57 , and an MTJ  75  sandwiched between the upper electrode  77  and the lower electrode  55 . The MTJ  75  includes a pinning layer  57 , a pinned magnetic layer  64 , an insulating barrier layer  65 , and a free magnetic layer  73 .  
         [0022]     Reference numbers  53   a ,  53   b ,  53   c  and  111  denote interlayer dielectric layers (ILDs). A bit line BL is connected to the upper electrode  73  of the magneto-resistive element MR 1  and is located on a top surface of the ILD  111 . A digit line DL extends orthogonally to the bit line BL on an upper surface of the ILD  53   b  and below the magneto-resistive element MR 1 .  
         [0023]     A transistor TA is defined by a word line (gate) WL, a source S and a drain D. The source S and drain D are formed in a substrate  51 . The source S is connected to a source pad  103 S via a contact plug  101 s. The drain D is connected to the lower electrode  55  via upper and lower drain pads  107 ,  103   d , and contact plugs  109 ,  105  and  101   d.    
         [0024]     A read operation is executed when a signal on the word line WL is sufficient to render the transistor TA in a conductive state. Current then flows from the bit line BL through the magneto-resistive element MR 1 . When the magneto-resistive element MR 1  is programmed in a low resistance state (logic “0”), a relatively large amount of current will flow through the transistor TA. When the magneto-resistive element MR 1  is programmed in a high resistance state (logic “1”), a relatively small amount of current will flow through the transistor TA. Thus, the amount of current flow can be used to determine the programmed state of the magneto-resistive element.  
         [0025]     The sensing margin of the magneto-resistive element is defined by the difference or ratio between the high resistive state Rmax and low resistance state Rmin of the magneto-resistive element MR 1 . Unfortunately, however, magnetic imperfections in the free magnetic layer of the MTJ adversely impact the sensing margin.  
         [0026]      FIG. 6 (A) depicts a free magnetic layer  14  having an external magnetic field H applied thereto. Each of the encircled areas denotes a domain of the free magnetic layer  14 . Upon application of the external magnetic field H, the magnetized direction of each domain should be parallel to the magnetic field H. However, as can be seen in  FIG. 6 (A), some of the magnetized directions are not parallel to the field H, particularly at the domain boundary. This reduces the sensing margin. Accordingly, to overcome the non-parallel moments at the domain boundaries, it becomes necessary to strengthen the magnetic field H by increasing the currents applied to the bit line and digit line. The result is increased power consumption.  
         [0027]     As shown at the right side of  FIG. 6 (B), the free magnetic layer is ideally formed of uniformly arranged grains. However, has shown by the enlarged view at the left side of  FIG. 6 (B), thick ferromagnetic layers exhibit large and irregular grains. The result is many domain boundaries that degrade magnetization uniformity.  
         [0028]      FIG. 7  is a hysteresis loop for explaining the effects of magnetic imperfections in the MTJ. The solid lined portion is the hysteresis loop for an ideal MTJ, and the dashed line to the right shows a loop characteristic of a conventional MRAM.  
         [0029]     As shown, in the case of an ideal MTJ, when the magnetic flux Heasy is +H 1  (Oe), the magnetic moment of the free magnetic layer completely rotates in one direction and the MTJ resistance Rw (Ω) goes from Rmin to Rmax. On the other hand, when the magnetic flux Heasy becomes −H 1  (Oe), the magnetic moment rotates in the other direction and the MTJ resistance Rw goes from Rmax to Rmin. Also, so long as the magnetic flux Heasy is greater than −H 1  and less than +H 1 , there is no change in the MTJ resistance Rw.  
         [0030]     The conventional MRAM, however, does not operate ideally, and instead the MTJ resistance Rw only begins to increase at “k” when the magnetic flux becomes +H 1 . The rotation of the magnetic moment of the free magnetic layer is gradual, and accordingly, the MTJ resistance Rw gradually increases with an increase in the magnetic flux Heasy. In order to achieve Rmax, an increased magnetic flux of +H 1 ′ is needed, which means additional power must be consumed.  
         [0031]     Incidentally, as mentioned previously, the conventional free magnetic layer consists of a lower layer of CoFe, and an upper layer of NiFe. The CoFe layer is provided to increase the sensing margin, i.e., the difference between Rmax and Rmin in  FIG. 7 . On the other hand, the NiFe layer is intended to decrease the width Q of the hysteresis loop of  FIG. 7 , which would mean less power consumption.  
         [0032]      FIG. 8 (A) shows the switching characteristic of an ideal MTJ in relation to the application of the magnetic flux Heasy and the magnetic flux Hhard. A write is achieved when the magnetic flux Heasy is HME (Oe), or when the magnetic flux Hhard is HMH (Oe). In addition, the curved lines BDL in each quadrant denote the minimum combination of Heasy and Hhard to write the MTJ, i.e., to switch the direction of the moment of the free magnetic layer of the MTJ. Thus, a write region WR is located outside the curved lines BDL, and a read region RR is located within the curved lines BDL. The ideal MTJ can be reliable written at point P 1 , where a magnetic flux Heasy is 20 Oe and the magnetic flux Hhard is 20 Oe.  
         [0033]     For comparison with the ideal MTJ,  FIG. 8 (B) shows the switching characteristics of the conventional MTJ. As shown, the ideal write flux P 2  (Heasy=Hhard=20 Oe) will not in most instances switch the magnetic moment of the free magnetic layer of the conventional MTJ. Rather, a magnetic flux where both Hheasy and Hhard are about 40 Oe is needed to reliably write the MTJ.  
         [0034]     Further, as shown in  FIG. 8 (B), the conventional MTJ is characterized by a wide write variation  1 W. This can be modeled as two ideal MTJs as shown in  FIG. 9 , wherein an inner MTJ 1  corresponds to the inner boundary of the write variation  1 W, and the outer MTJ 2  corresponds to the outer boundary of the write variation  1 W. In order to reliably write the outer MTJ 2 , a write flux such as that shown at point P 3  is needed. However, such a write flux is well in excess of both HME′ and HMH′ of the inner transistor MTJ 1 . This can cause write errors with respect to the inner transistor MTJ 1 .  
         [0035]     In summary, magnetic imperfections in the conventional magnetic tunnel junction can result in both increased power consumption and operational faults.  
       SUMMARY OF THE INVENTION  
       [0036]     According to a first aspect of the present invention, a magnetic tunnel junction device is provided which includes a magnetically programmable free magnetic layer, where the free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.  
         [0037]     According to another aspect of the present invention, a magnetic tunnel junction device is provided which includes an anti-ferromagnetic pinning layer, a tunneling layer, a ferromagnetic pinned layer located between the anti-ferromagnetic pinning layer and the tunneling layer, and a free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.  
         [0038]     According to still another aspect of the present invention, a memory device is provided which includes a first conductive line extending lengthwise in a first direction and located over a substrate, and a second conductive line extending lengthwise in a second direction which traverses the first direction, the second conductive line overlapping the first conductive line to define an overlapping region there between. The memory device further includes a magnetic tunnel junction device located in the overlapping region between the first and second conductive lines. The magnetic tunnel junction device has a magnetically programmable free magnetic layer located between a first electrode and a second electrode, and the free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers. The memory device also includes a transistor including a gate electrode and first and second source/drain regions, wherein the first source/drain region is electrically connected to the first electrode of the magnetic tunnel junction device.  
         [0039]     According to another aspect of the present invention, a magnetic tunnel junction device is provided which includes a magnetically programmable free magnetic layer, where the free magnetic layer includes a lamination of at least three material layers. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0040]     The above and other aspects and features of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:  
         [0041]      FIG. 1  is a simplified schematic view of a magnetic tunnel junction (MTJ) in each of a low resistance logic “0” magnetic state and a high resistance logic “1” magnetic state;  
         [0042]      FIG. 2  is a more detailed view of the conventional MTJ;  
         [0043]     FIGS.  3 (A) and  3 (B) illustrate a conventional MRAM memory cell, where  FIG. 3 (B) is a cross-sectional view taken along line I-I′ of  FIG. 3 (A);  
         [0044]      FIG. 4  illustrates a conventional MRAM array;  
         [0045]      FIG. 5 (A) is a cross-sectional schematic view of an MRAM cell including a transistor for reading a logic state of the cell, and  FIG. 5 (B) is a circuit representation of the same;  
         [0046]     FIGS.  6 (A) and  6 (B) are schematic views of explaining the effects of domain boundaries in a magnetic free layer of an MTJ;  
         [0047]      FIG. 7  is a hysteresis loop illustrating characteristics of an ideal MTJ and a conventional MTJ;  
         [0048]      FIG. 8 (A) shows a switching characteristic of an ideal MTJ, and  FIG. 8 (B) shows a switching characteristic of a conventional MTJ;  
         [0049]      FIG. 9  shows a switching characteristic a conventional MTJ which has been modeled as two ideal MTJ&#39;s;  
         [0050]      FIG. 10 (A) is a schematic cross-sectional view of a conventional free magnetic layer of an MTJ;  
         [0051]      FIG. 10 (B) is a schematic cross-sectional view of a free magnetic layer according to an embodiment of the present invention;  
         [0052]      FIG. 11  is a schematic cross-sectional view of an MTJ according to an embodiment of the present invention;  
         [0053]     FIGS.  12  is a schematic cross-sectional view of an MRAM cell according to an embodiment of the present invention;  
         [0054]      FIG. 13  shows a comparison between hysteresis loop characteristics of a conventional MTJ and hysteresis loop characteristics of an MTJ according to an embodiment of the present invention;  
         [0055]     FIGS.  14 (A) and  14 (B) are graphs respectively showing the slopes the hysteresis loop characteristics of the conventional MTJ and the hysteresis loop characteristics of an MTJ according to an embodiment of the present invention; and  
         [0056]      FIG. 15  illustrates schematic cross-sectional views of magnetic free layers according to alternative embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0057]     The present invention will now be described in detail below with reference to several preferred but non-limiting embodiments.  
         [0058]     The present invention is at least partially characterized by a magnetic tunnel junction (MTJ) containing a multi-laminated free magnetic layer. Attention is directed to FIGS.  10 (A) and  10 (B) showing a comparison between the conventional free magnetic layer and the multi-laminated free magnetic layer of an embodiment of the present invention.  
         [0059]     As shown in  FIG. 10 (A), the conventional free magnetic layer consists of a layer of NiFe stacked on a layer of CoFe. These layers are relatively thick. For example, the CoFe layer is about 10 Å thick, and the NiFe layer is about 30 Å thick, resulting in a total free magnetic layer thickness of about 40 Å. As explained previously, these thick layers of the MTJ, particularly the NiFe layer, contain large and irregular grains which form many domain boundaries that degrade magnetization uniformity.  
         [0060]     In contrast, as shown in  FIG. 10 (B), the multi-laminated free magnetic layer of the illustrated embodiment contains multiple and alternating thin layers CoFe and NiFe. The bottommost layer of CoFe has a thickness of about 5 Å, and the remaining layers of CoFe have a thickness of about 1 Å. Each of the layers of NiFe have a thickness of about 5 Å. Here, the total thickness of 40 Å is the same as that of the conventional free magnetic layer. The laminate structure of the embodiment prevents grain growth during lower-power sputter deposition of the thin layers. The resultant small grain size minimizes the number of domains of each layer, or reduces each layer to a single domain. Since the number of domain boundaries is reduced, the magnetic characteristics of the free magnetic layer are improved as will be demonstrated later.  
         [0061]      FIG. 11  is a schematic cross-sectional view of a magnetic tunnel junction device containing a multi-laminated free magnetic layer according to an embodiment of the present invention. As shown, the device of this example includes a magneto-resistive element  51  located over an interlayer dielectric (ILD)  53  and a substrate  51 . The magneto-resistive element includes a magnetic tunnel junction  75  sandwiched between an upper electrode  77  and a lower electrode  55 .  
         [0062]     The magnetic tunnel junction  75  is a multi-layer structure including pinning layer  57  located over the lower electrode  55 , a pinned layer  64  located over the pinning layer  57 , an tunneling barrier layer  65  located over the pinned layer  64 , a free magnetic layer  73  located over the insulating layer  65  and below the upper electrode  77 .  
         [0063]     The pinning layer  57  is formed of an anti-ferromagnetic layer. Examples include PtMn, IrMn, and FeMn.  
         [0064]     The pinned magnetic layer  64  is constituted by three layers, i.e., a lower ferromagnetic layer  59 , a metal layer  61 , and an upper ferromagnetic layer  63 . An example of the upper and lower ferromagnetic layers  59  and  63  is CoFe, and an example of the metal layer  61  is Ru.  
         [0065]     The tunneling barrier layer  65  is an insulating layer, and an example thereof is Al 2 O 3 .  
         [0066]     The free magnetic layer  73  is configured in the same manner as described above in connection with  FIG. 10 (B). That is, referring to  FIG. 11 , the free magnetic layer  73  includes a lowermost layer  67   a  of CoFe having a thickness of about 5 Å. Stacked above the layer  67   a  are multiple layers  67  and  71  of NiFe and CoFe, respectively. Each NiFe layer  67  has a thickness of about 5 Å, and each CoFe layer has a thickness of about 1 Å. In this embodiment, a total thickness of the free magnetic layer is about 40 Å.  
         [0067]      FIG. 12  is a schematic cross-sectional view of an MRAM cell according to an embodiment of the present invention. The MRAM cell of this embodiment is structurally the same as that previously described in connection with  FIG. 5 (A), except that the MTJ  75  of  FIG. 5 (A) is replaced with the multi-laminated free magnetic layer  73 A of embodiments of the present invention. For example, the multi-laminated free magnetic layer may be the same as that shown in  FIG. 10 (B). All other elements of  FIG. 12  are the same as the like-numbered elements of  FIG. 5 (A), and a detailed description thereof is omitted here to avoid redundancy.  
         [0068]      FIG. 13  illustrates measurement results of the average hysteresis loop of a sample of conventional MTJ structures (sample size was 100 ea) and a sample of MTJ structures (sample size was 100 ea) of an embodiment of present invention. In both sample sets, the same pinning layer configuration (CoFe 30 Å, Ru 8 Å, CoFe 34 Å) and tunneling barrier layer configuration (Al 2 O 3  12 Å) were used. Also, the horizontal cross-section of each sample was the same (0.8 μm*0.4 μm).  
         [0069]     The free magnetic layer of the tested conventional MTJ structures was composed of a layer of CoFe (10 Å) and a layer of NiFe (30 Å), with a total thickness of 40 Å. See  FIG. 10 (A).  
         [0070]     The free magnetic layer of the tested MTJ of the present embodiment structures was a multi-laminated structure composed of a first layer of CoFe (5 Å), and then alternating layers of NiFe (5 Å) and CoFe(1 Å), with a total thickness of 40 Å. See  FIG. 10 (B).  
         [0071]     The measurements were conducted without a hard magnetic field. The solid line  103  shows the average test results for the MTJ of the present embodiment, and the dashed line  101  shows the test results for the conventional MTJ. The MTJ resistance is normalized to 1.0 in the  FIG. 13 .  
         [0072]     As is apparent from  FIG. 13 , the test results associated with the present embodiment exhibit better symmetry when compared to those of the conventional MTJ. Also, less magnetic flux, and therefore less power, is needed to achieve the maximum and minimum resistance values.  
         [0073]      FIG. 14 (A) shows the rate of change in resistance (dR/dH) relative to the change the magnetic flux Heasy of the conventional MTJ. The dark line  105   a  shows the case where there is no hard magnetic flux Hhard (i.e., Hhard=0 Oe). The gray line  107   a  shows the case where a hard magnetic flux of 30 Oe is present. As is apparent from  FIG. 14 (A), large overlap regions OR 1  exists in which the magnetic spins of the free magnetic layer are rotated by the magnetic flux Heasy in the absence of the magnetic flux Hhard. The result is the increased incidence of write errors.  
         [0074]      FIG. 14 (B) shows the rate of change in resistance (dR/dH) relative to the change the magnetic flux Heasy of the MTJ of the embodiment of the present invention. The dark line  105   b  shows the case where there is no hard magnetic flux Hhard (i.e., Hhard=0 Oe). The gray line  107   b  shows the case where a hard magnetic flux of 30 Oe is present. As is apparent from  FIG. 14 (B), only minimal overlap regions OR 2  exists in which the magnetic spins of the free magnetic layer are rotated by the magnetic flux Heasy in the absence of the magnetic flux Hhard. As such, in comparison to the conventional MTJ, the incidence of write errors is substantially reduced.  
         [0075]     In the drawings and specification, there have been disclosed typical preferred embodiments of this invention and, although specific examples are set forth, they are used in a generic and descriptive sense only and not for purposes of limitation. For example, in the previous embodiment, the first CoFe layer has a thickness of about 5 Å, the remaining CoFe layers have a thickness of about 1 Å, the NiFe layers have a thickness of about 5 Å, and the total thickness of the free magnetic layer is about 40 Å. The invention is not limited to these thicknesses, nor is the invention limited to these materials. Further, the invention is not limited to the number of layers depicted in the previous embodiment. However, to minimize domain boundaries, it is preferable (but not required) that each layer of the free magnetic layer lamination have a thickness which is less than  10 A. Also, attention is directed to  FIG. 15  which illustrates several alternative embodiments of free magnetic layers  1501  through  1504  of the invention.  
         [0076]     The free magnetic layer  1501  is composed of alternating ferromagnetic layers  1  and  2  as shown. As examples only, the ferromagnetic layer  1  is one of CoFe or NiFe, and the ferromagnetic layer  2  is the other of NiFe, with the ferromagnetic layer  1  being the lowermost layer.  
         [0077]     The free magnetic layer  1502  is composed of alternating ferromagnetic layers  1  and amorphous ferromagnetic layers  3  as shown. As examples only, the ferromagnetic layer  1  is one of CoFe or NiFe, and the amorphous ferromagnetic layer  3  is CoFeB, with the ferromagnetic layer  1  being the lowermost layer.  
         [0078]     The free layer  1503  is similar to the free magnetic layer  1502 , except that the amorphous ferromagnetic  3  is the lowermost layer.  
         [0079]     The free layer  1504  is composed of alternating ferromagnetic layers  1  and non-ferromagnetic layers  4  as shown. As examples only, the ferromagnetic layer  1  is one of CoFe or NiFe, and the non-ferromagnetic layer  4  is Ta, with the ferromagnetic layer  1  being the lowermost layer.  
         [0080]     The embodiments herein, including those of  FIG. 15 , are examples-only, and it should therefore be understood the scope of the present invention is to be construed by the appended claims, and not by the exemplary embodiments.