Abstract:
An efficient Chien search method in Reed-Solomon decoding is adapted to be implemented in a processor having a parallel processing instruction set. The method includes the following steps: (a) calculating an error evaluation value; (b) subjecting the error evaluation value to mapping processing so as to find an index adjusting value; (c) storing a symbol index into an error location memory corresponding to a location index; (d) updating the location index according to the index adjusting value; (e) updating the symbol index; and (f) repeating steps (a) to (e) a particular number of times. The method primarily aims to reduce program flow branching so as to enhance the computation efficiency of the Chien search process.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority of Taiwanese Application No. 096122733, filed on Jun. 23, 2007. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a Chien search method in Reed-Solomon decoding, more particularly to a Chien search method in Reed-Solomon decoding, which can reduce program flow branching so as to enhance efficiency, and to a machine-readable recording medium including a plurality of instructions for executing the method. 
         [0004]    2. Description of the Related Art 
         [0005]    In recent years, demand for reliable signal transmission with respect to products ranging from consumer electronic products to communications electronic products has increased considerably. Therefore, error detection and correction mechanisms are becoming more and more important. During the process of digital communication, to ensure the accuracy of source data to be transmitted, a transmitting end generally will append redundant data to the source data, so that the receiving end can perform error correction based on the redundant data. The Reed-Solomon code is a widely used correction code. Since the Reed-Solomon code has a good correction capability with respect to errors generated in transmission channels, it has become a very popular channel coding scheme, and is now a widely used error correction code in satellite communication systems, digital television systems, various digital audiovisual recording media, etc. 
         [0006]    Even though the Reed-Solomon code has excellent performance in error correction, the amount of computations required for decoding is huge. Consequently, hardware is often used for calculation and processing. If the Reed-Solomon code is executed in a processor in the form of program decoding, the decoding speed will inevitably become extremely slow due to the huge computation amount. Therefore, in some applications of communications devices with software-defined operations (such as software defined radio (SDR)), accelerating the program decoding speed of the Reed-Solomon code has become an important subject of research. 
         [0007]    Referring to  FIG. 1 , an existing Reed-Solomon decoding procedure can be divided into four stages, which are, as shown, a stage  11  of calculating syndromes, a stage  12  of calculating error location polynomials, a stage  13  of executing a Chien search, and a stage  14  of calculating error values. In this Reed-Solomon decoding procedure, about 40% of the computation amount is concentrated on the Chien search at stage  13 . If the processing time for executing the Chien search can be effectively reduced, the decoding speed of the Reed-Solomon code can be successfully accelerated. 
         [0008]    Referring to  FIG. 2 , a conventional Chien search method in Reed-Solomon decoding includes the following steps. In step  21 , a location index j and a symbol index i are initialized, i.e., j=0, and i=0. In step  22 , an error evaluation value Λ(α i ) is calculated. In step  23 , a decision is performed to determine if the error evaluation value Λ(α i ) is equal to 0. If yes, this indicates that an error occurs in a symbol at the i th  position, and step  24  is carried out to perform the necessary processing. Otherwise, the flow goes to the processing in step  26 . In steps  24  and  25 , the current symbol index i is first stored in an error location array, Location[j]=1, followed by incrementing the location index, j=j+1. In steps  26 - 28 , a decision is performed to determine if the Chien search has been completed, i.e., determining if i=n−1. If yes, the Chien search is ended. Otherwise, the symbol index i is incremented, i=i+1, and the aforesaid steps  22 - 26  are repeated. In steps  24 - 25 , n represents a total number of symbols of a Reed-Solomon block code that was received. 
         [0009]    The determination processing in step  23  of the aforesaid conventional method will generate program flow branching. That is, one operation (step  24 ) will be executed when Λ(α i )=0, and another operation (step  26 ) will be executed when Λ(α i )≠0. Branching will result in disordered execution of a processor, causing a reset of internal instructions and data of a pipeline of the processor, thereby affecting the overall efficiency of the processor adversely. 
         [0010]    Other conventional Chien search schemes in the Reed-Solomon code, such as those disclosed in U.S. Pat. No. 6,263,470 and U.S. Pat. No. 6,360,348, are primarily concerned with the acceleration of the computation of the Chien search process using look-up tables, and are silent on the problem of program flow branching associated with the Chien search process. 
         [0011]    Therefore, there is a need for a solution to reduce the program flow branching in the aforesaid conventional method, so that the processing time of the Chien search can be further reduced to thereby increase the decoding speed of the Reed-Solomon code. 
       SUMMARY OF THE INVENTION 
       [0012]    Therefore, an object of the present invention is to provide an efficient Chien search method in Reed-Solomon decoding, which is adapted to be implemented in a processor having a parallel processing instruction set. 
         [0013]    Accordingly, the efficient Chien search method in Reed-Solomon decoding of the present invention includes the following steps: (a) calculating an error evaluation value; (b) subjecting the error evaluation value to mapping processing so as to find an index adjusting value; (c) storing a symbol index into an error location memory corresponding to a location index; (d) updating the location index according to the index adjusting value; (e) updating the symbol index; and (f) repeating steps (a) to (e) a particular number of times. 
         [0014]    Another object of the present invention is to provide a machine-readable recording medium adapted for execution of the efficient Chien search method in Reed-Solomon decoding. 
         [0015]    Accordingly, the machine-readable recording medium of the present invention includes a plurality of instructions. The instructions are used to execute the following steps in a processor having a parallel processing instruction set: (a) calculating an error evaluation value; (b) subjecting the error evaluation value to mapping processing so as to find an index adjusting value; (c) storing a symbol index into an error location memory corresponding to a location index; (d) updating the location index according to the index adjusting value; (e) updating the symbol index; and (f) repeating steps (a) to (e) a particular number of times. 
         [0016]    The present invention allows for a further reduction in the processing time of the Chien search process by reducing program flow branching in the Chien search, thereby enhancing the decoding speed of the Reed-Solomon code. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment with reference to the accompanying drawings, of which: 
           [0018]      FIG. 1  is a flow diagram to illustrate a conventional Reed-Solomon decoding procedure; 
           [0019]      FIG. 2  is a flowchart to illustrate a conventional Chien search method in Reed-Solomon decoding; 
           [0020]      FIG. 3  is a flowchart to illustrate a preferred embodiment of an efficient Chien search method in Reed-Solomon decoding according to the present invention; and 
           [0021]      FIG. 4  is a schematic diagram to illustrate mapping processing in the preferred embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0022]    Referring back to  FIG. 1 , as mentioned hereinbefore, the Reed-Solomon decoding procedure includes stages  11 ,  12 ,  13 , and  14 . In stage  11 , the purpose of calculating syndromes is to determine if the received signal has been contaminated by noise. If the result of syndrome calculation is 0, this indicates that the signal has not been contaminated (i.e., the received signal is correct). Otherwise, processing in stages  12  to  14  must be continued. In stage  12 , a Berlekamp-Massey algorithm is used to calculate an error location polynomial. In stage  13 , a Chien search is conducted according to the error location polynomial to find at least one error evaluation value. The error evaluation value can be used to confirm the location of the error. In stage  14 , at least one error value is found, and the error value is subtracted at an appropriate error location so as to recover the correct signal. 
         [0023]    In general, a Reed-Solomon block code is represented by Reed-Solomon (n,k), where n represents the total number of symbols of each block after encoding, k represents the number of source message symbols of each encoded block, and t=(n−k)/2, t representing the maximum number of correctable errors. For example, a digital video broadcasting (DVB) system of the European specification adopts Reed-Solomon (204,188). That is, there are altogether 204 symbols in the Reed-Solomon block code, the number of encoded source message symbols is 188, and the maximum number of correctable errors is 8. 
         [0024]    Suppose the Reed-Solomon block code received is as expressed in the following Equation (1): 
         [0000]        r=r   0   +r   1   +r   2   + . . . +r   i   + . . . +r   a−1    (1) 
         [0000]    where i is a symbol index, and r i  represents the i th  symbol in the Reed-Solomon block code. 
         [0025]    Using the Berlekamp-Massey algorithm, the number of symbols in which errors occur, and an error location polynomial can be found. Supposing there are altogether d symbols in which errors occur, the error location polynomial thus calculated is as expressed in the following Equation (2): 
         [0000]      Λ(α i )=λ 0 +λ 1 α 1 +λ 2 α 2i +λ 3 α 3i + . . . +λ d α di    (2) 
         [0000]    where d≦t. 
         [0026]    For each symbol r i , a corresponding error evaluation value Λ(α i ) is calculated. The calculation is expressed in the following Equation (3): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Λ 
                            
                           
                             ( 
                             
                               α 
                               0 
                             
                             ) 
                           
                         
                         = 
                         
                           
                             λ 
                             0 
                           
                           + 
                           
                             
                               λ 
                               1 
                             
                              
                             
                               α 
                               0 
                             
                           
                           + 
                           
                             
                               λ 
                               2 
                             
                              
                             
                               α 
                               0 
                             
                           
                           + 
                           
                             
                               λ 
                               3 
                             
                              
                             
                               α 
                               0 
                             
                           
                           + 
                           ⋯ 
                           + 
                           
                             
                               λ 
                               d 
                             
                              
                             
                               α 
                               0 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         
                           Λ 
                            
                           
                             ( 
                             
                               α 
                               1 
                             
                             ) 
                           
                         
                         = 
                         
                           
                             λ 
                             0 
                           
                           + 
                           
                             
                               λ 
                               1 
                             
                              
                             
                               α 
                               1 
                             
                           
                           + 
                           
                             
                               λ 
                               2 
                             
                              
                             
                               α 
                               2 
                             
                           
                           + 
                           
                             
                               λ 
                               3 
                             
                              
                             
                               α 
                               3 
                             
                           
                           + 
                           ⋯ 
                           + 
                           
                             
                               λ 
                               d 
                             
                              
                             
                               α 
                               d 
                             
                           
                         
                       
                     
                   
                   
                     
                       ⋮ 
                     
                   
                   
                     
                       
                         
                           Λ 
                            
                           
                             ( 
                             
                               α 
                               
                                 n 
                                 - 
                                 1 
                               
                             
                             ) 
                           
                         
                         = 
                         
                           
                             λ 
                             0 
                           
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                               λ 
                               1 
                             
                              
                             
                               α 
                               
                                 n 
                                 - 
                                 1 
                               
                             
                           
                           + 
                           
                             
                               λ 
                               2 
                             
                              
                             
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                                   2 
                                    
                                   n 
                                 
                                 - 
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                               λ 
                               3 
                             
                              
                             
                               α 
                               
                                 
                                   3 
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                                   n 
                                 
                                 - 
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                           + 
                           ⋯ 
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                               λ 
                               d 
                             
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                               α 
                               
                                 d 
                                  
                                 
                                   ( 
                                   
                                     n 
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                                     1 
                                   
                                   ) 
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0027]    If the error evaluation value Λ(α i ) thus calculated is 0, this indicates that an error has occurred in the symbol r i . Otherwise, this indicates that the symbol r i  is correct. 
         [0028]    Since the principles of encoding and decoding in the Reed-Solomon code and the finite field operations are constructed on the Galois field GF(2 m ), where (2 m ) represents the total number of corresponding elements in the Galois field, the finite field operation for the error evaluation value Λ(α i ) in Equation (3) herein is a Galois field operation. 
         [0029]    The preferred embodiment of an efficient Chien search method in Reed-Solomon decoding of the present invention can be accomplished using a software program. Therefore, in the present invention, a plurality of instructions are written using a programming language and are stored in a machine-readable recording medium. When the instructions are loaded into a processor having a parallel processing instruction set, the processor can be used to execute the method of the present invention. 
         [0030]    In the preferred embodiment, the method is executed in an x86 processor having a SSE2 instruction set. However, the method can also be executed in a digital signal processor (DSP), a general purpose processor, or a central processing unit (CPU) having a similar parallel processing instruction set. Thus, implementation of the present invention should not be limited to the preferred embodiment illustrated herein. 
         [0031]    Referring to  FIG. 3 , an efficient Chien search method in Reed-Solomon decoding of the present invention includes the following steps. 
         [0032]    In step  31 , a location index j is initialized to 0, i.e., j=0, and the symbol index i is initialized to 0, i.e., i=0. 
         [0033]    In step  32 , according to Equation (3), the error evaluation value Λ(α i ) is found. In the preferred embodiment, p entries of error evaluation values Λ(α i )˜Λ(α i+(p−1) ) are calculated in a single operation using the parallel processing instruction set to perform a vector finite field operation. As techniques relating to vector finite field operations are not crucial features of the present invention, they will not be discussed herein for the sake of brevity. Furthermore, since the p entries of error evaluation values Λ(α′)˜Λ(α i+(p−1) ) can also be obtained through look-up tables disclosed in the prior art (such as U.S. Pat. No. 6,263,470 and U.S. Pat. No. 6.360,348 mentioned hereinabove), implementation of the present invention should not be limited to the preferred embodiment as illustrated herein. 
         [0034]    In step  33 , the error evaluation value Λ(α′) is subjected to mapping processing to obtain an index adjusting value e i . That is, if the error evaluation value Λ(α′) is 0, the index adjusting value e i  is 1, and is 0 if otherwise, as expressed in the following Equation (4): 
         [0000]      ∀Λ(α i )=0:  e   i =1 
         [0000]      ∀Λ(α i )≠0:  e   i =0   (4). 
         [0035]    In the preferred embodiment, p entries of error evaluation values Λ(α i )˜Λ(α i+(p−1) ) are mapped in a single operation using the parallel processing instruction set. Using the SSE2 parallel processing instruction set of the x86 processor as an example, the p(p=16) entries of error evaluation values Λ(α i )˜Λ(α i+(p−1) ) are each compared with 0 at the same time using a pcmpeqb instruction, where if a certain error evaluation value Λ(α i+x ) is 0, Λ′(α i+x ) is equal to 0xFFh (hexadecimal); otherwise, Λ′(α i+x ) is equal to 0. Thereafter, a pand instruction is used to perform an AND operation of each of the p entries of error evaluation values Λ′(α i )˜Λ′(α i ) and 0x01h. As shown in  FIG. 4 , as a result of the pcmpeqb and pand instructions, p entries of index adjusting values e i ˜e i+(p−1)  can be obtained. 
         [0036]    Referring to  FIG. 3 , in step  34 , the symbol index i is stored in an error location memory corresponding to the location index j. The error location memory is actually an array, and is assumed to be Location[1×d]. Thus, the processing in step  34  can be expressed as Location[j]=i. 
         [0037]    In step  35 , the index adjusting value e i  is added to the location index j, so as to update the location index j, i.e., j=j+e i . 
         [0038]    In step  36 , the symbol index i is upated, i.e., i=i+1. 
         [0039]    It should be noted that, in this preferred embodiment, the p entries of index adjusting values e i ˜e i+(p−1)  are subjected to the processing in steps  34  to  36  in sequence. In other words, after completing the processing in step  33 , the processing in steps  34  to  36  is performed in sequence p times. When e i =0, this indicates that the symbol index i will be put in the same memory location, and this is the so-called memory in place technique. 
         [0040]    In steps  37  to  38 , a decision is performed to determine if the Chien search has been completed. If yes, the flow is ended. Otherwise, steps  32  to  36  are repeated. The number of times steps  32  to  36  are repeated depends on the total number n of symbols in the Reed-Solomon block code. After all the symbols in the Reed-Solomon block code have been processed (when i=n−1), this indicates that the Chien search has been completed. Referring back to  FIG. 2 , by utilizing mapping processing of the error evaluation value Λ(α i ) and the memory in place technique, the present invention can help avoid program flow branching as a result of the processing in step  23  of the conventional method. 
         [0041]    In sum, since the method of the present invention can eliminate the program flow branching problem associated with the Chien search, reduce disordered execution of the processor, and enhance utilization efficiency of the pipeline of the processor, the processing time of the Chien search can be further reduced to successfully increase the decoding speed of the Reed-Solomon code. 
         [0042]    While the present invention has been described in connection with what is considered the most practical and preferred embodiment, it is understood that this invention is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.