Abstract:
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.

Description:
BACKGROUND 
       [0001]    Some semiconductor devices, such as a DRAM (Dynamic Random Access Memory), perform a refresh operation to restore charge in memory cells to maintain the stored state of logical data. In general, the refresh operation is performed on a periodic basis or on a command basis with regard to a single die of DRAM. When a plurality of dice are involved, operations are more complex, such that current consumption and stability become more difficult to control. 
       SUMMARY 
       [0002]    According to a first aspect of the invention, a apparatus includes an interface chip including an oscillator producing an original clock signal, a first memory chip including a first terminal configured to receive a first clock signal in response to the original clock signal, a second terminal supplied with a first control signal, and first memory cells that are subject to a data refresh operation in response to the first clock signal when the first control single is active, and a second memory chip including a third terminal configured to receive a second clock signal in response to the original clock signal, a fourth terminal supplied with a second control signal, and second memory cells that are subject to a data refresh operation in response to the second clock signal when the second control signal is active. 
         [0003]    According to a second aspect of the invention, a apparatus includes a chip stack structure including first and second memory chips stacked over each other, and an interface chip coupled to the chip stack structure. The first memory chip includes first and second terminals and a plurality of first memory cell. The second memory chip includes third, fourth and fifth terminals. The first and second memory chips are stacked over each other such that the second terminal of the first memory chip is electrically connected to the fifth terminal of the second memory chip. The interface chip includes sixth, seventh, and eighth terminals, and is coupled to the chip stack structure such that the sixth, seventh and eighth terminals of the interface chip are electrically connected to the third, fourth and fifth terminals of the second memory chips, the second terminal is coupled to a first command decoder circuit of the first memory chip, and the fourth terminal is coupled to a second command decoder circuit of the second memory chip. The first and second command decoder circuits work independently from each other. 
         [0004]    According to a third aspect of the invention, an apparatus includes an interface chip that includes an oscillator circuit to provide an oscillator signal, a first memory chip on which a first refresh operation is performed in response to a first refresh enable signal supplied at a first node and a first oscillator enable signal supplied at a second node, a second memory chip on which a second refresh operation is performed in response to a second refresh enable signal supplied at a third node and a second oscillator enable signal supplied at a fourth node. The first and third nodes are configured to receive from the interface chip the first and second refresh enable signals independently of each other. The second and fourth nodes are configured to receive, based on the oscillator signal, the first and second oscillator enable signals in different timings from each other so that the first and second refresh operations are performed in different timings from each other even when the first and third nodes receive the first and second refresh enable signals simultaneously. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  illustrates an example of a high bandwidth memory according to a first embodiment. 
           [0006]      FIG. 2  illustrates an example structure having a high bandwidth memory and a graphics processing unit according to the first embodiment. 
           [0007]      FIG. 3  illustrates an example of the circuitry of the interface die according to the first embodiment. 
           [0008]      FIG. 4  illustrates an example of a high bandwidth memory according to a second embodiment. 
           [0009]      FIG. 5  illustrates an example of self-refresh timing according to the second embodiment. 
           [0010]      FIG. 6  illustrates another example of self-refresh timing according to the second embodiment. 
           [0011]      FIG. 7  illustrates an example of a high bandwidth memory according to the first embodiment. 
           [0012]      FIG. 8  illustrates a third example of a high bandwidth memory according to a third embodiment. 
           [0013]      FIG. 9  illustrates an example of a self-refresh timing according to the first embodiment. 
           [0014]      FIG. 10  illustrates an example of a core die according to the first embodiment. 
           [0015]      FIG. 11  illustrates an example of self-refresh waveforms in a core die according to the first embodiment. 
           [0016]      FIG. 12  illustrates a fourth example of a high bandwidth memory according to a fourth embodiment. 
           [0017]      FIG. 13  illustrates a fifth example of a high bandwidth memory according to a fifth embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    The description that follows includes illustrative an apparatus including semiconductor devices (circuits, systems, and the like) and processes (e.g., timing, waveforms, and the like) that embody the disclosed subject matter. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide an understanding of various embodiments of the subject matter. 
         [0019]      FIG. 1  illustrates an example of a high bandwidth memory (HBM) according to a first embodiment. The HBM  100  may include an interface die  101 , a stack of core dice  102  over the interface die  101 , through-silicon-vias (TSVs)  103  to connect the core dice  102  with each other, and bump pads  104 , and the HBM  100  may include a high band width memory explained below for example by referring to  FIGS. 7, 8, 12, and 13 . 
         [0020]    In some embodiments, the bump pads  104  may include micro bumps  104 , and may receive signals from a host controller (not shown). The interface die  101  may buffer signals from the bumps  104  to the TSVs  103 . In some embodiments, the core dice  102  may include memory cells, while the interface die  101  may not include any memory cells. In some embodiments, the core dice  102  may include one or more command decoders (such as a command decoder  116  as shown in  FIG. 7 ). 
         [0021]    In some embodiments, the interface die  101  may be divided into some independent channels. These channels may be independent of one another. The HBM  100  may have a wide data interface that may perform an operation with a high-speed and low-power-consumption. A self-refresh operation may be performed in the HBM  100 . 
         [0022]      FIG. 2  illustrates an example structure  200  including a HBM  100  and a Graphics Processing Unit (GPU)  105  according to the first embodiment. In some embodiments, a re-driver  106  may be disposed between the HBM  100  and the GPU  105  to drive a signal. The structure  200  may be called as a semiconductor device, an apparatus, or a system, that is accessed via a connection portion by a controller (not shown) or a processor (not shown). The connecting portion may be a bump, a ball, or a solder ball.  FIG. 3  illustrates an example of the circuitry of the interface die  101  according to the first embodiment. In some embodiments, the circuitry of the interface die  101  may include a memory Built-In-Self-Test (BIST) circuit  107  to test the core die  102 , internal circuits  108  (as shown in  FIG. 4  for example), and an input buffer  109  to receive signals from a corresponding micro bumps  104  and to convey the signals to corresponding TSVs  103 . 
         [0023]      FIG. 4  illustrates a first example of a HBM  400  according to a second embodiment. As shown in  FIG. 4 , the HBM  400  may include an interface die  401 , and a stack of core dice  402  (such as core die  402 A and core die  402 B), which are connected to each other by TSVs  403 . 
         [0024]    In some embodiments, the interface die  401  may include bumps  404  (such as bump_A and bump_B), and internal circuits  408  (which may have receivers (Rx)  410 , transmitters (Tx)  411 , transceivers (Tx Rx)  412 , logic  413 , and buffers  414 ). 
         [0025]    In some embodiments, the core die  402 A may include memory cells located in a DRAM memory array  415 , a command decoder  416 , a self refresh oscillator  417 , and a data controller  418 . Similarly, the core die  402 B may include memory cells located in a DRAM memory array  415 , a command decoder  416 , a self refresh oscillator  417 , and a data controller  418 . The core die  402 A and the core die  402 B may operate on commands respectively, and may thus work independently from each other. 
         [0026]      FIG. 5  illustrates an example of self-refresh timing when both the core A and the core B as shown in  FIG. 4  are in a self-refresh state according to the second embodiment.  FIG. 6  illustrate another example of self-refresh timing when the core A as shown in  FIG. 4  is in a self-refresh state and the core B as shown in  FIG. 4  is not in a self-refresh state according to the second embodiment. In  FIG. 5  and  FIG. 6 , self_osc represents a Self Refresh Oscillator signal, ACT represents an Active Command (which can be provided by a GPU), WR represents a WRITE signal, and RD represents a READ signal. 
         [0027]    A DRAM die  102  A has a self refresh function and a DRAM die  102 B also has a refresh function. The refresh function may be known as a self refresh mode of a DRAM. In self-refresh mode, the DRAM may automatically refresh the memory cell data, and all banks in the DRAM may be activated to refresh the memory cell data of the banks. 
         [0028]    In the second embodiment, refresh operations of the two dice  102 A and  102 B are performed independently of each other, and thus those two refresh operation may sometimes occur simultaneously, which may be indicated as same timing in  FIG. 5 . Therefore, consumption current in the same timing of refresh operations of two dice  102 A and  102 B may become higher than consumption current in different timing of refresh operations. So to speak, peak current in the second embodiment HBM may sometimes become high in the same timing refresh operations. The DRAM dice of HMB may consume a large amount of power at the same time, and thus may induce power noise, possibly affecting the integrity of the self refresh function. 
         [0029]      FIG. 7  illustrates an example of a HBM  700  according to the first embodiment. The explanations above may be applicable and/or identical at least in part to the first embodiment, and thus for simplicity, some common explanations are omitted. For example, the configurations shown above may be referred here according to the first embodiment. 
         [0030]    As shown in  FIG. 7 , the HBM  700  may include an interface die  701 , and a stack of core dice  702  (includes at least two dice such as a core die  702 A and a core die  702 B), which are connected to each other by TSVs  703 . 
         [0031]    In some embodiments, the interface die  701  may include bumps  704  (such as a bump_A and a bump_B), and internal circuits  708 . The internal circuits  708  of the interface die  701  may include a self refresh oscillator  717 , receivers  710 , transmitters  711 , transceivers  712 , logic  713 , and buffers  714 . 
         [0032]    Here, in some embodiments, the self refresh oscillator  717  may be located in the interface die  701 , and may work in common with both the core die  702 A and the core die  702 B. In contrast, a self refresh oscillator  427  is not located in the interface die  401  and is located in each of dice  401 A and  402 B in  FIG. 4  Thus, in the second embodiment, refresh operation may work independently of each other. According to the first embodiment, the self refresh oscillator  717  is configured common to stack of die including dice  702 A and  702 B. 
         [0033]    In some embodiments, the self-refresh oscillator  717  may be activated according to a reset signal when the HBM  700  is not in a reset state for example. 
         [0034]    In some embodiments, the core die  702 A may include memory cells located in a DRAM memory array  715 , a command decoder  716 , a data controller  718 , and a delay adjust circuit  719 A. Similarly, the core die  702 B may include memory cells located in a DRAM memory array  715 , a command decoder  716 , a data controller  718 , and a delay adjust circuit  719 B. The core die  702 A and the core die  702 B may operate on commands respectively, and thus may work independently of each other. 
         [0035]    Here, according to the first embodiment, the delay adjust circuit  719 A of the core die  702 A and the delay adjust circuit  719 B of the core die  702 B are coupled in series to each other. In such an arrangement, a delay amount of the delay adjust circuit  719 A may be configured to be the same as a delay amount of the delay adjust circuit  719 B, and the delay adjust circuits  719 A and  719 B may be configured to be identical to each other. 
         [0036]    According to the first embodiment, the refresh timing of the channels may be different due to the delay adjust circuits  719  (such as the delay adjust circuit  719 A and the delay adjust circuit  719 B), and thus a peak current consumption of the associated semiconductor device may be reduced. 
         [0037]      FIG. 8  illustrates a third example of a HBM  800  according to a third embodiment. As shown in  FIG. 8 , the HBM  800  may include an interface die  801 , and a stack of core dice  802  (includes at least two dice such as a core die  802 A and a core die  802 B), which are connected to each other by TSVs  803 . The explanations above may be applicable and/or identical at least in part to the third embodiment, and thus for simplicity, some common explanations are omitted. For example, the configurations shown above may be referred here according to the third embodiment. 
         [0038]    In some embodiments, the interface die  801  may include bumps (such as a bump_A and a bump_B), and internal circuits  808 . The internal circuits of the interface die  801  may include a self refresh oscillator  817 , receivers  810 , transmitters  811 , transceivers  812 , logic  813 , and buffers  814 . 
         [0039]    In some embodiments, the core die  802 A may include memory cells located in a DRAM memory array  815 , a command decoder  816 , a data controller  818 , and a delay adjust circuit  819 A. Similarly, the core die  802 B may include memory cells located in a DRAM memory array  815 , a command decoder  816 , and a data controller  818 , and a delay adjust circuit  819 B. The core die  802 A and the core die  802 B may operate on commands respectively, and thus may work independently of each other. 
         [0040]    According to the second embodiment, the delay adjust circuit  819 A of the core die  802 A and the delay adjust circuit  819 B of the core die  802 B are coupled in parallel to each other. In such an arrangement, a delay amount of the delay adjust circuit  819 A may be different from a delay amount of the delay adjust circuit  819 B, and the delay adjust circuits  819 A and  819 B may be configured to be different from each other. 
         [0041]    According to the second embodiment, the refresh timing of the channels may be different due to the delay adjust circuits  819  (such as the delay adjust circuit  819 A and the delay adjust circuit  819 B), and thus a peak current consumption of the associated semiconductor device may be reduced. 
         [0042]      FIG. 9  illustrates an example of a-self refresh timing according to the first embodiment. The timing in  FIG. 9  may be also referred according to other embodiments. 
         [0043]    As shown in  FIG. 9 , two self refresh operations to the core die  102 A and the core die  102 B can be performed at different timing values due to the delay adjust circuits  119 A and  119 B for example. 
         [0044]    According to the embodiments, two self oscillator singles SELF_OSC_A and SELF_OSC_B are commonly generated from one self oscillator signal SELF_OSC_IF and those two self oscillator singles SELF_OSC_A and SELF_OSC_B are triggered and activated to be high in different timing. Thus, simultaneous self-refresh operations of dice in stack can be prevented, and peak current in a self-refresh operation of HMB can be mitigated and become lower than the second embodiment. 
         [0045]      FIG. 10  illustrates an example of a core die  102  according to the first embodiment. The configuration shown in  FIG. 10  may be also referred according to other embodiments. 
         [0046]    As shown in  FIG. 10 , the core die  102  (e.g., the core die  102 A as shown in  FIG. 8 ) may include a command decoder  116 , and a delay adjust circuit  119 . When any channel is in a self-refresh mode, a self oscillator signal may be driven to the core die  102 . The delay adjust circuit  119  in the core die  102  may change a self refresh timing in each channel of the core die  102 . 
         [0047]      FIG. 11  illustrates an example of refresh waveforms in a core die  102  according to the first embodiment. The waveform in  FIG. 11  may be also referred according to other embodiments. 
         [0048]    In  FIG. 11 , “self_en” represents a Self Refresh Entry signal, which may be provided by a GPU. “self_exit” represents a Self Refresh Exit signal, which may be provided by a GPU. “self_st” represents a Self Refresh State signal, which may go up from the “self_en” and go down from the “self_en”. “self_osc” represents a Self Refresh Oscillator signal. “ref_go” represents a Refresh Start signal. “soak” represents a signal that is generated from a rising edge of the “ref_go”. The “soak” signal may come from a memory array region, and may indicate that it is ok to finish the refresh operation. “ref_state” represents a Refresh Command (State) signal, which may go to a memory array region. The refresh operation may be started from a rising edge of the “ref_state”, and may be finished at a falling edge of the “ref_state”. 
         [0049]      FIG. 12  illustrates an example of a HBM  1200  according to a fourth embodiment. The explanations above may be applicable and/or identical at least in part to the fourth embodiment, and thus for simplicity, some common explanations are omitted. For example, the configurations shown above may be referred here according to the fourth embodiment. 
         [0050]    As shown in  FIG. 12 , the HBM  1200  may include an interface die  1201 , and a stack of core dice  1202  (such as a core die  1202 A and a core die  1202 B), which are connected to each other by TSVs  1203 . 
         [0051]    In some embodiments, the interface die  1201  may include bumps (such as a bump_A and a bump_B), and internal circuits  1208 . The internal circuits  1208  of the interface die  1201  may include a self refresh oscillator  1217 , a delay adjust circuit  1219 A, a delay adjust circuit  1219 B, receivers  1210 , transmitters  1211 , transceivers  1212 , logic  1213 , and buffers  1214 . The delay adjust circuit  1219 A may receive a “self_osc” signal from the self-refresh oscillator  1217  for example. 
         [0052]    Here, according to the fourth embodiment, a delay adjust circuit  1219 A and a delay adjust circuit  1219 B are located in the interface die  1201 . In contrast, a delay adjust circuit  1219 A and a delay adjust circuit  1219 B are not located in the interface die  1201 , and are located in core dice, respectively. 
         [0053]    According to the fourth embodiment, the delay adjust circuit  1219 A may be coupled to the core die  1202 A. The delay adjust circuit  1219 B may be coupled between the delay adjust circuit  1219 A and the core die  1202 B, and thus the delay adjust circuit  1219 B may be coupled in series with the delay adjust circuit  1219 A. In such an arrangement, the circuit layout area in each core die (such as the core die  1202 A and the core die  1202 B) may be reduced. 
         [0054]    In some embodiments, the core die  1202 A may include memory cells located in a DRAM memory array  1215 , a command decoder  1216 , and a data controller  1218 . Similarly, the core die  1202 B may include memory cells located in a DRAM memory array  1215 , a command decoder  1216 , and a data controller  1218 . The core die  1202 A and the core die  1202 B may operate on command respectively, and thus may work independently of each other. 
         [0055]      FIG. 13  illustrates a fifth example of a HBM  1300  according to a fifth embodiment. The explanations above may be applicable and/or identical at least in part to the fifth embodiment, and thus for simplicity, some common explanations are omitted. For example, the configurations shown above may be referred here according to the fifth embodiment. 
         [0056]    As shown in  FIG. 13 , the HBM  1300  may include an interface die  1301 , and a stack of core dice  1302  (such as a core die  1302 A and a core die  1302 B), which are connected to each other by TSVs  1303 . [ 58 ] In some embodiments, the interface die  1301  may include bumps (such as a bump_A and a bump_B), and internal circuits  1308 . The internal circuits  1308  of the interface die  1301  may include a self refresh oscillator  1317 , a delay adjust circuit  1319 A, a delay adjust circuit  1319 B, receivers  1310 , transmitters  1311 , transceivers  1312 , logic  1313 , and buffers  1314 . 
         [0057]    Here, according to the fourth embodiment, a delay adjust circuit  1319 A and a delay adjust circuit  1319 B are located in the interface die  1301 . In contrast, a delay adjust circuit  1319 A and a delay adjust circuit  1319 B are not located in the interface die  1301 , and are located in core dice, respectively. 
         [0058]    According to the fourth embodiment, the delay adjust circuit  1319 A and the delay adjust circuit  1319 B are coupled in parallel to each other, and may receive a “self_osc” signal from the self-refresh oscillator  1317  for example. The delay adjust circuit  1319 A is coupled between the self refresh oscillator  1317  and the core die  1302 A. The delay adjust circuit  1319 B is coupled between the self-refresh oscillator  1317  and the core die  1302 B. 
         [0059]    In some embodiments, the core die  1302 A may include memory cells located in a DRAM memory array  1315 , a command decoder  1316 , and a data controller  1318 . Similarly, the core die  1302 B may include memory cells located in a DRAM memory array  1315 , a command decoder  1316 , and a data controller  1318 . The core dice  1302 A and  1302 B may operate on command respectively, and thus may work independently of each other. 
         [0060]    In some embodiments, the delay adjust circuit  1319 A of the interface die  1301  may be coupled to the DRAM memory array  1315  of the core die  1302 A via elements (such as a transmitter  111  of the interface die  1301 , a TSV  1303 , a receiver  1310  of the core die  1302 A, and logic  1313  of the core die  1302 A in series). Similarly, the delay adjust circuit  1319 B of the interface die  1301  may be coupled to the DRAM memory array  1315  of the core die  1302 B via elements (such as a transmitter  1311  of the interface die  1301 , a TSV  1303 , a receiver  1310  of the core die  1302 A, and logic  1313  of the core die  1302 A in series). 
         [0061]    In such an arrangement, an apparatus may only have one or more self refresh oscillators in an interface die, and the power consumption of the apparatus can be reduced. 
         [0062]    The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.