Abstract:
According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor light-emitting device having a plurality of light-emitting regions formed by diffusion of an impurity of a second conductive type into a substrate of a first conductive type, and more particularly to a structure and fabrication method that enable the light-emitting regions to be arranged more densely than before.  
         [0003]     2. Description of the Related Art  
         [0004]     Known semiconductor light-emitting devices include arrays of light-emitting elements such as arrays of light-emitting diodes, generally referred to as LED arrays. LED arrays formed on semiconductor chips are used as light sources in, for example, electrophotographic printers.  
         [0005]      FIGS. 28A and 28B  show an LED array disclosed on page  60  of the book  LED Purinta no Sekkei  (Design of LED Printers), published by Torikeppusu.  FIG. 28A  shows the cross-sectional structure of the LED array;  FIG. 28B  is a plan view showing the chip pattern.  
         [0006]     The LED array shown in these drawings has a plurality of light-emitting regions  3 . The light-emitting regions  3  are formed by growing an epitaxial layer  2  of a first conductive type (an n-type GaAs 0.6 P 0.4  layer) on a gallium-arsenide (GaAs) substrate  1  of the first conductive type (n-type), then selectively diffusing an impurity of a second conductive type (p-type), such as zinc (Zn), into the epitaxial layer  2 . Each light-emitting region  3  has an individual aluminum (Al) electrode  4 , and the light-emitting regions  3  share a common gold-germanium-nickel (Au—Ge—Ni) electrode  5 . The individual electrodes  4  are formed on an insulating layer  6  deposited on the epitaxial layer  2 , and make electrical contact with the surfaces of the light-emitting regions  3 . The common electrode  5  is formed on the underside of the n-type GaAs substrate  1 .  
         [0007]     There is an increasing demand for electrophotographic printers capable of printing very clear images. Improved clarity is obtained by increasing the resolution of the printer. For an LED printer, this means increasing the resolution of the LED arrays used as light sources, by increasing the density of the layout of their light-emitting elements.  
         [0008]      FIG. 29  illustrates relationships between the size and density of the light-emitting elements in an LED array.  FIG. 30  shows the relationship between the width of the diffusion areas and the diffusion depth, indicating width in arbitrary units on the horizontal axis, and depth in arbitrary units on the vertical axis.  
         [0009]     In the arrays shown on the left in  FIG. 29 , the width (in the array direction) of a light-emitting region  3  is equal to the distance between two adjacent light-emitting regions  3 . The resolution of the array is equal to twice this value. Accordingly, to increase the resolution, it is necessary to decrease the size of the light-emitting regions  3 , which entails decreasing the size of the diffusion windows through which the light-emitting regions  3  are formed. As shown in  FIG. 30 , however, if the size of the light-emitting regions  3  is decreased beyond a certain point, the diffusion depth must also decrease. Because of inadequate diffusion depth, the light-emitting regions  3  then fail to emit the desired amount of light.  
         [0010]     Referring once more to  FIG. 29 , it can be seen that as the size of the light-emitting regions  3 ,  3   a ,  3   b  is decreased to increase the density of the array, eventually the light-emitting regions become too small to be formed with adequate depth. If the density is increased without changing the size of the light-emitting regions  3 , however, it soon becomes impossible to fabricate the array because adjacent light-emitting regions overlap.  
       SUMMARY OF THE INVENTION  
       [0011]     An object of the present invention is to provide a semiconductor device including a dense array of light-emitting elements having an adequate diffusion depth.  
         [0012]     According to the present invention, the individual light-emitting elements are separated by isolation trenches. The isolation trenches are preferably formed on only two sides of each light-emitting element. The trenches enable the light-emitting elements to be formed with a suitable size and adequate depth.  
         [0013]     The light-emitting elements may be formed by creating a single band-shaped diffusion region with adequate depth, then forming isolation trenches that divide the single diffusion region into multiple diffusion regions, each of which becomes a light-emitting element having a suitable size. In this case the isolation trenches must be deeper than the diffusion depth.  
         [0014]     Alternatively, individual diffusion regions may be formed, and then isolation trenches may be formed between them, preferably removing parts of the sides of the diffusion regions. In this case the isolation trenches may be either deeper or shallower than the diffusion depth.  
         [0015]     The isolation trenches reliably prevent overlap between adjacent light-emitting elements, regardless of their diffusion depth and associated lateral diffusion width. A high-density array can accordingly be formed while maintaining adequate junction depth. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     In the attached drawings:  
         [0017]      FIG. 1A  is a plan view of an LED array according to a first embodiment of the invention;  
         [0018]      FIG. 1B  is a sectional view through line A-A′ in  FIG. 1A ;  
         [0019]      FIGS. 2A  to  9 A are plan views illustrating steps in a fabrication process for the LED array in  FIGS. 1A and 1B ;  
         [0020]      FIGS. 2B  to  9 B are sectional views through line A-A′ in  FIGS. 2A  to  9 A, respectively;  
         [0021]      FIG. 10A  is a plan view of an LED array according to a second embodiment of the invention;  
         [0022]      FIG. 10B  is a sectional view through line A-A′ in  FIG. 10A ;  
         [0023]      FIGS. 11A  to  18 A are plan views illustrating steps in a fabrication process for the LED array in  FIGS. 10A and 10B ;  
         [0024]      FIGS. 11B  to  18 B are sectional views through line A-A′ in  FIGS. 11A  to  18 A, respectively;  
         [0025]      FIG. 19A  is a plan view of an LED array according to a third embodiment of the invention;  
         [0026]      FIG. 19B  is a sectional view through line A-A′ in  FIG. 19A ;  
         [0027]      FIGS. 20A  to  27 A are plan views illustrating steps in a fabrication process for the LED array in  FIGS. 19A and 19B ;  
         [0028]      FIGS. 20B  to  27 B are sectional views through line A-A′ in  FIGS. 20A  to  27 A, respectively;  
         [0029]      FIG. 28A  is a sectional view of a light-emitting element in a conventional LED array;  
         [0030]      FIG. 28B  is a plan view of a conventional LED array;  
         [0031]      FIG. 29  illustrates factors limiting the density of a conventional LED array; and  
         [0032]      FIG. 30  is a graph of diffusion depth plotted against diffusion region width. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0033]     Preferred embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. Although the illustrated embodiments are LED arrays, the invention is not limited to LED arrays.  
       First Embodiment  
       [0034]      FIG. 1A  is a plan view of a first embodiment of the invention.  FIG. 1B  is a sectional view through line A-A′.  
         [0035]     The LED array shown in these drawings has a semiconductor substrate  10  of a first conductive type (n-type) in which a plurality of light-emitting regions, more specifically light-emitting diodes (LEDs)  11 , are formed by diffusion of an impurity of a second conductive type (p-type). A pn junction is created at the interface between the diffusion region  12  of each light-emitting diode  11  and the semiconductor substrate  10 . Between each pair of mutually adjacent light-emitting diodes  11 , an isolation trench  17  is provided to separate their two diffusion regions  12 .  
         [0036]     Except where the light-emitting diodes  11  and isolation trenches  17  are formed, the semiconductor substrate  10  is covered by an insulating layer  13 . A plurality of p-electrodes  14  and p-electrode pads  15  are formed on the insulating layer  13 , each light-emitting diode  11  being electrically coupled by a p-electrode  14  to a p-electrode pad  15 . An n-electrode  16  is formed on the underside of the semiconductor substrate  10 . A light-emitting diode  11  emits light from its pn junction when a forward voltage is applied between its p-electrode pad  15  and the n-electrode  16 . The light emitted through the surface  11   a  of the light-emitting diode  11  may be used in electrophotographic printing.  
         [0037]     As shown in  FIG. 1B , the isolation trenches  17  are deeper than the diffusion regions  12  of the light-emitting diodes  11 . The dimensions of the light-emitting diodes  11 , that is, the area of the surface  11   a  and the depth of the diffusion region  12 , are selected to provide a desired amount of light emission. The depth of the isolation trenches  17  is selected to exceed the depth of the diffusion region  12 .  
         [0038]     A fabrication process for the first embodiment will now be described.  
         [0039]     Referring to  FIGS. 2A and 2B , a diffusion mask  41  having a plurality of diffusion window  11   b  is formed on the surface of the semiconductor substrate  10 . The diffusion mask  41  may be used as the insulating layer  13  in the finished device. Each diffusion window  11   b  corresponds to one light-emitting diode  11 , the diffusion window  11   b  being large enough to permit formation of the surface  11   a  of the light-emitting diode  11  shown in  FIGS. 1A and 1B . In particular, the width of the diffusion window  11   b  in-the array direction (the direction parallel to line A-A′) exceeds the width of the surface  11   a  in this direction. The diffusion mask  41  may be, for example, a silicon nitride (SiN) film five hundred to three thousand angstroms (500 Å to 3000 Å) thick formed by chemical vapor deposition (CVD). The diffusion windows  11   b  may be formed by photolithography and etching.  
         [0040]     Referring to  FIGS. 3A and 3B , a diffusion source  42  is deposited on the diffusion mask  41  and the diffusion windows  11   b . The diffusion source  42  may be, for example, an insulating film doped with zinc, such as a film of zinc oxide and silicon dioxide (ZnO—SiO 2 ), likewise 500 Å to 3000 Å thick. The diffusion source  42  may be formed by sputtering.  
         [0041]     Referring to  FIGS. 4A and 4B , an anneal cap  43  is formed on the diffusion source  42 . The anneal cap  43  may be, for example, an aluminum nitride (AlN) film 500 Å to 3000 Å thick, which can be formed by sputtering.  
         [0042]     Referring to  FIGS. 5A and 5B , the device is annealed in, for example, a nitrogen atmosphere for one hour, causing a p-type impurity (zinc) to diffuse through the diffusion windows  11   b  to a desired depth into the semiconductor substrate  10 , forming diffusion regions  12   b . Diffusion proceeds laterally as well as vertically, so the diffusion regions  12   b  have a rounded shape. The boundary between each diffusion region  12   b  and the semiconductor substrate  10  becomes a pn junction. The annealing conditions are selected to produce a desired pn junction depth, regardless of how closely lateral diffusion causes adjacent diffusion regions  12   b  to approach each other. The diffusion depth or pn junction depth may be, for example, substantially one micrometer (1.0 μm).  
         [0043]     Referring to  FIGS. 6A and 6B , the diffusion source  42  and anneal cap  43  are now removed, exposing the diffusion mask  41  and the surfaces of the diffusion regions  12   b . The diffusion source  42  and anneal cap  43  may be removed by etching.  
         [0044]     Referring to  FIGS. 7A and 7B , the isolation trenches  17  are now formed by, for example, photolithography and etching. Formation of the isolation trenches  17  removes side material from the diffusion regions, reducing their width so that the surfaces  11   a  of the remaining diffusion regions  12  have the desired size.  
         [0045]     Referring to  FIGS. 8A and 8B , the p-electrodes  14  and p-electrode pads  15  are formed by, for example, evaporation deposition of a film of aluminum, followed by photolithography, etching, and sintering.  
         [0046]     Referring to  FIGS. 9A and 9B , the n-electrode  16  is formed on the underside of the semiconductor substrate  10 . The n-electrode  16  may comprise, for example, a gold alloy, and may be formed by evaporation deposition.  
         [0047]     The process described above makes it possible to form light-emitting diodes  11  with a very small surface  11   a , and to place these light-emitting diodes  11  very close together, while maintaining electrical isolation between adjacent light-emitting diodes  11  and while providing an adequate pn junction depth.  
         [0048]     Although it would be possible to surround each light-emitting diode  11  with isolation trenches on all four sides, there are advantages in forming the isolation trenches  17  on only two sides of each light-emitting diode  11 .  
         [0049]     One advantage is that more of the pn junction is left intact. The pn junction is present in the area directly below the surface  11   a , and also on the two sides of the diffusion region  12  extending parallel to the array axis, since no isolation trenches  17  are formed on these two sides. Considerable light is emitted from these two side regions, where the pn junction extends toward the surface of the device. If isolation trenches were to be formed on all four sides of the light-emitting diode  11 , the pn junction would be removed from all four sides, and less total light would be omitted.  
         [0050]     Another advantage is that if isolation trenches were to be formed on all four sides, the p-electrode  14  would have to cross an isolation trench to reach the surface  11   a  of the light-emitting diode  11 . Such a crossing would increase the likelihood of electrical discontinuities in the p-electrode  14 . In the first embodiment, the p-electrode  14  proceeds from the surface of the insulating layer  13  directly onto the surface  11   a  of the light-emitting diode  11  without having to cross an isolation trench  17 .  
         [0051]     Another advantage is that the dimensions in the vertical direction in  FIG. 1A  (orthogonal to the array direction) can easily be reduced to shrink the size of the LED array chip, since it is not necessary to reduce the width of any of the isolation trenches. If there were isolation trenches on all four sides of the light-emitting diodes  11 , it would be necessary to reduce the width of isolation trenches crossed by p-electrodes, further increasing the likelihood of an electrical discontinuity.  
         [0052]     Incidentally, it is also possible to reduce the horizontal dimensions of the array in  FIG. 1A , by reducing the width of the diffusion regions  12  without reducing the width of the trenches  17 , thus avoiding the difficulty of forming extremely narrow trenches. Reducing the width of the diffusion regions does not cause any structural problems.  
         [0053]     Next, a second embodiment will be described. The second embodiment is also an LED array.  
         [0054]     Referring to  FIG. 10A , the second embodiment has the same plan-view layout as the first embodiment, with the surfaces  21   a  of the light-emitting diodes separated by isolation trenches  27 .  
         [0055]     Referring to  FIG. 10B , the light-emitting diodes  21  in the second embodiment differ from the light-emitting diodes in the first embodiment in that the pn junction at the bottom of each light-emitting diode  21  extends straight across from the isolation trench  27  on one side to the isolation trench  27  on the other side, without having the rounded cross-sectional shape seen in the first embodiment.  
         [0056]     A fabrication process for the second embodiment will now be described.  
         [0057]     Referring to  FIGS. 11A and 11B , a diffusion mask  41 b is formed on the surface of the semiconductor substrate  10 . The diffusion mask  41   b  may be used as the insulating layer  13  in the finished device. The diffusion mask  41   b  has a single diffusion window  21   b  extending from one end of the device to the other. The diffusion mask  41   b  may be, for example, a silicon nitride film 500 Å to 3000 Å thick formed by chemical vapor deposition. The diffusion window  21   b  may be formed by photolithography and etching.  
         [0058]     Referring to  FIGS. 12A and 12B , a diffusion source  42  is deposited on the diffusion mask  41  and the diffusion window  21   b . The diffusion source  42  may be, for example, a sputtered ZnO—SiO 2  film 500 Å to 3000 Å thick.  
         [0059]     Referring to  FIGS. 13A and 13B , an anneal cap  43  is formed on the diffusion source  42 . The anneal cap  43  may be, for example, a sputtered aluminum nitride film 500 Å to 3000 Å thick.  
         [0060]     Referring to  FIGS. 14A and 14B , the device is annealed in, for example, a nitrogen atmosphere for one hour, causing a p-type impurity (e.g., zinc) to diffuse through the diffusion window  21   b  to a desired depth in the semiconductor substrate  10 , such as a depth of substantially 1.0 μm,, forming a diffusion region  22   b.    
         [0061]     Referring to  FIGS. 15A and 15B , the diffusion source  42  and anneal cap  43  are now removed, exposing the diffusion mask  41   b  and the surface of the diffusion region  22   b . The diffusion source  42  and anneal cap  43  may be removed by etching.  
         [0062]     Referring to  FIGS. 16A and 16B , the isolation trenches  27  are formed by, for example, photolithography and etching. Formation of the isolation trenches  27  removes part of the material of the diffusion region, which becomes divided into a plurality of mutually isolated diffusion regions  22 , creating an array of light-emitting diodes having surfaces  21   a  of the desired size.  
         [0063]     Referring to  FIGS. 17A and 17B , the p-electrodes  14  and p-electrode pads  15  are formed as in the first embodiment.  
         [0064]     Referring to  FIGS. 18A and 18B , the n-electrode  16  is formed as in the first embodiment.  
         [0065]     Compared with the first embodiment, the second embodiment provides each light-emitting diode  21  with a larger pn junction area at the full junction depth, thereby permitting the surfaces  21   a  of the light-emitting diodes  21  to be smaller than in the first embodiment. The formation of all the light-emitting diodes  21  from a single diffusion region  22   b  also leads to more uniform light-emitting characteristics.  
         [0066]     Next, a third embodiment will be described. The third embodiment is likewise an LED array.  
         [0067]     Referring to  FIG. 19A , the third embodiment has the same plan-view layout as the first embodiment, with the surfaces  31   a  of the light-emitting diodes separated by isolation trenches  37 .  
         [0068]     Referring to  FIG. 19B , the light-emitting diodes  31  in the third embodiment have substantially the same rounded cross-sectional shape as in the first embodiment, but the isolation trenches  37  in the third are not as deep as the diffusion regions  32  of the light-emitting diodes  31 .  
         [0069]     A fabrication process for the third embodiment will now be described.  
         [0070]     Referring to  FIGS. 20A and 20B , a diffusion mask  41  is formed on the surface of the semiconductor substrate  10 . The diffusion mask  41  may be used as the insulating layer  13  in the finished device. As in the first embodiment, the diffusion mask  41  has individual diffusion windows  31   b  defining the locations at which light-emitting diodes will be formed. The diffusion mask  41  may be, for example, a silicon nitride film 500 Å to 3000 Å thick formed by chemical vapor deposition. The diffusion windows  31   b  may be formed by photolithography and etching.  
         [0071]     Referring to  FIGS. 21A and 21B , a diffusion source  42  is deposited on the diffusion mask  41  and the diffusion windows  31   b . The diffusion source  42  may be, for example, a sputtered ZnO—SiO 2  film 500 Å to 3000 Å thick.  
         [0072]     Referring to  FIGS. 22A and 22B , an anneal cap  43  is formed on the diffusion source  42 . The anneal cap  43  may be, for example, a sputtered aluminum nitride film 500 Å to 3000 Å thick.  
         [0073]     Referring to  FIGS. 23A and 23B , the device is annealed in, for example, a nitrogen atmosphere for one hour, causing a p-type impurity (e.g., zinc) to diffuse through the diffusion windows  31   b  to a desired depth (e.g., 1.0 μm) in the semiconductor substrate  10 , forming diffusion regions  32   b.    
         [0074]     Referring to  FIGS. 24A and 24B , the diffusion source  42  and anneal cap  43  are now removed, exposing the diffusion mask  41  and the surfaces of the diffusion regions  32   b . The diffusion source  42  and anneal cap  43  may be removed by etching.  
         [0075]     Referring to  FIGS. 25A and 25B , the isolation trenches  37  are formed by, for example, photolithography and etching. Formation of the isolation trenches  27  removes part of the material from the upper sides of the diffusion regions  32   b , reducing the surfaces  31   a  of the light-emitting diodes to a desired size, but the etching process is stopped before the lower parts of the diffusion regions  32   b  are reached. The remaining diffusion regions  32  thus have rounded bottoms.  
         [0076]     Referring to  FIGS. 26A and 26B , the p-electrodes  14  and p-electrode pads  15  are formed as in the first embodiment.  
         [0077]     Referring to  FIGS. 27A and 27B , the n-electrode  16  is formed as in the first embodiment.  
         [0078]     The relative shallowness of the isolation trenches  37  in the third embodiment makes the etching process illustrated in  FIGS. 25A and 25B  easier to control than in the first embodiment. Consequently, if the surfaces  31   a  of the light-emitting diodes  31  in the third embodiment are equal in width to the surfaces  11   a  of the light-emitting diodes  11  in the first embodiment, the light-emitting diodes  31  can be placed closer together in the third embodiment than in the first embodiment.  
         [0079]     The present invention is not limited to the embodiments described above; those skilled in the art will recognize that various modifications are possible. The scope of the invention should accordingly be determined from the appended claims.