Abstract:
A method and apparatus of communicating data packets across the midplane of an electronic system in which the packets are partitioned into segments of a predetermined size and then serialized to a predetermined width. The serialized packets are transmitted, in phase staggered segments, across the midplane on a respective channel, received into receiving end and the serialized segments that have traversed the midplane, are deserialized and reassembled into the original data packet.

Description:
BACKGROUND AND BRIEF DESCRIPTION OF THE INVENTION  
         [0001]    This invention relates to a bus capable of transferring variable length packets (e.g. for POS) at a 10 Gbps rate between two separate cards across a midplane or backplane.  
           [0002]    The midplane or backplane (midplane/backplane) has a limited number of physical pins available and signals must pass through two connectors, which potentially could introduce signal integrity issues for high-speed signals.  
           [0003]    There is a width vs. speed tradeoff, wherein a slower bus rate is easier and more reliable to implement however it must also be wider, which can be inefficient for short packets.  
           [0004]    SQULB (prior art) is a sequenced utopia-3 like bus designed for asynchronous transfer mode (ATM) applications, i.e. fixed sized (56-byte) cells, and as such is not capable of handling variable length packets.  
           [0005]    In order to modify SQULB to handle variable length packets, the bus must be made four times wider (four-bytes to sixteen-bytes). This solution is not feasible for the following reasons:  
           [0006]    1. The limited number of pins available across the midplane/backplane. There is currently no offering of serializer/deserializer (SERDES) devices capable of handling this bus width. Separate SERDES devices would make it difficult to receive the packet data in the proper order and with minimal signal skew.  
           [0007]    2. A sixteen-byte wide bus implies that a single packet could contain up to fifteen empty bytes transferred during the end of packet. This transmission model would be very inefficient and would require a large increase in the operating frequency of the physical bus to maintain a 10 Gbps rate.  
         THE PRESENT INVENTION  
         [0008]    The present invention is directed to a method and apparatus for partitioning packets into segments of a predetermined size (e.g. 64 bytes), serializing the segments, and transmitting the segments over a plurality of channels (for example, four) that have a staggered phase relationship to one another, and wherein the phase difference between adjacent channels (actually, adjacent segments in the sequence of segments that form the packet) is more than the maximum latency that can occur in any one channel, thereby maintaining the ordering of the serialized packet segments, Preferably, there are 64-byte segments divided into four channels and staggering is 2 times maximum latency. While the invention is particularly applicable to variable length packets, the invention can also be used for fixed-length cells as well as variable length packets. 
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0009]    The above and other objects, advantages and features of the invention will become more apparent when considered with the following specification and accompanying drawings wherein:  
         [0010]    [0010]FIG. 1 is a block diagram illustrating the packets divided into 64-byte segments for transmitting over four channels are staggered in their phase relationship to one another,  
         [0011]    [0011]FIG. 2 is a timing chart showing a single channel bus timing of a given example, and  
         [0012]    [0012]FIG. 3 illustrates the staggering performed by the transmitting device. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    Referring to FIG. 1, packets from transmitter T are divided into 64-byte segments for transmission over four channels CHA, CHB, CHC and CHD that are staggered in their phase relationship to one another. A first array or set of SERDES (serializer/deserializer) devices TSA, TSB, TSC and TSD at the transmitter T in each channel is used to serialize the data and control for transmission across the midplane/backplane P and a second array or set of SERDES devices RSA, RSB, RSC and RSD are used at the receiver R in each channel to deserialize the data. These SERDES devices allow data and control to be passed across the midplane/backplane in a compressed manner and thus reduce the large variable amount of latency for a complete packet transfer. Furthermore, by staggering the phase relationship of the channels, the maximum latency that can occur in any one channel is accommodated and therefore the ordering of packet segments is maintained. For example, in the embodiment implemented in FIG. 1, the channels are staggered by 40 ns and the maximum latency per channel is 20 ns.  
         [0014]    The invention has two basic aspects: the topology of FIG. 1 and a bus protocol that runs on that topology to provide the required bandwidth of 10 Gbps for variable length packets.  
         [0015]    With reference to FIG. 2, the bus protocol will now be briefly described:  
         [0016]    Egress Data Path Signal Definitions  
         [0017]    The following describes a single channel and what is described is applicable for all four channels and can easily be extended to the complete bus.  
         [0018]    Each channel includes a plurality of core data path signals, a 32-bit wide data bus with eleven-bits of out-of-band control, and a number of non-core data path signals, which may be used to transfer additional information.  
         [0019]    Packets are broken apart into segments, 64-bytes of data, and transmitted 32-bits per cycle over 16 clock cycles. Packets that are greater than 64 bytes are required to be transmitted over more than one channel.  
         [0020]    When data is available for transmission, a Start of Segment (SOS) is raised for one clock cycle concurrent with the first word of the transfer.  
         [0021]    When a new packet is being transmitted, a Start of Packet (SOP) signal is raised for one clock cycle concurrent with the first word of the packet. Similarly, when the last word of a packet is being transmitted, an End of a Packet (EOP) signal is raised for one clock cycle concurrently with the last word. The Empty (MPTY) signals indicate how many bytes of the current word are valid. Since the bus is a word-wide (i.e. 32-bits will be transferred each clock cycle) up to three bytes of PAD may be present on a transfer. The MPTY signals are only valid when an EOP occurs. If the packet happens contain an error, then the Error (ERR) signal becomes active while EOP is active.  
         [0022]    During the complete data transfer, the Valid (VAL) signal is active. The parity across this interface should always be valid for both the data path (DPRTY) signal and the control path (CPRTY) signal.  
         [0023]    If there is no data to be transferred, idle cycles will occur on the bus. For an idle cycle, the data bus and all the control signals (except parity) will be driven low. The parity will remain valid at all times.  
         [0024]    Summarizing:  
         [0025]    1. Data packets are divided into 64-byte segments,  
         [0026]    2. This interface has parity protection for all data and control signals (DPRTY and CPRTY),  
         [0027]    3. Each segment is serialized to four bytes wide [Data(31:0)] and each segment is tagged with a set of out-of-band control signals, as shown in FIG. 2. The associated control signals consist of start and end of packet indications (SOP and EOP), error indication (ERR), and the number of empty bytes transmitted during the end of packet condition. This information is then used by the receiver to properly assemble the packet.  
         [0028]    [0028]FIG. 3 illustrates the staggering performed by the transmitting device T.  
         [0029]    The advantages of the invention, in general, and over the closest prior art solution include:  
         [0030]    1. variable length packets can be transmitted very efficiently at a low bus frequency while maintaining a bandwidth of 10 Gbps. Furthermore, in the present implementation, the segmentation of packets into 64-byte segments means that ATM cells can also be transmitted very efficiently over the bus.  
         [0031]    2. The described bus topology is easily amenable to quad OC48.  
         [0032]    3. Since the bus is divided into segments transmitted four-bytes at a time, there is only a need for a maximum of three empty bytes per packet. This scheme makes the bus more efficient and allows it to operate at a slower frequency while still achieving 10 Gbps rates.  
         [0033]    The invention is directed to the method and apparatus of partitioning packets into segments of predetermined size (for example, 64-bytes), serializing the segments, and transmitting them over a plurality of channels (for example, four) that have a staggered phase relationship to one another, and wherein the phase difference between adjacent channels (actually, adjacent segments in a sequence of segments that form the packet) and more than the maximum latency that can occur in any one channel, thereby maintaining the order of the serialized packet segments. The invention is not limited to variable-length packets as the invention can be used for both fixed-length cells and variable-length packets.  
         [0034]    This invention addresses an obstacle and solves the problem that will be encountered by any efforts to pass variable-length packet data between separate cards.  
         [0035]    While the invention has been described in relation to preferred embodiments of the invention, it will be appreciated that other embodiments, adaptations and modifications of the invention will be apparent to those skilled in the art.