Abstract:
A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

Description:
RELATED APPLICATIONS  
       [0001]     The present application is based on, and claims priority from, Taiwan Application Serial Number 93126240, filed Aug. 31, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety.  
       BACKGROUND  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to a method for detecting the data strobe signal (DQS) of a double data rate (DDR) synchronous dynamic random access memory (SDRAM). More particularly, the present invention relates to a method for detecting the data strobe signal when a DDR SDRAM is outputting the data.  
         [0004]     2. Description of Related Art  
         [0005]     In present data process systems, a SDRAM module is often used in memory unit. The SDRAM module is synchronous with the system, the data is accessed at rising edges of the system clock. Therefore, an SDRAM module can provide a higher data transmission rate than a memory module having an independent clock.  
         [0006]     A new memory module, called a double data rate (DDR) SDRAM module is similar to conventional SDRAM modules, but the data is accessed at both rising edges and falling edges of the system clock. Therefore, the DDR SDRAM module can provide double data transmission rate batter than the conventional SDRAM module. However, some problems have appeared because of the endless promotion of the system clock rate.  
         [0007]      FIG. 1  shows a timing diagram of data reading from a DDR SDRAM. CLK is the system clock. When a signal RC is enabled at low logic state with one clock cycle long as a reading command and then after passing through the latency  102 , the data will be transmitted in the data lines DQ at the rate of two data per clock cycle for reading. Assuming that eight data (data D 0 -D 7 ) can be read in a read operation. When the data is transmitted in the data lines DQ, a data strobe signal DQS, which is synchronous with the data lines DQ, is provided. Each rising edge and falling edge of the signal DQS indicates the one data arriving in the data line DQ. Signal DQS also provides a low logic state preamble  104  with one clock cycle to indicate data is arriving before transmitting the first data DO in the data lines DQ; and a low logic state postamble  106  with a half clock cycle to indicate the end of the data in the data lines DQ. Other than the foregoing conditions, the signal DQS maintains in a high impedance (HI-Z) status (between the high logic state and the low logic state), the signal DQS is a tristate logic signal.  
         [0008]     After the data and the data strobe signal DQS are outputted from the DDR SRAM, data in the data lines DQ is received next.  
         [0009]     On the whole, when a read command signal RC is asserted, an input enable signal TNI is enabled by a receiving unit to receive the data lines DQ and the data strobe signal DQS after a few time. When a preamble  104  of the data strobe signal DQS is detected by the input enable signal TNI, a high logic state of the input enable signal TNI will be maintained until a postamble  106  of the data strobe signal DQS is detected. The data receiving unit can provide a data reading signal ZI, which is synchronous with the data strobe signal DQS, for controlling the data receiving operation during the enable time of the input enable signal TNI, wherein the data receiving unit will read the data in the data lines DQ at both rising edges and falling edges of the data reading signal ZI.  
         [0010]     For a variety of reasons, such as the acceleration of clock frequency and different layouts of memory modules and circuit boards among all kinds of products, therefore the latency  102  is not the same (not a constant) for various products As a result, the appearance time of the preamble  104  of the data strobe signal DQS is also variable.  
         [0011]     In the conventional method, when asserting a reading command signal RC, the input enable signal TNI detects the preamble of the data strobe signal DQS after a fixed time. If the latency  102  is larger than the fixed time, the data read signal TNI will detect a high impedance part of the data strobe signal DQS, and then the data reading signal ZI will be unknown state. If the latency  102  is smaller than the fixed time, the input enable signal TNI will detect the data strobe signal DQS after the preamble, this will cause data reading lost.  
       SUMMARY  
       [0012]     The present invention provides a method for detecting the arrival timing of a data signal in a DDR SDRAM module.  
         [0013]     The data detecting method provided in the present invention can be applied in a DDR SDRAM module.  
         [0014]     In accordance with the foregoing and other objectives of the present invention, a reading command is firstly asserted and then data is outputted for a memory unit formed by the DDR SDRAM modules. Next, starting counting at the same time when the reading command is asserted. Stopping counting and the storing the counting value when a first data is outputted from the memory unit. Finally, for the identical memory unit, using the stored counting value to predict the data arrival timing in the subsequent reading operations.  
         [0015]     It is to be understood that both the foregoing general description and the following detailed description are by examples and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, of appended claims, and accompanying drawings where:  
         [0017]      FIG. 1  shows a timing diagram of the prior art;  
         [0018]      FIG. 2  shows a timing diagram of the present invention;  
         [0019]      FIG. 3  shows a flow chart of a method for counting latency in accordance with an embodiment of the present invention; and  
         [0020]      FIG. 4  shows a flow chart of a method for detecting preamble of a data strobe signal in accordance with an embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0022]     According to the foregoing description, it can be known that when a data receiving unit, such as. central processing unit (CPU), executes a reading operation from a memory unit of DDR SDRAM modules, time of the data return from the memory unit and time of the data strobe signal may be asynchronous, which causes a difficulty of the data receiving unit to detecting data receiving timing.  
         [0023]     Therefore, the embodiment according to the present invention, the data receiving timing is not a constant. Contrarily, data reading latency is counted and stored at first when the system operates. Then the arrival timing of the preamble of the data strobe signal can be predicted in accordance with the latency. After the data strobe signal is accurately detected, the data in the memory unit can be efficiently read.  
         [0024]      FIG. 2  illustrates an embodiment according to the present method. The purposes and the operations of a system clock CLK, a read command signal RC, data lines DQ and a data strobe DQS all are corresponding with the foregoing description. The present method is to obtain a latency  202  in data reading operation.  
         [0025]     In this embodiment, a TNDQS signal is defined at first, which can be enabled at high logic state or at low logic state. It is assumed that the TNDQS signal is enabled at high logic state herein. When the reading command signal RC is asserted, driving a rising edge  208  of the TNDQS signal simultaneously. And then the first raising edge  206  of the DQS signal drives a falling edge  210  of the TNDQS signal. That is to say, the enable duration of the TNDQS signal is as similar as the latency  202 . Furthermore, a ZIX signal is defined due to a delay between the falling edge  210  of the TNDQS signal and the first rising edge  206  of the DQS signal.  
         [0026]     Similarly, the ZIX signal can be enabled at a high logic state or at a low logic state. It is assumed that the ZIX signal is enabled at a low logic state herein. When the TNDQS signal is at low logic state (e.g. disable state), the ZIX signal is at high logic state (e.g. disable state). When the TNDQS signal is at high logic state (e.g. enable state), the ZIX signal is synchronous with the data strobe signal DQS. Otherwise, the high impedance state of the DQS signal causes the ZIX signal to be transited at high logic state (e.g. disable state). This transition can be implemented by a voltage comparative method which is popularly known by those skilled in the art. For example, a reference voltage, which voltage value is between the low logic state and the high impedance level, can be used to compare with the voltage of the DQS signal. Because the voltage of the DQS signal is higher than the reference voltage, thus a high logic state voltage is outputted and causes the ZIX signal to be transited at high logic state (e.g. disable state).  
         [0027]     Thus it can be seen from  FIG. 2 , rising edge  212  of the ZIX signal almostly synchronizes with the first rising edge  206  of the DQS signal. As a result, the duration between the rising edge  208  of the TNDQS signal and the rising edge  212  of the ZIX signal is identical with the latency  202  of data reading. Therefore, rising edge  208  of the TNDQS signal counts a counter register COUNT, which initial value is zero, and a counter register PHASE; and then rising edge  212  of the ZIX signal stops them. The counting value is then respectively latched in the accordingly to the counter register COUNT and PHASE.  
         [0028]     The counter register PHASE can provide higher timing resolution than counter register COUNT, because the counting rate of the counter register PHASE is four times of the system clock CLK, however, the counting rate of the counter register COUNT is two times of CLK. In practice, the counting rate can be designed according to the requirements and is not limited by the embodiment.  
         [0029]     According to the counting value stored in counter register COUNT or PHASE, the input enable signal TNI shown in  FIG. 1  can detect preamble of subsequent reading data.  
         [0030]     For example, when the data receiving unit issues a reading command signal, a reference counter register identical with the count register COUNT is simultaneously counted. If the counting value counted by the reference counter register is same as the counting value latched in the counter register COUNT, the input enable signal TNI is enabled for reading the data lines DQ and the data strobe signal DQS.  
         [0031]     Otherwise, when the data receiving unit issues a reading command signal, another reference count register identical with the count register PHASE is counted. If the counting value counted by the reference counter register is same as the counting value latched in the counter register PHASE, the input enable signal TNI is enabled for reading the data lines DQ and the data strobe signal DQS. Obviously, a higher timing resolution is provided in this example.  
         [0032]      FIG. 3  shows a flow chart of the method for evaluating latency in accordance with the present invention. In step  310 , respectively initialing both signal TNDQS and ZIX to its own initial state. In step  320 , enabling the signal TNDQS (high logic state) and counting a counter when a reading command is asserted. In step  330 , determining the logic state of the ZIX signal by comparing the voltage level of data strobe signal DQS with a reference voltage. If the voltage level of DQS is higher than the reference voltage, the ZIX signal is regarded as being in the disable state (high logic state); on the contrary, the ZIX signal is regarded as being in the enable state (low logic state). In step  340 , stopping counting when the ZIX signal transits from enable state to the disable state. In step  350 , storing a counting value counted by the counter, wherein the counting value is regarded as the latency.  
         [0033]      FIG. 4  shows a flow chart of the method for detecting preamble of data strobe signal DQS in accordance with the present invention. In step  410  using the foregoing method to evaluate the latency. In step  420 , a counter starts to count when a reading command (ex. reading command signal RC as shown in  FIG. 1  and  FIG. 2 ) is asserted to a memory unit. In step  430 , indicating the preamble by asserting a TNI signal when the counting value reaches to the latency.  
         [0034]     The present method can be implemented in any time, for example when the system is initializing or when the system is operating, to usually update the latency and make sure the most reading efficiency is obtained.  
         [0035]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.