Abstract:
An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Description:
CLAIM OF PRIORITY AND RELATED APPLICATIONS 
     This patent application is a conversion of and claims priority to U.S. Provisional Patent Application No. 61/250,830, entitled SYSTEMS AND METHODS FOR RESONANT CLOCKING INTEGRATED CIRCUITS, filed Oct. 12, 2009, which is incorporated herein in its entirety. This patent application is related to the technologies described in the following patents and applications, all of which are incorporated herein in their entireties:
     U.S. patent application Ser. No. 12/125,009, entitled R ESONANT  C LOCK AND  I NTERCONNECT  A RCHITECTURE FOR  D IGITAL  D EVICES WITH  M ULTIPLE  C LOCK  N ETWORKS , filed Oct. 12, 2009, which claims priority to U.S. Provisional Patent Application No. 60/931,582, entitled R ESONANT  C LOCK AND  I NTERCONNECT  A RCHITECTURE FOR  P ROGRAMMABLE  L OGIC  D EVICES , filed May 23, 2007;   U.S. patent application Ser. No. 12/903,154, entitled R ESONANT  C LOCK  D ISTRIBUTION  N ETWORK  A RCHITECTURE WITH  P ROGRAMMABLE  D RIVERS , filed Oct. 12, 2010;   U.S. patent application Ser. No. 12/903,158, entitled A RCHITECTURE FOR  C ONTROLLING  C LOCK  C HARACTERISTICS , filed Oct. 12, 2010;   U.S. patent application Ser. No. 12/903,166, entitled A RCHITECTURE FOR  A DJUSTING  N ATURAL  F REQUENCY IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010;   U.S. patent application Ser. No. 12/903,168, entitled A RCHITECTURE FOR  F REQUENCY -S CALED  O PERATION IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010;   U.S. patent application Ser. No. 12/903,172, entitled A RCHITECTURE FOR  S INGLE -S TEPPING IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010;   U.S. patent application Ser. No. 12/903,174, entitled A RCHITECTURE FOR  O PERATING  R ESONANT  C LOCK  N ETWORK IN  C ONVENTIONAL  M ODE , filed Oct. 12, 2010; and   U.S. patent application Ser. No. 12/903,188, entitled R ESONANT  C LOCK  D ISTRIBUTION  N ETWORK  A RCHITECTURE FOR  T RACKING  P ARAMETER  V ARIATIONS IN  C ONVENTIONAL  C LOCK  D ISTRIBUTION  N ETWORKS  filed Oct. 12, 2010.   

    
    
     FIELD OF INVENTION 
     This disclosure relates generally to clock distribution network architectures for digital devices with multiple clock networks and various clock frequencies such as microprocessors, application-specific integrated circuits (ASICs), and System-on-a-Chip (SOC) devices. 
     BACKGROUND OF THE INVENTION 
     Resonant clock distribution networks have been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through the reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance. 
     In practice, digital devices are often specified and designed to operate at multiple clock frequencies. For example, a high-performance microprocessor may be designed to operate at multiple clock frequencies ranging from 100 MHz to 3 GHz. The technique of operating a clock signal at different clock frequencies over time is commonly referred to as frequency scaling and is motivated by the need to reduce power consumption in semiconductor devices. Power consumption in digital semiconductor devices grows in proportion with the rate at which these devices switch between their digital values. When performance requirements decrease, this rate can be reduced by reducing the frequency of the clock signal, thereby reducing power consumption. 
     The operation of clock signals at more than a single frequency also arises in the context of device binning, that is, the practice of selling at a premium a device that, due to manufacturing variations, is capable of operating at a higher peak clock frequency than another device of identical design and functionality. For example, a batch of microprocessors that was fabricated on a “fast” semiconductor manufacturing corner may contain microprocessors capable of running at clock frequencies of up to 3 GHz, while an identical-in-design batch of microprocessors that was fabricated on a “typical” semiconductor manufacturing corner may contain microprocessors that can run at clock frequencies of at most 2 GHz. While of identical design, the microprocessors in the first “fast” batch can be sold at significantly higher prices, due to their better achieved performance. 
     The challenge with the deployment of resonant clock distribution networks in multi-frequency operation contexts is that these networks typically achieve their highest energy efficiency for a relatively narrow range of clock frequencies centered around the natural frequency of the resonant network. For clock frequencies outside this narrow range, energy efficiency degrades significantly, and to an extent that outweighs the inherent energy advantages of resonant clocking. For example, consider a microprocessor that has been designed with a target frequency of 3 GHz, but its digital logic can only achieve a peak clock rate of 2 GHz after manufacturing. In a non-resonant clock implementation of the microprocessor, the clock network can be operated at 2 GHz, consuming power in proportion to its 2 GHz operating frequency. In a resonant clock design, however, if the resonant clock network operates at 2 GHz, instead of its natural frequency of 3 GHz, its power consumption will significantly exceed the power consumption of the non-resonant design at 2 GHz. 
     In addition to excessive power consumption, when a resonant clock network operates away from its natural frequency, the shape of the clock waveform is increasingly deformed, as the mismatch between the natural and the operating frequency increases. In extreme situations, the peak clock frequency after manufacturing may be so far from the natural frequency of the resonant clock network that the clock waveform at the peak clock frequency becomes deformed to such an extent that incorrect operation of the clocked elements results, and the function of the overall device becomes incorrect. 
     It is possible to address the above challenges in a number of straightforward yet impractical ways. One such approach is to enable the adjustment of the natural frequency by providing for the selective introduction of capacitance to the resonant clock network. Since the energy efficiency of the resonant clock network decreases as its capacitance increases, adjusting the natural frequency by introducing capacitance compromises power savings at lower operating frequencies. Moreover, the area overhead of the spare capacitance may be prohibitively high. 
     Another approach to the adjustment of the natural frequency is the deployment of series or parallel combinations of inductors that can be selectively engaged. In general, such combinations require multiple inductors, or relatively complex inductor structures, resulting in potentially prohibitive area overheads, particularly when support for more than two natural frequencies is required. Moreover, depending on the target natural frequencies, certain combinations may be preferable. 
     Architectures for resonant clock distribution networks have been described and empirically evaluated in several articles, including “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al.,  International Symposium on Low - Power Electronic Design , August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” by Cooke, M., et al.,  International Symposium on Low - Power Electronic Design , August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al.,  Journal of Solid - State Circuits , Vol. 39, No. 9, September 2004; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al.,  IEEE  2006  Custom Integrated Circuits Conference , September 2006; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al.,  IEEE  2007  Custom Integrated Circuits Conference , September 2007. “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al.,  IEEE Journal of Solid State Circuits , Vol. 44, No. 1, January 2009. In all these articles, the resonant clock distribution networks are restricted to a single natural frequency. No attempt is made and no methods are proposed for adjusting the natural frequency of the resonant clock networks in a way that addresses the aforementioned challenges. 
     Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description. 
     SUMMARY OF THE DESCRIPTION 
     A resonant clock distribution network architecture is described herein that allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The architecture described herein is primarily targeted at the design of integrated inductors and exhibits no area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, low-power clocking requirements, and high-performance, for example, microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels. 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Other advantages and features will become apparent from the following description and claims. It should be understood that the description and specific examples are intended for purposes of illustration only and not intended to limit the scope of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       These and other objects, features and characteristics of the present invention will become more apparent to those skilled in the art from a study of the following detailed description in conjunction with the appended claims and drawings, all of which form a part of this specification. In the drawings: 
         FIG. 1  shows a typical architecture of a resonant clock distribution network. 
         FIG. 2  shows a typical driver design for resonant clocking with the clock load modeled as a lumped capacitor. 
         FIG. 3  shows an approach to adjusting natural frequency by selective introduction of capacitance in parallel to the clock load. 
         FIG. 4  shows an approach to adjusting natural frequency by selective introduction of inductance in parallel to the original inductor. 
         FIG. 5  shows an embodiment of the approach described herein for adjusting natural frequency by selective decoupling of inductors in the resonant clock distribution network. 
         FIG. 6  shows an alternative embodiment of the approach described herein for adjusting natural frequency by selective decoupling of inductors in the resonant clock distribution network. 
     
    
    
     The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. 
     In the drawings, the same reference numbers and any acronyms identify elements or acts with the same or similar structure or functionality for ease of understanding and convenience. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Various examples of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. One skilled in the relevant art will understand, however, that the invention may be practiced without many of these details. Likewise, one skilled in the relevant art will also understand that the invention can include many other obvious features not described in detail herein. Additionally, some well-known structures or functions may not be shown or described in detail below, so as to avoid unnecessarily obscuring the relevant description. 
     The terminology used below is to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the invention. Indeed, certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. 
       FIG. 1  shows a typical resonant clock distribution network architecture for a semiconductor device. In this network, a buffered distribution network is used to distribute a reference clock signal to multiple resonant clock drivers that are in turn used to drive the clock signal across an all-metal clock distribution network. Typically, this all-metal network has an approximately symmetric topology, delivering the clock signal to the clocked elements (for example, flip-flops and clock gaters) of the semiconductor device with very low skew. Each resonant clock driver incorporates an inductor that is used to provide additional drive strength with low energy consumption by resonating the parasitic capacitance of the load seen by the driver. 
       FIG. 2  shows a typical resonant clock driver design, in which the part of the overall clock distribution network serviced by the resonant clock driver, is modeled as a lumped capacitor C in series with a lumped resistance R. This driver comprises a pull-up PMOS and a pull-down NMOS device for driving the clock. The PMOS device is connected between the clock node and the power supply terminal. The NMOS device is connected between the clock node and the ground terminal. Both devices are driven by the reference clock signal. An inductor L is connected between the clock node and a supply node with voltage at approximately the mid-point of the clock signal oscillation. For example, if the clock signal oscillates between 0V and 1V, the mid-point supply voltage is approximately 0.5V. In the driver of this figure, the mid-point is implemented using two capacitors Cdd and Css. Capacitor Cdd is connected between the mid-point and the power supply terminal. Capacitor Css is connected between the mid-point and the ground terminal. To maximize energy savings, the value of the inductor is approximately chosen so that the LC tank set-up by the inductor and the parasitic capacitance of the clock distribution network has a natural frequency that is approximately equal to the frequency of the reference clock signal. The switch S can be used to selectively decouple the inductor from the mid-point supply, thus providing the option of driving the clock network in non-resonant mode. When the control signal EN turns the switch on, the driver operates in resonant mode. When the switch is off, then the driver operates in non-resonant mode. In this figure, the switch is shown conceptually as a single NMOS transistor. In general, this switch will be typically implemented as a transmission gate that incorporates both NMOS and PMOS transistors. 
     The energy efficiency of the resonant clock driver depends on design and operating parameters. The quality factor Q of the resonant system is an indicator of its energy efficiency. This factor is proportional to (L/C) 1/2 /R. In general, energy efficiency decreases as R increases, due to the I 2 R losses associated with the flow of the current/that charges and discharges the parasitic clock load C through the resistance R. Also, for a fixed natural frequency, energy efficiency decreases as capacitance C increases, since the current flowing through resistance R increases. 
     The mismatch between the natural frequency of the resonant LC-tank systems and the frequency of the reference clock signal is another important factor that affects the energy efficiency of the resonant clock network. As the frequency of the reference clock that drives the resonant clock driver moves further away from the natural frequency of the resonant clock driver&#39;s LC-tank, energy efficiency decreases. When the mismatch between the two frequencies becomes too large, the energy consumption of the resonant clock driver becomes excessive and impractically high. Moreover, the shape of the clock waveform is so distorted that it cannot be reliably used to clock flip-flops or other clocked storage elements. Consequently, resonant clock drivers tend to have a narrower range of clock frequencies within which they operate efficiently than the range of clock frequencies typically supported by a semiconductor device that uses frequency scaling. In practice, to support the broad range of operating frequencies used in a frequency-scaled semiconductor device, it is desirable for the LC-tank of the resonant clock driver to be capable of operating at more than one natural frequency. 
       FIG. 3  shows a possible approach for supporting a second natural frequency through selective introduction of capacitance in parallel to the clock load. A switch P is used to selectively connect capacitor Cp in parallel to the parasitic capacitance C of the clock network. When switch P is turned off by control signal ENP, the total capacitance seen at the clock node is C, and the natural frequency f1 of the resonant clock network is proportional to 1/(LC) 1/2 . When switch P is turned on, the total capacitance seen at the clock node increases to C+Cp, resulting in a lower natural frequency f2, which is proportional to 1/(L(C+Cp)) 1/2 . The main drawback of this approach is that due to the additional capacitance Cp and the resistance introduced by switch P, operation at f2 has a lower Q factor than at f1, thus resulting in decreased relative energy savings. Another drawback of this approach is that the implementation of capacitance Cp using an integrated capacitor results in significant area overheads. For example, to obtain f2=f1 1/2 , capacitance Cp must be approximately equal to the capacitance C of the clock distribution network. 
       FIG. 4  shows another possible approach for supporting a second natural frequency in a resonant clock driver. In this approach, an inductor Lp is selectively introduced in parallel to the original L of the resonant clock driver using a pair of switches P 1  and P 2 . When the two switches are turned off, the total inductance in the resonant clock network is L, and the natural frequency f1 of the resonant clock network is proportional to 1/(LC) 1/2 . When the two switches are turned on, the total inductance decreases to L Lp/(L+Lp), resulting in a higher natural frequency f2, which is proportional to 1/((L+Lp)C) 1/2 . The main drawback of this approach is that due to the decrease in total inductance, and the additional resistance introduced by switches P 1  and P 2 , operation at f2 has a lower Q factor than at f1, thus resulting in decreased relative energy savings. For clock networks operating at GHz frequencies, this decrease in energy savings is exacerbated by the fact that total resistance at the higher operating frequency f2 will be higher than at f1, due to skin effect. Another drawback of this approach is that inductance Lp must be implemented using an inductor in parallel to L, generally resulting in significant area overheads. For example, to obtain f2=f1 1/2 , inductance Lp must be approximately equal to the original inductance L in the resonant clock driver. 
       FIG. 5  shows an embodiment of an approach for adjusting a resonant clock network so that it supports multiple natural frequencies by selective decoupling of inductors connected to the resonant clock network. This embodiment relies on the existing inductors and decoupling switches S 1 , . . . , SM of the resonant clock drivers, thus incurring no additional overheads over the original resonant clock distribution network design. If all switches are turned on, the M inductors present an effective inductance of L/M, assuming that they all have equal inductance L. Moreover, the M clock loads present a total capacitance of M C. The resulting natural frequency f1 is proportional to 1/(LC) 1/2 . The natural frequency can be modified by decoupling inductors from the resonant clock distribution network using the control signals EN 1 , . . . , ENM. For example, if M/2 of the switches are turned off, only M/2 inductors remain coupled to the resonant clock network, yielding an effective inductance L/M/2=2 L/M and a natural frequency proportional to 1/(2LC) 1/2 . If 3M/4 of the switches are turned off, only M/4 inductors remain coupled to the resonant clock network, resulting in an effective inductance equal to L/M/4=4L/M and a natural frequency proportional to 1/(4LC) 1/2 . 
     The above described approach can be generalized in a straightforward manner to yield multiple natural frequencies by decoupling the appropriate number of inductors from the resonant clock network. In general, the inductors are not restricted to have equal inductance values. Moreover, the clock loads corresponding are not restricted to have equal capacitance values. When only a subset of these inductors is coupled to the resonant clock network, the effective inductance is determined by their parallel combination. The effective capacitance of the resonant clock network is determined by the parallel combination of the individual capacitors. 
       FIG. 6  shows an alternative embodiment of the approach described herein. In this embodiment, control signals EN 1 ′, . . . , ENM′ are included to selectively enable the drivers in the resonant clock network. 
     A key advantage of the proposed approach is that it requires no additional inductors over the original network with natural frequency f1. Moreover, it does not require any additional capacitors. 
     Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense (i.e., to say, in the sense of “including, but not limited to”), as opposed to an exclusive or exhaustive sense. As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements. Such a coupling or connection between the elements can be physical, logical, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
     The above Detailed Description of examples of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific examples for the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. While processes or blocks are presented in a given order in this application, alternative implementations may perform routines having steps performed in a different order, or employ systems having blocks in a different order. Some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified to provide alternative or sub-combinations. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed or implemented in parallel, or may be performed at different times. Further any specific numbers noted herein are only examples. It is understood that alternative implementations may employ differing values or ranges. 
     The various illustrations and teachings provided herein can also be applied to systems other than the system described above. The elements and acts of the various examples described above can be combined to provide further implementations of the invention. 
     Any patents and applications and other references noted above, including any that may be listed in accompanying filing papers, are incorporated herein by reference. Aspects of the invention can be modified, if necessary, to employ the systems, functions, and concepts included in such references to provide further implementations of the invention. 
     These and other changes can be made to the invention in light of the above Detailed Description. While the above description describes certain examples of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the invention disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the invention under the claims. 
     While certain aspects of the invention are presented below in certain claim forms, the applicant contemplates the various aspects of the invention in any number of claim forms. For example, while only one aspect of the invention is recited as a means-plus-function claim under 35 U.S.C. §112, sixth paragraph, other aspects may likewise be embodied as a means-plus-function claim, or in other forms, such as being embodied in a computer-readable medium. (Any claims intended to be treated under 35 U.S.C. §112, ¶ 6 will begin with the words “means for.”) Accordingly, the applicant reserves the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the invention.