Abstract:
Disclosed is an MOSIC including a plurality of silicon gate type MOSFET&#39;s in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Description:
This application is a continuation of application Ser. No. 07/247,506, filed on Sept. 22, 1988 and now abandoned which is a continuation of application Ser. No. 634,037, filed July 24, 1984 and now U.S. Pat. No. 4,792,871, which is a continuation application of Ser. No. 288,466, filed July 30, 1981, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to semiconductor devices and a process for producing the same. In particular, the invention relates to static memory semiconductor devices employing FET&#39;s (field effect transistors) and a process for producing them. 
     A memory portion of a static memory semiconductor device consists of a plurality of memory cells, each memory cell being made up of a plurality of MOS FET&#39;s. In a static memory cell of this type, the electrode has heretofore been connected to the source region or to the drain region of the MOS FET by using an aluminum wiring. However, since the memory portion occupies a very wide area in a chip in which the static memory semiconductor device is formed, the area occupied by the memory portion must be reduced if it is desired to increase the degree of integration of the semiconductor devices. In an attempt to reduce the area of the memory portion or to reduce the size of the memory cell, therefore, attempts have been made to connect a wiring 8 of polycrystalline silicon directly to the source region or the drain region 7 that is surrounded by a field SiO 2  film 5 and a polycrystalline silicon gate 6, as shown in FIGS. 1 and 2. However, the polycrystalline silicon wiring 8 is composed of a first layer that is formed simultaneously with the polycrystalline silicon gate 6, and is usually doped with phosphorus ions of a high concentration to reduce the resistance. The phosphorus ions are doped simultaneously with the formation of the source region and the drain region. While the phosphorus ions are being doped, the depth of an n +  -type diffusion layer 7 increases beneath the polycrystalline silicon wiring. Namely, the diffusion layer 7 swells beneath the polycrystalline silicon gate 6 as indicated by a dotted line 10 in FIG. 2, and it becomes difficult to obtain an MOSFET having a desired channel length or a desired shallow source region or drain region. To prevent this defect, a sufficient distance d 1  must be provided between an end portion of the polycrystalline silicon gate 6 and an end portion of the polycrystalline silicon wiring 8. This, however, contradicts the purpose of reducing the size of the cell; the degree of integration of the semiconductor devices is not increased. 
     Therefore, the inventors of the present invention have developed a method by which the polycrystalline silicon gate 6 and the polycrystalline silicon wiring 8 are formed as shown in FIG. 3, and are covered by an insulating film 9 such as PSG (phosphorus silicate glass). 
     A portion of the insulating film 9 is then selectively removed by photoetching, and an aluminum wiring 10 is formed in order to connect a semiconductor region 7 to the polycrystalline silicon wiring 8. It was, however, discovered that when the aluminum layer is brought into direct contact with the semiconductor region (source or drain region), there is formed an aluminum-silicon alloy which destroys a pn junction at a depth of as much as about 1 μm in the source or the drain region. 
     SUMMARY OF THE INVENTION 
     The present invention is to solve the above-mentioned defects and problems. 
     A first object of the present invention therefore is to provide an MOSFET which enables the degree of integration to be increased. 
     A second object of the present invention is to provide a process for producing such MOSFET&#39;s. 
     A third object of the present invention is to provide a memory cell having a high degree of integration. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plan view showing a portion of an MOSFET which is used for a conventional memory cell; 
     FIG. 2 is a section view along the line A--A&#39; of FIG. 1; 
     FIG. 3 is a section view of an MOSFET developed by the inventors of the present invention, which serves as a prerequisite for the present invention; 
     FIG. 4 is a plan view showing the construction of a static memory device according to the present invention; 
     FIG. 5 is a circuit diagram of a memory cell in the memory device; 
     FIG. 6 is a plan view of an MOSFET according to an embodiment of the present invention; 
     FIG. 7 is a section view of the MOSFET along the line A--A&#39; of FIG. 6; 
     FIGS. 8(a) to 8(f) are section views showing the steps in a process for producing the MOSFET of FIG. 7; 
     FIG. 9 is a plan view of the memory cell of FIG. 5 formed in accordance with the present invention; 
     FIGS. 10(a) to 10(f) are section views showing the steps in a process for producing the MOSFET according to another embodiment of the present invention; and 
     FIGS. 11(a) to 11(f) are section views showing the steps in a process for producing a CMOSIC according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 4, a static memory device according to the present invention has a memory portion (memory array) 2 which consists of a plurality of single-channel (for example, n-channel) MOSFET&#39;s formed in a well region that is formed in a portion of a silicon semiconductor chip 1. A peripheral circuit 3 consisting of complementary MOSFET&#39;s is formed by the side of the memory portion 2 to drive it. Further, a required number of bonding pads (terminals) 4 are formed in the periphery of the chip 1. 
     A memory cell of a single bit consists of four MOSFET&#39;s Q 1 , Q 2 , Q 3  and Q 4 , and load resistors R 1  and R 2 , as shown in FIG. 5, in which V CC  denotes a power supply of a voltage of, for example, +5 volts, W denotes a word line, and D 1  and D 2  denote data lines. 
     FIG. 6 is a plan view of an MOSFET which constitutes a memory cell of FIG. 5, and FIG. 7 is a section view along the line A--A&#39; of FIG. 6. In FIGS. 6 and 7, an SiO 2  film (gate insulation film) 13 of a thickness smaller than a field SiO 2  film 12 is formed on the surface of a region (active region) in a portion of a p-type substrate that is surrounded by the thick field SiO 2  film 12. On the SiO 2  film 13 is selectively formed a gate polycrystalline silicon layer 14 in a manner to traverse the active region. Further, polycrystalline silicon wirings 15 and 15&#39; of the first layer are selectively formed so as to stretch from the SiO 2  film 13 to the field SiO 2  film 12 in a direction to cross the gate polycrystalline silicon layer 14 at right angles thereto. An n +  -type source region 16 and an n +  -type drain region 17 are formed in the surface of the active region which is surrounded by the gate polycrystalline silicon layer 14, field SiO 2  film 12, and polycrystalline silicon wirings 15, 15&#39; of the first layer. Further, there are formed a second polycrystalline silicon wiring layer 19 that comes into direct contact with a portion of the surface of said source region 16 and with a portion of the surface of the first polycrystalline silicon wiring layer 15, and a second polycrystalline silicon wiring layer 19&#39; that comes into direct contact with a portion of the surface of the drain region 17 and with a portion of the surface of the first polycrystalline silicon wiring layer 15&#39;. An aluminum wiring 21 is connected to the first polycrystalline silicon wiring layer 15&#39;. 
     FIGS. 8(a) to 8(f) are section views showing the steps in a process for producing the MOSFET that is shown in FIGS. 6 and 7. The process for producing the MOSFET of FIGS. 6 and 7 will be described below in conjunction with FIGS. 8(a) to 8(f). 
     Referring to FIG. 8(a), first, a field SiO 2  film 12 is formed on one main surface of a p-type silicon substrate 11 by the low-temperature selective oxidation method, and an SiO 2  film (gate insulation film) 13 of a thickness smaller than that of the field SiO 2  film 12 is formed on the surface of the active region surrounded by the field SiO 2  film 12. Then, polycrystalline silicon is deposited on the whole surfaces of the field SiO 2  film 12 and the gate SiO 2  film 13, and is doped with phosphorus ions of a relatively high concentration to decrease its resistance. The polycrystalline silicon is then subjected to the selective photoetching, in order to form a polycrystalline silicon gate 14 and first polycrystalline silicon wiring layers 15, 15&#39;. 
     Referring to FIG. 8(b), n-type impurities are introduced into the surface of the p-type silicon substrate 11 with the polycrystalline silicon gate 14 and first polycrystalline silicon wiring layers 15, 15&#39; as a mask, in order to form, in the p-type substrate, a semiconductor region that forms a pn junction relative to the substrate. For instance, n-type impurity ions of phosphorus or arsenic are injected into the p-type silicon substrate 11, followed by the annealing (heat treatment), to form the n +  -type source region 16 and drain region 17 having a desired depth in the p-type silicon substrate 11. 
     Referring to FIG. 8(c), an SiO 2  film 18 is formed as a first interlayer insulation film on the whole surface of the p-type substrate 11 by the thermal oxidation method or the CVD (chemical vapor deposition) method. Then, portions of the surface of the source region 16 and the drain region 17 are exposed by the contact photoetching. 
     Referring to FIG. 8(d), a second polycrystalline silicon layer is deposited on the whole surface of the substrate 11, and is doped with phosphorus ions of a relatively small concentration. Then, unnecessary portions of the polycrystalline silicon are removed by the patterning. Thus, there are formed second polycrystalline silicon wiring layers 19, 19&#39; to connect the source region 16 and the drain region 17 to the first polycrystalline silicon wiring layers 15, 15&#39;. 
     Referring to FIG. 8(e), the first polycrystalline silicon wiring layer 15&#39; is selectively exposed and, then, a PSG (phosphorus silicate glass) film 20 is deposited on the whole surface of the p-type substrate 11 to form a second interlayer insulation film (or passivation film). 
     Referring to FIG. 8(f), portions of the second interlayer insulation film 20 are selectively removed, and an aluminum wiring (third wiring) 21 which connects to the second polycrystalline silicon wiring layer is formed by vaporizing aluminum. 
     According to the present invention which makes use of a polycrystalline silicon wiring layer (second polycrystalline silicon wiring layer) in addition to the gate wiring layer (first polycrystalline silicon wiring layer) and electrode wiring of aluminum as mentioned above, it is possible to connect the first polycrystalline silicon wiring layer to a semiconductor region such as source region or drain region selectively formed in the substrate via the second polycrystalline silicon wiring layer. Therefore, there is no need to deeply form the semiconductor region, or to increase the distance between the gate wiring 14 and the first polycrystalline silicon wiring layers 15, 15&#39;, or between the gate wiring 14 and the second polycrystalline silicon wiring layers 19, 19&#39;. Consequently, the degree of integration of the semiconductor devices can be increased. Further, since aluminum is not directly connected to the diffusion layer, there takes place no Al-Si reaction which destroys the pn junction. 
     FIG. 9 is a plan view of a static memory cell according to the present invention, which constitutes the circuit of the memory cell of FIG. 5. In FIG. 9, portions surrounded by a dot-dash line serve as active regions that are surrounded by the field insulation film 12, most of the regions thereof being diffusion regions (source and drain regions). A portion of the diffusion region is connected to ground line GND. 
     A solid line 14 denotes a first polycrystalline silicon wiring layer (gate wiring layer). A portion of the active region which crosses the wiring layer 14 works as a channel portion 22. MOS memory portions Q 1 , Q 2 , Q 3  and Q 4  are thus formed. A portion surrounded by a solid line 19 denotes a second polycrystalline silicon wiring layer which is connected to the first polycrystalline silicon wiring layer 14 via diffusion regions of Q 1  and Q 2 , and a contact portion. Portions of the second polycrystalline silicon wiring layer 19 serve as high resistances R 1 , R 2 , and are inserted between Q 3  and Q 4  and are connected to the power supply V CC . Portions D 1 , D 2  surrounded by a broken line serve as data lines consisting of an aluminum wiring 21, and are connected to the diffusion regions of Q 1  and Q 2  via a contact portion of the second polycrystalline silicon layer that is superposed on the diffusion region. 
     In the thus constructed memory cell, the second polycrystalline silicon wiring layer is used for the power supply. Therefore, the impurities are doped in such small amounts that they do not affect the diffusion region. Accordingly, the depth of the source and drain regions is reduced, and the channel length of the gate portion is reduced to increase the degree of integration. 
     FIGS. 10(a) to 10(f) are section views showing the steps in a process for producing an MOSFET which constitutes the memory of FIG. 5 according to another embodiment of the present invention. 
     Referring to FIG. 10(a), a field SiO 2  film 42 is formed on one main surface of a p-type silicon substrate 41 by the low temperature selective oxidation method, and an SiO 2  film (gate insulation film) 43 having a thickness smaller than that of the field SiO 2  film 42 is formed on the surface of the active region surrounded by the field SiO 2  film 42. Then, polycrystalline silicon is deposited on the whole surfaces of the field SiO 2  film 42 and the gate SiO 2  film 43, and is doped with phosphorus ions of a relatively high concentration to reduce its resistance. The polycrystalline silicon is then subjected to the selective photoetching to form a polycrystalline silicon gate 44 and first-layer polycrystalline silicon wirings 45, 45&#39;. In this case, the polycrystalline silicon wirings 45, 45&#39; are not permitted to stretch onto the gate SiO 2  film 43. 
     Referring to FIG. 10(b), n-type impurities are introduced into the surface of the p-type silicon substrate 41 with the polycrystalline silicon gate 44 and the field SiO 2  film 42 as a mask, thereby to form, in the p-type substrate, a semiconductor region that forms a pn junction with respect to the substrate. For example, n-type impurity ions such as phosphorus ions or arsenic ions are introduced into the p-type silicon substrate 41 by the ion injection, followed by annealing (heat treatment) to form the n +  -type source region 46 and drain region 47 having a desired depth in the p-type silicon substrate 41. 
     Referring to FIG. 10(c), an SiO 2  film 48 is formed as a first interlayer insulation film on the whole surface of the p-type substrate 41 by the thermal oxidation method or the CVD (chemical vapor deposition) method. Then, portions of the surface of the source region 46 and the drain region 47 are exposed by the contact photoetching. In this case, portions of the first polycrystalline silicon wiring layers 45, 45&#39; are also exposed. 
     Referring to FIG. 10(d), a second polycrystalline silicon layer is deposited on the whole surface of the substrate 41, and is doped with phosphorus ions of a relatively small concentration. Thereafter, unnecessary portions of the polycrystalline silicon are removed by patterning. Thus, there are formed second polycrystalline silicon wiring layers 49, 49&#39; to connect the source region 46 to the drain region 47, and to connect the first polycrystalline silicon wiring layers 45, 45&#39; together. 
     Referring to FIG. 10(e), the first polycrystalline silicon wiring layer 45&#39; is selectively exposed, and a PSG (phosphorus silicate glass) film 50 is deposited on the whole surface of the p-type substrate 41 to form a second interlayer insulating film (or passivation film). 
     Referring to FIG. 10(f), a portion of the second interlayer insulation film 50 is selectively removed, and an aluminum wiring (third wiring) 51 which connects to the first polycrystalline silicon wiring layer 45&#39; is formed by vaporizing aluminum. 
     According to the above-mentioned embodiment, the first polycrystalline silicon wiring layers 45, 45&#39; are not permitted to stretch onto the gate SiO 2  film 43, but are terminated on the thick field SiO 2  film 42. Therefore, the areas of the source region 46 and the drain region 47 can be reduced. In other words, the degree of integration of memory cells can be increased. 
     FIGS. 11(a) to 11(f) illustrate a process when the present invention is adapted to the manufacture of a complementary MOSIC. This will be described below for each of the manufacturing steps. 
     Referring, first, to FIG. 11(a), boron ions are injected into a portion of the surface of an n-type silicon substrate 23 to form a p-type well region 24. A field SiO 2  film 25 is selectively formed on the surface of the n-type substrate 23 and the well region 24. Then, an SiO 2  film 26 of a thickness of about 380 angstroms is formed by gate oxidation on the surface of the n-type substrate 23 and the well region 24 that are surrounded by the field SiO 2  film 25. Then, the polycrystalline silicon is deposited to a thickness of about 3500 angstroms, and is doped with phosphorus ions (at 1000° C., for 5 minutes, 20 minutes and 5 minutes). A polycrystalline silicon gate 27 and a first polycrystalline silicon wiring layer 28 are formed by photoetching the polycrystalline silicon. 
     Referring to FIG. 11(b), the surfaces of the polycrystalline silicon gate 27 and the first polycrystalline silicon wiring layer 28 are lightly oxidized at a temperature of 850° C., and an Si 3  N 4  is deposited on the whole surface of the substrate to a thickness of 1000 angstroms. Thereafter, only the Si 3  N 4  is selectively removed by etching from the surface of the p-type well region 24. Namely, the Si 3  N 4  film 29 is left on the surface of the n-type substrate 23 on which the p-type well region 24 has not been formed. Arsenic ions are introduced into the p-type well region by the injection method using the Si 3  N 4  film 29 as a mask. Thereafter, an n +  -type source region or drain region 30 is formed by the annealing. Then, by using the Si 3  N 4  film 29 as a mask for selective oxidation, the low-temperature selective oxidation is effected to increase the thickness of the SiO 2  film 31 on the surfaces of the polycrystalline silicon gate 27, first polycrystalline silicon wiring layer 28, and on the surface of the source or drain region 30. 
     Referring to FIG. 11(c), the Si 3  N 4  film 29 is removed by hot phosphoric acid, and an Si 3  N 4  film 32 is newly deposited to a thickness of about 500 angstroms. A portion of the source or drain region 30 is exposed by effecting the contact photoetching onto the Si 3  N 4  film 32 and the underlying SiO 2  film 31. A PSG (phosphorus silicate glass) film 33 is then deposited on the whole surfaces of the n-type substrate 11 and the well region 24, and is annealed at 1000° C. in a nitrogen atmosphere. 
     Referring to FIG. 11(d), a portion of the PSG film 33 is removed by etching, and boron ions are introduced into the p-channel side (n-type substrate) by the ion injection method through the Si 3  N 4  film 32. Thus, the p-type source and drain regions 37 are formed. 
     Referring to FIG. 11(e), the PSG film 33 is removed to expose the surface of the n +  -type diffusion region 30 and the first polycrystalline silicon wiring layer 28 on the n-channel side (p-well side). A second polycrystalline silicon layer 34 (3500 angstroms) is deposited on the p-channel side and on the n-channel side, and the polycrystalline silicon layer 34 is doped with phosphorus ions while masking the second polycrystalline silicon layer 34 on the p-channel side. Thereafter, unnecessary portions of the polycrystalline silicon layer 34 are removed by photoetching. Thus, the second polycrystalline silicon wiring 34 is formed which connects to the n +  -type region 30 and to the first polycrystalline silicon wiring layer 28. 
     Referring to FIG. 11(f), the second polycrystalline silicon wiring layer 34 is lightly oxidized, a PSG film 35 is deposited thereon to a thickness of about 6000 angstroms, followed by annealing in a nitrogen atmosphere, and the films are selectively removed by the contact photoetching. Then, aluminum is deposited followed by patterning to form an aluminum wiring (electrode) 36 that connects to the p +  -type diffusion region 37 and to the second polycrystalline silicon wiring layer 34. 
     In the CMOS device obtained by the above-mentioned process, the aluminum wiring 36 is connected at a portion to the diffusion region (p + ) 37, and is connected at another portion to the diffusion region (n + ) 30 via the second polycrystalline silicon wiring layer 34. At still another portion, furthermore, the aluminum wiring 36 is connected to the first polycrystalline silicon wiring layer 28 via the second polycrystalline silicon wiring layer 34. 
     According to the present invention as mentioned in the foregoing, the first wiring layer or the third aluminum wiring layer is connected to the diffusion regions via the second wiring layer. Therefore, increased freedom is provided for laying out the wiring. Consequently, the degree of integrating the semiconductor devices can be increased, for example, by 10 to 20%. 
     The present invention can be effectively adapted to the MOS memory devices having polycrystalline silicon wirings of a multi-layer construction, and especially to static memory devices manufactured by the CMOS process.