Abstract:
A charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor. The higher efficiency the pre-charge MOSFET is, the lower the gate level of a pass transistor is. Thus, the charge sharing efficiency becomes better, and the body effect will be eliminated. The following pump stage is the same as the first pump stage. In addition, this pre-charging is implemented by PMOSFET only; therefore, only a single well is needed and then a small layout area can be achieved. Consequently, a high efficiency negative pump can be obtained.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to integrated circuits and, in particular, to charge pump circuits used in integrated circuits. 
   2. Description of the Related Art 
   In some integrated circuits, it is desirable to have a circuit that provides a relatively high negative voltage. This is particularly true for integrated circuits that include memory devices, such as, for example, electrically erasable programmable read-only-memory (EEPROM) devices. The high negative voltage is applied to control gates of memory cells during erasure to erase the data stored in the memory cells. 
   Disadvantageously, many conventional circuits suffer from significant body-effect, which modulates a transistor threshold voltage when the voltage between the bulk and the source is not zero. For example, the body effect can cause the effective threshold voltages of the capacitor-connected MOSFET transistors in one or more pump stages to increase. Because the clock signals have small amplitudes, the body effect can cause transistor conductance to decrease. As transistor conduction decreases, the affected pump stages can become more resistive, which can disadvantageously limit current and adversely affect the charge pump efficiency. 
   While attempts have been made to reduce the body effect, using certain techniques, the gate of pre-charge MOSFET is insufficiently negative enough, and the pre-charge efficiency is relatively low. 
   SUMMARY OF THE INVENTION 
   The present invention relates to charge pump circuits used in integrated circuits, such as FLASH/EEPROM memory circuits. For example, the charge pump can be a PMOS negative pump circuit used to generate a negative voltage. In one example embodiment, a circuit reduces the body effect influence, which is typically present in a PMOS negative pump circuit, by using a sub-pump to increase pre-charge efficiency. In particular, the gate of the pre-charge MOSFET is pumped down to a very negative level. The charge pump efficiency is thereby improved. 
   One example embodiment provides a charge pump circuit, comprising: a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor; and a second pump stage coupled to the first pump stage, the second pump stage including a second sub-pump coupled to a second pre-charge MOSFET transistor, wherein the second sub-pump is used to pump down a gate of the second pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the second pre-charge MOSFET transistor. 
   Another example embodiment provided a charge pump circuit, comprising: a pre-charge transistor having a source, a gate, and a drain; a discharge transistor coupled to the gate of the pre-charge transistor, wherein the discharge transistor selectively discharges the pre-charge transistor; a pass transistor coupled to the source of the pre-charge transistor; and an initialization transistor coupled to the pass transistor, wherein the initialization transistor initializes the drain of the pass transistor. 
   Still another example embodiment provides memory device, comprising: non-volatile memory cells; a charge pump coupled to the memory cells to erase the memory cells, the charge pump comprising: a pre-charge transistor having a source, a gate, and a drain; a discharge transistor coupled to the gate of the pre-charge transistor, wherein the discharge transistor selectively discharges the pre-charge transistor; a pass transistor coupled to the source of the pre-charge transistor; and an initialization transistor coupled to the pass transistor, wherein the initialization transistor initializes the drain of the pass transistor. 
   In one embodiment, the circuit is implemented using a small layout in a single N-well, although other embodiments can be implemented in multiple wells or otherwise. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-B  illustrate an example pump circuit and a clock timing diagram. 
       FIGS. 2 and 3  illustrate example actual plots of charge pump clock and node voltages as a function to time. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The present invention relates to charge pump circuits used in integrated circuits, such as FLASH/EEPROM memory circuits. For example, the charge pump can be a PMOS negative pump circuit used to generate a relatively high negative voltage that can be applied to memory cell control gates to erase memory cell data. In one embodiment, a circuit reduces the body effect influence, which is typically present in a PMOS negative pump circuit, by using a sub-pump to increase pre-charge efficiency. In particular, the gate of the pre-charge MOSFET is pumped down to relatively very negative level. The charge pump efficiency is thereby improved. 
     FIG. 1A  illustrates an example embodiment of a P channel charge pump circuit  100 . In this example, the illustrated transistors are MOSFETs. The example circuit  100  includes three stages, although other embodiments can include fewer or more stages, such as five, seven, nine, or still additional stages. For example, more stages can be connected together to generate a more negative voltage. In this example, the circuit includes an initial stage, a stage  1 , and a stage  2 . As will be described in greater detail herein, Stage  1  includes a sub-pump  102  and a pre-charge MOSFET transistor M 8 . Likewise, stage  2  includes a sub-pump  104  and a pre-charge MOSFET transistor M 11 . The sub-pump is used to pump down the gate of the corresponding pre-charge MOSFET transistor to thereby increase the pre-charge efficiency. 
   The inputs to the P-channel charge pump circuit  100  include a four phase clock, including clock signals DP 1 , DP 2 , DP 3 , and DP 4 . In one embodiment, the clock signals DP 1 , DP 2 , DP 3 , and DP 4  periodically alternate between ground and approximately a supply voltage, which for example can be 1.8 volts, 3.3 volts, or other voltages. 
   Referring to  FIG. 1A , transistors M 1  (in the initial stage), M 2  (in stage  1 ), and M 3  (in stage  2 ) are pass transistors. Transistors M 4  (in the initial stage), M 8  (in stage  1 ), and M 11  (in stage  2 ) are pre-charge transistors. Transistors M 6  and M 10  are configured to act as diodes and are used to correspondingly keep Node  3  (including the gate of transistor M 8 ) and Node N 6  (including the gate of transistor M 11 ) at a negative voltage level. 
   Transistors M 5  (in stage  1 ) and M 9  (in stage  2 ) are initialization transistors that have their gate and source coupled together. The initialization transistors M 5  and M 9  correspondingly initialize the N 2  and N 5  under a transistor threshold voltage above ground. Transistors M 7  (in stage  1 ) and M 12  (in stage  2 ) are discharge transistors. 
   In particular, in this example clock signal DP 4  is capacitor coupled via capacitor C 1  to the gate of pass transistor M 1  and the drain of pre-charge transistor M 4  (node N 1 ). The sources of pass transistor M 1  and pre-charge transistor M 4  are coupled to ground. 
   Node N 2  connects the drain of pass transistor M 1 , the source of pass transistor M 2 , the gate of pre-charge transistor M 4 , the drain of initialization transistor M 5 , the source and gate of transistor M 6 , and the clock signal DP 1  via capacitor C 2 . 
   Node N 3  connects the gate of pre-charge transistor M 8 , the drain of transistor M 6 , drain of discharge transistor M 7 , and clock signal DP 3  via capacitor C 3 . The gate of discharge capacitor M 7  is capacitor coupled to the enable signal EN via capacitor C 4 , and is coupled to ground via transistor M 13 , which is configured as a diode. 
   Node N 4  connects the gate of pass transistor M 2 , the drain of pre-charge transistor M 8 , and is capacitor coupled to clock signal DP 2  via capacitor C 5 . 
   Node N 5  connects the drain of pass transistor M 2 , the source of pass transistor M 3 , the drain of initialization transistor M 9 , the source and gate of transistor M 10 , and the clock signal DP 3  via capacitor C 6 . 
   Node  6  connects the gate of pre-charge transistor M 11 , the drain of transistor M 10 , the drain of discharge transistor M 12 , and clock signal DP 1  via capacitor C 7 . 
   The gate of discharge capacitor M 12  is capacitor coupled to the enable signal EN via capacitor C 8 , and is coupled to ground via transistor M 14 , which is configured as a diode. 
   Node N 7  connects the gate of pass transistor M 3 , the drain of pre-charge transistor M 11 , and is capacitor coupled to clock signal DP 4  via capacitor C 9 . 
   The drain of pass transistor M 3  is connected to the negative charge pump output signal VNCP, which can be, by way of example, −2 volts for a two stage negative charge pump, although other voltages can be used. 
   With reference to  FIGS. 1A-1B , and  FIGS. 2 and 3 , which illustrate example actual plots of charge pump clock and node voltages as a function to time, circuit  100  and the timing signals for clock signals DP 1 , DP 2 , DP 3 , and DP 4 , the circuit operation will now be described in greater detail. In this example, the charge pump circuit timing can be divided into 8 regions T 1  to T 8 . 
   When enable signal EN goes low, the transistors M 7  and M 12  will correspondingly discharge pre-charge transistors M 8  and M 11  to ground. 
   Then, at time period T 1 : 
   Assuming that the state of clock DP 3  is low from a prior state, the voltage at node N 5  is at negative level. When clock DP 1  transitions from a high level to a low level at T 1 , nodes N 2  and N 6  are gradually pulled or pumped down to a negative level. 
   Node N 4  discharges gradually to the voltage at node N 3  plus the threshold voltage of pre-charge transistor M 8  (VN 4 =VN 3 +VT(M 8 )), and the pre-charge transistor M 8  turns off. 
   Pre-charge transistors M 4  and M 11  turn on as a result of the negative voltage at nodes N 2  and N 6 , and pass transistors M 1  and M 3  turn off. 
   At time period T 2 : 
   Clock DP 3  transitions from low to high, and the voltages of nodes N 3  and N 5  are correspondingly boosted up. The voltage of node N 3  discharges gradually to the voltage of node N 2  plus the threshold voltage of transistor M 6  (VN 3 =VN 2 +VT(M 6 )), thereby operating as a sub-negative pump. 
   At this time, transistor pre-charge transistor M 8  is turned off, and the voltage at node N 4  will remain at the previous level (VN 4 =VN 3 +VT(M 8 )). 
   As a result of pre-charge transistor M 11  being on, the voltage at node N 7  is equal to the voltage at node N 5 , and so pass transistor M 3  is off. 
   Similarly, as a result of pre-charge transistor M 4  being on, pass transistor M 1  is off. 
   At time period T 3 : 
   Clock DP 2  transitions from high to low. 
   At this time, the voltage at N 4  is pulled or pumped down gradually to a more negative level. 
   As a result of the more negative voltage at N 4 , pass transistor M 2  turns on fully, and charge flows from node N 5  to node N 2 . 
   During time T 3 , pass transistors M 1  and M 3  remain off. 
   The voltage at node N 5  is equal to the voltage at node N 2  after charge distribution and the body effect influence is small and can be ignored. The Vt vs. Vsb can be approximated via the following formula: Vt=Vt 0 +r(√{square root over (2φf+Vsb)}−√{square root over (2φf)}), where the r≈0.6,2φf=0.65. Therefore, a Vt for Vsb=0 and for Vsb=6v, the ΔVt≈1V}. 
   At time period T 4 : 
   Clock DP 2  transitions from low to high. 
   At this time, the voltage at node N 4  is pulled up to the level at time T 2  (VN 4 =VN 3 +VT(M 8 )). Pass transistor M 2  turns off, and pass transistors M 1  and M 3  remain off. 
   At time period T 5 : 
   Clock DP 3  transitions from high to low, pulling nodes N 5  and N 3  down to the lowest voltage level. 
   At this time, pre-charge transistor M 8  will turn on, and then the voltage at node N 4  will be equal to the voltage at node N 2 . Pass transistor M 2  then turns off. The voltage at node N 6  is pulled down to the voltage at node N 5  plus the threshold voltage of transistor M 10  (VN 6 =VN 5 +VT(M 10 ). The voltage at node N 7  is pulled down to the voltage at node N 6  plus the threshold voltage of the pre-charge transistor M 11  (VN 7 =VN 6 +VT(M 11 )). 
   At time period T 6 : 
   Clock signal DP 1  transitions from low to high, boosting upwards the voltages at nodes N 2  and N 6 . Additionally, the voltage at node N 6  discharges to the voltage at node N 5  plus the threshold voltage of transistor M 10  (VN 6 =VN 5 +VT(M 10 )), thereby acting as a sub-negative pump. 
   At this time, pre-charge transistor M 4  will turn on, and N 1  is at ground. 
   Pre-charge transistor M 11  turns off, and the voltage of node N 7  remains at the same voltage level as at time T 5  (VN 6 +VT(M 11 )). Pre-charge transistor M 8  turns on, therefore pass transistor M 2  turns off. 
   At time period T 7 : 
   Clock signal DP 4  transitions from high to low. 
   At this time, nodes N 1  and N 7  are pulled down to a more negative level, and pass transistors M 1  and M 3  fully turn on. Because the voltage at node N 4  is equal to the voltage of node N 2 , transistor M 2  is turned off. After charge sharing, the node N 2  voltage is equal to ground, and the voltage of node VNCP is equal to the voltage of node N 5 . The influence of body effect is not significant, as similarly described above. 
   At time period T 8 : 
   Clock signal DP 4  transitions from low to high. At this time, nodes N 1  and N 7  are pulled up to about the same voltage level at time period T 6 . Pre-charge transistor M 8  turns on, and pass transistor M 2  remains off. 
   In one embodiment, the circuit is implemented using a small layout in a single N-well, although other embodiments can be implemented in multiple wells or otherwise. For example, in an NMOS charge pump, which needs to separate the well of the transistor, the size is approximate twice that of a PMOS charge pump, which can use single well. 
   It should be understood that certain variations and modifications of this invention would suggest themselves to one of ordinary skill in the art. The scope of the present invention is not to be limited by the illustrations or the foregoing descriptions thereof.