Abstract:
A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. provisional patent application No. 62/174,573, filed Jun. 12, 2015, and is a continuation-in-part of U.S. patent application Ser. No. 14/273,316, filed May 8, 2014, the disclosures of which are incorporated herein by reference in their entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure relates to varactors, and in particular to varactor diodes. 
       BACKGROUND 
       [0003]    A varactor is an electronic component with a capacitance that changes in response to an applied bias voltage. While there are many different types of varactors, an exemplary varactor diode  10  is shown in  FIGS. 1A and 1B . The exemplary varactor diode  10  is operated by coupling the varactor diode  10  between a bias voltage V BIAS  and ground. Specifically, the varactor diode  10  is coupled such that a cathode of the varactor diode  10  is coupled to the bias voltage V BIAS  while an anode of the varactor diode  10  is coupled to ground. An input node  12 A may be coupled to the cathode of the varactor diode  10 , while an output node  12 B may be coupled to the anode of the varactor diode  10 . As the bias voltage V BIAS  is changed, a capacitance C D  between the input node  12 A and the output node  12 B also changes. This is due to the fact that the bias voltage V BIAS , which is a reverse-bias voltage, controls a width W DR  of a depletion region within a P-N junction of the varactor diode  10 , as shown in  FIG. 1B . Specifically, the bias voltage V BIAS  is directly proportional to the width W DR  of the depletion region, such that as the bias voltage V BIAS  increases, the width W DR  of the depletion region also increases, and vice-versa. The width W DR  of the depletion region is in turn inversely proportional to the capacitance C D  across the varactor diode  10 , such that as the width W DR  of the depletion region increases, the capacitance C D  across the varactor diode  10  decreases. Accordingly, the bias voltage V BIAS  is able to control the capacitance C D  across the varactor diode  10 . 
         [0004]    Varactors are used in a variety of different applications. For example, many varactors are currently used in radio frequency (RF) circuitry such as RF front-end circuitry. In such applications, a time-varying RF signal is generally applied across the varactor diode  10 . The RF signal may modulate the capacitance C D  of the varactor diode  10  due to the same mechanism of action described above with respect to the bias voltage V BIAS , which may be undesirable in many situations. In order to counteract this modulation effect, multiple varactor diodes  10  may be coupled in series between the input node  12 A and the output node  12 B, as shown in  FIG. 2 . Specifically,  FIG. 2  shows a number of varactor diodes  10 A- 10 H coupled in an alternating-polarity configuration such that a cathode of a first varactor diode  10 A is coupled to the input node  12 A, an anode of the first varactor diode  10 A is coupled to an anode of a second varactor diode  10 B, a cathode of the second varactor diode  10 B is coupled to a cathode of a third varactor diode  10 C, an anode of the third varactor diode  10 C is coupled to an anode of a fourth varactor diode  10 D, a cathode of the fourth varactor diode  10 D is coupled to a cathode of a fifth varactor diode  10 E, an anode of the fifth varactor diode  10 E is coupled to an anode of a sixth varactor diode  10 F, a cathode of the sixth varactor diode  10 F is coupled to a cathode of a seventh varactor diode  10 G, an anode of the seventh varactor diode  10 G is coupled to an anode of an eighth varactor diode  10 H, and a cathode of the eighth varactor diode  10 H is coupled to the output node  12 B. The bias voltage V BIAS  is coupled to the cathode of the first varactor diode  10 A via a first bias resistor R B1 , coupled to the cathode of the second varactor diode  10 B and the third varactor diode  10 C via a second bias resistor R B2 , coupled to the cathode of the fourth varactor diode  10 D and the fifth varactor diode  10 E via a third bias resistor R B3 , and coupled to the cathode of the sixth varactor diode  10 F and the seventh varactor diode  10 G via a fourth bias resistor R B4 . Further, the anode of the first varactor diode  10 A and the second varactor diode  10 B are coupled to ground via a fifth bias resistor R B5 , the anode of the third varactor diode  10 C and the fourth varactor diode  10 D are coupled to ground via a sixth bias resistor R B6 , the anode of the fifth varactor diode  10 E and the sixth varactor diode  10 F are coupled to ground via a seventh bias resistor R B7 , and the anode of the seventh varactor diode  10 G and the eighth varactor diode  10 H are coupled to ground via an eighth bias resistor R B8 . Because each one of the varactor diodes  10 A- 10 H are essentially coupled in a reverse-bias configuration between the bias voltage V BIAS  and ground, each one of the varactor diodes  10 A- 10 H will vary the capacitance C D  thereof in response to the bias voltage V BIAS  as discussed above. Further, due to the fact that the varactor diodes  10 A- 10 H are stacked in an alternating-polarity configuration, an increase in the capacitance of one of the diodes due to an RF signal placed across the varactor diodes  10 A- 10 H is counteracted by a decrease in the capacitance of a corresponding reverse-connected varactor diode such that the net effect of an applied RF signal on the overall capacitance of the varactor diodes  10 A- 10 H is minimal. 
         [0005]    Generally, it is desirable for the capacitance of a varactor diode to change as quickly as possible in response to a change in the bias voltage V BIAS . The response over time of a resistor-capacitor (RC) circuit such as a varactor to a given voltage function is described by Equation (1): 
         [0000]      τ=RC   (1)
 
         [0000]    where τ is the time constant of the circuit, R is a total resistance of the circuit as seen from the source of the voltage, and C is a total capacitance as seen from the source of the voltage. Higher values of rare associated with an increased delay between an applied voltage and a change in the capacitance of the circuit. Accordingly, the larger the time constant associated with a varactor diode, the longer the time delay associated with a change in the bias voltage VBIAS and a corresponding change in the capacitance of the varactor diode. 
         [0006]    In order to reduce the propagation of RF signals towards the bias voltage V BIAS  and ground in the circuitry shown in  FIG. 2 , the bias resistors R B1 -R B8  must generally be kept quite large, on the order of 20 kΩ and larger. Further, due to the fact that each one of the varactor diodes  10 A- 10 H are essentially coupled in parallel between the bias voltage V BIAS  and ground, the combined capacitance of the varactor diodes as seen by the bias voltage V BIAS  is the sum of each one of the varactor diodes  10 A- 10 H. Accordingly, the combination of the resistance and the capacitance RC seen by the bias voltage VBIAS is quite large, resulting in a large time constant τ, and thus a relatively slow response time of the varactor circuitry shown in  FIG. 2 . 
         [0007]    Accordingly,  FIG. 3  shows an alternative configuration for the varactor diodes  10 A- 10 H. Specifically,  FIG. 3  shows the varactor diodes coupled in series between the input node  12 A and the output node  12 B, such that the cathode of the first varactor diode  10 A is coupled to the input node, the anode of the eighth varactor diode  10 H is coupled to the output node  12 B, and the remaining diodes are coupled between the first varactor diode  10 A and the eighth varactor diode  10 H in an anode-to-cathode configuration as shown. The bias voltage V BIAS  is coupled to the cathode of the first varactor diode  10 A via a first biasing resistor R B1  and coupled to the anode of the eighth varactor diode  10 H via a second biasing resistor R B2 . The resistance seen from the bias voltage V BIAS  is thus significantly decreased compared to the circuitry shown in  FIG. 2 . Further, because the varactor diodes  10 A- 10 C are coupled in series, the effective value thereof is calculated as shown in Equation (2): 
         [0000]    
       
         
           
             
               
                 
                   1 
                   
                     
                       1 
                       
                         C 
                         1 
                       
                     
                     + 
                     
                       1 
                       
                         C 
                         2 
                       
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           3 
                         
                       
                        
                       … 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0008]    Accordingly, both the resistance and the capacitance RC associated with the circuitry shown in  FIG. 3  is significantly reduced compared to that shown in  FIG. 2 , which results in significant reductions in the time constant τ thereof. Such a performance increase in the response time of the varactor diode circuitry shown in  FIG. 3  comes at the expense of the ability of the circuitry to cancel the effects of RF signal modulation as in the alternating-polarity circuitry discussed above with respect to  FIG. 2 . 
         [0009]    Conventionally, varactor diode structures such as those described above with respect to  FIGS. 2 and 3  have been made by placing a number of co-planar varactor diodes  10 A- 10 H next to one other on a substrate, as shown in  FIG. 4 . Each one of the diodes consumes area on the substrate, and thus the area required for the diodes may become quite large for circuitry requiring multiple stacked varactor diodes such as that shown in  FIGS. 2 and 3 . While a dual-stack varactor for alternating-polarity applications such as that shown in  FIG. 2  has been described in co-pending and co-assigned U.S. patent application Ser. No. 14/273,316, the contents of which are hereby incorporated by reference in their entirety, series-coupled varactor diodes such as those shown in  FIG. 2  have thus far been limited to single-stack solutions, resulting in the consumption of a relatively large area on a substrate. 
         [0010]    Accordingly, there is a need for stacked varactor circuitry for series-connected varactor diodes with a reduced area. 
       SUMMARY 
       [0011]    The present disclosure relates to varactors, and in particular to varactor diodes. In one embodiment, a semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced. 
         [0012]    In one embodiment, the first varactor diode includes a first cathode contact layer, a first cathode layer over the first cathode contact layer, a first varactor layer over the first cathode layer, and a first anode contact layer over the first varactor layer. Further, the first varactor diode may include a cathode contact on the first cathode contact layer and an anode contact on the first anode contact layer. 
         [0013]    The second varactor diode may include a second cathode contact layer over the first anode contact layer, a second cathode layer over the second cathode contact layer, a second varactor layer over the second cathode layer, and a second anode contact layer over the varactor layer. Further, the second varactor diode may include a cathode contact on the second cathode contact layer and an anode contact on the second anode contact layer. 
         [0014]    A first etch stop layer may be between the first cathode contact layer and the first cathode layer. A second etch stop layer may be between the first anode contact layer and the second cathode contact layer. A third etch stop layer may be between the second cathode contact layer and the second cathode layer. 
         [0015]    In one embodiment, the first varactor diode includes a first anode contact layer, a first anode layer over the first anode contact layer, a first varactor layer over the first anode layer, and a first cathode contact layer over the first varactor layer. Further, the first varactor diode may include an anode contact on the first anode contact layer and a cathode contact on the first cathode contact layer. 
         [0016]    The second varactor diode may include a second anode contact layer over the first cathode contact layer, a second anode layer over the second anode contact layer, a second varactor layer over the second anode layer, and a second cathode contact layer over the second varactor layer. Further, the second varactor diode may include an anode contact on the second anode contact layer and a cathode contact on the second cathode contact layer. 
         [0017]    A first etch stop layer may be between the first anode contact layer and the first anode layer. A second etch stop layer may be between the first cathode contact layer and the second anode contact layer. A third etch stop layer may be between the second anode contact layer and the second anode layer. 
         [0018]    Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
           [0020]      FIGS. 1A and 1B  show a single varactor diode. 
           [0021]      FIG. 2  shows a number of varactor diodes stacked in an alternating-polarity configuration. 
           [0022]      FIG. 3  shows a number of varactor diodes connected in series. 
           [0023]      FIG. 4  shows the physical layout of a number of varactor diodes coupled in series. 
           [0024]      FIG. 5  shows a dual-stack varactor according to one embodiment of the present disclosure. 
           [0025]      FIG. 6  shows a dual-stack varactor according to an additional embodiment of the present disclosure. 
           [0026]      FIG. 7  is a flow diagram illustrating a method for manufacturing an epitaxial stack for a dual-stack varactor according to one embodiment of the present disclosure. 
           [0027]      FIG. 8  is a flow diagram illustrating a method for manufacturing a dual-stack varactor from an epitaxial stack as shown in  FIG. 7  according to one embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0029]      FIG. 5  shows a dual-stack varactor  14  according to one embodiment of the present disclosure. The dual-stack varactor  14  includes a first cathode contact layer  16 , a first etch stop layer  18  over the first cathode contact layer  16 , a first cathode layer  20  over the first etch stop layer  18 , a first varactor layer  22  over the first cathode layer  20 , a first anode contact layer  24  over the first varactor layer  22 , a second etch stop layer  26  over the first anode contact layer  24 , a second cathode contact layer  28  over the second etch stop layer  26 , a third etch stop layer  30  over the second cathode contact layer  28 , a second cathode layer  32  over the third etch stop layer  30 , a second varactor layer  34  over the second cathode layer  32 , and a second anode contact layer  36  over the second varactor layer  34 . 
         [0030]    The dual-stack varactor  14  is formed as a number of different mesas in order to allow contacts to be placed on the various layers therein. The first cathode contact layer  16  forms a first mesa  38  on top of which a first ohmic contact  40 , which may be separated into a pair of ohmic contacts, is located. The first ohmic contact(s)  40  effectively forms a cathode contact of a first varactor diode in the dual-stack varactor  14 . The first etch stop layer  18 , the first cathode layer  20 , the first varactor layer  22 , and the first anode contact layer  24  form a second mesa  42  on top of which a second ohmic contact  44 , which may be separated into a pair of ohmic contacts, is located. The second ohmic contact(s)  44  effectively form an anode contact of the first varactor diode in the dual-stack varactor  14 . The second etch stop layer  26  and the second cathode contact layer  28  form a third mesa  46  on top of which a third ohmic contact  48 , which may be separated into a pair of ohmic contacts, is located. The third ohmic contact(s)  48  effectively form a cathode contact of a second varactor diode in the dual-stack varactor  14 . Finally, the third etch stop layer  30 , the second cathode layer  32 , the second varactor layer  34 , and the second anode contact layer  36  form a fourth mesa  50  on top of which a fourth ohmic contact  52  is located. The fourth ohmic contact  52  effectively forms an anode contact of the second varactor diode in the dual-stack varactor  14 . A metallization layer  54  connects the second ohmic contact(s)  44  to the third ohmic contact(s)  48 . Accordingly, a pair of series-connected varactor diodes are formed between the first ohmic contact(s)  40  and the fourth ohmic contact  52 . 
         [0031]    Due to the fact that two varactor diodes  10  are vertically disposed in the dual-stack varactor  14  with a footprint that is comparable to a single-stack varactor, the number of varactor diodes per unit area can effectively be doubled when using the dual-stack varactor  14 . Accordingly, significant reductions in the size of circuitry such as that shown in  FIGS. 2 and 3  can be achieved. Such size reductions may result in similar reductions in the cost of the circuitry. 
         [0032]    In one embodiment, the first cathode contact layer  16  is a heavily doped p-layer with a thickness between about 0.4 μm and 2.0 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The first etch stop layer  18  may be a heavily doped p-layer with a thickness between about 0.005 μm and 0.03 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The first cathode layer  20  may be a heavily doped p-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The first varactor layer  22  may be a lightly doped n-layer with a thickness between about 0.5 μm and 2.0 μm and a doping concentration between about 1×10 15  cm −3  and 1×10 17  cm −3 . The first anode contact layer  24  may be a heavily doped n-layer with a thickness between about 0.1 μm and 0.5 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The second etch stop layer  26  may be a n+ layer with a thickness between about 0.005 μm and 0.03 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The second cathode contact layer  28  may be a heavily-doped p-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The third etch stop layer  30  may be a heavily-doped p-layer with a thickness between about 0.005 μm and 0.03 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The second cathode layer  32  may be a heavily doped p-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The second varactor layer  34  may be a lightly-doped n-layer with a thickness between about 0.5 μm and 2.0 μm and a doping concentration between about 1×10 15  cm −3  and 1×10 17  cm −3 . The second anode contact layer  36  may be a heavily-doped n-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The n-dopants used in the n-layers described above may include silicon (Si), tellurium (Te), or the like. The p-dopants used in the p-layers described above may include carbon (C), beryllium (Be), zinc (Zn), or the like. Notably, the foregoing thicknesses and doping concentration for the various layers in the dual-stack varactor  14  are merely illustrative. Any number of suitable thicknesses or doping concentrations may be used for the layers in the dual-stack varactor  14  without departing from the principles of the present disclosure. 
         [0033]    In one embodiment, the first cathode contact layer  16 , the first cathode layer  20 , the varactor layer  22 , the first anode contact layer  24 , the second cathode contact layer  28 , the second cathode layer  32 , the second varactor layer  34 , and the second anode contact layer  36  are all gallium arsenide (GaAs). The first etch stop layer  18 , the second etch stop layer  26 , and the third etch stop layer  30  may be aluminum gallium arsenide (AlGaAs) or indium gallium arsenide (InGaAs). The first ohmic contact(s)  40  may comprise titanium-platinum-gold (TiPtAu). The second ohmic contact(s)  44  may comprise gold-germanium-nickel-gold (AuGeNiAu). The third ohmic contact(s)  48  may comprise titanium-plantium-gold (TiPtAu). The fourth ohmic contact  52  may comprise titanium-tungsten (TiW). Finally, the metallization layer  54  may comprise titanium/gold (Ti/Au). Notably, the foregoing materials for the dual-stack varactor  14  are merely illustrative, and any number of different materials may be used for the various layers without departing from the principles of the present disclosure. 
         [0034]      FIG. 6  shows a dual-stack varactor  56  according to an additional embodiment of the present disclosure. The dual-stack varactor  56  shown in  FIG. 6  is substantially similar to that shown in  FIG. 5 , except that the varactor diodes in the dual-stack varactor  56  are reversed. Accordingly, the dual-stack varactor  56  includes a first anode contact layer  58 , a first etch stop layer  60  over the first anode contact layer  58 , a first anode layer  62 , a first varactor layer  64  over the first anode layer  62 , a first cathode contact layer  66  over the first varactor layer  64 , a second etch stop layer  68  over the first cathode contact layer  66 , a second anode contact layer  70  over the second etch stop layer  68 , a third etch stop layer  72  over the second anode contact layer  70 , a second anode layer  74  over the third etch stop layer  72 , a second varactor layer  76  over the second anode layer  74 , and a second cathode contact layer  78  over the second varactor layer  76 . 
         [0035]    The dual-stack varactor  56  is formed as a number of different mesas in order to allow contacts to be placed on the various layers therein. The first anode contact layer  58  forms a first mesa  80  on top of which a first ohmic contact  82 , which may be separated into a pair of ohmic contacts, is located. The first ohmic contact(s)  82  effectively forms an anode contact of a first varactor diode in the dual-stack varactor  56 . The first etch stop layer  60 , the first anode layer  62 , the first varactor layer  64 , and the first cathode contact layer  66  form a second mesa  84  on top of which a second ohmic contact  86 , which may be separated into a pair of ohmic contacts, is located. The second ohmic contact(s)  86  effectively forms a cathode contact of the first varactor diode. The second etch stop layer  68  and the second anode contact layer  70  form a third mesa  88  on top of which a third ohmic contact  90 , which may be separated into a pair of ohmic contacts, is located. The third ohmic contact(s)  90  effectively forms an anode contact of a second varactor diode in the dual-stack varactor  56 . The third etch stop layer  72 , the second anode layer  74 , the second varactor layer  76 , and the second cathode contact layer  78  form a fourth mesa  92  on top of which a fourth ohmic contact  94  is located. The fourth ohmic contact  94  effectively forms a cathode contact of the second varactor diode. A metallization layer  96  connects the second ohmic contact(s)  86  to the third ohmic contact(s)  90 . Accordingly, a pair of series-connected varactor diodes are formed between the first ohmic contact(s)  82  and the fourth ohmic contact  94 . 
         [0036]    Due to the fact that two varactor diodes are vertically disposed in the dual-stack varactor  56  with a footprint that is comparable to a single-stack varactor, the number of varactor diodes per unit area can effectively be doubled when using the dual-stack varactor  56 . Accordingly, significant reductions in the size of circuitry such as that shown in  FIGS. 2 and 3  can be achieved. Such size reductions may result in similar reductions in the cost of the circuitry. 
         [0037]    In one embodiment, the first anode contact layer  58  is a heavily doped n-layer with a thickness between about 0.4 μm and 2.0 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The first etch stop layer  60  may be a heavily doped n-layer with a thickness between about 0.005 μm and 0.03 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The first anode layer  62  may be a heavily doped n-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The first varactor layer  64  may be a lightly doped n-layer with a thickness between about 0.5 μm and 2.0 μm and a doping concentration between about 1×10 15  cm −3  and 1×10 17  cm −3 . The first cathode contact layer  66  may be a heavily doped p-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The second etch stop layer  68  may be a p+ layer with a thickness between about 0.005 μm and 0.03 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . The second anode contact layer  70  may be a heavily doped n-layer with a thickness between about 0.05 μm and 0.5 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The third etch stop layer  72  may be a heavily doped n-layer with a thickness between about 0.005 μm and 0.03 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The second anode layer  74  may be a heavily doped n-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 18  cm −3  and 5×10 18  cm −3 . The second varactor layer  76  may be a lightly doped n-layer with a thickness between about 0.5 μm and 2.0 μm and a doping concentration between about 1×10 15  cm −3  and 1×10 17  cm −3 . Finally, the second cathode contact layer  78  may be a heavily doped p-layer with a thickness between about 0.05 μm and 0.2 μm and a doping concentration between about 1×10 19  cm −3  and 4×10 19  cm −3 . Notably, the foregoing thicknesses and doping concentrations for the various layers in the dual stack varactor  56  are merely illustrative. Any number of suitable thicknesses or doping concentrations may be used for the layers in the dual-stack varactor  56  without departing from the principles of the present disclosure. 
         [0038]    In one embodiment, the first anode contact layer  58 , the first anode layer  62 , the first varactor layer  64 , the first cathode contact layer  66 , the second anode contact layer  70 , the second anode layer  74 , the second varactor layer  76 , and the second cathode contact layer comprise gallium arsenide (GaAs). The first etch stop layer  60 , the second etch stop layer  68 , and the third etch stop layer  72  may be aluminum gallium arsenide (AlGaAs) or indium gallium arsenide (InGaAs). The first ohmic contact(s)  82  may comprise gold-germanium-nickel-gold (AuGeNiAu). The second ohmic contact(s)  86  may comprise titanium-platinum-gold (TiPtAu). The third ohmic contact(s)  90  may comprise gold-germanium-nickel-gold (AuGeNiAu). The fourth ohmic contact  94  may comprise titanium-tungsten (TiW). Notably, the foregoing materials for the dual-stack varactor  56  are merely illustrative, and any number of different materials may be used for the various layers without departing from the principles of the present disclosure. 
         [0039]    While  FIGS. 5 and 6  illustrate only two varactor diodes vertically stacked with respect to one another, the principles of the present disclosure may be used to stack any number of varactor diodes on top of one another. 
         [0040]      FIG. 7  is a flow diagram illustrating a method for manufacturing the epitaxial stack making up the dual-stack varactor  14  shown in  FIG. 5 . The epitaxial stack of the dual stack varactor  56  shown in  FIG. 6  may be made by a similar process. First, the first anode contact layer  16  is provided (step  100 ). The first etch stop layer  18  is provided over the first anode contact layer  16  (step  102 ). The first cathode layer  20  is provided over the first etch stop layer  18  (step  104 ). The first varactor layer  22  is provided over the first cathode layer  20  (step  106 ). The first anode contact layer  24  is provided over the first varactor layer  22  (step  108 ). The second etch stop layer  26  is provided over the first anode contact layer  24  (step  110 ). The second cathode contact layer  28  is provided over the second etch stop layer  26  (step  112 ). The third etch stop layer  30  is provided over the second cathode contact layer  28  (step  114 ). The second cathode layer  32  is provided over the third etch stop layer  30  (step  116 ). The second varactor layer  34  is provided over the second cathode layer  32  (step  118 ). The second anode contact layer  36  is provided over the second varactor layer (step  120 ). Any suitable epitaxial growth or deposition process may be used to provide the layers as described above without departing from the principles of the present disclosure. 
         [0041]      FIG. 8  is a flow diagram illustrating a method for constructing the dual-stack varactor  14  discussed above with respect to  FIG. 5  from the epitaxial stack described above with respect to  FIG. 7 . A similar process may be used to construct the dual-stack varactor  56  shown in  FIG. 6 . First, the fourth ohmic contact  52  is provided on the second anode contact layer  36  (step  200 ). The fourth ohmic contact  52 , the second anode contact layer  36 , the second varactor layer  34 , and the second cathode layer  32  are then selectively etched using any number of masking and etching processes (step  202 ). Notably, the material of the third etch stop layer  30  is not compatible with the etching process used in step  202 , and therefore the etching process does not affect the third etch stop layer  30 . Accordingly, a separate etch process using a different etch process and/or chemistry is then used to selectively etch away the third etch stop layer  30  to form the fourth mesa  50  (step  204 ). Notably, the material of the second cathode contact layer  28  is not compatible with the etching process used in step  204 , and therefore the etching process does not affect the second cathode contact layer  28 . Accordingly, a separate etch process using a different etch process and/or chemistry is then used to selectively etch away the second cathode contact layer  28  (step  206 ). As discussed above, the second etch stop layer  26  is not affected by the etch process in step  206 , and thus a separate etching process is used to selectively etch the second etch stop layer  26  to form the second mesa  46  (step  208 ). The first anode contact layer  24 , the first varactor layer  22 , and the first cathode layer  20  are then selectively etched (step  210 ). A separate etching process is then used to selectively etch the first etch stop layer  18  to form the first mesa  38  and the second mesa  42  (step  212 ). The first ohmic contact(s)  40 , the second ohmic contact(s)  42 , and the third ohmic contact(s) are then provided (step  214 ). Finally, the metallization layer  54  is provided (step  216 ). As will be appreciated by those of ordinary skill in the art, any number of masking and etching processes may be used to form the dual-stack varactor  14 . All of these processes are contemplated herein. 
         [0042]    Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.