Abstract:
A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.

Description:
[0001]     The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0102125 (filed on Oct. 28, 2005), which is hereby incorporated by reference in its entirety.  
       BACKGROUND  
       [0002]     A biCMOS device may have high speed, low power consumption, and high integration. A biCMOS device is a device (e.g. a chip) that includes both a bipolar transistor and a CMOS transistor. A biCMOS device may have low-power consumption characteristics and high-integration characteristics of CMOS transistors and high-speed switching characteristics and a high-current driving capabilities of bipolar transistors.  
         [0003]     There is a variety of bipolar transistor manufacturing methods suitable for the biCMOS technology. These methods may be optimized to be compatible with CMOS transistor manufacturing methods, while maintaining high-speed switching characteristics and high-current driving capabilities. It may be desirable to integrate a Polysilicon/Insulator/Polysilicon (PIP) capacitor on a biCMOS device adjacent to a bipolar transistor. Integrating both a bipolar transistor and a PIP capacitor on a biCMOS device may be accomplished by a high-integration technique.  
         [0004]     Example  FIGS. 1A  to  1 D are cross-sectional views illustrating a method of manufacturing a biCMOS device having a bipolar transistor and a PIP capacitor. As illustrated in  FIG. 1A , P-type semiconductor substrate  10  may include PIP capacitor region A and bipolar transistor region B. Semiconductor substrate  10  may include buried layer  12  (e.g. doped with an N-type material) formed in bipolar transistor region B. An epitaxial layer (not shown) may be formed on buried layer  12 . First well region  14   a  (e.g. doped with N-type material) and second well region  14   b  (e.g. doped with P-type material) may be formed adjacent to each other within a epitaxial layer (not shown).  
         [0005]     Field insulating layer  16  may be formed over surfaces of PIP capacitor region A and bipolar transistor region B. First polysilicon layer  18  may be formed over field insulating layer  16 . A photoresist layer (not shown) may be formed over first polysilicon layer  18 . Mask pattern  19  (e.g. for ion implantation) may be formed from a photoresist layer.  
         [0006]     As illustrated in  FIG. 1B , an ion implantation process using the mask pattern  19  may be performed by implanting ions into exposed areas of first polysilicon layer  18  to form doped first polysilicon layer  18   a.  As illustrated in  FIG. 1C , mask pattern  19  may be stripped. First polysilicon layer  18  may be patterned so that only doped first polysilicon layer  18 a remains. First polysilicon layer  18   a  may become a lower electrode of a PIP capacitor. Capacitor dielectric layer  20  and upper electrode  22  may be sequentially formed on doped first polysilicon layer  18   a.    
         [0007]     As illustrated in  FIG. 1D , collector region  28  may be formed by doping a region of first well region  14   a  with N-type material. Emitter region  26  may be formed by doping a region of second well region  14   b  with N-type material. Base region  24  may be formed by doping a region of second well region  14   b  with P-type material. Base region  24  and emitter region  26  may be isolated from each other. Buried layer  12  and first well region  14   a  may work with collector region  28  in a bipolar transistor. Second well region  14   b  may work with base region  24 .  
         [0008]     A biCMOS device (e.g. a chip including a CMOS transistor and a bipolar transistor) may include the structure illustrated in  FIGS. 1A through 1D . The concentration of N-type material in first well region  14   a  may be relatively low compared to a device that does not integrate CMOS transistors with bipolar transistors. Accordingly, it may be difficult to form a bipolar transistor having an adequate high amplification rate if the series resistance of collector region  28  is relatively high.  
       SUMMARY  
       [0009]     Embodiments relate to a biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor. In embodiments, a biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate, according to embodiments.  
         [0010]     In embodiments, a biCMOS device may include at least one of a semiconductor substrate, a first well region, a second well region, a doping region, and a bipolar transistor. A semiconductor substrate may be of a second conductive type. A first well region may be doped with a second conductive type material. A first well region may be formed in a predetermined region within a semiconductor substrate. A second well region may be doped with a first conductive type material. A second well region may be adjacent to the first well region. A doping region may be doped with the same conductive type as a first well region. A doping region may be formed within the first well region. A bipolar transistor may include an emitter region doped with a second conductive type material on a surface of a semiconductor substrate within the doping region.  
         [0011]     Embodiments relate to a method of manufacturing a biCMOS device, including at least one of forming a first well region, forming a field insulating layer, depositing a first polysilicon layer, implanting ions, stripping a mask pattern, and forming a collector region. A first well region may be doped with a second conductive type. A second well region may be doped with a first conductive type. A field insulating layer may be formed on a surface of a semiconductor substrate between a first well region and a second well region. A first polysilicon layer may be formed on a field insulating layer. A mask pattern may be formed for ion implantation on a first polysilicon layer. Ions may be implanted of a first conductive type through a mask pattern. A doping region may be formed in a first well region of a bipolar transistor region while doping a first polysilicon layer of a PIP capacitor region. A mask pattern may be stripped for ion implantation. A collector region doped with a first conductive type may be formed on a surface of a semiconductor substrate within a doping region. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     Example  FIGS. 1A  to  1 D are cross-sectional views illustrating a method of manufacturing a biCMOS device.  
         [0013]     Example  FIG. 2  is a cross-sectional view of a biCMOS device, according to embodiments.  
         [0014]     Example  FIGS. 3A  to  3 D are cross-sectional views illustrating a method of manufacturing a biCMOS device, according to embodiments. 
     
    
     DETAILED DESCRIPTION  
       [0015]     Example  FIG. 2  is a cross-sectional view of a biCMOS device having a PIP capacitor and a bipolar transistor, according to embodiments.  FIGS. 3A  to  3 D are cross-sectional views illustrating a method of manufacturing a biCMOS device having a PIP capacitor and a bipolar transistor, according to embodiments. A biCMOS device may include a bipolar transistor and a PIP capacitor, in accordance with embodiments.  
         [0016]     As illustrated in  FIG. 2 , a bipolar transistor may include buried layer  32  doped with a second conductive type material (e.g. N-type material) on semiconductor substrate  30 . Semiconductor substrate  30  may be implanted with a first conductive type material (e.g. P-type material). An epitaxial layer (not shown) may be formed over buried layer  32 .  
         [0017]     First well region  34   a  (e.g. which may be doped with a second conductive type material) may be formed within an epitaxial layer (not shown). Second well region  34   b  (e.g. which may be doped with a first conductive type material) may be formed adjacent to first well region  34   a.    
         [0018]     In embodiments, doping region  40  may be formed within first well region  34   a . Doping region  40  may be doped with a second conductive type material. Collector region  46  of a bipolar transistor may be formed on a surface of a semiconductor substrate in which doping region  40  is formed. In embodiments, series resistance of collector region  46  may be reduced by doping region  40 . Accordingly, in embodiments, a bipolar transistor having a relatively high amplification rate can realized through use of doping region  40 .  
         [0019]     Emitter region  48  (e.g. which may be doped with a second conductive type material) may be formed on a surface of a semiconductor substrate in second well region  34   b . Base region  49  (e.g. which may be doped with a first conductive type material) may be formed in second well region  34   b . Base region  49  may be separated from emitter region  48 . Field insulating layer  36  may be formed on a surface of a semiconductor substrate between first well region  34   a  and second well region  34   b.    
         [0020]     As illustrated in  FIG. 2 , a PIP capacitor may include field insulating layer  36  formed over semiconductor substrate  30 . Lower electrode  38   a  (e.g. which may be doped with a second conductive type material), dielectric layer  42 , and upper electrode  44  may be sequentially formed over field insulating layer  36 .  
         [0021]     As illustrated in  FIG. 3A , semiconductor substrate  30  may be implanted with a first conductive type material (e.g. a P-type material), in accordance with embodiments. Semiconductor substrate  30  may include a PIP capacitor in region A and a bipolar transistor in region B. Buried layer  32  may be doped with a second conductive type material (e.g. a N-type material). Buried layer  32  may be formed within bipolar transistor region B. An epitaxial layer (not shown) may be formed over buried layer  32 . First well region  34   a  may be doped with a second conductive type material. Second well region  34   b  may be doped with a first conductive type material. First well region  34   a  and second well region  34   b  may be adjacent to each other and formed within an epitaxial layer (not shown). Field insulating layer  36  may be formed over semiconductor substrate  30 .  
         [0022]     First polysilicon layer  38  may be formed over field insulating layer  36 . A photoresist layer (not shown) may be formed over first polysilicon layer  38 . An exposure and development process may be performed to form mask pattern  39 . Mask pattern  39  may be used for ion implantation.  
         [0023]     Mask pattern  39  may be formed in order to expose a predetermined portion (e.g. a region D in which a collector region of a bipolar transistor will be formed) of first well region  34   a . Mask pattern may be formed in order to expose region C of first polysilicon layer. To expose region D of first well region  34   a , first polysilicon layer  38  below mask layer  39  may be stripped.  
         [0024]     As illustrated in  FIG. 3B , an ion implantation process using mask pattern  39  may be performed. First well region  34   a  may be doped to form doped region  40 . First polysilicon layer  38  may be doped to form doped first polysilicon layer  38   a . Doped first polysilicon layer  38   a  and doped region  40  may be doped at the same time.  
         [0025]     As illustrated in  FIG. 3C , mask pattern  39  may be stripped. A photoresist layer coating, exposure, and development processes may be performed on doped first polysilicon layer  38   a  to form an etch-stop mask pattern (not shown). An etch process may be performed using an etch-stop mask pattern (not shown). An undoped region of first polysilicon layer  38  may be stripped with only doped first polysilicon layer  38   a  remaining. Doped first polysilicon layer  38   a  may become a lower electrode of a PIP capacitor. An etch-stop mask pattern (not shown) may then be stripped. A dielectric layer and a second polysilicon layer may be sequentially formed and patterned over doped first polysilicon layer  38   a  to form capacitor dielectric layer  42  and upper electrode  44 .  
         [0026]     As illustrated in  FIG. 3D , collector region  46  doped with a second conductive type material (e.g. N-type material) may be formed in doped region  40  of first well region  34   a . Emitter region  48  may be doped with a second conductive type material (e.g. N-type material). Base region  49  may be doped with first conductive type material (e.g. P-type material). Emitter region  48  may be isolated from base region  49  in second well region  34   b.    
         [0027]     In embodiments, doped region  40  may be formed in first well region  34   a  to increase the concentration of second conductive type material in first well region  34   a . Doped region  40  can work with collector region  46  during the operation of a bipolar transistor, in accordance with embodiments. In embodiments, a bipolar transistor may have a high amplification rate due to a relatively low series resistance in a collector region.  
         [0028]     P-type material may be either first conductive type material or second conductive type material. N-type material may be either first conductive type material or second conductive type material.  
         [0029]     It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims.