Abstract:
One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Description:
BACKGROUND OF THE INVENTION 
     The present application claims the benefit of and priority to a pending provisional application entitled “Metal Clip for Efficient, Low Cost Package with Improved Current Carrying Capability and Reduced Form Factor and with Application in Buck Converters,” Ser. No. 61/460,553 filed on Jan. 3, 2011. The disclosure in that pending provisional application is hereby incorporated fully by reference into the present application. Additionally, pending applications Ser. No. 11/986,848, filed on Nov. 27, 2007, titled “Synchronous DC/DC Converter,” and Ser. No. 12/928,102, filed on Dec. 3, 2010, titled “DC/DC Converter with Depletion-Mode III-Nitride Switches,” are also incorporated fully by reference into the present application. 
    
    
     DEFINITION 
     In the present application, “III-nitride” (or “III-Nitride”) refers to a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like. 
     1. Field of the Invention 
     The present invention relates generally to semiconductor devices. More particularly, the present invention relates to packaging of semiconductor devices. 
     2. Background Art 
     For optimization of form factor, performance, and manufacturing cost, it is often desirable to integrate the components of a power circuit, such as a half-bridge based DC-DC converter or buck converter, into a single compact package. Thus, several package designs, including quad flat no leads (QFN) packages, have been developed to integrate several transistors within a single compact package. To provide sufficient electrical performance for the reliable operation of high power semiconductor packages, it is crucial to ensure high current carrying capacity and low resistance between transistors within the package. 
     Unfortunately, conventional high power semiconductor package designs use wirebonds for transistor interconnections, undesirably increasing electrical resistance while reducing current carrying capacity. Additionally, by following conventional package design rules to successfully accommodate such wirebonds, package form factor and complexity may undesirably increase. For example, package height may be increased to provide sufficient wirebond loop height, lateral package size may be increased to avoid wire crossing and the potential for wire shorting, and additional area on the package may be reserved for bond pad connections, thereby undesirably reducing package power density. Additionally, the increased package complexity resulting from the wirebonds may negatively affect manufacturing time, cost, and package yields. 
     Thus, a unique and cost-effective solution is needed to support the efficient design and operation of high power semiconductor packages integrating multiple transistors, such as buck converters. 
     SUMMARY OF THE INVENTION 
     A high power semiconductor package with conductive clip, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a circuit diagram of a buck converter using a half-bridge topology. 
         FIG. 1B  illustrates a top view of a conventional high power semiconductor package. 
         FIG. 2A  illustrates a top view of a high power semiconductor package with a conductive clip according to an embodiment of the invention. 
         FIG. 2B  illustrates a cross sectional view of a portion of a high power semiconductor package according to an embodiment of the invention. 
         FIG. 2C  illustrates a cross sectional view of a portion of a high power semiconductor package according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present application is directed to a high power semiconductor package with conductive clip. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art. 
     The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings. 
       FIG. 1A  illustrates a circuit diagram of a buck converter using a half-bridge topology. Diagram  100  includes switched node  115 , driver integrated circuit (IC)  120 , control transistor  140  (also referred to as a “control switch” or a “control FET”), and synchronous transistor  160  (also referred to as a “synchronous switch,” a “sync switch,” a “synchronous FET,” or a “sync FET”). The source of control transistor  140  is coupled to the drain of sync transistor  160  at switched node  115 . Driver IC  120  operates on voltage Vdr and controls the duty cycles of control transistor  140  and sync transistor  160 , thereby converting the input voltage Vin to a specific output voltage Vout. Control transistor  140  and sync transistor  160  may each comprise a conventional field effect transistor (FET) switch, for example a silicon FET. However, control transistor  140  and sync transistor  160  may each also comprise a non-silicon FET or any other FET in general. Alternatively, one or both of control transistor  140  and sync transistor  160  may also comprise a III-nitride transistor. 
     As discussed above, it may be desirable to implement the circuit of diagram  100  of  FIG. 1A  in a compact and integrated package, such as a QFN package. Accordingly, turning to  FIG. 1B ,  FIG. 1B  illustrates a top view of a conventional high power semiconductor package. Package  110  of  FIG. 1B  includes leadframe  112 , leadframe paddle  113 , wirebonds  114   a ,  114   b ,  114   c , and  114   d , driver IC  120 , control transistor  140 , and sync transistor  160 . Package  110  may comprise, for example, a QFN package. Control transistor  140  includes a top surface having a control gate  142  and a control source  144 . Control transistor  140  also includes a bottom surface having a control drain  146 , hidden from view in  FIG. 1B . Sync transistor  160  includes a top surface having a sync gate  162  and a sync source comprised of sync source pads  164   a ,  164   b ,  164   c ,  164 d, and  164   e . Sync transistor  160  also includes a bottom surface having a sync drain  166 , hidden from view in  FIG. 1B . 
     The sync source of sync transistor  160  is electrically coupled to leadframe  112  by several wirebonds connected to various sync source pads such as, for example, wirebonds  114   d  connected to sync source pad  164   c . Driver IC  120  is connected to several sections of leadframe  112  for input/output. Driver IC  120  is also electrically coupled to control gate  142  via wirebond  114   b  and sync gate  162  via wirebond  114   a . Sync drain  166  is electrically coupled to leadframe paddle  113  of leadframe  112 , and leadframe paddle  113  in turn is electrically coupled to control source  144  through wirebonds  114   c . Similarly, control drain  146  may also be disposed on leadframe paddle  113 , hidden from view in  FIG. 1B . Leadframe paddle  113  may comprise an easily solderable metal such as aluminum, or other solderable materials such as a metal alloy or a tri-metal. 
     Thus, the layout of package  110  in  FIG. 1B  connects driver IC  120 , control transistor  140 , and sync transistor  160  as shown in diagram  100  of  FIG. 1A . As previously noted, for high power semiconductor packages, it is particularly important to optimize the interconnections between transistors, such as at switched node  115  of  FIG. 1A . However, the conventional package design shown in  FIG. 1B  requires the use of wirebonds  114   c  to connect control transistor  140  and sync transistor  160  at switched node  115  of  FIG. 1A . Moreover, the current input/output path for sync source pads  164   a  through  164   e  must travel through restrictive wirebonds as well, such as wirebonds  114   d . The wirebonds of package  110  in  FIG. 1B  thus disadvantageously increase package electrical resistance, form factor, complexity, and cost. 
     Moving to  FIG. 2A ,  FIG. 2A  illustrates a top view of a high power semiconductor package with a conductive clip according to an embodiment of the invention. Package  210  in  FIG. 2A  may comprise, for example, a leadless package such as a QFN package. Package  210  includes leadframe pads  212   a ,  212   b ,  212   c ,  212   d , and  212   e , wirebonds  214   a ,  214   b , and  214   c , IC driver  220 , control transistor  240 , sync transistor  260 , and conductive clip  280 . Control transistor  240  includes a top surface having a control gate  242  and a control source  244 . Control transistor  240  also includes a bottom surface having a control drain  246 , hidden from view in  FIG. 2A . Sync transistor  260  includes a top surface having a sync drain  266 . Sync transistor  260  also includes a bottom surface having a sync gate  262  and a sync source comprised of sync source pads  264   a ,  264   b ,  264   c ,  264   d , and  264   e . Sync gate  262  and sync source pads  264   a  through  264   e  are further arranged into a grid. However, alternative embodiments may use other pad arrangements, such as an L-shaped sync source pad. Significantly, it is noted that sync transistor  260  is reversed in orientation (sync transistor  260  has drain on top, with source and gate on bottom) in relation to sync transistor  160  of  FIG. 1B  (sync transistor  160  has source and gate on top, with drain on bottom). It is noted that in various embodiments of the present invention, one or both of control transistor  240  and sync transistor  260  can be depletion mode transistors, for example, III-nitride depletion mode transistors. 
     For purposes of clarity, an encapsulating mold compound or a hermetic seal is omitted from  FIGS. 2A ,  2 B, and  2 C, but may be included in package  210 . Furthermore, with respect to  FIG. 2A , driver IC  220  may correspond to driver IC  120  from  FIG. 1A , control transistor  240  may correspond to control transistor  140  from  FIG. 1A , and sync transistor  260  may correspond to sync transistor  160  from  FIG. 1A . 
     As shown in  FIGS. 2A and 2B , conductive clip  280  electrically couples sync drain  266  and leadframe pad  212   a . In turn, leadframe pad  212   a  is electrically coupled to control source  244  through wirebonds  214   c . Thus, sync drain  266  is connected to control source  244  using the direct mechanical connection and large surface area conduction of conductive clip  280  in  FIG. 2A , in conjunction with wirebonds  214   c . Conductive clip  280  may comprise a metal such as copper, a metal alloy, or another highly conductive material, and may be attached to sync drain  266  and leadframe pad  212   a  using solder, conductive adhesive, or another attachment means. 
     Thus, package  210  of  FIG. 2A  may also implement the buck converter of  FIG. 1A , but with far greater package performance compared to package  110  of  FIG. 1B . More specifically, conductive clip  280  provides a low resistance, high current path for the connection at switched node  115  of  FIG. 1A , while the sync source, i.e. source of sync transistor  260 , is connected to ground through the low resistance, low inductance, and reliable mechanical connection provided by leadframe pad  212   b , instead of the restrictive wirebonds  114   d  of  FIG. 1B , thereby advantageously reducing package electrical resistance, form factor, complexity, and cost. 
       FIG. 2B  illustrates a cross sectional view of a portion of a high power semiconductor package according to an embodiment of the invention. The portion shown in  FIG. 2B  corresponds to the cross sectional line indicated by line  2 B- 2 B of  FIG. 2A .  FIG. 2B  includes leadframe pads  212   a ,  212   b , and  212   e , sync gate  262 , sync source pads  264   b  and  264   d , sync transistor  260 , sync drain  266 , and conductive clip  280 . While only the semiconductor device body is indicated as sync transistor  260  for simplicity, it is to be understood that sync transistor  260  may also include any top and bottom surface electrodes such as sync drain  266 , sync gate  262 , and sync source pads  264   b  and  264   d.    
     Comparing  FIG. 2B  with  FIG. 2A , it can be seen that the sync gate  262  is electrically coupled to leadframe pad  212   e , where leadframe pad  212   e  is in turn electrically coupled to IC driver  220  through wirebond  214   a . Additionally,  FIG. 2B  makes more apparent the L-shape of conductive clip  280 , which enables the electrical coupling of sync drain  266  to leadframe pad  212   a . As previously discussed, leadframe pad  212   a  may then be electrically coupled to control source  244  through wirebonds  214   c . The direct electrical and mechanical coupling of the source of sync transistor  260  to leadframe pad  212   b  is also illustrated in  FIG. 2B . Thus, more efficient current conduction is provided to and from external connections of the package, such as leadframe pad  212   b.    
     With respect to  FIG. 2C ,  FIG. 2C  illustrates a cross sectional view of a portion of a high power semiconductor package according to an embodiment of the invention. The portion shown in  FIG. 2C  corresponds to the cross sectional line indicated by line  2 C- 2 C of  FIG. 2A .  FIG. 2C  includes leadframe pads  212   b ,  212   d , and  212   e , IC driver  220 , sync gate  262 , sync source pad  264   a , sync transistor  260 , sync drain  266 , and conductive clip  280 . Comparing  FIG. 2C  with  FIG. 2A ,  FIG. 2C  makes more apparent the orientation of sync transistor  260  and the routing of leadframe pads  212   b ,  212   d , and  212   e.    
     According to the present invention, by using a direct leadframe pad connection for the sync source, and by using conductive clip  280  for the connection between the control source  244  and the sync drain  266 , a package with reduced electrical resistance, form factor, complexity, and cost may be achieved when compared to conventional packaging methods using wirebonds such as wirebonds  114   d  of  FIG. 1B . Additionally, the large surface area provided by leadframe pad  212   b , and conductive clip  280  in conjunction with leadframe pad  212   a  allows for more efficient input and output current conduction. 
     From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without depting from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skills in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. As such, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.