Abstract:
A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.

Description:
This application claims priority under 35 U.S.C. §119(e)(1) of provisional application Ser. No. 60/175,613 filed on Jan. 11, 2000, the entirety of which is incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates to the field of integrated circuit layout and design. More specifically, the present invention relates to a design process and structure for providing input/output components on an integrated circuit. 
   2. Description of the Related Art 
   The development of the technology for the fabrication and design of integrated circuits has allowed designers to place ever increasing functionality onto a smaller area of integrated circuits. This makes the surface area of an integrated circuit extremely valuable. A component of integrated circuits that occupies a relatively large area are the input/output (I/O) modules. 
   I/O Modules provide the attachment point for electrical bonding to the integrated circuit die. I/O modules generally consist of a bond pad, an electrostatic discharge protection device and I/O buffer circuitry. The core circuitry is generally composed of very small devices. These devices are fast and densely packed, but fragile. The I/O modules provide protection to the core circuitry as well as a connection point for getting signals on and off of the integrated circuit. Because they must provide this protection function, I/O modules use relatively large devices and occupy a disproportionate area on the integrated circuit die. 
   I/O modules are generally positioned on the periphery of the integrated circuit die. This makes the process of bonding to the bond pads easier and helps buffer the core circuitry from the physical stresses of cutting the die from the semiconductor wafer during manufacturing. The area occupied by the I/O modules is determined by the height (distance from the edge of the die to interior edge of the I/O modules) of the I/O modules. The remaining portion of the chip is available for core circuitry. Designers are always looking for ways to put more functionality onto an integrated circuit. Because of this, it is desirable to use the minimum area necessary for I/O modules to provide as much area as possible for the core circuitry. 
   BRIEF SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide a structure and method allowing the positioning of integrated circuit elements efficiently. 
   It is a further object of the present invention to minimize the area necessary for the I/O periphery in an integrated circuit. 
   These and other objects are provided by a described embodiment of the present invention, which includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference should be made to the following Detailed Description taken in connection with the accompanying drawings in which: 
       FIG. 1  is a layout diagram of a prior art I/O module; 
       FIG. 2  is a layout diagram of the I/O module of  FIG. 1  positioned on an integrated circuit die; 
       FIG. 3  is a layout diagram showing a plurality of prior art I/O modules positioned next to a functional core; 
       FIG. 4  is a layout diagram of an embodiment of the present invention; 
       FIG. 5  is a layout diagram another embodiment of the present invention in which a plurality of I/O modules positioned by a functional core; 
       FIG. 6  is a chart showing the die area recovered using the described embodiments of the present invention; 
       FIG. 7  is a detailed layout diagram of the embodiment of  FIG. 4 ; 
       FIG. 8  is a schematic diagram of an output circuit suitable for used with the described embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  is a layout diagram of a prior art I/O module. I/O module  10  includes a bond pad  12 , electrostatic discharge (ESD) device  14  and I/O buffer  16 . Also included in  FIG. 1  are scribe area  20  and scribe seal  22 . Scribe area  20  provides space for the saw that separates a wafer into die. Scribe seal  22  is a physical buffer area between the dice and the scribe area. Scribe seal allows for the dissipation of physical stress during the dicing process. 
   The components of I/O module  10  are laid out in the conventional manner with the bond pad and the edge of the integrated circuit die and the I/O buffer  16  positioned between the functional core  40  and bond pad  12 . I/O module  10  is an advanced module in that ESD device  14  is positioned beside bond pad  12 . 
     FIG. 2  is a layout diagram showing the position of I/O modules  10  on die  30  in I/O region  32 . Functional core  40  is surrounded by I/O region  32 . The overall size of the die  30  is determined by the width of core  40  (X) plus twice the height of the I/O modules  10  times the length of core  40  (Y) plus twice the height of the I/O modules  10 . The formula for the area is
 Area=( X+ 2 H )*( Y+ 2 H ) 
which can be written as
 Area= XY+ 2 HY+ 2 HX+ 4 H   2 . 
As can be seen from the above formula, the height of the I/O modules  10  has a large impact on the overall area of the die  30 . Although  FIG. 2  includes fourteen I/O modules  10 , it is more common for an integrated circuit to include from 64 to 300 I/O modules.  FIG. 3  is an enlarged portion of the layout of  FIG. 2  showing four I/O modules  10  and their position relative to functional core  40 .
 
     FIG. 4  is a layout diagram of a novel I/O module  100 , which is structured according to the teachings of the present invention. I/O module  100  is preferably formed on a crystalline semiconductor substrate. Bond pad  112  is positioned adjacent to scribe seal  122  as in the I/O module  10  of  FIG. 1 . Bond pad  112  is preferably formed of an aluminum composite layer, copper layer or gold clad copper layer having conductive upper surface for ball bonding. I/O buffer  116  is a similar I/O buffer circuit with a similar layout to that of I/O buffer  16 . However, because I/O buffer  116  is positioned adjacent to scribe seal  122 , the overall height Z of I/O module  100  is the height of I/O buffer  116  plus the width of scribe seal  122  and one half of scribe line  120 . 
   In contrast, the height H of prior art I/O Module is height of I/O buffer  16  plus the height of ESD device  14  plus the width of scribe seal  22  and one half of scribe line  20 . For example, the height of I/O buffer  16  may be 71μ, the height of ESD device  14  may be 21μ, the height of bond pad  12  may be 50μ and the combined height of the scribe seal  22 , scribe line  20  and additional spacing may be 46μ. This provides an overall height H of 188μ. 
   The inventive I/O module  100 , however, provides a much smaller height Z using the same design rules. With the same dimensions for components of I/O module  10 , I/O module  100  has a height of 81μ for I/O module  116  plus 46μ for scribe line  120  and scribe seal  122 . By careful layout of I/O module  116 , its height can be reduced to 74μ, thus providing an overall height Z of 120μ. 
     FIG. 5  shows I/O modules  100  as positioned adjacent to functional core  40 . Functional core  40  may be any function capable of being implemented with integrated circuitry. For example, functional core  40  may comprise an application specific integrated circuit or a digital signal processor. Preferably, the circuitry of functional core  40  is fabricated using CMOS or BiCMOS processes. Because I/O modules  100  are wider than corresponding prior art modules, fewer I/O modules  100  can be provided for a given size of functional core  40 . However, integrated circuit designs are rarely constrained by the number of I/O buffers. More often, the number of input/output connections is limited by the package. Packages that provide more that 200 connection points (for advanced ball grid arrays) can be cost prohibitive. Therefore, I/O modules  100  significantly reduce the die size for a given functionality without constraining the operational characteristics of the integrated circuit. Conversely, I/O modules  100  allow for a larger functional core for a given die size. 
     FIG. 6  is a chart comparing the die size and wasted area using the prior art I/O module. Six functional core sizes are listed. For each core size, a prior art I/O module with height H is listed and a corresponding novel module with the height Z is listed. Also listed is the total area using each module, the maximum number of I/O modules that can be placed on the die, the wasted area and the percentage of area wasted using the prior art. As can be seen from  FIG. 6 , the novel I/O module  100  reduces wasted space by 6%–13%, depending on functional core size. 
     FIG. 7  is a layout diagram showing the specific topographical features of I/O module  100 . ESD device  114  can be any number of electrostatic discharge devices. Examples of suitable devices can be found in Chen et al., U.S. Pat. No. 5,982,217, which is assigned to the assignee of this application and which is incorporated herein by reference. 
   I/O buffer  116  can be any number of known designs for providing input and output drivers. An example is shown in  FIG. 8 . I/O buffer  116  is preferably fabricated using a multi-level metal system and a device fabrication process such as that shown in Smayling et al., U.S. Pat. No. 5,767,551, which is assigned to the assignee of this application and which is hereby incorporated by reference. I/O buffer  116  is a three stage, complementary output buffer designed for high speed and to provide a well conditioned output signal. 
   The input signal on input A of I/O buffer  116  is inverted by transistor  202  and a push-pull inverter formed by transistors  204  and  206 . Transistor  208  prevents saturation of transistor  206  for high speed operation. The output from transistors  204  and  206  is inverted again by transistors  210  and  212  with a pull up (when appropriate) from transistor  214 . The drain of transistor  214  is connected to the high V DD  voltage supply (symbolized by a circle). The output from transistors  204  and  206  also drives the push-pull inverter formed by transistors  216  and  218 . The output from transistors  210  and  212  drives the gate of drive transistor  220 . The output from transistors  216  and  218  drives the gate of drive transistor  222 . The output from transistors  210  and  212  also drives the gate of pull-up transistor  224 . 
   The inverse of input A, A′ is applied to the gates of transistors  226 ,  228  and  230 . Transistors  226 ,  228 ,  230 ,  232 ,  234 ,  236 ,  238 ,  240 ,  242  and  244  provide the same functions as transistors  202 ,  204 ,  206 ,  208 ,  214 ,  210 ,  212 ,  216 ,  218 , and  224 , respectively. Additionally, transistors  245  and  248  invert and delay the output of transistors  236  and  238 . In addition, transistors  250  and  252  invert and delay the output of transistors  240  and  242 . The output of transistors  236  and  238  drives the gate of output transistor  254 . The output of transistors  250  and  252  are used to drive the gate of output transistor  256 . 
   Transistors  258 ,  260 ,  262 ,  264  and  266  constitute a pull down AND gate driving output transistor  278 . Transistors  268 ,  270 ,  272 ,  274  and  276  constitute a pull-down AND gate driving output transistor  280 . The pull-down portions of the gates are voltage limited by transistors  262  and  272  in that are gate strapped to V DD  (the lower voltage supply symbolized by a horizontal line). This prevents saturation of transistors  278  and  280 . The parallel pull-up transistors  258 ,  260 ,  268  and  270  provide rapid shut off of transistors  278  and  280 . The gate inputs of transistors  258 – 270  are timed to provide staggered gate charging or draining capacity and to avoid race conditions where all transistors in a series are on. 
   Transistors  282 – 290  provide a complementary pull-up function for output transistors  298  and  300  to the function provided by transistors  258 – 270  for output transistors  278  and  280 . In summary, transistors  220 ,  222 ,  254  and  256  provide rapid medium drive signals to begin and signal transition. Transistors  278 ,  280 ,  298  and  300  provide high capacity drive with gate drive signals that are carefully controlled. I/O buffer  116  in  FIG. 8  is an output buffer of a certain preferred structure. However, the structure of  FIG. 8  in no way limits the intended scope of the invention. The invention contemplates the use of any input or output buffer. 
   Although specific embodiments of the present invention are described herein, they are not to be construed as limiting the scope of the invention. For example, although specific circuits and device fabrication techniques are described and referred to herein, many specific devices and fabrication techniques may be advantageously used within the scope of the invention. Many embodiments of the invention will become apparent to those skilled in the art in light of the teachings of this specification. The scope of the invention is only limited by the claims appended hereto. 
   Having thus described my invention, what I claim as new and desire to secure by Letters Patent is set forth in the following claims.