Abstract:
A cross-coupled differential MOS oscillator having reduced phase noise is applicable to a RF communication device such as a transmitter or receiver. The oscillator having low phase noise is formed of a frequency dependent amplifier to amplify a signal having a fundamental frequency; a frequency dependent feedback device that is connected between an output of the frequency dependent amplifier and an input of the frequency dependent amplifier to feed a portion of an amplified signal having the fundamental frequency to an input of the frequency dependent amplifier to stimulate oscillation; and a attenuating device in communication with the frequency dependent amplifier. The attenuating device reduces the gain of the frequency dependent amplifier for signals having frequencies much, much less than the fundamental frequency to decrease the phase noise.

Description:
This application is based on a provisional patent application, 60/204885, filed on May 17, 2000. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to high frequency oscillator circuits. More particularly, this invention relates to metal oxide semiconductors (MOS) oscillators having low phase noise. 
     2. Description of the Related Art 
     Inductive/capacitive (LC) oscillators are important elements of any Radio Frequency (RF) communication devices, such as transmitters, where the LC oscillators are used as master oscillators, or as receivers where the LC oscillators are used as local oscillators. An important performance benchmark of and LC oscillator is the phase noise characteristic. An oscillator with a lower phase noise indicates that the oscillator produces lower spurious energy outside the desired fundamental signal tone. 
     Phase noise is produced as a result of low frequency noise signal found in active elements used in the oscillator. This low frequency signal is modulated (up converted) by the fundamental signal tone, resulting in the spreading of the oscillator frequency energy beyond the intended target frequency. This low frequency noise signal is often referred to as flicker noise (commonly referred to in the literature as 1/f) in bipolar and Metal Oxide Semiconductor (MOS) transistors. The 1/f noise energy in bipolar transistors is known to be significantly less than that of MOS transistors. This is the reason why practically all low phase noise LC oscillators are built using bipolar transistors or even more esoteric transistors such as Galium-Arsenide devices. 
     Complementary MOS (CMOS) based LC oscillators are now being investigated again for application to systems-on-a-chip (SOC) devices for RF communication applications. LC oscillators of the prior art fall far short of the minimum performance requirements of many of today&#39;s wireless communication systems. 
     A typical example of an LC oscillator in MOS technology is shown in FIG.  2 . It is based on cross-coupled NMOS transistors M 1  and M 2 , a pair of inductors L 1  and L 2 , and capacitor C 1  and C 2  tuning elements. PMOS transistors, which usually have slightly lower 1/f noise characteristics, can be used to replace the NMOS transistors M 1  and M 2  at a slight increase in power dissipation and lower maximum operating frequency. 
     A review of a general form of the criteria for designing an oscillator circuit of the prior art is shown in FIG.  1 . The necessary components of an oscillator are a frequency dependent gain circuit  100 , a frequency dependent feedback circuit  105 , and a combining block  110 . The output V 0    120  of the gain circuit  100  is the input to the feedback circuit  105 . The input signal V 1    115  is combined in the combining block  110  with the output V fb    107  of the feedback circuit  105  to form the input  112  of the gain circuit  100 . 
     The gain of the gain block  100  is designated (G(jω) and the gain of the feedback circuit  105  is designated H(jω). These gains G(jω) and H(jω) describe the relationship of their respective output signals V o    120  and V fb    107  to their respective input signals  112  and V o    120 . Therefore, the output signal V o    120  becomes          V   o     =         V   i          G        (     j                 ω     )           1   +       G        (     j                 ω     )            H        (     j                 ω     )                                    
     For an oscillator, the output signal V o    120  must be nonzero even if the input voltage V 1    115  is zero. For this to be true, then 
     
       
         1+ G ( j ω) H ( j ω)=0  
       
     
     or 
     
       
           G ( j ω) H ( j ω)=−1  
       
     
     That is, the magnitude of the open-loop transfer function must be equal to 1 and the phase shift of the gain circuit  100  and the feedback circuit  105  must be 180°. 
     In FIG. 2, the gain circuit of the oscillator is formed by the differentially cross-connected pair of transistors M 1  and M 2  and the constant current source I 1 . The frequency dependent gain determining impedances are formed by the inductors L 1  and L 2  and the capacitors C 1  and C 2 . 
     The feedback circuit is accomplished by the connecting of the drain of the NMOS transistor M 1  to the gate of the NMOS transistor M 2  and the drain of the NMOS transistor M 2  to the gate of the NMOS transistor M 1 . This forms a cross-coupled differential oscillator. 
     A CMOS oscillator of the prior art is illustrated in FIG.  3 . In this case, the gain circuit is formed by the differentially connected pair of NMOS transistors M 1  and M 2 , the differentially connected pair of PMOS transistors M 3  and M 4 , and the current sources I 1  and I 2 . As described above, the frequency dependent gain determining impedances are formed by the inductors L 1  and L 2  and capacitors C 1  and C 2 . 
     The fundamental frequency f 0  of a cross coupled differential oscillator is determined by the formula:        ω   =         1         L   eff          C   eff                         such                 that                   f   o       =     1     2      π            L   eff          C   eff                                      
     where: 
     L elf  is the value of the effective inductance of the inductors L 1  and L 2 . 
     C eff  is the value of the effective capacitance of the capacitors C 1  and C 2 . 
     For the structure of the design where the inductors are mutually coupled then the effective inductance is: 
     
       
           L   eff =4 L   1 =4 L   2   
       
     
     The effective capacitance of the capacitors C 1  and C 2  is the parallel combination of the two capacitors C 1  and C 2  and is: 
     
       
           C   eff =½ C   1 =½ C   2   
       
     
     Combining the above, the frequency of the oscillators of FIGS. 2 and 3 is:          f   o     =       1     2      π          2      L1C2           .                            
     It should be noted that the capacitances C 1  and C 2  included the parasitic capacitances of the oscillator circuit. 
     It is well known in the art that phase noise is the result of small perturbations in phase due to small random shifts in oscillator frequency. These shifts are caused by thermal noise, shot noise, and flicker noise (1/f noise). These noises are functions of the device characteristics of the NMOS transistors M 1  and M 2  of FIGS. 2 and 3 and the PMOS transistors M 3  and M 4  of FIG.  3 . The phase noise is modeled as small voltage sources Vn 1  and Vn 2  at the gates of the NMOS transistors M 1  and M 2  of FIGS. 2 and 3 and voltage sources Vp 1  and Vp 2  at the gates of the PMOS transistors M 4  and M 4  of FIG.  3 . 
     The flicker noise (1f/noise) is a function of the active device characteristics of the NMOS transistors M 1  and M 2  of FIGS. 1 and 2 and PMOS transistors M 3  and M 4  of FIG.  3 . 
     The advancements in scaling of the device features in semiconductor processing allow multi-gigahertz operating frequencies to be readily achievable. Unfortunately, the same scaling down of MOS transistors have the opposite effect on the 1/f noise characteristics. The smaller device geometries are, the higher the 1/f noise components, leading to higher phase noise on the final oscillator. 
     “A 1.8 Ghz CMOS Voltage-Controlled Oscillator”,—Razavi, B., Digest of Technical Papers, 43rd ISSCC, 1997, pp. 388-389 and shown in FIG. 4 describes a structure of having multiple oscillators OSC 1  and OSC 2  coupled together to oscillate in quadrature or 90° out-of-phase. The oscillator OSC 1  and OSC 2  are structured and function as described in FIG.  2 . The differential pair of NMOS transistors M 3  and M 4  and the current source  12  form a first coupling circuit. The first coupling circuit has an in-phase input that is formed by the gate of the NMOS transistors M 3  and a out-of-phase input that is formed by the gate of the NMOS transistors M 4 . The first coupling circuit has a in-phase output that is formed by the drain of the NMOS transistor M 4  and an out-of-phase output that is formed by the drain of the NMOS transistor M 3 . The in-phase input of the first coupling circuit is connected to the drain of the NMOS transistor M 5  and the gate of the NMOS transistor M 6 . The out-of-phase input of the first coupling circuit is connected to the drain of the NMOS transistor M 6  and the gate of the NMOS transistor M 5 . The in-phase output of the first coupling circuit is connected to the drain of the NMOS transistor M 2  and the gate of the NMOS transistor M 1 . The out-of-phase output of the first coupling circuit is connected to the drain of the NMOS transistor M 1  and the gate of the NMOS transistor M 2 . 
     The differential pair of NMOS transistors M 7  and M 8  and the current source  14  form a second coupling circuit. The second coupling circuit has an in-phase input that is formed by the gate of the NMOS transistors M 7  and a out-of-phase input that is formed by the gate of the NMOS transistor M 8 . The second coupling circuit has a in-phase output that is formed by the drain of the NMOS transistor M 8  and an out-of-phase output that is formed by the drain of the NMOS transistor M 7 . The in-phase input of the second coupling circuit is connected to the drain of the NMOS transistor M 2  and the gate of the NMOS transistor M 1 . The out-of-phase input of the second coupling circuit is connected to the drain of the NMOS transistor M 1  and the gate of the NMOS transistor M 2 . The in-phase output of the second coupling circuit is connected to the drain of the NMOS transistor M 6  and the gate of the NMOS transistor M 5 . The out-of-phase output of the second coupling circuit is connected to the drain of the NMOS transistor M 6  and the gate of the NMOS transistor M 5 . 
     The structure as shown generates two oscillatory signals, one between the drains of the NMOS transistors M 1  and M 2  and one between the drains of the NMOS transistors M 5  and M 6 . The two oscillatory signals are in quadrature or 90° out of phase. The quadrature oscillator as described is subject to the phase noise problems as above-described. 
     “Design Issues in CMOS Differential LC Oscillators,” Hajimiri, A., Lee, T. H., IEEE Journal of Solid-State Circuits, pp. 717-724, May 1999 Vol. 34 Issue No. 5, presents an analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators. The effect of tail current and tank powder dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. 
     “Phase Noise in CMOS Differential LC Oscillators”, Hajimiri, A., Lee, T. H., Digest of Technical Papers—1988 Symposium on VLSI Circuits, 1988, pp. 48-51, describes an analysis of phase noise in differential cross-coupled tuned tank voltage controlled oscillators. The effect of active device noise sources as well as the noise due to the passive elements is taken into account. 
     U.S. Pat. No. 5,475,345 (Gabara) teaches a CMOS coupled-tank oscillator having two inverters coupled, input-to-output, by inductances that may be simply wires, and a capacitance acting in parallel with each inverter that may be, simply, the inverter&#39;s gate capacitance. 
     U.S. Pat. No. 5,850,163 (Drost, et al.) discusses an active inductor oscillator with wide frequency range. The active inductor oscillator includes a tank circuit, buffer and integrating circuit that use differential transistor pairs that reduce phase jitter due to external common-mode noise sources. 
     U.S. Pat. No. 5,959,504 (Wang) describes a voltage controlled oscillator CMOS circuit using back gate terminals of CMOS transistors to vary the parasitic capacitances of the transistors. The back gate terminals receive a signal from a variable voltage source so that oscillation can be controlled by adjusting the variable voltage. 
     “A Low-Noise, 900-MHz VCO in 0.6um CMOS” (Park, et al), IEEE Journal Of Solid-State Circuits, Vol. 34, pp 586-591, May 1999, Issue No. 5, describes a low-noise, 900 MHz, voltage controlled oscillator (VCO) fabricated in a 0.6-um CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. 
     “10 MHz CMOS OTA-C Voltage-Controlled Quadrature Oscillator,” Linares-Barranco, et al., IEEE Electronics Letters, June 1989, pp. 765-767, Vol. 25, Issue No. 12, details a quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C). 
     “RC Sequence Asymmetric Polyphase Networks for RF Integrated Transceives,” Galal et al. Transactions On Circuits And Systems—II: Analog And Digital Signal Processing, January 2000, pp. VOL 47, Issue No. 1, describes Resistance-Capacitance (RC) sequence asymmetric polyphase networks. A sequence of asymmetric polyphase networks provide the generation of highly matched wide-band quadrature signals which are immune to components mismatch, and suppression of the image signals without the need for highly selective RF filters and without employing image-reject mixing technique. 
     U.S. Pat. No. 5,714,911 (Gilbert) describes a quadrature oscillator that includes an amplitude control circuit. The amplitude control circuit is that is based upon the trigonometric identity sin 2 (Ωt)+cos 2 (Ωt)=1. The amplitude control circuit, referred to as a Pythagorator, includes two squaring circuits. Each squaring circuit receives a respective quadrature oscillator signal and squares it. The outputs of the two squaring circuits are joined together so as to sum the outputs of the two squaring circuits to produce a sum of squares signal. This signal, a current in the preferred embodiment, is provided to damping diodes coupled to the outputs of the quadrature oscillator. The damping diodes produce a shunt positive resistance at the outputs of the quadrature oscillator in response to this current that has the effect of canceling the shunt negative resistance of the regenerative elements of the oscillator thereby establishing the amplitude of the quadrature oscillator signals at a desired amplitude. 
     U.S. Pat. No. 5,949,295 (Schmidt) teaches an integratable tunable resonant circuit for use in filters and oscillators. The circuit incorporates differential amplifier stage with a pair of differentially connected transistors with two negative feedback resistors. The two negative feedback resistors increase the linearity range of an input voltage of the differential amplifier stage. 
     U.S. Pat. No. 6,008,701 (Gilbert) details a quadrature oscillator using inherent nonlinearities of impedance cells to limit amplitude. The quadrature oscillator based on two cross-coupled integrator cells utilizing the inherent nonlinearity of positive and negative impedance cells to control the amplitude of oscillation. The oscillator is simplified thus eliminating the need for an outer control loop. A negative impedance cell is coupled to each integrator cell for assuring proper start-up and enhancing the amplitude of oscillation. A positive impedance cell is also coupled to each integrator cell to dampen the amplitude of oscillation. The transconductance of each impedance cell varies in response to the bias current provided to the cell. Thus, by controlling the bias currents through the cells, the negative and positive impedances seen by each integrator cell can made to cancel at the desired oscillation amplitude, so that the circuit oscillates without any damping or enhancement. By utilizing the inherent nonlinearity of positive and negative impedance cells, the bias currents provided to the impedance cells can remain fixed for a given frequency of operation, thereby simplifying the design of the oscillator and providing precise, robust control. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a cross-coupled differential MOS oscillator. 
     Another object of this invention is to provide a cross-coupled differential MOS oscillator having reduced phase noise. 
     Another object of this invention is to provide a RF communication device, e.g., a transmitter or receiver, having a cross-coupled differential MOS oscillator. 
     To accomplish these and other objects, an oscillator having low phase noise that is formed of a frequency dependent amplifier to amplify a signal having a fundamental frequency; a frequency dependent feedback device that is connected between an output of the frequency dependent amplifier and an input of the frequency dependent amplifier to feed a portion of an amplified signal having the fundamental frequency to an input of the frequency dependent amplifier to stimulate oscillation; and a attenuating device in communication with the frequency dependent amplifier. The attenuating device reduces the gain of the frequency dependent amplifier for signals having frequencies much, much less than the fundamental frequency to decrease the phase noise. 
     The frequency dependent amplifier has an amplifying means. The amplifying means has an input and an output, whereby a signal at the input is amplified by a gain factor to form a signal at the output. The frequency dependent amplifier further, has a frequency dependent gain determining in communication with the amplifying means. The frequency dependent gain determining impedance determines the frequency at which the maximum gain of the frequency dependent amplifier occurs. 
     The amplifying means is composed of a pair of cross-coupled MOS transistors. The drain of each MOS transistor is connected to a gate of the other MOS transistor and to a port of the frequency dependent gain determining impedance. A first current source is connected to a source of one of the MOS transistors and to a ground reference point and to a first port of the attenuating device. A second current source is connected to a source of the other MOS transistor and to a second port of the attenuating device. 
     The frequency dependent determining impedance is formed by at least one inductor in communication with the amplifying means and a power supply voltage source, and at least one capacitor in communication with the amplifying means and a ground reference point. 
     The attenuating device is in the preferred embodiment, a capacitor in communication with the sources of the cross-coupled MOS transistors. The value of the capacitor is selected such that the fundamental frequency of oscillation is from approximately 10 times to approximately 20 times the high pass bandwidth of the cross-coupled MOS transistors. 
     Alternately, the amplifying means is formed of a cross-coupled pair of MOS transistors of the first conductivity type and a cross-coupled pair of MOS transistors of the second conductivity type to form a CMOS amplifying means. The drain of each MOS transistor of the first conductivity type is connected to a gate of the other MOS transistor of the first conductivity type and to a port of the frequency dependent gain determining impedance. A first current source is connected to a source of one of the MOS transistors of the first conductivity type and to a first port of the attenuating device, and a second current source is connected to a source of the other MOS transistor of the first conductivity type and to a second port of the attenuating device. 
     The drain of each MOS transistor of the second conductivity type is connected to a gate of the other MOS transistor of the second conductivity type and to one port of the frequency dependent gain determining impedance. A third current source in communication with a source of one of the MOS transistors of the second conductivity type and to a third port of the attenuating device, and a fourth current source in communication with a source of the other MOS transistor of the second conductivity type and to a fourth port of the attenuating device. 
     The attenuating device in the CMOS embodiment of the amplifying means is composed of a first capacitor connected from the first port to the second port of the gain attenuating means and a second capacitor in communication with the third and fourth ports of the gain attenuating means. 
     An application of the cross-coupled differential MOS oscillator is as the carrier oscillator of an RF transmitter. Alternately, the cross-coupled differential MOS oscillator is the local oscillator of an RF receiver that is used to demodulate the incoming RF signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a system block diagram of a frequency dependent system with feedback of the prior art. 
     FIG. 2 is a schematic diagram of a cross-coupled differential NMOS oscillator of the prior art. 
     FIG. 3 is a schematic diagram of a cross-coupled differential CMOS oscillator of the prior art. 
     FIG. 4 is a schematic diagram of a quadrature oscillator of the prior art. 
     FIGS. 5 a  and  5   b  are schematic diagrams of two embodiments of cross-coupled differential MOS oscillators of this invention. 
     FIGS. 6 a  and  6   b  are schematic diagrams of the cross-coupled differential MOS oscillator of this invention (FIG. 5 a ) operating at low frequencies (FIG. 6 a ) and at high frequencies (FIG. 6 b ). 
     FIG. 7 is a schematic diagram of a cross-coupled differential CMOS oscillator of this invention. 
     FIG. 8 is a schematic diagram of a quadrature oscillator having low phase noise of this invention having. 
     FIG. 9 is a block diagram of a multiple frequency transforming circuit having low phase noise of this invention. 
     FIG. 10 is a schematic diagram of a differential amplifier having low phase noise of this invention. 
     FIG. 11 is a plot of the spectral display of the phase noise versus the frequency offset from the fundamental frequency. 
     FIG. 12 a  is a schematic diagram of an ideal current source implemented by a biased MOSFET. 
     FIG. 12 b  is a schematic diagram of a current source of FIG. 12 a  having the noise component represented as a voltage source. 
     FIG. 12 c  is a schematic diagram of a current source of FIG. 12 a  having the noise component represented as a parallel current source. 
     FIG. 13 a  is a current source implemented as a programmable resistance. 
     FIG. 13 b  is an example of a programmable resistance of FIG. 13 a.    
     FIG. 14 a  is a current source implemented as an inductance and programmable resistance. 
     FIG. 14 b  is an example of a programmable resistance of FIG. 14 a.    
     FIG. 14 c  is an example of programmable inductance/resistance of FIG. 14 a.   
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Refer now to FIG. 5 a  for a discussion of the cross-coupled differential NMOS oscillator having low phase noise of this invention. The frequency dependent gain amplifier is formed by the NMOS transistors M 1  and M 2  and the constant current sources I 1  and I 2 . The frequency dependent gain determining impedance is formed by the inductors L 1  and L 2  and the capacitors C 1  and C 2 . 
     The inductor L 1  is connected from the drain of the NMOS transistors M 1  to the reference voltage source V cc  and the inductor L 2  is connected from the drain of the NMOS transistor M 2  to the reference voltage source V cc . The capacitor C 1  is connected from the drain of NMOS transistor M 1  to the ground reference point and the capacitor C 2  is connected from the drain of the NMOS transistor M 2  to the ground reference point. It is apparent to those skilled in the art that, while the capacitors C 1  and C 2  are connected to the ground reference point, the capacitors C 1  and C 2  may be connected to any reference voltage source or to any power supply voltage source and not effect the operation of the oscillator as explained above. 
     The fundamental frequency f 0  of the cross-coupled differential oscillator of this invention is determined as:        ω   =     1       2        L   1          C   1                                  
     such that          f   o     =     1     2      π          2        L   1          C   1                                    
     where: 
     L 1  is the value of the inductance of the inductor L 1  or L 2 . 
     C 1  is the value of the capacitance of the 
     capacitor C 1  or C 2 . 
     The drain of the NMOS transistor M 1  is connected to the gate of the NMOS transistor M 2  and the drain of the NMOS transistor M 2  is connected to the gate of the NMOS transistor M 1 . This cross-coupling of the drains to the gates of the NMOS transistors M 1  and M 2  forms the feedback circuit of the oscillator. 
     The source of the NMOS transistor M 1  is connected to the constant current source I 1  and the source of the NMOS transistor M 2  is connected to the constant current source I 2 . The decoupling capacitor C c  is connected between the sources of the NMOS transistors M 1  and M 2  to act as a gain-attenuating device. 
     Refer now to FIGS. 6 a  and  6   b  to understand the operation of the cross-coupled differential oscillator of this invention. The decoupling capacitor C c  is chosen to have very high impedance at frequencies much, much lower than the fundamental frequency f 0  of the cross-coupled differential NMOS oscillator of FIG. 6 a.  At frequencies much lower than the fundamental frequency f 0 , the cross-coupled differential NMOS oscillator of this invention functions as shown in FIG. 6 a.  The current sources are separated and the gain of the frequency dependent gain circuit formed by the NMOS transistors M 1  and M 2  and the current sources I 1  and I 2  becomes much, much less than one, preventing the flicker noise or 1/f noise of the noise voltage sources Vn 1  and Vn 2  from being amplified and being added to the output signal of the cross-coupled differential NMOS oscillator of this invention. 
     At the fundamental frequency f 0 , the decoupling capacitor C c  is chosen to have an impedance that is very low. Thus, the cross-coupled differential NMOS oscillator of this invention functions as shown in FIG. 6 b.  The frequency dependent gain circuit formed by the NMOS transistors M 1  and M 2  and the constant current sources I 1  and I 2  function as described in FIG.  2 . The constant current sources I 1  and I 2  are summed together to form effectively one current source (I 1 +I 2 ). Thus, the frequencies at the fundamental frequency f 0  are amplified. The frequency gain determining impedance formed by the inductors L 1  and L 2  and the capacitors C 1  and C 2  insure that the peak gain of the frequency dependent gain circuit is at the fundamental frequency f 0  and that the higher and lower frequencies are attenuated. 
     The noise voltage sources Vn 1  and Vn 2  are, as described above, the models of the flicker or 1/f noise that is caused by the device characteristics of the NMOS transistors M 1  and M 2 . The noise voltage sources Vn 1  and Vn 2  having frequency content that is much less than the fundamental frequency f 0  and thus will be attenuated as shown in FIG. 6 a.    
     The high pass bandwidth (BW) of the cross-coupled differential oscillator is a function of the transconductance of the NMOS M 1  and M 2  and the value of the decoupling capacitor Cc and is determined by the formula:        BW   =         g   m       2      π                 Cc       .                            
     The high pass bandwidth BW must be maintained at a level that is much, much smaller than the cutoff frequency of the cross-coupled differential oscillator to prevent loss of the fundamental frequency signal. The decoupling capacitor Cc should be chosen such that the fundamental frequency f 0  of the cross-coupled differential oscillator is from approximately ten times to approximately twenty times the high pass bandwidth BW of the cross-coupled oscillator. 
     FIG. 5 b  illustrates a second embodiment of a cross-coupled differential NMOS oscillator of this invention. The frequency dependent gain amplifier in this case is formed by the NMOS transistors M 1  and M 2  and the resistors R 1  and R 2 . The resistor R 1  is connected between the source of the NMOS transistor M 1  and the ground reference point. The resistor R 2  is connected between the source of the NMOS transistor M 2  and the ground reference point. 
     The inductor L 1  is connected from the drain the NMOS transistor M 1  to the reference voltage source V cc  and the inductor L 2  is connected from the drain of the NMOS transistor M 2  to the reference voltage source V cc . The capacitor C 1  is connected from the drain of NMOS transistor M 1  to the ground reference point and the capacitor C 2  is connected from the drain of the NMOS transistor M 2  to the ground reference point. As described above, it is apparent to those skilled in the art that, while the capacitors C 1  and C 2  are connected to the ground reference point, the capacitors C 1  and C 2  may be connected to any reference voltage source or to any power supply voltage source and not effect the operation of the oscillator. 
     The decoupling capacitor Cc 2  is connected between the sources of the NMOS transistors M 1  and M 2  and acts as gain attenuating device as above-described. 
     A third embodiment of this invention, as shown in FIG. 7, implements the frequency dependent gain circuit as a cross-coupled differential CMOS amplifier. The frequency dependent gain circuit is formed by the NMOS transistors M 1  and M 2 , the P-type MOS (PMOS) transistors M 3  and M 4 , and the current sources I 1 , I 2 , I 3 , and I 4 . 
     The drain of the NMOS transistors M 1  is connected to the gate of the NMOS transistor M 2  and the drain of the NMOS transistor M 2  is connected to the gate of the NMOS transistor M 1 . Similarly, the drain of the PMOS transistor M 3  is connected to the gate of the PMOS transistor M 4  and the drain of the PMOS transistor M 4  is connected to the gate of the PMOS transistor M 3 . The cross-coupling of the drains and gates of the NMOS transistors M 1  and M 2  and the PMOS transistors M 3  and M 4  forms the feedback circuit of the oscillator. 
     The inductor L 1  is connected between the drains of the NMOS and PMOS transistors M 1  and M 3  and the reference voltage source V cT . The inductor L 2  is connected between the drains of the NMOS and PMOS transistors M 2  and M 4  and the reference voltage source V cT . The capacitor C 1  is connected between the drains of the NMOS and PMOS transistors M 1  and M 3  and the ground reference point. The capacitor C 2  is connected between the drains of the NMOS and PMOS transistors M 2  and M 4  and the ground reference point. Again, as described above, it is apparent to those skilled in the art that, while the capacitors C 1  and C 2  are connected to the ground reference point, the capacitors C 1  and C 2  may be connected to any reference voltage source or to any power supply voltage source and not effect the operation of the oscillator. 
     The inductors L 1  and L 2  and the capacitors C 2  and C 2  form the frequency dependent gain determining impedance. 
     The constant current source I 1  is connected to the source of the NMOS transistors M 1 , and the constant current source I 2  is connected to the source of the NMOS transistors M 2 . Similarly, the constant current source I 3  is connected to the source of the PMOS transistor M 3  and the constant current source I 4  is connected to the source of the PMOS transistor M 4 . 
     The gain-attenuating circuit is formed by the decoupling capacitors C c   3  and C c   4 . The decoupling capacitor C c   3  is connected between the sources of the NMOS transistors M 1  and M 2 . The decoupling capacitor C c   4  is connected between the sources of the PMOS transistors M 3  and M 4 . 
     The gain-attenuating circuit (C c   3  and C c   4 ) functions much as described in FIGS. 6 a  and  6   b.  For frequencies much, much less than the fundamental frequency f 0 , the decoupling capacitors C c   3  and C c   4  have a large impedance and force the gain of the frequency dependent gain circuit to a level much, much less than one to attenuate the low frequency flicker or 1/f noise. Conversely, for frequencies equal to the fundamental frequency f c , the decoupling capacitors Cc 3  and Cc 4  have low impedance and the frequency dependent gain circuit functions equivalently to that described in FIG.  3 . The constant current sources I 1  and I 2  are summed as described in FIG. 5 b  and, similarly, the constant current sources I 3  and I 4  are summed together to function equivalently to the description of FIG.  3 . 
     The high pass bandwidth (BW) of the cross-coupled differential oscillator is a function of the transconductance of the NMOS M 1  and M 2  and the value of the decoupling capacitor Cc 3  and the transconductance of the PMOS transistors M 3 ′ and M 4  and the value of the decoupling capacitor Cc 4  and is determined by the formula:        BW   =         g   m       2      π                 Cc       .                            
     The high pass bandwidth BW must be maintained, as described above, at a level that is much, much smaller than the cutoff frequency of the cross-coupled differential oscillator to prevent loss of the fundamental frequency signal f 0 . The decoupling capacitor Cc should be chosen such that the fundamental frequency f 0  of the cross-coupled differential oscillator is from approximately ten times to approximately twenty times the high pass bandwidth BW of the cross-coupled oscillator. 
     FIG. 8 illustrates a quadrature oscillator having low phase noise of this invention. The cross-coupled differential oscillators OSC 1  and OSC 2  are structured and function as cross-coupled differential oscillators as described in FIG. 5 a.  The NMOS transistors M 3  and M 4  and the current sources I 3  and I 4  form a first coupling circuit. The current source I 3  is connected between the source of the NMOS transistor M 3  and the ground reference point. The current source I 4  is connected between the source of the NMOS transistor M 4  and the ground reference point. The gate of the NMOS transistor M 3  functions as the in-phase input of the first coupling circuit and the gate of the NMOS transistor M 4  functions as the out-of-phase input of the first coupling circuit. The drain of the NMOS transistor M 4  functions as the in-phase output of the first coupling circuit and the drain of the NMOS transistor M 3  functions as the out-of-phase output of the first coupling circuit. The decoupling capacitor Cc 6  is connected between the sources of the NMOS transistors M 3  and M 4 . The decoupling capacitor Cc 6  is chosen to function similar to the decoupling capacitor Cc of FIG. 5 a  to eliminate the phase noise from the first coupling circuit. 
     The in-phase input of the first coupling circuit is connected to the drain of the NMOS transistor M 5  and the gate of the NMOS transistor M 6  of the second cross-coupled differential oscillator OSC 2 . The out-of-phase input of the first coupling circuit is connected to the drain of the NMOS transistor M 6  and the gate of the NMOS transistor M 5  of the second cross-coupled differential oscillator OSC 2 . The in-phase output of the first coupling circuit is connected to the drain of the NMOS transistor M 2  and the gate of the NMOS transistor M 1  of the first cross-coupled differential oscillator OSC 1 . The out-of-phase output of the first coupling circuit is connected to the drain of the NMOS transistor M 1  and the gate of the NMOS transistor M 2  of the first cross-coupled differential oscillator OSC 1 . 
     The NMOS transistors M 7  and M 8  and the current sources I 7  and I 8  form the second coupling circuit. The current source I 7  is connected between the source of the NMOS transistor M 7  and the ground reference point. The current source I 8  is connected between the source of the NMOS transistor M 8  and the ground reference point. The gate of the NMOS transistor M 7  functions as the in-phase input of the second coupling circuit and the gate of the NMOS transistor M 4  functions as the out-of-phase input of the second coupling circuit. The drain of the NMOS transistor M 7  functions as the in-phase output of the second coupling circuit and the drain of the NMOS transistor M 8  functions as the out-of-phase output of the second coupling circuit. The decoupling capacitor Cc 8  is connected between the source of the NMOS transistors M 7  and M 8 . The decoupling capacitor Cc 8  is chosen to function similar to the decoupling capacitor Cc of FIG. 5 a  to eliminate the phase noise from the first coupling circuit. 
     The in-phase input of the second coupling circuit is connected to the drain of the NMOS transistor M 1  and the gate of the NMOS transistor M 2  of the first cross-coupled differential oscillator OSC 1 . The out-of-phase input of the second coupling circuit is connected to the drain of the NMOS transistor M 2  and the gate of the NMOS transistor M 1  of the first cross-coupled differential oscillator OSC 1 . The in-phase output of the second coupling circuit is connected to the drain of the NMOS transistor M 6  and the gate of the NMOS transistor M 5  of the second cross-coupled differential oscillator OSC 2 . The out-of-phase output of the second coupling circuit is connected to the drain of the NMOS transistor M 5  and the gate of the NMOS transistor M 6  of the second cross-coupled differential oscillator OSC 2 . 
     The in-phase and the out-of-phase of the first coupling circuit are transposed relative to the similar in-phase and out-of-phase connections of the second coupling circuit. This transposition is to force the necessary phase shift to cause the cross-coupled differential oscillations OSC 1  and OSC 2  to oscillate in quadrature or 90° out of phase as described above in Razavi. 
     The structure of the oscillator of FIG. 8 is generalized to a structure as shown in FIG.  9 . This circuit is used to create multiple phased oscillators, mixers, modulators, demodulators, and any circuit requiring the transforming of the an input signal with multiple frequencies. The frequency transforming circuit of FIG. 9 has multiple coupling elements CE 1 , CE 2 , . . . , CEn that are serially connected output to input. The frequency transforming circuit, further, has multiple cross-coupled differential oscillators OSC 1 , OSC 2 , . . . , OSCn. The output of each of the multiple cross-coupled differential oscillators OSC 1 , OSC 2 , . . . , OSCn is connected to an input of one of the coupling elements coupling elements CE 1 , CE 2 , . . . , CEn. 
     The input signal is developed between the input terminals IN+ and IN− and is transferred to the first coupling element CE 1 . The input signal is then combined with the oscillatory signal from the first cross-coupled differential oscillator OSC 1 . The signal at the output of the first coupling element CE 1  is transferred to the input the second coupling element CE 2  where it is combined with the second oscillatory signal from the second cross-coupled differential oscillator OSC 2 . The signal at the output of the second coupling element CE 2  is transferred to the following coupling elements CEn for combination with the oscillatory signals from the subsequent oscillators OSCn. The signal from the final coupling element CEn is transferred to subsequent circuitry. In the alternative, the output of the last coupling element CEn may be connected to the input of the first coupling element CE 1  to feedback the output signal (or a portion of the output signal) to the input of the circuit. 
     The coupling elements coupling elements CE 1 , CE 2 , . . . , CEn, in addition to combining the oscillatory signals from the multiple cross-coupled differential oscillators OSC 1 , OSC 2 , . . . , OSCn, may provide phase shifting for a multiple phased oscillator, or any appropriate filtering, integrating, differentiating function. 
     Further, the outputs of each of the coupling elements CE 1 , CE 2 , . . . , CEn is connected to an input of a buffering amplifier BUF 1 , BUF 2 , . . . . , BUFn. Each of the a buffering amplifiers BUF 1 , BUF 2 , . . . , BUFn capture the output of one of the coupling elements CE 1 , CE 2 , . . . , CEn and amplifies and isolates the signal to form the output signals φ 1 , φ 2 , . . . , φn that are transferred to external circuitry. 
     Each cross-coupled differential oscillators OSC 1 , OSC 2 , . . . , OSCn, each coupling element CE 1 , CE 2 , . . . , CEn, and each buffering amplifier BUF 1 , BUF 2 , . . . , BUFn has a differential amplifier with low phase noise of this invention as shown in FIG.  10 . The differential amplifier is formed by the NMOS transistors M 1  and M 2  and the current sources I 1  and I 2 . 
     The gates of the NMOS transistors M 1  and M 2  respectively form the in-phase input IN+ and the out-of-phase input IN−. The drains of the NMOS transistors M 1  and M 2  respectively form the in-phase output OUT+ and the out-of-phase output OUT−. 
     The current source I 1  is connected between the source of the NMOS transistor M 1  and the ground reference point. The current source I 2  is connected between the source of the NMOS transistor M 2  and the ground reference point. 
     The decoupling capacitor Cc is connected between the sources of the NMOS transistors M 1  and M 2  to provide the necessary gain attenuating to eliminate the phase noise. When the differential amplifier is operating at sufficiently high frequency, the impedance of the decoupling capacitor Cc is very low and the current sources I 1  and I 2  combine. The differential amplifier operates as a true differential amplifier having very high gain. However, if the frequency of operation is sufficiently low, the impedance of the decoupling capacitor Cc is very high and the gain of the differential amplifier is very low, thus attenuating the signals of the phase noise. 
     The high pass bandwidth BW of the differential amplifier of this invention is a function of the transconductance (g m ) of the NMOS transistors “looking” into the sources and is determined by the formula:        BW   =         g   m       2      π                 Cc       .                            
     For the most successful operation of the differential amplifier the decoupling capacitor Cc should be chosen such that the fundamental frequency f 0  of the cross-coupled differential oscillator is from approximately ten times to approximately twenty times the high pass bandwidth BW of the cross-coupled oscillator. This insures that the fundamental frequency f 0  is not affected by the operation of the decoupling capacitor Cc. 
     FIG. 11 is plots  700  and  750  that illustrate the spectral density of the phase noise of the output signal versus the frequency offset from the fundamental frequency f 0  of cross-coupled differential oscillators of this invention  700  and the prior art. As can be seen, the spectral density of the phase noise of the cross-coupled differential NMOS transistor is lower than an equivalent design of the prior art. 
     FIG. 12 a  is an example of an ideal current source utilized by the present invention. In FIG. 12 a  the ideal current source is implemented as a MOS transistor which is biased so that the MOS transistor operates in the saturation region. Such a current source may generate a 1/f noise component, which can be significant in MOS devices. This problem is exacerbated at higher frequencies, in which the oscillator of the present invention is designed to operate. Additionally, as the device geometry becomes small the 1/f noise becomes more pronounced. FIG. 12 c  illustrates an equivalent representation showing a current source I and a noise component current source I noise . 
     A conventional solution to reduce or eliminate the 1/f noise is to utilize a resistor as the current source. However, it is difficult to set the appropriate amount of resistance for the oscillator to function properly. In accordance with an embodiment of the present invention a programmable resistance R is utilized as the current source, as shown in FIG. 13 a.  The programmable resistance can insure the appropriate amount of resistance to provide the current to the oscillator. The programmable resistance may be implemented as a switched resistor array. One example of the resistor array is shown in FIG. 13 b.  The resistor array shown therein comprises resistors R 1 -Rn and associated switches S 1 -Sn. Of course as will be appreciated by one of ordinary skill in the art, other resistor configurations may be employed and are within the scope and spirit of the present invention. 
     An alternative embodiment of the current source in accordance with the present invention is to utilize an inductance L in series with a programmable resistance R, as shown in FIG. 14 a.  As with the previous embodiment there is no 1/f noise, since the inductance and resistance are passive components. This configuration behaves like a constant current source regardless of the input voltage, especially if the inductance is sufficiently high, at high frequencies the current is essentially constant (due to the inductance properties). In this embodiment of the programmable resistance may be implemented as a switched resistor array. One example shown therein comprises resistors R 1 -Rn and associated switches S 1 -Sn. Of course as will be appreciated by one of ordinary skill in the art, other resistor configurations may be employed and are within the scope and spirit of the present invention. The inductance L inherently has some resistance. Accordingly, the inductance and programmable resistance may be alternatively be implement by a switched inductance array, wherein each inductance inherently has the appropriate amount of resistance. 
     It will be apparent to those skilled in the art that the NMOS transistors M 1  and M 2  of FIG. 5 a  can be replaced by PMOS transistors with appropriate changes to the power supply voltage source V cc  and the ground reference point. Further, it would be apparent that the NMOS transistors could be replaced by bipolar junction transistors or other field effect transistors constructed of materials such as Galium-Arsenide and still be in keeping with this invention. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.