Abstract:
An image sensor includes a plurality of pixels for capturing an image; a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image; a decoder for selecting each of the units of the sample and hold circuit array for output; and a delay circuit that includes an adjustable time delay to the decoder for compensating for time delays.

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates generally to the field of CMOS image sensors and, more particularly to, such image sensors having a programmable delay circuit for correcting the non-uniform delays at the column decoder output caused by the long address bus.  
       BACKGROUND OF THE INVENTION  
       [0002]     As the CMOS image size and speed continue to increase, the column sample and hold array is becoming larger and time to read out a column S/H circuit is shorter. A decoder circuit is needed to address each individual S/H circuit within such S/H array to the output. The input address codes are sent to the decoder inputs through long buses which are usually the size of a row of pixels. Due to the large resistance and capacitance of the wires, these decoder addresses are sent the decoder with larger and larger delays as the column S/H circuit array is being read out one by one in the direction away from the decoder address drivers. These delays reduce the effective read-out time and cause noise at the output of the column S/H array. An additional delay which reduces as the column sample and hold array is read out is added to the decoder address buses to compensate the delay due to the bus parasitic resistance and capacitance.  
         [0003]     Consequently, a need exists for a CMOS image sensor which corrects for the non-uniform delays at the column decoder output caused by the long address bus.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in an image sensor comprising a plurality of pixels for capturing an image; a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image; a decoder for selecting each of the units of the sample and hold circuit array for output; and a delay circuit that includes an adjustable time delay to the decoder for compensating for time delays.  
         [0005]     These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.  
         [0000]     Advantageous Effect of the Invention  
         [0006]     The present invention has the following advantage of correcting for the non-uniform delays at the column decoder output caused by the long address bus. The present invention also increases the effective sensor readout speed and reduces the mis-sampling of the S/H circuit by the next stage circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  is a schematic diagram of a typical pixel of the present invention;  
         [0008]      FIG. 2  is a block diagram of the image sensor of the present invention;  
         [0009]      FIG. 3  is a block diagram of the delay management circuit of the present invention;  
         [0010]      FIG. 4  is a block diagram of the programmable delay circuit of the present invention; and  
         [0011]      FIG. 5  is a side view of a digital camera of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]      FIG. 1  shows a typical 4-transistor CMOS active image sensor pixel. A photodiode PD collects charge in response to incident light. Transistor M 1  is controlled by a voltage applied on its gate TG to transfer the charge accumulated in PD to the floating diffusion capacitor C FD  when TG is “high”. Floating diffusion capacitor C FD  converts the charge to voltage. Transistor M 2  resets the floating diffusion capacitor C FD  when a “high” voltage is applied to its gate RG. The selectable pixel output buffer amplifier is composed of M 3  and M 4 . M 3  is the amplifier input transistor and M 4  is the row-selecting transistor to enable the amplifier. The voltage at the floating diffusion FD is applied to the input of the pixel amplifier and sent to the sample-and-hold circuit array outside the pixel array when a “high’ voltage is applied to the gate RS of transistor M 4 .  
         [0013]     A block diagram of a CMOS image sensor  10  is shown in  FIG. 2 . The image sensor  10  includes a pixel array  20 , a row decoder  30 , a column sample and hold circuit array  40  and a column decoder  50 . The image signal is generated within the pixel array  20  and is transferred to the column sample and hold circuit array  40  row by row (as indicated by the solid arrows). One row of the image signal is sampled and held by the sample and hold circuit array  40  which includes a plurality of units  60 , one for each pixel signal. The sample and hold circuit array  40  sends the signals from each of the units  60  to the output  70  of the sample and hold circuit array  40  one unit at a time. The column decoder  50  selects which signal value from the sample and hold circuit array  40  will be output to an output bus  75  and the particular sequence of output to the output bus  75 . Column decoder address drivers  80  are used to drive the address bus lines of the column decoder  50 . Once a row of signal is sent out of the sample and hold circuit array  40 , another row of image signal is moved to the sample and hold circuit array  40  from the pixel array  20 . This process repeats until all rows in a frame of image are processed.  
         [0014]      FIG. 3  shows a programmable delay circuit  90 , an address synchronizer  100  and the decoder address driver circuit  80 . A programable delay circuit  90  adds a time delay to a master clock. The time delay at the output varies according to the particular address of the column decoder. For example, the address 000 (the first address) receives the maximum delay and address 111 (the last address) receives zero or substantially zero delay or minimal delay. Address 000 represents the physical location of the sample and hold circuit  40  which is closest to the driver  80 , and address 111 represents the physical location of the sample and hold circuit  40  which is farthest from the driver  80 . This delay will compensate for the inherent time delay that the decoder address bus  110  will have since there is an inherent delay as the signal travels along the bus of the column decoder  50 . The first address 000 will have substantially zero inherent delay from the bus  110  so it receives the maximum time delay from the delay circuit  90 . The last address will have maximum inherent time delay from the decoder bus  110  and will receeive mimium time delay from the delay circuit  90 . This produces a uniform or substantially uniform delay across the column decoder array  50 . The synchronizer  100  synchronizes the input address to the output of the programmable delay circuit  90  so that the delay is added to the input address of the decoder  50 .  
         [0015]     Referring to  FIG. 4 , there is shown a detailed schematic of the delay circuit  90 . The delay circuit  90  includes a plurality of delay cells  120  having the same amount of time delay. A multiplexer  130  is connected to outputs of the delay cells  120  for selecting one output of the delay cells  120 . This output corresponds to the desired time delay. For example, the output D 0  includes zero delay cells, output D 1  includes one delay cell and DK includes K delay cells. The particular address determines which output the multiplixer  130  selects to the output.  
         [0016]     Referring to  FIG. 5 , there is shown a digital camera  140  having the image sensor  10  of the present invention included therein for illustrating a typical commercial embodiment (end user product) to which the ordinary consumer is accustomed.  
         [0017]     The present invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.  
       PARTS LIST  
       [0000]    
       
           10  image sensor  
           20  pixel array  
           30  row decoder  
           40  column sample and hold circuit array  
           50  column decoder  
           60  units  
           70  output  
           75  output bus  
           80  decoder address driver  
           90  programmable delay circuit  
           100  address synchronizer  
           110  address bus  
           120  delay cells  
           130  multiplexer  
           140  digital camera