Abstract:
The present invention provides a system and method for simultaneously controlling a plurality of print engines connected together (in series, in parallel or otherwise) that facilitates electronic stitching between the print engines. More specifically, the present invention provides a system and method for synchronizing the pixel deposition frequencies and the drive mechanisms between the various inter-connected print engines so as to eliminate synchronization between the print engines. The method for synchronizing the pixel deposition frequencies and/or drive mechanisms between a plurality of print engines comprises the steps of: (a) coupling the plurality of print engines together with a printer controller, (b) embedding a first clock signal in data; (c) transmitting the data to the print engines; (d) each of the print engines receiving the data; (e) each of the print engines deriving a second clock signal from the data received, which is directly proportional to the first clock signal; and (f) each of the print engines driving its corresponding pixel deposition mechanism and/or its drive mechanisms with the second clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     The present application is a continuation-in-part of U.S. application Ser. No. 08/745,699, filed Nov. 12, 1996. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to digital and print-on-demand printing systems; and more particularly, to a high-speed printer controller system that is configured to control a multitude of print engines simultaneously, and is configured to synchronize the deposition of image pixels and to “lock-step” the transport mechanisms on the multitude of print engines to a single clock source, thereby reducing beat frequency and other errors between the print engines. 
     An ink jet printing system is an example of a printing system that is notorious for having registration problems and beat frequency errors between various print engines (ink jet printheads) controlled by at least one printer controller. Ink jet printing is a non-impact print method which is based upon controlling the behavior of a fluid ink stream using pressure, ultrasonic vibration and electrostatic forces. A typical ink jet printhead will include a multitude of nozzle orifices, aligned in an array, for emitting a corresponding multitude of fluid ink streams, commonly referred to as an array of ink. Pressure is created by a push rod to force the ink from the ink chamber and through an array of nozzle orifices. 
     A high frequency ultrasonic vibration (referred to as a “modulation signal”) is applied to the push rod and, in turn, to the ink stored in an ink chamber within the ink jet printhead, to establish a standing wave pattern within the ink. To create the modulation signal, the typical ink jet print head will utilize an internal clock source which is sent to a piezoelectric crystal, typically mounted within the push rod assembly. The piezoelectric crystal will thus vibrate at the frequency of the clock source. The vibrational waves will conduct into the ink chamber, causing the standing wave pattern within the ink. This standing wave pattern in the ink causes the ink to break into individual droplets, corresponding to individual pixels of the printed image, when the ink emerges from the nozzle orifices. The resulting array of ink droplet streams is directed (typically downward) towards the substrate to receive the printed image. 
     A multitude of electrodes are positioned adjacent to each of the ink droplet streams, near the nozzle orifices. The electrodes, controlled by the ink jet printhead, apply a voltage to the droplets which are not intended to contact the substrate. Below the electrodes, the droplet streams pass through a high voltage field which forces the charged droplets to be deflected into a gutter and which allows the uncharged droplets to pass through the field and onto the substrate, thus forming the printed image. 
     The nozzle orifices are typically arranged on the ink jet printhead in a row, where each nozzle orifice corresponds to one column of image pixels on the final printed image. The printed image is formed by emitting successive horizontal lines of the ink droplets (referred to as “strokes”) applied to the continuously moving substrate (moving in the vertical direction). Each stroke forms one row of pixels on the final printed image. The electrodes are controlled for each stroke by the ink jet printhead in accordance with the bitmap data sent to the print head by the raster printer controller. 
     In low-speed printing operations, where the substrate is moved at low speeds under the ink jet printheads, the width of the row of nozzle orifices is not a concern. However, in high-speed printing operations, where the substrate is moved at high speeds under the ink jet printheads (i.e., to print 1000 feet per minute), the size of the row of nozzle orifices becomes a real concern because of the time it takes for the vibrational waves in the chamber to travel from the push rod to the far ends of the printhead. Accordingly, to be able to print detailed, full size images in high speed ink jet print operations, it is necessary to utilize a plurality of the ink jet print heads, where each print head is responsible to print one vertical portion or “swath” of the image. One “swath” of an image corresponds to the number of vertical columns of pixels that one ink jet printhead will be able to print. Typically, the width of each swath can range from approximately 20 to 1024 pixels (i.e., the swath would comprise 20 to 1024 columns of pixels), however the range can vary depending upon the application. 
     Because the physical width of the ink jet printhead exceeds the width of the swath printed by the ink jet printhead, the multiple ink jet printheads cannot be aligned side by side with respect to each other without experiencing noticeable gaps between the swaths. Therefore, to get a continuous image across the width of the entire printed page, with no noticeable gaps between the swaths, it is necessary to stagger the ink jet print heads vertically with respect to the substrate such that they do not interfere with each other. It is also necessary to simultaneously control the multiple ink jet printheads such that their respective swaths are vertically and horizontally aligned with respect to the substrate. The process of vertically and horizontally aligning these swaths on the substrate to form one image is commonly referred to as “stitching”. 
     Stitching the multiple ink jet swaths down to the pixel level in order to obtain sub pixel resolution is extremely challenging. Mechanical alignment is the most common method of aligning the printheads to achieve stitching of the swaths. Utilizing micrometer adjustment and measurement devices on the x and y axes, the position of the printheads can be adjusted to approach sub pixel resolution. However, such alignment is only useful for a particular ink viscosity, temperature of the environment, humidity of the environment and print speed. Once any one of these variables changes, i.e., the viscosity of the ink changes, the pixel resolution will again become misaligned. Furthermore, even if the printheads are perfectly aligned, the piezoelectric crystals in each printhead will be driven at a slightly different frequency, thus causing beat frequency drift errors between the printheads which eventually leads to very visible alignment errors between the pixels of the different swaths. 
     Electronic alignment methods and mechanisms, while more flexible than mechanical alignment systems, also cannot achieve sub pixel resolution because of the piezo beat frequency drift errors, which will eventually cause drift between the printheads, independent of the mechanical and/or electronic methods and systems used for stitching the swaths together. 
     The problem of beat frequency drift errors is not limited to ink jet engines. As will be appreciated by those of ordinary skill in the art, similar errors may occur in other types of print engines that are linked together to print upon a single substrate or web. For example, magnetographic engines utilize magnetic recording heads to create a latent magnetic image on the surface of a revolving hard metal drum, which is then exposed to magnetic toner particles and transferred/fused to paper. The modulation frequency of the magnetic recording heads is controlled by a clock source, which may be slightly different on each of the print engines. Therefore, if a plurality of the magnetographic print engines are used in series to print a single image, the slight differences in the magnetic recording heads&#39; clock sources may cause slight (but perceptible) registration errors in the printed pixels of the image. Similar beat frequency errors may occur in LED engines, Ion deposition engines, laser engines, magnetographic, xerographic engines and the like. 
     Accordingly, a need exists for a system and method for simultaneously controlling the plurality of staggered ink jet printheads such that stitching between the swaths generated by the ink jet printheads can be easily accomplished electronically, regardless of the ink viscosity, print speed, temperature and humidity. Furthermore, a need exists for a system and method for synchronizing the piezo clock sources on each of the ink jet printheads to each other such that the stitching can be accomplished down to sub pixel levels without experiencing beat frequency drift errors between the pixel swaths. Furthermore, a need exists for a system and method for synchronizing clock sources controlling the deposition frequency of image pixels on print engines connected (in series, in parallel or otherwise) so as to eliminate beat frequency errors between the print engines. Finally, a need exists for a system and method for synchronizing the drive mechanisms of print engines controlled by a single controller so as to “lock-step” the transport mechanisms of the printers. 
     SUMMARY OF THE INVENTION 
     The present invention provides a system and method for simultaneously controlling a plurality of print engines connected (in series, in parallel, or otherwise) that facilitates electronic stitching between the print engines. More specifically, the present invention provides a system and method for synchronizing the pixel deposition frequencies between the various inter-connected print engines so as to eliminate beat frequency errors between the print engines. The present invention also provides a system and method for synchronizing the transport mechanisms of the inter-connected print engines so as to reduce overall errors and failures of the printing system. 
     In a specific embodiment, the present invention provides a system and method for simultaneously controlling a multitude of continuous-flow ink jet printheads which facilitates the electronic stitching between the ink jet printheads; and furthermore, the present invention provides a system and method for synchronizing the piezo clock sources on each of the ink jet printheads to each other such that the electronic stitching can be accomplished down to the pixel levels. 
     The method for synchronizing the pixel deposition frequencies between a plurality of print engines comprises the steps of: (a) coupling the plurality of print engines together with at least one printer controller, (b) embedding a first clock signal in data; (c) transmitting the data to the print engines; (d) each of the print engines receiving the data; (e) each of the print engines deriving a pixel deposition clock signal from the data received, which is directly proportional to the first clock signal; and (f) each of the print engines driving its corresponding pixel deposition mechanism with the pixel deposition clock signal. Accordingly, all of the pixel deposition clock sources will be synchronized in frequency with each other, eliminating beat frequency drift errors between the print engines. The pixel deposition mechanism, as apparent to those of ordinary skill in the art, includes the LED switching device for LED engines, the ion generating cartridge for Ion deposition engines, the magnetic recording heads for magnetographic engines, the piezoelectric crystal coupled to the ink-well push rod for ink jet printheads, and the like. 
     Preferably, the print engines and controller are connected together in a daisy-chain configuration and the method also includes the steps of: (i) determining the time it will take for the data to propagate to each of the print engines; and (ii) adjusting the phase of the second clock signal to reflect the propagation measurement. Accordingly, all of the pixel deposition clock signals will also be synchronized in phase as well as frequency to each other. 
     The above method is accomplished by operating a plurality of print engines with a high-speed raster printer controller. The type of print engine is not critical and a plurality of different print engine technologies can be used. Each print engine includes a customized communication circuit, which in the preferred embodiment is a separate circuit board, hereinafter referred to as a “target adapter board” (“TAB”). The TAB provides a direct interface between the print engine electronics and the controller. The controller and each TAB includes a serial data input port and a serial data output port. The controller is attached to the plurality of TABs in a daisy-chained ring configuration, such that the controller will transmit commands and data to the first TAB on the daisy-chain, and the commands and data will flow in the same direction along the daisy-chain to the rest of the TABs, and will eventually flow back to the controller. Furthermore, the controller is adapted to transmit rasterized bitmap image data to the TABs, and in turn to the print engines, in an on-demand manner. The daisy-chained serial communication ring configuration of the controller and the plurality of TABs is hereinafter referred to as “the ring.” 
     The ring configuration allows all of the TABs to see all of the data all of the time. This also provides a clean mechanism for the raster printer controller to receive status from all of the print engines with minimal cabling requirements. Furthermore, use of fiber optic links in the ring provides high bandwidth data transfer capabilities, excellent electrical isolation and immunity from excessive high voltages associated with print engine electronics. 
     The raster printer controller has a multiplexed command/data-stream protocol structure at its fiber optic interface in which the controller transmits a command followed by the associated data. The controller initiates all commands, and manages the allocation of fiber optic band-width to receive all print engine status. Each TAB is adapted to listen for commands addressed to it, and responds appropriately; and further, the TAB never responds unless commanded by the controller. Nevertheless, each TAB must retransmit the entire command/data-stream it receives on its fiber optic input port back to its fiber optic output port, and in turn, to the next TAB on the ring. This allows all of the TABs to see all of the controller commands and data, all of the time. 
     Each TAB includes a fiber optic receiver/decoder, a fiber optic encoder/transmitter, a standard discrete output bus, a standard discrete input bus, a print engine instruction register, print engine status register, a bitmap data memory storage, a stroke rate counter and associated stroke rate count preload register, a high-speed fiber optic message processing circuit, and an on-board CPU. Therefore, each TAB essentially includes all the necessary print engine components. 
     The CPU and message processing circuit are adapted to manage the incoming and outgoing commands, to manage the TAB&#39;s hardware, and to provide an interface to the print engine electronics. The message processing circuit monitors the fiber optic input and executes the commands transmitted by the raster printer controller if the commands are addressed to it. The message processing circuit also continuously retransmits the commands/data-stream back to the fiber optic encoder/transmitter, supports the general purpose discrete output bus and instruction register in response to the commands, reads the general purpose discrete input bus and print engine status register which can be incorporated into messages sent directly to the raster printer controller as status, and also manages the data update of the bitmap data memory storage when commanded by the raster printer controller. 
     The raster printer controller&#39;s multiplexed command/data protocol scheme allows the raster printer controller to transmit bitmap data to the print engines in any order and at any time, thus providing print-on-demand capabilities to the print engines; allows the controller to embed a “Print Trigger” command within the command/data stream at any time thus providing real-time print trigger generation to the print engines; and allows the controller to embed a stroke rate signal within the command/data stream indicative of the web velocity and/or acceleration. 
     The command/data stream is transmitted over the fiber optic ring utilizing a self-clocking data transmission code such as 8B/10B code. The fiber optic encoder on the raster printer controller embeds a clock signal into the command/data stream by encoding the raw data. This allows the fiber optic decoders on each of the TAB boards to extract the embedded digital clock signal from the encoded data and to decode the command/data stream back into its raw data. 
     The extracted digital clock is used by each TAB to generate the pixel deposition clock signal for driving the pixel deposition mechanism on its corresponding print engine. Because each extracted clock signal will have the exact frequency (directly proportional to the clock signal embedded by the raster printer controller), each pixel deposition clock signal generated from the external clock source will also have the exact frequency. 
     Preferably, the pixel deposition clock signal is generated as follows: The extracted digital clock drives a free running counter whose count output is sent to a memory device which acts as a lookup table. The lookup table includes a voltage amplitude value for every count input. The voltage amplitude values in the lookup table each correspond to a particular voltage amplitude level in one period of the pixel deposition clock signal&#39;s sinusoidal wave, square wave and the like. Thus, the memory device will output the particular voltage amplitude value from the lookup table, depending upon the count input received from the counter; therefore, for each cycle through the counter, the voltage amplitude values corresponding to one period of the pixel deposition clock signal&#39;s output will be output from the lookup table. The voltage amplitude value is sent to a digital-to-analog converter, the amplified output of this digital-analog converter is the analog clock source for the pixel deposition clock signal. 
     To reset the counters, the raster printer controller will broadcast a CLOCK RESET command to the first TAB on the ring. The first TAB will receive this command and restart its counter to start generating its pixel deposition clock signal. As discussed above, the first TAB will also pass this command to the next TAB on the ring; which will restart its counter in response to the command and will in turn pass the command to the next TAB on the ring. This is repeated until the command is passed back to the raster printer controller. 
     Because it will take time for the a CLOCK RESET command to propagate to each TAB on the fiber optic ring, the present invention includes a method to assure that all the pixel deposition clock signals are synchronized in phase as well as frequency. Thus, each counter includes a preload input coupled to a phase-shift preload register. Each phase-shift preload register will be initialized by the raster printer controller during the boot-up process to a count pre-set value which corresponds to the time it takes for the CLOCK RESET command to reach the particular TAB. Thus, even though each pixel deposition clock signal will be started at progressively different instances, each phase-shift preload register is set to a particular count value to assure that the output voltage level of the piezoelectric clock source of a given TAB upon receiving the CLOCK RESET command is at the same voltage amplitude levels of all pixel deposition clock signal started prior to the present one. 
     Each pixel deposition clock signal is therefore locked in both phase and frequency to each other. 
     In a specific embodiment of the present invention, a method for synchronizing the plurality of piezoelectric crystals on a corresponding plurality of ink jet printheads comprises the steps of: (a) coupling the plurality of printheads together with a printer controller, (b) embedding a first clock signal in data; (c) transmitting the data to the printheads; (d) each of the printheads receiving the data; (e) each of the printheads deriving a second clock signal from the data received, which is directly proportional to the first clock signal; and (e each of the printheads driving its corresponding piezoelectric crystal with the second clock signal. Accordingly, all of the piezoelectric crystal clock sources will be synchronized in frequency with each other, eliminating beat frequency drift errors between the printheads. 
     The method for synchronizing or “lock-stepping” a plurality of print engines comprises the steps of: (a) coupling the plurality of print engines together with at least one printer controller, (b) embedding a first clock signal in data; (c) transmitting the data to the print engines; (d) each of the print engines receiving the data; (e) each of the print engines deriving a drive clock from the data received, which is directly proportional to the first clock signal; and (f) each of the print engines driving its corresponding drive mechanism with the drive clock. 
     Accordingly, it is an object of the present invention to provide print system with multiple print engines which can dispatch rasterized bitmap data to the print engines in an on-demand manner; which can transmit print trigger and stroke rate information to the print engines at any time; which synchronizes the pixel deposition clock signals for each print engine to a single clock source; which synchronizes the pixel deposition clock signals for each print engine in both phase and frequency; and which provides a system which facilitates electronic stitching of the print engines down to the pixel level. These and other objects will be apparent from the following description, the accompanying drawings and the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a  is a block diagram representation of the present invention, depicting a plurality of print engines coupled together in a daisy-chain ring configuration with a printer controller; 
     FIG. 1 b  is a block diagram of a specific embodiment of the present invention, depicting a plurality of ink jet print heads arranged in a staggered array to print upon a web and controlled by a single printer controller, the ink jet printheads and the controller being coupled in a daisy-chain ring configuration; 
     FIG. 2 is a schematic block diagram of a print engine communication device for use with the present invention; 
     FIG. 3 is a schematic block diagram of a stroke machine circuit for use with the present invention; 
     FIG. 4 is a schematic block diagram of an alternate arrangement of the printer controllers and print engines; and 
     FIG. 5 is a block diagram representation of a print engine (such as an ion-deposition, LED or magnetographic print engine) for use with the present invention. 
    
    
     DETAILED DESCRIPTION 
     As shown in FIG. 1 a , at least one high speed raster printer controller  10  is used to simultaneously drive a plurality of print engines  12   a - 12   c  each of which are to print portions of an image onto a substrate  14  moving through each of the print engines in the direction indicated by arrow A. In a specific embodiment, as shown in FIG. 1 b , the plurality of print engines is a plurality of ink jet printheads  12   a - 12   d  each of which have a nozzle array  13   a - 13   d  for ejecting strokes of ink to a substrate or web  14  moving in a vertical direction indicated by arrow A. The ink jet printheads  12   a - 12   d  are positioned in a staggered formation along the web  14  and each ink jet printhead is controlled by the controller  10  to transfer a corresponding swath  16   a - 16   f  of an image  18  to the web  14 . 
     The print engines  12 , may include an LED engine, an ion deposition engine, a xerographic engine, a magnetographic engine, a laser engine, an ink jet engine or any other type of high-speed print engine, or any combination of such engines, as is known to those of ordinary skill in the art. With each of these high speed print engines, a pixel deposition mechanism is utilized, which includes a clock input for providing a pixel deposition frequency. As shown in FIG. 5, at least with LED engines, ion deposition engines and magnetographic engines, the pixel deposition mechanism  6 , includes a source  7  of a pixel deposition clock signal for providing a deposition frequency for the mechanism  6 . The pixel deposition mechanism  6  is controlled to transfer a latent image on a rotating drum  8 . Toner particles are transferred onto the latent image by a toner supply  9 , which are then transferred onto the paper or substrate  14  in the form of the final image. Motorized drive mechanisms  11  are used to drive the paper through the printer at a controlled speed. The speed of the rotating drum  8  is synchronized with the drive mechanisms  11 , and is essentially a drive mechanism itself. In LED engines, the pixel deposition mechanism includes an array of LEDs  6  and a switching device for switching the arrays on and off for creating the latent image on a revolving charged drum  8 . In magnetographic engines, the pixel deposition mechanism is a plurality of magnetic recording heads  6  that are selectively energized to create the latent magnetic image on the surface of the revolving hard metal drum  8 . In ion deposition engines, the pixel deposition mechanism is an ion generating cartridge  6  which digitally creates the latent image on the rotating dielectric drum  8 . 
     The pixel deposition mechanism for ink jet print heads, discussed above in detail, includes an ink chamber having a multitude of nozzle orifices, aligned in an array, for emitting a corresponding multitude of fluid ink streams, commonly referred to as an array of ink. Pressure is created by a push rod to force the ink from the ink chamber and through an array of nozzle orifices. A piezoelectric crystal is coupled to the ink-well push rod so as to create a high frequency ultrasonic vibration to the push rod and, in turn, to the ink stored in the ink chamber. This high frequency vibration in the ink chamber causes the ink droplets to emerge from the nozzles at the same frequency. 
     Referring to FIGS. 1 a  and  1   b , the high speed raster printer controller  10  is preferably a multi-processor system for interpreting and processing an image or images defined by a page description language and for dispatching rasterized bitmap data generated by the processing of the page description language as described, for example, in U.S. Pat. No. 5,796,930. Each print engine or printhead  12   a - 12   d  is coupled to one of a plurality of print engine communication circuits, which preferably reside on individual circuit boards, hereinafter referred to as “target adapter boards” (“TAB”)  20   a - 20   d . For the purposes of this disclosure, when it is disclosed that one component is “coupled” to another component, it will mean that the one component is linked to the other component by any data link such as an electronic data link (wires or circuits), a fiber optic data link, an RF (radio frequency) data link, infrared data link, an electromagnetic data link, or any other type of data link known to one of ordinary skill in the art. 
     Each TAB  20   a - 20   d  provides an interface between the raster printer controller  10  and the respective plurality of print engines  12   a - 12   d . Preferably each TAB includes a universal controller interface section to provide a means to communicate with the raster printer controller  10 ; and a customized print engine interface section which provides a direct interface between the print engine electronics and the raster printer controller  10 . 
     The raster printer controller  10  includes a serial data output port  22  and a serial data input port  24 . The output port  22  is preferably a fiber optic transmitter and the input port  24  is preferably a fiber optic receiver. Each of the TABs  20   a - 20   d  also include a serial data input port  26  and a serial data output port  28  (see FIG.  2 ); where the input port  20  is preferably a fiber optic receiver and the output port is preferably a fiber optic transmitter. Therefore, both the raster printer controller  10  and the plurality of TABs  20   a - 20   d  each have duplex communications via fiber optics. 
     As is further shown in FIGS. 1 a  and  1   b , the raster printer controller  10  is coupled to the plurality of TABs  20   a - 20   d  in a daisy-chain configuration; and furthermore, the last TAB  20   d  on the daisy-chain is coupled again to the raster printer controller to form a daisy-chain “ring”. The raster printer controller  10  transmits a command/data stream to the first TAB  20   a  on the ring over a serial data link, which is preferably a fiber optic link  30 ; the last TAB  20   d  on the ring transmits command/data stream back to the raster printer controller  10  over a serial data link, which is preferably a fiber optic link  32 ; and each of the TABs  20   a - 20   c  transmit command/data stream to the next TAB on the ring, over serial data links, which are preferably fiber optic links  34   a - 34   c . The data output port  22  of the raster printer controller  10  transmits coded data serially over the fiber optic link  30 . The data is encoded from raw digital data by an encoder device  35 . The raw digital data is passed over a parallel data line to the encoder device  35  from the control circuitry  37  of the raster printer controller. The data input port  24  receives the coded data back from the fiber optic link  32 . This data is then decoded back into raw digital data by a decoder device  39 . The raw digital data is then passed on to the control circuitry  37  of the raster printer controller in parallel form. The fiber optic links  30 ,  32 ,  34   a - 34   c  provide substantial electrical isolation and immunity from excessive high voltages associated with print engine electronics and the fiber optic links are scalable, i.e., their data rates can be easily slowed down if desired. 
     As will be discussed in significant detail below, the a printer controller embeds a first clock signal (from a first clock source  73 ) in data and transmits the data to the fiber optic ring. Each TAB  20   a - 20   d  on the fiber optic ring derives a pixel deposition clock signal  68  from the data received, which is directly proportional to the first clock signal. Finally, each of the print engines  12   a - 12   d  drives its corresponding pixel deposition mechanism  6   a - 6   d  with the pixel deposition clock signal  68 . Accordingly, all of the pixel deposition clock sources will be synchronized in frequency with each other, eliminating beat frequency drift errors and/or other synchronization errors between the print engines. It is within the scope of the invention that pixel deposition clock signal be used to synchronize the drive mechanisms  11 , 8  between the print engines, thereby “lock-stepping” the operations of the various print engines together. 
     It should be apparent to one of ordinary skill in the art, that while fiber optic links are preferred for the present embodiment of the invention, it is within the scope of the invention to utilize any other type of serial data link capable of performing applications described herein. For example, the fiber optic links could be replaced with coax or twisted pair links. 
     Furthermore, while the above daisy-chain ring configuration is preferred, it is within the scope of the invention to couple the controller  10  to the plurality of TABs  20   a-d  in a configuration (daisy-chain or otherwise) which is not configured as a ring. For example, as shown in FIG. 4, it is within the scope of the invention to couple the printer controller  10 ′ to the plurality of print engines  12 ′ in a “star” or “spoked wheel” configuration where the controller  10 ′ will be at the “hub” and is coupled to each of the print engines  12 ′ separately with individual data links  200 . As is also shown in FIG. 4, it is also within the scope of the invention to utilize print engine communication circuits  20 ′ to interface between the controller  10 ′ and one or a plurality of print engines  12 ′ in the “star” configuration. 
     The preferred daisy-chained serial configuration of the raster printer controller and plurality of TABs is hereinafter referred to as “the ring.” 
     Each TAB is configured to transmit the entire command/data stream received on its input port  26  back to its output port  28 . Accordingly the raster printer controller  10  will transmit the command/data stream to the first TAB  20   a  on the ring and the command/data stream will flow in the same direction along the daisy-chain to the rest of the TABs  20   b - 20   d , and eventually will flow from the last TAB  20   d  on the ring back to the raster printer controller  10 . This configuration allows all the TABs to see all the command/data stream all of the time. 
     As shown in FIG. 2, each TAB  20  includes a digital decoder  36  for decoding the data stream received by the fiber optic receiver  26  into raw digital input data on the input data bus  38 , and a digital encoder  40  for transforming the raw digital output data on the output data bus  42  into an encoded data stream to be transmitted by the fiber optic transmitter  28 . Also included on each TAB is a high-speed message processing circuit  44 , coupled between the decoder  36  and encoder  40 . The high-speed message processing circuit  44  is designed to monitor the digital input data on the input data bus  38  and to execute the commands embedded in the command/data stream when the embedded TAB address field matches the TAB&#39;s internal address. The high speed message processing circuit  44  also continuously retransmits this digital input data to its fiber optic encoder  40  as digital output data on the output data bus  42 , which is in turn transmitted to the next TAB on the ring (or back to the raster printer controller if the present TAB is the last TAB on the ring) by the fiber optic transmitter  28 . 
     Preferably, the high-speed message processing circuit  44  is a non-intelligent device, that is, it is a “hardware” device whose internal functions are not directed by a software program. Therefore the high-speed message processing circuit is very fast and is able to handle the bandwidth requirements for the multiplexed command/data protocol structure described below. Furthermore, the high-speed message processing circuit  44  is not as susceptible to the errors and failures which may commonly occur in software controlled devices. The high-speed message processing circuit  44  may be fabricated from standard TTL devices, CMOS devices, 7400 series logic, or incorporated into single or multiple chip implementations such as programmable logic arrays (PALs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs) or any hardware description language (HDL) based device; and in a preferred embodiment, the high-speed message processing circuit  44  is an ASIC device. 
     The high-speed message processing circuit  44  is coupled to a discrete output buffer  46  and a discrete input buffer  48  via a data busses  50 , 51 , respectively. In executing commands transmitted by the raster printer controller, the high-speed message processing circuit  44  can set or reset lines on the discrete output buffer  46  and can report back to the raster printer controller messages pertaining to the status of lines on the discrete input buffer  48 . Such output discretes can include, for example, “print on-line,” “printer reset,” and “reset communications.” Such input discretes can include, for example, “engine error.” Thus, the discrete buffers provide a mechanism for handling general purpose I/O requirements of print engine. 
     The TAB  14  also includes a bitmap data transfer circuit  57  which includes a bitmap data memory storage buffer  52  for interfacing directly to the corresponding print engine&#39;s video data input port  54 . Therefore, the message processing circuit  44  is also designed to update the bitmap data memory storage buffer  52  when commanded by the raster printer controller  10 . This bitmap data memory storage buffer, in the preferred embodiment, is a FIFO buffer; however, the bitmap data memory storage buffer  52  may also be video memory, a single byte of memory (i.e., a register), a dram array, or any other type of memory device as required by the design of the print engine interface. Therefore, the message processing circuit will update the bitmap memory storage buffer  52  by activating a “FIFO memory write” signal  55  coupled to the memory storage buffer. For at least ink jet applications, the transfer circuit  57  also includes a multiplexor device  56  coupled between the ink jet printhead&#39;s video data input port  54  and the bitmap data memory storage buffer  52  for injecting NULL data between the vertical swaths of bitmap data. 
     The TAB includes an optional on-board CPU  58  which is used to manage higher level tasks as warranted by some types of print engines; a control port  60  controlled by the message processing circuit  44  or the on-board CPU  58 , which can be used as part of the print engine interface to transmit ink print engine instructions (otherwise known as “print engine commands”) and instruction parameters (otherwise known as “print engine command parameters”) to the print engine; and an print engine status buffer  62  monitored by the message processing circuit  44  or the on-board CPU  58 , which can be used to access print engine status information from the print engine. The CPU  58 , the control port  60  and the status port  62  are coupled to each other by a bidirectional data bus  61 . 
     At least in ink jet applications, the TAB also includes a Stroke Machine  63 , coupled to the bidirectional data bus  61 , for determining when to transfer a scanline (“stroke”) of the bitmap data from the memory storage buffer  52  to the ink jet printhead&#39;s video data input port  54 . This is accomplished by the activation of a “FIFO memory read” signal  64  by the Stroke Machine  63 . The stroke machine  63  provides a video data control signal  65  to the ink jet printhead  12  and controls the multiplexor  56  through a multiplexor control signal  66 . Furthermore, as will be described in further detail below, the stroke machine  63  generates the pixel deposition clock signal  68  for driving the piezoelectric crystal  70  on the corresponding ink jet printhead  12 . 
     Each digital decoder  36  derives an extracted digital clock signal  72  from the command/data stream transmitted by the raster printer controller  10  over the fiber optic data links  30 ,  32 ,  34   a-c  to the ring. The command/data stream is transmitted by the raster printer controller  10  over the fiber optic ring utilizing a self-clocking data transmission code as commonly known to one of ordinary skill in the art, such as the 8B/10B encoding algorithm as described in U.S. Pat. Nos. 4,486,739 and 4,665,517. The 8B/10B code is a block code which encodes 8-bit data blocks into 10-bit code words for serial transmission. The devices supporting this 8B/10B standard range in frequency from 125 MHZ to 1.5 GHz (today), with future enhancements up to 2 to 4 GHz. 
     The message processing circuit  44  includes a message processing state machine  76 , an address decrement device  78 , a bi-directional command data buffer circuit  80  which couples the bidirectional data bus  61  to the output data bus  42  (or input data bus  38 ), and a bidirectional discrete data circuit  82  which couples the discrete input and output buffers  48 ,  46  to the output data bus  42  (or input data bus  38 ). The bidirectional command data buffer circuit  80  includes an output data register  84 , fed by an output data buffer  86  which is controlled by the output data enable line  88  activated by the message processing state machine  76 . Likewise, the bi-directional command buffer circuit  80  includes an input data register  90 , for feeding an input data buffer  92  which is controlled by the input data enable line  94  activated by the message processing state machine  76 . The bidirectional discrete data circuit  82  includes an output discrete data buffer  96 , controlled by an output discrete data enable line  98 , activated by the message processing state machine  76 . Likewise, the bi-directional discrete data circuit  82  includes an input discrete data buffer  100 , controlled by an input discrete data enable line  102  which is activated by the message processing state machine  76 . The address decrement device  78  is controlled by a control line  104  activated by the message processing state machine  76 . 
     The discrete output buffer  46 , the discrete input buffer  48 , the bitmap data memory storage buffer  52 , and the other print engine interface components described above, controlled by the message processing state machine  76 , in response to commands embedded in the command/data stream sent over the ring, provide an interface between the print engines  12  and the fiber optic ring. Furthermore, this design allows the raster printer controller  10  to utilize a multiplexed command/data protocol for communicating with the plurality of TABs  20   a - 20   d , in which the raster printer controller transmits a command followed by a corresponding data-stream on the fiber optic ring. 
     The raster printer controller  10  initiates all commands and manages the allocation of fiber optic bandwidth to receive all print engine discretes and status. Each command contains an address field, and each TAB includes its own internal address. Thus, each TAB  20   a - 20   d  monitors the commands using their respective high-speed message processing circuits  44 , and if addressed, the TABs respond appropriately. A TAB  20   a - 20   d  will never respond to a command unless that particular TAB is addressed by the command or unless the command is a “broadcast” command (i.e., a particular bit of the address field could be reserved for as a broadcast bit) intended to be processed by all of the TABs. Nevertheless, as discussed above, even if the particular TAB is not addressed by the command, its message processing circuit  44  will always retransmit that command and corresponding data-stream to the next TAB on the daisy-chain (or if the present TAB is the last TAB  20   d  on the daisy-chain, back to the raster printer controller). This allows all TABs  20   a - 20   d  to see all of the commands all of the time 
     Referring to FIGS. 1 and 2, the encoder device  35  on the raster printer controller  10  embeds a digital clock signal derived from an internal clock source  73  into the encoded data transmitted on the ring. The digital decoding devices  36 , utilized by each TAB, derive the extracted digital clock signal  72  from the encoded data received on the input port  26  utilizing an on-chip data tracking phase locked loop “PLL” as is known to one of ordinary skill in the art. Therefore, each extracted digital clock signal  72  on each of the TABs  20   a-d , will have substantially the exact frequency, or a frequency that is exactly proportional to, the controller&#39;s internal clock source  73 . Therefore, because this extracted digital clock signal  72  is used to create the piezoelectric clock source  66  as described in detail below; each piezoelectric clock source  66  on each TAB will have substantially the exact frequency, eliminating beat frequency drift errors between the pixel swaths. 
     In one embodiment, the encoder device  35 , utilized by the raster printer controller  10 , and the digital encoders  40 , utilized by the TABs  20   a-d , are CY7B923 HOTLink™ Transmitter devices available through Cypress Semiconductor Corp. (HOTLink is a trademark of Cypress Semiconductor Corp.). These devices convert the 8-bit raw digital data blocks into 10-bit code words which are subsequently transmitted on the ring. The decoder device  39 , utilized by the raster printer controller  10 , and the digital decoders  36 , utilized by the TABs  20   a-d , are CY7B933 HOTLink™ Receiver devices also available through Cypress Semiconductor Corporation. These devices receive the 10-bit coded data, and using a completely integrated PLL clock synchronizer, recover the timing information, in the form of the extracted digital clock signal  72 , necessary for reconstructing the 8-bit raw digital data. The digital encoder  35  of the raster printer controller  10  utilizes the on-board clock source  73  as the byte rate reference clock “CKW” which is used by the encoder to create a bit rate clock embedded into the 10-bit coded data stream transmitted to the fiber optic ring. An on-board clock source  74  is used by the digital decoders  36  as a clock frequency reference (“REFCLK”) for the clock/data synchronizing PLL which tracks the frequency of the incoming bit stream and aligns the phase of its internal bit rate clock to the serial data transmissions. The extracted digital clock signal output  72  is the byte rate clock output of the digital decoders  38 , which is aligned in phase and frequency to the on-board clock source  73  of the raster printer controller. The operation and design of the HOTLink™ CY7B923/933 devices is described in detail in the HOTLink™ User&#39;s Guide (Copyright 1995, Cypress Semiconductor Corp.); and in particular, the CY7B923/933 Datasheet section (pp.1-28) of the User&#39;s Guide, the disclosure of which is incorporated herein by reference. 
     As shown in FIG. 3, in ink jet applications, the stroke machine  63  generates the pixel deposition clock signal  68  for driving the piezoelectric crystal  70  on the corresponding ink jet printhead  12 . It will be apparent to those of ordinary skill in the art that, with simple modifications, the design of the stroke machine described herein for ink jet applications can be used to generate the pixel deposition clock signal  68  for all other printing applications such as magnetographic, ion deposition, xerographic, laser, LED and the like. The stroke machine  63  includes a pixel deposition clock generation circuit  110 , a stroke frequency generation circuit  112 , a dispatch control circuit  114 , and a registration control circuit  116 . The extracted digital clock signal  72 , a 25 MHz signal in the present embodiment, is used by the pixel deposition clock generation circuit to generate the pixel deposition clock signal  68  for driving the piezoelectric crystal  70  on the corresponding ink jet printhead  12 . 
     The extracted digital clock signal  72  drives a digital counter  118 . The MSB  120  of the output count value is the clock used by the stroke frequency generation circuit  112 , the dispatch control circuit  114 , and the registration control circuit  116 . The other bits  122  of the output count value are sent to a memory device  124  which operates as a lookup table. The lookup table includes a voltage amplitude value for every count value  122  received. These voltage amplitude values  126  are sent to a digital-to-analog converter  128  which converts the voltage amplitude values  126  to their corresponding analog voltages  130 . To obtain the pixel deposition clock signal  68 , a voltage amplifier device  132  is used to amplify the analog voltages  130  to the voltage levels required for the pixel deposition clock source. 
     The voltage amplitude values  126  output by the memory device  124  are derived from the lookup table. The lookup table contains a particular voltage amplitude value  126  corresponding to a particular voltage amplitude level in one period of the pixel deposition clock signal&#39;s sinusoidal wave. Thus, the memory device  124  will output the particular voltage amplitude value  126  from the lookup table, depending upon the count value  122  received from the counter  118 . For example, if the count value is a five-bit value (0-31), as in the present embodiment, the lookup table will have thirty-two voltage amplitude values (for transmitting to the digital-to-analog converter  128 ) corresponding to thirty-two uniformly spaced-apart output voltages along a 5 v peak-to-peak (the peak-to-peak voltage output from the digital-to-analog converter is selected depending upon the level of amplification desired to reach the 60V peak-to-peak pixel deposition clock source signal) sinusoidal period as shown in the table below: 
     
       
         
               
               
               
             
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Count 
                 Output 
               
               
                   
                 Value 
                 Voltage 
               
               
                   
                 (122) 
                 (130) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 0 
                 0.0 
                 V 
               
               
                   
                 1 
                 1.01 
                 V 
               
               
                   
                 2 
                 1.97 
                 V 
               
               
                   
                 3 
                 2.86 
                 V 
               
               
                   
                 4 
                 3.62 
                 V 
               
               
                   
                 5 
                 4.24 
                 V 
               
               
                   
                 6 
                 4.69 
                 V 
               
               
                   
                 7 
                 4.94 
                 V 
               
               
                   
                 8 
                 4.99 
                 V 
               
               
                   
                 9 
                 4.84 
                 V 
               
               
                   
                 10 
                 4.49 
                 V 
               
               
                   
                 11 
                 3.95 
                 V 
               
               
                   
                 12 
                 3.26 
                 V 
               
               
                   
                 13 
                 2.43 
                 V 
               
               
                   
                 14 
                 1.50 
                 V 
               
               
                   
                 15 
                 0.51 
                 V 
               
               
                   
                 16 
                 −0.51 
                 V 
               
               
                   
                 17 
                 −1.50 
                 V 
               
               
                   
                 18 
                 −2.43 
                 V 
               
               
                   
                 19 
                 −3.26 
                 V 
               
               
                   
                 20 
                 −3.95 
                 V 
               
               
                   
                 21 
                 −4.49 
                 V 
               
               
                   
                 22 
                 −4.84 
                 v 
               
               
                   
                 23 
                 −4.99 
                 V 
               
               
                   
                 24 
                 −4.94 
                 V 
               
               
                   
                 25 
                 −4.69 
                 V 
               
               
                   
                 26 
                 −4.24 
                 V 
               
               
                   
                 27 
                 −3.62 
                 V 
               
               
                   
                 28 
                 −2.86 
                 V 
               
               
                   
                 29 
                 −1.97 
                 V 
               
               
                   
                 30 
                 −1.01 
                 V 
               
               
                   
                 31 
                 0.0 
                 V 
               
               
                   
                   
               
             
          
         
       
     
     In the present embodiment, a frequency divider device  134  is inserted before the digital counter  118  to further reduce the frequency of the extracted digital clock signal  72  from 25 MHz to 3.2 MHz. Accordingly, the pixel deposition clock signal  68  for the piezoelectric crystal  70  will have a frequency of {fraction (1/32 )}the frequency of the divided-down digital clock signal  136  (i.e., in the present embodiment, the pixel deposition clock signal  68  will have a frequency of 100 KHz). 
     The extracted digital clock signal  72  is thus used by each TAB  20   a - 20   d  to generate the pixel deposition clock signal  68  for driving the pixel deposition mechanism and/or its drive mechanism on its corresponding print engine  12   a - 12   d . Therefore, because each extracted digital clock signal  72  on each of the TABs  20   a-d  will have substantially the exact frequency, as discussed above, synchronization errors between the print engines will be virtually eliminated. 
     The present invention also includes a system and method to eliminate any phase offset errors between all of the pixel deposition clock signals  68 . As discussed above, the embedded command in the command/data stream transmitted on the ring by the raster printer controller  10  includes an address field, which specifies which TAB is to receive the command. However, in the preferred embodiment every TAB is set up with an identical predefined internal address of zero (address=0); and further, every TAB is configured to modify the address field of every command received by decrements the address field by one prior to retransmitting the command/data stream back to the ring. Thus, for example, if there are four TABs on the ring, and the raster printer controller intends to transmit a command to the fourth TAB on the ring, the address field of the command sent to the first TAB on the ring will equal three. The first TAB will not accept the command because the address field does not equal zero. The first TAB will subtract one from the address field, and it will then retransmit the command to the second TAB on the ring. The second TAB will not accept the command because the address field does not equal zero (address field now equals two). The second TAB will subtract one from the address field, and it will then retransmit the command to the third TAB on the ring. This is repeated for each TAB until the command finally reaches the fourth TAB on the ring. At this time, the address field equals zero, and therefore, the fourth TAB on the ring will accept and process the command. Because the fourth TAB does not know that it is the last TAB on the ring, it will also decrement the value of the address field prior to retransmitting the command back to the raster printer controller. 
     When the raster printer controller  10  boots up, it does not know the number of TABs  20   a - 20   d  on the ring. Accordingly, the raster printer controller will send an initialization command to the ring. The address field of this initialization command will be decremented by each of the TABs on the ring; and thus, upon receiving the initialization command back from the ring, the raster printer controller will be able to determine the number of TABs on the ring and it will know how to address each of the TABs based upon the number of times the address field has been decremented prior to receiving the initialization command back from the ring. 
     The pixel deposition clock generation circuit  110  includes a preload register  138  coupled to the load port  140  of the digital counter  118  and updatable by the raster printer controller  10  via commands transmitted on the ring. As shown in FIGS. 2 and 3, the state machine  76  for controlling the operations of the message processing circuit  44 , includes a counter reset line  142 , coupled to the reset port  144  of the digital counter  118 . The preload register  138  stores a preload count which the digital counter  118  will start counting from upon being reset by the state machine  76 . 
     During boot-up, the raster printer controller will send a PHASE SYNC command to each TAB on the ring. This command will instruct the state machine  76  to fill the preload register  138  with the count value contained in the associated data sent with the PHASE SYNC command. The count value loaded into the preload register  138  will correspond to the number of counts the digital counter  118  will count in the time required for a command to propagate from the first TAB  20   a  on the ring to the present TAB. Thus, in the present embodiment, the preload register  138  of the first TAB  20   a  will be set to 0; in the present embodiment, if the time required for a command to propagate from the first TAB  20   a  to the second TAB  20   b  on the ring is 1.25 micro-seconds, the preload register  138  for the second TAB will be set to  4  (which corresponds to the number of counts that the digital counter  118 , counting at 3.2 MHz, will count in 1.25 micro-seconds); in the present embodiment, if the time required for a command to propagate from the first TAB  20   a  to the third TAB  20   c  on the ring is 2.50 micro-seconds, the preload register  138  for the second TAB will be set to 8 (which corresponds to the number of counts that the digital counter  118 , counting at 3.2 MHz, will count in 2.50 micro-seconds); and, in the present embodiment, if the time required for a command to propagate from the first TAB  20   a  to the fourth TAB  20   d  on the ring is 3.75 micro-seconds, the preload register  138  for the second TAB will be set to 12 (which corresponds to the number of counts that the digital counter  118 , counting at 3.2 MHz, will count in 3.75 micro-seconds). 
     Preferably, to allow for any number of print engines to be coupled to the ring at any one time, each fiber optic link between the TABs  20 , will have the same length. Thus, the time it takes for a command to propagate from one TAB to the next will always be equal and deterministic; and the preload register  138  preload setting will be calculated by the raster printer controller  10  as directly proportional to the position that a particular TAB will have on the ring (i.e., whether a particular TAB is the first, second, third, etc. TAB on the ring). 
     To reset the digital counters  138  to their respective preload values, the raster printer controller will broadcast a CLOCK RESET command to the ring. The CLOCK RESET command will, of course first be received and executed by the message processing circuit  44  of the first TAB  20   a  on the ring. The state machine  76  of the first TAB&#39;s message processing circuit will, in response to the CLOCK RESET command, will activate the counter reset line  142 , which in turn resets the counter  118  to start counting at its corresponding preload value, read from its corresponding preload register  138 . The first TAB will then pass the command to the next TAB  20   b  on the ring. Likewise, each successive TAB, upon receiving this command will reset its counter  118  to start counting at its corresponding preload value, read from its corresponding preload register  138 ; and the will then pass the command to the next TAB on the ring, until the command is eventually passed back to the raster printer controller  10 . Because each preload register  138  on each TAB is set to an initial count value corresponding to the time it takes for the command to propagate to the respective TAB, the voltage levels  130  output from the digital-to-analog converter  128  on all the TABs will be equal at any given time. Thus, in addition to each piezoelectric clock source being locked in frequency as described above, each piezoelectric clock source will also be locked in phase. 
     As shown in FIG. 3, the stroke frequency generation circuit  112 , includes a stroke clock counter  146  and a stroke rate preload register  148  updatable by the raster printer controller  10 . The terminal count output  149  of the stroke clock counter  146  is the stroke clock signal  150  sent to the registration circuit  116  and the dispatch circuit  114 . A typical stroke frequency is approximately 50 Khz. The 50 Khz stroke signal could be embedded into the command/data protocol and sent to each of the TABs; however, this would impair the bandwidth capabilities of the command/data protocol. Therefore, the raster printer controller will send a command within the command/data stream to each of the TABs on the ring at a 1 or 2 Khz rate indicative of the web velocity and/or acceleration. Based upon this velocity/acceleration data in the command, the microcontroller  58  will calculate a preload value to load into the stroke rate preload register  148  which is the accurate count of the number of piezo cycles between the dispatch of real bitmap data. The terminal count output  149  of the stroke clock counter  146  will activate every time the stroke clock counter  146  counts down from the preload value (stored in the preload register  148 ) to zero. All piezo cycles between the stroke periods get null data. Therefore, the stroke frequency generation circuit  112  provides an alternate approach to stroke clock generation when real-time shaft clock transmission over the fiber optic cable is not feasible. 
     The registration circuit  116 , the design of which is practical knowledge to those of ordinary skill in the art, controls the issuance of the Top of Form signal  152  based upon the stroke clock signal  150  and the piezo cycle frequency signal  120 . In generating the Top of Form signal  152 , the registration circuit may also take into account clamp distance values and/or flight delay values as updated by the raster printer controller  10  using the command/data protocol scheme of the present invention. 
     The dispatch circuit  114 , the design of which is practical knowledge to those of ordinary skill in the art, controls the issuance of the FIFO Memory Read signal  64  and the multiplexor control signal  66  (for injecting null data) based upon the stroke clock signal  150 , the Top of Form signal  152 , an End of Page signal  154  generated by the bitmap memory storage device  52 , and the piezo cycle frequency signal  120 . In generating the FIFO Memory Read signal  64 , the dispatch circuit may take into account drops-per-dot values and/or stroke width values as updated by the raster printer controller  10  using the command/data protocol scheme of the present invention. 
     In conclusion, the present invention provides a high-speed printer controller system which is configured to control and “lock-step” a multitude of print engines simultaneously, and which is also configured to synchronize, in frequency as well as phase, all of the pixel deposition mechanisms located within the print engines. Further, while the system and method described herein constitutes the preferred embodiments of the present inventions, it is to be understood that the present inventions are not limited to their precise form, and that variations may be made without departing from the scope of the invention as set forth in the following claims,