Abstract:
This invention discloses a digital to analog converter (DAC) for converting a digital signal with a predetermined number of bits to a corresponding analog signal, the DAC comprises a first current source element having a first control signal, the first control signal controlling the conduction current provided by the first current source element, and a second current source element having a second control signal, the second control signal controlling the conduction current provided by the second current source element, wherein the first and the second control signals have different voltages during operation of the DAC.

Description:
PRIORITY DATA 
       [0001]    The present invention claims priority to provisional patent application No. 61/051,514 filed May 8, 2008 entitled “DIGITAL TO ANALOG CONVERTER.” 
     
    
     BACKGROUND 
       [0002]    Various different kinds of digital to analog converters (DACs) are used to convert digital signals to analog signals. Binary weighted DAC&#39;s are used in many applications because they require relatively few components, and are thus relatively small. A binary weighted DAC includes a plurality of current or voltage generating elements. Each element corresponds to a bit of the incoming digital signal. The outputs of the different elements are weighted, based on the significance of their corresponding bits. Elements corresponding to more significant bits are weighted higher than elements corresponding to less significant bits. The sum of all of the outputs is equal to the output analog signal. Weighted binary DAC&#39;s are advantageous because they require a relatively small number of elements, and therefore can be implemented in a relatively small chip area. On the other hand, weighted binary DAC&#39;s often suffer from poor glitch performance. Also, to insure linear operation, the weighting of each element must be carefully tuned. 
         [0003]    Thermometer coded DACs address some of the problems of binary weighted DACs. A thermometer coded DAC first converts binary input into thermometer code. Following Table 1 illustrates a conversion between the binary code and the thermometer code. As an example seven thermometer coded bits are required to represent three binary bits. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Decimal 
                 Binary 
                 Thermometer code 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 2 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
               
               
                 3 
                 0 
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
               
               
                 4 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
               
               
                 5 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 6 
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                 7 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
               
               
                   
               
             
          
         
       
     
         [0004]    A thermometer code DAC includes a current or voltage generating element for each possible value of the incoming digital signal. A decoder receives the incoming digital signal and derives a thermometer code. The thermometer code is a digital signal having one bit for each possible value of the incoming digital signal. The number of asserted bits in the thermometer code is proportional to the value of the incoming digital signal. Each bit of the thermometer code is provided to a corresponding element. When a bit is asserted, the corresponding element generates an output (i.e., a current or voltage). Unlike those of binary weighted DAC&#39;s, all of the element outputs in a thermometer DAC are equal. The sum of the outputs over all of the elements is the output analog signal. Thermometer code DAC&#39;s have glitch properties more favorable than those of binary weighted DAC&#39;s and are simpler to calibrate. Because a separate element is required for each allowed value, however, thermometer code DAC&#39;s require many components and have a large chip area. 
         [0005]      FIG. 1  is a schematic diagram illustrating a current source section of a conventional binary and thermometer-coded hybrid DAC  100 . The hybrid DAC  100  has twelve bits. A binary  110  block converts the four least significant bits (LSBs) to analog currents, and a thermometer coded block  120  converts the eight most significant bits (MSBs) to analog currents. These analog currents are summed up to represent a converted analog signal. Specifically, the current source for the binary block  110  comprises four PMOS transistors B[0:3]. If the PMOS transistor B[ 0 ] for the LSB has one leg, i.e., M=1, the PMOS transistor B[ 1 ], B[ 2 ] and B[ 3 ] for the upper bits will have 2, 4 and 8 legs, respectively. Referring to  FIG. 1 , the number of legs is represented by the M number. The more the number of legs the larger the conduction current i[0:3]. Thereby, the PMOS transistor B[ 1 ] is twice as large in size and conduction current as the PMOS transistor B[ 0 ], i.e., i[ 1 ]=2*i[ 0 ]. Similarly, i[ 2 ]=2*i[ 1 ], and i[ 3 ]=2*i[ 2 ]. Then the binary block  110 , when all transistors are on, produces a total amount of current of 15*i[ 0 ]. 
         [0006]    Referring again to  FIG. 1 , the thermometer coded block  120  has 255 parallel connected PMOS transistors T[1:255] of identical sizes, i.e., all have 16 legs (M=16). Conduction current by any of the PMOS transistor T[1:255] is 16 times of the i[ 0 ], i.e., j=16*i[ 0 ]. A total current the 12-bit DAC  100  can produce equals then to (255*16+15)*i[ 0 ]=4095*i[ 0 ]. This means a current source area for the 12-bit DAC  100  occupies 4095 legs of the basic PMOS transistor B[ 0 ]. The thermometer coded DAC also requires a binary to thermometer code decoder. While the thermometer coded DAC improves accuracy and conversion speed of a DAC, it also takes up a larger chip area than a pure binary DAC and hence increases cost. 
         [0007]      FIG. 2  is a schematic diagram illustrating a current source section of an alternative conventional binary and thermometer-coded hybrid DAC  200 . The hybrid DAC  200  has also 12-bits. The 4-bit binary block  110  is the same as in  FIG. 1 . The eight most-significant-bits are divided into two thermometer coded blocks  220  and  230 . The thermometer coded block  220  converts two binary bits, and therefore, has three thermometer coded bits and employing three PMOS transistors S[1:3] having 16 legs, i.e., M=16. Their conduction current k=16*i[ 0 ]. The thermometer coded block  230  converts 6 most significant binary bits, and therefore has sixty three thermometer coded bits and employing sixty three PMOS transistors T[1:63]. M=64 for the PMOS transistors T[1:63], therefore, the conduction current of each transistor m=64*i[ 0 ]. A total current of the hybrid DAC  200  is (63*64+3*16+15)*i[ 0 ]=4095*i[ 0 ]. The hybrid DAC  200  occupies the same among of chip area as the hybrid DAC  100 . They both have the disadvantage of large chip area and high cost. 
       SUMMARY 
       [0008]    This invention discloses a digital to analog converter (DAC) for converting a digital signal with a predetermined number of bits to a corresponding analog signal. The DAC comprises a first current source element having a first control signal, the first control signal controlling the conduction current provided by the first current source element, and a second current source element having a second control signal, the second control signal controlling the conduction current provided by the second current source element, wherein the first and the second control signals have different voltages during operation of the DAC. 
         [0009]    The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The drawings accompanying and forming part of this specification are included to depict certain aspects of the invention. A clearer conception of the invention, and of the components and operation of systems provided with the invention, will become more readily apparent by referring to the exemplary, and therefore non-limiting, embodiments illustrated in the drawings, wherein like reference numbers (if they occur in more than one view) designate the same elements. The invention may be better understood by reference to one or more of these drawings in combination with the description presented herein. 
           [0011]      FIG. 1  is a schematic diagram illustrating a current source section of a conventional binary and thermometer-coded hybrid DAC. 
           [0012]      FIG. 2  is a schematic diagram illustrating a current source section of an alternative conventional binary and thermometer-coded hybrid DAC. 
           [0013]      FIG. 3  is a schematic diagram of a current source section of a hybrid DAC according to one embodiment of the present invention. 
           [0014]      FIG. 4  is a schematic diagram of a current source section of a hybrid DAC according to another embodiment of the present invention. 
       
    
    
     DESCRIPTION 
       [0015]    The conventional current source for digital-to-analog converters (DACs) as shown in  FIGS. 1 and 2 , scales transistor sizes to obtain weighted currents for each individual bit. The more bits the DAC has, the larger the transistor sizes become for more significant bits. The present invention discloses a current source scheme that scales transistor biasing instead of sizes to achieve weighted currents for various bits. 
         [0016]    Referring back to  FIGS. 1 and 2 , each current source element in the binary block  110  of either  FIG. 1  or  FIG. 2 , or the thermometer coded blocks  120 ,  220  and  230 , is a PMOS transistor. When a saturated PMOS transistor is biased at a different gate voltage, its source-drain conduction current follows approximately following equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     ds 
                   
                    
                   
                     
                       
                         μ 
                         n 
                       
                        
                       
                         C 
                         ox 
                       
                     
                     2 
                   
                    
                   
                     W 
                     L 
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           GS 
                         
                         - 
                         
                           V 
                           th 
                         
                       
                       ) 
                     
                     2 
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0000]    Where, I ds  is the source-drain conduction current, V GS  is the gate bias voltage, V th  is the threshold voltage, W and L are transistor channel width and length, respectively. The conventional method of scaling the conduction current is through changing the transistor channel width W. According one embodiment of the present invention, the transistor gate bias voltage V GS  is adjusted to achieve conduction current I ds  scaling effect. According to Eq. 1, adjusting V GS  is more effective as the conduction current, I ds , is proportional to the V GS  square. 
         [0017]      FIG. 3  is a schematic diagram of a current source section of a hybrid 12-bit DAC  300  according to one embodiment of the present invention. Four least significant bits are still converted by the binary block  110  as depicted in  FIGS. 1 and 2 . Eight most significant bits are converted by a thermometer coded block  320  which has 255 current source elements D[1:255]. The current source elements D[1:255] are exemplarily implemented by PMOS transistors. Conduction current j, for each current source elements D[1:255] are the same, as they are biased by the same node N 1  and have an identical transistor size. As discussed in the background section, conduction current j=2*i[ 3 ]. To achieve this, conventional method is to make the PMOS transistor T[ 1 ] twice as large as the PMOS transistor B[ 3 ] while all the PMOS transistors B[0:3] and T[1:255] are biased the same as shown in  FIG. 1 . According to the embodiment of the present invention, the PMOS transistors B[0:3] are biased by a node N 2 , and the PMOS transistors D[1:255] are biased by a node N 3 . Then the conduction currents can be expressed by following equations: 
         [0000]    
       
         
           
             
               
                 
                   j 
                   = 
                   
                     
                       
                         
                           μ 
                           n 
                         
                          
                         
                           C 
                           ox 
                         
                       
                       2 
                     
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                         W 
                         D 
                       
                       L 
                     
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                         ( 
                         
                           
                             V 
                             
                               N 
                                
                               
                                   
                               
                                
                               3 
                             
                           
                           - 
                           
                             V 
                             th 
                           
                         
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                       2 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   2 
                 
               
             
             
               
                 
                   
                     i 
                      
                     
                       [ 
                       3 
                       ] 
                     
                   
                   = 
                   
                     
                       
                         
                           μ 
                           n 
                         
                          
                         
                           C 
                           ox 
                         
                       
                       2 
                     
                      
                     
                       
                         W 
                         B 
                       
                       L 
                     
                      
                     
                       
                         ( 
                         
                           
                             V 
                             
                               N 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                           - 
                           
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                       2 
                     
                   
                 
               
               
                 
                   Eq 
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                    
                   3 
                 
               
             
           
         
       
     
         [0000]    where, W D  is the channel width of the PMOS transistors D[1:255], W B[3]  is the channel width of the PMOS transistors B[ 3 ], V N3  is the biasing voltage at the node N 3 , and V N2  is the biasing voltage at the node N 2 . As an example, the PMOS transistors D[1:255] have 2 legs (M=2), while the PMOS transistor B[ 3 ] has 8 legs (M=8), thus W D =W B[3] /4. In order to make j=2*i[ 3 ], the biasing voltages are then set according to following equation: 
         [0000]        W   D ( V   N3   −V   th ) 2 =2· W   B[3] ( V   N2   −V   th ) 2    Eq. 4 
         [0000]      or ( V   N3   −V   th ) 2 =8·( V   N2   −V   th ) 2    Eq. 5 
         [0018]    Referring again to  FIG. 3 , the different biasing voltages, V N3  and V N2 , is achieved by the current mirror circuit  305 . The current mirror circuit  305  comprises a pair of PMOS transistors X 1  and X 2 , and NMOS transistors X 3 , X 4 , X 5  and X 6 . The cascoded NMOS transistors X 3  and X 4  provide biasing for the PMOS transistor X 1 . Similarly, the cascoded NMOS transistors X 4  and X 6  provide biasing for the PMOS transistor X 2 . The node N 2  is connected to a gate of the PMOS transistor X 2 . The node N 3  is connected to a gate of the PMOS transistor X 1 . When transistor sizes of X 1 , X 3  and X 5  equal the transistor sizes of X 2 , X 4  and X 5 , respectively, a conduction current flowing through the PMOS transistor X 1  equals the conduction current flowing through the PMOS transistor X 2 . In this case, the voltage V N2  becomes the same as the voltage V N3 . Through adjusting the ratio of the transistor sizes between the transistor group comprised of X 1 , X 3 , X 5 , and the transistor group comprised of X 2 , X 4  and X 6 , a desired voltage ratio between V N2  and V N3  can be achieved. The mechanism of the current mirror circuit  305  is well known in the art. In fact, the current mirror circuit  305  is only one of many ways to control the ratio between the voltages, V N2  and V N3 . 
         [0019]    Referring again to  FIG. 3 , the current sources of the thermometer coded block  320  have a total transistor leg number of 255*2=510, while the similar circuit, block  120  in  FIG. 1 , has a total transistor leg number of 255*16=4080. Apparently, the present invention causes a large amount of transistor size reduction, and therefore reducing chip size and cost of the DAC  300 . 
         [0020]      FIG. 4  is a schematic diagram of a current source section of an alternative 12-bit hybrid DAC  400  according to the embodiment of the present invention. The current source section of the DAC  400  comes from applying a current mirror circuit  405  to the current source section of the DAC  300  in  FIG. 2 . A thermometer coded block  420  corresponds to the thermometer coded block  220  of  FIG. 2 . The thermometer coded block  430  corresponds to the thermometer coded block  230  of  FIG. 2 . The current mirror circuit  405  has identical structure as the current mirror circuit  305  of  FIG. 3 . The transistor sizes of the current mirror circuit  405  is so adjusted for controlling biasing voltages at nodes N 2  and N 4 , even though each of the transistors E[1:3] is eight time smaller in size than the transistor B[ 3 ], the conduction current of each of the transistors E[1:3] is still twice as large as the conduction current of the transistor B[ 3 ], i.e., k=2*k[ 3 ]. With the transistors E[ 3 ] having only one leg each and the transistors F[1:63] having four legs each, a total transistor leg count of the thermometer blocks  420  and  430  is (63*4+3*1)=255. Apparently the current source section of the DAC  400  provides more dramatic transistor size reduction. 
         [0021]    The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
         [0022]    Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.