Abstract:
An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.

Description:
BACKGROUND 
     Field 
     The disclosure relates generally to a linear voltage regulator circuits and, more particularly, to a linear voltage regulator circuit device having improved power supply reduction ratio (PSRR) thereof. 
     Description of the Related Art 
     Linear voltage regulators are a type of voltage regulators used in conjunction with semiconductor devices, integrated circuit (IC), battery chargers, and other applications. Linear voltage regulators can be used in digital, analog, and power applications to deliver a regulated supply voltage. In power management semiconductor chips, it is desirable to consume the least amount of power possible to extend the battery power. In the initialization of a power management semiconductor chip, a bias current is needed for the internal nodes and branches. This start-up bias current establishes a pre-condition state for many power applications. The bias current magnitude should be a low value to extend battery life. With the reduction of the bias current, leads to bias lines to become high impedance. Additionally, with the reduction of the bias current, noise has a larger influence. The noise signals enter the system through the parasitic capacitance. With the long bias lines on the order of milli-meters, the magnitude of the capacitance, and the noise signal is significant, and impacts the power supply rejection ratio (PSRR). 
     In systems today, the design methodology typically provide two different methods for biasing for global biasing and local biasing. Current biasing is used for global biasing. Voltage biasing is used for local biasing within the functional block. In an example of a system known to the inventors, a system floorplan design can contain a plurality of digital blocks, a bias block  30 , and routing lines. In a large system, the routing lines can be of significant length leading to power supply reduction ratio (PSRR) degradation. 
     In linear voltage regulators, usage of isolation circuits has been discussed. As discussed in published U.S. Pat. No. 8,525,716 to Bhatia et al describes an isolation network. An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit. 
     In low dropout regulators, establishing line drivers that address bias supply issues have been discussed. As discussed in U.S. Pat. No. 7,443,977 to Toumani et al., discloses a line driver which includes: at least one amplifier, a delay element, a control signal generator and a generator. At least one amplifier includes at least one bias supply, a signal input and a signal output. The delay element accepts as an input the data signal and delays delivery of the data signal to the at least one line amplifier for amplification. The generator is responsive to a control signal to generate varying voltage levels corresponding thereto on the at least one bias supply of the at least one amplifier. The control signal generator is responsive to the input data signal to detect peaks therein and to generate the control signal corresponding thereto in advance of delivery of the data signal to the amplifier. 
     In digital-to-analog converter (DAC) circuit utilizes a bias circuit. As discussed in U.S. Pat. No. 6,100,833 to Park et al, describes a digital to analog converter and bias network. A b-bit digital and analog converter addressed non-expensive and monotonic with relatively high differential and integral non-linearities. The converter uses weighed current ratio to achieve decrease the number of current cells to provide a cumulative current which corresponds to the digital value on the input data bus. 
     In these prior art embodiments, the solution to improve the response for bias line issues utilized various alternative solutions. 
     It is desirable to provide a solution to address the disadvantages of the low dropout (LDO) regulator for improved PSRR. 
     SUMMARY 
     A principal object of the present disclosure is to provide a circuit implementation which lessens the impact of parasitic capacitance associated with bias lines. 
     A principal object of the present disclosure is to provide a circuit that reduces the impact of parasitic capacitance on power supply rejection ratio (PSRR) of analog functional blocks. 
     Another further object of the present disclosure is to provide a circuit device with analog blocks that reduces the standby current for the system. 
     Another further object of the present disclosure is to provide a circuit device with an enabling switch driven by a pre-regulated supply. 
     The above and other objects are achieved by a low dropout device with improved power supply reduction ratio (PSRR). The device comprising a p-channel MOSFET pull-up, an n-channel MOSFET switch, a digital gate driven by a ripple free battery pre-regulated filtered power source, a battery voltage source, and a ground. 
     The above and other objects are further achieved by a system with improved power supply rejection ratio (PSRR), the system comprising a regulated power supply, a bias control block electrically connected to said regulated power supply, providing a bias control function, a functional block electrically connected to the bias control block, and a bias line electrically coupling said bias control block and said functional block. 
     The above and other objects are further achieved by a system with improved power supply rejection ratio (PSRR), the system comprising of a regulated power supply, an enabling switch electrically connected to said regulated power supply, providing an enabling function, a functional block electrically connected to the enabling switch, and a bias line electrically coupling said enabling switch and said functional block. 
     The above and other objects are further achieved by a system with improved power supply rejection ratio (PSRR), the device comprising an enabling switch providing an enabling function, a low pass filter electrically coupled to the output of said enabling switch, a functional block electrically coupled to said low pass filter, and a bias line electrically coupling said low pass filter and said functional block. 
     The above and other objects are further achieved by a system with improved power supply rejection ratio (PSRR), the device comprising a regulated power supply, an enabling switch electrically connected to said regulated power supply, providing an enabling function a low dropout (LDO) regulator electrically connected to the enabling switch; and a bias line electrically coupling said enabling switch and said low dropout (LDO) regulator. 
     The above and other objects are further achieved by a method of improved power supply rejection ratio (PSRR) frequency dependence in a system comprising the steps of providing a system comprising a functional block, a master bias network, an enabling switch, a bias line, and a regulated power supply, feeding a regulated voltage to said enabling switch, feeding a voltage representing a voltage supply to said functional block; and minimizing bias line parasitic capacitance for improved power supply rejection ratio (PSRR) through design layout. 
     The above and other objects are further achieved by a method of improved power supply rejection ratio (PSRR) frequency dependence in a system comprising the steps of providing a system comprising a functional block, a master bias network, an enabling switch, a bias line, a low pass filter (LPF) and a regulated power supply, feeding a regulated voltage to said enabling switch, filtering the output of said enable switch using said low pass filter (LPF), and minimizing bias line parasitic capacitance for improved power supply rejection ratio (PSRR) through design layout. 
     As such, a novel low dropout (LDO) device with an improved power supply rejection ratio (PSSR) over a wide frequency range. Other advantages will be recognized by those of ordinary skill in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure and the corresponding advantages and features provided thereby will be best understood and appreciated upon review of the following detailed description of the disclosure, taken in conjunction with the following drawings, where like numerals represent like elements, in which: 
         FIG. 1  is an example of a system floor plan; 
         FIG. 2  is an example of the plot of a measured and simulated power supply rejection ratio (PSRR) as a function of frequency; 
         FIG. 3  is an example of a high level diagram of a Master Bias, an LDO, connecting bias line, and a bias line parasitic capacitance; 
         FIG. 4  is a plot of a simulated power supply rejection ratio (PSRR) as a function of the logarithm of frequency with and without a parasitic capacitance on the bias line; 
         FIG. 5  is a circuit schematic illustrating the internal connections from the bias current from the bias block to the low dropout (LDO) regulator; 
         FIG. 6  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a first embodiment of the disclosure; 
         FIG. 7  is a plot of the measured and simulated power supply rejection ratio (PSRR) as a function of frequency in accordance with the first embodiment of the disclosure; 
         FIG. 8  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a second embodiment of the disclosure; 
         FIG. 9  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a third embodiment of the disclosure; 
         FIG. 10  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a fourth embodiment of the disclosure; and 
         FIG. 11  is a flow chart of the method of providing a system with improved power supply rejection ratio (PSRR). 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows the full system  1  illustrating an embodiment known to the inventor. In systems today, the design methodology typically provide two different methods for biasing for global biasing and local biasing. Current biasing is used for global biasing. Voltage biasing is used for local biasing within the functional block. In an example of a system known to the inventors, a system floor plan design is illustrated in  FIG. 1 .  FIG. 1  shows the full system  1  containing a plurality of circuit blocks  20 , a bias block  30 , and routing lines  40 . The routing lines  40  show the routing from the bias block  30  to the plurality of blocks  20  for the bias current. In a large system, the routing lines can be of significant length leading to power supply reduction ratio (PSRR) degradation. Bias lines are not routed to digital blocks. 
       FIG. 2  is an example of the plot of a measured and simulated power supply rejection ratio (PSRR) as a function of frequency.  FIG. 2  PSRR versus frequency plot  50  compares the measured PSRR plot  55  and the simulated PSRR plot  60 . At low frequency below 1000 Hz (e.g. 1 kHz), the measured PSRR  55  and simulated PSRR  60  are equal in magnitude. For frequencies above 1000 Hz, the measured PSRR  55  deviates from the simulated. At 10 kHz frequency, the measured PSRR  55  is approximately 20 dB worse than the simulated PSRR  60 . The observed degradation is associated with the parasitic capacitance of the bias line. 
       FIG. 3  is an example of a high level diagram of a Master Bias, an LDO, connecting bias line, and a bias line parasitic capacitance. The system  70  is shown comprising of a Master Bias function  75 , a low dropout (LDO) regulator  80 , a bias line  85 , and a parasitic capacitance  90 . The parasitic capacitance  90  is illustrated as the capacitance between the Bias Line and ground potential  95 . 
       FIG. 4  plots the power supply rejection ratio (PSRR) as a function of logarithm of frequency for a low drop-out (LDO) regulator as illustrated in  FIG. 3 . The PSRR simulation without a 500 fF capacitance on the bias line is shown as PSRR vs frequency curve trace  105 . The PSRR simulation with a parasitic capacitance is shown in PSRR vs frequency curve trace  110 . As can be observed, the curve trace  105  and curve trace  110  deviate at frequencies above 1 kHz. 
       FIG. 5  illustrates the internal connection of the bias current from the bias block to the low dropout (LDO) regulator. The circuit contains an n-channel MOSFET switch N 1   120 . The n-channel MOSFET switch N 1   120  enables the flow of bias current to the low dropout (LDO) when the LDO is in an enable mode of operation. The circuit contains a p-channel MOSFET  130  between the battery voltage  135 , and the n-channel MOSFET switch N 1   120 . A bias current generator  140  represents the circuit bias between n-channel MOSFET  120  and ground connection  150 . A digital gate  160  is represented by I 1  which is driven of the LDO supply and controls the gate of n-channel MOSFET N 1   120  and is electrically connected to the battery voltage supply  135 . The ENABLE function enters the network as a input to circuit element  162 . Parasitic capacitance associated with n-channel MOSFET  120  are gate-to-drain capacitance  121 , gate-to-source capacitance  122 , and source-to-drain capacitance  123 . Parasitic capacitance from the routing line  165  to ground connection  150  can be expressed as capacitance element  170 . Parasitic capacitance from the routing line  165  to the battery  135  can be expressed as capacitance element  180 . In operation, when the LDO is enabled, the gate of n-channel MOSFET  120  rises to the battery voltage. This would include any alternating current (a.c.) signal present on the gate of the n-channel MOSFET  120 . The alternating current (a.c.) signal leads to coupling into the discussed bias line  165  leading to degradation of the power supply rejection ratio (PSRR). Note that this is not a function of an n-channel MOSFET, but will also be true if the switch was a p-channel MOSFET 
       FIG. 6  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a first embodiment of the disclosure. The circuit contains an n-channel MOSFET switch N 1   120 . The n-channel MOSFET switch N 1   120  enables the flow of bias current to the low dropout (LDO) when the LDO is in an enable mode of operation. The circuit contains a p-channel MOSFET  130  between the battery voltage  135 , and the n-channel MOSFET switch N 1   120 . A bias current generator  140  represents the circuit bias between n-channel MOSFET  120  and ground connection  150 . A circuit  200  is represented by I 1  controls the gate of n-channel MOSFET N 1   120 . The circuit  200  is electrically connected to regulated power supply  210 . With the electrical connection to VREG, the circuit utilizes a ripple free/regulated/filtered supply. The ENABLE function enters the network as a input to circuit element  220 . Parasitic capacitance associated with n-channel MOSFET  120  are gate-to-drain capacitance  121 , gate-to-source capacitance  122 , and source-to-drain capacitance  123 . Parasitic capacitance from the routing line  165  to ground connection  150  can be expressed as capacitance element C 1   170 . Parasitic capacitance from the routing line  165  to the battery  135  can be expressed as capacitance element C 2 . This would include any alternating current (a.c.) signal present on the gate of the n-channel MOSFET  120 . The alternating current (a.c.) signal leads to coupling into the discussed bias line  165  leading to degradation of the power supply rejection ratio (PSRR). 
     In this embodiment, as illustrated in  FIG. 6 , the modification of  FIG. 5  is the utilization of the circuit element I 1   200  with the regulated supply which has more desirable features for the network. The regulated voltage source has a high power supply rejection ratio (PSRR) for a low dropout (LDO) In addition, the capacitance C 2  which is the parasitic capacitance from the routing line  165  to the battery  135  can be minimized by design layout. With the combined influence of the utilization of the voltage regulated supply, and the lowering of C 2  capacitance using design layout and improved floor planning an improved PSRR is achieved. 
       FIG. 7  is a plot of the measured and simulated power supply rejection ratio (PSRR) as a function of frequency in accordance with the first embodiment of the disclosure. In the plot  240 , the simulated PSRR  245  is compared to the measured PSRR  250 . From the plot  240 , there is no evidence of PSRR degradation with frequency as a result of the reduced bias line parasitic capacitance. 
       FIG. 8  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a second embodiment of the disclosure. The circuit contains an n-channel MOSFET switch N 1   120 . The n-channel MOSFET switch N 1   120  enables the flow of bias current to the low dropout (LDO) when the LDO is in an enable mode of operation. The circuit contains a p-channel MOSFET  130  between the battery voltage  135 , and the n-channel MOSFET switch N 1   120 . A bias current generator  140  represents the circuit bias between n-channel MOSFET  120  and ground connection  150 . A circuit  160  is represented by I 1  is electrically connected to the power supply  135 . The ENABLE function enters the network as an input to circuit element  162 . Parasitic capacitance associated with n-channel MOSFET  120  are gate-to-drain capacitance  121 , gate-to-source capacitance  122 , and source-to-drain capacitance  123 . Parasitic capacitance from the routing line  165  to ground connection  150  can be expressed as capacitance element C 1   170 . Parasitic capacitance from the routing line  165  to the battery  135  can be expressed as capacitance element C 2   180 . 
     In this second embodiment, the modification includes a low pass filter (LPF) represented as a resistor R 1   260  and capacitor C 3   270 . The resistor element R 1   260  is in series between I 1   160  and the gate of n-channel MOSFET  120 . The capacitor C 3   270  is electrically connected to the output of the resistor R 1   260  and the ground connection  150 , forming an RC network. In this embodiment, any network that provides the function for a low pass filter can achieve the equivalent results. The resistor element R 1  and the capacitor element C 3  can be implemented using passive or active elements, including metal oxide semiconductor (MOS) field effect transistors. 
       FIG. 9  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a third embodiment of the disclosure.  FIG. 9  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a first embodiment of the disclosure. The circuit contains an n-channel MOSFET switch N 1   120 . The n-channel MOSFET switch N 1   120  enables the flow of bias current to the low dropout (LDO) when the LDO is in an enable mode of operation. The circuit contains a bias current network  280  between the power supply  135 , and the n-channel MOSFET switch N 1   120 . A “On MOSFET” NFET N 2   290  is electrically connected bias between n-channel MOSFET  120  and ground connection  150 . A circuit  200  is represented by I 1  which controls the gate of n-channel MOSFET N 1   120 . The circuit  200  is electrically connected to the regulated voltage  210 . With the electrical connection to the regulated voltage, the circuit utilizes a ripple free/regulated/filtered supply. The ENABLE function enters the network as an input to circuit element  220 . Parasitic capacitance associated with n-channel MOSFET  120  are gate-to-drain capacitance  121 , gate-to-source capacitance  122 , and source-to-drain capacitance  123 . Parasitic capacitance from the bias line  166  to ground connection  150  is capacitance element C 1   170 , the bias line should be shielded with power supply track running below it to reduce C 1  this avoids degradation of high frequency PSRR. Parasitic capacitance from the bias line  166  to the power supply  135  can be expressed as capacitance element C 2   230 . The bias line  166  is the line between the bias circuit  280  and the n-channel MOSFET  120 . This would include any alternating current (a.c.) signal present on the gate of the n-channel MOSFET  120 . The alternating current (a.c.) signal leads to coupling into the discussed bias line  165  leading to degradation of the power supply rejection ratio (PSRR). In this embodiment, the utilization of the circuit element I 1   200  with the regulated power supply  210  which has more desirable features for the network. The regulated voltage source has a high power supply rejection ratio (PSRR) for a low dropout (LDO) In addition, the parasitic capacitances can be minimized by design layout. With the combined influence of the utilization of the regulated voltage supply, and the lowering of parasitic capacitances using design layout and improved floor planning an improved PSRR is achieved. 
       FIG. 10  is a circuit schematic diagram illustrating the internal connections from the bias current from the bias block to the low drop out (LDO) regulator in accordance with a fourth embodiment of the disclosure. The circuit contains a p-channel MOSFET switch PFET  310 . The p-channel MOSFET switch  310  enables the flow of bias current to the low dropout (LDO) when the LDO is in an enable mode of operation. The circuit contains a bias current network  280  between the battery voltage  135 , and the p-channel MOSFET switch  310 . A “On MOSFET” NFET N 2   290  is electrically connected bias between p-channel MOSFET  310  and ground connection  150 . A digital gate  220  is represented by I 1  which is driven of the LDO supply and controls the gate of p-channel MOSFET  310  and is electrically connected to the regulated voltage supply  300 . With the electrical connection to the regulated voltage supply, the circuit utilizes a ripple free/regulated/filtered supply. The ENABLE function enters the network as an input to circuit element  220 . Parasitic capacitance associated with p-channel MOSFET  310  are gate-to-drain capacitance, gate-to-source capacitance, and source-to-drain capacitance (not shown). Parasitic capacitance from bias line  166  to ground connection  150  can be expressed as capacitance element C 1   170 , the bias line should be shielded with power supply track running below it to reduce C 1  this avoids degradation of high frequency PSRR. Parasitic capacitance from the bias line  166  to the battery  135  can be expressed as capacitance element C 2   230 . The bias line  166  is the line between the bias circuit  280  and the p-channel MOSFET  310 . In this embodiment, the utilization of the circuit element I 1   220  with the regulated voltage supply  300  which has more desirable features for the network. The regulated voltage source has a high power supply rejection ratio (PSRR) for a low dropout (LDO) In addition, the parasitic capacitances C 1   170  and C 2   230  can be minimized by design layout. With the combined influence of the utilization of the regulated voltage supply, and the lowering of C 1   170  and C 2   230  capacitance using design layout and improved floor planning an improved PSRR is achieved. 
       FIG. 11  illustrates a method of improved power supply rejection ratio (PSRR) frequency dependence in a system. The method includes (1) providing a system comprising a functional block, a master bias network, an enabling switch, a bias line, and a regulated power supply  320 , (2) feeding a regulated voltage to said enabling switch  330 , (3) feeding a voltage representing a battery voltage to said functional block  340 , and (4) minimizing bias line parasitic capacitance through design layout  350 . In this method, the functional block can be a low dropout (LDO) regulator. 
     A second method for improved power supply rejection ratio (PSRR) frequency dependence in a system includes (1) providing a system comprising a functional block, a master bias network, an enabling switch, a bias line, a low pass filter (LPF) and a regulated power supply, (2) feeding a regulated voltage to said enabling switch, (3) filtering the output of said enable switch using said low pass filter (LPF), and (4) minimizing bias line parasitic capacitance through design layout. 
     The low dropout (LDO) regulator can be defined using bipolar transistors, or metal oxide semiconductor field effect transistors (MOSFETs). The LDO regulator can be formed in a complementary metal oxide semiconductor (CMOS) technology and utilize p-channel and re-channel field effect transistors (e.g. PFETs and NFETs, respectively). The LDO regulator can be formed in a bipolar technology utilizing homo-junction bipolar junction transistors (BJT), or hetero-junction bipolar transistors (HBT) devices. The LDO regulator can be formed in a power technology utilizing lateral diffused metal oxide semiconductor (LDMOS) devices. The LDMOS devices can be an n-type LDMOS (NDMOS), or p-type LDMOS (PDMOS). The LDOvoltage regulator can be formed in a bipolar-CMOS (BiCMOS) technology, or a bipolar-CMOS-DMOS (BCD) technology. The LDO regulator can be defined using both planar MOSFET devices, or non-planar FinFET devices. 
     As such, a novel voltage regulator with improved voltage regulation are herein described. The improvement is achieved with minimal impact on silicon area or power usage. The improved low dropout (LDO) regulator circuit improves voltage regulation with improved Power Supply Rejection Ratio (PSRR) frequency characteristics by reduction of the parasitic capacitance associated with the bias line. Other advantages will be recognized by those of ordinary skill in the art. The above detailed description of the disclosure, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the disclosure have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the disclosure.