Abstract:
A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of, and incorporates herein by reference in its entirety, U.S. Provisional Patent Application No. 61/195,449, which was filed on Oct. 7, 2008. 
    
    
     TECHNICAL FIELD 
     In various embodiments, the present invention relates to electronic circuits, and more particularly to electronic decoding circuits having low component complexity. 
     BACKGROUND 
     The semiconductor memory business is a very competitive one in which cost is a function of, among other things, the bit density, the die size, and the device yield. The price commanded by a memory part is further impacted by the part&#39;s access speed and power consumption (particularly in the case of memory parts that are to be used in portable devices). For the highest bit density, a memory array having a two feature square (2F 2 ) storage cell size is the most efficient (ignoring multiple bit per cell devices). A diode cross-point memory structure achieves this density. To interface to such a memory structure, row and column decoder circuits must be incorporated and, to minimize the die size, a high ratio of memory circuitry to peripheral circuitry must be achieved which requires that the decoder circuitry must be efficiently designed. 
     Array decoders based on diode decoding circuits are very efficient. Device yield must be maximized and, since redundant circuitry increases both die size and test (repair) costs, error correcting (ECC) techniques can be utilized in their place. Furthermore, to better support ECC efficiency in the case of defects in word lines and bit lines, a diagonal access technique (as is disclosed in U.S. Pat. No. 7,149,394 to Shepard, the entire disclosure of which is hereby incorporated by reference herein) can be employed which requires the word-line and bit-line access to advance while a data block is accessed. A trade-off is often an issue with speed and power consumption. Many memory decoders utilize a tree decoding structure to save power and reduce die size, but this can introduce decoding delays as the address decoding must be decoded in a first stage and be allowed to stabilize before decoding in a second or subsequent stage. This approach saves power by not energizing portions of the decoder outside of the tree branch being selected. 
     Many types of non-volatile storage arrays exist in the prior art and the array lines in most of these arrays are connected with decoder driver circuits. Often, as can be found in the prior art, to enable the drivers to be fabricated with half the pitch as the array lines themselves, these driver circuits are placed on both sides of the array with alternate array lines exiting the array on opposite sides. A drawback to this approach is that the decoder circuitry is duplicated to some degree on both sides of the array. If the decode circuitry is not very efficient, this duplication will significantly increase the die size and cost. 
     SUMMARY 
     Many types of electronic circuits exist in the prior art. With any given circuit, there can be many types of different components to implement a given functionality. Many of these circuits are ultimately implemented in a monolithic integrated circuit form. As it turns out, the cost of manufacturing an integrated circuit, or chip, is closely related to the number of process steps. For every different type of component included in a given chip, additional process steps are typically required. Therefore, in the design of a circuit, each addition of a component type adds to the final cost of manufacturing that chip. 
     Embodiments of the present invention feature a circuit block for implementing a particular functionality. This circuit block has been designed with low component complexity (i.e., with a goal of minimizing the number of different component types). Consequently, various embodiments implement a particular circuit functionality for low manufacturing cost. Furthermore, since many high density memory devices for use in consumer applications today work on block transfers of large data sets (e.g., a photograph image), most of the memory accesses consist of long, sequential operations; embodiments of the present invention may be used to sequentially advance through the memory space of a memory array. 
     Embodiments of the present invention may also achieve a diagonal access capability as well as power savings by auto-incrementing the address; only a small portion of the array that is sequentially adjacent to the most recently selected portion is precharged following each memory access. Various embodiments utilize a diode decoder with driver circuit that sequences the row selection automatically with each memory access. As will be clear to one skilled in the art, the same technique may be implemented for the array columns. 
     In an aspect, embodiments of the invention feature a memory-array decoder including or consisting essentially of first and second decoder stages. The decoder receives as input a plurality of address bits and is operably coupled to a memory array comprising a sequence of rows. The first decoder stage selects one or more first rows by decoding a first subset of the address bits. The second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows. 
     Embodiments of the invention may include one or more of the following. The one or more second rows may be selected by incrementing the locations of the one or more third rows. The one or more third rows may be selected by an applied signal different from the plurality of address bits alone or in conjunction with a second subset of the address bits. The first and second subsets of address bits may be different, and all of the address bits in the first subset may be different from those in the second subset. The second stage may be capable of selecting one or more second rows from all of the rows of the memory array. The plurality of address bits may include or consist essentially of an input memory address and its complement. The first stage may select a single first row from the one or more second rows selected by the second stage. 
     The memory array may be programmed with data including or consisting essentially of music, video, computer software, a computer application, reference data, text, and/or a diagram. The decoder and the memory array may be disposed within a removable memory storage device. The memory array may include or consist essentially of a plurality of storage cells. At least one of the storage cells may include or consist essentially of a phase-change material. 
     In another aspect, embodiments of the invention feature a method of forming a memory-array decoder that receives as input a plurality of address bits and is operably coupled to a memory array comprising rows and columns. The method includes or consists essentially of providing first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits. The second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows. 
     In yet another aspect, embodiments of the invention feature a method of decoding a memory array comprising rows and columns. A plurality of address bits is received as input by a decoder. A first stage of the decoder selects one or more first rows by decoding a first subset of the address bits. A second stage of the decoder selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows. 
     Embodiments of the invention may include one or more of the following. The one or more second rows may be selected by incrementing the locations of the one or more third rows. A signal different from the plurality of address bits may be applied to the decoder to select the one or more third rows. To select the one or more third rows, a signal different from the plurality of address bits may be applied to the decoder alone or in conjunction with the decoding of a second subset of the address bits. The first and second subsets of address bits may be different, and all of the address bits in the first subset may be different from those in the second subset. The second stage may be capable of selecting one or more second rows from all of the rows of the memory array. The plurality of address bits may include or consist essentially of an input memory address and its complement. Selecting the one or more first rows may include or consist essentially of selecting, with the first stage, a single row from the one or more second rows selected by the second stage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawing, in which: 
         FIG. 1  is a circuit diagram of a sequencing decoder circuit with split, dual-sided decoding in accordance with various embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention feature a sequencing diode decoder circuit for memory or other types of array circuits. This decoder, in a single decoding stage, performs the function of a multi-stage decoder by activating only a portion of the decode circuit at a time (following initial activation). In various embodiments, the decoder also automatically steps the access into the array thereby eliminating the need for a separate sequencing circuit or logic. 
       FIG. 1  depicts a sequencing diode decoder circuit  100  with split, dual sided decoding. A cross-point diode array with diode decoding is described in U.S. Pat. No. 5,673,218 to Shepard, the entire disclosure of which is hereby incorporated by reference herein. In the depicted array, power for reading or writing (+V) is applied to the array through the VPP inputs. One way to address a memory cell has +V applied to a given VPP input and a path to GND applied to a given column within the array (not shown in FIGURE). To select the desired row through the array, the gate of one of the row driver FETs must have a positive voltage applied to switch on that FET to pass the voltage from VPP. 
     In  FIG. 1 , the cross-point memory array structure is shown schematically with the word-line decoder being split and the halves positioned on opposite sides of the array. In such a structure, the word lines alternate between connecting to the left-side decoder and the right-side decoder (see U.S. Pat. No. 7,054,219 by Petti et al., the entire disclosure of which is hereby incorporated by reference). Specifically, lowest-order address line A 0  selects between the two array access sides (e.g., a low state selects the left-side decoder and a high state selects the right-side decoder) and address lines A 1  through A 4  select one of sixteen word-lines in a group in the array. Referring to  FIG. 1 , at the right side of the FIGURE are the row lines into the array; only 64 lines of the array are shown and these are separated into two groups of 32—a top  32  and a bottom  32 . Of the top 32 lines, half of the lines (the even numbered lines) are connected to the drive transistors shown as a column along the right side of the FIGURE (the odd numbered lines are connected to drive transistors in a decoder circuit on the right side of the array that is nearly identical to the decoder shown in  FIG. 1 ). Of the bottom 32 lines, half of the lines (the even numbered lines) are connected to the drive transistors also shown as a column along the right side of the FIGURE (the odd numbered lines are also connected to drive transistors in the decoder circuit on the right side of the array). The top group is one of the even numbered groups and the bottom group is one of the odd numbered groups. There are many such even and odd groups in the array; an 8K×8K array would have 256 of these row groups. Located on the right of the FIGURE between the groups of row line drive transistors are three transistors in a cluster (there are three such trios shown, one at the top, middle and bottom of the FIGURE). Each of these trios performs a pass-forward of a token that enables the currently selected group to enable the group below it to be the next selected group. 
     Operation is initialized with a positive voltage pulse on the “NEW ADDRESS PCH” precharging input (PCH). This voltage is great enough to place a voltage on all the drive transistor gates (after passing through the that row&#39;s corresponding precharge diode) to allow a voltage from a V PP  input to be passed to the desired row line. If the threshold voltage (V TH ) of the NMOS FETs is approximately 0.5 volts and the voltage drop on a diode (V f ) is approximately 0.7 volts and the desired active voltage (V R ) on the targeted row is approximately 2.5 volts, then the drive transistor gate voltage (V GD ) should be V R +V TH  (approximately 3.0 volts) as it should exceed the voltage for the row by the threshold voltage (to compensate for the drive transistor); the PCH input level should exceed the drive transistor gate voltage by the diode forward voltage (to compensate for the precharge diode voltage drop) V GD +V f =V R +V TH +V f  or approximately 3.7 volts (the “PCH voltage”). Following this initial PCH pulse, all of the drive transistor gates will generally hold a voltage charge and the diode decoder is activated by pulling down on one of each of the complementary address pair inputs (as described in U.S. Pat. No. 5,673,218). The pull-down voltage should be low enough to shut off any given drive transistor by discharging its gate through the decoder diodes to below the turn on voltage; a pull down voltage level of approximately −0.7 volts will discharge the gates to approximately zero volts while taking the V f  of the decoder diodes into account. After applying an address voltage pulse, only one transistor gate will remain switched on at which point a V PP  signal may be raised to energize the desired row line. If each row group consists of N lines (e.g.,  32  in  FIG. 1 ) of which N/2 are connected to drive transistors on a given side of the array (e.g.,  16  in  FIG. 1 ), then the number of address bits in the “Low Address Bits” must be that number which can decode one out of N/2 in a binary decoding (e.g., 4 address bits in FIG.  1 —A 1  through A 4 ). The lowest address bit (A 0 ) is used to select the array side, left or right (the left side is shown in  FIG. 1 ). The “High Address Bits” decode to select a given group of rows into the array (additional address bits will typically be utilized to decode the columns and may be decoded with a similar sequencing decoder circuit). The lowest-order bit of the “High Address Bits” (A 5  in  FIG. 1 ) generally identifies which of the V PP  signals corresponds to which row group (when A 5  is low, the bottom group shown in  FIG. 1  is active and V PP1  is utilized; when A 5  is high, the top group shown in  FIG. 1  is active and V PP0  is utilized). 
     In an embodiment, within each of the trios of transistors, one transistor is configured as a switch transistor and two are configured as capacitors. When PCH is pulsed, the gate of the switch transistor of each trio is charged along with the drive transistor gates and when the address is asserted, only the switch transistor corresponding to the target group (shown in  FIG. 1  as the trio just below the group) remains turned on; this is affected by the “High Address Bits” as the gates of the switch transistors are connected into the diode address decoder by only the “High Address Bits” and bypass the low address bits. In this way, when an address is decoded leaving one drive transistor turned on into the array, only the switch transistor of the trio associated with that group (the trio shown in  FIG. 1  to be just below that group) will also be left turned on. In this way, when the V PP  corresponding to the target group is raised, voltage from that V PP  may pass through the selected drive transistor into the array as well as from that V PP  through the switch transistor of the associated trio and through a string of (N/2)+1 diodes (or other non-linear elements) to precharge the gates of the transistors of the subsequent group (since this subsequent group is connected to the alternate V PP  input, charging the gates of these drive transistors does not energize the associated rows into the array). It should also be noted that to precharge those gates sufficiently, V PP  should be large enough to offset the voltage threshold of the switch transistor of the trio and the one diode of the string of (N/2)+1 diodes. As stated above, if the desired active voltage (V R ) on the targeted row is approximately 2.5 volts and the threshold voltage (V TH ) of the drive transistor is approximately 0.5 volts, the voltage on the gate of the drive transistor should be approximately 3.0 volts (V R +V TH ). To place V R +V TH  on the gate of the drive transistors (given a forward voltage drop on a diode, V f , is approximately 0.7 volts), then the voltage on the gate of the switch transistor in the trio should be (V R +V TH )+V f +V TH  or approximately 3.0+0.7+0.5 volts (approximately 4.2 volts). This may be achieved by adjusting the previously calculated voltage for PCH upward to approximately 4.9 volts by adding one additional voltage drop of V f  to accommodate for the precharge diode. Alternatively, as is shown in  FIG. 1 , a capacitor may be added by incorporating an additional FET configured as a capacitor (the upper capacitor FET of each trio), as is well known and understood by those skilled in the art. This “boosting” capacitor will generally be sized to enable sufficient charge to be coupled to the gate of the switch transistor when V PP  is applied so as to raise its voltage above the voltage placed thereon by the PCH input (taking into account the capacitance of the gate and of the diode decoder diodes also connected to that gate). If the applied PCH signal was approximately 3.7 volts, this boost should add an additional approximately 1.2 volts to the gate voltage. The amount of boost is typically a function of the level of V PP , the size of the upper transistor of the trio and the parasitic capacitances and resistances associated with the gate of the switch transistor. 
     When V PP  is passed through the switch transistor of the active trio and the one diode of the string of (N/2)+1 diodes to place the drive transistor gate voltage, V GD =V R +V TH , on the gate of the drive transistors, this voltage is also placed on the gate of the switch transistor of the trio subsequent to the active trio (just as it is done during the application of PCH). In this way, following the initial application of PCH to the entire decoder circuit&#39;s drive transistor gates, the application of V PP  will have the effect of performing the PCH application to only the next group (along with its corresponding transistor trio)—the drive transistors and the switch transistor of the trio will receive V GD . Selection of a single line within that subsequent group is then affected by asserting the address inputs which will discharge all but one of the drive transistor gates for selection of a single row. Since the groups&#39; drive transistors will alternately connect to one of the two V PP  inputs, raising the alternate V PP  following the selection of a single drive transistor within the group will energize the next row in sequence and will also have the effect of performing the PCH application to yet the next group with row energization occurring when returning to the initial V PP  input, and so on. In effect, the selection of a row in each group sets up the subsequent group for selection. With the last group wrapping around and being connected to the first group, this process may continue over and over. Furthermore, at any point in the process a new address may be loaded to enable selection of a different numbered row within a group or the same address may be maintained for selection of the same row within multiple group selections. In addition, accesses may be affected from the decoder on one side of the array and then suspended in lieu of accesses via the other side of the array. As a variation, the accesses may be interleaved with accesses by the row decoder on the opposite side of the array, whereby during the address assertion phase on one side of the array, V PP  could be applied via the other side. 
     In an embodiment, a third (optional) transistor, configured as a capacitor, is included in the trio of transistors as shown in  FIG. 1 . This is the lower capacitor transistor. This transistor may be utilized to help reduce the applied V PP  voltage by boosting the voltage on the subsequent gates as required as a consequence of the lowered V PP  voltage. Care should be taken to not assert the addresses while applying V PP  in any way that would allow a current path from that V PP  through a switch transistor in a trio through a diode of the string of (N/2)+1 diodes and then through the decoder diodes as excess power will be consumed and wasted. 
     Another embodiment of the present invention, while less compact to manufacture, has the sequential selection occurring at the finest decode resolution; that is, a single row in the array is selected and in so doing the pass-forward of the token goes to the next single row selection. This variation would use a subset of the address bits to select a starting point and then would walk through the rows sequentially. 
     Embodiments of the present invention will typically, though not necessarily, be built as integrated circuits. Variations will be apparent to those skilled in the art, including driver devices consisting of different types of components than NMOS FETs, as well as different numbers of components in more complex driver circuits. Embodiments may be implemented on the bit lines or on the word lines and bit-lines simultaneously. Embodiments may be implemented with cross-point memory arrays and these arrays may be one of many tiles or sub-arrays in a larger device or an array within a three-dimensional arrangement of arrays or tiles. The storage cells may include various non-linear elements, e.g., transistors, field-emitters, diodes, or any other device that conducts current better in one direction than the other for a given applied voltage. The storage element may be a fuse, an antifuse, a phase-change material such as a chalcogenide (including a chalcogenide in which the programmed resistivity may be one of two resistance values and, in the case of more than one bit per cell storage cells, in which the programmed resistivity may be one of three or more resistance values), or a field-emitter element programming mechanism including an element for which the resistance or the volume is changeable and programmable. Orientation of the array may be rotated, i.e., the “rows” may be “columns,” or vice versa. The polarity of the voltages and direction of the steering elements in the storage bits may be reversed while still keeping within what is envisioned by embodiments of the present invention. 
     Memory devices incorporating embodiments of the present invention may be applied to memory devices and systems for storing digital text, digital books, digital music (such as MP3 players and cellular telephones), digital audio, digital photographs (wherein one or more digital still images may be stored including sequences of digital images), digital video (such as personal entertainment devices), digital cartography (wherein one or more digital maps can be stored, such as GPS devices), and any other digital or digitized information as well as any combinations thereof. Devices incorporating embodiments of the present invention may be embedded or removable, and may be interchangeable among other devices that can access the data therein. Embodiments of the invention may be packaged in any variety of industry-standard form factor, including Compact Flash, Secure Digital, MultiMedia Cards, PCMCIA Cards, Memory Stick, any of a large variety of integrated circuit packages including Ball Grid Arrays, Dual In-Line Packages (DIPs), SOICs, PLCC, TQFPs and the like, as well as in proprietary form factors and custom designed packages. These packages may contain just the memory chip, multiple memory chips, one or more memory chips along with other logic devices or other storage devices such as PLDs, PLAs, micro-controllers, microprocessors, controller chips or chip-sets or other custom or standard circuitry. 
     The terms and expressions employed herein are used as terms and expressions of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described or portions thereof. In addition, having described certain embodiments of the invention, it will be apparent to those of ordinary skill in the art that other embodiments incorporating the concepts disclosed herein may be used without departing from the spirit and scope of the invention. Accordingly, the described embodiments are to be considered in all respects as only illustrative and not restrictive.