Abstract:
In order to implement the Digital Video Broadcasting descrambling algorithm in the context of MPEG compressed data streams containing interleaved sections of scrambled and unscrambled data, at a data rate of 60 MBits/sec with a clock of 2.7 MHz, a stream cipher has an input to receive scrambled video data, and an output coupled to a block cipher for providing descrambled data, the stream cipher comprises shift register means for holding input data coupled to a first mapping logic mechanism comprising at least a first logic means and a second logic means coupled in sequence and arranged to carry out similar logical steps, and the block cipher means comprising shift register means for holding the output of the stream cipher means and a second logic mapping mechanism, comprising at least a first logic means, a second logic means, a third logic means and a fourth logic means coupled in sequence being arranged to carry out similar logical steps.

Description:
The present invention relates to digital video broadcasting. 
     With the advent of digital video broadcasting (DVB), various standards have been set for design of equipment. In particular, a standard, known as the DVB descrambler algorithm has been set by the ETSI Committee for descrambling scrambled video information, such as may be required in pay-on-demand situations. There is a requirement for such algorithm to handle compressed video data, compressed according to the well known MPEG standards. The application of the DVB descrambler algorithm to typical MPEG transport data streams requires the ability to process data at rates of at least 60 MBits per second. Typical transport devices operate from a standard video clock of 27 MHz which is readily available in MPEG system designs. A straightforward implementation of the DVB descrambler algorithm using the 27 MHz clock is unable to meet a data throughput of 60 MBits per second. 
     The DVB descrambling algorithm consists of two ciphers, a stream cipher and a block cipher. These ciphers are described in the DVB Common Scrambling Specifications, and are specified as a step register and a step to step mapping between logical stages or conditions of the ciphers. The stream cipher requires 4 time sequential steps of the step register to process each byte of scrambled data and the block cipher requires 56 time sequential steps of the respective step register to process each 8 byte block of scrambled data. A straightforward implementation of the algorithm involves implementing the step registers as flip-flops and the step to step mappings as asynchronous logic between the flip-flop outputs and inputs. The minimum clock frequency required to support 60 Mbits/second with the stream cipher is 30 MHz and for the block cipher is 52.5 MHz in order to clock the step registers through the respective steps. Whilst it would clearly be possible to provide two separate clocks, one at 52.5 MHz and the other at 27 MHz, this is an expensive solution. 
     SUMMARY OF THE INVENTION 
     It is clearly advantageous in terms of cost and simplicity to use the same clock for the descrambling function as for the other transport processing functions. The present invention seeks to avoid the use of an extra 52.5 MHz clock by providing an implementation of the descrambling algorithm which requires only a single clock. 
     The present invention provides apparatus for descrambling broadcast video data, comprising a stream cipher means having an input to receive scrambled video data, and an output coupled to a block cipher means, the block cipher means having an output for providing descrambled data, wherein the stream cipher means includes shift register means for holding input data coupled to a first logic mechanism for moving the stream cipher means between logical states and for providing a stream cipher output, the first logic mechanism comprising at least a first logic means and a second logic means coupled in sequence and arranged to carry out similar logical steps, and the block cipher means including shift register means for holding the output of the stream cipher means and including a second logic mechanism coupled to the shift register means, for moving the block cipher between logical states, and having an output for providing descrambled data, the second logic mechanism comprising at least a first logic means, a second logic means, a third logic means and a fourth logic means coupled in sequence and being arranged to carry out similar logical steps. 
     In accordance with the invention, it is possible to speed up the descrambling operation since logical steps required for descrambling may be carried out by said logic means essentially at the same time or at least within a very short time period. The term logic mechanism as used above is equivalent to the term mapping logic as used herein, in the sense that the logic maps or moves a cipher between its logical states in carrying out a ciphering operation. 
     In accordance with the invention, the throughput of the cipher is increased without increasing the clocking rate by performing multiple steps of operation in each clock cycle. The ciphers contain register means implemented as flip-flops. In order to carry out multiple steps the mapping logic to calculate one step is duplicated more than once and connected serially. Thus since the stream cipher has two sets of mapping logic then as will become clear below only 2 clock cycles are required to calculate the four steps required per scrambled byte. Similarly since the block cipher contains four sets of mapping logic then only 14 clock cycles (as will become clear below) are required to process each 8 byte block of scrambled data. For these cases the minimum clock rates required to process scrambled data at 60 Mbits/second are 13.125 MHz for the stream cipher and 26.25 MHz for the block cipher. 
     This approach can be extended to a total of 4 steps for the stream cipher and 8 steps for the block cipher before it is necessary to increase the clock frequency for higher performance. These values yield a theoretical maximum data processing rate of 216 MBits/second for the stream cipher and 246 MBits/second for the clock cipher. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A preferred embodiment of the invention will now be described with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of an implementation of the DVB descrambling algorithm, including a block cipher and a stream cipher; 
     FIGS. 2 is a block diagram of a recommended implementation of the stream cipher of the DVB algorithm; 
     FIG. 3 is a block diagram of a recommended implementation of the block cipher of the DVB algorithm; 
     FIGS. 4 and 5 are generalised block diagrams of an implementation of the stream cipher and block cipher respectively, for the DVB algorithm, in accordance with a preferred embodiment of the invention; and 
     FIG. 6 is a schematic view of an integrated circuit chip incorporating the circuits of FIGS. 4 and 5. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, this shows an implementation of the descrambling algorithm, according to the recommendations of the ETSI Committee. An input 2 provides an input data stream to a first input 4 of an exclusive OR gate 6. The data is also applied to the input of a stream cipher unit 8 whose output is coupled to a second input 10 of the exclusive OR gate, the output of which is applied to a serial input of a shift register 12 (denoted herein as Reg 1). The serial output of the Reg 1 is coupled via a switch 14 either to the serial input of a second shift register 16 (denoted herein as Reg 2), or to an input of an exclusive OR gate 18. A parallel output 20 of Reg 1 is coupled to the input of a block cipher unit 22, whose output is applied to the parallel input 24 of Reg 2. The output of Reg 2 is applied to an input of exclusive OR gate 18, where it is combined with the data at the other input in order to provide descrambled data at an output 26. The notation in FIG. 1 is as follows: 
     k indexes bytes through the stream 
     p end of a scrambled field 
     n number of complete 8 bytes blocks in a scrambled field 
     r the residue that is left in a scrambled field after the last complete 8 byte block of that scrambled field 
     Referring now to FIG. 2, this shows a recommended implementation of the stream cipher unit 8 of FIG. 1. The stream cipher is a finite state machine with 107 state bits organised as 26 nibbles (4 bits per nibble) and 3 bits: 10 nibbles in register A, denoted as A1 to A10; 10 nibbles in register B, denoted as B1 to B10; 1 nibble in each register X, Y, Z, D, E and F; 1 bit in each register p, q and r. The finite state machine evolves by successive logical states or steps, the common key CK entering at the reset state. The first scrambled block SB(1) of 88 bytes (sb(1) . . . sb(8)) enters within the next 32 steps, namely the 32 steps of initialisation. Each scrambling byte is produced within 4 steps of generation. The step of reset is performed before any use of the stream cipher: the first 32 bits of CK are loaded in the state registers A1 to A8 i.e., in a1 to a32 bits and the last 32 bits of CK in the state registers B1 to B8 i.e., in b1 to b32. The other state registers, i.e., A9, A10, B9, B10, D, E, F, X, Y, Z, p, q and r, are set to 0. 
     In FIG. 2, the values of the registers, together with the value of the input byte, are processed according to the lines and arrows. The results of these operations appear on arrows entering the registers A1, B1, X, Y, Z, D, F and r which store these values as the results of the step. Each byte of a scrambled block SB(1) is loaded in 4 steps of initialisation; the first block SB(1) is thus loaded in 32 steps of initialisation as a sequence of 32 input bytes. At each step of initialisation the ms nibble of the input byte, denoted as IN1 is fed to transformation T1 and the 1s nibble IN2 to transformation T2. Moreover, nibble D is fed back to transformation T1. At each step of generation, there is no input byte and no feed back of nibble D. The 4 bits of register D are XORed two by two for producing two output bits. Consequently, four consecutive steps of generation are needed for producing one scrambling byte. 
     In registers A and B, the nibble with number i (i from 1 to 10, numbering from left to right) consists of bits 4i-3 to 4i-2, 4i-1 and 4i. The bits of A and B are respectively denoted as a1 to a40 and b1 to b40. Transformation T1 results in a nibble by XOR-ing all its input nibbles. The 4 bits resulting from T1 are fed in to A1, namely a1 a2 a3 a4. The input nibbles are A10, X, IN1 and D during a step of initialization, and A10 and X during a step of generation. 
     Transformation T2 first results in a nibble by XOR-ing all its input nibbles. The 4 bits are denoted as w1 w2 w3 w4. Depending upon the value of p, either w1 w2 w3 w4 (p=0) or w2 w3 w4 w1 (p=1) are fed into B1, namely b1 b2 b3 b4. The input nibbles are B7, B10, Y and IN2 during a step of initialization and B7, B10 and Y during a step of generation. The specification provides a table to fix how to extract 16 bits from B and how to XOR them 4 by 4 for producing an extra nibble for T3. 
     Transformation T3 results in a nibble by XOR-ing all its input nibbles, i.e., E, Z and the aforementioned extra nibble constructed from B. Register D stores the 4 bits resulting from T3, for providing two output bits via exclusive OR gates. 
     Transformation T4 results in 5 bits, consisting of a carry and a nibble, for updating respectively bit r and nibble F. Depending upon the value of q transformation T4, either (q=0) presents the current values of r and E, or (q=1) adds nibble Z, nibble E and bit r for obtaining a carry and a nibble. From register A, 35 bits are selected as inputs to 7 S-boxes, namely 5 bits for each S-box. The standard specification provides a table for the S-boxes (substitution boxes). The registers X, Y, Z, p and q store the 14 bits resulting from the 7 S-boxes in a given permuted order. c1 to c14 denote the resultant 14 bits. Nibble X consists of the bits c1 to c4. Nibble Y consists of the bits c5 to c8. Nibble Z consists of c9 yo c12. The bit p is c13. The bit q is c14. 
     Referring now to FIG. 3, this shows the block cipher unit in more detail in its recommended form, according to the ETSI specification. The current data block B consists of 8 bytes denoted as b(1), b(2), . . . b(8). The input block is loaded into a block register R consisting of 8 byte registers R1, R2, . . . R8, namely b(i) into Ri. The algorithm is performed in 56 steps of operations. At the end of 56 steps, the output block is taken from the block register R namely b(i) from Ri. Each step performs operations on the 8 registers and under the control of a single key byte. The sequence of 56 key bytes for decipherment are kk(56) to kk(1). The 56 key bytes are deduced from the common key by a key schedule operation. The function labelled S-box comprises a table look up in which the input byte, regarded as an address i the range from 0 to 255, accesses a table and reads out a number in the same range, which is the output byte. The table is a permutation of the integers 0. 1, 2, . . . 255. Consequently, any two different inputs give two different outputs. The function labelled Perm permutes the bits within a byte. 
     According to FIG. 3, the values of the registers R1 to R8, together with the key byte kk(i), are processed according to the lines and arrows. The operations take place in parallel for each step. All operations are on one byte. The results of these operations appear on arrows entering the registers. The registers R1 to R8 store those results. There is a defined key schedule defining the derivation of the 56 key bytes kk(1) to kk(56) from the common key ck(1) to ck(8). The 56 steps of the block cipher are divided into 7 rounds of 8 steps. The construction of the 56 key bytes implies an intermediate sequence denoted as kb(1, 1), kb(1, 2), . . . kb(1, 7), kb(1, 8), . . . kb(7, 1) . . . kb(7, 2) . . . kb(7, 7), db(7, 8). The 8 bytes ck(1) to ck(8) are equal to kb(7, 1) to kb(7, 8). For each round n, a key register holds the 8 bytes kb(n, 1) to kb(n, 8). The key register for the round n-1 is derived from the key register for the round n by a 64-bit permutation called kd-perm. The successive key register values are obtained by using the kd-perm transformation between decipherment rounds. At each round n (n is valued for 1 to 7), the key byte kk(7n-7+i) results from XOR-ing the byte kb(n, i) with the byte valued to n-1. 
     Referring now to FIG. 4, this shows a generalised form of block diagram of a stream cipher unit in accordance with the invention wherein a shift register 40 holds input data and a mapping logic mechanism 42 comprises a first mapping logic unit 44 coupled to the shift register 40 and a second mapping logic unit 46 connected in series with the first logic unit 44 so they perform sequential logic operations, the outputs of logic units 44, 46 being coupled back to the shift register 40, and the output of logic 46 providing an output signal at 48. Each logic unit 44, 46 is arranged to carry out the operations and transformations shown in FIG. 2. Insofar as logics 44, 46 merely perform logical operations and do not contain shift registers or memory elements, they performed the requisite operations practically instantaneously, or at any rate within the space of a very few clock cycles. FIG. 2 requires four state cycles to accomplish its operation, whereas the arrangement shown in FIG. 4, producing at the output within each state cycle 4 output bits (2 bits per logic means), requires only two state cycles to produce an output byte. 
     Referring now to FIG. 5, this shows a generalised form of block diagram of a block cipher unit in accordance with the invention, wherein a shift register 50 receives input data and is coupled to a logic mechanism 52 comprising first, second, third and fourth mapping logic units 54, 56, 58 and 60 connected in series so as to perform logical operations within the same state cycle. The outputs of the logic units are coupled back to the input of the shift register and the state of register 50 at tie end of the deciphering operations provides an output 62, representing descrambled data. 
     Each mapping logic is arranged to perform the logical operations shown in FIG. 3. As described above, the unit shown in FIG. 3 requires 56 machine cycles to carry out the algorithm. The arrangement shown in FIG. 4 takes only 14 machine cycles of operation to produce a deciphered output. 
     There will now be described a detailed implementation of the unit shown in FIGS. 4 and 5. In accordance with current engineering practice, these detailed implementations will be described in terms of a software routine defined in a hardware programming language VHDL. As will be appreciated it is current engineering practice to produce hardware units from a software routine, by arranging for a computer to take the programming steps and generate directly therefrom chip lay-outs and masks. Thus there is not normally implemented detailed functional block diagrams in producing the chip shown in FIG. 6. 
     BLOCK CIPHER IMPLEMENTATION 
     Thus there will now be described a detailed implementation of the block cipher unit of FIG. 5. This following is a VHDL description that implements the block cipher defined in the DVB common scrambling specifications. The specifications detail a number of transforms and mappings which advance the state of a machine. Each of these transforms and mappings have a corresponding VHDL function or procedure defined in this file. The overall behaviour for calculating the next state of the machine from the current state and inputs is provided in the `p --  bc --  one --  step` procedure as a series of calls to the transform and mapping procedures and functions. The VHDL processes `step --  proc` and `clock --  proc` then build this next state generation into a synchronous state machine which advances four states per clock cycle. 
     The ETSI common scrambling specifications use a different bit notation to the commonly used notation of `0` as LSB and largest number as MSB. They use `1` as MSB and largest number as LSB. To help with clear translation from specification to VHDL code the code also uses this same, DVB common scrambling specifications defined, notation. 
     The following extract of VHDL code illustrates the process of multiple mapping logic to calculate more than one step. In the code the procedure `p --  bc --  one --  step` calculates one step of the clock cipher operation, and the process `step --  proc` calculates four steps of operation by repetitive calling of the procedure `p --  bc --  one step`. Each successive call takes the output of the previous call as input, the final call giving as output the value to be recorded in the step flip-flops. 
     
         ______________________________________step.sub.-- proc : process(step.sub.-- count, current.sub.-- state,mode, ck, curr.sub.-- kb, dataIn, kki)variable step1.sub.-- in        : t.sub.-- r1r2;variable step1.sub.-- out        : t.sub.-- r1r2;variable step2.sub.-- out        : t.sub.-- r1r2;variable step3.sub.-- out        : t.sub.-- r1r2;variable step4.sub.-- out        : t.sub.-- r1r2;beginstep1.sub.-- in :=current.sub.-- state;if(mode = RUN or mode =  PERM) thenp.sub.-- bc.sub.-- one.sub.-- step( step1.sub.-- in,            kki, 4*step.sub.-- count,                          step1.sub.-- out);p.sub.-- bc.sub.-- one.sub.-- step( step1.sub.-- out,            kki, 4*step.sub.-- count+1,                          step2.sub.-- out);p.sub.-- bc.sub.-- one.sub.-- step( step2.sub.-- out,            kki, 4*step.sub.-- count+2,                          step3.sub.-- out);p.sub.-- bc.sub.-- one.sub.-- step( step3.sub.-- out,            kki, 4*step.sub.-- count+3,                          step4.sub.-- out);next.sub.-- state &lt;= step4.sub.-- out;elsif( mode = HOLD) thennext.sub.-- state &lt;= current.sub.-- stateelsif( mode = LOAD) thennext.sub.-- state &lt;=  dataIn;end if;dataOut &lt;= current.sub.-- state;end process step.sub.-- proc;______________________________________ 
    
     Each iteration p --  bc --  one --  step is carried out by one of the mapping logics 54-60 of FIG. 5. 
     A more detailed implementation is as follows:- 
     
         ______________________________________entity dsc.sub.-- bc.sub.-- top isport ( ck :     in    t.sub.-- key;common key form key filereset.sub.-- b     :      in      std.sub.-- logicsystem.sub.-- resetmode             in      t.sub.-- bc.sub.-- mode;bc mode from control blocksclk             in      std.sub.-- logic;system clockdataIn           in  :                    t.sub.-- r1r2;current value of reg1round.sub.-- count     :      in   integercounter from control                 range 0 to 7;step.sub.-- count      :     in   integercounter from control                 range 0 to 1;dataOut          out    t.sub.-- r12rdata to load into reg2);end dsc.sub.-- bc.sub.-- top;architecture behave of dsc.sub.-- bc.sub.-- top isFunction  :f.sub.-- bc.sub.-- perm______________________________________ 
    
     This function performs the bit perm function defined in the common scrambling specifications. 
     function f --  bc --  perm(d: byte) return byte is 
     variable result: byte; 
     begin 
     result(1):=d(7) 
     result(2):=d(3) 
     result(3):=d(6) 
     result(4):=d(5) 
     result(5):=d(1) 
     result(6):=d(4); 
     result(7):=d(8) 
     result(8):=d(2) 
     return(result); 
     end f --  bc --  perm; 
     Function :f --  bc --  kdPerm 
     This function performs the kd perm function defined in the common scrambling specifications. It is used to generate the next kb value from the previous kb value between de-cipherment rounds. 
     Function :f --  bc --  kk --  gen 
     This function generates the Idd word from the 64 bit kb word and the count number of the current de-cipherment round. 
     Function :f --  bc --  sbox --  in --  gen 
     This function generates the s-box input value from the current value of r7 and kki. 
     
         ______________________________________function   f.sub.-- bc.sub.-- sbox.sub.-- in.sub.-- gen(kki            : t.sub.-- key;r7                     : byte;step.sub.-- count          : integer range 0 to 7return byte isvariable s.sub.-- box.sub.-- in : byte;begincase( step.sub.-- count) is  when7 =&gt; s.sub.-- box.sub.-- in: = kki(1 to 8)  xor r7;  when6 =&gt; s.sub.-- box.sub.-- in: = kki(9 to 16)  xor r7;  when5 =&gt; s.sub.-- box.sub.-- in: = kki(17 to 24) xor r7;  when4 =&gt; s.sub.-- box.sub.-- in: = kki(25 to 32) xor r7;  when3 =&gt; s.sub.-- box.sub.-- in: = kki(33 to 40) xor r7;  when2 =&gt; s.sub.-- box.sub.-- in: = kki(41 to 48) xor r7;  when1 =&gt; s.sub.-- box.sub.-- in: = kki(49 to 56) xor r7;  when0 =&gt; s.sub.-- box.sub.-- in: = kki(57 to 64) xor r7;  when others =&gt; NULL;end case;return(s.sub.-- box.sub.-- in);end;Function  : f.sub.-- bc.sub.-- sBox______________________________________ 
    
     This function implements the s --  box mapping defined in the common scrambling specifications. It is modelled as a look up table. 
     Procedure :p --  bc --  one --  step 
     This procedure implements the architecture diagram of the block cipher given in FIG. 3. Each of the s-box and perm generation functions defined in the specification are implemented as functions in the preceding code. This procedure calls these functions appropriately to implement one step of the decipherment defined in the architecture diagram. 
     
         ______________________________________procedure p.sub.-- bc.sub.-- one.sub.-- step(current.sub.-- state      : in t.sub.-- r1r2;kki              : in t.sub.-- key;step.sub.-- count         : in integer range 0 to 7;next.sub.-- state         : out t.sub.-- r1r2) isvariable perm.sub.-- out      : byte;variable sbox.sub.-- in      : byte;variable sbox.sub.-- out      : byte;beginsbox.sub.-- in   : = f.sub.-- bc.sub.-- sbox.sub.-- in.sub.-- gen( kki,      current.sub.-- state(7), step.sub.-- count );sbox.sub.-- out   : = f.sub.-- bc.sub.-- sbox(sbox.sub.-- in);perm.sub.-- out   : = f.sub.-- bc.sub.-- perm(sbox.sub.-- out);next.sub.-- state(1): = current.sub.-- state(8) xor sbox.sub.-- out;next.sub.-- state(2): = current.sub.-- state(1);next.sub.-- state(3): = current.sub.-- state(2) xor (current.sub.--state(8) xor sbox.sub.-- out);next.sub.-- state(4): = current.sub.-- state(3) xor (current.sub.--state(8) xor sbox.sub.-- out);next.sub.-- state(5): = current.sub.-- state(4) xor (current.sub.--state(8) xor sbox.sub.-- out);next.sub.-- state(6): = current.sub.-- state(5);next.sub.-- state(7): = current.sub.-- state(6) xor perm.sub.-- out;next.sub.-- state(8): = current.sub.-- state(7);end;______________________________________ 
    
     The block cipher is constructed as a four step per clock cycle circuit. The implementation of one step is identical to the architecture diagram of FIG. 3. The preceding functions are written directly from that diagram using the same nomenclature. Calling the procedure `p --  bc --  one --  step` results in the next step values being calculated for the entire block cipher. 
     To achieve a four steps per clock implementation the process `step --  proc` calls `p --  bc --  one --  step` four times, passing the output from the first pass as the input to the second pass etc. Each step is implemented by a respective one of mapping logics 54-60 of FIG. 5. The process `clock --  proc` registers the output of the fourth pass using the system clock, and this is used as the input to the first pass next time through `step proc`. 
     Control of the block cipher is achieved by applying correctly round-count, step --  count and mode. round --  count and step --  count are as described in the common scrambling specifications, except we only need the MS bit of step --  count since we have a four step per clock cycle block cipher. Mode specifies whether the block cipher is running (RUN or PERM), generating a new kb value (PERM), holding (HOLD) or loading a new 8 byte block (LOAD). 
     signal curr --  kb : t --  key; 
     signal next --  kb : t --  key; 
     signal current --  state: t --  r1r2; 
     signal next state : t --  r1r2; 
     signal kld : t --  key; begin 
     Process : kb --  proc 
     This process generates the next value of kb depending upon the mode of the block cipher. The value next --  kb is calculated for registering by clock --  proc to generate curr --  kb. 
     Process : kki --  proc 
     This process calculates the value of kki. 
     Process : step --  proc 
     This process calculates the next registered state of the block cipher depending upon the mode of the block cipher. For RUN or PERM modes four steps of operation are calculated. For HOLD mode the state is held and for LOAD mode the 8 bytes on input data in are loaded in the state register. 
     
         ______________________________________step.sub.-- proc       : process( step.sub.-- count, current state, mode, ck, curr.sub.-- kb dataIn, kki variable step1.sub.-- in           : t.sub.-- r1r2;variable step1.sub.-- out           : t.sub.-- r1r2;variable step2.sub.-- out           : t.sub.-- r1r2;variable step3.sub.-- out           : t.sub.-- r1r2;variable step4.sub.-- out           : t.sub.-- r1r2;begin______________________________________ 
    
     Now depending on the mode of operation we either load the next set of data from the inputs, hold the current state or generate four steps of operation. As far as step calculation is concerned PERM operation is the same as RUN operation. 
     
         ______________________________________stepl.sub.-- in : =  current.sub.-- state;if ( mode =  RUN or mode =  PERM) thenp.sub.-- bc.sub.-- one.sub.-- step( step1.sub.-- in,           kki, 4*step.sub.-- count,                         step1.sub.-- out);p.sub.-- bc.sub.-- one.sub.-- step( step1.sub.-- out,            kki, 4*step.sub.-- count+1,                         step2.sub.-- out);p.sub.-- bc.sub.-- one.sub.-- step( step2.sub.-- out,            kki, 4*step.sub.-- count+2,                         step3.sub.-- out);p.sub.-- bc.sub.-- one.sub.-- step( step3.sub.-- out,            kki, 4*step.sub.-- count+3,                         step4.sub.-- out);next.sub.-- state &lt;=  step4.sub.-- .sub.-- out;elsif( mode =  HOLD) then next.sub.-- state &lt;=  current.sub.-- state;elsif( mode = LOAD) then next.sub.-- state &lt;=  dataIn;end if;dataOut &lt;=  current.sub.-- state;end process step.sub.-- proc;Process  : clock.sub.-- proc______________________________________ 
    
     This process clocks all registered data into their registers. 
     
         ______________________________________configuration dsc.sub.-- bc.sub.-- top.sub.-- con of dsc.sub.-- bc.sub.--top isfor behaveend for;d dsc.sub.-- bc.sub.-- top.sub.-- con;______________________________________ 
    
     STREAM CIPHER IMPLEMENTATION 
     This following file contains a VHDL description that implements the stream cipher described above with reference to FIGS. 2, which details a number of transforms and mappings which advance the state of a machine. Each of these transforms and mapping have a corresponding VHDL function or procedure defined in this file. The overall behaviour for calculating the next state of the machine from the current state and inputs is provided in the `p --  one --  step` procedure as a series of calls too the transform and mapping procedures and functions. The VHDL processes `step --  proc` and `clock --  proc` then build this next state generation into a synchronous state machine which advances two states per clock cycle. Each state is implemented by one of mapping logics 44 or 46 of FIG. 4. 
     
         ______________________________________entity dsc.sub.-- sc.sub.-- top isport ( sclk  : in std.sub.-- logic;system clock inputreset.sub.-- b       : in std.sub.-- logic;system resetinput.sub.-- byte       : in byte;input byte from the                     scrambled streamcommon-key  : in t.sub.-- key;common key from the                     key filemode        : in t.sub.-- sc.sub.-- mode;defines RESET, INIT,                    GEN or HOLD modessb          : out byteoutput byte for XORing                    with stream);end dsc.sub.-- sc.sub.-- top;______________________________________ 
    
     architecture behave of dsc --  sc --  top is 
     Function : f --  t1 
     This function performs the T1 transform for the stream cipher. 
     Function : f --  t2 
     This function performs the Tr transform of the stream cipher. 
     Function : f --  t3 
     This function performs the T3 transform for the stream cipher. 
     Function : f --  t3extra 
     The T3 transform requires an input which is a 4 by 4 XOR of bits from the `b` state. This function performs that XOR. 
     Procedure : p --  t4 
     This function implements the T4 transform of the stream cipher. State bits r and f are updated by this transform. The transform defines an addition A11 variable are ultimately std --  logic or std --  logic --  vector so they need conversion to integer to perform the addition. 
     Procedure :p --  s --  gen 
     The s-boxes require as index inputs a concatenation of various bits from the current state of `a`. This concatenation is performed by this function. Each of the 7 s-boxes has an output from this function. 
     Procedure : p --  s --  box 
     This procedure implements all seven s-boxes for the stream cipher. It accepts as input the variables s1 to s7 which are the concatenation of bits from the current state of `a`. It outputs the next state of the registers x, y, z, p and q 
     The concatenation from the `a` bits to create inputs s1 to s7 is performed using the `p --  s --  gen` procedure defined above. Consequently `p --  s --  gen` must be called before `p --  s --  box`. The s-boxes themselves are defined as look up tables which will be synthesised to random logic gates. 
     Procedure : p --  reset 
     This procedure implements the reset step of the stream cipher. 
     Procedure : p --  one --  step 
     This procedure implements FIG. 2. Each of the T transforms and the S-boxes defined have a corresponding function or procedure defined in the preceding code. This procedure calls these appropriately to cause the next value of all the state bits in the diagram to be calculated from the current values. 
     
         ______________________________________procedure p.sub.-- one.sub.-- step(   signal input.sub.-- byte                : in byte;  variable step.sub.-- input                   : in t.sub.-- stepreg;  signal mode                        : in t.sub.-- sc.sub.-- mode;  variable step.sub.-- output                  : out t.sub.-- stepreg;  variable polarity                               : inout t.sub.-- polarity) is  variable extra                     : nibble variable s1, s2, s3, s4, s5, s6, s7: nibblebegin______________________________________ 
    
     Perform shift register advance for `a` and `b` states. 
     
         ______________________________________forj in 10 downto 2 loop  step.sub.-- output.a(j)             : =step.sub.-- input.a(j-1);  step.sub.-- output.b(j)              : =step.sub.-- input.b(j-1)end loop;______________________________________ 
    
     Generate new value for `a` and `b` shift register inputs using t1 and t2. The input --  byte bits that are passed to the t1 and t2 functions differ depending on the step being odd or even. 
     Firstly generate the next value of state `a`. 
     
         ______________________________________  if (polarity = ODD) then   step.sub.-- output.a(1)=     f.sub.-- t1 (input.sub.-- byte(1 to 4),       step.sub.-- input.a(10),       step.sub.-- input.d, step.sub.-- input.x,       mode  );  else     step-output.a(1)  :=  f.sub.-- t1 (input.sub.-- byte (t to 8),       step.sub.-- input.a(10),       step.sub.-- input.d, step.sub.-- input x,       mode  );  end if;______________________________________ 
    
     Secondly generate the next value of state `b`. 
     
         ______________________________________If ( polarity =  ODD) then  step-output.b(1) =    f.sub.-- t2 (input.sub.-- byte (5 to 8),      step.sub.-- input.b(7), step.sub.-- input(b(10),      step.sub.-- input.y, step.sub.-- input.p,      mode     );else           step.sub.-- output.b(1)  :=    f.sub.-- t2 (input.sub.-- byte (1 to 4),      step.sub.-- input.b(7),step.sub.-- input.b(10),                   step.sub.-- input.y, step.sub.-- input.p,                      mode    );end if;______________________________________ 
    
     The generation of the next `d` state is a combination of generating an extra nibble from the current b&#39; state, then using transform t3. 
     
         ______________________________________extra : = f.sub.-- t3.sub.-- extra ( step.sub.-- input.b );step.sub.-- output.d : = f.sub.-- t3 ( extram, step.sub.-- input.e,step.sub.-- input.z);States `f`  and `r`  are generated using transform t4, and the next stateof`e ` is simply the current state of `f`.p.sub.-- t4( step.input.e. step.sub.-- input.z, step.sub.-- input.q,step.sub.-- input.r   step-output.r, step.sub.-- output.f);step-output.e : =  step.sub.-- input f;______________________________________ 
    
     Finally the states `x`, `y`, `z`, `p` and `q` are generated from the s-box mappings of the current state of the `a`. The s-box mappings are done in two steps. Firstly generating the s inputs from the `a` state bits using p --  s --  gen and then applying these values to the s-boxes to generate the results using p --  s box. 
     
         ______________________________________p.sub.-- s.sub.-- gen ( step.sub.-- input.a, s1, s2,, s3, s4, s5, s6, s7);p.sub.-- s.sub.-- box ( s1, s2, s3, s4, s5, s6, s7,step.sub.-- output.x, step.sub.-- output.y, step.sub.-- output.z,step.sub.-- output.p, step.sub.-- output.q);end;______________________________________ 
    
     The stream cipher is constructed as a two step per clock cycle circuit, the implementation of one step being carried out by one of the logics 44, 46. The preceding functions are written directly from that diagram using the same nomenclature. Calling the procedure `p --  one step` results in the next step values being calculated for the entire stream cipher. 
     To achieve a two steps per clock cycle implementation the process ;step --  proc` calls `p --  one --  step` twice passing the output from the pass (logic 44) as the input to the second pass (logic 46). The process `clock --  proc` registers the output of the second pass using the system clock, and this is used as the input to the first pass next time through `step proc`. 
     
         ______________________________________signal current.sub.-- state             : t.sub.-- stepreg;signal next.sub.-- state                 : t.sub.-- stepreg;signal a.sub.-- step.sub.-- counter              : std.sub.`3 logic;signal step.sub.-- counter               : std logic;signal next.sub.-- sb.sub.-- nibble              : nibble;signal int.sub.-- sb                     : byte;begin step.sub.-- proc :     process(  input.sub.-- byte, current.sub.-- state, common.sub.-- key  mode, step.sub.-- counter, int.sub.-- sb )variable polarity   : t.sub.-- polarity;variable step1.sub.-- in                : t.sub.-- stepreg;variable step1.sub.-- out              : t.sub.-- stepreg;variable step2.sub.-- out              : t.sub.-- stepreg;begin______________________________________ 
    
     On RESET condition call the p --  reset procedure. All next state registers are reset according to the DVC common scrambling specifications reset step definition. 
     
         ______________________________________    If (mode = RESET) then    p.sub.-- reset (common.sub.-- key, next.sub.-- state );    next.sub.-- sb.sub.-- nibble &lt;= `0000`;  elsif ( mode = HOLD) then      next.sub.-- state &lt;= current.sub.-- state;    if (step.sub.-- counter = `0`  ) then    next.sub.-- sb.sub.-- nibble &lt;=  int.sub.-- sb(1 to 4);  else      next.sub.-- sb.sub.-- nibble &lt;= int.sub.-- sb(5 to 8);    end if;  else______________________________________ 
    
     If not in RESET or HOLD we are in either INIT or GEN. Both these conditions are implemented by the `p --  one --  step` procedure. In addition we need to tell `p --  one --  step` whether we are at an odd or even call number from the RESET condition. The application of the input --  byte to some of the transforms changes between ODD and EVEN. 
     The state input to the first pass through `p --  one --  step` is the current registered state. After the second pass through `p --  one --  step` the output of the procedure is assigned to the `next state` signal which is subsequently registered on the next clock edge. 
     
         ______________________________________   step1.sub.-- in           : =  current.sub.-- state;   polarity           : ODD;   p.sub.-- one.sub.-- step(     input-byte, step1.sub.-- in,     mode, step1.sub.-- out, polarity);     polarity: =  EVEN     p.sub.-- one.sub.-- step(           input.sub.-- byte, step1.sub.-- out.       mode, step2.sub.-- out,polarity     );     next.sub.-- state &lt;=  step2.sub.-- out;______________________________________ 
    
     If, in INIT then the stream cipher has no defined output and we must pass the data into reg1 unaffected. Ensure this by forcing the output to all 
     
         ______________________________________If (mode =  GEN) then next.sub.-- sb.sub.-- nibble &lt;=  (step1.sub.-- out.d(1) xor step1.sub.-- out.d(2) ) &amp;  (step1.sub.-- out.d(3) xor step1.sub.-- out.d(4) ) &amp;  (step2.sub.-- out.d(1) xor step2.sub.-- out.d(2) ) &amp;  (step2.sub.-- out.d(3) xor step2.sub.-- out.d(4) ) &amp;else next.sub.-- sb.sub.-- nibble &lt;= `0000`;end if;end if;end process step.sub.-- proc;reset.sub.-- proc; process (step.sub.-- counter, mode)beginif (mode - RESET) thena.sub.-- step.sub.-- counter &lt;= `0`;elsif (mode =  HOLD) then   if (step.sub.-- counter = `0`) thena.sub.-- step.sub.-- counter &lt;=  `1`else   a.sub.-- step.sub.-- counter &lt;= `0`end if;else  a.sub.-- step.sub.-- counter &lt;= step.sub.-- counter;end if;and process rest.sub.-- proc;endconfiguration dsc.sub.-- sc.sub.-- top.sub.-- con of dsc.sub.-- sc.sub.--top is for behaveend for;end dsc.sub.-- sc.sub.-- top.sub.-- con;______________________________________