Abstract:
A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization.

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to the fabrication of semiconductor integrated circuits. More specifically, the present invention relates to the arrangement of the metal interconnect structures employed in integrated circuits. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits (IC) are manufactured by forming discrete semiconductor devices on a surface of a semiconductor substrate, such as a silicon wafer. A multi-level network of interconnect structures is then formed to interconnect the devices. Copper is the material of choice for interconnect structures of advanced IC devices having high circuit density. In addition to superior electrical conductivity, copper is more resistant than aluminum to electromigration, a phenomenon that may destroy a thin film conductive line during IC operation. 
     An IC device comprises a plurality of interconnect structures that are separated from each other and the substrate by the ILD layers. Such structures are generally fabricated using a dual damascene technique that comprises forming an insulator layer (e.g., ILD layer) into which trenches and openings are etched to pattern the conductive lines and contact holes, or vias. The copper is then used to fill (metallize) the trenches and openings in the IMD layer forming the conductive lines and vias, respectively. During the copper metallization process, an excess amount of copper may be deposited onto the substrate. The excess metal may be removed using a planarization process, e.g., chemical-mechanical polishing (CMP) process. After the planarization process, the interconnect structure is embedded in the ILD layer coplanar with an exposed surface of the layer, such that the next wiring layer may be formed on top of the embedded ILD layer. 
     In the semiconductor industry, much effort is spent in developing smaller IC devices with ever-increasing operating speeds. To increase the circuit density, a dual damascene technique may be used during fabrication of the IC devices. To increase the operating speed of such a device, the ILD layers are formed using materials having dielectric constants less than about 4.0. Such materials are generally referred to as low-k materials. The low-k materials generally comprise carbon-doped dielectrics, such as organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), organic polymers, and the like. 
     While performance of the active elements in an IC device generally increases as the size of the IC device decreases, this is not the case for the interconnect structures because the resistance and capacitance of the conductive lines increase as the device size decreases. This relationship between interconnect size and performance is sometimes referred to as the Reverse-Scaling Rule (RSR). Because of RSR, the increase in resistance and capacitance of the conductive lines is becoming a dominant factor in determining circuit performance. As a result, continued reductions in IC device size do not simply lead to improved circuit performance, but may lead to worse performance. 
     The reverse-scaling rule can be particularly problematic when a new generation of an existing IC device is being developed. The most straightforward way to reduce an existing IC device in size is to simply reduce all the lateral dimensions of the various elements with respect to the previous generation. Because of the reverse-scaling rule, however, this cannot be done for the interconnect structure without sacrificing performance. 
     Accordingly, it would be desirable to provide a procedure for using the same interconnect architecture used in the previous generation and adapting it for a new, smaller generation of IC devices to thereby avoid the need for designing an entirely new interconnect architecture. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization. 
     In accordance with one aspect of the invention, at least a subset of the lines in the given level of metallization each have conductive vias vertically extending therefrom. 
     In accordance with another aspect of the invention, a subset of lines in the second level of metallization have a recess for preventing an electrical short with one of the vertically extending vias that is adjacent thereto. 
     In accordance with another aspect of the invention, an integrated circuit is formed in accordance with the reduced lateral dimension design set forth above. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a cross-sectional view of an IC device having an interconnect structure in which the conductive lines are formed in trenches by a dual damascene process. 
         FIG. 2  shows the conductive lines and vias from the interconnect structure of  FIG. 1  without the remaining features of the IC device. 
         FIG. 3  shows the architecture of the conductive lines after they have been rearranged into two levels in accordance with one embodiment of the present invention. 
         FIG. 4(   a ) shows a cross-sectional view taken along line I-I in  FIG. 4(   b ) and  FIG. 4(   b ) shows a plan view of one embodiment of the interconnect structure constructed in accordance with the present invention. 
         FIGS. 5-13  show cross-sectional views illustrating the formation of a dual damascene structure constructed in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The methods and structures described herein do not form a complete process for manufacturing semiconductor device structures. The remainder of the process is known to those of ordinary skill in the art and, therefore, only the process steps and structures necessary to understand the present invention are described herein. 
     The present invention can be applied to microelectronic devices, such as highly integrated circuit semiconductor devices, processors, micro electromechanical (MEM) devices, optoelectronic devices, and display devices. In particular, the present invention is highly useful for devices requiring high-speed characteristics, such as central processing units (CPUs), digital signal processors (DSPs), combinations of a CPU and a DSP, application specific integrated circuits (ASICs), logic devices, and SRAMs. 
     As used herein the term “vertical” refers to the direction perpendicular to the plane of the IC substrate, regardless of the orientation of the substrate. Likewise, the terms “above” and “below” refer to relative locations in the vertical direction that are more remote from, or closer to, the substrate, respectively. 
       FIG. 1  shows a cross-sectional view of an IC device having an interconnect structure in which the conductive lines are formed in trenches by a dual damascene process. The IC device is formed on a substrate  100 . A lower ILD  105 , including lower interconnections  110 , is formed on the substrate  100 . Various active devices and passive devices may be formed on the substrate  100 . The lower interconnection  110  may be formed of various interconnection materials, such as copper, copper alloy, aluminum, and aluminum alloy. The lower interconnection  110  is preferably formed of copper because of its low resistance. 
     The interconnect structure includes a series of parallel conductive lines  165  (lines  165   1 - 165   6 ) that are electrically isolated from one another by ILD  130 . Vias  150  electrically connect the lines  165  to the lower interconnections  110 . In the particular cross-section shown in  FIG. 1 , lines  165   1 ,  165   3 ,  165   4 , and  165   6  are respectively connected to lower interconnection  110   1 ,  110   3 ,  110   4 , and  110   6  by vias  150   1 ,  150   3 ,  150   4 , and  150   6 , respectively. 
     When a new generation of an existing IC device is being developed, the simplest way to reduce it in size is to simply reduce all the lateral dimensions of the various elements with respect to the previous generation. Because of the reverse-scaling rule, however, this cannot be done for the interconnect structure without sacrificing performance. The present invention provides a procedure for using the same interconnect architecture used in the previous generation and adapting it for a new, smaller generation of IC devices. In this way the need for designing an entirely new interconnect architecture can be avoided. 
     In accordance with the present invention, a single metal level in the interconnect structure, such as the metal level formed by lines  165   1 - 165   6  in  FIG. 1 , is divided into two or more separate metal levels. Then, if the level is divided into two levels, for instance, the width of each line is selected to be twice what the width would otherwise be after all the lateral dimensions of the various elements have been reduced by the desired amount. 
     For clarity in understanding the principles of the present invention,  FIG. 2  shows the conductive lines  165  and vias  150  from the interconnect structure of  FIG. 1  without the remaining features of the IC device. The dimensions of the lines  165  in  FIG. 2  are assumed to have been already reduced from those in  FIG. 1 , along with the lateral dimensions of the other elements in the IC device. That is, the lines  165  in  FIG. 2  each have a width W that is less than their original width in the previous generation IC device of  FIG. 1 . 
       FIG. 3  shows the architecture of the lines  165  after they have been rearranged into two levels in accordance with the present invention. As shown, each line now has a width of 2 W. Since the width of the individual lines has been increased, degradations in performance arising from the reverse-scaling rule have been reduced. However, this increase in width has not been at the expense of any overall increase in the lateral dimension of the interconnect structure. That is, as  FIG. 3  shows, the total width X occupied by any two adjacent lines in  FIG. 2  is the same as the total width occupied by any two adjacent lines shown in  FIG. 3 . This is accomplished by staggering the lines in each level so that each line in the lower level (lines  165   2 ,  165   4 ,  165   6 ) is situated in part below one of the lines in the upper level (lines  165   1 ,  165   3 ,  165   5 ). In the embodiment of the invention depicted in  FIG. 2  in which one metal level has been divided into two levels of metal, half of each line in the lower level is situated below one of the lines in the upper level. In this way two adjacent lines on different levels (e.g., lines  165   1  and  165   2 ) only occupy as much space in the lateral direction as the same two lines in  FIG. 2 . Put another way, the width of the lines in  FIG. 3  have been increased over that in  FIG. 2  at the expense of an increase in the vertical dimension they occupy instead of an increase in the lateral dimension they occupy. 
     One problem that can arise when a level of metal is divided into two or more levels as depicted in  FIG. 3  is that an electrical short may occur whenever a line on the lower level contacts a via of an adjacent line of the upper level. For instance, in  FIG. 3  a short may arise between line  165   2  and via  150   1  as well as between line  165   4  and via  150   3 . As detailed below, this problem can be overcome by reshaping those lines on the lower level that would otherwise give rise to an electrical fault so that they do not contact the adjacent via. 
       FIG. 4(   a ) shows the same cross sectional view of the two levels of metal that is depicted in  FIG. 3 .  FIG. 4(   b ) shows a plan view corresponding to the cross-sectional view of  FIG. 4(   a ). That is,  FIG. 4(   a ) is a cross-sectional view taken along line I-I in  FIG. 4(   b ). As shown in the plan view of  FIG. 4(   b ), a vertically extending recess is provided in the portion of the line in the lower level that vertically overlaps with a line in the upper level from which a via extends. That is, lines  1652  and  1654  have recesses  1702  and  1704 , respectively. Recesses  170   2  and  170   4  are filled with a dielectric. While recesses  170   2  and  170   4  are shown in  FIG. 4(   b ) as having a rectangular configuration in the plane of the substrate, the recesses more generally may have any shape desired so long as the line is which the recess is provided is electrically isolated from its adjacent via. The recesses may be formed during the lithographic process used to pattern the lines. That is, an appropriate mask is used so that when the trenches in which the lines are formed are etched, the trenches will have the desired configuration. 
     The vertical separation Y (see  FIG. 4(   a )) between the two levels of metallization should preferably be chosen to reduce or prevent crosstalk between the vertically overlapping lines. 
       FIGS. 5-13  show an exemplary process for forming the conductive lines in accordance with the present invention. For simplicity, only a single line and via are illustrated. Of course, the same process may be used to form a series of parallel lines and vias such as depicted in  FIGS. 1-4 . It should be noted that this process is presented by way of illustration only and not as a limitation on the invention. More generally, the present invention encompasses any process for forming an interconnect structure in an IC device and is not limited, for example, to the dual damascene technique presented below. In  FIGS. 1-13  like reference numerals are used to denote like elements. 
     As shown in  FIG. 5 , substrate  100  is prepared. The lower ILD  105  including a lower interconnection  110  is formed on the substrate  100 . The substrate  100  may be, for example, a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenic substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for display. As previously noted, various active devices and passive devices may be formed on the substrate  100 . The lower interconnection  110  may be formed of various interconnection materials, such as copper, copper alloy, aluminum, and aluminum alloy. The lower interconnection  110  is preferably formed of copper because of its low resistance. Also, the surface of the lower interconnection  110  is preferably planarized. 
     Referring to  FIG. 6 , an etch stop layer  120 , the low-k ILD  130 , and a capping layer  140  are sequentially stacked on the surface of the substrate  100  where the lower interconnection  110  is formed, and a photoresist pattern  145  is formed on the capping layer  140  to define a via. 
     The etch stop layer  120  is formed to prevent electrical properties of the lower interconnection  110  from being damaged during a subsequent etch process for forming a via. Accordingly, the etch stop layer  120  is formed of a material having a high etch selectivity with respect to the ILD  130  formed thereon. Preferably, the etch stop layer  120  is formed of SiC, SiN, or SiCN, having a dielectric constant of 4 to 5. The etch stop layer  120  is as thin as possible in consideration of the dielectric constant of the entire ILD, but thick enough to properly function as an etch stop layer. 
     The ILD  130  may be formed of a hybrid low-k dielectric material, which has advantages of organic and inorganic materials. That is, the ILD  130  can be formed of a hybrid low-k dielectric material having low-k characteristics, which can be formed using a conventional apparatus and process, and which is thermally stable. The ILD  130  has a dielectric constant of e.g., 3.5 or less, to prevent an RC delay between the lower interconnection  110  and dual damascene interconnections and minimize cross talk and power consumption. For example, the ILD  130  may be formed of low-k organosilicon material such as Black Diamond™, Silk™, CORAL™, or a similar material. The ILD  130  can be formed using chemical vapor deposition (CVD), and more specifically, plasma-enhanced CVD (PECVD). The ILD  130  may be also formed from low k materials such as spin-on organics and organo silicates. The ELD  130  is formed to a thickness of about 3,000 angstroms to 20,000 angstroms or other appropriate thicknesses determined by those skilled in the art. 
     The capping layer  140  prevents the ILD  130  from being damaged when dual damascene interconnections are planarized using chemical mechanical polishing (CMP). Thus, the capping layer  140  may be formed of SiO 2 , SiOF, SiON, SiC, SiN, or SiCN. The capping layer  140  may also function as an anti-reflection layer (ARL) in a subsequent photolithographic process for forming a trench. In this case the capping layer  140  is more preferably formed of SiO 2 , SiON, SiC, or SiCN. 
     The via photoresist pattern  145  is formed by forming a layer of a photoresist and then performing exposure and developing processes using a photo mask defining a via. Referring to  FIG. 7 , the ILD  130  is anisotropically etched ( 147 ) using the photoresist pattern  145  as an etch mask to form a via  150 . The ILD  130  can be etched, for example, using a reactive ion beam etch (RIE) process, which uses a mixture of a main etch gas (e.g., C x F y  and C x H y F z ), an inert gas (e.g. Ar gas), and possibly at least one of O 2 , N 2 , and CO x . Here, the RIE conditions are adjusted such that only the ILD  130  is selectively etched and the etch stop layer  120  is not etched. 
     Referring to  FIG. 8 , the via photoresist pattern  145  is removed using a plasma etch, for example. Next, referring to  FIG. 9 , a trench photoresist pattern  185  is formed, followed by formation of a trench  190  in  FIG. 10 . The capping layer  140  is etched using the photoresist pattern  185  as an etch mask, and then the ILD  130  is etched to a predetermined depth to form the trench  190 . If required, the trench photoresist pattern  185  defines the recess  170  of the trench depicted in  FIG. 4(   b ). The resulting structure, shown in  FIG. 11 , defines a dual damascene interconnection region  195 , which includes the via  150  and the trench  190 . 
     Referring to  FIG. 12 , the etch stop layer  120  exposed in the via  150  is etched until the lower interconnection  110  is exposed, thereby completing the dual damascene interconnection region  195 . The etch stop layer  120  is etched so that the lower interconnection  110  is not affected and only the etch stop layer  120  is selectively removed. 
     A barrier layer  160  is formed on the dual damascene interconnection region  195  to prevent the subsequently formed conductive layer from diffusing into ILD  130 . The barrier layer  160  is generally formed from a conventional material such as tantalum, tantalum nitride, titanium, titanium silicide or zirconium. After formation of the barrier layer  160  the copper conductive layer is formed on the barrier layer by an electroplating process. Referring to  FIG.13 , the bulk copper layer  165  is formed on the dual damascene interconnection region  195  by electroplating and then planarized, thereby forming a dual damascene interconnection  210  having conductive line  165 . 
     The aforementioned process depicted in  FIGS. 5-13  illustrates the formation of one level of metallization defined by conductive line  165 . The additional levels of metallization that are required by the present invention may be formed in a similar manner.