Abstract:
The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefit of China application serial no. 201610099443.X, filed on Feb. 23, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
       FIELD OF THE INVENTION 
       [0002]    The present invention is related to a static RAM, in particular to a static RAM for Differential Power Analysis Resistance. 
       BACKGROUND ART 
       [0003]    Static RAM is a high-performance memory extensively applied to the encrypted circuit; however, as the circuit power consumption is related to the data as read, it may be probably decoded by the differential power analysis. Output circuit of existing static RAM is single-terminal output; dual-rail pre-charge logic is not applicable to the design of static RAM due to the lack of fully identical complementary output; on the contrary, three-phase dual-rail pre-charge logic and self-timing three-phase dual-rail pre-charge logic can realize one-off charging/discharging for major nodes in each periodic circuit through addition of discharging process on SABL basis, which can overcome the disadvantage of power consumption difference incurred by inconsistent load and wiring capacitance; nevertheless, as they are requested to reset the output before the end of each cycle, it is impossible to keep the data as read; therefore, they are not applicable to the design of static RAM for defense of power attack. 
       SUMMARY OF THE INVENTION 
       [0004]    The technical issue to be settled by the present invention is to provide a static RAM for Differential Power Analysis Resistance. 
         [0005]    Technical solution used by the present invention to settle aforesaid technical issue is stated as follows: A static RAM for Differential Power Analysis Resistance, comprising a replica bit-line circuit, a decoder, an address data latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuits and n-bit output circuits; n is an integral equal to or over 1; the said decoder is connected to the said replica bit-line circuit, the said address data latch circuit, the said n-bit memory arrays and the said n-bit data selectors respectively; the said clock circuit is connected to the said replica bit-line circuit, the said n-bit input circuits, the said n-bit output circuits respectively; the said input circuit j is connected to the said data selector j; the said replica bit-line circuit is connected to the said n-bit output circuits; the said data selector j is connected to the said memory array j and the said output circuit j respectively; j=1, 2, . . . , n; the said output circuit comprises a sensitivity amplifier and a data latch circuit; the said sensitivity amplifier comprises the 1 st , the 2 nd , the 3 rd , the 4 th , the 5 th , the 6 th  and the 7 th  PMOS tubes and the 1 st , the 2 nd  the 3 rd , the 4 th  and the 5 th  NMOS tubes; source of the 1 st  PMOS tube, the 4 th  PMOS tube and the 5 th  PMOS tube is connected to the power supply respectively; drain of the 1 st  PMOS tube and source of the 2 nd  PMOS tube are connected to the source of the 3 rd  PMOS tube; drain of the 2 nd  PMOS tube, grid of the 3 rd  PMOS tube, drain of the 4 th  PMOS tube, drain of the 6 th  PMOS tube, drain of the 1 st  NMOS tube and grid of the 2 nd  NMOS tube are connected to the drain of the 4 th  NMOS tube respectively, and the connecting terminal is the 1 st  output terminal of the said sensitivity amplifier; grid of the 2 nd  PMOS tube, drain of the 3 rd  PMOS tube, drain of the 5 th  PMOS tube, drain of the 7 th  PMOS tube, grid of the 1 st  NMOS tube and drain of the 2 nd  NMOS tube are connected to the drain of the 5 th  NMOS tube respectively, and the connecting terminal is the 2 nd  input terminal of the said sensitivity amplifier; grid of the 1 st  PMOS tube and the 4 th  NMOS tube is connected to the grid of the 5 th  NMOS tube, and the connecting terminal is the SADIS terminal of the said sensitivity amplifier; SADIS terminal of the said sensitivity amplifier is used to receive discharging signals from sensitivity amplifier; grid of the 4 th  PMOS tube is connected to the grid of the 5 th  PMOS tube, and the connecting terminal is SAPRE terminal of the said sensitivity amplifier; SAPRE terminal of the said sensitivity amplifier is used to receive charging signals from the sensitivity amplifier; grid of the 6 th  PMOS tube is connected to the grid of the 7 th  PMOS tube, and the connecting terminal is SASEL terminal of the said sensitivity amplifier; SASEL terminal of the said sensitivity amplifier is used to receive reading signals from the sensitivity amplifier; grid of the 3 rd  NMOS tube serves as SAE terminal of the said sensitivity amplifier; SAE terminal of the said sensitivity amplifier is used to receive enabling signals from the sensitivity amplifier; source of the 1 st  NMOS tube and the 2 nd  NMOS tube is connected to the drain of the 3 rd  NMOS tube respectively; source of the 3 rd  NMOS tube, the 4 th  NMOS tube and the 5 th  NMOS tube is grounded respectively; source of the 6 th  PMOS tube serves as the 1 st  signal input terminal of the said sensitivity amplifier; source of the 7 th  PMOS tube serves as the 2 nd  signal input terminal of the said sensitivity amplifier; the 1 st  signal input terminal of the said sensitivity amplifier serves as BL terminal of the output circuit of the said static RAM; the 2 nd  signal input terminal of the said sensitivity amplifier serves as BLB terminal of the output circuit of the said static RAM; BL terminal and BLB terminal of the output circuit of the said static RAM are used to connect the data selector to receive bit-line pairs. 
         [0006]    The said data latch circuit comprises two NOR gates, the 8 th  PMOS tube, the 9th PMOS tube, the 10 th  PMOS tube, the 11 th  PMOS tube, the 6 th  NMOS tube, the 7 th  NMOS tube, the 8 th  NMOS tube, the 9 th  NMOS tube and the 10 th  NMOS tube; the said NOR gate is provided with the 1 st  input terminal, the 2 nd  input terminal and the output terminal; the said two NOR gates comprise the 1 st  NOR gate and the 2 nd  NOR gate; source of the 9 th  PMOS tube and grid of the 6 th  NMOS tube are connected to the power supply; the 1 st  input terminal of the 1 st  NOR gate serves as the 1 st  input terminal of the said data latch circuit; the 1 st  input terminal of the said data latch circuit is connected to the 1 st  output terminal of the said sensitivity amplifier; the 2 nd  input terminal of the 1 st  NOR gate, output terminal of the 2 nd  NOR gate and grid of the 10 th  PMOS tube are connected to the grid of the 10 th  NMOS tube; output terminal of the 1 st  NOR gate, the 1 st  input terminal of the 2 nd  NOR gate, source of the 6 th  NMOS tube, source of the 11 th  PMOS tube and grid of the 8 th  PMOS tube are connected to the grid of the 9 th  NMOS tube; the 2 nd  input terminal of the 2 nd  NOR gate serves as the 2 nd  input terminal of the said data latch circuit; the 2 nd  input terminal of the said data latch circuit is connected to the 2 nd  input terminal of the said sensitivity amplifier; drain of the 9 th  PMOS tube is connected to the source of the 8 th  PMOS tube; grid of the 9 th  PMOS tube is connected to the grid of the 7 th  NMOS tube, and the connecting terminal is OUTDIS terminal of the said data latch circuit; OUTDIS terminal of the said data latch circuit is used to receive discharging control signals from the output terminal; source of the 10 th  PMOS tube, drain of the 10 th  PMOS tube, drain of the 10 th  NMOS tube, source of the 10 th  NMOS tube, source of the 8 th  NMOS tube, source of the 9 th  NMOS tube, source of the 7th NMOS tube and grid of the 11 th  PMOS tube are grounded; drain of the 6 th  NMOS tube and drain of the 11 th  PMOS tube are connected to the grid of the 8 th  NMOS tube; drain of the 8 th  PMOS tube, drain of the 8 th  NMOS tube and drain of the 9 th  NMOS tube are connected to the drain of the 7 th  NMOS tube, and the connecting terminal is the output terminal of the said data latch circuit; output terminal of the said data latch circuit serves as the output terminal of the output circuit of the said static RAM. 
         [0007]    The said input circuit comprises the 11 th  NMOS tube, the 12 th  NMOS tube, the 13 th  NMOS tube, the 14 th  NMOS tube, the 15 th  NMOS tube, the 16 th  NMOS tube, the 17 th  NMOS tube, the 18 th  NMOS tube, the 19 NMOS tube, the 20 th  NMOS tube, the 21 st  NMOS tube, the 12 th  PMOS tube, the 13 th  PMOS tube, the 14 th  PMOS tube, the 15 th  PMOS tube, the 16 th  PMOS tube, the 17 th  PMOS tube, the 18 th  PMOS tube, the 19 th  PMOS tube, the 20 th  PMOS tube, the 21 st  PMOS tube, the 22 nd  PMOS tube, the 23 rd  PMOS tube and the 24 th  PMOS tube; source of the 12 th  PMOS tube, the 14 th  PMOS tube, the 16 th  PMOS tube, the 17 th  PMOD tube, the 18 th  PMOS tube, the 20 th  PMOS tube, the 22 nd  PMOS tube, the 23 rd  PMOS tube and the 24 th  PMOS tube is connected to the power supply respectively; drain of the 12 th  PMOS tube is connected to the source of the 13 th  PMOS tube; drain of the 13 th  PMOS tube, the 11 th  NMOS tube, the 15 th  PMOS tube and the 13 th  NMOS tube and grid of the 16 th  PMOS tube are connected to the grid of the 15 th  NMOS tube; source of the 11 th  NMOS tube is connected to the drain of the 12 th  NMOS tube; source of the 12 th  NMOS tube, the 14 th  NMOS tube, the 15 th  NMOS tube, the 16 th  NMOS tube, the 17 th  NMOS tube, the 19 th  NMOS tube and the 21 st  NMOS tube is grounded respectively; drain of the 14 th  PMOS tube is connected to the source of the 15 th  PMOS tube; source of the 13 th  NMOS tube is connected to the drain of the 14 th  NMOS tube; grid of the 14 th  PMOS and the 14 th  NMOS tube, drain of the 15 th  NMOS tube and the 16 th  PMOS tube and grid of the 17 th  PMOS tube, 16 th  NMOS tube and 19 th  NMOS tube are connected to the grid of the 20 th  PMOS tube; drain of the 17 th  PMOS tube and the 16 th  NMOS tube and grid of the 17 th  NMOS tube are connected to the grid of the 18 th  PMOS tube; drain of the 17 th  NMOS tube and the 18 th  PMOS tube and source of the 18 th  NMOS tube are connected to the source of the 19 th  PMOS tube; drain of the 18 th  NMOS tube and the 19 th  PMOS tube is connected to the drain of the 22 nd  PMOS tube, and the connecting terminal is the 1 st  output terminal of the said input circuit; drain of the 19 th  NMOS tube and the 20 th  PMOS tube and source of the 20th NMOS tube are connected to the source of the 21 st  PMOS tube; drain of the 20 th  NMOS tube and the 21 st  PMOS tube is connected to the drain of the 23 rd  PMOS tube, and the connecting terminal is the 2 nd  output terminal of the said input circuit; grid of the 12 th  PMOS tube, the 18 th  NMOS tube, the 20 th  NMOS tube, the 13 th  NMOS tube and the 21 st  NMOS tube is connected to the grid of the 24 th  PMOS tube, and the connecting terminal is the clock signal input terminal of the said input circuit, used to receive write-in signals output from the said clock circuit; grid of the 12 th  NMOS tube and the 15 th  PMOS tube, drain of the 24 th  PMOS tube and the 21 st  NMOS tube and grid of the 19 th  PMOS tube are connected to the grid of the 21 st  PMOS tube, and the connecting terminal is the inverted clock signal input terminal of the said input circuit, used to receive inverted signals among write-in signals output from the said clock module; grid of the 13 th  PMOS tube is connected to the grid of the 11 th  NMOS tube, and the connecting terminal is the signal input terminal of the said input circuit, used to receive external data; grid of the 22 nd  PMOS tube is connected to the grid of the 23 rd  PMOS tube, and the connecting terminal is the charging signal input terminal of the said input circuit, used to receive charging signals output from the said clock circuit. The circuit aims to make use of the 14 th  PMOS tube, the 15 th  PMOS tube, the 12 th  NMOS tube and the 14 th  NMOS tube to guard against the impact of leakage current, maintain the voltage to the grid of the 15 th  NMOS tube and the 16 th  PMOS tube, improve data input precision, and reduce the leakage current based on functions of the input circuit as realized. 
         [0008]    As compared with prior art, the present invention has the following advantages: It can ensure basically identical power consumption in each working cycle in case of data reading, which is provided with higher capability in Differential Power Analysis Resistance; as compared with existing static RAMs, it can improve power consumption equilibrium by 53% for effective defense of differential energy attack. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0009]      FIG. 1  is the structural block diagram for the present invention; 
           [0010]      FIG. 2  is the structural block diagram for the memory array of the present invention; 
           [0011]      FIG. 3  is the circuit diagram for the output circuit of the present invention; 
           [0012]      FIG. 4  is the timing diagram for the output circuit of the present invention; 
           [0013]      FIG. 5  is the energy consumption distribution diagram for the output circuit of the present invention; 
           [0014]      FIG. 6  is the energy consumption distribution diagram for existing output circuit; 
           [0015]      FIG. 7  is the diagram showing superposition of supply current produced by reading of 100 groups of data by the present invention; 
           [0016]      FIG. 8  is the diagram showing superposition of supply voltage produced by reading of 100 groups of data by existing static RAM; 
           [0017]      FIG. 9  is the input circuit of the static RAM in Embodiment 2. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0018]    The present invention is further described as follows in combination with drawings and embodiments: 
         [0019]    Embodiment A: shown in  FIGS. 1, 2 and 3 , a static RAM for Differential Power Analysis Resistance  1000 , comprising a replica bit-line circuit  1100 , a decoder  1200 , an address data latch circuit  1300 , a clock circuit  1400 , n-bit memory arrays  1510 - 1 - 1510 - n , n-bit data selectors  1520 - 1 - 1520 - n , n-bit input circuits  1530 - 1 - 1530 - n  and n-bit output circuits  1540 - 1  thru  1540 - n , where n is an integral equal to or over 1. The said decoder  1200  is connected to the said replica bit-line circuit  1100 , the said address data latch circuit  1300 , the said n-bit memory arrays  1510 - 1 - 1510 - n  and the said n-bit data selectors  1520 - 1 - 1520 - n , respectively. The said clock circuit  1400  is connected to the said replica bit-line circuit  1100 , the said n-bit input circuits  1530 - 1 - 1530 - n , the said n-bit output circuits  1540 - 1 - 1540 - n , respectively. The said input circuit j is connected to the said data selector j; the said replica bit-line circuit is connected to the said n-bit output circuits  1540 - 1 - 1540 - n . The said data selector j is connected to the said memory array j and the said output circuit j, respectively, where j=1, 2, . . . , n. With reference to  FIG. 2 , array of memory units  1500 - 1 - 1500 - n  are illustrated. 
         [0020]    With reference to  FIG. 3 , the said output circuit  1540  comprises a sensitivity amplifier  1541  and a data latch circuit  1542 . The said sensitivity amplifier  1541  comprises a 1 st  PMOS tube P 1 , a 2 nd  PMOS tube P 2 , a 3 rd  PMOS tube P 3 , a 4 th  PMOS tube P 4 , a 5 th  PMOS tube P 5 , a 6 th  PMOS tube P 6 , a 7 th  PMOS tube P 7  and a 1 st  NMOS tube N 1 , a 2 nd  NMOS tube N 2 , a 3 rd  NMOS tube N 3 , a 4 th  NMOS tube N 4  a 5 th  NMOS tube N 5 . In detail, a source of the 1 st  PMOS tube P 1 , a source of the 4 th  PMOS tube P 4  and a source of the 5 th  PMOS tube P 5  are connected to the power supply VDD, respectively. A drain of the 1 st  PMOS tube P 1  and a source of the 2 nd  PMOS tube P 2  are connected to the source of the 3 rd  PMOS tube P 3 . A drain of the 2 nd  PMOS tube P 2 , a grid of the 3 rd  PMOS tube P 3 , a drain of the 4 th  PMOS tube P 4 , a drain of the 6 th  PMOS tube P 6 , a drain of the 1 st  NMOS tube N 1  and a grid of the 2 nd  NMOS tube N 2  are connected to a drain of the 4 th  NMOS tube N 4 , respectively, and a common connection thereof is the 1 st  output terminal SAOUT of the said sensitivity amplifier  1541 . A grid of the 2 nd  PMOS tube P 2 , a drain of the 3 rd  PMOS tube P 3 , a drain of the 5 th  PMOS tube P 5 , a drain of the 7 th  PMOS tube P 7 , a grid of the 1 st  NMOS tube N 1  and a drain of the 2 nd  NMOS tube N 2  are connected to a drain of the 5 th  NMOS tube N 5  respectively, and a common connection thereof is the 2 nd  input terminal SAOUTB of the said sensitivity amplifier  1541 . A grid of the 1 st  PMOS tube P 1  and a grid of the 4 th  NMOS tube N 4  are connected to a grid of the 5 th  NMOS tube N 5 , and a common connection thereof is a SADIS terminal of the said sensitivity amplifier  1541 . The SADIS terminal of the said sensitivity amplifier  1541  is used to receive discharging signals from sensitivity amplifier  1541 . A grid of the 4 th  PMOS tube P 4  is connected to a grid of the 5 th  PMOS tube, and a common connection thereof is a SAPRE terminal of the said sensitivity amplifier  1541 , and the SAPRE terminal of the said sensitivity amplifier  1541  is used to receive charging signals from the sensitivity amplifier  1541 . A grid of the 6 th  PMOS tube P 6  is connected to a grid of the 7 th  PMOS tube P 7 , and a common connection thereof is a SASEL terminal of the said sensitivity amplifier  1541 . The SASEL terminal of the said sensitivity amplifier  1541  is used to receive reading signals from the sensitivity amplifier  1541 . A grid of the 3 rd  NMOS tube N 3  serves as a SAE terminal of the said sensitivity amplifier  1541 . The SAE terminal of the said sensitivity amplifier  1541  is used to receive enabling signals from the sensitivity amplifier  1541 . A source of the 1 st  NMOS tube N 1  and a source of the 2 nd  NMOS tube N 2  are connected to a drain of the 3 rd  NMOS tube N 3  respectively. A source of the 3 rd  NMOS tube N 3 , a source of the 4 th  NMOS tube N 4  and a source of the 5 th  NMOS tube N 5  are grounded VSS, respectively. A source of the 6 th  PMOS tube P 6  serves as a 1 st  signal input terminal of the said sensitivity amplifier  1541 . A source of the 7 th  PMOS tube P 7  serves as a 2 nd  signal input terminal of the said sensitivity amplifier  1541 . The 1 st  signal input terminal of the said sensitivity amplifier  1541  serves as BL terminal of the output circuit of the said static RAM. The 2 nd  signal input terminal of the said sensitivity amplifier  1541  serves as BLB terminal of the output circuit of the said static RAM. The BL terminal and the BLB terminal of the output circuit of the said static RAM are used to connect the data selector to receive bit-line pairs. 
         [0021]    The said data latch circuit  1542  comprises two NOR gates G 1 , G 2 , a 8 th  PMOS tube P 8 , a 9 th  PMOS tube P 9 , a 10 th  PMOS tube P 10 , a 11 th  PMOS tube P 11 , a 6 th  NMOS tube N 6 , a 7 th  NMOS tube N 7 , a 8 th  NMOS tube N 8 , a 9 th  NMOS tube N 9  and a 10 th  NMOS tube N 10 . In detail, each of the said NOR gates is provided with the 1 st  input terminal, the 2 nd  input terminal and the output terminal. The said two NOR gates comprise the 1 st  NOR gate G 1  and the 2 nd  NOR gate G 2 . A source of the 9 th  PMOS tube P 9  and a grid of the 6 th  NMOS tube N 6  are connected to the power supply. A 1 st  input terminal of the 1 st  NOR gate G 1  serves as a 1 st  input terminal of the said data latch circuit. The 1 st  input terminal of the said data latch circuit  1542  is connected to the 1 st  output terminal of the said sensitivity amplifier  1541 . A 2 nd  input terminal of the 1 st  NOR gate G 1 , an output terminal of the 2 nd  NOR gate G 2  and a grid of the 10 th  PMOS tube P 10  are connected to a grid of the 10 th  NMOS tube N 10 , and a common connection thereof is marked as node  2 . An output terminal of the 1 st  NOR gate G 1 , a 1 st  input terminal of the 2 nd  NOR gate G 2 , a source of the 6 th  NMOS tube N 6 , a source of the 11 th  PMOS tube P 11  and a grid of the 8 th  PMOS tube P 8  are connected to a grid of the 9 th  NMOS tube N 9 , and a common connection thereof is marked as node  1 . A 2 nd  input terminal of the 2 nd  NOR gate serves as a 2 nd  input terminal of the said data latch circuit  1542 . The 2 nd  input terminal of the said data latch circuit  1542  is connected to the 2 nd  input terminal of the said sensitivity amplifier  1541 . The drain of the 9 th  PMOS tube P 9  is connected to the source of the 8 th  PMOS tube P 8 . The grid of the 9 th  PMOS tube P 9  is connected to the grid of the 7 th  NMOS tube N 7 , and a common connection thereof is OUTDIS terminal of the said data latch circuit  1542 . The OUTDIS terminal of the said data latch circuit  1542  is used to receive discharging control signals from the output terminal Q of the data latch circuit  1542 . A source of the 10 th  PMOS tube P 10 , a drain of the 10 th  PMOS tube P 10 , a drain of the 10 th  NMOS tube N 10 , the source of the 10 th  NMOS tube N 10 , a source of the 8 th  NMOS tube N 8 , a source of the 9 th  NMOS tube N 9 , a source of the 7 th  NMOS tube N 7  and a grid of the 11 th  PMOS tube P 11  are grounded. A drain of the 6 th  NMOS tube N 6  and a drain of the 11 th  PMOS tube P 11  are connected to a grid of the 8 th  NMOS tube N 8 . A drain of the 8 th  PMOS tube P 8 , a drain of the 8 th  NMOS tube N 8  and a drain of the 9 th  NMOS tube N 9  are connected to a drain of the 7 th  NMOS tube N 7 , and a common connection thereof is the output terminal of the said data latch circuit  1542 . The output terminal of the said data latch circuit  1542  serves as the output terminal Q of the output circuit of the said static RAM. 
         [0022]    As shown in  FIG. 9 , the said input circuit comprises a 11 th  NMOS tube N 11 , a 12 th  NMOS tube N 12 , a 13 th  NMOS tube N 13 , a 14 th  NMOS tube N 14 , a 15 th  NMOS tube N 15 , a 16 th  NMOS tube N 16 , a 17 th  NMOS tube N 17 , a 18 th  NMOS tube N 18 , a 19 th  NMOS tube N 19 , a 20 th  NMOS tube N 20 , a 21 st  NMOS tube N 21 , a 12 th  PMOS tube P 12 , a 13 th  PMOS tube P 13 , a 14 th  PMOS tube P 14 , a 15 th  PMOS tube P 15 , a 16 th  PMOS tube P 16 , a 17 th  PMOS tube P 17 , a 18 th  PMOS tube P 18 , a 19 th  PMOS tube P 19 , a 20 th  PMOS tube P 20 , a 21 st  PMOS tube P 21 , a 22 nd  PMOS tube P 22 , a 23 rd  PMOS tube P 23  and a 24 th  PMOS tube P 24 . 
         [0023]    In detail, a source of the 12 th  PMOS tube P 12 , the 14 th  PMOS tube P 14 , the 16 th  PMOS tube P 16 , the 17 th  PMOD tube P 17 , the 18 th  PMOS tube P 18 , the 20 th  PMOS tube P 20 , the 22 nd  PMOS tube P 22 , the 23 rd  PMOS tube P 23  and the 24 th  PMOS tube P 24  is connected to the power supply respectively. A drain of the 12 th  PMOS tube P 12  is connected to a source of the 13 th  PMOS tube P 13 . A drain of the 13 th  PMOS tube P 13 , a drain of the 11 th  NMOS tube N 11 , a drain of the 15 th  PMOS tube P 15 , a drain of the 13 th  NMOS tube N 13  and a grid of the 16 th  PMOS tube P 16  are connected to a grid of the 15 th  NMOS tube N 15 . A source of the 11 th  NMOS tube N 11  is connected to a drain of the 12 th  NMOS tube N 12 . A source of the 12 th  NMOS tube N 12 , a source of the 14 th  NMOS tube N 14 , a source of the 15 th  NMOS tube N 15 , a source of the 19 th  NMOS tube N 19  and a source of the 21 st  NMOS tube N 21  are grounded respectively. A drain of the 14 th  PMOS tube P 14  is connected to the source of the 15 th  PMOS tube P 15 . A source of the 13 th  NMOS tube N 13  is connected to a drain of the 14 th  NMOS tube N 14 . A grid of the 14 th  PMOS tube P 14  and a grid of the 14 th  NMOS tube N 14 , a drain of the 15 th  NMOS tube N 15 , a drain of the 16 th  PMOS tube P 16 , a grid of the 17 th  PMOS tube P 17 , a grid of the 16 th  NMOS tube N 16  and a grid of the 19 th  NMOS tube N 19  are connected to a grid of the 20 th  PMOS tube P 20 . A drain of the 17 th  PMOS tube P 17 , a drain of the 16 th  NMOS tube N 16  and a grid of the 17 th  NMOS tube N 17  are connected to a grid of the 18 th  PMOS tube P 18 . A drain of the 17 th  NMOS tube N 17 , a drain of the 18 th  PMOS tube P 18  and a source of the 18 th  NMOS tube N 18  are connected to a source of the 19 th  PMOS tube P 19 . A drain of the 18 th  NMOS tube N 18  and a drain of the 19 th  PMOS tube P 19  are connected to the drain of the 22 nd  PMOS tube P 22 , and a common connection thereof is the 1 st  output terminal of the said input circuit. A drain of the 19 th  NMOS tube N 19 , a drain of the 20 th  PMOS tube P 20  and a source of the 20 th  NMOS tube N 20  are connected to a source of the 21 st  PMOS tube P 21 . A drain of the 20 th  NMOS tube N 20  and a drain of the 21 st  PMOS tube P 21  are connected to the drain of the 23 rd  PMOS tube P 23 , and a common connection thereof is the 2 nd  output terminal of the said input circuit. A grid of the 12 th  PMOS tube P 12 , a grid of the 18 th  NMOS tube N 18 , a grid of the 20 th  NMOS tube N 20 , a grid of the 13 th  NMOS tube N 13  and a grid of the 21 th  NMOS tube N 21  are connected to a grid of the 24 th  PMOS tube P 24 , and a common connection thereof is a clock signal input terminal WCLK of the said input circuit, used to receive write-in signals output from the said clock circuit. A grid of the 12 th  NMOS tube N 12 , a grid of the 15 th  PMOS tube P 15 , a drain of the 24 th  PMOS tube P 24 , a drain of the 21 st  NMOS tube N 21  and a grid of the 19 th  PMOS tube P 19  are connected to a grid of the 21 st  PMOS tube P 21 , and a common connection thereof is the inverted clock signal input terminal WCLKB of the said input circuit, used to receive inverted signals among write-in signals output from the said clock module. A grid of the 13 th  PMOS tube P 13  is connected to a grid of the 11 th  NMOS tube N 11 , and a common connection thereof is the signal input terminal In of the said input circuit, used to receive external data. A grid of the 22 nd  PMOS tube P 22  is connected to a grid of the 23 rd  PMOS tube P 23 , and a common connection thereof is the charging signal input terminal PC of the said input circuit, used to receive charging signals output from the said clock circuit. 
         [0024]    In this embodiment, the replica bit-line circuit  1100 , the decoder  1200 , the address latch circuit  1300 , the clock circuit  1400 , the memory array  1510 - 1 - 1510 - n , the data selector  1520 - 1 - 1520 - n  and the input circuit  1540 - 1 - 1540 - n  are well-established products in the technical field. The SADIS, SAPRE, SASEL and SAE terminals of the sensitivity amplifier  1541  as well as OUTDIS terminal of the data latch circuit  1542  are connected to the clock circuit respectively. The terminal BL and BLB of the output circuit of the static RAM are connected to the data selector. Timing diagram for the output circuit of the static RAM of the present invention is as shown in  FIG. 4 . According to read data outputted from the output circuit in previous and current stages, four working states S 00 , S 01 , S 10 , S 11  can be categorized, the working states S 00  represents that logic 0 is read for the previous stage and logic 0 for the current stage; the working states S 01  represents that logic 0 is read for the previous stage and logic 1 for the current stage; the working states S 10  represents that logic 1 is read for the previous stage and logic 0 for the current stage; and the working states S 11  represents that logic 1 is read for the previous stage and logic 1 for the current stage. As shown in  FIG. 4 , output terminal Q may subject to one-time charging before the evaluation stage. It is to be maintained or discharged according to the reading data at the evaluation stage. The node  1  and node  2  may charge and discharge one of nodes in each cycle. The 1 st  output terminal SAOUT and the 2 nd  output terminal SAOUTB of the sensitivity amplifier  1541  may experience one-time charging and discharging in each cycle to ensure balanced power consumption. 
         [0025]    Energy consumption distribution diagram for the output circuit of the static RAM of the present invention is as shown in  FIG. 5 . The energy consumption distribution diagram for output circuit of existing static RAM is as shown in  FIG. 6 . According to the analysis of  FIG. 6 , the output circuit of the present invention has eliminated the difference between switching and short-circuit power consumption, which ensuring basically identical power consumption at each working state in each cycle. According to analysis of  FIG. 6 , output circuit of existing static RAM may produce obvious discrepancy to the power consumption at different working states. The output circuit of existing static RAM is requested to alter the data as stored in the data latch circuit  1542  to produce corresponding switching and short-circuit power consumption at working state S 01  and S 10 . As a result of it, power consumption at working state S 01  and S 10  is obviously higher than that at working state S 11  and S 00 .  FIG. 7  is the diagram showing superposition of supply current produced by the static RAM for Differential Power Analysis Resistance when reading 100 groups of data.  FIG. 8  is the diagram showing superposition of supply current produced by existing static RAM when reading 100 groups of data. According to analysis of  FIGS. 7 and 8 , existing static RAM has obvious current discrepancy at the evaluation stage, for example a circled area  810  shown in  FIG. 8 . On the contrary, the present invention has overcome defects associated with power consumption and data reading, which can ensure consistent power consumption and current in each reading cycle. As compared with prior art, the present invention has effectively improved the power equilibrium by 53%, which can effectively minimize differential power analysis attack.