Abstract:
A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority from U.S. provisional application No. 61/298,555 filed on Jan. 27, 2010 by the present inventor. 
     
    
     BACKGROUND 1. Technical Field 
       [0002]    The present invention relates to voltage level switching and, more particularly to a voltage level shifter circuit and a method for the operation of the voltage level shifter circuit. 
         [0003]    2. Description of Related Art 
         [0004]    Reference is now made to  FIG. 1  which shows a current mirror circuit  10  according to conventional art. The base of a transistor Q 1  is connected to the base of a transistor Q 2 , along with both of the emitters of Q 1  and Q 2  typically connected to ground or another common voltage point. A link connects the collector of Q 1  to the bases of Q 1  and Q 2 . The collector of Q 1  also connects to voltage supply (V cc ) via a resistor R. The voltage output (V out ) of current mirror circuit  10  is between the collector of Q 2  and ground or between the collector of Q 2  and another voltage point. 
         [0005]    Bipolar transistors such as Q 1  or Q 2  have a current gain (β) which is the ratio of the collector current to the base current. The relationship between I REF  and I OUT  is given by equation Eq. 1 below: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     
                       ( 
                       
                         β 
                         
                           β 
                           + 
                           2 
                         
                       
                       ) 
                     
                      
                     
                       I 
                       REF 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0006]    Where the current gain (β) is high I REF  equals I OUT  and I REF  is said to ‘mirror’ I OUT . The current being ‘mirrored’ can be, and sometimes is, a varying signal current. The current mirror is typically used to provide bias currents and active loads to circuits. Current mirrors may typically be constructed using various types of semiconductor switches such as a metal oxide semiconductor field effect transistor (MOSFET), field effect transistor (FET), insulated gate field effect transistor (IGFET), bipolar junction transistor (BJT) or Schottky transistor. 
         [0007]    Reference is now made to  FIG. 2  which shows a level shifter circuit  20  according to conventional art. Level shifter circuit  20  includes inverting amplifier A, resistors R 1  and R 2  (or equivalent loads), switches TCM 1 , TCM 2 , T 1  and T 2  which are preferably insulated gate field effect transistors (IGFETs). A current mirror circuit in level shifter circuit  20  is shown with the gate of IGFET TCM 1  is connected to the gate (G) of a IGFET TCM 2 , along with both of the sources (S) of TCM 1  and TCM 2  typically connected to ground. A link connects the drain (D) of TCM 1  to the gates (G) of TCM 1  and TCM 2 . The drain (D) of TCM 1  also connects to voltage supply (V cc ) via a resistor (not shown) to form current source I. 
         [0008]    The drain of TCM 2  connect to the sources (S) of IGFETS T 1  and T 2 . The drain (D) of T 1  connects to voltage supply (V cc ) through resistor R 1 . The drain (D) of T 2  connects to voltage supply (V cc ) through resistor R 2 . The floating output voltage (Vf) of circuit  20  may be between voltage supply (V cc ) and node X or may be between voltage supply (V cc ) and node Y. Voltage input terminal (Control) is connected to the gate (C) of IGFET T 2  and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T 1  via inverting amplifier A. 
         [0009]    In operation, shifter circuit  20  current I flows through resistors R 1  or R 2  which are referenced to floating output voltage (Vf) by virtue of current I flowing through resistors R 1  or R 2 . The switching time for IGFETs T 1  and T 2  is typically a function of the miller drain capacitors of T 1  and T 2  plus all parasitic capacitances of T 1  and T 2  that are charged by the current I to a voltage swing value of the voltage input terminal (Control). IGFET T 1  and resistor R 1  are connected in circuit  20  as a common source (S) amplifier with output on node X common to the input from voltage input terminal Control. Similarly, IGFET T 2  and resistor R 2  are connected in circuit  20  as a common source (S) amplifier with output on node Y common to the inverse of input voltage input terminal Control. The bandwidth of the common-source amplifier typically tends to be low, due to high capacitance resulting from the Miller effect. The Miller effect accounts for the increase in the equivalent input capacitance of a common source (S) amplifier due to amplification of the capacitance between the input and output terminals. The additional input charge (Q CM ) due to the Miller effect for both IGFETs T 1  or T 2  is given by equation Eq. 2 below: 
         [0000]    
       
         
           
             
               
                 
                   
                     Q 
                     CM 
                   
                   = 
                   
                     
                       
                          
                         V 
                       
                       
                          
                         t 
                       
                     
                      
                     
                       ( 
                       
                         
                           C 
                           GD 
                         
                         + 
                         
                           C 
                           DS 
                         
                         + 
                         
                           C 
                           p 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                    
                   2 
                 
               
             
           
         
       
     
         [0010]    C P =Parasitic capacitance of the drain (D) of T 1  or T 2   
         [0011]    C GD =The capacitance between gate (C) and drain (D) of T 1  or T 2   
         [0012]    C DS =The capacitance between drain (D) and source (S) of T 1  or T 2   
         [0013]    V=Voltage at node X for T 1  or voltage at node Y for T 2   
         [0014]    Where even a small parasitic capacitance C GD  between gate (G) and drain (D) may become a large influence in the frequency response and hence bandwidth of the common source amplifier. A low bandwidth due to the effect of Miller capacitance typically reduces switching speed of the common source amplifier. Additionally, with a level shifter like shifter circuit  20 , the switching times of IGFETs T 1  and T 2  are typically proportional to current consumption in resistors R 1  and R 2  because current in resistors R 1  and R 2  charges the Miller capacitance (C M =C P +C GD +C DS ). 
         [0015]    The terms “field-effect transistor (FET) switch” is used herein interchangeably and equivalently with the term “bipolar junction transistor (BJT) switch”. Whereby the gate of the FET switch is equivalent to the base of the BJT switch, the drain of the FET switch is equivalent to the collector of the BJT switch and the source of the FET switch is equivalent to the emitter of the BJT switch. 
         [0016]    The term “leg of a switch” as used herein, refers to the actuation of a gate (of an FET) by application of a voltage to the gate for example, which causes a reduction in impedance between a drain and a source (of the FET). The reduction in impedance between the drain and the source (of the FET) is considered equivalent to the connection together of two contacts of a mechanical switch (e.g. single pole double throw switch (SPDT)). 
         [0017]    The terms “charging” and “discharging” in the context of the present invention in reference to charging and discharging a capacitor, are used herein interchangeably except that current flow while charging and discharging is usually in the opposite direction. 
         [0018]    The term “switch” as used herein refers to any of: silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), insulated gate field effect transistor (IGFET), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, mechanically operated single pole double pole switch (SPDT), SPDT electrical relay, SPDT reed relay, SPDT solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), and triode for alternating current (TRIAC). 
         [0019]    An ideal switch takes no time to go from off to on or from on to off. The switching time of the ideal switch is therefore zero. The term “switching time” as used herein refers to a finite period of time it takes for a switch to go from being in an “off” state to an “on” state or from the “on” state to the “off” state. 
         [0020]    The terms “on” and “off” as used herein, when applied to a switch, refer to an increased current value flowing through the switch when the switch is “on” compared to the relative decreased current value flowing through the switch when the switch is “off”. 
         [0021]    The term “minimal current” as used herein refers to the relative decreased current value flowing through a switch when the switch is off when compared to an increased current value flowing through the switch when the switch is on. 
       BRIEF SUMMARY 
       [0022]    According to embodiments of the present invention there is provided a voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. The input voltage typically produces an output voltage on the output terminal based on the current. A charge storage circuit may be operatively attached to the input terminal and an input of the current mirror circuit. The charge storage circuit may include a capacitor or a battery. 
         [0023]    The charge storage circuit has an inverting amplifier with an input connected to the input terminal. A capacitor connected between an output of the inverting amplifier and an anode of a diode. A cathode of the diode is connected to the input of the current mirror circuit. A second diode with a second cathode connected to the anode of the diode and a second anode connected to the electrical earth. A second inverting amplifier with a second input connected to the output of the inverting amplifier. A second capacitor connected between a second output of the second inverting amplifier and a third anode of a third diode. A third cathode of the third diode is connected to the input of the current mirror circuit. A fourth diode with a fourth cathode connected to the third anode of the third diode and a third anode connected to the electrical earth. 
         [0024]    According to embodiments of the present invention there is provided a voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a switch driven by an input voltage applied to the input terminal to produce an output voltage on the output terminal based on a current drawn through the switch. The switch may be a silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, electrical relay, reed relay, solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), or triode for alternating current TRIAC. A current changing mechanism operatively connected to the switch. The current changing mechanism is preferably adapted for changing the current through the switch. The current changing mechanism is typically adapted to change the current when the switch is switched. The current changing mechanism is preferably adapted to provide a current control signal to a leg of the switch. 
         [0025]    The level shifting circuit optionally includes further, a current mirror circuit having an output connected between the switch and an electrical earth. A charge storage circuit operatively attached to the input terminal and an input of the current mirror circuit and a second charge storage circuit operatively attached to the output terminal. The second charge storage circuit may include either a capacitor or a battery. 
         [0026]    According to embodiments of the present invention there is provided a method to operate a voltage level shifting circuit. The level shifting circuit typically includes a switch which has an input terminal and an output terminal and a current mirror circuit having a current-mirror circuit output. The switch is connected in series with the current-mirror circuit output and an electrical earth, wherein a charge storage circuit is attached to the input terminal and an input of the current mirror circuit. 
         [0027]    The method applies a voltage on the input terminal thereby driving a current through the switch and the current-mirror circuit output. The current is preferably a minimal value prior to the applying of the voltage. The charge storage circuit is typically charged prior to the applying of the voltage. The driving typically provides a voltage on the output terminal. The current is preferably increased by a discharge of the charge storage circuit into the input of the current mirror circuit. The current is preferably increased by switching the switch on. The current may also be increased at a time just prior to the switching the switch on. The current is preferably decreased by switching the switch off. The current may be further decreased by a charge of said charge storage circuit from said input of said current mirror circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein: 
           [0029]      FIG. 1  shows a current mirror circuit according to conventional art. 
           [0030]      FIG. 2  shows a level shifter circuit according to conventional art. 
           [0031]      FIG. 3 a    shows a general circuit diagram of a level shifter circuit, according to an embodiment of the present invention. 
           [0032]      FIG. 3 b    shows a level shifter circuit, according to an embodiment of the present invention. 
           [0033]      FIG. 4  shows a method to operate the level shifter circuit shown in  FIG. 3 b   , according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0034]    Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures. 
         [0035]    Before explaining embodiments of the invention in detail, it is to be understood that the invention is not limited in its application to the details of design and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. 
         [0036]    By way of introduction, an embodiment of the present invention is directed to allow high current consumption only in the switching time. After the switching time, current is typically reduced to maintain low current consumption and allow for current overflow (by use of diodes) to the output floating voltage of the shifter circuit. 
         [0037]    Reference is now made to  FIG. 3 a    which shows a general circuit diagram of a level shifter circuit  30   a,  according to an embodiment of the present invention. The drain (D) of T 1  connects to voltage supply (V cc ) through resistor R 1 . The drain (D) of T 2  connects to voltage supply (V cc ) through resistor R 2 . Capacitor CH 1  is connected in parallel with resistor R 1 . Capacitor CH 2  is connected in parallel with resistor R 2 . The anode of diode D 6  is connected to the anode of diode D 5 . The connected anodes of D 5  and D 6  may provide one output terminal of floating output voltage Vf. The other terminal of floating output voltage Vf is connected to voltage power supply V. The cathode of diode D 6  is connected to node X and the cathode of diode D 5  is connected to node Y. Voltage input terminal (Control) is connected to the gate (G) of IGFET T 1  and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T 2  via inverting amplifier A 1 . The sources (S) of IGFET T 1  and T 2  are connected together and connect to one end of current controlled source  36 . The other end of source  36  is connected to electrical earth. Flow of current through source  36  is controlled by current control line  38 . 
         [0038]    Reference is now made to  FIG. 3 b    which shows a level shifter circuit  30   b,  according to an embodiment of the present invention. Level shifter  30   b  is a more detailed embodiment of level circuit  30   a  shown in  FIG. 3 a   . Shifter circuit  30   b  additionally includes inverting amplifiers A 1 , A 2  and A 3 , capacitors CH 1  and CH 2  and diodes D 1 , D 2 , D 3 , D 4 , D 5  and D 6 . Switches TCM 1 , TCM 2 , T 1  and T 2  which are preferably insulated gate field effect transistors (IGFETs). A current mirror circuit in level shifter circuit  30   b  is shown with the gate of IGFET TCM 1  is connected to the gate (G) of a IGFET TCM 2 , along with both of the sources (S) of TCM 1  and TCM 2  typically connected to ground. A link connects the drain (D) of TCM 1  to the gates (G) of TCM 1  and TCM 2 . The drain (D) of TCM 1  also connects to voltage supply (V cc ) via a resistor (not shown) to form current source I. 
         [0039]    The drain of TCM 2  connect to the sources (S) of IGFETS T 1  and T 2 . The drain (D) of T 1  connects to voltage supply (V cc ) through resistor R 1 . The drain (D) of T 2  connects to voltage supply (V cc ) through resistor R 2 . Capacitor CH 1  is connected in parallel with resistor R 1 . Capacitor CH 2  is connected in parallel with resistor R 2 . The anode of diode D 6  is connected to the anode of diode D 5 . The connected anodes of D 5  and D 6  may provide one output terminal of floating output voltage Vf. The other terminal of floating output voltage Vf is connected to voltage power supply V. The cathode of diode D 6  is connected to node X and the cathode of diode D 5  is connected to node Y. Voltage input terminal (Control) is connected to the gate (G) of IGFET T 1  and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T 2  via inverting amplifier A 1 . Voltage input terminal (Control) is also connected to the input of inverting amplifier A 2 . The output of inverting amplifier A 2  is connected to the input of inverting amplifier A 3 . The output of inverting amplifier A 2  is also connected to one end of capacitor Ci 1 , the other end of capacitor Ci 1  connects to the anode of diode D 1  and the cathode of diode 
         [0040]    D 2 . The cathode of diode D 1  connects to the gates (C) of switches TCM 1  and TCM 2 . The anode of diode D 2  connects to ground. The output of inverting amplifier A 3  is connected to one end of capacitor Ci 2 , the other end of capacitor Ci 2  connects to the anode of diode D 4  and the cathode of diode D 3 . The cathode of diode D 4  connects to the gates (G) of switches TCM 1  and TCM 2 . The anode of diode D 3  connects to ground. Switch TCM 2  is the realization of current controlled source  36  shown in  FIG. 3 a    along with current control line  38  provided by the connection to the gate (G) of switch TCM 2 . 
         [0041]    Reference is now made to  FIG. 4  which shows a method  401  to operate level shifter circuit  30   b  shown in  FIG. 3 , according to an embodiment of the present invention. The explanation of method  401  that follows, relies for the most part on the circuit symmetry of level shifter circuit  30   b  operating in a dynamic mode of operation and as such reference will be made to one half of circuit  30   b,  namely the operation of switch T 1  and associated components. Accordingly as such, the operation of switch T 1  during the dynamic mode of operation of circuit  30   b  typically corresponds to the opposite operation of switch T 2  and associated components. That is to say, by virtue of inverting amplifier A 1 , when switch T 1  is switched on, switch T 2  is switched off and vice versa. Similarly, by virtue of amplifiers A 2  and A 3  the charging of capacitor Ci 1  via diodes D 1  and D 2  corresponds to the opposite charging of capacitor Ci 2  via diodes D 4  and D 3  respectively and vice versa. Additionally by virtue switch T 1  being on and switch T 2  off and vice versa, the charging of capacitor CH 1  and diode D 6  corresponds to the opposite charging of capacitor CH 2  and diode D 5  respectively. 
         [0042]    During quiescent operation of circuit  30   b  when no voltage is applied to voltage input terminal (Control), capacitors Ci 1  and Ci 2  are charged (step  403 ). Current I is at a minimal value and both switches T 1  and T 2  are off. 
         [0043]    During the dynamic mode of operation, voltage input terminal (Control) has a voltage level applied (step  405 ) such that switch T 1  is turned on and transistor T 2  is turned off. The current I is pushed high by the discharge of capacitor Ci 1  and consequently the current through switch T 1 , which mirrors current I, is increased (step  407 ). The change in current I, causes the output voltage Vf to vary in sympathy with the input voltage effectively causing a voltage level shift of the input voltage applied to voltage input terminal (Control) in step  405 . The increased current through switch T 1  quickly charges floating capacitor CH 1  and Miller capacitance of switch T 1 , which reduces the switching time of switch T 1 . Overflow of the charging of capacitor CH 1  is typically discharged by diode D 6 . 
         [0044]    Shifter circuit  30   b  can either use or not use capacitors CH 1  and CH 2 . The reason for capacitors CH 1  and CH 2  is to prevent a mismatch of the level shifter circuit  30   b  output via switches T 1  and T 2  not being matched. 
         [0045]    The definite articles “a”, “an” is used herein, such as “a charge storage circuit”, “a switch” have the meaning of “one or more” that is “one or more charge storage circuits” or “one or more switches”. 
         [0046]    Although selected embodiments of the present invention have been shown and described, it is to be understood the present invention is not limited to the described embodiments. 
         [0047]    Instead, it is to be appreciated that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and the equivalents thereof.