Abstract:
The high side or low side FET of a buck converter, or both, are replaced by plural parallel devices of different threshold voltage and are turned on and off in a sequence which offers the best turn on and turn off characteristics related to high and low threshold voltages. The parallel devices can have the same or different active areas.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/913,597, filed Apr. 24, 2007, the entire disclosure of which is incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to a switch mode power supply circuit such as a synchronous buck converter and more specifically relates to such a circuit with parallel switches of different threshold voltage. 
       BACKGROUND OF THE INVENTION 
       [0003]    Switch-mode power supply circuits such as synchronous buck converters are well known.  FIG. 1  shows a typical synchronous buck converter circuit in which an input d-c voltage Vin is applied to MOSFETs Q 1  and Q 2 , which may be silicon or III-Nitride based devices. The node between Q 1  and Q 2  is connected to output inductor L and output capacitor C. The output voltage V o  is connected to the output load which has a voltage lower than that of V in . 
         [0004]    In operation, an integrated circuit IC, of well known structure, is connected to the gates of Q 1  and Q 2  as shown by dotted lines and turns Q 1  and Q 2  on and off at a controlled frequency to maintain a fixed predetermined output voltage at node V o . More particularly, FET Q 2  is turned on when Q 1  is off, and is turned off when Q 1  is off so that a current I L  flows through inductor L. This drive circuit can be integrated with or separate from the MOSFETs Q 1  and Q 2 . 
         [0005]    Each FET Q 1  and Q 2  has a respective fixed threshold gate voltage V TH  at which it turns on. Each threshold voltage will produce its own peak performance at different load conditions and different on/off conditions. The threshold voltage selected for each device is a trade-off value selected for acceptable performance over the range of load conditions. For example, at full output load the V TH  of Q 1  should be low to reduce the R DSON  of Q 1  and thus reduce turn on loss. At light load or no load however, the V TH  of Q 1  should be higher to reduce turn-off loss without the penalty of too high an R DSON  loss. Thus, in some cases it would be desirable if Q 1  were able to turn on with a lower V TH  but turn off with a higher V TH  for the lowest switching loss. However, the V TH  of Q 1  must be selected as a trade-off for these opposing conditions. 
         [0006]    As to FET Q 2 , it would be desirable to have a high V TH  for Cdv/dt immunity at turn off, but a low V TH  drive at light load to minimize gate drive loss. Its V TH  however, is selected at a trade-off value which would be acceptable over the range of load conditions. 
       BRIEF DESCRIPTION OF THE INVENTION 
       [0007]    In accordance with the invention, one or both of FETs Q 1  and Q 2  is formed with at least 2 parallel devices of different V TH  with separate gate connections. Thus, each device can have either of two (or more) different threshold voltages which are switched in and out, depending on load conditions. The individual FETs of each pair may be both silicon; or both III-Nitride such as a GaN device; or one or more silicon devices and one or more III-Nitride devices. 
         [0008]    Further, the FETs with different threshold voltages can be respective discrete FETs in parallel or can be monolithically integrated in a common silicon or III-Nitride chip. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  shows a prior art switch mode power supply, in the form of a buck converter circuit with high-side and low-side switching devices of respectively fixed threshold voltages. 
           [0010]      FIG. 2  shows a first embodiment of the invention in which the high side switching device consists of two FETs having different threshold voltage. 
           [0011]      FIG. 3  shows a first drive scheme for driving the gates of the two high side FETs. 
           [0012]      FIG. 4  shows a second drive scheme for driving the gates of the two high side FETs of  FIG. 2  under a relatively high load condition. 
           [0013]      FIG. 5  shows the second drive scheme of  FIG. 4  for driving the two high side FETs under a relatively low load condition. 
           [0014]      FIG. 6  shows a second embodiment of the invention in which low-side FET Q 2  of  FIG. 1  consists of at least two FETs Q 2 -L and Q 2 -H respectively of different threshold voltages with Q 2 -H having a higher V TH  and Q 2 -L having a relatively lower V TH . 
           [0015]      FIG. 7  shows a timing diagram of a first drive scheme for driving the FETs Q 1 , Q 2 -H and Q 2 -L of the circuit of  FIG. 6 . 
           [0016]      FIGS. 8 and 9  show second timing diagrams for FETs Q 2 -L and Q 2 -H for light loads and full loads respectively. Note that the gate voltage need not be a fixed value. Thus, a high voltage gate drive, for example, 5 volts and a low voltage gate drive, for example 3.3 volts can be applied to the high V TH  and low V TH  FETs respectively to reduce gate charge losses and enhance R DSON . For example, at light load, only Q 2 -L is switched with Q 2 -H off, which reduces gate charge loss and improves efficiency at light load. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0017]      FIG. 2  shows the circuit of  FIG. 1 , modified to show the invention applied to FET Q 1  which consists of two (or more) parallel FETs, labeled Q 1 -H and Q 1 -L, having separate gate electrodes. FET Q 1 -H has a higher V TH  and FET Q 1 -L has a lower V TH  compared to that of FET Q 1 -H. The FETs Q 1 -L and Q 1 -H may be sized differently and may have different active areas. 
         [0018]    3 or more parallel FET could be used in the Q 1  position, each having a progressively higher V TH . 
         [0019]    Further, the IC may be coupled to the load as shown by dotted lines to provide gate signals to Q 1 -H and Q 1 -L in accordance with the measured load current. 
         [0020]    A first drive scheme for FETs Q 1 -L and Q 1 -H is shown in  FIG. 3 , where it is seen that the lower V TH  FET Q 1 -L, with faster turn on is first to turn on when gate voltage is applied from the IC, while Q 1 -H, with higher V TH  and faster turn off is last to turn off Thus, the arrangement of  FIG. 2  has the benefit of both fast turn on and fast turn off, which is not possible with the prior art circuit and a single FET. 
         [0021]      FIG. 4  shows a second drive scheme, wherein, at full load, Q 1 -L which is operable at reduced R DSON  at high load is turned on first and off last. Q 1 -H may turn on second and off first, or, if desired, may not turn on at all as shown by the alternate dotted line. 
         [0022]      FIG. 5  shows the second drive scheme for light load, where Q 1 -H is first to turn on and last to turn off If desired, turn on of Q 1 -L may be prevented at light load as shown by the alternative dotted line. 
         [0023]    Note further that Q 1 -L may be much smaller in active area than Q 1 -H. 
         [0024]      FIG. 6  shows the invention applied to FET Q 2 , in which two or more parallel FETs Q 2 -L and Q 2 -H replace FET Q 2  in  FIG. 1  and have a relatively low and a relatively high V TH  respectively. For example, FET Q 2 -L may have a V TH  of about 3.3 volts and FET Q 2 -H may have QV TH  of about 5 volts. 
         [0025]    FETs Q 2 -L and Q 2 -H have separate and isolated gates which will be driven by IC, depending on load conditions. 
         [0026]      FIG. 7  shows a first drive scheme for FETs FETs Q 2 -L and Q 2 -H of  FIG. 6 . It is seen that FET Q 2 -L with the lower V TH  turns on first and Q 2 -H with the higher V TH  and better Cdv/dt immunity turns off last, thus making the best use of the threshold voltages of the two FETs. 
         [0027]      FIGS. 8 and 9  show a second drive scheme for the circuit of  FIG. 6 , where, under full load, ( FIG. 9 ) only FET Q 2 -H operates, while under light load, ( FIG. 8 ) only FET Q 2 -L operates. Note that the two FETs Q 2 -H and FET Q 2 -L) can have different active areas for the best R DSON S. 
         [0028]    It is also possible to combine  FIGS. 2 and 6  together so that each of Q 1  and Q 2  are composed of plural parallel FETs of different V TH S. Each of the parallel FETs can be copacked as a single discrete and can be in integrated form in silicon on GaN or the like. 
         [0029]    While embodiments of the invention are shown for a buck converter, the invention has application to any other load switching. 
         [0030]    Further, the invention can employ vertical conduction or lateral conduction or planar silicon MOSFETs or III-Nitride devices or combination of Silicon-based and III-Nitride based devices with diverse threshold voltages and preferred selection of such devices in response to load current. 
         [0031]    Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.