Abstract:
In an example embodiment, an apparatus includes a sensing device. The sensing device includes circuitry configured to sense self-capacitance and circuitry configured to sense mutual-capacitance, each configured to detect capacitance values corresponding to whether an object is proximate to a touch screen. The sensing device is configured to measure a first capacitance value using the self-capacitance circuitry during self-capacitance sensing operations and to measure a second capacitance value using the mutual-capacitance circuitry during mutual-capacitance sensing operations.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of and claims benefit to pending U.S. patent application Ser. No. 12/395,462, filed Feb. 27, 2009, which is a non provisional of and claims the benefit of U.S. Provisional Patent Application No. 61/067,539 filed Feb. 27, 2008, all of which are incorporated by reference herein in their entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates generally to touch sensors and, more particularly, to capacitive touch sensors. 
       BACKGROUND 
       [0003]    Capacitive touch sensors may be used to replace mechanical buttons, knobs and other similar mechanical user interface controls. The use of a capacitive sensor allows for the elimination of complicated mechanical switches and buttons, providing reliable operation under harsh conditions. In addition, capacitive sensors are widely used in modern customer applications, providing new user interface options in existing products. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Embodiments are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
           [0005]      FIG. 1  illustrates alternative models of two electrodes situated close to each other, according to one embodiment; 
           [0006]      FIG. 2  illustrates one embodiment of a self-capacitance circuit that uses a charge accumulation technique; 
           [0007]      FIG. 3  illustrates a block diagram of an apparatus for measuring mutual or self capacitance, according to one embodiment; 
           [0008]      FIG. 4A  illustrates one embodiment of a capacitance to current sink converter having an integration capacitor coupled to ground; 
           [0009]      FIG. 4B  illustrates one embodiment of a capacitance to current sink converter having an integration capacitor coupled to a high voltage supply potential; 
           [0010]      FIG. 5A  illustrates one embodiment of a capacitance to current sink converter having an integration capacitor coupled to ground; 
           [0011]      FIG. 5B  illustrates one embodiment of a capacitance to current sink converter having an integration capacitor coupled to a high voltage supply potential; 
           [0012]      FIG. 6  illustrates phases of a converter operation, according to one embodiment; 
           [0013]      FIG. 7A  illustrates one embodiment of a capacitance to current sink converter used for mutual capacitance measurement, having an integration capacitor coupled to ground; 
           [0014]      FIG. 7B  illustrates one embodiment of a capacitance to current sink converter used for mutual capacitance measurement, having an integration capacitor coupled to V CC ; 
           [0015]      FIG. 8A  illustrates one embodiment of a capacitance to current source converter having an integration capacitor coupled to ground; 
           [0016]      FIG. 8B  illustrates one embodiment of a capacitance to current source converter having an integration capacitor coupled to a high voltage supply potential; 
           [0017]      FIG. 9A  illustrates one embodiment of a capacitance to current sink converter used for self capacitance measurement, having an integration capacitor coupled to ground; 
           [0018]      FIG. 9B  illustrates one embodiment of a capacitance to current sink converter used for self capacitance measurement, having an integration capacitor coupled to a high voltage supply potential; 
           [0019]      FIG. 10A  illustrates one embodiment of a capacitance to current source converter used for self capacitance measurement, having an integration capacitor coupled to ground; 
           [0020]      FIG. 10B  illustrates one embodiment of a capacitance to current source converter used for self capacitance measurement, having an integration capacitor coupled to a high voltage supply potential; 
           [0021]      FIG. 11  illustrates one embodiment of an interval timer method for capacitance measurement; 
           [0022]      FIG. 12  illustrates one embodiment of a resettable current integrator with an operation amplifier and an analog-to-digital converter (ADC); 
           [0023]      FIG. 13  illustrates one embodiment of a current-to-voltage converter built around an operational amplifier; 
           [0024]      FIG. 14  illustrates one embodiment of a capacitance to current converter with a conversion circuit; 
           [0025]      FIG. 15  illustrates one embodiment of a capacitance to current converter with a low pass filter; 
           [0026]      FIG. 16  illustrates one embodiment of a sigma-delta modulator configured as a capacitance to duty cycle converter; 
           [0027]      FIG. 17  illustrates one embodiment of a low pass filter with a differential analog to digital converter; 
           [0028]      FIG. 18A  illustrates base capacitance current compensation using a resistor as a current sink in a capacitance to current converter, according to one embodiment; 
           [0029]      FIG. 18B  illustrates base capacitance current compensation using a resistor for a current source in a capacitance to current converter, according to one embodiment; 
           [0030]      FIG. 19A  illustrates base capacitance current compensation using a current source as a current sink in a capacitance to current converter, according to one embodiment; 
           [0031]      FIG. 19B  illustrates base capacitance current compensation using a current source in a capacitance to current converter, according to one embodiment; 
           [0032]      FIG. 20A  illustrates using a current mirror with a voltage conversion system, according to one embodiment; 
           [0033]      FIG. 20B  illustrates using a current mirror with a current conversion system, according to one embodiment; 
           [0034]      FIG. 20C  illustrates one embodiment of a current mirror using a bipolar process technology; and 
           [0035]      FIG. 21  illustrates one embodiment of a capacitance measurement circuit in a multi-touch touchpad system. 
       
    
    
     DETAILED DESCRIPTION 
       [0036]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description. 
         [0037]    Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. 
         [0038]    A capacitive sensor may be characterized by a base capacitance that includes a self capacitance component and a mutual capacitance component. Since the values of these capacitance components affect the operation of the capacitive touch sensor and may vary from one capacitive sensor to another, a capacitive sensing circuit may benefit from the capability of independently measuring the self and mutual capacitances of a capacitive sensor. 
         [0039]    Apparatus for and methods of measuring mutual and self capacitance in a capacitive touch sensor are described. The apparatus and methods described herein may be used in capacitive touch detection systems such as, for example, capacitive touch screens and, in particular, with capacitive touch screens having multiple simultaneous touch detection capabilities. Alternatively, the apparatus and methods described herein may be used with single touch detection systems or other types of capacitive touch system. 
         [0040]    Embodiments of the present invention allow for measurement of two or more electrodes&#39; mutual and self capacitance separately. Capacitance measurement can be performed with a single pair of electrodes or with the use of a multiple electrode system. Alternative models of two electrodes situated close to each other are shown at  FIG. 1 , where C e1    101  and C e2    102  are electrode self capacitances, and C m    103  is the mutual capacitance between the two electrodes E 1    104  and E 2    105 . 
         [0041]    There are various circuit implementations that may be used for performing capacitance measurement.  FIG. 2  illustrates a self-capacitance circuit  200  that uses a charge accumulation technique to measure the capacitance C X    204 . A charge accumulation technique operates in the following way: initially the integration capacitor is reset by turning on the reset signal for some time. After reset, the switches  201  and  202  start operation in the two non-overlapping phases. The voltage on C int    203  starts increasing. The sensing capacitance is determined by the number of switching cycles used to get the integrator capacitor voltage to some threshold value. 
         [0042]    With such a charge accumulation technique, the voltage on the integration capacitance rises exponentially with respect to time (which can be measured by the cycle count). This relationship can be linearized for measurement methods where capacitance is calculated as a function of integration capacitor voltage after a predefined number of cycles. Also, the mutual capacitance measurement scheme has some sensitivity to the sensor self capacitance, which decreases the measurement accuracy. 
         [0043]      FIG. 3  illustrates a block diagram of a capacitance measurement circuit for measuring mutual or self capacitance, according to one embodiment of the present invention. The apparatus illustrated in  FIG. 3  can be used for separately measuring mutual or self sensor capacitances. In order to measure a mutual capacitance, the C e 1, C e 2 capacitance influence should be excluded. This can be accomplished by charging and discharging the C e 2 electrode from a low-impedance voltage source and keeping the voltage of the C e 1 electrode close to constant to minimize the influence of its charge-discharge current. In order to measure the self-capacitance (of C e 1 or C e 2) the voltage change across C m  should be kept to zero to minimize the influence of this capacitance on the measurement results. 
         [0044]    The capacitance measurement circuit  300  can be separated into two parts: the switching capacitor front-end capacitance to current (C-I) converter  301 , and the back-end current to digital value (I-code) converter  302 , as illustrated in  FIG. 3 . In the following description, the front-end and back-end circuits are described separately. A switching capacitor front-end converts the sensing capacitance to current pulses (C-I Converter). The back-end system averages the current and converts it into readable digital values (I-Code Converter). The circuits described herein are based on a switching capacitor technique in capacitance to current converter circuits. 
         [0045]      FIGS. 4A ,  4 B,  5 A and  5 B show different embodiments for a capacitance to current converter (CTC or C-I Converter) for mutual capacitance measurement. In the following figures, a voltage buffer  401  resides between the integration capacitor C int    406  and the switches  402 ,  404  connecting to the mutual electrodes of the CTC. It should be noted that the integration capacitor C int    406  is considered as part of the current measurement system and shown here for ease of explanation. The integration capacitor  406  can be connected between the converter output and a fixed potential net, for example, GND and Vcc, as illustrated in  FIGS. 4A and 4B  respectively. 
         [0046]    The operation of the circuit may be described in several stages, which are repeated in cycle. Table 1 contains the switching sequence of switches for the circuits shown in  FIGS. 4A and 4B . 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Switching sequence of switches shown in FIGS. 4A and 4B. 
               
             
          
           
               
                   
                 Switch 
                 Switch 
                 Switch 
                 Switch 
                   
               
               
                 Stage 
                 402 
                 403 
                 404 
                 405 
                 U Cint , U Ce1 , U Ce2 , U Cm   
               
               
                   
               
               
                 1 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cint  = U 0   
               
               
                 2 
                 ON 
                 OFF 
                 ON 
                 OFF 
                 U Cm  = 0, 
               
               
                   
                   
                   
                   
                   
                 U Ce1  = U Ce2  = U C   int  = U buf   
               
               
                 3 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = 0, 
               
               
                   
                   
                   
                   
                   
                 U Ce1  = U Ce2  = U Cint   
               
               
                 4 
                 OFF 
                 ON 
                 OFF 
                 ON 
                 U Cm  = U Cint  = U Ce1 , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = 0 
               
               
                 5 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = U Ce1 , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = 0 
               
               
                   
               
             
          
         
       
     
         [0047]    Table 2 contains the switching sequence of switches for the circuits shown in  FIGS. 5A and 5B . 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Switching sequence of switches shown in FIGS. 5A and 5B. 
               
             
          
           
               
                   
                 Switch 
                 Switch 
                 Switch 
                 Switch 
                   
               
               
                 Stage 
                 402 
                 403 
                 404 
                 405 
                 U Cint , U Ce1 , U Ce2, , U Cm   
               
               
                   
               
               
                 1 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cint  = U 0   
               
               
                 2 
                 OFF 
                 ON 
                 ON 
                 OFF 
                 U Cm  = U buf  = U Cint  = U Ce1   
               
               
                 3 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = U Cint  = U Ce1   
               
               
                 4 
                 ON 
                 OFF 
                 OFF 
                 ON 
                 U Cm  = 0, U Ce1  = U Cint , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = U Cint   
               
               
                 5 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = 0, U Ce1  = U Cint , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = U Cint   
               
               
                   
               
             
          
         
       
     
         [0048]    The stages from 2 to 5 are performed in cycles. In effect, the circuits shown in  FIGS. 4A and 4B  act as current sinks, and the circuits shown in  FIGS. 5A and 5B  act as current sources. The integration capacitor C int    406  is external to the CTC and is not part of the current measurement circuit. 
         [0049]      FIG. 6  illustrates one embodiment of the operation phases for the circuits shown in  FIGS. 4A and 4B . During the first phase, both ends of the C m    103  are connected to voltage buffer  401 . During the second phase, the left C m  terminal is grounded and the right terminal is connected to the integration capacitor C int    406 . 
         [0050]    For both circuits, an averaged absolute current sink/source (I s ) value can be calculated by Equation 1: 
         [0000]        I   S   =f   sw   ·U   Cint   ·C   m   (1)
 
         [0000]    where, f sw  is the switching frequency of phases 2-5 repeating. It should be noted that the capacitance of C e 1 electrode  102  is shunted by switch  402  or  403  in each operation phase and does not have an impact on the output current. The capacitance of the C e1  electrode  101  has a potential equal to U Cint  during both charge transfer stages and is not recharged between different operation phases. Therefore, the output current is determined by the value of C m    103 . 
         [0051]    A special case of the current converter operation is now considered, when it is loaded by stand-alone integration capacitor C int    406 . In this case, the relationship between the voltage change on U cint  and the cycles count N has a nonlinear exponential character, as expressed in Equation 2: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       U 
                       
                         C 
                          
                         
                             
                         
                          
                         int 
                       
                       N 
                     
                     = 
                     
                       
                         U 
                         
                           C 
                            
                           
                               
                           
                            
                           int 
                         
                         0 
                       
                       · 
                       
                         
                           ( 
                           
                             1 
                             - 
                             
                               
                                 C 
                                 m 
                               
                               
                                 C 
                                 int 
                               
                             
                           
                           ) 
                         
                         N 
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     ( 
                     
                       
                         U 
                         
                           C 
                            
                           
                               
                           
                            
                           int 
                         
                         N 
                       
                       ≈ 
                       
                         
                           U 
                           
                             C 
                              
                             
                                 
                             
                              
                             int 
                           
                           0 
                         
                         · 
                         
                            
                           
                             
                               - 
                               N 
                             
                              
                             
                               
                                 C 
                                 m 
                               
                               
                                 C 
                                 int 
                               
                             
                           
                         
                       
                     
                     ) 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0052]    where, N is the quantity of conversion cycles and U Cint   0  is the voltage on the integration capacitor  406  at the initial time. 
         [0053]    The exponential character of this dependence is caused by the positive voltage feedback via buffer  401 : increasing voltage on the integration capacitor  406  causes a larger charge quantum being added in each phase and an increase in the speed of the integration capacitor  406  voltage rising. This may be considered as drawback in some applications, especially when the current measurement circuit does not keep a voltage on the integration capacitor  406  constant. 
         [0054]    To avoid this drawback, the circuit embodiments illustrated in  FIGS. 7A ,  7 B,  8 A, and  8 B may be used. The difference between the circuit embodiments illustrated in  FIGS. 7A ,  7 B,  8 A, and  8 B, versus those illustrated in  FIGS. 4A ,  4 B,  5 A, and  5 B, is that the right terminal of C m    103  is connected to the fixed voltage source V DD  instead of the floating buffer output voltage of the analog buffer  701 . Only the switch  702  connection is changed on the circuits illustrated in  FIGS. 7A ,  7 B,  8 A, and  8 B. The switching sequence of the switches illustrated in  FIGS. 7A and 7B  is shown in Table 3 below. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 Switching sequence of switches in FIGS. 7A and 7B. 
               
             
          
           
               
                   
                 Switch 
                 Switch 
                 Switch 
                 Switch 
                   
               
               
                 Stage 
                 702 
                 703 
                 704 
                 705 
                 U Cint , U Ce1 , U Ce2, , U Cm   
               
               
                   
               
               
                 1 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cint  = U 0   
               
               
                 2 
                 ON 
                 OFF 
                 ON 
                 OFF 
                 −U Cm  = U Vdd  − U Cint , 
               
               
                   
                   
                   
                   
                   
                 U Ce1  = U C   int  = U buf , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = U Vdd   
               
               
                 3 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = U Vdd  − U Cint , 
               
               
                   
                   
                   
                   
                   
                 U Ce1  = U C   int , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = U Vdd   
               
               
                 4 
                 OFF 
                 ON 
                 OFF 
                 ON 
                 U Cm  = U Cint  = U Ce1 , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = 0 
               
               
                 5 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = U Ce1 , U Ce2  = 0 
               
               
                   
               
             
          
         
       
     
         [0055]    The switching sequence of the switches illustrated in  FIGS. 8A and 8B  is shown by Table 4 below. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 Switching sequence of switches in FIGS. 8a and 8b 
               
             
          
           
               
                   
                 Switch 
                 Switch 
                 Switch 
                 Switch 
                   
               
               
                 Stage 
                 702 
                 703 
                 704 
                 705 
                 U Cint , U Ce1 , U Ce2, , U Cm   
               
               
                   
               
               
                 1 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cint  = U 0   
               
               
                 2 
                 OFF 
                 ON 
                 ON 
                 OFF 
                 U Cm  = U buf  = U Cint  = U Ce1   
               
               
                 3 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = U Cint  = U Ce1   
               
               
                 4 
                 ON 
                 OFF 
                 OFF 
                 ON 
                 −U Cm  = U Vdd  − U Cint , 
               
               
                   
                   
                   
                   
                   
                 U Ce1  = U Cint , U Ce2  = U Vdd   
               
               
                 5 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cm  = 0, U Ce1  = U Cint , 
               
               
                   
                   
                   
                   
                   
                 U Ce2  = U Vdd   
               
               
                   
               
             
          
         
       
     
         [0056]    The stages from 2 to 5 are performed in cycles. As a result, the average current flowing out of the C int    406  capacitor for the circuits on  FIGS. 7A ,  7 B,  8 A, and  8 B can be calculated by Equation 3: 
         [0000]        I   S   =f   sw   ·U   vdd   ·C   m   (3)
 
         [0000]    For the given values of f sw  and V DD  parameters, the output current (I S ) linearly depends only on C m  and is proportional to f sw  and V DD . The change of current direction is done by a change of the switches&#39; operation phases. If the current measurement subsystem does not load the integration capacitor C int    406 , a voltage on this capacitor changes linearly with the number of cycles N, as expressed in Equation 4: 
         [0000]    
       
         
           
             
               
                 
                   
                     U 
                     
                       C 
                        
                       
                           
                       
                        
                       int 
                     
                     N 
                   
                   = 
                   
                     
                       U 
                       Vdd 
                     
                     · 
                     
                       ( 
                       
                         1 
                         - 
                         
                           N 
                           · 
                           
                             
                               C 
                               m 
                             
                             
                               C 
                               int 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0057]    A similar Equation 5 is used for describing the circuits illustrated in  FIGS. 8A and 8B : 
         [0000]    
       
         
           
             
               
                 
                   
                     U 
                     
                       N 
                        
                       
                           
                       
                     
                   
                   = 
                   
                     N 
                     · 
                     
                       U 
                       Vdd 
                     
                     · 
                     
                       
                         C 
                         m 
                       
                       
                         C 
                         int 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0058]    The circuit embodiments described above may be used for self-capacitance measurement with minimal hardware changes by routing the buffer signal to the right side switches. To do this, the switches voltages may be adjusted in such way that the voltage change on the mutual capacitance C m  is equal to zero between different phases. In other circuit configurations, the voltage on C e 2 is kept constant but the voltage on C m  is varied. In the circuit embodiments illustrated in  FIGS. 7A ,  7 B,  8 A, and  8 B, the voltage on C e 2 is varied and the voltage on C m  is kept constant. 
         [0059]      FIGS. 9A and 9B  illustrate embodiments of a capacitance to current sink converter for self capacitance measurement. As previously noted, the integration capacitor C int    406  is considered part of the current measurement system and is shown here for ease of explanation. The integration capacitor  406  can be connected between the converter output and any fixed potential net, for example, GND and V CC , as illustrated in  FIGS. 9A and 9B  respectively. Alternatively, the integration capacitor  406  can be connected between the converter output and other fixed potentials. The switching sequence of switches illustrated in the circuit of  FIGS. 9A and 913  is shown in Table 5 below. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                 Switching sequence of switches illustrated in FIGS. 9A, 9B. 
               
             
          
           
               
                   
                 Switch 
                 Switch 
                 Switch 
                 Switch 
                   
               
               
                 Stage 
                 902 
                 903 
                 904 
                 905 
                 U Cint , U Ce1 , U Ce2, , U Cm   
               
               
                   
               
               
                 1 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cint  = U 0   
               
               
                 2 
                 OFF 
                 ON 
                 ON 
                 OFF 
                 U Ce1  = U Ce2  = 0, U Cm  = 0 
               
               
                 3 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Ce1  = U Ce2  = 0, U Cm  = 0 
               
               
                 4 
                 ON 
                 OFF 
                 OFF 
                 ON 
                 U e1  = U Cint  = U Ce2 , 
               
               
                   
                   
                   
                   
                   
                 = U Cm  = 0 
               
               
                 5 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U e1  = U Cint  = U Ce2 , 
               
               
                   
                   
                   
                   
                   
                 = U Cm  = 0 
               
               
                   
               
             
          
         
       
     
         [0060]    The switching sequence of switches in  FIGS. 10A and 10B  is shown in Table 6 below. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 6 
               
             
             
               
                   
               
               
                 Switching sequence of switches illustrated in FIGS. 10A, 10B. 
               
             
          
           
               
                   
                 Switch 
                 Switch 
                 Switch 
                 Switch 
                   
               
               
                 Stage 
                 902 
                 903 
                 904 
                 905 
                 U Cint , U Ce1 , U Ce2, , U Cm   
               
               
                   
               
               
                 1 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Cint  = U 0   
               
               
                 2 
                 ON 
                 OFF 
                 ON 
                 OFF 
                 U Ce1  = U Ce2  = U Vdd , 
               
               
                   
                   
                   
                   
                   
                 U Cm  = 0 
               
               
                 3 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U Ce1  = U Ce2  = U Vdd ,, 
               
               
                   
                   
                   
                   
                   
                 U Cm  = 0 
               
               
                 4 
                 OFF 
                 ON 
                 OFF 
                 ON 
                 U e1  = U Cint  = U Ce2 , 
               
               
                   
                   
                   
                   
                   
                 U Cm  = 0 
               
               
                 5 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 U e1  = U Cint  = U Ce2 , 
               
               
                   
                   
                   
                   
                   
                 U Cm  = 0 
               
               
                   
               
             
          
         
       
     
         [0061]    Stages  2  through  5  are performed in cycles. As a result, the average current flowing into capacitor C int  for the circuits illustrated in  FIGS. 9A and 98  is described by Equation 6 below: 
         [0000]        I   S   =f   sw   ·U   Cint   ·C   e1   (6)
 
         [0062]    The average current flowing out of C int  capacitor for the circuits illustrated in  FIGS. 10A and 10B  are described by Equation 7: 
         [0000]        I   S   =f   sw ·( U   vdd   −U   Cint )· C   e1   (7)
 
         [0063]    The potential difference on electrode capacitor C m    103  is equal to approximately zero during the stages of charge transfer and does not have an impact on the measurement. The C e   2  electrode  102  capacitance is switched off by switches  902  and  904  during the stages of operation. In this case, the relationship between the voltage change on U Cint  and the cycle count N has a nonlinear exponential character for the circuits illustrated in  FIGS. 9A and 9B , in accord with Equation 8 below: 
         [0000]    
       
         
           
             
               
                 
                   
                     U 
                     
                       C 
                        
                       
                           
                       
                        
                       int 
                     
                     N 
                   
                   = 
                   
                     
                       U 
                       
                         C 
                          
                         
                             
                         
                          
                         int 
                       
                       0 
                     
                     · 
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                             
                               C 
                               
                                 e 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             
                               C 
                               int 
                             
                           
                         
                         ) 
                       
                       N 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0064]    Equation 9 below similarly describes the circuits illustrated in  FIGS. 10A and 10B : 
         [0000]    
       
         
           
             
               
                 
                   
                     U 
                     
                       C 
                        
                       
                           
                       
                        
                       int 
                     
                     N 
                   
                   = 
                   
                     
                       U 
                       Vdd 
                     
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         [0065]    Various alternative variants of the conversion circuits described above may be used, including, for example: 
         [0066]    Time measurement of the integration capacitor voltage threshold crossing; 
         [0067]    Current integration using current integrator on the operational amplifier; 
         [0068]    Converting current-to-voltage the operational amplifier and measuring the voltage using the ADC; and 
         [0069]    Sigma-delta modulator circuits. 
         [0070]      FIG. 11  illustrates an interval timer method for capacitance measurement. In the circuit of  FIG. 11 , the integrator consists of a capacitor  406 . The circuit of  FIG. 11  operates in the following way. Initially, the voltage of integration capacitor  406  is set to U init  by turning on, for some time period, a switch  1102 . The comparator  1101  is used as threshold circuit and compares the voltage on the integration capacitor  406  with a reference voltage U ref . The capacitance is measured by the time measurement circuit  1103  as the time elapsed (in the cycles count) until the comparator  1101  is triggered. The time is inversely proportional to the converter current. It should be noted that for switching capacitor current sink schemes, an integrator initial voltage (U init ) is set higher than the threshold voltage (U ref ). For the current source schemes, the integrator initial voltage is lower than threshold voltage U ref . 
         [0071]    For more accurate current conversion, circuits based on current-to-voltage converters and current integrators may be used, as illustrated in the following figures.  FIG. 12  illustrates one embodiment of a resettable current integrator (where integration capacitor  1203  can be reset using switch  1204 ) with an operational amplifier  1201  and an analog-to-digital converter (ADC)  1202 . The ADC  1202  is used for integrator voltage measurement after the completion of a predefined number of integration cycles. 
         [0072]      FIG. 13  illustrates one embodiment of a current-to-voltage converter built around an operational amplifier  1301 . The converter of  FIG. 13  also functions as a low pass filter (LPF) due to the presence of the filter capacitor C filt    1302  in the amplified feedback path. The output voltage U S  is proportional to the input current I S . The circuit of  FIG. 13  operates continuously such that ADC conversion can be started any time after transient signals have stabilized. It should be noted that the buffer input inside the capacitance to code converter can be connected to the V ref  net for the circuits illustrated in  FIGS. 12 and 13 , taking into account that both operational amplifier inputs have approximately the same potential. The schematic diagram of such a circuit configuration is illustrated in  FIG. 14 , where the input of voltage buffer  1401  is connected to the V ref  net. 
         [0073]    In an alternative embodiment, when the V ref  voltage source has an acceptable low output resistance, then the voltage buffer  1401  may be eliminated from the circuits illustrated herein. As an example, the circuit from  FIG. 4  composed of the measurement circuit of  FIG. 13  is illustrated in  FIG. 15 . Accordingly,  FIG. 15  is an exemplary illustration of a capacitance to current converter with a low pass filter that can be implemented without a voltage buffer  1401  coupled to the reference voltage source V ref . In one embodiment, the reference voltage V ref  used to supply the switches in the capacitance to current converter is selected to be as close to V dd  as possible (limited by the working range of the operational amplifier  1301 ), to minimize the current flow out of C e 2  102  relative to the current flowing through C m    103 . In alternative embodiments, the switches in the converters can be supplied with other known voltages such as, for example, V dd . 
         [0074]    The sigma-delta modulator circuits can be effectively used for the current to code conversion. An advantage of the sigma-delta modulator circuits is their integrative nature.  FIG. 16  illustrates one possible example of a modulator implementation for a first order modulator. It should be noted that higher order modulator circuits can be used as well. The sigma-delta modulator of  FIG. 16  converts the current I S  to a code in output bitstream  1601 . The current I S  discharges modulation capacitor C mod    1602  until the voltage at C mod    1602  falls below V ref , at which point comparator  1603  asserts its output to latch  1604 , which outputs bits synchronously with a clock signal provided by clock  1605 . The latch  1604  then closes switch  1606  to recharge C mod    1602  for the next measurement cycle. 
         [0075]    In one embodiment, the capacitance measurement circuit embodiments described above may be used in touch sensitive devices. With such devices, a small capacitance change should be detected over the presence of large base capacitance. Such sensors have two components of capacitance, described in Equation 10 below: 
         [0000]        C   S   =C   Sconst   +C   Stouch   (10)
 
         [0000]    where, C Sconst  is the capacitance of sensor when touch is absent, and C Stouch  is the additional capacitance caused by an input, such as a finger touch. The informative part of the sensor capacitance C S  is the C Stouch  component. In order to increase the resolution of the sensor, the particular compensation of the current generated by the C Sconst  capacitance can be used. There are several possible implementations of this technique. In one embodiment, an ADC  1701  with differential inputs may be used as illustrated in  FIG. 17 . In the circuit of  FIG. 17 , the U comp  voltage is supplied to the second input of ADC  1701 . 
         [0076]    Alternative embodiments provide base capacitance current compensation using a programmable current source or a resistor, as illustrated in  FIGS. 18A ,  18 B,  19 A, and  19 B. More specifically,  FIG. 18A  illustrates base capacitance current compensation using a resistor R bias    1801  as a current source in a capacitance to current converter, according to one embodiment.  FIG. 18B  illustrates base capacitance current compensation using a resistor R bias    1811  as a current sink in a capacitance to current converter, according to one embodiment.  FIG. 19A  illustrates base capacitance current compensation using a current source  1901  as a current sink in a capacitance to current converter, according to one embodiment.  FIG. 19B  illustrates base capacitance current compensation using a current source  1911  in a capacitance to current converter, according to one embodiment. 
         [0077]    The capacitance measurement circuits described herein may be used for touch detection in single electrode systems, transmit/receive (TX-RX) systems, or in combined TX-RX and single electrode systems. The TX-RX systems can use the mutual capacitance change detection, and single electrode systems can use the self capacitance change detection. In some embodiments, additional multiplexers can be added for multiple electrode scanning. The capacitance measurement circuits described herein may be used in various applications including, for example, single button applications, multiple buttons applications, linear and radial sliders, dual dimension touchpads, and multi-touchpad applications. Multi-touchpad systems are composed of a matrix of RX and TX electrodes, where the presence (e.g., touch) of a finger (or other conductive object) is detected as a decrease in the mutual capacitance at the intersection of the TX-RX electrodes. 
         [0078]      FIGS. 20A ,  20 B, and  20 C illustrate using a current mirror in the conversion circuits.  FIG. 20A  shows an example of a circuit for current-to-voltage conversion using a low-pass filter, formed by the combination of load resistance R L    2002  and filter capacitor C filt    2003 . A filter output voltage can be measured using an ADC.  FIG. 20B  illustrates a current-to-current conversion circuit. A current is sourced to the filter capacitor C filt    2013 . The different circuits can be used for integration capacitor current measurement. In one embodiment, a current can be measured using a threshold comparator and a timer (not shown). In another embodiment, a filter capacitor voltage is measured using an ADC after running operation within a predefined amount of time. The current mirror has low input impedance, which allows keeping a current mirror input pin voltage close to a constant voltage (e.g. V CC ). This improves the operating conditions of the capacitance to current conversion circuit, allowing the use of a voltage buffer with a smaller slew rate and reduced current consumption. Also, the current mirror serves as a current amplifier, boosting the converter current by a multiple N. Many implementations of the current mirror circuit are possible, and one implementation is shown at  FIG. 20C . 
         [0079]      FIG. 21  illustrates a simplified schematic of a multi-touch pad system. The multi-touch pad system  2100  is composed of a dual dimension array (matrix) of electrodes  2101 , column and row signal multiplexers  2102  and  2103 , multiplexor control  2107 , clock source  2104 , drive switches  2105 , capacitance to current converter  301 , current to code converter  302 , and touch coordinate estimation system  2106 . The electrodes matrix can be fabricated from any conductive material, as copper, conductive ink, Indium Thin Oxide, PEDOT, etc. 
         [0080]    Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. 
         [0081]    In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.