Abstract:
Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals&#39; forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to the field of non-volatile memory devices; more specifically, it relates to non-volatile switching and memory devices using vertical nanotubes and the method of fabricating non-volatile switching and memory devices using vertical nanotubes.  
       BACKGROUND OF THE INVENTION  
       [0002]     There is a continuing need to improve the performance, decrease the power consumption and decrease the dimensions of solid-state electronic devices, particularly those used as cells for memory devices and as switching devices. Further, as semiconductor device sizes decrease, various sources of radiation have been shown to cause changes in state of semiconductor-based memory and switching devices.  
         [0003]     Therefore, there is a need for memory and switching devices that are both non-volatile and radiation hard.  
       SUMMARY OF THE INVENTION  
       [0004]     A first aspect of the present invention is a structure, comprising: an insulating layer on a top surface of a substrate; an electrically conductive bitline formed in the insulating layer or on a top surface of the insulating layer, a top surface of the bitline parallel to the top surface of the substrate; a first electrically conductive wordline having a bottom surface, a top surface and a first sidewall; a second electrically conductive wordline having a bottom surface, a top surface and a second sidewall, the top and bottom surfaces of the first and second wordlines parallel to the top surface of the bitline, the first and second sidewalls about perpendicular to the top surface of the bitline, the first and second wordlines spaced apart, the first and second sidewalls facing each other; a dielectric layer between the bottom surfaces of the first and second wordlines and the top surface of the bitline; a dielectric first spacer on the first sidewall and a dielectric second spacer on the second sidewall; the first and second spacers spaced apart, the first and second spacers facing each other, and the top surface of the bitline exposed between the first and second spacers; and at least one electrically conductive nanotube having a first end and an opposite second end, the first end permanently attached to the bitline, the at least one nanotube extending away from the top surface of bitline.  
         [0005]     A second aspect of the present invention is the first aspect of the present invention wherein the at least one nanotube is flexible and has a length between the first and second ends such that a portion of the one or more nanotubes proximate to the second end may reversibly contact either the first or the second spacers.  
         [0006]     A third aspect of the present invention is the first aspect of the present invention wherein the at least one nanotube is reversibly held in contact with the first or second spacers by van der Waals′ forces.  
         [0007]     A fourth aspect of the present invention is the first aspect of the present invention wherein the at least one nanotube is a carbon nanotube.  
         [0008]     A fifth aspect of the present invention is the first aspect of the present invention wherein the at least one nanotube is a single-wall carbon nanotube.  
         [0009]     A sixth aspect of the present invention is the first aspect of the present invention further including: means for voltage biasing the first wordline and the bitline opposite to the second wordline and for voltage biasing the second wordline and the bitline opposite to the first wordline.  
         [0010]     A seventh aspect of the present invention is the first aspect of the present invention further including: means for detecting a spike of current on the first or second wordline or on the bitline or means for sensing a change in capacitance between the first wordline and the bitline or between the second wordline and the bitline.  
         [0011]     An eighth aspect of the present invention is the first aspect of the present invention further including a third spacer on top of the first spacer, a total thickness of the first and second spacers measured perpendicular to the first sidewall greater than a thickness of the second spacer measured perpendicular to the second sidewall.  
         [0012]     A ninth aspect of the present invention is the first aspect of the present invention further including: means for sensing a tunneling current through the second spacer, the current flow between the second wordline and the bitline, the current flowing through the one or more nanotubes.  
         [0013]     A tenth aspect of the present invention is the first aspect of the present invention further including: a first dielectric cap having a bottom surface, a top surface and a third sidewall, the bottom surface of the first dielectric cap in direct physical contact and coextensive with the top surface of the first wordline; a second dielectric cap having a bottom surface, a top surface and a fourth sidewall, the bottom surface of the second dielectric cap in direct physical contact and coextensive with the top surface of the second wordline, the third and fourth sidewalls facing each other, the first spacer extending over and in direct physical contact with the third sidewall and the second spacer extending over and in direct physical contact with the fourth sidewall; and an electrically conductive third spacer on the first spacer and an electrically conductive fourth spacer on the second spacer, the third and fourth spacers spaced apart, the third and fourth spacers facing each other, a bottom surface of the third spacer facing and overhanging the top surface of the bitline exposed between the first and second spacers, and a bottom surface of the fourth spacer facing and overhanging the top surface of the bitline exposed between the first and second spacers.  
         [0014]     An eleventh aspect of the present invention is the tenth aspect of the present invention wherein: when an upper portion of the at least one nanotube proximate to the second end of the at least one nanotube is in contact with the first spacer, the second end of the at least one nanotube is positioned under but not touching a bottom surface of third spacer; and when the upper portion of the at least one nanotube proximate to the second end of the at least one nanotube is in contact with the second spacer, the second end of the at least one nanotube is positioned under but not touching the bottom surface of fourth spacer.  
         [0015]     A twelfth aspect of the present invention is the eleventh aspect of the present invention further including: means for voltage biasing the first wordline and the third spacer opposite to the second wordline and the bitline and for voltage biasing the second wordline and the fourth spacer opposite to the first wordline.  
         [0016]     A thirteenth aspect of the present invention is the eleventh aspect of the present further including: means for sensing a field emission current across a first gap between the second end of the at least one nanotube and the bottom surface of the third spacer when the upper portion of the at least one nanotube proximate to the second end of the at least one nanotube is in contact with the first spacer; and means for sensing a field emission current across a second gap between the second end of the at least one nanotube and the bottom surface of the fourth spacer when the upper portion of the at least one nanotube proximate to the second end of the at least one nanotube is in contact with the second spacer.  
         [0017]     A fourteenth aspect of the present invention is the first aspect of the present invention wherein the bitline comprises a catalytic material for the formation of carbon nanotubes. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0018]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0019]      FIGS. 1A through 1G  are cross-sectional views illustrating fabrication of a device according to a first embodiment of the present invention;  
         [0020]      FIG. 2  is an isometric cross-section of a device according to the first embodiment of the present invention;  
         [0021]      FIGS. 3A through 3G  are cross-sectional views illustrating fabrication of a device according to a second embodiment of the present invention;  
         [0022]      FIG. 4  is an isometric cross-section of a device according to the second embodiment of the present invention;  
         [0023]      FIGS. 5A through 5K  are cross-sectional views illustrating fabrication of a device according to a third embodiment of the present invention;  
         [0024]      FIG. 6  is an isometric cross-section of a device according to the third embodiment of the present invention; and  
         [0025]      FIGS. 7, 8  and  9 , are plan views illustrating memory arrays using devices according the embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Nanotubes are more correctly called fullerenes, which are closed-cage molecules comprised of atoms arranged in hexagons and pentagons. There are two types of fullerenes, namely closed spheroid cage fullerenes also called “bucky balls”, and fullerene tubes. Fullerene tubes come in two types, single-wall fullerenes tubes, which are hollow tube-like structures or and multi-wall fullerene tubes. Multi-wall fullerenes resemble sets of concentric cylinders. Single-wall fullerenes are hereinafter called single-wall nanotubes (SWNT) and multi-wall fullerenes are hereafter called multi-wall nanotubes (MWNT).  
         [0027]     While the present invention is described using electrically conductive single-wall and multiple-wall carbon nanotubes comprised of sp 2 -hybridized carbon, electrically conductive or semi-conductive single-wall and multiple wall nanotubes comprised of other electrically conductive or semi-conductive materials may be substituted for electrically conductive or semi-conductive single or multi-wall carbon nanotubes. For the purposes of the present invention, the term carbon nanotube (CNT) denotes either a carbon SWNT or a carbon MWNT unless otherwise specified.  
         [0028]     CNTs used in the embodiments of the present invention are grown on electrically conductive bitlines formed on or embedded in an insulating layer by exposing bitlines to a vapor mixture of a CNT precursor and optionally a CNT catalyst at an elevated temperature. In one example, the CNT precursor is hydrocarbon or hydrocarbon isomer mixture and the bitline comprises iron (Fe), cobalt (Co), nickel (Ni) or other materials known in the art. In one example, formation of CNTs is performed at elevated temperatures between about 400° C. to about 900° C.  
         [0029]     When non-carbon SWNTs and MWNTs are substituted for CNTs, besides changes to reactants used to form the non-carbon SWNTs and MWNTs, appropriate changes to the composition of the bitline may be required, however, the material of the bitline remains an electrically conductive material.  
         [0030]      FIGS. 1A through 1G  are cross-sectional views illustrating fabrication of a device according to a first embodiment of the present invention. In  FIG. 1A , formed on a top surface of a substrate  100  is a first insulating layer  105 . The top surface of substrate  100  defines a horizontal plane and a line perpendicular to the top surface of substrate  100  defines a vertical direction. Formed on a top surface of first insulating layer  105  is a bitline  110 . Alternatively, bitline  110  may be damascened into first insulating layer  105 , top surfaces of the first insulating layer  105  and bitline  110  being coplanar (see  FIG. 2 ). Formed on a top surface of bitline  110  (and exposed top surface of first insulating layer  105 ) is a first dielectric layer  115 .  
         [0031]     In one example, first insulating layer  105  comprises SiO 2 . In one example, bitline  110  comprises Fe, Co, Ni, other conductive CNT-catalytic material, or combinations thereof. In one example, bitline  110  comprises a layer of Fe, Co, Ni, or other CNT catalytic material and combinations thereof. In one example, bitline  110  comprises a layer Fe, Co, Ni, or other CNT catalytic material over a layer or layers of tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), aluminum (Al) or combinations thereof. In one example, first dielectric layer  115  comprises silicon nitride (Si 3 N 4 ).  
         [0032]     In  FIG. 1B , a first electrically conductive wordline  120 A and a second electrically conductive wordline  120 B are formed on a top surface of first dielectric layer  115 . First and second wordlines  120 A and  120 B are each covered by a respective dielectric cap  125  formed on respective top surfaces of the wordlines. First and second wordlines  120 A and  120 B and dielectric caps  125  may be formed, for example, by deposition of a conductive layer on the top surface of first dielectric layer  115 , deposition of a capping layer on a top surface of the conductive layer followed by a photolithographic masking process and an anisotropic etch to define the first and second wordlines and dielectric caps.  
         [0033]     A photolithographic masking process includes, applying a layer of photoresist, exposing the photoresist to actinic radiation through a patterned mask that will block the radiation from reaching regions of the photoresist layer, and developing the photoresist layer to generate a pattern of photoresist. After etching of underlying structure, the islands of photoresist are removed.  
         [0034]     In one example, first and second wordlines  120 A and  120 B comprise doped polysilicon, W, Ti, Ta, Cu, TiN, TaN, Al and combinations thereof. In one example, dielectric caps  125  comprise Si 3 N 4 .  
         [0035]     In  FIG. 1C , a conformal second dielectric layer  130  is formed over all exposed surfaces of first dielectric layer  115 , first and second wordlines  120 A and  120 B, and dielectric caps  125 . In one example, second dielectric layer  130  comprises Si 3 N 4 . In one example, second dielectric layer  130  is a high K (dielectric constant) material, examples of which include but are not limited metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high K dielectric material has a relative permittivity above about 10. In one example, second dielectric layer  130  is about 7 nm to about 20 nm thick.  
         [0036]     In  FIG. 1D , a reactive ion etch (RIE) process is performed to form, from second dielectric layer  130  (see  FIG. 1C ), dielectric sidewall spacers  135  on sidewalls of first and second wordlines  120 A and  120 B.  
         [0037]     In  FIG. 1E , a second insulating layer  140  is formed. Top surfaces of second insulating layer  140  are coplanar with top surfaces of dielectric cap  125 . In one example, second insulating layer  140  may be formed by deposition of a dielectric material to a depth greater than the distance between the top surface of first dielectric layer  115  and top surfaces of dielectric caps  125 , followed by a chemical-mechanical-polish (CMP). In one example second insulating layer  140  comprises SiO 2 .  
         [0038]     In  FIG. 1F , a trench  145  is formed between first and second wordlines  120 A and  120 B exposing a top surface  150  of bitline  110  by removing second insulating layer  140  and first dielectric layer  115  from between the wordlines. In one example, trench  145  is formed using a photolithographic masking process followed by a RIE.  
         [0039]     In  FIG. 1G , one or more electrically semi-conductive or conductive CNTs  155  are grown on exposed top surface  150  of bitline  110  between first and second wordlines  120 A and  120 B. CNTs  155  have two opposite ends. The first ends are permanently attached to bitline  110  but the second ends are not permanently attached to any other structure. CNTs  155  extend upward from bitline  110  in the generally vertical direction. In one example, growth conditions for CNTs  155  are selected so as to grow at least one and up to a number of CNTs sufficient to cover exposed dielectric spacers  135  on one or the other of wordlines  120 A or  120 B with about a single layer of upper ends of CNTs  155 . In one example, the growth of CNTs  155  is limited such that the CNTs do not extend above the top surfaces of dielectric caps  125 . CNTs  155  are flexible so as to be able to bend and temporally touch sidewall spacer  135  on wordline  120 A (shown) or touch sidewall spacer  135  on wordline  120 B. It is expected that single-wall CNTs will be more flexible than multi-wall CNTs.  45 ] Bitline  110 , wordlines  120 A and  120 B, dielectric caps  125 , dielectric spacers  135  and CNTs  155  comprise a switching or memory device (or memory cell)  225  according to the first embodiment of the present invention. Substrate  100  may be a semiconductor substrate, for example a bulk silicon or silicon-on-insulator (SOI) substrate, and include devices such as transistors, capacitors, resistors, diodes and inductors which are wired together to form support circuits for device  225 .  
         [0040]     Operation of device  225  is described infra, in relationship to  FIG. 2 , but a discussion of van der Waals′ forces is required first. Though not entirely understood, in general, van der Waals′ forces are attractive forces between molecules. Bonding in a molecule is caused by orbiting electrons. Any given electrons may be thought of being on one side or the other of a molecule in any one instance of time creating a surplus of negative charge on one side of the molecule and a lack of charge (positive charge) on the opposite side of the molecule, i. e. a dipole. When the dipoles on adjacent molecules are aligned positive pole to negative pole, negative pole to positive pole, there is a weak and transient electrostatic attraction. Since an object is made up of many molecules, there are always a finite number of pairs molecules having attracting dipoles. Van der Waals′ forces are very small forces and can be easily broken, but absent an external force to force two objects apart, objects attached to one another by van der Waals′ forces will remain attached. At the nano-scale, van der Walls; forces are significant forces.  
         [0041]     Because van der Waals′ forces do not require externally supplied power, the devices of the embodiments of the present invention when de-powered will retain the state in which they remained when last powered, and are thus non-volatile memory devices. Because van der Waals′ forces are not effected by ionizing radiation, the devices of the embodiments of the present invention will retain their state even when struck by ionizing radiation and are thus radiation-hard devices.  
         [0042]      FIG. 2  is an isometric cross-section of a device according to the first embodiment of the present invention. In  FIG. 2 , with a positive (negative) charge on first wordline  120 A and a negative (positive) charge on second wordline  120 B and bitline  110 , CNTS  155  will become negatively (positively) charged and be attracted toward first wordline  120 A. With sufficient voltage applied between first wordline  120 A and bitline  110 , the upper ends of CNTs  155  will press against dielectric sidewall spacer  135  on first wordline  120 A. With the voltage differential removed (first and second wordlines  120 A and  120 B and bitline all at the same potential), CNTS  155  will continue to stick to sidewall spacer  135  on first wordline  120 A because of van der Wall attraction between molecules in CNTs  155  and molecules in dielectric sidewall spacer  135 .  
         [0043]     The location of CNTs  155  can be “flipped” by placing a positive (negative) charge on second wordline  120 B and a negative (positive) charge on first wordline  120 A and bitline  110 , CNTS  155  will become negatively (positively) charged and be attracted toward second wordline  120 B. With sufficient voltage, applied between second wordline  120 B and bitline  110 , the upper ends of CNTs  155  will release from sidewall spacer  135  of first wordline  120 A and move to and press against sidewall spacer  135  on second wordline  120 B. With the voltage differential removed (first and second wordlines  120 A and  120 B and bitline all at the same potential), CNTS  155  will continue to stick to dielectric sidewall spacer  135  on second wordline  120 B because of van der Wall attraction between molecules in CNTs  155  and molecules in dielectric sidewall spacer  135 .  
         [0044]     The state (whether CNTs are attached to dielectric sidewall spacer  135  of first wordline  120 A or attached to dielectric sidewall spacer  135  of second wordline  120 B) can be sensed as a change in capacitance in the wordlines or a spike in current flow through the bitline.  
         [0045]      FIGS. 3A through 3G  are cross-sectional views illustrating fabrication of a device according to a second embodiment of the present invention. The initial fabrication steps for the second embodiment of the present invention are that same as illustrated in  FIGS. 1A, 1B ,  1 C and  1 D and described supra.  FIG. 3A  is the same as  FIG. 1D .  
         [0046]     In  FIG. 3B , a photolithographic masking process followed by an isotropic etch is performed to remove dielectric sidewall spacer  135  from a sidewall  160 B of second wordline  120 B that is adjacent to first wordline  120 A, exposing sidewall  160 B of the first wordline  120 B. Sidewall  160 A of first wordline  120 A is still covered by sidewall spacer  135 .  
         [0047]     In  FIG. 3C , a conformal third dielectric layer  165  is formed over all exposed surfaces of first dielectric layer  115 , dielectric caps  125 , dielectric sidewall spacers  135 , and exposed sidewall  160 B of second wordline  120 B. In one example, third dielectric layer  165  comprises Si 3 N 4 . In one example third dielectric layer  165  is a high K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high K dielectric material has a relative permittivity above about 10. In one example, third dielectric layer  165  is about 1 nm to about 5 nm thick.  
         [0048]     In  FIG. 3D , a RIE process is performed to form, from third dielectric layer  165  (see  FIG. 3C ), dielectric sidewall spacers  170  on dielectric sidewall spacers  135  of first wordline  120 A, dielectric sidewall spacer  135  of second wordline  120 B, and sidewall  160 B of second wordline  120 B.  
         [0049]     In  FIG. 3E , second insulating layer  140  is formed as described supra in reference to  FIG. 1E . In  FIG. 3F , trench  145  is formed between first and second wordlines  120 A and  120 B exposing a top surface  150  of bitline  110  as described supra in reference to  FIG. 1F . In  FIG. 3G , one or more electrically conductive CNTs  155  are grown on exposed top surface  150  of bitline  110  between first and second wordlines  120 A and  120 B as described supra in reference to  FIG. 1G .  
         [0050]     Bitline  110 , wordlines  120 A and  120 B, dielectric caps  125 , dielectric sidewall spacers  135 , dielectric spacers  170 , and CNTs  155  comprise a switching or memory device (or memory cell)  230  according to the second embodiment of the present invention. Substrate  100  may be a semiconductor substrate, for example a bulk silicon or silicon-on-insulator (SOI) substrate, and include devices such as transistors, capacitors, resistors, diodes, and inductors which are wired together to form support circuits for device  230 . Operation of device  230  is described infra, in relationship to  FIG. 4 .  
         [0051]      FIG. 4  is an isometric cross-section of a device according to the second embodiment of the present invention. Change of state of device  230  is similar to that described for device  225  in reference to  FIG. 2 . However, the method of sensing the state of device  230  is different from that described for device  225  (see  FIG. 2 ). The state (whether CNTs  155  are attached to dielectric spacer  170  on dielectric sidewall spacer  135  of first wordline  120 A or attached to dielectric spacer  170  of second wordline  120 B) can be sensed as a flow of tunneling leakage current (a flow of electrons through the dielectric) from second wordline  120 B, through dielectric spacer  170 , through CNTs  155  to bitline  110  when CNTs  155  are attached to dielectric spacer  170  of second wordline  120 B by van der Waals′ forces. There is no current flow (or a much smaller current flow) from first wordline  120 A to bitline  110  when CNTs  155  are attached to dielectric spacer  170  on dielectric sidewall spacer  135  of first wordline  120 A.  
         [0052]     Tunneling leakage current is a flow of current through dielectric spacer  170  is similar to tunneling current flow in a field effect transistor (FET). Tunneling current flow in a FET is current flow from the gate, through the gate dielectric into the channel and thence to either the source or the drain. Tunneling leakage current is different from normal current flow from the source to the drain (or vice versa) in a FET when the gate of the FET is at the threshold voltage (V T ) of the device. Tunneling leakage current is different from sub-threshold leakage current flow from the source to the drain (or vice versa) in a FET when the gate of the FET is below threshold voltage (VT) of the device  
         [0053]     Therefore, a dielectric spacer  170  should to be thin enough to allow tunneling leakage current while the thickness of a dielectric sidewall spacer  135  or the combined thickness of a dielectric spacer  170  and a dielectric sidewall spacer  135  should be thick enough to preclude tunneling leakage current or at least prevent it rising above a predetermined current level.  
         [0054]      FIGS. 5A through 5K  are cross-sectional views illustrating fabrication of a device according to a third embodiment of the present invention. The initial fabrication steps for the third embodiment of the present invention are that same as illustrated in  FIGS. 1A, 1B ,  1 C and  1 D and described supra, with the exception that dielectric cap  125  of  FIGS. 1B, 1C  and  1 D is replaced with a significantly thicker dielectric cap  175  in  FIG. 5A . Otherwise  FIG. 5A  is similar to  FIG. 1D . In one example, dielectric cap  175  comprises Si 3 N 4  and is about 0.85 to about 1.5 times as thick as wordlines  120 A and  120 B as measured in a direction perpendicular to the top surface of substrate  100 .  
         [0055]     In  FIG. 5B , a second insulating layer  180  is formed. A top surface of a second insulating layer  180  is coplanar with top surfaces of dielectric cap  175 . In one example, second insulating layer  180  may be formed by deposition of a dielectric material to a depth greater than the distance between the top surface of first dielectric layer  115  and top surfaces of dielectric caps  175 , followed by a CMP. In one example second insulating layer  180  comprises SiO 2 .  
         [0056]     In  FIG. 5C , a trench  185  is formed between first and second wordlines  120 A and  120 B exposing top surface  150  of bitline  110  by removing second insulating layer  180  and first dielectric layer  115  from between the wordlines. In one example, trench  185  is formed using a photolithographic masking process followed by a RIE.  
         [0057]     In  FIG. 5D , one or more electrically conductive or semi-conductive CNTs  190  are grown on exposed top surface  150  of bitline  110  between first and second wordlines  120 A and  120 B. CNTs  190  have two ends. The first ends are permanently attached to bitline  110  but the second ends are not permanently attached to any other structure. In one example growth conditions for CNTs  190  are selected so as to grow at least one and up to a number of CNTs sufficient to cover exposed dielectric sidewall spacers  135  on one or the other of wordlines  120 A or  120 B with about a single layer of upper ends of CNTs  190 . CNTs  190  may extend (as shown) above the top surfaces of dielectric caps  175  or may be shorter and not extend above the top surfaces of dielectric caps  175 .  
         [0058]     In  FIG. 5E , the space (trench  185  of  FIG. 5C ) between wordlines  120 A and  120 B is filled with fill material  195  and a CMP performed to so a top surface of fill material  195  is coplanar with top surfaces of dielectric caps  175 . This CMP also polishes away any portions of CNTs  190  that extended above top surface of dielectric caps  175 , forming CNTs  190 A. In one example fill material  195  comprises poly-crystalline or amorphous germanium (Ge).  
         [0059]     In  FIG. 5F , upper portions of fill layer  195  are removed to form a trench  200  partially filled with fill material  195 . Upper portions of second insulating layer  180  can also be removed. Next, CNTs  190 A of  FIG. 5E  are also reduced in height, to the same height as the remaining portion of fill layer  195 , to form CNTS  190 B. These three operations may be performed as one, two or three distinct etch operations. In the case of two operations, the CNTs  190  may be etched along with the fill material  195 , the CNTs  190  may be etched along with the second insulating layer  180 , or the fill material  195  may be etched along with the second insulating layer  180 .  
         [0060]     In  FIG. 5G , a conformal conductive layer  200  is formed over all exposed surfaces of second insulating layer  180 , fill material  195 , dielectric sidewall spacers  135 , and dielectric caps  175 . In one example, conductive layer  200  comprises WSi x , TiSi 2 , TiN, TaN, doped polysilicon, or combinations thereof.  
         [0061]     In  FIG. 5H , an RIE is performed to form conductive spacers  205  on exposed sidewall surfaces of dielectric sidewall spacers  135 .  
         [0062]     In  FIG. 5I , fill material  195  (see  FIG. 5F ) is removed. In the example of fill material  195  being Ge, an etch in aqueous hydrogen peroxide (H 2 O 2 ) or other oxidizing solution may be used to remove the fill material  195 . CNTs  190 B are now free-standing.  
         [0063]     In  FIG. 5J , an isotropic etch (for example a wet etch or a high pressure plasma etch) is performed to remove a small amount of material from conductive spacers  205  (see  FIG. 5I ) generating conductive spacers  205 A and a field emission gap  235  having of dimension G between bottom edges of conductive spacers  205 A and top ends of CNTS  190 B. In one example, G is between about 4 nm and about 10 nm.  
         [0064]     In  FIG. 5K , CNTs  155  are flexible so as to be able to bend and temporally touch dielectric sidewall spacer  135  on first wordline  120 A (shown) or touch dielectric sidewall spacer  135  on second wordline  120 B. Bitline  110 , wordlines  120 A and  120 B, dielectric sidewall spacers  135 , dielectric caps  175 , conductive spacers  205 A, and CNTs  190 B comprise a switching or memory device (or memory cell)  240  according to the third embodiment of the present invention. Substrate  100  may be a semiconductor substrate, for example a bulk silicon or silicon-on-insulator (SOI) substrate, and include devices such as transistors, capacitors, resistors, diodes and inductors which are wired together to form support circuits for device  240 . Operation of device  240  is described infra, in relationship to  FIG. 6 .  
         [0065]      FIG. 6  is an isometric cross-section of a device according to the third embodiment of the present invention. Change of state of device  240  is similar to that described supra for device  225  in reference to  FIG. 2 . However, the method of sensing the state of device  230  is different from that described for device  225  (see  FIG. 2 ). The state (whether CNTs  190 B are attached to dielectric sidewall spacer  135  of first wordline  120 A or attached to dielectric sidewall spacer  135  of second wordline  120 B by van der Waals′ forces) can be sensed as a flow of field emission current from bitline  110  to conductive spacer  205 A of first wordline  120 A to conductive spacer  205 A of second wordline  120 B. To enhance the amount of field emission current, polarities may be adjusted so that conductive spacers  205 A are anodes and CNTs  190 B cathodes. Therefore it is useful to keep bitline  110  negative and opposite polarities on wordlines  120 A and  120 B, the conductive spacers associated with the positive wordline being the anode through which current will flow.  
         [0066]      FIGS. 7, 8  and  9 , are plan views illustrating memory arrays using devices according the embodiments of the present invention.  FIG. 7  illustrates a first array of memory cells  210  using devices according to the first and second embodiments of the present invention. In  FIG. 7 , a first cell comprises wordlines WL 1  and WL 2 , CNTs CNT 1  and bitline BL 1 . A second cell comprises wordlines WL 3  and WL 4 , CNTs CNT 2  and bitline BL 1 . A third cell comprises wordlines WL 1  and WL 2 , CNTs CNT 3  and bitline BL 2 . A fourth cell comprises wordlines WL 3  and WL 4 , CNTs CNT 4  and bitline BL 2 . To write the first cell of array  210 , wordline WL 1  is brought up while wordlines WL 2 , WL 3 , and WL  4  are brought down. The state of BL 1  will then determine whether CNTs CNT 1  are attracted to, and attach via van der Waals′ forces to, WL 1  or WL 2 . All cells between wordlines WL 1  and WL 2  must be written simultaneously. While writing the first cell of array  210  WL 3  and WL 4  are shorted together so that the second cell is not disturbed.  
         [0067]      FIG. 8  illustrates a second array of memory cells  215  using devices according to the first and second embodiments of the present invention. In  FIG. 8 , a first cell comprises wordlines WL 1  and WL 2 , CNTs CNT 1  and bitline BL 1 . A second cell comprises wordlines WL 2  and WL 3 , CNTs CNT 2  and bitline BL 1 . A third cell comprises wordlines WL 3  and WL 4 , CNTs CNT 3  and bitline BL 1 . A fourth cell comprises wordlines WL 4  and WL 5  (not shown), CNTs CNT 4  and bitline BL 1 . A fifth cell comprises wordlines WL 1  and WL 2 , CNTs CNT 5  and bitline BL 2 . A sixth cell comprises wordlines WL 2  and WL 3 , CNTs CNT 6  and bitline BL 2 . A seventh cell comprises wordlines WL 3  and WL 4 , CNTs CNT 7  and bitline BL 2 . An eighth cell comprises wordlines WL 4  and WL 5  (not shown), CNTs CNT 8  and bitline BL 2 .  
         [0068]     To write the second cell of array  215 , wordline WL 1  and WL 2  are brought up while wordlines WL 3 , WL 4  and WL  5  are brought down. In the array of  FIG. 8 , in order not to disturb inactive wordline bits, all wordlines to the “left” of the active cell (i. e. wordline WL 1 ) are “shorted” to the active wordline, wordline WL 2 , and all wordlines to the “right” of the active cell (i. e. wordlines WL 3  and WL 4 ) are shorted together and to wordline WL 2 . (They are held at the opposite polarity to the “left-hand” wordlines).  
         [0069]      FIG. 9  is similar to  FIG. 7 , except a third array of memory cells  220  comprises devices according to the third embodiment of the present invention. In  FIG. 9 , a first cell comprises wordlines WL 1  and WL 2 , CNTs CNT 1 , bitline BL 1 , and anodes (conductive spacers) A 1  and A 2 . A second cell comprises wordlines WL 1  and WL 2 , CNTs CNT 2  bitline BL 2 , and anodes A 1  and A 2 . A third cell comprises wordlines WL 3  and WL 4 , CNTs CNT 3 , bitline BL 1 , and anodes A 3  and A 4 . A fourth cell comprises wordlines WL 3  and WL 4 , CNTs CNT 4 , bitline BL 2 , and anodes A 3  and A 4 . To write the first cell of array  220 , wordline WL 1  is brought up, wordlines WL 2 , WL 3  and WL  4  are brought down, and the bitline potential is set appropriately, depending on which “side” of the first cell CNTs CNT 1  are to attach. To read the first cell, bitline BL 1  is biased negatively, and other bitlines and anodes A 1  and A 2  are biased positively. A tunnel current will become established only between CNTs CNT 1  and only the anode on the side of the first cell to which the CNTs CNT 1  are attached.  
         [0070]     Devices according to the third embodiment of the present invention may be arranged into arrays similar to those depicted in  FIGS. 7 and 8 . The number of cells illustrated in  FIGS. 7, 8  and  9  are to be taken as exemplary and any number of cells arranged in any number of rows and columns may be fabricated.  
         [0071]     Thus, the embodiments of the present invention provide memory and switching devices that are both non-volatile and radiation hard.  
         [0072]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.