Abstract:
An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 13/480,298, filed May 24, 2012 and entitled “Controlling On-Die Termination in a Dynamic Random Access Memory Device,” which is a continuation of U.S. patent application Ser. No. 13/180,550, filed Jul. 12, 2011 and entitled “Controlling Dynamic Selection of On-Die Termination” (issued as U.S. Pat. No. 8,188,762), which is a continuation of U.S. patent application Ser. No. 13/043,946, filed Mar. 9, 2011 and entitled “Integrated Circuit Device with Dynamically Selected On-Die Termination” (issued as U.S. Pat. No. 8,089,298), which is a continuation of U.S. patent application Ser. No. 12/861,771, filed Aug. 23, 2010 and entitled “A Memory Controller That Controls Termination in a Memory Device” (issued as U.S. Pat. No. 7,924,048), which is a continuation of U.S. patent application Ser. No. 12/507,794, filed Jul. 22, 2009 and entitled “Memory-Module Buffer with On-Die Termination” (issued as U.S. Pat. No. 7,782,082), which is a continuation of U.S. patent application Ser. No. 12/199,726, filed Aug. 27, 2008 and entitled “Controlling Memory Devices That Have On-Die Termination” (issued as U.S. Pat. No. 7,602,209), which is a continuation of U.S. patent application Ser. No. 11/422,022, filed Jun. 2, 2006 and entitled “Integrated Circuit with Graduated On-Die Termination” (issued as U.S. Pat. No. 7,486,104). Each of the foregoing applications is hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to high-speed signaling systems and components. 
     BACKGROUND 
     High-speed signal lines are commonly terminated by resistive loads selected to match the characteristic impedance of the signal lines and thereby cancel undesired reflections. Historically, the terminating elements have been implemented by discrete resistors connected to metal traces on a mother board or other printed circuit board. More recently, particularly in the domain of high-bandwidth memory systems, on-die termination structures have been provided, for example, on the integrated circuit die of a memory device or memory controller. 
       FIG. 1  illustrates a prior-art memory system  100  that employs an on-die termination scheme. The memory system  100  includes a memory controller  101  and pair of memory modules  103 A and  103 B, with each memory module coupled in parallel to a shared data path  102  (DATA), and each memory module ( 103 A,  103 B) coupled to a termination control line (TC 1 , TC 2 , respectively) to enable receipt of respective termination control signal from the memory controller. As shown in detail view  106 , each of the memory devices  105  within a given memory module  103  includes a set of data input/output (I/O) circuits  107   1 - 107   N  having a data signal transceiver  109  (i.e., output driver and signal receiver coupled to provide inbound data to and receive outbound data from I/O logic/memory core circuitry  115 ) and a switched termination structure  111  coupled in parallel to a respective data line  117   1 - 117   N  of data path  112  (Data[N:1]), where data lines  117   1 - 117   N  of data path  112  constitutes a subset of the data lines within data path  102 . The switched termination structures  111  themselves each include a respective load element (R) coupled to the corresponding data line via a switch element (X), with each of the switch elements within the memory devices of a given memory module  103  coupled to a common termination control input, TC, to receive an incoming termination control signal. By this arrangement, the memory controller  101  may assert the termination control signal supplied to either of the memory modules  103  (i.e., via termination control lines TC 1  and TC 2 ) to switchably connect the load elements within the constituent memory devices of the memory module to respective lines of the data path  102 . During write operations in which data is output onto the data path  102  to be received within a selected one of the memory modules ( 103 A or  103 B), the memory controller  101  asserts a termination control signal on the termination control line coupled to the non-selected memory module, thereby terminating the data path stub coupled to that memory module and suppressing undesired reflections. At the same time, the memory controller  101  deasserts the termination control signal supplied to the selected memory module thereby isolating the data path  102  from the on-die terminations within the memory devices  105  of that memory module to avoid undue signal attenuation. This operation of the memory controller is shown at  120  of  FIG. 1 . 
     Analysis shows that, unfortunately, the single-termination scheme of  FIG. 1  may yield sub-optimal signaling performance due, at least in part, to impedance discontinuity that tends to result at the selected memory module when the on-die terminations within that module are decoupled from the data path  102 . On the other hand, asserting the termination control signal at the selected memory module tends to unduly attenuate the incoming data signals, reducing signaling margin and increasing the likelihood of signaling errors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
         FIG. 1  illustrates a prior-art memory system that employs an on-die termination scheme; 
         FIG. 2  illustrates an embodiment of a memory system having multiple, graduated on-die terminations per high-speed signaling line; 
         FIG. 3  illustrates an exemplary approach for achieving graduated termination within a memory system without adding additional termination structures within the constituent memory devices; 
         FIG. 4  illustrates an alternative embodiment of a memory system having graduated on-die terminations; 
         FIG. 5  illustrates another embodiment of a memory system having graduated on-die terminations; and 
         FIG. 6  illustrates an exemplary state diagram of a finite state machine that may be applied within a memory device in combination with explicit or implicit termination control detection circuitry to effect a desired one of multiple, graduated terminations. 
     
    
    
     DETAILED DESCRIPTION 
     Signaling systems having improved signaling characteristics that result from multiple, graduated on-die terminations are disclosed in various embodiments. In one embodiment, each memory device within a multiple-module memory system includes multiple on-die termination structures per incoming high-speed signal line to enable any of multiple different termination loads to be switchably coupled to the signal line according to whether the memory module is a destination for incoming signals. For example, in a particular embodiment, each memory device within a two-module memory system includes two termination structures per incoming data line, with the load elements within the two termination structures being implemented by or programmed to have different impedance values, thereby enabling selection between a relatively high-load termination and a relatively low-load termination within a given memory module according to whether the memory module is the destination for high-speed signals. Thus, during a write operation, the high-load terminations, referred to herein as hard terminations, may be switchably connected to the high-speed signaling lines within the memory devices of the non-selected (e.g., non-addressed) memory module to provide transmission line load-matching, while the low-load termination, referred to herein as a soft termination, may be switchably connected to the high-speed signaling lines within the memory devices of the selected memory module to provide a desired level of energy absorption (e.g. to cancel reflections) without unduly attenuating the incoming signals. In a subsequent write operation directed to the alternate memory module, the termination selections may be quickly reversed to establish soft termination at the alternately selected memory module and hard termination at the non-selected memory module. 
     In one embodiment, multiple termination control lines are provided for each rank of memory devices on a memory module (a rank of memory devices being a set of one or more memory devices that are selected to receive or output data as a parallel group) to enable independent selection between soft and hard terminations therein. In an alternative embodiment, a snoop logic circuit is provided within each of the memory devices to determine whether the memory device is the target of a particular signaling transaction and to switchably couple either the soft terminations or the hard terminations to the data lines and/or other high-speed signal lines accordingly. In another embodiment, a buffer integrated circuit (IC) is provided to receive incoming signals within a memory module and to distribute the signals to one of multiple ranks of memory devices on the memory module. In such an embodiment, multiple, graduated on-die termination structures per high-speed signaling line may be provided on the buffer IC instead of, or in addition to, the memory devices. The high-speed signal lines coupled to the multiple, graduated on-die termination structures may include data signal lines, address signal lines, command signal lines (any or all of which may be time multiplexed and thus constitute a single set of signal lines) or any combination thereof. Further, a non-volatile memory such as a serial presence detect (SPD) memory may be programmed with information indicating whether the memory devices within a given memory module include support for graduated terminations. By this arrangement, a memory controller may read the SPD memory (or other characterizing circuit or storage) to determine whether graduated terminations are supported and, if so, issue termination control signals accordingly, thus enabling the memory controller to operate in either a legacy termination mode or graduated termination mode. Also, in a system having dual-rank memory modules, the termination values for each of the two ranks on a given memory module may be programmed to have low-load and high-load values, thus enabling selection between hard and soft terminations according to whether the module is the destination for high-speed signals. These and other embodiments are described in further detail below. 
       FIG. 2  illustrates an embodiment of a memory system  150  having multiple, graduated on-die terminations per high-speed signaling line. The memory system  150  includes a memory controller  151  coupled to two memory modules,  153 A and  153 B via a multi-drop data path  152  (i.e., the memory modules  153 A and  153 B are coupled in parallel to the data path  152 ), though additional memory modules may be coupled to the multi-drop data path  152  in alternative embodiments. Also, one or more additional signal paths (not shown) for conveying command, address and timing signals may be coupled between the memory controller  151  and memory modules  153 . 
     Each of the memory modules  153  includes multiple integrated-circuit memory devices  155  coupled to respective subsets of signal lines of the data path (i.e., coupled to respective slices of the data path  152 ), thereby forming a memory rank. In general, the memory devices within the memory rank are accessed as a group, thus enabling transfer of N×M-bit wide read and write data words, where N is the number of data bits conveyed to or from a given memory device in a given transaction (i.e., the slice width), and M is the number of memory devices within the memory rank (i.e., the number of data path slices). 
     In contrast to the memory devices of  FIG. 1 , described above, each of the memory devices  155  within memory modules  153  includes two termination control inputs to enable reception of two independent termination control signals and thus provide for switched connection of one of two graduated termination loads (i.e., termination loads having different impedance values) to each data line of the incoming data slice. In the particular embodiment shown, termination control signals are output from the memory controller  151  on termination control lines, TC 1  and TC 2 , that are coupled respectively to termination control inputs, TCa and TCb, of memory module  153 A and, in reverse order, to termination control inputs TCb and TCa of memory module  153 B. Within each of the memory modules  153 , the TCa and TCb termination control inputs are coupled to corresponding TCa and TCb inputs of the individual memory devices  155 . Referring to detail view  156 , each of the memory devices  155  within a given module  153  includes a set of data I/O circuits  157   1 - 157   N  having a data transceiver structure  159  (e.g., output driver  160   a  and signal receiver  160   b  coupled to provide inbound data to and receive outbound data from I/O logic and memory core  165 ) and a pair of switched termination structures  161   a  and  161   b  all coupled in parallel to a respective data line  167   1 - 167   N  of data path  162 , where data lines  167   1 - 167   N  of data path  162  constitute a subset of the data lines within overall data path  152 . Each of the switched termination structures  161   a ,  161   b  includes a respective load element R 1 , R 2  coupled to the corresponding data line via a corresponding switch element X 1 , X 2 . As shown, the switch elements X 1  within each of the data I/O circuits  157   1 - 157   N  is coupled in common to termination control input TCa and the switch elements X 2  are coupled in common to termination control input TCb. By this arrangement, when a termination control signal is asserted on signal line TC 1 , load elements R 1  are switchably coupled to respective lines of the data path  152  within module  153 A, and load elements R 2  are switchably coupled to the respective lines of the data path within module  153 B (i.e., by virtue of the swapped coupling of lines TC 1 /TC 2  to the TCa and TCb inputs of the two memory modules  153 A and  153 B). Thus, by programming (or implementing) load elements R 1  to have a relatively high load (i.e., a relatively low impedance) and load elements R 2  to have a relatively low load (i.e., a relatively high impedance) within each of the memory devices  155 , load elements R 1  may be switchably coupled to the data path to effect a hard termination and load elements R 2  may be switchably coupled to the data path to effect a soft termination. Accordingly, as shown by the controller operation at  170 , during a write operation directed to memory module  153 A, the memory controller  151  may assert a termination control signal on line TC 2  (and deassert the termination control signal on line TC 1 ) to switchably couple load elements R 1  to the data path  152  within memory module  153 B and to switchably couple load elements R 2  to the data path  152  within memory module  153 A, thus effecting a graduated termination within the selected and non-selected memory modules; that is, a soft termination in the selected memory module and a hard termination in the non-selected memory module (note that a third control state may be established by deasserting both termination control signals, thus decoupling termination loads from the data path  102  within both memory modules). When compared with the conventional on/off termination scheme described above in reference to  FIG. 1 , the multiple, graduated terminations generally yield larger signaling margins (i.e., more open data eyes), thus providing reduced bit error rate and additional headroom for increased signaling rates. 
     Still referring to  FIG. 2 , it should be noted that the termination structures  161   a  and  161   b  may alternatively be included within output driver  160   a , in which case the output driver  160   a  may turn on a subset of the elements used to drive the signal line (e.g., a weaker subset of drive elements the full set used when actually driving a signal) and concurrently couple pull-up and/or pull-down termination elements to the signal line at the same time to establish the termination. Also, while a single pair of termination control lines are shown in  FIG. 2  and described above (i.e., coupled to the termination control inputs TCa and TCb of memory module  153 A and in reverse order to the termination control inputs of memory module  153 B), a separate pair of termination control lines may be provided to each memory module in an alternative embodiment. 
       FIG. 3  illustrates an exemplary approach for achieving graduated termination within a memory system  200  without adding additional termination structures within the constituent memory devices. As shown, the memory system  200  includes a memory controller  201  coupled to two dual-rank memory modules,  203 A and  203 B, via a multi-drop data path  152  (though additional dual-rank memory modules  203  may be coupled to the multi-drop data path  152  in alternative embodiments and additional ranks may be provided per memory module), but with only one termination control line provided per memory rank, instead of multiple termination control lines per memory rank as in the embodiment of  FIG. 2 . Because the two ranks ( 207   1  and  207   2 ) of memory devices  205  within a given memory module  203  are coupled in parallel to the data path  152 , and the impedance of the relatively short path between them ( 208 ) is relatively small as compared to the off-module portion of the data path  152 , the termination structures (or load elements thereof) within corresponding memory devices  205  within the two different ranks  207   1  and  207   2  may be programmed to have (or implemented with) different impedance values, and thus provide for selection between graduated termination loads. More specifically, as shown at detail views  216   a  and  216   b , in each of the memory devices  205 A within memory rank  207   1  of module  203 A may be programmed to have a relatively high termination load, R 1  (i.e., low impedance) and each of the memory devices  205 B within memory rank  2  of memory module  203 A may be programmed to a relatively low termination load, R 2 , thus establishing a soft-terminated memory rank  207   1  and a hard-terminated memory rank  207   2  within the same memory module. Note that this arrangement is possible even within memory devices  205  that have a single termination structure (i.e., with switch X and termination load coupled in parallel with signal transceiver  159  within an I/O circuit  211 ) per incoming data line  214 , and that the programming of soft and hard termination loads (R 1  and R 2 ) within the devices of the different memory ranks may be achieved through register programming (e.g., storing a value within register  221  within the I/O logic and memory core  219 ), production-time configuration (e.g., fuse, anti-fuse, non-volatile storage element, etc.) or external contact strapping. The memory devices  205  within the two memory ranks  207   1  and  207   2  of memory module  203 B may be programmed in the same manner as shown in detail views  216   c  and  216   d . By this arrangement, instead of deasserting termination the control signals supplied to a memory module selected to receive write data, the termination control signal that controls switched coupling of the soft-terminated memory rank  207   2  of the selected memory module  203  may be asserted, and the termination control signal that controls switched coupling of the hard-terminated memory rank  207   1  deasserted to establish a soft termination at the selected memory module  203 , while the termination control signals supplied to the non-selected memory module are oppositely asserted and deasserted (i.e., asserting the termination control signal to engage the hard termination at memory rank  207   1  and deasserting the termination control signal to disengage (decouple) the soft termination at memory rank  207   2 ) to establish a hard termination at the non-selected memory module. Accordingly, as shown by the controller operation at  230 , in a write operation directed to memory module  203 A (memory module A), termination control signals are deasserted on termination control lines TC 1  and TC 4  (i.e., set to logic ‘0’) and asserted on termination control lines TC 2  and TC 3  (set to logic ‘1’) to switchably couple the R 2  termination loads within memory rank  207   2  of memory module  203 A to the data path  152  (and switchably decouple the R 1  termination loads within memory rank  207   1 ) to effect soft-termination for the selected memory module, and switchably coupling the R 1  termination loads within memory rank  207   1  of memory module  203 B to the data path  152  to effect hard termination for the non-selected memory module. In a write operation directed to memory module  203 B, the signal levels on the termination control lines are inverted to establish soft termination (TC 3 =0, TC 4 =1) in the selected memory module  203 B, and hard termination (TC 1 =1, TC 2 =0) in the non-selected memory module  203 A. 
     In an alternative approach to that shown in  FIG. 3 , hard termination may be achieved by asserting both the termination control signals provided to a given memory module, in effect switchably coupling the load elements within commonly coupled termination structures of the two memory ranks  207   1  and  207   2  in parallel to establish an impedance R 1 *R 2 /(R 1 +R 2 ) which, when R 1  and R 2  are programmed to (or implemented with) the same value, becomes R 1 / 2 . Thus, in such an approach, both termination control signals may be asserted simultaneously to effect hard termination within a non-selected module, while a single termination control signal is asserted to effect soft termination (R 1  or R 2  or, if programmed with the same value, then either of them) within the selected memory module. 
       FIG. 4  illustrates an alternative embodiment of a memory system  250  having graduated on-die terminations. The memory system  250  includes a memory controller  251  coupled to memory modules  253 A and  253 B via a multi-drop data path  152  and termination control lines TC 1  and TC 2  generally as described in reference to  FIG. 2 . In contrast to  FIG. 2 , however, each of the memory modules  253  includes a buffer IC  261  that operates as an intermediary between the memory controller  251  and one or more ranks of memory devices  263   1 - 263   R . More specifically, the buffer IC  261  includes controller interface to receive signals from and output signals to the memory controller  251  (i.e., coupled to the data path, termination control lines as well as other signal lines (not shown) for conveying command, address and timing signals to/from the memory controller  251 ), and multiple memory interfaces to transfer signals to and from respective memory ranks  263  (note that, in this regard, the buffer IC  261  may be implemented by multiple separate ICs, each interfacing with a respective one of the memory ranks  263  or a respective subset of the memory ranks). Each of the data paths (and/or other signal paths for conveying command, address and timing signals) coupled between a memory rank  263  and a given memory interface of the buffer IC  261  may be a point-to-point link or and may be singly or doubly terminated (i.e., termination structures coupled to one or both ends) either on die or on the memory module  253 . In one embodiment, the controller interface within the buffer IC  261  is implemented in generally the manner described for the individual memory devices within the embodiment of  FIG. 2 . That is, each buffer IC  261  includes two termination control inputs, TCa and TCb, to enable reception of two independent termination control signals and thus provide for switched connection of one of two graduated termination loads to each high-speed signal line of the data path  152 . As in the embodiment of  FIG. 2 , the termination control line connections between TC 1 /TC 2  and TCa/TCb are reversed in memory module  253 A relative to memory module  253 B so that, when a termination control signal is asserted on line TC 1 , it is received via termination control input TCa in memory module  253 A and via termination control input TCb in memory module  253 B (as discussed above, a separate pair of termination control lines may be provided for memory module instead of a shared pair of polarity-reversed control lines). Similarly, when a termination control signal is asserted on line TC 2 , it is received via termination control input TCb in memory module  253 A and via termination control input TCa in memory module  253 B. As mentioned, multiple buffer ICs may be provided to interface with respective ranks or other groupings of memory ICs within a memory module. 
     Referring to detail view  256 , the controller interface within each buffer IC  261  may be implemented by a set of data I/O circuits  157  that are constructed generally as described above in reference to detail view  156  of  FIG. 2 . That is, each I/O circuit  157  includes a data transceiver structure  159  (e.g., output driver and signal receiver) and a pair of switched termination structures  161   a  and  161   b  all coupled in parallel to a respective data line of data path  152 . Each of the switched termination structures  161   a  and  161   b  includes a respective load element (R 1 , R 2 ) coupled to the data line via a corresponding switch element (X 1 , X 2 ). The data transceivers  159  are coupled to a buffer logic circuit  265  which operates to multiplex (e.g., switchably couple) inbound signals received from the memory controller  251  via transceivers  159  to a selected one of the memory ranks  263   1 - 263   R  via a corresponding one of memory interfaces  266   1 - 266   R , and to multiplex outbound signals received from one of the memory ranks  263   1 - 263   R  to the data transceivers  159  and thus to the memory controller  251 . 
     As in the embodiment of  FIG. 2 , the switch elements X 1  within each of the I/O circuits  157  is coupled in common to termination control input TCa and the switch elements X 2  are coupled in common to termination control input TCb. By this arrangement, and by virtue of the reversed connection of the TCa/TCb termination control inputs of memory modules  253 A and  253 B to termination control lines TC 1  and TC 2 , when a termination control signal is asserted on termination control line TC 1 , load elements R 1  are switchably coupled to respective lines of the data path  152  within memory module  253 A, and load elements R 2  are switchably coupled to respective lines of the data path  152  within memory module  253 B. Similarly, when a termination control signal is asserted on termination control line TC 2 , load elements R 2  are switchably coupled to the data path  152  within memory module  253 A and load elements R 1  are switchably coupled to the data path  152  within memory module  253 B. Accordingly, by programming (or implementing) load elements R 1  to have a relatively low impedance (i.e., relatively high load) and load elements R 2  to have a relatively high impedance (i.e., relatively low load), load elements R 1  may be switchably coupled to the data path  152  to effect hard termination and load elements R 2  may be switchably coupled to the data path to effect soft termination. Thus, as shown by the controller operation at  272 , during a write operation directed to memory module  253 A (memory module A), a termination control signal may be asserted on line TC 2  to switchably couple load elements R 1  to the data path within memory module  253 B, and to switchably couple load elements R 1  to the data path within memory module  253 A, thus effecting a graduated termination within the selected and non-selected memory modules; a soft termination within the selected memory module and a hard termination within the non-selected memory module. 
       FIG. 5  illustrates another embodiment of a memory system  300  having graduated on-die terminations. The memory system  300  includes a memory controller  301  coupled to memory modules  303 A and  303 B via a multi-drop data path  152 , as in the embodiments described above, and also via a multi-drop command/address path  302  (CA) which may also be referred to herein as a request path (note that the command/address path may also be provided in the embodiments of  FIGS. 2 ,  3  and  4 , but is omitted to avoid obscuring other features of those embodiments). In contrast to the embodiments of  FIGS. 2 ,  3  and  4 , however, termination control lines TC 1 /TC 2  are omitted (or at least unused) in favor of snoop logic circuitry within the memory devices  305  of memory modules  303 A and  303 B. In one embodiment, shown in by detail view  306  of a memory device  305 , the snoop logic  315  is included with in the I/O logic and memory core circuitry  310  and is coupled via signal receiver  311  to receive all or a subset of the signals conveyed on command/address path  302 . The snoop logic  315  includes circuitry to determine the nature of a requested transaction (e.g., read or write) and to compare a module selector (or module address) conveyed on the command/address path  302  with a module identifier value established for the memory module to determine whether a given memory access transaction is directed to the host memory device  305  (i.e., the memory device in which the snoop logic  315  resides) or to another memory device  305  coupled to the same data slice, and to generate control signals C 1  and C 2 , accordingly (which control signals are supplied to respective switch elements within data I/O circuits  157  implemented as described above in reference to  FIG. 2 ). As shown by the memory operation at  320 , if the snoop logic  315  within the memory devices of memory module  303 A detects a memory write transaction directed to memory module  303 A (i.e., write-enable signal asserted (WE=1) and module selector=module identifier for module  303 A), the snoop logic will deassert control signal C 1  and assert on control signal C 2  to switchably couple load elements R 2  (i.e., programmed or implemented by a relatively low-load value to establish a soft termination within the selected module) to the respective lines of data path  152  and switchably decouple load elements R 1  from the data path  152 . During the same transaction, the snoop logic  315  within the memory devices of memory module  303 B will determine that the memory write transaction is directed to another memory module (i.e., memory module A) and, in response, assert terminal control line C 2  and deassert control signal C 1  to switchably couple load elements R 1  to the data path  152  and switchably coupled load elements R 2  from the data path  152 , thereby establishing a hard termination in the non-selected memory module  303 B. When the memory controller issues a memory write command directed to memory module  303 B, the snoop logic circuits  315  within memory modules  303 A and  303 B will detect the reversed roles of the memory modules, with the snoop logic  315  within the memory devices  305  of the non-selected memory module  303 A switchably coupling load elements R 1  to the data path  152  to effect hard terminations and the snoop logic  315  within the memory devices  305  of the selected memory module  303 B switchably coupling load elements R 2  to the data path  152  to effect soft terminations. 
     Note that a module address may be established for the memory module through configuration register programming, production-time programming or configuration (e.g., established by a fuse, anti-fuse or other non-volatile circuit element), pin strapping, etc. Also, with respect to the signals actually snooped by snoop logic  315  to determine whether the host memory device is intended to participate in a given transaction, the snoop logic may evaluate one or all bits of an incoming address field, chip-select signals and/or any other signals that bear on whether the memory device is to respond to the incoming command. 
     Still referring to  FIG. 5 , it should be noted that snoop logic circuit  315  may be combined with explicit termination control in alternative embodiments. For example, in one such embodiment, a single termination control line is provided per memory module. A termination control signal is asserted on the termination control line to indicate that a termination should be enabled, while the snoop logic indicates the gradation of the termination to be applied (e.g., soft termination or hard termination). In another alternative embodiment, a finite state machine (FSM) may be provided in place of or in combination with snoop logic circuit  315  to determine the termination value. For example, if a given memory device (or group of memory devices) or buffer IC is expecting to receive data at the time that a termination control signal is asserted (e.g., based on a command, address value or other information received within the memory device or buffer IC a predetermined amount of time prior to transmission of the data or assertion of the control signal), the FSM may signal such expectation and thus elect to apply an appropriate one of multiple termination values. If a single termination control line is provided per module, and the termination control line to a given module is activated but no data is expected, the FSM may elect to apply a different (e.g., higher-load) termination value. A memory device or buffer IC may include an internal state machine for request/command handling purposes (and other control functions), in which case only a relatively small amount of additional logic should be needed within the state machine to select between multiple graduated terminations. Note that a state machine implementation may also be combined with snoop logic instead of or in addition to providing a dedicated termination control line. For example, a FSM within each memory module may determine the termination timing and termination value to be applied within the module according to whether the snoop logic circuit indicates the memory module to be a selected or non-selected memory module for a given transaction. In all such cases, the combination of state machine, dedicated control line input and/or snoop logic circuitry may be provided within a buffer IC as generally described in reference to  FIG. 4  instead of within memory ICs. 
     In an embodiment in which a finite state machine or other control circuit is used instead of or in combination with snoop logic circuit  315  to determine the termination value to be applied during a given transaction, each individual memory devices within each memory rank may include a finite state machine that indicates the operating state of the memory device at any given time, including whether a write or read operation is currently being performed within the memory device. Accordingly, each memory device may respond to assertion of a termination control signal on a shared or dedicated termination control line (i.e., termination control line coupled in common to multiple memory ranks or a dedicated termination control line per memory rank) by effecting hard termination, soft termination or no-termination according to the present device operating state. Alternatively, each memory device may include snoop logic circuitry (e.g., generally as described in reference to  FIG. 5 ) in addition to the finite state machine and may respond to detection of a transaction indicating need for termination control (i.e., the snoop logic, in effect, substituting for dedicated termination control lines) by effecting hard termination, soft termination or no-termination according to the present operating state.  FIG. 6  illustrates an exemplary state diagram  350  of a finite state machine that may be applied within a memory device in combination with explicit or implicit termination control detection circuitry (i.e., circuitry coupled to a shared or dedicated termination control line, or snoop logic circuitry) to effect a desired one of multiple, graduated terminations. As shown, the memory devices of a given rank (the state machines of which may generally be operated in lock step) may initially be in an idle operating state  351  in which no rows of the constituent memory banks are activated. Although not specifically shown, the memory devices may transition between the idle state (or any of the other states shown in  FIG. 6 ) and various low power states, initialization states, calibration states, configuration states (i.e., for device configuration operations, including setting of programmable registers), refresh states, etc. that are not specifically shown in  FIG. 6 . Because no read or write operation is occurring within the memory devices while in the idle state, detection of a termination demand (e.g., detection assertion of a dedicated or shared termination control signal or detection of information on a control and/or address path that indicates a memory read or write transaction) may be inferred to be directed to another memory rank, so that the idle-state memory devices will effect a hard termination (“Hard T”). When an activate command is received within the idle memory rank (i.e., memory rank in which the constituent memory devices are in idle state  351 ), the constituent memory devices perform respective row activations at the specified row and bank address (and may assume one or more intermediate operating states) and thus transition to active state  353 . During the transition to the active state and while in the active state, termination demands may still be inferred to be directed to other memory ranks (i.e., because no read or write operations are occurring within the subject memory rank) so that hard termination is applied as shown. When a write command is received within an activated rank, the constituent memory devices transition to a write state  355  in which write data is delivered to the write-state memory rank and a soft termination (“Soft T”) is applied to improve the signaling characteristics over the data path as described above. Note that other memory ranks may apply hard termination during transfer of the write data in accordance with their operating states. After the write operation is completed (or multiple successive write operations completed), the memory devices of the memory rank may transition to a precharge state (“Prchg”)  359  (e.g., in an auto-precharge mode) or back to the active state  353 . In the precharge state  359 , the memory devices of the memory rank perform operations to close the open bank and precharge internal signal lines in preparation for a subsequent activation operation. Accordingly, termination demands detected while in the precharge state  359  may be inferred to be directed to other memory ranks so that hard termination is applied as shown. Referring again to active state  353 , if a memory read command is received, the memory devices of the memory rank will transition to a read state  357  in which read data is output from the memory devices to a memory controller or other device. Accordingly, during the read state, the memory devices may decouple all termination elements from the data lines on which read data is being driven to avoid undue signal attenuation. As in the write state  355 , other memory ranks may apply hard termination during transfer of the read data in accordance with their operating states. 
     It should be noted that while embodiments and approaches that include or support graduated signal terminations have been described primarily in the context of memory systems, such embodiments and approaches may readily be applied in any signaling system or components thereof in which dynamically-selected, graduated terminations may be beneficial. Also, with respect to memory systems, the nature of the core memory storage elements may vary according to application needs and may include, for example and without limitation, dynamic random access memory (dynamic RAM or DRAM) storage elements, static random access memory (SRAM) storage elements, non-volatile storage elements such as floating-gate transistors within an electrically erasable programmable read only memory (EEPROM or Flash EEPROM) or the like. With regard to implementation of on-die terminations themselves, the load elements may be implemented by virtually any type of passive components (e.g., resistors), active components (e.g., transistors or diodes) or any combination thereof, and the switch elements likewise may be implemented by transistor switches or any other on-die structures that may be used to connect or disconnect a load element from a given node. Also, while the multiple on-die termination elements or circuits have generally been depicted herein as distinct termination circuits, in all such cases two or more termination circuits may be implemented by respective load elements that include shared components. For example, a first load element within a first termination circuit may be implemented by a first set of transistors that are enabled or disabled as a group to effect a first termination impedance, while a second load element within a second termination circuit may include a subset of the first set of transistors that are enabled or disabled as a group to effect a different termination impedance. 
     Various aspects of embodiments disclosed herein are set forth, for example and without limitation, in the following numbered clauses: 
     1. A memory module comprising: 
     a plurality of data inputs to couple to signal lines of an external data path; first and second termination control inputs to receive first and second termination control signals, respectively; 
     a buffer integrated circuit (IC) having a first interface coupled to the plurality of data inputs and to the first and second control inputs and having a first memory interface that includes a plurality input/output (I/O) nodes; and 
     a first plurality of memory ICs, each memory IC coupled to a respective subset of the plurality of I/O nodes. 
     2. The memory module of clause 1 wherein the buffer IC comprises a plurality of termination circuits coupled respectively to the subset of the plurality of data inputs, each termination circuit including a first load element switchably coupled to a corresponding one of the data inputs and a second load element switchably coupled to the corresponding one of the data inputs.
 
3. The memory module of clause 2 wherein each of the plurality of termination circuits includes a first switch element to switchably couple the first load element to or switchably decouple the first load element from the corresponding one of the data inputs according to the state of a signal received via the first termination control input, and a second switch element to switchably couple the second load element to or switchably decouple the second load from the corresponding one of the data inputs according to the state of a signal received via the second termination control input.
 
4. The memory module of clause 1 wherein each memory IC of the first plurality of memory ICs comprises an array of dynamic random access memory (DRAM) storage elements.
 
5. The memory module of clause 1 wherein the buffer IC comprises a second memory interface, and wherein the memory module comprises a second plurality of memory ICs coupled to the second memory interface.
 
     It should also be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.). 
     When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process. 
     In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which logical elements may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘  &lt;signal name&gt; ’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement. 
     While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.