Abstract:
A fast voltage differential signaling (LVDS) transceiver ( 50 ) having high repeater speeds up to 1.36 GBps, and also meeting the TIA/EIA-644 standard short-to-ground requirements. A mixed voltage-current mode differential driver has a respective control signal (A 3 ) driving each of the drive transistors (Q 3 ). The control signal (A 3 ) is controlled by a transistor (M 1 ) being a function of current through the respective drive transistor (Q 3 ). A current mirror (Q 4 , Q 5 , Q 6 ) is used to mirror current conducting through a transistor (Q 4 ) in parallel with the drive transistor (Q 3 ), which mirror current is compared against a current reference (Iref).

Description:
FIELD OF THE INVENTION 
     The present invention is generally related to differential driver circuits, and more particularly to fast LVDS drivers including those having stringent short-to-ground requirements. 
     BACKGROUND OF THE INVENTION 
     The next generation low voltage differential signaling (LVDS) transceiver parts being developed are the high speed LVDS repeater type, such as PECL/ECL to LVDS converter type. These transceivers are configured to receive a differential input signal and drive a TIA/EIA-644 compliant LVDS signal. There are several high speed LVDS repeater parts currently on the market, but none which is fully TIA/EIA-644 compliant. The chief technical problem with a high speed repeater (up to 1.36 GBps) is to reduce the rise/fall times into the range in which the maximum speed requirement can be adequately met. Existing TIA/EIA-644 compliant drivers are typically current mode differential drivers which are limited by their architecture to around 600 MBps. Existing Gigibit speed repeaters are generally not TIA/EIA-644 compliant. 
     Moreover, the high speed repeaters currently on the market do not conform to the short-to-ground requirements called out in the TLA/EIA-644 specification, and therefore are not truly LVDS compatible. 
     There is desired a Gigibit fast LVDS driver which limits output current for shorts-to-ground. 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantage as a Gigabit fast LVDS transceiver ( 50 ) which also limits output current for shorts to ground. The circuit acts to both detect and limit the current in the voltage reference portion of the output. A methodology is used to detect and limit the current which provides a significant improvement in performance over the prior art. The fast LVDS transceiver is particularly adapted to be fully TIA/EIA-644 compliant. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of an Existing Current Mode LVDS Driver; 
     FIG. 2 is a typical differential output waveform for the existing LVDS Driver of FIG. 1; 
     FIG. 3 is a schematic of an existing Fast LVDS Driver Topology; 
     FIG. 4 is a typical differential output waveform for the fast LVDS Driver of FIG. 3; 
     FIG. 5 is a graph of a simulated short circuit current condition for the circuit of FIG. 3; 
     FIG. 6 is a schematic of a Fast LVDS Current Control Circuit according to the present invention; and 
     FIG. 7 is a simulated short circuit current for the improved fast LVDS driver of FIG. 6 compared to that of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     TIA/EIA-644 LVDS drive levels are defined as a differential voltage signal with a nominal magnitude of 350 mV and 1.2V common mode offset across a differential resistive load of 100 ohms. The circuit  10  of FIG. 1 achieves differential levels across the load resistance R L  by switching the source currents of I 1  and I 2  through the MOS switches M 1 -M 4 . The in 1  and in 2  differential signals are data input to the driver  10 , and are driven inverted from each other. The MOS switches M 1 -M 4  are operated like an H bridge, steering the I 1 /I 2  current through load RL in the positive direction on one phase of the data, and in the negative direction on the other data phase. 
     A common mode control system is provided by the two (2) 40 kOhm resistors R 1  and R 2  and the differential opamp A 1 . The common mode is detected internally at the junction C of the 40 kOhm resistors, and is fed to the negative (inverting) input of the opamp A 1 . The opamp output is used to control the magnitude of the I 1  and I 2  current sources differentially, which controls the common mode of the output based on the reference voltage Vref, which is generally the bandgap, voltage (approximately 1.2 v). 
     This circuit  10  is fully compliant to the TLA/EIA-644 specifications, including short-to-ground current. However, short-to-ground current in this design is limited by the fact that the output current to Vcc and to Ground is current limited by source currents I 1  and I 2 . The rise and fall times of the circuit  10  illustrated in FIG. 1 is limited to about 400 pS in current BiCmos technologies. BiCmos or bipolar processes are used for LVDS parts since the high speed bipolar devices are needed for the receiver inputs. 
     A typical differential output waveform  20  for this circuit  10  is shown in FIG. 1, showing a rise time of about 400 pS. 
     The circuit  30  in FIG. 3 depicts one current topology used for Fast LVDS drivers. While the circuit  10  of FIG. 1 is a fully current mode driver, the circuit  30  of FIG. 3 is a mixed voltage and current mode driver. The bipolar transistors Q 1  and Q 2  are used to switch between clock phases, and are driven by a low signal voltage pre-drive stage which insures that they do not saturate. The output levels are set by the emitter follower transistors Q 3  and Q 4 , and the current source Iref. Current source Iref provides the current reference, and voltage Vref provides a voltage reference for the common mode. 
     The common mode control used in circuit  30  of FIG. 3 is similar to that used in the circuit  10  of FIG.  1 . Common mode feedback from the junction C of the two 40 kOhm resistors R 1  and R 2  is fed back to the inverting side of the opamp A 2 , and controls the base voltage at transistors Q 3  and Q 4 . Current source Ifref is set to the current required through the load R L  plus whatever current is required to bias the inactive side of the circuit  30 . 
     For example, when input in 1  is high and input in 2  is low, very little current flows in transistor Q 2 . Transistor Q 4  provides current to the load resistor R L , and current Iref is sized to provide enough current to pull the emitter of transistor Q 3  down to the level needed to achieve the proper voltage at the collector of transistor Q 1 . Transistor Q 1 , therefore, sinks current equal to the current in the load resistor RL plus the current from transistor Q 3 . Since the transistor Q 1  side pulls down farther than the transistor Q 2  side, the emitter voltage of transistor Q 3  is lower than the emitter voltage of transistor Q 4 . This means that transistor Q 3  actually provides more current than transistor Q 4 , since the collector current is exponentially related to the base emitter voltage. The base inputs of Q 1 /Q 2  must be driven at appropriate levels to prevent saturation, so the predrive circuit for the circuit  30  of FIG. 3 is more complex than the predrive for circuit  10  of FIG.  1 . 
     The advantage of the fast LVDS circuit  30  is that since much faster bipolar transistors are used to provide switching, the circuit can achieve rise/fall times of less than 200 pS, providing a significant increase in performance over the MOS switched LVDS driver  10 . Since transistors Q 3  and Q 4  act as voltage followers, the circuit  30  of FIG. 3 is not strictly a current mode driver, and is not current limited to the positive supply. 
     FIG. 4 illustrates a typical differential output waveform  40  (compare with FIG. 2) for the fast LVDS driver of FIG. 3, showing a rise time of about 180 pS. 
     The problem with the circuit  30  of FIG. 3 is that a short-to-ground on either bus pin undesirably causes excessive output current. The TIA/EIA-644 specification calls for a maximum short-to-ground current of 24 mA. When either bus pin is shorted to ground, the common mode control circuit tries to maintain the reference voltage at the common mode point C. Since the base voltages of the control transistors Q 3 /Q 4  are held constant and the emitter voltage is reduced, the base-emitter voltage is increased, which causes an exponential increase in the current provided by the control device on the shorted side according to the collector current relationship: 
     
       
         
           Ic=Is·A·e Vbe/V 
           T 
         
       
     
     This problem presents itself as an excessive short to ground current for the bus pins. Short to ground current can be as high as 50 mA in typical applications. The waveform  50  of FIG. 5 shows simulated results of a short to ground test for the circuit  30  of FIG.  3 . The x axis is the voltage which the output is shorted to, and the y axis is the current into that short. As the voltage approaches zero, the short circuit current increases to about 40 mA. 
     A circuit is therefore needed to limit the current in fast LVDS drivers to prevent short to ground violations of the TIA/EIA-644 standard. 
     The mixed voltage-current mode differential driver circuit  60  of FIG. 6 achieves technical advantages by limiting short circuit current that meets the TLA/EIA-644 requirement. For the purposes of clarity, only one side of the control circuit is shown being associated with transistors Q 1  and Q 3 , with it being understood an identical control circuit is provided for the otherside including transistor Q 2 . The basic circuit  60  of FIG. 6 is similar to circuit  30  of FIG. 3, with transistor Q 3  being the voltage control device, transistors Q 1  and Q 2  being the switching transistors receiving a differential signal input, and resistors R 3 /R 4  and the opamp A 3  comprising the common mode feedback circuit. 
     The basic operation of the current limiting circuit  60  is to detect the current in transistor Q 3 , compare it against a reference current, and use the M 1  MOS transistor to limit the base drive to transistor Q 3 . To accomplish this, transistor Q 4  is connected in parallel with transistor Q 3  to detect the transistor Q 3  current. Advantageously, since the base-emitter voltages of transistor Q 3  and Q 4  are the same, the collector current of transistor Q 4  will be approximately equal to the collector current in transistor Q 3 , but times the known ratio of the emitter areas of the 2 transistors, thus providing a scaling factor. Advantageously, transistor Q 4  can be made a fraction of the physical size of transistor Q 3 , so that the scaled mirrored current is not exceedingly high. Transistor Q 5  is a PNP device that mirrors the detected current from transistor Q 4  to transistor Q 6 , and the MOS device M 2  is used to provide a reference current to compare with the mirror current through transistor Q 6 . 
     When the mirrored current in transistor Q 6  is less than the known reference current in transistor M 2 , the gate control of transistor M 1  is responsively pulled down, and base current flows freely from the feedback opamp A 3  to drive transistor Q 3 . 
     When the mirror current in transistor Q 6  approaches the reference current in transistor M 2 , the gate voltage of control transistor M 1  responsively begins to pull up, which responsively starts to limit the collector current in transistor Q 3 . Since the collector current is also responsively limited in sensing transistor Q 4 , and this sensing current is mirrored to mirror transistor Q 6 , the feedback circuit advantageously provides a “soft” cutoff for the current. 
     In other words, as the current in drive or reference transistor Q 3  approaches the predetermined limit set by the reference current Iref, the collector current in transistor Q 3  is advantageously limited gradually, rather than cutting off all at once. The resistor R 1  in the mirror circuit provides an adjustment to the current limit by degrading the performance of transistor Q 5 . For a given current in transistors Q 3  and Q 4 , a greater resistance R 1  provides a greater voltage drop from the positive supply rail to the base node of Q 5 /Q 6 . Since the base voltage is reduced, the current in transistor Q 6  is increased, providing a higher voltage at the gate of control transistor M 1 . Since this higher voltage tends to turn M 1  off, the net advantageous effect is a reduction in the collector current which the circuit is limited to. Advantageously, in this case, it is appreciated that the short circuit current has been reduced to 20 mA, which meets the TIA/EIA-644 requirement of no more than 24 mA. 
     FIG. 7 shows the simulated short circuit current at  70  for the circuit  60  of FIG. 6, where the x axis is the voltage which the output is shorted to, and the y axis is the current into that short. 
     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.