Abstract:
An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.

Description:
TECHNICAL FIELD 
     Embodiments of the invention relate to input/output architectures and interfaces. More particularly, embodiments of the invention relate to high-bandwidth on-package input/output architectures and interfaces. 
     BACKGROUND 
     High bandwidth interconnections between chips using conventional input/output (I/O) interfaces require significant power and chip area. Thus, in applications requiring significantly reduced power consumption and/or smaller chip area, these conventional interfaces are not desirable. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. 
         FIG. 1  is a block diagram of one embodiment of a multichip package (MCP) having on-package input/output (OPIO) interfaces between at least two chips. 
         FIG. 2 a    is a circuit diagram of a first embodiment of a feedback inverter termination (FIT) scheme. 
         FIG. 2 b    is a circuit diagram of a second embodiment of a feedback inverter termination (FIT) scheme. 
         FIG. 2 c    is a circuit diagram of a third embodiment of a feedback inverter termination (FIT) scheme. 
         FIG. 3  provides an example resistance characteristic of a FIT scheme. 
         FIG. 4  is a block diagram of one embodiment of a system that may utilize the OPIO interface between multiple system components. 
         FIG. 5  is an impedance graph of one embodiment of a FIT. 
         FIG. 6  is a block diagram of one embodiment of an electronic system. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. 
     Described herein is an On-Package I/O (OPIO) interface that solves the problems of conventional I/O interfaces by providing very high bandwidth I/O between chips in a Multi Chip Package (MCP) with very low power, area and latency. OPIO may be useful, for example, to interconnect a processor to memory (eDRAM/DRAM), another processor, a chip set, a graphics processor, or any other chip in a MCP with an order of magnitude lower energy per bit and area per bandwidth compared to conventional I/O. 
     Various embodiments of the interfaces described herein include one or more of the following components: (1) a single-ended, high-speed I/O interface (e.g., CMOS interface) between IC chips in a MCP with a relatively small die-to-die gap; (2) an impedance matched transmitter (e.g., CMOS transmitter) with no receiver termination or very weak termination, and no equalization; (3) a forwarded clock signal for a cluster of signals with length-matched routing to minimize or eliminate per pin de-skew; and/or (4) reduced electrostatic discharge (ESD) protection (e.g., 50 V, 70 V, 95 V, 100 V) to provide lower pad capacitances and higher data rates. 
     Close chip assembly in MCP enables very short length matched I/O traces, which in turn enables OPIO architectures described herein to run at high bandwidth using simplified single-ended I/O and clocking circuits to reduce power, area and latency. In one embodiment, high-speed, single-ended I/O with minimum bump pitch reduces bump limited silicon area for required bandwidth. 
     In one embodiment, use of a CMOS transmitter and receiver with no or weak receiver termination and no equalization can reduce I/O power. In another embodiment, where distance between chips is longer, optional weak to fully matched receiver termination is enabled to achieve high data rate at the expense of I/O power. Simplified clocking with forwarded clock per cluster of signals and no per pin de-skew can be achieved due to careful length matched routing reduces clock power. Thus, the OPIO architectures described herein provide high bandwidth between chips at very low power, area and latency. MCP with OPIO provides product, process and die area flexibility without significant power and area overhead. The OPIO architectures described herein can also be extended to close discrete packages with full ESD protection for small form factor mobile applications at lower data rates. Multi-level (e.g., M-PAM) signaling can be used at higher data rates to keep the clock frequency down. 
       FIG. 1  is a block diagram of one embodiment of a multichip package (MCP) having on-package input/output (OPIO) interfaces between at least two chips. The example of  FIG. 1  illustrates two chips with interfaces; however, any number of chips within a package can be interconnected using the techniques described herein. 
     Package  100  may be any type of package that may contain multiple integrated circuit chips. In the example of  FIG. 1 , package  100  contains chip  120  and chip  140 . These chips may be, for example, processors, memory chips, graphics processors, etc. 
     In one embodiment, chip  120  includes OPIO transmitters  125  and OPIO receivers  130 . Similarly, chip  140  includes OPIO transmitters  145  and OPIO receivers  150 . Transmitters  125  are coupled with receivers  150  and transmitters  145  are coupled with receivers  130 . 
     In one embodiment, gap  175  between chip  120  and chip  140  is relatively small. In one embodiment, gap  175  is less than 20 mm. In one embodiment, gap  175  is less than 10 mm. In one embodiment, gap  175  is approximately 1.5 mm. In other embodiments, gap  175  may be less than 1.5 mm. In general, the smaller gap  175 , the greater the bandwidth that may be provided between chips. 
     In one embodiment, the interfaces between transmitter  125  and receiver  150 , and between transmitter  145  and receiver  130  are single-ended, relatively high-speed interfaces. In one embodiment, the interfaces are CMOS interfaces between chip  120  and chip  140 . In one embodiment, transmitters  125  and  145  are impedance matched CMOS transmitters and no termination or equalization is provided. In one embodiment, transmitters  125  and  145  are impedance matched CMOS transmitters and very weak termination and no equalization is provided. 
     In one embodiment, a forwarded clock signal is transmitted for a cluster of signals. In one embodiment, length-matched routing is provided between the transmitters and the receivers. In one embodiment, minimal electrostatic discharge (ESD) protection (as little as 70 Volts) is provided for the interfaces between chips  120  and  140 . 
     In one embodiment, use of a CMOS transmitter and receiver with no or weak receiver termination and no equalization can reduce I/O power. Simplified clocking with forwarded clock per cluster of signals and no per pin de-skew can be achieved due to careful length matched routing reduces clock power. Thus, the architectures described herein provide high bandwidth between chips at very low power, area and latency. 
     The architectures described herein can also be extended to close discrete packages with full ESD protection for small form factor mobile applications at lower data rates. Multi-level (e.g., M-PAM) signaling can be used at higher data rates to keep the clock frequency down. 
     Under certain conditions, the interface of  FIG. 1  may benefit from termination. However, conventional center-tap termination (CCTs) implemented using passive resistors consume static power and degrade I/O power efficiency. CCTs also typically consume significant die area and increase the  110  pad capacitance. Described herein is a non-linear termination approach that may significantly reduce the power/area/pad capacitance cost while preserving the benefits of a linear CCT. 
       FIG. 2 a    is a circuit diagram of a first embodiment of a feedback inverter termination (FIT) scheme. The FIT of  FIG. 2 a    has a non-linear current-voltage (I-V) characteristic to provide a voltage-dependent resistance that may be used for termination purposes. 
     Pad  210  provides an electrical interface with a remote portion of for example, an interface (not illustrated in  FIG. 2 ). Pad  210  may be coupled with FIT, which includes inverter  220  (e.g., a CMOS inverter) and resistive element  230  coupled to provide feedback to inverter  220 . 
       FIG. 2 b    is a circuit diagram of a second embodiment of a feedback inverter termination (FIT) scheme. The FIT of  FIG. 2 b    has a non-linear current-voltage (I-V) characteristic to provide a voltage-dependent resistance that may be used for termination purposes. 
     Pad  240  provides an electrical interface with a remote portion of, for example, an interface (not illustrated in  FIG. 2 b   ). Pad  240  may be coupled with FIT, which includes inverter  250  (e.g., a CMOS inverter) and resistor  245  with inverter  250  coupled to provide feedback to from the output of inverter  250  to the input of inverter  250 . 
       FIG. 2 c    is a circuit diagram of a first embodiment of a feedback inverter termination (FIT) scheme. The FIT of  FIG. 2 c    has a non-linear current-voltage (I-V) characteristic to provide a voltage-dependent resistance that may be used for termination purposes. 
     Pad  260  provides an electrical interface with a remote portion of, for example, an interface (not illustrated in  FIG. 2 c   ). Pad  260  may be coupled with FIT, which includes resistor  270  coupled with and adjustable inverter  280  that may provide varying impedances. 
       FIG. 3  provides an example resistance characteristic of a FIT scheme. The large signal resistance is at a maximum at approximately Vcc/2 and decreases as the voltage approaches the supply rail values. This type of variation may be advantageous in source-series terminated (SST) links, which may be used, for example, in the interface of  FIG. 1 . 
     Line  300  provides a linear I-V characteristic, for reference purposes. Line  310  represents a non-linear I-V characteristic, such as may be provided by the FIT scheme described herein. Boxes  350  and  360  indicate the smaller resistance values corresponding to ONcc. 
     When an incident wave arrives at the receiver, the value is approximately Vcc/2 due to voltage division between the driver termination and the channel characteristic impedance. At this value, the receiver large signal termination resistance is at a maximum, maximizing the reflection and speeding the transition to the full supply rail value. Once the signal has settled close to 0/Vcc, the small signal resistance is smaller, which mitigates further reflections and reduces undershoot/overshoot. 
     Thus, the termination scheme described herein takes advantage of the inherently non-linear I-V characteristics of MOS devices to achieve the benefits of receiver CCT to reduce the termination power/area, while maintaining the signal integrity benefits provided by conventional CCT. Thus, the scheme described herein may be used to reduce the termination power in I/O links that may use CCT. It is particularly well suited to the interface of  FIG. 1  and other SST I/O interfaces that require only weak termination to improve signal integrity and reduce overshoot/undershoot. FIT may also significantly reduce the area and pad capacitance impact of CCT because it can be implemented using only active devices without relying on area-intensive passive devices. 
     Mobile, small form factor devices (e.g., thin laptops, tablets, smart phones) generally allocate limited power to chips due to thermal and battery life constraints. Conventional interfaces require significant power as compared to the interfaces described herein. The interfaces may be used to couple multiple chips and/or provide multiple links with in a MCP. The individual interfaces may be of varying widths, speeds and/or protocols (e.g., memory or non-memory), while using a common physical layer architecture. 
       FIG. 4  is a block diagram of one embodiment of a system that may utilize the OPIO interface between multiple system components. Processor  400  may be coupled with one or more of memory  410 , wireless components  420 , graphics components  430  and/or platform controller hub (PCH)  440  using the OPIO interface. 
     The bus widths and/or the frequencies at which the different interfaces may be different based on the needs and/or characteristics of the devices being connects. For example, the data bus between processor  400  and graphics components  430  may be asymmetrical and/or the interface between processor  400  and memory  410  may operate at a different frequency than the interface between processor  400  and PCH  440 . 
       FIG. 5  is an impedance graph of one embodiment of a FIT. In the graph of  FIG. 5 , line  500  represents the large signal impedance of the FIT and line  510  represents the small signal impedance of the FIT. 
       FIG. 6  is a block diagram of one embodiment of an electronic system. The electronic system illustrated in  FIG. 6  is intended to represent a range of electronic systems (either wired or wireless) including, for example, a tablet device, a smartphone, a desktop computer system, a laptop computer system, a server etc. Alternative electronic systems may include more, fewer and/or different components. 
     One or more of the components illustrated in  FIG. 6  may be interconnected utilizing the OPIO architectures described herein. For example, multiple processor chips may be interconnected, or a processor and a cache memory or dynamic random access memory, etc. 
     Electronic system  600  includes bus  605  or other communication device to communicate information, and processor(s)  610  coupled to bus  605  that may process information. Electronic system  600  may include multiple processors and/or co-processors. Electronic system  600  further may include random access memory (RAM) or other dynamic storage device  620  (referred to as memory), coupled to bus  605  and may store information and instructions that may be executed by processor  610 . Memory  620  may also be used to store temporary variables or other intermediate information during execution of instructions by processor(s)  610 . 
     Electronic system  600  may also include read only memory (ROM) and/or other static storage device  630  coupled to bus  605  that may store static information and instructions for processor  610 . Data storage device  640  may be coupled to bus  605  to store information and instructions. Data storage device  640  such as a magnetic disk or optical disc and corresponding drive may be coupled to electronic system  600 . 
     Electronic system  600  may also be coupled via bus  605  to display device  650 , which can be any type of display device, to display information to a user, for example, a touch screen. Input device  660  may be any type of interface and/or device to allow a user to provide input to electronic system  600 . Input device may include hard buttons and/or soft buttons, voice or speaker input, to communicate information and command selections to processor(s)  610 . 
     Electronic system  600  may further include sensors  670  that may be used to support functionality provided by Electronic system  600 . Sensors  670  may include, for example, a gyroscope, a proximity sensor, a light sensor, etc. Any number of sensors and sensor types may be supported. 
     Electronic system  600  further may include network interface(s)  680  to provide access to a network, such as a local area network. Network interface(s)  680  may include, for example, a wireless network interface having antenna  685 , which may represent one or more antenna(e). Network interface(s)  680  may also include, for example, a wired network interface to communicate with remote devices via network cable  687 , which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable. 
     In one embodiment, network interface(s)  680  may provide access to a local area network, for example, by conforming to IEEE 802.11b and/or IEEE 802.11g and/or IEEE 802.11n standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported. IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents. IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 6: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents. Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Associated as well as previous or subsequent versions of the Bluetooth standard may also be supported. 
     In addition to, or instead of, communication via wireless LAN standards, network interface(s)  680  may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol. 
     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. 
     While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.