Abstract:
A voice-synthesizer timepiece capable of providing advance announcement before time settings and reciting time setting is required already entered, in the form of synthesized voices is disclosed. For example, in the voice-synthesizer timepiece disclosed herein, an audible message &#34;please set time in hours and minutes soon&#34; is given in advance of a time set mode and time settings are audibly recalled in such a form as &#34;X (in hours) and Y (in minutes) have already set&#34; after the setting of time.

Description:
This application is a continuation, copending application Ser. No. 096,319, filed on Nov. 21, 1979, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a voice-synthesizer timepiece capable of requesting and/or reciting time settings in the form of synthesized voices when in a time set mode. 
     A voice-synthesizer timepiece has already been proposed in U.S. Pat. No. 3,998,045, TALKING SOLID STATE TIMEPIECE, assigned to Camin Ind. However, no consideration was of audibly announcing time setting functions. 
     Accordingly, it is an object of the present invention to provide a voice-synthesizer timepiece capable of providing advance announcement before time setting is required and reciting time settings already entered, in the form of synthesized voices. For example, in a voice-synthesizer timepiece according to the present invention, an audible message &#34;please set time in hours and minutes soon&#34; is given in advance of a time set mode and time settings are audibly recalled in such a form as &#34;X(in hours) and Y(in minutes) have already been set&#34; after the setting of time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a plan view of the other appearance of a clock calculator embodying the present invention; 
     FIGS. 2(A) and 2(B) are block diagrams of a principal circuit configuration of the clock calculator of FIG. 1; 
     FIG. 3 is a flow chart for explanation of operation of the clock calculator of FIG. 1; 
     FIG. 4 is a flow chart showing word data; and FIGS. 5 through 7 are flow charts detailing operation of the clock calculator. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a plan view of the outer appearance of a clock calculator for which the present invention is applied and FIGS. 2(A) and 2(B) are block diagrams showing principal circuit configuration of the clock calculator of FIG. 1. It is obvious to those skilled in the art that the present invention is also equally applicable to any other types of timepieces such as solid state wristwatches. 
     There is illustrated a keyboard K, a keyboard encoder KE which converts signals entered via the keyboard K into corresponding codes, a program memory RU implemented with a well known read only memory, an address register RAR, an address decoder RDC, and instruction selection gates RUG. An instruction decoder IM is adapted to generate microinstructions  1 - n according to the contents of the program memory RU inputted via the instruction selection gates RUG. There are further provided a memory unit RM consisting of a random access memory, an address counter AC, an address decoder AD, an input/output control circuit MS, an adder FA incrementing the address counter AC and a reset circuit CA for resetting the counter AC. An accumulator is labeled ACC, an input gate to the accumulator ACC is labeled GA, an output buffer is labeled BS 1  and an input gate thereto is labeled GO. 
     A clock generator CG and a frequency divider DV generate time base signals for timekeeping. A seconds register TS, a minutes register TM and a hours register TH are further provided in relation with the divider DV. Although not shown in the drawings, registers storing time or calender information in other units of time such as a date register and a month register may be provided. An input gate GT is provided for the minutes register TM and the hours register TH as well as an output selection gate ST. A specific time detector JT senses if the contents of the seconds register TS and the minutes register TM reach 59 minutes and 50 seconds. 
     A memory unit VR of a read only memory storing sound quantizing data has an address counter VAC and an address decoder VAD. A reset circuit CLA resets the address counter VAC in order to inhibit the delivery of an audible output by failing to specify any of the addresses of the memory unit VR. A subtractor SB decrements one of the address of the addresses counter VAC and, after an initial address has been set up in the address counter VAC for a desired one of voice regions P, executes the operation of VAC-1→VAC automatically at a fixed sampling frequency, thus fetching the sound quantizing data in sequence from that region P. The memory unit VR is provided with an output gate G. An END code detector JE is adapted to sense an END code located at the final step of the respective regions P and provide an output for rendering the reset circuit CLA operative to reset the address counter VAC. A reset state detector JZ senses if the address counter VAC is in the reset state and is connected to the instruction selection gate RUG together with the outputs as denoted as S 2  of the END code detector JE and the specific time detector JT and so forth. 
     A code converter CC receives voice region identifying signals S 1  supplied from the output buffer BS 1  and converts initial addresses of selected ones of the voice regions P into codes compatible with the address counter VAC. A flip-flop F controls the output gate G of the memory unit VR. The code converter CC supplies a reset signal GR when the voice region identifying signal S 1  is received and supplies a set signal GS otherwise, thereby setting and resetting the flip-flop F. The output gate G is enabled with the flip-flop F in the reset state. 
     In the drawings, a digital-to-analog converter is labeled DAC, a low pass filter LPF. a speaker driver DD and a loud speaker SP. 
     Operation of the above device will be described by reference to a flow chart of FIG. 3. The step n 0  is executed to decide if any key input has been entered and selects any of the steps n 1 , n 2 , n 3 , n 4 , n 5  . . . for identifying the type of an actuated key. For example, if a digit key N is identified during the step n 5 , then the step n 6  decides if a flip-flop F S1  is in the set state and if negative the next step n 7  is reached so that the key input is treated as an input to the calculator. 
     The step n 3  senses the presence of an actuated time set key  TIME.SET and if so the step n 8  becomes operative to generate the micro-instruction  3  and set a flip-flop F S . As will be described later, the flip-flop F S1  is set. Upon the actuation of the digit key N subsequent to that of the time set key  TIME.SET  the step n 6  perceives the flip-flop F S1  in the set state, followed by the step n 9  wherein the micro-instruction  15  is developed to load the instantaneous input into the accumulator ACC. The step n 1  decides if a hours unit selection key  H O    is depressed and if affirmative the step n 10  follows wherein the microinstruction  19  is developed to transfer the contents of the accumulator ACC into the register TH. Thereafter, the step n 11  is executed to generate the micro-instruction  24  and set a flip-flop F H . The step n 2 , on the other hand, is to sense if a minutes unit selection key Mi is actuated, followed by the step n 12 , when the affirmative answer is given, wherein the micro-instruction  23  is developed to unload the accumulator ACC into the minutes register TM and the next succeeding step n 13  wherein the micro-instruction  25  is developed to set a flip-flop F M . 
     The time set mode is initiated upon the actuation of the time set key TIME.SET  and any desired time is set after a succession of the actuations of the digit keys N, the hours unit selection key  H O    and the minutes selection key  M O   . 
     When the time set key  TIME.SET  is actuated, the step n 14  is executed to generate the micro-instruction  11  and set a flip flop F L  and the step n 15  senses the flip flop F L  in the set state, followed by the steps n 16  →n 17  → for monitoring the operating states of the respective flip flops. In this case, since the flip flop F S  has been set upon the actuation of the time set key  TIME.SET , the step n 17  results in the affirmative answer as to the flip flop F S , rendering the step n 22  operative to monitor the set state of the flip-flop F S1 . If the flip-flop F S1  is not in the set state, then the step n 23  is executed to transfer a series of the word data L S  from the program memory RU to the memory unit RM. 
     As depicted in FIG. 4, the word data L S  has a chain of the word data in which m 1  generates the micro-instruction  13  to reset the address counter AC and m 2  -m 14  send a the word date of &#34;tadaima kara ji fun wo settei shimasu (its English version is &#34;please set time in hours and minutes soon&#34;) including pause codes Pa to the program memory RM. This transferring procedure is carried out as shown in a flow chart of FIG. 5. P 1  generates the micro-instruction  15  and transfers the word data (e.g., &#34;tadaima&#34; in m 2 ) from the program memory RU into the accumulator ACC. Subsequently, P 2  generates themicro-instruction  22 for transference into the memory unit RM. In order to lead the next succeeding word data (the pause code P a2  in m 3  in the illustrated example) into the next address, the micro-instruction  14  is developed to increment one the address. If the word data L S  are completely transferred into the memory unit, the step advances toward n.sub. 24 and n 25  wherein the microinstructions  4  and  7  are respectively developed to reset the flip-flop F S  and set the flip-flop F S1 . 
     Then, the step n 26  is effected to generate the micro-instruction  12 and reset the flip-flop F u , followed by the step n 27  which is a voice output routine as shown in FIG. 6. This includes O 1  for generating the micro-instruction  13  and resetting the address counter AC, O 2  for generating the micro-instruction  16  and transferring the word data from the memory unit RM into the accumulator ACC, O 3  for deciding if a signal S 2  has been developed and in other words whether the address counter VAC is reset or whether the END code detector JE senses the presence of the END code. When the signal S 2  is outputted, O 4  is reached where the micro-instruction  18  is developed to transfer the word data from the accumulator ACC into the output buffer BS 1 . This step allows audible outputs corresponding to the word data to be delivered later. While the audible outputs are delivered, the above mentioned signal S 2  is not developed and the next succeeding word data remain stored in the accumulator ACC. O 5  develops the micro-instruction  14 , increments the address counter AC and specifies the read-out position for the next succeeding word data. O 6  decides if the address counter AC reaches &#34;O&#34;. O 2  -O 5  are repeatedly executed until the overall regions of the illustrated example, the contents of the memory unit RM includes the steps up to m 14  to complete the delivery of the advance announcement &#34;please set time in hours and minutes soon&#34;. 
     Upon the delivery of the advance announcement the step n 0  is returned and ready for the subsequent actuation of any key. If the hours unit selection key H O  is actuated subsequent to the actuation of the digit key N, then the step n 18  is effected to decide if the flip-flop F H  is in the set state, through the steps n 14  and n 15 . The step n 28  is carried out to transfer word data L H  into the memory unit RU. The word data L H , as indicated in FIG. 4, include&#34;&#34;X&#34; ji wo settei shimashita, tadaimakara fun wo settei shimasu&#34; (its English version if &#34;time X in hours has been set and please set time in minutes soon&#34;). The transmission of the hours information TH, i.e. the process m 2  for L H  is carried out in the following manner as depicted in a flow chart of FIG. 7. 
     q 1  is effected to generate the micro-instruction  17  and transfer the contents of the hours counter TH or the minutes counter TM into the accumulator ACC. When the hours unit selection key H O  is actuated, the output selection circuit ST selects the hours counter TH side in response to the micro-instruction  21  and &#34;hours&#34; information as decided by the digit keys N and the hours unit selection key  H O    is sent to the accumulator ACC. q 2  generates the micro-instruction  22  and unloads the accumulator ACC into the memory unit RU. The next step q 3  develops the micro-instruction  14  and increments the address counter AC. 
     When the word data including the &#34;hours&#34; information TH are transferred into the memory unit RM in this manner, the step n 29  is reached where the flip-flop F H  is reset, followed by the steps n 26  →n 27 . The step n 27  for the delivery of an audible message &#34;time X in hours has been set and time in minutes is about to be set.&#34; 
     Since the step n 19  is effected to decide the set state of the flip-flop F M  upon the actuation of the minutes unit selection key  Mi , the step n 30  is carried out to transfer word data L M  into the memory unit RM. By way of example, FIG. 4 shows the word data L M  &#34;time TM in minutes has been set.&#34; The &#34;minutes&#34; information TM is carried out in m 2  as indicated in FIG. 7. When this occurs, the output selection circuit ST responds to the micro-instruction  20  for selection of the minutes register TM side. After the word data L M  have been loaded into the memory unit RM in this manner, the step n 31  is at work to develop the micro-instruction  27  and reset the flip-flop F M , followed by n 26  →n 27 . During the step n 27  an audible message &#34;time TM in minutes has been set&#34; is delivered to the operator. 
     When the time set key  TIME.SET  is actuated under these circumstances, the steps n 17  →n 22  are executed and the step n 32  is reached because of the flip flop F S1  in the set state. The step n 32  transfers the word data L S1  into the memory unit RM. In other words, as indicated in FIG. 14, the word data L S1  &#34;time in hours (TH) and minutes (TM) has been set&#34; are transferred and delivered during the step n 27 . The n 33  stands behind the step n 32  and develops the micro-instructions  4  and  8  and resets the flip flops F S  and F S1 , thus completing the time set mode. 
     Provided that the actuation of a time recall key TK (the tough switch type in FIG. 1) is sensed by the step n 4 , the step n 32  is effected to generate the micro-instruction useful in setting a flip flop F T . That set state is sensed by the step n 20  and the step n 33  transfers word data L T  into the memory unit RM, which word data are audibly delivered through the step n 27 . For example, a message &#34;it is now TH in hours and TM in minutes&#34; indicative of the instantaneous time when the time recall key  TK  is actuated. The step n 34  generates the micro-instruction  6  and resets the flip flop F T . 
     If any key is not actuated, the steps n 0  →n 35  →n 15  →n 10  → . . . are repeated and the specific time detector JT senses &#34;59 minutes 50 seconds&#34; each hour and makes the steps n 36  →n 14  operative. During the step n 36  the micro-instruction  1  is developed and the flip-flop F J  is set. During n 14  the flip-flop F L  is set. Accordingly, a chain of the steps n 15  →n 16  →n 37  →n 38  are practiced. The step n 37  develops the micro-instruction  2  and resets the flip-flop F J , whereas the step n 38  transfers word data L J  into the memory unit RM. As indicated in FIG. 4, the word data L J  carry a message &#34;tadaima kara TH ji rei fun wo oshirase shimasu, pu, pu, pu, puhn&#34; (its English version is &#34;this is to announce that it is now TH hours 00 minutes, peep, peep, peep, peep&#34;). The &#34;hours&#34; information TH in m 6  is transferred while the &#34;hours&#34; information from the hours register TH is incremented by one. The correct time comes when the last monotone is released. The step n 27  delivers this message. 
     The pause codes P a1 , P a2  and so forth shown in FIG. 4 are silent data and useful in appropriately dividing the messages and controlling the full length of the messages. 
     Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.