Abstract:
A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 62/365,402 filed on Jul. 22, 2016, the entirety of which is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
       [0002]    The present invention relates to a semiconductor package structure, and in particular to a fan-out package structure. 
       Description of the Related Art 
       [0003]    In order to ensure the continued miniaturization and multi-functionality of electronic products and communication devices, it is desired that semiconductor packages be small in size, support multi-pin connection, operate at high speeds, and have high functionality. Additionally, in a high frequency application, such as a radio frequency (RF) system-in-package (SiP) assembly, antennas are typically used for enabling wireless communication. 
         [0004]    In a conventional SiP structure, a discrete antenna component is individually encapsulated or mounted on a printed circuit board (PCB) or package. Moreover, semiconductor dies, components, and passive devices are arranged side-by-side. However, it is required to provide additional area for the antenna component mounted thereon. Moreover, it is required to provide a large area for arrangement of these semiconductor dies, components, and passive devices. 
         [0005]    As a result, it is difficult to reduce the footprint (i.e., plane size) of the SiP structure. Additionally, the reduction of the total height of the SiP structure is also difficult due to the configuration including the antenna component encapsulated or mounted on the package and the underlying semiconductor dies, components, and passive devices with a side-by-side arrangement. 
         [0006]    Therefore, a novel semiconductor package structure is desirable. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    Semiconductor package structures are provided. An exemplary embodiment of a semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. 
         [0008]    Another exemplary embodiment of a semiconductor package structure including an RDL structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an IMD layer, a first conductive layer disposed at a first layer-level of the IMD layer, and a second conductive layer disposed at a second layer-level below the first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. 
         [0009]    Yet another exemplary embodiment of a semiconductor package structure including an RDL structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an IMD layer, a first conductive layer disposed at a first layer-level of the IMD layer, a second conductive layer disposed at a second layer-level below the first layer-level of the IMD layer, and a third conductive layer disposed at a third layer-level below the second layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the disclosure. 
           [0013]      FIG. 2  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the disclosure. 
           [0014]      FIG. 2-1  is a plan view of an arrangement of an antenna pattern in the semiconductor package structure shown in  FIG. 2 . 
           [0015]      FIG. 3  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the disclosure. 
           [0016]      FIG. 4  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the disclosure. 
           [0017]      FIG. 4-1  is a plan view of an arrangement of an antenna pattern and a ground shielding pattern in the semiconductor package structure shown in  FIG. 4 . 
           [0018]      FIG. 5  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the disclosure. 
           [0019]      FIG. 5-1  is a plan view of an arrangement of an antenna pattern and a ground shielding pattern in the semiconductor package structure shown in  FIG. 5 . 
           [0020]      FIG. 6  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the disclosure. 
           [0021]      FIG. 6-1  is a plan view of an arrangement of an antenna pattern and a ground shielding pattern in the semiconductor package structure shown in  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by reference to the appended claims. 
         [0023]    The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention. 
         [0024]      FIG. 1  is a cross-sectional view of a semiconductor package structure  10  in accordance with some embodiments of the disclosure. In some embodiments, the semiconductor package structure  10  is a wafer-level semiconductor package structure, for example, a flip-chip semiconductor package structure. 
         [0025]    Referring to  FIG. 1 , the semiconductor package structure  10  may be a wafer-level semiconductor package structure that may be mounted on a base (not shown). In some embodiments, the semiconductor package structure  10  may be a system-on-chip (SOC) package structure. Moreover, the base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). In some embodiments, the base may include a package substrate. The semiconductor package structure  10  is mounted on the base by a bonding process. For example, the semiconductor package structure  10  includes bump structures  160  (such as conductive ball structures, conductive pillar structure, or conductive paste structures) that is mounted on and electrically coupled to the base by the bonding process. 
         [0026]    In the embodiment, the semiconductor package structure  10  includes an RDL structure  110  and the bump structures  160  electrically coupled thereto. The RDL structure  110 , which is also referred to as a fan-out structure, has a first surface  101  and a second surface  103  opposite thereto. In some embodiments, the RDL structure  110  includes one or more conductive layers disposed in an IMD layer  100 . For example, a single first conductive layer  102  is disposed at a first layer-level of the IMD layer  100 . In such cases, the IMD layer  100  may include first and second sub-dielectric layers  100   a  and  100   b  successively stacked from the first surface  101  of the RDL structure  110  toward the second surface  103  of the RDL structure  110 , such that the first conductive layer  102  is positioned between the first and second sub-dielectric layers  100   a  and  100   b . In some embodiments, the IMD layer  100  may be formed of organic materials, which include a polymer base material, non-organic materials, which include silicon nitride (SiN X ), silicon oxide (SiO X ), graphene, or the like. For example, the first and second sub-dielectric layers  100   a  and  100   b  are made of a polymer base material. 
         [0027]    Moreover, the bump structures  160  are disposed over the second surface  103  of the RDL structure  110  and electrically coupled to the RDL structure  110 . In some embodiments, pad portions of the first conductive layer  102  are exposed to openings of the second sub-dielectric layer  100   b  and connected to the corresponding bump structures  160  through the corresponding under bump metallization (UBM) layers  160   a.    
         [0028]    In the embodiment, the semiconductor package structure  10  further includes a first semiconductor die  120 , such as an SOC die. The first semiconductor die  120  is disposed over the second surface  103  of the RDL structure  110  and the first conductive layer  102  is electrically coupled to the first semiconductor die  120 . As shown in  FIG. 1 , the first semiconductor die  120  is fabricated by flip-chip technology. Bump structures  120   a  of the first semiconductor die  120  are electrically connected to the circuitry (not shown) of the first semiconductor die  120 . In some embodiments, the bump structures  120   a  of the first semiconductor die  120  are surrounded by an underfill layer  122  that is interposed between the second surface  103  of the RDL structure  110  and the first semiconductor die  120 . Moreover, the bump structures  120   a  of the first semiconductor die  120  are in contact with corresponding conductive structures  111  (e.g., conductive bumps, posts or solder pastes), so that the first semiconductor die  120  is electrically coupled to the first conductive layers  102  through conductive structures  111 . It should be noted that the number of SOC dies integrated in the semiconductor package structure  10  is not limited to that disclosed in the embodiment. 
         [0029]    In the embodiment, the semiconductor package structure  10  further includes one or more second semiconductor dies  130  and one or more electronic components  140  disposed on the second surface  103  of the RDL structure  110 . In order to simplify the diagram, only a second semiconductor die  130  and three electronic components  140  are depicted. Also, it should be noted that the number of semiconductor dies or electronic components integrated in the semiconductor package structure  10  is not limited to that disclosed in the embodiment. 
         [0030]    In some embodiments, the second semiconductor die  130  and the electronic components  140  are arranged side-by-side and electrically coupled to the RDL structure  110  through the first conductive layer  102 . In some embodiments, the second semiconductor die  130  is a radio frequency front-end component, an integrated passive device (IPD)), or a combination thereof. Alternatively, the second semiconductor die  130  may include a microcontroller (MCU), a microprocessor (MPU), a random access memory (RAM), a power management integrated circuit (PMIC), a flash memory, or a global positioning system (GPS) device, or any combination thereof. In some embodiments, the electronic component  140  is a passive device, such as a capacitor, an inductor, a resistor, or a combination thereof. 
         [0031]    In the embodiment, the semiconductor package structure  10  further includes a molding compound  150  covering the first surface  101  of the RDL structure  110 . In such a case, the second semiconductor die  130  and the electronic components  140  are disposed within the molding compound  150 . In some embodiments, the molding compound  150  may be formed of an epoxy, a resin, a moldable polymer, or the like. The molding compound  150  may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In some other embodiments, the molding compound  150  may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around the second semiconductor die  130  and the electronic components  140 , and then may be cured through a UV or thermal curing process. The molding compound  150  may be cured with a mold (not shown). 
         [0032]    The bump structures  160  are separated from the molding compound  150  through the RDL structure  110 . In other words, the bump structures  160  are free from contact with the molding compound  150 . 
         [0033]      FIG. 2  is a cross-sectional view of an exemplary semiconductor package structure  20  in accordance with some embodiments of the disclosure and  FIG. 2-1  is a plan view of an arrangement of an antenna pattern in the semiconductor package structure  20  shown in  FIG. 2 . Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to  FIG. 1  are omitted for brevity. 
         [0034]    In the embodiment, the semiconductor package structure  20  is similar to the semiconductor package structure  10  shown in  FIG. 1 , except that the first conductive layer  102  has one or more antenna patterns  102   a . The first conductive layer  102  with antenna patterns  102   a  enables wireless communication for the semiconductor package structure  20 . Additionally, in order to simplify the diagram, only a second semiconductor die  130  and an electronic component  140  are depicted. Also, it should be noted that the number of semiconductor dies or electronic components integrated in the semiconductor package structure  20  is not limited to that disclosed in the embodiment. 
         [0035]    As shown in  FIG. 2-1 , for example, the first conductive layer  102  has four antenna patterns  102   a  that are arranged in an array as seen from a top view. In such cases, the antenna patterns  102   a  of first conductive layer  102  are laterally spaced apart from the first semiconductor die  120 , the second semiconductor die  130 , and the electronic components  140  (not shown), as viewed from a top-view aspect. Moreover, each of the antenna patterns  102   a  of the first conductive layer  102  is rectangular, as viewed from a top-view aspect. 
         [0036]    However, it should be understood that those of ordinary skill in the art know that various shapes can be used for the antenna patterns  102   a  of the first conductive layer  102 . Also, it should be noted that the number of antenna patterns integrated in the semiconductor package structure  20  and the arrangement of the antenna patterns are not limited to those disclosed in the embodiment. 
         [0037]    In the embodiment, since the antenna component is integrated in the RDL structure  110 , the overall height of the semiconductor package structure  20  can be reduced. 
         [0038]    In some embodiments, the first conductive layer  102  semiconductor package structure  20  may have a ground shielding pattern (not shown) instead of the antenna patterns. In such cases, the antenna patterns may be mounted on the semiconductor package structure  20 . The ground shielding component may reduce the effect of electrical noise on the signals, and to reduce the electromagnetic radiation that can interfere with other devices. 
         [0039]      FIG. 3  is a cross-sectional view of an exemplary semiconductor package structure  30  in accordance with some embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to  FIG. 1 or 2  are omitted for brevity. 
         [0040]    In the embodiment, the semiconductor package structure  30  is similar to the semiconductor package structure  20  shown in  FIG. 2 , except the configuration of the RDL structure  110 . In the embodiment, the RDL structure  110  includes two conductive layers disposed at different layer-levels of the IMD layer  100 . For example, a first conductive layer  102  is disposed at a first layer-level of the IMD layer  100  and a second conductive layer  104  is disposed at a second layer-level below the first layer-level of the IMD layer  100 . In such a case, the IMD layer  100  may include first, second, and third sub-dielectric layers  100   a ,  100   b , and  100   c  successively stacked from the first surface  101  of the RDL structure  110  toward the second surface  103  of the RDL structure  110 , such that the first conductive layer  102  is positioned between the first and second sub-dielectric layers  100   a  and  100   b . Moreover, the second conductive layer  104  is positioned between the second and third sub-dielectric layers  100   b  and  100   c.    
         [0041]    In some embodiments, pad portions of the second conductive layer  104  are exposed to openings of the third sub-dielectric layer  100   c  and connected to the corresponding bump structures  160  through the corresponding UBM layers  160   a.    
         [0042]    In the embodiment, the antenna patterns  102   a  of the first conductive layer  102  may have a shape and an arrangement that are the same as or different than those shown in  FIG. 2-1 . It should be understood that those of ordinary skill in the art know that various shapes can be used for the antenna patterns  102   a  of the first conductive layer  102 . Also, it should be noted that the number of antenna patterns integrated in the semiconductor package structure  30  and the arrangement of the antenna patterns are not limited to those disclosed in the embodiment. 
         [0043]    In some embodiments, the first conductive layer  102  in the semiconductor package structure  30  may have a ground shielding pattern (not shown) instead of the antenna patterns. In such cases, the antenna patterns may be mounted on the semiconductor package structure  30 . 
         [0044]      FIG. 4  is a cross-sectional view of an exemplary semiconductor package structure  40  in accordance with some embodiments of the disclosure and  FIG. 4-1  is a plan view of an arrangement of an antenna pattern and a ground shielding pattern in the semiconductor package structure  40  shown in  FIG. 4 . Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to  FIG. 3  are omitted for brevity. 
         [0045]    In the embodiment, the semiconductor package structure  40  is similar to the semiconductor package structure  30  shown in  FIG. 3 , except the configuration of the RDL structure  110 . In the embodiment, the first conductive layer  102  has one or more antenna patterns  102   a  and the second conductive layer  104  has a ground shielding pattern  104   a  that is arranged underneath the antenna patterns  102   a . The second conductive layer  104  with the ground shielding pattern  104   a  may reduce electrical noise between the antenna patterns  102   a  and the first semiconductor die  120 , and reduce the electromagnetic radiation that can interfere with other devices. 
         [0046]    Moreover, in the embodiment, the RDL structure  110  includes three conductive layers disposed at different layer-levels of the IMD layer  100 . For example, a first conductive layer  102  is disposed at a first layer-level of the IMD layer  100 , a second conductive layer  104  is disposed at a second layer-level below the first layer-level of the IMD layer  100 , and a third conductive layer  106  disposed at a third layer-level below the second layer-level of the IMD layer  100 . In such a case, the IMD layer  100  may include first, second, third, and fourth sub-dielectric layers  100   a ,  100   b ,  100   c , and  100   d  successively stacked from the first surface  101  of the RDL structure  110  toward the second surface  103  of the RDL structure  110 , such that the first conductive layer  102  is positioned between the first and second sub-dielectric layers  100   a  and  100   b . Moreover, the second conductive layer  104  is positioned between the second and third sub-dielectric layers  100   b  and  100   c . Additionally, the third conductive layer  106  is positioned between the third and fourth sub-dielectric layers  100   c  and  100   d.    
         [0047]    In some embodiments, pad portions of the third conductive layer  106  are exposed to openings of the fourth sub-dielectric layer  100   d  and connected to the corresponding bump structures  160  through the corresponding UBM layers  160   a.    
         [0048]    As shown in  FIG. 4-1 , for example, the first conductive layer  102  has four antenna patterns  102   a  that are arranged in an array as seen from a top view. In such a case, the surface of the first semiconductor die  120  is entirely covered by the ground shielding pattern  104   a , as viewed from a top-view aspect. Moreover, the antenna patterns  102   a  of first conductive layer  102  are laterally spaced apart from the second semiconductor die  130  and the electronic components  140  (not shown), as viewed from a top-view aspect. Each of the antenna patterns  102   a  of the first conductive layer  102  is rectangular, as viewed from a top-view aspect. 
         [0049]    However, it should be understood that those of ordinary skill in the art know that various shapes can be used for the antenna patterns  102   a  of the first conductive layer  102 . Also, it should be noted that the number of antenna patterns integrated in the semiconductor package structure  40  and the arrangement of the antenna patterns are not limited to those disclosed in the embodiment. 
         [0050]    In the embodiment, since the antenna component is integrated in the RDL structure  110 , the overall height of the semiconductor package structure  40  can be reduced. Moreover, since the ground shielding component is integrated in the RDL structure  110 , the electrical noise between the antenna patterns  102   a  and the first semiconductor die  120  can be prevented by the ground shielding component. As a result, the first semiconductor die  120  can be arranged underneath the antenna component, as shown in  FIG. 4-1 , thereby reducing the footprint (i.e., plane size) of the semiconductor package structure  40 . 
         [0051]      FIG. 5  is a cross-sectional view of an exemplary semiconductor package structure  50  in accordance with some embodiments of the disclosure and  FIG. 5-1  is a plan view of an arrangement of an antenna pattern and a ground shielding pattern in the semiconductor package structure  50  shown in  FIG. 5 . Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to  FIG. 4 or 4-1  are omitted for brevity. 
         [0052]    In the embodiment, the semiconductor package structure  50  is similar to the semiconductor package structure  40  shown in  FIG. 4 . Unlike the semiconductor package structure  40 , the second semiconductor die  130  and electronic components  140  (as shown in  FIG. 4 ) are not disposed in the semiconductor package structure  50 . 
         [0053]    As shown in  FIG. 5-1 , in the semiconductor package structure  50 , the antenna patterns  102   a  of the first conductive layer  102  may have a shape and an arrangement that are the same as those shown in  FIG. 4-1 . Moreover, the arrangement of the ground shielding pattern  104   a  and the first semiconductor die  120  is the same as that shown in  FIG. 4-1 . However, it should be understood that those of ordinary skill in the art know that various shapes can be used for the antenna patterns  102   a  of the first conductive layer  102 . Also, it should be noted that the number of antenna patterns integrated in the semiconductor package structure  50  and the arrangement of the antenna patterns are not limited to those disclosed in the embodiment. 
         [0054]      FIG. 6  is a cross-sectional view of an exemplary semiconductor package structure  60  in accordance with some embodiments of the disclosure and  FIG. 6-1  is a plan view of an arrangement of an antenna pattern and a ground shielding pattern in the semiconductor package structure  60  shown in  FIG. 6 . Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to  FIG. 4 or 4-1  are omitted for brevity. 
         [0055]    In the embodiment, the semiconductor package structure  60  is similar to the semiconductor package structure  40  shown in  FIG. 4 . In the semiconductor package structure  60 , unlike the semiconductor package structure  40 , the second semiconductor die  130  and the electronic components  140  are disposed over the second surface  103  of the RDL structure  110 , such that the first semiconductor die  120 , the second semiconductor die  130  and the electronic components  140  are arranged side-by-side. 
         [0056]    As shown in  FIG. 6-1 , in the semiconductor package structure  60 , the antenna patterns  102   a  of the first conductive layer  102  may have a shape and an arrangement that are the same as those shown in  FIG. 4-1 . However, it should be understood that those of ordinary skill in the art know that various shapes can be used for the antenna patterns  102   a  of the first conductive layer  102 . Also, it should be noted that the number of antenna patterns integrated in the semiconductor package structure  60  and the arrangement of the antenna patterns are not limited to those disclosed in the embodiment. 
         [0057]    In the embodiment, unlike the semiconductor package structure  40 , the surfaces of the first semiconductor die  120 , the second semiconductor die  130 , and the electronic components  140  (not shown) are entirely covered by the ground shielding pattern  104   a , as viewed from a top-view aspect. 
         [0058]    In the embodiment, since the antenna component is integrated in the RDL structure  110 , the overall height of the semiconductor package structure  60  can be reduced. Moreover, since the ground shielding component is integrated in the RDL structure  110 , the electrical noise between the antenna patterns  102   a  and the first semiconductor die  120  can be prevented by the ground shielding component. As a result, the first semiconductor die  120 , the second semiconductor die  130 , and the electronic components  140  (not shown) can be arranged underneath the antenna component, as shown in  FIG. 6-1 . As a result, the footprint (i.e., plane size) of the semiconductor package structure  60  can be further reduced compared to the semiconductor package structure  40 . 
         [0059]    According to the foregoing embodiments, the semiconductor package structure is designed to fabricate an antenna component and a ground shielding component integrated into the semiconductor package(s). These components can be formed by an RDL process. Accordingly, there is no need to perform an additional process for forming the antenna component and the ground shielding component. As a result, reliability, yield, and throughput of the semiconductor package structure are increased and the manufacturing cost of the semiconductor package structure is reduced. Additionally, the integrated antenna and ground shielding components can provide design flexibility for the system integration of the semiconductor package structure and effectively reduce the package size. 
         [0060]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.