Abstract:
A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence, according to digital input. A switching network charges a capacitor according to the difference between the two selected reference voltages, then connects another capacitor to the first capacitor to generate a voltage intermediate between the two selected reference voltages by redistributing charge between the capacitors. The switching network also selects one of the selected reference voltages or the intermediate voltage as the analog output voltage. This conversion scheme saves space with little or no increase in current consumption.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital-to-analog converter useful in, for example, a circuit that drives a liquid crystal display. 
     2. Description of the Related Art 
     With the recent increase in the size of liquid crystal display devices, various needs have arisen for improved performance in their driving circuits. One need is for a gradation scale with more gradation levels, especially for the display of more vivid colors. The current state of the art is a liquid crystal display device that can reproduce over one billion different colors by using ten bits of data (1024 gradation levels) for each of the three primaries (red, green, blue). The increased number of gradation levels demands improved performance from the digital-to-analog (D/A) converters that convert digital signals received from an outside source to analog signals. D/A converters of the resistor string type are often employed. 
     The simplest resistor string D/A converters have the structure shown in  FIG. 8 , which converts two-bit digital data (bits  1 D and  2 D and their complementary values  1 DB and  2 DB), and  FIG. 9 , which converts three-bit digital data (bits  1 D– 3 D and their complementary values  1 DB– 3 DB). An output decoder comprising transistor switches selects one of the voltage levels (V 0 , V 1 , V 2 , . . . ) generated by the resistor string (R 1 , R 2 , . . . ) for output (V out ). With this circuit configuration, each time the number of bits increases by one, the number of resistors and transistors substantially doubles, doubling the circuit area. 
     Japanese Patent Application Publication No. 2000-183747 (U.S. Pat. No. 6,373,419) describes an alternative circuit configuration with fewer resistors and transistors, but the output decoder requires an averaging voltage-follower amplifier with two parallel differential input stages, an arrangement that consumes an undesirably large amount of current. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a D/A converter that has a reduced number of circuit elements, does not take up a large amount of space, and does not consume excessive current. 
     The invented D/A converter includes a voltage generator that generates a plurality of reference voltages forming a monotonic sequence of voltage levels. A first control circuit and a second control circuit select two of the reference voltages, mutually adjacent in the monotonic sequence, as a first output and a second output. A third control circuit has a plurality of capacitors and a switching network for charging at least one of the capacitors to a voltage difference between the first output and the second output, then redistributing charge among the capacitors to generate a voltage intermediate between the first and second outputs, and selectively supplying the first or second output or the intermediate voltage as the final analog output. 
     Compared with the simplest conventional type of resistor string D/A converter, the invented D/A converter takes up less space because it requires fewer circuit elements. The invented D/A converter also consumes less current than a D/A converter requiring a voltage follower amplifier with parallel input stages. To achieve further reductions in space and current consumption, the gate capacitances of metal-oxide-semiconductor transistors may be used as some or all of the capacitors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the attached drawings: 
         FIG. 1  is a circuit diagram of a D/A converter illustrating a first embodiment of the present invention; 
         FIG. 2  is a circuit diagram of the switching circuit in  FIG. 1 , 
         FIG. 3  is a circuit diagram of a D/A converter illustrating a second embodiment of the invention; 
         FIG. 4  is a circuit diagram of a D/A converter illustrating a third embodiment; 
         FIG. 5  is a circuit diagram of a D/A converter illustrating a fourth embodiment; 
         FIG. 6  is a circuit diagram of a D/A converter illustrating a fifth embodiment; 
         FIG. 7  is a circuit diagram of a D/A converter illustrating a sixth embodiment; 
         FIG. 8  is a circuit diagram of a conventional two-bit D/A converter; and 
         FIG. 9  is a circuit diagram of a conventional three-bit D/A converter. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. For convenience, the same symbols will be used to represent capacitors and their capacitance values. 
     First Embodiment 
     The first embodiment is a D/A converter that converts n-bit digital data to an analog signal. Referring to  FIG. 1 , the D/A converter  100  comprises a voltage generator  101  and three control circuits  102 ,  103 ,  104 . The illustrated circuit converts three-bit digital data comprising bits  1 D,  2 D,  3 D and their complementary values  1 DB,  2 DB,  3 DB. 
     The voltage generator  101  is a string of resistors (R 0 , R 1 , R 2 , R 3 ) connected in series, receiving a voltage V 0  from a power source (not shown) and generating successively lower voltages (V 1  to V 4 ) by resistive voltage drops. Voltages V 0  to V 4  will be referred to below as reference voltages. In general, if n is the number of bits of digital input data, the voltage generator  101  in the first embodiment has 2 n−1  resistors generating 2 n−1 +1 reference voltages. 
     The first control circuit  102  uses the upper two bits of input data ( 2 D,  3 D and their complementary values  2 DB and  3 DB) to select one of the even-numbered reference voltages (V 0 , V 2 , or V 4 ) as a first output V out1 . In general, the upper n−1 bits of input data are used to select an even-numbered one of the 2 n−1 +1 reference voltages generated by the voltage generator  101 . 
     The second control circuit  103  uses the most significant bit ( 3 D and its complementary value  3 DB) to select an odd-numbered reference voltage (V 1  or V 3 ) adjacent to the even-numbered reference voltage selected by the first control circuit  102 , and outputs it as a second output V out2 . In general, the upper n−2 bits are used to select an odd-numbered one of the 2 n−1 +1 reference voltages generated by the voltage generator  101 . 
     The first control circuit  102  and second control circuit  103  may be any types of control circuits that can select two mutually adjacent reference voltages. They are not limited to the circuit configurations shown in  FIG. 1 . 
     The first and second outputs V out1 , V out2  are supplied as first and second inputs V in1 , V in2  through a switching circuit  105  to the third control circuit  104 , which generates a third output V out3 . The third control circuit  104  comprises first and second capacitors C 11 , C 12  and five switches. The first switch S 11  is connected between the second input V in2  and third output V out3 . A pair of second switches S 12  are connected between the first input V in1  and first capacitor C 11  and between the second input V in2  and second capacitor C 12 . A pair of third switches S 13  are connected between the first capacitor C 11  and the third output V out3  and between the second capacitor C 12  and the third output V out3 . The first and second capacitors C 11 , C 12  are connected in series between a node disposed between one pair of second and third switches S 12 , S 13  and a node disposed between the other pair of second and third switches S 12 , S 13 , and have a common node connected to the second input V in2 . 
     The switches S 11 , S 12 , and S 13  are controlled by the least significant bit of the digital input data ( 1 D and its complementary value  1 DB, not shown). The first and second capacitors C 11 , C 12  have identical capacitance values. 
     Here and in the descriptions of the following embodiments, the term ‘identical’ means that the two capacitance values are the same to within a tolerance that allows for normal fabrication process variations. As the number of reference voltages increases, the voltage difference between the first and second outputs V out1  and V out2  decreases, so the error caused by process variations can be tolerated. 
     Referring to  FIG. 2 , the switching circuit  105  has first and second input terminals that receive the outputs V out1  and V out2  from the first and second control circuits  102 ,  103 ; first and second output terminals that supply the first and second input voltages V in1  and V in2  to the third control circuit  104 ; and switches S 14 , S 15  that can connect either input terminal to either output terminal. The switches S 14 , S 15  are controlled by the second least significant bit ( 2 D and its complementary value  2 DB) of the digital input signal. 
     The switches S 11 , S 12 , S 13 , S 14  and S 15  in the third control circuit  104  and switching circuit switching circuit  105  are analog switches comprising metal-oxide-semiconductor (MOS) transistors (not shown). 
     Next the operation of the first embodiment will be described. 
     The first control circuit  102  selects an even-numbered reference voltage as the first output voltage V out1 , according to digital input data  2 D,  2 DB,  3 D, and  3 DB. The second control circuit  103  selects an odd-numbered reference voltage as the second output voltage V out2 , according to digital input data  3 D and  3 DB. The first control circuit  102  and second control circuit  103  are configured so as to assure that the selected first and second outputs V out1 , V out2  are mutually adjacent in the series of reference voltages generated by the voltage generator  101 . 
     When the least significant bit of the input data is zero ( 1 D=0), the first switch S 11  in the third control circuit  104  is turned on, the second and third switches S 12 , S 13  are turned off, and the second input V in2  is output as the third output V out3 . When the least significant bit of the input data is one ( 1 D=1), the first and third switches S 11 , S 13  are turned off and the second switch S 12  is turned on, connecting the first capacitor C 11  to the first input V in1  so that it is charged to (V in1 −V in2 ) while the second capacitor C 12  is discharged to zero volts. After a time sufficient for the capacitors to charge and discharge, the second switches S 12  are turned off and the third switches S 13  are turned on. Due to the equal capacitance of the two capacitors, half of the charge stored in the first capacitor C 11  is redistributed to the second capacitor C 12 . Both capacitors now store a charge equal to (V in1 −V in2 )/2, and a voltage halfway between the first and second inputs V in1 , V in2  is output through the third switches S 13  as the third output V out3 . 
     When the middle bit of the input data is zero ( 2 D=0), switches S 14  are turned on and switches S 15  are turned off in the switching circuit  105 , connecting the first output V out1  to the first input V in1  and the second output V out2  to the second input V in2 . When the middle bit of the input data is one ( 2 D=1), switches S 14  are turned off and switches S 15  are turned on, connecting the first output V out1  to the second input V in2  and the second output V out2  to the first input V in1 . This switchover causes the third output V out3  to increase monotonically from V 4  to (V 0 +V 1 )/2 as the digital input increases from ‘000’ to ‘111’, as shown in Table 1. 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Input 
                 V out1   
                 V out2   
                 V out3   
               
               
                   
                   
               
             
             
               
                   
                 111 
                 V 0   
                 V 1   
                 (V 0  + V 1 )/2 
               
               
                   
                 110 
                 V 0   
                 V 1   
                 V 1   
               
               
                   
                 101 
                 V 2   
                 V 1   
                 (V 1  + V 2 )/2 
               
               
                   
                 100 
                 V 2   
                 V 1   
                 V 2   
               
               
                   
                 011 
                 V 2   
                 V 3   
                 (V 2  + V 3 )/2 
               
               
                   
                 010 
                 V 2   
                 V 3   
                 V 3   
               
               
                   
                 001 
                 V 4   
                 V 3   
                 (V 3  + V 4 )/2 
               
               
                   
                 000 
                 V 4   
                 V 3   
                 V 4   
               
               
                   
                   
               
             
          
         
       
     
     As Table 1 shows, the first embodiment produces the same number of output voltage gradations as the conventional D/A converter shown in  FIG. 9 , using a resistor string with only about half as many resistors. More precisely, the first embodiment requires a string of 2 n−1  resistors, as noted above, whereas the conventional circuits shown in  FIGS. 8 and 9  require a string of 2 n −1 resistors. 
     When the first embodiment is adapted to convert n-bit input data (n&gt;3), the first and second control circuits  102 ,  103  require additional transistors, but the switching circuit  105  and third control circuit  104  do not. For large numbers of bits (n=10, for example), the first embodiment requires far fewer circuit elements in all than a conventional D/A converter of the type shown in  FIGS. 8 and 9 , the difference increasing as the number of bits increases. 
     In addition, since the third control circuit  104  consumes power only when the first and second capacitors C 11 , C 12  charge and discharge, it adds only slightly to the total power consumption. In particular, if the least significant data bit  1 D is zero, then once switches S 12  are switched off, there is no flow of current from the voltage generator  101  into the control circuits  102 ,  103 ,  104 . 
     Second Embodiment 
     The second embodiment is a modification of the first embodiment that operates as an (n+1)-bit D/A converter. In the example shown in  FIG. 3 , the second embodiment is a four-bit D/A converter receiving digital data bits  1 D,  2 D,  3 D,  4 D, and their complementary values  1 DB,  2 DB,  3 DB,  4 DB. The second embodiment has the same voltage generator  101 , first control circuit  102 , second control circuit  103 , and switching circuit  105  as the first embodiment, but has a modified third control circuit  204 , which will be described below. 
     The third control circuit  204  comprises switches S 21 , S 22 , S 23  and capacitors C 21 , C 22  identical to the corresponding switches S 11 , S 12 , S 13  and capacitors C 11 , C 12  in the first embodiment and interconnected in the same way. In addition, the third control circuit  204  of the second embodiment has a third capacitor C 23  with a terminal connected to the node at which the first and second capacitors C 21 , C 22  are interconnected, so that all three capacitors C 21 , C 22 , C 23  have one terminal connected to the second input V in2 . The other terminal of the third capacitor C 23  is connected through a fourth switch S 24  to the other terminal of the first capacitor C 21 , and through a fifth switch S 25  to the other terminal of the second capacitor C 22 . 
     In the third control circuit  204  of the second embodiment, the first and second capacitors C 21 , C 22  have mutually identical capacitances, the third capacitor C 23  has twice the capacitance of the first capacitor C 21 , and switches S 21 , S 22 , S 23 , and S 24  are controlled by the two least significant bits ( 1 D and  2 D and their complementary values  1 DB and  2 DB). The switches S 14  and S 15  in the switching circuit  105  are controlled by the third least significant bit ( 3 D and its complementary value  3 DB). 
     The operation of the second embodiment will now be described. 
     When  2 D=0 and  1 D=0, only the first switch S 21  is turned on and all the other switches are turned off, so the second input V in2  is output directly as the third output V out3 . 
     When  2 D=0 and  1 D=1, first the second and fifth switches S 22  and S 25  are turned on and all the other switches are turned off, connecting the first capacitor C 21  to the first input V in1  so that it is charged to (V in1 −V in2 ) while the second and third capacitors C 22  and C 23  are discharged to zero volts. After a time sufficient for capacitor C 21  to charge, the second switches S 22  are turned off and the third and fourth switches S 23  and S 24  are turned on instead, connecting the first, second, and third capacitors C 21 , C 22 , and C 23  in parallel with one another so that the charge stored in the first capacitor C 21 , i.e., C 21 (V in1 −V in2 ), is shared by these three capacitors. Since C 21 =C 22  and C 23 =2C 21  as noted above, the third output V out3  can be calculated according to the law of conservation of charge as follows:
 
 V   out3   =V   in2 +(¼)( V   in1   −V   in2 ).
 
The third output V out3  is therefore higher than the second input V in2  by one quarter of the voltage difference between the first and second inputs V in1 , V in2 .
 
     When  2 D=1 and  1 D=0, first the second switches S 22  are turned on and all the other switches are turned off, connecting the first capacitor C 21  to the first input V in1  so that it is charged to (V in1 −V in2 ) while the second capacitor C 22  is discharged to zero volts. After a time sufficient for the first capacitor C 21  to charge, the second switches S 22  are turned off and the third switches S 23  are turned on instead, connecting the first and second capacitors C 21 , C 22  in parallel with each other so that the charge stored in the first capacitor C 21  is redistributed between them. Since C 21 =C 22 , the third output V out3  can be calculated according to the law of conservation of charge as follows:
 
 V   out3   =V   in2 +(½)( V   in1   −V   in2 ).
 
     The third output V out3  is therefore higher than the second input V in2  by one half of the voltage difference between the first and second inputs V in1 , V in2 . 
     Finally, when  2 D=1 and  1 D=1, first the second and fourth switches S 22 , S 24  are turned on and all the other switches are turned off, connecting the first and third capacitors C 21  and C 23  to the first input V in1  so that they are charged to (V in1 −V in2 ) while the second capacitor C 22  is discharged to zero volts. After a time sufficient for the first and third capacitors C 21  and C 23  to charge, the second switches S 22  are turned off, the fourth switch S 24  is left turned on, and the third and fifth switches S 23  and S 25  are turned on, connecting the first, second, and third capacitors C 21 , C 22 , and C 23  in parallel with one another so that the charge stored in the first and third capacitors C 21 , C 23 , i.e., (C 21 +C 23 )(V in1 −V in2 ), is shared by these three capacitors. Since C 21 =C 22  and C 23 =2C 21 , the third output V out3  can be calculated according to the law of conservation of charge as follows:
 
 V   out3   =V   in2 +(¾)( V   in1   −V   in2 ).
 
The third output V out3  is therefore higher than the second input V in2  by three-quarters of the voltage difference between the first and second inputs V in1 , V in2 .
 
     In summary, the output voltages V out1 , V out2 , V out3  have the values shown in Table 2. 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Input 
                 V out1   
                 V out2   
                 V out3   
               
               
                   
                   
               
             
             
               
                   
                 1111 
                 V 0   
                 V 1   
                 V 1  + (3/4)(V 0  − V 1 ) 
               
               
                   
                 1110 
                 V 0   
                 V 1   
                 V 1  + (1/2)(V 0  − V 1 ) 
               
               
                   
                 1101 
                 V 0   
                 V 1   
                 V 1  + (1/4)(V 0  − V 1 ) 
               
               
                   
                 1100 
                 V 0   
                 V 1   
                 V 1   
               
               
                   
                 1011 
                 V 2   
                 V 1   
                 V 2  + (3/4)(V 1  − V 2 ) 
               
               
                   
                 1010 
                 V 2   
                 V 1   
                 V 2  + (1/2)(V 1  − V 2 ) 
               
               
                   
                 1001 
                 V 2   
                 V 1   
                 V 2  + (1/4)(V 1  − V 2 ) 
               
               
                   
                 1000 
                 V 2   
                 V 1   
                 V 2   
               
               
                   
                 0111 
                 V 2   
                 V 3   
                 V 3  + (3/4)(V 2  − V 3 ) 
               
               
                   
                 0110 
                 V 2   
                 V 3   
                 V 3  + (1/2)(V 2  − V 3 ) 
               
               
                   
                 0101 
                 V 2   
                 V 3   
                 V 3  + (1/4)(V 2  − V 3 ) 
               
               
                   
                 0100 
                 V 2   
                 V 3   
                 V 3   
               
               
                   
                 0010 
                 V 4   
                 V 3   
                 V 4  + (3/4)(V 3  − V 4 ) 
               
               
                   
                 0011 
                 V 4   
                 V 3   
                 V 4  + (1/2)(V 3  − V 4 ) 
               
               
                   
                 0001 
                 V 4   
                 V 3   
                 V 4  + (1/4)(V 3  − V 4 ) 
               
               
                   
                 0000 
                 V 4   
                 V 3   
                 V 4   
               
               
                   
                   
               
             
          
         
       
     
     Controlling the third control circuit  204  by the lower two bits of the digital input data  2 D and  1 D makes it possible to generate three additional voltage levels from the first and second inputs V in1  and V in2 , thereby obtaining five voltage levels in all from two adjacent reference voltages generated by the resistor string in the voltage generator  101 . By adding only one capacitor and two switches to the circuit configuration of the first embodiment and modifying the switch control scheme, the second embodiment doubles the number of output voltage levels. 
     Third Embodiment 
     The third embodiment is an n-bit D/A converter having the voltage generator  101 , first control circuit  102 , and second control circuit  103  shown in  FIG. 1 , the switching circuit  105  shown in  FIG. 2 , and the third control circuit  304  shown in  FIG. 4 . 
     As in the first embodiment, the third control circuit  304  has first and second inputs V in1  and V in2  and a third output V out3 . The second input V in2  is connected to the third output V out3  through a first switch S 31 . A pair of second switches S 32  are provided, one connecting the second input V in2  to the third output V out3  in parallel with the first switch S 31 , the other connecting the first input V in1  to the first terminal of a first capacitor C 31 . The first terminal of the first capacitor C 31  is also connected through a third switch S 33  to the third output V out3 . The second terminal of the first capacitor C 31  is connected to the second input V in2 . Second and third capacitors C 3p , C 3n  are connected between the third output V out3  and a power supply (Vdd) and between the third output V out3  and ground (Vss), respectively. 
     The capacitance of the first capacitor is equal to the sum of the capacitances of the second and third capacitors (C 31 =C 3p +C 3n ). All of the switches S 31 , S 32 , S 33  are controlled by the least significant bit  1 D and its complementary value  1 DB (not shown). 
     Next, the operation of the third control circuit  304  will be described. 
     When  1 D=0, the first switch S 31  is turned on and the second and third switches S 32 , S 33  are turned off, so the second input V in2  is output directly as the third output V out3 . 
     When  1 D=1, the first and third switches S 31 , S 33  are turned off and the second switches S 32  are turned on, connecting the first capacitor C 31  to the first input V in1  and the second and third capacitors C 3p , C 3n  to the second input V in2  so that the first capacitor C 31  is charged to (V in1 −V in2 ), the second capacitor C 3p  to (Vdd−V in2 ), and the third capacitor C 3n  to (V in2 −Vss). After a time sufficient for these capacitors to charge, the second switches S 32  are turned off and the third switch S 33  is turned on instead, whereby the charges stored in the first, second, and third capacitors C 31 , C 3p , and C 3n  are redistributed among these three capacitors according to the law of conservation of charge. Consequently, from the condition that C 31 =C 3p +C 3n , the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(½)( V   in1   −V   in2 )
 
The third output V out3  is therefore a voltage halfway between the first and second inputs V in1  and V in2 , as in the first embodiment.
 
     The second and third capacitors C 3p , C 3n  in the third embodiment may be input capacitance components of a voltage follower amplifier (not shown) connected to the third output V out3 , in which case the third control circuit  304  provides the same function as the third control circuit  104  of the first embodiment with only one capacitor C 31  instead of two. Alternatively, the second and third capacitors C 3p , C 3n  may be physically present in the third control circuit  304 , but their capacitance values may be reduced by an amount equivalent to the input capacitance of the amplifier, thereby reducing the capacitive loads on the first and second control circuits  102 ,  103  and improving the D/A conversion speed. In any case, the third control circuit  304  of the third embodiment uses fewer switches than the third control circuit  104  in the first embodiment and has a simpler structure and smaller size, although both embodiments convert the same number of input data bits. 
     The third embodiment can be modified by eliminating the second switch S 32  connected in parallel with the first switch S 31 , and modifying the operation of the first switch S 31  so that when  1 D=1, the first switch S 31  is turned on and off together with the remaining second switch S 32 . 
     The third embodiment can also be modified by eliminating the second capacitor C 3p , in which case the remaining first and third capacitors should have equal capacitance values, or by eliminating the third capacitor C 3n , in which case the remaining first and second capacitors should have equal capacitance. More generally, the second and third capacitors C 3p , C 3n  may be replaced by a single capacitor connected between the third output V out3  and any fixed potential. 
     Fourth Embodiment 
       FIG. 5  illustrates a third control circuit  404  according to a fourth embodiment of the invention. The fourth embodiment is a modification of the third embodiment that operates as an (n+1)-bit D/A converter. The voltage generator  101 , first control circuit  102 , second control circuit  103  and switching circuit  105  are the same as in the first embodiment, as shown in  FIGS. 1 and 2 . 
     The third control circuit  404  in the fourth embodiment has first, second, and third switches S 41 , S 42 , S 43  and capacitors C 41 , C 4n , C 4p  similar to the first, second, and third switches S 31 , S 32 , S 33  and capacitors C 31 , C 3n , C 3p  of the third embodiment, with similar interconnections thereamong. In addition, the third control circuit  404  in the fourth embodiment has fourth and fifth capacitors C 44 , C 45  and fourth and fifth switches S 44 , S 45 . The fourth switch S 44  and fourth capacitor C 44  are connected in series with each other and in parallel with the first capacitor C 41 . Similarly, the fifth switch S 45  and fifth capacitor C 45  are connected in series with each other and in parallel with the first capacitor C 41 . The first terminals of the first, fourth, and fifth capacitors C 41 , C 4n , C 4p  are thus connected through switches to the first input V in1 , while the second terminals of these capacitors are connected in common to the second input V in2 . 
     The capacitance values of the first to fifth capacitors C 41 , C 4p , C 4n , C 44 , and C 45  in the third control circuit  404  in the fourth embodiment satisfy the following conditions:
 
3 C   41   =C   4p   +C   4n 
 
C 44 =2C 41 
 
C 45 =6C 41 
 
     The switches S 41 , S 42 , S 43 , S 44 , and S 45  in the third control circuit  404  in the fourth embodiment are controlled by the two least significant bits  1 D and  2 D of the (n+1)-bit input data, and their complementary values  1 DB and  2 DB. 
     Next, the operation of the third control circuit  404  will be described. 
     When  2 D=0 and  1 D=0, the first switch S 41  is turned on and all the other switches are turned off, so the second input V in2  is output directly as the third output V out3 . 
     When  2 D=0 and  1 D=1, the second switches S 42  are turned on and all the other switches are turned off, connecting the first capacitor C 41  to the first input V in1  and the second and third capacitors C 4p , C 4n  to the second input V in2  so that the first capacitor C 41  is charged to (V in1 −V in2 ), the second capacitor C 4p  to (Vdd−V in2 ), and the third capacitor C 4n  to (V in2 −Vss). After a time sufficient for these capacitors to charge, the second switches S 42  are turned off and the third switch S 43  is turned on instead, whereby the charges stored in the first, second, and third capacitors C 41 , C 4p , and C 4n  are redistributed among these three capacitors according to the law of conservation of charge. Consequently, from the condition that 3C 41 =C 4p +C 4n , the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(¼)( V   in1   −V   in2 )
 
The third output V out3  is therefore higher than the second input voltage V in2  by one quarter of the voltage difference between the first and second inputs V in1 , V in2 .
 
     When  2 D=1 and  1 D=0, the second and fourth switches S 42 , S 44  are turned on and all the other switches are turned off, causing the first and fourth capacitors C 41 , C 44  to charge to (V in1 −V in2 ), the second capacitor C 4p  to charge to (Vdd−V in2 ), and the third capacitor C 4n  to charge to (V in2 −Vss). After a time sufficient for these capacitors to charge, the second switches S 42  are turned off and the third switch S 43  is turned on instead, whereby the charges stored in the first to fourth capacitors C 41 , C 4p , C 4n , and C 44  are redistributed among these four capacitors according to the law of conservation of charge. Because C 41 +C 44 =C 4p +C 4n , the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(½)( V   in1   −V   in2 )
 
The third output V out3  is therefore a voltage halfway between the first and second inputs V in1 , V in2 .
 
     Finally, when  2 D=1 and  1 D=1, the second, fourth, and fifth switches S 42 , S 44 , and S 45  are turned on and the other switches are turned off, causing each of the first, fourth, and fifth capacitors C 41 , C 44 , and C 45  to charge to (V in1 −V in2 ), the second capacitor C 4p  to charge to (Vdd−V in2 ), and the third capacitor C 4n  to charge to (V in2 −Vss). After a time sufficient for these capacitors to charge, the second switches S 42  are turned off and the third switch S 43  is turned on instead, whereby the charges stored in the first to fifth capacitors C 41 , C 4p , C 4n , C 44 , and C 45  are redistributed among these five capacitors according to the law of conservation of charge. Because C 41 +C 44 +C 45 =9C 41 =3(C 4p +C 4n ), the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(¾)( V   in1   −V   in2 )
 
The third output V out3  is therefore higher than the second input voltage V in2  by three-quarters of the voltage difference between the first and second inputs V in1  and V in2 .
 
     As in the third embodiment, the second and third capacitors C 4p , C 4n  may be input capacitance components of an amplifier (not shown) connected to the third output V out3 , or the capacitance values of the second and third capacitors C 4p , C 4n  may be reduced by an amount equivalent to the input capacitance of the amplifier. 
     The fourth embodiment can be modified to convert (n+m)-bit input data, where m is an integer greater than one, by adding further switches and capacitors in parallel with the fourth and fifth switches and capacitors. 
     Fifth Embodiment 
       FIG. 6  illustrates a third control circuit  504  according to a fifth embodiment of the invention. The fifth embodiment has first, second, and third switches S 51 , S 52 , S 53  and first and second capacitors C 51 , C 52  similar to the first, second, and third switches S 11 , S 12 , S 13  and first and second capacitors C 11 , C 12  in the first embodiment, with similar interconnections, except that the second capacitor C 52  is connected through the lower second switch S 52  to the first input V in1  instead of the second input V in2 . In addition, the fifth embodiment has third and fourth capacitors C 5p , C 5n  connected to the third output V out3 , similar to the second and third capacitors C 3p , C 3n  in the third embodiment, the fourth capacitor C 5p  being connected between the third output V out3  and the power supply Vdd, the fifth capacitor C 5n  being connected between the third output V out3  and ground Vss. 
     Alternatively, the fifth embodiment can be derived from the circuit structure of the third embodiment by adding the second capacitor C 52  and the switches S 52 , S 53  that connect it to the first input V in1  and third output V out3 . 
     The fifth embodiment also includes a voltage generator  101 , first control circuit  102 , second control circuit  103  and switching circuit  105  as shown in  FIGS. 1 and 2 . 
     The capacitors C 51 , C 52 , C 5p , and C 5n  in the third control circuit  504  of the fifth embodiment all have equal capacitance values. The first and third capacitors C 51 , C 5p  are structured as p-channel MOS (PMOS) transistors, the capacitance being provided by the transistor gate capacitance. The second and fourth capacitors C 52 , C 5n  are structured as n-channel MOS (NMOS) transistors, the capacitance being provided by the transistor gate capacitance. 
     Like the first embodiment, the fifth embodiment operates as an n-bit D/A converter. The switches S 51 , S 52 , and S 53  in the third control circuit  504  are controlled by the least significant bit  1 D and its complementary value  1 DB (not shown). 
     Next, the operation of the third control circuit  504  will be described. 
     When  1 D=0, the first switch S 51  is turned on and the second and third switches S 52 , S 53  are turned off, so the second input V in2  is output directly as the third output V out3 . 
     When  1 D=1, the first and second switches S 51 , S 52  are turned on and the third switches S 53  are turned off, causing both the first and second capacitors C 51 , C 52  to charge to (V in1 −V in2 ), the third capacitor C 5p  to charge to (Vdd−V in2 ), and the fourth capacitor C 5n  to charge to (V in2 −Vss). After a time sufficient for these capacitors to charge, the first and second switches S 51 , S 52  are turned off and the third switches S 53  are turned on instead, whereby the charges stored in the first to fourth capacitors C 51 , C 52 , C 5p , and C 5n  are redistributed among them according to the law of conservation of charge. Since all the capacitors have identical capacitance values as noted above, the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(½)( V   in1   −V   in2 )
 
The third output V out3  is therefore a voltage halfway between the first and second inputs V in1  and V in2 .
 
     Since all the capacitors in the third control circuit  504  of the fifth embodiment are formed by the gate capacitances of MOS transistors and the third output V out3  is determined by the ratios of these capacitances, process variations that cause a difference between the gate capacitances of PMOS and NMOS transistors affect the third output V out3 , but the third control circuit  504  is structured so that the effect of a capacitance difference between the first and second capacitors C 51  and C 52  is canceled by the similar difference between the capacitance of the third and fourth capacitors C 5p  and C 5n . The third output V out3  therefore has higher precision than in the first to fourth embodiments. Furthermore, the gate capacitance of a MOS transistor is comparatively small, so the capacitors in the fifth embodiment can be charged and discharged rapidly, resulting in high-speed D/A conversion. 
     Sixth Embodiment 
       FIG. 7  illustrates a third control circuit  604  according to a sixth embodiment of the invention. The sixth embodiment is a modification of the fifth embodiment that operates as an (n+1)-bit D/A converter: in the example shown in  FIG. 7 , as a four-bit D/A converter receiving data bits  1 D– 4 D and their complementary values  1 DB– 4 DB. The sixth embodiment also includes a voltage generator  101 , first control circuit  102 , second control circuit  103  and switching circuit  105  as shown in  FIGS. 1 and 2 . 
     The third control circuit  604  has first and second inputs V in1 , V in2  and a third output V out3  as in the first embodiment, and comprises first to fifth capacitors C 61 , C 62 , C 63 , C 6p , and C 6n  and first to fifth switches S 61 , S 62 , S 63 , S 64 , and S 65 . The first switch S 61  is connected between the second input V in2  and third output V out3 . The second and third switches S 62  and S 63  are connected in series between the first input V in1  and third output V out3 . The first to third capacitors C 61 , C 62 , and C 63  are connected between the second input V in2  and a node disposed between the second and third switches S 62 , S 63 , the first and second capacitors C 61 , C 62  being connected in series, the third capacitor C 63  being connected in parallel with the second capacitor C 62 . The fourth switch S 64  is connected between the third output V out3  and the node at which the first and second capacitors C 61 , C 62  are interconnected. The fifth switch S 65  is connected in parallel with the first capacitor C 61 . The fourth and fifth capacitors C 6p  and C 6n , are similar to the third and fourth capacitors C 5p , C 5n  in the fifth embodiment, the fourth capacitor C 6p  being connected between the third output V out3  and power supply Vdd, the fifth capacitor C 6n  being connected between the third output V out3  and ground Vss. 
     The capacitors C 61 , C 62 , C 63 , C 6p , and C 6n  in the third control circuit  604  of the sixth embodiment are all formed by the gate capacitances of MOS transistors and have equal capacitance values. The first and fourth capacitors C 61 , C 6p  are formed by the gate capacitances of PMOS transistors, whereas the second, third, and fifth capacitors C 62 , C 63 , and C 6n  are formed by the gate capacitances of NMOS transistors. The switches S 61 , S 62 , S 63 , S 64 , and S 65  are controlled by the two least significant bits  1 D and  2 D and their complementary values  1 DB and  2 DB. 
     Next, the operation of the third control circuit  604  will be described. 
     When  2 D=0 and  1 D=0, the first switch S 61  is turned on and all the other switches are turned off, so the second input V in2  is output directly as the third output V out3 . 
     When  2 D=0 and  1 D=1, the first and second switches S 61 , S 62  are turned on and all the other switches are turned off, causing the capacitor circuit comprising the first to third capacitors C 61 , C 62 , and C 63  to charge to a total voltage of (V in1 −V in2 ), the fourth capacitor C 6p  to charge to (Vdd−V in2 ), and the fifth capacitor C 6n  to charge to (V in2 −Vss). After a time sufficient for the capacitors to charge, the first and second switches S 61 , S 62  are turned off and the third switch S 63  is turned on instead, whereby the charges stored in the first to fifth capacitors C 61 , C 62 , C 63 , C 6p , and C 6n  are redistributed among these five capacitors according to the law of conservation of charge. Since all the capacitors have identical capacitance values as noted above, the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(¼)( V   in1 −V in2 )
 
The third output V out3  is a voltage higher than the second input voltage V in2  by one quarter of the voltage difference between the first and second inputs V in1  and V in2 .
 
     When  2 D=1 and  1 D=0, the first, second, and fifth switches S 61 , S 62 , and S 65  are turned on and the other switches are turned off, causing both the second and third capacitors C 62  and C 63  to charge to (V in1 −V in2 ), the fourth capacitor C 6p  to charge to (Vdd−V in2 ), and the fifth capacitor C 6n  to charge to (V in2 −Vss) while the first capacitor C 61  discharges to zero volts. After a time sufficient for these capacitors to charge and discharge, the first, second, and fifth switches S 61 , S 62 , and S 65  are turned off and the third and fourth switches S 63  and S 64  are turned on instead, whereby the first capacitor C 61  remains discharged to zero volts and the charge stored in the second to fifth capacitors C 62 , C 63 , C 6p , and C 6n  is redistributed among these four capacitors according to the law of conservation of charge. Since the four capacitors have identical capacitance values, the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(½)( V   in1   −V   in2 )
 
The third output V out3  is a voltage halfway between the first and second inputs V in1  and V in2 .
 
     Finally, when  2 D=1 and  1 D=1, the first, second, and fifth switches S 61 , S 62 , and S 65  are turned on and the other switches are turned off, causing both the second and third capacitors C 62  and C 63  to charge to (V in1 −V in2 ), fourth capacitor C 6p  to (Vdd−V in2 ), and fifth capacitor C 6n  to (V in2 −Vss). After a time sufficient for these capacitors to charge, the first, second, and fifth switches S 61 , S 62 , and S 65  are turned off and only the third switch S 63  is turned on instead, whereby the charge stored in the second to fifth capacitors C 62 , C 63 , C 6p , and C 6n  is redistributed among all five capacitors, including the first capacitor C 61 , according to the law of conservation of charge. Since all the capacitors have identical capacitance values, the third output V out3  is given by the following equation.
 
 V   out3   =V   in2 +(¾)( V   in1 −V in2 )
 
The third output V out3  is a voltage higher than the second input voltage V in2  by three-quarters of the voltage difference between the first and second inputs V in1  and V in2 .
 
     All the capacitors in the third control circuit  604  of the sixth embodiment are formed by the gate capacitances of MOS transistors and the third output V out3  is determined by the ratios of these capacitors. Like the third control circuit  504  in the fifth embodiment, third control circuit  604  of the sixth embodiment is structured so that variations in capacitance values caused by process variations cancel out and the third output V out3  has higher precision than in the first to fourth embodiments, and the relatively small gate capacitance of an MOS transistor means that the first to fifth capacitors can be charged and discharged rapidly, resulting in high-speed D/A conversion. 
     The second and third capacitors C 62 , C 63  can be replaced by a single capacitor having twice the capacitance of the first capacitor C 61 . 
     Those skilled in the art will recognize that further variations in the preceding embodiments are possible within the scope of the invention, which is defined in the appended claims.