Abstract:
A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This present application is a divisional application of U.S. patent application Ser. No. 13/670,502, filed Nov. 7, 2012. The aforementioned U.S. patent application, including any appendices or attachments thereof, is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    The present disclosure generally relates to complementary metal-oxide semiconductor (CMOS) image sensors. 
         [0003]    Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. 
         [0004]      FIG. 1  is a block diagram of an image sensor  100 . Image sensor  100  includes an active pixel sensor (APS) pixel  102 , a correlated double sampling (CDS) circuit  104  coupled to the APS pixel, and an analog-to-digital converter (ADC) circuit  106  coupled to the CDS circuit. 
         [0005]    APS pixel  102  includes a pinned photodetector  108 . Photodetector  108  includes a P-type body  110 , an N-type implant  112 , and a shallow pinning P-type implant  114  that separates the N-type implant from the surface. A transfer gate  116  controls the charge transfer from photodetector  108  to a floating diffusion (FD) node  118 . A reset transistor  120  is coupled to FD node  118  to reset photodetector  108  before and after charge is integrated. A source follower (SF) transistor  122  is coupled to FD node  118  to convert charge to output voltage. 
         [0006]    CDS circuit  104  includes a sample and hold reset (SHR) transistor  124  coupled to the source of SF transistor  122  to transfer a reset signal to a SHR capacitor  126  for storage. A sample and hold signal (SHS) transistor  128  is coupled to the source of SF transistor  122  to transfer a charge signal to a SHS capacitor  130  for storage. An amplifier  132  has its negative and positive inputs coupled to SHR capacitor  126  and SHS capacitor  130 , respectively. Amplifier  132  outputs a signal that is the difference between the charge signal and the reset signal to remove reset noise. 
         [0007]    ADC circuit  106  includes a comparator  134  with a negative input coupled to a ramp generator  136  and a positive input coupled to the output of amplifier  132 . The output of comparator  134  is coupled to a latch  138  so the latch stores the value of a counter  140  when the signal from ramp generator  136  becomes larger than the signal from amplifier  132 . 
       SUMMARY 
       [0008]    In one or more embodiments of the present disclosure, a method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level. 
         [0009]    The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings. 
           [0011]    In the drawings: 
           [0012]      FIG. 1  is a block diagram of an image sensor; 
           [0013]      FIG. 2  is a block diagram of an image sensor with a pair of pixels; 
           [0014]      FIG. 3  is a flowchart of a method to read out a pair of pixels in the pixel sensor of  FIG. 2 ; 
           [0015]      FIG. 4  is a timing diagram for the method of  FIG. 3 ; and 
           [0016]      FIGS. 5 and 6  combine to form a block diagram of an image sensor with multiple pairs of pixels, all arranged in accordance with at least some embodiments of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]      FIG. 2  is a block diagram of an exemplary image sensor  200  in one or more embodiments of the present disclosure. Image sensor  200  includes a pair of active pixel sensor (APS) pixels  202  and  204  that are read in a collaborative manner where correlated double sampling (CDS) and analog-to-digital (ADC) timing are shared. Although only one pair of pixels is shown in sensor  200 , the general concept described herein may be applied to multiple pairs of pixels forming an array of pixels. 
         [0018]    First APS pixel  202  includes a first floating diffusion (FD) node  206 , a first photodetector  208 , a first transfer transistor  210  that couples the first photodetector to the first FD node, a ramp up line Rup&lt; 0 &gt; coupled to the first FD node, and a first reset transistor  214  coupling a first supply line HVDD&lt; 0 &gt; to the first FD node. Specifically, first transfer transistor  210  has its source coupled to the cathode of first photodetector  208  and its drain coupled to first FD node  206 . First transfer transistor  210  has its gate connected to a first transfer line TX&lt; 0 &gt;, which controls the charge transfer from first photodetector  208  to first FD node  206 . First reset transistor  214  has its drain coupled to first supply line HVDD&lt; 0 &gt; and its source coupled to first FD node  206 . First reset transistor  214  has its gate connected to a first reset line RST&lt; 0 &gt;, which controls the reset of first photodetector  208  and/or first FD node  206 . Although not shown, first APS pixel  202  includes a first source follower (SF) transistor with near unity gain (0.9) that converts the charge at first FD node  206  to an output voltage. 
         [0019]    Ramp up line Rup&lt; 0 &gt; supplies a signal that ramps up a transferred charge signal, which is compared with a reference signal that is ramped down to determine a digital level of APS pixel  202  as described later. Ramp up line Rup&lt; 0 &gt; also supplies a signal that ramps down a reference signal, which is compared with a transferred charge signal that is ramped up to determine a digital level of APS pixel  204  as described later. Ramp up line Rup&lt; 0 &gt; is placed adjacent to but insulated from first FD node  206  so the ramp up line is capacitively coupled to the first FD node. This capacitive coupling is represented by a capacitor  260  between ramp up line Rup&lt; 0 &gt; and first FD node  206 . Image sensor  200  includes a polarity reversing switch  263  that couples a positive ramp generator  264  to ramp up line Rup&lt; 0 &gt; and a negative ramp generator  266  to ramp down line Rdn&lt; 0 &gt;, and vise versa. 
         [0020]    Second APS pixel  204  includes a second FD node  216 , a second photodetector  218 , a second transfer transistor  220  that couples the second photodetector to the second FD node, a ramp down line Rdn&lt; 0 &gt; coupled to the second FD node, and a second reset transistor  222  coupling a second supply line HVDD&lt; 1 &gt; to the second FD node. Specifically, second transfer transistor  220  has its source coupled to the cathode of second photodetector  218  and its drain coupled to second FD node  216 . Second transfer transistor  220  has its gate coupled to a second transfer line TX&lt; 1 &gt;, which controls the charge transfer from second photodetector  218  to second FD node  216 . Second reset transistor  224  has its drain coupled to second supply line HVDD&lt; 1 &gt; and its source coupled to second FD node  216 . Second reset transistor  224  has its gate coupled to a second reset line RST&lt; 1 &gt;, which controls the reset of second photodetector  218  and/or second FD node  216 . Although not shown, second APS pixel  204  includes a second SF transistor with near unity gain (e.g., 0.9) that converts the charge at second FD node  216  to an output voltage. 
         [0021]    Ramp down line Rdn&lt; 0 &gt; supplies a signal that ramps down a reference signal, which is compared with a transferred charge signal that is ramped up to determine a digital level of APS pixel  202  as described later. Ramp down line Rdn&lt; 0 &gt; also supplies a signal that ramps up a transferred charge signal, which is compared with a reference signal that is ramped down to determine a digital level of APS pixel  204  as described later. Ramp down line Rdn&lt; 0 &gt; is placed adjacent to but insulated from second DF node  216  so the ramp down line is capacitively coupled to the second FD node. This capacitive coupling is represented by a capacitor  262  between ramp down line Rdn&lt; 0 &gt; and second FD node  216 . As introduced above, polarity reversing switch  263  couples positive ramp generator  264  to ramp up line Rup&lt; 0 &gt; and negative ramp generator  266  to ramp down line Rdn&lt; 0 &gt;, and vise versa. 
         [0022]    Image sensor  200  includes a readout circuit  228  having one or more stages. Readout circuit  228  includes a first stage with a first comparator  230  having its negative input  232  coupled by the first SF transistor (not shown) to first FD node  206  and its positive input  234  coupled by the second SF transistor (not shown) to second FD node  216 . APS pixels  202  and  204  may be collaboratively read using CDS. When reading first APS pixel  202 , the transferred charge signal from first photodetector  208  at first FD node  206  is compared with a reference signal at second FD node  216  that has been reset. When reading second APS pixel  204 , the transferred charge signal from second photodetector  218  at second FD node  216  is compared with a reference signal at first FD node  206  that has been reset. 
         [0023]    Readout circuit  228  may include a second stage with a second comparator  236  having its negative input  238  coupled by a capacitor  240  to a negative output  242  of first comparator  230 , and its positive input  244  coupled by a capacitor  246  to a positive output  248  of the first comparator. 
         [0024]    Readout circuit  228  includes a latch  250  having its control input  252  coupled to an output  254  of second comparator  236 , and its data input  256  coupled to a counter  258 . 
         [0025]      FIG. 3  is a flowchart of an exemplary method to  300  to read out pixels in image sensor  200  ( FIG. 2 ) in one or more embodiments of the present disclosure.  FIG. 4  is a timing diagram  400  for reading out pixels in image sensor  200  using method  300  in one or more embodiments of the present disclosure. Method  300  may include one or more operations, functions, or actions illustrated by one or more blocks. Although the blocks are illustrated in sequential orders, these blocks may also be performed in parallel, and/or in a different order than those described herein. Also, the various blocks may be combined into fewer blocks, divided into additional blocks, and/or eliminated based upon the desired implementation. Method  300  may begin in a block  302 . 
         [0026]    In block  302 , first photodetector  208  is reset at time t 0  by driving lines RST&lt; 0 &gt;, HVDD&lt; 0 &gt;, and TX&lt; 0 &gt; high at time t 0 . Line TX&lt; 0 &gt; stays high until time t 1 , and line HVDD&lt; 0 &gt; stays high until time t 2  (t 2 &gt;t 1 ) to ensure first photodetector  208  is fully reset. Line RST&lt; 0 &gt; may stay high until time t 8 . Note that line RST&lt; 1 &gt; is also driven high at t 0  and stays high until time t 8 . Block  302  may be followed by block  304 . 
         [0027]    In block  304 , first photodetector  208  is integrated by exposing it to light for a predetermined exposure time. Block  304  may be followed by bock  306 . 
         [0028]    In block  306 , second photodetector  218  is reset at time t 4  by maintaining line RST&lt; 1 &gt; high and driving lines HVDD&lt; 1 &gt; and TX&lt; 1 &gt; high at time t 4 . Line TX&lt; 1 &gt; stays high until time t 5 , and line HVDD&lt; 1 &gt; stays high until time t 6  (t 6 &gt;t 5 ) to ensure second photodetector  218  is fully reset. Line RST&lt; 1 &gt; may remain high until time t 8 . Block  306  may be followed by block  308 . 
         [0029]    In block  308 , second photodetector  218  is integrated by exposing it to light for the predetermined exposure time. Block  308  may be followed by bock  310 . 
         [0030]    In blocks  310  to  318 , first APS pixel  202  is read out. In block  310 , first FD node  206  and second FD node  216  are reset at time t 7  by maintaining lines RST&lt; 0 &gt; and RST&lt; 1 &gt; high and driving lines HVDD&lt; 0 &gt; and HVDD&lt; 1 &gt; high at time t 7 . Lines RST&lt; 0 &gt; and RST&lt; 1 &gt; are returned to low at time t 8 . Lines HVDD&lt; 0 &gt; and HVDD&lt; 1 &gt; are returned to low at time t 9  (t 9 &gt;t 8 ) to ensure first FD node  206  and second FD node  216  are fully reset. During time t 7  to t 9 , lines TX&lt; 0 &gt; and TX&lt; 1 &gt; are maintained low to isolate first FD node  206  and second FD node  216  from first photodetector  208  and second photodetector  218 , respectively. Note that turning off first reset transistor  214  and second reset transistor  224  during the reset of first FD node  206  and second FD node  216  introduces charge injection and clock feedthrough at time t 8 . Block  310  may be followed by block  312 . 
         [0031]    In block  312 , charge from first photodetector  208  is transferred to first FD node  206  by driving line TX&lt; 0 &gt; high from time t 10  to t 11 . Note that turning on and off first transfer transistor  210  during the charge transfer introduces charge injection and clock feedthrough at times t 10  and t 11 . Block  312  may be followed by block  314 . 
         [0032]    In block  314 , first comparator  230  trips at time t 11  when a first signal (e.g., a first voltage) at negative input  232  is less than a second signal (e.g., a second voltage) at positive input  234 , which causes second comparator  236  to trip and generate a first latch signal that causes latch  250  to capture a first counter value from counter  258 . Block  314  may be followed by block  316 . 
         [0033]    In block  316 , from time t 12  to t 13 , positive ramp generator  264  ramps up line Rup&lt; 0 &gt; to increment the first voltage at negative input  232  of first comparator  230 , and negative ramp generator  266  ramps down line Rdn&lt; 0 &gt; to decrement the second voltage at positive input  234  of the first comparator. As described above, polarity switch  263  is used to provide the proper connection between generators  264 ,  266  and lines Rup&lt; 0 &gt;, Rdn&lt; 0 &gt;. Block  316  may be followed by block  318 . 
         [0034]    In block  318 , first comparator  230  trips again (indicated by reference number  402  in  FIG. 4 ) when the first voltage at negative input  232  is greater than the second voltage at positive input  234 , which causes second comparator  236  to trip again and generate a second latch signal that causes latch  250  to capture a second counter value from counter  258 . The difference between the second counter value and the first counter value indicates a digital value of first APS pixel  202 . Block  318  may be followed by block  320 . 
         [0035]    In blocks  320  to  328 , second APS pixel  204  is read out. In block  320 , first FD node  206  and second FD node  216  are reset at time t 13  by driving lines RST&lt; 0 &gt;, RST&lt; 1 &gt;, HVDD&lt; 0 &gt;, and HVDD&lt; 1 &gt; high. Lines RST&lt; 0 &gt; and RST&lt; 1 &gt; are returned to low at time t 14 . Lines HVDD&lt; 0 &gt; and HVDD&lt; 1 &gt; are returned to low at time t 15  (t 15 &gt;t 14 ) to ensure first FD node  206  and second FD node  216  are fully reset. During time t 13  to t 15 , lines TX&lt; 0 &gt; and TX&lt; 1 &gt; are maintained low to isolate first FD node  206  and second FD node  216  from first photodetector  208  and second photodetector  218 , respectively. Block  320  may be followed by block  322 . 
         [0036]    In block  322 , charge from second photodetector  218  is transferred to second FD node  216  by driving line TX&lt; 1 &gt; high from time t 16  to t 17 . Block  322  may be followed by block  324 . 
         [0037]    In block  324 , first comparator  230  trips when the first voltage at negative input  232  is higher than the second voltage at positive input  234 , which causes second comparator  236  to trip and generate a third latch signal that causes latch  256  to capture a third counter value from counter  258 . Block  324  may be followed by block  326 . 
         [0038]    In block  326 , from time t 18  to t 19 , positive ramp generator  264  ramps up line Rdn&lt; 0 &gt; to increment the second voltage at positive input  234  of first comparator  230 , and negative ramp generator  266  ramps down line Rup&lt; 0 &gt; to decrement the first voltage at negative input  232  of the first comparator. As described above, polarity switch  263  is used to provide the proper connection between generators  264 ,  266  and lines Rup&lt; 0 &gt;, Rdn&lt; 0 &gt;. Block  326  may be followed by block  328 . 
         [0039]    In block  328 , first comparator  230  trips again when the first voltage at negative input  232  is lower than the second voltage at positive input  234 , which causes second comparator  236  to trip again and generate a fourth latch signal that causes latch  250  to capture a fourth counter value from counter  258 . The difference between the fourth counter value and the third counter value indicates a digital value of second APS pixel  204 . 
         [0040]    As described above, image sensor  200  ( FIG. 2 ) of the present disclosure provide low readout noise compared to image sensor  100  ( FIG. 1 ). Image sensor  200  does not employ any sampling and hold circuit and operation, thereby eliminating a source of kTC reset noise. Image sensor  200  also does not amplify signals with operational amplifier or source follower transistor, thereby eliminating another source of noise. 
         [0041]      FIGS. 5 and 6  combine to form a block diagram of an exemplary image sensor  500  in one or more embodiments of the present disclosure. Image sensor  500  applies the concept of image sensor  200  ( FIG. 2 ) to four pairs of APS pixels arranged in a four by four pixel array. 
         [0042]    The pixels in image sensor  500  are arranged in four columns  502 ,  504 ,  506 , and  508 . Each column has two pairs of pixels and each pair is collaboratively read out in the manner described above for APS pixels  202  and  204  ( FIG. 2 ) in image sensor  200  ( FIG. 2 ). 
         [0043]    Column  502  includes a first pair of APS pixels  202  and  204 . Shown in more detail, first APS pixel  202  includes a first SF transistor  516  that couples first FD node  206  to negative input  232  of comparator  230 , and second APS pixel  204  includes a second SF transistor  518  that couples second FD node  216  to positive input  234  of comparator  230 . SF transistors  516  and  518  form an input pair for comparator  230 . Specifically, first SF transistor  516  has its gate coupled to first FD node  206 , its source coupled to negative input  232  of comparator  230 , and its drain coupled to a bias line  520 . Second SF transistor  518  has its gate coupled to second FD node  216 , its source coupled to positive input  244  of comparator  230 , and its drain coupled to bias line  520 . 
         [0044]    Column  502  further includes a second pair of APS pixels  522  and  524  that are read in the same manner described the first pair of APS pixels  202  and  204 . 
         [0045]    Third APS pixel  522  includes a third FD node  526 , a third photodetector  528 , a third transfer transistor  530  that couples the third photodetector to the third FD node, a ramp up line Rup&lt; 1 &gt; coupled to the third FD node, a third reset transistor  534  coupling a third supply line HVDD&lt; 2 &gt; to the third FD node, and a third SF transistor  535  that couples the third FD node to negative input  232  of comparator  230 . Specifically, third transfer transistor  530  has its source coupled to the cathode of third photodetector  528  and its drain coupled to third FD node  526 . Third transfer transistor  530  has its gate connected to a third transfer line TX&lt; 2 &gt;, which controls the charge transfer from third photodetector  528  to third FD node  526 . Third reset transistor  534  has its drain coupled to third supply line HVDD&lt; 2 &gt; and its source coupled to third FD node  526 . Third reset transistor  534  has its gate connected to a third reset line RST&lt; 2 &gt;, which controls the reset of third photodetector  528  and/or third FD node  526 . Third SF transistor  535  has its gate coupled to third FD node  526 , its source coupled to negative input  232  of comparator  230 , and its drain coupled to bias line  520 . 
         [0046]    Ramp up line Rup&lt; 1 &gt; is placed adjacent to but insulated from third FD node  526  so the ramp up line is capacitively coupled to the third FD node. This capacitive coupling is represented by a capacitor  560  between ramp up line Rup&lt; 1 &gt; and third FD node  526 . Ramp up line Rup&lt; 1 &gt; receives a ramp up signal from positive ramp generator  260  ( FIG. 2 ). 
         [0047]    Fourth APS pixel  524  includes a fourth FD node  536 , a fourth photodetector  538 , a fourth transfer transistor  540  that couples the fourth photodetector to the fourth FD node, a ramp down line Rdn&lt; 1 &gt; coupled to the fourth FD node, a fourth reset transistor  544  coupling a fourth supply line HVDD&lt; 3 &gt; to the fourth FD node, and a fourth SF transistor  545  that couples the fourth FD node to positive input  234  of comparator  230 . Specifically, fourth transfer transistor  540  has its source coupled to the cathode of fourth photodetector  538  and its drain coupled to fourth FD node  536 . Fourth transfer transistor  540  has its gate coupled to a fourth transfer line TX&lt; 3 &gt;, which controls the charge transfer from fourth photodetector  538  to fourth FD node  536 . Fourth reset transistor  544  has its drain coupled to fourth supply line HVDD&lt; 3 &gt; and its source coupled to fourth FD node  536 . Fourth reset transistor  544  has its gate coupled to a fourth reset line RST&lt; 3 &gt;, which controls the reset of fourth photodetector  538  and/or fourth FD node  536 . Fourth SF transistor  545  has its gate coupled to fourth FD node  536 , its source coupled to positive input  234  of comparator  230 , and its drain coupled to bias line  520 . 
         [0048]    Ramp down line Rdn&lt; 1 &gt; is placed adjacent to but insulated from fourth FD node  536  so the ramp down line is capacitively coupled to the fourth FD node. This capacitive coupling is represented by a capacitor  562  between ramp down line Rdn&lt; 1 &gt; and fourth FD node  536 . Ramp down line Rdn&lt; 1 &gt; receives a ramp down signal from negative ramp generator  262  ( FIG. 2 ). 
         [0049]    Column  502  includes a bias transistor  564  that biases SF transistors  516 ,  518 ,  535 , and  545 . Bias transistor  564  has its gate coupled to a line SF_BIAS, its drain coupled to bias line  520 , and its source coupled to a negative power supply line. 
         [0050]    Columns  504 ,  506 , and  508  are arranged similarly to column  502 . Columns  502 ,  504 ,  506 , and  508  share lines SF_BIAS, RST&lt; 0 &gt;, HVDD&lt; 0 &gt;, TX&lt; 0 &gt;, Rup&lt; 0 &gt;, RST&lt; 1 &gt;, HVDD&lt; 1 &gt;, TX&lt; 1 &gt;, Rdn&lt; 0 &gt;, RST&lt; 2 &gt;, HVDD&lt; 2 &gt;, TX&lt; 2 &gt;, Rup&lt; 1 &gt;, RST&lt; 3 &gt;, HVDD&lt; 3 &gt;, TX&lt; 3 &gt;, and Rdn&lt; 1 &gt; that run across the rows. In particular, ramp up line Rup&lt; 0 &gt; is a horizontal line placed across the first row of pixels and adjacent to but insulated from the FD nodes in the first row so the ramp up line is capacitively coupled to these FD nodes. Ramp down line Rdn&lt; 0 &gt; is a horizontal line placed across the second row of pixels and adjacent to but insulated from the FD nodes in the second row so the ramp down line is capacitively coupled to these FD nodes. Ramp up line Rup&lt; 1 &gt; is a horizontal line placed across the third row of pixels and adjacent to but insulated from the FD nodes in the third row so the ramp up line is capacitively coupled to these FD nodes. Ramp down line Rdn&lt; 1 &gt; is a horizontal line placed across the fourth row of pixels and adjacent to but insulated from the FD nodes in the fourth row so the ramp down line is capacitively coupled to these FD nodes. 
         [0051]    From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.