Abstract:
Disclosed is a method for fabricating a semiconductor device capable of preventing a residue from being generated during etching a gate conductive layer and forming a plurality of trenches having an identical width in a substrate. The method includes: selectively etching a substrate by employing tetramethylammoniumhydroxide (TMAH) solution, thereby forming a plurality of trenches of which lateral slopes are gradual; and forming a plurality of gate patterns on the substrate such that each sloped portion of the trenches becomes a part of a channel of the individual gate pattern.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a semiconductor device capable of preventing a residue from being generated during etching a gate conductive layer and forming a plurality of trenches having an identical width in a substrate.  
       DESCRIPTION OF RELATED ARTS  
       [0002]     As a scale of integration of a semiconductor device has increased, a channel length of a transistor has been decreased. If the channel length gets shorter, a short channel effect that a threshold voltage abruptly decreases arises more frequently.  
         [0003]     Accordingly, in order to increase the channel length of a gate, a plurality of trenches are formed in a substrate and a gate pattern is formed on the trenches.  
         [0004]      FIGS. 1A and 1B  are cross-sectional views illustrating a method for fabricating a conventional semiconductor device.  
         [0005]     Referring to  FIG. 1A , a substrate  10  provided with a field oxide layer  11  is selectively subject to a dry etch, thereby forming a plurality of trenches T. At this time, each lateral side of the trenches has a vertical profile.  
         [0006]     Subsequently, as shown in  FIG. 1B , a gate oxide layer  12 , a conductive layer  13  and an insulation layer  14  for a hard mask are sequentially deposited on the substrate  10 . Afterwards, the gate oxide layer  12 , the conductive layer  13  and the insulation layer  14  for the hard mask are patterned, thereby forming a plurality of gate patterns G 1  on an upper portion of the substrate  10  such that the lateral sides of the trenches T become a portion of each gate pattern G 1 .  
         [0007]     During depositing the conductive layer  13 , the conductive layer  13  is deposited with a different thickness in a boundary of portions where the substrate is etched and the substrate is not etched due to height differences between the lateral sides of the trenches  12 . Accordingly, after the conductive layer  13  is etched for forming the gate patterns G 1 , a residue R of the conductive layer  13  remains in the trench region of the boundary of the portions where the substrate is etched and the substrate is not etched. This residue R induces an electric short between interconnection lines of the gate patterns G 1 .  
         [0008]     Furthermore, in order to secure an operation reliability of the semiconductor device, it is required to have a uniform etch selectivity according to a location of the substrate to form a uniform channel length of the gate pattern. In case of performing the dry etch to the substrate without an additional etch stop layer, there may be a problem that a width of the individual trench T gets different since an etched amount of the substrate is different due to the etch selectivity that varies depending on the location of the substrate  
       SUMMARY OF THE INVENTION  
       [0009]     It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device capable of preventing a residue from being generated during etching a gate conductive layer and forming a plurality of trenches having an identical width in a substrate.  
         [0010]     In accordance with one aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: selectively etching a substrate by employing tetramethylammoniumhydroxide (TMAH) solution, thereby forming a plurality of trenches of which lateral slopes are gradual; and forming a plurality of gate patterns on the substrate such that each sloped portion of the trenches becomes a part of a channel of the individual gate pattern. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0012]      FIGS. 1A and 1B  are cross-sectional views illustrating a method for fabricating a conventional semiconductor device; and  
         [0013]      FIGS. 2A  to  2 F are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]     Hereinafter, detailed descriptions on preferred embodiments of the present invention will be provided with reference to the accompanying drawings.  
         [0015]      FIGS. 2A  to  2 F are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.  
         [0016]     Referring to  FIG. 2A , a field oxide layer  21  for a device isolation is formed on a substrate  20 .  
         [0017]     Subsequently, a sacrificial layer  22  for use in a hard mask is formed on the substrate  20 . The sacrificial layer  20  includes an oxide layer, e.g., an aluminum oxide layer, a nitride layer or a tungsten layer.  
         [0018]     Next, a first photoresist pattern  23  for forming a plurality of trenches T is formed on the sacrificial layer  22 .  
         [0019]     As shown in  FIG. 2B , the sacrificial layer  22  is selectively etched by using the first photoresist pattern  23  as an etch mask, thereby forming a mask pattern  22 A.  
         [0020]     Next, as shown in  FIG. 2C , a wet etch employing tetramethylammoniumhydroxide (TMAH) solution is performed with use of the mask pattern  22 A as an etch mask. Thus, a plurality of trenches T with a gradual slope are formed in the substrate  20 .  
         [0021]     At this time, a temperature of the TMAH solution ranges from approximately 50° C. to approximately 100° C. and thus, the TMAH solution has a high selectivity with respect to the mask pattern  22 A and the field oxide layer  21 . Accordingly, the mask pattern  22 A and bottom portions of the field oxide layer  21  are not etched. Thus, a line width of an individual etch pattern, i.e., the individual trench T, is uniformly maintained and an etched amount is uniform with regardless of a location of the substrate  20 .  
         [0022]     Herein, before or after the wet etch for forming the plurality of trenches T is performed, one more step of performing a dry etch to a portion where the plurality of trenches T are formed in the substrate  20  by using a gas selected from a group consisting of oxygen (O 2 ), argon (Ar), C x F x , N x F x  and chlorine (Cl 2 ) can be included in order to control the slope of the individual etch pattern.  
         [0023]     Subsequently, as shown in  FIG. 2D , the mask pattern  22 A formed on the substrate  20  is removed. In case of forming the mask pattern  22 A with use of an oxide layer, the mask pattern  22 A is removed through a wet etch employing buffered oxide etchant (BOE) solution or hydrogen fluoride (HF) solution, or a dry etch employing a gas selected from a group consisting of C x F x , NF x  SF x .  
         [0024]     In case of forming the mask pattern  22 A with use of a nitride layer, the mask pattern  22 A is removed through a wet etch employing phosphate (H 2 PO 4 ) solution maintained at a temperature ranging from approximately 150° C. to approximately 200° C. or a dry etch employing a gas selected from a group consisting of C x F x , NF x  and SF x .  
         [0025]     In case of forming the mask pattern  22 A with use of a tungsten layer, the mask pattern  22 A is removed through a wet etch employing a standard clean (SC)-1 solution, i.e., a solution obtained by mixing ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and deonized water (H 2 O), maintained at a temperature ranging form approximately 50° C. to approximately 80° C. or a dry etch employing a gas selected from a group consisting of Cl 2 , boron trichloride (BCl 3 ), C x F x , NF x  and SF x .  
         [0026]     Subsequently, as shown in  FIG. 2E , a gate oxide layer  24 , a conductive layer  25  and an insulation layer  26  for use in a hard mask are sequentially formed on the substrate  20 . The conductive layer  25  is formed by using a material selected from a group consisting of WSi x , W, Co x Si x , Ti x Si x  and a family of polysilicon. Also, the conductive layer  27  can be formed in a stack structure by stacking at least two materials among the aforementioned materials.  
         [0027]     Subsequently, a second photoresist pattern  27  is formed on the insulation layer  26 .  
         [0028]     Next, as shown in  FIG. 2F , the insulation layer  26  is selectively etched by using the second photoresist pattern  27  as an etch mask and afterwards, the second photoresist pattern  27  is removed. Subsequently, the conductive layer  25  is etched by using the etched insulation layer  26  as the etch mask, thereby forming a plurality of gate patterns G 2 . Despite the fact that the gate patterns G 2  are not properly arranged in the etched substrate  20 , it is still possible to prevent a residue from remaining on the conductive layer  25  in an etched region during etching the conductive layer  25  since the gate patterns G 2  are formed on the substrate  20  with a gradual slope.  
         [0029]     In case of forming the conductive layer  25  in a stack structure by stacking a top layer including at least more than one of WSix, W, Co x Si x  and Ti x Si x , and a bottom layer based on polysilicon, the top layer is etched through using a high density plasma etch apparatus such as an inductively coupled plasma (ICP) type etch apparatus, a decoupled plasma source (DPS) type etch apparatus and an electron cyclotron resonance (ECR) type etch apparatus. Particularly, the top layer is etched by using at least one gas selected from a group consisting of BCl 3 , C x F x , NF x  and SF x  with an amount ranging from approximately 10 sccm to approximately 50 sccm, a Cl 2  gas with an amount ranging from approximately 50 sccm to approximately 200 sccm or a mixed gas thereof.  
         [0030]     Herein, in case of employing the ICP type etch apparatus or the DPS type etch apparatus, the etching process is performed by using a source power ranging from approximately 500 W to approximately 2,000 W and adding more than one gas selected from a group consisting of O 2  gas with an amount ranging from approximately 1 sccm to approximately 20 sccm, nitrogen (N 2 ) gas with an amount ranging from approximately 1 sccm to approximately 100 sccm, Ar gas with an amount ranging from approximately 50 sccm to approximately 200 sccm and helium (He) ranging from approximately 5 sccm to approximately 200 sccm in order to obtain the vertical etch profile.  
         [0031]     In case of using the ECR type apparatus, the etching process is performed by using a microwave power ranging from approximately 1,000 W to approximately 3,000 W and adding more than one selected from a group consisting of O 2  gas with an amount ranging from approximately 1 sccm to approximately 20 sccm, N 2  gas with an amount ranging from approximately 1 sccm to approximately 100 sccm, Ar gas with an amount ranging from approximately 50 sccm to approximately 200 sccm and He with an amount ranging from approximately 5 sccm to approximately 200 sccm in order to obtain the vertical etch profile.  
         [0032]     The bottom layer is etched without causing any loss of the top layer and the gate oxide layer  24  by using a plasma to which hydrogen bromide (HBr) and O 2  gases are added at the high density plasma etch apparatus such as the ICP type etch apparatus, the DPS type etch apparatus and the ECR type etch apparatus.  
         [0033]     Herein, in case of using the ICP type etch apparatus or the DPS etch apparatus, the etching process is performed by using a source power with an amount ranging from approximately 500 W to approximately 2,000 W and adding at least one gas selected from approximately 50 sccm to approximately 200 sccm of the HBr gas and approximately 2 sccm to approximately 20 sccm of the O 2  gas.  
         [0034]     Furthermore, in case of the ECR type etch apparatus, the etching process is performed by using a microwave power ranging from approximately 1,000 W to approximately 3,000 W and a gas selected from approximately 50 sccm to approximately 200 sccm of the HBr gas and approximately 2 sccm to 20 sccm of the O 2  gas or a mixed gas thereof.  
         [0035]     As described above, the plurality of trenches with the gradual slope are formed through performing the wet etch employing the TMAH solution on the substrate. Accordingly, it is possible to eliminate the residue generation during etching the conductive layer for forming the gate patterns since the thickness of the conductive layer decreases in proportion to a level of the decrease in the height of the lateral sides of the trenches. Furthermore, it is also possible to obtain the etched amount of the substrate uniform regardless of the location of the substrate.  
         [0036]     In accordance with the present invention, the plurality of trenches with the gradual slop are formed through the wet etch employing the TMAH solution. Accordingly, the residue of the conductive layer is removed and the width of the individual trench becomes uniform throughout the substrate.  
         [0037]     The present application contains subject matter related to the Korean patent application No. KR 2004-0087700, filed in the Korean Patent Office on Oct. 30, 2004, the entire contents of which being incorporated herein by reference.  
         [0038]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.