Abstract:
A coding system for data and a demultiplexer and decoder forming an interface for a computer is disclosed. Both are improvements upon the system disclosed and claims in U.S. Pat. No. 4,188,581 of this inventor. Improvements include the use of a RC differentiator in combination with a diode for introducing coded data into a reflective terminated tapped delay line. Data is coded in the form of the time duration between two successive pulses in discrete increments. One feature involves the use of the second of two pulses to define the end of one character and the beginning of the next character. Multiple code banks allow a variety of data rates.

Description:
REFERENCE TO RELATED PATENT AND APPLICATIONS 
     This is an improvement on the system of U.S. Pat. No. 4,188,581 a copy of which is attached hereto and incorporated on its entirety by reference. 
     This application is a non provisional application based upon Provisional Patent Application 60/074,267 filed Feb. 10, 1998 the benefit of which is claimed. 
    
    
     BACKGROUND OF THE INVENTION 
     The synchronous methods presently employed in data communications generally and in particular computer communications are under the control of a clock generator or timer. Evasive means are employed in countering interference which is major concern. High-speed computer systems have their upper limits set on performance but their potential is impeded by delays. This is due in part to the necessity of binary coding of alphanumerics. To transmit, receive, store, decode and convert a long train of bits, includes the problems of framing, synchronization, debugging and parity check (all associated with the present synchronous systems). These problems relating to efficiency and control remain unsolved. 
     The development of reliable communications have been retarded to a large extend by different forms of interference. Present systems rely mainly on evasive means of countering interference. Added circuitry and component parts represent further delays and the evasive methods used are not always an acceptable alternative. 
     The number of central processing units (CPU&#39;s) being manufactured continues to increase and many are different and incompatible with each other. This effects an area of technology which would otherwise support portability and compatibility of encoded data. 
     The communication link between computer systems must be provided with an interface which will provide all systems portability and data exchange compatibility with efficiency and control at the highest degree, free from all extraneous signal interference. 
     This document describes the concepts developed for such an interface. Included are character and digit coded logic (universal language codes). 
     Several different attempts have been tried to produce asynchronous data transmission systems in which each character is encoded as a single waveform or pulse duration 
     Prior Art 
     U.S. Pat. No. 4,584,691 Herr Apr. 22, 1986 
     Pulse length modulation system in which detection is accomplished by gating a stable local oscillator and detecting the character or numeral using a cycle counter for the local oscillator. 
     U.S. Pat. No. 5,661,758 M. E. Long Aug. 26, 1997 
     The patent discloses a method of encoding in which distinct disruptions are selected for each character of data and introduced on a carrier. The start time and duration of the disruption represent the character encoded. 
     U.S. Pat. No. 5,588,023 K. F. Ho Dec. 24, 1996 
     A system for transmitting data employing half cycle wavelength. Information is carried in the duration of the wavelength. A wave duration circuit is disclosed in FIG. 111 as employing a switch, a flip flop, a decoder, a 15 bit counter and a 16 bit latch. And active differentiator is disclosed in FIG. 14. The foregoing prior art issued since U.S. Pat. No. 4,188,581 of this invention recognizes the value of one unique pulse or waveform per pulse as an efficient form of data transmission. A schematic of the sensor (outlined) and a proposed schematic for the “active” section are shown. 
     BRIEF DESCRIPTION OF THE INVENTION 
     This is an improvement upon the Signaling System of the U.S. Pat. No. 4,188,581 of this inventor issued Feb. 12, 1980 and involves the design and features of a new computer interface based upon this prior patent. A copy thereof is attached hereto and is incorporated in its entirety by reference. Universal language codes and formulas developed to eliminate any ambiguous readouts are likewise disclosed. The measurements obtained from pulse parameters and the method used for detection are described. 
     The computer interface was designed primarily for asynchronous pulse code modulation. Pulses received as applied to the interface are rectified and of fixed duration and are sequenced in time, thereby providing the various elements of information required. 
     Unlike pulse width and pulse duration modulation where each has only one parameter measurement, in pulse code modulation there are three measurements per character, each character being different. Amplitude is not a parameter of concern. For a more complete understanding of pulse code modulation reference should be made to Oppenheimer and Willsky, Published by Prentice Hall, Inc. SIGNALS AND SYSTEMS©1997. 
     The method of coding and decoding alphanumerics expands the interface systems range with a “bank of codes” vocabulary. There are five Banks of Codes. Code Bank#1, for example has 23 individual codes lettered “A” through “W”. Each code increases in number and digit length, extending from common Binary to the 46 th  character of the Fortran IV code of alphanumerics. 
     The 23 codes marked “A” through “W” can be combined into a series of 621 single digit byte instructions by switching from one code to another, or codes can be selected individually by the number of instructions required. 
     The receiving system of this invention typically includes an input stage such as a receiving antenna input device, followed by an asynchronous wide-band receiver in which output is heterodyned through a down converter by a stabilized oscillator. The output of the converter is applied to a wide-bank I.F. (intermediate frequency) amplifier and precedes to an envelope detector for rectification. 
     A data acquisition sensor section of the computer interface is basically passive and solid state having linear characteristics. It is capable of use with either low or high level signals and requires no synchronization. 
     A highly selective anti jamming demultiplexer is also disclosed which is an improvement of the system of U.S. Pat. No. 4,188,581 of R. A. Stevenson. The code demultiplexer is also designed for counter measures as an anti-jam device. 
     A demultiplexer is employed including a transmission line which is terminated in a reflective termination. The transmission line has a plurality of taps, each related in position to detect a particular alphanumerica encoded pulse. Each tap is spaced from the termination distance related to one half of a discrete pulse length in terms of its propagation rate down the medium. Diodes are associated with each tap and are connected to the logic gates for the system. For the Code Bank#1, the total length of the line is 120 nanoseconds, which allows for detection of pulse lengths from 10 N/Sec. to 240 N/Sec. 
     The improvements to the demultiplexer of this invention over U.S. Pat. No. 4,188,581, include: 
     1. the presence a differentiator circuit; and 
     2. A high speed diode—D 1 . 
     The differeniator circuit consists of a network of resistors and a capacitor, followed by a high-speed diode. The diode is forward biased by the positive leading edge of the differentiated pulse and conducts. The diode is reversed biased by the negative trailing edge of the same pulse and acts as a very high impedance or open circuit gate, thereby preventing any premature triggering of following logic gates where negative signals might exceed the logic gate thresholds. The prior art is believed to lack this feature and result. 
     The positive leading edge of the differentiated pulse and the trailing open circuit gate conduct down the demultiplexer line towards the low impedance ground. Upon reaching ground, the positive leading edge reverses polarity and direction. This negative reflective signal and the incident pulse open circuit gate, each traveling at approximately the speed of light, pass the demultiplexer tap simultaneously, from opposite directions, providing an output pulse with a approximately 50% reduction in duration, rise time and fall time, denoting a detected character. 
     As shown in the drawings to follow, the demultiplexer taps marked “A” through “W” are the START pulses and represent the 23 individual codes in the code bank. Each START pulse is used to identify the code to be processed and may also provide spacing for bytes and words, and provide synchronization to computer subsystems. 
     Following the START pulses is the data from the tap marked “A” (“A prime”). For Code Bank#1 the data pulses are of a fixed duration, e.g. increments of 10 N/Sec., and in one embodiment are spaced apart in time representing the various characters in the code. The taps constitute the detection point for the first and second parameters of each character and represent the measurement of duration of a first and second pulse representing each character. 
     The signals detected at each tap are transferred to a decoder, where each character is detected by the measurement of a third parameter. Parameter  3  is the time measurement between the parameters  1  and  2 . The start and the signals detected from the third measurements are transferred through the logic gates and data bus to the computer for conversion into machine code, storage and processing. 
     In a second embodiment there is no space between characters unless installed as described above. The detected trailing edge of the first pulse is the beginning of the first character, the trailing edge of the second pulse is the end of the first character and the beginning of the second character. The trailing edge of the third pulse is the end of the second character and the beginning of the third character, etc. 
     Character recognition is accomplished when the leading parameter  1  of one signal is present at a logic gate tap at the same instant that a parameter  2  signal is at the decoder input. When this occurs, both signals add in amplitude. The parameter one signal at the logic gate tap will exceed the logic gate threshold sending a signal through the data bus to the computer for storage, conversion and processing. 
     Following the start pulse is the data from the tap marked “A” (“A prime”). For Code Bank#1 the data pulses are of fixed 10 N/Sec. difference in durations and thus are spaced apart in time representing the various characters in the code. Point “A” is the detection point for the first and second parameters of each character and represent the measurement of duration of a first and second pulse representing each character. 
     In addition to the coding scheme for information, the system for receiving and decoding information as described above and in more detail below is believed to constitute a truly novel data receiver and decoder. 
     The system by reason of the coding employed and the detection and decoding features make them both immune to pulse jamming. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention may be more clearly understood with the following detailed description and by reference to the drawings of Section I of this provisional application in which: 
     FIG. 1 is data code bank showing the relative time delays for different characters in single pulse coding or for use in hexidecimal, octal, or Fortran format as used in this invention. 
     FIG. 2 is a schematic diagram of the decoder data port for use with code banks such as the code bank of FIG. 1; 
     FIGS. 2A,  2 B and  2 C are an enlarged schematic diagram of an alternate form of decoder integrated into a data decoding subsystem; 
     FIG. 3 is a simplified block diagram of an RF data receiving system for representing a typical source of data coded in accordance with this invention; 
     FIG. 4 is an electrical schematic diagram of the code demultiplexer, logic gates and delay line utilized in this invention; 
     FIG. 5 is a block diagram of a typical data utilization system which can benefit by this invention; 
     FIG. 6 is a layout diagram for FIGS. 1-5; 
     FIG. 7 is a time line representation of signals as they appear in the system of FIGS. 1-4; 
     FIG. 8 is a data time line graphical representation of signals in accordance with this invention in the presence of a long duration jamming pulse interference; 
     FIG. 9 is a time line corresponding to FIG. 8 after differentiation; 
     FIG. 10 is a circuit diagram of a single detector of the demultiplexer of FIG. 4; 
     FIG. 11 is a time line showing the data output of the detector of FIG. 10; 
     FIG. 12 is a logic network diagram employing and gates and delay units for demultiplexing data in accordance with this invention of FIGS. 1-5; 
     FIG. 13 is a logic diagram for the demultiplexer of FIG. 12; 
     FIG. 14 is a truth table for the demultiplexer of FIG. 4; 
     FIG. 15 is a time line of the output of the demultiplexer of FIG. 4; 
     FIG. 16 is a time line diagram of the output of decoder of FIG. 2; 
     FIGS. 17 through 21 are five different code banks, each with different standard time duration for different characters; 
     FIGS. 22A and 22B are tabular comparisons of the operating characteristics of an embodiment of this invention with an industry standard high-speed computer; and 
     FIG. 23 is a reproduction of photograph of a prototype illustrative of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1-4 illustrate the new computer interface of this invention. Universal language codes and formulas developed and used in the interface, eliminate any ambiguous readouts. The measurements obtained from pulse parameters and the method used for the detection of alphanumerics are also disclosed. 
     The method of coding and decoding alphamunerics expands the interface systems range with a bank of codes vocabulary. There are five banks of codes, one of which, Code Bank#1, shown in FIG. 1 includes individual codes lettered “A” through “W”. Each code increases in number and digit length, extending from common binary to the 46 th  character of the Fortran IV code of alphanumerics. The 23 codes marked “A” through “W” can be combined into a series of 621 single digit byte instructions by switching from one code to another, or codes can be selected individually by the number of instructions required. These codes are selectively inputted to a decoder  40  at FIG.  20 . Other banks of codes are described below in connection with FIGS. 17-21. 
     The receiving system shown in FIG.  3  and generally designated  10  typically includes receiving antenna  11 , followed by an asynchronous wide-bank receiver  12 , in which output is heterodyned through a down convertor  13 , by a stabilized oscillator  14 . The output of the convertor  13  is applied to a wide-band I.F. (intermediate frequency) amplifier  15 , and precedes to an envelope detector  16  for rectification. 
     A data acquisition sensor section  20  of the computer interface shown in FIGS. of  3  and  4 , is basically passive and solid-state having linear characteristics. It is capable of use with either low or high level signals and requires no synchronization. 
     The code demultiplexer of FIG. 4 was first designed for countermeasures as an anti jam device for radar, missile guidance and communication system applications but has now been discovered to have even greater utility in computer interface applications. 
     The demultiplexer  21  employs a transmission line  22  which is terminated in a reflective termination. The transmission line  22  has a plurality of taps  22 T, each related in position to detect a particular alphanumeric encoded pulse. Each tap  22 T is spaced from the termination by a distance related to one half of a discrete pulse length in terms of its propagation rate down the medium e.g. 5 nsec. Diodes  23 D are associated with each tap and are connected to the logic gates  24  for the system. For the Code Bank#1 of FIG. 1, the total length of the line  40  is 120 nanoseconds, which allows the detection of pulse length differences from 10 N/S to 240 N/Sec. 
     The most notable improvements of this system as compared with the demultiplexer of FIG. 3, U.S. Pat. No. 4,188,581 include: 
     1. A DIFFERENTIATOR circuit  30 ; 
     2. A HIGH SPEED DIODE—D 1 . 
     The differentiator circuit  30  consists of shunt resistors R 1 , R 2  and a series capacitor C 1 . Following the differentiator circuit  30  is a high-speed diode D 1 . The values R 1 , R 2  and C are selected to provide the sharp spike wave form shown in FIG. 4 next to resistor R 2 . The diode D 1  is forward biased by the positive leading edge of the differentiated pulse and conducts. The diode D 1  is reversed biased by the negative trailing edge and acts as a very high impedance or open circuit gate, thereby preventing any premature triggering of the logic gates  24  where negative signals might exceed the logic gate  24  thresholds. 
     The positive leading edge of the differentiated pulse and the trailing open circuit gate conduct down the demultiplexer line  22  towards the low impedance ground. Upon reaching ground, the positive leading edge reverses polarity and direction. This negative reflected signal and the incident pulse, each traveling at approximately the speed of light, pass the correct code demultiplexer tap  22 T simultaneously from opposite directions, providing and output pulse with a 50% reduction in duration and rise and fall-time at the corresponding tap  22 T. 
     As shown in the drawing of FIG. 1, the code demultiplexer taps marked “A” through “W” are the start pulses and represent the 23 individual code in the code-bank. Each start pulse is used to identify the code to be processed and may also provide spacing for bytes and words, and provide synchronization to the computer sub-system  50  of FIG.  5 . 
     Following the START pulse are the data marked “A” (“A prime”). For Code Bank#1 of FIG. 1, the data pulses are of a fixed 10 N/Sec. difference in durations and are spaced apart in time representing the various characters in the code. Point “A” of FIG. 4 is the detection point for the first and second parameters of each character and represents the measurement of duration of a first and second pulse representing each character. 
     The signals detected from “A” are transferred to the decoder  40  of FIG. 2, where each character is detected by the measurement of a third parameter. Parameter  3  is the time measurement between the detected parameters  1  and  2 . 
     There is no space between characters unless installed as described above in the preceding paragraph. The trailing edge of the first pulse, detected at “A”, is the beginning of the first character, the trailing edge of the second pulse is the end of the first character and the beginning of the second character, the trailing edge of the third pulse is the end of the second character and the beginning of the third character, etc. 
     The following is in reference to Code “A” of Code Bank#1, shown in FIG.  1 . From the input of the decoder  40  to the first tap is 25 N/Sec., representing the first character in Code A. All decoder taps  40 T which follows are equally spaced 10 N/Sec. The second character of the data bank will include the time 25 N/Sec. of the first character plus 10 N/Sec. equaling 35 N/Sec. The third character will include the time of the second character plus 10 N/Sec. equaling 45 N/Sec., etc. 
     Character recognition is accomplished when the leading parameter  1  signal is present at a logic gate tap  24 T at the same instant that a parameter  2  signal is at the decoder  40  input. When this occurs, both signals will add together in amplitude. The parameter  3  signal at the logic gate tap  40 T will exceed the logic gate threshold, sending a signal through the data bus  41  to the computer  50  of FIG. 5 via peripherals and a communications processor and encriptor, which may be associated with the computer  50  for storage, conversion and processing. 
     Each code in the code-banks  1  through  5  may be tested for any ambiguous readouts as follows: Add any unlike measurements together, double and triple any character lengths, if the total lengths are within the code, this measurement will be evenly spaced between two logic gates. If the measurement is beyond the longest character length, then it is of no consequence. 
     ALTERNATIVE DECODER SUBSYSTEM 
     To illustrate now this coding system invention maybe utilized in combination with the features of U.S. Pat. No. 4,188,581, reference is hereby noted to FIGS. 2A-C. This diagram shows the patented system designated in FIG. 2A as the input to a decoder made up of the entire FIGS. 2A-C. The output of system  1  is introduced into a variable delay  5  to provide a delayed incoming signal to point C at the input to the decoder tapped delaying of FIG.  2 B. This tapped delay line has a START/STOP incremental delay of 25 n/sec and an incremental character delay of 10 n/sec, followed by a second bank of delay sections appearing on FIG.  2 C. 
     The input from system  1  is also introduced through a logic controlled switch  2 . Upon coincidence of inputs B &amp; D to AND Gate  7 , the AND gate  7  output, after the delay controlled by variable delay  6 , operate the switch  2  triggering pulse generator  3 . The pulse generator  3  provides an input signal to a second &#39;581 patented system  4 . The output of system  4  at point B is introduced into delay line B-D having a START/STOP incremental delay of 50 n/sec and incremental character delay of 20 n/sec per character and per tap. 
     The second tapped delay line of FIG. 2C has a START/STOP incremental delay of 50 n/sec and a character incremental delay of 20 n/sec. Coincidence of the three delayed signals after a START signal constitutes a valid character which is passed to the output. Coincidence is detailed by one of the banks of AND gates of FIG.  2 B. Upon coincidence the character detected in sequence constitutes the output of FIG.  2 A. 
     JAMMING AND INTERFERENCE PROTECTION 
     The timeline of FIG. 7 illustrates the time sequence relationship between the rectified output from receiver  10  of FIG. 3 in time sequence with the differentiator  30  and diode D 1  output, both of FIG.  4 . It should be noted that after the differentiator  30  all pulses including the start pulse appear as sharp spikes followed by a negative spike. After the diode D 1  only the positive spikes remain. The information contained in the pulse train is contained only in the two successive pulses and their time differential in predetermined increments. Thus white noise will not meet these criteria. 
     FIGS. 8 and 9 represent the output of the system of this invention in the presence of interference in the form of a long jamming pulse, which is present during data transmission. The data transmitted as well as the interfering pulse is differentiated as shown in FIG. 9 as having a common base line. 
     It should be noted that the integrity of timing and data content is not lost owing to the presence of the jamming pulse. To interfere, the jamming pulse would necessarily need to coincide in rise and fall time with the time duration of a valid digit and correspond in start time with one of the valid data pulses. If such coincidence occurs, a single digit would be lost from the data transmitted. 
     SINGLE STAGE DETECTOR 
     FIGS. 10 and 11 represent in simplified form a single detector  60  of the demultiplexer  21  including a delay line section  61  and diode  62  designed to detect each differentiated data pulse for demultiplexing. In the example given in FIGS. 10 and 1, the length of each valid data pulse is 6 n. sec. In FIG. 11, the data output from the detector of FIG. 10 consists of a coincidence signal between the differentiated negative leading edge and the data pulse positive trailing edge. 
     FIG. 12 represents a series of delay units  70  for demultiplexing data in combination with AND gates  71  at the output stage. The truth table of a single AND gate  71  appears in FIG.  13  and the truth table for the entire output array of outputs  1 - 11  along with the input appears in FIG.  14 . 
     The output bus timeline for the demultiplexer  21  appears in FIG. 15 while the time line for the decoder  40  of FIG. 2 is shown in FIG.  16 . 
     FIGS. 17 through 21 show five different code banks, each with a different time interval between characters. The time intervals are as follows: 
     
       
         
               
               
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 Code bank #1 
                 FIG. 17 
                 10 
                 nsec. 
               
               
                   
                 Code bank #2 
                 FIG. 18 
                 8 
                 nsec. 
               
               
                   
                 Code bank #3 
                 FIG. 19 
                 6 
                 nsec. 
               
               
                   
                 Code bank #4 
                 FIG. 20 
                 4 
                 nsec. 
               
               
                   
                 Code bank #5 
                 FIG. 21 
                 2 
                 nsec. 
               
               
                   
                   
               
             
          
         
       
     
     FIGS. 22A and 22B are a comparison of several significant parameters of a well-known standard high speed, highly respected computer as compared with a computer system incorporating this invention. 
     FIG. 23 is an experimental circuit board used to verify the operativeness of this invention. 
     ADVANTAGES OF THIS INVENTION 
     This system includes: 
     1. No input clocking network. (Asynchronous Detection) 
     2. No external cooling support equipment required. One Bit to process One character means far less circuitry and power required. 
     3. Ability to send and receive the Fortran IV alphabet, via burst transmission. 
     4. 3-4 times faster and greater capacity than available high-speed computer systems. 
     5. Up to sixteen times greater memory capacity using the same type of storage modules and disk drives. (One bit to process one character.) 
     6. No synchronization to send and receive data. 
     7. Ability to send data at a very high or low rate, asynchronously. 
     8. Less chance for programming errors. 
     9. RANGE: 5,000,000.00 to 400,000,000.00 bits per second and higher depending on the practicality of the application. 
     10. Immunity from most pulse jamming. 
     11. Relatively simple stable solid state compounds used. 
     12. Improved immunity form white noise jamming 
     The above described embodiments of the present invention are merely descriptive of its principles and are not to be considered limiting. The scope of the present invention instead shall be determined from the scope of the following claims including their equivalents.