Abstract:
Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 12/821,243, entitled “UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE”, filed Jun. 23, 2010, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     This invention relates generally to processor input/output (I/O) interfacing within a computing environment, and more particularly to upbound processing of I/O expansion requests and responses over a PCIe bus and switch architecture. 
     PCIe is a component level interconnect standard that defines a bi-directional communication protocol for transactions between I/O adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission on a PCIe bus. Packets originating at I/O adapters and ending at host systems are referred to as upbound packets. Packets originating at host systems and terminating at I/O adapters are referred to as downbound packets. PCIe transactions include a request packet and, if required, a completion packet (also referred to herein as a “response packet”) in the opposite direction. The PCIe topology is based on point-to-point unidirectional links that are paired (e.g., one upbound link, one downbound link) to form the PCIe bus. The PCIe standard is maintained and published by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). 
     One drawback to the use of PCIe is that all I/O adapters connected to a PCIe bus are required to operate within the parameters defined in the PCIe standard (i.e., they are PCIe compatible I/O adapters). The PCIe standard sets rigid constraints on requests and, completions and on packet packaging and addressing. In some system architectures, for example the IBM® System z® architecture, there is a need to be able to support communications over a PCIe bus between I/O adapters and host systems using transactions that are not supported by the PCIe standard. An example is the ability to communicate with non-PCIe compatible adapters (e.g., I/O expansion adapters), which are typically supporting legacy systems and applications that may be difficult (due, for example to technology issues and/or expense) to convert into the PCIe standard. Thus, while PCIe is suitable for its intended purpose of communicating with PCIe compatible adapters, there remains a need for expanding this capability to allow PCIe to communicate with non-PCIe compatible adapters to support legacy systems. 
     BRIEF SUMMARY 
     A method for implementing non-standard I/O adapters in a standardized I/O architecture, the method comprising initiating a first request to perform an operation on a host system at an I/O adapter, the I/O adapter communicating in a first protocol, the first request formatted for the first protocol and comprising data required to process the first request and creating a second request responsive to the first request, the second request comprising a header and formatted according to a second protocol, the second protocol supported by an I/O bus, and the creating comprising storing the data required to process the first request in the header of the second request. The method further comprising sending the second request to a host system via the I/O bus. 
     A method for implementing non-standard I/O adapters in a standardized I/O architecture, the method comprising receiving a request from a requester to perform an operation on an I/O adapter, the requester requiring a completion status, performing the operation resulting in a response, the response comprising the completion status, generating a new request in response to the performing, the new request in a format supported by an I/O bus, and modifying the header of the new request to include the response. The method further comprising sending the new request as the completion status to the requester via the I/O bus. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
         FIG. 1  depicts a block diagram of a computer system that may be implemented in an exemplary embodiment; 
         FIG. 2   a  depicts a block diagram of a standard Peripheral Component Interconnect Express (PCIe) request header; 
         FIG. 2   b  depicts a block diagram of a standard PCIe completion header; 
         FIG. 3  depicts a block diagram of an exemplary embodiment of input/output (I/O) expansion logic for downbound request and completion processing; 
         FIG. 4  depicts a block diagram of an exemplary embodiment of I/O expansion logic for upbound request and completion processing; 
         FIG. 5  depicts a process flow of an exemplary embodiment of I/O expansion logic for processing an upbound request; 
         FIG. 6  depicts block diagram of a transformed PCIe request header that may be implemented by an exemplary embodiment; 
         FIG. 7  depicts a process flow of an exemplary embodiment of I/O expansion logic for processing a upbound response; and 
         FIG. 8  depicts a block diagram of an exemplary embodiment of a transformed PCIe request header containing an I/O expansion response. 
     
    
    
     DETAILED DESCRIPTION 
     An exemplary embodiment of the present invention provides for processing of input/output (I/O) expansion requests and responses in a Peripheral Component Interconnect Express (PCIe) architecture without requiring modification of the PCIe bus and PCIe switch infrastructure. 
       FIG. 1  depicts a computer system  100  that may be implemented by an exemplary embodiment of the present invention. In an embodiment, the computer system  100  is a System z® server offered by International Business Machines Corporation (IBM®). System z is based on the z/Architecture® offered by IBM. Details regarding the z/Architecture are described in an IBM publication entitled, “z/Architecture Principles of Operation,” IBM Publication No. SA22-7832-07, February 2009, which is hereby incorporated herein by reference in its entirety. 
     In an exemplary embodiment, computer system  100  includes one or more central processing units (CPUs)  102  coupled to a system memory  104  via a memory controller  106 . System memory  104  is accessed when a CPU  102 , PCIe adapter  110 , or I/O expansion adapter  111  issues a memory request (read or write) that includes an address used to access the system memory  104 . The address included in the memory request is typically not directly usable to access system memory  104 , and therefore, it requires translation to an address that is directly usable in accessing system memory  104 . In an embodiment, the address is translated via an address translation mechanism (ATM)  108 . In an embodiment, the ATM  108  translates the address from a virtual address to a real or absolute address using, for example, dynamic address translation (DAT). 
     The memory request, including the translated address, is received by the memory controller  106 . In an embodiment, the memory controller  106  maintains consistency in the system memory  104  and arbitrates between requests for access to the system memory  104  from hardware and software components including, but not limited to, the CPUs  102 , the PCIe adapters  110 , and the I/O expansion adapters  111  known collectively as I/O adapters. 
     In an exemplary embodiment, the PCIe adapters  110  perform one or more PCIe I/O functions; and the I/O expansion adapters  111  are not PCIe compatible and perform one or more non-PCIe I/O functions. A memory request that is sent from one of the CPUs  102  to the PCIe adapters  110  or the I/O expansion adapters  111  (i.e., a downbound memory request) is first routed to an I/O hub  112  (e.g., a PCIe hub), which is connected to a PCIe bus  126  (also described herein as an I/O bus). The memory request is then sent from the PCIe bus  126  to one of the PCIe adapters  110  or to one of the I/O expansion adapters  111  via one or more PCIe switches  114 . The PCIe bus  126  and PCIe switches  114  communicate in a standard PCIe format (or protocol) as is known in the art. 
     In an exemplary embodiment, the I/O hub  112  includes one or more state machines, and I/O expansion logic  122  for interpreting and transmitting I/O expansion operations, bi-directionally, between the host system  124  and the I/O expansion adapters  111 . The host system  124  transmits requests to the I/O expansion adapters  111  in a format supported by the I/O expansion adapters  111  but incompatible (i.e. not supported) by the PCIe bus  126  and the PCIe switches  114 . The I/O expansion logic  122  receives requests and responses from the host system  124  via the host bus  120  and transforms them into a format supported by the PCIe bus  126 . As depicted in  FIG. 1 , the I/O expansion logic  122  includes both downbound expansion logic  128  and upbound expansion logic  130  which are shown as separate logic blocks, however portions or all of the logic within these blocks may overlap. The I/O hub  112  depicted in  FIG. 1  also includes a root complex  116  that receives request and completions from one of the PCIe switches  114 . Memory requests include an I/O address that may need to be translated, and thus, the I/O Hub  112  provides the address to an address translation and protection unit (ATP unit)  118 . The ATP unit  118  is used to translate, if needed, the I/O address into to an address directly usable to access system memory  104 . 
     An upbound memory request initiated from one of the PCIe adapters  110  or I/O expansion adapters  111 , including the address (translated or initial address, if translation is not needed), is provided to the memory controller  106  via, for instance, the host bus  120 . The memory controller  106  performs arbitration and forwards the memory request with the address to the system memory  104  at the appropriate time to the system memory  104 . 
     In an exemplary embodiment, a memory request is initiated by one of the PCIe adapters  110 , by one of the I/O expansion adapters  111 , or by the host system  124 . In an exemplary embodiment, there are two types of memory requests, posted requests and non-posted requests. Non-posted requests (e.g. memory reads) return a response called a completion that contains the requested data and information related to the status of the result of processing the associated memory request as will be described in more detail below. Posted transactions (e.g. memory writes) are similar to non-posted transactions except that the data is the payload and posted transactions do not return a completion packet. Therefore, any error that occurs during the posted transaction will be unknown to the requester. Both posted and non-posted requests flow through the PCIe infrastructure based on address information contained in their headers as will be described in more detail below. 
     While PCI defines only Memory Read and Posted Memory Write requests from the PCIe adapters  110  to the root complex  116 , System z uses several higher function requests not defined by the PCI specification. All of these requests are various types of atomic requests used for locking protocols and bit manipulation. 
     One request is called Test and Set. This request operates like a memory read and includes a lock byte and a memory address. If the first byte of the target address (8 byte aligned) is zero, the lock byte is written into this first byte. The target data, up to 256 bytes in this implementation, is returned to the requester. A second request is called Test and Store. This request operates like a Memory Write with a payload of up to 256 bytes in this implementation. It differs from a Memory Write in that the first byte of the payload is used as a lock byte. If the first byte in the target address is zero, the payload is written into the target address. If the first byte in the target address is not zero, the payload is not written into the target address, and a response is generated indicating that the first target byte was not zero. 
     Three other requests manipulate bits in memory and one also causes an interruption. All three operate like Memory Write requests, and all three include a mask to indicate which target bits should be set or reset. In this implementation, the mask is 8 bytes. The Set Bit Request sets bits indicated by the mask at the target in memory. The Reset Bit Request resets bits indicated by the mask at the target memory. The Set Bit with Interrupt Request first sets bits indicated by the mask at the target in memory and then causes an interruption to the host processor. 
     Turning now to  FIGS. 2   a  and  2   b , a standard PCIe request and completion header will be described. A typical PCIe memory request includes a header, and if the request is a write, it also includes payload data. A typical PCIe memory completion for a read request includes a header and payload data. The standard PCIe request header  200  comprises a plurality of fields. As shown in the embodiment in  FIG. 2   a , the first 4 bytes  202  of the standard 64 bit address PCIe request header  200  includes 8 reserved bits indicated by “R,” a format field describing the address length (32 or 64 bits) and whether the packet is a request or completion, a traffic class field (“TC”), a transaction layer packet digest (“TD”), a poison bit (“EP”), attributes (“Attr”), address type (AT), length in 4 byte increments, a requester ID  204  and a tag field  210  which together comprise the transaction ID, and last and first doubleword byte enables (Last DW BE and 1st DW BE). The requester ID field  204  includes information used by the routing mechanisms of the computer system  100  to identify the source of the request and to route a response, if provided, to the requester. The address field ( 206  and  208 ) comprises a set of high order bits  206  and a set of low order bits  208 . Taken together the address field ( 206  and  208 ) indicates either the address of the PCIe adapter  110  or I/O expansion adapter  111  to which the request is directed for a downbound transaction, or the system memory address of the system memory  104  for an upbound transaction. 
     The completion packet generally comprises a header and payload (not shown) segment.  FIG. 2   b  depicts a standard PCIe completion header  250 . The first bytes  252  of the PCIe completion header  250  includes 9 reserved bits indicated by “R,” a Format field describing the address length (32 or 64 bits) and whether the packet is a request or completion, a traffic class field (“TC”), a transaction layer packet digest (“TD”), a poison bit (“EP”), attributes (Attr), length in 4 byte increments, a completer ID  254 , completion status  258 , byte count modified  260  (“BCM”), a byte count  262 , a requester ID  256  and tag field  264  which comprises the transaction ID of the request, and the low order address  268  indicating the starting point of the payload data. The completer ID field  254  is the identification of the PCIe adapter  110  or I/O expansion adapter  111  or host that performed the completion. The requester ID  256  and Tag  264  of the PCIe completion header  250  contains the requester ID  204  and Tag  210  of the PCIe request header  200  to match memory completions to their corresponding memory requests. The requester ID  256  is used to route the completion information back to the originator of the memory request. The PCIe completion header  250  also includes a completion status field  258  for indicating if the request was completed successfully or if an error occurred while the adapter (PCIe adapter  110  or I/O expansion adapter  111 ) or host was processing the request. 
     Turning now to  FIG. 3 , an exemplary embodiment of the downbound expansion logic  128  (part of I/O expansion logic  122 ) depicted in  FIG. 1  for interpreting and transmitting I/O expansion operations from the host bus  120  to the PCIe bus  126  will be described. I/O expansion operations include a plurality of memory requests (also referred to herein as “downbound requests”) and a plurality of responses (also referred to herein as “downbound responses”). The host bus  120  connects the host system  124  to the I/O hub  112  of  FIG. 1  and provides transport services for directing requests and responses from the host system  124  to the PCIe adapters  110  and the I/O expansion adapters  111 . The I/O expansion adapters  111  operate in a communication format which is incompatible (i.e. not supported) with the PCIe standard format used by the PCIe bus  126 , therefore, transformation logic  132  executes within the I/O expansion adapters  111  to enable communication to the PCIe bus  126 . The transformation logic  132  transforms (i.e. reformats) requests and responses in the I/O expansion adapter  111  to a format that can be interpreted by the PCIe bus  126 . In an exemplary embodiment, the transformation logic  132  executes in logic circuits on the I/O expansion adapter  111 . In an alternate embodiment, the transformation logic  132  executes on one or more specialized hardware circuits communicatively coupled to the I/O expansion adapters  111  and the PCIe bus  126 . In an additional alternate embodiment, the transformation logic  132  executes as software in the I/O expansion adapter  111 . Although downbound requests and downbound responses are operations that are both initiated by the host system  124 , different process flows in the downbound expansion logic  128  are used to process each of the operations. 
     In an exemplary embodiment, a downbound request is placed onto the host bus  120 . After a downbound request is placed on the host bus  120 , the I/O hub  112  of  FIG. 1  collects the downbound request and passes it to the downbound expansion logic  128 . The downbound expansion logic  128  provides routing and transformation services based on information contained in the memory request. A downbound I/O expansion vector  304  is used to determine if the downbound request is being sent to one of the I/O expansion adapters  111  of  FIG. 1 . The downbound I/O expansion vector  304  retrieves information from a header of the downbound request, and using bit select logic  306  determines the destination of the downbound request. A cache inhibited (CI) load/store control  308  stores information related to downbound requests, such as a portion of the host address indicating the target I/O expansion adapter  111  and an operation code, if the host system  124  has indicated a response is required. 
     In an exemplary embodiment, a downbound request that is bound for one of the I/O expansion adapters  111  of  FIG. 1  is transformed into a PCIe compatible downbound request by a multiplexor  312 . In an additional embodiment, the CI load/store control  308  sets the opcode in the header of the memory request that is sent from the I/O hub  112  to the PCIe bus  126 , this data is used to process an upbound response at block  310  as will be described in more detail in reference to  FIG. 4 . 
     In an exemplary embodiment, a downbound response is initiated from the host system  124  in response to completing a request from one of the I/O expansion adapters  111 . The downbound response is placed on the host bus  120  and is collected by the I/O hub  112  and passed to the downbound expansion logic  128 . A DMA completion table  320 , as depicted in  FIG. 3 , contains records for all requests that are awaiting responses. In an exemplary embodiment the records in the DMA completion table  320  are updated to include information required to forward the downbound response from the host system  124  to the I/O expansion adapter  111 . A response address table (RAT)  318  is used to lookup downbound response routing information. The address information is stored for requests sent from the I/O expansion adapters  111  to the host bus  120  (also referred to herein as “upbound requests”) as they are processed, as will be described in more detail below. The upbound processing logic transmits the address data to the RAT  318  at the appropriate processing step at block  316  as will be described in more detail below in reference to  FIG. 4 . Control logic  322  adds an operation code (also referred to herein as “opcode”) to the downbound response which is used by the I/O expansion adapters  111  to process the downbound response. In an exemplary embodiment the downbound expansion logic  128  is implemented in hardware circuits in the I/O hub, however, it will be understood that in alternate embodiments the downbound expansion logic may be executed as software in the hub or as a combination of hardware and software executing on the hub or other logic circuits as is known in the art. 
     Turning now to  FIG. 4 , an exemplary embodiment of the upbound expansion logic  130  (part of I/O expansion logic  122 ) depicted in  FIG. 1  for interpreting and transmitting I/O expansion operations from the PCIe bus  126  to the host bus  120  will be described. These I/O expansion operations include a plurality of requests (also referred to herein as “upbound requests”) and a plurality of responses (also referred to herein as “upbound completions”). Both upbound requests and upbound completions are initiated by one or more of the I/O expansion adapters  111 . An upbound I/O expansion vector  422  is used to determine if the upbound request is being sent from one of the I/O expansion adapters  111 . The upbound I/O expansion vector  422  retrieves information from a header of the upbound request, and using the bit select logic  424  determines the source of the upbound request. Once the source of the upbound request is determined, the address routing information is stored in the RAT  318  of  FIG. 3 , by transporting the data to the RAT  318  at block  416 . A multiplexor  412  is used to extract the requester ID field  204  from the PCIe request header  200  of  FIG. 2   a  from the upbound request. The requester ID field  204  bus number is passed to the RAT  318 . The requester ID field  204  including the bus number, device number, and function number is passed from the multiplexor  412  to a requester ID content addressable memory (RID CAM)  414 . The RID CAM  414  provides an index into the device table  402 . The device table  402  is used to determine the virtual address of a particular function within the I/O expansion adapter  111  of  FIG. 1  based on the requester ID field  204 . The data extracted from the device table  402  is modified by a multiplexor  410 , and the output of the multiplexor  410  is used by a zone relocation table  404  to determine the correct address and partition of the host system  124  for which the request is to be sent. The operation code of the packet is processed by control logic  418  and is transformed into the appropriate I/O expansion operation code before being transmitted to the host bus  120 . 
     In an exemplary embodiment, the upbound completions are processed as described above, however, the control logic  418  matches the upbound completion with a downbound request using data transmitted to it from the CI load/store control  308  at block  420  when the downbound request was processed as described above. 
     Turning now to  FIG. 5 , a detailed block diagram of an exemplary embodiment of an upbound I/O expansion request processing flow will now be described. In an exemplary embodiment, the upbound I/O expansion request processing flow depicted in  FIG. 5  executes in the I/O expansion logic  122  of the I/O hub  112  and the transformation logic  132  of the I/O expansion adapter  111  of  FIG. 1 . The processing flow depicted in  FIG. 5  transforms an upbound request (or upbound packet(s) of a transaction) into the format of the PCIe request header  200  of  FIG. 2   a . At block  502 , one of the I/O expansion adapters  111  of  FIG. 1  initiates a request for an operation to be executed on the host system  124  of  FIG. 1  and the transformation logic  132  creates a standard PCIe request including a PCIe request header  200 . 
     At block  504 , I/O expansion information from the request is embedded in a transformed PCIe request header, such as the transformed PCIe request header  600  depicted in  FIG. 6 .  FIG. 6  depicts block diagram of a transformed PCIe request header that may be implemented by an exemplary embodiment. The first 4 bytes of the PCIe request header  202  shown in  FIG. 6  remain unchanged and function in the same way as described above with regard to  FIG. 2   a . As shown in  FIG. 6 , the requester ID field  204  of  FIG. 2   a  is replaced with two new fields, a request ID bus number field  602  and a zone ID field  604 . The request ID bus number field  602  identifies the I/O expansion adapter  111  from which the request was received on the host system  124 . The zone id field  604  is used to indicate a logical partition (not shown) of the host system  124 , which is used by the I/O expansion logic  122  to indicate which area of system memory the request is for. Each Logical Partition (LPAR) has its separate area of system memory, or zone. The high order bits of the address field  206  of  FIG. 2   a , are replaced with a field to indicate to the I/O expansion logic  122  that this request is a DMA write operation as opposed to an atomic or test &amp; store operation which are also transmitted from the I/O expansion adapter  111  as posted memory write requests. A key field  608  is used to protect unauthorized system memory accesses. The remaining bits including the high order bits of the address field  206  (field  610 ) are left unchanged. The low order bits of the address field  208  as well as the reserve bits  216  are left unchanged. Although specific modifications have been described, it will be understood that other fields or values in the request header could be modified or added in alternate embodiments while still preserving the functions described above. 
     Returning now to block  506  of  FIG. 5 , once the PCIe request header has been formatted to embed the I/O expansion transaction information into a PCIe formatted request, the request, including the transformed PCIe request header  600 , is sent to the host system  124  via the I/O hub  112 . At block  508 , the I/O hub  112  uses the PCIe bus number  602  of  FIG. 6  from the transformed I/O PCIe request header  600  as an index into the upbound I/O expansion vector  422  to determine if the request is from an I/O expansion adapter  111 . If the bit corresponding to the bus number is on, the request is from an I/O expansion adapter  111 . If the bit is off, the request is from a PCIe adapter  110 . If the request is from a PCIe adapter  110 , the fields in the PCIe header are interpreted as a normal PCIe request header and processed accordingly at block  514 . If the request is from an I/O expansion adapter  111 , the zone ID field  604  identifies the memory zone of the LPAR (not shown), and the zone ID field  604  is used to relocate the system memory address through multiplexor  410  and the zone relocation table  404 . The resulting relocated address is included in the host request. The key field  608  is a memory protection key and controls access to system memory. The key is included in the host request. The high order bits of the address field  606  indicate to the I/O expansion logic  122  that this request is a DMA write operation as opposed to an atomic or test &amp; store operation which at block  510  the I/O hub  112  sends the request to the host system  124 . If the operation is an atomic or test &amp; store operation, further modifications to the header include lock bytes and opcodes. 
     Turning now to  FIG. 7 , a detailed block diagram of an exemplary embodiment of an upbound I/O expansion response processing flow will now be described. In an exemplary embodiment, the upbound I/O expansion response processing flow depicted in  FIG. 7  executes in the I/O expansion logic  122  of the I/O hub  112  and the transformation logic  132  of the I/O expansion adapters  111  of  FIG. 1  and transforms an upbound response into the format of the PCIe request header  200  of  FIG. 2   a  for I/O expansion transactions that require a response but for which a PCIe response is not supported (e.g., write requests). At block  702 , the I/O expansion adapter  111  of  FIG. 1  creates a response to a request that was previously sent by the host system  124  of  FIG. 1 . In an exemplary embodiment, the response includes data such as, but not limited to a requestor identifier, and an operation code to match the response to the corresponding request. At block  704  the I/O expansion adapter  111  determines if the response is for a read or a write request. If the response is for a read request, the I/O expansion adapter  111  replaces a portion of the completer ID field  254  of  FIG. 2   b  with a response code (not shown) which is not defined by the PCI specification. 
     At block  706 , if the response is for a posted memory write, I/O expansion information from the response is embedded in a transformed PCIe request header, such as the transformed PCIe request header  800  depicted in  FIG. 8 .  FIG. 8  depicts a block diagram of an exemplary embodiment of a transformed PCIe request header containing an I/O expansion response. The first 4 bytes of the PCIe request header  200  of  FIG. 2   a  remain unchanged and function in the same way as described above with regard to  FIG. 2   a . As shown in  FIG. 8 , the requester ID field  204  of  FIG. 2   a  is replaced with two new fields, a request ID bus number field  802  and an operation code field  804 . The request ID bus number field  802  is the identification information of the I/O expansion adapter  111  that initiated the request. The operation code field  804 , is used to indicate the type of request that was completed by the I/O expansion adapter  111 . Three of the high order bits of the address field  206  of  FIG. 2   a , are replaced with bits indicating that the response is to update the CI load/store control  308  of  FIG. 3  with an indicator flagging the transaction as complete. The low order bits of the address field  208  of  FIG. 2   a  are modified to include a response code field  814  for indicating the status of the completed request, the write tag  816  from the request for which this response is being generated, and a set of filler bits  818 . The reserved bits  216  of  FIG. 2   a  remains unchanged. Although specific modifications have been described, it will be understood that other fields or values in the request header could be modified or added in alternate embodiments while still preserving the functions described above. 
     Returning now to block  708  of  FIG. 7 , once the PCIe request header has been formatted to embed the response information into a PCIe formatted request, the formatted request, including the transformed PCIe request header  800 , is sent to the host system  124  via the I/O hub  112 . At block  710 , the I/O hub  112  receives the PCIe request and transforms it to a response format supported by the host system  124 . The host system response includes a host tag and a return code. If the response is determined to be a memory read, the payload data (i.e. the data that has been read) is also included. At block  712  the I/O hub  112  sends the response to the host system  124 . 
     Technical effects and benefits include enabling non-PCIe compatible I/O adapters to be implemented on a PCIe architecture along with PCIe compatible adapters without requiring modifications to the PCIe bus and PCIe switch mechanisms. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
     As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. 
     Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. 
     A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. 
     Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. 
     Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user&#39;s computer, partly on the user&#39;s computer, as a stand-alone software package, partly on the user&#39;s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user&#39;s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). 
     Aspects of the present invention are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
     These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. 
     The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
     As described above, embodiments can be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. In exemplary embodiments, the invention is embodied in computer program code executed by one or more network elements. Embodiments include a computer program product on a computer usable medium with computer program code logic containing instructions embodied in tangible media as an article of manufacture. Exemplary articles of manufacture for computer usable medium may include floppy diskettes, CD-ROMs, hard drives, universal serial bus (USB) flash drives, or any other computer-readable storage medium, wherein, when the computer program code logic is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. Embodiments include computer program code logic, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code logic is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code logic segments configure the microprocessor to create specific logic circuits. 
     The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.