Abstract:
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is a Continuation of application Ser. No. 10/460,662, Filed: Jun. 13, 2003, Titled: D ISTRIBUTED  A VERAGING  A NALOG  T O  D IGITAL  C ONVERTER  T OPOLOGY , Inventors: M ULDER  et al., which is a Continuation of application Ser. No. 10/153,709, Filed: May 24, 2002, Titled: D ISTRIBUTED  A VERAGING  A NALOG  T O  D IGITAL  C ONVERTER  T OPOLOGY , Inventors: M ULDER  et al., which are both incorporated by reference herein. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to analog to digital converters (ADC&#39;s), and more particularly, to various topologies for high speed analog to digital converters that use interleaving of amplifier connections to reduce parasitic capacitance.  
           [0004]    2. Related Art  
           [0005]    A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC&#39;s (i.e. high speed, low power, low area, high resolution). FIG. 1 shows the generic two-step subranging architecture, comprising a reference ladder  104 , a coarse ADC  102 , a switching matrix  103 , a fine ADC  105 , coarse comparators  107 , fine comparators  108  and an encoder  106 . In most cases, a track-and-hold  101  is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC  102 . The coarse ADC  102  compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix  103  connects the fine ADC  105  to a subset of the reference voltages (called a ‘subrange’) that is centered around the input signal voltage.  
           [0006]    Modern flash, folding and subranging analog to digital converters (ADC&#39;s) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.  
           [0007]    In general, flash, folding and subranging ADC&#39;s use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators  107 ,  108 . These residue signals are obtained by subtracting different DC reference voltages from an input signal V in . The DC reference voltages are generated by the resistive ladder (reference ladder)  104  biased at a certain DC current. Two implementation aspects of averaging that should be distinguished are circuit implementation and topology.  
           [0008]    With respect to circuit implementation, various ideas have been published in the literature, e.g., connecting resistors between amplifier outputs, and connecting capacitors between amplifier inputs. Interpolation is a type of averaging, and additional published techniques include capacitive interpolation, active interpolation using differential pairs, active interpolation using current mirrors, and active interpolation using current splitting.  
           [0009]    In general, little attention has been paid to the second aspect: the averaging topology. FIG. 2 shows an example of a conventional averaging topology. As may be seen from FIG. 2, three arrays of amplifiers are used to effect an averaging topology: an “a” amplifier array, comprising amplifiers a 1 , a 2 , a 3  . . . , a “b” amplifier array, comprising amplifiers b 1 , b 2 , b 3  . . . , and a “c” amplifier array, comprising amplifiers c 1 , c 2 , c 3  . . . . The inputs of the “b” amplifiers combine several outputs of the “a” amplifiers, and the inputs of the “c” amplifiers combine several outputs of the “b” amplifiers. Taking the b 2  amplifier as an example, the b 2  amplifier is connected to amplifiers a 1 , a 2 , a 3 , a 4  through a summer SB 2 . Similarly, the amplifier c 2  is connected to the amplifiers b 2  and b 3  through a summer SC 2 . The amplifier c 2  therefore ultimately combines the outputs of the amplifiers a 1 , a 2 , a 3 , a 4  and a 5  through the amplifiers b 2  and b 3  and the summers SB 2  and SB 3 . Because of this, the weights on the inputs (i.e., the weights on the outputs of the amplifiers a 1  . . . a 5 ) are not equal.  
           [0010]    Averaging is needed to improve noise and offset performance of the amplifiers. Since the signals are correlated (i.e., add linearly) and the noise is uncorrelated (root mean square addition) the signal to noise ratio (SNR) at the “b” array of amplifiers is nominally unity for each “a” amplifier, and {square root}{square root over ( )}4=2 for 4 amplifiers. The downside of this arrangement is that many connections are needed between the “a” array and the “b” array. Another downside of this arrangement is the resulting different weighting coefficients, as discussed above, which detract from the root mean square additive property of noise.  
           [0011]    The characteristic aspect of the topology of FIG. 2 is that averaging is always performed on a set of neighboring amplifiers. For example, the amplifier b 2  combines the outputs of the amplifiers a 1 , a 2 , a 3  and a 4 , implementing 4× averaging. The amplifier c 2  combines the outputs of amplifiers b 2  and b 3 , implementing 2× averaging. Furthermore, the ‘averaging window’ is optimized separately for each set of connections between two arrays of amplifiers. The averaging window may be considered a one-dimensional spacial filter. See Pan et al.,  IEEE J. of Solid State Circ.  36(12):1847-1858 (December 2001).  
           [0012]    In most publications, the averaging window has an infinite width (neglecting edge effects). This is an artifact of the circuit implementation used, i.e., averaging is implemented by connecting resistors between the amplifier outputs. An averaging window with a finite width can be obtained if different circuit implementations are used, e.g., active averaging or capacitive averaging.  
           [0013]    In general, finite width averaging windows provide better performance, since they have a smaller edge effect, and they average only across amplifiers that are in their linear region. The disadvantage is that they require many connections between the amplifiers. For example, as shown in FIG. 2, each “b” amplifier requires connections to four “a” amplifiers. This results in a considerable layout complexity, which can seriously degrade the ADC performance.  
         SUMMARY OF THE INVENTION  
         [0014]    The present invention is directed to an analog to digital converter topology that substantially obviates one or more of the problems and disadvantages of the related art.  
           [0015]    There is provided an analog to digital converter including a first amplifier array connected to taps from a reference ladder and to an input signal, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.  
           [0016]    In another aspect of the present invention there is provided an analog to digital converter including a reference ladder connected to an input voltage, a first amplifier array connected to taps from the reference ladder, a second amplifier array connected to the first amplifier array in an interleaved manner, a third amplifier array connected to the second amplifier array in an interleaved manner, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.  
           [0017]    In another aspect of the present invention there is provided an analog to digital converter including a reference ladder connected to an input voltage, a first plurality of amplifiers connected to taps from the reference ladder, a second plurality of amplifiers connected to the first plurality in an interleaved manner, a third plurality of amplifiers connected to the second plurality in an interleaved manner, and an encoder connected to outputs of the third plurality that converts the outputs to an N-bit digital signal representing the input voltage.  
           [0018]    In another aspect of the present invention there is provided an analog to digital converter including a reference ladder, a plurality of amplifier arrays “a”, “b”, “c” . . . “n” arranged in a cascade, wherein the amplifiers in the array “a” are connected to taps from the reference ladder and to an input voltage, a plurality of connections between consecutive arrays of the plurality of amplifier arrays “a”, “b”, “c” . . . “n”, wherein the connections are configured for m a ×m b ×m c × . . . m n × averaging of the taps, m a , m b , m c  . . . m n  representing an averaging factor of the corresponding amplifier array, and an encoder connected to outputs of the “n” amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.  
           [0019]    In another aspect of the present invention there is provided an analog to digital converter including a first amplifier array connected to taps from a reference ladder and to an input signal, a second amplifier array, wherein each amplifier in the second amplifier array is connected to at least two amplifiers of the first amplifier array, a third amplifier array, wherein each amplifier in the third array is connected to two at least two amplifiers of the second amplifier array, wherein an output of each amplifier of the first array has only one path to a corresponding amplifier of the third array, and an encoder converting outputs of the third amplifier array to an N-bit digital signal representing the input signal.  
           [0020]    In another aspect of the present invention there is provided an analog to digital converter including a reference ladder, a plurality of amplifier arrays A i , i=1 through n, arranged in a cascade, wherein the amplifiers in the array A 1  are connected to taps from the reference ladder and to an input voltage, a plurality of connections between consecutive arrays of the plurality of amplifier arrays A i , wherein each amplifier of each array A i , i=2 through n, is connected to an output of a corresponding amplifier of an array A k , k=1 through i−1, through only one path, and an encoder connected to outputs of the A n  amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.  
           [0021]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0022]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:  
         [0024]    [0024]FIG. 1 illustrates a conventional sub-ranging ADC;  
         [0025]    [0025]FIG. 2 illustrates a conventional averaging topology;  
         [0026]    [0026]FIG. 3 illustrates an interleaved averaging topology of the present invention;  
         [0027]    [0027]FIG. 4 shows a topology for 2×3× averaging;  
         [0028]    [0028]FIG. 5 shows a topology for 3×2× averaging;  
         [0029]    [0029]FIG. 6 shows a topology for 2×2×2× averaging  
         [0030]    [0030]FIG. 7 illustrates an averaging topology of the present invention that also uses interpolation;  
         [0031]    [0031]FIG. 8 illustrates the averaging topology of the present invention at an edge of the amplifier array;  
         [0032]    [0032]FIG. 9 illustrates a termination of the averaging topology of the present invention at the edge of the array of amplifiers that also utilizes differential interpolation;  
         [0033]    [0033]FIG. 10 shows improvements obtained using the topology of the present invention;  
         [0034]    [0034]FIG. 11 illustrates an auto-zero amplifier used in the present invention;  
         [0035]    [0035]FIG. 12 illustrates an interpolation method of the present invention; and  
         [0036]    [0036]FIG. 13 illustrates a circuit diagram of averaging amplifier connection. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0037]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0038]    This disclosure describes new averaging topologies, whose primary advantage is a significant reduction in layout complexity, in turn, resulting in improved ADC performance. An example of a proposed averaging topology is shown in FIG. 3. As may be seen from FIG. 3, the topology of the present invention includes a number of amplifier arrays, for example, an amplifier array “a,” an amplifier array “b,” and an amplifier array “c,” similar to that of FIG. 1. It should be noted that in real-life applications, there may be more than three arrays, for example, 4 or 5 arrays. The “a” array takes as inputs tap voltages from a reference ladder (such as the reference ladder  104  of FIG. 1), and from a track- and-hold amplifier (e.g., the track-and-hold  101  of FIG. 1). Typically, the amplifiers used are differential amplifiers, with differential inputs.  
         [0039]    Although connections between the “c” array and “b” array are similar to that of FIG. 2, the connections between the “a” array and the “b” array are interleaved. Thus, each “b” amplifier takes inputs from only two amplifiers in array “a.” Using amplifier b 2  as an example, it takes inputs only from amplifiers a 1  and a 3 , but not from a 2 . Thus, only two connections are required between each amplifier in the “b” array, and each amplifier in the “a” array. Nonetheless, each amplifier in the “c” array still ultimately connects to outputs of 4 amplifiers in the “a” array. In other words, taking amplifier c 2  as an example, it connects to amplifiers a 1 , a 2 , a 3 , and a 4  through the amplifiers b 2  and b 3  and summers SB 2 , SB 3  and SC 2 . Accordingly, a 4× averaging interpolation is still accomplished, with the number of connections between the “b” array and the “a” array reduced by 50% as compared to conventional art. Furthermore, the outputs of the “a” array are now equally weighted. Since each “c” amplifier still does an averaging over 4 “a” amplifiers, the root mean square noise properties are taken advantage of, to reduce the noise. Furthermore, the outputs of the “a” array are now equally weighted.  
         [0040]    The outputs of the “c” amplifiers are inputted into an array of comparators (not shown in FIG. 3, but which correspond to elements  107 ,  108  of FIG. 1), and then to an encoder (not shown in FIG. 3, which corresponds to the encoder  106  of FIG. 1), which converts the outputs of the comparators to an N-bit binary number representing the input signal.  
         [0041]    It will be appreciated that while FIG. 3 shows an interleaving of adjacent amplifiers (i.e., “skipping” every other amplifier in a row), other interleaving arrangements are possible, including, for example, skipping every two, or every three amplifiers in a row.  
         [0042]    Additionally, the topology of FIG. 3 is much easier to lay out compactly, due to a reduced number of connections between the “a” array and the “b” array, resulting in an estimated speed improvement of between 50 and 100%. In this topology, the averaging connections between the amplifiers are optimized for all connections simultaneously. This can result in a significant reduction in layout complexity. Comparing FIGS. 2 and 3, it is obvious that the required number of connections, and therefore, the layout complexity, is lower for the topology shown in FIG. 3.  
         [0043]    An important characteristic of the topology shown in FIG. 3 can be observed when considering the averaging connections. When starting at the input of a “c” amplifier, there is always only (at most) one path to an output of an “a” amplifier. For example, the input of c 2  connects to the output of a 3  only through amplifier b 2 . In the conventional averaging topology, the input of c 2  connects to the output of a 3  both through amplifiers b 2  and b 3 .  
         [0044]    Another way of comparing conventional and the proposed averaging topologies is to compare the effective averaging accomplished for the same number of connections between the amplifiers. A table in FIG. 10 shows such a comparison for different numbers of connections between the “a” amplifiers and the “b” amplifiers, and between the “b” amplifiers and the “c” amplifiers. (The final row in the table also has averaging between the “c” amplifiers and a “d” array of amplifiers.) The fourth and fifth column in this table show across how many “a” amplifiers averaging has effectively been accomplished, for the conventional art and the proposed averaging topology, respectively. Note that emphasis is placed on averaging of the first row of amplifiers, because these are most sensitive to mismatch and noise. The last column in FIG. 10 shows the factor of improvement obtained.  
         [0045]    Several generalizations of the topology shown in FIG. 3 are possible. If the depicted topology of FIG. 3 could be referred to as “2×2×” averaging, effectively implementing 4× averaging of the “a” amplifier array and 2× of the “b” amplifier array. A more general topology would implement “m a ×m b ×” averaging, effectively implementing “m a ×m b ×” averaging of the “a” amplifier array and m b ×of the “b” amplifier array. As an example, FIGS. 4 and 5 show the topologies for 2×3× averaging (i.e., m a =2, m b =3) and for 3×2× averaging, respectively.  
         [0046]    Further generalization is possible if more cascaded arrays of amplifiers are used in the ADC. As an example, FIG. 6 shows a topology for 2×2×2× averaging (i.e., m a =2, m b =2, m c =2).  
         [0047]    The most general averaging topology would then be referred to as “m a ×m b ×m c × m n ×” averaging of amplifier arrays “a”, “b” . . . “n”, effectively implementing “m 1 =m a ×m b ×m c  . . . m n ×” averaging of the “a” amplifier array, “m 2 =m b ×m c ×m d  . . . m n ×” averaging of the “b” amplifier array, etc.  
         [0048]    Note that the number X a  of amplifiers that are “skipped” in the first row of amplifiers can be expressed by:  
                 X   a     =         m   1       m   a       -   1       ,           (   1   )                               
 
         [0049]    the number X b  of amplifiers that are “skipped” in the second row of amplifiers can be expressed by:  
                 X   b     =         m   2       m   b       -   1       ,           (   2   )                               
 
         [0050]    etc.  
         [0051]    The proposed averaging topology can easily be combined with interpolation, a technique that can decrease a required number of amplifiers in the first row(s) of cascaded amplifiers. As an example, FIG. 7 shows the topology depicted in FIG. 2 supplemented with 4× averaging. As may be seen in FIG. 7, once the alternating amplifier outputs from the “a” array are summed, they are fed into three amplifiers in the “b” array. Thus, taking amplifiers a 2  and a 4  as an example, their output is summed by a summer SB 5 . The outputs of the amplifiers a 1  and a 3  are summed by the summer SB 3 . The input to the amplifier b 5  is the output of the summer SB 5 , and the input to the amplifier b 3  is the output of the summer SB 3 . The amplifier b 4 , however, is differentially inputted outputs of the summers SB 3  and SB 5 .  
         [0052]    An array of distributed amplifiers necessarily comprises a finite number of amplifiers. At the edges, special care has to be taken to avoid the occurrence of edge effects. FIGS. 8 and 9 propose two methods for terminating the averaging topology at the edges of the amplifier arrays.  
         [0053]    A first method, shown in FIG. 8, uses a wider signal range for amplifier rows that are closer to the ADC input. This ensures that 4× averaging is maintained also for the “c” amplifiers that are close to, or at, the edges. The disadvantage is that a few extra amplifiers are required to remove the edge effect.  
         [0054]    A second method (shown in FIG. 9) uses different connections between the amplifiers at the edges. For example, the input of the amplifier b 1  now connects only to the output of the amplifier a 1 . The advantage is that the same signal range is maintained along all arrays of amplifiers. A small disadvantage is that the amount of averaging decreases at the edges. Fortunately, in subrange ADC&#39;s, the edges are usually used for overrange purposes, which makes offset and noise performance at the edges less important.  
         [0055]    The techniques are illustrated based on the auto-zero amplifier shown in FIG. 11. FIG. 11 illustrates the structure of one of the amplifiers in an amplifier array A 1 , A 2 , A 3  . . . (I.e., an amplifier used in a first array of cascaded arrays. The amplifiers in the first array have to connect to both the track-and-hold  101  and the reference ladder  104  on two different clock phases, while subsequent cascaded stages do not.) As shown in FIG. 11, a non-overlapping two-phase clock is used, with non-overlapping phases φ 1  and φ 2 . At a “−” input of the amplifier, two NMOS transistors M 1  and M 2  are used, with a source of the transistor M 2  being connected to the “−” input terminal, and a gate of the transistor M 2  being connected to the clock phase φ 2 . A gate of the transistor M 1  is driven by the clock phase φ 1 . The drains of the transistors M 1  and M 2  are tied together and connected to one side of a capacitor C−. The other side of the capacitor C− is connected to a source of a transistor M 3 , and to a gate of a transistor M 4 . A gate of the transistor M 3  is connected to the clock phase φ 1 . Drains of the transistors M 3  and M 4  are tied together and a resistor that is connected to a positive supply voltage V dd . A symmetrical structure is used for the “+” input, as shown in FIG. 11, using transistors M 8 , M 7 , M 6  and M 5 , and a capacitor C+.  
         [0056]    During clock phase φ 1  the amplifier is in a reset mode and the sampling capacitors are charged to the value of the sampled voltage V sample . During the next clock phase, φ 2 , the φ 1  amplifier is connected to the reference ladder and the amplifier output voltage V out  equals: V out =G·(V ref −V sample ),  
         [0057]    where G is the voltage gain of the amplifier, V ref =V +input −V −input  and V sample =V TH,pos −V TH,neg .  
         [0058]    [0058]FIG. 12 illustrates the use of the auto zero amplifier of FIG. 11 in more detail and shows the three amplifiers A 1 , A 2 , A 3  (without the switches driven by the two phase clock). The A 1  and A 3  amplifiers have their own input capacitors (C 1 , C 2 , and C 5 , C 6 , respectively), the A 1  amplifier has differential inputs V ref,m /V ref,0 , the amplifier A 3  has differential inputs V ref,m−1 /V ref,1 . The amplifier A 2  does not have its own input capacitors. Instead, the amplifier A 2  comprises two differential transistor pairs M 4 , M 6  (both half the size of the differential pairs M 4 , M 6  of A 1  and A 3 ). It&#39;s current sources are each half of the current source of A 1  or A 3 . Gates of one of the transistor pairs M 4 , M 6  connect to the gates of the corresponding transistors of the A 1  amplifier, and gates the other differential transistor pairs M 4 , M 6  connect to corresponding gates of transistors of the A 3  amplifier. The drain currents of the two differential transistor pairs of A 2  are summed. As a result, output of the amplifier A 2  (V OUT,2 ) is (approximately) equal to the average of the outputs of A 1  and A 3  (i.e., the average of V OUT,1  and V OUT,3 ).  
         [0059]    It will be appreciated that although the auto-zero amplifier of FIG. 11 is shown as using N channel MOSFET&#39;s, P channel MOSFET&#39;s can also be used. Note further that the track-and-hold  101  of FIG. 1 is typically a differential input and output amplifier.  
         [0060]    [0060]FIG. 13 illustrate a particular averaging implementation of 2× capacitive averaging (the topology of FIG. 3). This is accomplished by splitting each input capacitor in two equal parts, to form four capacitors C 1  through C 4 . C 1  connects to a first positive input V i,p1  and to the gate of one transistor in the differential pair. C 2  connects to a second positive input V i,p2  and to the gate of the same transistor in the differential pair. C 3  connects to a first negative input V 1,n1  and to a gate of the other transistor in the differential pair. C 4  connects to a second negative input V i,n2  and to the gate of the other transistor in the differential pair. The inputs are connected to interleaved outputs of amplifiers of the preceding amplifier array. Capacitive averaging is now accomplished between charge sharing between C 1  and C 2  and between C 3  and C 4 .  
         [0061]    The averaging topologies described herein can be applied in many types of ADC architectures. In particular, it is very suitable for application in flash, folding and subranging ADC&#39;s. Various circuit implementation techniques, especially capacitive or active averaging, can be employed for implementing the proposed averaging topologies.  
         [0062]    It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.