Abstract:
A semiconductor memory device disclosed herein has a memory cell array in which memory cells are arranged in a matrix form, data being written into each of the memory cells by passing a cell current therethrough; word lines which are provided in parallel along a row direction in the memory cell array; bit lines which are provided in parallel along a column direction in the memory cell array, the column direction being crossed with the row direction; sense amplifiers which are respectively connected to the bit lines and which write data held in the sense amplifiers into the memory cells; a data line which supplies data to be written into the sense amplifiers; and a control circuit which, in a continuous write operation of performing write operations by continuously switching a column address to select a column, opens only a connection between the sense amplifier selected by the column address and the bit line to write the data held in the sense amplifier into the memory cell.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2004-150492, filed on May 20, 2004, the entire contents of which are incorporated by reference herein. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor device including an FBC (Floating Body Cell) which stores information by accumulating majority carriers in a body in a floating state in a field effect transistor (FET). 
   2. Background Art 
   The fabrication of a related DRAM cell having one transistor and one capacitor which includes a trench capacitor or a stacked capacitor is getting difficult with its miniaturization. However, as an alternative memory cell thereto, a new memory cell FBC which stores information by accumulating majority carriers in a body in a floating state in an FET (Field Effect Transistor) formed on a Silicon on Insulator (SOI) or the like (See Document 1: Japanese Patent Application Laid-open No. 2003-68877, and Document 2: Japanese Patent Application Laid-open No. 2002-246571, for example) was proposed. 
   An element unit of this memory cell to store one bit of information has only one MISFET (Metal Insulator Semiconductor Field Effect Transistor), whereby the area occupied by one bit is small, so that a mass storage element can be formed on a limited silicon area. Accordingly, it is thought that this can contribute to an increase in storage capacity. 
   The reading of data from such a MISFET is performed by current read (See Document 3: 2002 IEEE International Solid-State Circuits Conference, “Memory Design Using One-Transistor Gain Cell on SOI”, p152, p153, p454). Namely, a word line connected to a gate of the MISFET is set, for example, to 1.5 V, a bit line connected to a drain is set, for example, to as low as 0.2 V, the transistor is operated in a linear region, and “1” data and “0” data are distinguished by detecting current difference using an effect (body effect) in which a threshold voltage Vth of the transistor differs according to the number of holes accumulated in the body. Incidentally, the reason the voltage of the bit line is set to as low as 0.2 V in a read operation in this example is that if the voltage of the bit line is set high and biased to a saturation state, there is a possibility that when the “0” data is read, the “0” data cannot be correctly detected because the data is changed into the “1” data by impact ionization. 
   In a related semiconductor memory device using FBCs, one sense amplifier is provided for plural bit lines, and when the sense amplifier is connected to a bit line, one bit line is selected from the plural bit lines and connected. This makes it possible to realize a reduction in the number of sense amplifiers and a reduction in chip area. The reason which makes this configuration possible is based on the premise that the FBC is capable of non-destructive read-out. In other words, this is because the FBC is thought to have a characteristic that data in a memory cell from which the data is not read is not destroyed even when a word line rises, and if the word line returns to a holding level, the data remains held as it was before. 
   However, in the later FBC characteristic evaluation, it has turned out that the FBC is not completely a non-destructive read-out cell. This is because it has proved that a charge pumping phenomenon exerts an influence on the characteristic of the memory cell. This charge pumping phenomenon is a phenomenon in which holes gradually disappear at an interface between a silicon surface and a gate insulating film (for example, SiO 2 ) when operations of bringing the silicon surface into an inversion state and an accumulation state are alternately repeated by pumping the gate of the transistor a plurality of times. 
   The number of holes which disappear by one change of state of inversion/accumulation depends on an interface state density Nit of the Si—SiO 2  interface. If Nit=1×10 10  cm −2  is assumed, the area of the Si—SiO 2  interface is 1.0×10 −10  cm 2  per cell when the cell transistor has W/L=0.1 μm/0.1 μm, whereby the number of holes which disappear by one change of state is approximately one on average per cell. The difference in the number of holes between “1” data and “0” data in one FBC is approximately 1000. This means that after approximately 1000-time pumping of the word line, the “1” data completely changes to the “0” data. Actually, the read margin of the “1” data disappears after approximately 500-time pumping, and the risk of causing failures increases. Accordingly, it turns out that the FBC is neither a destructive read-out cell nor a complete non-destructive read-out cell. It turns out that it is, so to speak, a quasi non-destructive read-out cell. 
   If a sense amplifier of a related system is used in the aforementioned case, since data is not written back even if a word line rises, a failure in which the “1” data has changed to the “0” data is caused if the word line rises approximately 500 times before a refresh operation is performed. Therefore, apart from whether the memory cell is selected for read/write, the design of a sense amplifier which takes some measures against the charge pumping phenomenon is needed for all of the memory cells holding the “1” data whose word lines are activated. 
   Moreover, there is a problem that the related system sense amplifier is inefficient in the refresh operation. Namely, there is a problem that the number of memory cells which can be refreshed in one refresh cycle is smaller as compared with the conventional DRAM. For example, in a sense amplifier disclosed in Document 3, the refresh efficiency reduces to ⅛. Accordingly, when the refresh time is the same, it is necessary to set the refresh cycle eight times as frequently as the conventional DRAM, and correspondingly the proportion in which the normal operation cannot be performed increases. 
   Furthermore, in the configuration of the semiconductor memory device in Document 3, there is a problem that the number of memory cells which can be accessed in a high-speed column access is limited. In other words, when a mode in which data in memory cells are read by raising a word line, latched in a sense amplifier, and continuously accessed at high speed by switching the column address to thereby increase data transfer rate (this mode is also called the Fast Page Mode) is used, the number of accessible data reduces to ⅛ as compared with the normal DRAM. 
   On the other hand, when sense amplifiers are provided independently corresponding to respective bit lines, the cell current flows from each sense amplifier to a source of a memory cell in a write operation, which causes a problem that current consumption increases. Namely, in a write cycle, a connection between each sense amplifier and each bit line is opened irrespective of whether each memory cell is a memory cell into which data is actually written, and therefore the cell current flows from each sense amplifier to each memory cell. Besides, the cell current continues flowing until one write cycle is completed. 
   SUMMARY OF THE INVENTION 
   In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device, comprises:
         a memory cell array in which memory cells are arranged in a matrix form, data being written into each of the memory cells by passing a cell current therethrough;   word lines which are provided in parallel along a row direction in the memory cell array;   bit lines which are provided in parallel along a column direction in the memory cell array, the column direction being crossed with the row direction;   sense amplifiers which are respectively connected to the bit lines and which write data held in the sense amplifiers into the memory cells;   a data line which supplies data to be written into the sense amplifiers; and   a control circuit which, in a continuous write operation of performing write operations by continuously switching a column address to select a column, opens only a connection between the sense amplifier selected by the column address and the bit line to write the data held in the sense amplifier into the memory cell.       

   According to another aspect of the present invention, a semiconductor memory device, comprises:
         a memory cell array in which memory cells are arranged in a matrix form, data being written into each of the memory cells by passing a cell current therethrough;   word lines which are provided in parallel along a row direction in the memory cell array;   bit lines which are provided in parallel along a column direction in the memory cell array, the column direction being crossed with the row direction;   sense amplifiers which are respectively connected to the bit lines and which write data held in the sense amplifiers into the memory cells;   a data line which supplies data to be written to the sense amplifiers; and   a control circuit which, in a continuous write operation of performing write operations by continuously switching a column address to select a column, after cutting off connections between the sense amplifiers and the bit lines and continuously switching the column address such that each of the sense amplifiers holds the data to be written, opens the connections between the sense amplifiers and the bit lines and writes the data held in the sense amplifiers into the memory cells at once.       

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram explaining the structure of an FBC according to a first embodiment; 
       FIG. 2  is a diagram explaining the layout of a memory cell array in a semiconductor memory device according to the first embodiment; 
       FIG. 3  is a diagram showing the configurations of a sense amplifier and a column selection circuit according to the first embodiment; 
       FIG. 4  is a timing chart explaining a refresh operation of the semiconductor memory device according to the first embodiment; 
       FIG. 5  is a timing chart explaining a continuous write operation of the semiconductor memory device according to the first embodiment; 
       FIG. 6  is a timing chart explaining a continuous read operation of the semiconductor memory device according to the first embodiment; 
       FIG. 7  is a diagram explaining the layout of the sense amplifiers and the column selection circuits in the semiconductor memory device according to the first embodiment; 
       FIG. 8  is a diagram explaining a modification of the first embodiment; 
       FIG. 9  is a diagram explaining the configuration of a sense amplifier according to a second embodiment; 
       FIG. 10  is a diagram explaining the layout of the sense amplifiers according to the second embodiment; and 
       FIG. 11  is a timing chart explaining a continuous write operation of a semiconductor memory device according to the second embodiment. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
   First Embodiment 
   In a semiconductor memory device according to this embodiment, all bit lines are connected to sense amplifiers, paths to write back data held in the sense amplifiers into memory cells are controlled not only in a row direction but also in a column direction. Further details will be given below. 
   First, a write and a read principle of an FBC according to this embodiment will be explained. The FBC according to this embodiment has an N-type MISFET formed on a PD (partially Depleted)-SOI. Hereinafter, a state where there are many holes in a body of the MISFET is defined as “1” data, whereas a state where there are very few holes therein is defined as “0” data. 
     FIG. 1  shows an FBC transistor. An SOI substrate includes a silicon substrate  10  and an insulating film  12 . The FBC includes an N-type MISFET formed on this SOI substrate. More specifically, a semiconductor layer  14  is formed on the SOI substrate, and a source S and a drain D are formed in this semiconductor layer  14 . The semiconductor layer  14  between the source S and the drain D constitutes the aforementioned body. A gate G is formed on the semiconductor layer  14  with a gate insulating film  16  therebetween. Here, the source S is a ground GND (0 V), the drain D is connected to a bit line BL, and the gate G constitutes a word line WL. The body is electrically floating. 
   To write the “1” data, the transistor is operated in a saturation state. For example, the word line WL and the bit line BL are biased to 1.5 V and 1.5 V, respectively. In such a state, many electron-hole pairs are created in the neighborhood of the drain D due to impact ionization. Out of these electron-hole pairs, electrons are drawn into a drain terminal, whereas holes are accumulated in the body with a low potential. The body voltage reaches an equilibrium state when a current generated by the holes due to the impact ionization and a forward current in a pn junction between the body and the source S are balanced. The body voltage is approximately 0.7 V. 
   On the other hand, to write the “0” data, the voltage of the bit line BL is lowered to a negative voltage. For example, it is lowered to −1.5 V. A p-region of the body and an n-region connected to the bit line BL are strongly forward biased by this operation, and hence most of the holes accumulated in the body are emitted to the n-region. Consequently, the number of holes reduces, and the state of the “0” data can be obtained. 
     FIG. 2  is a diagram showing part of the configuration of a memory cell array of the semiconductor memory device according to this embodiment. As shown in  FIG. 2 , the memory cell array according to this embodiment is formed in an open bit line configuration. 
   More specifically, on the right side of sense amplifiers S/A 0  to S/A 1023 , 256 word lines RWL 0  to RWL 255  are provided in parallel along a row direction, and on the left side thereof, 256 word lines LWL 0  to LWL 255  are provided in parallel along the row direction. Moreover, to the right side of the sense amplifiers S/A 0  to S/A 1023 , 1024 bit lines RBL 0  to RBL 1023  which are provided in parallel along a column direction are connected, and to the left side thereof, 1024 bit lines LBL 0  to LBL 1023  which are provided in parallel along the column direction are connected. Namely, one sense amplifier S/A is provided for a pair of right and left bit lines RBL and LBL. Memory cells MC each having an FBC are respectively provided at intersection points of the word lines RWL 0  to RWL 255  and the bit lines RBL 0  to RBL 1023  and at intersection points of the word lines LWL 0  to LWL 255  and the bit lines LBL 0  to LBL 1023 . The structure of the memory cell MC is the same as that in  FIG. 1 . 
   On the right side of the sense amplifiers S/A 0  to S/A 1023 , a dummy word line RDWL is provided in parallel with the word lines RWL 0  to RWL 255 , and on the left side of the sense amplifiers S/A 0  to S/A 1023 , a dummy word line LDWL is provided in parallel with the word lines LWL 0  to LWL 255 . Dummy cells DMC having the same structure as the memory cell MC are respectively provided at intersection points of the dummy word line RDWL and the bit lines RBL 0  to RBL 1023  and at intersection points of the dummy word line LDWL and the bit lines LBL 0  to LBL 1023 . 
   Moreover, the semiconductor memory device according to this embodiment is provided with a control circuit CTL, and this control circuit CTL generates and supplies signals and voltages required for the operation of this semiconductor memory device when necessary. 
   A basic read operation of the memory cell array thus configured can be performed in the following manner. First, out of left and right cell arrays of this memory cell array, the cell array from which data is read is selected, one word line WL (RWL or LWL) included in the selected cell array rises, and at the same time, the dummy word line DWL (LDWL or RDWL) included in the cell array on the opposite side rises. Intermediate level (½ level) data between the “0” data and the “1” data is held in each of the dummy cells DMC connected to the dummy word line DWL. However, it is also possible to write the “0” data and the “1” data alternately into the dummy cells DMC and average each of these pairs by a circuit not shown at the time of the read operation to create a state where the ½ level data is written. Further, it is also possible to average every plural pairs or all the pairs to create the state where the ½ level data is written. 
   Then, in this embodiment, by comparing a cell current flowing through the memory cell MC from which data is to be read and a reference current flowing through the ½ level dummy cell DMC and judging which of the cell current and the reference current is larger, it can be judged whether the data held in the memory cell MC is the “0” data or the “1” data. 
     FIG. 3  is a diagram showing an example of the circuit configuration of a sense amplifier S/A and a column selection circuit CSC. In  FIG. 3 , two sense amplifiers S/A 0  and S/A 1  and their corresponding one column selection circuit CSC 0  are shown, and the other sense amplifiers S/A also have the same configuration. Namely, in this embodiment, one column selection circuit CSC is provided for two sense amplifiers S/A. 
   The sense amplifiers S/A 0  and S/A 1  each include transfer gates TG 100  and TG 101 , N-type FETs N 100  to N 105 , and P-type FETs P 100  to P 105 . The transfer gate TG 100  includes an N-type FET TGN 100  and a P-type FET TGP 100 . The transfer gate TG 101  includes an N-type FET TGN 101  and a P-type TGP 101 . 
   Moreover, as wiring, a signal line FITL, a data line DQ 0 , a data line BDQ 0 , a data line DQ 1 , a data line BDQ 1 , a signal line FB, a voltage supply line SAP, a voltage supply line VBLH, a signal line BLOADON, a voltage supply line BSAN, a signal line FITR, a signal line CSL 0 , and a signal line WCSL 0  are provided. A positive voltage (1.5 V, for example) is constantly applied to the voltage supply line VBLH. 0 V or a negative voltage (−1.5 V, for example) is selectively applied to the voltage supply line BSAN, and 0 V or a positive voltage (1.5 V, for example) is selectively applied to the voltage supply line SAP. 
   The column selection circuit CSC 0  includes inverter circuits IN 100  and IN 101 , AND circuits AN 100  to AN 103 , and NOR circuits NR 100  and NR 101 . A signal A 9R  and a signal BA 9R  are inputted to the column selection circuit CSC 0 . In this embodiment, one signal line CSL and one signal line WCSL are provided for one column selection circuit CSC. 
   A signal of the signal line FITL, data of the data line DQ 0 , data of the data line BDQ 0 , data of the data line DQ 1 , data of the data line BDQ 1 , a signal of the signal line FB, a voltage of the voltage supply line SAP, a voltage of the voltage supply line VBLH, a signal of the signal line BLOADON, a voltage of the voltage supply line BSAN, a signal of the signal line FITR, the signal A 9R , and the signal BA 9R  are supplied from the control circuit CTL. A signal of the signal line CSL 0  and a signal of the signal line WCSL 0  are supplied from the column decoder circuit not shown here. 
   Incidentally, the transfer gates TG 100  and TG 101  constitute a first switch circuit which turns on/off the connection between the sense amplifier S/A and the bit lines RBL and LBL, and FETs N 103  and N 104  constitute a second switch circuit which turns on/off the connection between the sense amplifier S/A and the data lines DQ 0 , BDQ 0 , DQ 1 , and BDQ 1 . Moreover, the signal line CSL 0  constitutes a first control signal line, the signal line FB constitutes a second control signal line, and the signal line WCSL 0  constitutes a third control signal line. 
     FIG. 4  is a diagram showing operation waveforms in a refresh operation. At a point in time T 10 , one word line WL rises, and at the same time, the dummy word line DWL in the cell array on the opposite side rises.  FIG. 4  shows a case where one word line RWL on the right side of the sense amplifiers S/A 0  to S/A 1023  rises, and one dummy word line LDWL on the left side of the sense amplifiers S/A 0  to S/A 1023  rises as an example. In short, a case where the memory cells MC in the right cell array in the drawing are refreshed is assumed here. 
   At this point in time T 10 , the signal line BLOADON goes low, whereby the FETs P 100  and P 104  are turned on. Since the signal lines FITL and FITR are high, the FETs N 102  and N 105  are on. Since the bit lines RBL 0  to RBL 1023  are low, the FETs P 101  and P 105  are on. Therefore, a current flows from the voltage supply line VBLH to which the positive voltage is supplied to the bit lines LBL 0  to LBL 1023  and RBL 0  to RBL 1023 . 
   Accordingly, a current (cell current) which corresponds to data held in each of the memory cells MC, from which the data is to be read, flows to the bit lines RBL 0  to RBL 1023  in the right cell array which is to be refreshed, and a ½ level current (reference current) held in the dummy cells DMC flows to the bit lines LBL 0  to LBL 1023  in the left cell array which is not to be refreshed. Consequently, nodes RSN 0  to RNS 1023  connected to the memory cells MC each come to have a voltage corresponding to the “0” data or the “1” data held in each of the memory cells MC, and nodes LSN 0  to LSN 1023  connected to the dummy cells DMC come to have an intermediate voltage between the “0” data and the “1” data. 
   Then, at a point in time T 11 , the signal line BLOADON goes high, whereby the FETs P 100  and P 104  are turned off. Therefore, the supply of the voltage from the voltage supply line VBLH is stopped. Simultaneously with this, the voltage supply line SAP goes high, and the voltage supply line BSAN goes low. As a result, as concerns the nodes LSN 0  to LSN 1023  and RSN 0  to RSN 1023 , the node with the upper voltage comes to have the positive voltage (1.5 V, for example) and the node with the lower voltage comes to have the negative voltage (−1.5 V. for example), respectively. 
   For example, when the “0” data is held in the memory cell MC connected to RBL 0 , the threshold value of the memory cell MC becomes high, whereby the voltage of the node RSN 0  becomes higher than the voltage of the node LSN 0 . Accordingly, the FET P 103  is turned on and the FET P 102  is turned off. Hence, the positive voltage (1.5 V, for example) of the voltage supply line SAP is transmitted to the node RSN 0 . On the other hand, the FET N 100  is turned on and the FET N 101  is turned off. Hence, the negative voltage (−1.5 V, for example) of the voltage supply line BSAN is transmitted to the node LSN 0 . 
   Thereafter, at a point in time T 12 , the signal lines FITL and FITR go low. Therefore, the FETs N 102  and N 105  are turned off. Moreover, at the same time at which the signal line FB goes high, one signal out of the signal A 9R  and the signal BA 9R  which is on the side of the cell array to be refreshed goes high, and the transfer gate TG 100  or TG 101  is turned on. 
   In the aforementioned example, the cell array on the right side in the drawing is to be refreshed, whereby the signal A 9R  goes high. Therefore, an output of the AND circuit AN 100  goes high and an output of NOR 100  goes low, whereby the transfer gate TG 100  is turned on. Accordingly, the negative voltage (−1.5 V, for example) is applied to the bit line RBL 0  and applied to the drain D of the memory cell MC selected by the word line WL. As a result, the “0” data is written into the memory cell MC and refreshed. 
   As can be seen from the above, in the refresh operation, the signal lines CSL 0  to CSL 511  and WCSL 0  to WCSL 511  do not rise, whereby write-back to the memory cells MC is performed on all of the memory cells MC whose word line RWL or LWR is high on the side of the cell array to be refreshed (all of the bit lines RBL 0  to RBL 1023  or LBL 0  to LBL 1023 ) during a period when the signal line FB is high. 
     FIG. 5  is a diagram showing operation waveforms when a continuous write operation is performed by switching the column address to select a column. 
   As can be seen from  FIG. 5 , the same operation as the aforementioned refresh operation is performed from a point in time T 20  to a point in time T 23 . Namely, when a case where the continuous write operation is performed on the cell array on the right side of the sense amplifiers S/A 0  to S/A 1023  is assumed, one word line RWL on the right side of the sense amplifiers S/A 0  to S/A 1023  rises and one dummy word line LDWL on the left side of the sense amplifiers S/A 0  to S/A 1023  rises. Then, the signal line FB goes high, and the refresh operation is performed. As a result, holes which have disappeared due to a charge pumping phenomenon are made up. 
   Then, between a point in time T 24  and a point in time T 25 , the 31st signal line CSL 31  and the 31st signal line WCSL 31  go high. Thereby, the FET N 103  and the FET N 104  of the sense amplifier S/A 62  are turned on. If data to be written is assumed here to be “1”, the positive voltage (1.5 V, for example) is supplied to the data line DQ 0  and the negative voltage (−1.5 V, for example) is supplied to the data line BDQ 0 . Hence, the node LSN 62  goes high and the node RSN 62  goes low. 
   Since the signal A 9R  is also high, an output of the NOR circuit  100  goes low, and the transfer gate TG 100  of the sense amplifier S/A 62  is turned on. Consequently, the bit line RBL 62  goes high (1.5 V, for example), and the “1” data is written into the memory cell MC. 
   Incidentally, in this embodiment, the signal line CSL 31  and the signal line WCSL 31  for the sense amplifier S/A 62  is shared with the sense amplifier S/A 63 . Therefore, data inputted from the data lines DQ 1  and the BDQ 1  is also written as it is into the memory cell MC connected to the bit line RBL 63 . 
   Then, in the example in  FIG. 5 , between the point in time T 25  and a point in time T 26 , the 10th signal line CSL 10  and the 10th signal line WCSL 10  go high, and the “0” data is written into the memory cell MC connected to the bit line RBL 20 . Subsequently, between the point in time T 26  and a point in time T 27 , the 112th signal line CSL 112  and the 112th signal line WCSL 112  go high, and the “0” data is written into the memory cell MC connected to the bit line RBL 224 . 
   Finally, at a point in time T 28 , the word line RWL which has risen is driven low, the dummy word line LDWL which has also risen is driven low, and the continuous write operation on the memory cells MC connected to one word line RWL is completed. 
   As can be seen from  FIG. 5 , the signal of the signal line FB provided along the row direction rises only once between the point in time T  22  and the point in time T 23 , and thereafter it is deactivated. In the write operation, only the transfer gates TG 100  and TG 101  associated with the signal line WCSL which has risen are turned on, and data is written into the memory cells MC in sequence. In a column not selected, the signal line WCSL remains low, and the transfer gates TG 100  and TG 101  are off, whereby the bit lines LBL and RBL are in a floating state, and therefore no cell current flows, resulting in a reduction in current consumption. 
     FIG. 6  is a diagram showing operation waveforms when a continuous read operation is performed by switching the column address. As can be seen from  FIG. 6 , similarly to the aforementioned write operation, the refresh operation is performed between a point in time T 30  and a point in time T 33 . In this refresh operation, data read from the memory cells MC are held in the sense amplifiers S/A 0  to S/A 1023 , and the nodes LSN 0  to LSN 1023  and RSN 0  to RSN 1023  come to have voltages corresponding to the data. 
   If it is assumed here that data is read from the memory cell MC on the right side of the sense amplifiers S/A 0  to S/A 1023 , when the memory cell MC holds the “0” data, the corresponding node RNS goes high and the corresponding node LSN goes low. When the memory cell MC holds the “1” data, the corresponding node RNS goes low, and the corresponding node LSN goes high. 
   Then, by driving the signal line CSL 31  high between a point in time T 34  and a point in time T 35 , the FETs N 103  and N 104  are turned on, and data latched by the nodes LSN 62  and RSN 62  are read from the data line DQ 0  and the data line BDQ 0 . More specifically, both the data lines DQ 0  and BDQ 0  are precharged high. Since the node RNS 62  is high, the data line BDQ 0  remains high. Since the node LSN 62  is low, the voltage of the data line DQ 0  drops from high level. By detecting these changes of the data lines DQ 0  and BDQ 0 , the data in the memory cell MC is read. During this period, the signal line WCSL 31  remains low. Therefore, the transfer gates TG 100  and TG 101  are turned off, whereby the node LSN 62  is separated from the bit line RBL 62  and the node RSN 62  is separated from the bit line LBL 62 . 
   Incidentally, in this embodiment, the signal line CSL 31  of the sense amplifier S/A 62  is shared with the sense amplifier S/A 63 . Hence, data held in the sense amplifier S/A 63  is simultaneously read from the data lines DQ 1  and BDQ 1 , but unnecessary data has only to be abandoned. 
   In the same manner as above, in the example in  FIG. 6 , next, between the point in time T 35  and a point in time T 36 , data held in the nodes LSN 20  and RSN 20  of the sense amplifier S/A 20  are read by driving the signal line CSL 10  high. Subsequently, between the point in time T 36  and a point in time T 37 , data held in the nodes LSN 224  and RSN 224  of the sense amplifier S/A 224  are read by driving the signal line CSL 112  high. 
   Finally, at a point in time T 38 , the word line RWL which has risen is driven low, the dummy word line LDWL which has also risen is driven low, and the continuous read operation on the memory cells MC connected to one word line RWL is completed. 
   Incidentally, in this embodiment, as shown in  FIG. 7 , an input unit of the signal lines CSL 0  to CSL 511  (signal lines which control the connection between the data lines DQ 0 , BDQ 0 , DQ 1 , and BDQ 1  and the sense nodes RSN and LSN) and an input unit of the signal lines WCSL 0  to WCSL 511  (signal lines which control the connection between the bit lines RBL and LBL and the sense nodes RSN and LSN) are the same in that two sense amplifiers S/A are their controlled objects. But, the present invention is not limited to this aspect. For example, as shown in  FIG. 8 , it is possible that one signal line CSL is provided to control two sense amplifiers S/A and one signal line WCSL is provided to control four sense amplifiers S/A. In other words, it is possible to provide one signal line CSL for two pairs of bit lines and one signal line WCSL for four pairs of bit lines. Similarly, one signal line WCSL can be provided for 8 pairs, 16 pairs, . . . of bit lines. 
   In  FIG. 8 , in the continuous write operation, for example, when the sense amplifier to which the memory cell MC, into which data is written, is connected is S/A 3 , not only the sense amplifier S/A 3  writes data of the data lines DQ 1  and BDQ 1  into the memory cell MC, but also the sense amplifiers S/A 0  to S/A 2  are activated and latched data is rewritten. Therefore, current consumption increases. But, since the number of column selection circuits CSC can be reduced, the chip area can be correspondingly reduced. In other words, the range which the signal line WCSL can control needs to be determined in consideration of a trade-off between chip area and current consumption. 
   Second Embodiment 
   In the aforementioned first embodiment, every time data to be written is held in the sense amplifier S/A, the data is written into the memory cell MC, but in the second embodiment, after all data to be written are held in the sense amplifiers S/A 0  to S/A 1023 , data latched in the sense amplifier S/A 0  to S/A 1023  are written into the memory cells MC all at once. 
     FIG. 9  is a diagram showing an example of the configuration of the sense amplifiers S/A 0  and S/A 1 , and  FIG. 10  is a diagram showing the layout of the sense amplifiers S/A 0  to S/A 1023  and the signal lines CSL 0  to CSL 511 . Incidentally, the placement of the word lines RWL 0  to RWL 255  and LWL 0  to LWL 255 , the bit lines RBL 0  to RBL 1023  and LBL 0  to LBL 1023 , the dummy word lines RDWL and LDWL, and the memory cells MC is the same as that in  FIG. 2  described above. 
   As can be seen from these figures, the basic configuration of the sense amplifier S/A according to this embodiment is the same as that in the aforementioned first embodiment. However, the column selection circuit CSC is omitted, and a signal line FBR, a signal line BFBR, a signal line FBL, and a signal line BFBL are additionally provided. 
   The signal line FBR is connected to a gate of the N-type FET TGN 100  in the transfer gate TG 100 , and the signal line BFBR is connected to a gate of the P-type FET TGP 100  in the same transfer gate TG 100 . The signal line FBL is connected to a gate of the N-type FET TGN 101  in the transfer gate TG 101 , and the signal line BFBL is connected to a gate of the P-type FET TGP 101  in the same transfer gate TG 101 . 
   As can be seen from  FIG. 10 , in this embodiment, the signal lines CSL 0  to CSL 511  are each provided for two sense amplifiers S/A, and unlike the first embodiment, the column selection circuit CSC and the signal line WCSL are not provided. 
   A refresh operation in a semiconductor memory device according to this embodiment is the same as that in  FIG. 4  in the first embodiment, and a continuous read operation is also the same as that in  FIG. 6  in the first embodiment. However, a continuous write operation is different from that in the first embodiment. 
     FIG. 11  is a diagram showing an example of operation waveforms when a continuous write operation is performed by switching the column address to select a column. Here, a case where the continuous write operation is performed on memory cells on the right side of the sense amplifiers S/A 0  to S/A 1023  is assumed. 
   As shown in  FIG. 11 , between a point in time T 40  and a point in time T 43 , a refresh operation to make up for holes which have disappeared due to the charge pumping phenomenon is performed as in the aforementioned first embodiment. However, this embodiment is different from the aforementioned first embodiment in that when data is written back to the memory cells MC, the transfer gate TG 100  is turned on by driving the signal line FBR high and the signal line BRFR low in place of driving the signal line FB between a point in time T 42  and the point in time T 43 . 
   Then, between a point in time T 44  and a point in time T 45 , the 31st signal line CSL 31  goes high. Thereby, the FET N 103  and the FET N 104  of the sense amplifier S/A 62  are turned on. If data to be written is assumed here to be “1”, the positive voltage (1.5 V, for example) is supplied to the data line DQ 0  and the negative voltage (−1.5 V, for example) is supplied to the data line BDQ 0 . Hence, the node LSN 62  goes high and the node RSN 62  goes low. As a result, the “1” data is held in the sense amplifier S/A 62 . 
   Incidentally, in this embodiment, the signal line CSL 31  for the sense amplifier S/A 62  is shared with the sense amplifier S/A 63 . Therefore, the FETs N 103  and N 104  of the sense amplifier S/A 63  are also turned on, and hence write voltages of the data lines DQ 1  and BDQ 1  are simultaneously written into the sense amplifier S/A 63 . 
   Then, in the example in  FIG. 11 , between the point in time T 45  and a point in time T 46 , the 10th signal line CSL 10  goes high, and the “0” data is held in the sense amplifier S/A 20 . Subsequently, between the point in time T 46  and a point in time T 47 , the 112th signal line CSL 112  goes high, and the “0” data is held in the sense amplifier S/A 224 . 
   Finally, between a point in time T 48  and a point in time T 49 , the signal line FBR goes high and the signal line BRFR goes low, whereby the transfer gates TG 100  are turned on. As a result, data held in the respective sense amplifiers S/A 0  to S/A 1023  are written into the respective memory cells MC all at once. 
   Incidentally, data of the data line DQ 0 , data of the data line BDQ 0 , data of the data line DQ 1 , data of the data line BDQ 1 , a signal of the signal line FBL, a signal of the signal line BFBL, a signal of the signal line FITL, a signal of the signal line BLOADON, a signal of the signal line FITR, a signal of the signal line BFBR, a signal of the signal line FBR, a voltage of the voltage supply line SAP, a voltage of the voltage supply line VBLH, and a voltage of the voltage supply line BSAN are supplied from the control circuit CTL shown in  FIG. 2 . A signal of the signal line CSL is supplied from the column decoder circuit not shown here. 
   Moreover, the signal lines FBL, BFBL, FBR, and BFBR constitute a first control signal line which controls on/off of the transfer gates TG 100  and TG 101  as a first switch circuit in this embodiment, and the signal line CSL constitutes a second control signal line which controls on/off of the FETs N 103  and N 104  as a second switch circuit in this embodiment. 
   As can be seen from  FIG. 11 , during the relatively long time required to hold data to be written into the respective sense amplifiers S/A 0  to S/A 1023 , the bit lines RBL 0  to RBL 1023  and LBL 0  to LBL 1023  have 0 V, and no cell current flows. Therefore, the current consumption can be greatly reduced. During the period when data is written into the respective memory cells MC (between the point in time T 48  and the point in time T 49 ), the cell current flows through the respective bit lines RBL 0  to RBL 1023 , but the period is short, which does not lead to a great increase in current consumption. 
   In this embodiment, the area of a sense amplifier region can be reduced as compared with the aforementioned first embodiment since the column selection circuit CSC is omitted. However, at the end of the continuous write operation, a write operation on each of the memory cells MC is performed all at once, whereby the cycle time in the row direction is lengthened. Further, since the write operation is performed on all the memory cells MC, the write operation is performed even on the memory cells MC which have not been actually rewritten, which results in an increase in current consumption. Furthermore, the write operation is performed on the memory cells MC connected to one word line WL all at once, whereby the peak of the current rises, and hence noise in a semiconductor chip possibly increases. Accordingly, it is recommended to determine whether to adopt the first embodiment or the second embodiment in consideration of boundary conditions imposed on actual products (Which is the most important, a reduction in chip size, a reduction in cycle in the row direction, or a significant reduction in noise?). 
   It should be mentioned that the present invention is not limited to the aforementioned embodiments, and various changes may be made therein. For example, the application of the present invention is not limited to the FBC memory, and the present invention is applicable to a semiconductor memory device having a memory cell through which a current (usually, DC current) is passed in a write operation. For example, it is applicable to an MRAM (magnetic Random Access Memory). 
   To make high-speed access in the column direction possible, even in the MRAM, it is necessary to amplify and hold data in memory cells along the word line in sense amplifiers. This is a concept of so-called sense amplifier cache. Access to a page which needs a row address input is relatively slow, but once the page is opened, access to data in the page can be made at high speed by only switching the column address. 
   In this case, if the sense amplifier and the memory cell remain connected while the page is open, the current continues flowing through the memory cell. Accordingly, the current consumption can be further reduced if a path between the memory cell and the sense amplifier is cut off after the page is opened and data is transferred to the sense amplifier. 
   In the read operation, this path may remain cut off, but in the write operation, there are two methods of thinking as well. Namely, one is a method in which similarly to the first embodiment, at each write cycle, a path between a sense amplifier and a memory cell corresponding to each other is opened, and data is written into the memory cell. The other is a method in which similarly to the second embodiment, in a continuous write operation, data held in sense amplifiers are only rewritten, and after a continuous write cycle is completed, all paths between the sense amplifiers and memory cells are opened, and data is written into the memory cells. 
   Moreover, the aforementioned FET and transfer gate are examples of the switch circuit, and switch circuits with other configurations can also be used.