Abstract:
Provided are: a circuit device which has improved connection reliability in a solder joint portion by suppressing the occurrence of sink of solder; and a method for manufacturing the circuit device. In a method for manufacturing a circuit device of the present invention, a plurality of solders ( 19 ), which are apart from each other, are firstly formed on the upper surface of a pad ( 18 A), and a chip component ( 14 B) and a transistor ( 14 C) are affixed at the same time. After that, a solder paste ( 31 ) is supplied to the upper surface of the pad ( 18 A) using a syringe ( 30 ), a heatsink ( 14 D) is mounted on top of the solder paste ( 31 ), and melting is caused by a reflow process. There is little risk of sinking of the solders ( 19 ) in the present invention since the solders ( 19 ) are discretely arranged on the upper surface of the pad ( 18 A).

Description:
[0001]    REFERENCE TO RELATED APPLICATIONS 
         [0002]    This application is a national stage application under 35 USC 371 of International Application No. PCT/JP2011/005716, filed Oct. 12, 2011, which claims the priority of Japanese Patent Application No. 2010-247063, filed Nov. 4, 2010, the entire contents of which are incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0003]    The present invention relates to a circuit device and a method for manufacturing the same, and relates particularly to a method for manufacturing a circuit device for soldering a large circuit element. 
       BACKGROUND OF THE INVENTION 
       [0004]    With reference to  FIG. 8 , a conventional method for manufacturing a circuit device is described. Here, a description is given of a method for manufacturing a hybrid integrated circuit device in which a conductive pattern  108  and circuit elements are formed on a surface of a substrate  106  (refer, for example, to Patent Document 1 below). 
         [0005]    Referring to  FIG. 8A , first, solder  109  is formed at portions on a surface of the conductive pattern  108  formed on the surface of the substrate  106 . The substrate  106  is for example a metallic substrate made of a metal such as aluminum, and is insulated from the conductive pattern  108  by an insulating layer  107 . Pads  108 A, pads  108 B, and pads  108 C are formed by the conductive pattern  108 . In a later step, a heat sink is attached to an upper portion of each pad  108 A. In a later step, a small-signal transistor is attached to each pad  108 B. In a later step, a lead is attached to each pad  108 C. Here, the solder  109  is formed on the surfaces of the relatively large pads  108 A and the pads  108 C. 
         [0006]    Referring to  FIG. 8B , next, a small-signal transistor  104 C and a chip component  104 B are attached with solder. In this step, heating is performed until the solder for connecting the transistor  104 C and the like melts. Consequently, the solder  109  formed on the pads  108 A and the pads  108 C in the previous step also melt. 
         [0007]    Referring to  FIG. 8C , next, the small-signal transistor  104 C is connected to predetermined portions of the conductive pattern  108  with thin wires  105 B. 
         [0008]    Referring to  FIG. 9A , next, a heat sink  111  and a lead  101  are attached to each pad  108 A and each pad  108 C, respectively, by melting the solder  109  previously formed thereon. Here, the heat sink  111  has a power transistor  104 A placed thereon, and is attached onto the pad  108 A via the solder  109  previously formed. Then, the transistor  104 A is connected to a desired portion of the conductive pattern  108  with a thick wire  105 A. 
         [0009]    Referring to  FIG. 9B , a sealing resin  102  is formed to cover the circuit elements and the conductive pattern  108  formed on the surface of the substrate  106 . With the steps above, a hybrid integrated circuit device  100  is manufactured. 
         [0010]    Patent Document 1: Japanese Patent Application Publication No. 2002-134682 
       SUMMARY OF THE INVENTION 
       [0011]    Referring to  FIG. 10 , the conventional manufacturing method described above, however, has a problem of dewetting of the molten solder  109 .  FIG. 10A  is a plan view of the substrate  106  on which dewetting has occurred,  FIG. 10B  is a sectional view thereof, and  FIG. 10C  is an enlarged sectional view of the portion where the dewetting has occurred. 
         [0012]    Referring to  FIGS. 10A and 10B , the “dewetting” is a phenomenon where the solder  109  applied to the entire surface of the pad  108 A is attracted to one side when melted. The pad  108 A to which the heat sink  111  is to be attached is formed into a large quadrangle, each side of which is, for example, 9 mm or longer. A large amount of solder is therefore deposited onto the pad  108 A compared to other portions, and consequently a large surface tension acts on the molten solder  109 , causing dewetting of the solder. 
         [0013]    When the solder  109  dewets, a circuit element is not joined to the pad  108 A at the dewetting portion. Hence, the thermal resistance around that dewetting portion increases. Further, the dewetting lowers the strength of solder joint, which lowers reliability of the connection at a solder joint against temperature change. 
         [0014]    Referring to  FIG. 10C , a cause of the dewetting is an alloy layer  110  formed between the pad  108 A and the solder  109 . When solder paste is deposited onto the upper portion of the pad  108 A and is then heated and melted, an intermetallic compound of copper and tin is formed, the copper being a material of the pad  108 A, the tin being a material of the solder. In this drawing, a layer made of the intermetallic compound is shown as the alloy layer  110 . Specifically, the alloy layer  110  is about several micrometers thick, and is made of an intermetallic compound having a composition of Cu6Sn5 or Cu3Sn. This alloy layer  110  provides extremely poor solder wettability, compared to copper which is the material of the pad  108 A. The formation of the alloy layer  110  providing poor solder wettability causes the solder dewetting. Further, when the solder is melted multiple times, the alloy layer  110  formed on the upper surface of the pad  108 A becomes thick, which makes the solder wettability even worse. In a description below, an alloy layer made of copper and tin is called a Cu/Sn alloy layer. 
         [0015]    In recent years, lead-free solder has been used due to environmental consciousness. When lead-free solder is used as the solder  109 A, a thicker alloy layer  110  is formed, and then the above-described dewetting problem occurs noticeably. This is because the lead-free solder contains more tin than tin-lead eutectic solder. Specifically, the percentage of tin contained in general tin-lead eutectic solder is about 60 weight percent, whereas the percentage of tin contained in lead-free solder is about 90 weight percent. 
         [0016]    Further, when solder paste in which a rosin-based flux is added is used to aim productivity improvement or other purposes, there arises a problem in which the molten solder paste does not wet. This is because the rosin-based flux is less active than a water-soluble flux. Moreover, the problem of the solder paste not wetting is noticeable in a case where an upper surface of a copper pad is coated with a nickel film and where a rosin-based solder paste is applied to an upper surface of this nickel film. 
         [0017]    Poor wettability refers to a situation where solder does not spread because no alloy layer is formed between a pad and the solder. The dewetting, on the other hand, refers to a situation where although an alloy layer is formed between the solder and the pad and the solder wets and spreads temporarily thereon, the solder is soon attracted to one side due to the surface tension of the solder. Hence, when the solder dewetting occurs, the alloy layer is exposed on the upper surface of the pad to cause void formation, as will be described layer. 
         [0018]    Further, assume a case where a circuit element is soldered, with a Cu/Sn alloy layer being formed thickly at a border portion between solder and a pad. Then, since a thick Cu/Sn layer has a low mechanical strength, connection reliability of soldering might be degraded. 
         [0019]    The present invention has been made in view of the above problems, and a main objective thereof is to provide a method for manufacturing a circuit device in which occurrence of solder dewetting is prevented to improve connection reliability at a solder joint. 
         [0020]    A circuit device of the present invention comprises: a substrate; a pad formed on an upper surface of the substrate; and a circuit element attached to the pad with solder. An alloy layer made of an intermetallic compound of a metal forming the solder and a metal forming the pad is formed at a border between the solder and the pad, and the alloy layer has a first alloy layer and a second alloy layer thicker than the first alloy layer. 
         [0021]    A method of manufacturing a circuit device of the present invention comprises the steps of: forming a plurality of portions of first solder on an upper surface of a pad placed on a circuit substrate, the portions being spaced away from each other; applying solder paste to cover the portions of first solder and the upper surface of the pad; and placing a circuit element on an upper surface of the solder paste and attaching the circuit element to the pad by heating. 
         [0022]    In the circuit device of the present invention, the alloy layer provided at a border between the pad and each portion of solder for soldering the circuit element includes the thick first alloy layer and the thin second alloy layer. Thus, the connection strength is secured by the thin alloy layer, which improves the reliability of connection between the solder and the pad. 
         [0023]    In the method for manufacturing a circuit device of the present invention, multiple portions of first solder are placed away from each other on the upper surface of the relatively large pad and bonded. On the upper surface of the pad, multiple pads of first solder are provided discretely, instead of a single solder pad. Thereby, a surface tension acting on each portion of first solder is reduced to prevent the dewetting from occurring in the step of forming the first solder. 
         [0024]    Further, since the dewetting of the first solder does not occur, the Cu/Sn alloy layer is not exposed on the upper surface of the pad at a region where no first solder is formed. Since the Cu/Sn alloy layer having poor solder wettability is not exposed, the dewetting is prevented in the next step in which additional solder paste is melted. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1  is diagrams showing a circuit device manufactured by a preferred embodiment of the invention,  FIG. 1A  being a perspective view,  FIG. 1B  being a sectional view, and  FIG. 1C  being an enlarged sectional view. 
           [0026]      FIG. 2  is diagrams showing a method for manufacturing the circuit device of the preferred embodiment of the invention,  FIG. 2A  being a plan view,  FIG. 2B  being a sectional view. 
           [0027]      FIG. 3  is diagrams showing the method for manufacturing the circuit device of the preferred embodiment of the invention,  FIG. 3A  being a sectional view,  FIG. 3B  being a plan view, and  FIG. 3C  being an enlarged plan view. 
           [0028]      FIG. 4  is diagrams showing the method for manufacturing the circuit device of the preferred embodiment of the invention,  FIG. 4A  being a sectional view,  FIG. 4B  being a sectional view, and  FIG. 4C  being a sectional view. 
           [0029]      FIG. 5  is diagrams showing the method for manufacturing the circuit device of the preferred embodiment of the invention,  FIG. 5A  being a plan view,  FIG. 5B  being an enlarged plan view. 
           [0030]      FIG. 6  is diagrams showing the method for manufacturing the circuit device of the preferred embodiment of the invention,  FIG. 6A  being a sectional view,  FIG. 6B  being a sectional view, and  FIG. 6C  being an enlarged sectional view. 
           [0031]      FIG. 7  is diagrams showing the method for manufacturing the circuit device of the preferred embodiment of the invention,  FIG. 7A  being a sectional view,  FIG. 7B  being a sectional view. 
           [0032]      FIG. 8  is diagrams showing a conventional method for manufacturing a circuit device,  FIGS. 8A to 8C  each being a sectional view. 
           [0033]      FIG. 9  is diagrams showing the conventional method for manufacturing a circuit device,  FIGS. 9A  being a sectional view,  FIG. 9B  being a sectional view. 
           [0034]      FIG. 10  is diagrams showing the conventional method for manufacturing a circuit device,  FIGS. 10A  being a plan view,  FIG. 10B  being a sectional view,  FIG. 10C  being an enlarged sectional view. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     First Embodiment  
       [0035]    In this embodiment, with reference to  FIG. 1 , a description is given of the configuration of a hybrid integrated circuit device  10  as an example of a circuit device of a preferred embodiment of the invention.  FIG. 1A  is a perspective view of the hybrid integrated circuit device  10 , and  FIG. 1B  is its sectional view.  FIG. 1C  is a sectional view showing how a transistor  14 A (a circuit element) is attached. 
         [0036]    Referring to  FIGS. 1A and 1B , in the hybrid integrated circuit device  10 , a conductive pattern  18  is formed on a surface of the substrate  16 , and circuit elements such as transistors are attached to the conductive pattern  18  with solder  19 . Then, at least the top surface of the substrate  16  is sealed by sealing resin  12 . 
         [0037]    The substrate  16  is a metallic substrate made of a metal such as aluminum or copper or a substrate made of a resin material such as epoxy resin. If an aluminum substrate is employed as the substrate  16 , main surfaces of the substrate  16  are both coated with an anode oxide film formed through an alumite treatment. A specific size of the substrate  16  is about, for example, length×width×thickness=60 mm×40 mm×1.5 mm. 
         [0038]    An insulating layer  17  is formed, covering an entire upper surface of the substrate  16 . The insulating layer  17  is made for example of epoxy resin which is highly filled with a filler of Al203 or the like. Thereby, heat produced by the embedded circuit elements can be released well to the outside through the substrate  16 . A specific thickness of the insulating layer  17  is about, for example, 50 μm. 
         [0039]    The conductive pattern  18  is formed by a metal film made mainly of copper, and is formed on a surface of the insulating layer  17  so that a predetermined electric circuit is implemented. By the conductive pattern  18 , pads  18 A, pads  18 C, and pads  18 E are formed. Each pad will be described in detail later with reference to  FIG. 2 . 
         [0040]    Circuit elements such as the power transistor  14 A, a chip component  14 B, and a small-signal transistor  14 C are attached to predetermined portions of the conductive pattern  18  with the solder  19 . The power transistor  14 A is improved in its heat release performance by being attached to the pad  18 A with a heat sink  14 D interposed therebetween. The chip component  14 B is attached at its both electrodes to the conductive pattern  18  with the solder  19 . The small-signal transistor  14 C is attached at its rear surface to the pad  18 C via the solder  19 . For example, the power transistor  14 A is a transistor through which a current of  1  A or larger flows, and the small-signal transistor  14 C is a transistor through which a current of smaller than  1  A flows. An electrode at a surface of the power transistor  14 A is connected to the conductive pattern  18  with a thick wire  15 A which is a metal wire having a thickness of 100 μm or more. An electrode formed on a surface of the small-signal transistor  14 C is connected to the conductive pattern  18  with thin wires  15 B having a thickness of about 80 μm or less. 
         [0041]    Circuit elements that can be mounted on the substrate  16  are semiconductor elements such as transistors, LSI chips, and diodes. In addition, chip components such as chip resistors, chip capacitors, inductors, thermistors, antennas, and oscillators can be employed as the circuit elements. Moreover, a resin-sealed circuit device can be embedded in the hybrid integrated circuit device  10  as a circuit element. In this embodiment, the transistor  14 A having the heat sink  14 D attached to its lower surface can be regarded as one circuit element. 
         [0042]    A lead  11  is attached to each pad  18 E provided at a peripheral portion of the substrate  16  and plays a role in receiving inputs from and sending outputs to the outside. Although a number of leads  11  are attached to a single side here, the leads  11  can be led from four sides of the substrate  16  or from two opposite sides thereof. 
         [0043]    A sealing resin  12  is formed through transfer molding using a thermosetting resin. Referring to  FIG. 1B , the sealing resin  12  covers the conductive pattern  18  and the circuit elements formed on the surface of the substrate  16 . The side surface and the rear surface of the substrate  16  are also covered by the sealing resin  12 , whereby the moisture resistance of the whole device can be improved. The rear surface of the substrate  16  does not have to be covered by the sealing resin  12  in order to improve the heat release performance of the substrate  16 . Further, the sealing may be done not with the sealing resin  12 , but with a case member. 
         [0044]    Referring to  FIG. 1C , a description is given of how the heat sink  14 D is bonded to the pad  18 A. Specifically, the heat sink  14 D is being attached, with the solder  19 , to the upper surface of the pad  18 A made mainly of copper, and an electrode of the transistor  14 A at its lower side is being attached to an upper surface of the heat sink  14 D. 
         [0045]    With the thick wire  15 A, the electrode on the upper surface of the power transistor  14 A is connected to a pad-shaped portion of the conductive pattern  18  located near the pad  18 A. As described above, placing the heat sink  14 D between the transistor  14 A and the pad  18 A increases a heat transfer area, so that heat released by the transistor  14 A is transferred to the substrate  16  well. 
         [0046]    When a MOSFET is used as the transistor  14 A, a drain electrode provided at a lower surface of the transistor  14 A is connected to the pad  18 A via the heat sink  14 D, and a source electrode provide at the upper surface of the transistor  14 A is connected, with the thin line  15 A, to a different portion of the conductive pattern  18  located near the pad  18 A. Then, a gate electrode placed at the upper surface of the transistor  15 A is connected, with the thick wire  15 A or a thin wire, to a different portion of the conductive pattern  18  placed around the pad  18 A. 
         [0047]    An intermetallic compound is formed at a border portion between the upper surface of the pad  18 A and the solder  19 , the intermetallic compound being formed by the material of the solder pad  18 A and the material of the solder  19 . When, for example, the pad  18 A is made of copper and the solder  19  is made mainly of tin, the Cu/Sn alloy layer described above is formed. Particularly when lead-free solder made mainly of tin is used as the solder  19 , a thick Cu/Sn alloy layer is likely to be formed. 
         [0048]    In this embodiment, the heat sink to the upper surface of which the transistor  14 A is attached is used as an element attached to the upper surface of the pad  18 A. Instead, a different element may be attached to the pad  18 A. For example, the transistor  14 A may be directly attached to the upper surface of the pad  18 A. 
         [0049]    As an advantage of this embodiment, the above-described alloy layer is partly reduced in thickness to improve the reliability of connection between the solder  19  and the pad  18 A. Specifically, an alloy layer made of a Cu/Sn alloy is brittle. Due to this property, when the alloy layer is formed thickly, while the device is in use, the solder  19  and the pad  18 A might detach from each other at a portion where the alloy layer is formed. To prevent this, the alloy layer formed is partly reduced in thickness. Thereby, although the strength is low at a thick alloy layer  22 , the strength is secured at a thin alloy layer  23 . Thus, cracking occurring while the device is in use is suppressed at this alloy layer portion. 
         [0050]    The thick alloy layer  22  is formed into portions arranged in matrix at the upper surface of the pad  18 A, and the thin alloy layer  23  is formed in grids extending between the portions of the thick alloy layer  22 . The grid formation of the thin alloy layer  23  prevents detachment of the alloy layer  23  over the entire pad  18 A. 
         [0051]    The thin alloy layer  22  is placed at the four sides of the pad  18 A, and this also suppresses detachment between the solder  19  and the pad  18 A. 
         [0052]    Such an alloy layer is obtained by forming solder at multiple separate portions, as will be described later. Referring to  FIG. 5B , portions on the upper surface of the pad  18 A where the solder  19  is formed are regions where the thick alloy layer  22  above described is formed, and regions on the upper surface of the pad  18 A where the solder  19  is not formed are regions where the thin alloy layer  23  above described is formed. 
       Second Embodiment  
       [0053]    In this embodiment, with reference to  FIGS. 2 to 7 , a method for manufacturing a hybrid integrated circuit device  10  described above is described. 
         [0054]    First Step: Refer to  FIG. 2   
         [0055]    In this step, a conductive pattern  18  is formed on a surface of a substrate  16 .  FIG. 2A  is a plan view of the substrate  16  in this step, and  FIG. 2B  is a sectional view thereof 
         [0056]    Referring to  FIGS. 2A and 2B , the conductive pattern  18  of a predetermined pattern shape is formed by patterning a conductive foil adhered to the surface of the substrate  16 . Here, pads  18 A to  18 E are formed by the conductive pattern  18 . Each pad  18 A is a pad to which a heat sink is to be attached in a later step, and is formed in a relatively large size. For example, the pad  18 A is formed into a quadrangular shape of 9 mm×9 mm or larger. The pads  18 B and  18 C are pads to which both electrodes of a chip element, such as a chip capacitor, are to be attached with solder in a later step. The pad  18 D is a pad to which a small-signal transistor or an LSI is to be attached, and is formed in a small size compared to the pad  18 A. The pad  18 D is a quadrangle having a size of about, for example, 2 mm×2 mm. There are multiple pads  18 E formed along an upper side (as in the drawing) of the substrate  16  at substantially equal intervals. Leads  11  are attached to the respective pads  18 E in a later step. Moreover, a wiring pattern  18 F is formed, extending to connect the pads to each other. 
         [0057]    The conductive pattern  18  described above is formed with a metal the main material of which is copper. The upper surfaces of the pads  18 A and so on are not coated with a plating film or the like, and the metal material forming the conductive pattern  18  is exposed there. Further, under a general working atmosphere, the surface of the pad  18 A may be coated with a thin oxide film, but this oxide film is removed by a flux contained in solder paste to be applied later. 
         [0058]    Second Step: Refer to  FIG. 3   
         [0059]    In this step, solder paste  21 A is applied to the upper surfaces of the pads  18 A to  18 D. 
         [0060]    Specifically, referring to  FIG. 3A , the solder paste  21 A is applied to the upper surfaces of the pads  18 A to  18 D through screen printing. In this step. the solder paste  21 A is printed and applied to the upper surfaces of the pads  18 B to  18 D to which small-signal elements are to be mounted in a later step and to the upper surface of each large pad  18 A. 
         [0061]    Referring to  FIGS. 3A and 3B , the pads  18 B and  18 C are elements on which a chip element, such as a resistor, is to be mounted, and the solder paste  21 A is applied, as a single portion, to an almost entire area of the upper surface of each of the pads  18 B and  18 C. The pad  18 D is a pad to which an LSI for control is to be attached, and the solder paste  21 A is applied to an almost entire area of its upper surface as a single portion. 
         [0062]    The pad  18 E located at the right end in  FIG. 3A  is a pad to which a lead (an external output terminal) is to be attached in a later step, and solder is therefore not bonded there in this step. 
         [0063]    On the other hand, referring to  FIG. 3C , the solder paste  21 A is applied to the upper surface of the pad  18 A not with an even thickness over the entire surface, but discretely. Specifically, on the upper surface of the pad  18 A, a total of nine portions of the solder paste  21 A are arranged away from each other in a matrix of three rows and three columns. Although nine portions of the solder paste  21 A are arranged on the surface of the pad  18 A here, the number of the portions may be about two, four, or six. 
         [0064]    First, the pad  18 A on which the portions of the solder paste  21 A are discretely arranged has a quadrangular shape in a plan view, L1 thereof being between 4.5 mm and 13.0 mm, inclusive, L2 thereof being about the same. 
         [0065]    Each portion of the solder paste  21 A has a quadrangular shape in a plan view, L3 thereof being between 2.4 mm and 3.4 mm, inclusive, L4 thereof being about the same. The solder paste  21 A may be square or rectangular. When each side of the solder paste  21 A is too long, the amount of the solder paste  21 A increases to increase the surface tension, making it more likely to cause the dewetting described earlier. Conversely, when each side of the solder paste  21 A is too short, the amount of the solder paste  21 A becomes insufficient, so that the strength of connection between the pad  18 A and an element to be attached to the upper surface of the pad  18 A becomes insufficient. 
         [0066]    The portions of the solder paste  21 A are spaced away from each other so that they can maintain the discretized state even after they are melted. Distance L5 by which the portions of the solder paste  21 A are away from each other in a vertical direction in the drawing is for example between 0.9 mm and 1.7 mm, inclusive. Length L6 by which the portions of the solder paste  21 A are away from each other in a horizontal direction in the drawing is the same. If the distance by which the portions of the solder paste  21 A are away from each other is too short, they are integrated when melted, and consequently, the surface tension of the liquid solder increases to cause the dewetting. If the distance by which the portions of the solder paste  21 A are away from each other is too long, the amount of the solder paste  21 A might be insufficient. 
         [0067]    This step is performed by screen printing or supply by use of a syringe. When screen printing is used, a screen having openings at regions to be coated with the solder paste  21 A is placed on the upper surface of the substrate  16 , and solder paste is supplied to the openings of the screen by use of a squeegee. After that, the screen is removed from the substrate  16  to apply the solder paste  21 A to the predetermined positions. 
         [0068]    The solder paste  21 A used in this step is a mixture of a flux and a solder powder. The solder powder mixed for the solder paste  21 A can be either lead-containing solder or lead-free solder. A specific conceivable composition of the solder powder includes, for example, Sn63/Pb37, Sn/Ag3.5, Sn/Ag3.0/Cu0.5, Sn/Ag2.9/Cu0.5, Sn/Ag3.0/Cu0.5, Sn/Bi58, Sn/Cu0.7, Sn/Zn9, Sn/Zn8/Bi3, and the like. These numbers indicate the weight percent of the total solder. Considering the fact that lead puts a heavy environmental load, lead-free solder is preferably used. 
         [0069]    Among the above-described compositions of the lead-free solder, solder having a composition of Sn/Ag3.0/Cu0.5 is optimal in view of its favorable melting point and the like. The weight percent of Ag contained in the solder may be between 2.0% and 4.0%, inclusive, and the weight percent of Cu may be between 0.5% and 0.8%, inclusive. 
         [0070]    Since lead-free solder is often made mainly of Sn (tin), an intermetallic compound layer containing copper and tin and providing poor wettability is generated at the border between the pad  18 A and the solder  19 . 
         [0071]    A rosin-based flux can be used as the flux contained in the solder paste  21 A. In this embodiment, after completion of a reflow step, residual flux is removed by cleaning 
         [0072]    Third Step: Refer to  FIGS. 4 and 5   
         [0073]    Next, elements other than the power transistors (e.g., the small-signal transistor and chip components) are electrically connected, and the solder  19  is formed discretely on the upper surface of each pad  18 A. 
         [0074]    First, referring to  FIG. 4A , elements to be connected in this step are placed on the corresponding solder paste  21 A. Specifically, a chip component  14 B is placed on and temporarily fixed to the solder paste  21 A applied to the pads  18 B and  18 C. Similarly, a transistor  14 C is placed on the upper surface of the solder paste  21 A applied to the upper surface of the pad  18 D. 
         [0075]    Next, referring to  FIG. 4B , the solder paste  21 A described above is melted by being superheated through a reflow step, and the solder  19  is formed consequently. Thereby, electrodes of the chip component  14 B are attached to the pads  18 B and  18 C, respectively, with the solder  19 . A rear surface of the transistor  14 C is also attached to the upper surface of the pad  18 D with the solder  19 . By this reflow step, the portions of the solder paste applied to the upper surface of the pad  18 A are also melted and become the solder  19  (first solder). 
         [0076]    Referring to  FIG. 4C , next, electrodes located on the upper surface of the transistor  14 C are connected, via the thin wires  15 B, to pads formed by the conductive pattern and located around the pad  18 D. The thin wire  15 B is a metallic wire made of gold, copper, or aluminum and having a thickness of 80 μm or smaller. 
         [0077]      FIG. 5  shows the state of the substrate  16  after completion of this step.  FIG. 5A  is a plan view showing the upper surface of the substrate  16  after the completion of this step, and  FIG. 5B  is an enlarged plan view showing the pad  18 A. 
         [0078]    Referring to  FIGS. 5A and 5B , on the upper surface of the pad  18 A, a total of nine portions of solder  19  are arranged away from each other in three rows and three columns. The planar size of each portion of the solder  19  is slightly larger than that described with reference to  FIG. 3C , and has a quadrangular shape which is somewhat swelling. This is because the solder paste has spread outward by being melted. Distances L5 and L6 by which the portions of the solder  19  are away from each other are slightly shorter than those shown in  FIG. 3C . However, even after this step, the portions of the solder  19  maintain to be separated from each other. 
         [0079]    In this embodiment, the solder dewetting is prevented by providing small portions of solder  19  discretely on the upper surface of the pad  18 A. 
         [0080]    To be more specific, as described above, the pad  18 A onto which a heat sink is to be mounted in a later step is large, each side being, for example, 9 mm or more. For this reason, when solder paste is applied to the entire upper surface of the pad  18 A and melted into a large amount of liquid solder, a high surface tension acts on the liquid solder. This surface tension causes the solder  19  to dewet. At this dewetting portion having no solder  19 , the Cu/Sn alloy generated by the pad  18 A and the solder  19  is exposed. At this Cu/Sn alloy exposing surface, extremely poor wettability is exhibited, and consequently solder is not bonded to this region in a later step, so that a void is formed. 
         [0081]    In this embodiment, the small portions of the solder  19  are formed discretely on the upper surface of the pad  18 A to make the surface tension small, and therefore the solder  19  bonded to the upper surface of the pad  18 A is prevented from dewetting. Consequently, the Cu/Sn layer is not exposed on the upper surface of the pad  18 A at a region where the solder  19  is not formed. In other words, in this region, a metal material of the pad  18 A, such as copper, is exposed. This prevents lowering of the solder wettability at this region. 
         [0082]    Fourth Step: Refer to  FIG. 6   
         [0083]    Referring to  FIG. 6 , next, a heat sink  14 D to which the transistor  14 D is attached is attached to the upper surface of each pad  18 A. 
         [0084]    Referring to  FIG. 6A , first, solder paste  31  is additionally supplied to the upper surface of the pad  18 A. Since circuit elements such as the chip component  14 B have already been placed on the upper surface of the substrate  16 , it is difficult to perform screen printing. For this reason, in this step, the solder paste  31  is supplied to the upper surface of the pad  18 A by use of a syringe  30 . In this step, the solder paste  31  is supplied into balls to fill the gaps between the portions of the solder  19  already formed on the upper surface of the pad  18 A. The composition of the solder paste  31  used in this step may be the same as that of the solder paste  21 A shown in  FIG. 3A . 
         [0085]    In this step, the solder paste  31  is in contact with the upper surface of the pad  18 A at the region where no solder  19  is formed. Further, the surfaces of the portions of the solder  19  are covered with the solder paste  31 . 
         [0086]    Referring to  FIG. 6B , next, the heat sink  14 D to which the power transistor  14 A is attached is placed on the upper surface of the solder  19 . Although the transistor  14 A is attached to the upper surface of the heat sink  14 D with solder in advance here, the transistor  14 A may be attached to the heat sink  14 D after the heat sink  14 D is attached to the pad  18 A. 
         [0087]    By performing a reflow step in this state, the solder formed on the upper surface of the pad  18 A and the solder paste  31  melt. As a result of the melting, the solder  19  formed previously and the solder paste  31  mix together, so that the heat sink  14 D is attached to the upper surface of the pad  18 A with solder  19  (second solder) shown in  FIG. 6C  additionally formed. Moreover, the solder  19  attaching the chip component  14 B and the transistor  14 C is also melted in this step and is then solidified. 
         [0088]    Copper, which is the material of the pad  19 A, is exposed at the region of the upper surface of the pad  18 A where the solder  19  is not bonded. In other words, the Cu/Sn alloy layer having poor solder wettability is not exposed in this region. Hence, the solder formed in this embodiment adheres to this region well, and thus void formation is suppressed. 
         [0089]    Referring to  FIG. 6C , after completion of the attachment of the heat sink  14 D with the solder  19 , an electrode located at the upper surface of the transistor  14 A is connected to the conductive pattern  18  via a thick wire  15 A. 
         [0090]    In this step, the above-described alloy layer is generated between the pad  18 A and the solder  19  as a result of melting the solder paste to form the solder  19 . Specifically, alloy layers  22  and  23  having different thicknesses are generated at the border portion between the pad  18 A and the solder  19 . 
         [0091]    The alloy layer  22  is located at spots where the above-described portions of solder  19  are discretely arranged, and is relatively thick since melting of solder is performed twice. In other words, the alloy layer  22  includes the alloy layer generated in the step shown in  FIG. 4  and the alloy layer generated in this step. 
         [0092]    The alloy layer  23 , on the other hand, is generated only in this step (i.e., as a result of only one melting), and its thickness is, for example, about half or less than half of that of the alloy layer  22 . Referring to  FIG. 6A , such an alloy layer having an uneven thickness is provided by forming portions of the solder  19  first, and then later forming the solder paste  31  throughout the surface. 
         [0093]    In this embodiment, as described above, solder is provided discretely first, and then the solder paste  31  is supplied again thereafter to form the solder  19 . Thereby, two effects are obtained: securement of a sufficient amount of solder for mounting the heat sink  14 D and prevention of dewetting of the solder. 
         [0094]    Fifth Step: Refer to  FIG. 7   
         [0095]    In this step, the lead  11   s  are attached, and the sealing resin  12  is formed. 
         [0096]    Referring to  FIG. 7A , first, the solder paste  21 A is applied to the upper portion of each pad  18 E, and the lead  11  is placed thereon. Then, the solder paste  21 A is melted to attach the lead  11 . 
         [0097]    Referring to  FIG. 7B , next, the sealing resin  12  is formed, covering the circuit elements attached to the surface of the substrate  16 . In this embodiment, the sealing resin  12  is formed to cover the side surface and the rear surface of the substrate  16 , as well. 
         [0098]    The sealing resin  12  may be formed, exposing the rear surface of the substrate  16  to the outside. Moreover, the surface of the substrate  16  may be sealed by using a case member. 
         [0099]    With the steps described above, the hybrid integrated circuit device  10  shown in  FIG. 1  is formed.