Abstract:
An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a delay locked loop (DLL) for compensating a clock skew between an external clock signal and an internal clock signal; and, more particularly, to a DLL capable of correcting a duty cycle of the external clock signal.  
       DESCRIPTION OF PRIOR ART  
       [0002]     Generally, in a synchronous semiconductor memory device, data access operations such as a read operation and a write operation are performed in synchronization with rising and falling edges of an external clock signal.  
         [0003]     Since there is a time delay while the external clock signal is inputted to the synchronous semiconductor memory device in order to be used as an internal clock signal of the synchronous semiconductor memory device, a delay locked loop (DLL) is employed for synchronizing the internal clock signal with the external clock signal by compensating a clock skew between the internal clock signal and the external clock signal.  
         [0004]     As an operational speed of the synchronous semiconductor memory device is increased, an apparatus for synchronizing the internal clock signal with the external clock signal and correcting a duty cycle of the external clock signal has been required for enhancing a performance of the synchronous semiconductor memory device. Therefore, various techniques of the DLL have been introduced for compensating the clock skew between the internal clock signal and the external clock signal and for correcting the duty cycle.  
         [0005]      FIG. 1  is a block diagram showing a conventional DLL disclosed in a commonly owned copending application, U.S. Ser. No. 10/331,412, filed on Dec. 30, 2002, entitled “DIGITAL DLL APPARATUS FOR CORRECTING DUTY CYCLE AND METHOD THEREOF”, which is incorporated herein by reference.  
         [0006]     As shown, the conventional DLL includes a buffer  110 , a delay line unit  120 , a duty error controller  130 , a first delay model unit  140 , a first direct phase detector  150 , a second delay model unit  160  and a second direct phase detector  170 .  
         [0007]     The buffer  110  receives an external clock signal ext_clk and generates a first internal clock signal by buffering the external clock signal ext_clk. The first internal clock signal is inputted to the delay line unit  120 .  
         [0008]     The delay line unit  120  receives the first internal clock signal and also receives a first and a second detection signals from the first and the second direct phase detectors  150  and  170 . The delay line unit  120  delays the first internal clock signal based on the first and the second detection signals and outputs a first delayed internal clock signal intclk 1  and a second delayed internal clock signal intclk 2  to the duty error controller  130 .  
         [0009]     In detail, the delay line unit  120  includes a first controller  121 , a first delay line  122 , a second controller  123  and a second delay line  124 .  
         [0010]     The first controller  121  generates a first control signal for controlling a delay amount according to the first detection signal and outputs the first control signal to the first delay line  122 .  
         [0011]     The first delay line  122  receives the first control signal and the first internal clock signal. The first internal clock signal is delayed according to the first control signal through the delay line  122 . That is, the first delay line  122  generates the first delayed internal clock signal intclk 1  by delaying the first internal clock signal according to the first control signal. The first delayed internal clock signal intclk 1  is inputted to the duty error controller  130 .  
         [0012]     The second controller  123  outputs a second control signal to the second delay line  124  for controlling a delay amount according to the second detection signal.  
         [0013]     The second delay line  124  receives the second control signal and the first internal clock signal. The second delay line  124  delays the first internal clock signal based on the second control signal. Then, the delayed first internal clock signal is inverted and outputted as the second delayed internal clock signal intclk 2 . The second delayed internal clock signal intclk 2  is outputted to the duty error controller  130 .  
         [0014]     The duty error controller  130  receives the first and the second delayed internal clock signals intclk 1  and intclk 2 . The duty error controller  130  generates a first duty controlled clock signal int_clk and a second duty controlled clock signal intclk 2 ′ by adjusting falling edges of the first and the second duty controlled clock signals int_clk and intclk 2 ′ to a middle of the falling edges of the first and the second duty controlled clock signals int_clk and intclk 2 ′. Herein, after the first and the second duty controlled clock signals int_clk and intclk 2 ′ are duty corrected by shifting their falling edges as mentioned above, a 50% duty ratio. The first and the second duty controlled clock signals int_clk and intclk 2 ′ are respectively outputted to the first and the second delay model units  140  and  160 .  
         [0015]     The duty error controller  130  includes a first phase detector  131 , a mixer controller  132 , a first phase mixer  133  and a second phase mixer  134 .  
         [0016]     The first and the second delayed internal clock signals intclk 1  and intclk 2  are inverted and inputted to the first phase detector  131 . The first phase detector  131  compares phases of falling edges of the first and the second delayed internal clock signals intclk 1  and the intclk 2  in order to determine which one of their falling edges leads the other for generating a phase detection signal based on the comparison result. The phase detection signal is outputted to the mixer controller  132 .  
         [0017]     The mixer controller  132  receives the phase detection signal to determine a weight k, which contains a phase difference between two falling edges of the first and the second delayed internal clock signals intclk 1  and intclk 2 , according to the phase detection signal. The weight k is outputted to the first and the second phase mixers  133  and  134 . The weight k includes the plural number of weight signals.  
         [0018]     The first phase mixer  133  receives the weight k, the first and the second delayed internal clock signals intclk 1  and intclk 2 . The first phase mixer  133  calculates a difference value by subtracting the weight k from 1. By applying the difference value to the first delayed internal clock signal intclk 1  and applying the weight k to the second delayed internal clock signals intclk 2 , the first phase mixer  133  generates a first duty controlled clock signal int_clk. The first duty controlled clock signal int_clk is outputted to the first delay model unit  140 .  
         [0019]     The second phase mixer  134  receives the weight k and calculates a difference value by subtracting the weight k from 1. The second phase mixer  134  generates a second duty controlled clock signal intclk 2 ′ by applying the weight k to the first delayed internal clock signal intclk 1  and applying the difference value to the second delayed internal clock signal intclk 2 . The second phase mixer  134  outputs the second duty controlled clock signal intclk 2 ′ to the second delay model unit  160 .  
         [0020]     Herein, as above mentioned, the first and the second duty controlled clock signals int_clk and intclk 2 ′ are generated by adjusting their falling edges to a middle of their falling edges; and a direction and a amount of the phase shift is determined by the weight k and the difference value.  
         [0021]     The first delay model unit  140  receives the first duty controlled clock signal int_clk and estimates a delay amount generated while the external clock signal ext_clk is passed through the conventional DLL to be outputted as the first and the second duty controlled clock signals int_clk and intclk 2 ′. The first delay model unit  140  generates a first compensated clock signal iclk 1  based on the estimated delay amount and outputs the first compensated clock signal iclk 1  to the first direct phase detector  150 .  
         [0022]     The first direct phase detector  150  receives the external clock signal ext_clk and the first compensated clock signal iclk 1  to thereby generate the first detection signal in response to a result of comparing the external clock signal ext_clk with the first compensated clock signal iclk 1 . The first detection signal is inputted to the delay line unit  120 .  
         [0023]     The second delay model unit  160  receives the second duty controlled clock signal intclk 2 ′ and estimates a delay amount generated while the second duty controlled clock signal intclk 2 ′ travels from the conventional DLL to a data input/output pin (DQ pin). The second delay model unit  160  generates a second compensated clock signal iclk 2  based on the estimated delay amount and outputs the second compensated clock signal iclk 2  to the second direct phase detector  170 .  
         [0024]     The second direct phase detector  170  receives the external clock signal ext_clk and the second compensated clock signal iclk 2  to generate the second detection signal based on a result of comparing the external clock signal ext_clk and the second compensated clock signal iclk 2 . The generated second detection signal is inputted to the delay line unit  120 .  
         [0025]     However, using the first and the second delay lines  122  and  124 , the conventional DLL shown in  FIG. 1  synchronizes both of the first and the second compensated clock signals iclk 1  and iclk 2  with a rising edge of the external clock signal ext_clk respectively. Therefore, each of the first and the second delay lines should have a delay amount of  1 tCK as shown in  FIG. 2 . As a result, whole delay amount of both the first and the second delay lines should have a delay amount of 2tCK.  
         [0026]     Furthermore, if a conventional DLL has a dual delay line structure, the whole delay amount becomes 4tCK. Herein, in the dual delay line structure, a first and a second delay lines are respectively constituted with a coarse and a fine delay lines. As result, a size of a semiconductor memory device is increased, and a power consumption of the semiconductor memory device is also increased.  
       SUMMARY OF INVENTION  
       [0027]     It is, therefore, an object of the present invention to provide a DLL device capable of reducing a length of a delay line and reducing a delay locking time.  
         [0028]     In accordance with an aspect of the present invention, there is provided a semiconductor device for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.  
         [0029]     In accordance with another aspect of the present invention, there is provided a method of generating a duty corrected clock signal using an external clock signal, including the steps of: generating a rising edge clock signal whose rising edge is synchronized with a rising edge of the external clock signal; generating a falling edge clock signal whose falling edge is synchronized with a rising edge of the external clock signal; selecting one of the rising edge clock signal and the falling edge clock signal based on a feed-backed clock signal; generating a first delay locked clock signal and a second delay locked clock signal by delaying the one of the rising edge clock signal and the falling edge clock signal within one clock cycle of the external clock signal based on a first phase detecting signal and a second phase detecting signal; and generating a first output clock signal and a second output clock signal by delaying the first delay locked clock signal and the second delay locked clock signal; and generating the duty corrected clock signal by correcting duty cycles of the first output clock signal and the second output clock signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0030]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0031]      FIG. 1  is a block diagram showing a conventional DLL;  
         [0032]      FIG. 2  is a timing diagram showing an operation of the conventional DLL shown in  FIG. 1 ;  
         [0033]      FIG. 3  is a block diagram showing a DLL in accordance with the present invention;  
         [0034]      FIG. 4  is a timing diagram showing an operation of the DLL shown in  FIG. 3 ;  
         [0035]      FIG. 5  is a schematic circuit diagram showing a delay line unit shown in  FIG. 3 ;  
         [0036]      FIG. 6  is a schematic circuit diagram showing a clock signal selector shown in  FIG. 3 ; and  
         [0037]      FIG. 7  is a timing diagram showing an operation of a first and a second phase detectors shown in  FIG. 6 .  
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0038]     Hereinafter, a delay locked loop in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0039]      FIG. 3  is a block diagram showing a delay locked loop (DLL) in accordance with the present invention.  
         [0040]     As shown, the DLL includes a clock multiplexing unit  310 , a first direct phase detector  350 , a second direct phase detector  370 , a first delay model unit  340 , a second delay model unit  360 , a delay line unit  320 , a first clock phase control unit  380 , a second clock phase control unit  390  and a duty cycle correction unit  330 .  
         [0041]     The clock multiplexing unit  310  receives an external clock signal CLK and an inverted signal of the external clock signal CLK, i.e., an external clock bar signal /CLK. The clock multiplexing unit  310  selects one of the external clock signal CLK and the external clock bar signal /CLK in order to output the selected clock signal to the delay line unit  320  so that the selected clock signal can be delay locked within tCK/ 2  in the delay line unit  320 , wherein the tCK is a clock cycle of the external clock signal CLK.  
         [0042]     The clock multiplexing unit  310  includes a first input buffer  311 , a second input buffer  312 , a clock signal selector  313  and a multiplexer  314 .  
         [0043]     The first input buffer  311  receives the external clock signal CLK and the external clock bar signal /CLK respectively through a non-inverting terminal (+) and an inverting terminal (−) of the first input buffer  311  in order to output the external clock signal CLK as a rising edge clock signal rclk by buffering the external clock signal CLK. The second input buffer  312  receives the external clock bar signal /CLK respectively through an inverting terminal (−) and a non-inverting terminal (+) of the second input buffer  312  in order to output the external clock bar signal /CLK as a falling edge clock signal fclk by buffering the external clock bar signal /CLK. Herein, the rising edge clock signal rclk is synchronized with the external clock signal CLK, and the falling edge clock signal fclk is synchronized with the external clock bar signal /CLK.  
         [0044]     The clock signal selector  313  compares a phase of the external clock signal CLK with a phase of a feed-backed clock signal fb_clk outputted from the first delay model unit  340  in order to generate a clock selection signal clk_sel.  
         [0045]     The multiplexer  314  selects one of the rising edge clock signal rclk and the falling edge clock signal fclk based on the clock selection signal clk_sel in order to output the selected signal to the delay line unit  320 .  
         [0046]     The delay line unit  320  includes a first delay line  322 , a first delay line controller  321 , a second delay line  324  and a second delay line controller  323 .  
         [0047]     The rising edge clock signal rclk or the falling edge clock signal fclk selected by the multiplexer is delay locked within tCK/ 2  in the first delay line  322 . Thereafter, the first delay line  320  outputs a first delay locked clock signal pre_clk to the first clock phase control unit  380  and the second delay line  324 .  
         [0048]     Meanwhile, the first direct phase detector  350  generates a first phase detecting signal pd 1 . The first phase detecting signal pd 1  is inputted to both of the first delay line controller  321  and the second delay line controller  323 . The first and the second delay line controllers  321  and  323  respectively control delay amounts of the first and the second delay lines  322  and  324  based on the first phase detecting signal pd 1 . Since the first phase detecting signal pd 1  is inputted both of the first and the second delay line controllers  321  and  323 , the first delay locked clock signal pre_clk is delayed in the second delay line  324  for the same delay time as that of the first delay line  322 . The second delay line  324  outputs a second delay locked clock signal by delaying the first delay locked clock signal pre_clk.  
         [0049]      FIG. 4  is a timing diagram showing an operation of the digital DLL.  
         [0050]     As shown, the feed-backed clock signal fb_clk should be delayed for a delay amount of α to be synchronized with the external clock signal CLK. Therefore, the first direct phase detector  350  outputs the first phase detecting signal pd 1  to the first and the second delay line controllers  321  and  323  for controlling the first and the second delay lines  322  and  324  to have the delay amount of α. Subsequently, the first delay line  322  delays the feed-backed clock signal fb_clk for the delay amount of α, and, then, outputs the delayed signal as the first delay locked clock signal pre_clk. As a result, a rising edge of the first delay locked clock signal pre_clk is synchronized with a rising edge of the external clock signal CLK.  
         [0051]     Meanwhile, the first delay locked clock signal pre_clk is delayed for the delay amount of a by the second delay line  324 . Herein, since the first and the second delay lines  322  and  324  are connected in series, the second delay line  324  receives the first delay locked clock signal pre_clk from the first delay line  322 . Subsequently, the second delay locked clock signal post_clk outputted from the second delay line  324  becomes a delayed version of the feed-backed clock bar signal /fb_clk inputted to the second direct phase detector  370  having a delay amount of 2α.  
         [0052]     At this time, since the first delay locked clock signal pre_clk is synchronized with the external clock signal CLK, a delay amount of the first delay line  322  is no longer changed. The second delay locked clock signal post_clk is still required to be delayed for a delay amount of β to be synchronized with the external clock signal CLK. Therefore, the second delay locked clock signal post_clk is delayed for the delay amount of β under control of the second direct phase detector  370  and the second delay line controller  323 .  
         [0053]     Above-mentioned delay locking operation of the first and the second delay lines  322  and  324  is referred as a coarse delay operation.  
         [0054]     Meanwhile, the first clock phase control unit  380  includes a first fine delay line  381 , a second fine delay line  382  and a first phase mixer  383 . Likewise, the second clock phase control unit  390  includes a third fine delay line  391 , a fourth fine delay line  392  and a second phase mixer  393 .  
         [0055]     The first and the second fine delay lines  381  and  382  perform a fine delay operation to the first delay locked clock signal pre_clk respectively. Likewise, the third and the fourth fine delay lines  391  and  392  perform the fine delay operation to the second delay locked clock signal post_clk respectively. The fine delay operation is performed in order to finely delay the first and the second delay locked clock signal pre_clk and post_clk for phase locking. The fine delay operation is performed independently of the coarse delay operation.  
         [0056]     Since an operation of the first clock phase control unit  380  is same to that of the second clock phase control unit  390 , only the operation of the first clock phase control unit  380  is described below.  
         [0057]     The first delay locked clock signal pre_clk is inputted to the first and the second fine delay lines  381  and  382 . Herein, the number of unit delay cells included in the first fine delay line  381  can be smaller that that of the second fine delay line  382  by one. That is, a weight value K is determined based on the first phase detecting signal pd 1 ; and, the number of unit delay cells, through which the first delay locked clock signal pre_clk is passed in the first fine delay line  381 , is determined based on a control signal outputted from the first phase mixer  383 . Herein, the number of unit delay cells of the first fine delay line  381  passed by the first delay locked clock signal pre_clk is smaller than that of the second fine delay line  382  passed by the first delay locked clock signal pre_clk by one.  
         [0058]     That is, if the number of unit delay cells passed by the first delay locked clock signal pre_clk in the first fine delay line is 1, 3 or 5, the number of unit delay cells passed by the first delay locked clock signal pre_clk in the second fine delay line is 2, 4 or 6 respectively. For example, if the first delay locked clock signal pre_clk is passed through three unit delay cells in the first fine delay line  381 , the first delay locked clock signal pre_clk is passed through four unit delay cells in the second fine delay line  382 .  
         [0059]     The first and the second fine delay lines  381  and  382  respectively output a first input signal IN 1  and a second input signal IN 2  to the first phase mixer  383 .  
         [0060]     If the weigh value K is set to 0 based on the first phase detecting signal pd 1 , the first fine delay line  381  outputs the first delay locked clock signal pre_clk without delaying the first delay locked clock signal pre_clk.  
         [0061]     However, if it is detected that a phase of the feed-backed clock signal fb_clk leads a phase of the external clock signal CLK by the first direct phase detector  351 , the first phase mixer  383  increases the weight value K. The more the weight value K is approached to 1, the more an outputted clock signal of the phase mixer  383  is synchronized with the second input signal IN 2 .  
         [0062]     Thereafter, if the weight value becomes 1, the first phase mixer  383  outputs the second input signal IN 2  as the outputted clock signal of the phase mixer  383 . At this time, if a phase of the feed-backed clock signal fb_clk is still leads a phase of the external clock signal CLK, the first phase mixer  383  shifts a delay amount of the first fine delay line  381  in a left direction. That is, the number of unit delay cells passed by the first delay locked clock signal pre_clk is increased by two, e.g., 1 to 3 or 3 to 5. At this time, since the weigh value K is 1, the outputted clock signal of the first phase mixer  383  is not influenced by delay amount variance of the first fine delay line  381 .  
         [0063]     If it is required that the feed-backed clock signal fb_clk is more delayed after left-shifting the delay amount of the first fine delay line  381 , the weight value K is decreased. If the weight value K is decreased, a phase of the outputted clock signal of the first phase mixer  383  is approached to a phase of the first input signal IN 1 .  
         [0064]     Meanwhile, for decreasing a delay amount of the first and the second fine delay lines  383  and  393 , the above-mentioned operation can be performed in an opposite way.  
         [0065]     In addition, the first phase mixer  383  generates a plurality of control signals, i.e., a shift-right signal and a shift-left signal for controlling a delay amount of the first and the second fine delay lines  381  and  382 . The first phase mixer  383  can be designed by various design techniques, e.g., an up-down counter or a decoder, which is well known to those skilled in the art.  
         [0066]     Since a delay locking operation is almost completed by the coarse delay operation, the fine delay operation is performed in order to finely adjust a small delay variance generated due to external noises such as a power supply voltage variance. Therefore, a physical delay line length for adjusting the small delay variance is an enough physical length of the first to the fourth fine delay lines  381 ,  382  and  392 .  
         [0067]      FIG. 5  is a schematic circuit diagram showing the delay line unit  320  shown in  FIG. 3 .  
         [0068]     As shown, the first delay line controller  321  generates a first to a third shift-left signals SL 1  to SL 3  based on the first phase detecting signal pd 1 . The first delay line  322  delays input signals of the first line  322  according to the first to the third shift-left signals SL 1  to SL 3 . The second delay line  324  has the same structure with the first delay line  322 .  
         [0069]      FIG. 6  is a schematic circuit diagram showing the clock signal selector  313  shown in  FIG. 3 .  
         [0070]     As shown, the clock signal selector  313  includes a feed-backed clock delay unit  621 , a first phase detector  623 , a second phase detector  625 , a p-channel metal oxide semiconductor (PMOS) transistor  627  and a first to a third n-channel metal oxide semiconductor (NMOS) transistors  629  to  633 .  
         [0071]     The feed-backed clock delay unit  621  delays the feed-backed clock signal for a predetermined delay time in order to generate a delayed feed-backed clock signal fb_clkd. The first phase detector  623  compares phases of the external clock signal CLK and the feed-backed clock signal fb_clk. The second phase detector  625  compares phases of the external clock signal CLK and the delayed feed-backed clock signal fb_clkd.  
         [0072]     The feed-backed clock delay unit  621  includes K numbers of unit delay cells. The K numbers of unit delay cells are required numbers of unit delay cells in order to delaying the feed-backed clock signal avoiding a dead zone.  
         [0073]      FIG. 7  is a timing diagram showing an operation of the first and the second phase detectors  623  and  625 .  
         [0074]     As shown, if a phase of a signal inputted to a first terminal ‘a’ leads a phase of a signal inputted to a second terminal ‘b’, an output signal of the first phase detector  623  or the second phase detector  625  is in a logic high level. On the other hand, if a phase of a signal inputted to a first terminal ‘a’ lags behind a phase of a signal inputted to a second terminal ‘b’, an output signal of the first phase detector  623  or the second phase detector  625  is in a logic low level.  
         [0075]     Therefore, if a phase of the external clock signal CLK leads phases of the feed-backed clock signal fb_clk and the delayed feed-backed clock signal fb_clkd, output signals of the first and the second phase detectors  623  and  625  are in a logic high level. As a result, the first and the second NMOS transistors  629  and  631  are turned on; and, thus, the clock selection signal clk_sel becomes in a logic high level. Therefore, the multiplexer  314  shown in  FIG. 3  selects the falling edge clock signal fclk in response to the clock selection signal which is in a logic high level. Except in the above-mentioned case, the multiplexer selects the rising edge clock signal rclk.  
         [0076]     As described above, the DLL in accordance with the present invention can reduce a physical length of a delay line by using the clock multiplexing unit  310 . Therefore, the DLL can reduce a required time for delay locking a clock signal. In addition, a power consumption of the DLL can be reduced since a physical length of a delay line is reduced.  
         [0077]     The present application contains subject matter related to Korean patent application No. 2004-49848, filed in the Korean Patent Office on Jun. 30, 2004, the entire contents of which being incorporated herein by reference.  
         [0078]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.