Abstract:
Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure is generally related to generating and amplifying a differential signal. 
       BACKGROUND 
       [0002]    Single-ended data sensing is commonly used in memory arrays in which a memory cell (e.g., a transistor) is coupled to a capacitor and a bit line. The memory cell, when being invoked for reading, is required to discharge the bit line capacitance in a certain time period (e.g., an evaluation period before reading). For example, in some approaches, the memory cell is required to discharge (e.g., to pull the voltage level of) the bit line from the operation voltage Vdd to below the trip-point voltage of an inverter in the next reading stage. The evaluation period is the time it takes for the memory to discharge. The trip-point voltage is the voltage at which the inverter changes its state. Accurately reading the data, in effect, depends on the strength (e.g., the current driving/pulling capabilities) of the memory cell. In many applications (e.g., in high density memory arrays with multi-million memory cells/bits), the memory cell is inherently very small with low current driving capabilities (e.g., in the range of 20-30 μA). In some approaches, when the evaluation period is short and/or the current of the memory cell is weak, e.g., due to a weak cell, in a leakage process, or when the operation voltage is low (e.g., at the minimum required operation voltage (Vccmin) applications), the memory cell cannot completely discharge the bit line to the required voltage within the evaluation period, which results in incorrect read data. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims. 
           [0004]      FIG. 1  is a circuit in accordance with some embodiments. 
           [0005]      FIG. 2  is a flowchart illustrating an operation of the circuit in  FIG. 1 , in accordance with some embodiments. 
       
    
    
       [0006]    Like reference symbols in the various drawings indicate like elements. 
       DETAILED DESCRIPTION 
       [0007]    Embodiments, or examples, illustrated in the drawings are now being disclosed using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. Reference numbers may be repeated throughout the embodiments, but they do not require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number. 
         [0008]    Some embodiments can have one or a combination of the following features and/or advantages. Some embodiments related to memory arrays sense data faster and independent of the cell current, especially when the current is limited, e.g., in a leakage process, due to a weak bit or in a low voltage (e.g., Vccmin) operation. Some embodiments can be used in short evaluation periods in which a weak device generates a low current level to discharge the loading capacitance and/or in conjunction with an adjustable delay circuit to synchronize with a word line time window. Some embodiments can use a short recovery time. Some embodiments can be used in low power (e.g., ultra low power (ULP)) environments and/or with high density arrays (e.g., arrays having long bit lines coupling a plurality of small memory cells). Some embodiments can be used when the memory cells (bits) are weak (e.g., the memory cells pull little current). Some embodiments can be used with low operation voltage (e.g., low Vccmin) in ROMS, one-port/two-port register files (1PRF, 2PRF), etc. 
       Exemplary Circuit 
       [0009]      FIG. 1  is a diagram of a circuit  100  in accordance with some embodiments. Memory cell MC stores data. Word line WL turns on/off memory cell MC. When memory cell MC is turned off, i.e., circuit  105  is not affected by an external circuit/current, the voltage levels of nodes In 11  and In 12  are substantially equal (e.g., equal). In some embodiments, when memory cell MC is turned on, e.g., for reading data, a “read” transistor (e.g., a pull down transistors) in memory cell MC is turned on and sinks some current, a portion of current Ip 1  in circuit  105  flows into memory cell MC as current Imc. As a result, circuit  105  is imbalanced, and a differential signal (e.g., signal In 112 , not labeled) is generated between nodes In 11  and In 12 . Memory cell MC is shown coupled to input In 1051  of circuit  105  for illustration, memory cell MC can be coupled to input In 1052 . In some embodiments, when an input (e.g., input In 1052 ) not connected to memory cell MC, that input is connected to a reference voltage, a reference circuit, a de-activated memory cell, etc. 
         [0010]    Recursive amplification circuit  105  is used with memory cell MC to read the data stored in memory cell MC independent of the current strength of memory cell MC. When memory cell MC is accessed, e.g., for reading, a part of current Ip 1 , i.e., current Imc, flows into memory cell MC resulting in a differential signal In 112  between nodes In 11  and In 12 . As soon as differential signal In 112  is created (i.e., there is a voltage difference between nodes In 11  and In 12 ), circuit  105  “recursively” amplifies the voltage difference based on which latch LCH generates data on line Qout corresponding to the data stored in memory cell MC to be read. 
         [0011]    Latch LCH, based on the voltage difference between nodes In 11  and In 12 , generates a signal to be read on line Qout. In some embodiments, the larger the voltage difference between nodes In 11  and In 12 , the easier it is for latch LCH to sense (e.g. read) the data. In some embodiments, when the voltage level of node In 11  is higher than that of node In 12 , latch LCH generates a logical “1” (e.g., a High logic level) on line Qout, and when the voltage level of node In 11  is lower than that of node In 12 , latch LCH generates a logical “0” (e.g., a Low logic level) on line Qout. Embodiments of the disclosure, however, are not limited to any particular set of data generated by latch LCH. For example, the embodiments are equally usable if latch LCH generates a Low when the voltage level of node In 11  is higher than that of node In 12 , and generates a High when the voltage level of node In 11  is lower than that of node In 12 , etc. Further, the embodiments are not limited to any particular method or mechanism based on which latch circuit LCH generates signal Qout based on the voltage difference between nodes In 11  and In 12 . Various circuits generating signal Qout are within the scope of the embodiments. 
         [0012]    Transistors P 1 , P 2 , P 3 , and P 4  serve as power switches providing power (e.g., the respective currents Ip 1 , Ip 2 , Ip 3 , and Ip 4 ) for circuit  105 . Signal Power controls (e.g., turn on/off) transistors P 1 , P 2 , P 3 , and P 4 . In some embodiments, signal Power is synchronized with a word line (e.g., signal) WL (e.g., through an adjustable delay circuit) so that when signal WL is activated (e.g., driven High) that turns on memory cell MC signal Power is also activated (e.g., driven Low) to turn on transistors P 1 , P 2 , P 3 , and P 4 . When signal Power is driven High, transistors P 1 , P 2 , P 3 , and P 4  are off, but when signal Power is driven Low, transistors P 1 , P 2 , P 3 , and P 4  are on, and currents Ip 1 , Ip 2 , Ip 3 , and Ip 4  flow. Transistors P 5  and P 6  are called voltage (or power) kick transistors because, in some embodiments, at some point during differential signal amplification one transistor (e.g., transistor P 5 ) is off while the other transistor (e.g., transistor P 6 ) is on that maximizes the amplification of differential signal In 112 . Transistors P 1 , P 2 , P 3 , P 4  are shown for illustration, other circuitries providing powers/currents, including, for example, current sources, are within the scope of the disclosed embodiments. Additionally, a current source replacing operation voltage VDD for each transistor P 1 , P 2 , P 3 , and P 4  and providing the corresponding current is within the scope of the disclosed embodiments. 
         [0013]    Circuit  105  is symmetrical about the axis  107 . That is, a transistor on the left of axis  107  is configured to match (e.g., to have the same size, the same current driving capability, etc., as those of) a transistor on the right of axis  107 . For example, transistor P 1  is configured to match transistor P 4 , transistor P 2  is configured to match transistor P 3 , transistor P 5  is configured to match transistor P 6 , transistor N 1  is configured to match transistor N 2 , and transistor M 1  is configured to match transistor M 2 , etc. Because of the symmetrical structure, when circuit  105  is not affected by an external circuit (e.g. memory cell MC), current, and/or voltage, a current generated by a transistor on the left of axis  107  is substantially the same as a current generated by a transistor on the right of axis  107 . For simplicity, the term “the same” used in this document indicates “substantially the same.” As a result, Ip 1 ≅Ip 4 , Ip 2 ≅Ip 3 , Ip 5 ≅Ip 6 , In 1 ≅In 2 , and Im 1 ≅Im 2 . In  FIG. 1 , currents Ip 1 , Ip 2 , Ip 3 , Ip 4 , Ip 5 , and Ip 6  flow from the sources to the drains of respective transistors P 1 , P 2 , P 3 , P 4 , P 5 , and P 6 . Similarly, currents In 1 , In 2 , Im 1 , and Im 2  flow from the drains to the sources of respective transistors N 1 , N 2 , M 1 , and M 2 . 
         [0014]    Node P 156  couples the drains of transistors P 1  and P 5 , the gate of transistor P 6 , the drain and the gate of transistor M 1 , and the gate of transistor N 2 . Similarly, node P 465  couples the drains of transistors P 4  and P 6 , the gate of transistor P 5 , the drain and the gate of transistor M 2 , and the gate of transistor N 1 . 
       Recursive Amplification 
       [0015]    For illustration, signal WL is activated (e.g., driven High), which turns on memory cell MC. At about the same time, signal Power is also activated (e.g., driven Low) through, e.g., an adjustable delay circuit (not shown) synchronized with signal WL, which turns on transistors P 1 , P 2 , P 3 , and P 4 . 
         [0016]    On the left side of axis  107 , because transistor P 1  is on, current Ip 1  flows, and, because memory cell MC is on, memory cell MC (e.g., via a pull down device) sinks current Imc. As a result, current Ip 1  is divided into (or is the sum of) currents Imc, Im 1 , and In 1  (i.e., Ip 1 =Imc+Im 1 +In 1 ). On the right side of axis  107 , because transistor P 4  is on, current Ip 4  flows, which is divided into (or is the sum of) currents Im 2  and In 2  (i.e., Ip 4 =Im 2 +In 2 ). Current Im 1 +In 1  and current Im 2 +In 2  are the net current flowing into transistors M 1  and N 1 , and M 2  and N 2 , respectively. Because Ip 1 =Ip 4 , Im 1 +In 1 =Ip 1 −Imc, and Im 2 +In 2 =Ip 4 , Im 1 +In 1  is less than Im 2 +In 2 , which causes the voltage at node P 156  or at node In 11  is less than the voltage at node P 465  or at node In 12 . Stated another way, a differential voltage In 112  between nodes In 11  and In 12  is created wherein the voltage at node In 11  is less than the voltage at node In 12 . 
         [0017]    Because the voltage at node P 156  is the same as the voltage at the gate of transistor N 2  (e.g., voltage Vgm 2 , not labeled), which is less than the voltage at node P 456 , which is the same as the voltage at the gate of transistor N 1  (e.g., voltage Vgm 1 , not labeled), transistor N 2  is weaker than transistor N 1 . Consequently, current In 2  is lesser than current In 1 . Because current In 2  is lesser than current In 1 , current Im 2  is greater than current Im 1 . As a result, transistor M 2  is stronger than transistor M 1 , enabling transistor N 1  to be stronger. Because transistor N 1  competes for current provided to node P 156  with transistor M 1 , as transistor N 1  becomes stronger, transistor M 1  becomes weaker. Further, as transistor N 1  becomes stronger, transistor N 1  further pulls down the voltage level at node P 156  or node In 11 , and further increases the voltage difference between nodes In 11  and In 12 . 
         [0018]    Because transistor N 1  is stronger than transistor N 2 , transistor N 1  pulls the voltage at its drain (e.g., node In 11 ) to it source (e.g., ground) stronger than transistor N 2  pulls the voltage at its drain (e.g., node In 12 ) to its source (e.g., ground). Consequently, the voltage level at node In 12  is further higher than that at node In 11 . Stated another way, the differential signal In 112  or the voltage difference between nodes In 11  and In 12  is further amplified (e.g., recursively amplified). 
       The Voltage Kick Mechanisms 
       [0019]    Transistors P 5  and P 6  are called “voltage” kick transistors because, at an appropriate time, one transistor (e.g., transistor P 5 ) is off while the other transistor (e.g., transistor P 6 ) is on, maximizing the amplification of signal In 112  (e.g., maximizing the voltage difference between nodes In 11  and In 12 ). In some embodiments, both transistors P 5  and P 6  are initially on when signal Power is driven Low. During this time, transistors P 5  and P 6  provide the respective currents Ip 5  and Ip 6  to the corresponding nodes P 156  and P 456 . 
         [0020]    Further, in the above example where memory cell MC is coupled to input In 1051  of circuit  105 , because the voltage level at node In 11  (or node P 156 ) is driven further and further (recursively) lower than that at node In 12  (or at node P 465 ), the voltage level at node P 156  continues to keep transistor P 6  on because transistor P 6 , a PMOS transistor, is turned on by a Low voltage applied at its gate. In contrast, the voltage at node P 465  keeps rising and rising, and eventually reaches a point that it is high enough to turn off transistor P 5  because transistor P 5 , a PMOS transistor, is turned off by a High applied at its gate. As the voltage at the gate of transistor P 6  (e.g., node P 156 ) keeps decreasing (e.g., lower and lower), current Ip 6  keeps increasing and increasing. On the other hand, as the voltage at the gate of transistor P 5  (e.g., at node P 465 ) keeps increasing and increasing (e.g., higher and higher), current Ip 5  keep decreasing and decreasing, resulting in current Im 2 +In 2  being further greater than current Im 1 +In 1 . As a result, the voltage difference between nodes In 11  and In 12  is further amplified consistent with the above illustration until transistor P 5  is turned off. Transistors P 5  and P 6  are shown for illustration, other mechanisms increasing the voltage difference between current Im 2 +In 2  and Im 1 +In 2  are within the scope of the disclosure. 
         [0021]    In some embodiments, a predetermined differential signal In 112  is calculated based on currents Imc, Ip 1 , Ip 2 , Ip 3 , Ip 4 , Ip 5 , Ip 6 , In 1 , In 2 , Im 1 , and Im 2 , each of which is calculated based on sizing the corresponding transistor. That is, the predetermined differential signal In 112  (e.g., the voltage difference between nodes In 11  and In 12 ) is calculated by adjusting the size of one or a combination of the transistors P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , N 1 , N 2 , M 1 , and M 2 . Because the voltage level of signal Power at the gate of transistors P 1 , P 2 , P 3 , and P 4  also affect the amount/flow of currents Ip 1 , Ip 2 , Ip 3 , and Ip 4 , signal Power, in some embodiments, is also used in calculating and generating the differential signal In 112  to correspond to the predetermined signal In 112 . 
         [0022]    Circuit  105  used with memory cell MC as illustrated in  FIG. 1  is for illustration, the disclosed embodiments are not limited to such a usage. Circuit  105  can be used in various other applications, including, for example, where a differential signal is desired, in a circuit that sinks or sources currents based on which a voltage level (e.g., a digital voltage level) is transformed, etc. 
         [0023]    Some embodiments are advantageous over other approaches because circuit  105  in those embodiments does not depend on the current strength of memory cell MC. As soon as there is some circuit, current and/or voltage that causes an imbalance in circuit  105  (e.g., the memory cell MC is pulling current Imc, a differential signal pulling current from or injecting current into nodes In 1051  and  1052 , etc.), circuit  105  automatically generates and recursively amplifies differential signal In 112 . Further, circuit  105  does not have to wait for the whole evaluation for the required discharge to complete like other approaches. For example, memory cell MC can be turned off as soon as the differential signal In 112  in circuit  105  is generated. Circuit  105  continues to amplify the differential signal In 112  for latch LCH to read the data as appropriate. As a result, circuit  105  can be used in high density applications where the memory cell MC is tiny with ultra low current driving/pulling capabilities. Because circuit  105  does not depend on the discharge time like other approaches, circuit  105  also does not depend on the corresponding charge time. 
       Exemplary Method 
       [0024]      FIG. 2  is a flowchart illustrating a method related to circuit  100 , in accordance with some embodiments. 
         [0025]    In step  205 , the differential signal In 112  (the voltage difference between nodes In 11  and In 12 ) is determined. In some embodiments, the required voltage difference of this differential signal depends on the sensing capability of latch circuit LCH. For illustration, the voltage level at node In 11  is lower than the voltage level at node In 12 . 
         [0026]    In step  210 , circuit  105  is formed having a first current branch having current Im 1 , a second current branch having current In 1 , a third current branch having current Im 2 , and a fourth current branch having current In 2 . 
         [0027]    In step  215 , circuit  100  is formed where memory cell MC is coupled to input In 1011  of circuit  105 . 
         [0028]    In step  220 , a word line WL is activated to turn on memory cell MC, which sinks current Imc. Because memory cell MC sinks current Imc, the total current Im 1 +In 1  is lesser than the total current Im 2 +Im 1 . 
         [0029]    In step  225 , currents are provided to the current branches by synchronizing signal Power with word line WL to turn on transistors P 1 , P 2 , P 3 , and P 4 . 
         [0030]    In step  230 , because of the current difference in current Im 1 +In 1  and Im 2 +In 2 , circuit  105  generates and amplifies differential signal In 112  in which current Im 1  is lesser than current Im 2  and current In 1  is greater than current In 2 . 
         [0031]    In step  235 , latch LCH, based on the differential signal In 112 , generates the data at node Qout that reflects the data stored in memory cell MC. 
         [0032]    In the above example, because memory cell MC is coupled to input In 1051  the voltage level of node In 11  is lower than that of node In 12 . If, however, memory cell MC is coupled to node In 1052 , the voltage level of node In 11  is higher than that of node In 12 , or latch LCH would generate output Qout with an inverse logic. Further, memory cell MC is used to sink current Imc causing the imbalance (e.g., current difference) in circuit  105  for differential signal In 112  to be generated. Other circuitry/signal (e.g., a differential signal at nodes In 1051  and In 1052 ) causing a current imbalance in circuit  105  can equally be used to generate differential signal In 112  based on which circuit  105  further amplifies differential signal In 112 . 
         [0033]    A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosed embodiments. For example, the various transistors being shown as a particular dopant type (e.g., NMOS (N-type Metal-Oxide Silicon) and PMOS (P-type Metal Oxide Silicon)) are for illustration, embodiments of the disclosure are not limited to a particular type, but the dopant type selected for a particular transistor is a design choice and is within the scope of embodiments. The logic level (e.g., Low or High) of the various signals used in the above description is also for illustration purposes, embodiments are not limited to a particular level when a signal is activated and/or deactivated, but, rather, selecting such a level is a matter of design choice. 
         [0034]    The above method embodiment shows exemplary steps, but they are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments. 
         [0035]    Each claim of this document constitutes a separate embodiment, and embodiments that combine different claims and/or different embodiments are within scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure.