Abstract:
The disclosure describes a charge device capable of charging electricity storage cells while eliminating a voltage variation among the electricity storage cells without a need for at least a circuit section playing a role in voltage equalization among the electricity storage cells to be designed to have a large current capacity, and describes a charge-discharge device constructed by additionally equipping a discharging function with the charge device. Provided are a charge device and a charge-discharge device each of which comprises a convertor, an input circuit, and a multi-stage voltage doubler rectifier circuit. An element in the convertor configured to be applied with a rectangular waveform voltage is connected to the multi-stage voltage doubler rectifier circuit via the input circuit to thereby realize a voltage equalization function, and an output section of the convertor is connected to the multi-stage voltage doubler rectifier circuit to thereby realize a charging-discharging function.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a charge-discharge device for charging and discharging an electricity storage module composed of a series-connection of a plurality of electricity storage cells (secondary batteries, electric double layer capacitors, etc.), while equalizing voltages of the electricity storage cells. 
       BACKGROUND ART 
       [0002]    In order to obtain a desired voltage depending on the intended use, an electricity storage cell such as a secondary battery or an electric double layer capacitor is plurally provided, wherein the plurality of electricity storage cells are connected in series to form an storage module, and used. In the electricity storage module, along with repetitive charging and discharging, a variation in cell voltage occurs among the respective cells, due to variation in capacity, internal resistance, environmental temperature, self-discharge and the like. The variation occurring in the electricity storage module causes problems such as accelerated progression of degradation, and reduction in utilizable energy. Thus, in the case where a plurality of electricity storage cells are connected in series and used, there is a need for an equalization circuit designed to eliminate a voltage variation among the respective cells. 
         [0003]    Heretofore, various types of equalization circuits have been employed. However, many of the types require a large number of switches, causing a problem of an increase in complexity of a circuit configuration. As measures against this problem, there have been proposed two types of equalization circuits capable of operating, respectively, using one transistor and two transistors (i.e., one switch and two switches) (see FIG. 1 and FIG. 2 corresponding, respectively, to the following Patent Document 1, and Japanese Patent Application No. 2012-46569 which is an earlier patent application filed by the same applicant as that of the present invention). These schemes make it possible to significantly reduce the number of required switches, and therefore have an advantage of being able to significantly simplify a circuit configuration. However, the schemes are directed to an “equalization circuit” specialized in voltage equalization, so that it is necessary to separately equip a charge-discharge device for charging and discharging the electricity storage cells. That is, in terms of an electricity storage system, it is necessary to equip a “charge-discharge device” in addition to an “equalization circuit”. Thus, there still remains a need for simplification of the electricity storage system. 
         [0004]    In this connection, there has been proposed an equalization function-equipped charger capable of operating using one transistor (i.e., one switch) (see FIG. 3 corresponding to the following Patent Document 2). This scheme is based on an integration of a charger and an equalization circuit, and is therefore capable of charging series-connected electricity storage cells while eliminating a voltage variation among the electricity storage cells. That is, there is no need to equip a charger and an equalization circuit in a separate manner, so that it becomes possible to promote simplification in terms of an electricity storage system. However, this scheme is configured to supply charging electric power to the series-connected electricity storage cells, individually. Thus, each of all components composing a circuit needs to be designed to have a relatively large current capacity, so that the circuit tends to be increased in size and cost. Moreover, it does not have any function of a discharge device. Thus, a discharge device is required separately. 
       CITATION LIST 
     Patent Document 
       [0000]    
       
         Patent Document 1: JP 2012-186881A 
         Patent Document 2: JP 2011-199949A 
         Patent Document 3: JP 2011-45162A 
       
     
       Non-Patent Document 
       [0000]    
       
         Non-Patent Document 1: M. Uno and A. Kukita, “Cell Voltage Equalizer Using Series Resonant Inverter and Voltage Multiplier for Series-Connected Supercapacitors”, IEEE Energy Conversion Congress and Exposition, 2012, pp. 672-677. 
       
     
       SUMMARY OF INVENTION 
     Problem to be Solved by the Invention 
       [0009]    The present invention has been made under the above circumstance. The problem to be solved by the present invention are: providing of a charge device capable of charging while eliminating a voltage variation among the electricity storage cells without a need for at least a circuit section serving a function of voltage equalization among the electricity storage cells to be designed to have a large current capacity; and providing of a charge-discharge device constructed by additionally equipping a discharging function with such the charger. 
       Means for Solving the Problem 
       [0010]    In order to solve the problem, the present invention provides a charge device which comprises: a multi-stage voltage doubler rectifier circuit in which two series-connected diodes are connected in parallel, respectively, to each of series-connected 1st to nth capacitors (where n is an integer of 2 or more), and an intermediate capacitor is further connected, respectively, to each intermediate point of the two series-connected diodes; a converter comprising an element configured to be applied with a rectangular waveform voltage during operation; and an input circuit operable, in response to receiving an input of a voltage from the element, to output a voltage to the multi-stage voltage doubler rectifier circuit, wherein the charge device is configured such that the series-connected 1st to nth capacitors are connected to an output part of the converter to thereby charge the 1st to nth capacitors by an output voltage of the converter, and a voltage is input from the element into the multi-stage voltage doubler rectifier circuit via the input circuit to thereby equally charge the 1st to nth capacitors. 
         [0011]    In a charging operation, the charge device charges the series-connected capacitors chain by the output voltage of the converter, while equalizing voltages across the series-connected capacitors chain by utilizing the rectangular waveform voltage applied to the element in the convertor. An electricity storage cell or a group of electricity storage cells may be connected to the series-connected capacitors chain so as to be charged, as mentioned in an aftermentioned embodiment. 
         [0012]    Preferably, the input circuit comprises a first coil connected to the element, and a second coil magnetically coupled to the first coil and connected to the multi-stage voltage doubler rectifier circuit. The input circuit may be composed using a transformer in this manner. In this case, a current ratio between the first coil side and the second coil side can be adjusted, therefore allowing for increased flexibility in design. Particularly, in this embodiment, a series resonance circuit comprising an inductor and a capacitor connected in series is connected to the first coil. The use of the series resonance circuit makes it possible to control a magnitude of (electric) current to flow into the multi-stage voltage doubler rectifier circuit via the input circuit, as mentioned in an aftermentioned embodiment. 
         [0013]    The converter used in the charge device of the present invention may be composed of a bidirectional converter. The use of the bidirectional converter makes it possible to perform charging and discharging of the 1st to nth capacitors, so that the charge device of the present invention becomes capable of operating as a charge-discharge device. 
       Effect of Invention 
       [0014]    In the equalization function-equipped charge-discharge device of the present invention, an equalization function can be newly added by connecting the multi-stage voltage doubler rectifier circuit to a switching node in a charge-discharge device using a conventional converter. In a typical embodiment, charging and discharging of electricity storage cells are mainly performed by the converter, and the multi-stage voltage doubler rectifier circuit is operable to supply only small electric power for eliminating a voltage variation among the electricity storage cells. Thus, a charge-discharge circuit section (converter) and an equalization circuit section (multi-stage voltage doubler rectifier circuit) can be adequately designed separately, so that it becomes possible to reduce a size and cost of the circuit, as compared to the conventional schemes. 
     
    
     
       BRIEF EXPLANATION OF DRAWINGS 
         [0015]      FIG. 1  is a circuit diagram of a conventional one-transistor equalization circuit described in the Patent Document 1. 
           [0016]      FIG. 2  is a circuit diagram of a conventional two-transistor equalization circuit proposed in Japanese Patent Application No. 2012-046569. 
           [0017]      FIG. 3  is a circuit diagram of a conventional one-transistor equalization circuit described in the Patent Document 2. 
           [0018]      FIG. 4 a    is circuit diagram of a step-down converter usable in a charge device and a charge-discharge device of the present invention. 
           [0019]      FIG. 4 b    is circuit diagram of a step-up converter usable in the charge device and the charge-discharge device of the present invention. 
           [0020]      FIG. 4 c    is circuit diagram of a step-up and step-down converter usable in the charge device and the charge-discharge device of the present invention. 
           [0021]      FIG. 4 d    is circuit diagram of a SEPIC converter usable in the charge device and the charge-discharge device of the present invention. 
           [0022]      FIG. 4 e    is circuit diagram of a Zeta converter usable in the charge device and the charge-discharge device of the present invention. 
           [0023]      FIG. 4 f    is circuit diagram of a Cuk converter usable in the charge device and the charge-discharge device of the present invention. 
           [0024]      FIG. 5  is a graph presenting an operating waveform of the SEPIC converter. 
           [0025]      FIG. 6 a    is a diagram illustrating a current pathway under a condition where a switch Q is in an ON state, during operation of the SEPIC converter. 
           [0026]      FIG. 6 b    is a diagram illustrating a current pathway under a condition where the switch Q is in an OFF state, during operation of the SEPIC converter. 
           [0027]      FIG. 7  is a circuit diagram illustrating one example of a multi-stage voltage doubler rectifier circuit and an input circuit. 
           [0028]      FIG. 8  is a graph presenting operating waveforms in the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 7 . 
           [0029]      FIG. 9 a    is a diagram illustrating a current pathway in a mode  1 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 7 . 
           [0030]      FIG. 9 b    is a diagram illustrating a current pathway in a mode  2 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 7 . 
           [0031]      FIG. 10  is a circuit diagram of an equivalent circuit of the multi-stage voltage doubler rectifier circuit illustrated in  FIG. 7 . 
           [0032]      FIG. 11  is a circuit diagram of a system in which series-connected electricity storage cells B 1  to B 4  are connected to an equalization function-equipped charge device comprising a SEPIC converter, an input circuit and a multi-stage voltage doubler rectifier circuit, according to a first embodiment of the present invention. 
           [0033]      FIG. 12  is a circuit diagram, wherein the circuit configuration in  FIG. 7  is changed in terms of a connection point between the multi-stage voltage doubler rectifier circuit and the input circuit. 
           [0034]      FIG. 13 a    is a diagram illustrating a current pathway in a mode  1 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 12 . 
           [0035]      FIG. 13 b    is a diagram illustrating a current pathway in a mode  2 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 12 . 
           [0036]      FIG. 14  is a circuit diagram illustrating the multi-stage voltage doubler rectifier circuit, and another example of the input circuit, wherein a series resonance circuit is used as the input circuit. 
           [0037]      FIG. 15  is a graph presenting operating waveforms in the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 14 , in a DCM (Discontinuous Conduction Mode). 
           [0038]      FIG. 16 a    is a diagram illustrating a current pathway in modes  1  and  5 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 14 . 
           [0039]      FIG. 16 b    is a diagram illustrating a current pathway in modes  2  and  4 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 14 . 
           [0040]      FIG. 17  is a circuit diagram of a system in which the series-connected electricity storage cells B 1  to B 4  are connected to an equalization function-equipped charge device comprising a SEPIC converter, an input circuit (series resonance circuit) and a multi-stage voltage doubler rectifier circuit, according to a second embodiment of the present invention. 
           [0041]      FIG. 18  is graphs presenting a result of an experiment on an equalization function-equipped charge device (a SEPIC converter, a series resonance circuit and a multi-stage voltage doubler rectifier circuit are used in the equalization function-equipped charge device) according to the present invention. 
           [0042]      FIG. 19  is a circuit diaphragm of a bidirectional SEPIC converter usable in the charge device and the charge-discharge device of the present invention. 
           [0043]      FIG. 20  is a graph presenting operating waveforms in the bidirectional SEPIC converter during charging. 
           [0044]      FIG. 21 a    is a diagram illustrating a current pathway under a condition where a switch Qa is in an ON state, and a switch Qb is in an OFF state, during a charging operation of the bidirectional SEPIC converter. 
           [0045]      FIG. 21 b    is a diagram illustrating a current pathway under a condition where the switch Qa is in an OFF state, and the switch Qb is in an ON state, during the charging operation of the bidirectional SEPIC converter. 
           [0046]      FIG. 22  is a graph presenting operating waveforms in the bidirectional SEPIC converter during discharging. 
           [0047]      FIG. 23 a    is a diagram illustrating a current pathway under a condition where the switch Qa is in the OFF state, and the switch Qb is in the ON state, during a discharging operation of the bidirectional SEPIC converter. 
           [0048]      FIG. 23 b    is a diagram illustrating a current pathway under a condition where the switch Qa is in the ON state, and the switch Qb is in the OFF state, during the discharging operation of the bidirectional SEPIC converter. 
           [0049]      FIG. 24  is a circuit diagram of a system in which the series-connected electricity storage cells B 1  to B 4  are connected to an equalization function-equipped charge device comprising a bidirectional SEPIC converter, an input circuit (series resonance circuit) and a multi-stage voltage doubler rectifier circuit, according to a third embodiment of the present invention. 
           [0050]      FIG. 25  is a circuit diagram illustrating a configuration in the case where a converter and a multi-stage voltage doubler rectifier circuit are connected without using any coil. 
           [0051]      FIG. 26 a    is a diagram illustrating a current pathway in a mode  1 , during operations of the multi-stage voltage doubler rectifier circuit and an input circuit illustrated in  FIG. 25 . 
           [0052]      FIG. 26 b    is a diagram illustrating a current pathway in a mode  2 , during operations of the multi-stage voltage doubler rectifier circuit and the input circuit illustrated in  FIG. 25 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0053]    With reference to the drawings, a charge device and a charge-discharge device according to the present invention will now be described. It should be understood that configurations of the charge device and the charge-discharge device according to the present invention are not limited to specific embodied configurations illustrated in the respective drawings, but may be appropriately modified within the scope of the present invention. For example, in the following description, a capacitor will be described mainly as an independent electricity storage element, and an electricity storage cell will be described as a secondary battery, an electric double layer capacitor or the like. Alternatively, each of them may be any chargeable and dischargeable element, or a module composed of a plurality of such elements, or may be any device composed using the module. Further, although a multi-stage voltage doubler rectifier circuit in the following embodiments is described as a 4-stage voltage doubler rectifier circuit, the number of stages of the multi-stage voltage doubler rectifier circuit in the present invention, i.e., the number n of serial-connected capacitors, may be any integer of 2 or more. 
         [0054]    A voltage equalization function-equipped charge device and charge-discharge device of the present invention comprises three functional sections: a converter (charging circuit); an input circuit; and a multi-stage voltage doubler rectifier circuit. As a representative example usable as the converter,  FIGS. 4 a  to 4 f    illustrate, respectively, a step-down converter, a step-up converter, an inverting step-up and step-down converter, a SEPIC converter, a Zeta converter, and a Cuk converter. Respective capacitors comprised in the multi-stage voltage doubler rectifier circuit can be charged by an output voltage of those converters. 
         [0055]    In  FIGS. 4 a  to 4 f   , a rectangular waveform voltage generated at a switching node in the converter is also illustrated. Voltages across the respective capacitors comprised in the multi-stage voltage doubler rectifier circuit can be equalized by inputting the rectangular waveform voltage generated at those switching nodes, into the multi-stage voltage doubler rectifier circuit via the input circuit. 
         [0056]    In the case where there are two switching nodes, as in the SEPIC converter illustrated in  FIG. 4 d   , the Zeta converter illustrated in  FIG. 4 e   , and the Cuk converter illustrated in  FIG. 4 f   , either of the nodes may be used. Although a non-isolated PWM (Pulse Width Modulation) converter has been taken as an example here, it is also possible to use any other non-isolated converter, an isolated converter (half-bridge, full-bridge, etc.), a resonant converter, and the like. Each of the converters illustrated here is a unidirectional converter using a diode, and is therefor usable only in a charge device (or only in a discharge device). A charge-discharge device of the present invention can be constructed by replacing the diode with a switch so as to allow the above converter to be used as a bidirectional converter, as described later. 
         [0057]    As an example, operating waveforms and current pathways during operation of the SEPIC converter in  FIG. 4 d    among the converters illustrated in  FIGS. 4 a  to 4 f    are illustrated, respectively, in  FIG. 5  and  FIGS. 6 a  and 6 b   . In the graph of  FIG. 5 , V Q  represents a voltage applied to a switch Q (wherein a polarity causing a current to flow through the switch Q in a direction illustrated in  FIG. 6 a    is defined as positive), and V L2  represents a voltage applied to an inductor L 2  (wherein a polarity causing a current to flow through the inductor L 2  in a direction illustrated in  FIG. 6 a    is defined as negative). i L  represents a current flowing through an inductor L 1  (L 1  in the graph of  FIG. 5 ) and a current flowing through the inductor L 2  (L 2  in the graph of  FIG. 5 ), and i Do  represents a current flowing through a diode Do in a forward direction. 
         [0058]    During a time period in which the switch Q is in an ON state, a voltage is applied from each of a capacitor Cin and a capacitor Cet to a respective one of the inductor L 1  and the inductor L 2 , so that a current flowing through each of the inductors L 1 , L 2  linearly increases. A voltage applied to the switch Q in this process is zero (on-resistance is ignored). During a time period in which the switch Q is in an OFF state, a current flowing through each of the inductors L 1 , L 2  flows toward a load via the diode Do. Although an induced electromotive force of the inductor L 1  is applied to the switch Q, no current flows therethrough because the switch Q is kept in the OFF state. Further, a voltage (having a polarity opposite to that of the voltage applied from the capacitor Cet during the ON time period of the switch Q) is applied from a capacitor Cout to the inductor L 2 . As above, along with a switching operation, each of the voltage V Q  of the switch Q and the voltage V L2  of the inductor L 2  is formed as a rectangular waveform voltage. 
         [0059]    One example of a multi-stage voltage doubler rectifier circuit and an input circuit is illustrated in  FIG. 7 . The multi-stage voltage doubler rectifier circuit is configured such that two series-connected diodes D 1 , D 2 ; D 3 , D 4 ; D 5 , D 6 ; D 7 , D 8 , are connected in parallel, respectively, to series-connected capacitors Cout 1  to Cout 4 , and intermediate capacitors C 1  to C 4  are connected, respectively, to intermediate points of the two series-connected diodes. 
         [0060]    The input circuit is connected to the multi-stage voltage doubler rectifier circuit, and configured to input, into the multi-stage voltage doubler rectifier circuit, a voltage which is output from an element of the converter. In the example illustrated in  FIG. 7 , the input circuit comprises a first coil connected to the side of the element of the converter, and a second coil magnetically coupled to the first coil, e.g., through an arbitrary core, and further connected to the multi-stage voltage doubler rectifier circuit. A capacitor Cblock connected to the first coil is a blocking capacitor for blocking a DC (direct current) component of a current flowing out from the element of the converter. The number of turn ratio of the first coil:the second coil is expressed as N:1. 
         [0061]    A rectangular waveform voltage generated at an element (switching node) of the aforementioned converter is input between terminals A, B of the input circuit. Then, according to a change in the input rectangular waveform voltage, a charging and discharging current flows through the capacitors Cout 1  to Cout 4 , so that a group of the odd-numbered diodes D 1 , D 3 , D 5 , D 7  and a group of the even-numbered diodes D 2 , D 4 , D 6 , D 8  in the multi-stage voltage doubler rectifier circuit are alternately conducted. 
         [0062]    Specifically, a rectangular waveform voltage (e.g., V Q  in  FIG. 5 ) presented in the graph of V SN  in  FIG. 8 , is input into the input circuit, and, after being subjected to transformation by the transformer and to a DC component removal action of the blocking capacitor Cblock, input into the multi-stage voltage doubler rectifier circuit. In that case, in a mode  1  (see V SN  presented in the graph of  FIG. 8 ), a current flows along a pathway illustrated in  FIG. 9 a   , and, in a mode  2  (see V SN  presented in the graph of  FIG. 8 ), a current flows along a pathway illustrated in  FIG. 9   b.    
         [0063]    Assuming that a capacitance of each of the capacitors Cout 1  to Cout 4  is sufficiently large as compared to a capacitance of each of the intermediate capacitors C 1  to C 4 , when an operating frequency of the input voltage V SN  is sufficiently high, it can be deemed that voltages V Cout1 , V Cout2 , V Cout3 , V Cout4  across the respective capacitors Cout 1 , Cout 2 , Cout 3 , Cout 4  are constant before and after one cycle. On the assumption that a magnitude of the V SN  in the mode  1  is E (thus, a voltage to be input from the second coil into the multi-stage voltage doubler rectifier circuit is E/N), and magnitudes of voltages across the respective intermediate capacitors C 1 , C 2 , C 3 , C 4  in the mode  1  are, respectively, V C1a , V C2a , V C3a  and V C4a , the following formula group (1) can be obtained by applying the Kirchhoff&#39;s second law to the current pathway in  FIG. 9   a.    
         [0000]        E/N−V   Cout2   −V   Cout1   −V   C1a =0 
         [0000]        E/N−V   Cout2   −V   C2a =0 
         [0000]        E/N−V   C3a =0 
         [0000]        E/N+V   Cout3   −V   C4a =0   (1)
 
         [0064]    As to V Cout1  to V Cout4 , a voltage having a polarity causing a current to flow through the capacitor Cout 3  in a direction illustrated in  FIG. 9 a    is defined as positive. As to V C1a  to V C4a  (and aftermentioned V C1b  to V C4b ), a voltage having a polarity causing a current to flow through each of the intermediate capacitors C 1  to C 4  in a direction illustrated in  FIG. 9 a    is defined as negative. 
         [0065]    Similarly, on the assumption that a magnitude of V SN  in the mode  2  is 0 (For example, a voltage of the inductor L 2  comprised in the SEPIC converter in  FIG. 4 d    has positive and negative values. In this case, however, a voltage reference point may be set at a negative voltage so as to allow the V SN  in the mode  2  to become zero), and magnitudes of voltages across the respective intermediate capacitors C 1 , C 2 , C 3 , C 4  in the mode  2  are, respectively, V C1b , V C2b , V C3b  and V C4b , the following formula group (2) can be obtained by applying the Kirchhoff&#39;s second law to the current pathway in  FIG. 9   b.    
         [0000]        V   Cout2   +V   C1b =0 
         [0000]        V   C2b =0 
         [0000]      − V   Cout3   +V   C3b =0
 
         [0000]      − V   Cout3   −V   Cout4   +V   C4b =0   (2)
 
         [0066]    Based on the above formula groups (1) and (2), voltage variations Δ (delta) V C1 =V C1a −V C1b , Δ (delta) V C2 =V C2a −V C2b , Δ (delta) V C3 =V C3a −V C3b , Δ (delta) V C4 =V C4a −V C4b  in the intermediate capacitors C 1  to C 4  between the mode  1  and the mode  2  are calculated as follows. 
         [0000]      Δ V   C1   =E/N−V   Cout1  
 
         [0000]      Δ V   C2   =E/N−V   Cout2  
 
         [0000]      Δ V   C3   =E/N−V   Cout3  
 
         [0000]      Δ V   C4   =E/N−V   Cout4    (3)
 
         [0067]    On the assumption that capacitances of the intermediate capacitors C 1  to C 4  are, respectively, G 1 , G 2 , G 3 , G 4 , considering the relationship: current=frequency×(multiplied by) charge amount=frequency×(multiplied by) capacitance×(multiplied by) voltage variation, currents I C1 , I C2 , I C3 , I C4  flowing, respectively, from the intermediate capacitors C 1  to C 4  to the capacitors Cout 1  to Cout 4  are calculated as follows. 
         [0000]        I   C1   =f×G 1×( E/N−V   Cout1 )
 
         [0000]        I   C2   =f×G 2×( E/N−V   Cout2 )
 
         [0000]        I   C3   =f×G 3×( E/N−V   Cout3 )
 
         [0000]        I   C4   =f×G 4×( E/N−V   Cout4 )   (4)
 
         [0000]    In this formula group (4), f is a frequency of V SN . From the Ohm&#39;s law, it turns out that each of f×(multiplied by) G 1 , f×(multiplied by) G 2 , f×(multiplied by) G 3  and f×(multiplied by) G 4  is a reciprocal of electrical resistance, i.e., dimension of conductance. 
         [0068]    Thus, from the formula group (4), the circuit illustrated in  FIG. 7  can be replaced with an equivalent circuit illustrated in  FIG. 10 . In this equivalent circuit, an equivalent power supply Vdc is a DC power supply having an output voltage E/N, and equivalent resistors R 1  to R 4  are replacements of charging-discharging operations of the respective intermediate capacitors C 1  to C 4  to equivalent resistors. Resistance values of the equivalent resistors R 1 , R 2 , R 3 , R 4  can be expressed, respectively, as 1/(f×(multiplied by) G 1 ), 1/(f×(multiplied by) G 2 ), 1/(f×(multiplied by) G 3 ) and 1/(f×(multiplied by) G 4 ). In the case where G 1 , G 2 , G 3  and G 4  are equal to each other, values of R 1 , R 2 , R 3  and R 4  also become equal to each other. Thus, in the case where voltages across respective capacitors Cout 1  to Cout 4  in  FIG. 10  are equal to each other, currents flowing through the respective equivalent resistors R 1  to R 4  also become equal to each other. That is, the capacitors Cout 1  to Cout 4  are equally charged. 
         [0069]    As a result, the voltages across the respective capacitors Cout 1  to Cout 4  becomes equal to each other in a steady state. Each of the voltages across the capacitors Cout 1  to Cout 4  in a steady state is E/N (where a voltage drop in each of the diodes is ignored). 
       First Embodiment 
       [0070]      FIG. 11  illustrates a circuit diagram of a voltage equalization function-equipped charging system in which four series-connected electricity storage cells group B 1  to B 4  are connected to a charge device according to a first embodiment of the present invention, wherein the charge device comprises the SEPIC converter illustrated in  FIG. 4 d   , and the input circuit and the multi-stage voltage doubler rectifier circuit illustrated in  FIG. 7 . A switching node composed of a connection point of the capacitor Cet, the diode Do and the inductor L 2  in the SEPIC converter is connected to the multi-stage voltage doubler rectifier circuit via the input circuit. An output terminal, i.e., the diode Do, of the SEPIC converter is connected to the capacitors Cout 1  to Cout 4 , and the capacitors Cout 1  to Cout 4  are connected to the electricity storage cells B 1  to B 4 . Therefore, the electricity storage cells B 1  to B 4  are serially charged by an output voltage of the SEPIC converter. On the other hand, the multi-stage voltage doubler rectifier circuit is connected to each of the electricity storage cells B 1  to B 4 . As described using the formula groups (1) to (4), the capacitors Cout 1  to Cout 4  are equally charged, so that currents are supplied, respectively, to the electricity storage cells B 1  to B 4  connected in parallel thereto, depending on a state of voltage variation to thereby eliminate the voltage variation. The SEPIC converter is operable to charge the electricity storage cells B 1  to B 4  under PWM control. A relationship between a magnitude of an input voltage from an input power supply Vin (the magnitude of the input voltage will hereinafter referred to as “V in ”) and a total voltage V total  of the B 1  to B 4  is expressed as the following formula using a time ratio D (a ratio of an ON time period to one switching cycle period of the switch Q). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       total 
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     D 
                     
                       ( 
                       
                         1 
                         - 
                         D 
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0071]    It is considered that the equalization operation described using the formula groups (1) to (4) and the charging operation according to the formula (5) are performed in parallel, thereby making it possible to equally charge the electricity storage cells B 1  to B 4 . 
         [0072]    The number of switches required for the equalization function-equipped charge device according to the present invention is only one (switch Q) in the converter, and the multi-stage voltage doubler rectifier circuit itself for providing a balancing function can be constructed in a switchless manner. Thus, the equalization function-equipped charge device according to the present invention can be constructed using a small number of switches, as with the conventional equalization circuits illustrated in  FIGS. 1 and 2 , so that it becomes possible to significantly simplify a circuit configuration, as compared to the various conventional schemes requiring a large number of switches. Further, in this equalization function-equipped charge device, the converter section having a charging function and the multi-stage voltage doubler rectifier circuit having an equalization function can be optimally designed, individually, so that it becomes possible to achieve compact and economical design, as compared to the conventional equalization function-equipped charger devices. For example, generally, an electric power required for the equalization is significantly less than that required for charging. Thus, it is optimal to design in such a manner that elements for large electric power are used in the converter, and elements for small electric power are used in the multi-stage voltage doubler rectifier circuit. 
         [0073]    The charger illustrated in  FIG. 11  has been described based on the configuration in which the switching node composed of the connection point of the capacitor Cet, the diode Do and the inductor L 2  in the SEPIC converter is connected to the multi-stage voltage doubler rectifier circuit via the input circuit (a configuration in which the multi-stage voltage doubler rectifier circuit is connected to the inductor L 2  to be applied with a rectangular waveform voltage, via the input circuit). Alternatively, another switching node, i.e., a switching node composed of a connection point of the capacitor Cet, the switch Q and the inductor L 1 , may be connected to the multi-stage voltage doubler rectifier circuit via the input circuit to have a similar function (a configuration in which the multi-stage voltage doubler rectifier circuit is connected to the switch Q to be applied with a rectangular waveform voltage, via the input circuit). The voltage equalization function-equipped charge device may be constructed using converters other than the SEPIC converter. 
         [0074]    It should be noted that a position of the multi-stage voltage doubler rectifier circuit to which a voltage for the equalization is input from the input circuit is not limited to the position illustrated in  FIG. 7 , but may be any other suitable position. As one example,  FIG. 12  illustrates a circuit diagram, wherein the circuit configuration in  FIG. 7  is changed in terms of a connection point between the multi-stage voltage doubler rectifier circuit and the input circuit. 
         [0075]    Assuming that a capacitance of each of the capacitors Cout 1  to Cout 4  is sufficiently large as compared to a capacitance of each of the intermediate capacitors C 1  to C 4 , as with the above example using the configuration illustrated in  FIG. 7 , the Kirchhoff&#39;s second law is applied to each of a current pathway illustrated in  FIG. 13 a    (mode  1 ), and a current pathway illustrated in  FIG. 13 b    (mode  2 ), to obtain the following formula groups (6) and (7) (reference signs used in the formula groups (6) and (7), such as reference signs for voltages across respective elements, are the same as those in the formula groups (1) to (4)). 
         [0000]        E/N−V   Cout3   −V   Cout2   −V   Cout1   −V   C1a =0 
         [0000]        E/N−V   Cout3   −V   Cout2   −V   C2a =0 
         [0000]        E/N−V   Cout3   −V   C3a =0 
         [0000]        E/N−V   C4a =0   (6)
 
         [0000]        V   Cout3   +V   Cout2   +V   C1b =0 
         [0000]        V   Cout3   +V   C2b =0 
         [0000]        V   C3b =0 
         [0000]      − V   Cout4   +V   C4b =0   (7)
 
         [0076]    The aforementioned formula group (3) can be obtained from the formula groups (6) and (7). Thus, an operation of the multi-stage voltage doubler rectifier circuit in the configuration illustrated in  FIG. 12  can also be described using the equivalent circuit illustrated in  FIG. 10 . 
       Second Embodiment 
       [0077]    A resonance circuit may also be used as the input circuit. As one example,  FIG. 14  illustrates a circuit diagram of a configuration in which a series resonance circuit is used as the input circuit, and connected to the multi-stage voltage doubler rectifier circuit. 
         [0078]    The series resonance tank is composed of a resonance inductor Lr and a resonance capacitor Cr, and a transformer and the subsequent circuit are the same as those illustrated in  FIG. 7 . A rectangular waveform voltage V SN  generated at a switching node in a converter is applied between terminals A, B, so that a sine wave-shaped AC (alternate current) voltage is input into the multi-stage voltage doubler rectifier circuit. 
         [0079]      FIG. 15  presents operating waveforms generated when the circuit illustrated in  FIG. 14  is operated in a DCM (Discontinuous Conduction Mode). i Lr  represents a current flowing through the resonance inductor Lr (a current flowing in a direction indicated by the arrowed line in  FIG. 14  is defined as positive), and i D(2i-1)  and i D(2i)  represent, respectively, a forward current flowing through each of a group of odd-numbered diodes D 1 , D 3 , D 5 , D 7 , and a forward current flowing through each of a group of the even-numbered diodes D 2 , D 4 , D 6 , D 8 . 
         [0080]    When the rectangular waveform voltage V SN  changes to positive (when the terminal A side in  FIG. 14  has a high potential), a positive current i Lr  starts to flow through the resonance inductor Lr (mode  1  in  FIG. 15 ). The waveform of the current i Lr  changes in a sine wave-like shape due to a resonance phenomenon caused by the resonance inductor Lr and the resonance capacitor Cr, and will decline and eventually become negative (mode  2 ). The current i Lr  reaches a local minimum value, and then re-rises to zero. According to inventors&#39; researches, the current i Lr  will subsequently keep a constant value of zero (mode  3 ). If the rectangular waveform voltage V SN  is switched to negative at this timing, a negative current i Lr  starts to flow through the resonance inductor Lr (mode  4 ). Due to the resonance phenomenon caused by the resonance inductor Lr and the resonance capacitor Cr, the current i Lr  changes in a sine wave-like waveform, and will rise and eventually become positive (mode  5 ). The current i Lr  reaches a local maximum value, and then re-decline to zero. According to inventors&#39; researches, the current i Lr  will subsequently keep a constant value of zero (mode  6 ). When the current i Lr  is positive, a current flows along a pathway illustrated in  FIG. 16 a   , in the multi-stage voltage doubler rectifier circuit. On the other hand, when the current i Lr  is negative, a current flows along a pathway illustrated in  FIG. 16 b   , in the multi-stage voltage doubler rectifier circuit. Corresponding to the fact that the current i Lr  changes in a sine wave-like waveform, a current flowing through each of the diodes in the multi-stage voltage doubler rectifier circuit also changes in a sine wave-like waveform ( FIG. 15 ). 
         [0081]    As above, the multi-stage voltage doubler rectifier circuit in  FIG. 14  operates while taking two pathways illustrated in  FIGS. 16 a  and 16 b   , depending on a polarity of the current i Lr  flowing through the resonance inductor Lr. When the current pathway illustrated in  FIG. 16 a    is established (when the current i Lr  is positive; corresponding to the mode  1  and the mode  5  in  FIG. 15 ), the odd-numbered diodes D( 2   i− 1) (i=1, - - - , 4) in the multi-stage voltage doubler rectifier circuit are conducted. On the other hand, when the current i Lr  is negative (corresponding to the mode  2  and the mode  4  in  FIG. 15 ), the even-numbered diodes D( 2   i ) in the multi-stage voltage doubler rectifier circuit are conducted. In the mode  3  and the mode  6 , no current flows through the circuit. In order to realize an operation in DCM (allow respective time periods of the mode  3  and the mode  6  to exist), it is necessary to determine a switching frequency or a circuit constant in such a manner that a time period of each of a high level and a low level of the voltage V SN  to be applied to the series resonance circuit becomes longer than a resonance period of the series resonance circuit. 
         [0082]    When the series resonance circuit operates in DCM, the current i Lr  flowing through the resonance inductor Lr in each mode can be expressed as the following formula (8) using time t as a function. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       i 
                       Lr 
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     { 
                     
                       
                         
                           
                             
                               
                                 
                                   
                                      
                                     
                                       V 
                                       SN 
                                     
                                      
                                   
                                   / 
                                   2 
                                 
                                 + 
                                 
                                   V 
                                   P 
                                 
                               
                               
                                 Z 
                                 0 
                               
                             
                              
                             sin 
                              
                             
                                 
                             
                              
                             
                               ω 
                               0 
                             
                              
                             t 
                           
                         
                         
                           
                             ( 
                             
                               Mode 
                                
                               
                                   
                               
                                
                               1 
                             
                             ) 
                           
                         
                       
                       
                         
                           
                             
                               
                                 
                                   
                                     - 
                                     
                                        
                                       
                                         V 
                                         SN 
                                       
                                        
                                     
                                   
                                   / 
                                   2 
                                 
                                 + 
                                 
                                   V 
                                   P 
                                 
                               
                               
                                 Z 
                                 0 
                               
                             
                              
                             sin 
                              
                             
                                 
                             
                              
                             
                               ω 
                               0 
                             
                              
                             t 
                           
                         
                         
                           
                             ( 
                             
                               Mode 
                                
                               
                                   
                               
                                
                               2 
                             
                             ) 
                           
                         
                       
                       
                         
                           
                             
                               - 
                               
                                 ( 
                                 
                                   
                                     
                                       
                                          
                                         
                                           V 
                                           SN 
                                         
                                          
                                       
                                       / 
                                       2 
                                     
                                     + 
                                     
                                       V 
                                       P 
                                     
                                   
                                   
                                     Z 
                                     0 
                                   
                                 
                                 ) 
                               
                             
                              
                             sin 
                              
                             
                                 
                             
                              
                             
                               ω 
                               0 
                             
                              
                             t 
                           
                         
                         
                           
                             ( 
                             
                               Mode 
                                
                               
                                   
                               
                                
                               4 
                             
                             ) 
                           
                         
                       
                       
                         
                           
                             
                               - 
                               
                                 ( 
                                 
                                   
                                     
                                       
                                         - 
                                         
                                            
                                           
                                             V 
                                             SN 
                                           
                                            
                                         
                                       
                                       / 
                                       2 
                                     
                                     + 
                                     
                                       V 
                                       P 
                                     
                                   
                                   
                                     Z 
                                     0 
                                   
                                 
                                 ) 
                               
                             
                              
                             sin 
                              
                             
                                 
                             
                              
                             
                               ω 
                               0 
                             
                              
                             t 
                           
                         
                         
                           
                             ( 
                             
                               Mode 
                                
                               
                                   
                               
                                
                               5 
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0083]    In the formula (8), |V SN | represents a voltage amplitude of the rectangular waveform input voltage; V P  represents a voltage to be applied to a first coil ( FIG. 14 ); Z 0  represents a characteristic impedance of the resonance circuit (Z 0 =(Lr/Cr) 0.5 ), where Lr is an inductance of the resonance inductor, and Cr is a capacitance of the resonance capacitor); and ω 0  is a resonance angular frequency (ω 0 =2πfr, where fr is a frequency of the series resonance circuit). 
         [0084]    An operation in the mode  1  to the mode  2  and an operation in the mode  4  to the mode  5  are symmetrical operations. Thus, an average current absolute value of the current i Lr  is derived by integrating absolute values of the currents i Lr  represented in the mode  1  and the mode  2  in the formula (8), over a half cycle T S /2, i.e., calculated by the following formula (9). 
         [0000]    
       
         
           
             
               
                 
                   
                      
                     
                       i 
                       Lr 
                     
                      
                   
                   = 
                   
                     
                       
                         1 
                         
                           
                             T 
                             S 
                           
                           2 
                         
                       
                        
                       
                         
                           ∫ 
                           0 
                           
                             
                               T 
                               S 
                             
                             2 
                           
                         
                          
                         
                           
                              
                             
                               
                                 i 
                                 Lr 
                               
                                
                               
                                 ( 
                                 t 
                                 ) 
                               
                             
                              
                           
                            
                           
                               
                           
                            
                           
                              
                             t 
                           
                         
                       
                     
                     = 
                     
                       
                         2 
                          
                         
                           f 
                           S 
                         
                          
                         
                           V 
                           SN 
                         
                       
                       
                         π 
                          
                         
                             
                         
                          
                         
                           f 
                           r 
                         
                          
                         
                           Z 
                           0 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0085]    In the formula (9), fs represents a switching frequency of the rectangular waveform voltage V SN . As above, in the DCM operation, a current in the circuit can be set to an arbitrary value or less by appropriately setting the switching frequency fs or the circuit constant Z 0 , without using a circuit for current limiting, or feedback control. 
         [0086]    As previously mentioned, in order to allow the series resonance circuit to operate in DCM, a time period of each of a high level and a low level of the voltage V SN  needs to become longer than a resonance period of the resonance circuit. That is, it is necessary to satisfy the following inequality group. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       f 
                       r 
                     
                     &gt; 
                     
                       
                         f 
                         S 
                       
                       
                         D 
                         min 
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     
                       f 
                       r 
                     
                     &gt; 
                     
                       
                         f 
                         S 
                       
                       
                         ( 
                         
                           1 
                           - 
                           
                             D 
                             min 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0087]    In the equality group (10), D min , represents a minimum time ratio during operation of the SEPIC converter. In the converter, although the time ratio D varies according to a ratio between input and output voltages, as shown by the formula (5), as long as the inequality group (10) is satisfied, it is possible to prevent excessive current from flowing through the series resonance circuit and the multi-stage voltage doubler rectifier circuit, so that the charge device can safely operate. 
         [0088]    On the other hand, in other types of resonance circuits, an operating characteristic is largely influenced by variation in time ratio, so that there is a need for some current limiting function or circuit. The same applies to a resonance converter using frequency control instead of time ratio control. 
         [0089]      FIG. 17  illustrates a circuit diagram of an equalization function-equipped charging system in which four series-connected electricity storage cells group B 1  to B 4  are connected to a charge device according to a second embodiment of the present invention, wherein in the charge device, the SEPIC converter illustrated in  FIG. 4 d   , and the input circuit and the multi-stage voltage doubler rectifier circuit illustrated in  FIG. 14  are connected. As previously mentioned, when the rectangular waveform voltage is input into the input circuit, a current flows along each of the pathways illustrated in  FIGS. 16 a  and 16 b   , in the multi-stage voltage doubler rectifier circuit. Thus, in a qualitative aspect, the similar equalization operation as that described using the formula groups (1) to (4) is performed to thereby equalize voltages across the electricity storage cells group B 1  to B 4 . In addition, an output voltage of the SEPIC converter is applied to the electricity storage cells group B 1  to B 4  to thereby charge the electricity storage cells. Further, a current limiting function based on the DCM operation of the series resonance circuit may be utilized to eliminate a need for an additional current limiting function or circuit. 
         [0090]    Although  FIG. 17  describes a configuration in which a switching node composed of a connection point of a capacitor Cet, a diode Do and an inductor L 2  in the SEPIC converter is connected to the multi-stage voltage doubler rectifier circuit, another switching node, i.e., a switching node composed of a connection point of the capacitor Cet, a switch Q and an inductor L 1 , may be connected to the multi-stage voltage doubler rectifier circuit. In this case, it is possible to obtain a similar equalization function. The voltage equalization function-equipped charge device of the present invention may be constructed using converters other than the SEPIC converter. In the above, the series resonance type multi-stage voltage doubler rectifier circuit is shown, but any other suitable resonance scheme may be employed. 
         [0091]      FIG. 18  presents a result of an experiment using an equalization function-equipped charge device (charging electric power: 50 W) according to the present invention. In the experiment, four electric double layer capacitor modules each having an electrostatic capacitance of 220 F were connected in series, and they were subjected to a charging-discharging cycle using the charge device illustrated in  FIG. 17  according to the present invention, for charging, and an electronic load (constant current: 1.8 A) for discharging. Parameters of each element used in the charge device were set as follows. First of all, as regards the SEPIC converter, an inductance of each of the inductors L 1 , L 2 : 100 μH, a capacitance of the capacitor Cet: 20 μF, an ON resistance of an N-Ch MOSFET switch Q: 150 mΩ, and a forward voltage drop of a schottky diode Do: 0.67 V. As regards the multi-stage voltage doubler rectifier circuit, a capacitance of each of intermediate capacitors C 1  to C 4 : 33 μF, a capacitance of each of capacitors Cout 1  to Cout 4 : 66 μF, and a forward voltage drop of each of schottky diodes D 1  to D 8 : 0.43 V. As regards the input circuit, an inductance of the resonance inductor Lr: 15.2 μH, a capacitance of the resonance capacitor Cr: 10 nF, the number of turn ratio of the first coil:a second coil=39:6, and a mutual inductance: 3.09 mH. The experiment was started under the condition that initial voltages of the electric double layer capacitors were non-uniform. During charging, a standard deviation of an electric double layer capacitor module voltage is gradually reduced by the equalization function of the charge device according the present invention (graph with a scale “Standard Deviation”, in  FIG. 18 ). This shows that voltage variation starts to be eliminated. On the other hand, during discharging, the constant-current electronic load is used for discharging. Thus, it is shown that there is not a large change in the standard deviation, and there is no change in the state of voltage variation. The standard deviation is reduced to about 30 mV at a time of completion of two cycles. This has shown that the voltage variation can be eliminated by the equalization function-equipped charge device according to the present invention. In  FIG. 18 , the graph of Module Voltage presents a voltage of each of the electric double layer capacitor modules, and the graph of Total Voltage and Current presents a total voltage and a total current of each of the electric double layer capacitor modules, respectively. 
       Third Embodiment 
       [0092]    The embodiments of the equalization function-equipped charge devices have been described above. The charge devices are constructed using a unidirectional converter configured to transmit electric power in one direction. This charge device of the present invention may be configured using a bidirectional converter so as to allow electric power to be bidirectionally transmitted. By this, an equalization function-equipped charge-discharge device according to the present invention can be obtained. As one example, the charge-discharge device according to the present invention can be obtained by replacing the diode Do in the SEPIC converter comprised in the configuration illustrated in  FIG. 17 , with a switch, so as to use the converter as a bidirectional SEPIC converter. 
         [0093]    Firstly, with reference to  FIGS. 19 to 23   b , an operation of the bidirectional SEPIC converter will be described.  FIG. 19  is a circuit diaphragm of a bidirectional SEPIC converter obtained by replacing the diode in the SEPIC converter with a switch. A power supply Vbat in  FIG. 19  corresponds to the series-connected electricity storage cells B 1  to B 4  ( FIG. 11 ,  FIG. 17 ). In the case where an output voltage [V in ×(multiplied by) D/(1−D)] of the SEPIC converter is greater than a voltage of the power supply Vbat, where V in  represents a voltage of a power supply Vin, the bidirectional SEPIC converter is operable to charger the power supply Vbat (charging mode). In the case where the output voltage of the SEPIC converter is less than the voltage of the power supply Vbat, the bidirectional SEPIC converter is operable to cause the power supply Vbat to perform a discharging operation (discharging mode). 
         [0094]    Current pathways during the charging mode are as illustrated in  FIGS. 21 a    and  21   b , which are similar to the current pathways illustrated in  FIGS. 6 a  and 6 b   . In a mode  1  ( FIG. 21 a   ) where a switch Qa is in an ON state, and a switch Qb is in an OFF state, voltages from the power supply Vin and the capacitor Cet are applied, respectively, to the inductor L 1  and the inductor L 2 , so that currents flowing through the respective inductors L 1 , L 2  linearly increase. A voltage applied to the switch Qa in this process is zero (on-resistance is ignored). In a mode  2  ( FIG. 21 b   ) where the switch Qa is in an OFF state, and the switch Qb is in an ON state, each of the currents flowing through the inductors L 1 , L 2  flows to the power supply Vbat via the switch Qb. Although an induced electromotive force of the inductor L 1  is applied to the switch Qa, no current flows therethrough because the switch Qa is kept in the OFF state. Further, a voltage (having a polarity opposite to that of the voltage applied from the capacitor Cet during the ON time period of the switch Qa) is applied from a capacitor Cout to the inductor L 2 . As above, along with a switching operation, each of a voltage V Qa  of the switch Qa and a voltage V L2  of the inductor L 2  is formed as a rectangular waveform voltage ( FIG. 20 ). Thus, the above elements can be connected to the multi-stage voltage doubler rectifier circuit via the input circuit, thereby making it possible to perform an operation for equalizing voltages across the respective electricity storage cells. 
         [0095]      FIG. 22  presents voltages and currents at the respective elements during the discharge mode, and  FIGS. 23 a  and 23 b    illustrate current pathways during the discharge mode. In a mode  1  ( FIG. 23 a   ) where the switch Qa is in the OFF state, and the switch Qb is in the ON state, a voltage of the power supply Vbat and a total voltage of the power supply Vbat and the capacitor Cet are applied, respectively, to the inductor L 2  and the inductor L 1 , so that currents flowing through the respective inductors L 1 , L 2  linearly increase. Although an induced electromotive force of the inductor L 1  is applied to the switch Qa, no current flows therethrough because the switch Qa is kept in the OFF state. In a mode  2  ( FIG. 23 b   ) where the switch Qa is in the ON state, and the switch Qb is in the OFF state, each of the currents flowing through the inductors L 1 , L 2  flows through the switch Qa. A voltage applied to the switch Qa in this process is zero, and a voltage having a polarity opposite to that of the voltage applied from the power supply Vbat in the mode  1  is applied from the capacitor Cet to the inductor L 2 . As above, along with a switching operation, each of the voltage V Qa  of the switch Qa and the voltage V L2  of the inductor L 2  is formed as a rectangular waveform voltage. Throughout the both time periods, only a current flowing through the inductor L 1  flows toward the power supply Vin. As above, along with a switching operation, each of the voltage V Qa  of the switch Qa and the voltage V L2  of the inductor L 2  is formed as a rectangular waveform voltage ( FIG. 22 ). Thus, the above elements can be connected to the multi-stage voltage doubler rectifier circuit via the input circuit, thereby making it possible to perform an operation for equalizing voltages across the respective electricity storage cells. 
         [0096]      FIG. 24  is a circuit diagram of a charge-discharge system in which a charge-discharge device according to the present invention is connected to the series-connected electricity storage cells B 1  to B 4 , wherein the charge-discharge device configured such that the bidirectional SEPIC converter illustrated in  FIG. 19  is connected to the multi-stage voltage doubler rectifier circuit via the input circuit (series resonance circuit). As with the system illustrated in  FIG. 17 , when the rectangular waveform voltage is input into the input circuit, a current flows along each of the pathways illustrated in  FIGS. 16 a  and 16 b   , in the multi-stage voltage doubler rectifier circuit. Thus, in a qualitative aspect, the same equalization operation as that described using the formula groups (1) to (4) is performed to thereby equalize voltages across the respective electricity storage cells group B 1  to B 4 . In addition, an output voltage of the bidirectional SEPIC converter is applied to the electricity storage cells group B 1  to B 4  to thereby charge and discharge the electricity storage cells. Further, as with the system illustrated in  FIG. 17 , a current limiting function based on the DCM operation of the series resonance circuit may be utilized to eliminate a need for an additional current limiting function or circuit (However, in this configuration, it is not necessary to use the series resonance circuit. For example, the input circuit illustrated in  FIG. 11  may be used. Alternatively, the bidirectional converter and the multi-stage voltage doubler rectifier circuit may be simply connected by a conductive wire without using a transformer, as in an aftermentioned fourth embodiment). 
       Fourth Embodiment 
       [0097]    In the above embodiments, a circuit comprising a transformer is used as the input circuit, and a voltage for equalizing voltages across the respective electricity storage cells is input into the multi-stage voltage doubler rectifier circuit. However, the use of a transformer is not necessary for the present invention. For example, the multi-stage voltage doubler rectifier circuit may be connected to both ends of the inductor L 2  in the SEPIC converter illustrated in  FIG. 4 d    or  FIG. 19  via a conductive wire (serving as an “input circuit” in this embodiment). In this case, the rectangular waveform voltage is input from the inductor L 2  into the multi-stage voltage doubler input circuit, and a current flows along similar current pathways as those in  FIGS. 9 a  and 9 b   . That is, the same equalization operation as that described using the formula groups (1) to (4) is performed to thereby equalize voltages across the respective electricity storage cells group B 1  to B 4 . In addition, the electricity storage cells B 1  to B 4  are charged or discharged by an output voltage of the converter. Therefore, a charge device and charge-discharge device according to the present invention can operate also in this embodiment. 
         [0098]    It should be noted, also in this case, that a position of the multi-stage voltage doubler rectifier circuit to which a voltage for the equalization is input from the input circuit may be arbitrarily set. For example, in a multi-stage voltage doubler rectifier circuit illustrated in  FIG. 25 , when the rectangular waveform voltage V SN  from an element in a converter is input between terminals A, B as shown in that Figure, a current pathway flowing through the multi-stage voltage doubler rectifier circuit are switched between pathways illustrated in  FIG. 26 a    (mode  1 ) and  FIG. 26 b    (mode  2 ). On the assumption that each reference sign is defined in the same manner as that in the formula groups (1) to (4), according to the Kirchhoff&#39;s second law, the following formula group is satisfied in the mode  1 . 
         [0000]        E−V   Cout1   −V   C1a =0 
         [0000]        E−V   Cout2   −V   Cout1   −V   C2a =0 
         [0000]        E−V   Cout3   −V   Cout2   −V   Cout1   −V   C3a =0 
         [0000]        E−V   Cout4   −V   Cout3   −V   Cout2   −V   Cout1   −V   C4a =0   (11)
 
         [0000]    Further, the following formula group is satisfied in the mode  2  (wherein a waveform of the rectangular waveform voltage V SN  is set to that illustrated in  FIG. 8 , and polarities of V C1a  to V C4a  and V C1b  to V C4b  are defined to be reverse to those at the time when deriving the formula groups (1) to (4)). 
         [0000]        V   C1b =0 
         [0000]        V   Cout1   +V   C2b =0 
         [0000]        V   Cout1   +V   Cout2   +V   C3b =0 
         [0000]        V   Cout1   +V   Cout2   +V   Cout3   +V   C4b =0   (12)
 
         [0099]    From the formula groups (11) and (12), a voltage variations Δ (delta) V C1 =V C1a −V C1b , Δ (delta) V C2 =V C2a −V C2b , Δ (delta) V C3 =V C3a −V C3b , Δ (delta) V C4 =V C4a −V C4b  in the intermediate capacitors C 1  to C 4  between the mode  1  and the mode  2  are calculated as follows. 
         [0000]      Δ V   C1   =E−V   Cout1  
 
         [0000]      Δ V   C2   =E−V   Cout2  
 
         [0000]      Δ V   C3   =E−V   Cout3  
 
         [0000]      Δ V   C4   =E−V   Cout4    (13)
 
         [0100]    Thus, an operation of the multi-stage voltage doubler rectifier circuit illustrated in  FIG. 25  can also be described using the equivalent circuit illustrated in  FIG. 10 . Thus, the electricity storage cells group can be equally charged by a charge device configured, for example, such that both ends of the inductor L 2  in the SEPIC converter illustrated in  FIG. 4 d    are directly connected, respectively, to the terminals A, B of the multi-stage voltage doubler rectifier circuit illustrated in  FIG. 25 , using conductive wires, and an output part of the SEPIC converter is connected to both ends of the series-connected capacitors C 1  to C 4 . 
       INDUSTRIAL APPLICABILITY 
       [0101]    A charge device and a charge-discharge device for equally charging electricity storage cells such as secondary batteries or electric double layer capacitors can be configured according to the present invention. The present invention can be widely applied to a power supply using electricity storage cells such as secondary batteries and electric double layer capacitors. 
       LIST OF REFERENCE SIGNS 
       [0000]    
       
         B 1  to B 4 : electricity storage cell 
         Cout 1  to Cout 4 : capacitor 
         C 1  to C 4 : intermediate capacitor 
         D 1  to D 8 : diode 
         Cblock: blocking capacitor 
         Lr: resonance inductor 
         Cr: resonance capacitor 
         Vin, Vbat: power supply 
         L 1 , L 2 : inductor 
         Q, Qa, Qb: switch 
         Do: diode 
         Cet: capacitor