Abstract:
Disclosed is an address comparator configured to flow a current only for an initial short time, but not at other times, such as when an address is input thereto for a repair operation. The address comparator includes a plurality of unit address comparators comparing addresses received for the repair operation, a PMOS transistor turned on for a short time, an NMOS transistor controlling a current flow through the plurality of unit address comparators , and a PMOS transistor turned off when the plurality of unit comparators allows the current flow, and turned on when the plurality of unit comparators does not allow the current flow.

Description:
BACKGROUND  
       [0001]     1. Field of the Disclosure  
         [0002]     The present disclosure relates to semiconductor memory devices and, more specifically, to an address comparator with decreased current consumption.  
         [0003]     2. Discussion of Related Technology  
         [0004]     A memory chip typically has a storage space that is substituted for a normal storage space when the normal storage space is defective, for which a redundancy circuit is provided to the memory chip. There are various techniques for storing information about a defective memory address to be substituted. One technique for storing redundancy information is a fuse cutting method using laser option. An operation substituting a defective cell with a spare cell is referred to as a repairing operation. In such cases, an address comparison step precedes the repairing operation.  
         [0005]      FIG. 1  is a circuit diagram illustrating a conventional address comparator, and  FIG. 2  is a circuit diagram illustrating an operation of the address comparator shown in  FIG. 1 . Referring to  FIG. 1 , a conventional address comparator includes fuses F 0 -Fn, NMOS transistors MN and MN 0 -MNn, a PMOS transistor MP 1 , inverters IV 1 -IV 3 , a N 0 R gate NR 1 , and a capacitor CP 1 , for carrying out address comparison with cutting fuses oppositely arranged against a corresponding address.  
         [0006]     In operation, and with reference to  FIG. 2 , a repairing operation is accomplished by cutting the fuse F 0  connected to a power source voltage VCC and cutting the fuses F 1 -Fn in suit with the arrangement of addresses A 0 -An and /A 0 -/An.  
         [0007]     As an example, when the address A 1 :A 0 =10 is required to be repaired, the fuses F 1  and F 4  are cut off. Then, the NMOS transistors MN 2  and MN 3  are turned on to flow a current. Thereby, a node RF becomes logical low, while a repair signal RFEN becomes logical high.  
         [0008]     During this, as the PMOS transistor MP 1  continues to be turned on, it may be problematic to maintain a current flow if the address A 1  and A 0  are activated a long time. If the PMOS transistor MP 1  is decreased in size in order to reduce the current flow, it may cause the response speed of the repair signal RFEN to be lower.  
       SUMMARY OF THE DISCLOSURE  
       [0009]     Disclosed herein is an address comparator configured to allow current flow only for an initial short time period, but not at other times, even when an address is input thereto for a repair operation.  
         [0010]     In accordance with one aspect of the disclosure, an address comparator includes a plurality of unit address comparators connected between first and second nodes to compare addresses input for a repairing operation, a first precharging circuit to precharge the first node for a short time, a first discharging circuit to control a current flow through the plurality of unit address comparators connected between the first and second nodes, and a second precharging circuit inactivated when the current flow is allowed and to precharge the first node when the current flow is not allowed.  
         [0011]     In one embodiment, the address comparator further includes an enable signal generator configured to generate an enable signal for operating the plurality of unit address comparators. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The accompanying drawings are included to provide further details regarding the disclosed address comparator, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosed address comparator and, together with the description, also serve to set forth principles, features and aspects of the disclosed address comparator. In the drawings:  
         [0013]      FIG. 1  is a circuit diagram illustrating a conventional address comparator;  
         [0014]      FIG. 2  is a circuit diagram illustrating an operation of the address comparator shown in  FIG. 1 ;  
         [0015]      FIG. 3  is a circuit diagram illustrating an address comparator in accordance with one embodiment of the disclosure;  
         [0016]      FIG. 4  is a circuit diagram illustrating an operation of the address comparator shown in  FIG. 3 ; and  
         [0017]      FIG. 5  is a timing diagram illustrating the operation of the address comparator shown in  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0018]     A number of embodiments of the disclosed address comparator will be described below in more detail with reference to the accompanying drawings. The disclosed address comparator may, however, be embodied in different forms and should not be considered to be limited to the embodiments set forth herein. Rather, the exemplary nature of these embodiments will fully convey the scope of the appended claims to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Further, like numerals refer to like elements throughout the specification.  
         [0019]      FIG. 3  is a circuit diagram illustrating an address comparator in accordance with one embodiment of the disclosed address comparator that includes unit address comparators  310 ,  320  and  330 , an enable signal generator  340 , PMOS transistors P 11  and P 12 , an NMOS transistor N 17 , and an inverter IV 14 . The PMOS transistor P 11  has a terminal connected to a power source voltage VCC and another terminal connected to a node RF, the transistor P 12  being turned on or off in response to a reset signal RST applied to its gate. The PMOS transistor P 11  is turned on to precharge the node RF only when the reset signal RST is applied with a logical low pulse, which may have a short duration to minimize or decrease current consumption. The inverter IV 14  inverses a signal of the node RF and outputs a repair signal RFEN.  
         [0020]     The PMOS transistor P 12  has a terminal connected to a power source voltage VCC and another terminal connected to the node RF, the transistor P 12  being turned on or off in response to the output signal of the inverter IV 14  applied to its gate. The PMOS transistor P 12  is turned on to precharge the node RF when the node RF is set to a logical high, and turned off when the node RF is at a logical low. In other words, if the unit address comparators  320 ,  330  and  340  allow a current flow, the node RF becomes logical low to turn the PMOS transistor P 12  off.  
         [0021]     The unit address comparator  310  includes NMOS transistors N 11  and N 12 , and fuses FS 11  and FS 12 . The NMOS transistor N 11  has a terminal connected to the node RF and another terminal connected to an end of the fuse FS 11 , the transistor N 11  receiving the address bit A 0  through to its gate. The NMOS transistor N 12  has a terminal connected to the node RF and another terminal connected to an end of the fuse FS 12 , the transistor N 12  receiving the address bit/A 0  through to its gate. The fuse FS 11  is connected between the NMOS transistors N 11  and N 13 , while the fuse FS 12  is connected between the NMOS transistors N 12  and N 14 . The other ends of the fuses FS 11  and FS 12  connected to the transistors N 13  &amp; N 14  are also connected to each other.  
         [0022]     The unit address comparator  320  includes the NMOS transistors N 13  and N 14 , and fuses FS 13  and FS 14 . The NMOS transistor N 13  is connected between the fuses FS 11  and FS 13 , and receives the address bit A 1  through its gate. The NMOS transistor N 14  is connected between the fuses FS 12  and FS 14 , and receives the address bit/A 1  through its gate. The fuse FS 13  is connected between the NMOS transistors N 13  and N 15 . The fuse FS 14  is connected between the NMOS transistors N 14  and N 16 . Ends of the fuses FS 13  and FS 14  connected to the transistors N 15  and N 16  are also connected to each other.  
         [0023]     The unit address comparator  330  includes the NMOS transistors N 15  and N 16 , and fuses FS 15  and FS 16 . The NMOS transistor N 15  is connected between the fuses FS 13  and FS 15 , and receives the address bit A 2  through its gate. The NMOS transistor N 16  is connected between the fuses FS 14  and FS 16 , and receives the address bit/A 2  through its gate. The fuse FS 15  is connected between the NMOS transistor N 15  and anode NC. The fuse FS 16  is connected between the NMOS transistor N 16  and the node NC.  
         [0024]     The enable signal generator  340  is provided to activate the unit address comparators  310 ,  320  and  330 , and includes a fuse FS 10 , a capacitor CP 11 , an NMOS transistor N 10 , and inverters IV 11 , IV 12  and IV 13 . The fuse FS 10  is connected to the power source voltage VCC at one end and connected to a node NA at another end. The inverter IV 11  inverts a signal of the node NA. The NMOS transistor N 10  is connected to the node NA through one terminal thereof and connected to the ground voltage VSS through another terminal thereof, the transistor N 10  receiving an output signal of the inverter IV 11  through it gate. The capacitor CP 11  is connected between the node NA and the ground voltage VSS, the capacitor CP 11  being coupled with the NMOS transistor N 10  in parallel. The inverters IV 12  and IV 1  transfer the output signal of the inverter IV 11  with a delay.  
         [0025]     An NMOS transistor N 17  is connected to the node NC through one terminal thereof and connected to the ground voltage VSS through another terminal thereof, the transistor N 17  being turned on or off in response to an output signal of the enable signal generator  340  applied to its gate. The NMOS transistor N 17  is turned on to enable discharging when the output signal of the enable signal generator  340  is at a logical high, so that the node NC is connected to the ground voltage VSS and the unit address comparators  310 ,  320  and  330  can be conductive.  
         [0026]      FIG. 4  is a circuit diagram illustrating an operation of the address comparator shown in  FIG. 3 , and  FIG. 5  is a timing diagram illustrating the operation of the address comparator shown in  FIG. 3 . Specifically, an operation of comparing addresses in conjunction is now described in connection with.  FIGS. 4 and 5 .  
         [0027]     First, in order to activate the redundancy circuit (not shown) for utilization, i.e., in order to initiate the repairing operation, the fuse FS 10  connected to the power source voltage VCC is cut, along with those fuses of fuses FS 11 , FS 12 , FS 13 , FS 14 , FS 15  and FS 16  suitable for the arrangement of the address bits A 0 -A 2  and /A 1 -/A 2 . Cutting the fuse FS 10  causes the NMOS transistor N 17  to be activated.  
         [0028]     For instance, in the case of repairing the address A 2 :A 1 :A 1 =110, the fuses FS 11 , FS 14 , and FS 16  are cut off as illustrated in  FIG. 4 . In this case, if the reset signal RST is applied to the transistor P 11  as a low pulse for a time to take a node RF to a high level as shown in  FIG. 5 , the PMOS transistor P 11  is turned on and the node RF goes to logical low. But if the address bits A 2 , A 1 , and A 0  are supplied with  110  and the NMOS transistor N 17  is being turned on, the NMOS transistors N 12 , N 13 , and N 15  are turned on to flow a current I and the repair signal RFEN becomes logical high. Thus, the current I flows only when the reset signal RST remains low for a short time t rst , as shown in  FIG. 5 , and no current flows thereafter. Thus, the time t rst  may be a time period selected or predetermined to minimize or decrease current consumption. As a further result, there is no need to control the address comparator on or off with a signal RDEN, and instead the reset signal RST is input with a low pulse at the time when an address for repairing is introduced thereto. Unless the address for repairing is introduced thereto, i.e., if the address A 2 :A 1 :A 0 =100 is input thereto, there is no flow of the current I and thereby the node RF is floated. The node RF becomes logical high when the reset signal RST is being on logical low at the initial state, and retains the logical high, without being floated, by a turn-on state of the PMOS transistor P 12  even if the PMOS transistor P 11  is turned off.  
         [0029]     As described above, the disclosed address comparator is advantageous for reducing current consumption in a semiconductor memory device by limiting current flow through an address comparator to an initial short time even if an address for repairing is introduced therein.  
         [0030]     Moreover, the address comparator disclosed herein is effective in reducing current consumption for a chip in need of low current during a standby mode or, more generally, for a low-power chip.  
         [0031]     Although the disclosed address comparator has been described in connection with the embodiments illustrated in the accompanying drawings, it shall be understood that the scope of the disclosed address comparator is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.