Abstract:
An image apparatus and method is disclosed for extending the dynamic range of an image sensor. A first linear pixel circuit produces a first pixel output signal based on charge integration by a first photo-conversion device over a first integration period. A second linear pixel circuit produces a second pixel output signal based on charge integration by a second photo-conversion device over a second integration period, where the second integration period is shorter than the first integration period. A sample-and-hold circuit captures signals representing the first and second pixel output signals.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation of U.S. application Ser. No. 10/294,686, filed Nov. 15, 2002, the disclosure of which is herewith incorporated by reference in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the pixel structure used in a CMOS active pixel array. 
       BACKGROUND OF THE INVENTION 
       [0003]    The dynamic range (DR) for an image sensor is commonly defined as the ratio of the largest nonsaturating signal to the standard deviation of noise under dark conditions. The quality of an image sensor is largely defined by its dynamic range—as it increases, the sensor can detect a wider range of illuminations and consequently produce images of greater detail and quality. 
         [0004]    Several pixel architectures have been developed in an effort to produce good dynamic range. However, conventional pixel architectures are subject to one or more of the drawbacks of high photodiode dark current, thermal (kTC) noise, fixed light sensitivity ratio and charge leakage. Moreover, when logarithmic architectures are used to increase dynamic range, a more complicated color pixel processing is required. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    The present invention provides a pixel architecture which seeks to mitigate many of the noted drawbacks and employs a dual pixel pinned photodiode architecture operating in a dual charge integration. The two pixels enable a dual sensitivity pixel array in which one pixel functions to reproduce normal images, while the other pixel functions to reproduce images with high illumination levels. The dual charge integration mode and dual sensitivity, in combination, produce a pixel architecture having good dynamic range without having to resort to a logarithmic pixel architecture. 
         [0006]    Various dual pixel, dual integration mode embodiments are provided together with associated operating methods. These and other features and advantages of the invention will be more closely described from the following detailed description provided in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0007]      FIG. 1  is a schematic diagram of a first embodiment of a pixel in accordance with the invention; 
           [0008]      FIG. 2  is a timing diagram illustrating operation of the embodiment shown in  FIG. 1 ; 
           [0009]      FIG. 3  is a schematic diagram of a second embodiment of a pixel circuit in accordance with the invention; 
           [0010]      FIG. 4  is a timing diagram illustrating operation of the embodiment shown in  FIG. 3 ; 
           [0011]      FIG. 5  is a schematic diagram of a third embodiment of a pixel circuit in accordance with the invention; 
           [0012]      FIG. 6  is a timing diagram illustrating operation of the  FIG. 5  embodiment; and 
           [0013]      FIG. 7  is a graph illustrating an example of signal transfer characteristics according with the present invention; 
           [0014]      FIG. 8  is an example of pixel and on-chip microlens placement. 
           [0015]      FIG. 9  is an example system according to an embodiment described herein. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]      FIG. 1  illustrates a first embodiment of the present invention, wherein the circuit comprises an upper pixel circuit  130  and a lower pixel circuit  131 . The upper pixel circuit is defined by pinned photodiode PPD 1  ( 110 ), transfer transistor  100 , floating diffusion node “A,” a capacitor  108  coupled to node “A”, source follower transistor  102  having a gate connected to node “A” and a row select transistor  103 . The pixel circuit includes a reset transistor  101 , which operates in response to a reset pulse signal φ RS  applied to its gate. Row select transistor  103  is further coupled to the first of two column signal lines (COL.  1 ) and receives a row select pulse signal φ RD  at its gate. Transfer transistor  100  is responsive to a transfer pulse signal φ T1  applied to its gate to transfer charge from the pinned photodiode  110  to diffusion node “A.” The upper pixel circuit is operated to handle “normal” light conditions (i.e., from low light to medium light levels) and has high sensitivity characteristics by use of a longer integration time (T INT1 ,  FIG. 2 ). Capacitor  108  may be the parasitic capacitance of node “A” or a discrete capacitor. 
         [0017]    The lower pixel circuit  131  is defined by pinned photodiode PPD 2  ( 111 ), transfer transistor  107 , floating diffusion node “B,” capacitor  109 , coupled to node “B,” source follower transistor  105  having a gate connected to node “B” and a row select transistor  104 . Pixel circuit  131  also includes reset transistor  106 , having a gate which receives a reset pulse signal φ RS . Row select transistor  104  is further coupled to the second of two column signal lines (COL.  2 ). Transfer transistor  107  is responsive to a transfer pulse signal φ T2  applied to its gate to transfer charge from pinned photodiode  111  to floating diffusion node “B.” The lower pixel circuit is operated to have a lower sensitivity to handle very high light levels by use of a shorter integration time T INT2  ( FIG. 2 ). Capacitor  109  may be the parasitic capacitance of node “B” or a discrete capacitor. 
         [0018]    Both column lines (COL.  1 , COL.  2 ) are output to respective sample-and-hold circuits  120 ,  121  for obtaining respective pairs of an integrated pixel (V SIG1 , V RST1 ) for pixel circuit  130 , and (V SIG2 , V RST2 ) for pixel circuit  131 . With the 2-column signal line configuration shown in  FIG. 1 , common reset φ RS , row select φ RD , sample reset signal φ SHR  and sample integration pixel φ SHS  can be used for both pixels. An exemplary timing diagram disclosing operation of the circuit of  FIG. 1 , is illustrated in  FIG. 2 . The timing diagram illustrates the relationship between signals φ RS , φ T1 , φ T2 , φ RD , φ SHR1 , φ SHS1 , φ SHR2 , and φ SHS2 . An integration time shown in  FIG. 2  corresponds to the period between the falling edge and the rising edge of transfer pulse φ T . In the illustrated embodiment, the pixel signal integration time occurs during a frame time between horizontal blanking periods (H-BL) corresponding to a respective row. 
         [0019]    Since signal charge accumulates on each pinned photodiode during the integration period (typically a few 10 s of a ms), and the time for the signal charge to stay on the floating diffusion is very short (a few μs during blank-out period H-BL), signal degradation due to leakage current is negligible. This is true even if the leakage current on the floating diffusion node is relatively large (assuming the leakage current of the pinned diode is sufficiently low). During the integration period, reset pulse φ RS  is turned ON so that the floating diffusion acts as a lateral overflow drain. When a Correlated Double Sampling (CDS) operation is used in which both reset (V RST ) and charge integration (V SIG ) signals are taken during the same image frame, little kTC noise appears with the proper pulse timing, and a very low dark current exists as a result. 
         [0020]    Turning to  FIG. 2 , during the charge integration period (T INT1  for pixel  130 , and T INT2  for pixel  131 ), electrons accumulate across the pinned photodiodes  110  and  111 . As reset pulse signal φ RS  is brought high during the blanking period, it turns reset transistors  101  and  106  on and resets the floating diffusion nodes A and B in pixel circuits   130 ,  131  from any previous integration cycle. Thus, a potential on floating diffusion nodes A and B is set at V RS . 
         [0021]    After the reset signal φ RS  is returned to its initial low potential, the sample and hold circuitry ( 120 ,  121 ) briefly samples the potential of the floating diffusion nodes A and B. As can be seen from  FIG. 2 , φ SHR1  and φ SHR2  sample signals are pulsed concurrently. 
         [0022]    As shown in  FIG. 2 , the integration period T INT1  for pixel  130  begins first when the transfer gate signal φ T1  is low. During integration period T INT1 , charge is accumulated by photodiode  110 . The integration period T INT2  for pixel  131  begins after that of pixel  130  when transfer signal φ T2  goes low. During integration period T INT2  charge is accumulated by photodiode  111 . Then, transfer pulses φ T1  and φ T2  are turned on and the charge stored on pinned photodiodes are transferred to the floating diffusion nodes ( 110 →A,  111 →B). After the transfer pulses φ T1  and φ T2  are returned to their initial low potential, the sample and hold circuitry ( 120 ,  121 ) briefly samples the potential of the floating diffusion nodes A and B. As can be seen from  FIG. 2 , φ SHS1  and φ SHS2  sample signals are pulsed concurrently. Once the sample signals V SIG1 , V SIG2  are obtained, the pixel circuits  130 ,  131  are ready to begin a charge integration period. 
         [0023]      FIG. 3  illustrates a second embodiment of the present invention, wherein one column signal line ( 310 ) is being used to output the signals from two pixels  320 ,  321 . The circuit of  FIG. 3  obtains two sets of output signals (V RST1 , V SIG1 ; V RST2 , V SIG2 ), and the charge transfer operation for the two pixels is performed sequentially (as shown by the timing diagram in  FIG. 4 ). 
         [0024]    The upper pixel circuit  320  of the pixel configuration includes a transfer transistor  300 , having a source coupled to pinned photodiode PPD 1   307 , a drain coupled to floating diffusion node “A,” a capacitor  305  having one terminal coupled to diffusion node “A” and to the drain of transfer transistor  300  and another terminal coupled to ground. An anode of pinned photodiode  307  is also coupled to ground. The gate of transfer transistor  300  receives transfer control signal φ T1 . Reset transistor  301  is coupled to both the upper and lower pixel circuits  320 ,  321  at node “A”, and is triggered by reset pulse signal φ RS . The upper pixel circuit  320  is operated to handle normal light conditions, and is set to have high sensitivity characteristics by use of a longer integration time T INT1  ( FIG. 4 ). Capacitor  305  may be the parasitic capacitance of node “A” or a discrete capacitor. 
         [0025]    The lower pixel circuit  321  includes transfer transistor  304 , having a source coupled to pinned photodiode PPD 2  ( 308 ), and a drain coupled to floating diffusion node “A”. The pinned photodiode  308  is also coupled to ground. The gate of transfer transistor  304  receives transfer control signal φ T2 . The lower pixel circuit  321  is operated to have lower light sensitivity to handle very high light levels by use of a shorter integration time T INT2  ( FIG. 4 ). 
         [0026]    The upper pixel and lower pixel circuits  320 ,  321  output respective reset signals (V RST1 , V RST2 ) and integration signals (V SIG1 , V SIG2 ) to a source follower transistor   302 , which is further coupled to row select switch  303 . The gate of row select switch  303  is coupled a row select pulse signal φ RD , and the source of switch  303  is coupled to the column signal line (COL). The column signal line outputs the signals V SIG1 , V SIG2 , as well as reset signals V RST1 , V RST2 . 
         [0027]    An exemplary timing diagram depicting operation of the circuit in  FIG. 3  is shown in  FIG. 4 . The sample and hold circuit  330  for the  FIG. 3  embodiment operates in response to applied sample signals φ SHR1 , φ SHS1 , φ SHR2 , and φ SHS2  to sample and hold the pixel signal V RST1 , V SIG1 , V RST2  and V SIG2 . Similar to the timing diagram in  FIG. 2 , the two integration times T INT1  (long) and T INT2  (short) are respectively set by the transfer pulse signals φ T1 , φ T2 . 
         [0028]    Starting with reset, the floating node “A” is twice reset during the horizontal blanking period (H-BL) by the two pulse signals φ RS , which turn on reset transistor  301 . The row select signal φ RD  turns on row select transistor  303  during the entire blanking period. The reset voltage V RST2  of pixel  321  is sampled by applying the φ SHR2  signal to sample and hold circuit  330 . Then the transfer pulse for the lower pixel circuit φ T2  turns on and the charge stored on the pinned photodiode  308  is transferred to the node “A”. When the integration period T INT2  ends by signal φ T2  returning high and transferring charge to node “A,” the integration charge signal V SIG2  is sampled and held by sample and hold circuit  330  in response to sample signal φ SHS2 . After V SIG2  is sampled and held, the reset pulse is again turned on, thereby clearing the charge on the floating diffusion node “A”. The reset voltage V RST1  of pixel  320  is sampled by applying the φ SHR1  signal to sample and hold circuit  330 . Then the transfer pulse for the upper pixel circuit φ T1  turns on and the charge stored on the pinned photodiode  307  is transferred to the node “A”. When the integration period T INT1  ends by signal φ T1  returning high and transferring charge to node “A,” the integration charge signal V SIG1  is sampled and held by sample and hold circuit  330  in response to sample signal φ SHS1 . Charge integration for pixel  320  begins when transfer signal φ T1  goes low to begin the longer integration period T INT1 , while charge integration for pixel  321  begins when transfer signal φ T2  goes low sometime in the frame time to begin the shorter integration period T INT2 . Thus, a single column line (COL) and sample and hold circuit  330  can be used for the two pixel circuits  320 ,  321  to provide the pixel signals V RST1 , V SIG1 , and V RST2 , V SIG2 . 
         [0029]    A third embodiment of the present invention is illustrated in  FIG. 5 , where the circuit comprises an upper and lower pixel circuits  520 ,  521 , with the upper pixel circuit   520  including pinned photodiode PPD 1  ( 510 ), transfer transistor  502 , coupled between the photodiode  510  and floating diffusion node FD 1 , and the capacitor  507  having one terminal connected to floating diffusion node FD 1  and another terminal coupled to ground, reset transistor  500  coupled between a reset voltage V RS  and node FD 1 , and capacitor  506  having one terminal coupled to capacitor  507  and the terminal coupled to a floating gate line  560  shared with lower pixel circuit  521 . The reset transistor  500  receives a reset control signal φ RS  at its gate. The upper pixel circuit  520  provides an output on line  560  coupled to transistor  501  which has one side connected to voltage V RFG  and another side connected to common floating gate line  560 . The gate of transistor  501  receives a control signal φ RFG . 
         [0030]    The lower pixel circuit includes pinned photodiode PPD 2  ( 511 ), transfer transistor  505 , coupled between the photodiode  511  and floating diffusion node FD 2 , a capacitor  509  having one terminal connected to node FD 2  and another terminal connected to ground, reset transistor  504  coupled between a reset voltage V RS  and node FD 2 , a capacitor  508  having one terminal connected to node FD 2  and another terminal connected to floating gate line  560 . Reset transistor  504  also has a gate connected to reset control signal φ RS . Transfer transistors  502  and  505  are respectively controlled by transfer control signals φ T1  and φ T2 . 
         [0031]    In the third embodiment, the two pinned photodiodes ( 510 ,  511 ) accumulate signal charge during the integration times T INT1  and T INT2  respectively. Then, during the horizontal blanking period (H-BL), the accumulated charges at the photodiodes  510 ,  511  are transferred to the floating diffusion nodes (“FD 1 ”, “FD 2 ”) respectively, wherein the signal voltages are added at the gate of transistor  503  (node V FG ) and sampled and held by sample signal φ SHS . The diffusion regions FD 1  and FD 2  are reset by respective reset transistors  500  and  504 , which have their gates commonly connected to receive reset control signal φ RS . The reset signals from the two pixels are combined at the gate of the transistor  503  and sampled and held by sample signal φ SHR . Voltages at the V FG  node and FD 1  and FD 2  nodes are summarized in Table 1, shown below. The table shows the on/off states of the timing signals of  FIG. 6 , and five different operational states denoted by signal subscripts 0, 1, 2, 3, 4 for pixel circuits  520  (i=1) and  521  (i=2). 
         [0000]    
       
         
               
             
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 V FG  and V FD, i  (i = 1, 2) 
               
             
          
           
               
                 Timing 
                 V FG   
                 V FD, i   
               
               
                   
               
             
          
           
               
                 φ RS  = ON 
                 φ RFG  = ON 
                 V FG     —   0 = V RFG   
                 V FD, i     —   0 = V RS   
               
               
                 φ RS  = ON 
                 φ RFG  = OFF 
                 V FG     —   1 = V RFG  + 
                 V FD, i     —   1 = V RS   
               
               
                   
                   
                 v kTC, FG   
               
               
                 φ RS  = OFF 
                 φ RFG  = OFF 
                 V FG     —   2 = V FG1  + 
                 V FD, i     —   2 = V RS  + 
               
               
                   
                   
                 α · (v kTC, FD1 ) + 
                 v kTC, FD, i   
               
               
                   
                   
                 β · (v kTC, FD2 ) 
               
               
                 φ T1  = ON 
                 φ T2  = ON 
                 V FG     —   3 = V FG     —   2 + 
                 V FD, i     —   3 = V FD, i     —   2 + 
               
               
                   
                   
                 α · V sig1  + β · V sig2   
                 V sig, i   
               
               
                 φ T1  = OFF 
                 φ T2  = OFF 
                 V FG     —   4 = V FG     —   3 
                 V FD, i     —   4 = V FD, i     —   3 
               
               
                   
               
             
          
         
       
     
         [0032]    During a first operational state (phase 0), the floating diffusion nodes FD 1  and FD 2  are reset at V RS , while the floating gate line is reset at V RFG . During a second operational state (phase 1) the pulse φ RFG  is turned off, and the kTC noise, v kTC,FG , appears on the floating gate line. During a third operational state (phase 2), the reset pulse φ RS  is turned off, and the kTC noise, v kTC,FD,i , appears on the floating diffusion nodes FD 1  and FD 2 . At this moment, these kTC noise voltages, v kTC,FD,1 , and v kTC,FD,2 , affect the floating gate line potential through coupling capacitors  506  and  508 , and the resulting floating gate potential is shown in the third row of Table 1. This floating gate potential is sampled and held by pulsing the reset sampling pulse φ SHR . 
         [0033]    During a fourth operational state (phase 3), transfer pulses φ T1  and φ T2  are turned on and the signal charge stored on the photodiodes are transferred to the floating diffusion nodes ( 510 →FD 1 ,  511 →FD 2 ). As a result, the floating diffusion potential becomes V FD,i     —     3 =V FD,i     —     2 +V sig,i . These potentials again affect the floating gate potential through coupling capacitors  506  and  508 , and the resulting floating gate potential is shown in the fourth row of Table 1. This floating gate potential is sampled and held by pulsing the signal sampling pulse φ SHS . 
         [0034]    During a fifth operational state (phase 4), no change occurs from the state in phase 3. During the integration period, φ RS  is preferably set at high so that the floating diffusion nodes act as lateral overflow drains. Also, the pulse φ RFG  is set high with V RFG  being set below the threshold voltage of the source follower transistor  503 , so that a row select transistor, which is used in the 1 st  and 2 nd  embodiments, can be eliminated. 
         [0035]    The sample-and-hold pulses (φ SHR  and φ SHS ) sample the reset level (corresponds to V FG     —     2 ) and the signal level (corresponds to V FG     —     3  or V FG     —     4 ), respectively. The output voltage of the CDS circuit is given by: 
         [0000]        V   OUT     —     CDS ∝( V   FG     —     4   −V   FG     —     2 )=α· V   sig1   +β·V   sig2   (1) 
         [0000]    which calculates a weighted-sum operation, and where α and β are characterized by: 
         [0000]    
       
         
           
             
               
                 
                   α 
                   = 
                   
                     
                       C 
                       
                         C 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     
                       
                         C 
                         
                           C 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       + 
                       
                         
                           C 
                           
                             C 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                          
                         
                           C 
                           G 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   β 
                   = 
                   
                     
                       C 
                       
                         C 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     
                       
                         C 
                         
                           C 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       + 
                       
                         C 
                         
                           C 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       + 
                       
                         C 
                         G 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where capacitors C C1  and C C2  are illustrated as capacitors  506  and  508 , respectively and C G  is the parasitic capacitance between the floating gate (i.e., the node at which V FG  accumulates) and the substrate.
 
V sig1  and V sig2  are given by:
 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       sig 
                       , 
                       i 
                     
                   
                   = 
                   
                     
                        
                       · 
                       
                         N 
                         
                           sig 
                           , 
                           i 
                         
                       
                     
                     
                       C 
                       
                         FD 
                         , 
                         i 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Where i=(1,2) for pixel circuit  520  and  521  respectively, C FD,i  represent the capacitance of capacitors  507  or  509 , and N sig,i  represents the signal electrons accumulated on the pinned photodiode  510  or  511 . 
         [0036]    As is shown in Table 1, by employing proper timing, a correlated double sampling (CDS) sample and hold circuit  530  on a column line eliminates the kTC noise from transistors  500 ,  504  and  501 . In order to obtain the same saturation voltage, the photodiode size and the floating diffusion size can be set as 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       A 
                       
                         PPD 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     
                       C 
                       
                         FD 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                   = 
                   
                     
                       A 
                       
                         PPD 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     
                       C 
                       
                         FD 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where C FD1  and C FD2  represent the capacitance of the floating diffusion  510  and  511  and A PPD1  and A PPD2  are the light sensitive area of the photodiodes  510  and  511 . 
         [0037]    For example, assuming that C FD1 /C FD2 =4, A PPD1 /A PPD2 =4, T INT1 =16 ms and T INT2 =160 μs (see  FIG. 6 ), the ratio of sensitivities will be 100 (+40 dB). An example of the output transfer characteristic of the  FIG. 5  embodiment is illustrated in  FIG. 7 . When the relationship of equation (5) holds, the graph in  FIG. 7  discloses the correlation among signals V out , V sig1  and V sig2 , as described above. Since the floating gate node  560  can be set at a voltage below the threshold of the source follower transistor  503  during the integration period, a row select transistor can be removed from the circuitry ( FIG. 5 ). In the first and second embodiments, two sets of output images for a pixel are obtained for the two pixel pairs. In the embodiment in  FIGS. 5-6 , one output signal set V FG     —     4 , V FG     —     2  is obtained having reset components of both pixels (V FG     —     2 ) and pixel signal component of both pixels (V FG     —     4 ) with linearly kneed characteristics ( FIG. 7 ). 
         [0038]    When an on-chip microlens array as shown in  FIG. 8  is used, it is possible to further increase the dynamic range of an imager containing pixels constructed in accordance with the invention.  FIG. 8  provides an example of an on-chip microlens placement. Under the configuration shown, most of the incident light passing through the lens ( 801 ) array of a unit pixeL;  800  is focused onto PPD 1   802 , the photodiode having the longer integration time in each of the embodiments described above, while the remaining incident light is unfocused and passed to photodiode PPD 2   803 , having the shorter integration time. The increased effective area of PPD 1  (A PPD1 ) would further extend the dynamic range. 
         [0039]    A typical processor based system that includes a CMOS imager device according to the present invention is illustrated generally in  FIG. 9 . A processor based system is exemplary of a system having digital circuits that could include CMOS imager devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision system, vehicle navigation system, video telephone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention. 
         [0040]    A processor system, such as a computer system, for example generally comprises a central processing unit (CPU)  944  that communicates with an input/output (I/O) device  946  over a bus  952 . The CMOS imager  910  also communicates with the system over bus  952 . The computer system  900  also includes random access memory (RAM)  948 , and, in the case of a computer system may include peripheral devices such as a floppy disk drive  954  and a compact disk (CD) ROM drive  956  which also communicate with CPU  944  over the bus  952 . As described above, CMOS imager  910  is combined with a pipelined JPEG compression module in a single integrated circuit. 
         [0041]    As can be seen in the embodiments described herein, the present invention encompasses a unique two pixel structure that employs pinned photodiodes to provide extended dynamic ranges for imaging circuits. By using dual sensitivity and dual integration time techniques in the circuitry along with the pinned photodiodes, the dynamic range can effectively be extended without experiencing excessive noise. Accordingly, image sensors employing this circuit and method can detect a wider range of illuminations and consequently produce images of greater detail and quality. 
         [0042]    It should again be noted that although the invention has been described with specific reference to CMOS imaging devices, the invention has broader applicability and may be used in any imaging apparatus. The above description and drawings illustrate preferred embodiments of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention that comes within the spirit and scope of the following claims should be considered part of the present invention.