Abstract:
Image sensor devices are provided having reduced dark current generation characteristics. These image sensor devices include a semiconductor substrate and a photo-detector therein (e.g., P-N photodiode). The photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers. A first transistor, which has a terminal configured to receive the charge carriers generated by the photo-detector, is also provided. The first transistor includes a first gate electrode and a first pair of lightly doped source and drain regions of unequal width on opposite sides of the first gate electrode. This first transistor may be a three-terminal device and the terminal that is configured to receive the charge carriers may be selected from a group consisting of a gate, source and drain terminals. In particular, the first transistor may be configured as a reset transistor or as a source-follower transistor.

Description:
REFERENCE TO PRIORITY APPLICATION  
       [0001]     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application 2005-63392, filed Jul. 13, 2005, the entire contents of which are hereby incorporated herein by reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to image sensors and methods of fabricating the same and, more particularly, to CMOS image sensors and methods of fabricating the same.  
       BACKGROUND OF THE INVENTION  
       [0003]     Image sensors are devices that can transform optical images into electrical signals. Image sensors are typically classified into charge-coupled devices (CCD) and CMOS image sensors. The CCD has a plurality of MOS capacitors and operates by moving charges that are generated by optical light. The CMOS image sensor includes a plurality of unit pixels and a CMOS circuit controlling output signals from each unit pixel.  
         [0004]     The CCD has several disadvantages such as requiring relatively complicated operation and manufacturing processes, consuming relatively large amounts of power, and being difficult in integrating a signal processing circuit on a CCD chip. A CMOS image sensor, however, can be more easily fabricated because CMOS image sensors can be manufactured using conventional CMOS technology.  
         [0005]     Conventional CMOS image sensors may be degraded because of reductions in charge transmission efficiency and reductions in charge storage capacity due to noise or dark currents. Dark currents, which result from the accumulation of charges without optical incidence from photo-detecting devices, have been treated as being generated from silicon dangling bonds or defects on silicon substrate surfaces; however, hot carriers may also be a major factor in generating dark currents.  
         [0006]     As described in an article by C. C. Wang et al., entitled “The Effect of Hot Carriers on the Operation of CMOS Active Pixel Sensors,” IEDM Tech. Dig., 2001, pp. 563-566, hot carriers arising from transistors within the active pixel sensor, specifically, from pinch-off regions of source follower transistors, can raise a substrate potential and make drain-to-source currents (Ids) of the transistors higher. As these currents are increased, the hot carriers are further generated to thereby increase the dark current and degrade image quality effect.  
       SUMMARY OF THE INVENTION  
       [0007]     Embodiments of the present invention include image sensor devices having reduced dark current generation characteristics. These image sensor devices include a semiconductor substrate and a photo-detector therein. The photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers. A first transistor, which has a terminal configured to receive the charge carriers generated by the photo-detector, is also provided. The first transistor includes a first gate electrode and a first pair of lightly doped source and drain regions of unequal width on opposite sides of the first gate electrode. This first transistor may be a three-terminal device and the terminal that is configured to receive the charge carriers may be selected from a group consisting of a gate, source and drain terminals. In particular, the first transistor may be configured as a reset transistor or as a source-follower transistor. In the event the first transistor is a reset transistor, then the first transistor may have a first lightly doped drain region and a first lightly doped source region that is narrower than the first lightly doped drain region. This first lightly doped drain region may be electrically coupled to a power supply terminal (e.g., Vdd) of the image sensor device. A source-follower transistor may be configured to have a second lightly doped drain region and a second lightly doped source region that is narrower than the second lightly doped drain region. A transfer transistor may also be provided having a first source/drain region electrically connected to the charge generating region and a second source/drain region electrically connected to a floating diffusion region (FDR) extending in the semiconductor substrate.  
         [0008]     Additional embodiments of the invention include methods of forming the image sensor devices described herein. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0009]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the invention and, together with the description, serve to explain principles of the present invention. In the figures:  
         [0010]      FIG. 1  is an equivalent circuit view of a conventional unit pixel for an image sensor;  
         [0011]      FIG. 2  is a layout view of the unit pixel shown in  FIG. 1 ;  
         [0012]      FIGS. 3 through 9  are cross-sectional views of intermediate structures that illustrate methods of fabricating an image sensor in accordance with a first embodiment of the invention; and  
         [0013]      FIGS. 10-11  are cross-sectional views of intermediate structures that illustrate methods of fabricating an image sensor in accordance with a second embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0014]     Exemplary embodiments of the present invention will now be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.  
         [0015]     Exemplary embodiments of the present invention are relevant to image sensors such as CCD devices and CMOS image sensors, especially to CMOS image sensors and methods of fabricating the same. A unit pixel of the CMOS image sensor may comprise a photo-detector element and transistors for transferring and outputting charges generated in the photo-detector element. The unit pixel of the CMOS image sensor may include various numbers of the transistor. For example, the unit pixel of the CMOS image sensor may be configured to include one, three, four, five, or six transistors, for example. For purposes of discussion herein, a CMOS image sensor with a unit pixel having four transistors will be described. However, the invention is not limited to only the embodiments described herein, but may be applicable to various configurations of CMOS image sensors with pixels each having one, three, five, or six transistors, and so forth. Further, the invention is also applicable to other types of CMOS image sensors having a unit pixel that includes a photo-detector element and transistors.  
         [0016]      FIG. 1  is an equivalent circuit of a unit pixel for an image sensor of exemplary embodiments of the present invention. Referring to  FIG. 1 , the unit pixel  100  includes a photodiode PD, and four transistors. These transistors include a transfer transistor Tx, a reset transistor Rx, a source-follower transistor Dx, and a selection transistor Sx. The unit pixel  100  further includes a floating diffusion region FD at a side of the transfer transistor Tx.  
         [0017]      FIG. 2  is a layout view of transistors defining a unit pixel having the electrical configuration shown in  FIG. 1 . Referring to  FIG. 2 , a substrate  200  includes a first active pattern, where the photodiode PD is defined by a field oxide film, and a second active pattern where the transistors are formed. In the second active pattern, there are arranged a transfer gate  230 , a reset gate  250 , a source-follower gate  260 , and a selection gate  270 . In the second active pattern between the gates, impurity diffusion regions  240 ,  255 ,  265 ,  275  are formed. The impurity diffusion region  240  between the transfer gate  230  (Tg) and the reset gate  250  (Rg) serves as a floating diffusion region  240  (FD). Respective gate and impurity diffusion regions on both sides of the respective gate form a transistor. An impurity diffusion region can serve as a source region or drain region depending on a voltage applied thereto. Usually, in an N-channel transistor, the impurity diffusion region to which a higher voltage is applied functions as a drain region and the impurity diffusion region to which a lower voltage (e.g., ground voltage) is applied functions as a source region. Thus, the impurity diffusion region between the source-follower gate  260  (Dg) and the selection gate  270  (Sg) may act as a drain or source depending on a voltage applied thereto. The floating diffusion region  240  is electrically connected to the source-follower gate  260  of the source-follower transistor Dx by way of local interconnection, as illustrated by  FIG. 1 .  
         [0018]     An operation of the CMOS image sensor will now be described with reference to  FIGS. 1 and 2 . When a gate-on voltage is applied to the reset gate  250 , the reset transistor Rx is turned on to initialize the floating diffusion region  240 . And, a gate-on voltage is applied to the transfer gate  230  to turn the transfer transistor Tx on, so that signal charges generated by external light incident in the photodiode element PD are transferred to the floating diffusion region  240 . Accordingly, a voltage corresponding to charges transferred to the floating diffusion region  240  is applied to the source-follower gate  260  of the source-follower transistor Dx. When an external voltage Vdd is applied to the drain  255  of the source-follower transistor Dx, a potential value by a voltage of the source-follower gate  260  is amplified and transferred to the source  265  of the source-follower transistor Dx. Thus, in selecting and driving a pixel, the gate-on voltage applied to the selection gate  270  turns the selection transistor Sx on and thereby the signal charges transferred to the source  265  of the source-follower transistor Dx are output through the drain  275  of the selection transistor Sx.  
         [0019]      FIGS. 3 through 8  are sectional views illustrating processing features for fabricating an image sensor in accordance with a first embodiment of the invention, taken along with the line A-A′ of  FIG. 2 . Referring to  FIG. 3 , a semiconductor substrate  200  is provided. A shallow trench isolation (STI) process is carried out to form a field oxide film  210  in the semiconductor substrate  200  and define active patterns  200 A and  200 B in which the photo-detective element and transistors are to be formed. The active pattern  200 A is provided for the photodiode PD as a photo-detective element, while the active pattern  200 B is provided for the transistors. After forming a gate insulation film  220  on the active pattern  200 B of the substrate  200  and forming a conductive film thereon, a patterning process is carried out to form the gate patterns  230 ,  250 ,  260 , and  270 . These gate patterns include the transfer gate Tg, the reset gate kg, the source-follower gate Dg, and the selection gate Sg.  
         [0020]     Referring to  FIG. 4 , a first ion-implantation mask  300  is arranged to form the photodiode  320  and a hole accumulation diode (HAD) region  340  in the active region  200 A. The first ion-implantation mask  300  is formed to expose the active pattern  200 A where the photodiode PD is to be formed, and block the active pattern  200 B where the transistors are to be formed. The first ion-implantation mask  300  may be formed of a photoresist film. For example, the first ion-implantation mask  300  is patterned to expose regions for the photodiode  320  and a part of the transfer gate  230 , adjacent to the regions for the photodiode  320 . Ion impurities  310 , such as phosphorous (P) or arsenic (As), are then implanted into the active pattern  200 A of the semiconductor substrate  200 , to thereby form the photodiode  320  with N-type conductive layer extending to a predetermined depth. Ion impurities  330 , such as boron (B) or boron fluoride (BF 2 ), are implanted into the surface of the photodiode  320  to thereby form the HAD region  340  with P-type conductivity. As illustrated, one implant mask  300  may be used to guide both N-type and P-type implantation steps.  
         [0021]     Referring to  FIG. 5 , a second ion-implantation mask  400  is then defined. This second mask  400  covers the active pattern  200 A, including the photodiode  320 , but exposes the active pattern  200 B where the transistors are to be formed. For instance, the second ion-implantation mask  400  is formed to cover the photodiode  320  and a part of the transfer gate  230  adjacent to the photodiode  320 . The second ion-implantation mask  400  may be made of a photoresist film. The lightly doped regions,  420   tr ,  420   rd ,  420   ds , and  420   so , are formed in the active pattern  200 B by injecting ion impurities  410  with phosphorous (P) or arsenic (As), at a dose in a range between about 1×10 13  atoms/cm 2  and about 5×10 4  atoms/cm 2 . [Please confirm units]. The lightly doped regions,  420   tr ,  420   rd ,  420   ds , and  420   so , are formed in the active pattern  200 B and are self-aligned to the gate patterns  230 ,  250 ,  260 , and  270 , respectively.  
         [0022]     Referring to  FIG. 6 , a silicon nitride film (not shown) is formed over the semiconductor substrate  200  and then etched away to form spacers,  500   t ,  500   r   1 ,  500   r   2 ,  500   d   1 ,  500   d   2 ,  500   s   1 , and  500   s   2 , at both sidewalls of the gate patterns. During this step, a blocking layer  510  is formed that covers the photodiode  320  and partially covers the transfer gate  230 . This blocking layer  510  inhibits contamination (e.g., impurity/dopant contamination) of the photodiode  320 / 340  while the spacers are being formed.  
         [0023]     Referring to  FIG. 7 , third ion-implantation masks,  600 A,  600 B, and  600 C, are arranged to enable formation of heavily doped regions. The third ion-implantation mask  600 A covers the photodiode  320 . In order to define asymmetrical lightly doped regions at both sidewalls of the source-follower gate (Dg)  260  (i.e., lightly doped regions of a different width), the third ion-implantation masks  600 B and  600 C are formed on the source-follower gate  260  and/or on the reset gate (Rg)  250 , such that the third ion-implantation masks,  600 B and  600 C, are formed to partially cover the lightly doped region  420   rd   2  adjacent to the source-follower gate (Dg)  260 , or the lightly doped region  420   rd   1  adjacent to the reset gate (Rg)  250 , or both the lightly doped regions  420   rd   1  and  420   rd   2 . For instance, the third ion-implantation mask  600 A is formed on the photodiode  320  and a part of the transfer gate  230 . The third ion-implantation mask  600 C is arranged to cover the spacer  500   d   1  at the sidewall of the source-follower gate  260  and partially the semiconductor substrate  200  adjacent to the spacer  500   d   1 . Here, it is preferred to further form the third ion-implantation mask  600 C on a part of the source-follower gate  260 . The third ion-implantation mask  600 B is arranged to cover the spacer  500   r   2  at the sidewall of the reset gate  250  and partially the semiconductor substrate  200  adjacent to the spacer  500   r   2 . Here, it is preferred to further form the third ion-implantation mask  600 B on a part of the reset gate  250 .  
         [0024]     Ion impurities  610  of phosphorous (P) or arsenic (As) are implanted into the substrate  200  using the third ion-implantation masks  600 A,  600 B, and  600 C as an implant mask at 1×10 15  atoms/cm 2  and 9×10 5  atoms/cm 2 , to thereby form the heavily doped regions  620 TR,  620 RD,  620 DS, and  620 SO of N-type conductive layers. These heavily doped regions are self-aligned to the gate spacers  500   t ,  500   r   1 ,  500   d   2 ,  500   s   1 , and  500   s   2 , or the third ion-implantation masks  600 B and  600 C. For example the heavily doped region  6201 D between the source-follower gate  260  and the reset gate  250  is spaced from the spacers  500   r   2  and  500   d   1 , while the other heavily doped regions,  620 TR,  620 DS, and  620 SO, are self-aligned to their corresponding spacers. The lightly doped regions,  420   tr ,  420   rd ,  420   ds , and  420   so , are each divided into two parts,  420   tr   1 / 420   tr   2 ,  420   rd   1 / 420   rd   2 ,  420   ds   1 / 420   ds   2 ,  420   so   1 / 420   so   2 , by the heavily doped regions  620 TR,  620 RD,  620 DS, and  620 SO, respectively.  
         [0025]     The third ion-implantation masks  600 B and  600 C make the lightly doped regions  420   rd   2  and  420   ds   1  different from each other in width at both sides of the source-follower gate (Dg)  260 . The width X 1  of the lightly doped region  420   rd   2  is larger than the width X 2  of the lightly doped region  420   ds   1 . As also, the lightly doped regions  420   tr   2  and  420   rd   1  are different from each other in width at both sides of the reset gate (Rg)  250 . The width X 3  of the lightly doped region  420   rd   1  is larger than the width X 4  of the lightly doped region  420   tr   2 .  
         [0026]     Referring to  FIG. 8 , after depositing an interlevel insulation film  720  on the overall structure, processing steps are carried out to form contact holes, deposit a metallic film, and pattern the metallic film. Thus, metallic interconnections  740 ,  742 ,  744 ,  746 , and  748  are formed thereon. The metallic interconnection  740  is electrically connected to the transfer gate  230  and the metallic interconnection  742  connects the floating diffusion region  620 TR electrically with the source-follower gate  260 . The metallic interconnection  744  is electrically connected to the heavily doped region  620 RD between the reset and source-follower gates  250  and  260 , while the metallic interconnection  746  is electrically connected to the selection gate  270 . The metallic interconnection  748  is electrically connected with the heavily doped region  620 SO at the side of the selection gate  270 . These metallic interconnections may be formed using the same processing steps or they may be independently formed using separate processing steps.  
         [0027]      FIG. 9  is a sectional view illustrating the image sensor in accordance with the first embodiment of the invention. Referring to  FIG. 9 , the field oxide film  210  is formed to define the active regions in the semiconductor substrate  200  including an active pixel sensor block (not shown) and peripheral circuit field (not shown). The photodiode region  320  is formed at the side of the field oxide film  210 . The photodiode region  320  is made of an N-type conductive layer with ion impurities of phosphorous (P) or arsenic (As). In addition, the HAD region  340  is further formed on the photodiode region  320  at the surface of the semiconductor substrate  200  to thereby form a P-N junction (i.e., diode with the photodiode region  320 ). The HAD region  340  is a P-type conductive layer with ion impurities of boron (B) or boron fluoride (BF 2 ). The spacers  500  are formed at the sides of the gate patterns (i.e., the transfer gate  230 , the reset gate  250 , the source-follower gate  260 , and the selection gate  270 ).  
         [0028]     On the surface of the photodiode region  320  and a part of the transfer gate  230 , the blocking layer  510  is formed to prevent the photodiode region  320  from defects due to penetration of metallic ions therein. Here, it is preferred for the blocking layer  510  be formed of silicon nitride at the same time with the spacers  500 .  
         [0029]     Improved layout efficiency can be achieved by configuring the transistors with shared source and drain regions. As an example, the active region  700  between the transfer gate Tg and the reset gate Rg is provided both for a drain region of the transfer transistor Tx (i.e., the floating diffusion region) and a source region of the reset transistor Rx. Namely, the source region of the reset transistor Rx and the drain region of the transfer gate Tg share the same region. The active region  710  between the reset gate Rg and the source-follower gate Dg is shared by drain regions of the reset transistor Rx and the source-follower transistor Dx. As also, the active region  720  between the source-follower gate Dg and the selection gate Sg is shared by a source region of the source-follower transistor Dx and a drain region of the selection transistor Sx.  
         [0030]     Referring to  FIG. 9 , at least in one or more transistors, the lightly doped region of the drain region is different from the lightly doped region of the source region in width. In detail, at least in one or more transistors, the lightly doped region of the drain region is larger than the lightly doped region of the source region in width. For example, the lightly doped region  710   c  of the drain region  710  in the source-follower transistor Dx is larger than the lightly doped region  720   a  of the source region  720  in width. And, the lightly doped region  710   a  of the drain region  710  in the reset transistor Rx is larger than the lightly doped region  700   c  of the source region  700  in width.  
         [0031]     As previously mentioned with reference to  FIG. 7 , since the heavily doped region  710   b  of the common drain region  710  in the source-follower and reset transistors Dx and Rx is formed in a self-aligned manner to the spacers  500   d   1  and  500   r   1  (by the arrangement of the third ion-implantation masks  600 B and  600 C), the lightly doped regions  710   a  and  710   c  of the drain region  710  are larger than the lightly doped regions  700   c  and  700   a  of the source regions  700  and  720  in width.  
         [0032]      FIG. 10  is a sectional view illustrating processing features for fabricating an image sensor in accordance with a second embodiment of the invention, taken along the line A-A′ of  FIG. 2  with the exception of the third ion-implantation masks for the heavily doped regions, the processing features of this embodiment are similar to the first embodiment so the same reference numerals are used for the same elements without further detailed description of them. Referring to  FIG. 10 , third ion-implantation masks  800 A and  800 B are arranged to form heavily doped regions. The third ion-implantation mask  800 A covers the photodiode region  320 . For the purpose of defining asymmetrical lightly doped regions at both sidewalls of the source-follower gate (Dg)  260  (i.e., lightly doped regions of a different width), the third ion-implantation mask  500 B is formed, such that the third ion implantation mask  500 B is formed on a part of the lightly doped region adjacent to the source-follower gate  260 . In particular, the third ion-implantation mask  500 A is formed on the photodiode region  320  and a part of the transfer gate  230 . The third ion-implantation mask  800 B is arranged to cover the spacer  500   d   1  at the sidewall of the source-follower gate  260  and partially the semiconductor substrate  200  adjacent to the spacer  500   d   1 . Here, it is preferred to further form the third ion-implantation mask  800 B on a part of the source-follower gate  260 .  
         [0033]     Ion impurities  810  of phosphorous (P) or arsenic (As) are implanted into the substrate  200  under the third ion-implantation masks  800 A and  800 B at a dose level in a range between about 1×10 15  atoms/cm 2  and about 9×10 15  atoms/cm 2 , to thereby form the heavily doped regions  820 TR,  820 RD,  820 DS, and  820 SO of N-type conductive layers. These heavily doped regions are self-aligned to the gate spacers  500   t ,  500   r   1 ,  500   r   2 ,  500   d   2 ,  500   s   1 , and  500   s   2 , or the third ion-implantation mask  800 B. For example, the heavily doped region  8201 D outside of the source-follower gate  260  is spaced from the spacer  500   d   1 , but the other heavily doped regions,  820 TR,  820 DS, and  820 SO, are self-aligned to their corresponding spacers. The lightly doped regions,  420   tr ,  420   rd ,  420   ds , and  420   so , are each divided into two parts,  420   tr   1 / 420   tr   2 ,  420   rd   1 / 420   rd   2 ,  420   ds   1 / 420   ds   2 ,  420   so   1 / 420   so   2 , by the heavily doped regions  820 TR,  8201 D,  820 DS, and  820 SO. In addition, the third ion-implantation mask  800 B makes the lightly doped regions  420   rd   2  and  420   ds   1  different from each other in width at both sides of the source-follower gate (Dg)  260 . The width X 1  of the lightly doped region  420   rd   2  is larger than the width X 2  of the lightly doped region  420   ds   1 .  
         [0034]      FIG. 11  is a sectional view illustrating the image sensor in accordance with the second embodiment of the invention. Referring to  FIG. 11 , at least in one or more transistors, the lightly doped region of the drain region is different from the lightly doped region of the source region in width. In detail, at least in one or more transistors, the lightly doped region of the drain region is larger than the lightly doped region of the source region in width. For example, the lightly doped region  910   c  of the drain region  910  in the source-follower transistor Dx is larger than the lightly doped region  920   a  of the source region  920  in width.  
         [0035]     As aforementioned with reference to  FIG. 10 , since the heavily doped region  910   b  of the drain region  910  in the source-follower transistor Dx is formed apart from the spacer  500   d   1  by the arrangement of the third ion-implantation mask  800 B, the lightly doped region  910   c  of the drain region  910  is larger than the lightly doped region  700   a  of the source region  920  in width. This asymmetric drain and source width configuration improves dark current generation. Further, in the structure with the transistors, it is preferred that the heavily doped region  920   b  of the source region  920  is self-aligned to the spacer, while the heavily doped region  910   b  of the drain region  910  is disposed apart from the spacer.  
         [0036]     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.