Abstract:
The invention provides a parametric EDA function tool and a method of simplifying EDA programming language, characterized by using an EDA language unit to convert the programming language into a parametric EDA language mode having format strings and variable length arguments; using a function formation unit to form EDA function codes from the parametric EDA language; and using an executive file generator to compile the EDA function codes into an executive file to be executed by a verification device, thereby overcoming the drawbacks of having vast and inflexible EDA programming language that occupies large memory spaces and thus the increased costs for verification as encountered in prior techniques.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to parametric EDA function tools and methods of simplifying EDA programming language, and more particularly to an EDA function tool and a method of simplifying EDA programming language that convert the programming language into a parametric EDA language mode through format strings and variable length arguments. 
         [0003]    2. Description of Related Art 
         [0004]    At present, automatic symbolic verification technologies play a key role in the software engineering and chip design area. For example, designers often use EDA (Electronic Design Automation) software tools to speed up design processes. They can use EDA tools to simulate chip designs, build up product models or design operation processes prior to prototyping or production. Design using EDA software tools generally involves an iterative process through which problems or defects can be found and overcome. 
         [0005]    The design concept of EDA software tools is to use data structures to express mathematic or logic conditions. In recent years, a large number of libraries have been developed. However, during the use of these libraries, if a condition needs to be built up according to an execution state of a program, a complicated conditional expression needs to be established from the most basic logic atom level by induction, thereby leading to vast programming language that occupies large memory spaces and consumes a lot of development time, and leads to an increased verification cost of EDA models. 
         [0006]    Therefore, that is a need to provide a parametric EDA function tool and a method of simplifying EDA programming language so as to simplify the content of EDA programming language, thereby decreasing the verification cost of EDA models. 
       SUMMARY OF THE INVENTION 
       [0007]    According to the above drawbacks, the present invention is to provide a parametric EDA function tool and a method of simplifying EDA programming language so as to simplify the content of EDA programming language and thereby reduce the verification cost of EDA models. 
         [0008]    The present invention provides a parametric EDA function tool and a method of simplifying EDA programming language. The parametric EDA function tool comprises: an EDA function code generator for converting the programming language into EDA function codes; and an executive file generator for compiling the EDA function codes into an executive file to be executed by a verification device, wherein the EDA function code generator comprises: an EDA language unit for converting the programming language into a parametric EDA language mode having format strings and variable length arguments; and a function formation unit for forming the EDA function codes from the parametric EDA language. 
         [0009]    The method of simplifying EDA programming language of the present invention comprises the following steps: (1) converting the programming language into a parametric EDA language mode having format strings and variable length arguments; (2) forming EDA function codes from the parametric EDA language; and (3) compiling the EDA function codes into an executive file. 
         [0010]    In a preferred embodiment, step (1) further comprises: (1-1) converting the programming language into at least a conditional format string; (1-2) establishing a positional parameter and a variable length argument corresponding to the conditional format string; and (1-3) substituting the positional parameter and variable length argument into the conditional format string so as to form the parametric EDA language mode. 
         [0011]    In another preferred embodiment, the method of simplifying EDA programming language further comprises step (4) of loading the executive file into a memory of a verification device and executing the executive file. 
         [0012]    Compared with the prior art, the present invention converts the programming language into a parametric EDA language mode having format strings and variable length arguments so as to simplify the programming language, thereby saving memory spaces and reducing the development time, and reducing the cost for building up and verifying EDA models. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0013]      FIG. 1  is a diagram showing a parametric function tool according to the present invention; 
           [0014]      FIG. 2  is an application diagram of the parametric function tool according to a preferred embodiment of the present invention; 
           [0015]      FIG. 3  is a flow diagram showing a method of simplifying EDA programming language according to the present invention; and 
           [0016]      FIG. 4  is a flow diagram showing a method of simplifying EDA programming language according to a preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0017]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. 
         [0018]      FIG. 1  is a diagram showing a parametric EDA function tool according to the present invention. As shown in the drawing, the parametric EDA function tool  1  comprises an EDA function code generator  10  and an executive file generator  11 , wherein the EDA function code generator  10  further comprises an EDA language unit  101  and a function formation unit  102 . 
         [0019]    The EDA function code generator  10  is used for converting programming language into EDA function codes. In order to facilitate the development and maintenance of symbolic verification applications, the EDA function code generator  10  converts the EDA programming language into EDA function codes, thereby building up simplified program contents. 
         [0020]    The EDA language unit  101  is used for converting the programming language into a parametric EDA language mode having format strings and variable length arguments. The EDA language unit  101  uses the concept of printf( ) in C language to create a flexible and parametric programming interface. By setting and converting the programming language through format strings and variable length arguments, a parametric EDA language mode is formed to simplify programming codes. 
         [0021]    In a preferred embodiment, the EDA language unit  101  is applied to a programming interface for variable declaration, temporal logic formula declaration and game role declaration. 
         [0022]    In another preferred embodiment, the EDA language unit  101  is used for designing a declaration program of a mode, a state, a control point or a rule of a state transition system. 
         [0023]    The function formation unit  102  is used for forming EDA function codes from the parametric EDA language so as to facilitate subsequent compiling. 
         [0024]    The executive file generator  11  is used for compiling the EDA function codes into an executive file, which is then executed by a verification device, wherein the executive file generator  11  may be an assembler, a compiler and/or an interpreter. The verification device may be a software/hardware test case generator, a software/hardware test scheme generator, a software/hardware model checker or a software/hardware simulator. 
         [0025]    In practice, the EDA language unit  101  converts the programming language into a parametric EDA language mode having format strings and variable length arguments; then, the function formation unit  102  forms EDA function codes from the parametric EDA language; and finally, the executive file generator  11  compiles the EDA function codes into an executive file. For example, supposed a parameter i and variables m, x0, x1, . . . , xi, for a condition            jε[1,i] (m=j         0≦xj≦j), since each basic logic atom varies with the value of variable j, it is difficult to express the condition through simplified programming codes by using the traditional library programs. But through the parametric EDA function tool  1  of the present invention, the condition can be expressed using following function codes: 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for(j=1;j&lt;=i;j++) 
               
               
                   
                 red_declare_variable(“x%d”,j); 
               
               
                   
                 c=red_false( ); 
               
               
                   
                 for(j=1;j&lt;=i;j++){ 
               
               
                   
                 c=red_or(c,red_diagram( 
               
               
                   
                 “m=%d&amp;&amp;0&lt;=x%d&amp;&amp;x%d&lt;=%1d”, j,j,j,j)); 
               
               
                   
                 } 
               
               
                   
                   
               
             
          
         
       
     
         [0026]    In the above codes, firstly, i variables x1, x2, . . . , xi are declared. Then, red_false( ) sends back a logic false conditional expression and stores it in variable c. Subsequently, red_or( ) is executed repeatedly to perform an OR operation between the conditional expression in variable c and the conditional expression of red_diagram( ) and further stores the result of the OR operation in variable c. Therefore, through the parametric EDA function tool  1 , simple programming codes that are easy to read and easy to maintain can be formed. 
         [0027]      FIG. 2  is an application diagram of the parametric EDA function tool according to the present invention. As shown in the drawing, the whole structure comprises: programming language  20 , a parametric EDA function tool  21  of the present invention, an EDA model verification executive file  22 , a verification device  23  and a memory  231 . 
         [0028]    In practice, through the parametric EDA function tool  21 , the EDA programming language  20  is converted into an EDA model verification executive file  22 , which is stored in the memory  231  of the verification device  23  such that it can be executed by the verification device  23 . 
         [0029]    In a preferred embodiment, the programming language can be programming codes for establishing an EDA model, an EDA object and/or an EDA operation process. 
         [0030]      FIG. 3  is a flow diagram showing a method of simplifying the EDA programming language. As shown in the drawing, the method comprises the following steps. 
         [0031]    First, at step S 30 , the programming language is converted into a parametric EDA language mode having format strings and variable length arguments. Then, the process goes to step S 31 . 
         [0032]    At step S 31 , EDA function codes are formed from the parametric EDA language. Then, the process goes to step S 32 . 
         [0033]    At step S 32 , the EDA function codes are compiled into an executive file. 
         [0034]    In a preferred embodiment, step S 32  further comprises: compiling the EDA function codes into an object file, and linking the object file into an executive file by an executive file generator. 
         [0035]    In another preferred embodiment, the method of the present invention further comprises the step of loading the executive file by a verification device into a memory thereof and executing the executive file. 
         [0036]      FIG. 4  is a flow diagram showing a method of simplifying the EDA programming language according to a preferred embodiment of the present invention. As shown in the drawing, the method comprises the following steps. 
         [0037]    First, at step S 40 , the programming language is converted into at least a conditional format string. Then, the process goes to step S 41 . 
         [0038]    At step S 41 , a position parameter and a variable length argument are established corresponding to the conditional format string. Then, the process goes to step S 42 . 
         [0039]    At step S 42 , the positional parameter and the variable length argument are substituted into the conditional format string so as to form a parametric EDA language mode. Then, the process goes to step S 43 . 
         [0040]    At step S 43 , EDA function codes are formed from the parametric EDA language. Then, the process goes to step S 44 . 
         [0041]    At step S 44 , the EDA function codes are compiled into an executive file. Then, the process goes to step S 45 . 
         [0042]    At step S 45 , a verification device loads the executive file into a memory thereof and executes the executive file. 
         [0043]    In a preferred embodiment, in order to declare five variables x1, x2, x3, x4 and x5, the following programming codes are generated according to steps S 40  to S 42 . 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for(i=1;i&lt;=5;i++) 
               
               
                   
                 red_declare_variable(“x%1d”,i); 
               
               
                   
                   
               
             
          
         
       
     
         [0044]    wherein red_declare_variable( ) can also accept a variable argument in the style of printf( ). 
         [0045]    In another preferred embodiment, the above-described concept can be used to design a declaration program of a mode, a state, a control point or a rule of a state transition system. For example, to declare three system modes ma, mb and mc, wherein the state conditions are x3≦1, x2≦2 and x1≦3, respectively, the following programming codes can be generated. First, the following programming codes are established: 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 for(i=1;i&lt;=3;i++) 
               
               
                   
                 red_declare_mode( ); 
               
               
                   
                   
               
             
          
         
       
     
         [0046]    which represents a conditional format string at step S 40 . 
         [0047]    Then, (“m % c”, “x % 1d&lt;=% 1d”, ‘a’+i−1,4−i,i) is established, which represents a positional parameter and a variable length argument at step S 41 . 
         [0048]    Finally, the above two parts are combined as 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                  for(i=1;i&lt;=3;i++) 
               
               
                   
                 red_declare_mode( 
               
               
                   
                 “m%c”, “x%1d&lt;=%1d”, `a`+i−1,4−i,i); 
               
               
                   
                   
               
             
          
         
       
     
         [0049]    which forms a parametric EDA language mode at step S 42 . 
         [0050]    Alternatively, the following programming codes can be established for declaring the three state transition rules. 
         [0000]    
       
         
               
               
             
           
               
                   
                   
               
             
             
               
                   
                  for(i=1;i&lt;=3;i++) 
               
               
                   
                  red_declare_transition(“x%1d&lt;=%1d”, 
               
               
                   
                 “x%1d=0;”,4−i,i,i); 
               
               
                   
                   
               
             
          
         
       
     
         [0051]    wherein the trigger or guard conditions are x3≦1, x2≦2 and x1≦3, and the statements or actions after trigger are “x1=0;”, “x2=0;”, and “x3=0;”, respectively. 
         [0052]    Therefore, the present invention builds up a flexible and parametric program interface and converts the programming language into a parametric EDA language mode having format strings and variable length arguments. Accordingly, complicated and huge EDA programming codes in the prior art at converted into symbolic verification application programs that are simple, easy to read and easy to maintain, thereby saving memory spaces occupied by the EDA programming codes, saving the development time, and reducing the development cost and the equipment cost. 
         [0053]    Therefore, the parametric EDA function tool and method of simplifying the EDA programming language according to the present invention achieve the following effects:
       (1) saving memory spaces occupied by EDA programming codes. When the programming language is converted into a parametric EDA language mode, the EDA programming codes are greatly reduced, thereby saving the memory spaces occupied by the EDA programming codes.   (2) reducing the development cost and equipment cost of manufacturers. Currently, manufacturers in information industries, software verification industries and embedded systems spend a lot of manpower and material resources on the development of EDA softwares. The parametric EDA function tool of the present invention is helpful to reduce the software development and maintenance time and relatively reduce the cost spent on EDA development tools, thereby reducing the development cost and equipment cost of manufacturers.       
 
         [0056]    The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.