Abstract:
A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a divisional of U.S. Ser. No. 10/880,048 filed Jun. 29, 2004, which is a divisional of U.S. Ser. No. 10/880,044 filed Jun. 29, 2004, which is a divisional of U.S. Ser. No. 10/651,277 filed Aug. 28, 2003, which is a divisional of Ser. No. 10/283,981 filed Oct. 30, 2002, now U.S. Pat. No. 6,649,478 which is a divisional of Ser. No. 08/962,322 filed Oct. 31, 1997, now U.S. Pat. No. 6,498,366 which is a divisional of Ser. No. 08/409,900 filed Mar. 22, 1995 now U.S. Pat. No. 5,689,130 which is a continuation of Ser. No. 07/953,766 filed Sep. 30, 1992, ABD, which is a divisional of Ser. No. 07/652,920 filed Feb. 8, 1991 now U.S. Pat. No. 5,242,862. This application claims the benefit of JPSN P2-33367, filed Feb. 14, 1990. The disclosure of the above applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to a semiconductor device which has a low ON-resistance, and further, to a method of manufacturing such a semiconductor device.  
         [0004]     2. Description of the Related Art  
         [0005]     Many kinds of methods of manufacturing for reducing an ON-resistance of a semiconductor device have been known. For example, Japanese Unexamined Patent Publication 1-169970 discloses a method which an N-type impurity layer is formed in a back surface of a drain substrate so as to reduce a contact resistance between the drain substrate and a drain electrode. Japanese Examined Patent Publication 58-45814 discloses a method of manufacturing the semiconductor device which has a good ohmic contact between the drain substrate and the drain electrode. The device has a multilayer metal electrode on a back surface of a drain substrate. The multilayer metal electrode consists of layers having a gold layer as a main layer.  
         [0006]     As shown in  FIG. 13 , the ON-resistance of a field effect transistor (FET) is represented by the following equation: 
 
 R   ON   =R 1 +R 2 +R 3+ R 4+ R 5+ R 6+ R 7+ R 8+ R 9+ R 10 
 
 wherein, R 1  denotes a contact resistance of a drain electrode  50 ; R 2  denotes a contact resistance between the drain electrode  50  and an N-Type impurity layer  52 ; R 3  denotes a resistance of N drain substrate  54 ; R 4 , R 5  and R 6  denote resistances of N drain region  56  respectively; R 7  denotes a resistance of P-Type diffusion region  58  for forming a channel; R 8  denotes a resistance of N-type source  60 ; R 9  denotes a contact resistance between the N-Type source  60  and a source electrode  62 ; and R 10  denotes a resistance of the source electrode  62 . 
 
         [0007]     However, such a conventional method of manufacturing the semiconductor device has many problems. For example, the method by which the N-Type impurity layer is formed is complex because an oxide film adhered to the back surface of the N drain substrate  54  and a diffusion layer having an opposite conductive type (P) to that of the N drain substrate  54  must be removed before the N-type impurity layer  52  is formed.  
         [0008]     A semiconductor device for household use is demanded with a withstanding voltage more than 100V, normally more than 200V. It is a necessary to make a resistance of a epitaxial layer (the N drain region  56 ) formed on the N drain substrate  54  high to get the withstanding voltage. Therefore, the ratio of the resistance of the N drain substrate  54  to the resistance of the epitaxial layer becomes small. On the contrary, a semiconductor device for a motor vehicle is demanded with a withstanding voltage of at most 50-60V. The resistance of the epitaxial layer is relatively low, and the ratio of the resistance of N drain substrate  54  to the resistance of the epitaxial layer becomes large. Therefore, in the semiconductor device for a motor vehicle, it is effective to reduce the resistance of the N drain substrate  54  for reducing the ON-resistance.  
         [0009]     The resistance R 3  of the N drain substrate  54  is represented by the following equation: 
 
 R 3=ρ N   ×t   n   /S  
 
 wherein, ρ N  denotes resistivity of the N drain substrate  54 ; t n  denotes a thickness of the N drain substrate  54 ; and S denotes a cross section of the N drain substrate  54 . It is necessary to reduce the thickness t n  of the N drain substrate  54  so as to reduce this resistance R 3 . However, the thickness t n  of the N drain substrate  54  for forming the N-Type impurity layer  52  is determined in accordance with a thickness of a silicon wafer. The reason is that the N drain substrate  54  is warped by heat generated in a step that the N-Type impurity layer  52  is formed when the thickness t n  of the N drain substrate  54  is too thin. To get a wafer of large diameter, the thickness t n  needs to be thick to keep the strength thereof. Therefore, the resistance R 3  of the N drain substrate  54  becomes high, and thus the ON-resistance also becomes high. 
 
         [0010]     The technique by which the concentration of antimony (Sb) as a impurity in the N drain substrate  54  is heightened and the resistivity is diminished, may be adopted so as to reduce the resistance R 3  of the N drain substrate  54 . However, it is impossible to make the resistance R 3  less than 0.01Ω·cm because of the limitation of the amount solution of Sb which can be in the solution.  
         [0011]     Moreover, since it is impossible to make the impurity concentration in the substrate high because of the limitation of solution, it is difficult to get a good ohmic contact between an N-type substrate and an electrode.  
         [0012]     On the other hand, in the method which utilizes gold as an electrode material, the barrier height of the gold for an P-type silicon substrate is 0.2 eV, and therefore so a good ohmic contact between those can be obtained. However, since the barrier height of the gold for an N-type silicon substrate is relatively high, 0.8 eV, the contact between those becomes a schottky contact and may have undesirable diode character.  
         [0013]     Moreover, when an overall thickness is thick, stress from a package and a step between a lead frame and the source electrode  62  becomes higher. Therefore, the wire bonding work becomes very difficult. Also, the cost of gold is very high.  
         [0014]     Techniques other than the aforementioned techniques have also been known. The technique which is disclosed in Japanese Unexamined Patent Publication 57-15420 suggests that a back surface of a silicon substrate is ground to improve adherence between the back surface and a collector electrode formed on the back surface. The technique which is disclosed in “IEEE ELECTRON DEVICE LETTERS, VOL. 10, NO. 3 MARCH 1989, P101-103” suggests that a 0.004Ω·cm arsenic-doped silicon substrate is used.  
       SUMMARY OF THE INVENTION  
       [0015]     An object of this invention is to reduce the ON-resistance of a semiconductor device.  
         [0016]     Another object of this invention is to get a good ohmic contact.  
         [0017]     A still further object of this invention is to provide a thin semiconductor device having the advantage of small stress from a package and easy wire bonding.  
         [0018]     To accomplish the above objects, a semiconductor device according to this invention includes an N-type semi-conductor substrate including arsenic as an impurity and having a ground surface formed on one surface thereof, said ground surface having concavo-convex irregularities, a first electrode formed on another surface other than said one surface of said N-type semiconductor substrate, a second electrode formed on said ground surface and ohmically contacted with said N-type semiconductor substrate through said ground surface, and a semiconductor element formed in said N-type semiconductor substrate and in which an electric current flows between said first electrode and said second electrode during an ON-state thereof.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]      FIG. 1  is a sectional view of a semiconductor device of this invention;  
         [0020]      FIG. 2A-2C  are sectional views showing the sequence of processes of the semiconductor device of this of this invention;  
         [0021]      FIG. 3  is a side view for explaining a surface grinding proceeding;  
         [0022]      FIG. 4  is a side view for explaining a lapping grinding proceeding;  
         [0023]      FIG. 5  shows a relationship between the thickness t and destructive strength;  
         [0024]      FIG. 6  is a sectional view for explaining a load test;  
         [0025]      FIG. 7  shows a relationship between the granularity of a grindstone and warp of the silicon substrate;  
         [0026]      FIG. 8  shows a relationship between the impurity concentration and the contact resistance;  
         [0027]      FIG. 9  shows a relationship between V  DS  and I DS  of power MOS FET;  
         [0028]      FIG. 10  shows a relationship between V  F  and the concentration of As in the silicon substrate;  
         [0029]      FIG. 11  shows a relationship between the concentration of As and the value of the leak current;  
         [0030]      FIG. 12  shows a relationship between the thickness t and shearing stress;  
         [0031]      FIG. 13  is a sectional view of a semiconductor device of the prior art;  
         [0032]      FIG. 14  shows a relationship between the granularity and surface roughness; and  
         [0033]      FIG. 15  shows a relationship between the granularity and an ON-resistance. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0034]     The preferred embodiments of this invention will be described with reference to the drawings. The embodiments are suitable for a semiconductor device for a motor vehicle.  
         [0035]      FIG. 1  shows an N-type drain region  2  formed on a silicon substrate  1  which is doped with As (arsenic) formed by crystallizing melted silicon that has As therein. A P-type region  4  is formed in the N-type drain region  2  for forming a channel. An N-type source region  6  is formed in the P-type region  4 . A polycrystalline silicon gate  10  is formed on the N-type drain region  2  and the P-type region  4  through an oxide film (SiO 2 )  8 . A source electrode  12  is formed on the oxide film  8  and electrically connected with the P-type region  4  and the N-type source region  6 . An ohmic electrode  26  is formed on a ground surface  22  which is formed on a back surface of the silicon substrate  1 .  
         [0036]     Here, the prior art used Sb (antimony) as an N-type impurity. However, the concentration of Sb could not be more than 5×10 18 cm −3  owing to its limitation of solution. The inventors have solved this problem by including As in the silicon substrate  1  as the N-type impurity. As has a higher limitation of solution than Sb and therefore solves this problem. The concentration of As is set within a range between 7×10 18  cm −3 −1×10 21  cm −3  Therefore, the contact resistance between the silicon substrate  1  and the ohmic electrode  26  can be reduced sufficient to avoid a schottky contact and get an ohmic contact. Since the concentration of As is more than 7×10 18  cm −3 , a good ohmic contact can be obtained for almost all electrode materials. Moreover, the resistivity of the silicon substrate  1  is also diminished because of the higher concentration of As included in the silicon substrate  1  as an impurity. Consequently, the resistance R 3  of the silicon substrate  1  is also reduced. The ground surface  22  has been ground to have a concavo-convex surface which has many coarse surface irregularities. Therefore, the ohmic electrode  26  can be firmly adhered to the ground surface  22  because the ground surface  22  has a suitable concavo-convex surface.  
         [0037]     The process of forming the aforementioned semiconductor device of the embodiment of this invention will now be described with reference to  FIG. 2A-2C .  FIG. 2A-2C  show the sequence of the process. A silicon crystal is formed by a CZ (Czochralski) method, where As is added as a dopant in a melted silicon. The silicon substrate  1  is formed by slicing the silicon crystal. Therefore the silicon substrate  1  has As a solid solution, the concentration of As being 7×10 18 −1×10 21  cm −3 , and resistivity of the silicon wafer is less than 0.008Ω·cm.  FIG. 2A  shows the N-type drain region  2  having P (phosphorus) as an impurity and being grown on a main surface of the silicon substrate  1  by an epitaxial growth method. The oxide film (SiO 2 )  8  is formed on a surface of the N-type drain region  2 . The polycrystalline silicon is deposited on the oxide film  8  by an LPCVD (low pressure chemical vapor deposition) technique. P (phosphorus) is introduced in the polycrystalline silicon, and the polycrystalline silicon is locally etched to form the polycrystalline silicon gate  10 . The polycrystalline silicon gate  10  is oxidized, and P-type impurities such as B (boron), Al (aluminium), Ga (gallium) or the like are diffused into the N-type drain region  2  by using this polycrystalline silicon gate  10  as a mask for forming the P-type region  4 . A portion of the P-type region  4  becomes a channel region. The N-type source region  6  is formed by locally diffusing N-type impurities such as As, P (phosphorus) or the like into the P-type region  4 . Windows are then opened in the oxide film  8  and Al—Si is deposited by a sputtering method for forming the source electrode  12 , so that the source electrode  12  is connected to both the P-type region  4  and the N-type source region  6 . Here, a device layer  14  consists of the P-type region  4 , the N-type source region  6 , the oxide film  8 , the polycrystalline silicon gate  10 , and the source electrode  12 . Moreover, a passivation film such as a plasma-SiN or the like may be formed on the source electrode  12  for stabilizing a surface of the device layer  14 .  
         [0038]     During this process, a by-product layer  16 , such as a polycrystalline silicon, a silicon oxide (SiO 2 ) or the like, is spontaneously formed on another (back) surface of the silicon substrate  1  while the aforementioned device is being manufactured. The another surface of the silicon substrate  1  on which the by-product layer  16  is formed thereon is ground by a surface grinding (SG) proceeding for removing the by-product layer  16 . The surface grinding is carried out by using a grindstone  18  as shown in  FIG. 3 . The granularity of the grindstone  18  is between No. 300-No. 500. In this embodiment, a surface of the device layer  14  is covered with a adhesive film (not shown) and the device layer  14  is fixed by a vacuum chuck  20 .  
         [0039]      FIG. 2B  shows the by-product layer  16  removed by the grinding, and a ground surface  22  being formed. In this condition, the thickness t from one surface of the device layer  14  to the another surface of the silicon substrate  1  is 200-450 μm. After grinding, the whole device is washed by super pure water.  
         [0040]     The silicon crystal of the another surface of the silicon substrate  1  is damaged by the grinding. This damage destroys some part of the crystalline structure of the silicon substrate, and should therefore be avoided. It also decreases the destruction strength. However, the depth of this damaged layer is only 1-2 μm if the surface grinding device of  FIG. 3  is used.  FIG. 5  shows a graph of depth of the damaged layer. Because the depth of the damaged layer is shallow, the destruction strength of this device is still between 1.0-1.6 kg.  FIG. 6  shows a load test where the destruction strength is defined as a maximum load when a chip destroyed. The load test is carried out in such a way that the center of the chip is supported at its both ends and has a load applied thereon by a load piece  24 .  
         [0041]     If the another surface of the silicon substrate  1  is ground by lapping grinding instead of surface grinding, the depth of the damaged layer is 6-7 μm, and the destruction strength of this device becomes 0.3-0.6 kg (shown in  FIG. 5 ).  FIG. 4  shows the lapping grinding is carried out in the condition which the device is fixed on upper surface plate  30  by paraffin glue and abrasives (a mix of abrasives No. 800 and No. 1200 of SiC) are supplied between the device and a lower surface plate  32 . As understood by comparing the two lines in  FIG. 5 , surface grinding will make the destruction strength stronger than lapping grinding.  
         [0042]      FIG. 7  shows that when the granularity of the grindstone  18  is No. 300-No. 500, the warping of the silicon substrate  1  can be reduced. If the granularity is finer than No. 500, however the warp becomes larger. If the granularity is coarser than No. 300, the possibility which of breaking of the silicon substrate  1  is increased.  
         [0043]     The reason why the warping is reduce is that the coarser the granularity is, the more stress in the silicon substrate is dispersed.  
         [0044]      FIG. 14  shows a relationship between the granularity of the grindstone  18  and surface roughness Ra. When the granularity is No. 320, the surface roughness Ra is in a range between 0.3-0.6 μm. When the granularity is No. 600, the surface roughness Ra is almost 0,2 μm. When the granularity is No. 4000, the surface roughness Ra becomes almost 0 μm. It is to be noted that surface roughness Ra of the silicon substrate  1  which is polished up is also almost 0 μm.  
         [0045]      FIG. 15  shows a relationship between the granularity of the grindstone  18  and an ON-resistance. As shown in  FIG. 15 , when the granularity is coarser, the ON-resistance becomes low. The reason is that when the granularity is coarser, barrier height of the ohmic electrode  26  for the silicon substrate  1  becomes high, and the contact resistance between the ohmic electrode  26  and the silicon substrate  1 . It is desirable that the granularity is a range between No. 320-No. 600 to reduce the ON-resistance.  
         [0046]      FIG. 2C  snows that after the spontaneously formed by product layer  16  (not shown) has been removed by a wet etching or an RF etching, and an ohmic electrode  26  is formed on the ground surface  22  by a sputtering method. The ohmic electrode  26  acts as a drain electrode. In this embodiment, the ohmic electrode  26  is a multilayer electrode consisting of Ti—Ni—Au layers. When electrode material, such as Ti (titanium), V (vanadium), Cr (chromium), Ni (nickel) or the like, is adopted, it is necessary to make an impurity concentration in the silicon substrate  1  more than 5×10 18  cm −3 , preferably, more than 7×10 18  cm −3  so as to make an ohmic contact with the electrode material. The barrier height Φ B  of the electrode material for silicon is 0.4-0.6 eV. As shown in  FIG. 8 , if the impurity concentration is more than 5×10 18 cm −3 , the contact resistance between the electrode material and the silicon substrate  1  begins to rapidly be reduced, and if the impurity concentration is more than 7×10 18 cm −3 , the contact resistance becomes less than 10 −3 Ω·cm 2 .  
         [0047]      FIG. 9  shows a relationship between V  DS  (voltage between the source and the drain) and I  DS  (current between the source and drain) of this power MOS FET. Voltage of the gate V  G  is a parameter shown in Figure as being used as an index so as to judge whether the contact is a schottky contact.  
         [0048]      FIG. 10  shows a relationship between this calculated V  F  and a concentration of As in the silicon substrate  1 . As shown in  FIG. 10 , when the concentration of As is more than 7×10 18  cm −3 , V  F  becomes substantially 0(zero) and the contact is an ohmic contact.  
         [0049]     The upper limitation of the concentration of As which is included in the silicon substrate  1  is its limitation of solution. This limitation is found by measuring the value of leakage current through the P-N junction.  
         [0050]      FIG. 11  shows a relationship between the concentration of As and the value of the leakage current through the P-N junction. Before the value of the leakage current is measured, to form P-N junction, a P-type impurity such as B(boron) or the like is diffused in an N-type silicon substrate including As as an impurity. When the concentration of As is higher than its limitation of solution, the crystallinity of silicon is disordered and leakage current flows through the P-N junction. Therefore, the concentration when the leakage current begins to flow is defined as the value of its limitation of solution. As shown in  FIG. 11 , the limitation of solution is 1×10 21  cm −3 .  
         [0051]     The chip which was manufactured by abovementioned manufacturing steps is molded by silicone resin, and an IC package is formed. In this molding step, because a thickness of the chip is thin, as shown in  FIG. 12 , the shearing stress becomes low. Consequently, the stress of the IC package is relaxed. Moreover, when a lead frame (not shown) is bonded to the source electrode  12  with a wire, the wire-bonding work becomes easy because the height of the lead frame and the source electrode  12  are similar and therefore these makes a low step.  
         [0052]     The present invention has been described with reference to the abovementioned embodiment, but the present invention is not limited to this embodiment and can be modified without departing from the spirit or concept of the present invention. For example, the present invention may be applied to an IGBT (Insulated Gate Bipolar Transistor), SIT (Static Induction Transistor), SI (State Induction) thyristor or the like other than the power MOSFET. These semiconductor elements flow current in a vertical direction (a direction of a thickness of a substrate) and an electrode formed on N-type silicon substrate.