Abstract:
Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to microcontrollers and in particular microcontrollers including peripherals. 
         [0003]    2. Description of the Related Art 
         [0004]    Microcontrollers generally include a central unit, memories including a volatile memory and a non-volatile memory, and several peripherals such as external bus controllers, timers, analog-digital converters, digital-analog converters, etc. 
         [0005]    Certain microcontrollers have an idle mode during which some of their circuits and particularly all or part of their peripherals are switched off for energy-saving purposes. Generally, the idle mode is left when an external event occurs, and such an exit should be as swift as possible, particularly to react within an acceptable response time to the external event. 
         [0006]    In general, microcontrollers execute an initialization procedure when switching on the microcontroller and when leaving the idle mode. This initialization procedure particularly enables state registers and registers for accessing the peripherals to be put into a predefined state. This initialization procedure is generally defined in the form of a sequence of instructions stored in a non-volatile program memory of the microcontroller and is executed by the central unit of the microcontroller. The initialization instruction sequence generally includes for each register to be initialized, an instruction for reading an initialization value in the non-volatile memory and an instruction for writing the read value in the register. This initialization sequence can also be performed by a DMA (Direct Memory Access) transfer unit previously programmed by the central unit of the microcontroller. 
         [0007]    The result is that the initialization of the microcontroller is relatively costly in terms of execution time, power consumption and space in the non-volatile memory. The relatively significant time taken to execute this initialization procedure thus limits the use of idle mode and the energy savings likely to be made. 
         [0008]    It is thus desirable to provide a means to enable registers of peripherals to be initialized without penalizing the activation time of the microcontroller after switching on the microcontroller or leaving an idle mode. 
       BRIEF SUMMARY 
       [0009]    Some embodiments relate to a method for initializing registers of peripherals in a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral having registers to be initialized, and transferring the data read into the registers of the activated peripheral. According to one embodiment, the initialization data is accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus. 
         [0010]    According to one embodiment, access to the non-volatile memory by the main bus has priority over access by the initialization bus, and access to the registers of peripherals by the initialization bus has priority over access requested by the main bus. 
         [0011]    According to one embodiment, the method includes an act of selecting several registers of the activated peripheral, of sending several register initialization words for initializing a register of a peripheral simultaneously (e.g. concurrently) by the initialization bus, and of loading the initialization words sent into the selected registers of the activated peripheral. 
         [0012]    According to one embodiment, several peripherals are activated simultaneously to each receive simultaneously at least one register initialization word. 
         [0013]    According to one embodiment, several register initialization words for initializing several registers of a peripheral are sent simultaneously by the initialization bus and loaded into selected registers of the peripheral in one cycle of the clock signal of the microcontroller. 
         [0014]    According to one embodiment, the initialization circuit transfers requests for accessing the memory sent by the main bus and transfers the data read in the memory to the main bus, in response to the access requests. 
         [0015]    Some embodiments also relate to a microcontroller including a processing unit, peripherals having registers to be initialized, and a main bus linking the processing unit to the peripherals and to a non-volatile memory. According to one embodiment, the microcontroller includes an initialization circuit for initializing registers of peripherals, the initialization circuit linking the main bus to the memory and being linked to the peripherals by an initialization bus, the initialization circuit being configured to implement the method defined above. 
         [0016]    According to one embodiment, the initialization bus has a width corresponding to several register initialization words for initializing a register of a peripheral. 
         [0017]    According to one embodiment, the initialization circuit is linked to each peripheral by an activation link for activating the peripheral so as to initialize the registers of the peripheral, and a data link for sending a selection signal for selecting a peripheral register initialization word in a datum sent by the initialization bus. 
         [0018]    According to one embodiment, the initialization circuit is linked to each peripheral by several activation links for activating the peripheral so as to initialize the registers of the peripheral, each activation link being associated with a data link for sending a selection signal for selecting a peripheral register initialization word in a datum sent by the initialization bus. 
         [0019]    According to one embodiment, each peripheral includes an interface circuit configured to select a register and a register initialization word in a datum sent by the initialization bus and to load the word selected into the selected register. 
         [0020]    According to one embodiment, the initialization circuit includes circuits for storing a storage base address in the memory containing initialization data for initializing the registers of a peripheral, and for each peripheral, a number of registers to be initialized, and indicators indicating whether or not the peripheral should be initialized and whether or not the peripheral has been initialized. 
         [0021]    According to one embodiment, each peripheral includes an interface circuit connected to the main bus and to the initialization bus and configured to give priority to the access requests received by the initialization bus over those received by the main bus. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0022]    Some examples of embodiments described in the present disclosure will be described below in relation with, but not limited to, the following figures. 
           [0023]    Non-limiting and non-exhaustive embodiments are described with reference to the following drawings, wherein like labels refer to like parts throughout the various views unless otherwise specified. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn are not intended to convey any information regarding the actual shape of the particular elements and have been solely selected for ease of recognition in the drawings. One or more embodiments are described hereinafter with reference to the accompanying drawings in which: 
           [0024]      FIG. 1  schematically represents a microcontroller including a register initialization circuit for initializing registers of peripherals, according to one embodiment, 
           [0025]      FIG. 2  schematically represents the microcontroller and in particular the initialization circuit according to one embodiment, 
           [0026]      FIG. 3  represents the structure of a state register of the initialization circuit, 
           [0027]      FIG. 4  schematically represents an input interface of a peripheral of the microcontroller, according to one embodiment, 
           [0028]      FIGS. 5 and 6  schematically represent circuits of the input interface in  FIG. 4 , according to some embodiments, 
           [0029]      FIG. 7  represents an example of peripheral register initialization data stored in a non-volatile memory of the microcontroller, and 
           [0030]      FIG. 8  represents timing diagrams of signals exchanged between a processing unit and peripherals of the microcontroller, during an initialization phase, according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]      FIG. 1  represents a microcontroller MC according to one embodiment. The microcontroller includes a processing unit PU and possibly a DMA (Direct Memory Access) transfer unit, a volatile memory VM, a non-volatile memory NVM, and peripherals PH 1 , PH 2 , . . . PHn. The unit PU, the DMA unit and the peripherals PH 1 -PHn are linked to a main address and data bus ADB of the microcontroller MC. The peripherals PH 1 -PHn may include one or more external bus controllers, one or more timers, one or more analog-digital converters, one or more digital-analog converters, etc. The memory VM is for example of RAM or SRAM type and the memory NVM can be for example of Flash or EEPROM type. 
         [0032]    According to one embodiment, the memory NVM is linked to the bus ADB through an initialization circuit AINT that is also linked to the peripherals by an initialization bus ITB, to initialize registers of the peripherals PH 1 -PHn. Therefore, the peripherals PH 1 -PHn are connected both to the bus ADB and to the bus ITB. The circuit AINT is configured to read, in the memory, data for initializing registers of the peripherals PH 1 -PHn and to send the data read to the peripherals PH 1 -PHn concerned during an initialization phase of the microcontroller MC. 
         [0033]      FIG. 2  represents the microcontroller MC and in particular, the circuit AINT according to one embodiment. The circuit AINT is linked to each peripheral PH 1 -PHn through the bus ITB and control links CTP. The circuit AINT includes a control circuit FSM, an arbitration circuit ARB controlled by the circuit FSM, a demultiplexer DMX controlled by the circuit ARB and a protocol conversion circuit PRCV connected to the bus ITB and to the control links CTP. The circuit ARB is connected at input to the bus ADB and at output to an addressing input of the memory NVM. The demultiplexer DMX is connected at input to a data output of the memory NVM and includes an output connected to the bus ADB and an output connected to the circuit PRCV. The circuit FSM includes for example a state machine that is initialized and activated upon receiving an initialization signal RS. The circuit FSM is configured to send read commands for reading in the memory NVM initialization data for initializing the registers of the peripherals PH 1 , PHn, and to supply the circuit PRCV, for each datum addressed in the memory NVM, with signals indicating the register(s) of peripherals PH 1 -PHn, receiving the datum. The circuit ARB is configured to retransmit to the memory NVM read commands from either the bus ADB, coming from the unit PU or DMA, or from the circuit FSM, giving priority to the read commands sent by the bus ADB. The demultiplexer DMX is controlled by the circuit ARB to send the data read in the memory NVM either to the bus ADB when the data corresponds to a read command received from the bus ADB, or to the circuit PRCV when the memory NVM was addressed by the circuit FSM to read data for initializing registers of the peripherals PH 1 -PHn. The circuit PRCV is configured to activate peripherals PH 1 -PHn according to the register initialization data received from the memory NVM and sent by the demultiplexer DMX, and to supply the activated peripherals PH 1 -PHn with selection signals for selecting the registers to be initialized, via the control links CTP, in correlation with the initialization data read in the memory NVM which it transmits through the bus ITB to the peripherals PH 1 -PHn. 
         [0034]    It shall be noted that the peripherals PH 1 -PHn may be linked to the bus ADB through a specific bus linked to the bus ADB by an interface circuit BDG ensuring the communication between the two buses. The specific bus may be of AMBA (Advanced Microcontroller Bus Architecture) type such as the AHB (Advanced High-performance Bus) or APB (Advanced Peripheral Bus) developed by the company ARM. 
         [0035]    The circuit FSM also includes configuration and state registers for each peripheral PH 1 -PHn of the microcontroller MC.  FIG. 3  represents the structure of the configuration and state registers STRi corresponding to one of the peripherals PHi. Each register STRi includes a non-modifiable field NRG storing the number of registers to be initialized of the peripheral PHi, a field EN indicating whether or not the registers of the peripheral PHi should be initialized, and a field AI indicating whether or not the registers of the peripheral PHi have been initialized. The field AI is changed when all the registers of the peripheral PHi have been initialized. The circuit FSM also includes a register containing an address of the memory NVM from which the data for initializing the registers of the peripherals PH 1 -PHn is stored. The fields EN corresponding to all the peripherals PHi are for example initialized from the memory NVM upon activation of the microcontroller MC. The fields AI corresponding to all the peripherals PHi are initialized to a value indicating that the registers should be initialized. The circuit FSM initializes registers if at least one field EN of a peripheral indicates that a register initialization should be performed. When all the registers of a peripheral PHi have been initialized, the relevant field AI is updated. 
         [0036]      FIG. 4  represents input interface circuits of a peripheral PHi of the microcontroller. These circuits include an interface circuit INTk for each register RGk of the peripheral. Each circuit INTk includes a bus interface circuit ABIT connected to the bus ADB, a bus interface circuit IBIT connected at input to the bus ITB, a bus selecting circuit BMX connected to outputs of the interface circuits ABIT, IBIT and to the register RGk and a register selecting circuit RSEL. The circuits IBIT and ABIT are configured to perform a data format adjustment between the buses ABD and ITB and the register RGk. The circuit BMX is configured to select one or other of the buses ADB, ITB to be linked to the register RGk of the peripheral PHi according to the control signals CTP. Thus, during the initialization phase, the control signals CTP control the circuit BMX to supply an initialization datum sent by the bus ITB to the register RGk. Outside the initialization phase (when the signals CTP are inactive), the circuit BMX transfers data between the bus ADB and the register RGk. During the initialization phase, the circuit BMX can be configured to process, as a priority, the initialization of the register RGk in relation to access requests coming from the bus ADB. The circuit RSEL is configured to select the register(s) to be activated, particularly to receive an initialization datum during the initialization phase, according to the datum present on the bus ITB. Outside the initialization phase, the circuit RSEL activates the register indicated by the address sent by the bus ADB. 
         [0037]    Referring to  FIGS. 4 and 5 , signals CTP include an activation signal CS(i) for each peripheral PHi, which is sent to the latter. If a data read in the memory NVM can simultaneously (e.g., concurrently) supply several register initialization words and if the bus ITP can simultaneously send all the words read, the signals CTP further include a word select signal WSEL that is sent to each peripheral PHi to indicate which word in the datum sent by the bus ITB should be transferred into a register of the selected peripheral. The signal WSEL includes a number of bits enabling the number of initialization words to be encoded for each datum sent by the bus ITB. The circuit IBIT is then configured to select a word sent by the bus ITB to be transferred into the register RGk to initialize it, according to the signals CTP. 
         [0038]    The initialization procedure for initializing the registers of the peripherals can be speeded up by providing several signals CS(i) for each peripheral PHi, to simultaneously activate several peripherals PHi and simultaneously initialize registers of the activated peripherals PHi. In this case, a word select signal WSEL should be provided for each activation signal CS(i) sent to a same peripheral PHi to enable an initialization word to be selected in the datum present on the bus ITB for each activated peripheral PHi. 
         [0039]      FIGS. 5 to 8  show the case of a memory NVM and of a bus ITB which can simultaneously send four words for initializing registers of peripherals, read in the memory NVM, and the case of control signals CTP including two activation signals CS 1 (i), CS 2 (i) for each peripheral PHi and thus two word select signals WSEL 1 , WSEL 2  each including two bits to designate one word out of four. The output bus of the memory NVM and the bus ITP may thus include for example 128 data bits, while the output bus of the processing unit PU, the bus ABD and the registers of the peripherals PHi to be initialized have 32 data bits. By providing two pairs of signals (CS 1 , WSEL 1 ), (CS 2 , WSEL 2 ) it is possible to simultaneously activate two peripherals PHi, and to simultaneously initialize several registers in the two peripherals activated, if several register initialization words can be read at the same time in the memory NVM and sent by the bus ITB. 
         [0040]      FIG. 5  represents a part of the register selecting circuit RSEL, according to one embodiment. The circuit RSEL includes two AND-type logic gates AG 3 , AG 4 , two OR-type logic gates OG 2 , OG 3 , a timer CNT and a logic circuit LC. The circuit RSEL receives at input the control signals CTP including in this example, a first selection signal CS 1 (i) for selecting the peripheral PHi and an associated word select signal WSEL 1  for selecting a word in a datum sent by the bus ITB, and a second selection signal CS 2 (i) for selecting the peripheral PHi and an associated word select signal WSEL 2  for selecting a word in a datum sent by the bus ITB. The gate AG 3  receives at input the signals CS 1 (i) and WSEL 1 . Similarly, the gate AG 4  receives at input the signals CS 2 (i) and WSEL 2 . The output of each gate AG 3 , AG 4  is connected to a respective input of the gate OG 2  that supplies the circuit LC at a given instant with a word select signal WSEL. The gate OG 3  receives at input the signals CS 1 (i), CS 2 (i) and supplies at output on an initialization input of the timer CNT a signal CS indicating when the peripheral PHi is selected to be initialized. The timer CNT receives a clock signal CLK from the microcontroller MC, defining the rate at which the bus ITB sends register initialization data. The output of the timer CNT is connected to an input of the circuit LC. The timer is initialized to 0 by the signal CS when the peripheral is selected by one or other of the signals CS 1 (i), CS 2 (i) in order to be initialized. The circuit LC is connected at output to each of the register select inputs RGk of the peripheral PHi, and is configured to activate one or more registers RGk according to the signal WSEL and the value of the timer CNT when the peripheral PHi is selected to be initialized by one of the signals CS 1 (i), CS 2 (i). 
         [0041]    When the timer CNT is equal to 1 upon the first cycle of initializing the registers of the peripheral PHi, the circuit LC is configured to simultaneously activate the registers having the numbers 0 to 3-WSEL, without exceeding the number of registers of the peripheral PHi minus one. Upon each of the following cycles of the initialization phase, when the value of the timer CNT is greater than 1, the circuit LC is configured to simultaneously activate four registers of the peripheral PHi, after those initialized in the previous cycle, without exceeding the number of registers of the peripheral PHi minus one. Therefore, during the n cycles following the first cycle, the circuit LC activates the registers having the numbers 4(n-1)-WSEL to 4n-1-WSEL. 
         [0042]      FIG. 6  represents a part of the interface circuit IBIT of one of the registers RGk, according to one embodiment. The circuit IBIT includes two multiplexers MX 1 , MX 2 , two AND-type logic gates AG 1 , AG 2 , an OR-type logic gate OG 1  and two adders AD 1 , AD 2 . Each multiplexer MX 1 , MX 2  includes four inputs receiving the four register initialization words ITB[ 1 ], ITB[ 2 ], ITB[ 3 ], ITB[ 4 ] sent simultaneously by the bus ITB. Each of the adders AD 1 , AD 2  supplies the control input of one of the multiplexers MX 1 , MX 2  with one of the word select signals WSEL 1 , WSEL 2 , added to a register number k of the register RGk to which the circuit IBIT is connected. The output of the multiplexer MX 1  is connected to an input of the gate AG 1  another input of which receives the selection signal CS 1 (i) for selecting the peripheral PHi. Similarly, the output of the multiplexer MX 2  is connected to an input of the gate AG 2  another input of which receives the selection signal CS 2 (i) for selecting the peripheral PHi. The output of each gate AG 1 , AG 2  is connected to a respective input of the gate OG 1  that supplies at a given instant a word WI coming from the bus ITB to be written in the relevant register RGk of the peripheral PHi. 
         [0043]    As a result of these arrangements, when one or other of the signals CS 1 (i) or CS 2 (i) is active for the peripheral PHi, the circuit IBIT of each register activated by the circuit LC, supplies at output WI one of the four words ITB[ 1 ], ITB[ 2 ], ITB[ 3 ], ITB[ 4 ] contained in the datum present on the bus ITB. The first word to be sent into the first register RG 0  of the peripheral PHi is selected by the signal WSEL 1 , WSEL 2  corresponding to the active signal CS 1 (i), CS 2 (i). 
         [0044]      FIG. 7  represents an example of initialization data D 1  to D 4  stored in the memory NVM, in the event that the width of the bus ITB corresponds to the size of four words for initializing registers of peripherals PHi, and where the microcontroller MC includes four peripherals PH 1 , PH 2 , PH 3 , PH 4 . In the example in  FIG. 7 , the peripheral PH 1  includes seven registers to be initialized (NRG(1)=7, EN(1)=1), the peripheral PH 2  includes 6 registers which are not to be initialized (NRG(2)=6, EN(2)=0), the peripheral PH 3  includes three registers to be initialized (NRG(3)=3, EN(3)=1), and the peripheral PH 4  includes four registers to be initialized (NRG(4)=4, EN(4)=1). The datum D 1  thus includes the register initialization words W 1 -W 4  for initializing the first four registers of the peripheral PH 1 . The datum D 2  includes the register initialization words W 5 -W 7  for initializing the last three registers of the peripheral PH 1  and the register initialization word W 1  for initializing the first register of the peripheral PH 3 . The datum D 3  includes the register initialization words W 2 -W 3  for initializing the last two registers of the peripheral PH 3 , and the register initialization words W 1 -W 2  for initializing the first two registers of the peripheral PH 4 . Finally, the datum D 4  includes the register initialization words W 3 -W 4  for initializing the last two registers of the peripheral PH 4 . 
         [0045]      FIG. 8  represents timing diagrams of signals appearing during the initialization phase, between the circuit AINT, the memory NVM, and the peripherals PH 1 , PH 2 , PH 3 , PH 4 , in the example in  FIG. 6 . The timing diagrams in  FIG. 8  include the clock signal CLK of the microcontroller MC, the output signals of the memory NVM, the signals CS 1 , CS 2 , WSEL 1 , WSEL 2 , and the content of the registers of the peripherals PH 1 -PH 4 . Before an instant t 0 , the signals CS 1 , CS 2 , WSEL 1 , WSEL 2  are all on  0  and the registers of the peripherals PH 1 -PH 4  are at any initial values RV. At the instant t 0 , the datum D 1  is read in the memory NVM, and the signals CS 1  are set to the value  0001  to activate the peripheral PH 1 . During the next clock cycle up to an instant t 1 , the signal WSEL 1  remains on  0 . The circuit LC thus activates the registers RG 0  to RG 3  of the peripheral PH 1 , and the words W 1 -W 4  of the datum D 1  are transferred simultaneously into the activated registers. At the instant t 1 , the datum D 2  is read in the memory NVM, the signals CS 1  remain on the value  0001  to keep the peripheral PH 1  activated, and the signal WSEL 1  remains on  0 . The signals CS 2  are set to  0100  to activate the peripheral PH 3 , and the signal WSEL 2  is set to  3  to select the fourth word W 1  of the datum D 2 . During the next clock cycle up to an instant t 2 , the circuit LC of the peripheral PH 1  activates the registers RG 4  to RG 6 . The first three words W 5 , W 6 , W 7  of the datum D 2  are thus transferred simultaneously into the registers RG 4  to RG 6  of the peripheral PH 1 . In parallel, the circuit LC of the peripheral PH 3  activates the register RG 0  (3-WSEL 2 =0). The fourth word W 1  of the datum D 2  selected by the signal WSEL 2  is thus transferred into the first register RG 0  of the peripheral PH 3 . At the instant t 2 , the datum D 3  is read in the memory NVM, the signals CS 1  are set to  1000  to activate the peripheral PH 4 , and the signal WSEL 1  is set to  2  to read the datum D 3  starting from the third word. The signals CS 2  remain on  0100  to keep the peripheral PH 3  activated and the signal WSEL 2  remains on  3 . During the next clock cycle up to an instant t 3 , the circuit LC of the peripheral PH 4  selects the registers RG 0 , RG 1  (0 and 3-WSEL 1 ). The last two words W 1 , W 2  of the datum D 3  are thus transferred simultaneously into the registers RG 0  and RG 1  of the peripheral PH 4 . In parallel, the circuit LC of the peripheral PH 3  selects the registers RG 1 , RG 2  (4(n-1)-WSEL 2 =1 and 4n-1-WSEL 2 =4 limited to 2 because the peripheral PH 3  only includes three registers). The first two words W 2 , W 3  of the datum D 3  are thus transferred simultaneously into the registers RG 1  and RG 2  of the peripheral PH 3 . At the instant t 3 , the datum D 4  is read in the memory NVM, the signals CS 1  remain on  1000  to keep the peripheral PH 4  activated, the signal WSEL 1  remains on  2  to read the datum D 4  starting from the first word W 3  for initializing the third and fourth registers RG 2 , RG 3  of the peripheral PH 4  (4(n-1)-WSEL 1 =2 and 4n-1-WSEL 1 =5 limited to 3 because the peripheral PH 3  only includes four registers). The signals CS 2  are put to  0000  and the signal WSEL 2  is put to  0  because there are no more peripherals to be initialized. During the next clock cycle up to an instant t 4 , the circuit LC of the peripheral PH 4  selects the registers RG 2 , RG 3 . The first two words W 3 , W 4  of the datum D 4  are thus transferred simultaneously into the registers RG 2  and RG 3  of the peripheral PH 4 . At the instant t 4 , the signals CS 1  are put to  0000  and the signal WSEL 1  is put to  0  because there are no more peripherals to be initialized. Thus, at the instant t 4 , all the registers of the peripherals PH 1 , PH 3 , PH 4  have been initialized with words read in the memory NVM. As the peripheral PH 2  is not to be initialized (EN(2)=0), its six registers keep their initial value. 
         [0046]    The timing diagrams in  FIG. 8  show that four registers can be initialized during one clock signal cycle, whether these four registers all belong to a single peripheral or are split between two peripherals. If a single register could be initialized upon each read of the memory NVM (number of initialization words per datum read in the memory NVM equal to 1), one clock cycle would be taken to initialize each of the registers of the peripherals. As a comparison, the initialization of such registers by a sequence of instructions executed by the processing unit PU would take approximately 5 cycles for each register to be initialized. In addition, the sequence of instructions uses the resources of the program memory and its execution uses the resources of the processing unit PU. On the other hand, the implementation of the circuit AINT enables the registers of the peripherals to be initialized without using the resources of the processing unit PU or of the program memory. 
         [0047]    It will be understood by those skilled in the art that various alternative embodiments and various applications of the present invention are possible. In particular, the present invention is not limited to the examples of embodiments described herein and also, for example, covers an initialization circuit distinct from the processing unit of the microcontroller, capable of executing a sequence of instructions to initialize the registers of the peripherals of the microcontroller, through the initialization bus ITB. 
         [0048]    It is not necessary for the accesses to the memory NVM, requested by the processing unit PU, to have priority over those requested by the initialization circuit AINT. Indeed, failing to comply with this priority rule merely delays the instant at which the processing unit PU starts up. Furthermore, if this priority rule is not met, it is not necessary to give priority to the initialization bus AINT on the main bus ADB to access the registers of the peripherals PHi. Indeed, if the processing unit PU has not started, no request to access the peripherals PHi is sent by the main bus ADB. 
         [0049]    Also, the number of register initialization words sent by the bus ITP may be chosen different to four, or the number of peripherals liable to be activated simultaneously can be chosen higher than two. In this case, the control signals include as many signals CS and WSEL as peripherals to be activated simultaneously. 
         [0050]    Furthermore, the non-volatile memory NVM in which the words for initializing the registers of the peripherals are contained, may be internal or external to the microcontroller MC. 
         [0051]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.