Abstract:
A bipolar electrostatic chuck containing apparatus, and a concomitant method, for balancing an electrostatic force that the bipolar electrostatic chuck imparts upon a workpiece. More specifically, the bipolar electrostatic chuck contains a chuck body having a pair of electrodes embedded therein, a primary power supply and an offset power supply. Each electrode within the bipolar electrostatic chuck is respectively connected to a terminal on the primary power. Based upon a voltage produced by the primary power supply and a bias voltage of the workpiece, an offset voltage is applied by the offset power supply to one of the terminals, thus balancing the electrostatic force applied to the workpiece.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of prior, co-pending U.S. patent application Ser. No. 09/593,848, filed Jun. 14, 2000 which claims benefit to U.S. Provisional Application No. 60/139,710 filed Jun. 17, 1999, which are herein incorporated by reference. 
     
    
     
       BACKGROUND OF THE DISCLOSURE  
         [0002]    1. Field of the Invention  
           [0003]    The invention relates to a substrate support chuck for electrostatically retaining a workpiece upon the support surface of the chuck. More particularly, the invention relates to a bipolar electrostatic chuck having apparatus for balancing the electrostatic force applied to a workpiece supported by the chuck.  
           [0004]    2. Description of the Background Art  
           [0005]    Substrate support chucks are widely used to support substrates within semiconductor processing systems. One example of an electrostatic chuck is described in commonly assigned European Patent Publication Number 0 439 000 B1, published Sep. 14, 1994. This electrostatic chuck has a conventional chuck body containing a dielectric material having a pair of coplanar electrodes embedded therein. The electrodes are half-moon or D-shaped such that each electrode provides clamping force to half the workpiece that is supported by a support surface of the chuck body.  
           [0006]    In operation, a chucking voltage is applied to each electrode that causes an electric field to form between the electrodes. This electric field causes charge to distribute on the underside of the wafer that is oppositely polarized to charge located on the chuck surface. The Coulomb force between the charge on the wafer and the charge on the chuck surface attracts the wafer to the chuck. As such, the wafer is retained (clamped) upon the chuck surface.  
           [0007]    Ideally, the electrostatic force that retains the wafer should be uniform across the entire underside of the wafer. However, in reality, this electrostatic force may vary substantially across the wafer during processing. The force primarily varies due to the reduction in voltage at one electrode and the increase in voltage at the other electrode caused by a bias voltage acquired by the wafer once the wafer is exposed to an RF-induced plasma. The bias voltage acquired by the wafer is the result of electrons, which are highly mobile as compared to ions also comprising the plasma, leaving the plasma and accumulating on the wafer surface, thus creating a negative charge. As the local electrostatic force is proportional to the voltage drop across each electrode and the wafer, a disparity in electrostatic force laterally across the wafer results.  
           [0008]    For example, in a bipolar, dielectric electrostatic chuck such as that described in European Patent discussed above, the combination of the two electrodes and the wafer form, in effect, a pair of series connected capacitors. If, for example, a power source applies ±400 Volts to the electrodes of a bipolar electrostatic chuck, and a plasma imparts a wafer bias of −100 Volts (as most electrostatic chucks are configured to be cathodes), the voltage drop between one electrode and the wafer will decrease by 100 Volts while at the electrode of opposite polarity, the voltage drop will increase by 100 Volts. This change in the voltage drop between the electrodes and the wafer due to the wafer bias results in an unequal clamping forces to be applied to each half of the wafer.  
           [0009]    One example of apparatus used to balance these electrostatic forces is a bipolar electrostatic chuck driven by a dual power supply having a center tap. The center tap is coupled directly to a wafer residing atop the bipolar electrostatic chuck. The center tap effectively creates a feedback loop such that a change in the bias voltage on the wafer is referenced back to the power supply. As such, the voltage differential that generates the electrostatic force is maintained at both electrodes. Such an apparatus is disclosed in U.S. Pat. No. 5,764,471, issued Jun. 9, 1998, by Burkhart.  
           [0010]    Although using the center tap coupled to the wafer provides an improvement in electrostatic force balancing in a bipolar electrostatic chuck, the connection between the center voltage tap and the wafer creates current leakage paths through the wafer. This current flow through the wafer often damages devices fabricated into the workpiece.  
           [0011]    Another apparatus for balancing these electrostatic forces uses a third power supply at the center tap. The third power supply provides a voltage that approximately matches the wafer potential. As such, the imbalance in power supply voltages that are applied to the electrodes are compensated for. That is, an unequal voltage drop from the wafer to each of the electrodes would be adjusted by supplying a matched voltage from the third power supply. However, this type of configuration requires additional hardware (i.e., the third power supply, matching networks, and computer software/hardware I/O and the like) that are both costly and undesirable.  
           [0012]    Therefore, a need exists in the art for apparatus and a concomitant method of automatically balancing the electrostatic force between an electrostatic chuck and a workpiece without relying on the presence of a plasma proximate the workpiece, coupling the wafer with the chucking circuit, or adding power supplies.  
         SUMMARY OF THE INVENTION  
         [0013]    The disadvantages of the prior art are overcome by the present invention of a bipolar electrostatic chuck containing apparatus for balancing the electrostatic force that the bipolar electrostatic chuck imparts to a workpiece positioned upon the bipolar electrostatic chuck. More specifically, the invention is a bipolar electrostatic chuck coupled to a first and a second power supply. The electrostatic chuck contains a chuck body that is adapted to support a wafer during processing. A first electrode coupled to a first terminal of the first power supply is embedded in the chuck body. A second electrode is embedded in the chuck body. The second electrode is coupled to a second terminal of the second power supply and a first terminal of the second power supply. A second terminal of the second power supply is also coupled to ground.  
           [0014]    In another embodiment, a method for balancing the electrostatic force that the bipolar electrostatic chuck imparts to a workpiece positioned upon the bipolar electrostatic chuck is provided. The method comprises measuring a bias voltage between a substrate and an electrostatic chuck having two electrodes, calculating an ouput voltage, and applying the output voltage to only one electrode of the electrostatic chuck. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:  
         [0016]    [0016]FIG. 1 depicts a schematic cross-sectional view of a bipolar electrostatic chuck in accordance with the subject invention;  
         [0017]    [0017]FIG. 2 depicts a simplified circuit schematic for the bipolar electrostatic chuck of FIG. 1; and  
         [0018]    [0018]FIG. 3 depicts a block diagram of a method for balancing voltages within a bipolar electrostatic chuck in accordance with the subject invention.  
         [0019]    To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. 
     
    
     DETAILED DESCRIPTION  
       [0020]    [0020]FIG. 1 depicts a schematic cross-sectional view a bipolar electrostatic chuck  100  coupled to a power circuit  102 . To illustrate the use of the invention, FIG. 1 depicts the bipolar electrostatic chuck  100  disposed within a semiconductor processing chamber  104 . The semiconductor processing chamber  104  has walls  148  and a lid  150  that confine a plasma  120 . The walls  148  of the semiconductor processing chamber  104  are coupled to ground  132 . The semiconductor processing chamber  104  is coupled to a controller  140 . The bipolar electrostatic chuck  100  has a surface  138  that supports a semiconductor wafer  106 . FIG. 2 depicts a simplified circuit schematic for the electrostatic chuck of FIG. 1. For best understanding of the invention, the reader is encouraged to refer to both FIG. 1 and FIG. 2 while reading the following disclosure.  
         [0021]    The bipolar electrostatic chuck  100  contains a first electrode  108  and a second electrode  110  embedded within a dielectric chuck body  112 , preferably fabricated from a ceramic such as aluminum nitride, boron nitride, or alumina. The first electrode  108  and the second electrode  110  are separated from the surface  138  of the bipolar electrostatic chuck  100  by a thin dielectric layer  134  of the chuck body  112 . The dielectric layer  134  may be a separate layer of material or a portion of the chuck body  112  defined between the respective electrode  108 ,  110  and the surface  138  of the electrostatic chuck  100 . Preferably, the dielectric layer  134  has a uniform thickness between each electrode  108 ,  110  and the surface  138 . An illustrative ceramic electrostatic chuck is disclosed in U.S. Pat. No. 4,117,121, issued May 26, 1992 herein incorporated by reference. Examples of dielectric electrostatic chucks are disclosed in U.S. Pat. No. 4,184,188 issued Jan. 15, 1980 and U.S. Pat. No. 4,384,918 issued May 24, 1983, both of which are incorporated herein by reference.  
         [0022]    During wafer  106  processing, the plasma  120  characterized by an impedance Z i , is generated within the semiconductor processing chamber  104 . The plasma  120  conductively couples the wafer  106  to the semiconductor processing chamber  104  and ground  132 . Due to the charge distribution within the plasma  120 , a wafer bias E w  is imparted upon the wafer  106 . The magnitude of the wafer bias E w  is determined using a measuring means  122 . The measuring means  122  provides a signal indicative of the wafer bias E w  to the controller  140 . The measuring means  122  determines the wafer bias E w  from an exposed electrode, RF peak to peak measurement, selected (manually or via software and/or hardware) from a pre-defined table, or the like.  
         [0023]    To facilitate application of an electrostatic force between the wafer  106  and bipolar electrostatic chuck  100 , the first electrode  108  and the second electrode  110  are coupled to the power circuit  102 . The power circuit  102  is coupled to the controller  140 . Central to the power circuit  102  is a primary power supply  114 . The primary power supply  114  has a positive terminal  124  coupled to the first electrode  108  by a first circuit leg  116  and a negative terminal  126  coupled, to the second electrode  110  by a second circuit leg  118 . The power circuit  130  also comprises an offset power supply  130 . The offset power supply  130  is coupled between the second electrode  110  and the ground  132 . The offset power supply  130  provides a voltage output E OFFSET  that is further discussed below. The offset power supply is coupled to, and controlled by the controller  140 .  
         [0024]    The equivalent circuit of FIG. 1 is depicted in FIG. 2 when considering only the DC components of the process chamber  104 . Using conventional circuit analysis techniques, currents i 1  and i 2  can be expressed as follows:  
               i   1     =           (       E   W     -     E   OFFSET       )          (       R   l1     -     R   l2       )       -       E   ESC          R   l1               (       Z   i     +     R   l1       )          (       R   l1     -     R   l2       )       -     R   l1   2                 (   1   )                 i   2     =           -     (       Z   t     +     R   l1       )            E   ESC       +       (       E   W     -     E   OFFSET       )          R   l1               (       Z   i     +     R   l1       )          (       R   l1     -     R   l2       )       -     R   l1   2                 (   2   )                               
 
         [0025]    and  
           V   1 =( i   1   −i   2 )R /1    (3)  
           V   2   =i   2   R   /2    (4)  
         [0026]    where,  
         [0027]    E OFFSET : offset voltage output  
         [0028]    E ESC : primary power supply output  
         [0029]    E w : wafer potential  
         [0030]    Z I : plasma impedance  
         [0031]    R /1  leakage resistance between wafer and first electrode  108   
         [0032]    R /2  leakage resistance between wafer and second electrode  110   
         [0033]    To balance the chucking forces applied by the first electrode  108  and the second electrode  110  to the wafer  106 , the voltage drop V 1  must equal −V 2 . Thus, setting equation 3 equal to equation 4 and substituting equation 1 for i 1  and equation 2 for i 2 , the offset voltage E OFFSET  can be resolved as:  
               E   OFFSET     =       E   w     +             Z   i          (       R   l1     -     R   l2       )       -       R   l1          R   l2           2        R   l1          R   l2              E   ESC                 (   5   )                               
 
         [0034]    Assuming uniform resistance across the dielectric layer  134 , i.e., R /1 =R /2 , equation (5) simplifies to:  
               E   OFFSET     =       E   w     -       1   2          E   ESC                 (   6   )                               
 
         [0035]    Thus the chucking forces are balanced in the bipolar electrostatic chuck  100  by applying the voltage output E OFFSET  from the offset power supply  130  based upon wafer bias voltage E w  obtained from the measuring means  122  and the known chucking voltage E ESC . As such, variations in the electrostatic bipolar chuck construction or wafer bias imparted by a plasma proximate the wafer that may cause changes in the electrostatic force exerted upon the wafer by the electrodes are balanced by the voltage applied to one electrode by the offset power supply. As such, the voltage differential that generates the electrostatic force is maintained constant on both sides of the wafer.  
         [0036]    The electrostatic forces between a bipolar electrostatic chuck and a wafer are balanced by executing the balancing method  300  illustrated in FIG. 3. The balancing method  300  begins at step  302 , followed by applying chucking voltage E ESC  to the pedestal (step  304 ), measuring the wafer bias voltage E w  (step  306 ), calculating the voltage output E OFFSET  using equation (6)(step  308 ), applying the voltage output E OFFSET  to the second electrode  110  (step  310 ) and ending at step  312 .  
         [0037]    The controller  140  comprises a central processing unit (CPU)  144 , a memory  142 , and support circuits  146  for the CPU  144  is used to facilitate the application of the voltage output E OFFSET  to the second electrode  110 . The CPU  144  may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and subprocessors. The memory  142  is coupled to the CPU  144 . The memory  142 , or computer-readable medium, may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits  146  are coupled to the CPU  144  for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. The control software that is used for implementing the etching process of the present invention is generally stored in memory  142  as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU  144 . The software routine contains the method  300  depicted in FIG. 3 and is discussed below with respect to FIG. 1 and FIG. 2.  
         [0038]    Referring simultaneously to FIG. 1 and FIG. 2, the software routine when executed by the CPU  144 , transforms the general purpose computer into a specific purpose computer (controller)  140  that controls the chamber operation such that a fabrication process (i.e., etching) is performed. Although the process of the present invention is discussed as being implemented as a software routine, some of the method steps that are disclosed therein may be performed in hardware as well as by the software controller. As such, the invention may be implemented in software as executed upon a computer system, in hardware as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware.  
         [0039]    The software routine controls the voltage output E OFFSET  . The software routine is executed as soon as the chucking voltage E ESC  if applied to the wafer  106 . The software routine comprises the steps of applying chucking voltage E ESC  to the pedestal (step  304 ), measuring the wafer bias voltage E W  (step  306 ), calculating the voltage output E OFFSET  using equation (6) (step  308 ), and applying the voltage output E OFFSET  to the second electrode  110  (step  310 ).  
         [0040]    In operation, as the wafer  106  is chucked in absence of the plasma  120  over the wafer  106 , the chucking voltage E ESC  applied between the wafer  106  and each of the electrodes ( 108  and  110 ) is relatively equal such that the electrostatic force retaining the wafer  106  will be balanced. Once the plasma  120  is present above the wafer  106 , the wafer  106  will obtain the wafer bias E w . The wafer bias E W  is measured by the measuring means  122  that supplies a signal to the controller  140 . The controller  140  executes the software routine  300 , and resolves equation (6). The controller  140  then provides a signal to the offset power supply  130  that applies the output voltage E OFFSET  to the second electrode  110  in response to the signal. The output voltage E OFFSET  thus balances V I  and V 2 , thus equalizing the chucking force across the wafer  106 .  
         [0041]    One skilled in the art will readily recognize that bipolar electrostatic chucks may often comprise more than two electrodes. However, the novel aspects of invention are easily adaptable to electrostatic chucks having a first circuit connecting a plurality of electrodes to one pole of a primary power supply and having a second circuit coupled to an offset power supply connecting a second plurality of electrodes to the second pole of the primary power supply. In either power circuit configuration, the use of neither extra (i.e., a third) power supply nor a resistor (or similar) bridge network is required to achieve the desired offset voltage to balance the chucking forces on the wafer.  
         [0042]    Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.