Abstract:
A method for forming a metal layer having a predetermined thickness on an underlying material is disclosed. According to the method, the underlying material is electroplated to form the metal layer having a fraction of the predetermined thickness thereon. The step of electroplating is interrupted for a predetermined period of time. The step of electroplating is then resumed to form the metal layer having the predetermined thickness on the underlying material, thereby improving planarity of the metal layer.

Description:
BACKGROUND  
       [0001]     The present invention relates generally to semiconductor processing technology, and more particularly to a method for forming a metal layer in multiple steps.  
         [0002]     Semiconductor integrated circuits (ICs) have many levels of patterned metal layers. Different levels of metal layers can be connected by interconnection structures, such as vias and cross-over trenches that contain inlaid conductive materials. The process of forming the metal layers is usually referred to as metallization. Copper is usually selected as the material for forming the metal layers, because of its superior electrical conductivity.  
         [0003]     The copper layer is usually formed by an electroplating process. A thin seed layer is deposited on an underlying material, such as a semiconductor substrate or a dielectric layer. The underlying material, on which the seed layer is disposed, is placed in a chemical electroplating solution or a chemical reaction chamber. The seed layer then grow into a thicker copper layer atop the underlying material. The copper layer is then patterned to form a desired conductive structure.  
         [0004]     In certain applications, some very thick copper layers are needed. Those thick copper layers often cause the problem of “hillock.” During the electroplating process, each grain grows in an individual crystal orientation. As growth proceeds, grains fill the space between them and generally grow upward at similar rates. However, some grains find early nucleation and have a head start in growth. Also, some grains grow at a crystal orientation that promotes a faster growth rate. Such grains that grow substantially taller than their neighbors are identified as “hillocks.” As the thickness of the copper layer increases, the problem of “hillock” becomes more serious. When the thickness of the copper layer is under 13K angstroms, the grain size of copper is relatively small, and does not cause serious problems to the copper layer. However, when the thickness of the copper layer is above 40K angstroms, the copper grain may become a “hillock,” and cause serious problems to the copper layer.  
         [0005]     The “hillocks” may cause certain drawbacks. One drawback is the irregular etching rates over the surface of the copper layer due to the “hillocks.” Another drawback is that the “hillocks” may increase the possibility of bumping failures when using the copper layer as a bonding pad during an IC packaging process.  
         [0006]     Therefore, desirable in the art of semiconductor processing technology is a method for forming a metal layer without suffering from the “hillock” problems.  
       SUMMARY  
       [0007]     The present invention discloses a method for forming a metal layer having a predetermined thickness on an underlying material. In one embodiment of the invention, the underlying material is electroplated to form the metal layer having a fraction of the predetermined thickness thereon. The step of electroplating is interrupted for a predetermined period of time. The step of electroplating is then resumed to form the metal layer having the predetermined thickness on the underlying material, thereby improving planarity of the metal layer.  
         [0008]     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  illustrates a cross-sectional view of a semiconductor structure having a metal layer with “hillocks” generated during a conventional electroplating process.  
         [0010]      FIG. 2  illustrates a cross-sectional view of a semiconductor structure having a metal layer of a fraction of a predetermined thickness in accordance with one embodiment of the present invention.  
         [0011]      FIG. 3  illustrates a cross-sectional view of a semiconductor structure having a metal layer of the predetermined thickness in accordance with one embodiment of the present invention. 
     
    
     DESCRIPTION  
       [0012]      FIG. 1  illustrates a cross-sectional view of a semiconductor structure  100  having a metal layer  106  formed thereon by a conventional electroplating process. The semiconductor structure  100  includes an underlying material  102 , which can be a semiconductor substrate or a dielectric layer. A seed layer  104  is formed on the underlying material  102 . During an electroplating process, the underlying material  102  together with the seed layer  104  is placed in a chemical electroplating solution or a chemical reaction chamber. The seed layer  104  then grows into a metal layer  106  of a certain thickness. As discussed above, when the thickness of the metal layer  106  is large enough, a plurality of metal grains  108  will extend substantially beyond the surface of the metal layer  106  and become undesirable “hillocks.” This causes problems, such as uneven etching rates over the surface of metal layer  106 , and higher possibility of bumping failure when using the metal layer  106  as a bounding pad during an IC packaging process.  
         [0013]      FIGS. 2 and 3  present a process flow of forming a metal layer with reduced grain size in accordance with one embodiment of the present invention.  FIG. 2  illustrates a cross-sectional view of a semiconductor structure  200 . The semiconductor structure  200  includes an underlying material  202 , which can be a semiconductor substrate or a dielectric layer. A seed layer  204  is formed on the underlying material  202 . During an electroplating process, the underlying material  202  together with the seed layer  204  is placed in a chemical electroplating solution or a chemical reaction chamber. The seed layer  204  then grows into a metal layer  206 . Before the metal layer  206  grows into its full predetermined thickness, the electroplating process is interrupted for a predetermined period of time.  
         [0014]     In this embodiment, the metal layer  206  is made of copper. However, other conductive materials, such as aluminum, titanium, tantalum, cobalt, nickel, and an alloy thereof, can also be selected as the material for the metal layer  206 . The predetermined time period of interruption can be any time period more than one second. The predetermined thickness is the thickness eventually the metal layer  206  will have after the processing steps present by  FIGS. 2 and 3  are completed. The thickness of the metal layer  206  is only a fraction of the predetermined thickness. For example, the predetermined thickness may be 40K angstroms, and the thickness of the metal layer  206  is only 50 percent of the predetermined thickness. In other words, the thickness of the metal layer  206  is about 20K angstroms, which is relatively thin as opposed to the whole predetermined thickness. As a result, the grains  208  of the metal layer  206  would not become hillocks that make the surface of metal layer  206  uneven.  
         [0015]     During the interruption of the electroplating process, the semiconductor structure  200  is removed from the chemical electroplating solution or the chemical reaction chamber. This interrupts the continuous growth of the grains  208 .  
         [0016]      FIG. 3  illustrates a cross-sectional view of a semiconductor structure  300 , which is sued to explain the step of resuming the electroplating process. After the interruption, the semiconductor structure  200  (see  FIG. 2 ) is reintroduced into the chemical electroplating solution or the chemical reaction chamber. The electroplating process is resumed and the metal layer  206  further grows into the full predetermined thickness with the addition of the metal layer  206 ′. In this embodiment, the predetermined thickness is in a range between 1 and 100K angstroms. Due to the interruption, new nucleation sites are created. In most cases, plating new metal grains does not continue with the same crystal orientation or locations as in the original metal grains  208  (see  FIG. 2 ). The additional metal layer  206 ′ has a different grain structure than the originally grown metal layer  206 . While grains  304  make the additional metal layer  206 ′ uneven, they do not present a “hillock” problem. Similarly, while a rare grain  306  continues to grow from the metal layer  206 , it does not present a significant “hillock” problem, either. As such, the planarity of the surface of the metal layer  206 ′ is improved.  
         [0017]     The advantage of this invention is that the totality of the irregularity of the originally grown metal layer and the irregularity of the additional metal layer is less than that of the irregularity of a metal layer formed by the conventional one-step electroplating process. The full predetermined thickness of the metal layer may be divided into more than two metal layers of fractional thickness. The steps of interrupting and resuming the electroplating process can be repeated for many times to form a metal layer of a desirable thickness without generating “hillocks.” Thus, the present invention helps to provide the surface of metal layer with even etching rates. It also helps to reduce the possibility of bumping failure when using the metal layer as a bounding pad during an IC packaging process.  
         [0018]     The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0019]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.