Abstract:
A power-on control circuit for an integrated circuit of the type having plural voltage source. The circuit is powered on sequentially, thereby preventing bus contention. The power-on control circuit includes a power-on detection for generating an enabling signal and disabling signal to control output buffer. When the high voltage source is powered on and the low voltage is not, the output buffer is at a high impedance state to prevent bus contention. When the low voltage is powered on after the high voltage is powered on, the output buffer is at a normal state.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to the field of an integrated circuit technology. In particular, it relates to a power-on detection circuit at output buffer to ensure output buffer tri-state when high voltage is powered on. 
     2. Description of the Related Art 
     In order to prevent leakage and latch up in an ESD device of an IC with plural voltage supply, power-on sequence must be precise in output buffer design. The power-on sequence turns on the high voltage source first and the low voltage source second, but, bus contention results. FIG. 1A shows the function block of the I/O circuits and the bus. FIG. 1B shows a conventional output buffer  30 . The I/O voltage source VD 33  is powered on, but the core voltage source VDD is not. A PMOS  41  in an output buffer  30  of a circuit  101  is turned on such that a output terminal  40  of the circuit  101  is at high voltage level. A NMOS  40  in a output buffer  30  of a circuit  103  is turned on that an output terminal  40  of the circuit  103  is at low voltage level. Neither a PMOS  41  nor a NMOS  42  is turned on in a output buffer  30  of a circuit  105  such that a output terminal  40  of the circuit  105  is at high-impedance. A short current starts from the circuit  101  to the circuit  103  through a bus  102 . This causes a bus contention among the circuit  101 , the circuit  103 , and the circuit  105 . 
     The disadvantage of the conventional output buffer is that the state of the output terminal is undetermined when the I/O voltage source is powered on. There are three possible states: high voltage level, low voltage level, or high impedance, creating bus contention. It is necessary to add a power-on detect circuit in a output buffer to ensure the output buffer is at high impedance when I/O voltage source is power-on. 
     FIG. 2 shows a conventional power-on detect circuit. The gate of a PMOS  62  is coupled to a test signal  67 , the source is coupled to a power supply  75 , and the drain is coupled to a node B. The gate of a NMOS  63  is coupled to a power supply  75 , the source is coupled to a ground, and the drain is coupled to a node B. The input terminals of a NOR gate  65  couple to the test signal  67  and the node B respectively, the output terminal generates reset signal  66  to the reset of a standby flag  61 . The input terminals of AND gate  68  couple to a write signal  69  and node A respectively, and the output terminal of it couples to the set of the standby flag  61 . A standby flag implemented by a R/S latch flip-flop has its output coupled to a bus driver  70 . The control terminal of the bus driver is coupled to a read signal  71 , and the output terminal of it is coupled to the node A. 
     As shown in FIG. 3, the power supply  75  is powered on at time t 1 , the test signal  67  is at low voltage level, such that the PMOS  62  turns on. At time t 2 , the voltage of the power supply increases gradually such that the NMOS turns on and the power-on detect signal  64  (i.e. the node B) is maintained at a low level until the power supply  75  becomes the inversion level. Therefore, the NOR gate  65  is supplied with two low level input signals, so that the NOR gate  65  supplies a high level reset signal  66  to the reset terminal of the standby flag  61  to be reset. At time t 3 , the power supply  75  increases to the inversion level, power-on detecting signal  64  reaches a high level, so that the NOR gate  65  supplies a low level reset signal  66  to the standby flag  61 . The standby flag  61  is set when the AND gate  68  supplies a high logic level on the condition that the write signal  69  is active and the bus  72  is at a high level. An output signal of the standby flag  61  is supplied to the bus  72  through the bus driver  70  when a read signal  71  supplied to the bus  72  becomes active. At time t 4 , the test signal  67  is set be high, so that the PMOS  62  is turned off and the power-on detecting signal  64  is at a low level. During the times t 3  to t 4 , a constant current I 1  flows through the PMOS  62  and the NMOS  63 . 
     There are two disadvantages in the conventional power-on detect circuit. First, an extra test signal is needed to control the duration of the power-on detecting signal. Second, a constant current flows through the power-on detect circuit when the power-on detecting signal is active. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein: 
     FIG. 1A is a block diagram of conventional I/O circuits and the bus; 
     FIG. 1B is a schematic diagram of a conventional output buffer; 
     FIG. 2 is a schematic diagram of a conventional power-on detect circuit; 
     FIG. 3 shows a time chart of the conventional power-on detect circuit; 
     FIG. 4 is a function block diagram of the present invention; 
     FIG. 5 is a schematic diagram of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention utilizes a power-on detection circuit to ensure an output buffer is at high impedance when only high voltage is powered on. The output buffer operates normally when low voltage is powered on. 
     FIG. 4 illustrates the operation between a power-on detection circuit and a output buffer. The architecture in FIG. 4 includes a power-on detection circuit  10 , a pull up circuit  22 , a pull down circuit  21 , an output buffer  30 . The power-on detection circuit is coupled to I/O voltage source VD 33  and core voltage source VDD, generating two control signals coupled to a pull-down circuit and a pull-up circuit through signal lines  11   a  and  11   b  respectively. The pull-down circuit  21  is coupled between the input terminal  27  and a low voltage level. The pull up circuit  22  is coupled between the input terminal  28  and a high voltage level. The power-on detection circuit detects the power-on sequence. When the I/O voltage source is powered on and the core voltage is not, the two control signals enable the pull down circuit  21  and the pull up circuit  22 . The input terminal  27  is coupled to the low voltage level, so that a PMOS  41  of the output buffer  30  is turned off. The input terminal  28  is coupled to the high voltage level, so that a NMOS  42  of the output buffer  30  is turned off. Therefore, the output buffer  30  is at high impedance to prevent bus contention. 
     The core voltage source VDD is powered on after the I/O voltage source is powered on. The power-on detection circuit  10  outputs a control signal to disable the pull down circuit  21  and pull up circuit  22 . Thus, the input terminal  27  and input terminal  28  of the output buffer  30  are enabled, that is, they can receive the internal signal. 
     Accordingly, a schematic of the present invention is shown in FIG.  5 . The power-on detection circuit  10  includes a PMOS  12 , a PMOS  14 , a NMOS  13 , an inverter  15 , and an inverter  16 . A source of the PMOS  12  to the I/O voltage source VD 33 . The NMOS  13  is connected at a drain to a node  17 , the drain of the PMOS  12 , at a gate to core voltage source VDD, and a source to a low voltage level VSS. The PMOS  14 , acting as a capacitance is connected at a drain and a source both to the I/O voltage source VD 33 , and at a gate to the node  17 . An inverter  15  is connected at the input terminal to the node  17 , and at an output terminal  19   b  to the gate of the PMOS  12  and to the signal line  11   b . An inverter  16  is connected at an input terminal to the output terminal  19   b , and at an output  19   a  to the signal line  11   a . A PMOS  24  is connected at a drain to the input terminal  28 , at a source to a high voltage level, and a gate to the signal line  11   b . A NMOS  23  is connected at a drain to the input terminal  27 , at source to a low voltage level, and a gate to the signal  11   a.    
     The PMOS  12 , the NMOS  14 , and the inverter  15  form a positive feedback loop. When the core voltage source VDD is not powered on, the NMOS  13  is turned off. In such a state, when the I/O voltage source VD 33  is powered on, the capacitance of the PMOS  14  and the parasitic capacitance of the NMOS  13  couple a voltage drop to the node  17 , so that the inverter  15  inverts the voltage to supply a low voltage to turn on the PMOS  12  to charge the node  17 . Therefore, the node  17  is latched at a high voltage, and the output terminal  19   b  is at low voltage supplied to the inverter  16  such that the output terminal  19   a  is at high voltage. 
     The NMOS  23  is turned on by the signal line  11   a , the input terminal  27  is pulled down to a low voltage level, and the PMOS  41  is turned off. The PMOS  24  is turned on by the signal line  11   b , the input terminal  28  is pulled up to a high voltage level, and the NMOS  42  is turned off. Thus, the output terminal  40  of the output buffer  30  is at high impedance to prevent bus contention. 
     When the core voltage source VDD is powered on after the I/O voltage source VD 33  is powered on, the NMOS  13  is turned on thereby. The NMOS  13  pulls down the voltage of the node  17  to a low level such that the inverter  15  supplies a high voltage to the gate of the PMOS  12  to turn off the PMOS  12  to break off the positive feedback loop. The gate of the PMOS  24  is turned off by a high voltage of the output terminal  19   b . The output terminal  19   a  of the inverter  16  is inverted to a low voltage level owing to the output terminal  19   b  being at a high voltage level. The gate of the NMOS  23  is turn off by a high voltage of the output terminal  19   b . Thus, the input terminal  27  and the input terminal  28  are enabled, such that they can receive the internal signal. 
     There are four advantages concluded from the above description of the present invention. First, it can detect the state when only the high voltage source is powered on. Second, when only high voltage source is powered on, it ensures the output buffer is at high impedance. Third, the powered on detection circuit utilizes the couple capacitance, so that it responds quickly. Fourth, the power-on detection circuit requires a small layout area. 
     While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modification or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents.