Abstract:
A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.

Description:
BACKGROUND 
   1. Field 
   The present disclosure relates generally to register files, and more specifically, to methods and systems for providing energy efficient register files. 
   2. Background 
   An embedded processor design typically includes temporary storage such instruction caches, data caches and register files, etc. These storage components are relatively small, high speed memories that increase the speed of the processor by reducing the number of times the processor has to access slower external memory. Unfortunately, these storage components tend to consume a lot of power due to the switching capacitive loads. Larger components tend to switch more capacitive loads than smaller components, and therefore, consume more power. For example, after instruction and data caches, register files that are used as general purpose registers typically tend to consume more power than most of the other smaller components in an embedded processor design. 
   When an instruction is executed, appropriate source operands are first retrieved from the corresponding register file(s). After the instruction has been executed, results, if any, are written back into the register file(s). However, before these results are written back into the register file(s), one or more of these results are often needed for a subsequent instruction as a source operand and are thus taken by a forwarding network for further processing. The longer the pipeline the more likely that the source operands will be delivered to the forwarding network instead of the register file; furthermore, the more often the results are taken by the forwarding network, the longer the corresponding register file(s) have to wait before they are updated with the latest data. One ramification is that invalid data remain in the register file(s) for longer periods of time. If subsequent read operations are performed on register file(s) having invalid data, such read operations would produce incorrect results if used for instruction execution. In addition, power expended on such operations would be wasted. Hence, it would be desirable to provide an energy efficient means to prevent invalid read operations. 
   SUMMARY 
   A register file is disclosed. The register file includes a plurality of registers, and a decoder configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid. 
   Another register file is disclosed. The register file includes a plurality of registers, means for receiving an address for any one of the registers, and means for disabling a read operation to the addressed register if data in the addressed register is invalid. 
   A method of accessing a register file having a plurality of registers includes receiving an address for one of the registers, and disabling a read operation to the addressed register in response to the data in the addressed register being invalid. 
   It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein: 
       FIG. 1  is a simplified block diagram illustrating a system having an energy efficient register file according to the present disclosure; 
       FIG. 2  is a simplified block diagram illustrating one embodiment of an energy efficient register file according to the present disclosure. 
   

   DETAILED DESCRIPTION 
   The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. 
     FIG. 1  is a conceptual block diagram illustrating an example of a data processing system  100 , capable of processing, retrieving and storing information. The data processing system  100  may be a stand-alone component, or alternatively, embedded in a device such as a mobile telephone, PDA, PC, laptop, digital camera, game console, or any other suitable device. The data processing system  100  may include a processor  102 , such as a microprocessor, a digital signal processor, a video graphics processor, or any other suitable processor. The data processing system  100  may also include memory  104 , which holds the program instructions and data needed by the processor  102  to perform its functions. 
   The processor  102  may be configured as a pipeline processor. Instruction and data caches  108  may also be provided for storage of the most recently accessed instructions and data. A register file  106  may be provided to store operands that are needed by the pipeline  110  for the execution of instructions. When an instruction is to be executed, the source operands for such instruction can be retrieved from the register file  106  and then used in the pipeline  110  to execute the instruction. Upon completion of the instruction, any results may then be written back into the register file  106  to be used as source operands for subsequent instructions, or provided to a forwarding network for further processing. The processor  102  may also include peripheral devices, or any other types of devices that handle computational processes or data movement. 
     FIG. 2  is a schematic block diagram illustrating an example of how the processor accesses its internal register file. The register file  106  may include a number of registers  200   a - m . Each register  200  may be used to store data. Such data can be used as an operand for an instruction. The register file  106  may also include a number of other components including, for example, a decoder  202 , and logic devices  204   a - m . The decoder  202  and logic devices  204   a - m  are shown in  FIG. 2  to illustrate the manner in which the processor reads from the register file. The circuitry required to write to the cells is well known in the art, and therefore, is not shown. 
   Each of the registers  200   a - m  may include a number of cells 0-rdy, and a number of switches  210   a - m . The internal circuitry and logic details of the 0-rdy are well known in the art, and therefore, will not be discussed any further. The switches are shown as field effect transistors (FET), but may be any type of suitable switches. Two switches are used with each cell to couple the stored bit and its complement to a pair of differential bit-lines  216   a - 216   n  when its register is enabled. The registers may be enabled through their corresponding logic devices  204   a - 204   m . The logic devices  204   a - 204   m  are used to generate an enable signal on one of the word lines WL 0 - WL m  which select the corresponding register. The logic devices  204   a - 204   m  are implemented in  FIG. 2  with AND functionality, but may be implemented in any suitable manner. An operand-ready signal  212   a - 212   m  from each cell  206   a - m  may be provided as an input to its corresponding logic device  204   a - m . The use of the operand-ready signal  212   a - m  will be further described below. A clock signal  218  may also be provided as an input to the logic devices  204   a - m  to control their activation based on circuit timing. Since only one register is selected at a time, the differential bit lines for each bit position of the multiple registers may share the same sense amplifier. The sense amplifiers  208   a - 208   n  provide an output based on its corresponding differential bit lines. 
   The operations of the register file  106  is further described as follows. On a read operation, a register file address  214  is provided to the decoder  202  from a register access stage  215  in the processor pipeline. The decoder  202  activates the target register by providing the appropriate control signal to the corresponding logic device. The logic device corresponding to the target register also receives, as an input, an ready signal  212   a - m  from one of the cells associated with the target register. The logic device uses the state of the ready signal  212   a - m  to determine whether to enable the cells associated with the target register. Depending on the state of the ready signal, the logic device may then enable the target register by connecting the target register cells to the differential bit lines through their respective switches, thereby allowing data contained in the cells to be read out via the sense amplifiers  208   a - n.    
   Each of the registers  200   a - m  may include a number of cells 0-rdy, and a number of switches  210   a - m . The internal circuitry and logic details of the cells 0-rdy are well known in the art, and therefore, will not be discussed any further. The switches are shown as field effect transistors (FET), but may be any type of suitable switches. Two switches are used with each cell to couple the stored bit and its complement to a pair of differential bit-lines  216   a - 216   n  when its register is enabled. The registers may be enabled through their corresponding logic devices  204   a - 204   m . The logic devices  204   a - 204   m  are used to generate an enable signal on one of the word lines WL 0 - WL m  which select the corresponding register. The logic devices  204   a - 204   m  are implemented in  FIG. 2  with AND functionality, but may be implemented in any suitable manner. An operand-ready signal  212   a - 212   m  from each cell  206   a - m  may be provided as an input to its corresponding logic device  204   a - m . The use of the operand-ready signal  212   a - m  will be further described below. A clock signal  218  may also be provided as an input to the logic devices  204   a - m  to control their activation based on circuit timing. Since only one register is selected at a time, the differential bit lines for each bit position of the multiple registers may share the same sense amplifier. The sense amplifiers  208   a - 208   n  provide an output based on its corresponding differential bit lines. 
   The state of the ready signal  212  can be controlled in a number of ways. For example, the ready signal  212  can be switched to an “off” state to indicate that data is not valid when an instruction that will update that register is fetched by the pipeline, and to an “on” state to indicate that data is valid when the data resulting from the execution of that write instruction has been written back into the register. 
   An example of a methodology to update the ready signal is shown in  FIG. 2 . A decoder  222  may be configured to provide a “set” and “reset” signal to the cell in each register holding the ready signal. In this example, the “set” signal is used to switch the ready signal to the “on” state, and the “reset” signal is used to switch the ready signal to the “off” state. The polarities may be different in other embodiments depending on the word line WL x  gating logic. The decoder  222  may be controlled from various stages within the pipeline depending on the particular application and the overall design constraints. In at least one embodiment of the processor, ready signal is “reset” when a write instruction is fetched by the pipeline. That is, the address of the register file for the write instruction, along with a “reset” control signal, is provided to the decoder  222  from a fetch instruction stage  224  in the pipeline. Once the write instruction works its way through the pipeline and reaches the write back stage  226 , the address of the register file and a “set” control signal can be provided to the decoder  222 . This causes the decoder to “set” the ready signal in the register file. 
   Another methodology for updating the ready signal is to use the bit lines  216   a  in a manner similar to how other cells are written. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate how to use the appropriate logic, circuits and/or other components to implement the operand-ready signal  212  according to the present disclosure. 
   When the state of the operand-ready signal  212  indicates that data stored in the target register is not valid, the corresponding logic device is gated off (i.e., the corresponding word line WL X  output from the logic does not activate the switches associated with the target register). As a result, the bit lines  216   a - n  are prevented from switching which, in turn, means the sense amplifiers  208   a - n  are also prevented from switching. Therefore, data stored in the target register is not outputted via the sense amplifiers  208   a - n.    
   The following is an example further illustrating operations of the register file  106 . It is assumed that the register file address identifies the register  200   a  for a read operation pursuant to an instruction. The decoder  202  decodes such information and sends the appropriate control signal to the logic device  204   a  to indicate that the register  200   a  has been targeted for the read operation. Other control signals are also sent by the decoder  202  to the other logic devices  204   b - m  to indicate that the other registers  200   b - m  are not needed for this particular read operation. 
   The logic device  204   a  also receives an operand-ready signal  212   a  from one of the cells  206   a  associated with the register  200   a . If the operand-ready signal  212   a  indicates that data in the register  200   a  is not valid, the logic device  204   a  is gated off, i.e., the logic device  204   a  outputs a control signal on the word line WL 0  that prevents the switches  210   a  from switching on. As a result, the bit lines  216   a - n  are not switched and data stored in the cells 0-rdy are not outputted via the sense amplifiers  208   a - n . Alternatively, if the operand-ready signal  212   a  indicates that the data stored in the register  200   a  is valid, the logic device  204   a  outputs a control signal on the word line WL 0  that turns on the switches  210   a . As a result, the data from the target register  200   a  is placed on the bit lines  216   a - n  and outputted from the register file  106  via the sense amplifiers  208   a - n . 
   The various illustrative logical blocks, modules, circuits, elements, and/or components described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. 
   The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executable by a processor, or in a combination of both, in the form of control logic, programming instructions, or other directions. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. 
   The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit of scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the full scope consistent with the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more”. All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for”.