Abstract:
A capacitor charging-discharging system, including a plurality of serially connected capacitors, a voltage source for setting an equalization potential, and a plurality of parallel monitoring circuit. Each parallel monitoring circuit is connected to the two ends electrodes of one capacitor, and includes: a voltage dividing circuit configured to resistively divide and attenuate two voltages respectively on the two end electrodes of the one capacitor, a differential amplifier configured to amplify a difference between the two divided voltages to thereby detecting a charge potential of the one capacitor, a comparator configured to compare the charge potential with the equalization potential, and a charge current bypass circuit configured to control charge current of the one capacitor, based on an output of the comparator, so that the charge potential of the one capacitor matches the equalization potential.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application under 35 U.S.C. §120 of International Application PCT/JP2013/076008 having the International Filing Date of Sep. 26, 2013. The identified application is fully incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a parallel monitoring circuit that is connected in parallel with a corresponding capacitor from a plurality of capacitors connected in series, and that controls the charging current thereof to equalize the charge potentials of the capacitors. 
         [0004]    2. Background Art 
         [0005]    A capacitor charge-discharge system disclosed in Japanese Patent Application Publication No. 2008-271722 (hereinafter “JPAP&#39;722”; see, e.g., paragraphs [0016] to [0019] and FIG. 1 of JPAP&#39;722) is known as the conventional means for equalizing a charge potential of a plurality of electrical double layer capacitors connected in series. 
         [0006]      FIG. 2  is a circuit diagram illustrating the charge-discharge system disclosed in JPAP&#39;722. In  FIG. 2 , C 1 , C 2 , . . . , C n  are electrical double layer capacitors connected in series between a charging current source  10  and the GND (ground); reference numeral  20  is a load connected in parallel with the series circuit of the electrical double layer capacitors C 1 , C 2 , . . . , C n ; PMC 1 , PMC 2 , . . . , PMC n  are parallel monitoring circuits of the same configuration which are connected in parallel to respective capacitors; CMP 1 , CMP 2 , . . . , CMP n  are comparators; V r1 , V r2 , . . . , V rn  are equalization potentials of the capacitors which are provided as reference potentials (usually, V r1 =V r2 = . . . =V rn =V r  and equals to the full charge potential of each capacitor); R 1 , R 2 , . . . , R 3  are resistors for current restriction, and Tr 1 , Tr 2 , . . . , Tr n  are transistors for current bypass. 
         [0007]    With such a conventional technique, the comparators CMP 1 , CMP 2 , . . . , CMP n  compare the difference in potentials between the terminals of the capacitors C 1 , C 2 , . . . , C n , that is, the charge potential of the capacitors C 1 , C 2 , . . . , C n , with the equalization potential V r . Where the charge potential is less than V r , the transistor is switched OFF, and charging of the capacitor is continued, and where the charge potential is greater than V r , the transistor is switched ON, the charging current is bypassed, and charging of the capacitor is stopped, thereby performing equalization charging of all of the capacitors C 1 , C 2 , . . . , C n . 
         [0008]    In JPAP&#39;722, as depicted in  FIG. 2 , the lower-potential side of each capacitor is connected to an inverting input terminal of each comparator through a voltage source that generates the equalization potential V r , and the upper-potential side of each capacitor is connected to the non-inverting input terminal of each comparator. Such a circuit configuration is disclosed not only in JPAP&#39;722, but also in other literature. 
         [0009]    However, in such a circuit configuration, the voltage source that generates the equalization potential V r  is needed for each capacitor and is not shared. The resultant problem is that the circuit configuration is complex. Further, since the equalization potential V r  has a fixed value, the charge potential cannot be changed and the capacitors cannot be equalization charged to a random value. 
         [0010]    A capacitor charge control circuit disclosed in Japanese Patent Application Publication No. 2008-178202 (hereinafter “JPAP&#39;202”; see, e.g., paragraphs [0032] to [0042] and FIGS. 3 and 4 of JPAP&#39;202) is known as the conventional means for resolving the above-described problems. 
         [0011]      FIG. 3  is a block diagram illustrating the capacitor charge control circuit disclosed in JPAP&#39;202. In  FIG. 3 , PMC 11 , PMC 12 , . . . , PMC 1n  are parallel monitoring circuits of the same configuration that are connected in parallel with respective electrical double layer capacitors C 1 , C 2 , . . . , C n ;  31  is a voltage-current conversion circuit;  32  is a current-voltage conversion circuit (trimming resistor);  33  is a capacitor voltage division circuit;  34  is a bypass element drive circuit;  35  is a bypass element;  40  is a reference voltage generation circuit;  50  is a decoder; and  60  is a D-A (digital-to-analog) converter. 
         [0012]      FIG. 4  depicts a specific circuit of the capacitor charge control circuit depicted in  FIG. 3 ; here,  70  is a control circuit generating a control signal which is input to the decoder  50  on the basis of the voltages V c1 , V c2 , . . . of the capacitors C 1 , C 2 , . . . . 
         [0013]    In this conventional configuration, the equalization potential V r  input to a comparator  34   a  in the bypass element drive circuit  34  can be easily changed by using the D-A converter  60 . Another advantage is that as a result of providing the voltage-current conversion circuit  31  and the current-voltage conversion circuit  32  before inputting the equalization potential V r  to the comparator  34   a , the D-A converter  60 , which is the source of the equalization potential V r , can be shared by all of the capacitors C 1 , C 2 , . . . , C n . 
       BRIEF SUMMARY OF THE INVENTION 
       [0014]    With the conventional configuration disclosed in JPAP&#39;722 (see  FIG. 2  described hereinabove), the upper-potential side of each capacitor is directly connected to the non-inverting input terminal of the comparator. Therefore, the voltage applied to the non-inverting input terminal is the same as the power supply voltage of the comparator. In particular, where power is supplied from the two end electrodes of each capacitor to the comparator, the voltage applied to the non-inverting input terminal becomes equal to the power supply voltage of the comparator. 
         [0015]    In the case of a commonly used comparator, the common-mode input voltage range of at least about 1 V is specified for the power supply voltage. Therefore, where the input voltage is the same as the power supply voltage, unpredictable operation occurs and the device can be damaged. In order to avoid such a problem, it is necessary to select a special comparator of the so-called input rail-to-rail type which can be adapted even to the input voltage substantially equal to the power supply voltage. 
         [0016]    Further, where power is supplied not from the two end electrodes of the capacitor, a comparator with a high breakdown voltage should be selected. This is because where power is supplied not from the two end electrodes of the capacitor, since the negative power supply terminal of each comparator is connected to the GND (0 V), the highest potential, with respect to the GND (0 V), of a plurality of electrical double layer capacitors, which has been connected in series to increase voltage, differs depending on the application and can reach several hundreds of volts in high-voltage applications, and a comparator corresponding to a capacitor close to this highest potential inputs a higher voltage. 
         [0017]    Meanwhile, with the conventional configuration disclosed in JPAP&#39;202 (see  FIGS. 3 and 4  described hereinabove), a restriction is placed on the equalization potential which can be set. 
         [0018]    The full charge potential per one electrical double layer capacitor is usually about 2 V to 3 V. By contrast, even special devices that can be driven by a low voltage require an operation power supply voltage of the comparator of about 1 V. In JPAP&#39;202, for example, where the voltage-dividing resistance values of the capacitor voltage dividing circuit  33  are equal to each other when the capacitors are charged to about 1 V, the input voltage to the comparator is 0.5 V. To prevent the comparator from malfunctioning even in this state, it is necessary to select a special comparator of the input rail-to-rail type in the same manner as in the case described in JPAP&#39;722. Further, even when such a special comparator is selected, the operation of the comparator cannot be guaranteed when the charge potential of the capacitor is less than the operation power supply voltage of the comparator. 
         [0019]    Therefore, in JPAP&#39;202, the equalization potential, which is set for the comparator  34   a , is prescribed to be equal to or higher than the operation power supply voltage of the comparator. 
         [0020]    Further, in the circuit disclosed in JPAP&#39;202, since an N-MOS (N-type metal-oxide-semiconductor field-effect transistor) is used for the voltage-current conversion circuit  31 , the equalization potential which is set for the comparator  34   a  is also prescribed to be equal to or higher than the threshold voltage (usually about 0.6 V to 0.7 V) of the N-MOS. 
         [0021]    As described hereinabove, in the conventional configurations disclosed in JPAP&#39;722 and JPAP&#39;202, a special comparator sometimes needs to be selected for a bypass current, and various restrictions are placed on the lower limit value of the equalization potential. The resultant problem is that equalization charging of a plurality of capacitors cannot be performed at a potential lower than the lower limit value. 
         [0022]    Accordingly, an objective to be attained by the present invention is to provide a parallel monitoring circuit that can use generally used comparators and can perform equalization charging of a plurality of serially connected capacitors at the desired potential. 
         [0023]    In order to resolve the abovementioned problems, the invention provides in one embodiment a parallel monitoring circuit for a capacitor, the circuit being connected to both ends of a corresponding capacitor from among a plurality of serially connected capacitors and including: comparison means for comparing a charge potential of the capacitor with an equalization potential; and charge current bypass means operated by an output of the comparison means and controlling a charge current of the capacitor such that the charge potential matches the equalization potential. 
         [0024]    The specific feature of the present invention is that the parallel monitoring circuit is provided with voltage dividing means for resistively dividing and attenuating a potential of two end electrodes of the capacitor; differential amplification means for amplifying a difference between the divided voltages obtained with the voltage dividing means and detecting the charge potential; and equalization potential setting means for setting the equalization potential as a variable value, wherein the comparison means compares the charge potential detected by the differential amplification means with the equalization potential which has been set by the equalization potential setting means. 
         [0025]    In one embodiment of the invention, the voltage dividing means resistively divides a voltage between a ground potential and the potential of two end electrodes of the respective capacitors. 
         [0026]    In one embodiment of the invention, a voltage attenuation ratio determined by the voltage dividing means is equal to an inverse value of a voltage amplification ratio in the differential amplification means. 
         [0027]    In one embodiment of the invention, the equalization potential setting means can set the equalization potential at predetermined magnitude between 0 V and the full charge equivalent value of the capacitor. 
         [0028]    In one embodiment of the invention, the operation power supply voltages of the differential amplification means and comparison means are supplied from a power supply other than the two end electrodes of the capacitor. 
         [0029]    In accordance with the present invention, the equalization charging of a plurality of capacitors connected in series can be performed to an unrestricted desired value, without using a special comparator of an input rail-to-rail type or a comparator and an operational amplifier with a high voltage resistance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]      FIG. 1  is a circuit diagram of a parallel monitoring circuit according to an embodiment of the present invention. 
           [0031]      FIG. 2  is the circuit diagram of the capacitor charge-discharge system disclosed in JPAP&#39;722. 
           [0032]      FIG. 3  is the block diagram of the capacitor charge-discharge system disclosed in JPAP&#39;202. 
           [0033]      FIG. 4  is a specific circuit diagram of the capacitor charge-discharge system depicted in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0034]    An embodiment of the present invention will be explained hereinbelow with reference to the drawings. 
         [0035]      FIG. 1  is a circuit diagram of a parallel monitoring circuit according to one embodiment of the invention. In  FIG. 1 , capacitors such as electrical double layer capacitors C 1 , C 2 , C 3 , . . . , C n  are connected in series between a charging current source  10  and the GND (ground), and parallel monitoring circuits PMC 21 , PMC 22 , PMC 23 , . . . , PMC 2n  are connected to both ends of the respective capacitors C 1 , C 2 , C 3 , . . . , C n . 
         [0036]    In this configuration, the charge potentials of all of the capacitors C 1 , C 2 , C 3 , . . . , C n  are to be controlled to the same value by the operation of the parallel monitoring circuits PMC 21 , PMC 22 , PMC 23 , . . . , PMC 2n . 
         [0037]    Since the parallel monitoring circuits PMC 21 , PMC 22 , PMC 23 , . . . , PMC 2n  have substantially the same configuration, the configuration thereof is explained hereinbelow by considering mainly the parallel monitoring circuit PMC 21  on the highest potential side by way of example. 
         [0038]    In the parallel monitoring circuit PMC m , an emitter and a collector of a PNP transistor Tr b1  are respectively connected to two end electrodes of the capacitor C 1 , and a resistor R 11  is connected between the emitter and a base of the PNP transistor Tr b1 . A collector and an emitter of a NPN transistor Tr a1  are connected between the base of the transistor Tr b1  and the GND. Here, the transistors Tr b1 , Tr a1  and the below-described resistors R a1 , R 11  and the like constitute the charge current bypass means or the charge current bypass circuit. 
         [0039]    The output of a comparator CMP 1  is applied through the resistor R a1  to the base of the transistor Tr a1 . An equalization voltage V r  is applied from a D-A converter  80  serving as the equalization potential setting means, or a voltage source, to the inverting input terminal of the comparator CMP 1 . This D-A converter  80  is shared with other parallel monitoring circuits PMC 22 , PMC 23 , . . . , PMC 2n , and the equalization voltage V r  is also applied to the inverting input terminals of the comparators CMP 2 , CMP 3 , . . . , CMP n . 
         [0040]    The connection point of the resistor R 11  and the emitter of the transistor Tr b1  is connected through the series circuit of resistors R a12 , R a14  to the non-inverting input terminal of the operational amplifier AMP 1 . Further, the connection point of the resistor R a12  and the resistor R a14  is connected through a resistor R a13  to the GND, and the non-inverting input terminal of the operational amplifier AMP 1  is connected through a resistor R a15  to the GND. 
         [0041]    The collector of the transistor Tr b1  is connected through the series circuit of resistors R b12 , R b14 , R b15  to the output terminal of the operational amplifier AMP 1 , and the connection point of the resistor R b12  and the resistor R b14  is connected through the resistor R b13  to the GND. 
         [0042]    The connection point of the resistor R b12  and the resistor R b14  is connected through the resistor R a24  of the parallel monitoring circuit PMC 22  of the next stage to the non-inverting input terminal of an operational amplifier AMP 2 . Therefore, the resistors R b12 , R b13  and resistors R a24 , R a25  are connected between the high-potential-side electrode of the capacitor C 2  of the next stage and the non-inverting input terminal of the operational amplifier AMP 2  and have the same connection relationship as that of the resistors R a12 , R a13  and R a14 , R a15  with respect to the operational amplifier AMP 1  of the parallel monitoring circuit PMC 21 . 
         [0043]    The same is true for other parallel monitoring circuits PMC 23 , . . . , PMC 2n . 
         [0044]    In the parallel monitoring circuits PMC 22 , PMC 23 , . . . , PMC 2n , Tr a2 , Tr a3 , . . . , Tr an  are NPN transistors, Tr b2 , Tr b3 , . . . , Tr bn  are PNP transistors, AMP 2 , AMP 3 , . . . , AMP n  are operational amplifiers, CMP 2 , CMP 3 , . . . CMP n  are comparators, and R 21 , R 31 , . . . , R n1 , R a2 , R a3 , . . . , R an , R a24 , R a25 , R b22 , R b23 , R b24 , R b25 , R a34 , R a35 , R b32 , R b33 , R b34 , R b35 , R an4 , R an5 , R bn2 , R bn3 , R bn4 , R bn5  are resistors. 
         [0045]    In the parallel monitoring circuits PMC 21 , PMC 22 , PMC 23 , . . . , PMC 2n , the resistors R a12 , R a13 , R b12 , R b13 , R b22 , R b23 , R b32 , R b33 , . . . , R bn2 , R bn3  are voltage-dividing resistors for dividing the potential of the two end electrodes of the capacitors C 1 , C 2 , C 3 , . . . , C n  with respect to the GND (0 V). The resistance values of those voltage-dividing resistors R a12 , R a13 , R b12 , R b13 , R b22 , R b23 , R b32 , R b33 , . . . , R bn2 , R bn3  may be set such that divided voltages fit into the input voltage range of the operational amplifiers AMP 1 , AMP 2 , AMP 3 , . . . , AMP n . 
         [0046]    Further, the resistors R a14 , R a15 , R b14 , R b15 , R a24 , R a25 , R b24 , R b25 , R a34 , R a35 , R b34 , R b35 , . . . , R an4 , R an5 , R bn4 , R bn5  serve to set the amplification ratios of the respective differential amplification circuits, and the resistance values thereof fulfil the following conditions: R a14 =R b14 , R a15 =R b15 , R a24 =R b24 , R a25 =R b2 , . . . , R an5 =R bn5 . 
         [0047]    Further, the resistance values of those resistors R a14 , R a15 , . . . , R bn4 , R bn5  are made higher than the resistance values of the voltage-dividing resistors R a12 , R a13 , R b12 , R b13 , R b22 , R b23 , R b32 , R b33 , . . . , R bn2 , R bn3  to a degree such as not to distort the Voltages V a1P , V a1N  (=V a2P ), V a2N  (=V a3P ), V a3N , . . . , V a(n-1)N  (=V anP ), V anN  appearing at the respective voltage-dividing resistors. 
         [0048]    The output voltage V b1  of the differential amplification circuit (operational amplifier AMP 1 ) in the parallel monitoring circuit PMC 21  can be determined from Expression 1. 
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         [0049]    Therefore, where the resistance values of the resistors R a12 , R a13 , R a14 , R a15  are determined such as to satisfy Expression (2), the output voltage V b1  of the differential amplification circuit becomes equal to the charge potential V cap  of the capacitor C 1  (V b1 =V cap ). Expression (2) indicates that the voltage attenuation ratio determined by the resistors R a12 , R a13  serving as a voltage dividing means, or a voltage dividing circuit, is equal to the inverse value of the voltage amplification ratio in the differential amplification circuit. 
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         [0050]    Thus, where the resistance values of the resistors R a12 , R a13 , R a14 , R a15  are determined such as to satisfy Expression (2), the comparator CMP 1  compares the charge potential V cap  (voltage V b1 ) of the capacitor C 1  with the equalization potential V r . 
         [0051]    Further, in this embodiment, V b1 =V cap  and V cap  is usually equal to less than 2 V to 3 V, regardless of the number of capacitors connected in series. Therefore, the power supply voltage V dd  of all of the comparators may be, for example, about 5 V even when the common-mode input voltage range is taken into account. This power supply voltage V dd  is used commonly also for all of the operational amplifiers. 
         [0052]    Concerning the voltage V b1  and equalization potential V r  compared by the comparator CMP 1 , when V b1 &lt;V r , both transistors Tr a1 , Tr b1  are OFF. Therefore, the current from the charging current source  10  flows to the capacitor C 1 , without bypassing, the capacitor C 1  is charged and the charge potential V cap  approaches the equalization potential V r . 
         [0053]    Further, where V b1 ≧V r , both transistors Tr a1 , Tr b1  are ON and the current from the charging current source  10  is bypassed. As a result, no current flows to the capacitor C 1  and charging is stopped. 
         [0054]    Thus, the charge potential V cap  of each capacitor C 1 , C 2 , C 3 , . . . , C n  depends on the equalization potential V r , and the equalization potential V r  is common for all of the capacitors C 1 , C 2 , C 3 , . . . , C n . Therefore, where the equalization potential V r  is variably controlled by the D-A converter  80 , the charge potential V cap  of all of the capacitors C 1 , C 2 , C 3 , . . . , C n  can be easily changed. 
         [0055]    Further, in the present embodiment, the power supply voltage V dd  of the comparators CMP 2 , CMP 3 , . . . , CMP n , is supplied separately, rather than from the two end electrodes of the capacitors. Therefore, the comparators CMP 2 , CMP 3 , . . . , CMP n  can operate irrespectively of the charge potential V cap  of the capacitors. 
         [0056]    Thus, the V cap  of each capacitor C 1 , C 2 , C 3 , . . . , C n  can be set such as to increase in steps, for example, of 0.1 V, from the state of 0 V, and the capacitors C 1 , C 2 , C 3 , . . . , C n  can be equalization charged to the desired value in a range from 0 V to a potential corresponding to a full charge. 
       INDUSTRIAL APPLICABILITY 
       [0057]    The present invention can be used, for example, for equalization charging of various capacitor series circuits such as batteries for electric automobiles configured by connecting in series a plurality of electrical double layer capacitors.