Abstract:
An FET load gate compensator employing feedback to control the load gate voltage holds the circuit delay and power dissipation of an integrated circuit nearly constant. The integrated circuit chip is provided with several stages of inverters which act as a delay sensor to simulate the delay of the operational circuit on the chip. The time delay of the delay sensor on the integrated circuit chip is compared with an external clock reference by a delay comparator. The delay comparator generates an output voltage which is used to adjust the load gate voltage until the delay in the delay sensor is equal to the clock reference. Since the same load gate voltage is distributed in the rest of the operational circuits in the integrated circuit chip, the delay times of these circuits will track with that of the delay sensor and thus also tend to be held constant.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to field effect transistor (FET) circuits having particular application to integrated circuit technology, and more specifically to an FET load gate compensator which will hold the circuit delay and power dissipation of an integrated circuit chip nearly constant. 
     2. Description of the Prior Art 
     In integrated circuits employing FETs there are several parameters which, while fixed in a particular integrated circuit chip, may vary from integrated circuit chip to chip due to manufacturing tolerances. These include the transconductance (γ m ) of the FETs, the threshold voltage (V T ) of the FETs, the device width and length of the FETs, and the capacitive leadings of the interconnections. Besides these on-chip parameters, there are external variables such as temperature, and supply voltages, which may vary from application to application or within a specific application of the integrated circuits. The variation in on-chip parameters and the external variables associated with a particular application of the integrated circuit all contribute to variations in circuit delay and power dissipation of the integrated circuit chips. This complicates design requiring delay calculations and race condition considerations. Furthermore, input noise immunity is degraded because of the relationship of circuit delay and power dissipation due to variations in supply voltages. While it is known to provide a source of regulated supply voltage to overcome in part these problems, such regulated voltage supplies are complicated and employ Zener diodes. Such regulated voltage supplies cannot compensate for variations in on-chip parameters. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a device which will tightly regulate circuit delay and power dissipation of FET integrated circuit chips in spite of a wide range of device parameters and operating conditions. 
     According to the present invention, the foregoing and other objects are attained by providing a load gate compensator the operation of which is based on the comparison of the circuit delay in the chip with an external time reference and adjusting the load gate voltage (V LG ) until the two are equal. The time reference is assumed to come from the system clock, which is usually available and usually has a very accurate repetition rate. The circuit delay is measured using a delay circuit sensor in the chip. Preferably, this takes the form of several stages of FET inverters which simulate the average delay of the operational circuit on the chip. The comparison of the delay time of the delay sensor with the clock reference is made with a delay comparator which generates an output voltage to control V LG . The range of V LG  can be as wide as from 5 to 12 volts, depending on the standard deviation of the device parameters. The V LG  of each integrated circuit chip is a function of the device parameters and the operating environment of that chip. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The specific nature of the invention, as well as other objects, aspects, uses, and advantages thereof will clearly appear from the following description and from the accompanying drawings, in which: 
     FIG. 1 is a block diagram of the preferred embodiment of the load gate compensator according to the invention; 
     FIG. 2 is a timing diagram illustrating the operation of the load gate compensator shown in FIG. 1; 
     FIG. 3 is a schematic diagram of a typical delay chain or sensor used to simulate the operational circuit delay on an integrated circuit chip; 
     FIG. 4 is a block diagram of a timing generator which may be used in the load gate compensator shown in FIG. 1; 
     FIG. 5 is a timing diagram illustrating the operation of the timing generator shown in FIG. 4; 
     FIG. 6 is a circuit diagram of a binary or flip-flop which may be used in the timing generator shown in FIG. 4; 
     FIG. 7 is a circuit diagram of a typical two-input NOR gate which may be used in the timing generator shown in FIG. 4; 
     FIG. 8 is a circuit diagram of a voltage doubler circuit which may be used in the load gate compensator shown in FIG. 1; 
     FIG. 9 is a circuit diagram of a start-up control which may be used in the load gate compensator shown in FIG. 1; 
     FIG. 10 is a block diagram of an alternative timing generator and delay comparator; and 
     FIG. 11 is a timing diagram illustrating the operation of the alternative timing generator and delay comparator shown in FIG. 10. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description of the preferred embodiment, N-channel FET technology is assumed by way of illustration only and not limitation of the invention. Referring now to the drawings wherein like reference numerals designate identical or corresponding parts throughout the several figures, and more particularly, to FIGS. 1 and 2, there is shown a block diagram and a timing diagram, respectively, which illustrate the operation of the load gate compensator according to this invention. The timing generator 100 generates three pulses designated A, C and E that are required by the delay comparator 130. Pulse A whose pulse width is a function of the clock input repetition rate only, provides a time reference T REF . An output pulse B is obtained from the delay chain or sensor 120 on the integrated circuit chip. The time delay T d , between pulses A and B is a measure of the circuit delay in the chip. The delay comparator 130 detects whether T d  is greater or smaller than T REF  by sensing the absence or presence of an overlap between pulses A and B. 
     Each delay comparison cycle requires four clock cycles to complete the operation. First, node D in the delay comparator 130 is precharged during clock cycle 1. This is accomplished by applying the precharge pulse C to the gate electrode of FET 131. This causes FET 131 to conduct thereby precharging capacitor 132 to a voltage equal to the supply voltage, V DD , or the amplitude of pulse C minus the threshold voltage, V T , of the FET 131, whichever is lower. The A pulse comes during clock cycle 2 and is applied to the gate electrode of FET 133. The B pulse is applied to the gate electrode of FET 134 which has its drain connected to the source of FET 133. If the time delay through the delay chain 120 is less than T REF , the B pulse will overlap the A pulse as shown in clock cycle 2 in FIG. 2. This causes FETs 133 and 134 to conduct simultaneously resulting in the discharge of node D. The sampling pulse E is applied to the gate electrode of FET 135. During the sampling time, clock cycle 4, FET 135 is turned on, and the charge in capacitors 132 and 136 is redistributed. Since capacitor 132 is much larger than capacitor 136, the voltage across capacitor 136 will be very close to that of the voltage across capacitor 132 before it is sampled. As a result, node F will drop to near ground potential. Node F is connected to the gate electrode of FET 137 having a load FET 138 connected to its drain electrode. When node F drops to near ground potential, node G will rise. The output voltage at node G is supplied to a voltage doubler 140, and the rise in voltage at node G results in a decline in V LG  until T d  &gt; T REF . 
     When V LG  falls to a level such that T d  &gt; T REF , as illustrated in clock cycles 6 and 7 in the timing diagram of FIG. 2, the precharged node D will remain charged during the sampling time in clock cycle 8. Node F will rise, node G will fall, and V LG  will rise until T d  &lt; T REF . As a practical matter, it may take many delay comparison cycles to reverse the direction of V LG , especially if the time constant of the V LG  node is very large. The larger the time constant, the smaller the ripple V LG  wil have. 
     A typical delay chain 120 is illustrated in FIG. 3. The delay chain has eight stages of inverter in the test chip. Each inverter stage comprises an FET 121 with its associated load FET 122. The supply voltage V DD  is connected to the drains of each of the load FETs 122, while V LG  is connected to the gate electrodes of each of the load FETs 122. The requirements of the delay chain are that its nominal delay equal T REF  and that it contain an even number of stages. For better compensation, the delay chain should contain circuits and loadings that are typical of the operational circuit on the integrated circuit chip. The delay chain may be distributed across the integrated circuit chip so that it will sample the average circuit delay. 
     A simple implementation of the timing generator 100 is illustrated in FIGS. 4 and 5 of the drawings. The external clock reference is connected to inverter 101 to generate the clock signal C1. The clock signals C1 and C1 are connected to the two inputs of a first binary or flip-flop 102. The outputs, C2 and C2, are connected to the two inputs of binary 103. Binaries 102 and 103 constitute a two-stage binary counter which divides the clock pulse frequency as is shown in the timing diagrams C2 and C3 in FIG. 5. The C2 output of binary 102 and the C3 output of binary 103 are connected as two inputs of NOR gate 104 to produce the timing generator precharge pulse C. NOR gate 104 additionally receives as an input the output pulse B of delay chain 120. The purpose of connecting the output of delay chain 120 to the third input of NOR 104 is to eliminate the pulse spike that might occur at the output of NOR gate 104 during the beginning of clock cycle 3. In actuality, there is a delay between C3 and C2, as indicated by the dotted line in FIG. 5. As a result, both C2 and C3 are up for a short period of time during the beginning of clock cycle 3. Therefore, C2 and C3, the two inputs NOR gate 104, are down during that time, and this would cause a pulse spike to appear at the output of NOR gate 104 if it were not for pulse B holding down the output of the NOR gate. It should be noted that if the B pulse appears later in time, a pulse spike will be present at the output of the NOR gate 104; but this situation occurs only when T.sub. d &gt; T REF  and the pulse spike would not alter the operation of the system under that condition. The C2 output of binary 102 and the C3 output of binary 103 are connected to the two inputs of NOR gate 105 to generate the timing generator reference pulse A. Finally, the C2 output of binary 102 and the C3 output of binary 103 are connected to the two inputs of NOR gate 106 to produce the sample output pulse E of the timing generator. 
     It is essential to hold the width, the rise time, and the fall time of the timing generator reference pulse A close to a constant under any condition in order to minimize the delay tolerance. Therefore, as shown in FIG. 1 of the drawings, V LG  is supplied to the timing generator 100. This, in addition to accomplishing a minimum delay tolerance, will also reduce the power dissipation of the timing generator. T REF  is dependent on the period of the external clock pulse only. It is independent of the clock pulse rise time, fall time, and duty cycle; otherwise, additional delay tolerance would be introduced. 
     FIGS. 6 and 7 illustrate, respectively, typical circuit diagrams for the binaries and NOR gates shown in block diagram form in FIG. 4. Referring first to FIG. 6 and taking binary 102 as exemplary, a charging capacitor 107 is shown connected across the gate and source electrodes of FET 108. A load FET 109 is connected to the drain electrode of FET 108. The supply voltage V DD  is connected to the drain of load FET 109, while V LG  is connected to the gate electrode of load FET 109. The C1 input terminal of the binary 102 is connected to the gate electrode of FET 110 which is connected between the drain electrode of FET 108 and capacitor 111. Capacitor 111 is connected across the gate and source electrodes of FET 112. Connected to the drain electrode of FET 112 is a load FET 113 having the same voltage connections as load FET 109. The drain electrode of FET 112 is connected both to the gate electrode of FET 114 and the output terminal C2 of the binary 102. A third load FET 115 is connected to the drain electrode of FET 114. The drain electrode of FET 114 is connected both to the C2 output terminal of the binary 102 and through FET 116 to the capacitor 107. The second input terminal C1 is connected to the gate electrode of FET 116. 
     The operation of binary 102 will be appreciated by reference to the timing diagrams C1 and C2 shown in FIG. 5. It is initially assumed that there is no charge on capacitor 107 so that FET 108 is not conducting. When clock pulse C1 is up causing FET 110 to conduct, capacitor 111 will be charged through load FET 109. This causes FET 112 to conduct and FET 114 not to conduct. When clock pulse C1 is up, FET 116 conducts charging capacitor 107 through load FET 115. FET 108 is therefore biased into conduction, and when clock pulse C1 is up again capacitor 111 will discharge through FET 108. FET 112 will therefore be off, and FET 114 will be on. Thus, when C1 is up again, capacitor 107 will be discharged through FET 114 thereby completing the cycle. 
     The NOR gate 105 is illustrated in FIG. 7 and is exemplary of the NOR gates which may be used in the timing generator 100. It will be understood, of course, that a three-input NOR gate such as NOR gate 104 is an obvious extension of the circuit shown in FIG. 7. In FIG. 7, the C3 output of binary 103 is connected to the gate electrode of FET 117, while the C2 output of binary 102 is connected to the gate electrode of FET 118. FETs 117 and 118 share a common load FET 119. Again, the supply voltage V DD  is connected to the drain electrode of FET 119, while V LG  is connected to the gate electrode of FET 119. The output reference pulse A of the timing generator 100 is taken at the common junction of the drain electrodes of FETs 117 and 118. The output pulse A occurs only when both of the FETs 117 and 118 are not conducting, and this condition is satisfied only when both C3 and C2 are down. 
     A circuit which may be used as the voltage doubler 140 is shown in FIG. 8 of the drawings. This voltage doubler circuit needs an A.C. input to generate an output that is higher than the supply voltage. The A.C. input can be derived either from the external clock pulse or from an on-chip ring oscillator. This A.C. input is connected to the gate electrodes of FETs 141 and 142. The drain electrode of FET 142 is connected to the source electrode of FET 143, while the gate electrode of FET 143 is connected to the drain electrodes of FETs 141 and 144. The source electrodes of FETs 141, 142, and 144 are connected in common to ground, and the drain electrode of FET 143 is connected to a source of supply voltage V H . The drain electrodes of FETs 141 and 144 are also connected to the source electrode of FET 145. The drain electrodes of FETs 145 and 146 and the gate electrode of FET 146 are connected in common to the source of supply voltage. A capacitor 147 is connected between the source electrode of FET 145 and the common node J between the gate electrode of FET 145 and the source electrode of FET 146. 
     The circuit of the voltage doubler thus far described constitutes a push-pull driver stage having outputs at nodes J and H. The output taken at node H at the drain electrode of FET 142 is connected to the gate electrode of FET 148. The drain electrode of FET 148 is connected in common to node I with the source electrode of FET 149 and the drain electrode of FET 150. The source electrodes of FETs 148 and 150 are connected in common to ground. The drain electrodes of FETs 149 and 151 are connected in common to the source of supply V H . A second capacitor 152 is connected between node I and node K at the junction between the source electrodes of FET 151 and the gate electrode of FET 149. The gate electrode of FET 151 is connected to node J. FETs 148, 149, 150 and 151 constitute the output stage of the voltage doubler 140, and the output at node K is coupled through diode connected FET 153 to the V LG  terminal. Also connected to the V LG  terminal is the drain electrode of a FET 154. The gate electrodes of FETs 144, 150, and 154 are connected in common to the output node G of the delay comparator 130. A capacitor 155 is shown connected in shunt with the V LG   terminal and represents the load capacitance but may also include a filter capacitor for the purpose of minimizing ripple on V LG . 
     The push-pull driver stage of the voltage doubler 140 drives the output stage at nodes H and J. When the clock input is down, node H is up and node I is down. Since FET 141 is not conducting, node J rises above the supply voltage V H  because of the feedback capacitor 147. In the case when FET 144 is on, node J will rise to V H  minus V T , where V T  is the threshold voltage of FET 146. The very high gate voltage on FET 151 results in node K being charged to the supply voltage V H . When the clock input rises to the up level, node I will rise to V H  thereby pushing node K to nearly twice V H  through feedback capacitor 152. As a practical matter, however, it takes many cycles before V LG  can be charged to 2 V H  - V T  through the FET diode 153. Any leakage current at the V LG  terminal will, in addition, reduce the maximum level that it can reach. A positive voltage at node G will reduce V LG  by discharging the capacitance 155 and by limiting voltage swings at nodes J and K. 
     There are conditions under which V LG  may not be able to build up when power is turned on. The start-up control 160 shown in FIGS. 1 and 9 prevents this from happening. If the clock is not present when power is turned on, node F in the delay comparator 130 will be at a down level because the precharge pulse C and the sample pulse E from the timing generator 100 will not be present to charge node F up. Node G will therefore be up, and V LG  would be clamped down. If the clock is applied to the input of the timing generator 100 subsequently, no timing pulse will be generated because that circuit requires V LG  for its operation. Thus, the system would never start. With the start-up control 160, however, node G is clamped down until V LG  rises to an operating level. 
     The start-up control circuit is shown in FIG. 9 and comprises a FET 161 having its drain electrode connected to a load FET 162. The drain electrode of FET 161 is connected to the gate electrode of FET 163. The drain electrode of FET 163 is connected to node G of the delay comparator 130, while the source electrode of FET 163 is connected to ground. At start-up in the absence of output pulses from the timing generator 100, FET 161 is off and FET 163 is on clamping node G to ground. 
     A pulse detection circuit comprising FET 164, capacitor 165, FET 166, and capacitor 167 is connected between the source of supply voltage V DD  and the gate electrode of FET 161. The gate electrode of FET 164 is connected to receive the sample pulse E from the timing generator 100, and the gate electrode of FET 166 is connected to receive the reference pulse A. Before V LG  reaches an operating level, pulses E and A will not be present, and node M will be at a down level. As mentioned, this causes node N to be up, holding node G down and allowing V LG  to rise. After V LG  reaches an operating level, and if the clock is on, pulses A and E will occur in the sequence shown in FIG. 2. The charge will be transferred from the supply voltage V DD  to capacitor 165 and thence to capacitor 167 thereby biasing FET 161 into conduction and pulling N down and isolating the start-up control circuit 160 from node G. Thereafter, the load gate comparator will be operating in its normal manner. 
     Those skilled in the art will recognize that there are other and alternative ways of implementing the load gate compensator according to the teachings of the invention. One such alternative is illustrated in FIGS. 10 and 11 of the drawings. More specifically, FIG. 10 illustrates in block diagram form an alternative to the timing generator 100, delay chain 120, and delay comparator 130 shown in FIG. 1 of the drawings. It will be understood that the output of the delay comparator would be used to control V LG  as before. 
     In the alternative embodiment shown in FIG. 10, the timing generator comprises a frequency divider 170, such as a counter, and inverter 171, and an AND gate 172. The generator produces a gate pulse P and a reset pulse Q as illustrated in FIG. 11 of the drawings. The chain of the delay sensor is looped back to form an oscillator 174, and the frequency of the oscillation of oscillator 174 is a function of the circuit delay. A six-stage counter 173 is gated on by the gate pulse P to count the output of oscillator 174 and is reset by the reset pulse Q. The clock and the frequency divider 170 determine the time period which the counter 173 will count. The output of the first five stages of counter 173 are connected through OR gate 175 to one input of AND gate 176. The other input of AND gate 176 is connected to the inverted output of the last or sixth stage of counter 173. Counter 173, OR gate 175 and AND gate 176 constitute the delay comparator which will generate a chain of positive pulses if during each period the count is greater than a predetermined value, which in the specific example illustrated is 32. The count of 32 is chosen because it gives reasonable precision of control; a one-count error means approximately 3% error in delay. Obviously, other combinations of clock frequency, oscillator frequency and stages of counter will also work. The number of lines from the frequency divider 170 to the AND gate 172, which generate the reset pulse Q for the counter 173 depends on how many stages are in the frequency divider and how narrow the reset pulse one wishes to have. The output G of the delay comparator taken from the output of AND gate 176 is used exactly in the same way as in the load gate compensator illustrated in FIG. 1 of the drawings. 
     It is further noted that although the illustrated embodiments utilize N-channel technology, those skilled in the art could easily transform and utilize the concepts of the present invention in P-channel technology. It will therefore be apparent that the embodiments shown are only exemplary and that various modifications can be made in construction and arrangement within the scope of the invention as defined in the appended claims.