Abstract:
A charge pump includes a first switch coupled between a first voltage source and a first node, second switch coupled between the first node and a second node, a third switch coupled between the second node and a third node, the third node is for outputting from the charge pump. A fourth switch is coupled between the output node and a fourth node, a fifth switch is coupled between the fourth node and a fifth node, and a sixth switch is coupled between the fifth node and ground. A seventh switch is coupled between ground and the first node and an eighth switch is coupled between a second voltage source and the fifth node. A first capacitor is coupled between the second node and a first voltage signal and a second capacitor is coupled between the fourth node and a second voltage signal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to a charge pump utilized in a phase locked loop, and more particularly to a charge pump having fast turn on and turn off response times. 
         [0003]    2. Description of the Prior Art 
         [0004]    A charge pump can be an important component when utilizing a phase locked loop (PLL) to obtain a specific frequency. Commonly a phase and frequency detector (PFD) receives as input a reference frequency signals and a divided frequency signals outputted by a voltage controlled oscillator (VCO). The PFD outputs an UP signal if the phase of the reference frequency signal leads the phase of the divided frequency signal or outputs a DOWN signal if the phase of the divided frequency signal leads the phase of the reference frequency signal. 
         [0005]    The UP and DOWN signals are sent to control switches in the charge pump to cause the charge pump to act as a current source to a low pass filter or a current sink from the low pass filter according to the respective UP and DOWN signals. The positive or negative flow of current through the low pass filter controls the VCO to adjust its output frequency accordingly. The output of the VCO is transmitted through the frequency divider and back to an input of the PFD, completing the loop. The process continues until the phases of the reference frequency and the divided frequency are aligned. 
         [0006]    Therefore, to a great degree, the reduction of noise as well as the performance of the entire PLL depends upon the response speed of the charge pump to switch between outputting or sinking a constant current regardless of variable loads according to the received UP and DOWN signals. 
         [0007]    Please refer to  FIG. 1 , which shows a conventional charge pump  100  comprising a cascoded current mirror and switch on source node of a MOS switch. The current mirror is cascoded with high output impedance so that the current variation is less sensitive to the output voltage and retains a substantially constant current level regardless of loading. 
         [0008]    The charge pump  100  comprises a first row of cascoded switches P 7 , P 8 , and P 9  in order. The source of switch P 7  is coupled to VDD and the drain of switch P 9  is coupled to ground via a current source Icp. The gates of switches P 7 , P 8 , and P 9  are coupled to ground, a node F, and a first input voltage Vb 1  respectively. 
         [0009]    A second row of cascoded switches P 6 , P 3 , P 4 , N 3 , N 4 , and N 6  in order are also comprised by the charge pump  100  as are a third row of cascoded switches P 5 , P 1 , P 2 , N 1 , N 2 , and N 5  in order. The source of switches P 6  and P  5  are each coupled to VDD and the source of switches N 6  and N 5  are each coupled to ground. The gates of the second row of cascoded switches P 6 , P 3 , P 4 , N 3 , N 4 , and N 6  are coupled to ground, the node F, the first input voltage Vb 1 , a second input voltage Vb 2 , a node H, and VDD respectively. The gates of the third row of cascoded switches P 5 , P 1 , P 2 , N 1 , N 2 , and N 5  are coupled to a signal UPB, the node F, the first input voltage Vb 1 , the second input voltage Vb 2 , the node H, and a signal DN respectively. Node F is also coupled with a node G, which is in turn coupled between the drain of switch P 4  and the drain of switch N 3 . 
         [0010]    There are also capacitors C 1  formed between VDD and a node E, which is coupled to the NODE F, and C 2  formed between ground and the node H. The signals DN and UPB are derived from the UP and DOWN signals outputted by the PFD described earlier and are utilized to alternate the charge pump  100  between a current source and a current sink. UPB is an inverted version of the UP signal (UP BAR), so that when the signal UP goes from high to low, UPB goes from low to high and visa versa. 
         [0011]    Switches P 1 -P 9  function to cause the charge pump  100  to act as a current source and switches N 1 -N 5  function to cause the charge pump  100  to act as a current sink. In these embodiments, switches P 1 -P 9  are P-MOS transistors and switches N 1 -N 5  are N-MOS transistors but a reversal of these P and N characteristics and accompanying adjustments is to be considered well within the scope of the present invention and present in other embodiments. 
         [0012]    Please refer to  FIG. 2  in conjunction with  FIG. 1  for an example description of the operation of the charge pump  100 .  FIG. 2  is a timing diagram showing the relative voltages at the switches N 1  and N 2  as the charge pump  100  is switched from off state (no current flow out or in) to a current sink via the signal DN at the gate of switch N 5 . It should be noted that all indicated voltages and current values in  FIG. 2 ,  FIG. 4 , and  FIG. 6  are approximations given as examples only and actual results may vary depending on design considerations and manufacturing methods. 
         [0013]    As the diagram in  FIG. 2  shows, when the signal DN goes high, the switch N 5  is turned on and the node D will be dragged down to 0 volts. Because the gate voltage at switch N 2  maintains a relative high voltage, the voltage at the node D being reduced to 0 volts causes the switch N 2  to turn on. The voltage at the source of the switch N 1  then goes low because the switch N 2  is turned on, causing the switch N 1  to also turn on. With the switches N 5 , N 2 , and N 1  all turned on, the charge pump  100  sinks current from the node  1 , which may be coupled to a low pass filter, to ground. It should be apparent to one skilled in the art that a similar process is followed when the signal UPB goes from high to low at the gate of switch P 5  as the charge pump  100  converts from being a current sink to being a current source. 
         [0014]    The cascoded arrangement of the switches in the charge pump  100  essentially maintains a constant current level regardless of loading as desired. However, when the switch N 5  is turned off, the node D become floating, which makes the switch N 2  turn off very slow, which in turn causes the switch N 1  to also turn off slowly. Please notice the circled portions of three of the waveforms in  FIG. 2  that illustrate the slow rise of voltages at nodes D and C and the resulting very slow turn off of the output current from node  1 . This ripple effect of having a faster transistor turning on a slower transistor, which in turn turns on a yet slower transistor, gives slow response and introduces unwanted noise into the charge pump. 
       SUMMARY OF THE INVENTION  
       [0015]    It is therefore a primary objective of the claimed invention to provide a charge pump that maintains a substantially constant output current regardless of loading. 
         [0016]    It is a second primary objective of the claimed invention to reduce the response time when turning off the charge pump. 
         [0017]    It is a third primary objective of the claimed invention to reduce the response time when turning on the charge pump. 
         [0018]    A charge pump according to the claimed invention includes a first switch coupled between a first voltage source and a first node, and is controlled by a signal UPB. A second switch is coupled between the first node and a second node, a third switch is coupled between the second node and a third node, the third node for output from the charge pump. A fourth switch is coupled between the output node and a fourth node, a fifth switch is coupled between the fourth node and a fifth node, and a sixth switch coupled between the fifth node and ground and controlled by a signal DN. A seventh switch is coupled between ground and the first node and controlled by a signal UP which is opposite from the signal UPB and an eighth switch is coupled between a second voltage source and the fifth node and controlled by a signal DNB which is opposite from the signal DN. A first capacitor is coupled between the first node and the second node and a second capacitor is coupled between the fourth node and the fifth node. 
         [0019]    The capacitors effectively reduce the ripple delay when turning on the charge pump by allowing multiple cascoded switches to turn off and on approximately simultaneously while retaining the constant output current benefit of utilizing cascoded switches in the charge pump. 
         [0020]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a diagram of a conventional charge pump according to the present invention. 
           [0022]      FIG. 2  is a timing diagram of the operation of the charge pump of  FIG. 1 . 
           [0023]      FIG. 3  is a diagram of a charge pump according to the present invention. 
           [0024]      FIG. 4  is a timing diagram of the operation of the charge pump of  FIG. 3 . 
           [0025]      FIG. 5  is a diagram of another charge pump according to the present invention. 
           [0026]      FIG. 6  is a timing diagram of the operation of the charge pump of  FIG. 5 . 
           [0027]      FIG. 7  illustrates voltage and current waveform timing relationships for the charge pump of  FIG. 3 . 
           [0028]      FIG. 8  illustrates voltage and current waveform timing relationships for the charge pump of  FIG. 5 . 
           [0029]      FIG. 9  is a comparison diagram of the turn on speeds of the charge pumps in  FIG. 1 ,  FIG. 3 , and  FIG. 5 . 
           [0030]      FIG. 10  is a diagram of a third charge pump according to the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0031]    The first embodiment of the present invention is directed to speeding up the response of the charge pump  100  when the switch N 5  is turned off. Please refer to  FIG. 3  for an explanation. The charge pump  300  comprises virtually the same structure as does the charge pump  100  with similar components identified with the same labels. The difference between the charge pump  300  and the charge pump  100  is the addition of switches P 10  and N 7 . Switch P 10  may be a P-MOS transistor while switch N 7  may be an N-MOS transistor, but other variations are considered within the scope of the present invention. 
         [0032]    The drain of switch P 10  is coupled to ground and the source of switch P 10  is coupled to node A, which is situated between the drain of switch P 5  and the source of switch P 1 . The gate of switch P 10  is coupled to the UP signal, which is opposite to the UPB signal previously discussed. The drain of switch N 7  is coupled to VDD and the source of switch N 7  is coupled to node D, which is situated between the drain of switch N 5  and the source of switch N 2 . The gate of switch N 7  is coupled to a DNB signal, which is the same as DN BAR and is opposite to the DN signal previously discussed. 
         [0033]    Please refer to  FIG. 4  in conjunction with  FIG. 3  for an example description of the operation of the charge pump  300 .  FIG. 4  is a timing diagram showing the relative voltages at the switches N 1  and N 2  as the charge pump  300  is switched from off state to a current sink via the signal DN at the gate of switch N 5 . 
         [0034]    The diagram in  FIG. 4  shows that turning off the charge pump  300  is similar to turning off the charge pump  100  with the exception of improved response time due to the switch N 7 . As the circles in  FIG. 4  show, the voltage at node D becomes very high voltage during the off stage and makes sure the switch N 2  is turned off. The transition time to turn off is improved due to the switch N 7  rapidly pulling node D from 0 to high voltage. Please compare this with the same waveform in  FIG. 2 . The voltage ramping at node C at the source of switch N 1  is still relatively slow, however, there is a marked improvement in speed during turn off since the voltage at node D rises fast. Turn on operation of the charge pump  300  remains similar to that of the charge pump  100 . 
         [0035]    The charge pump  300  shows a decrease in response time required when turning off which may be viewed as an improvement over the charge pump  100 . However, the current at the drain of the switch N 1  turns on slower than the current at the drain of the switch N 2  as the turn on sequence shows when the switch N 5  turns on. The node D goes to 0 volts, and turns on the switch N 2 . After the switch N 2  turns on, the node C voltage goes low, which then turns on the switch N 1  to sink the current from node I. 
         [0036]    There is still a ripple delay between the switch N 5  being turned on and the switch N 1  being turned on, with each succeeding switch depending upon the status of previous switches in the cascoded chain of switches causing the delay. This delay occurs between faster nodes and slower nodes receiving suitable voltages. The relative terms “faster” and “slower” are intended to describe the order of receiving the appropriate voltage and not necessarily the speed at which the voltages are received. Examples in  FIG. 3  of a faster node and a slower node are node A being a faster node and node B being a slower node. The next embodiments of the present invention are directed to speed up the response of the charge pump  100  when the switch N 5  is turned on. 
         [0037]    Please refer now to  FIG. 5  that illustrates a charge pump  500  with an improved turn on speed. The charge pump  500  comprises virtually the same structure and definitions as does the charge pump  300  with similar components identified with the same labels. The difference between the charge pump  500  and the charge pump  300  is the addition of capacitors C 3  and C 4 . One terminal of capacitor C 4  is coupled to the node B (slower node) while the second terminal of capacitor C 4  is coupled to a first voltage signal which may be a node B (faster node) and is situated between the drain of switch P 1  and the source of switch P 2 . One terminal of capacitor C 3  is coupled to the node C (slower node) while the second terminal of capacitor C 3  is coupled to a second voltage signal which may be a node D (faster node) and is situated between the drain of switch N 2  and the source of switch N 1 . 
         [0038]    Please refer to  FIG. 6  in conjunction with  FIG. 5  for an example description of the operation of the charge pump  300 .  FIG. 6  is a timing diagram showing the relative voltages at the switches N 1  and N 2  as the charge pump  300  is switched from a current sink to a current source via the signal DN at the gate of switch N 5 . 
         [0039]    The diagram in  FIG. 6  shows that turning on the charge pump  500  is similar to turning on the charge pump  300  with the exception of improved response time due to the capacitor C 3 .  FIG. 6  illustrates the current sink case, too. The node D goes low at the turn on and goes high at the turn off moment due to the switch N 7 . The capacitor C 3  couples the node D signal as a pulse down signal at the turn on moment very instantly. This coupled signal assists node C to go to a lower voltage level faster than can the switch N 2  turning on to pull node C to low voltage. The turn off stage functions similarly with the capacitor C 3  pulling the node C up to a higher voltage quicker than the switch N 2  turning off. The results are shown in the  FIG. 6 . The circles in the timing diagram reveal the node D retains the fast rising edge seen in  FIG. 4 , and that the voltage at node C now shows a substantial increase in voltage rising speed due to the coupling of capacitor C 3 . The increased rising speed results in an even faster turn on and turn off speed of the output current than was achieved in  FIG. 4 . 
         [0040]    Please refer now to  FIG. 10  that illustrates a charge pump  1000  with a further improved turn on and off speed. The charge pump  1000  comprises virtually the same structure and definitions as does the charge pump  300  with similar components identified with the same labels. The difference between the charge pump  1000  and the charge pump  300  is again the addition of capacitors C 3  and C 4 . One terminal of capacitor C 4  is coupled to the node B (slower node) while the second terminal of capacitor C 4  is coupled to a first voltage source, which may be a control signal UP discussed previously. One terminal of capacitor C 3  is coupled to the node C (slower node) while the second terminal of capacitor C 3  is coupled to a second voltage source which may be the DNB (Down BAR) control signal discussed previously. This arrangement of the capacitors C 3  and C 4  allows the slower nodes B and C to respond directly to the UP and DNB control signals speeding response time even further. 
         [0041]    The capacitors C 3  and C 4  effectively reduce the ripple delay between faster nodes and slower nodes by allowing both the switches N 2  and N 1  to turn off and on approximately simultaneously according to the UP and DNB signals without any delay introduced by the faster nodes A and D respectively, while retaining the constant output current benefit of utilizing cascoded switches in the charge pump  500 . As can be readily seen to one skilled in the art, the embodiment depicted in  FIG. 10  shown a marked improvement in both turn on and turn off response time. 
         [0042]    The present invention utilizes rows of cascoded switches to form the core of a charge pump because the cascading of switches provides a relatively constant output current regardless of loading when compared to prior art single switched charge pumps. However, the cascading of the switches slows response time by introducing an unwanted ripple delay, as turning on or off a first switch is required before a next switch is turned on or off. The addition of switches respectively coupled between ground and a voltage source and the drains of the switches that determine whether the charge pump is to function as a current source of a current sink improves the response time when turning off the charge pump. The addition of the capacitors respectively coupling slower nodes with a voltage signal or coupled between faster and slower nodes decreases the response time both when turning on and off the charge pump. The addition of the capacitors respectively coupling slower nodes and the UP and DNB control signals maximally decreases the response time both when turning on and off the charge pump. The present invention presents a clear improvement over the prior art. 
         [0043]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.