Abstract:
An I/O driver comprising: a circuit adapted to be powered by a first power supply. The circuit is adapted to receive a first signal referenced to the voltage of a second power supply and is adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply. The circuit is adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to the field of integrated circuits; more specifically, it relates to input/output (I/O) driver circuits in integrated circuit chips having a power saving mode.  
         BACKGROUND OF THE INVENTION  
         [0002]    Power consumption of integrated circuit chips is a critical concern in many applications, for example, in portable devices such as lap-top computers and cell phones. In order to save power, integrated circuits used in power saving applications often include two or more power supplies, the normal chip power supply which may be powered down to save power and a alternative power supply that is powered at all times. However, when integrated circuit chips are in “power saving mode” they often still need to communicate with off chip devices.  
           [0003]    As the normal chip power supply voltage is powered down, it is necessary that unknown or “in-between” states not be propagated to off chip devices. Further, when the normal chip power supply is powered back up, it is again necessary that unknown or “in-between” states not be propagated to off chip devices.  
           [0004]    Therefore, the possibility of propagating errors between integrated circuits that may be placed in power saving mode and off chip devices is a problem of significant concern to designers of power saving mode chips.  
         BRIEF SUMMARY OF THE INVENTION  
         [0005]    A first aspect of the present invention is an I/O driver comprising: a circuit adapted to be powered by a first power supply, the circuit adapted to receive a first signal referenced to the voltage of a second power supply and adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply, the circuit adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.  
           [0006]    A second aspect of the present invention is An I/O driver comprising: a first circuit adapted to be powered by a first power supply, the first circuit adapted to receive a first signal referenced to the voltage of a second power supply and adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply; the first circuit including a first latching circuit, the first latching circuit adapted to maintain the logical state of the second signal when the second power supply is powered off; a second circuit adapted to be powered by the first power supply, the second circuit adapted to receive a third signal referenced to the voltage of the second power supply and adapted to convert the third signal to a fourth signal of the same logical value as the second signal and referenced to the voltage of the first power supply; the second circuit including a second latching circuit, the second latching circuit adapted to maintain the logical state of the fourth signal when the second power supply is powered off; and a combinational logic circuit adapted to combine the second and fourth signals into a fifth signal to maintain the fifth signal on an output of the I/O driver when the second power supply is powered off.  
           [0007]    A third aspect of the present invention is a method of maintaining the output state of an I/O driver when an integrated circuit chip is in a low power mode comprising: providing a circuit adapted to be powered by a first power supply, the circuit adapted to receive a first signal referenced to the voltage of a second power supply and adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply, the circuit adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.  
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0008]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0009]    [0009]FIG. 1 is a schematic diagram of an I/O driver circuit; and  
         [0010]    [0010]FIG. 2 is a schematic diagram of an I/O driver circuit according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]    VDDG is defined as a global voltage supplied to an integrated circuit chip that is powered off during power saving mode. VDDX (where X is an integer) is defined as an alternative voltage supplied to specific circuits that are kept powered during power saving mode. Fencing is defined as the operation of holding I/O pads of a integrated circuit chips in power saving mode at known voltage states while VDDG is off or sequencing on or off. In one example, VDDG is lower than VDDX. In another example VDDX is about 2.5 volts or higher and VDDG is 1.8 volts or lower.  
         [0012]    [0012]FIG. 1 is a schematic diagram of an I/O driver circuit. In FIG. 1, I/O driver  100  includes a TS input, an A input, a PAD output, an inverter I 1 , a first level shifter  105 , a second level shifter  110 , a NAND gate  115 , a NOR gate  120  and output circuit  125 . Input TS is coupled to an input of inverter I 1 . Inverter I 1  is coupled to VDDG. The output of inverter I 1  is coupled to an input of first level shifter  105 . A first output of first level shifter  105  is coupled to a first input of NAND gate  115  and a second output of first level shifter  105  is coupled to a first input of NOR gate  120 . NAND gate  115  and NOR gate  120  are each coupled to VDDX. Input A is coupled to an input of second level shifter  110 . An output of second level shifter  110  is coupled to a second input of NAND gate  115  and to a second input of NOR gate  120 . The output of NAND gate  115  is coupled to a first input of output circuit  125  and the output of NOR gate  120  is coupled to a second input of output circuit  125 . The output of output circuit  125  is coupled to output PAD.  
         [0013]    First level shifter  105  includes PFETs T 1  and T 2 , NFETs T 3  and T 4  and inverter I 2 . The sources of PFETs T 1  and T 2  are coupled to VDDX and the drains of PFETs T 1  and T 2  are coupled respectively to nodes XX and YY. Node XX is coupled to a first output of first level shifter  105  and node YY is coupled to a second output of level shifter  105 . The gate of PFET T 1  is coupled to node YY and the gate of PFET T 2  is coupled to node XX. The drain of NFET T 3  is coupled to node XX and the drain of NFET T 4  is coupled to node YY. The sources of NFETs T 3  and T 4  are coupled to ground. The gate of NFET T 3  and the input of inverter I 2  are both coupled to the input to level shifter  105 , which is coupled to the output of inverter I 1  as described supra. Inverter I 1  is coupled to VDDG. Node XX is coupled to the first input of NAND gate  115  and node YY is coupled to the first input of NOR gate  120 .  
         [0014]    Second level shifter  110  is similar to first level shifter  105 . Second level shifter  110  include PFETs T 5  and T 6 , NFETs T 7  and T 8  and inverter I 3 , wherein PFETs T 5  and T 6 , NFETs T 7  and T 8  and inverter I 3  of second level shifter  110  correspond respectively to PFETs T 1  and T 2 , NFETs T 3  and T 4  and inverter I 2  of first level shifter  105 . Nodes X and Y of second level shifter  110  correspond respectively to nodes XX and YY of first level shifter  105 . The differences being the gate of NFET T 7  and the input of inverter I 3  are both coupled to input A and node Y is coupled to the second input of NAND gate  115  and node Y is coupled to the second input of NOR gate  120 .  
         [0015]    Output circuit  125  includes a PFET T 9  and an NFET T 10 . The source of PFET T 9  is coupled to VDDX and the source of NFET T 10  is coupled to ground. The drains of PFET T 9  and NFET T 10  are coupled to each other and to the output of output circuit  125 , which is coupled to output PAD as described supra. The gate of PFET T 9  is coupled to the first input of output circuit  125 , which is coupled to the output of NAND gate  115  as described supra. The gate of NFET T 10  is coupled to the second input of output circuit  125 , which is coupled to the output of NOR gate  120  as described supra.  
         [0016]    In operation input TS receives a mode signal referenced to a voltage VDDG (or another voltage) indicating the mode of I/O driver  100 . A logical 1 indicates normal function mode and a logical 0 indicates a tri-state mode. Input A receives a data signal referenced to VDDG (or another voltage) that is either a logical 0 or a logical 1. Both the mode signal and the data signal are level shifted from the voltage they are received at to VDDX, the mode signal shifted by first level shifter  105  and the data signal shifted by second level shifter  110 .  
         [0017]    In a first scenario, with VDDG on, and a mode signal that is a logical 1 (normal mode) on input TS, NFET T 3  is off, PFET T 1  is on, node XX is at a logical 1, NFET T 2  is on, PFET T 2  is off, and node YY is at a logical 0. With a logical 0 data signal on input A, NFET T 7  is off, PFET T 5  is on, node X is at a logical 1, NFET T 8  is on, PFET T 6  is off and node Y is at a logical 0. With node XX at a logical 1, node YY at a logical 0 and node Y at a logical 0, the signal at output PAD is at a logical 0, the same as input A.  
         [0018]    In a second scenario, with VDDG on, and a mode signal that is a logical 1 (normal mode) on input TS, NFET T 3  is off, PFET T 1  is on, node XX is at a logical 1, NFET T 2  is on, PFET T 2  is off, and node YY is at a logical 0. With a lobical 1 data signal on input A, NFET T 7  is on, PFET TS is off, node X is at a logical 0, NFET T 8  is off, PFET T 6  is on and node Y is at a logical 1. With node XX at a logical 1, node YY at a logical 0 and node Y at a logical 1, the signal at output PAD is at a logical 1, the same as input A.  
         [0019]    In a third scenario, with VDDG on, and a mode signal that is a logical 0 (tri-state mode) on input TS, NFET T 3  is on, PFET T 1  is off, node XX is at a logical 0, NFET T 4  is off, PFET T 2  is on, and node YY is at a logical 1. With node XX at a logical 0, node YY at a logical 1, regardless of the state of nodes X and Y, NAND gate  115  at a logical 1, NOR gate  120  is at a logical 0 and both PFET T 9  and NFET T 10  are off and the signal at output PAD is floating or unknown.  
         [0020]    In a fourth scenario, which includes first and second scenarios, VDDG is powered down (VDDX is still on), the chip is in power saving mode(VDDG=0). With VDDG off the outputs of inverters I 1  and I 2  are zero turning both NFETs T 3  and T 4  off so nodes XX and YY are unknown or floating which in turn causes output PAD to be unknown or floating. Therefore, in power saving mode, the state of the output PAD is lost and may or may not be recovered after VDDG is powered back up.  
         [0021]    [0021]FIG. 2 is a schematic diagram of an I/O driver circuit according to the present invention. In FIG. 2, I/O driver  200  includes a TS input, an A input, a FENCEN input, a PAD output, an inverter I 4 , a first level shifter  205 , a second level shifter  210 , a NAND gate  215 , a NOR gate  220  and output circuit  225 . Output PAD is coupled to an I/O pad of an integrated circuit chip containing I/O driver  200 . Input TS is coupled to an input of inverter I 4 . Inverter I 4  is coupled to VDDG. The output of inverter I 4  is coupled to a first input of first level shifter  205 . Input FENCEN is coupled to a second input of first level shifter  205 . A first output of first level shifter  205  is coupled to a first input of NAND gate  215  and a second output of first level shifter  205  is coupled to a first input of NOR gate  220 . NAND gate  215  and NOR gate  220  are each coupled to VDDX. Input A is coupled to a first input of second level shifter  210 . Input FENCEN is coupled to a second input of second level shifter  210 . A first output of second level shifter  210  is coupled to a second input of NAND gate  215  and a second output of second level shifter  210  is coupled to a second input of NOR gate  220 . The output of NAND gate  215  is coupled to a first input of output circuit  225  and the output of NOR gate  220  is coupled to a second input of output circuit  225 . The output of output circuit  225  is coupled to output PAD.  
         [0022]    First level shifter  205  includes PFETs T 11  and T 12 , NFETs T 13 , T 14 , T 21 , T 22 , T 23  and T 24  and inverter I 5 . The sources of PFETs T 11  and T 12  are coupled to VDDX and the drains of PFETs T 11  and T 12  are coupled respectively to nodes XX and YY. Node XX is coupled to a first output of first level shifter  205  and node YY is coupled to a second output of level shifter  205 . The gate of PFET T 11  is coupled to node YY, the gate of NFET T 23  and the drain of NFET T 24 . The gate of PFET T 12  is coupled to node XX, the gate of NFET T 24  and the drain of NFET T 23 . The drain of NFET T 13  is coupled to node XX and the drain of NFET T 14  is coupled to node YY. The sources of NFETs T 13  and T 14  are coupled to the drains of NFETs T 21  and T 22  respectively. The sources of NFETs T 21  and T 22  are each coupled to ground. The gate of NFET T 13  and the input of inverter I 5  are both coupled to the input of level shifter  205 , which is coupled to the output of inverter I 4  as described supra. Inverter I 4  is coupled to VDDG. Node XX is coupled to the first input of NAND gate  215  and node YY is coupled to the first input of NOR gate  220 .  
         [0023]    Second level shifter  210  is similar to first level shifter  205 . Second level shifter  210  include PFETs T 15  and T 16 , NFETs T 17 , T 18  and T 25 , T 26 , T 27  and T 28  and inverter I 6 , wherein PFETs T 15  and T 16 , NFETs T 17 , T 18  and T 25 , T 26 , T 27  and T 28  and inverter I 6  of second level shifter  210  correspond respectively to PFETs T 11  and T 12 , NFETs T 13 , T 14 , T 21 , T 22 , T 23  and T 24  and inverter I 5  of first level shifter  205 . Nodes X and Y of second level shifter  210  correspond respectively to nodes XX and YY of first level shifter  205 . The differences being the gate of NFET T 17  and the input of inverter I 6  are both coupled to input A and node Y is coupled to the second input of NAND gate  215  and to the second input of NOR gate  220 .  
         [0024]    Output circuit  225  includes a PFET T 19  and an NFET T 20 . The source of PFET T 19  is coupled to VDDX and the source of NFET T 20  is coupled to ground. The drains of PFET T 19  and NFET T 20  are coupled to each other and to the output of output circuit  225 , which is coupled to output PAD as described supra. The gate of PFET T 19  is coupled to the first input of output circuit  225 , which is coupled to the output of NAND gate  215  as described supra. The gate of NFET T 20  is coupled to the second input of output circuit  225 , which is coupled to the output of NOR gate  220  as described supra.  
         [0025]    In operation input TS receives a mode signal referenced to a voltage VDDG (or another voltage) indicating the mode of I/O driver  200 . A lobical 1 indicates normal function mode and a logical 0 indicates a tri-state mode. Input A receives a data signal referenced to VDDG (or another voltage) that is either a logical 0 or a logical 1. Both the mode signal and the data signal are level shifted from the voltage they are received at to VDDX, the mode signal by first level shifter  205  and the data signal by second level shifter  210 . When input FENCEN receives a fencing signal that is a logical 1 (fencing off) NFETs T 21 , T 22  T 25  and T 26  turn on and circuit operation proceeds normally. When input FENCEN receives a fencing signal that is a logical 0 (fencing on, prior to going into power saving mode) NFETs T 21 , T 22  T 25  and T 26  turn off and the logical value of the signal on input TS are latched by NFETs T 23  and T 24  and the logical value of the signal on input A is latched by NFETs T 27  and T 28  as described infra. The fencing signal is received at input FENCEN before VDDG is powered off. FENCEN is referenced to a backup power supply VDDBU. FENCEN remains at a logical 0 when VDDG is powered down.  
         [0026]    In a first scenario, with VDDG on, a mode signal that is a lobical 1 (normal mode) on input TS and a fencing signal that is a lobical 1 (no fencing) on input FENCEN, NFETs T 21 , T 22 , T 25  and T 26  are on, NFET T 13  is off, PFET T 11  is on, node XX is at a logical 1, NFET T 12  is on, PFET T 12  is off, and node YY is at a logical 0. With a logical 0 data signal on input A, NFET T 17  is off, PFET T 15  is on, node X is at a logical 1, NFET T 18  is on, PFET T 16  is off and node Y is at a logical 0. With node XX at a logical 1, node YY at a logical 0 and node Y at a logical 0, the signal at output PAD is at a logical 0, the same as input A.  
         [0027]    In a second scenario, with VDDG on, a mode signal that is a lobical 1 (normal mode) on input TS and a fencing signal that is a lobical 1 (no fencing) on input FENCEN, NFETs T 21 , T 22 , T 25  and T 26  are on, NFET T 13  is off, PFET T 11  is on, node XX is at a logical 1, NFET T 12  is on, PFET T 12  is off, and node YY is at a logical 0. With a lobical 1 data signal on input A, NFET T 17  is on, PFET T 15  is off, node X is at a logical 0, NFET T 18  is off, PFET T 16  is on and node Y is at a logical 1. With node XX at a logical 1, node YY at a logical 0 and node Y at a logical 1, the signal at output PAD is at a logical 1, the same as input A.  
         [0028]    In a third scenario, with VDDG on, and a mode signal that is a logical 0 (tri-state mode) on input TS and a fencing signal that is a logical 1 (no fencing) on input FENCEN, NFETs T 21 , T 22 , T 25  and T 26  are on, NFET T 13  is on, PFET T 11  is off, node XX is at a logical 0, NFET T 14  is off, PFET T 12  is on, and node YY is at a logical 1. With node XX at a logical 0, node YY at a logical 1 both and node Y at a logical 1, both PFET T 19  and NFET T 20  are off and the signal at output PAD is floating or unknown.  
         [0029]    In a fourth scenario, which includes first and second scenarios, input TS is at a logical 1, then VDDG is powered down (VDDX is still on), the chip is put in power saving mode (VDDG=0), fencing is turned on (input FENCEN is at a logical 0) and then the logical state of input TS floats. With fencing turned on NFETs T 21 , T 22 , T 25  and T 26  are turned off. NFETs T 23  and T 24  hold nodes XX and YY at the logical values set by the state of input TS before VDDG was powered down (either NFET T 23  and PFET T 12  are on and NFET T 24  and PFET T 11  are off or NFET T 23  and PFET T 12  are off and NFET T 24  and PFET T 11  are on). NFETs T 27  and T 28  hold node Y at the logical value set by the state of input A before VDDG was powered down (either NFET T 27  and PFET T 16  are on and NFET T 28  and PFET T 15  are off or NFET T 273  and PFET T 162  are off and NFET T 28  and PFET T 15  are on). With nodes XX, YY and Y “latched” the logical value at output PAD is held at the state of input A before VDDG was powered down. VDDG is powered back up before fencing is turned off. The turning of fencing off (FENCEN back to a logical 1) is timed to occur (at the system level) when the signal on input A is the same as before VDDG was powered down to avoid “glitching” (primarily a clocking problem) and one of normal skill in the art may design a glitch preventing circuit keeping in mind that it may be necessary for that glitch preventing circuit to be powered by VDDX.  
         [0030]    Thus, the present invention provides a need for an I/O driver circuit communicating between integrated circuits that may be placed in power saving mode and off chip devices that does not propagate unknown or “in-between” states to off chip devices during power down or power up.  
         [0031]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.