Abstract:
An oversampling digital/analog (D/A) converter is provided that has a reduced circuit area and an improved dynamic range of a converted voltage signal. The oversampling D/A converter includes an interpolation filter that receives a digital signal and oversamples the digital signal to provide a multibit digital signal. A digital noise shaper quantizes a noise contained in the digital signal passed through the interpolation filter, and an IFIR (Interpolated Finite Impulse Response) reconstruction filter converts a noise shaped digital signal in an analog signal corresponding to the noise shaped digital signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital/analog converter, and more particularly, to an oversampling digital/analog converter using an Interpolated Finite Impulse Response (IFIR) filter. 
     2. Background of the Related Art 
     A related art oversampling digital/analog converter will now be described. FIG. 1 illustrates a system block diagram of the related art digital/analog converter (DAC). A sigma delta DAC is generally used as a digital/analog converter. 
     Referring to FIG. 1, related art the sigma delta digital/analog converter includes an interpolation filter  11 , a digital noise shaper  12  and an FIR reconstruction filter  13 . The interpolation filter  11  receives a multibit digital word of first sampling frequency and converts it to a multibit digital word of a second sampling frequency higher than the first sampling frequency. The second sampling frequency multibit digital word is then converted into a single-bit word in the digital noise shaper  12 . The single-bit quantization used for the conversion in the digital noise shaper  12  shifts a quantization noise from a low frequency band to a high frequency band (noise shaping). The FIR reconstruction filter  13  has low pass filters, which either have a switch-capacitor or have a resistor and a capacitor. The low pass filter with the switch-capacitor, which has a non-linear phase response, is embodied as a CMOS integrated circuit. The low pass filter with the resistor and the capacitor provides a wider dynamic range, but it requires a precise matching between components for precise filtering. 
     FIG. 2 illustrates a related art Finite Impulse Response (FIR) type reconstruction filter. Referring to FIG. 2, the related art FIR type reconstruction filter includes a plurality of one bit shift registers SR 1 , SR 2 , SR 3 , . . . , SRn connected in series, a plurality of current sources CS 1 , CS 2 , CS 3 , . . . , CSn that each supply a respective current to an I-V converter part  21  or drain the respective current to ground in response to a signal from the shift register SR 1 , SR 2 , SR 3 , . . . , SRn. The I-V converter part  21  converts the selectively received current depending on respective outputs of the shift registers SR 1 , SR 2 , SR 3 , . . . , SRn to a voltage. 
     The operation of the related art oversampling digital/analog converter will now be described. First, the related art oversampling digital/analog converter subjects a one bit data stream to low-pass filtering using a FIR semi-digital reconstruction filter and subjects a resulting current to I-V conversion. That is, as shown in FIGS. 1 and 2, a noise shaped digital data provided to the FIR reconstruction filter  13  is converted into an analog signal. In other words, the noise shaped digital data stream is provided to the shift registers SR 1 , SR 2 , . . . , SRn in the FIR reconstruction filter  13 . If the shift register provides a data “0”, the current from a current source of the shift register is connected to ground. For example, if the first shift register SR 1  provides a data “1”, the second shift register SR 2  provides a data “0” and the third shift register SR 3  provides a data “1”, paths of the first and third current sources CS 1  and CS 3  are established toward the I-V converter part  21  and a path of the second current source CS 2  is established to the ground. Therefore, the currents from the first current source CS 1  and the third current source CS 3  are together provided to the I-V converter part  21 . The I-V converter part  21  converts the received current into a voltage corresponding to the digital data stream received at the shift registers. In this instance, to convert the digital data into a voltage corresponding to the digital data with more precision, more current sources are required. That is, the more orders the filter is extended, the more exact the analog output can be obtained. 
     In summary, as shown in FIG. 1, digital data is provided to the FIR reconstruction filter  13  through the interpolation filter  11  and the digital noise shaper  12 . The FIR reconstruction filter  13  subjects the digital data to low pass filtering according to a transmission function. The transmission function of the FIR reconstruction filter can be expressed as equation 1 as follows. 
     
       
           H ( Z )= a   1   z   −1   +a   2   z   −2   +, . . . , a   n   z   −n   (1)  
       
     
     Therefore, when the noise shaped digital data is passed through the FIR reconstruction filter  13 , a high frequency component in the noise shaped digital data is removed, which leaves a baseband signal. 
     However, as described above the related art oversampling digital/analog converter has various problems. First, the high order of FIR reconstruction filter required for conversion of a signal from digital to analog results in an increase of occupied area due to the filter system. Second, the error in a filter coefficient caused by process change coming from increased order degrades a filter performance. Third, the current to the I-V converter part being at least greater than “0” at the minimum and smaller than a sum of all current sources at the maximum places a limitation on a dynamic range of the converted voltage signal. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a digital/analog converter that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art. 
     Another object of the present invention is to provide a digital/analog converter that occupies a reduced area. 
     Another object of the present invention is to provide a digital/analog converter that has an increased dynamic range of a converted voltage signal. 
     To achieve at least these objects and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, an over sampling digital/analog converter includes an interpolation filter that receives a digital signal and oversamples the digital signal to generate a multibit digital signal; a digital noise shaper that quantizes noise in the multibit digital signal to output a noise shaped digital signal; and an Interpolated Finite Impulse Response (IFIR) reconstruction filter that converts the noise shaped digital signal to a corresponding analog signal. 
     To further achieve the above objects in a whole or in part, there is provided a digital/analog converter according to the present invention that includes a plurality of shift registers coupled in series that receive a noise shaped digital signal; a plurality of current sources, wherein each of the current sources is connected to an output terminal of a unit of the shift registers, wherein each unit comprises more than one shift register; and an I-V converter part that selectively receives currents from the current sources based on an output signal from a corresponding unit, wherein the I-V converter part converts the received currents to a voltage. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein: 
     In the drawings: 
     FIG. 1 is a block diagram showing a related art oversampling digital/analog converter; 
     FIG. 2 is a diagram showing a related art FIR reconstruction filter; 
     FIG. 3 is a diagram showing an oversampling digital/analog converter in accordance with a preferred embodiment of the present invention; 
     FIG. 4 is a diagram that illustrates an IFIR reconstruction filter in accordance with a preferred embodiment of the present invention; and, 
     FIGS.  5   a  to  5   c  are diagrams that illustrate operation timing waveforms of the IFIR reconstruction filter of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     As shown in FIG. 3, an oversampling digital/analog converter in accordance with a preferred embodiment of the present invention includes an interpolation filter  11 , a digital noise shaper  12  and an Interpolated Finite Impulse Response (IFIR) reconstruction filter  31 . FIG. 4 is a diagram that illustrates a preferred embodiment of a system of the IFIR reconstruction filter  31  in accordance with the present invention. 
     As shown in FIG. 4, the preferred embodiment of the IFIR reconstruction filter  31  includes a plurality of one bit shift registers SR 1 , SR 2 , SR 3 , . . . , SRn coupled in series, and a plurality of current sources CS 1 , CS 2 , . . . , CSn respectively supplying a current to an I-V converter part or draining the current to ground. The plurality of current sources CS 1 , CS 2 , . . . , CSn preferably supply or drain the corresponding current in response to a signal from an even numbered shift register SR 2 , SR 4 , . . . , SRn. The I-V converter part  21  converts a plurality of the currents selectively received from the current sources CS 1 , CS 2 , CS 3 , . . . , CSn to a voltage. 
     Preferably, a DC-offset correcting part  41  by-passes a prescribed amount of the current source to correct a dynamic range of an output voltage of the I-V converter  21 . Depending on an output of one unit of the shift registers SR 1 , SR 2 , . . . , SRn, which is preferably two shift registers, a corresponding source current CS 1 , CS 2 , CS 3 , . . . , CSn may or may not be coupled to an input terminal on the I-V converter part  21 . Thus, a number of the current sources is preferably one half of a number of the shift registers. However, the present invention is not intended to be so limited. For example, even though one switching part is preferably coupled to every two one bit shift registers in the preferred embodiment, one switching part can be coupled to more than two one bit shift registers. 
     Operations of the preferred embodiment of the IFIR filter  31  in accordance with the present invention will now be described. As shown in FIG. 3, when a noise shaped digital data is provided to the IFIR reconstruction filter  31 , the IFIR filter  31  provides an analog signal corresponding to the digital data. In other words, the noise shaped digital data from the digital noise shaper  12  is provided to the plurality of one bit shift registers or a shift register in the IFIR reconstruction filter  31 . Since the shift registers are operative by two as one unit, a corresponding source current is provided either to the I-V converter part  21  or to the ground terminal preferably depending on an output of every second shift register. Thus, the corresponding current source CS 1 , CS 2 , CS 3 , . . . , CSn is coupled to the I-V converter part  21  if the one bit shift registers SR 2 , SR 4 , . . . , SRn respectively have an output data “1” and to the ground terminal if the one bit shift register SR 2 , SR 4 , . . . , SRn has an output data “0”. 
     For example, assume the second shift register SR 2  has an output data “1”, the fourth shift register SR 4  has an output data “0”, and the sixth shift register SR 6  has an output data “1.” As the output data from the second and sixth shift registers SR 2  and SR 6  are “1”, the currents from the first and third current sources are coupled to the I-V converter part  21 . As the output data from the fourth shift register SR 4  is “0”, the second current source is coupled to the ground terminal. Accordingly, the currents from the first current source CS 1  and the third current source CS 3  are provided together to the I-V converter part  21 . The operation of the IFIR filter  31  of the preferred embodiment can be expressed by a general IFIR filter transmission function of equation 2 as follows: 
     
       
           H ( Z )= a   1   z   −2   +a   2   z   −4   +, . . . , a   n   z   −2n   (2)  
       
     
     The currents passed through the IFIR filter  31  and provided to the I-V converter part  21  are converted into a voltage signal. An image band that occurred when the signal passes through the IFIR filter is converted into a voltage signal, and at the same time low pass-filtered in the I-V converter part  21 . 
     FIGS.  5   a  to  5   c  illustrate operation timing diagrams of the preferred embodiment of the IFIR reconstruction filter  31  according to the present invention. FIG.  5   a  illustrates a required filter response signal. As shown in FIG.  5   b,  when a preferred embodiment of an IFIR filter according to the present invention is extended as compared to the related art, the required filter response signals as well as not required filter response signals are obtained at the same time. However, as shown in FIG.  5   c,  the response signal that is not required is eliminated by the I-V converter part  21 , which converts the current source into a voltage signal. In the meantime, as shown in FIG. 4, the DC-offset correcting part  41  preferably subtracts a half of a maximum current I out.max  before the current is converted into a voltage. The ½ I out.max  is subtracted from the current to preferably make the current provided to the I-V converter part  21  fall on a range of −½ I out.max &lt;I out &lt;½ I out.max  according to the preferred embodiment, which increases a dynamic range of the voltage signal converted by the I-V converter part  21  two times. 
     As described above, an oversampling digital/analog converter according to the preferred embodiment of the present invention has various advantages. A number of current sources may be reduced (e.g., by ½, 1/n or the like) using an IFIR filter having one switching part for every “n” shift registers. A DC-offset correcting part extends a dynamic range of the converted voltage signal and improves an S/N ratio. Further, reducing a number of current sources reduces or minimizes a chip area, and a simple IFIR filter structure of the preferred embodiments easily makes the IFIR filter operative at a low voltage. Accordingly, a digital/analog converter with improved performance characteristics is provided. In addition, the use of the IFIR filter according to the preferred embodiments that reduces the number of current sources is less sensitive to a filtering band characteristic variation, which prevents degradation of the digital/analog converter performance caused by degradation of matching in fabrication of a semiconductor device. 
     The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.