Abstract:
The subject invention reveals a new coupled inductor boost converter which achieves zero voltage turn on switching for all four circuit switches. The coupled inductor of the circuit is fully clamped and thereby achieves excellent noise performance with neither snubbers nor clamps. The new coupled inductor boost converter is outstanding for isolated high voltage applications because the voltage stress of the secondary switches does not exceed the output voltage, it requires only one magnetic circuit element, and the average voltage stress of the secondary winding is equal to or less than half the output voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of PPA Ser. No. 60/766,547, filed 2006 January 26 by the present inventor. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The subject invention generally pertains to electronic power conversion circuits, and, more specifically, to high frequency, switched mode electronic power converters. The subject matter relates to new isolated power converters which achieve higher efficiency at high and medium output voltages compared to prior art power converters. 
   2. Description of Related Art 
   The solution to the problem of converting power efficiently to high voltage loads has frequently relied on solutions that resemble the solutions typically used for medium and low voltages. Often a power conversion circuit such as a ZVS flyback converter, as illustrated in  FIG. 1 , is used to generate a relatively high voltage and the desired higher load voltage is generated with a chopper and a diode capacitance multiplier. The number of stages, efficiency, and complexity of the diode capacitance multiplier depends on the starting voltage, so it is important to generate as high a starting voltage as possible. In  FIG. 1  the limiting factor to generating higher voltage is the voltage stress of D REC . In  FIG. 1  the voltage stress of D REC  is typically at least 2 times the output voltage, and the secondary winding stress of L MAIN  is typically equal to or larger than the output voltage, depending largely on the line voltage range. What is needed is a simple high efficiency power converter that can generate higher voltages efficiently with a minimum of component voltage stress. 
   OBJECTS AND ADVANTAGES 
   An object of the subject invention is to reveal a new beneficial power conversion circuit for applications with medium and high output voltage. 
   Further objects and advantages of my invention will become apparent from a consideration of the drawings and ensuing description. 
   These and other objects of the invention are provided by a novel circuit that limits voltage stress of the power converter&#39;s secondary side switches and reduces overall component stress factors compared to the prior art. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by reference to the drawings. 
       FIG. 1  illustrates a zero voltage switching (ZVS) active clamp flyback converter according to the prior art. 
       FIG. 2  illustrates a ZVS isolated coupled inductor boost converter with synchronous rectifiers according to the subject invention. 
       FIG. 3  illustrates a ZVS isolated coupled inductor boost converter with diode rectifiers according to the subject invention. 
       FIG. 4  illustrates a double switch reconfiguration of the  FIG. 2  circuit according to the subject invention. 
       FIG. 5(   a ) illustrates a voltage wave form for the M 1  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   b ) illustrates a voltage wave form for the M 2  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   c ) illustrates a voltage wave form for the M 3  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   d ) illustrates a voltage wave form for the M 4  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   e ) illustrates a current wave form for the M 1  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   f ) illustrates a current wave form for the M 2  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   g ) illustrates a current wave form for the M 3  switch of  FIG. 2  according to the subject invention. 
       FIG. 5(   h ) illustrates a current wave form for the M 4  switch of  FIG. 2  according to the subject invention. 
       FIG. 6  illustrates a ZVS coupled inductor boost converter according to the subject invention. 
       FIG. 7  illustrates a ZVS coupled inductor boost converter with a diode capacitance multiplier according to the subject invention. 
   

   SUMMARY 
   The subject invention reveals a new isolated ZVS coupled inductor boost converter which relies on leakage inductance of the coupled inductor to drive a zero voltage turn on switching transition for the main switch. The circuit requires only a single magnetic circuit element plus two active primary side switches and two secondary side rectifiers. The circuit achieves lower component stress, lower electromagnetic interference, and higher efficiency compared to other alternatives for high voltage applications. 
   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 6  illustrates a ZVS coupled inductor boost power converter according to the subject invention. A first terminal of an input source of dc power and voltage is connected to a first terminal of a capacitor C RESET  and to a dotted terminal of a primary winding of a coupled inductor L MAIN  which has a substantial amount of leakage inductance and leakage flux due to its construction. A second terminal of the input source of dc power and voltage is connected to a first terminal of a switch S 1 . A second terminal of switch S 1  is connected to a first terminal of a switch S 2  and to an undotted terminal of primary winding of coupled inductor L MAIN . A second terminal of switch S 2  is connected to a second terminal of capacitor C RESET . A first terminal of a capacitor C SEC  is connected to a dotted terminal of a secondary winding of coupled inductor L MAIN . A second terminal of capacitor C SEC  is connected to a first terminal of a switch S 3 , to a first terminal of a capacitor C OUT , and to a first terminal of a load R LOAD . A second terminal of switch S 3  is connected to a first terminal of a switch S 4  and to an undotted terminal of the secondary winding of coupled inductor L MAIN . A second terminal of switch S 4  is connected to a second terminal of capacitor C OUT  and to a second terminal of load R LOAD . 
   In operation the circuit has two operating states with dead times between operating states which are brief by comparison to the duration of the operating states. For purposes of analysis we will assume that the circuit has reached a steady state condition. We will also assume that the capacitors are sufficiently large that the capacitor voltages are invariant over a single operating cycle. During a first operating state switches S 1  and S 3  are on (conducting) and switches S 2  and S 4  are off (non-conducting). Current flows in a primary loop comprising the input source of dc voltage and power, the primary winding of coupled inductor L MAIN , and switch S 1 . Current also flows clockwise in a first secondary loop comprising C SEC , S 3 , and the secondary winding of coupled inductor L MAIN , and clockwise in a second secondary loop comprising C OUT  and R LOAD . During the first operating state current ramps up in the primary loop. The rate of current rise is dependent on the value of leakage inductance of L MAIN  and the effective voltage applied to the leakage inductance. The voltage applied by the input source will be divided between the magnetizing inductance of L MAIN  and the leakage inductance of L MAIN , based on the relative magnitudes of leakage inductance and magnetizing inductance. Current in the primary winding of L MAIN  induces current into the secondary winding of L MAIN  to charge C SEC . The current in the secondary loop will also be a current ramp due to the effect of the leakage inductance. At the end of the first operating state S 1  is turned off. Stored magnetic energy in the leakage inductance and magnetizing inductance of L MAIN  forces the voltage to rise at the undotted terminal of the primary winding of L MAIN . The voltage at the undotted terminal of L MAIN  continues to rise until the switch S 2  is turned on at the instant that the applied voltage of S 2  drops to zero volts or at a time at which a diode intrinsic to S 2  becomes forward biased and begins to conduct. With the change in applied voltages to the components in the primary circuit the current in the primary loop rapidly decreases. As a result of the rapidly decreasing current in the primary circuit the induced secondary current decreases until the current in the secondary circuit decreases to zero at which time switch S 3  is turned off. At the instant the switch S 3  turns off a voltage transition in the secondary circuit takes place and the switch S 4  is turned on. The voltage transition in the secondary circuit is slightly delayed with respect to the voltage transition in the primary circuit due to the effect of stored magnetic energy in the leakage inductance. 
   During a second operating state switches S 2  and S 4  are on and switches S 1  and S 3  are off. In the primary circuit current flows in a loop comprising the primary winding of L MAIN , C RESET , and S 2 . During the second operating state, current first flows clockwise in the primary loop, but ramps down rapidly until the current is equal to the magnetizing current of L MAIN  after which the current ramps down at a lower rate, drops to zero, reverses direction, and ramps up in the counterclockwise direction. In the secondary circuit current flows in a loop comprising the secondary winding of L MAIN , S 4 , C SEC , C OUT , and R LOAD . The secondary current results from induced current from the primary circuit. During the second operating state current ramps up in the secondary loop starting from zero. The second operating state ends when switch S 2  is turned off. Stored energy from the leakage inductance of L MAIN  forces the voltage at the undotted terminal of L MAIN  to fall until the applied voltage of S 1  reaches zero volts at which instant S 1  is turned on. With S 1  on the current in the leakage inductance of L MAIN  falls rapidly and the induced current in the secondary winding of L MAIN  also falls rapidly until the current in the switch S 4  reaches zero at which instant S 4  is turned off and a voltage transition in the secondary circuit takes place after which S 3  is turned on and the cycle repeats.  FIGS. 5(   a ) through  5 ( h ) illustrate the voltage and current wave forms in each of the switches. 
   The  FIG. 6  circuit achieves zero voltage switching for all of its switches and zero current switching for switches S 3  and S 4  for all switching transitions, thereby eliminating first order switching losses. The  FIG. 6  circuit is particularly attractive for medium and high voltage applications since the maximum switch voltage stress in the secondary circuit does not exceed the output voltage. Another beneficial feature of the  FIG. 6  circuit is that the circuit is fully clamped. In both operating states both windings of the coupled inductor are clamped so that the winding voltages are fixed and no ringing is possible. The transfer function for the  FIG. 6  circuit is 
               V   OUT     =       nV   IN       (     1   -   D     )         ,         
where V OUT  is the load voltage, V IN  is the voltage of the input source, n is the ratio of secondary turns to primary turns, and D is the duty cycle of the S 1  switch. Except for the turns ratio, n, the transfer function for the  FIG. 6  circuit is identical to the transfer function for the simple boost converter.
 
   Another embodiment of the subject invention is illustrated in  FIG. 2 . In the  FIG. 2  circuit all of the switches are implemented with mosfets and the secondary switches are synchronous rectifiers. The polarity of the secondary winding is reversed in  FIG. 2  compared to the polarity indicated in  FIG. 6 . The output voltage is a sum of two voltages, one voltage is the secondary winding voltage of the first operating state and the second voltage is the secondary winding voltage of the second operating state. These two voltages will be reversed if the winding polarity is reversed, but the sum of voltages remains the same, regardless of the order and regardless of the secondary winding polarity, and the transfer function for  FIG. 2  is the same as the transfer function for  FIG. 6 . In  FIG. 6  the series inductance is illustrated as an inductor L ZVS , which may be the leakage inductance of the coupled inductor L MAIN , or L ZVS  may be a separate wound inductor separate from the leakage inductance of L MAIN . Whether the series inductance is provided by a leakage inductance or the series inductance is provided by a separate discrete inductor is inconsequential and has no effect on the operation of the circuit. One other difference between the  FIG. 6  circuit and the  FIG. 2  circuit is the connection of the capacitor C RESET  to the input. In  FIG. 6  C RESET  is connected to the positive input terminal and in  FIG. 2  C RESET  is connected to the negative input terminal. During the second operating state the input source V IN  remains in the current loop so that V IN  remains in the primary current loop during both or all operating states. In  FIG. 6  the current from V IN  is pulsating, but in  FIG. 2  the current from V IN  is continuous, non-pulsating, and linear, so that the electromagnetic interference from the current from V IN  is reduced in  FIG. 2  by comparison to the  FIG. 6  current. The  FIG. 6  connection of C RESET  has the advantage of lower capacitor voltage stress. Another difference between the  FIG. 6  embodiment and the  FIG. 2  embodiment is that the  FIG. 2  embodiment contains two secondary capacitors, both of which are connected to the secondary winding, but  FIG. 2  contains no capacitor in parallel with the load, but rather a series pair of capacitors connected in parallel with the load. The  FIG. 2  arrangement of secondary capacitors is a typical voltage doubler connection and results in reduced voltage stress of the two capacitor combination. 
   Another embodiment of the subject invention is illustrated in  FIG. 3 . In  FIG. 3  the primary switches are implemented with mosfets, the secondary switches are implemented with diodes, and the series inductance L ZVS  is placed in series with the secondary winding, instead of in series with the primary winding of the coupled inductor L MAIN . The performance described above for  FIG. 6  does not depend on the specific placement of the series inductance except that the series inductance must be placed in series with the coupled inductor. It does not matter whether the series inductance is placed in the primary winding, the secondary winding, or some combination of the two windings. Also, in  FIG. 3  the connection of the capacitor C SEC  is different than the connection shown in  FIG. 6  in that the capacitor is connected to the negative terminal of the load in  FIG. 6  and to the positive load terminal in  FIG. 3 . Again the results of the capacitor connection are inconsequential. Since the circuit performance is the same, regardless of how the capacitor C SEC  is connected to the load it would make sense to connect C SEC  to the load terminal which results in the lowest voltage stress on C SEC . Another possibility is to connect two capacitors to the secondary winding and connect one of the capacitors to the positive load terminal and the other capacitor to the negative load terminal and eliminate the capacitor C OUT , as illustrated in  FIG. 2 . 
     FIG. 4  illustrates another embodiment of the subject invention wherein the primary switches are split and rearranged in a way that reduces the primary switch voltage stress by an amount equal to the line voltage for the M 1A  and M 2A  switches. The voltage stress for the M 1B  and M 2B  switches will be equal to the input voltage. The primary switch arrangement resembles a full bridge circuit but it offers the same advantages that a double switch arrangement offers over a single switch arrangement, as is often done in single ended flyback and single ended forward converters to reduce switch voltage stress and extend the power handling capability of the circuit. In  FIG. 4  the secondary circuit is also rearranged with two pairs of switches. In the secondary arrangement shown, the output voltage is reduced by a factor of two and power is delivered to the load in both operating states. The  FIG. 4  secondary switch arrangement offers an advantage for higher power medium voltage applications because of its ability to transfer power directly from primary circuit to load in both operating states. 
     FIG. 7  illustrates another embodiment of the subject invention using four secondary switches arranged to double the output voltage in comparison to the output voltage achieved in the  FIG. 2  and  FIG. 6  circuits. Additional diodes and capacitors can be added to achieve output voltages higher than those in any of the circuits illustrated by adding more diodes and capacitors in the manner illustrated in  FIG. 7 . 
   CONCLUSION, RAMIFICATIONS, AND SCOPE OF INVENTION 
   Thus the reader will see that by the addition of an inductance in series with the coupled inductor in a coupled inductor boost converter a new beneficial coupled inductor boost converter is formed which achieves zero voltage turn on switching for all switches for all transitions. Variations of the new coupled inductor boost converter are also revealed which achieve higher or lower output voltage and reduced component stresses. The new coupled inductor boost converter achieves zero voltage switching without the ringing often associated with some zero voltage switching circuits because the new coupled inductor boost converter is fully clamped so that in all operating states all of the windings of the coupled inductor are coupled to capacitors. 
   While my above description contains many specificities, these should not be construed as limitations on the scope of the invention, but rather, as exemplifications or preferred embodiments thereof. Many other variations are possible. For example, in some of the circuits illustrated one can find alternate workable switches which can perform the same function as the switches illustrated in the figures. Circuits with higher orders of diode capacitance multipliers can be formed with higher output voltages by adding diodes and capacitors to the  FIG. 7  circuit. Circuits similar to the circuits shown, but with multiple interleaved parallel circuits that share common capacitors are possible and should be considered embodiments of the subject invention. Circuits similar to the circuits shown but with polarity of the input or output reversed from that illustrated in the figures shall be considered embodiments of the subject invention. Circuits similar to those shown, but having coupled magnetic circuit elements with more than two windings and circuits with more than one output shall be considered embodiments of the subject invention. In many of the circuits shown there are series connected networks. The order of placement of circuit elements in series connected networks is inconsequential in the illustrations shown so that series networks in the illustrated circuits with circuit elements reversed or placed in an entirely different order within series connected networks are equivalent to the circuits illustrated and shall be considered embodiments of the subject invention. Also, one of the embodiments illustrated shows simple switches, but the operation revealed and the benefits achieved in the subject invention can also be realized in circuits that implement the switches using N channel mosfets, P channel mosfets, IGBTs, JFETs, bipolar transistors, junction rectifiers, or schottky rectifiers, which should be considered embodiments of the subject invention. 
   Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.