Abstract:
A semiconductor device includes a chip, a plurality of pads that is formed along the perimeter of the chip, and that includes a first pad and a second pad placed next to the first pad, and a circuit that is formed on the chip, and that is coupled to the first and second pads. The circuit includes first and second conductivity type transistors that are coupled between first and second reference potentials and a comparator that includes a first input node coupled to the first pad and a second input node coupled to the second pad, and that compares a potential of the first input node with a potential of the second input node. The first pad is coupled to gate electrodes of the first and second conductivity type transistors, and the second pad is coupled to drain electrodes of the first and second conductivity type transistors.

Description:
[0001]    The present application is a Continuation application of U.S. patent application Ser. No. 12/222,734, filed on Aug. 14, 2008, now U.S. Pat. No. ______, which is based on and claims priority from Japanese Patent Application No. 89790/2008 filed on Mar. 31, 2008, the entire contents of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device and an operation mode setting method for the semiconductor device. More specifically, the present invention relates to a semiconductor device that switches operation modes based on the presence or absence of bonding and an operation mode setting method for the semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    It is a common practice to form circuits for implementing different functions on a substrate (chip) in advance, select a specific function that meets the user&#39;s (customer&#39;s) request upon assembly into a semiconductor device, and customize the semiconductor device by activating a circuit that has the selected function. With this, a semiconductor device that fulfils customers&#39; individual requests can be manufactured while reducing the total manufacture cost by making a general-purpose chip. 
         [0006]    U.S. Pat. No. 5,754,879 describes a technology of selecting any one of multiple operation modes based on whether or not an external terminal (power supply external terminal, ground external terminal, or reset external terminal) is bonded to an internal terminal (mode pad), which is provided on a chip for operation mode selection. This technology enables a semiconductor device to select an operation mode merely from the presence or absence of bonding without newly installing an external terminal through which special signals for operation mode selection are supplied. 
         [0007]    The inventor of the present invention has recognized that the premise of the technology described in U.S. Pat. No. 5,754,879 resides in that the voltage (logical level) input to a mode pad from the outside is determined in advance. In other words, whether an operation mode is selected at the H level or the L level is determined for each mode pad in advance. This means that each mode pad has to be placed adjacent to a specific internal terminal (power supply pad, ground pad, or reset pad) connected by a bonding wire to a specific external terminal (power supply external terminal, ground external terminal, or reset external terminal). In short, mode pads are arranged under layout limitations. 
       SUMMARY 
       [0008]    The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part. 
         [0009]    In one embodiment, a semiconductor device according to the present invention includes: a first internal terminal; a second internal terminal; a first switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a first reference electric potential and a state in which the second internal terminal is not electrically coupled to the first reference electric potential; a second switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a second reference electric potential and a state in which the second internal terminal is not electrically coupled to the second reference electric potential; and a comparator coupled to the first internal terminal and the second internal terminal to compare an electric potential of the first internal terminal with an electric potential of the second internal terminal, in which the first switching circuit and the second switching circuit exclusively operate in accordance with the electric potential of the first internal terminal. 
         [0010]    In such a structure described above, when the second internal terminal is not bonded to an external terminal, the second internal terminal is pulled up or pulled down in accordance with a logical level of a signal input to the first internal terminal. What connection state an external terminal and the second internal terminal (mode pad) are in can thus be detected irrespective of the logical level (H level/L level) of the signal input to the first internal terminal. 
         [0011]    This eliminates the need to place an internal terminal for operation mode selection adjacent to a specific internal terminal (power supply pad, ground pad, or reset pad). Freedom of layout is therefore secured in arrangement of internal terminals (mode pads) for operation mode selection. 
         [0012]    In another embodiment, a semiconductor device according to the present invention includes: a first internal terminal; a second internal terminal; a first switching circuit coupled to the first internal terminal and the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a first reference electric potential and a state in which the second internal terminal is not electrically coupled to the first reference electric potential, based on a logical value that corresponds to an electric potential of the first internal terminal; a second switching circuit coupled to the first internal terminal and the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a second reference electric potential and a state in which the second internal terminal is not electrically coupled to the second reference electric potential, based on the logical value that corresponds to the electric potential of the first internal terminal; and a comparator coupled to the first internal terminal and the second internal terminal to compare the electric potential of the first internal terminal with an electric potential of the second internal terminal, in which the first switching circuit and the second switching circuit are caused to operate so that the second internal terminal is electrically coupled to one of the first reference electric potential and the second reference electric potential that corresponds to a logical value different from the logical value corresponding to the electric potential of the first internal terminal. 
         [0013]    In such a structure described above, when the second internal terminal is not bonded to an external terminal, the second internal terminal is pulled up or pulled down to an electric potential that corresponds to a logical level different from the logical level of a signal input to the first internal terminal. What connection state an external terminal and the second internal terminal (mode pad) are in can thus be detected irrespective of whether the logical level of the signal input to the first internal terminal is at the H level or the L level. 
         [0014]    In yet another embodiment, an operation mode setting method for a semiconductor device according to the present invention includes: electrically coupling a second internal terminal to a first reference electric potential when an electric potential of a first internal terminal indicates a first logical level; electrically coupling the second internal terminal to a second reference electric potential when the electric potential of the first internal terminal indicates a second logical level; comparing the electric potential of the first internal terminal with an electric potential of the second internal terminal electrically coupled to one of the first reference electric potential and the second reference electric potential; and setting an operation mode in response to a result of the comparison. 
         [0015]    By such a method described above, what connection state an external terminal and the second internal terminal (mode pad) are in can be detected correctly irrespective of whether a signal input to the first internal terminal is at the H level or the L level. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0017]      FIG. 1  is a structural diagram of a semiconductor device according to a first embodiment of the present invention; 
           [0018]      FIG. 2  is a detailed structural diagram of the semiconductor device according to the first embodiment of the present invention; 
           [0019]      FIG. 3  is a circuit diagram of an operation mode selection circuit according to the first embodiment of the present invention, and illustrates a length L 1  and a length L 2 ; 
           [0020]      FIG. 4  is a truth table illustrating an operation of the operation mode selection circuit according to the first embodiment of the present invention; 
           [0021]      FIG. 5  is a circuit diagram of an operation mode selection circuit according to a second embodiment of the present invention; 
           [0022]      FIG. 6  is a timing chart illustrating an operation of the operation mode selection circuit according to the second embodiment of the present invention; 
           [0023]      FIG. 7  is another timing chart illustrating the operation of the operation mode selection circuit according to the second embodiment of the present invention; 
           [0024]      FIG. 8  is a circuit diagram of an operation mode selection circuit according to a third embodiment of the present invention; 
           [0025]      FIG. 9  is a timing chart illustrating an operation of the operation mode selection circuit according to the third embodiment of the present invention; 
           [0026]      FIG. 10  is another timing chart illustrating the operation of the operation mode selection circuit according to the third embodiment of the present invention; 
           [0027]      FIG. 11  is a detailed structural diagram of a semiconductor device according to a fourth embodiment of the present invention; 
           [0028]      FIG. 12  is a circuit diagram of an operation mode selection circuit according to the fourth embodiment of the present invention; 
           [0029]      FIG. 13  is a truth table showing input-output relations of an operation mode determining circuit according to the fourth embodiment of the present invention; 
           [0030]      FIG. 14  is a timing chart illustrating an operation of the operation mode selection circuit according to the fourth embodiment of the present invention; 
           [0031]      FIG. 15  is another timing chart illustrating the operation of the operation mode selection circuit according to the fourth embodiment of the present invention; 
           [0032]      FIG. 16  is still another timing chart illustrating the operation of the operation mode selection circuit according to the fourth embodiment of the present invention; 
           [0033]      FIG. 17  is a diagram showing a modification example of a semiconductor device according to the present invention; 
           [0034]      FIG. 18  is a cross sectional view along line B-B′ in  FIG. 17 . 
           [0035]      FIG. 19  is a diagram showing another modification example of a semiconductor device according to the present invention; 
           [0036]      FIG. 20  is a cross sectional view along line C-C′ in  FIG. 19 . 
           [0037]      FIG. 21  is a cross sectional view along line C-C′ in  FIG. 19 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0038]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
       First Embodiment 
       [0039]      FIG. 1  is a structural diagram of a semiconductor device  1  according to a first embodiment of the present invention. As shown in  FIG. 1 , the semiconductor device  1  has a substrate (chip)  2 , multiple bonding wires  6 , multiple external terminals (leads)  5  respectively connected to the chip  2  by the multiple bonding wires  6 , and a mold resin  3 . 
         [0040]    Multiple internal terminals (pads)  4  are placed along the perimeter of the chip  2 . An internal circuit  7  is formed in an area on the chip  2  that is within the square of the pads  4 . The internal circuit  7  contains an operation mode selection circuit, and a functional block (for example, a central processing unit (CPU), a memory, and peripheral circuits (an input/output circuit, a protection circuit, and the like)) as well. 
         [0041]    The pads  4  include a pad for operation mode selection (a mode pad) in addition to usual pads such as a pad to which a power supply electric potential is supplied, a pad connected to a ground electric potential, a pad to which a reset signal is input, and a pad for communicating input/output signals. The mode pad is connected to the operation mode selection circuit within the internal circuit  7 , and the operation mode selection circuit selects a specific operation mode from among multiple operation modes based on whether bonding to the mode pad is detected or not. When an external terminal (lead) is bonded to the mode pad, two bonding wires  6  are connected to one lead  5  as shown in  FIG. 1 . 
         [0042]    By selecting an operation mode, bus protocol settings (for example, whether it is an operation mode in which data is output in one bit or an operation mode in which data is output in four bits is set), reliability level settings (for example, whether it is an operation mode that enables an error correction function or an operation mode that disables the error correction function is set), and the like can be set. The initially set operation mode thus makes the semiconductor device  1  operate in a manner that meets the customer&#39;s request. 
         [0043]      FIG. 2  shows details of a portion A circled by the dotted line of  FIG. 1 . The leads  5  include four types of leads  5   a  to  5   d . The lead  5   a  is a reset external terminal for inputting a reset signal from the outside into the chip  2 . The lead  5   b  is a power supply external terminal for supplying a power supply electric potential to the chip  2 . The lead  5   c  is a signal external terminal for communicating input/output signals between the chip  2  and the outside. The lead  5   d  is a ground external terminal connected to an external ground electric potential. 
         [0044]    The pads  4  include five types of pads  4   a  to  4   e . The pad  4   a  is a reset internal terminal (reset pad) which is connected to the lead  5   a  by one of the bonding wires  6  to receive a reset signal. The pad  4   a  is pulled up (because it is low-active (active LOW)) by a pull-up resistor  10  to output the reset signal to the operation mode selection circuit  8 , and the functional block  9 . 
         [0045]    The pad  4   b  is a power supply internal terminal (power supply pad) which is connected to the lead  5   b  by one of the bonding wires  6  to receive a power supply electric potential. The pad  4   b  outputs a power supply electric potential supplied from the outside to the operation mode selection circuit  8  and the functional block  9 . 
         [0046]    The pad  4   c  is a signal internal terminal (signal pad) which is connected to the lead  5   c  by one of the bonding wires  6  to communicate input/output signals. The pad  4   c  is pulled down by a pull-down resistor  11  (or by a pull-up resistor instead), and connected to the operation mode selection circuit  8  and the functional block  9 . 
         [0047]    The pad  4   d  is an internal terminal for operation mode selection (mode pad) and is connected to the operation mode selection circuit  8 . The pad  4   d  and the lead  5   c  are bonded to each other in some cases and not bonded in other cases. Whether the pad  4   d  and the lead  5   c  are bonded or not is utilized in selecting an operation mode. In the drawings, the bonding wire  6  that connects the pad  4   d  to the lead  5   c  is represented by a dotted line since the lead  5   c  and the pad  4   d  are not always bonded. 
         [0048]    The pad  4   e  is a ground internal terminal (ground pad) which is connected to the lead  5   d  by one of the bonding wires  6  to be connected to a ground electric potential. The pad  4   e  is connected to the operation mode selection circuit  8  and the functional block  9 . 
         [0049]    The functional block  9  is connected to the pads  4  (pads  4   a ,  4   b ,  4   c , and  4   e ), and an output (operation mode switching signal) from the operation mode selection circuit  8  is input to the functional block  9 . The functional block  9  causes the circuit to operate in an operation mode that is selected in accordance with the input operation mode switching signal. 
         [0050]    The operation mode selection circuit  8  is described next.  FIG. 3  is a circuit diagram of the operation mode selection circuit  8   a . Power supply relations (connections with the pad  4   b  and the pad  4   e ) are omitted from the circuit diagram. The operation mode selection circuit  8   a  according to the first embodiment does not always need reset signals. Therefore, wiring for reset signals is also omitted from  FIG. 3 . 
         [0051]    The operation mode selection circuit  8   a  has a pull-up circuit  12 , a pull-down circuit  13 , and a comparator circuit (exclusive OR gate)  14 . The operation mode selection circuit  8   a  receives electric potentials input from the pads  4   c  and  4   d , and outputs an operation mode switching signal to the functional block  9 . 
         [0052]    The pull-up circuit  12  has a pull-up resistor  120  and a switching circuit (P-channel (Pch) transistor)  121 . One end of the Pch transistor  121  is connected to a power supply line via the pull-up resistor  120 . The other end of the Pch transistor  121  is connected to the pad  4   d  and the pull-down circuit  13 . A gate of the Pch transistor  121  is connected to the pad  4   c.    
         [0053]    The pull-up circuit  13  has a pull-down resistor  130  and a switching circuit (N-channel (Nch) transistor)  131 . One end of the Nch transistor  131  is connected to a ground line via the pull-down resistor  130 . The other end of the Nch transistor  131  is connected to the pad  4   d  and the pull-up circuit  12 . A gate of the Nch transistor  131  is connected to the pad  4   c.    
         [0054]    The gate of the Pch transistor  121  and the gate of the Nch transistor  131  thus receive an electric potential input from the shared pad  4   c . The Pch transistor  121  and the Nch transistor  131  are turned ON/OFF by the logical level of a signal input to the pad  4   c , and operate in a mutually exclusive manner. Specifically, when the logical level of the signal input to the pad  4   c  is H, the Pch transistor  121  is turned OFF whereas the Nch transistor  131  is turned ON. When the logical level of the signal input to the pad  4   c  is L, the Pch transistor  121  is turned ON whereas the Nch transistor  131  is turned OFF. Therefore, when the lead  5   c  and the pad  4   d  are not bonded to each other by a bonding wire, the pad  4   d  is pulled up or pulled down to an electric potential that indicates a logical level opposite to the logical level of the signal input to the pad  4   c.    
         [0055]    The input of the exclusive OR gate  14  is connected to the pad  4   c  and the pad  4   d , and the output of the exclusive OR gate  14  is connected to the functional block  9 . The exclusive OR gate  14  compares the logical level of a signal input to the pad  4   c  and the logical level of a signal input to the pad  4   d  with each other. When the comparison reveals that the two match, the exclusive OR gate  14  outputs an L-level operation mode switching signal to the functional block  9  and, when the two do not match, outputs an H-level operation mode switching signal to the functional block  9 . 
         [0056]    How the operation mode selection circuit  8   a  operates is described next.  FIG. 4  is a truth table illustrating the operation of the operation mode selection circuit  8   a.    
         [0057]    When the pad  4   d  is bonded to the lead  5   c , it means that the same signal is input to the pad  4   c  and the pad  4   d , thereby giving the pads  4   c  and  4   d  the same logical level as shown in  FIG. 4 . When the pad  4   d  is not bonded to the lead  5   c , on the other hand, a signal is input only to the pad  4   c  whereas the pad  4   d  is pulled up or pulled down by the pull-up circuit  12  or the pull-down circuit  13  to an electric potential that indicates a logical level opposite to the logical level of the signal input to the pad  4   c . The pad  4   c  and the pad  4   d  in this case thus have logical levels opposite to each other. Accordingly, the operation mode switching signal output when the pad  4   d  is bonded to the lead  5   c  is at the L level, which indicates a match, and the operation mode switching signal output when the pad  4   d  is not bonded to the lead  5   c  is at the H level, which indicates a mismatch. This means that if the pad  4   d  is bonded to the lead  5   c  or not can be correctly detected and an operation mode can be selected accordingly irrespective of whether the logical level of a signal input to the pad  4   c  is H or L. 
         [0058]    For example, when an L-level operation mode switching signal is to indicate Operation Mode One and an H-level operation mode switching signal is to indicate Operation Mode Two, a selection can be made from two different operation modes per one mode pad (pad  4   d ). The functional block  9  receives an operation mode switching signal generated in the operation mode selection circuit  8   a , and causes the circuit to operate in Operation Mode One or Operation Mode Two. 
         [0059]    As described above, according to the first embodiment of the present invention, an operation mode can be selected whichever of an H-level signal and an L-level signal is input to the operation mode selection pad  4   d . This eliminates the need for the lead  5   c , which is in some cases bonded to the operation mode selection pad  4   d  by one of the bonding wires  6 , to be a specific external terminal (power supply terminal, ground terminal, or reset terminal) to which a voltage that gives the terminal a certain logical level is applied. In other words, the operation mode selection pad  4   d  does not need to be placed adjacent to a specific internal terminal that is bonded to the specific external terminal (power supply external terminal, ground external terminal, or reset external terminal). Freedom of layout is thus secured in placement of the operation mode selection pad  4   d  (mode pad). 
       Second Embodiment 
       [0060]    The structure and operation of the semiconductor device  1  according to a second embodiment of the present invention will be described with reference to  FIGS. 5 to 7 . The difference of the second embodiment from the first embodiment is that, after an operation mode is selected, the operation mode is fixed with only one of the pull-up circuit  12  and the pull-down circuit  13  being enabled. 
         [0061]      FIG. 5  is a circuit diagram of an operation mode selection circuit  8   b  according to the second embodiment. Components common to the first embodiment are denoted by the same reference symbols and descriptions on those components will be omitted here. Power supply relations (connection relations with the pad  4   b  and the pad  4   e ) are also omitted. The second embodiment is the same as the first embodiment except for the circuit structure shown in  FIG. 5 , and repetitive descriptions will be avoided. 
         [0062]    The operation mode selection circuit  8   b  has the pull-up circuit  12 , the pull-down circuit  13 , the comparator circuit (exclusive OR gate)  14 , an inverter  15 , a delay element  16 , a switching circuit (AND gate)  17 , and a holding circuit  18 . 
         [0063]    The pull-up circuit  12  and the pull-down circuit  13  of the second embodiment have the same structures as those of the first embodiment, except that the input source shared by the gate of the Pch transistor  121  and the gate of the Nch transistor  131  is the output of the AND gate  17 . 
         [0064]    The inverter  15  inverts the logic of a reset signal input via the pad  4   a . The output of the inverter  15  is connected to the delay element  16 . The delay element  16  delays a signal output from the inverter  15  by a given period of time before the signal is output to the AND gate  17 . 
         [0065]    The input of the AND gate  17  is connected to the output of the delay element  16  and the pad  4   c , and the output of the AND gate  17  is connected to the gate of the Pch transistor  121  and the gate of the Nch transistor  131 . When a signal output from the delay element  16  is at the H level, the AND gate  17  outputs the signal that has been input to the pad  4   c . When a signal output from the delay element  16  is at the L level, the AND gate  17  outputs an L-level signal. 
         [0066]    The holding circuit  18  is connected to the exclusive OR gate  14 , the pad  4   a , and the functional block  9 . When a reset signal input from the pad  4   a  is at the L level, the holding circuit  18  outputs a signal input from the exclusive OR gate  14  as it is (lets the signal pass through). When a reset signal input from the pad  4   a  is at the H level, an output of the holding circuit  18  is latched. An output signal of the holding circuit  18  is output as an operation mode switching signal to the functional block  9 . 
         [0067]    Described next is how the operation mode selection circuit  8   b  operates.  FIGS. 6 and 7  are timing charts illustrating the operation of the operation mode selection circuit  8   b.    
         [0068]      FIG. 6  shows operation timing for a case where the lead  5   c  and the pad  4   d  are bonded to each other by one of the bonding wires  6 . The pad  4   c  and the pad  4   d  are connected to the lead  5   c  separately by different bonding wires  6 , which means that a logical level indicated by the electric potential of the pad  4   c  (N 1 ) and a logical level indicated by the electric potential of the pad  4   d  (N 2 ) are equal to each other throughout the entire period (t 0  to t 9 ). Accordingly, the output (N 5 ) of the exclusive OR gate  14  is at the L level, which indicates that the two match, throughout the entire period (t 0  to t 9 ). 
         [0069]    In a period t 0  to t 1  where the reset signal (N 3 ) is at the H level, the output of the delay element  16  is at the L level and the output (N 4 ) of the AND gate  17  is at the L level. Since the Pch transistor  121  is ON during this period, the pull-up resistor  120  is connected to the pad  4   d . The holding circuit  18  in this period receives an input of an H-level reset signal, and the output (N 6 ) of the holding circuit  18  is therefore held (at an indefinite value). 
         [0070]    At t 1 , the reset signal (N 3 ) changes from the H level to the L level. The holding circuit  18  operates so as to output an input value as it is, and the output (N 6 ) of the holding circuit  18  is therefore at the L level. 
         [0071]    At t 2 , the output (N 4 ) of the AND gate  17  changes from the L level to the H level. The length of time from t 1  to t 2  corresponds to a delay put by the delay element  16 , and a change in logic of the reset signal is propagated to the AND gate  17  with this delay. Since the output of the delay element  16  which is one of the inputs of the AND gate  17  is now at the H level, the output (N 4 ) of the AND gate  17  changes depending on the logical level of a signal input to the pad  4   c  (N 1 ). The pad  4   c  (N 1 ) at t 2  receives an input of an H-level signal, thereby changing the output (N 4 ) of the AND gate  17  to the H level. This turns the Pch transistor  121  OFF and the Nch transistor  131  ON, and the pull-down resistor  130  is therefore connected to the pad  4   d.    
         [0072]    The logical level of the signal input to the pad  4   c  (N 1 ) changes at t 3  and again at t 4 , causing the output (N 4 ) of the AND gate  17  to change in a similar manner. As a result, the pull-up connection and the pull-down connection are switched. 
         [0073]    At t 5 , the reset signal (N 3 ) changes from the L level to the H level, causing the output (N 6 ) of the holding circuit  18  to be held. In short, a period between t 2  and t 5  is an operation mode selection period and the operation mode is established at t 5 . For example, when an L-level operation mode switching signal is to prompt a switch to Operation Mode One and an H-level operation mode switching signal is to prompt a switch to Operation Mode Two, the operation mode is established at Operation Mode One at t 5  and the semiconductor device  1  operates in this mode from then on. 
         [0074]    At t 6 , the change in logic of the reset signal (N 3 ) reaches the AND gate  17 , causing the output (N 4 ) of the AND gate  17  to change from the H level to the L level. This turns the Pch transistor ON and the Nch transistor OFF, and the pull-up resistor is accordingly connected to the pad  4   d.    
         [0075]    As shown in  FIG. 6 , logical level changes at t 7  and t 8  of the signal input to the pad  4   c  (N 1 ) do not cause the output (N 4 ) of the AND gate  17  to change. The pull-up connection and the pull-down connection are therefore not switched. In other words, the pull-up circuit  12  is enabled at t 6  and the pad  4   d  is fixed to the pulled-up level from then on. 
         [0076]    If the logical level of the signal input to the pad  4   c  (N 1 ) is reversed to the one of  FIG. 6  so that an L-level signal is input in periods t 0  to t 3 , t 4  to t 7 , and t 8  to t 9  whereas an H-level signal is input in periods t 3  to t 4  and t 7  to t 8 , the output (N 5 ) of the exclusive OR gate  14  and the output (N 6 ) of the holding circuit  18  are exactly the same as in  FIG. 6 . In this case, the pad  4   d  is also fixed to the pulled-up level in t 6  and the subsequent periods. 
         [0077]      FIG. 7  shows operation timing for a case where the lead  5   c  and the pad  4   d  are not bonded to each other by one of the bonding wires  6 . Unlike  FIG. 6 , a logical level indicated by the electric potential of the pad  4   c  and a logical level indicated by the electric potential of the pad  4   d  are equal to each other in some periods, but not throughout the entire period (t 0  to t 9 ). The logical level of the pad  4   c  is determined by a signal supplied from the lead  5   c  whereas the logical level of the pad  4   d  is determined by whether the pull-up connection with the pull-up circuit  12  or the pull-down connection with the pull-down circuit  13  is active. 
         [0078]    In a period t 0  to t 1  where the reset signal (N 3 ) is at the H level, the output of the delay element  16  is at the L level and the output (N 4 ) of the AND gate  17  is at the L level. Since the Pch transistor  121  is ON during this period, the pull-up resistor  120  is connected to the pad  4   d . In  FIG. 7 , the pad  4   d  (N 2 ) is not bonded to the lead  5   c  and therefore is pulled up to the H level. The output (N 5 ) of the exclusive OR gate  14 , which compares the pad  4   c  (N 1 ) and the pad  4   d  (N 2 ) with each other, is therefore at the L level, which indicates that the two match. The holding circuit  18  in this period receives an input of an H-level reset signal, causing the output (N 6 ) of the holding circuit  18  to be held (at an indefinite value). 
         [0079]    At t 1 , the reset signal (N 3 ) changes from the H level to the L level. The holding circuit  18  operates such that it outputs an input value as it is, and the output (N 6 ) of the holding circuit  18  is therefore at the L level. 
         [0080]    At t 2 , the output (N 4 ) of the AND gate  17  changes from the L level to the H level. The length of time from t 1  to t 2  corresponds to a delay put by the delay element  16 , and a change in logic of the reset signal is propagated to the AND gate  17  with this delay. Since the output of the delay element  16  which is one of the inputs of the AND gate  17  is now at the H level, the output (N 4 ) of the AND gate  17  changes depending on the logical level of a signal input to the pad  4   c  (N 1 ). The pad  4   c  (N 1 ) at t 2  receives an input of an H-level signal, thereby changing the output (N 4 ) of the AND gate  17  to the H level. This turns the Pch transistor  121  OFF and the Nch transistor  131  ON, and the pull-down resistor  130  is therefore connected to the pad  4   d . As a result, the pad  4   d  (N 2 ) is pulled down to the L level. Accordingly, the output (N 5 ) of the exclusive OR gate  14  and the output (N 6 ) of the holding circuit  18  change from the L level to the H level. 
         [0081]    The logical level of the signal input to the pad  4   c  (N 1 ) changes at t 3  and again at t 4 , causing the output (N 4 ) of the AND gate  17  to change in a similar manner. As a result, the pull-up connection with the pull-up circuit  12  and the pull-down connection with the pull-down circuit  13  are switched, thereby changing the logical levels of the pad  4   c  (N 1 ) and the pad  4   d  (N 2 ) such that N 2  is opposite to N 1  as shown in  FIG. 7 . 
         [0082]    At t 5 , the reset signal (N 3 ) changes from the L level to the H level, causing the output (N 6 ) of the holding circuit  18  to be held. In short, a period between t 2  and t 5  is an operation mode selection period and the operation mode is established at t 5 . For example, when an L-level operation mode switching signal is to prompt a switch to Operation Mode One and an H-level operation mode switching signal is to prompt a switch to Operation Mode Two, the operation mode is established at Operation Mode Two at t 5  and the semiconductor device  1  operates in this mode from then on. 
         [0083]    At t 6 , the change in logic of the reset signal (N 3 ) reaches the AND gate  17 , causing the output (N 4 ) of the AND gate  17  to change from the H level to the L level. This turns the Pch transistor ON and the Nch transistor OFF, and the pull-up resistor is accordingly connected to the pad  4   d . As a result, the pad  4   d  (N 2 ) is pulled up to the H level. 
         [0084]    Logical level changes at t 7  and t 8  of the signal input to the pad  4   c  (N 1 ) do not cause the output (N 4 ) of the AND gate  17  to change. The pull-up connection and the pull-down connection are therefore not switched. In other words, the pull-up circuit  12  is enabled at t 6  and the pad  4   d  is fixed to the pulled-up level from then on. Since the pad  4   d  (N 2 ) in this case is fixed to the H level, a change in logical level of the signal input to the pad  4   c  (N 1 ) causes a change in the output (N 5 ) of the exclusive OR gate  14  as well. However, the operation mode is not switched because the operation mode switching signal is being held at the H level by the holding circuit  18 . 
         [0085]    If the logical level of the signal input to the pad  4   c  (N 1 ) is reversed to the one of  FIG. 7  so that an L-level signal is input in periods t 0  to t 3 , t 4  to t 7 , and t 8  to t 9  whereas an H-level signal is input in periods t 3  to t 4  and t 7  to t 8 , the output (N 5 ) of the exclusive OR gate  14  and the output (N 6 ) of the holding circuit  18  are exactly the same as in  FIG. 7  in t 2  and the subsequent periods. In this case, the pad  4   d  is also fixed to the pulled-up level in t 6  and the subsequent periods. 
         [0086]    As described above, according to the second embodiment of the present invention, a period in which the reset signal is at the L level (for example, a period in which reset is applied) is positioned as an operation mode selection period, and the exclusive OR gate  14  selects an operation mode during this period in the same manner as in the first embodiment. When a period in which the reset signal is at the H level (for example, a period in which reset is canceled) arrives, the holding circuit  18  holds the output of the exclusive OR gate  14  to establish the operation mode. The output of the AND gate  17  is fixed to the L level at this point, with the result that the pull-up circuit  12  alone is enabled and the pad  4   d  is fixed to the pulled-up level from then on irrespective of the logical level of the signal input to the pad  4   c . In short, the second embodiment has an effect of reducing a through current which is generated when a switch is made between the pull-up connection with the pull-up circuit  12  and the pull-down connection with the pull-down circuit  13 , in addition to the effects of the first embodiment. 
         [0087]    While a case in which the pad  4   d  is fixed to the pulled-up level at t 6  and the subsequent periods is taken as an example in  FIGS. 5 to 7 , the pad  4   d  can be fixed to the pulled-down level instead if the logic is reversed. Also,  FIG. 5  shows the delay element  16  explicitly, but the delay element  16 , which is for preventing a change in logic of the reset signal from changing the input of the holding circuit  18  before the operation mode switching signal is held, may be implemented by gate delays of the inverter  15 , the AND gate  17 , and the exclusive OR (EXOR) gate  14 . In addition, although a reset signal is used in  FIG. 5  to define the operation mode selection period and to establish an operation mode, other signals than the reset signal may be employed instead. 
       Third Embodiment 
       [0088]    The structure and operation of the semiconductor device  1  according to a third embodiment of the present invention will be described with reference to  FIGS. 8 to 10 . The difference of the third embodiment from the first embodiment and the second embodiment is that, after an operation mode is selected, the pull-up circuit  12  and the pull-down circuit  13  are controlled such that the electric potential of the pad  4   d  indicates the same logical level as the logical level of a signal input to the pad  4   c.    
         [0089]      FIG. 8  is a circuit diagram of an operation mode selection circuit  8   c  according to the third embodiment. Components common to the first embodiment and the second embodiment are denoted by the same reference symbols and descriptions on those components will be omitted here. Power supply relations (connection relations with the pad  4   b  and the pad  4   e ) are also omitted. The third embodiment is the same as the first embodiment except for the circuit structure shown in  FIG. 8 , and repetitive descriptions will be avoided. 
         [0090]    The operation mode selection circuit  8   c  has the pull-up circuit  12 , the pull-down circuit  13 , the comparator circuit (exclusive OR gate)  14 , the inverter  15 , an inverter  19 , the delay element  16 , the holding circuit  18 , and a selector  20 . 
         [0091]    In the third embodiment, as shown in  FIG. 8 , the input source shared by the gate of the Pch transistor  121  of the pull-up circuit  12  and the gate of the Nch transistor  131  of the pull-down circuit  13  is the output of the selector  20 . 
         [0092]    The inverter  19  inverts the logic of a signal input via the pad  4   c . The output of the inverter  19  is connected to the input of the selector  20 . 
         [0093]    The input of the selector  20  is connected to the pad  4   c  and the output of the inverter  19 . The output of the selector  20  is connected to the gate of the Pch transistor  121  and the gate of the Nch transistor  131 . The selector  20  receives an output of the delay element  16  as a control signal. When a signal output from the delay element  16  is at the H level, the selector  20  outputs a signal that is selected out of signals input to the pad  4   c . When a signal output from the delay element  16  is at the L level, the selector  20  outputs a signal that is selected out of signals output from the inverter  19 . In other words, the selector  20  has the function of a switching circuit that switches between a state in which the pad  4   c  is connected to the output of the selector  20  and a state in which the output of the inverter  19  is connected to the output of the selector  20  based on the output of the delay element  16 . 
         [0094]    Described next is how the operation mode selection circuit  8   c  operates.  FIGS. 9 and 10  are timing charts illustrating the operation of the operation mode selection circuit  8   c.    
         [0095]      FIG. 9  shows operation timing for a case where the lead  5   c  and the pad  4   d  are bonded to each other by one of the bonding wires  6 . The pad  4   c  and the pad  4   d  are connected to the lead  5   c  separately by different bonding wires  6 , which means that a logical level indicated by the electric potential of the pad  4   c  (N 1 ) and a logical level indicated by the electric potential of the pad  4   d  (N 2 ) are equal to each other throughout the entire period (t 0  to t 7 ). Accordingly, the output (N 5 ) of the exclusive OR gate  14  is at the L level, which indicates that the two match, throughout the entire period (t 0  to t 7 ). 
         [0096]    In a period t 0  to t 1  where the reset signal (N 3 ) is at the H level, the output of the delay element  16  is at the L level and the selector  20  selects from among outputs of the inverter  19 . The output (N 4 ) of the selector  20  is accordingly at the L level. Since the Pch transistor  121  is ON during this period, the pull-up resistor  120  is connected to the pad  4   d . The holding circuit  18  in this period receives an input of an H-level reset signal, and the output (N 6 ) of the holding circuit  18  is therefore held (at an indefinite value). 
         [0097]    At t 1 , the reset signal (N 3 ) changes from the H level to the L level. The holding circuit  18  operates such that it outputs an input value as it is, and the output (N 6 ) of the holding circuit  18  is therefore at the L level. 
         [0098]    At t 2 , the output (N 4 ) of the selector  20  changes from the L level to the H level. The length of time from t 1  to t 2  corresponds to a delay put by the delay element  16 , and a change in logic of the reset signal is propagated to the selector  20  with this delay. Since the output of the delay element  16  is now at the H level, the selector  20  selects from among signals input to the pad  4   c  (N 1 ). The pad  4   c  (N 1 ) at t 2  receives an input of an H-level signal, thereby changing the output (N 4 ) of the selector  20  to the H level. This turns the Pch transistor  121  OFF and the Nch transistor  131  ON, and the pull-down resistor  130  is therefore connected to the pad  4   d.    
         [0099]    At t 3 , the reset signal (N 3 ) changes from the L level to the H level, causing the output (N 6 ) of the holding circuit  18  to be held. In short, a period between t 2  and t 3  is an operation mode selection period and the operation mode is established at t 3 . For example, when an L-level operation mode switching signal is to prompt a switch to Operation Mode One and an H-level operation mode switching signal is to prompt a switch to Operation Mode Two, the operation mode is established at Operation Mode One at t 3  and the semiconductor device  1  operates in this mode from then on. 
         [0100]    At t 4 , the change in logic of the reset signal (N 3 ) reaches the selector  20 , causing the selector  20  to select from among outputs of the inverter  19  and changing the output (N 4 ) of the selector  20  from the H level to the L level. This turns the Pch transistor ON and the Nch transistor OFF, and the pull-up resistor is accordingly connected to the pad  4   d.    
         [0101]    As shown in  FIG. 9 , logical level changes at t 5  and t 6  of the signal input to the pad  4   c  (N 1 ) cause the output of the inverter  19  to change, with the result that the output (N 4 ) of the selector  20  is changed. At t 5  where the signal input to the pad  4   c  changes from the H level to the L level, the output (N 4 ) of the selector  20  changes from the L level to the H level. At t 6  where the signal input to the pad  4   c  changes from the L level to the H level, the output (N 4 ) of the selector  20  changes from the H level to the L level. In other words, in t 4  and the subsequent periods, the pull-up circuit  12  or the pull-down circuit  13  is controlled with the output (N 4 ) of the selector  20  such that the pad  4   d  is pulled up by the pull-up connection, or pulled down by the pull-down connection, to an electric potential that indicates the same logical level as the logical level of the signal input to the pad  4   c.    
         [0102]    If the logical level of the signal input to the pad  4   c  (N 1 ) is reversed to the one of  FIG. 9  so that an L-level signal is input in periods t 0  to t 5  and t 6  to t 7  whereas an H-level signal is input in periods t 5  to t 6 , the output (N 5 ) of the exclusive OR gate  14  and the output (N 6 ) of the holding circuit  18  are exactly the same as in  FIG. 9 . In this case, the pull-up circuit  12  or the pull-down circuit  13  is also controlled such that the pad  4   d  is pulled up by the pull-up connection, or pulled down by the pull-down connection, to an electric potential that indicates the same logical level as the logical level of the signal input to the pad  4   c  in t 4  and the subsequent periods. 
         [0103]      FIG. 10  shows operation timing for a case where the lead  5   c  and the pad  4   d  are not bonded to each other by one of the bonding wires  6 . Unlike  FIG. 9 , a logical level indicated by the electric potential of the pad  4   c  and a logical level indicated by the electric potential of the pad  4   d  are equal to each other in some periods, but not throughout the entire period (t 0  to t 7 ). The logical level of the pad  4   c  is determined by a signal supplied from the lead  5   c  whereas the logical level of the pad  4   d  is determined by whether the pull-up connection with the pull-up circuit  12  or the pull-down connection with the pull-down circuit  13  is active. 
         [0104]    In a period t 0  to t 1  where the reset signal (N 3 ) is at the H level, the output of the delay element  16  is at the L level and the selector  20  selects from among outputs of the inverter  19 . The output (N 4 ) of the selector  20  is accordingly at the L level. Since the Pch transistor  121  is ON during this period, the pull-up resistor  120  is connected to the pad  4   d . In  FIG. 10 , the pad  4   d  (N 2 ) is not bonded to the lead  5   c  and therefore is pulled up to the H level. The output (N 5 ) of the exclusive OR gate  14 , which compares the pad  4   c  (N 1 ) and the pad  4   d  (N 2 ) against each other, is therefore at the L level which indicates that the two match. The holding circuit  18  in this period receives an input of an H-level reset signal, causing the output (N 6 ) of the holding circuit  18  to be held (at an indefinite value). 
         [0105]    At t 1 , the reset signal (N 3 ) changes from the H level to the L level. The holding circuit  18  operates so as to output an input value as it is, and the output (N 6 ) of the holding circuit  18  is therefore at the L level. 
         [0106]    At t 2 , the output (N 4 ) of the selector  20  changes from the L level to the H level. The length of time from t 1  to t 2  corresponds to a delay put by the delay element  16 , and a change in logic of the reset signal is propagated to the selector  20  with this delay. With the output of the delay element  16  changed from the L level to the H level, the selector  20  now selects from among signals input to the pad  4   c  (N 1 ). The pad  4   c  (N 1 ) at t 2  receives an input of an H-level signal, thereby changing the output (N 4 ) of the selector  20  to the H level. This turns the Pch transistor  121  OFF and the Nch transistor  131  ON, and the pull-down resistor  130  is therefore connected to the pad  4   d . As a result, the pad  4   d  (N 2 ) is pulled down to the L level. The output (N 5 ) of the exclusive OR gate  14  and the output (N 6 ) of the holding circuit  18  are accordingly changed from the L level to the H level. 
         [0107]    At t 3 , the reset signal (N 3 ) changes from the L level to the H level, causing the output (N 6 ) of the holding circuit  18  to be held. In short, a period between t 2  and t 3  is an operation mode selection period and the operation mode is established at t 3 . For example, when an L-level operation mode switching signal is to prompt a switch to Operation Mode One and an H-level operation mode switching signal is to prompt a switch to Operation Mode Two, the operation mode is established at Operation Mode Two at t 3  and the semiconductor device  1  operates in this mode from then on. 
         [0108]    At t 4 , the change in logic of the reset signal (N 3 ) reaches the selector  20 , causing the selector  20  to select from among outputs of the inverter  19  and changing the output (N 4 ) of the selector  20  from the H level to the L level. This turns the Pch transistor ON and the Nch transistor OFF, and the pull-up resistor is accordingly connected to the pad  4   d . As a result, the pad  4   d  (N 2 ) is pulled up to the H level. 
         [0109]    As shown in  FIG. 10 , logical level changes at t 5  and t 6  of the signal input to the pad  4   c  (N 1 ) cause the output of the inverter  19  to change, with the result that the output (N 4 ) of the selector  20  is changed. At t 5  where the signal input to the pad  4   c  changes from the H level to the L level, the output (N 4 ) of the selector  20  changes from the L level to the H level. At t 6  where the signal input to the pad  4   c  changes from the L level to the H level, the output (N 4 ) of the selector  20  changes from the H level to the L level. In other words, in t 4  and the subsequent periods, the pull-up circuit  12  or the pull-down circuit  13  is controlled with the output (N 4 ) of the selector  20  such that the pad  4   d  is pulled up by the pull-up connection, or pulled down by the pull-down connection, to an electric potential that indicates the same logical level as the logical level of the signal input to the pad  4   c.    
         [0110]    If the logical level of the signal input to the pad  4   c  (N 1 ) is reversed to the one of  FIG. 10  so that an L-level signal is input in periods t 0  to t 5  and t 6  to t 7  whereas an H-level signal is input in periods t 5  to t 6 , the output (N 5 ) of the exclusive OR gate  14  and the output (N 6 ) of the holding circuit  18  are exactly the same as in  FIG. 9  in t 2  and the subsequent periods. In this case, the pull-up circuit  12  or the pull-down circuit  13  is also controlled such that the pad  4   d  is pulled up by the pull-up connection, or pulled down by the pull-down connection, to an electric potential that indicates the same logical level as the logical level of the signal input to the pad  4   c.    
         [0111]    As described above, according to the third embodiment of the present invention, a period in which the reset signal is at the L level (for example, period to which reset is applied) is positioned as an operation mode selection period, and the exclusive OR gate  14  selects an operation mode during this period in the same manner as in the first embodiment and the second embodiment. When a period in which the reset signal is at the H level (for example, period in which reset is canceled) arrives, the holding circuit  18  holds the output of the exclusive OR gate  14  to establish the operation mode. The selector  20  at this point comes to output a signal that is selected from outputs of the inverter  19  and, from then on, the pull-up circuit  12  or the pull-down circuit  13  is controlled depending on the logical level of the signal input to the pad  4   c . Specifically, the pull-up circuit  12  or the pull-down circuit  13  is controlled such that the pad  4   d  is pulled up by the pull-up connection, or pulled down by the pull-down connection, to an electric potential that indicates the same logical level as the logical level of the signal input to the pad  4   c . In short, the third embodiment has the effects of the first embodiment and an additional effect obtained when the lead  5   c  and the pad  4   d  are bonded to each other by one of the bonding wires  6 . The additional effect is that a current flowing from the lead  5   c  into the pad  4   d , or a current flowing from the pad  4   d  into the lead  5   c , is reduced because the pad  4   d  is pulled up or pulled down to the same logical level as the logical level of a signal input from the lead  5   c.    
       Fourth Embodiment 
       [0112]    The structure and operation of the semiconductor device  1  according to a fourth embodiment of the present invention will be described with reference to  FIGS. 11 to 16 . The difference of the fourth embodiment from the first to third embodiments is that a mode pad has a role as a signal pad in addition to a role as an operation mode selection pad. In the fourth embodiment, components identical to the ones of the first to third embodiments are denoted by the same reference symbols and descriptions on those components will be omitted. 
         [0113]      FIG. 11  shows the structure of the semiconductor device  1  according to the fourth embodiment, and corresponds to a detailed structural diagram of the portion A circled by the dotted line of  FIG. 1 . A pad  4   fa  and a pad  4   fb  are signal/mode pads which double as signal pads and mode pads. The pad  4   fa  and the pad  4   fb  both communicate signals in some cases, and are therefore connected to the functional block  9 . 
         [0114]    A lead  5   e  is an external terminal that is bonded to the pad  4   fa  or the pad  4   fb  by one of the bonding wires  6 . Since at least one of the pad  4   fa  and the pad  4   fb  must function as a signal pad as mentioned above, there are three connection patterns for connection between the lead  5   e  and the pads  4   fa  and  4   fb : 1) the lead  5   e  is bonded to the pad  4   fa  and the pad  4   fb , 2) the lead  5   e  is bonded only to the pad  4   fa , and 3) the lead  5   e  is bonded only to the pad  4   fb . In other words, whereas the pad  4   c  and the lead  5   c  have to be always bonded to each other by one of the bonding wires  6  in the first to third embodiments, it is sufficient in the fourth embodiment if at least one of the pad  4   fa  and the pad  4   fb  is bonded to the lead  5   e , and either of the pad  4   fa  and the pad  4   fb  can be the pad that is bonded to the lead  5   e.    
         [0115]    The operation mode selection circuit  8   d  selects one of the above three connection patterns, namely, three different operation modes, and outputs an operation mode switching signal to the functional block  9 . 
         [0116]      FIG. 12  is a circuit diagram of the operation mode selection circuit  8   d . Power supply relations (connection relations with the pad  4   b  and the pad  4   e ) are omitted from the circuit diagram. As shown in  FIG. 12 , the operation mode selection circuit  8   d  has the pull-up circuit  12 , pull-down circuit  13 , inverter  19 , and selector  20  of  FIG. 8  for each of the pad  4   fa  and the pad  4   fb.    
         [0117]    More specifically, a pull-up circuit  12   a  and a pull-down circuit  13   a  are connected to the pad  4   fa , and a selector  20   a  which outputs signals for controlling the pull-up circuit  12   a  and the pull-down circuit  13   a  is provided for the pad  4   fa . The input of the selector  20   a  is connected to the pad  4   fb  and an inverter  19   a . The selector  20   a  thus has the function of a switching circuit that switches between a state in which the pad  4   fb  is connected to the output of the selector  20   a  and a state in which the output of the inverter  19   a  is connected to the output of the selector  20   a  based on an output from the delay element  16 . A pull-up circuit  12   b  and a pull-down circuit  13   b  are connected to the pad  4   fb , and a selector  20   b  which outputs signals for controlling the pull-up circuit  12   b  and the pull-down circuit  13   b  is provided for the pad  4   fb . The input of the selector  20   b  is connected to the pad  4   fa  and an inverter  19   b . The selector  20   b  thus has the function of a switching circuit that switches between a state in which the pad  4   fa  is connected to the output of the selector  20   b  and a state in which the output of the inverter  19   b  is connected to the output of the selector  20   b  based on an output from the delay element  16 . 
         [0118]    The operation mode selection circuit  8   d  has logic change detecting circuits (toggle flip-flops)  21   a  and  21   b , an operation mode determining circuit  22 , a delay element  23 , and a holding circuit  24 , in addition to the components of  FIG. 8 . 
         [0119]    The toggle flip-flop (T-FF)  21   a  is connected to the pad  4   a , the pad  4   fa , and the operation mode determining circuit  22 . The T-FF  21   a  outputs an L-level signal upon reception of an L-level reset signal from the pad  4   a . When detecting a change in logic of the pad  4   fa  while receiving an H-level reset signal from the pad  4   a , the T-FF  21   a  inverts its own output. The T-FF  21   b  is connected to the pad  4   a , the pad  4   fb , and the operation mode determining circuit  22 . When detecting a change in logic of the pad  4   fb  while receiving an H-level reset signal from the pad  4   a , the T-FF  21   b  inverts its own output. 
         [0120]    The T-FF  21   a  and the T-FF  21   b  are for detecting a change in logic that occurs in one of the pad  4   fa  and the pad  4   fb  that is not bonded to the lead  5   e  when the output of the delay element  16  changes from the H level to the L level. For instance, when the lead  5   e  is bonded only to the pad  4   fa , a change in logic of the output of the delay element  16  changes the output of the selector  20   b , and the change is accompanied by a change in logic of the pad  4   fb  which is not bonded to the lead  5   e . The T-FF  21   b  detects this change and outputs the detection result to the operation mode determining circuit  22 . Since the logic change detecting circuits  21  of  FIG. 12  are constituted of T-FFs, a logic change caused in the pad  4   fa  or the pad  4   fb  inverts the output of the T-FF  21   a  or of the T-FF  21   b  (from the L level to the H level). The operation mode determining circuit  22  recognizes a logic change in the pad  4   fa  or the pad  4   fb  by receiving an H-level signal from the T-FF  21   a  or the T-FF  21   b.    
         [0121]    The operation mode determining circuit  22  receives as inputs an output of the holding circuit  18 , an output of the T-FF  21   a , and an output of the T-FF  21   b , and outputs a 2-bit signal to the holding circuit  24 .  FIG. 13  shows input-output relations of the operation mode determining circuit  22  in the form of a truth table. In  FIG. 13 , when the output (N 7 ) of the holding circuit  18  is L, the output (N 8 ) of the T-FF  21   a  is L, and the output (N 9 ) of the T-FF  21   b  is L, the output (N 10 ) of the operation mode determining circuit  22  is LL (b00 in binary notation, the same applies below). When N 7  is H, N 8  is L, and N 9  is H, N 10  is LH (b01). When N 7  is H, N 8  is H, and N 9  is L, N 10  is HL (b10). When N 7 , N 8 , and N 9  are other combinations than the aforementioned combinations, N 10  is HH (b11). The operation mode determining circuit  22  thus determines the connection state of the lead  5   e  and the pad  4   fa  based on the output of the holding circuit  18  and the output of the T-FF  21   a , and determines the connection state of the lead  5   e  and the pad  4   fb  based on the output of the holding circuit  18  and the output of the T-FF  21   b . In the case where the pad  4   fa  and the pad  4   fb  are both, but separately, connected to the lead  5   e , the operation mode determining circuit  22  can determine the connection state from the output of the holding circuit  18  alone. In short, the operation mode determining circuit  22  has the function as a judging circuit that determines the state of connection from the outside to the pad  4   fa  and the pad  4   fb.    
         [0122]    The delay element  23  delays a reset signal input to the pad  4   a  by a given period of time when the reset signal is output to the holding circuit  24 . The delay put by the delay element  23  is set larger than the delay put by the delay element  16 . 
         [0123]    The holding circuit  24  receives as inputs an output of the operation mode determining circuit  22  and an output of the delay element  23 , and outputs a 2-bit signal. When it is an L-level signal that is received from the delay element  23 , the holding circuit  24  outputs a signal output from the operation mode determining circuit  22  as it is (lets the signal pass through). When it is an H-level signal that is received from the delay element  23 , the holding circuit  24  holds the output. A 2-bit signal output from the holding circuit  24  is input as an operation mode switching signal to the functional block  9 . 
         [0124]    Described next is how the operation mode selection circuit  8   d  operates.  FIGS. 14 to 16  are timing charts illustrating the operation of the operation mode selection circuit  8   d . The pull-up circuit  12   a  and other components introduced in the fourth embodiment operate the same way as their equivalents of the third embodiment, and a detailed description on the operation of those components will be omitted. 
         [0125]      FIG. 14  shows operation timing for a case where the pad  4   fa  and the pad  4   fb  are connected to the lead  5   e  separately by different bonding wires  6 . Since the pad  4   fa  and the pad  4   fb  are both connected to the lead  5   e , the pads  4   fa  and  4   fb  receive the same signal from the lead  5   e . The exclusive OR gate  14  therefore outputs an L-level signal which indicates a match throughout the entire period (t 0  to t 7 ). The example shown in  FIG. 14  is a case where the pad  4   fa  (N 1 ) and the pad  4   fb  (N 2 ) receive H-level signals throughout the entire period (t 0  to t 7 ). As shown in  FIG. 14 , at t 1 , the reset signal (N 3 ) changes to the L level, causing the output (N 7 ) of the holding circuit  18 , the output (N 8 ) of the T-FF  21   a , and the output (N 9 ) of the T-FF  21   b  to change from an indefinite value to the L level. The change also changes the output (N 10 ) of the operation mode determining circuit  22  to LL (b00). 
         [0126]    At t 2 , the output (N 4 ) of the selector  20   a  and the output (N 5 ) of the selector  20   b  are changed, but no logic changes occur in the pad  4   fa  (N 1 ) and the pad  4   fb  (N 2 ) since the pad  4   fa  and the pad  4   fb  are both bonded to the lead  5   e.    
         [0127]    At t 3 , the output (N 11 ) of the delay element  23  is changed. The length of time from t 1  to t 3  thus corresponds to a delay put by the delay element  23 . The holding circuit  24  at this point receives the delayed L-level reset signal from the delay element  23 , and changes its own output (N 12 ) from an indefinite value to LL (b00). 
         [0128]    At t 4 , the reset signal (N 3 ) changes to the H level. The output (N 7 ) of the holding circuit  18  is thus held at the L level. 
         [0129]    At t 5 , the output (N 4 ) of the selector  20   a  and the output (N 5 ) of the selector  20   b  are changed. The changes cause no logic changes in the pad  4   fa  (N 1 ) and the pad  4   fb  (N 2 ) as is the case for t 2 . Accordingly, while the T-FF  21   a  and the T-FF  21   b  can detect changes in logic in the periods subsequent to t 4 , the output (N 8 ) of the T-FF  21   a  and the output (N 9 ) of the T-FF  21   b  do not change during those periods. 
         [0130]    At t 6 , the output (N 11 ) of the delay element  23  changes to the H level, and the output (N 12 ) of the holding circuit  24  is held. In other words, the operation mode switching signal is established at LL (b00). For example, if Operation Mode One is to be selected when the operation mode switching signal is LL (b00), the functional block  9  activates functions relevant to Operation Mode One upon reception of the operation mode switching signal “LL (b00)”. 
         [0131]      FIG. 15  shows operation timing for a case where the pad  4   fa  alone is bonded to the lead  5   e  by one of the bonding wires  6 . The electric potential of the pad  4   fb  which is not connected to the lead  5   e  is determined by controlling the pull-up circuit  12  and the pull-down circuit  13 . The example shown in  FIG. 15  is a case where the pad  4   fa  (N 1 ) receives H-level signals throughout the entire period (t 0  to t 7 ). 
         [0132]    As shown in  FIG. 15 , at t 1 , the reset signal (N 3 ) changes to the L level, causing the output (N 7 ) of the holding circuit  18 , the output (N 8 ) of the T-FF  21   a , and the output (N 9 ) of the T-FF  21   b  to change from an indefinite value to the L level. Receiving those signals, the output (N 10 ) of the operation mode determining circuit  22  changes to LL (b00). 
         [0133]    At t 2 , the output (N 5 ) of the selector  20   b  changes from the L level to the H level, and the pad  4   fb  (N 2 ) is accordingly pulled down to the L level. The output (N 6 ) of the exclusive OR gate  14  at this point changes to the H level, which indicates a mismatch, and, in response, the output (N 7 ) of the holding circuit  18  changes to the H level. As a result, the operation mode determining circuit  22  receives as inputs the output (N 7 ) of the holding circuit  18 =H, the output (N 8 ) of the T-FF  21   a =L, and the output (N 9 ) of the T-FF  21   b =L, which changes the output (N 10 ) of the operation mode determining circuit  22  to HH (b11). 
         [0134]    At t 3 , the output (N 11 ) of the delay element  23  changes to the L level, causing the output (N 12 ) of the holding circuit  24  to change from an indefinite value to HH (b11). 
         [0135]    At t 4 , the reset signal (N 3 ) changes to the H level. The output (N 7 ) of the holding circuit  18  is thus held at the H level. 
         [0136]    At t 5 , the output (N 5 ) of the selector  20   b  changes to the L level, causing a logic change in the pad  4   fb  (N 2 ) from the L level to the H level. Since the T-FF  21   a  and the T-FF  21   b  can detect changes in logic in the periods subsequent to t 4 , the logic change caused in the pad  4   fb  (N 2 ) is detected, and the detection causes the output (N 9 ) of the T-FF  21   b  to invert from the L level to the H level. As a result, the output (N 7 ) of the holding circuit  18 =H, the output (N 8 ) of the T-FF  21   a =L, and the output (N 9 ) of the T-FF  21   b =H are input to the operation mode determining circuit  22 , thereby changing the output (N 10 ) of the operation mode determining circuit  22  to LH (b01). The holding circuit  24  receives the output (N 10 ) of the operation mode determining circuit  22 , and the output (N 12 ) of the holding circuit  24  is accordingly changed to LH (b01). 
         [0137]    At t 6 , the output (N 11 ) of the delay element  23  changes to the H level, and the output (N 12 ) of the holding circuit  24  is latched. In other words, the operation mode switching signal is established at LH (b01). For example, if Operation Mode Two is to be selected when the operation mode switching signal is LH (b01), the functional block  9  activates functions relevant to Operation Mode Two upon reception of the operation mode switching signal “LH (b01)”. 
         [0138]      FIG. 16  shows operation timing for a case where the pad  4   fb  alone is bonded to the lead  5   e  by one of the bonding wires  6 . The difference from  FIG. 15  is that it is the pad  4   fb  that is connected to the lead  5   e  instead of the pad  4   fa . The timing chart of  FIG. 16  is obtained by switching the pad  4   fa  (N 1 ), the output (N 5 ) of the selector  20   a , and the output (N 8 ) of the T-FF  21   a  of  FIG. 15  with the pad  4   fb  (N 2 ), the output (N 6 ) of the selector  20   b , and the output (N 9 ) of the T-FF  21   b , respectively. 
         [0139]    As shown in  FIG. 16 , at t 5 , the output (N 7 ) of the holding circuit  18 =H, the output (N 8 ) of the T-FF  21   a =H, and the output (N 9 ) of the T-FF  21   b =L are input to the operation mode determining circuit  22 , thereby changing the output (N 10 ) of the operation mode determining circuit  22  to HL (b10). The holding circuit  24  receives the output (N 10 ) of the operation mode determining circuit  22 , and the output (N 12 ) of the holding circuit  24  is accordingly changed to HL (b10). 
         [0140]    At t 6 , the output (N 11 ) of the delay element  23  changes to the H level, and the output (N 12 ) of the holding circuit  24  is latched. In other words, the operation mode switching signal is established at HL (b10). For example, if Operation Mode Three is to be selected when the operation mode switching signal is HL (b10), the functional block  9  activates functions relevant to Operation Mode Three upon reception of the operation mode switching signal “HL (b10)”. 
         [0141]    As described above, the fourth embodiment of the present invention employs the pad  4   fa  and the pad  4   fb  which double as signal pads and mode pads, thereby providing three different operation modes to select from based on three connection patterns: 1) the pad  4   fa  and the pad  4   fb  are each bonded to the lead  5   e , 2) the pad  4   fa  alone is bonded to the lead  5   e , and 3) the pad  4   fb  alone is bonded to the lead  5   e . While two pads, the pad  4   c  (signal pad) and the pad  4   d  (mode pad), provide two operation mode options in the first to third embodiments, two pads in the fourth embodiment, the pad  4   fa  (signal/mode pad) and the pad  4   fb  (signal/mode pad), provide three operation mode options. The fourth embodiment thus has the effects of the first embodiment and an additional effect of enabling the semiconductor device  1  to set more operation modes than in the first to third embodiments. 
         [0142]    The first to third embodiments of the present invention have described a structure in which one mode pad (pad  4   d ) is installed. Alternatively, two or more mode pads may be installed. In a structure that has two mode pads (pads  4   d ), there are two possible bonding wire connection patterns per mode pad (pad  4   d ), and a selection can be made from four different operation modes in total. 
         [0143]    The semiconductor device  1  according to the fourth embodiment of the present invention may have three or more signal/mode pads (pads  4   f ). In the case where three signal/mode pads (pads  4   fa ,  4   fb , and  4   fc ) are installed, operation mode switching signals are calculated for all combinations of the pads  4   f : the pad  4   fa  and the pad  4   fb , the pad  4   fb  and the pad  4   fc , and the pad  4   fc  and the pad  4   fa , thereby obtaining seven different operation modes in total to select from. The first to third embodiments can provide seven operation mode options if one signal pad (pad  4   c ) and three mode pads (pads  4   d ), four pads in total, are installed, which are more pads than the fourth embodiment needs to provide seven operation mode options. Keeping the number of pads low helps to reduce the chip size. 
         [0144]    The second to fourth embodiments use a reset signal input from the pad  4   a  as a signal to be input to the inverter  15 , the holding circuit  18 , and other components. However, other signals than the reset signal may be employed instead. 
         [0145]    The signal pad (pad  4   c ) of the first to third embodiments is an input/output terminal. In the above description, the signal pad (pad  4   c ) functions during operation mode selection as a pad that receives an input signal from the lead  5   c , namely, an input terminal. Instead, the pad  4   c  may function during operation mode selection as an output terminal. This is accomplished by having the internal circuit  7  output a given signal to the pad  4   c . Alternatively, the pad  4   c  may be pulled down to the L level by the pull-down resistor  11  (or pulled up to the H level by the pull-up resistor  10 ) in order to function as an output terminal. 
         [0146]    The first to fourth embodiments describe an example in which the leads (external terminals)  5  and the pads (internal terminals)  4  are bonded to each other by the bonding wires  6 , but the external terminals do not need to be leads. An example in which the external terminals are not leads is shown in  FIGS. 17 and 18 . 
         [0147]      FIGS. 17 and 18  show a case of applying the first to fourth embodiments of the present invention to a wire connection type ball grid array (BGA) package.  FIG. 17  is a plan view viewed from above the chip  2 , and  FIG. 18  is a sectional view taken along the line B-B′ of  FIG. 17 . As shown in  FIGS. 17 and 18 , the external terminals are conductor patterns  26  arranged on a printed board  25 . 
         [0148]    As shown in  FIGS. 17 and 18 , the semiconductor device  1  is structured such that a half of the printed board  25  is covered with the mold resin  3  to cover the chip  2  mounted onto the printed board  25 . The conductor patterns (external terminals)  26  are arranged on the printed board  25 , and are bonded to the pads  4 , which are on the chip  2 , by the bonding wires  6 . The pad  4   c  and the pad  4   d  which are relevant to operation mode selection are connected to a conductive pattern  26   c . The conductor patterns  26  are connected to solder balls  28  through printed wiring lines  27 . 
         [0149]    The first to fourth embodiments describe an example in which the leads (external terminals)  5  and the pads (internal terminals)  4  are bonded to each other by the bonding wires  6 , but other means than wires may connect the external terminals and the internal terminals to each other. An example in which other means than wires are employed is shown in  FIGS. 19 to 21 . 
         [0150]      FIGS. 19 to 21  show a case of applying the present invention to a flip chip connection type BGA package.  FIG. 19  is a plan view showing the chip  2  and the printed board  25  (+bumps  29 ) separately, and  FIG. 20  is a sectional view taken along the line C-C′ of  FIG. 19 . The chip  2  and the printed board  25  of  FIG. 19  are stuck together through the bumps  29  such that C and C′ of the chip  2  coincide with C and C′ of the printed board  25 , respectively. The internal terminals and the external terminals of  FIGS. 19 and 20  are connected to each other by the bumps  29 . 
         [0151]    As shown in  FIGS. 19 and 20 , the chip  2  is mounted as a flip chip to the printed board  25  to structure the semiconductor device  1 . The bumps  29  are sandwiched between the pads  4  formed on the chip  2  and the conductor patterns  26  formed on the printed board  25 , and electrically connect the pads  4  and the conductor patterns  26 . The mold resin  3  is filled between the chip  2  and the printed board  25 . The conductor patterns  26  are connected to the solder balls  28  through the printed wiring lines  27 . 
         [0152]    As shown in  FIGS. 19 and 20 , the pad  4   c  is connected to the conductor pattern  26   c  by a bump  29   a . The pad  4   d , which is a mode pad, is connected to the conductor pattern  26   c  by a bump  29   b . In other words, the bump  29   b  is present when an external terminal is bonded to the pad  4   d  and is absent when no external terminal is bonded to the pad  4   d . An operation mode can be selected based on the presence or absence of the bump  29   b.    
         [0153]    In the case where no external terminal is bonded to the pad  4   d , a structure as the one shown in  FIG. 21  may be employed.  FIG. 21  is similar to  FIG. 20  and corresponds to a sectional view taken along the line C-C′ of  FIG. 19 . The difference is that the conductor pattern  26   c  of  FIG. 20  is divided into conductor patterns  26   a  and  26   b  in  FIG. 21 . 
         [0154]    As shown in  FIG. 21 , the pad  4   c  is connected to the conductor pattern  26   a  by the bump  29   a , and the conductor pattern  26   a  is connected to one of the solder balls  28  through a printed wiring line  27   a . The pad  4   d , which is a mode pad, is connected to the conductor pattern  26   b  by the bump  29   b , and the conductor pattern  26   b  is connected to one of the solder balls  28  through a printed wiring line  27   b.    
         [0155]    In the structure of  FIG. 21 , the printed wiring line  27   b  is present when an external terminal is bonded to the pad  4   d  and is absent when no external terminal is bonded to the pad  4   d . In short, an operation mode can be selected based on the presence or absence of the printed wiring line  27   b . The solder balls  28  correspond to external terminals in  FIG. 21 . Operation mode selection may be based on the presence or absence of the conductor pattern  26   b  instead of the printed wiring line  27   b . Further, operation mode selection may be based on the presence or absence of the printed wiring line  27   b  and the conductor pattern  26   b  both. 
         [0156]    As has been described, the semiconductor device according to the present invention can detect what connection state an external terminal and an internal terminal for operation mode selection are in irrespective of the logical level (H level/L level) of a signal input to an internal terminal that has to be placed adjacent to the operation mode selection internal terminal. This eliminates the need for the internal terminal that has to be placed adjacent to the operation mode selection internal terminal to be a specific internal terminal (power supply pad, ground pad, or reset pad). In other words, freedom of layout is secured in placement of the operation mode selection internal terminal. 
         [0157]    Although the invention has been described above in connection with several preferred embodiments thereof, it will be appreciated by those skilled in the art that those embodiments are provided solely for illustrating the invention, and should not be relied upon to construe the appended claims in a limiting sense.