Abstract:
Display unevenness is suppressed. A display device includes pixels ( 22 ) arranged in matrix, each including a current-driven type light emitting element (EL) and a drive transistor (Tr 3 ) for supplying a current to the current-driven type light emitting element (EL). The current-driven type light emitting element (EL) is driven by dividing each frame period into a plurality of sub-frame periods for lighting time. The drive transistor is controlled under current write driving using two write currents having a ratio of 1:1/2 N  and a sum of the two write currents.

Description:
[0001]    The present invention claims the benefit of Japanese Patent Application No. 2010-23287, filed in Japan on Feb. 4, 2010, which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a display device in which pixel data for display is written into each pixel arranged in matrix, and to a drive method for the display device. 
         [0004]    2. Description of the Related Art 
         [0005]    There have been proposed various types of display devices, typified by the one disclosed in Japanese Patent Application Laid-open No. 1998-214060, in which gradation display is performed by dividing each frame period into a plurality of sub-frame periods for driving. 
         [0006]      FIG. 1  illustrates a configuration of a circuit of one pixel (pixel circuit) in an organic electroluminescence (EL) display device of time-division gradation display mode disclosed in Japanese Patent Application Laid-open No. 1998-214060. In a simple 2T-1C configuration (including two transistors and one capacitor), when a gate line is at high level, a transistor Tr 11  is turned ON to write a data voltage on a data line into a storage capacitor Ch. When the gate line becomes low level and the transistor Tr 11  is turned OFF, a transistor Tr 12  is driven with the voltage stored in the storage capacitor Ch so that a drive current corresponding to the data voltage flows through an organic EL element EL. 
         [0007]    In a normal driving mode, the data line voltage is controlled to control a current of the transistor Tr 12 , thereby controlling the emission amount (luminance) of the organic EL element EL. Further, in the normal driving mode, the transistor Tr 12  is used in the saturation region, and the current flowing through the transistor Tr 12  is a current I d , which is determined by a threshold voltage V th , mobility μ, a gate width W, and a gate length L of the transistor Tr 12 , as expressed in the following expression. 
         [0000]        I   d   =μC   o ( W/L )( V   gs   −V   th ) 2    
         [0000]    where V gs  is a gate-source potential difference and C o  is a gate capacitance per unit area. In a thin film transistor (TFT) formed on a glass substrate, especially a low-temperature polysilicon (LIPS) TFT, the values of the threshold voltage V th  and the mobility μ are varied among pixels, resulting in a problem of uneven display. 
         [0008]    As a method for solving the problem, the data voltage on the data line is written so that the transistor Tr 12  may be completely turned ON to serve as a simple switch (linear region operation) for directly applying “(positive power supply voltage PVDD)-(negative power supply voltage CV)” to the organic EL element, thereby performing gradation display under lighting control with each frame divided into a plurality of sub-frames.  FIG. 2  illustrates an example of the lighting method for 4-bit gradation display. As in the example, lighting time is set to T 1 , T 2  (=2T 1 ), T 4  (=4T 1 ), or T8 (=8T 1 ) corresponding to each bit. 
         [0009]    The voltage-driven type device illustrated in  FIG. 1  as the related art has a problem of screen burn-in because luminance becomes lowered as the current amount is reduced by the influence of voltage rise due to the temporal change in the organic EL element. There is another problem that the luminance depends on pixel positions and becomes uneven because of the currents flowing through the organic EL elements in a plurality of pixels as well as voltage drop in power lines. Further, if the number of display gradations is increased, a sub-frame period becomes too short to ensure sufficient write time, which is also a problem. 
         [0010]    In view of the above-mentioned problems, as in Japanese Patent Application Laid-open No. 2002-351357, a time-division gradation display device using a current-driven type pixel drive circuit has been proposed. However, such a display device has problems that luminance becomes uneven because of fluctuations in individual current writing and that sufficient write time cannot be ensured. 
         [0011]    As exemplified in Japanese Patent Application Laid-open No. 2006-243060, some ideas concerning the problem of the write time inherent in the current-driven type have been proposed. However, there still remains a problem in cost because a multi-bit current source driver has a complicated configuration and it is difficult to set individual current values with accuracy. Further, because the current luminous efficiency of the organic EL element is improving year by year, it is not unusual that a maximum drive current in one pixel of the display device is 1 mA or less. In such a case, a problem of the accuracy in minimum gradation arises. 
       SUMMARY OF THE INVENTION 
       [0012]    The present invention provides a display device including pixels arranged in matrix, each including a current-driven type light emitting element and a drive transistor for supplying a current to the current-driven type light emitting element, in which: the current-driven type light emitting element is driven by dividing each frame period into a plurality of sub-frame periods for lighting time; and the drive transistor is controlled under current write driving using two write currents having a ratio of 1:1/2 N  and a sum of the two write currents. 
         [0013]    Further, it is preferred that the display device according to the present invention further include two current sources for generating the two write currents, and that each write current be generated by a combination of the two write currents from the two current sources. 
         [0014]    Further, it is preferred that, in the display device according to the present invention, when defining that a lighting period in a shortest sub-frame of the plurality of sub-frame periods is 1, a total of the lighting periods of the plurality of sub-frame periods be 2 N −1 so as to perform N-bit gradation display, and to perform 2N-bit gradation display when combined with a drive current value of the write current. 
         [0015]    Further, it is preferred that, in the display device according to the present invention, when defining that a shortest sub-frame period among the plurality of sub-frame periods is 1, each frame be constituted by one sub-frame having a length of 2 k , where k is 0 to N−3, and three sub-frames each having a length of 2 N-2 , thereby providing redundancy to reduce false contouring of a moving image. 
         [0016]    It is possible to suppress the influence of voltage rise due to fluctuations in the drive TFTs and the temporal change in the current-driven type light emitting element, and to perform uniform display operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    In the accompanying drawings: 
           [0018]      FIG. 1  is a diagram illustrating a configuration of a conventional pixel circuit; 
           [0019]      FIG. 2  is a diagram illustrating an operation of conventional time-division gradation driving; 
           [0020]      FIG. 3  is a diagram illustrating an overall configuration of a display device; 
           [0021]      FIG. 4  is a diagram illustrating configurations of a pixel circuit and a source driver; 
           [0022]      FIG. 5  is a diagram illustrating a write operation; 
           [0023]      FIG. 6  is a diagram illustrating an emission operation; 
           [0024]      FIG. 7  is a diagram illustrating waveforms in respective sections; 
           [0025]      FIG. 8  is a diagram illustrating gradation expression in one-pixel lighting; 
           [0026]      FIG. 9  is a diagram illustrating drive timings of gate lines; 
           [0027]      FIG. 10  is a diagram illustrating a drive timing concept; 
           [0028]      FIG. 11  is a diagram illustrating another drive timing concept; 
           [0029]      FIG. 12  is a diagram illustrating an example of current switching for precharging; 
           [0030]      FIG. 13  is a diagram illustrating another gradation expression in one-pixel lighting; 
           [0031]      FIG. 14  is a diagram illustrating a lighting example in one-pixel lighting; and 
           [0032]      FIG. 15  is a diagram illustrating a lighting example of one-pixel lighting at redundant lighting timings. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0033]    Now, an embodiment of the present invention is described below with reference to the accompanying drawings. 
       [Outline] 
       [0034]    In this embodiment, pixel portions are subjected to current write type control, in which a write current having a maximum current value and a write current having another current value are set. The another current value is suppressed to a relatively small ratio of 1/2 N , such as 1/8 or 1/16, of the maximum current value so that lighting time control is performed within a range for high-speed writing by using the two write current values of the maximum current and 1/2 N  thereof. 
         [0035]    In this way, the order in a section for time gradation control is reduced by N bits, thereby solving the problem of the write time, which is inherent in a display device using a current-driven type circuit of time gradation display mode, to realize high-order gradation display. In addition, providing only two current set values offers an advantage in cost because of simple management and simple circuitry. It is also possible to improve luminance uniformity in the display device as a whole by integrating a circuit for correcting the two current values into a current writing section so that fluctuations in current among source lines may be corrected. 
       Embodiment 
       [0036]      FIG. 3  illustrates an overall configuration of a display device as an embodiment.  FIG. 4  illustrates a configuration of one pixel portion and a configuration of a source driver for one line. 
         [0037]    As illustrated in  FIG. 3 , an image signal, a horizontal synchronization signal, a vertical synchronization signal, and other control signals are supplied to a timing control current selection circuit  10 . A current selection signal indicating image data (bit data) of each pixel and a horizontal control signal indicating its timing are generated based on the image signal, the horizontal synchronization signal, and the like, and then supplied to a source driver  12 . 
         [0038]    The source driver  12  is connected to a current detection correction value writing section  14 . The current detection correction value writing section  14  detects each current value of current sources provided for each column in the source driver  12  as described later, and determines a correction value therefor. The current detection correction value writing section  14  is connected to a correction memory  16 , and the determined correction value of the current sources for each column is written into the correction memory  16  by the current detection correction value writing section  14 . A current correction control section  18  reads out the correction value stored in the correction memory  16  according to a column having pixels to be written, and supplies the read correction value to the source driver  12 . Therefore, each constant current value of the two current sources provided for each column in the source driver  12  is corrected by the correction value stored in the correction memory  16 . 
         [0039]    A vertical control signal from the timing control current selection circuit  10  is supplied to a gate driver  20 . The gate driver  20  sequentially supplies power to gate lines Gate provided for rows of pixels  22 . In other words, the source driver  12  sequentially receives the current selection signals on the pixels and outputs the image signal on the pixels in each column, and the image signal is controlled to be supplied to a corresponding row selected by the gate driver  20 . 
         [0040]    Note that, each pixel  22  is supplied with power supply voltages PVDD and CV. In general, one of the power supply voltages is connected to a supply electrode of an organic electroluminescence (EL) element and another thereof is connected to a drive transistor. 
         [0041]      FIG. 4  illustrates a pixel circuit corresponding to one pixel, and a write circuit of current write type for pixel data, which is provided for each column of the source driver  12 . 
         [0042]    The pixel  22  is constituted by three transistors and one capacitor. A transistor Tr 1  has a source connected to a data line DataB and a drain connected to a gate of a transistor Tr 3 . A transistor Tr 2  has a source connected to a data line DataA and a drain connected to a source of the transistor Tr 3 . A storage capacitor Ch is disposed between the gate and source of the transistor Tr 3 . The transistor Tr 3  has a drain connected to the power source PVDD having a voltage V PVDD . The source thereof is connected to an anode of an organic EL element EL. The organic EL element EL has a cathode connected to the power source CV having a voltage V CV . Note that, in the organic EL element EL, the anode serves as a pixel electrode and the cathode serves as a common electrode for all the pixels. 
         [0043]    In the source driver  12 , two current sources  24 A and  24 B are provided. The current source  24 A has a constant current I max  and the current source  24 B has a constant current I max /2 N . The current source  24 A and the current source  24 B are connected in common via a switch  26 A and a switch  26 B, respectively. A common connection terminal of the switches  26 A and  26 B is connected to a negative input terminal of an operational amplifier  28 . A positive input terminal of the operational amplifier  28  is connected to a power source V X  and supplied with a voltage V x . An output terminal thereof is connected to the data line DataB. The common connection terminal of the switches  26 A and  26 B, which is connected to the negative input terminal of the operational amplifier  28 , is further connected to the data line DataA. The example of  FIG. 4  illustrates the data lines DataA and DataB in the m-th column. 
         [0044]    In the configuration described above, the circuits used as the pixel circuit and the source driver have a simple 3T-1C configuration and form a feedback loop in two source lines by the operational circuit and the current sources illustrated in the upper part of  FIG. 4 , so as to shorten the write time. 
         [0045]      FIGS. 5 and 6  illustrate the principles of writing and light emission in the configuration described above, respectively. In  FIGS. 5 and 6 , a current source  24  represents a current source which is formed of the current sources  24 A and  24 B and the switches  26 A and  26 B and is thus capable of adjusting the current amount, and the current source  24  supplies a current I x =f(V in ). In other words, the current amount to be output is set by controlling ON/OFF of the switches  26 A and  26 B according to a data signal V in . 
         [0046]    In the configuration described above, when a horizontally-extending gate line n (Gate) is changed to high level to turn ON selection TFTs (transistor Tr 1  and transistor Tr 2 ), the circuit including the operational amplifier operates as a voltage follower. Then, a gate voltage of the transistor Tr 3  is controlled so that a source potential V x ′ of the transistor Tr 3  may be equal to the voltage V x  at the positive input terminal of the operational amplifier  28 . 
         [0047]    On this occasion, the reference voltage V x  of the voltage follower is set to a voltage for turning OFF the organic EL element EL as a light emitting element, and hence the current I x  drawn into the current source  24  becomes equal to a current I x ′ flowing through the transistor Tr 3 . Then, the gate potential of the transistor Tr 3  at that time is charged into the storage capacitor Ch. 
         [0048]    In other words, if both of the transistors Tr 1  and Tr 2  are turned ON, as illustrated in  FIG. 5 , no current flows through the organic EL element EL but the current I x =I x ′ flows through the transistor Tr 3 , with the result that the source voltage V x ′ thereof becomes equal to a negative input terminal voltage (=positive input terminal voltage V x ) of the operational amplifier. A gate-source voltage of the transistor Tr 3  on this occasion is a voltage V(I x ) at which the current I x  flows through the transistor Tr 3 . Therefore, the gate voltage of the transistor Tr 3  takes a value determined by adding the gate-source voltage V(I x ) to the source voltage V x . 
         [0049]    Subsequently, the gate line n is changed to low level to turn OFF the transistors Tr 1  and Tr 2 , and the voltage charged in the storage capacitor Ch maintains the gate-source voltage of the transistor Tr 3 , allowing the organic EL element to emit light by bootstrapping. In other words, the transistor Tr 3  maintains the current I x , and an anode voltage of the organic EL element EL is increased to a voltage V z  which is obtained when the current I x  flows through the organic EL element, with the result that the organic EL element emits light. 
         [0050]      FIG. 7  illustrates voltage waveforms at that time. The gate lines Gate are sequentially turned ON. The data signal V in  sequentially supplies the constant current source  24  with data on pixels in each row. Accordingly, the constant current source  24  sequentially supplies the current I x  corresponding to the data signal V in . 
         [0051]    In  FIG. 7 , I x ′ to I OLED  represent each state of pixels in the n-th row. When the gate line n is at the high level, the current I x ′ of the transistor Tr 3  becomes equal to the current I x . On this occasion, a gate-source voltage V gs  of the transistor Tr 3  is set to the voltage V(I x ) corresponding to the current I x , and the voltage V(I x ) is stored in the storage capacitor Ch. In a write period, the anode voltage V z  of the organic EL element EL becomes equal to the voltage V x ′ (=V x ), and a gate voltage V g  of the transistor Tr 3  becomes higher than the anode voltage of the organic EL element EL by V(I x ). 
         [0052]    When the transistors Tr 1  and Tr 2  are turned OFF, the data line DataA and the data line DataB are disconnected from the pixel circuit but the gate-source voltage V gs  of the transistor Tr 3  is maintained, and hence the current I x ′ of the transistor Tr 3  and the current I of the organic EL element EL are both made equal to the current I x . 
         [0053]    Next, description is given of gradation control with the current amounts of the current sources  24 A and  24 B set to I max  and I max /8, which is 1/8 of I max , respectively. 
         [0054]    In Drive Example 1, those two kinds of drive currents and three kinds of sub-frames (T 1 , 2T 1 , and 4T 1 ) are used to perform gradation display of 6 bits in total.  FIG. 8  illustrates an example of lighting one pixel,  FIG. 9  illustrates drive waveforms of the gate lines in this case, and  FIG. 10  is a conceptual diagram thereof. 
         [0055]    If the minimum average luminance is obtained when the pixel is lit with I max /8 for T 1 , the maximum average luminance corresponds to the case of lighting with “I max /8+I max ” for a whole period, and is estimated as (1+8)×(1+2+4)=63 times the minimum average luminance. In other words, luminance obtained by lighting with the current “I max /8+I max ” for a period 7T 1  is a maximum average luminance L max , and an average luminance obtained by lighting with the current I max /8 only for the period T 1  takes L max /63. The gradation expression of 6 bits from 0 to 63 can be performed by a combination of L max ×1/63, L max ×2/63, L max ×4/63, and L max ×8/63 illustrated in  FIG. 8 . 
         [0056]    As illustrated in  FIGS. 9 and 10 , the gate lines are sequentially driven with respect to the respective sub-frames to write data, to thereby perform lighting control on the respective sub-frames. 
         [0057]    As Drive Example 2,  FIG. 11  illustrates a conceptual diagram of drive waveforms for weakening the constraints on drive time.  FIG. 11  illustrates the case where two gate lines are written at the same timing during horizontal writing. The write period is divided and data is written in pixels in the two corresponding lines. Note that, it is also preferred that the constraints on the drive time be further weakened by multi-line writing, such as simultaneous writing for three lines. 
         [0058]    Further, as illustrated in  FIG. 12 , it is also preferred that the write time be reduced by performing precharge operation of activating the current I max  for a short period of time during the writing with I max /8. This enables reliable data writing into the storage capacitor Ch based on a small current value. 
         [0059]    Still further, it is also preferred that the outputs of the circuits in the source driver  12  be cramped to V CV  during turn-OFF operation, thereby performing the turn-OFF operation reliably and speedily. In other words, in a sub-frame in which light is OFF, during the write period, V CV  may be supplied to the positive input terminal of the operational amplifier  28  while bypassing V X  in  FIG. 4 , so as to quickly discharge the charges stored in the storage capacitor Ch. 
         [0060]      FIG. 13  illustrates an example of lighting one pixel for gradation display of 8 bits in total using two drive currents of I max  and I max /16, which is 1/16 of I max , and simple sub-frames. In this example, in order to perform the gradation display of 8 bits, the number of sub-frame bits is 4 and the drive current ratio is set to 2 4 . 
         [0061]    This configuration has a problem of occurrence of false contouring. Specifically, for example, a gradation change point as illustrated in  FIG. 14  is present in a moving image. In this example, when the sub-frames are switched from luminance levels  127  to  128 , the gradation is changed from the full-lighting for the period 7T 1  in the first half and the lighting with the minimum luminance for the period 8T 1  in the second half, to the turn-OFF in the first half and the full-lighting in the second half. 
         [0062]    Regarding such a large change point, the longest sub-frame is divided into two, and as illustrated in  FIG. 15 , display with redundant level of lighting is performed while switching the lighting as appropriate on a frame basis or a pixel basis, to thereby make the false contouring less visually recognizable. In other words, the sub-frame of 8T 1  is eliminated but three sub-frames of 4T 1  are provided so that three kinds of lighting modes may be formed for 128 gradations, and the lighting modes are selected as appropriate to reduce the occurrence of false contouring. 
         [0063]    Further, if the source driver in the configuration of  FIG. 6  is configured as an external IC, it is possible to test the organic EL element in the display portion before mounted, and hence the yield of display devices is improved. In this case, it is preferred in view of accuracy and cost that the current detection and correction sections be built in the external IC. 
         [0064]    Note that, the configuration of this embodiment is also applicable to a display device using other current-driven type light emitting elements than the organic EL element.