Abstract:
The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Continuation-In-Part of pending U.S. patent application Ser. No. 14/103,066, filed on Dec. 11, 2013, which is a Continuation of U.S. patent application Ser. No. 13/332,658, filed on Dec. 21, 2011, now U.S. Pat. No. 8,633,588, issued on Jan. 21, 2014. The entireties of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor package, and in particular, to a solder resist layer design of a flip chip package. 
         [0004]    2. Description of the Related Art 
         [0005]    For the conventional flip chip package, it is well known that the underfill protects the conductive bumps by considerably reducing the stress to the conductive bumps. However, the underfill itself is subject to shear or peeling stress and consequently, may induce failure modes. For instance, an imperfect underfill with voids or microcracks will produce cracks or delamination under temperature cycling conditions. 
         [0006]    Delamination at bimaterial interfaces such as the underfill and conductive traces, driven by coefficient of thermal expansion (CTE) mismatching between organic underfills and inorganic conductive traces, is one of failure modes. Once the underfill delamination, occurs, failure usually results from conductive bump fatigue cracks because of the loss of the underfill protection and stress concentration arising from the underfill delamination. 
         [0007]    Thus, a novel flip chip package without the underfill delamination is desirable. 
       BRIEF SUMMARY OF INVENTION 
       [0008]    A semiconductor package is provided. An exemplary embodiment of a semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resist layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resist layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace. 
         [0009]    Another exemplary embodiment of a semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resist layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein the extending portion of the solder resist layer has a vertical sidewall extruding over to an adjacent vertical sidewall of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  shows a top view of one exemplary embodiment of a semiconductor package of the invention. 
           [0013]      FIG. 2  shows a cross section along line A-A′ of  FIG. 1 . 
           [0014]      FIG. 3  shows a cross section along line B-B′ of  FIG. 1 . 
           [0015]      FIG. 4  shows a top view of another exemplary embodiment of a semiconductor package of the invention. 
           [0016]      FIG. 5  shows a cross section along line A-A′ of  FIG. 4 . 
           [0017]      FIG. 6  shows a cross section along line B-B′ of  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF INVENTION 
       [0018]    The following description is a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts. 
         [0019]    The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice of the invention. 
         [0020]      FIG. 1  shows a top view of one exemplary embodiment of a semiconductor package  500   a  of the invention.  FIG. 2  shows a cross section along line A-A′ of  FIG. 1 .  FIG. 3  shows a cross section along line B-B′ of  FIG. 1 . One exemplary embodiment of a semiconductor package  500   a  is a flip chip package using copper pillars connecting a semiconductor die and a substrate. As shown in  FIGS. 1-3 , one exemplary embodiment of a semiconductor package  500   a  comprises a substrate  200  with first conductive traces  204  and second conductive traces  202  disposed thereon. In one embodiment, the substrate  200  may be formed of by semiconductor materials such as silicon, or organic materials such as bismaleimide triacine, (BT), polyimide or ajinomoto build-up film (ABF). In one embodiment, the first conductive trace  204  and the second conductive trace  202  may comprise signal traces or ground traces, which are used for input/output (I/O) connections of a semiconductor die  210  mounted directly onto the substrate  200 . In this embodiment, each of the first conductive traces  204  serves as a signal/ground trace segment for routing, and each of the second conductive traces  202  has a portion  202   a  as a pad region of the substrate  200 . 
         [0021]    Next, still referring to  FIGS. 1-3 , a solder resist layer  206  is conformably formed covering the substrate  200  by a deposition method and then the solder resist layer  206  is subjected to a patterning process. After the patterning process, the solder resist layer  206 , except for extending portions  208 , exposes an overlapping region between a subsequently mounted semiconductor die  210  and the substrate  200 . It is noted that the extending portions  208  of the solder resist layer  206  extends along the first conductive trace  204  and covering a portion of the first conductive trace  204 . Also, the solder resist layer  206 , except for extending portions  208 , is disposed away from the subsequently mounted semiconductor die  210  by a distance d1. In one embodiment, the solder resist layer  206  may comprise solder mask materials, oxide, nitride, or oxynitride. As shown in  FIG. 2 , the extending portions  208  of the solder resist layer  206  covers a portion  204   a  of the first conductive trace  204 . It is noted that a width W2 of the extending portion  208  of the solder resist layer  206  is designed to be larger than a width W1 of the portion  204   a  of the first conductive trace  204 , so that a portion of a bottom surface  209  of the extending portion  208  of the solder resist layer  206  is exposed from the  204   a  of the first conductive trace  204 , and the extending portion  208  of the solder resist layer  206  has a vertical sidewall  207  extruding over to an adjacent vertical sidewall  205  of the portion  204   a  of the first conductive trace  204 . Therefore, the extending portion  208  and the portion  204   a  of the first conductive trace  204  collectively have a T-shaped cross section. 
         [0022]    Next, a dry film photoresist or a liquid photoresist (not shown) is entirely laminated on the substrate  200 . Next, the dry film photoresist/liquid photoresist is patterned by a photolithography process comprising an exposure step and a development step to form openings (not shown) respectively over the portions (pad regions)  202   a  of the second conductive traces  202 , so that formation positions of a subsequently formed conductive pillar may be defined. 
         [0023]    Then, the conductive pillars  212  are respectively formed on the portions (pad regions)  202   a  of the second conductive traces  202 , filling the openings of the dry film photoresist/liquid photoresist. Alternatively, conductive buffer layers (not shown) formed of Ni may be formed between the conductive pillars  212  and the portions (pad regions)  202   a  of the second conductive traces  202 , and the conductive buffer layers may serve as seed layers, adhesion layers and barrier layers for the conductive pillars  212  formed thereon. In one embodiment, the conductive pillars  212  are used as a solder joint for a subsequently formed conductive bump, which transmits input/output (I/O), ground or power signals of the semiconductor die  210 , formed thereon. Therefore, the conductive pillars  212  may help to increase the mechanical strength of the bump structure. In one embodiment, the conductive pillars  212  may be formed of copper. Next, the dry film photoresist/liquid photoresist is removed by a stripping process such as a wet etching process using a suitable etchant. 
         [0024]    Next, still referring to  FIGS. 1-3 , the semiconductor die  210  has a plurality of conductive bumps  214  formed on bond pads (not shown) of the semiconductor die  210  mounted on the substrate  200 . The conductive bumps  214  respectively connect to the portions (pad regions)  202   a  of the second conductive traces  202  through the conductive pillars  212  therebetween. As shown in  FIG. 1 , the solder resist layer  206  is disposed away from the portions (pad regions)  202   a  of the second conductive traces  202 , which overlap with the conductive pillars  212 , by at least a distance d2. As shown in  FIG. 3 , the extending portion  208  of the solder resist layer  206  is below the semiconductor die  210 , over a bottom surface  224  of the semiconductor die  210  and within a projection area  222  of the semiconductor die  210 . 
         [0025]    Next, referring to  FIGS. 2-3 , a molding compound  220 ′ may be formed over the substrate  200  and cover the semiconductor die  210 , the first and second conductive traces  204  and  202 , and the solder resist layer  206 , and flow to fill a gap between the substrate  200  and the semiconductor die  210  to compensate for differing coefficients of thermal expansion (CTE) between the substrate, the conductive traces and the semiconductor die. The molding compound  220 ′ is then cured. In one embodiment of the invention, the portion of the bottom surface  209  of the extending portion  208  of the solder resist layer  206  is wrapped by the molding compound  220 ′. After the aforementioned processes, one exemplary embodiment of a semiconductor package  500   a  is completely formed. 
         [0026]      FIG. 4  shows a top view of one exemplary embodiment of a semiconductor package  500   b  of the invention.  FIG. 5  shows a cross section along line A-A′ of  FIG. 4 .  FIG. 6  shows a cross section along line B-B′ of  FIG. 4 . One exemplary embodiment of a semiconductor package  500   b  is a flip chip package using solder bumps but not copper pillars for a connection between a semiconductor die and a substrate. As shown in  FIGS. 4-6 , one exemplary embodiment of a semiconductor package  500   b  comprises a substrate  300  with first conductive traces  304  and second conductive traces  302  disposed thereon. In one embodiment, the substrate  300  may be formed of by semiconductor materials such as silicon, or organic materials such as bismaleimide triacine, (BT), polyimide or ajinomoto build-up film (ABF). In one embodiment, the first conductive trace  304  and the second conductive trace  302  may comprise signal traces or ground traces, which are used for input/output (I/O) connections of a semiconductor die  310  mounted directly onto the substrate  300 . In this embodiment, each of the first conductive traces  304  serves as a signal/ground trace segment for routing, and each of the second conductive traces  302  has a portion  302   a  as a pad region of the substrate  300 . 
         [0027]    Next, still referring to  FIGS. 4-6 , a solder resist layer  306  is conformably formed covering the substrate  300  by a deposition method and then the solder resist layer  306  is subjected to a patterning process. After the patterning process, the solder resist layer  306 , except for extending portions  308 , exposes an overlapping region between a subsequently mounted semiconductor die  310  and the substrate  300 . It is noted that the extending portions  308  of the solder resist layer  306  extends along the first conductive trace  304  and covering a portion of the first conductive trace  304 . Also, the solder resist layer  306 , except for extending portions  308 , is disposed away from the subsequently mounted semiconductor die  310  by a distance d1. In one embodiment, the solder resist layer  306  may comprise solder mask materials, oxide, nitride, or oxynitride. As shown in  FIG. 5 , the extending portions  308  of the solder resist layer  306  covers a portion  304   a  of the first conductive trace  304 . It is noted that a width W2 of the extending portion  308  of the solder resist layer  306  is designed to be larger than a width W1 of the portion  304   a  of the first conductive trace  304 , so that a portion of a bottom surface  309  of the extending portion  308  of the solder resist layer  306  is exposed from the  304   a  of the first conductive trace  304 , and the extending portion  308  of the solder resist layer  306  has a vertical sidewall  307  extruding over to an adjacent vertical sidewall  305  of the portion  304   a  of the first conductive trace  304 . Therefore, the extending portion  308  and the portion  304   a  of the first conductive trace  304  collectively have a T-shaped cross section. 
         [0028]    Next, referring to  FIGS. 4-6 , a solder printing process is performed to form solder paste patterns (not shown) on the portions (pad regions)  302   a  of the second conductive traces  302 . Next, a semiconductor die  310  having a plurality bond pads (not shown) is mounted on the substrate  300 . Bond pads (not shown) of the semiconductor die  310  respectively connect the solder paste patterns. Next, a reflow process and a cooling process are performed in sequence, so that the solder paste patterns are transformed into solder bumps  312  connecting the portions (pad regions)  302   a  of the second conductive traces  302  of the substrate  300  and the bond pads (not shown) of the semiconductor die  310 . As shown in  FIG. 4 , the solder resist layer  306  is disposed away from the portions (pad regions)  302   a  of the second conductive traces  302 , which overlap with the solder bumps  312 , by at least a distance d2. As shown in  FIG. 6 , the extending portion  308  of the solder resist layer  306  is below the semiconductor die  310 , over a bottom surface  324  of the semiconductor die  310  and within a projection area  322  of the semiconductor die  310 . 
         [0029]    Next, referring to  FIGS. 5-6 , a molding compound  320 ′ may be formed over the substrate  300  and cover the semiconductor die  210 , the first and second conductive traces  204  and  202 , and the solder resist layer  206 , and flow to fill a gap between the substrate  300  and the semiconductor die  310  to compensate for differing coefficients of thermal expansion (CTE) between the substrate, the conductive traces and the semiconductor die. The molding compound  320 ′ is then cured. In one embodiment of the invention, the portion of the bottom surface  309  of the extending portion  308  of the solder resist layer  306  is wrapped by the molding compound  320 ′. After the aforementioned processes, another exemplary embodiment of a semiconductor package  500   b  is completely formed. 
         [0030]    Some advantages of exemplary embodiments of a semiconductor package  500   a  and  500   b  of the invention are described in the following. The molding compound wraps the portion of the bottom surface of the extending portion of the solder resist layer, which has a wider width than the portion of the first conductive trace, so that the molding compound may be anchored with a T-shaped feature formed by both the extending portion of the solder resist layer and the portion of the first conductive trace. Thus, the conventional underfill delamination problem occurring between the conductive trace and the underfill material is improved. Also, the extending portion of the solder resist layer only extends into a projection area of the die to cover a portion of the first conductive trace, and the remaining portion of the solder resist layer is disposed away from the semiconductor die by a distance, so that the semiconductor package still has enough space to allow the molding compound to flow to fill the gap between the substrate and the semiconductor die. Therefore, the extending portion of the solder resist layer does not affect the formation of the molding compound. Moreover, exemplary embodiments of a semiconductor package can be used in many types of package methods. For example, a gap between the substrate and the semiconductor die can be filled with a molding compound only. Alternatively, the gap between the substrate and the semiconductor die can be filled with a molding compound and an underfill material. Further, the gap between the substrate and the semiconductor die can be filled with an underfill material only. 
         [0031]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.