Abstract:
An I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the I/O buffer circuit; and a first and second tracking circuits to bias each of said pull-up and pull-down devices in response to voltages internal and external to the I/O buffer circuit in a shutdown mode.

Description:
TRADEMARKS  
       [0001]     IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present disclosure relates generally to electrical and electronic circuits and more specifically to prevention of leakage current during PAD overshoot and undershoot.  
         [0004]     2. Description of Background  
         [0005]     CMOS bi-directional interface circuits generally require some tolerance to voltage over/undershoots at a driver/receiver interface terminal, referred to herein as a PAD, caused by mismatch impedance between the output of the driver/receiver and the transmission line. Interface circuit electrical specifications often require a certain amount of over/undershoot tolerance be designed into the I/O. For example, the electrical specification for a Universal Serial Bus interface circuit requires an I/O operating between 0-3.3V to be capable of withstanding continuous exposure to a −1V to 4.6V signal.  
         [0006]     Two unique problems occur in the driver circuit of an I/O when the PAD voltage extends beyond the supply rail voltages (i.e. VDD and GND). First, the drain-substrate or drain-nwell diodes can forward bias causing unwanted leakage current from PAD to VDD or from GND to PAD. Second, the transistors making up the output stage of the driver can turn on slightly even when the driver is supposed to be disabled (e.g., the driver is in receive mode).  
         [0007]      FIG. 1  illustrates the output stage of a typical bidirectional driver. The gate nodes of the output FETs are controlled by pre-drive circuits that tune the rise and fall times of the driver signal. The PAD pin is the output of the driver and also the input of the receiver circuit (not shown). The I/O circuitry runs off a 3.3V power supply in this example. In the event of an overshoot, the PAD pin can reach 4.6V. The drain of the pFET rises to a higher potential than the n-well that is connected to VDD330 (3.3V). As a result, the PFET drain to well junction becomes forward biased, and current is allowed to flow from PAD to VDD330 supply. Similarly, in the event of an undershoot, the PAD pin can reach −1.0V. The drain of the NFET falls to a lower potential than the substrate that is connected to ground (0.0V). As a result, the NFET drain to substrate junction becomes forward biased, and current is allowed to flow from GND to PAD.  
         [0008]     Specific to the case when the bi-drectional I/O is in receive mode, the driver circuit should be disabled. From  FIG. 1 , this happens when both pull-up and pull-down transistors in the driver are cut off (i.e., the pFET gate is at 3.3V and the nFET gate is at 0.0V). As long as the PAD voltage does not extend beyond the supply rails, these transistors remain off. However, the output pFET in the driver will turn on slightly if the PAD experiences an overvoltage e.g., PAD goes up to 4.6V). This is because the pFET drain voltage exceeds the gate voltage. The result is unwanted current flow from PAD to VDD330 supply through the pFET. Similarly, the output nFET in the driver will turn on slightly if the PAD experiences an undervoltage (e.g., PAD goes to −1V). This is because the nFET gate voltage exceeds the drain voltage. The result is unwanted current flow from GND supply to PAD through the nFET.  
         [0009]     Accordingly, a leakage current prevention scheme is needed.  
       SUMMARY  
       [0010]     The shortcomings of the prior art are overcome and additional advantages are provided through the provision of test generation methods.  
         [0011]     Exemplary embodiments include an I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the IC; and a first and second tracking circuits to bias each of said pull-up and pull-down devices in response to voltages internal and external to the IC in a shutdown mode.  
         [0012]     Exemplary embodiments also include an I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the IC; and a first and second tracking circuits to bias each of said pull-up and pull-down devices in response to voltages internal and external to the IC in a shutdown mode, wherein the driver circuit further comprises one or more transistors in series, the first and second biasing circuits comprise one or more transistors in series, the first and second tracking circuits comprise one or more transistors in parallel, the first floating well is a n-well and the second floating well is a p-well, and the circuit provides overvoltage and undervoltage protection.  
         [0013]     System and computer program products corresponding to the above-summarized methods are also described and claimed herein.  
         [0014]     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.  
       TECHNICAL EFFECTS  
       [0015]     As a result of the summarized invention, technically we have achieved a solution that prevents current leakage during over/undershoot. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:  
         [0017]      FIG. 1  illustrates the output stage of a typical bidirectional driver;  
         [0018]      FIG. 2  illustrates an exemplary circuit that completely eliminates unwanted currents in the event of PAD over-voltage or under-voltage; and  
         [0019]      FIG. 3  illustrates sample waveforms corresponding to the operation of the circuit in  FIG. 2 . 
     
    
       [0020]     The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.  
       DETAILED DESCRIPTION  
       [0021]     The disclosed circuit takes advantage of the ability to float an isolated p-well in a CMOS triple-well process technology. The output nFETs of the driver are placed in p-wells that are biased independent of the substrate voltage. A circuit that sets the well voltage to always be the lower potential of ground or PAD controls the floating p-well voltage. The p-well is set to the ground potential under normal operation, but in the event of an undershoot, the p-well floats to the PAD voltage. In this way, the problem of leakage currents from ground to PAD caused by a forward biased drain-substrate diode can be avoided.  
         [0022]     This disclosed circuit also addresses the driver transistors turning on while the I/O is receiving a signal that presents voltage over/undershoots. The problem is corrected by implementing a feedback loop within the driver circuit that prevents the driver output transistors from turning on during receive mode, and does not adversely affect the performance of the driver in drive mode.  
         [0023]     Referring now to  FIG. 2 , a circuit that completely eliminates unwanted currents in the event of PAD over-voltage or under-voltage is illustrated generally as  100 . The transistors making up the output stage of the CMOS driver are TP 1  and TN 1 . The protection circuit is broken into two parts: floating well and gate feedback.  
         [0024]     The floating well circuit consists of two pFET transistors (T 2  and T 3 ) and two nFET transistors (T 4  and T 5 ). The pFET transistors T 2  and T 3  control the n-well voltage for the output stage of the I/O driver and the nFET transistors T 4  and T 5  control the p-well voltage for the output stage of the I/O driver. In one embodiment, the nFETs are placed within an isolated p-well that is biased independent from the rest of the substrate. Therefore, a triple well technology is used to implement this scheme.  
         [0025]     During normal operation, the voltage at PAD is between VDD330 (3.3V) and GND (0V). In this mode, T 2  is on while T 3  is off. The n-well (node “NW”) for the pFET TP 1  is held at VDD330. Transistor T 5  is on while T 4  is off. The isolated p-well (node “PW”) for the nFET output driver is held at GND. During an overshoot, PAD can reach 4.6V, causing T 3  to turn on and T 2  to turn off. As a result, the n-well voltage, NW, rises to whatever the PAD voltage is, thereby insuring that the output pFET drain-n-well junction can never forward bias. In other words, the pFET n-well voltage always floats to the higher of VDD330 or PAD. During an undershoot, PAD can reach −1V, causing T 5  to turn off and T 4  to turn on. As a result, the isolated p-well voltage, PW, falls to whatever the pad voltage is, thereby insuring that the output nFET drain to p-well junction can never forward bias. In other words, the nFET p-well voltage always floats to the lower of PAD or GND.  
         [0026]     Referring now to  FIG. 3 , waveforms for PAD, NW and PW are illustrated. The NW node is always held at VDD330 (3.3 Volts) unless an overshoot exists at PAD; during an overshoot, the NW node rises to the PAD voltage. Likewise, the PW node is always held at GND (0 Volts) unless an undershoot exists at PAD; during undershoot, the PW node falls to the PAD voltage.  
         [0027]     In one embodiment, only the pFETs and nFETs that are connected directly or indirectly to PAD need to be placed in the floating n-wells and p-wells. All other pFETs may be placed in n-wells connected to VDD330 and all other nFETs may be placed in the substrate connected to GND.  
         [0028]     Returning now to  FIG. 2 , the circuit also addresses the driver transistors turning on when the I/O is receiving an overshoot or undershoot signal. The problem is corrected by implementing a feedback loop between PAD and the gates of the output driver transistors. Transistor TP 4  connects PAD to the gate of TP 1 . If the voltage of PAD exceeds the VDD330 voltage, then TP 4  will turn on and raise the gate voltage of TP 1  to track with PAD. In this way, the pFET TP 1  is never allowed to turn on in receive mode due to an over-voltage at PAD. Similarly, transistor TN 4  connects PAD to the gate of TN 1 . If the voltage of PAD extends below GND, then TN 4  will turn on and lower the gate voltage of TN 1  to track with PAD. In this way, the nFET TN 1  is never allowed to turn on in receive mode due to an under-voltage at PAD.  
         [0029]     The function of the pass gate (made up of TP 5  and TN 5 ) depends on the I/O mode. While in drive mode, the pass gate passes an undistorted signal from the pre-drive to the output pFET TP 1 . During receive mode, the pass gate TP 5 , TN 5  prevents current from flowing back to the pre-drive stage in the event of a PAD voltage overshoot. Similarly, the pass gate (made up of TP 6  and TN 6 ) passes an undistorted signal from the pre-drive to the output nFET TN 1 . In receive mode, the pass gate TP 6 , TN 6  prevents current from flowing from the pre-drive stage in the event of a PAD voltage undershoot.  
         [0030]     Transistors TP 8 , TN 8 , TP 9  and TN 9  change the mode of the pass gates. While in drive mode (TS=3.3V and TSBAR=0.0V), the nodes EN 0  and EN 1  are 3.3V and 0.0V, respectively. While in receive mode (TS=0.0V and TSBAR=3.3V), the nodes EN 0  and EN 1  remain at these values unless the PAD has a voltage over/undershoot. If the PAD voltage is higher than VDD330, then node EN 1  assumes the value of PAD and keeps TP 5  from turning on, which prevents current flow back into the pre-drive stage. If the PAD voltage is lower than GND, then node EN 0  assumes the value of PAD and keeps TN 6  from turning on, which prevents current from the pre-drive forward.  
         [0031]     In one embodiment, transistors TP 8  and TN 9  may be sized much larger than TN 8  and TP 9  to avoid degradation in signal integrity through the pass gates while in driving mode. In an alternative embodiment, device TP 7  and TN 7  can be used to ensure signal integrity during normal driving mode.  
         [0032]     The circuit  100  illustrated in  FIG. 2  prevents junction leakage from drain to substrate of PMOS transistor TP 1  when the PAD voltage is higher than VDD330, and prevents junction leakage from drain to substrate of NMOS transistor TN 1  when the PAD voltage is lower than GND. In addition, the circuit  100  turns PMOS transistor TP 1  off completely even when the PAD voltage is higher than VDD330, turns NMOS transistor TN 1  off completely even when the PAD voltage is lower than GND, and ensures that no transistor has a gate oxide voltage that exceeds the maximum allowable oxide voltage for the technology.  
         [0033]     In one embodiment, the voltages applied to nodes VBIAS 1  and VBIAS 0  are generated according to the following equations: 
 
 V BIAS1= V pad(max)− V ox(max) 
 
 V BIAS0= V ox(max)+ V pad(min) 
 
 where Vpad(max) is the maximum overshoot voltage at PAD, Vpad(min) is the minimum undershoot voltage at PAD, and Vox(max) is the maximum gate oxide allowed by the technology. For example, the PAD voltage will reach 4.6V during an overshoot and the maximum gate oxide voltage allowed is 3.6V. Thus, VBIAS 1  would need to be 4.6-3.6 or 1.0V. Similarly, the pad voltage will reach −1V during an undershoot. Thus, VBIAS 0  would need to be 3.6+(−1) or 2.6V. 
 
         [0034]     The circuit  100  includes a driver output stage, n-well biasing circuit, p-well biasing circuit, PMOS gate tracking circuit, and NMOS gate tracking circuit. Operationally, the circuit can be broken down into four modes: driving a logic high, driving a logic low, receiving a logic high (possibly with overshoot), and receiving a logic low (possibly with undershoot).  
         [0035]     When the circuit  100  is in drive high mode, the inputs PREDRIVE_ 1  and PREDRIVE_ 0  are both 0V. The driver enable inputs TS and TSBAR are 3.3V and 0V respectively. Output transistors TP 1  and TP 2  are on while transistors TN 1  is off. This causes the output, PAD, to rise to VDD (3.3V). The pre-drive signal, PREDRIVE_ 1 , propagates through transistor TN 5  because the gate of the transistor TN 5  is connected to VDD (3.3V). The gate of TP 2  is controlled by VBIAS 1  (1.0V) and the gate of T 14  is controlled by VBIAS 0  (2.6V) according to the equations given in the previous section. With the pad at 3.3V and the gate of passgate T 18  at 1.0V, the passgate T 18  is on. The 3.3V at the pad propagates through T 18  to the drain of TP 4 , keeping it off. The n-well bias circuit made up of T 2  and T 3  sets the floating NW node to 3.3V. There is no leakage current through the parasitic p-n junction diode at the drain of TP 1  because the drain and substrate are both 3.3V. The input PREDRIVE_ 0  is set to 0V and propagates through the passgate TN 6  to the gate of TN 1 . The signal is allowed to propagate through TN 6  because EN 0  is 3.3V. The node EN 0  is set to 3.3V because TP 8  and T 20  are on. With pad at 3.3V and the gate of passgate T 1  set to VBIAS 0  (2.6V), the node connected to the gate of TN 7  is approximately VBIAS 0 -Vthn (Vthn is threshold voltage of T 1 ). The transistor TN 4  remains off. The p-well bias circuit made up of T 4  and T 5  set the floating PW node to 0V. There is no leakage through the device TN 1  because the gate and source of the device are both at 0V. There is no leakage current through the parasitic n-p junction diode at the drain of TN 1  because the drain and substrate are both 0V.  
         [0036]     When the circuit is in drive low mode, the inputs PREDRIVE_ 1  and PREDRIVE_ 0  are both 3.3V. The driver enable inputs TS and TSBAR are still 3.3V and 0V respectively. Output transistor TP 1  is off while transistors T 14  and TN 1  are on. This causes the output, PAD, to fall to GND (0V). The pre-drive signal, PREDRIVE_ 1 , propagates through transistor TP 5  because the gate of transistor TP 5  is connected to EN 1 . The node EN 1  is set to 0V because the input signal TS is 3.3V causing transistor TN 9  to pull EN 1  to ground. The gate of TP 2  is controlled by VBIAS (1.0V) and the gate of T 14  is controlled by VBIAS 0  (2.6V) according to the equations given in the previous section. With pad at 0V and the gate of passgate T 18  set to VBIAS 1  (1V), the node connected to the gate of TP 7  is approximately VBIAS 1 +Vthp (Vthp is threshold voltage of T 18 ). The transistor TP 4  remains off. The n-well bias circuit made up of T 2  and T 3  sets the floating NW node to 3.3V. There is no leakage through the device TP 1  because the source and gate of the device are both at 3.3V. The input PREDRIVE_ 0  is set to 3.3V and propagates through the passgate TP 6  to the gate of TN 1 . The signal is allowed to propagate through TP 6  because the gate of TP 6  is connected to GND (0V). With pad at 0V and the gate of passgate T 1  set to VBIAS 0  (2.6V), the node connected to the gate of TN 7  is 0V. The transistor TN 4  remains off. The p-well bias circuit made up of T 4  and T 5  sets the floating PW node to 0V. There is no leakage through the device TP 1  because the gate and source of the device are both at 3.3V. There is no leakage current through the parasitic n-p junction diode at the drain of TN 1  because the drain and substrate are both 0V.  
         [0037]     When the circuit is in receive mode the pad may experience an overshoot voltage reaching 4.6V. The input PREDRIVE_ 1  is set to 3.3V and the input PREDRIVE_ 0  is set to 0V. During normal receive mode operation (no overshoot), transistor TP 1  would be turned off by applying 3.3V to the gate and TN 1  would be turned off by applying 0V to the gate. However, since the pad voltage is 4.6V the transistor TP 1  would not remain turned off. To avoid this problem, the pad voltage is passed through transistor T 18  to the drain of TP 4 . The gate of TP 4  is connected to VDD (3.3 v), which turns on the transistor TP 4  and forces the gate of TP 1  to 4.6V also. Therefore, transistor TP 1  remains off even though the pad voltage has exceeded the VDD supply level. At the same time, the 4.6V level passed through transistor T 18  allows the n-well bias circuit, made up of T 2  and T 3 , to set the floating NW node to 4.6V. There is no leakage current through the parasitic p-n junction diode at the drain of TP 1  because the drain and substrate are both 4.6V. Also at the same time, the gate voltage of TP 7  is 4.6V, which turns off the device. The transistor TP 5 , whose gate is connected to EN 1 , is also turned off. Node EN 1  is 4.6V because transistors T 19  is on while TN 9  is off. Since all three transistors TP 7 , TN 5 , TP 5  are off, there is no connection between the gate of TP 1  (now 4.6V) and the PREDRIVE_ 1  input (at 3.3V).  
         [0038]     The node EN 1  can reach 4.6V during overshoot, so it is important that an additional NMOS (TP 9 ) be inserted between T 19  and TN 9 . This prevents an excessively large gate oxide voltage from developing across the gate of TN 9 . With the pad voltage at 4.6V, the transistor T 1  passes a voltage equal to VBIAS 0 −Vtln (where Vthn is the threshold voltage of T 1 ). This voltage level keeps TN 4  off and the p-well bias circuit sets PW to 0V. The signal from PREDRIVE_ 0  (0V) is passed through TN 6  and TN 7  to the gate of TN 1 . Therefore, the transistor TN 1  remains completely off. During an overshoot voltage event at the pad, the transistors TP 2 , T 14  and T 18 , T 1  protect the other transistors (TP 1 , TN 1 , TP 4 , TN 4 , T 3 , T 4 , TN 7 , TP 7 ) from otherwise developing excessively large voltages across their gate oxides or from drain to source.  
         [0039]     When the circuit is in receive mode the pad may experience an undershoot voltage reaching −1V. The input PREDRIVE_ 1  is set to 3.3V and the input PREDRIVE_ 0  is set to 0V. During normal receive mode operation (no undershoot), transistor TP 1  would be turned off by applying 3.3V to the gate and TN 1  would be turned off by applying 0V to the gate. However, since the pad voltage is −1V the transistor TN 1  would not remain turned off. To avoid this problem, the pad voltage is passed through transistor T 1  to the drain of TN 4 . The gate of TN 4  is connected to GND (0V), which turns on the transistor and forces the gate of TN 1  to −1V also. Therefore, transistor TN 1  remains off even though the pad voltage is below the GND supply level. At the same time, the −1V level passed through transistor T 1  allows the p-well bias circuit, made up of T 4  and T 5 , to set the floating PW node to −1V. There is no leakage current through the parasitic n-p junction diode at the drain of TN 1  because the drain and substrate are both −1V. Also at the same time, the gate voltage of TN 7  is −1V, which turns off the device. The transistor TN 6 , whose gate is connected to EN 0 , is also turned off. Node EN 0  is −1V because transistors TN 8  is on while TP 8  is off. Since all three transistors TN 7 , TP 6 , TN 6  are off, there is no connection between the gate of TN 1  (now −1V) and the PREDRIVE_ 0  input (at 0V).  
         [0040]     The node EN 0  can reach −1V during undershoot, so it is important that an additional PMOS (T 20 ) be inserted between TP 8  and TN 8 . This prevents an excessively large gate oxide voltage from developing across the gate of TP 8 . With the pad voltage at −1V, the transistor T 18  passes a voltage equal to VBIAS 1 +Vthp (where Vthp is the threshold voltage of T 18 ). This voltage level keeps TP 4  off and the n-well bias circuit sets NW to 3.3V. The signal from PREDRIVE_ 1  (3.3V) is passed through TP 5  and TP 7  to the gate of TP 1 . Therefore, the transistor TP 1  remains completely off. During an undershoot voltage event at the pad, the transistors TP 2 , T 14  and T 18 , T 1  protect the other transistors (TP 1 , TN 1 , TP 4 , TN 4 , T 3 , T 4 , TN 7 , TP 7 ) from otherwise developing excessively large voltages across their gate oxides or from drain to source.  
         [0041]     The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.  
         [0042]     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.