Abstract:
The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    (a) Field of the Invention 
         [0002]    The present invention relates to a chip testing circuit, and more particularly, to a chip testing circuit that increases the testing throughput. 
         [0003]    (b) Description of the Related Art 
         [0004]    Because of the small size and the powerful functionalities of an integrated circuit (IC), the integrated circuit has become one of the indispensable electronic components of the information technology related equipments. In order to make sure that the chips are working normally, all the chips must go through rigorous testing before shipped out of the factory. For example, a simple testing method inputs a known test signal into the circuit of the chip and then retrieves the cell signal from the circuit of the chip to determine whether the function of the chip is normal or not. 
         [0005]      FIG. 1A  shows a schematic diagram illustrating the write portion of a chip testing circuit  100  in the prior art. The write portion of the chip testing circuit  100  is coupled to the chip testing system (such as a probe card) via the first interface circuit  11  to receive the test signal TS outputted by the chip testing system and to transmit the test signal TS to the write unit  12 . The write unit  12  is coupled to a DRAM cell array  1001  of the chip for inputting the test signal TS to the DRAM cell array  1001  of the chip. In order to increase testing efficiency, the first interface circuit  11  is coupled to a plurality of write units  12  so that the first interface circuit  11  can simultaneously input the testing signal TS into the write units  12  of the same write group  12   a.    
         [0006]      FIG. 1B  shows a schematic diagram illustrating the read portion of a chip testing circuit  100  in the prior art. The read unit  22  receives the cell signal FS transmitted from the DRAM cell array  1001  of the chip and transmits the cell signal to the second interface circuit  21 . On the other hand, the read units  22  of the same read compressing group  22   a  transmit the cell signal FS to the compressing circuit  23  for compression in order to generate a compressing signal CS. The compressing signal CS is then transmitted to the second interface circuit  21 . The second interface circuit  21  then generates a determining signal DS according to the statuses of a cell signal FS and the compressing signal CS and transmits the determining signal to the chip testing system. Thus, the chip testing system can confirm whether the DRAM cell array  1001  of the chip is normal or not according to the determining signal DS. 
         [0007]    As shown in  FIG. 1B , each second interface circuit  21  can access the testing results of the four circuits of the chip that are coupled to the read units  22 . This is the traditional four-terminal input/output signal compressing method (IO compress4 method) commonly used in the industry. However, according to the above-mentioned traditional architecture of the chip testing circuit, two dedicated pins must be utilized to couple the two first interface circuits  11  and the two second interface circuits  21  to the two probes of the chip testing system for correctly testing the chip. Therefore, the number of pins for testing will be increased and the testing cost for the chip will be increased as well. In order to increase the testing speed, more probes have to be used and the overall production cost is further increased. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    One object of the invention is to provide a chip testing circuit (a data compressing chip testing multiplexing circuit), and more particularly, to provide a chip testing circuit that increases the testing throughput and reduces the production cost. 
         [0009]    In order to achieve the above-mentioned purpose, one embodiment of the invention provides a chip testing circuit. The chip testing circuit comprises a plurality of write units, a first interface circuit, a first switch, a plurality of read units, a first compressing circuit, a second compressing circuit, a second interface circuit, a first multiplexer, and a second multiplexer. 
         [0010]    Each of the write units is coupled to at least one memory cell array (or internal circuit) of the chip and the write units are divided into a first write group and a second write group. The first interface circuit is coupled to the write units for receiving a test signal and transmitting the test signal to the write units to input the test signal into the memory cell array of the chip. The first switch is disposed between the first write group and the second write group for selectively coupling the first write group and the second write group. 
         [0011]    Each of the read units is coupled to at least one memory cell array of the chip for receiving the cell signal from the circuit of the chip. The read units are divided into a first group of read units and a second group of read units. The first compressing circuit is coupled to the read units of the first group of read units for compressing the cell signals outputted from the read units to generate a first compressing signal. The second compressing circuit is coupled to the read units of the second group of read units for compressing the cell signals outputted from the read units to generate a second compressing signal. The second interface circuit generates a first determining signal according to the cell signals outputted from the first group of read units and the first compressing signal, or generates a second determining signal according to the cell signals outputted from the second group of read units and the second compressing signal. The first multiplexer is disposed among the second interface circuit, the first group of read units, and the second group of read units for selectively coupling the second interface circuit to the first group of read units or the second group of read units. The second multiplexer is disposed among the second interface circuit, the first compressing circuit, and the second compressing circuit for selectively coupling the second interface circuit to the first compressing circuit or the second compressing circuit. 
         [0012]    Another embodiment of the invention provides a chip testing circuit comprising a first write group, a second write group, a first interface circuit, and a first switch. The first write group comprises a plurality of write units. The second write group also comprises a plurality of write units. The first interface circuit is electrically coupled to the plurality of write units of the first write group constantly. The first switch is disposed between the first write group and the second write group and selectively electrically couples the write units of the second write group to the first interface circuit. Thus, when the first interface circuit receives a test signal, the first interface circuit simultaneously transmits the test signal to the write units of the first write group and the write units of the second write group. 
         [0013]    One other embodiment of the invention provides a chip testing circuit comprising a first group of read units, a first compressing circuit, a second group of read units, a second compressing circuit, a first selecting circuit, a second selecting circuit, and a second interface circuit. The first group of read units is to read a first group of cell signals from the chip. The first group of read units includes a first read unit for reading a first cell signal from the chip. The first compressing circuit is electrically coupled to the first group of read units and generates a first compressing signal according to the first group of cell signals. The second group of read units is to read a second group of cell signals from the chip. The second group of read units includes a second read unit for reading a second cell signal from the chip. The second compressing circuit is electrically coupled to the second group of read units and generates a second compressing signal according to the second group of cell signals. The first selecting circuit is electrically coupled to the first read unit and the second read unit and the first selecting circuit selectively outputs the first cell signal or the second cell signal to thereby generate a first output signal. The second selecting circuit is electrically coupled to the first compressing circuit and the second compressing circuit and the second selecting circuit selectively outputs the first compressing signal or the second compressing signal to thereby generate a second output signal. The second interface circuit is electrically coupled to the first selecting circuit and the second selecting circuit and the second interface circuit determines whether the chip is defective or not according to the first output signal and the second output signal. 
         [0014]    Another embodiment of the invention provides a chip testing circuit comprising a first compressing circuit, a second compressing circuit, a first selecting circuit, a second selecting circuit, and a second interface circuit. The first compressing circuit generates a first compressing signal according to a first group of cell signals outputted from the chip wherein the first group of cell signals includes a first cell signal. The second compressing circuit generates a second compressing signal according to a second group of cell signals outputted from the chip wherein the second group of cell signals includes a second cell signal. The first selecting circuit selectively outputs the first cell signal or the second cell signal for generating a first output signal. The second selecting circuit selectively outputs the first compressing signal or the second compressing signal for generating a second output signal. The second interface circuit is electrically coupled to the first selecting circuit and the second selecting circuit and the second interface circuit determines whether the chip is defective or not according to the first output signal and the second output signal. 
         [0015]    The chip testing circuit according to the embodiments of the invention utilizes the selecting circuit (or the first and the second multiplexers) for switching so that a single second interface circuit can acquire the test data of N groups (N is a positive integer and is less than infinite) of memory cell arrays of the chip. Therefore, the chip testing circuit according to the embodiments of the invention can effectively increase the testing throughput per time unit without increasing the number of the interface circuits and the number of pins. The production cost is reduced and the testing efficiency is increased. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0016]      FIG. 1A  shows a schematic diagram illustrating the write circuit of a chip testing circuit in the prior art; 
           [0017]      FIG. 1B  shows a schematic diagram illustrating the read circuit of a chip testing circuit in the prior art; 
           [0018]      FIG. 2A  shows a schematic diagram illustrating the write circuit of a chip testing circuit according to one embodiment of the invention; 
           [0019]      FIG. 2B  shows a schematic diagram illustrating the read circuit of a chip testing circuit according to one embodiment of the invention; and 
           [0020]      FIG. 3  shows a schematic diagram illustrating the read circuit of a chip testing circuit according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Detail descriptions of the chip testing circuit of the invention will be given herein with reference to the drawings in which one element is represented by the same symbol. 
         [0022]      FIGS. 2A and 2B  show schematic diagrams illustrating the chip testing circuit according to one embodiment of the invention. The chip testing circuit  300  according to one embodiment of the invention comprises the write circuit portion (as shown in  FIG. 2A ) for inputting the test signal TS to the DRAM cell array (or internal circuit)  3001  of the chip and the read circuit portion (as shown in  FIG. 2B ) for acquiring the cell signal FS from the DRAM cell array  3001  of the chip. 
         [0023]    As shown in  FIG. 2A , the write circuit of the chip testing circuit  300  according to one embodiment of the invention comprises a plurality of write units  32 , a first interface circuit  31 , and a first switch  33 . 
         [0024]    Each write unit  32  is coupled to at least one DRAM cell array of the chip. For example, the chip can be a memory component, a memory-containing semiconductor device, or a logic component in a form of a wafer, a bare die, or a packaged chip. The write units  32  according to one embodiment of the invention can be part of the DRAM cell array  3001  of the chip. For example, in the memory component, the write units  32  may operate with the word driver for writing the test data into the specific address of the memory unit. The write units  32  can be divided into a first write group  32   a  and a second write group  32   b.    
         [0025]    The first interface circuit  31  is coupled to the plurality of write units  32 . In one embodiment, the first interface circuit  31  can be electrically coupled (or constantly electrically coupled) to the write units  32  of the first write group  32   a . The first interface circuit  31  can receive the test signal TS inputted from the chip testing system (such as a probe card) and transmit the test signal TS to the write units  32  of the first write group  32   a  and the write units  32  of the second write group  32   b  simultaneously or via time-sharing for inputting the test signal TS to the DRAM cell array of the chip. 
         [0026]    The first switch  33  is disposed between the first write group  32   a  and the second write group  32   b . In one embodiment, the first switch  33  can selectively couple (or electrically couple) the first write group  32   a  and the second write group  32   b  according to a control signal. Or, the first switch  33  can selectively electrically couple the write units  32  of the second write group  32   b  to the first interface circuit  31  when the first interface  31  is constantly electrically coupled to the first write group  32   a . In other words, the first interface circuit  31  can be separately coupled to the write units  32  of the first write group  32   a  or the second write group  32   b . Or, the first interface circuit  31  can be simultaneously coupled to the first write group  32   a  and the second write group  32   b.    
         [0027]    It should be noted that the above-mentioned control signal can be a redundancy address signal. 
         [0028]    As shown in  FIG. 2B , the read circuit of the chip testing circuit  300  according to one embodiment of the invention comprises a plurality of read units  42 , a first compressing circuit  43 , a second compressing circuit  44 , a second interface circuit  41 , a first multiplexer mux 1 , and a second multiplexer mux 2 . 
         [0029]    The plurality of read units  42  are coupled to the DRAM cell array of the chip for receiving the cell signal FS transmitted from the DRAM cell array of the chip. The plurality of read units  42  can be divided into a first group of read units  42   a  and a second group of read units  42   b . In one embodiment, the read units  42  can be part of the DRAM cell array  3001  of the chip. For example, in the memory component, the read units  42  may operate with the sense amplifier for reading the test data stored in the specific address of the memory unit. 
         [0030]    The first compressing circuit  43  is coupled to (or electrically coupled to) the read units  42  of the first group of read units  42   a  for receiving the cell signal FS outputted from the read units  42  of the chip and compressing the cell signal FS to generate a first compressing signal CS 1 . The second compressing circuit  44  is coupled to (or electrically coupled to) the read units  42  of the second group of read units  42   b  for compressing the cell signal FS outputted from the read units  42  to generate a second compressing signal CS 2 . In one embodiment, the first compressing circuit  43  and the second compressing circuit  44  can be exclusive-OR (XOR) circuits. For the case of the first compressing circuit  43 , the first compressing signal CS 1  is a first voltage signal (such as a low voltage signal Low) when the contents of the plurality of cell signals FS transmitted from the plurality of read units  42  of the first group of read unit  42   a  are the same. On the other hand, the first compressing signal CS 1  is a second voltage signal (such as a high voltage signal High) when the contents of the plurality of cell signals FS transmitted from the plurality of read units  42  are not the same. 
         [0031]    The first multiplexer mux 1  can be of various existing selecting circuits or future selecting circuits to be developed and is disposed among the second interface circuit  41 , the first group of read units  42   a , and the second group of read units  42   b . The first multiplexer mux 1  can be selectively coupled to (or electrically coupled to) the read units  42  of the first group of read units  42   a  or the second group of read units  42   b . Thus, the second interface circuit  41  can selectively output the cell signal FS transmitted from the read units  42  of the first group of read units  42   a  or the second group of read units  42   b  for generating a first output signal O 1 . The second multiplexer mux 2  can be of various existing selecting circuits or future selecting circuits to be developed and is disposed among the second interface circuit  41 , the first compressing circuit  43 , and the second compressing circuit  44 . The second multiplexer mu 2  can be selectively coupled to the first compressing circuit  43  or the second compressing circuit  44  for selectively outputting the first compressing signal CS 1  and the second compressing signal CS 2  transmitted from the first compressing circuit  43  and the second compressing circuit  44  to thereby generate a second output signal O 2 . 
         [0032]    The second interface circuit  41  is coupled to (or electrically coupled to) the first multiplexer mux 1  and the second multiplexer mux 2  according to the first output signal O 1  and the second output signal O 2  to generate the first determining signal DS 1  and the second determining signal DS 2  for determining whether the DRAM cell array  3001  of the chip is defective or not. 
         [0033]    In one embodiment, the first interface circuit  31  and the second interface circuit  41  can be the same interface circuit, that is, one interface circuit performs the functions of the first interface circuit  31  and the second interface circuit  41  at the same time. Obviously, in another embodiment, the first interface circuit  31  and the second interface circuit  41  can be two different interface circuits. During testing, the additional redundancy address of the chip testing system, such as the row address A 11  of the probe card, can be utilized to transmit the control signal to the first switch  33 , the first multiplexer mux 1 , and the second multiplexer mux 2  for controlling the operations of the switch and the multiplexers. 
         [0034]    For example, as shown in  FIG. 2A , for the write portion, the chip testing system firstly inputs the test signal TS to the write circuit of the chip testing circuit  300 . The first interface circuit  31  receives the test signal TS while the chip testing system provides a control signal to the first switch  33  via the redundancy address for coupling the first and the second write groups  32   a ,  32   b . Then, the write units  32  of the two write groups  32   a ,  32   b  receive the test signal TS and transmit the test signal TS to the DRAM cell array  3001  of the chip. 
         [0035]    As shown in  FIG. 2B , for the read portion, the first multiplexer mux 1  firstly couples the second interface circuit  41  to the first group of read units  42   a  according to a control signal provided by chip testing system via the redundancy address. Then, the second multiplexer mux 2  also couples the second interface circuit  41  to the first compressing circuit  43  according to the control signal. The second interface circuit  41  then generates a first determining signal DS 1  according to the cell signal FS outputted from the read units  42  of the first group of read units  42   a  and the first compressing signal CS 1 . In one embodiment, the first determining signal DS 1  outputted from the second interface circuit  41  is the cell signal FS of the read unit  42  when the first compressing signal CS 1  is a low voltage signal Low. When the first compressing signal CS 1  is a high voltage signal High, the first determining signal DS 1  outputted from the second interface circuit  41  is a Hi-Z signal, that is, the output terminal of the second interface circuit  41  is in a high impedance state. The chip testing system receives the first determining signal DS 1  and determines the status of the DRAM cell array  3001  of the chip that is coupled to the first group of read units  42   a  according to the first determining signal DS 1 . 
         [0036]    Thereafter, the first multiplexer mux 1  couples the second interface circuit  41  to the read units  42  of the second group of read units  42   b  according to a control signal provided by chip testing system via the redundancy address. Then, the second multiplexer mux 2  also couples the second interface circuit  41  to the second compressing circuit  44  according to the control signal. The second interface circuit  41  then generates a second determining signal DS 2  according to the cell signal FS outputted from the read units  42  of the second group of read units  42   b  and the second compressing signal CS 2 . The chip testing system receives the second determining signal DS 2  and determines the status of the DRAM cell array  3001  of the chip that is coupled to the second group of read units  42   b  according to the second determining signal DS 2 . It should be noted that various modifications or changes regarding the method of how the chip testing system determines the status of the DRAM cell array  3001  of the chip according to the determining signal DS 2  can be performed by those who are skilled in the art according to the above-mentioned descriptions. Further details will not be repeated herein. 
         [0037]    Thus, the chip testing system needs only one probe, that is, just a single contact is needed, when inputting the test signal TS and the determining signals DS 1 , DS 2  to test whether the function of the chip is normal or not (or, determining whether the chip is defective or not). As the number of pins of the chip is reduced, the size and the cost of the chip are also reduced. And since fewer probes are used, the testing speed for a chip can be increased so that the overall production cost can be reduced. The problems of the prior art can thus be solved. 
         [0038]    It should be noted that the first and the second write groups  32   a ,  32   b  of the chip testing circuit according to the above-mentioned embodiments of the invention comprise an equal number of the write units  32 , that is, each comprises four write units  32 . But, the invention is not limited to the above example. In one other embodiment of the invention, the first and the second write groups  32   a ,  32   b  can also comprise different numbers of the write units  32 . Although the first and the second groups of read units  42   a ,  42   b  of the chip testing circuit according to the above-mentioned embodiments of the invention each comprise four read units  42 . But, the invention is not limited to the above example. In one other embodiment of the invention, the first and the second group of read units  42   a ,  42   b  can also comprise different numbers of the read units  42 . Furthermore, in one embodiment, the number of the write units  32  of the first write group  32   a  can be the same as the number of the read units  42  of the first group of read units  42   a . However, in another embodiment, they can be different. Likewise, in one embodiment, the number of the write units  32  of the second write group  32   b  can be the same as the number of the read units  42  of the second group of read units  42   b . However, they can be different in another embodiment of the invention. 
         [0039]    The chip testing circuit according to the embodiments of the invention utilizes the first switch  33 , the first multiplexer mux 1 , and the second multiplexer mux 2  to perform switching so that a single second interface circuit can acquire the test data of N groups (N is a positive integer and is less than infinite) of DRAM cell arrays of the chip. For example, eight groups of data can be acquired according to the above-mentioned embodiments and such method is defined as the eight-terminal input/output signal compressing method (IO compress8 method). Therefore, the chip testing circuit according to the embodiments of the invention can effectively increase the testing throughput per time unit without increasing the number of the second interface circuit and the number of pins. Thus, the production cost is reduced and the testing efficiency is increased. 
         [0040]    It should be noted that various embodiments of the invention can be performed by those who are skilled in the art according to the above-mentioned descriptions. By the operations of the first switch  33 , the first multiplexer mux 1 , and the second multiplexer mux 2  according to the embodiments of the invention, the chip testing circuit can be backward compatible with the four-terminal input/output signal compressing method (IO compress4 method). Those who are skilled in the art can also understand that the chip testing circuit according to the embodiments of the invention is also compatible with the repair algorithm in the prior art and can be implemented accordingly. Likewise, it is also understood by those who are skilled in the art from the above-mentioned descriptions that the chip testing circuit according to the invention can also be upward developed to be the N-terminal (N is a positive integer and is less than infinite) input/output signal compressing method (IO compress N method). For example, a chip testing circuit utilizing sixteen-terminal input/output signal compressing method is shown in  FIG. 3 . The circuit of the read portion of the chip testing circuit is shown in the figure. By properly controlling the six multiplexers mux of the chip testing circuit, the cell signals FS from the read units of the four read compressing circuits are processed separately to determine the status of the DRAM cell array of the chip. Thus, the chip testing circuit utilizes only one interface circuit and one pin for being coupled to the probe of the chip testing system to achieve the effect of receiving sixteen cell signals. The chip testing efficiency is then increased and the cost of testing a chip is reduced. 
         [0041]    Although the description of the invention is by way of above-mentioned examples of embodiment, it should not be construed as any limitation on the scope of the invention. Various modifications or changes can be performed by those who are skilled in the art without deviating from the scope of the invention.