Abstract:
A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry in the cache. Upon determining that the snoop request has a valid entry in the cache, the data is caught and sent to the cache for update.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates generally to a memory management scheme and, more particularly, to using a cache memory with a locking feature to directly access the cache memory for data. 
   2. Description of the Related Art 
   In a large configuration computer system, applications data are transferred from a system memory to computer engines for computation. The computed data will then be transferred back to the system memory before the same set of computed data can be reused by other computing engines. In a large system configuration, there is a hierarchy of memory consisting of a system memory and one or more caches. 
   Generally, level one cache (L 1  cache) is next to a specific computing engine and usually not shared with other computing engines in the system. Level two cache (L 2  cache) is usually shared by computing engines in the system. There may be more levels of cache depending on the architecture and/or complexity of the computer system. 
   Typically, the time consumed by transferring data to and from a system memory becomes a big issue for system performance. If the system design is not well tuned, the computing engine will spend most of the time waiting for data availability. 
   Therefore, there is a need for a system and method for directly accessing a cache for data in a computer system. 
   SUMMARY OF THE INVENTION 
   The present invention provides a system and method for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry in the cache. Upon determining that the snoop request has a valid entry in the cache, the data is caught and sent to the cache for update. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram illustrating a computer system having a single processor directly accessing a cache for data; 
       FIG. 2  is a block diagram illustrating a computer system having two processors directly accessing a cache for data; 
       FIG. 3  is a flow diagram illustrating the operation of the computer system of  FIG. 1 ; and 
       FIG. 4  is a flow diagram illustrating the operation of the computer system of  FIG. 2 . 
   

   DETAILED DESCRIPTION 
   In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. 
   It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code, software and/or integrated circuits that are coded to perform such functions, unless indicated otherwise. 
   Referring to  FIG. 1  of the drawings, the reference numeral  100  generally designates a computer system having a single processor directly accessing a cache for data. The computer system  100  comprises a first bus controller  102 , a system bus  104 , a system memory  106 , a second bus controller  108 , a cache  110 , and a processor  112 . The first bus controller  102  is coupled to the system bus  104 . The system bus  104  is coupled to both the system memory  106  and the second bus controller  108 . The second bus controller  108  is coupled to the cache  110 . The cache  110  is coupled to the processor  112 . 
   The first bus controller  102  is configured via a connection  114  to receive a request to transfer data from the first bus controller  102  to the system memory  106  via connections  116  and  118 . The first bus controller  102  first sends the request to the system bus  104  via the connection  116 . The second bus controller  108  snoops the request via a connection  120 . The second bus controller  108  then sends a snoop request to the cache  110  via a connection  122 . Preferably, the cache  110  includes a cache controller (not shown) to handle this snoop request. The cache controller then determines whether the cache  110  has a valid entry for this snoop request. If there is no valid entry for this snoop request, then the snoop request is denied. Therefore, the data is transferred on the system bus  104  via a connection  124  and is eventually stored in the system memory  106 . 
   If there is a valid entry for this snoop request, then the second bus controller  108  catches the data from the system bus  104  when the data is being transferred on the system bus via the connection  124 . The second bus controller  108  then sends the data to the cache  110  for update. In this case, the data is not stored in the system memory. Preferably, the cache  110  comprises locked cache lines for valid entries, such as valid entries  126  and  128 . 
   Now referring to  FIG. 2 , a block diagram illustrates a computer system  200  having two processors directly accessing a cache for data. The computer system  200  includes all the components of the computer system  100  of  FIG. 1  and further includes first and second processors  202  and  204 , a local memory  206 , and a direct memory access controller (DMAC)  208 . The first processor  202  is coupled to the cache  110 . The connection between the cache  110 , the first and second bus controllers  102  and  108 , the system bus  104 , and the system memory  106  remain the same as in  FIG. 1 . So are the connections  114 ,  116 ,  118 ,  120 , and  122 . 
   The second processor  204  is coupled to both the local memory  206  and the DMAC  208 . The DMAC  208  is also coupled to the first bus controller  102 . 
   The second processor  204  sets up a DMA transfer whereby data is transferred from the local memory  206  to the system memory  106  via a connection  210 . Subsequently, the DMAC  208  sends the first bus controller  102  a request for transferring the data from the local memory  206  to the system memory  106 . This is done via the connection  114 . The first bus controller  102  then sends the request to the system bus  104  via the connection  116 . The second bus controller  108  snoops the request via the connection  120 . The second bus controller  108  then sends a snoop request to the cache  110  via the connection  122 . Preferably, the cache  110  includes a cache controller (not shown) to handle this snoop request. The cache controller then determines whether the cache  110  has a valid entry for this snoop request. If there is no valid entry for this snoop request, then the snoop request is denied. Therefore, the data is transferred on the system bus  104  via the connection  124  and is eventually stored in the system memory  106 . 
   If there is a valid entry for this snoop request, then the data is read out from the local memory  206 . The second bus controller  108  catches the data from the system bus  104  when the data is being transferred on the system bus via the connection  124 . The second bus controller  108  then sends the data to the cache  110  for update. In this case, the data is not stored in the system memory. 
   The computer system  200  may be generalized to a computer system having a plurality of processors. In that case, an additional cache (not shown) and an additional bus controller (not shown) may be coupled between each additional processor (not shown) and the system bus  104  in a manner similar to the connection between the processor  202  and the system bus  104 . 
   In  FIG. 3 , a flow diagram  300  is shown to illustrate the operation of the computer system  100  of  FIG. 1 . In step  302 , the first bus controller  102  first sends a data transfer request to the system bus  104  for transferring data to the system memory  106 . In step  304 , the second bus controller  108  snoops the data transfer request. In step  306 , the second bus controller  108  sends a snoop request to the cache  110 . In step  308 , the data is transferred on the system bus  104 . Preferably, the cache  110  includes a cache controller (not shown) to handle this snoop request. In step  310 , the cache controller determines whether the snoop request is valid. For example, the cache  110  may be searched to find a valid entry for this snoop request. If there is no valid entry for this snoop request, then the snoop request is denied. Therefore, the data is eventually stored in the system memory  106  in step  314 . 
   If there is a valid entry for this snoop request, then the second bus controller  108  catches the data from the system bus  104  and sends the data to the cache  110  for update in step  312 . In this case, the data is not stored in the system memory. 
   In  FIG. 4 , a flow diagram  400  is shown to illustrate the operation of the computer system  200  of  FIG. 2 . In step  402 , the second processor  204  sets up a DMA transfer for transmitting data from the local memory  206  to the system memory  106 . In step  404 , the DMAC  208  sends the first bus controller  102  a data transfer request for transferring the data from the local memory  206  to the system memory  106 . Steps  302  through  314  are virtually identical as illustrated above in reference to  FIG. 3 . 
   It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. This description is intended for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.