Abstract:
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 14/302,160 filed on Jun. 11, 2014, and issued as U.S. Pat. No. ______ on ______, which is a continuation of U.S. patent application Ser. No. 14/066,340, filed on Oct. 29, 2013, and issued as U.S. Pat. No. 8,759,980, which is a divisional of U.S. patent application Ser. No. 12/724,491 filed on Mar. 16, 2010, and issued as U.S. Pat. No. 8,569,891 on Oct. 29, 2013. These applications and patent are incorporated herein by reference, in their entirety, and for any purpose. 
     
    
     BACKGROUND 
       [0002]    This relates generally to semiconductor memories, such as non-volatile memories or volatile memories. Particularly, it relates to forming array contacts in memories. 
         [0003]    Semiconductor memories may be volatile or non-volatile memories. Examples of volatile memories include dynamic random access memories (DRAMs) and static random access memories (SRAMs). Examples of non-volatile memories include Flash memories and resistive random access memories (ReRAM), such as phase change memories, to mention a few examples. 
         [0004]    Typically, semiconductor memories include an array made up of parallel conductive rows and parallel conductive columns perpendicular to the rows. Selectable memory cells are formed at the intersections of those rows and columns. 
         [0005]    Array contacts electrically connect elements in the array to metallization lines overlying the array. The array contacts then are conductive vias. With increasingly smaller memory cell sizes, array contacts need to effectively scale correspondingly. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is an enlarged, top plan view of one embodiment of the present invention at an early stage of manufacture; 
           [0007]      FIG. 2  is a reduced cross-sectional view taken generally along the line  2   2  in  FIG. 1 ; 
           [0008]      FIG. 3  is a cross sectional view corresponding to  FIG. 2  at a subsequent stage in accordance with one embodiment; 
           [0009]      FIG. 4  is a top plan view at a subsequent stage in accordance with the embodiment of  FIGS. 1-3 ; 
           [0010]      FIG. 5  is an enlarged, cross-sectional view taken generally along the line  5 - 5  in  FIG. 4 ; 
           [0011]      FIG. 6  is an enlarged, cross-sectional view of an alternate embodiment at a stage subsequent to the stage shown in  FIG. 3  in accordance with one embodiment; 
           [0012]      FIG. 7  is an enlarged, cross-sectional view at a subsequent stage to that shown in  FIG. 6  in accordance with one embodiment; 
           [0013]      FIG. 8  is an enlarged top plan view of still another embodiment; 
           [0014]      FIG. 9  is an enlarged top plan view at a subsequent stage; and 
           [0015]      FIG. 10  is an enlarged top plan view at a subsequent stage. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    In accordance with some embodiments, array contacts can be formed without some of the limitations typically imposed by conventional lithographic techniques. For example, conventional array contacts for high density arrays may be made using a dipole illumination mode for lithographic contact hole definition. One problem with this technique is that the illumination mode results in an elliptical shape for the contact where the X/Y ratio is reduced with reducing critical pitch. Overly elliptical contacts can sometimes result in integration issues in terms of contact to gate distance. 
         [0017]    In accordance with some embodiments of the present invention, at least two perpendicular masks and definition stages are used to define the array contacts instead of using the single mask, dipole illumination mode technique. This may result, in some embodiments, in reducing the integration issues that sometimes arise from an overly elliptical contact shape. 
         [0018]    Referring to  FIG. 1 , a memory array  10  may include a plurality of parallel, spaced conductive lines  16 , extending generally perpendicularly to parallel, spaced active areas  12 , situated below the lines  16 . The active areas are the regions where the memory cells are formed. The regions surrounding the lines  16  may be filled with a dielectric  14 , such as pre-metal deposition (PMD) oxide, over an etch stop layer (not shown) such as borderless nitride for example. However, other dielectrics may be used as well. The conductive lines  16  may, for example, be control gates, in a Flash memory embodiment. However, the present invention is applicable to any semiconductor memory technology, including volatile and non-volatile memories. 
         [0019]    A plurality of spaced parallel masks  18  may be aligned over the conductive lines  16 , each mask  18  having dimensions slightly larger than the conductive lines  16 . Thus, the masks  18  may extend in the same direction as the conductive lines  16  and generally perpendicularly to the active areas  12  in one embodiment. The masks  18  may be patterned photoresist for example. 
         [0020]    Referring to  FIG. 2 , the conductive lines  16  extend perpendicularly across the active areas  12 . Other elements are not shown for simplicity. In this case  1  spaced, parallel tapered trenches  20  are formed between adjacent conductive lines  16 . The trenches  20  extend in the same lengthwise direction and have the same pitch as the conductive lines  16  in this embodiment. The trenches  20  may be formed using the masks  18 , shown in  FIG. 1  with dry etching for example. The mask  18  widths may be altered by the etching process. The etching may stop on an etch stop layer (not shown) at the bottom of the dielectric  14 . In some embodiments, the etching is highly selective of the etch stop. 
         [0021]    After etching, the masks  18  may be removed. In some embodiments, the trenches  20  may taper inwardly from top to bottom as a result of the selected etching techniques. However, in other embodiments, vertical wall trenches may be formed. 
         [0022]    Referring to  FIG. 3 , at this second masking stage, the trenches  20  may be filled with trench filler  24  and planarized to the height of the dielectric  14 . Examples of trench filler materials include nitrides, such as SiON, polysilicon, etc. Parallel spaced masks  22 , formed of any suitable material, including photoresist, may extend generally perpendicularly to the lengths of the filled trenches  24 . The masks  22  may cover the region between the active areas  12 , shown in  FIG. 1 . The width of the masks  22  determines the desired spacing between resulting, later formed array contacts, as well as the thicknesses of those array contacts. A dry etching process used with masks  22  may be very selective to the selected trench filler  24 , in some embodiments. 
         [0023]    Moving to  FIG. 4 , the filled trenches  24  extend generally parallel to the conductive lines  16  and may be situated between adjacent conductive lines. In the direction perpendicular to the trenches  24 , the active areas  12  extend parallel to one another. An array contact  26  may be formed in the active areas at the intersection between a trench filler  24  and an active area  12 . Other array contact pitches may so be used. 
         [0024]    Thus, as shown in  FIG. 5   1  the array contacts  26  are formed at the locations never covered by the masks  18  or  22  (which have been removed at this point). The masks  18  and  22  are arranged perpendicularly to one another. An etchant may be used with the mask  22 , which etchant is highly selective of the pre-metal deposition oxide  14 . As a result, only the trench filler  24  is removed. The masks  22  may then remove as well. 
         [0025]    The resulting etched holes in the trench filler  24  may then filled by standard barrier layers and metal, such as tungsten. Then, a standard chemical mechanical planarization process may be utilized to form the array contacts  26 , shown in  FIG. 5 . The array contacts  26  may be columnar with a square or rectangular cross-section. The array contacts may taper toward the semiconductor substrate. Thus, the contacts  26  may be high aspect ratio or elongate, truncated pyramids. In some cases, the resulting array contacts  26  are more circular or elliptical because the corners tend to etch away. 
         [0026]    Referring to  FIG. 6   1  in accordance with a dual damascene embodiment, in the same region used to form the array contacts  26 , the fill trenches  24  are partially etched out, as indicated at  28 . A dual damascene structure can be formed in the same vertical space that was used to form the array contacts  26  in  FIG. 5  in some embodiments. This may be important, in some embodiments, because the amount of vertical space may be limited. However, in some embodiments, the etch out step may not be used. The etch out step entirely removes the upper portion of the trench filler  24 , extending into the page in  FIG. 6 , and leaving a vertically shortened trench filler. A suitable wet etchant that selectively etches the trench filler  24  may be used in some embodiments. 
         [0027]    Then, as shown  FIG. 7 , the remaining trench filler  24  may be removed at the intersections of masks as described previously, resulting in the array contacts  32 . Where the upper layer of the trench filler  24  was removed, spaced parallel metal lines  30  may extend transversely to the conductive lines  16  and have array contacts  32  extend downwardly from the metal lines  30  between adjacent conductive lines  16 . These metal lines may, for example, be used as row or bit lines. The metal lines  30  may be formed of the same or different materials. 
         [0028]    Of course, the same process may be done in the reverse order wherein the structure is first masked off perpendicularly to the direction of the conductive lines  16  by forming masks  40  overlying the regions between adjacent active areas  12 , as shown in  FIG. 8 . Dry etching may be used to form trenches  42  in the dielectric  14  between masks  40 . 
         [0029]    The intervening trenches  42  may be trench filled, for example, by a suitable material  44 , as shown in  FIG. 9 . Then the trench fill material  44  may be etched back to the height desired. 
         [0030]    Thereafter the array contacts  46  may be formed by etching out the filler material using masks  48  shown in  FIG. 10 . The contacts  46  are found at the intersections of two masks, as shown in  FIG. 10 , by metal filling, followed by chemical mechanical planarization. 
         [0031]    References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. 
         [0032]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.