Abstract:
An integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency. A current mirror circuit generates a primary current and a mirrored current. Under the control of a clock signal, a switched capacitor circuit uses the mirrored current to constantly accumulate charges on primary capacitor while also alternately sharing such charges with and then discharging one of two additional capacitors. The magnitude of the current drawn by the switched capacitor circuit is a factor of the junction area of a diode and absolute temperature. To maintain equality of the primary and mirrored currents, a node voltage within the current mirror circuit is monitored by a bias circuit which provides a bias signal for controlling the current mirror circuit. An additional current replication stage is driven by the current mirror circuit to provide an additional mirrored current which is proportional to a product of absolute temperature and the frequency of the clock signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to bias circuits for switched capacitor circuits, and in particular, to bias circuits for switched capacitor circuits which compensate for process tolerances, temperature and clock frequency. 
     2. Description of the Related Art 
     In circuit applications involving switched capacitor circuits, the amplifiers are typically required to drive only capacitive loads which do not require much, if any, DC current. Accordingly, such amplifiers can be designed without a low impedance output stage, such as an emitter follower or source follower circuit. As a result of this design simplification, such amplifiers used in switched capacitor circuits typically have a high output impedance and are often referred to as “operational transconductance amplifiers” to differentiate them from operational amplifiers having low output impedance. Applications in which high output impedances are acceptable allow single-stage operational transconductance amplifiers to be used. Such amplifiers are typically folded-cascode or telescopic (i.e., unfolded cascode) designs. 
     Referring to FIG. 1, such an amplifier will typically have a single dominant pole, thereby making the unity gain bandwidth proportional to the ratio of the transconductance g m  of the input stage and the load capacitance C LOAD . Accordingly, as represented in the graph of FIG. 1, this relationship between unity gain bandwidth frequency f unity , transconductance g m  and load capacitance C LOAD  can be expressed by Equation (1) below.                f   unity     ∝       g   m       C   LOAD               (   1   )                                
     If the input differential pair of transistors (metal oxide semiconductor field effect transistors, or MOSFETs) of the operational transconductance amplifier are biased in the subthreshold region, then the input stage transconductance g m  is inversely proportional to the product of Boltzmann&#39;s constant k and absolute temperature T divided by charge q. Accordingly, it follows that the input stage transconductance g m , using equations 2, 3 and 4 below, can be found using the drain current I D , majority carrier mobility μ, gate oxide capacitance per unit area C ox , channel width W and length L, gate-to-source voltage V GS , threshold voltage V T0 , source voltage V S  and number n of output devices.                  If                   I   D              β   ·       (     kT   q     )     2                     where                 β       =     μ                   C   ox                     W   L               (   2   )                 Then                   I   D       =         β        (     kT   q     )       2               (       (       V   GS     -     V   T0     -     nV   s       )       nkT   q       )                 (   3   )                 g   m     =         ∂     I   D         ∂     V   GS         =         I   D       nkT   q                       (   subthreshold   )                 (   4   )                                
     Equations (1) and (4) can be combined to express the unity gain bandwidth frequency f unity  according to Equation (5).                f   unity     ∝       I   D         nkT   q     ·     C   LOAD                 (   5   )                                
     As seen in Equation (5), if the drain current I D  can be made proportional to the product of absolute temperature T and load capacitance C LOAD , the unity gain frequency f unity  will be constant for all process and temperature variations. Ideally, the unity gain frequency f unity  of the operational transconductance amplifier should track the frequency of the clock signal (with clock signal period T clock ) for the switched capacitor filter. Accordingly, relations for the unity gain frequency f unity  and drain current I D  can be expressed according to Equations (6) and (7) below.                assuming                   f   unity       ∝     1     T   clock               (   6   )                 then                   I   D       ∝         nkT   q     ·     C   LOAD         T   clock               (   7   )                                
     As should be recognized, the quotient of load capacitance C LOAD  and clock signal T clock  in Equation (7) is the approximate expression for a switched capacitor resistor equivalent. 
     Referring to FIG. 2, many conventional designs generate a PTAT (proportional to absolute temperature) bias current by developing a “difference voltage” across a resistor, where such “difference voltage” is the difference between the forward biased junction voltages of the diodes D 21 , D 22 . When the bias current lout generated by this circuit is substituted into Equation (4), the relationship for the subthreshold MOSFET transconductance g m  can be expressed according to Equation (8) below.                g   m     =         I   D       nkT   q       =         ln                   (   A   )         n   ·   R                       (   subthreshold   )                 (   8   )                                
     According to Equation (8), if the resistor R has no temperature dependance, the transconductance g m  will be constant. Based upon this, it can then be shown that the unity gain frequency f unity  of the operational transconductance amplifier can be expressed according to Equation (9).                f   unity     ∝       ln                   (   A   )         n   ·     R        (     1   +   aT   +     bT   2       )       ·     C   LOAD                 (   9   )                                
     According to Equation (9), the unity gain frequency f unity  and the settling of the operational transconductance amplifier is a function of the absolute tolerances of the resistor R (typically within a range of ±20%) and the load capacitance C LOAD  (typically within a range of ±10%). Assuming a linear resistor temperature coefficient equal to +700 ppm/° C. and a temperature range of −40° C. to +85° C., the overall tolerance of the unity gain frequency will be within a range of ±40%. This implies that in order to guarantee that the operational transconductance amplifiers (which are biased by the circuit of FIG. 2) will meet minimum settling time requirements, the bias current must be 40% larger than what would otherwise be considered optimum. 
     Referring to FIG. 3, another conventional design provides a compensated reference current Iref which is a function of a reference voltage Vref, a capacitance C and clock signal period Td. (This circuit is described in more detail in E. A. Vittoz, “The Design of High-Performance Analog Circuits on Digital CMOS Chips,” IEEE Journal of Solid-State Circuits, Vol. SC-20, no. 3, June 1985, pp. 657-65.) This circuit forms a servo loop in which, during one clock phase Td, capacitor C is charged to the reference voltage Vref and transistor M 1  drains charge from capacitor Cs which is equal to the product of the reference current Iref and the clock period Td. 
     During the next clock phase, capacitors C and Cs are shorted together and also connected to the inverting input of the operational amplifier. If the charge drained from capacitor Cs by transistor M 1  was more than that which is now available via charge sharing from capacitor C (i.e., the product of the reference voltage Vref and capacitance C), then the inverting input of the operational amplifier will be pulled to a lower potential which, in turn, will cause the gate terminal of transistor M 4  to be pulled to a higher potential, thereby reducing the magnitude of the reference current Iref (due to the current mirror action of transistors M 3  and M 5 ). 
     This circuit has a number of disadvantages. This circuit requires a separate voltage reference circuit, the accuracy of the charge transfer (and power supply rejection) from capacitor C to capacitor Cs is sensitive to switch charge injection, and the value of the reference current is sensitive to the clock period Td. Additionally, this circuit is sensitive to parasitic capacitances on the top plates of capacitors C and Cs. Stray capacitances on these nodes will become discharged when the voltage changes during different clock cycles. 
     Referring to FIG. 4, another conventional design operates in an “open loop” manner and does not use any feedback. (This design is discussed in more detail in Olesin et al., U.S. Pat. No. 4,374,357, the disclosure of which is incorporated herein by reference.) In this design, capacitors C 22  and C 40  are alternately charged and discharged by transistors M 18 , M 20 , M 36  and M 38  during successive states of the clock signal. An average current equal to the product of the capacitance of capacitor C 22  (or capacitor C 40  since they are equal), the reference voltage Vref and two times the frequency of the clock signal (=C 22 *Vref*2*f clock ) flows through the diode-connected MOSFET M 50 . The gate terminal of transistor M 50  is a low impedance node which is bypassed by filter capacitor C 52  and is used to bias transistor M 54 . 
     This circuit also has a number of disadvantages, including poor accuracy and poor power supply rejection. There are inherent errors caused by the drain voltage of transistor M 50  not matching the drain voltage of transistor M 54 , as well as mismatched drain voltages for transistors M 56  and M 60 , transistors M 62  and M 64 , and transistors M 28  and M 30 . Additionally, this circuit provides little high frequency ripple filtering due to the lack of high impedance nodes. All filter capacitors are connected directly across diode-connected transistors (e.g., transistors M 50  and M 56 ). Accordingly, the reference current generated by this circuit will have ripple at twice the frequency of the clock signal. 
     SUMMARY OF THE INVENTION 
     A switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, capacitance and clock frequency in accordance with the present invention uses a double-sampled switched capacitor “resistor” and an integration capacitor within a PTAT (proportional to absolute temperature) loop to generate bias currents which are proportional to capacitance, clock frequency and absolute temperature. Such currents are optimal for biasing operational amplifiers in switched capacitor filters where settling is dominated by the closed loop bandwidth rather than slewing. Such a circuit compensates for variation in the load capacitance and temperature to minimize power dissipation. 
     In accordance with one embodiment of the present invention, an integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency includes a current mirror circuit, a bias circuit and a switched capacitor circuit. The current mirror circuit is configured to receive a bias voltage and in accordance therewith provide a primary current, first and second mirrored currents and a node voltage, with the node voltage being responsive to the first mirrored current. The bias circuit, coupled to the current mirror circuit, is configured to receive the node voltage and in accordance therewith provide the bias voltage. The switched capacitor circuit, coupled to the current mirror circuit, includes a capacitance and is configured to receive first and second clock signals which are equal in frequency and mutually inverse in phase and in accordance therewith receive and conduct the first mirrored current in proportion to an absolute temperature of the switched capacitor circuit, the capacitance and the clock signal frequency. The second mirrored current is proportional to a product of the absolute temperature, the capacitance and the clock signal frequency. 
     In accordance with another embodiment of the present invention, a method of generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency includes the steps of: 
     receiving a bias voltage and in accordance therewith generating a primary current, first and second mirrored currents and a node voltage, wherein the node voltage is responsive to the first mirrored current; 
     receiving the node voltage and in accordance therewith generating the bias voltage; and 
     receiving, with a capacitive circuit having a capacitance, first and second clock signals which are equal in frequency and mutually inverse in phase and in accordance therewith receiving and conducting the first mirrored current in proportion to an absolute temperature, the capacitance and the clock signal frequency; 
     wherein the second mirrored current is proportional to a product of the absolute temperature, the capacitance and the clock signal frequency. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram and corresponding frequency response graph for the open loop frequency response of a typical operational transconductance amplifier. 
     FIG. 2 is a schematic diagram of a conventional PTAT current generator. 
     FIG. 3 is a schematic diagram of a conventional voltage-to-current conversion circuit. 
     FIG. 4 is a schematic diagram of a conventional switched capacitor reference current source. 
     FIG. 5 is a schematic diagram of a switched capacitor bias circuit in accordance with one embodiment of the present invention. 
     FIG. 6 is a timing diagram with waveforms for selected signals in the circuit of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 5, a switched capacitor bias circuit (preferably in integrated circuit form) for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency in accordance with one embodiment of the present invention uses a double-sampled switched capacitor “resistor” Cs and an integration capacitor CI inside a PTAT loop to generate an output bias current Ibias which is proportional to the clock frequency and absolute temperature, as well as its load capacitance. Transistors M 1 , M 2 , M 4  and M 5  form part of a current mirror circuit which is biased by a bias circuit formed in part by transistors M 3  and M 6 . Capacitors CI and Cs and transistors Msa, Msb, Msc and Msd form a switched capacitor circuit which uses a mirrored current I 1  from the current mirror circuit to accumulate and discharge charges across the capacitors CI, Cs (as discussed in more detail below). Diode D 2  has a junction area of A and can be implemented as a parasitic substrate PNP transistor. Diodes D 1  and D 3  have normalized junction areas of unity. 
     An additional current mirror branch circuit is formed in part by transistors M 7  and M 8  to produce the output bias current I bias  which is a replicated, i.e., mirrored, version of the primary current mirror current I 2 . The master clock signal CLOCK is inverted by an invertor circuit to produce corresponding inverse clock signals CLOCK, {overscore (CLOCK)} for driving the switching transistors Msa, Msb, Msc, Msd within the switched capacitor circuit. 
     The PTAT loop servos in such a manner as to maintain the voltage VI across the integrating capacitor CI at a value which is equal to an average of the natural logarithm of the area A of diode D 2  times Boltzmann&#39;s constant K times absolute temperature T divided by charge q (=In(A)*KT/q). If the voltage VI across the integration capacitor CI becomes less than this average, this means that diode D 2  is conducting more current than D 1 . Under these conditions, current I 1  through transistor M 1  is greater than the primary current mirror current I 2 . Due to the current mirror action of transistors M 4  and M 5 , the drain current of M 4  is equal to the primary mirror current I 2 . However, since the drain current of transistor M 1  is greater than the primary mirror current I 2 , i.e., drawing more current from the node connecting the gate terminal of transistor M 6  and compensation capacitor Cc, the voltage at node A decreases. In turn, this causes the drain current of transistor M 6  to increase, thereby causing the voltage at node C to increase. Further in turn, this pulls up the voltage potential at the gate terminal of transistor M 1 , thereby increasing the voltage potential at node B. Still further in turn, this causes the average of the voltage VI across the integration capacitor CI to increase. Hence, this feedback action drives the loop to correct and maintain the average value of the voltage VI across the integration capacitor CI. 
     In summary then, the average value of the voltage VI across the integration capacitor CI is a function of the area A of diode D 2 . Since diode D 2  has a larger junction area than diode D 1 , the current density in diode D 2  is less than the current density in diode D 1  and, therefore, the forward-bias voltage drop VD 2  across diode D 2  is less than the forward-bias voltage drop VD 1  across diode D 1 . Hence, since the voltages at the source terminals of transistors M 1  and M 2  are equal, this voltage difference VD 2 −VD 1  appears in the form of the voltage VI across the integration capacitor CI. 
     Referring to FIG. 6, the operation of this circuit can perhaps be better understood by considering the details of the voltage within the switched capacitor loop. During both phases CLOCK, {overscore (CLOCK)} of the clock signal, the drain current I 1  of transistor M 1  will charge a total capacitance of CI+Cs, thereby creating a ramp-shaped voltage waveform. For a 50% duty cycle clock signal the ramp will move linearly from a minimum voltage Vmin to a maximum voltage Vmax. Each time a sampling capacitor CS with zero initial voltage (due to the discharging action of transistors Msa and Msd) is switched across the integration capacitor CI, charge sharing occurs. This charge sharing action establishes the ratio of the minimum voltage Vmin (i.e, the initial ramp voltage) to the maximum voltage Vmax (i.e., the final ramp voltage) as the ratio of CI/(Cs+CI). Because the ramp is linear, the average voltage is equal to ln(A)KT/q, i.e., the arithmetic mean of the maximum Vmax and minimum Vmin voltages. This can be expressed according to Equation (10) below.                V   avg     =         ln        (   A   )       ·     KT   q       =     0.5   ·     V   max     ·     (     1   +     CI     CI   +   Cs         )                 (   10   )                                
     Rearranging and solving for the maximum voltage Vmax produces Equation (11).                V   max     =     2   ·     ln        (   A   )       ·     KT   q     ·     (       CI   +   Cs         2   ·   CI     +   Cs       )               (   11   )                                
     The minimum voltage Vmin can then be found using Equations (12) and (13).                V   min     =       V   max     ·     (     CI     CI   +   Cs       )               (   12   )                 V   min     =     2   ·     ln        (   A   )       ·     KT   q     ·     (     CI       2   ·   CI     +   Cs       )               (   13   )                                
     The amplitude of the voltage ramp is the difference between the maximum Vmax and Vmin voltages, as expressed in Equation (14).                  V   max     -     V   min       =     2   ·     ln        (   A   )       ·     KT   q     ·     (     CI       2   ·   CI     +   Cs       )               (   14   )                                
     To solve for the drain current I 1  of transistor M 1 , it is noted that the load capacitance during charging is the sum of the sampling capacitance Cs and integration capacitance CI. During steady state operation, the primary current I 2  and mirrored currents I 1 , Ibias are equal. Therefore, the output bias current Ibias can be computed in accordance with Equation (15).              Ibias   =         (     Cs   +   CI     )     ·          v          T         =       4   ·     (     Cs   +   CI     )     ·     ln        (   A   )       ·     KT   q     ·     (     Cs       2   ·   CI     +   Cs       )         T   clock                 (   15   )                                
     Accordingly, by substituting Equation (15) into Equation (5) the relationship for the unity gain frequency f unity  can be expressed according to Equation (16).                f   unity     ∝       4   ·     (     Cs   +   CI     )     ·     ln        (   A   )       ·     (     Cs       2   ·   CI     +   Cs       )         n   ·     C   LOAD     ·     T   clock                 (   16   )                                
     Under normal circumstances, the sampling capacitance Cs, integration capacitance CI and load capacitance C LOAD  (not shown) will track each other due to the fact that the corresponding capacitors are fabricated from the same material. Accordingly, it can be seen in Equation (16) that the unity gain frequency f unity  will be inversely proportional to the clock period, or alternatively, proportional to the clock frequency. 
     The circuit of FIG. 5 provides a high degree of power supply rejection since the drain and source voltages of all “matched” device pairs are designed to be matched within tens of millivolts. For example, transistor pair M 1 /M 2  and pair M 4 /M 5  have well matched operating points. 
     Further, charge injection is inherently cancelled by the double sampling design. For example, when switching transistor Msb turns off, thereby dumping its channel charge, transistor Msa turns on, thereby collecting the channel charge. Similar charge injection cancellation occurs on the opposite clock phase with transistors Msc and Msd. 
     Further still, node A is a high impedance node at which compensation provides a low frequency dominant pole that filters out ripple. The compensation capacitor Cc provides the low frequency filter pole at the frequency of 1/(Rds*Cc). Additional filtering and power supply rejection is established based upon the RC time constant of the filter capacitor Cfilter and the drain-to-source resistance of transistor M 7  which is biased in triode mode (resistive) with a bias voltage V 1 . 
     The foregoing equations assume that the operational transconductance amplifiers are biased in subthreshold mode. If, however, the input MOSFETs are biased in strong inversion modes, other equations will apply. For example, for biasing in saturation mode, Equation (17) below will apply.                g   m     =         ∂     I   D         ∂     V   GS         =           2                 μ                   CoxWI   D       L                       (   saturation   )                 (   17   )                                
     Substituting for the drain current I D  in Equation (15) into Equation (17), we obtain Equation (18).                g                 m     =         2                 μ                   CoxW        (     4   ·     (     Cs   +   CI     )     ·   Cs   ·     ln        (   A   )       ·   KT     )           L   ·   q   ·     (       2   ·   CI     +   Cs     )     ·     T   clock                   (   18   )                                
     The carrier mobility μ has a temperature dependence of T −{fraction (3/2)} . When this is combined with the linear temperature dependence of the PTAT current, the overall temperature variance of the transconductance g m  will be T −¼ . For a temperature range of −40 to +100° C., the overall spread of transconductance g m  variations due to temperature will be within a range of ±5.7%. 
     The unity gain frequency f unity  is proportional to the quotient of the transconductance g m  and load capacitance C LOAD  (=g m /C LOAD ). Substituting this expression into Equation (18) demonstrates that the sensitivity of the unity gain bandwidth f unity  to capacitor variations is −½. In other words, for every 10% increase in capacitance value, the unity gain frequency will decrease by approximately 5%. Additionally, there will be a dependence upon the effective channel length L of the transistors. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.