Abstract:
An integrated transformation apparatus is provided. The apparatus includes a first multiplexer, a second multiplexer, and a transformation unit. The first multiplexer retrieves point data from columns or rows of a multi-dimensional matrix and input data. The second multiplexer retrieves transformation coefficients corresponding to the point data. The transformation unit transforms data blocks of the multi-dimensional matrix to a plurality of sub data blocks according to the input data, the point data, and the transformation coefficients.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to an integrated conversion method and apparatus, and more particularly to a data conversion method for video or audio data, converting different data block sizes for video or audio data using the same designed hardware architecture. 
         [0003]    2. Description of the Related Art 
         [0004]    With respect to dynamic data compression, a memory can be divided to multiple 16×16 blocks, referred to as macroblocks. Each macroblock can be divided into 4 blocks, each serving as a basic unit for compression 
         [0005]    Implementation of one-dimensional or multi-dimensional conversion of data blocks requires different hardware architecture designs. With respect to 8×4 and 8×8-block conversion, for example, 8×1-block one-dimensional inverse conversion and 4×1-block one-dimensional inverse conversion are implemented using different hardware architecture designs. Different hardware architecture designs convert different block sizes, for example, common operations units. Further, conversion is achieved with only one block size in a period while other block size conversion operations are idle, thus, hardware design resources are wasted. 
         [0006]    Thus, the invention provides an integrated conversion method and apparatus, integrating common operation units to achieve conversions with different block sizes using the same hardware architecture. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    Integrated conversion methods are provided. An exemplary embodiment of an integrated conversion method comprises the following. Row or column point data of a multi-dimensional matrix is obtained. Input data and conversion coefficients corresponding on the point data are obtained. Data blocks of the multi-dimensional matrix are converted to a plurality of sub data blocks according on the input data, and conversion coefficients, and the point data and a conversion operation is performed. 
         [0008]    The input data is obtained using a multiplexer and transmitted to a conversion unit. Column conversion with M-point or N-point is implemented on the input data using the conversion unit. The column conversion data is temporarily stored in an output buffer. The row conversion data is accessed from the output buffer and row conversion with M-point or N-point is implemented on the row conversion data using the conversion unit. The row conversion data is stored in the output buffer for data output. 
         [0009]    Integrated conversion apparatus are provided. An exemplary embodiment of an integrated conversion apparatus comprises a first multiplexer, a second multiplexer, and a conversion unit. The first multiplexer obtains row or column point data of a multi-dimensional matrix and input data. The second multiplexer obtains conversion coefficients corresponding on the point data. The conversion unit converts data blocks of the multi-dimensional matrix to a plurality of sub data blocks according on the input data, and conversion coefficients, and the point data and performs a conversion operation. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a schematic view of an embodiment of an integrated conversion apparatus; 
           [0013]      FIG. 2  is a flowchart of an embodiment of an integrated conversion method; and 
           [0014]      FIGS. 3A and 3B  show a detailed flowchart of an integrated conversion method shown in  FIG. 2 ; 
           [0015]      FIG. 4  is a schematic view of common items generated from multiplication of a 4-point conversion coefficient matrix by input data; 
           [0016]      FIG. 5  is a schematic view of a parallel architecture of 4-point one-dimensional conversion shown in  FIG. 4 ; 
           [0017]      FIG. 6  is a schematic view of a structure of D0·X n ; 
           [0018]      FIG. 7  is a schematic view of a structure of D 1 ·X 1  and D 2 ·X 3 ; 
           [0019]      FIG. 8  is a schematic view of common items generated from multiplication of a 8-point conversion coefficient matrix by input data; 
           [0020]      FIG. 9  is a schematic view of a parallel architecture of 8-point one-dimensional conversion shown in  FIG. 8 ; 
           [0021]      FIG. 10  is a schematic view of a structure of C0·X n ; 
           [0022]      FIG. 11  is a schematic view of a structure of C 1 ·X n ˜C4·X n ; and 
           [0023]      FIG. 12  is a schematic view of a structure of C5·X n  and C6·X n . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    Several exemplary embodiments of the invention are described with reference to  FIGS. 1 through 12 , which generally relate to data conversion. It is to be understood that the following disclosure provides various different embodiments as examples for implementing different features of the invention. Specific examples of components and arrangements are described in the following to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and/or configurations. 
         [0025]    The invention discloses an integrated conversion method and apparatus, converting different data block sizes for video or audio data using the same hardware architecture design. 
         [0026]    An embodiment of an integrated conversion method and apparatus provides one-dimensional or multi-dimensional conversion methods, comprising Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT), to convert a 1 ×a 2 × . . . ×a n  data blocks to multiple b 1 ×b 2 × . . . ×b n  data blocks, where a i  is a multiplier of bi, 1≦i≦n, and n is a dimensional value. Thus, conversion of small block sizes can be implemented using an originally designed conversion architecture based on selected paths and conversion coefficients, maximally reducing hardware cost. 
         [0027]    The apparatus further comprises an output buffer. The first multiplexer obtains and transmits the input data on the conversion unit. The conversion unit implements column conversion with M-point or N-point on the input data, temporarily stores the column conversion data in the output buffer, accesses the row conversion data from the output buffer, implements row conversion with M-point or N-point on the row conversion data, and stores the row conversion data in the output buffer for data output. 
         [0028]    Generally, two-dimensional conversion architecture can be implemented using one-dimensional architecture. 
         [0029]      FIG. 1  is a schematic view of an embodiment of an integrated conversion apparatus. Integrated conversion apparatus  100  comprises an 8-point conversion unit  110 , an 8×8-point output buffer  120 , and multiplexers  130  and  140 . 8-point conversion unit  110  further comprises 4-point conversion unit  111  and  112 . 
         [0030]    When two-dimensional conversion is implemented, 8-point conversion unit  110  implements 8-point one-dimensional column conversion to input data or 4-point conversion units  111  and  112  implements 4-point one-dimensional column conversion to the input data. The column converted data is temporarily stored in output buffer  120 . Next, 8-point conversion unit  110  or 4-point conversion unit  111  and  112  access the converted data from output buffer  120  and implement 8-point or 4-point one-dimensional row conversion. The row converted data is stored in output buffer  120  for output. Additionally, the selection of reading, writing, and conversion coefficients are implemented using multiplexers  130  and  140 . Thus, a two-dimensional conversion architecture is implemented using a one-dimensional architecture. 
         [0031]      FIG. 4  illustrates common items generated from multiplication of a 4-point conversion coefficient matrix by input data. As shown in  FIG. 4 , X 0 ˜X 3  indicate input data for one-dimensional conversion and are multiplied by the 4-point conversion coefficient matrix to generate “D 0 ·X 0 +D 0 ·X 2 =P 1 ”, “D 0 ·X 0 −D 0 ·X 2 =P 2 ”, “D 1 ·X 1 +D 2 ·X 3 =Q 1 ”, and “D 2 ·X 1 −D 1 ·X 3 =Q 2 ”. 
         [0032]      FIG. 5  illustrates a parallel architecture of 4-point one-dimensional conversion shown in  FIG. 4 . As shown in  FIG. 5 , Z 0 , Z 1 ·Z 2 , and Z 3  are calculated by “Z 0 =P 1 +Q 1 ”, “Z 1 =P 2 +Q 2 ”, “Z 2 =P 2 −Q 2 ”, and “Z 3 =P 1 −Q 1 ” and further operated with Y 0 , Y 1 , Y 2 , and Y 3 . Additionally, the result of “D 0 ·X n ”, “D 1 ·X n ”, and “D 2 ·X n ” (where 0≦n≦3) can be calculated using architectures shown in  FIGS. 6 and 7 . 
         [0033]      FIG. 8  illustrates common items generated from multiplication of an 8-point conversion coefficient matrix by input data. As shown in  FIG. 8 , X 0 ˜X 7  indicate input data for one-dimensional conversion and are multiplied by the 4-point conversion coefficient matrix, results represented as: 
         [0000]        P   1   =C   0   ·X   0   +C   0   ·X   4   Equation (1); 
         [0000]        P   2   =C   0   ·X   0   +C   0   ·X   4   Equation (2); 
         [0000]        R   1   =C   5   ·X   2   +C   6   ·X   6   Equation (3); 
         [0000]        R   2   =C   6   ·X   2   +C   5   ·X   6   Equation (4); 
         [0000]        Q   1   =C   1   ·X   1   +C   3   ·X   5   Equation (5); 
         [0000]        Q   2   =C   2   ·X   1   +C   1   ·X   5   Equation (6); 
         [0000]        Q   3   =C   3   ·X   1   +C   4   ·X   5   Equation (7); 
         [0000]        Q   4   =C   4   ·X   1   +C   2   ·X   5   Equation (8); 
         [0000]        S   1   =C   1   ·X   3   +C   2   ·X   7   Equation (9); 
         [0000]        S   2   =C   2   ·X   3   +C   4   ·X   7   Equation (10); 
         [0000]        S   3   =C   3   ·X   3   +C   1   ·X   7   Equation (11); and 
         [0000]        S   4   =C   4   X   3   +C   3   ·X   7   Equation (12). 
         [0034]    P 1 , P 2 , R 1 , R 2 , Q 1 , Q 2 , Q 3 , Q 4 , S 1 , S 2 , S 3 , and S 4  are composed of operation units comprising C 0 ·X n ˜C 6 ·X n  (where 0≦n≦7) and are represented by equations (1)˜(12). 
         [0035]      FIG. 9  illustrates a parallel architecture of 8-point one-dimensional conversion shown in  FIG. 8 . As shown in  FIG. 9 , P 1 , P 2 , R 1 , R 2 , Q 1 , Q 2 , Q 3 , Q 4 , S 1 , S 2 , S 3 , and S 4  are processed to generate U 0 ˜U 7 , and U 0 ˜U 7  are processed to generate Z 0 ˜Z 7 . The generated Z 0 ˜Z 7  are further operated with Y 0 ˜Y 7 . Additionally, the result of “C 0 ·X n ” “C 6 ·X n ” (where 0≦n≦7) can be calculated using architectures shown in  FIGS. 10-12 . 
         [0036]    Referring to  FIGS. 5 and 9 , 8-point and 4-point one-dimensional architectures comprise common operation units such that the 8-point one-dimensional architecture can be divided into two sets of 4-point one-dimensional architectures. Thus, such two conversions can be integrated to build an effective hardware platform using multiplexers, as shown in  FIG. 1 . 
         [0037]    An embodiment of an integrated conversion apparatus selects a correct data path and conversion coefficients to implement block operations for 8×8, 8×4, 4×8, and 4×4-points. 
         [0038]    With respect to an example of 8×8-point two-dimensional inverse conversion, 8-point one-dimensional column conversion for 8 times is first performed and then 8-point two-dimensional row conversion for 8 times, completing the 8×8-point two-dimensional inverse conversion. 
         [0039]    With respect to an example of 8×4-point two-dimensional inverse conversion, 8-point one-dimensional column conversion for 8 times is first performed and then two sets of 4-point two-dimensional row conversion for 8 times, completing the 8×4-point two-dimensional inverse conversion. 
         [0040]    With respect to an example of 4×8-point two-dimensional inverse conversion, two sets of 4-point one-dimensional column conversion for 8 times are first performed and then 8-point two-dimensional row conversion for 8 times, completing two sets of the 4×8-point two-dimensional inverse conversion. 
         [0041]    With respect to an example of 4×4-point two-dimensional inverse conversion, four sets of 4-point one-dimensional column conversion for 4 times are first performed and then four sets of 4-point two-dimensional row conversion for 4 times, completing two sets of the 4×4-point two-dimensional inverse conversion. Thus, the described two-dimensional inverse conversions for different block sizes (8×8, 8×4, 4×8, and 4×4-point) can be achieved using the integrated conversion apparatus. 
         [0042]      FIG. 2  is a flowchart of an embodiment of an integrated conversion method. 
         [0043]    Input data is first obtained using a multiplexer and transmitted to a conversion unit (the 8-point or 4-point conversion unit as described, for example) (step S 1101 ). Column conversion with M-point or N-point is implemented on the input data using the conversion unit (step S 102 ), where M=8 and N=4 in this embodiment, but is not intended to be limitative. The column conversion data is temporarily stored in an output buffer (step S 1103 ). Next, the conversion unit accesses the column conversion data from the output buffer and implements M-point or N-point one-dimensional row conversion on the column conversion data (step S 1104 ) and stores the row conversion data in the output buffer for data output (step S 1105 ). 
         [0044]      FIGS. 3A and 3B  show a detailed flowchart of an integrated conversion method shown in  FIG. 2 . 
         [0045]    It is determined whether M×M, M×N, N×M, or N×N-point two-dimensional conversion is performed (step S 1201 ), where M=8 and N=4 in this embodiment, but is not intended to be limitative. If the M×M-point two-dimensional conversion is performed, M-point data of each column of the input data is obtained using a first multiplexer, M-point conversion coefficients of each column is obtained using a second multiplexer (step S 1211 ), and M-point one-dimensional column conversion for M times is performed using a first conversion unit (step S 1212 ). Next, M-point data of each row of the input data is obtained using the first multiplexer and M-point conversion coefficients of each row is obtained using the second multiplexer (step S 1213 ), and M-point one-dimensional row conversion for M times is performed using the first conversion unit (step S 1214 ). 
         [0046]    If the M×N-point two-dimensional conversion is performed, M-point data of each column of the input data is obtained using the first multiplexer and M-point conversion coefficients of each column is obtained using the second multiplexer (step S 1221 ). M-point one-dimensional column conversion for M times is performed using the first conversion unit (step S 1222 ). Next, N-point data of each row of the input data is obtained using the first multiplexer and N-point conversion coefficients of each row is obtained using the second multiplexer (step S 1223 ), and two sets of N-point one-dimensional row conversion for M times are performed using a second conversion unit. 
         [0047]    If the N×M-point two-dimensional conversion is performed, N-point data of each column of the input data is obtained using the first multiplexer and N-point conversion coefficients of each column is obtained using the second multiplexer (step S 1231 ). Two sets of N-point one-dimensional column conversion for M times are performed using the second conversion unit (step S 1232 ). M-point data of each row of the input data is obtained using the first multiplexer and M-point conversion coefficients of each row is obtained using the second multiplexer (step S 1233 ), and M-point one-dimensional row conversion for M times is performed using the first conversion unit (step S 1234 ). 
         [0048]    If the N×M-point two-dimensional conversion is performed, N-point data of each column of the input data is obtained using the first multiplexer and N-point conversion coefficients of each column are obtained using the second multiplexer (step S 1241 ). Four sets of N-point one-dimensional column conversion for N times are performed using the second conversion unit (step S 1242 ). N-point data of each row of the input data is obtained using the first multiplexer and N-point conversion coefficients of each row are obtained using the second multiplexer (step S 1243 ), and four sets of N-point one-dimensional row conversion for N times are performed using the first conversion unit (step S 1244 ). 
         [0049]    It is noted that, in this embodiment, the method and apparatus processes data via a selected 8-point or 4-point conversion unit selected using a first multiplexer, selects conversion coefficients, and reads and writes conversion data stored in the output buffer using a second multiplexer, but is not further described for brevity. Additionally, matrix data is concurrently input and output to obtain 8-point or 4-point matrix data. 
         [0050]    Methods and systems of the present invention, or certain aspects or portions of embodiments thereof, may take the form of program code (i.e., instructions) embodied in media, such as floppy diskettes, CD-ROMS, hard drives, firmware, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing embodiments of the disclosure. The methods and apparatus of the present invention may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing and embodiment of the disclosure. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits. 
         [0051]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.