Abstract:
A charge pump circuit includes a first switch for connecting an input terminal to a first pumping node, a first pumping capacitor for boosting up a voltage level of the first pumping node in response to a first control signal, a second switch for connecting the first pumping node to an output terminal, a third switch for connecting the input terminal to the second pumping node, a second pumping capacitor for boosting up a voltage level of the second pumping node in response to a second control signal, and a fourth switch for connecting the second pumping node to the output terminal. The charge pump circuit decreases a loss of an output voltage and prevents malfunctions in MOS devices by preventing damages of gate oxides of the MOS devices due to excessively high voltage differences.

Description:
[0001]    The present invention claims the benefit of Korean Patent Application No. 2001-87974, filed in Korea on Dec. 29, 2001, which is hereby incorporated by reference.  
         BACKGROUND OF INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to charge pump circuits in semiconductor integrated circuits, and more specifically, to charge pump circuits with minimal output voltage losses and less stress on gate oxides of the MOS devices in the circuits.  
           [0004]    2. Discussion of the Related Art  
           [0005]    It is now usual to employ charge pump circuits in nonvolatile memories, for the purpose of preparing high voltages to conduct internal operations such as programming and erasing thereof. The charge pump circuits generate operational voltages higher than a power supply voltage provided from the external into the nonvolatile memory chips, by which the operational voltages induce charge tunneling effects through thin gate oxides in programming and erasing cell data.  
           [0006]    Since the switched capacitor type of application in analog circuits, it has been mostly used the way of charge pump that was proposed by J. Dickson in IEEE Journal of Solid-State Circuits published on June 1976 (Vol. 11, pp. 374-378), entitled “On-chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier technique.” 
           [0007]    The Dickson&#39;s architecture is a construction of diode-coupled switches and pumping capacitors responding to two-phase clock signals. But, it has been well known that pumping circuits based on the Dickson&#39;s architecture fails to provide sufficient pumping when a power supply voltage becomes low, in which their output gains for boosting voltages decrease to an unusable condition.  
           [0008]    The circuit shown in FIG. 1 is one of trials to overcome the problems of the circuits based on the Dickson&#39;s architecture, disclosed in IEEE Journal of Solid-State Circuits on April 1998 (Vol. 33, pp. 592-597) by J. T. Wu and K. L. Chang), entitled “MOS charge pumps for low-voltage operation.” 
           [0009]    Referring to FIG. 1, a first charge transfer switch T 11  is connected between an input terminal and a node Q 12 . The first charge transfer switch T 11  responds to a power supply voltage Vcc from the input terminal and a voltage at a node Q 11 . A first NMOS transistor Nil is connected between the power supply voltage Vcc and the node Q 11 , and responds to a voltage at the node Q 12 . A first PMOS transistor P 11  is connected between the node Q 11  and a node Q 14 , and responds to the voltage at the node Q 12 . The bulk terminal of the first PMOS transistor P 11  is connected to the node Q 14 . A first capacitor C 11  is connected between a clock terminal and the node Q 12 , and responds to a clock signal φ from the clock terminal to charge the node Q 12 .  
           [0010]    A second charge transfer switch T 12  is connected between the nodes Q 12  and Q 14 , and responds to the voltage at the node Q 12  and a node Q 13 . A second NMOS transistor N 12  is connected between the nodes Q 12  and Q 13 , and responds to a voltage at the node Q 14 . A second PMOS transistor P 12  is connected between the node Q 13  and a node Q 16 , and responds to the voltage at the node Q 12 . The bulk terminal of the second PMOS transistor P 12  is connected to a node Q 16 . Also, a second capacitor C 12  is connected between a clock bar terminal and the node Q 14 , and responds to a clock bar signal φB from the clock bar terminal to charge the node Q 14 .  
           [0011]    A third charge transfer switch T 13  is connected between the nodes Q 14  and Q 16 , and responds to a voltage at the node Q 14  and a node Q 15 . A third NMOS transistor N 13  is connected between the nodes Q 14  and Q 15 , and responds to a voltage at the node Q 16 . A third PMOS transistor P 13  is connected between the node Q 15  and a node Q 17 , and responds to the voltage at the node Q 16 . The bulk terminal of the third PMOS transistor P 13  is connected to a node Q 17 . Also, a third capacitor C 13  is connected to the clock terminal and the node Q 16 , and responds to the clock signal φ from the clock terminal to charge the node Q 16 .  
           [0012]    A fourth charge transfer switch T 14  is connected to the node Q 16  and an output terminal Vout, and responds to the voltages at nodes Q 16  and Q 17 . A capacitor C 14  is coupled between the node Q 17  and the clock bar terminal, and responds to a clock bar signal φB from the clock bar terminal. A capacitor C 15  is coupled between the output terminal Vout and a ground voltage terminal Vss.  
           [0013]    In the operation of the charge pump circuit shown in FIG. 1, when the clock signal φ is LOW and the clock bar signal φB is HIGH, the voltage at the node Q 12  is set to be a voltage lower than Vcc, and the voltages at the nodes Q 14  and Q 16  are set to Vcc+2ΔV (ΔV is a voltage increment). Meanwhile, the node Q 17  maintains a voltage of ΔV. Since the voltage at the node Q 12  is lower than Vcc and the voltage at the node Q 14  is Vcc+2ΔV, the PMOS transistor P 11  is turned ON and the voltage at the node Q 11  is set at Vcc+2ΔV. In the meantime, as the voltage at the node Q 12  is held to be the voltage lower than Vcc, the NMOS transistor N 11  is turned OFF. Since the voltage at the node Q 11  is Vcc+2ΔV, the charge transfer switch T 11  is turned ON. Thus, the node Q 12  maintains the voltage lower than Vcc.  
           [0014]    To the contrary, when the clock signal φ is HIGH and the clock bar signal φB is LOW, the voltages at the nodes Q 12  and Q 14  are set to Vcc+ΔV and the node Q 16  rises up to Vcc+3ΔV. While the voltage at the node Q 12  turns the NMOS transistor N 11  ON, the charge transfer switch T 11  is turned OFF because the voltage of the node Q 12  (i.e., Vcc+ΔV) is higher than Vcc. At this time, the PMOS transistor P 11  is turned OFF. In the meantime, as the voltages at the nodes Q 14  and Q 16  are held at Vcc+ΔV and Vcc+3ΔV, respectively, the PMOS transistor P 12  is turned ON to make the voltage of the node Q 13  at Vcc+3ΔV. And, the NMOS transistor N 12  is turned OFF because the voltages at the nodes, Q 12  and Q 14 , are identical each other. The voltage at the node Q 13  being Vcc+3ΔV turns the charge transfer switch T 12  ON. Thus, the node Q 14  maintains Vcc+ΔV.  
           [0015]    Therefore, the nodes, Q 12  and Q 16 , are established respectively on Vcc+ΔV and Vcc+3ΔV by means of pumping in response to the clock signal φ being HIGH, while the node Q 14  is pumped up to Vcc+2ΔV in response to the clock bar signal φB being HIGH. That is, the clock signal φ and the clock bar signal φB, alternately oscillate to maintain the output voltage at Vout at Vcc+3ΔV.  
           [0016]    As described above, in the conventional charge pump circuit, a front charge transfer switch responds to a high voltage generated from subsequent charge transfer switches. Therefore, in contrast to the circuits based on the Dickson&#39;s architecture, the less is the propagation loss for a pumping voltage, the better is the pumping efficiency of the circuit.  
           [0017]    However, the conventional charge pump circuit shown in FIG. 1 inevitably faces problems of a high voltage stress at gate oxide films of the MOS devices forming the charge transfer switches because the gate electrodes of the front charge transfer switches are driven by the high voltages generated from subsequent charge transfer switches. For instance, the charge transfer switch T 12  is turned on by the voltage of Vcc+3ΔV at the node Q 16 , and thereby transfers the voltage of Vcc+ΔV at the node Q 12  to the node Q 14 . At this time, a high voltage difference of 2ΔV is between the nodes Q 16  and Q 12  and applied to gate oxide layers of the MOS devices of the charge transfer switch T 12 . Such a high voltage stress is disadvantageous to the reliability of the MOS devices.  
           [0018]    Furthermore, as the MOS transistor acting T 14  as a transmission switch for the output terminal Vout is formed in a diode circuit, there is a voltage drop when a voltage level at the node Q 16  is transmitted to the output voltage Vout. Such a voltage drop is also disadvantageous to the reliability of the MOS devices.  
         SUMMARY OF THE INVENTION  
         [0019]    Accordingly, the present invention is directed to a charge pump circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.  
           [0020]    An object of the present invention is to provide a charge pump circuit capable of driving a higher pumping voltage without degrading the reliability of MOS devices.  
           [0021]    Another object of the present invention is to provide a charge pump circuit enhancing the efficiency of a voltage pumping operation, increasing an output voltage gain.  
           [0022]    Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0023]    To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the charge pump circuit includes a first switch for selectively connecting an input terminal to a first pumping node; a first pumping capacitor for boosting a signal at the first pumping node in response to a first clock signal; a second switch for selectively connecting the first pumping node to an output terminal; a third switch for selectively connecting the input terminal to a second pumping node; a second pumping capacitor for boosting a signal at the second pumping node in response to a second clock signal; and a fourth switch for selectively connecting the second pumping node to the output terminal.  
           [0024]    In another aspect, the charge pump circuit includes a first NMOS transistor having a drain terminal connected to an input terminal, a gate terminal connected to a first pumping node and a source terminal connected to a second pumping node; a second NMOS transistor having a drain terminal connected to the input terminal, a gate terminal connected to the second pumping node and a source terminal connected to the first pumping node; a first PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to a first pumping node and a drain terminal connected to an output terminal; a second PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to the output terminal; a third PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to the first pumping node and a drain terminal connected to a bulk terminal of the first PMOS transistor; a fourth PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to a bulk terminal of the second PMOS transistor; a first pumping capacitor for boosting a signal at the first pumping node in response to a first clock signal; and a second pumping capacitor for boosting a signal at the second pumping node in response to a second clock signal, wherein the first and second clock signals being complementary in phase each other, and wherein the second NMOS transistor, and the second and fourth PMOS transistors are driven in response to a voltage level of the first pumping node while the first NMOS transistor, and the first and third PMOS transistors are driven in response to a voltage level of the second pumping node.  
           [0025]    In yet another aspect, the charge pump circuit includes a first NMOS transistor having a drain terminal connected to an input terminal, a gate terminal connected to a first pumping node and a source terminal connected to a second pumping node; a second NMOS transistor having a drain terminal connected to the input terminal, a gate terminal connected to the second pumping node and a source terminal connected to the first pumping node; a third NMOS transistor having a drain terminal connected to a bulk terminal of the first NMOS transistor, a gate terminal connected to a first pumping node and a source terminal connected to a second pumping node; a fourth NMOS transistor having a drain terminal connected to a bulk terminal of the second NMOS transistor, a gate terminal connected to a second pumping node and a source terminal connected to a first pumping node; a first PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to a first pumping node and a drain terminal connected to an output terminal; a second PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to the output terminal; a third PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to the first pumping node and a drain terminal connected to a bulk terminal of the first PMOS transistor; a fourth PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to a bulk terminal of the second PMOS transistor; a first pumping capacitor for boosting a signal at the first pumping node in response to a first clock signal; and a second pumping capacitor for boosting a signal at the second pumping node in response to a second clock signal, wherein the first and second clock signals being complementary in phase each other, and wherein the second and fourth NMOS transistors, and the second and fourth PMOS transistors are driven in response to a voltage level of the first pumping node while the first and third NMOS transistors, and the first and third PMOS transistors are driven in response to a voltage level of the second pumping node.  
           [0026]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:  
         [0028]    [0028]FIG. 1 is a circuit diagram of a conventional charge pump;  
         [0029]    [0029]FIG. 2 is a circuit diagram of a charge pump circuit according to an embodiment of the invention;  
         [0030]    [0030]FIG. 3 is a circuit diagram of a charge pump circuit according to another embodiment of the invention;  
         [0031]    [0031]FIG. 4 is a graphic diagram comparing boost characteristics of the charge pump circuit according to the invention with the conventional features; and  
         [0032]    [0032]FIG. 5 is a graphic diagram illustrating boost characteristics in accordance with the number of pumping stages in various charge pump circuits. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0034]    [0034]FIG. 2 shows a structure of a charge pump circuit with three pumping stages (first pumping stage PS 1 , second pumping stage PS 2 , and third pumping stage PS 3 ).  
         [0035]    Referring to FIG. 2, in the first pumping stage PSI, between an input terminal supplying a power supply voltage Vcc and a node Q 22  is connected a first NMOS transistor N 21  whose gate is coupled to a node Q 21 . Between the node Q 21  and a node Q 23  is connected to a first PMOS transistor P 21  whose gate and bulk are coupled to the node Q 21  and a node Q 24  respectively. A first capacitor C 21  is coupled between a clock terminal supply a clock signal φ and the node Q 22 . Between the nodes Q 22  and Q 24  is connected a second PMOS transistor P 22  whose gate and bulk are coupled to the nodes Q 21  and Q 24  respectively.  
         [0036]    Between Vcc and the node Q 21  is connected a second NMOS transistor N 22  whose gate is coupled to the node Q 22 . Between the node Q 21  and a node Q 23  is connected a third PMOS transistor P 23  whose gate and bulk are coupled to the nodes Q 22  and Q 24  respectively. A second capacitor C 22  is a second clock terminal supplying a clock bar signal φB and the node Q 21 . Between the nodes Q 21  and Q 22  is connected a fourth PMOS transistor P 24  whose gate and bulk are coupled to the nodes Q 22  and Q 24  respectively.  
         [0037]    Further, transistors N 21  and N 22  are cross-coupled. Transistors P 21  and P 23  are cross-coupled, while P 22  and P 24  are cross-couple. The cross-coupled of the transistor pair is such that a gate of one transistor is connected to a source of the other transistor while a source of the one transistor to a gate of the other transistor. For instance, the gate terminal of the transistor N 21  is connected to the source terminal of the transistor N 22 , while the source terminal of the transistor N 21  is connected to the gate terminal of the transistor N 22 .  
         [0038]    As shown in FIG. 2, the first pumping stage is constructed of the MOS transistors N 21 , N 22 , P 21 , P 22 , P 23 , and P 24 , with cross-coupled transistor pairs of N 21  and N 22 , P 21  and P 23 , and P 22  and P 24 . The PMOS transistors, P 22  and P 24 , cut off a current flowing through the bulk terminals of the PMOS transistors P 21  and P 23  in order to prevent an abnormal conduction of them.  
         [0039]    The second and third pumping stages, PS 2  and PS 3 , are constructed in the same circuit pattern with the first pumping stage. That is, the second pumping stage PS 2  is constructed of cross-coupled pairs of N 23  and N 24 , P 25  and P 27 , and P 26  and P 28 . The third pumping stage PS 3  is constructed of cross-coupled pairs of N 25  and N 26 , P 29  and P 31 , and P 30  and P 32 .  
         [0040]    In an operation of the charge pumping circuit shown in FIG. 2, when the clock signal φ or φB goes to HIGH, an initial state is set by the voltages of Vcc at the nodes Q 21  and Q 22 . The voltages at the nodes of the second stage PS 2 , Q 25  and Q 26 , maintain at Vcc+ΔV, which is identical to the voltage at the node Q 23 . The voltages at the nodes of the third stage PS 3 , Q 29  and Q 30  maintain at Vcc+2ΔV, which is also a voltage at a node Q 27  acting as an input terminal for the third stage PS 3 .  
         [0041]    Next, in the first stage PS 1 , when the clock signal φ is HIGH while φB is a LOW, the voltage at the node Q 22  rises up to Vcc+ΔV while the voltage at the node Q 21  is held at Vcc. Since the voltage at the node Q 21  is lower than the voltage at the node Q 22 , the PMOS transistors P 21  and P 22  are turned ON and the NMOS transistor N 21  is turned OFF. Also, since the voltage at the node Q 22  is higher than Vcc, the NMOS transistor N 22  is turned ON. Also, since the voltage at the node Q 22  is higher than the voltage at the node Q 21 , the PMOS transistors P 23  and P 24  are turned OFF. Thus, the voltage at the node Q 21  maintains at Vcc, and the voltage at the node Q 22  becomes Vcc+ΔV, since the node Q 22  is connected to the node Q 23  through the PMOS transistor P 21 . At this time, the voltage at the node Q 24  becomes Vcc+ΔV, since the node Q 24  is connected to the node Q 22  through the PMOS transistor P 21 , and the voltages at the bulk of PMOS transistors P 21  and P 22  maintain at Vcc+ΔV.  
         [0042]    In the second stage PS 2 , when the clock signal φ is a HIGH while φB is a LOW, the voltages at the nodes Q 25  and Q 26  are Vcc+2ΔV and Vcc+ΔV respectively. As the voltage at the node Q 26  maintains at Vcc+ΔV, which is lower than that the voltage at the node Q 25 , the PMOS transistors P 27  and P 28  are turned ON while the NMOS transistor N 24  is turned OFF.  
         [0043]    Also, since the voltage at the node Q 25  is higher than that at the node Q 23 , the NMOS transistor N 23  is turned ON. Since the voltage at the node Q 25  is higher than that at the node Q 26 , the PMOS transistors P 25  and P 26  are turned OFF. Thus, the voltage at the node Q 26  maintains at Vcc+ΔV, and the voltage at the node Q 25  becomes Vcc+ΔV, since the node Q 25  is connected to the node Q 27  through the PMOS transistor P 26 . At this time, the voltage at the node Q 28  becomes Vcc+2ΔV, since the node Q 28  is connected to the node Q 25  through the turned on PMOS transistor P 28 , and the voltages at the bulk of PMOS transistors P 27  and P 28  maintain at Vcc+2ΔV.  
         [0044]    In the third stage PS 3 , when the clock signal φ is HIGH while φB is LOW, the voltages at the nodes Q 30  and Q 29  are Vcc+3ΔV and Vcc+2ΔV respectively. Since the voltage at the node Q 29  is lower than that of Q 30 , the PMOS transistors P 29  and P 30  are turned ON while the NMOS transistor N 25  is turned OFF.  
         [0045]    Also, since the voltage at the node Q 30  is higher than Vcc+2ΔV, the NMOS transistor N 26  is turned ON. Since the voltage at the node Q 30  is higher than that of the node Q 29 , the PMOS transistors P 31  and P 32  are turned OFF. Thus, the voltage at the node Q 29  maintains at Vcc+2ΔV, and the node Q 30  becomes Vcc+3ΔV, since the node Q 30  is connected to the node Q 31  through the PMOS transistor P 29 . The voltage at the node Q 31  maintains at Vcc+3ΔV and is outputted to the output terminal Vout. At this time, the voltage at the node Q 32  becomes Vcc+3ΔV since the node Q 32  is connected to the node Q 30  through the PMOS transistor P 30 , and the voltages at the bulk of PMOS transistors P 29  and P 30  maintain at Vcc+3ΔV.  
         [0046]    While the above description about the charge pumping operation is for the time when the clock signal φ is HIGH, the final output voltage Vout of Vcc+3ΔV can also be obtained even when the clock signal φ is LOW, i.e., its complementary clock bar signal φB is HIGH. With reference to the high-leveled clock signal φB, the voltage of Vcc+ΔV is transferred from the first stage PSI to the second stage PS 2  through the PMOS transistor P 23  and the voltage of Vcc+2ΔV is transferred to the third stage PS 3  from the second stage PS 2  through the PMOS transistor P 25 . And finally, the Vcc+3ΔV is transferred to the output terminal Vout from the third stage through the PMOS transistor P 31 . As a result, the charge pump circuit of FIG. 2 always generates the Vcc+3ΔV as the output voltage. It should be understood that, either with φ or with φB, there is no voltage drop because the pumped voltages are transferred through the PMOS transistors.  
         [0047]    [0047]FIG. 3 shows another example of a charge pump circuit according to the invention, composed of three pumping stages PS 1 ′, PS 2 ′, and PS 3 ′, such as that of FIG. 2.  
         [0048]    Referring to FIG. 3, in the first pumping stage PS 1 ′, between Vcc and a node Q 42  is connected a first NMOS transistor N 41  whose gate and bulk are coupled to the node Q 41  and a node Q 44  respectively. Between the node Q 41  and a node Q 43  is connected a first PMOS transistor P 41  whose gate and bulk are coupled to the node Q 41  and a node Q 45  respectively. A first capacitor C 41  is coupled between a clock terminal and a node Q 42 . Between the nodes Q 42  and Q 44  is connected a second NMOS transistor N 42  whose gate and bulk are coupled to the node Q 41  and the node Q 44  respectively. Between the nodes Q 42  and Q 45  is connected a second PMOS transistor P 42  whose gate and bulk are coupled to the nodes Q 41  and Q 45  respectively.  
         [0049]    Between Vcc and the node Q 41  is connected a third NMOS transistor N 43  whose gate is coupled to the node Q 42 . Between the nodes Q 41  and Q 43  is connected a third PMOS transistor P 43  whose gate and bulk are coupled to the nodes Q 42  and Q 45  respectively. A second capacitor C 42  is coupled between the complementary clock bar terminal and the node Q 41 . Between the nodes Q 41  and Q 44  is connected a fourth NMOS transistor N 44  whose gate and bulk are coupled to the node Q 42  and Q 44  respectively. Between the nodes Q 41  and Q 45  is connected a fourth PMOS transistor P 44  whose gate and bulk are coupled to the nodes Q 42  and Q 45  respectively.  
         [0050]    As shown in FIG. 3, the first pumping stage PS 1 ′ is constructed of cross-coupled transistor pairs of N 41  and N 43 , N 42  and N 44 , P 41  and P 43 , and P 42  and P 44 . The NMOS transistors N 42  and N 44  are to regulate a bulk voltage of the NMOS transistors N 41  and N 43  those transfer a voltage level thereto from a prior stage. The PMOS transistors, P 42  and P 44 , cut off a current flowing through the bulk of the PMOS transistors P 41  and P 43  in order to prevent an abnormal conduction of them.  
         [0051]    Other pumping stages, PS 2 ′ and PS 3 ′, are constructed in the same circuit pattern with the first pumping stage PS 1 ′. That is, the second pumping stage PS 2 ′ is constructed of cross-coupled pairs of N 45  and N 47 , N 46  and N 48 , P 45  and P 47 , and P 46  and P 48 . The third pumping stage PS 3 ′ is constructed of cross-coupled pairs of N 49  and N 51 , N 50  and N 52 , P 49  and P 51 , and P 50  and P 52 .  
         [0052]    The charge pump circuit shown in FIG. 3 further includes the NMOS transistors, e.g., N 42  and N 44 , to regulate the bulk voltage of other NMOS transistors, e.g., N 41  and N 43 . The addition of the NMOS transistors overcomes a limit to the number of pumping stages. If the pumping stages approximate more than five, it is hard to transfer a high voltage via the stages due to a body effect of the NMOS transistor. The body effect increases a threshold voltage of the NMOS transistor. Therefore, a desired high voltage cannot be obtained at an output terminal. As shown in FIG. 3, the bulk of the NMOS transistors N 41  and N 43  is controlled through the bulk of the NMOS transistors N 42  and N 44 , not connected to a ground voltage but to sources of the NMOS transistors N 42  and N 44 , so that the body effect does not more severe in accordance with an increase of the pumping stages.  
         [0053]    [0053]FIG. 4 graphically illustrates a comparison result about multiplication efficiency of charge pump circuits, the Dickson&#39;s of (the curve A), the conventional one shown in FIG. 1 (the curve B), and the present one shown in FIG. 2 (the curve C), by means of HSPICE simulation. In the graph of FIG. 4, it is assumed that each charge pump circuit is composed of four pumping stages. The multiplication efficiencies are along an increase of the power supply voltage Vcc, being obtained by Vout/5Vcc. The 5Vcc is the maximum voltage permitted by the four-stage pumping circuit. It is also assumed that: a loading capacitor (C LOAD ) coupled between the output terminal Vout and the ground voltage, e.g., C 15  or C 27 , is 100 pF; the pumping capacitor coupled to the clock signal, e.g., C 11  or C 21 , is 20 pF; and a pumping frequency (F PUMP ) is 10 MHz.  
         [0054]    As shown in FIG. 4, the Dickson&#39;s curve A is characterized with the lowest multiplication efficiency, which is caused from the fact that voltage drops happen at every pumping stages. The circuit of FIG. 1 has higher multiplication efficiency than that of the Dickson&#39;s because it meets to a voltage drop only at the output terminal through the diode-coupled NMOS transistor (i.e., T 14 ). And, it can be seen by the curve C that the circuit of FIG. 2 generates the highest multiplication efficiency. Such an advanced result of the curve C rises from the fact that pumped voltages at the stages are transferred through the PMOS transistors, by which there is no voltage drop for the pumping voltages. Without a voltage loss throughout the serial pumping stages, the charge pump circuit of FIG. 2 can obtain the multiplication efficiency reaching 0.9 even in a lower power supply voltage such as 1.5 V.  
         [0055]    [0055]FIG. 5 shows variable characteristics of an output voltage in accordance with the number of the pumping stages. The curves D, E, F, and G are relevant to the circuit shown in FIG. 1, the circuit shown in FIG. 2, the circuit shown in FIG. 1 in which a voltage level of the clock signal rises up to 2Vcc from Vcc, and the circuit shown in FIG. 3. As shown with the curves D and E, the output voltage does not increase more if the number of pumping stages is over five approximately, i.e., a saturation state if the output voltage. On the other hand, the curves F and G continue to increase along the number of pumping stages. However, the clock signal of 2Vcc (F) is not advantageous to lightening a voltage stress against gate oxide layers of the MOS devices forming the charge transfer switches in FIG. 1. As a result, the charge pumping circuit shown in FIG. 3 generates a higher output voltage than any other types.  
         [0056]    As aforementioned, the charge pump circuit of the invention desirably generates a high voltage without causing a voltage stress on gate oxide layers of MOS devices constructing the circuit. In addition, the circuit of the invention enhances the efficiency of transferring pumped voltages without voltage drops. Moreover, the present charge pumping circuit overcomes the limit in the number of pumping stages, being free from a saturation state of an output voltage due to body effects that increases threshold voltages of MOS devices forming the circuit.  
         [0057]    While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.