Abstract:
A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to semiconductor component manufacturing techniques. 
       DISCUSSION OF THE RELATED ART 
       [0002]    In the field of semiconductor components, transistors having an active portion (channel, base) completely surrounded with a control electrode enabling, according to its bias state, setting the transistor to an on or off state, are known. 
         [0003]    US Patent Application 2002/0149031 (Samsung) discloses a transistor comprising a silicon nanofinger fully surrounded with a gate electrode. This transistor has various drawbacks, in particular as regards the high value of the gate-source and gate-drain capacitances. 
       SUMMARY OF THE INVENTION 
       [0004]    Thus, an object of the present invention is to overcome at least some of the disadvantages of the methods resulting in the above-mentioned devices. 
         [0005]    Another object of the present invention is to provide a method for manufacturing a transistor with parallel semiconductor nanofingers which is particularly efficient and simple to implement and that provides low gate-source and gate-drain capacitances. 
         [0006]    To achieve these and other objects, the present invention provides a method for manufacturing a transistor with semiconductor nanofingers in parallel, comprising: 
         [0007]    forming a single-crystal layer of a semiconductor material on a layer of an underlying material selectively etchable with respect to the single-crystal layer; 
         [0008]    etching parallel walls in the single-crystal layer and in the underlying layer and etching away a portion of said layer of an underlying material; 
         [0009]    filling the interval between the walls and the etched away portion with a first insulating material; 
         [0010]    delimiting a central portion of the walls and eliminating the first insulating material around the central portion of said single-crystal layer, whereby a finger of said semiconductor material is formed; and 
         [0011]    filling and coating the central portion with a conductive material. 
         [0012]    According to an embodiment of the present invention, the walls have a width smaller than 100 nm, preferably smaller than 50 nm. 
         [0013]    According to an embodiment of the present invention, the method comprises, before the step of filling with a conductive material, the step of coating with a second insulating material ( 22 ) the finger periphery. 
         [0014]    According to an embodiment of the present invention, the coating with an insulator comprises a thermal oxidation. 
         [0015]    According to an embodiment of the present invention, the method comprises, before the step of filling with a conductive material, the step of performing an anneal to round the finger periphery. 
         [0016]    According to an embodiment of the present invention, the semiconductor layer is a silicon layer and the underlying layer is a silicon-germanium layer. 
         [0017]    According to an embodiment of the present invention, the silicon-germanium layer rests on a thin lower silicon layer forming the upper portion of an SOI-type structure and, in the finger etch step, fingers are also formed in the lower layer. 
         [0018]    According to an embodiment of the present invention, the method provides several semiconductor finger stages. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
           [0020]      FIG. 1  is a partial perspective view of a structure according to the present invention at an intermediary manufacturing stage; 
           [0021]      FIG. 2  is a partial top view corresponding to  FIG. 1 ; 
           [0022]      FIG. 3  is a cross-section view along line III-III of  FIG. 2 , corresponding to  FIG. 1 ; 
           [0023]      FIG. 4  is a top view showing the structure at a subsequent manufacturing step according to the present invention; 
           [0024]      FIG. 5  is a cross-section view along line V-V of  FIG. 4  at a subsequent manufacturing stage according to the present invention; 
           [0025]      FIG. 6  is a cross-section view similar to that of  FIG. 5  at a subsequent manufacturing stage according to the present invention; and 
           [0026]      FIGS. 7A and 7B  are cross-section views along line VII-VII of  FIG. 4  of two alternative embodiments at a subsequent manufacturing step according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]      FIG. 1  is a perspective view of a structure at an intermediary manufacturing step according to an example of implementation of the method according to the present invention. In this example of implementation, it is started from a structure currently commonly available for sale, called an SOI wafer, comprising on a silicon substrate  1  a thin insulating layer  2 , currently silicon oxide, and a single-crystal silicon layer  3 . On single-crystal silicon layer  3 , a single-crystal silicon-germanium layer  4  and a single-crystal silicon layer  5  have successively been grown. The assembly is coated with a layer used as a hard etch mask  6 , currently silicon nitride. This hard mask is etched according to the pattern shown in top view in  FIG. 2 , to define openings  11  between walls  12  which extend from a block  13  to a block  14 . 
         [0028]    According to an aspect of the invention, during the formation of openings  11  between the walls  12 , the silicon-germanium  4  is etched away in the walls  12  and partially outside openings  11 , as shown by the dashed lines  15  under blocks  13  and  14 . 
         [0029]    As illustrated in the perspective view of  FIG. 1  and the cross-section view of  FIG. 3 , which is a cross-section along plane III-III of  FIG. 2 , each wall extends vertically down to insulating layer  2  and thus comprises the superposition of corresponding portions of single-crystal silicon layer  3 , of single-crystal silicon layer  5 , and of hard mask  6  single-crystal silicon-germanium layer  4  has been etched away. Similarly, each of blocks  13  and  14  comprises a portion of the stacking of layers  3 ,  5 , and  6 . 
         [0030]    The result of a subsequent step during which openings  11  have been filled between walls  12  with an insulating material  16  selectively etchable with respect to the various materials forming walls  12  has also been illustrated in  FIG. 3 . Insulating material  16  may for example be silicon oxide deposited by chemical vapor deposition, the deposition step being followed by a physico-chemical polishing step to bring the upper surface of material  16  to the level of the upper surface of hard mask  6 . It will be understood that the insulating material fills in the spaces from which portions of the silicon-germanium layer  4  have been etched away. 
         [0031]    Then, as illustrated in the top view of  FIG. 4 , the portion external to a central area of the walls is masked according to the contour designated by dotted lines  20 . Previously-described hard mask  6  and all of insulating material  16  is then eliminated between dotted lines  20 . The etching of insulator  16  is carried on down to insulating layer  2 . The central portion of walls  12  has thus been disengaged across the entire length and depth of this central area. 
         [0032]      FIG. 5  is a cross-section view along line V-V of  FIG. 4 , that is, along to the length of a wall  12 . In this drawing, the longitudinal limits between a wall and blocks  13  and  14  (see  FIG. 4 ) have been indicated by vertical dotted lines. At the step illustrated in  FIG. 5 , after having eliminated insulating material  16  between walls  12  in the central portion thereof, a selective isotropic etching of intermediary insulating layer  16  comprised between silicon layers  3  and  5  has been performed. An upper silicon finger  21  is thus disengaged but insulating regions  16 - 1  and  16 - 2  remain under extensions of the silicon finger at the neighborhood of source and drain regions. An insulating coating is then formed around finger  21  to form an insulating ring designated in  FIG. 5  with reference numeral  22 . This insulator is formed by any selected means, for example, by thermal oxidation. In the same step, an insulator  23  has been formed on the upper side and around the apparent portions of a lower silicon finger  25  formed in silicon layer  3  and resting on insulating layer  2 . At a same step or at a subsequent step, the exposed portions of insulating regions  16 - 1  and  16 - 2  are also coated with an insulator  24 . The hollowed step initially occupied by the silicon-germanium region and then by insulating material  16  is designated with reference numeral  28 . 
         [0033]    At the next step, illustrated in  FIG. 6 , a filling with a conductive material is performed, which then fills all the intervals between fingers and hollowed portion  28  and which covers the structure. This conductive material may be a metal, or heavily-doped polysilicon, preferably at least partially turned into a metal silicide. A planarization, for example, by chem./mech. polishing, is then performed. A conductive ring  29  around the central portion of finger  21  is thus obtained, as illustrated in  FIG. 6 . 
         [0034]    It will be understood the insulating regions  16 - 1  and  16 - 2  improve the isolation between the gates surrounding the fingers and the structures integral with the drain and source blocks. Thus the gate-source and gate-drain couplings is reduced. In the absence of insulating regions  16 - 1  and  16 - 2 , the gate-source and gate-drain couplings would be higher, the silicon-germanium regions being more or less conductive, and being then separated from the gate only by the thin insulating layer  24 . 
         [0035]      FIG. 7A  is a cross-section view, in cross-section plane VII-VII illustrated in  FIGS. 4 and 6 , of the structure obtained at the step of  FIG. 6 . It shows in cross-section view upper silicon fingers  21  and lower silicon fingers  25 . Fingers  21  and  25  are surrounded with insulator, respectively  22  and  23 , and are embedded in the conductive layer formed of material  29 . 
         [0036]    The present invention is likely to have many variations which will be described hereafter, some of which are aspects of the present invention. It should be noted that these variations may be used separately or in combination. 
         [0037]    According to a first variation of the present invention, the result of which is illustrated in  FIG. 7B , after having disengaged semiconductor fingers  21  at the steps described in relation with  FIGS. 4 and 5 , an anneal is performed to turn the fingers with substantially square or rectangular cross-sections into fingers with rounded, round, or oval cross-sections. The other steps of the present invention are unchanged. This variation provides a better quality still of control by the gate of the MOS transistor fingers. It should be noted that, according to an aspect of the present invention, the anneal occurs while only the active portions of the silicon fingers which will be surrounded with the control conductor overhang. Finger bending risks, which would appear if the fingers exhibited great lengths when overhanging, are thus limited. 
         [0038]    According to a second variation of the present invention, it is aimed at eliminating lower fingers  25 , to obtain a structure only comprising fingers  21  completely surrounded with a conductor. For this purpose, the present invention provides two ways. 
         [0039]    The first way comprises the use of a structure in which layer  3  does not exist, that is, in which silicon-germanium  4  directly rests on an insulating support  2 . In this case, all the previously-described steps may be used identically. 
         [0040]    According to a second way, upper silicon layer  5  is not used. The structure then only comprises single-crystal silicon layer  3  coated with single-crystal silicon-germanium layer  4  and, instead of selectively etching the silicon-germanium with respect to silicon, the silicon is selectively etched with respect to the silicon-germanium. This structure, with silicon-germanium fingers, may become preferable, if oxidation and lateral silicon-germanium insulation methods are improved. 
         [0041]    According to a third variation, an SOI-type structure with several stages in which a first insulating layer, a first semiconductor layer, a second insulating layer, and a second semiconductor layer, have been assembled on a substrate, is used as a starting structure. The fingers are obtained by selectively etching the insulator with respect to the semiconductor. 
         [0042]    According to a fourth variation of the present invention, instead of providing a single stage of conductive fingers, several stages are provided by alternating the selectively-etchable semiconductor layers. For example, by making an Si—SiGe—Si—SiGe—Si—SiGe—Si . . . sandwich or an Si—SiO 2 —Si—SiO 2 —Si—SiO 2 e-Si . . . sandwich. This method can be implemented without modifying whatsoever the previously-described steps of implementation of the present invention. 
         [0043]    The present invention has been more specifically described in the context of the forming of a MOS transistor with parallel nanofingers. The present invention also enables forming bipolar transistors with parallel nanofingers. The method remains substantially the same, with the difference that the doping levels will be properly selected and that the control electrode, instead of being an insulated gate, will be a conductive portion (possibly a silicide) in direct contact with the central portion of each finger which then forms the base of the bipolar transistor. 
         [0044]    The present invention easily lends itself to the forming of adapted dopings for the channel, source, and drain, or base, emitter, and collector regions. The doping steps may be provided at various stages of the method. These steps will not be detailed herein since they are quite apparent to those skilled in the art. LDD-type MOS transistor structures, comprising less doped source and drain regions in the immediate vicinity of the channel region may especially be formed, by using conventional techniques with spacers, or others. 
         [0045]    Assemblies of semiconductors other than Si and SiGe may be used. A couple of materials such that one of these materials can be used as a support for the single-crystal growth of a semiconductor material and is selectively etchable with respect to the other must only be provided. 
         [0046]    As an example of embodiment of the present invention, and only in the context of a specific technology, it should be noted, referring to  FIG. 1 , that silicon layers  3  and  5  may have thicknesses from 10 to 20 nm and silicon-germanium layer  4  has a thickness on the order of from 20 to 30 nm. The width of walls  12  may range from 10 to 20 nm. The interval between walls may range from 30 to 40 nm. The active portions of the fingers form a channel or base area and for example have a length on the order of from 5 to 30 nm. 
         [0047]    Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.