Abstract:
A digital phase lock detector and phase lock loop filter selector circuit implemented in hardware that dynamically selects a phase lock loop filter of appropriate bandwidth for the instant phase error condition. Phase error is primarily determined by an XOR gate receiving the PLL reference signal and the oscillator feedback signal coupled to a counter that is clocked by a high frequency signal.

Description:
FIELD OF THE INVENTION 
     This invention relates to phase lock loops, and more particularly to a digital phase lock detector and phase lock loop filter selector in a phase lock loop. 
     BACKGROUND OF THE INVENTION 
     A phase lock loop (PLL) is a circuit used to synthesize a &#34;clean&#34; output signal based on an input reference signal that may be noisy and jittery. The output signal will have the same long-term frequency and phase as the input signal. 
     The components of a typical PLL include an input reference signal, which displays a level of noise and jitter that may be unacceptable. A voltage controlled oscillator (VCO) is used to produce the PLL output signal. The input reference signal and the PLL output signal, which is carried by a feedback loop from the VCO output, are input to a phase detector which produces an error signal indicating the magnitude of the phase difference between the input reference signal and the PLL output signal. The phase error signal is integrated through a phase lock loop filter and input as a control signal to the VCO. This control signal causes the phase of the VCO output signal to converge on the phase of the input reference signal, thus minimizing the phase error. 
     In designing a PLL for a specific application, a decision must be made regarding the value of the bandwidth of the phase lock loop filter. A low-pass filter with a higher bandwidth will cause the VCO output signal to converge on the input reference signal more rapidly. However, the low-pass filter will be more sensitive to fluctuations in phase and frequency, and thus cause the VCO output signal to exhibit a larger degree of instability. A low-pass filter with a lower bandwidth will cause the VCO output signal to exhibit a larger degree of long-term stability, but the PLL will take longer to converge on the input reference signal when fluctuations in phase and frequency are present. 
     Therefore, it is desirable to have functionality incorporated into a PLL that will automatically select among a set of available phase lock loop filters the one that, for the instant situation, will most rapidly bring the VCO output signal into convergence with the input reference signal. 
     In the field of the present invention, i.e., digital PLLs, a known solution to providing functionality to select an appropriate phase lock loop filter is a microprocessor-controlled digital phase lock detector that determines the magnitude of the phase error and adjusts the bandwidth of the loop filter. However, a microprocessor and the firmware required to control the PLL can be too expensive a solution. 
     Accordingly, it is an object of the present invention to provide a relatively inexpensive circuit in hardware for use in analog or digital PLLs that will automatically generate a phase lock loop filter selection signal that is based on the magnitude of the phase error between an input reference signal and the VCO output signal. 
     SUMMARY OF THE INVENTION 
     The present invention provides a digital phase lock detector (DPLD) for use in an analog phase lock loop (PLL) or a digital phase lock loop (DPLL) that provides a control signal to be used to select a phase lock loop filter of the appropriate bandwidth. In the illustrative embodiment, the DPLD of the present invention comprises two circuits. The fast lock circuit is used to acquire initial lock and also when the digital controlled oscillator feedback signal and reference signal become greater than perfect lock ±90 degrees out of phase. When this circuit is active, the output control signal of the DPLD indicates to use the broadest bandwidth low-pass filter for fast lock acquisition. This circuit determines that the oscillator feedback signal and the reference signal are within perfect lock ±90 degrees for 256 consecutive cycles of the reference signal, and then transmits a DPLD output signal indicating that the narrow bandwidth low-pass filter should now be used to acquire and keep perfect lock. The fine adjustment circuit of the DPLD now becomes active. This circuit continues to transmit the DPLD output signal indicating that the narrow bandwidth low-pass filter should be used while the feedback signal and the reference signal are within perfect lock ±45 degrees. If the feedback signal and reference signal become greater than perfect lock ±45 degrees out of phase, the fine adjustment circuit transmits a DPLD output signal indicating that the medium bandwidth low-pass filter should be used to bring the feedback signal and the reference signal to within perfect lock ±45 degrees. The circuit then transmits the DPLD output signal indicating that the narrow bandwidth low-pass filter can again be used to acquire and keep perfect lock. Should the feedback signal and reference signal become greater than perfect lock ±90 degrees out of phase, the fast lock circuit becomes active again. The fine adjustment circuit uses a counter to determine the phase angle between the feedback signal and the reference signal. The counter is clocked by a signal that has a much higher frequency than the reference signal, and is enabled during the pulse output of an XOR gate that receives the feedback and reference signals. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of the illustrative embodiment of the present invention. 
     FIGS. 2A and 2B show a logic diagram of the digital phase lock detector of the present invention. 
     FIG. 3 shows a first timing diagram of selected signals present in the digital phase lock detector of the present invention. 
     FIG. 4 shows a second timing diagram of selected signals present in the digital phase lock detector of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The illustrative embodiment of the present invention is a DPLD in a DPLL that monitors an input reference frequency and dynamically switches between three low-pass filter bandwidths of the DPLL to ensure that the DPLL output signal is on-frequency and phase-locked and free from the jitter and other perturbations of the input reference signal. The DPLD controls a DPLL that is used in a synchronized optical network (SONET) clock system. The DPLD&#39;s input reference frequency is extracted from a fiber optic signal received from another SONET node that typically is many miles away. Since the SONET input reference signal may contain high frequency jitter, low frequency phase shifts and large phase jumps due to clock rearrangements upstream, the DPLL must be able to average out these perturbations and phase jumps and supply an on-frequency jitter-free clock at its output. 
     In order to supply an on-frequency jitter-free clock output, the DPLL of the illustrative embodiment uses a very low bandwidth low-pass filter of approximately 0.1 Hz. The 0.1 Hz bandwidth works well under normal phase locked conditions to extract the long term frequency average from the input frequency reference signal, but may not be capable of initially acquiring lock or following small phase jumps. To initially acquire lock, a higher bandwidth low-pass filter bandwidth of approximately 10 Hz is used. The 10 Hz bandwidth is ideal for quickly acquiring lock but is too high a bandwidth to extract the long-term average frequency. Therefore, the bandwidth of the low-pass filter is switched to 0.1 Hz after phase lock is acquired. To follow small phase jumps, a low-pass filter bandwidth of approximately 1 Hz is used. The 1 Hz bandwidth works well to keep the DPLL locked during small phase jumps but is also too high a bandwidth to extract the long-term average frequency. Therefore the low-pass filter bandwidth is switched to 0.1 Hz after phase lock is established. The DPLD of the present invention determines the phase error between the input reference signal and the DPLL output signal and generates a low-pass filter selection control signal that causes the DPLL to select the appropriate low-pass filter bandwidth. 
     FIG. 1 shows a block diagram of the DPLL of the illustrative embodiment of the present invention. Digital phase lock detector DPLD 1 receives 8 KHz reference signal 8K --  REF over lead 2, 8 KHz digital controlled oscillator output signal 8K --  DCO over lead 3, and 4.32 MHz DPLD counter clock signal 4 --  32M over lead 4. DPLD 1 transmits low-pass filter select signals 0.1HZ --  OR --  1HZ and 10 --  HZ over leads 5 and 6, respectively, to logic block 7. Logic block 7 transmits a low-pass filter control signal over lead 8 to the modulus control input of digital loop filter counter K-COUNTER 9. K-COUNTER 9 also receives a 12.96 MHz clock signal 12 --  96M over lead 10 and a phase angle signal from XOR gate 11 over lead 12. K-COUNTER 9 transmits a &#34;carry&#34; signal over lead 13 to the increment input of increment/decrement counter ID --  CNTR 15, and a &#34;borrow&#34; signal over lead 14 to the decrement input of ID --  CNTR 15. ID --  CNTR 15 also receives signal 12 --  96M over lead 10, and transmits a 6.48 MHz DPLL output signal 6 --  48M over lead 16. K-COUNTER 9 and XOR gate 11 comprise the loop filter of the DPLL, and ID --  CNTR 15 comprises the digital controlled oscillator. K-COUNTER 9, XOR gate 11, and ID --  CNTR 15 comprise LOOP FILTER AND DCO 22. 
     Signals 8K --  REF on lead 2 and 4 --  32M on lead 4 are both derived from an OC3 155.52 MHz line signal 155 --  52M on lead 17 from another SONET system, and are divided down by frequency dividers 18 and 19, respectively. Signal 8K --  DCO on lead 3 is derived from ID --  CNTR output signal 6 --  48M on lead 16 and is divided down by frequency divider 20. Signal 12 --  96M on lead 10 is generated by a 12.96 MHz oscillator 21. 
     In operation, signal 155 --  52M on lead 17 is the external reference signal for the DPLL. Signal 155 --  52M is divided down by frequency divider 18 and is presented to DPLD 1 as signal 8K --  REF on lead 2. Signal 6 --  48M on lead 16 from ID --  CNTR 15 is the output signal of the DPLL, and is divided down by frequency divider 20 and is presented to DPLD 1 as signal 8K --  DCO on lead 3. DPLD 1 measures the phase angle between signals 8K --  REF and 8K --  DCO and, based upon predetermined phase angle values, asserts low-pass filter control signals 10 --  HZ and 0.1HZ --  OR --  1HZ. Signals 10 --  HZ and 0.1HZ --  OR --  1HZ are transmitted to logic control block 7, which transmits a signal in the proper format to the modulus control input of K-COUNTER 9. The modulus of K-COUNTER 9 controls the digital loop filter bandwidth. 
     LOOP FILTER AND DCO 22 of the present invention preferably comprises a Signetics, Inc. model 74HCT297 Digital Phase-Locked Loop Filter. Detailed information on the specifications, use and operation of the 74HCT297 are contained in Signetics publication &#34;74HCT297 Phase-Locked Loop Filter,&#34; 1988. In overview, the operation of K-COUNTER 9 is controlled by the down/up signal received on lead 12 from XOR gate 11. XOR gate 11 acts as a phase detector, with the duty cycle of its output signal dependent on the phase relationship of its two input signals 8K --  REF and 8K --  DCO. When signal 8K --  DCO leads signal 8K --  REF by 90 degrees, the DPLL is in perfect lock, and the output signal of XOR gate 11 will be a pulse train having a duty cycle of 50%. If signal 8K --  DCO leads signal 8K --  REF by more than 90 degrees, then the output signal of XOR gate 11 will be a pulse train with greater logic &#34;1&#34; pulse widths. If signal 8K --  DCO leads signal 8K --  REF by less than 90 degrees, then the output signal of XOR gate 11 will be a pulse train with greater logic &#34;0&#34; pulse widths. 
     K-COUNTER 9 has two counters: an up-counter that is active while the output signal of XOR gate 11 is low, and a down-counter that is active while the output signal of XOR gate 11 is high. Both counters are clocked by signal 12 --  96M on lead 10. Both counters have the same modulus &#34;k&#34; that is controlled by the output signal of logic control block 7 on lead 8, received at the modulus control input of K-COUNTER 9. Both counters roll over to zero when their counts exceed k-1. The most significant bit of the up-counter is output on carry lead 13, and the most significant bit of the down-counter is output on borrow lead 14. When the DPLL is in perfect lock, the pulse count of the carry-out signal will be the same as that of the borrow signal. If signal 8K --  DCO leads signal 8K --  REF by more than 90 degrees, then the pulse count of the borrow signal will be greater than that of the carry signal. If signal 8K --  DCO leads signal 8K --  REF by less than 90 degrees, then the pulse count of the carry signal will be greater than that of the borrow signal. Larger phase errors result in larger pulse count differences between the carry and borrow signals. Higher values of modulus k decrease the pulse frequencies of both the carry and borrow signals. 
     Digital controlled oscillator ID --  CNTR 15 is a counter that is clocked by signal 12 --  96M on lead 10, and outputs signal 6 --  48M on lead 16 that has a frequency equal to half that of the input clock signal. A pulse on increment input lead 13 causes ID --  CNTR 15 to add a pulse to output signal 6 --  48M, and a pulse on decrement input lead 14 causes ID --  CNTR 15 to delete a pulse from output signal 6 --  48M. Thus, when signal 8K --  DCO leads signal 8K --  REF by more than 90 degrees, LOOP FILTER AND DCO 22 operates to decrease the frequency of signal 8K --  DCO until the signals are in lock, and when signal 8K --  DCO leads signal 8K --  REF by less than 90 degrees, LOOP FILTER AND DCO 22 operates to increase the frequency of signal 8K --  DCO until the signals are in lock. Decreasing the value of modulus k corresponds to increasing the bandwidth of the low-pass filter of a DPLL. Because DPLL output signal 6 --  48M is inherently jittery, it may be processed by an analog PLL before further use. 
     In the illustrative embodiment, a clock signal for ID --  CNTR 15 of 12.96 MHz was chosen based on frequency constraints of the model 74HCT297 Digital Controlled Oscillator. A frequency of 8 KHz was chosen for the frequencies of DPLD input signals 8K --  DCO and 8K --  REF in order to achieve the desired loop time constant, as explained in the aforementioned data sheet. 
     FIGS. 2A and 2B show a logic diagram of the illustrative embodiment of the digital phase lock detector and low-pass filter bandwidth selector circuit DPLD 1 of the present invention. DPLD 1 comprises two measuring circuits: a fast lock circuit and a fine adjustment circuit. The fast lock circuit comprises a first deglitch flip-flop DG --  1 51, coarse lock detector flip-flop COARSE --  LOCK 52, 256-bit lock acquisition counter ACQ --  CNTR 53, acquired lock flip-flop ACQ --  LCK 54, acquired lock synchronizer flip-flop A --  L --  SYNC 55, and final lock flip-flop FINAL --  LCK 56. The fine adjustment circuit comprises XOR gate 57, a second deglitch flip-flop DG --  2 58, time gate flop-flop TIMEGATE 59, bandwidth select counter BW --  CNTR 60, XNOR gate 61, and 0.1 Hz or 1 Hz bandwidth selector flip-flop 0.1 --  OR --  1 62. 
     8 KHz Signal 8K --  DCO, derived from output signal 6 --  48M from ID --  CNTR 15, is received at the D input of flip-flop DG --  1 51 over lead 3, and 8 KHz signal 8K --  REF, derived from DPLL external reference signal 155 --  52M on lead 17, is received at the positive-edge triggered clock input of flip-flop DG --  1 51 over lead 2. The Q output of flip-flop DG --  1 51 is received at the D input of flip-flop COARSE --  LOCK 52 over lead 63. Signal 8K --  REF is received at the negative-edge triggered clock input of flip-flop COARSE --  LOCK 52 over lead 2. Counter ACQ --  CNTR 53 receives a constant positive voltage signal at counter enable input EN over lead 64. The Q-complement output of flip-flop COARSE --  LOCK 52 is received by counter ACQ --  CNTR 53 at its CLR input over lead 65. Bit 7 of the 8-bit counter output signal on lead 66 is received by the J input of flip-flop ACQ --  LCK 54. Flip-flop ACQ --  LCK 54 also receives at its K input a constant ground voltage signal over connection 67, and receives signal 8K --  REF at its positive-edge triggered clock input over lead 2, and further receives at its asynchronous reset input the Q-complement output signal of flip-flop COARSE --  LOCK 52 over lead 65. The Q output of flip-flop ACQ --  LCK 54 is received by the D input of flip-flop A --  L --  SYNC 55 over lead 68. Flip-flop A --  L --  SYNC 55 also receives signal 4 --  32M, derived from DPLL external reference signal 155 --  52M, over lead 4 at its negative-edge triggered clock input, and receives at its asynchronous reset input the Q-complement output signal from flip-flop COARSE --  LOCK 52 over lead 65. The Q output of flip-flop A --  L --  SYNC 55 is received by the J input of flip-flop FINAL --  LCK 56 over lead 69. The K input of flip-flop FINAL --  LCK 56 receives a constant ground voltage signal over connection 70, and receives at its asynchronous reset input the Q-complement output signal from flip-flop COARSE --  LOCK 52 over lead 65. Signal 10 --  HZ is transmitted on the Q-complement output of flip-flop FINAL --  LCK 56 over lead 6. 
     XOR gate 57 receives signal 8K --  DCO over lead 3 and signal 8K --  REF over lead 2. Output signal PH --  DIFF from XOR gate 57 is received by flip-flop DG --  2 58 at its D input over lead 71. Flip-flop DG --  2 58 also receives signal 4 --  32M at its negative-edge triggered clock input over lead 4. The Q output of flip-flop DG --  2 58 is received by the D input of flip-flop TIMEGATE 59 over lead 72. Flip-flop TIMEGATE 59 also receives signal 4 --  32M at its positive-edge triggered clock input over lead 4. The Q-complement output of flip-flop TIMEGATE 59 is received at the CLR input of counter BW --  CNTR 60 over lead 73. Counter BW --  CNTR 60 also receives a constant positive voltage at its counter enable input EN over lead 74, and signal 4 --  32M at its negative-edge triggered clock input over lead 4. Bits (7:6) of the 8-bit counter output signal on lead 75 are received by XNOR gate 61. Flip-flop 0.1 --  OR --  1 62 receives the output signal of XNOR gate 61 at its D input over lead 76, and receives the Q-complement output of flip-flop TIMEGATE 59 at its positive-edge triggered clock input over lead 73. The Q output of flip-flop 0.1 --  OR --  1 62 transmits DPLD 1 output signal 0.1HZ --  OR --  1HZ on lead 5. 
     Not shown in FIGS. 2A and 2B are power-up and system asynchronous reset signals to flip-flops DG --  1 51, COARSE --  LOCK 52, DG --  2 58, TIMEGATE 59, and 0.1 --  OR --  1 62. 
     The fast lock circuit of DPLD 1 indicates that the phase angle between signals 8K --  DCO and 8K --  REF is between 0 and π radians, and has stayed so for a predetermined number of 8K --  REF cycles. In the fast lock circuit of DPLD 1, flip-flop DG --  1 51 receives signal 8K --  DCO at its D input over lead 3, and signal 8K --  REF at its clock input over lead 2. While signal 8K --  DCO leads signal 8K --  REF by 0&lt;Φ≦π, where Φ is the phase angle between signals 8K --  DCO and 8K --  REF, a logic &#34;1&#34; will be clocked into flip-flop DG --  1 51 at each leading edge of signal 8K --  REF. This logic &#34;1&#34; is clocked into flip-flop COARSE --  LOCK 52 over lead 63 at each trailing edge of signal 8K --  REF. This arrangement of flip-flops 51 and 52 will be recognized as a common method to clock a glitch-free input signal into flip-flop 52, and is used elsewhere in the DPLD circuit of the present invention. 
     While flip-flop COARSE --  LOCK 52 is receiving a logic &#34;1&#34; from flip-flop DG --  1 51, the Q-complement output signal of flip-flop COARSE --  LOCK 52 asserted on the CLR input of counter ACQ --  CNTR 53 over lead 65 will be a logic &#34;0&#34;, allowing counter ACQ --  CNTR 53 to increment with each leading edge of signal 8K --  REF received by counter ACQ --  CNTR 53 over lead 2. When counter ACQ --  CNTR 53 reaches a count of 256, bit 7 of the counter output signal on lead 66 is asserted, and signals 8K --  DCO and 8K --  REF are considered to be in coarse lock. A counter value of 256 for counter ACQ --  CNTR 53 was chosen based on the period of signal 8K --  REF and a desired interval to allow the DPLL to converge to a phase locked condition using the broad low-pass filter bandwidth. If signal 8K --  DCO leads signal 8K --  REF by π&lt;Φ≦2π, the Q-complement output signal of flip-flop COARSE --  LOCK 52 asserted on the CLR input of counter ACQ --  CNTR 53 will be a logic &#34;1&#34;, causing ACQ --  CNTR 53 to reset to zero until signal 8K --  DCO again leads signal 8K --  REF by 0&lt;Φ≦π. 
     FIG. 3 shows a timing diagram illustrating the phase relationship governing coarse lock. Phase angle Φ is defined by leading edge 301 of signal 8K --  DCO and leading edge 302 of signal 8K --  REF. While 0&lt;Φ≦π, leading edge 302 of signal 8K --  REF will clock signal 8K --  DCO into flip-flip DG --  1 51 while signal 8K --  DCO has a value of logic &#34;1&#34;. If π&lt;Φ≦2π, leading edge 302 of signal 8K --  REF will clock signal 8K --  DCO into flip-flip DG --  1 51 while signal 8K --  DCO has a value of logic &#34;0&#34;, causing counter ACQ --  CNTR 53 to reset. 
     Referring again to FIGS. 2, bit 7 of the counter output signal from counter ACQ --  CNTR 53 over lead 66 is received by the J input of flip-flop ACQ --  LCK 54. When bit 7 of the counter output signal goes to &#34;1&#34; at a counter value 256, it is clocked into flip-flop ACQ --  LCK 54 at the next leading edge of signal 8K --  REF. The Q output of flip-flop ACQ --  LCK 54 is then clocked into flipflop A --  L --  SYNC 55 at the next trailing edge of signal 4 --  32M and appears on the Q output lead 69, where it is then clocked into flip-flop FINAL --  LCK 56 at the next leading edge of signal 4 --  32M, and then appears as a &#34;0&#34; on the Q-complement output of flip-flop FINAL --  LCK 56 on lead 6 as signal 10 --  HZ. Signal 10 --  HZ will remain at logic &#34;1&#34; after coarse lock has been established and while signal 8K --  DCO leads signal 8K --  REF by 0&lt;Φ≦π. If phase angle Φ falls outside this range, flip-flops ACQ --  LCK 54, A --  L --  SYNC 55 and FINAL --  LCK 56 will be reset by the Q-complement signal of flip-flop COARSE --  LOCK 52 on lead 65 causing signal 10 --  HZ to go to &#34;1&#34;. Signal 10 --  HZ will remain at &#34;1&#34; until coarse lock is again established by counter ACQ --  CNTR 53. 
     When signal 10 --  HZ changes to a value of logic &#34;0&#34;, it indicates that the DPLL has had sufficient time to converge on phase lock using the broad low-pass filter, and the two narrow low-pass filters may now be used to fine adjust the DPLL to perfect lock. 
     In the fine adjustment circuit of the DPLD 1, XOR gate 57 receives signal 8K --  DCO over lead 3, and signal 8K --  REF over lead 2. Output signal PH --  DIFF from XOR gate 57 on lead 71 will have pulses with a pulse width corresponding to the phase difference between signals 8K --  DCO and 8K --  REF, and will have a 50% duty cycle when the DPLL is perfectly locked, i.e., signal 8K --  DCO leads signal 8K --  REF by exactly 90 degrees. 
     As signal 8K --  DCO leads signal 8K --  REF by phase angles from 0 to π, signal PH --  DIFF over lead 71 will have duty cycles starting at zero and increasing to 100%. While signal PH --  DIFF has a value of logic &#34;1&#34;, a logic &#34;1&#34; will be clocked into flip-flop DG --  2 58 at each trailing edge of 4.32 MHz signal 4 --  32M. This logic &#34;1&#34; is clocked into flip-flop TIMEGATE 59 over lead 72 at each leading edge of signal 4 --  32M, causing the Q-complement output of flip-flop TIMEGATE 59 to assert a logic &#34;0&#34; at the CLR input of counter BW --  CNTR 60 over lead 73 and allowing counter BW --  CNTR 60 to increment at each trailing edge of signal 4 --  32M. When signal PH --  DIFF goes to &#34;0&#34;, the Q-complement output of flip-flop TIMEGATE 59 goes to &#34;1&#34; at the CLR input of counter BW --  NTR 60, causing the counter to clear. 
     FIG. 4 shows a timing diagram illustrating the phase relationship governing the control of counter BW --  NTR 60. Phase angle Φ is defined by leading edge 401 of signal 8K --  DCO and leading edge 402 of signal 8K --  REF. Signal PH --  DIFF from XOR gate 57 has pulses defined by a leading edge 403 and trailing edge 404 having width corresponding to phase angle Φ. Leading edge 403 causes the Q-complement signal of flip-flip TIMEGATE 59 on lead 73 to go to &#34;0&#34;, allowing counter BW --  NTR 60 to increment at each trailing edge of signal 4 --  32M. Trailing edge 404 causes the Q-complement signal of flip-flip TIMEGATE 59 on lead 73 to go to &#34;1&#34;, clearing counter BW --  CNTR 60. The value of counter BW --  NTR 60 attained just prior to clearing is indicative of phase angle Φ. 
     It can be seen that as signal 8K --  DCO leads signal 8K --  REF by phase angles from π to 2π, signal PH --  DIFF over lead 71 will have duty cycles starting at 100% and decreasing to zero. Thus, a value of counter BW --  NTR 60 will usually represent two phase angles centered about π. In applications where the value of the phase angle from 0 to 2π is desired, the Q output signal of flip-flop DG --  1 51, or another appropriate downstream signal of the fast lock circuit, in conjunction with the value of the counter output signal of counter BW --  NTR 60 may be used. 
     Referring again to FIGS. 2, XNOR gate 61 receives bits (7:6) of the 8-bit counter output signal of counter BW --  NTR 60 on lead 75. The output signal from XNOR gate 61 over lead 76 will have a value of logic &#34;0&#34; when counter BW --  NTR 60 has values between 64 and 191, inclusive. These values correspond to pulse widths for signal PH --  DIFF of between about 14.8 usec and 44.2 usec, which corresponds to a phase angle between 8 Khz signals 8K --  DCO and 8K --  REF of about 43 degrees to 127 degrees, or roughly perfect lock ±45 degrees. 
     The instantaneous value of the output signal from XNOR gate 61 over lead 76 is clocked into flip-flop 0.1 --  OR --  1 62 when the Q-complement output signal of flip-flip TIMEGATE 59 goes to &#34;1&#34;, which occurs at each trailing edge 404 of signal PH --  DIFF. 
     Thus, the value of flip-flop 0.1OR --  1 62 will be &#34;0&#34; if the phase angle between signals 8K --  DCO and 8K --  REF is within roughly 90±45 degrees, and &#34;1&#34; if the phase angle is outside this range. A value of &#34;1&#34; for signal 0.1HZ --  OR --  1HZ on Q output lead 5 of flip-flop 0.1 --  OR --  1 62 indicates to use the 1 Hz low-pass filter to acquire phase lock, and a value of &#34;0&#34; indicates to use the 0.1 Hz low-pass filter to acquire phase lock. 
     As stated above, if the phase angle between signals 8K --  DCO and 8K --  REF is outside the 90±45 degrees range, but still within the 90±90 degrees range, a &#34;1&#34; will be clocked into flip-flop 0.1 --  OR --  1 62 at the trailing edges of the pulses of signal PH --  DIFF, indicating that the slightly broader 1 Hz low-pass filter is needed to bring the DPLL back into lock. When the phase angle between signals 8K --  DCO and 8K --  REF is again within the 90±45 degrees range, a &#34;0&#34; will be clocked into flip-flop 0.1 OR 1 62 at the trailing edges of the pulses of signal PH DIFF, indicating that the 0.1 Hz low-pass filter is to be used to bring the DPLL back into perfect lock. A value of &#34;1&#34; for signal 10 --  HZ on lead 6 will override signal 0.1HZ --  OR --  1HZ and will force the DPLL to use the 10 Hz low-pass filter of the fast lock circuit to acquire lock. 
     While only one illustrative embodiment is disclosed herein, it will be apparent to those skilled in the art that a DPLD incorporating the inventive concepts disclosed herein can be designed to include any desired number of phase angle range detectors, each with an associated phase angle range and an &#34;in-range/out-of-range&#34; output signal, through a judicious choice for the frequency of the counter timing signal of counter BW --  NTR 60 and appropriate combinatorial logic acting on the counter output signal of counter BW --  NTR 60. 
     While the inventive system has been particularly shown and described, it is not intended to be exhaustive nor to limit the invention to the embodiment disclosed. It will be apparent to those skilled in the art that modifications can be made to the present invention without departing from the scope and spirit thereof. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.