Abstract:
A hardware unit within a DSP includes various circuits and components that allow spreading, complex scrambling, and complex correlation to be performed at the software level in a programmable processor at the speed levels required by third generation wireless communication systems.

Description:
FIELD OF THE INVENTION 
   The present invention relates to digital signal processors, and in particular, to digital signal processing on a chip. 
   DESCRIPTION OF RELATED ART 
   In digital wireless communication systems based on the Wideband CDMA (WCDMA) standard, the transmitter typically performs two operations on the incoming data stream. The first operation is channelization, whereby the data stream is modulated with a binary code sequence called the channelization code. 
   Channelization is actually a form of spreading: As the rate of the channelization code is higher than the data rate, the bandwidth of the channelized data stream is higher than the bandwidth of the original data stream. After channelization, the transmitter performs the second operation, complex scrambling, which modulates the channelized data stream with a complex-valued scrambling code. On the other side of the communication link, the receiver performs complex correlation operations in order to recover the transmitted data. 
   Spreading, complex scrambling, and complex correlation functions have been traditionally implemented by application-specific integrated circuits (ASICs), since software-level implementations on conventional digital signal processors (DSPs) cannot perform those operations with the required efficiency. However, hardware-level implementation requires the design of a complex ASIC device to handle the various parameters in the baseband processing, such as different oversampling factors, different sample bit widths, and different spreading factors. Furthermore, the need for ASICs increases the time-to-market, the complexity, and the cost of the system when compared to a software solution. 
   Accordingly, there is a need for a system that allows wireless baseband processing without the disadvantages discussed above with respect to conventional systems. 
   SUMMARY OF THE INVENTION 
   According to one aspect of the invention, a reconfigurable digital signal processor (DSP) includes a specialized functional hardware unit that enables spreading, complex scrambling, and complex correlation functions to be performed efficiently in software. In one embodiment, such a hardware unit is part of a Reconfigurable Cell (or RC), where a plurality of RCs are contained in the reconfigurable DSP. Software-level spreading and complex scrambling during transmitting and complex correlation during receiving are supported by the unit, thereby resulting in performance higher than previously possible on conventional DSPs and eliminating the need for ASICs. The hardware unit conforms the complex scrambling and complex correlation operations specified in the WCDMA standard. Consequently, wireless baseband processing can be performed with the throughput required by a widely-adopted third generation (3G) wireless communication system. It also supports spreading and correlation as specified in the second-generation IS-95 standard. 
   In one embodiment, the hardware unit is part of a so-called CDMA unit that receives two pairs of data bits, with each pair including in-phase and quadrature data bits. The CDMA unit comprises four blocks, each block receiving a data input and computing the negative value of the input. Four sets of multiplexers select either the input bits or the output of the blocks that calculate the negative of the input, based on the data stored in code registers. The output of the multiplexers are then selectively input to arithmetic circuits for addition and subtraction. Another set of arithmetic circuits subtracts and/or adds values, which can be concatenated, from the first set of multiplexers. A second set of multiplexers selects the outputs of either the first or second set of arithmetic circuits. The output of the second set of multiplexers can then be used by other parts of the DSP. 
   In one embodiment, the hardware unit performs WCDMA channelization by mapping the data bits into a sequence of complex-valued chips. The WCDMA scrambling process consists of modulating the complex-valued chip stream with a complex-valued scrambling code by multiplying the two quantities. The channelized and scrambled data can then be transmitted. In order to recover the transmitted data, the same hardware unit in the receiving reconfigurable DSP computes complex correlation functions between the received chip stream and locally-generated replicas of the same channelization and scrambling codes used by the transmitter. 
   By performing the spreading, complex scrambling, and complex correlation functions within the DSP, instead of using a separate ASIC, wireless baseband processing can be accomplished. Previously, these operations had to be performed completely in hardware, such as ASICs, with less flexibility and higher costs. The present invention, used with higher clock speeds found in deep sub-micron technologies, provides the necessary hardware support to perform the spreading, scrambling, and correlation functions at the software level. 
   The same hardware unit in the DSP is able to support spreading, complex scrambling, and complex correlation for multiple wireless communication systems, such as IS-95, WCDMA, and cdma2000. Further, this allows a single unit to provide the same capability of multiple conventional application-specific integrated circuits. 
   The present invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a CDMA unit within a reconfigurable cell of a reconfigurable DSP, where the CDMA unit performs spreading, complex scrambling, and complex correlation according to one embodiment of the invention; 
       FIG. 2  shows a data path for implementing a spreading operation according to one embodiment of the invention; 
       FIG. 3  shows a data path for implementing a scrambling operation according to one embodiment of the invention; 
       FIG. 4  shows the data flow for a 4-bit complex scrambling operation according to one embodiment of the invention; 
       FIG. 5  shows the data flow for an 8-bit complex scrambling operation according to one embodiment of the invention; 
       FIG. 6  shows a data path for implementing a correlation operation according to one embodiment of the invention; 
       FIG. 7  shows the data flow for a 4-bit correlation operation according to one embodiment of the invention; and 
       FIG. 8  shows the data flow for the 8-bit complex correlation operation according to one embodiment of the present invention. 
   

   Use of the same reference symbols in different figures indicates similar or identical items. 
   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  shows a reconfigurable cell (RC)  100 , which is part of a reconfigurable digital signal processor (rDSP). Numerous RCs form an RC array within the rDSP. RC  100  includes a CDMA (Code Division Multiple Access) unit  105 . According to one embodiment of the invention, CDMA unit  105  performs spreading and complex scrambling at the transmitter and complex correlation at the receiver. These operations will be discussed in detail. CDMA unit  105  receives its input data from the RC input multiplexers  115  and  120 , with each set selected from either the data bus or another RC. CDMA unit  105  then utilizes these signals for spreading, scrambling, and correlation. Multiplexer  115  receives signals from a data bus (not shown), neighboring or adjacent reconfigurable cells, and a register file. Similarly, multiplexer  120  receives signals from the data bus, neighboring or adjacent RCs, and the register file. 
   Spreading Operations 
   In the IS-95 standard, each data bit to be transmitted is mapped into a sequence of chips s n (t), with the number of chips per data bit being called a Spreading Factor (SF). The range of the SF is set forth in the IS-95 standard, and the specific SF selected is through software. The spreading operation can be expressed as follows:
 
 s   n ( t )= d ( t ) C ( t ) 0 ≦n≦SF −1  (1)
 
where d(t) is the input data stream and C(t) is the spreading code sequence, both in the domain {+1,−1}. The result of multiplying the data bit with the spreading code sequence is the chip sequence s n (t). The value +1 is mapped to binary value 0 and value −1 is mapped to binary value 1. In the domain {0,1}, the multiplication in equation (1) becomes a 1-bit modulo-2 addition, which can be implemented by a simple exclusive-or logic gate. Therefore, Equation (1) can be re-written as:
 
 s   n ( t )= d ( t )( xor ) C ( t ) 0 ≦n≦SF −1  (2)
 
where (xor) denotes the Boolean exclusive-or operator. For example, for a spreading factor of 8, correlation operations need to be performed 8 times.
 
     FIG. 2  shows a data path that implements the spreading operation of equation (2) according to one embodiment. Inputs A and B receive the code sequence bits C(t) and the data bits d(t), respectively. Multiplexer  200  is a 4-bit 3-to-1 multiplexer. The three possible inputs are {d 0 , d 1 , d 2 , d 3 }, {d 0 , d 0 , d 1 , d 1 }, and {d 0 , d 0 , d 0 , d 0 }. The input set is selected depending on the spreading factor, as indicated in the table below: 
                                                   Connected to   Selected for           Input   data bits   Spread Factor                           0   d 0 , d 1 , d 2 , d 3     SF = 4           1   d 0 , d 0 , d 1 , d 1     SF = 8           2   d 0 , d 0 , d 0 , d 0     SF ≧ 16                        
In one embodiment, shown in  FIG. 2 , there are 16 sets of exclusive OR gates and multiplexers. So, if the SF is 4, four data bits can be accepted (i.e., 4×4). However, if the SF is 8, only two data bits can be used (i.e., 2×8).
 
   When input  0  of multiplexer  200  is selected (for an SF of 4, i.e. 4 chips per data bit), each of four data bits d 0 , d 1 , d 2 , d 3  is exclusive-ored (with two-input XOR gates  205 ) four times, each time with a different one of four different code bits from input A. When spreading is desired, data bits through multiplexer  200  are selected by 2-to-1 multiplexers  202 , and when data bits are simply to be copied or passed through, multiplexers  202  select data bits from input B directly. As seen from  FIG. 2 , the result of the XOR operations on the four bits d 0  to d 3  and four code bits C 0  to C 3  produces a sequence of sixteen chips s i  as follows:
 
 s   i   =d   0 ( xor ) C   0  for 0 ≦i≦ 3
 
 s   i   =d   1 ( xor ) C   1  for 4 ≦i≦ 7
 
 s   i   =d   2 ( xor ) C   2  for 8 ≦i≦ 11
 
 s   i   =d   3 ( xor ) C   3  for 12 ≦i≦ 15
 
When input  1  of multiplexer  200  is selected (for an SF of 8, i.e. 8 chips per data bit), each of the two data bits d 0  and d 1  are exclusive-ored eight times with two different code bits C 0  and C 1 , resulting in the following sixteen chips:
 
 s   i   =d   0 ( xor ) C   0  for 0 ≦i≦ 7
 
 s   i   =d   1 ( xor ) C   1  for 8 ≦i≦ 15
 
When input 2 is of multiplexer  200  selected (for an SF of 16 or more, i.e., 16 or more chips per data bit), the single data bit d 0  is exclusive-ored sixteen times with the same code bit C 0 , producing the following sixteen chips:
 
 s   i   =d   0 ( xor ) C   0  for 0 ≦i≦ 15
 
The resulting sequence of chips s i  from the series of multiplexers  205  is then used for subsequent scrambling operations, also performed by CDMA unit  115  of  FIG. 1 . However, scrambling operations are performed in a different block than the spreading operations. Referring to  FIG. 1 , the results of scrambling are stored in registers  135 , which are then transferred back to the CDMA unit for subsequent processing for scrambling.
 
Channelization and Complex Scrambling Operations
 
   In the WCDMA channelization, the input data bits are mapped to a complex-valued chip stream obtained from the two real-valued chip streams:
 
 I ( t )= d   I ( t ) C   I ( t ) and
 
 Q ( t )= d   Q ( t ) C   Q ( t )
 
where d I  and d Q  are data bits, and C I (t) and C Q (t) are the channelization codes that assume values in the domain {+1,−1}. For WCDMA downlink, C I (t)is equal to C Q (t). The input complex chip stream is therefore:
 
 I ( t )+ jQ ( t )= s   I,n ( t )+ js   Q,n ( t )=[ d   I ( t ) C   I ( t )]+ j[d   Q ( t ) C   Q ( t )]  (3)
 
where I and Q represent the in-phase and quadrature components, respectively.
 
   Scrambling is done by multiplying the complex chip stream I(t)+jQ(t) by the complex scrambling code sequence S I (t)+jS Q (t), where S I (t) and S Q (t) are the components of the complex scrambling code and assume values in the domain {+1, −1}. The result is the scrambled complex chip sequence Y I (t)+jY Q (t) given in equation (4) below:
 
 Y   I ( t )+ jY   Q ( t )=[ I ( t )+ jQ ( t )]×[ S   I ( t )+jS Q ( t )]=[ I ( t ) S   I ( t )− Q ( t ) S   Q ( t )]+ j[I ( t ) S   Q ( t )+ Q ( t ) S   I ( t )]=[ d   I ( t ) C   I ( t ) S   I ( t )− d   Q ( t ) C   Q ( t ) S   Q ( t )]+ j[d   I ( t ) C   I ( t ) S   Q ( t )+ d   Q ( t ) C   Q ( t ) S   I ( t )]  (4)
 
     FIG. 3  shows the data path, with corresponding hardware elements, that implements the scrambling operation given in equation (4) within CDMA unit  105  according to one embodiment of the invention. In the 4-bit format, both d I (t) and d Q (t) are 4-bit signed numbers in 2&#39;s complement representation. Each input A and B receives a pair of values (d I (t), d Q (t)). In the 8-bit format, both d I (t) and d Q (t) are 8-bit 2&#39;s complement signed numbers. In this case, input A receives d I (t) and input B receives d Q (t). 
   The data path of  FIG. 3  includes blocks  300  labeled Neg, which compute the negative values of the input data. Neg blocks can be any circuit that receives an input and outputs the negative of the input, such as an inverter. In the case of 4-bit format, the four Neg blocks  300 - 1  to  300 - 4  calculate the negative value of the two input data pairs (d I (t), d Q (t)). In the case of 8-bit format, the two Neg blocks on the left  300 - 1  and  300 - 2  calculate the negative value of d I (t) and the two blocks on right  300 - 3  and  300 - 4  compute the negative value of d Q (t). Multiplexers  305  coupled to the output of Neg blocks  300  and to inputs A or B select either the input data or the output of a Neg block  300 . The input is selected based on the most significant bit of the binary code sequences stored in a register file  310 , which includes in-phase code registers (Ci and Si) and quadrature code registers (Cq and Sq). If the most significant bit of the in-phase and quadrature registers is 0, then multiplexers  305  select the input data. Since bit  0  is mapped to value +1, this corresponds to multiplying the input data by 1. If the most significant bit of the registers is 1, then multiplexers  305  select the output of the Neg block. Because bit  1  is mapped to value −1, the operation of the Neg block and the multiplexer is equivalent to multiplying the input data by −1. Processing after the outputs of multiplexers  305  will now be described for 4-bit and 8-bit complex scrambling. 
     FIG. 4  shows the data flow for 4-bit complex scrambling. Given two input data pairs (d I,1 ,d Q,1 ) and (d I,2 ,d Q,2 ), the following values are present for signals at A 1  to A 8  of the data path (at the outputs of multiplexers  305 ) indicated in FIG.  4 :
 A1=d I,1 C I S I,n   A2=d I,1 C I S Q,n   A3=d Q,1 C Q S I,n   A4=d Q,1 C Q S Q,n   A5=d I,2 C I S I,n+1   A6=d I,2 C I S Q,n+1   A7=d Q,2 C Q S I,n+1   A8=d Q,2 C Q S Q,n+1   
where S I,n  and S Q,n  are the nth bit of the code sequences S I  and S Q , respectively. As described above, the code bits from register file  310  act as control signals to the multiplexers  305 , such that those bits act to determine, in effect, whether the sign of the input data is reversed or remains unchanged.
 
   Signals at B 1  to B 4 , which are the output of subtractors  400  and adders  405 , are given as follows:
 
 B 1= A 1− A 4= d   I,1   C   I   S   I,n   −d   Q,1   C   Q   S   Q,n 
 
 B 2= A 2+ A 3= d   I,1   C   I   S   Q,n   +d   Q,1   C   Q   S   I,n 
 
 B 3= A 5− A 8= d   I,2   C   I   S   I,n+1   −d   Q,2   C   Q   S   Q,n+1 
 
 B 4= A 6+ A 7= d   I,1   C   I   S   Q,n+1   −d   Q,2   C   Q   S   I,n+1 
 
Output signals Y I (t) and Y Q (t) from 3-to-1 multiplexers  410  provide two pairs (Y I,1 ,Y Q,1 ) and (Y I,2 ,Y Q,2 ) as follows:
 
 Y   I,1 ( t )= B 1= d   I,1   C   I   S   I,n   −d   Q,1   C   Q   S   Q,n  or
 
 Y   I,2 ( t )= B 3= d   I,2   C   I   S   I,n+1   −d   Q,2   C   Q   S   Q,n+1 
 
 Y   Q,1 ( t )= B 2= d   I,1   C   I   S   Q,n   +d   Q,1   C   Q   S   I,n  or
 
 Y   Q,2 ( t )= B 4= d   I,2   C   I   S   Q,n+1   +d   Q,2   C   Q   S   I,n+1 
 
The output pairs (Y I,1 ,Y Q,1 ) and (Y I,2 ,Y Q,2 ), which have been scrambled, can then be used by other parts of the reconfigurable cell and transmitted to an intended receiver.
 
   When CDMA unit  105  is performing a 4-bit complex scrambling operation, only the B 1  or B 3  inputs for multiplexer  410 - 1  and the B 2  or B 4  inputs for multiplexer  410 - 2  are used. The third input, the output from subtractor  415  and adder  420 , is used when an 8-bit complex scrambling operation is performed, as will be discussed. 
     FIG. 5  shows the data flow in the case of 8-bit format complex scrambling. The following values are present for signals at points A 1  to A 8  of the data path indicated in FIG.  5 :
 A1A3=d I C I S I,n   A2A4=d I C I S Q,n   A5A7=d Q C Q S I,n   A6A8=d Q C Q S Q,n   
The notation AiAk represents a concatenation of two four bit signals A for an 8-bit representation for 8-bit scrambling operations. The signals bypass the arithmetic circuits (subtractors  400  and adders  405 ) and are placed onto buses  500  or other suitable signal carrying medium. These signals at points B 1  to B 4  are given as follows:
 B1=A1A3=d I C I S I,n   B2=A6A8=d Q C Q S Q,n   B3=A5A5=d Q C Q S I,n   B4=A2A4=d I C I S Q,n   
Signals at B 1  and B 2  are then input into a subtractor circuit  505 , while signals at points B 3  and B 4  are input to an adder circuit  510 . The output signals of subtractor  505  and the output of adder  510  are given at points C 1  and C 2 , respectively, as follows:
   C 1= B 1− B 2= d   I   C   I   S   I,n   −d   Q   C   Q   S   Q,n     C 2= B 3+ B 4= d   Q   C   Q   S   I,n   +d   I   C   I   S   Q,n   
Multiplexer  410 - 1  selects the output of subtractor  505  for the output signal Y I , while multiplexer  410 - 2  selects the output of adder  510  for the output signal Y Q . Outputs Y I (t) and Y Q (t) are given as follows:
   Y   I ( t )= d   I   C   I   S   I,n   −d   Q   C   Q   S   Q,n     Y   Q ( t )= d   I   C   I   S   Q,n   +d   Q   C   Q   S   I,n   
These channelized and scrambled data signals are then transmitted or further processed in other portions of CDMA unit  115 . Note that scrambling and correlation operations are performed in the same block, while the spreading operation is performed within a different block of CDMA unit  105 .
 
Correlation Operations
 
   Channelized and scrambled data signals are received by CDMA unit  105 . In order to recover the original information, the receiver-computes complex correlation functions between the received chip stream and locally-generated replicas of the same channelization and scrambling codes used by the transmitter. The discrete-time, complex domain correlation function between two code sequences:
 
σ 1 ( n )=σ I,1 ( n )+ jσ   Q,1 ( n ) and
 
σ 2 ( n −τ)=σ I,2 ( n −τ)+ jσ   Q,2 ( n −τ)
 
is given as follows:
 
 R   c (τ)=Σ p [σ I,1 ( n )+ jσ   Q,1 ( n )][σ I,2 ( n −τ)− jσ   Q,2 ( n −τ)]  (5)
 
where P is the period of the two sequences and τ is the phase shift between the two sequences. If the two code sequences are in phase (i.e., τ=0), code sequences σ 1 (n)=σ I,1 (n)+jσ Q,1 (n) and σ 2 (n)=σ I,2 (n)+jσ Q,2 (n) are orthogonal and normalized if they exhibit the following two properties:
 
Σ p [σ I,1 ( n )+ jσ   Q,1 ( n )][σ I,2 ( n )− jσ   Q,2 ( n )]=0, and  (6a)
 
Σ p [σ I,1 ( n )+ jσ   Q,1 ( n )][σ I,1 ( n )− jσ   Q,1 ( n )]=Σ p [σ I,2 ( n )+ jσ   Q,2 ( n )][σ I,2 ( n )− jσ   Q,2 ( n )]=1  (6b)
 
The transmitted signal Y I (t)+jY Q (t) is given by equation (4) above. This complex chip stream arrives at the receiver as signal R I (t)+jR Q (t) (the same as the transmitted signal Y I (t)+jY Q (t)), given as follows:
 
 R   I ( t )+ jR   Q ( t )=[ d   I ( t ) C   I ( t ) S   I ( t )− d   Q ( t ) C   Q ( t ) S   Q ( t )]+ j[d   I ( t ) C   I ( t ) S   Q ( t )+ d   Q ( t ) C   Q ( t ) S   I ( t )]  (7)
 
   To recover the data d I (t) according to one embodiment, the receiver computes the complex correlation function between the received chip stream and the complex code sequence C I (t)S I (t)−jC I (t)S Q (t). 
   The correlation for recovering d I (t) from the received scrambled signal is given as follows:
 
Σ[ R   I ( t )+ jR   Q ( t )]×[ C   I ( t ) S   I ( t )− jC   I ( t ) S   Q ( t )]=Σ[ R   I ( t ) C   I ( t ) S   I ( t )− jR   I ( t ) C   I ( t ) S   Q ( t )+ jR   Q ( t ) C   I ( t ) S   I ( t )+ R   Q ( t ) C   I ( t ) S   Q ( t )]=Σ[ R   I ( t ) C   I ( t ) S   I ( t )+ R   Q ( t ) C   I ( t ) S   Q ( t )]+ j[R   Q ( t ) C   I ( t ) S   I ( t )− R   I ( t ) C   I ( t ) S   Q ( t )]=Σ[ R   I ( t ) C   I ( t ) S   I ( t )+ ΣR   Q ( t ) C   I ( t ) S   Q ( t )+ j[ΣR   Q ( t ) C   I ( t ) S   I ( t )− ΣR   I ( t ) C   I ( t ) S   Q ( t )]  (8)
 
   Replacing R I (t) and R Q (t) from equation (7) in each of the terms of equation (8), the following set of equations are obtained:
 
Σ R   I ( t ) C   I ( t ) S   I ( t )=Σ d   I ( t ) C   I ( t ) S   I ( t ) C   I ( t ) S   I ( t )−Σ d   Q ( t ) C   Q ( t ) S   Q ( t ) C   I ( t ) S   I ( t )  (9a)
 
Σ R   Q ( t ) C   I ( t ) S   Q ( t )=Σ d   I ( t ) C   I ( t ) S   Q ( t ) C   I ( t ) S   Q ( t )+Σ d   Q ( t ) C   Q ( t ) S   I ( t ) C   I ( t ) S   Q ( t )  (9b)
 
Σ R   Q ( t ) C   I ( t ) S   I ( t )=Σ d   I ( t ) C   I ( t ) S   Q ( t ) C   I ( t ) S   I ( t )+Σ d   Q ( t ) C   Q ( t ) S   I ( t ) C   I ( t ) S   I ( t )  (9c)
 
Σ R   I ( t ) C   I ( t ) S   Q ( t )=Σ d   I ( t ) C   I ( t ) S   I ( t ) C   I ( t ) S   Q ( t )−Σ d   Q ( t ) C   Q ( t ) S   Q ( t ) C   I ( t ) S   Q ( t )  (9d)
 
   The components C I (t) and C Q (t) of the channelization code, as well as S I (t) and S Q (t) of the complex scrambling code, are orthogonal. Therefore, applying properties (6a) and (6b) to the set of equations above and noting that C I (t) is normalized (i.e., C I (t)×C I (t)=1), equations (9a) to (9d) reduce to the following:
 
Σ R   I ( t ) C   I ( t ) S   I ( t )= d   I ( t )  (10a)
 
Σ R   Q ( t ) C   I ( t ) S   Q ( t )= d   I ( t )  (10b)
 
Σ R   Q ( t ) C   I ( t ) S   I ( t )=0  (10c)
 
Σ R   I ( t ) C   I ( t ) S   Q ( t )=0  (10d)
 
Replacing equations (10a) to (10d) into equation (8) results in the following correlation:
 
Σ[ R   I ( t )+ jR   Q ( t )]×[ C   I ( t ) S   I ( t )− jC   I ( t ) S   Q ( t )]=2 d   I ( t )  (11)
 
where d I (t) is the original information data stream.
 
   To recover the data d Q (t) from the received signal, the receiver computes the complex correlation function between the received chip stream and the complex code sequence C Q (t)S I (t)−jC Q (t)S Q (t). Thus, similar to d I (t), the correlation is given as follows:
 
Σ[ R   I ( t )+ jR   Q ( t )]×[ C   Q ( t ) S   I ( t )− jC   Q ( t ) S   Q ( t )]=Σ[ R   I ( t ) C   Q ( t )S I ( t )− jR   I ( t ) C   Q ( t ) S   Q ( t )+ jR   Q ( t ) C   Q ( t )S I ( t )+ R   Q ( t ) C   Q ( t ) S   Q ( t )]=Σ[ R   I ( t ) C   Q ( t )S I ( t )+ R   Q ( t ) C   Q ( t ) S   Q ( t )]+ j[R   Q ( t ) C   Q ( t )S I ( t )− R   I ( t ) C   Q ( t ) S   Q ( t )]=Σ R   I ( t ) C   Q ( t )S I ( t )+ ΣR   Q ( t ) C   Q ( t ) S   Q ( t )+ j[ΣR   Q ( t ) C   Q ( t )S I ( t )− ΣR   I ( t ) C   Q ( t ) S   Q ( t )]  (12)
 
which reduces to the following:
 
Σ[ R   I ( t )+ jR   Q ( t )]×[ C   Q ( t ) S   I ( t )− jC   Q ( t ) S   Q ( t )]=2 d   Q ( t )  (13)
 
where d Q (t) is the original information data stream.  FIG. 6  shows the data path which implements the correlation operation as given by equation (8), according to one embodiment. The input is the received chip sequence R I (t)+jR Q (t). Neg blocks  600  calculate the negative of its associated input. Internal register file  310  store the replicas of the channelization and scrambling codes of the receiver. Eight 2-1 multiplexers  605  select either the input data or the output of a Neg block 600, depending on the most significant bit of the code sequences stored in the code registers. The output of multiplexers  605  are coupled to arithmetic circuits., such as adders  615  and subtractors  620 , via buses  610  or other suitable signal carrying medium. The output of adders  615  and subtractors  620 , along with the outputs of multiplexers  605 , are coupled to inputs of 2-1 multiplexers  630  via buses  625  or other suitable medium. The output of multiplexers  630  are input to adder/subtractor circuits  635 . The outputs of adder/subtractor circuit  635  are accumulated by adders  640  with a feedback signal from register blocks  645 . Register blocks  645  hold intermediate results and feed those results back to adders  640  to obtain the desired output from adders  640 . The output of register blocks  645  is then transmitted to multiplexers  410  (see  FIG. 4 ) for subsequent processing out of CDMA unit  105  (see  FIG. 1 ).
 
     FIG. 7  shows the data flow for the 4-bit correlation case. In the 4-bit format, R I (t) and R Q (t) are 4-bit 2&#39;s-complement signed numbers and inputs A and B receive the pairs (R I,1 , R Q,1 ) and (R I,2 , R Q,2 ), respectively. In the case of 4-bit format, the four Neg  600  blocks calculate the negative of the two (R I (t), R Q (t)) input data pairs. Signals at the output of multiplexers (at points A 1  to A 8  of the data path) are given below. In the following development, C n  and C n+1  can be either a C i  or a C q  code, depending on whether d I  or d Q , respectively, is being recovered.
 A1=R I,1 C n S I,n   A2=R I,1 C n S Q,n   A3=R Q,1 C n S I,n   A4=R Q,1 C n S Q,n   A5=R I,1 C n+1 S I,n+1   A6=R I,2 C n+1 S Q,n+1   A7=R Q,2 C n+1 S Q,n+1   A8=R Q,2 C n+1 S Q,n+1   
The signals at the output of adders  615  and subtractors  620  (at points B 1  to B 4 ) are as follows:
   B 1= A 1+ A 4= R   I,1   C   n   S   I,n   +R   Q,1   C   n   S   Q,n     B 2= A 3+ A 2= R   Q,1   C   n   S   I,n   −R   I,1   C   n   S   Q,n     B 3= A 5+ A 8= R   I,2   C   n+1   S   I,n+1   +R   Q,2   C   Q,n+1   S   Q,n+1     B 4= A 7+ A 6= R   Q,2   C   n+1   S   I,n+1   −R   I,1   C   n+1   S   Q,n+1   
For the 4-bit correlation, circuits  635  add two inputs provided by multiplexers  630 . The output signals, at points C 1  and C 2 , are given as follows:
   C 1= B 1+ B   3=(R   I,1   C   n   S   I,n   +R   Q,1   C   n   S   Q,n )+( R   I,2   C   n+1   S   I,n+1   +R   Q,2   C   n+1   S   Q,n+1 )   C 2= B 2+ B   4=(R   Q,1   C   n   S   I,n   −R   I,1   C   n   S   Q,n )+( R   Q,2   C   n+1   S   I,n+1   −R   I,2   C   n+1   S   Q,n+1 ) 
The output of adders  640  at points D 1  and D 2  are then given as:
   D 1= Z   1 ( n )= C   1 +Σ( R   I,1   C   k   S   I,k   +R   Q,1   C   k   S   Q,k )=( R   I,1 C n   S   I,n   +R   Q,1   C   n   S   Q,n )+( R   I,2   C   n+1   S   I,n+1   +R   Q,2   C   n+1   S   Q,n+1 )+Σ( R   I,1   C   k   S   I,k   +R   Q,1   C   k   S   Q,k   )   k&lt;n   D 2= Z   2 ( n )= C   2 +Σ( R   Q,1   C   k   S   I,k   −R   I,1   C   k   S   Q,k )=( R   Q,1 C n   S   I,n   −R   I,1   C   n   S   Q,n )+( R   Q,2   C   n   S   I,n+1   −R   I,2   C   n   S   Q,n+1 )+Σ( R   Q,1   C   k   S   I,k   −R   I,1   C   k   S   Q,k   )   k&lt;n 
where D 1  and D 2  are transmitted to multiplexers  410 .
 
     FIG. 8  shows the data flow for the 8-bit correlation case. In the 8-bit format, both R I (t) and R Q (t) are 8-bit 2&#39;s-complement signed numbers. Inputs A and B receive R I (t) and R Q (t) data, respectively. For the 8-bit format, the two Neg blocks  600 - 1  and  600 - 2  on the left calculate the negative of R I (t) whereas the two Neg blocks  600 - 3  and  600 - 4  on right compute the negative of R Q (t). The output of multiplexers  605  (at points A 1  to A 8  of the data path) are given as follows:
 A1A3=R I C n S I,n   A2A4=R I C n S Q,n   A5A7=R Q C n S I,n   A6A8=R Q C n S Q,n   
where C n  can be either C i  or C q , depending on whether d i  or d q ; respectively, is being recovered. Again, the notation AiAk is a concatenation of the two 4-bit signals Ai and Ak. In the 8-bit processing, signals from multiplexers  605  bypass adders  615  and subtractors  620  and are then selected by multiplexers  630  for input to circuits  635  for appropriate adding or subtracting. The signal at point B 1  (sum) and the signal at point B 2  (difference) are given as follows:
   B 1= A 1 A 3+ A 6 A 8= R   I   C   n   S   I,n   +R   Q   C   n   S   Q,n     B 2= A 5 A 7+ A 2 A 4= R   Q   C   n   S   I,n   −R   I   C   n   S   Q,n   
The output of circuits  635  is then summed with a feedback signal, resulting in the following signals at points C 1  and C 2 :
   C 1= Z   1 ( n )= B   1+Σ(   R   i   C   k   S   I,k   +R   Q   C   k   S   Q,k )=( R   I   C   n   S   I,n   +R   Q   C   n   S   Q,n )+Σ( R   I   C   k   S   I,k   +R   Q   C   k   S   Q,k)   k&lt;n   C 2= Z   2 ( n )= B   2+Σ(   R   Q   C   k   S   I,k   −R   Q   C   k   S   Q,k )=( R   Q   C   n   S   I,n   −R   I   C   n   S   Q,n )+Σ( R   Q   C   k   S   I,k   −R   I   C   k   S   Q,k)   k&lt;n 
where signals at C 1  and C 2  are transmitted to multiplexers  410 .
 
   Note that the implementations shown in  FIGS. 3  through 8 are all performed with a single design. The various implementations are shown with simplified connections for ease of illustration. 
   Although the invention has been described with reference to particular embodiments, the description is only an example of the invention&#39;s application and should not be taken as a limitation. For example, the data paths and description focused on IS-95 and WCDMA; however, other systems may also be used, such as cdma2000. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.