Abstract:
The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the semiconductor substrate and being comprised of a stacked structure of a first conductive layer, an insulation film and a second conductive layer; and a bonding pad which is disposed on the front surface side to the capacitor and to which a bonding wire being connected, wherein the bonding pad are arranged overlapping the capacitor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     The disclosure of Japanese Patent Application No. 2004-145819 filed on May 17, 2004 including specification, drawings and claims is incorporated herein by reference in its entirety  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a power semiconductor device in which a control circuit controls a power switching element, and more particularly, to a power semiconductor device having a capacitor.  
         [0004]     2. Description of the Related Art  
         [0005]      FIGS. 8A and 8B  are a schematic drawing of a conventional power semiconductor device generally denoted at  600 .  FIG. 8A  is a top view of bonding pad portions, and  FIG. 8B  is a cross sectional view taken along the direction VIII-VIII shown in  FIG. 8A . The power semiconductor device  600  includes an insulated gate bipolar transistor (IGBT) and a control circuit (not shown) which controls the same.  
         [0006]     As shown in  FIGS. 8A and 8B , the power semiconductor device  600  includes a die pad  51  of alumina or the like. A semiconductor chip  53  is fixed on the die pad  51  by a bonding material  52  such as a solder. The semiconductor chip  53  includes the control circuit, the IGBT which is a power switching element, and the like. A bonding pad  54  of aluminum or the like is disposed on the top surface of the semiconductor chip  53  and connected to a bonding wire  55  of aluminum or the like.  
         [0007]      FIG. 9  is a cross sectional view expanding the bonding pad  54  and a surrounding area. The semiconductor chip  53  shown in  FIG. 8B  includes a silicon substrate  56 , and on the silicon substrate  56 , the bonding pad  54  is disposed via a silicon oxide film  57  and the bonding wire  55  is connected on this (JP, 2000-058765, A).  
       SUMMARY OF THE INVENTION  
       [0008]     However, in the event that the power semiconductor device  600  includes a large-capacity capacitor, the power semiconductor device  600  becomes large-sized partly because the capacity is in proportion to the area size of the capacitor. This pushes up a manufacturing cost and makes it difficult to reduce the size of the power semiconductor device  600 .  
         [0009]     Noting this, the inventor found through dedicated research and investigation that when a capacitor was fabricated using metal wires and insulation layers belonging to a power semiconductor device, it was possible to arrange a bonding pad and the capacitor over each other and reduce the size of the power semiconductor device, thus completing the present invention.  
         [0010]     An object of the present invention is to reduce the size of a power semiconductor device in which a control circuit controls a power switching element.  
         [0011]     The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the semiconductor substrate and being comprised of a stacked structure of a first conductive layer, an insulation film and a second conductive layer; and a bonding pad which is disposed on the front surface side to the capacitor and to which a bonding wire being connected, wherein the bonding pad are arranged overlapping the capacitor.  
         [0012]     According to the present invention, a bonding pad and a capacitor are arranged over each other, and therefore, it is possible to reduce the size of a power semiconductor device which comprises a large-capacity capacitor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is a circuit diagram of the power semiconductor device according to the embodiment 1 of the present invention;  
         [0014]      FIG. 2  is a cross sectional view of the power semiconductor device according to the embodiment 1 of the present invention;  
         [0015]      FIG. 3  is a cross sectional view of the power semiconductor device according to the embodiment 2 of the present invention;  
         [0016]      FIG. 4  is a cross sectional view of the power semiconductor device according to the embodiment 3 of the present invention;  
         [0017]      FIG. 5  is a circuit diagram of the power semiconductor device according to the embodiment 3 of the present invention;  
         [0018]      FIG. 6  is a cross sectional view of the power semiconductor device according to the embodiment 4 of the present invention;  
         [0019]      FIG. 7  is a cross sectional view of the power semiconductor device according to the embodiment 5 of the present invention;  
         [0020]      FIGS. 8A and 8B  are a schematic drawing of the conventional power semiconductor device; and  
         [0021]      FIG. 9  is a cross sectional view of the conventional power semiconductor device. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     Embodiment 1  
       [0022]      FIG. 1  is a circuit diagram of a power semiconductor device B 2  according to the embodiment 1 of the present invention. The power semiconductor device B 2  includes an insulated gate bipolar transistor (IGBT) T 1  which is a power switching element. A control circuit B 1  is connected to a control input terminal P 1  of the IGBT T 1 . The IGBT T 1  further includes an output terminal P 2  and a GND terminal P 3 . There is a capacitor C 1  between the control circuit B 1  and the GND terminal P 3 .  
         [0023]      FIG. 2  is a cross sectional view of the power semiconductor device according to the embodiment 1 generally denoted at  100 , as viewed in the same direction as the direction VIII-VIII of  FIG. 8A . The power semiconductor device  100  includes a silicon substrate  1 . On the silicon substrate  1 , an insulation film  2  of silicon oxide for instance, a polycrystalline silicon layer  3  and an insulation film  4  of silicon oxide for instance are stacked in this order. A metal layer  5  of aluminum for example is disposed on the insulation film  4 .  
         [0024]     The metal layer  5  also serves as a bonding pad, and a bonding wire  6  of aluminum or the like is connected to the metal layer  5 . The bonding wire  6  is used for connection with an external signal, a fix potential (GND) or the like.  
         [0025]     As described above, the power semiconductor device  100  includes the IGBT and the control circuit (not shown), the polycrystalline silicon layer  3  is formed at the same time that a wiring layer of the control circuit is formed, and the metal layer  5  is formed at the same time that a metal wiring layer used as the fix potential (GND potential) is formed.  
         [0026]     In the power semiconductor device  100 , the insulation film  4  and the polycrystalline silicon layer  3  and the metal layer  5  which are on the both sides of the insulation film  4  form a capacitor. The metal layer  5  of this capacitor serves also as a bonding pad for connection with the bonding wire  6 . As the bonding pad and the capacitor are thus arranged over each other, the size of the power semiconductor device  100  is reduced.  
         [0027]     With the polycrystalline silicon layer  3  connected to a gate of the IGBT, it is possible to increase the gate capacitance of the IGBT and enhance the electrostatic surge resistance. A structure according to an embodiment 3 described later also attains an IGBT having a large electrostatic surge resistance  
       Embodiment 2  
       [0028]      FIG. 3  is a cross sectional view of a power semiconductor device according to the embodiment 2 generally denoted at  200 , as viewed in the same direction as the direction VIII-VIII of  FIG. 8A . In  FIG. 3 , the same reference symbols as those used in  FIG. 2  denote the same or corresponding portions.  
         [0029]     The power semiconductor device  200  includes the silicon substrate  1 . An impurity implantation layer  7  to which a high-concentration impurity has been implanted is formed on the silicon substrate  1 . The impurity implantation layer  7  is used usually as the fix potential (GND). An insulation film  8  of silicon oxide for instance which also serves as a gate oxide film of the IGBT is formed on the impurity implantation layer  7 . The polycrystalline silicon layer  3 , the insulation film  4  and the metal layer  5  are disposed on the insulation film  8 . The metal layer  5  serves also as a bonding pad, and the bonding wire  6  is connected to the metal layer  5 .  
         [0030]     In the power semiconductor device  200 , the insulation film  8  and the impurity implantation layer  7  and the polycrystalline silicon layer  3  which are on the both sides of the insulation film  8  form a capacitor. Since the bonding pad and the capacitor are arranged over each other in this structure, the size of the power semiconductor device  200  is reduced.  
         [0031]     Further, as described above, since the insulation film  8  is formed at the same time that the gate oxide film of the IGBT is formed, the film thickness becomes as thin as a few hundreds angstroms and it therefore is possible to increase the capacitance of the capacitor per unit area.  
         [0032]     In addition, since the insulation film  4  is formed on the capacitor, it is possible to prevent mechanical destruction of the capacitor while the bonding wire  6  is connected to the metal layer  5 .  
       Embodiment 3  
       [0033]      FIG. 4  is a cross sectional view of a power semiconductor device according to the embodiment 3 generally denoted at  300 , as viewed in the same direction as the direction VIII-VIII of  FIG. 8A . In  FIG. 4 , the same reference symbols as those used in  FIG. 2  denote the same or corresponding portions.  
         [0034]     As in the power semiconductor device  100 , in the power semiconductor device  300 , the insulation film  2  and the polycrystalline silicon layer  3  are formed on the silicon substrate  1 , and further, an insulation film  9  of silicon oxide, a metal layer  10  of aluminum or the like and an insulation film  11  of silicon oxide or the like are formed on this. The metal layer  5  which serves also as a bonding pad is disposed on the insulation film  11 , and the bonding wire  6  is connected on the metal layer  5 . The polycrystalline silicon layer  3  and the metal layer  10  are used also as wiring layers of the control circuit or the like.  
         [0035]     In the power semiconductor device  300  having this structure, the insulation film  9  and the polycrystalline silicon layer  3  and the metal layer  10  which are on the both sides of the insulation film  9  form a capacitor, while the insulation film  11  and the metal layer  10  and the metal layer  5  which are on the both sides of the insulation film  11  also form a capacitor.  
         [0036]      FIG. 5  is a circuit diagram of the power semiconductor device  300 . In addition to the circuits of the power semiconductor device  100  shown in  FIG. 1 , a capacitor C 2  is connected between a gate terminal and an emitter terminal of the IGBT T 1 . In this circuitry, the capacitor C 2  has a function of increasing the electrostatic surge resistance.  
         [0037]     Since the bonding pad and the capacitors are arranged over each other in this structure, the size of the power semiconductor device  300  is reduced.  
         [0038]     Parallel connection increases the capacitance of the capacitor per unit area approximately twice, particularly because of the two stacked capacitors in the power semiconductor device  300 .  
       Embodiment 4  
       [0039]      FIG. 6  is a cross sectional view of a power semiconductor device according to the embodiment 4 generally denoted at  400 , as viewed in the same direction as the direction VIII-VIII of  FIG. 8A . In  FIG. 6 , the same reference symbols as those used in  FIG. 2  denote the same or corresponding portions.  
         [0040]     As in the power semiconductor device  200 , in the power semiconductor device  400 , the impurity implantation layer  7  and the insulation film  8  are formed on the silicon substrate  1 , and the polycrystalline silicon layer  3  is formed further on this. The insulation film  8  serves also as the gate oxide film of the IGBT, and the insulation film  8  and the impurity implantation layer  7  and the polycrystalline silicon layer  3  which are on the both sides of the insulation film  8  form a capacitor.  
         [0041]     The insulation film  9  of silicon oxide or the like, the metal layer  10  of aluminum or the like and the insulation film  11  of silicon oxide or the like are formed on the polycrystalline silicon layer  3 . The metal layer  5  which serves also as a bonding pad is disposed on the insulation film  11 , and the bonding wire  6  is connected on the metal layer  5 . In the power semiconductor device  400 , the metal layer  10  is connected to the fix potential (GND).  
         [0042]     Since the bonding pad and the capacitor are arranged over each other in this structure, the size of the power semiconductor device  400  is reduced.  
         [0043]     Further, the metal layer  10  disposed above the capacitor is connected to the fix potential (GND), it is possible to shield the capacitor against a change of a potential occurring at the surface of the power semiconductor device  400  (i.e., above the metal layer  10 ) and stabilize the capacitance of the capacitor.  
       Embodiment 5  
       [0044]      FIG. 7  is a cross sectional view of a power semiconductor device according to the embodiment 5 generally denoted at  500 , as viewed in the same direction as the direction VIII-VIII of  FIG. 8A . In  FIG. 7 , the same reference symbols as those used in  FIG. 2  denote the same or corresponding portions.  
         [0045]     In the power semiconductor device  500 , the impurity implantation layer  7  and the insulation film  8  are formed on the silicon substrate  1 . The insulation film  8  serves also as the gate oxide film of the IGBT. A polycrystalline silicon layer  12  shaped like stripes extending in a direction perpendicular to the plane of  FIG. 7  is formed on the insulation film  8 . The insulation film  9  of silicon oxide or the like, the metal layer  10  of aluminum or the like and the insulation film  11  of silicon oxide or the like are formed on the polycrystalline silicon layer  12 . Further, the impurity implantation layer  7 , the polycrystalline silicon layer  12  and the metal layer  10  are connected by an impurity implantation layer  13  to which a high-concentration impurity has been implanted.  
         [0046]     The metal layer  5  which serves also as a bonding pad is formed on the insulation film  11 , and the bonding wire  6  is connected on the metal layer  5 . The insulation film  8  and the polycrystalline silicon layer  12  and the impurity implantation layer  7  which are on the both sides of the insulation film  8  form a capacitor.  
         [0047]     Since the bonding pad and the capacitor are arranged over each other in this structure, the size of the power semiconductor device  500  is reduced.  
         [0048]     Further, since the impurity implantation layer  7 , the polycrystalline silicon layer  12  and the metal layer  10  are connected by the impurity implantation layer  13 , the capacitor is shielded against the back surface of the power semiconductor device  500  which seats a collector electrode (not shown). Because of this, even when a voltage of a few hundreds volts is applied upon the collector electrode, it is possible to stabilize the capacitance of the capacitor.  
         [0049]     While the foregoing has described the embodiments 1 through 5 in relation to an example that a silicon substrate is used, the embodiments 1 through 5 are applicable to where other semiconductor substrate such as a substrate of GaAs, InP or the like is used.  
         [0050]     Further, other than an IGBT, a semiconductor element such as a power FET may be used as the power switching element.