Abstract:
A memory cell array includes a memory cell comprising a ferroelectric capacitor and a transistor arranged therein. A plate line applies a drive voltage to one end of the ferroelectric capacitor. A bit line reads data stored in the memory cell from the other end of the ferroelectric capacitor. A sense amplifier circuit detects and amplifies a signal read to the bit line from the ferroelectric capacitor. A bit line voltage control circuit performs control of changing a voltage of the bit line to which the signal is read, thereby pulling up a potential difference between the plate line and the bit line, prior to operation of the sense amplifier circuit for data read. The bit line voltage control circuit varies a range of variation of the voltage of the bit line depending on ambient temperature.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2008-297838, filed on Nov. 21, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor memory device. More specifically, it relates to a ferroelectric memory that stores data in a non-volatile manner using a memory cell including a ferroelectric capacitor and a transistor. 
         [0004]    2. Description of the Related Art 
         [0005]    A ferroelectric memory (FeRAM) is a semiconductor memory device using hysteresis properties of a ferroelectric capacitor. FeRAM can store data in a nonvolatile manner based on two different polarization strengths of a ferroelectric material. In general, a memory cell in a conventional ferroelectric memory adopts a similar architecture to DRAM. That is, a paraelectric capacitor in DRAM is replaced with a ferroelectric capacitor, and the ferroelectric capacitor and a transistor are connected in series to form a memory cell (JP2001-250376A). A plurality of such ferroelectric capacitors and transistors are arranged to form a memory cell array. The ferroelectric memory includes a 2 transistor-2 cell scheme (2T/2C scheme) in which data is read from two memory cells, and a 1 transistor-1 cell scheme (1T/1C scheme) in which data is read from one memory cell. 
         [0006]    The 1T/1C system selects a word line of the cell to be read, and turns on the select transistor, thereby connecting the memory cell to a bit line. A plate voltage is then applied to a plate line connected to the memory cell, and a voltage is applied across the ferroelectric capacitor included in the memory cell. The charge from the ferroelectric capacitor is read to the bit line. The bit line forms a bit-line pair with another bit line (complementary bit line). The complementary bit line is applied with a reference potential from a reference potential generating circuit. A sense amplifier amplifies the difference between the bit-line pair potentials. The difference in the charge read to the bit-line pair thus represents an amount of signal. 
         [0007]    The 1T/1C scheme is advantageous for high integration, but because the amount of signal is half that of the 2T/2C scheme, increasing the amount of signal is a problem. Known as a way of increasing the amount of signal in the 1T/1C scheme is, for example, a technique as disclosed in JP2001-319472A. 
         [0008]    In the technique of this JP2001-319472A, after the voltage is applied across the ferroelectric capacitor and the signal corresponding to data is read to the bit line, and prior to operation of a sense amplifier circuit, control is performed to reduce (step down) the voltage of the bit line to which the signal is read. The step down operation causes an absolute value of the amount of the signal to decrease in both data “1” and data “0”. However, as a result of the latter decrement being larger than that of the former, the difference in the amount of signal can be increased. The technique of this JP2001-319472A has some effectiveness as a way of increasing the difference in the amount of signal. 
       SUMMARY OF THE INVENTION 
       [0009]    In accordance with an aspect of the present invention, a semiconductor memory device includes: a memory cell array including a memory cell comprising a ferroelectric capacitor and a transistor arranged therein; a word line configured to select the memory cell; a plate line configured to apply a drive voltage to one end of the ferroelectric capacitor; a bit line configured to read data stored in the memory cell from the other end of the ferroelectric capacitor; a sense amplifier circuit configured to detect and amplify a signal read to the bit line from the ferroelectric capacitor; and a bit line voltage control circuit configured to perform control of changing a voltage of the bit line to which the signal is read, thereby pulling up a potential difference between the plate line and the bit line, prior to operation of the sense amplifier circuit for data read, the bit line voltage control circuit being configured to vary a range of variation of the voltage of the bit line depending on ambient temperature. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a simple circuit diagram showing an example of a circuit of a common ferroelectric memory. 
           [0011]      FIG. 2  is an operation wave pattern chart showing an operation of the ferroelectric memory of  FIG. 1 . 
           [0012]      FIG. 3  shows a voltage application curve (at a time of low temperature) of a ferroelectric capacitor included in a memory cell, when a read operation of the ferroelectric memory is performed. 
           [0013]      FIG. 4  shows a voltage application curve (at a time of normal temperature) of a ferroelectric capacitor included in a memory cell, when a read operation of the ferroelectric memory is performed. 
           [0014]      FIG. 5  shows a voltage application curve (at a time of high temperature) of a ferroelectric capacitor included in a memory cell, when a read operation of the ferroelectric memory is performed. 
           [0015]      FIG. 6  shows a variation in an amount of signal in accordance with variation in ambient temperature for each of “0” data and “1” data. 
           [0016]      FIG. 7  shows a circuit configuration of a ferroelectric memory in accordance with a first embodiment of the present invention. 
           [0017]      FIG. 8  shows an operation wave pattern of the ferroelectric memory in the first embodiment. 
           [0018]      FIG. 9  is a graph explaining an optimum value of an overdrive voltage Vod. 
           [0019]      FIG. 10  is a graph explaining an optimum value of an overdrive voltage Vod. 
           [0020]      FIG. 11  is a graph explaining an optimum value of an overdrive voltage Vod. 
           [0021]      FIG. 12  is a graph explaining an optimum value of an overdrive voltage Vod. 
           [0022]      FIG. 13  is a graph explaining an optimum value of an overdrive voltage Vod. 
           [0023]      FIG. 14  is a circuit diagram showing a specific configuration example of a voltage generating circuit  4 . 
           [0024]      FIG. 15  is a graph showing output voltage characteristics of the voltage generating circuit  4  shown in  FIG. 14 . 
           [0025]      FIG. 16  shows a circuit configuration of a ferroelectric memory in accordance with a second embodiment of the present invention. 
           [0026]      FIG. 17  shows an operation wave pattern of the ferroelectric memory in the second embodiment. 
           [0027]      FIG. 18  shows a circuit configuration of a ferroelectric memory in accordance with a third embodiment of the present invention. 
           [0028]      FIG. 19  shows an operation wave pattern of the ferroelectric memory in the third embodiment. 
           [0029]      FIG. 20  shows a circuit configuration of a ferroelectric memory in accordance with a fourth embodiment of the present invention. 
           [0030]      FIG. 21  shows an operation wave pattern of the ferroelectric memory in the fourth embodiment. 
           [0031]      FIG. 22  shows a circuit configuration of a ferroelectric memory in accordance with a fifth embodiment of the present invention. 
           [0032]      FIG. 23  shows an operation wave pattern of the ferroelectric memory in the fifth embodiment. 
           [0033]      FIG. 24  shows a circuit configuration of a ferroelectric memory in accordance with a sixth embodiment of the present invention. 
           [0034]      FIG. 25  shows an operation wave pattern of the ferroelectric memory in the sixth embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0035]    Embodiments of the present invention will now be described in detail with reference to the drawings. 
         [0036]    [Basic Concept] 
         [0037]    Before explanation of specific embodiments, a basic concept of the present invention is described. 
         [0038]    First, an example of a circuit of a common ferroelectric memory is simply described with reference to  FIGS. 1 and 2 . A memory cell in the ferroelectric memory shown in this  FIG. 1  is configured to connect one NMOS transistor and one ferroelectric capacitor in series, similarly to DRAM. This memory cell structure is referred to as a 1T/1C structure. It is also possible for one memory cell to be comprised by a pair of memory cells connected to each of bit lines of a bit-line pair, and this structure is referred to as a 2T/2C structure. 
         [0039]      FIG. 2  shows an operation wave pattern of the ferroelectric memory shown in  FIG. 1 . During standby, bit lines BL and /BL are pre-charged to a ground potential Vss, and plate lines PL 0  and PL 1  are also set to the ground potential Vss. During active state, the bit lines BL and /BL are first set to a floating state, a selected word line WL is applied with a voltage Vpp, and a selected plate line PL 0  is raised from the ground potential Vss to an array voltage Vaa. Here, the array voltage Vaa is an internal common power supply used commonly within a memory cell array, and is normally an external power supply voltage Vdd or a stepped-down voltage thereof. 
         [0040]    At this time, a voltage is applied to the ferroelectric capacitor of the selected cell with a bit line capacitance Cb as a load capacitance, and a signal charge is read to the bit line. A potential read to the bit line differs between cell data “1” and “0”. When data is “1”, polarization inversion occurs to produce a large potential in the bit line; when data is “0”, there is no occurrence of polarization inversion, and the bit line shows a small potential change. 
         [0041]    In the case of the 1T/1C structure, a reference potential is set midway between a bit line potential of “0” and “1” data, and a sense is performed of data with a sense amplifier. That is, after data read to the bit line, “1” data and “0” data are amplified to the array voltage Vaa and the ground voltage Vss, respectively, by setting a sense amplifier activation signal SEN to “H”. 
         [0042]    “1”-data read is a destructive read causing polarization inversion. In a cell of “1” data, after a read data sense, the bit line is at a voltage of Vaa, and a voltage across the ferroelectric capacitor is approximately 0. Thereafter, the plate line is returned to Vss. This allows a reversed-polarity voltage Vaa that is opposite to the voltage during read is applied to the ferroelectric capacitor, and the destructed data “1” is written again. 
         [0043]    On the other hand, in a cell of “0” data, because the bit line is Vss, the voltage Vaa is applied to the ferroelectric capacitor from the plate line side. When the plate line is returned to Vss, the voltage across the ferroelectric capacitor becomes zero, and it returns to an original residual polarization state. That is, the destructive read does not occur. Then, the word line WL 0  is lowered, and the bit lines BL and /BL are returned to the voltage Vss, thereby returning to standby. 
         [0044]      FIGS. 3-5  show a voltage application curve of a ferroelectric capacitor included in a memory cell, when a read operation of the ferroelectric memory is performed, at times of low temperature, normal temperature and high temperature ambient temperature, respectively. The horizontal axis of  FIGS. 3-5  shows a magnitude of a voltage applied to the ferroelectric capacitor. The voltage is expressed as a positive value when a voltage of a plate line side terminal is higher than that of a bit line side terminal, whereas expressed as a negative value when a voltage of a bit line side terminal is higher than that of the plate line side terminal.  FIGS. 3-5  each illustrates a load straight line of bit line capacitance Cb on the hysteresis curve of the ferroelectric capacitor. A read voltage to the bit line is obtained as a voltage at an intersection of the hysteresis curve and the load straight line for each of “0” and “1” data. 
         [0045]      FIG. 6  shows a variation in an amount of signal with ambient temperature for each of “0” data and “1” data. As is apparent from  FIG. 6 , the amount of signal changes with temperature in both the case where the memory cell holds “0” data and the case where it holds “1” data. 
         [0046]    Thus, in the present invention, a voltage is applied between both ends of the ferroelectric capacitor to transmit a signal corresponding to the stored data to the bit line. Then, prior to operation of the sense amplifier circuit, a voltage of the bit line where the signal is read is pulled down. In this case, the amount of the pull-down is varied in accordance with the ambient temperature. Specific embodiments are described below. 
       First Embodiment 
       [0047]    Next, a ferroelectric memory in accordance with a first embodiment of the present invention is described.  FIG. 7  shows a circuit configuration of the ferroelectric memory in accordance with the first embodiment of the present invention. 
         [0048]    A memory cell array  1  of this embodiment employs the 2T/2C structure. One data is stored by two memory cells MC 1  and MC 2  connected to bit lines BL and /BL comprising a bit-line pair, respectively. For example, when “1” data is stored in the memory cell MC 1 , “0” data which is the complementary data thereto is stored in the memory cell MC 2 . A memory cell MC is configured having a ferroelectric capacitor F and an NMOS transistor Q connected in series. 
         [0049]    One end of ferroelectric capacitors F 1  and F 2  is connected to a plate line PL 1 , and the other end is connected to the bit lines /BL and BL via NMOS transistors Q 1  and Q 2 , respectively. The NMOS transistors Q 1  and Q 2  have a gate thereof connected to a common word line WL 1  and are turned on simultaneously. The bit-line pair BL and /BL is connected to a sense amplifier circuit  2 . In addition, the bit-line pair BL and /BL is provided with a bit line voltage control circuit  3  to control the bit line voltage during data read. 
         [0050]    The bit line voltage control circuit  3  has capacitors C 1  and C 2  for coupling, and NMOS transistors Q 11  and Q 21 . The capacitors C 1  and C 2  are coupled to selected bit lines during read, and pull down a potential of the selected bit lines. The NMOS transistors Q 11  and Q 21  selectively connect one ends N 1  and N 2  of the capacitors C 1  and C 2 , respectively, to the bit line pair /BL and BL. Other ends of the capacitors C 1  and C 2  are connected to a voltage generating circuit  4 , and are applied with a certain voltage from control signal lines V 1  and V 2 . A voltage of these control signal lines V 1  and V 2  is given a certain temperature characteristic. The NMOS transistors Q 11  and Q 21  are controlled by a control signal line Vs 2 . 
         [0051]    Nodes N 1  and N 2  of the capacitors C 1  and C 2  are further provided with reset NMOS transistors Q 12  and Q 22  to reset a potential of the nodes N 1  and N 2  to the ground potential Vss. The reset NMOS transistors Q 12  and Q 22  are controlled by a control signal line Vs 1 . Note that the control signal lines Vs 1  and Vs 2  have a voltage controlled by a row decoder circuit not shown, for example. 
         [0052]      FIG. 8  shows an operation wave pattern of the ferroelectric memory in this embodiment. 
         [0053]    This operation wave pattern is for the case where a word line WL 1  and the plate line PL 1  connected to the memory cell MC 1  and the memory cell MC 2  are selected to execute a data read and re-write. Note that, here, an example is shown when the bit line /BL is set to “H”. When the bit line BL is set to “H”, the same operation is performed. 
         [0054]    During standby, the bit-line pair /BL and BL, the word line WL 1  and the plate line PL 1  are all set to the ground potential Vss. In addition, voltages of the control signal lines V 1  and V 2  are both set to “H” (=Vaa). Moreover, a voltage of the control signal line Vs 1  is set to “H”, and a voltage of the control signal line Vs 2  is set to “L” (=Vss). The capacitors C 1  and C 2  are thereby charged with a charge of Vaa·C. 
         [0055]    Next, at time t 1 , the word line WL 1  is set to “H” and then, at time t 2 , the plate line PL 1  is set to “H”. The voltage (a, b) depending on the stored data of the memory cells MC 1  and MC 2  thereby appears in the bit-line pair /BL and BL. 
         [0056]    Subsequently, at time t 3 , the voltage of the control signal line Vs 1  is lowered from “H” to “L”, and, following this, at time t 4 , the voltage of the control signal line Vs 2  is raised from “L” to “H”. The nodes N 1  and N 2  of the capacitors C 1  and C 2  are thereby connected to the bit-line pair /BL and BL. 
         [0057]    In addition, at time t 5 , the voltage of the control signal lines V 1  and V 2  is pulled down from “H” by an amount of a certain overdrive voltage Vod (overdrive operation). The voltage of the nodes N 1  and N 2  thereby becomes −Vod by capacitance coupling. Because these nodes N 1  and N 2  are connected to the bit-line pair /BL and BL, the voltage of the bit-line pair /BL and BL is pulled down as shown by “c” and “d”. The voltage applied to the ferroelectric capacitor in the selected memory cell by this overdrive operation being carried out is increased in comparison with before (a difference between voltage “c” and “d” is greater than a difference between “a” and “b”), and an accumulated residual polarization can thus be read effectively. Then, at time t 6 , the signal Vs 2  is set to “L”, thereby isolating the voltage generating circuit  4  and the bit-line pair /BL and BL, and, when an activation signal SAE for activating the sense amplifier circuit  2  is raised from “L” to “H”, the voltage of the bit-line pair /BL and BL changes to either of “H” or “L”. 
         [0058]    As shown in  FIGS. 9-11 , the magnitude of the overdrive voltage Vod is given a temperature characteristic by the voltage generating circuit  4 . That is, because an optimum value of the overdrive voltage Vod changes with temperature, the voltage generating circuit  4  is configured to set the overdrive voltage to the optimum value matched to the temperature. 
         [0059]    Application of the overdrive voltage Vod causes the amount of signal of both a “0” cell and a “1” cell to decrease. As shown in  FIG. 12 , the voltage applied to the ferroelectric capacitor of memory cells becomes greatest when an amount of read signal from “0” cells becomes 0 V, and, thus, a value of the overdrive voltage Vod in this case becomes the optimum value. Note that, when the amount of read signal from “0” cells becomes a negative value, there is a risk that an unanticipated reverse current flows in the memory cell causing damage to the circuit. Thus, the overdrive voltage Vod should be set to the greatest value such that the amount of read signal from “0” cells becomes 0V, but does not become a negative value. That is, the overdrive voltage Vod should be set such that the bit line of the bit line pair showing a lower voltage becomes 0 V. Thus, as shown in  FIG. 13 , the overdrive voltage Vod is given a temperature characteristic such that it increases with rising temperature. 
         [0060]    A specific configuration example of the voltage generating circuit  4  is shown in  FIG. 14 . This voltage generating circuit  4  has the following current paths. The first current path comprises resistors  41  (resistance R 1 ) and  42  (resistance R 2 ) and a diode  43  connected in series between a node N 0  and a ground terminal GND. The second current path comprises a resistor  44  (resistance R 1 ) and a diode  45  connected in series between the node N 0  and the ground terminal GND. The third current path comprises resistors  48  (resistance R 3 ) and  49  (resistance R 4 ) connected in series between the node N 0  and the ground terminal GND. Note that a connection node N 3  of the resistors  48  and  49  is treated as an output terminal of an output voltage. 
         [0061]    A connection node N 1  of the resistors  41  and  42  of the first current path and a connection node N 2  of the resistor  44  and the diode  45  of the second current path are connected to input terminals of a differential amplification circuit  46 . An output terminal of the differential amplification circuit  46  is connected to a gate of an NMOS transistor  47 . The NMOS transistor  47  has a drain supplied with the voltage Vaa and a source connected to the node N 0 . In such a voltage generating circuit, a temperature characteristic of the output voltage as shown in  FIG. 15  can be obtained by adjusting the resistances R 1 -R 4  of the resistors  41 ,  42 ,  44 ,  48 , and  49 . A gradient of the output voltage characteristic depends on the ratio of the resistances R 1  and R 2 . 
       Second Embodiment 
       [0062]    Next, a ferroelectric memory in accordance with a second embodiment of the present invention is described.  FIG. 16  shows a circuit configuration of the ferroelectric memory in accordance with the second embodiment of the present invention. Note that in the second embodiment, identical symbols are assigned to elements similar to those in the ferroelectric memory of the first embodiment ( FIG. 7 ) and a detailed description thereof is hereafter omitted. 
         [0063]    A memory cell array  1  of this embodiment employs the 1T/1C structure. One data is stored in one memory cell MC connected to bit lines BL and /BL comprising a bit-line pair. The memory cell array  1  is provided with a reference voltage supply circuit  5  for supplying a complementary bit line with a reference voltage for comparison with a signal read from the memory cell MC. The reference voltage supply circuit  5  comprises NMOS transistors Q 31  and Q 32  connected in series between the bit-line pair BL and /BL, and, in addition, comprises a reference voltage generating circuit  51  providing the reference voltage to a connection node of the NMOS transistors Q 31  and Q 32 . Selectively switching signals R 1  and R 2  to “H” allows the NMOS transistors Q 31  and Q 32  to be turned on alternately, and the reference voltage is thereby supplied to the bit line to which the signal charge of the memory cell is read and to the twin complementary bit lines. 
         [0064]      FIG. 17  shows an operation wave pattern of the ferroelectric memory in this embodiment. This operation wave pattern shows the case where a word line WL 1  and a plate line PL 1  connected to a memory cell MC 1  are selected to execute a data read and re-write. 
         [0065]    During standby, the bit-line pair /BL and BL, the word lines WL 1  and WL 2 , and the plate line PL 1  are all set to the ground potential Vss. 
         [0066]    In addition, voltages of control signal lines V 1  and V 2  are both set to “H” (=Vaa). Moreover, a voltage of a control signal line Vs 1  is set to “H”, and a voltage of a control signal line Vs 2  is set to “L” (=Vss). Capacitors C 1  and C 2  are thereby charged with a charge of Vaa·C. 
         [0067]    Next, at time t 1 , the word line WL 1  connected to the memory cell MC 1  to be selected is set to “H” and then, at time t 2 , the plate line PL 1  is set to “H” and, in addition, the signal R 2  is set to “H”. A voltage “a” depending on the stored data of the memory cell MC 1  thereby appears in the bit line /BL. At the same time, a voltage “b” supplied from the reference voltage supply circuit  5  appears in the bit line BL. 
         [0068]    Subsequently, at time t 3 , the voltage of the control signal line Vs 1  is lowered from “H” to “L”, and, following this, at time t 4 , the voltage of the control signal line Vs 2  is raised from “L” to “H”. Nodes N 1  and N 2  of the capacitors C 1  and C 2  are thereby connected to the bit-line pair /BL and BL. 
         [0069]    In addition, at time t 5 , the voltage of the control signal line V 1  is pulled down from “H” by an amount of a certain overdrive voltage Vod (overdrive operation). Note that since the overdrive operation is not required in the bit line BL applied with the reference voltage, the control signal line V 2  is held at “H”. The voltage of the node N 1  thereby becomes −Vod. Because this node N 1  is connected to the bit line /BL of the bit-line pair, the voltage of the bit line /BL of the bit-line pair is pulled down as shown by c. That is, an overdrive operation similar to that of the first embodiment is executed and an accumulated residual polarization in the ferroelectric capacitor of memory cells can be read effectively. 
         [0070]    Then, at time t 6 , the signal Vs 2  is set to “L”, thereby isolating the voltage generating circuit  4  and the bit-line pair /BL and BL, and, when an activation signal SAE for activating the sense amplifier circuit  2  is raised from “L” to “H”, the voltage of the bit-line pair /BL and BL changes to either of “H” or “L”. 
       Third Embodiment 
       [0071]    Next, a ferroelectric memory in accordance with a third embodiment of the present invention is described.  FIG. 18  shows a circuit configuration of the ferroelectric memory in accordance with the third embodiment of the present invention. Note that in the third embodiment, identical symbols are assigned to elements similar to those in the ferroelectric memory of the first and second embodiments ( FIGS. 7 and 16 ) and a detailed description thereof is hereafter omitted. The ferroelectric memory of this embodiment is directed to a so-called TC parallel unit series-connected ferroelectric memory configured as an arrangement of memory cell blocks MB each formed of a plurality of memory cells MC connected in series, each memory cell MC constituted by a ferroelectric capacitor F and a transistor Q connected in parallel. Moreover, this TC parallel unit series-connected ferroelectric memory adopts the 2T/2C scheme. 
         [0072]    In this embodiment, memory cell blocks MB 1  and MB 2  share word lines WL 0 -WL 3 , and complementary data are stored in memory cells MC connected to the same word line WL (for example, “0” is stored in a memory cell MC 24  when “1” is stored in a memory cell MC 14 ); the 2T/2C scheme is adopted. 
         [0073]    Plate lines PL 1  and PL 2  for applying the plate line voltage are respectively connected to memory cells MC 11  and MC 21  lying at one end of the memory cell blocks MB 1  and MB 2 . 
         [0074]    Moreover, the other end of the memory cell blocks MB 1  and MB 2  is connected to the bit-line pair /BL and BL via block select transistors BS 1  and BS 2 , respectively. The block select transistors BS 1  and BS 2  are on/off controlled by block select signals BS 1  and BS 2 . 
         [0075]    In these memory cell blocks MB 1  and MB 2 , all word lines WLi (i=0-3) are set to “H” during standby, and all ferroelectric capacitors Fi are thereby prevented from being applied with a voltage. However, when, for example, a word line WL 0  only is set to “L” for a data read, a voltage is applied across the ferroelectric capacitors F 14  and F 24 , and a voltage based on the cell data stored in the ferroelectric capacitors F 14  and F 24  appears in the bit-line pair /BL and BL, thereby executing the data read. 
         [0076]      FIG. 19  shows an operation wave pattern of the ferroelectric memory in this embodiment. This operation wave pattern shows the case where the word line WL 0  and the plate lines PL 1  and PL 2  connected to the memory cell MC 14  and the memory cell MC 24  are selected to execute a data read and re-write. 
         [0077]    During standby, the bit-line pair /BL and BL, and the plate lines PL 1  and PL 2  are all set to the ground potential Vss. The word lines WL 0 -WL 3  are all set to “H”. In addition, the block select signals BS 1  and BS 2  are set to “H”. Furthermore, voltages of control signal lines V 1  and V 2  are both set to “H” (=Vaa). Moreover, a voltage of a control signal line Vs 1  is set to “H”, and a voltage of a control signal line Vs 2  is set to “L” (=Vss). A capacitor C 1  is thereby charged with a charge of Vaa·C. 
         [0078]    Then, at time t 1 , the word line WL 0  only is switched from “H” to “L”, the word line WL 0  being the word line connected to the selected memory cells MC 14  and MC 24 , and, following this, at time t 2 , the voltage of the plate lines PL 1  and PL 2  is switched to “H”. A voltage is thereby applied across the ferroelectric capacitors F 14  and F 24 . Subsequent operation is substantially similar to that of the first embodiment and a description thereof is omitted. 
       Fourth Embodiment 
       [0079]    Next, a ferroelectric memory in accordance with a fourth embodiment of the present invention is described.  FIG. 20  shows a circuit configuration of the ferroelectric memory in accordance with the fourth embodiment of the present invention. Note that in the fourth embodiment, identical symbols are assigned to elements similar to those in the ferroelectric memory of the aforementioned embodiments and a detailed description thereof is hereafter omitted. 
         [0080]    The ferroelectric memory of this embodiment is similar to the third embodiment in that it is directed to the so-called TC parallel unit series-connected type ferroelectric memory. But it differs from the third embodiment in adopting the 1T/1C scheme. That is, in memory blocks MB 1  and MB 2 , either one of memory cells MC is selected by block transistors BS 1  and BS 2  being turned on selectively, and the signal is thereby read to a bit line of the bit-line pair /BL and BL. Moreover, a reference voltage supply circuit  5  similar to that of the second embodiment is provided to execute the 1T/1C scheme. 
         [0081]      FIG. 21  shows an operation wave pattern of the ferroelectric memory in this fourth embodiment. 
         [0082]    This operation wave pattern shows the case where a word line WL 0  and a plate line PL 1  connected to a memory cell MC 14  in the memory cell block MB 1  are selected to execute a data read and re-write. 
         [0083]    During standby, the bit-line pair /BL and BL, and the plate lines PL 1  and PL 2  are all set to the ground potential Vss. The word lines WL 0 -WL 3  are all set to “H”. In addition, block select signals BS 1  and BS 2  are set to “L”. Furthermore, voltages of control signal lines V 1  and V 2  are both set to “H” (=Vaa). Moreover, a voltage of a control signal line Vs 1  is set to “H”, and a voltage of a control signal line Vs 2  is set to “L” (=Vss). A capacitor C 1  is thereby charged with a charge of Vaa·C. 
         [0084]    Then, at time t 1 , the word line WL 0  only is switched from “H” to “L”, the word line WL 0  being the word line connected to the selected memory cell MC 14 , and, following this, at time t 2 , the voltage of the plate line PL 1  is switched to “H”. A voltage is thereby applied to the ferroelectric capacitor F 14 . Subsequent operation is substantially similar to that of the second embodiment and a description thereof is omitted. 
       Fifth Embodiment 
       [0085]    Next, a ferroelectric memory in accordance with a fifth embodiment of the present invention is described.  FIG. 22  shows a circuit configuration of the ferroelectric memory in accordance with the fifth embodiment of the present invention. Note that in the fifth embodiment, identical symbols are assigned to elements similar to those in the ferroelectric memory of the aforementioned embodiments and a detailed description thereof is hereafter omitted. 
         [0086]    The ferroelectric memory of this embodiment has a DRAM-like structure and adopts the 2T/2C scheme, similarly to the first embodiment. However, a direction of the voltage applied to a selected memory cell MC during a read operation in this embodiment differs from that of the aforementioned embodiments. 
         [0087]    That is, prior to execution of the read operation, the bit-line pair /BL and BL are pre-charged to voltage Vaa by a pre-charge circuit  6 , while the potential of a plate line PL is constantly fixed at 0 V. The pre-charge circuit  6  comprises NMOS transistors Q 41  and Q 42  connected in series between the bit-line pair /BL and BL, and has a power source voltage Vaa applied to a connection node thereof. In addition, a signal P is commonly inputted to a gate of both the transistors Q 41  and Q 42 . 
         [0088]    This embodiment further differs from the previous embodiments in that an overdrive voltage Vod applied by an overdrive operation is a positive value, not a negative value. This is due to the fact that the direction of the voltage applied to the memory cell MC differs from that of the aforementioned embodiments, as previously mentioned. 
         [0089]      FIG. 23  shows an operation wave pattern of the ferroelectric memory in this embodiment. 
         [0090]    This operation wave pattern is for the case where a word line WL 1  and a plate line PL 1  connected to a memory cell MC 1  and a memory cell MC 2  are selected to execute a data read and re-write. 
         [0091]    During standby, the bit-line pair /BL and BL, and the word line WL 1  are all set to the ground potential Vss. As previously mentioned, the potential of the plate line PL 1  is constantly fixed at the ground potential Vss. 
         [0092]    In addition, voltages of control signal lines V 1  and V 2  are both set to “L” (=Vss). Moreover, a voltage of a control signal line Vs 1  is set to “H”, and a voltage of a control signal line Vs 2  is set to “L” (=Vss). A charge in capacitors C 1  and C 2  is thereby discharged. 
         [0093]    Next, at time t 1 , the signal P of the pre-charge circuit  6  is raised to “H” for a certain period of time, whereby the bit-line pair /BL and BL are charged to Vaa. Subsequently, at time t 3 , the word line WL 1  is set to “H”. The voltage (a, b) depending on the stored data of the memory cells MC 1  and MC 2  thereby appears in the bit-line pair /BL and BL. 
         [0094]    Then, at time t 4 , the voltage of the control signal line Vs 1  is lowered from “H” to “L”, and, following this, at time t 5 , the voltage of the control signal line Vs 2  is raised from “L” to “H”. Nodes N 1  and N 2  of the capacitors C 1  and C 2  are thereby connected to the bit-line pair /BL and BL. 
         [0095]    In addition, at time t 6 , the voltage of the control signal lines V 1  and V 2  is increased from “L” by an amount of a certain overdrive voltage Vod (overdrive operation). The voltage of the nodes N 1  and N 2  thereby becomes +Vod. Because these nodes N 1  and N 2  are connected to the bit-line pair /BL and BL, the voltage of the bit-line pair /BL and BL is pulled up as shown by “c” and “d”. Thus, the voltage applied to the ferroelectric capacitor can be increased, and an accumulated residual polarization can be read effectively, similarly to the aforementioned embodiments. 
         [0096]    Then, at time t 7 , the signal Vs 2  is set to “L”, thereby isolating the voltage generating circuit  4  and the bit-line pair /BL and BL, and, when an activation signal SAE for activating the sense amplifier circuit  2  is raised from “L” to “H”, the voltage of the bit-line pair /BL and BL changes to either of “H” or “L”. 
       Sixth Embodiment 
       [0097]    Next, a ferroelectric memory in accordance with a sixth embodiment of the present invention is described.  FIG. 24  shows a circuit configuration of the ferroelectric memory in accordance with the sixth embodiment of the present invention. Note that in the sixth embodiment, identical symbols are assigned to elements similar to those in the ferroelectric memory of the aforementioned embodiments and a detailed description thereof is hereafter omitted. 
         [0098]    The ferroelectric memory of this embodiment has a DRAM-like structure, similarly to the fifth embodiment, but adopts the 1T/1C system. The ferroelectric memory of this embodiment is therefore provided with a reference voltage supply circuit  5 , as shown in  FIG. 24 . Also similarly to the fifth embodiment, a direction of the voltage applied to a selected memory cell MC during a read operation differs from that of the first embodiment, the bit-line pair /BL and BL side being applied with a positive voltage, and a plate line PL 1  being constantly fixed at the ground potential Vss (0 V). 
         [0099]      FIG. 25  shows an operation wave pattern of the ferroelectric memory in this embodiment. This operation wave pattern is for the case where a word line WL 1  and a plate line PL connected to a memory cell MC 1  are selected to execute a data read and re-write. 
         [0100]    During standby, the bit-line pair /BL and BL, and the word line WL 1  are all set to the ground potential Vss. The potential of a plate line PL 1  is constantly fixed at the ground potential Vss. 
         [0101]    In addition, voltages of control signal lines V 1  and V 2  are both set to “L” (=Vss). Moreover, a voltage of a control signal line Vs 1  is set to “H”, and a voltage of a control signal line Vs 2  is set to “L” (=Vss). A charge in capacitors C 1  is thereby discharged. 
         [0102]    Next, at time t 1 , a signal P 1  of a pre-charge circuit  6  is raised to “H” for a certain period of time, whereby the bit line /BL is charged to Vaa. The bit line BL is left “L”, since it is later charged by the reference voltage supply circuit  5  and therefore does not require charging at this time. 
         [0103]    Subsequently, at time t 3 , the word line WL 1  is set to “H”, and, in addition, a signal R 2  is set from “L” to “H”. Thereby, a voltage depending on the stored data of the memory cell MC 1  appears in the bit line /BL, and a reference voltage appears in the bit line BL. 
         [0104]    Then, at time t 4 , the voltage of the control signal line Vs 1  is lowered from “H” to “L”, and, following this, at time t 5 , the voltage of the control signal line Vs 2  is raised from “L” to “H”. A node N 1  of a capacitor C 1  is thereby connected to the bit-line pair /BL and BL. 
         [0105]    In addition, at time t 6 , the voltage of the control signal line V 1  is increased from “L” by an amount of a certain overdrive voltage Vod (overdrive operation). The voltage of the node N 1  thereby becomes +Vod. Because this node N 1  is connected to the bit line /BL, the voltage of the bit line /BL is increased. Thus, the voltage applied to the ferroelectric capacitor can be increased, and an accumulated residual polarization can be read effectively, similarly to the aforementioned embodiments. 
         [0106]    Then, at time t 7 , the signal Vs 2  is set to “L”, thereby isolating the voltage generating circuit  4  and the bit-line pair /BL and BL, and, when an activation signal SAE for activating the sense amplifier circuit  2  is raised from “L” to “H”, the voltage of the bit-line pair /BL and BL changes to either of “H” or “L”. 
         [0107]    This concludes description of embodiments of the semiconductor memory device in accordance with the present invention, but it should be noted that the present invention is not limited to the above-described embodiments, and that various alterations, additions, and so on, are possible within a range not departing from the scope and spirit of the invention.