Abstract:
A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a method and apparatus for testing and redundancy allocation for defective array rows and columns of one or more memory arrays of an integrated circuit. 
       BACKGROUND OF THE INVENTION 
       [0002]    The need for increasing performance is driving the use of smaller and local memory macros that are embedded in the various circuit functions of custom integrated circuits. However there is a large amount of support circuitry associated with each memory macro in order to test the memory macros. The support circuits consume significant silicon area thus increasing the cost of the integrated circuits. Therefore, there is a need to reduce the area impact of test circuits of embedded memory macros without significant reduction in test coverage or increase in test time. 
       SUMMARY OF THE INVENTION 
       [0003]    A first aspect of the present invention is a method of implementing redundancy programming in an integrated circuit chip having one or more memory macros and an automatic built-in self-test circuit, the method comprising: (a) sending a test pattern to the memory macro from the automatic built-in self-test circuit; (b) sending an expected test pattern based on the test pattern to a fail register and writing the test pattern into a memory array of a memory macro of the one or more memory macros; (c) in a standard mode, reading out a resultant pattern from the memory array and sending the resultant pattern from the memory array to the fail register, the fail register comparing the resultant pattern with the expected pattern and generating a current fail record based on the comparison in the fail register if the resultant pattern does not match the expected pattern, the current fail record comprising a type of fail field, a wordline address field and a data field as wide as the number of columns in the memory array and indicating which bits of the test pattern failed; (d) storing the current fail record in the fail register if another fail record in the fail register does not have a same wordline address as the current fail record and writing the type of fail field of the current fail record as a wordline fail; (e) if all bits in the data field of the current fail record match all bits of a data field of any other fail record in the fail register and the number of failing bits is less than a preset number of bits but at least equal to one, then changing the type of fail field of the current fail record to a bitline fail; (f) repeating steps (a) through (e) until the fail register is full or no more test patterns are to be sent to the memory array; (g) sending a fail record from the fail register to a repair register of the memory macro; (h) generating and storing in the repair register a wordline repair record based on the fail record and sending a wordline repair command to the memory array if the fail type field of the fail record indicates wordline fail, or generating and storing a bitline repair record and sending a bitline repair command to the memory array if the fail type field indicates a bitline fail, the bitline repair record based on the data field of the fail record; 
         [0004]    (i) replacing defective wordlines and bitlines of the memory array of the memory macro of the one or more memory macros with redundant wordlines and bitlines of the memory array based on the wordline and bitline repair commands; (j) repeating steps (a) through (i) until no more test patterns are to be sent to the memory array. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0006]      FIG. 1  is a schematic circuit diagram of an integrated circuit chip according to embodiments of the present invention; and 
           [0007]      FIG. 2  is a flow diagram of the operation of the circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0008]      FIG. 1  is a schematic circuit diagram of an integrated circuit chip according to embodiments of the present invention. In  FIG. 1 , an integrated circuit chip  100  includes two exemplary memory macros  105 A and  105 B. Memory macro  105 A includes a memory cell array  110 A comprising memory cells arranged in rows and columns, a repair register  115 A (which includes support and logic circuits) and a MUX  125 A. The rows and columns of memory cell array  110 A include normal rows and columns and spare (or redundant) rows and columns. Generally rows are addressable as wordlines and columns as bitlines. A write bus  135 A is connected to the I/O circuits of memory cell array  110 A, to repair register  115 A and to a first data input of MUX  125 A. The I/O circuits of memory cell array  110 A and a second data input of MUX  125 A are connected by a read bus  140 A. Write bus carries both wordline and bitline addresses and column or bitline data, however only the column data is delivered to MUX  125 A (the branch of bus  135 A connected to MUX  125 A is a sub-bus). Read bus  140 A carries only column or bitline data. Repair register  115 A is connected to memory cell array  110 A by a bus  145 A to allow repair commands generated in the repair register to be transferred and implemented in memory cell array  110 A. Repair register  115 A is connected to the switch input of MUX  125 A and can send a “HIT” signal  150 A which switches the output of MUX  125 A from read bus  140 A to write bus  135 A. This effectively redirects data on write bus  135 A back to the test circuits as described infra. 
         [0009]    Integrated circuit  100  also includes an optional second memory macro  105 B, which is similar to memory macro  105 A. However, memory cell array  110 B may be the same array size (number of memory cells) or a different array size from memory cell array  110 A. Memory cell array  110 B may be the same array shape (number of rows and columns) or a different array shape as memory cell array  110 A. Memory cell array  110 B may be of the same type of memory or a different type of memory as memory cell array  110 A. Examples of types of memory include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM). 
         [0010]    Integrated circuit chip  100  may include an optional error correction circuit (ECC)  155 . When ECC  155  is included, the ECC unit includes a pass through function that is invoked in both operating modes (discussed infra) of the invention. Integrated circuit chip  100  also includes a fail register  160 , an automatic built-in self-test (ABIST) macro  165 , a test/repair MUX  170 . a read MUX  175  and a write MUX  180 . ECC  155  is connected to fail register  160  via a bus  185 . ABIST  165  is connected to fail register  160  by a bus  190  and to a first data input of MUX  170  by a bus  195 . Fail register  160  is connected to a second data input of MUX  170  by a bus  200 . The data output of MUX  170  is connected to ECC  155  by a bus  205 . Buses  185  and  205  are buses in the logic path connecting the memory macros to other circuits in integrated circuit  100  as opposed to being dedicated test buses. However test buses may be used. Buses  135 A and  135 B are connected to respective data outputs of MUX  180  and buses  210 A and  210 B connect respective data outputs of MUXes  125 A and  125 B to data inputs of MUX  175 . The data output of MUX  175  is connected to ECC  155  by a bus  210  and the data input of MUX  180  is connected to ECC  155  by a bus  215 . The switch inputs of MUXes  175  and  180  are connected to ECC  155  by a bus  220 . The pass through function of ECC  155  passes records/data on bus  205  to bus  215  unaltered and passes records/data on bus  210  to bus  185  unaltered. 
         [0011]    While two memory macros are illustrated in  FIG. 1 , there may be one or more memory macros and for each additional memory macro MUX  175  requires another data input and MUX  180  another data output. 
         [0012]    Test data is a pattern of bits that is written to the columns (bitlines) of memory arrays during test and resultant data is a pattern of bits read out of columns (bitlines) of the memory arrays after a period of test time. An expected pattern is a pattern that will be read out of a memory array after writing a test pattern if the memory is working correctly. A repair record includes a memory macro ID field (if there are more than one memory macros), a type of fail field (wordline or bitline), a wordline address field and a data field as wide as the number of columns (bitlines, not counting redundant bitlines) in the memory array of the memory macro and indicating which bits failed. The data field indicates which bits are failing. This record organization allows all fails to first be assumed to be wordline fails and then later changed to bitline fails if necessary after a comparison of the data fields of subsequent fail of other wordlines. Details of this process are described in U.S. Pat. No. 5,859,804 issued to Hedberg et al. on Jan. 12, 1999 and hereby incorporated by reference. 
         [0013]    ABIST  165  generates a test pattern of bits that is sent to MUX  170  and presented to ECC  155 . ABIST also sends an expected pattern of bits to fail register  160 . ECC  155  sends a resultant pattern of bits to fail register  160 . Fail register  160  generates fail record that is sent to MUX  170  and presented to ECC  155 . Fail register generates the fail record by comparing resultant patterns to expected patterns. Details of this process are described in U.S. Pat. No. 5,805,789 issued to Huott et al. on Sep. 8, 1998 and hereby incorporated by reference. In one example, the number of records that can be stored in fail register  160  is half or less than the number of records that can be stored in repair register  115 A or repair register  115 B. Therefore an enhanced mode is provided, which is useful when the fail register  160  is significantly smaller than the repair registers  115 A and  115 B and the fail register must be cycled two or more times to complete testing of a memory cell array. In enhanced mode repair registers  115 A and  115 B are enabled to compare the destination wordline address of each test pattern sent to the repair register with the wordline addresses of fail records having a type of fail field=wordline previously stored in the repair register. If a wordline is already marked for replacement repair registers  115 A and  115 B send a hit signal to respective MUXes  125 A and  125 B to redirect the entire test pattern to MUX  175 . In enhanced mode, the expected pattern must be the same as the test pattern. Since comparing a test pattern with itself will result in a passing test, fail register  160  will not generate another (redundant) repair record. In a similar fashion repair registers  115 A and  115 B are enabled to, in the absence of a wordline hit and the presence of the fail field=bitline, allow any bitline repairs to generate a hit signal to respective MUXes  125 A and  125 B in order to redirect the portion of the test pattern corresponding to the marked bitlines to MUX  175 . Since comparing a test pattern with itself will result in a passing test, fail register  160  will not generate another (redundant) repair record. Enhanced mode can be disabled or the circuits physically not present (in some or all of the memory macros) in an alternative embodiment of the present invention. For example, if the memory macro is small, then the repair register may be smaller than the fail register. 
         [0014]      FIG. 2  is a flow diagram of the operation of the circuit of  FIG. 1 . The method starts in step  290 . In step  290 , if the testing is initializing then the method proceeds directly to step  300  otherwise it is determined if further testing is to be performed. If further testing is to be performed then the method proceeds to step  300 , otherwise the method proceeds to step  345  (via connector “A”). In step  300 , ABIST sends a test pattern to a selected wordline of the memory macro. In step  305 , ABIST sends an expected pattern to the fail register (in enhanced mode the expected pattern must be the same as the test pattern). In step  310 , ABIST sends a read command to the memory macro. In step  312 , which mode the test is being performed in is determined. If the test is in standard mode the method proceeds to step  315 , otherwise to step  385 . In step  315 , the memory macro sends a resultant pattern to the fail register. In step  320 , the fail register compares the received and expected patterns and generates a data field of current fail record. In step  325 , if a fail is detected (resultant and expected patterns don&#39;t match), the method proceeds to step  330  (unless all patterns have been used and testing is complete, in which case testing of the memory macro is complete) otherwise it loops back to step  300  for another test pattern. 
         [0015]    In step  330 , it is determined if another fail record for the selected wordline already exists in the fail register. If another fail record for the current wordline does not exist the method proceeds to step  335  otherwise it loops back to step  300  for another test pattern (unless all patterns have been used and testing is complete, in which case testing of the memory macro is complete). In step  335 , it is determined if the fail type should be changed from wordline to bitline. If the data field of the current fail record matches the data field of any other fail record in the fail register and the number of failing bits in the current fail record is less than a preset number of bits but at least equal to one, then the fail type field is changed from a wordline fail to a bitline fail and the fail record entered in the fail register. The present number of bits may range from 2 to the number of redundant bitlines available in the memory cell array. Generally, the present number will be small. In one example the present number is 1, 2 or 3. In one example, the present number is equal to about 10% of the number of redundant bitlines available. The method then proceeds to step  340 . 
         [0016]    In step  340  it is determined if the fail register is full. If the fail register is not full and an existing wordline fail was not changed to a bitline fail then a wordline fail record is created and the method loops back to step  300 . If the fail register is full the method proceeds to step  345 . In step  345  the fail register instructs ABIST to pause testing and send the fail records to the repair register and the method proceeds to step  350 . 
         [0017]    In step  350 , the first/next fail record is received from the fail register and it is determined if the first (or next) fail record fail type field indicates a wordline or a bitline fail. If a wordline fail is indicated the method proceeds to step  360  otherwise to step  365 . In step  360  the repair register ignores the data field of the record, stores the fail record and issues a repair wordline command to the repair register. The method then proceeds to step  370 . In step  370  it is determined if another fail record is to be received from the fail register. If so, then the method loops back to step  350 , otherwise the method proceeds to step  375 . 
         [0018]    In step  365  the repair register ignores the wordline field of the record, stores repair record and issues a repair bitline command to the redundancy register. The method then proceeds to step  370 . In step  370  it is determined if another fail record is to be received from the fail register. If so, then the method loops back to step  350 , otherwise the method proceeds to step  375 . 
         [0019]    In step  375 , it is determined if more testing of the memory macro is to be performed. If so, then the method loops back to step  300 , otherwise the method terminates or proceeds to testing another memory macro. 
         [0020]    Steps  385  through  400  are performed only in enhanced mode. In step  385 , up to three comparisons between the current fail record from fail register  160  (see  FIG. 1 ) and the repair records of repair register  115 A/ 115 B are performed against three different sets of criteria in the following sequence. First, if the wordline address of the current test pattern matches any wordline address of any wordline repair record in said repair register then in step  390  the current test pattern to is returned to fail register  160  in step  320 . In enhanced mode, the expected pattern and said current test pattern are the same pattern. Second, if the wordline address of the current test pattern does not match any wordline address of any wordline repair record in repair register  115 A/ 115 B and if a bitline repair record exists in the repair register then in step  395 , a modified resultant pattern is generated in repair register  115 A/ 115 B and returned to fail register  160  in step  320 . The modified resultant pattern is generated by replacing the values of bits in positions of the resultant pattern corresponding to failing bit positions marked in the bitline repair record with the value of bits in the corresponding bit positions of the current test pattern. Third, if the wordline address of the current test pattern does not match any wordline address of any wordline repair record in repair register  115 A/ 115 B and if no bitline repair record exists in the repair register then in step  400 , the resultant test pattern is returned to fail register  160  in step  320 . 
         [0021]    Steps  300  through  400  will repeat for each memory macro to be tested. 
         [0022]    Thus, the embodiments of the present invention provide a method and apparatus to reduce the area impact of test circuits of embedded memory macros without significant reduction in test coverage or increase in test time. 
         [0023]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.