Abstract:
A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-069067 filed on Mar. 13, 2002, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention generally relates to semiconductor integrated circuits functioning as level-shifter circuits, and particularly relates to an semiconductor integrated circuit functioning as a level-shifter circuit that operates stably at high speed even with a low voltage input.  
           [0004]    2. Description of the Related Art  
           [0005]    Level-shifter circuits are used for the purpose of converting a signal having a predetermined voltage to a signal having a higher voltage level. A typical level-shifter circuit is disclosed in Japanese Patent Laid-open Application No. 6- 37624 , for example.  
           [0006]    [0006]FIG. 1 is a circuit diagram showing a typical construction of a level-shifter circuit.  
           [0007]    The level-shifter circuit of FIG. 1 includes PMOS transistors  11  and  12 , NMOS transistors  13  and  14 , and an inverter  15 . An incoming signal IN is applied to the gate of the NMOS transistor  14 , and is also inverted by the inverter  15  to be applied to the gate of the NMOS transistor  13 . The incoming signal IN being HIGH (V L ) makes the NMOS transistors  13  and  14  nonconductive and conductive, respectively, resulting in the PMOS transistors  11  and  12  being conductive and nonconductive, respectively. Accordingly, an output signal OUT is set to 0 V. If the incoming signal IN is LOW (0 V), the NMOS transistors  13  and  14  are conductive and nonconductive, respectively, resulting in the PMOS transistors  11  and  12  being nonconductive and conductive, respectively. In this case, therefore, the output signal OUT is set at V H . In this manner, the incoming potential level ranging between 0 and V L  is shifted to a range between 0 and V H .  
           [0008]    The transistors  11  through  14  that control the output signal OUT are those designed for high-potential operations so as to properly operate at a potential range between 0 and V H . In general, high-speed signal transition requires the operating range of an incoming signal IN to be set at a increasingly lower potential level as the technology improves. In such a case, since the transistors  13  and  14  are designed for high-potential operations corresponding to the potential range boosted by the level shift, the potential level V L  that is relatively low may not be able to turn on or off the transistors at sufficient speed. In some cases, the transistors may fail to be sufficiently conductive.  
           [0009]    Accordingly, there is a need for a level-shifter circuit that can stably operate at high speed even when the incoming signal is set at a potential level significantly lower that the operating potential range of the circuit-component transistors.  
         SUMMARY OF THE INVENTION  
         [0010]    It is a general object of the present invention to provide a level-shifter circuit that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.  
           [0011]    Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a level-shifter circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.  
           [0012]    To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor integrated circuit, including first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.  
           [0013]    In the semiconductor integrated circuit functioning as a level-shifter circuit as described above, the substrate-bias potential of the first field-effect transistor is controlled by the incoming signal. The substrate-bias potential is set at an elevated level to lower the threshold when the first field-effect transistor is turned on. The lowering of the threshold makes it possible to achieve a high-speed switching-on operation of the first field-effect transistor even when the signal level of the incoming signal is relatively low. This insures that the transition of the output signal is stable and high speed.  
           [0014]    Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 is a circuit diagram showing a typical construction of a level-shifter circuit;  
         [0016]    [0016]FIG. 2 is a circuit diagram showing a first embodiment of a level-shifter circuit according to the present invention;  
         [0017]    [0017]FIG. 3 is an example of a substrate-bias potential Vbs;  
         [0018]    [0018]FIG. 4 is a chart showing an output signal waveform of the level-shifter circuit according to the first embodiment;  
         [0019]    [0019]FIG. 5 is a circuit diagram showing a second embodiment of the level-shifter circuit of the present invention;  
         [0020]    [0020]FIG. 6 is a chart showing an output signal waveform of the level-shifter circuit of the second embodiment;  
         [0021]    [0021]FIG. 7 is a circuit diagram showing a third embodiment of the level-shifter circuit of the present invention;  
         [0022]    [0022]FIG. 8 is a chart showing an output signal waveform of the level-shifter circuit of the third embodiment;  
         [0023]    [0023]FIG. 9 is a circuit diagram showing a fourth embodiment of the level-shifter circuit of the present invention;  
         [0024]    [0024]FIG. 10 is a chart showing an output signal waveform of the level-shifter circuit of the fourth embodiment;  
         [0025]    [0025]FIG. 11 is a circuit diagram showing a fifth embodiment of the level-shifter circuit of the present invention;  
         [0026]    [0026]FIG. 12 is a chart showing an example of a substrate-bias potential Vbs according to the fifth embodiment;  
         [0027]    [0027]FIG. 13 is a chart showing an output signal waveform of the level-shifter circuit of the fifth embodiment;  
         [0028]    [0028]FIG. 14 is a circuit diagram showing a sixth embodiment of the level-shifter circuit of the present invention;  
         [0029]    [0029]FIG. 15 is a chart showing an output signal waveform of the level-shifter circuit of the sixth embodiment;  
         [0030]    [0030]FIG. 16 is a circuit diagram showing a seventh embodiment of the level-shifter circuit of the present invention; and  
         [0031]    [0031]FIG. 17 is a chart showing an output signal waveform of the level-shifter circuit of the seventh embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]    In the following, embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0033]    [0033]FIG. 2 is a circuit diagram showing a first embodiment of a level-shifter circuit according to the present invention.  
         [0034]    A level-shifter circuit  20  of FIG. 2 includes PMOS transistors  21  and  22 , NMOS transistors  23  and  24 , an inverter  25 , and an NMOS transistor  26 . An incoming signal IN is applied to the gate of the NMOS transistor  24 , and is also inverted by the inverter  25  to be applied to the gate of the NMOS transistor  23 . The incoming signal IN being HIGH (VL) makes the NMOS transistors  23  and  24  nonconductive and conductive, respectively, resulting in the PMOS transistors  21  and  22  being conductive and nonconductive, respectively. Accordingly, an output signal OUT is set to 0 V. If the incoming signal IN is LOW (0 V), the NMOS transistors  23  and  24  are conductive and nonconductive, respectively, resulting in the PMOS transistors  21  and  22  being nonconductive and conductive, respectively. In this case, therefore, the output signal OUT is set at V H . In this manner, the incoming potential level ranging between 0 and V L  is shifted to a range between 0 and V H .  
         [0035]    In the circuit construction of FIG. 2, the NMOS transistor  26  is provided in the level-shifter circuit  20 . The NMOS transistor  26  has a first node thereof (i.e., a drain node or a source node) coupled to the well of the NMOS transistor  24 , and has a second node (i.e., a source node or a drain node) and gate node thereof coupled to the incoming signal IN.  
         [0036]    In the level-shifter circuit  20 , a potential at the gate of the NMOS transistor  26  rises from LOW to HIGH at the start of a conductive state of the NMOS transistor  24 , i.e., at the negative transition of the output signal OUT responding to the transition from LOW to HIGH of the incoming signal IN. As the gate level exceeds the threshold of the NMOS transistor  26 , the NMOS transistor  26  is turned on, resulting in an electric current running between the drain and the source. A potential at the first node coupled to the well of the NMOS transistor  24  is thus brought closer to the potential of the incoming signal applied to the second node. Since the second node of the NMOS transistor  26  is coupled to the gate thereof, the NMOS transistor  26  becomes nonconductive in response to the approaching of the first-node potential to the second-node potential within a predetermined range. In this manner, the first node of the NMOS transistor  26  is maintained at a predetermined potential.  
         [0037]    The first node of the NMOS transistor  26  is coupled to the well of the NMOS transistor  24 . It follows that a substrate-bias potential Vbs of the NMOS transistor  24  (i.e., the potential of the well) is set at a predetermined potential lifted off the ground potential.  
         [0038]    When the conductive state of the NMOS transistor  24  comes to an end, i.e., when the output signal is about to rise in response to the transition from HIGH to LOW of the incoming signal IN, the NMOS transistor  26  coupled to the well of the NMOS transistor  24  is turned off while maintaining the potential at its first node. Since the well of the NMOS transistor  24  is connected to the first node of the NMOS transistor  26 , the substrate-bias potential Vbs is sustained at the predetermined potential.  
         [0039]    In this manner, the bias potential of the NMOS transistor  24  is in a floating state and always maintained at the predetermined potential. This means that the threshold is always kept at a reduced level.  
         [0040]    [0040]FIG. 3 is an example of the substrate-bias potential Vbs. At the negative transition of the output signal OUT, the substrate-bias potential Vbs does not rise to the level of the incoming-signal high potential V L  because the second node is set to the same potential as the gate node. In FIG. 3, the waveform of the substrate-bias potential Vbs is illustrated for the positive transition of the output signal OUT and for the negative transition of the output signal OUT. As shown in FIG. 3, the substrate-bias potential Vbs is always maintained at a predetermined potential. Since the substrate-bias potential Vbs is always in existence as a positive potential, the threshold of the NMOS transistor  24  is in a lowered state all the time. As a result, the output signal OUT is output at higher speed than in the conventional circuit construction. In FIG. 3, waveforms illustrated by solid lines are those of the first embodiment of the present invention shown in FIG. 2, and waveforms illustrated by dotted lines are those of the related-art construction shown in FIG. 1.  
         [0041]    [0041]FIG. 4 is a chart showing an output signal waveform of the level-shifter circuit  20  according to the first embodiment. As shown in FIG. 4, the output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition than a related-art output signal waveform shown by dotted lines. Here, the waveform of the substrate-bias potential Vbs shown in FIG. 3 and the output signal waveform of FIG. 4 are simulated waveforms obtained by a circuit simulator. Waveforms that will be shown hereafter are also obtained by use of the circuit simulator.  
         [0042]    [0042]FIG. 5 is a circuit diagram showing a second embodiment of the level-shifter circuit of the present invention. In FIG. 5, the same elements as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.  
         [0043]    A level-shifter circuit  20 A of FIG. 5 includes a NMOS transistor  27  newly provided in addition to the construction of the first embodiment shown in FIG. 2. The NMOS transistor  27  has a first node thereof coupled to the well of the NMOS transistor  23 , and has a second node thereof and a gate node thereof commonly coupled to an inverse of the incoming signal IN that is output from the inverter  25 .  
         [0044]    In the first embodiment shown in FIG. 2, the threshold of the NMOS transistor  24  that pulls down the output signal OUT is lowered, thereby making faster the negative transition of the output signal OUT. In addition, the second embodiment shown in FIG. 5 is further provided with a function to lower the threshold of the NMOS transistor  23 , which drives the PMOS transistor  22  that pulls up the output signal OUT. This makes it possible to achieve faster signal transition not only for the negative transition of the output signal OUT but also for the positive transition of the output signal OUT.  
         [0045]    [0045]FIG. 6 is a chart showing an output signal waveform of the level-shifter circuit  20 A of the second embodiment. As shown in FIG. 6, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.  
         [0046]    [0046]FIG. 7 is a circuit diagram showing a third embodiment of the level-shifter circuit of the present invention. In FIG. 7, the same elements as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.  
         [0047]    A level-shifter circuit  20 B of FIG. 7 includes a NMOS transistor  26 B that replaces the NMOS transistor  26  of the first embodiment shown in FIG. 2. The second node of the NMOS transistor  26 B has a different coupling than that of the NMOS transistor  26 . In the third embodiment, the second node of the NMOS transistor  26 B is coupled to the output of the inverter  25 .  
         [0048]    The output of the inverter  25  changes from HIGH to LOW with a predetermined time delay after the transition from LOW to HIGH of the incoming signal IN. When the gate node of the NMOS transistor  26 B is raised to HIGH by the incoming signal IN, therefore, the second node of the NMOS transistor  26 B still remains at the HIGH level. Because of this, lowering of the threshold occurs only for the duration of the delay time of the inverter  25 , thereby achieving high-speed switching. The output of the inverter  25  subsequently becomes LOW, so that the well of the NMOS transistor  24  coupled to the first node of the NMOS transistor  26 B is pulled down to the LOW level. In this manner, the threshold is set in the zero-biased state while the NMOS transistor  24  is conductive. This prevents the flowing of an excessive through current.  
         [0049]    [0049]FIG. 8 is a chart showing an output signal waveform of the level-shifter circuit  20 B of the third embodiment. As shown in FIG. 8, an output signal waveform of the present invention illustrated by solid lines exhibits a faster change at the negative signal transition than a related-art output signal waveform shown by dotted lines. As described above, the threshold is set in the zero-bias state during the LOW period of the output signal. This makes it possible to switch off the NMOS transistor  24  at high speed at the positive signal transition, thereby further enhancing the speed of positive signal transition compared with the first embodiment.  
         [0050]    [0050]FIG. 9 is a circuit diagram showing a fourth embodiment of the level-shifter circuit of the present invention. In FIG. 9, the same elements as those of FIG. 7 are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.  
         [0051]    A level-shifter circuit  20 C of FIG. 9 includes a NMOS transistor  27 C newly provided in addition to the construction of the third embodiment shown in FIG. 7. The NMOS transistor  27 C has a first node thereof coupled to the well of the NMOS transistor  23 , and has a second node thereof and a gate node thereof commonly coupled to an inverse of the incoming signal IN that is output from the inverter  25 .  
         [0052]    In the third embodiment shown in FIG. 7, the threshold of the NMOS transistor  24  that pulls down the output signal OUT is lowered, thereby making faster the negative transition of the output signal OUT. In addition, the fourth embodiment shown in FIG. 9 is further provided with a function to lower the threshold of the NMOS transistor  23 , which drives the PMOS transistor  22  that pulls up the output signal OUT. This makes it possible to achieve faster signal transition not only for the negative transition of the output signal OUT but also for the positive transition of the output signal OUT.  
         [0053]    [0053]FIG. 10 is a chart showing an output signal waveform of the level-shifter circuit  20 C of the fourth embodiment. As shown in FIG. 10, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.  
         [0054]    [0054]FIG. 11 is a circuit diagram showing a fifth embodiment of the level-shifter circuit of the present invention. In FIG. 11, the same elements as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.  
         [0055]    A level-shifter circuit  20 D of FIG. 11 includes a NMOS transistor  26 D that replaces the NMOS transistor  26  of the first embodiment shown in FIG. 2. The second node of the NMOS transistor  26 D has a different coupling than that of the NMOS transistor  26 . In the fifth embodiment, the second node (i.e., source node) of the NMOS transistor  26 D is coupled to the ground potential Vss.  
         [0056]    When the output signal OUT is about to rise in response to the change from HIGH to LOW of the incoming signal, i.e., when the NMOS transistor  24  is about to become nonconductive, the NMOS transistor  26 D coupled to the well commences its switching-off operation. As a result, positive charge (i.e., positive holes) is accumulated in the well of the NMOS transistor  24 , which leads to an increase in the well potential (i.e., the substrate-bias potential Vbs). When the NMOS transistor  26 D is fully nonconductive, the substrate-bias potential Vbs of the NMOS transistor  24  is thus at a raised level. The threshold is thus at a lowered level.  
         [0057]    Thereafter, the incoming signal changes from LOW to HIGH, resulting in the output signal OUT being pulled down. In this case, the output signal exhibits a faster change than in the related-art construction because the threshold of the NMOS transistor  24  has been held at the lowered level up to this point. When the NMOS transistor  26 D subsequently becomes conductive, the drain potential drops to the source potential coupled to the ground potential. This brings the threshold of the NMOS transistor  24  down to the zero-bias level, thereby preventing the occurrence of an excessive through current.  
         [0058]    [0058]FIG. 12 is a chart showing an example of a substrate-bias potential Vbs according to the fifth embodiment. At the positive transition of the output signal OUT, the substrate-bias potential Vbs is initially set to zero since the NMOS transistor  26 D has been conductive up to this point. In this case, therefore, the threshold is relatively high, so that the NMOS transistor  24  will be switched off at high speed in response to the change from HIGH to LOW of the incoming signal IN. At the negative transition of the output signal OUT, the substrate-bias potential Vbs has been held at an elevated level because of the nonconductive state of the NMOS transistor  26 D. In this case, thus, the threshold is relatively low, so that the NMOS transistor  24  will be switched on at high speed in response to the change from LOW to HIGH of the incoming signal.  
         [0059]    [0059]FIG. 13 is a chart showing an output signal waveform of the level-shifter circuit  20 D of the fifth embodiment. As shown in FIG. 13, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.  
         [0060]    [0060]FIG. 14 is a circuit diagram showing a sixth embodiment of the level-shifter circuit of the present invention. In FIG. 14, the same elements as those of FIG. 11 are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.  
         [0061]    A level-shifter circuit  20 E of FIG. 14 includes a NMOS transistor  27 E newly provided in addition to the construction of the fifth embodiment shown in FIG. 11. The NMOS transistor  27 E has a drain node thereof coupled to the well of the NMOS transistor  23 , and has a source node thereof coupled to the ground potential, with a gate node thereof coupled to an inverse of the incoming signal IN that is output from the inverter  25 .  
         [0062]    In the fifth embodiment shown in FIG. 11, the threshold of the NMOS transistor  24  that pulls down the output signal OUT is lowered, thereby making faster the negative transition of the output signal OUT. In addition, the sixth embodiment shown in FIG. 14 is further provided with a function to lower the threshold of the NMOS transistor  23 , which drives the PMOS transistor  22  that pulls up the output signal OUT. This makes it possible to achieve faster signal transition not only for the negative transition of the output signal OUT but also for the positive transition of the output signal OUT.  
         [0063]    [0063]FIG. 15 is a chart showing an output signal waveform of the level-shifter circuit  20 E of the sixth embodiment. As shown in FIG. 15, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.  
         [0064]    [0064]FIG. 16 is a circuit diagram showing a seventh embodiment of the level-shifter circuit of the present invention. In FIG. 16, the same elements as those of FIG. 2 are referred to by the same numerals.  
         [0065]    In a level-shifter circuit  20 F of FIG. 16, the well of the NMOS transistor  24  is directly coupled to the incoming signal IN. Such a direct coupling of the substrate to the incoming signal potential may destroy the NMOS transistor  24 , and, thus, careful circuit design is required. If the potential V L  of the incoming signal IN is sufficiently lowered through scaling, direct coupling may be used to boost the substrate bias by coupling the well of the NMOS transistor  24  to the incoming signal IN as shown in FIG. 16. This achieves high-speed signal transition of the output signal by lowering the threshold of the NMOS transistor  24  at the time of switching-on.  
         [0066]    [0066]FIG. 17 is a chart showing an output signal waveform of the level-shifter circuit  20 E of the seventh embodiment. As shown in FIG. 17, an output signal waveform of the present invention illustrated by solid lines exhibits a faster change in the negative signal transition than a related-art output signal waveform shown by dotted lines.  
         [0067]    Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.