Abstract:
There is provided a charge pump circuit suited for reducing the power consumption. A capacitor  201   a,  a capacitor  201   b,  a capacitor  201   c,  and switching elements  202   a  to  202   k,  for electrically connecting or separating capacitors  201   a,    201   b,  and  201   c,  repeats: a first state where charge supplied from an input power-supply voltage V DD  is accumulated in the capacitors  201   a  and  201   b;  a second state where the charge accumulated in the capacitor  201   a  is transferred to the third capacitor  201   c,  and a positive output power-supply voltage is held by the charge accumulated in the capacitor  201   b;  a third state where the charge supplied from an input power supply is accumulated in the capacitors  201   a  and  201   b ; and a fourth state where the charge accumulated in the capacitor  201   b  is transferred to the third capacitor  201   c , and the positive output power-supply voltage V CC  is held by the charge accumulated in the capacitor  201   a.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a charge pump circuit for supplying both positive and negative power supply to a driven circuit, a control method thereof, and a semiconductor integrated circuit for driving the charge pump circuit, in particular, to a charge pump circuit capable of generating positive and negative power-supply voltages, control method thereof, and a semiconductor integrated circuit. 
       BACKGROUND ART 
       [0002]      FIG. 11  is a view showing an existing charge pump circuit for driving a video amplifier. The charge pump circuit shown is configured to be a circuit to be driven by a single power supply, which is a positive power supply. Such a charge pump circuit is disclosed by, for example, Patent Document 1. 
         [0003]    The existing charge pump circuit shown in  FIG. 11  generates a negative power-supply voltage (V EE ) with a positive power-supply voltage (V DD ) supplied from a positive power supply and ground voltage (GND). Then, a driven circuit to be driven between the positive power-supply voltage and the negative power-supply voltage directly drives a load without the use of a capacitor for cutting DC (Direct Current) with the ground voltage set as a center level, and outputs signals. In such a charge pump circuit, switching elements  111  and  113  are switched on in a first period of a clock signal, and a capacitor C 1  is directly connected between the supplied positive voltage and the ground voltage. In this situation, electric charge is accumulated in the capacitor C 1 . 
         [0004]    In addition, in a second period of the clock signal, the switching elements  111  and  113  are switched off, and simultaneously switching elements  112  and  114  are switched on. In this situation, a capacitor C 2  is directly connected between a negative voltage terminal for generating the negative voltage and the ground voltage, and the accumulated electric charge is transferred. The charge pump circuit shown in  FIG. 11  repeatedly performs a series of operations as described above to generate the negative voltage. 
       PRIOR ART DOCUMENT 
     Patent Document 
       [0005]    Patent Document 1: JP 2001-309400 A 
       Problem to be Solved 
       [0006]    In the charge pump circuit of a conventional technique described in Patent Document 1, however, substantially a voltage of −V DD  as a negative power-supply voltage is output regardless of the voltage value output from the video amplifier. Therefore, the video amplifier always operates at a power-supply range of 2 V DD , thereby causing a problem that the power consumption of the video amplifier is increased. 
         [0007]    The present invention has been made in view of the above circumstances, and has an object to provide a charge pump circuit for generating a power-supply voltage to drive a driven circuit with the generated power-supply voltage to be suitable for reducing the power consumption, a control method thereof, and a semiconductor integrated circuit. 
       Solution to the Problem 
       [0008]    In order to solve the above problem, according to an aspect of the present invention, there is provided a charge pump circuit, to be supplied with electric charge from an input power supply (for example, a power supply connected to V DD , as illustrated in  FIG. 2 ), for generating a positive output power-supply voltage (for example, V CC , as illustrated in  FIG. 2 ) of a positive output power supply and a negative output power-supply voltage (for example, V EE , as illustrated in  FIG. 2 ) of a negative output power supply, the charge pump circuit comprising: a first capacitor (for example, a capacitor  201   a,  as illustrated in  FIG. 2 ); a second capacitor (for example, a capacitor  201   b,  as illustrated in  FIG. 2 ) connected in series with the first capacitor; a third capacitor (for example, a capacitor  201   c,  as illustrated in  FIG. 2 ) for holding the electric charge corresponding to the negative output power-supply voltage; and a switching circuit (for example, switching elements  202   a  to  202   k  as illustrated in  FIG. 2 ) for electrically connecting or separating the first capacitor, the second capacitor, and the third capacitor, wherein the switching circuit repeats: a first state (for example, a clock signal CLK 1  is high, as illustrated in  FIG. 4 ) in which the charge supplied from the input power supply is accumulated in the first capacitor and the second capacitor connected in series with the first capacitor; a second state (for example, a clock signal CLK 2  is high, as illustrated in  FIG. 4 ) in which the charge accumulated in the first capacitor in the first state is transferred to the third capacitor and the positive output power-supply voltage is held by the charge accumulated in the second capacitor; a third state (for example, a clock signal CLK 3  is high, as illustrated in  FIG. 4 ) in which the charge supplied from the input power supply is accumulated in the first capacitor and the second capacitor connected in series with the first capacitor; and a fourth state (for example, a clock signal CLK 4  is high, as illustrated in  FIG. 4 ) in which the charge accumulated in the second capacitor in the third state is transferred to the third capacitor and the positive output power-supply voltage is held by the charge accumulated in the first capacitor. 
         [0009]    In addition, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, the switching circuit (for example, switching elements  202   a  to  202   k,  as illustrated in  FIG. 2 ) includes: a first switching unit (for example, switching elements  202   a  and  202   e,  as illustrated in  FIG. 2 ) for connecting the input power supply (for example, V DD , as illustrated in  FIG. 2 ) or a ground terminal (for example, a terminal of a ground voltage GND, as illustrated in  FIG. 2 ) to an anode terminal of the first capacitor (for example, the capacitor  201   a,  as illustrated in  FIG. 2 ); a second switching unit (for example, switching elements  202   b  and  202   f,  as illustrated in  FIG. 2 ) for connecting the positive output power supply (for example, a power supply for outputting the positive output power-supply voltage V CC , as illustrated in  FIG. 2 ) or the negative output power supply (for example, a power supply for outputting the negative output power-supply voltage V EE , as illustrated in  FIG. 2 ) to a cathode terminal of the first capacitor; a third switching unit (for example, switching elements  202   c  and  202   g,  as illustrated in  FIG. 2 ) for connecting the positive input power supply or the ground terminal to an anode terminal of the second capacitor; and a fourth switching unit (for example, switching elements  202   d  and  202   h,  as illustrated in  FIG. 2 ) for connecting the ground terminal or the negative output power supply to a cathode terminal of the second capacitor. 
         [0010]    In addition, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, wherein, in the first state (for example, when the clock signal CLK 1  is high, as illustrated in  FIG. 2 ), the switching circuit (for example, switching elements  202   a  to  202   k,  as illustrated in  FIG. 2 ) connects the input power supply (for example, V DD , as illustrated in  FIG. 2 ) to the anode terminal of the first capacitor (for example, the capacitor  201   a,  as illustrated in  FIG. 2 ) and connects the positive output power-supply voltage (for example, a power supply for outputting the positive output power-supply voltage V CC , as illustrated in  FIG. 2 ) to the cathode terminal of the first capacitor, the switching circuit connects the positive output power supply to the anode terminal of the second capacitor (for example, the capacitor  201   b,  as illustrated in  FIG. 2 ) and connects the ground terminal (for example, the terminal of the ground voltage GND, as illustrated in  FIG. 2 ) to the cathode terminal of the second capacitor, and the switching circuit connects the ground terminal to the anode terminal of the third capacitor (for example, the capacitor  201   c,  as illustrated in  FIG. 2 ) and connects the negative output power supply to the cathode terminal of the third capacitor, wherein, in the second state (for example, the clock signal CLK 2  is high, as illustrated in  FIG. 4 ), the switching circuit connects the ground terminal to the anode terminal of the first capacitor and connects the negative output power supply to the cathode terminal of the first capacitor, the switching circuit connects the positive output power supply to the anode terminal of the second capacitor and connects the ground terminal to the cathode terminal of the second capacitor, and the switching circuit connects the ground terminal to the anode terminal of the third capacitor and connects the negative output power supply to the cathode terminal of the third capacitor, wherein, in the third state (for example, the clock signal CLK 3  is high, as illustrated in  FIG. 4 ), the switching circuit connects the input power supply to the anode terminal of the first capacitor and connects the positive output power supply to the cathode terminal of the first capacitor, the switching circuit connects the positive output power supply to the anode terminal of the second capacitor and connects the ground terminal to the cathode terminal of the second capacitor, and the switching circuit connects the ground terminal to the anode terminal of the third capacitor and connects the negative output power supply to the cathode terminal of the third capacitor, and wherein, in the fourth state (for example, the clock signal CLK 4  is high, as illustrated in  FIG. 4 ), the switching circuit connects the input power supply to the anode terminal of the first capacitor and connects the positive output power supply to the cathode terminal of the first capacitor, the switching circuit connects the ground terminal to the anode terminal of the second capacitor and connects the negative output power supply to the cathode terminal of the second capacitor, and the switching circuit connects the ground terminal to the anode terminal of the third capacitor and connects the negative output power supply to the cathode terminal of the third capacitor. 
         [0011]    Furthermore, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, absolute values of the positive output power-supply voltage (for example, V CC , as illustrated in  FIG. 2 ) and the negative output power-supply voltage (for example, V EE , as illustrated in  FIG. 2 ) are approximately a half a voltage of the input power supply (for example, V DD , as illustrated in  FIG. 2 ), by accumulating the charge in the first capacitor (for example, the capacitor  201   a,  as illustrated in  FIG. 2 ), the second capacitor (for example, the capacitor  201   b,  as illustrated in  FIG. 2 ), and the third capacitor (for example, the capacitor  201   c,  as illustrated in  FIG. 2 ). 
         [0012]    Moreover, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, the switching circuit further repeats: a fifth state (for example, the clock signal CLK 1  or CLK 3  is high, as illustrated in  FIG. 6 ) in which the charge supplied from the input power supply is accumulated in the first capacitor, the charge accumulated in the second capacitor is transferred to the third capacitor, and the input power supply is connected to the positive output power supply; and a sixth state (for example, the clock signal CLK 2  or CLK 4  is high, as illustrated in  FIG. 6 ) in which the charge supplied from the input power supply is accumulated in the second capacitor, the charge accumulated in the first capacitor is transferred to the third capacitor, and the input power supply is connected to the positive output power supply. 
         [0013]    In addition, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, wherein the switching circuit (for example, the switching elements  202   a  to  202   k,  as illustrated in  FIG. 2 ) further includes: a fifth switching unit (for example, the switching element  202   k,  as illustrated in  FIG. 2 ) for connecting a terminal into which the input power supply is input and the positive output power supply; a sixth switching unit (for example, the switching element  202   i,  as illustrated in  FIG. 2 ) for connecting the cathode terminal of the first capacitor (for example, the capacitor  201   a,  as illustrated in  FIG. 2 ) and the ground terminal (for example, the terminal of the ground voltage GND, as illustrated in  FIG. 2 ); and a seventh switching unit (for example, the switching element  202   j,  as illustrated in  FIG. 2 ) for connecting the anode terminal of the second capacitor and the input power supply. 
         [0014]    Furthermore, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, in the fifth state (for example, the clock signal CLK 1  or CLK 3  is high, as illustrated in  FIG. 6 ), the switching circuit (for example, the switching elements  202   a  to  202   k , as illustrated in  FIG. 2 ) connects the input power supply (for example, V DD , as illustrated in  FIG. 2 ) to the anode terminal of the first capacitor (for example, the capacitor  201   a,  as illustrated in  FIG. 2 ) and connects the ground terminal (for example, the terminal of the ground voltage GND, as illustrated in  FIG. 2 ) to the cathode terminal of the first capacitor, the switching circuit connects the ground terminal to the anode terminal of the second capacitor (for example, the capacitor  201   b,  as illustrated in  FIG. 2 ) and connects the negative output power supply (for example, the power supply for outputting the negative power-supply voltage V EE , as illustrated in  FIG. 2 ) to the cathode terminal of the second capacitor, and the switching circuit connects the ground terminal to the anode terminal of the third capacitor (for example, the capacitor  201   c,  as illustrated in  FIG. 2 ), connects the negative output power supply to the cathode terminal of the third capacitor, and connects the input power supply to the positive output power supply, and wherein, in the sixth state (for example, the clock signal CLK 2  or CLK 4  is high, as illustrated in  FIG. 6 ), the switching circuit connects the ground terminal to the anode terminal of the first capacitor and connects the negative output power supply to the cathode terminal of the first capacitor, the switching circuit connects the input power supply to the anode terminal of the second capacitor and connects the ground terminal to the cathode terminal of the second capacitor, and the switching circuit connects the ground terminal to the anode terminal of the third capacitor, connects the negative output power supply to the cathode terminal of the third capacitor, and connects the input power supply to the positive output power supply. 
         [0015]    Moreover, according to an aspect of the present invention, in the above-described charge pump circuit, preferably, absolute values of the positive output power-supply voltage (for example, V CC , as illustrated in  FIG. 2 ) and the negative output power-supply voltage (for example, V EE , as illustrated in  FIG. 2 ) are approximately same with a voltage of the input power supply (for example, V DD , as illustrated in  FIG. 2 ), by accumulating the charge in the first capacitor (for example, the capacitor  201   a,  as illustrated in  FIG. 2 ), the second capacitor (for example, the capacitor  201   b,  as illustrated in  FIG. 2 ), and the third capacitor (for example, the capacitor  201   c,  as illustrated in  FIG. 2 ). 
         [0016]    In addition, according to an aspect of the present invention, in the above-described invention, there is provided a semiconductor integrated circuit so that the charge pump circuit is operated to repeat the first state to the fourth state, when a differential voltage between the positive output power-supply voltage and a value of an output signal voltage of an amplifier that operates by the positive output power-supply voltage (for example, V CC , as illustrated in  FIG. 2 ) and the negative output power-supply voltage (for example, V EE , as illustrated in  FIG. 2 ), and a differential voltage between a value of the output signal voltage and a value of the negative output power-supply voltage are both higher than a preset reference voltage, and further comprises a mode detecting circuit (for example, a mode detecting circuit  7 , as illustrated in  FIG. 1 ) for operating the charge pump circuit according to any one of claim  5  to claim  8  to repeat the fifth state and the sixth state, when any one of the differential voltages is lower than a preset reference voltage. 
         [0017]    Furthermore, according to an aspect of the present invention, in the above-described semiconductor integrated circuit, preferably, the charge pump circuit is operated to repeat the first state to the fourth state, when an absolute value of a differential voltage between a value of an output signal voltage from an amplifier that operates by the positive output power-supply voltage and the negative output power-supply voltage and a value of ground voltage is lower than a preset reference voltage, further comprising a mode detecting circuit (for example, the mode detecting circuit  7 , as illustrated in  FIG. 1 ) for operating the charge pump circuit according to any one of claim  5  to claim  8  to repeat the fifth state and the sixth state, when the absolute value of the differential voltage is higher than a preset reference voltage. 
         [0018]    In addition, according to an aspect of the present invention, there is provided a control method of a charge pump circuit, to be supplied with electric charge from an input power supply, for generating a positive output power-supply voltage of a positive output power supply and a negative output power-supply voltage of a negative output power supply, the charge pump circuit comprising: a first capacitor; a second capacitor connected in series with the first capacitor; and a third capacitor for holding the electric charge corresponding to the negative output power-supply voltage, the control method repeats: a first state in which the charge supplied from the input power supply is accumulated in the first capacitor and the second capacitor connected in series with the first capacitor; a second state in which the charge accumulated in the first capacitor in the first state is transferred to the third capacitor and the positive output power-supply voltage is held by the charge accumulated in the second capacitor; a third state in which the charge supplied from the input power supply is accumulated in the first capacitor and the second capacitor connected in series with the first capacitor; and a fourth state in which the charge accumulated in the second capacitor in the third state is transferred to the third capacitor and the positive output power-supply voltage is held by the charge accumulated in the first capacitor. 
         [0019]    Furthermore, according to an aspect of the present invention, in the above-described control method of the charge pump circuit, preferably, the method repeats: a fifth state in which the charge supplied from the input power supply is accumulated in the first capacitor, the charge accumulated in the second capacitor is transferred to the third capacitor, and the input power supply is connected to the positive output power supply; and a sixth state in which the charge supplied from the input power supply is accumulated in the second capacitor, the charge accumulated in the first capacitor is transferred to the third capacitor, and the input power supply is connected to the positive output power supply. 
       Advantageous Effects of the Invention 
       [0020]    According to the above-described present invention, it is possible to generate positive and negative output power supplies in the charge pump circuit. In addition, such a charge pump circuit can be configured with switching elements and capacitors. Furthermore, in the above charge pump circuit, absolute values of the voltages supplied from the positive and negative output power supplies are made to a half an input voltage, so that the power consumption from the load driving system can be reduced. This is exhibited that the output current of 2I is made available from input current of I, by converting the input power of V DD ×I into the power of  ½ V   DD ×2I. 
         [0021]    In addition, according to the above-described invention, it is further possible to generate other positive and negative output power supplies in the charge pump circuit. Furthermore, such a charge pump circuit can be configured with switching elements and capacitors. Moreover, in the above-described charge pump circuit, the absolute value of the voltage supplied from the positive and negative output power supplies can be made to the same value with the input voltage. In this situation, the charge accumulation and the charge transfer of two capacitors are performed complementarily when the negative voltage is generated. Therefore, the charge pump circuit according to the present invention has a double capability of supplying current as compared to the conventional charge pump circuit. 
         [0022]    Moreover, according to the above-described invention, when a signal output from a driven circuit to be driven by a charge pump circuit to a load is relatively small, it is possible to make small the voltage value supplied from an output power supply, whereas when the signal is relatively great, it is possible to make greater the voltage value supplied from an output power supply. Accordingly, it is made possible to switch the power consumption of a load driving system as needed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a block diagram illustrative of the load driving system according to an embodiment of the present invention; 
           [0024]      FIG. 2  is a circuit diagram illustrative of a detailed configuration of a charge pump circuit illustrated in  FIG. 1 ; 
           [0025]      FIG. 3-1  is a diagram illustrative of an operation state of the charge pump circuit in mode 1 according to an embodiment of the present invention; 
           [0026]      FIG. 3-2  is a diagram illustrative of another operation state of the charge pump circuit in mode 1 according to an embodiment of the present invention; 
           [0027]      FIG. 4  is a view illustrative of the clock signals in mode 1 and switch controlling signals to be input into the charge pump circuit according to an embodiment of the present invention; 
           [0028]      FIG. 5  is a view illustrative of an operation state of the charge pump circuit in mode 2 according to an embodiment of the present invention; 
           [0029]      FIG. 6  is a view illustrative of the clock signals in mode 2 and the switch controlling singles to be input into the charge pump circuit according to an embodiment of the present invention; 
           [0030]      FIG. 7  is a view illustrative of a configuration example of a mode detecting circuit illustrated in  FIG. 1  in more detail, and is a view illustrative of relationships between output power-supply voltages V EE  and V CC  and an output signal S OUT ; 
           [0031]      FIG. 8  is a view illustrative of a configuration example of the mode detecting circuit illustrated in  FIG. 1  in more detail, and is a view illustrative of relationships between a reference voltage and the output signal S OUT ; 
           [0032]      FIG. 9  is a view illustrative of switching a mode detecting signal according to an embodiment of the present invention; 
           [0033]      FIG. 10  is a view illustrative of relationships between magnitude of the output signal and current I DD  consumed by the load driving system according to an embodiment of the present invention; and 
           [0034]      FIG. 11  shows an existing charge pump circuit for driving a video amplifier. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0035]    Hereinafter, a charge pump circuit, a control method thereof, and a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the charge pump circuit according to the present embodiment is applied to an amplifier circuit that is a driven circuit . A description will be given of a load driving system configured with the amplifier circuit for amplifying an input signal to supply it to a load. 
         [0036]    (Circuit Configuration) 
         [0037]      FIG. 1  is a block diagram illustrative of the load driving system according to the present embodiment. Referring to FIG. 
         [0038]      1 , a load driving system  1  includes: a clock generating circuit  2 ; a switch controlling circuit  3 ; a charge pump circuit  4 ; an amplifier circuit  5 ; a load  6 ; and a mode detecting circuit  7 . The charge pump circuit  4  has a function of generating a positive output power-supply voltage V CC  and a negative output power-supply voltage V EE  from a positive input power-supply voltage V DD , in a charge pump system configured with capacitors and switching elements. Such a charge pump circuit  4  will be described later in detail. 
         [0039]    The clock generating circuit  2  outputs clock signals CLK 1  to CLK 4 . The output clock signals CLK 1  to CLK 4  are input into the switch controlling circuit  3 . The switch controlling circuit  3  generates switch controlling signals SW 1  to SW 11  based upon the clock signals CLK 1  to CLK 4 , and outputs the switch controlling signals SW 1  to SW 11  to the charge pump circuit  4 . The switch controlling signals SW 1  to SW 11  are signals for controlling multiple switching elements, respectively, provided in the charge pump circuit  4 . 
         [0040]    The charge pump circuit  4  outputs the positive output power-supply voltages V CC  and V EE  by switching the switches, and the output power-supply voltages V CC  and V EE  are supplied to the amplifier circuit  5 . The amplifier circuit  5  outputs an output signal S OUT  from the supplied output power-supply voltages V CC  and V EE , an input signal S IN , and a level adjusting voltage V r . The load  6  is connected to a terminal to which the output signal S OUT  is output. 
         [0041]    In addition, the charge pump circuit  4  has two switching modes, and the load driving system  1  is provided with the mode detecting circuit  7  for detecting the mode in which the charge pump circuit  4  is to operate. The mode detecting circuit  7  receives the output signal S OUT  and the output power-supply voltages V CC  and V EE , and generates a mode determining signal M based upon the output signal S OUT  and the output power-supply voltages V CC  and V EE . The mode determining signal M is input into the switch controlling circuit  3 , and the switch controlling circuit  3  generates the switch controlling signals SW 1  to SW 11  according to the mode determining signal M. 
         [0042]    When the mode determining signal M is a low level, the charge pump circuit  4  operates in mode 1, and the absolute values of the output power-supply voltages V CC  and V EE  are equal to approximately a half the input power-supply voltage V DD . When the mode determining signal is a high level, the charge pump circuit  4  operates in mode 2. In this case, the absolute values of the output power-supply voltages V CC  and V EE , which are output at this time, are approximately equal to the input power-supply voltage V DD . 
         [0043]    The clock generating circuit  2  is provided with an oscillator such as a crystal oscillator, ceramic oscillator, or the like, and has a function of generating four types of clock signals CLK 1 , CLK 2 , CLK 3 , and CLK 4  for controlling on and off of the switching elements included in the charge pump circuit  4 . Specifically, CLK 1  to CLK 4  are signals each having the same cycle and same amplitude, and the level thereof becomes higher sequentially from CLK 1 . In this situation, the other three signals are each a low level. 
         [0044]    The clock signals CLK 1  to CLK 4  and the mode determining signal M are input into the switch controlling circuit  3 . Then, the switch control signals SW 1  to SW 11  for controlling on and off of the switches based upon the clock signals CLK 1  to CLK 4  and the mode determining signal M are supplied to the charge pump circuit  4 . 
         [0045]    The amplifier circuit  5  is an inverting amplifier circuit including an operational (OP) amplifier, and has a function of outputting the output signal S OUT  in which a differential signal between the input signal S IN  input into the inverting input terminal (indicated by “−” in the drawing) and a level adjusting voltage V r  of an offset voltage input into a non-inverting input terminal (indicated by “+” in the drawing) is inverted and amplified. 
         [0046]    The load  6  is a load to be driven by the output signal OUT output from the amplifier circuit  5 . Examples of the load  6  are speakers or headphones. In this case, the input signal S IN  is an audio input signal. In addition, the load  6  also corresponds to a buffer circuit or the like for driving the speakers or headphones. 
         [0047]      FIG. 2  is a circuit diagram illustrative of a configuration of the charge pump circuit  4  illustrated in  FIG. 1 , in more detail. The charge pump circuit  4  illustrated in  FIG. 2  includes: capacitors  201   a  to  201   c;  and switching elements  202   a  to  202   k.  Additionally, the terminal indicated by V DD  in  FIG. 2  is a terminal connected to the input power supply. The terminal indicated by V CC  is a terminal into which the positive output power-supply voltage V CC  is input, whereas the terminal indicated by V EE  is a terminal into which the negative output power-supply voltage V EE  is input. 
         [0048]    In the present embodiment, hereinafter, a description will be given such that a terminal V DD  is a terminal connected to the input power supply, a terminal V CC  is a terminal connected to a positive output power supply, and a terminal V EE  is a terminal connected to a negative output power supply. In addition, being connected to the terminal V DD  means electrical connection with the terminal into which the input power-supply voltage V DD  is input, and being connected to the terminal V CC  means electrical connection with the terminal into which the output power-supply voltage V CC  is input. Furthermore, being connected to the terminal V EE  means electrical connection with the terminal into which the negative output power-supply voltage V EE  is input. 
         [0049]    In the present embodiment, switching elements  202   d  to  202   i  are each configured with an N-channel MOS transistor. However, the present embodiment is not limited to the switching elements  202   d  to  202   i  each configured with an N-channel MOS transistor. The switching elements  202   d  to  202   i  may be each configured with a P-channel MOS transistor. 
         [0050]    Moreover, in the present embodiment, switching elements  202   a  to  202   c,    202   j,  and  202   k  are each configured with a P-channel MOS transistor. However, the present embodiment is not limited to the switching elements  202   a  to  202   c,    202   j , and  202   k  each configured with the P-channel MOS transistor. The switching elements  202   a  to  202   c,    202   j,  and  202   k  may be each configured with an N-channel MOS transistor. 
         [0051]    The anode terminal of the capacitor  201   a  is electrically connected to the switching element  202   a  and the drain terminal of the switching element  202   e,  respectively. The source terminal of the switching element  202   a  is connected to the terminal V DD . The source terminal of the switching element  202   e  is electrically connected to the terminal of the ground voltage GND. 
         [0052]    Additionally, the cathode terminal of the capacitor  201   a  is electrically connected to the source terminal of the switching element  202   b,  and the drain terminal of the switching element  202   f  and the switching element  202   i , respectively. The drain terminal of the switching element  202   b  is connected to the terminal V CC . The source terminal of the switching element  202   f  is connected to the terminal V EE , and the source terminal of the switching element  202   i  is electrically connected to the terminal of the ground voltage GND. 
         [0053]    The anode terminal of the capacitor  201   b  is electrically connected to the drain terminals of the switching elements  202   c,    202   g,  and  202   j,  respectively. The source terminal of the switching element  202   c  is connected to the terminal V. The source terminal of the switching element  202   g  is electrically connected to the ground voltage GND. The source terminal of the switching element  202   j  is connected to the terminal V DD . 
         [0054]    The cathode terminal of the capacitor  201   b  is electrically connected to the drain terminals of the switching elements  202   d  and  202   h,  respectively. The source terminal of the switching element  202   d  is electrically connected to the terminal of the ground voltage GND. The source terminal of the switching element  202   h  is connected to the terminal V EE . 
         [0055]    The anode terminal of the capacitor  201   c  is electrically connected to the terminal of the ground voltage GND, and the cathode terminal thereof is connected to the terminal V EE . The source terminal of the switching element  202   k  is connected to the terminal V DD , and the drain terminal thereof is connected to the terminal V CC . Specifically, the potential of the ground voltage GND is maintained at the ground voltage (0 [V]). 
         [0056]    (Operations) 
         [0057]    Next, operations in mode 1 and mode 2 of the charge pump circuit  4  according to the present embodiment will be described independently. 
       Mode 1 
       [0058]      FIG. 3-1  and  FIG. 3-2  are diagrams illustrative of operation states of the charge pump circuit  4  in mode 1.  FIG. 4  is a view illustrative of the clock signals CLK 1  to CLK 4  in mode 1 and the switch controlling signals SW 1  to SW 11  to be input into the charge pump circuit  4 . The switch controlling signals SW 1  to SW 11  respectively correspond to control signals of the switching elements  202   a  to  202   k . The switch is switched on when the control signal is a high level, whereas the switch is switched off when the control signal is a low level. As illustrated, the clock signals CLK 1  to CLK 4  are pulse signals having different phases from each other. 
         [0059]    Out of the switch controlling signals SW 1  to SW 8 , the switch controlling signals SW 1  and SW 2  are pulse signals having the same phase, and the switch controlling signals SW 3  and SW 4  are pulse signals having the same phase. In addition, the switch controlling signals SW 5  and SW 6  are pulse signals having the same phase, and the switch controlling signals SW 7  and SW 8  are pulse signals having the same phase. Furthermore, the switch controlling signals SW 1  and SW 2 , and the switch controlling signals SW 5  and SW 6  are pulse signals having the opposite phases, and the switch controlling signals SW 3  and SW 4 , and the switch controlling signals SW 7  and SW 8  are pulse signals having the opposite phases. The switch controlling signals SW 9 , SW 10 , and SW 11  are signals each always having a constant value, and are always low. 
         [0060]      FIG. 3-1A  is a view illustrative of on and off states of the switching elements  202   a  to  202   k  when the clock signal CLK 1  is a high level (hereinafter, referred to “high”), and  FIG. 3-1B  is a view illustrative of on and off states of the switching elements  202   a  to  202   k  when the clock signal CLK 2  is high.  FIG. 3-2C  is a view illustrative of on and off states of the switching elements  202   a  to  202   k  when the clock signal CLK 3  is high, and  FIG. 3-2D  is a view illustrative of on and off states of the switching elements  202   a  to  202   k  when the clock signal CLK 4  is high. However, in  FIG. 3-1  and  FIG. 3-2 , the polarities of the MOS transistors constituting the switching elements have been described with reference to  FIG. 2 . 
         [0061]    As illustrated in the drawing, when the clock signal CLK 1  output from the clock generating circuit  2  is high, the switching elements  202   a  to  202   d  are switched on and the switching elements  202   e  to  202   k  are switched off in the charge pump circuit  4 . In this situation, a path from the terminal V DD , the switching element  202   a,  the switching element  202   b , the capacitor  201   a,  the switching element  202   c,  the capacitor  201   b,  the switching element  202   d  to GND is established, and the capacitors  201   a  and  201   b  connected in series are charged. 
         [0062]    In addition, when the clock signal CLK 2  is high, the switching elements  202   c  to  202   f  are switched on and the switching elements  202   a,    202   b,  and  202   g  to  202   k  are switched off in the charge pump circuit  4 . In this situation, a closed loop from GND, the switching element  202   e,  the capacitor  201   a , the switching element  202   f,  the capacitor  201   c  to GND is established, and the electric charge accumulated in the capacitor  201   a  is transferred to the capacitor  201   c.  In this situation, the positive output power-supply voltage V CC  is held by the capacitor  201   b.    
         [0063]    When the clock signal CLK 3  is high, the switching elements  202   a  to  202   d  are switched on and the switching elements  202   e  to  202   k  are switched off in the charge pump circuit  4 . In this situation, in the same manner as the case where the clock signal CLK 1  is high, the path from the terminal V DD , the switching element  202   a,  the capacitor  201   a,  the switching element  202   b,  the switching element  202   c,  the capacitor  201   b,  the switching element  202   d  to GND is established, and the capacitors  201   a  and  201   b  are charged. 
         [0064]    When the clock signal CLK 4  is high, the switching elements  202   a,    202   b,    202   g,  and  202   h  are switched on and the switching elements  202   c  to  202   f  and the switching elements  202   i  to  202   k  are switched off in the charge pump circuit  4 . In this situation, a closed loop from GND, the switching element  202   g,  the capacitor  201   b,  the switching element  202   h , the capacitor  201   c  to GND is established, and the electric charge accumulated in the capacitor  201   b  is transferred to the capacitor  201   c.  In this situation, the positive output power-supply voltage V CC  is held by the capacitor  201   a.    
         [0065]    Specifically, in the above description, the switching elements  202   b,    202   d,    202   f,    202   h,  and  202   i  are subject to level shift appropriately to switch on and off the path in a negative voltage region. 
         [0066]    Switching of the above-described four states repeatedly continues in response to the switching timings of the clock signals CLK 1  to CLK 4 . In the present embodiment, a positive voltage can be generated between the terminal of the ground voltage GND and the terminal V CC , such that the positive voltage has the same polarity with the input power-supply voltage V DD  and has a substantially same level with the voltage which has a value approximately a half thereof. In addition, a negative voltage can be generated between the terminal of the ground voltage GND and the terminal V EE , such that the negative voltage has the opposite polarity with the input power-supply voltage V DD  and has a substantially same level with the voltage which has a value approximately a half thereof. 
       Mode 2 
       [0067]    Next, operations of mode 2 performed in the charge pump circuit  4  according to the present embodiment will be described. 
         [0068]      FIG. 5  is a view illustrative of an operation state of the charge pump circuit  4  in mode 2.  FIG. 5A  illustrates on and off states of the switching elements  202   a  to  202   k  when the clock signal CLK 1  or the clock signal CLK 3  is high.  FIG. 5B  illustrates on and off states of the switching elements  202   a  to  202   k  when the clock signal CLK 2  or the clock signal CLK 4  is high. In  FIG. 5 , the polarities of the MOS transistors constituting the switching elements have been described with reference to  FIG. 2 . 
         [0069]      FIG. 6  is a view illustrative of the clock signals CLK 1  to CLK 4  in mode 2 and the switch controlling signals SW 1  to SW 11  to be input into the charge pump circuit  4 . The switch controlling signals SW 1  to SW 11  respectively correspond to control signals of the switching elements  202   a  to  202   k.  The switch is switched on at a high level, and the switch is switched off at a low level. The clock signals CLK 1  to CLK 4  illustrated in  FIG. 6  are same with the clock signals CLK 1  to CLK 4  illustrated in  FIG. 4 . However, in mode 2, the switch controlling signals SW 1  to SW 11  to be output by the switch controlling circuit  3  based upon the clock signals CLK 1  to CLK 4  are different from those in mode 1. 
         [0070]    That is to say, out of the switch controlling signals SW 1  to SW 11  in mode 2, the switch controlling signals SW 4  to SW 6  and the switch controlling signal SW 10  are signals having the same phase, and the switch controlling signal SW 1  and the switch controlling signals SW 7  to SW 9  are signals having the same phase. Then, the switch controlling signals SW 4  to SW 6  and SW 10  are pulse signals having opposite phases from those of the switch controlling signals SW 1  and SW 7  to SW 9 . The switch controlling signals SW 2 , SW 3 , and SW 11  are signals each having a certain value, and the switch controlling signals SW 2  and SW 3  are always low and the switch controlling signal SW 11  is always high. 
         [0071]    In such mode 2, when the clock signal CLK 1  or CLK 3  is high, the switching elements  202   a,    202   g  to  202   i,  and  202   k  are switched on, and the switching elements  202   b  to  202   f  and  202   j  are switched off. 
         [0072]    In addition, when the clock signal CLK 2  or CLK 4  is high, the switching elements  202   d  to  202   f,    202   j,  and  202   k  are switched on, and the switching elements  202   a  to  202   c  and  202   g  to  202   i  are switched off. However, the switching elements  202   b,    202   d,    202   f,    202   h,  and  202   i  are subject to level shift appropriately to switch on and off the path in a negative voltage region. 
         [0073]    In the charge pump circuit  4  in mode 2, when the switching elements  202   a  and  202   g  to  202   i  are switched on, a path from the terminal V DD , the switching element  202   a,  the capacitor  201   a,  the switching element  202   i  to GND is established. In this situation, the capacitor  201   a  is charged. 
         [0074]    In addition, when the switching elements  202   a  and  202   g  to  202   i  are switched on, a closed loop from GND, the switching element  202   g,  the capacitor  201   b,  the switching element  202   h , the capacitor  201   c  to GND is established. In this situation, the electric charge accumulated in the capacitor  201   b  is transferred to the capacitor  201   c.    
         [0075]    Furthermore, when the switching elements  202   d  to  202   f  and  202   j  are switched on, a path from the terminal V DD , the switching element  202   j,  the capacitor  201   b,  the switching element  202   d  to GND is established, and the capacitor  201   b  is charged. Moreover, the switching elements  202   d  to  202   f  and  202   j  are switched on, a closed loop from GND, the switching element  202   e,  the capacitor  201   a,  the switching element  202   f , the capacitor  201   c  to GND is established. In this situation, the electric charge accumulated in the capacitor  201   a  is transferred to the capacitor  201   c.    
         [0076]    In addition, the switching element  202   k  is always switched on, a path from the terminal V DD , the switching element  202   k  to the terminal V CC  is established, and V CC  has a substantially same potential to VDD. 
         [0077]    In mode 2, switching of the above-described two states are repeatedly performed in accordance with the switching timings of the clock signals CLK 1  to CLK 4 . Thus, a positive voltage having can be generated between the terminal of the ground voltage GND and the terminal V CC , such that the positive voltage has the same polarity with the input power-supply voltage V DD  and has a substantially same level with the voltage which has an approximately same value. Furthermore, a negative voltage can be generated between the terminal of the ground voltage GND and the terminal V EE , such that the negative voltage has the opposite polarity with the input power-supply voltage V DD  and has a substantially same level with the voltage which has an approximately same value. In this situation, the capacitor  201   a  and the capacitor  201   b  complementarily operate. Therefore, in the present embodiment, it is possible to provide the charge pump circuit  4  having a greater capability of supplying current than that of the conventional charge pump circuit shown in  FIG. 11 . 
         [0078]    Moreover, each state is successively repeated in the above-described mode 1 and mode 2. Accordingly, in the charge pump circuit  4  according to the present embodiment, the positive output power-supply voltage V CC  and the negative output power-supply voltage V EE  are generated. In particular, the positive output power-supply voltage V CC  and the negative output power-supply voltage V EE  in mode 1 and the negative output power-supply voltage V EE  in mode 2 repeat minute fluctuations in a voltage region where rises and drops are balanced. However, minute fluctuations of the generated positive output power-supply voltage V CC  and the negative output power-supply voltage V EE  can be absorbed by providing the capacitors  201   a  to  201   c  each having an appropriate capacitance value in the charge pump circuit  4 . 
         [0079]    Specifically, the appropriate capacitance values of the capacitors  201   a  to  201   c  are determined depending on the magnitude or the like of the load  6  to be driven by the charge pump circuit  4 . Generally, 0.01 μF-100 μF, preferably, 0.1 μF-10 μF, and more preferably, approximately 1 μF. 
         [0080]    The amplifier circuit  5  illustrated in  FIG. 1  is driven by a power supply for outputting the positive output power-supply voltage V CC  generated and supplied by the charge pump circuit  4  and by the negative power supply for outputting the negative output power-supply voltage V EE . When the amplifier circuit  5  is driven, the amplifier circuit  5  inverts and amplifies the input signal S IN  with the level adjusting voltage V r  set as a center, and outputs the output signal S OUT  with the ground voltage (0 V) set as a center. With this configuration, the output signal S OUT  is output over an upper and lower voltage range of the ground voltage, so that the load  6  can be driven sufficiently. 
         [0081]    The mode detecting circuit  7  detects the positive output power-supply voltage V CC , the negative output power-supply voltage V EE , and the output signal S OUT , and outputs the mode determining signal M for determining whether the charge pump circuit  4  operates in mode 1 or in mode 2 to the switch controlling circuit  3 . 
         [0082]      FIG. 7A  is a view illustrative of a configuration of the mode detecting circuit  7  illustrated in  FIG. 1  in more detail. The mode detecting circuit  7  is provided with: subtracting circuits  701   a  and  701   b;  comparator circuits  702   a  and  702   b ; and an OR circuit  703 . Then, the subtracting circuit  701   a  detects a differential voltage between the positive output power-supply voltage V CC  and the output signal S OUT  from the amplifier circuit  5 . In addition, the subtracting circuit  701   b  detects a differential voltage between the output signal S OUT  and the negative output power-supply voltage V EE . Furthermore, by use of the comparator circuits  702   a  and  702   b , the values of the differential voltages are respectively compared with a preset reference voltage. 
         [0083]    The OR circuit  703  carries out an operation on two comparison results detected by the comparator circuits  702   a  and  702   b,  and switches the mode determining signal M from a low level to a high level when either of the differential voltages becomes lower than a preset reference voltage.  FIG. 7B  illustrates relationships between the negative output power-supply voltage V EE , the positive output power-supply voltage V CC , and the output signal S OUT  from the amplifier circuit  5 , in the mode detecting circuit  7 . In the example illustrated in  FIG. 7B , the negative output power-supply voltage V EE , the positive output power-supply voltage V CC , and the output signal S OUT  are compared with the reference voltage. However, it is possible to directly compare the voltage of the output signal S OUT  with the reference voltage. 
         [0084]      FIG. 8A  is a view illustrative of a configuration of the mode detecting circuit  7  in the above case in more detail. The mode detecting circuit  7  is provided with: subtracting circuits  801   a  and  801   b;  comparator circuits  802   a  and  802   b ; and an OR circuit  803 . Then, the subtracting circuit  801   a  detects the differential voltage between the ground voltage GND and the output signal S OUT  from the amplifier circuit  5 . In addition, the subtracting circuit  801   b  detects the differential voltage between the output signal S OUT  and the ground voltage GND. Furthermore, by use of the comparator circuits  802   a  and  802   b,  the respective differential voltages are compared with a preset reference voltage. 
         [0085]    The OR circuit  803  carries out an operation on two comparison results detected by the comparator circuits  802   a  and  802   b,  and switches the mode determining signal M from a low level to a high level when either of the differential voltages becomes lower than a preset reference voltage.  FIG. 8B  illustrates relationships between the ground voltage GND and the output signal S OUT  from the amplifier circuit  5 , in the mode detecting circuit  7 . In the present embodiment, at least the charge pump circuit  4  out of the charge pump circuit  4  and the amplifier circuit  5 , as described above, can be configured as a semiconductor integrated circuit that is integrated on a semiconductor substrate by use of MOS transistors. 
         [0086]    (Load Driving System) 
         [0087]    Next, operations of the load driving system  1  according to the present embodiment will be described more specifically. 
         [0088]    The mode detecting circuit  7  detects the positive output power-supply voltage V CC , the negative output power-supply voltage V EE , and the output signal S OUT , and makes the charge pump circuit  4  operate in mode 1 in a range where the amplitude of the output signal S OUT  is small and the charge pump circuit  4  can operate in mode 1 without a problem. On the other hand, the mode detecting circuit  7  makes the charge pump circuit  4  operate in mode 2 in a range where the charge pump circuit  4  has a problem in operating in mode 1, such as in a case where the output signal S OUT  is subject to clipping or the like. 
         [0089]    In such operations, the charge pump circuit  4  according to the present embodiment automatically switches between mode 1 and mode 2 in accordance with the state of the output signal S OUT . Then, the positive output power-supply voltage V CC  and the negative output power-supply voltage V EE  generated in the charge pump circuit  4  timely change as illustrated in  FIG. 9 , so that they can output the output signal S OUT  without a problem. 
         [0090]      FIG. 10  is a view illustrative of relationships between magnitude of the output signal S OUT  and current I DD  consumed by the load driving system  1 . A driven circuit operates in a voltage range of V DD  that is the input power-supply voltage in mode 1, whereas it operates in a voltage range of 2 V DD  in mode 2. Therefore, in mode 1, only a half the current consumed in mode 2 is consumed. This is because the output current of 21 is made available from the input current of I, by converting the input power of V DD ×I in mode 1 into the power of ½ V DD ×2I. That is to say, in mode 1, the power consumption of the load driving system  1  can be cut in half. Accordingly, in the present embodiment, by operating the load driving system  1  in mode 1 as much as possible in the range where the load driving system  1  can operate without a problem, it is possible to reduce the power consumption of the load driving system  1 . 
         [0091]    In addition, the above embodiment is a proffered embodiment of the present invention. Technically preferable various limitations have been set, but the scope of the present invention is not limited thereto, unless there is a specific description of limiting the present invention. Furthermore, in the drawings described in the above description, for convenience of drawings, reduction scales in horizontal and vertical sizes of members and parts are different from the actual ones. 
         [0092]    Moreover, the present invention is not limited to the above-described embodiment, and it is to be understood that variations, modifications, and the like may occur within the scope where an object of the present invention is achievable. 
       INDUSTRIAL AVAILABILITY 
       [0093]    The present invention is adaptable to any type of charge pump circuit and a semiconductor circuit for driving the charge pump circuit, as far as the charge pump circuit supplies the power to a load by driving a driven circuit and has a configuration for which the reduction in power consumption is desired. 
       REFERENCE SIGNS LIST 
       [0000]    
       
           201   a - 201   c  capacitors 
           202   a - 202   k  switching elements 
           1  load dicing system 
           2  clock generating circuit 
           3  switch controlling circuit 
           4  charge pump circuit 
           5  amplifier circuit 
           6  load 
           7  mode detecting circuit 
           701   a,    701   b,    801   a,    801   b  subtracting circuits 
           702   a,    702   b,    802   a,    802   b  comparator circuits 
           703 ,  803  OR circuits