Abstract:
On a surface of a semiconductor substrate, an epitaxial layer of a conductivity type opposite to a conductivity type of the semiconductor substrate is formed, trenches are formed in portions other than a portion serving as a resistor, and the trenches are filled with an insulating film to three-dimensionally form U-shaped resistors which are separated from each other.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device, and more particularly, to a resistor with which high integration of the semiconductor device can be obtained and a method of manufacturing the same. 
         [0003]    2. Description of the Related Art 
         [0004]    In recent years, along with the progress in miniaturization and integration of a semiconductor device, various attempts have been made to form a number of semiconductor elements in a small area of a semiconductor chip. As the semiconductor device formed with those semiconductor elements, there is a semiconductor device provided with a ladder circuit which divides a voltage. 
         [0005]    In the miniaturization and integration of the semiconductor device, it is extremely important to form the ladder circuit in a small area. 
         [0006]    Conventionally, in order to miniaturize the ladder circuit, an insulating film is formed on a first resistor formed on a field region, a second resistor is formed on the insulating film to make the resistors into a two layer structure, and thus miniaturization and integration of the ladder circuit are attained. In a semiconductor device including such a ladder circuit, as shown in  FIG. 2 , in a field region of a semiconductor substrate  75 , a first layer resistor  77  and a second layer resistor  66  are formed into a two layer structure via an interlayer insulating film  78  in a thickness direction of the semiconductor substrate  75  (for example, see JP 09-51072 A, JP 06-140573 A, and JP 2003-314296 A). 
         [0007]    However, in the case of adopting the resistors having the two layer structure, there arise problems in that the manufacturing steps are complicated and the manufacturing cost increases, and also in that it is difficult to obtain specific accuracy equal to or more than specific accuracy of the ladder circuit formed of the resistors which are formed above the conventional field region. Conventionally, the resistors are formed only on the field region to be two-dimensionally arranged. Accordingly, when the resistors are formed in the semiconductor device, an area obtained by adding an area where the semiconductor element is formed and an area where the resistors are formed is necessary on the semiconductor substrate. Therefore, if the resistors can be three-dimensionally arranged, an area of the entire semiconductor device can be reduced, which leads to further progress in miniaturization and integration of the semiconductor chip. 
         [0008]    Thus, a first object of the present invention is to provide a semiconductor device in which a breeder resistance circuit can be miniaturized and integrated. In addition, a second object of the present invention is to provide a method of manufacturing the semiconductor device which can be miniaturized and integrated. 
       SUMMARY OF THE INVENTION 
       [0009]    In order to achieve the aforementioned objects, the present invention employs the following means. 
         [0010]    (1) A semiconductor device according to the present invention includes: a first conductivity type semiconductor substrate; two types of trenches having different depths, the two types of trenches being arranged so that a second conductivity type epitaxial layer which is formed on the first conductivity type semiconductor substrate and has a conductivity type opposite to a conductivity type of the first conductivity type semiconductor substrate serves as a resistor having a substantially three-dimensional U-shaped contour; an insulating film for electrically insulating a plurality of the resistors formed by the two types of trenches from each other; and a second conductivity type heavily-doped region in which a concentration of an impurity is increased to obtain contact with a metal wire arranged at both ends of the resistors. 
         [0011]    (2) A method of manufacturing a semiconductor device according to the present invention includes: forming, on a first conductivity type semiconductor substrate, a second conductivity type epitaxial layer having a conductivity type opposite to a conductivity type of the first conductivity type semiconductor substrate; providing two types of trenches having different depths in a portion other than a portion serving as a resistor of the second conductivity type epitaxial layer; arranging an insulating film for electrically insulating a plurality of the resistors formed by the two types of trenches from each other; and forming a second conductivity type heavily-doped region in which a concentration of an impurity is increased so that sufficient contact can be obtained with the second conductivity type epitaxial layer in the portion serving as the resistor and a metal wire. 
         [0012]    According to the present invention, the resistor forming the breeder resistance circuit or the like can be three-dimensionally arranged. This leads to effects that the semiconductor device can be integrated, and that the breeder resistance circuit can be formed in an area smaller than an occupying area thereof in a conventional method. 
         [0013]    In a voltage detector or a voltage regulator according to the present invention, because voltage can be divided with high accuracy in an area smaller than a conventional chip area, a production yield as an integrated circuit (IC) is improved, which makes it possible to manufacture an inexpensive product more accurately. Further, in order to suppress current consumption of the IC, a resistance value of the entire breeder resistance circuit is set to a high level, which is equal to or more than the order of megohms in many cases. In this case, resistors having an extremely slender shape are combined for keeping a certain degree of accuracy, and thus a large area is required. Therefore, it is not uncommon that more than half of the entire area of the IC chip is taken up by the breeder resistance circuit in the voltage detector. The breeder resistance circuit according to the present invention can have a three-dimensional arrangement, with the result that a certain degree of accuracy can be obtained in a small area. Accordingly, an occupying area of the breeder resistance circuit can be reduced, which greatly contributes to reducing an area of the entire IC chip. 
         [0014]    Employment of the method of manufacturing a semiconductor device according to the present invention leads to an effect that the semiconductor device described above can be formed without involving a special manufacturing step or significantly increasing manufacturing steps. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    In the accompanying drawings: 
           [0016]      FIGS. 1A and 1B  are schematic sectional views showing a trench-shaped resistor of a semiconductor device according to a first embodiment of the present invention; and 
           [0017]      FIG. 2  is a sectional view of a portion in which a resistor is formed into two layers in a conventional field region. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0018]    Hereinafter, a preferred embodiment of the present invention is described with reference to the drawings. 
         [0019]      FIGS. 1A and 1B  are schematic sectional views showing a resistor of a semiconductor device according to a first embodiment of the present invention. 
         [0020]      FIG. 1B  is a view showing the semiconductor device of  FIG. 1A , which is viewed from above.  FIG. 1A  is a sectional view of  FIG. 1B , which is taken along a line A-A′ of  FIG. 1B . 
         [0021]    A p-type epitaxial layer  202  is formed on an n-type silicon semiconductor substrate  201 , and two types of trenches  205  and  206  having different depths are formed in a portion of the p-type epitaxial layer  202 , which is not a resistor. The depth of the trench  205  is less than a full depth of the p-type epitaxial layer  202 , and there remains the p-type epitaxial layer  202  on a bottom of the trench  205 . The depth of the trench  206  is deeper than the depth of the trench  205 , and the trench  206  reaches the n-type silicon semiconductor substrate  201  located under the p-type epitaxial layer  202  and divides the p-type epitaxial layers  202  adjacent to each other. Further, the trenches  205  and  206  are filled with an insulating film  203  for electrically insulating resistors, and an epitaxial layer  207  which becomes a resistor is provided with p-type heavily-doped regions  204  whose impurity concentration is increased so as to have sufficient contact with an aluminum wire. The p-type epitaxial layer  202  which becomes a resistor has a three-dimensional U-shape. Note that the n-type silicon semiconductor substrate does not always need to be used, and an n-type epitaxial layer may be formed using a p-type silicon semiconductor substrate to form the resistor. The p-type heavily-doped region  204  is formed of BF 2 , and an impurity concentration during the formation is 1E15 atm/cm 3 . 
         [0022]    Note that BF 2  does not always need to be used, and B may be used. The impurity concentration during the formation does not always need to be 1E15 atm/cm 3 , and if equal to or more than 1E15 atm/cm 3 , sufficient contact can be obtained. 
         [0023]    The trench includes the first trench  205  and the second trench  206 . The second trench  206  is formed to electrically insulate the adjacent resistors from each other, while the first trench  205  is formed to three-dimensionally arrange the resistor. Depending on the depth of the first trench  205 , a thickness and a length of the resistor can be varied with ease, whereby the resistor can be easily set to have an appropriate resistance value. 
         [0024]    When the p-type epitaxial layer  202  has a thickness ranging from 0.1 μm to 10 μm, and more preferably from 0.5 μm to 5.0 μm, the resistor with high specific accuracy can be formed, and thus the aforementioned first object can be achieved. 
         [0025]    If the thickness of the p-type epitaxial layer  202  is thin, the resistor with a large resistance value cannot be formed in a small area, and thus the thickness of the epitaxial layer may be equal to or more than 0.1 μm, and preferably equal to or more than 0.5 μm. Meanwhile, when the thickness thereof is large, processing accuracy of the trench decreases, and the stable resistance value cannot be obtained. In particular, sufficient characteristics cannot be obtained in a circuit such as a breeder resistance circuit, in which high specific accuracy is required, and thus the thickness of the epitaxial layer  202  may be equal to or less than 10 μm, and preferably equal to or less than 5.0 μm. 
         [0026]    Further, a specific resistance of the p-type epitaxial layer  202  is set to 0.01 to 150 Ωcm, and preferably 1 to 50 Ωcm. The first object is attained with the configuration described above. 
         [0027]    If the specific resistance of the epitaxial layer is extremely small, the resistor with a large resistance value cannot be formed in a small area, and thus the specific resistance thereof may be set to equal to or more than 0.01 Ωcm, and preferably equal to or more than 1 Ωcm. Meanwhile, extremely large specific resistance causes large variations in the resistance value, whereby a stable resistance value cannot be obtained. In particular, the sufficient characteristics cannot be obtained in the circuit such as the breeder resistance circuit, in which high specific accuracy is required, and hence the specific resistance of the epitaxial layer may be set to equal to or less than 150 Ωcm, and more preferably equal to or less than 50 Ωcm.