Abstract:
A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.

Description:
REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is continuation of U.S. patent application Ser. No. 13/403,454, filed Feb. 23, 2012, now U.S. Pat. No. 8,441,849, which is a continuation of U.S. patent application Ser. No. 12/551,548, filed Aug. 31, 2009, now U.S. Pat. No. 8,125,822, each of which is incorporated by reference herein in its entirety for all purposes. 
         [0002]    The present application is related to the following patent applications, which are hereby incorporated by reference herein in their entirety for all purposes: 
         [0003]    U.S. patent application Ser. No. 12/551,546, filed Aug. 31, 2009, now U.S. Pat. No. 8,040,721; and 
         [0004]    U.S. patent application Ser. No. 12/551,553, filed Aug. 31, 2009, and titled “FLEXIBLE MULTI-PULSE SET OPERATION FOR PHASE-CHANGE MEMORIES.” 
     
    
     BACKGROUND 
       [0005]    The present invention relates generally to integrated circuits containing memory arrays, and more particularly, to reducing the programming time of memory cells of such arrays. 
         [0006]    Conventionally, memory performance is affected by the need to limit the amount of current used to program memory cells. If too much current is applied to a memory cell, the memory cell may be damaged. However, limiting the amount of current used to program the memory cell increases the amount of time needed to program the cell. Thus, what are needed are methods and apparatus for quickly programming memory cells without risking damage to the memory cells. 
       SUMMARY 
       [0007]    In a first aspect of the invention, a method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. 
         [0008]    In a second aspect of the invention, apparatus are provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. The apparatus includes a control circuit coupled to the word line, and a sense amplifier coupled to the bit line. During a first predetermined time interval, the control circuit is adapted to switch the word line from a first standby voltage to a first voltage, the sense amplifier is adapted to charge the bit line from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the control circuit is adapted to switch the word line from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. 
         [0009]    In a third aspect of the invention, a memory array is provides that includes a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. The memory array includes a control circuit coupled to the word line, and a sense amplifier coupled to the bit line. During a first predetermined time interval, the control circuit is adapted to switch the word line from a first standby voltage to a first voltage, the sense amplifier is adapted to charge the bit line from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the control circuit is adapted to switch the word line from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. 
         [0010]    Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0011]      FIG. 1  is a schematic representation of an electronic device according to an embodiment of the present invention. 
           [0012]      FIG. 2A  is a schematic representation of a memory array, such as the memory array of  FIG. 1 . 
           [0013]      FIG. 2B  is a schematic representation of a sense amplifier, such as the sense amplifier of  FIG. 2A . 
           [0014]      FIG. 3  is a flowchart of an exemplary method of programming a memory cell according to an embodiment of the present invention. 
           [0015]      FIG. 4  is a schematic representation of voltages of a bit line and a word line according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures. 
         [0017]    As used herein, the terms “a,” “an” and “the” may refer to one or more than one of an item. The terms “and” and “or” may be used in the conjunctive or disjunctive and will generally be understood to be equivalent to “and/or.” For brevity and clarity, a particular quantity of an item may be described or shown while the actual quantity of the item may differ. 
         [0018]    Initially, it should be noted that the term voltage should be broadly interpreted to include the phrase “programming energy.” 
         [0019]    In accordance with an embodiment of the present invention, voltages of both a bit line and a word line may be adjusted to program a memory cell. Voltages of the bit line and the word line may initially be at standby voltages. Voltages of a word line may switch between a first voltage and a second voltage. The first voltage (e.g., 3 volts) may be high enough relative to the voltage applied to the bit line (e.g., 8 volts), that a net voltage (e.g., 5 volts) may result that may be less than a voltage that may program the memory cell. That is, the first voltage may result in a safe voltage. Using the voltage of the word line to adjust the net voltage to be less than a voltage that may program the memory cell is counter-intuitive in that conventionally the voltage of the bit line is used to control the net voltage. The second voltage (e.g., 0 volts) may be low enough relative to the voltage applied to the bit line (e.g., 8 volts), that a net voltage (e.g., 8 volts) may result that is effective to program the memory cell (i.e., a programming voltage). Thus, by switching from the safe voltage to the programming voltage (e.g., instead of switching from the standby voltage to the programming voltage), a much smaller voltage change may be used during programming that does not require the current to be limited. 
         [0020]      FIG. 1  is a schematic representation of an electronic device  100  according to an embodiment of the present invention. The electronic device  100  may include an integrated circuit  102 . The integrated circuit  102  may include a memory array  104 . The memory array  104  may include a memory cell  106 . The memory cell  106  is shown as part of the memory array  104  which is shown as part of the integrated circuit  102  which is shown as part of the electronic device  100 . However, the electronic device  100  may otherwise access memory cells  106 . 
         [0021]    The electronic device  100  may include any of a variety of known or later-developed electronic devices that include or access memory cells  106 . For example and not by way of limitation, the electronic device  100  may include a flash drive, a digital audio player, or a portable computer. 
         [0022]      FIG. 2A  is a schematic representation of a memory array  200 , such as the memory array  104  of  FIG. 1 . The memory array  200  may include a memory cell  202 , a bit line  204 , a bit line driver  206 , a bit line select  208 , a sense amplifier  210 , a word line  220 , a word line driver  222 , a word line select  224 , a control circuit  226 , and a capacitor  230 . 
         [0023]    The memory cell  202  may be formed of any of a variety of known or later-developed materials. For example and not by way of limitation, the memory cell  202  may be formed of chalcogenide/PVM or chalcogenide-type materials. The memory cell  202  may be a two-terminal memory cell. The memory cell  202  may include an isolation unit. The isolation unit may include a diode including an anode and a cathode. The anode side may be sensed. The cathode side may be controlled. Alternatively, the anode side may be controlled, and the cathode side may be sensed. 
         [0024]    The memory cell  202  may be connected to the bit line  204 . The bit line  204  may be coupled to a terminal on the anode side of the memory cell  202 . That is, the bit line may be on the sensed side. The bit line  204  may be long relative to the word line  220 . The bit line  204  may be connected to the bit line driver  206 . The bit line driver  206  may be controlled by the bit line select  208 . When the bit line select  208  is enabled, it may connect the bit line  204  to the sense amplifier  210 . The bit line driver  206  may be enabled or disabled based on a charge of the capacitor  230 . 
         [0025]    The memory cell  202  may be connected to the word line  220 . The word line  220  may be coupled to a terminal on the cathode side of the memory cell  202 . That is, the word line may be on the side that is controlled. The word line  220  may be connected to the word line driver  222 . The word line driver  222  may be controlled by the word line select  224 . When the word line select  224  is enabled, it may connect the word line  220  to the control circuit  226 . The word line  220  may be shorted together with another word line so that word lines are shared. 
         [0026]    The sense amplifier  210  may be a write sense amplifier. As will be described further below, the sense amplifier  210  may control programming of the memory cell  202  in conjunction with the control circuit  226 . 
         [0027]    The control circuit  226  may include a dedicated regulator (e.g., a MUX). The control circuit  226  may control the amount of voltage applied to the word line  220 . The control circuit  226  may switch between two voltages. 
         [0028]    It should be noted that the word line and the bit line may be switched between more than two voltages, such as from standby voltages to, for example, a first voltage and to a second voltage. Examples of standby voltages are described in U.S. Pat. Nos. 6,822,903 and 6,963,504, both to Scheuerlein and Knall, and both entitled “APPARATUS AND METHOD FOR DISTURB-FREE PROGRAMMING OF PASSIVE ELEMENT MEMORY CELLS,” both of which are incorporated by reference herein in their entirety for all purposes. In these examples, first and second array lines may be driven to selected bias voltages. Then, the first and second array lines may be driven to unselected bias voltages. The timing of when the first and second array lines may be driven to selected bias voltages and when the first and second array lines may be driven to unselected bias voltages may be adjusted relative to one another (i.e., the first array line relative to the second array line), for example, to prevent unintended programming of cells located near target cells in an array. It should be appreciated that in the present disclosure, such standby voltages should not be confused with the first voltage (i.e., as discussed below, the voltage that, when coupled with the voltage applied to the bit line, results in a safe voltage). 
         [0029]    The first voltage (e.g., 3 volts) may be high enough that when coupled with voltage applied to the bit line  204  (e.g., 8 volts), may result in a net voltage (e.g., 5 volts) that may be less than a voltage that may program the memory cell  202 . That is, the first voltage may result in a safe voltage. The second voltage (e.g., 0 volts) may be low enough that when coupled with voltage applied to the bit line  204  (e.g., 8 volts), may result in a net voltage (e.g., 8 volts) effective to program the memory cell  202 . That is, the second voltage may result in a programming voltage. 
         [0030]    Alternatively, the control circuit  226  may include a diode connected NMOS device and a bypass path. The diode connected NMOS device may generate the first voltage (i.e., the safe voltage). The bypass path, when selected, may generate the second voltage (resulting in the programming voltage). 
         [0031]    The actual value of the first and second voltages may be determined based upon multiple considerations. One consideration may be that the difference between the two voltages should be sufficient to distinguish between programming and not programming. Another consideration may be that the smaller the difference between the two voltages is, the faster the programming of the memory cell  202  may be. 
         [0032]      FIG. 2B  is a schematic representation of a sense amplifier  250 , such as the sense amplifier  210  of  FIG. 2A . The sense amplifier  250  may be a write sense amplifier. The sense amplifier  250  may control programming of the memory cell  202  in conjunction with the control circuit  226 . The sense amplifier  250  may include a voltage  252 , a current limiter  254 , a node  256 , a pMOS  258 , and a voltage reference  260 . 
         [0033]    The voltage  252  may flow through the current limiter  254 , the node  256 , and the pMOS  258 . The current limit may limit to a predetermined amount (e.g., 1 microamp). The voltage  252  may be compared with the voltage reference  260 . Once the memory cell  202  programs, the voltage  252  flowing through the node  256  may fall. 
         [0034]    The operation of the memory array  200  is now described with reference to  FIGS. 3 and 4 , which illustrate, respectively, an exemplary method  300  of programming a memory cell  202 , and voltages  400  of a bit line  204  and a word line  220 . 
         [0035]    In operation  302 , the word line  220  may be set to a first voltage  406 . For example and not by limitation, the voltage of the word line  220  may be set to 3 volts. The word line select  224  may be enabled thereby connecting the word line  220  through the word line driver  222  to the control circuit  226 . 
         [0036]    In operation  304 , the bit line  204  may be charged from an initial level  402  to a predetermined voltage  404 . For example and not by limitation, the bit line  204  may be charged from an initial level of 0 volts to a predetermined voltage of 8 volts. The bit line  204  may be charged from the initial level  402  to the predetermined voltage  404  quickly and without limitation. The bit line select  208  may be enabled thereby connecting the bit line  204  through the bit line driver  206  to the sense amplifier  210 . 
         [0037]    The first voltage  406  of the word line (e.g., 3 volts) may be high enough that relative to the predetermined voltage  404  of the bit line  204  (e.g., 8 volts), a net voltage difference results (e.g., 5 volts) that may be less than a voltage needed to program the memory cell  202 . That is, the first voltage  406  may result in a safe voltage. 
         [0038]    In operation  306 , the word line  220  may be switched from the first voltage  406  to a second voltage  408 . The second voltage (e.g., 0 volts) may be low enough that relative to the predetermined voltage  404  applied to the bit line  204  (e.g., 8 volts), a net voltage difference (e.g., 8 volts) may result that is effective to program the memory cell  202 . That is, the second voltage  408  may result in a programming voltage. The control circuit  226  may switch between the first voltage  406  and the second voltage  408 . 
         [0039]    As noted above, the bit line  204  may be long relative to the word line  220 . Thus, the switching of the word line  220  may be faster than if the bit line were switched or otherwise controlled. 
         [0040]    The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above-disclosed embodiments of the present invention of which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. 
         [0041]    Accordingly, while the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention as defined by the following claims.