Abstract:
A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.

Description:
FIELD OF THE DISCLOSURE 
       [0001]    The present disclosure relates generally to radio frequency (RF) receivers, and more particularly to signal processors for RF receivers. 
       BACKGROUND 
       [0002]    Radio frequency (RF) receivers are used in a wide variety of applications such as television receivers, cellular telephones, pagers, global positioning system (GPS) receivers, cable modems, cordless phones, satellite radio receivers, and the like. One common type of RF receiver is the so-called superheterodyne receiver. A superheterodyne receiver mixes the desired data-carrying signal with the output of tunable oscillator to produce an output at a generally fixed intermediate frequency (IF). The fixed IF signal can then be conveniently filtered and converted down to baseband for further processing. Thus a superheterodyne receiver requires two mixing steps. 
         [0003]    Traditionally, certain RF receivers have adopted standard IFs. For example a television receiver translates a selected channel in the band of 48 MHz to 870 MHz to a standard IF of 44 MHz. Within the United States, FM radios typically translate FM audio signals, which are broadcast in 200 KHz channels in the frequency band from 88.1 MHz to 107.9 MHz, to a standard IF of 10.7 MHz. More recently, RF receivers have adopted low intermediate frequency (LIF) and zero intermediate frequency (ZIF) architectures to take advantage of processing capabilities of modern digital signal processors (DSPs). 
         [0004]    Moreover high quality RF receivers use automatic gain control (AGC) circuits to adjust the gain or attenuation of various elements in the receiver in order to regulate the power levels. For example, a television signal with low input power can be amplified to increase the signal strength for further processing. In another example, a filtered signal may be too powerful for a following component, and so the filtered signal is attenuated to decrease the power level. Without such AGC circuits, the quality of the received desired signal would be reduced. For instance, the displayed image of a television signal would get dimmer as the power level dropped and eventually would start showing an increasing level of background noise. Conversely, the displayed image would be brighter as the power level rose and eventually would show image artifacts due to the system&#39;s non-linearities, like beat frequency waves or images in the background of the desired image. 
         [0005]    Terrestrial and cable television transmission environments make AGC difficult due to the presence of blockers. A blocker is an unwanted channel with significant signal energy whose frequency is close to the desired channel frequency and thus is difficult to filter out. Since the blocker is not easily filtered, it can degrade the signal quality of the desired channel. Filtering out the undesirable energy of a blocker is especially difficult when the receiver uses an LIF or ZIF architecture because television transmission systems use many closely spaced channels. 
         [0006]    Moreover the strongest blocker will sometimes be adjacent in frequency to the desired channel, and at other times be more remote in frequency. Also the blocker may have a much larger signal strength than the desired channel, and the signal strength can vary over time, for example, when a moving receiver passes into a tunnel or behind a building, or an obstruction, such as an airplane, passes between the transmitter and the receiver. These factors make AGC in LIF or ZIF signal processors especially difficult. 
         [0007]    What is needed, then, are new analog baseband processor architectures for applications such as television receivers with AGC suitable for use in the presence of strong blockers and which are also suitable for LIF and ZIF architectures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: 
           [0009]      FIG. 1  illustrates in block diagram form an integrated circuit television receiver according to an embodiment of the present invention; 
           [0010]      FIG. 2  illustrates in block diagram form an analog baseband processor suitable for use as one of the analog processors of  FIG. 1 . 
           [0011]      FIG. 3  illustrates in graphical form a set of graphs useful in understanding the operation of the analog baseband processor of  FIG. 2  in the presence of a strong adjacent channel blocker. 
           [0012]      FIG. 4  illustrates in graphical form a set of graphs useful in understanding the operation of analog baseband processor of  FIG. 2  in the presence of a strong remote channel blocker. 
           [0013]      FIG. 5  illustrates in block diagram form a programmable gain amplifier with analog direct current (DC) offset correction known in the prior art. 
           [0014]      FIG. 6  illustrates in block diagram form a signal processor with offset correction suitable for use as one of the analog baseband processors of  FIG. 1  according to another aspect of the present invention. 
           [0015]      FIG. 7  illustrates a circuit model of a portion of the analog baseband processor of  FIG. 6  useful in understanding the calibration operation. 
           [0016]      FIG. 8  illustrates a circuit model of a portion of an analog baseband processor according to another embodiment of the present invention. 
       
    
    
       [0017]    The use of the same reference symbols in different drawings indicates similar or identical items. 
       DETAILED DESCRIPTION 
       [0018]      FIG. 1  illustrates in block diagram form an integrated circuit television receiver  100  according to an embodiment of the present invention. Receiver  100  includes generally a low noise amplifier (LNA)  110 , a bandpass filter  120 , an attenuator  130 , a lowpass filter  140 , a mixing circuit  150 , an analog baseband processor  160  for the in-phase (I) path, an analog baseband processor  170  for the quadrature (Q) path, a demodulator  180 , and a controller  190 . LNA  110  has an input for receiving a radio frequency (RF) input signal labeled “RF IN ”, a control input for receiving a gain control signal, and an output. While  FIG. 1  depicts a television receiver, it is applicable to other RF systems. In general a “radio frequency” signal means an electrical signal conveying useful information and having a frequency from about 3 kilohertz (kHz) to hundreds of gigahertz (GHz), regardless of the medium through which such signal is conveyed. Thus an RF signal may be transmitted through air, free space, coaxial cable, fiber optic cable, etc. Tracking bandpass filter  120  has a first input connected to the output of LNA  110 , a second input for receiving a tuning signal, and an output. Attenuator  130  has a first input connected to the output of tracking bandpass filter  120 , a second input for receiving an attenuation control signal, and an output. Filter  140  has a first input connected to the output of attenuator  130 , a second input for receiving a cutoff frequency adjustment signal, and an output. 
         [0019]    Mixing circuit  150  includes a local oscillator  152  and a mixer  154 . Local oscillator  152  has an input for receiving a local oscillator tuning signal, and an output for providing two signals, including an in-phase mixing signal and a quadrature mixing signal. Mixer  154  has a first input connected to the output of filter  140 , a second input connected to the output of local oscillator  152 , a first output for providing an in-phase intermediate frequency (IF) signal labeled “I”, and a second output for providing a quadrature IF signal labeled “Q”. 
         [0020]    Analog baseband processor  160  has a signal input connected to the output of mixer  152  for receiving signal I, a control input/output terminal, and an output. Analog baseband processor  170  has a signal input connected to the output of mixer  152  for receiving signal Q, a control input/output terminal, and an output. Demodulator  180  has a first input connected to the output of analog baseband processor  160 , a second input connected to the output of analog baseband processor  170 , and an output for providing a demodulated baseband television signal labeled “TV OUT ”. 
         [0021]    Controller  190  includes a microcontroller (MCU)  192  and firmware  194 . MCU  190  has a first input/output terminal connected to the control input/output terminal of analog baseband processor  160 , a second input/output terminal connected to the control input/output terminal of analog processor  170 , and a bidirectional memory interface terminal between it and firmware  194 . MCU  192  has outputs for controlling LNA  110 , filter  120 , attenuator  130 , filter  140 , and local oscillator  152 . MCU  192  also has other inputs and outputs not important in understanding the relevant operation of receiver  100  and which are not shown in  FIG. 1 . 
         [0022]    Generally, receiver  100  functions as a television receiver adapted to receive and demodulate television channels from sources including broadcast and cable television. MCU  192  is adapted to control the various elements in receiver  100  according to the channel selected by the user and under the control of a program stored in firmware  194 . 
         [0023]    Receiver  100  uses a dual-filter architecture for the pre-mixing tuner. Signal RF IN  is received and amplified as necessary in LNA  110  under the control of MCU  192 . Receiver  100  is thus able to present a signal to the input of tracking bandpass filter  120  at a suitable level. Tracking bandpass filter  120  is a second-order LC filter that assists in providing rejection for strong interferers (or blockers) by filtering neighboring channels. The center frequency of the passband of tracking bandpass filter  120  is set by MCU  192  according to the selected channel. 
         [0024]    Attenuator  130  functions as a separately controllable gain element under the control of MCU  192  such that MCU  192  can appropriately divide the gain or attenuation between different portions of the signal processing path. Filter  140  provides additional attenuation above the third harmonic of the mixing signal under the control of MCU  192  to prevent unwanted energy from a neighboring channel from being mixed into the passband. This third harmonic frequency is important because local oscillator  154  uses a digital mixing signal that is a square wave, which therefore has significant energy at its third harmonic. 
         [0025]    Mixer  154  is a quadrature mixer that mixes the filtered and attenuated RF input signal with the signal from local oscillator  152  to mix a selected channel to a desired IF. In receiver  100 , the desired IF is selectable in the range of 3 to 5 megahertz (MHz), and thus receiver  100  is configurable as a low-IF (LIF) receiver. Additionally, receiver  100  is also configurable as a direct down conversion receiver or zero IF (ZIF) receiver. Local oscillator  152  is tuned to a frequency that mixes the selected channel to the desired IF, under the control of MCU  192 . Receiver  100  is also configurable to be compatible with various television standards around the world that have somewhat different channel and spectral characteristics. 
         [0026]    Each of analog baseband processors  160  and  170  is a signal processor that performs signal conditioning, including lowpass filtering to pass signals below a cutoff frequency of between 6 and 9 MHz for LIF configurations, and further gain stages under the control of MCU  192 . Note that as used herein, signal processors  160  and  170  are considered to be “baseband” in the sense that they support either LIF or ZIF. Analog baseband processors  160  and  170  convert the analog signals so processed to the digital domain, such that demodulator  180  can demodulate them digitally to provide signal TV OUT . 
         [0027]      FIG. 2  illustrates in block diagram form an analog baseband processor  200  suitable for use as either analog baseband processor  160  or analog baseband processor  170  of  FIG. 1 . Analog baseband processor  200  includes generally a lowpass filter  210 , a first automatic gain control (AGC) loop  220 , a lowpass filter  230 , a second AGC loop  240 , a lowpass filter  250 , and an ADC  260 . Lowpass filter  210  has an input for receiving an input signal labeled “IF IN ”, and an output. AGC loop  220  has an input connected to the output of lowpass filter  210 , and an output. Lowpass filter  230  has an input connected to the output of AGC loop  220 , and an output. AGC loop  240  has an input connected to the output of lowpass filter  230 , and an output. Lowpass filter  250  has an input connected to the output of AGC loop  240 , and an output. ADC  260  has an input connected to the output of lowpass filter  250 , and an output for providing a digital output signal labeled “DIGITAL OUTPUT”. 
         [0028]    AGC loop  220  includes a programmable gain amplifier (PGA)  222 , a peak detector  224 , and a controller  226 . PGA  222  has an input connected to the output of lowpass filter  210 , a control input, and an output connected to the input of lowpass filter  230 . Peak detector  224  has an input connected to the output of PGA  222 , and an output. Controller  226  has an input connected to the output of peak detector  224 , and an output connected to the control input of PGA  222 . AGC loop  240  includes a PGA  242 , a peak detector  244 , and a controller  246 . PGA  242  has an input connected to the output of lowpass filter  230 , a control input, and an output connected to the input of lowpass filter  250 . Peak detector  244  has an input connected to the output of PGA  242 , and an output. Controller  246  has an input connected to the output of peak detector  244 , and an output connected to the control input of PGA  242 . Controllers  226  and  246  are implemented by MCU  192  under the control of firmware  194  as illustrated previously in  FIG. 1 . 
         [0029]    In general, analog baseband processor  200  provides filtering to attenuate significant channel blockers while effectively utilizing the available dynamic range of ADC  260 . Analog baseband processor  200  implements distributed independent gain control and distributed filtering that allows it to accommodate varying television reception environments while avoiding the need for extremely aggressive filtering associated with conventional designs. In the illustrated embodiment, analog baseband processor  200  implements a distributed fifth-order lowpass filter, realizing two of the poles using simple passive resistor-capacitor (RC) filters, and only three of the poles using active elements. In particular, lowpass filter  210  combines a first-order passive RC stage followed by a first-order active lowpass filter. The active filter portion injects a fixed amount of gain, about 8 decibels (dB) in the contemplated embodiment. Lowpass filter  230  uses an active biquadratic (biquad) filter to provide two additional poles. Finally lowpass filter  250  uses another first-order passive RC filter. 
         [0030]    In this embodiment, to accommodate both LIF and ZIF architectures, the corner frequency of the distributed lowpass filter can be altered to points between 3-9 MHz in 250 kHz steps. The corner frequency is set by adjusting digitally tunable capacitor banks that implement filter capacitors. In LIF mode, the IF can be set anywhere between 3 MHz and 5 MHz. In the contemplated embodiment, analog baseband processors  160  and  170  also include on-chip calibration circuits for calibrating RC time constants associated with filter poles. 
         [0031]    Moreover in this embodiment, each PGA has a gain range of 18 decibels (dB) with 0.5 dB steps each having a relative gain accuracy of 0.025 dB. 
         [0032]    The advantages of distributed filtering and gain control with independent AGC loops can be better understood with reference to  FIGS. 3 and 4 .  FIG. 3  illustrates in graphical form a set of graphs  300  useful in understanding the operation of analog baseband processor  200  of  FIG. 2  in the presence of a strong adjacent channel blocker. To aid understanding, analog baseband processor  200  of  FIG. 2  is also reproduced below the graphs. Graphs  300  include six graphs  310 - 360 . In each graph the horizontal axis represents frequency in hertz (Hz) and the vertical axis represents amplitude in volts. Each graph illustrates the signal level of the desired signal  312 - 362 , respectively, and of the blocker  314 - 364 , respectively, at various nodes in analog baseband processor  200  as indicated in  FIG. 3 . As shown in graph  310 , the signal at the input of lowpass filter  210  includes desired signal  312  and blocker  314  both having amplitudes less than a target signal level. The target signal level is an analog level corresponding to the dynamic range of ADC  260 . Lowpass filter  210  attenuates the blocker as shown in graph  320  to make the signal level of desired signal  322  closer to that of blocker  324 . AGC loop  220  increases the signal levels of both the desired signal and the blocker until the gain is sufficient to increase the strongest signal of the two, in this case blocker  334 , to the target signal level. Subsequently lowpass filter  330  decreases the signal level of the blocker and, as shown in  FIG. 3 , the amplitude of desired signal  342  becomes higher than that of blocker  344 . AGC loop  240  increases the signal levels of both the desired signal and the blocker but now uses the signal level of desired signal  342  to determine the gain. Finally lowpass filter  250  decreases the signal level of the blocker while maintaining the level of desired signal  362 , which remains at the target level at the input of ADC  260 . Thus the operation of analog baseband processor  200  in the presence of a strong adjacent blocker causes PGA  222  to have low gain and PGA  242  to have high gain. 
         [0033]      FIG. 4  illustrates in graphical form a set of graphs  400  useful in understanding the operation of analog baseband processor  200  of  FIG. 2  in the presence of a strong remote channel blocker. As in  FIG. 3 , analog baseband processor  200  of  FIG. 2  is again reproduced. Graphs  400  include six graphs  410 - 460 . In each graph the horizontal axis represents frequency in hertz (Hz) and the vertical axis represents amplitude in volts. Each graph illustrates the signal level of the desired signal  412 - 462 , respectively, and of the blocker  414 - 464 , respectively. As shown in graph  410 , the signal at the input of lowpass filter  210  includes the desired signal  412  and the blocker  414  both having amplitudes less than the target signal level. Lowpass filter  210  attenuates the blocker as shown in graph  420  to make the signal level of desired signal  422  closer to that of blocker  424 . Note that the attenuation of blocker  424  is relatively greater since the blocker is farther away in frequency. AGC loop  220  increases the signal levels of both the desired signal and the blocker until the gain is sufficient to increase the strongest signal of the two, in this case desired signal  432 , to the target level. In the example of  FIG. 4 , the desired signal has an amplitude much smaller than the target level so AGC loop  220  sets the gain of PGA  222  to a high gain. Subsequently lowpass filter  230  decreases the signal level of the blocker. AGC loop  240  is configured to increase the signal levels of both the desired signal and the blocker but, as illustrated in  FIG. 4 , the desired signal already has an amplitude at the desired level so AGC loop  240  sets the gain of PGA  242  to 1. Finally lowpass filter  250  decreases the signal level of the blocker further while maintaining the level of desired signal  462 , which remains at the target level at the input of ADC  260 . Thus the operation of analog baseband processor  200  in the presence of a strong remote blocker causes PGA  222  to have high gain and PGA  242  to have no gain. 
         [0034]    Thus by the use of distributed filtering with independent AGC loops, analog baseband processor  200  utilizes the full dynamic range of ADC  260  while attenuating strong out-of-band blockers that may be either adjacent channels or more remote channels. Conventional television receivers do not include baseband ADCs and tend to have aggressive baseband filters, which may be up to eighth order. By distributing AGC loops among the filters and performing additional filtering and down conversion digitally, analog baseband processor  200  is thus simpler and less expensive than conventional designs. 
         [0035]    Thus as seen from the illustrated embodiment in  FIGS. 3 and 4 , two AGC loops appear to be coordinated in achieving appropriate gain settings for different types of blockers even though they operate independently. In an alternate embodiment, the loops can provide a “take-over” option. With this option, the AGC loops operate independently unless one of the AGC loops exhausts its gain range, by reaching either minimum or maximum gain. Once one AGC loop has exhausted its gain range, it signals the other AGC loop, which then may set its gain based on levels at other points in the analog baseband chain. 
         [0036]    While the design of analog baseband processor  200  is robust, it also simply and efficiently corrects offset voltages introduced by non-ideal characteristics of the actual circuit elements.  FIG. 5  illustrates in block diagram form a programmable gain amplifier (PGA) with analog direct current (DC) offset correction  500  known in the prior art. PGA  500  includes an amplifier  510 , a DC offset correction circuit (DCOC)  520 , and a summing device  530 . Amplifier  510  has an input, and an output for providing an output signal labeled “V OUT ”. DCOC  520  includes an operational amplifier  522 , a resistor  524 , a capacitor  526 , and an amplifier  528 . Operational amplifier  522  has an inverting input, a non-inverting input connected to ground, and an output. Resistor  524  has a first terminal connected to the output terminal of PGA  510 , and a second terminal connected to the inverting input of operational amplifier  522 . Capacitor  526  has a first terminal connected to the inverting input of operational amplifier  522 , and a second terminal connected to the output terminal of operational amplifier  522 . Amplifier  528  has an input connected to the output terminal of operational amplifier  522 , and an output terminal. Summing device  530  has a first input terminal for receiving an input voltage labeled “V IN ”, a second input connected to the output of amplifier  528 , and an output connected to the input of PGA  510 . 
         [0037]    PGA  500  implements DC offset correction by placing active lowpass filter  520 , formed by operational amplifier  522 , resistor  524 , and capacitor  526 , in a closed loop around PGA  510 . Placing lowpass filter  520  in a feedback path creates an overall highpass response that attenuates DC offset voltages. However when used in baseband architectures, especially ZIF, PGA  500  rejects some low frequency content and thus distorts the desired signal. Also to bring the corner frequency of the highpass filter as low as possible, this type of DCOC topology requires large filter capacitors. Besides consuming a large amount of integrated circuit area, the larger capacitors also increase settling time after gain changes. Thus a new technique of offset correction that overcomes these problems would be desirable. 
         [0038]      FIG. 6  illustrates in block diagram form an analog baseband processor  600  with offset correction suitable for use as either analog baseband processor  160  or analog baseband processor  170  of  FIG. 1  according to another aspect of the present invention. Analog baseband processor  600  includes generally a lowpass filter  610 , a first AGC loop  620 , a lowpass filter  630 , a second AGC loop  640 , a lowpass filter  650 , and an ADC  660 . Lowpass filter  610  has an input for receiving input signal IF IN , and an output. AGC loop  620  has an input, and an output. Lowpass filter  630  has an input connected to the output of AGC loop  620 , and an output. AGC loop  640  has an input, and an output. Lowpass filter  650  has an input connected to the output of AGC loop  640 , and an output. ADC  660  has an input connected to the output of lowpass filter  650 , and an output for providing the DIGITAL OUTPUT signal. 
         [0039]    AGC loop  620  includes a PGA  622 , a peak detector  624 , and a controller implemented using controller  190 . PGA  622  has an input, a control input received from MCU  192 , and an output connected to the input of lowpass filter  630 . Peak detector  624  has an input connected to the output of PGA  622 , and an output provided to MCU  192 . AGC loop  640  includes a PGA  642 , a peak detector  644 , and a controller implemented using controller  190 . PGA  642  has an input, a control input received from MCU  192 , and an output connected to the input of lowpass filter  650 . Peak detector  644  has an input connected to the output of PGA  642 , and an output provided to MCU  192 . 
         [0040]    Analog baseband processor  600  also includes DCOC circuits  670  and  680 . DCOC circuit  670  includes a digital-to-analog converter (DAC)  672  and a summing device  674 . DAC  672  has an input for receiving a 5-bit offset correction word from MCU  192 , and an output. Summing device  674  has a first input connected to the output of lowpass filter  610 , a second input connected to the output of DAC  672 , and an output connected to the input of PGA  622 . DCOC circuit  680  includes a DAC  682  and a summing device  684 . DAC  682  has an input for receiving a 5-bit offset correction word from MCU  192 , and an output. Summing device  684  has a first input connected to the output of lowpass filter  630 , a second input connected to the output of DAC  682 , and an output connected to the input of PGA  642 . 
         [0041]    DCOC circuits  670  and  680  overcome the disadvantages of DCOC circuit  500  of  FIG. 5 : they use low-resolution (5-bit in the illustrated example) DACs that are small in area compared to the feedback DCOC filters shown in  FIG. 5 , and do not attenuate low frequency content of the desired signal. In addition, they settle faster compared to DCOC circuit  500  of  FIG. 5 . Having dedicated offset correction for each PGA allows better utilization of the available dynamic range of ADC  660 . 
         [0042]    Now considering  FIGS. 1 and 6  together, controller  190  determines offset correction words at power up using available circuitry. Firmware  194  controls ADC  660  to measure the voltage at the output of lowpass filter  650 , as will be described more fully below. Firmware  194  causes MCU  192  to measure and store offsets at different gain settings. Then during operation whenever a gain change is performed, appropriate gain values can be retrieved from memory and used to determine accurate offset values. 
         [0043]    Calibration generally proceeds as follows. Controller  190  grounds IF IN  and changes the settings of PGAs  622  and  642  to three different combinations. By making measurements at the output of lowpass filter  650  under three different gain combinations, controller  190  defines three equations in three variables, which can be solved using conventional algebraic substitution. Moreover by a careful choice of gain values to be binarily related, the computations can be greatly simplified. These operations are detailed below. 
         [0044]    The offset at the input to PGA  622 , designated “V OS1 ”, includes the local oscillator leakage of mixer  150 , the output offset of the second, active lowpass filter in lowpass filter  610 , and the input referred offset voltage of PGA  622  itself. The offset at the input to PGA  642 , designated “V OS2 ”, includes the output offset of the active biquad filter forming lowpass filter  630  and the input referred offset voltage of PGA  642  itself. The offset at the output of lowpass filter  650 , designated “V OS3 ”, simply includes the input referred offset voltage of ADC  660 . 
         [0045]    The three offsets can be understood by how many gain stages they go through. V OS1  is amplified by both PGA  622  and PGA  642 ; V OS2  is only amplified by PGA  642 ; and V OS3  does not go through any amplification. Thus the analog baseband chain output referred offset voltage, designated V OSout , is given by 
         [0000]        V   OSout   =G   PGA1   G   PGA2   V   OS1   +G   PGA2   V   OS2   +V   OS3   [1]
 
         [0000]    in which G PGA1  represents the gain of PGA  622  and G PGA2  represents the gain of PGA  642 . 
         [0046]    Equation [1] includes three unknowns, namely the equivalent offset voltages. Controller  190  controls the various elements in analog baseband chain  600  to change the gain settings and then to make the three required measurements. TABLE 1 illustrates the general case for the measurements: 
         [0000]                                TABLE 1               Measurement No.   PGA 622 Gain   PGA 642 Gain   Output Offset                   1   G PGA1     —     1     G PGA2     —     1     V OSout     —     1         2   G PGA1     —     2     G PGA2     —     2     V OSout     —     2         3   G PGA1     —     3     G PGA2     —     2     V OSout     —     3                      
With three measurements at the output of ADC  660 , the following three different digitized output voltages are obtained:
 
         [0000]        V   OSout     —     1   =G   PGA1     —     1   G   PGA2     —     1   V   OS1   +G   PGA2     —     1   V   OS2   +V   OS3   [2]
 
         [0000]        V   OSout     —     2   =G   PGA1     —     2   G   PGA2     —     2   V   OS1   +G   PGA2     —     2   V   OS2   +V   OS3   [3]
 
         [0000]        V   OSout     —     3   =G   PGA1     —     3   G   PGA2     —     3   V   OS1   +G   PGA2     —     3   V   OS2   +V   OS3   [4]
 
         [0000]    Since these measurements yield three equations in three unknowns, one can solve for V OS3 , V OS3 , and V OS3  using algebraic substitution. 
         [0047]    However there are opportunities to simplify the calculations to allow them to be made more easily using MCU  192 . The math can be simplified if one uses two different gain settings (instead of three) for each PGA with the following combinations and further uses the relationship given in Equation [8] below: 
         [0000]        V   OSout     —     1   =G   PGA1     —     1   G   PGA2     —     1   V   OS1   +G   PGA2     —     1   V   OS2   +V   OS3   [5]
 
         [0000]      V OSout     —     2   =G   PGA1     —     2   G   PGA2     —     1   V   OS1   +G   PGA2     —     1   V   OS2   +V   OS3   [6]
 
         [0000]      V OSout     —     3   =G   PGA1     —     1   G   PGA2     —     2   V   OS1   +G   PGA2     —     2   V   OS2   +V   OS3   [7]
 
         [0000]      G PGA1     —     2   ×G   PGA2     —     1   =G   PGA1     —     1   ×G   PGA2     —     2   [8]
 
         [0000]    which allows the offset equations to be simplified as follows: 
         [0000]    
       
         
           
             
               
                 
                   
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                           2 
                            
                           _ 
                            
                           2 
                         
                       
                       - 
                       
                         G 
                         
                           PGA 
                            
                           
                               
                           
                            
                           2 
                            
                           _ 
                            
                           1 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   10 
                   ] 
                 
               
             
             
               
                 
                   
                     V 
                     
                       OS 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       V 
                       
                         OSout_ 
                          
                         1 
                       
                     
                     - 
                     
                       
                         G 
                         
                           PGA 
                            
                           
                               
                           
                            
                           1 
                            
                           _ 
                            
                           1 
                         
                       
                        
                       
                         G 
                         
                           PGA 
                            
                           
                               
                           
                            
                           2 
                            
                           _ 
                            
                           1 
                         
                       
                        
                       
                         V 
                         
                           OS 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                     - 
                     
                       
                         G 
                         
                           PGA 
                            
                           
                               
                           
                            
                           2 
                            
                           _ 
                            
                           1 
                         
                       
                        
                       
                         V 
                         
                           OS 
                            
                           
                               
                           
                            
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   11 
                   ] 
                 
               
             
           
         
       
     
         [0048]    Further simplification can be achieved by selecting values of G PGA1     —     1 , G PGA1     —     2 , G PGA2     —     1 , and G PGA2     —     2  so that evaluation of equations [9]-[11] becomes trivial and thus can be achieved easily with a conventional MCU. The inventors chose the values in TABLE 2 below: 
         [0000]                                TABLE 2               Measurement No.   PGA 622 Gain   PGA 642 Gain   Output Offset                   1   2×   2×   V OSout     —     1         2   4×   2×   V OSout     —     2         3   2×   4×   V OSout     —     3                      
Under these circumstances, equations [9]-[11] are simplified as follows:
 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OS 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         V 
                         
                           OS 
                           , 
                           
                             
                               out 
                                
                               _ 
                             
                              
                             2 
                           
                         
                       
                       - 
                       
                         V 
                         
                           OS 
                           , 
                           
                             out 
                              
                             
                                 
                             
                              
                             _ 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                     
                     4 
                   
                 
               
               
                 
                   [ 
                   12 
                   ] 
                 
               
             
             
               
                 
                   
                     V 
                     
                       OS 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   = 
                   
                     
                       
                         V 
                         
                           OS 
                           , 
                           
                             
                               out 
                                
                               _ 
                             
                              
                             3 
                           
                         
                       
                       - 
                       
                         V 
                         
                           OS 
                           , 
                           
                             out 
                              
                             
                                 
                             
                              
                             _ 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                     
                     2 
                   
                 
               
               
                 
                   [ 
                   13 
                   ] 
                 
               
             
             
               
                 
                   
                     V 
                     
                       OS 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       V 
                       
                         OSout 
                          
                         
                             
                         
                          
                         _ 
                          
                         1 
                       
                     
                     - 
                     
                       4 
                        
                       
                         V 
                         
                           OS 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                     - 
                     
                       2 
                        
                       
                         V 
                         
                           OS 
                            
                           
                               
                           
                            
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   14 
                   ] 
                 
               
             
           
         
       
     
         [0000]    Evaluation of these equations requires no multiplication or division operations and these equations can be evaluated with simple binary arithmetic using shift and add operations. Once V OS1 -V OS3  are determined, MCU  192  provides the offset correction words so determined to DACs  672  and  682 . 
         [0049]    The offset correction values are computed differently, however, based on the configuration of the PGA.  FIG. 7  illustrates in partial block diagram and partial schematic form a PGA  700  useful in understanding the offset correction operation. PGA  700  includes DAC  672 , summing device  674 , and PGA  622  configured substantially as shown in  FIG. 6 . In addition, however, the offset voltage is modeled as a voltage source  710  connected in series between the output terminal of summing device  674  and the input of PGA  622  with its positive terminal connected to the output terminal of summing device  674  and its negative terminal connected to the input terminal of PGA  622 . If PGA  700  is configured as illustrated in  FIG. 7 , the offset correction words do not need to be modified when the gain of PGA  622  changes during normal operation. This relationship holds for PGA  642  as well. 
         [0050]    However in another embodiment PGAs  622  and  642  can be configured in a way that requires modification of the offset correction words based on the gain setting. This configuration is better understood with respect to  FIG. 8 , which illustrates in partial block diagram and partial schematic form another embodiment of a PGA  800  according to the present invention. PGA  800  includes an operational amplifier  810 , variable resistors  820  and  830 , an offset voltage source  840 , a summing device  850 , and a DAC  860 . Operational amplifier  810  has an inverting input terminal, a non-inverting input terminal connected to ground, and an output terminal for providing an output voltage V OUT . Resistor  820  has a first terminal, a second terminal, and a control terminal for receiving a control signal from MCU  192 . Resistor  830  has a first terminal connected to the second terminal of resistor  820 , a second terminal connected to the output of operational amplifier  810 , and a control terminal for receiving a control signal from MCU  192 . Summing device  850  has a first input connected to the second terminal of resistor  820 , a second input, and an output connected to the inverting input terminal of operational amplifier  810 . DAC  860  has an input terminal for receiving the offset correction word from MCU  192 , and an output terminal connected to the second input of summing device  850 . Offset voltage source  840  is connected in series between the input of the PGA and the first terminal of resistor  820  with its positive terminal receiving input voltage V IN , and its negative terminal connected to the first terminal of resistor  820 . 
         [0051]    MCU  192  sets the gain of PGA  800  by changing the values of resistors  820  and  830 . Since DAC  860  provides an input inside PGA  800 , the digitized offset cannot be applied directly to the input of DAC  860 , but instead needs to be modified as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OS 
                        
                       
                           
                       
                        
                       1 
                     
                     ′ 
                   
                   = 
                   
                     
                       
                         G 
                         
                           PGA 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       
                         ( 
                         
                           1 
                           + 
                           
                             G 
                             
                               PGA 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         ) 
                       
                     
                     × 
                     
                       V 
                       
                         OS 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                 
               
               
                 
                   [ 
                   15 
                   ] 
                 
               
             
             
               
                 
                   
                     V 
                     
                       OS 
                        
                       
                           
                       
                        
                       2 
                     
                     ′ 
                   
                   = 
                   
                     
                       
                         G 
                         
                           PGA 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       
                         ( 
                         
                           1 
                           + 
                           
                             G 
                             
                               PGA 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                         
                         ) 
                       
                     
                     × 
                     
                       V 
                       
                         OS 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                 
               
               
                 
                   [ 
                   16 
                   ] 
                 
               
             
           
         
       
     
         [0000]    Thus the offset correction words are gain dependent. During normal operation, whenever a gain change is made to any PGA, the corresponding updated offset correction words should be applied at the same time. Note that the settling time after such a gain change is much faster than the settling time of an analog DCOC circuit such as DCOC circuit  520  shown in  FIG. 5 . 
         [0052]    Thus a signal processor such as disclosed above is suitable for use in an LIF or ZIF architecture receivers by distributing filtering and gain stages. The signal processor is able to establish proper gain and filter settings to utilize available dynamic range even when the characteristics of channel blockers change. Moreover offset voltages present in active elements such as PGAs and active filters are corrected with digital-to-analog converters (DACs) that convert stored digital correction words into analog offset corrections. This type of offset correction avoids conventional highpass DCOC circuits that would attenuate desired signal content when used in receivers with ZIF and LIF architectures. These values are determined during a calibration procedure at startup by making multiple measurements using an existing ADC. By making certain related gain settings and then measuring the output digital value, multiple offsets can be determined using simple algebraic substitution. 
         [0053]    Various modifications will be apparent from the foregoing description. For example, in the illustrated embodiment controller  190  was implemented with an MCU and firmware. In particular, MCU  192  executed stored program instructions from firmware  194  to implement the AGC loop control and offset calibration functions. In other embodiments, these functions can be performed with different types of controllers using hardware, software, or different combinations of the two. While the signal processing uses differential signals, in other embodiments it may use single-ended signals instead. Moreover while the signal processor described herein was designed for a multi-standard television receiver, in other embodiments the signal processor could be used in other type of RF systems. The ADCs contemplated herein are 3-bit delta-sigma ADCs, but could be implemented using other known ADC architectures. Also the signal processor was disclosed in the context of an analog baseband processor, but the principles used could also be used for digital processors and processors used with higher IFs. 
         [0054]    Therefore above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.