Abstract:
A phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.

Description:
CROSS-REFERENCE  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/536,304, filed Jan. 14, 2004; is related to U.S. application Ser. No. 10/264,360 entitled PHASE-LOCK LOOP HAVING PROGRAMMABLE BANDWIDTH and U.S. application Ser. No. 10/264,359 entitled PWM CONTROLLER WITH INTEGRATED PLL, both of which were filed on Oct. 4, 2002; and all of which are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     A graphics board is a printed-circuit board that typically includes at least one graphics processor and other electronic components that process and display graphics or other video data in a computer system.  FIG. 1  is a block diagram of a graphics board  100  that includes a graphics processor  105 , as discussed in the aforementioned U.S. applications. Typically, one of the electronic components connected to the graphics processor  105  is a double-data-rate random-access memory (DDS RAM) chip  106 . Both the graphics processor  105  and the DDR RAM  106  typically have high power requirements, as compared to other electronic components. For example, the graphics processor  105  typically requires 5-15 amps (A) of power at 1.6 volts (V), and the DDR RAM  106  typically 5-10 A and 10-20 A at 1.25 V and 2.5 V, respectively. Because the processor  105  and DDR RAM  106  have such high power requirements, pulse-width-modulated (PWM) switching power supplies  110   a ,  110   b , and  110   c  are typically provided for the graphics processor  105  and the DDR RAM  106 . A common power supply  108  feed the PWM switching power supplies  110   a ,  110   b  and  110   c . Typically, the PWM power supplies  110   a ,  110   b  and  110   c  each includes a separate PWM-controller chip  112   a ,  112   b  and  112   c , although these controllers can be integrated into the graphics processor  105  and DDR RAM  106  chips, respectively.  
         [0003]     Ideally, the operating frequencies of the PWM power supplies  110   a ,  110   b  and  110   c  are the same. If, however, these frequencies are different, undesirable “beat” frequencies can result. A beat frequency is equal to the difference between the two frequencies. Unfortunately, the beat frequency can cause undesirable artifacts to appear in a video display.  
         [0004]     A technique for reducing or eliminating the beat frequency is for two of the PWM controllers  112   b  and  112   c  (slaves) of the graphics board  105  to lock onto the PWM signal of the other PWM controller  112   a  (master) using a phase-lock loop (PLL). The slave PLLs can each generate one or more slave-PWM output signals that are phase locked to the master-PWM signal and that have the same frequency as the master-PWM signal.  
         [0005]     As illustrated in  FIG. 2 , the master-PWM controller  112   a  provides output signals UG and LG to driver  120   a , which provides a signal to integrator  122   a . The output of the integrator  122   a  is V 1 . The master-PWM controller  112   a  also has signal LG connected as the input to a slave-PWM  112   b . The output signals UG and LG of the slave-PWM  112   b  are provided to driver  120   b , which provides a signal to integrator  122   b . The output signal is V 2 . The slave-PWMs have a tendency to overcorrect if there are disturbances on the input signal. In other systems wherein the input signals to the PWM controllers are a crystal oscillator, there are no missed pulses. However, in PWM master/slave applications, there are missed pulses if the load current is stepped. If there are few missing pulses, it is possible that either the up or down pulses in the pulse width in the PLL will be very wide and drive the voltage control oscillator (VCO) to follow.  
         [0006]     An example of this type of PLL is illustrated in  FIG. 3  and disclosed in detail in the aforementioned U.S. applications. The input or reference signal IN 2  at  202  is provided to a phase frequency detector (PFD)  200 . The input signal  202  is compared against a feedback signal  204  coming from VCO  206 . Depending upon the frequency difference, an up signal UP  208  or a down signal DN  210  is provided through a switching, gate or logic circuit  212  as UPG and DNG to a charge pump  220 . The output of the charge pump  220  is provided through a filter  226  to the VCO  206 . The output of VCO  206  is the output signal IN 1  at  234 , as well as feedback signal  204 . A ÷ N counter  218  is responsive to the cycles of the PFD  220  to transmit the up/down signals on  208  and  210  through the gate circuit  212  to operate the charge pump  220 . In the above-mentioned applications, the circuit  212  is shown as gated inverters, as well as multiplexes. In  FIG. 3 , they are illustrated by AND gates  214 ,  216 . It should also be noted that the filter  226  has capacitor  218  in parallel with the series connection resistor  232  and capacitor  230 . ÷ N counter  218  is a decrementing counter and maintains a transmission signal having a width of a cycle of the PFD  220 . It is the width of this signal through the circuit  212  which causes the overcorrection for the instability in the input signal at  202 .  
       SUMMARY OF THE INVENTION  
       [0007]     One embodiment is a phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.  
         [0008]     The PLL may be provided in a slave-PWM controller of a pulse width modulated system wherein the reference signal is from the master-PWM controller, and the oscillator proves a PWM signal. Also, the pulse width modulation system may be part of a power supply circuit having master and slave power supplies. The power supply may be part of a video processor, which may be part of a computer system. The PLL may be provided in a transmitter/receiver.  
         [0009]     These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  is a block diagram of a graphic board that utilizes an embodiment of a PWM controller, according to an embodiment of the present disclosure.  
         [0011]      FIG. 2  is a schematic of a master/slave-PWM controller.  
         [0012]      FIG. 3  is a schematic of a type of PLL to which the present disclosure is directed.  
         [0013]      FIG. 4  is a block diagram of an even further embodiment of the PLL, according to the present disclosure, with a variable rate of the transmission of the correction signal.  
         [0014]      FIG. 5  is an even further embodiment of the PLL, according to the present disclosure, showing a further variable rate of transmission of the correction signal.  
         [0015]      FIGS. 6A and 6B  are graphs showing the counter output or gating or transmission signal and the voltage at the loop filter, respectively, of the prior art.  
         [0016]      FIGS. 7A and 7B  are graphs showing the counter output or gating or transmission signal and of the loop filter for a first embodiment of the present disclosure, respectively.  
         [0017]      FIGS. 8A and 8B  are graphs showing the counter output or gating or transmission signal and of the loop filter of the first and a second embodiment of the present disclosure, respectively.  
         [0018]      FIGS. 9A and 9B  are graphs showing the correspondence between the count pulse cnt and the gating or en_pfd pulse output of the counter.  
         [0019]      FIG. 10  is a circuit diagram of the counting stage of an incremental counter, according to the present disclosure.  
         [0020]      FIG. 11  is a circuit diagram of the logic of the rate selector of the incremental counter, according to the present disclosure.  
         [0021]      FIG. 12  is a block diagram illustrating the hand shake between a master- and slave-PWM power controller, according to the principles of the present disclosure.  
         [0022]      FIGS. 13A and 13B  are graphs showing the soft-start cycle of the master/slave controllers of  FIG. 12 , according to the principles of the present disclosure.  
         [0023]      FIG. 14  is a diagram of a Wireless-Area-Network (WAN) transmitter/receiver that can incorporate the PLL of the present disclosure.  
         [0024]      FIG. 15  is a block diagram of a computer that incorporates the graphic board of  FIG. 1  with one of the PLLs of the present disclosure. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]     The PLLs of the present disclosure may be used in the graphic card  100  of  FIG. 1 , the slave PWM controller  112   b  of  FIG. 2 , the WAN transmitter/receiver of  FIG. 14  or the computer of  FIG. 15 . They may also be used in other devices requiring a PLL. The embodiments of  FIGS. 4 and 5  are PLLs with a variable rate of transmission of the correction signal.  
         [0026]     Those elements of the PLL which are common to that shown of  FIG. 3  will have the same reference numbers and function the same way as those elements in  FIG. 3 . The operation of the PLL including the phase frequency detector (PFD)  200 , the counter  218 , the logic transmission circuit  212 , the charge pump  220 , the filter  226  and the VCO  206  are well known and will not be described in detail. Reference will be made to the aforementioned applications, as well as other prior art devices.  
         [0027]     As previously described with respect to  FIG. 3 , the frequency of the correction pulses UPG and DNG are defined by the period in which the output en_pfd of the counter  218  activates the gates  212  and  214  and transmits the signal to the charge pump  220 . This frequency is a function of the frequency of the input signal  202  and the feedback signal  234  at input  204 .  
         [0028]     Although the up/down counter  218  has been described in the aforementioned applications as a decrementing counter  218 , it can also be an up counting frequency divider.  
         [0029]     An improvement to the PLL, as illustrated in  FIGS. 4 and 5 , is to change the transmission rate or frequency of the PLL. This allows the system to respond differently during start-up and non-lock and during lock. Thus, it is basically changing the bandwidth of the response of the PLL. A rate selector circuit  400 , as illustrated in  FIG. 4 , monitors the charge on capacitor  230  of the filter  226 . The amount of charge on capacitor  230  is a function of the operation of the charge pump circuit  220 . The rate selector circuit  400  includes a switch or MOS FET  402 , which senses the voltage at capacitor  230 . Connected to the source of MOS FET  402  is a current source  404 . Once the voltage of the capacitor  230  exceeds the threshold of the MOS FET  402 , it sends an enabling signal through Schmitt trigger  406  to the counter  218 . Prior to this point, counter  218  is disabled or has a count of one and, therefore, for each cycle, an enable pulse is transmitted through to the logic gates  214 ,  216 . Thus, for every cycle, the up and down pulses UP, DN on  208  and  210  are transmitted through as signals UPG and DNG. Thus, initially, the PLL will have a correction every comparison cycle. Once the system gets closer to lock, the voltage on the capacitor  230  is maintained high and, therefore, the counter  218  will slow down the correction frequency by the comparison cycle divided by N. By way of example, whereas the time for lock of a 300 kHz signal using the circuit of  FIG. 3  and N=16 is 5 milliseconds, as shown in  FIG. 6 . With a selector circuit  400  of  FIG. 4 , the lock time has been decreased to the range of 2.5 milliseconds, as shown in  FIG. 7 .  
         [0030]      FIG. 5  shows another embodiment of the rate selector  400 . In this case, the rate selector  410  has more than one adjustment value, wherein N may be 1 to M cycles. The rate selector  410  may be a state machine which senses various levels of voltage on the capacitor  230  and sets the appropriate rate to the counter  218 . For example, using a count of sixteen, the various levels or thresholds may set a count of 2, 4, 8, 12, 16. Alternatively, the state machine, after reading a first threshold, may incrementally or sequentially increase the count of counter  218 . Thus, the lock process may be initially sped up to get to lock faster and then slowed down to maintain lock. By way of example, whereas the time for lock of a 300 kHz signal using the circuit of  FIG. 3  and N=16 is in the range of 5 milliseconds, as shown in  FIG. 6 . With a selector circuit  400  of  FIG. 5 , the lock time has been decreased to the range of 1 milliseconds, as shown in  FIG. 8 . Thus, the PLLs of  FIGS. 4 and 5  are variable bandwidth PLLs.  
         [0031]     The output signal en_pfd of the counter  218  is illustrated in  FIG. 6A . The pulse opens or turns off the charge pump  220 . In  FIG. 6A , enable count pulses are every sixteen comparison cycles for the example used. The resulting voltage on the filter  226  is illustrated in  FIG. 6B . Each time the output counter is provided, there is a spike in the filter voltage. The circuit of  FIG. 5  reaches a lock at approximately 5.0 milliseconds.  
         [0032]     The regions A and B are provided in  FIG. 6B  for a point of reference when compared to  FIGS. 7B and 8B . The demarcation between regions A and B is when the voltage on the capacitor  230  of the filter  226  reaches the preset threshold. Thus, region A is the region in which the counter  218  would be disabled, and the charge pump  220  would provide a signal every comparison cycle. Region B is where the rate selector  400  provides a variable rate to achieve the desired lock results.  
         [0033]      FIGS. 7A and 7B  show the graphs for the embodiment of  FIG. 4 . The output of the counter signal en_pfd is illustrated in graph A, and the resulting voltage of the output of the filter  226  is shown as graph B. The charge pump  220  open signals are shown at the pulses in graph A, which produce the spikes in graph B. In region A, the counter  218  is disabled, and the charge pump  220  is activated every comparison cycle. After a given threshold is reached, the charge pump  220  is actuated every time the counter  218  reaches its preset value. In the example used, this is sixteen comparison cycles. As previously discussed, using the device and method of  FIG. 4 , the lock time is decreased approximately in half from 5 milliseconds to 2.553 milliseconds. In region B, the charge pump  220  is activated every sixteen comparison cycles in the given example.  
         [0034]     A second embodiment is illustrated in  FIG. 8 . In the particular method shown, the rate selector  400  disables the counter  218  such that the charge pump  220  is activated every comparison cycle in the region A of the graph. This takes benefit of the increased tracking of lock illustrated in  FIG. 7 . In region B, instead of counting and providing an output en_pfd every sixteen cycles, the rate selector  400  causes the counter  218  to progressively and sequentially increase from every cycle up to once every sixteen cycles. This results in a lock time of 1.12 milliseconds compared to the lock time of 2.553 of  FIG. 7  using only the region A speed-up and the lock time of 5 milliseconds of  FIG. 6  of the prior art. Although the example shown is a progressive and sequential increase of the count from 1 to 16, M may be a number other than 16. The increments may be greater than one, as well as other variations.  
         [0035]      FIGS. 9A and 9B  are graphs of the PFD  200  illustrating the relationship between the counter comparison cycle cnt of the PFD  200  and the output en_pfd of the counter  218 , respectively, for the progressions  1 ,  2 ,  3  and  4 . In reviewing  FIG. 9A , every time the counter  218  reaches its preset count, the output of the counter en_pfd goes high. The next count cnt is used to reset the counter  218  and bring the output of the counter en_pfd low. As the counter  218  is sequenced from 1 to 4, the resulting counter output pulses A, B, C and D are produced with increased spacing. The counter  218  and rate selector  400  that produce the sequential rate change illustrated in  FIGS. 8 and 9  are shown in  FIGS. 10 and 11 , respectively.  
         [0036]     The counter  218  includes eight stages  501 - 508 . Each stage is illustrated, for example, as a D flip flop. The first stage  501  has a data input TE connected at  516  to a fixed voltage. Its clock input CPN is connected to the count input cnt at  514 , and its clock CP input is connected to the inverse of the count input cnt through inverter  516 . The outputs Q and QN of each of the stages are connected to CPN and CP, respectively, of the next stage. For stages  502 - 508 , the QN output is fed back to its data input D. The reset terminal of each of the stages  501 - 508  is connected to the output of SR flip flop  520 . The set input  522  of flip flop  520  receives signal end_b, and its reset input at  524  is the reset signal RST.  
         [0037]     The output of each of the stages  501 - 508  (namely, qc and qcb) are used in the logic of the rate selector  400  illustrated in  FIG. 11 . As will be noted in the discussion of  FIG. 11 , all eight stages  501 - 508  are used in the start-up region B to sequentially increase the count from 1 to 16. After 16 is reached, only the first four stages  501 - 504  are used in the counter  218 .  
         [0038]     The rate selector  400  includes sixteen NAND gates  451 - 466 . Each NAND gate has an input from one or more of the counting stages  501 - 508  and provides a count of 1-16, respectively. This produces the ÷ N results of the progressive count. A NAND gate by definition has a low output when all of its inputs are high. Connected to the first fifteen NAND gates  451 - 465  is a start_b signal, which indicates that the B region of the speed-up portion of the cycle has been initiated. Thus, the first fifteen gates  451 - 465  provide an output in sequence. The last gate  466 , which represents a ÷ 16 count, has an input of end_b. This is at the end of that portion of the start-up cycle, which is the increasing sequence. This deactivates the gates  451 - 465  and allows only the gate  466  to operate providing a ÷ 16 signal.  
         [0039]     The start_b and end_b signals are produced by flip flop  470 , which is illustrated as an RS flip flop having its S input  472  connected to the output of the ± 15 NAND gate  465 . Its reset input  474  receives the reset signal RST. The Q output  470  of the flip flop  470  is the end_b signal, and the QN output  475  is the start_b signal.  
         [0040]     The outputs of all of the NAND gates  451 - 466  are provided to NAND gate  570 . The output of NAND gate  570  is connected through two inverters  572 ,  574  to provide the charge pump enable signal en_pfd. As discussed with respect to  FIG. 9 , the output of the counter  218  or the charge pump enable signal en_pfd goes high when the output of any of the NAND gates  451 - 466  is low and goes low when the outputs of all of the NAND gates  451 - 466  are high. Thus, when one of the NAND gates  451 - 466  goes low, en_pfd goes high.  
         [0041]     Initially, the outputs of all of the stages  501 - 508  are low. Since at least one input of all of the NAND gates  451 - 466  is from a QC output and it being low, all of the outputs of the NAND gates  451 - 466  are high. Since the input to NAND gate  557  are all high, its output en_pfd is low. At count  1 , NAND gate  451  changes from a high to a low output, since all of its inputs are high. Thus, one of the inputs to NAND gate  570  is low, and the output of the circuit en_pfd becomes high. After the second counter pulse cnt, NAND gate  451  returns to its high state, and the other gates  452 - 466  remain at their high state. Thus, all of the inputs to the NAND gate  570  are high, and the output en_pfd returns to low.  
         [0042]     For the third and fourth count pulses, all of the gates  451 - 466  remain at a high output. At the termination of the fourth pulse, gate  452 , having all of its inputs high, will become low. This provides a low input to NAND gate  570  producing a high output. An output at en_pfd stays high until the termination of the fifth pulse.  
         [0043]     This sequence is repeated by the gates  451 - 466  sequentially increasing the ÷ count from 1 to 16. Once the gate  465  indicating a count of 15 has terminated, flip flop  470  toggles causing the start_b output  478  to go low and the end_b output  476  to go high. The start_b output going low provides a low input to the first fifteen gates  451 - 465  and, basically, maintains them high. Thus, the toggling of the NAND gate  570  and the output en_pfd is under the control of the output of the count sixteen gate  466 .  
         [0044]     The input to the count sixteen gate  466  includes the end_b signal from flip flop  460  and the Q output of the first four stages  501 - 504  of the counter  218 . As the counter  218  counts from zero to 15, at least one of the inputs is low. Thus, the output of the gate  466  is high prior to the 16 th  count. This makes all of the inputs to NAND gate  570  high and, therefore, its output en fd is low. Upon the termination of the 16 th  count, all of the outputs of  501 - 504  are high. Thus, the output of NAND gate  466  is low. This low output on NAND gate  570  produces a high output signal en_pfd until the next count signal.  
         [0045]     The reset signal RST on flip flop  470  of the rate selector circuit  400  and on  524  of flip flop  520  of the counter  218  is a signal received from monitoring the threshold of the capacitor  230  of filter  226 . The reset signal RST is high until its threshold is reached. Thus, all of the stages  501 - 508  are reset before the threshold is reached. The NAND gates  451 - 465  receive the end_b signal, and gate  466  receives the start_b signal. Since these are opposite, the outputs of one of the logic gates  451 - 466  will be low, and the output en_pfd through the NAND gate  570  will be high. This allows the charge pump  220  to operate in response to every count pulse in region A of the speed-up cycle.  
         [0046]     Thus, it can be seen that the eight stage counter  218  forms a progressive counter from stages  1 - 16  using all eight stages. However, once it has reached its last value, only the first four stages are used as a traditional binary counter. The use of the eight stage counter in combination with the rate select circuit  400  produces the sequential and lock counting. It also provides the disable of the counter  218  during stage A of the speed-up circuit. The illustrated counter  218  has sixteen stages, which is more than the four stages for a minimum rate of 1/(2 4 ) or 1/16.  
         [0047]     In the master/slave set-up of  FIG. 2 , reduction of the time to allow the slave PLL to achieve lock is illustrated in the circuit of  FIG. 12  and the diagram of  FIG. 13 . Each of the PWMs  112   a ,  112   b  have a soft-start. The soft-start is controlled by soft-start circuit SS  132 , which is responsive to the input enable signal EN_SS. The soft-start circuit  132  controls a switch  134  to control the Power Good output PG, which indicates that the soft-start has terminated, and the output signals are considered to be good PWM signals. This is required because the power-up of the circuits and the PLL achieving this stable voltage is required. Connected to the soft-start enable input EN_SS is a capacitor  140 . Connected to the synchronization input FSYNC or the input to the PLL is a resistor  142 . The PG output of the master controller  112   a  is connected to the enable input EN_SS 2  of the slave  112   b . The LG output of the master  112   a  is connected to the FSYNC input of the slave  112   b.    
         [0048]     The operation of the interconnection of the master  112   a  and the slave  112   b  is illustrated in  FIG. 13 .  FIG. 13A  shows the master voltages, while  FIG. 13B  shows the slave voltages. Upon power-up POR, the voltage on the capacitor  140  of the master  112   a  begins to charge at time A. The slave  112   b  is also responsive to the power-up signal POR at time A. A short time later, an output is provided on LG as out  1  at time B. At time C, the output of the VCO or the voltage across the filter reaches a steady state as does the input voltage EN_SS 1 . At this point, the PG signal output of the master  112   a  goes high and stays high. This is a high impedance for an open drain circuit. This output is applied to the input of the EN_SS 2  of the slave  112   b  and begins charging its capacitor  140 . This starts the soft-start period of the slave  112   b . At a short time period later at time D, the output out  2  starts rising. At time E, the input enable signal EN_SS 2  reaches stable voltage. Although not shown, the slave  112   a  also provides a PG output signal at time E. The capacitor  140  of master controller  112   a  should be timed to determine a soft-start period which is greater than the time required for the PLL of slave controller  112   b  to lock.  
         [0049]     Although the master controller  112   a  is outputting a signal LG or UG because of the soft-start, an output signal LG or UG is not considered an appropriate PWM signal since the PG signal is not present. The LG or UG signals are connected to the input FSYNC of the slave controller  112   b  during the period from time B to time C. This allows the slave controller  112   b  to begin to track the signal received from the master controller  112   a . Thus, it does not start its tracking at time C but begins at time B. Thus, it starts tracking before it even begins its soft-start cycle. This allows the soft-start cycle of the slave controller  112   b  to be reduced since the tracking has already taken place. This shortens the start-up period for the slave controller  112   b . This is advantageous alone or when used with the speed-up methods described above. The soft-start period of the master  112   a  may be set to be greater than the period of time for the slave&#39;s  112   b  PLL to achieve lock. This would make the soft-start period of the slave  112   b  independent of loop lock requirements. The values of the capacitors  140  are independently set to determine the soft-start period of each of the controllers  112 .  
         [0050]      FIG. 14  is a WAN transmitter/receiver  700  that can incorporate any of the PLLs of  FIGS. 4 and 5 , according to an embodiment of the invention. In addition to the PFD  200 , charge pump  220 , VCO  206 , frequency divider  218  (omitted from  FIG. 14  for clarity), rate selector RS circuit  300  and the filter  226  (omitted from  FIG. 14  for clarity), the PLL includes a terminal  718  for receiving the reference signal and a local-oscillator (LO) distributor  720  for distributing the output of the VCO  206  as an LO signal. In addition to the PLL, the transmitter/receiver  700  includes a transmitter  704  and a receiver  706 . The transmitter  704  includes a mixer  722  that modulates the LO with a differential base-band data signal received from a computer (not shown) via data terminals  724 ,  762 . The transmitter  704  then provides this modulated data signal to a transmit-terminal  728  for wireless transmission to a remote receiver (not shown). Similarly, the receiver  706  receives a modulated data signal from a remote wireless transmitter (not shown) via a terminal  730 , and includes a mixer  732  that demodulates the received data signal with the LO signal and provides a differential demodulated data signal to the computer via the terminals  724  and  726 . The PLL is operable to synchronize the LO signal from the VCO  206  to the reference signal received on terminal  718 . The transmitter/receiver  700  also includes other circuits that are conventional and that are thus omitted from  FIG. 10  for brevity.  
         [0051]      FIG. 15  is a block diagram of a general-purpose computer system  820  that incorporates the graphics board  100  of  FIG. 1 , according to an embodiment of the invention. The computer system  820  (e.g., personal or server) includes one or more processing units  821 , system memory  822 , and a system bus  823 . The system bus  823  couples the various system components including the system memory  822  to the processing unit  821 . The system bus  823  may be any of several types of busses (including a memory bus, a peripheral bus and a local bus) using any of a variety of bus architectures. The system memory  822  typically includes read-only memory (ROM)  824  and random-access memory (RAM)  825 . Firmware  826  containing the basic routines that help to transfer information between elements within the computer system  820  is also contained within the system memory  822 . The computer system  820  may further include a hard disk-drive system  827  that is also connected to the system bus  823 . Additionally, optical drives (not shown), CD-ROM drives (not shown), floppy drives (not shown) may be connected to the system bus  823  through respective drive controllers (not shown) as well.  
         [0052]     A user may enter commands and information into the computer system  820  through input devices such as a keyboard  840  and pointing device  842 . These input devices, as well as others not shown, are typically connected to the system bus  823  through a serial port interface  846 . Other interfaces (not shown) include Universal Serial Bus (USB) and parallel ports  840 . A monitor  847  or other type of display device may also be connected to the system bus  823  via an interface such as the graphics card  100 .  
         [0053]     Although the present disclosure has been described and illustrated in detail, it is to be clearly understood that this is done by way of illustration and example only and is not to be taken by way of limitation. The scope of the present disclosure is to be limited only by the terms of the appended claims.