Abstract:
A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying smal logic level signals for connecting data from a network&#39;s first circuit to a network&#39;s second circuit in which a network&#39;s input terminal connects a terminator circuit to the network&#39;s second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit and to a differential hysteresis receiver. The tuned voltage levels supplied to said terminator input circuit for the termination to the network as a terminator on the data line passing data from said first circuit to said second citcuit supplying, and also, supplied to the hysteresis differential receiver which is integrated into the terminator circuit to set up a threshold tuned reference voltage between the logic levels of said terminator input circuit for the network.

Description:
RELATED APPLICATIONS 
     This application is related to the following concurrently filed application (s): 
     U.S. Ser. No. 09/580,290, filed May 30, 2000, entitled: CMOS Small Signal Terminator and Network, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/583,187, filed May 30, 2000, entitled: SOI SMALL SIGNAL TERMINATOR AND NETWORK, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/583,185, filed May 30, 2000, entitled: Method for use with a Terminator and Network, naming David T. Hui,” inventor; and 
     U.S. Ser. No. 09/580,289, filed May 30, 2000, entitled: CMOS Small Signal Terminated Receiver, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/583,055, filed May 30, 2000, entitled: CMOS Small Signal Switchable Terminator Network, naming David T. Hui, inventor, and 
     U.S. Ser. No. 09/583,186, filed May 30, 2000, entitled: CMOS Small Signal Switchable Adjustable Impedance Terminator Network, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/580,789, filed May 30, 2000, entitled: CMOS Small Signal Switchable and Adjustable Terminator Network, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/583,188, filed May 30, 2000, entitled: CMOS Small Signal Switchable Impedance and Voltage Adjustable Terminator Network, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/580,805, filed May 30, 2000, entitled: CMOS Small Signal Switchable Impedance and Voltage Adjustable Terminator Network and Receiver Integration, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/583,680, filed May 30, 2000, entitled: CMOS Small Signal Switchable Impedance and Voltage Adjustable Terminator with Hysteresis Receiver Network, naming David T. Hui, inventor; and 
     U.S. Ser. No. 09/580,942, filed May 30, 2000, entitled: SOI Small Signal Terminated Hysteresis Receiver, naming David T Hui, inventor; and 
     U.S. Ser. No. 09/580,943, filed May 30, 2000, entitled: SOI Small Signal Terminated Receiver, naming David T. Hui, inventor. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to terminators which are applicable to metal oxide semiconductor (MOS) integrated circuit technology and which are particularly useful for terminator networks. 
     This related application(s) and the present application are owned by one and the same assignee, International Business Machines Corporation of Armonk, N.Y. 
     The descriptions set forth in these co-pending applications are hereby incorporated into the present application by this reference. 
     Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies. 
     BACKGROUND 
     For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4,748,426: entitled “Active termination circuit for computer interface use”, granted May 31, 1988 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat. No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM. 
     As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g. CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM&#39;s new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz. 
     The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed. 
     Also, a conventional CMOS receiver does not have good control on its threshold voltage to deal with small signals. It is therefore a need to set up a well balanced threshold voltage between the logic levels, and implement hysteresis in its receiver, so that maximum noise tolerance between logic levels can be achieved for this network and digital system. 
     SUMMARY OF THE INVENTION 
     The preferred embodiment of the invention provides a CMOS small signal terminated hysteresis receiver for a terminator network which allows setting up a well balanced threshold voltage between the logic levels of a terminator for a network, and to implement hysteresis in the network receiver, so that maximum noise tolerance between logic levels can be achieved for this network and digital system. The hysteresis receiver can receive small signals properly. The receiver has enlarged noise tolerance between upper and lower logic levels. 
     The terminator network is adapted for MOS that can match the characteristic impedance of the line. 
     The present invention also provides a terminator network which is fast and suitable for small signal swings and may also in a mixed technologies communication. 
     The combined terminator and receiver network has low current flow and low power consumption. 
     Still another objective of the present invention to provide a terminator network that provides ESD protection at the input of an attached circuit. 
     Other objects and advantages of the invention will be apparent from the specification. 
     These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates the piror art Resistor Terminator Network. 
     FIG. 2 illustrates the preferred embodiment of a new CMOS small signal terminated hysteresis receiver network. 
     FIG. 3 is a graph having two curves depicting input currents as a function of the input voltages for the CMOS small signal terminator network constructed according to the present invention and a ideal 50 ohm terminator. 
     FIG. 4 is a graph having curves depicting the input current as a function of the input voltages for the CMOS small signal terminator constructed according to the present invention and curves of the upper and lower power supply currents as a function of the input voltage. 
     FIG. 5 is a graph having curves depicting the input current as a function of the input voltages for the CMOS small signal terminator constructed according to the present invention and curves of its currents to the upper and lower power supplies as a function of the input voltages. Also having curves of the corresponding input current, and the currents to the upper and lower power supplies for an split resistor terminator as in the piror art. 
     FIG. 6 is a graph having curves of the power consumption as a function of input voltages for the CMOS small signal terminator constructed according to the present invention and the power consumption of a split resistor as in piror art. 
     FIG. 7 is a graph with a curves showing the output voltage as a function of input voltages for the CMOS small signal terminated hysteresis receiver constructed according to the present invention. 
    
    
     Our detailed description explains the preferred embodiments of my invention, together with advantages and features, by way of example with reference to the drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     As noted, prior art resistor terminators were used in prior art as shown in FIG.  1 . Where resistor  13  is connected to node  11  to the upper power supply VDD and the other end of resistor  13  is connected to the node  10  and is also connected in series to resistor  14 , The other end of resistor  14  is then connected to node  12  to the lower power supply VSS. The value of the resistors are set so that node  10  has a bias voltage equal to the center of the in coming signal swing and the parallel combination of the resistors matches the characteristic impedance Z 0  of the transmission line that it is connected to, so that no reflections will occur and a clean signal can be obtained. However, These resistor terminators cannot now be used in the high speed applications because of the significant power that is dissipated in them. It would also be very difficult to construct these resistor terminators on chips using the new sub-micron MOS technologies because of the high currents in this network to meet all the cooling and reliability requirements. 
     In describing the preferred embodiment of the present invention, reference will be made herein to FIG. 2 to FIG. 7 of the drawings. FIG. 2 shows a network  20  carrying signals from a first circuit  25  to a second circuit  24 . An input terminal  10  connects the terminator circuit  21  to the input circuit  24 . The first circuit  25  may be operating at a different voltages then the second circuit  24 . Generally, the terminating circuit  21  and the second circuit  24  will be constructed very close together physically in the same electronic system. In this invention, Circuit  21  and circuit  24  are integrated together so that it will be most efficient. The first circuit  25  communicating over net  20  may be remotely located in the same electronic system or even external to the electronic system in which the terminating circuit and the second circuit  24  are located. It is preferred that the electronic systems in which the circuits  21 ,  25  and  24  are located are digital systems as computer systems, and the network  20  may be connecting different components such as different processor or memory buses or data links or may be connecting different electronic components between two computer systems or other electronic systems which need to communicate data, digitized electrical signals or electrical signals. 
     In the terminator circuit  21  illustrated in FIG. 2 is comprised of a reference circuit  30  and an input circuit  31 . The reference circuit  30  generates two reference voltages on node  14  and node  15 . These two voltages can be produce independently on separate paths or a single path with series connected devices as shown in FIG. 2 as a prefer embodiment. This reference path is comprised of a series connected resistor  51  from the upper power supply  11  to node  15 , and from node  15  it is connected to the gate and drain of nfet  52  the source of nfet  52  is connected to node  100 , node  100  is then connected to the source of pfet  53 , the gate of pfet  53  is tie to its drain and both connected to node  14 , and from node  14  connected resistor  54  and the other end of resistor  54  is connected to the lower power supply  12  or around in this case. 
     Note that in the preferred embodiment node  100  is tuned to a voltage level equal to the center of the in coming voltage swing between the logic ‘1’ and ‘0’ voltage levels, from herein this center voltage will be call Vcenter. This Vcenter will set node  15  at a voltage which is a vt above the Vcenter and node  14  at a voltage which is a vt below Vcenter. Node  15  is also connected to the gate of nfet  16 . Node  14  is also connected to the gate of pfet  17 . The sources of nfet  16  and pfet  17  are tie together to the input terminal  10  or PAD, then it is connected to net  20 , where it then connects to the driving circuit  25  as stated in the beginning. The operation of this invention is as follows, When the terminal  10  is driven to rise above the Vcenter, The gate to source voltage in pfet  17  is driven to below vt and more, and it starts to turn-on and conduct current to  12  or ground, whereas gate to source of nfet  16  is below vt and therefore no conduction, no current will flow in nfet  16  to  11  or VDD. On the other hand When terminal  10  fall below Vcenter, The gate to source voltage of nfet  16  is above vt and turn-on to conduct current to  11  or the top power supply VDD. Now the pfet  17  is off since the gate to source voltage is above vt. 
     The preferred embodiment has a back to back gate to drain connected configuration of nfet  52  and pfet  53  in the reference circuit, and this tracks to its corresponding mirror like nfet  16  and pfet  17 , and therefore controls each of their turn on voltages and so no excessive through current in nfet  16  and pfet  17  will occur, and since at its logic states one of the input device will be off, and therefore achieve the claim of low power. Therefore it is best suited for a the small signal input operation. 
     The hysteris receiver is in circuit  24  which is integrated into the terminator circuit  21 . The receiver input device nfet  516  is mirror to nfet  16  with its gate connected to node  15 , its source to input terminal  10  and drain to node  521  and to drain of load device pfet  502  and the source of pfet  502  connects to node  11  or VDD, pfet  502  is bias “on” with its gate connected to node  12 . The other input device pfet  517  is mirrored to pfet  17 , with its gate connected to node  14  and its source to input terminal  10  and its drain connected to node  520  and to the drain of a load device nfet  501 , The nfet  501  is biased “on” with its gate connected to node  11 , The source of nfet  501  is connected to node  12 . Since the load devices nfet  501  and pfet  502  are biased “on” at all times, it could be replaced by resistors. Node  520  is then connected to the gate of nfet  504 , The source of nfet  504  is connected to node  12  and its drain connected to node  522 . The gate of pfet  503  is connected to node  521 , source to node  11  and drain to  522 . Node  522  is also connected to a two inverter latch which is made up of pfet  505  and nfet  506  for the first inverter, its output node  523  from the first inverter is connected to the input of the second inverter from pfet  507  and nfet  508 , The output of this inverter is feed back to node  522  to made the latch and the hysteris path of the receiver. Node  522  is then connected to the gates of the output inverter pfet  509  and nfet  510 . The inverter output then connected to the output terminal Z of the hysteris receiver circuit  24 . 
     When a logical “1” is driven to input terminal  10 , mirrored pfet  517  will turn on the same way pfet  17  in terminator circuit  21  turns on. It then pull up node  520  above the turn on voltage of nfet  504 , Nfet  504  then turns on and over comes the latch feed back pfet  507  and pull down node  522 . This then set the receiver output Z to “1” after the output inverter. The nfet  516  is off and node  521  will stay at vdd and pfet  503  will also be off. 
     When a logical “0” is driven to input terminal  10 , mirrored nfet  516  turns on the same way nfet  16  in the terminator circuit  21  turns on. It then pull down node  521  and turn on pfet  503 . The pfet  503  turns on will overcome the hysteris latch nfet  508  and node  522  will be pulled up to a logical “1” level. This then set the receiver output Z to “0” after the output inverter. Pfet  517  will be off and node  520  will sit at the same voltage as node  11  GND, and nfet  504  will also be off. 
     The terminator voltage levels are well set by the Vcenter in node  100  and mirrored into the receiver input devices by the references node  14  and node  15 . It will have less process variations. 
     The sizes of the devices in these paths will determine the amount of hysteris in this receiver to obtain a good noise tolerance and still have good performance. 
     The results of the small signal terminated hysteris receiver network as constructed according to the present invention are shown in the following figures. The center of the input voltage swing is at vdd/2 for this illustration. Other input voltage swing can be design as well by changing the resistors. 
     FIG. 3 is a graph having two curves depicting input currents as a function of the input voltages for the CMOS small signal terminator network constructed according to the present invention and a ideal 50 ohm split resistor terminator. As shown the impedance of the present invention can be match very closely to the ideal resistor terminator. 
     FIG. 4 is a graph having curves depicting the input current as a function of the input voltages for the CMOS small signal terminator constructed according to the present invention and curves of the upper and lower power supply currents as a function of the input voltage. The input current at the upper half cycle of the input voltage is directed to flow into the lower power supply, and current of the lower half cycle are directed to flow out from the upper power supply. Other then the bias current, there are no through current from the upper to the lower power supplies. 
     FIG. 5 is a graph having curves depicting the input current as a function of the input voltages for the CMOS small signal terminator constructed according to the present invention and curves of its currents to the upper and lower power supplies as a function of the input voltages. The FIG. 5 also has curves of the corresponding input current, and the currents to the upper and lower power supplies for an split resistor terminator as in the piror art. This shows the large difference in the power supply currents at and near the center of the swing between the piror art and the present invention. 
     FIG. 6 is a graph having curves of the power consumption as a function of input voltages for the CMOS small signal terminator constructed according to the present invention and the power consumption of a split resistor as in piror art. This shows the power which the prior art consumes is a lot more then the present invention in small signal applications. 
     FIG. 7 has a curve showing the output voltage as a function of input voltages switching at the Vcenter for the CMOS small signal terminated receiver constructed according to the present invention. 
     In terms of ESD protection, when the circuit described in the present invention is powered up, it has a low resistance path to one of the power supplies depending on the input voltage level, If the input terminal voltage move more then about 0.7 volts outside the upper or lower power supplies, the parasitic diodes and the parasitic bipolar transistor in the pfet  15  and nfet  16  also turn on to further reduce the input impedance, hence improving the performance of the ESD protection. This performance is so effective that an additional ESD protection device may not be necessary to protect this circuit or the input/output circuit connected to this terminal there after. The parasitic elements in pfet  15  and nfet  16  are active even when the devices are not powered which provides significant ESD protection during handing of the device. The implementation shown result in a clean signal on network  20  with no or minimum reflection and noise generated in the system and a fast, solid, clean and reliable small swing can be obtain for a point to point nets as well as a cleaner multiple drop net. This implementation provide the fastest transmission of data and signals with much lower power consumption as compared to split resistive termination networks. The combination of the small signal terminating network and receiver, providing both the termination to the net as well as the center voltage to the differential receiver is a perfect marriage to do small signal operations at high speeds. 
     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.