Abstract:
A printed circuit board having a signal plane with increased channel width for enhanced wireability. The printed circuit board has a top plane having component lands arranged in a grid, wherein the component lands include a first grouping arranged in a first diagonal, and a second grouping arranged in a second diagonal where the second diagonal is parallel and adjacent to the first diagonal, a plurality of offset lands placed within the first diagonal between the component lands therein, and a plurality of electrical connectors electrically coupling component lands in the second diagonal to adjacent offset lands in the first diagonal.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to printed wiring boards, and more particularly relates to a wireability enhancement for use on printed wiring boards. 
     2. Related Art 
     Printed wiring boards, circuit boards, and cards (hereinafter “PCB&#39;s”) typically comprise a plurality of “horizontally oriented” layers which include one or more “inner” signal planes (hereinafter “signal planes”) that include wiring patterns for delivering signals to various points along a horizontal plane within the PCB, a top plane for receiving components which, like the signal planes, may also include wiring patterns (i.e., the top plane may technically be considered an “outer” signal plane capable of delivering signals to various points on the top plane), and one or more power planes for providing power to various points on the PCB. Connections between and among the signal planes and top plane are made with vertical connections between conductive points or “lands,” which reside on the surface of each plane. The vertical connections, referred to as vias, are often implemented as plated through holes (PTH&#39;s). 
     With the advent of more and more complex PCB&#39;s, demands have been placed on signal plane designs to provide higher wiring densities or “wireability” in order to service the increasingly complex componentry on the top plane of such PCB&#39;s. Accordingly, the wireability of PCB&#39;s depends upon the size of the lands, the width of the wire, the space between the wires, the number of signal planes, and the distance between lands. The typical solution for achieving higher density wiring involves either shrinking of the size of the features on the PCB or increasing the number of signal planes. Unfortunately, these solutions generally lead to increased complexity and cost, and almost always adversely affect the PCB&#39;s electrical performance. 
     Assuming additional signal planes cannot be utilized, and it is impractical to further reduce the wire and land size, present designs for signal planes are strictly limited by a fixed channel width. This limitation is described with reference to a simplified example shown in FIGS. 1 and 2. FIG. 1 depicts an example of a top plane  10  of a multi-layered printed circuit board. The top plane  10  comprises a plurality of component lands  12  for receiving componentry, such as pseudo-component  18 . As noted, the top plane  10  could also comprise wiring (not shown) between and among the lands  12 . The component lands  12 , in this case, are spaced in a predetermined pattern. In this case, the pattern is a grid pattern commonly used in the art, such as that implemented with a ball grid array (BGA). Each component land  12  generally comprises a conductive area  14  for receiving a component lead or wire connection, and a via or plated through hole  16  for providing vertical connections to different layers of the PCB. The component lands  12  are generally arranged in a predetermined manner such that each land has a uniform spacing “x” with adjacent lands. Such a predetermined arrangement of lands is preferable because it allows for the easy attachment of components on the PCB. For example, pseudo-component  18  is shown with a plurality of connectors  20  located at predetermined positions that will readily match up with the component lands on the PCB. Consequently, if the arrangement of the circuit lands on the PCB were to be altered, the geometry of the components that are to be attached to the PCB would likewise need to be altered. Such an alteration would clearly be impractical as componentry, which typically comes from many different sources, must adhere to predetermined size specifications. Accordingly, PCB designs are generally required to conform to a particular arrangement with respect to the placement of component lands on the top plane. 
     In order to deliver a complex network of signals between and among components residing on a top plane of a PCB, an inner signal plane  21  such as that shown in FIG. 2 must be utilized. For each component land  12  on the top plane  10 , a corresponding signal land  13  on a signal plane  21  generally exists directly below the corresponding component land  12 . A via or PTH may then be used to interconnect the corresponding lands on different planes as required by the particular design. Accordingly, the arrangement of signal lands on the signal plane must generally coincide with the arrangement of component lands on the top plane. Thus, as depicted in FIG. 2, the arrangement of signal lands  13  on the signal plane  21  duplicates the grid depicted on the top plane  10  of FIG.  1 . Because wiring on the signal plane  21  must be routed between signal lands  13 , the wiring must pass within a channel space  22  having a maximum width of “x.” Therefore, as can be seen in FIG. 2, the wiring density  23  on the signal plane  21  is generally limited by a width “x,” which directly results from the arrangement of the component lands  12  on the top plane  10 . 
     As noted, given the need for a standard component geometry, the state-of-the-art dictates that the distance between the component lands  12  must be fixed. Accordingly, the wireability on a signal plane  21  has heretofore been limited by the fixed channel width available on the signal plane. Without some method of easily increasing the channel width size in signal plane designs, printed circuit boards will continue to have limited wiring densities. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the above-mentioned problems in the art by providing a multi-planed wiring board, comprising: (1) a signal plane having a plurality of signal lands positioned for enhanced wireability; (2) a top plane located in a co-planar manner above the signal plane and having a plurality of component lands positioned for receiving components of a standard geometry, wherein each component land on the top plane has a corresponding signal land on the signal plane, and wherein a subset of the signal lands on the signal plane do not reside directly below their corresponding component lands (i.e., they are horizontally offset for enhanced wireability); (3) a plurality of auxiliary lands located on the top plane, wherein the auxiliary lands are directly above the subset of horizontally offset signal lands; and (4) a plurality of horizontal connections electrically coupling auxiliary lands to component lands. 
     In addition, multiple auxiliary lands may be clustered together with a single component land on the top plane to prevent the fragmentation of the power plane. Fragmentation of the power plane is avoided since cluster will cause the required clearance holes in the power plane to overlap and therefore occupy less area. 
     It is therefore an advantage of the present invention to provide increased wireability within a signal plane without changing the geometry of the components on the PCB. 
     It is therefore a further advantage of the present invention to provide auxiliary lands on a top plane of a PCB to allow signal lands on a signal plane to be arranged for enhanced wireability. 
     It is therefore a further advantage of the present invention to cluster lands on a PCB in order to avoid the fragmentation of the power plane. 
     The foregoing and other objects, features and advantages of the invention will be more apparent in the following and more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The preferred exemplary embodiment of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements and: 
     FIG. 1 depicts a top plane of a printed circuit board; 
     FIG. 2 depicts a signal plane of the printed circuit board of FIG. 1; 
     FIG. 3 depicts a top plane of an improved circuit board in accordance with a preferred embodiment of the present invention; 
     FIG. 4 depicts a signal plane corresponding to the top plane of FIG. 3 in accordance with a preferred embodiment of the present invention; and 
     FIG. 5 depicts a power plane corresponding to the signal plane and top plane of FIGS. 2 and 3 in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIGS. 3-5, a simplified version of a multilayer PCB is depicted having a top plane  24 , a signal plane  50 , and a power plane  56 . It is understood that multilayer PCB&#39;s may be implemented with additional layers (e.g., multiple power and signal planes) and configurations, and such implementations are within the scope of this invention. Referring now to FIG. 3, a top plane  24  of a simple PCB in accordance with a preferred embodiment of this invention is depicted. The top plane  24  includes a plurality of component lands (e.g.,  25 - 28  and  30 - 34 ) arranged in a grid-like manner for receiving components of a predetermined geometry similar to that shown in FIG.  1 . The PCB may comprise a BGA structure, or any other structure that utilizes surface lands for the attachment of components. The top plane  24  further comprises a plurality of offset or auxiliary lands (e.g.,  36  and  38 ) and a plurality of electrical connectors (e.g.,  44  and  46 ) connecting certain ones of the component lands to certain ones of the offset lands. In the preferred embodiment depicted in FIG. 3, the component lands are grouped into adjacent diagonals  47 ,  48 , each having lands suitable for receiving a component. In the first diagonal  47 , each of the component lands  30 ,  31 ,  32 ,  33  and  34  may include a vertical connector  35  for delivering electrical signals to the planes below the top plane  24 . The vertical connectors  35  may comprise a via, PTH, or any other type of vertical connection system. The second diagonal  48  comprises a group of component lands,  25 ,  26 ,  27  and  28  that do not include vertical connections. Thus, the component lands in the second diagonal  48  do not include direct vertical connections to adjacent planes. Instead, a system of offset lands  36  and  38  are utilized to provide vertical connections at offset locations. By offsetting the vertical connections for the component lands in the second diagonal  48 , more robust wiring can be achieved and implemented at the signal plane level. 
     Accordingly, in the preferred embodiment, signals are delivered between component lands in the second diagonal  48  and corresponding lands on adjacent planes (e.g., a signal plane) with (1) offset lands  36 ,  38  on the top plane  24 , (2) electrical connectors  44 ,  46  (residing on the same horizontal plane as the top plane  24 ) connecting the component lands  27 ,  28  to the offset lands  36 ,  38 , and (3) vertical connections  40 ,  42  connecting the offset lands  36 ,  38  to the corresponding lands  53 ,  55  on an adjacent plane (see FIG.  4 ). 
     As such, the second diagonal  48  provides operational component lands for receiving components of a standard geometry, but does not provide direct vertical connections to adjacent planes. Instead, electrical connections are shifted over or offset into the first diagonal  47 , where their signals can be routed in a vertical direction. Therefore, from the componentry standpoint, no changes are required since top plane  24  can still receive components of a standard geometry, such as component  18 ′ shown in phantom. Thus, standard BGA land arrangements and the like may still be utilized. 
     The advantages of offsetting the vertical connections from second diagonal  48  to first diagonal  47  are evident in FIG. 4, which depicts the corresponding signal plane  50  for the top plane  24  of FIG.  3 . With the aforementioned alteration to the top plane  24 , the corresponding signal plane  50  will comprise a plurality of diagonal channels  52  that have a usable channel width of x{square root over (2)}, as compared to the prior art, which provided a usable channel width of just “x” (x being the distance between adjacent component lands on the corresponding top plane  24 ). Thus, signal plane  50  comprises channels  52  having a greater wiring density since a greater number of wires  54  can be run in the channels  52  on the signal plane  50 . 
     Referring back to FIG. 3, it can be seen that the offset lands (e.g.,  36  and  38 ) are clustered around every other component land  31  and  33  in the first diagonal  47 . The result is a first diagonal having a single component land  30 , an adjacent cluster of three lands including component land  31 , a single component land  32 , a second cluster of three lands including component land  33 , a single component land  34 , etc. By clustering the lands in such a manner, performance on the power plane is maintained in a manner explained below. 
     FIG. 5 depicts a power plane  56  corresponding to the top plane  24  of FIG.  3  and signal plane  50  of FIG.  4 . The power plane  56  is generally a sheet of conductive material used to provide electrical power to predetermined component lands on the top plane or signal lands on the signal plane. Power is delivered with the use of vias and PTH&#39;s (not shown) to those points where power is required. Because the power plane  56  may be sandwiched between signal planes, the power plane  56  must include numerous clearance holes  58 ,  60  to allow for the unimpeded passage of vertical connectors (e.g., vias and PTH&#39;s) that deliver signals between signal planes and the top plane. In particular, the clearance holes  58 ,  60  must be large enough to guard against inadvertent electrical short circuits between the power plane  56  and vertical connectors carrying signals that must pass through the plane  56 . Thus, a typical power plane will look much like a slice of “swiss cheese” having numerous holes drilled therethrough to provide this necessary clearance. However, too many holes in the plane  56 , or in a portion of the plane  56 , will decrease the dielectric properties of the plane  56  and result in decreased performance. 
     By clustering the offset lands  36 ,  38  with the component lands  31 ,  33  in the first diagonal  47  on the top plane  24 , the resultant clearance holes  58 ,  60  on the power plane take up less area due to the fact that the clearance holes will overlap and create a single triplet hole  58 . The advantage of having such a triplet hole  58  (versus a plurality of equally spaced signal holes) is that the power plane  56  retains a greater surface area of conductive material. This arrangement results in a more uniform power plane with greater mechanical integrity and better capacitive characteristics. If for instance the power plane were to have a plurality of single holes  60 , rather than the triplets  58 , the capacitive value of the power plane would decrease creating a potential loss of electrical signals on the board. By grouping the holes in such manner, the dielectric properties of the power plane  56  are retained. 
     The foregoing description of the preferred embodiments of the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of above teachings. For example, this invention need not be implemented to create diagonal channels on the signal plane, but could be implemented to create user defined channels of varying dimensions and shapes. Moreover, the clustering of lands could be done with various numbers of lands and different positioning to achieve a specific need of a PCB. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.