Abstract:
A device controls internal voltage. Increased reliability of a semiconductor memory device is obtained by increasing or decreasing a level of internal reference voltage according to change of the device. Fuse ROMs generate fuse signals having different levels according to a cutting condition of each fuse. A bit counter performs up/down counting operation in response to a count control signal after setting the fuse signals to initial values in response to a set signal and generates counter output signals which are higher or lower than the initial values by a counting number. A decoder decodes the counter output signals and activates one of switching signals. A reference voltage selector provides a trimming level of internal reference voltage in response to the switching signals and generating reference voltage.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a device for controlling internal voltage; and, more particularly, to a scheme for increasing reliability of a semiconductor memory device by increasing or decreasing a level of internal reference voltage according to changes of the device.  
       BACKGROUND  
       [0002]     Characteristics or performances of semiconductor memory devices are not equal to those of each other because conditions or circumstances for producing plural semiconductor memory devices in wafers, e.g., mass production, are not exactly and continuously kept. Particularly circumstance changes on fabrication process, i.e., PVT (Process, Voltage and Temperature), according to each memory chip are considered in order to revise the reference voltage VREF to target level.  
         [0003]      FIG. 1  is a block diagram of a conventional internal voltage control device.  
         [0004]     The conventional internal voltage control device includes a fuse ROM block  10 , a decoder  20 , an internal reference generator  30 , a reference voltage selector  40  and a voltage comparator  50 .  
         [0005]     Each fuse ROM is provided with a fuse F, inverters IV 1  to IV 3  and a NMOS transistor N. The fuse F is connected between supply voltage and the NMOS transistor N. The NMOS transistor N connected between the fuse F and ground voltage receives a fuse enable signal FEN through a gate. The first and the second inverters IV 1  and IV 2  latch output of the fuse F. The third inverter IV 3  inverting output of the latch outputs plural fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt;. Herein, i is a positive integer.  
         [0006]     In addition, the decoder  20  decodes the plural fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt; and outputs plural switching signals SW&lt; 0 &gt; to SW&lt;k−1&gt;. Herein, k is positive integer. The internal reference generator  30  generates internal reference voltage PRE_VREF. The reference voltage selector  40  trims the internal reference voltage PRE_VREF according to the plural switching signals SW&lt; 0 &gt;-SW&lt;k−1&gt; and outputs reference voltage VREF.  
         [0007]     The reference voltage selector  40  is provided with k number of NMOS transistors N 0  to Nk−1, k+1 number of resisters RO to Rk connected in series. The plural NMOS transistors NO to Nk−1 respectively connected between the plural resisters RO to Rk and an output stage of the reference voltage VREF receive corresponding switching signal through gates. Accordingly the plural NMOS transistors are switched selectively.  
         [0008]     The voltage comparator  50  is provided with an amplifier  51  and first and second resisters Ra to Rb. The amplifier  51  compares the reference voltage VREF and output of the resisters Ra to Rb, generating internal voltage VINT. The resisters Ra to Rb divide the internal voltage VINT through resister-division and output divided internal voltage VINT to the amplifier  51 .  
         [0009]     The conventional operation process of the internal voltage control device of  FIG. 1  is described below.  
         [0010]     When the fuse enable signal FEN is activated, the fuse ROMs are initialized. The NMOS transistor N turns on and node AA maintains low level during high pulse period of the fuse enable signal FEN. When the fuse enable signal FEN has low value, the node AA has high value through the fuse F. If the fuse F is cut electrically or physically, the node AA is disconnected with the supply voltage and the node AA has low value. As a result, fuse signals FU are controlled. Each fuse signal, i.e., the output of fuse ROM, is output at a logic high state if the fuse F is cut. On the contrary, a fuse signal having a logic low state is output in case that the fuse F is not cut.  
         [0011]     Thereafter, the decoder  20  decodes the plural fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt; and outputs the plural switching signals SW&lt; 0 &gt; to SW&lt;k−1&gt;. The decoder  20  activates a corresponding signal of the plural switching signal SW&lt; 0 &gt; to SW&lt;k−1&gt; according to the fuse signals output high.  
         [0012]     The internal reference generator  30  outputs an internal reference voltage PRE_VREF having a stably settled level regardless of an external voltage level and a chip temperature. However, the internal reference generator  30  cannot adjust a level of the internal reference voltage PRE_VREF in response to process change in fabrication. Accordingly each reference voltage PRE_VREF generated in each memory chip has a different level.  
         [0013]     In order to trim the internal reference voltage PRE_VREF, the reference voltage selector  40  turns on one of the plural NMOS transistors N 0  to Nk−1 according to the plural switching signals SW&lt; 0 &gt; to SW&lt;k−1&gt;, outputting a reference voltage VREF. Thereafter, the voltage comparator  50  outputs the internal voltage VINT having a predetermined voltage level based on the reference voltage VREF.  
         [0014]     The internal voltage VINT is defined as follows. 
 
VINT=(( Ra+Rb )/ Rb )*VREF 
 
         [0015]     The constant reference voltage VREF is required to output constant internal voltage VINT coping with process change. The reference voltage selector  40  switches the plural NMOS transistor N 0  to Nk−1 selectively, generating constant level of reference voltage VREF.  
         [0016]     In the event that level of the internal reference voltage PRE_VREF is high, a NMOS transistor Nk, herein k is a large number, turns on. In the event that level of the internal reference voltage PRE_VREF is low, a NMOS transistor Nk, herein k is a small number, turns on. Constant reference voltage VREF is output. For the above described operation, one of the k number switching signals SW&lt; 0 &gt; to SW&lt;k−1&gt; is activated by the operation of the fuse ROM block  10  and the decoder  20  after the reference voltage VREF or the internal voltage VINT is monitored in the manufactured chip.  
         [0017]     The step for changing internal voltage through reliability or a worst condition test in a quality control process of conventional semiconductor memory chip is required. However, the level of the pre-programed internal voltage VINT is not changed in a conventional device controlling an internal voltage. Generating a stable internal voltage based on process changes in a semiconductor memory device is difficult.  
       SUMMARY OF THE INVENTION  
       [0018]     It is, therefore, an object of the present invention to provide a voltage controller for increasing or decreasing a level of internal reference voltage, which is programmed as a predetermined level, by using a counter to cope with process changes of a semiconductor memory device and increasing a reliability of the semiconductor memory device.  
         [0019]     In accordance with an aspect of the present invention, there is provided an internal voltage controller, including a fuse ROM block for generating plural fuse signals having different levels according to a cutting condition of each fuse, a bit counter for performing up/down counting operation in response to a count control signal after setting the plural fuse signals to initial values in response to a set signal and for generating plural counter output signals which are higher or lower than the initial values by counting number, a decoder for decoding the plural counter output signals and activating one of plural switching signals and a reference voltage selector for controlling level of internal reference voltage in response to the switching signals and generating reference voltage. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0021]      FIG. 1  is a block diagram of a conventional internal voltage control device;  
         [0022]      FIG. 2  is a block diagram of an internal voltage control device in accordance with the present invention;  
         [0023]      FIG. 3  is a schematic circuit diagram of a bit counter shown in  FIG. 2 ;  
         [0024]      FIG. 4  is a timing diagram illustrating an up-counting operation of the internal voltage control device shown in  FIG. 2 ; and  
         [0025]      FIG. 5  is a timing diagram illustrating a down-counting operation of the internal voltage control device shown in  FIG. 2 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Hereinafter, a semiconductor device in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0027]      FIG. 2  is a block diagram of an internal voltage control device in accordance with the present invention.  
         [0028]     The internal voltage control device includes fuse ROM block  100 , a bit counter  200  a decoder  300 , a reference voltage selector  500  and a voltage comparator  600 .  
         [0029]     The fuse ROM block  100 , the reference voltage selector  500  and the voltage comparator  600  have the same composition as the conventional device described above, and are described with the same characters used in the conventional device.  
         [0030]     The each fuse ROM is provided with a fuse F, inverters IV 1  to IV 3  and a NMOS transistor N. The fuse F is connected between supply voltage and the NMOS transistor N. The NMOS transistor N connected between the fuse F and ground voltage receive a fuse enable signal FEN through a gate. The first and the second inverters IV 1  and IV 2  latch output of the fuse F. The third inverter IV 3  inverting output of the latch outputs plural fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt;. Herein, i is a positive integer.  
         [0031]     In addition, the bit counter  200  receives i number of fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt; from the fuse ROM block  100  and outputs j number of counter output signals CU&lt; 0 &gt; to CU&lt;j−1&gt; according to each count control signal TUPCNT, count signal TCNT and set signal SET. Herein, j is larger than i and i and j are natural numbers. The bit number of outputs from the bit counter  200  is larger than the bit number of inputs from the fuse ROM block  100 . The embodiment of the present invention is explained wherein j which is larger than i by 2. The bit counter  200  initializes programmed values in the fuse ROM block  100  and performs a up/down counting operation.  
         [0032]     Continuously, the decoder  300  decodes the j number of counter output signals CU&lt; 0 &gt; to CU&lt;i+1&gt; and outputs plural switching signals SW&lt; 0 &gt; to SW&lt;k−1&gt;. The internal reference generator  400  generates internal reference voltage PRE_VREF. The reference voltage selector  500  trims the internal reference voltage PRE_VREF according to the plural switching signals SW&lt; 0 &gt; to SW&lt;k−1&gt; and outputs reference voltage VREF.  
         [0033]     The reference voltage selector  500  is provided with k number of NMOS transistors N 0  to Nk−1, k+1 number of resisters R 0  to Rk connected in series. The plural NMOS transistors N 0  to Nk−1 respectively connected between the plural resisters R 0  to Rk and an output stage of the reference voltage VREF receive corresponding switching signal through gates. Accordingly the plural NMOS transistors are switched selectively.  
         [0034]     The voltage comparator  600  is provided with an amplifier  51  and first and second resisters Ra to Rb. The amplifier  51  compares the reference voltage VREF and output of the resisters Ra to Rb, generating internal voltage VINT. The resisters Ra to Rb divide the internal voltage VINT through resister-division and output divided internal voltage VINT to the amplifier  51 .  
         [0035]      FIG. 3  is a schematic circuit diagram of the bit counter  200  shown in  FIG. 2 .  
         [0036]     The bit counter  200  is provided with plural flip-flops F/F&lt; 1 &gt; to F/F&lt;i+2&gt; connected in series. A first flip-flop F/F&lt; 1 &gt; receives a count signal TCNT. The plural flip-flops F/F&lt; 1 &gt; to F/F&lt;i&gt; receive the plural fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt; input from fuse ROM block  100 .  
         [0037]     The supply voltage VDD and the ground voltage VSS are set to initial value respectively in last two flip-flops F/F&lt;i&gt; and F/F&lt;i+1&gt;. Accordingly, the counter output signal CU&lt;i&gt; has one value and the counter output signal CU&lt;i+1&gt; has zero value in initial operation. When all initial values of the fuse signals are zero, 2 i−1  number of down counting is performed. When all initial values of the fuse signals are one, 2 i−1  number of up counting is performed.  
         [0038]     Each flip-flop F/F&lt; 1 &gt; to F/F&lt;i+2&gt; receives high pulse in response to activation of the set signal SET. The plural fuse signals FU&lt; 0 &gt; to FU&lt;i−1&gt; input from fuse ROM block  100  are stored as an initial value of each counter in the activation period. From the initial value, the each flip-flops F/F&lt; 1 &gt; to F/F&lt;i+2&gt; perform up-counting or down-counting operation according to the count control signal TUPCNT and output the plural counter output signals CU&lt; 0 &gt; to CU&lt;i+1&gt;.  
         [0039]     Through the plural counter output signals CU&lt; 0 &gt; to CU&lt;i+1&gt;, it is possible to generate reference voltage VREF which is higher or lower than a reference voltage programmed in fuse ROM block  100  by counting-number.  
         [0040]      FIG. 4  is a timing diagram illustrating the up-counting operation of the internal voltage control device shown in  FIG. 2 . As an example embodiment of the present invention, the case wherein i is 3 is explained.  
         [0041]     When the count control signal TUPCNT becomes logic high level and the count signal TCNT is input, the bit counter  200  performs an up-counting operation from an initialized value. The plural flip-flops perform a counting operation in synchronization with a falling edge of the count signal TCNT. How many the count signal TCNT is toggled means the number of up-counting. A code which is higher than a programmed value in the fuse block by counting-number could be generated.  
         [0042]      FIG. 5  is a timing diagram illustrating the down-counting operation of the internal voltage control device shown in  FIG. 2 . As an example embodiment of the present invention, the case where i is 3 is explained.  
         [0043]     When the count control signal TUPCNT becomes logic low level and the count signal TCNT is input, the bit counter  200  performs a down-counting operation from an initialized value. The plural flip-flops perform a counting operation in synchronization with a rising edge of the count signal TCNT. How many times the count signal TCNT is toggled corresponds to the number of down-counting. A code which is lower than a programmed value in the fuse block by counting-number could be generated.  
         [0044]     In the present invention, a level of the internal voltage VINT adjusted based on process change could be increased or decreased preferredly. In a conventional device, different programmed codes are used in the fuse ROM block in order to control the internal voltage to a target level. In the present invention, however, levels programmed by the different codes can be controlled higher or lower in response to a counting-number. Thus a stable internal voltage can be generated from a lot of chips fabricated under process changes.  
         [0045]     As described above, the present invention is used in an embodiment of worst condition and stress mode for distinguishing inferior goods on production of numerous semiconductor memory chips, experiment to generate optimum internal voltage or another embodiment of internal voltage required at particular timing of system. Further the present invention improves reliability and test/screen abilities of the semiconductor device. The present invention can be efficient in easily controlling internal voltage according to a system requirement not only in a production of solitary semiconductor memory chip but also in other applications such as Embedded and System On Chip.  
         [0046]     The present application contains subject matter related to Korean patent applications Nos. 10-2005-0091571 and 10-2006-0040697, filed in the Korean Patent Office on Sep. 29, 2005 and May 4, 2006, respectively, the entire contents of which are incorporated herein by reference.  
         [0047]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.