Abstract:
An inverting circuit is disclosed. The inverting circuit includes a pull-up unit including first, second, and third terminals. The first terminal receives a first control signal, and the third terminal is connected to a signal output terminal and outputs a first level signal. The inverting circuit also includes a pull-down unit including fourth, fifth, and sixth terminals. The fourth terminal is connected to the second terminal of the pull-up unit, and the fifth terminal receives a second control signal. In addition, the sixth terminal is connected to the signal output terminal and outputs a second level signal. The inverting circuit also includes a first capacitor, connected to the second terminal of the pull-up unit and the fourth terminal of the pull-down unit, and to the third terminal of the pull-up unit and the sixth terminal of the pull-down unit.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present application is a divisional application of U.S. patent application Ser. No. 14/526,505, filed on Oct. 28, 2014, which claims priority to Chinese Patent Application No. 201410309278.7, filed with the State Intellectual Property Office of People&#39;s Republic of China on Jun. 30, 2014 entitled “OLED INVERTING CIRCUIT AND DISPLAY PANEL”, the content of all of which is incorporated herein by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to the technical field of Organic Light Emitting Display (OLED) display, and in particular to an OLED inverting circuit and a display panel. 
       BACKGROUND 
       [0003]    Recently, in the field of display device, a current-driven optical device has been developed, the light intensity of which varies with a value of the current flowing there through. For example, there is a display device in which an Organic Light Emitting Device (OLED) is adopted as a light emitting device for a pixel. Different from a liquid crystal device, the OLED is a self-luminescence device. In a display device in which the OLED is adopted, classification of a color is obtained by controlling the current in the OLED. 
         [0004]    As with a liquid crystal display, a driving system in the OLED may be a passive matrix system or an active matrix system. The passive matrix system has a simple structure; however, it is difficult to achieve a display device with large size and high resolution by adopting the passive matrix system. Therefore, the development of the active matrix system is popular. In the active matrix system, a transistor is driven to control the current in the light emitting device provided for each pixel. 
         [0005]    Presently, in designing an Active Matrix Organic Light Emitting Diode (AMOLED), especially a large-size substrate, unevenness of the current in the OLED is caused due to the unevenness and instability of a Thin Film Transistor (TFT) during its manufacturing process. To offset the threshold voltage shift (Vth Shift) due to the unevenness of the TFT during the manufacturing process of a backplane, and the instability of the TFT due to turning on a bias voltage for a long time, it is necessary to design a compensation circuit. In the conventional art, a P-type Metal Oxide Semiconductor (Pure PMOS) driving circuit is used, and the driving circuit outputs an effective low level; but during node initialization, threshold detection and data inputting, the OLED device needs to be turned off. Due to the single PMOS, the Pure PMOS is turned on in the case of a low voltage of the gate electrode, and turned off in the case of a high voltage of the gate electrode. The Pure PMOS driving circuit generally outputs effective low level. Therefore the signal output from the Pure PMOS driving circuit needs to be inverted, so that the OLED device is turned off. The inverting of the signal is achieved by a light emitting-control led (EMIT) driving circuit in the conventional art. 
         [0006]    To achieve the inversion into a high level from a low level, an inverter is proposed in the conventional art, the structural diagram of which is shown in  FIG. 1   a.  The inverter includes N-type TFT and a P-type TFT. A gate electrode of the P-type TFT is connected to a gate electrode of the N-type TFT, and is connected to an input terminal IN together with the gate electrode of the N-type TFT. A source electrode of the P-type TFT is connected to a high-voltage signal (VGH). A drain electrode of the N-type TFT is connected to a low-voltage signal (VGL). A drain electrode of the P-type TFT is connected to a source electrode of the N-type TFT, and is connected to an output terminal (OUT) together with the source electrode of the N-type TFT.  FIG. 1 b    is a control timing diagram of the CMOS inverting circuit in  FIG. 1   a.  It can be seen from  FIG. 1 b    that when the IN is in high level, the P-type TFT is turned off, the N-type TFT is turned on, and the OUT outputs a low level signal; and when the IN is in a low level, the P-type TFT is turned on, the N-type TFT is turned off, and the OUT outputs a high-level signal. Since such PMOS inverter has both the P-type TFT and the N-type TFT, the manufacturing process is complicated, and the cost is high as compared with the pure P-type inverter or the pure N-type inverter. 
         [0007]    To achieve the inversion into a high level from a low level, another inverter is proposed in the conventional art, the structural diagram of which is shown in  FIG. 2 a   . The inverter includes two P-type TFTs, i.e., a first TFT and a second TFT. A gate electrode of the first TFT is connected to an input terminal IN, a source electrode of the first TFT is connected to a high-voltage signal (VGH), and a drain electrode of the first TFT is connected to an output terminal (OUT). A gate electrode and a drain electrode of the second TFT each are connected to a low-voltage signal (VGL), and a source electrode of the second TFT is connected to the OUT.  FIG. 2 b    is a control timing diagram of the pure PMOS inverting circuit in  FIG. 2 a   . It can be seen from  FIG. 2 b    that when the IN inputs high level, the first TFT is turned off, the OUT outputs low level due to the Diode connection manner of the second TFT (in which the gate electrode and the drain electrode of the second TFT each are connected to the low-voltage signal VGL), and the voltage of the low level is higher than the VGL by Vth. When the IN is in low level, the first TFT and the second TFT each are turned on, the OUT outputs high level. However, in the above circuit, the OUT is connected to both the VGH and the VGL, and if the TFT is turned on/off completely, the OUT is connected to either VGH or VGL, and the OUT takes the VGH as the high voltage and the VGL as the low voltage. The above circuit has the problem that the two TFTs are turned on at the same time, and with this, the OUT outputs the intermediate level between the VGH and the VGL due to the voltage-division function. That is to say, the high/low output level is between the VGH and the VGL, which is not enough, then the power supply continuously supplies power, the power consumption is increased. Further, since the output level is not enough (input ranges from −5V to 10V, and output ranges from −4.43V to 5.07V), the TFT in the pixel cannot be controlled effectively, so that the compensation circuit cannot work effectively. 
       SUMMARY 
       [0008]    One inventive aspect is an inverting circuit applicable to an active matrix organic light emitting display panel. The inverting circuit includes a pull-up unit including a first power supply input terminal, where the first power supply input terminal is configured to receive a first voltage signal. The pull-up unit also includes first, second, and third terminals. The first terminal is configured to receive a first control signal, and the third terminal is electrically connected to a signal output terminal and is configured to output a first level signal. The inverting circuit also includes a pull-down unit including a second power supply input terminal, and fourth, fifth, and sixth terminals. The fourth terminal is electrically connected to the second terminal of the pull-up unit, the second power supply input terminal is configured to receive a second voltage signal, and the fifth terminal is configured to receive a second control signal. In addition, the sixth terminal is electrically connected to the signal output terminal and is configured to output a second level signal. The inverting circuit also includes a first capacitor, where a first terminal of the first capacitor is electrically connected to the second terminal of the pull-up unit and the fourth terminal of the pull-down unit, and a second terminal of the capacitor is electrically connected to the third terminal of the pull-up unit and the sixth terminal of the pull-down unit. 
         [0009]    Another inventive aspect is a display panel, including an inverting circuit. The inverting circuit includes a pull-up unit including, a first power supply input terminal, where the first power supply input terminal is configured to receive a first voltage signal. The pull-up unit also includes first, second, and third terminals. The first terminal is configured to receive a first control signal, and the third terminal is electrically connected to a signal output terminal and is configured to output a first level signal. The inverting circuit also includes a pull-down unit including a second power supply input terminal, and fourth, fifth, and sixth terminals. The fourth terminal is electrically connected to the second terminal of the pull-up unit, the second power supply input terminal is configured to receive a second voltage signal, and the fifth terminal is configured to receive a second control signal. In addition, the sixth terminal is electrically connected to the signal output terminal and is configured to output a second level signal. The inverting circuit also includes a first capacitor, where a first terminal of the first capacitor is electrically connected to the second terminal of the pull-up unit and the fourth terminal of the pull-down unit, and a second terminal of the capacitor is electrically connected to the third terminal of the pull-up unit and the sixth terminal of the pull-down unit. 
         [0010]    Another inventive aspect is a driving method for an inverting circuit, where The inverting circuit includes a pull-up unit including a first power supply input terminal, where the first power supply input terminal is configured to receive a first voltage signal, the pull-up unit also includes first, second, and third terminals. The first terminal is configured to receive a first control signal, and the third terminal is electrically connected to a signal output terminal and is configured to output a first level signal. The inverting circuit also includes a pull-down unit including a second power supply input terminal, and fourth, fifth, and sixth terminals. The fourth terminal is electrically connected to the second terminal of the pull-up unit, the second power supply input terminal is configured to receive a second voltage signal, and the fifth terminal is configured to receive a second control signal. In addition, the sixth terminal is electrically connected to the signal output terminal and is configured to output a second level signal. The inverting circuit also includes a first capacitor, where a first terminal of the first capacitor is electrically connected to the second terminal of the pull-up unit and the fourth terminal of the pull-down unit, and a second terminal of the capacitor is electrically connected to the third terminal of the pull-up unit and the sixth terminal of the pull-down unit. The first transistor, the second transistor, the third transistor and the fourth transistor each are P-type transistors. The first terminal of the pull-up, unit is a level signal input terminal, the second terminal of the pull-up unit is a first electrode of the second transistor, the third terminal of the pull-up unit is a first electrode of the first transistor, the fourth terminal of the pull-down unit is a third electrode of the fourth transistor, the fifth terminal of the pull-down unit is a clock signal input terminal, and the sixth terminal of the pull-down unit is a third electrode of the third transistor. The driving method includes: during a first stage T 1 , a low-level signal is input into the level signal input terminal, a high-level signal is input into the clock signal input terminal, the pull-up unit is turned on and the pull-down unit is turned off by turning on the first transistor and the second transistor and turning off the third transistor and the fourth transistor. In addition, a high-level signal from the first voltage signal is transmitted to the second electrode of the third transistor and to the signal output terminal. The third transistor is turned off, and a high-level signal is output from the signal output terminal steadily. During a second stage T 2 , a high-level signal is input into the level signal input terminal, a low-level signal is input into the clock signal input terminal, the pull-up unit is turned, off and the pull-down unit is turned on by turning off the first transistor and the second transistor and turning on the third transistor and the fourth transistor. In addition, a low-level signal input into the second power supply input terminal is transmitted to the second electrode of the third transistor via the fourth transistor, the third transistor is turned on, and the fourth transistor is in an on-state until a level of the second electrode of the third transistor becomes VSS+Vth. Furthermore, an output signal from the signal output terminal is changed into a low-level signal from a high-level signal as a result of the first electrode of the third transistor being connected to the second power supply input terminal, a level of the second electrode of the third transistor is further pulled down due to a coupling of the first capacitor, the third transistor is turned on, and a low-level signal input into the second power supply input terminal is transmitted to the signal output terminal integrally. During a third stage T 3 , the first transistor, the second transistor and the fourth transistor each are turned off, the low level of the second electrode of the third transistor during the second stage T 2  is maintained due to the first capacitor, the third transistor maintains an on-state, and the signal output terminal maintains a low-level signal. During a fourth stage T 4 , in response to a low-level signal being input into the clock signal input terminal, an electrode of the fourth transistor connected to the second electrode of the third transistor becomes a drain electrode due to the low level of the second electrode of the third transistor, the fourth transistor is in an off-state, the second electrode of the third transistor maintains the low level due to the first capacitor, the third transistor keeps in the on-state, and the third transistor continues transmitting the low-level signal to the signal output terminal. 
         [0011]    Another inventive aspect is a driving method for an inverting circuit. The inverting circuit includes a pull-up unit including a first power supply input terminal, where the first power supply input terminal is configured to receive a first voltage signal. The pull-up unit also includes first, second, and third terminals. The first terminal is configured to receive a first control signal, and the third terminal is electrically connected to a signal output terminal and configured to output a first level signal. The inverting circuit also includes a pull-down unit including a second power supply input terminal, and fourth, fifth, and sixth terminals. The fourth terminal is electrically connected to the second terminal of the pull-up unit, the second power supply input terminal is configured to receive a second voltage signal, and the fifth terminal is configured to receive a second control signal. In addition, the sixth terminal is electrically connected to the signal output terminal and is configured to output a second level signal. The inverting circuit also includes a first capacitor, where a first terminal of the first capacitor is electrically connected to the second terminal of the pull-up unit and the fourth terminal of the pull-down unit, and a second terminal of the capacitor is electrically connected to the third terminal of the pull-up unit and the sixth terminal of the pull-down unit. The first transistor, the second transistor, the third transistor and the fourth transistor each are P-type transistors. The first terminal of the pull-up unit is a level signal input terminal, the second terminal of the pull-up unit is a first electrode of the second transistor, the third terminal of the pull-up unit is a first electrode of the first transistor, the fourth terminal of the pull-down unit is a third electrode of the fourth transistor, the fifth terminal of the pull-down unit is a clock signal input terminal and the sixth terminal of the pull-down unit is a third electrode of the third transistor. The driving method includes: during a first stage T 1 , a high-level signal is input into the level signal input terminal, a low-level signal is input into the clock signal input terminal, the pull-down unit is turned on and the pull-up unit is turned off by turning off the first transistor and the second transistor and turning on the third transistor and the fourth transistor, a low-level signal from the second voltage signal is transmitted to the second electrode of the first transistor and to the signal output terminal, the first transistor is turned off, and a low-level signal is output from the signal output terminal. During a second stage T 2  a low-level signal is input into the level signal input terminal, a high-level signal is input into the clock signal input terminal, the pull-down unit is turned off and the pull-up unit is turned on by turning on the first transistor and the second transistor and turning off the third transistor and the fourth transistor, a high-level signal input into the first power supply input terminal is transmitted to the second electrode of the first transistor via the second transistor, the first transistor is turned on, the second transistor maintains an on-state until a level of the second electrode of the first transistor becomes VDD−Vth, an output signal from the signal output terminal is changed into a high-level signal from a low-level signal as a result of the first electrode of the first transistor being connected to the first power supply input terminal, a level of the first terminal of the first capacitor, and a level of the second electrode of the first transistor are further pulled up due to a coupling of the first capacitor, the first transistor is turned on, the high-level signal input into the first power supply input terminal is transmitted to the signal output terminal integrally. During a third stage T 3  the second transistor, the third transistor, and the fourth transistor each are turned off, the high level of the second electrode of the first transistor during the second stage T 2  is maintained due to the first capacitor, the first transistor remains in an on-state, and the signal output terminal keeps outputting a high-level signal. During a fourth stage T 4  when a high-level signal is input into the clock signal input terminal, an electrode of the second transistor connected to the second electrode of the first transistor becomes a source electrode due to the high level of the second electrode of the first transistor, the second transistor is in an off-state, the second electrode of the first transistor remains at high level due to the first capacitor, the first transistor remains in the on-state, and the first transistor continues transmitting the high-level signal to the signal output terminal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    In order to illustrate the technical solutions according to the embodiments of the present invention or in the prior art more clearly, drawings to be used in the description of the prior art or the embodiments will be described briefly hereinafter. Apparently, the drawings described hereinafter are only a few of embodiments of the present invention, and other drawings may be obtained by those skilled in the art according to those drawings without creative labor. 
           [0013]      FIG. 1 a    is a structural diagram of a CMOS inverting circuit in the conventional art; 
           [0014]      FIG. 1 b    is a control timing diagram of the CMOS inverting circuit in  FIG. 1   a;    
           [0015]      FIG. 2 a    is a structural diagram of a pure PMOS inverting circuit in the conventional art; 
           [0016]      FIG. 2 b    is a control timing diagram of the pure PMOS inverting circuit in  FIG. 2   a;    
           [0017]      FIG. 3 a    is a structural diagram of an inverting circuit according to an embodiment of the invention; 
           [0018]      FIG. 3 b    is a control timing diagram of the inverting circuit in  FIG. 3   a;    
           [0019]      FIGS. 3 c  to 3 e    are structural diagrams of another inverting circuit according to an embodiment of the invention; 
           [0020]      FIG. 4 a    is a structural diagram of an inverting circuit according to an embodiment of the invention; 
           [0021]      FIG. 4 b    is a control timing diagram of the inverting circuit in  FIG. 4   a;    
           [0022]      FIGS. 4 c  to 4 e    are structural diagrams of another inverting circuit according to an embodiment of the invention; 
           [0023]      FIG. 5 a    is a structural diagram of an inverting circuit according to an embodiment of the invention; 
           [0024]      FIG. 5 b    is a control timing diagram of the inverting circuit in  FIG. 5   a;    
           [0025]      FIGS. 5 c  to 5 e    are structural diagrams of another inverting circuit according to an embodiment of the invention; 
           [0026]      FIG. 6 a    is a structural diagram of an inverting circuit according to an embodiment of the invention; 
           [0027]      FIG. 6 b    is a control timing diagram of the inverting circuit in  FIG. 6 a   ; and 
           [0028]      FIGS. 6 c  to 6 e    are structural diagrams of another inverting circuit according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0029]    Hereinafter, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Apparently, the described embodiments are only a few of the embodiments of the present invention, but not all the embodiments. All the other embodiments obtained by those skilled in the art based on the embodiment in the present invention without creative labor will fall within the scope of protection of the present invention. 
         [0030]      FIG. 3 a    is a structural diagram of an inverting circuit according to an embodiment of the invention. The inverting circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4  and a first capacitor C 1 . The first transistor M 1 , the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  each are P-type transistors. 
         [0031]    A first electrode of the first transistor M 1  is connected to a second terminal of the first capacitor C 1  and a third. electrode of the third capacitor M 3 , and is connected to a signal output terminal Vout together with the second terminal of the first capacitor C 1  and the third electrode of the third capacitor M 3 ; a second electrode of the first transistor M 1  is connected to a second electrode of the second transistor M 2 , and is connected to a level signal input terminal Vin together with the second electrode of the second transistor M 2 ; a third electrode of the first transistor M 1  is connected to a third electrode of the second transistor M 2 , and is connected to a first power supply input terminal VDD together with the third electrode of the second transistor M 2 . 
         [0032]    A first electrode of the second transistor M 2 , a second electrode of the third transistor M 3  and a third electrode of the fourth transistor M 4  are connected at an node N 1 , and are connected to a first terminal of the first capacitor C 1 ; the second electrode of the second transistor M 2  is connected to the second electrode of the first transistor M 1 , and is connected to the level signal input terminal Vin together with the second electrode of the first transistor M 1 ; a third electrode of the second transistor M 2  is connected to the third electrode of the first transistor M 1 , and is connected to the first power supply input terminal VDD together with the third electrode of the first transistor M 1 . 
         [0033]    A first electrode of the third transistor M 3  is connected to a first electrode of the fourth transistor M 4 , and is connected to a second power supply input terminal VSS together with the first electrode of the fourth transistor M 4 ; the second electrode of the third transistor M 3 , the third electrode of the fourth transistor M 4  and the first terminal of the first capacitor C 1  are connected at the node N 1 ; the third electrode of the third transistor M 3  is connected to the first electrode of the first transistor M 1  and the second terminal of the first capacitor C 1 , and is connected to the signal output terminal Vout together with the first electrode of the first transistor M 1  and the second terminal of the first capacitor C 1 . 
         [0034]    The first electrode of the fourth transistor M 4  is connected to the first electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the first electrode of the third transistor M 3 ; a second electrode of the fourth transistor M 4  is connected to a clock signal input terminal CLK; the third electrode of the fourth transistor M 4 , the second electrode of the third transistor M 3  and the first terminal of the first capacitor C 1  are connected at the node N 1 . 
         [0035]      FIG. 3 b    is a control timing diagram of the inverting circuit in  FIG. 3   a.    
         [0036]    During a first stage T 1 , a low-level signal is input into the level signal input terminal Vin, a high-level signal is input into the clock signal input terminal CLK. A pull-up unit is turned on and a pull-down unit is turned off, i.e., the first transistor M 1  and the second transistor M 2  each are turned on and the third transistor M 3  and the fourth transistor M 4  each are turned off. Because of turning on the first transistor M 1  and the second transistor M 2 , a high-level signal of the first supply voltage VDD is transmitted to the node N 1  and the signal output terminal Vout respectively, the third transistor M 3  is turned off completely, and a high-level signal is output from the signal output terminal steadily. 
         [0037]    During a second stage T 2 , a high-level signal is input into the level signal input terminal Vin, a low-level signal is input into the clock signal input terminal CLK. The pull-up unit is turned off and the pull-down unit is turned on, i.e., the first transistor M 1  and the second transistor M 2  each are turned off and the third transistor M 3  and the fourth transistor M 4  each are turned on. Because of turning on the fourth transistor M 4 , a low-level signal from the second power supply input terminal VSS is transmitted to the node N 1  from the fourth transistor M 4 , and the third transistor M 3  is turned on. The fourth transistor M 4  is in the on-state until a level of the node N 1  becomes VSS+Vth, and an output signal from the signal output terminal Vout is changed into a low-level signal from a high-level signal since the first electrode of the third transistor M 3  is connected to the second power supply input terminal VSS. The level of the second terminal of the first capacitor C 1 , the level of the node N 1 , is further pulled down due to the coupling function of the first capacitor C 1 , the third transistor M 3  is turned on completely, and the low-level signal from the second power supply input terminal VSS is transmitted to the signal output terminal Vout integrally. 
         [0038]    During a third stage  13  in which the CLK and the Vin each are in high level, the first transistor M 1 , the second transistor M 2  and the fourth transistor M 4  each are turned off. The low level of the node N 1  in the previous stage (the second stage T 2 ) is kept due to the first capacitor C 1 , therefore, the third transistor M 3  keeps in the complete on-state, and the signal output terminal Vout keeps outputting the low-level signal. 
         [0039]    During a fourth stage T 4 , when the CLK is in the low level again, the electrode of the fourth transistor M 4  connected to the node N 1  becomes a drain electrode due to the low level of the node N 1 , the fourth transistor M 4  keeps in the off-state for a long time the node N 1  keeps in the low level due to the first capacitor the third transistor M 3  keeps in the complete on-state, and the third transistor M 3  keeps transmitting the low-level signal to the signal output terminal Vout integrally for a long time. 
         [0040]    In this embodiment, the inverting circuit may further include a second capacitor C 2 , as shown in  FIG. 3 c   . A first terminal of the second capacitor C 2  is connected to the third electrode of the first transistor M 1 , and is connected to the first power supply input terminal VDD together with the third electrode of the first transistor M 1 ; and a second terminal of the second capacitor C 2  is connected to the signal output terminal Vout. The driving manner of the inverting circuit shown in  FIG. 3C  is the same as that shown  FIG. 3 a   , and is shown in  FIG. 3 b   . The advantage of adding the second capacitor C 2  lies in that the Vout can be kept as a stable output of low level for a long time without being affected by other factors. 
         [0041]    In this embodiment, the inverting circuit may further include a fifth transistor M 5 , as shown, in  FIG. 3 d   . A first electrode of the fifth transistor M 5  is connected to the second electrode of the first transistor M 1  and the second electrode of the second transistor M 2 , and is connected to the level signal input terminal Vin together with the second electrode of the first transistor M 1  and the second electrode of the second transistor M 2 ; a second electrode of the fifth transistor M 5  is connected to the second electrode of the fourth transistor M 4 , and is connected to the clock signal input terminal CLK together with the second electrode of the fourth transistor M 4 ; a third electrode of the fifth transistor M 5  is connected to the third electrode of the first transistor M 1 , and is connected to the first power supply input terminal VDD together with the third electrode of the first transistor M 1 . The driving manner of the inverting circuit shown in  FIG. 3 d    is the same as that shown in  FIG. 3 a   , and is shown in  FIG. 3 b   . The advantage of adding the fifth transistor M 5  lies in that the VDD can be transmitted to the second electrode of the first transistor M 1  when the CLK is in low level, so that the first transistor M 1  is turned off completely, and negative factors leading to the un-complete turning off of the first transistor M 1  and affecting the outputting of the low level can be avoided. 
         [0042]    In this embodiment, the inverting circuit may include both the second capacitor C 2  and the fifth transistor M 5 , as shown in  FIG. 3 e   . The connection relation between the second capacitor C 2  and the fifth transistor M 5  is the same as the above connection relation, and the driving manner is also the same as above, as shown in  FIG. 3   b.    
         [0043]      FIG. 4 a    is a structural diagram of an inverting circuit according to an embodiment of the invention. The inverting circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4  and a first capacitor C 1 . The first transistor M 1 , the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  each are P-type transistors. 
         [0044]    A first electrode of the first transistor M 1  is connected to a second terminal of the first capacitor C 1  and a third electrode of the third capacitor M 3 , and is connected to a signal output terminal Vout together with the second terminal of the first capacitor C 1  and the third electrode of the third capacitor M 3 ; a second electrode of the first transistor M 1  is connected to a second electrode of the second transistor M 2 , and is connected to a level signal input terminal Vin together with the second electrode of the second transistor M 2 ; a third electrode of the fast transistor M 1  is connected to a third electrode of the second transistor M 2 , and is connected to a first power supply input terminal VDD together with the third electrode of the second transistor M 2 . 
         [0045]    A first electrode of the second transistor M 2  is connected to a second electrode of the fourth transistor M 4 , and is connected to the clock signal input terminal CLK together with the second electrode of the fourth transistor M 4 ; the second electrode of the second transistor M 2  is connected to the second electrode of the first transistor M 1 , and is connected to the level signal input terminal Vin together with the second electrode of the first transistor M 1 ; the third electrode of the second transistor M 2 , a second electrode of the third transistor M 3  and a third electrode of the fourth transistor M 4  are connected at a node N 1 , and are connected to the first terminal of the first capacitor C 1 . 
         [0046]    A first electrode of the third transistor M 3  is connected to a first electrode of the fourth transistor M 4 , and is connected to a second power supply input terminal VSS together with the first electrode of the fourth transistor M 4 ; the second electrode of the third transistor M 3 , the third electrode of the fourth transistor M 4  and the first terminal of the first capacitor C 1  are connected at the node N 1 ; the third electrode of the third transistor M 3  is connected to the first electrode of the first transistor M and the second terminal of the first capacitor C 1 , and is connected to the signal output terminal Vain together with the first electrode of the first transistor M 1  and the second terminal of the first capacitor C 1 . 
         [0047]    The first electrode of the fourth transistor M 4  is connected to the first electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the first electrode of the third transistor M 3 ; the second electrode of the fourth transistor M 4  is connected to the first electrode of the second transistor M 2 , and is connected to the clock signal input terminal CLK together with the first electrode of the second transistor M 2 ; the third electrode of the fourth transistor M 4 , the second electrode of the third transistor M 3  and the third electrode of the second transistor M 2  are connected at the node N 1 , and are connected to the first terminal of the first capacitor C 1 . 
         [0048]      FIG. 4 b    is a control timing diagram of the inverting circuit in  FIG. 4   a.    
         [0049]    During a first stage T 1 , a low-level signal is input into the level signal input terminal Vin, a high-level signal is input into the clock signal input terminal CLK. A pull-up unit is turned on and the pull-down unit is turned off, i.e., the first transistor M 1  and the second transistor M 2  each are turned on and the third transistor M 3  and the fourth transistor M 4  each are turned off. Because of turning on the first transistor M 1  and the second transistor M 2 , a high-level signal of the first supply voltage VDD is transmitted to the node N 1  and the signal output terminal Vout respectively, the third transistor M 3  is turned off completely, and a high-level signal is output from the signal output terminal steadily. 
         [0050]    During a second stage T 2 , a high-level signal is input into the level signal input terminal Vin, a low-level signal is input into the clock signal input terminal CLK. The pull-up unit is turned off and the pull-down unit is turned on, i.e., the first transistor M 1  and the second transistor M 2  each are turned off and the third transistor M 3  and the fourth transistor M 4  each are turned on. Because of turning on the fourth transistor M 4 , a low-level signal from the second power supply input terminal VSS is transmitted to the node N 1  from the fourth transistor M 4 , and the third transistor M 3  is turned on. The fourth transistor M 4  is in the on-state until a level of the node N 1  becomes VSS+Vth, and an output signal from the signal output terminal Vout is changed into a low-level signal from a high level signal since the first electrode of the third transistor M 3  is connected to the second power supply input terminal VSS. The level of the second terminal of the first capacitor C 1 , i.e., the level of the node N 1 , is further pulled down due to the coupling function of the first capacitor C 1 , the third transistor M 3  is turned on completely, and the low-level signal from the second power supply input terminal VSS is transmitted to the signal output terminal Vout integrally. 
         [0051]    During a third stage T 3  in which the CLK and the Vin each are in high level, the first transistor M 1 , the second transistor M 2  and the fourth transistor M 4  each are turned off. The low level of the node N 1  in the previous time sequence (the second sequence T 2 ) is kept due to the first capacitor C 1 , therefore, the third transistor M 3  keeps in the complete on-state, and the signal output terminal Vout keeps outputting the low-level signal. 
         [0052]    During a fourth stage T 4 , when the CLK is in the low-level signal again, the electrode of the fourth transistor M 4  connected to the node N 1  becomes a drain electrode due to the low level of the node N 1 , the fourth transistor M 4  keeps in the off-state for a long time, the node N 1  keeps in the low level due to the first capacitor C 1 , the third transistor M 3  keeps in the complete on-state, and the third transistor M 3  keeps transmitting the low-level signal to the signal output terminal Vout integrally for a long time. 
         [0053]    In this embodiment, the inverting circuit may further include a second capacitor C 2 , as shown in  FIG. 4 c   . A first terminal of the second capacitor C 2  is connected to the third electrode of the first transistor M 1 , and is connected to the first power supply input terminal VDD together with the third electrode of the first transistor M 1 ; a second terminal of the second capacitor C 2  is connected to the signal output terminal Vout. The driving manner of the inverting circuit shown in  FIG. 4 c    is the same as that shown in  FIG. 4 a   , and is shown in  FIG. 4 b   . The advantage of adding the second capacitor C 2  lies in that the Vout can be kept as a stable output of low level for a long time without being affected by other factors. 
         [0054]    In this embodiment, the inverting circuit may further include a fifth transistor M 5 , as shown in  FIG. 4 d   . A first electrode of the fifth transistor M 5  is connected to the second electrode of the first transistor M 1  and the second electrode of the second transistor M 2 , and is connected to the level signal input terminal Vin together with the second electrode of the first transistor M 1  and the second electrode of the second transistor M 2 ; a second electrode of the fifth transistor M 5  is connected to the second electrode of the fourth transistor M 4 , and is connected to the clock signal input terminal CLK together with the second electrode of the fourth transistor M 4 ; a third electrode of the fifth transistor M 5  is connected to the third electrode of the first transistor M 1 , and is connected to the first power supply input terminal VDD together with the third electrode of the first transistor M 1 . The driving manner of the inverting circuit shown in  FIG. 4 d    is the same as that shown in  FIG. 4 a   , and is shown in  FIG. 4 b   . The advantage of adding the fifth transistor M 5  lies in that the VDD can be transmitted to the second electrode of the first transistor M 1  when the CLK is in low level, so that the first transistor M 1  is turned off completely, and negative factors leading to the un-complete turning off of the first transistor M 1  and affecting the outputting of the low level on the input line can be avoided. 
         [0055]    In this embodiment, the inverting circuit may include both the second capacitor C 2  and the fifth transistor M 5 , as shown in  FIG. 4 e   . The connection relation between the second capacitor C 2  and the fifth transistor M 5  is the same as the above connection relation, and the driving manner is also the same as above, as shown in  FIG. 4   b.    
         [0056]      FIG. 5 a    is a structural diagram of an inverting circuit according to an embodiment of the invention. The inverting circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4  and a first capacitor C 1 . The first transistor M 1 , the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  each are N-type transistors. 
         [0057]    A first electrode of the first transistor M 1  is connected to a first terminal of the second transistor M 2 , and is connected to a first power supply input terminal Vin together with the first terminal of the second transistor M 2 ; a second electrode of the first transistor M 1 , a third electrode of the second transistor M 2  and a first electrode of the fourth transistor M 4  are connected at a node N 1 , and are connected to a first terminal of the first capacitor C 1 ; a third electrode of the first transistor M 1  is connected to a first electrode of the third transistor M 3  and a second terminal of the first capacitor C 1 , and is connected to a signal output terminal Vout together with the first electrode of the third transistor M 3  and the second terminal of the first capacitor  1 . 
         [0058]    The first electrode of the second transistor M 2  is connected to the first electrode of the first transistor M 1 , and is connected to the first power supply input terminal Vin together with the first electrode of the first transistor M 1 ; a second electrode of the second transistor M 2  is connected to a clock signal input terminal CLK; the third electrode of the second transistor M 2 , the second electrode of the first transistor M 1  and the first electrode of the fourth transistor M 4  are connected at the node N 1 , and are connected to the first terminal of the first capacitor C 1 . 
         [0059]    The first electrode of the third transistor M 3  is connected to the third electrode of the first transistor M 1  and a second terminal of the first capacitor C 1 , and is connected to the signal output terminal Vout together with the third electrode of the first transistor M 1  and the second terminal of the first capacitor C 1 ; a second electrode of the third transistor M 3  is connected to a second electrode of the fourth transistor M 4 , and is connected to the level signal input terminal Vin together with the second electrode of the fourth transistor M 4 ; a third electrode of the third transistor M 3  is connected to a third electrode of the fourth transistor M 4 , and is connected to a second power supply input terminal VSS together with the third electrode of the fourth transistor M 4 . 
         [0060]    The first electrode of the fourth transistor M 4 , the third electrode of the second transistor M 2  and the second electrode of the first transistor M 1  are connected at the node N 1 , and are connected to the first terminal of the first capacitor C 1 ; the second electrode of the fourth transistor M 4  is connected to the second electrode of the third transistor M 3 , and is connected to the level signal input terminal Vin together with the second electrode of the third transistor M 3 ; the third electrode of the fourth transistor M 4  is connected to the third electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the third electrode of the third transistor M 3 .  FIG. 5 b    is a control timing diagram of the inverting circuit in  FIG. 5   a.    
         [0061]    During a first stage T 1 , a high-level signal is input into the level signal input terminal Vin, a low-level signal is input into the clock signal input terminal CLK. A pull-down unit is turned on and a pull-up unit is turned off, i.e., the first transistor M 1  and the second transistor M 2  each are turned off and the third transistor M 3  and the fourth transistor M 4  each are turned on. Because of turning on the third transistor M 3  and the fourth transistor M 4 , a low-level signal of the second supply voltage VSS is transmitted to the node N 1  and the signal output terminal Vout respectively, the first transistor M 1  is turned off completely, and a low-level signal is output from the signal output terminal Vout steadily. 
         [0062]    During a second stage T 2 , a low-level signal is input into the level signal input terminal Vin, a high-level signal is input into the clock signal input terminal CLK. The pull-down unit is turned off and the pull-up unit is turned on, i.e., the first transistor M 1  and the second transistor M 2  each are turned on and the third transistor M 3  and the fourth transistor M 4  each are turned off Because of turning on the second transistor M 2 , a high-level signal from the first power supply input terminal VDD is transmitted to the node N 1  from the second transistor M 2 , and the first transistor M 1  is turned on. The second transistor M 2  is on the on state until a level of the node N 1  becomes VDD−Vth, and an output signal from the signal output terminal Vout is changed into a high-level signal from a low-level signal since the first electrode of the first transistor M 1  is connected to the first power supply input terminal VDD. The level of the first terminal of the first capacitor C 1 , i.e., the level of the node N 1 , is further pulled up due to the coupling function of the first capacitor C 1 , the first transistor M 1  is turned on completely, and the high-level signal from the first power supply input terminal VDD is transmitted to the signal output terminal Vout integrally. 
         [0063]    During a third stage T 3  in which the CLK and the Vin each are in low level, the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  each are turned off. The high level of the node N 1  in the previous time sequence (the second sequence T 2 ) is kept due to the first capacitor C 1 , therefore, the first transistor M 1  keeps in the complete on-state, and the signal output terminal Vout keeps outputting the high-level signal. 
         [0064]    During a fourth stage T 4 , when the CLK is in the high level again, the electrode of the second transistor M 2  connected to the node N 1  becomes a source electrode due to the high level of the node N 1 , the second transistor M 2  keeps in the off-state for a long time, the node N 1  keeps in the high level due to the first capacitor C 1 , the first transistor M 1  keeps in the complete on-state, and the first transistor M 1  keeps transmitting the high-level signal to the signal output terminal Vout integrally for a long time until a next effective input arrives. 
         [0065]    In this embodiment, the inverting circuit may further include a second capacitor C 2 , as shown in  FIG. 5   c.  A first terminal of the second capacitor C 2  is connected to the third electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the third electrode of the third transistor M 3 ; a second terminal of the second capacitor C 2  is connected to the signal output terminal Vout. The driving manner of the inverting circuit shown in  FIG. 5 c    is the same as that shown in  FIG. 5 a   , and is shown in  FIG. 5   b.  The advantage of adding the second capacitor C 2  lies in that the Vout can be kept as a stable output of high level for a long time without being affected by other factors. 
         [0066]    In this embodiment, the inverting circuit may further include a fifth transistor M 5 , as shown in  FIG. 5 d   . A first electrode of the fifth transistor M 5  is connected to the second electrode of the third transistor M 3  and the second electrode of the fourth transistor M 4 , and is connected to the level signal input terminal Vin together with the second electrode of the third transistor M 3  and the second electrode of the fourth transistor M 4  a second electrode of the fifth transistor M 5  is connected to the second electrode of the second transistor M 2 , and is connected to the clock signal input terminal CLK together with the second electrode of the second transistor M 2 ; a third electrode of the fifth transistor M 5  is connected to the third electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the third electrode of the third transistor M 3 . The driving manner of the inverting circuit shown in  FIG. 5 d    is the same as that shown in  FIG. 5 a   , and is shown in  FIG. 5 b   . The advantage of adding the fifth transistor M 5  lies in that the VSS can be transmitted to the second electrode of the third transistor M 3  when the CLK is in high level, so that the third transistor M 3  is turned off completely, and negative factors leading to the un-complete turning off of the third transistor M 3  and affecting the outputting of the low level on the input line can be avoided. 
         [0067]    In this embodiment, the inverting circuit may include both the second capacitor C 2  and the fifth transistor M 5 , as shown in  FIG. 5 e   . The connection relation between the second capacitor C 2  and the fifth transistor M 5  is the same as the above connection relation, and the driving manner is also the same as above, as shown in  FIG. 5   b.    
         [0068]      FIG. 6 a    is a structural diagram of an inverting circuit according to an embodiment of the invention. The inverting circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4  and a first capacitor C 1 . The first transistor M 1 , the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  each are N-type transistors. 
         [0069]    A first electrode of the first transistor M 1  is connected to a first terminal of the second transistor M 2 , and is connected to a first power supply input terminal Vin together with the first terminal of the second transistor M 2 ; a second electrode of the first transistor, a third electrode of the second transistor M 2  and a first electrode of the fourth transistor M 4  are connected at a node N 1 , and are connected to a first terminal of the first capacitor C 1 ; a third electrode of the first transistor M 1  is connected to a first electrode of the third transistor M 3  and a second terminal of the first capacitor C 1 , and is connected to a signal output terminal Vout together with the first electrode of the third transistor M 3  and the second terminal of the first capacitor  1 . 
         [0070]    The first electrode of the second transistor M 2  is connected to the first electrode of the first transistor M 1 , and is connected to the first power supply input terminal Vin together with the first electrode of the first transistor M 1 ; a second electrode of the second transistor M 2  is connected to a clock signal input terminal CLK; the third electrode of the second transistor M 2 , the second electrode of the first transistor M 1  and the first electrode of the fourth transistor M 4  are connected at the node N 1 , and are connected to the first terminal of the first capacitor C 1 . 
         [0071]    The first electrode of the third transistor M 3  is connected to the third electrode of the first transistor M 1  and a second terminal of the first capacitor C 1 , and is connected to the signal output terminal Vout together with the third electrode of the first transistor M 1  and the second terminal of the first capacitor C 1 ; a second electrode of the third transistor M 3  is connected to a second electrode of the fourth transistor M 4 , and is connected to the level signal input terminal Vin together with the second electrode of the fourth transistor M 4 ; a third electrode of the third transistor M 3  is connected to a third electrode of the fourth transistor M 4 , and is connected to a second power supply input terminal VSS together with the third electrode of the fourth transistor M 4 . The first electrode of the fourth transistor M 4  is connected to the second electrode of the second transistor M 2 , and is connected to the clock signal input terminal CLK together with the second electrode of the second transistor M 2 ; the second electrode of the fourth transistor M 4  is connected to the second electrode of the third transistor M 3 , and is connected to the level signal input terminal Vin together with the second electrode of the third transistor M 3 ; the third electrode of the fourth transistor M 4 , the second electrode of the first transistor M 1  and the third electrode of the second transistor M 2  are connected at the node N 1 , and are connected to the first terminal of the first capacitor C 1 . 
         [0072]      FIG. 6 b    is a control timing diagram of the inverting circuit in  FIG. 6   a.    
         [0073]    During a first time sequence T 1 , a high-level signal is input into the level signal input terminal Vin, a low-level signal is input into the clock signal input terminal CLK. A pull-down unit is turned on and a pull-up unit is turned off, i.e., the first transistor M 1  and the second transistor M 2  each are turned off and the third transistor M 3  and the fourth transistor M 4  each are turned on. Because of turning on the third transistor M 3  and the fourth transistor M 4 , a low-level signal of the second supply voltage VSS is transmitted to the node N 1  and the signal output terminal Vout respectively, the first transistor M 1  is turned off completely, and a low-level signal is output from the signal output terminal Vout steadily. 
         [0074]    During a second stage T 2 , a low-level signal is input into the level signal input terminal Vin, a high-level signal is input into the clock signal input terminal CLK. The pull-down unit is turned off and the pull-up unit is turned on, i.e., the first transistor M 1  and the second transistor M 2  each are turned on and the third transistor M 3  and the fourth transistor M 4  each are turned off. Because of turning on the second transistor M 2 , a high-level signal from the first power supply input terminal VDD is transmitted to the node N 1  from the second transistor M 2 , and the first transistor M 1  is turned on. The second transistor M 2  is in the on-state until a level of the node N 1  becomes VDD−Vth, and an output signal from the signal output terminal Vout is changed into a high-level signal from a low-level signal since the first electrode of the first transistor M 1  is connected to the first power supply input terminal VDD. The level of the first terminal of the first capacitor C 1 , i.e., the level of the node N 1 , is further pulled up due to the coupling function of the first capacitor C 1 , the first transistor M 1  is turned on completely, and the high-level signal from the first power supply input terminal VDD is transmitted to the signal output terminal Vout integrally. 
         [0075]    During a third stage T 3  in which the CLK and the Vin each are in low level, the second transistor M 2 , the third transistor M 3  and the fourth transistor M 4  each are turned off. The high level of the node N 1  in the previous time sequence (the second sequence T 2 ) is kept due to the first capacitor C 1 , therefore, the first transistor M 1  keeps in the complete on-state, and the signal output terminal Vout keeps outputting the high-level signal. 
         [0076]    During a fourth stage T 4 , when the CLK is in the low level again, the electrode of the second transistor M 2  connected to the node N 1  becomes a source electrode due to the high level of the node N 1 , the second transistor M 2  keeps in the off-state for a long time, the node N 1  keeps in the high level due to the first capacitor C 1 , the first transistor M 1  keeps in the complete on-state, and the first transistor M 1  keeps transmitting the high-level signal to the signal output terminal Vout integrally for a long time until a next effective input signal arrives. 
         [0077]    In this embodiment, the inverting circuit may further include a second capacitor C 2 , as shown in  FIG. 6 c   . A first terminal of the second capacitor C 2  is connected to the third electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the third electrode of the third transistor M 3 ; a second terminal of the second capacitor C 2  is connected to the signal output terminal Vout. The driving manner of the inverting circuit shown in  FIG. 6 c    is the same as that shown in  FIG. 6 a   , and is shown in  FIG. 6 b   . The advantage of adding the second capacitor C 2  lies in that the Vout can be kept as a stable output of high level for a long time without being affected by other factors. 
         [0078]    In this embodiment, the inverting circuit may further include a fifth transistor M 5 , as shown in  FIG. 6 d   . A first electrode of the fifth transistor M 5  is connected to the second electrode of the third transistor M 3  and the second electrode of the fourth transistor M 4 , and is connected to the level signal input terminal Vin together with the second electrode of the third transistor M 3  and the second electrode of the fourth transistor M 4 ; a second electrode of the fifth transistor M 5  is connected to the second electrode of the second transistor M 2 , and is connected to the clock signal input terminal CLK together with the second electrode of the second transistor M 2 ; a third electrode of the fifth transistor M 5  is connected to the third electrode of the third transistor M 3 , and is connected to the second power supply input terminal VSS together with the third electrode of the third transistor M 3 . The driving manner of the inventing circuit shown in  FIG. 6 d    is the same as that shown in  FIG. 6 a   , and is shown in  FIG. 6 b   . The advantage of adding the fifth transistor M 5  lies in that the VSS can be transmitted to the second electrode of the third transistor M 3  when the CLK is in high level, so that the third transistor M 3  is turned off completely, and negative factors leading to the un-complete turning off of the third transistor M 3  and affecting the outputting of the low level in the input can be avoided. 
         [0079]    In this embodiment, the inverting circuit may include both the second capacitor C 2  and the fifth transistor M 5 , as shown in  FIG. 6 e   . The connection relation between the second capacitor C 2  and the fifth transistor M 5  is the same as the above connection relation, and the driving manner is also the same as above, as shown in  FIG. 6   b.    
         [0080]    The structure and driving method for the inverting circuit according to the embodiment of the invention have been described in detail hereinbefore. The principle and embodiment of the invention are explained in specific examples herein. The descriptions of the embodiments above are only used to help understanding the method and core idea of the invention. Modifications can be made to the embodiment and the application scope of the invention by those skilled in the art based on the idea of the invention. In conclusion, the content of the description should not be interpreted as to limit the invention.