Abstract:
In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection.

Description:
This is a continuation of application Ser. No. 620,894, filed on June 15, 1984, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a pulse control circuit which is suitable for driving a capacitance load at high speed. 
     Reductions in the sustain voltage of elements which have resulted from the recent miniaturization of bipolar or MOS transistors have tended to reduce the operating voltages of integrated circuits. From the user&#39;s point of view, conventional supply voltages, such as supply voltages in units of 5 V, are desirable for ease of use. It is considered that means by which it will be possible to satisfy both the needs of the manufacturers of integrated circuits and the users is a reduction of the external supply voltage Vcc within the chips and the operation of miniaturized elements by a voltage V L  which has been lowered thereby. 
     FIG. 1A is taken from U.S. patent application No. 368,162 applied for by the present Applicant. A miniaturized element 12a of FIG. 1B is used in an internal circuit a which determines the effective integration density of chips 10, and the remedy for the reduction in the voltage resistance resulting from miniaturization is to operate the element by a voltage V DP  which is the external supply voltage Vcc reduced by a voltage limiter 30. However, it is usually easier to design a drive circuit b which uses a higher supply voltage and which includes, for example, an input-output interface, which does not contribute much to the integration density. Thus, a comparatively large element 12b, as shown in FIG. 1B, is used for the driving circuit b which is operated by applying Vcc thereto. 
     A chip is a single substrate on which memory, logic or other LSI devices are fabricated. In a memory LSI device, a from FIG. 1A is a memory array and its related circuits. On the other hand, in a logic LSI device, a is an area constructed of repeated cells making up the ROM or RAM area of a microcomputer. Details of embodiments of voltage limiters using this voltage limiter system are given in U.S. patent application Nos. 368,162 and 562,969. 
     When this kind of voltage limiter system is utilized for charging a capacitance load which has only a low voltage resistance in the circuit a, the output V DP  of the voltage limiter 30 is supplied to the drain of a charging transistor as a supply voltage and, pulses of the same level as that of the external supply voltage Vcc are applied to the gate of the transistor, turning the transistor on. 
     In FIG. 2, a precharge circuit for a data line of a semiconductor memory is shown as an example of this type of circuit. In FIG. 2, charging transistors Q 6 , Q 7  controlled by precharge pulse φ P2  of a maximum level of Vcc charge data lines D o  and D o  to a voltage as large as the output voltage V DP  of the voltage limiter 30. Numeral 1 denotes a memory cell array. 
     However, in this circuit, the equivalent internal resistance of the voltage limiter 30 is connected in series to the equivalent resistances of the charging transistors Q 6  or Q 7  when they are on, and thus it is necessary to make these resistances much smaller to enable charging at a higher speed when there is a larger capacitance load. For that purpose, the size of the transistors in the voltage limiter 30 and the transistors Q 6 , Q 7  must be larger, and thus it can be understood that it is difficult to drive a large capacitance load faster when there must be a high degree of integration. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a pulse drive circuit which is suitable for driving a large capacitance load at high speed. 
     In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a diagram of the chip structure of a conventional semiconductor circuit. 
     FIG. 1B is a diagram of an example of the structure of two transistors used in the chip of FIG. 1A. 
     FIG. 2 is a diagram of a precharge circuit for data lines of a semiconductor memory. 
     FIG. 3 is a circuit diagram of a first embodiment of the present invention. 
     FIG. 4 is a circuit diagram of a second embodiment of the present invention. 
     FIG. 5 is a graph of the output characteristic of the voltage limiter 30 used in the circuit of FIG. 4. 
     FIGS. 6A and 6B illustrate the high-voltage generation circuit (31c) used in the embodiment of FIG. 4. 
     FIG. 7 is a circuit diagram of a third embodiment of the present invention. 
     FIG. 8 is a graph of the output characteristic of the voltage limiter (30D) used in the circuit of FIG. 9. 
     FIG. 9 is a circuit diagram of a fourth embodiment of the present invention. 
     FIGS. 10A and 10B illustrate the voltage generation circuit (31C) used in the circuit of FIG. 8. 
     FIGS. 11A and 11B are circuit diagrams of two parts of a semiconductor memory of the present invention which are different from each other. 
     FIG. 12 is a circuit diagram of the voltage limiter (30E) used in the circuit of FIG. 11B. 
     FIG. 13 is a circuit diagram of the pulse-limiting circuit (G) of FIG. 11B. 
     FIG. 14 is a circuit diagram of the voltage converter circuit (H) of FIG. 11B. 
     FIG. 15 is a circuit diagram of a fifth embodiment of the present invention which discharges a charge from a capacitance load. 
     FIG. 16 is a circuit diagram of a sixth embodiment of a discharge circuit. 
     FIG. 17 is a graph illustrating conventional problems encountered when driving a capacitance load. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 shows a fundamental embodiment of the present invention. A signal φ il  whose amplitude is controlled by the operation of a pulse-generating circuit PG is input to a gate of a MOS transistor Q L  &#39;, and a capacitance load C L  connected to the source of the transistor is driven thereby. 
     The pulse-generating circuit PG inputs pulse φ i  of a maximum voltage equivalent to the supply voltage Vcc. 
     Details of this pulse-generating circuit PG and its operation are given in &#34;Electronics&#34; Mar. 24th, 1982, pp. 132-136. An outline thereof is provided below. 
     An inverted output of a driver 12 to which the input pulse φ i  is applied makes a MOS transistor Q D  discharge its gate voltage so that its electric potential changes from high to low. Simultaneously, a bootstrap capacitance (not shown) acts so that the gate voltage of a transistor Q L  is charged by a non-inverted output of the driver 12 so that its low potential becomes a high potential of at least the level of Vcc, turning the transistor Q L  on. 
     An internal supply voltage V DP  which is different from the external supply voltage Vcc and is applied to the gate of a transistor Q LL  so that a voltage of V DP  -V T  is applied to the drain of transistor Q L . Thus, the output φ il  rises from a low voltage of zero to the drain voltage V DP  -V T  of the transistor Q L . V T  denotes the threshold voltage of each transistor in this embodiment. 
     The external supply voltage Vcc is applied to the drain of transistor Q L  &#39;, but the capacitance load C L  is charged by a voltage of up to V DP  -2V T  which is equal to the high voltage V DP  -V T  of the pulse φ il  reduced by the threshold voltage V T  of the transistor Q L  &#39;. By suitably increasing the size of transistor Q L  &#39; alone, that is, by increasing the magnitude of W/L (channel width/channel length), it is possible to drive the capacitance load C L  at high speed, however large C L  is. Concrete details of circuits embodying the voltage limiter 30 are disclosed in U.S. patent application Nos. 368,162 and 562,969. One example of these will now be described with reference to FIG. 4. This embodiment removes the problem often encountered in the prior art that, when charging the capacitance load C L  the voltage limiter and the charge-control transistors must all be large-sized transistors. When the voltage with which the capacitance load C L  is charged is V out  (hereinafter, &#34;signal voltage&#34; denotes any voltage on the high electric potential side, without particular limitations), the voltage of the pulse φ il  is V in  and the threshold voltage of the transistor Q L  is V T , V out  is generally given by: 
     
         V.sub.out =V.sub.in -V.sub.T                               (1) 
    
     Accordingly, a control of the output voltage on the high electric potential side can be accomplished by controlling V in  which can be defined in response to the essential voltage V out . 
     Thus for V in  it is necessary to generate a voltage which is higher than the required charge voltage by the voltage V T . For this purpose, the output voltage V DP  of the voltage limiter 30 of FIG. 3 could be modified. 
     FIG. 4 discloses an embodiment in which the voltage of V DP  -V T  is applied to the capacitance load C L . FIG. 4 differs from FIG. 3 only in that a voltage limiter 30A is designed so that it outputs a voltage V DP  +V T  which is only V T  higher than the output V DP  of the voltage limiter 30 of FIG. 3. FIG. 4 shows a concrete example of the voltage limiter 30 which outputs V DP  from a contact point between a resistor R LM  and a series of n diodes D 1  to D n . The voltage limiter 30 outputs the voltage V DP  of which has a characteristic as shown in FIG. 5 with respect to the external supply voltage Vcc. This characteristic shows that if the external supply voltage Vcc is less than V 0 , the output of the voltage limiter is equal to Vcc; and if it is greater than V 0 , the output thereof varies with a gradient of m which is less than 1. When the standard voltage is 5 V, V 0  is selectively defined by a value which is less than 5 V; and when Vcc is 5 V, V DP  can be determined to be, for example, 3.5 V by this characteristic. 
     V 0  is equal to the external supply voltage when the n series-connected diodes D 1  to D n  of FIG. 4 start to be turned on. The gradient m is defined by the ratio of the resistance R LM  in series with the resistance of the group of diodes D 1  . . . D n  when on. 
     Returning to FIG. 4, a high-voltage generation circuit 31 generates a voltage V pp  which is higher than the external supply voltage Vcc. This circuit will be described later with reference to FIGS. 6A and 6B. 
     In FIG. 4, two transistors Q 103 , Q 101 , which are arragned so that the drain of one is connected to the gate of other, and a resistance R p  are connected in series between an output terminal of the high-voltage generation circuit 31 and an output terminal of the limiter 30. Thus, the drain voltage of transistor Q 103  is equal to V DP  +2V T . Since this voltage V DP  +2V T  is applied to the gate of a transistor Q 102  whose drain receives the external supply voltage Vcc, V DP  +V T  is applied to the gate of the transistor Q LL  in the pulse-generating circuit PG. Accordingly, the high electric potential of the pulse φ il  is equal to V DP  and so a charging voltage of up to V DP  -V T  is applied to the capacitance load C L . The output voltage V pp  of the high-voltage generation circuit 31 is set by the formula: 
     
         V.sub.pp ≧V.sub.DP +2V.sub.T 
    
     The high-voltage generation circuit 31 will now be described with reference to the circuit diagram thereof of FIG. 6A. A circuit C p1  has a construction and operation such that pulse φ B  is applied through a charge-pump capacitor C B  to a node between two transistors Q c1  and Q c2  arranged so that the source of Q c1  is connected to the gate of Q c2 , and pulses higher than Vcc are generated. A circuit C p2  also comprises of two transistors Q c  &#39; 1  and Q c  &#39; 2  connected in the same state as in circuit C p1  and a charge-pump capacitor C B  &#39;. However, it differs from C p1  in that pulse φ B  is generated. The sources of transistors Q c2  and Q c  &#39; 2  for a wired OR. φ B  and φB, respectively are pulses of a certain period and inverses thereof, in a chip. The circuits for producing these pulses are not shown in the drawings for simplicity. C p  denotes a parasitic capacitance generated in the output wiring. Nodes N 1  and N 1  &#39; respectively of transistors Q c1  and Q c  &#39; 1  of FIG. 6B are precharged to the voltage Vcc-V T . Each of the pulses φB and φB then reach Vcc during each of time bands T 1 , T 2 , respectively, when the corresponding nodes N 1  and N 1  &#39; are raised to 2Vcc-V T  during T 1  and T 2  by the capacitive coupling of charge-pump capacitors C B  and C B  &#39;, respectively. This voltage appears as an output voltage V pp  through transistors Q c2 , Q c2  &#39; but the voltage is reduced by the threshold voltage V T  of the transistors Q c2 , Q c2  &#39; and thus V pp  is given by the formula V pp  =2(Vcc-V T ). As a result, the output V pp  becomes a d.c. voltage which is greater than Vcc. 
     Since the high-voltage generation circuit 31 receives the charges of the capacitors C B , C B  &#39; output during both time bands T 1 , T 2 , the ability of the circuit to supply charge is great, and a ripple noise in its output V pp  is low. 
     FIG. 7 shows an embodiment which can charge the capacitance load C L  to the voltage V DP . The circuit shown in FIG. 7 differs from that of FIG. 4 in that a voltage limiter 30B is constructed so that the output voltage V DP  of the voltage limiter 30 is raised to V DP  +2V T . Namely, the circuit in FIG. 7 differs from that of FIG. 4 in that the drain and gate of a transistor Q 104  are connected in series to transistors Q 101  and Q 103  and high voltages V ppA  and V ppB  generated by voltage generation circuits 31A and 31B are applied to the drain of a transistor Q 102  and a resistor R p , respectively. 
     The gate voltage of the transistor Q 103  is made to be V DP  +3V T  by activating the transistor Q 104 . Thus, a voltage which is higher by V T  than that in the circuit of FIG. 4 is applied to the gates of transistors Q LL , Q L  &#39;, and the capacitance load C L  is charged to the voltage V DP . 
     In addition, the high-voltage generation circuit 31B supplies the transistor Q LL  with a voltage V ppB  which value is V DP  +2V T , in order to raise the gate voltage of the transistor Q L , to V DP  +V T  which is higher than that in FIG. 4. 
     The output V ppA  from the high-voltage generation circuit 31A must be greater that the drain voltage V DP  +3V T  of the transistor Q 103 . 
     Ordinary integrated circuits are subjected to aging tests after the final production step in order to ensure their reliability. These aging tests are designed to detect any transistor in which basic problems are likely to occur because of a failure of its gate oxide film, and are performed by deliberately applying to each transistor in the circuit a voltage which is higher than those encountered during normal usage. It is necessary to apply to each element a voltage which is slightly lower than the destructive voltage of a normal element in order to improve the chances of finding failures with these aging tests. For an integrated circuit chip which is so constructed that a supply voltage is supplied through a voltage limiter within the chip, examples which can accomplish these aging tests, even for the circuit part a of FIG. 1 which has a low voltage resistance, are disclosed in U.S. Patent Application Nos. 368,162 and 562,969. 
     It is desirable that the present invention can accomplish these aging test. In the embodiments thereof shown in FIGS. 3, 4 and 7, the voltage limiter 30 varies the output voltage V DP  in accordance with the characteristic of FIG. 5. Thus, if the gradient m is selected to have a certain magnitude, the output V DP  can be charged to the voltage required for the aging tests by varying the magnitude of Vcc. This change means that the voltage applied to the load capacitance C L  can be varied, and thus the aging tests can be accomplished for the load capacitance C L . 
     However, when Vcc is near the normal operating voltage 5 V, it is better not to change V DP  much if Vcc is varied. For this purpose, it is desirable to minimize the gradient m of the characteristic of FIG. 5 as far as possible. Therefore, in the voltage limiter 30 of FIGS. 3, 4 and 7, when the external voltage Vcc is greater than Vo&#39;, which is greater than the normal operating voltage 5 V, it is desirable, as shown in FIG. 8, to generate V DP  so that its characteristic varies with respect to the voltage Vcc above the voltage Vo with a gradient m&#39; that is greater than the gradient m when Vcc is between the voltages Vo and Vo&#39;. 
     FIG. 9 shows an embodiment in which the capacitance load C L  is supplied with a voltage which varies in accordance with the characteristic of FIG. 8. 
     FIG. 9 differs from FIG. 7 in that a voltage limiter 30D is used instead of the voltage limiter 30 of FIG. 7. The circuit of the voltage limiter 30D is disclosed in U.S. Patent Application Nos. 368,162 and 562, 969. This voltage limiter 30D ouputs a voltage V DP  which has the characteristic shown in FIG. 8. Namely, in FIG. 9, V G  (for example, Vcc+2V T ) is applied to the gate of a transistor Q o  of the voltage limiter 30D. The magnitude of the voltage V G  is selected so that it can turn Q o  on. When the magnitude of the external supply voltage Vcc is between 0 and V 0 , a transistor Q l  is turned off, and thus the output V DP  is equal to Vcc. When the external supply voltage Vcc is between V 0  and V 0  &#39;, the transistor Q l  is turned on because transisors Q 1 , Q m  are on. Accordingly, the output V DP  varies according to a gradient m (m&lt;1 ) determined by the conductance ratio of transistors Q o  and Q l . 
     When the external supply voltage Vcc is above V 0  &#39;, a transistor Q l  &#39; is turned on because transistors Q 1  &#39; and Q n  &#39; are on. consequently, the output is defined by a gradient m&#39; (m&#39;&gt;m) which is also determined by the ratio of conductance of transistors Q o  and Q l , and also by the sum of the conductances of the transistors Q o  and Q l  &#39;. 
     The circuit shown in FIG. 9 differs from that of FIG. 7 in that a high voltage V ppc  generated by a high-voltage generation circuit 31C (which will be described later with reference to FIGS. 11A and 11B), is applied to the drain of the transistor Q LL . 
     The voltage V ppc  is selected to have a magnitude greater than that of the gate voltage V DP  +V T  of the transistor Q LL  even if that gate voltage varies. Thus, in the same way as in the circuit of FIG. 7, the voltage V ppc  is applied to the capacitor C L  even if the magnitude of V DP  varies. As a result, the aging tests of the capacitance load C L  can be accomplished by varying Vcc. It is obvious that the voltage limiter 30C of FIG. 9 can be used instead of the voltage limiter 30 of FIGS. 3, 4 and 7, and it also goes without saying that the high-voltage generation circuits 31A and 31B of FIG. 9 must generate output voltages V ppA  and V ppB  that are higher than V DP  +3V T  and V DP  +2V T  respectively, even if Vcc varies. 
     The high-voltage generation circuit 31C will now be described. A pulse-generating circuit PG&#39;, shown in FIG. 10A, differs from the pulse-generating circuit PG of FIG. 3 only in that it does not have the transistor Q LL . Pulse φ BB  output from the pulse-generating circuit PG&#39; are connected to the source of a transistor Q BB  by a bootstrap capacitor C BB . The drain and gate of the transistor Q BB  are connected to the external supply voltage Vcc. 
     The operation of this voltage generation circuit 31C will now be described with reference to FIG. 10B. An output V ppc  is precharged to the voltage V CC  -V T  by the transistor Q BB . When an input pulse φ i  of the pulse generation circuit PG&#39; rises, an output pulse φ BB  starts to rise simultaneously with an output pulse φ il  of the pulse generation circuit PG (FIG. 9). The pulse φ BB  rises as far as Vcc, and φ il  rises to V DP  +V T . In response to the rise of the pulse φ BB , V ppc  rises because of the capacitive coupling of C BB . The magnitude of C BB  is such that the maximum value of V ppc  becomes the voltage necessary for obtaining the source voltage V DP  +V T  of a transistor Q LL  (FIG. 9), that is, a voltage higher than V DP  +V T . It is better to employ the voltage generation circuit 31C than a circuit which outputs V ppc  continuously, because V ppc  is generated only when a pulse φ il  is generated, and so the power consumption is reduced. 
     This means that the high-voltage generation circuits 31A and 31B can be constructed of the same circuit. 
     FIGS. 11A and 11B show an embodiment in which the present invention is applied to MOS dynamic memory with a single -transistor type memory cell. In these drawings, a group of circuits 1 enclosed within a dot-dash line comprise a memory array circuit. A group of circuits 2 enclosed within a dot-dot-dash line comprise circuits (direct peripheral circuits) which control the memory array circuit and amplify signals from memory cells. A group of circuits 3 enclosed within a triple-dot dash line denotes circuits (indirect peripheral circuits) which supply signals to the direct peripheral circuits, amplify memory signals from the memory array circuit, and write memory signals into the memory array circuit. 
     In the memory array 1, capacitors C 1  and C 2 , transistors Q 8 , Q 9  and Q 11 , Q 12  represent dummy cells. Capacitors CM 1 , CM 2  . . . CM n-1 , CM n  and transistors QM 1 , QM 2  . . . QM n-1 , QM n  each form memory cells. Pulse φ p3  applied to the gates of transistors Q 9  and Q 10  are used to discharge the capacitors C 1 , C 2  before reading, and is generated in a pulse-generating circuit 33. 
     A denotes a word driver circuit which generates word-selecting signals from address signals. 
     When a transistor QD 1  or QD 2  on a word line W 1  or W 2 , respectively, is selected, the word driver circuit A raises the gate voltage of a transistor Q 16  on a dummy word line WD 1  to a higher level, and outputs a signal φ xl  to a dummy word line WD 1  and the appropriate word line W 1  or W 2 . 
     On the other hand, when a transistor QD n-1  or QD n  on a word line W n-1  or W n , respectively, is selected, a transistor Q 17  on a dummy word line WD 2  is selected. 
     Transistors Q 21 , Q 22  connect I/O and I/O lines to data lines D and D by pulses φ 4 . 
     Transistors Q 1 , Q 2  form part of a sense amplifier and transistors Q 3 , Q 4  act as switches to connect data lines to the sense amplifier. 
     Transistors Q 6 , Q 7  are used for precharging and will be described later. A transistor Q 5  is used for switching between the short-circuiting of data lines D o , D o  &#39;. 
     A transistor Q 18  is used for precharging a line l, and transistors Q 19 , Q 20  are used for driving the sense amplifier. 
     A voltage limiter 30E outputs two voltages V L1  and V L2  through a circuit shown in FIG. 12. This circuit is formed by connecting the gate of the transistor Q 104  of the voltage limiter 30C of FIG. 9 to the transistor Q 102  of FIG. 4. 
     Each transistor is constructed to as to have a threshold voltage V T  of 0.5 V, and a voltage limiter 30D is constructed so that V DP  is 3.5 V when the external supply voltage Vcc is 5 V. Thus, the outputs V L1  and V L2  are 4.0 V and 4.5 V, respectively, when Vcc is 5 V. 
     The voltage limiter 30E can generate these two voltage magnitudes within a single circuit. Thus, the area of the semiconductor chip can be reduced, and fluctuations between V L1  and V L2  can be made smaller because the voltage limiter 30E operates on the basis of the same output V DP  of the voltage limiter 30D. 
     In FIG. 11B, F denotes a circuit which receives a precharge signal φ P2  (5 V) and also V L2  (4.5), and which outputs a precharge signal φ P2l  whose voltage is V T  less than V L2 . F is composed of a circuit which is identical to the pulse-generating circuit PG of FIG. 9. 
     The data lines D, D and a common source terminal of the sense amplifier composed of the transistors Q 1 , Q 2  is precharged to a voltage equal to V L2  reduced by only the threshold voltage V T , by transistors Q 6 , Q 7  and Q 18  to the gates of which pulses are applied. 
     For example when the external supply voltage Vcc is 5 V and the threshold voltage is 0.5 V, the precharge voltage is 3.5 V. 
     Since there are numerous data lines within a memory, the total capacitance thereof is fairly large. However, according to the present invention, these lines can be precharged to a voltage which is lower than Vcc at high speed. 
     In order to prevent any differences in data line voltages caused by the difference between the threshold voltages of transistors Q 6  and Q 7 , the gate voltage φ P1  of Q 5  can be made higher than φ P2  l, transistor Q 5  is can be turned on to short-circuit lines D and D. 
     I/O, IO lines are common data input and output lines connected to a plurality of data lines. 
     In FIG. 11B, B denotes a pulse-generating circuit and C denotes another pulse-generating circuit which inputs write data Din and generate pulses din, din which are complementary to each other. 
     Numeral 33 denotes a circuit which inputs external control pulse signals at the voltage Vcc and generates pulses such as φ P1 , φ P2 , etc. 
     In FIG. 11B, G denotes a circuit which receives a signal φ x  of a voltage amplitude of 5 V and also V L2  (4.5 V), and which outputs a signal φ X  l of the same voltage amplitude as V L2 . This circuit, shown in FIG. 13, is well-known and is disclosed in U.S. patent application No. 368162 wherein it is described as a circuit for converting a signal amplidute, employing a self-bootstrapping effect. This signal φ x  l becomes a word line signal of a memory cell. 
     In this embodiment, the present invention is not applied to the driving circuit G for word lines W 1  . . . W n . That is the reason why, since only one word line should be selected and the capacitance thereof is small, the driving speed is made much faster by the circuit G. However, a component in which the present invention is applied must charge all the data lines at once so that the load on it is heavy, and its speed is must therefore be made slower by such means as the driving circuit G. If a data line is charged according to the present invention, it is clearly impossible to make the speed faster than the speed obtained when only one word line is charged by the driving circuit G. However the present invention is suitable for precharging a large capacitance load such as several data lines, etc., since high-speed charging is not needed. 
     In FIG. 11B, H denotes a voltage converter circuit which receives V L1  (4.0 V) and Vcc(5 V), and which generates a set up d.c. voltage of V cp  (3.5 V). As shown in FIG. 14, it is composed of a so-called source-follower transistor Q ss  which inputs Vcc through its drain and V L1  through its gate, and outputs V cp  from its source. It is possible to stabilize the operation of the circuit by inserting a large resistance R ss  between an output terminal and ground, and by passing a small current therethrough, as shown in FIG. 14. In the Figure, V cp  is a precharge voltage supplied to the I/O and I/O lines, or it is a writing voltage in the writing circuit composed of transistors Q 23  to Q 26 , and is set to 3.5 V, equal to the data line voltage. 
     In order to precharge the I/O, I/O lines, a conventional method of inputting the controlled voltage V cp  to the drains of transistors Q 28 , Q 29  is employed. However, in the same way as in the precharging means for data lines, it is possible to employ the method of controlling the voltages of the I/O, I/O lines at a predetermined magnitude by applying voltage-controlled pulse signals within the chip to the gates of the transistors Q 28 , Q 29 . The I/O, I/O lines can be precharged as fast as the data lines, so the present invention should be applied thereto. A circuit such as that shown in FIG. 12 is suitable for this purpose because it has a small capacitance and a convenient layout. 
     Circuits for discharging the capacitance load are shown in FIGS. 15 and 16. 
     FIG. 15 shows an embodiment in which a signal φ il , an inversion of the signal φ il  of FIG. 3, is input to the gate of a transistor Q&#39; D , and an output can be extracted from the drain thereof. In this embodiment, the inverted signal φ il  is output and the capacitance load C&#39; L  is driven on the basis of the driving ability of a transistor Q D  &#34; defined by its W/L ratio. Thus, in the same way as in the embodiment of FIG. 3, any size of driving ability can be obtained by selecting a suitable value of W/L. 
     FIG. 16 shows an embodiment in which a push-pull type of buffer circuit is constructed from two of the pulse-generating circuits PG of FIG. 3 which form an inverted signal and apply it and the original signal to the gates of transistors Q L  &#34;, Q D  &#34;. φ i  l is input to Q L  &#34; and the inverted signal φ il  of φ il  is input to Q D  &#34;. An output φ o  &#34; therefrom is a signal of the same phase as φ il  at a voltage controlled by the voltage of φ il . In the present embodiment, the rise term of φ il  of φ o  &#34; and is output on the basis of the driving ability of transistor Q L  &#34; determined by the ratio W/L, and the fall term thereof is output according to that of transistor Q D  &#34;. The driving ability required for each section can be easily obtained so that the capacitance load C L  can be driven at high speed. 
     Each of these embodiments have been described using n-channel MOS transistors as examples, but p-channel MOS transistors can be employed if all the potential relationships are reversed. For example, if p-channel MOS transistors are used for the pulse-generating circuit and the supply voltage is -5 V (the circuit operates within the range of -5 V to 0 V), the circuit can be operate under conditions in which -5 V is applied to the drain of transistor Q L  &#34; and 0 V (ground) is applied to the source of transistor Q D  &#34;. In this case, the output voltage is given by the formula V out  =V in  -V T , in the same way as in formula (1), when the voltage of the input φ il  is V in  ; so that if, for example, V in  is -4 V and V T  is -0.5 V (p-channel transistors have negative threshold voltages), V o  =-4-(-0.5)=-3.5 V. This means that the magnitude of V in  can control V out . If an operating range of from 0 V (corresponding to the previous -5 V) to 5 V (corresponding to the previous OV) is wanted, the whole range can be shifted intact in the positive direction by 5 V. The drain of transistor Q L  &#34; can be set to OV and that of transistor Q D  &#34; to 5 V so that V in  =1 V. The output voltage V out  in this case is 1.5 V (a signal inverted by 1.5 V on the basis of +5 V). Both n-channel and p-channel MOS transistors are used for in a CMOS type of LSI device, and any of the above embodiments can be used therein, according to the purpose of the device. Bipolar transistors can be used instead of MOS transistor, the same operations as those of a MOS transistor can be accomplished by a circuit in which the collector, emitter and base of a bipolar transistor replace the drain, source and gate of a MOS transistor, respectively. 
     When this discharge circuit is used together with the voltage limiter 30 with the characteristics of FIGS. 4 and 9, the following effect is obtained, in the same way as in the charging circuit of FIG. 3. The amplitude of the voltage of the pulse signal applied to the gates of the transistors Q D  &#34; (in FIGS. 15 and 16) and Q L  &#34; (in FIG. 16) follows the curve of FIG. 5 when the external supply voltage Vcc is higher or lower than V o , to control the operating speeds of the transistors Q D  &#34;, Q L  &#34;. 
     For example, in the transistor type of dynamic memory shown in FIGS. 11A and 11B, even when the external supply voltage Vcc is varied in order to stabilize the memory operations between the memory array 1 and the direct peripheral circuits 2 and the indirect peripheral circuits 3, it is necessary to maintain the matching between the operating speeds of each of the circuits. 
     However, when not using a voltage limiter such as that of FIGS. 5 and 8, in which the gradient m is controlled so that it is less than the variation in the external supply voltage Vcc, the operating speed depends on the operating and manufacturing conditions because each circuit has a different operating mode, so that it is difficult to maintain this matching. In particular in recent years, the wiring resistances within the memory array circuit 1, the direct peripheral circuits 2, etc., have increased because of the increased integration of memories, and also the characteristics of MOS transistors make it more difficult to match them to the circuits which determine the operating speed. 
     This problem is very important, particularly when the external supply voltage Vcc varies. FIG. 17 illustrates this state, with reference to an example in which a signal 101a must be generated when the waveform of a signal 100a has fallen below the voltage V crT . This is equivalent to the relationship between the discharge speed (100a) for the data lines D o , D o  during read-out and the signal φ 4  (101a) for extracting those signals onto the I/O line. 100b denotes the discharge speed for the data lines D o , D o  when the external supply voltage V cc  drops. Since the discharge speed for a data line is mainly controlled by its wiring resistance, the time taken for discharge as far as the voltage V crT  hardly varies in comparison with the signal waveform of 100a in a memory array in which the integration density and wiring resistance have been increased. However, since φ 4  (100a) generated by the peripheral circuits is usually determined by the characteristics of several MOS transistors, the time taken for its generation is greatly delayed, as shown by the signal waveform 101b, when the external supply voltage Vcc drops. 
     In contrast, if an attempt is made to reduce the delay in the generation of the signal waveform 101b when the external supply voltage Vcc is low, the signal waveform 101b is generated earlier than that when the signal waveform 100b reaches V crT  when the external supply voltage is high. 
     Thus, if one of the circuits shown in FIGS. 9, 15 and 16 is employed as a circuit controlling the delay in the signal waveform 101, the delay in the generation of the signal waveform due to variations in the external supply voltage Vcc can be eliminated. 
     This means that, since variations in the voltage output by the voltage limiter 30 are smaller than those in the external supply voltage Vcc, and the operating speeds of the transistors Q L  &#39;, Q D  &#34;, Q L  &#34; (FIGS. 9, 15 and 16) hardly vary, the signal waveform 101b can be generated earlier, as shown by the wave form 101b&#39;. 
     Accordingly, it is possible to realize a memory which can operate stably with no delaying in its access time. 
     The memories of FIGS. 11A and 11B have been described by way of example, but this method can be applied to any other type of memory with the same objectives, without any modification. 
     As stated above, details of the present invention have been given in accordance with various embodiments thereof, but the potential application of the present invention should not be limited to these embodiments. For example, the present invention can be employed in LSI devices other than memory circuits. It can also be employed in LSI devices which use transistor other than n-type MOS transistors.