Abstract:
A variable resistance circuit comprises a resistance circuit including a plurality of resistors serially connected, and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors. The bypass circuit includes a plurality of transistors selectively turned on or off. The variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. The gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value. Various resistance values can be set in high precision by selectively turning on or off the plurality of transistors.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a variable resistance circuit that has a variable resistance value being gradually variable, an operational amplification circuit employing this variable resistance circuit, and a semiconductor integrated circuit employing this operational amplification circuit.  
           [0003]    2. Description of the Background Art  
           [0004]    In recent years, optical disk drives such as a CD (compact disk) drive, a CD-ROM (compact disk read only memory) drive and the like come into wide use, followed by development of various semiconductor integrated circuits applied to these optical disk drives.  
           [0005]    [0005]FIG. 7 is a block diagram showing the structure of a conventional semiconductor integrated circuit applied to a CD-ROM drive.  
           [0006]    The circuit shown in FIG. 7, formed by a plurality of semiconductor integrated circuits, comprises a signal processing circuit  200 , an RF (radio frequency) amplifier  220 , a drive circuit  230 , a microcomputer  240  and a DRAM (dynamic random access memory)  250 .  
           [0007]    The signal processing circuit  200  includes a DSP (digital signal processor)  201 , a DAC (digital-to-analog converter)  202 , a servo circuit  203  and an error correction circuit  204 . The RF amplifier  220  is formed by a bipolar integrated circuit with different components, and the signal processing circuit  200  is integrated into a single chip by a CMOS (complementary metal oxide semiconductor) integrated circuit.  
           [0008]    An optical pickup  210  converts data recorded on a CD-ROM disk to an RF signal, and outputs the RF signal to the RF amplifier  220 . The RF amplifier  220  generates a reproduced signal (EFM (eight to fourteen modulation) signal), a focus error signal and a tracking error signal etc., and outputs these signals to the signal processing circuit  200 .  
           [0009]    The signal processing circuit  200  creates a control signal for controlling the optical pickup  210  from the focus error signal, the tracking error signal etc. through the DSP  201  and the servo circuit  203 , and outputs the control signal to the drive circuit  230 . The drive circuit  230  drives an actuator provided in the optical pickup  210  in response to the input control signal, for controlling the optical pickup  210  to reproduce an excellent RF signal.  
           [0010]    The signal processing circuit  200  further performs error correction of the reproduced data by the error correction circuit  204  with the DRAM  250 , for converting the reproduced data to an analog signal by the DAC  202  and outputting the analog signal when reproducing a sound signal.  
           [0011]    The microcomputer  240  serves as a system controller controlling operations of the overall drive and transmits/receives data etc. to/from the signal processing circuit  200  at need so that the CD-ROM drive executes various operations.  
           [0012]    The RF amplifier  220  of the CD-ROM drive having the aforementioned structure internally varies the amplification factor for the RF signal with various levels of RF signals for reproducing data from various optical disks such as a CD, a CD-ROM, a CD-RW (compact disk rewritable) and the like. Therefore, the RF amplifier  220  comprises a PGA (programmable gain amplifier) or the like varying the amplification factor for the RF signal, and employs a variable resistance circuit settable to various resistance values for gain control.  
           [0013]    [0013]FIG. 8 is a circuit diagram showing the structure of a conventional variable resistance circuit. The variable resistance circuit shown in FIG. 8 includes a decoding circuit  300 , switches SW 0  to SW 255  and resistors TR 0  to TR 255 .  
           [0014]    The 256 resistors TR 0  to TR 255  are serially connected with each other, the resistance values of all resistors TR 0  to TR 255  are set to R (Ω), and the resistors TR 0  to TR 255  are identical to each other. The switches SW 0  to SW 255 , connected in parallel with the corresponding ones of the resistors TR 0  to TR 255  respectively, are identical to each other. When the switches SW 0  to SW 255  are turned on, the resistors TR 0  to TR 255  connected therewith are so bypassed as to change the resistance value of the variable resistance circuit.  
           [0015]    Control signals d1 to d8 of eight bits are input in the decoding circuit  300 . The control signal d1 expresses the least significant bit, the control signal d8 expresses the most significant bit, and the respective values of 0 to 255 can be expressed by the control signals d1 to d8. The decoding circuit  300  decodes the control signals d1 to d8 of eight bits and outputs control signals for turning on/off the switches SW 0  to SW 255  and setting resistance values corresponding to data expressed by the control signals d1 to d8 of eight bits to the switches SW 0  to SW 255 .  
           [0016]    The switches SW 0  to SW 255  are turned on/off by the control signals output from the decoding circuit  300  respectively, and the ON-state switches bypass the resistors. Therefore, the resistance value of the variable resistance circuit is set to an arbitrary value among O (Ω), R (Ω), 2R (Ω), . . . , 255R (Ω) by bypassing an arbitrary resistor among the 256 resistors TR 0  to TR 255  in response to the control signals d1 to d8 of eight bits.  
           [0017]    [0017]FIG. 9 is a circuit diagram showing the structure of another conventional variable resistance circuit. The variable resistance circuit shown in FIG. 9 includes switches SW 10  to SW 17  and resistors TR 10  to TR 17 . The eight resistors TR 10  to TR 17  are serially connected with each other. The resistors TR 10 , TR 11  and TR 12  have resistance values R (Ω), 2R (Ω) and 4R (Ω) respectively, and the resistance values of the subsequent resistors TR 13  to TR 17  are successively doubled so that the resistance value of the final resistor TR 17  is set to 128 R (Ω).  
           [0018]    The switches SW 10  to SW 17  are connected in parallel with the corresponding ones of the resistors TR 10  to TR 17  respectively, and turned on/off thereby bypassing the resistors TR 10  to TR 17  connected therewith.  
           [0019]    The aforementioned control signals d1 to d8 of eight bits are input in the switches SW 10  to SW 17  respectively, for setting the resistance value of the variable resistance circuit to an arbitrary value among O (Ω), 2R (Ω), . . . , 255R (Ω).  
           [0020]    Linearity of the resistance value of the variable resistance circuit shown in FIG. 9 is deteriorated due to parasitic resistances of the switches SW 10  to SW 17 . Assuming that the parasitic resistance value of each of the switches SW 10  to SW 17  is r (Ω), the resistance value of the variable resistance circuit is 255R (Ω) when all switches SW 0  to SW 17  are off, 254R+r×R/(r+R) (Ω) when the switch SW 10  is on and the switches SW 11  to SW 17  are off, 253R+2r×R/(r+2R) (Ω) when the switch SW 11  is on and the switches SW 10  and SW 12  to SW 17  are off, or 252R+r×R/(r+R)+2r×R/(r+2R) (Ω) when the switches SW 10  and SW 11  are on and the switches SW 12  to SW 17  are off.  
           [0021]    Thus, the change rate of the resistance value of the variable resistance circuit is R−r×R/(r+R) (Ω), R+r×R/(r+R)−2r×R/(r+2R) (Ω) or R−r×R/(r+R) (Ω). In other words, even if the change rate of the resistance value by the resistors TR 10  to TR 17  is constant, the change rate of the resistance value by the parasitic resistances of the switches SW 10  to SW 17  is not constant. Therefore, the change rate is not constant but the linearity of the resistance value of the variable resistance circuit is deteriorated due to the parasitic resistances of the switches SW 10  to SW 17 .  
         SUMMARY OF THE INVENTION  
         [0022]    An object of the present invention is to provide a variable resistance circuit capable of setting the resistance value in high precision, an operational amplification circuit employing this variable resistance circuit and a semiconductor integrated circuit employing this operational amplification circuit.  
           [0023]    A variable resistance circuit that has a variable resistance value being gradually variable, according to one aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the bypass circuit includes a plurality of transistors selectively turned on or off, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed, and gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0024]    In the variabe resistance circuit, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. Thus, various resistance values can be set by selectively turning on or off the plurality of transistors. The gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0025]    The plurality of transistors may be connected to ends of the plurality of resistors respectively.  
           [0026]    A variable resistance circuit that has a variable resistance value being gradually variable, according to another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a switch circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the switch circuit includes a plurality of switches selectively turned on or off, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more switches being turned on and one ore more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed, and parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0027]    In the variabe resistance circuit, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more switches being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. Thus, various resistance values can be set by selectively turning on or off the plurality of switches. The parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value varies approximately in steps of a predetermined value. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0028]    The plurality of switches may include a plurality of transistors connected to ends of the plurality of resistors respectively. Each of the plurality of switches may include a CMOS switch. In this case, a circuit including the variable resistance circuit can be formed by a CMOS integrated circuit.  
           [0029]    A variable resistance circuit that has a variable resistance value being gradually variable, according to still another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the bypass circuit includes a plurality of: transistors selectively turned on or off, the plurality of transistors are connected to ends of the plurality of resistors respectively, and gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0030]    In the variabe resistance circuit, the bypass circuit includes a plurality of transistors selectively turned on or off, the plurality of transistors are connected to ends of the plurality of resistors respectively. Thus, various resistance values can be set by selectively turning on or off the plurality of transistors. The gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0031]    A variable resistance circuit that has a variable resistance value being gradually variable, according to still another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a switch circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the switch circuit includes a plurality of switches selectively turned on or off, the plurality of switches are connected to ends of the plurality of resistors, and parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0032]    In the variable resistance circuit, the switch circuit includes a plurality of switches selectively turned on or off, and the plurality of switches are connected to ends of the plurality of resistors. Thus, various resistance values can be set by selectively turning on or off the plurality of switches. The parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value varies approximately in steps of a predetermined value. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0033]    Each of the plurality of switches may include a CMOS switch. In this case, a circuit including the variable resistance circuit can be formed by a CMOS integrated circuit.  
           [0034]    A variable resistance circuit that has a variable resistance value being gradually variable based on a control signal, according to still another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the bypass circuit includes a plurality of transistors selectively turned on or off based on the control signal, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed, and gate widths of the plurality of transistors are so set that the variable resistance value has approximately linearity with respect to the control signal.  
           [0035]    In the variable resistance circuit, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. Thus, various resistance values can be set by selectively turning on or off the plurality of transistors. The gate widths of the plurality of transistors are so set that the variable resistance value has approximately linearity with respect to the control signal. Thus, plurality of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0036]    The plurality of transistors may be connected to ends of the plurality of resistors respectively.  
           [0037]    A variable resistance circuit that has a variable resistance value being gradually variable based on a control signal, according to still another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a switch circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the switch circuit includes a plurality of transistors selectively turned on or off based on the control signal, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed, and parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value has approximately linearity with respect to the control signal.  
           [0038]    In the variable resistance circuit, the variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. Thus, various resistance values can be set by selectively turning on or off the plurality of switches. The parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value has approximately linearity with respect to the control signal. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0039]    The plurality of switches may include a plurality of transistors connected to ends of the plurality of resistors respectively. Each of the plurality of switches may include a CMOS switch. In this case, a circuit including the variable resistance circuit can be formed by a CMOS integrated circuit.  
           [0040]    A variable resistance circuit that has a variable resistance value being gradually variable based on a control signal, according to still another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the bypass circuit includes a plurality of transistors selectively turned on or off based on a control signal, the plurality of transistors are connected to ends of the plurality of resistors respectively, and gate widths of the, plurality of transistors are so set that the variable resistance value has approximately linearity with respect to the control signal In the variable resistance circuit, the bypass circuit includes a plurality of transistors selectively turned on or off based on a control signal, and the plurality of transistors are connected, to ends of the plurality of resistors respectively. Thus, various resistance values can be set by selectively turning on or off the plurality of transistors. The gate widths of the plurality of transistors are so set that the variable resistance value has approximately linearity with respect to the control signal. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0041]    A variable resistance circuit that has a variable resistance value being gradually variable based on a control signal, according to still another aspect of the present invention, comprises a resistance circuit including a plurality of resistors serially connected; and a switch circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the switch circuit includes a plurality of switches selectively turned on or off based on a control signal, the plurality of switches are connected to ends of the plurality of resistors respectively, and predetermined resistance values of the plurality of switches in an ON state are so set that the variable resistance value has approximately linearity with respect to the control signal.  
           [0042]    In the variable resistance circuit, the switch circuit includes a plurality of switches selectively turned on or off based on a control signal, and the plurality of switches are connected to ends of the plurality of resistors respectively. Thus, various resistance values can be set by selectively turning on or off the plurality of switches. The predetermined resistance values of the plurality of switches in an ON state are so set that the variable resistance value has approximately linearity with respect to the control signal. Thus, linearity of the variable resistance value can be ensured. Consequently, the resistance value can be set in high precision.  
           [0043]    Each of the plurality of switches may include a CMOS switch. In this case, a circuit including the variable resistance circuit can be formed by a CMOS integrated circuit.  
           [0044]    An operational amplification circuit according to another aspect of the present invention comprises a variable resistance circuit and an operational amplifier, connected with the variable resistance circuit, having an amplification factor varying with the resistance value of the variable resistance circuit, while the variable resistance circuit includes a resistance circuit including a plurality of resistors serially connected; and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the bypass circuit includes a plurality of transistors selectively turned on or off, the plurality of transistors are connected to ends of the plurality of resistors respectively, and gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0045]    In the operational amplification circuit, the aforementioned variable resistance circuit is connected with the operational amplifier for varying the amplification factor with the resistance value of the variable resistance circuit capable of varying the resistance value in high precision, whereby the amplification factor can be set in high precision.  
           [0046]    An operational amplification circuit according to another aspect of the present invention comprises a variable resistance circuit and an operational amplifier, connected with the variable resistance circuit, having an amplification factor varying with the resistance value of the variable resistance circuit, while the variable resistance circuit includes a resistance circuit including a plurality of resistors serially connected; and a switch circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the switch circuit includes a plurality of switches selectively turned on or off, the plurality of switches are connected to ends of the plurality of resistors, and parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0047]    In the operational amplification circuit, the aforementioned variable resistance circuit is connected with the operational amplifier for varying the amplification factor with the resistance value of the variable resistance circuit capable of varying the resistance value in high precision, whereby the amplification factor can be set in high precision.  
           [0048]    A semiconductor integrated circuit according to still another aspect of the present invention, receiving an output signal from an optical pickup, comprises an operational amplification circuit amplifying the output signal from the optical pickup and another circuit, while the operational amplification circuit and the other circuit are integrated into a single chip by a CMOS integrated circuit, the operational amplification circuit includes a variable resistance circuit and an operational amplifier, connected with the variable resistance circuit, having an amplification factor varying with the resistance value of the variable resistance circuit, the variable resistance circuit includes a resistance circuit including a plurality of resistors serially connected; and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the bypass circuit includes a plurality of transistors selectively turned on or off, the plurality of transistors are connected to ends of the plurality of resistors respectively, and gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0049]    The semiconductor integrated circuit employs the aforementioned operational amplification circuit capable of setting the amplification factor in high precision for the amplification circuit amplifying the output signal from the optical pickup, and integrates the amplification circuit and the other circuit into a single chip by the CMOS integrated circuit, whereby a one-chip CMOS integrated circuit for an optical disk drive including a high-precision amplification circuit can be implemented.  
           [0050]    A semiconductor integrated circuit according to still another aspect of the present invention, receiving an output signal from an optical pickup, comprises an operational amplification circuit amplifying the output signal from the optical pickup and another circuit, while the operational amplification circuit and the other circuit are integrated into a single chip by a CMOS integrated circuit, the operational amplification circuit includes a variable resistance circuit and an operational amplifier, connected with the variable resistance circuit, having an amplification factor varying with the resistance value of the variable resistance circuit, the variable resistance circuit includes a resistance circuit including a plurality of resistors serially connected; and a switch circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors, wherein the switch circuit includes a plurality of switches selectively turned on or off, the plurality of switches are connected to ends of the plurality of resistors, and parasitic resistance values of the plurality of switches in an ON state are so set that the variable resistance value varies approximately in steps of a predetermined value.  
           [0051]    The semiconductor integrated circuit employs the aforementioned operational amplification circuit capable of setting the amplification factor in high precision for the amplification circuit amplifying the output signal from the optical pickup and integrates the amplification circuit and the other circuit into a single chip by the CMOS integrated circuit, whereby a one-chip CMOS integrated circuit for an optical disk drive including a high-precision amplification circuit can be implemented.  
           [0052]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0053]    [0053]FIG. 1 is a circuit diagram showing the structure of a variable resistance circuit according to a first embodiment of the present invention;  
         [0054]    [0054]FIG. 2 is a circuit diagram showing an exemplary switch shown in FIG. 1;  
         [0055]    [0055]FIG. 3 illustrates an exemplary operational amplification circuit employing the variable resistance circuit shown in FIG. 1;  
         [0056]    [0056]FIG. 4 is a circuit diagram showing the structure of a tracking-system signal processing circuit of an RF amplifier employing the operational amplification circuit shown in FIG. 3;  
         [0057]    [0057]FIG. 5 is a block diagram showing the structure of a semiconductor integrated circuit for a CD-ROM drive including the RF amplifier shown in FIG. 4;  
         [0058]    [0058]FIG. 6 is a circuit diagram showing the structure of a variable resistance circuit according to a second embodiment of the present invention;  
         [0059]    [0059]FIG. 7 is a block diagram showing the structure of a conventional semiconductor integrated circuit applied to a CD-ROM drive;  
         [0060]    [0060]FIG. 8 is a circuit diagram showing the structure of a conventional variable resistance circuit;  
         [0061]    [0061]FIG. 9 is a circuit diagram showing the structure of another conventional variable resistance circuit; 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0062]    (First Embodiment)  
         [0063]    A first embodiment of the present invention is described with reference to FIGS.  1  to  6 .  
         [0064]    [0064]FIG. 1 is a circuit diagram showing the structure of a variable resistance circuit VT according to the first embodiment of the present invention.  
         [0065]    Referring to FIG. 1, the variable resistance circuit VT includes resistors T 1  to T 8  and switches S 1  to S 8 . The resistor T 1  is connected between a terminal N 1  and the resistor T 2 , and the switch S 1  is connected in parallel with the resistor T 1 . Similarly, the resistors T 2  to T 8  and the switches S 2  to S 8  connected in parallel with each other are serially connected. Control signals d1 to d8 of eight bits are input in the switches S 1  to S 8  respectively so that the switches S 1  to S 8  are turned on/off in response to the control signals d1 to d8.  
         [0066]    The resistors T 1  and T 2  have resistance values R (Ω) and 2R (Ω) respectively, and the resistance values of the subsequent resistors T 3  to T 8  are successively doubled. In other words, each resistance value of the resistors T 1  to T 8  is set to R×2 i  (i=0 to 7) (Ω). The resistance value of each parasitic resistance of the switches S 1  to S 8  in an ON state is set to r×2 i  (i=0 to 7) (Ω). Therefore, the resistance values of the resistors T 1  to T 8  and the resistance values of the parasitic resistances of the switches S 1  to S 8  connected in parallel with the resistors T 1  to T 8  are in proportion to each other.  
         [0067]    Among the control signals d1 to d8 corresponding to data of eight bits, the control signal d1 corresponds to the least significant bit, and the control signal d8 corresponds to the most significant bit. Thus, values 0 to 255 can be expressed by the control signals d1 to d8. The switches S 1  to S 8  are turned off when the control signals d1 to d8 are 1, while the former are turned on when the latter are zero for bypassing the resistors connected with the ON-state switches.  
         [0068]    When 1, 1, 1, 1, 1, 1, 1 and 1 are input in the switches S 1  to S 8  as the control signals d1 to d8 respectively, for example, all switches S 1  to S 8  are turned off and the resistance values of the resistors T 1  to T 8  are added up so that the resistance value of the variable resistance circuit VT is 255R (Ω).  
         [0069]    When 0, 1, 1, 1, 1, 1, 1 and 1 are input as the control signals d1 to d8 respectively, the switch S 1  is turned on and the switches S 2  to S 8  are turned off. At this time, the resistors T 2  to T 8  are serially connected and the resistance value of this part reaches 254R (Ω), the combined resistance value of the switch S 1  and the resistor T 1  is r×R/(r+R) (Ω), and the resistance value of the variable resistance circuit VT is 254R+r×R/(r+R) (Ω).  
         [0070]    When 1, 0, 1, 1, 1, 1, 1 and 1 are input as the control signals d1 to d8 respectively, the resistance value of the variable resistance circuit VT is 253R+2r×R/(r+R) (Ω). The resistance value of the variable resistance circuit VT thereafter similarly varies with the control signals d1 to d8, to reach R+254r×R/(r+R) (Ω) when 1, 0, 0, 0, 0, 0, 0 and 0 are input or reach R+255r×R/(r+R) (Ω) when 0, 0, 0, 0, 0, 0, 0 and 0 are input.  
         [0071]    As hereinabove described, the resistance value of the variable resistance circuit VT varies by R−r×R/(r+R) (Ω) with the control signals d1 to d8. Thus, the resistance value of the variable resistance circuit VT varies by the constant rate R−r×R/(r+R) (Ω), and can ensure linearity.  
         [0072]    While eight resistors T 1  to T 8  and eight switches S 1  to S 8  are employed in the above description, the numbers of the serially connected resistors and switches are not particularly restricted to the above but other numbers of resistors and switches may be employed in response to the resistance value to be varied etc. Further, the resistance values of the resistors T 1  to T 8  are not particularly restricted to the above either but various resistance values can be employed in response to the resistance value to be varied etc. while the arrangement of the resistance values is not particularly restricted to the aforementioned arrangement successively increased from the terminal N 1  toward the terminal N 2  but the resistors T 1  to T 8  may be arranged on different positions. In addition, the resistance values of the parasitic resistances may not be completely in proportion to the resistance values of the resistors T 1  to T 8  but may be in positive correlation similar to proportion to the resistance values of the resistors T 1  to T 8 .  
         [0073]    [0073]FIG. 2 is a circuit diagram showing an exemplary switch S 1  forming each of the switches S 1  to S 8  shown in FIG. 1. The switch S 1  shown in FIG. 2 includes an N-channel MOS field-effect transistor (hereinafter referred to as an NMOS transistor) Q 1 , a p-channel MOS field-effect transistor (hereinafter referred to as a PMOS transistor) Q 2  and an inverter I 1 .  
         [0074]    The NMOS transistor Q 1  and the PMOS transistor Q 2  are connected between the terminals N 11  and N 12 , so that the control signal di (i=1 to 8) is input in the gate of the NMOS transistor Q 1  through the inverter I 1  and also input in the gate of the PMOS transistor Q 2  for forming a CMOS switch. Therefore, the NMOS transistor Q 1  and the PMOS transistor Q 2  are turned off when 1 is input as the control signal di, and turned on when 0 is input.  
         [0075]    When employing CMOS switches each having the aforementioned structure for the switches S 1  to S 8  shown in FIG. 1, the gate lengths of the NMOS transistors Q 1  and the PMOS transistors Q 2  are set constant, gate widths W are varied and the resistance values of the parasitic resistances of the switches S 1  to s 8  are set as described above.  
         [0076]    Assuming that W represents the gate width W of the NMOS transistor Q 1  and the PMOS transistor Q 2  of the switch S 1 , the gate width of the NMOS transistor Q 1  and the PMOS transistor Q 2  of the switch S 2  is set to W/2, the gate width of the NMOS transistor Q 1  and the PMOS transistor Q 2  of the switch S 3  is set to W/4, and the gate widths of the remaining switches S 4  to S 8  are successively halved. The resistance values of the parasitic resistances of the CMOS switches can be set to r×2 i  (i=0 to 7) (Ω) by varying the gate widths in the aforementioned, manner.  
         [0077]    When forming the switches S 1  to S 8  by transistors as described above, the linearity of the variable resistance circuit VT is independent of the resistance values of the parasitic resistances and hence the transistor sizes may not be particularly increased but the circuit area of the variable resistance circuit VT can be reduced.  
         [0078]    The switches S 1  to S 8  are not particularly restricted to the aforementioned CMOS switches but may be formed by other switches so far as the resistance values of the parasitic resistances in ON states can beset in response to the resistance values of the resistors T 1  to T 8  connected therewith. Further, the gate widths of the transistors may not be completely in inverse proportion to the resistance values of the resistors T 1  to T 8  but may be in negative correlation similar to inverse proportion to the resistance values of the resistors T 1  to T 8 .  
         [0079]    [0079]FIG. 3 illustrates an exemplary operational amplification circuit employing the variable resistance circuit VT shown in FIG. 1. The operational amplification circuit shown in FIG. 3 includes the variable resistance circuit VT, an operational amplifier  1  and a resistor T 9 .  
         [0080]    Referring to FIG. 3, the resistor T 9  is connected between an inversion input terminal of the operational amplifier  1  and a terminal N 1 , while a non-inversion input terminal receives a prescribed reference voltage. The variable resistance circuit VT shown in FIG. 1, forming a negative feedback loop, is connected between the inversion input terminal and an output terminal of the operational amplifier  1 , so that the resistor T 1  and the switch S 1  are connected to the output terminal and the resistor T 8  and the switch S 8  are connected to the inversion input terminal.  
         [0081]    Assuming that VR represents the resistance value of the variable resistance circuit VT and Rf represents the resistance value of the resistor T 9 , a signal input in the terminal N 1  is amplified with an amplification factor of VR/Rf and output from a terminal N 3  in the operational amplification circuit shown in FIG. 3, due to the aforementioned structure. At this time, the variable resistance circuit VT can vary the resistance value VR in 256 stages in response to the control signals d1 to d8 with excellent linearity, whereby the signal input from the terminal N 1  can be amplified in high precision and output from the terminal N 3 .  
         [0082]    [0082]FIG. 4 is a circuit diagram showing the structure of a tracking-system signal processing part of an RF amplifier employing the operational amplification circuit shown in FIG. 3.  
         [0083]    In the RF amplifier for a CD-ROM drive processing each signal output from an optical pickup employing a photodetection part formed by a quartered photodetection part provided at the center for performing focus servo control employing a stigmatism and two photodetection parts provided on both sides of the quartered photodetection part for performing tracking servo control by a three beam method, FIG. 4 shows a part subtracting a tracking signal F of the second tracking servo photodetection part from a tracking signal E from the first tracking servo photodetection part and outputting a tracking error signal TE for performing tracking servo control.  
         [0084]    The RF amplifier shown in FIG. 4 includes resistors T 11  to T 23 , operational amplifiers  11  to  18 , variable resistance circuits VT 11  to VT 15 , capacitors C 11  and C 12  and a variable capacitor VC 11 .  
         [0085]    An end of the resistor T 11  is connected to a terminal N 11 , and receives the tracking signal E from the first photodetection part. An inversion input terminal and a non-inversion input terminal of the operational amplifier  11  are connected to the other end of the resistor T 11  and a terminal N 13  receiving a shift voltage VREF1 respectively, and the resistor T 13  is connected between the inversion input terminal and an output terminal. Thus, a level shifting circuit is formed for shifting the tracking signal E input from the terminal T 11  from a 5 V-system signal to a 3 V-system signal by the shift voltage VREF1.  
         [0086]    The variable resistance circuit VT 11  is connected between the output terminal of the operational amplifier  11  and an inversion input terminal of the operational amplifier  13 , a non-inversion input terminal of the operational amplifier  13  receives a prescribed reference voltage, and the resistor T 15  is connected between the inversion input terminal and an output terminal of the operational amplifier  13 . The variable resistance circuit VT 11  is formed similarly to the variable resistance circuit VT shown in FIG. 1 with a plurality of resistors, and four types of resistance values can be set for the variable resistance circuit VT 11 .  
         [0087]    Thus, a programmable gain amplifier is so formed that the amplification factor thereof can be set to 0 dB, 6 dB, 14 dB and 20 dB. Therefore, the RF amplifier shown in FIG. 4 is applicable to two types of optical pickups outputting signals of 300 mV and 600 mV by switching the amplification factor to 6 dB, and is also applicable to an optical pickup for a CD-RW drive by switching the amplification factor to 14 dB.  
         [0088]    The resistor T 17  is connected between the output terminal of the operational amplifier  13  and an inversion input terminal of the operational amplifier  15 , a non-inversion input terminal of the operational amplifier  15  receives the prescribed reference voltage, and the variable resistance circuit VT 13  is connected between the inversion input terminal and an output terminal of the operational amplifier  15 . The variable resistance circuit VT 13  is formed similarly to the variable resistance circuit VT shown in FIG. 1, and the resistance value thereof can be switched in 256 stages in response to control signals of eight bits. Thus, a balance circuit is so formed that switching can be made in 256 stages in the rage of 0 dB to 6 dB in response to the control signals of eight bits.  
         [0089]    An end of the resistor T 12  is connected to the terminal N 12 , and receives the tracking signal F from the second photodetection part. An inversion input terminal and a non-inversion input terminal of the operational amplifier  12  are connected to the other end of the resistor T 12  and the terminal N 13  receiving the shift voltage VREF1, and the resistor T 14  is connected between the inversion input terminal and an output terminal. Thus, a level shifting circuit is formed for shifting the tracking signal F input from the terminal N 12  from a 5 V-system signal to a 3 V-system signal with the shift voltage VREF1.  
         [0090]    The variable resistance circuit VT 12  is connected between the output terminal of the operational amplifier  12  and an inversion input terminal of the operational amplifier  14 , a non-inversion input terminal of the operational amplifier  14  receives the prescribed reference voltage, and the resistor T 16  is connected between the inversion input terminal and an output terminal of the operational amplifier  14 . The variable resistance circuit VT 12  is formed similarly to the variable resistance circuit VT 11 , and four types of resistance values can be set therefor. Thus, a programmable gain amplifier is so formed that the amplification factor thereof can be set to 0 dB, 6 dB, 14 dB and 20 dB.  
         [0091]    The resistor T 18  is connected between the output terminal of the operational amplifier  14  and an inversion input terminal of the operational amplifier  16 , a non-inversion input terminal of the operational amplifier  16  is connected to a terminal N 25  receiving an externally settable reference voltage VDA2, and the variable resistance circuit VT 14  is connected between the inversion input terminal and an output terminal of the operational amplifier  16 . The variable resistance circuit VT 14  is formed similarly to the variable resistance circuit VT 13 , and the resistance value thereof can be switched in 256 stages in response to control signals of eight bits. Thus, a balance circuit is formed and switching can be made in 256 stages in the range of 0 dB to 6 dB in response to the control signals of eight bits.  
         [0092]    The resistor T 19  is connected between the output terminal of the operational amplifier  15  and a non-inversion input terminal of the operational amplifier  17 , the capacitor C 11  and the resistor T 21  are connected between an inversion input terminal and a non-inversion output terminal of the operational amplifier  17 , the resistor T 20  is connected between the output terminal of the operational amplifier  16  and the non-inversion input terminal of the operational amplifier  17 , the resistor T 22  and the capacitor C 12  are connected between the non-inversion input terminal and an inversion output terminal of the operational amplifier  17 , and the inversion output terminal of the operational amplifier  17  receives the prescribed reference voltage. Thus, a subtraction circuit is formed and the non-inversion output terminal of the operational amplifier  17  outputs a signal obtained by subtracting the output of the operational amplifier  15  from the output of the operational amplifier  16 .  
         [0093]    The variable resistance circuit VT 15  is connected between the non-inversion output terminal of the operational amplifier  17  and an inversion input terminal of the operational amplifier  18 , anon-inversion input terminal of the operational amplifier  18  receives the prescribed reference voltage, and the variable capacitor VC 11  and the resistor T 23  are connected between the inversion input terminal and an output terminal of the operational amplifier  18 .  
         [0094]    The variable resistance circuit VT 15  is formed similarly to the variable resistance circuit VT shown in FIG. 1 with a plurality of resistors, and the resistance value thereof can be switched in 16 stages with control signals of four bits. The variable capacitor VC 11  is so formed that two types of capacitances can be set therefor.  
         [0095]    Thus, a programmable gain amplifier is formed and switching can be made in 16 stages in a range of −6 dB to 6 dB in response to the control signals of four bits while two types of frequency characteristics can be set.  
         [0096]    Due to the aforementioned structure, the tracking signal E from the first photodetection part is shifted from a 5 V-system signal to a 3 V-system signal with the shift voltage VREF1 by the operational amplifier  11  serving as a level shifting circuit, amplified by the operational amplifier  13  serving as a programmable gain amplifier with the amplification factor of 0 dB, 6 dB, 14 dB or 20 dB and balance-controlled by the operational amplifier  15  serving as a balance circuit at any level of the 256 stages in the range of 0 dB to 6 dB, while the output signal F from the second photodetection part is also processed similarly to the above.  
         [0097]    The output signals E and F controlled in level etc. in the aforementioned manner are subjected to subtraction by the operational amplifier  17  serving as a subtraction circuit and finally amplified by the operational amplification circuit  18  with any amplification factor of the 16 stages in the range of −6 dB to 6 dB, for outputting the tracking error signal TE.  
         [0098]    A focus-system signal processing part (not shown) is formed similarly to the above, for operating (A+C)−(B+D) with output signals A, B, C and D of the quartered photodetection part and outputting a focus error signal FE.  
         [0099]    As hereinabove described, the RF amplifier shown in FIG. 4 employs a number of variable resistance circuits, while the resistance values thereof can be set in high precision by employing the inventive variable resistance circuit. Therefore, the RF amplifier itself can be improved in precision.  
         [0100]    [0100]FIG. 5 is a block diagram showing the structure of a semiconductor integrated circuit  100  for a CD-ROM drive, including the RF amplifier shown in FIG. 4.  
         [0101]    The semiconductor integrated circuit  100  shown in FIG. 5 includes an RF amplifier  101 , a DSP  102 , a DAC  103 , a servo circuit  104 , a microcomputer  105 , an error correction circuit  106  and a DRAM  107 .  
         [0102]    The semiconductor integrated circuit  100  is a CMOS integrated circuit formed by integrating the RF amplifier  101 , the DSP  102 , the DAC  103 , the servo circuit  104 , the microcomputer  105 , the error correction circuit  106  and the DRAM  107  into a single chip through a CMOS process. In consideration of the cost, the DRAM  107  may alternatively be formed as another chip while integrating the RF amplifier  101 , the DSP  102 , the DAC  103 , the servo circuit  104 , the microcomputer  105  and the error correction circuit  106  into a single chip as a CMOS integrated circuit and sealing the chips in the same package.  
         [0103]    An optical pickup  110  converts data recorded on a CD-ROM disk to an RF signal and outputs the same to the RF amplifier  101 . The RF amplifier  101 , formed similarly to the RF amplifier shown in FIG. 4, generates a focus error signal, a tracking signal and a reproduced signal (EFM (eight to fourteen modulation) signal) etc. through the aforementioned processing and outputs these signals to the DSP  102 .  
         [0104]    The DSP  102  and the servo circuit  104  create a control signal for controlling the optical pickup  110  from the focus error signal and the tracking error signal etc., and output the control signal to a drive circuit  120 . The drive circuit  120  drives an actuator provided in the optical pickup  110  in response to the input control signal, for controlling the optical pickup  110  to reproduce an excellent RF signal.  
         [0105]    The error correction circuit  106  performs error correction on the reproduced data with the DRAM  107 , converts the reproduced data to an analog signal through the DAC  103  and outputs the analog signal when reproducing a sound signal.  
         [0106]    The microcomputer  240  serves as a system controller controlling operations of the overall drive, and transmits/receives data etc. to/from the DSP  102  etc. at need, so that the CD-ROM drive executes various operations.  
         [0107]    As hereinabove described, the semiconductor integrated circuit  100  shown in FIG. 6 can be integrated into a single chip through the CMOS process along with other blocks by employing the RF amplifier  101  reduced in area and improved in precision, for implementing a miniature one-chip CMOS integrated circuit for a CD-ROM having high performance.  
         [0108]    While the above description has been made with reference to the circuit for the CD-ROM drive, the circuit to which the inventive variable resistance circuit etc. are applied is not particularly restricted to this example but the present invention can, be similarly applied to various circuits requiring high precision, for attaining a similar effect.  
         [0109]    (Second Embodiment)  
         [0110]    A second embodiment of the present invention is described with reference to FIG. 7. FIG. 7 is a circuit diagram showing the structure of a variable resistance circuit VT according to the second embodiment. The second embodiment is different from the first embodiment only in a point that a resistor T 0  is provided in series with a resistor T 8  in the variable resistance circuit VT, and the remaining structure of the former is similar to that of the latter. The resistor T 0  is a fixed resistor connected with no switch in a parallel manner.  
         [0111]    When applying the variable resistance circuit VT according to the second embodiment to the operational amplification circuit shown in FIG. 3, the resistor T0 is located between the resistor T 8  and the inversion input terminal of the operational amplifier  1 . Thus, the fixed resistor T 0  included in the variable resistance circuit VT can freely control the minimum amplitude of a gain.  
         [0112]    Further, the resistor T 0  is located between the resistor T 8  and the inversion input terminal of the operational amplifier  1 , whereby the signal of the output terminal N 3  of the operational amplifier  1  passes through the resistors T 1  to T 8  and thereafter passes through the fixed resistor T 0  to be fed back to the inversion input terminal of the operational amplifier  1 . Thus, it follows that the parasitic capacitances of the switches S 1  to S 8  are present in front of the fixed resistor T 0  and a parasitic capacitance generated in the rear stage of the fixed resistor T 0  is extremely reduced, so that deterioration of the frequency characteristic can be prevented.  
         [0113]    According to this embodiment, an operational amplification circuit having an excellent frequency characteristic and an integrated circuit employing this operational amplification circuit can be provided.  
         [0114]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.