Abstract:
A variable delay apparatus comprises a calibrating unit receiving a signal from a variable delay unit and from a plurality of fixed delay sources, the calibrating unit comparing the signal from the variable delay unit with a plurality of signals from the fixed delay sources to control operation of the variable delay unit over a delay range independently of environmentally-induced drift.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is related to concurrently filed, co-pending, and commonly assigned U.S. patent application Ser. No. ______, Attorney Docket No. 71866-204-10700762, entitled “SYSTEMS AND METHODS FOR PROVIDING TRIGGER TIMING”; and U.S. patent application Ser. No. ______, Attorney Docket No. 71866-205-10700765, entitled “SYSTEMS AND METHODS USING MULTIPLE DOWN-CONVERSION RATIOS IN ACQUISITION WINDOWS”, the disclosures of which are hereby incorporated herein by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present description relates, in general, to signal delays and, more specifically, to systems and methods for providing delayed signals. 
       BACKGROUND OF THE INVENTION 
       [0003]    Equivalent time sampling is a technique to sample substantially repeating signals. In one example, a high-frequency signal is sampled at a given point during a first cycle. During the next cycle, it is sampled at another point offset some amount from the first point, the offset represented in time by At. In successive cycles, At is increased so that the sampling point moves, eventually covering the entire waveform. Thus, the waveform is sampled over a time window spanning multiple signals cycles, and the samples can be processed to create a reconstructed waveform with the same shape as the original waveform, though “stretched out” over time. Analysis can then be performed on the reconstructed waveform instead of using the original, high-frequency signal. 
         [0004]    One technique to perform equivalent time sampling on a wave uses two trigger signals. The first trigger signal is fixed in frequency, and it triggers the transmission of the waveform. The second trigger signal is delayed from the first trigger, and it is used to cause a sampling of the waveform. The delay of the second trigger is has a Δt that is increased with each cycle, as described above. 
         [0005]    Prior art systems for creating the two trigger signals in radar systems are based on analog circuits. For example, one system has a dual-ramp mode which has a slow ramp and a fast ramp, where the slow ramp adds delay in a finer increments than does the fast ramp. The slow ramp determines where on the fast ramp the pulse is generated. The signal is then fed to an analog comparator to generate the pulse at the desired points. 
         [0006]    Such prior art systems usually have several disadvantages. For instance, such systems tend to perform differently at different operating temperatures and ages. Moreover, delay units of the same model have intrinsic fabrication variations. Tuning such systems to compensate for the temperature drift, age variation, and fabrication variation involves adjusting one or more potentiometers, which is difficult to do with precision during operation of the device. There is currently no system available that provides delayed signals reliably and with effective and efficient tuning. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    The present invention is directed to systems and methods for calibrating delayed signals and further to systems and methods for providing digitally controlled triggers in radar systems. 
         [0008]    In one example embodiment, a technique compares a delayed signal from a programmable delay line to a known, fixed delay. The known, fixed delay may be independent of various phenomena that cause operational variance in the programmable delay line so that it is a dependable calibration delay. The delayed signal is adjusted so that its delay eventually equals or closely approximates the known delay. Moreover, multiple delay points in the signal may be calibrated in this way with the use of multiple known delays. 
         [0009]    In some embodiments, systems and methods use a digitally programmable delay line to achieve strobe modulation for equivalent time sampling for radar acquisition. Calibration techniques, such as the one described above, may be used to calibrate the delay from the digitally programmable delay line. 
         [0010]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0012]      FIG. 1  is an illustration of an exemplary system adapted according to one embodiment of the invention; 
           [0013]      FIG. 2  is an exemplary delay diagram for the system of  FIG. 1 ; 
           [0014]      FIG. 3  is an exemplary delay diagram for the system of  FIG. 1 , showing example calibration points; 
           [0015]      FIG. 4  is an illustration of an exemplary system adapted according to one embodiment of the invention for providing a delayed signal and calibrating the delay mechanism; 
           [0016]      FIG. 5  is a signal timing diagram for the operation of the system of  FIG. 4 ; 
           [0017]      FIG. 6  is an illustration of an exemplary system adapted according to one embodiment of the invention; 
           [0018]      FIG. 7  is an illustration of an exemplary method for calibrating a signal, adapted according to one embodiment of the invention; and 
           [0019]      FIG. 8  is an illustration of an exemplary method for providing a delayed signal to a radar system, such as in the system of  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]      FIG. 1  is an illustration of exemplary system  100  adapted according to one embodiment of the invention. System  100  includes variable delay unit  101 . Variable delay unit can be any of a variety of delay units now known or later developed that apply a variable delay to a signal. Examples include a digitally controllable, programmable delay line model SY89296, available from Micrel, Inc. Variable delay unit  101  provides delay in a series of discrete steps, as explained in more detail below with regard to  FIG. 2 . 
         [0021]    System  100  also includes second delay  102 . Second delay  102  may be any of a variety of delay components now known or later developed, including but not limited to signal traces and coaxial cable. Coaxial cable is a desirable material in many embodiments due to its relatively precise and constant delay characteristics, even at a variety of operating temperatures. In system  100 , the signal that is input to second delay  102  includes the delay provided by variable delay unit  101 . In effect, variable delay unit  101  and second delay  102  are arranged in system  100  as fine step and coarse step delays, respectively. 
         [0022]    System  100  also includes output unit  103  that selectively outputs one of its two input signals. Output unit  103  can include any kind of switch, such as a digital multiplexor. In one example, smaller delays are produced by outputting the signal from variable delay unit  101 , whereas larger delays are produced by outputting the signal from second delay  102 . The smallest delay can be produced by outputting the signal from variable delay  101  when it is at or near its defined minimum delay. Variable delay unit  101  can be controlled to produce an increasing delay with each cycle of the trigger signal. After variable delay unit  103  reaches its defined maximum, output unit  103  switches its output to the signal from second delay  102 , and variable delay  101  decreases its delay at or near its minimum (e.g., a defined zero). Variable delay  101  then continues to increase its delay with each successive cycle. 
         [0023]    While not shown, it should be noted that system  100  can be controlled by any of a variety of control units. For example, digital control can be provided by a general use processor (as in a personal computer), an Application Specific Integrated Circuit (ASIC), a specialized digital control chip, a Field Programmable Gate Array (FPGA), and/or the like. 
         [0024]      FIG. 2  is an exemplary delay diagram for system  100  ( FIG. 1 ). In one example, fixed delay  102  provides 10 nsec of delay, and variable delay  101  provides up to 10 nsec of delay in linearly-increasing discrete steps. This allows for a total adjustment range of 20 nsec, as shown. Range  200  shows discrete steps attributable to variable delay  101 , when output unit  103  outputs the signal from variable delay  101 . Range  201  shows the delay that is possible when output unit  103  outputs the signal from fixed delay  102 , wherein the first 10 nsecs are attributable to fixed delay  102 , and the additional delay steps are provided by variable delay  102  with each successive cycle. Using this scenario, the delay “ramp” increases monotonically over the entire 20 nsec range. 
         [0025]      FIG. 3  is an exemplary delay diagram for system  100  ( FIG. 1 ), showing example calibration points. A characteristic of some variable delay units (such as unit  101  of  FIG. 1 ) is that performance is often dependent on temperature, age, and/or fabrication variation. For example, the silicon-based Micrel SY89296 experiences drift as the operating temperatures increase. Therefore, the delay provided at one point may be a few nanoseconds off from the corresponding delay step in the same system 5 minutes later. By contrast, wire-based fixed delays are relatively constant over most normal operating temperatures and ages as long as length is constant, though not all fixed delays are necessarily constant. Accordingly, many embodiments may benefit from one or more calibration techniques to compensate for drift and/or variation of delay components. 
         [0026]    One example technique to compensate for drift and/or variation calibrates the delay to three known fixed delays (at points  0 , A, &amp; B in  FIG. 3 ) provided by three known and real delays, for example, from three separate calibration coaxial cables. The calibration points in  FIG. 3  generally correspond to near the beginning of the delay range (Point  0 ), near the middle of the delay range (Point A), and near the end of the delay range (Point B). In an embodiment wherein the calibration delay is provided by coaxial cables, the respective length of each of the cables corresponds to one of the delay points. 
         [0027]    For instance, a first coaxial cable corresponding to Point  0  is cut so that a variable delay (e.g.,  101  of  FIG. 1 ) can be calibrated to match the delay at Point  0  when it is near the beginning of its delay range when a fixed delay (e.g.,  102  of  FIG. 1 ) is not switched in. This delay is chosen to be the defined zero point (e.g., the beginning of a radar observation window) in order to provide room for later adjustment, if needed. (The same can be said for Point B, which is near but not at the high end of the range.) 
         [0028]    Continuing with this example, a second compensation coaxial cable corresponding to Point A is cut so that the variable delay can be calibrated to match the delay when adjusted to near the end of its delay range when the fixed delay line is not switched in. 
         [0029]    As described above with regard to  FIG. 2 , various embodiments switch the output when the variable delay source reaches or nears its defined maximum, for example, by switching to an output that comes from a fixed delay source. In order to improve continuity at this switching point, some embodiments calibrate for Point A both with and without the fixed delay source switched in. 
         [0030]    A third calibration coaxial cable corresponding to point B is cut so that the variable delay can be calibrated to match the output when adjusted to near the its defined maximum when the fixed delay line is switched in. This point can be defined as the end of an observation window. 
         [0031]      FIG. 4  is an illustration of exemplary system  400  adapted according to one embodiment of the invention for providing a delayed signal and calibrating the delay mechanism. System  400  includes system  100  with associated components for calibrating the delay provided to the signal. Calibration delay  401  corresponds to Point  0  of  FIG. 3 , calibration delay  402  corresponds to Point A, and calibration delay  403  corresponds to Point B. Each calibration delay  401 - 403 , feeds into an associated phase detector  411 - 413 . Output from phase detectors  411 - 413  goes to a control unit. In this example, phase detectors  411 - 413  are rising-edge flip-flops, though other embodiments may use different techniques, such as employing falling-edge flip-flops. The control unit (not shown) in this embodiment is the same control unit that controls system  101 . 
         [0032]    In system  400 , calibration is performed as follows. First, output unit  103  selects the signal from variable delay  101 , which is at or near its minimum. With each successive cycle, the delay is stepped up until phase detector  41   1  returns a zero. The zero indicates that the delay in the output signal and the delay from component  401  are the same. Similarly, a zero at phase detector  412  indicates that the delay in the signal is the same as that from component  402 , and a zero at phase detector  413  indicates that the delay in the signal is the same as that from component  403 . After the calibration tests are performed, the control unit knows which control word inputs are associated with Points  0 , A, and B and controls system  100  accordingly. 
         [0033]      FIG. 5  is a signal timing diagram for the operation of system  400 .  FIG. 5  shows one repetition of the trigger signal. The outputs of phase comparators  411 - 413  are read by the control unit after Point B plus a small amount of propagation delay (for a more accurate reading) and before the next repetition. In some embodiments, this period represents the valid phase detector window. 
         [0034]    In order to find the proper calibration settings of the trigger delay mechanism, the following procedure is used by system  400 : 
         [0035]    1. Set the control word to the minimum delay setting with fixed delay  102  ( FIG. 4 ) switched out or not inserted. The output from phase detector  411  will be high during the valid phase detector window because the rising edge of the output of system  100  appears at an input to phase comparator  411  before the output from calibration unit  401  (clock input to the flip-flop). 
         [0036]    2. Increment the control delay word once per signal cycle until the output read from phase detector  41   1  is low. At this control delay word value (called “delay zero”), the delay in system  100  matches the delay in calibration unit  401 . 
         [0037]    3. Repeat steps 1 and 2 for phase detector  412  also with fixed delay  102  switched out. The resulting control delay word can be called “delay A.” 
         [0038]    4. Repeat steps 1 and 2 for phase detector  412  with fixed delay  102  switched in. The resulting control delay word can be called “delay A prime.” 
         [0039]    5. Repeat steps 1 and 2 for phase detector  413  with fixed delay  102  switched in. The resulting control delay word can be called “delay B.” 
         [0040]    The control unit then uses these delay word values to increment the delay substantially linearly (i.e., at least 95% linear) and monotonically from the beginning to the end of the end of the observation window. The control delay word is incremented linearly from delay  0  to delay A without fixed delay  102  (delay window  1 ) and then from delay A prime to delay B with fixed delay  102  (delay window  2 ). Since the effective delay of the values “delay A” and “delay A prime” are equal, the control unit can calibrate before and after switching in fixed delay  102  while eliminating much non-linearity and discontinuity. 
         [0041]    Systems such as system  100  (FIG.  1 } and system  200  ( FIG. 2 ) can be used in a variety of applications. For instance, the ramping delay provided by various embodiments can be adapted for use in systems that perform equivalent time sampling. Thus, in one embodiment, a radar system can use the trigger signal (input to system  100 ) as a transmit trigger and use the delayed trigger (output from system  100 ) as a receive trigger. The linearly increasing delay in the receive trigger can be used to capture successive portions of the returned signal waveform. The observation window discussed above can be used as the radar observation window. 
         [0042]    A radar system adapted according to one embodiment of the invention is shown in  FIG. 6 , which is a simple schematic. System  600  includes trigger mechanism  601 , Radio Frequency (RF) module  602 , antenna  603 , and signal processing unit  604 . Trigger mechanism  601  in this example provides triggers  611  and  612 , with trigger  612  being a delayed version of trigger  611 . Trigger mechanism  601  can be implemented in a variety of ways, including as system  100  ( FIG. 1 ) or as system  400  ( FIG. 4 ) with associated control mechanisms. RF module  602  receives triggers  611  and  612  and performs the transmitting and receiving operations via antenna  603 . While one antenna is shown, it should be noted that any number of antennas may be used and that separate antenna arrangements for transmitting and receiving may be employed by some embodiments. Returned signals are analyzed by processing unit  604  to provide output to a user or to another application. For example, processing unit  604  may analyze the signal using equivalent time sampling facilitated by the delayed trigger arrangement. A reconstructed waveform can then be used to provide data to a user or application. 
         [0043]    In addition to finding utility in radar applications, various embodiments of the invention can be used in numerous applications. Any application that uses delayed signals to capture waveforms can potentially benefit, including signal analyzers in physics laboratories, microchip testers, and the like. 
         [0044]      FIG. 7  is an illustration of exemplary method  700  for calibrating a signal, adapted according to one embodiment of the invention. Method  700  may be performed, for example, by a calibration system, such as system  400  ( FIG. 4 ) with an associated control unit. In one example, the control unit executes machine readable code in the form of software and/or firmware to perform the operations. 
         [0045]    In step  701 , a first signal is received, the first signal including a delay from a variable delay unit. In one example, the variable delay unit is a semiconductor-based delay line that experiences drift with operating temperature. However, method  700  can be adapted for use with any kind of variable delay unit, regardless of the type of drift that it experiences. 
         [0046]    In step  702 , a second signal is received, the second signal including a delay from a known and fixed delay source. For example, the delay produced by cut coaxial cables can serve as a known and fixed delay. Further, the second delay is real, as it is actually applied to the second signal. In this example, the second delay is independent of the factors causing drift in the variable delay unit. For example, if the variable delay unit is a semiconductor device that drifts with temperature, the second delay may be provided by a component that is substantially temperature-independent, such as a wire-based component. 
         [0047]    In step  703 , the first and second signals are compared. The comparing can be performed, for example, by any of phase comparators  411 - 413  ( FIG. 4 ). Further, the comparing may be performed over multiple cycles of the first signal with increasing or decreasing delay from the variable delay unit. Such comparing is described above with regard to  FIG. 4 . Step  703  may also include saving a parameter (such as an associated data control word) indicating when the delays of the first and second signals match. 
         [0048]    In step  704 , the variable delay unit is controlled to output the first delay substantially the same as the second delay in response to the comparing. For example, the first delay is calibrated so that it matches the known delay, at least at one delay point. 
         [0049]    In step  705 , the first signal with the controlled first delay is provided to a triggered system along with another signal without the first delay. For example, the two signals can be provided to a radar system with the delayed signal used as a receive trigger and the other signal used as a transmit trigger to perform equivalent time sampling. (Although it should be noted that it is possible to use a delayed trigger as a transmit signal and another non-delayed signal as a receive signal.) 
         [0050]    Method  700  is shown as a series of discrete steps; however, various embodiments may add, omit, rearrange, or modify some steps. For example, steps  701 - 704  can be repeated for a plurality of calibration delays. For example  FIG. 4  illustrates an embodiment with three calibration delays, and various embodiments are scalable for any number of calibration delays. Moreover, calibration can be performed at any of a variety of times during the operation of the system. It can be performed after a specified number of signal cycles, after a specified amount of time has passed, after an operating temperature change, and/or the like. Further, various embodiments are scalable for any number of delayed triggers, and each trigger can be calibrated for a number of delay points. 
         [0051]      FIG. 8  is an illustration of exemplary method  800  for providing a delayed signal to a radar system, such as in system  600  ( FIG. 6 ). Method  800  may be performed, for example, in a radar system, such as system  600 . In one example, a control unit in radar system  600  executes machine readable code in the form of software and/or firmware to perform the operations. 
         [0052]    In step  801 , a trigger signal is received in a variable delay unit that applies a variable delay thereto to produce a first output signal. For example, the delay can be increased or decreased with successive cycles of the trigger signal so that the variable delay unit adds a changing delay to the trigger signal. An example of a variable delay is delay  101  of  FIG. 1 . 
         [0053]    In step  802 , the output of the variable delay unit is received by a coarse delay unit that adds a coarse delay thereto to produce a second output signal. Thus, the second output signal adds another delay to the first output signal. In some embodiments, the coarse delay may be a fixed delay, such as a coaxial cable, though other embodiments are not necessarily limited thereto. 
         [0054]    In step  803 , one of the first and second output signals are selectively output to produce a third output, the third output having a delay range from a reference zero to a delay equal to a defined maximum variable delay plus the fixed delay. A diagram of an example delay is shown in  FIG. 2 , with the variable delay acting as a fine delay in addition to the coarse delay. The selective outputting can be performed, for example, by a multiplexor, as shown in  FIG. 1 . In some embodiments, control input is used to select the output of the switching device so that the output is substantially linear over the entire delay range. 
         [0055]    In step  804 , the third signal and the trigger signal are applied in a radar system to perform equivalent time sampling on a received waveform. For example, the trigger signal can be used as a transmit trigger, and the third signal can be used as a ramping-delay receive trigger to successively sample different parts of a waveform with each cycle of the trigger. 
         [0056]    Method  800  is shown as a series of discrete steps; however, various embodiments may add, omit, rearrange, or modify some steps. For example, steps  801 - 803  can be repeated over many cycles to produce two repeating triggers of a given frequency, with one trigger being increasingly delayed. Further, various embodiments are scalable for any number of delayed triggers. 
         [0057]    Embodiments of the present invention may provide one or more advantages over prior art systems. For example, it is generally easier to control systems  100  ( FIG. 1) and 400  ( FIG. 4 ) than to control prior art analog signal-summing circuits that relied upon potentiometers for tuning. Thus, some embodiments may be more efficient to operate when compared to prior art systems. 
         [0058]    Further, various embodiments of the invention are relatively independent of prior cycles. In prior art systems, such as systems that use analog signal summing circuits, the exact timing and the exact delay of the delay network is somewhat dependent on the length of time since the prior transmit to receive trigger pulse, mostly due to residual energy in associated capacitors and inductors. By contrast, many embodiments of the present invention eliminate much of the capacitance and inductance that causes prior event dependency in prior art systems. 
         [0059]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.