Abstract:
A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Description:
REFERENCES TO RELATED APPLICATIONS 
     This application is related to U.S. Pat. No. 5,706,424 filed Oct. 23, 1995 entitled &#34;System for fast read and verification of microcode RAM&#34; and also related to U.S. Pat. No. 5,737,567 filed Oct. 23, 1995 entitled &#34;Fast write initialization system for microcode RAM via data path array using pre-loaded flash memory and programmable control logic array&#34;. 
    
    
     REFERENCES TO RELATED APPLICATIONS 
     This application is related to U.S. Pat. No. 5,706,424 filed Oct. 23, 1995 entitled &#34;System for fast read and verification of microcode RAM&#34; and also related to U.S. Pat. No. 5,737,567 filed Oct. 23, 1995 entitled &#34;Fast write initialization system for microcode RAM via data path array using pre-loaded flash memory and programmable control logic array&#34;. 
     FIELD OF THE INVENTION 
     A system for enabling the maintenance subsystem of a computer network to rapidly read and verify data in main memory connected to the network. 
     BACKGROUND OF THE INVENTION 
     A simplified network illustrating a computing system is seen in FIG. 3A which shows the basic elements of a central processing module (CPM) 10, a Main Memory Module 40 and an Input/Output Module 50. These modules are interconnected via a dual system bus structure shown as having two system busses 22a and 22b. These busses are interchangeable system busses and provide parallel redundant transfer paths. 
     The network of FIG. 3A is seen enhanced with the addition of a Maintenance Subsystem Module 60 which is shown in FIG. 3B. The Maintenance Subsystem Module 60 provides both diagnostic functions to all of the modules in the network but is also required to &#34;initialize&#34; all the system modules and to &#34;start-up&#34; the system for operation. In FIG. 3B, the Maintenance Subsystem 60 is shown connecting to all of the system modules by means of a dashed line series of connections 64a, 64b and 64c. These connections represent the basic maintenance connections of a JTAG integrity system such as is specified in IEEE 1149.1. The IEEE 1149.1 specification is an industry standardized type of interface which provides a bit-serial data transfer between the various targeted modules of the network and the Maintenance Subsystem 60. 
     All the various system modules in the network are setup or &#34;initialized&#34; for system operation through the bit-serial interface lines 64a, 64b, and 64c. This type of interface is a system compromise between cost and performance. It is inexpensive cost-wise since it is standard and only uses a few wires but slow in performance since it is a bit-serial data transfer operation. 
     However, the bit-serial aspect of data transfer also makes it a an especially slow operation when massive amounts of information must be transferred. In many systems this is tolerable because the system initialization does not require an excessive amount of data transfer to most of the interconnecting modules in a network. 
     In the architecture of FIG. 3B, the case is presented where inordinate and significant time periods are lost when initialization is effectuated by only using the standard JTAG interface, 60si, especially when it is desired to transfer &#34;channel microcode&#34; instructions for the I/O module 50. 
     One type of central processing module 10 (CPM) is shown in FIG. 2 connected to a Maintenance Subsystem 60. The Maintenance Subsystem 60 is seen to have a maintenance processor 64 with several peripheral units attached, such as cartridge tapes 61, hard disk 62, and floppy disk 63. These devices can be used to provide the large database information that may be necessary to set-up the system for operation. The serial interface between the Maintenance Subsystem 60 and the central processing module 10 is shown on serial interface line 60si which connects the maintenance processor 64 from the maintenance subsystem 60 over to the maintenance controller 12 of the CPM module 10. 
     Also seen in FIG. 2 are the major elements of the processor logic in the CPM 10. These include the processor 14, the Data Path Array 20, the Control PAL 16 and the microcode RAM 18 which holds the instruction codes for the processor 14. It will be seen that the processor 14 can access the major system modules 40 and 50 via the system busses 22a and 22b through the on-card Data Path Array 20. The data path array converts from the on-card high speed processor bus 14b over to the slower inter-module system busses 22a and 22b. The soft, flexible Control PALs 16 is used to provide control of these system busses and also the data path array operations. 
     In FIG. 2, the dashed lines are used to show the on-card versions of the serial JTAG connections which are indicated as 12p, 12c and 12d. Once initialization of a system has been completed in FIG. 2, these JTAG connection lines are no longer essentially used. 
     Another view of the computer network is illustrated in FIG. 3C where the Input/Output Module 50 is seen to have a dedicated unit for channel adapters 50ca and in which the main system memory module 40 is seen to have a dedicated section 40cm for holding the channel microcode words. The Input/Output Modules 50 connect to various peripherals 70 and are under control of the channel adapters 50ca which provide the appropriate protocol and timing for communication purposes. 
     The channel microcode area 40cm in main memory 40 of FIG. 3C is a dedicated repository for channel microcode instructions which enables the channel adapters 50ca of the Input/Output Module 50 to control and communicate data transfers between I/O module 50 and various types of peripherals 70. 
     For efficiency of design and of production, it is most desirable to make as few types of unique hardware units as possible, that is to say, it is optimum to use identical hardware to accomplish many different tasks. Thus, the I/O module 50, although it must interface with many different types of peripheral devices 70 (for example, SCSI disks, tapes, printers and etc.) may optimally use identical or very similar hardware to accomplish this. Each I/O device interface is accomplished via a Channel Adapter 50ca. These channel adapters which are used are essentially identical hardware. Then to allow each adapter to properly interface to the different interface and device protocols, requires a unique &#34;driver&#34; software using the &#34;channel microcode&#34; to run each of the channel adapters 50ca. 
     At the original system initialization period, the Maintenance Subsystem 60 is sensitive to the system I/O device configurations and connections. Because of this, it must load the appropriate &#34;channel microcode&#34; into the appropriate locations in Main Memory 40, shown as repository 40cm in FIG. 3C. When the I/O module 50 is initialized and running, it will then access the appropriate &#34;channel microcode&#34; for each peripheral device, from the unit 40cm of the main system memory 40, and then bring this into the channel adapters 50ca for normal system operation. 
     The power of having &#34;soft&#34; microcode routines is that somewhat standardized I/O hardware can be used to implement numerous types and various types of I/O device connectivity. This flexibility comes at the cost of having to load up (Write) the channel microcode into the dedicated channel microcode repository 40cm of Main Memory 40. This must be done each time that the system is initialized. 
     Such systems as indicated in FIG. 3C are essentially known for loading the channel microcode since it was done through the JTAG bus 64 which has various sub-bus lines 64a, 64b, and 64c. The presently described system in FIG. 1 will be seen to operate a verification function to eliminate the long time periods necessary to read and transfer data from the channel microcode repository 40 cm  back to a maintenance controller 12 which has a flash memory 15 holding the original channel microcode data which can be used to verify the channel microcode data which has been read back from the main memory 40. 
     Earlier architectures and systems were very inefficient in regard to the loading of channel microcode into main memory. If the logic and architecture were implemented only as shown in FIGS. 2 and 3C, then it would still be possible to provide for the necessary writing of channel microcode into Main Memory 40. But, however, there would be a quite significant delay, even to the extent of several minutes, each individual time that the system was initialized and each time that there as a readback and verification. Thus, in the systems of FIG. 2 and FIG. 3C, it could be remarked that there were two levels of inefficiency (i) (ii) in regard to the loading up and writing in of channel microcode into the Main Memory Module 40 after which the readback verification cycle could be executed. 
     (i) Transfer Path from Disk or Tape to Main Memory 
     The first undesirable inefficiency in the loading of channel microcode into the dedicated section 40cm of FIG. 3C would involve the source of the microcode data to be loaded. The source of the microcode data will be seen from FIG. 2 and FIG. 3C as originating from the cartridge tape 61 or from one of the disks 62, 63 which connect directly to the Maintenance Processor 64. Normally, unless a new release of microcode data words were being loaded, the source would normally and logically be the hard disk 62. However, it should be noted that every byte of the channel microcode data would have to be transferred over the serial interfaces 64a, 64b, and 64c, between the Maintenance Subsystem 60 and the various system modules 40 and 50. Then on readback of the channel microcode in Main Memory 40 there would be a slow transfer of data on JTAG line 12 d  to Maintenance Controller 12 then via serial interface line 60 si  to the Maintenance Processor 64 for verification of the channel microcode. 
     The protocol involved on the serial interface 60 si  of FIG. 2 and 3C is not feasible for allowing &#34;bursts&#34; of data transfer but instead requires several detailed actions of protocol operations for &#34;each byte&#34; of data transferred. For ordinary diagnostic operations, this seeming inefficient serial transfer method is normally sufficient. However, in network situations where there are large or massive amounts of channel microcode data which must be loaded, then read back and verified by the Maintenance Subsystem 60 each time the system is initialized, then the overhead involved in the serial interface 60si for transferring the read-back data from memory for comparison with the original data in disk 62 is relatively very significant and very inefficient. 
     (ii) Channel Microcode Read and Verify Loop (FIG. 2) 
     The second inefficiency of the earlier art seen in FIG. 2 and 3C is that the standard JTAG interface 12si (12p, 12d, 12c) used in the central processing module 10 (CPM) involves connections for all of the on-card components of CPM 10 to the maintenance controller 12 (FIG. 2). Again, for ordinary and standard diagnostics of the central processing module 10, this bit-serial interface 12si is useful and relatively cost effective. However, for loading of the channel microcode data from the Maintenance Subsystem 60 into the Main Memory 40 via the JTAG bit-serial connection via bus 60si and the JTAG bus 12d, it is apparent that the slowness of this transfer operation would be unwanted and often unacceptable. This slowness of transfer is further compounded on read-back of the main memory channel microcode back to the Maintenance Controller 12 which then conveys the read-back data to the Maintenance Processor 64 for comparison with the original microcode data in disk 62 or disk 63. 
     Thus, by using only the JTAG serial connections 12p, 12c and 12d, it is still possible to write into the dedicated channel microcode area 40cm in the Main Memory 40 and then read back the channel microcode for verification by the Maintenance Processor 64. However, this procedure would require a complex protocol with separate items to be shifted by the Maintenance Subsystem 60 according to the series of steps (a)-(f) indicated hereinbelow using the FIG. 2 configuration. 
     (a) The maintenance processor 64 (FIG. 2) shifts the main memory address value into the Data Path Array 20 by using the serial interface 60si and the JTAG bus 12d. 
     (b) The maintenance processor 64 will shift the appropriate control states via 12c into the control PAL 16 in order to cause a system bus Read operation to occur on busses 22 a , 22 b  from the main memory 40. 
     (c) It may be noted that the above step (b) actually requires several steps to sequence through the appropriate bus protocol steps. 
     (d) The maintenance processor 64 will signal the data path array 20 and cause the channel microcode word which had been read from main memory 40, out of the data path array 20 and over the JTAG path 12 d  through the maintenance controller 12 and the serial interface 60 si  over to the maintenance processor 64. 
     (e) Maintenance software in the maintenance subsystem 60 will then check and verify each channel microcode word that had been read out from memory 40, against the data base held in the hard disk 62 of the maintenance subsystem 60. 
     (f) Then there is required a repetition of steps (a) through (e) for each one of the channel microcode words which were read out from the main memory 40, and passed on to the data path 20 and transferred on line 12 d  through the maintenance controller 12 and the serial interface 16 si  through to the maintenance processor 64 so that each word can be verified against data in the hard disk 62. 
     The above steps (a) through (f) will be seen to entail many bit serial shifts of some very long flip-flop shift chains, in some cases involving over 2,000 flip-flops. Thus, with the above cumbersome procedure, controlled by the maintenance software running in maintenance processor 64, it is possible to read each channel microcode word from the main memory 40 and pass it over to the maintenance processor 64 for verification, but this reading and verification process will be very slow, possibly on the order of several long minutes. However, as will be indicated later, the improved and enhanced system and method disclosed herein will enable a much faster Read and verify of the channel microcode at virtually no additional hardware cost. 
     Thus, it is an object of the present system to overcome the long transfer times characteristic of the earlier systems and provide for a rapidly efficient read and verification of data from main memory in a rapid fashion which does not entail long waiting periods. 
     SUMMARY OF THE INVENTION 
     A computer network utilizes a Central Processing Module which is connected to a maintenance subsystem on one end and has dual system busses which connect to a main memory and I/O module at the other end. The I/O module has channel adaptors for communicating with various types of peripheral units. However, in order to operate, the I/O module must access channel microcode routines from the main memory module. The main memory module must be loaded with the channel microcode during the initialization period and further, the channel microcode must be read back and verified as to its accuracy before actual operations begin. Earlier systems took relatively long periods of time to read out the channel microcode from main memory and pass it back to a maintenance subsystem so that each word of channel microcode could be verified as being accurate. 
     The present system provides a maintenance controller and specialized transfer bus connected to a data path array which is controlled by a programmable array controller so that rapid transfer of channel microcode data from main memory can be passed though the data path array on to a maintenance controller through the transfer bus whereupon the maintenance controller has a pre-loaded flash memory holding the original microcode data which can then be used to check out and verify each word of the channel microcode which had been placed in the main memory. Thus, there is no need for the verification cycle to be slowed down and delayed by having to use the slow serial interface to the maintenance subsystem. The maintenance controller, specialized transfer bus and the programmable array controller provide an emulation of the high speed transfer operations of the central processor, its processor bus and its microcode cache thus enabling a high speed operation of data transfer comparable to the high speed processor bus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a drawing of the enhanced network for reading out microcode from main memory and transferring it to a maintenance controller for verification of accuracy in a rapid fashion; 
     FIG. 2 is a network diagram of an earlier architecture which used slow bit-serial transfers and JTAG transfer lines for transferring data; 
     FIG. 3A is a generalized block diagram of a basic computer network connected to dual system busses; 
     FIG. 3B is a block diagram of a basic computer network using a maintenance subsystem connected to the computer network by slow bit-serial data transfer and control lines; 
     FIG. 3C is a diagram of a computer network with a maintenance subsystem and indicating the dedicated section in main memory for channel microcode and also the use of channel adaptors in the input/output module; 
     FIG. 4 is a schematic diagram showing the sequence of operations for reading out a word of channel microcode data and transferring this data to the maintenance controller for verification; 
     FIG. 5 is a timing diagram showing the signals involving the direct interface protocol and the new control sequences for providing fast read-out from main memory of channel microcode data for subsequent verification by the maintenance controller. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     FIG. 1 shows the enhanced system for the fast read-out of channel microcode from main memory 40 through the data path array 20 over the transfer bus 12 b  to the maintenance controller 12 which uses its pre-loaded flash memory 15 to check the microcode words read out from main memory 40. The network, seen in FIG. 1, indicates a maintenance subsystem 60 connected to Central Processing Module 10 through a serial interface 60 si . The Central Processing Module 10 is connected through a data path array 20 using dual system busses 22a and 22b to a main memory 40 and an input/output module 50. The main memory 40 has a dedicated repository 40 cm  for holding the channel microcode which is used by the channel adaptors 50 ca  in the I/O module 50 for communicating to specialized peripheral devices which require specialized instructions and protocol provided by the channel microcode. 
     The Central Processing Module 10 has a maintenance controller 12 which communicates with the maintenance sub-system 60 in order to allow the pre-loading of microcode data from the maintenance subsystem 60 over to a flash memory 15, which then can make the channel microcode data readily available for distribution without the need to wait for transmission from the maintenance system via the slow serial interface 60 si . A data path array 20 uses a processor bus 14 b  to communicate with the processor 14 and the microcode RAM 18. A programmable array logic controller designated Control PAL 16 provides control signals to the processor 14, the microcode RAM 18 and the data path array 20 for the handling of data transfers. 
     In the enhanced system of FIG. 1, the maintenance controller 12 provides a high speed, high capacity transfer bus 12b between the maintenance controller and the data path array 20 in addition to providing two control channels 12 c  1 to the Control PAL 16 and 12 c  2 to the data path array 20. The diagnostic JTAG lines 12 p , 12 c  and 12 d  are only used for diagnostic purposes and are no longer needed for transfer of microcode data words as was done in the earlier architecture. 
     The flash memory storage RAM 15 is a non-volatile unit which allows for a pre-loaded method of storing microcode data within the Central Processing Module itself, so that it is not necessary to wait for subsequent loading from the maintenance subsystem or for the transfer of read- back data to the maintenance processor 64 for verification. The flash memory 15 provides a large capacity on-card storage facility for the maintenance controller 12 within the Central Processing Module 10. 
     Under normal conditions with the improved system of FIG. 1, the maintenance subsystem 60 will pre-load channel microcode into the flash memory RAM 15. Then on system initialization, the channel microcode will be transferred from the database stored within the flash memory RAM 15 and passed over transfer bus 12 b  to the data path array 20 after which it can be loaded onto one or other of the system busses 22 a  or 22 b  for deposit in the main memory repository section 40 cm  dedicated to channel microcode. This is accomplished with control signals provided by the programmable array logic Control PAL 16. 
     The transfer path 12b is very fast when compared to the serial path 60 si  and the JTAG path 12 d  as was previously used and shown in FIG. 2. Only when there is a &#34;new set&#34; of channel microcode words being added to the system, does the channel microcode data base require transfer over the serial interface 60 si  from the tape cartridge 61 or the hard disk 62. Further, at this time, the flash memory RAM 15 will be updated with a new data base for the new channel microcode items. 
     Enhanced Channel Microcode Read Loop 
     As seen in FIG. 1, there has been added two new direct sets of control lines 12 c  1 and 12 c  2 in addition to a new direct transfer bus  12   b  from the maintenance controller 12 to the data path array 20 in order to provide for a channel microcode read loop. This enhanced loop then allows the maintenance controller 12 to utilize the fast wide parallel paths of bus 12 b  through the data path array 20 and over to the main memory 40 via the system busses 22 a  and 22 b , rather than having to use the previous slow, serial JTAG path 12 d  and the JTAG control lines 12 d  and 12 c . These new direct lines allow the maintenance controller 12 to emulate the actions that the processor 14 would normally have to take if it were reading out data from the main memory 40. 
     Data Path Array (FIG. 1) 
     The data path array 20 of FIG. 1 provides the connection between the processor bus 14 b  on one side and the system busses 22 a  and 22 b  on the other side. The data path array has a path for addresses and a path for data information which can then be read out from the main memory 40 via the system busses 22 a  and 22 b . This is done under direction of the Control PAL 16 using the control lines 16 c . The data path array 20 will be seen to have an address register 20 a  and a data register 20 d  for temporarily holding addresses and data read out from main memory destined for subsequent transfer to the maintenance controller 12 for verification. 
     Under the earlier art, for each word read out from main memory and placed in the data path array 20, the values for the address data and the microcode channel data had to be shifted serially by means of the JTAG path 12 d  into the boundary scan area 20 s  of the data path array. After this, and under the control of the programmable array logic Control PAL 16, the addresses and data in the data path array 20 could be transferred to the maintenance controller 12 and then transferred on the slow serial interface 60 si  to the maintenance processor 64 for verification. 
     In the enhanced configuration of FIG. 1, there is provided the additional parallel transfer bus path 12 b  onto the data path array 20 from the maintenance controller 12. Further, the new direct interface connections include four control signals on lines 12 c  1 and six control signals on lines 12 c  2, plus the 16-bit data transfer bus 12 b  (MP --  DATA). By using the 16-bit direct transfer bus 12 b , this permits the necessary wider fields (addresses equal 32 bits; data equals 52 bits) to be much more quickly built up from the data path array 20 than could possibly have been done using the earlier serial JTAG shifting method. The signals involved in the new direct interface are described below in Table I. 
     
                       TABLE I______________________________________MP.sub.-- LADDB         Signal from the Maintenance         Controller 12 causing the current         value on the MP.sub.-- DATA bus 12b to be         loaded into the selected upper portion         of the data path array address         register, 20a.MP.sub.-- STRDATLB         Signal from the Maintenance         Controller 12 causing the current         value on the MP.sub.-- DATA bus to be loaded         into the selected lower portion of the         Data Path Array data register, 20d.         (Not used for reading data).MP.sub.-- STRDATUB         Signal from the Maintenance         Controller 12 causing the current         value on the MP.sub.-- DATA bus 12b to be         loaded into the selected upper portion         of the Data Path Array data register.         (Not used for reading data).MP.sub.-- REGSEL(1:0)         Two signals from the Maintenance         Controller 12 used to select which         half of the address register is to be         loaded or which portion of the data         register in the Data Path Array is to         be loaded or read.MP.sub.-- ADDINCB         Signal from the Maintenance         Controller 12 causing the value in the         Data Path Array address register 12a         to be incremented by one.______________________________________ Note signals ending in &#34;B&#34; are active low. 
    
     Thus, the direct interface while minimal as to hardware impact, is quite significant as to providing enhancement of the read channel microcode loop. The address value need only be issued once by the maintenance controller 12 by thereafter can be easily and quickly incremented to the next address value by the Control PAL 16. Further, the data values read from the main memory 40 as channel microcode values can be easily steered to the maintenance controller 12 in a fraction of the time and effort previously required. Further, and most significantly, the priorly required time for the maintenance software in the maintenance processor 64 to calculate the new address each time, has now been saved. Once the address is resident in the data path array 20, all that is necessary to emulate the processor paths to the main memory 40 in the system bus 22, is that the necessary high-speed control signals be activated as they would for normal processor operations. This is done by means of the maintenance controller 12 and the Control PAL 16 of FIG. 1. 
     Enhanced Mode--Control PAL 16 (FIG. 1) 
     The Control PAL 16 functions as a master logic unit which decodes processor commands and controls the steering of all data into and out of the data path array 20. The Control PAL 16 also provides all the control signals and timing required for the system bus operations to or from main memory 40. All bus traffic on the processor bus 14 b  is directed by signals from the Control PAL 16. The Control PAL 16 controls all actions at the faster and full clock speed of the processor 14. Further, all bus access and protocol for the system busses 22 a  and 22 b  operations is directed by signals from the Control PAL 16. Thus, all the necessary controls are already in place to read data over the system bus 22 from the main memory 40. The Control PAL 16 already has the required signals necessary to steer the address values in the data path array 20 onto the system busses 22 a  and 22 b . All control signals are already present to receive memory data into the data path array 20 from the system busses. Further, signals already exist for all system bus and main memory operations. The Control PAL 16 can function at the full processor speed rather than some slow, serial type operation as would be required on the JTAG lines 12 d  or 12 p  and 12 c . The normal control signals used by Control PAL 16 are shown below in Table II. 
     
                       TABLE II______________________________________SIGNALS FROM CONTROL PAL 16______________________________________NWB.sub.-- OUTB          Signal when active indicates that a          non-write type memory operation is          active. This signal initiates a          system bus access and system bus cycle          for non-write type (e.g. reads)          operation.BIU.sub.-- CMD(2:0)          Signals indicating the type of active          system operation; equals &#34;000&#34; for          system bus single word read          operations.DOUT.sub.-- MSEL(3:0)          Bus steering controls to the Data Path          Array. Controls what values are          driven onto the system busses.RDCMPLT        Signal indicating that the current          system bus operation has completed          successfully. For a Write operation,          this signal indicates that the Write          operation is totally complete. For a          Read operation, this signal indicates          the availability of the system Read          data with the Data Path Array          registers.G.sub.-- DRIVEB          Signal enabling Data Path Array to          drive out memory data onto processor          bus.G.sub.-- LDINB Signal causing data on the processor          bus to be strobed into input register          of the Data Path Array.G.sub.-- MSEL(3:0)          Signals controlling the steering of          data within the Data Path Array onto          the processor bus. For SA bus, =0000;          for SB bus =0100.______________________________________ 
    
     It should be noted that each of these signals were previously used in the earlier architecture in the Control PAL 16. What the present improved system does for enhancement is to add a simple, direct way by which the maintenance controller 12 can initiate and cause the sequences that normally control these signals of Table III to be executed. In effect, the new direct controls of the maintenance controller 12 simply do a &#34;logic-OR&#34; into the existing control logic for these signals. 
     The control signals shown in Table III are used in logic equations which effectuate the functioning of this system. These new logic equations are also shown in Table III below. The newly added maintenance controller terms are denoted. From these equations in Table I and II, it can be seen that very little new logic needed to be added to the existing control terminology in order to provide the fast read path. 
     
                       TABLE III______________________________________LOGIC EQUATION       DESCRIPTION______________________________________NWB.sub.-- OUTB= RDMISSFF/* RDLKDLYFF/                normal logic* (MPFF3 * MP.sub.-- WRB)/                maintenance controller termBIU.sub.-- CMD(2) = SNDMSGFF*RTODFF/    normal logic+ WB.sub.-- OUT      normal logic+ READLKFF           normal logicBIU.sub.-- CMD(1) = WB.sub.-- OUT       normal logic+ READLKFF           normal logic+ RDMISSFF * READ4   normal logicBIU.sub.-- CMD(0) = SNDMSGFF * WB.sub.-- OUT/                normal logic+ RTODFF * WB.sub.-- OUT/                normal logic+ READLKFF * WB.sub.-- OUT/                normal logic+ RDMISSFF * WB.sub.-- OUT/ * READ4                normal logicDOUT.sub.-- MSEL(3,2) . . .               normal logic+ WRITE * MPFF3/     maintenance controller termDOUT.sub.-- MSEL(1) = . . .               normal logic+ MPFF3              normal logicDOUT.sub.-- MSEL(0) = . . .               normal logic+ MPFF3*(A.sub.-- CVOUTF+B.sub.-- CVOUTF)                maintenance controller termRDCMPLT := RDCMPLT/*SCMPLTFF*RDMISSFF                normal logic+ . . .              normal logic+ RDCMPLT/*SCMPLTFF*MPFF3                maintenance controller termG.sub.-- DRIVEB := BIUFF2 + MEMFF2 * RDMISSFF                normal logic+ . . .              normal logic+ MPFF2 * MP.sub.-- MEM.sub.-- OP                maintenance controller termG.sub.-- LDINB := . . . BIUOPFF + MEM.sub.-- OP                normal logic+ MPFF2 * MPFF3/     maintenance controller termG.sub.-- MSEL(3,1,0) := . . .                normal logicG.sub.-- MSEL (2)  := . . .                normal logic +MPFF2*MP.sub.-- MEMOP*B.sub.-- BUSACTIVEF                maintenance controller term______________________________________ Signals ending in &#34;B&#34; are active low Notes: := means to set a DFlip-flop + means logicalor / means logicalnot = means a gate (combinatorial) term * means logicaland . . . means more normal logic not shown 
    
     In addition to the new &#34;OR&#34; terms seen in Table III, a short, new sequence was provided to handle the protocol for the direct control from the maintenance controller 12. This new sequence was inserted into the Control PAL 16. This is described in the following section involving the new mode direct protocol. 
     Enhanced Mode--Direct Protocol 
     In order to provide the ability to emulate the usage of the high-speed wide bus structure 12 b  by the maintenance controller 12, a four-signal direct interface is made between the maintenance controller 12 and the Control PAL 16. This is seen in FIG. 1 by the control lines 12 c  1. The Control PAL 16 operates at the maximum clock rate which is the high speed of the processor 14. The maintenance controller 12 operates at a much slower clock rate and thus the new direct interface must provide for this asynchronous condition. This is accomplished by a hand-shaking arrangement. Of the four new signals in the direct interface, 12 c  1, only three are used for reading the channel microcode words from main memory. The signals involved are given in Table IV. 
     
                       TABLE IV______________________________________INTERFACE SIGNALS ON BUS 12c1 (FIG. 1)______________________________________MP.sub.-- WRB       (not used here).MP.sub.-- DONEB       Return handshake signal from the Control       PAL 16 indicating that the current operation       is now complete.MP.sub.-- RDB       Control signal from the Maintenance       Controller 12 indicating that the Control       PAL 16 should execute a read operation.MP.sub.-- MEMOP       Signal from the Maintenance Controller 12       indicating that the Control PAL 16 should       execute a system bus (Memory) type of       operation.______________________________________ 
    
     These are active low signals. 
     The incoming signal of MP --  RDB in Table IV is captured and synchronized to the processor clock rate with a flip-flop designated MPRDBFFB within the Control PAL 16. This flip-flop is then used in the control sequence. As seen in FIG. 1, three flip-flops 16f (FF1,2,3) which are internal to the Control PAL 16 are used to control the sequence of the protocol and the fast transfer bus 12b controls. These flip-flops are called MPFF1, MPFF2, MPFF3. 
     FIG. 4 is a schematic diagram showing the sequence of control operations from conditions A, B, C, and D. The Idle condition at (A) shows that each of the three control flip-flops are off. After this, the maintenance controller 12 initiates a read operation and memory operation in order to effectuate the results at (B). Here, the data path array 20 makes addresses available to the system bus and the Control PAL 16 selects a read operator and provides a Read operation on the system bus to access the main memory 40. When the read command is completed, the system at (C) shows that the Read operation has been completed over the system bus and that one word of channel microcode has been placed in the data path array 20. It is seen at (C) that while flips-flops 1 and 3 are &#34;off,&#34; the flip-flop 2 is turned &#34;on&#34;. Subsequently, at the status position (D), the flip-flops 1 and 2 are &#34;on,&#34; and flip-flop 3 is &#34;off&#34; in order to complete the handshake protocol to show that the cycle is finished and can return to the Idle position (A). 
     FIG. 5 is a timing diagram showing the timing of the protocol, the three sequence flip-flops, and the various normal control signals used in reading the channel microcode over the system bus from main memory through the data path array to the maintenance controller 12 for verification against the data in the flash memory 15. 
     FIG. 5 indicates how the processor path emulation sequence occurs in the fast reading of channel microcode. First, the maintenance controller 12 initiates a &#34;Read&#34; operation using the newly enhanced direct protocol signals, MP --  MEMOP and MP --  RDB, Table IV. With these signals, the maintenance controller 12 signals to the Control PAL 16 that a Read operation to memory is desired. These signals cause the third flip-flop MPFF3 of the enhanced control sequence to be set as shown in FIGS. 4 and 5. This control flip-flop then accomplishes most of the remaining effort to be accomplished. As was seen in the equations of Table III, the normal signal designated, NWB --  OUTB (line (i) of FIG. 5) is forced &#34;on&#34; by the third flip-flop MPFF3, line (f). Once the signal NWB --  OUTB is &#34;on&#34;, it automatically operates through all the normal Control PAL logic to cause a system bus operation to occur. This logic automatically does a memory read operation into main memory 40. The only special actions taken are that the signals &#34;DOUT --  MSEL (3:0)&#34;, line (k) for the steering of the maintenance port address (in the data path array 20) onto the system busses 22 a  and 22 b . 
     As with the normal control logic there is a delay or wait time while the slower system bus (22 a  and 22 b ) operation takes place. When this operation is complete, the signal RDCMPLT, line (m) is issued, which indicates the completion of the Read operation. This signal then terminates the enhanced control sequence and the enhanced direct protocol procedures. Thus, a full-speed, normal system bus Read operation occurs to main memory 40 on behalf of the maintenance controller for the reading out of channel microcode from memory and subsequent verification by the maintenance controller 12 using the flash memory RAM 15. 
     The new enhanced fast emulation path will be seen as being implemented with very little additional hardware cost. The new transfer bus 12b and the controls 12 c  1 and 12  c  2 into the data path array may take up 22 additional array connection pins. However, in most cases, these pins are already available and thus the change to the data path array is on a cost-free basis. Also, the extra silicon used internally within the data path array is there for the taking. In the case of the new enhanced direct interface protocol sequence and the extra &#34;OR&#34; terms, these are all built in the Control PAL 16 and this is completely implemented using the spare capacity within the existing programmable array logic 16 and thus no new hardware is added. The interconnections for the control signals and the transfer bus 12b, of course, do add a few more etch connections on the printed circuit board. However, the cost of these are actually almost negligible. 
     The herein described fast read and verification system with a enhanced path emulation enabling a large channel microcode data base to be quickly read out from the main memory and verified each time the system is initialized, will be seen to be a most efficient implementation and rapid transfer of information quite superior to the prior art usage. By using the existing high-speed, wide bus path and emulating the normal controls utilized by the high speed processor logic, the system allows the reading to be virtually invisible to the human operator. In the earlier architectural systems, the time to load, read and verify the channel microcode was measurable in long minutes and is now accomplished in a matter of a few seconds. 
     While the above-described enhanced system for fast read and verify of main memory has been described in a preferred embodiment, other embodiments may also utilize the concept which is defined in the following claims.