Abstract:
A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Description:
RELATED APPLICATION  
       [0001]    This is a continuation-in-part (CIP) application of application Ser. No. 09/723,957, filed Nov. 27, 2000, and entitled, “METHOD OF FABRICATING A HIGH-VOLTAGE TRANSISTOR”, which is assigned to the assignee of the present CIP application. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates to high voltage field-effect transistors. More specifically, the present invention relates to processes for fabricating high voltage field-effect transistor structures that include a high-voltage junction field-effect transistor.  
         BACKGROUND OF THE INVENTION  
         [0003]    It is conventional to construct a high-voltage, insulated-gate, field-effect transistor (HVFET) having a high breakdown voltage and a low “on-state” resistance. To accomplish this end, practitioners in the art have used an insulated gate field-effect transistor (IGFET) placed in series with a high-voltage junction field-effect transistor (JFET). Such a transistor is capable of switching at high voltages, has low values of on-state resistance, and has insulated-gate control. Moreover, the HVFET may advantageously be fabricated near low voltage logic transistors on a single integrated circuit chip to form what is commonly referred to as a power integrated circuit (PIC).  
           [0004]    Lateral HVFETs with a JFET conduction channel have been used in power conversion applications such as in AC/DC converters for offline power supplies. One goal in such devices is to produce a transistor having a high breakdown voltage (V bd ) using as small a surface area as possible. In order to achieve high breakdown voltage in these devices is necessary to accurately control the amount of charge in the JFET conduction channel(s) and also in each of the JFET gate layers. For this reason, it is desirable to fabricate such devices using a process that minimizes variance in the charge of each layer.  
           [0005]    It is also desirable to fabricate HVFETs that occupy as small a surface area as possible to realize a given on-state resistance. The figure of merit often used is known as specific on-resistance (R sp ), which is the product of on-state resistance and surface area. A lower R sp  allows a smaller area HVFET transistor to be used to meet the on-state resistance requirements of a given application, which reduces the area and, respectively, the cost of the PIC. One way of reducing the on resistance of a HVFET is to incorporate multiple JFET conduction channels into the transistor device.  
           [0006]    Another goal in the art is to provide a highly manufacturable HVFET design that consistently delivers the required combination of V bd  and R sp  over a range of normal process variances. To realize this goal, the manufacturing process should introduce minimal variance in the critical device parameters, and the HVFET should exhibit minimal sensitivity to process variations.  
           [0007]    To try to achieve the aforementioned goals, researchers and engineers have experimented with a variety of different structures and processing methods. For example, U.S. Pat. Nos. 5,146,298 and 5,313,082 both describe a method of fabricating an HVFET with multiple JFET conduction channels. The &#39;082 patent teaches a HVFET in which two JFET channels are arranged in parallel to increase charge and reduce R sp . A triple diffusion process is disclosed, in which three separate implant and diffusion steps are required to form a HVFET (see FIG. 1 of the &#39;082 patent) that includes N-type top layer  28 , P-layer  27 , and N-type extended drain region  26 . The multiple layers of alternating conductivity types is fabricated by implanting, and then diffusing, dopants into the semiconductor substrate. That is, according to the &#39;082 patent, the N-well region, the P-type buried region, and the N-type extended drain region are all diffused from the surface.  
           [0008]    One shortcoming of this prior art approach is that each successive layer is required to have a surface concentration that is higher than the preceding layer, in order to fully compensate and change the conductivity type of the corresponding region. Diffusion of dopants from the surface makes it very difficult to maintain adequate charge balance among the layers. In addition, the heavily doped p-n junction between the buried layer and drain diffusion region degrades the V bd  of the device. The concentrations also tend to degrade the mobility of free carriers in each layer, thereby compromising the on-resistance of the HVFET. As a result of these difficulties, this method of manufacture is generally limited to producing HVFET devices having no more than two JFET conduction channels.  
           [0009]    Another method of fabricating an HVFET with multiple JFET conduction channels is disclosed in U.S. Pat. No. 4,754,310. The &#39;310 patent teaches a method of construction that consists of epitaxially depositing material of alternating conductivity types and then forming V-shaped grooves to contact the resulting plurality of layers. This method suffers, however, from the high costs associated with multiple epitaxial deposition processing steps and the formation of the grooves. Furthermore, it is difficult to precisely control the charge in each layer formed by epitaxially deposition. As noted previously, proper charge control is crucial to achieving a device that is characterized by a consistently high breakdown voltage.  
           [0010]    A similar method of fabricating an HVFET with multiple JFET conduction channels is described in an article by Fujihira entitled, “Theory of Semiconductor Superjunction Devices,” Jpn. J. Appl. Phys., Vol. 36, pp. 6254-6262 (October 1997). Fujihira also teaches the technique of epitaxial growth and the formation of grooves to fabricate the HVFET. This method suffers from the same charge control problems and high manufacturing cost discussed above.  
           [0011]    Yet another method of fabricating an HVFET with multiple JFET conduction channels is disclosed in U.S. patent application Ser. No. 09/245,029, filed Feb. 5, 1999, of Rumennik, et. al., which application is assigned to the assignee of the present application. Rumennik teaches the use of multiple high-energy implants through the surface of the semiconductor substrate to form a plurality of buried layers. One drawback of this approach, however, is that the number and maximum depth of the buried layers is limited by the available implantation energy. For example, the maximum boron implantation energy available from a typical high-energy implanter is about 7 MeV. Using the techniques disclosed in Rumennik, such an implanter would allow for the formation of four separate buried layers, providing five JFET conduction channels, with a corresponding specific on-resistance of about 6 ohm-mm 2 .  
           [0012]    By way of further background, U.S. Pat. No. 5,386,136 of Williams teaches a lightly doped drain (LDD) lateral MOSFET transistor having reduced peak electric fields at the gate edge. The peak electric field is reduced due to the presence of a P+ buried layer that pushes the electrical equipotential lines beneath the silicon surface laterally further and more evenly in the direction of the drain contact region. Yamanishi, et al. (JP404107877A) teaches construction of a P-buried layer in an extended drift region using processing technique of dopant segregation by thermal heating.  
           [0013]    Thus, there still exists a need for a reliable, economically efficient method of fabricating HVFETs with multiple JFET conduction channels that overcomes the problems associated with the prior art.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:  
         [0015]    FIGS.  1 A- 1 E are cross-sectional side views illustrating the fabrication of a high-voltage, field-effect transistor (HVFET) device structure in accordance with one embodiment of the present invention.  
         [0016]    [0016]FIG. 2 is a cross-sectional side view of a HVFET fabricated according to an alternative embodiment of the present invention.  
         [0017]    [0017]FIG. 3 is a cross-sectional side view of a HVFET fabricated according to another alternative embodiment of the present invention.  
         [0018]    [0018]FIG. 4 is a cross-sectional side view of a HVFET fabricated according to yet another alternative embodiment of the present invention.  
         [0019]    [0019]FIG. 5 is a cross-sectional side view of a HVFET fabricated according to still another alternative embodiment of the present invention.  
         [0020]    [0020]FIG. 6 is a cross-sectional side view of a HVFET fabricated according to a further alternative embodiment of the present invention.  
         [0021]    FIGS.  7 A- 7 E are cross-sectional side views illustrating the fabrication of a high-voltage, field-effect transistor (HVFET) device structure in accordance with still another alternative embodiment of the present invention.  
         [0022]    [0022]FIG. 8 is a cross-sectional side view of a HVFET fabricated according to another alternative embodiment of the present invention.  
         [0023]    [0023]FIG. 9 is a cross-sectional side view of a HVFET fabricated according to yet another alternative embodiment of the present invention.  
         [0024]    FIGS.  10 A- 10 G are cross-sectional side views illustrating the fabrication of a high-voltage, field-effect transistor (HVFET) device structure in accordance with another alternative embodiment of the present invention.  
         [0025]    [0025]FIG. 11 is a cross-sectional side view of a HVFET fabricated according to a further alternative embodiment of the present invention.  
         [0026]    [0026]FIG. 12 is a cross-sectional side view of a HVFET fabricated according to still another alternative embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0027]    In the following description, numerous specific details are set forth, such as material types, structures, particular processing steps, etc., in order to provide a thorough understanding of the present invention. Practitioners having ordinary skill in the semiconductor arts will understand that the invention may be practiced without many of these details. In other instances, well-known elements, techniques, and processing steps have not been described in detail to avoid obscuring the invention.  
         [0028]    The present invention relates to a method for fabricating a high-voltage field-effect transistor with multiple JFET conduction channels that provide a low on-state resistance for a given breakdown voltage. While n-channel HVFETs are presented herein for illustrative purposes, p-channel HVFETs can also be fabricated utilizing complementary processing techniques that appropriately reverse the conductivity types associated with the various regions and layers.  
         [0029]    Referring now to FIG. 1A, a cross-sectional view of an N-type substrate following formation of the buried regions  15 - 17  is shown. Substrate  10  comprises a top surface  18  and a bottom surface  19 . In the described embodiment, substrate  10  is uniformly doped N-type. The doping level is chosen to provide the required amount of charge in each of the JFET conduction channels of the final HVFET device. The JFET conduction channels comprise the N-type regions disposed between the P-type buried layers  15  in FIG. 1A. In accordance with the present invention, buried layers  15  and their associated JFET conduction channels are formed in a laterally extended region of the substrate that eventually will be part of the laterally extended drain of the completed HVFET.  
         [0030]    Practitioners in the art will appreciate that the laterally extended region may also comprise the high-voltage portion of another lateral power device. For example, high-power diodes, JFETs, LIGBTs, and so on may also be incorporated in the laterally extended region of the HVFET.  
         [0031]    In one embodiment, substrate  10  includes an etch-stop layer and/or cleave plane to facilitate control of the final thickness of this layer (after wafer bonding and etch-back, as will be described shortly below). It is appreciated that substrate  10  may comprise an epitaxial layer. In another embodiment, substrate region  10  may comprise an implanted and diffused N-well region formed in a uniformly doped P-type substrate material.  
         [0032]    The buried regions  15 - 17  of FIG. 1A are formed using conventional photolithography followed by implantation of a P-type dopant such as boron into substrate  10 . For example, masking layer members  11 ,  12 , and  13  are formed on top surface  18  and multiple implantation steps have been performed through top surface  18  (represented by arrows  14 ) to form the multiple P-type buried layers shown. The dose and energy for each of the ion implants is chosen to provide the required amount of charge in each of the buried layers  15 , and also in the corresponding JFET conduction channels. The N-type conduction channels around the P-type buried layers  15  provide paths for current to flow in the extended drain region of the HVFET.  
         [0033]    For a given implantation energy, the thickness of masking layer members  11 - 13  affects the penetration of the dopant into substrate  10 . As can be seen, both masking members  11  and  12  have a thickness t 1  that effectively prevents any dopant ions from penetrating into the substrate material. Conversely, where top surface  18  is exposed, the depth of individual buried layer regions  15  and  16  is determined according to the energy and dose of each implant step.  
         [0034]    Note that according to the embodiment shown, corresponding P-type buried layer regions  15  and  16  (labeled PB′) are formed simultaneously using the same implantation step. For instance, buried layer regions  15   a  &amp;  16   a  are formed at the same depth in substrate  10  utilizing the same implantation step. Similarly, buried layer region pairs  15   b  &amp;  16   b ,  15   c  &amp;  16   c , and  15   d  &amp;  16   d  are each formed using the identical implant processing step. The difference in vertical depth between the buried layer regions  15   a - d  and  16   a - d  relative to the top surface is due to differences in implant energy and dose associated with each of the multiple implantation steps. The exposed portions of surface  18  may also be covered with additional layers of material, such as oxide, to screen or block the implants.  
         [0035]    It should be understood that the PB′ buried layer regions  16  are optionally included in the process of the present invention. In other words, alternative embodiments may exclude these PB′ buried layer regions. In the embodiment represented by FIGS.  1 A- 1 E, buried layer regions  16  are formed an area beneath the substrate surface where the source region of the HVFET will be located.  
         [0036]    [0036]FIG. 1A also illustrates how a difference in thickness of the surface masking layer may be utilized to achieve buried layer regions  17  disposed at different depths within substrate  10  relative to corresponding regions  15  and  16 . In this case, masking layer member  13  is purposefully formed to have a thickness t 2  that is less than thickness t 1 . Thickness t 2  is chosen to cause buried layer regions  17   a - 17   d  (labeled PB″) to be formed at a slightly shallower, offset depth as compared to corresponding buried layer regions  16   a - 16   d . Masking layer members  11 - 13  may comprise oxide, nitride, photoresist, or any other suitable material.  
         [0037]    By appropriate selection of the thickness t 2  of masking member  13  and implant energy, the adjacently formed PB′ and PB″ buried layer regions will form a continuous region of P-type doping extending below surface  18  of substrate  10 . This continuous P-type region may be used to isolate the HVFET from other circuitry fabricated in the same substrate. This aspect of the invention will be discussed in more detail below.  
         [0038]    It should be understood that for this embodiment the PB″ buried layer regions  17   a - 17   d  may be formed using the same implantation steps used to form the corresponding PB′ buried layer regions  16   a - 16   d  (and also P-type buried layer regions  15   a - 15   d ).  
         [0039]    [0039]FIG. 1B is a cross-sectional view of substrate  10  after it has been flipped over and bonded to P-type substrate  20 . The bonding of top surface  18  to substrate  20  may be achieved by conventional wafer bonding techniques. During the wafer bonding process, a relatively low temperature is preferably maintained to avoid out-diffusion of the P-type buried layers  15 - 17 . Since the bonded interface between substrate  10  and substrate  20  will lie within the depletion region of the HVFET under reverse bias, the interface should ideally be free of traps, voids, and contamination.  
         [0040]    [0040]FIG. 1B also shows the device at a stage in the fabrication process after thinning of substrate  10 . According to the embodiment of FIG. 1B, thinning occurs from the top down, i.e., from surface  19  down toward surface  18 . After thinning, the new top surface of the device substrate is denoted by numeral  19 ′ in FIG. 1B. Thinning may be performed using any one of a variety of techniques, including conventional chemical etching, mechanical, or chemo-mechanical methods.  
         [0041]    In one embodiment, an etch stop layer or cleave plane is embedded within substrate  10  where surface  19 ′ is to be located, so as to provide good control over the final thickness of substrate  10 . As will be seen shortly, the final thickness of substrate  10  is important in establishing the spacing between buried layer region  15   d  and buried layer region  15   e , as formed in subsequent processing steps.  
         [0042]    [0042]FIG. 1C is a cross-sectional view of the device of FIG. 1B following formation of uppermost buried layer regions  15   e - 15   h ,  16   e - 16   h , and  17   e - 17   h . (Once again, it should be understood that buried layers  16  and  17  are optionally included in the embodiment shown.) Uppermost buried regions  15   e - 15   h ,  16   e - 16   h , and  17   e - 17   h  may be formed utilizing similar photolithography and ion implantation steps used to form the underlying buried layer regions  15   a - 15   d ,  16   a - 16   d , and  17   a - 17   d . In this example, an optional oxide layer  30  is first grown or deposited on surface  19 ′ of substrate  10 . Oxide layer  30  may become the field oxide of the final HVFET. Ideally, optional oxide layer  30  is produced using low temperature processing techniques to minimize out-diffusion of the previously formed buried layers. Another layer  32  may also be provided with the same thickness as layer  30 .  
         [0043]    Masking layer members  31 ,  34  and  35  are formed over surface  19 ′ and multiple implantation steps are performed (represented by arrows  37 ) to form the multiple, uppermost P-type buried layers and corresponding JFET conduction channels shown. The dose and energy of each implant is chosen to provide the required amount of charge in each of the uppermost P-type buried layers and also in the corresponding JFET conduction channels. The thickness of members  34  and  35  is chosen to completely block the implant.  
         [0044]    The thickness of layer  30  allows implant ions to penetrate to a certain depth in the substrate. Because buried layer regions  15   e - 15   h  and  16   d - 16   h  are each formed using the same implantations, the relatively thinner masking layer  31  produces a set of buried layer regions  16   d - 16   h  that are disposed more deeply within substrate  10 , as compared with the corresponding buried layer regions  15   d - 15   h , respectively. As shown, the relatively thinner masking layer  31  produces a buried layer region  16   e  that is merged with underlying buried layer region  16   d . In this embodiment, merging of regions  16   d  and  16   e  is important to establish a continuous P-type isolation region that extends from the source region down to substrate  20  in the completed device structure. This continuous P-type isolation region may be used to isolate the HVFET from other circuitry.  
         [0045]    The cross-sectional side view of FIG. 1C also shows the optional inclusion of P-type buried layer regions  17   e - 17   h  (labeled PB″) formed adjacent, and connected to, corresponding PB′ buried layer regions  16   e - 16   h . These PB″ buried layer regions are formed by the same implantation steps used to form the PB′ buried layer regions. In the example shown, a masking layer  32  having a thickness greater than that of layer  31  is formed on surface  19 ′ prior to the implantation steps. The greater thickness of masking layer  32  relative to layer  31  causes the respective buried layer regions  17   e - 17   h  to be formed at relatively shallower depths as compared to their counterpart buried layer regions  16   e - 16   h . Here again, appropriate selection of mask layer thickness&#39; and implantation energies causes the PB′ and PB″ buried layer regions to merge, thereby forming a continuous region of P-type doping that extends from just beneath surface  19 ′ down to substrate  20 .  
         [0046]    Once the extended drain region or drift region of the HVFET has been formed according to the preceding steps, the following fabrication steps may be utilized to complete the device.  
         [0047]    [0047]FIG. 1D illustrates a cross-sectional view of an insulated-gate HVFET after the formation of source region  42 , drain region  47 , and polysilicon gate  43 , which is insulated from substrate  10  by a thin gate oxide layer  44 . These structural features may be formed by conventional processing techniques.  
         [0048]    In the method of manufacturing a high-voltage IGFET, the growth or deposition of gate oxide layer  44  follows the high-energy implantation steps that form the buried layers. After formation of gate oxide layer  44 , polysilicon gate  43  may be deposited and patterned. In the particular embodiment shown, a P-type body region  40  is formed prior to the N-type implantation used to simultaneously form source and drain regions  42  and  47 , respectively. For clarity purposes, body region  40  is shown merged with P-type buried layer regions  17   g ,  16   h , and  17   h . Region  40  may be formed using conventional angled implantation techniques.  
         [0049]    The embodiment of FIG. 1D also shows the optional formation of P-type region  41  to increase the integrity of the source-to-substrate connection and reduce susceptibility of the device to parasitic bipolar effects.  
         [0050]    Another optional processing step shown in FIG. 1D is the formation of a drain polysilicon member  45 . Drain polysilicon member  45  is shown insulated from substrate  10  by oxide layer  46  and extending over a portion of field oxide  30 . Similarly, a portion of polysilicon gate  43  is made to extend over part of field oxide  30 . These polysilicon extensions are useful for field-plating purposes. Oxide layers  44  and  46  may be formed simultaneously by the same process steps, as may polysilicon layers  43  and  45 .  
         [0051]    [0051]FIG. 1E is a cross-sectional side view of the embodiment of FIG. 1D following the formation of an inter-level dielectric layer  50 , etching of contact openings, and deposition and patterning of a conductive layer. The inter-level dielectric layer  50  may be deposited (and then densified or reflowed, if necessary). By way of example, dielectric layer  50  may comprise a low-temperature oxide (LTO).  
         [0052]    Conventional photolithography and etching steps are employed to form contacts to the source and drain regions. A suitable conductive material such as aluminum, titanium alloy, or copper is commonly deposited, patterned, and etched to form respective source and drain electrodes  52  and  51 , which provide electrical contact to source and drain regions  42  and  47 , respectively. Note that electrode  52  also contacts region  41  to provide electrical connection to region  40  and substrate  20  (via layers  16  and  17 ) in the embodiment shown. Practitioners in the art will appreciate that the HVFET of the illustrated embodiment is typically operated with the source and substrate connected to ground, which provides the double-sided JFET with enhanced switching characteristics.  
         [0053]    Furthermore, each of electrodes  51  and  52  may include a portion that extends over dielectric layer  50  to act as a field plate member. These field plate members reduce peaks in the localized electric field, thereby increasing the breakdown voltage of the transistor.  
         [0054]    In the completely fabricated device, the IGFET channel region comprises the area of body region  40  directly under gate  43  between N+ source region  42  and the extended drain region, which begins at the lateral boundary of body region  40  and substrate  10 . Also note that the embodiment of FIG. 1E shows each of the P-type buried layer regions  15   a - 15   h  is surrounded above, below and laterally by N-type material of substrate  10 ; the JFET conduction channels being formed in a parallel manner between the corresponding buried layer regions. It is appreciated that the separation of buried layer regions  15  from N+ drain region  47  by a portion of the N-type substrate  10  improves the breakdown voltage of the transistor.  
         [0055]    When the HVFET is in the on-state, electron current flows from the source diffusion region  42  through the IGFET channel region beneath gate  43 , then through the parallel JFET channels formed between buried layer regions  15   a - 15   h , and finally to drain diffusion region  47 . The formation of a large number of parallel-configured P-type buried layers (e.g., 8 in this example) and their corresponding JFET conduction channels (e.g., 9 in this example) greatly reduces the resistance of the extended drain region as compared to a conventional device.  
         [0056]    In one particular implementation of the HVFET process, each of the buried layer regions  15  includes a connection to substrate  20  (not shown in the cross-sectional views  1 A- 1 E) or another region having substantially the same potential. This insures that buried layer regions  15  are not left floating (electrically).  
         [0057]    Another embodiment of the invention is shown in FIG. 2. This embodiment obviates the need for a uniformly doped N-type starting substrate material. Instead, a diffused N-well region  60  is initially formed in a P-type substrate  68  using ordinary processing techniques. N-well region  60  is fabricated prior to introduction of the buried layers  15 . In this embodiment, the HVFET can be effectively isolated from other circuitry by the lateral junction of N-well  60  and P-type substrates  20  and  68 . Thus, the approach of FIG. 2 obviates the need for the aforementioned steps associated with the formation and merging of the PB′ and PB″ layers.  
         [0058]    Yet another alternative embodiment is shown in the cross-sectional side view of FIG. 3. Rather than forming a continuous P-type region by merging PB′ and PB″ layers  16  and  17 , a deep P-type diffusion into the N-type substrate  10  is performed prior to formation of the first plurality of buried layers (e.g., regions  15   a - 15   d ). During the subsequent formation of P-type body region  40 , deep P+ diffusion region  61  merges with region  40  to provide isolation of the HVFET from other circuitry fabricated on the same substrate.  
         [0059]    [0059]FIG. 4 shows still another embodiment of the invention in which a trench isolation oxide region  62  is formed in substrate  10  to electrically isolate the HVFET. By way of example, the trench may be formed by conventional etching methods after substrate  10  has been bonded to substrate  20  and thinned, as described previously. A low-temperature oxide may be used to fill the isolation trench region.  
         [0060]    The alternative embodiments shown in FIGS. 5 &amp; 6 involve replacing the gate and/or drain regions of the device with trench structures to provide more uniform current flow through the parallel-configured JFET conduction channels.  
         [0061]    For example, the device structure shown in the cross-section of FIG. 5 may be produced by replacing the formation of gate  43  (see FIG. 1E) with the following processing steps. First, a deep trench region is etched down to substrate  20  in substrate  10  adjacent to the source region of the device. Next, gate oxide layer  64  is formed followed by formation of a vertical polysilicon gate  63 . The remainder of the HVFET may be completed in accordance with the teachings associated with FIGS. 1D &amp; 1E.  
         [0062]    The device structure shown in the cross-section of FIG. 6 may be produced by replacing the formation of N+ drain diffusion region  47  with etching and diffusion steps that form a N+ drain trench region  67  extending deeply into substrate  10 . In this particular embodiment, the drain electrode includes a segment  71  that extends into the trench to contact drain trench region  67 .  
         [0063]    Although the processing steps in the foregoing description are for fabrication of an n-channel HVFET, it is appreciated that a p-channel HVFET can be realized by simple reversal of the conductivity types employed to form the various regions/layers.  
         [0064]    Referring now to FIG. 7A, there is shown a cross-sectional view of a first N-type epitaxial layer (Epi 1 )  60  deposited on a P-type substrate  20  in accordance with another embodiment of the present invention. To fabricate a device with a breakdown voltage of 700V or more the substrate is doped to a resistivity of about 100-150 ohm/cm. The N-type epitaxial layer thickness and doping level are chosen to provide the proper charge balance among the alternating P-type and N-type layers that are formed in the device. A multi-level masking layer  61  is formed on top of epitaxial layer  60  followed by multiple ion implantations (shown by arrows  64 ) to form multiple P-type buried layers  65 . For example, a thickness t 1  is formed to prevent dopants from being implanted in selected regions of epitaxial layer  60 . A thickness t 2  permits the formation of a first set of buried layers  65  (and optional layers  66 ) whereas the absence of masking layer  61  results in the optional formation of buried layers  67 .  
         [0065]    The dose and energy of each implant is chosen to provide the required amount of charge in each of the P-type buried layers, as well as in the corresponding JFET conduction channels that are formed in the N-type material above and below each of buried layers  65   a - 65   d . By way of example, the charge in each of the conduction channels and in each of the buried layers may be in the range of 1.5-2.5×10 12  cm −2 . Although four P-type buried layers  65   a - 65   d  are shown in FIG. 7A, more or fewer layers may be formed by implantation depending on the maximum available ion implantation energy.  
         [0066]    The cross-section of FIG. 7A also shows the optional inclusion of P-type buried layers  66  (PB′) and  67  (PB″) in the area where the source region of the transistor is formed by subsequent processing steps. The PB′ layers  66  and PB″ layers  67  are formed by the same implantation steps used to form buried layers  65 . As can be seen, appropriate selection of the thickness t 2  of masking layer  61  and the energy of implantation  64  allows for the merging of layers  66   a - 66   d  and  67   a - 67   d  to form a continuous region of P-type doping. This continuous P-type region may be used to isolate the HVFET from other circuitry fabricated in the same epitaxial layer.  
         [0067]    It should be understood that the inclusion of layers  67  is a separate option to the inclusion of layers  66 , which are also an option to the embodiment of FIGS.  7 A- 7 E. In other words, certain implementations may include PB′ layers  66  without PB″ layers  67 .  
         [0068]    [0068]FIG. 7B shows the embodiment of FIG. 7A after a second N-type epitaxial layer  70  has been formed on the upper surface of epitaxial layer  60 . Again, the thickness and doping level of N-type epitaxial layer  70  are chosen to provide charge balance among the second set of alternating P-type buried layers  75   a - 75   d  and N-type conduction channels formed in the device by multiple ion implantations  74  through multi-level masking layer  71 . In one implementation the charge in each of the conduction channels and each of the buried layers may be in the range of 1.5-2.0×10 12  cm −2 . Because the uppermost N-type conduction channel at the surface of epitaxial layer  70  is not sandwiched between two P-type buried layers, there may be less charge (e.g., half) in the uppermost layer as compared to the other conduction channels.  
         [0069]    Optional PB′ layers  76  and PB″ layers  77  may be formed in epitaxial layer  70  in the same manner described above for layer  60 . Note that PB″ layer  77   d  is formed to merge with PB′ layers  76   d  and  66   a , so that a continuous P-type doping region is formed from the top of layer PB′  76   a  down to P-substrate  20 . Following the formation of P-type buried layers  75  in epitaxial layer  70  (along with PB′ and PB″ layers  76  &amp;  77 , if optionally included) the extended drain region of the HVFET is essentially complete.  
         [0070]    Practitioners in the art will appreciate that the foregoing processing sequence of epitaxial deposition followed by formation of multiple P-type buried layers may be repeated to produce a device with even more JFET conduction channels in the extended drain region of the HVFET.  
         [0071]    FIGS.  7 C- 7 E illustrate the processing steps employed to form an insulated gate HVFET having an extended drain region fabricated according to the method described above for FIGS.  7 A- 7 B. By way of example, FIG. 7C shows the device after formation of a field oxide layer  79  and gate oxide layer  84  over the upper surface of epitaxial layer  70 . Gate oxide layer  84  is formed above the MOS channel region of the device. Field oxide layer  79  is disposed above the drift region of the device and may be formed utilizing low temperature processing techniques that minimize diffusion of the underlying P-type buried layers. Although field oxide layer  79  provides flexibility in the formation of field plate members at the source and drain ends of the device, it should be understood that certain alternative embodiments may constructed without field oxide layer  79 .  
         [0072]    The example of FIG. 7C also shows the formation of a polysilicon gate member  83 . Gate member  83  includes a field plate that extends over a portion of field oxide  79 . A polysilicon drain field plate member  85  is also shown formed over a portion of field oxide  79  near where the drain region of the device will be located. FIG. 7C further illustrates the formation of a P-type body region  80  in epitaxial layer  70 . Note that in the example of FIG. 7C, body region  80  extends down to the depth of optional PB″ layer  77   a . Body region  80  may be formed by conventional implantation techniques either before or after the formation of the oxide layers  79  &amp;  84  and polysilicon layers  83  &amp;  85 . To minimize diffusion of the P-type buried layers  75  &amp;  65 , body region  80  should be formed using low temperature processing steps.  
         [0073]    [0073]FIG. 7D shows the device of FIG. 7C after formation of N+ source and drain regions  82  and  87 , respectively. Also included is an optional P+ region  81  located adjacent to N+ source region  82  to provide contact to body region  80  of the MOSFET. Again, low temperature processing techniques should be used to minimize diffusion of P-type buried layers  75  and  65 .  
         [0074]    In FIG. 7E the HV-IGFET device is shown completed by the addition of an inter-level dielectric layer  90  (e.g., a low-temperature oxide), etching of contact openings, followed by deposition and patterning of a conductive layer (e.g., aluminum or copper alloy) to form respective drain and source electrodes  91  and  92 . Subsequent deposition and patterning of a passivation layer (e.g., silicon nitride) may also be included in the process.  
         [0075]    [0075]FIG. 8 illustrates another alternative embodiment of the present invention in which the formation of the PB′ and PB″ layers is obviated by the formation of a dielectric trench isolation region  102  that extends through epitaxial layers  70  and  60 . The method of forming the device of FIG. 8 is similar to that of FIG. 7E, except that there is no need for a second masking layer (with different thickness) at each of the high-energy implantation steps. Trench isolation region  102  may be formed after formation of epitaxial layers  60  &amp;  70  utilizing ordinary trench and refill processing techniques. It is further appreciated that isolation region  102  may also comprise a sandwich of multiple layers, e.g., oxide/polysilicon/oxide, in accordance with known trench isolation techniques.  
         [0076]    [0076]FIG. 9 shows yet another alternative embodiment of the present invention in which a trench gate structure is constructed rather than a planar MOS gate structure, as shown in FIGS. 7 &amp; 8. The trench gate structure comprises a gate member  103  that is insulated from epitaxial layers  60  and  70  by dielectric layer  104 . Gate member  103  may be polysilicon, silicide, or other conductive material. Although dielectric layer  104  is shown as having a constant thickness in this example, this layer may also be formed with varying thickness. It may be advantageous, for example, for dielectric layer  104  to be thicker near the bottom of the trench.  
         [0077]    Note that in this embodiment the location of the P+ and N+ regions  101  and  102  in body region  80  are reversed from the previous embodiments. That is, N+ source region  102  is disposed adjacent the trench gate structure such that a vertically oriented conducting channel is formed through body region  80 . In this embodiment, contact to gate member  103  may be made periodically in the third dimension (i.e., into the page).  
         [0078]    FIGS.  10 A- 10 G are cross-sectional side views illustrating the fabrication of still another embodiment of the present invention. In this embodiment, instead of a first epitaxial layer, an N-well  110  is formed in a P-substrate  20  by ion implantation  106 , as shown in FIG. 10A. Masking layers  111  and  112  are then utilized with multiple ion implantations  114  to form a first set of P-type buried layers  115   a - 115   d  in N-well  110  together with corresponding PB′ layers  116   a - 116   d  in an adjacent region of P-substrate  20  (see FIG. 10B). An N-type epitaxial layer (Epi 1 )  120  is then formed over this structure (see FIG. 10C).  
         [0079]    Masking layers  121  and  122  are formed using conventional photolithographic techniques and multiple ion implantations  124  are performed to create a second set of P-type buried layers  125   a - 125   d  in epitaxial layer  120 . The same ion implantations  124  used to form buried layers  125  may also be used to produce PB′ and PB″ buried layers  126  and  127 , respectively, in the same manner as described for the previous embodiments. In this case, PB′ layers  126   a - 126   d  merge with PB″ layers  127   a - 127   d  to form a continuous P-type region.  
         [0080]    [0080]FIG. 10E shows the device after formation of P-body region  130  in epitaxial layer  120 . Also shown are field oxide  129 , gate oxide  134 , gate member  133 , and drain field plate member  135  formed above epitaxial layer  120 . In FIG. 10F the respective N+ source and drain regions  132  &amp;  137  have been formed, along with an optional P+ region  131  in body region  130 . FIG. 10G shows the device essentially complete following formation of an inter-level dielectric layer  140  with drain and source electrodes  141  &amp;  142  contacting the corresponding diffusion regions.  
         [0081]    The embodiment of FIG. 11 illustrates the device structure of FIG. 10E, except that the optional PB′ layers  116  &amp;  126  and PB″ layers  127  are replaced with a trench isolation region  152  that extends through epitaxial layer  120 . FIG. 12 shows yet another embodiment, which employs a trench, gate structure comprising gate polysilicon member  153  insulated from N-well  110  and epitaxial layer  120  by dielectric layer  154 . Here again, note that N+ source region  152  is disposed in body region  130  adjacent dielectric layer  154 , with optional P+ region  151  being disposed on an opposite side of N+ source region  152 .  
         [0082]    It should be understood that although the present invention has been described in conjunction with specific embodiments, numerous modifications and alterations are well within the scope of the present invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.