Abstract:
A two phase, second order capacitance-to-digital (CD) modulator includes a first stage sigma-delta integrator that forms charge packets as a function of sensor capacitance during an auto-zero phase and integrates the packets during an integration phase to produce an output voltage. The first stage integrator holds its output voltage during the auto-zero phase, so that a second stage sigma-delta integrator can sample the first stage output voltage during the auto-zero phase and integrate the sampled voltage during the integration phase.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     Reference is made to a commonly assigned co-pending application filed on even date entitled “Fold-back Free Capacitance-to-Digital Modulator”.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a measurement system. In particular, the present invention relates to a capacitance-to-digital modulator for use with a capacitive differential pressure sensor.  
         [0003]     A field transmitter is a device that is used to monitor the operation of an industrial process. The field transmitter includes a transducer that responds to a measured process variable with a sensing element and converts the variable to a standardized transmission signal that is a function of the measured variable. The term “process variable” refers to a physical or chemical state of matter or conversion of energy. Examples of process variables include pressure, temperature, flow, conductivity, and pH.  
         [0004]     One such transmitter is described in U.S. Pat. No. 6,295,875 by Roger L. Frick and David A. Broden. This transmitter employs a capacitive sensor having a deflectable sensing diaphragm and three or more capacitor electrodes which form separate capacitive sensing elements with the diaphragm. Two of the capacitor elements are primary sensing capacitors that are arranged differentially so that the capacitances of the primary sensing capacitors charge oppositely in proportion to the process variable. The third and fourth capacitor elements are compensation capacitors that provide signals representing offset errors or hysteresis associated with the primary capacitors. As pressure is applied to one or both sides of the diaphragm, the diaphragm deflects. The deflection of the diaphragm can be detected by measuring a change in a ratio of electrical capacitance related to the deflection. This capacitance ratio is converted into a digital format using an analog-to-digital converter.  
         [0005]     One particularly advantageous form of analog-to-digital converter uses a sigma-delta (or delta-sigma) modulator. The use of sigma-delta modulators in transmitters is described in U.S. Pat. No. 5,083,091 by Roger L. Frick and John P. Schulte; U.S. Pat. No. 6,140,952 by Michael Gaboury; U.S. Pat. No. 6,509,746 by Rongtai Wang; and U.S. Pat. No. 6,516,672 by Rongtai Wang.  
         [0006]     In a transmitter having a sigma-delta modulator acting as a capacitance-to-digital (CD) converter, an excitation circuit provides charge packets to the capacitive sensor elements. The sensor elements are charged by an amount based on the capacitance value of that capacitive element. The charges are transferred to an integrator/amplifier of the sigma-delta modulator to produce a one-bit binary output which is a function of a capacitance ratio.  
         [0007]     The basic function of the CD modulator is to convert the capacitance ratio into a PCM (pulse code modulation) signal. The capacitance ratio under measurement is defined as: η=(C X −C Y )/(C X +C Y ), where C X  and C Y  represent capacitance of two sensor capacitors with a common plate.  
         [0008]     For a CD modulator using sigma-delta architecture, the actual process involves converting a charge ratio into a PCM signal. Under normal operating conditions, since the charge is proportional to the capacitance, the charge ratio is equal to the capacitance ratio.  
         [0009]     However, this equivalent relation is not true under certain abnormal operating conditions. One such operating condition is overpressure in conjunction with a short circuit in one of the sensor capacitors. Due to the leakage caused by the short circuit, the charge that is transferred from the sensor capacitor may be very small. As a result of this, the digital reading provided by PCM signal is not equal to the capacitance ratio. Not only is the magnitude of the reading not correct, in many cases even the polarity of the reading is wrong. This kind of phenomena is called “fold-back anomaly”. There is a need for improved circuitry that eliminates the fold-back anomaly.  
       BRIEF SUMMARY OF THE INVENTION  
       [0010]     A second order capacitance-to-digital (CD) modulator includes first and second stage sigma-delta integrators which operate together in a two phase operation, in which a first phase is an auto-zero phase and a second phase is an integration phase. The first stage sigma-delta integrator is not reset during the auto-zero phase, so that the output of the first stage sigma-delta integrator can be sampled by a second stage sigma-delta integrator during the auto-zero phase and integrated during the integration phase.  
         [0011]     Suppression of fold-back anomaly caused by a combined overpressure and short circuit condition is provided by an auto-zero capacitor of the first stage sigma-delta integrator. The auto-zero capacitor stores a voltage that is a function of leakage resistance of a sensor capacitor during each auto-zero phase. 
     
    
     A BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a block diagram of a differential pressure transmitter.  
         [0013]      FIG. 2  is a block diagram of a capacitance-to-digital (CD) modulator of the transmitter of  FIG. 1 .  
         [0014]      FIG. 3  is a schematic diagram of one embodiment of a first stage integrator of the CD modulator of  FIG. 2 .  
         [0015]      FIG. 4  is a diagram showing an example of V OUT1 , auto-zero (Z) and integration (I) signals of the first stage integrator of  FIG. 3 .  
         [0016]      FIG. 5  is a schematic diagram of a second stage integrator of the CD modulator of  FIG. 2 .  
         [0017]      FIG. 6  is a schematic diagram of a quantizer of the CD modulator of  FIG. 2 .  
         [0018]      FIGS. 7A and 7B  show waveforms of first stage output voltage V OUT1  and pulse code modulation pressure signal PCMP from a computer simulation of normal operation of the CD modulator of  FIGS. 2-6 .  
         [0019]      FIGS. 8A and 8B  show waveforms of first stage output voltage V OUT1  and pulse code modulation pressure signal PCMP from a computer simulation of overpressure/short circuit operation of the CD modulator of  FIGS. 2-6 .  
         [0020]      FIG. 9  is a schematic diagram of another embodiment of a first stage integrator of CD modulator of  FIG. 2 .  
         [0021]      FIGS. 10A and 10B  show output current and output voltage, respectively, as a function of load resistance for an operational transconductance amplifier (OTA) buffer.  
         [0022]      FIGS. 11A and 11B  show a computer simulation of output current and output voltage characteristics of the OTA buffer used in the first stage integrator of  FIG. 9 .  
         [0023]      FIGS. 12A and 12B  show waveforms of first stage output voltage V OUT1  and pressure signal PCMP from a computer simulation of overpressure/short circuit operation of a CD modulator without anti-foldback circuitry.  
         [0024]      FIGS. 13A and 13B  show waveforms of first stage output voltage V OUT1  and pressure signal PCMP from a computer simulation of overpressure/short circuit operation of a CD modulator including the first stage integrator of  FIG. 9 . 
     
    
     DETAILED DESCRIPTION  
       [0025]      FIG. 1  shows pressure transmitter  10 , which is a capacitance-based differential pressure transmitter that includes main sensor capacitors C MX  and C MY , linear compensation capacitors C LX  and C LY , resistors R X  and R Y , analog section  12  (which includes second order capacitance to digital (CD) modulator  14 , first order voltage to digital (VD) modulator  16 , and digital interface unit  18 ), digital section  20 , microprocessor  22 , and interface  24 . Communication between transmitter  10  and a control room is provided through interface  24 . The communication may be through a two-wire loop or network over which analog, digital, or a combination of analog and digital signals are transmitted, or may be via wireless transmission.  
         [0026]     Analog section  12  and digital section  20  may be incorporated in a mixed signal application specific integrated circuit (ASIC) chip. Digital interface unit  18  of analog section  12  receives digital clock signals and other control signals from digital section  20 . Digital interface unit  18  provides a level shift function between the signal levels required for digital section  20  and those required for analog section  12 . It also generates timing signals and other control signals for CD modulator  14  and VD modulator  16 .  
         [0027]     The timing signals provided by digital interface unit  18  include zero phase signals Z and ZD, integration phase signals I and ID, quantizer timing signals SCK and DCK, and a reset signal.  
         [0028]     Second order CD modulator  14  is a sigma-delta converter that receives capacitance inputs C X  and C Y  at input nodes  30  and  32  and produces a pulse code modulation pressure (PCMP) signal that is a function of the difference of capacitances C X  and C Y  divided by the sum of capacitances C X  and C Y . CD modulator  14  receives timing and control signals from digital interface unit  18  and generates excitation signals SENEX and LINEX.  
         [0029]     Components C MX  and C MY  represent the sensor capacitors, with their common plate connected to receive sensor excitation signal SENEX. Components C LX  and C LY  are linear compensation capacitors having their common plate connected to a linearization excitation signal LINEX.  
         [0030]     Input capacitances C X  and C Y  are defined as: 
 
 C   X   =C   MX   −C   LX  
 
 C   Y   =C   MY   −C   LY  
 
         [0031]     The differential capacitance ratio η P  is:  
         η   p     =         C   X     -     C   Y           C   X     +     C   Y             
 
         [0032]     The transfer function for CD modulator  14  is: 
 
η P =2·D P −1 
 
 where D P  is the pulse density of PCMP signal. For normal operation, the dynamic range of the ratio η P  is: 
 
−0.8≦η P ≦0.8, 
 
 where C X  and C Y  can each reach a maximum effective capacitance of about 100 pF. CD modulator  14  must be fold-back free in the case of overpressure with a short circuit. 
 
         [0033]     VD modulator  16  is a first order sigma-delta converter or integrator which receives a voltage input VTIN from the voltage divider performed by resistor R O  and temperature sensing resistor RTD at its input node  34 . The output of VD modulator  16  is a pulse code modulation temperature (PCMT) signal.  
         [0034]     The PCMP and PCMT outputs from CD modulator  14  and VD modulator  16  are provided to digital section  20  where they are filtered. Pressure and temperature data based on the filtered PCMP and PCMT signals is stored in digital section  20  for use by microprocessor  22  and for transmission through interface circuit  24 .  
         [0035]      FIG. 2  shows a block diagram of CD modulator  14 , which includes first stage integrator  40 , second stage integrator  42 , quantizer  44 , control unit  46 , and bias circuit  48 . First stage integrator  40  is a sigma-delta integrator that produces a first stage output that is a function of capacitances C X  and C Y . Integrator  40  operates in an auto-zeroing mode during a first (or auto-zero) phase defined by the timing signals Z and ZD, where ZD is slightly delayed with respect to Z. Integrator  40  operates in an integration mode during a second (or integration) phase defined by the integration timing signals I and ID, where ID is slightly delayed with respect to 1. The selection of which input (C X  or C Y ) is connected to integrator  40  is based upon the state of output signal Y from quantizer  44 .  
         [0036]     Second stage integrator  42  is a sigma-delta integrator that samples the output of first stage integrator  40 , and produces an output that is supplied to quantizer  44 . Because first stage integrator  40  is not reset during the auto-zero phase, a two phase second order CD modulation is possible. Second stage integrator  42  performs its auto-zero and integration phases at the same time as first stage integrator  40 , using the Z, ZD, I, and ID timing signals. In addition, second stage integrator  42  receives a reset signal.  
         [0037]     The function of quantizer  44  is to convert the output signal of second stage integrator  42  to pulse code modulation signal PCMP, which is delivered to digital section  20 . Quantizer  44  also provides signal Y, which is the inverse of signal PCMP. Y is used by CD control unit  46  and first stage integrator  40 .  
         [0038]     The main function of control unit  46  is to generate the SENEX signal and the LINEX signal. These signals are generated as a function of Y and the ZD and ID timing signals. The SENEX and LINEX signals are switched between a midlevel excitation voltage source VMID and a low side excitation voltage source VSSA. The LINEX signal is the inverse of the SENEX signal.  
         [0039]     CD bias circuit  48  provides source current for the amplifiers of integrators  40  and  42  and the comparator of quantizer  44 . It also generates bias voltages for the amplifiers, and provides a source current for the bias circuitry of VD modulator  16 .  
         [0040]      FIG. 3  is a circuit schematic diagram of first stage integrator  40 . Also shown in  FIG. 3  are sensor capacitors C X  and C Y , leakage resistors R XL  and R YL , and resistors R X  and R Y , and a simplified diagram of CD control unit  46 .  
         [0041]     First stage integrator  40  includes amplifier A 1 , feedback capacitor C F1 , auto-zero capacitor C Z1 , switches SW 1 -SW 7  and on chip resistors R 1 -R 3 . In one embodiment, feedback capacitor C F1  is 150 pF, auto-zero capacitor C Z1  is 30 pF, resistors R 1  and R 2  are 10 kΩ each, and resistor R 3  is 4 kΩ.  
         [0042]     The switch control signals for switches S 1 -S 7 , SW A  and SW B  are: 
 
 SW   1   =SW   4   =Y  
 
SW 2 =SW 3 =  Y 
 
SW 5 =I 
 
SW 6 =Z 
 
SW 7 =ZD 
 
 SW   A   =Y·ID+  Y ·ZD  
 
 SW   B   =Y·ZD+  Y ·ID  
 
         [0043]     The operation of first stage integrator  40  is as follows. During the auto-zero phase, switch SW 5  is off and switches SW 6  and SW 7  are on. The offset of amplifier A 1  is stored in capacitor C Z1  without first stage integrator  40  being reset (i.e., without feedback capacitor C F1  being discharged). At the same time, the sensor capacitor (either C X  or C Y ) is charged or discharged.  
         [0044]     In the case where Y is high, sensor C X  is selected with its input node connected by S W1  to common node A of integrator  40 . With Y high and ZD high, switch SW B  of CD control unit  46  is on and the SENEX signal applied to sensor C X  is VSSA. As a result, a voltage drop is built across C X , since integrator input node A of integrator  40  is connected through switch SW 7  and resistor R 3  to VMID.  
         [0045]     In the case where Y is low, sensor C Y  is connected by SW 3  to integrator input node A of integrator  40 . In that case, switch SW A  is on and SW B  is off so that the SENEX node is connected to VMID. Voltage drop across C Y  is zero, because switches SW 3  and SW 7  are closed and C Y  has voltage VMID applied to both of its plates.  
         [0046]     During the integration phase, switch SW 5  is on and switches SW 6  and SW 7  are off. Integrator  40  is in an integration mode.  
         [0047]     In the case where Y is high, the SENEX node will have suddenly changed from VSSA to VMID as a result of switch SW B  turning off and SW A  turning on. A positive charge package is transferred from C X  through S W1  to integrator input node A of integrator  40 . As a result, a negative voltage step is created at V OUT1 .  
         [0048]     In the case where Y is low, the SENEX node is suddenly switched from VMID to VSSA. A negative charge package is transferred from C Y  through SW 3  to integrator input node A. As a result, a positive voltage step is created at V OUT1 .  
         [0049]     The excitation voltage ΔV EX  is the voltage difference between VMID and VSSA. The amount of charge transferred into first stage integrator  40  from C X  or C Y  in each operation can be expressed as ΔQ X =C X ·ΔV EX  or ΔQ Y =C Y ·ΔV EX  respectively. By denoting N 0  as the number C X  operations, N 1  as the number C Y  operations, and N=N 0 +N 1  as the total number of operations, the charge balancing equation for first stage integrator  40  can be written as: 
 
 N   0   ·C   X   ·ΔV   EX   −N   1   C   Y   ·ΔV   EX =0. 
 
 This gives the required measurement relation:  
               C   X     -     C   Y           C   X     +     C   Y         =       2   ⁢       N   1     N       -   1       ,       
 
 where the ratio N 1 /N is the pulse density of the PCMP signal. 
 
         [0050]      FIG. 4  shows an example waveform of V OUT1  for first stage integrator  40 , along with the auto-zero phase signal Z and the integration phase signal I. In this example, C X =75 pF, C Y =25 pF, C n =150 pF, C z =30 pF, and VDDA=4.8V, VSSA=0 and VMID=2.4V.  
         [0051]     As seen in  FIG. 4 , the output V OUT1  of first stage integrator  40  is on hold during the auto-zero phase (when Z is high). In other words, V OUT1  is not reset to zero during each auto-zero phase. This allows two phase second order operation, in which second stage integrator  42  uses the same auto-zero and integration phases as first stage integrator  40 . As a result, the number of switches and control signals required for CD modulator  14  is reduced, circuit complexity and layout complexity is reduced, and the settling of integrators  40  and  42  is improved.  
         [0052]      FIG. 5  shows a circuit schematic diagram of second stage integrator  42 , which includes amplifier  82 , feedback capacitor C F2 , auto-zero capacitor C Z2 , two sampling capacitors C 1  and C 2 , and switches SW 8 -SW 15 . In one embodiment, C F2 =40 P F, C Z =10 P F, C 1 =20 P F and C 2 =10 P F.  
         [0053]     The switch control signals for SW 8 -SW 15  are: 
 
SW 8 =SW 11 =ID 
 
SW 9 =SW 10 =ZD 
 
SW 12 =I 
 
SW 13 =Z 
 
SW 14 =ZD 
 
SW 15 =RESET 
 
         [0054]      FIG. 6  is a simplified circuit schematic of CD quantizer  44 , which compares V OUT2  to VMID and produces the pulse code modulated pressure signal PCMP as well as control signal Y. CD quantizer  44  includes comparator  50 , D flip-flop  52  and inverters  54  and  56 .  
         [0055]     The positive input node of comparator  50  is connected to VMID, while the negative input node is connected to the output V OUT2  of second stage integrator  42 . Timing signal SCK provides an active low trigger for comparator  50 .  
         [0056]     D flip-flop  52  serves a synchronization purpose. It is triggered by the front edge of the DCK signal. That front edge is located between the falling edge of the integration phase timing signal ID and the rising edge of the auto-zero phase timing signal Z.  
         [0057]     Two stage CD modulator  14  provides an automatic fold-back feature, without the need for a short circuit detector or other auxiliary circuitry in order to suppress the fold-back anomaly. Two cases need to be considered: C X  side overpressure with a short circuit; and C Y  side overpressure with a short circuit. In both cases, first stage integrator  40  prevents fold-back.  
         [0058]     In the case of C X  side overpressure together with a short circuit, auto-zero capacitor C Z1  also serves as a short circuit adapter. During auto-zero phase, switches SW 6  and SW 7  are closed, and SW B  is closed, applying VSSA to C X . Current flows from VMID, through R 3  and SW 7  to node A, and through SW 1 , R X  and R XL  to VSSA. Due to the small leakage resistance R XL  across C X (i.e. a short circuit), the voltage at integrator input node A becomes much lower than VMID during the auto-zero phase. This lower voltage is sampled in the auto-zero phase, and is held by first integrator  40  in the integration phase.  
         [0059]     During the integration phase, SW 5  is closed, SW 6  and SW 7  are open, and SW A  is closed to apply VMID to C X . The lower voltage at node A induces a current during the integration phase from VMID through R XL , R X , and SW 1  and SW 5  into C F1 . It is this induced current that keeps integrator  40  in saturation. As a result, no fold-back anomaly occurs.  
         [0060]     In the case of C Y  side overpressure with a short circuit, the voltage drop on C Y  is discharged to zero in the auto-zero phase because it has VMID applied to both plates of C Y  when Y is low and ZD is high. Therefore, the leakage resistor R YL  across C Y  has no effect on the voltage across C Y . In the integration phase with Y low, the SENEX node is connected to VSSA. The short circuit across C Y  will make integrator saturation even deeper, and no fold-back anomaly will occur.  
         [0061]     In order to protect the VMID voltage source from an overpressure short circuit, resistors R-R 3  are provided in integrator  40  shown in  FIG. 3 . Resistor R 1  is placed between switch SW 2  and VMID. Resistor R 2  is placed between switch SW 4  and VMID. Resistor R 3  is placed between switch SW 7  and VMID. The values of the resistors are chosen in such a way that the average DC current leak from VMID to VSSA is always below 100 microamps. At the same time, the RC time constant is reasonably small, so that first stage integrator  40  will settle as required.  
         [0062]     In order to demonstrate the automatic fold-back suppression, a simulation of circuit operation was performed using HSPICE software. The results are illustrated in  FIGS. 7A and 7B  and  FIGS. 8A and 8B .  
         [0063]      FIGS. 7A and 7B  are an example of the operations of CD modulator  14  with a normal input. In this example, C X =75 pF, C Y =25 pF, C F1 =150 pF, C z1 =30 pF, and VDDA=4.8V, VSSA=0 and VMID=2.4V.  FIG. 7A  shows a waveform of output V OUT1  from first stage integrator  40 .  FIG. 7B  shows corresponding pulse code modulation output signal PCMP.  
         [0064]      FIGS. 8A and 8B  show an example in which X side overpressure and a short circuit have occurred. In this example, C X =2,000 pF, C Y =10 pF, C F1 =150 pF, C Z1 =30 pF, VDDA=4.8V, VSSA=0 and VMID=2.4V. The leakage resistor R XL  across C x  is 1 ohm, while the leakage resistor R YL  across C Y  is 1 Gohm.  FIG. 8A  is a waveform of output V OUT1  of first stage integrator  40 .  FIG. 7B  shows the waveform of the corresponding pulse code modulation output signal PCMP. As can be seen, despite the combined effects of X side overpressure and a short circuit, output signal PCMP indicates a high or overpressure condition.  
         [0065]      FIG. 9  shows another embodiment of first stage integrator  40 ′, which is generally similar to the embodiment shown in  FIG. 3 , except that protection resistors R 1 -R 3  have been replaced by operational transconductance amplifier (OTA) buffer  70 , which converts midlevel supply voltage (VMID) to a variable voltage VMIDA that varies as a function of load resistance at the output of OTA buffer  70 . The positive input of OTA buffer  70  is connected at VMID. The negative input and the output of OTA buffer  70  are connected together.  
         [0066]      FIGS. 10A and 10B  illustrate the output current and output voltage characteristics, respectively, of OTA buffer  70 . In  FIG. 10A , output current I OUT  Of OTA buffer  70  is shown as a function of load resistance R L . In the region where load resistance R L  is greater than characteristic resistance R O , the buffer output current I OUT  decreases as load resistance R L  increases. The relationship is approximately I OUT =V REF /R L . In the region where load resistance R L  is less than R O , the buffer output current I OUT  remains a constant approximately. This constant current is equal to the maximum slew current I O  of OTA buffer  70 .  
         [0067]     As shown in  FIG. 10B , output voltage V OUT  also varies as a function of load resistance R L . In the region where load resistance R L  is greater than R O , output voltage V OUT  of OTA buffer  70  is determined by the output current I OUT  and the transconductance G M  of OTA buffer  70 . That is, 
 
 V   OUT   ≈V   REF   +V   OFFSET   −I   OUT   /G   M . 
 
 In the region where load resistance R L  is less than R O , the buffer output voltage V OUT  decreases as load resistance decreases: 
 
 V   OUT   ≈I   OUT   ·R   L . 
 
 The characteristic resistance value R O  can be estimated by R O =V REF /I OUT . 
 
         [0068]     Under normal operating conditions without a short circuit, leakage resistance R XL  of sensor capacity C X  is very high. During the auto-zero phase, since the load resistance seen by OTA buffer  70  is R X +R XL  (and therefore is very high) buffer  70  serves as a constant voltage source. VMIDA at the output of buffer  70  differs from VMID by small offset.  
         [0069]     The voltage difference VMIDA−VSSA is fully dropped across sensor capacitor of C X  during the auto-zero phase, and a desired charge package is stored in sensor capacitor C X . During the integration phase, an expected voltage step is created at the integrator output node during normal operation. In the case of overpressure without a short circuit, since the value of the input capacitor C X  exceeds the value of feedback capacitor C F1 , integrator  40 ′ becomes saturated.  
         [0070]     During an abnormal operating condition involving an overpressure of C X  with a short circuit, leakage resistance R XL  across sensor capacitor C X  is very small. During auto-zero phase, since the effective load resistance seen by OTA buffer  70  is much smaller than R O , buffer  70  serves as a current source through switch SW 1 , R X , and R XL  and switch SW B  to voltage supply VSSA. The buffer output voltage VMIDA becomes lower than VMID. The lower buffer output voltage VMIDA causes a lower voltage at node A. The voltage difference between node A and the negative input of amplifier A 1  is stored in auto-zero capacitor C Z1 .  
         [0071]     During integration phase, due to the stored voltage in auto-zero capacitor C Z1 , a current is induced. This current flows from VMID, through SW A , R XL , R X , SW 1 , and SW 5  into feedback capacitor C F1 . It is this current that forces integrator  40 ′ to be fully saturated.  
         [0072]     In summary, with the embodiment shown in  FIG. 9 , during the auto-zero phase the leakage resistance R XL (an analog variable) is converted into an input node A voltage (another analog variable) and is stored in auto-zero capacitor C Z1 . During the integration phase, the voltage stored in auto-zero capacitor C Z1  will control integrator operation. In the case of overpressure with a short circuit, integrator  40 ′ will become saturated.  
         [0073]     In order to demonstrate the automatic fold back suppression of the circuit shown in  FIG. 9 , a simulation of circuit operation was performed using HSPICE software. The results are illustrated in  FIGS. 11A and 11B ,  12 A and  12 B, and  13 A and  13 B.  
         [0074]      FIGS. 11A and 11B  show the HSPICE simulation results of the characteristics of OTA buffer  70  with a variable resistance load.  FIG. 11A  shows output current, and  FIG. 11B  shows output voltage.  
         [0075]     In the simulation results shown in  FIGS. 11A and 11B , the supply of the buffer circuit is 4.8V, and the reference input VMID is 2.4V. In this simulation, a linear voltage control load resistor is employed. That is, when the control voltage is 1 V C , the load resistor value is 100 K. When the control voltage is 500V, the load resistor value is 50 K. The characteristic load resistance in the simulation was R O =45.4 K.  
         [0076]      FIG. 11A  shows output current I OUT  as a function of the control voltage V C . In the region R L  is less than R O , the output current is close to a constant (about 58 μA ). In the region where load resistance R L  is greater than the characteristic load resistance R O , the output current decreases as R L  increases.  
         [0077]      FIG. 11B  shows output voltage V OUT  versus the control voltage Vc. In the region where load resistance R L  is less than characteristic load resistance R O , the output voltage V OUT  decreases as load resistor value (control voltage) decreases. In the region where load resistance R L  exceeds characteristic load resistance R O , the buffer output voltage V OUT  is close to a constant.  
         [0078]      FIGS. 12A and 12B  show the HSPICE simulation results of a CD modulator without anti-foldback circuitry.  FIG. 12A  shows waveform of output voltage V OUT1  representing the output of first stage integrator  40 ′.  FIG. 12B  shows a waveform of the PCMP output signal.  
         [0079]     In this simulation, the input sensor capacitance size is C X =2,000 pF and C Y =10 pF. The leakage resistor for the X side is R XL =500 ohm, and for the Y side RYL=100 Gohm. The input series resistor R X  and R Y  are 12.1 K.  
         [0080]     Based upon the input, the calculated capacitance ratio for this simulation is above 0.90. However, based upon the PCMP signal, the capacitance ratio produced by the CD modulator is about 0.65. This illustrates the inaccuracy produced by fold-back anomaly.  
         [0081]      FIGS. 13A and 13B  show the HSPICE simulation results of the two phase CD modulator with the anti-foldback feature using OTA buffer  70  as shown in  FIG. 9 .  FIG. 13A  shows the output of first stage integrator  40 ′, while  FIG. 13B  shows the waveform of the PCMP output signal.  
         [0082]     For the simulation shown in  FIGS. 13A and 13B , the capacitances are C X =2,000 pF and C Y =10 pF. The leakage resistors are R XL =500 ohms and R Y =100 Gohm. The input series resistors R X  and R Y  are 12.1 K. Thus the capacitance and resistance values are the same as used for the simulation in  FIGS. 12A  and  12 B. The OTA characteristics used for buffer  70  are the ones shown in  FIGS. 11A and 11B .  
         [0083]     Based upon the input, the calculated capacitance ratio is above 0.90. Based on the PCMP signal shown in  FIG. 13B , capacitance ratio reading is about 0.90. Thus, the fold-back anomaly has been suppressed.  
         [0084]     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.