Abstract:
According to the present invention, there is provided a semiconductor device having: a switching element serially connected to a resistive element to be measured; a plurality of transistors respectively connected in parallel to a series circuit consisting of the resistive element to be measured and the switching element, which will respectively take desired resistance values when turned on; and a measurement section which measures a resistance value of a parasitic resistance which occurs so as to be coupled to the resistive element to be measured by turning off the switching element and then controlling switching operations of the plurality of transistors to change the resistance values of resistors formed by the plurality of transistors, and subsequently measures a resistance value of the resistive element to be measured based on a resistance value of the parasitic resistance by turning on the switching element while turning off the plurality of transistors.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority under 35 USC 119 from the Japanese Patent Application No. 2005-355925, filed on Dec. 9, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a semiconductor device and a testing method thereof, and a resistance measurement apparatus.  
         [0003]     Production testing prior to shipment may include wafer tests, which are electrical tests performed in the form of a wafer on a plurality of silicon chips formed on a wafer after conclusion of front-end processing for the purpose of selecting good chips, and final tests, which are electrical tests performed on IC chips obtained by dicing and incorporating the selected good chips into packages.  
         [0004]     In some cases, such production testing may involve measuring a total resistance value of respective resistors formed on a silicon chip. This measurement is performed by connecting a tester to the silicon chip to be measured, applying a desired voltage thereto, and measuring a current flowing through the silicon chip.  
         [0005]     In this case, the measurement represents a combined value of a total resistance value of respective resistors formed within the silicon chip and a total resistance value of parasitic resistances occurring between the silicon chip and the tester.  
         [0006]     In recent years, lower levels in the total resistance value of respective resistors formed within silicon chips have lead to a problem in that, if a total resistance value of parasitic resistances is high between the silicon chip and the tester, accurate measurement of the total resistance value of respective resistors formed in the silicon chip cannot be accomplished.  
         [0007]     The following is a patent document related to a contact resistance measurement element.  
         [0008]     Japanese Patent Laid-Open No. 4-316344.  
       SUMMARY OF THE INVENTION  
       [0009]     A semiconductor device according to an aspect of the present invention includes:  
         [0010]     a switching element serially connected to a resistive element to be measured;  
         [0011]     a plurality of transistors respectively connected in parallel to a series circuit consisting of the resistive element to be measured and the switching element, which will respectively take desired resistance values when turned on; and  
         [0012]     a measurement section which measures a resistance value of a parasitic resistance which occurs so as to be coupled to the resistive element to be measured by turning off the switching element and then controlling switching operations of the plurality of transistors to change the resistance values of resistors formed by the plurality of transistors, and subsequently measures a resistance value of the resistive element to be measured based on a resistance value of the parasitic resistance by turning on the switching element while turning off the plurality of transistors.  
         [0013]     A semiconductor device testing method according to an aspect of the present invention, which tests a semiconductor device having  
         [0014]     a switching element serially connected to a resistive element to be measured, and  
         [0015]     a plurality of transistors respectively connected in parallel to a series circuit consisting of the resistive element to be measured and the switching element, which will respectively take desired resistance values when turned on, the testing method includes:  
         [0016]     measuring a resistance value of a parasitic resistance which occurs so as to be coupled to the resistive element to be measured by turning off the switching element and controlling switching operations of the plurality of transistors to change the resistance values of resistors formed by the plurality of transistors; and  
         [0017]     measuring a resistance value of the resistive element to be measured based on a resistance value of the parasitic resistance by turning on the switching element while turning off the plurality of transistors. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]      FIG. 1  is a circuit diagram showing a configuration of a resistance measurement apparatus according to a first embodiment of the present invention;  
         [0019]      FIG. 2  is a circuit diagram showing a configuration of a resistance measurement apparatus according to a second embodiment of the present invention; and  
         [0020]      FIG. 3  is an explanatory diagram showing a relationship between a number of MOS transistors which have been turned on, and a current value “I” flowing through a resistance measurement apparatus. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]     Embodiments of the present invention will now be described with reference to the drawings.  
       (1) FIRST EMBODIMENT  
       [0022]     A configuration of a resistance measurement apparatus  10  according to a first embodiment of the present invention is shown in  FIG. 1 . The resistance measurement apparatus  10  is used in final tests which test IC chips obtained by dicing and incorporating the good chips selected through wafer tests into packages are electrically tested.  
         [0023]     More specifically, the resistance measurement apparatus  10  is formed by connecting a package  30  having a silicon chip  20  incorporated therein to a socket  40  placed on a tester board  50 . Additionally, a tester  55  is connected to the tester board  50 . A plurality of resistors having desired resistance values are formed in the silicon chip  20 . An internal resistor “Rin” represents a combined resistor of these resistors. Therefore, the resistance value of the internal resistor “Rin” represents the resistance value of the combined resistor of the respective resistors formed in the silicon chip  20 .  
         [0024]     A MOS transistor TR 10  as a switching element is serially connected to the internal resistor “Rin” to be measured. MOS transistors TR 20   1  and TR 20   2 , having the same transistor characteristics, are parallel-connected to the series circuit consisting of the internal resistor “Rin” and the MOS transistor TR 10 .  
         [0025]     In the present embodiment, the package  30  includes package resistors Rp 1  and Rp 2  as parasitic resistances, the socket  40  includes socket resistors Rs 1  and Rs 2  as parasitic resistances, while the tester board  50  includes board resistors Rb 1  and Rb 2  as parasitic resistances. In addition, contact resistors Rps 1  and Rps 2  exist as parasitic resistances between the package  30  and the socket  40 , while contact resistors Rsb 1  and Rsb 2  exist as parasitic resistances between the socket  40  and the tester board  50 .  
         [0026]     The resistance measurement apparatus  10  measures a resistance value of the internal resistor “Rin”, which is a combined resistor of each resistor formed within the silicon chip  20  to be measured by applying a voltage “Vdd” to the silicon chip  20 , and measuring a current “I” which flows through the silicon chip  20 .  
         [0027]     More specifically, the MOS transistor TR 10  is initially turned off to create a state in which the internal resistor “Rin” is not connected. Next, a drain-source voltage, i.e., the voltage “Vdd”, to be applied between the drains and the sources of the MOS transistors TR 20   1  and TR 20   2  are adjusted so that the MOS transistors TR 20   1  and TR 20   2  respectively take a desired resistance value “Rtr” when turned on.  
         [0028]     Generally, MOS transistors TR 20   1  and TR 20   2  each have a linear region in which a current value flowing between the drain and the source increases so as to have a constant gradient (i.e. resistance value “Rtr”) as the drain-source voltage increases, and a region in which a constant value is approximately maintained after the current reaches the constant value. In the case of the present embodiment, drain-source voltage is adjusted within the range of the linear region.  
         [0029]     Next, the MOS transistor TR 20   1  is turned on while the MOS transistor TR 20   2  is turned off in order to measure a current “I 1 ” flowing through the resistance measurement apparatus  10 . A resistance value “R 1 ” of the combined resistor of the entire resistance measurement apparatus  10  in a state in which only the MOS transistor TR 20   1  is turned on may be expressed using voltage “Vdd” and current “I 1 ” by the formula. 
 
 R 1   32  Vdd/I 1  (1) 
 
         [0030]     In the resistance measurement apparatus  10 , if “Rex” represents a total resistance value of an external parasitic resistance existing on the exterior  60  of the silicon chip  20 , then the total value “Rex” may be expressed by the formula, 
 
 Rex=R 1 −Rtr/ 1  (2) 
 
 where the denominator of the resistance value “Rtr”, namely “1”, represents the number of the MOS transistor TR 20   1  that has been turned on. 
 
         [0031]     Subsequently, both MOS transistors TR 20   1  and TR 20   2  are turned on to measure a current “I 2 ” flowing through the resistance measurement apparatus  10 . A resistance value “R 2 ” of the combined resistor of the entire resistance measurement apparatus  10  in a state in which both MOS transistors TR 20   1  and TR 20   2  are turned on may be expressed using voltage “Vdd” and current “I 2 ” by the formula. 
 
 R 2 =Vdd/I 2  (3) 
 
         [0032]     The total resistance value “Rex” of the external parasitic resistance may be expressed in a similar manner to the above-provided Formula 2 by the formula, 
 
 Rex=R 2 −Rtr/ 2  (4) 
 
 where the denominator of the resistance value “Rtr”, namely “2”, represents the number of MOS transistors TR 20   1  and TR 20   2  that have been turned on. 
 
         [0033]     Eliminating the total resistance value “Rex” of the external parasitic resistance from the Formulas 2 and 4 results in the formula 
 
 R 1 −Rtr/ 1 =R 2 −Rtr/ 2  (5) 
 
 being true, which may be re-written as the formula. 
 
 Rtr =( R 1= R 2)×2  (6) 
 
         [0034]     Next, the resistance value “R 1 ” of the combined resistor of the entire resistance measurement apparatus  10  in a state in which only the MOS transistor TR 20   1  is turned on is calculated using the Formula 1 provided above, while the resistance value “R 2 ” of the combined resistor of the entire resistance measurement apparatus  10  in a state in which both MOS transistors TR 20   1  and TR 20   2  are turned on is calculated using the Formula 3 provided above.  
         [0035]     By substituting the calculated resistance values “R 1 ” and “R 2 ” into the above-described Formula 6, a resistance value “Rtr” is calculated for the MOS transistors TR 20   1  and TR 20   2  which have been turned on after adjusting the drain-source voltage. Then, by substituting the resistance value “Rtr” into the above-described Formula 4, the total resistance value “Rex” of the external parasitic resistance is calculated.  
         [0036]     As a result, when the total resistance value “Rex” of the parasitic resistance is smaller than a predetermined value, the MOS transistor TR 10  is turned on while the MOS transistors TR 20   1  and TR 20   2  are turned off. Subsequently, by measuring a current “I” flowing through the resistance measurement apparatus  10 , the resistance value of the combined resistor of the entire resistance measurement apparatus  10  is calculated. The resistance value of the internal resistor “Rin” formed within the silicon chip  20  is calculated by subtracting the total resistance value “Rex” of the external parasitic resistance existing on the exterior  60  of the silicon chip  20  from the calculated resistance value of the combined resistor of the entire resistance measurement apparatus  10 .  
         [0037]     Therefore, in the present embodiment, an IC chip (silicon chip  20  and package  30 ) placed on the socket  40  need not be replaced when, for instance, measuring the total resistance value “Rex” of the external parasitic resistance and then measuring the resistance value of the internal resistor “Rin”. This prevents changes in the resistance values of the contact resistors Rps and Rsb, thereby enabling resistance values of the internal resistor “Rin” to be measured in a more accurate manner.  
         [0038]     In contrast, when the total resistance value “Rex” of the parasitic resistance is greater than a predetermined value, the resistance values of the contact resistors Rps and Rsb are determined to be high. In this case, reconnection and subsequent re-measurement is performed.  
         [0039]     As seen, according to the present embodiment, the accuracy of resistance value measurement performed on the internal resistor “Rin” formed in the silicon chip  20  may be improved. Therefore, determination of good/bad products may be conducted in a more accurate manner.  
         [0040]     In addition, according to the present embodiment, it is suffice to add MOS transistors TR 10 , TR 20   1  and TR 20   2  to the inherent circuit elements of the silicon chip  20 . This enables measurement to be performed using a simpler configuration.  
       (2) SECOND EMBODIMENT  
       [0041]     A configuration of a resistance measurement apparatus  100  according to a second embodiment of the present invention is shown in  FIG. 2 . In a silicon chip  110  of the present embodiment, a MOS transistor TR 10  is serially connected to the internal resistor “Rin” to be measured, while three or more MOS transistors TR 20   1  to TR 20   n , having the same transistor characteristics, are parallel-connected to the series circuit consisting of the internal resistor “Rin” and the MOS transistor TR 10 . With the exception of the silicon chip  110 , components of the resistance measurement apparatus  100  are the same as the components shown in  FIG. 1 . Therefore, like reference numerals will be assigned thereto, and descriptions thereon will be omitted.  
         [0042]     A method for measuring a resistance value of an internal resistor “Rin”, which is a combined resistor of respective resistors formed within the silicon chip  110  to be measured, will now be described.  
         [0043]     First, in the same manner as in the first embodiment, the MOS transistor TR 10  is turned off to create a state in which the internal resistor “Rin” is not connected. Next, a drain-source voltage, i.e. the voltage “Vdd”, is adjusted so that the MOS transistors TR 20   1  to TR 20   n  respectively take a desired resistance value “Rtr” when turned on.  
         [0044]     Subsequently, the MOS transistors TR 20   1  to TR 20   n  are all turned on to measure a current “I n ” flowing through the resistance measurement apparatus  100 . A resistance value “R n ” of the combined resistor of the entire resistance measurement apparatus  100  in a state in which all MOS transistors TR 20   1  to TR 20   n  are turned on may be expressed using voltage “Vdd” and current “I n ” by the formula 
 
 Rn=Vdd/In   (7) 
 
         [0045]     In the resistance measurement apparatus  100 , if “Rex” represents a total resistance value of an external parasitic resistance existing on the exterior  60  of the silicon chip  110 , then “Rex” may be expressed by the formula, 
 
 Rex=Rn−Rtr/n   (8) 
 
 where the denominator of the resistance value “Rtr”, namely “n”, represents the number of MOS transistors TR 20   1  to TR 20   n  that have been turned on. 
 
         [0046]     Next, the MOS transistor TR 20   n  is turned off, and a current “I n−1 ” flowing through the resistance measurement apparatus  100  in a state in which MOS transistors TR 20   1  to TR 20   n−1  are turned on is measured. A resistance value “R n−1 ” of the combined resistor of the entire resistance measurement apparatus  100  in a state in which the MOS transistors TR 201  to TR 20   n−1  are turned on may be expressed using voltage “Vdd” and current “I n−1 ” by the formula. 
 
 R   n−1   =Vdd/I   n−1   (9) 
 
         [0047]     The total resistance value “Rex” of the external parasitic resistance may be expressed in a similar manner to the above-provided Formula 8 by the formula, 
 
 Rex=R   n−1   −Rtr /( n− 1)  (10) 
 
 where the denominator of the resistance value “Rtr”, namely “n−1”, represents the number of MOS transistors TR 20   1  to TR 20   n−1  that have been turned on. 
 
         [0048]     Eliminating the total resistance value “Rex” of the external parasitic resistance from the Formulas 8 and 10 results in the formula, 
 
 R   n−1   −Rtr /( n− 1)= Rn−Rtr/n   (11) 
 
 being true, which may be re-written as the formula. 
 
 Rtr =( R   n−1   −Rn )/(1/( n− 1)−1/n)  (12) 
 
         [0049]     Next, the resistance value “R n ” of the combined resistor of the entire resistance measurement apparatus  100  in a state in which all the MOS transistors TR 20   1  to TR 20   n  are turned on is calculated using the Formula 7 provided above, while the resistance value “R n−1 ” of the combined resistor of the entire resistance measurement apparatus  100  in a state in which the MOS transistors TR 20   1  to TR 20   n−1  are turned on is calculated using the Formula 9 provided above.  
         [0050]     By substituting the calculated resistance values “R n ” and “R n−1 ” to the above-described Formula 12, the resistance value “Rtr” is calculated for the MOS transistors TR 20   1  to TR 20   n  which have been turned on after adjusting the drain-source voltage. Then, by substituting the resistance value “Rtr” to the above-described Formula  10 , the total resistance value “Rex” of the external parasitic resistance is calculated.  
         [0051]     As a result, when the total resistance value “Rex” of the parasitic resistance is smaller than a predetermined value, the MOS transistor TR 10  is turned on while the MOS transistors TR 20   1  to TR 20   n  are turned off. Subsequently, by measuring a current “I” flowing through the resistance measurement apparatus  100 , the resistance value of the combined resistor of the entire resistance measurement apparatus  100  is calculated. The resistance value of the internal resistor “Rin” formed within the silicon chip  110  is calculated by subtracting the total resistance value “Rex” of the external parasitic resistance existing on the exterior  60  of the silicon chip  110  from the calculated resistance value of the combined resistor of the entire resistance measurement apparatus  100 .  
         [0052]     Therefore, in the present embodiment, an IC chip (silicon chip  110  and package  30 ) placed on the socket  40  need not be replaced when, for instance, measuring the resistance value of the internal resistor “Rin”, as was the case with the first embodiment. This prevents changes in the resistance values of the contact resistors Rps and Rsb, thereby enabling resistance values of the internal resistor “Rin” to be measured in a more accurate manner.  
         [0053]     In contrast, when the total resistance value “Rex” of the parasitic resistance is greater than a predetermined value, the resistance values of the contact resistors Rps and Rsb are determined to be high. In this case, reconnection and subsequent re-measurement is performed.  
         [0054]     As seen, according to the present embodiment, the accuracy of resistance value measurement performed on the internal resistor “Rin” formed in the silicon chip  110  may be improved. Therefore, determination of good/bad products may be conducted in a more accurate manner, as was the case with the first embodiment.  
         [0055]     As performed in the present embodiment, by respectively parallel-connecting three or more MOS transistors TR 20   1  to TR 20   n  to a series circuit consisting of an internal resistor “Rin” and a MOS transistor TR 10 , accuracy of resistance value measurement performed on the internal resistor “Rin” may be further improved in comparison to the first embodiment in which two MOS transistors TR 20   1  and TR 20   2  are parallel-connected, even in the event that the resistance values “Rtr” of the MOS transistors TR 20   1  to TR 20   n , which have been turned on, are dispersed.  
         [0056]     A relationship between a number of MOS transistors TR 20   1  to TR 20   n  which have been turned on, and a current value “I” flowing through a resistance measurement apparatus  100  is shown in  FIG. 3 . As shown, when the total resistance value “Rex” of the external parasitic resistance is significantly smaller than the resistance value “Rtr” of the MOS transistors TR 20   1  to TR 20   n  which have been turned on, a graph G 1  resembles a straight line.  
         [0057]     In contrast, when the total resistance value “Rex” of the external parasitic resistance is significantly greater than the resistance value “Rtr”, a graph G 2  resembles a curved line. The rate of increase of the current value “I” is reduced even when the number of MOS transistors TR 20   1  to TR 20   n  to be turned on is increased.  
         [0058]     Therefore, for instance, when performing a test to merely determine whether the total resistance value “Rex” of the external parasitic resistance is greater than a predetermined value, such a test may be performed in a simple manner based on the curvature of the graphs shown in  FIG. 3 , without having to measure the total resistance value “Rex” of the external parasitic resistance.  
         [0059]     The above-described embodiments are merely examples, and therefore do not limit the present invention. For instance, the method of measuring a resistance value of internal resistors “Rin”, formed within the silicon chips  20  and  110  to be measured, may be used when executing wafer tests instead of final tests.