Abstract:
An apparatus for a digital video tape recorder for detecting a sync signal in digital data includes: a data restoring device for producing serial data and a serial clock signal received from a reproducing head of the digital video tape device; a servo device for producing a head switching pulse and a super-video home system (S-VHS)/video home system (VHS) discriminating signal; an identification detecting device for producing a signal indicative of an end of reading one segment of tracks; and a sync signal detecting device, responsive to each signal produced by the aforementioned devices, for determining correspondence in sync patterns even in a case where not all corresponding bits coincide with one another, for removing erroneously detected sync patterns using a window situated around a position at which a sync signal is produced, and for detecting a sync signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an apparatus in a digital video tape recorder (DVTR) for detecting a sync signal in digital data. More particularly, the present invention relates to an apparatus for the detection of a sync signal in serial data which has been reconstituted from parallel data. Such an apparatus facilitates recovery from the slip-off of synchronization of bits, and enables the detection of sync patterns with less circuitry than that of a sync detection system operating at a parallel data rate. 
     U.S. Pat. No. 4,275,466 discloses a sync detection scheme in which circuitry operates at a serial clock rate. Meanwhile, U.S. Pat. No. 4,879,731 discloses a system for detecting a sync signal in parallel data converted from serial data. 
     FIG. 1 is a block diagram of conventional sync detection circuitry operating at a serial data rate. FIG. 2 is a waveform diagram for explaining the operation of the system shown in FIG.  1 . FIG. 3 is a block diagram of another conventional sync detection system operating at a parallel data rate. 
     Referring to FIG. 1, data signal S D  is applied to a predetermined sync pattern matching means  15  operative to detect when a bit pattern in a shift register corresponds to a predetermined sync bit pattern that is supposed to be recorded once in each of the successive blocks of N bits recorded on a recording medium. The sync pattern matching means  15  generates a detected sync signal Si whenever such a correspondence is detected. A pulse signal PG indicates the reading of a track has begun, and a signal SM is a search-mode setting signal. The signal SM attains a high level upon receipt of the signal PG, and then attains a low level once the signal Si is generated to thereby search an initial sync signal Sync. 
     The sync signal Sync serves as a clear signal to a counter  22  so that the counter  22  is cleared by an output of an OR gate  18  each time a sync signal is generated. Once cleared, the counter  22  continues counting reference pulses P R . The counter  22  repeatedly counts the output of the OR gate  18  from 0 to N−1 in response to the pulses of reference pulse signal P R , and an AND gate  23  supplied a counted sync signal S 1 . That is to say, the counter  22  counts the output of the OR gate  18  to produce a sync signal, and when the count of N counter  22  attains a value of N−1, the AND gate  23  supplies a counted sync signal S 1 . CM indicates a check mode signal. The CM signal becomes a high signal when the detected sync signal Si does not correspond to the counted sync signal S 1 , and attains a low level every time an output Sc of a comparator  35  is produced. When all the signals Si, CM and Sc attain a high level, they are recognized as sync signals. 
     This system requires proper re-alignment of the data for the recovery from the slip-off synchronization of bits, but only performs the delay propagation of serial data. This gives rise to a disadvantageous problem in subsequent data processing. 
     FIG. 3 is a block diagram of a sync detection system performed at a parallel data rate. This system includes a converting means  51  that receives serial digital data and a serial clock signal from a reproducing head of a digital tape recorder. The converting means  51  converts this data into a parallel form, and generates a parallel clock signal that is provided to other parts of the circuit. 
     It is assumed that a sync pattern of this type may have any one of eight different positions or alignments in the parallel data stream. A detecting means  52  detects the sync pattern in one of these eight alignments. Whenever a sync pattern is detected, the detecting means  52  produces a sync signal and a position signal indicating the particular alignment detected. A comparing means  52  calculates the difference between the situation where a sync pattern is detected and where it is expected on the basis of the previous sync pattern. This system is different from the one operating at a serial data rate in comparing the actual position with an expected position indicated by an expected position signal. This parallel-data sync detection needs N comparators (not illustrated) in the comparing means  53  in the situation where M−N modulation-demodulation is being performed, and when a detected sync signal is generated from one of the N comparators, re-aligned data and a final sync signal are produced by means of an encoder (not illustrated) and a decoder (not illustrated). 
     When a sync slip occurs before and after a position at which a sync signal is detected, by using a first signal generating means  54  and a third signal generating means  56 , a SYNC-IN-WINDOW signal is moved forward and backward. The decoder of the comparing means  53 , the first signal generating means  54 , and the third signal generating means  56  should employ N multiplexers, an adder (not shown), and a memory (not shown), respectively, which results in a complicated circuitry arrangement. 
     In the sync detection circuit operating at a parallel data rate, the sync patterns in a data bit stream that are recorded in serial form become an important factor, and may be impaired by damage to a tape, degradation of signals, or errors in the rotational speed of drums, all of which make sync detection difficult. Besides, there may occur errors in data patterns, as well as a lack of coincidence between clock signals of sync patterns. The serial-data sync detection has a problem in that synchronization errors adversely affect the correction of sync slip in bit positions. 
     The sync detection system performing at a parallel data rate has a first step for converting the incoming serial data to parallel data without regard to proper alignment. Sync detection is then performed upon the parallel data at the parallel data rate, and the parallel data is shifted into its original alignment, using the position of the detected sync patterns as a guide. Such a sync detection scheme reduces the need for high speed logic and facilitates correction for the slip-off of the synchronization of bits. This scheme, however, is difficult to carry out in large scale integration. 
     SUMMARY OF THE INVENTION 
     There is a need for an apparatus in a digital video tape recorder according to which sync detection and data alignment may be performed at a serial clock rate, thus correcting synchronization errors using a predetermined window situated around the expected position of the sync signal, and providing a proper response to the displacement or absence of sync signals, while at the same time, reducing circuitry as compared to that of the sync detection system operating at a parallel data rate. 
     With this in mind, the present invention relates to an apparatus in a digital video tape recorder for detecting a sync signal in digital data, comprising: data restoring means for producing serial data and a serial clock signal received from a reproducing head of the digital video tape recorder; servo means for producing a head switching pulse and a super-video home system (S-VHS)/video home system (VHS) discriminating signal; identification detecting means for producing a signal indicative of an end of reading one segment of tracks; and sync signal detecting means, responsive to each signal produced by the aforementioned means, for determining correspondence in sync patterns even in a case where not all corresponding bits coincide with one another, for removing erroneously detected sync patterns using a window situated around a position at which a sync signal is produced, and for detecting a sync signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of conventional sync detection system operating at a serial data rate; 
     FIG. 2 is a waveform diagram for explaining the operation of the system shown in FIG. 1; 
     FIG. 3 is a block diagram of a conventional sync-detection system operating at a parallel data rate; 
     FIG. 4 depicts a sync block in one general segment; 
     FIGS. 5A and 5B are data formats that are recorded on a tape of a super-video home system (S-VHS) and on a tape of a video home system (VHS), respectively; 
     FIG. 6 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 7 is a preferred implementation of the sync signal detecting means of FIG. 6; 
     FIG. 8 is a preferred implementation of the track-initial portion recognition signal generating means of FIG. 7; 
     FIG. 9 is a preferred implementation of the block sync signal detecting means of FIG. 7; 
     FIG. 10 is a preferred implementation of the window processing means of FIG. 9; 
     FIG. 11 is a preferred implementation of the clock converting means of FIG. 7; 
     FIG. 12 is a preferred implementation of the data aligning means of FIG. 7; 
     FIG. 13 is a timing diagram showing the relation of track-initial portion recognition signal, block sync signal and aligned data; and 
     FIGS. 14A through 14H are waveform diagrams of various signals relating to the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. 
     Prior to discussing the present invention, a data format recorded on a tape and a sync clock will be described. In this regard, FIG. 4 shows a sync block in one segment that includes a block sync pattern of 2 sync bytes, a block ID (identification) of 1 sync byte, shuffled data of 104 sync bytes, and parity of 8 sync bytes. 
     FIG. 5A is a data format recorded on an S-VHS tape and FIG. 5B is a data format recorded on a VHS tape. The lined part therein is indicative of a dummy data recording region and the other part therein indicates an effective data recording region. 
     FIG. 6 is a block diagram of a preferred embodiment of the present invention having a data restoring means  200  that restores data and a clock recorded on a tape and that transfers them to a sync signal detecting means  100 , a servo means  300  that transmits a head switching pulse HSP each time a track is changed and an S-VHS/VHS discriminating signal S/V for discriminating S-VHS from VHS, and a demodulating means  400  that retrieves original signals from the data recorded on the tape produced from the sync signal detecting means  100 . 
     The sync detection system also includes an identification (ID) detecting means  500  that transmits a segment-end signal Seg-end to indicate that one segment of a given track is finished. The sync signal detecting means  100  produces n-bit data, a first clock signal clk 1 , a signal Isync indicating the reading of an initial portion of a given track, and a block sync signal Bsync, in response to a sync pattern, on the basis of the above signals. 
     FIG. 7 is a preferred implementation of the sync signal detecting means  100 . Preferably, the sync signal detecting means  100  includes a track-initial portion recognition signal generating means  110 , a block sync signal detecting means  120 , a clock converting means  130  producing first and second clock signals clk 1  and clk 2 , respectively, and a data aligning means  140  that produces final data in response to the sync pattern. The track-initial portion recognition signal generating means  110  produces the signal Isync that is indicative of the reading of an initial portion of a given track, by using the head switching pulse HSP and S/V signal from the servo means  300  and the first clock signal clk 1  from the clock converting means  130 . 
     The block sync signal detecting means  120  produces a final block sync signal Bsync by using the serial data Sdata and the serial clock signal Sclk from the data restoring means  200 , and the first clock signal clk 1  from the clock converting means  130 . The clock converting means  130  produces first and second clock signals clk 1  and clk 2  in response to the serial clock signal Sclk and a matched block sync signal Bsync matched in a window in response to a predefined sync pattern. 
     The data aligning means  140  produces final data in response to the sync pattern by using the first and second clock signals clk 1  and clk 2  from the clock converting means  130  and the serial clock signal Sclk from the data restoring means  200 . The track-initial portion recognition signal generating means  110  includes an S-VHS discriminator  111 , a VHS discriminator  112 , and a track recognition signal selector or track-initial portion recognition signal selector  113 , as shown in FIG.  8 . Through these means, a signal Isync indicating the reading of the initial portion of a given track in a S-VHS tape and a signal Isync indicating the reading of the initial portion of a given track in a VHS tape, are detected. In the case where the S-VHS/VHS discriminating signal S/V produced from the servo means  300  attains a high level or a low level, S-VHS or VHS are selected, respectively. 
     The S-VHS discriminator  111  produces the Isync signal indicative of reading the initial portion of every given track in an S-VHS tape by using the head switching pulse HSP and first clock signal clk 1 , and generates the Isync signal indicative of reading the initial portion of a given track every two tracks. The track recognition signal selector  113  selects an output of the S-VHS discriminator  111  in the case where the S-VHS/VHS discriminating signal S/V attains a high level, and selects an output of the VHS discriminator  112  in the case where the incoming S-VHS/VHS discriminating signal S/V attains a low level. 
     FIG. 9 shows components of the block sync signal detecting means  120 . With reference to FIG. 9, the block sync signal detecting means  120  includes first and second pattern match detecting means  121  and  122 , and AND gate AND 1 , a matched block sync signal detecting means  123 , a BSYNC 1  detecting means  124 , a window processing means  125 , and a final block sync signal detecting means  126 . 
     The block sync signal detecting means  120  produces a final block sync signal Bsync. The block sync signal detecting means  120  matches and detects a block sync signal at a serial data rate, and recognizes the block sync signal if it occurs within a predetermined window around the expected position of the sync signal. The block sync signal detecting means  120  converts the serially-matched block sync signal into a block sync signal having a width of the first clock signal clk 1 , and produces a final block sync signal Bsync by means of a window. 
     The first and second pattern match detecting means  121  and  122  each receive the serial data and serial clock signal Sclk, and MSB 6 bits of the data are detected from each expected position of them. Other bits than MSB 6 bits are detected to a maximum of 4 bits, even if errors occur. The AND gate AND 1  receives outputs generated from the first and second pattern match detecting means  121  and  122 . The matched block sync signal detecting means  123  processes an output of the AND gate AND 1  with a predetermined window to generate a matched block sync signal, namely, matched Bsync, that may be used as a clear signal of the second clock signal clk 2 . 
     The BSYNC 1  detecting means  124  converts the output of the AND gate AND 1  into the block sync signal BSYNC 1  having the width of the first clock signal clk 1 , and processes it with a predetermined window so that the output signal therefrom may be recognized as a final block sync signal Bsync. The window processing means  125  receives the Isync signal, the Seg-end signal from the ID detecting means  500 , and the first clock clk 1  to define a window so that the final block sync signal detecting means  126  removes block sync signals erroneously detected in the AND gate AND 1 . 
     As shown in FIG. 10, the window processing means  125  includes an I window processor  125 a, and N window processor  125 b, a D window processor  125 c, and an AND gate AND 2 . The I window processor  125 a generates an I window signal Iwin for detecting an initial block sync signal in a given track in response to the Isync signal, the output signal Bsync 1  of the BSYNC 1  detecting means  124 , and the first clock signal clk 1 . Receipt of the Isync signal and the Bsync signal determines a “window open” state and a “window closed” state, respectively. 
     The N window processor  125 b generates an N window signal Nwin for making the window open state or the window closed state in response to a counted value of the signals, by using as a clear signal the block sync signal Bsync 1 , the first clock signal clk 1 , and the output signal Iwin of the I window processor  125 a. The size of the N window is set by a control signal of error correct means for correcting errors at a signal-finally outputting terminal. The D window processor  125 c produces a D window signal Dwin that makes the window open for a predetermined block duration upon receipt of the Seg-end signal from the detecting means  500 , and defines the window closed state upon receipt of the block sync signal Bsync. The AND gate AND 2  outputs as a final window signal a logical product of the outputs of I, N, and D window processors  125 a to  125 c. 
     As seen from FIG. 11, the block converting means  130  has a first clock generator  131  and a second clock generator  132 . The first clock generator  131  constitutes a first clock signal clk 1  having a duty cycle of 50% by using the serial clock signal Sclk, and the second clock generator  132  produces a second clock signal having a different duty cycle every time the block sync signal Bsync is applied, by using as a clear signal the matched block sync signal from the matched block sync signal detecting means  123  with the window. 
     Referring to FIG. 12, the data aligning means  140  is composed of first, second, and third delay means  141 ,  142 , and  143 , respectively. The data aligning means  140  delays data three times to achieve data alignment. In the case of performing M-N modulation-demodulation, the first delay means  141  delays the serial data Sdata from the data restoring means  200  with the serial clock Sclk N times, and produces parallel data Pdata 1 . The second delay means  142  receives the parallel data from the first delay means  141  and delays it with the second clock signal clk 2  by using the detected block sync signal Bsync as a clear signal. Finally, the third delay means  143  latches the parallel data Pdata 2  with the first clock clk 1  having a duty cycle of 50% such that n-bit data is produced to the demodulator  400  to be retrieved as m-bit data. 
     FIG. 13 is a timing diagram showing the relation of the Isync signal, the Bsync signal, and the aligned data produced or the head switching pulse HSP basis. The Bsync signal is produced in response to the sync pattern So at the beginning of the data blocks. 
     FIGS. 14A to  14 H are waveform diagrams of signals of the present invention. FIG. 14A shows the serial data Sdata including sync patterns (high level), and FIG. 14B depicts the serial clock signal Sclk. FIG. 14C depicts the second clock signal clk 2  having a width varying with the generation of the signal of FIG.  14 E. FIGS. 14D and 14E depict the first clock signal clk 1  having a constant duty cycle and the matched block sync signal matched to the sync pattern. FIG. 14F shows parallel data latched by the serial clock signal Sclk and FIG. 14F shows parallel data produced by latching the data of FIG. 14F by the second clock clk 2  of FIG. 14C. 14H depicts final parallel data produced by latching the parallel data of FIG. 14G by the first clock clk 1  of FIG.  14 D. 
     The first and second clock signals clk 1  and clk 2  are produced in the same form before the matched block sync signal is produced and, after application of the matched block sync signal, the duty cycle of the second clock signal slk 2  is changed to be moved up at the position of the matched block sync signal. The second clock signal clk 2  has a duty cycle of 50% until the block sync signal is applied. 
     Accordingly, the data is delayed N times to be shifted to a serial clock signal at the point when the data has a different duty cycle from the original one. At this point, data alignment is achieved. After the application of the matched block sync signal, the first and second clock signals clk 1  and clk 2  have the same duty cycle but have different rising and falling edges from one another. The data that was latched by the second clock signal clk 2  is latched by the first clock signal clk 1  in the middle portion to thereby stabilize the production of the data. 
     The present invention provides an apparatus for a digital video tape recorder in which sync detection and data alignment may be performed at a serial clock rate, thus correcting synchronization errors with a predetermined window around the expected position of the sync signal, and providing a proper response to the displacement or absence of sync signals, while at the same time, reducing the amount of required circuitry as compared to that of the sync detection system operating at a parallel data rate. 
     The subject invention has been described above in terms of several specific embodiments. It will be understood, however, that these embodiments have been used merely to illustrate the principles of the invention, and it is possible that the principles of the invention could be implemented in embodiments other than those specifically described above.