Abstract:
An input circuit can minimize a circuit area required for data prefetch operation for an increased bit number of prefetch data. A control signal generating unit generats a plurality of control signals in response to a clock signal and a data strobe signal, wherein external data are input in synchronism with the data strobe signal. A synchronizing unit for aligns the input data into N-bit data in parallel by performing a data alignment operation at least three times, N being a positive integer larger than one.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a semiconductor memory device, and more particularly to a data input circuit of the semiconductor memory device.  
       DESCRIPTION OF RELATED ART  
       [0002]     Generally, a semiconductor memory device performs a data prefetch operation in order to increase data access time. The data prefetch operation is one method for internally transferring data in response to a write command. Typically, a data input circuit of the semiconductor memory device performs the data prefetch operation in synchronization with a system clock. The data input circuit prefetches some data, i.e., 2-bit data, 4 bit data and 8 bit data input in response to the write command.  
         [0003]     As the semiconductor memory device is required to operate with higher speeds, the bit number of data to be prefetched increases. Double data rate synchronized dynamic random access memories (DDR SDRAM) have evolved from a 2-bit prefetch operation is used for the data access to 4 bit prefetch operation and recently to 8 bit prefetch operation.  
         [0004]     The data input circuit commonly includes a plurality of circuits, i.e., latches whose number corresponds to the bit number of data to be prefetched.  
         [0005]      FIG. 1  is a block diagram of a prior art data input circuit for 2-bit prefetch of a semiconductor memory device.  
         [0006]     The data input circuit includes a buffer unit  10  for receiving data DQ from the external device, a synchronizing control unit  20  for generating a plurality of synchronizing control signals DSRP, DSFP and DSTROB, and a synchronizing unit  30  for synchronizing an output of the buffer unit  10  with the plurality of synchronizing control signals DSRP, DSFP and DSTROB to output aligned data DIO_ 0 R and DIO_OF.  
         [0007]     The buffer unit  10  includes a buffer  12  for receiving the data from the external device and a delay unit  14  for delaying an output of the buffer  12  for a predetermined time and providing the delayed data to synchronizing unit  30 .  
         [0008]     The synchronizing control unit  20  includes a buffer  21  for receiving a data strobe signal DQS and a reference signal VREF, a driver  22  for receiving an output of the buffer  21  to output the first and the second synchronizing control signals DSRP and DSFP, a buffer  24  for receiving a clock signal CLK and a inverted clock signal/CLK, a driver  25  for driving an output of the driver  25  to output an internal clock signal ICLK and a signal generator  26  for receiving the internal clock signal ICLK and an enable signal EN to generate the third synchronizing control signal DSTROB.  
         [0009]     The third synchronizing control signal DSTROB is generated by logically combining the internal clock signal ICLK and the enable signal EN. After 2-bit data is input into and aligned in the data input circuit, the aligned 2-bit data are synchronized with a system clock, i.e., the clock signal CLK. The enable signal EN is generated from a circuit for carrying out an operation in response to a write command and then provided to the signal generator  26 .  
         [0010]     The synchronizing unit  30  includes an alignment unit  32  for aligning outputs of the buffer unit  10  in response to the first and the second synchronizing control signals DSRP and DSFP, a domain cross unit  36  for synchronizing outputs of the alignment unit  32  with the third synchronizing control signal DSTROB to output the aligned data DIO_ 0 R and DIO_OF.  
         [0011]     The alignment unit  32  includes a first latch  33  for latching the output of the buffer unit  10  in response to the first synchronizing control signal DSRP, a second latch  34  for latching an output of the first latch  33  in response to the second synchronizing control signal DSFP and the third latch  35  for latching the output of the buffer unit  10  respectively in response to the second synchronizing control signal DSFP.  
         [0012]     The domain cross unit  36  includes a fourth latch  37  for latching an output of the second latch  34  to output the aligned data DIO_ 0 R and a fifth latch  38  for latching an output of the third latch  35  to output the aligned data DIO_OF, wherein the fourth and the fifth latches  37  and  38  perform the latching operation in response to the third synchroning control signal DSTROB.  
         [0013]      FIG. 2  is a timing diagram for an operation of the conventional data input circuit shown in  FIG. 1 .  
         [0014]     Hereinafter, the operation of the conventional data input circuit will be described referring to  FIGS. 1 and 2 .  
         [0015]     The buffer unit  10  receives data  0 R and  0 F from the external device and outputs internal data DIN. The data  0 R and  0 F are respectively input into the buffer unit  10  in a state of being synchronized with a rising timing and a falling timing of the data strobe signal DQS. The data  0 R is a first input data input into the buffer unit  10  in response to the first rising transition timing of the data strobe signal DQS. The data  0 F is a second input data input into the buffer unit  10  in response to the first falling transition timing of the data strobe signal DQS.  
         [0016]     The synchronizing control unit  20  receives the data strobe signal DQS and the reference signal VREF and generates the first and the second synchronizing control signals DSRP and DSFP, respectively being synchronized with the rising timing and the falling timing of the data strobe signal DQS.  
         [0017]     The first latch  33  of the alignment unit  32  latches the internal data DIN, i.e., the data  0 R, in response to the first synchronizing control signal DSRP. The second latch  34  latches the output of the first latch  33  in response to the second synchronizing control signal DSFP. The third latch  35  latches the internal data DIN, i.e., the data  0 F, in response to the second synchronizing control signal DSRF. That is, the sequentially input data  0 R and  0 F are latched in parallel at the second latch  34  and the third latch  35 , respectively.  
         [0018]     The synchronizing control unit  20  generates the third synchronizing control signal DSTROB synchronized with the internal clock ICLK in response to the activated enable signal EN.  
         [0019]     The enable signal EN is activated in response to a rising transition timing of the clock signal CLK when the inputting of data begins and is inactivated in response to the next rising transition timing of the clock signal CLK.  
         [0020]     The latches  37  and  38  of the domain cross unit  36  latch, respectively, the outputs F 0 _R and F 0 _F of latches  34  and  35  in response to the third synchronizing control signal DSTROB and output the aligned data DIO_ 0 R and DIO_OF, respectively. The aligned data DIO_ 0 R and DIO_OF are data aligned in synchronism with the clock signal CLK since the third synchronizing control signal DSTROB is synchronized with the internal clock signal ICLK.  
         [0021]     For reference, the word “domain crossing” means an operation for changing a referential signal to a transfer signal. In above description, the data strobe signal DQS is changed into the clock signal CLK as the referential signal for transferring data.  
         [0022]     Generally, in a DDR SDRAM, all internal operations of a core area are performed in synchronism with the clock signal CLK. Therefore, the data input circuit performs a domain crossing operation that changes the data strobe signal DQS into the clock signal CLK as the referential signal for transferring data.  
         [0023]      FIG. 3  is a block diagram of a prior art data input circuit for 4-bit prefetch of a semiconductor memory device The data input circuit includes a buffer unit  40 , a synchronizing control unit  50  and a synchronizing unit  60 . The data input circuit for 4-bit prefetch has substantially the same constitution as the data input circuit for 2-bit prefetch shown in  FIG. 1 . The number of latches arranged in the synchronizing unit  60  is greater than that of the synchronizing unit  30  in  FIG. 1 . That is because the synchronizing unit  60  latches and aligns 4-bit data input in series, which are synchronized with a rising timing or a falling timing of the data strobe signal DQS.  
         [0024]     The synchronizing control unit  50  generates the first and the second synchronizing control signals DSRP and DSFP in response to the data strobe signal DQS and the third synchronizing control signals DSTROB 2  in response to the internal clock signal ICLK. After the latching operation of a latch unit  62 , the third synchronizing control signal DSTROB 2  is generated by the synchronizing control unit  50 .  
         [0025]      FIG. 4  is a timing diagram for an operation of the data input circuit shown in  FIG. 3 .  
         [0026]     Hereinafter, the operation of the data input circuit for 4-bit prefetch will be described referring to  FIGS. 3 and 4 .  
         [0027]     The buffer unit  40  receives data input from the external device and outputs internal data DIN.  
         [0028]     The synchronizing control unit  50  receives the data strobe signal DQS and the reference signal VREF and generates the first and the second synchronizing control signals DSRP and DSFP, respectively synchronized with the rising timing and the falling timing of the data strobe signal DQS.  
         [0029]     The alignment unit  62  aligns the internal 4-bit data DIN, i.e., a first data  0 R, a second data  0 F, a third data  1 R and a fourth data  1 F transferred sequentially in synchroniism with the first and the second synchronizing control signals DSRP and DSFP into data R 0 _R, F 0 _F, F 1 _R and F 1 _F aligned as a type of two rows.  
         [0030]     The synchronizing control unit  50  receives the clock signals CLK and /CLK and generates the third synchronizing control signal DSTROB 2  in response to an enable signal EN 2 .  
         [0031]     A domain crossing unit  66  latches the R 0 _R, F 0 _F, F 1 _R and F 1 _F and outputs as a aligned data DIO_ 0 R, DIO_ 0 F, DIO_ 1 R and DIO_ 1 F in synchronism with the third synchronizing control signal DSTROB 2 .  
         [0032]     Therefore, the sequentially input 4-bit data  0 R,  0 F,  1 R and  1 F are aligned into the 4-bit aligned data DIO_ 0 R, DIO_ 0 F, DIO_ 1 R and DIO_LF by a prefetch operation of the conventional data input circuit for 4-bit prefetch as shown in  FIG. 4 .  
         [0033]     As described above, the data input circuit has a plurality of latches configured in two rows. At first, the data input circuit arranges all bit data into first data aligned one of two rows using latches and, secondly, rearranges the first data into second data aligned in parallel. The number of latches requested in order to arrange data input in series into data aligned in parallel is 2N-1+N, N being a positive integer. The 2N-1 latches are needed for the first arranging and the N latches are needed for the second arranging.  
         [0034]     If the number of data bits for the prefetch operation increases, more latches may be needed. Therefore, a greater bit number for the prefetch operation is needed and a larger area is required for the data input circuit in the semiconductor memory device. The increase of the area of the data input circuit results in rising cost for fabricating the semiconductor memory device.  
       SUMMARY OF THE INVENTION  
       [0035]     The present invention provides various embodiments for a data input circuit that can minimize a circuit area required for a prefetch operation although the bit number of data for the prefetch operation increases.  
         [0036]     In accordance with a first embodiment of the present invention, there is provided an input circuit of a semiconductor memory device for N-bit prefetch including: a control signal generating unit for generating a plurality of control signals in response to a clock signal and a data strobe signal wherein externally input data are synchronized with the data strobe signal; and a synchronizing unit for aligning the input data into N-bit data aligned in parallel through greater than three data alignment operations, wherein the N is an integer number greater than two.  
         [0037]     In accordance with a second embodiment of the present invention, there is provided an input circuit of a semiconductor memory device including: a control signal generating unit for generating a plurality of alignment control signals in response to a data strobe signal and a plurality of domain cross control signals in response to a clock signal wherein externally input data are synchronized with the data strobe signal; an alignment unit for aligning the N-bit input data into data aligned in parallel through greater than two data align operations; and a domain cross unit for synchronizing outputs of the alignment unit with the domain cross control signals to output N-bit aligned data in parallel, wherein the N is an integer number of two or greater.  
         [0038]     In accordance with a third embodiment of the present invention, there is provided an input circuit of a semiconductor memory device, including: a control signal generating unit for generating first and second alignment control signals and a plurality of domain cross control signals in response to a clock signal and a data strobe signal wherein externally input data are synchronized with the data strobe signal; an alignment unit for aligning the N-bit input data into data aligned in two rows in response to the first and the second alignment control signals; and a domain cross unit for synchronizing the data aligned by the alignment unit with the plurality of domain cross control signals through two data synchronizing operations to output N-bit aligned data in parallel, wherein N is an integer number of two or greater.  
         [0039]     In accordance with fourth embodiment the present invention, there is provided an input circuit of a semiconductor memory device for N-bit prefetch, including: a first data alignment unit for aligning and outputting a predetermined number of external N-bit data sequentially input in response to a first control signal in synchronism with a data strobe signal wherein the N-bit data input are synchronized with transition timing of the data strobe signal; a latch unit for latching an output of the data alignment unit in response to a second control signal in synchronism with a system clock; and a second alignment unit for aligning the aligned data by the data alignment unit and the latched data by the latch unit into N bit data aligned in parallel in response to a third control signal generated in synchronism with the system clock.  
         [0040]     In accordance with a fifth embodiment of the present invention, there is provided an input circuit of a semiconductor memory device for N-bit prefetch including: a data alignment unit for aligning and outputting a predetermined number of external N-bit data sequentially input; a first domain cross unit for latching an output of the data alignment unit in response to a first domain cross control signal; and a second domain cross unit for latching the aligned data by the data alignment unit and the latched data by the first domain cross unit into a N-bit data aligned in parallel in response to a second domain cross control signal.  
         [0041]     In accordance with a sixth embodiment of the present invention, there is provided a method for operating a semiconductor memory device for N-bit prefetch, including: aligning a predetermined number of M-bit data of external N-bit data sequentially input into a first M-bit data aligned in parallel using an alignment unit; latching the first M-bit data into second data; aligning the other data of the N-bit data into third data in parallel using the alignment unit; and aligning the second data and the third data into N-bit data aligned in parallel. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0042]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0043]      FIG. 1  is a block diagram of a conventional data input circuit for 2-bit prefetch of a semiconductor memory device;  
         [0044]      FIG. 2  is a timing diagram of an operation of the conventional data input circuit shown in  FIG. 1 ;  
         [0045]      FIG. 3  is a block diagram of a conventional data input circuit for 4-bit prefetch of a semiconductor memory device;  
         [0046]      FIG. 4  is a timing diagram of an operation of the data input circuit as shown  FIG. 3 ;  
         [0047]      FIG. 5  is a block diagram of a data input circuit for 8-bit prefetch of a semiconductor memory device in accordance with a specific embodiment of the present invention;  
         [0048]      FIG. 6  is a block diagram of a data input circuit for 8-bit prefetch of a semiconductor memory device in accordance with another specific embodiment of the present invention; and  
         [0049]      FIG. 7  is a timing diagram of an operation of the data input circuit shown in  FIG. 6 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0050]     Hereinafter, a data input circuit for 8-bit prefetch of a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings.  
         [0051]      FIG. 5  is a block diagram of a data input circuit for 8-bit prefetch of a semiconductor memory device in accordance with a first embodiment of the present invention.  
         [0052]     As shown in  FIG. 5 , the data input circuit for operating 8-bit prefetch includes a buffer unit  70 , a synchronizing control unit  80  and a synchronizing unit  90 .  
         [0053]     The buffer unit  70  includes a buffer  71  for receiving the data DQ from external device and a delay unit  72  for delaying an output of the buffer  71  for a predetermined time to output as an internal data DIN into the synchronizing unit  90 .  
         [0054]     The synchronizing control unit  80  includes a buffer  81  for receiving data strobe signals DQS and /DQS, a driver  82  for receiving a output of the buffer  81  to respectively output as the first and the second synchronizing control signals DSRP and DSFP, a buffer  83  for receiving a clock signals CLK and /CLK, a driver  84  for driving an output of the inverter  83  to output as an internal clock signal ICLK and a signal generator  85  for receiving the internal clock signal ICLK and an enable signal EN to generate the third synchronizing control signal DSTROB 4 .  
         [0055]     The synchronizing unit  90  includes an alignment unit  92 , a delay unit  94  and a domain cross unit  96 .  
         [0056]     The alignment unit  92  aligns the internal data DIN into data aligned in two rows. The delay unit  94  delays an output of the alignment unit  92  for a predetermined time to output into the delay unit  94 . Herein, the predetermined time is a time given for increasing insufficient operating margin that results in domain cross from a short difference between transition timing of the data strobe signal DQS and transition timing of the clock signals CLK and /CLK. For The difference is called tDQSS with reference to DDR SDRAM.  
         [0057]     The alignment unit  92  includes a total of fifteen latches. The fifteen latches of the alignment unit  92  is arranged in order to align first data input sequentially in synchronism with transition timing of the data strobe signal DQS into second data aligned in two rows.  
         [0058]     The delay unit  94  includes eight delays for delaying respectively the second data output from the alignment unit  92  to output as the third data into the domain cross unit  96 .  
         [0059]     The domain cross unit  96  includes eight latches for latching the third data output from the delay unit  94  to output 8-bit aligned parallel data DIO_ 0 F, DIO_ 1 F, DIO_ 2 F, DIO 3 F, DIO_ 0 R, DIO_ 1 R, DIO_ 2 R and DIO_ 3 R.  
         [0060]     Therefore, the data input circuit for 8-bit prefetch aligns an 8-bit data, i.e.,  0 R,  0 F,  1 R,  1 F,  2 R,  2 F,  3 R and  3 F input sequentially in synchronism with the transition timing of the data strobe signal DQS into the 8-bit aligned parallel data, i.e., DIO_ 0 F, DIO_ 1 F, DIO_ 2 F, DIO 3 F, DIO_ 0 R, DIO_ 1 R, DIO_ 2 R and DIO_ 3 R.  
         [0061]     Herein, the first and the second synchronizing control signals DSRP and DSFP are activated sequentially four times, respectively. The third synchronizing control signal DSTROB is activated after the eighth data  3 F are input into the data input circuit.  
         [0062]      FIG. 6  is a block diagram showing a data input circuit for 8-bit prefetch of a semiconductor memory device in accordance with a second embodiment of the present invention.  
         [0063]     As shown in  FIG. 6 , the data input circuit for 8-bit prefetch includes a buffer unit  100  for receiving data DQ from the external device to output as internal data DIN, a synchronizing control unit  200  for receiving data strobe signals DQS and /DQS and clock signals CLK and /CLK to generate a plurality of control signals DSRP, DSFP, DSTROB 2  and DSTROB 4  and a synchronizing unit for synchronizing an output of the buffer unit  100  with the plurality of control signals DSRP, DSFP, DSTROB 2  and DSTROB 4  to output as 8-bit aligned data, i.e., DIO_ 0 R, DIO_ 1 R, DIO_ 2 R, DIO_ 3 R, DIO_ 0 F, DIO_ 1 F, DIO 2 F and DIO_ 3 F.  
         [0064]     Herein, the synchronizing unit includes an alignment unit  300 , a first domain cross unit  400  and a second domain cross unit  500 . The synchronizing unit aligns the internal data DIN at first into aligned data in two rows and secondly into aligned data in four rows and then finally, into aligned 8-bit data in parallel. In detail, the alignment unit  300  aligns 8-bit data in series output from the buffer unit  100  into first 4-bit data in four rows and second 4-bit data in two rows in response to first and second synchronizing control signals DSRP and DSFP. The first domain cross unit  400  latches the first 4-bit data in four rows in response to a first domain cross control signals DSTROB 2 . After the first domain cross unit  400  latches the first 4-bit data, the second 4-bit data in two rows are transferred into the delay unit  340 . The second domain cross unit  500  latches the first 4-bit data output from the first domain cross unit  400  and the second 4-bit data output from the alignment unit  300  to output as the aligned 8-bit parallel data, i.e., DIO_ 0 R, DIO_ 1 R, DIO_ 2 R, DIO_ 3 R, DIO_ 0 F, DIO_ 1 F, DIO_ 2 F and DIO_ 3 F in response to a second domain cross control signal DSTROB 4 .  
         [0065]     The alignment unit  300  includes a latch unit  320  for aligning selected 4-bit data of 8-bit data output in series from the buffer unit  100  into the first 4-bit data in two rows and a delay unit  340  for receiving and delaying the first 4-bit data to output into the first domain cross unit  400 .  
         [0066]     The latch unit  320  includes seven latches  321  to  327  wherein the seven latches  321  to  327  are arranged two rows and latches, respectively, outputs of prior latches in response to the first or second synchronizing control signals DSRP and DSFP. The latch  321  and  323  latches the internal data DIN from the buffer unit  100 .  
         [0067]     In detail, the latch  321  latches the internal data DIN in response to the first synchronizing control signals DSRP. The latch  322  latches an output of the latch  321  in response to the second synchronizing control signals DSFP and outputs into the latch  324 . The latch  323  latches the internal data DIN in response to the second synchronizing control signals DSFP. The latch  324  latches an output of latch  322  in response to the first synchronizing control signals DSRP. The latch  325  latches an output of latch  323  in response to the first synchronizing control signals DSRP. The latch  326  latches an output of latch  324  in response to the second synchronizing control signals DSFP. The latch  327  latches an output of latch  325  in response to the second synchronizing control signals DSFP. That is, the latches  321 ,  324  and  325  carry out a latch operation in response to the first synchronizing control signals DSRP, respectively. The latches  322 ,  323 ,  326  and  327  carry out a latch operation in response to the second synchronizing control signals DSFP, respectively.  
         [0068]     The delay unit  340  unit includes four delays  342 ,  344 ,  346  and  348 . The four delays  342 ,  344 ,  346  and  348  delay respectively the outputs of the latches  322 ,  326 ,  323  and  327  for a predetermined time to output into the first domain cross unit  400 . The delay unit  340  can delay the data signals output from the latch unit  320  independently since the delay unit  340  has latches corresponding to signals transferred from latch unit  320 . The four delay units  342 ,  344 ,  346  and  348  use a propagation delay by a plurality of inverters or RC delay value by a resistor and a capacitor for delay operation.  
         [0069]     The first domain cross unit  400  includes four latches  420 ,  440 ,  460  and  480  for respectively latching the outputs of the fourth delays  342 ,  344 ,  346  and  348  in response to the first domain cross control signal DSTROB 2 .  
         [0070]     The second domain cross unit  500  includes eight latches  510  to  580  for respectively latching the second 4-bit data output from the fourth delays  342 ,  344 ,  346  and  348  and the first 4-bit data output from four latches  420 ,  440 ,  460  and  480  in response to the second domain cross control signal DSTROB 4 .  
         [0071]     A latch arranged in the alignment unit  300 , the first domain cross unit  400  and the second domain cross unit  500  can be a D flip-flop and contain a circuit for performing edge triggering operation.  
         [0072]     The synchronizing control unit  200  includes an alignment control unit  220  for generating the first and the second synchronizing control signals DSRP and DSFP in respective synchronism with a rising edge and a falling edge of the data strobe signal DQS and a domain cross control unit  240  for generating the first and the second domain cross control signals DSTROB 2  and DSTROB 4  in response to enable signals EN 2  and EN 4  and clock signals CLK and /CLK.  
         [0073]     The alignment control unit  220  includes a buffer  222  for receiving the data strobe signals DQS and /DQS and a driver  224  for receiving an output of the buffer  222  and generating the first and the second synchronizing control signals DSRP and DSFP.  
         [0074]     The domain cross control unit  240  includes a clock input unit  242  for receiving the clock signal CLK and the inverted clock signal /CLK and generating the internal clock ICLK and a domain cross control signal generating unit  244  for generating a first domain cross control signal DSTROB 2  in synchronism with the internal clock ICLK in response to enable signals EN 2  and a second domain cross control signal DSTROB 4  in synchronism with the internal clock ICLK in response to enable signals EN 4 .  
         [0075]     The clock input unit  242  includes a buffer  242   a  for receiving the clock signal CLK and the inverted clock signal /CLK and a driver  242   a  for receiving an output of the buffer  242   a  and generating the internal clock ICLK.  
         [0076]     The domain cross control signal generating unit  244  includes a first generating unit  244   a  for generating the first domain cross control signal DSTROB 2  in synchronism with the internal clock ICLK in response to the enable signal EN 2  and a second generating unit  244   b  for generating the second domain cross control signal DSTROB 4  in synchroniism with the internal clock ICLK in response to the enable signal EN 4 .  
         [0077]     The first generating unit  244   a  performs a logical operation of the internal clock ICLK and the enable signals EN 2  to generate the first domain cross control signal DSTROB 2 . The second generating unit  244   b  performs a logical operation of the internal clock ICLK and the enable signal EN 4  to generate the second domain cross control signal DSTROB 4 .  
         [0078]     The enable signals EN 2  and EN 4  are generated by a control circuit performing an operation in response to a write command and are activated and inactivated in response to the internal clock signal ICLK.  
         [0079]      FIG. 7  is a timing diagram illustrating an operation of the data input circuit as shown  FIG. 6 . Hereinafter, the data input circuit for 8-bit prefetch in accordance with the second embodiment of the present invention will be described referring to  FIG. 6  and  FIG. 7 .  
         [0080]     Herein, ‘R’ and ‘F’ in  FIG. 7  are abbreviations to distinguish data input respectively in synchronism with a rising edge and a falling edge of the data strobe signal DQS. The natural number in front of ‘R’ and ‘F’ in  FIG. 7  means input order of data.  
         [0081]     As shown in  FIG. 7 , at first data are sequentially input into the input buffer unit  100  in synchroniism with the rising edge and the falling edge of the data strobe signal DQS.  
         [0082]     The input buffer  100  receives the external data input and outputs the same as internal data DIN.  
         [0083]     The alignment control unit  220  generates the first and the second synchronizing control signals DSRP and DSFP, respectively, in synchronism with a rising edge and a falling edge of the data strobe signal DQS. Since the second embodiment of the present invention receives 8-bit data, the first and the second synchronizing control signals DSRP and DSFP have four transition times, respectively.  
         [0084]     The latch unit  320  of the alignment unit  300  latches first 4-bit data of the input 8-bit data in two rows in response to the first and the second synchronizing control signals DSRP and DSFP. That is, the latch unit  320  latches 4-bit data, i.e.,  0 R,  0 F,  1 R and  1 F input sequentially in two rows using the latches  321  to  327  in response to the first and the second synchronizing control signals DSRP and DSFP.  
         [0085]     The delay unit  340  delays the latched data, i.e.,  0 R,  0 F,  1 R and  1 F by the latches  322 ,  326 ,  323  and  327  to output as the output F 0 _R, F 1 _R, F 0 _R and F 1 _F into the first domain cross unit  400 .  
         [0086]     In addition, the domain cross control unit  240  generates the first domain cross control signal DSTROPB 2  in synchronism with the internal clock signal ICLK when the enable signal EN 2  is activated in response to the input timing of fourth data, i.e.,  1 F.  
         [0087]     The first domain cross unit  400  latches the output F 0 _R, F 1 _R, F 0 _R and F_F of the delay unit  340  to output as the output D_ 1 R, D_ 0 R, D_ 1 F and D_ 0 F in response to the first domain cross control signal DSTROPB 2 . Therefore, 4-bit data, i.e.,  0 R,  0 F,  1 R and  1 F input sequentially are aligned as 4-bit data in parallel by the first domain cross unit  400 .  
         [0088]     While the first 4-bit data of the 8-bit data sequentially input are latched at the first domain cross unit  400 , the latch unit  320  of the alignment unit  300  latches the other 4-bit data of the input 8-bit data in two rows in response to the first and the second synchronizing control signals DSRP and DSFP. That is, the latch unit  320  latches 4-bit data, i.e.,  2 R,  2 F,  3 R and  3 F input sequentially in two rows using the latches  321  to  327  in response to the first and the second synchronizing control signals DSRP and DSFP.  
         [0089]     The delay unit  340  delays the latched data, i.e.,  2 R,  2 F,  3 R and  3 F by the latches  322 ,  326 ,  323  and  327  to output as the output F 0 _R, F 1 _R, F 0 _R and F 1 _F.  
         [0090]     In addition, the domain cross control unit  240  generates the second domain cross control signal DSTROPB 4  in synchronism with the internal clock signal ICLK when the enable signal EN 4  is activated in response to the input timing of eighth data, i.e.,  3 F.  
         [0091]     The second domain cross unit  500  latches the output D_ 1 R, D_ 0 R, D_ 1 F and D_ 0 R of the first domain cross unit  400  to output as the output DIO_ 1 R, DIO_ 0 R, DIO_ 1 F and DIO_ 0 F and latches the output F 0 _R, F 1 _R, F 0 _F and F 1 _F of the delay unit  340  to output as the output DIO_ 2 F, DIO_ 3 F, DIO_ 2 R and DIO_ 3 R in response to the second domain cross control signal DSTROPB 4 . Therefore, 8-bit data, i.e.,  0 R,  0 F,  1 R,  1 F,  2 R,  2 F,  3 R and  3 F input sequentially are aligned as 8-bit data in parallel by the second domain cross unit  500 .  
         [0092]     As described above, the data input circuit for 8-bit prefetch in accordance with a second embodiment of the present invention has two domain cross unit  400  and  500 , and performs domain crossing operation twice. The first domain cross unit  400  aligns first 4-bit data of the input 8-bit data into the aligned 4-bit data in parallel in synchronism with the reference signal, i.e., the first domain cross control signal DSTROB 2 . The second domain cross unit  500  aligns the next 4-bit data of the input 8-bit and the aligned 4-bit data in the first domain cross unit  400  into the aligned 8-bit data in parallel in synchronism with the reference signal, i.e., the second domain cross control signal DSTROB 2 .  
         [0093]     Because domain cross operation is performed twice, the number of latches in the alignment unit  300  can be reduced. In detail, the data input circuit for 8-bit prefetch in accordance with a first embodiment of the present invention has fifteen latches to align 8-bit data in series into 8-bit data in two rows. However, the data input circuit for 8-bit prefetch in accordance with a second embodiment of the present invention has only seven latches to align 4-bit data in series into 4-bit data in two rows. The alignment unit  300  aligns only 4-bit data in series of the input 8-bit data into 4-bit data in parallel with two domain crossing operations. Therefore, eight latches of the input circuit are no longer required.  
         [0094]     In addition, with two domain crossing operations, the four additional latches  420 ,  440 ,  460  and  480  of the first domain cross unit  400  are needed as compared with that of the first embodiment.  
         [0095]     Although these four additional latches are required, the total number of latches required in the data input circuit for 8-bit prefetch can be reduced. That is, the total number of latches changes  23  latches in the first embodiment to 19 latches in the second embodiment.  
         [0096]     As the total number of latches is reduced, the area of the data input circuit for 8-bit prefetch can be reduced. As a result, the cost of the semiconductor having the input circuit for 8-bit prefetch can be cut down.  
         [0097]     Although it is disclosed about the data input circuit for 8-bit prefetch in described above, it is possible to use various alternatives, modifications and equivalents. For example, those skilled in the art appreciate that the data input circuits for 4-bit prefetch, 16-bit prefetch or 32-bit prefetch can be employed in the context of any type of semiconductor memory device, or can be modified in the bit number for appropriately dividing an input entire data or can be modified in which control signal is selected for twice or more domain cross operation.  
         [0098]     The present application contains subject matter related to Korean patent application No. 2005-90919 and 2006-26260 in the Korea Patent Office on Sep. 29, 2005 and Mar. 22, 2006 respectively, the entire contents of which being incorporated herein by reference.  
         [0099]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.