Abstract:
A method for demodulating a square root is disclosed. The demodulation comprises the following steps. First, define |large| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by the inequalities 16|small|≦16|large|≦18|small| and 16|large|=16|small|. In addition, define a second determining form by the inequalities 16|small|≦16|large|≦18|small| and 16|large|≠16|small|. When the relation between |large| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2 −5 |large|. When the relation between |large| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2 −6 |large|.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method and apparatus for demodulating a square root. More particularly, the present invention relates to a method and apparatus used by a digital system or a signal communication system for demodulating a square root.  
         [0003]     2. Description of the Related Art  
         [0004]     In as very large scale integrated circuit (VLSI) digital system or a signal communication system, two input signals I and Q are often modulated into {square root}{square root over (I 2 +Q 2 )}. In other words, the input values I and Q are combined to form a square root of the sum of squares. To obtain an accurate value of the square root, lots of hardware is required. Moreover, the performance of hardware is usually poor and the processing time is usually long. Hence, hardware circuits are not too suitable for the real-time computation of square roots. To resolve this problem, methods and apparatus for finding an approximate solution such as the coordinate rotation digital computer (CORDIC), the angular cone approximate wave envelop inspection method and circuits and so on have been developed.  
         [0005]     In Taiwan Patent No. 480,415, a square root demodulation apparatus is disclosed. In the invention, a coordinate slicing theory is utilized to obtain an approximate square root of two input signals I and Q. Although the patent is capable of resolving the aforementioned problems, too many comparators must be used to obtain the solution. Therefore, the required integrated circuit is large and its production cost is high.  
         [0006]      FIG. 1  is a table listing the relation between angle and error ratio for the aforementioned Taiwan Patent No. 480,415. As shown in  FIG. 1 , the error ratios within some range of phase angles (the ones inside the circles) for the input signals I and Q are large. For example, the error ration when the angle is 76° is as high as 3.00303%. This error ratio is quite significant in a communication system or other digital computation system having a narrow tolerance for errors.  
       SUMMARY OF THE INVENTION  
       [0007]     Accordingly, at least one objective of the present invention is to provide a method for demodulating a square root to provide an approximate square root with a very small error ratio.  
         [0008]     At least a second objective of the present invention is to provide an apparatus having the simplest hardware structure for demodulating a square root to provide an approximate square root.  
         [0009]     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for demodulating a square root. The method utilizes a formula aX+bY to find an approximate square root solution of two input values I and Q. Here, X=|I|, Y=|Q|, and a and bare the coefficients of X and Y respectively. The method of demodulating the square root according to the present invention includes the following steps. First, define |large| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by a pair of inequalities A|small|≦A|large|≦B|small| and A|large|=B|small|. In addition, define a second determining form by another pair of inequalities A|small|≦A|large|≦B|small| and A|large|≠B|small|. Here, A and B are positive numbers. When the relation between |large| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2 −5 large|. When the relation between |large| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values land Q is |large|+2 −6 large|.  
         [0010]     The coefficient A and the coefficient B in the first determining form and the second determining form are 1 and 1.15 respectively. To simplify the hardware structure, the floating-point computation is converted to a fixed-point computation so that the value of coefficient A is set to 16 and the value of coefficient B is set to 18.  
         [0011]     In addition, define a third determining form by a pair of inequalities C|small|≦D|large|≦E|small| and F|small|≦D|large|≦G|small|, and then define a fourth determining form by another pair of inequalities C|small|≦D|large|≦E|small| and F|small|&gt;D|large|&gt;G|small|. Here, C, D, E, F and G are positive constants. When the relation between |large| and |small| conforms to the third determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2 −5 |large|. When the relation between |large| and |small| conforms to the fourth determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2 −6 |large|.  
         [0012]     The values of the coefficients C, D, E, F and G in the third and the fourth determining form are 3.07, 1, 6.3, 3.48 and 4.7 respectively. Similarly, to simplify the hardware structure, the values of C, D, E, F and G are set to 12, 4, 25, 14 and 19 respectively.  
         [0013]     Furthermore, when the relation between |large| and |small| does not conform to the first, the second, the third and the fourth determining form, a comparison formula ⅞|large+½|small∥ is defined. Thereafter, the value of |large| is compared with the value found by the comparison formula. The larger one of the two is the approximate root-mean-square value of the input values I and Q.  
         [0014]     The present invention also provides an apparatus for demodulating a square root. The apparatus comprises a compare absolute value circuit capable of receiving at least two input values I and Q. The compare absolute value circuit performs a comparison between the absolute value of the two input values I and Q to find the larger and the smaller value. The compare absolute value circuit also has a larger value output terminal and a smaller value output terminal. The larger value output terminal is used for outputting the larger one between the input values I and Q, also defined to be |large|. Similarly, the smaller value output terminal is used for outputting the smaller one between the input values I and Q, also defined to be |small|. The apparatus also comprises a multiplier for receiving the value sent from the larger value output terminal and the smaller value output terminal, multiplying the absolute value of I and Q by a plurality of preassigned values and then outputting the final value. The apparatus also comprises a compare/compensate circuit having a first input terminal, a second input terminal and a computation input terminal. The first input terminal is coupled to the larger value output terminal, the second input terminal is coupled to the smaller value output terminal and the computation input terminal is coupled to the output terminal of the multiplier. In addition, the compare/compensate circuit has an approximate value output terminal for outputting the approximate root-mean-square value of the two input values I and Q. When the multiplier outputs A|large| and B|small| and the compare/compensate circuit discovers that the relation between the two conforms to a first determining form embodied in a pair of inequalities A|small|≦A|large|≦B|small| and A|large|=A|small|, the compare/compensate circuit outputs a value |large|+2 −5 |large| from the approximate output terminal. Here, A and B are positive numbers. On the other hand, when the relation between A|large| and B|small| conforms to a second determining form embodied in another pair of inequalities A|small|≦A|large|≦B|small| and A|large|≠A|small|, the compare/compensate circuit outputs a value |large|+2 −6 |large| from the approximate output terminal.  
         [0015]     In one embodiment of the present invention, the coefficient A and the coefficient B in the first determining form and the second determining form are 1 and 1.15 respectively. To simplify the hardware structure, the value of coefficient A is set to  16  and the value of coefficient B is set to 18.  
         [0016]     When the multiplier outputs D|large|, C|small|, E|small|, F|small|, G|small| and the compare/compensate circuit discovers that the relation between them conforms to a third determining form embodied by a pair of inequalities C|small|≦D|large|≦E|small| and F|small|≦D|large|≦G|small|, where C, D, E, F and G are positive numbers, the compare/compensate circuit outputs a value |large|+2 −5 |large| from the approximate output terminal. On the other hand, when D|large|,C|small|,E|small|,F|small| and G|small| conforms to a fourth determining form embodied by another pair of inequalities C|small|≦D|large|≦E|small| and F|small|&gt;D|large|&gt;G|small|, the compare/compensate circuit outputs a value |large|+2 −6 |large| from the approximate output terminal.  
         [0017]     In one embodiment of the present invention, the values of the coefficients C, D, E, F and G in the third and the fourth determining form are 3.07, 1, 6.3, 3.48 and 4.7 respectively. Similarly, to simplify the hardware structure, the values of C, D, E, F and G are set to 12, 4, 25, 14 and 19 respectively.  
         [0018]     In brief, the present invention provides fourth determining forms for deciding whether the input values I and Q fall within the range of angles having a large error ratio. If the input values I and Q do fall within the range of angles having a large error ratio, the present invention provides two approximate solutions to reduce the error ratio. Furthermore, only simple devices such as shifters, multipliers and comparators are deployed to construct the apparatus for finding an approximate value to {square root}{square root over (I 2 +Q 2 )}. Hence, the cost of for producing the apparatus is reduced.  
         [0019]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0021]      FIG. 1  is a table listing the relation between angle and error ratio for the aforementioned Taiwan Patent No. 480,415.  
         [0022]      FIG. 2  is a block diagram showing the major components within an apparatus for demodulating a square root according to one preferred embodiment of the present invention.  
         [0023]      FIG. 3  is a block diagram showing the external connections of the compare/compensate circuit according to one preferred embodiment of the present invention.  
         [0024]      FIG. 4  is a block diagram showing the major components within the compare/compensate circuit according to one preferred embodiment of the present invention.  
         [0025]      FIG. 5  is a graph showing the basic concept behind the method of demodulating a square root when the input values are I and Q.  
         [0026]      FIG. 6  is a flow diagram showing the steps in demodulating a square root according to one preferred embodiment of the present invention.  
         [0027]      FIG. 7  is a table listing the relation between angle and error ratio deploying the method according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0029]      FIG. 2  is a block diagram showing the major components within an apparatus for demodulating a square root according to one preferred embodiment of the present invention. As shown in  FIG. 2 , the output terminals of the compare absolute value circuit  210  are coupled to a multiplier  220  and a compare/compensate circuit  230 . The output terminal of the multiplier  220  is coupled to the compare/compensate circuit  230 . The compare/compensate circuit  230  generates an approximate root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q according to the outputs from the compare absolute value circuit  210  and the multiplier  220 .  
         [0030]     The compare absolute value circuit  210  has a larger value output terminal  21  and a smaller value output terminal  23 . After receiving the input values I and Q, the compare absolute value circuit  210  converts the input values I and Q into absolute values. Thereafter, the absolute values of I and Q are compared and the larger absolute value is defined as |large| and output via the larger value output terminal  21  while the smaller absolute value is defined as |small| and output via the smaller value output terminal  23 . The larger value output terminal  21  and the smaller value output terminal  23  are coupled to the multiplier  220  and the compare/compensate circuit  230 . The output from the multiplier  220  is sent to the compare/compensate circuit  230 . According to the outputs from the compare absolute value circuit  230  and the multiplier  220 , the compare/compensate circuit  230  provides an approximate root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q through an approximate value output terminal  25 .  
         [0031]      FIG. 3  is a block diagram showing the external connections of the compare/compensate circuit according to one preferred embodiment of the present invention. As shown in  FIG. 3 , the compare/compensate circuit  230  has a plurality of computational input terminals  31 . In the present embodiment, the computational input terminals  31  are connected to the output terminal of the multiplier  220 , for example. In an alternative embodiment, the multiplier may have a plurality of multiplier output terminals coupled to the computational input terminals of the compare/compensate circuit. After receiving |large| and |small| from the compare absolute value circuit  210 , the multiplier  220  multiplies them with different assigned values before outputting to the computational input terminals of the compare/compensate circuit  230 . For example, the value received by the computational input terminal  31  is four times |large| or 4|large|. According to the output from the larger value output terminal  21 , the smaller value output terminal  23  and the value received at the computational input terminal, the compare/compensate circuit  220  outputs an approximate root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q to an approximate value output terminal  25 .  
         [0032]      FIG. 4  is a block diagram showing the major components within the compare/compensate circuit according to one preferred embodiment of the present invention. The internal structure of the compare/compensate circuit as illustrated in  FIG. 4  is just an example and should by no means limit the circuit as such. As shown in  FIG. 4 , all the computational input terminals of the compare/compensate circuit  230  are coupled to the comparator  403 . The comparator  403  performs a comparison of all the values gathered by the computational input terminal. According to the results of the comparison, the compensation circuit  401  or the comparator  405  is triggered to output an approximate root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q to the approximate value output terminal  25 .  
         [0033]      FIG. 5  is a graph showing the basic concept behind the method of demodulating a square root when the input values are I and Q. As shown in  FIG. 5 , the solution of the root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q is approximated using the formula aX+bY. Here, X=|I|, Y=|Q| and a and b are the coefficients of X and Y. In the present invention, the right-angled rectangular coordinate axes |I| and |Q| is divided into four sectors. The first sector I occupies the angle between 0° to 14°, the second sector II occupies the angle between 14° to 45°, the third sector III occupies the angle between 45° to 76° and the fourth sector IV occupies the angle between 76° to 90°. The present invention provides four formulae to find the root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q, namely: 
   R 1=| I|=R  cos θ   R 2=⅞| I|+ ½| Q|=R (⅞ cos θ+½ sin θ)    R 3=½| I|+ ⅞| Q|=R (½ cos θ+⅞ sin θ)    R 4=| Q|=R  sin θ,         where R1, R2, R3 and R4 are the approximate solution to the root-mean-square value {square root}{square root over (I 2 +Q 2 )} within the sector I, II, III and IV and θ is the angle between the coordinate point (I,Q) and the origin (0,0).          
         [0035]     In addition, the present invention also provide four determining forms as follows: 
 
|small|≦|large|≦1.15|small| and |large|=|small|  (1) 
 
|small|≦|large|≦1.15|small| and |large|≠|small|  (2) 
 
3.07|small≦|large|≦6.3|small∥ and 3.48|small|≦|large|≦4.7|small|  (3) 
 
3.07|small≦|large|≦6.3|small∥ and 3.48|small|&gt;|large|&gt;4.7|small|  (4) 
        where the larger one between |I| and |Q| is |large| and the smaller one between |I| and |Q| is |small|. When the relation between |large| and |small| conforms to inequalities (1) and (3), the approximate solution of the root-mean-square value {square root}{square root over (I 2 +Q 2 )} is |large|+2 −5 |large|. When the relation between |large| and |small| conforms to inequalities (2) and (4), the approximate solution of the root-mean-square value {square root}{square root over (I 2 +Q 2 )} is |large|+ 2   −6 |large|.        
 
         [0037]      FIG. 6  is a flow diagram showing the steps in demodulating a square root according to one preferred embodiment of the present invention. As shown in  FIGS. 2, 4  and  6 , the compare absolute value circuit  210  finds the absolute values of the input values I and Q in step S 610 . The larger value between |I| and |Q| is defined as |large| and the smaller value between |I| and |Q| is defined as |small| in step S 620 . Thereafter, |large| and |small| are individually multiplied with different preassigned values and then transmitted to the comparator  403  for assessment in steps S 630  and S 650 . Thus, either an approximate solution of the root-mean-square value {square root}{square root over (I 2 +Q 2 )} of |large|+2 −5 |large| is output from the compensation circuit  401  after compensating for |large| and |small|in step S 640  or |large|+2 −6 |large| is output from the compensation circuit  401  after compensating for |large| and |small| in step S 660 .  
         [0038]     When the comparator  403  discovers that the output values from the multiplier  220  conforms to the determining forms (1) and (2) in steps S 632  and S 634 , step S 640  is executed. On the other hand, when the comparator  403  discovers that the output values from the multiplier  220  conforms to the determining forms (3) and (4) in steps S 652  and S 654 , step S 660  is executed.  
         [0039]     Although the comparator  403  seems to inspect the relation between |large| and |small| using the determining forms (1), (2), (3) and (4) in sequential order in the present embodiment, it is not. Anyone familiar with the technique knows that the comparator  430  may inspect the four determining forms (1), (2), (3), (4) in whatever sequence or together simultaneously without affecting the spirit of the present invention.  
         [0040]     When the relation between |large| and |small| does not conform to any one of the four determining forms, the comparator  403  outputs a value ⅞|large|+½|small| to the comparator  405 . The comparator  405  compares the value ⅞|large|+½|small| with {square root}{square root over (I 2 +Q 2 )} and outputs the larger one as the approximate root-mean-square {square root}{square root over (I 2 +Q 2 )} value.  
         [0041]     To simplify the hardware structure of the present invention, the aforementioned four determining forms are modified as follows: 
 
16|small|≦16|large|≦18|small| and 16|large|=16|small|  (1) 
 
16|small|≦16|large|≦18|small| and 16|large|≠16|small|  (2) 
 
12|small≦4|large|≦25|small∥ and 14|small|≦4|large|≦19|small|  (3) 
 
12|small≦4|large|≦25|small∥ and 14|small|&gt;4|large|&gt;19|small|  (4) 
 
 The purpose of modifying the four determining forms is to convert a floating-point computation into a fixed decimal point computation so that the complexity of the hardware computational circuit is reduced. 
 
         [0042]      FIG. 7  is a table listing the relation between angle and error ratio deploying the method according to the present invention. As shown in  FIG. 7 , the error ratio for the majority of angles is smaller than 1% and the largest error ratio does not exceed 1.1%  
         [0043]     In summary, the present invention utilizes the conversion of floating point computation into fixed decimal point computation to simplify the hardware circuit structure. Hence, only simple shifters, multipliers and comparators are required to find the approximate root-mean-square value {square root}{square root over (I 2 +Q 2 )} of the input values I and Q. In this way, the demodulating speed is faster and the cost of the apparatus for demodulating square root is reduced. Furthermore, the setup of four determining forms in the present invention for finding the root-mean-square value substantially increases the accuracy of the solution.  
         [0044]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.