Abstract:
A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Description:
[0001]    This application claims the priority under 35 U.S.C. §119 of European patent application no. 09180585.3, filed on Dec. 23, 2009, the contents of which are incorporated by reference herein. 
       FIELD OF THE INVENTION 
       [0002]    This invention relates to micro-electromechanical systems (MEMS). More particularly, it relates to piezo-resistive MEMS resonator devices. 
       BACKGROUND OF THE INVENTION 
       [0003]    MEMS resonators allow the integration of accurate timing and frequency reference devices on a silicon chip. This allows major cost and size reductions compared, for example, to conventional quartz oscillator circuits. 
         [0004]    MEMS resonators can use extensional (longitudinal) modes, or torsional (bending) modes. Extensional modes are favourable in some applications because they can store more energy than most flexural modes, and are therefore less susceptible to non-linearity. 
         [0005]    Extensional-mode—also known as planar-mode—vibration consists of a compression wave in the plane of the material. That is, the physical displacement of the material takes place in directions lying in the same plane as the resonator, alternately stretching and compressing the material. There is little or no displacement (that is, bending or flexion) in the direction transverse to the plane. Torsional mode vibration involves the bending of a structure out of its plane. 
         [0006]    In a typical MEMS resonator, the mechanical vibration is excited by electrostatic forces resulting from an electrical signal applied via one or more electrodes spaced a small distance apart from the resonator. The vibration gives rise to a changing capacitance, which can be detected either via a separate output electrode (or electrodes) or via the body of the resonator itself. 
         [0007]    In a capacitive read-out arrangement, in order to have a measurable signal, the change in capacitance during movement of the MEMS resonator needs to be large enough. This is usually achieved by making the MEMS structures high (using˜10 μm Silicon-on-Insulator (SOI) layers) and wide. It is therefore very hard to scale these devices down to smaller sizes (and higher frequencies) without decreasing the signal (the admittance) too much. 
         [0008]    One method to overcome this disadvantage is to make use of a piezo-resistive read-out arrangement, as disclosed by J. T. M. van Beek et al, “Scalable 1.1 GHz fundamental mode piezo-resistive silicon MEMS resonator”, IEDM 2007 pages 411-414. The read out method involves sending a small current through the resonating devices. The mechanical movement of the device will induce mechanical stretching which in turn will change the resistance of the current path (by the piezo-resistive effect) and register as an electrical signal. 
         [0009]    When the input signal is at or near the resonant frequency of the device, resonance occurs, effectively amplifying the output signal at this frequency by the gain factor Q of the device. 
         [0010]    The size of a MEMS resonator is inversely related to the resonant frequency. Current sizes are sufficiently small to make Radio-Frequency (RF) resonators realizable using this technology. This makes MEMS technology an exciting prospect for next generation wireless communication devices. However, to prove a viable alternative to conventional resonators, MEMS devices must match or exceed their performance. The devices must resonate in predictable and stable modes and be highly efficient transducers of electrical/mechanical energy. 
         [0011]    One of the disadvantages of the piezo-resistive read-out method is that a small current is needed through the resistor in order to measure the change in resistance. The read out method therefore consumes electrical power. 
       SUMMARY OF THE INVENTION 
       [0012]    According the invention there is provided a piezo-resistive MEMS resonator comprising an anchor, a resonator body mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator, wherein the resonator body has an area of at least 100 μm 2  and the nanowire has a cross section of at most 10 −14  m 2 . 
         [0013]    This design combines a low power miniature piezo-resistive readout scheme with a large size resonator. A piezo-resistive effect is created that exceeds the piezo-resistive effect that is observed for bulk silicon. 
         [0014]    In operation the MEMS resonator is excited by an electrostatic force and the mechanical motion of the resonator is detected using the piezo-resistive properties of silicon. 
         [0015]    The invention is based on the realisation that silicon nanowires show a giant piezo-resistive effect. This means that the change in resistance for a certain applied stress is much larger in silicon nanowires than in bulk silicon (about a factor 30). By using this effect in MEMS resonators the operating power is decreased and the transconductance is increased. The giant piezo-resistive effect is discussed by P. Schewe et al.: “Giant Piezoresistance”, Physics News Update, May 2008. 
         [0016]    It has been found that when scaling down the size of the readout path, the transconductance does not scale linearly with the wire diameter, but increases faster than would be expected simply from geometric considerations. 
         [0017]    Preferably, the resonator body has an area of at least 200 μm 2  and more preferably at least 400 μm 2 . The nanowire preferably has a cross section of at most 5×10 −15  m 2 . In one example, the nanowire comprises a structure having a width of approximately 50 nm. 
         [0018]    The resonator can be fabricated on a silicon-on-insulator (SOI) layer, and the nanowire is made by oxidising and etching the SOI layer. Alternatively, the resonator can be fabricated on a silicon-on-insulator (SOI) layer and the nanowire can be made by growing a SiGe layer at a pre-selected place, growing a c-Si layer on the SiGe layer, oxidising the SiGe layer and selectively etching the oxidised SiGe layer to form the nanowire. 
         [0019]    The nanowire portion preferably comprises an isolated portion of the silicon layer. Thus, a small depth part of the relatively thick SOI layer is isolated to enable the desired small cross section nanowire to be formed. 
         [0020]    The invention also provides a method of manufacturing a piezo-resistive MEMS resonator, comprising: 
         [0021]    forming an anchor, a resonator body mounted on the anchor and a piezo-resistive read-out means on a silicon on insulator substrate; and providing an actuator for applying an electrostatic force on the resonator; 
         [0022]    wherein the piezo-resistive read-out means comprises a nanowire coupled to the resonator, formed by etching and isolating a silicon portion from the silicon-on-insulator layer, and wherein the resonator body has an area of at least 100 μm 2  and the nanowire has a cross section of at most 10 −14  m 2 . 
         [0023]    By isolating a small depth portion of the silicon layer, a nanowire can be formed. 
         [0024]    Etching the silicon portion can comprise: 
         [0025]    etching a silicon line of first width; 
         [0026]    oxidising a portion of the silicon line and etching away the oxidised silicon to form a line of second, smaller width. 
         [0027]    This creates a line of the desired width, using standard processes. 
         [0028]    In one example, etching the silicon portion further comprises removing a top portion of the line of second width to define a nanowire portion as a remaining bottom portion. For example, removing a top portion can comprise implanting a species which amorphises a portion of the line of second width to a desired depth, and removing the amorphised part of the silicon line of second width. 
         [0029]    In another example, etching the silicon portion further comprises providing an isolated top portion of the line of second width to define a nanowire portion. For example, a silicon germanium layer can be formed between a lower silicon portion and an upper silicon portion in the region of the nanowire portion, and the silicon germanium layer is removed to isolate the upper silicon portion. 
         [0030]    In all examples, wherein the isolated portion preferably has a depth of less than 100 nm (e.g. 50 nm) and a line width of less than 100 nm. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]    The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: 
           [0032]      FIG. 1  is a diagrammatic view of a MEMS resonator made in accordance with the present invention, 
           [0033]      FIG. 2  is a top-down picture of a MEMS resonator made in accordance with the present invention, 
           [0034]      FIG. 3  shows the resonator of  FIG. 2  in perspective view and in more detail; 
           [0035]      FIG. 4  shows the resonator of  FIG. 3  in plan view; 
           [0036]      FIGS. 5   a  to  5   d  illustrate one method of forming a silicon nanowire for use in the MEMS resonator made in accordance with the present invention, and 
           [0037]      FIGS. 6   a  to  6   d  illustrate another method of forming a silicon nanowire for use in the MEMS resonator made in accordance with the present invention. 
       
    
    
       [0038]    In the drawings the same reference numerals have been used to indicate corresponding features. 
       DETAILED DESCRIPTION OF EMBODIMENTS 
       [0039]    The invention is based on the use of the giant piezo-resistive effect as the readout mechanism for a MEMS resonator. This enables a decrease in the operating power of the device. 
         [0040]      FIG. 1  shows schematically the elements of the resonator of the invention. A silicon resonator mass  10  is resiliently mounted to an anchor  12  for example, by means of a spring  14 . The resonator mass  10  is excited electrostatically by means of an actuation electrode  16 . 
         [0041]    A silicon nanowire  18  is connected between the resonator  10  and the anchor  12 . As the resonator mass  10  vibrates, the nanowire  18  is subject to stress causing its electrical resistance to vary and a voltage difference between the resonator mass  10  and the anchor  12  will cause a current in the nanowire. Since this nanowire  18  shows a giant piezo-resistive effect, the read-out signal will be much larger compared to a bulk resistor. In this way the dissipating power for the resistor can be decreased in order to have the same output signal. 
         [0042]      FIG. 2  differs from the diagram shown in  FIG. 1  by the resonator mass  10  being attached to the rest of the silicon (not shown) by means of the anchor  12 , without the need for a separate spring element as in  FIG. 1 . The resonator mass  10  is also connected to another part of the silicon by the nanowire  18  in such a way that a current I can flow from the anchor  12  through the resonator mass  10  and through the nanowire  18 . In this way the piezo-resistive effect can be measured and the movement of the resonator mass  10  can be monitored. 
         [0043]    In the example illustrated in  FIG. 2 , the nanowire  18  can have a cross-section of 50×50 nm. However the giant piezo-resistive effect starts to be visible for 100×100 nm cross-sections. 
         [0044]    The use of the giant piezo-resistive effect for readout of miniature resonator devices has been suggested. 
         [0045]    This invention is based on the recognition that the nanowire readout is suitable for large resonator structures, for example with area greater than 100 μm 2 . 
         [0046]      FIG. 3  shows a perspective view of the resonator design of the invention corresponding to the design of  FIG. 2 . A dc current source  19  provides current to the nanowire  18  and this flows to earth through the anchor  12 . The output voltage is measured at the nanowire as shown. 
         [0047]      FIG. 4  shows the patterning of the silicon layer (typically a silicon layer of a SOI substrate) to define the structure. The lines  20  represent removed material which provides an isolated resonator mass  10  suspended by a hinge defined by the anchor  12 , and also defines the narrow opening which forms the nanowire. 
         [0048]      FIG. 4  shows with dotted lines the current path and the output voltage used for readout. 
         [0049]    The dimensions of the resonator body  10  in  FIG. 4  are approximately 60 μm by 10 μm. Thus, the resonator body is substantially larger than the nanowire structure. This combines a resonator mass for which the resonance frequency can manufactured with high accuracy (because of good control over the dimensions) with good read out sensitivity using the giant piezo-resistive effect. Generally, the area of the resonator body is more than 100 (μm) 2 . More preferably, the resonator body area is more than 200(μm) 2  and even more preferably more than 400 (μm) 2 . 
         [0050]    The nanowire has a cross section of at most 10 −14  m 2  (10,000(nm) 2 ). It may be less than 5×10 −15  m 2  (5,000(nm) 2 ). 
         [0051]      FIGS. 5 and 6  show two possible manufacturing methods for the nanowire structures. As shown in  FIG. 4 , the nanowire comprises an isolated area of silicon across which an electrical connection is made. The methods are shown are for forming an isolated small cross sectional area (e.g. 50 nm width×50 nm depth) of silicon. As shown in  FIG. 4 , one end of the nanowire will be connected to the resonator mass and the other end will be connected to a readout pad.  FIGS. 5 and 6  simply show the concepts used and show the cross section of the top silicon layer of the SOI substrate. The top silicon layer may be a few microns thick, and the etching lines in  FIG. 4  are anisotropically etched through the silicon. The underlying oxide is isotropically etched in a subsequent step to release the resonator from the substrate (in conventional manner). 
         [0052]    Referring to  FIGS. 5   a  to  5   d , in one example, the resonators are made on SOI wafers with a silicon thickness of 1.5 μm. The top silicon layer is shown. In order to make nanowires it is necessary to etch approximately 50 nm wide structures and to separate the top part (e.g. the top or bottom 50 nm) of that structure in order to form the nanowire. 
         [0053]      FIG. 5   a  shows a silicon line  21  etched in the SOI layer. This has a width greater than the desired nanowire width, for example 100-300 nm.  FIG. 5   b  shows the silicon line  21  being partially oxidised to form an oxide layer  22  enveloping a non-oxidised line  24  of the desired width. In  FIG. 5   c  the oxide layer  22  is etched away using hydrofluoric acid (HF). 
         [0054]    This creates a line of narrower width, and having the desired width for the nanowire (e.g. 50 nm). 
         [0055]    The non-oxidised line  24  is then treated by implanting with a species that amorphises the silicon to a desired depth. In this way, the silicon is made amorphous apart from the bottom 50 nm (for example). 
         [0056]    Finally  FIG. 5   d  shows that the amorphised silicon is etched away selectively to the crystalline-Si using HF to leave a nanowire  18 , in the form of a remaining portion of silicon. 
         [0057]      FIGS. 6   a  to  6   d  show another method of making a nanowire.  FIG. 6   a  shows a silicon line  21  in which a layer  26  of silicon germanium (SiGe) is epitaxially grown on top of the silicon, in those places where it is desired to have a nanowire. On top of the SiGe layer  26  a thin layer  27  (&lt;50 nm) of crystalline Si is grown. 
         [0058]      FIGS. 6   b  and  6   c  show the oxidation and etching processes which were in the embodiments shown in  FIGS. 5   b  and  5   c  above. Thus, in  FIG. 6   c , the 50 nm wire comprises a silicon base, a SiGe layer and the nanowire portion of desired thickness on top. 
         [0059]    Finally  FIG. 6   d  shows the nanowire  18  after the SiGe layer  26  has been removed selectively to the silicon with a dry etch. Again, a nanowire portion  18  of the desired dimensions remains. Thus, SiGe can be used to define the isolation between the top nanowire portion  18  and the thicker (1.5 μm) silicon layer beneath. 
         [0060]    The invention has particular, but not exclusive, application in timing devices for example in integrated circuits used in GSM phones, Bluetooth devices, RF-ID devices, Smartcards and clocks. 
         [0061]    In the present specification and claims the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. Further, the word “comprising” does not exclude the presence of other elements or steps than those listed. 
         [0062]    The use of any reference signs placed between parentheses in the claims shall not be construed as limiting the scope of the claims. 
         [0063]    From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of MEMS resonators and component parts therefor and which may be used instead of or in addition to features already described herein.