Abstract:
A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2007-324408, filed on Dec. 17, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    An attempt to improve carrier mobility in an inversion layer by applying a stress to a channel region in a planar FET has been made. For example, a method of applying a stress to a channel region by etching a part of a drain region and/or source region and filling therein a semiconductor having different lattice constant is used (for example, JP. 2007-129235). 
         [0003]    However, in a fin-type MOS transistor (hereinbelow, Fin FET), a material having different lattice constant can be buried in a part of a fin, but it is difficult to effectively apply a stress to the channel region. 
       SUMMARY OF THE INVENTION 
       [0004]    A fin transistor according to one aspect of the invention includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode. 
         [0005]    A fin transistor according to another aspect of the invention includes: a semiconductor substrate; a plurality of semiconductor fins formed over the substrate so as to be isolated from the semiconductor substrate by an insulating layer; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIGS. 1A and 1B  are diagrams showing the configuration of a Fin FET according to a first embodiment; 
           [0007]      FIGS. 2A and 2B  are diagrams showing a mode in which a member is buried to the surface of an insulating layer and a mode in which the member is buried to the inside of the insulating layer; 
           [0008]      FIG. 3  is a diagram showing the configuration of a Fin FET according to a second embodiment; 
           [0009]      FIG. 4  is a diagram showing the configuration of a Fin FET according to a third embodiment; 
           [0010]      FIG. 5  is a diagram showing the configuration of a Fin FET according to a fourth embodiment; 
           [0011]      FIGS. 6A and 6B  are diagrams for explaining a method of burying a member in a part of a gate electrode in a Fin FET according to an embodiment of the present invention; 
           [0012]      FIGS. 7A and 7B  are diagrams for explaining a method of burying a member in a part of a gate electrode in a Fin FET according to an embodiment of the present invention; 
           [0013]      FIGS. 8A and 8B  are diagrams showing the configuration of a Fin FET according to a fifth embodiment; 
           [0014]    and  FIGS. 9A and 9B  are diagrams showing the configuration of a Fin FET according to a sixth embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     First Embodiment 
       [0015]      FIG. 1A  is a diagram showing the configuration of a Fin FET according to a first embodiment. 
         [0016]    An insulating layer  11  as a silicon oxide (SiO 2 ) film is formed on a silicon wafer  10 , and two fins  20  and  21  are formed on a top face of the insulating layer  11  so that their longitudinal direction is set in an X direction. The fins  20  and  21  are made of, for example, a semiconductor material such as silicon. The Fin FET according to the first embodiment is constructed by a bulk substrate  12  in which the silicon wafer  10  and the fins  20  and  21  divide the insulating layer  11  and are coupled. 
         [0017]    Insulating layers  22  and  23  are formed on the top face of the fins  20  and  21 , respectively. The insulating layers  22  and  23  are formed by, for example, a silicon nitride (SiN) film. A gate electrode  30  is formed in such a manner that a first gate electrode  30 A formed so as to cover the top face and both side faces of the fin  20  and a second gate electrode  30 B formed so as to cover the top face and both side faces of the fin  21  extend continuously in the Y direction. The gate electrode  30  is made of, for example, polysilicon (hereinbelow, poly Si). Although two fins are used as an example in the first embodiment, any plural number of fins may be provided. In a Fin FET, at least side faces of a fin and, sometimes, even the top face of the fin are used as a channel region. Since the insulating layers  22  and  23  are formed on the top face of the fins in the first embodiment, both side faces are used as the channel regions. In the following, a mode using both side faces of a fin as the channel region will be called a double-gate type, and a mode using both side faces and the top face as the channel region will be called a tri-gate type. Like a common Fin FET, a gate oxide film  26  is formed on faces which are in contact with the gate electrode  30  and the fins  20  and  21 . 
         [0018]    A sectional structure of the Fin FET according to the first embodiment will now be described with reference to  FIGS. 1B to 2B . The gate electrode  30  is formed so as to cover the fins  20  and  21 . In the gate electrode  30 , regions  31  on the side faces of the fins  20  and  21  are removed (hereinbelow, the regions  31  will be called “removed regions  31 ”). In the removed region  31 , a member  32  is buried (buried member  32 ). Therefore, the buried member  32  is formed at the lateral portion of the side faces of the fins  20  and  21  except the top faces of the fins  20  and  21 . In  FIG. 1B , the bottoms of the removed regions  31  exist between the top face of the gate electrode  30  and the top face of the insulating layer  11 . Specifically, the bottom face does not reach the top face of the insulating layer  11 , and poly Si as the material of the gate electrode  30  exists between the bottom face of the buried member  32  and the surface of the insulating layer  11 . In addition, an upper portion of the buried member  32  is formed higher than the top faces of the fins  20  and  21 . The buried member  32  is made of a material having lattice constant different from that of poly Si as the material of the gate electrode  30 , such as silicon germanium (hereinbelow, SiGe). The buried member  32  can be formed by, for example, CVD. The buried member  32  is formed so that its conduction type is the same as that of the gate electrode  30 . With this configuration, the resistance value of the fins  20  and  21  decreases and a voltage is applied more easily to the bottom of the fins  20  and  21  as compared with the case where the conduction type of the buried member  32  is different from that of the gate electrode  30 . For example, when the gate electrode  30  is of the “n” type, the buried member  32  is also formed of the “n” type. The buried member  32  having the same conduction type as that of the gate electrode  30  can be formed by doping an impurity during execution of CVD or the like. Alternatively, after formation of the buried member  32 , the buried member  32  may be doped with an impurity by ion implantation or the like. 
         [0019]    In the first embodiment as described above, by burying SiGe having lattice constant larger than that of poly Si as the material of the gate electrode  30  in the removed region  31  to form the buried member  32 , compression stress is generated in the gate electrode  30 . As a result, the compression stress is applied to channel regions  24  and  25  in the fins  20  and  21 , thereby increasing carrier mobility in a MOSFET. Since the gate electrode  30  is continuously formed between the fins  20  and  21 , the stress in the buried member  32  buried in the removed region  31  between the fins  20  and  21  is laconically applied to the channel regions  24  and  25  in the fins  20  and  21  disposed on both sides. 
         [0020]    The material of the buried member  32  is not limited to SiGe but any material may be used as long as compression stress can be applied to the channel regions  24  and  25 . By using a material having density higher than that of the material of the gate electrode  30  in place of the material having lattice constant different from that of the material of the gate electrode  30 , the compression stress can be applied to the channel regions  24  and  25 . For example, by burying amorphous silicon (hereinbelow, amorphous Si) having density higher than that of poly Si as the buried member  32  in the removed region  31  and performing heat treatment to increase the volume of amorphous Si, the compression stress can be applied to the channel regions  24  and  25 . 
         [0021]    The stress applied to the channel regions  24  and  25  is not limited to compression stress but may be tensile stress. For example, a material having density lower than that of poly Si, such as silicon carbide obtained by doping silicon with carbon (hereinbelow, SiC) can be employed as the material of the buried member  32 . By forming the buried member  32  in the removed region  31 , tensile stress can be applied to the channel regions  24  and  25 . A similar effect can be obtained by burying amorphous Si having density lower than that of poly Si in place of SiC in the removed region  31  as the material of the buried member  32  and performing heat treatment to form polycrystal. 
         [0022]    The bottom of the buried member  32  may be positioned between the top face of the gate electrode  30  and the surface of the insulating layer  11  as shown in  FIG. 1B . It may reach the surface of the insulating layer  11  as shown in  FIG. 2A  or reach a point below the surface of the insulating layer  11  as shown in  FIG. 2B . Therefore, the buried member  32  is formed at the portion lower than that of the bottom end of the gate oxide film  26 . It is preferable, however, that it does not penetrate the insulating layer  11  to reach the silicon wafer  10 . In any case, the stress (compression stress or tensile stress) can be applied to the channel regions  24  and  25 . 
         [0023]    The case of using poly Si as the material of the gate electrode  30  has been described in the first embodiment. A similar effect can be also obtained by a method of using a metal or a conductive compound for the gate electrode  30 , and burying a material having a linear expansion coefficient different from that of the material of the gate electrode  30  to generate a stress in the gate electrode  30  and apply the stress to the channel regions. 
       Second Embodiment 
       [0024]      FIG. 3  is a configuration diagram of a Fin FET according to a second embodiment. The same reference numerals are designated to the same parts as those of the first embodiment. The second embodiment relates to a Fin FET having an SOI (Silicon On Insulator) substrate structure, and the structure of the substrate is different from that of the first embodiment. 
         [0025]    In the Fin FET according to the second embodiment, an insulating layer  11  as an oxide film (SiO 2 ) is formed on a silicon wafer  10 , and two fins  20  and  21  made of single-crystal silicon are formed on a top face of the insulating layer  11  as an SOI form in which their longitudinal direction is set in an X direction. In an SOI substrate  13 , by forming the fins  20  and  21  made of silicon on the insulating layer  11  as an oxide film, parasitic capacitance of a transistor part can be reduced more than that in a Fin FET using a bulk substrate. Therefore, operation speed can be improved and power consumption can be reduced. 
         [0026]    The parts such as a gate electrode  30  and a buried member  32  are similar to those of the first embodiment. That is, the buried member  32  may be made of a material having lattice constant different from that of poly Si as the material of the gate electrode  30 . The buried member  32  may be formed so that its conduction type is the same as that of the gate electrode  30 . For the buried member  32 , a material having density higher than that of poly Si or a material having density lower than that of poly Si may be used. Consequently, a stress can be applied to the channel regions  24  and  25  in the fins  20  and  21 . An effect similar to that of the first embodiment can be obtained. The bottom of the buried member  32  may not reach the surface of the insulating layer  11  as shown in  FIG. 3  or may reach the surface of the insulating layer  11  as shown in  FIG. 2A . The bottom of the buried member  32  may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . It is preferable, however, that it does not penetrate the insulating layer  11  to reach the silicon wafer  10 . 
       Third Embodiment 
       [0027]      FIG. 4  is a configuration diagram of a Fin FET according to a third embodiment. The same reference numerals are designated to the same parts as those of the first embodiment. The third embodiment relates to a tri-gate Fin FET in which the insulating layers  22  and  23  are not formed on the top faces of the fins  20  and  21 , and the top faces of the fins  20  and  21  are also used as the channel regions  24  and  25 . The third embodiment is different from the first embodiment only in this part. 
         [0028]    In the tri-gate Fin FET, the opening/closing of a channel is controlled in three directions. Consequently, the leak current when the FET is off can be reduced more than the double-gate type in which the opening/closing of a channel is controlled in two directions. 
         [0029]    The parts such as a gate electrode  30  and a buried member  32  are similar to those of the first embodiment. That is, the buried member  32  may be made of a material having a lattice constant different from that of poly Si as the material of the gate electrode  30 . The buried member  32  may be formed so that its conduction type becomes the same as that of the gate electrode  30 . For the buried member  32 , a material having density higher than that of poly Si or a material having a density lower than that of poly Si may be used. Consequently, a stress can be applied to the channel regions  24  and  25  in the fins  20  and  21 . An effect similar to that of the first embodiment can be obtained. 
         [0030]    The bottom of the buried member  32  may not reach the surface of the insulating layer  11  as shown in  FIG. 4  or may reach the surface of the insulating layer  11  as shown in  FIG. 2A . The bottom of the buried member  32  may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . It is preferable, however, that it does not penetrate the insulating layer  11  to reach the silicon wafer  10 . 
       Fourth Embodiment 
       [0031]      FIG. 5  is a configuration diagram of a Fin FET according to a fourth embodiment. The same reference numerals are designated to the same parts as those of the first embodiment. The fourth embodiment is similar to the first embodiment except that the substrate is of the SOI type, and the gate is of the tri-gate type. Therefore, in the fourth embodiment, the operation speed can be improved, power consumption can be reduced, and the leak current when the FET is off can be reduced more than the first embodiment. Since the parts such as a gate electrode  30  and a buried member  32  are similar to those of the first embodiment, a stress can be applied to the channel regions  24  and  25  in the fins  20  and  21 . An effect similar to that of the first embodiment can be obtained. 
         [0032]    The bottom of the buried member  32  may not reach the surface of the insulating layer  11  as shown in  FIG. 5  or may reach the surface of the insulating layer  11  as shown in  FIG. 2A . The bottom of the buried member  32  may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . It is preferable that it does not penetrate the insulating layer  11  to reach the silicon wafer  10 . 
       Fifth Embodiment 
       [0033]      FIG. 8A  is a configuration diagram of a Fin FET according to a fifth embodiment. The same reference numerals are designated to the same parts as those of the first embodiment. The fifth embodiment is similar to the first embodiment except that the buried member  32  is made of a metal and, further, the buried member  32  is formed even to the surface of a gate oxide film  26  formed on side faces of fins  20  and  21  as shown in  FIG. 8A . In this embodiment, an upper end of the buried member  32  is formed on the approximately same level of the top faces of the fins  20  and  21 . 
         [0034]    Also by a method of using metal for the buried member  32  and burying a material having a linear expansion coefficient different from that of the gate electrode  30  to generate a stress in the gate electrode  30  and apply the stress to a channel region, an effect similar to that of the first embodiment can be obtained. 
         [0035]    The bottom of the buried member  32  may reach the surface of the insulating layer  11  as shown in  FIG. 8A  or may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . Preferably, it may not penetrate the insulating layer  11  and reach the silicon wafer  10 . 
         [0036]    As shown in  FIG. 8B , an SOI substrate may be used. A Fin FET shown in  FIG. 8B  can realize improved operation speed and reduced power consumption more than the Fin FET shown in FIG.  8 A. 
         [0037]    Also by a method of using a metal for the buried member  32  and burying a material having a linear expansion coefficient different from that of the gate electrode  30  to generate a stress in the gate electrode  30  and apply the stress to a channel region, an effect similar to that of the first embodiment can be obtained. 
         [0038]    The bottom of the buried member  32  may reach the surface of the insulating layer  11  as shown in  FIG. 8B  or may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . It is preferable, however, that it does not penetrate the insulating layer  11  to reach the silicon wafer  10 . 
       Sixth Embodiment 
       [0039]      FIG. 9A  is a configuration diagram of a Fin FET according to a sixth embodiment. The same reference numerals are designated to the same parts as those of the first embodiment. The sixth embodiment is similar to the fifth embodiment except that the gate is of a tri-gate type. 
         [0040]    In the sixth embodiment, leak current when the FET is off can be reduced more than that in the fifth embodiment. Further, since a buried member  32  is formed also on the top faces of fins  20  and  21 , a more stress can be applied to channel regions  24  and  25  in the fins  20  and  21  than in the fifth embodiment. 
         [0041]    The bottom of the buried member  32  may reach the surface of the insulating layer  11  as shown in  FIG. 9A  or may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . Preferably, it may not penetrate the insulating layer  11  and reach the silicon wafer  10 . 
         [0042]    As shown in  FIG. 9B , an SOI substrate may be used. A Fin FET shown in  FIG. 9B  can realize improved operation speed and reduced power consumption more than the Fin FET shown in  FIG. 9A . 
         [0043]    The bottom of the buried member  32  may reach the surface of the insulating layer  11  as shown in  FIG. 9B  or may penetrate the surface of the insulating layer  11  and reach the inside of the insulating layer  11  as shown in  FIG. 2B . Preferably, it may not penetrate the insulating layer  11  and reach the silicon wafer  10 . 
         [0044]    A method of burying the buried member  32  in the embodiments of the present invention will now be described with reference to the drawings. The first embodiment will be taken as an example. 
         [0045]    In order to pattern the removed region  31  formed in the gate electrode  30 , a Fin FET is masked.  FIG. 6A  is a top view of the Fin FET in that state.  FIG. 6B  is a cross-sectional view taken along the line B-B of  FIG. 6A . An interlayer insulating layer  35  is formed around the gate electrode  30 . 
         [0046]    By etching patterned portions in poly Si of the gate electrode  30 , the removed regions  31  are formed. The etching is, for example, reactive ion etching (RIE). The etching is not limited to RIE but may be dry etching or wet etching. The buried member  32  is buried in the removed regions  31  by CVD, after which the top face of the gate electrode  30  is planarized. The buried member  32  can be formed by, for example, doping an impurity during execution of CVD. The impurity doping may be performed by ion implantation or the like after formation of the buried member  32 .  FIG. 7A  is a top view of a Fin FET after the planarization, and  FIG. 7B  is a cross-sectional view taken along the line C-C. 
         [0047]    After that, by siliciding the top face of the gate electrode  30 , a Fin FET capable of applying a normal stress to the channel parts in the fins can be manufactured.