Abstract:
Methods of performing two point calibration of a linear-logarithmic image sensor pixel include measuring voltages of a floating diffusion region of the pixel after establishing a plurality of unequal sub-threshold currents through a transfer transistor of the pixel. These sub-threshold currents operate to sequentially increase a voltage of the floating diffusion region to respective voltage levels that enable knee-point (KNPT) voltage and logarithmic sensitivity (LOGS) determination. The methods also include depleting a photodiode within the pixel by driving a cathode of the photodiode with a pull-up current in advance of establishing the sub-threshold currents. The method is photocurrent-independent.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is related to U.S. application Ser. No. 14/224,198, filed Mar. 25, 2014, entitled “Methods of Calibrating Linear-Logarithmic Image Sensors,” the disclosure of which is hereby incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to integrated circuit devices and, more particularly, to image sensor devices and methods of operating same. 
       BACKGROUND OF THE INVENTION 
       [0003]    Conventional CMOS image sensors can have a linear response to relatively low illumination and a logarithmic response to relatively high illumination, with a transition between the linear and logarithmic responses being referred to as a knee point (KNPT). As will be understood by those skilled in the art, an image sensor may be fully characterized when its linear sensitivity, logarithmic sensitivity (LOGS) and KNPT voltage are known. Because these parameters vary with process, transistor mismatch and temperature, etc., calibration is required. Without accurate calibration, a linear-logarithmic image sensor may introduce very large fixed pattern noise (FPN), which is typically not suitable for commercially viable applications. One conventional technique to inhibit FPN uses an external frame memory to store a sensor characteristic response. Based on this technique, a correction of the sensor readout for each pixel is performed after a full frame of image data is captured by an image signal processing (ISP) circuit and then modified by the sensor data stored in the external frame memory, which may have a relatively large capacity. Moreover, relatively complex ISP algorithms may be required to perform image sensor correction, which can be computationally expensive and time consuming. 
         [0004]    A conventional linear-logarithmic image sensor is disclosed in U.S. Pat. No. 7,804,537 to Storm et al., entitled “Combined Linear-Logarithmic Image Sensor.” This sensor includes an array of pixels, with each pixel including a photodiode and a first output circuit for deriving a linear output signal by applying a reset signal to a photodiode and reading a voltage on the photodiode after an integration time. A second output circuit is also provided, which derives a logarithmic output signal by reading a near instantaneous illumination-dependent voltage on the photodiode that is a logarithmic function of the illumination. In the logarithmic mode, the pixels are calibrated to remove fixed pattern noise (FPN). The pixels may be operated in linear and log modes sequentially with the linear output being selected for low light signals and the log output being selected for high light signals. 
       SUMMARY OF THE INVENTION 
       [0005]    Methods of calibrating a linear-logarithmic image sensor pixel according to embodiments of the invention may utilize on-the-fly calibration operations, which can avoid the need for a large frame “calibration” memory and extensive image signal processing (ISP) algorithms. These calibration operations can measure a voltage at a pixel floating diffusion (FD) region after at least one sub-threshold current is enabled to flow from a photodiode (PD) to the FD region via a transfer transistor, which is responsive to a transfer gate (TG) voltage. Because the direction of the sub-threshold current(s) is inverse to the one used during pixel integration, the resulting calibration process can be photocurrent-independent. 
         [0006]    According to some of the embodiments of the invention, the methods of calibrating include at least partially depleting a photodiode within the pixel prior to supplying a floating diffusion (FD) region within the pixel with a first subthreshold current. This first subthreshold current is achieved by passing charge carriers from the at least partially depleted photodiode to the floating diffusion (FD) region. A first voltage of the floating diffusion region may then be read through a series arrangement of a source follower transistor and a selection transistor within the pixel (e.g., within a four transistor (4T) cell). A calibration operation may then performed to use the first voltage to determine a knee-point (KNPT) voltage associated with a transition from a linear to logarithmic response of the pixel. The step of at least partially depleting the photodiode may include establishing a reverse bias across anode and cathode regions of the photodiode by shorting the floating diffusion region to the cathode region concurrently with supplying the floating diffusion region with a pull-up current. This supplying the floating diffusion region with a pull-up current may include turning on a reset transistor within the pixel. This reset transistor may have a first current carrying terminal electrically connected to the floating diffusion region and a second current carrying terminal responsive to a positive reset voltage (VR), which may be controlled to have an adjustable magnitude. In some embodiments of the invention, the reset transistor may be an NMOS transistor having a source terminal electrically connected to the floating diffusion region and a drain terminal responsive to the positive reset voltage. 
         [0007]    According to still further embodiments of the invention, the step of supplying the floating diffusion (FD) region within the pixel with a first subthreshold current is preceded by discharging the floating diffusion region, after the step of at least partially depleting the photodiode. The step of discharging the floating diffusion region may include discharging the floating diffusion region through the reset transistor within the pixel. In this manner, the reset transistor may be used to provide a pull-up current to deplete the photodiode and thereafter sink a pull-down current from the floating diffusion region. 
         [0008]    According to additional embodiments of the invention, the reading step is followed by supplying the floating diffusion region with a second subthreshold current by passing charge carriers from the at least partially depleted photodiode to the floating diffusion region. Thereafter, an operation is performed to read a second voltage of the floating diffusion region and estimate a logarithmic sensitivity of the pixel based at least in part on the value of the second voltage. In these embodiments, the duration of supplying the floating diffusion region with a second subthreshold current may be different, usually greater, than a duration of supplying the floating diffusion region with the first subthreshold current, so that the decrease in the charge during supplying the floating diffusion region with a second subthreshold current is compensated and made similar to the charge transferred during supplying the floating diffusion region with the first subthreshold current. 
         [0009]    Still further embodiments of the invention include methods of performing two point calibration of a linear-logarithmic image sensor pixel by, among other things, measuring voltages of a floating diffusion region of the pixel after establishing a plurality of unequal sub-threshold currents through a transfer transistor of the pixel. These methods include at least partially depleting a photodiode within the pixel by driving a cathode of the photodiode with a pull-up current. Thereafter, a floating diffusion region of the pixel is supplied with a first subthreshold current by passing charge carriers from the at least partially depleted photodiode to the floating diffusion region. A first voltage of the floating diffusion region is then read and used for calibration. The floating diffusion region is further supplied with a second subthreshold current by passing charge carriers from the at least partially depleted photodiode to the floating diffusion region. A second voltage of the floating diffusion region is then read and used for calibration. 
         [0010]    According to some of these two-point calibration methods, the step of driving the cathode of the photodiode with the pull-up current includes shorting the cathode of the photodiode to the floating diffusion region. Moreover, in the event the pixel includes a series arrangement of a reset transistor and a transfer transistor, a source terminal of the reset transistor may be electrically connected to the floating diffusion region and to a drain terminal of the transfer transistor and the driving the cathode of the photodiode with the pull-up current may include turning on the reset and transfer transistors. In this manner, the step of driving the cathode of the photodiode with the pull-up current may include pulling-up the cathode of the photodiode to a voltage equivalent to a drain terminal of the reset transistor minus a threshold voltage of the reset transistor and a threshold voltage of the transfer transistor. In addition, the step of supplying a floating diffusion region within the pixel with a first subthreshold current can be preceded by a step of discharging the floating diffusion region by driving the drain terminal of the reset transistor high-to-low while a gate terminal of the reset transistor is maintained at a high voltage level. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1A  is an electrical schematic of a four transistor (4T) linear-logarithmic image sensor pixel that supports on-the-fly calibration according to embodiments of the invention. 
           [0012]      FIG. 1B  illustrates a well-potential sequence associated with the transfer and reset transistors associated with a left side of the 4T linear-logarithmic image sensor pixel of  FIG. 1A , according to embodiments of the invention. 
           [0013]      FIG. 1C  is a timing diagram that illustrates the timing of voltages associated with the well-potential sequence of  FIG. 1B , according to embodiments of the invention. 
           [0014]      FIG. 1D  is a flow diagram of operations associated with on-the-fly pixel calibration according to embodiments of the invention. 
           [0015]      FIG. 2  is a graph illustrating a simulated linear-logarithmic response of the 4T pixel of  FIG. 1A  before calibration. 
           [0016]      FIG. 3  is a graph illustrating a simulated linear-logarithmic response of the 4T pixel of  FIG. 1A  after one-point calibration. 
           [0017]      FIG. 4  is a graph illustrating a simulated correlation between the knee-point (KNPT) voltage and the one-point calibration voltage, according to embodiments of the invention. 
           [0018]      FIG. 5  is a graph illustrating a simulated correlation between logarithmic sensitivity (LOGS) and the one-point calibration voltage, according to embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0019]    The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. 
         [0020]    It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer (and variants thereof), it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer (and variants thereof), there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. 
         [0021]    It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. 
         [0022]    Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
         [0023]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components. 
         [0024]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0025]      FIG. 1A  is an electrical schematic of a four transistor (4T) linear-logarithmic image sensor pixel  100  that has a linear response to relatively low illumination and a logarithmic response to relatively high illumination. This pixel  100  advantageously supports large pixel densities and typically uses the same architecture associated with 4T linear pixels, which are widely used in CMOS image sensor (CIS) design. As will be understood by those skilled in the art, because the knee-point (KNPT) and logarithmic sensitivity (LOGS) of the pixel  100  typically vary with fabrication process, transistor mismatch and temperature etc., image sensors based on such pixels may require calibration in order to avoid excessive fixed pattern noise (FPN). As described herein, the pixel  100  may be calibrated on-the-fly without requiring a frame memory, using an algorithm that is independent of photocurrent. Depending on the process characteristics, one or two calibration measurements may be required. These measurements, which may require only a few microseconds, can be done adjacent in time to the pixel readout. If required by the sensor timing, a line buffer may be used to store the pixel or calibration data between the pixel readout and calibration readout. 
         [0026]    As shown by  FIG. 1A , the 4T pixel  100  includes a first series arrangement of an NMOS reset transistor  10  and an NMOS transfer transistor  20  and a second series arrangement of an NMOS source follower (SF)  30  and an NMOS select transistor  40 , interconnected as illustrated. The reset transistor  10  has a drain terminal responsive to a variable reset voltage (VR), a source terminal electrically connected to a floating diffusion (FD) region and gate terminal of the source follower  30 , and a gate terminal responsive to a reset gate signal (RG). The transfer transistor  20  has a drain terminal electrically connected to the floating diffusion region FD, a source terminal electrically connected to a cathode of a photodiode  50  and a gate terminal responsive to a transfer gate signal (TG). The source follower  30  has a drain terminal responsive to a positive supply voltage (VPIX), which may be a fixed voltage, and a source terminal electrically connected to a drain terminal of the select transistor  40 . The select transistor  40  has a gate terminal responsive to a pixel select signal (SEL) and a source terminal connected to a pixel output terminal (OUT). 
         [0027]    Linear-logarithmic operation of the pixel  100  can be enabled by setting the TG voltage to a medium voltage. At low illumination, no current flows through the transfer transistor  20  during photocurrent integration and the response of the pixel is linear. However, when the illumination increases, a subthreshold current flows through the transfer transistor  20  in a direction opposite to the photocurrent and causes a logarithmic response of the pixel  100 . Because of the large variation of the subthreshold current, the logarithmic response becomes highly variable in response to process variation, device (e.g., transistor) mismatch and temperature. The variable reset voltage (VR) shown in  FIG. 1A  is typically held at a positive supply voltage equivalent to VPIX, but can be varied to enable reset of internal pixel voltages (e.g., FD voltage) that are used in the calibration process described more fully hereinbelow. 
         [0028]    As will be understood by those skilled in the art, the pixel signal can be read as in a linear pixel in two steps following a Correlated Double Sampling (CDS) procedure. The first measure of the CDS is the FD reset voltage and the second measure of the CDS is the FD voltage after transferring the accumulated photodiode (PD) charge. The CDS pixel signal is the difference between the second and first measurements. Moreover, as will now be described, following the two-step pixel read operations, which enable the determination of the CDS pixel signal, on-the-fly calibration measurements may be performed that are independent of photocurrent and adjacent-in-time to the pixel signal determination. In particular, as shown by the well-potential sequence of  FIG. 1B , which corresponds to the first series arrangement of the reset transistor  10 , transfer transistor  20  and photodiode  50 , two-point calibration of the pixel  100  may be performed using steps (a) through (h), whereas one-point calibration may be performed using steps (a) through (f) (and omitting steps (g) and (h)). 
         [0029]    As shown by initial step (a) in  FIGS. 1B-1C , a hard reset of the pixel  100  is performed by fully depleting the photodiode  50  by establishing a large reverse bias across the cathode and anode of the photodiode  50 . This reverse bias can be achieved by pulling up the voltage on the cathode of the photodiode  50  by turning on the reset transistor  10  and the transfer transistor  20  and holding the variable reset voltage (VR) at a positive voltage level (e.g., VPIX). This combination of conditions can yield: (i) a cathode voltage equal to VR-Vth 10 -Vth 20 , where Vth 10  and Vth 20  are the threshold voltages of the NMOS reset transistor  10  and the NMOS transfer transistor  20 , respectively; and (ii) a floating diffusion (FD) region voltage equal to VR-Vth 10 . 
         [0030]    Thereafter, as shown by step (b), the TG voltage is lowered to thereby isolate the photodiode while the photocurrent begins to integrate at the diode capacitance. Then, in step (c), the voltage of the floating diffusion (FD) region is reset to a low voltage level by driving the variable reset voltage (VR) high-to-low before the FD region is electrically isolated at step (d) by switching the reset gate voltage RG high-to-low. Next, as shown by step (e), the transfer gate voltage TG is increased to a medium voltage (mid TG) to thereby establish a first subthreshold current, which flows from the photodiode (PD) to the floating diffusion (FD) region for a relatively short duration (e.g., t short ). Then, as shown by step (f), the transfer gate voltage TG is lowered to thereby isolate the FD region and enable read-out of a first FD calibration voltage via the second series arrangement of the NMOS source follower (SF)  30  and the NMOS select transistor  40 . Next, as shown by steps (g)-(h), to support two-point calibration, the transfer gate voltage TG is again increased to the medium voltage (mid TG) for a somewhat longer duration (e.g., t long ) before it is lowered to isolate the FD region and enable read-out of a second FD calibration voltage. 
         [0031]    As will be understood by those skilled in the art, the calibration operations highlighted by  FIGS. 1B-1C  advantageously do not depend upon the photocurrent, as highlighted by the current directions shown in steps (e) and (g). In contrast, during conventional photocurrent integration, the photocurrent and TG subthreshold current flow in opposite directions and compensate each other. However, to make the calibration process photocurrent independent, the subthreshold current direction (during calibration) is inversed, which means the photocurrent and subthreshold current flow in the same direction to thereby partially discharge the reversed-biased capacitance of the photodiode (PD). During calibration, the reverse voltage across the PD varies, but the FD voltage is not affected and the value of the FD voltage depends only on the TG voltage applied, the KNPT and the LOGS. 
         [0032]    As determined by the inventors herein, to achieve one-point calibration, the FD voltage can be read after a fixed time duration and its value can be used for KNPT determination and LOGS correction. Moreover, for two-point calibration, two sub-threshold currents of different duration (or achieved in response to unequal TG voltages) may be established by setting the correct lengths of t short  and t long  at steps (e) and (g). The duration of t short  should be long enough to obtain a proper value of the subthreshold current, but not too long to fully charge the FD region or fully discharge the PD. In addition, because the subthreshold current may decrease exponentially with time, the time required for t long  may be greater than t short  but nonetheless short enough to avoid fully discharging the PD. 
         [0033]    Precise subthreshold currents through the transfer transistor  20  may not be necessary, but adequate timing and voltages must be chosen in order to support operation of the transfer transistor  20  in subthreshold. In two-point calibration, the time windows can be adjusted to provide approximately one order of magnitude difference between the subthreshold currents generated during steps (e) and (g) or an approximately 100 mV voltage difference between the TG voltages during these steps (where the differences between t long  and t short  may no longer apply). During one-point calibration, the duration of the subthreshold current should be short enough to maintain operation in subthreshold but long enough to provide adequate sensitivity to subthreshold variations so that the calibration voltage can be used to provide correction of both KNPT and LOGS variation. In contrast, during two-point calibration, one of the calibration voltages is used to calibrate the KNPT while the difference between the first and second calibration voltages provides an estimate of the LOGS. The timing for the calibration sequence of  FIG. 1B  and the voltages of the PD and FD are shown by  FIG. 1C . A CDS readout is still necessary to eliminate the variations in the pixel transistors, particularly since the offset variations in the source follower (SF) transistor  30  can be substantial. CDS may be introduced by measuring the FD reset voltage at step (d). 
         [0034]    Embodiments of the calibration methods described hereinabove have been simulated using MOSFET transistors from a 65 nm fabrication process. Temperature, transistor and device mismatch and process variations are included in the simulation by proper setting of device corners and running Monte-Carlo simulations. The reset transistor  10  and transfer transistor  20  are included in the simulation and proper values of the PD and FD capacitances were adjusted by adding ideal capacitors, which adjust the pixel response to the one measured from fabricated pixels. The simulated linear-logarithmic pixel response before calibration for different temperatures and process variations is highlighted by the graph of  FIG. 2 . In this graph, the linear response is essentially the same for all pixels, but quite variable in the logarithmic region of operation. The simulated effect of one-point calibration is shown by  FIG. 3 , where the following conditions apply: (i) a target pixel response to illumination is determined by simulation at typical conditions; (ii) a linear fix function from each pixel response to the target pixel response is calculated; (iii) a single correlation function is calculated based on average or best fit to all functions calculated in (ii); and a linear-logarithmic weight function is calculated as a function of illumination. The process described herein is tailored to simulation requirements. However, when the calibration is based on measurements, the pixel response required for the first step is determined by the average pixel response across a silicon chip. As shown by  FIG. 4 , a simulated correlation coefficient (R 2 ) between KNPT voltage and the one-point calibration voltage is 0.9849, which is close to unity. Likewise, as shown by  FIG. 5 , a simulated correlation coefficient (R 2 ) between the LOGS and the one-point calibration voltage is 0.935, which is sufficiently close to unity to support calibration. 
         [0035]    Accordingly, as hereinabove described with respect to  FIGS. 1A-1C  and  2 - 5  and illustrated more fully by the flow diagram of  FIG. 1D , methods of calibrating linear-logarithmic image sensors  110  according to embodiments of the invention including performing an operation to deplete a photodiode (PD) of a pixel by establishing a strong reverse bias across the photodiode, Block  110 A. This reverse bias may be achieved by driving a floating diffusion (FD) region of the pixel to a relatively high voltage while a transfer transistor between the FD region and the PD is turned on. Thereafter, the FD region is discharged, Block  110 B, in advance of supplying the FD region with a 1 st  subthreshold current via the transfer transistor, Block  110 C. This 1 st  subthreshold current is insufficient to discharge a capacitance of the at least partially depleted PD. As shown by Block  110 D, a first calibration point may be determined by reading a 1 st  voltage of the FD region via, for example, an output stage of the pixel, which may include a source follower and select transistor in some embodiments of the invention. Next, the FD region is further supplied with a 2 nd  subthreshold current and then the 2 nd  voltage of the FD region is read, Blocks  110 E- 110 F. The quantity of charge transferred from the PD to the FD region by the 2 nd  subthreshold current may be greater than a quantity of charge transferred by the 1 st  subthreshold current. Finally, as shown by Block  110 G, two-point calibration may be performed as described above using the 1 st  and 2 nd  voltages read from the FD region of the pixel. 
         [0036]    In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.