Abstract:
Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate layer that is integrated within the chip. A transistor layer is integrated within the chip and is shielded from the substrate layer by a shielding layer. At least one transistor of a first transistor type couples the transistor layer to the shielding layer and a quiet voltage source may be coupled to the transistor of the first transistor type. At least one transistor of a second transistor type is coupled to the shielding layer. The transistor of the second transistor type may be a n-type transistor, which may be disposed within the transistor layer and the transistor of the second transistor type may be resistively coupled to the shielding layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE  
       [0001]    This application is a continuation of U.S. application Ser. No. 10/294,880 filed on Nov. 14, 2002, which makes reference to, claims priority to and claims the benefit of U.S. Provisional Patent Application Serial No. 60/402,095 filed on Aug. 7, 2002.  
         [0002]    All of the above stated applications are incorporated herein by reference in their entirety. 
     
    
     
       FIELD OF THE INVENTION  
         [0003]    Certain embodiments of the invention relate to integrated circuit (IC) designs. More specifically, certain embodiments of the invention relate to a system for reducing noise in a substrate of an integrated circuit.  
         BACKGROUND OF THE INVENTION  
         [0004]    As more and more functional blocks are added, for example, to a chip, an integrated circuit (IC) or an integrated system or device, the risk for the generation and propagation of noise between the different functional blocks or within a functional block may become quite substantial.  
           [0005]    An exemplary conventional complementary metal oxide semiconductor (CMOS) transistor arrangement is illustrated in FIG. 1. As shown in FIG. 1, the conventional CMOS transistor arrangement  10  includes an n-channel MOS (NMOS) transistor  30  and a p-channel MOS (PMOS) transistor  40 . The conventional CMOS arrangement  10  also includes a p-substrate  20  (e.g., a p-substrate). The NMOS transistor  30  is disposed in the p-substrate  20 . The NMOS transistor  30  includes a p + -body (B), an n + -source (S) and an n + -drain (D) disposed in the p-substrate  20 . A voltage source V SS    7  having a ground is coupled to the p + -body (B) and the n + -source (S) of NMOS transistor  30 . An input line  5  is coupled to a gate (G) of the NMOS transistor  30 . An output line  15  is coupled to the n + -drain (D) of the NMOS transistor  30 . The PMOS transistor  40  includes an n-well  50  that is disposed in the p-substrate  20 . The PMOS transistor  40  also includes an n + -body (B), a p + -source (S) and a p + -drain (D) disposed in the n-well  50 . A voltage source V DD    17  is coupled to the p + -source (S) and the n + -body (B) of PMOS transistor  50 . The input line  5  is also coupled to a gate of the PMOS transistor  40 . The output line  15  is also coupled to the p + -drain (D) of the PMOS transistor  40 .  
           [0006]    During normal operation of the conventional CMOS transistor arrangement  10 , the voltage sources V SS    7 , V DD    17  may be noisy. For example, the noise may be caused by other circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources V SS    7 , V DD   17 . High swing or high power devices such as, data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. The noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit) which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip.  
           [0007]    In the NMOS transistor  30 , if the voltage source V SS    7  is noisy, then the noise may propagate to the p-substrate  20  via, for example, at least through the resistive coupling  9  between the p + -body (B) and the p-substrate  20 . In the PMOS transistor  40 , if the voltage source V DD    17  is noisy, then the noise may propagate to the n-well  50  via the n + -body (B) of the PMOS transistor  40  via a resistive coupling  19 . The noise in the n-well  50  may propagate to the p-substrate  20  via, for example, at least the capacitive coupling  29  between the n-well  50  and the p-substrate  20 . If the noise is able to propagate to the p-substrate  20 , then noise may propagate to or otherwise affect other circuits on or off the chip that may be coupled to the p-substrate  20 .  
           [0008]    [0008]FIG. 1A shows another conventional CMOS arrangement  10 , which is similar to the conventional CMOS arrangement  10  shown in FIG. 1, except that a quieter voltage source V SS    3  is coupled to the p + -body (B) of the NMOS transistor  30  and a noisy voltage source V SS    7  is coupled to the n + -source (S) of the NMOS transistor  30 . Thus, less noise is resistively coupled from the p + -body (B) to the p-substrate  20 . To a lesser extent, noise may be capacitively coupled between the n + -source and the p-substrate  20 . Noise may be coupled from the PMOS transistor  40  to the p-substrate  20  as described above with respect to the conventional CMOS arrangement  10  as shown in FIG. 1. In the CMOS arrangement of FIG. 1A, noise may substantially propagate to the p-substrate  20 . Accordingly, there is a need to mitigate noise in the substrate of a chip.  
           [0009]    Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.  
         BRIEF SUMMARY OF THE INVENTION  
         [0010]    Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip. Aspects of the system may comprise a substrate layer that is integrated within the chip and a transistor layer that is integrated within the chip and is shielded from the substrate layer by a shielding layer. At least one transistor of a first transistor type couples the transistor layer to the shielding layer and a quiet voltage source may be coupled to the transistor of the first transistor type. At least one transistor of a second transistor type is coupled to the shielding layer.  
           [0011]    The transistor of the second transistor type may be a n-type transistor, which may be disposed within the transistor layer. The transistor of the second transistor type may be resistively coupled to the shielding layer. A first noisy voltage source may be coupled to, for example, a source of the second transistor type. The transistor of the first transistor type may be a p-type transistor, which may be disposed within the transistor layer. The transistor of the first transistor type may be capacitively coupled to the shielding layer and the shielding layer may be capacitively coupled to the substrate layer. The shielding layer may be a deep N-well, which may be disposed between the substrate layer and the transistor layer. A second noisy voltage source may be coupled to, for example, a source of the transistor of the first transistor type.  
           [0012]    These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.  
       
    
    
     BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS  
       [0013]    [0013]FIGS. 1 and 1A shows embodiments of conventional complementary metal oxide semiconductor (CMOS) transistor arrangements.  
         [0014]    [0014]FIG. 2 shows an embodiment of a CMOS transistor arrangement according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    [0015]FIG. 2 shows an embodiment of a complementary metal oxide semiconductor (CMOS) transistor arrangement  60  in accordance with the present invention. The CMOS transistor arrangement  60  may include a p-substrate  70 , a deep n-well  80 , an n-channel MOS (NMOS) transistor  90  and a p-channel MOS (PMOS) transistor  100 . The NMOS transistor  90  may include, for example, a p + -body (B), an n + -source (S) and an n + -drain (D) which may be disposed in a p-well  110 . The p-well  110  may be an isolated p-well since, for example, it may be disposed between two n-wells  120  and the deep n-well  80 . A voltage source V SS    170  having an electrical ground, may be coupled to the p + -body (B) and the n + -source (S) of the NMOS transistor  90 . An input signal line  150  may be coupled to a gate of the NMOS transistor  90 . An output signal line  160  may be coupled to the n + -drain of the NMOS transistor  90 .  
         [0016]    The PMOS transistor  100  may include, for example, an n + -body (B), a p + -source (S) and a p + -drain (D), which may be disposed in an n-well  120 . A first voltage source V DD    130  may be coupled to the p + -source (S) and a second voltage source V DD    140  may be coupled to the n + -body (B) of the PMOS transistor  100 . In one embodiment, the second voltage source V DD    140  is less noisy than the first voltage source V DD    130 . In this regard, V DD    140  may be a quieter voltage source in comparison to the voltage source V DD    130 . The input signal line  150  may be coupled to a gate of the PMOS transistor  100 . The output signal line  160  may be coupled to the p + -drain (D) of the PMOS transistor  100 .  
         [0017]    The voltage source V DD    130  and the quieter voltage source V DD    140  may be different voltage sources. The quieter voltage source V DD    140  may be a dedicated voltage source that is not coupled to some sources of noise. For example, it can be an active component of a transistor. The quieter voltage source V DD    140  may be dedicated, for example, to a guard bar for well taps or substrate taps. Alternatively, the voltage source V DD    130  and the quieter voltage source V DD    140  may be coupled to the same voltage source. However, the quieter voltage source V DD    140  may be isolated or separated from the voltage source V DD    130  so that less noise may be carried by the quieter voltage source V DD    140 .  
         [0018]    In operation, the voltage source V SS    170  and the voltage source V DD    130  may be noisy due to a number of factors, some of which are described herein. For example, the noise may be caused by other circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources V SS    170 , V DD    130 . High swing or high power devices such as, data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. The noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit) which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip and/or any associated circuitry.  
         [0019]    In accordance with the inventive CMOS transistor arrangement  60 , one source of noise is that the voltage sources V SS    170 , V DD    130  may be coupled to the sources of the NMOS transistor  90  and the PMOS transistor  100 . Thus, for example, when the circuit is in a transitional state such as during a signal transition from a high level to a low level or from a low level to a high level, a transient current may flow between the voltage sources V SS    170  and V DD    130 . Notably, if other devices (e.g., other CMOS transistor arrangements) are sharing the voltage sources V SS    170 , V DD    130 , then the noise generated by the transient current flows may be substantial.  
         [0020]    The noise in the voltage source V SS    170  may flow into the body (B) and the source (S) of the NMOS transistor  90 . The body (B) of the NMOS transistor  90  may be resistively coupled  180  to the p-well  110  and the source (S) of the NMOS transistor  90  may be capacitively coupled  190  to the p-well  110 . The resistive coupling  180  may be much more substantial than the capacitive coupling  190 . Accordingly, most of the noise in the p-well  110  may be associated with the p + -body of the NMOS transistor  90 . For the noise in the p-well  110  to reach the p-substrate  70 , the noise may need to pass through two capacitive couplings: a capacitive coupling  200  between the p-well  110  and the deep n-well  80  and a capacitive coupling  210  between the deep n-well  80  and the p-substrate  70 . Importantly, the capacitive coupling is generally fairly weak, but the capacitive coupling is even weaker when the couplings are placed in series. Thus, in this embodiment of the present invention, the resistive couplings  180 ,  200  and  210  between the p + -body (B) of the NMOS transistor  90  through to the p-substrate  70  may be replaced with a much weaker capacitive coupling.  
         [0021]    The noise in the voltage source V DD    130  may flow into the p + -source (S) of the PMOS transistor  100 . In this embodiment, the present invention may employ a quieter voltage source V DD    140  which may be coupled to the n + -body (B) of the PMOS transistor  100 . The p + -source (S) of the PMOS transistor  100  may be capacitively coupled  220  to the n-well  120  and the n + -body (B) of the PMOS transistor  100  may be resistively coupled  230  to the n-well  120 . Since the resistive coupling  230  may be more substantial than the capacitive coupling, the noise in the n-well  120  may be mostly from the quieter voltage source V DD    140 . Advantageously, the noise in the n-well  120  may be substantially reduced by connecting the quieter voltage source V DD    140  to the n + -body (B) of the PMOS transistor  100 . The n-well  120  and the deep n-well  80  may be resistively coupled  240 . Notably, the deep n-well  80  may provide a substantial amount of resistance to the noise, thereby further reducing any noise propagating through PMOS resistor  100  and reaching substrate  70 . The deep n-well  80  and the p-substrate  70  may be capacitively coupled, which may offer the noise only a weak coupling.  
         [0022]    Although illustrated in use with a CMOS transistor arrangement, the present invention need not be so limited. The present invention may also be applicable for use with other types of transistors or other types of transistor arrangements. Notably, in a an embodiment of the invention, the quiet V dd  may be used to replace a conventional V ss  without an area penalty. In this regard, the area used by the V dd  may replace the area used by the V ss , in for example, a block or standard resistor/transistor logic (RTL) arrangement. The present invention may also be applicable for use with other electrical, magnetic or electromagnetic components or circuits. Furthermore, although one or more of the embodiments described above may employ semiconductor materials (e.g., semiconductor material, compound semiconductor material, etc.), the present invention may also contemplate using other materials (e.g., ceramics, metals, alloys, superconductors, etc.) or combinations thereof. In addition, the present invention may also contemplate using different dopant types, dopant schemes or dopant concentrations other than or in addition to the above-described dopant types, dopant schemes or dopant concentrations.  
         [0023]    While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.