Abstract:
The present invention relates to a temperature detecting circuit. The temperature detecting circuit includes a first delay means for outputting a reference signal that is delayed by some time according to an input signal without being affected by variation in temperature, a second delay means for delaying the input signal in different delay time according to variation in temperature to generate a plurality of delay signals, a detecting means for comparing the reference signal and the plurality of the delay signals, respectively, to output a plurality of detecting signals, an encoder for encoding the plurality of the detecting signals into given numbers of output signals, a buffer for outputting the output signal of the encoder to the outside and receiving a control signal from the outside as an input, and a select means that can be programmed according to the control signal, for selecting one of the detecting signals according to a program state. Since the refresh periods can be differentiated depending each temperature, consumption of the standby current can be significantly reduced.

Description:
BACKGROUND  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a temperature detecting circuit and, more particularly, to a temperature detecting circuit that can be exactly implemented since trimming is possible depending on variation in process or voltage and that can significantly reduce consumption of the standby current since the refresh period is differentiated depending on temperature, in such a manner that the width of variation in temperature that can be detected by the temperature detecting circuit can be widened using a plurality of detectors, the status of the plurality of the detectors can be detected at the outside by an encoder, and one of the detectors that can detect correct temperature information by transferring fuse trimming information from the outside to the detecting means via the select means.  
           [0003]    2. Discussion of Related Art  
           [0004]    In semiconductor devices, if a device requiring a periodical refresh so as to keep data is needed, a large amount of standby current is necessary for a self-refresh. The refresh period that is actually required, however, very differs depending on temperature. If temperature is detected and the refresh period is varied depending on temperature, the standby current can be significantly reduced. The exactness of a common temperature detecting circuit, however, is lowered depending on variation in external conditions such as process, voltage, and the like.  
           [0005]    [0005]FIG. 1 is a block diagram illustrating the construction of a conventional temperature detecting circuit.  
           [0006]    A first delay means  11  receives an input signal (IN) as an input to output a reference signal (ref) depending on temperature that will be detected without being influenced by variation in operating environments such as change in process, voltage, temperature, etc. A second delay means  12  outputs a delay signal (tem) whose delay value is changed depending on variation in temperature. A detector  13  receives the reference signal (ref) from the first delay means  11  and the delay signal (tem) from the second delay means  12 , as an input and then outputs (dout) a detecting signal (det) indicating whether the delay signal (tem) is lower or higher the reference signal (ref) to the outside through a DQ buffer  14 .  
           [0007]    As such, the detection width of temperature is controlled by correcting the delay width of the first delay means  11  or the second delay means  12  using the data outputted via the DQ buffer  14 .  
           [0008]    In the conventional temperature detecting circuit constructed above, however, since only one detector is employed, the width of variation in temperature that can be detected depending on variation in process or voltage is limited. Therefore, if the width of variation in temperature that can be actually detected by a device is large, the device fails to serve as the temperature detecting circuit.  
         SUMMARY OF THE INVENTION  
         [0009]    The present invention is contrived to solve the aforementioned problems. The present invention is directed to provide a temperature detecting circuit that can widely control the width of variation in temperature depending on variation in process or voltage by use of a plurality of detectors.  
           [0010]    According to a preferred embodiment of the present invention, there is provided a temperature detecting circuit wherein the state of a plurality of detectors can be detected externally using an encoder.  
           [0011]    Further, the present invention is to provide a temperature detecting circuit that can select a detector capable of detecting correct temperature information by allowing fuse trimming information to be transferred via a select means so that correct temperature information can be transferred to a device from the outside.  
           [0012]    According to a preferred embodiment of the present invention, there is provided A temperature detecting circuit, comprising: a first delay means for outputting a reference signal that is delayed by some time according to an input signal without being affected by variation in temperature; a second delay means for delaying the input signal in different delay time according to variation in temperature to generate a plurality of delay signals; a detecting means for comparing the reference signal and the plurality of the delay signals, respectively, to output a plurality of detecting signals; an encoder for encoding the plurality of the detecting signals into given numbers of output signals; a buffer for outputting the output signal of the encoder to the outside and receiving a control signal from the outside as an input; and a select means that can be programmed according to the control signal, for selecting one of the detecting signals according to a program state.  
           [0013]    One aspect of the present invention is to provide a temperature detecting circuit, comprising: a first delay means for outputting a reference signal that is delayed by some time according to an input signal without being affected by variation in temperature; a second delay means for delaying the input signal in different delay time according to variation in temperature to generate a plurality of delay signals; a detecting means having a plurality of detectors, wherein the detector compares the reference signal and the plurality of the delay signals, respectively, to output a plurality of detecting signals; an encoder for encoding the plurality of the detecting signals into given numbers of output signals; a buffer for outputting the output signal of the encoder to the outside and receiving a control signal from the outside as an input; and a select means having a plurality of fuses that can be cut, for cutting the fuses according to the control signal and selecting one of the plurality of the detectors according to the fuse signal depending on the state of the fuse.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The above and other objects, features and advantages of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0015]    [0015]FIG. 1 is a block diagram illustrating the construction of a conventional temperature detecting circuit;  
         [0016]    [0016]FIG. 2 is a block diagram illustrating the construction of a temperature detecting circuit according to the present invention;  
         [0017]    [0017]FIG. 3 is a block diagram illustrating the detailed construction of the second delay means shown in FIG. 2 according to an embodiment of the present invention;  
         [0018]    [0018]FIG. 4 is a block diagram illustrating the detailed construction of the detecting means shown in FIG. 2 according to an embodiment of the present invention;  
         [0019]    [0019]FIG. 5 is a block diagram illustrating the detailed construction of the detector shown in FIG. 4 according to an embodiment of the present invention;  
         [0020]    [0020]FIG. 6 is a block diagram illustrating the detailed construction the encoder shown in FIG. 2 according to an embodiment of the present invention; and  
         [0021]    [0021]FIGS. 7A and 7B are block diagrams illustrating the detailed construction of the select means shown in FIG. 2 according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0022]    The present invention will now be described in detail in connection with preferred embodiments with reference to the accompanying drawings, in which like reference numerals are used to identify the same or similar parts.  
         [0023]    [0023]FIG. 2 is a block diagram illustrating the construction of a temperature detecting circuit according to the present invention.  
         [0024]    A first delay means  21  outputs a reference signal (ref) that is delayed by some time according to an input signal (IN) without being affected by variation in operating environments such as variation in temperature, etc. The reference signal (ref) is fixed to temperature to be detected and becomes a signal indicating that temperature.  
         [0025]    A second delay means  22  changes the value of the input signal (IN) that is delayed according to on variation in temperature. The second delay means  22  outputs a delay signal corresponding temperature to be detected and a plurality of delay signals (tem) corresponding to temperature for which a sufficient margin is taken into consideration on the basis of that temperature to be detected.  
         [0026]    A detecting means  23  consists of a plurality of detectors. Each of the detectors uses the reference signal (ref) inputted from the first delay means  21  and the plurality of the delay signals (tem) inputted from the second delay means  22  to detect whether the delay signal (tem) is higher or lower than the reference signal (ref), and then outputs a detecting signal (det).  
         [0027]    The detecting signal (det) outputted from the detecting means  23  has temperature information that is currently being measured in a device. In order to output such temperature information to the outside, the encoder  24  encodes temperature information to output a plurality of output signals (dout). The plurality of the output signals (dout) outputted by the encoder  24  are provided as information to the outside through a DQ buffer  26 . It is confirmed whether such information matches external environments. At this time, if actual temperature and temperature that is being recognized in the device are different, fuse information (Fuse Info) is provide to a select means  25  via the DQ buffer  26  so that the detecting means  23  within the device that actually recognizes external temperature can be selected.  
         [0028]    The select means  25  may have a programmable fuse. The select means  25  cuts the fuse depending on fuse information (Fuse Info) externally inputted, combines signals depending on the result to produce information for allowing the means  25  to select one detector that must be used by the device, and then transfers such information to the detecting means  23 . Based on information thus transferred, only one of the plurality of the detectors in the detecting means  23  is enabled and remaining detectors are disabled. Only the signal detected in the selected detector is thus outputted through the encoder  24  and the DQ buffer  26 .  
         [0029]    [0029]FIG. 3 is a block diagram illustrating the detailed construction of the second delay means shown in FIG. 2 according to an embodiment of the present invention.  
         [0030]    An inverter chain  31  delays the input signal (IN) by some time to output a first delay signal (tem 0 ). The first delay signal (tem 0 ) is delayed through first and second inverters I 31  and I 32  to become a second delay signal (tem 1 ). The second delay signal (tem 1 ) is delayed through third and fourth inverters I 33  and I 34  to become a third delay signal (tem 2 ). The third delay signal (tem 2 ) is delayed through fifth and sixth inverters I 35  and I 36  to become a fourth delay signal (tem 3 ).  
         [0031]    In the above, the delay value is extended to some degree depending on a given difference in temperature, by means of the first and second inverters I 31  and I 32 , the third and fourth inverters I 33  and I 34 , and the fifth and sixth inverters I 35  and I 36 . It is thus possible to identify the difference in temperature.  
         [0032]    [0032]FIG. 4 is a block diagram illustrating the detailed construction of the detecting means  23  shown in FIG. 2 according to an embodiment of the present invention.  
         [0033]    A first detector  41  uses the first delay signal (tem 0 ) outputted from the second delay means and the reference signal (ref) outputted from the first delay means to output a first detecting signal (det 0 ). A second detector  42  uses the second delay signal (tem 1 ) outputted from the second delay means and the reference signal (ref) outputted from the first delay means to output a second detecting signal (det 1 ). A third detector  43  uses the third delay signal (tem 2 ) outputted from the second delay means and the reference signal (ref) outputted from the first delay means to output a third detecting signal (det 2 ). A fourth detector  44  uses the fourth delay signal (tem 3 ) outputted from the second delay means and the reference signal (ref) outputted from the first delay means to output a fourth detecting signal (det 3 ).  
         [0034]    A first transfer gate T 41  outputs the first detecting signal (det 0 ) as the final detecting signal (last_det) according to the first output signal (out 0 ) of the encoder and its inverse signal (outb 0 ). A second transfer gate T 42  outputs the second detecting signal (det 1 ) as the final detecting signal (last_det) according to the second output signal (out 1 ) of the encoder and its inverse signal (outb 1 ). A third transfer gate T 43  outputs the third detecting signal (det 2 ) as the final detecting signal (last_det) according to the third output signal (out 2 ) of the encoder and its inverse signal (outb 2 ). A fourth transfer gate T 44  outputs the fourth detecting signal (det 3 ) as the final detecting signal (det) according to the fourth output signal (out 3 ) of the encoder and its inverse signal (outb 3 ).  
         [0035]    In the detecting means constructed above, at the initial stage, the first to fourth output signals (out 0  to out 3 ) are encoded by the encoder  24  and are then outputted to the outside by the DQ buffer  26 . However, only one of the first to fourth transfer gates T 41  to T 44  is turned on according to the output signal of the select means  25  by fuse information (Fuse Info) externally inputted, and only one of the detecting signals (det 0  to det 3 ) of the first to fourth detectors  41  to  44  is outputted to the outside.  
         [0036]    [0036]FIG. 5 is a block diagram illustrating the detailed construction of the detector shown in FIG. 4 according to an embodiment of the present invention.  
         [0037]    A first NAND gate  51  performs a NAND operation for an input signal (in) and the output signal of a second NAND gate  52 . A second NAND gate  52  performs a NAND operation for the reference signal (ref) and the output signal of the first NAND gate  51 . In the above, the input signal (in) is one of the first to fourth delay signals outputted from the second delay means and the reference signal (ref) is a signal inputted from the first delay means. The first transfer gate T 51  is driven according to a control signal (act) and its inverse signal (actb) to transfer the output signal of the first NAND gate  51 . Further, a latch  53  having first and second inverters I 51  and I 52  latches the output signal of the first NAND gate  51  that is transferred via the first transfer gate T 51 . A third inverter I 53  inverts the data that was latched by the latch  53  to output an inverse signal, which is a detecting signal (det).  
         [0038]    [0038]FIG. 6 is a block diagram illustrating the detailed construction the encoder  24  shown in FIG. 2 according to an embodiment of the present invention.  
         [0039]    A first inverter I 61  inverts the second detecting signal (det 2 ) outputted from the second detector of the detecting means to produce a first output signal (dout 0 ). A first NAND gate  61  performs a NAND operation for the output signal of the first inverter I 61  and the first detecting signal (det 1 ) outputted from the first detector of the detecting means. A second NAND gate  62  performs a NAND operation for the second detecting signal (det 2 ) and the third detecting signal (det 3 ) outputted from the third detector of the detecting means. A NOR gate  63  performs a NOR operation for the output signals of the first NAND gate  61  and the second NAND gate  62  to output a second output signal (dout 1 ).  
         [0040]    [0040]FIG. 7A and 7B are block diagrams illustrating the detailed construction of the select means  25  shown in FIG. 2 according to an embodiment of the present invention, wherein FIG. 7A is a circuit diagram illustrating a fuse signal generating means and FIG. 7B is a circuit diagram illustrating a select signal generating means.  
         [0041]    Referring to FIG. 7A, a first fuse F 71  is connected between the power supply terminal (Vcore) and a first node Q 71 . A first NMOS transistor N 71 ) driven by an enable signal (enable) and a second NMOS transistor N 72  driven by the potential of a second node Q 72  are connected in parallel between the first node Q 71  and the ground terminal (Vss). A first inverter I 71  inverts the potential of the first node Q 71  to decide the potential of the second node Q 72 . The potential of the second node Q 72  becomes a first fuse signal (fu 0 ). Furthermore, the potential of the second node Q 72  is inverted through the second inverter I 72  and is then outputted as a first fuse bar signal (fu 0 _b).  
         [0042]    Meanwhile, a second fuse F 72  is connected between the power supply terminal (Vcore) and a third node Q 73 . A third NMOS transistor N 73  driven by the enable signal (enable) and a fourth NMOS transistor N 74  driven by the potential of a fourth node Q 74  are connected in parallel between the third node Q 73  and the ground terminal (Vss). A third inverter I 73  inverts the potential of the third node Q 73  to decide the potential of the fourth node Q 74  and the potential of the fourth node Q 74  becomes a second fuse signal (fu 1 ). Furthermore, the potential of the fourth node Q 74  is inverted through the fourth inverter I 74  and is then outputted as a second fuse bar signal (fu 1 _b).  
         [0043]    By reference to FIG. 7B, a first NAND gate  71  performs a NAND operation for the first fuse bar signal (fu 0 _b) and the second fuse bar signal (fu 1 _b) and a fifth inverter I 75  inverts the output signal of the first NAND gate  71  to output a third output signal (out 2 ). A second NAND gate  72  performs a NAND operation for the first fuse bar signal (fu 0 _b) and the second fuse signal (fu 1 ) and a sixth inverter I 76  inverts the output signal of the second NAND gate  72  to output a first output signal (out 0 ). A third NAND gate  73  performs a NAND operation for the first fuse signal (fu 0 ) and the second fuse bar signal (fu 1 _b) and a seventh inverter I 77  inverts the output signal of the third NAND gate  73  to output a fourth output signal (out 3 ). Furthermore, a fourth NAND gate  74  performs a NAND operation for the first fuse signal (fu 0 ) and the second fuse signal (fu 1 ) and an eighth inverter I 78  inverts the output signal of the fourth NAND gate  74  to output a second output signal (out 1 ).  
         [0044]    The select means constructed above selectively cuts the first and second fuses F 71  and F 72  according to fuse information (Fuse Info) inputted through the DQ buffer  26  and, according to its result, selects one of the plurality of the detectors  31  to  34  constituting the detecting means  23 . The operation when only the fuse F 71  is cut according to fuse information (Fuse Info) will now be described by way of an example.  
         [0045]    If the first NMOS transistor N 71  is turned on by the enable signal (enable), the first node Q 71  keeps a LOW state since the first fuse F 71  is cut. The potential of the first node Q 71  keeping the LOW state is inverted to a HIGH state through the first inverter I 71  and the potential of the second node Q 72  keeping the HIGH state becomes the potential of the first fuse signal (fu 0 ). Further, the second NMOS transistor N 72  is turned on by the potential of the second node Q 72  and the potential of the second node Q 72  is inverted to a LOW state through the second inverter I 72  to become the potential of the first fuse bar signal (fu 0 _b).  
         [0046]    Meanwhile, if the third NMOS transistor N 73  is turned on by the enable signal (enable), the third node Q 73  keeps a HIGH state since the second fuse F 72  keeps a normal state. The potential of the third node Q 73  keeping the HIGH state is inverted to a LOW state through the third inverter I 73  and the potential of the fourth node Q 74  keeping the LOW state becomes the potential of the second fuse signal (fu 1 ). Furthermore, the fourth NMOS transistor N 74  is turned off by the potential of the fourth node Q 74  and the potential of the fourth node Q 74  is inverted to a HIGH state through the fourth inverter I 74  to become the potential of the second fuse bar signal (fu 2 _b).  
         [0047]    The first fuse bar signal (fu 0 _b) of the LOW state and the second fuse bar signal (fu 1 _b) of the HIGH state are inputted to the first NAND gate  71 . The first NAND gate  71  then performs a NAND operation for the two signals (fu 0 _b and fu 1 _b) to output a signal of a HIGH state. The output signal of the first NAND gate  71  keeping the HIGH state is inverted to the LOW state through the fifth inverter I 75  to become the third output signal (out 2 ). The first fuse bar signal (fu 0 _b) of the LOW state and the second fuse signal (fu 1 ) of the LOW state are inputted to the second NAND gate  72 . The second NAND gate  72  performs a NAND operation for the two signals (fu 0 _b and fu 1 ) to output a signal of a HIGH state. The output signal of the second NAND gate  72  keeping the HIGH state is inverted to a LOW state through the sixth inverter I 76  to become the first output signal (out 0 ). The first fuse signal (fu 0 ) of the HIGH state and the second fuse bar signal (fu 1 _b) of the HIGH state are inputted to the third NAND gate  73 . The third NAND gate  73  performs a NAND operation for the two signals (fu 0  and fu 1 _b) to output a signal of a LOW state. The output signal of the third NAND gate  73  keeping the LOW state is inverted to a HIGH state through the seventh inverter I 77  to become the fourth output signal (out 3 ). The first fuse signal (fu 0 ) of the LOW state and the second fuse signal (fu 1 ) of the LOW state are inputted to the fourth NAND gate  74 . The fourth NAND gate  74  performs a NAND operation for the two signals (fu 0  and fu 1 ) to output a signal of a HIGH state. The output signal of the fourth NAND gate  74  keeping the HIGH state is inverted to a LOW state through the eighth inverter I 78  to become a second output signal (out 1 ).  
         [0048]    As described above, according to the present invention, the width of variation in temperature that can be detected by a temperature detecting circuit using a plurality of detectors. The state of the plurality of the detectors can be detected using the encoder from the outside. Fuse trimming information is transferred from the outside to the detector though the select means to select one of the detectors that can detect correct temperature information. Therefore, the present invention has new effects that it can implement a correct temperature detecting circuit since trimming is possible depending on variation in process or voltage and it can significantly reduce consumption of the standby current since the refresh period can be differentiated depending on each temperature.  
         [0049]    Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.