Abstract:
A method of fabricating a replacement metal gate structure for a CMOS device. The method includes forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess on the nFET portion and a recess on the pFET portion; depositing a first layer of titanium nitride into the recesses on the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion; depositing a gate metal onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion to fill the remainder of the recesses.

Description:
RELATED APPLICATION 
       [0001]    This application is related to U.S. patent application Ser. No. ______ (Attorney docket No. YOR920120149US1), entitled “REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE”, filed even date herewith. 
     
    
     BACKGROUND 
       [0002]    The exemplary embodiments relate to a manufacturing process for replacement metal gate CMOS devices and, more particularly, relate to a simpler manufacturing process to obtain quarter-gap pFET. 
         [0003]    Today&#39;s integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field Effect Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. 
         [0004]    Device performance may be enhanced by the use of metal gates and high-k dielectric materials. 
       BRIEF SUMMARY 
       [0005]    The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, a method of fabricating a replacement metal gate structure for a CMOS device on a semiconductor substrate. The method comprising: forming a high dielectric constant (high-k) dielectric on an nFET portion of the CMOS device and on a pFET portion of the CMOS device; forming a dummy gate structure on the high-k dielectric of the nFET portion of the CMOS device and on the high-k dielectric of the pFET portion of the CMOS device, each of the dummy gate structures comprising a layer of nitride, a layer of polysilicon or amorphous silicon and a nitride hard mask; forming spacers on the dummy gate structures; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess bounded by the spacers on the nFET portion and a recess bounded by the spacers on the pFET portion, the recesses having high-k dielectric on a bottom of each of the recesses; depositing a first layer of titanium nitride into the recesses in contact with the high-k dielectric on the nFET portion and pFET portion, the first layer of titanium nitride being present only on the high-k dielectric in the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only to expose the high-k dielectric; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion, the second layer of titanium nitride being in direct contact with the high-k dielectric in the nFET portion and in direct contact with the first layer of titanium nitride in the pFET portion; depositing titanium aluminum onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion; and filling the remainder of the cavity on the nFET portion and pFET portion with a metal different from titanium aluminum. 
         [0006]    According to a second aspect of the exemplary embodiments, there is provided a method of fabricating a replacement metal gate structure for a CMOS device on a semiconductor substrate. The method comprising: forming a high dielectric constant (high-k) dielectric on an nFET portion of the CMOS device and on a pFET portion of the CMOS device; forming a dummy gate structure on the high-k dielectric of the nFET portion of the CMOS device and on the high-k dielectric of the pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess on the nFET portion and a recess on the pFET portion, each of the recesses containing a high-k gate dielectric only on a bottom of each of the recesses; depositing a first layer of titanium nitride into the recesses on the nFET portion and pFET portion, the first layer of titanium nitride being present only on the high-k gate dielectric; removing the first layer of titanium nitride from the nFET portion only; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion, the second layer of titanium nitride being in direct contact with the high-k gate dielectric on the nFET portion and in direct contact with the first layer of titanium nitride on the pFET portion; and depositing a gate metal onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion and filling the remainder of the recesses on the nFET portion and pFET portion with the gate metal. 
         [0007]    According to a third aspect of the exemplary embodiments, there is provided a CMOS device comprising: a semiconductor substrate having an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion; the nFET portion having a gate structure, the gate structure comprising a recess filled with a high-k dielectric only on a bottom of the recess, a titanium nitride layer on the high-k dielectric and a gate metal filling the remainder of the recess; and the pFET portion having a gate structure, the gate structure comprising a recess filled with a high-k dielectric only on a bottom of the recess, a first titanium nitride layer on the high-k dielectric, a second titanium nitride layer on the first titanium nitride layer and a gate metal filling the remainder of the recess. 
     
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         [0008]    The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: 
           [0009]      FIGS. 1 to 11  illustrate a first method of the exemplary embodiments of forming a CMOS structure wherein: 
           [0010]      FIG. 1  illustrates dummy gate structures on nFET and pFET portions of a semiconductor substrate; 
           [0011]      FIG. 2  illustrates forming spacers on the dummy gate structures; 
           [0012]      FIG. 3  illustrates forming an interlayer dielectric layer; 
           [0013]      FIG. 4  illustrates planarizing to remove the hard nitride mask of the dummy gate structures; 
           [0014]      FIG. 5  illustrates removing the polysilicon (or amorphous silicon) of the dummy gate structures; 
           [0015]      FIG. 6  illustrates removing the titanium nitride of the dummy gate structures; 
           [0016]      FIG. 7  illustrates depositing titanium nitride; 
           [0017]      FIG. 8  illustrates an optional low temperature oxidation process; 
           [0018]      FIG. 9  illustrates removing the titanium nitride from the nFET portion only; 
           [0019]      FIG. 10  illustrates a first process for depositing an additional layer of titanium nitride on both the nFET and pFET portions; and 
           [0020]      FIG. 11  illustrates deposition of titanium aluminum alloy and aluminum on both the nFET and pFET portions. 
           [0021]      FIGS. 12 and 13  illustrate a second method of the exemplary embodiments of forming a CMOS structure beginning with the structure shown in  FIG. 9  wherein: 
           [0022]      FIG. 12  illustrates a second process for depositing an additional layer of titanium nitride on both the nFET and pFET portions; and 
           [0023]      FIG. 13  illustrates deposition of titanium aluminum alloy and aluminum on both the nFET and pFET portions. 
           [0024]      FIG. 14  is a flow chart illustrating the process flow of the exemplary embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    Typically, small FET devices with high-k dielectrics and metal gates require expensive complicated processing. It would be useful to find ways to simplify the fabrication process, while maintaining most of the performance benefits offered by such advanced structures. In addition, reduction of gate leakage current and improvement in thermal stability of nFET devices. 
         [0026]    Referring to the Figures in more detail, and particularly referring to  FIGS. 1 to 13 , there is disclosed one or more methods for fabricating CMOS devices according to the exemplary embodiments. 
         [0027]    In  FIG. 1 , gate stack structures are formed which become dummy gate structures in a replacement gate process of the exemplary embodiments. Blanket layers of a gate dielectric, preferably a high dielectric constant (“high-k”) dielectric material, titanium nitride, polysilicon (could also be amorphous silicon), and a nitride hard mask are deposited on a semiconductor substrate. Tantalum nitride may be used in place of the titanium nitride. 
         [0028]    For purposes of illustration and not limitation, the gate dielectric may be HfO 2  and may be deposited by an atomic layer deposition (ALD) process or chemical vapor deposition (CVD) process to a thickness of about 2 nanometers (nm). The titanium nitride may be deposited by a physical vapor deposition (PVD) process or an ALD process to a thickness of about 2 nm. The polysilicon (or amorphous silicon) may be conventionally deposited to a thickness of about 100 nanometers (nm). The nitride hard mask, such as silicon nitride, may be conventionally deposited to a thickness of about 50 nm. 
         [0029]    The various layers of gate dielectric, titanium nitride, polysilicon and nitride hard mask may be conventionally patterned by a reactive ion etching (RIE) process resulting in a semiconductor structure  100  including a gate structure  102  on an nFET portion of the semiconductor structure  100  and a gate structure  104  on a pFET portion of the semiconductor structure  100 . Each of the gate structures  102 ,  104  includes a gate dielectric layer  106 , a titanium nitride layer  108 , a polysilicon (or amorphous silicon) layer  110  and a hard mask layer  112 . 
         [0030]    The semiconductor structure  100  further includes a semiconductor substrate  114  which may be a bulk semiconductor material or may be a semiconductor on insulator (SOI). The semiconductor material making up the semiconductor substrate may be a silicon material or any other semiconductor material. 
         [0031]    Each of the gate structures  102 ,  104  may further include a source  116  and a drain  118  adjacent to the gate structures  102 ,  104  as is known in the art. Separating the nFET portion from the pFET portion may be an isolation region  120 . 
         [0032]    Referring now to  FIG. 2 , spacers  122  have been conventionally formed on the nFET gate structure  102  and the pFET gate structure  104 . Portions  126  of sources  116  not blocked by spacers  122  and portions  128  of drains  118  not blocked by spacers  122  may be ion implanted  124  followed by a dopant activation anneal. 
         [0033]    An interlayer dielectric (ILD)  130  may be deposited and planarized, stopping on the nitride hard mask  112  of the gate structures  102 ,  104  as shown in  FIG. 3 . The ILD may be any conventional ILD such as an oxide. 
         [0034]    The planarization process may continue to remove the nitride hard mask and expose the polysilicon  110  as shown in  FIG. 4 . 
         [0035]    Referring now to  FIG. 5 , the polysilicon  110  may be removed from the gate structures  102 ,  104 . The polysilicon  110  may be removed by a wet etching process such as tetramethylammonium hydroxide (TMAH), tetraethylammonium Hydroxide (TEAH) or ammonium hydroxide (NH 4 OH). The polysilicon  110  may alternatively be removed by a combination of wet etching, using any of the foregoing etchants, and RIE. The polysilicon  110  is schematically illustrated in  FIG. 5  as being removed in one piece for the purpose of illustration but it should be understood that the polysilicon  110  will actually be gradually removed upon continued exposure to the etchant. 
         [0036]    Subsequently, as shown in  FIG. 6 , the titanium nitride layer  108  may be removed from the gate structures  102 ,  104  by a wet etching process that is selective to the HfO 2  gate dielectric. Suitable etchants may include a solution of hydrogen peroxide (H 2 O 2 ), NH 4 OH and water or a solution of H 2 O 2  and water. The titanium nitride layer  108  is schematically illustrated in  FIG. 6  as being removed in one piece for the purpose of illustration but it should be understood that the titanium nitride layer  108  will actually be gradually removed upon continued exposure to the etchant. Once the titanium nitride layer  108  is removed from gate structures  102 ,  104 , the only layer left from the original gate structures  102 ,  104  is gate dielectric  106 . The recesses  132 ,  134  resulting from the removal of the titanium nitride layer  108 , polysilicon layer  110  and hard nitride mask layer  112  will be filled with work function and metal gate materials to result in permanent gate structures  102 ,  104  in the nFET portion and pFET portion of the semiconductor structure  100 . Recesses  132 ,  134  may also be called trenches. 
         [0037]    Referring now to  FIG. 7 , titanium nitride  136  may be deposited by a PVD, ALD or CVD process including within recesses  132 ,  134 . Although not as preferred, tantalum nitride may be used in place of titanium nitride  136 . The thickness of the titanium nitride may be about 5 nm. Oxygen vacancies in HfO 2  may be passivated by removing the dummy titanium nitride layer  108  ( FIG. 6 ) and depositing the fresh titanium nitride layer  136 . 
         [0038]    It may be desirable to subject the semiconductor structure  100  to a low temperature oxidation step as indicated in  FIG. 8 . The low temperature oxidizing, indicated by arrows  138 , may be at a temperature of about 400° C. for about 1 to 10 minutes in an oxidizing atmosphere. The low temperature oxidizing is an optional process step but may be useful to modify the titanium nitride to be titanium-rich. 
         [0039]    A photoresist mask  140  has been defined to block the pFET portion of the semiconductor structure  100 . Thereafter, the titanium nitride  136  is removed from the nFET portion by an etchant selective to the HfO 2  gate dielectric as shown in  FIG. 9 . A suitable etchant for removing the titanium nitride  136  may be a solution of hydrogen peroxide (H 2 O 2 ), NH 4 OH and water or a solution of H 2 O 2  and water. Removal of the titanium nitride  136  includes removal from the recess  132  leaving only gate dielectric  106  within recess  132 . The titanium nitride  136  is schematically illustrated in  FIG. 9  as being removed in one piece for the purpose of illustration but it should be understood that the titanium nitride  136  will actually be gradually removed upon continued exposure to the etchant. 
         [0040]    Referring now to  FIG. 10 , the photoresist mask  140  is conventionally stripped and then 2 to 3 nm thick layer of titanium-rich titanium nitride  142  is formed on the semiconductor structure  100 . The titanium nitride  142  may be deposited by a PVD process wherein the proportions of titanium and nitrogen are adjusted so that titanium-rich titanium nitride  142  is deposited. Titanium-rich means that there is greater than 50 atomic percent titanium and less than 50 atomic percent nitrogen. The semiconductor structure  100  may then undergo an optional low temperature oxidation indicated by arrows  143  at 400° C. for 1 to 10 minutes. 
         [0041]    Thereafter, now referring to  FIG. 11 , a titanium aluminum alloy  144  may be deposited in the recesses  132 ,  134  in direct contact with the titanium-rich titanium nitride  142  followed by a metal  146  such as aluminum or tungsten to fill the remainder of the recesses  132 ,  134 . The semiconductor structure  100  may then be conventionally planarized to remove any overburden of titanium nitride  142 , titanium aluminum alloy  144  and aluminum  146 . The titanium aluminum alloy  144  may be deposited by PVD or ALD to a thickness of about 3 nm. The aluminum or tungsten  146  may be deposited by PVD (for Al) and CVD (for W) to fill the remaining thickness of the recesses  132 ,  134 . 
         [0042]    The last steps of the exemplary embodiments may be modified as illustrated in  FIGS. 12 and 13 . This alternative begins with the semiconductor structure  100  illustrated in  FIG. 9 . Then, referring to  FIG. 12 , the photoresist mask  140  is conventionally stripped and then 2 to 3 nm thick layer of titanium nitride  148  (about a 50/50 mixture based on atomic percent) is formed everywhere on the semiconductor structure  100 ′. The titanium nitride  148  lines the walls of the recesses  132 ,  134 . The titanium nitride  148  may be conformally deposited by an ALD process. As-deposited ALD titanium nitride  148  may have a composition of about 50 atomic percent titanium and about 50 atomic percent nitrogen. The semiconductor structure  100 ′ may then undergo a low temperature oxidation at 400° C. for 1 to 10 minutes indicated by arrows  149  to render the titanium nitride  148  titanium-rich when combined with the oxygen gettering effect of titanium aluminum in the downstream process. While not wishing to be held to any particular theory, it is believed that the low temperature oxidation causes some of the nitrogen to be replaced with oxygen to form a titanium oxynitride. 
         [0043]    Thereafter, now referring to  FIG. 13 , a titanium aluminum alloy  144  may be deposited in the recesses  132 ,  134  in direct contact with the titanium-rich titanium nitride  148  followed by aluminum or tungsten  150  to fill the remainder of the recesses  132 ,  134 . The semiconductor structure  100 ′ may then be conventionally planarized to remove any overburden of titanium nitride  142 , titanium aluminum alloy  144  and aluminum or tungsten  150 . 
         [0044]    The semiconductor structures  100 ,  100 ′ may undergo additional processing such as back end of the line processing to form finished semiconductor structures. 
         [0045]    A summary of the exemplary embodiments is illustrated in  FIG. 14 . In a first processing step, box  202 , dummy gate structures are formed on nFET and pFET portions of a semiconductor substrate. 
         [0046]    Thereafter, spacers may be formed on the dummy gate structures, box  204 . 
         [0047]    An ILD is deposited between the dummy gate structures and planarized, stopping on the dummy gate structures, box  206 . 
         [0048]    The hard nitride mask, gate polysilicon (or amorphous silicon) and titanium nitride of the dummy gate structures are removed, boxes  208 ,  210 ,  212 , respectively, leaving recesses in the nFET and pFET portions. 
         [0049]    A layer of titanium nitride is deposited in the recesses, box  214 , and in an optional step, may undergo low temperature oxidation, box  216 . 
         [0050]    The layer of titanium nitride is then removed from the recess in the nFET portion only, box  218 . 
         [0051]    Another layer of titanium nitride may then be deposited in the recesses, box  220 . This layer of titanium nitride may be titanium-rich as deposited or may need an optional low temperature oxidation, box  222 , to become titanium-rich. 
         [0052]    Then, additional metals are deposited to fill the recesses including titanium aluminum and then aluminum or tungsten, boxes  224  and  226  respectively. 
         [0053]    Other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.