Abstract:
Provided are a memory device providing fast booting and a memory system including the same. The memory device may include a nonvolatile first memory that stores boot data; a buffer that provides the boot data to a host via a volatile memory interface; and a controller that controls transmission of the boot data from the first memory to the buffer in response to a command from the host.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2015-0152534, filed on Oct. 30, 2015, and Korean Patent Application No. 10-2016-0024712, filed on Feb. 29, 2016, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entireties by reference. 
       BACKGROUND 
       [0002]    Example embodiments of the inventive concepts relate to a memory device and a memory system including the same, and more particularly, to a memory device providing fast booting and a memory system including the same. 
         [0003]    Conventionally, a separate storage interface may be used in order to obtain data required for booting during a boot process for booting a host. In such a case, when the boot process is initiated, data required for booting is read out from the separate storage interface. Here, a memory space may be used to store codes for a host to control the corresponding storage interface and a time period may be required for executing the codes. Therefore, continuous efforts have been made to reduce the booting time. 
       SUMMARY 
       [0004]    Example embodiments of the inventive concepts provide a non-volatile memory device, a system including the same, and/or a method of operating the same. For example, at least some example embodiments relate to a non-volatile memory device providing fast booting, a system including the same, and/or a method of operating the same. 
         [0005]    According to another example embodiment of the inventive concepts, there is provided a memory module including at least one nonvolatile memory; and a memory device, where the memory device includes a buffer that provides a same interface as that of the volatile memory; a volatile first memory that stores boot data; and a controller that controls transmission of the boot data from the first memory to the buffer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0007]      FIG. 1  is a block diagram showing a host and a non-volatile memory device, according to an example embodiment; 
           [0008]      FIG. 2  is a block diagram of a modified example of the non-volatile memory device of  FIG. 1 , according to an example embodiment; 
           [0009]      FIG. 3  is a block diagram of a non-volatile memory device according to an example embodiment; 
           [0010]      FIG. 4A  is a block diagram of a memory according to an example embodiment; 
           [0011]      FIG. 4B  is a block diagram of a memory according to an example embodiment; 
           [0012]      FIG. 5  is a flowchart of a method of operating a memory device, according to an example embodiment; 
           [0013]      FIGS. 6A and 6B  are flowcharts of methods of operating the non-volatile memory device of  FIG. 3 , according to example embodiments; 
           [0014]      FIGS. 7 and 8  are flowcharts of methods of operating the memory devices of  FIGS. 4A and 4B , according to an example embodiment; 
           [0015]      FIG. 9  is a diagram showing operations, performed over time, between a host processor and a non-volatile memory device; 
           [0016]      FIG. 10  is a diagram showing operations, performed over time, between a host processor and a non-volatile memory device according to an example embodiment; 
           [0017]      FIG. 11  is a diagram showing operations, performed over time, between a host processor and a non-volatile memory device according to an example embodiment; and 
           [0018]      FIG. 12  is a diagram showing a memory module including a non-volatile memory device, according to an example embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIG. 1  is a block diagram showing a host  100 , a non-volatile memory device  200 , and a memory interface  300 , according to an embodiment. 
         [0020]    As shown in  FIG. 1 , the host  100  may include a host processor  110 , and the non-volatile memory device  200  may include a buffer  210 , a non-volatile memory  220 , and a non-volatile memory controller  230 . 
         [0021]    The non-volatile memory controller  230  may be implemented by at least one semiconductor chip disposed on a printed circuit board. The semiconductor chip may be an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor or any other device capable of responding to and executing instructions in a defined manner. The non-volatile memory controller  230  may execute instructions that configure the non-volatile memory controller  230  as a special purpose processor to load boot data from the non-volatile memory  220  to the buffer  210  based on a command from the host  100 . The non-volatile memory controller  230  may improve the function of the system itself by allowing the host processor  110  to read out the boot data  211  from the buffer  210  at high speed, and thus a time taken to perform a boot process may be reduced. 
         [0022]    Likewise, the host processor  110  may be implemented by at least one semiconductor chip disposed on a printed circuit board. The semiconductor chip may be an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor or any other device capable of responding to and executing instructions in a defined manner. The host processor  110  may execute instructions that configure the host processor  110  as a special purpose processor to load the boot data from the non-volatile memory device  200 , and use the loaded boot data to boot the host  100 . 
         [0023]    A memory interface  300 , via which the host  100  and the non-volatile memory device  200  communicate with each other, may be an interface of a memory device (or a memory system or a memory module) that does not include a non-volatile memory (e.g., an interface of a volatile memory device). For example, the host processor  110  may transmit a command to the buffer  210  using a memory controller (not shown) included in the host  100  that is connected to the memory interface  300 , and the buffer  210  may perform a task in response to the received command. Furthermore, the non-volatile memory controller  230  may control the buffer  210  and the non-volatile memory  220  based on the received command, where the buffer  210  and the non-volatile memory  220  may perform tasks under the control of the non-volatile memory controller  230 . 
         [0024]    The buffer  210  is a component capable of exchanging commands and data with the host  100 , and the buffer  210  may support the memory interface  300 . The memory interface  300  may be a volatile memory interface. More particularly, the memory interface  300  may be a dynamic random access memory (DRAM) interface. An interface of a volatile memory, such as a DRAM, may exhibit a high transmission speed. Therefore, the buffer  210  of the memory interface  300  may exchange data with the host  100  at high speed. For example, the non-volatile memory device  200  may be a non-volatile dual in-line memory module (NVDIMM) that provides a DRAM interface. The memory interface  300  may be a DDR3 NVDIMM, a DDR4 NVDIMM, but is not limited thereto. 
         [0025]    As described below, the buffer  210  may receive at least a portion of boot data  221  from the non-volatile memory  220  under the control of the non-volatile memory controller  230  and may store the boot data  221  in a desired (or, alternatively, a pre-set) region in correspondence to a pre-set address in the host  100 . The desired (or, alternatively, the pre-set) address in the host  100  may be the address of a region accessed by the memory interface  300 . Due to the memory interface  300  providing a high transmission speed, the host processor  110  may read out the boot data  211  from the buffer  210  at high speed, and thus a time taken to perform a boot process may be reduced. 
         [0026]    According to an example embodiment, the buffer  210  is a memory capable of writing or reading out data faster than the non-volatile memory  220  and, for example, may include a volatile memory, such as a static random access memory (SRAM), a DRAM, a latch, a flip-flop, and a register, or a non-volatile memory, such as a NAND flash memory, a vertical NAND (VNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), and a spin transfer torque RAM (STT-RAM). Hereinafter, for convenience of explanation, the buffer  210  is described as a DRAM supporting a DRAM interface. However, example embodiments of the inventive concepts are not limited thereto. 
         [0027]    The non-volatile memory  220  may refer to a memory or a memory device that retains data stored therein even if power supply is stopped. Therefore, even if power supplied to the non-volatile memory  220  is blocked, data stored in the non-volatile memory  220  may be retained. For example, the non-volatile memory  220  may be a NAND flash memory, a VNAND flash memory, a NOR flash memory, a RRAM, a PRAM, a MRAM, a FRAM, or a STT-RAM, but is not limited thereto. The non-volatile memory device  200  may be embodied to have a three-dimensional (3D) array structure. Furthermore, instead of a semiconductor memory device, the non-volatile memory  220  may be embodied as a magnetic disk device. Example embodiments of the inventive concepts may be applied not only to a flash memory having a charge trapping layer including a conductive floating gate, but also to a charge trap flash (CTF) having a charge trapping layer including an insulation film. 
         [0028]    As shown in  FIG. 1 , the non-volatile memory  220  may include the boot data  221 . The boot data  221  includes data necessary for booting a system. For example, the boot data  221  may include setting data regarding devices included in the host  100  or devices communicably connected to the host  100 . Since the boot data  221  includes data required by a boot process, the boot data  221  may be stored in the non-volatile memory  220 , where the host processor  110  may normally boot a system including the host  100  and the non-volatile memory device  200  by executing or referring to the boot data  221  at the beginning of a boot process. 
         [0029]    As shown in  FIG. 1 , the host  100  may be communicably connected to the buffer  210  of the non-volatile memory device  200 . The buffer  210  may receive a command, an address, and/or data from the host  100  (or the host processor  110 ) via the memory interface  300 . For example, the buffer  210  may receive a boot data request command from the host processor  110  and transmit the boot data  211  to the host  100 . 
         [0030]    As shown in  FIG. 1 , the non-volatile memory controller  230  of the non-volatile memory device  200  is communicably connected to the non-volatile memory  220  and the buffer  210 . The non-volatile memory controller  230  may read out data stored in the buffer  210  or write data to the buffer  210  by controlling the buffer  210 . Furthermore, the non-volatile memory controller  230  may read out data stored in the non-volatile memory  220  or write data to the non-volatile memory  220  by controlling the non-volatile memory  220 . For example, the non-volatile memory controller  230  may read out at least a portion of the boot data  221  stored in the non-volatile memory  220 . The non-volatile memory controller  230  may write the at least some of the boot data  221  read out from the non-volatile memory  220  (e.g., the boot data  211 ) to the buffer  210 . 
         [0031]    Although  FIG. 1  shows that the buffer  210 , the non-volatile memory  220 , and the non-volatile memory controller  230  as independent components, it is merely an example, and two or more of the buffer  210 , the non-volatile memory  220 , and the non-volatile memory controller  230  may be embodied as a single hardware component. Furthermore, the non-volatile memory controller  230  may be an independent processor or a digital circuit including a plurality of logic gates. 
         [0032]      FIG. 2  is a block diagram of a modified example  200 ′ of the non-volatile memory device  200  of  FIG. 1 , according to an example embodiment. 
         [0033]    As shown in  FIG. 2 , the non-volatile memory device  200 ′ may include a buffer  210 ′, a non-volatile memory  220 ′, a non-volatile memory controller  230 ′, a bus interface block  240 ′, a command register  250 ′, a status register  260 ′, a volatile memory  270 ′, a scrambler  280 ′, and an error correcting code (ECC) encoder  290 ′. The buffer  210 ′, the non-volatile memory  220 ′, and the non-volatile memory controller  230 ′ may perform functions identical or similar to those of the corresponding components in the embodiment shown in  FIG. 1 . 
         [0034]    The bus interface block  240 ′ may be communicably connected to the command register  250 ′ and the status register  260 ′. The bus interface block  240 ′ may provide a communication channel to the host  100  of  FIG. 1 . In other words, referring to  FIG. 1 , the non-volatile memory device  200  may communicate with the host  100  not only via a channel provided by the memory interface  300 , but also via a channel provided by the bus interface block  240 ′. The host  100  and the bus interface block  240 ′ may communicate with each other via a bus different from a bus for the memory interface  300  connected to the buffer  210 ′. For example, the bus interface block  240 ′ may support a system management bus (SMBus). 
         [0035]    The command register  250 ′ may be accessed by the host  100  via the memory interface  300  or the bus interface block  240 ′ and may be directly accessed by the non-volatile memory controller  230 ′. The command register  250 ′ may store a command received from the host  100 . A command received from the host  100  may include a write command and a read command and may include a boot data request. 
         [0036]    The status register  260 ′ may be accessed by the host  100  via the memory interface  300  or the bus interface block  240 ′ and may be directly accessed by the non-volatile memory controller  230 ′. The non-volatile memory controller  230 ′ may store data in the status register  260 ′, and the host  100  may read out data stored in the status register  260 ′. For example, the non-volatile memory controller  230 ′ may store boot data ready in the status register  260 ′, and the host  100  may read out the boot data ready stored in the status register  260 ′. 
         [0037]    The volatile memory  270 ′ may store boot data or data obtained by processing boot data under the control of the non-volatile memory controller  230 ′. For example, as described below with reference to  FIG. 3 , the volatile memory  270 ′ may provide a storage space for the scrambler  280 ′ or the ECC encoder  290 ′. To this end, the volatile memory  270 ′ may be connected to the non-volatile memory controller  230 ′ and may be communicably connected to the scrambler  280 ′ and/or the ECC encoder  290 ′. For example, the volatile memory  270 ′ may refer to a SRAM, a DRAM, a latch, a flip-flop, or a register, but is not limited thereto. Although the memory  270 ′ has been described above as a volatile memory  270 ′, example embodiments of the inventive concepts are not limited thereto. That is, the volatile memory  270 ′ may perform a same function even if the volatile memory  270 ′ is replaced with a non-volatile memory, such as a NAND flash memory, a VNAND flash memory, a NOR flash memory, a RRAM, a PRAM, a MRAM, a FRAM, or a STT-RAM. 
         [0038]    The scrambler  280 ′ may be a logic element or a circuit that employs an algorithm for randomizing a transmitted code sequence based on, for example, an exclusive OR operation between an original code sequence to be transmitted and a random signal. The scrambler  280 ′ may communicate with the volatile memory  270 ′ and may write data to the volatile memory  270 ′ or may read out data stored in the volatile memory  270 ′. Furthermore, the scrambler  280 ′ may communicate with the buffer  210 ′ and may write data to the buffer  210 ′ or may read out data stored in the buffer  210 ′. 
         [0039]    The scrambler  280 ′ may randomize boot data included in the volatile memory  270 ′ and write the randomized boot data to the buffer  210 ′. Since boot data may be encrypted by the scrambler  280 ′, security thereof may be improved, and the integrity of signals transmitted via the memory interface  300  may be improved. Scrambled boot data may be descrambled by a descrambler that may be included in the host  100 . 
         [0040]    The ECC encoder  290 ′ may be a logic device or a circuit that adds a code for correcting an error that may occur in data. For example, the ECC encoder  290 ′ may generate and add a parity bit, thereby performing encoding for correcting an error in the data. The ECC encoder  290 ′ may communicate with the volatile memory  270 ′ and may write data to the volatile memory  270 ′ or may read out data stored in the volatile memory  270 ′. Furthermore, the ECC encoder  290 ′ may communicate with the buffer  210 ′ and may write data to the buffer  210 ′ or read out data stored in the buffer  210 ′. Therefore, the ECC encoder  290 ′ may check and correct an error of boot data stored in the volatile memory  270 ′, thereby improving reliability of the non-volatile memory device  200 ′. 
         [0041]    In some example embodiments, the NVM controller  230 ′ may execute instructions that configure the NVM controller  230 ′ to perform the functions of the scrambler  280 ′ and/or the ECC encoder  290 ′. 
         [0042]      FIG. 3  is a block diagram of a non-volatile memory device  200   a  according to an embodiment. Hereinafter, operations of a scrambler  280   a  and an ECC encoder  290   a  will be described with reference to  FIG. 3 . Although  FIG. 3  shows that the non-volatile memory device  200   a  includes both the scrambler  280   a  and the ECC encoder  290   a , the non-volatile memory device  200   a  may include just one of either the scrambler  280   a  or the ECC encoder  290   a , according to some example embodiments. 
         [0043]    Referring to  FIG. 3 , the non-volatile memory controller  230   a  may receive boot data D_BOOT from a non-volatile memory  220   a  and write the boot data D_BOOT to a volatile memory  270   a . Furthermore, the volatile memory  270   a  may temporarily store boot data  271   a.    
         [0044]    The scrambler  280   a  may read out the boot data D_BOOT from the volatile memory  270   a  and scramble the boot data D_BOOT. The scrambler  280   a  may write scrambled boot data D_SCR to a buffer  210   a.    
         [0045]    Similar to the scrambler  280   a , the ECC encoder  290   a  may read out boot data D_BOOT from the volatile memory  270   a  based on a read-out command and encode the boot data D_BOOT. The ECC encoder  290   a  may write encoded boot data D_ENC to the buffer  210   a . Furthermore, the ECC encoder  290   a  may transmit the encoded boot data D_ENC to the scrambler  280   a . In some example embodiments, the scrambler  280   a  may write encoded and scrambled boot data D_ENCSCR to the buffer  210   a  rather than the scrambled boot data D_SCR. 
         [0046]      FIGS. 4A and 4B  are block diagrams of memory devices according to example embodiments. 
         [0047]    In detail,  FIG. 4A  is a block diagram for describing an example that a host processor  110   b  accesses a command register  250   b  and/or a status register  260   b  via a buffer  210   b , whereas  FIG. 4B  is a block diagram for describing an example that a host processor  110   c  accesses a command register  250   c  and/or a status register  260   c  via a bus interface block  240   c.    
         [0048]    Referring to  FIGS. 2 and 4A , as described above with reference to  FIG. 2 , the command register  250   b  may be accessed by a host  100   b  (or the host processor  110   b ) and a non-volatile memory controller  230   b.    
         [0049]    For example, as shown in  FIG. 4A , the host  100   b  may write a boot data request C_BTReq to the command register  250   b  via a bus connected to the buffer  210   b . The non-volatile memory controller  230   b  may read out the boot data request C_BTReq stored in the command register  250   b , thereby controlling an operation for transmitting boot data to the host  100   b.    
         [0050]    As described above with reference to  FIG. 2 , the status register  260   b  may be accessed by the host  100   b  (or the host processor  110   b ) and the non-volatile memory controller  230   b . For example, the non-volatile memory controller  230   b  may write a boot data ready S_BTRdy to the status register  260   b . The host  100   b  may read out the boot data ready S_BTRdy stored in the status register  260   b  via a bus connected to the buffer  210   b.    
         [0051]      FIG. 4B  is a block diagram showing that a host  100   c  accesses the command register  250   c  and/or the status register  260   c  via a separate bus, that is, the bus interface block  240   c  instead of the buffer  210   b.    
         [0052]    As shown in  FIG. 4B , the host  100   c  may write a boot data request C_BTReq to the command register  250   c  via the bus interface block  240   c . A non-volatile memory controller  230   c  may read out the boot data request C_BTReq stored in the command register  250   c.    
         [0053]    Furthermore, according to an example embodiment as shown in  FIG. 4B , the non-volatile memory controller  230   c  may write a boot data ready S_BTRdy to the status register  260   c . The host  100   c  may read out the boot data ready S_BTRdy stored in the status register  260   c  via the bus interface block  240   c.    
         [0054]    Although  FIGS. 4A and 4B  show the operations related to the command register  250   b  or  250   c  and the status register  260   b  or  260   c  as different operations, the two operations may be successively performed. For example, the host  100   b  or  100   c  may store a boot data request C_BTReq in the command register  250   b  or  250   c  and, when a boot data ready S_BTRdy is written to the status register  260   b  or  260   c  after the non-volatile memory controller  230   b  or  230   c  completes loading boot data to the buffer  210   b  or  210   c , the host processor  110   b  or  110   c  may recognize completion of loading of the boot data by reading out the boot data ready S_BTRdy stored in the status register  260   b  or  260   c  and may be booted by using the boot data written to the buffer  210   b  or  210   c.    
         [0055]      FIG. 5  is a flowchart of a method of operating a memory device, according to an example embodiment. 
         [0056]    Referring to  FIGS. 1 and 5 , in operation S 110 , the non-volatile memory device  200  may be powered. 
         [0057]    In operation S 130 , the non-volatile memory controller  230  may read out boot data, which is stored in the non-volatile memory  220  in advance, from the non-volatile memory  220 . 
         [0058]    In operation S 150 , the non-volatile memory controller  230  may load the boot data to the buffer  210 . 
         [0059]    In operation S 170 , the host processor  110  may proceed with a booting operation using the boot data loaded to the buffer  210 . 
         [0060]      FIGS. 6A and 6B  are flowcharts of methods of operating the non-volatile memory device  200   a  of  FIG. 3 , according to example embodiments. In detail,  FIG. 6A  shows an operation of a memory device including the ECC encoder  290   a  of  FIG. 3 , whereas  FIG. 6B  shows an operation of a memory device including the scrambler  280   a  of  FIG. 3 . 
         [0061]    Referring to  FIGS. 3 and 6A , in operation S 210   a , the non-volatile memory device  200   a  may be powered. 
         [0062]    In operation S 220   a , the non-volatile memory controller  230   a  may read out boot data from the non-volatile memory device  200   a.    
         [0063]    Next, in operation S 230   a , for ECC encoding, the non-volatile memory controller  230   a  may write the boot data to the volatile memory  270   a . In operation S 240   a , the ECC encoder  290   a  may read out the boot data written to the volatile memory  270   a  and encode the boot data. In operation S 250   a , the ECC encoder  290   a  may write encoded boot data to the buffer  210   a.    
         [0064]    Next, in operation S 260   a , the host processor  110  may perform a booting operation by using the encoded boot data written to the buffer  210   a.    
         [0065]    Referring to  FIG. 6B , in operation S 210   b , the non-volatile memory device  200   a  may be powered. 
         [0066]    In operation S 220   b , the non-volatile memory controller  230   a  may read out boot data from the non-volatile memory device  200   a.    
         [0067]    Next, to perform scrambling, in operation S 230   b , the non-volatile memory controller  230   a  may write the boot data to the volatile memory  270   a . In operation S 240   b , the scrambler  280   a  may read out the boot data written to the volatile memory  270   a  and scramble the boot data. In operation S 250   b , the scrambler  280   a  may write scrambled boot data to the buffer  210   a.    
         [0068]    Next, in operation S 260   b , the host processor  110  may perform a booting operation by using the scrambled boot data written to the buffer  210   a.    
         [0069]    Although  FIGS. 6A and 6B  show the ECC encoding and the scrambling as two different operations for convenience of explanation, the two operations may be successively performed as described above with reference to  FIG. 3 . For example, boot data that is input to the volatile memory  270   a , encoded by the ECC encoder  290   a , and scrambled by the scrambler  280   a  may be written to the buffer  210   a.    
         [0070]      FIG. 7  is a flowchart of a method of operating the memory devices of  FIGS. 4A and 4B , according to an example embodiment. 
         [0071]    In detail,  FIG. 7  shows operations of the non-volatile memory devices  200   b  and  200   c  respectively including the command register  250   b  and  250   c . As described above with reference to  FIGS. 4A and 4B , the host processor  110   b  and  110   c  may access the command register  250   b  and  250   c  via the buffer  210   b  and  210   c  or via the bus interface block  240   c.    
         [0072]    Referring to  FIGS. 4A, 4B and 7 , in operation S 310   a , the host processor  110   b  may write a ‘boot data request’ to the command register  250   b.    
         [0073]    In operation S 320   a , the non-volatile memory controller  230   b  may read out the ‘boot data request’ from the command register  250   b.    
         [0074]    In operation S 330   a , the non-volatile memory controller  230   b  may recognize that the host  100   b  requests boot data and may write the boot data to the buffer  210   b  in response to the ‘boot data request’. 
         [0075]    Next, in operation S 360   a , the host processor  110   b  may perform a booting operation using the boot data written to the buffer  210   b.    
         [0076]      FIG. 8  is a flowchart of a method of operating the memory devices of  FIGS. 4A and 4B , according to an example embodiment. 
         [0077]    In detail,  FIG. 8  shows operations of the non-volatile memory devices  200   b  and  200   c  respectively including the status registers  260   b  and  260   c . As described above with reference to  FIGS. 4A and 4B , the host processor  110   b  and  110   c  may access the status registers  260   b  and  260   c  via the buffer  210   b  and  210   c  or via the bus interface block  240   c.    
         [0078]    Referring to  FIGS. 4A, 4B and 8 , in operation S 330   b , the non-volatile memory controller  230   b  may write boot data to the buffer  210   b.    
         [0079]    In operation S 340   b , the non-volatile memory controller  230   b  may write a ‘boot data ready’ to the status register  260   b.    
         [0080]    In operation S 350   b , the host processor  110   b  may read out the ‘boot data ready’ from the status register  260   b.    
         [0081]    Therefore, the host  100   b  may recognize that boot data is prepared by the non-volatile memory controller  230   b , and thus, in operation S 360   b , the host processor  110   b  may perform a booting operation by using the boot data loaded to the buffer  210   b.    
         [0082]      FIG. 9  is a diagram showing operations, performed over time, between a host processor and a non-volatile memory device. 
         [0083]    In detail,  FIG. 9  shows data flows that occur over time between the host processor  110  of  FIG. 1  and the buffer  210 ′, the non-volatile memory controller  230 ′, and the non-volatile memory  220 ′ included in the non-volatile memory device  200 ′ of  FIG. 2 . 
         [0084]    Referring to  FIGS. 2 and 9 , in operation T 110 , the non-volatile memory device  200 ′ is powered. 
         [0085]    In operation T 120 , the non-volatile memory controller  230 ′ may transmit a boot data read-out command to the non-volatile memory  220 ′. 
         [0086]    In operation T 130 , the non-volatile memory controller  230 ′ may read out boot data stored in the non-volatile memory  220 ′. 
         [0087]    In operation T 140 , the non-volatile memory controller  230 ′ may transmit a boot data write command and boot data to the buffer  210 ′, thereby writing the boot data to the buffer  210 ′. 
         [0088]    In operation T 180 , a host processor  110 ′ may receive the boot data from the buffer  210 ′ (operation T 180 ) and, in operation T 190 , the host processor  110 ′ may perform a booting operation using the boot data. 
         [0089]      FIG. 10  is a diagram showing operations, performed over time, between a host processor and a non-volatile memory device according to an embodiment. 
         [0090]    In detail,  FIG. 10  is a diagram showing operations, performed over time, between the host processor  110  of  FIG. 1  and the buffer  210   a , the non-volatile memory controller  230   a , the non-volatile memory  220   a , the volatile memory  270   a , the ECC encoder  290   a , and the scrambler  280   a  included in the non-volatile memory device  200   a  of  FIG. 3 , according to an embodiment. 
         [0091]    Referring to  FIGS. 3 and 10 , in operation T 210 , the memory device  200   a  is powered. 
         [0092]    In operation T 220 , the non-volatile memory controller  230   a  may transmit a boot data read-out command to the non-volatile memory  220   a.    
         [0093]    In operation T 230 , the non-volatile memory controller  230   a  may read out boot data stored in the non-volatile memory  220   a.    
         [0094]    In operation T 240 , the non-volatile memory controller  230   a  may store the boot data in the volatile memory  270   a.    
         [0095]    In operation T 250 , the non-volatile memory controller  230   a  may transmit a boot data write command and the boot data read out from the non-volatile memory  220   a  to the volatile memory  270   a.    
         [0096]    The ECC encoder  290   a  and the scrambler  280   a  may receive original boot data from the volatile memory  270   a . Here, the ECC encoder  290   a  and the scrambler  280   a  may transmit read-out commands to the volatile memory  270   a  and receive the boot data. 
         [0097]    In operation T 260 , the ECC encoder  290   a  may perform ECC encoding with regard to the received boot data. Further, the scrambler  280   a  may scramble the received boot data. As described above, the ECC encoding and the scrambling may be performed successively or independently. 
         [0098]    In operation T 270 , the ECC encoder  290   a  and the scrambler  280  may write ECC encoded and/or scrambled boot data to the buffer  210   a , respectively. Here, the ECC encoder  290   a  and the scrambler  280   a  may transmit a write command and processed boot data to the buffer  210   a.    
         [0099]    Next, in operations T 280  and T 290 , a host processor  110   a  may receive boot data loaded to the buffer  210   a  and perform a booting operation. Here, as described above, the host processor  110   a  may transmit a read-out command to the buffer  210   a , may receive boot data, and may descramble scrambled data by using a descrambler included in a host. 
         [0100]      FIG. 11  is a diagram showing operations, performed over time, between a host processor and a non-volatile memory device according to an example embodiment. 
         [0101]    In detail,  FIG. 11  is a diagram showing operations, performed over time, between the host processors  110   b  and  110   c  of  FIGS. 4A and 4B  and the buffers  210   b  and  210   c , the non-volatile memory controllers  230   b  and  230   c , the non-volatile memories  220   b  and  220   c , the command registers  250   b  and  250   c , and the status registers  260   b  and  260   c  included in the non-volatile memory devices  200   b  and  200   c  of  FIGS. 4A and 4B , according to an embodiment. 
         [0102]    Referring to  FIGS. 4A and 11 , in the non-volatile memory device  200   b , boot data may be stored in the buffer  210   b  according to a command from the host processor  110   b.    
         [0103]    In operation T 310 , the host processor  110   b  may write ‘boot data request’ to the command register  250   b  of the non-volatile memory device  200   b . Here, as described above with reference to  FIGS. 4A and 4B , the host processor  110   b  may access the command register  250   b  via the buffer  210   b  or the bus interface block  240   c  of  FIG. 4 . Furthermore, the host processor  110   b  may store the ‘boot data request’ in the command register  250   b , thereby requesting boot data to the non-volatile memory device  200   b  or the non-volatile memory controller  230   b.    
         [0104]    In operation T 320 , the non-volatile memory controller  230   b  may read out the ‘boot data request’ stored in the command register  250   b.    
         [0105]    In operation T 330 , in response to the ‘boot data request,’ the non-volatile memory controller  230   b  may transmit a boot data read-out command to the non-volatile memory  220   b.    
         [0106]    In operation T 340 , the non-volatile memory controller  230   b  may read out boot data from the non-volatile memory  220   b.    
         [0107]    In operation T 350 , the non-volatile memory controller  230   b  may load the read-out boot data to the buffer  210   b.    
         [0108]    When the non-volatile memory controller  230   b  completes loading the boot data to the buffer  210   b , in operation T 360 , the non-volatile memory controller  230   b  may write information indicating that transmission of the boot data is completed to the status register  260   b . The information may be written as the non-volatile memory controller  230   b  transmits a ‘boot data ready’ and a write command to the status register  260   b.    
         [0109]    Next, in operation T 370 , the host processor  110   b  may access the status register  260   b  and read out data corresponding to the ‘boot data ready’. Here, as described above with reference to  FIGS. 4A and 4B , the host processor  110   b  may access the status register  260   b  or  260   c  via the buffer  210   b  or  210   c  or may access the status register  260   b  or  260   c  via the bus interface block  240   c . Furthermore, the host processor  110   b  may read out the ‘boot data ready’ from the status register  260   b.    
         [0110]    When the ‘boot data ready’ is read out, in operation T 380 , the host processor  110   b  may transmit a read-out command to the buffer  210   b  and receive boot data from the buffer  210   b.    
         [0111]    In operation T 390 , the host processor  110   b  may perform a booting operation using the received boot data. 
         [0112]    According to an example embodiment, a non-volatile memory device may include the ECC encoder  290   a  and/or the scrambler  280   a  of  FIG. 3  and the command register  250   b  and/or the status register  260   b  of  FIG. 4A . 
         [0113]    Referring to  FIG. 2 , a host may request boot data via the command register  250 ′ and, when, the non-volatile memory controller  230 ′ receives the boot data from the non-volatile memory  220 ′ and writes the boot data to the volatile memory  270 ′ based on the request, the boot data may be ECC encoded by the ECC encoder  290 ′, scrambled by the scrambler  280 ′, and written to the buffer  210 ′. When the scrambler  280 ′ finishes writing the boot data, the non-volatile memory controller  230 ′ may indicate boot data preparation status via the status register  260 ′, and then the host processor  110 ′ may perform a booting operation by using the boot data. 
         [0114]      FIG. 12  is a diagram showing a memory module  400  including a non-volatile memory device, according to an example embodiment. 
         [0115]    Referring to  FIG. 12 , the memory module  400  may be applied to a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small-outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully-buffered DIMM (FBDIMM), a rank-buffered DIMM (RBDIMM), a load-reduced DIMM (LRDIMM), a non-volatile DIMM (NVDIMM), a mini-DIMM, a micro-DIMM, etc. 
         [0116]    As shown in  FIG. 12 , the memory module  400  may include a printed circuit board  410 , a plurality of memory chips  420 , a non-volatile memory device  430 , and a connector  440 . The plurality of memory chips  420  and the non-volatile memory device  430  may communicate with a memory controller outside the memory module  400  via the connector  440 . 
         [0117]    Each of the plurality of memory chips  420  is a memory device and may include a volatile memory, such as a static random access memory (SRAM), a DRAM, a latch, a flip-flop, and a register. Although it is described below that each of the memory chips  420  includes a DRAM, example embodiments of the inventive concepts are not limited thereto. 
         [0118]    The non-volatile memory device  430  may include a non-volatile memory and a buffer. The non-volatile memory may store boot data used by a host (or a host processor) accessing the memory module  400  during a booting operation in a non-volatile manner. The buffer may provide a same interface as those of the memory chips  420  and may be accessed by the host. At the beginning of a booting operation, boot data stored in the non-volatile memory device  430  may be loaded to the buffer by a non-volatile memory controller (not shown), and the host may receive the boot data stored in the buffer via a same interface as those of the memory chips  420  via the connector  440 . 
         [0119]    While example embodiments of the inventive concepts have been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.