Abstract:
A low reflection driver is provided for a high speed simultaneous bi-directional transmission line/data bus which is designed such that units at both ends of the transmission line/data bus can transmit data at any time without waiting for the bus to become available so that the baud rate of the bus is increased. A push-pull current source driver for the bi-directional simultaneous data bus provides greater flexibility for an output voltage swing, a matching impedance and bandwidth compensation.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates generally to a low reflection driver for a high speed simultaneous bi-directional transmission line/data bus which is designed such that units at both ends of the transmission line/data bus can transmit data at any time without waiting for the bus to become available so that the baud rate of the bus is increased. The present invention also relates generally a PCB (printed circuit board) having thereon at least the low reflection driver for the high speed simultaneous bi-directional transmission line/data bus and a method of transmitting high speed simultaneous bi-directional data over a transmission line/data bus. 
   A push-pull current source driver for the bi-directional simultaneous data bus provides greater flexibility for an output voltage swing, a matching impedance and bandwidth compensation. The push-pull current source driver minimizes external components such as an analog delay line and provides an easy PCB (printed circuit board) design. 
   2. Discussion of the Prior Art 
     FIG. 1  illustrates a conventional simultaneous bi-directional data bus structure and system consisting of identical units, Unit A and Unit B, at opposite ends of a data bus/transmission line TL having a characteristic impedance Z 0 . Each unit has a driver and a receiver. 
   The driver is similar to an inverter with two resistors wherein Rpa=Rna=Rpb=Rnb=Z 0 , the characteristic impedance of the transmission line TL. Pa, Pb are pfets, and Na and Nb are nfets. 
   Table 1 (second and third lines) shows the voltages at CA and CB when Va and Vb are at different logic states. 
   
     
       
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               Va 
               Vb 
               Pa 
               Na 
               Pb 
               Nb 
               CA 
               CB 
                 
             
             
                 
             
           
           
             
               Logic 0 
               Logic 0 
               ON 
               OFF 
               ON 
               OFF 
               Vcc 
               Vcc 
               State 0 
             
             
               (0 V) 
               (0 V) 
             
             
               Logic 0 
               Logic 1 
               ON 
               OFF 
               OFF 
               ON 
               Vcc/2 
               Vcc/2 
               State 1 
             
             
               (0 V) 
               (Vcc) 
             
             
               Logic 1 
               Logic 0 
               OFF 
               ON 
               ON 
               OFF 
               Vcc/2 
               Vcc/2 
               State 2 
             
             
               (Vcc) 
               (0 V) 
             
             
               Logic 1 
               Logic 1 
               OFF 
               ON 
               OFF 
               ON 
               0 
               0 
               State 3 
             
             
               (Vcc) 
               (Vcc) 
             
             
                 
             
           
        
       
     
   
   In operation, unit A can detect the logic signal Vb sent from the unit B based on the voltage on CA and the logic state at Va, e.g. if Va=0 and CA is Vcc, Vb is determined as logic 0 (State 0), and if Va=1 and CA is 0, Vb is determined as logic 1 (State 3). 
   The problems with the prior art driver structure are: 
   1. Impedance Mismatch: When the data rate is high, the impedance match of the transmission line TL and the termination is very important. If the impedances are mismatched, reflection occurs, which seriously increases jitter and error bits. When Va or Vb are at Vcc or 0V, the transmission line TL has a good impedance match because Rpa=Rna=Rpb=Rnb=Z 0 , the nfet is turned on completely, presenting a very low impedance, the pfet is cut off, presenting a very high impedance, or the nfet is cut off, presenting a very high impedance, and the pfet is turned on completely, presenting a very low impedance. But when the voltage on Va or Vb sweeps across Vcc/2, both the nfet and the pfet are in a saturation mode, presenting a high impedance, and the termination impedance at that moment is much higher than Z 0  the characteristic impedance of TL. If at that moment, a transition arrives at CA or CB, the impedance mismatch results in a large reflection. A problem with impedance matching in the simultaneous bi-directional data bus occurs when an input signal edge arrives at the same time the driver is switching states, which results in the output impedance mismatching the transmission line characteristic impedance, resulting in a serious signal reflection. 
   2. Parasitic Capacitance: Parasitic capacitance on CA or CB increases the coming signal rise time and fall time, resulting in increased jitter. 
   SUMMARY OF THE INVENTION 
   The present invention provides a push-pull current source driver for a bi-directional simultaneous data bus that has very low reflection and provides greater flexibility for an output voltage swing, a matching impedance and bandwidth compensation. The push-pull current source driver minimizes external components such as an analog delay line and provides an easy PCB (printed circuit board) design. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a conventional simultaneous bi-directional data bus structure and system consisting of identical units, Unit A and Unit B, at opposite ends of a data bus/transmission line TL having a characteristic impedance Z 0 . 
       FIG. 2  illustrates a simultaneous bi-directional data bus structure and system pursuant to the present invention consisting of identical units, Unit A and Unit B, at opposite ends of a data bus/transmission line TL, each having switching current sources. 
       FIG. 3  is a detailed schematic of a sinking current source pursuant to the present invention. 
       FIG. 4  is a detailed schematic of a sourcing current source pursuant to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention provides a new driver structure as shown in  FIG. 2  to solve the problems of impedance mismatch and parasitic capacitance. 
     FIG. 2  illustrates a simultaneous bi-directional data bus structure and system pursuant to the present invention consisting of identical units, Unit A and Unit B, at opposite ends of a data bus/transmission line TL, each having switching current sources. Each unit has a driver and a receiver, and the output of the receiver is directed to a post process circuit as is known in the art. 
   In operation, unit A can detect the logic signal Vb sent from the unit B based on the voltage on CA and the logic state at Va. Referring to Table 2 below, e.g. if Va=0 and CA is Vcc/2, Vb is determined as logic 0 (State 1), and if Va=1 and CA is Vcc/2, Vb is determined as logic 1 (State 3). 
   In the new driver structure of  FIG. 2 , R 1   a =R 2   a =R 1   b =R 2   b =2 Z 0 , and I 1   a , I 2   a , I 1   b  and I 2   b  are switching current sources. I 1   a  and I 1   b  are identical sourcing current sources, and I 2   a  and I 2   b  are identical sinking current sources. The input VA controls the turn on/off of I 1   a  and I 2   a , each of which has transition compensation. The input Vb controls the turn on/off of I 1   b  and I 2   b , each of which has transition compensation. I 1   a , I 2   a , I 1   b  and I 2   b  provide the same amount of current I 0 . 
   Similar to Table 1, Table 2 shows the operation of the new driver. 
   
     
       
             
             
             
             
             
             
             
             
             
           
         
             
                 
             
             
               Va 
               Vb 
               I1a 
               I2a 
               I1b 
               I2b 
               CA 
               CB 
                 
             
             
                 
             
           
           
             
               Logic 0 
               Logic 0 
               ON 
               OFF 
               ON 
               OFF 
               Vcc/2 + I0 * Z0 
               Vcc/2 + I0 * Z0 
               State 0 
             
             
               (0 V) 
               (0 V) 
             
             
               Logic 0 
               Logic 1 
               ON 
               OFF 
               OFF 
               ON 
               Vcc/2 
               Vcc/2 
               State 1 
             
             
               (0) 
               (Vcc) 
             
             
               Logic 1 
               Logic 0 
               OFF 
               ON 
               ON 
               OFF 
               Vcc/2 
               Vcc/2 
               State 2 
             
             
               (Vcc) 
               (0 V) 
             
             
               Logic 1 
               Logic 1 
               OFF 
               ON 
               OFF 
               ON 
               Vcc/2 − I0 * Z0 
               Vcc/2 − I0 * Z0 
               State 3 
             
             
               (Vcc) 
               (Vcc) 
             
             
                 
             
           
        
       
     
   
   According to the network theory, on A side, the impedance terminating the transmission line TL is R 1   a , R 2   a , I 1   a  and I 2   a  in parallel, on B side the impedance terminating the transmission line TL is R 1   b , R 2   b , I 1   b  and I 2   b  in parallel. Since the current sources always present a high impedance, the terminal impedances at CA and CB are determined substantially solely by respectively R 1   a  and R 2   a  in parallel, and R 1   b  and R 2   b  in parallel, and are always at the characteristic impedance Z 0  of the transmission line TL because R 1   a , R 2   a , R 1   b  R 2   b  have the resistance of 2 Z 0 , such that the transmission line TL has a good impedance match at both ends. 
   The voltage swing at CA, CB is 2*I 0 *Z 0 , which can be adjusted by changing the value of the current I 0  to meet the requirement of a LVDS (low voltage digital system) for high data rate systems. 
   The high speed simultaneous bi-directional driver at each terminal end of the transmission line TL comprises a p side driver and an n side driver, which are serially connected between the voltage supply Vcc and ground, with the connection between the serially connected drivers being connected to the transmission line. Each of the drivers has an output impedance of twice the characteristic impedance Z 0  of the transmission line so that the total output impedance of the driver matches the transmission line characteristic impedance. Each driver unit has a resistor having a resistance value of twice the transmission line characteristic impedance and a switching current source in parallel. Since the impedance of a current source is much higher than the impedance of the resistor, the total impedance of the driver is always substantially equal to the characteristic impedance regardless of whether the current course is turned on or off so that the driver has excellent impedance matching and very low signal reflection at all times including when an input signal arrives at the same time the driver is switching states. 
   Resistors with zero voltage coefficiency and low temperature coefficiency should be selected for R 1   a , R 2   a , R 1   b  and R 2   b  in  FIG. 2 . For applications with a large environmental temperature range, each of the resistors R 1   a , R 2   a , R 1   b  and R 2   b  can consist of two resistors in series with opposite temperature coefficients so that a zero or very low temperature coefficiency can be obtained. 
   The resistors of current technologies have almost a zero voltage coefficient (for example, Salicide-blocked and salicided resistors) so that when the signal voltage transients or changes to different voltage levels, the impedance is always constant and is equal to the characteristic impedance. Also current technologies provide resistors with a very low temperature coefficient such as 1e−4/C°, so the resistance is quite stable with temperature variation. If required, a zero resistance temperature coefficient can be attained by using two resistors with opposite sign temperature coefficients in series. 
   A set of programmable compensation capacitors Cn 1 , Cn 2 , Cnk, or Cp 1 , Cp 2 , Cpk, are provided in the driver to compensate for parasitic capacitance and to accelerate transitions to higher speeds. 
   In very high speed applications, the parasitic capacitance may slow down the rising and falling edges of the current switching, and a voltage follower and current source trigger can be used to compensate for the parasitic capacitance of the current source. 
   The push-pull current source driver illustrated in  FIG. 2  minimizes external components required in prior art circuits, such as a large and expensive programmable bi-directional analog delay line, which made the prior art circuits difficult to implement on a PCB (printed circuit board) design. The push-pull current source driver illustrated in  FIG. 2  eliminates the large programmable bi-directional analog delay line, and accordingly provides an easy PCB (printed circuit board) design. A PCB design might incorporate all of the components illustrated in  FIG. 2  mounted on a single PCB, or unit A could be provided on a first PCB connected by the transmission line TL to unit B provided on a second PCB. 
     FIG. 3  is a detailed schematic of a sinking current source, and  FIG. 4  is a detailed schematic of a sourcing current source. The circuit of  FIG. 4  is similar to the circuit of  FIG. 3 , but the pfets and nfets are reversed. 
   Referring to  FIG. 3 , each sinking current source includes a pfet device P 0 s, with its gate coupled to Vin, is coupled to the power supply Vcc, with the pfet device being coupled through first, second and third resistors Rgn 1 , Rgn 2  and Rgn 3  to ground 0V, with a plurality of programmable pfet devices P 1 , P 2 , Pk and series connected compensating capacitors Cn 1 , Cn 2 , Cnk being connected in parallel with the second resistor Rgn 2 , and the connection between the first and second resistors Rgn 1 , Rgn 2  being connected to the gate of an nfet device N 0 . 
   In  FIG. 3 , N 0  is the main nfet with the source connecting to 0V and the drain connecting to CA or CB, and the gate-source voltage Vgn=Vcc*Rgn 1 /(Rgn 1 +Rgn 2 +Rgn 3 ) when Vin is at logic 0 and P 0 s is turned on. 
   The width and length of N 0  and the values of Rgn 1 , Rgn 2  and Rgn 3  are chosen to meet the following requirements:
         1. Ids of N 0  is I 0  when Vgn 1 =Vcc*Rgn 1 /(Rgn 1 +Rgn 2 +Rgn 3 ).   2. Vgn 1 −Vthn (the threshold voltage of N 0 )&lt;(Vcc−I 0 *Z 0 )/2, so that N 0  is at a saturation region/mode when it is turned on.       

   Cn 1 , Cn 2  . . . Cnk are a set of preset compensation capacitors. When a logic low is applied to one or more of the gates of P 1 , P 2  . . . Pk, the corresponding capacitors are selected. At the moment when Vin is transiting from a logic high to a logic low, the resistor Rgn 2  is shorted by the compensation capacitors temporally, the gate voltage of N 0  can reach the peak value of Vgn 2  at that moment, then the gate voltage of N 0  decays to Vgn 1 .
 
 Vgn 2= Vcc*Rgn 1/( Rgn 1+ Rgn 3).
 
   The peak voltage can compensate for the parasitic capacitance of N 0  and decrease the current rising time of N 0 . It should be noted that Vgn 2  must meet the requirement of
 
 Vgn 2− Vthn &lt;( Vcc−I 0* Z 0)/2 so that N 0  is at saturation region.
 
   Referring to  FIG. 4 , each sourcing current source includes an nfet device N 0   s , with its gate coupled to Vin, is coupled to ground 0V, with the nfet device being coupled through first, second and third resistors Rgp 1 , Rgp 2 , Rgp 3  to the power supply Vcc, with a plurality of programmable nfet devices N 1 , N 2 , Nk and series connected compensating capacitors Cp 1 , Cp 2 , Cpk being connected in parallel with the second resistor Rgp 2 , and the connection between the first and second resistors being connected to the gate of a pfet device P 0 . 
   In  FIG. 4 , P 0  is the main pfet with the source connecting to Vcc and the drain connecting to CA or CB, the gate-source voltage Vgp=Vcc*Rgp 1 /(Rgp 1 +Rgp 2 +Rgp 3 ) when Vin is at logic 1 and N 0 s is turned on. The width and length of P 0  and the values of Rgp 1 , Rgp 2  and Rgp 3  are selected to meet the following requirements.
         1. Ids of P 0  is I 0  when Vgp 1 =Vcc*Rgp 1 /(Rgp 1 +Rgp 2 +Rgp 3 ).   2. Vgp 1 −Vthp&lt;(Vcc−I 0 *Z 0 )/2, where Vthp is the threshold voltage of P 0 .       

   Therefore P 0  is at saturation region when it is turned on. Cp 1 , Cp 2  . . . Cpk are a set of preset compensation capacitors. When logic high is applied to one or more of the gates of N 1 , N 2  . . . Nk, the corresponding capacitors are selected. At the moment when Vin is transiting from logic low to logic high, the resistor Rgp 2  is shorted by the compensation capacitors temporally, the gate voltage of P 0  can reach the peak value of Vgp 2  at that moment, then the gate voltage of P 0  decays to Vgp 1 .
 
 Vgp 2= Vcc*Rgp 1/( Rgp 1+ Rgp 3).
 
   The peak voltage can compensate for the parasitic capacitance of P 0  and decrease the current rising time of P 0 . It should be noted that Vgp 2  must meet the requirement of
 
 Vgp 2− Vthp &lt;( Vcc−I 0 *Z 0)/2 so that  P 0 is at saturation region.
 
   While several embodiments and variations of the present invention for a low reflection driver for a high speed simultaneous bi-directional data bus simultaneous bi-directional data bus are described in detail herein, it should be apparent that the disclosure and teachings of the present invention will suggest many alternative designs to those skilled in the art.