Abstract:
An ESD protection structure has: a first P-type semiconductor region connected to a pad; a first N-type semiconductor region coupled with the first P-type semiconductor region; a second P-type semiconductor region coupled with the first N-type semiconductor region and connected to a ground terminal; a second N-type semiconductor region coupled with the second P-type semiconductor region and connected to a ground terminal; and a trigger circuit configured to draw a trigger current from the first N-type semiconductor region when a surge is applied to the pad. The trigger circuit is connected to the first N-type semiconductor region through a resistive element.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device provided with an electrostatic discharge (ESD) protection circuit that protects destruction of an internal circuit due to an ESD stress or an application of a surge.  
         [0003]     2. Description of the Related Art  
         [0004]     An ESD protection circuit is incorporated in a semiconductor integrated circuit so as to protect an internal circuit against a surge applied to an input and output pad. One of well-known topologies of the ESD protection circuit is a circuit topology using a silicon controlled rectifier (SCR). Japanese Laid Open Patent Application (JP-P2003-203985A) discloses an ESD protection circuit using an SCR.  FIG. 1  is a cross-sectional view showing a structure of the ESD protection circuit disclosed in the patent document.  
         [0005]     As shown in  FIG. 1 , the ESD protection circuit within the public domain has an SCR region  2  and a trigger circuit region  3  which are integrated on a P-type semiconductor substrate  1 . The trigger circuit region  3  is isolated from the SCR region  2  by an STI (shallow trench isolation) layer  4  as an insulator.  
         [0006]     An N-well  5  is formed in the SCR region  2 , and an N +  diffusion layer  6  and a P 4  diffusion layer  7  are formed in a surface portion of the N-well  5 . Further, an N +  diffusion layer  8  and a P +  diffusion layer  9  are formed in a portion of the SCR region  2  outside of the N-well  5 . The N +  diffusion layer  6 , the P +  diffusion layer  7 , the N +  diffusion layer  8  and the P +  diffusion layer  9  are isolated from one another by STI layers  10  as insulators. The P +  diffusion layer  7 , the N-well  5 , a portion near a surface of the P-type semiconductor substrate  1 , and the N +  diffusion layer  8  function as an SCR having a pnpn structure. More specifically, the P +  diffusion layer  7  functions as an anode of the SCR, the N-well  5  functions as a base thereof, and the N +  diffusion layer  8  functions as a cathode thereof. On the other hand, the N +  diffusion layer  6  and the P +  diffusion layer  9  function as contact layers for realizing electrical connections to the N-well  5  and the P-type semiconductor substrate  1 , respectively. The p +  diffusion layer  7  is connected to an input and output (I/O) pad  11  used for inputting and outputting a signal to and from an internal circuit (not shown). The N +  diffusion layer  8  and the P +  diffusion layer  9  are connected in common to a grounding terminal  12 .  
         [0007]     The trigger circuit region  3  is a region in which a trigger circuit that turns on the above-mentioned SCR when a surge is applied to the I/O pad  11  is formed. In the ESD protection circuit shown in  FIG. 1 , an NMOS transistor  13  having a source and a gate connected in common to the grounding terminal  12  is used as the trigger circuit. More specifically, a source region  14  and a drain region  15  of N +  conductive type are formed in a surface portion of the P-type semiconductor substrate  1 . Further, a gate insulating layer  16  is formed on the surface of the P-type semiconductor substrate  1 , and a gate electrode  17  is formed on the gate insulating layer  16 . The gate electrode  17  typically includes a polysilicon layer  17   a  and a silicide layer  17   b  formed on the polysilicon layer  17   a . Examples of the silicide layer  17   b  include a titanium silicide layer, a cobalt silicide layer, and a tungsten silicide layer. The drain region  15  is electrically connected to the N +  diffusion layer  6  in the SCR region  2  through a metal wiring  18 . The source region  14  and the gate electrode  17  are connected to the grounding terminal  12 .  
         [0008]      FIG. 2  shows an equivalent circuit of the ESD protection circuit shown in  FIG. 1 . The ESD protection circuit shown in  FIG. 1  equivalently functions as a circuit that includes a PNP transistor  21 , an NPN transistor  22 , a substrate resistance R SUB , an N-well resistance R NW  and the NMOS transistor  13 . An emitter of the PNP transistor  21  is connected to the I/O pad  11 , a collector thereof is connected to the grounding terminal  12  through the substrate resistance R SUB , and a base thereof is connected to a collector of the NPN transistor  22 . A base of the NPN transistor  22  is connected to the collector of the PNP transistor  21 , and an emitter thereof is connected to the grounding terminal  12 . With regard to the NMOS transistor  13  that functions as the trigger circuit, a drain thereof is connected to the base of the PNP transistor  21  through the N-well resistance R NW  and the metal wiring  18 , and a source and a gate thereof are connected to the grounding terminal  12 .  
         [0009]     When a surge voltage is applied to the I/O pad  11 , the ESD protection circuit shown in  FIG. 1  operates as follows to protect the internal circuit. When the surge voltage is applied to the I/O pad  11 , the surge voltage is applied to the drain of the NMOS transistor  13  through the emitter and base of the PNP transistor  21 . If the surge voltage causes breakdown of the NMOS transistor  13 , then a trigger current flows from the base of the PNP transistor  21  toward the grounding terminal  12 , and the PNP transistor  21  is thereby turned on. When the PNP transistor  21  is turned on, an emitter-collector current flows from the emitter to the collector of the PNP transistor  21 . The emitter-collector current flows into the grounding terminal  12  through the substrate resistance R SUB . When the emitter-collector current flows through the substrate resistance R SUB , a base potential of the NPN transistor  22  is increased due to a voltage drop at the substrate resistance R SUB . When the base potential of the NPN transistor  22  is increased, a base current flows in the NPN transistor  22 , and the NPN transistor  22  is thereby turned on. When the NPN transistor  22  is turned on, the surge voltage applied to the I/O pad  11  is discharged through the NPN transistor  22 , and thus the internal circuit is protected.  
         [0010]     The ESD protection circuit shown in  FIG. 1  is advantageous in that a high discharge capability and a low trigger voltage can be simultaneously ensured because the SCR and the trigger circuit are isolated from each other. Specifically, the ESD protection circuit shown in  FIG. 1  has the following advantages. First, since the SCR is isolated from the trigger circuit, a length of the base of the SCR can be designed to be small. This can enhance the discharge capability of the ESD protection circuit. Secondly, since the trigger circuit can be designed irrespective of the SCR, the trigger voltage can be arbitrarily designed in the ESD protection circuit shown in  FIG. 1 . This means that the ESD protection circuit shown in  FIG. 1  satisfies both the high discharge capability and the low trigger voltage.  
       SUMMARY OF THE INVENTION  
       [0011]     However, the ESD protection circuit shown in  FIG. 1  has the following disadvantages. The ESD protection circuit may possibly operate at unnecessary time because of an inevitable increase in a parasitic capacity of a path through which the trigger current is carried. The parasitic capacity of the path through which the trigger current is carried is mainly derived from a drain capacity of the NMOS transistor  13 . The NMOS transistor  13  needs to be large in size since the NMOS transistor itself should not be destructed by the surge voltage. Accordingly, the drain capacity of the NMOS transistor  13 , that is, the parasitic capacity of the path through which the trigger current flows is inevitably made large. However, if the parasitic capacity of the path through which the trigger current flows is large, the ESD protection circuit may unnecessarily operate when an abruptly rising voltage pulse is applied to the I/O pad  11 , because the trigger current I flowing in the base of the PNP transistor  21  is represented by the following equation: 
 
 I=C  (dV/dt), 
 
         [0012]     wherein the trigger current I is increased in proportion to a time variation dV/dt of the voltage applied to the I/O pad  11  and the parasitic capacity C. If the time variation dV/dt of the voltage applied to the I/O pad  11  is large, a large trigger current is carried even when a voltage level of the voltage pulse applied to the I/O pad  11  is within a normal range. Such a large trigger current causes the ESD protection circuit to operate. It is desirable to prevent such a malfunction of the ESD protection circuit.  
         [0013]     A semiconductor device according to the present invention has: a first P-type semiconductor region connected to a pad; a first N-type semiconductor region connected with the first P-type semiconductor region; a second P-type semiconductor region connected with the first N-type semiconductor region and connected to a ground terminal; a second N-type semiconductor region connected with the second P-type semiconductor region and connected to a ground terminal; and a trigger circuit configured to draw a trigger current from the first N-type semiconductor region when a surge is applied to the pad. The trigger circuit is connected to the first N-type semiconductor region through a resistive element.  
         [0014]     In the semiconductor device thus constructed, an electrostatic destruction of the trigger circuit itself hardly occurs, because the resistive element is used for the electrical connection between the first N-type semiconductor region and the trigger circuit. Thus, the trigger circuit is allowed to be small in its size, namely, a parasitic capacity of the trigger circuit can be small. Therefore, the semiconductor device according to the present invention is capable of suppressing a malfunction of the ESD protection circuit caused by the large parasitic capacity of the path through which the trigger current flows.  
         [0015]     According to the present invention, the parasitic capacity of the path through which the trigger current is carried can be reduced, and thereby the malfunction of the ESD protection circuit can be prevented. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0017]      FIG. 1  is a cross-sectional view showing a structure of a conventional ESD protection circuit;  
         [0018]      FIG. 2  is a circuit diagram showing an equivalent circuit of the conventional ESD protection circuit shown in  FIG. 1 ;  
         [0019]      FIG. 3  is a cross-sectional view showing a structure of an ESD protection circuit incorporated in a semiconductor device according to an embodiment of the present invention;  
         [0020]      FIG. 4  is a circuit diagram showing an equivalent circuit of the ESD protection circuit according to the present embodiment;  
         [0021]      FIG. 5A  is a circuit diagram showing another configuration of a trigger circuit;  
         [0022]      FIG. 5B  is a circuit diagram showing still another configuration of the trigger circuit;  
         [0023]      FIG. 5C  is a circuit diagram showing still another configuration of the trigger circuit;  
         [0024]      FIG. 5D  is a circuit diagram showing still another configuration of the trigger circuit;  
         [0025]      FIG. 5E  is a circuit diagram showing still another configuration of the trigger circuit;  
         [0026]      FIG. 5F  is a circuit diagram showing still another configuration of the trigger circuit; and  
         [0027]      FIG. 5G  is a circuit diagram showing still another configuration of the trigger circuit.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed. It should be noted that the same or similar constituent elements are denoted by the same or corresponding reference numerals in the drawings.  
         [0029]      FIG. 3  is a cross-sectional view showing a structure of an ESD protection circuit incorporated in a semiconductor device according to an embodiment of the present invention. The ESD protection circuit according to the present embodiment differs from the conventional ESD protection circuit shown in  FIG. 1  in the following respect. The N +  diffusion layer  6  in the SCR region  2  and the drain region  15  of the NMOS transistor  13  are connected through a resistive element  31 . The remaining constituent elements of the ESD protection circuit according to the present embodiment are equal to those of the ESD protection circuit shown in  FIG. 1 . In the present embodiment, a multilayer structure that includes a polysilicon layer  31   a  formed on the STI layer  4  and a silicide layer  31   b  formed on the polysilicon layer  31   a  is used as the resistive element  31 . Examples of the silicide layer  31   b  include a titanium silicide layer, a cobalt silicide layer, and a tungsten silicide layer.  
         [0030]      FIG. 4  is a circuit diagram showing an equivalent circuit of the ESD protection circuit according to the present embodiment. The equivalent circuit of the ESD protection circuit according to the present embodiment is equal to the equivalent circuit of the ESD protection circuit shown in  FIG. 2  except that the drain region  15  of the MOS transistor  13  is connected to the N-well resistance R NW  through the resistive element  31 . Accordingly, the ESD protection circuit according to the present embodiment operates similarly to the ESD protection circuit shown in  FIG. 2 . If a surge voltage is applied to the I/O pad  11 , the surge voltage is applied to the drain of the NMOS transistor  13  through the emitter and base of the PNP transistor  21  and the resistive element  31 . If the surge voltage causes a breakdown of the NMOS transistor  13 , then a trigger current flows from the base of the PNP transistor  21  toward the grounding terminal  12 , and the PNP transistor  21  is thereby turned on. When the PNP transistor  21  is turned on, an emitter-collector current flows from the emitter to the collector of the PNP transistor  21 . The emitter-collector current flows into the grounding terminal  12  through the substrate resistance R SUB . When the emitter-collector current flows through the substrate resistance R SUB , a base potential of the NPN transistor  22  is increased due to a voltage drop at the substrate resistance R SUB . When the base potential of the NPN transistor  22  is increased, a base current flows in the NPN transistor  22 , and the NPN transistor  22  is thereby turned on. When the NPN transistor  22  is turned on, the surge voltage applied to the I/O pad  11  is discharged through the NPN transistor  22 , and thus the internal circuit is protected.  
         [0031]     The most important feature of the ESD protection circuit according to the present embodiment is as follows. Since the N +  diffusion layer  6  is connected to the drain region  15  of the NMOS transistor  13  through the resistive element  31 , an electrostatic destruction of the NMOS transistor  13  itself hardly occurs. Since the electrostatic destruction hardly occurs, it is possible to reduce a size of the NMOS transistor  13 , i.e., to reduce a drain capacity of the NMOS transistor  13  in the ESD protection circuit according to the present embodiment. Therefore, the ESD protection circuit according to the present embodiment can reduce the parasitic capacity of the path through which the trigger current is carried. This is effective to suppress the malfunction of the ESD protection circuit.  
         [0032]     Alternatively, a resistive element having a structure other than the multilayer structure that includes the polysilicon layer  31   a  and the silicide layer  31   b  can be used as the resistive element  31 . For example, the resistive element  31  can be formed of a single polysilicon layer. Also, the resistive element  31  can be formed of a single tungsten silicide layer. Moreover, the resistive element  31  can have a multilayer structure that includes a tungsten silicide layer and a titanium nitride layer.  
         [0033]     It should be noted, however, that it is preferable to use the single polysilicon layer or the multilayer of the polysilicon layer and the silicide layer as the resistive element  31  from the aspect of simplifying the manufacturing processes. When the single polysilicon layer or the multilayer that includes the polysilicon layer and the silicide layer is used as the resistive element  31 , the resistive element  31  can be formed simultaneously with a gate of a MOS transistor. As a result, a specific process for forming the resistive element  31  becomes unnecessary, which simplifies the manufacturing processes.  
         [0034]     As mentioned above, the resistive element  31  is allowed to have various structures. Nevertheless, it is unfavorable to use a diffusion resistance formed in the P-type semiconductor substrate  1  as the resistive element  31 . In other words, it is preferable that the resistive element  31  is formed outside of the P-type semiconductor substrate  1 . If the diffusion resistance is used as the resistive element  31 , then a pn junction is formed in the P-type semiconductor substrate  1 , and hence the parasitic capacity of the path through which the trigger current flows is increased. This reduces the above-mentioned advantage of suppressing the malfunction of the ESD protection circuit.  
         [0035]     The resistive element  31  is preferably formed of a layer or a multilayer whose sheet resistance is equal to or higher than 1.0 Ω/sq. More preferably, its sheet resistance is equal to or higher than 5.0 Ω/sq. If the sheet resistance is excessively low, the NMOS transistor  13  cannot be sufficiently protected against the surge voltage. Therefore, the sheet resistance of the layer or the multilayer that constitutes the resistive element  31  is preferably equal to or lower than 1.0 kΩ/sq. Conversely, if the sheet resistance is excessively high, it becomes difficult to turn on the NMOS transistor  13  when the surge voltage is applied. As a result, the internal circuit cannot be sufficiently protected.  
         [0036]     A configuration of the trigger circuit for turning on the SCR can be variously changed.  FIGS. 5A  to  5 G are circuit diagrams showing examples of a configuration of a circuit that can be used as the trigger circuit. It should be noted in  FIGS. 5A  to  5 G that a reference numeral  31   c  denotes a resistive element connection node connected to the resistive element  31 .  
         [0037]     As shown in  FIG. 5A , a PMOS transistor  32  having a source and a gate connected to the resistive element  31  and having a drain connected to the grounding terminal  12  can be used as the trigger circuit.  
         [0038]     As shown in  FIG. 5B , a trigger circuit constituted by an NMOS transistor  33  and an inverter  34  can be used as the trigger circuit. The NMOS transistor  33  has a drain connected to the resistive element  31  and a source connected to the grounding terminal  12 . The inverter  34  is constituted by a PMOS transistor  34   a  connected in series between a power supply terminal  35  and the grounding terminal  12 , and an NMOS transistor  34   b . An output of the inverter  34  (i.e., drains of the PMOS transistor  34   a  and the NMOS transistor  34   b ) is connected to a gate of the NMOS transistor  33 . An input of the inverter  34  (i.e., gates of the PMOS transistor  34   a  and the NMOS transistor  34   b ) is connected to the power supply terminal  35 .  
         [0039]     One feature of the trigger circuit shown in  FIG. 5B  is that the surge voltage causing the ESD protection circuit to operate can be set low since the NMOS transistor  33  is not completely turned off. When the semiconductor device provided with the ESD protection circuit is not powered on, the power supply terminal  35  is in a floating state, and both the PMOS transistor  34   a  and the NMOS transistor  34   b  of the inverter  34  are not completely turned on. Accordingly, the gate of the NMOS transistor  33  connected to the output of the inverter  34  is in a floating state, and the NMOS transistor  33  is not completely turned off. This makes it easier to cause the ESD protection circuit to operate when a surge voltage having a positive polarity relative to the grounding terminal  12  is applied to the I/O pad  11 .  
         [0040]     As shown in  FIG. 5C , an NMOS transistor  36  having a drain and a gate connected to the resistive element  31  and a source connected to the grounding terminal  12  can be used as the trigger circuit. One feature of the trigger circuit shown in  FIG. 5C  is that the surge voltage causing the ESD protection circuit to operate can be set low. According to the trigger circuit shown in  FIG. 5C , a surge voltage is applied to the gate of the NMOS transistor  36  when the surge voltage is applied to the I/O pad  11 . This makes it easier to turn on the NMOS transistor  36 .  
         [0041]     The trigger circuit shown in  FIG. 5C  may possibly be confronted with a problem that a high leakage current flows through the NMOS transistor  36 . In order to avoid the leakage current problem, it is preferable that a gate length of the NMOS transistor  36  is sufficiently increased. As another approach, a plurality of NMOS transistors connected in series can be used as the trigger circuit, which is shown in  FIG. 5D .  FIG. 5D  shows a trigger circuit configured such that two NMOS transistors  36   a  and  36   b  are connected in series. A drain and a gate of each of the NMOS transistors are connected to the resistive element  31  either directly or through another NMOS transistor. A source of each of the NMOS transistors is connected to the grounding terminal  12  either directly or through another NMOS transistor. In the example shown in  FIG. 5D , the drain and the gate of the NMOS transistor  36   a  are directly connected to the resistive element  31 , and the drain and the gate of the NMOS transistor  36   b  are connected to the resistive element  31  through the NMOS transistor  36   a . Further, the source of the NMOS transistor  36   a  is connected to the grounding terminal  12  through the NMOS transistor  36   b , and the source of the NMOS transistor  36   b  is directly connected to the grounding terminal  12 .  
         [0042]     Furthermore, as shown in  FIG. 5E , a PMOS transistor  37  having a source connected to the resistive element  31  and a drain and a gate connected to the grounding terminal  12  can be used as the trigger circuit. One feature of the trigger circuit shown in  FIG. 5E  is that the surge voltage causing the ESD protection circuit to operate can be set low. According to the trigger circuit shown in  FIG. 5E , a gate of the PMOS transistor  37  is connected to the grounding terminal  12 , which makes it easier to turn on the PMOS transistor  37 .  
         [0043]     Similarly to the trigger circuit shown in  FIG. 5C , the trigger circuit shown in  FIG. 5E  may possibly be confronted with a problem that a high leakage current flows through the PMOS transistor  37 . In order to avoid the leakage current problem, it is preferable that a gate length of the PMOS transistor  37  is sufficiently increased. As another approach, a plurality of PMOS transistors connected in series can be used as the trigger circuit, which is shown in  FIG. 5F .  FIG. 5F  shows a trigger circuit configured such that two PMOS transistors  37   a  and  37   b  are connected in series. A source of each of the PMOS transistors is connected to the resistive element  31  either directly or through another PMOS transistor. A drain and a gate of each of the PMOS transistors are connected to the grounding terminal  12  either directly or through another PMOS transistor. In the example shown in  FIG. 5F , the source of the PMOS transistor  37   a  is directly connected to the resistive element  31 , and the source of the PMOS transistor  37   b  is connected to the resistive element  31  through the PMOS transistor  37   a . Further, the drain and the gate of the PMOS transistor  37   a  are connected to the grounding terminal  12  through the PMOS transistor  37   b , and the drain and the gate of the PMOS transistor  37   b  are directly connected to the grounding terminal  12 .  
         [0044]     Moreover, as shown in  FIG. 5G , a plurality of diodes connected in series in a forward direction from the resistive element  31  to the grounding terminal  12  can be used as the trigger circuit.  FIG. 5G  shows a trigger circuit constituted by three diodes  38   a  to  38   c  connected in series. According to the trigger circuit shown in  FIG. 5G , it is possible to adjust the surge voltage causing the ESD protection circuit to operate and a leakage current flowing through the trigger circuit by changing the number of the plurality of diodes.  
         [0045]     It is apparent that the present invention is not limited to the above embodiment, and that may be modified and changed without departing from the scope and spirit of the invention.