Abstract:
A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to switched-capacitor circuits and more specifically to switched-capacitor circuits of very high resolution. 
     2. Discussion of the Related Art 
     A switched-capacitor circuit comprises at least one capacitor having at least one armature alternately connected, at a switching frequency, to one or the other of two terminals by switches. In operation, the assembly formed by the capacitor and the associated switches has an equivalent resistance equal to the ratio of the switching period to the capacitance of the capacitor. Switched-capacitor circuits have many advantages. They enable to simulate a variable resistance which depends on the switching frequency. This is the reason why switched-capacitor circuits are especially used for the forming of filters having a cut-off frequency depending on the switching frequency. Further, for equivalent manufacturing technologies, a switched-capacitor circuit takes up a smaller surface area when integrated than that which would be taken up by an equivalent circuit formed with real resistors. Further, for equivalent manufacturing technologies, the capacitance of an integrated capacitor may be obtained with an accuracy greater than that of a resistor. 
     The current tendency is to form switched-capacitor circuits of very high resolution, that is, for which the signal-to-noise ratio or SNR is greater than some hundred decibels. For a conventional switched-capacitor circuit, this requires increasing the capacitances of the circuit capacitors up to values that can exceed several hundreds of picofarads. The capacitance increase of the capacitors translates as an unwanted increase of the total consumption of the switched-capacitor circuit. It is further generally difficult to integrate capacitors with high capacitances. 
     SUMMARY OF THE INVENTION 
     The present invention aims at a switched-capacitor circuit enabling to obtain a high SNR while maintaining a low consumption. 
     Another object of the present invention is the forming of a switched-capacitor circuit taking up a decreased surface area when it is made in integrated form. 
     For this purpose, the present invention provides a switched-capacitor circuit comprising at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one or the other of two terminals at a switching frequency. The circuit further comprises a second capacitor connected to the first capacitor at a node and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range. 
     According to an embodiment, the filtering circuit is capable of connecting the node to the virtual ground only for frequencies smaller than a threshold frequency greater than half the switching frequency. 
     According to an embodiment, the filtering circuit comprises an amplifier with differential inputs having an input connected to the node and having a main cut-off frequency, the threshold frequency of the filtering circuit corresponding to the main cut-off frequency. 
     According to an embodiment, the filtering circuit comprises at least one active filter comprising at least one active electronic component and at least one passive filter comprising at least one passive electronic component. 
     According to an embodiment, the capacitance of the second capacitor is smaller than the capacitance of the first capacitor. 
     According to an embodiment, the first capacitor comprises first and second armatures, the circuit comprising first, second, and third terminals; a first switch connecting the first terminal to the first armature of the first capacitor; a second switch connecting the second terminal to the first armature of the first capacitor; a third switch connecting the third terminal to the second armature of the first capacitor; and a fourth switch connecting the node to the second armature of the first capacitor, the first and fourth switches being controlled by a first binary signal and the second and third switches being controlled by a second binary signal, the first and second binary signals being non-overlapping. 
     According to an embodiment, the filtering circuit comprises an operational amplifier comprising an input connected to said node and an output connected to said input via the second capacitor, the threshold frequency of the filtering circuit corresponding to the cut-off frequency of the operational amplifier. 
     According to an embodiment, the second terminal is connected to a source of the reference voltage and the operational amplifier comprises an additional input connected to said source of the reference voltage. 
     According to an embodiment, the circuit further comprises a fifth switch across the second capacitor, the fifth switch being on, when the first and fourth switches are on, for a first time period and off for a second time period. 
     According to an embodiment, the circuit further comprises a third capacitor comprising third and fourth armatures, the operational amplifier comprising an additional input connected to an additional node and an additional output connected to the additional input via a fourth capacitor; fourth and fifth terminals; a sixth switch controlled by the first signal connecting the fourth terminal to the third armature of the third capacitor; a seventh switch controlled by the second signal connecting the fifth terminal to the fourth armature of the third capacitor; and an eighth switch controlled by the first signal connecting the additional node to the fourth armature of the third capacitor, the second terminal being located between the third armature of the third capacitor and the fifth switch. 
     The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically shows a conventional embodiment of a switched-capacitor circuit; 
         FIG. 2  shows an electric circuit used to model the noise transfer function of the circuit of  FIG. 1 ; 
         FIG. 3  schematically shows the variation of the noise power spectral density at the output of the circuit of  FIG. 2 ; 
         FIGS. 4 and 5  are drawings respectively similar to  FIGS. 1 and 2  of a variation of the circuit of  FIG. 1 ; 
         FIG. 6  shows an electric circuit illustrating the operating principle of a switched-capacitor circuit according to the present invention; 
         FIG. 7  shows an embodiment of a switched-capacitor circuit according to the present invention; 
         FIG. 8  schematically shows the variation of the noise power spectral density at the output of the circuit of  FIG. 7 ; 
         FIG. 9  shows an alternative embodiment of the circuit of  FIG. 7 ; 
         FIGS. 10 and 12  show two conventional embodiments of an integrator with switched capacitors; and 
         FIGS. 11 and 13  show two embodiments of an integrator with switched capacitors according to the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     For clarity, the same elements have been designated with the same reference numerals in the different drawings. Further, in the following description, the same reference is used to designate a capacitive element, or capacitor, and its capacitance, and the same reference is used to designate a resistive element, or resistor, and the value of its resistance. Further, “switched-capacitor circuit” is used in a general sense and may designate a circuit comprising a single capacitor having at least one of its armatures switched between two terminals. 
       FIG. 1  shows a conventional example of a switched-capacitor circuit  10  comprising an input terminal IN and an output terminal OUT. Call V IN  the voltage between terminal IN and a source of a reference voltage, for example, ground GND, and V OUT  the voltage between terminal OUT and ground GND. Circuit  10  comprises a capacitor C 0  having an armature connected to a node A and its other armature connected to a node B. Node A is connected to terminal IN via a switch SW 1  controlled by a control signal P 1 . Node A is further connected to ground GND via a switch SW 2  controlled by a control signal P 2 . Node B is connected to terminal OUT via a switch SW 3  controlled by signal P 2 . Node B is further connected to ground GND via a switch SW 4  controlled by signal P 1 . As an example, control signals P 1  and P 2  are binary signals alternating between a high state, noted “1”, and a low state, noted “0”. As an example, when signal P 1  is at “1” (signal P 2  at “0”), switches SW 1  and SW 4  are on and switches SW 2  and SW 3  are off. When signal P 1  is at “0” (signal P 2  at “1”), switches SW 1  and SW 4  are off and switches SW 2  and SW 3  are on. Signals P 1  and P 2  are non-overlapping, that is, they are not simultaneously in the state for which they control the turning-on of the associated switch (the high state in the present example). However, signals P 1  and P 2  may be simultaneously in the state for which they control the turning-off of the associated switches (the low state in the present example). As an example, signals P 1  and P 2  are complementary, that is, signal P 1  is in the low state when signal P 2  is in the high state and conversely. As an example, signals P 1  and P 2  are periodic with a frequency f S  (called switching frequency or sampling frequency hereafter) and a period T S . Call α the duty cycle of signal P 1 . This means that over a time period T S , signal P 1  is in the high state for duration αT S  and in the low state for duration (α−1)T S , α being strictly smaller than 1. As an example, α is equal to ½. 
     Conventionally, circuit  10  is equivalent to a resistor R placed between terminals IN and OUT and having a resistance equal to:
 
 R=T   S   /C   0 =1/( C   0   f   S )  (1)
 
       FIG. 2  shows a circuit  12  equivalent to the circuit  10  used to estimate the noise power spectral density at the output of circuit  10 . In the case where switches SW 1  and SW 4  are formed of MOS transistors, it can be considered that, when switches SW 1  and SW 4  are on, circuit  10  is equivalent to a source S b  of a thermal noise in series with a resistor R ON  which corresponds to the internal resistance of MOS transistors in the on state. Voltage V IN  provided by noise source S b  is filtered by a low-pass filter formed by resistor R ON  and capacitor C 0  and having the following transfer function H: 
                   H   =     1     1   +     j   ⁢     f     f   C                     (   2   )               
where f C  is the cut-off frequency of the low-pass filter and is equal to:
 
 f   C =1/2π R   ON   C   0   (3)
 
     It is considered that cut-off frequency f C  is much higher than sampling frequency f S , to obtain a proper charge of capacitor C 0 . 
     The spectral power density S 0  of the noise provided by source S b  is equal to:
 
 S   0 =4 kTR   ON   (4)
 
where k is Boltzmann&#39;s constant and T is temperature.
 
     The noise power spectral density S 1  at the output of circuit  12  is equal to: 
     
       
         
           
             
               
                 
                   
                     S 
                     1 
                   
                   = 
                   
                     
                       S 
                       0 
                     
                     
                       1 
                       + 
                       
                         
                           ( 
                           
                             f 
                             
                               f 
                               C 
                             
                           
                           ) 
                         
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
       FIG. 3  schematically shows the variation of noise spectral density S 1 . After sampling at frequency f S , noise power spectral density S 2  at the output of circuit  10  is provided by the following relation: 
     
       
         
           
             
               
                 
                   
                     
                       S 
                       2 
                     
                     ⁡ 
                     
                       ( 
                       f 
                       ) 
                     
                   
                   = 
                   
                     
                       S 
                       0 
                     
                     ⁢ 
                     
                       
                         ∑ 
                         
                           n 
                           = 
                           
                             - 
                             ∞ 
                           
                         
                         
                           n 
                           = 
                           
                             + 
                             ∞ 
                           
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         1 
                         
                           1 
                           + 
                           
                             
                               ( 
                               
                                 
                                   f 
                                   - 
                                   
                                     nf 
                                     S 
                                   
                                 
                                 
                                   f 
                                   C 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Call f N /2 the maximum frequency of the useful signal to be transmitted. To respect Shannon&#39;s sampling criterion, frequency f N /2 must be smaller than half sampling frequency f S . Relation (6) shows an aliasing in the useful band of the thermal noise due to the sub-sampling of the wide-band noise. 
     In practice, frequency f N  is much smaller than sampling frequency f S . As an example, frequency f S  is on the order of 1 MHz and frequency f N  is on the order of 1 kHz. An approached value of the RMS value of the noise voltage at the output of circuit V b  can be determined in a simple way. First, the sampling is not taken into account. The RMS value of noise voltage V b  at the output of circuit  12  is provided by the following relation: 
     
       
         
           
             
               
                 
                   
                     V 
                     b 
                   
                   = 
                   
                     
                       
                         
                           ∫ 
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                             + 
                             ∞ 
                           
                         
                         ⁢ 
                         
                           
                             
                               S 
                               1 
                             
                             ⁡ 
                             
                               ( 
                               f 
                               ) 
                             
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             ⅆ 
                             f 
                           
                         
                       
                     
                     = 
                     
                       
                         
                           
                             S 
                             0 
                           
                           ⁢ 
                           
                             
                               ∫ 
                               0 
                               
                                 + 
                                 ∞ 
                               
                             
                             ⁢ 
                             
                               
                                 1 
                                 
                                   1 
                                   + 
                                   
                                     
                                       ( 
                                       
                                         f 
                                         
                                           f 
                                           C 
                                         
                                       
                                       ) 
                                     
                                     2 
                                   
                                 
                               
                               ⁢ 
                               
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                                 f 
                               
                             
                           
                         
                       
                       ⁢ 
                       
                         
 
                       
                       ⁢ 
                       
                           
                       
                       = 
                       
                         
                           
                             
                               S 
                               0 
                             
                             ⁢ 
                             
                               f 
                               C 
                             
                             ⁢ 
                             
                               π 
                               2 
                             
                           
                         
                         ⁢ 
                         
                           
 
                         
                         ⁢ 
                         
                             
                         
                         = 
                         
                           
                             kT 
                             
                               C 
                               0 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     The noise being sampled at frequency f S , the noise is taken back into frequency band [0,f S /2]. Further, the useful signal being in frequency band [0,f N /2], only part of the noise is kept. The RMS value of the aliased noise voltage corresponds to: 
     
       
         
           
             
               
                 
                   
                     V 
                     b 
                   
                   = 
                   
                     
                       kT 
                       
                         
                           C 
                           0 
                         
                         ⁢ 
                         
                           
                             f 
                             S 
                           
                           
                             f 
                             C 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     A possibility to decrease the RMS value of noise voltage V b  is to increase capacitance C 0 . Typically, to obtain an SNR greater than some hundred decibels, capacitance C 0  must be greater than some hundred picofarads. A disadvantage is that circuit  10  generally belongs to a circuit comprising other capacitors having values depending on C 0 . For example, circuit  10  may belong to an integrator, possibly comprising another capacitor, called integration capacitor, having a capacitance that can be equal to approximately 10 times C 0 . The integrated forming of capacitors having high capacitances, for example, greater than several hundreds of picofards, is difficult. Further, the increase in the capacitances of the capacitors of switched-capacitor circuits results in an increase in the total circuit consumption. This may be incompatible with applications for which the total circuit consumption is critical. 
     To increase the SNR of a switched-capacitor circuit without increasing the capacitance of the circuit capacitor, the applicant has first attempted to replace capacitor C 0  with two series-assembled capacitors to form a capacitive bridge. 
       FIG. 4  shows a switched-capacitor circuit  14  having a structure similar to that of circuit  10  of  FIG. 1 , with the difference that capacitor C 0  has been replaced with a capacitor C 1  and that a capacitor C 2  has been added between switch SW 4  and ground GND. Capacitance C 1  is greater than capacitance C 2 . As an example, capacitance C 1  may be equal to ten times capacitance C 2 . A node located between switch SW 4  and capacitor C 2  is designated as N. 
       FIG. 5  is an electric diagram  16  equivalent to circuit  14  when switches SW 1  and SW 4  are on and which illustrates the operation thereof. Voltage V OUT  corresponds to the voltage across capacitor C 1 . Call V′ OUT  the voltage between node A and ground GND. 
     Transfer function H′ of circuit  16  is: 
                       H   ′     ⁡     (   f   )       =         V   OUT       V   IN       =           V   OUT       V   OUT   ′       ⁢       V   OUT   ′       V   IN         =         C   2         C   2     +     C   1         ⁢     1     1   +     j   ⁢     f     f   C   ′                           (   9   )               
where f′ C  is the cut-off frequency of the low-pass filter formed by resistor R ON  and capacitors C 1  and C 2 . At low frequencies, transfer function H′ of circuit  16  is substantially equal to transfer function H of circuit  12  multiplied by attenuation factor C 2 /(C 1 +C 2 ). When capacitance C 1  is equal to 10 times capacitance C 2 , the attenuation factor is 1/11. The capacitive bridge formed by capacitors C 1  and C 2  thus enables to decrease the contribution of noise across capacitor C 1 . A 21-dB gain on the noise is thus obtained. However, the amplitude of the useful signal at low frequencies is also decreased by 21 decibels. The SNR of circuit  16  is thus not improved with respect to that of circuit  12 .
 
     The applicant has demonstrated that all of the useful low-frequency signal and only part of the high-frequency noise across capacitor C 1  could be obtained by connecting node N between capacitors C 1  and C 2  to a “virtual low-frequency ground”. 
       FIG. 6  shows a circuit  20  illustrating the principle of a virtual low-frequency ground. Node N is connected to a virtual low-frequency ground GND′ by a line  22  shown in dotted lines. Capacitor C 2 , on the side opposite to node N, is connected to a circuit S C . For low frequencies, virtual ground GND′ is equivalent to ground GND. Everything happens as if node N was then directly connected to ground GND, short-circuiting capacitor C 2 . For high frequencies, everything happens as if ground GND′ was not present and as if node B was normally connected to capacitor C 2 . At high frequencies, circuit S C  maintains the armature of capacitor C 2  at a fixed voltage. The low-frequency components and especially the useful signal are thus only seen by capacitor C 1  while the high-frequency components (and, in particular, the high-frequency components of the wide-band thermal noise) are shared between capacitors C 1  and C 2 . Advantage is thus taken of the attenuation of the high-frequency components of the noise without for the useful signal to be attenuated. Thereby, at the aliasing of the spectrum due to the sampling, the contribution of the high-frequency noise in the useful frequency band is decreased. Thereby, to obtain a given SNR, capacitance C 1  of circuit  20  according to the present invention may be smaller, for example, up to ten times, than capacitance C 0  of conventional circuit  10 . The capacitances of capacitors C 1  and C 2  being low, the integrated manufacturing of circuit  20  is eased and the consumption of circuit  20  is decreased. 
     According to an embodiment the virtual “low frequency” ground is formed by a differential-input amplifier having an input connected to node N and having its other input connected to ground GND. Call main cut-off frequency the lowest frequency for which the amplifier gain falls by 3 dB with respect to the maximum amplifier gain. The amplifier may comprise active components (for example, an operational amplifier) and possibly passive components (resistor, capacitor, etc.). 
       FIG. 7  shows an embodiment of a switched-capacitor circuit  30  with a virtual ground. Circuit  30  comprises all the elements of circuit  14  of  FIG. 4 , but node N is connected to an inverting input I− of an operational amplifier  32 . Non-inverting input I+ of operational amplifier  32  is connected to ground GND. Capacitor C 2  is provided between node N and output O+ of operational amplifier  32 . Conventionally, operational amplifier  32  has a cut-off frequency f′ C  on the order of from 1 to a few Megahertz, for example, 2 MHz, which is smaller than cut-off frequency f C  and is greater than half switching frequency f S  of switches SW 1  to SW 4 . In the following description, frequencies smaller than cut-off frequency f′ C  are called low frequencies and frequencies greater than cut-off frequency f′ C  are called high frequencies 
     The operation of circuit  30  will be described when switches SW 1  and SW 4  are on. For frequencies smaller than cut-off frequency f′ C , operational amplifier  32  operates normally. In particular, the voltages at inverting and non-inverting inputs I− and I+ of operational amplifier  32  are equal. Node N is thus effectively directly connected to ground GND. For frequencies greater than cut-off frequency f′ C , operational amplifier  32  no longer operates properly, and everything happens as if it was not present, with output O+ being at high impedance. The high-frequency components are thus well distributed between capacitors C 1  and C 2 . 
       FIG. 8  schematically shows an example of the variation of the noise power spectral density S 3  at the output of circuit  30  without taking the sampling into account. At low frequencies, the 1/f noise contribution of operational amplifier  32 , also called flicker noise, can be observed. The amplitude of noise power spectral density S 3  at the output of circuit  30  decreases for frequencies greater than f′ C . In the sampling, the high-frequency components of the thermal noise are aliased on interval [0, f S /2]. Due to the fact that these high-frequency components have been attenuated, their contribution in useful band [0, f N /2] is decreased. 
     Capacitance C 2  should advantageously be as low as possible with respect to C 1  to improve the attenuation of the high-frequency components. However, when switches SW 1  and SW 4  are on, voltage V S  at output O+ of the amplifier is equal to: 
                     V   S     =       -       C   1       C   2         ⁢     V   IN               (   10   )               
so that if the ratio of capacitances C 1  and C 2  is too high, operational amplifier  32  risks saturating.
 
       FIG. 9  shows a switched-capacitor circuit  35  corresponding to a variation of circuit  30  of  FIG. 7  in which a switch SW 5  is arranged across capacitor C 2 . Switch SW 5  is controlled by a control signal P 3 . During time αT S  for which signal P 1  is in the high state, signal P 3  is in the low state (switch SW 5  off) for a time period βαT S , β being strictly smaller than 1, and then in the high state (switch SW 5  off) for time period (1−β)αT S . During time period (1−α)T S  for which signal P 1  is in the low state, signal P 3  is in the high state (switch SW 5  off). Value β is selected so that capacitor C 2  does not have time to completely charge during time period βαT S  so that voltage V S  does not reach too high values, likely to cause the saturation of operational amplifier  32 . For a conventional operational amplifier  32 , and for a ratio C 1 /C 2  equal to 10, β may be on the order of 1/2. 
       FIG. 10  shows a conventional example of application of switched-capacitor circuit  10  of  FIG. 1  for the forming of an integrator  40 . Terminal OUT of circuit  10  is connected to inverting input I′− of an operational amplifier  42 . Non-inverting input I′+ of operational amplifier  42  is connected to ground GND. A capacitor C 3  is provided between inverting input I′− and an output terminal OUT′ of integrator  40 . Output O′+ of operational amplifier  42  is connected to terminal OUT′. 
     The operation of integrator  40  will now be schematically described, assuming that voltage V OUT ′ is initially equal to V 0  and considering that signal P 1  is in the low state (signal P 2  in the high state). Switches SW 1  and SW 4  are then off and switches SW 2  and SW 3  are on. The charge stored in the right-hand armature of capacitor C 0  shown to the right of  FIG. 10  is zero and the charge stored in the armature of capacitor C 3  shown to the left of  FIG. 10  is equal to −C 3 V 0 . 
     When signal P 1  switches to the high state (P 2  in the low state), which corresponds to an accumulation phase, switches SW 1  and SW 4  are on and switches SW 2  and SW 3  are off. Capacitors C 0  and C 3  are separate. Charge −C 3 V 0  remains trapped on the left-hand armature of capacitor C 3 . The voltage at terminal OUT′ does not change. Further, capacitor C 0  charges and the right-hand armature of capacitor C 0  receives charge −C 0 V IN . 
     When signal P 1  switches back to the low state (P 2  in the high state), which corresponds to an integration phase, capacitors C 0  and C 3  are connected to each other again. The output voltage of amplifier  42  then switches to V′ OUT . The balance of the charges between capacitors C 0  and C 3  can be written as:
 
0− C   3   V′   OUT   =−C   0   V   IN   −C   3   V   0   (11)
 
that is:
 
 V′   OUT   =V   0 +( C   0   /C   3 ) V   IN   (12)
 
     At each switching cycle of switches SW 1  to SW 4 , voltage V′ OUT  is equal to the sum of the value of the preceding cycle and of a term proportional to V IN . An integrator operation is thus obtained. 
       FIG. 11  shows an embodiment of an integrator  50  of the type shown in  FIG. 10 , implementing circuit  30  shown in  FIG. 9 . For this purpose, output terminal OUT of circuit  30  is connected to inverting input I′− of operational amplifier  42 . 
     The operation of circuit  50  will now be described. When signal P 1  is in the high state during time αT S , that is, during the acquisition phase, switches SW 1  and SW 4  are on and switches SW 2  and SW 3  are off. Circuit  30  is not connected to operational amplifier  42  and operates as described previously. More specifically, switch SW 5  is off during time βαT S  and is on during time (1−β)αT S . 
     When signal P 1  is in the low state for time (1−α)T S , that is, during the integration phase, switches SW 1  and SW 4  are off and switches SW 2 , SW 5 , and SW 3  are on. Node B is no longer connected to node N and capacitor C 1  is connected to operational amplifier  42  identically to what has been previously described for capacitor C 0  of circuit  40 . The high-frequency noise components which might be present during the integration phase are filtered by operational amplifier  42 . 
       FIG. 12  shows a conventional embodiment of an integrator  60  having a differential structure. Integrator  60  comprises the elements of circuit  40  and, further, a capacitor C′ 1  having an armature connected to an input terminal IN′ by a switch SW′ 1  and is connected to switch SW 2 . The other armature of capacitor C′ 1  is connected to non-inverting input I′+ of differential amplifier  32  via a switch SW′ 3  and to switch SW 4 . Switch SW′ 1  is controlled by signal P 1  and switch SW′ 3  is controlled by switch P 2 . Inverting input I′− of operational amplifier  42  is connected to an output terminal OUT″. A capacitor C′ 3  is provided between non-inverting input I′+ and inverting output O′− of operational amplifier  42 . The operation of integrator  60  is identical to that of integrator  40 , the role of ground GND for integrator  40  being played, in this case, by the common-mode voltage of operational amplifier  42 . 
       FIG. 13  shows the use of circuit  30  according to the present invention arranged in differential form for the forming of a positive differential integrator  70 . Integrator  70  comprises the elements of circuit  60  and, further, a switch SW′ 4  connecting capacitor C′ 1  to non-inverting input I+ of operational amplifier  32 . Integrator  70  further comprises a capacitor C′ 2  arranged between non-inverting input I+ and inverting output O− of operational amplifier  32  and a switch SW′ 5  arranged across capacitor C′ 2 . Switch SW′ 5  is controlled by signal P 3 . The operation of integrator  70  is identical to that of integrator  50 , the role of ground GND for integrator  40  being played, in this case, by the common-mode voltage of operational amplifier  42 . 
     The present invention enables to decrease the contribution of the high-frequency noise in the frequency band of the useful signal. Thereby, for a same SNR, it enables to decrease capacitance C 1  of circuit  30 ,  35  with respect to capacitance C 0  of circuit  10 . In the present embodiment, capacitance C 1  may be ten times smaller than capacitance C 0 . Further, when the switched-capacitor circuit is used to form an integrator, integration capacitance C 3  may be advantageously decreased with respect to a conventional circuit, for example, by a factor 10. More generally, the use of the switched-capacitor circuit according to the present invention in an electronic system may enable to decrease the capacitances of other capacitors of the electronic system. The present invention advantageously enables to decrease the surface area necessary to make switched-capacitor circuit  40  in integrated form, the surface area taken up by operational amplifier  32  being substantially equivalent to the surface area taken up by a capacitor having a capacitance of a few picofarads. 
     The present invention further provides a consumption gain on the order of from 7 to 8 with respect to a conventional switched-capacitor circuit. The circuit consumption is not exactly decreased by capacitance ratio C 1 /C 2  since the consumption of operational amplifier  32  must be taken into account. Further, when the switched-capacitor circuit corresponds to a stage of an electronic system comprising several successive stages, the decrease in the input capacitance of the switched-capacitor circuit enables to decrease the constraints on the stage preceding the switched-capacitor circuit, for example, a pre-amplifier. 
     Specific embodiments of the present invention have been described. Different variations and modifications will occur to those skilled in the art. In particular, although an example of a switched-capacitor circuit comprising four switches SW 1  to SW 4  has been described, it should be clear that the present invention can apply to a switched-capacitor circuit in which a same armature of capacitor C 1  is switched between terminals IN and OUT, the other armature of capacitor C 1  being then connected to inverting input I− of operational amplifier  32 . 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.