Abstract:
A transimpedance amplifier, which is useful as an optical fiber preamplifier, is disclosed. The illustrative embodiment exhibits four characteristics. First, it minimizes the equivalent input noise current. Second, it has a wide bandwidth. Third, it has a reasonably large output voltage, and fourth, it is stable over wide temperature and voltage ranges. The illustrative embodiment comprises a transimpedance stage and a gain stage. Both stages employ a pure NMOS design which contributes to the above four advantages. Bandwidth is further increased over the prior art by the use of inductive loads. The inductive loads of the illustrative embodiment are not physical inductors, but transistor-based “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor.

Description:
FIELD OF THE INVENTION 
     The present invention relates to electronics in general, and, more particularly, to a transimpedance amplifier design. 
     BACKGROUND OF THE INVENTION 
     Modern optical telecommunications systems often employ optical fibers for carrying signals. Low-cost, high-performance, highly integrated fiber optic interface circuits are becoming increasingly necessary to meet the demands of high-speed digital data communication. One standard circuit function for fiber optic communication systems is a transimpedance amplifier that is used within an optical receiver. 
       FIG. 1  depicts an architectural diagram of a typical optical receiver. The light from an optical fiber  101  impinges on photodiode detector  102 , producing a current IPD. Transimpedance amplifier  103  converts the very small currents indicative of optical signals applied to photodetector  102  into a large signal voltage, VTIA, which is further amplified by post amplifier  104  to voltage VPA for output to digital circuitry. 
       FIG. 2  depicts a schematic diagram of the transimpedance-input stage of a transimpedance amplifier in the prior art. An input current is injected into node  201 . This current falls across input resistance RS and reverse-biased diode D 1 , both connected to power source V SS . Node  201  is electrically connected to the gate terminal of NMOS transistor MB and the source of NMOS transistor M 1 . The gate terminal of transistor M 1  is electrically connected to the drain terminal of transistor M 2  and one terminal of resistor RB. The output of the circuit is terminal  202 , which is electrically connected to the drain of transistor M 1 , and one terminal of resistor R 1 . The second terminal of resistor R 1  is electrically connected to the second terminal of resistor RB and to power supply V DD . 
     The feedback of the voltage at point  2  between transistor MB and resistor RB to the gate of transistor M 1  serves to keep the biasing of the output voltage at point  3 , V OUT , stable. When the current of M 1  increases, the voltage at point  3  increases and the drain current of MB increases. This causes the voltage at point  2  to decrease and this, in turn, causes the drain current of M 1  to decrease to its previous value. 
       FIG. 3  depicts the small signal analysis of the circuit of  FIG. 2  in the prior art. This analysis is for the circuit at mid-band, where parasitic capacitances are ignored. From  FIG. 3   a , the sum of the two transistor gate-to-source voltages is equal to the voltage drop across resistor RB, or
   V   GS1   +V   GSB   =−g   mB   V   GSB   RB   (Eq. 1) 
       FIG. 3   a  is rearranged in  FIGS. 3   b  and  3   c .  FIG. 3   b  shows the dependent current source between nodes V IN  and V OUT  in  FIG. 3   a  can be split into two dependent current sources to ground. From  FIG. 3   c - 1  and equation (1), since V GS1 =−V GSB  (1+g mB RB), then the value of dependent current source is −g m1 V GSB (1+g mB RB). Since the voltage across the current source is proportional to the current through the source by a factor of V GSB , the current source, with polarity reversed, can be replaced by an equivalent resistor of value 1/(g m1 (1+g mB RB)). Also from  FIG. 3   c - 1 , V GSB =V IN , so
   V   GSB   =RS ∥1/( g   m1 (1 +g   mB   RB ) I   IN   (Eq. 2)   Z   IN   =RS ∥1/( g   m1 (1 +g   mB   RB )≈1/( g   m1 (1 +g   mB   RB )  (Eq. 3) 
Thus, the input impedance is low, an ideal characteristic for an input current source represented by the photodetector.
 
     From  FIG. 3   c - 2 : 
                           V   OUT     =       ⁢       -     g   m1       ⁢     V   GS1     ⁢   R1                 =       ⁢       -   R1     ⁢           ⁢       g   m1     ⁡     (     -       V   GSB     ⁡     (     1   +       g   sB     ⁢   RB       )         )                     =       ⁢       R1I   IN     ⁢       g   m1     [     RS   ⁢          1   /     (       g   m1     ⁡     (     1   +       g   mB     ⁢   RB       )       )       ]     ⁢     (     1   +       g   mB     ⁢   RB       )                       ≈       ⁢       I   IN     ⁢   RB                   (     Eq   .           ⁢   4     )               
so that the transimpedance is:
   V   OUT   /I   IN   ≈RB   (Eq. 5) 
As the circuit operates at higher and higher frequencies, the parasitic capacitances of the transistors must be taken into consideration. They will have the effect of inducing poles into the transimpedance equation 4, thus reducing transimpedance gain.
 
Once the input current has been converted into a voltage by the transimpedance amplifier, it is often desirable to further amplify the voltage output.  FIG. 4  depicts a typical common-source voltage amplifier circuit of the prior art.  FIG. 4   a  is the circuit with input resistance RS connected to the gate of an NMOS transistor. The drain of the transistor is connected to a resistor RD at the output VOUT. RD is also connected to power supply VDD.  FIG. 4   b  is the high frequency model of the common-source amplifier taking parasitic capacitance into effect across the terminals of the transistor. We obtain the transfer function of the voltage amplifier using nodal analysis:
 
                           V   X     -     V   IN         R   S       +       V   X     ⁢     sC   gs       +       (       V   X     -     V   OUT       )     ⁢     sC   gd         =   0           (     Eq   .           ⁢   5     )                     (       V   OUT     -     V   X       )     ⁢     sC   gd       +       g   m     ⁢     V   X       +       V   OUT     ⁡     (       1     R   D       +     sC   db       )         =   0           (     Eq   .           ⁢   6     )               
From (6), V X  can be expressed as
 
                     V   x     =         V   OUT     ⁡     (       sC   gd     +     1     R   D       +     sC   db       )           g   m     -     sC   gd                 (     Eq   .           ⁢   7     )               
By substituting &amp;7) into equation (5), the transfer function of the amplifier is:
 
                               V   OUT       V   IN       ⁢     (   s   )       =                       ⁢         (       sC   gd     -     g   m       )     ⁢     R   D             R   S     ⁢     R   D     ⁢   ξ   ⁢           ⁢     s   2       +       [           R   S     ⁡     (     1   +       g   m     ⁢     R   D         )       ⁢     C   gd       +       R   s     ⁢     C   gs       +       R   D     ⁡     (       C   gd     +     C   db       )         ]     ⁢   s     +   1                     And   ⁢           ⁢   ξ     =         C   gs     ⁢     C   gd       +       C   gd     ⁢     C   db       +       C   gs     ⁢     C   db                       (     Eq   .           ⁢   8     )               
By manipulating equation (8), the denominator can be expressed as:
 
                   D   =         (       s     ω   p1       +   1     )     ⁢     (       s     ω   p2       +   1     )       =         s   2         ω   p1     ⁢     ω   p2         +       (       1     ω   p1       +     1     ω   p2         )     ⁢   s     +   1               (     Eq   .           ⁢   9     )               
The coefficient of s is approximately equal to 1/ω p1  if ω p2  is much higher in frequency. It follows from equation (8) and (9) that the poles are located at:
 
                     ω   p1     =     1           R   S     ⁡     (     1   +       g   m     ⁢     R   D         )       ⁢     C   gd       +       R   S     ⁢     C   gs       +       R   D     ⁡     (       C   gd     +     C   db       )                   (     Eq   .           ⁢   10     )             and                           ω   p2     =             R   S     ⁡     (     1   +       g   m     ⁢     R   D         )       ⁢     C   gd       +       R   S     ⁢     C   gs       +       R   D     ⁡     (       C   gd     +     C   db       )             R   S     ⁢       R   D     ⁡     (         C   gs     ⁢     C   gd       +       C   gs     ⁢     C   db       +       C   gd     ⁢     C   db         )                   (     Eq   .           ⁢   11     )               
This analysis shows that the amplifier gain falls off at about 40 dB per decade of frequency at high frequencies, i.e. frequencies that are likely to be in the range of the data of the fiber optic receiver of  FIG. 1 .
 
     To achieve higher bandwidth for the amplifier of  FIG. 4  in the prior art, an inductance is introduced in series with the load resistor R D .  FIG. 5  shows what is called a shunt peaked amplifier of the prior art.  FIG. 5   a  shows shows capacitance C o  which includes all the capacitance at the output node. When the amplifier is used for a wideband application, inductance L S  in series with resistance R D  extends the bandwidth of the amplifier that is normally limited by the time constant R D C o , by introducing a zero as shown by the small signal analysis represented by the circuit of  FIG. 5   b  as follows: 
                       V   OUT       V   IN       =           g   m     ⁡     (       R   D     +     j   ⁢           ⁢   ω   ⁢           ⁢     L   S         )         1   +     j   ⁢           ⁢   ω   ⁢           ⁢     R   D     ⁢     C   o       -       ω   2     ⁢     L   S     ⁢     C   o           ⁢     
     ⁢           =         g   m     ⁢       R   D     ⁡     (     1   +     j   ⁢           ⁢   ωτ   ⁢           ⁢   m       )           1   +     j   ⁢           ⁢   ωτ     ⁢           -       ω   2     ⁢     τ   2     ⁢   m                   (     Eq   .           ⁢   12     )               
Where τ=R D C o  and m=L S /(R D   2 C o )
 
     In order to bring the resonance frequency close to the bandwidth of the fiber optic receiver of  FIG. 1 , the value of L S  would be unrealistically high and therefore too large to fit on a typical integrated circuit. 
     SUMMARY OF THE INVENTION 
     The present invention provides a transimpedance amplifier, which is useful as an optical fiber preamplifier. The illustrative embodiment is advantageous in four ways. First, it minimizes the equivalent input noise current. Second, it has a wide bandwidth. Third, it has a reasonably large output voltage, and fourth, it is stable over wide temperature and voltage ranges. 
     The illustrative embodiment comprises a transimpedance stage and a gain stage. The transimpedance stage has a low input impedance to minimize input noise current. Both stages employ a pure NMOS design which contributes stability over temperature and power supply fluctuations. Gain is increased by the gain stage. Bandwidth is increased over the prior art by replacing R 1  in  FIG. 2  by an inductive load. A monolithic inductor on an integrated circuit is quite large, so instead of using a monolithic inductor, the illustrative embodiment employs an “active” inductor: the combination of a resistor connected in series with the gate of an NMOS transistor, where the potential at the drain of the NMOS transistor is held below that of the second terminal of the resistor by at least the threshold, or turn-on voltage, of the transistor. This transistor/resistor combination acts inductively at the data rates of interest. These active inductors are also employed in the gain stage of the illustrative embodiment to improve bandwidth. 
     The illustrative embodiment of the present invention comprises: a first transistor having a gate terminal, a drain terminal, and a source terminal; a first resistor having a first terminal and second terminal, wherein the first terminal of the first resistor is electrically connected to the gate terminal of the first transistor; and a second transistor having a gate terminal, a drain terminal, and a source terminal, wherein the drain terminal of the second transistor is electrically connected to the source terminal of the first transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts an architectural diagram of a typical optical receiver. 
         FIG. 2  depicts a schematic of the transimpedance-input stage of a transimpedance amplifier of the prior art. 
         FIG. 3  depicts the small signal analysis of the circuit of  FIG. 2  of the prior art. 
         FIG. 4  depicts a typical common-source voltage amplifier circuit of the prior art. 
         FIG. 5  shows what is called a shunt peaked amplifier of the prior art. 
         FIG. 6  depicts a block diagram of a transimpedance amplifier in accordance with the illustrative embodiment of the present invention. 
         FIG. 7  depicts a schematic diagram of a transimpedance amplifier in accordance with the illustrative embodiment of the present invention. 
         FIG. 8  depicts schematics of the small signal model for the active inductors of  FIG. 5 . 
         FIG. 9  depicts a bode-plot of the magnitude of Z o  as a function of frequency. 
         FIG. 10  shows a common source amplifier stage with active inductor load and feedback resistor of the current embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 6  depicts a block diagram of a transimpedance amplifier in accordance with the illustrative embodiment of the present invention. The transimpedance amplifier  400  comprises transimpedance stage  401  and voltage gain stage  402 . 
       FIG. 7  depicts a schematic diagram of a transimpedance amplifier in accordance with the illustrative embodiment of the present invention. The illustrative embodiment comprises: eight resistors, R 1  through R 6 , RS, and RB, and ten transistors, M 1  through M 10 . In accordance with the illustrative embodiment, transistors M 1  through M 10  are N-Type Enhancement mode transistors, as are well-known to those skilled in the art. 
     Transimpedance stage  401  has a terminal labeled INPUT into which the input current is injected. This INPUT terminal is electrically connected to the gate of transistor M 3 , the source of transistor M 2 , and one terminal of resistor RS. The second terminal of RS and the source terminal of transistor M 3  are connected to ground potential. The gate terminal of transistor M 2  is electrically connected to the drain terminal of transistor M 3  and to one terminal of resistor RB. The drain terminal of transistor M 2  is electrically connected to the source terminal of transistor M 1 . The drain terminal of transistor M 1  is electrically connected to the second terminal of resistor RB and to a supply voltage V EE . The gate terminal of transistor M 1  is electrically connected to one terminal of resistor R 1 , while the second terminal of resistor R 1  is electrically connected to a second voltage supply V DD . Resistor R 1  and transistor M 1  comprise active inductor AI 1 , to be described in  FIG. 6  below. All the substrate terminals of transistors M 1  through M 3  are connected to the lowest potential, which is ground potential. 
     Notice that active inductor AI 1 , if represented by an impedance Z 1 , creates a circuit that closely resembles that of  FIG. 2 , with Z 1  replacing R 1  of  FIG. 2 , M 2  replacing M 1  of  FIG. 2 , M 3  replacing MB of  FIG. 2 , V SS  connected to ground potential, and diode D 1  removed. Thus, the transconductance of stage  401  at mid-band frequencies, ignoring parasitic capacitances, is just Z 1 , the impedance of active inductor AI 1 , thereby increasing bandwidth. 
     The output terminal  501  of the transimpedance stage feeds voltage gain stage  402 , electrically connected to the gate of transistor M 5 . Voltage gain stage  402  comprises common source voltage gain stages, with drain resistors replaced by active inductor pairs R 2 /M 4 , R 3 /M 6 , and R 4 /M 8 . The active inductor pairs of gain stage  402  serve to increase bandwidth. The source terminals of NMOS transistors M 5 , M 7 , M 9 , and M 10  are all connected to each other and ground potential. The substrate terminals of NMOS transistors M 4  through M 10  are also connected to ground potential. The first terminal of each of resistors R 2 , R 3 , and R 4  are electrically connected to power supply V DD . The drain terminals of each of transistors M 4 , M 6 , and M 8  are connected to a second power supply V EE . 
     The source terminal of transistor M 4  is electrically connected to the drain terminal of transistor M 5  and to the gate terminal of transistor M 7 . The gate terminal of transistor M 4  is connected to the second terminal of resistor R 2 . The drain terminal of transistor M 7  is electrically connected to the source terminal of transistor M 6 , to the gate terminal of transistor M 9 , and to the first terminal of resistor R 5 . The gate terminal of transistor M 6  is electrically connected to the second terminal of resistor R 3 . The drain terminal of transistor M 9  is electrically connected to the source terminal of transistor M 8 , to the second terminal of resistor R 5 , and to the gate terminal of transistor M 10 . The gate terminal of transistor M 8  is electrically connected to the second terminal of resistor R 4 . The drain terminal of transistor M 10  is electrically connected to the first terminal of resistor R 6  and to the OUTPUT terminal of gain stage  402 , which is the output terminal of the entire transimpedance amplifier. The second terminal of resistor R 6  is electrically connected to the supply voltage V EE . 
     The illustrative embodiment comprises “active inductors,” which are CMOS-based designs that function as a real inductor in the circuit. While inductors can be used in IC design to enhance the bandwidth of the circuit, a “real” inductor is disadvantageous to implement on an integrated circuit. As a consequence, active inductors are used for the same purpose. In  FIG. 7 , the passive inductor that would appear at the drain terminals of transistors M 1 , M 5 , M 7 , and M 9  in series with resistances, as described in  FIG. 5  of the prior art, are replaced by active inductors. Note that the potential at the drain of the NMOS transistor, V EE  is held below that of the second terminal of the resistor V DD  by at least the threshold, or turn-on voltage, of the transistor. For the illustrative embodiment of the present invention, V DD  is about 3.3 Volts, and V EE  is about  1 . 8  Volts. It should be clear to those skilled in the art that other supply voltages are possible. 
       FIG. 8  depicts schematics of the small signal model for the active inductors of  FIG. 7 .  FIG. 8  represents active inductor AI 1  of  FIG. 7 , but the analysis for active inductor pairs R 2 /M 4 , R 3 /M 6 , and R 4 /M 9  are the same. The DC power supply rails V DD  and V EE  have been replaced by AC ground potentials. At node V g , we have 
                         sC   gs1     ⁡     (       V   g     -     V   o1       )       +       V   g     R1     +       V   g     ⁢   s   ⁢           ⁢     C   gd1         =   0           (     Eq   .           ⁢   13     )               
Rearranging slightly, we have
 
                     V   g     =         sC   gs1     ⁢     R1V   o1         1   +     sR1   ⁡     (       C   gs1     +     C   gd1       )                   (     Eq   .           ⁢   14     )               
At node V OUT   − ,
   I   o1   =g   m1 ( V   g   −V   o1 )+( V   g   −V   o1 ) sC   gs1   −V   o1   sC   L   (Eq. 15) 
Solving (14) and (15), we have
 
                     Z   o     =         V   o1       I   o       ⁢     
     ⁢           =     [       1   +     sR1   ⁡     (       C   gs1     +     C   gd1       )               [     R1   ⁡     (         C   gd1     ⁢     C   gs1       +       C   gs1     ⁢     C   L       +       C   gd1     ⁢     C   L         )       ]     ⁢     s   2       +       [     (       C   gs1     +     C   L     +       g   m1     ⁢   R1   ⁢           ⁢     C   gd1         )     ]     ⁢   s     +     g   m1         ]               (     Eq   .           ⁢   16     )               
From equation (16) the poles (18 and 19) and zero (17) can be identified as:
 
                     Z   1     =     1     R1   ⁡     (       C   gs1     +     C   gd       )                 (     Eq   .           ⁢   17     )                 P   1     =       g   m1         C   gs1     +     C   L     +       g   m1     ⁢     R1C   gd1                   (     Eq   .           ⁢   18     )                 P   2     =         C   gs1     +     C   L     +     C   gd1         R1   ⁡     (         C   gs1     ⁢     C   gd1       +       C   L     ⁢     C   gd1       +       C   L     ⁢     C   gs1         )                 (     Eq   .           ⁢   19     )                 FIG. 9  depicts a bode-plot of the magnitude of Z o  as a function of frequency. In the range of frequency between Z 1  and P 1 , the active inductor induces a zero, increasing gain with frequency, similar in function to a real inductor. The active inductor introduces inductive impedance as a load at the data rates of interest.
   FIG. 10  shows a common source amplifier stage with active inductor load and feedback resistor of the current embodiment of the present invention.  FIG. 10   a  shows the common source amplifier with feedback sub-circuit, while  FIG. 10   b  is the high frequency model for this sub-circuit. At node V OUT ,
 
                         (       V   OUT     -     V     i   ⁢           ⁢   n         )     ⁢     sC   gd       +       (       V   OUT     -     V   IN       )       R   5       +       g   m     ⁢     V   gs       +       V   OUT       Z   o       +       sC   L     ⁢     V   OUT         =   0           (     Eq   .           ⁢   20     )               
And V IN =V GS . Solving (20), we have
 
                       V   OUT       V   IN       =       (     1   -       g   m     ⁢     R   5       +       sC   gd     ⁢     R   5         )       (     1   +       R   5       Z   o       +       sC   gd     ⁢     R   5       +       sC   L     ⁢     R   5         )               (     Eq   .           ⁢   21     )               
Feedback resistor R 5  provides better stability and more linear operation of the common source amplifier than if the amplifier did not have feedback.
 
     The values of resistors R 1  through R 6 , RB, and RS are shown in Table 1. 
     
       
         
               
             
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Values of Resistors R1 through R8 
               
             
          
           
               
                   
                 Device 
                 Value 
               
               
                   
                   
               
             
          
           
               
                   
                 R1 
                 1 
                 KΩ 
               
               
                   
                 R2 
                 2 
                 KΩ 
               
               
                   
                 R3 
                 1.8 
                 KΩ 
               
               
                   
                 R4 
                 700 
                 Ω 
               
               
                   
                 R5 
                 1.5 
                 KΩ 
               
               
                   
                 R6 
                 200 
                 Ω 
               
               
                   
                 RB 
                 400 
                 Ω 
               
               
                   
                 RS 
                 500 
                 Ω 
               
               
                   
                   
               
             
          
         
       
     
     The dimensions of transistors M 1  through M 10  are shown in Table 2. 
     
       
         
               
             
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Dimensions of Transistors M1 through 10 
               
             
          
           
               
                 Device 
                 Dimension 
               
               
                   
               
               
                 M1 
                 W = 5 μm L = 0.18 μm 
               
               
                 M2 
                 W = 24 μm L = 0.18 μm 
               
               
                 M3 
                 W = 12 μm L = 0.18 μm 
               
               
                 M4 
                 W = 18 μm L = 0.18 μm 
               
               
                 M5 
                 W = 28 μm L = 0.18 μm 
               
               
                 M6 
                 W = 8 μm L = 0.18 μm 
               
               
                 M7 
                 W = 30 μm L = 0.18 μm 
               
               
                 M8 
                 W = 8 μm L = 0.18 μm 
               
               
                 M9 
                 W = 30 μm L = 0.18 μm 
               
               
                  M10 
                 W = 16 μm L = 0.18 μm 
               
               
                   
               
             
          
         
       
     
     All ten of the transistors are NMOS because the mobility of electrons in NMOS is greater than the mobility of holes in PMOS. It will be clear to those skilled in the art how to make and use embodiments of the present invention. 
     It is to be understood that the above-described embodiments are merely illustrative of the present invention and that many variations of the above-described embodiments can be devised by those skilled in the art without departing from the scope of the invention. It is therefore intended that such variations be included within the scope of the following claims and their equivalents.