Abstract:
A switched capacitor circuit includes: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese patent application No. 2010-026441, filed on Feb. 9, 2010, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to a switched capacitor circuit. 
     2. Description of Related Art 
     In a circuit that handles a high frequency signal, such as a cellular phone, it is necessary to match a characteristic impedance to transmit a signal power efficiently. Matching the characteristic impedance requires an accurate inductor and capacitor. However, a variation in capacitance value becomes a problem in a semiconductor circuit. Therefore, it is necessary to detect the variation in capacitance value. To detect the variation, both a reference capacitor and an object capacitor are configured to act as switched capacitors. Then, an operational amplifier is driven through these equivalent resistors, thereby detecting the variation in capacitance as a voltage. 
       FIGS. 3A and 3B  show an integrator  1  using a switched capacitor circuit. As shown in  FIGS. 3A and 3B , the integrator  1  includes an operational amplifier OP 1 , a switching capacitor C 1 , a feedback capacitor C 2 , and a switch SW 1 . 
     An operation of the integrator  1  is explained with reference to  FIGS. 3A and 3B . As shown in  FIG. 3A , the switch SW 1  is connected to a side of an input terminal Vin. Assume that an input voltage Vin is applied to the input terminal Vin. At this time, the switching capacitor C 1  is charged according to the voltage Vin. 
     Referring next to  FIG. 3B , the switch SW 1  is connected to a side of an inverting input terminal of the operational amplifier OP 1 . Because voltages at both terminals of the switching capacitor C 1  are set to a ground voltage GND, the electric charge stored in the switching capacitor C 1  is discharged. In this manner, the switching capacitor C 1  is repeatedly charged and discharged by alternately repeating the connection states of  FIGS. 3A and 3B . Assuming that a charge and discharge current is represented by Ij and a switching frequency of the switch SW 1  is represented by Fs at this time, the following expression (1) holds.
 
 Ij=C 1× V in× Fs   (1)
 
     As shown in the expression (1), a constant current flows to the switching capacitor C 1 . Thus, the switching capacitor C 1  can be considered as an equivalent resistance. Therefore, the integrator  1  can be considered as an equivalent circuit like a circuit shown in  FIG. 3C . A time constant T of this integrator  1  is represented by the following expression (2). The time constant T depends only on a relative accuracy regardless of an absolute variation of the capacitors C 1  and C 2 . 
     
       
         
           
             
               
                 
                   
                     
                       
                         T 
                         = 
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                           × 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             Vin 
                             Ij 
                           
                           × 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             Vin 
                             
                               C 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                               × 
                               Vin 
                               × 
                               Fs 
                             
                           
                           × 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             C 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                           
                             C 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                             × 
                             Fs 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
       FIGS. 4A to 4C  show a voltage amplification circuit  2  using a switched capacitor, in which the configuration of the integrator  1  shown in  FIGS. 3A to 3B  is changed. As shown in  FIGS. 4A and 4C , the voltage amplification circuit  2  includes the operational amplifier OP 1 , the switching capacitor C 1 , the feedback capacitor C 2 , and switches SW 1  to SW 3 . 
     An operation of the voltage amplification circuit  2  is explained with reference to  FIGS. 4A and 4B . As shown in  FIG. 4A , the switches SW 1  and SW 2  are connected to a side of the inverting input terminal of the operational amplifier ON, and the switch SW 3  is connected to a side of an output terminal Vout. Assume that an output voltage of the output terminal Vout is represented by Vout. At this time, the capacitors C 1  and C 2  are charged. 
     Referring next to  FIG. 4B , the switch SW 1  is connected to the side of the inverting input terminal, and the switches SW 2  and SW 3  are connected to the side of the ground terminal GND. Therefore, the electric charge stored in the capacitors C 1  and C 2  are discharged. A charging current I 1  flows to the capacitor C 1  and a charging current I 2  flows to the capacitor C 2 , due to the repetition of the charge and discharge. These currents I 1  and I 2  are expressed by the following expressions (3) and (4), respectively.
 
 I 1= C 1× V in× Fs   (3)
 
 I 2= C 1×( V out− V in)× Fs   (4)
 
     The capacitors C 1  and C 2  act as equivalent resistors as seen from the expressions (3) and (4). Then, the voltage amplification circuit  2  can be considered as an equivalent circuit like a circuit shown in  FIG. 4C . 
     When the output voltage Vout at this time is represented by Vin, Expression (5) holds. The output voltage Vout is represented by a capacitance ratio between the capacitors C 1  and C 2 . 
     
       
         
           
             
               
                 
                   
                     
                       
                         Vout 
                         = 
                         
                           Vin 
                           × 
                           
                             
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               + 
                               
                                 R 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           Vin 
                           × 
                           
                             
                               
                                 Vin 
                                 
                                   I 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               + 
                               
                                 
                                   Vout 
                                   - 
                                   Vin 
                                 
                                 
                                   I 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                             
                               Vin 
                               
                                 I 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           Vin 
                           × 
                           
                             
                               
                                 1 
                                 
                                   C 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                   × 
                                   Fs 
                                 
                               
                               + 
                               
                                 1 
                                 
                                   C 
                                   ⁢ 
                                   
                                       
                                   
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                                   2 
                                   × 
                                   Fs 
                                 
                               
                             
                             
                               1 
                               
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                                 1 
                                 × 
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                         = 
                         
                           Vin 
                           × 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   C 
                                   ⁢ 
                                   
                                       
                                   
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                                   1 
                                   × 
                                   Fs 
                                 
                                 
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                                   × 
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                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           Vin 
                           × 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   C 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                                 
                                   C 
                                   ⁢ 
                                   
                                       
                                   
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                                   2 
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     In the manner, assuming that the capacitor C 2  is used as a reference capacitor, for example, a capacitor whose variation is to be detected is connected to the capacitor C 1 . This makes it possible to detect a variation in capacitance as a voltage. 
     Note that an integrator that uses a switched capacitor is disclosed in Japanese Unexamined Patent Application Publication No. 2003-203195. A technique in which a low-pass filter is connected in cascade with a switched capacitor filter is disclosed in Japanese Unexamined Patent Application Publication No. 58-198918. 
     SUMMARY 
     The present inventor has found a problem as described below. The output voltage Vout of the voltage amplification circuit  2  of  FIGS. 4A and 4B  has no relation with the switching frequency Fs as shown by the expression (5). However, since the switches SW 1 , SW 2 , and SW 3  are repeatedly switched in an actual circuit operation, the output terminal Vout of the operational amplifier OP 1  repeats a connection or an open state with respect to the capacitor C 2 . Therefore, noise of the switching frequency Fs (hereafter, referred to as switching noise Ns) is superimposed in the same manner as in Japanese Unexamined Patent Application Publication No. 58-198918. 
     Thus, as shown in  FIGS. 5A and 5B , it is necessary to insert a low-pass filter LPF 1  that includes a resistor R 3  and a capacitor C 3  between the output terminal of the operational amplifier OP 1  and the output terminal Vout to remove the switching noise Ns. In this case, however, it is necessary to increase the order of the low-pass filter LPF 1  or to increase the driving ability of the output of the operational amplifier OP 1  to sufficiently remove the switching noise Ns. However, this causes an increase in circuit size or current consumption of the operational amplifier OP 1 . 
     A first exemplary aspect of the present invention is a switched capacitor circuit including: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the first capacitor between the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other. 
     A second exemplary aspect of the present invention is a switched capacitor circuit that amplitudes an input voltage and outputs at an first output terminal, including: an operational amplifier having a non-inverting terminal receiving the input voltage, an inverting terminal connected with a first node, and an output terminal connected with a second node; a first capacitor connected between a third node and a fourth node; a second capacitor connected between a fifth node and a ground terminal; a third capacitor connected between a sixth node and the ground terminal; a low-pass filter connected between the sixth node and the first output terminal; a first switch that switches a connection between the first node and the third node, or a connection between the third node and the ground terminal in a first predetermined period; a second switch that operates in synchronization with the first switch and switches a connection between the second node and the fourth node, or a connection between the fourth node and the ground terminal in the first predetermined period; a third switch that connects the second node with the sixth node from an open state after a second predetermined period from a time when the second switch connects the second node and the fourth node; and a fourth switch that switches a connection between the first node and the fifth node, or a connection between the fifth node and the ground terminal in the first predetermined period. 
     In the switched capacitor circuit according to the first exemplary aspect of the present invention, the first switch connects the output terminal of the switched capacitor circuit and the output terminal of the operational amplifier after a predetermined time after the first switch connects the first capacitor between the inverting input terminal and output terminal of the operational amplifier. As a result, the noise which is generated during switching of the first switch and output from the operational amplifier is attenuated, and when the output voltage of the operational amplifier reaches a predetermined value, the output terminal of the switched capacitor circuit and the output terminal of the operational amplifier can be connected together. This prevents transmission of the noise to the output terminal of the switched capacitor circuit. Therefore, it is possible to lower the order of the low-pass filter for attenuating the noise, and there is no need to use a high-performance operational amplifier which has higher power consumption. 
     The switched capacitor circuit according to an exemplary aspect of the present invention can remove the switching noise without increasing the order of the low-pass filter and without increasing the current consumption of the operational amplifier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1A  is an exemplary configuration and operation of a switched capacitor in accordance with an exemplary embodiment of the present invention; 
         FIG. 1B  is another exemplary configuration and operation of the switched capacitor in accordance with an exemplary embodiment of the present invention; 
         FIG. 1C  is still another exemplary configuration and operation of the switched capacitor in accordance with an exemplary embodiment of the present invention; 
         FIG. 2  is a timing diagram showing operation of the switched capacitor in accordance with an exemplary embodiment of the present invention; 
         FIG. 3A  is a configuration and operation of an integrator using a switched capacitor in accordance with a related art; 
         FIG. 3B  is another configuration and operation of the integrator using the switched capacitor in accordance with the related art; 
         FIG. 3C  is still another configuration of the integrator using the switched capacitor in accordance with the related art; 
         FIG. 4A  is a configuration and operation of a voltage amplification circuit using a switched capacitor in accordance with a related art; 
         FIG. 4B  is another configuration and operation of the voltage amplification circuit using the switched capacitor in accordance with the related art: 
         FIG. 4C  is still another configuration and operation of the voltage amplification circuit using the switched capacitor in accordance with the related art; 
         FIG. 5A  is a configuration and operation of a switched capacitor circuit in which a low-pass filter is added in accordance with a related art; and 
         FIG. 5B  is another configuration and operation of the switched capacitor circuit in which the low-pass filter is added in accordance with the related art; 
     
    
    
     DETAILED DESCRIPTION 
     An exemplary embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In this exemplary embodiment, a switched capacitor circuit according to the present invention is applied to a voltage amplification circuit  100 . 
       FIGS. 1A to 1C  each show an exemplary configuration and operation of the voltage amplification circuit  100  in accordance with this exemplary embodiment. As shown in  FIGS. 1A to 1C , the voltage amplification circuit  100  includes an operational amplifier OP 1 , capacitors C 1 , C 2 , and C 4 , switches SW 1  to SW 4 , a low-pass filter LPF 1 , an input terminal Vin, and an output terminal Vout. 
     The low-pass filter LPF 1  includes a capacitor C 3  and a resistor R 3 . 
     The operational amplifier OP 1  has a non-inverting input terminal connected to the input terminal Vin, an inverting input terminal connected to a node N 1 , and an output terminal connected to a node N 2 . Hereinafter, a voltage output from the output terminal of the operational amplifier OP 1  is represented by Vop. 
     The switch SW 1  has a terminal “a” connected to one of terminals of the capacitor C 1 , a terminal “b” connected to the node N 1 , and a terminal “c” connected to a ground terminal GND. The switch SW 1  connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S 1 . For instance, when the control signal S 1  of a low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S 1  of a high level is input, the terminal and terminal “c” are connected. 
     The capacitor C 1  has one terminal connected to the terminal “a” of the switch SW 1  and the other terminal connected to the ground terminal GND. 
     The switch SW 2  has a terminal “a” connected to one terminal of the capacitor C 2 , a terminal “b” connected to the node N 1 , and a terminal “c” connected to the ground terminal GND. The switch SW 2  connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S 2 . For instance, when the control signal S 2  of the low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S 2  of the high level is input, the terminal “a” and terminal “c” are connected. 
     The capacitor C 2  has one terminal connected to the terminal “a” of the switch SW 2  and the other terminal connected to the terminal of the switch SW 3 . 
     The switch SW 3  has a terminal “a” connected to the other terminal of the capacitor C 2 , a terminal “b” connected to the node N 2 , and a terminal “c” connected to the ground terminal GND. The switch SW 3  connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S 3 . For instance, when the control signal S 3  of the low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S 3  of the high level is input, the terminal “a” and terminal “c” are connected. 
     The switch SW 4  has a terminal “a” connected to the node N 2 , a terminal “b” connected to a node N 3 . A terminal “c” of the switch SW 4  is open. The switch SW 4  connects between the terminal “a” and the terminal “b”, or between the terminal “a” and the terminal “c” according to a control signal S 4 . For instance, when the control signal S 4  of the low level is input, the terminal “a” and terminal “b” are connected. Moreover, when the control signal S 4  of the high level is input, the terminal “a” and terminal “c” are connected. 
     The capacitor C 4  has one terminal connected to the node N 3  and the other terminal connected to the ground terminal GND. 
     The resistor R 3  has one terminal connected to the node N 3  and the other terminal connected to the output terminal Vout. 
     The capacitor C 3  has one terminal connected to the output terminal Vout and the other terminal connected to the ground terminal GND. 
     An operation of the voltage amplification circuit  100  is described with reference to  FIGS. 1A to 1C  and  FIG. 2 .  FIG. 2  is a timing diagram that shows the operation of the voltage amplification circuit  100 . Note that a circuit unit  110  shown in  FIGS. 1A to 1C  is basically similar in configuration to the voltage amplification circuit  2 . Therefore, the operation of the circuit unit  110  is also basically similar to that described above with reference to  FIGS. 4A to 4C . Therefore, an explanation of a detailed operation of the circuit unit  110  is omitted, and operation different from that of the voltage amplification circuit  2  is mainly described in this exemplary embodiment. 
     First, the control signals S 1  to S 4  are all at a high level before a time t 1 , as shown in  FIG. 2 . As shown in  FIG. 1A , the terminal “a” and the terminal “c” of each of the switches SW 1  to SW 4  are connected. 
     Next, the control signals S 1  to S 3  are at a low level at the time t 1 , as shown in  FIG. 2 . As shown in  FIG. 1B , the terminal “a” and the terminal “b”of each of the switches SW 1  to SW 3  are connected. Here, at the time t 1 , the output terminal of the operational amplifier OP 1  is electrically connected with the non-inverting input terminal via the capacitor C 2  from an open state. Therefore, as shown in  FIG. 2 , the voltage Vop output from the output terminal of the operational amplifier OP 1  has a disturbed waveform. Thus, a similar switching noise Ns similar to that described above with reference to  FIGS. 4A and 4B  is generated. 
     However, because the control signal S 4  remains at the high level, the terminal “a” and the terminal “c” of the switch SW 4  are connected. Therefore, the low-pass filter LPF 1  and the node N 2  are electrically disconnected, thereby preventing the switching noise Ns from being transmitted to the low-pass filter LPF 1 . 
     Next, at a time t 2  after a predetermined period from the time t 1  in  FIG. 2 , the control signal S 4  also becomes low level. Therefore, as shown in  FIG. 1C , the terminal “a” and the terminal “b” of each of the switches SW 1  to SW 4  are connected. Accordingly, the node N 2  and N 3  are electrically connected, and the voltage Vop output from the output terminal of the operational amplifier OP 1  is transmitted to the low-pass filter LPF 1 . At the time t 2 , the voltage Vop has no such a disturbed waveform as described above. Thus, no waveform disturbance occurs in the output voltage Vout output from the output terminal Vout of the voltage amplification circuit  100 . 
     Next, all the control signals S 1  to S 4  become high level at a time t 3  in  FIG. 2 . Therefore, the terminal “a” and the terminal “c” of each of the switches SW 1  to SW 4  are connected, thereby restoring the configuration as shown in  FIG. 1A . 
     Then, the voltage amplification circuit  100  repeats the operation described above. This makes it possible to detect a variation in capacitance as a voltage, assuming the capacity C 2  is used as a reference capacitor and a capacitor whose variation is to be detected is connected to the capacitor C 1 . 
     Here, in the voltage amplification circuit  2  that uses the switched capacitor circuit of the related art, the switching noise is superimposed on the output voltage of the operational amplifier OP 1  and output. It is necessary to connect the low-pass filter LPF 1  shown in  FIG. 5  to remove this switching noise. In this case however, it is necessary to increase the amount of attenuation of the low-pass filter LPF 1 . Therefore, there is a need to increase the size of the resistor R 3  and the capacitor C 3  that constitute the low-pass filter LPF 1 , or to increase the order of the low-pass filter LPF 1 . This results in increased circuit size. 
     Moreover, it is necessary to increase a response speed of the operational amplifier OH when the amount of attenuation of the low-pass filter LPF 1  cannot be increased, and to rapidly settle the waveform disturbance of the output voltage of the operational amplifier OP 1 . This requires an increase in driving ability of the output of the operational amplifier OP 1 , leading to an increase in current consumption of the operational amplifier OP 1 . 
     Here, as shown in  FIGS. 1B and 2 , the terminal “a” of the switch SW 4  is connected with the terminal “c” thereof, and the node N 2  and N 3  are electrically disconnected in the voltage amplification circuit  100  that uses the switched capacitor circuit of this exemplary embodiment, during a period in which the waveform of the output voltage Vop of the operational amplifier OP 1  is disturbed. Then, as shown in  FIG. 1C , the terminal “a” of the switch SW 4  is connected with the terminal “b” thereof after the output voltage Vop of the operational amplifier OP 1  reaches a predetermined voltage, and the nodes N 2  and N 3  are electrically connected. This prevents a great disturbance in waveform of the output voltage Vop of the operational amplifier OP 1  from being transmitted to the low-pass filter LPF 1 . 
     Consequently, the amount of attenuation of the low-pass filter LPF 1  can be reduced, so that the capacitor C 3  and the resistor R 3  that constitute the low-pass filter LPF 1  can be reduced in size. Alternatively, the order of the low-pass filter can be lowered, which makes it possible to employ a one-order low-pass filter like the low-pass filter LPF 1 . This results in suppressing an increase in the size of the voltage amplification circuit  100 . 
     Ideally, it is also possible to omit the low-pass filter LPF 1 . However, it is necessary to leave the low-pass filter LPF 1  because, in practice, a waveform disturbance occurs during switching of the switch SW 4 . Further, the capacity C 4  is required to maintain the input voltage of the low-pass filter LPF 1  while the switch SW 4  is in the open state. 
     Moreover, an output response of the operational amplifier OP 1  can be suppressed in this exemplary embodiment. This means that the time t 2  is delayed. In other word, a time period between the time t 1  and the time t 2  can be increased to such extent as to settle the waveform disturbance of the voltage Vop. Therefore, it is possible to suppress a bias current of an output stage of the operational amplifier OP 1 , and to suppress the current consumption of the operational amplifier OP 1 . Furthermore, a time constant in phase compensation can be sufficiently increased, thereby stabilizing the circuit. 
     Note that the present invention is not limited to the exemplary embodiments described above. 
     While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above. 
     Further, the scope of the claims is not limited by the exemplary embodiments described above. 
     Furthermore, it is noted that, Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution.