Abstract:
An encryption and decryption apparatus includes a round key generator generating at least one round key for iterative operations in each of a plurality of rounds using an input key for one of the encryption and decryption; an initial round key adder receiving a plurality of divided parts of an input data, consecutively receiving a plurality of parts of an initial round key which is output from the round key generator for an initial round and corresponds to each of the divided input data, and adding the input data and the corresponding part of the initial round key; a first operator receiving a first data which is output from the initial round key adder and a part of the round key which is output from the round key generator and performing operations for one of the encryption and decryption; a second operator receiving a second data which is output from the initial round key adder and another part of the round key which is output from the round key generator, and performing operations for one of the encryption and decryption; and a register part temporarily storing the first data which is output from the first operator and the second data which is output from the second operator, inputting the first and second data to the first and second operators, respectively, for operations of a next round among the plurality of the rounds, and outputting an encrypted or decrypted data when the plurality of the rounds are completed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of Korean Patent Application No. 2003-86560, filed on Dec. 1, 2003 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates generally to an apparatus and a method of performing the advanced encryption standard (AES) Rijndael algorithm. More specifically, the present invention is directed to an apparatus and a method of implementing the Rijndael algorithm in a hardware, which can rapidly perform an encryption by dividing data into blocks for parallel-processing operations.  
         [0004]     2. Description of the Related Art  
         [0005]     The Rijndael algorithm has been selected as the Advanced Encryption Standard (AES) for performing an encryption of documents and data information which are transmitted through a network or stored into a smart card or a computer storage. According to the AES, the Rijndael algorithm is a symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256 bits, and outputs 128-bit encrypted data. Other block sizes are possible in addition to 128-bit blocks, but the AES selected 128 bits.  
         [0006]      FIG. 1  illustrates structures of an input data, a state array that is transformed from the input data, and an encrypted or decrypted output data according to the conventional Rijndael algorithm.  
         [0007]     Referring to  FIG. 1 , the input data  101 , the state array  102 , and the output data  103  of 128 bit blocks are structured with four rows of 32 bits each. The input data  101  are encrypted or decrypted to generate the output data  103 . The state array  102  is generated by executing the encryption or decryption operations on the input data  101 .  
         [0008]     In general, the AES Rijndael algorithm is iteratively performed in, what is called, the number of rounds.  FIGS. 2A and 2B  are flowcharts of a round of the general Rijndael algorithm.  
         [0009]     Referring to  FIG. 2A , an input state array is processed by several operations which are called AES rounds. The input state array is processed by a byte substitution operation at operation S 201 , a shiftrow operation at operation S 203 , a mixed columns operation at operation S 205 , and a round key addition operation at operation S 207 , thus performing one AES round.  
         [0010]     The byte substitution operation at operation S 201  is a non-linear byte substitution that independently operates on each byte of the data using a substitution table which is called S-box. The S-box is constructed by the multiplicative inverse in the finite field Galois Field (GF) GF(28) and the affine transformation over GF(28).  
         [0011]     The shiftrow operation at operation S 203  shifts positions of the last three rows, excluding the first row, of the state array  102  without changing the byte values. The mix columns operation at operation S 205  treats elements of each column of the state array  102  as a coefficient of a four-term, order-3, polynomial over GF(28), and transforms the coefficients of the four-term polynomial corresponding to a remainder obtained by multiplying the polynomial by a fixed polynomial a(x)={03}x 3 +{01}x 2 +{01}x+{02} and dividing by x 4 +1.  
         [0012]     The round key addition operation at operation S 207  adds a round key to the state data  102  by a simple bit-wise exclusive-or (XOR) operation. Specific operations of the round of the AES Rijndael algorithm are well-known technologies, and thus, the detailed descriptions are omitted for conciseness.  
         [0013]      FIG. 2B  illustrates an alterative AES round. Referring to  FIG. 2B , the alternative AES round includes a shiftrow operation S 211 , a byte substitution operation S 213 , a mixed columns operation S 215 , and a round key addition operation S 217 .  
         [0014]     The alternative AES round of  FIG. 2B  has the same operations as the AES round of  FIG. 2A . The only difference lies in that the order of the shiftrow operation S 211  and the byte substitution operation S 213  are switched. The alternative AES round of  FIG. 2B  acquires the same results as the AES round of the  FIG. 2A  since the switch of the shiftrow operation S 211  and the byte substitution operation S 213  produces the same results.  
         [0015]     According to the AES algorithm, the data encryption is performed by processing the AES round for a predetermined number of times. The number of the AES rounds Nr depends on a cipher key length. Specifically, the Nr is “10” for a 128-bit cipher key, “12” for a 192-bit cipher key, and “14” for a 256-bit cipher key.  
         [0016]     After the predetermined number of the AES rounds are iteratively processed, a final AES round includes the shiftrow operation S 211  and the byte substitution operation S 213  (or vice versa) followed by the round key addition operation S 217  while omitting the mixed columns operation S 215 , to thus generate the output data  103  of  FIG. 1 .  
         [0017]     The AES Rijndael decryption algorithm is a reverse order of the AES Rijndael encryption algorithm. Accordingly, the decryption of the input data is performed through the inverse byte substitution operation, the inverse shiftrow operation, the inverse mix columns operation, and the round key addition operation S 207 . The alternative AES decryption is similar to the AES Rijndael decryption, thus the detailed description thereof is omitted for conciseness.  
         [0018]     A number of apparatuses have been devised to implement the AES Rijndael algorithm. For example, an apparatus to implement the conventional AES Rijndael algorithm uses only one data processing module to implement all the rounds. Hence, Nr-ary rounds denote that the data processing module performs operations for a single data Nr times. As a result, a time for performing the entire rounds is Nr times as long as a time for performing one round.  
         [0019]     Since the AES Rijndael algorithm requires the additional round key addition operation at the first round execution, the conventional Rijndael algorithm implementation apparatus of iterative loop architecture requires an additional process to operate the data processing module, thus decreasing throughput of the Rijndael algorithm implementation apparatus.  
         [0020]     The conventional Rijndael algorithm implementation apparatus processes a single state array as a whole, and accordingly, requires more resources to configure the data processing modules so as to perform the operations with respect to the whole 128-bit data.  
         [0021]     When the AES Rijndael algorithm implementation apparatus is used in a resource-constrained environment, such as a smart card, a certain level of processing speed should be maintained while keeping the scale of the apparatus small. Thus, the data input to the AES Rijndael apparatus and the data processing are not executed at the same time. In addition, the data processing speed is deteriorated since the data processing modules have to stand by during the data input.  
       SUMMARY OF THE INVENTION  
       [0022]     An aspect of the present invention is to provide an apparatus and a method for implementing the AES Rijndael algorithm in a resource-constrained environment by simultaneously executing data input and data processing through parallel-processing AES rounds using a plurality of input data handling routines.  
         [0023]     According to an aspect of the present invention, the encryption and decryption apparatus includes a round key generator generating at least one round key for iterative operations in each of a plurality of rounds using an input key for one of the encryption and decryption; an initial round key adder receiving a plurality of divided part of an input data, consecutively receiving a plurality of part of an initial round key which is output from the round key generator for an initial round and corresponds to each of the divided input data, and adding the input data and the corresponding part of the initial round key; a first operator receiving a first data which is output from the initial round key adder and a part of the round key which is output from the round key generator and performing operations for one of the encryption and decryption; a second operator receiving a second data which is output from the initial round key adder and another part of the round key which is output from the round key generator, and performing operations for one of the encryption and decryption; and a register part temporarily storing the first data which is output from the first operator and the second data which is output from the second operator, inputting the first and second data to the first and second operators, respectively, for operations of a next round among the plurality of the rounds, and outputting an encrypted or decrypted data when the plurality of the rounds are completed.  
         [0024]     According to an aspect of the present invention, the first and second operators perform the operations according to a Rijndael encryption or decryption algorithm. The first operator includes a first byte substitution part receiving any one of output data from the initial round key adder and the register part and performing one of a Rijndael byte substitution operation and a Rijndael inverse byte substitution operation for one of the encryption or decryption; a first column mixer receiving an output data from the first byte substitution part and performing one of a Rijndael mixed columns operation and a Rijndael inverse mixed columns operation for the encryption and decryption; and a first round key adder receiving any one of output data from the first column mixer and the first byte substitution part, receiving a part of the round key from the round key adder, and performing a round key addition operation.  
         [0025]     According to an aspect of the present invention, the first operator further includes a first selector which receives output data from the initial round key adder and the register part and selectively inputs any one of the output data to the first byte substitution part. The first operator further includes a third selector which receives output data from the first column mixer and the first byte substitution part and selectively inputs the output data to the first round key adder.  
         [0026]     According to an aspect of the present invention, the third selector selects and inputs the output data of the first byte substitution part to the first round key adder at a final round among the plurality of the round. The second operator includes a second byte substitution part receiving output data of the register part and performing one of a Rijndael byte substitution operation and a Rijndael inverse byte substitution operation for the encryption and decryption; a second column mixer receiving output data of the initial round key adder and performing a Rijndael mixed columns operation or a Rijndael inverse mixed columns operation for the encryption and decryption; and a second round key adder receiving any one of output data from the first operator and the second column mixer, receiving a part of the round key from the round key adder, and performing a round key addition operation.  
         [0027]     According to an aspect of the present invention, the second operator further includes a second selector which receives output data from the second column mixer and the second byte substitution part and selectively inputs any one of the output data to the second round key adder. The second selector selects and inputs the output data of the second byte substitution part to the second round key adder at a final round among the plurality of the rounds.  
         [0028]     According to an aspect of the present invention, the register part includes at least one register storing an input data, and a selector receiving data from the register and selectively outputting the data. The register part includes first to sixteenth registers.  
         [0029]     According to an aspect of the present invention, the first to fourth registers receive output data from the first operator, and the fifth to eighth registers receive output data from the second operator. The data stored in the first to eight registers are input to the ninth to sixteenth registers.  
         [0030]     According to an aspect of the present invention, the data stored in the ninth to sixteenth registers are processed through a Rijndael shiftrow operation by the selector, an output data of the selector is input to the first operator and the second operator. The a size of the input data is 128 bits, and the input data is divided into four 32-bit columns and is consecutively input to the initial round key adder.  
         [0031]     Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]     These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:  
         [0033]      FIG. 1  is a diagram illustrating structures of an input data, a state array which is transformed from the input data, and an encrypted or decrypted output data according to a conventional Rijndael algorithm;  
         [0034]      FIGS. 2A and 2B  are flowcharts illustrating operations of the conventional Rijndael algorithm;  
         [0035]      FIG. 3  is a block diagram illustrating an encryption and decryption apparatus implementing the Rijndael algorithm according to an embodiment of the present invention;  
         [0036]      FIG. 4  is a block diagram illustrating the register part of  FIG. 3 ; and  
         [0037]      FIG. 5  is a flowchart illustrating exemplary operations of the encryption and decryption apparatus implementing the Rijndael algorithm according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0038]     Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures.  
         [0039]      FIG. 3  is a block diagram of an apparatus implementing the Rijndael algorithm according to an embodiment of the present invention, which is described in detail below.  
         [0040]     Referring to  FIG. 3 , the Rijndael algorithm implementation apparatus includes a round key generator  310 , an initial round key adder  320 , a first operator  330 , a second operator  340 , and a register part  400 .  
         [0041]     The round key generator  310  receives a key input from an external source and outputs the input key to the initial round key adder  320 , for example, by 32 bits, at an initial round. The round key generator  310  generates round keys corresponding to each round by processing the input key, outputs the round key RKey A of, for example, 32 bits to the first operator  330 , and outputs the round key RKey B of 32 bits to the second operator  340  from a first round.  
         [0042]     The initial round key adder  320  receives a part of data for encryption and decryption and a part of the round key output from the round key generator  310 , and performs addition operations through an XOR operation bit by bit. If the input data is 128 bits, the part of the input data of the initial round key adder  320  may be, for example, 32 bits. Accordingly, the input data  101  of  FIG. 1  is input to the initial round key adder  320  by the row or by the column in sequential order.  
         [0043]     An example case when the part of the data, which is input for the encryption and decryption at one time, is 32 bits. If the input data is 32 bits, the round key output from the round key generator  310  at a time is the same 32 bits as the input data.  
         [0044]     The first operator  330  and the second operator  340  perform operations for the encryption and the decryption. The first operator  330  includes a first selector  331 , a first byte substitution part  333 , a first column mixer  335 , a third selector  337 , and a first round key adder  339 . The second operator  340  includes a second byte substitution part  343 , a second column mixer  345 , a second selector  347 , and a second round key adder  349 .  
         [0045]     The first selector  331  selectively inputs to the first byte substitution part  333  any one of the data output from the initial round key adder  320  or data from the register part  400 . Thus, the new data input and the round operations on the input data are processed together in the first operator  330 .  
         [0046]     The first byte substitution part  333  receives the data output from the first selector  331  and performs a Rijndael byte substitution operation for the encryption or a Rijndael inverse substitution operation for the decryption. The data output from the first byte substitution part  333  is input to the first column mixer  335  or the third selector  337 .  
         [0047]     The first column mixer  335  performs a mixed columns or an inverse mixed columns operation of the Rijndael algorithm on each column of the input data from the first byte substitution part  333 . The data output from the first column mixer  335  is input to the third selector  337 .  
         [0048]     The third selector  337  receives the data output from the first column mixer  335  and the first byte substitution part  333 , selects one of the output data, and selectively inputs the selected data to the first round key adder  339  or the second operator  340 . The first round key adder  339  adds the data input from the third selector  337  and the round key Rkey A input from the round key generator  310  by performing the bit-wise XOR operation. The output data of the first round key adder  339  is input to the register part  400 . The register part  400  stores the data for a predetermined time, performs shift operations of the Rijndael algorithm, and inputs the data to the first selector  331 , thus executing second round operations.  
         [0049]     The second selector  347  of the second operator  340  receives and selectively inputs the data output from the third selector  337  of the first operator  330  and the data from the second byte substitution part  343  and the second column mixer  345 , to the second round key adder  349 .  
         [0050]     The second round key adder  349  receives the data output from the second selector  347  and the round key output from the round key generator  310 , and performs addition operations through the bit-wise XOR operation. The data output of the second round key adder  349  is input to the register part  400 , to end the round operation. The register part  400  stores the data for a predetermined number of times, performs the Rijndael shift operation, and inputs the data to the second byte substitution part  343 , thus executing a next round operation.  
         [0051]     The second byte substitution part  343  receives the data output from the register part  400  and performs either the byte substitution operation for the encryption or the inverse byte substitution operation for the decryption. The output data of the second byte substitution part  343  is input to the second column mixer  345  or the second selector  347 .  
         [0052]     The second column mixer  345  performs either a mixed column or an inverse mixed column operation of the Rijndael algorithm on each column of the data input from the second byte substitution part  343 . The output data of the second column mixer  345  is input to the second selector  347 .  
         [0053]      FIG. 4  is a block diagram illustrating the register part of  FIG. 3 . Referring to  FIG. 4 , the register part  400  includes first to eighth registers  401  to  408 , ninth to sixteenth registers  409  to  416 , and a selector  417 .  
         [0054]     The first to sixteenth registers  401  to  416  store data which are output after performing all the operations of one round with respect to the input data. The first to fourth registers  401  to  404  are input with the output data from the first round key adder  339 . The fifth to eighth registers  405  to  408  are input with the output data from the second round key adder  349 .  
         [0055]     Specifically, the first column of the state array is input to the first to fourth registers  401  to  404 , and the second column of the state array is input to the fifth to eighth registers  405  to  408 . When the third column of the state array is input, the previous first column of the state array stored in the first to fourth registers  401  to  404  is output to and stored in the ninth to twelfth registers  409  to  412 , and the third column of the state array is stored in the first to fourth registers  401  to  404 .  
         [0056]     When the fourth column of the state array is input, the previous second column of the state array stored in the fifth to eighth registers  405  to  408  is output to and stored in the thirteenth to sixteenth registers  413  to  416 , and the fourth column of the state array is stored in the fifth to eighth registers  405  to  408 .  
         [0057]     The selector  417  receives the data output from the ninth to sixteenth registers  409  to  416 , the data stored in the second to fourth registers  402  to  404 , and the data stored in the sixth to eighth data  406  to  408 .  
         [0058]     When the entire rounds of the Rijndael operations are completed for the Rijndael encryption and decryption, either the encrypted or decrypted data are output directly from the first to sixteenth registers  401  to  416  without passing through the selector  417 , which is indicated as E of  FIG. 4 .  
         [0059]      FIG. 5  is a flowchart illustrating exemplary operations of the encryption and decryption apparatus implementing the Rijndael algorithm according to an embodiment of the present invention, which is described in detail below.  
         [0060]     If the initial round begins according to the Rijndael algorithm, data to be encrypted or decrypted is loaded and input to the initial round key adder  320  at operation S 501 . The input data is a part of 128-bit data, such as, for example, a 32-bit data array. That is, the input data corresponds to a single column or row of the input data  101  of  FIG. 1 .  
         [0061]     The round key generator  310  receives the initial key value from the external source and supplies the initial round key adder  320  with the initial round key for the initial round at operation S 503 . The initial round key IKey, which is input to the initial round key adder  320 , corresponds to the size of data input to the initial round key adder  320  and is the part of the entire initial round keys. According to an embodiment of the present invention, the initial round key IKey corresponds to 32 bits.  
         [0062]     The initial round key adder  320  adds the input data and the initial round key at operation S 505 . The data to be encrypted or decrypted is configured, for example, as the input data  101  of  FIG. 1 . After the first column of the input data  101  is input to and added by the initial round key adder  320 , the next column of the input data  101  is processed until the last column of the input data  101  is input and added. Until the whole input data  101  is completely input at operation S 507 , the data is consecutively input to and added by the initial round key adder  320 .  
         [0063]     Depending on the order of the data output from the initial round key adder  320  with respect to the whole data to be encrypted or decrypted, that is, depending on which column of the input data  101  the output data corresponds to at operation S 509 , the Rijndael algorithm implementation apparatus processes the operations of each round of the Rijndael algorithm following separate routines. Specifically, the input data  101  is divided into a plurality of parts and the divided parts are input in order. Depending on the data input order, the operations of each round are divided into two routines to be performed.  
         [0064]     The encryption and decryption apparatus implementing the Rijndael algorithm according to an embodiment of the present invention has two separate operation routines in which the first operator  330  and the second operator  340  are respectively operated, and constituents in each operation routine are independently operated. Accordingly, the operations of each round are performed in parallel following the two separate routines. The round operations of odd-numbered data are processed by the first operator  330  at operation S 515 , and those of even-numbered data are processed by the second operator  340  at operation S 519 . When the first and second operators  330  and  340  complete the round operations of the Rijndael algorithm following the two separate routines at operations S 517  and S 521 , either the encrypted or decrypted data is output at operation S 523 . Table 1 shows constituents of the encryption and decryption apparatus, which perform in each round of the Rijndael operation and in each cycle according to an embodiment of the present invention.  
                                           TABLE 1                       Round   Cycle   Constituents                   1 (initial)   0   Initial round key adder 320               First byte substitution part 333               First column mixer 335               First round key adder 339               Register part 400           1   Initial round key adder 320               First byte substitution part 333               First column mixer 335               Second round key adder 349               Register part 400           2   Initial round key adder 320               First byte substitution part 333               First column mixer 335               First round key adder 339               Register part 400           3   Initial round key adder 320               First byte substitution part 333               First column mixer 335               Second round key adder 349               Register part 400       2   4   First byte substitution part 333               First column mixer 335               First round key adder 339               Second byte substitution part 343               Second column mixer 345               Second round key adder 349               Register part 400           5   First byte substitution part 333               First column mixer 335               First round key adder 339               Second byte substitution part 343               Second column mixer 345               Second round key adder 349               Register part 400            . . .            Nr − 1   (Nr − 1) * 2   First byte substitution part 333               First column mixer 335               First round key adder 339               Second byte substitution part 343               Second column mixer 345               Second round key adder 349               Register part 400           (Nr − 1) * 2 + 1   First byte substitution part 333               First column mixer 335               First round key adder 339               Second byte substitution part 343               Second column mixer 345               Second round key adder 349               Register part 400       Nr   (Nr − 1) * 2 + 2   First byte substitution part 333               First round key adder 339               Second byte substitution part 343               Second round key adder 349               Register part 400           (Nr − 1) * 2 + 3   First byte substitution part 333               First round key adder 339               Second byte substitution part 343               Second round key adder 349               Register part 400                  
 
         [0065]     At the initial round, the data loading and the data input, and the initial round operations are performed at the same time. The first column of the input data  101  is supplied to the first byte substitution part  333  via the initial round key adder  320 , in which either the byte substitution operation for the encryption or the inverse byte substitution operation for the decryption of the Rijndael algorithm is executed. Next, the first column is passed through the first column mixer  335  and the first round key adder  339 , and stored in the first to fourth registers  401  to  404  of the register part  400 .  
         [0066]     During the process of the round operations on the first column of the input data  101 , the second column of the input data  101  is input and supplied to the first byte substitution part  333  via the initial round key adder  320 , in which either the Rijndael byte substitution operation for the encryption or the Rijndael inverse byte substitution operation for the decryption is executed. After performing the column mix operation in the first column mixer  335 , the second column is output from the third selector  337  to the second selector  347 , is added with the round key in the second round key adder  349 , and is stored in the fifth to eighth registers  405  to  408  of the register part  400 .  
         [0067]     During the process of the round operations on the second column of the input data  101 , the third column of the input data  101  is passed through the same routine as the first column of the input data  101  and is stored in the first to fourth registers  401  to  404  of the register part  400 . The previous first column of the input data  101  stored in the first to fourth registers  401  to  404  is output and stored in the ninth to twelfth registers  409  to  412 .  
         [0068]     During the process of the round operations on the third column of the input data  101 , the fourth column of the input data  101  is consecutively input, passed through the same routine as the second column of the input data  101 , and stored in the fifth to eighth registers  405  to  408  of the register part  400 . The previous second column of the input data  101  stored in the fifth to eighth registers  405  to  408  is output and stored in the thirteenth to sixteenth registers  413  to  416 . Table 2 shows outputs of the register part  400  at each cycle according to types of the Rijndael operation.  
                                                                 TABLE 2                                       Outputs of the selector 417            Rijndael operation   Cycle   1   2   3   4   5   6   7   8               Encryption   1   b00   b05   b10   b15   b04   b09   b14   b03           2           b02   b07       b01   b06       Decryption   1       b13   b10               b14           2       b05   b02               b06   b11                  
 
         [0069]     In the first cycle, the register part  400  performs either the Rijndael shiftrow operation or the Rijndael inverse shiftrow operation, the first column of the state array is output as the outputs of the first to fourth registers  401  to  404 , and the second column of the state array is output as the outputs of the fifth to eighth registers  405  to  408  of the register part  400  according to Table 2. The first operator  330  performs either the Rijndael encryption or decryption operation on the output first column of the state array, and the second operator  304  performs either the Rijndael encryption or decryption operation on the output second column of the state array. In the second cycle for the encryption operation, the previous third and fourth columns, which are stored in the first to eighth registers  401  to  408  of the register part  400 , are stored in the ninth to sixteenth registers  409  to  416 . In more detail, values in the first register  401  and the fourth to sixth registers  404  to  406  are stored in the ninth register  409  and the twelfth to fourteenth registers  412  to  414 , respectively. The tenth register  410 , the eleventh register  411 , the fifteenth register  415 , and the sixteenth register  416  preserve the stored value.  
         [0070]     In the second cycle for the encryption operation, the Rijndael shiftrow operation is performed, the third column of the state array is output as first to fourth outputs of the register part  400 , and the fourth column of the state array is output as fifth to eighth outputs of the register part  400 . Hence, the first operator  330  performs the Rijndael encryption operation on the third column of the state array, and the second operator  340  performs the Rijndael operation on the fourth column of the state array.  
         [0071]     In the second cycle for the decryption operation, the third and fourth columns in the first to eighth registers  401  to  408  of the register part  400  are stored in the ninth to sixteenth registers  409  to  416 . Values in the first register  401 , the second register  402 , the fifth register  405 , and the eighth register  408  are stored in the ninth register  409 , the tenth register  410 , the thirteenth register  413 , and the sixteenth register  416 . The eleventh register  411 , the twelfth register  412 , the fourteenth register  414 , and the fifteenth register  415  preserve the stored value. Hence, the first operator  330  performs the Rijndael decryption operation on the third column, and the second operator  340  performs the Rijndael decryption operation on the fourth column of the state array.  
         [0072]     In the second cycle for the decryption operation, the Rijndael inverse shiftrow operation is performed, the third column of the state array is output as first to fourth outputs of the register part  400 , and the fourth column of the state array is output as fifth to eighth outputs of the register part  400 . The first operator  330  performs the Rijndael decryption operation on the third column of the state array, and the second operator  340  performs the Rijndael decryption operation of the fourth column of the state array.  
         [0073]     The register part  400  stores the data and performs the shiftrow operation or the inverse shiftrow operation in the first and second cycles to thus enable either the Rijndael encryption or decryption operation. Thus, the register part  400  allows the simultaneous processing of the data loading and input, and the Rijndael operations at the Rijndael initial round.  
         [0074]     At the final round of the Rijndael algorithm, the data of the first and the second operators  330  and  340  are not processed through the first and second column mixers  335  and  345 . Thus, the output data of the first byte substitution part  333  is input to the third selector  337  and the second byte substitution part  343  is input to the second selector  347 .  
         [0075]     In the light of the foregoing, the round operations are iteratively executed for the predetermined times of Nr-ary rounds, and the final encrypted or decrypted output data  103  is output from the register part  400 .  
         [0076]     The Rijndael encryption or decryption apparatus implementing the Rijndael algorithm according to an embodiment of the present invention, has the two separate routines to process each round operation of the Rijndael algorithm. Accordingly, the loading and input of the data, and the process of the round operations are performed at the same time, and the Rijndael algorithm is rapidly implemented by parallel processing of the round operations following the two separate routines.  
         [0077]     Since the initial round key adder is additionally provided to process the initial round, the Rijndael encryption or decryption apparatus obtains the increased throughput. Since the data are divided and processed in parallel, the data processing modules require less resource. Accordingly, the data processing speed is high even in the resource-constrained environment, for example, in smart cards.  
         [0078]     Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.