Abstract:
Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

Description:
RELATED APPLICATIONS  
       [0001]     This Application is a division of copending U.S. patent application Ser. No. 11/325,786 filed on Jan. 5, 2006 which is continuation-in-part of U.S. patent application Ser. No. 11/070,730, filed on Mar. 2, 2005, which is a divisional of U.S. patent application Ser. No. 10/661,050; filed on Sep. 11, 2003. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to the field of integrated circuits; more specifically, it relates to programmable high-frequency divider circuit with low power consumption.  
       BACKGROUND OF THE INVENTION  
       [0003]     Computer systems employ data input, storage, processing and output integrated circuits. In order to assure proper operation of these circuits, they often need to be time-domain synchronized. In order to provide such synchronization, computer systems typically employ clock circuits for synchronizing the data transfer and process timing of these circuits. Synchronization of these circuits in modern high-performance and low-power computers requires several clock signals of varying frequency that themselves must be synchronized to one another. It is not a trivial undertaking to design such clock circuits that operate at multiple frequencies, with high-speed and with low power consumption.  
       SUMMARY OF THE INVENTION  
       [0004]     A first aspect of the present invention is a master/slave latch comprising: a master latch comprising: a NAND gate having a clock signal input, a data signal input and an output; and an N-clocked inverter stage, a first input of said N-clocked inverter stage connected to said output of said NAND gate and a second input of said clocked inverter connected to said clock signal input; and a slave latch, comprising: a first P-clocked inverter stage, a first input of said first P-clocked inverter stage connected to an output of said N-clocked inverter stage and a second input of said first P-clocked inverter stage connected to said clock signal input; and a second P-clocked inverter stage having an output, an input of said second P-clocked inverter stage connected to an output of said first P-clocked inverter stage and a second input of said second P-clocked inverter stage connected to said clock signal input.  
         [0005]     A second aspect of the present invention is a master/slave latch comprising: a master latch comprising: a NAND gate having a first clock signal input, a data signal input and an output; and an N-clocked inverter stage, a first input of said N-clocked inverter stage connected to said output of said NAND gate and a second input of said clocked inverter connected to said first clock signal input; and a slave latch, comprising: a first dual-clocked inverter stage, a first input of said dual-clocked inverter stage connected to an output of said N-clocked inverter stage, a second input of said dual-clocked inverter stage connected to said first clock signal input and a third input of said dual-clocked inverter stage connected to a second clock signal input; and an inverter stage having an output, an input of said inverter stage connected to an output of said dual-clocked inverter stage.  
         [0006]     A third aspect of the present invention is a clock duty cycle correction circuit, comprising: the master/slave latch according to the second aspect; a first inverter connected between the output of the inverter stage of the slave latch and a first input of a first NAND gate, a second input of the first NAND gate connected to a control signal input of the duty cycle correction circuit; a buffer connected between the data signal input and a first input of a second NAND gate, an output of the first NAND gate connected to a second input of the second NAND gate; and a second inverter connected between an output of the second NAND gate and a output of the clock duty cycle correction circuit.  
         [0007]     A fourth aspect of the present invention is a frequency divider, comprising: a serial shift register comprising at least two master/slave latches according to claim  1 , a data output of each master/slave latch of the shift register connected to a data input of one different master/slave latch of the shift register and a data output of a last master/slave latch of the shift register connected to a data input of a first master/slave latch of the shift register; an output of the frequency divider connected to a data output of a next to last master/slave latch of the shift register; and wherein, a frequency of an output clock signal of the frequency divider is a function of a frequency of an input clock signal to the frequency divider and a number of master/slave latches in the shift register.  
         [0008]     A fifth aspect of the present invention is a programmable frequency divider, comprising: a multiplicity of frequency dividers according to the fourth aspect of the present invention, each frequency divider having a different clock signal output; wherein a number of master/slave latches in each frequency divider is different; means for generating a different reset signal for each frequency divider; and means for selecting and connecting said clock signal output of one of said frequency dividers to a clock output of said programmable frequency divider.  
         [0009]     A sixth aspect of the present invention is a method, comprising: generating, from a first clock signal having a first clock cycle time, a second clock signal having a second clock cycle time, said second clock cycle time greater than said first clock cycle time, an off-time of one cycle of said second clock signal being one first clock cycle time less than an on-time of one cycle of said second clock signal; shifting in time said second clock signal by half the first clock cycle time to generate a third clock signal having a third clock cycle time, said second clock cycle time equal to said third clock cycle time; performing a logical AND of said second clock signal and said third clock signal to generate a fourth clock signal having a fourth cycle time, said third cycle time equal to said fourth cycle time, an on-time of one cycle of said fourth clock signal equal to an off-time of one cycle of said fourth clock signal. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0010]     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:  
         [0011]      FIG. 1  is a schematic diagram of an exemplary programmable frequency divider according to embodiments of the present invention;  
         [0012]      FIG. 2A  is a schematic diagram of a first type divide by 3 or 4 frequency divider circuit according to embodiments of the present invention;  
         [0013]      FIG. 2B  is a schematic diagram of a second type divide by 3 or 4 frequency divider circuit according to embodiments of the present invention;  
         [0014]      FIG. 3  is a schematic diagram of a divide by 5 or 6 frequency divider circuit according to embodiments of the present invention;  
         [0015]      FIG. 4  is a schematic diagram of a divide by 7 or 8 frequency divider circuit according to embodiments of the present invention;  
         [0016]      FIG. 5  is a schematic diagram of a divide by 9 or 10 frequency divider circuit according to embodiments of the present invention;  
         [0017]      FIG. 6A  is a schematic diagram of a one-shot pulse generator according to embodiments of the present invention;  
         [0018]      FIG. 6B  is a timing diagram of the one-shot generator of  FIG. 6A ;  
         [0019]      FIG. 7A  is a schematic diagram of a clock duty cycle correction circuit according to embodiments of the present invention;  
         [0020]      FIG. 7B  is a timing diagram of the clock duty cycle correction circuit of  FIG. 7A ;  
         [0021]      FIG. 8  is a schematic diagram of a first fast latch according to embodiments of the present invention;  
         [0022]      FIG. 9  is a schematic diagram of a frequency a divide by 2 frequency divider circuit according to embodiments of the present invention;  
         [0023]      FIG. 10  is a schematic diagram of a first fast master/slave latch according to embodiments of the present invention;  
         [0024]      FIG. 11  is a schematic diagram of a second fast master/slave latch according to embodiments of the present invention;  
         [0025]      FIG. 12  is a schematic diagram of an exemplary frequency divider circuit that may advantageously utilize the first and second fast master/slave latches according to embodiments of the present invention;  
         [0026]      FIG. 13A  is a schematic diagram of the feedback circuit of  FIG. 12 ;  
         [0027]      FIG. 13B , is block diagram of an exemplary frequency divider homologue circuit for an even integer divide according to embodiments of the present invention n;  
         [0028]      FIG. 13C , is block diagram of a exemplary frequency divider homologue circuit for an odd integer divide according to embodiments of the present invention; and  
         [0029]      FIG. 14  is a schematic diagram of the clock duty cycle correction circuit of  FIG. 12 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]     Unless otherwise noted it should be understood that when a signal is described as divided by a number, it is meant that the frequency of the signal is divided by that number. Unless otherwise stated a signal described as low or zero (0) is a logical 0 and a signal described as a high or one (1) is a logical 1. Transitions from 1 to 0 (high to low) or 0 to 1 (low to high) are similarly defined as logical transitions.  
         [0031]     The present invention utilizes a unique circuit for dividing frequencies by two, two different types of circuits for dividing frequencies by three or four and a homologous set of circuits for frequency division above two (the second type of circuit for dividing by three or four is the lowest member of this set of homologous circuits). The term fast latch refers to a novel latch of the present invention. The fast latch of the present invention has low power consumption and very fast latching speed and is illustrated in  FIG. 8  and described infra. The term fast master/slave latch refers to additional novel latches of the present invention. The fast master/slave latches of the present invention have low power consumption and very fast latching speed and are illustrated in  FIGS. 10 and 11  and described infra.  
         [0032]     An inverter is comprised of a PFET and an NFET, the gates of the PFET and NFET connected to an input of the inverter, drains of the PFET and the NFET connected to the output of the inverter, the source of the PFET connected to VCC (a high voltage terminal of a power supply) and the source of the NFET connected to ground (a low voltage terminal of a power supply.)  
         [0033]     An N-clocked inverter is defined as an inverter comprising: a PFET, a first NFET and a second NFET, a gate of the first NFET connected to a clock signal, gates of the PFET and second NFET connected to an input of the inverter, drains of the PFET and the first NFET connected to an output of the inverter, a source of the first NFET connected to the drain of the second NFET, a source of the PFET connected to VCC (a high voltage terminal of a power supply) and the source of the second NFET connected to ground (a low voltage terminal of the power supply).  
         [0034]     A P-clocked inverter is defined as an inverter comprising: a first PFET, a second PFET and an NFET, a gate of the second PFET connected to a clock signal, gates of the first PFET and the NFET connected to an input of the inverter, drains of the second PFET and the NFET connected to an output of the inverter, a drain of the first PFET connected to a source of the second PFET, a source of the first PFET connected to VCC (a high voltage terminal of a power supply) and the source of the NFET connected to ground (a low voltage terminal of the power supply).  
         [0035]     A dual-clocked inverter is defined as an inverter comprising: a first PFET, a second PFET, a first NFET and a second NFET, gates of the first PFET and second NFET connected to an input of the dual clocked inverter stage, a gate of the second PFET connected to a first clock signal input and a gate of the first NFET connected to a second clock signal input (the signal impressed on the second clock input is the complement of the clock signal impressed on the first clock signal input), drains of the second PFET and the first NFET connected to an output of the inverter, a source of the first NFET connected to a drain of the second NFET, a drain of the first PFET connected a source of the second PFET, a source of the first PFET connected to VCC (a high voltage terminal of a power supply) and a source of the second NFET connected to ground (a low voltage terminal of the power supply).  
         [0036]      FIG. 1  is a schematic diagram of an exemplary programmable frequency divider according to the present invention. A frequency divide circuit produces an output clock signal numerically equal to the frequency of an input clock signal divided by a fixed number, often a whole positive integer. In  FIG. 1 , a programmable frequency divider circuit  100  for outputting an output clock signal DIVCLK based on inputted clock signals CLKIN and CLKINB includes a reset generator  105 , a divide frequency by two circuit (2divider)  110 , a divide frequency by three or four circuit (3/4divider)  115 , divide frequency by five or six circuit (5/6 divider)  120 , a divide frequency by seven or eight circuit (7/8divider)  125 , a divide frequency by nine or ten circuit (9/10divider)  130  and an inverting multiplexer  135 . The number of frequency divider circuits is exemplary and more or less may be used and the numerical division of frequency may be changed as well. The notation CLKINB denotes the complement of CLKIN.  
         [0037]     Reset generator  105  is coupled to an external reset signal EXT RESET for resetting the state of programmable frequency divider circuit  100  and a four-bit SELECT signal (having bits BIT 1 , BIT 2 , BIT 3  and BIT 4 ) for selecting the divide value that the frequency of CLKIN is to be divided by. Reset generator  105  generates a RESET2 signal coupled to a RESET input of 2 divider  110 , a RESET3/4 signal coupled to a RESET input of 3/4 divider  115 , a RESET5/6 signal coupled to a RESET input of 5/6 divider  120 , a RESET7/8 signal coupled to a RESET input of 7/8 divider  125  and a RESET9/10 signal coupled to a RESET input of 9/10 divider  130 . CLKIN is coupled to respective CLKIN inputs of 2 divider  110 , 3/4 divider  115 , 5/6 divider  120 , 7/8 divider  125  and 9/10 divider  130 . CLKINB is coupled to respective CLKINB inputs of 2 divider  110  and 3/4 divider  115  (when 3/4 divider  115  is of the type illustrated in  FIG. 2A  and described infra). There is no CLKINB input to 3/4 divider  115  is of the type illustrated in  FIG. 2B  and described infra. BIT 1  of SELECT is coupled to respective CNTRL inputs of 3/4 divider  115 , 5/6 divider  120 , 7/8 divider  125  and 9/10 divider  130 . The function of the EXT RESET signal is described infra.  
         [0038]     A CLKOUT2 signal from 2 divider  110  is coupled to a first input of inverting multiplexer  135 . CLKOUT2 has a frequency of half that of CLKIN. CLKOUT3 signal from 3/4 divider  115  is coupled to a second input of inverting multiplexer  135  and a CLKOUT4 signal from 3/4 divider  115  is coupled to a third input of inverting multiplexer  135 . CLKOUT3 has a frequency of one third and CLKOUT4 has a frequency of one quarter the frequency of CLKIN. A CLKOUT5/6 signal from 5/6 divider  120  is coupled to a fourth input of inverting multiplexer  135 . CLKOUT5/6 has a frequency of one fifth or one sixth that of CLKIN depending on whether BIT 1  is a one or a zero. A CLKOUT7/8 signal from 7/8 divider  125  is coupled to a fifth input of inverting multiplexer  135 . CLKOUT7/8 has a frequency of one seventh or one eighth that of CLKIN depending on whether BIT 1  is a one or a zero. A CLKOUT9/10 signal from 9/10 divider  130  is coupled to a sixth input of inverting multiplexer  135 . CLKOUT9/10 has a frequency of one ninth or one tenth that of CLKIN depending on whether BIT 1  is a one or a zero.  
         [0039]     Switching inputs of inverting multiplexer  135  are coupled to the SELECT signal. The output of inverting multiplexer  135 , DIVCLK is either CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5/6, CLKOU7/8 or CLKOUT 9/10 based on the value of the bits in the SELECT signal. BIT 1  also determines whether CLKOUT 5/6 is CLKIN divided by 5 or CLKIN divided by 6, whether CLKOUT7/8 is CLKIN divided by 7 or CLKIN divided by 8 and whether CLKOUT9/10 is CLKIN divided by 9 or CLKIN divided by 10. It should be understood that the output of 3/4 divider  115  is CLKOUT3 and CLKOUT4 when 3/4 divider  115  is of the first type, but the output of 3/4 divider  115  its output is a CLKOUT3/4 signal when 3/4 divider  115  is of the second type.  
         [0040]     In one example, CLKIN has a frequency of about 4200 MHz or less and programmable frequency divider circuit  100  runs using a supply voltage (VCC) as low as about 1.15 volts. TABLE I illustrates the value of the frequency of DIVCLK as a function of the value of the frequency of CLKIN based on the values of the bits in the SELECT signal.  
                               TABLE I                       BIT1   BIT2   BIT3   BIT4   DIVCLK                   0   1   1   0   CLKIN/2       1   0   1   0   CLKIN/3       0   0   1   0   CLKIN/4       1   1   0   0   CLKIN/5       0   1   0   0   CLKIN/6       1   0   0   0   CLKIN/7       0   0   0   0   CLKIN/8       1   0   0   1   CLKIN/9       0   0   0   1    CLKIN/10                  
 
         [0041]      FIG. 2A  is a schematic diagram of a first type divide by 3 or 4 frequency divider circuit according to the present invention. In  FIG. 2A , 3/4 divider  115  is comprised of two interconnected similar circuits, a first section  140 A and a second section  140 B.  
         [0042]     First section  140 A includes an inverting multiplexer  145 A, a one-shot generator  150 A and two fast latches  155 A and  160 A. The select input of inverting multiplexer  145 A is coupled to RESET3/4, a first input of the inverting multiplexer is coupled to ground and a second input of the inverting multiplexer is coupled to CLKIN. When RESET3/4 is high, the output of inverting multiplexer  145 A is high and CLKOUT4 is low saving power. When RESET3/4 is low, the output of inverting multiplexer  145 A is inverted CLKIN. The output of inverting multiplexer  145 A is coupled to the input of one-shot generator  150 A which generates an OUT1 signal coupled to the clock (C) input of fast latch  155 A and an OUT2 signal coupled to the C input of fast latch  160 A. One-shot generator  150 A is illustrated in  FIG. 6A  and OUT1 and OUT2 are identical signals illustrated in  FIG. 6B  and described infra. One-shot generator  150 A has two outputs in order to increase drive. RESET is coupled to the RESET input of fast latches  155 A and  160 A. The output (Q) of fast latch  155 A is coupled to the data (D) input of fast latch  160 A through invertors I 1 A and I 2 A and to a first input of NAND gate N 1 A. The output of fast latch  160 A is coupled to the input of inverter I 3 A. The output of inverter I 3 A is coupled to a first input of NAND gate N 2 A and to a first input of NAND gate N 3 A through series inverters I 5 A and I 6 A. BIT 1  is coupled to a second input of NAND gate N 1 A and the output of NAND gate N 1 A is coupled to a second input of NAND gate N 2 A. The output of NAND gate N 2 A is coupled to the data input of fast latch  155 A through inverter I 4 A. A second input of NAND gate N 3 A is coupled to VCC and the output of NAND gate N 3 A passed through series inverters I 7 A and I 8 A to generate CLKOUT4.  
         [0043]     Second section  140 B includes an inverting multiplexer  145 B, a one-shot generator  150 B and two fast latches  155 B and  160 B. The select input of inverting multiplexer  145 B is coupled to RESET3/4, a first input of the inverting multiplexer is coupled to ground and a second input of the inverting multiplexer is coupled to CLKINB. When RESET3/4 is high, the output of inverting multiplexer  145 B is high and CLKOUT3 is low saving power. When RESET3/4 is low, the output of inverting multiplexer  145 B is inverted CLKINB. The output of inverting multiplexer  145 B is coupled to the input of one-shot generator  150 B which generates an OUT1 signal coupled to the C input of fast latch  155 B and an OUT2 signal coupled to the C input of fast latch  160 B. One-shot generator  150 B is illustrated in  FIG. 6A  and OUT1 and OUT2 are identical signals illustrated in  FIG. 6B  and described infra. One-shot generator  150 B has two outputs in order to increase drive. RESET is coupled to the RESET input of fast latches  155 B and  160 B. The output Q of fast latch  155 B is coupled to the D input of fast latch  160 B through invertors I 1 B and I 2 B and to a first input of NAND gate N 1 B. The output of fast latch  160 B is coupled to the input of inverter I 3 B. The output of inverter I 3 B is coupled to a first input of NAND gate N 2 B and to a first input of NAND gate N 3 B through series inverters I 5 B and I 6 B. BIT 1  is coupled to a second input of NAND gate N 1 B and the output of NAND gate N 1 B is coupled to a second input of NAND gate N 2 B. The output of NAND gate N 2 B is coupled to the data input of fast latch  155 B through inverter I 4 B. A second input of NAND gate N 3 B is coupled to the output of inverter I 6 A and the output of NAND gate N 3 B passed through series inverters I 7 B and I 8 B to generate CLKOUT3.  
         [0044]     One-shot generator  150 A generates a clock pulse of user defined length on the rising edge (transition from 0 to 1) of CLKIN and one shot generator  150 B generates the same user defined length pulse on the rising edge of CLKINB which is the falling edge (transition from 1 to 0) of CLKIN. The pair of fast latches  155 A and  160 A ( 155 B and  160 B) connected as a shift register provide a divide by 3 or 4 depending on the value of BIT 1 . NAND gates N 1 A(B) and N 2 A(B) couple the output of fast latches  155 A(B) and  160 A(B) to the input of fast latch  155 A(B). For a divide by 3, BIT 1  is set to 1, causing NAND gates N 1 A(B) and N 2 A(B) to act as a NAND gate with a first input from P 2 A and a second input from P 1 A (NAND gate N 1 A(B) performs the function of inverter I 1 A(B)). For a divide by 4, BIT 1  is set to 0 causing NAND gate N 2 A(B) to act as an inverter, inverting P 2 A(B). The two sections  140 A and  140 B latching on opposite edges of CLKIN provides automatic duty cycle correction via NAND gate N 3 B because P 2 A and P 2 B are shifted exactly half a cycle (of CLKIN) apart. Duty cycle correction is illustrated in  FIG. 7B  and described infra. Note, the separate CLKOUT3 and CLKOUT4 provide increased drive versus a shared CLK3/4 output which is important in high speed circuits. Insufficient drive or high current loading can slow a circuit down.  
         [0045]     In TABLE II, there are only three combinations of logical states of nodes P 1 A/B and P 2 A/B when BIT 1  is a 1 and four combinations of logical states when BIT 1  is a 0. The states are presented in the sequence they appear as the shift register cycles. Only one cycle is shown. The number of different possible states corresponds to the amount by which the frequency of CLKIN is divided.  
                                                         TABLE II                                       Divide by 3       Divide by 4                State/Node   P1A/B   P2A/B   P1A/B   P2A/B               1   1   1   1   1       2   0   1   0   1       3   1   0   0   0       4           1   1                  
 
         [0046]      FIG. 2B  is a schematic diagram of a second type divide by 3 or 4 frequency divider circuit according to the present invention. In  FIG. 2B , 3/4 divider  115  includes an inverting multiplexer  165 , a one-shot generator  170 , two fast latches  175  and  180  and a duty cycle correction circuit  185 . The select input of inverting multiplexer  165  is coupled to RESET3/4, a first input of the inverting multiplexer is coupled to ground and a second input of the inverting multiplexer is coupled to CLKIN. When RESET3/4 is high, the output of inverting multiplexer  165  is high and CLKOUT3/4 is low saving power. When RESET3/4 is low, the output of inverting multiplexer  165  is inverted CLKIN. The output of inverting multiplexer  165  is coupled to the input of one-shot generator  170  which generates an OUT1 signal coupled to the C input of fast latch  175  and an OUT2 signal coupled to the C input of fast latch  180 . One-shot generator  170  is illustrated in  FIG. 6A  and OUT1 and OUT2 are identical signals illustrated in  FIG. 6B  and described infra. One-shot generator  170  has two outputs in order to increase drive. RESET is coupled to the RESET input of fast latches  175  and  180 . The output Q of fast latch  175  is coupled to the D input of fast latch  180  through invertors I 9  and I 10  and to a first input of NAND gate N 4 . The output of fast latch  180  is coupled to the input of inverter I 11 . The output of inverter I 11  is coupled to a first input of NAND gate N 5 . BIT 1  is coupled to a second input of NAND gate N 4  and the output of NAND gate N 4  is coupled to a second input of NAND gate N 5 . The output of NAND gate N 5  is coupled to the data input of fast latch  175  through inverter I 12 . The output of inverting multiplexer  165  is coupled to a CLKB input of duty cycle correction circuit  185  through series inverters  113 ,  114 ,  115 ,  116  and  117 . A DIN input of duty cycle correction circuit  185  is coupled between the output of inverter I 9  and the input of inverter I 10 . BIT 1  is coupled to a CNTRL input of duty cycle correction circuit  185 . The output of duty cycle correction circuit  185  is CLKOUT3/4. Duty cycle correction cycle is illustrated in  FIG. 7A  and described below.  
         [0047]     One-shot generator  150 A generates a clock pulse of user defined length on the rising edge (transition from 0 to 1) of CLKIN. The pair of fast latches  175  and  180  connected as a shift register provide a divide by 3 or 4 depending on the value of BIT 1 . NAND gates N 4  and N 5  couple the outputs of fast latches  175  and  180  to the input of fast latch  175 . For a divide by 3, BIT 1  is set to 1, causing NAND gates N 4  and N 5  to act as a NAND gate with a first input from P 2  and a second input from P 1  (NAND gate N 4  performs the function of inverter I 9 ). For a divide by 4, BIT 1  is set to 0, causing NAND gate N 5  to act as an inverter, inverting P 2 . Since duty cycle correction is only required on odd divisions of frequency (i. e. by 3, 5, 7, 9) when BIT 1 =1 duty cycle correction circuit  185  is in correction mode and when BIT 1 =0 duty cycle correction circuit  185  is in bypass mode.  
         [0048]      FIG. 3  is a schematic diagram of a divide by 5 or 6 frequency divider circuit according to the present invention. In  FIG. 3 , 5/6 divider  120  includes an inverting multiplexer  190 , two one-shot generators  195 A and  195 B, three fast latches  200 ,  205  and  210  arranged as a shift register and a duty cycle correction circuit  215 . The select input of inverting multiplexer  190  is coupled to RESET5/6, a first input of the inverting multiplexer is coupled to ground and a second input of the inverting multiplexer is coupled to CLKIN. When RESET5/6 is high, the output of inverting multiplexer  190  is high and CLKOUT5/6 is low saving power. When RESET5/6 is low, the output of inverting multiplexer  190  is inverted CLKIN. Note duty cycle correction circuit  215  is coupled between fast latch  205  and fast latch  210 , which are the last two latches of the shift register comprised of fast latches  200 ,  205  and  210 . While two one-shot generators are illustrated, (for increased drive) one to three could be used. It will be noticed that 5/6 divider  120  is a homologue of 3/4 divider  115  of  FIG. 2A  in that an additional, third fast latch has been added to the shift register with appropriate additional one-shot generator circuitry.  
         [0049]     One-shot generators  195 A and  195 B generate a clock pulse of user defined length on the rising edge (transition from 0 to 1) of CLKIN. The three fast latches  200 ,  205  and  210  connected as a shift register provide a divide by 5 or 6 depending on the value of BIT 1 . NAND gates N 6  and N 7  couple the output of fast latches  205  and  210  to the input of fast latch  200 . For a divide by 5, BIT 1  is set to 1, causing NAND gates N 6  and N 7  act as a NAND gate with a first input from P 5  and a second input from P 4  (NAND gate N 6  performs the function of inverter I 18 ). For a divide by 6, BIT 1  is set to 0, causing NAND gate N 7  to act as an inverter, inverting P 5 . Since duty cycle correction is only required on odd divisions of frequency when BIT 1 =1 duty cycle correction circuit  215  is in correction mode and when BIT 1 =0 duty cycle correction circuit  215  is in bypass mode.  
         [0050]     In TABLE III, there are only five combinations of logical states of nodes P 3 , P 4  and P 5  when BIT 1  is a 1 and six combinations of logical states of nodes P 3 , P 4  and P 5  when BIT 1  is a 0. The states are presented in the sequence they appear as the shift register cycles. Only one cycle is shown. The number of different possible states corresponds to the amount by which the frequency of CLKIN is divided.  
                                                         TABLE III                                       Divide by 5   Divide by 6            State/Node   P3   P4   P5   P3   P4   P5               1   1   1   1   1   1   1       2   0   1   1   0   1   1       3   0   0   1   0   0   1       4   1   0   0   0   0   0       5   1   1   0   1   0   0       6               1   1   0                  
 
         [0051]      FIG. 4  is a schematic diagram of a divide by 7 or 8 frequency divider circuit according to the invention. In  FIG. 4 , 7/8 divider  125  includes an inverting multiplexer  220 , two one-shot generators  225 A and  225 B, four fast latches  230 ,  235 ,  240  and  245  arranged as a shift register and a duty cycle correction circuit  250 . The select input of inverting multiplexer  220  is coupled to RESET7/8, a first input of the inverting multiplexer is coupled to ground and a second input of the inverting multiplexer is coupled to CLKIN. When RESET7/8 is high, the output of inverting multiplexer  220  is high and CLKOUT7/8 is low saving power. When RESET7/8 is low, the output of inverting multiplexer  190  is inverted CLKIN. Note duty cycle correction circuit  250  is coupled between fast latch  240  and fast latch  245 , which are the last two latches of the shift register comprised of fast latches  230 ,  235 ,  240  and  245 . While two one-shot generators are illustrated, (for increased drive) one to four could be used. It will be noticed that 7/8 divider  125  is a homologue of 5/6 divider circuit of  FIG. 3  in that an additional, fourth fast latch has been added to the shift register with appropriate additional one-shot generator circuitry.  
         [0052]     One-shot generators  225 A and  225 B generate a clock pulse of user defined length on the rising edge (transition from 0 to 1) of CLKIN. The four fast latches  230 ,  235 ,  240  and  245  connected as a shift register provide a divide by 7 or 8 depending upon the value of BIT 1 . NAND gates N 8  and N 9  couple the output of fast latches  240  and  245  to the input of fast latch  230 . For a divide by 7, BIT 1  is set to 1, causing NAND gates N 8  and N 9  act as a NAND gate with a first input from P 9  and a second input from P 8  (NAND gate N 8  performs the function of inverter I 29 ). For a divide by 4, BIT 1  is set to 0, causing NAND gate N 9  to act as an inverter, inverting P 9 . Since duty cycle correction is only required on odd divisions of frequency when BIT 1 =1 duty cycle correction circuit  250  is in correction mode and when BIT 1 =0 duty cycle correction circuit  250  is in bypass mode.  
         [0053]     In TABLE IV, there are only seven combinations of logical states of nodes P 6 , P 7 , P 8  and P 9  when BIT 1 =1 and eight combinations of logical states of nodes P 6 , P 7 , P 8  and P 9  when BIT 1 =0. The states are presented in the sequence they appear as the shift register cycles. Only one cycle is shown. The number of different possible states corresponds to the amount by which the frequency of CLKIN is divided.  
                                                                 TABLE IV                                       Divide by 7   Divide by 8            State/Node   P6   P7   P8   P9   P6   P7   P8   P9               1   1   1   1   1   1   1   1   1       2   0   1   1   1   0   1   1   1       3   0   0   1   1   0   0   1   1       4   0   0   0   1   0   0   0   1       5   1   0   0   0   0   0   0   0       6   1   1   0   0   1   0   0   0       7   1   1   1   0   1   1   0   0       8                   1   1   1   0                  
 
         [0054]      FIG. 5  is a schematic diagram of a divide by 9 or 10 frequency divider circuit according to the present invention. In  FIG. 5 , 9/10 divider  130  includes an inverting multiplexer  255 , three one-shot generators  260 A,  260 B and  260 C, five fast latches  265 ,  270 ,  275 ,  280  and  285  arranged as a shift register and a duty cycle correction circuit  290 . The select input of inverting multiplexer  255  is coupled to RESET9/10, a first input of the inverting multiplexer is coupled to ground and a second input of the inverting multiplexer is coupled to CLKIN. When RESET9/10 is high, the output of inverting multiplexer  255  is high and CLKOUT9/10 is low saving power. When RESET9/10 is low, the output of inverting multiplexer  255  is inverted CLKIN. Note duty cycle correction circuit  290  is coupled between fast latch  280  and fast latch  285 , which are the last two latches of the shift register comprised of fast latches  265 ,  270 ,  275 ,  280  and  285 . While three one-shot generators are illustrated, (for increased drive) one to five could be used. It will be noticed that 9/10 divider  130  is a homologue of 7/8 divider circuit of  FIG. 4  in that an additional, fifth fast latch has been added to the shift register with appropriate additional one-shot generator circuitry.  
         [0055]     One-shot generators  260 A,  260 B and  260 C generate a clock pulse of user defined length on the rising edge (transition from 0 to 1) of CLKIN. The five fast latches  265 ,  270 ,  275 ,  280  and  285  connected as a shift register provide a divide by 9 or 10 depending upon the value of BIT 1 . The four fast latches  230 ,  235 ,  240  and  245  connected as a shift register provide a divide by 9 or 10 depending upon the value of BIT 1 . NAND gates N 10  and N 11  couple the output of fast latches  280  and  285  to the input of fast latch  265 . For a divide by 9, BIT 1  is set to 1, causing NAND gates N 10  and N 11  act as a NAND gate with a first input from P 14  and a second input from P 13  (NAND gate N 10  performs the function of inverter  142 ). For a divide by 4, BIT 1  is set to 0 causing NAND gate N 11  to act as an inverter, inverting P 14 . Since duty cycle correction is only required on odd divisions of frequency when BIT 1 =1 duty cycle correction circuit  290  is in correction mode and when BIT 1 =0 duty cycle correction circuit  290  is in bypass mode.  
         [0056]     In TABLE V, there are only seven combinations of logical states of nodes P 10 , P 11 , P 12 , P 13  and P 14  when BIT 1 =1 and eight combinations of logical states of nodes P 10 , P 11 , P 12 , P 13  and P 14  when BIT 1 =0. The states are presented in the sequence they appear as the shift register cycles. Only one cycle is shown. The number of different possible states corresponds to the amount by which the frequency of CLKIN is divided.  
                                                                                                                       TABLE V                                       Divide by 9   Divide by 10            State/Node   P10   P11   P12   P13   P14   P10   p11   P12   P13   P14                    1   1   1   1   1   1   1   1   1   1   1       2   0   1   1   1   1   0   1   1   1   1       3   0   0   1   1   1   0   0   1   1   1       4   0   0   0   1   1   0   0   0   1   1       5   0   0   0   0   1   0   0   0   0   1       6   1   0   0   0   0   0   0   0   0   0       7   1   1   0   0   0   1   0   0   0   0       8   1   1   1   0   0   1   1   0   0   0       9   1   1   1   1   0   1   1   1   0   0       10                       1   1   1   1   0                  
 
         [0057]      FIG. 6A  is a schematic diagram of a one-shot generator  295  according to the present invention. One-shot generator  295  is exemplary of one-shot generators  150 A and  150 B of  FIG. 2A , one-shot generator  170 B of  FIG. 2B , one-shot generators  195 A and  195 B of  FIG. 3 , one-shot generators  225 A and  225 B of  FIG. 4 , and one-shot generators  260 A,  260 B and  260 C of  FIG. 5 . A first input a NAND gate N 12  is coupled to an IN signal (which in the present invention is CLKIN or CLKINB in the case of one-shot generator  150 B of  FIG. 2A ) and to the input of buffer B 1 . The output of buffer B 1  is coupled to the input of buffer B 2 . The output of buffer B 2  is coupled to the input of inverter I 61 . The output of inverter I 61  is to the input of inverter I 62 . The output of inverter I 62  is coupled to the input of inverter I 63 . The output of inverter I 63  is coupled to a second input of NAND gate N 12 . The output of NAND gate N 12  is coupled to the inputs of inverters I 64  and I 65 . The outputs of inverters I 64  and I 65  are signals OUT1 and OUT2 respectively.  
         [0058]     The propagation delay through buffers B 1  and B 2  and inverters I 61 , I 62  and I 63  is chosen such that OUT1 and OUT2 have a 50% duty cycle at a maximum frequency of MAXFREQ. MAXFREQ is defined as about 5 to 15% higher than the maximum allowable frequency of CLKIN (CLKINMAQXFREQ) and is defined by equation 1: 
 
 MAXFREQ=CLKINMAXFREQ +WINDOW( CLKINMAXFREQ )   (1) 
 
         [0059]     where:  
         [0060]     MAXFREQ=maximum frequency of the one-shot generator;  
         [0061]     CLKINMAXFREQ=maximum frequency divider circuits can operate on; and  
         [0062]     WINDOW=5 to 15%.  
         [0063]     OUT1 and OUT2 will always have a high signal time duration equal to that of the high signal time duration of a clock at MAXFREQ but the low signal time duration of OUT1 and OUT 2 will be greater than the low signal time duration of a clock signal at MAXFREQ. This is illustrated in  FIG. 6B . The difference in frequency between MAXFREQ and CLKINMAXFREQ is purposeful and prevents data just shifted into a fast latch to be shifted again into the following latch on the same clock cycle of any of the frequency divider circuits described supra.  
         [0064]      FIG. 6B  is a timing diagram of the one-shot generator of  FIG. 6A . Each cycle of a CLKIN signal at MAXFREQ=4.545 GHz will have a high signal time duration of 0.11 ns and a low signal time duration of 0.11 ns and OUT1 and OUT2 will have a high signal time durations of 0.11 ns and low signal time durations of 0.11 ns. One cycle of a CLKIN signal at a frequency=3.33 GHz will have a high signal time duration of 0.15 ns and a low signal time duration of 0.15 ns and OUT1 and OUT2 will have high signal time durations of 0.11 ns and low signal time durations of 0.19 ns. Each cycle of a CLKIN signal at a frequency=2.173 GHz will have a high signal time duration of 0.23 ns and a low signal time duration of 0.23 ns and OUT1 and OUT2 will have high signal time durations of 0.11 ns and a low signal time duration of 0.35 ns. Thus, one-shot generator  295  provides a clock signal with a constant high time, which is independent of the high time of CLKIN. It should be remembered that OUT1 and OUT2 are the clock inputs to the fast latches of the divider circuits described supra and those latches switch on the rising clock edge as described infra in relation to  FIG. 8 . In one example, MAXFRQ is about 4.545 GHz, corresponding to a time-period of 0.22 ns. Assuming a 50% duty cycle, the on time is 0.11 ns. 0.11 ns is a short enough clock on time just sufficient to transfer data from the input of a fast latch to the output of the fast latch yet prevent data just shifted into a fast latch to be shifted again into the following fast latch on the same CLKIN (or CLKINB) clock cycle in the frequency divider circuits described supra.  
         [0065]      FIG. 7A  is a schematic diagram of a clock duty cycle correction circuit  300  according to the present invention. Duty cycle correction circuit  300  is exemplary of duty cycle correction circuits  185  of  FIG. 2B, 215  of  FIG. 3, 250  of  FIG. 4  and  290  of  FIG. 5 . In  FIG. 7A , clock duty cycle circuit  300  includes a fast latch  305 , buffer B 3 , inverters I 67  and I 68  and NAND gates N 13  and N 14 . CLKB is coupled to the C input of fast latch  305 . DIN (from a node of a shift register of divider circuits described supra) is coupled to the D input of fast latch  305  and to the input of buffer B 3 . The reset of fast latch  305  is coupled to ground and the output of fast latch  305  is coupled to the input of inverter I 67 . BIT 1  is coupled to a first input of NAND gate N 14  and the output of inverter I 67  is coupled to a second input of NAND gate N 14 . The output of NAND gate N 14  is coupled to a first input of NAND gate N 13  and the output of inverter I 66  is coupled to a second input of NAND gate N 13 . The output of NAND gate N 13  is coupled to the input of inverter I 68 . The output of inverter I 68  is DOUT, which is a duty cycle corrected version of DIN.  
         [0066]     BIT 1  applied to NAND gate N 14  prevents duty cycle correction being performed on even divisions of frequency (see TABLE 1 supra).  
         [0067]      FIG. 7B  is a timing diagram of the clock duty cycle correction circuit of  FIG. 7A .  FIG. 7A  utilizes the operation of 5/6 divider  120  of  FIG. 3  to illustrate duty cycle correction for a divide by 5 operation. In  FIG. 7B , CLK and CLKB have a cycle time of T, DIN has a cycle time of 5T but is high for a time of 3T and low for a time of 2T, a 60% duty cycle). This may also may be seen by referring to the P 4  node column under Divide by 5 of TABLE III which is 11001 (11100) where each one represents a high DIN signal for one CLKIN cycle T and each 0 represents a low DIN signal for one CLKIN cycle T. DELAYDIN is shifted one half CLKIN time cycle (T/2) from DIN. Buffer  166  has the same delay as the total delay through fast latch  305 , inverter I 67  and NAND gate N 14  so that the output of NAND gate N 14  and the output of buffer I 66  are half a clock CLKIN cycle apart (T/2) apart. DOUT, which is the result of NAND gate N 13  of  FIG. 7A  has a signal high time of 2.5T and a signal low time of 2.5T, and thus a 50% duty cycle. That no correction is needed for a divide by 6 may also be seen by referring to the P 4  node column under Divide by 5 of TABLE III, which is 110001 (111000).  
         [0068]      FIG. 8  is a schematic diagram of a fast latch  310  according to the present invention. Fast latch  310  is exemplary of fast latches  155 A,  155 B,  160 A and  160 B of  FIG. 2A , of fast latches  175  and  180  of  FIG. 2B , of fast latches  200 ,  205  and  210  of  FIG. 3 , of fast latches  230 ,  235 ,  240 , and  245  of  FIG. 4 , of fast latches  265 ,  270 ,  275 ,  280  and  285  of  FIG. 5  and of fast latch  305  of  FIG. 7A . Fast latch  310  includes a NAND gate  315  comprised of PFETs (P-channel field effect transistor) T 1  and T 4  and NFETs (N-channel field effect transistor) T 2 , T 3 , T 5  and T 6 , an N-clocked inverter  320  comprised of PFET T 7  and NFETs T 8  and T 9 , a first inverter  325  comprised of a PFET T 10  and an NFET T 11  and a second inverter  330  comprised of a PFET T 12  and an NFET T 13 . First inverter also includes a reset PFET.  
         [0069]     The sources of PFETS T 1 , T 4 , T 7 , T 10  and T 12  are coupled to VCC and the sources of NFETs T 3 , T 6 , T 9  and T 13  and the drain of NFET T 14  are coupled to ground. The gates of PFET T 1  and NFETs T 2 , T 5  and T 8  are coupled to the C (clock) input of fast latch  310 . The gates of PFET T 4  and NFETs T 3  and T 6  are coupled to the D (data) input of fast latch  310 . The drains of PFETs T 1  and T 4  and NFETs T 2  and T 5  and the gates of PFET T 7  and NFET T 9  are coupled to a node P 15 . The source of NFET T 8  is coupled to the drain of NFET T 9 . The drains of PFET T 7  and NFET T 8 , the source of PFET T 14  and the gates of PFET T 10  and NFET T 11  are coupled to a node P 16 . The drains of PFET T 10  and NFET T 11  and the gates of PFET T 12  and NFET T 13  are coupled to a node P 17 . The drains of PFET T 12  and NFET T 13  are coupled to the output (Q) of fast latch  310 . RESET is coupled to the gate of NFET T 14  through serially coupled inverters I 69  and  170 .  
         [0070]     In operation, a high on RESET turns on NFET T 14  bringing node P 16  to ground, turning PFET T 10  on bringing node P 17  high and turning NFET T 13  on bringing Q low. When C is low, PFET T 1  turns on precharging node P 15  high and PFET T 7  and NFET T 8  turns off, isolating node P 16  and preserving the state of node P 16 . When C is high a high or low on D will influence the state of node P 15 . Node P 15  will assume the state corresponding to the inverse of D.  
         [0071]     If, with C high, D is high NFETs T 3  and T 6  turn on, PFET T 4  turns off and, node P 15  is pulled low. With C high, PFET T 7  turns on, NFET T 9  turns off and node P 16  is pulled high. A high on node P 16  turns on NFET T 11  and turns off PFET T 10  bringing node P 17  low. A low on node P 17  turns on PFET T 12  and turns off NFET T 13  bringing Q high.  
         [0072]     If, with C high, D is low NFETs T 3  and T 6  turn off, PFET T 4  turns on and, node P 15  is remains high (the precharge state). With C high, NFET T 9  turns on, PFET T 7  turns off and node P 16  is pulled low. A low on node P 16  turns on PFET T 10  and turns off NFET  11  bringing node P 17  high. A high on node P 17  turns on NFET T 13  and turns off PFET T 12  bringing Q low.  
         [0073]     With C high NFET T 8  turns on and node P 16  is determined by the state of node P 15 , a high on node P 15  turning on NFET T 9  and turning off PFET T 7  bringing node P 16  low and a low on node P 15  turning off NFET T 9  and turning on PFET T 7  bringing node P 16  high. Thus, the state of node P 15  (determined by the state of D) is only transferred to node P 16  when C is high. Since node P 15  is precharge high, transfer of high from P 15  to P 16  is very fast. It should be remembered that the pulse width of C in the frequency divider circuits described supra is user defined and it is this width that determines when data transfer between nodes P 15  and P 16  can take place. The latch capture time is defined by equation 2: 
 
 LCT= 1/(2( CLKINMAXFREQ ))   (2) 
 
         [0074]     where:  
         [0075]     LCT is the latch capture time;  
         [0076]     CLKINMAXFREQ=maximum frequency divider circuits can operate on.  
         [0077]      FIG. 9  is a schematic diagram of a frequency divide by 2 frequency divider circuit according to the present invention. This frequency divider does not utilize fast latches as described supra and is not a homologue of the divider circuits presented supra. In  FIG. 9 , 2 divider  110  includes a first transistor cascade  335 A comprising PFETs T 15  and T 16  and NFETs T 17  and T 18  cascaded between power supply VCC and ground and a second transistor cascade  335 B comprising PFETs T 19  and T 20  and NFETs T 21  and T 22  cascaded between VCC and ground; the source of PFET T 15  (T 19 ) coupled to VCC, the drain of PFET T 15  (T 19 ) coupled to the source of PFET T 16  (T 20 ), the drain of PFET T 16  (T 20 ) coupled to the drain of NFET T 17  (T 21 ) which is node P 18  (P 19 ), the source of NFET T 17  (T 21 ) coupled to the drain of NFET T 18  (T 22 ) and the source of NFET T 17  (T 22 ) coupled to ground. A PFET T 23  and an NFET T 24  form an inverter  340 , the source of PFET T 23  coupled to VCC, the drain of PFET T 23  coupled to the drain of NFET T 24  which is node P 20 , the source of NFET T 24  coupled to ground, the gate of PFET T 23  coupled to node P 18  and the gate of NFET T 24  coupled to node P 19 . An inverter I 71  is coupled between node P 20  and a node P 21 . An inverter I 72  is coupled between node P 21  and the CLKOUT2 output of 2 divider  110 .  
         [0078]     In  FIG. 9 , 2 divider  110  also includes a first inverting multiplexer  345 A and a second inverting multiplexer  345 B. The select input of inverting multiplexer  345 A ( 345 B) is coupled to RESET2, a first input of the inverting multiplexer is coupled to ground (VCC) and a second input of the inverting multiplexer is coupled to CLKINB (CLKIN). When RESET2 is high, the output of inverting multiplexer  345 A is high (VCC) and the output of inverting multiplexer  345 B is low (ground). When RESET2 is low, the output of inverting multiplexer  345 A ( 345 B) is inverted CLKINB (inverted CLKIN). The output of inverting multiplexer  345 A is coupled to the gate of PFETs T 16  and T 19  and an NFET T 25  (node P 22 ). The output of inverting multiplexer  345 B is coupled to the gate of NFETs T 21  and T 18  and a PFET T 26  (node P 23 ). The drain of PFET T 26  and the source of NFET T 25  are coupled to node P 21 . The source of PFET T 26  and the drain of NFET T 25  are coupled to form a node P 24  hence forming a transmission gate. The gates of PFETs T 15  and T 20  and NFETs T 17  and T 22  are coupled to node P 24 . The 2 divider  110  is completed by a pull down NFET T 25 , the drain of NFET T 27  coupled to node P 21 , the source of NFET T 27  coupled to ground, and the gate of NFET T 27  coupled to RESET2. When RESET 2 is high, NFET T 27  is on and node P 21  is pulled low. With node P 21  low, CLKOUT2 is high and no division occurs.  
         [0079]     In operation, when RESET2 is high, node P 21  transitions to 0, node P 22  transitions to 1 and node P 23  transitions to 0, PFETs T 16  and T 20  and NFETs T 18  and T 22  are off, nodes P 18  and P 19  hang, NFET T 25  and PFET T 26  are on and P 21 =P 24 =0. When RESET2 transitions to 0 and if CLKIN=1 and CLKINB=0 then node P 22 =1, node P 23 =0, PFETs T 16  and T 20  and NFETs T 18  and T 22  are off, nodes P 18  and P 19  hang, NFET T 25  and PFET T 26  are on and P 21 =P 24 =0. The 2 divider  110  is essentially a divide by 2 state machine having four states which transition in the following order.  
         [0080]     In state  1 , when RESET2 transitions to 0, CLKIN=0 and CLKINB=1, then node P 22  transitions to 0, node P 23  transitions to 1, PFETs T 15 , T 16 , T 19  and T 20  are on, NFETs T 18  and T 22  are on, node P 18 =1, node P 19 =1, NFET T 24  is on, node P 20  transitions to 0, node P 21  transitions to 1, CLKOUT2 transitions to 0, NFET T 25  and PFET T 26  are off so node P 24 =0.  
         [0081]     In state  2 , when CLKIN transitions to 1 and CLKINB transitions to 0, then node P 24 =0, node P 22  transitions to 1, node P 23  transitions to 0, PFETs T 16  and T 20  are off, NFETs T 18  and T 22  are off, nodes P 18  and P 19  hang at 1, NFET T 24  is on, node P 20 =0, node P 21 =1, CLKOUT2=0, NFET T 25  and PFET T 26  are on so node P 21  transitions to 1 and node P 24  transitions to 1.  
         [0082]     In state  3 , when CLKIN transitions to 0 and CLKINB transitions to 1, then node P 22  transitions to 0, node P 23  transitions to 1, PFETs T 16  and T 20  are on, NFETs T 18  and T 22  are on, node P 18  transitions to 0, node P 19  transitions to 0, PFET T 23  is on, NFET T 24  is off, node P 20  transitions to 1, node P 21  transitions to 0 and CLKOUT2 transitions to 1, NFET T 26  are off so node P 24 =0 so node P 24 =1 retaining its previous value.  
         [0083]     In state  4 , when CLKIN transitions to 1 and CLKINB transitions to 0, then node P 22  transitions to 1, node P 23  transitions to 0, PFET T 26  and NFET T 25  are on, nodes P 24  and P 21  are equal, PFETs T 16  and T 20  are off, NFETs T 18  and T 22  are off, nodes P 18  and P 19  hand at 0, PFET T 23  is on, NFET T 24  is off, node P 20 =1, node P 21 =0 and CLKOUT2 transitions to 1.  
         [0084]     The fours states of 2 divider  110  are illustrated in TABLE VI.  
                       TABLE VI                       Node P24   CLKIN   CLKOUT2                   0   0   0       0   1   0       1   0   1       1   1   1                  
 
         [0085]      FIG. 10  is a schematic diagram of a first fast master/slave latch (hereinafter MS 1  latch)  400  according to the present invention. MS 1  latch  400  is exemplary of latches  460 ,  465 ,  470  and  475  of  FIG. 12 . described infra. In  FIG. 10 , MS 1  latch  400  includes a master latch  405  and a slave latch  410 . Master latch  405  includes a NAND gate  415  comprised of PFETs (P-channel field effect transistor) T 31  and T 34  and NFETs (N-channel field effect transistor) T 32 , T 33 , T 35  and T 36  and a first N-clocked inverter stage  420  comprised of PFET T 37  and NFETs T 38  and T 39 . Slave latch  410  a second first P-clocked inverter stage  425  comprised of a PFET T 40  and T 41  and an NFET T 42  and a second P-clocked clocked inverter  430  comprised of PFETs T 44  and T 45  and an NFET T 46 . A reset NFET T 43  is coupled to first P-clocked inverter stage  425 .  
         [0086]     The sources of PFETs T 31 , T 34 , T 37 , T 40  and T 44  are connected to VCC and the sources of NFETs T 33 , T 36 , T 39 , T 43 , T 42  and T 46  are connected to ground. The gates of PFETs T 31 , T 41  and T 45  and NFETs T 32 , T 35  and T 38  are connected to the C (clock) input of MS 1   400 . The gates of PFET T 34  and NFETs T 33  and T 36  are connected to the D (data) input of MS 1   400 . The drains of PFETs T 31  and T 34  and NFETs T 32  and T 35  and the gates of PFET T 37  and NFET T 39  are connected to a node P 25 . The source of NFET T 38  is connected to the drain of NFET T 39 . The drains of PFET T 37  and NFETs T 38  and T 43  and the gates of PFET T 40  and NFET T 42  are connected to a storage node P 26 . The drains of PFET T 41  and NFET T 42  and the gates of PFET T 44  and NFET T 46  are connected to a storage node P 27 . The drain of PFET T 40  is connected to the source of PFET T 41 . The drains of PFET T 45  and NFET T 46  are connected to the output (Q) of MS 1  latch  400 . RESET is connected to the gate of NFET T 43 .  
         [0087]     In a first state, on a clock (C) transition from low to high, if the data signal (D) is 0 then node P 25  goes to 1 and storage node P 26  stores a 0. First P-clocked inverter stage  425  blocks propagation of the data to storage node P 27 . If D is 1, then P 25  goes to 0, storage P 26  goes to 1 and first P-clocked inverter stage  425  lets allows propagation of the data (with inversion) into to storage node P 27  and storage node P 27  goes to 0. Second P-clocked inverter stage  430  blocks propagation of the data to output Q. Output Q is thus isolated from the storage nodes P 26  and P 27 .  
         [0088]     In a second state, on a clock (C) transition from high to low, node P 25  goes high and the N-clocked inverter stage blocks propagation of the data to storage node P 26  and storage node P 26  retains the value stored before the clock transition.  
         [0089]     In the second state, if the data signal (D) in the first state was 0 then storage node P 26  remains a 0 and first P-clocked inverter stage  425  passes the data on storage node P 26  (with inversion) to storage node P 27  and second P-clocked  430  passes the data on storage node P 27  (with inversion) to output Q which goes low.  
         [0090]     In the second state, if the data signal (D) in the first state was 1 then storage node P 27  remains at 0 and second P-clocked  430  passes the data on storage node P 27  (with inversion) to output Q, which goes high.  
         [0091]     It should be noted that when D is low, the 0 is stored on storage node P 26  but when D is 1, the 1 is stored on both storage node P 26  and P 27 .  
         [0092]      FIG. 11  is a schematic diagram of a second fast master/slave latch (herein after MS 2 )  435  according to embodiments of the present invention. In  FIG. 11 , clocks C and CN are complementary, when C is high, CN is low and when C is low CN is high. In  FIG. 11 , MS 2  latch  435  includes master latch  405  and a slave latch  440 . Master latch  405  has been described supra with respect to  FIG. 10 . Slave latch  440  includes a dual-clocked inverter stage  445  comprised of PFETs T 47  and T 48  and NFETs T 49  and T 50  and an inverter  450  comprised of a PFETs T 52  and an NFET T 53 . A reset NFET T 51  is coupled to dual-clocked inverter stage  445 .  
         [0093]     The sources of PFETs T 47  and T 52  are connected to VCC and the sources of NFETs T 51 , T 50  and T 53  are connected to ground. The gate of PFET T 48  is connected to the C (clock) input of MS 2  latch  435 . The gate of NFET T 49  is connected to the CN (clock complement) input of MS 2  latch  435 . The gates of PFET T 47  and NFET T 50  and the drain of NFET T 51  are connected to storage node P 26 . The drain of PFET T 47  is connected to the source of PFET T 48  and the source of NFET T 49  is connected to the drain of NFET T 50 . The gates of PFET T 52  and NFET T 53  are connected to a node P 28 . The drains of PFET T 52  and NFET T 53  are connected to the output (Q) of MS 2  latch  435 . RESET is connected to the gate of NFET T 51 .  
         [0094]     Operation of MS 2  latch  435  is similar to operation of MS 1  latch  400  of  FIG. 10  except there is only one storage node (P 26 ) which store the value of D whether it a 1 or a 0. MS 2  latch  435  has an advantage in that slave latch  440  transmission time for the stored value to reach Q is evenly balanced.  
         [0095]      FIG. 12  is a schematic diagram of an exemplary frequency divider circuit  455  that may advantageously utilize the first and second fast master/slave latches according to embodiments of the present invention. In  FIG. 12 , frequency divider circuit  455  is similar to frequency divider circuit  125  of  FIG. 4  except the following differences:  
         [0096]     (1) latches  230 ,  235 ,  240  and  245  of  FIG. 4  are replaced respectfully with latches  460 ,  465 ,  470  and  475 , which are MS 1  latches  400  (see  FIG. 10 ) latches;  
         [0097]     (2) the one shot generators  225 A and  225 B of  FIG. 4  are eliminated and the clock inputs (C) of latches  460 ,  465 ,  470  and  475  (latch  460  is the first and latch  475  is the last latch of a register comprised of latches  460 ,  465 ,  470  and  475 ) connected directly to the output of multiplexer  220 ;  
         [0098]     (3) NAND gates N 9  and N 8  are replaced with a feedback circuit  480 , the output of the feedback circuit connected to the data (D) input of latch (first latch)  460 , the output Q of latch (the next to last latch)  475  connected to an IN 3  input of feedback circuit  480 , the output Q of latch  475  (the last latch) connected to an IN 1  input of feedback circuit  480  and the BIT 1  input coupled through an inverter I 78  to an IN 2  input of feedback circuit  480 ;  
         [0099]     (4) duty cycle correction circuit  250  of  FIG. 4  is replaced with duty cycle correction circuit  485 , the output of inverter I 35  coupled to the data in (DIN) input of duty cycle correction circuit  485  through an inverter I 75 ;  
         [0100]     (5) inverters I 39  and I 40  of  FIG. 4  replaced with a buffer B 4 ; and  
         [0101]     (6) inverters I 76  and I 77  coupled in series between the output of inverter I 38  and a CLKBN input of duty cycle correction circuit  485 .  
         [0102]     Duty cycle correction circuit  485  advantageously utilizes a MS 2  latch (see  FIG. 11 ) in the circuit as illustrated in  FIG. 12 , in which case the delays of buffer B 4  and inverter I 41  may be tuned so the total delay though buffer B 4  and inverter I 41  matches the total delay through inverters I 76  and I 77 . Alternatively, duty cycle correction circuit  485  may utilize a MS 1  latch (see  FIG. 10 ) in which case inverters I 76  and I 77  and input CLKBN are eliminated.  
         [0103]     Frequency divider circuit  455  is a divide by 7 or 8 frequency divider circuit and should be considered exemplary of a homologous series of frequency dividers that would differ from frequency divider circuit  455  only in the number of MS 1  latches  400  in the register similarly to homologous series of frequency divider circuits illustrated in  FIGS. 2B, 3 ,  4 , and  5 . Thus, a 3 or 4 frequency divider circuit would use a series of two MS 1  latches  400 , a 5 or 6 frequency divider circuit would utilize a series of three MS 1  latches  400  and a 9 or 10 frequency divider circuit would utilize a series of five MS 1  latches  400 , etc. Homologue frequency dividers utilizing MS 1  latches  400  may replace frequency dividers  115 ,  120 ,  125  and  130  of  FIG. 1 .  
         [0104]      FIG. 13A  is a schematic diagram of the feedback circuit of  FIG. 12 . In  FIG. 13A , feedback circuit  480  comprises NFETs T 55 , T 56  and T 57  and PFETs T 54 , T 58  and T 59 . The gates of PFET T 54  and NFET T 55  are connected to input IN 1 . The gates of NFET T 56  and PFET T 58  are connected to input IN 2  and the gates of NFET T 57  and PFET T 59  are connected to input IN 3 . The source of PFET T 54  and source of PFET T 59  are connected to VCC and sources of NFETs T 56  and T 57  are connected to ground. The drain of PFET T 54  and drains of NFET T 55  and PFET T 59  are connected to output OUT. The drain of PFET T 58  is connected to the source of PFET T 59  and the sources of NFETs T 55  and T 57  are connected to the drain of NFET T 56 . It should be remembered that BIT 1  is coupled through inverter I 78  to IN 2  (see  FIG. 12 ).  
         [0105]      FIG. 13B , is block diagram of a exemplary frequency divider homologue circuit for an even integer divide according to embodiments of the present invention. Only the shift register latches and equivalent logic gate that feedback circuit  480  (see  FIG. 13A ) reduces to are illustrated. In  FIG. 13B , for a even divide (BIT 1 =0) a feedback circuit  480 A is equivelant to an inverter I coupled between the Q output of the last latch and D input to of the first latch. TABLE VI indicates the data stored on each latch for the divide by 7 or 8 frequency divider  455  of  FIG. 12 .  
                               TABLE VI                       CLK Cycle   Latch 1   Latch 2   Latch 3   Latch 4                   1   1   1   1   1       2   0   1   1   1       3   0   0   1   1       4   0   0   0   1       5   0   0   0   0       6   1   0   0   0       7   1   1   0   0       8   1   1   1   0       9   1   1   1   1                    
         [0106]      FIG. 13C , is block diagram of a exemplary frequency divider homologue circuit for an odd integer divide according to embodiments of the present invention. Only the shift register latches and equivalent logic gate that feedback circuit  480  (see  FIG. 13A ) reduces to are illustrated. In  FIG. 13C , for a odd divide (BIT 1 =1) a feedback circuit  480 B is equivelant to a NAND gate N having a first input coupled to the Q output of the last latch, a second input coupled to the Q output of the next to last latch and an output coupled to the D input to of the first latch. TABLE VII indicates the data stored on each latch for the divide by 7 or 8 frequency divider  455  of  FIG. 12 .  
                               TABLE VII                       CLK Cycle   Latch 1   Latch 2   Latch 3   Latch 4                   1   1   1   1   1       2   0   1   1   1       3   0   0   1   1       4   0   0   0   1       5   1   0   0   0       6   1   1   0   0       7   1   1   1   0       8   1   1   1   1                    
         [0107]     The Master Transmission time (MTT) of a MS 1  latch is defined as the time taken for data to get stored as the clock signal transitions from low to high assuming data is already presented to the input of the input of the latch is ready before the C transition. Slave Transmission time (STT) of a MS 1  latch is defined as the time taken for stored data to reach the input of the next MS 1  latch after C transitions from high to low, assuming data is already stored in the slave latch before the C transition. Therefore, the highest frequency of a divider (FREQMAX) using MS 1  latches  400  is given by equation 3: 
 
 FREQMAX= 1/(2×[Max of { MTT, STT }])   (3) 
 
         [0108]     In, one example, homologue frequency dividers having shift registers comprising MS 1  latches  400  are capable of running at frequencies between about 100 MHz and about 4.5 GHz while drawing about 6 mA.  
         [0109]      FIG. 14  is a schematic diagram of clock duty cycle correction circuit  485  of  FIG. 12 . In  FIG. 14 , duty cycle correction circuit  485  includes a MS 2  latch  435 . Duty cycle correction circuit  485  is required only for odd divides because the output is, in the case of a divide by 7) “1 1 1 1 0 0 0.” (see TABLE VII). This is advantageously corrected to be 50%.  
         [0110]     In  FIG. 14 , duty cycle correction circuit includes a MS 2  latch  235 , a buffer B 5 , NAND gates N 16  and N 17  and an inverter I 80 . The CLKB signal is connected to the C input, the CLKBN signal is connected to the CN input, the DIN signal is connected to the D input and the RESET signal is connected to the RESET input of MS 2  latch  435 . The DIN signal is also connected to the input of buffer B 5 . The BIT 1  signal is connected to a first input of NAND gate N 16  and the Q output of MS 2  latch  435  is coupled to a second input of NAND gate N 16  through inverter I 81 . The output of buffer B 5  is connected to a first input of NAND gate N 17  and the output of NAND gate N 16  is connected to a second input of NAND gate N 17 . The output of NAND gate N 17  is coupled to the output Q of MS 2  latch  235  through an inverter I 80 .  
         [0111]     Duty cycle correction circuit  485  operates by MS 2  latch  435  shifting the DIN signal by half a period followed by a logically AND of the original DIN signal and the half-period shifted signal (at Q) to produce 50% duty cycle output.  
         [0112]     A comparison chart for Slave transmission time between MS 1  latch  400  and the MS 2  latch  435  is given in TABLE VII. These values are for a specific corner (VCC voltage level, operating temperature and process specification limit), for comparison purpose.  
                                                       TABLE VII                                       Slave Transmission Time                    Q Rise   Q FALL                        MS1 Latch   21.5 ps   45 ps       MS2 Latch     43 ps   44 ps                  
 
         [0113]     Thus the present invention provides latches and frequency divider circuits with high-speed and with low power consumption.  
         [0114]     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention