Abstract:
The open-drain type output buffer includes a first driver and at east one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to open drain type output buffers. FIG.  1 ( a ) illustrates a circuit diagram of an NMOS open-drain type output buffer system. The NMOS open drain type output buffer system  100  includes an NMOS open drain type output buffer  110  having an output pad  120 . The output pad  120  is connected via a channel  130  to a power supply Vterm (often called a termination power Vterm) via a termination resistor Rterm. The channel  130  represents, for example, a bus or a portion of a bus, over which a device including the open drain type output buffer  110  and other devices (not shown) communicate. 
     The NMOS open-drain type output buffer  10  includes a N-type MOS (NMOS) transistor MN. The NMOS transistor MN has its drain coupled to the termination power Vterm via the output pad  120 , the channel  130  and the termination resistor Rterm. The NMOS transistor MN has its source coupled to the ground power VSS, and the gate of the NMOS transistor MN is controlled by input data DIN. 
     When the logic value of the input data DIN is “1” and a high input data voltage represents the logic “1” state, a pull-down current I flows down from the termination power Vterm (e.g., 1.8V) to ground power VSS (e.g., 1.0V) via the NMOS transistor MN. As a result, an output data DOUT at the output pad  120  and the channel  130  is a low voltage VOL=Vterm−I*Rterm. When the logic value of the input data DIN is “0” and a low input data voltage represents the logic “0” state, the output data DOUT is a high voltage VOH=Vterm. 
     FIG.  1 ( b ) shows the voltage level of the input data DIN in relation to the output data DOUT. In this type of open drain output buffer system  100 , the low voltage VOL as output data DOUT typically represents a logic “1” and the high voltage VOH as output data DOUT typically represents logic “0”. 
     There also exist PMOS output drain buffer systems where a P-type MOS (PMOS) transistor is connected between a high, power supply voltage VDD (e.g., 1.8V) and a low, termination voltage Vterm (e.g., 1.0V). More specifically, the PMOS transistor is connected to the termination voltage Vterm via an output pad, a channel, and a termination resistor Rterm. Here, a low input voltage DIN representing a logic “0” produces a low output voltage DOUT also representing a logic “0”, and a high input voltage DIN representing a logic “1” produces a high output voltage DOUT representing a logic “1”. 
     Unfortunately, open drain type output buffer systems such as discussed above are adversely affected by Intersymbol Interference (ISI). ISI is where previous symbols cause an unwanted variation in the voltage representing successive symbols. As such ISI can result in the erroneous detection of the output data DOUT. FIGS.  2 ( a ),  2 ( b ),  3 ( a ) and  3 ( b ) illustrate examples of the voltage variation in the output data DOUT caused by ISI for the open drain type output buffer system  100  in FIG.  1 ( a ). 
     FIG.  2 ( a ) shows a voltage variation Δ1 of the output data DOUT caused by ISI when input data DIN transitions from two successive logic “1”s to “0”. As shown, the channel attenuation of the output data DOUT is represented by A, when the input data DIN toggles between logic value “0”and “1”. As the input data DIN toggles between logic “0” and “1”, the output data DOUT voltage transitions between a high voltage level VOH=Vterm−A and a low voltage level VOL=Vterm−I*Rterm+A. As further shown, the logic state of the output data DOUT is determined based on the voltage level of the output data DOUT in relation to a reference voltage Vref. When the output data DOUT exceeds the reference voltage Vref, the output data DOUT is recognized as a logic “0”; and when the output data DOUT is less than the reference voltage Vref, the output data DOUT is recognized as a logic “1”. 
     When the input data DIN is two successive “1”, the channel attenuation of the output data DOUT reduces to A−Δ1 due to the increased turn-on time of the NMOS transistor MN. This causes an increase in the transition time, which is the time for the output data DOUT to transition above or below the reference voltage Vref when changing from one logic value to another. 
     FIG.  2 ( b ) illustrates a voltage variation Δ2 of the output data DOUT caused by ISI when the input data DIN transitions from three successive logic “1”s to “0”. The channel attenuation A−Δ2 of the output data DOUT in this situation is even less than the case of transitioning from two successive “1”s to “0”. The lengthening of the transition time T 1  during toggling of the input data DIN to the transition time T 2  in this instance demonstrates the amount of skew that occurs in the voltage of the output data DOUT as a result of the ISI. 
     FIG.  3 ( a ) illustrates a voltage variation Δ1 of the output data DOUT cause by ISI when the input data DIN transitions from two successive logic “0”s to “1”. As stated before, when the input data DIN toggles between logic value “0” and “1”, the channel attenuation of the output data DOUT is A so that the high voltage level of the output data DOUT is VOH=Vterm−A and the low voltage level of the output data DOUT is VOL=Vterm−I*Rterm+A. When the input data DIN is two successive “0”s, the channel attenuation of the output data DOUT reduces to A−Δ1 due to the increased turn-off time of the NMOS transistor MN. Consequently, the transition time of the output data DOUT is skewed in a manner similar to that discussed above with respect to FIG.  2 ( a ). 
     FIG.  3 ( b ) illustrates a voltage variation Δ2 of the output data DOUT caused by ISI when the input data DIN transitions from three successive logic “0”s to “1”. The channel attenuation A−Δ2 of the output data DOUT is even less than the case of the transition from two successive logic “0”s to “1” due to the increased turn-off time of the NMOS transistor MN. Consequently, the transition time of the output data DOUT is skewed in a manner similar to that discussed above with respect to FIG.  2 ( b ). 
     SUMMARY OF THE INVENTION 
     In the present invention, the open drain type output buffer includes a control circuit that detects the potential for skew in transition time of the output data and controls a driver circuit to mitigate against the skew. 
     In one exemplary embodiment, the driving circuit includes a first driver and at least one secondary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary driver has first and second states. The secondary driver pulls the output node towards the low voltage when in the first state, but does not pull the output node towards the low voltage in the second state. The control circuit determines when at least two consecutive low voltage output data at an output node have been generated, and controls the secondary driver such that the secondary driver is in the second state when the control circuit determines at least two consecutive low voltage output data have been generated. 
     In another exemplary embodiment, the driving circuit includes a first driver and at least one secondary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary driver has first and second states. The secondary driver pulls the output node towards the low voltage when in the first state, but does not pull the output node towards the low voltage in the second state. The control circuit determines when a transition from a steady high voltage output data to a low voltage output data occurs at an output node and controls the secondary driver such that the secondary driver is in the first state when the transition is determined. 
     A further embodiment of the invention combines the features of above-described embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given below and the accompanying drawings, wherein like elements are represented by like reference numerals, which are given by way of illustration only and thus are not a limit on the present invention and wherein: 
     FIG.  1 ( a ) illustrates a circuit diagram of a prior art NMOS open drain type output buffer system; 
     FIG.  1 ( b ) shows the voltage level of the input data DIN in relation to the output data DOUT for the NMOS open drain type output buffer system of FIG.  1 ( a ); 
     FIGS.  2 ( a ),  2 ( b ),  3 ( a ) and  3 ( b ) illustrate examples of the voltage variation in the output data DOUT caused by Intersymbol Interference for the NMOS open drain type output buffer system in FIG.  1 ( a ); 
     FIG. 4 illustrates a circuit diagram of an embodiment of an NMOS open drain type output buffer system according to the present invention; 
     FIG. 5 illustrates the voltage variation in the output data DOUT generated by the open drain type output buffer of FIG. 4 for exemplary input data DIN; and 
     FIG. 6 each illustrates a circuit diagram of another embodiment of an open drain type output buffer according to the present invention. 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     FIG.4 illustrates a circuit diagram of an embodiment of an NMOS open drain type output buffer system according to the present invention. In this embodiment, a low voltage level as an input voltage DIN represents a logic “0”, a high voltage level as an input voltage DIN represents a logic “1”, a low voltage level as an output data DOUT represents a logic “1”, and a high voltage level as an output data DOUT represents a logic “0”. A low voltage level means a voltage low enough to turn off an NMOS transistor, and a high voltage level means a voltage high enough to turn on an NMOS transistor. 
     As shown in FIG. 4, the NMOS open drain type output buffer system includes an NMOS open drain type output buffer  400  having an output pad POUT. The output pad POUT is connected via an output node NOUT and a channel  460  to a power supply Vterm (called a termination power) via a termination resistor Rterm. The channel  460  represents, for example, a bus or a portion of a bus, over which a device including the open drain type output buffer  400  and other devices (not shown) communicate. 
     The NMOS open-drain type output buffer  400  includes the output pad POUT, a driver circuit  410 , and a control circuit  420 . The output node NOUT is anywhere on the channel  460 . The voltage of the output node NOUT is that of the output pad POUT. 
     The control circuit  420  includes a first determining control circuit  440 , a second determining control circuit  450  and a latch circuit  430 . The control circuit  420  receives input data DIN per clock edge of a clock CLK and generates a first control signal CTRL 1  and a second control signal CTRL 2  to partially control operation of the driver circuit  410 . 
     The latch circuit  430  includes a first latch  431  and a second latch  433 . The first and second latches  431  and  433  are D-type edge-triggered flip-flops and latch at their input D per clock edge of the clock CLK. The first latch  431  latches the input data DIN per the clock edge of clock CLK and outputs a first output signal D 1 . The second latch  433  latches the first output signal D 1  per clock edge of the clock CLK and outputs a second output signal D 2 . Accordingly, with respect to a current input data DIN, the first and second output signals D 1  and D 2  represent the two previous input data DIN. 
     The first determining control circuit  440  includes a NAND gate  441  and an AND gate  443 . The input signals of the NAND gate  441  are the first output signal D 1  and the second output signal D 2  of the latch circuit  430 . The AND gate  443  receives the output of the NAND gate  441  and the input data DIN, and generates the first control signal CTRL 1 . 
     The first determining control circuit  440  generates the first control signal CTRL 1  of low voltage level when the first and second output signals D 1  and D 2  are logic “1” (high voltage levels in this embodiment), irrespective of the current logic value of the input data DIN. When either of the logic values of the first and second output signals D 1  and D 2  is a logic “0” (low voltage level in this embodiment), the voltage level of the first control signal CTRL 1  is based on the logic value of the input data DIN. Namely, if the input data DIN has logic value “0”, then the first control signal CTRL 1  is a low voltage, and if the input data DIN has logic value “1”, then the first control signal CTRL 1  is a high voltage. 
     The second determining control circuit  450  includes a NOR gate  451  and an AND gate  453 . The input signals of the NOR gate  451  are the first and second output signal D 1  and D 2  of the latch circuit  430 . The AND gate  453  receives the output of the NOR gate  451  and the input data DIN, and generates the second control signal CTRL 2 . 
     The second determining control circuit  450  generates the second control signal CTRL 2  of high voltage level when the first and second output signals D 1  and D 2  are logic value “0”s and the logic value of the input data DIN is “1”. When the logic value of the first and second output signals D 1  and D 2  are not both logic value “0”s or the logic value of input data DIN is not “1”, the second control signal CTRL 2  is a low voltage. 
     The driver circuit  410  includes a first driver DRV 1 , a second driver DRV 2 , and a third driver DRV 3 . The drivers DRV 1 , DRV 2  and DRV 3  are connected between the output node NOUT and the ground power VSS in parallel. The drivers DRV 1 , DRV 2  and DRV 3  control the voltage level of the output node NOUT according to the input data DIN and the first and second control signals CTRL 1  and CTRL 2 . 
     The first driver DRV 1  is an NMOS transistor having a first gate width size. The source and drain of the NMOS transistor are coupled to the ground power VSS and the output node NOUT, respectively. The gate of the NMOS transistor for the first driver DRV 1  is coupled to the input data DIN via an AND gate  415 . The AND gate  415  ANDs the input data DIN with a power supply voltage VCC. Accordingly, when the device including the open drain type output buffer is off the first driver DRV 1  is off. More particularly, however, the AND gate  415  serves as a delay so that the input data DIN reaching the gate of the first driver DRV 1  is offset from the first and second control signals CTRL 1  and CTRL 2  reaching the second and third drivers DRV 2  and DRV 3 , respectively. 
     When the logic value of the input data DIN is “1”, the first driver DRV 1  drives a first pull-down current I 1  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is VOL=Vterm−I 1 *Rterm. 
     The second driver DRV 2  is an NMOS transistor having a second gate width size. The second gate width size is less than the first gate width size. The source, drain and gate of the NMOS transistor are coupled to the ground power VSS, the output node NOUT and the output of the first determining control circuit  440 , respectively. When the first control signal CTRL 1  is a high voltage (e.g., logic “1”), the second driver DRV 2  drives a second pull-down current I 2  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is VOL=Vterm−I 2 *Rterm. Accordingly, when both the first and second drivers DRV 1  and DRV 2  are turned on, the level of the output voltage DOUT becomes VOL=Vterm−I 1 *Rterm−I 2 *Rterm. In one exemplary embodiment of the present invention, the first and second gate width sizes are established such that the data output DOUT voltage achieved when the first and second drivers DRV 1  and DRV 2  are turned on is substantially equal to the low voltage VOL of the output data in the prior art open drain type output buffer of FIG.  1 ( a ). As will be appreciated from the description in this application, the gate width sizes chosen for the first and second drivers DRV 1  and DRV 2  are design parameters established based on the application of the open drain type output buffer. However, in one exemplary embodiment, the gate width sizes where established so that I 1 =25 mA and I 2 =5 mA. 
     The third driver DRV 3  is an NMOS transistor having a third gate width size, which is less than the first gate width size. The source, drain and gate of the NMOS transistor are coupled to the ground power VSS, the output node NOUT and the output of the second determining control circuit  450 , respectively. When the second control signal CTRL 2  is a high voltage (e.g., logic “1”), the third driver DRV 3  drives a third pull-down current I 3  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is Vterm−I 3 *Rterm. Accordingly, when the first, second and third drivers DRV 1 , DRV 2  and DRV 3  are turned on, the level of the output voltage DOUT becomes VOL=Vterm−I 1 *Rterm−I 2 *Rterm−I 3 *Rterm. 
     Exemplary operation of the open drain type output buffer according to the present invention will now be described with reference to FIG.  5 . FIG.5 illustrates the voltage variation in the output data DOUT generated by the open drain type output buffer of FIG. 4 for exemplary input data DIN. The voltage level at the output node NOUT is determined by the combination of the pull-down currents I 1 , I 2  and I 3  driven by the first driver DRV 1 , the second driver DRV 2  and DRV 3 , respectively. 
     A First Case—The Output Data DOUT Toggles between a High Voltage Level and a Low Voltage Level 
     As indicated under Type I in FIG. 5, in the embodiment of FIG. 4, the output data DOUT toggles between a high voltage level and a low voltage level when the logic value of the input data DIN repeats “0” and “1” (i.e., toggles between a low voltage level and a high voltage level). As a result, the outputs of the latch circuit  430 , which are the first and second output signals D 1  and D 2 , are different. The output of the NOR gate  451  is thus a logic “0” such that the logic value of the second control signal CTRL 2  is “0” regardless of the logic value of the input data DIN. Therefore, the third driver DRV 3  is in a turned-off state regardless of the logic value of the input data DIN. 
     When the logic value of the input data DIN repeats “0” and “1”, the logic value of the NAND gate  441  is “1”. Accordingly, the logic value of the first control signal CTRL 1  is determined by the logic value of the input data DIN. For example, when the logic value of the input data DIN is “1”, the logic value of the first control signal CTRL 1  is “1” (a high voltage level) and when the logic value of the input data DIN is “0”, the logic value of the first control signal CTRL 1  is “0” (a low voltage level). Therefore, the second driver DRV 2  is in a turned-on state when the input data DIN is logic value “1”, and is in a turned-off state when the input data DIN is logic value “0”. 
     Similarly, the state of the first driver DRV 1  is controlled by the input data DIN such that the first driver DRV 1  is in a turned-on state when the input data DIN is logic value “1”, and is in a turned-off state when the input data DIN is logic value “0”. 
     In view of the above, when the logic value of the input data DIN repeats “0” and “1”, the output voltage DOUT is driven to the high voltage level VOH=Vterm when the input data DIN is logic value “0”. When the input data DIN is logic value “1”, the logic value of the control signals CTRL 1  and CTRL 2  are “1” and “0”, respectively, so that the output voltage DOUT is driven to the low voltage level VOL=Vterm−(I 1 +I 2 )*Rterm due to the turned-on state of the first and second drivers DRV 1  and DRV 2 . However, the voltage swing of the output data DOUT is VOH=Vterm−A and VOL=Vterm−(I 1 +I 2 )*Rterm+A due to the channel attenuation A. 
     A Second Case—The Output Data DOUT Transitions from Two Successive High Voltage Level Data to a Low Voltage Level Data 
     As indicated under type II in FIG. 5, in the embodiment of FIG. 4, the output data DOUT transitions from two successive high voltage level data to a low voltage level data when the logic value of the input data DIN transitions from two successive “0”s to a “1” (i.e., transitions from two successive low voltage level data to high voltage level data). When the logic values of the input data DIN are two successive “0”s, the output signals D 1  and D 2  of the latch circuit  430  are logic value “0”s. Referring to the dashed circle  560  in FIG. 5, the high voltage level of the output data DOUT for the second bit of the two successive “0”s is VOL=Vterm−A+Δ1 due to the decrease in the channel attenuation from A to A−Δ1. 
     When the output signals D 1  and D 2  of latch circuit  430  are both “0”s, the logic value of the NOR gate  451  is “1” so that the logic value (or voltage level) of the second control signal CTRL 2  is determined by the logic value of the input data DIN. For example, when the logic value of the input data DIN is “1”, the logic value of the second control signal CTRL 2  is “1”, and when the logic value of the input data DIN is “0”, the logic value of the second control signal CTRL 2  is “0”. Accordingly, a transition from two success “0”s to a “1” in the input data DIN causes the second control signal CTRL 2  to achieve a high voltage level. 
     When the output signals D 1  and D 2  of latch circuit  430  are “0”s, the logic value of the NAND gate  441  is “1” so that the logic value of the first control signal CTRL 1  is determined by the logic value of the input data DIN. For example, when the logic value of the input data DIN is “1”, the logic value of the first control signal CTRL 1  is “1” and when the logic value of the input data DIN is “0”, the logic value of the first control signal CTRL 1  is “0”. 
     Accordingly, as shown in FIG. 5, when the input data DIN transitions from two successive “0”s to “1”, the first control signal CTRL 1  and the second control signal CTRL 2  are at a high voltage level (e.g., logic value “1”) so that the first, second and third drivers DRV 1 , DRV 2  and DRV 3  are in the turned-on state and drive the total current of I 1 +I 2 +I 3 . The output voltage at the output node NOUT is Vterm−(I 1 +I 2 +I 3 )*Rterm due to the total current of I 1 +I 2 +I 3 . 
     Referring to the dashed circle  560  in FIG. 5, when the output data DOUT is at a high voltage level for two successive data and then transitions to low voltage level, the first, second and third drivers DRV 1 , DRV 2  and DRV 3  are turned on so that the slope of the transition increases from  520  (slope when in Type  1  of FIG. 5) to  530 . As a result, the output data DOUT reaches approximately VOL within the bit time, and skew in the transition time is mitigated. 
     Namely, having the additional third driver DRV 3  turn on compensates for the output voltage variation Δ1  510  in the output data DOUT due to the ISI so that the output data DOUT swings from VOH=Vterm−A+Δ1 to VOL=Vterm−(I 1 +I 2 ) when the output data DOUT is at a high voltage level for two successive data and then transitions to a low voltage level (e.g., detected when the input data DIN transitions from two successive logic “0”s to “1”). 
     A Third Case—The Output Data DOUT Includes Two Successive Low Voltage Level Data 
     As indicated as Type III of FIG. 5 in the embodiment of FIG. 4, the output data DOUT includes two successive low voltage level data when the logic value of the input data DIN includes two successive logic “1”s (i.e., includes two successive high voltage level data). When the logic values of the input data DIN are two successive logic “1”s, the output signals D 1  and D 2  of the latch circuit  430  become logic value “1”s. Referring to the dashed circle  550  in FIG. 5, the voltage level of the output data DOUT for the second bit of the two successive “1”s is VOL=Vterm−(I 1 +I 2 )*Rterm+A−Δ1 due to the decrease of the channel attenuation from A to A−Δ1. 
     When the output signals D 1  and D 2  of latch circuit  430  are “1”s, the logic value of the NOR gate  451  is “0” so that the logic value of the second control signal CTRL 2  is “0” regardless of the logic value of the input data DIN. Also, the logic value of the NAND gate  441  is “0” so that the logic value of the first control signal CTRL 1  is “0” regardless of the logic value of the input data DIN. 
     As a result, prior to the next output data DOUT following the two successive low voltage level output data, the logic value of the first control signal CTRL 1  changes to “0” so that the second driver DRV 2  is placed in the turned-off state. The total pull-down current reduces from I 1 +I 2  to I 1 . As shown in the dashed circle  550  in FIG. 5, the voltage level of the output data DOUT increases from Vterm−(I 1 +I 2 )*Rterm+A−Δ1 to Verm−I 1 *Rterm+A−Δ1 due to the decreased pull-down current. In an exemplary embodiment of the present invention, the second channel width size is selected such that the increase in the output data voltage level is equal to Δ1. 
     Consequently, if the next output data DOUT is a high voltage level data as shown in FIG. 5, the first driver DRV 1  becomes placed in the turned-off state because the input data DIN transitions from logic value “1” to “0”. This drives the output voltage of the output data DOUT to Vterm from Vterm−I 1 *Rterm. Because the transition to a high voltage level begins from the elevated low voltage level, the detrimental impact of ISI is mitigated. 
     Another NMOS Embodiment 
     FIG.6 illustrates a circuit diagram of another embodiment of an NMOS open drain type output buffer system according to the present invention. In this embodiment, a low voltage level as an input voltage DIN represents a logic “0”, a high voltage level as an input voltage DIN represents a logic “1”, a low voltage level as an output data DOUT represents a logic “1”, and a high voltage level as an output data DOUT represents a logic “0”. A low voltage level means a voltage low enough to turn off an NMOS transistor, and a high voltage level means a voltage high enough to turn on an NMOS transistor. 
     As shown in FIG. 6, the NMOS open drain type output buffer system includes an NMOS open drain type output buffer  600  having an output pad POUT. The output pad POUT is connected via an output node NOUT and a channel  460  to a power supply Vterm (called a termination power) via a termination resistor Rterm. The channel  460  represents, for example, a bus or a portion of a bus, over which a device including the open drain type output buffer  600  and other devices (not shown) communicate. 
     The NMOS open drain type output buffer  600  includes the output pad POUT, a driver circuit  610 , and a control circuit  620 . The output node NOUT is anywhere on the channel  460 . The voltage of the output node NOUT is that of the output pad POUT. 
     The control circuit  620  includes a first determining control circuit  440 , a second determining control circuit  450 , a third determining control circuit  660 , a fourth determining control circuit  670  and a latch circuit  630 . The control circuit  620  receives input data DIN per clock edge of a clock CLK and generates a first control signal CTRL 1 , a second control signal CTRL 2 , a third control signal CTRL 3  and a fourth control signal CTRL 4  to partially control operation of the driver circuit  610 . 
     The latch circuit  630  includes a first latch  631 , a second latch  632  and a third latch  633 . These latches  631 ,  632  and  633  are D-type edge-triggered flip-flops and latch their input D per clock edge of the clock CLK. The first latch  631  latches the input data DIN per the clock edge of clock CLK and outputs a first output signal D 1 . The second latch  632  latches the first output signal D 1  per clock edge of the clock CLK and outputs a second output signal D 2 . The third latch  633  latches the second output signal D 2  per clock edge of the clock CLK and outputs a third output signal D 3 . Accordingly, with respect to a current input data DIN, the first, second and third output signals D 1 , D 2  and D 3  represent the three previous input data DIN. 
     The operation and structure of the first and second determining control circuits  440  and  450  are the same as that described above with respect to FIG.  4 . Therefore a description of these circuits will not be repeated for the sake of brevity. 
     The third determining control circuit  660  includes a NAND gate  661  and an AND gate  663 . The input signals of the NAND gate  661  are the first, second and third output signals D 1 , D 2  and D 3  of the latch circuit  630 . The AND gate  663  receives the output of the NAND gate  661  and the input data DIN, and generates the third control signal CTRL 3 . 
     The third determining control circuit  660  generates the third control signal CTRL 3  of low voltage level when the first, second and third output signals D 1 , D 2  and D 3  are logic “1” (high voltage levels in this embodiment), irrespective of the logic value of the input data DIN. When any of the logic values of the first, second and third output signals D 1 , D 2  and D 3  is a logic “0” (low voltage level in this embodiment), the voltage level of the third control signal CTRL 3  is based on the logic value of the input data DIN. Namely, if the input data DIN has logic value “0”, then the third control signal CTRL 3  is a low voltage, and if the input data DIN has logic value “1”, then the third control signal CTRL 3  is a high voltage. 
     The fourth determining control circuit  670  includes a NOR gate  671  and an AND gate  673 . The input signals of the NOR gate  671  are the first, second and third output signals D 1 , D 2  and D 3  of the latch circuit  630 . The AND gate  673  receives the output of the NOR gate  671  and the input data DIN, and generates the fourth control signal CTRL 4 . 
     The fourth determining control circuit  670  generates the fourth control signal CTRL 4  of high voltage level when the first, second and third output signals D 1 , D 2  and D 3  are logic value “0”s and the logic value of the input data DIN is “1”. When the logic value of the first, second and third output signals D 1 , D 2  and D 3  are not all logic value “0”s or the logic value of input data DIN is not “1”, the fourth control signal CTRL 4  is a low voltage. 
     The driver circuit  610  includes the first driver DRV 1 , the second driver DRV 2 , the third driver DRV 3 , a fourth driver DRV 4  and a fifth driver DR 5 . The drivers DRV 1 -DRV 5  are connected between the output node NOUT and the ground power VSS in parallel. The drivers DRV 1 -DRV 5  control the voltage level of the output node NOUT according to the input data DIN and the first-fourth control signals CTRL 1 -CTRL 4 . 
     The first driver DRV 1  is an NMOS transistor having a first gate width size. The source and drain of the NMOS transistor are coupled to the ground power VSS and the output node NOUT, respectively. The gate of the NMOS transistor for the first driver DRV 1  is coupled to the input data DIN via an AND gate  415 . The AND gate  415  ANDs the input data DIN with a power supply voltage VCC Accordingly, when the device including the open drain type output buffer is off, the first driver DRV 1  is off. More particularly, however, the AND gate  415  serves as a delay so that the input data DIN reaching the gate of the first driver DRV 1  is offset from the first-fourth control signals CTR 1 -CTRL 4  reaching the second-fifth drivers DRV 2 -DRV 5 , respectively. 
     When the logic value of the input data DIN is “1”, the first driver DRV 1  drives a first pull-down current I 1  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is VOL=Vterm−I 1 *Rterm. 
     The second and fourth drivers DRV 2  and DRV 4  are NMOS transistors having second and fourth gate width sizes, respectively. The second and fourth gate width sizes are less than the first gate width size. The source, drain and gate of the NMOS transistor for the second driver DRV 2  are coupled to the ground power VSS, the output node NOUT and the output of the first determining control circuit  440 , respectively. The source, drain and gate of the NMOS transistor for the fourth driver DRV 4  are coupled to the ground power VSS, the output node NOUT and the output of the third determining control circuit  660 , respectively. 
     As stated previously with respect to the embodiment of FIG. 4, when the logic value of the first control signal CTRL 1  is “1”, the second driver DRV 2  drives a second pull-down current I 2  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is VOL=Vterm−I 2 *Rterm. Similarly, when the logic value of the third control signal CTRL 3  is “1”, the fourth driver DRV 4  drives a fourth pull-down current I 4  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is VOL=Vterm−I 4 *Rterm. 
     Accordingly, when the first, second and fourth drivers DRV 1 , DRV 2  and DRV 4  are turned on, the level of the output voltage DOUT becomes VOL=Vterm−I 1 *Rterm−I 2 *Rterm−I 4 *Rterm. In one exemplary embodiment of the present invention, the first, second and fourth gate width sizes are established such that the data output DOUT voltage achieved when the first, second and fourth drivers DRV 1 , DRV 2  and DRV 4  are turned on is substantially equal to the low voltage VOL of the output data in the prior art open drain type output buffer of FIG.  1 ( a ). As will be appreciated from the description in this application, the gate width sizes chosen for the first, second and fourth drivers DRV 1 , DRV 2  and DRV 4  are design parameters established based on the application of the open drain type output buffer. As described above with respect to FIG.  4 . an exemplary second driver DRV 2 , in transitioning from a turned-on to a turned-off state compensates for additional attenuation caused by ISI when two successive low voltage output data DOUT are generated. Likewise, an exemplary embodiment of the fourth driver DRV 4 , in transitioning from a turned-on state to a turned-off state compensates for the further additional attenuation caused by ISI when three successive low voltage output data DOUT are generated. 
     The third and fifth drivers DRV 3  and DRV 5  are NMOS transistors having third and fifth gate width sizes, which are less than the first gate width size. The source, drain and gate of the NMOS transistor in the third driver DRVS are coupled to the ground power VSS, the output node NOUT and the output of the second determining control circuit  450 , respectively. The source, drain and gate of the NMOS transistor in the fifth driver DRV 5  are coupled to the ground power VSS, the output node NOUT and the output of the fourth determining control circuit  670 , respectively. When the logic value of the second control signal CTRL 2  is a high voltage, the third driver DRV 3  drives a third pull-down current I 3  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is Vterm−I 3 *Rterm. When the logic value of the fourth control signal CTRL 4  is a high voltage, the fifth driver DRV 5  drives a fifth pull-down current I 5  from the output node NOUT to the ground power VSS. The level of the output voltage DOUT generated by this pull down operation is Vterm−I 5 *Rterm. 
     Exemplary operation of the open drain output buffer according to the present invention will be readily understood from the previous discussion of the embodiment of FIG. 4 with respect to FIG.  5 . Namely, the second and third drivers DRV 2  and DRV 3  are controlled by the first and second determining control circuits  440  and  450  in the same manner as discussed above with respect to the embodiment of FIG.  4 . The fourth driver DRV 4  is controlled by the third determining control circuit  660  in the same manner that the first determining control circuit  440  controls the second driver DRV 2 , except that the control is based upon the output data DOUR having been at a low voltage level for three successive output data (i.e., three successive “1”s in the input data DIN). Similarly, the fifth driver DRV 5  is controlled by the fourth determining control circuit  670  in the same manner that the second determining control circuit  450  controls the third driver DRV 3 . except that the control is based on the output data DOUT transitioning from three high voltage level data to a low voltage level data (i.e., transitioning from three successive “0”s to a “1” in the input data DIN). 
     The invention being thus described, it will be obvious that the same may be varied in many ways. For example, PMOS embodiments of the present invention will be readily understood from the forgoing disclosure. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the present invention.