Abstract:
A comparator circuit is described and contains a comparator, which is provided with an operating point. A monitoring circuit suppresses undesired signal bouncing at the output. The bouncing is produced by interferences of the input signal. The monitoring circuit ensures that the circuit output is locked from being switched back to another logical level after switching until the input signal has reached a second threshold value that is higher than the operating point.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
         [0001]    This application is a continuation of copending International Application No. PCT/DE00/00306, filed Feb. 1, 2000, which designated the United States.  
         BACKGROUND OF THE INVENTION  
       FIELD OF THE INVENTION  
         [0002]    The invention relates to a comparator circuit. Comparators are used in order to map an input variable, for example an input voltage, onto a logic state. If the input voltage is below the threshold value of the comparator, then the output voltage from the comparator is at the first logic level, for example low (L), and if the input voltage is above the threshold value, then the output voltage is at the second logic level, for example high (H).  
           [0003]    A quality criterion for comparators is the accuracy with which a specific, defined switching threshold is carried out. In a sensor system, or else in comparators, which are used in peripheral circuit parts, one problem, which often arises is that the input signal of the comparator is subject to interference or noise. This leads to the comparator switching backward and forward in a rapid sequence between the logic levels L and H. The signal bouncing is undesirable. Bouncing must be avoided, particularly when the aim, for example, is to count events or to generate a clock on the basis of an external signal.  
           [0004]    One known remedial measure is to provide the comparator with hysteresis. In this case, the threshold above which the input signal must rise is higher for switching from L to H than for switching back from H to L. If the interval between the switching thresholds is made greater than the amplitude of the interference to be expected, then unambiguous signal evaluation is feasible. However, the interference immunity is gained at the expense of switching threshold accuracy, since it is split between two values. If the switching thresholds are chosen such that the upper and the lower value are each symmetrical with respect to the actually desired switching threshold, then this admittedly results in the minimum discrepancies overall, but there is now no longer any switching threshold precisely where it actually should be. This is irrelevant if one just wishes to count events. However, if accurate position or time determination is also intended to be carried out, for example in the sensor system, this response has a disturbing effect. For example, for sensors, which have to evaluate an approximately sinusoidal signal, for example gear wheel sensors, it is advantageous for reasons of accuracy to switch at the signal zero crossing, while one would have to switch in the vicinity of the signal peak, for interference immunity reasons.  
         SUMMARY OF THE INVENTION  
         [0005]    It is accordingly an object of the invention to provide a comparator circuit that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has an accurate, largely hysteresis-free switching threshold, but which also offers interference immunity, by which disturbing bouncing is avoided.  
           [0006]    With the foregoing and other objects in view there is provided, in accordance with the invention, a comparator circuit. The comparator circuit contains an input for receiving an input signal, an output terminal outputting an output signal, and a first comparator connected to the input and receiving the input signal. When the input signal exceeds a threshold value T 1 , the first comparator generates a first output signal switching from a first logic signal to a second logic signal, in which case a switching of the output signal from the first logic signal to the second logic signal can be initiated only by the first comparator switching from the first logic signal to the second logic signal. A monitoring circuit is connected between the input and the output terminal. The monitoring circuit contains a second comparator connected to the input and has a switching hysteresis with a switching-on threshold T 2  and a switching-off threshold T 3 , where T 2 &gt;T 3 . The second comparator and the first comparator each have an output. An output circuit and a logic circuit are provided. The logic circuit is connected to the output circuit, to the output of the first comparator, and to the output of the second comparator. The logic circuit links the output of the first comparator and the second comparator to the output circuit in such a manner that, when the input signal exceeds the threshold value T 1 , the output circuit emits the second logic signal and then remains inhibited against returning to the first logic signal until the input signal has once again fallen below the threshold value T 1  after exceeding the switching-on threshold value T 2 . A reset circuit is connected to the output circuit and the logic circuit. The reset circuit is able to reset the output circuit to a quiescent state irrespective of a state of the first comparator and the second comparator, and in the quiescent state the output signal at the output terminal is at the first logic signal, and the output circuit maintains its present state until the first comparator and the second comparator output signals are the first logic signal.  
           [0007]    According to the invention, the undesirable bouncing is avoided in that, after switching from the first to the second logic level, the circuit output remains inhibited against switching back until the input signal has reached a second threshold value, which is higher than the switching threshold of the first comparator. The switching threshold of the circuit output is governed by the switching threshold of the comparator, but the switching times are dependent on whether and when the input signal reaches the second threshold value.  
           [0008]    According to one refinement of the invention, the monitoring circuit contains a further comparator, which has hysteresis and whose input is connected to the circuit input, and a logic circuit. The monitoring circuit is configured such that the comparator can emit a signal only when the input signal supplied to it is sufficiently large to switch the further comparator that has hysteresis, as well. If the input signal is too low, the output signal is not switched. Although the comparator does not act directly on the output itself, it must, however, enable the circuit to allow the comparator to switch back again and to produce a new output flank.  
           [0009]    In one particularly advantageous refinement of the invention, a reset circuit is provided, by which the comparator circuit can be switched to a defined initial state, which is independent of the switching states of the comparators when the reset signal is present. The purpose of the reset circuit is that the very first switching (the very first output flank or edge) of the comparator is not defined by a reset event or by the reset end, but occurs precisely at the time at which the input signal would lead to switching of the comparator. The reset signal changes the output signal from the comparator circuit to the reset state, and locks the comparator output circuit. Enabling does not take place until the time when the internal comparator output matches the reset state, which is present at the output. This ensures that the next output flank at the output of the comparator circuit is also related to switching of the comparator.  
           [0010]    A further advantage of the reset circuit is that a defined output situation is reached, in which, for example, the output signals from the comparators assume the level; this has an advantageous effect on the power consumption of the circuit.  
           [0011]    In accordance with an added feature of the invention, the output circuit is a flip-flop with a set input, a reset input and an output being the output terminal.  
           [0012]    In accordance with an additional feature of the invention, the logic circuit has a first AND gate, a second AND gate, a first NOT gate with an output, and a second NOT gate with an output. The first AND gate has a first input connected to the output of the first comparator and a second input connected to the output of the second NOT gate. The second NOT gate has an input connected to the output of the second comparator. The second AND gate has a first input connected to the output of the first NOT gate and a second input connected to the output of the second comparator. The first NOT gate has an input connected to the output of the first comparator.  
           [0013]    In accordance with a further feature of the invention, the flip-flop includes a first NOR gate having an output and inputs and a second NOR gate having an output and inputs. The output of the first NOR gate is connected to one of the inputs of the second NOR gate, and the output of the second NOR gate connected to one of the inputs of the first NOR gate.  
           [0014]    In accordance with another feature of the invention, the reset circuit includes a third NOT gate having an input and an output; an input connection connected to the input of the third NOT gate; and a third AND gate having a first input connected to the output of the second NOR gate of the flip-flop, a second input connected to the output of the third NOT gate, and an output connected to one of the inputs of the first NOR gate of the flip-flop. A further flip-flop is provided and has a set input, a reset input connected to the input connection for receiving a reset signal, and an output connected to a third input of the first AND gate and to a third input of the second AND gate. An exclusive-OR gate is provided and has an output connected to the set input of the further flip-flop, a first input connected to the output of the first NOT gate and to the second input of the second AND gate, and a second input connected to the output of the third AND gate.  
           [0015]    In accordance with a further added feature of the invention, the threshold value T 1 , the switch-on threshold T 2  and the switch-off threshold T 3  are chosen such that T 3 &lt;T 1 &lt;T 2 .  
           [0016]    In accordance with a concomitant feature of the invention, the first logic signal is low (logic 0), and the second logic signal is high (logic 1).  
           [0017]    Other features which are considered as characteristic for the invention are set forth in the appended claims.  
           [0018]    Although the invention is illustrated and described herein as embodied in a comparator circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
       
    
    
       [0019]    The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    [0020]FIG. 1 is a circuit diagram of a first embodiment of a comparator circuit according to the invention;  
         [0021]    [0021]FIG. 2 is a timing diagram of an input signal and of switching processes initiated by the input signal; and  
         [0022]    [0022]FIG. 3 is a circuit diagram of a second embodiment, in which the comparator circuit is provided with a reset circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case. Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a first exemplary embodiment of the invention. An input is connected to inputs of two comparators K 1 , K 2  and receives an input signal E. The comparator K 1  essentially has no hysteresis, and it switches from L to H when the input signal E exceeds a threshold T 1  (see FIG. 2). The comparator K 2  has hysteresis. The comparator K 2  switches from L to H when the input signal E exceeds a threshold T 2 , and from H to L when the input signal E falls below T 3 . The output signals from the comparators K 1 , K 2  are supplied to a logic circuit LS, which itself has two outputs which are supplied to an output circuit F 1 . The output circuit F 1  is a flip-flop containing two NOR gates N 1 , N 2 , and whose signal level at an output A is L in the quiescent state. The logic circuit LS has two AND gates U 1 , U 2 . An output of the first AND gate U 1  is connected to a set input S 1  of the flip-flop F 1 , and an output of the second AND gate U 2  is connected to a reset input R 1  of the flip-flop F 1 . The output of the comparator K 1  is connected to a first input of the AND gate U 1 , and, via a first NOT (inverter) gate I 1 , to the first input of the AND gate U 2 . The output of the comparator K 2  is connected to the second input of a second AND gate U 2 , and via a second NOT (inverter) gate I 2  to the second input of the first AND gate U 1 .  
         [0024]    The initial state of the circuit is assumed to be defined by the input signal being E=0. In this case, the output signal from the comparators K 1  and K 2  is in each case L. The signal L is thus present at the first input of the AND gate U 1  and, as a consequence of the inversion by the NOT gate I 2 , the signal H is present at its second input. As a consequence of the inversion by the NOT gate I 1 , a value H is present at the first input of the second AND gate U 2 , and the output signal from the comparator K 2 , which assumes the value L, is present at the second input. In consequence, the signal L is present both at the set input S 1  of the flip-flop F 1  and at its reset input R 1 , and the output signal A from the flip-flop F 1  is likewise L.  
         [0025]    [0025]FIG. 2 shows the profile of the input signal E, schematically. In the diagram, the line T 1  denotes the switching threshold of the comparator K 1 , the line T 2  the switching-on threshold and T 3  the switching-off threshold of the comparator K 2 .  
         [0026]    As shown in FIG. 2, the input signal E rises from the value 0 to the threshold value T 1  of the comparator K 1 , which it reaches at a time t 1 . The output signal from K 1  thus becomes H at the time t 1 . In consequence, the signal H is present at both inputs of the AND gate U 1  at the time t 1 , and the output signal from U 1  likewise changes to H. Since the output signal from the AND gate U 1  is supplied to the set input S 1  of the flip-flop F 1 , the flip-flop F 1  is set, and its output assumes the value H at the time t 1 . Since the input signal E is still below the switching-on threshold T 2  of the comparator K 2 , its output signal remains at L at the time t 1 .  
         [0027]    The signal E rises further and reaches the switching-on threshold value T 2  of the comparator K 2  at a time t 2 . The output of the comparator K 2  thus switches to H. As a consequence of the inversion by the NOT gate I 2 , the second input of the first AND gate U 1  thus changes to L, so that the output signal from the AND gate U 1  likewise falls to L. The output signal H from the comparator K 1  is inverted by the NOT gate I 1 , so that the signal L is present at the first input of the AND gate U 2 . In consequence, the output signal from the second AND gate remains at L, and the output signal from the flip-flop F 1  remains unchanged at the value H.  
         [0028]    At a time t 3 , the input signal E falls below the threshold value T 2 . Since, owing to its hysteresis, the output of the comparator K 2  does not fall back to L until the input signal E falls below the lower threshold value T 3 , nothing changes in the switching states of the comparators K 1 , K 2  at the time t 3 , and the output A of the flip-flop F 1  remains at H.  
         [0029]    The input signal E falls below the threshold value T 1  of the comparator K 1  at a time t 4 , and its output signal changes back to L. However, the output signal from the comparator K 2  remains at H, since the input signal E has not yet fallen below the threshold value T 3 . In consequence, the signal L is present at each of the inputs of the first AND gate U 1 , and the signal H is present at each of the two inputs of the second AND gate U 2 . The output signal from the AND gate U 2  is thus reset to H at the time t 4 , and the flip-flop F 1  is reset such that its output changes back from H to L. The input signal E once again reaches the threshold value T 1  of the comparator K 1  at the time t 5 , so that its output signal changes to H. The inversion by the first NOT gate I 1  results in the first input of the second AND gate U 2  being set to the value L. The output of the second AND gate U 2  thus likewise remains at L. Since the inversion of the output signal from the comparator K 2  by the NOT gate I 2  also results in the second input of the first AND gate U 1  being at L, the signal level which is present at the set input S 1  is also L. The flip-flop F 1  is thus locked in the state, which it assumed at the time t 4 , and its output signal remains L. At a time t 6 , the input signal E once again falls below the level T 1 , so that the output signal from the comparator K 1  becomes L once again. The signal L is thus present at both inputs of the first AND gate U 1 , and its output is likewise L. The inversion by the NOT gate I 1  then results in the value H being present at both inputs of the second AND gate U 2 , so that the signal H appears at the output of the second AND gate U 2 , and the flip-flop F 1  is reset. However, since its output had previously assumed the level L, the output signal A remains unchanged. The input signal E falls below the switching-off threshold value T 3  of the comparator K 2  at a time t 7 . The output signal from the comparator K 2  thus changes back to L. In this state, both comparators K 1 , K 2  produce the output signal L and, in consequence, the output signals from the two AND gates U 1  and U 2  are both L. The output of the flip-flop F 1  thus remains unchanged at L. At a time t 8 , the input signal E once again reaches the switching-off threshold value T 1  of the comparator K 2 . However, since this does not switch from L to H at T 3 , but not until T 2 , and the input signal likewise results in the comparator K 1  output being L, no change in the switching state occurs at time t 8 . The input signal E once again reaches the switching-on threshold T 1  of the comparator K 1  at a time t 9 , and its output signal in consequence changes from L to H. At this time, the output signal from the comparator K 2  is L. This is inverted by the second NOT gate I 2 , so that the signal H is present at both inputs of the first AND gate U 1  at the time t 9 . The output signal from the AND gate U 1  thus changes to H at the time t 9 , which results in the flip-flop F 1  being set, and its output A changing from L to H. The input signal E once again falls below the threshold value T 1  of the comparator K 1  at the time t 10 , so that its output signal changes from H to L. In consequence, the output of the first AND gate U 1  falls from H to L. The inversion of the output signal from the comparator K 1  by the NOT gate I 1  results in the signal H being present at the first input of the second AND gate U 2 , and the output signal from the comparator K 2 , which is L, being present at the second input. The output signal from the AND gate U 2  is thus L, and the state of the flip-flop F 1  remains unchanged at the value H. The input signal E once again reaches the switching threshold T 1  of the first comparator K 1  at the time t 11 , and its output signal thus becomes H. Since the output signal from the comparator K 2  continues to remain at L, the output signal from the first AND gate U 1  becomes H, and the output signal from the second AND gate U 2  remains at L. The flip-flop F 1  is thus set. However, since the output signal had already assumed the value H at t 9 , the output level of the flip-flop F 1  remains unchanged.  
         [0030]    The switching processes which take place at the times t 12  to t 17  correspond to those at the times t 2  to t 7  and therefore do not need to be explained once again.  
         [0031]    It can be seen from the illustration in FIG. 2 that the flip-flop F 1  is set when the threshold value T 1  of the comparator K 1  is exceeded, and is not reset until the higher, upper threshold value T 2  has been exceeded by the comparator K 2  with hysteresis. If the threshold value T 2  is not reached, the output of the comparator K 2  never reaches the value H and, in consequence, the reset input R 1  of the flip-flop F 1  cannot assume the value H required for resetting.  
         [0032]    [0032]FIG. 3 shows a further exemplary embodiment of the comparator circuit according to the invention, in which a reset circuit RS is provided. The reset circuit RS contains a third AND gate U 3 , whose first input is connected to the output of the second NOR gate N 2  in the flip-flop F 1 . However, in contrast to FIG. 1, the second input of the first NOR gate N 1  is no longer directly connected to the output of the second NOR gate N 2 , but to the output of the third AND gate U 3 . The second input of the third AND gate U 3  is connected via a third NOT gate I 3  to a reset input connection C. When the signal L is present at the reset input connection C, then the inversion by the NOT gate I 3  results in the input signal at the second input of the AND gate U 3  assuming the value H. In this situation, the output signal A depends only on whether the second NOR gate N 2  in the flip-flop F 1  is producing the value H or L at its output. Therefore, when the reset input C is at L, the flip-flop F 1 , to which the third AND gate U 3  has been added, operates in precisely the same way as the flip-flop F 1  in FIG. 1. If the signal H is applied to the reset input C, the input signal at the second input of U 3  becomes L and, in consequence, the output A of the circuit is changed to L.  
         [0033]    The reset input connection C is also connected to the reset input R 2  of a second flip-flop F 2 , which contains NOR gates N 3 , N 4 .  
         [0034]    The AND gates U 1 , U 2  each have three inputs. The first two inputs are connected in precisely the same way as in the exemplary embodiment shown in FIG. 1. The third inputs are both connected to the output A 2  of the second flip-flop F 2 . A set input S 2  of the flip-flop F 2  is connected to an output of an exclusive-OR gate X. One input of the exclusive-OR gate is connected to the output of the NOT gate I 1 , and to the first input of the second AND gate U 2 . The other input of the exclusive-OR gate X is connected to the output A of the circuit.  
         [0035]    In order to describe the method of operation of the reset circuit, the following text assumes the situation in which the output signal from the comparator K 1  is H, and the output signal from the comparator K 2  is L. This would correspond, for example, to the interval between t 9  and t 10  in FIG. 2.  
         [0036]    If the signal H is applied to the reset input connection C in this situation, the output A is reset to the signal L. The signal H is present at the reset input of the flip-flop F 2 . The output signal from the comparator K 1 , inverted by I 1 , that is to say the signal L, is present at the first input of the exclusive-OR gate X. The signal L is likewise present at the second input of the exclusive-OR gate X. In consequence, the output signal from the exclusive-OR gate X is likewise L. This results in the flip-flop F 2  being set to the basic state. The output A 2  of the flip-flop F 2  becomes L. In consequence, the AND gates U 1  and U 2  each block the output signals from the comparators K 1 , K 2 .  
         [0037]    If the reset signal now becomes L, then the output A remains at the value L, and the flip-flop F 1  remains in the initial state. The flip-flop F 2  does not change its state either, and its output A 2  remains at L. Thus, as before, the AND gates U 1  and U 2  block the output signals from the comparators K 1 , K 2 .  
         [0038]    If the output signal from the comparator K 1  then assumes the value L owing to a change in the input signal, that is to say the situation, which corresponds to the initial state, then one input of the exclusive-OR gate X becomes H, and the other remains at L. In a corresponding way, the output signal from the exclusive-OR gate X assumes the value H, so that H is applied to the set input of the flip-flop F 2 . The flip-flop F 2  is thus set, that is to say its output becomes H. In consequence, the two third inputs of the AND gates U 1 , U 2  are each set to H, so that the blocking of the signals from the comparators K 1 , K 2 , which was previously carried out by the reset circuit, is cancelled once again.  
         [0039]    The exemplary embodiments described above can also be implemented using inverted logic, in which the logic signals L and H are interchanged with one another.