Abstract:
An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level. A control circuit is responsive to the output of the control circuit to control the voltage at the gates of the second pull-up transistor and the second pull-down transistor to provide the logic level at the output node only when the output of the control circuit indicates when the supply voltage is below the predetermined level.

Description:
TECHNICAL FIELD OF THE INVENTION  
       [0001]     The present invention relates to integrated circuits, and more particularly relates to general purpose output buffers.  
       BACKGROUND OF THE INVENTION  
       [0002]     In an integrated circuit chip, signals are transferred out of the circuit by output buffers, configured as part of the integrated circuit on the chip. General purpose output buffers generally perform relatively standard functions that are useful on all outputs, such as isolation of the integrated circuit from the load it is driving and the provision of sufficient power in the driving of the output signal to maintain circuit performance, even when the load includes significant capacitance. In other words, for circuits driving loads with a high capacitance, such as a system bus, for example, the general purpose output buffer is intended to provide sufficient power to charge up that capacitance quickly enough to effectively deliver the output signal to the load within a short enough time interval considered acceptable for the integrated circuit&#39;s intended function.  
         [0003]     The design of general purpose output buffers for a given integrated circuit is typically optimized for a single supply voltage, for example V CC =3.3 V. This is because the entire integrated circuit is generally intended to run at a given supply voltage. However, the supply voltage for a given integrated circuit may not be the same from chip to chip, because of variations in the manufacturing process for the chip. Unfortunately, the circuit performance tends to depend upon the supply voltage, so that chips having higher supply voltages perform better than necessary, while chips having lower supply voltages perform more poorly than desired. The problem may be addressed by designing the output buffer with larger transistor devices, ensuring adequate performance at supply voltages at the lowest end of the expected range of variation of the supply voltage. However, for chips having a supply voltage at higher supply voltages their output buffers will draw excessive current because of the larger transistor devices, and therefore may dissipate excessive power.  
       SUMMARY OF THE INVENTION  
       [0004]     It would therefore be desirable to have a general purpose output buffer that provides improved performance that is maintained, even when the supply voltage is at the low end of its range of variation. The present invention provides such an output buffer. It has a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level. A control circuit is responsive to the output of the control circuit to control the voltage at the gates of the second pull-up transistor and the second pull-down transistor to provide the logic level at the output node only when the output of the control circuit indicates when the supply voltage is below the predetermined level.  
         [0005]     These and other aspects and features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  is a circuit diagram of a typical prior art general purpose output buffer.  
         [0007]      FIG. 2  is a circuit diagram of an embodiment of a general purpose output buffer according to the present invention.  
         [0008]      FIG. 3  is a circuit diagram of a supply voltage control circuit for the circuit of  FIG. 2 , according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0009]      FIG. 1  is a circuit diagram of a typical prior art general purpose output buffer. An enable signal EN and an input signal IN are provided as inputs, and an output signal OUT is provided as an output. An NMOS driver transistor T 1  and a PMOS driver transistor T 2  are connected in series between a power supply having a voltage V CC  and ground, as shown. A NOR gate  1 , a NAND gate  2  and an inverter  3  are interconnected as shown, and operate in conjunction with signal EN to provide an enable function for the circuit. When the circuit is enabled, a HIGH value of IN causes transistor T 2  to turn on and transistor T 1  to turn off, thus driving a HIGH value of OUT at the output. Conversely, when the circuit is enabled, a LOW value of IN causes transistor T 1  to turn on and transistor T 2  to turn off, thus driving a LOW value of OUT at the output.  
         [0010]     In a design of a general purpose output buffer like that of  FIG. 1  for a particular integrated circuit, depending on the supply voltage for the integrated circuit, the performance and power dissipation requirements for the output buffer, the size of transistors T 1  and T 2  is determined accordingly by the designer. For a given supply voltage, larger transistors provide increased (faster) performance at the cost of higher power dissipation, while, conversely, smaller transistors provide decreased (slower) performance with lower power dissipation. Higher or lower power supply voltage result in increased or decreased performance, respectively. Thus, to ensure at least a minimum performance, the size transistors T 1  and T 2  are designed to a sufficient size to ensure such performance, with the result that at higher supply voltages, increased power dissipation and unneeded speed are provided.  
         [0011]      FIG. 2  is a circuit diagram of an embodiment of a general purpose output buffer  20  according to the present invention. As in the buffer of  FIG. 1 , an enable signal EN and an input signal IN are provided as inputs, and an output signal OUT is provided as an output. An NMOS driver transistor T 3  and a PMOS driver transistor T 4  are connected in series between a power supply having a voltage V CC  and ground, as shown. However, these transistors are designed to be optimized in size for operation at the high end of the range of supply voltages. A NOR gate  21 , a NAND gate  22  and an inverter  23  are interconnected as shown, and operate in conjunction with signal EN to provide an enable function for the circuit. When the circuit is enabled, a HIGH value of IN causes transistor T 4  to turn on and transistor T 3  to turn off, thus driving a HIGH value of OUT at the output. Conversely, when the circuit is enabled, a LOW value of IN causes transistor T 3  to turn on and transistor T 4  to turn off, thus driving a LOW value of OUT at the output.  
         [0012]     In addition, however, are provided an additional pair of output transistors, an NMOS transistor T 5  and a PMOS transistor T 6  connected in series between a power supply having a voltage V CC  and ground, as shown. A NAND gate  25 , a NOR gate  24  and an inverter  26  are interconnected as shown and to a control unit  27 . The NAND gates, NOR gates and inverters of the circuit of  FIG. 2  are all of standard design.  
         [0013]     In operation, the control unit  27  provides an output signal of logic one as long as the supply voltage remains above a predetermined minimum that ensures adequate performance using only transistors T 3  and T 4 . In this mode, NOR gate  21 , NAND gate  22  and inverter  23  operate with transistors T 3  and T 4  in substantially the same way as NOR gate  1 , NAND gate  2  and inverter  3  operate with transistors T 1  and T 2  in  FIG. 1 ., while transistors T 5  and T 6  are held OFF.  
         [0014]     However, when the supply voltage drops below the aforementioned predetermined minimum, the control unit  27  provides an output signal of logic zero, which enables NAND gate  25 , NOR gate  24  and inverter  26  to operate with transistors T 5  and T 6  in substantially the same way as NAND gate  22 , NOR gate  21  and inverter  23  operate with transistors T 3  and T 4 , only with an inverted enabling signal. In this way, transistors T 5  and T 6  operate in parallel with transistors T 3  and T 4  to effectively increase the size of the output driver transistors in conditions of low power supply voltage.  
         [0015]     It was mentioned above that transistors T 3  and T 4  are designed to be optimized in size for operation at the high end of the range of supply voltages. This size will depend upon the supply voltage range and other circuit considerations, and are well within the purview of those of ordinary skill in the relevant art area. Similarly, the size of T 5  and T 6  are designed to be optimized in size for operation in parallel with transistors T 3  and T 4  at the low end of the range of supply voltages. Exemplary sizes for these transistors a width of 200 microns and a length of one micron for the PMOS transistors T 4  and T 6 , and a width of 100 microns and a length of one micron for the NMOS transistors T 3  and T 5 . As mentioned, however, these are merely exemplary sizes, and the actual size will depend upon the supply voltage range and other circuit considerations.  
         [0016]      FIG. 3  is a diagram of the control unit  27  of  FIG. 2 . It is designed to provide an output signal of logic one when the supply voltage V CC  is above a predetermined minimum, while providing a logic zero when the supply voltage drops below the predetermined minimum. In the particular embodiment shown in  FIG. 3 , that predetermined minimum is approximately 2.1 V. Operating in conjunction with the circuit of  FIG. 2 , the design of this embodiment is optimized for operation with a supply voltage that may vary between 3.3 V and 1.6 V, while limiting the degradation in performance experienced with prior art designs.  
         [0017]     In the circuit of  FIG. 3 , an inverter  31  provides the output signal for the control unit  27 . A relatively small PMOS transistor T 7 , having its source connected to V CC  and its gate connected to ground and its drain connected to the input of inverter  31 , provides weak pull-up to the input of inverter  31 . NMOS transistors T 8  and T 9  are connected in series between the input of inverter  31  and ground. Another relatively small PMOS transistor T 12 , having its source connected to V CC  and its gate connected to its source and its drain connected to the gate of transistor T 8 , provides weak pull-up to the gate of transistor T 8 . NMOS transistors T 10  and T 11  are connected in series between the gate of transistor T 8  and ground, with the gates of transistors T 10  and T 11  being connected together and to V CC . A further relatively small PMOS transistor T 15 , having its source connected to V CC  and its gate connected to its source and its drain connected to the gate of transistor T 9 , provides weak pull-up to the gate of transistor T 9 . NMOS transistors T 13  and T 14  are connected in series between the gate of transistor T 9  and ground, with the gates of transistors T 13  and T 14  being connected together and to V CC .  
         [0018]     The circuit of  FIG. 3  operates as follows. As mentioned above, transistor T 7  provides a weak pull-up to the input of inverter  31 . At supply voltages relatively low (i.e. threshold voltage of both NMOS &amp; PMOS), transistors T 10 , T 11 , and T 12  are OFF, thus no current exists to charge the gate of transistor T 8 , keeping transistor T 8  OFF. Similarly, transistors T 13 , T 14  and T 15  are OFF, thus keeping transistor T 9  OFF. T 12  will remain OFF until the supply voltage is high enough to turn T 11  and T 10  ON and pull T 11 &#39;s source and gate low, thus allowing transistor T 12  to operate in saturation region. T 13  and T 4  work similarly to transistors T 10  and T 11 , and transistors T 15  to T 12 , to control the turn-ON of transistor T 9 . Thus, the pull-down of transistors T 8  and T 9  controls the input of inverter  31 , and the output of the control unit  27 , i.e., of inverter  31 , is logic low when transistors T 8  and T 9  are OFF. As the supply voltage V CC  increases, the voltage at the gates of transistors T 10  and T 11  increases, as does the voltage at the gates of transistors T 1   3  and T 1   4 . When V CC  reaches the threshold voltage of both transistors T 10  and T 11 , they begin to turn ON, allowing transistor T 12  to start to turn ON transistor T 8 . The voltage at gate of T 8  will be a voltage divider between the ON resistance, Ro, of transistors T 10  &amp; T 11  combined and T 12 . In other words, 
 
 Vg 8=( Vcc*[Ro 10+ Ro 11]/[ Ro 11+ Ro 12+ Ro 12]). 
 
 where Vg 8  is the gate voltage of transistor T 8 , and RoN is the ON resistance of transistor TN. T 8  will turn ON once Vg 8  rises above the threshold voltage, Vt, of transistor T 8 , which is approximately 0.7 V. At this point, the drain of transistor T 8  is substantially at the threshold voltage of transistor T 8 . Also at this point, since substantially the same process has occurred with transistors T 13 , T 14  and T 15  as occurred with transistors T 10 , T 11  and T 12 , as described above, the gate of transistor T 9  will be just at the threshold voltage, relative to ground, of transistor T 9 . When the supply voltage reaches approximately 2.1 V, and the gate to both T 8  and T 9  is ˜0.8 V, both transistors T 8  and T 9  are strongly enough ON to overcome the weak pull-up of transistor T 7 , and the input of inverter  31  is pulled low, causing a logic one to appear at the output of control unit  27 . 
 
         [0019]     The circuit designer will recognize that the selection of the size of transistors T 7  through T 15  will determine the crossover point for the supply voltage for the output of control unit  27  to change state. Selection of these sizes is well within the scope of ordinary skill in this art area. Exemplary sizes of these transistors in a working embodiment having a crossover point of a supply voltage of 2.1 V, with units expressed in microns, are T 7  width=8, length=10; T 12  &amp; T 15  width=10, length=1; T 8  &amp; T 9  width=80, length=1; T 10  &amp; T 13  width=8, length=18; T 11  &amp; T 13  width=8, length=8. In other circuit technologies and for other crossover voltages these sizes will be different.  
         [0020]     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.