Abstract:
A control device for a switching converter has an input terminal and an output terminal; the converter includes a half-bridge of a first and a second transistor coupled between the input terminal and a reference voltage. The control device detects a signal on the output terminal of the converter, integrates the detected signal and imposes a predefined minimum frequency of the detected signal. The control device regulates the average value of the detected signal by comparison with a reference signal and drives the first and second transistors in during the regulation. The control device turns off an integrator when the predefined minimum frequency is imposed.

Description:
RELATED APPLICATION  
       [0001]     The present application claims priority of European Patent Application No. 05425725.8 filed Oct. 17, 2005, which is incorporated herein in its entirety by this reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention refers to a control device for a switching converter and relative switching converter, preferably a converter from direct voltage to direct voltage.  
       BACKGROUND OF THE INVENTION  
       [0003]     In the state of the art converters from direct voltage to direct voltage or DC-DC converters are generally known; a switching converter with controller in pulse frequency mode and with a constant turn-on time is shown in  FIG. 1 . The converter comprises a first MOS transistor HS having a non-drivable terminal coupled to an input voltage Vin and another non-drivable terminal coupled to a terminal of an inductance L and to a non-drivable terminal of another MOS transistor LS having the other non-drivable terminal coupled to ground GND. The inductance L has its other terminal coupled to a sense resistance Rsense in turn coupled to a filter  1  constituted by a resistance ESR in series to a capacitor Cout where the resistance ESR is the parasitic resistance of the capacitor Cout; the filter  1  is placed in parallel to the load LOAD. The converter comprises a control circuit  2  having in input on the terminals CSENSEPLUS and CSENSEMINUS the current detected at the terminals of the resistance Rsense, the output voltage Vout at the terminals of the load LOAD on the input terminal VFB, a reference voltage VREF and the clock pulses MIN_FREQ coming from a timer  3 ; said control circuit  2  is suitable for driving the transistors HS and LS by means of the drive signals HSIDE and LSIDE through buffers  81  and  82 .  
         [0004]     In  FIG. 2  the control circuit  2  is shown in more detail. Said circuit comprises a comparator  21  suitable for comparing the voltage Vout, present on the terminal VFB, with the voltage VREF, a comparator  22  having the input terminals coinciding with the terminals CSENSEPLUS and CSENSEMINUS and suitable for detecting the zero crossing of the current that flows through the inductance L and three set-reset flip-flops  23 - 25  in which the flip-flop  23  has the input set S coupled with the output of the comparator  21 , the flip-flop  24  has the input reset R coupled with the output of the comparator  22  and the flip-flop  25  has the input set S coupled with the output of the oscillator  3 . The outputs of the flip-flops  23  and  24  are respectively the drive signals HSIDE and LSIDE for the transistors HS and LS. The circuit  2  also comprises a timer  26  which when the input is at a low logic level has a low output. Initially the set reset flip-flops  23  and  25  are reset while the flip-flop  24  is set. When the signal Vout falls below the value VREF the comparator  21  sets the flip-flop  23 ; in this manner the signal HSIDE is raised while the signal LSIDE is lowered and the voltage Vout rises above the value of the voltage VREF. After a period given by the turn-on time Ton of the transistor HS the timer  26  changes the output signal taking it to a high logic level; said signal resets the flip-flop  23  which in turn lowers the signal HSIDE and raises the signal LSIDE. In these operating conditions, that is for loads exceeding half the ripple on the current IL in pulse width modulation, the period Tp of repetition of the charge transfer cycles in output in the converters is equal to Ton*Vin/Vout.  FIG. 3  shows the time diagrams of the voltages Vout and VREF, of the current IL on the inductance L and of the signals HSIDE and LSIDE.  
         [0005]     In the case that the load LOAD absorbs low value currents, for example of the order of milliamperes, it can happen that the current IL that flows in the inductance L becomes negative during the turn-off period Toff of the transistor HS; in this case the comparator  22  resets the flip-flop  24  so as to lower the signal LSIDE. In this manner the half-bridge constituted by the transistors LS and HS is left at high impedance to prevent the inversion of the sign of the current and the output voltage Vout is discharged on the load LOAD. When the voltage Vout falls below the value of VREF the flip-flop  24  is set and the previous cycle is repeated with the turn-on of the transistor HS; the control circuit  2  works in pulse frequency mode. The control circuit  2  can also comprise a timer  27  suitable for establishing the minimum turn-off time Toff of the transistor HS; in this manner the stability is ensured in regard to the noise induced by the switching of the transistors HS and LS.  
         [0006]     In the case of low load and in the presence of pulse frequency modulation a charge  
       Q   =         1   2     ⁢       Vin   -   Vout     L     ⁢     Ton   ⁡     (     Ton   +   Toff     )         =       1   2     ⁢       Vin   -     V   ⁢           ⁢   out       L     ⁢     Vin   Vout     ⁢     Ton   2             
 
 is transferred at every cycle. The frequency fp of repetition of the charge transfer cycles in output in the converters is directly proportional to the current on the load Iload because fp=Q/Iload; if said current becomes low the frequency fp can return within the range of frequencies audible by humans. For this reason the converter has a device for limiting the minimum frequency; said device is implemented by the timer  3 . When in the conditions of detection of negative current IL and consequent lowering of the signals HSIDE and LSIDE, the timer  3  prevents the pulse period Tp, inverse of the frequency fp, from exceeding a predefined value Tpmax by sending a pulse to the set input of the flip-flop  25  which, in turn, sends a signal on the set input of the flip-flop  24  to raise the value of the signal LSIDE. When the voltage Vout falls below the value VREF the flip-flop  25  is reset. In  FIG. 4  the course of the voltage Vout, of the current IL and of the signals HSIDE, LSIDE and MIN-FREQ if the flip-flop  25  is activated can be seen. 
 
         [0007]     A converter of this type suffers from an error in direct current given by half of the ripple on the output signal Vout; this comes about because the regulation is carried out on the minimum value of the voltage Vout. An integrator can be inserted whose object is to correct said error, as shown in  FIG. 5 . The integrator  4  comprises a transconductance amplifier  41  having the inverting input coupled to the reference voltage VREF and the non-inverting input coupled to the voltage Vout. The integrator comprises a capacitor Cint coupled between the voltage Vout and the output terminal of the amplifier  41  coupled to the control circuit  2  so that the voltage VFB is  
       VFB   =         Gm     s   ⁢           ⁢   C   ⁢           ⁢   int       ⁢     (     Vout   -   Vref     )       +   Vout         
 
 where Gm is the transconductance gain of the amplifier  41 . In this case the comparator  21  compares the voltage VREF with the voltage VFB. To reach the stationary state the average of the voltage Vout within a cycle must be constant. Given that the comparator PWM compares the voltage VFB with the voltage VREF the time average of the voltage VFB must also be constant and therefore Vout=VREF must be direct. The regulation that is operated on the signal VFB is on the minimum values of the signal or valley of the signal VFB. 
 
         [0008]     If the load LOAD absorbs low value currents the regulation on the signal Vout is made on the average value. After a cycle of turn-on time Ton and turn-off time Toff in which the current IL goes to zero, the output voltage Vout is overloaded in relation to the value VREF. While the output voltage remains above the regulated value VREF, integrator  4  raises the voltage VFB. When the load LOAD brings the output voltage below the voltage VREF, the voltage VFB decreases until it reaches the voltage VREF and the comparator  21  is triggered, as can be seen in the time diagrams of  FIG. 6 .  
         [0009]     Nevertheless it is possible that, should the converter be applied to a low load LOAD, the output voltage Vout and the current Il start to oscillate and diverge, that is the circuit results unstable. Said instability is due to the delay of the integrator; when the signal MIN_FREQ is sent, the flip-flop  25  turns on the transistor LS raising the signal LSIDE. The turn-off of the transistor LS is no longer bound to the output voltage but to the voltage VFB. The additional contribution caused by the integrator can introduce a certain delay in the turn-off of the transistor LS and thus enable the loading of a negative current of a certain value in the inductance, with consequent charge transient in the successive cycles; this can lead to the triggering of diverging oscillations on the output, as can be seen in the time diagrams of  FIG. 7 .  
       SUMMARY OF THE INVENTION  
       [0010]     In view of the state of the art described, an embodiment of the present invention provides a control device of a switching converter that overcomes the above-mentioned deficiencies.  
         [0011]     In accordance with an embodiment of the present invention, a control device for a switching converter has an input terminal and an output terminal, said converter comprising a half-bridge of a first and a second transistor coupled between the input terminal and a reference voltage, said control device comprising means capable of detecting a signal on the output terminal of the converter, first means suitable for integrating the detected signal and second means suitable for imposing a predefined minimum frequency of the detected signal, said control device being suitable for carrying out a regulation on the average value of said detected signal by comparison with a further reference signal and being suitable for driving said first and second transistor in function of said regulation, characterized in that it comprises further means suitable for unfiring said first means when said second means are active.  
         [0012]     In accordance with a further embodiment of the present invention, a switching converter has an input terminal, an output terminal, a half-bridge of a first and a second transistor coupled between the input terminal, a reference voltage, and a control device comprising means capable of detecting a signal on the output terminal of the converter, first means suitable for integrating the detected signal and second means suitable for imposing a predefined minimum frequency of the detected signal, said control device being suitable for carrying out a regulation on the average value of said signal detected by comparison with a further reference signal and being suitable for driving said first and second transistor in function of said regulation, characterized in that said control device comprises further means suitable for turning off said first means when said second means are active. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The characteristics and the advantages of the present invention will appear evident from the following detailed description of an embodiment thereof, illustrated as non-limiting example in the enclosed drawings, in which:  
         [0014]      FIG. 1  shows a diagram of a switching converter with constant turn-on time and provided with a controller operating in pulse frequency mode in accordance with the known art;  
         [0015]      FIG. 2  is a more detailed diagram of the controller of  FIG. 1 ;  
         [0016]      FIG. 3  shows time diagrams of signals in the converter of  FIG. 1 ;  
         [0017]      FIG. 4  shows time diagrams of signals in the converter of  FIG. 1  with the activation of the flip-flop  25 ;  
         [0018]      FIG. 5  shows a diagram of another switching converter with constant turn-on time and provided with a controller working in pulse frequency mode in accordance with the known art;  
         [0019]      FIG. 6  shows time diagrams of signals in the converter of  FIG. 5 ;  
         [0020]      FIG. 7  shows time diagrams of signals in the converter of  FIG. 5  if the converter is instable;  
         [0021]      FIG. 8  is a diagram of a switching converter according to the present invention;  
         [0022]      FIG. 9  is a diagram of a variant of the converter of  FIG. 8 ;  
         [0023]      FIG. 10  is a detailed diagram of a part of the control device of  FIG. 9 ;  
         [0024]      FIG. 11  shows time diagrams of signals in the converter of  FIG. 9 ;  
         [0025]      FIG. 12  shows the time diagrams of the signals of  FIG. 10  in a particular period of time; and  
         [0026]      FIG. 13  shows a detailed diagram of a part of the control device according to a variant on the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0027]     In  FIG. 8 a  switching converter is shown according to the present invention. The switching converter has an input terminal IN on which the voltage Vin is present and an output terminal OUT to which the load LOAD is coupled. The converter comprises a half-bridge of a first transistor HS and a second transistor LS coupled between the input terminal IN and a reference voltage, preferably ground GND, an inductance L coupled to the half-bridge and to the output terminal OUT, a control device  100  comprising means capable of detecting a signal Vout on the output terminal OUT of the converter. The control device comprises an integrator  101  suitable for integrating the signal detected Vout and a device  102  suitable for imposing a preset minimum frequency to the signal detected Vout. The control device  100  is suitable for carrying out a regulation on the average value of said signal detected Vout and on the minimum value of the signal VFB and for driving said first HS and second LS transistor in function of said regulation. The control device  100  comprises a logic part  200  having in input the signal VFB in output from the integrator  101 , the signal VREF and the signal MIN_FREQ in output from the device  102  and suitable for sending the signals LSIDE and HSIDE for driving the transistors HS and LS.  
         [0028]     The control device  100  comprises means  105  suitable for disconnecting the integrator  101  when said device for limiting the frequency  102  is active.  
         [0029]     Said means  105  can include a comparator suitable for comparing the voltage Vout with the reference voltage VREF and suitable for turning off the transistor LS, which has been switched on following a pulse MIN-FREQ, and starting up the successive cycle. In this manner the delay of the integrator is ignored.  
         [0030]     The integrator  101  preferably comprises a transconductance amplifier  41  having the inverting input coupled to the reference voltage VREF and the non-inverting input coupled to the voltage Vout. The integrator comprises a capacitor Cint coupled between the voltage Vout and the output terminal of the amplifier  41  coupled to the control circuit  2  so that the voltage VFB is  
       VFB   =         Gm     s   ⁢           ⁢   C   ⁢           ⁢   int       ⁢     (     Vout   -   VREF     )       +   Vout         
 
 where Gm is the transconductance gain of the amplifier  41 . 
 
         [0031]     In a preferred embodiment an offset voltage Voff is introduced into the reference voltage VREF at the input of the comparator  105 ; the voltage Voff has to compensate the existing offset voltage on the transconductance amplifier of the integrator  101  and a value of voltage Vt suitable for compensating the delay of the comparator due to its trigger time. This is because the effect of a trigger voltage of the comparator that is lower than that of regulation causes an instability similar to that given by the delay of the integrator itself.  
         [0032]     In another preferred embodiment of the invention, visible in  FIG. 9 , the means  105  comprise a switch  106  placed between a terminal of the capacitance Cint and the output terminal of the transconductance amplifier  41 . The switch is suitable for disconnecting the capacitance Cint when the transistor LS is turned on by means of the signal MIN_FREQ; the switch is commanded by the signal Dis coming from the logical part  200 . In this manner the transconductance amplifier  41  acts, together with the capacitance Cint, as an integrator to correct the error given by half ripple on the output voltage Vout and acts as a comparator when the capacitance Cint is disconnected from the output terminal of the amplifier  41 ; it is not necessary to carry out a compensation of the offset voltage of the amplifier given that the same amplifier is used as an integrator and as a comparator. Transistors HS and LS are driven through buffers  91  and  92 .  
         [0033]     The logical part  200  of the control device  100  can be seen better in  FIG. 10 . The logical part comprises a comparator  21  suitable for comparing the voltage VFB, present on the terminal VFB, with the voltage VREF, a comparator  22  having the input terminals coinciding with the terminals CSENSEPLUS and CSENSEMINUS, that is the terminals of a resistance Rsense placed between the inductance L and the terminal OUT, and suitable for detecting the zero crossing of the current that flows through the inductance L and three set-reset flip-flops  23 - 25  in which the flip-flop  23  has the set input S coupled with the output of the comparator  21 , the flip-flop  24  has the reset input R coupled with the output of the comparator  22  and the flip-flop  25  has the set input S coupled with the output of the timer  3 . The outputs of the flip-flops  23  and  24  are respectively the drive signals HSIDE and LSIDE for the transistors HS and LS. The circuit  100  also comprises a timer  26  which when the input is at a low logic level has a low output. Initially the set-reset flip-flops  23  and  25  are reset while the flip-flop  24  is set. When the signal VFB falls below the value VREF the comparator  21  sets the flip-flop  23 ; in this manner the signal HSIDE is raised while the signal LSIDE is lowered and the voltage Vout rises above the value of the voltage VREF. After a period given by the turn-on time Ton of the transistor HS the timer  26  changes the signal in output taking it to a high logic level; said signal resets the flip-flop  23  which in turn lowers the signal HSIDE and raises the signal LSIDE. The circuit  100  also comprises a timer  27  suitable for establishing the minimum turn-off time Toff of the transistor HS; in this manner the stability is assured in relation to the noise induced by the switching of the transistors HS and LS. The signal Dis is the signal Q in output from the flip-flop  25 .  
         [0034]     In  FIG. 11  the time diagrams of the signals Vout, VFB, VREF, IL and MIN_FREQ are shown; it can be observed that the regulation of the output voltage Vout comes about on the minimum value or downstream. In  FIG. 12  the trigger instant of the amplifier  41  is highlighted.  
         [0035]     It is possible to compensate the delay of the comparator by introducing a suitable systematic offset which is active only when the comparator is used. For this purpose it is necessary to introduce an additional voltage Vofft to the voltage VREf as shown in  FIG. 9 .  
         [0036]     It is also possible to add a clamp circuit suitable for limiting the charge voltage of the capacitance Cint.  
         [0037]     If the load LOAD is so low that the current  
       Iload   =       fp   ⁢           ⁢   min   *   Q     =     fp   ⁢           ⁢   min   *     1   2     ⁢       Vin   -   Vout     L     ⁢     Vin   Vout     ⁢     Ton   2             
 
 where fpmin is the minimum pulse frequency we have the coexistence of frequency limitation cycles with activation of the transistor LS and pulse frequency modulation cycles with activation of the transistor HS. This can cause oscillations in the frequency of repetition of the cycles that could lead to beating in the range of the audible frequencies. 
 
         [0038]     To avoid said problem it is possible to increase the turn-on time Ton by a period Dton only after the turn-on of the transistor LS due to a pulse MIN_FREQ. Given that the current Iload depends on the square of Ton this introduces a hysteresis on the load current between the input and the output in frequency limitation mode.  
         [0039]     Therefore if the frequency limitation cycle is entered with a current  
         Iload   =       fp   ⁢           ⁢   min   *   Q     =     fp   ⁢           ⁢   min   *     1   2     ⁢       Vin   -   Vout     L     ⁢     Vin   Vout     ⁢     Ton   2           ,       
 
 after the turn-on of the transistor LS with a pulse MIN_FREQ, the current Iload becomes  
       Iloadnew   =       fp   ⁢           ⁢   min   *   Q     =     fp   ⁢           ⁢   min   *     1   2     ⁢       Vin   -   Vout     L     ⁢     Vin   Vout     ⁢       (     Ton   +   Dton     )     2             
 
 and therefore in order to return in pulse frequency modulation mode the current of the load should ideally exceed the value Iloadnew. 
 
         [0040]     In  FIG. 13 a  modified control device  100  is shown that comprises means  110  for increasing the turn-on time Ton by a time period Dton after the turn-on of the transistor LS following a pulse MIN_FREQ. Said means  110  comprise a set-reset flip-flop  111  which is set with the sending of the pulse MIN_FREQ and is reset at the successive turn-off of the transistor LS. The output HIGHERTON of the flip-flop  111  works on the timer  26  to increase its output by the time period Dton.  
         [0041]     While there have been described above the principles of the present invention in conjunction with specific memory architectures and methods of operation, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicant hereby reserves the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.