Abstract:
A CMOS image sensor according to the present invention has a low-voltage photodiode which is fully depleted at a bias of 1.2-4.5V. The photodiode comprises: a P-epi layer; a field oxide layer dividing the P-epi layer into a field region and an active region; a N −  region formed within the P-epi layer, wherein the first impurity region is apart from the isolation layer; and a P 0  region of the conductive type formed beneath a surface of the P-epi layer and on the N −  region, wherein a width of the P 0  region is wider than that of the N −  region so that a portion of the P 0  region is formed on the P-epi layer, whereby the P 0  region has the same potential as the P-epi layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a solid state image sensing device capable of producing a high quality picture, and more particularly to an image sensor associated with the CMOS technology and a method for fabricating the same. 
     2. Description of the Related Art 
     With the development of the telecommunication and computer system, CMOS image sensors can be utilized in electronic imaging systems. The demand for CMOS image sensors will be much more increased in proportion to the development of digital still cameras, PC cameras, digital camcoders and PCS (personal Communication Systems), as well as standard analog and advanced digital TV and video systems. Further, the CMOS image sensor can be used in video game machines, security cameras and micro cameras for medical treatment. 
     FIG. 1 is a block diagram illustrating a conventional CCD (Charge Coupled Device) image sensor. As shown in FIG. 1, the CCD image sensor  100  includes a photoelectric conversion and charge accumulator  10  for absorbing light from an object and collecting the photogenerated charges into signal charge packets. Also, the CCD image sensor  100  includes a charge transfer region  20  to convey charge packets from the photoelectric conversion and charge accumulator  10  and a charge-to-voltage signal converter  30  to generate a voltage output of the signal charge packets as transferred through the charge transfer region  20 . 
     A photodiode is widely used as a photoelectric conversion and a charge accumulator. The photodiode having a PN junction forms a potential well to accumulate the charges generated by light from the object. The charges generated in the photoelectric conversion and charge accumulator  10  are trapped in the potential well of the photodiode and the trapped charges are transferred to a desired position according to the movement of the potential well. Such a charge movement is controlled by the charge transfer region  20 . 
     The charge-to-voltage signal converter  30  generates a voltage that is related to the transferred signal charge packets. Since electric charges generate an electric field which corresponds to an electrostatic potential. The charge in electric charge concentration as a result of introducing a signal charge packet can be measured by the charge in the electrostatic potential (i.e. the depth of the potential well). This potential well depth variation contributes to a voltage detection in the CCD image sensor. 
     On the other hand, after detecting the signal, the charges in the current potential well must be removed for subsequent signal detections. This removal of the charges is achieved by flushing the signal charge packet into a drain. By lowering the potential barrier between the potential well and the drain, the potential well can be “reset”. 
     As stated above, the conventional CCD image sensor detects the image signals through the charge coupling. The photodiode, which acts as a photosensitive plate corresponding to an image pixel, does not immediately extract photoelectric current, but extracts it after the charges are accumulated for a predetermined time into a signal packet. Accordingly, the CCD image sensor has a good sensitivity with low noise. However, since the CCD image sensor must continuously transfer photoelectric charge packets, the required driving signals are very complicated, require large voltage swing of approximately 8V to 10V, have high power consumption, and require both positive and negative power supply. Compared with submicron CMOS technology which needs about 20 photomasks, CCD technology is more complicated and also more expensive due to additional photomask processes (about 30 to 40 photomasks). In addition, since the CCD image sensor chip can not be integrated with signal processing circuitry which is typically implemented by CMOS circuitry, it is very difficult to miniaturize the size of the image sensor and implement in a wider variety of applications. 
     Accordingly, a wider and deeper study of the APS (active pixel sensor), which is controlled by the switching operation of a transistor, has been made with the combination of the CMOS and CCD technologies. 
     FIG. 2 is a circuit diagram illustrating a unit pixel of the conventional APS proposed by U.S. Pat. No. 5,471,515 of Fossum, et al. The APS uses a photogate  21  of the MOS capacitor structure to collect photoelectric charges. In order to transfer the charges generated under the photogate  21  to a floating diffusion region  22 , the APS includes a transfer transistor  23 . Also, the APS includes a reset transistor  24 , a drain diffusion region  25 , a drive transistor  26  acting as a source follower, a select transistor  27  to select a pixel array row, and a load transistor  28 . 
     However, in the APS as shown in FIG. 2, the MOS capacitor, which acts as a photosensitive plate, is made of a thick polysilicon layer so that a large fraction of blue light (with a shorter wavelength than red light) is preferentially absorbed by the polysilicon. As a result, it is difficult to obtain high quality color images at low illumination. 
     FIG. 3 is a cross-sectional view of the APS proposed by U.S. Pat. No. 5,625,210 of Lee, et al. U.S. Pat. No. 5,625,210 disclosed the APS with a well-known pinned photodiode. The APS in FIG. 3 includes a pinned photodiode (PPD) to collect the photoelectric charges and a transfer transistor T x  having an N −  region  36  for transferring the photoelectric charges from the PPD to a floating N +  region  37  of an output node. There is provided a reset transistor having the N +  region  37  for one active region and also having an N +  region  38  for another active region coupled to a power supply VDD. The impurities are introduced into a lightly doped P-epi (epitaxial) layer  32  which is grown on a more heavily doped P-type substrate  31 . The PPD is formed by a buried N +  region  33  and a P +  pinning region  34 . Additionally, in FIG. 3, each of the reference numerals  35   a ,  35   b  and  35   c  denote a transistor gate. 
     Specifically, as shown in FIG.  4  and in U.S. Pat. No. 5,625,210 of Lee, et al, the PPD is formed by sequential ion implantation of N +  and P +  impurities, using a single mask layer  41  (e.g., photoresist pattern). In particular, the PPD is formed by only one mask for both N +  and P +  ion implantation processes. 
     However, if the N +  and P +  ion implantation are sequentially performed using only one mask, the P +  pinning region  34  formed above the N +  region  33  will not be reliably electrically connected to the P-epi layer  32 . Especially, since a higher energy is used to implant the N +  region  33  compared with the P +  pinning region  34 , such a ion implantation processes will result in the P +  pinning region  34  being electrically isolated from the P-epi  32 . As a result, the P +  pinning region  34  and the P-epi layer  32  will be at different potential especially when using a low power supply of 3.3V. This difference in potential prevents the full depletion of the N +  region  33  and, therefore, a stable pinning voltage can not be obtained. Furthermore, dopant segregation of boron atoms into the field oxide layer  39  may also contribute toward isolating the P +  pinning region  34  from the P-epi layer  32 . 
     Another U.S. Pat. No. 5,567,632 of Nakashiba and Uchiya disclosed the buried (or pinned) photodiode fabricating method, which employs an inclined ion implantation and a single mask layer. In this case, it is difficult to control and monitor the ion implantation angle in mass production environment. That is, it is very difficult to measure the precise alignment of the N +  pinning region  34  and the P +  region  33  and to make the buried photodiodes uniform and reliable. In addition, the use of an oriented angled ion implantation of either N +  or P +  limits the placement of the transfer gate to a specific orientation relative to the chip and wafer due to the angled ion implantation. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide an image sensor which can operate at low voltage. 
     Another object of the present invention is to provide a method for fabricating an image sensor using a submicron CMOS technology. 
     Further another object of the present invention is to provide an image sensor with improved charge transfer efficiency and a method fabricating the same. 
     In accordance with an aspect of the present invention, there is provided a photodiode used in a CMOS image sensing device, comprising: a semiconductor layer of a first conductive type; an isolation layer dividing the semiconductor layer into a field region and an active region; a first impurity region of a second conductive type, being formed within the semiconductor layer, wherein the first impurity region is apart from the isolation layer; and a second impurity region of the first conductive type, being formed beneath a surface of the semiconductor layer and on the first impurity region, wherein a width of the second impurity region is wider than that of the first impurity region so that a portion of the second impurity region is formed on the semiconductor layer, whereby the second impurity region has the same potential as the semiconductor layer. 
     In accordance with another aspect of the present invention, there is provided a method for fabricating a photodiode used in a CMOS image sensing device, comprising the steps of: providing a semiconductor layer of a first conductive type; forming an isolation layer dividing the semiconductor layer into a field region and an active region; forming a first impurity region of a second conductive type within the semiconductor layer using a first ion implantation mask, wherein the first ion implantation mask covers a portion of the semiconductor layer so that the first impurity region is apart from the isolation layer; and forming a second impurity region of the first conductive type beneath a surface of the semiconductor layer and on the first impurity region using a second ion implantation mask, wherein the second ion implantation mask opens a portion of the semiconductor layer so that a width of the second impurity region is wider than that of the first impurity region and a portion of the second impurity region is in contact with the semiconductor layer. 
     In accordance with further another aspect of the present invention, there is provided a method for fabricating a CMOS image sensing device having a photodiode, the method comprising the steps of: providing a semiconductor layer of a first conductive type; forming an isolation layer on the semiconductor layer in order to define a field region and an active region; forming a gate electrode of a depletion transistor on the semiconductor layer, being apart from the isolation layer; forming a first ion implantation mask exposing a portion of a light sensing area which is positioned between the isolation layer and the gate electrode of the depletion transistor, wherein the first ion implantation mask covers the isolation layer and a portion of the light sensing area which is near to the isolation layer; forming a first impurity region, by introducing impurity ions of a second conductive type into the exposed light sensing area; removing the first ion implantation mask; forming a second ion implantation mask opening all the light sensing area, wherein the second ion implantation mask is positioned at an interface between the isolation layer and the light sensing area so that an open area of the second ion implantation mask is wider than that of the first ion implantation; and forming a second impurity region, by introducing impurity ions of the first conductive type into all the light sensing area, whereby the first impurity region is apart from the isolation layer, a width of the second impurity region is wider than that of the first impurity region, and a portion of the second impurity region is in contact with the semiconductor layer. 
     In accordance with still further another aspect of the present invention, there is provided a method for fabricating a CMOS image sensing device having a photodiode, the method comprising: a first step of providing a semiconductor layer of a first conductive type; a second step of forming a well region of the first conductive type in a portion of the semiconductor layer; a third step of introducing impurity ions into the well region in order to adjust a threshold voltage; a forth step of forming a first gate for a transfer transistor, a second gate for a reset transistor and at least one third gate for an output transistor, wherein the first gate and the second gate are formed outside of the well region and the third gate is formed on the well region and wherein a common active region of the reset transistor and the output transistor is positioned at a boundary between the semiconductor layer and the well region; a fifth step of forming a photodiode in the semiconductor layer, wherein the photodiode electrically coupled to the transfer transistor; a sixth step of forming a first ion implantation mask exposing the well region and introducing low concentration impurity ions of a second conductive type into the well region; a seventh step of forming an insulating spacer layer a sidewall of the third gate; and an eight step of forming a second ion implantation mask exposing the semiconductor layer and the well region, except for the photodiode, and introducing high concentration impurity ions of the second conductive type into the semiconductor layer and the well region, whereby the transfer and reset transistors, whose active regions are formed in the semiconductor layer, operate in a depletion mode, and the output transistor, whose an active region is form 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram illustrating a conventional CCD image sensor; 
     FIG. 2 is a circuit diagram illustrating a unit pixel of the conventional APS; 
     FIGS. 3 and 4 are cross-sectional views illustrating the conventional APS of FIG. 2; 
     FIG. 5 is a circuit diagram illustrating a unit pixel of a CMOS image sensor according to the present invention; 
     FIG. 6 is a cross-sectional view illustrating a unit pixel of a CMOS image sensor according to the present invention; 
     FIGS. 7A to  7 J are cross-sectional views illustrating a method for fabricating the unit pixel of FIG. 6; and 
     FIGS. 8A and 8B are top views of mask patterns used to implant impurity ions into an active region. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, the present invention will be described in detail referring to the accompanying drawings. 
     Referring to FIG. 5, there is shown a unit pixel of a CMOS image sensor according to the present invention. The unit pixel includes a low-voltage photodiode (LVPD)  510  and four NMOS transistors. A transfer transistor (T x )  520  transfers photoelectric charge collected by the low-voltage photodiode  510  for sensing on a floating node  560 . A reset transistor (R x )  530  resets the floating node  560  by flushing charges and setting the potential of the node to a known value. A drive transistor (D x )  540  acts as a source follower buffer amplifier, and a select transistor  550  provides addressing capability to a common load transistor  570 . 
     The present invention has the important advantage in that the image sensor including the low-voltage photodiode  510  and NMOS transistors can be fabricated using common CMOS technology. Also, the transfer transistor (T x )  520  and the reset transistor (R x )  530  are formed as depletion mode or low threshold voltage NMOS transistor in order to improve the charge transfer efficiency and reduce any voltage drop and/or loss of signal charge in the output signal. In particular, a suitable NMOS transistor can be fabricated by using the P-epi layer without the P-well. This negative NMOS transistor may have a slightly negative threshold voltage. 
     FIG. 6 is a cross-sectional view illustrating the unit pixel of the CMOS image sensor according to the present invention. As show in FIG. 6, to improve the sensitivity of the CMOS image sensor and to improve the modulation transfer function by reducing the “miscollection” of photogenerated charges, an epitaxial layer is used to build CMOS devices in the present invention. Namely, a wafer having a P-epi layer  602 , which is formed on a P +  substrate  601  to an impurity concentration of approximately 10 14  ions/cm 3 , is used. The P-epi layer  602  is used for the following reasons: 
     1) the P-epi layer  602  allows the depletion region of the low-voltage photodiode to be large and deep which improves the sensitivity by increasing the ability of the low-voltage photodiode in collecting photogenerated charges. In the present invention, the thickness of the P-epi layer  602  is in a range of approximately 2 to 5 μm. 
     2) the highly doped P +  substrate  601  beneath the P-epi layer  32  improves the sensor array modulation transfer function by reducing the random diffusion of the photoelectric charges. The random diffusion of charges in the P-type substrate leads to the possible “miscollection” of the photogenerated charges by neighboring pixels and directly results in a loss of image sharpness or a lower modulation transfer function. The shorter minority carrier lifetime and higher doping concentration of the P +  substrate  601  significantly reduces the “miscollection” of photoelectric charges since the charges are quickly recombined before diffusing to the neighboring pixels. In the present invention, preferably, the P +  substrate  601  and the P-epi layer  602  have resistivity of about 0.01 Ωcm and 10-25 Ωcm, respectively. Accordingly, the impurity concentration of the P +  substrate  601  should be much higher than that of the P-epi layer  602  and the corresponding minority carrier lifetime of the P +  substrate  601  should be much lower than that of the P-epi layer  602 . 
     Referring again to FIG. 6, the low-voltage photodiode according to the present invention includes a lightly doped N −  region  603  formed in the P-epi layer  602  and a lightly doped p 0  region  604  formed about the lightly doped N −  region  603 . This low-voltage photodiode has excellent sensitivity and photon-to-electron quantum efficiency since the light sensing region is not covered with a polysilicon layer. In particular, the sensitivity of short wavelength, blue light, is significantly improved. As a result of the lightly doped P-epi layer, the charge depletion region of the low-voltage photodiode also has high sensitivity for long wavelength, red or infrared light. In addition, this low-voltage photodiode has the ability to rapidly and efficiently transfer charge to the floating sensing node from the light sensing region. Furthermore, dark current is decreased by controlling the potential of interface generation states at the silicon-silicon dioxide interface. 
     To implement the above-mentioned advantages, the low-voltage photodiode should be fully depleted at a low voltage which is compatible with a power supply of 5V, 3.3V or 2.5V. However, the conventional CCDs require high driving voltage in excess of 8V in order to effectively transfer charges and fully deplete the buried photodiode fabricated in a typical CCD process. Due to high temperature processes after ion implantation of the buried photodiode in a CCD process, the resulting buried photodiode can not be fully depleted at a voltage of less than 5V. Also, buried photodiodes using inclined ion implantation techniques can not be stably implemented by a typical submicron CMOS process which utilizes the low-temperature processes. 
     For example, 0.5 μm CMOS process for 3.3V operation should have a buried photodiode structure which is fully depleted in the range of 1.2V-2.8V. If this voltage is too high, incomplete charge transfer of the photoelectric charges to the floating sensing node will cause many undesirable imaging artifacts. On the other hand, if this voltage is too low, the charge capacity of the buried photodiode will be very low resulting in a small output signal. 
     Without additional thermal treatment which has been used in the conventional CCD processes, by using only two masks, two ion implantation processes and the thermal treatment of the conventional submicron CMOS process, the present invention fabricates a low-voltage photodiode which can be fully depleted at a voltage range of 1.2V-4.5V in the case of the power supply of 3.3V and 5V. This will be concretely illustrated in the processing steps according to the present invention. As shown in FIG. 6, because the edge of a field oxide layer  607  and the edge of the N −  region  603  are sufficiently spaced apart (see “A” in FIG.  6 ), the P 0   region  604  is electrically connected to the P-epi layer  602  and is insured to be at the same potential. That is, a sidewall and a bottom portion of the p 0  region  604  is in contact with the P-epi layer  602 , thereby making the same potential in two layers  603  and  602 . So, by appropriate selection of the N −  and P 0  implant energy and does, the N −  layer  603  can be reliably fully depleted at a voltage between 1.2V-4.5V. 
     Of four NMOS transistors, the transfer transistor (T x ) and the reset transistor (R x ) are low threshold voltage or depletion mode transistors to insure a full reset of the floating node and maximize the output voltage dynamic range. The drive transistor (D x ) and the select transistor (S x ) are typical NMOS transistors. Accordingly, the drive transistor (D x ) and the select transistor (S x ) are formed in the P-well. However, a lateral well diffusion within the pixel causes the electrical characteristics of the low-voltage photodiode and the native transistors to deteriorate. Accordingly, the P-well  605  is limited to a small area but, through a lateral diffusion, incorporates all the drive and select transistors without impacting the low-voltage photodiode and associated reset and transfer transistors. In the preferred embodiment of the present invention, the P-well region includes a portion of the drain  606  of the rest transistor (R x ) and extends to the field oxide layer  607  (hereinafter, this P-well  605  is referred to as a mini P-well). Further, the drive transistor (D x ) and the select transistor (S x ) formed in the P-well  605  use the LDD (Lightly Doped Drain) structure. The transfer transistor (T x ) and the reset transistor (R x ) formed in the P-epi layer  602  do not use the LDD (Lightly Doped Drain) structure, which improves the isolation of the floating node from the reset voltage, reduces the amount of coupling between the reset and transfer clock signal by reducing the overlap capacitance, and increases the overall sensitivity of the pixel by reducing the total capacitance associated with the floating node. 
     The image sensing mechanism according to the present invention will be described in detail: 
     a) the transfer transistor (T x ), the reset transistor (R x ) and the select transistor (S x ) are turned off. At this time, the low-voltage photodiode is fully depleted. 
     b) photons are absorbed in the silicon substrate and generate photoelectric charges. 
     c) the photoelectric charges are collected by the low-voltage photodiode. 
     d) after a predetermined integration time to collect photoelectric charges, the floating sensing node is reset by turning on the reset transistor (R x ). 
     e) the unit pixel is selected for read out by turning on the select transistor (S x ). 
     f) the output voltage V 1  of the source follower buffer is measured (this voltage means only the DC level shift of the floating sensing node). 
     g) the transfer transistor (T x ) is turned on. 
     h) all the collected photoelectric charges are transferred to the floating sensing node. 
     i) the transfer transistor (T x ) is turned off. 
     j) the output voltage V 2  of the source follower buffer is measured. The resulting difference output signal, V 1 -V 2 , is due to the transfer of photoelectric charges. This method is called the CDS (Correlated Double Sampling) method and provides for cancellation of offset voltage, reset switch noise and 1/f flicker noise. 
     k) repeat steps (a) to (j). The low-voltage photodiode is fully depleted at step (h). 
     FIGS. 7A to  7 J are cross-sectional views illustrating a method for fabricating the unit pixel of the CMOS image sensor according to the present invention. 
     Referring to FIG. 7A, a P-epi layer  702  is formed on a P +  substrate  701  and impurities are introduced into the exposed P-epi layer. At this time, since there are, within the unit pixel, one low-voltage photodiode and two native NMOS transistor (transfer and reset transistors) as well as submicron NMOS transistors (drive and select transistors), a conventional P-well substrate as found in a typical submicron CMOS process is not used for the CMOS image sensor of the present invention. The conventional well structure as found in a typical submicron CMOS process will deteriorate the electrical characteristics of the low-voltage photodiode and the native NMOS transistors due to the limited tolerance for lateral dopant diffusion within the small pixel. That is, as illustrated above, the mini P-well process is carried out. 
     Referring to FIG. 7B, after removing the P-well ion implantation mask  703 , a P-well  705  which incorporates both the drive and select transistors is formed by the lateral diffusion during thermal treatment. 
     Referring to FIG. 7C, for the purpose of device isolation, a field oxide layer  707  to define a field region and an active region is formed by the LOCOS process, the trench isolation process or the like. In this embodiment, a multilayer mask pattern  706  where a pad oxide layer, buffer polysilicon layer and a nitride layer are formed in this order is used as a wet oxidation mask for forming the field oxide layer. The isolation is well-known to those of ordinary skill in the art to which the subject matter pertains. 
     Referring FIG. 7D, after removing the multilayer mask pattern  706 , a mask pattern  740  to expose the P-well  705  is formed and an ion implantation is carried out to adjust the N-channel threshold voltage and the punchthrough. By using such an ion implantation, the drive and select transistors within the unit pixel can exhibit the typical characteristics of the submicron NMOS transistors. Meanwhile, this ion implantation adjusting the threshold voltage is not carried out in a region in which the low-voltage photodiode and two native transistors are to be formed. 
     Referring to FIG. 7E, to form four NMOS transistors within the unit pixel, a polysilicon layer  709  and a tungsten silicide layer  710  are, in this order, formed on the P-epi layer  702  and patterned by mask and etching processes, thereby forming four gate electrodes  711  which are spaced a predetermined distance apart. 
     Next, referring to FIG. 7F, a mask pattern  713  is formed on the resulting structure to form a lightly doped N −  region  721  of the low-voltage photodiode and impurities are introduced into the P-epi layer  702  at a concentration of approximately 10 17  ions/cm 3 . At this time, it should be noted that it is very important to define an ion implantation area using the mask pattern  713  as an implantation mask. As shown in the cross-sectional view of FIG. 7F, one end  715  of the mask pattern  713  is positioned in the middle of the gate electrode of the transfer transistor and the other  716  thereof is positioned inside the active region. In other words, the interface between the field region and the active region is covered with the mask pattern  713  so that a portion of the active region, which is in the neighborhood of the interface, is not applied to the ion implantation. The mask patten  713  is taken along line A-A′ of a photomask in FIG.  8 A. As shown in FIG. 8A, the mask pattern  713  is aligned along an interface (dotted lines in FIG. 8A) between the active region and the field region but it covers a portion  800  of the active region, thereby preventing N −  impurity ions from being introduced into the edge thereof. 
     Referring to FIG. 7G, the mask pattern  713  is removed and another mask pattern  717  is formed to form a lightly doped p 0  region  722 . The impurities are introduced into the P-epi layer  702  at a concentration of approximately 10 18  ions/cm 3 . At this time, the acceleration energy of the p 0  ions is lower than that of N −  ions of FIG. 7F so that the lightly doped P 0  region  722  is positioned on the lightly doped N −  region  721 . As shown in the cross-sectional view of FIG. 7G, one end  719  of the mask pattern  717  is positioned in the middle of the gate electrode of the transfer transistor and the other  720  thereof is positioned on the field oxide layer  707 . 
     FIG. 8B shows a top view of the mask pattern  717 . Accordingly, the entire active region of the low-voltage photodiode of the present invention is exposed so that the sufficient electrical connection A is achieved between the P 0  region  722  and the P-epi layer  702 , compared with the electrical connection shown in FIG.  3 . Although the present invention employs two masks of different size, it should be noted that such a connection A can be achieved by controlling the depth of the impurity regions. 
     On the other hand, with respect to these ion implanting processes of FIGS. 7F and 7G, the thickness of the gate electrode of the transfer transistor must be controlled. Since the doping profile of the low-voltage photodiode determines the charge transfer efficiency, the doping area is self-aligned with the one end of the gate electrode of the transfer transistor. Accordingly, the gate electrode of the transfer transistor must have such a thickness as to block the accelerated ions. If not, the ions penetrate into the gate electrode so that the ion doped layers  721  and  722  are not self-aligned with the edge of the gate electrode of the transfer transistor. This misalignment degrades the charge transfer efficiency. The polysilicon layer and the tungsten silicide layer are formed at a thickness of about 1500 Å and below 1500 Å, respectively, in the conventional CMOS process, but in the preferred embodiment of the present invention they are formed at a thickness of above 2000 Å and above 1500 Å, respectively. As a result, the thickness of the gate electrode of the transfer transistor according to the present invention is relatively thicker than that of the NMOS transistor fabricated by the conventional CMOS processes. 
     In addition, since the edge of the lightly doped N −  region  721  is apart from the edge of the field oxide layer  707  and the sufficient electrical connection A is achieved between the P 0  region  722  and the P-epi layer  702 , the P 0  region  722  and the P-epi layer  702  has the same potential even at a supply voltage below 5V. Accordingly, the lightly doped N −  region  721  should be fully depleted at 1.2-4.5V. If sufficient electrical connection A between the P +  region  722  and the P-epi layer  702  is not achieved, the photodiode may not act as a low-voltage photodiode and not achieve a full depletion. 
     Next, referring to FIG. 7H, after removing the mask pattern  717 , a mask pattern  723  is formed on the resulting structure, exposing the P-well region in order to provide the drive and select transistors with the LDD structure. By doing so, the drive and select transistors in the P-well will have the same characteristics as the conventional submicron NMOS transistors. Since this ion implantation for LDD structure is not carried out in the P-epi layer  702 , the transfer and reset transistors do not have the LDD structure, i.e., native NMOS transistors. 
     Referring to FIG. 7I, after removing the mask pattern  723 , an oxide layer is deposited on the resulting structure by the LPCVD (Low Pressure Chemical Vapor Deposition) method in order to form source/drain regions of the four transistors within the unit pixel. The etchback process is applied to the oxide layer and then an oxide spacer layers  726  are formed on the sidewalls of all the transistors. A mask pattern  727  for implanting impurity ions into P-epi layer  702  and the P-well  705 , except for the low-voltage photodiode area, is formed on the resulting structure and N +  ion implantation is carried out, thereby forming a highly doped N +  regions  729  for source/drains. 
     As described above, the native transistors T x  and R x  formed on the P-epi layer  702  have a negative threshold voltage (depletion mode). The characteristics of the native depletion mode transistor are effectively used in the transfer transistor of the present invention. For example, when the charge capacity of the photodiode is reached, excess photoelectric charges will overflow the photodiode and be collected by neighboring pixels. The resulting cross-talk from an intense light source in an image is called a “Blooming.” 
     As illustrated in the present invention, in the case where the native transfer transistor in a depletion mode is used, although 0V is applied to the gate of the native transfer transistor, current can flow because of the increased potential difference between the low-voltage photodiode and the floating sensing node, thereby removing the “Blooming.” 
     On the other hand, the self-aligned N −  region  721  and P 0  region  722  within the low-voltage photodiode undergo the out-diffusion process through the high-temperature LPCVD process for forming the oxide spacer layer  726 . In the case where the P 0  region  722  diffuses beyond the N −  region  721  below the transfer transistor gate, a potential barrier, which decreases the charge transfer efficiency, is created at one side of the transfer transistor. Accordingly, in order that this undesired potential barrier is not created at the time of performing the high-temperature LPCVD process, the lateral profile of the P 0  and N −  regions  722  and  721  is carefully controlled. 
     FIG. 7J is a cross-sectional view of the unit pixel after the general back-end processes. As shown in FIG. 7J, after forming a highly doped N +  regions  729 , interlayer insulating layers PMD, IMD 1  and IMD 2  and metal layers M 1  and M 2  are formed and a passivation layer is formed for protecting the device from moisture and scratch. Finally, a color filter array consisting of red, green and blue color arrangement or yellow, magenta and cyan color arrangement is formed on the passivation layer. There are only the insulating layer, passivation layer and color filter on the sensitivity area of the low-voltage photodiode. Also, to shield non-photosensing regions from incident light, another metal layer or opaque light shielding may be used. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.