Abstract:
A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages.

Description:
RELATED APPLICATIONS 
     This application claims benefit of priority under 35 U.S.C. section 119(e) of the U.S. Provisional Patent Application Ser. No. 60/997,832 filed Oct. 4, 2007, entitled “FLIP CHIP CAVITY PACKAGE,” which is hereby incorporated by reference in its entirety. 
     This Application is a Continuation-in-part of the co-pending application Ser. No. 12/002,186, filed Dec. 14, 2007, and titled “CAVITY MOLDED LEADFRAME AND METHOD OF MANUFACTURING THE SAME”, application Ser. No. 12/002,054, filed Dec. 14, 2007, and titled “MOLDED LEADFRAME AND METHOD OF MANUFACTURING THE SAME” and application Ser. No. 12/002,187, filed Dec. 14, 2007, and titled “HALF ETCH PADDLE MOLDED LEADFRAME AND METHOD OF MANUFACTURING THE SAME”, all of which claim priority under 35 U.S.C. section 119(e) to the U.S. Provisional Application Ser. No. 60/875,162, filed Dec. 14, 2006, and titled “MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” and the U.S. Provisional Application Ser. No. 60/877,274, filed Dec. 26, 2006, and titled “MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” all of which are hereby incorporated by reference in their entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention is in the field of semiconductor packaging and is more specifically directed to a flip chip cavity package. 
     BACKGROUND 
     The increasing demand for computer performance has led to higher chip internal clock frequencies and parallelism, and has increased the need for higher bandwidth and lower latencies. Processor frequencies are predicted to reach 29 GHz by 2018, and off-chip signaling interface speeds are expected to exceed 56 Gb/s. Optimization of bandwidth, power, pin count, or number of wires and cost are the goals for high-speed interconnect design. The electrical performance of interconnects is restricted by noise and timing limitations of the silicon, package, board and cable. To that end, semiconductor packages must be made smaller, conforming more and more closely to the size of the die encapsulated within. However, as the size of the package shrinks to the size of the die itself, the size of the package becomes insufficient to support the number of leads generally required by current applications. 
     Chip Scale Packages (CSP) have emerged as the dominant package for such applications.  FIG. 1  shows an example of a CSP in current practice. More specifically, the package in  FIG. 1  is a Wafer Level Chip Scale Package  10  (WLCSP), commonly marketed by companies such as National Semiconductor Corporation as the Micro SMD and Maxim Integrated Products as the UCSP. Generally, solder bumps  11  are formed on processed and completed semiconductor wafers  12  before the wafers are sawed to form an individual semiconductor device  13 . Although this has dramatically reduced package size and can be useful in some instances, it suffers from drawbacks which remove it from consideration for certain applications. First, the pitch between the solder bumps  11  must be made wide enough to effectuate assembly of the device onto a printed circuit board in application. This requirement can force manufacturers to artificially grow die sizes to meet the minimum pitch, thereby increasing cost. Second, the total I/O count of the device is generally constrained due to the decreased reliability at the high bump counts. At bump counts higher than 49, or a 7×7 array, reliability becomes critical and applications such as hand held devices, which require a high degree of reliability, no long become a possible marketplace. 
     To overcome the issues mentioned above, the semiconductor industry has moved toward Ball Grid Array (BGA) packages. The BGA is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern. These pins are used to conduct electrical signals from the integrated circuit (IC) to the printed circuit board (PCB) it is placed on. In a BGA, the pins are replaced by balls of solder formed on the bottom of the package. The device is placed on a PCB that carries copper pads in a pattern that matches the solder balls. The assembly is then heated, such as in a reflow oven or by an infrared heater, causing the solder balls to melt. Surface tension causes the molten solder to hold the package in alignment with the circuit board at the correct separation distance while the solder cools and solidifies. The BGA is a solution to the problem of producing a miniature package for an IC with many hundreds of I/O. As pin grid arrays and dual-in-line (DIP) surface mount (SOIC) packages are produced with more and more pins, and with decreasing spacing between the pins, difficulties arose in the soldering process. As package pins got closer together, the danger of accidentally bridging adjacent pins with solder grew. BGAs do not have this problem, because the solder is factory-applied to the package in exactly the right amount. Alternatively, solder balls can be replaced by solder landing pads, forming a Land Grid Array (LGA) package. 
       FIG. 2  shows a cutaway image of a generic BGA package  20 . Generally, an IC  21  has bondpads  22  to which bondwires  23  are affixed. The IC  21  is mounted on a substrate  24 . In current practice, the substrate  24  is a laminate, such as polyimide. Generally, the substrate  24  is of a similar construction to a PCB. The substrate  24  has copper patterns  25  formed thereon. The bondwires  23  effectuate electrical contact between the IC  21  and the copper patterns  25 . The copper patterns  25  are electrically connected to solder balls  26  through via holes  27  in the substrate  24 . In most embodiments of BGA packages, the IC  21  is encapsulated by a mold compound  28 . Although BGA packages effectuate large I/O count devices in small areas, they are susceptible to moisture. Generally, moisture seeps into packages while awaiting assembly into a finished product, such as a computer. When the package is heated to solder the device into its end application, moisture trapped within the device turns into vapor and cannot escape quickly enough, causing the package to burst open. This phenomenon is known as the “popcorn” effect. What is needed is a semiconductor package that is robust to both structural stressors and moisture. 
     SUMMARY OF THE DISCLOSURE 
     One aspect of the invention is a process for forming a semiconductor package. The process includes forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip in a face to face manner to allow electrical interconnection between each flip chip semiconductor device and its corresponding leadframe. Each flip chip semiconductor device has conductive masses attached thereon to effectuate electrical contact between the at least one flip chip semiconductor device and the corresponding molded leadframe. Preferably, the conductive masses are formed of solder. In one embodiment, the conductive masses are substantially spherical. In another embodiment, the conductive masses are substantially cylindrical. Liquid encapsulant is dispensed on each flip chip semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between each flip chip semiconductor device and its molded leadframe. The molded leadframe strip, the at least one flip chip semiconductor device, and the conductive masses are at least partially encased in a second mold compound. In one embodiment, the second mold compound is molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed. In another embodiment, the second mold compound is dispensed to produce a globular form on the at least one flip chip semiconductor device to form the cavity between the at least one flip chip semiconductor device and the at least one molded leadframe. The molded leadframe strip is singulated to form discrete semiconductor packages. 
     In some embodiments, a second leadframe strip is coupled to the first leadframe strip to form a dual leadframe strip. The first leadframe strip and the second leadframe strip are able to be coupled by a soft metal which is formed of at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds can be identical or differing materials. 
     Another aspect of the invention is an apparatus for forming a semiconductor package. The apparatus includes a means for forming a first leadframe strip mounted upon an adhesive tape. Means is provided for at least partially encasing the first leadframe strip in a first mold compound thereby forming a molded leadframe strip. Means is provided for mounting at least one flip chip semiconductor device on the molded leadframe strip so that each flip chip semiconductor device having conductive masses attached thereon to effectuate electrical contact between each flip chip semiconductor device and the corresponding molded leadframe. Preferably, the conductive masses are formed of solder. In one embodiment, the conductive masses are substantially spherical. In another embodiment, the conductive masses are substantially cylindrical. Means is provided for dispensing liquid encapsulant on each flip chip semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between each flip chip semiconductor device and its molded leadframe. Means is provided for at least partially encasing the molded leadframe strip, each flip chip semiconductor device, and the conductive masses in a second mold compound. In one embodiment, the second mold compound is molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed. In another embodiment, the second mold compound is dispensed to produce a globular form on the at least one flip chip semiconductor device to form the cavity between each flip chip semiconductor device and its molded leadframe. Means is provided for singulating the molded leadframe strip to form discrete flip chip semiconductor packages. 
     In some embodiments, the apparatus includes a means to couple the first leadframe to a second leadframe by a soft metal. The soft metal is formed of at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds can be identical or differing materials. 
     Another aspect of the invention is a semiconductor package. The package includes a first leadframe so that the first leadframe is formed with a half etch technique. A substrate supports the first leadframe. The substrate includes a first mold compound. At least one flip chip semiconductor die is mounted on the first leadframe. A plurality of conductive masses effectuate electrical contact between the first leadframe and the corresponding flip chip semiconductor die. Preferably, the conductive masses are formed of solder. In one embodiment, the conductive masses are substantially spherical. In another embodiment, the conductive masses are substantially cylindrical. A second mold compound at least partially encases the first leadframe, each flip chip semiconductor die, and the plurality of conductive masses. In one embodiment, the second mold compound is molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed. In another embodiment, the second mold compound is molded to produce a globular form on each flip chip semiconductor device to form the cavity between each flip chip semiconductor device and its molded leadframe. 
     Optionally the semiconductor package includes a second leadframe coupled to the first leadframe by a soft metal. The soft metal is formed of at least one of the following materials: gold, silver, lead and tin. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. 
         FIG. 1  shows a prior art Chip Scale Package. 
         FIG. 2  shows a prior art Ball Grid Array package in cross section. 
         FIG. 3  shows a process of forming a molded leadframe according to an embodiment of the current invention. 
         FIG. 4A  shows a process of forming a molded leadframe according to an embodiment of the current invention. 
         FIG. 4B  shows a process of forming a molded leadframe according to another embodiment of the current invention. 
         FIG. 4C  shows a process of forming a molded leadframe according to yet another embodiment of the current invention. 
         FIG. 4D  shows a process of forming a molded leadframe according to yet another embodiment of the current invention. 
         FIG. 5  shows a process of forming individual packages according to an embodiment of the current invention. 
         FIG. 6A  shows a semiconductor package according to an embodiment of the current invention. 
         FIG. 6B  shows an apparatus for realizing the package depicted in  FIG. 6A  according to an embodiment of the current invention. 
         FIG. 6C  shows an alternate process of forming a package in  FIG. 6A  according to an embodiment of the current invention. 
         FIG. 6D  shows the remainder of the process for forming the package  FIG. 6A  according to an embodiment of the current invention. 
         FIG. 6E  shows an alternate apparatus of realizing the package depicted in  FIG. 6A  according to an embodiment of the current invention. 
         FIG. 7  shows a process of forming a Flip Chip Cavity package according to an embodiment of the current invention. 
         FIG. 8  shows a process of forming an alternative embodiment of a Flip Chip Cavity package according to an embodiment of the current invention. 
         FIG. 9  shows a process of forming yet another embodiment of a Flip Chip Cavity package according to an embodiment of the current invention. 
         FIG. 10  shows a double layered leadframe per one embodiment of this invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous details and alternatives are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. For example, it is commonly known in the art of semiconductor device assembly that assembly is generally done on a matrix array of leadframes, often referred to as leadframe strips. Each strip has a plurality of individual positions that will all be processed in the same way through various steps to form individual packaged semiconductor devices. A position can have one or more semiconductor die within. 
     Additional information on leadframe strips as described in the present invention can be found in the related U.S. patent application Ser. No. 11/788,496 filed Mar. 19, 2007, entitled “MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” the entirety of which is hereby incorporated by reference. 
     In a first aspect of the invention, a process  300  of forming semiconductor packages is detailed in  FIG. 3 . A leadframe strip  301  is shown in cross section. In some embodiments, a top mold  302  and a bottom mold  303  are placed to effectuate the injection therein of a mold compound  304 . The top and bottom molds  302 ,  303  can be metal, ceramic, or any material having an appropriate thermal characteristic to withstand the temperatures of the mold compound  304  in its liquid state. It is commonly known by those of ordinary skill in the art of semiconductor device manufacturing that a wide variety of mold compounds  304  are able to be used, each having advantages, disadvantages, and characteristics appropriate for a given application. By way of example, in high temperature applications such as microprocessors which generate a significant amount of heat, a high thermal conductivity mold compound  304  can be used. What is formed is a molded lead frame  305 . Advantageously, the molded leadframe strip  305  will display enhanced rigidity and robust reliability characteristics. The use of a mold compound  304  further enhances encapsulation and protection from external moisture that standard PCB substrates such as polyimide or FR4 cannot provide. 
     For more predictable molding results, carrier tape can be used to effectuate the molding process as shown in  FIG. 4A . A process  400  includes applying a tape  405  on its adhesive side to a leadframe strip  401 . The leadframe strip  401  is then placed in a top mold  412  by the top surface of the leadframe  401 . On the opposite side of the leadframe strip  401 , non-adhesive tape  406  is prepared in a tape loader  407  at the bottom mold  413 . Once the leadframe strip  401  is in place between a top mold  412  and a bottom mold  413 , mold compound  404  is injected and substantially fills all empty cavities. When removed from the mold, a molded leadframe strip  410  is formed. Optionally, a de-gate/de-runner step removes excess mold compound  411 . 
       FIGS. 4B, 4C and 4D  show alternate embodiments for the process detailed in  FIG. 4A . In some embodiments, the leadframe strip  401  can be placed between the top mold  412  and bottom mold  413  with adhesive tape  405  applied to the bottom as shown in  FIG. 4B .  FIG. 4C  shows another embodiment wherein the leadframe strip  401  can be placed between the top mold  412  and bottom mold  413  without the use of adhesive tape. Non adhesive tape  406  can be provided by a tape loader  407  on the bottom surface of the leadframe strip  401 .  FIG. 4D  shows yet another exemplary embodiment where two tape loaders  407  are provided to effectuate the molding of the leadframe strip  401 . It will be appreciated by those of ordinary skill in the art of semiconductor manufacturing that several embodiments exist to place a leadframe strip  401  between a top mold  412  and a bottom mold  413  and the embodiments discussed herein are written solely to be exemplary and non limiting. 
       FIG. 5  shows a process  500  of completing the semiconductor packaging process. Semiconductor devices  501  are mounted on the molded leadframe strip  502 . In some embodiments, multiple semiconductor devices  501  are mounted in each individual position on the molded leadframe strip  502 . Such devices are known as multi chip modules (MCM). Bondwires  503  are mounted on the semiconductor devices  501  to effectuate electrical contact between the molded leadframe strip  502  and the semiconductor devices  501 . In some embodiments where multiple semiconductor devices  501  are placed in each position, bondwires  503  can be placed to effectuate electrical contact between two or more semiconductor devices as applications require. Next, a second mold compound  505  is applied to the molded leadframe strip  502 . The second mold  505  encases the semiconductor devices  501  and bondwires  503  to protect them from outer environments. In some embodiments, the second mold compound  505  and the first mold compound described in  FIGS. 3 and 4  are the same material type. Alternatively, the first and second mold compound  505  are able to be different material types to meet the demands of particular applications. By way of example, the semiconductor device  501  and the leadframe  401  in  FIG. 4  can have different coefficients of expansion in response to heat. The semiconductor device  501  and the leadframe  401  can have different mold compounds having different thermal characteristics such as thermal resistivity and thermal expansion to offset the differing coefficients. The molded leadframe strip  502  are then singulated such as by saw blades  515  to form singulated semiconductor packages  520 ,  530  and  540 . The singulated devices  520 ,  530  and  540  are generally tested, subjected to stress, and tested again to ensure reliability and to filter out non passing or non standard units. 
     In some applications, it is advantageous to allow for greater height clearance within the semiconductor package for example to accept thicker semiconductor devices.  FIG. 6A  shows a singulated semiconductor package  600  in cross section. Within the package, a step cavity or recessed area  601  is capable of receiving a thicker semiconductor die  602 , larger bondwires  603  or in certain embodiments multiple stacked die.  FIG. 6B  shows an exemplary surface  610  of the mold  412  or  413  shown in  FIG. 4B . Elevated protrusions  611  are placed to coincide with a leadframe strip to form the recessed area  601  into the molded leadframe. In an exemplary embodiment, adhesive tape  621  is applied to the back surface of the leadframe strip  622  as shown in  FIG. 6C . The non adhesive tape  610  is embossed by the molded element  613  having the protrusions  611 . The molded leadframe  622  will include step cavities corresponding to the protrusions  611 . 
       FIG. 6D  shows the leadframe strip  622  with a first mold compound  623  to form a molded leadframe  630  having recessed areas  601 . To form singulated packages, semiconductor devices  602  and bondwires  603  are affixed onto the molded leadframe  630 . The devices  602 , bondwires  603  and molded leadframe  630  are encased in a second mold compound  650 . The second mold compound  650  and the first mold compound  623  are able to be the same compound or different compounds depending on the application. Saw blades  655  then singulate the molded leadframe strip  630  into individual semiconductor packages  690 . 
     An alternative surface is shown in  FIG. 6E . In certain applications, such as high temperature applications, thick leadframes are advantageous. To accommodate thick leadframes, the non adhesive tape  610  can have pre-formed holes  660  configured to receive protrusions  670  on a mold surface  675 . The mold surface  675  can be the surface of the top mold  612  or the bottom bold  613 . The mold can be formed of metal, ceramic, hard impact rubber, or any other suitable material. 
       FIG. 7  shows a process  700  for forming flip chip cavity packaged devices  790 . At the step  710 , a leadframe strip  701  is mounted to an adhesive tape  702 . In some embodiments, the leadframe strip  701  is a half etched leadframe. At the step  720 , the leadframe strip  701  is molded by a first mold compound  703  by any of the processes described relative to  FIGS. 4 and 5 . The lead frame strip  701  typically comprises copper, Alloy 42, or another suitable material, and has a typical thickness in the range of 127 to 500 micro meters. Optionally, the lead frame strip  701 , or a portion of the lead frame strip  701  can be pre-plated to form a pre-plated leadframe (PPF). Such plating preferably can be appropriately selected to improve strength, bonding, electrical conductivity, and/or thermal transfer. 
     At the step  730 , the flip chip semiconductor devices  706  are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices  706  can be placed in each position as applications require. The flip chip devices  706  include conductive spheres  707  such as a solder ball affixed to effectuate electrical contact between the molded leadframe strip  705  and the devices  706 . Alternatively, conductive cylinders (not shown) can be used instead of the conductive spheres  707 . At the step  740 , a liquid encapsulant  708  is dispensed to form a cavity  711  between the flip chip semiconductor devices  706  and the molded leadframe strip  705 . Alternatively, a silicon coating can be used as the encapsulant  708  to form the cavity  711  between the flip chip semiconductor devices  706  and the molded leadframe strip  705 . At the step  750 , the molded leadframe strip  705 , flip chip semiconductor devices  706  and conductive spheres  707  are encased in a second mold compound  712 . The second mold compound  712  and the first mold compound  703  can be identical mold compounds or different mold compounds as applications require. The second mold compound  712  is preferably marked to facilitate alignment of a later singulation step. The adhesive tape  702  is removed. A post-mold plating process as practiced by a person of ordinary skill in the art can be performed on the molded leadframe  705 . The post-mold plating process can be skipped if a pre-plated leadframe (PPF) is utilized for the leadframe strip  701 . 
     At the step  760 , the double molded leadframe strip  705  is singulated by saw blades  714 . At the step  770 , the singulated double molded leadframe strip  705  forms individual flip chip cavity packages  790 . These individual devices can then be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads  718  are shown, a few to hundreds of leads are able to be realized using the process described herein. Flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) can be used. The second leadframe can couple to the first leadframe by use of a soft metal. The soft metal can include the materials of gold, silver, lead and tin. The second leadframe can be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns. 
       FIG. 10  shows a double layered leadframe described above. A first leadframe  1001  faces a second leadframe  1002 . In some embodiments, the first leadframe  1001  and second leadframe  1002  are able to be coupled together during a first molding process as described above. Any of the first leadframe  1001  and second leadframe  1002  may be exposed to a first mold  1004  to enhance rigidity and reliability as described in  FIG. 4 . In some embodiments, a soft metal  1003  such as gold or silver may be applied to one of or both of the top and bottom surfaces of the first leadframe  1001  and second leadframe  1002  to increase the performance of desired electrical contact between them. When a double layered leadframe  1000  is formed, it may be used in a similar fashion to the processes described in  FIGS. 7-9 . By way of example, one or more flip chip semiconductor die may be placed thereon, and a second mold compound may be applied before singulation. 
     In another aspect of the invention,  FIG. 8  shows an alternative process  800  for forming flip chip cavity packaged devices  890 . At the step  810 , a leadframe strip  801  is mounted to an adhesive tape  802 . In some embodiments, the leadframe strip  801  is a half etched leadframe. At the step  820 , the leadframe strip  801  is molded by a first mold compound  803  by any of the processes described relative to  FIGS. 4 and 5 . The lead frame strip  801  typically comprises copper, Alloy 42, or another suitable material, and has a typical thickness in the range of 127 to 500 micro meters. Optionally, the lead frame strip  801 , or a portion of the lead frame strip  801  can be pre-plated to form a pre-plated leadframe (PPF). Such plating preferably can be appropriately selected to improve strength, bonding, electrical conductivity, and/or thermal transfer. 
     At the step  830 , the flip chip semiconductor devices  806  are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices  806  can be placed in each position as applications require. The flip chip devices  806  include conductive spheres  807  such as a solder ball affixed to effectuate electrical contact between the molded leadframe strip  805  and the devices  806 . Alternatively, conductive cylinders (not shown) can be used instead of the conductive spheres  807 . At the step  840 , a liquid encapsulant  808  is dispensed to form a cavity  811  between the flip chip semiconductor devices  806  and the molded leadframe strip  805 . Alternatively, a silicon coating can be used as the encapsulant  808  to form the cavity  811  between the flip chip semiconductor devices  806  and the molded leadframe strip  805 . At the step  850 , the molded leadframe strip  805 , flip chip semiconductor devices  806  and conductive spheres  807  are encased in a second mold compound  812 . The second mold compound  812  is molded such that a top surface  809  of the flip chip semiconductor devices  806  are exposed. The second mold compound  812  and the first mold compound  803  can be identical mold compounds or different mold compounds as applications require. The second mold compound  812  is preferably marked to facilitate alignment of a later singulation step. The adhesive tape  802  is removed. A post-mold plating process as practiced by a person of ordinary skill in the art can be performed on the molded leadframe  805 . The post-mold plating process can be skipped if a pre-plated leadframe (PPF) is utilized for the leadframe strip  801 . 
     At the step  860 , the double molded leadframe strip  805  is singulated by saw blades  814 . At the step  870 , the singulated double molded leadframe strip  805  forms individual flip chip cavity packages  890 . These individual devices can then be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads  818  are shown, a few to hundreds of leads are able to be realized using the process described herein. Flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) can be used. The second leadframe can couple to the first leadframe by use of a soft metal. The soft metal can include the materials of gold, silver, lead and tin. The second leadframe can be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns. 
     In another aspect of the invention,  FIG. 9  shows yet another alternative process  900  for forming flip chip cavity packaged devices  990 . At the step  910 , a leadframe strip  901  is mounted to an adhesive tape  902 . In some embodiments, the leadframe strip  901  is a half etched leadframe. At the step  920 , the leadframe strip  901  is molded by a first mold compound  903  by any of the processes described relative to  FIGS. 4 and 5 . The lead frame strip  901  typically comprises copper, Alloy 42, or another suitable material, and has a typical thickness in the range of 127 to 500 micro meters. Optionally, the lead frame strip  901 , or a portion of the lead frame strip  901  can be pre-plated to form a pre-plated leadframe (PPF). Such plating preferably can be appropriately selected to improve strength, bonding, electrical conductivity, and/or thermal transfer. 
     At the step  930 , the flip chip semiconductor devices  906  are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices  906  can be placed in each position as applications require. The flip chip devices  906  include conductive spheres  907  such as a solder ball affixed to effectuate electrical contact between the molded leadframe strip  905  and the devices  906 . Alternatively, conductive cylinders (not shown) can be used instead of the conductive spheres  907 . At the step  940 , a liquid encapsulant  908  is dispensed to form a cavity  911  between the flip chip semiconductor devices  906  and the molded leadframe strip  905 . Alternatively, a silicon coating can be used as the encapsulant  908  to form the cavity  911  between the flip chip semiconductor devices  906  and the molded leadframe strip  905 . The molded leadframe strip  905 , flip chip semiconductor devices  906  and conductive spheres  907  are encased in a second mold compound or globular form  912 . The second mold compound  912  is dispensed and molded to produce the globular form  912  encasing the molded leadframe strip  905 , flip chip semiconductor devices  906  and conductive spheres  907 . The second mold compound  912  and the first mold compound  903  can be identical mold compounds or different mold compounds as applications require. At the step  950 , the second mold compound  912  and the molded leadframe strip  905  are preferably marked to facilitate alignment of a later singulation step. The adhesive tape  902  is removed. A post-mold plating process as practiced by a person of ordinary skill in the art can be performed on the molded leadframe  905 . The post-mold plating process can be skipped if a pre-plated leadframe (PPF) is utilized for the leadframe strip  901 . 
     At the step  960 , the double molded leadframe strip  905  is singulated by saw blades  914 . At the step  970 , the singulated double molded leadframe strip  905  forms individual flip chip cavity packages  990 . These individual devices can then be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads  918  are shown, a few to hundreds of leads are able to be realized using the process described herein. Flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) can be used. The second leadframe can couple to the first leadframe by use of a soft metal. The soft metal can include the materials of gold, silver, lead and tin. The second leadframe can be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns. 
     While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.