Abstract:
The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention is related to testing of logic circuit designs, in particular in the context of compression of test patterns for logic testing.  
         [0002]     Testing of complicated digital logic circuits requires the generation of large test patterns. Unfortunately, the sizes of scan test patterns for today&#39;s large designs can be even larger than the sizes of typical tester memory. This necessitates multiple loading of test patterns during a test application and, in turn, increases test application time and test cost. The oversized test pattern set problem is even more severe in delay testing, which has become a necessary test procedure for deep-sub micron chips. Delay test set sizes are often significantly larger than memory capacities of inexpensive testers. Test set sizes and test application times are major factors that determine the test cost of an integrated circuit.  
         [0003]     One technique for addressing the issue is to compress the test data. It has been proposed, for example, to use reseeding of a pseudo-random pattern generator (such as a linear feedback shift register), to encode test cubes of difficult to test faults. See B. Könemann, “LFSR-coded Test Patterns for Scan Designs,”  Proc. Of European Test Conf ., pp. 237-42 (1991). LFSR reseeding has been used for some time to improve fault coverage for random patterns resistant circuits in built-in self-test (BIST). A number of companies have begun to offer test data compaction tools that take advantage of encoding and reseeding techniques to reduce the size of large test patterns—such as Mentor Graphics Embedded Deterministic Test (EDT), Syntest VirtualScan, and Synopsys DBIST/XDBIST. See, e.g., J. Rajski et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” in Proc. International Test Conference, pp. 301-310 (2002). In general, however, such prior art test compression schemes generate one test pattern from one seed. For example when using either Mentor Graphics EDT or Syntest VirtualScan, one compressed pattern corresponds to one test cube. Syntest VirtuaScan compresses test set sizes by broadcasting; one single test pattern can be shared among multiple scan chains. In order to achieve significant compression rates, typical lengths of scan chains should be split into a larger number of short scan chains. This can result in high routing overhead. Synopsys DBIST/XDBIST does generate a fixed number of test patterns from each seed; however, the additional generated test patterns are not guaranteed to detect any new faults, thereby resulting in disadvantageous increases in test application time.  
         [0004]     Accordingly, there is a need for improved test pattern compression which can achieve greater compression rates without unduly increasing test application times.  
       SUMMARY OF INVENTION  
       [0005]     The present invention is directed to a logic testing architecture that is capable of reusing seeds to generate multiple test patterns. In accordance with an embodiment of the present invention, the decompression engine comprises three pseudo-random pattern generators, such as linear feedback shift registers. Two out of the three pseudo-random pattern generators are seeded while the third pseudo-random pattern generator can be free running. The three pseudo-random pattern generators have outputs which are combined so as to generate values which are inserted into one or more scan chains. For example, the three pseudo-random pattern generators can be combined using a selection circuit which selects values for the scan chain from either a seeded pseudo-random pattern generator or the free running pseudo-random pattern generator, based on a value from the other seeded pseudo-random pattern generator. The selection circuit can be readily implemented, for example, using a multiplexer or a circuit comprising an AND gate and an OR gate.  
         [0006]     The seed can be advantageously chosen so as to specify deterministic test patterns for the scan chain. The seed need only be chosen so as to affect the values in the scan chain that will deviate from the desired deterministic test pattern, as generated for example by automatic test pattern generator. The compression ratio and the hardware overhead of the embodiment will depend on the number of changes that are needed to alter the free running pseudo-random pattern generator to the desired deterministic pattern. In accordance with another embodiment of the present invention, the two seeded patterns can be generated from a single pseudo-random pattern generator based on a single seed. Moreover, additional layers of compression can be inserted between the decompression engine and the automatic test equipment.  
         [0007]     Unlike other reseeding based methods where one seed is used to generate one test pattern, the present invention can reuse seeds for many test patterns all of which can detect at least one new fault. Hence, it can potentially achieve greater compression rate with test application time. These and other advantages of the invention will be apparent to those of ordinary skill in the art by reference to the following detailed description and the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0008]      FIG. 1  is a diagram illustrating a decompression architecture in accordance with an embodiment of the present invention.  
         [0009]      FIG. 2  further illustrates the decompression architecture shown in  FIG. 1  using an example circuit with two scan chains.  
         [0010]      FIG. 3  is a set of illustrative test patterns corresponding to the example shown in  FIG. 2 .  
         [0011]      FIG. 4  is a diagram illustrating a decompression architecture in accordance with another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0012]      FIG. 1  is a diagram illustrating a decompression architecture  100  in accordance with an embodiment of the present invention. The decompression engine  105  comprises three linear feedback shift registers (LFSRs), namely, U-LFSR  110 , F-LFSR  120 , and S-LFSR  130 , and n multiplexers (2 to 1 multiplexers)  141 ,  142 , . . .  145 , where n is the number of scan chains  151 ,  152 , . . .  155  in the circuit. The U-LFSR  110  is a free running LFSR and generates pure pseudo-random pattern sequences. One input of each multiplexer connects to an output of the U-LFSR  110  and the other input connects to an output of the F-LFSR  120 . The F-LFSR  120  and the S-LFSR  130  are re-loadable, i.e. a new seed can be loaded into these LFSRs from external automatic test equipment (ATE)  190  whenever it is necessary to change test pattern sequences. Outputs of the S-LFSR  120  drive select inputs of the n multiplexers; if the select input of a multiplexer is set to a 0 at a scan shift cycle, a random value, which is generated by the U-LFSR  110 , is scanned into the scan chain that connects to the output of the multiplexer and if the select input of the multiplexer is set to a 1, a value generated by the F-LFSR  130  is scanned into the scan chain.  
         [0013]     The seeds for the S-LFSR  120  and the F-LFSR  130  are preferably computed from deterministic test cubes and U-LFSR patterns. A special automatic test pattern generation (ATPG) technique can be used to generate deterministic test patterns that are suitable to maximize compression rate and minimize hardware overhead. Each pair of seeds that is loaded into the S-LFSR  120  and the F-LFSR  130  is used to generate a set of test patterns. The number of test patterns generated by each seed is determined during the seed calculation step.  
         [0014]      FIG. 2  further illustrates the decompression architecture using an example circuit with two scan chains. The decompression engine consists of a  4  stage U-LFSR  210 , a  3  stage S-LFSR  220 , and a 3 stage F-LFSR  230 . Feedback polynomials of the LFSR are shown below the circuit. Assume that we want to apply the four deterministic test patterns shown in the table  301  labeled “Deterministic test pattern” of  FIG. 3  to the circuit by using the decompression engine. If the U-LFSR is initialized with all 1&#39;s and the test sequences generated by the U-LFSR are directly loaded into the scan chains without being altered by the decompression engine, then the two scan chains will be loaded with patterns shown in the table right hand side of the deterministic test pattern table of  FIG. 3 . U-LFSR pattern values that conflict with determinist test patterns in the same rows are highlighted with underlines. Those conflicting values are altered by the decompression engine to apply the desired deterministic test patterns to the scan chains.  
         [0015]     Consider altering random pattern R 1  by using the decompression engine to apply a pattern to the scan chains that can be covered by deterministic pattern T 1 . T 1  has four specified bits (care bits): s 15 , s 13 , s 23 , and s 21  and among them only s 15  conflicts with its corresponding random pattern R 1 . Hence, the random value generated by the U-LFSR should be altered at the scan shift cycle when the value for s 15  is scanned into scan chain  1  to detect all the faults that are targeted by T 1 . Since U-LFSR patterns for the other scan inputs s 13 , s 23 , and s 21  are equivalent to deterministic test patterns, U-LFSR patterns for those scan inputs can be directly scanned into the scan chains without being altered. If the F-LFSR value and the U-LFSR value at a scan shift cycle are equivalent, then S-LFSR value during the scan shift cycle is “don&#39;t care”. For example, since f 2  is assigned a 1 and r 2  is also assigned a 1 at the cycle when the value for s 21  is scanned into the scan chain  2  ( 521  is assigned a 1 in both F 1  and R 1 ), the value at selection signal sel 2  is a “don&#39;t care” (since whether sel 2  is assigned a 0 or 1, a 1 is scanned into the scan chain  1 ). In contrast, for the cycles when desired deterministic test pattern values are not identical to F-LFSR values but only identical to U-LFSR values, the S-LFSR values should be specified to 0&#39;s to select the U-LFSR values (random pattern values). For example, scan input s 23  is assigned a 1 in deterministic pattern T 1  but assigned a 0 in F 1 . Hence, sel 2  should be set to a 0 to scan in the value generated by the U-LFSR when the value for s 23  is scanned into scan chain  2 .  
         [0016]     Since the compression ratio and hardware overhead for this embodiment of the present invention depends on the number of specified inputs in the F-LFSR patterns and the S-LFSR pattern, it is important to maximize the “don&#39;t cares”, i.e., minimize the number of specified inputs. The values that must be satisfied by F-LFSR and S-LFSR patterns to apply desired values to the scan chains are underlined in the F-LFSR pattern table  303  and the S-LFSR pattern table  304 . When the F-LFSR is loaded with seed  011  and the S-LFSR is loaded with seed  001 , the decompression engine can generate test patterns that alter U-LFSR patterns to the desired deterministic patterns. In this simple example, the pair of seeds are used to generate  4  deterministic patterns. The table  305  with caption “Altered test patterns” shows test patterns that are applied to the scan chains.  
         [0017]     The required stages of the F-LFSR (S-LFSR) are determined by the number of specified values, i.e., values that must be satisfied in the F-LFSR pattern (S-LFSR pattern) that has the most number of specified bits. If the number of specified bits in the pattern that has the maximum number of specified bits among all F-LFSR patterns is S max , then the required stages for the F-LFSR is S max +20.  
         [0018]     Each deterministic pattern shown in FIG. 3  can be replaced by a generator that is computed from a set of test patterns that are generated by an ATPG.  FIG. 7  shows how generator G 1  is computed from a set of test patterns t 1 , t 2 , and t 3 . s 15  is always assigned 0 or x but never assigned 1 in t 1 , t 2 , and t 3 . Hence, fixing s 15  to 0 can still detect all faults that are detected t 1 , t 2 , and t 3 . In contrast, s 14  is assigned 1 in t 2  but assigned 0 in t 3 . Hence, if we set s 14  to 0 (1), then faults that are detected by t 2  (t 3 ) may not be detected. Hence, s 14  cannot be fixed. On the other hand, s 13  is assigned only 1 and x but never assigned 0 t 1 , t 2 , and t 3 . Hence, s 13  can be fixed to 1 without making any fault that is detected by t 1 , t 2 , and t 3  undetectable. Inputs that are always assigned x such as s 11  are assigned x. A seed that is computed for generator G 1  will be used to generate three test patterns that can detect all faults that are detected by t 1 , t 2 , and t 3 . Since multiple test patterns are generated by a single seed, we can achieve even higher compression ratio by using generators instead of individual test patterns.  
         [0019]      FIG. 4  shows a variant of the present invention. The decompression engine of this scheme comprises three LFSRs, U-LFSR  410 , 0-LFSR  430 , and 1-LFSR  420 , and n fixing logics  441 ,  442 , . . .  445 , where n is the number of scan chains in the circuit. The S-FLSR and the F-FLSR of the scheme shown in  FIG. 1  are replaced by the 0-LFSR  430  and the 1-LFSR  430  and n multiplexers are replaced by n fixing logics  441 ,  442 , . . .  445 . Each fixing logic consists of an AND gate and an OR gate. If a U-LFSR value needs to be altered to a 1 at a scan shift cycle, then corresponding o i , where i=1,2, . . . , n, should be set to a 1 by the 1-LFSR. Similarly, if a U-LFSR value needs to be altered to a 0, then corresponding z i  should be set to a 1 by the 0-LFSR and o i  should be set to a 0 by the 1-LFSR.  
         [0020]      FIG. 5  illustrates another variant of the present invention. The two seeded LFSRs have been combined into a single longer LFSR  520  which accepts a single longer seed from the ATE  590 . The single LFSR  520  generates all of the outputs provided by the two LFSRs.  
         [0021]      FIG. 6  illustrates another variant of the present invention. An additional layer of compression is provided at  607  between the decompression engine  605  and the ATE  690 . The module  607  can be, for example, another decompression engine that lies off-chip as a component of the ATE  690 .  
         [0022]     While exemplary drawings and specific embodiments of the present invention have been described and illustrated, it is to be understood that that the scope of the present invention is not to be limited to the particular embodiments discussed. Thus, the embodiments shall be regarded as illustrative rather than restrictive, and it should be understood that variations may be made in those embodiments by workers skilled in the arts without departing from the scope of the present invention as set forth in the claims that follow and their structural and functional equivalents. As but one of many variations, it should be understood that pseudo-random pattern generators other than linear feedback shift registers can be readily utilized in the context of the present invention.