Abstract:
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional of U.S. Nonprovisional patent application Ser. No. 12/275,812, filed Nov. 21, 2008, the contents of which are herein incorporated by reference in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to the field of integrated circuits. More particularly, this invention relates to replacement metal gates of MOS transistors in integrated circuits. 
       BACKGROUND OF THE INVENTION 
       [0003]    N-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) transistors in advanced integrated circuits frequently have replacement metal gates to improve on-state current densities. Attaining desired effective work functions of the metal gates in both NMOS and PMOS transistors without significantly increasing fabrication cost and complexity has been problematic. 
       SUMMARY OF THE INVENTION 
       [0004]    The instant invention provides a process for forming an integrated circuit which includes NMOS and PMOS transistors with metal replacement gates. The process forms gate work function metal layers in the PMOS transistors with effective work functions above 4.85 eV and gate work function metal layers in the NMOS transistors with effective work functions below 4.25 eV. 
         [0005]    Work function metal layers with effective work functions approximately at mid-gap are formed in both the NMOS and PMOS gates. The work function metal layers are oxidized to increase their effective work functions to the desired PMOS range. Various oxidation processes suitable for this step are disclosed. 
         [0006]    An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over both gates. Materials for the oxygen diffusion blocking layer and the getter are disclosed. A getter anneal extracts the oxygen from the NMOS work function layers into the getter material and adds metal atoms from the getter into the NMOS work function layers, reducing their effective work functions to the desired NMOS range. 
         [0007]    The getter is removed and a metal replacement gate material is formed in both NMOS and PMOS gates. 
     
    
     
       DESCRIPTION OF THE VIEWS OF THE DRAWING 
         [0008]      FIG. 1A  through  FIG. 1M  are cross-sections of an integrated circuit containing an NMOS transistor and a PMOS transistor formed according to the instant invention, depicted in successive stages of fabrication. 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention. 
         [0010]    For the purposes of this disclosure, the term “eV” is understood to mean the unit of energy known as electron-volt. One eV is substantially equal to 1.602×10 −19  joules. The term “meV” is understood to mean milli-electron volts. One meV is substantially equal to 1.602×10 −22  joules. 
         [0011]    For the purposes of this disclosure, the term “MOS transistor” will be understood to mean metal oxide semiconductor transistor. 
         [0012]    For the purposes of this disclosure, the term “work function” will be understood to mean a potential energy difference, measured in eV, between an electron at the Fermi level in a material, to which the work function is being referenced, and an electron in a vacuum adjacent to the material. For example, intrinsic silicon has a work function of approximately 4.6 eV at room temperature. N-type silicon with a doping density between 3×10 17  cm −3  and 3×10 18  cm −3  has a work function of approximately 4.1 eV at room temperature. P-type silicon with a doping density between 3×10 17  cm −3  and 3×10 18  cm −3  has a work function of approximately 5.1 eV at room temperature. The term “effective work function” will be understood to mean a calculated potential energy of an electron in a gate in an MOS transistor which is consistent with an observed flat-band potential and all substrate and gate interface charge effects. 
         [0013]    For the purposes of this disclosure, the term “getter” will be understood to refer to a material which has a capability of absorbing an element such as oxygen from a region surrounding the getter material. Similarly, the term “gettering” will be understood to mean the act of absorbing an element into a getter material. 
         [0014]    Chemical formulas such as SiON of a material in this disclosure are understood to list elements of which the material is substantially composed, but no stoichiometric relationships between the elements are implied or may be assumed, unless numerical subscripts are included in the chemical formulas. 
         [0015]    The instant invention provides a process for forming an integrated circuit which includes NMOS and PMOS transistors with metal replacement gates. The process forms gate work function metal layers in the PMOS transistors with effective work functions above 4.85 eV and gate work function metal layers in the NMOS transistors with effective work functions below 4.25 eV. 
         [0016]      FIG. 1A  through  FIG. 1M  are cross-sections of an integrated circuit containing an NMOS transistor and a PMOS transistor formed according to the instant invention, depicted in successive stages of fabrication. Referring to  FIG. 1A , the integrated circuit ( 1000 ) is formed on a semiconductor substrate ( 1002 ) which is commonly a single crystal silicon wafer, but may be a silicon-on-insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with regions of different crystal orientations, or other material appropriate for fabrication of the IC ( 1000 ). The integrated circuit ( 1000 ) contains an NMOS region ( 1004 ) for an NMOS transistor and a PMOS region ( 1006 ) for a PMOS transistor. An NMOS gate dielectric layer ( 1008 ) is formed on a top surface of the substrate ( 1002 ) in the NMOS region ( 1004 ). The NMOS gate dielectric layer ( 1008 ) is typically one or more layers of silicon oxide (SiO x ), silicon nitride (Si 3 N 4 ), silicon oxy-nitride (SiON), aluminum oxide (Al 2 O 3 ), aluminum oxy-nitride (AlON), hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium silicon oxy-nitride (HfSiON), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium silicon oxy-nitride (ZrSiON), a combination of the aforementioned materials, or other insulating material. The NMOS gate dielectric layer ( 1008 ) may include nitrogen as a result of exposure to a nitrogen containing plasma or a nitrogen containing ambient gas at temperatures between 50° C. and 800° C. The NMOS gate dielectric layer ( 1008 ) is typically between 1 and 4 nanometers thick. A thicker NMOS gate dielectric layer ( 1008 ) may be formed in NMOS transistors operating above 2.5 volts. The NMOS gate dielectric layer ( 1008 ) may be formed by any of a variety of gate dielectric formation processes, for example thermal oxidation, plasma nitridation of an oxide layer, and/or dielectric material deposition by atomic layer deposition (ALD). 
         [0017]    A PMOS gate dielectric layer ( 1010 ) is formed on a top surface of the substrate ( 1002 ) in the PMOS region ( 1006 ). The PMOS gate dielectric layer ( 1010 ) is typically between 1 and 4 nanometers thick, and includes some or all of the same materials in the NMOS gate dielectric layer ( 1008 ). A thicker PMOS gate dielectric layer ( 1010 ) may be formed in PMOS transistors operating above 2.5 volts. All or part of the PMOS gate dielectric layer ( 1010 ) is typically formed concurrently with the NMOS gate dielectric layer ( 1008 ). 
         [0018]    An NMOS gate work function metal layer ( 1012 ) is formed on a top surface of the NMOS gate dielectric layer ( 1008 ). The NMOS gate work function metal layer ( 1012 ) may be titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), or other metal with an effective work function between 4.5 and 4.7 eV. The NMOS gate work function metal layer ( 1012 ) may be between 1 and 10 nanometers thick, and may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), ALD, or other process appropriate for deposition of thin metal films. A PMOS gate work function metal layer ( 1014 ) is formed on a top surface of the PMOS gate dielectric layer ( 1010 ) of similar materials and properties as the NMOS gate work function metal layer ( 1012 ). In one embodiment, the PMOS gate work function metal layer ( 1014 ) may be formed concurrently with the NMOS gate work function metal layer ( 1012 ). 
         [0019]    An NMOS dummy gate layer ( 1016 ) is formed on a top surface of the NMOS gate work function metal layer ( 1012 ). The NMOS dummy gate layer ( 1016 ) may be polycrystalline silicon, commonly known as polysilicon, or other material such as silicon germanium which has a high etch selectivity to the NMOS gate work function metal layer ( 1012 ) during a subsequent wet etch process. In one embodiment, the NMOS dummy gate layer ( 1016 ) is between 40 and 80 nanometers thick. In another embodiment, the thickness of the NMOS dummy gate layer ( 1016 ) is between two and three times a width of an NMOS gate to be formed in the NMOS region ( 1004 ). The NMOS dummy gate layer ( 1016 ) may be formed by plasma enhanced chemical vapor deposition (PECVD) or other deposition process appropriate for forming thin films of dummy gate material. In an alternate embodiment, the NMOS dummy gate layer ( 1016 ) may be doped with phosphorus to improve etch selectivity to the NMOS gate work function metal layer ( 1012 ) during the subsequent wet etch process. 
         [0020]    A PMOS dummy gate layer ( 1018 ) is formed on a top surface of the PMOS gate work function metal layer ( 1014 ) of similar materials and properties as the NMOS dummy gate layer ( 1016 ). In one embodiment, the PMOS dummy gate layer ( 1018 ) may be formed concurrently with the NMOS dummy gate layer ( 1016 ). 
         [0021]    An NMOS hard mask ( 1020 ) is formed on a top surface of the NMOS dummy gate layer ( 1016 ). The NMOS hard mask ( 1020 ) may include one or more layers of silicon nitride (SiN), silicon oxy-nitride (SiON), silicon carbide (SiC), silicon oxy-carbide (SiOC), silicon oxy-nitride-carbide (SiCON), or other dielectric material appropriate for blocking silicidation of the top surface of the NMOS dummy gate layer ( 1016 ) during a subsequent silicidation process, and appropriate for providing a stop layer for a subsequent chemical mechanical polish (CMP) process. The NMOS hard mask ( 1020 ) may be formed by PVD, CVD, PECVD, MOCVD or other deposition process. In one embodiment, the NMOS hard mask ( 1020 ) may be between 20 and 40 nanometers thick. 
         [0022]    A PMOS hard mask ( 1022 ) is formed on a top surface of the PMOS dummy gate layer ( 1018 ) of similar materials and properties as the NMOS hard mask ( 1020 ). In one embodiment, the PMOS hard mask ( 1022 ) may be formed concurrently with the NMOS hard mask ( 1020 ). 
         [0023]    Referring to  FIG. 1B , unwanted material from the NMOS hard mask ( 1020 ), the NMOS dummy gate layer ( 1016 ), the NMOS gate work function metal layer ( 1012 ) and the NMOS gate dielectric layer ( 1008 ) is removed during a gate etch process. Similarly, unwanted material from the PMOS hard mask ( 1022 ), the PMOS dummy gate layer ( 1018 ), the PMOS gate work function metal layer ( 1014 ) and the PMOS gate dielectric layer ( 1010 ) is removed during the gate etch process. A gate photoresist pattern, not shown in  FIG. 1B  for clarity, is formed on top surfaces of the NMOS hard mask ( 1020 ) and the PMOS hard mask ( 1022 ). The gate etch process includes reactive ion etch (RIE) process steps which provide fluorine containing etchants and possibly chlorine containing etchants from a plasma to a top surface of the integrated circuit ( 1000 ). The photoresist pattern blocks the etchants from areas of the NMOS region ( 1004 ) and PMOS region ( 1006 ) defined for an NMOS gate and a PMOS gate. 
         [0024]    NMOS gate sidewall spacers ( 1024 ) are formed on lateral surfaces of the NMOS dummy gate layer ( 1016 ), the NMOS gate work function metal layer ( 1012 ) and the NMOS gate dielectric layer ( 1008 ), typically by deposition of one or more conformal layers of silicon nitride and/or silicon oxide on a top and lateral surfaces of the NMOS gate layers and the top surface of the substrate ( 1002 ), followed by removal of the conformal layer material from the top surface of the NMOS hard mask ( 1020 ) and the top surface of the substrate ( 1002 ) by anisotropic etching methods, leaving the conformal layer material on the lateral surfaces of the NMOS dummy gate layer ( 1016 ), the NMOS gate work function metal layer ( 1012 ) and the NMOS gate dielectric layer ( 1008 ). The NMOS gate sidewall spacers ( 1024 ) are typically 10 to 50 nanometers thick. Similarly, PMOS gate sidewall spacers ( 1026 ) are formed on lateral surfaces of the PMOS dummy gate layer ( 1018 ), the PMOS gate work function metal layer ( 1014 ) and the PMOS gate dielectric layer ( 1010 ). It is typical for a part of the PMOS gate sidewall spacers ( 1026 ) to be formed concurrently with the NMOS gate sidewall spacers ( 1024 ). 
         [0025]    N-type source and drain (NSD) regions ( 1028 ), including n-type lightly doped drain (NLDD) regions, are formed in the substrate ( 1002 ) adjacent to the NMOS gate dielectric layer ( 1008 ) by ion implanting n-type dopants such as phosphorus and arsenic into the substrate ( 1002 ). NLDD regions are formed by implanting n-type NLDD dopants adjacent to the NMOS gate dielectric layer ( 1008 ) prior to formation of the NMOS gate sidewall spacers ( 1024 ). Additional n-type NSD dopants are implanted after formation of the NMOS gate sidewall spacers ( 1024 ) and annealed to form the NSD regions ( 1028 ). Similarly, p-type source and drain (PSD) regions ( 1030 ), including p-type lightly doped drain (PLDD) regions, are formed in the substrate ( 1002 ) adjacent to the PMOS gate dielectric layer ( 1010 ) by ion implanting p-type dopants such as boron and possibly gallium into the substrate ( 1002 ). PLDD regions are formed by implanting p-type PLDD dopants adjacent to the PMOS gate dielectric layer ( 1010 ) prior to formation of the PMOS gate sidewall spacers ( 1026 ). Additional p-type PSD dopants are implanted after formation of the PMOS gate sidewall spacers ( 1026 ) and annealed to form the PSD regions ( 1030 ). 
         [0026]    NSD metal silicide layers ( 1032 ) are formed on top surfaces of the NSD regions ( 1028 ) and PSD metal silicide layers ( 1034 ) are formed on top surfaces of the PSD regions ( 1030 ). The metal silicide layers ( 1032 ,  1034 ) are formed on exposed silicon areas of the top surface of integrated circuit ( 1000 ), commonly by depositing a layer of metal, such as nickel, cobalt, or titanium, on a top surface of the IC ( 1000 ), heating the IC ( 1000 ) to react a portion of the metal with exposed silicon in active areas of the IC ( 1000 ), and selectively removing unreacted metal from the IC ( 1000 ) surface, commonly by exposing the IC ( 1000 ) to wet etchants including a mixture of an acid and hydrogen peroxide. The NMOS hard mask ( 1020 ) desirably blocks formation of metal silicide on the top surface of the NMOS dummy gate layer ( 1016 ), and the PMOS hard mask ( 1022 ) desirably blocks formation of metal silicide on the top surface of the PMOS dummy gate layer ( 1018 ). It is desirable to block formation of metal silicide on the top surfaces of the NMOS dummy gate layer ( 1016 ) and the PMOS dummy gate layer ( 1018 ) so as to improve etch characteristics of the dummy gate layers ( 1016 ,  1020 ) during a subsequent dummy gate removal process. 
         [0027]    Referring to  FIG. 1C , a conformal fill oxide layer ( 1036 ) is formed on an existing top surface of the integrated circuit ( 1000 ). In one embodiment, the fill oxide layer ( 1036 ) is composed substantially of silicon dioxide, formed by thermal decomposition of tetraethyl orthosilicate, also known as tetraethoxysilane or TEOS, by thermal curing of methylsilsesquioxane (MSQ), by a high density plasma (HDP) process, by an ozone based thermal chemical vapor deposition (CVD) process, also known as a high aspect ratio process (HARP), by a low pressure chemical vapor deposition (LPCVD) process or by an atmospheric pressure chemical vapor deposition (APCVD) process. The fill oxide layer ( 1036 ) is removed from top surfaces of the NMOS hard mask ( 1020 ) and the PMOS hard mask ( 1022 ) by a selective removal process such as an oxide CMP process. The NMOS hard mask ( 1020 ) and the PMOS hard mask ( 1022 ) desirably provide stop layers for the CMP process. 
         [0028]      FIG. 1D  depicts the integrated circuit ( 1000 ) after an etchback process ( 1038 ) which removes the NMOS hard mask ( 1020 ) and the PMOS hard mask ( 1022 ), and removes material from top surfaces of the NMOS gate sidewall spacers ( 1024 ), the PMOS gate sidewall spacers ( 1026 ) and the fill oxide layer ( 1036 ). In one embodiment, the etchback process ( 1038 ) provides substantially equal etch rates of the NMOS hard mask ( 1020 ), the PMOS hard mask ( 1022 ), the NMOS gate sidewall spacers ( 1024 ), the PMOS gate sidewall spacers ( 1026 ) and the fill oxide layer ( 1036 ). The etchback process ( 1038 ) may include an RIE step using fluorine containing etchants and possibly oxygen radicals and/or ions. 
         [0029]      FIG. 1E  depicts the integrated circuit ( 1000 ) after a dummy gate removal process. In one embodiment of the dummy gate removal process, the integrated circuit ( 1000 ) is exposed to wet etchants which include aqueous ammonium hydroxide (NH 4 OH) at a concentration between 0.5 and 5 percent, at a temperature between 25° C. and 50° C., for 20 to 150 seconds. In another embodiment of the dummy gate removal process, the integrated circuit ( 1000 ) is exposed to wet etchants which include an aqueous mixture of NH 4 OH and tetra-methyl ammonium hydroxide (TMAH). In a further embodiment, the integrated circuit ( 1000 ) is exposed to wet etchants which include choline. The NMOS dummy gate layer material and the PMOS dummy gate layer material is removed from the NMOS region ( 1004 ) and the PMOS region ( 1006 ) while providing an etch selectivity to the NMOS gate work function metal layer ( 1012 ) and the PMOS gate work function metal layer ( 1014 ) of more than 100:1. 
         [0030]      FIG. 1F  depicts the integrated circuit ( 1000 ) during a low temperature oxidation process. Oxygen atoms ( 1040 ) are provided by the low temperature oxidation process to an existing top surface of the integrated circuit ( 1000 ), and diffuse in to the NMOS gate work function metal layer ( 1012 ) and the PMOS gate work function metal layer ( 1014 ). In one embodiment, the oxygen atoms ( 1040 ) in the gate work function metal layers ( 1012 ,  1014 ) may have a distribution of at least 1×10 15  atoms/cm 2  within 1 nanometer of the top surfaces of the NMOS gate dielectric layer ( 1008 ) and the PMOS gate dielectric layer ( 1010 ). In another embodiment, the oxygen atoms ( 1040 ) in the gate work function metal layers ( 1012 ,  1014 ) may have an average concentration between 1×10 18  atoms/cm 3  and 1×10 21  atoms/cm 3 . The oxygen atoms ( 1040 ) in the gate work function metal layers ( 1012 ,  1014 ) increase the effective work functions of the gate work function metal layers ( 1012 ,  1014 ) to above 4.85 eV. 
         [0031]    In a first embodiment of the low temperature oxidation process, the integrated circuit ( 1000 ) may be exposed to a steam ambient between 300° C. and 600° C. for 10 seconds to 30 minutes, as described in U.S. Patent Provisional Application ______ (Texas Instruments docket number TI-67192, filed mm/dd/yyyy) hereby incorporated by reference. In an alternate embodiment, the integrated circuit may be exposed to a steam ambient between 900° C. and 1100° C. for less than 1 second, as described in U.S. Patent Provisional Application ______ (Texas Instruments docket number TI-67192, filed mm/dd/yyyy). 
         [0032]    In a second embodiment of the low temperature oxidation process, the integrated circuit ( 1000 ) may be exposed to a plasma containing oxygen and hydrogen at a temperature up to 500° C., as described in U.S. Patent Provisional Application ______ (Texas Instruments docket number TI-67192, filed mm/dd/yyyy). In an alternate embodiment, the integrated circuit may be exposed to a plasma containing oxygen, and subsequently exposed to a plasma containing hydrogen, as described in U.S. Patent Provisional Application ______ (Texas Instruments docket number TI-67192, filed mm/dd/yyyy). 
         [0033]    In a third embodiment of the low temperature oxidation process, the gate work function metal layers ( 1012 ,  1014 ) may be anodized at a temperature up to 100° C., as described in U.S. Patent Provisional Application ______ (Texas Instruments docket number TI-67192, filed mm/dd/yyyy). 
         [0034]    In a fourth embodiment of the low temperature oxidation process, the integrated circuit ( 1000 ) may be exposed to a dry ambient containing an oxidizing component, such as oxygen (O 2 ), ozone (O 3 ), nitric oxide (NO), nitrous oxide (NO 2 ), or any combination of these gases. The ambient may also include inert gases such as nitrogen or argon. The integrated circuit ( 1000 ) may be heated to 300° C. to 700° C. during exposure to the dry ambient. 
         [0035]    In a fifth embodiment of the low temperature oxidation process, the integrated circuit ( 1000 ) may be exposed to H 2 O containing dissolved ozone. 
         [0036]      FIG. 1G  depicts the integrated circuit ( 1000 ) after formation of an etch stop layer and an oxygen diffusion barrier layer. A thin etch stop layer ( 1042 ) is formed on an existing top surface of the integrated circuit ( 1000 ) including the top surfaces of the NMOS gate work function metal layer ( 1012 ) and the PMOS gate work function metal layer ( 1014 ). The etch stop layer ( 1042 ) is between 2 and 10 nanometers thick over the NMOS gate work function metal layer ( 1012 ) and the PMOS gate work function metal layer ( 1014 ), and is formed of a metallic material which allows oxygen to diffuse across the etch stop layer ( 1042 ) during a subsequent getter anneal process step, and provides an etch stop capability during a subsequent oxygen diffusion barrier etch process step, such as TaN, tungsten nitride (WN), titanium carbide (TiC), TaC, or tungsten carbide (WC). The etch stop layer ( 1042 ) may be formed by ALD, CVD, PVD, MOCVD or other suitable deposition method. An oxygen diffusion barrier layer ( 1044 ) is formed on a top surface of the etch stop layer ( 1042 ). The oxygen diffusion barrier layer ( 1044 ) is greater than 10 nanometers thick over the NMOS gate work function metal layer ( 1012 ) and the PMOS gate work function metal layer ( 1014 ), and is formed of a metallic material which blocks oxygen diffusion during the subsequent getter anneal process step, and has a high etch rate selectivity to the etch stop layer ( 1042 ) during the subsequent oxygen diffusion barrier etch process step, such as TiN. The oxygen diffusion barrier layer ( 1044 ) may be formed by ALD, CVD, PVD, MOCVD or other suitable deposition method. 
         [0037]      FIG. 1H  depicts the integrated circuit ( 1000 ) during a process step to remove the oxygen diffusion barrier layer ( 1044 ) in the NMOS region ( 1004 ). An oxygen diffusion barrier photoresist pattern ( 1046 ) is formed on a top surface of the oxygen diffusion barrier layer ( 1044 ) in the PMOS region ( 1006 ). An oxygen diffusion barrier etch process ( 1048 ) is performed which removes substantially all the oxygen diffusion barrier layer ( 1044 ) in the NMOS region ( 1004 ) from the top surface of the etch stop layer ( 1042 ) in direct contact with the NMOS gate work function metal layer ( 1012 ). The oxygen diffusion barrier etch process ( 1048 ) may be an RIE process using chlorine etchants and possibly fluorine etchants. After the oxygen diffusion barrier etch process ( 1048 ) is completed, the oxygen diffusion barrier photoresist pattern ( 1046 ) is removed from the top surface of the oxygen diffusion barrier layer ( 1044 ), for example by exposing the integrated circuit ( 1000 ) to an oxygen containing plasma, followed by a wet cleanup to remove any organic residue from the top surface of the oxygen diffusion barrier layer ( 1044 ). 
         [0038]      FIG. 1I  depicts the integrated circuit ( 1000 ) after formation of a oxygen getter layer ( 1050 ) on the top surface of the etch stop layer ( 1042 ) over the NMOS gate work function metal layer ( 1012 ) and on the top surface of the oxygen diffusion barrier layer ( 1044 ) over the PMOS gate work function metal layer ( 1014 ). In one embodiment, the oxygen getter layer ( 1050 ) may be formed on an existing top surface of the integrated circuit ( 1000 ). The oxygen getter layer ( 1050 ) may include titanium, hafnium, zirconium, tantalum, aluminum, cerium, lanthanum, or other metal capable of gettering oxygen atoms from the NMOS gate work function metal layer ( 1012 ) during a subsequent getter anneal process step. The oxygen getter layer ( 1050 ) may be formed by ALD, CVD, PVD, MOCVD or other suitable deposition method. 
         [0039]      FIG. 1J  depicts the integrated circuit ( 1000 ) during the getter anneal process step, in which the integrated circuit ( 1000 ) is heated to cause the oxygen atoms ( 1040 ) to diffuse from the NMOS gate work function metal layer ( 1012 ) through the etch stop layer ( 1042 ) into the oxygen getter layer ( 1050 ) in the NMOS region ( 1004 ). During the getter anneal process, metal atoms ( 1052 ) diffuse from the oxygen getter layer ( 1050 ) in the NMOS region ( 1004 ) through the etch stop layer ( 1042 ) into NMOS gate work function metal layer ( 1012 ). The effect of the getter anneal process is to reduce the effective work function of the NMOS gate work function metal layer ( 1012 ) to a value below 4.25 eV. After the getter anneal process is completed, the oxygen atoms ( 1040 ) in the NMOS gate work function metal layer ( 1012 ) have a distribution of less than 1×10 13  atoms/cm 2  within 1 nanometer of the top surface of the NMOS gate dielectric layer ( 1008 ). Metal atoms ( 1052 ) from the oxygen getter layer ( 1050 ) have a distribution of at least 1×10 13  atoms/cm 2  within 1 nanometer of the top surface of the NMOS gate dielectric layer ( 1008 ). 
         [0040]    Oxygen gettering in the PMOS region ( 1006 ) is blocked by the oxygen diffusion barrier layer ( 1044 ). Less than 10 percent of the oxygen atoms ( 1040 ) in the PMOS gate work function metal layer ( 1014 ) are removed during the getter anneal process, so that the effective work function of the PMOS gate work function metal layer ( 1014 ) remains above 4.85 eV. 
         [0041]    The getter anneal process is performed at less than 600° C. to avoid unwanted reactions in the silicide layers ( 1032 ,  1034 ). In one embodiment, the getter anneal process is performed in an inert ambient such as nitrogen or argon. In an alternate embodiment, the getter anneal process is performed at an ambient pressure below 1 millitorr. 
         [0042]      FIG. 1K  depicts the integrated circuit ( 1000 ) after removing the oxygen getter layer. An oxygen getter etch process is performed, which may include immersion in an aqueous solution of a mixture of hydrogen peroxide and an alkaline etchant such as NH 4 OH. All or part of the oxygen diffusion barrier layer ( 1044 ) may be removed from the PMOS region ( 1006 ). All or part of the etch stop layer ( 1042 ) in direct contact with the NMOS gate work function metal layer ( 1012 ) may be removed during the oxygen getter etch process. Similarly, all or part of the etch stop layer ( 1042 ) in direct contact with the PMOS gate work function metal layer ( 1014 ) may be removed during the oxygen getter etch process. 
         [0043]      FIG. 1L  depicts the integrated circuit ( 1000 ) after formation of a metal fill gate layer ( 1054 ) over the NMOS gate work function metal layer ( 1012 ) and the PMOS gate work function metal layer ( 1014 ). In one embodiment, the metal fill gate layer ( 1054 ) may be formed on an existing top surface of the integrated circuit ( 1000 ). The metal fill gate layer ( 1054 ) may be aluminum, tungsten, or any metal with a suitably low electrical resistivity. The metal fill gate layer ( 1054 ) may be formed by ALD, CVD, PVD, MOCVD or other suitable deposition method. 
         [0044]      FIG. 1M  depicts the integrated circuit ( 1000 ) after a planarizing process which removes the metal fill gate layer, the oxygen diffusion barrier layer ( 1044 ) if present, and the etch stop layer ( 1042 ) if present, from the top surface of the fill oxide layer ( 1036 ). Material from the metal fill gate layer is left over the NMOS gate work function metal layer ( 1012 ) to form an NMOS metal fill gate ( 1056 ) and is left over the PMOS gate work function metal layer ( 1014 )) to form a PMOS metal fill gate ( 1058 ). The planarizing process may be a CMP process, an isotropic chemical or physical etch process, or a combinations thereof. 
         [0045]    Formation of the integrated circuit ( 1000 ) is continued using known processes.