Abstract:
A silicon-on-insulator substrate comprises a first silicon substrate having a first crystal orientation, said first substrate having a first polished surface and a first wafer notch; a second silicon substrate having a second crystal orientation different from the first crystal orientation of the first silicon substrate, said second substrate having a second polished surface and a second wafer notch; and the first polished surface of the first silicon substrate being bonded to the second polished surface of the second silicon substrates.

Description:
RELATED APPLICATIONS  
       [0001]    The application is a divisional of U.S. patent application Ser. No. 10/355,872, filed Jan. 21, 2003, and entitled, “Bonded SOI Wafer with &lt;100&gt; Device Layer and &lt;110&gt; Substrate for Performance Improvement,” which is hereby incorporated by reference in its entirety. 
     
    
     
       BACKGROUND  
         [0002]    It is well known in the art that Integrated Circuit (IC) devices that are created over Semiconductor-On-Insulator (SOI) surfaces have significant performance advantages such as reduced parasitic capacitances, reduced power consumption, increased resistance against radiation, increased ability to operate at more elevated temperatures, operational capabilities at higher applied voltages, multi-layer device integration and, for CMOS devices, increased freedom from latch-up of the operational devices. It is common practice in the creation of SOI devices, whereby the semiconductor is the upper layer, to create active surface regions by creating isolation trenches through the semiconductor layer down to the isolation layer, whereby the sidewalls of such trenches are covered with an insulation material such as silicon dioxide, silicon nitride, silicon oxynitride, CVD oxide, and the like.  
           [0003]    One of the methods that is applied in the semiconductor technology for the extension of the crystalline nature of the silicon substrate is to grow a layer of epitaxy over the surface of the silicon substrate. The epitaxial layer, comprised of silicon, can be formed by conventional deposition techniques of contacting the substrate with a flow of gas (e.g. silicon tetrachloride) at an elevated temperature, the epitaxial layer can for instance include a N-well region and a P-well region previously created in the surface of a silicon substrate. Such an epitaxial layer may advantageously be grown because it may provide lower impurity concentrations and may even be of a different semiconductor type as the wafer over which it is grown. Semiconductor devices are in this case created in the active layer of the stack, which is typically only about a micron thick.  
           [0004]    One of the more serious drawbacks of the use of epitaxial layers is that such a layer typically adopts the crystalline structure of the substrate over which the layer is created. In most applications, the underlying substrate is a monocrystalline substrate having a particular crystallographic orientation, thus potentially causing a conflict between a desired crystallographic orientation of the epitaxial layer and the crystallographic orientation of the substrate over which the epitaxial layer is grown. Additionally, successful creation of an epitaxial layer over a surface requires extreme preparation of the conditions of cleanliness of this surface in order to avoid the occurrence of undesirable crystalline defects (such as “pipes” and “spikes”) in the interface between the overlying layers. These and other considerations, which become more of a problem for semiconductor devices of increased complexity and increased surface area over which the devices are created, leads to the requirement of creating overlying surfaces of a crystalline nature that can be used for the creation of semiconductor devices.  
           [0005]    It is well known in the art that the creation of semiconductor devices conventionally starts with a monocrystalline silicon substrate having &lt;100&gt; plane orientation. Other plane orientations of the cubic crystals that form the silicon substrate, such as &lt;110&gt; and &lt;111&gt;, are also well known but are, for considerations of device performance and wafer dicing, less frequently used. The invention provides a method that makes available a bonded SOI wafer with a &lt;100&gt; layer for the creation of active devices and a &lt;110&gt; substrate layer for performance improvements. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    [0006]FIGS. 1 through 3 show top views and a cross section relating to the first embodiment of the invention, a first silicon substrate having a &lt;100&gt; crystallographic orientation is bonded to the surface of a second silicon substrate having a &lt;110&gt; crystallographic orientation, the wafer alignment notches of the first and the second silicon substrates are aligned with each other.  
         [0007]    [0007]FIGS. 4 through 6 shows top views and a cross section relating to the second embodiment of the invention, a first silicon substrate having a &lt;100&gt; crystallographic orientation is bonded to the surface of a second silicon substrate having a &lt;110&gt; crystallographic orientation, the wafer alignment notches of the first and the second silicon substrates are not aligned with each other. 
     
    
     DESCRIPTION  
       [0008]    Referring now specifically to FIG. 1, there is shown of top view of wafer  10 , having &lt;100&gt; crystallographic orientation and having a wafer  10  alignment notch  14 . Also shown in FIG. 1 is wafer  12 , in this case having &lt;110&gt; crystallographic orientation and having a wafer  12  alignment notch  16 . The two wafers that are shown in top view of FIG. 1 are, FIG. 2, aligned with each other with wafer  10  being positioned above the surface of wafer  12 . Prior to this alignment of the two wafers  10  and  12 , a layer  18  of hydrogen based material has been deposited over the surface of wafer  12 .  
         [0009]    After the alignment of the two wafers  10  and  12  has been performed as shown in the cross section of FIG. 2, the two wafers are via motion  20  brought in physical contact with each other and are bonded together, whereby the lower surface of wafer  10  overlies the surface of the layer  18  of a hydrogen based material.  
         [0010]    The bonding of the two substrates  10  and  12  is accomplished by:  
         [0011]    1. Polishing the surface of the substrate where these surfaces interface.  
         [0012]    2. Making the polishing surface of the substrate hydrophilic by creating layer  18  over the surface of substrate  12 .  
         [0013]    3. Heating the two wafers  10  and  12  for a time between about 30 seconds and 3 minutes, at a temperature between about 800 and 1,400 degrees C., forming hydrogen bonds in the interface between substrates  10  and  12 .  
         [0014]    As examples, hydrogen based layer  18  can consist of:  
         [0015]    silicon oxide, containing monosilane (SiH 4 ) and nitrous oxide (N 2 O)  
         [0016]    silicon nitride, containing monosilane (SiH 4 ) and ammonia (NH 3 ), and  
         [0017]    silicon oxynitride, containing monosilance (SiH 4 ), ammonia (NH 3 ) and nitrous oxide (N 2 O).  
         [0018]    From the cross section of the two wafers  10  and  12  that is shown in FIG. 2, it is clear that the wafer alignment notches  14  (wafer  10 ) and  16  (wafer  12 ) are aligned with each other, that is wafer alignment notch  14  is aligned with (overlies) wafer alignment notch  16 .  
         [0019]    Proceeding to the top view of wafers  10  and  12  that is shown in FIG. 3, the alignment of wafer alignment notches is more clear in this top view while, as an example of the advantageous use of the upper silicon substrate  10 , the creation of a CMOS device over the surface of this wafer  10  has been highlighted with the gate electrode  22  and the therewith self-aligned source impurity implantation  24  and drain impurity implantation  26 , both impurity implantations having been performed in the exposed surface of the upper wafer  10  of &lt;100&gt; crystallographic orientation.  
         [0020]    Conventional semiconductor device advantages of using a silicon surface of &lt;100&gt; crystallographic orientation, such as hole mobility and improved immunity to the short channel effect of the gate electrode  22 , are in this manner retained. By adding the lower wafer  12  to the thus created wafer stack, dicing of the created semiconductor devices, created in the exposed surface of wafer  10 , can be readily performed.  
         [0021]    Proceeding with the second embodiment of the invention, FIG. 4 shows of top view of wafer  30 , having &lt;100&gt; crystallographic orientation and having a wafer  30  alignment notch  34 . Also shown in FIG. 4 is wafer  32 , in this case having &lt;110&gt; crystallographic orientation and having a wafer  32  alignment notch  36 .  
         [0022]    In the top view of the two wafers  30  and  32  that is shown in FIG. 4 is further highlighted the wafer alignment notch  36 ′ which is the relative position of the wafer alignment notch  36  of wafer  32  with respect to the wafer alignment notch  34  of wafer  30 . Alignment notch  36 ′ as shown in FIG. 4 is therefore not an actual alignment notch but only an indication of the relative positioning of alignment notches  34  and  36 .  
         [0023]    The two wafers that are shown in top view in FIG. 4 are, FIG. 5, aligned with each other with wafer  30  being positioned above the surface of wafer  32 . Prior to this alignment of the two wafers  30  and  32 , a layer  38 , preferably comprising of a hydrogen based material, has been deposited over the surface of wafer  32 .  
         [0024]    As examples, hydrogen based layer  38  can consist of:  
         [0025]    silicon oxide, containing monosilane (SiH 4 ) and nitrous oxide (N 2 O)  
         [0026]    silicon nitride, containing monosilane (SiH 4 ) and ammonia (NH 3 ), and  
         [0027]    silicon oxynitride, containing monosilane (SiH 4 ), ammonia (NH 3 ) and nitrous oxide (N 2 O).  
         [0028]    After the alignment of the two wafers  30  and  32  has been performed as shown in the cross section of FIG. 5, the two wafers are via motion  40  brought in physical contact with each other and are bonded together, whereby the lower surface of wafer  30  overlies the surface of the layer  38  of hydrogen based material.  
         [0029]    The bonding of the two substrates  30  and  32  is accomplished by:  
         [0030]    1. Polishing the surface of the substrate where these surfaces interface.  
         [0031]    2. Making the polishing surface of the substrate hydrophilic by creating layer  38  over the surface of substrate  32 .  
         [0032]    3. Heating the two wafers  30  and  32  for a time between about 30 seconds and 3 minutes, at a temperature between about 800 and 1,400 degrees C., forming hydrogen bonds in the interface between substrates  30  and  32 .  
         [0033]    From the cross section of the two wafers  30  and  32  that is shown in FIG. 5, it is clear that the wafer alignment notches  34  (wafer  30  and not visible) and  36  (wafer  32  and visible) are not aligned with each other, that is wafer alignment notch  34  is not aligned with (does not overly) wafer alignment notch  36 .  
         [0034]    Proceeding to the top view of wafers  30  and  32  that is shown in FIG. 6, the alignment of wafer alignment notches is more clear in this top view while, as an exampled of the advantageous use of the upper silicon substrate, the creation of a CMOS device over the surface of this wafer  30  has been highlighted with the gate electrode  42  and the therewith self-aligned source impurity implantation  44  and drain impurity implantation  46 , both impurity implantations having been performed in the exposed surface of the upper wafer  30  of &lt;100&gt; crystallographic orientation.  
         [0035]    Conventional semiconductor device advantages of using a silicon surface of &lt;100&gt; crystallographic orientation, such as hole mobility and improved immunity to the short channel effect of the gate electrode  42 , are in this manner retained. By adding the wafer  32  to the thus created wafer stack, dicing of the created semiconductor devices, created in the exposed surface of wafer  30 , can be readily performed.  
         [0036]    Although the description herein focuses on the &lt;100&gt; and &lt;110&gt; crystalline orientations, substrates of other crystalline orientations may also be used. Also note that the polished surface of the substrate may be made hydrophilic by the application of suitable materials other than or in addition to a hydrogen-based material.  
         [0037]    Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.