Abstract:
A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.

Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates generally to a method of manufacturing semiconductor devices and, more particularly, to semiconductor devices and a method of manufacturing the same, in which a self-aligned electron trap film capable of securing a right and left-symmetrical type ONO film length can be formed.  
         [0003]     2. Discussion of Related Art  
         [0004]     In recent years, silicon-oxide-nitride-oxide-silicon (SONOS) type flash memory devices have been developed along with the development of flash memory devices. The SONOS type flash memory device is advantageous in that it can be easily fabricated and can be easily integrated with the peripheral region of such a device.  
         [0005]     In the existing SONOS type flash memory device, an oxide-nitride-oxide (ONO) film (i.e., a dielectric film) exists entirely on a channel region. This thickens a gate oxide film formed on the ONO film. As a result, the SONOS type flash memory device has a high threshold voltage (Vt), and high power consumption and a high program voltage corresponding to the high threshold voltage.  
         [0006]     Furthermore, electrons trapped at the silicon nitride film are moved in a horizontal direction in the silicon nitride film. Accordingly, the erase operation is not fully performed, and the erase rate is lengthened. On the other hand, as the program and erase operations are repeatedly performed, an initial threshold voltage (Vt) of an erased cell is increased. This can lower not only the cell current and the read speed, but also the data retention time.  
         [0007]     To solve the problems, there has been proposed local SONOS type (i.e., electron trap film) flash memory devices in which the silicon nitride film is locally overlapped with the gate electrode. A gate formation method of the local SONOS type flash memory device will be described below with reference to  FIGS. 1A  to  1 D.  
         [0008]     Referring to  FIG. 1A , an ONO film  11  (i.e., a dielectric film) is formed on a semiconductor substrate  10 . The ONO film  11  is selectively etched by an etch process employing a mask.  
         [0009]     Referring to  FIG. 1B , a gate oxide film  12  and a polysilicon film  13  are formed on the entire structure.  
         [0010]     Referring to  FIG. 1C , a photoresist pattern  14  is formed on the entire structure. The photoresist pattern  14  may be misaligned.  
         [0011]     Referring to  FIG. 1D , the polysilicon film  13 , the gate oxide film  12 , and the ONO film  1   1  are etched using the photoresist pattern  14  as a mask, forming a gate  15 .  
         [0012]     If the gate is formed as described above, there occurs a phenomenon in which the length of the ONO film of a region A is asymmetrical to the length of the ONO film of a region B in the gate  15  due to the misaligned photoresist pattern  14 , as shown in  FIG. 1 C . The length of the ONO film influences the erase rate, the erase efficiency, and the initial threshold voltage (Vt) of the flash memory device. If the length of the ONO film varies depending on a cell of a memory device, respective cells have different threshold voltages (Vt) and different erase rates.  
         [0013]     Accordingly, problems arise because the uniformity within the entire wafer is lowered and the threshold voltage (Vt) is severely changed.  
       SUMMARY OF THE INVENTION  
       [0014]     In one embodiment, the invention provides a semiconductor device and a method of manufacturing the same, in which a self-aligned electron trap film in which the lengths of a dielectric film are symmetrical to each other right and left in a gate is formed, thus preventing misalignment by a mask process.  
         [0015]     A semiconductor device according to one embodiment of the invention includes a gate oxide film formed on a semiconductor substrate; a third gate electrode formed on the gate oxide film; the whole surface of the third gate electrode other than a top surface being covered with the gate oxide film; first and second dielectric films formed on the semiconductor substrate at both sides of the gate oxide film; first and second gate electrodes which are formed on the first and second dielectric films, respectively, and have a height higher than the third gate electrode; and, a fourth gate electrode which is formed on the gate oxide film and the third gate electrode between the first and second gate electrodes and are electrically connected to the first, second, and third gate electrodes.  
         [0016]     According to one embodiment, the invention provides a method of manufacturing a semiconductor device, including the steps of forming a dielectric film on a semiconductor substrate and stripping the dielectric film of a predetermined region; forming an interlayer insulating film on the region from which a portion of the dielectric film has been stripped; forming a first conductive film on the entire structure, and blank etching the first conductive film to form first and second gate electrodes, which are insulated from the semiconductor substrate through the dielectric film, on sidewalls of the interlayer insulating film; stripping the dielectric film exposed between the first and second gate electrodes; forming an oxide film and a second conductive film on the entire structure, and then performing a blanket etch process to form a third gate electrode, which is insulated from the semiconductor substrate and the first and second gate electrodes by means of the oxide film between the first and second gate electrodes; forming a third conductive film on the entire structure, and then performing a blanket etch process to form a fourth gate electrode connected to the first, second, and third gate electrodes; and stripping the interlayer insulating film and then forming a source and drain at given regions of the semiconductor substrate. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     A more compete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:  
         [0018]      FIGS. 1A  to  1 D are cross-sectional views illustrating a method of manufacturing a semiconductor device in the related art; and  
         [0019]      FIGS. 2A  to  2 I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0020]     The invention will now be described in detail in connection with certain exemplary embodiments with reference to the accompanying drawings.  
         [0021]      FIGS. 2A  to  2 I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.  
         [0022]     Referring to  FIG. 2A , an ONO film including a first oxide film  102  as a dielectric film, a first nitride film  104 , and a second oxide film  106  is formed on a semiconductor substrate  100 . The second oxide film  106  may preferably be formed to a thickness of 50 Å to 200 Å by means of a low-pressure chemical vapor deposition (LP-CVD) method or a plasma-enhanced chemical vapor deposition (PE-CVD method. The second oxide film  106  is not used as a material of the ONO film since it is stripped in a subsequent process.  
         [0023]     A second nitride film  108  is formed on the ONO film. The second nitride film  108  may preferably be formed to a thickness of 2000 Å to 5000 Å. A photoresist pattern  110  is formed on the second nitride film  108 .  
         [0024]     Referring to  FIG. 2B , the second nitride film  108  is etched by an etch process using the photoresist pattern  110  as a mask. The exposed second oxide film  106  is stripped. The second nitride film  108  may preferably be etched by a dry etch method.  
         [0025]     Referring to  FIG. 2C , an interlayer insulating film  112  is formed on the entire structure. The interlayer insulating film  112  is polished until a top surface of the second nitride film  108  is exposed. The interlayer insulating film  112  is formed using an oxide film or a SiO x N y -based material having a fine structure since it is used as a polishing barrier or an etch barrier.  
         [0026]     Meanwhile, to form the interlayer insulating film  112  and secure polishing process margin, the second nitride film  108  may be formed to a sufficient thickness.  
         [0027]     Referring to  FIG. 2D , the second nitride film  108  is stripped, preferably using wet etch employing H 3 PO 4 . The second oxide film  106  serves to protect the first nitride film  104  during the wet etch process employing H 3 PO 4 . A cleaning process is performed to strip the second oxide film  106 . A third oxide film  114  is formed on the entire structure. The third oxide film  114  is used as the second oxide film of the ONO film.  
         [0028]     A cleaning process preferably employing a BF or BOE solution is performed to strip a native oxide film. A first conductive film  116  is then formed on the entire structure. The first conductive film  116  preferably may be formed using a doped polysilicon film, or Al, W, WSi x , CoSi x , WN x , TiSi x , Ti, Ta, TaN, Ru, Pt, or a mixture thereof. The first conductive film  116  may be deposited to have a thickness of ⅕ to ½ of a width of a buried region so that a portion of the buried region can be buried.  
         [0029]     Referring to  FIG. 2E , the first conductive film  116  is etched to form first and second gate electrodes  116 A and  116 B of a spacer shape on the sidewalls of the third oxide film  114 . The ONO film between the first gate electrode  116 A and the second gate electrode  116 B is etched partially or entirely, thereby forming a hole  200 .  
         [0030]     Referring to  FIG. 2F , films remaining on the semiconductor substrate  100  between the first gate electrode  116 A and the second gate electrode  116 B (for example, the first oxide film  102  and the first nitride film  104 ) are all stripped. A gate oxide film  118  is formed on the entire structure. The gate oxide film  118  may preferably be formed by a LP-CVD method.  
         [0031]     A cleaning process employing a BF or BOE solution is performed to strip a native oxide film. A second conductive film  120  is then formed on the entire structure. The second conductive film  120  may preferably be formed using a doped polysilicon film, or Al, W, WSi x , CoSi x , WN x , TiSi x , Ti, Ta, TaN, Ru, Pt, or a mixture thereof. Furthermore, the second conductive film  120  may preferably be formed to a thickness of 500 Å to 5000 Å.  
         [0032]     Furthermore, in the case where the second conductive film  120  is formed, the inlet of the hole  200  has a positive slope and can be therefore buried without voids.  
         [0033]     Referring to  FIG. 2G , the second conductive film  120  is etched back to form a third gate electrode  120 A having a height lower than that of the first and second gate electrodes  116 A and  116 B. A cleaning process is performed to strip the gate oxide film  118  existing the interlayer insulating film  112 , and the first, second, and third gate electrodes  116 A,  116 B and  120 A.  
         [0034]     A third conductive film  122  is then formed on the entire structure. The third conductive film  122  may preferably be formed using a doped polysilicon film, or Al, W, WSi x , CoSi x , WN x , TiSi x , Ti, Ta, TaN, Ru, Pt, or a mixture thereof.  
         [0035]     Referring to  FIG. 2H , the third conductive film  122  is polished until a top surface of the interlayer insulating film  112  is exposed, thus forming a fourth gate electrode  122 A. The interlayer insulating film  112  is stripped by wet etch. When the interlayer insulating film  112  is stripped, the third oxide film  114  and the first nitride film  104  formed on the sidewalls of the first and second gate electrodes  116 A and  116 B are stripped.  
         [0036]     Referring to  FIG. 21 , an ion implantation process is performed to form a source and drain  300 . Insulating film spacers  124  made of an oxide film or a nitride film are formed on the sidewalls of the first and second gate electrodes  116 A and  116 B.  
         [0037]     In the semiconductor device according to one embodiment of the invention, the gate oxide film is formed on the semiconductor substrate. The third gate electrode is formed on the gate oxide film so that the whole surface of the gate oxide film other than the top surface thereof is covered with the gate oxide film.  
         [0038]     The first and second dielectric films are formed on the semiconductor substrate at both sides of the gate oxide film. The first and second gate electrodes are formed on the first and second dielectric films, respectively so that they are higher than the third gate electrode. The fourth gate electrode is formed on the gate oxide film and the third gate electrode between the first and second gate electrode, so that they are electrically connected to the first, second, and third gate electrodes.  
         [0039]     As described above, according to the invention, the first gate electrode of the spacer shape is formed on an inner surface of the space. In the event that the second conductive film is to be formed, it can be buried without void due to a positive slope.  
         [0040]     Furthermore, the dielectric film is formed in a self-aligned manner by the first gate electrode of the spacer shape without an additional mask process. It is therefore possible to prevent irregular cell configuration due to a misalignment problem incurred by a mask process.  
         [0041]     While the invention has been described in connection with practical exemplary embodiments, the invention is not limited to the disclosed embodiments, but, to the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.