Abstract:
Known chip equalizers for Wideband-Code Division Multiple Access (W-CDMA) employ a co-efficient calculator that implements a Minimum Mean Square Error (MMSE) solution to a least squares technique for obtaining equalizer coefficients in response to receipt of a pilot sequence. However, this solution results in an undesirably high processing overhead in downlink receivers operating in a W-CDMA communications system. Consequently, the present invention provides a computationally simpler technique to calculate equalizer coefficients by implementing a minimum-norm solution to the least squares problem.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to an apparatus for generating equalizer coefficients of the type, for example, used by receivers in spread spectrum communications systems, such as a Wideband-Code Division Multiple Access communications system. The present invention also relates to a method of generating the equalizer coefficients.  
         [0002]     In the field of wireless communications, spread-spectrum communications systems, such as Code Division Multiple Access (CDMA) systems, are widely deployed in a number of communications applications. In particular, a variant of CDMA, known as Wideband-CDMA (W-CDMA), is employed in the third generation (3G) Universal Mobile Telecommunications System (UMTS).  
         [0003]     In the UMTS, downlink receivers comprising an equalizer coupled to a de-spreader are known. For such receivers, an input of the equalizer is coupled to a source of chips, the source of chips also being coupled to a coefficient calculation unit. An output of the coefficient calculation unit is coupled to another input of the equalizer in order to set coefficients of the equalizer. An output of the equalizer is, of course, coupled to an input of the de-spreader.  
         [0004]     Currently, terminals capable of operating in the UMTS are equipped with so-called “RAKE” receivers that comprise, as the coefficient calculation unit, an array of initial de-spreader “blocks” coupled to respective conjugator “blocks”. However, a traditional RAKE receiver cannot provide adequate performance in the presence of severe Multiple Access Interference (MAI) and Inter-Symbol Interference (ISI).  
         [0005]     The demand for enhanced CDMA downlink performance is constantly growing, particularly to support the forthcoming High Speed Data Packet Access (HSDPA) standard. Consequently, one known candidates to replace the RAKE receiver is a linear chip equalizer.  
         [0006]     In this respect, “Data detection algorithms specifically designed for the downlink of CDMA mobile radio systems” (A. Klein,  Proc. IEEE VTC,  vol. 1, pp. 203-7, May 1997) discloses linear Zero-Forcing (ZF) and Minimum-Mean-Squared-Error (MMSE) equalizers for a CDMA downlink. In particular, this document discloses a symbol-level solution to the problem of optimization of a mean-squared-error for a de-spread user symbol.  
         [0007]     A simpler approach is to consider a composite chip sequence, which is a sum of spread signals of all users in a cell, and solving ZF and MMSE problems at a chip level, as described in “Linear receiver for the DS-CDMA downlink exploiting orthogonality of spreading sequences” (I. Ghauri and D. T. M. Slock, Proc. 32nd Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, Calif., Nov. 1998), “Multiple access interference suppression with linear chip equalizes in WCDMA downlink receivers” (K. Hooli, M. Latva-aho and M. Juntti, Proc. IEEE Int. Global Comm. GLOBECOM, &#39;99, Rio de Janeiro, Brazil, December 1999, pp. 467-471), and “Simple MMSE equalizers for CDMA downlink to restore chip sequence: comparison to zero-forcing and RAKE” (T. P. Krauss, M. D. Zoltowski and G. Leus, Proc. ICASSP, vol. 5, Istanbul, Turkey, June 2000, pp. 2865-2868). Indeed, as disclosed in this latter document, a fairly simple solution can be obtained if a composite chip sequence is assumed to be independent and identically distributed. In such a case, no spreading/scrambling code information is needed and the coefficients of the linear equalizer are found using the channel response and the noise variance only. However, in reality the channel response is not known in a receiver, and so the most common approach is to use a training sequence for channel estimation and computation of equalizer coefficients. In this respect and in relation to the UMTS W-CDMA standard, a code-multiplexed pilot signal is used for the purpose of providing the training sequence either in block based or adaptive equalizer configuration, as is described in “Pilot-aided adaptive chip equalizer receiver for interference suppression in DS-CDMA forward link” (F. Petre, M. Moonen, M. Engels, B. Gyselinckx and H. De Man, Proc. IEEE VTC-Fall 2000, 2000, pp. 303-308.), “Semi-blind space-time chip equalizer receivers for WCDMA forward link with code-multiplexed pilot”, Proc. Int. Conf. ASSP, Salt Lake City, Utah, May 2001, pp. 2245-2248), and “Adaptive chip-equalizers for synchronous DS-CDMA systems with pilot sequences”, GLOBECOM &#39;01, Vol. 6, pages 25 to 29, November 2001).  
         [0008]     However, the above examples of linear equalizers are processing intensive and so result in significantly more complex apparatus than the traditional RAKE receivers in order to achieve the required improvement in performance over the RAKE receivers. Consequently, such equalizers are relatively expensive to produce as compared with RAKE receivers.  
       STATEMENT OF INVENTION  
       [0009]     The present invention provides an apparatus for generating a coefficient for an equalizer, a spread-spectrum receiver, a communications system, a method of generating a coefficient for an equalizer and a computer program element as described in the accompanying claims.  
         [0010]     It is thus possible to provide a method and apparatus for calculating an equalizer coefficient that employs a solution for an underdetermined least squares problem that needs to be solved to calculate the equalizer coefficient. Consequently, calculation of correlation between symbols is needed. It is therefore possible to vary the number of symbols used in the correlation calculation so as to provide a trade-off between computation complexity and performance of a receiver. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     At least one embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings:  
         [0012]      FIG. 1  is a schematic diagram of a downlink receiver;  
         [0013]      FIG. 2  is a schematic diagram of correlation between symbols of time-delayed streams of de-spread symbols constituting an embodiment of the invention;  
         [0014]      FIG. 3  is a flow diagram for use with the apparatus of  FIGS. 1 and 2 ; and  
         [0015]      FIG. 4  is a schematic diagram of an apparatus for calculating a coefficient of an equalizer constituting another embodiment of the invention. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0016]     In a Wideband-Code Division Multiple Access communications system, for example a Universal Mobile Telecommunications System (UMTS), at least one node B (not shown) is capable of communicating with a User Equipment (UE), for example a mobile subscriber handset (not shown).  
         [0017]     As much of the UE does not relate directly to the invention, for the sake of clarity and ease of understanding, the following part of this description will be confined to a downlink receiver of the UE.  
         [0018]     Referring to  FIG. 1 , the downlink receiver  100  comprises an equalizer  102  having a first input  104  and an output  106 . The first input  104  of the equalizer  102  is coupled to, in this example, an analog-to-digital converter (not shown) of the receiver that provides samples of received chips, and an input  108  of a coefficient calculation entity  110 . An output  112  of the coefficient calculation entity  110  is coupled to a second input  114  of the equalizer  102 . The output  106  of the equalizer  102  is coupled to an input  116  of a de-spreader unit  118 .  
         [0019]     By using a predetermined sequence of pilot symbols, expressed as a vector of pilot symbols {overscore (p)}, corresponding to a vector of received pilot chips, {overscore (y)}, the coefficient calculation unit  110  solves a least squares minimization problem of the form of the following equation in order to determine an equalizer coefficient vector, {overscore (f)}: 
 
 C   p   H   Y{overscore (f)}={overscore (p)}   (1)
 
 where: C p   H Y is a matrix of received symbols corresponding to the pilot symbols, Y being a Toeplitz convolution matrix based upon the vector of received pilot chips, {overscore (y)}, and C p   H  being a Hermitian matrix of a pilot spreading code. 
 
         [0020]     Referring to  FIGS. 2 and 3 , received signal data corresponding to the matrix of received symbols C p   H Y is generated by providing a plurality de-spreaders  200  for a respective plurality of time-delayed taps (not shown), the plurality of de-spreaders  200  being respectively coupled to a plurality of conjugator blocks  202  (Step  300 ). The plurality of time-delayed de-spreaders  200  therefore correspond to, for example, a first delay  11 , a second delay  12 , a third delay  13 , and a fourth delay  14 ; the time delays used can be any suitable set of time delays, including a time delay of zero. The plurality of time-delayed de-spreaders  200  in combination with the conjugator blocks  202  generate respective streams of de-spread chips, or symbols  204 , that constitute the received signal data corresponding to the matrix of received symbols C p   H Y.  
         [0021]     The coefficient calculation unit  110  then generates (Step  302 ) a correlation matrix C p   H YY H C p , hereinafter referred to as the correlation matrix R, and an inverse (Step  304 ) of the correlation matrix (C p   H YY H C p ) −1 .  
         [0022]     The product of the inverted correlation matrix, R −1 , and the vector of the predetermined sequence pilot symbols, {overscore (p)}, is then calculated (Step  306 ). A further correlation of each of the plurality of time-delayed streams of symbols  204  with the product, R −1 {overscore (p)}, is then calculated (Step  308 ) to obtain the solution to equation (1) above and hence equalizer coefficient vector {overscore (f)}.  
         [0023]     The above described steps correspond to a solution to the least squares minimization problem of equation (1). However, whereas known techniques for solving equation (1) compute equalizer coefficients by finding a minimum mean squared error solution to an over-determined case of the least squares problem, the above steps correspond to an underdetermined case of the least squares minimization problem, a minimum-norm solution to the least squares minimization problem being employed to determine the equalize coefficient vector, {overscore (f)}. Consequently, correlation between symbols of the plurality of time-delayed streams of symbols is calculated instead of correlation between so-called “fingers” or each of the plurality of time-delayed streams of symbols  204 . Hence, the equalizer coefficient vector, {overscore (f)}, can be expressed as: 
 
 {overscore (f)}=Y   H   C ( C   H   YY   H   C ) −1   {overscore (p)}   (2)
 
         [0024]     Determination of the equalizer coefficient vector, {overscore (f)}, in this way requires correlation between a first set of time-delayed symbols  206  spanning a number of the plurality of streams of symbols  204  and a second set of time-delayed symbols  208  spanning the number of the plurality of streams of symbols  204 . In this respect, each symbol of the first set of symbols  206  respectively correspond to a like position within the number of the plurality of streams  204 . Similarly, each symbol of the second set  208  of symbols respectively corresponds to a like position within the number of the plurality of streams  204 . The correlation between symbols can be expressed as:  
               〈       s   k     ,     s   m       〉     =       ∑   l     ⁢       s     k   ,   l       ⁢     s     m   ,   l     *                 (   3   )             
 
         [0025]     Consequently, the number of symbols used to calculate the correlation can be varied. Therefore, whilst a matrix representation for the correlation matrix, R, is:  
                 C   p   H     ⁢     YY   H     ⁢     C   p       =     (           〈       s   1     ,     s   1       〉           〈     s   ,     s   2       〉         …         〈       s   1     ,     s   B       〉               〈       s   2     ,     s   1       〉           〈       s   2     ,     s   2       〉                                     ⋮                                                 〈       s   B     ,     s   1       〉                                               )             (   4   )             
 
 where B is the size of a block of symbols used for the calculation of the correlation between the symbols, the size of the block of symbols B can be selected depending upon the performance and processing complexity requirement of the receiver. 
 
         [0026]     Clearly, any non-trivial size of the block of symbols, i.e. not a block containing a single symbol as this corresponds to a RAKE solution, can be employed, but the larger the size of the block, the more the processing complexity approaches that of existing MMSE-based equalizer coefficient calculation units  110 .  
         [0027]     Taking B=2 as an exemplary block size, an expression for the inverse of correlation matrix, R, is given as:  
                 C   p   H     ⁢     YY   H     ⁢     C   p       ∝     (             〈       s   1     ,     s   2       〉     ⁢                 -     〈       s   1     ,     s   2       〉       ⁢                     -     〈       s   2     ,     s   1       〉       ⁢                 〈       s   2     ,     s   1       〉     ⁢               )             (   5   )             
 
         [0028]     By substituting equation (4) into equation (2) above, an expression for an equalizer coefficient, f 1 , is obtained for a given time delay,  1 : 
 
 f   1   ∝[s   1,1   *   s   2   , s   2   −s   2,1   *   s   2   , s   1   ]p   1   −[s   2,1   *   s   1   , s   1   −s   1,1   *   s   1   , s   2   ]p   2   (6)
 
         [0029]     Further, equation (5) can be simplified, because for W-CDMA the first and second pilot symbols of the pilot sequence, {overscore (p)}, are identical, and so equation (5) becomes: 
 
 f   1   ∝s   1,1   *   s   2   −s   1   , s   2   +s   2,1   *   s   1   −s   2   , s   1       (7)
 
         [0030]     From equation (6), it can be seen that a matrix version of the expression for the equalizer coefficient, f 1 , is not required.  
         [0031]     Referring to  FIG. 4 , the coefficient calculator unit  110  supports a plurality of coefficient calculation fingers, each coefficient calculation finger  400  corresponding to a respective time delay,  1 , and being coupled to a common processing arrangement  401 . Each coefficient calculation finger  400  comprises a de-spreader  402  for the respective time delay,  1 , the de-spreader  402  having an input  404  for receiving a time-delayed stream of chips, y 1 . Although not shown, the delay to the stream of chips can be provided by the use of a time-delay tap known in the art. An output  406  of the de-spreader  402  is coupled to an input  408  of a serial-to-parallel converter  410 . A first output  412  of the serial-to-parallel converter  410  is coupled to an input  414  of a first complex conjugator  416 . The first output  412  of the serial-to-parallel converter  410  is also coupled to a first input  418  of a first multiplication unit  420  and a first input  422  of a subtraction unit  424 .  
         [0032]     A second output  426  of the serial-to-parallel converter  410  is coupled to an input  428  of a second complex conjugator  430 , as well as a first input  432  of a second multiplication unit  434  and a second input  436  of the subtraction unit  424 . An output  438  of the subtraction unit  424  is coupled to a second input  440  of the first multiplication unit  420  and a second input  442  of the second multiplication unit  434 .  
         [0033]     With respect to the common processing arrangement  401 , an output  444  of the first multiplication unit  420  is coupled to an input  446  of a first shared summation unit  448 , the first shared summation unit  448  being coupled to other first multiplication units (not shown) of other coefficient calculation fingers (not shown) included in the coefficient calculation unit  110 . Similarly, an output  450  of the second multiplication unit  434  is coupled to an input  452  of a second shared summation unit  454 , the second shared summation unit  454  being coupled to other second multiplication units (not shown) of other coefficient calculation fingers (not shown) included in the coefficient calculation unit  110 .  
         [0034]     An output  456  of the first shared summation unit  448  is coupled to a first input  458  of a first shared multiplication unit  460 , an output  462  of the first complex conjugator  416  being coupled to a second input  464  of the first shared multiplication unit  460 . Similarly, an output  466  of the second shared summation unit  454  is coupled to a first input  468  of a second shared multiplication unit  470 , an output  472  of the second complex conjugator  430  being coupled to a second input  474  of the second shared multiplication unit  470 .  
         [0035]     An output  476  of the first shared multiplication unit  460  is coupled to an inverting input  478  of a final summation unit  480 . An output  482  of the second shared multiplication unit  470  is coupled to a non-inverting input  484  of the final summation unit  480 . An output  482  of the final summation unit  480  is coupled to the second input  114  of the equalizer  102 .  
         [0036]     In operation, a stream of chips {overscore (y)} 1  are received by de-spreader  402  at the input  404  of the de-spreader  402 , the stream of chips being delayed by the time delay,  1 . The de-spreader  402  processes the received stream of chips {overscore (y)} 1 , and generates a corresponding stream of symbols, {overscore (s)} 1 , the stream of symbols also being delayed by the time delay,  1 .  
         [0037]     Thereafter, the stream of symbols, {overscore (s)} 1 , is processed in pairs of symbols. For example, a first pair of time-delayed symbols s 1,1 , s 2,1  comprising a first symbol s 1,1  and a second symbol s 2,1  are directed onto separate paths by the serial-to-parallel converter  410 , the first symbol s 1,1  being provided at the first output  412  of the serial-to-parallel converter  410  and the second symbol s 2,1  being provided at the second output  426  of the serial-to-parallel converter  410 . Consequently, the first complex conjugator  416 , the first multiplication unit  420 , and the subtraction unit  424  each receive the first symbol s 1,1 . Similarly, the second complex conjugator  430 , the second multiplication unit  434  and the subtraction unit  424  each receive the second symbol s 2,1 .  
         [0038]     As a result of receiving the first and second symbols s 1,1 , s 2,1  the subtraction unit  424  calculates the difference of the first and second symbols solo s 1,1 , s 2,1  (s 1,1 -s 2,1 ) and provides the difference result at the output  438  of the subtraction unit  424 . The difference result generated by the subtraction unit  424  is received by the first and second multiplication units  420 ,  434 , whereupon the first multiplication unit  420  calculates a first product (s 1,1 (s 1,1 -s 2,1 )) of the difference result of the subtraction unit  424  and the first symbol s 1,1  provided by the serial-to-parallel converter  410 . Similarly, the second multiplication unit  434  calculates a second product (s 2,1 (s 1,1 -s 2,1 )) of the difference result of the subtraction unit  424  and the second symbol s 2,1  provided by the serial-to-parallel converter  410 .  
         [0039]     The output  444  of the first multiplication unit  420  then provides the first product (s 1,1 (s 1,1 -s 2,1 )) calculated by the first multiplication unit  420  to the first shared summation unit  448 . Similarly, the second multiplication unit  434  provides the second product (s 2,1 (s 1,1 -s 2,1 )) calculated by the second multiplication unit  434  to the second shared summation unit  454 .  
         [0040]     The first and second shared summation units  448 ,  454  also receive product calculations  485 ,  486  generated by first and second multiplication units (not shown) of other calculation fingers, respectively, in respect of other streams of time-delayed chips.  
         [0041]     Thereafter, the respective sums calculated by the first shared summation unit  448  and the second shared summation unit  454  of all the products calculated by the first and second multiplication units of the coefficient calculation unit  110  are respectively received by the first shared multiplication unit  460  and the second shared multiplication unit  470 . The first shared multiplication unit  460  calculates a product of the sum generated by the first shared summation unit  448  and the complex conjugate of the first symbol s 1,1  generated by the first complex conjugator  416 . Similarly, the second shared multiplication unit  470  calculates a product of the sum generated by the second shared summation unit  454  and the complex conjugate of the second symbol s 2,1  generated by the second complex conjugator  430 . Subsequently, the products calculated by the first and second shared multiplication units  460 ,  470  are summed by the final summation unit  480  to yield the equalizer coefficient f 1  for the time delay,  1 .  
         [0042]     It should be appreciated that the arrangement described above in relation to  FIG. 4  is an exemplary arrangement to support the equation (6) above. Consequently, it should be understood that other, more complex, arrangements can be realised to support more complex minimum-norm solutions to the least squares problem described above.  
         [0043]     Alternative embodiments of the invention can be implemented as a computer program product for use with a computer system, the computer program product being, for example, a series of computer instructions stored on a tangible data recording medium, such as a diskette, CD-ROM, ROM, or fixed disk, or embodied in a computer data signal, the signal being transmitted over a tangible medium or a wireless medium, for example, microwave or infrared. The series of computer instructions can constitute all or part of the functionality described above, and can also be stored in any memory device, volatile or non-volatile, such as semiconductor, magnetic, optical or other memory device.