Abstract:
Systems and methods for improving resolution of low-noise signals in an analog-to-digital conversion circuit. A simple, low cost pseudo-noise generating circuit is disclosed that, when connected to the signal conditioning circuitry of A/D conversion circuit, adds pseudo-noise to an analog input voltage signal. Additional pseudo-noise is beneficial for improving the resolution of analog-to-digital conversion when oversampling and summing or averaging are used in post-conversion processing operations. The circuit is composed of a plurality of resistors configured in at least two parallel branches. An individually switchable voltage source output is connected to each branch. A resulting analog voltage can be measured at a common termination point for the branches, depending on the combination of switchable voltage source output turned on, and the branch to which the voltage output is applied. By varying the combination of switchable voltage source outputs turned on over time, a known analog pseudo-noise signal is developed.

Description:
GOVERNMENT INTEREST 
     The invention described herein was made in the performance of work under U.S. Government Contract No. N00030-08-C-0010 for the U.S. Navy. The Government may have rights to portions of this invention. 
    
    
     BACKGROUND OF THE INVENTION 
     The noise free code resolution of an A/D converter is the number of bits of resolution beyond which it is no longer possible to distinctly resolve individual codes. In other words, this is essentially the number of digital code levels actually available after correction for the loss in resolution due to input referred noise. Said another way, this is the degree to which digital codes become lumped together as indistinguishable from one another due to the noise added during conversion, and is called quantization noise. 
     To counter this loss in resolution, averaging of the digital output signal can be used. Averaging is effective because by collecting a sufficient number of digital output samples, the distribution of sampled outputs that determines noise resolution becomes increasingly tightly defined. The effect is visible as an increase in height and a narrowing in the neck of the distribution of sampled outputs compared with a distribution of fewer samples. This decreases the distribution&#39;s standard deviation, and therefore the noise free code resolution. 
     In order to develop a distribution, though, there must be a minimum level of variability in the acquired signal. This leads to a paradoxical requirement: to raise the resolution of an A/D converter, one can use digital averaging, but with this technique there is an accompanying need to actually have a minimum level of noise in the signal. If a suitable noise signal is not available, then one must be intentionally generated or something that gives the same result. 
     A general noise signal is one possibility, but is often not selected, most often because it has been filtered out at earlier circuit stages of the circuit than the A/D converter, or is an insufficient noise level. White noise is another choice, however it is cumbersome to introduce without adding significant circuitry and has disadvantages. 
     SUMMARY OF THE INVENTION 
     The present invention provides circuits and methods for improving the resolution of an analog to digital converter. With this method, an analog repeatable deterministic signal is deliberately summed with an analog input voltage signal before passing the summed signal to an analog digital converter. The analog repeatable deterministic signal is generated by a circuit including a plurality of resistors making up at least two circuit branches and a common connection point. The common connection point is connected to a ground connection through a current summing resistor. The common connection point is connected to a signal conditioning circuit at an amplifier input. Finally the two or more circuit branches are connected to a plurality of switchable voltage source outputs. 
     In one aspect of the invention, the plurality of switchable voltage source outputs are switched on and off in various combinations. At the common connection point, also referred to as the repeating deterministic signal output node, the voltage varies as a function of the combination of switchable voltage source outputs are switched on, and the circuit branches to which this voltage is applied. This deterministic varying voltage is added to the analog input voltage signal by connection of the deterministic signal output node to a signal conditioning amplifier input that is also receiving the analog input signal. 
     In another aspect of the invention, three switchable voltage source outputs are included. There are eight possible switching combinations for these three voltage source outputs. Each of the eight possible combinations is executed before repeating any combination a second time. In a further refinement, by repeating this sequence of combinations periodically, a known and periodic pseudo-noise signal is available to the signal conditioning circuit at the analog to digital converter. 
     Connection of the previously described repeating deterministic signal generating circuit to the amplifier input of the signal conditioning circuit makes an analog deterministic signal available to the signal conditioning circuit of A/D converter circuit. With the addition of the generated deterministic signal to the analog input voltage signal and oversampling and averaging of the resultant digital output signal, the resolution of the analog to digital converter can be increased. By adding a repeating deterministic signal with a repetition rate at an appropriate period shorter than the data averaging period it can be totally filtered out and any DC offset introduced is known and can be subtracted out. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings: 
         FIG. 1  is an electrical flow diagram of an analog-to-digital signal conversion circuit with repeating deterministic signal summation formed in accordance with an embodiment of the present invention; 
         FIG. 2  is a circuit diagram of a circuit for providing repeating deterministic signal summation to an analog-to-digital converter; 
         FIG. 3  is a circuit diagram of a repeating deterministic signal generating circuit formed in accordance with an embodiment of the present invention; 
         FIG. 4-1  thru  4 - 8  is a display of the possible switch configurations of the circuit shown in  FIG. 3 ; 
         FIG. 5  shows an analog voltage output signal from the repeating deterministic signal generating circuit in  FIG. 3  for a sequence of switchable voltage source output combinations of  FIG. 4 ; and 
         FIG. 6  is a circuit diagram of a temperature monitoring circuit, including a repeating deterministic signal generating circuit and an analog signal conditioning circuit for adding the repeating deterministic signal to the analog voltage input signal. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows an electrical flow diagram of the functional operations of an analog-to-digital (A/D) signal conversion circuit that includes repeating deterministic summation. First, an analog repeating deterministic signal  34  is added to an analog input voltage signal  28  in an analog signal summing step  24 - 1 . The output of the analog signal summing step  24 - 1  is a repeating deterministic enhanced sensor signal  16 , which is delivered to an A/D signal conversion step  22 - 1 , thus producing a digital output voltage signal  32 . Digital post-processor operations  35 , such as oversampling and either averaging or adding, are applied to the digital output voltage signal  32  in the oversample &amp; average block  35  ( FIG. 2  processor  25 ) to take advantage of the added analog repeating deterministic signal  34 . With the addition of the generated analog repeating deterministic signal  34  to the analog input voltage signal  28 , and oversampling and averaging of the resultant digital output signal  32 , the resolution of the analog to digital conversion step  22 - 1  can be increased. 
       FIG. 2  shows an A/D conversion circuit  20 . In this embodiment, the circuit  20  is a temperature monitoring circuit that includes an A/D converter  22 , an analog signal conditioning circuit  24 , a processor  25 , a sensor  26  and a repeating deterministic signal generating circuit  45 . The sensor  26  is connected to the A/D converter  22  by the analog signal conditioning circuit  24 . The sensor  26  outputs an analog input voltage signal  28  that is delivered to the signal conditioning circuit  24 . The signal conditioning circuit  24  outputs the pseudo-noise enhanced sensor signal  16  that is delivered to the A/D converter  22 . The A/D converter  22  outputs the digital output voltage signal  32  that is delivered to the processor  25 . The repeating deterministic signal generating circuit  45  provides an analog repeating deterministic signal  34  to the analog signal conditioning circuit  24 . 
     In one embodiment, the signal conditioning circuit  24  includes a capacitive filter  36 , an operational amplifier  38 , a feedback resistor  40 , a plurality of circuit resistors  42 - 1   42 - 2   42 - 3 , a reference voltage source  44 , and a ground connection  46 . The operational amplifier  38  includes a positive input port  38 - 1 , a negative input port  38 - 2  and an output port  38 - 3 . 
     In this embodiment, the electrical components of the analog signal conditioning circuit  24  are connected as is ordinary to one skilled in the art of analog signal conditioning. This includes constructing a differential operational amplifier filter and amplification circuit, including the following electrical component connections: the capacitive filter  36  is connected across the input of the analog signal conditioning circuit  24 , one leg to the output of the sensor  26  and the other to the ground connection  46 . The operational amplifier output port  38 - 3  is connected to the input of the A/D converter  22 . The feedback resistor  40  is connected across the operational amplifier negative input port  38 - 2  and the operational amplifier output port  38 - 3 . The operational amplifier negative input port  38 - 2  is separated from the ground connection  46  by circuit resistor  42 - 1  and is separated from the reference voltage source  44  by circuit resistor  42 - 2 . The operational amplifier positive input port  38 - 1  is connected to the output of the sensor  26  and is separated from the reference voltage source  44  by circuit resistor  42 - 3 . 
     The analog signal conditioning circuit  24  is a differential operational amplifier signal conditioning circuit which filters and amplifies the analog input voltage signal  28  received from the sensor  26  before it is delivered to input of the A/D converter  22 . Understandably the analog signal conditioning circuit  24  can take on a number of circuit configurations that accomplish the same filtering and amplification function without deviating from the thrust of this invention. 
       FIG. 3  shows a simple repeating deterministic generating circuit  45 . The repeating deterministic generating circuit  45  is a signal source for the analog repeating deterministic signal  34  that is added to the analog input voltage signal  28  in the signal conditioning circuit  24  of  FIG. 2 . The repeating deterministic signal generating circuit  45  includes a plurality of switchable voltage source outputs  48 , a resistor network  50 , and a current summing resistor  52 . The resistor network  50  includes a first resistor  50 - 1 , a second resistor  50 - 2 , a third resistor  50 - 3 , and a fourth resistor  50 - 4 . In one embodiment, the plurality of switchable voltage source outputs  48  is an application specific integrated circuit (ASIC) with multiple output pins. 
     The plurality of individual resistors  50 - 1 ,  50 - 2 ,  50 - 3 ,  50 - 4  is connected in a combination of series and parallel connections to furnish a plurality of branches. One end of each parallel branch is connected to one of a plurality of the switchable voltage source outputs  48 . At the other end of each parallel branch, the plurality of branches is connected together at a common repeating deterministic signal output node  53 . The repeating deterministic signal output node  53  is connected to the ground connection  46  through the current summing resistor  52 . In one embodiment, the switchable voltage source outputs  48  are connected to a common voltage source and the switchable voltage source outputs  48  are switches. In another embodiment the ASIC with multiple output pins provides a fixed voltage at each pin. Digital control of the ASIC allows each output pin to be switched on and off independently. This allows for multiple combinations of output pins having a voltage at their output. 
     In one embodiment, the first, second and third resistors  50 - 1 ,  50 - 2  and  50 - 3  of the resistor network  50  share a common resistance value, and the fourth resistor  50 - 4  has a value one half that of the first, second and third resistors  50 - 1 ,  50 - 2 ,  50 - 3 . Furthermore, the first and second resistors  50 - 1  and  50 - 2  are connected in series. The resistor network  50  includes three branches. The first branch includes the series connection of the first and second resistors  50 - 1 ,  50 - 2 . The second branch includes the third resistor  50 - 3 . The third branch includes the fourth resistor  50 - 4 . One end of each of the three branches of the resistor network  50  is connected to a different one of the three switchable source outputs  48 . 
     The output measured at the repeating deterministic signal output node  53 , the connection of the branches of the resistor network  50  to the current summing resistor  52 , is defined as the analog repeating deterministic signal  34 . The achievable values for the analog repeating deterministic signal  34  by the repeating deterministic signal generating circuit  45  depends on the value of the voltage available at the switchable voltage source outputs  48 , the individual resistor values selected for the plurality of resistors  50 - 1 ,  50 - 2 ,  50 - 3 ,  50 - 4  that make up the resistor network  50 , the configuration of the plurality of resistors  50 - 1 ,  50 - 2 ,  50 - 3 ,  50 - 4  that make up the resistor network  50 , and the value of the current summing resistor  52 . 
     Once individual resistor values and a configuration for connecting them is selected, and the value of the voltage available at the switchable voltage source outputs  48  is selected, the output of the analog repeating deterministic signal  34  is regulated by which ones of the switchable voltage source outputs  48  are switched on.  FIG. 4  shows the combinations of the switchable voltage source outputs  48  available for an embodiment having three outputs. Each combination is represented by one of the digital voltage levels [000], [001], [010], [011], [100], [101], [110] and [111]. For the embodiment using an ASIC, these are the available combinations for an ASIC having three output pins. 
       FIG. 5  shows an embodiment of the analog repeating deterministic signal  34  generated by the repeating deterministic signal generating circuit  45 . In a plot of repeating deterministic signal  34 , time is plotted on an independent axis  12  and voltage on a response axis  14 . The analog repeating deterministic signal  34  is an exemplary repeating deterministic signal generated by the repeating deterministic signal generating circuit  45  shown in  FIG. 3 . By sequentially switching through each of eight possible combinations of the three switchable voltage source outputs  48  represented by digital voltage levels [000], [001], [010], [011], [100], [101], [110] and [111], eight different voltage levels can be achieved in the analog repeating deterministic signal  34 . 
     In one embodiment, to maximize the reduction in noise, the frequency at which the deterministic signal  34  changes voltage levels matches the length of one averaging period of the digital output voltage signal  32  divided by an integer multiple of the number of voltage levels in the deterministic signal  34 . In applications emphasizing speed rather than accuracy, the integer multiple is raised and averaging is performed over only a portion of one period of the digital output voltage signal  32 . Ordering them in ascending and then descending level of voltage output yields the signal in the embodiment of  FIG. 5 , however there are numerable alternative orders for the voltage levels of the deterministic signal  34  that can be added in to improve the resolution of the digital output voltage signal  32 . 
     In alternative embodiments, a repeating deterministic signal, or a pseudo-noise signal of a different waveform is achievable by changing the order in which the switchable voltage source outputs  48  are activated. Frequency and periodicity of the waveform of the analog voltage signal  34  is also variable. The maximum number of unique voltage levels achievable is adjustable by adjusting the number of branches in the resistor network  50 , adjusting the number of or value of the plurality of resistors  50 - 1 ,  50 - 2 ,  50 - 3 ,  50 - 4  that make up the resistor network  50 , connecting the resistors of the resistor network  50  in a different configuration to yield branches of differing resistance value, or adjusting the switchable voltage source outputs  48  to offer a different voltage or voltages. Different number of samples can be averaged. 
       FIG. 6  shows the repeating deterministic signal generating circuit  45  connected to the analog signal conditioning circuit  24  by connection of the repeating deterministic signal output node  53  to the signal condition circuit  24  at the point at which the operational amplifier negative input port  38 - 2  in the signal conditioning circuit  24  was formerly connected to the ground connection  46 . This changes the reference voltage of the operational amplifier  38 , causing the analog repeating deterministic signal  34  to become added to the analog input voltage signal  28 . After amplification by the operational amplifier  38 , the sum of the input voltage  28  and the repeating deterministic signal  34  is delivered to the input of the A/D converter  22  as the analog A/D input voltage signal  16 . With the addition of the analog repeating deterministic signal  34  to the analog input voltage signal  28 , the analog A/D input voltage signal  16  contains sufficient pseudo-noise that following A/D conversion, there is sufficient distribution in the digital output voltage signal  32  for oversampling and averaging of the digital output voltage signal  32  to increase the effective resolution of A/D converter  22 . 
     The benefit of the pseudo-noise signal generating circuit  45  is that the resolution of the A/D converter  22  can be increased cheaply and simply, and with little additional circuitry. In one embodiment, the switchable voltage source outputs  48  are integral to a field programmable gate array (FPGA) already available in the analog A/D signal conversion circuit  20  for other purposes. In this embodiment, the only additional required components are the plurality of resistors  50 - 1 ,  50 - 2 ,  50 - 3 ,  50 - 4  in the resistor network  50 , and the connections between them, and the connection to the analog signal conditioning circuit  24 . Therefore this solution has a benefit over other methods, such as adding white noise, general noise or a integrated digital-to-analog converter, in its simplicity, lower cost, and use of purely passive components. A further benefit of pseudo-noise over other noise sources is that because all frequency components of the pseudo-noise are above the highest frequency of the averaging periods of the digital output signal, the additional noise is not disruptive to the digital output voltage signal  32 . 
     While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. For example, in alternative embodiments, different values or ratios for resistor values of the plurality of resistors  50 - 1 ,  50 - 2 ,  50 - 3 ,  50 - 4  could be used, different resistor branch configurations in the resistor network  50 , a different number of switchable voltage source outputs  48 , or connection of the repeating deterministic signal generating circuit  45  to an entirely different signal conditioning circuit  24 . Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.