Abstract:
A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to monitoring cool-down stress of a flip chip process, and more specifically, to monitoring the cool-down stress of the flip chip process using monitor solder bump structures. 
       BACKGROUND OF THE INVENTION 
       [0002]    During a conventional flip chip process, stress may occur in solder bump structures resulting in cracks beneath solder bumps of the solder bump structures. Therefore, there is a need for a method and structure for monitoring the cool-down stress of the flip chip process using monitor solder bump structures. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a structure stress monitoring scheme, comprising providing a semiconductor chip which includes: (a) M regular solder bump structures, and (b) N monitor solder bump structures, wherein M and N are positive integers, wherein each regular solder bump structure of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip, and wherein each monitor solder bump structure of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip; performing a flip chip process for the semiconductor chip resulting in P monitor solder bump structures of the N monitor solder bump structures being cracked, wherein P is a positive integer not greater than N, wherein the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures, and wherein the cool-down stress results from a cool-down step of the flip chip process; determining a value of P; specifying a maximum acceptable number Q of cracked monitor solder bump structures of the N monitor solder bump structures, wherein Q is a positive integer smaller than N; if the value of P is equal to or smaller than Q, then determining that the cool-down stress resulting from the flip chip process is low and acceptable; and if the value of P is greater than Q, then determining that the cool-down stress resulting from the flip chip process is too high and unacceptable. 
         [0004]    The present invention provides a method and structure for monitoring the cool-down stress of the flip chip process using monitor solder bump structures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  shows a top-down view of a semiconductor chip, in accordance with embodiments of the present invention. 
           [0006]      FIGS. 1A-1G  (cross-section views) illustrate a fabrication process for forming a solder bump structure of the semiconductor chip of  FIG. 1 , in accordance with embodiments of the present invention. 
           [0007]      FIG. 2  shows a cross-section view of the semiconductor chip of  FIG. 1  along a line  2 - 2 , in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0008]      FIG. 1  shows a top-down view of a semiconductor chip  10 , in accordance with embodiments of the present invention. More specifically, the semiconductor chip  10  comprises multiple regular solder bump structures  100   r  and monitor solder bump structures  100   a,    100   b,  and  100   c.  The multiple regular solder bump structures  100   r  are electrically connected to power supplies (ground, VDD) (not shown) and devices (not shown) of the chip  10 , whereas the monitor solder bump structures  100   a,    100   b,  and  100   c  are not electrically connected to the power supplies or the devices of the chip  10 . The regular solder bump structures  100   r  and the monitor solder bump structures  100   a,    100   b,  and  100   c  are simultaneously formed in a similar manner at top of the semiconductor chip  10 . The monitor solder bump structures  100   a,    100   b,  and  100   c  are structurally similar to the regular solder bump structure  100   r,  except for some differences as described below with reference to  FIG. 2 . In one embodiment, the monitor solder bump structures  100   a,    100   b,  and  100   c  are at a corner of the semiconductor chip  10  (as shown in  FIG. 1 ). The regular solder bump structures  100   r  and the monitor solder bump structures  100   a,    100   b,  and  100   c  can be collectively referred to as solder bump structures  100 . 
         [0009]      FIGS. 1A-1G  (cross-section views) illustrate a fabrication process for forming a solder bump structure  100  of the semiconductor chip  10  of  FIG. 1 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication of the solder bump structure  100  starts with a top interconnect layer  102  of the semiconductor chip  10  including (i) a dielectric layer  110 , and (ii) an electrically conductive line  112  (comprising copper (Cu) in one embodiment) embedded in the dielectric layer  110 . There are additional interconnect layers beneath and electrically coupled to the top interconnect layer  102 , but these additional interconnect layers are not shown for simplicity. 
         [0010]    Next, in one embodiment, a hole  116  is created in the dielectric layer  110  resulting in a top surface  114  of the Cu line  112  being exposed to the surrounding ambient. 
         [0011]    Next, in one embodiment, a bond pad  120  (comprising aluminum (Al) in one embodiment) is formed on top of the Cu line  112  and the dielectric layer  110  such that the Al bond pad  120  (i) fills the hole  116 , and (ii) is electrically coupled to the Cu line  112 . Illustratively, the Al bond pad  120  can be formed by (a) forming an Al layer (not shown) on the entire structure  100  including in the hole  116 , and then (b) directionally and selectively etching back the Al layer stopping at the dielectric layer  110 . The directional and selective etching in step (b) may be performed using traditional lithographic and etching processes such that what remains of the Al layer after the etching is the Al bond pad  120  (as shown in  FIG. 1A ). 
         [0012]    Next, with reference to  FIG. 1B , in one embodiment, a photosensitive polyimide (PSPI) layer  130  (having a thickness in a range of 3-5 μm in one embodiment) is formed on top of the entire structure  100  of  FIG. 1A . More specifically, the PSPI layer  130  is formed by (i) spin-applying a polyimide material on the entire structure  100  of  FIG. 1A , and then (ii) curing the deposited polyimide material at a high temperature resulting in the PSPI layer  130 . 
         [0013]    Next, in one embodiment, a hole  132  is created in the PSPI layer  130  such that a top surface  122  of the Al bond pad  120  is exposed to the surrounding ambient via the hole  132 . More specifically, the hole  132  is formed in the PSPI layer  130  by using a conventional lithographic process. It should be noted that polyimide is a photosensitive polymer. In general, other photosensitive polymers may be used instead of polyimide. 
         [0014]    Next, with reference to  FIG. 1C , in one embodiment, a bump limiting metallurgy (BLM) film  140  is formed on top of the entire structure  100  of  FIG. 1B  including on the bottom wall and side wall of the hole  132  such that the BLM film  140  is in direct physical contact with the Al bond pad  120 . Illustratively, the BLM film  140  comprises multiple layers of copper (Cu), chrome (Cr), and gold (Au). The BLM film  140  can be formed by sputter deposition. 
         [0015]    Next, with reference to  FIG. 1D , in one embodiment, a patterned photo-resist layer  150  is formed on top of the BLM film  140 . The patterned photo-resist layer  150  has a hole  152  aligned with and wider than the hole  132  such that a top surface  142  of the BLM film  140  is exposed to the surrounding ambient via the hole  152 . It should be noted that the holes  132  and  152  can be collectively referred to as a hole  132 + 152 . The patterned photo-resist layer  150  is formed by using a conventional lithographic process. 
         [0016]    Next, with reference to  FIG. 1E , in one embodiment, a solder bump  160  (comprising a mixture of silver (Ag) and tin (Sn) in one embodiment) is formed in the hole  132 + 152  by, illustratively, electroplating. More specifically, the structure  100  is submerged in a solution (not shown) containing tin and silver ions. The BLM film  140  is electrically coupled to the cathode of an external dc (direct current) power supply (not shown), while the solution is electrically coupled to the anode of the dc power supply. Under the electric field created in the solution by the dc power supply, tin and silver ions in the solution arrive at the exposed surface  142  of the BLM film  140  and deposit there forming the solder bump  160 , as shown in  FIG. 1E . The filled hole  132  of the PSPI layer  130  is called a solder bump via  132 . In one embodiment, the solder bump  160  is formed such that its top surface  162  is at a lower level than a top surface  154  of the patterned photoresist layer  150 . Alternatively, the solder bump  160  is formed such that its top surface  162  is at a higher level than the top surface  154  of the patterned photo-resist layer  150 . 
         [0017]    Next, in one embodiment, the patterned photoresist layer  150  is completely removed. The patterned photoresist layer  150  can be removed by wet etching. 
         [0018]    Next, in one embodiment, the BLM film  140  is etched with the solder bump  160  as a blocking mask resulting in a BLM region  140 ′ of  FIG. 1F . More specifically, the BLM film  140  is etched by using a plasma etch process. The resulting structure  100  is shown in  FIG. 1F . 
         [0019]    Next, in one embodiment, the solder bump  160  of  FIG. 1F  is reflowed at a high temperature, resulting the solder bump  160 ′ of  FIG. 1G . The resulting solder bump  160 ′ has a half-spherical shape at its top portion. Illustratively, the solder bump  160  of  FIG. 1F  is reflowed by subjecting it to a temperature lower than 400° C. It should be noted that  FIG. 1G  is a cross-section view of a regular solder bump structure  100   r  (cross-section views of the monitor solder bump structures  100   a,    100   b,  and  100   c  are the same) of the semiconductor chip  10  of  FIG. 1  along a line  1 G- 1 G. 
         [0020]    After the solder bump structures  100  are formed at top of the semiconductor chip  10  using the fabrication process described above in  FIGS. 1A-1G , a flip chip process is performed. More specifically, the chip  10  (in  FIG. 1 ) is flipped upside down and aligned to an organic laminate (not shown). Then, the solder bumps  160 ′ of the solder bump structures  100  are bonded directly, simultaneously, and one-to-one to pads (not shown) of the organic laminate at a high temperature and then cooled down. 
         [0021]    During the cool-down step of the flip chip process described above, stress may occur in the solder bump structures  100  due to the difference in the coefficients of thermal extension (CTE) of the chip  10  and the organic laminate (not shown). This cool-down stress may cause cracks beneath the solder bumps  160 ′ of the solder bump structures  100 . In one embodiment, the cracked solder bump structures can be identified by a sonoscan after the flip chip process. More specifically, the cracked solder bump structures can be easily identified on a sonoscan result, because they show up on the sonoscan result as bright dots, whereas the intact solder bump structures show up on the sonoscan result as dark dots. 
         [0022]      FIG. 2  shows a cross-section view of the monitor solder bump structures  100   a,    100   b,  and  100   c  and a regular solder bump structure  100   r  of the semiconductor chip  10  of  FIG. 1  along a line  2 - 2 , in accordance with embodiments of the present invention. As can be seen in  FIG. 2 , the monitor solder bump structures  100   a,    100   b,  and  100   c  share the same PSPI layer  130 . 
         [0023]    With reference to  FIG. 2 , in one embodiment, the diameters D r , D a , D b , and D c  of the solder bump vias  132 ,  132   a,    132   b,  and  132   c,  respectively, are such that D r &lt;D a &lt;D b &lt;D c , whereas the diameters S r , S a , S b , and S c  of BLM regions  140 ′,  140   a ′,  140   b ′, and  140   c ′, respectively, are such that S r =S a =S b =S c . The inventors of the present invention have found through modeling and experimental data that the larger the diameter of the solder bump via of the solder bump structure is, the more sensitive to the cool-down stress (more prone to the crack due to the cool-down stress) this solder bump structure becomes. As a result, the monitor solder bump structure  100   c  is more sensitive to the cool-down stress than the monitor solder bump structure  100   b;  the monitor solder bump structure  100   b  is more sensitive to the cool-down stress than the monitor solder bump structure  100   a;  and the monitor solder bump structure  100   a  is more sensitive to the cool-down stress than the regular solder bump structure  100   r.  Because of the differences in the diameters D a , D b , and D c  of the solder bump vias  132   a,    132   b,  and  132   c,  the number of the cracked monitor solder bump structures (identified by the sonoscan after the flip chip process) of the three monitor solder bump structures  100   a,    100   b,  and  100   c  indicates the level of the cool-down stress endured by the solder bump structures  100  of the semiconductor chip  10  during the cool-down step of the flip chip process. 
         [0024]    In one embodiment, multiple semiconductor chips (not shown) similar to the semiconductor chip  10  of  FIG. 1  are formed and then in turn go through the same flip chip process. That is each of the multiple semiconductor chips has three monitor solder bump structures (similar to the three monitor solder bump structures  100   a,    100   b,  and  100   c  of the semiconductor chip  10 ). After going through the flip chip process, assume that a first chip of the multiple semiconductor chips has only one cracked monitor solder bump structure  100   c;  that a second chip of the multiple semiconductor chips has two cracked monitor solder bump structures  100   b  and  100   c;  and that a third chip of the multiple semiconductor chips has three cracked monitor solder bump structures  100   a,    100   b,  and  100   c.  This indicates that the cool-down stress endured by the solder bump structures  100  of the first chip is lower than the cool-down stress endured by the solder bump structures  100  of the second chip; and that the cool-down stress endured by the solder bump structures  100  of the second chip is lower than the cool-down stress endured by the solder bump structures  100  of the third chip. 
         [0025]    In one embodiment, a structure stress monitoring scheme using the monitor solder bump structures of the multiple semiconductor chips (similar to the semiconductor chip  10  in  FIG. 1 ) can be as follow. If a chip of the multiple semiconductor chips after going through the flip chip process has only one cracked monitor solder bump structure of the three monitor solder bump structures, then the cool-down stress endured by the solder bump structures  100  of the chip during the cool-down step of the flip chip process is considered low and production is allowed to continue (i.e., the flip chip process is acceptable). If a chip of the multiple semiconductor chips after going through the flip chip process has two cracked monitor solder bump structures of the three monitor solder bump structures, then the cool-down stress endured by the solder bump structures  100  of the chip during the cool-down step of the flip chip process is considered high but the production is allowed to continue (i.e., the flip chip process is still acceptable). If a chip of the multiple semiconductor chips after going through the flip chip process has three cracked monitor solder bump structures, then the cool-down stress endured by the solder bump structures  100  of the chip during the cool-down step of the flip chip process is considered too high and the production is stopped (i.e., the flip chip process is unacceptable). 
         [0026]    In summary, by monitoring the monitor solder bump structures  100   a,    100   b,  and  100   c  of each semiconductor chip going through the flip chip process, the level of the cool-down stress associated with the cool-down step of the flip chip process can be monitored. 
         [0027]    In the embodiment described above, with reference to  FIG. 2 , D r &lt;D a &lt;D b &lt;D c  and S r =S a =S b =S c . Alternatively, D r =D a =D b =D c  and S r &gt;S a &gt;S b &gt;S c . The inventors of the present invention have found through modeling and experimental data that the smaller the diameter of the BLM region of the solder bump structure is, the more sensitive to the cool-down stress (more prone to the crack due to the cool-down stress) this solder bump structure becomes. As a result, the monitor solder bump structure  100   c  is more sensitive to the cool-down stress than the monitor solder bump structure  100   b;  the monitor solder bump structure  100   b  is more sensitive to the cool-down stress than the monitor solder bump structure  100   a;  and the monitor solder bump structure  100   a  is more sensitive to the cool-down stress than the regular solder bump structure  100   r.  The structure stress monitoring scheme described above can be applied to the semiconductor chip  10  formed accordant to this alternative embodiment. More specifically, if there are less than three cracked monitor solder bump structures in a chip, then the production is allowed to continue (i.e., the flip chip process is acceptable). If there are more than two cracked monitor solder bump structures in a chip, then the production is stopped (i.e., the flip chip process is unacceptable). 
         [0028]    In the embodiments described above, with reference to  FIG. 1 , each semiconductor chip has only three monitor solder bump structures  100   a,    100   b,  and  100   c.  In general, each semiconductor chip has N monitor solder bump structures, wherein N is a positive integer. 
         [0029]    In the embodiments described above, with reference to  FIG. 1 , the monitor solder bump structures  100   a,    100   b,  and  100   c  are at a corner of the semiconductor chip  10 . In general, the monitor solder bump structures  100   a,    100   b,  and  100   c  can be at anywhere of the chip  10 . 
         [0030]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.