Abstract:
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

Description:
RELATED APPLICATION DATA 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 09/619,988 filed Jul. 20, 2000, which claims the benefit of U.S. Provisional Application No. 60/167,136, filed Nov. 23, 1999, both of which are hereby incorporated by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    This invention relates generally to testing of integrated circuits and more particularly relates to compaction of test responses used in testing for faults in integrated circuits. 
       BACKGROUND 
       [0003]    As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. Second, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Third, applying the test data to a large circuit requires an increasingly long test application time. And fourth, present external testing equipment is unable to test such larger circuits at their speed of operation. 
         [0004]    Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements like flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing all (or almost all) memory elements are connected into one or more shift registers, as shown in U.S. Pat. No. 4,503,537. A circuit that has been designed for test has two modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit under test (CUT) works properly. 
         [0005]    Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (ATPG) and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns) that guarantee almost complete fault coverage of several types of fault models including stuck-at, transition, path delay faults, and bridging faults. Typically, when a particular potential fault in a circuit is targeted by an ATPG tool, only a small number of scan cells, e.g., 2-5%, must be specified to detect the particular fault (deterministically specified cells). The remaining scan cells in the scan chains are filled with random binary values (randomly specified cells). This way the pattern is fully specified, more likely to detect some additional faults, and can be stored on a tester. 
         [0006]      FIG. 1  is a block diagram of a conventional system  10  for testing digital circuits with scan chains. External automatic testing equipment (ATE), or tester,  12  applies a set of fully specified test patterns  14  one by one to a CUT  16  in scan mode via scan chains  18  within the circuit. The circuit is then run in normal mode using the test pattern as input, and the test response to the test pattern is stored in the scan chains. With the circuit again in scan mode, the response is then routed to the tester  12 , which compares the response with a fault-free reference response  20 , also one by one. For large circuits, this approach becomes infeasible because of large test set sizes and long test application times. It has been reported that the volume of test data can exceed one kilobit per single logic gate in a large design. The significant limitation of this approach is that it requires an expensive, memory-intensive tester and a long test time to test a complex circuit. 
         [0007]    These limitations of time and storage can be overcome to some extent by adopting a built-in self-test (BIST) framework as shown in  FIG. 2 . In BIST, additional on-chip circuitry is included to generate test patterns, evaluate test responses, and control the test. For example, a pseudo-random pattern generator  21  is used to generate the test patterns, instead of having deterministic test patterns. Additionally, a multiple input signature register (MISR)  22  is used to generate and store a resulting signature from test responses. In conventional logic BIST, where pseudo-random patterns are used as test patterns, 95-96% coverage of stuck-at faults can be achieved provided that test points are employed to address random-pattern resistant faults. On average, one to two test points may be required for every 1000 gates. In BIST, all responses propagating to observable outputs and the signature register have to be known. Unknown values corrupt the signature and therefore must be bounded by additional test logic. Even though pseudo-random test patterns appear to cover a significant percentage of stuck-at faults, these patterns must be supplemented by deterministic patterns that target the remaining, random pattern resistant faults. Very often the tester memory required to store the supplemental patterns in BIST exceeds 50% of the memory required in the deterministic approach described above. Another limitation of BIST is that other types of faults, such as transition or path delay faults, are not handled efficiently by pseudo-random patterns. Because of the complexity of the circuits and the limitations inherent in BIST, it is extremely difficult, if not impossible, to provide a set of test patterns that fully covers hard-to-test faults. 
         [0008]    Some of the DFT techniques include compactors to compress the test responses from the scan chains. There are generally two types of compactors: time compactors and spatial compactors. Time compactors typically have a feedback structure with memory elements for storing a signature, which represents the results of the test. After the signature is completed it is read and compared to a fault-free signature to determine if an error exists in the integrated circuit. Spatial compactors generally compress a collection of bits (called a vector) from scan chains. The compacted output is analyzed in real time as the test responses are shifted out of the scan chains. Spatial compactors can be customized for a given circuit under test to reduce the aliasing phenomenon, as shown in the U.S. Pat. No. 5,790,562 and in few other works based on multiplexed parity trees or nonlinear trees comprising elementary gates such as AND, OR, NAND, and NOR gates. 
         [0009]    Linear spatial compactors are built of Exclusive-OR (XOR) or Exclusive-NOR (XNOR) gates to generate n test outputs from the m primary outputs of the circuit under test, where n&lt;m. Linear compactors differ from nonlinear compactors in that the output value of a linear compactor changes with a change in just one input to the compactor. With nonlinear compactors, a change in an input value may go undetected at the output of the compactor. However, even linear compactors may mask errors in an integrated circuit. For example, the basic characteristic an XOR (parity) tree is that any combination of odd number of errors on its inputs propagates to their outputs, and any combination of even number of errors remains undetected. 
         [0010]    An ideal compaction algorithm has the following features: (1) it is easy to implement as a part of the on-chip test circuitry, (2) it is not a limiting factor with respect to test time, (3) it provides a logarithmic compression of the test data, and (4) it does not lose information concerning faults. In general, however, there is no known compaction algorithm that satisfies all the above criteria. In particular, it is difficult to ensure that the compressed output obtained from a faulty circuit is not the same as that of the fault-free circuit. This phenomenon is often referred to as error masking or aliasing and is measured in terms of the likelihood of its occurrence. An example of error masking occurs when the spatial compactor reads two fault effects at the same time. The multiple fault effects cancel each other out and the compactor output is the same as if no faults occurred. 
         [0011]    Unknown states are also problematic for error detection. An unknown state on one or more inputs of an XOR tree generates unknown values on its output, and consequently masks propagation of faults on other inputs. A common application of space compactors is to combine the observation points inserted into the CUT as a part of design-for-testability methodology. The spatial compactors can be also used to reduce the size of the time compactors by limiting the number of their parallel inputs. 
         [0012]    Undoubtedly, the most popular time compactors used in practice are linear feedback shift registers (LFSRs). In its basic form, the LFSR (see  FIG. 3 ) is modified to accept an external input in order to act as a polynomial divider. An alternative implementation (called type II LFSR) is shown in  FIG. 4 . The input sequence, represented by a polynomial, is divided by the characteristic polynomial of the LFSR. As the division proceeds, the quotient sequence appears at the output of the LFSR and the remainder is kept in the LFSR. Once testing is completed, the content of the LFSR can be treated as a signature. 
         [0013]      FIG. 5  shows another time compactor (which is a natural extension of the LFSR-based compactor) called a multiple-input LFSR, also known as a multiple-input signature register (MISR). The MISR is used to test circuits in the multiple scan chain environment such as shown in the U.S. Pat. No. 4,503,537. MISRs feature a number of XOR gates added to the flip-flops. The CUT scan chain outputs are then connected to these gates. 
         [0014]      FIG. 6  shows an example of a pipelined spatial compactor with a bank of flip-flops separating stages of XOR gates. A clock (not shown) controls the flip-flops and allows a one-cycle delay before reading the compacted output. 
         [0015]    The limitation of spatial compactors, such as the one shown in  FIG. 6 , is that unknown states can reduce fault coverage. Time compactors, such as shown in  FIGS. 3 ,  4 , and  5 , are completely unable to handle unknown states since an unknown state on any input can corrupt the compressed output generated by the compactor. With both time compactors and spatial compactors, multiple fault effects can reduce fault coverage. Additionally, if a fault effect is detected within the integrated circuit, these compactors have limited ability to localize the fault. 
         [0016]    An object of the invention, therefore, is to provide an efficient compactor that can select which scan chains are analyzed. This ability to select allows the compactor to generate a valid compressed output even when receiving unknown states or multiple fault effects on its inputs. The compactor can also be used diagnostically to determine the location of faults within an integrated circuit. 
       SUMMARY 
       [0017]    A compactor is disclosed that selects test responses in one or more scan chains to compact into a compressed output, while one or more other test responses are masked. Thus, test responses containing unknown states may be masked to ensure that the compactor generates a valid compressed output. Additionally, test responses can be masked to ensure fault masking does not occur. The compactor can also analyze test responses from individual scan chains to diagnostically localize faults in an integrated circuit. 
         [0018]    A compactor includes selection circuitry that controls which scan chains are analyzed. The selection circuitry passes desired test responses from scan chains onto a compactor, while masking other test responses. In one embodiment, the selection circuitry may include an identification register that is loaded with a unique identifier of a scan chain. Based on the state of a flag register, either only the test response stored within the scan chain identified is passed to the compactor or all test responses are passed to the compactor except the test response associated with the identified scan chain. 
         [0019]    In another embodiment, the selection circuitry includes a flag that controls whether only selected test responses are compacted or whether all test responses are compacted. 
         [0020]    In yet another embodiment, a control register is used that individually identifies each scan chain included in compaction. In this embodiment, a variable number (e.g., 1, 2, 3, 4 . . . ) of test responses within scan chains may be included in compaction. Alternatively, the control register may store a unique identifier that is decoded to select one test response that is compacted. 
         [0021]    In still another embodiment, the selection circuitry includes a control line that masks bits from scan chains on a per clock-cycle basis. Consequently, a test response may have only individual bits masked while the remaining bits of the test response are compacted. 
         [0022]    The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description, which proceeds with reference to the following drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a block diagram of a prior art system for testing integrated circuits. 
           [0024]      FIG. 2  is a block diagram of a prior art system using a built-in-test system. 
           [0025]      FIG. 3  is a circuit diagram of a prior art type I LFSR compactor. 
           [0026]      FIG. 4  is a circuit diagram of a prior art type II LFSR compactor. 
           [0027]      FIG. 5  is a circuit diagram of a prior art architecture of a multiple input signature register (MISR) compactor shown receiving input from scan chains. 
           [0028]      FIG. 6  is a circuit diagram of a prior art pipelined spatial compactor. 
           [0029]      FIG. 7  is a block diagram of a selective compactor according to the invention. 
           [0030]      FIG. 8  shows one embodiment of a selective compactor, including selection circuitry and a spatial compactor, for masking test responses from scan chains. 
           [0031]      FIG. 9  is another embodiment of a selective compactor including selection circuitry and a time compactor for masking test responses from scan chains. 
           [0032]      FIG. 10  is yet another embodiment of a selective compactor including selection circuitry and a cascaded compactor for masking individual bits of test responses from scan chains. 
           [0033]      FIG. 11  is another embodiment of a selective compactor including selection circuitry and multiple compactors for masking test responses. 
           [0034]      FIG. 12  is another embodiment of a selective compactor with selection circuitry that masks any variable number of test responses from the scan chains. 
           [0035]      FIG. 13  is another embodiment of a selective compactor with programmable selection of scan chains. 
           [0036]      FIG. 14  is a flowchart of a method for selectively compacting test responses from scan chains. 
       
    
    
     DETAILED DESCRIPTION 
       [0037]      FIG. 7  shows a block diagram of an integrated circuit  24  that includes multiple scan chains  26  in a circuit under test  28 . A selective compactor  30  is coupled to the scan chains  26  and includes a selector circuit  32  and a compactor  36 . The illustrated system is a deterministic test environment because the scan chains  26  are loaded with predetermined test patterns from an ATE (not shown). The test patterns are applied to the core logic of the integrated circuit to generate test responses, which are also stored in the scan chains  26  (each scan chain contains a test response). The test responses contain information associated with faults in the core logic of the integrated circuit  24 . Unfortunately, the test responses may also contain unknown states and/or multiple fault effects, which can negatively impact the effective coverage of the test responses. For example, if a memory cell is not initialized, it may propagate an unknown state to the test response. The test responses are passed to the selector circuit  32  of the selective compactor  30 . The selector circuit  32  includes control logic  34  that controls which of the test responses are passed through the selector circuit to the compactor  36 . The control logic  34  can control the selector circuit  32  such that test responses with unknown states or multiple fault effects are masked. The control logic is controlled by one or more control lines. Although not shown, the control lines may be connected directly to a channel of an ATE or they may be connected to other logic within the integrated circuit. For example, the control lines may be coupled to a Linear Finite State Machine (e.g., LSFR type 1, LSFR type 2, cellular automata, etc.) in combination with a phase shifter. The compactor  36  receives the desired test responses from the selector circuit  32  and compacts the responses into a compressed output for analysis. The compressed output is compared against a desired output to determine if the circuit under test contains any faults. The selection circuitry, compactor, and circuit under test are all shown within a single integrated circuit. However, the selection circuitry and compactor may be located externally of the integrated circuit, such as within the ATE. 
         [0038]      FIG. 8  shows one example of an integrated circuit  40  that includes a selective compactor  42  coupled to multiple scan chains  44  within a circuit under test. Although only 8 scan chains are shown, the test circuit  40  may contain any number of scan chains. The selective compactor  42  includes a selector circuit  46  and a compactor  48 . The compactor  48  is a linear spatial compactor, but any conventional parallel test-response compaction scheme can be used with the selector circuit  46 , as further described below. The selector circuit  46  includes control logic  50 , which includes an input register  52 , shown in this example as a shift register. The input register  52  has a clock input  54  and a data input  56 . Each cycle of a clock on the clock input  54 , data from data input  56  shifts into the input register  52 . The register  52  has multiple fields including a scan identification field  58 , a “one/not one” field  60  and a “not all/all” field  62 . A control register  64  has corresponding bit positions to input register  52 , and upon receiving an update signal on an update line  66 , the control register  64  loads each bit position from input register  52  in parallel. Thus, the control register  64  also contains fields  58 ,  60 , and  62 . Although the control register  64  is shown generically as a shift register, the update line  66  is actually a control line to a multiplexer (not shown) that allows each bit position in register  64  to reload its own data on each clock cycle when the update line deactivated. When the update line is activated, the multiplexer passes the contents of register  52  to corresponding bit positions of the control register  64 . The control register  64  is then loaded synchronously with the clock. 
         [0039]    The selector circuit  46  includes logic gates, shown generally at  68 , coupled to the control register  64 . The logic gates  68  are responsive to the different fields  58 ,  60 ,  62  of the control register  64 . For example, the scan identification field  58  contains a sufficient number of bits to uniquely identify any of the scan chains  44 . The scan identification field  58  of the control register  64  is connected to a decoder, shown at  70  as a series of AND gates and inverters. The decoder  70  provides a logic one on a decoder output depending on the scan identification field, while the other outputs of the decoder are a logic zero. 
         [0040]    The one/not one field  60  of the control register  64  is used to either pass only one test response associated with the scan chain identified in the scan identification field  58  or pass all of the test responses except for the scan chain identified in the scan identification field. The all/not all field  62  is effectively an override of the other fields. In particular, field  62  controls whether all of the test responses in the scan chains  44  are passed to the compactor  48  or only the test responses as controlled by the scan identification field  58  and the one/not one field  60 . With field  62  cleared, only test responses as controlled by the scan identification field  58  and field  60  pass to the compactor  48 . Conversely, if the field  62  is set to a logic one, then all of the test responses from all of the scan chains  44  pass to the compactor  48  regardless of the scan identification field  58  and the one/not one field  60 . 
         [0041]      FIG. 9  shows another embodiment of a selective compactor  80  that is coupled to scan chains  82 . The selective compactor includes a selector circuit  84 , which is identical to the selector circuit  46  described in relation to  FIG. 8 . The selective compactor  80  also includes a time compactor  84 , which is well understood in the art to be a circular compactor. The time compactor includes multiple flip-flops  86  and XOR gates  88  coupled in series. A reset line  90  is coupled to the flip-flops  86  to reset the compactor  84 . The reset line may be reset multiple times while reading the scan chains. Output register  92  provides a valid output of the compactor  84  upon activation of a read line  94 . 
         [0042]    Referring to both  FIGS. 8 and 9 , in operation the scan chains  82  are serially loaded with predetermined test patterns by shifting data on scan channels (not shown) from an ATE (not shown). Simultaneously, the input register  52  is loaded with a scan identification and the controlling flags in fields  60 ,  62 . The test patterns in the scan chains  44 ,  82  are applied to the circuit under test and test responses are stored in the scan chains. Prior to shifting the test responses out of the scan chains, the update line  66  is activated, thus moving fields  58 ,  60 ,  62  to the control register  64 . The control register thereby controls the logic gates  68  to select the test responses that are passed to the compactors  48 ,  84 . If the field  62  is in a state such that selection is not overridden, then certain of the test responses are masked. In the example of  FIG. 8 , the spatial compactor  48  provides the corresponding compressed output serially and simultaneously with shifting the test responses out of the scan chains. Conversely, in  FIG. 9  the selective compactor  80  does not provide the appropriate compressed output until the read line  94  is activated. The selective compactor  80  provides a parallel compressed output as opposed to serial. The selective compactor  80  may be read multiple times (e.g., every eighth clock cycle) while reading out the test responses. 
         [0043]      FIG. 10  shows another embodiment of a selective compactor  100 . Again, the selective compactor includes a selector circuit  102  and a compactor  104 . The compactor  104  is a type of spatial compactor called a cascaded compactor. N scan chains  106  include M scan cells  108 , each of which stores one bit of the test response. The selector circuit  102  includes logic gates  110 , in this case shown as AND gates, coupled to a control line  112 . The compactor  104  is a time compactor with a single serial output  114 . The control line  112  is used to mask the test responses. In particular, the control line  112  either masks all corresponding scan cells in the scan chains or allows all of the scan cells to pass to the compactor  80 . The control line  112  operates to mask each column of scan cells, rather than masking an entire scan chain. Thus, individual bits from any scan chain can be masked on a per clock-cycle basis and the remaining bits of that scan chain applied to the compactor  104 . With control line  112  activated, all bits from the scan chains pass to the compactor. With control line  112  deactivated, all bits from the scan chains are masked. Although  FIG. 10  shows only a single control line, additional control lines can be used to mask different groups of scan chains. Additionally, although control line  112  is shown as active high, it may be configured as active low. 
         [0044]      FIG. 11  shows yet another embodiment of the selective compactor  120 . Automatic testing equipment  122  provides test patterns to the scan chains  124 . The scan chains  124  are a part of the circuit under test  126 . The patterns that are loaded into the scan chains  124  by the ATE are used to detect faults in the core logic of the circuit  126 . The test responses are stored in the scan chains  124  and are clocked in serial fashion to the selective compactor  120 . The selective compactor includes a selector circuit  128  and a compactor  130 . The selector circuit  128  includes control logic including an input register  132 , multiple control registers  134 ,  136 , and multiple decoders  137  and  139 . The register  132  is loaded with a pattern of bits that are moved to the control registers  134 ,  136  upon activation of an update line (not shown). The control registers  134 ,  136  are read by the decoders  137  and  139  and decoded to select one or more logic gates  138 . A flag  140  is used to override the decoders  137  and  139  and pass all of the test responses to the compactor  130 . Although only a single flag  140  is shown, multiple flags may be used to separately control the decoders. In this example, the compactor  130  includes multiple spatial compactors, such as compactors  142  and  144 . Each control register may be loaded with different data so that the compactors  142 ,  144  can be controlled independently of each other. 
         [0045]      FIG. 12  shows yet another embodiment of the present invention with a selective compactor  150 . Control logic  152  variably controls which test responses are masked and which test responses are compacted. Thus, activating the corresponding bit position in the control logic  152  activates the corresponding logic gate associated with that bit and allows the test response to pass to the compactor. Conversely, any bit that is not activated masks the corresponding test response. 
         [0046]      FIG. 13  shows another embodiment of a selective compactor  156  including a selector circuit  158  and compactor  160 . In this case, an input shift register  162  having a bit position corresponding to each scan chain  164  is used to selectively mask the scan chains. A clock is applied to line  166  to serially move data applied on data line  168  into the shift register  162 . At the appropriate time, an update line  165  is activated to move the data from the shift register to a control register  169 . Each bit position that is activated in the control register  169  allows a test response from the scan chains  164  to pass to the compactor. All other test responses are masked. Thus, the selective compactor can mask any variable number of test responses. 
         [0047]    Each of the embodiments described above can be used as a diagnostic tool for localizing faults in the circuit under test. For example, each test response can be analyzed individually by masking all other test responses in the scan chains connected to the same compactor. By viewing the test response individually, the bit position in the test response containing fault effects can be determined. 
         [0048]      FIG. 14  shows a flowchart of a method for selectively compacting test responses. In process block  170 , an ATE loads predetermined test patterns into scan chains within an integrated circuit. This loading is typically accomplished by shifting the test patterns serially into the scan chains. The test patterns are applied to the circuit under test (process block  172 ) and the test responses are stored in the scan chains (process block  174 ). In process block  176 , the selector circuit controls which test responses are masked. In particular, the selector circuit controls which scan chains are masked or which bits in the scan chains are masked. For example, in  FIG. 8 , the selector circuit masks the entire scan chain that is identified in the scan identification field  58 . In  FIG. 10 , only individual bits of a scan chain are masked. In any event, in process block  176 , the selector circuit typically masks unknown data or multiple fault effects so that the desired fault effect can propagate to the output (in some modes of operation, all of the test responses may pass to the output). In the event that the selector circuit includes a control register, the control register may be loaded concurrently with loading the test patterns in the scan chains or it can be loaded prior to reading the test responses. In process block  178 , the test responses (one or more of which have been masked) are passed to the compactor and the compactor generates a compressed output associated with the test responses. In process block  180 , the compressed output generated by the compactor is compared to an ideal response. If they match, the integrated circuit is assumed to be fault free. 
         [0049]    Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles. For example, any of the illustrated compactors can be used with any of the illustrated selector circuits with minimum modification to create a selective compactor. Additionally, the selector circuit can easily be modified using different logic gates to achieve the selection functionality. For example, although the update lines are shown coupled to a separate bank of flip flops, the update lines can instead be coupled to input registers having tri-state outputs for controlling the logic in the selector circuit. Still further, although the scan chains are shown as serial shift registers, logic may be added so as to output test response data in parallel to the selective compactor. Additionally, although multiple spatial and time compactors were shown, compactors having features of both spatial and time compactors may be used. Indeed, any conventional or newly developed compactor may be used with the selection circuitry. 
         [0050]    In view of the many possible embodiments, it will be recognized that the illustrated embodiments include only examples of the invention and should not be taken as a limitation on the scope of the invention. Rather, the invention is defined by the following claims. We therefore claim as the invention all such embodiments that come within the scope of these claims.