Abstract:
An isolated forward switching power converter includes a primary side circuit and a secondary side circuit having an output inductor, a first MOS gated transistor coupled in series with the output inductor, a second MOS gated transistor coupled in shunt relationship with the output inductor, and a synchronous rectifier control circuit which senses the voltage across the output inductor and alternately biases the first and second transistors on and off in response thereto.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is based on U.S. Provisional Patent Application No. 60/017,962, filed May 20, 1996, entitled SYNCHRONIZING/DRIVING CIRCUIT FOR A FORWARD SYNCHRONOUS RECTIFIER. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a synchronizing and driving circuit for a forward converter employing a synchronous rectifier. 
     2. Related Art 
     In known forward switching power supply circuits employing synchronous rectifiers, the secondary side diodes are replaced by transistors to obtain a lower on-state voltage drop. The transistors must be biased to conduct from source to drain (for an N-channel power MOSFET) when a diode would have been conducting from anode to cathode, and conversely, must be gated to block voltage from drain to source when a diode would have been blocking from cathode to anode. 
     In these known synchronous rectifier circuits, the gate signals to the transistors must be synchronized as close as possible to the inflection points of the output inductor current, which inflection points correspond to the zero crossings of the squarewave output inductor voltage. The gate signals can be &#34;self-driven&#34; (i.e., the gate signal is tied directly to the circuit) or &#34;controlled synchronized&#34; (i.e., a synchronizing signal is derived from some point in the circuit and fed to a MOSFET gate driver). 
     Examples of prior art synchronous rectifiers may be found in U.S. Pat. Nos. 4,903,189 to Ngo, et al.; 5,430,640 to Lee; and 5,457,624 to Hastings; and in the following articles: &#34;Synchronous Rectifiers Improve Efficiency in Low Output Voltage Forward Converters&#34; by Clemente, et al. (pp. 347-350) and &#34;The Impact of Low Output Voltage Requirements on Power Converters&#34; by Jitaru, HFPC, May 1995 Proceedings (pp. 1-10). 
     Some synchronous rectifier circuits of the prior art monitor the primary side control signals and transfer such signals to the secondary side of the power converter (i.e., across the isolation boundary) in order to synchronize the gating of the synchronous transistors. Unfortunately, costly, non-optimal and complex circuitry is required to maintain isolation between primary and secondary portions of the circuit. For example, when opto-isolators are used to maintain isolation, undesirable delays and unpredictable gain variations introduce errors in the system. 
     Other synchronous rectifier circuits of the prior art use additional transformer windings to transfer synchronizing information to the secondary circuit transistors an still maintain isolation. However, such transformers are more costly and complex and a transformer reset problem also arises. 
     Accordingly, there is a need in the art for a new synchronous rectifier circuit which does not require opto-couplers or additional transformer windings to transfer synchronizing information across the isolation boundary between primary and secondary circuits in a forward power converter. 
     SUMMARY OF THE INVENTION 
     In order to overcome the disadvantages of the prior art synchronous rectifier circuits, the present invention provides &#34;self-driven&#34; gate signals produced by monitoring the voltage across the output inductor of the converter and alternately gating the transistors in response to transitions of the inductor voltage such that one transistor is always on when the other is off, and vice versa. 
     Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For the purpose of illustrating the invention, there is shown in the drawings forms which are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
     FIG. 1 is a circuit diagram partially in block form of a synchronous rectifier in accordance with the invention. 
     FIG. 2 is an equivalent circuit of a secondary circuit of FIG. 1 during a first mode of operation. 
     FIG. 3 is an equivalent circuit of the secondary circuit of FIG. 1 in a second mode of operation. 
     FIG. 4 illustrates waveforms at various points during operation of in the circuit of FIG. 1. 
     FIG. 5 shows the circuit of FIG. 1 with a comparator shown in the block diagram in FIG. 1 shown in detail in FIG. 5. 
     FIG. 6 shows an alternative embodiment of the comparator of FIG. 5. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings wherein like numerals indicate like elements, there is shown in FIG. 1 a synchronous rectifier 10 in accordance with the invention which includes a primary circuit 20 and a secondary circuit 30. The primary circuit 20 includes a voltage source V in , a primary winding 11 of a transformer 12, a switch S p , a reset winding 13 for resetting the core of the transformer 12 and a reset diode D r . The switch S p , for simplicity, is shown as a single pole, single-throw switch; in actuality, however, the switch may be a conventional MOS-gated semiconductor switch, such as power MOSFET or insulated gate bipolar transistor (IGBT). 
     The secondary circuit 30 includes a secondary winding 14, an output inductor L, and output capacitor C, a first power transistor S 1 , and a second power transistor S 2 . Each power transistor S 1 , S 2  includes an anti-parallel diode thereacross. 
     A comparator 40 is connected across the output conductor L for sensing the voltage thereacross, V L , that, is, for sensing the difference in potential between the voltages V A  and V out . The comparator 40 has an output connected to the gate of the transistor S 1  and an inverted output connected to the gate of the transistor S 2 . 
     When the voltage V L  across the inductor L is positive, the transistor S 1  is biased on and the transistor S 2  is biased off. Conversely, when the voltage V L  is negative, the transistor S 2  is biased on and the transistor S 1  is biased off. 
     Thus, the rectifier 10 has two modes of operation. In the first mode, Mode 1, the transistor S 1  is on and conducting current and the transistor S 2  is off and blocking current. In the second mode, Mode 2, the transistor S 1  is off and blocking current and the transistor S 2  is on and conducting current. 
     A better understanding of Mode 1 may be had by referring to the equivalent circuit of FIG. 2 in which V S  represents the voltage across the secondary winding 14, transistor S 1  is represented by an ideal diode S 1 , and the output voltage is represented by an output voltage source V O . The relationship between the various voltages is as follows: V S  =V L  +V O , and V L  =V S  -V O . Since V S  is greater than V O , V L  is thus positive. 
     Also, I L  in Mode 1 is ramping up or increasing. Accordingly, ##EQU1## is positive. Since ##EQU2## this analysis also shows that V L  is positive in Mode 1. 
     Mode 2, in which the transistor S 1  is blocking current and the transistor S 2  is conducting current, may be represented by the equivalent circuit shown in FIG. 3, where the transistor S 2  is represented by the ideal diode S 2 . As in the equivalent circuit for Mode 1, V S  =V L  +V out  and, therefore, V L  =V S  -V out . Here, V A  is zero volts which is less than V o  ut and, therefore, V L  is negative. Also, in Mode 2, I L  is decreasing or ramping down. Accordingly, ##EQU3## is negative. Since ##EQU4## this analysis also indicates that V L  is negative in Mode 2. 
     Waveforms occurring at different points in the circuit of FIG. 1 during operation are shown in FIG. 4. 
     Turning now to FIG. 5, there is shown a detailed implementation of the comparator 40 of FIG. 1 which includes a non-inverting transistor comparator Q 1  and associated (push-pull) driver transistors Q 3  and Q 4 , and an inverting transistor comparator Q 2  and associated (push-pull) driver transistors Q 5  and Q 6 . The transistors Q 1  and Q 2  respond to the voltage V sense  with respect to ground, where V sense  changes as a function of V L  and V A . 
     In Mode 1, V A  is greater than V out  (i.e., V A  =V in  ·(N S  /N p )) and, therefore, V sense  is a positive voltage approximately equal to V out  +V fd1 , where V fd1  is the forward voltage drop across the diode D 1 . This results in the transistor Q 1 , being biased on and Q 2  being biased off. The output from the emitter of Q 1  is therefore a positive voltage which causes Q 3  to turn on and Q 4  to turn off. Accordingly, the voltage at the gate of S 1  rises to about V ZZ  and S 1  turns on. Conversely, the output from the collector of Q 2  is about zero volts which causes Q 6  to turn on and sweep the charge off the gate of S 2  and turn it off. 
     In Mode 2, V A  is less than V out  (i.e., V A  ˜0 volts) and, therefore, V sense  =V A  ˜0 volts. This results in transistor Q 1  being biased off and Q 2  being biased on. The output from the collector of Q 2  is therefore a positive voltage which causes Q 5  to turn on and Q 6  to turn off. Accordingly, the voltage at the gate of S 2  rises to about V ZZ  and S 2  turns on. Conversely, the output from the emitter of Q 1  is about zero volts which causes Q 4  to turn on and sweep the charge off the gate of S 1  and turn it off. 
     Thus, the gating of S 1  and S 2  is a function of the voltage V L  across the inductor L, that is, when V L  is positive, S 1  is biased on (the gate of S 1  is positive with respect to its source) and S 2  is biased off (the gate of S 2  is low with respect to its source). When V L  is negative, on the other hand, S 1  is biased off and S 2  is biased on. 
     Advantageously, the gate of the transistors are &#34;self driven&#34; by sensing conditions in the secondary circuit 30, namely the inductor voltage, V L . Thus, there is no need for expensive, unpredictable and slow opto-isolators or additional windings in the transformer 12. Further, the efficient utilization of discrete components obviates the need for expensive integrated circuit type comparators. 
     It is noted that diode D 1  advantageously limits the voltage at V sense  to one diode drop above V out  which also limits the voltage input to Q 1  and Q 2 . Thus, the circuit is immune to back oscillation at peak values of V A  because such peak values are not fed back in the circuit of the present invention. Further, by limiting maximum excursions of V sense  to about V out , the transistors are off when V out  is under voltage (i.e. when V out  is less than 1) thereby providing for enhanced start up characteristics of the converter. 
     It is noted that D 1  allows an extra diode drop of driving voltage for driving Q 1  -Q 6  (i.e., V sense  =V out  +V fD1 ). Nonetheless, if V out  is designed to be a very low output which would not allow proper drive voltage to Q 1  -Q 6 , then the cathode of diode D 1  may be connected to V ZZ . Thus, a higher voltage would be obtained to drive Q 1  -Q 6  (i.e., V sense  =V ZZ  +V FD ) 
     Capacitors C 1  and C 2  are used to introduce respective time delays into the circuits of Q 1  and Q 2  in order to provide a requisite deadtime. 
     The reason for deadtime is as follows: The synchronous rectifier gate signals needs to be synchronized as closely as possible to the transitions in V L  (i.e., the zero crossing points). If the respective gates are on too long (i.e., turned on early, turned off late), current overshoot or oscillation due to cross conducting between S 1  and S 2  can occur. If the respective gates are turned on too late or turned off too early, the anti-parallel diode of the power MOSFETs will conduct giving higher conduction losses while it conducts and reverse recovery effects when turned off as the voltage swings to the opposite polarity. 
     Thus, to avoid cross-conduction, when V A  is greater than V out , the transistor S 1  turns on after a deadtime and the transistor S 2  turns off. Conversely, when V A  is less than V out , the transistor S 1  turns off and the transistor S 2  turns on after a deadtime. Advantageously, the amount of deadtime can be predetermined to allow for designs having different types of power MOSFETs. 
     The resistor R 8 , capacitor C 3  and diode D 2  serve as a driving power source or auxiliary source of DC power. Alternatively, V out  can be used as V ZZ  if V out  is high enough to provide sufficient drive voltage to the gates of S 1  and S 2  to reduce the forward resistance thereof (i.e., to fully enhance the transistors S 1  and S 2 ). 
     R 8  serves as a bleeding resistor to charge C 3 . C 3  provides the current to the circuit and maintains V ZZ  according to the breakdown voltage V D2  of the zener diode D 2 . If V A  is greater than V D2  then V ZZ  is approximately equal to the breakdown voltage of the zener diode D 2 . On the other hand, if V A  is less than VD 2 , then V ZZ  is approximately equal to the peak value of V A . 
     Advantageously, the V ZZ  supply permits driving the power MOSFETs with high enough voltage to fully enhance the devices and lower their forward resistances. This mitigates the need for an extra winding on the transformer or an extra power supply. 
     FIG. 6 shows an alternative embodiment 40&#39; of the comparator 40 of FIG. 5. In the embodiment of FIG. 6, FET transistors Q 7  -Q 11  are used in place of the bipolar transistors Q 1  -Q 6  of FIG. 5. Operation of this embodiment is essentially the same as the embodiment of FIG. 5. More specifically, when V A  is greater than V out , a high voltage is inputted to the gate of S 1  and a low voltage is inputted to the gate of S 2 . Conversely, when V A  is less than V out , a low voltage is applied to the gate of S 1  and a high voltage is applied to the gate of S 2 . 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.