Abstract:
In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a continuation of U.S. application Ser. No. 12/621,703, filed Nov. 19, 2009 (now U.S. Pat. No. 7,949,078), which is a continuation of U.S. application Ser. No. 10/961,004, filed Oct. 7, 2004 (now U.S. Pat. No. 7,643,583), which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 60/599,724, filed Aug. 6, 2004. The disclosures of the applications referenced above are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a signal detector circuit for a high-speed receiver. More particularly, this invention relates to a signal detector circuit that operates asynchronously of the received data and at a lower frequency, but nevertheless detects with high-precision the presence of incoming data. 
     High-speed receivers, such as are used in 10 Mbps (i.e., 10BASE-T) and 100 Mbps (i.e., 100BASE-T) Ethernet applications compliant with the IEEE 802.3 standard, gigabit Ethernet (i.e., 1000BASE-T) applications (IEEE 802.3ab), and 10 Gigabit Ethernet (i.e., 10GBASE-T) applications (IEEE 802.3an), are frequently idle, insofar as there may not be incoming data to process. (All references herein, including in the claims that follow, to any IEEE standard, is a reference to the version of that standard current on the filing date hereof.) It therefore would be desirable to be able to turn off such a receiver—e.g., to conserve power—until such time as incoming data are present. However, if the receiver were turned off, it would be desirable to be able to reliably turn on the receiver when data begin to arrive. 
     SUMMARY OF THE INVENTION 
     In accordance with this invention, a signal detector for detecting the presence of incoming data is provided. The signal detector according to the invention may be used as a trigger to activate, on the arrival of incoming data, a receiver that in the absence of data has been turned off, or placed in a low-power mode. Although the frequency of the incoming data may be high, such as in the gigabit Ethernet example above, it is desirable for the signal detector to operate at low power as part of the low-power mode of the receiver. Therefore, in accordance with the invention, the signal detector preferably operates at a lower clock speed than the incoming data to conserve power, and also preferably operates asynchronously of the incoming data to avoid the need to perform clock recovery operations on the incoming data. This allows the clock recovery portion of the receiver to remain in the low-power mode, along with most of the receiver, to maximize power savings. Essentially the only portions of the receiver that need to remain powered up preferably are the signal detector of the present invention, and a bias current generator. 
     The signal detector preferably compares an incoming signal to a preferably precisely-generated reference voltage and preferably generates a pulse when the incoming signal has an amplitude exceeding the reference voltage. Preferably, the detector is triggered whether the incoming signal is positive or negative, as long as its absolute value exceeds the reference voltage. If the incoming signal is a differential signal, as is the case in many high-speed signal protocols (e.g., Low-Voltage Differential Signaling, or LVDS, is one such protocol), then preferably the common mode of the reference signal is matched as closely as possible to the common mode of the differential input signal. The comparison of the input signal preferably is achieved by subtracting the input signal from the threshold value, and preferably also, in case the input signal is negative, by subtracting the inverse of the input signal from the threshold value. 
     Those differences preferably are sampled at a sampling frequency, generated in the signal detector, that is lower than, and asynchronous to, the data frequency. However, if the sampling frequency, as generated locally, turns out, by chance, to be an integer fraction of the data frequency, and if, also by chance, the first sample is at or near a zero crossing of the data signal, so that it does not exceed the threshold, then each subsequent sample also will be at or near a zero crossing, and the signal detector may fail to recognize a valid incoming data signal. 
     Therefore, the clock generator according to the present invention preferably varies its frequency slowly between a minimum sampling frequency and a maximum sampling frequency. This is achieved, in one preferred embodiment, by providing a first oscillator, such as a ring oscillator, to generate the local clock. Each stage of the ring oscillator preferably includes a resistance and a capacitance that determine the local oscillator frequency. Each capacitance preferably includes a first capacitor between the resistance and ground, and a second capacitor between the resistance and a second, slower oscillator circuit (which may, e.g., be another ring oscillator). As the second, slower oscillator oscillates, it varies the voltage at its end of the second capacitor, which varies the contribution of the second capacitor to the overall capacitance, thereby varying the frequency of the first oscillator and the frequency of the local clock. As the local clock varies, even if on some local clock cycles the sampling time occurs at or near a zero crossing in the incoming signal, the sampling time will move out of that region of the incoming data signal on a subsequent local clock cycle and so will detect the incoming data signal after at most a short delay. 
     The outputs of both samplers—i.e., the sampler monitoring the excess of the signal over the threshold and the sampler monitoring the excess of the inverted signal over the threshold—preferably are input to an OR-gate, so that the presence of a signal results in the output by the OR-gate of a logic “1” regardless of the polarity of the signal. 
     If the OR-gate outputs a logic “1”, meaning that a signal has been detected, then without more that signal will remain only high for one cycle of the local clock generator. That interval may be insufficient for activating the remainder of the receiver. Therefore, in accordance with the invention the output pulse preferably is stretched. 
     Thus, in accordance with the present invention there is provided a method of detecting a received signal having a signal amplitude and a signal frequency. The method includes comparing the signal amplitude to a threshold to generate a comparison signal that has having a first amplitude when the signal amplitude exceeds the threshold and a second amplitude when the signal amplitude fails to exceed the threshold. A sampling clock is generated having a sampling frequency that varies between a minimum sampling frequency and a maximum sampling frequency. The comparison signal is sampled at intervals determined by the sampling frequency. A detection signal is outputted when the sampled comparison signal has the first amplitude. Variation of the sampling frequency prevents detection failures resulting from repeated sampling of a signal in a region thereof wherein the signal amplitude fails to exceed the threshold. 
     A system operating in accordance with the method is also provided. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a schematic representation of a data signal to be detected by a detector in accordance with the invention; 
         FIG. 2  is a schematic diagram of a preferred embodiment of a signal detector in accordance with the invention; 
         FIG. 3  is a schematic diagram of a preferred embodiment of a reference generator for use in the signal detector of  FIG. 2 ; 
         FIG. 4  is a schematic diagram of a preferred embodiment of a subtractor for use in the signal detector of  FIG. 2 ; 
         FIG. 5  is a schematic diagram of a preferred embodiment of pulse stretcher for use in the signal detector of  FIG. 2 ; 
         FIG. 6  is a schematic diagram of a preferred embodiment of a clock generator for use in the signal detector of  FIG. 2 ; and 
         FIG. 7  is a graph of the output of a low-speed oscillator within the clock generator of  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described with reference to  FIGS. 1-7 . 
       FIG. 1  shows a generic digital signal  10  of a type with which the present invention may be used. As is conventional, signal  10  is represented by two traces  11 ,  12  which alternatively may represent either the signal pair of a differential signal as described above, or, for a single-ended signal, the fact that any particular pulse may be positive-going or negative-going. Level  13  represents the common mode of signal  10 , which may or may not be 0 volts. 
     As seen in  FIG. 1 , signal  10  includes a number of periods  14  in which pulses may occur, based on the signal frequency, f 0 , separated by zero-crossings  15 . The periods  14  are sometimes referred to as “data eyes” because of their shape. 
     A preferred embodiment of a signal detector  20  in accordance with the present invention is shown in  FIG. 2 . As discussed above, signal detector  20  preferably is part of a larger receiver circuit (not shown) which, for power conservation purposes, is mostly shut down during periods when no incoming signal is present. Such a receiver must be able to react quickly when a signal arrives, but if it reacts too indiscriminately, turning on when there is in fact no incoming signal, the power savings may be reduced. Therefore, it is desirable to be able to quickly and accurately detect an incoming signal so that the receiver can be turned on at the appropriate time. Signal detector  20  is designed to perform that function. 
     In the case of a differential digital signal  10  as shown in  FIG. 1 , except in the vicinity of zero-crossings  15 , the signal will be both +1 and −1. The actual voltage will depend on the particular signaling scheme in use (e.g., 5 volts for older schemes, or 3.3 volts or less for newer schemes). For an analog signal, the value between zero-crossings will vary regularly between 0 and +1 or between 0 and −1. In any case, the best way to determine if a signal is present is to detect a voltage with a sufficient absolute value to give confidence that it is not noise, such as threshold value  16 . 
     In the case of an analog signal (e.g., a sine wave), the sampling point might have to be somewhat farther from a zero-crossing  15  to exceed threshold  16 . Thus, it is desirable that sampling not occur too close to a zero-crossing  15 . Otherwise, even in the presence of a valid signal, the detector will “think” that no signal is present. 
     As set forth above, signal detector  20  preferably operates asynchronously of the incoming data, and at a slower frequency, to conserve power, and because any clock recovery circuitry in the receiver preferably is powered down along with most of the remainder of the receiver, so that synchronous operation is not even possible. Thus, it is possible that by chance, even if a valid signal is present, sampling will occur in the vicinity of a zero-crossing  15 . And if the sampling frequency, again by chance, is an integer fraction, f 0 /n, of the data frequency f 0 , subsequent samples will continue to occur in the vicinity of a zero-crossing  15 , and the signal will not be detected. Even if the sampling frequency is different from, but nevertheless close to, f 0 /n, it may be many cycles before the sampling point moves far enough from a zero-crossing  15 , resulting in unacceptable delay in detecting the signal, even though ultimately it will be detected. 
     In accordance with the present invention, as discussed in more detail below, the sampling frequency is varied so that even if a sample occurs in the vicinity of a zero-crossing  15 , on a subsequent cycle the sampling point will have moved sufficiently far from zero-crossing  15  that the signal can be detected. 
     Signal detector  20  as shown in  FIG. 2  is designed for a differential signal, but it will be recognized that signal detector  20  can be used essentially without modification with a single-ended signal (digital or even analog) by grounding one of the two input leads  21 . Alternatively, the second signal path can be omitted if the signal detector is designed specifically for a single-ended application. 
     Signal  10 , input at  21 , is compared at comparison signal generator circuitry  22  to a reference voltage generated by reference voltage generator  23 . It is preferable that in the case of a differential signal  10 , the reference voltage have a common mode identical or nearly identical to the common mode of signal  10 , so that an accurate difference is compared to the threshold level. A preferred embodiment  30  of a reference voltage generator capable of generating a reference signal with the appropriate common mode value is shown in  FIG. 3 . 
     Reference voltage generator  30  preferably includes a two-stage amplifier  31 , a constant current source  32  and resistor ladder  33  connected between constant current source  32  and the output of two-stage amplifier  31 . It is preferable that all resistors in resistor ladder  33  have the same resistance value, but it is only necessary the members of each pair of resistors about midpoint  330  have identical values. Thus, both resistors  331  preferably have the same value, both resistors  332  preferably have the same value, both resistors  333  preferably have the same value, and both resistors  334  preferably have the same value. For a differential reference voltage, the “upper” and “lower” components preferably are tapped from a pair of taps  34 ,  35  symmetrical about midpoint  330 . 
     Two-stage amplifier  31  preferably includes a first amplifier stage  310  having two inputs  311 ,  312 , and an output  313 , and a second amplifier stage  314  having one input  315  which is connected to first-stage output  313 , and having a second-stage output  316 . A floating compensation capacitor  317  is connected between second-stage output  316  and second-stage input  315  to prevent oscillation in reference voltage generator  30 . 
     One input  311  of first amplifier stage  310  preferably is connected to midpoint  330 , while the other input  312  of first amplifier stage  310  preferably is connected to upper and lower components of the input voltage at  21  by respective resistors  318 ,  319  having identical, relatively large resistance values (e.g.,  20   k   0 . This arrangement keeps midpoint  330 , which one can see is the common mode of the reference voltage at  34 ,  35 , substantially equal to the common mode of the voltage input at  21 . However, any arrangement that provides the desired common mode may be used. 
     Comparison signal generator circuitry  22  compares the input voltage at  21  to the reference voltage at  34 ,  35 . Preferably, both the input voltage and the inverse of the input voltage are compared to the reference voltage so that effectively the absolute value of the input voltage is being compared to the reference voltage. That way, even if the input voltage is negative-going at the sampling point, if its magnitude exceeds the threshold, the signal is detected. Preferably the comparison is a simple subtraction of the reference voltage from the input voltage and from its inverse. A preferred embodiment of a suitable subtractor  40 , using two differential pairs that subtract currents at their common drains. Two subtractors  40  are used in comparison signal generator circuitry  22 , as seen in  FIG. 2 , one each for the positive and inverted subtractions. 
     It will be apparent that for a single-ended signal (including an analog signal), input  312  of first amplifier stage  310  can be grounded so that the common mode of reference voltage generator  30  becomes ground, and the reference voltage output can be taken from a desired one of taps  34  only. In such a single-ended case, the subtractor preferably would be a single differential pair, with the signal connected to one side and the difference output from the other side. 
     The comparison signals generated by circuitry  22  are input to a comparator  29 . Preferably, comparator  29  includes two samplers  24 , and summer or OR-gate  26 . Samplers  24 , when activated on each cycle of sampling clock generator  25 , test whether the signal from either subtractor  40  is non-zero. If so, the corresponding one of samplers  24  outputs a logic “1” signal. The two sampler outputs  240  are summed or ORed by summer or OR-gate  26 , so that if either output  240  is high, detector  20  outputs a high signal  241 . Summer or OR-gate  26  may also serve as a preamplifier for the output signal. 
     Although comparator  29  is shown as including samplers  24  and summer or OR-gate  26 , any suitable comparator may be used. A different comparator, for example, may not share the common mode requirements of the embodiment described. However, such a comparator preferably would still sample the comparison signals at intervals determined by sampling clock generator  25 . 
     It is desirable that signal  241  be high long enough to activate the remainder of the receiver. A suitable duration might be twice the period of the clock used in the logic circuit involved—e.g., in the case of a receiver (not shown) having a physical coding sublayer (PCS) sampling clock of 40 ns, signal  241  preferably should be high for 80 ns. To achieve that result, pulse stretcher  27  preferably elongates the duration of signal  241 . One preferred embodiment  50  of pulse stretcher  27  is shown in  FIG. 5 . 
     In pulse stretcher  50 , signal  241  preferably is input to both a strong NMOS transistor  51  and a weak PMOS transistor  52 , having a shared output  53  connected both to Schmitt trigger  54  and to ground through capacitor  55 . If signal  241  goes high, strong NMOS transistor  51  will quickly discharge capacitor  55 , causing Schmitt trigger  54  to hold a zero output  540  which is inverted by inverter  56  to produce a high on signal detect output  28 , which will remain until capacitor  55  can be recharged to change the state of Schmitt trigger  54 . However, when signal  241  goes low, it will have to remain low for many clock cycles before weak PMOS transistor  52  can recharge capacitor  55 . During all that time, Schmitt trigger output  540 , and therefore signal detect output  28 , will remain unchanged. Thus, output  28  quickly reflects a signal detection, but does not return to a low state for several clock cycles, to allow sufficient time for the remainder of the receiver to be turned on. Preferably, that function is performed by the PCS of the receiver (not shown). 
     A preferred embodiment  60  of a sampling clock generator  25  is shown in  FIG. 6 . Sampling clock generator  25  preferably includes a main oscillator  61  and a low-speed oscillator  62 . Preferably, both oscillators  61 ,  62  are three-stage ring oscillators. Each ring oscillator  61 ,  62  preferably includes a NAND-gate  600  in its respective ring which can be used to turn off clock generator  25  by applying a “0” at input  601  to force a “1” output from each NAND-gate  600  and thereby stop each oscillator  61 ,  62  from oscillating. 
     Each stage  63  of ring oscillator  61  includes an RC circuit  64  that governs the frequency of output  65 . RC circuit  64  preferably includes a resistor or other resistance  40  and two capacitors  641 ,  642 . Each capacitor  642  preferably is connected between resistor  640  and ground, while each capacitor  641  preferably is connected between resistor  640  and the output of oscillator  62 . As the output voltage  70  (see  FIG. 7 ) of oscillator  62  varies, the voltage across each capacitor  641  varies as well, changing its contribution to the total capacitance of its respective RC circuit  64 , and therefore changing the frequency of output  65  between a minimum sampling frequency (f min ) and a maximum sampling frequency (f max ). For the frequency (f slow ) of output  70  to ensure that main oscillator output  65  spends enough time at f min  or f max , thus ensuring that the output frequency is sufficiently off from an integer fraction of f 0 , f slow  preferably is less than half the difference between f max  and f min . 
     Thus, it can be seen that local clock generator  25  generates a sampling clock that varies in frequency, so that the sampling point will not remain in the vicinity of a zero-crossing  15  for more than one, or a small number, of clock cycles. 
     The signal detector of the present invention may be used with any serial data receiver, including those in high-speed fiber channel transceivers for the physical layer of a TCP/IP stack, but also any other high-speed serial interface, whether differential or single-ended, and whether fiber-based or copper- or other metal-based. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.