Abstract:
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gate of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a transconductance circuit, suitable for use in an amplifier. 
   BACKGROUND OF THE INVENTION 
   It is often necessary to amplify an signal. A simple amplifier stage is shown in  FIG. 1  wherein a field effect transistor  1  has an impedance  2  connected between its drain terminal and a positive supply rail  3 . A source terminal of the field effect transistor  1  may be connected to a negative supply or ground rail either directly as shown or via a further impedance. A gate of the field effect transistor  1  is supplied with a DC bias voltage from a bias generating circuit  4  and an AC signal to be amplified which is decoupled from the bias circuit  4  via a decoupling capacitor  5 . 
   For an ideal transconductor the current flowing in a current flow path through the transconductor would be linearly related to a control voltage applied to a control terminal of the transconductor, and the transconductor draws no current at its control terminal. 
   However, real transistors have characteristics which differ significantly from idealised devices. The field effect transistor is commonly used in transconductance amplifiers because it&#39;s input impedance is high. However it is well known that a field effect transistor has a drain-source current I D  which for an idealised transistor exhibits the following characteristics
 
 I   D =0 when V gs −V th &lt;0  Equation 1
 
where
         V gs =gate source voltage   V th =threshold voltage of the FET       

   In a so called “linear region”, also known as a “triode region” of the device characteristic where V DS  is greater then zero but less than (V gs −V th ) the drain current is as follows: 
                   I   D     =     β   ⁡     (         (       V   gs     -     V   th       )     ⁢     V   DS       -       V   DS   2     2       )               Equation   ⁢           ⁢   2               
where:
         β is a constant which, amongst other things is proportional to the ratio of the FET channel width to the channel length.   V DS =drain-source voltage.       
   However once V DS  exceeds (V gs −V th ) the device enters its saturation region where 
                   I   D     =       β   2     ⁢       (       V   gs     -     V   th       )     2               Equation   ⁢           ⁢   3               
Following on from these idealised equations, we see that in the saturation region, the transconductance g m  is
 
   
     
       
         
           
             g 
             m 
           
           = 
           
             
               
                 ⅆ 
                 
                   I 
                   D 
                 
               
               
                 ⅆ 
                 
                   V 
                   gs 
                 
               
             
             = 
             
               β 
               ⁡ 
               
                 ( 
                 
                   
                     V 
                     gs 
                   
                   - 
                   
                     V 
                     th 
                   
                 
                 ) 
               
             
           
         
       
     
   
   However, real devices can deviate from these ideal characteristics. 
     FIG. 2   a  illustrates a transfer characteristic of a NMOS FET constructed having a gate dimension of 100 μm by 0.18 μm fabricated using a 0.18 μm CMOS technology as typically found in an integrated circuit, and showing the drain current as a function of the gate-source voltage. It will be seen that the transistor is essentially non conducting until the gate-source voltage exceeds the threshold voltage of the transistor which in this example is around 0.4 volts. From then on the current rises in a non linear manner until a gate-source voltage which is approximately 1 volt is reached and from then on the curve is approximately linear. In this final region the second and third order derivatives of drain current with respect to gate-source voltage have become reasonably small. However, these are all qualative rather than quantative assessments of the transistor&#39;s performance. It should also be noted that operating a transistor in this region can be relatively power hungry. 
   In these examples the drain-source voltage was held fixed at 1 volt. 
   The linearity of the response can be examined by looking at the derivatives of the curve I DS  versus V GS  shown in  FIG. 2   a .  FIG. 2   b  shows the first derivative of drain current with respect to gate-source voltage, i.e. the transconductance, and it can be seen that between 0.5 volts and approximately 0.7 volts there is quite a marked change in the rate of change of current with respect to gate-source voltage corresponding to the curved area generally designated  6  in  FIG. 2   a . In this region the gradient of the curve looks substantially constant. However from about 1.2 volts onwards the first derivative is substantially constant.  FIGS. 2   c  and  2   d  show the second derivative and the third derivative of the transfer characteristic of the transistor. These higher order derivatives represent sources of harmonic distortion when amplifying a signal, and represent sources of inter-signal mixing i.e. the creation of inter-modulation products when two or more signals having distinct frequencies are presented to the amplifier. 
   It is known that the distortion in small signal amplifiers can be represented by a Taylor series. If we consider only the lower order components of such an expansion, we have
 
 I   D   ≈I   DO   +g   1   V   in   +g   2   V   in   2   +g   3   V   in   3 
 
where
 
             g   n     =       ⅆ     I   n         ⅆ     V   gs   n               
Where
         n=1, 2, 3 . . .       
   It is known that the distortion resulting from the second derivative or the distortion resulting from the third derivative can be reduced to substantially zero provided the individual transistor is biased to a specific biased voltage which, unfortunately, is unique to that transistor. Thus, if a batch of identical circuits are made in a fabrication process, tiny variations from wafer to wafer and indeed from one transistor to another transistor within the same integrated circuit would mean that each transistor would have a slightly different bias point for, for example, reducing the third order derivative to zero even though the transistors were nominally identical. 
   Even so, it can be seen that if a transistor is biased to a point where the 3rd derivative is zero, the second derivative is still likely to have a significant non-zero value. Therefore this approach merely trades one source of distortion for another. In circuits, like that shown in  FIG. 1 , where no feedback is provided, the dominant source of third-order intermodulation products (IM 3 ) is the 3rd order non-linearity, g 3  shown in  FIG. 2   d . reducing g 3  can be achieved, for example, by biasing the transistor to the point where g 3  is zero. 
   In circuits having feedback the situation can become more complex. For transistors having a series-series feedback scheme (i.e. an impedance placed between the source terminal and ground) then there are two dominant mechanisms giving rise to third-order intermodulation products. These are
         1) 3rd order non-linearity within the transistor as characterised by g 3 .   2) 2nd order non-linearity as characterised by g  2 .       

   One might suppose that linearity could be achieved by merely operating a relatively large gate-source voltages where the drain -source current tends to become a linear function of the gate source voltage. Whilst this can work, it is a power hungry solution that is not suitable for a large number of applications, such as mobile radio or mobile telephones. 
   These non-linearities are particularly undesirable in amplifiers, such as radio frequency amplifiers, which may be required to amplify a relatively weak wanted signal, designated S in  FIG. 3 , in the presence of stronger interfering signals designated I 1  and I 2 . In the scenario shown in  FIG. 3  the frequency difference between the wanted signal S and the first interferer I 1  is the same as the frequency difference between the interferer I 1  and a second interferer I 2.  Thus non-linearities within the amplifier stage give rise to mixing of the interfering signals Iand I 2  such that a new interfering signal I 3  is generated within the amplifier which has the same frequency as the wanted signal S and which, as a consequence may impact on the ability of the receiver to recover the wanted signal S or which may inhibit reception of that signal completely. 
   SUMMARY OF THE INVENTION 
   According to a first aspect of the invention there is provided a transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gate of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor. 
   It is thus possible to provide a transconductance circuit which behaves as if it is a field effect transistor but where the transconductance exhibits increased linearity over a selected signal range. By biasing the first transistor into the “saturation region” of its characteristic the effective transconductance of the first transistor increases with increasing signal voltage, whereas by biasing the second transistor into the “linear region” and causing its drain-source voltage to vary so as to decrease with respect to increases in the input voltage V in  increases, then the effective transconductance of the second transistor decreases with increasing signal voltage. The transistors are in parallel and consequently the transconductance circuit can exhibit an improvement in the linearity of its transconductance over an operating window where the changes in transconductance of the first and second transistors can be arranged to substantially cancel one another. 
   Preferably the voltage modulator comprises a third field effect transistor in series with the second field effect transistor 
   Advantageously the gates of the second and third transistors are biased at the same bias potential. The gates of the second and third transistors do not need to be biased at exactly the same potential but this is a convenient choice. The third transistor acts to drop the voltage across its gate and source terminals such that the drain-source voltage across the second transistor is sufficiently low for it to be biased into its “linear region”. It also causes the drain-source voltage of the second transistor to be modified as a function of the gate-source voltage. This is because the gate voltage of the third transistor is held constant. Therefore, as the current flow through the transistor increases, the gate-source voltage must also increase in accordance with the transistors transfer characteristic. Hence the drain voltage of the second transistor decreases. 
   However, the voltage modulator could be another component, such as a resistor. It is advantageous to make the drain source voltage of the second transistor independent of changes in the voltage at the second node of the circuit, hence a further transistor is generally preferred. However, in some uses of the transconductance circuit, the voltage at the second node may be nominally constant (for example because the transconductance circuit drives a “load” including a cascode transistor), in which case a resistor can suffice as the voltage modulator. 
   According to a second aspect of the present invention there is provided a method of compensating for non-linearities of a first field effect transistor, where the first transistor is operated as an amplifier and is, in use, biased into its saturation region of its transfer characteristic, the method comprising the steps of providing a second field effect transistor in parallel with the first transistor, the second transistor being biased into its “linear region” and in series with a device for varying the drain-source voltage of the second transistor as a function of the gate source voltage such that changes in its transconductance with respect to input voltage partially or wholly cancel changes in transconductance of the first transistor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the present invention described, by way of example only, with reference to the accompanying drawings, in which: 
       FIG. 1  schematically illustrates a simple amplifier; 
       FIGS. 2   a  to  2   d  illustrate I DS  versus V GS  and the first, second and third derivatives thereof, respectively; 
       FIG. 3  schematically illustrates generation of inter-modulation products within a receiver due to non-linearities within an amplifier; 
       FIG. 4  is a circuit diagram of a circuit constituting an embodiment of the present invention; 
       FIG. 5  is a diagram showing an ideal transfer characteristic of a field effect transistor; 
       FIG. 6  schematically illustrates how non-linearity compensation can be achieved; 
       FIG. 7  shows a further bias arrangement adapted to give improved dynamic range; 
       FIG. 8  shows an amplifier circuit into which the arrangement of  FIG. 4  was inserted in place of the transistor; 
       FIG. 9  shows a bias voltage generator including a calculator for assessing an optimum bias point; 
       FIGS. 10   a  and  10   b  show variations to the circuit of  FIG. 4 ; and 
       FIGS. 11   a  and  11   b  show further variations to the circuit shown in  FIG. 4 . 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 4  schematically illustrates a transconductance circuit constituting an embodiment of the present invention. The circuit comprises four transistors, labelled M 1  to M 4 , although the fourth transistor forms a cascode stage and can be omitted and hence the drain of M 1  can be directly connected to the terminal  14 . 
   The transconductance circuit takes the place of a field effect transistor gain stage and has first, second and third terminals  12 ,  14  and  10  which correspond to the source, drain and gate of an equivalent transistor, and where the source and drain terminals correspond to first and second nodes of the transconductance circuit. The first transistor M 1  has its gate connected to the gate terminal  10  via a first DC blocking capacitor  20 . A source of the transistor M 1  is connected to the source terminal (first node)  12  of the transconductance circuit  8 . A drain of the transistor M 1  is in current flow communication with the drain terminal (second node)  14  of the transconductance circuit  8 , in this example, via intermediate transistor M 4 . If the fourth transistor M 4  was omitted, then the drain of the first transistor M 1  would be directly connected to the drain terminal  14  but, in the arrangement shown in  FIG. 4  the drain of the transistor M 1  is connected to the source of the fourth transistor M 4  and the drain of the fourth transistor M 4  is connected to the drain at terminal  14  of the transconductance circuit. 
   A gate of the first transistor M 1  is connected to a first bias node V b1  via a resistor  22 . 
   The second transistor M 2  also has its source terminal connected to the source terminal  12  of the transconductance circuit and its gate is connected to the gate terminal  10  via a second DC blocking capacitor  24 . The gate terminal is connected to a second bias node V b2  via a resistor  26 . A drain of the second transistor M 2  is connected to a voltage modulator, and more specifically to the source of a third transistor M 3 , whose drain is connected to the drain at terminal  14  and whose gate is also connected to the second bias node V b2  via a resistor  28 . Finally, a gate of the fourth transistor is connected to a third bias node V b3  via a resistor  30 . The resistors  28  and  30  are only needed if the transconductance circuit is to be degenerated, that is if there is an impedance connected between the source node  12  and ground. If this occurs, then resistors  28  and  30  have a non zero value and similarly AC coupling capacitors  32  and  34  are also provided such that the voltage between the gate of transistor M 3  and node  12  and between the gate of transistor M 4  and node  12  remains constant in the presence of an AC signal. 
   In use, transistor M 1  functions as the main amplification device and is biased into the saturation region of its transfer characteristic whereas transistor M 2  is biased into its linear region. By the term “saturation region” it is meant that for a given gate-source voltage greater than the threshold voltage V T  of the transistor then the drain current I D  is substantially constant with respect to changes in the drain-source voltage. Therefore the current passing through the transistor is responsive to a first order approximation, only to changes in the gate-source voltage. This is the normal regime while operating a FET transistor as an amplifier, and is illustrated in the transfer characteristics shown in  FIG. 5 . 
   For a given bias voltage V b1  changes to the transconductance of the first transistor M 1  resulting from an input signal supplied at the gate terminal are shown in  FIG. 6  by the chain line  40 . It can be seen that the first transistor M 1  is biased into a region such that its transconductance increases with increasing gate-source voltage. 
   By way of contrast, the transistor M 2  is biased into its “linear region”. This is the region designated in  FIG. 5  where for a given gate-source voltage the drain-source current is substantially proportional to the drain-source voltage. In this region the field effect transistor is effectively functioning as a voltage controlled resistor. Therefore the transconductance of transistor can also be represented as being like a voltage controlled current source, so for M 2  in its linear region
 
 g   m   L   =K·V   DS 
 
where
         K is a constant       

   If appropriate circuitry is added, i.e. transistor M 3 , so as to vary the drain-source voltage of M 2  as a function of V gs  such that
 
 V   DS   =V   0   +αV   gs 
 
where α is a coefficient
 
then the effective transconductance of M 2  is
 
           =         ⅆ     ⅆ     V   gs         ⁢     β   ⁡     [         (       V   gs     -     V   th       )     ⁢     (       V   0     +     α   ⁢           ⁢     V   gs         )       -       (         V   0     +     α   ⁢           ⁢     V   gs         2     )     2       ]         ⁢     
     =     β   ⁡     [         V   0     ⁡     (     1   -   α     )       -       V   th     ⁢   α     +         V   gs     ·   2     ⁢           ⁢     α   ⁡     (     1   -     α   2       )           ]               
which is a linear fumction of V gs .
 
   It should be noted that the co-efficient α can be selected such that the gradient of this linear function can be made negative. This is not achievable with a transistor in saturation. 
   The transconductance of the combination of the second and third transistor, dV GS /dI DS  is designated by the solid line  42  in  FIG. 6 . 
   It can be seen with suitable biasing of the first and second transistors M 1  and M 2  that the changes in transconductance in response to an AC signal centred, by definition, about zero volts can result in the changes in transconductance effectively cancelling each other out such that a composite transconductance designated by the chain line  44  of  FIG. 6  is obtained which is generally independent of the input signal swung over a limited voltage range. 
   It can be seen that, in this example, improved linearity is obtained for signal amplitudes smaller than 100 mV. Analysis of the curve shows that the second and third order derivatives of I D  as a function of V GS  are simultaneously considerably smaller than that which is achievable with a single transistor. Thus, the arrangement shown in  FIG. 4  behaves like a single transistor with improved linearity characteristics. 
   Linearity can be traded for dynamic range, as shown in  FIG. 7  where the composite linearity, as indicated by chain line  50  is not as flat as the corresponding curve  44  in  FIG. 6 , but where the effective signal range for which the transconductance is relatively linear (the relative change in transconductance is less than 10% in this example) now extends to ±350 mV or so. In order to evaluate performance, a simplified well known low noise amplifier circuit, as shown in  FIG. 8 , was used and its transistor was replaced by the circuit shown in  FIG. 4 . The arrangement shown in  FIG. 4  was biased so as to obtain the response curve shown in  FIG. 6 . The circuit performance was simulated with transistors M 2  and M 3  having dimensions of 78 μm by 0.18 μm and transistors M 1  and M 4  having dimensions of 85.8 μm by 0.18 μm. The gate source bias voltage was 784 mV for M 1  and 800 mV for M 2 . The current used by the circuit was 8.5 mA and the improvement in the IP 3  intercept point compared with an equivalent low noise amplifier similar gain, noise and input/output impedance is around 10 dB. Effectively the same amplifier configuration was used to investigate the large signal performance where the transistors were sized and biased so as to obtain the response shown in  FIG. 7 . In this arrangement transistors M 2  and M 3  had dimensions of 78 μm by 0.4 μm, whereas transistor M 1  was 46.8 μm by 0.36 μm and transistor M 4  was 93.6 μm by 0.18 μm. The gate source bias voltage was 978 mV for transistor M 2  and 1.127 volts for transistor M 1 . The amplifier consumed a current of 7.2 mA and exhibited in 1 dB compression point at an input power of 5 dBm. 
   Considering the small signal amplifier, it can be noted that if V b1  is too low, then the curve representing the transconductance of M 1  in  FIG. 6  shifts along the X axis in the positive direction and the slope of the transconductance at the zero volt signal input value becomes positive. If V b1  is too high, then the curve representing the transconductance of the transistor M 1  shifts in a negative direction and the slope of the composite transconductance at the zero input value becomes negative. The flatness of the transconductance curve as a function of the input voltage can therefore be changed by appropriately choosing the bias potential V b1 . The circuit shown in  FIG. 9  measures the slope of the transconductance of the transconducting circuit shown in  FIG. 4  and finds the bias potential V b1  which brings the slope of the transconductance close to zero for zero AC input signal. 
   In the arrangement shown in  FIG. 9  it can be seen that the arrangement shown in  FIG. 4  is effectively reproduced three times. Therefore, transistors M 1 , M 2 , M 3  and M 4  are effectively configured in an identical arrangement compared to that shown in  FIG. 4 . Considering transistor M 1  in greater detail, it can be seen that it is provided with a bias voltage V b1  derived at the output of the operational amplifier  60 . The voltage from the amplifier  60  is also provided to the gate of transistor M 1 +(situated to the right of transistor M 1  in  FIG. 9 ) and to transistor M 1  (situated to the left of transistor M 1  in  FIG. 9 ). The current source  62  and sink  64  are provided such that the transistor M 1 + has a gate voltage slightly in excess of that occurring at transistor M 1  whereas transistor M 1 − has a gate voltage slightly less than that occurring at transistor M 1 . A similar circuit is associated with transistor M 2 . The transistors in the circuit shown in  FIG. 9  may be scaled replicas of the transistors of the transconductance circuit such that the current drawn by the circuit can be reduced but the current density within the transistors is the same as the transconductance circuit. 
   It is known that the gradient of the transconductance can be formed, at a given bias voltage, by calculating the current passing through the circuit at the bias voltage, at a first test voltage which is slightly more than the bias voltage, and at a second test voltage which is slightly less than the bias voltage, and then forming the sum 
               Y   +     -     2   ⁢     Y   0       +     Y   2         Δ   ⁢           ⁢     X   2             
where Y +  represents the current flowing at the bias voltage plus the increment ΔX, Y 0  represents the current flowing at the bias voltage X and Y −  represents the current flowing at the bias voltage −ΔX, and ΔX represents the size of the perturbation used in the test. In fact, the circuit only needs to evaluate the numerator of this expression. The circuit shown in  FIG. 9  performs this calculation in the analog domain by comparing the current flowing through the unperturbed circuit with the sum of the current flowing through the “+” and “−” circuits where the “+” and the “−” designates those circuits which have the perturbing voltage added or subtracted from the bias voltage. The individual currents are supplied to an active load  70  which forces current flowing through transistor  72  to match that flowing through transistor  74  subject to a scaling factor of 2. Therefore any current difference which needs to flow along the conductor  76  towards the unperturbed circuit is derived by either charging or discharging the capacitor  78 , as appropriate. The voltage occurring across the capacitor is used as the reference voltage in the operational amplifier  60 , thereby forming a feedback loop. Thus the circuit shown in  FIG. 9  seeks to adjust the bias voltage V b1  in order to linearise the transconductance of the circuit shown in  FIG. 4 , i.e. to set
 
               ⅆ   2     ⁢     I   DS         ⅆ     V   GS   2             
to zero, or as close to zero as it can manage.
 
     FIG. 10   a  shows a circuit diagram equivalent to that of  FIG. 4 , but with transistor M4 omitted. This means that capacitor  34 , resistor  30  and bias node V B3  can also be omitted. 
   The bias circuit around transistors M 2  and M 3  can also be modified such that, M 2  can be directly connected to a bias node  100  via resistor R B1  such that the signal V in  can be superimposed upon the bias voltage whereas transistor M 3  can be directly connected to bias node  102 . In this way, the transistors can be set to individual bias voltages. 
   It was noted earlier that the voltage modulator could be formed by a resistor.  FIG. 11   a  shows a further embodiment of the present invention where the cascode transistor M 4  has been omitted and the modulating transistor M 3  has been replaced by resistor R 3 . This circuit can work provided that the drain source voltage of transistor M 2  is independent of the voltage at the second node, that is the effective drain terminal  14  of the transconductance circuit. This can be achieved where, for example, the transconductance circuit is used to drive a cascode transistor and consequently in the overall amplifier configuration the voltage at node  14  is substantially invariant. However, where this cannot be achieved then the cascode transistor M 4  of  FIG. 4  can be shared by transistors M 1  and M 2 , as shown in  FIG. 11   b . In this arrangement the voltage occurring at the source terminal of transistor M 4  is substantially invariant of the voltage occurring at the node  14  of the transconductance circuit and therefore resistor R 3  can be used to modulate the drain source voltage across transistor M 2  so as to reduce the drain source voltage as the current through transistor M 2  increases. 
   It is thus possible to provide a transconductance circuit which functions as a transistor having improved linearity and a circuit for optimally biasing the transconductance circuit.