Abstract:
A power-amplifier cell which comprises an inverting input amplifier made up of a first transistor (T 1 ) having a collector connected to a first supply-voltage terminal via a first resistor (R 11 ), and an output stage comprising a second (T 4 ) and a third (T 6 ) transistor whose collector-emitter paths are arranged in series. The common point between the second and third transistors forms an output (5) of the power amplifier. The second transistor (T 4 ) has its base connected to the collector of the first transistor (T 1 ) and a control signal is applied to the base of the third transistor (T 6 ) via a second resistor (R 16 ). Furthermore, a first capacitor (C 1 ) is arranged in parallel with the first resistor (R 11 ) and the control signal is the input signal (E) or a fraction thereof. The power amplifier may comprise two cells whose first transistors (T 1 ) have their emitters coupled to one another.

Description:
BACKGROUND OF THE DISCLOSURE 
     This invention relates to a power-amplifier cell which comprises an inverting input amplifier comprising a first transistor having a collector connected to a first supply-voltage terminal via a first resistor, and an output stage comprising a second and a third transistor whose collector-emitter paths are arranged in series, their common point forming an output of the power amplifier, the second transistor having its base connected to the collector of the first transistor, and means for applying to the base of the third transistor a control signal in phase with an input signal applied to the base of the first transistor. 
     Such an amplifier is known from U.S. Pat. No. 3,564,281 (FIG. 7b), which relates to a fast logic inverter, and from the article &#34;A Wide-Band Class AB Monolithic Power Amplifier&#34; by William D. Mack in the IEEE Journal of Solid State Circuits, Vol. 24, no. 1, Feb. 1989. 
     U.S. Pat. No. 3,564,281 describes a logic circuit which is used for switching but not as an amplifier. The amplifier described in the above article has been designed for use with sinusoidal signals and with a substantially resistive load. 
     SUMMARY OF THE INVENTION 
     It is an objective of the invention to provide a power amplifier capable of operating with rectangular input signals (for example, clock signals) and with a capacitive impedance. These two requirements, which are only met separately in the two above-mentioned documents, are particularly critical because they involve the rapid switching of comparatively large currents. 
     The basic idea of the invention is to realize the desired function while maintaining a minimal signal path. To achieve this, switching is accelerated in the inverting input amplifier so as to optimize the rise time in the branch comprising the inverting input amplifier in series with the second transistor, and the third transistor is driven directly by the input signal, in switching time being adapted to correspond to that of said branch. 
     A power-amplifier cell in accordance with the invention is characterized in that it comprises a first capacitor arranged in parallel with the first resistor, in that the control signal is the input signal multiplied by a coefficient smaller than or equal to 1, and in that said means for applying a control signal comprise a second resistor arranged in series with the base of the third transistor. 
     The second transistor and a first voltage source coupled to the first supply-voltage terminal enable the capacitive impedance to be charged and discharged respectively. Surprisingly, the first capacitor enables the switching speed of the first transistor to be raised and the second resistor enables the switching time of the third transistor to be adapted so as to synchronize switching of the second and the third transistor. 
     The cell may comprise a voltage divider adapted to receive a signal from an input source and to generate the input signal and the control signal. Thus, the amplitudes of the signals on the bases of the first and the third transistor can be adapted, in particular so as to avoid hard switching of these transistors, yielding an improved response time. 
     The cell may comprise a parallel resistor-capacitor network arranged in the emitter of the third transistor and having a time constant preferably equal to the product of the value of the first resistor and that of the first capacitor. 
     The invention also relates to a differential power amplifier comprising two power-amplifier cells as defined above, the first transistors of both cells being coupled to one another by their emitters. 
     In an advantageous embodiment the third transistors have a third resistor connected between their emitters. This has the advantage that the linear range of the differential stage comprising the third transistors can be adjusted. A first and a second current source may be connected to the respective emitters of the third transistors of both cells. 
     In a modification a fourth and a fifth resistor are connected in series between the emitters of the third transistors, and a third current source (serving as said first and second current sources) is connected to the node between the fourth and the fifth resistor. 
     A third capacitor may be connected between the emitters of the third transistors. 
     This capacitor is seen as an inductance in the collectors of the third transistors, which explain the increased pass band. 
     In a preferred embodiment a sixth and a seventh resistor can be respectively arranged in series with the collector-emitter path of the second and the third transistor of each cell. They can provide a decoupling between the collectors of the third transistors and the capacitive load of the outputs so as to preclude ripple on the transients. 
     An eighth resistor may be connected between the bases of the first transistors of both cells. 
     In the case where the voltage level is to be shifted, a diode-connected transistor poled in the forward direction is arranged between a node of the first resistors of the two cells and the first apply voltage terminal, and a fourth capacitor may then be arranged between said node and a second supply terminal source. The fourth capacitor creates a virtual ground point and provides common-mode rejection, while compensating for the self-induction effect caused by the diodes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be more fully understood by reading the following description, given by way of non-limitative example, with reference to the accompanying drawings, in which: 
     FIGS. 1a and 1b shows a class AB amplifier in accordance with the cited prior art, 
     FIG. 2 shows a power-amplifier cell in accordance with the invention, 
     FIG. 3 shows a power amplifier in accordance with the invention, 
     FIG. 4 shows a power amplifier in accordance with a preferred embodiment of the invention, and FIG. 5 shows a modification of the differential switching stage at the output, 
     FIGS. 6a and 6b show the switching on the emitter of T 4  via T 1  with and without the capacitor C 1  respectively, and 
     FIGS. 7a and 7b show the switching signals on the emitter of T 4  (cross-over) with and without the capacitor C&#39; 6  respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1a shows a prior-art amplifier which is a modification of the &#34;totem pole&#34; circuit as described in, for example, the publication by P. R. Gray and R. G. Meyer, &#34;Analysis and Design of Analog Intergrated Circuits&#34;, 2nd edition, John Wiley, New York, 1984. A transistor Q 1  having its base connected to the output of an inverter A 1 , whose input receives an input signal E, drives an output S via an output resistor R 1 . For output signals S of positive amplitude a transistor Q 2  having its base connected to the output of a non-inverting amplifier A 2 , whose input receives the input signal E 1 , is cut off completely. For negative signals at the output the transistor Q 2  is turned on to allow the passage of current without the transistor Q 1  being cut off, which enables the transfer function to be maintained (Q 1  operates at a lower current level). 
     FIG. 1b shows a modification of the amplifier shown in FIG. 1a. The amplifier A 1  comprises a transistor Q 3  having its base coupled to an input resistor R 3  and having its collector connected to the base of the transistor Q 1 . A feedback resistor R 4  is arranged between the emitter of the transistor Q 1  and the base of the transistor Q 3 . 
     A diode D 5 , poled in the forward direction in the emitter of the transistor Q 3 , shifts the bias of this transistor by one base-emitter voltage V be  and enables the emitter follower (transistor Q 4 ) forming the amplifier A 2  to operate at negative voltages S. A bias current source I B  connected to the base of Q 3  determines the bias voltage on the emitter of Q 1 . 
     The module shown in FIG. 2 is also of the &#34;totem pole&#34; type but the operating conditions are different. 
     It has the following similarities with the prior-art circuit of U.S. Pat. No. 3,564,281 (FIG. 7b). A transistor T 1  is loaded by a resistor R 11  at its collector. Two transistors T 4  and T 6  have their collector-emitter paths arranged in series like the transistors Q 1  and Q 2 , the transistor T 4  having a resistor R 14  in its collector circuit. Moreover, there is a connection between the base of the transistor T 1  and the base of the transistor T 6 . 
     The circuit shown in FIG. 2 differs from that in FIG. 7b of the prior-art document U.S. Pat. No. 3,564,281 in the following points: 
     for faster switching, which is favourable for the desired operation with rectangular signals, a capacitor C 1  is arranged in parallel with the resistor R 11 , which in a surprising manner improves the transient response (dynamic compensation effect). 
     to ensure that the transistor T 4 , whose base is connected to the collector of the transistor T 1  and whose collector-emitter path is arranged in series with that of the transistor T 6 , is switched in synchronism with the transistor T 6  a resistor R 16  is arranged in series in the base of T 6 . The resistor R 16  (whose value is determined by experiment on the basis of the signal waveforms) delays the change-over of the transistor T 6  in such a way that this transistor is switched substantially in synchronism with the switching of the transistor T 1  (accelerated by C 1 ) and of the transistor T 4 . This results in a minimum number of circuit elements and a signal path which is as short as possible, which is favourable for switching rectangular signals such as clock signals, in particular in the case of a substantially capacitive load C. 
     It is very favourable if the signals E on the base of the transistor T 1  have such a low level that the transistors T 1  and T 6  are not cut off, and such a high level that the transistors T 1  and T 6  are not bottomed. This would result in optimum conditions for fast switching. 
     When the input signal E has its low level T 1  is cut off (preferably not completely), the transistor T 4  is on and the transistor T 6  is off (or preferably operates with a small current). The capacitor C is charged via the collector-emitter path of the transistor T 4 . A resistor R 14  may be arranged in the collector of T 4 . When the input signal E has its high level T 4  is cut off (preferably not completely) and the transistor T 6  is turned on. The capacitor C discharges via the collector-emitter path of the transistor T 6 . A resistor R&#39; 6  may be arranged between the emitter of the transistor T 6  and the common-mode terminal. A capacitor C&#39; 6  whose function will be explained hereinafter, may be arranged in parallel with the resistor R&#39; 6 . 
     FIG. 3 shows a differential amplifier in accordance with the invention comprising two cells as shown in FIG. 2 The elements T 1 , T 4 , T 6 , R 11 , R 14 , R 16 , R&#39; 6  C 1  and C&#39; 6  of the first cell bear the references T 2 , T 3  T 5 , R 12 , R 13 , R 15 , R&#39; 5 , C 2  and C&#39; 5  in the second cell. The transistors T 1  and T 2  have their emitters coupled to form a differential stage, and a current source I 12  is connected to these coupled emitters. The base of T 1  receives a clock signal h and the base of T 2  receives its logic inverse h. The output H, which is in phase with h except for the response time, is formed by the emitter of the transistor T 3 . The output H, which is in phase with h except for the response time, is formed by the emitter of the transistor T 4 . The outputs H and H are adapted to be loaded by substantially capacitive impedances C and C&#39; respectively. 
     In FIG. 4 elements corresponding to those in FIG. 3 bear the same references. The current source I 12  is formed by a transistor T 11  and an emitter resistor R 21 , and the base of T 11  receives a reference voltage V REF . Current sources connected to the emitters of T 5  and T 6  respectively are formed by the transistors T 12  and T 13 , which have emitter resistors R 22  and R 23  respectively and whose bases receive a reference voltage V REF . By means of the dimensions of the transistors T 11 , T 12  and T 13  and the resistors R 21 , R 22  and R 23  the various values of the currents in the collectors of these transistors can be determined. 
     The circuit shown in FIG. 4 has certain improvements in comparison with that shown in FIG. 3 and can be combined or used separately. 
     First of all the clock signals h and h are applied to the inputs of two voltage dividers comprising the emitter-follower transistors T 7  and T 8  respectively (with base resistors R 17  and R 18 , respectively). The emitter of T 7  is connected to a first voltage-divider branch comprising a series arrangement of two resistors R 31  and R 33  and a current source (T 10 , R 20 , V REF ). The emitter of T 8  is connected to a second voltage-divider branch comprising two resistors R 30  and R 32  and a current source (T 9 , R 19 , V REF ). The node between the resistors R 31  and R 33  is connected to the base of transistor T 1 . The node between the two resistors R 30  and R 32  is connected to the base of T 2 . The node between the resistor R 33  and the current source (T 10 , R 20 , V REF ), i.e, the collector of T 10 , drives the base of T 6  via the resistor R 16 . The node between the resistor R 32  and the current source (T 9 , R 19 , V REF ), i.e. the collector of T 9 , drives the base of T 5  via the resistor R 15 . 
     The two said nodes, connected to the bases of the transistors T 1  and T 2  respectively, are interconnected by a resistor R 34 . If R 30  and R 31  have the same value this yields the following relationship (if the base voltages of the transistors T 1  and T 2  are designated h&#39; and h&#39; respectively); ##EQU1## 
     The resistors R 32  and R 33  serve to reduce the voltage, if necessary; in order to drive the base of T 5  and T 6  without these transistors being saturated. Allowance is to be made for the values of these resistors in series with R 15  and R 16  respectively in the calculation of the switching delay of T 5  and T 6  provided by the last-mentioned resistors. 
     By way of an alternative, a resistive divider bridge may be used for each of the cells. 
     By means of a capacitor C 5  arranged between the collectors of the transistors T 1  and T 2  current surges on the collectors of these transistors can be avoided. The value of this capacitor should be as a small as possible, allowance being made for a satisfactory attenuation of current surges (for example, 5 pF). 
     The resistors R 11  and R 12  may be connected to the supply-voltage source V cc , a voltage shift being provided by a diode-connected transistor T 35 . FIG. 4 shows two resistors R&#39; 11  and R&#39; 12  having one terminal interconnected and arranged in series with a resistor R 35  and the diode-connected transistor T 35 . A capacitor C 8  is arranged between the node of the resistors R&#39; 11  and R&#39; 12  and ground (or a second supply-voltage source) creates a virtual ground for the purpose of common-mode rejection C 8  may be also be small (for example, 20 pF), but is preferably large enough to compensate for the self-induction effect of T 35 . For example, it is possible to select R 35  C 8  ≃10 t f  (t f  =rise time of the stage T 1 , T 2 ), which provides a correction for harmonics. 
     A resistor R 56  arranged between the emitters of T 5  and T 6  serves to ensure that the transistors T 5  and T 6  operate as a differential stage whose linear range can be selected by adjusting the value of R 65 . 
     Thus, switching can be adjusted in such a way (dynamic linearization) that alternately a maximum or a minimum current flows in the transistors T 5  and T 6 , depending on the instantaneous sign of the clock voltage. For linear operation it is necessary that: 
     
         R.sub.56 I&gt;ΔV+V.sub.T 
    
     I : current of the current sources comprising the transistors T 12  and T 13   
     ΔV : maximum amplitude of the signals on the bases of the transistors T 5  and T 6   
     V T  =26 mV. 
     R 56  I can be adjusted to have a ratio K between the maximum and minimum currents of the order of 10. 
     A capacitor C 6  in parallel with the resistor R 56  enables the switching speed to be increased. The capacitor C 6  is seen as a self-inductance from the collectors of the transistors T 5  and T 6 . 
     Finally, resistors R 53  and R 64  connected between the emitter of T 3  and the collector of T 5  and between the emitter of T 4  and the collector of T 6 , respectively, enable the collectors of T 5  and T 6  to be decoupled from the capacitive loads C and C&#39; to avoid ripple on the high and low levels of the output signals. Their values should also be as small as possible to achieve the desired effect. 
     FIG. 5 shows a modification of the differential stage comprising the transistors T 5  and T 6 . Their emitters are interconnected by two resistors R&#39; 56  and R&#34; 56  in series. The node between these two resistors is connected to a current source (T 14 , R 24 , V REF ). 
     FIGS. 6a and 6b illustrate the influence of the capacitor C 1  on the switching process of the transistor T 1 . In the absence of the capacitor C 1  (FIG. 6a) the response is wholly stabilized at the instant t 1  (corresponding to a response time τ 1 ). Owing to the capacitor C 1  (FIG. 6b) the response is more rapid and stabilizes sooner at the instant t 2  (response time τ 2  &lt;τ 1 ). This yields a gain in time t 3  to obtain a fully stabilized response. The value of the capacitor C 1  is adjusted by experiment so as to obtain the shortest response time τ 2 . A response time τ 2  of a few ns (for example, approximately 2 ns) has been obtained with a transistor of a given type by choosing R 11  32 200 Ω and C 1  =2 pF, i.e. R 11  C 1  32 0.4 ns. In the present case this corresponds to a time constant smaller than the response time, which value can be optimized in practice. 
     FIGS. 7a and 7b illustrate the effect of the capacitor c&#39; 6  in parallel with the resistor R&#39; 6 . The object is to obtain the same impedance in the collector of the transistor T 6  and to achieve a symmetrical operation of the cell shown in FIG. 2 on the rising and falling edges, i.e. a cross-over in the centre of the voltage excursion. 
     This optimum operation is generally achieved when R 11  C 1  =R&#39; 6  C&#39; 6  (FIG. 7b), FIG. 7a showing the incorrect cross-over (and hence a faulty symmetry) in the absence of compensation. 
     Below, more precise guidelines will be given to allow the most favourable values to be calculated for at least some of the parts. 
     From the emitter of T 4  the parallel network R 11  C 1  is seen as a self-inductance L&#39; in series with a resistance R&#39;. ##EQU2## where τ=R 11  C 1 , 
     τ n  =transit time in the base of a transistor, 
     t f  : rise time of the signal on the base of T 4 . 
     The parallel network R&#39; 6  C&#39; 6  from the collector of T 6  is seen as a self-inductance L&#34; in series with a resistance R&#39;. 
     
         &#34;=R.sub.c R&#39;.sub.6 C&#39;.sub.6 
    
     
         R&#34;=R.sub.c 
    
     where: R c  is the intrinsic collector resistance of T 6  (if applicable, in series with R 64 ). 
     The transistors T 4  and T 6  are in the same switching state if L&#39;=L&#34; and R&#39;=R&#34;. 
     If the choice ##EQU3## is made this yields the approximation: 
     
         R.sub.c R&#39;.sub.6 C&#39;.sub.6 =τ.sub.n R.sub.11 
    
     
         C.sub.c C.sub.1 =τ.sub.n 
    
     so that: ##EQU4## 
     For FIG. 4 this yields: ##EQU5## In practice the rise time of the transistor T 1  may be chosen for t f . 
     Example: 
     
         R.sub.11 32 200Ω, C.sub.1 =2 pF 
    
     
         R.sub.56 =600Ω, C.sub.6 32 0.75 pF. 
    
     Moreover, it is necessary that R 11  I 12  &gt;ΔV, 
     To obtain a rapid discharge of C, the following choice is to be made: ##EQU6## 
     t=the desired discharge time for the capacitor C.