Abstract:
A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a memory technique field, and more particularly to a memory cell array. 
     BACKGROUND OF THE INVENTION 
     Basically, a general memory device is constituted by a memory cell array and an operation voltage supply circuit. In the memory cell array, all the memory cells in the same row are electrically coupled to a respective write word line; and all the memory cells in the same column are electrically coupled to a respective bit line. The operation voltage supply circuit is configured to provide an operation voltage to all the memory cells in the same column in the memory cell array. 
     However, in the memory cell array, because all the memory cells in the same column are electrically coupled to one another, the bit line in the same column may have an increasing load while the memory cells in the same column are supplied with the operation voltage. Thus, an IR-Drop may occur, and consequently the memory cells may have a poor static noise margin (SNM) in the data writing period. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a memory cell array having higher memory cell static noise margin (SNM). 
     The present invention provides a memory cell array, which includes a write bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, is configured to provide a first operation voltage. The second operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, is configured to provide a second operation voltage. The first memory cell, electrically coupled to the bit line and the complementary bit line, is configured to receive the first operation voltage. The second memory cell, electrically coupled to the bit line and the complementary bit line, is configured to receive the second operation voltage. Wherein, the first and second memory cells are located in a same column in the memory cell array. 
     In summary, by dividing the memory cells in the same column of a memory cell array into at least two groups of memory cells, configuring one of the two groups of memory cells to receive an operation voltage provided by one of the at least two groups of operation voltage supply circuits in the memory cell array, and configuring the other one of the two groups of memory cells to receive an operation voltage provided by the other one of the at least two groups of operation voltage supply circuits in the memory cell array, the memory cell array of the present invention employing the aforementioned structure not only can reduce the impact of the IR-Drop on the memory cells but also enhance the static noise margin (SNM) of the memory cells. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is an illustrative view of a memory cell array in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic diagram of an operation voltage supply circuit and a respective memory cell in accordance with an embodiment of the present invention; 
         FIG. 3  is a schematic diagram of an operation voltage supply circuit and a respective memory cell in accordance with another embodiment of the present invention; 
         FIG. 4  is a schematic diagram of an operation voltage supply circuit and a respective memory cell in accordance with yet another embodiment of the present invention; 
         FIG. 5  is a schematic view of an operation voltage supply circuit and a respective memory cell in accordance with still yet another embodiment of the present invention; 
         FIG. 6  is a schematic view of an operation voltage supply circuit and a respective memory cell in accordance with another further embodiment of the present invention; and 
         FIG. 7  is a schematic view of an operation voltage supply circuit and a respective memory cell in accordance with another yet further embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
       FIG. 1  is an illustrative view of a memory cell array in accordance with an embodiment of the present invention. As shown, a memory cell array  100  in this embodiment includes at least one bit line BL, at least one complementary bit line BLB, at least two groups of operation voltage supply circuits, at least two groups of memory cells and at least one write word line. In the memory cell array  100 , one group of a plurality of operation voltage supply circuits  101  and one group of memory cells  103  both are electrically coupled to the bit line BL and the complementary bit line BLB; wherein each one of the memory cells  103  is configured to receive an operation voltage V 1  supplied from one respective operation voltage supply circuit  101 . Another group of a plurality of operation voltage supply circuits  105  and another group of a plurality of memory cells  107  both are electrically coupled to the bit line BL and the complementary bit line BLB; wherein each one of the memory cells  107  is configured to receive an operation voltage V 2  supplied from one respective operation voltage supply circuit  105 . The memory cells  103 ,  107  both are electrically coupled to the write word lines. In this embodiment, the specific memory cells  103  and the respective memory cells  107  are located in the same column in the memory cell array  100 . Moreover, in this embodiment, the one group of the operation voltage supply circuits  101  is disposed in an array interstice  111  in the memory cell array  100 ; and the another group of the operation voltage supply circuits  105  is disposed in an array interstice  113  in the memory cell array  100 . 
     The operation of the memory cell array  100  will be exemplarily described by using one operation voltage supply circuit  101  and one respective memory cell  103  only. Because the operation voltage supply circuit  105  and the respective memory cell  107  corporately have the similar operation, no redundant detail is to be given herein. 
       FIG. 2  is a schematic diagram of an operation voltage supply circuit  201  and a memory cell  203  in accordance with an embodiment of the present invention; wherein the operation voltage supply circuit  201  and the memory cell  203  herein are equivalent to the operation voltage supply circuit  101  and the memory cell  103  in  FIG. 1 , respectively. As shown in  FIG. 2 , the operation voltage supply circuit  201  mainly includes two N-type transistors N 1 , N 2 , two P-type transistors P 1 , P 2 , and two inverters INV 1 , INV 2 . The N-type transistors N 1 , N 2  each is configured to have one source/drain thereof electrically coupled to a source voltage VDD and another source/drain thereof electrically coupled to a node for generating an operation voltage Vcell. The P-type transistor P 1  is configured to have one source/drain thereof electrically coupled to the node and a gate thereof electrically coupled to a gate of the N-type transistor N 2 . The P-type transistor P 2  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 1 , another source/drain thereof electrically coupled to the source voltage VDD, and a gate thereof electrically coupled to a gate of the N-type transistor N 1 . The inverter INV 1  is configured to have an input terminal thereof electrically coupled to the bit line BL and an output terminal thereof electrically coupled to a gate of the P-type transistor P 2 . The inverter INV 2  is configured to have an input terminal thereof electrically coupled to a complementary bit line BLB and an output terminal thereof electrically coupled to a gate of the P-type transistor P 1 . In this embodiment, the N-type transistors N 1 , N 2  each may be implemented by a general-threshold-voltage transistor, a high-threshold-voltage transistor or a low-threshold-voltage transistor. 
     The memory cell  203  mainly includes two P-type transistors P 3 , P 4  and four N-type transistors N 3 , N 4 , N 5  and N 6 . The P-type transistors P 3 , P 4  each are configured to have one source/drain thereof electrically coupled to the node in the operation voltage supply circuit  201  and from which to receive the operation voltage Vcell. The N-type transistor N 3  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 3 , another source/drain thereof electrically coupled to a source voltage VSS, and a gate thereof electrically coupled to a gate of the P-type transistor P 3 . The N-type transistor N 4  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 4 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to a gate of the P-type transistor P 4 . The N-type transistor N 5  is configured to have one source/drain thereof electrically coupled to the bit line BL, another source/drain thereof electrically coupled to one source/drain of the N-type transistor N 3  and a gate of the N-type transistor N 4 , and a gate thereof electrically coupled to the write word line WWL. The N-type transistor N 6  is configured to have one source/drain thereof electrically coupled to the complementary bit line BLB, another source/drain thereof electrically coupled to one source/drain of the N-type transistor N 4  and a gate of the N-type transistor N 3 , and a gate thereof electrically coupled to the write word line WWL. In this embodiment, the source voltage VDD is greater than the operation voltage Vcell; and the operation voltage Vcell is greater than the source voltage VSS. 
     Specifically, if both of the N-type transistors N 1 , N 2  in the operation voltage supply circuit  201  are implemented by a general-threshold-voltage transistor, the memory cell  203  is configured to receive an operation voltage about VDD-0.7V while being operated in a data write period. If both of the N-type transistors N 1 , N 2  in the operation voltage supply circuit  201  are implemented by a high-threshold-voltage transistor, the memory cell  203  is configured to receive an operation voltage less than VDD-0.7V while being operated in a data write period. If both of the N-type transistors N 1 , N 2  in the operation voltage supply circuit  201  are implemented by a low-threshold-voltage transistor, the memory cell  203  is configured to receive an operation voltage greater than VDD-0.7V while being operated in a data write period. In other words, the operation voltage Vcell received by the memory cell  203  may vary in accordance with the type of threshold-voltage transistor adopted in the N-type transistors N 1 , N 2 . 
       FIG. 3  is a schematic diagram of an operation voltage supply circuit  301  and a respective memory cell  303  in accordance with another embodiment of the present invention; wherein the operation voltage supply circuit  301  and the memory cell  303  herein are equivalent to the operation voltage supply circuit  101  and the memory cell  103  in  FIG. 1 , respectively. As shown, the circuit structure shown in  FIG. 3  is similar to that in  FIG. 2 . The main difference between the two circuit structures is that the operation voltage supply circuit  201  in  FIG. 2  is constituted by two N-type transistors, two P-type transistors and two inverters but the operation voltage supply circuit  301  in  FIG. 3  is constituted by one N-type transistor, two P-type transistors and two inverters. Specifically, in the operation voltage supply circuit  301 , the N-type transistor N 1  is configured to have one source/drain and a gate thereof electrically coupled to a source voltage VDD and another source/drain thereof electrically coupled to a node for generating an operation voltage Vcell. The P-type transistor P 1  is configured to have one source/drain thereof electrically coupled to the node. The P-type transistor P 2  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 1  and another source/drain thereof electrically coupled to the source voltage VDD. The inverter INV 1  is configured to have an input terminal thereof electrically coupled to the bit line BL and an output terminal thereof electrically coupled to a gate of the P-type transistor P 2 . The inverter INV 2  is configured to have an input terminal thereof electrically coupled to the complementary bit line BLB and an output terminal thereof electrically coupled to a gate of the P-type transistor P 1 . In this embodiment, the source voltage VDD is greater than the operation voltage Vcell. 
     The memory cell  303  has a circuit structure similar to that of the memory cell  203  in  FIG. 2 . As shown, the memory cell  303  includes two P-type transistors P 3 , P 4  and four N-type transistor N 2 , N 3 , N 4  and N 5 ; wherein the operations and circuit connections of these components in the memory cell  303  can be obtained by referring to the descriptions related to  FIG. 2 , and no redundant detail is to be given herein. In addition, it is to be noted that the N-type transistor N 1  herein may be implemented by a general-threshold-voltage transistor, a high-threshold-voltage transistor or a low-threshold-voltage transistor. 
       FIG. 4  is a circuit diagram of an operation voltage supply circuit  401  and a respective memory cell  403  in accordance with yet another embodiment of the present invention; wherein the operation voltage supply circuit  401  and the memory cell  403  herein are equivalent to the operation voltage supply circuit  101  and the memory cell  103  in  FIG. 1 , respectively. As shown, the circuit structure shown in  FIG. 4  is similar to that in  FIG. 3 . The main difference between the two circuit structures is that the operation voltage supply circuit  301  in  FIG. 3  is constituted by one N-type transistor, two P-type transistors and two inverters but the operation voltage supply circuit  401  in  FIG. 4  is constituted by three P-type transistors and two inverters. Specifically, in the operation voltage supply circuit  401 , the P-type transistor P 1  is configured to have one source/drain thereof electrically coupled to a source voltage VDD and another source/drain and a gate thereof electrically coupled to a node for generating an operation voltage Vcell. The P-type transistor P 2  is configured to have one source/drain thereof electrically coupled to the node. The P-type transistor P 3  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 2  and another source/drain thereof electrically coupled to the source voltage VDD. The inverter INV 1  is configured to have an input terminal thereof electrically coupled to the bit line BL and an output terminal thereof electrically coupled to a gate of the P-type transistor P 3 . The inverter INV 2  is configured to have an input terminal thereof electrically coupled to the complementary bit line BLB and an output terminal thereof electrically coupled to a gate of the P-type transistor P 2 . 
     The memory cell  403  has a circuit structure similar to that of the memory cell  203  in  FIG. 2 . As shown, the memory cell  403  includes two P-type transistors P 4 , P 5  and four N-type transistor N 1 , N 2 , N 3  and N 4 ; wherein the operations and circuit connections of these components in the memory cell  403  can be obtained by referring to the description related to  FIG. 2 , and no redundant detail is to be given herein. In addition, it is to be noted that the P-type transistor P 1  may be implemented by a general-threshold-voltage transistor, a high-threshold-voltage transistor or a low-threshold-voltage transistor. In this embodiment, the source voltage VDD is greater than the operation voltage Vcell; and the operation voltage Vcell is greater than the source voltage VSS. 
       FIG. 5  is a schematic diagram of an operation voltage supply circuit  501 , a respective memory cell  503  and an associated bias voltage supply circuit  502  in accordance with still yet another embodiment of the present invention; wherein the operation voltage supply circuit  501  and the memory cell  503  herein are equivalent to the operation voltage supply circuit  101  and the memory cell  103  in  FIG. 1 , respectively. As shown, the main difference between the circuit structure in  FIG. 5  and that in  FIG. 2  is that the operation voltage supply circuit  501  in  FIG. 5  is configured to receive a bias voltage Vbias (about 0.8×VDD) generated by the bias voltage supply circuit  502  and provide the operation voltage Vcell to the memory cell  503  when the memory cell  503  is selected. 
     Specifically, the operation voltage supply circuit  501  mainly includes four P-type transistors P 1 , P 2 , P 3  and P 4  and two inverters INV 1  and INV 2 . The P-type transistors P 1 , P 2  each are configured to have one source/drain thereof electrically coupled to the bias voltage Vbias and another source/drain thereof electrically coupled to the node in the operation voltage supply circuit  501  for generating an operation voltage Vcell. The P-type transistor P 3  is configured to have one source/drain thereof electrically coupled to the node. The P-type transistor P 4  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 3  and another source/drain thereof electrically coupled to the source voltage VDD. The inverter INV 1  is configured to have an input terminal thereof electrically coupled to the bit line BL and an output terminal thereof electrically coupled to a gate of the P-type transistor P 4 . The inverter INV 2  is configured to have an input terminal thereof electrically coupled to the complementary bit line BLB and an output terminal thereof electrically coupled to a gate of the P-type transistor P 3 . 
     The bias voltage supply circuit  502  mainly includes a P-type transistor P 5  and three N-type transistors N 1 , N 2  and N 3 . The P-type transistor P 5  is configured to have one source/drain thereof electrically coupled to the source voltage VDD and another source/drain and a gate thereof electrically coupled to the node in the bias voltage supply circuit  502  for generating the aforementioned bias voltage Vbias. The N-type transistor N 1  is configured to have one source/drain and a gate thereof electrically coupled to the node in the bias voltage supply circuit  502 . The N-type transistor N 2  is configured to have one source/drain and a gate thereof electrically coupled to another source/drain of the N-type transistor N 1 . The N-type transistor N 3  is configured to have one source/drain and a gate thereof electrically coupled to another source/drain of the N-type transistor N 2  and another source/drain thereof electrically coupled to the source voltage VSS. In this embodiment, the N-type transistors N 1 , N 2  and N 3  all are configured to have the substrates thereof electrically coupled to the source voltage VSS. 
     The memory cell  503  mainly includes two P-type transistors P 6 , P 7  and sixth N-type transistor N 4 , N 5 , N 6 , N 7 , N 8  and N 9 . The P-type transistors P 6 , P 7  each are configured to have one source/drain thereof electrically coupled to the node in the operation voltage supply circuit  501  from which to receive the operation voltage Vcell. The N-type transistor N 4  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 6 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to a gate of the P-type transistor P 6 . The N-type transistor N 5  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 7 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to a gate of the P-type transistor P 7 . The N-type transistor N 6  is configured to have one source/drain thereof electrically coupled to the bit line BL, another source/drain thereof electrically coupled to one source/drain of the N-type transistor N 4  and a gate of the N-type transistor N 5 , and a gate thereof electrically coupled to the write word line WWL. The N-type transistor N 7  is configured to have one source/drain thereof electrically coupled to the complementary bit line BLB, another source/drain thereof electrically coupled to one source/drain of the N-type transistor N 5  and a gate of the N-type transistor N 4 , and a gate thereof electrically coupled to the write word line WWL. The N-type transistor N 8  is configured to have one source/drain thereof electrically coupled to a read bit line RBL and a gate thereof electrically coupled to a read word line RWL. The N-type transistor N 9  is configured to have one source/drain thereof electrically coupled to another source/drain of the N-type transistor N 8 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to a gate of the N-type transistor N 4 . In this embodiment, the source voltage VDD is greater than the bias voltage Vbias, the operation voltage Vcell and the source voltage VSS; the bias voltage Vbias is equal to the operation voltage Vcell; and the bias voltage Vbias and the operation voltage Vcell both are greater than the source voltage VSS. 
       FIG. 6  is a schematic diagram of an operation voltage supply circuit  601  and a respective memory cell  603  in accordance with another further embodiment of the present invention; wherein the operation voltage supply circuit  601  and the memory cell  603  herein are equivalent to the operation voltage supply circuit  101  and the memory cell  103  in  FIG. 1 , respectively. As shown, the operation voltage supply circuit  601  in this embodiment mainly includes three N-type transistors N 1 , N 2  and N 3 . The N-type transistor N 1  is configured to have one source/drain and a gate thereof electrically coupled to a node for generating the operation voltage Vcell and another source/drain thereof electrically coupled to the source voltage VSS. The N-type transistor N 2  is configured to have one source/drain thereof electrically coupled to the aforementioned node and a gate thereof electrically coupled to the complementary bit line BLB. The N-type transistor N 3  is configured to have one source/drain thereof electrically coupled to another source/drain of the N-type transistor N 2 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to the bit line BL. 
     The memory cell  603  mainly includes two P-type transistors P 1 , P 2  and sixth N-type transistor N 4 , N 5 , N 6 , N 7 , N 8  and N 9 . The P-type transistors P 1 , P 2  each are configured to have one source/drain thereof electrically coupled to the source voltage VDD. The N-type transistor N 4  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 1 , another source/drain thereof electrically coupled to a node in the operation voltage supply circuit  601  from which to receive the operation voltage Vcell, and a gate thereof electrically coupled to a gate of the P-type transistor P 1 . The N-type transistor N 5  is configured to have one source/drain thereof electrically coupled to another source/drain of the P-type transistor P 2 , another source/drain thereof electrically coupled to the node in the operation voltage supply circuit  601  from which to receive the operation voltage Vcell, and a gate thereof electrically coupled to a gate of the P-type transistor gate P 2 . The N-type transistor N 6  is configured to have one source/drain thereof electrically coupled to the bit line BL, another source/drain thereof electrically coupled to one source/drain of the N-type transistor N 4  and a gate of the N-type transistor N 5 , and a gate thereof electrically coupled to the write word line WWL. The N-type transistor N 7  is configured to have one source/drain thereof electrically coupled to the complementary bit line BLB, another source/drain thereof electrically coupled to one source/drain of the N-type transistor N 5  and a gate of the N-type transistor N 4 , and a gate thereof electrically coupled to the write word line WWL. The N-type transistor N 8  is configured to have one source/drain thereof electrically coupled to a read bit line RBL and a gate thereof electrically coupled to a read word line RWL. The N-type transistor N 9  is configured to have one source/drain thereof electrically coupled to another source/drain of the N-type transistor N 8 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to a gate of the N-type transistor N 5  and another source/drain of the N-type transistor N 4 . In this embodiment, the source voltage VDD is greater than the operation voltage Vcell; and the operation voltage Vcell is greater than the source voltage VSS. 
     The memory cell  603  in the aforementioned description of the another further embodiment is exemplified by eight transistors. However, it is understood that the memory cell  603  in another different embodiment may be implemented by six transistors; in other words, the memory cell  603  may include just two P-type transistors P 1  P 2  and four N-type transistors, N 4 , N 5 , N 6  and N 7 . 
       FIG. 7  is a schematic diagram of an operation voltage supply circuit  701  and a respective memory cell  703  in accordance with another yet further embodiment of the present invention; wherein the operation voltage supply circuit  701  and the memory cell  703  herein are equivalent to the operation voltage supply circuit  101  and the memory cell  103  in  FIG. 1 , respectively. As shown, the circuit structure shown in  FIG. 7  is similar to that in  FIG. 6 . The main difference between the two circuit structures is that the operation voltage supply circuit  601  in  FIG. 6  is constituted by three N-type transistors but the operation voltage supply circuit  701  in  FIG. 7  is constituted by two P-type transistor and four N-type transistors. Specifically, the P-type transistor P 1  is configured to have one source/drain and a substrate thereof electrically coupled to a source voltage VDD and a gate thereof electrically coupled to the complementary bit line BLB. The P-type transistor P 2  is configured to have one source/drain and a substrate thereof electrically coupled to the source voltage VDD, another source/drain thereof electrically coupled to another source/drain of the P-type transistor P 1 , and a gate thereof electrically coupled to the bit line BL. The N-type transistor N 1  is configured to have one source/drain and a gate thereof electrically coupled to each of another source/drain of the P-type transistors P 1 , P 2 . The N-type transistor N 2  is configured to have one source/drain and a gate thereof electrically coupled to another source/drain of the N-type transistor N 1  and another source/drain thereof electrically coupled to a node for generating the operation voltage Vcell. The N-type transistor N 3  is configured to have one source/drain thereof electrically coupled to the node and a gate thereof electrically coupled to the complementary bit line BLB. The N-type transistor N 4  is configured to have one source/drain electrically coupled to another source/drain of the N-type transistor N 3 , another source/drain thereof electrically coupled to the source voltage VSS, and a gate thereof electrically coupled to the bit line BL. 
     The memory cell  703  has a circuit structure similar to that of the memory cell  603  in  FIG. 6 . As shown, the memory cell  703  includes two P-type transistors P 3 , P 4  and six N-type transistor N 5 , N 6 , N 7 , N 8 , N 9  and N 10 ; wherein the operations and circuit connections of these components in the memory cell  703  can be obtained by referring to the description related to  FIG. 6 , and no redundant detail is to be given herein. In this embodiment, the source voltage VDD is greater than the operation voltage Vcell; and the operation voltage Vcell is greater than the source voltage VSS. 
     The memory cell  703  in the aforementioned description of the another yet further embodiment is exemplified by eight transistors. However, it is understood that the memory cell  703  in this embodiment may be instead, be implemented by just six transistors; in other words, the memory cell  703  may just include two P-type transistors P 3 , P 4  and four N-type transistors, N 5 , N 6 , N 7  and N 8 . 
     In summary, by dividing the memory cells in the same column of a memory cell array into at least two groups of memory cells, configuring one of the two groups of memory cells to receive an operation voltage provided by one of the at least two groups of operation voltage supply circuits in the memory cell array, and configuring the other one of the two groups of memory cells to receive an operation voltage provided by the other one of the at least two groups of operation voltage supply circuits in the memory cell array, the memory cell array of the present invention employing the aforementioned circuit structure not only can reduce the impact of the IR-Drop on the memory cells but also enhance the static noise margin (SNM) of the memory cells. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.