Abstract:
A memory control circuit in a memory chip includes a selection controller that can switch the memory chip between selected and deselected states. The selection controller sends and receives access wait signals to and from at least one other memory chip. One access wait signal indicates that the selection controller has placed the memory chip in the deselected state. Another access wait signal, when received, causes the selection controller to place the memory chip in the selected state. A set of memory chips including this memory control circuit can shift access among themselves without receiving control signals from an external device. The external device can accordingly access the memory chips with minimal delays and minimal overhead.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a memory control circuit in a memory chip, more particularly to a memory control circuit that exchanges control signals with memory control circuits in other memory chips. 
         [0003]    2. Description of the Related Art 
         [0004]    In systems that access a plurality of memory chips, the memory chips are connected to a shared bus and are individually selected by chip select signals. In conventional systems, a processor or memory controller must generate a separate chip select signal for each memory chip, or a multi-bit chip select signal that can be decoded to select the memory chips individually. Each time memory access shifts from one chip to another, a new chip select signal and, for certain types of memory, other overhead signals must be generated. This overhead takes up time and imposes a processing load on the processor or memory controller. In read access, there is also a delay while the new memory chip senses and amplifies the data to be read. All of these factors slow down access operations, as will be shown in the detailed description of the invention. 
         [0005]    It would be desirable for access to proceed continuously from one memory chip to another without delay, and without overhead. 
       SUMMARY OF THE INVENTION 
       [0006]    An object of the present invention is to enable access to shift continuously among a plurality of memory chips. 
         [0007]    Another object of the invention is to enable the memory chips to shift access among themselves autonomously. 
         [0008]    The invention provides a memory control circuit disposed in a memory chip. The memory chip also has a memory array storing data for access by an external device. The memory chip operates in a selected state in which access is enabled and a deselected state in which access is disabled. The memory control circuit includes a selection controller that can switch the memory chip between the selected and deselected states. 
         [0009]    The selection controller sends and receives access wait signals to and from at least one other memory chip. The access wait signals indicate transitions between the selected and deselected states. One access wait signal is preferably sent to indicate that the selection controller has placed the memory chip in the deselected state. Another access wait signal is preferably received to make the selection controller place the memory chip in the selected state. 
         [0010]    The invention also provides a memory chip including the invented memory control circuit, and a system comprising a processor connected to a plurality of such memory chips. The memory chips can uses the access wait signals to select and deselect each other in a cyclic sequence, permitting access to shift from one memory chip to another without delay and without imposing an overhead load on the processor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    In the attached drawings: 
           [0012]      FIG. 1  is a block diagram of a system embodying the present invention; 
           [0013]      FIG. 2  is a timing waveform diagram illustrating write access in the system in  FIG. 1 ; 
           [0014]      FIG. 3  is a timing waveform diagram illustrating read access in the system in  FIG. 1 ; 
           [0015]      FIG. 4  is a block diagram of a conventional system; 
           [0016]      FIG. 5  is a timing waveform diagram illustrating write access in the system in  FIG. 4 ; and 
           [0017]      FIG. 6  is a timing waveform diagram illustrating read access in the system in  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    An embodiment of the invention will now be described with reference to the attached drawings, in which similar elements are indicated by similar reference characters. 
         [0019]    Referring to  FIG. 1 , the memory chips in the embodiment are random access memory (RAM) chips  10 A 1 ,  10 A 2 ,  10 A 3  accessed by a central processing unit (CPU)  1  via a shared bus. The bus signal lines include a plurality of address/data (AD/DT) signal lines  2  (shown as one line for simplicity), an address strobe (AS) signal line  3 , a write/read (WR) signal line  4 , an access clock (AC) signal line, and a plurality of chip select (CS) signal lines  6  (shown as one line for simplicity). 
         [0020]    The address/data signal lines  2  carry address signals, command signals, and data signals. Address and command signals are sent from the CPU  1  to the memory chips. Data signals may be sent in either direction. 
         [0021]    The address strobe signal is output from the CPU  1  to the memory chips. The address strobe signal goes high to indicate that the signals on the address/data signal lines  2  are address or command signals, and low to indicate that these signals are data signals. 
         [0022]    The write/read signal W/R indicates the direction of the signals on the address/data signal lines  2 . When W/R is high, the signals on the address/data signal lines  2  are sent by the CPU  1  and received by the memory chips  10 A 1 ,  10 A 2 ,  10 A 3 . When W/R is low, the signals on the address/data signal lines  2  are sent by the memory chips and received by the CPU  1 . 
         [0023]    The access clock AC synchronizes the signals on the address/data signal lines  2 . The signals on the address/data signal lines  2  are valid while the access clock signal is low and are latched at the rising edge of the access clock signal. 
         [0024]    The chip select signals CS select the memory chips  10 A 1 ,  10 A 2 ,  10 A 3  individually. The selected memory chip is available for data read or write access. 
         [0025]    Each memory chip  10 A i  (i=1 to 3) comprises an interface (I/F)  11   i , a register (REG)  12 A i , a memory array controller (MEM ARRAY CONTROLLER)  13 A i , a memory array  14   i , and a selection controller (SEL CNT)  15   i . The register  12 A i , memory array controller  13 A i , and selection controller  15   i  constitute the memory control circuit. 
         [0026]    The interface  11   i  receives control signals from the CPU  1  via the shared bus and sets them in the register  12 A i  or sends them to the memory array controller  13 A i , and transfers data between the memory array controller  13 A i  and the CPU  1 . 
         [0027]    The register  12 A i  holds control information set by the CPU  1  via the interface  11   i . This information includes a control bit (CON) that enables and disables the operation of the selection controller  15   i . The register  12 A i  outputs the value of this bit continuously to the selection controller  15   i . Information stored in the register  12 A i  may also be read by the CPU  1  through the interface  11   i . Although only one register  12 A i  is shown in the drawing, there may be a plurality of registers. 
         [0028]    The memory array controller  13 A i  controls the reading and writing of data in the memory array  14   i  according to commands and addresses received from the CPU  1 , sends address signals (ADR) to the memory array  14   i , and transfers data (DAT) between the interface  11   i  and memory array  14   i . In addition, the memory array controller  13 A i  stores addresses in the selection controller  15   i , and receives the stored addresses from the selection controller  15   i . 
         [0029]    The memory array  14   i  is organized into rows and columns. For simplicity, an array with three rows and three columns is shown, although in practice the number of rows and columns may be much larger. Memory locations are identified by column addresses X 1  to X 3  and row addresses Y 1  to Y 3 . 
         [0030]    The selection controller  15   i  holds the address stored by the memory array controller  13   i  and increments it in synchronization with the access clock signal, sends an access wait signal WTij to memory chip  10 A j , and receives an access wait signal WTki from memory chip  10 A k , where j and k are integers differing from each other and from i (j, k=1 to 3). The access wait signal lines interconnect the memory chips  10 A 1  to  10 A 3  in a loop: memory chip  10 A 1  sends access wait signal WT 12  to memory chip  10 A 2 ; memory chip  10 A 2  sends access wait signal WT 23  to memory chip  10 A 3 ; memory chip  10 A 3  sends access wait signal WT 31  to memory chip  10 A 1 . When the selection controller  15   i  is enabled by the CON control bit signal, the sending and receiving of access wait signals is related to the incrementing of the stored address as described below. When the selection controller  15   i  is disabled by the CON control bit signal, it simply sends the incoming access wait signal WTki to the next memory chip as the outgoing access wait signal WTij. 
         [0031]    The selection controller  15   i  also generates access start and end signals (not shown) that control the memory array controller  13 A i . 
         [0032]    Read and write operations in which the CPU  1  views the memory chips  10 A 1 ,  10 A 2 ,  10 A 3  as a single memory will now be described. The CPU  1  treats the memory space of the memory chips  10 A 1 ,  10 A 2 ,  10 A 3  as a combined array with three rows and nine columns, identified by column addresses X 1  to X 9  as shown in  FIG. 1 . The CPU  1  will write and then read data words MD 1  to MD 27  in this memory space. Access takes place in column-row order, all nine columns in each row being accessed before the next row is accessed. Access accordingly cycles among the three memory chips  10 A 1 ,  10 A 2 ,  10 A 3 . 
         [0033]    To enable this type of data access, before the access operations begin, the CPU  1  sends the memory chips  10 A 1 ,  10 A 2 ,  10 A 3  initialization commands that set their internal control signals CON to the active logic level, enabling the selection controller in each chip. 
         [0034]      FIG. 2  illustrates the first part of the write access sequence. The CPU  1  holds the write/read signal W/R at the high logic level, designating write access, throughout the write access sequence. The illustrated address signals (ADR) show the values stored in the selection controllers  15   1 ,  15   2 ,  15   3  in the memory chips  10 A 1 ,  10 A 2 ,  10 A 3 . 
         [0035]    Between times T 0  and T 1 , the CPU  1  sets the chip select signals CS to a value (denoted RAM 1 ) selecting the first memory chip  10 A 1 , outputs a write command (RAM) on the address/data signal lines  2 , and drives the address strobe signal AS high, transferring the write command to all three memory chips  10 A 1 ,  10 A 2 ,  10 A 3 . 
         [0036]    At time T 1  the address strobe signal AS goes low, the access clock signal AC goes high, and the write command and chip select signals are latched, placing all three memory chips  10 A 1  to  10 A 3  in the write mode. All three access wait signals WT 12 , WT 23 , WT 31  go high. In the selected memory chip  10 A 1 , selection controller  15   1  drives the access start signal (START) to the active (high) logic level, and memory array controller  13 A 1  writes the address of the first column in the first row (X 1 , Y 1 ) in selection controller  15   1 . 
         [0037]    In the intervals from times T 1  to T 2 , T 2  to T 3 , and T 3  to T 4 , the CPU  1  sets data MD 1 , MD 2 , and MD 3  on the address/data signal lines  2 , and memory array controller  13 A 1  writes these data at successive addresses (X 1 , Y 1 ), (X 2 , Y 1 ) and (X 3 , Y 1 ) in the first row in memory array  14   1 . Selection controller  15   1  increments the column address at times T 2  and T 3 . 
         [0038]    When the selection controller  15   1  recognizes the last column address X 3  at time T 3 , it activates the internal access end signal (END). At time T 4 , selection controller  15   1  drives the access start and end signals to the inactive (low) level, temporarily stops incrementing addresses, and drives access wait signal WT 12  low. While WT 12  is low, the first memory chip  10 A 1  remains in the write access mode but deselects itself and does not latch data on the address/data signal lines  2 . 
         [0039]    When selection controller  15   2  in the second memory chip  10 A 2  recognizes the high-to-low transition of the WT 12  signal, it activates the access start signal. Memory array controller  13 A 2  then performs the same operations as memory array controller  13 A 1  in the first memory chip  10 A 1  to write data MD 4 , MD 5 , MD 6 , which the CPU  1  places on the address/data signal lines  2  from time T 4  to time T 7 , at addresses (X 1 , Y 1 ), (X 2 , Y 1 ), (X 3 , Y 1 ) in memory array  14   2 . The first address (X 1 , Y 1 ) is written in selection controller  15   2  by memory array controller  13 A 2  at time T 4  and incremented at times T 5  and T 6 . 
         [0040]    When selection controller  15   2  recognizes that the last column address X 3  has been reached at time T 6 , it activates the internal access end signal in the second memory chip  10 A 2 . At time T 7 , selection controller  15   2  drives the access start and end signals and access wait signal WT 23  low, deselecting the second memory chip  10 A 2 . 
         [0041]    When selection controller  15   3  in the third memory chip  10 A 3  recognizes the high-to-low transition of the WT 23  signal, it selects the third memory chip  10 A 3  by driving its internal access start signal to the high level. Data MD 7 , MD 8 , and MD 9  are now written at addresses (X 1 , Y 1 ), (X 2 , Y 1 ), and (X 3 , Y 1 ) in memory array  14   3  from time T 7  to time T 10  by the same procedure as followed in the second memory chip  10 A 2  from time T 4  to time T 7 . At time T 10 , selection controller  15   3  drives the internal access start and end signals in memory chip  10 A 3  and access wait signal WT 31  to the low level. 
         [0042]    When selection controller  15   1  in the first memory chip  10 A 1  recognizes the high-to-low transition of access wait signal WT 31 , it restores access wait signal WT 12  to the high level, reactivates the internal access start signal, and increments the stored address from (X 3 , Y 1 ) to (X 1 , Y 2 ). From time T 10  to time T 13 , data MD 10 , MD 11 , and MD 12  are written at successive addresses (X 1 , Y 2 ), (X 2 , Y 2 ), and (X 3 , Y 2 ) in the second row in memory array  14   1  by the same procedure as followed in the second memory chip  10 A 2  from time T 4  to time T 7 . 
         [0043]    Access continues to cycle in this way among the three memory chips  10 A 1 ,  10 A 2 ,  10 A 3  until all the remaining data up to MD 27  have been stored at the locations shown in  FIG. 1  in the three memory arrays  14   1 ,  14   2 ,  14   3 . 
         [0044]    A feature of this write access sequence is that the CPU  1  only has to generate chip select signals once, at the beginning of the sequence. Thereafter, the access wait signals generated by the memory chips themselves override the chip select signals, shifting access from chip to chip at the proper times. 
         [0045]    Another feature is that commands have to be placed on the address/data signal lines  2  only once, in the interval from time T 0  to time T 1 . Thereafter, the CPU  1  can simply place successive data values (MD 1 -MD 27 ) on the address/data signal lines  2  in successive clock cycles. 
         [0046]    The entire write access sequence is accordingly completed in a minimum length of time with a minimum processing load on the CPU  1 . 
         [0047]    The read access sequence, the first part of which is illustrated in  FIG. 3 , is generally similar, the three memory chips using the access wait signals to shift access among themselves autonomously. The read access sequence is more complex, however, because of the delay from the generation of a new row address in a memory chip until the data in the new row become available for output. The delay time, which is necessary for sensing and amplification of the data, is equal to one cycle of the access signal AC in this embodiment. 
         [0048]    Between times T 0  and T 1 , while continuing to hold the write/read signal W/R at the high logic level, the CPU  1  sets the chip select signals CS to a value (RAM 1 ) selecting the first memory chip  10 A 1 , sets a read command (denoted RAM) on the address/data signal lines  2 , and drives the address strobe signal AS high, transferring the read command to all three memory chips  10 A 1 ,  10 A 2 ,  10 A 3 . 
         [0049]    At time T 1  the address strobe signal AS goes low, the access clock signal AC goes high, and the read command and chip select signals are latched, placing all three memory chips  10 A 1 ,  10 A 2 ,  10 A 3  in the read mode. The selection controllers  15   1 ,  15   2 ,  15   3  drive all three access wait signals WT 12 , WT 23 , and WT 31  and all three access start signals (START) to the high logic level. In addition, the memory array controllers  13 A 1 ,  13 A 2 ,  13 A 3  all write the first address in the first row (X 1 , Y 1 ) into the selection controllers  15   1 ,  15   2 ,  15   3 . 
         [0050]    Between times T 1  and T 2 , sense amplification of the data in the first row takes place in all three memory chips  10 A 1 ,  10 A 2 ,  10 A 3 . The selected memory chip  10 A 1  outputs dummy data (DMY) on the address/data signal lines  2 . 
         [0051]    Between times T 2  and T 3 , memory array controller  13 A 1  places the data MD 1  stored at address (X 1 , Y 1 ) in the first memory chip  10 A 1  in an output buffer (not shown) for output on the address/data signal lines  2 , and selection controller  15   1  increments to the next address (X 2 , Y 1 ). The CPU  1  reads data MD 1  from the address/data signal lines  2  in synchronization with the rise of the access signal AC at time T 3 . The addresses held in the selection controllers  15   2 ,  15   3  in the nonselected memory chips  10 A 2  and  10 A 3  are also incremented to (X 2 , Y 1 ), but no data are output from these chips. 
         [0052]    Between times T 3  and T 4 , the data MD 2  stored at address (X 2 , Y 1 ) in memory chip  10 A 1  are similarly buffered and read and the address stored in selection controller  15   1  is incremented to (X 3 , Y 1 ). Selection controller  15   1  recognizes that the end of the first row has been reached and activates the access end signal at time T 4 . The addresses held in the selection controllers  15   2 ,  15   3  in the nonselected memory chips  10 A 2  and  10 A 3  remain at (X 2 , Y 1 ) and are not incremented. 
         [0053]    Between times T 4  and T 5 , the data MD 3  stored at address (X 3 , Y 1 ) in memory chip  10 A 1  are similarly buffered and read. The address stored in selection controller  15   1  is incremented to (X 1 , Y 2 ), causing memory array controller  13 A 1  to start sense amplification of the data in the second row in the memory array  14   1 . 
         [0054]    At time T 5 , selection controller  15   1  drives the access start and end signals and access wait signal WT 12  low. These signals will remain low during the period in which the first memory chip  10 A 1  is deselected, until time T 11 . The address held in selection controller  15   1  is incremented to (X 2 , Y 2 ) at time T 5  and then left at this value. 
         [0055]    When the selection controller  15   2  in the second memory chip  10 A 2  recognizes the high-to-low transition of access wait signal WT 12  at time T 5 , it drives the internal access start signal in this memory chip to the high level. The second memory chip  10 A 2  is now selected for access. The data MD 4  stored at address (X 1 , Y 1 ), which have been available for output since time T 2 , are placed in the output buffer (not shown) and output on the address/data signal lines  2 . The CPU  1  latches data MD 4  at time T 6 . 
         [0056]    Between times T 6  and T 7 , the data MD 5  stored at address (X 2 , Y 1 ) in memory chip  10 A 2  are buffered and read and the address stored in selection controller  15   2 , which has remained at (X 2 , Y 1 ) since time T 2 , is incremented to (X 3 , Y 1 ). Selection controller  15   2  recognizes that the end of the first row in memory array  14   2  has been reached and activates the access end signal at time T 7 . 
         [0057]    Between times T 7  and T 8 , the data MD 6  stored at address (X 3 , Y 1 ) in memory chip  10 A 2  are similarly buffered and read and the address stored in selection controller  15   2  is incremented to (X 1 , Y 2 ), causing memory array controller  13 A 2  to start sense amplification of the data in the second row of memory array  14   2 . At time T 8 , selection controller  15   2  increments its stored address to (X 2 , Y 2 ) and drives the access start and end signals and access wait signal WT 23  low, deselecting the second memory chip  10 A 2 . Selection controller  15   3  now places the third memory chip  10 A 3  in the selected state. 
         [0058]    Data MD 7  to MD 9  are then read in a similar manner from the third memory chip  10 A 3  from time T 8  to time T 11 . At time T 11  selection controller  15   3  drives the access start and end signals and access wait signal WT 31  low, and access returns to the first memory chip  10 A 1 . 
         [0059]    From time T 11  to time T 14 , the first memory chip  10 A 1  outputs the data MD 10  to MD 12  stored in the second row of memory array  14   1 , which were sensed and amplified between times T 4  and T 5  and have been held in readiness since then. The procedure is the same as used by the second and third memory chips  10 A 2 ,  10 A 3  to output data MD 4  to MD 9 . Thereafter, access continues to cycle among the three memory chips until all data up to MD 27  have been read. 
         [0060]    This read access sequence has the same features as noted in the write access sequence described above: the CPU  1  only has to generate chip select signals and place commands on the address/data signal lines  2  once, at the beginning of the sequence. Another feature is that read access is delayed for sense amplification only once, from time T 0  to time T 1 . Thereafter, each memory chip completes sense amplification well in advance of data output, so read access can shift immediately from one memory chip to another with no delay. The entire read access sequence is thus completed in a minimum length of time with a minimum processing load on the CPU  1 . 
         [0061]    For comparison, read and write access sequences using conventional memory chips that do not generate access wait signals will now be described.  FIG. 4  shows a system including a CPU  1  and three conventional memory chips  10   1 ,  10   2 ,  10   3 . These memory chips are identical to the novel memory chips shown in  FIG. 1  except that they have no selection controller. Accordingly, the registers  12   1 ,  12   2 ,  12   3  do not output a CON signal, and the memory array controllers  13   1 ,  13   2 ,  13   3  store addresses internally and increment the addresses themselves. 
         [0062]      FIG. 5  shows the first part of a conventional write access sequence for storing data MD 1  to MD 27  in the conventional memory chips  10   1 ,  10   2 ,  10   3 . The sequence starts in the same way as the novel sequence in  FIG. 2  from time T 0  to time T 4 . Between times T 4  and T 5 , however, the CPU  1  must change the chip select signals to a value (denoted RAM 2 ) selecting the second memory chip  10   2  instead of the first memory chip  10   1 , and must place another write command (RAM) on the address/data signal lines  2  for the second memory chip  10   2  to receive. There is accordingly a one-cycle delay between the writing of data MD 3  in the first memory chip  10   1  and the writing of data MD 4  in second memory chip  10   2 . 
         [0063]    Similar delays occur between times T 8  and T 9 , when access shifts from the second memory chip  10   2  to the third memory chip  10   3  (the third memory chip is selected by a value denoted RAM 3  on the chip select signal lines), then between times T 12  and T 13 , when access shifts from the third memory chip  10   3  back to the first memory chip  10   1 , and so on. As a result, the conventional write access sequence in  FIG. 5  is slower than the novel write access sequence in  FIG. 2  by a factor of substantially 4:3. 
         [0064]      FIG. 6  shows the first part of a conventional read access sequence for reading data MD 1  to MD 27  from the conventional memory chips  10   1 ,  10   2 ,  10   3 . The sequence starts in the same way as the novel sequence in  FIG. 3  from time T 0  to time T 5 . Between times T 5  and T 7 , however, the CPU  1  must first, during one clock cycle, change the chip select signals to the value (RAM 2 ) selecting the second memory chip  10   2  and place a read command (RAM) on the address/data signal lines  2 , and must then wait for another clock cycle while the second memory chip  10   2  sense and amplifies the data in the first row in its memory array  14   2 . There is accordingly a two-cycle delay between the reading of data MD 3  from the first memory chip  10   1  and the reading of data MD 4  from second memory chip  10   2 . 
         [0065]    Similar delays occur between times T 10  and T 12 , between times T 15  and T 17 , and so on. The conventional read access sequence in  FIG. 6  is accordingly slower than the novel read access sequence in  FIG. 3  by a factor of about 5:3. 
         [0066]    The invention is not limited to the embodiment shown in  FIGS. 1 to 3 . For example, the memory chips need not be RAM chips; the invention is applicable to any type of memory chip. Each memory chip may have a plurality of memory arrays or banks. The CPU  1  may be replaced by another type of processor, or by a separate memory controller. 
         [0067]    Many variations in the memory control circuit itself are also possible. The following are some examples. 
         [0068]    The low-to-high transitions of access wait signals WT 23  and WT 31  at time T 1  in  FIGS. 2 and 3  may be delayed until the following high-to-low transitions of access wait signals WT 12  and WT 23 , respectively. 
         [0069]    Alternatively, the low-to-high transitions of the access wait signals may be synchronized with the low-to-high transitions of the internal access end signals. 
         [0070]    The active level of any signal may be either the high level or the low level. 
         [0071]    Data access need not start at the first column in row one; it may start at an arbitrary address specified by the CPU  1 . 
         [0072]    Addresses may be decremented instead of incremented. The incrementing and/or decrementing may be done by the memory array controller instead of the selection controller. 
         [0073]    If extra output buffers are provided, then during read access, amplification of the data in a given row in a memory array may start an arbitrary number of columns before the end of access to the preceding row, to provide adequate time for sense amplification. 
         [0074]    Those skilled in the art will recognize that still further variations are possible within the scope of the invention, which is defined in the appended claims.