Abstract:
In a power supply apparatus, a charge-pump type step-up circuit is adapted to charge a step-up capacitor by a power supply voltage, step up a charged voltage of the step-up capacitor using a charge-pump operation, and discharge a stepped-up voltage to a smoothing capacitor. A regulator has a first comparator adapted to compare a voltage corresponding to an output voltage of the step-up circuit with a reference voltage to generate a comparison output signal and skip a clock signal in accordance with the comparison output signal, so that the output voltage of the step-up circuit is brought close to a target voltage. Discharging of the smoothing capacitor is carried out through a resistor with a predetermined time constant when the output voltage of the step-up circuit is between the target voltage and a voltage lower than the target voltage by a predetermined value.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a power supply apparatus including a charge-pump type step-up circuit and a regulator for regulating the output voltage of the charge-pump type step-up circuit. 
         [0003]    2. Description of the Related Art 
         [0004]    A typical power supply apparatus suitably used in a driver for driving a display panel such as a liquid crystal display (LCD) panel of a mobile phone or a personal digital assistant (PDA) includes a charge-pump type step-up circuit and a regulator for regulating the output voltage of the charge-pump type step-up circuit. 
         [0005]    A prior art power supply apparatus is constructed by a charge-pump type step-up circuit having a single discharging (step-up) time constant of a smoothing capacitor, and a regulator formed by a voltage divider for dividing the output voltage of the step-up circuit to generate a divided voltage, a comparator for comparing the divided voltage with a reference voltage to generate a comparison output signal, and an AND circuit for supplying a clock signal to the step-up circuit in accordance with the comparison output signal (see: JP-2005-20971A). This will be explained later in detail. 
       SUMMARY OF THE INVENTION 
       [0006]    In the above-described prior art power supply apparatus, however, when a driven load is relatively small and the response characteristics of the comparator are relatively high, the power consumption would be remarkably increased. 
         [0007]    In order to decrease the power consumption, the response characteristics of the comparator are decreased or the comparator is a hysteresis-type comparator, by which large overshoots would be generated, which would deteriorate the elements of the apparatus. Also, the ripple of the output voltage of the step-up circuit would be increased. 
         [0008]    According to the present invention, in a power supply apparatus, a charge-pump type step-up circuit is adapted to charge a step-up capacitor by a power supply voltage, step up a charged voltage of the step-up capacitor using a charge-pump operation, and discharge a stepped-up voltage to a smoothing capacitor. A regulator has a first comparator adapted to compare a voltage corresponding to an output voltage of the step-up circuit with a reference voltage to generate a comparison output signal and skip a clock signal in accordance with the comparison output signal, so that the output voltage of the step-up circuit is brought close to a target voltage. Discharging of the smoothing capacitor is carried out through a resistor with a predetermined time constant when the output voltage of the step-up circuit is between the target voltage and a voltage lower than the target voltage by a predetermined value. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
           [0010]      FIG. 1  is a circuit diagram illustrating a prior art power supply apparatus; 
           [0011]      FIG. 2  is a timing diagram for explaining a first operation of the power supply apparatus of  FIG. 1 ; 
           [0012]      FIG. 3  is a timing diagram for explaining a second operation of the power supply apparatus of  FIG. 1 ; 
           [0013]      FIG. 4  is a timing diagram for explaining a third operation of the power supply apparatus of  FIG. 1 ; 
           [0014]      FIG. 5  is a circuit diagram illustrating an embodiment of the power supply apparatus according to the present invention; 
           [0015]      FIG. 6  is a detailed circuit diagram of an example of the step-up circuit of  FIG. 5 ; 
           [0016]      FIG. 7  is a timing diagram for explaining a first operation of the power supply apparatus of  FIG. 5 ; 
           [0017]      FIG. 8  is a timing diagram for explaining a second operation of the power supply apparatus of  FIG. 5 ; and 
           [0018]      FIG. 9  is a timing diagram for explaining a third operation of the power supply apparatus of  FIG. 1 . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0019]    Before the description of the preferred embodiment, a prior art power supply apparatus will be explained with reference to  FIGS. 1 ,  2 ,  3  and  4  (see: FIGS. 3, 4 and 5 of JP-2005-20971 A). 
         [0020]    In  FIG. 1 , a prior art power supply apparatus is constructed by a step-up circuit  10  for stepping up a power supply voltage V DD  as an input voltage in accordance with a skipped clock signal CLK 2  of a clock signal CLK 1  to generate a stepped-up voltage, i.e., an output voltage V out , and a regulator  20  for regulating the output voltage V out  of the step-up circuit  10  to a target voltage V t . In this case, the regulator  20  skips the clock signal CLK 1  in accordance with the output voltage V out  of the step-up circuit  10  to generate the clock signal CLK 2  and transmit it to the step-up circuit  10 . 
         [0021]    The charge pump circuit  10  is constructed by four switches SW 1 , SW 2 , SW 3  and SW 4 , a step-up capacitor C 1  and a smoothing capacitor C 2 . In this case, the set of the switches SW 1  and SW 2  as charging switching elements and the set of the switches SW 3  and SW 4  as discharging switching elements are complementarily turned ON and OFF by the clock signal CLK 2 . That is, a stand-by state where CLK 2 =“0” (low level), the switches SW 1  and SW 2  are turned ON while the switches SW 3  and SW 4  are turned OFF, so that the step-up capacitor C 1  is charged by a power supply voltage V DD . On the other hand, in a step-up state where CLK 2 =“1” (high level), the switches SW 1  and SW 2  are turned OFF while the switches SW 3  and SW 4  are turned ON, so that the power supply voltage V DD  is superposed onto the charged voltage of the step-up capacitor C 1 . Thus, the stand-by state and the step-up state are alternately repeated, so that a voltage at the smoothing capacitor C 2  becomes higher than the power supply voltage V DD . 
         [0022]    If duration periods of the stand-by state and the step-up state are long enough to charge the step-up capacitor C 1  and the smoothing capacitor C 2 , respectively, at their saturation states, the output voltage V out  of the step-up circuit  10  would become a voltage of 2·V DD . Conversely, if the duration period of the stand-by state and the step-up state is insufficient to charge the step-up capacitor C 1  and the smoothing capacitor C 2 , respectively, at their non-saturation states, the output voltage V out  of the step-up circuit  10  would become smaller than 2·V DD . That is, the regulator  20  is provided to make the output voltage V out  of the step-up circuit  10  to be a target voltage V t  which satisfies the following: 
         [0000]        V   t ≦2 ·V   DD    
         [0023]    The regulator  20  is constructed by a voltage divider  21  for generating a divided voltage V d1  of the output voltage V out  of the step-up circuit  10 , a reference voltage source  22  for generating a reference voltage V ref , a comparator  23  for comparing the divided voltage V d1  of the voltage divider  21  with the reference voltage V ref  to generate a comparison output signal CPS 1 , and an AND circuit  24  for passing a clock signal CLK 1  therethrough as the clock signal CLK 2  in accordance with the comparison output signal CPS 1 . That is, 
         [0000]        CLK 2 =CLK 1 ·CPS 1. 
         [0024]    Also, the divided voltage V d1  is represented by 
         [0000]        V   d1   =V   out   ·R 2/( R 1 +R 2) 
         [0025]    Therefore, the regulator  20  regulates the output voltage V out  of the step-up circuit  10  so that the output voltage V out  is brought close to the target voltage V t  represented by 
         [0000]        V   t   =V   ref ·( R 1 +R 2)/ R 2≦2 ·V   DD    
         [0026]    Thus, the target voltage V t  can be set by adjusting one or more of the reference voltage V ref  and the resistors R 1  and R 2 . 
         [0027]    In other words, the comparator  23  substantially compares the output voltage V out  of the step-up circuit  10  with the target voltage V t , to generate the comparison output signal CPS 1 . That is, if V out =≦V t , CPS 1 =“1” (high level). On the other hand, if V out &gt;V t , CPS 1 =“0” (low level). 
         [0028]    A first operation of the power supply apparatus of  FIG. 1  is explained next with reference to  FIG. 2  where a load L to which the output voltage V out  is applied is relatively large. 
         [0029]    First, at time t 1 , the clock signal CLK 1  is low so that the clock signal CLK 2  is also low. Therefore, the step-up circuit  10  is in a stand-by state where the switches SW 1  and SW 2  are turned ON and the switches SW 3  and SW 4  are turned OFF. 
         [0030]    Next, at time t 2 , since V out &lt;V t , the comparison output signal CPS 1  of the comparator  23  is “1” (high level), so that CLK 2 =CLK 1 . Therefore, when the clock signal CLK 1  is switched from “0” (low level) to “1” (high level), so that the clock signal CLK 2  (=CLK 1  CPS 1 ) is also switched from “0” (low level) to “1” (high level), the step-up circuit  10  enters a step-up state where the switches SW 1  and SW 2  are turned OFF and the switches SW 3  and SW 4  are turned ON. As a result, the output voltage V out  of the step-up circuit  10  approaches the target voltage V t . In this case, however, since the load L is relatively large, the output voltage V out  would not reach the target voltage V t  even at time t 3 , so that the comparison output signal CPS of the comparator  23  still remains at “1” (high level). 
         [0031]    Next, at time t 3 , when the clock signal CLK 1  is switched from “1” (high level) to “0” (low level), the clock signal CLK 2  is also switched from “1” (high level) to “0” (low level). Therefore, the step-up circuit  10  enters another stand-by state. 
         [0032]    After time t 4 , a similar step-up state to that from time t 2  to time t 3  and a similar stand-by state to that from time t 3  to time t 4  are alternately repeated. 
         [0033]    Thus, there is no problem in the first operation as shown in  FIG. 2 . 
         [0034]    A second operation of the power supply apparatus of  FIG. 1  is explained next with reference to  FIG. 3  where the load L to which the output voltage V out  is applied is relatively small and the response characteristics of the comparator  23  are relatively high. 
         [0035]    First, at time t 1 , the clock signal CLK 1  is low so that the clock signal CLK 2  is also low. Therefore, the step-up circuit  10  is in a stand-by state where the switches SW 1  and SW 2  are turned ON and the switches SW 3  and SW 4  are turned OFF. 
         [0036]    Next, at time t 2 , since V out &gt;V t , the comparison output signal CPS 1  of the comparator  23  is “1” (high level), so that CLK 2 =CLK 1 . Therefore, when the clock signal CLK 1  is switched from “0” (low level) to “1” (high level), so that the clock signal CLK 2  (=CLK 1  CPS 1 ) is also switched from “0” (low level) to “1” (high level), the step-up circuit  10  enters a step-up state where the switches SW 1  and SW 2  are turned OFF and the switches SW 3  and SW 4  are turned ON. As a result, the output voltage V out  of the step-up circuit  10  approaches the target voltage V t . In this case, however, since the load L is relatively small, the output voltage V out  would quickly reach the target voltage V t  at times t 21 , t 22 , . . . . In addition, since the response characteristics of the comparator  23  are relatively high, the comparison output signal CPS 1  of the comparator  23  would be quickly reversed. Therefore, step-up states and stand-by states are alternately and quickly repeated until time t 3  when the clock signal CLK 1  becomes “0” (low level). 
         [0037]    Next, at time t 3 , when the clock signal CLK 1  is switched from “1” (high level) to “0” (low level), the clock signal CLK 2  is also switched from “1” (high level) to “0” (low level). Therefore, the step-up circuit  10  enters another stand-by state. 
         [0038]    After time t 4 , similar step-up/stand-by states to these from time t 2  to time t 3  and a similar stand-by state to that from time t 3  to time t 4  are alternately repeated. 
         [0039]    In the second operation as shown in  FIG. 3 , however, since the clock signal CLK 2  repeats “0” (low level) and “1” (high level) very frequently when the clock signal CLK 1  is “1” (high level), the power consumption would be remarkably increased. 
         [0040]    A third operation of the power supply apparatus of  FIG. 1  is explained next with reference to  FIG. 4  where the load L to which the output voltage V out  is applied is relatively small and the response characteristics of the comparator  23  are relatively low. 
         [0041]    First, at time t 1 , the clock signal CLK 1  is low so that the clock signal CLK 2  is also low. Therefore, the step-up circuit  10  is in a stand-by state where the switches SW 1  and SW 2  are turned ON and the switches SW 3  and SW 4  are turned OFF. 
         [0042]    Next, at time t 2 , since V out &gt;V t , the comparison output signal CPS 1  of the comparator  23  is “1” (high level), so that CLK 2 =CLK 1 . Therefore, when the clock signal CLK 1  is switched from “0” (low level) to “1” (high level), so that the clock signal CLK 2  (=CLK 1  CPS 1 ) is also switched from “0” (low level) to “1” (high level), the step-up circuit  10  enters a step-up state where the switches SW 1  and SW 2  are turned OFF and the switches SW 3  and SW 4  are turned ON. As a result, the output voltage V out  of the step-up circuit  10  approaches the target voltage V t . In this case, however, since the load L is relatively small, the output voltage V out  would slowly reach the target voltage V t  at times t 31 , t 32 , . . . . On the other hand, since the response characteristics of the comparator  23  are relatively low, the comparison output signal CPS 1  of the comparator  23  would be slowly reversed. Therefore, step-up states and stand-by states are alternately and slowly repeated to have a large amplitude output voltage until time t 3  when the clock signal CLK 1  becomes “0” (low level). 
         [0043]    Next, at time t 3 , when the clock signal CLK 1  is switched from “1” (high level) to “0” (low level), the clock signal CLK 2  is also switched from “1” (high level) to “0” (low level). Therefore, the step-up circuit  10  enters another stand-by state. 
         [0044]    After time t 4 , similar step-up/stand-by states to these from time t 2  to time t 3  and a similar stand-by state to that from time t 3  to time t 4  are alternately repeated. 
         [0045]    In the third operation as shown in  FIG. 4 , the comparator  23  can be a hysteresis-type comparator with relatively high response characteristics. 
         [0046]    In the third operation as shown in  FIG. 4 , however, a time period from time t 31  to time t 32  or the like is large enough to generate large overshoots OS, which would remarkably increase the output voltage V out  of the step-up circuit  10 . At worst, when the output voltage V out  exceeds a rated value, the elements within the power supply apparatus of  FIG. 1  would deteriorate. Simultaneously, the ripple of the output voltage V out  would be increased. 
         [0047]    In  FIG. 5 , which illustrates an embodiment of the power supply apparatus according to the present invention, the step-up circuit  10  and the regulator  20  of  FIG. 1  are changed to a step-up circuit  10 ′ and a regulator  20 ′, respectively. 
         [0048]    In the step-up circuit  10 ′, the switch SW 4  of  FIG. 1  is replaced by a switch SW 4   a  as a discharging switching element controlled by a clock signal CLK 3  and a switch SW 4   b  as a discharging switching element associated with a resistor R 3  controlled by a clock signal CLK 4 . 
         [0049]    In the regulator  20 ′, the voltage divider  21  of  FIG. 1  is replaced by a voltage divider  21 ′, a comparator  25 , and gate circuits  26  and  27  are added to the elements of  FIG. 1 . 
         [0050]    In the voltage divider  21 ′, 
         [0000]        R 1 =R 1 a+R 1 b    
         [0051]    Therefore, the voltage divider  21 ′ generates a divided voltage V d2  of the output voltage V out  of the step-up circuit  10 ′ in addition to the divided voltage V d1 . In this case, the divided voltage V d2  is represented by 
         [0000]        V   d2   =V   out ( R 2 +R 1 b )/( R 1 +R 2)&gt; V   d1    
         [0052]    The comparator  25  compares the divided voltage V d2  with the reference voltage V ref  to generate a comparison output signal CPS 2 . Here, assume that a selection voltage for selecting the switches SW 4   a  and SW 4   b  is VS represented by 
         [0000]        V   s   =V   ref ·( R 1 +R 2)/( R 2 +R 1 b ) 
         [0000]      &lt;V t    
         [0053]    Then, the selection voltage V s  can be set by adjusting one or more of the reference voltage V ref , and the resistors R 1   a , R 1   b  and R 2 . 
         [0054]    In other words, the comparator  25  substantially compares the output voltage V out  of the step-up circuit  10 ′ with the selection voltage V s  to generate the comparison output signal CPS 2 . That is, if V out =≦V s , CPS 2 =“1” (high level). On the other hand, if V out &gt;V s , CPS 2 =“0” (low level). 
         [0055]    The gate circuit  26  passes the clock signal CLK 2  therethrough as the clock signal CLK 3  in accordance with the comparison output signal CPS 2 . That is, 
         [0000]        CLK 3 =CLK 2 ·CPS 2. 
         [0056]    The gate circuit  27  passes the clock signal CLK 2  therethrough as the clock signal CLK 4  in accordance with the comparison output signal /CPS 2 . That is, 
         [0000]        CLK 4 =CLK 2 ·/CPS 2. 
         [0057]    In the charge pump circuit  10 ′, the set of the switches SW 1  and SW 2  and the set of the switches SW 3 , SW 4   a  and SW 4   b  are complementarily turned ON and OFF by the clock signal CLK 2 . That is, in a stand-by state where CLK 2 =“0” (low level), the switches SW 1  and SW 2  are turned ON while the switches SW 3 , SW 4   a  and SW 4   b  are turned OFF, so that the step-up capacitor C 1  is charged by a power supply voltage V DD . On the other hand, in a fast step-up state where CLK 2 =“1” (high level), CLK 3 =“1” (high level) and CLK 4 =“0” (low level), the switches SW 1 , SW 2  and SW 4   b  are turned OFF while the switches SW 3  and SW 4   a  are turned ON, so that the power supply voltage V DD  is superposed onto the charged voltage of the step-up capacitor C 1  at a small time constant determined by the ON-resistance of the switch SW 4   a  and the capacitance of the smoothing capacitor C 2 . Also, in a slow step-up state where CLK 2 =“1” (high level), CLK 3 =“0” (low level) and CLK 4 =“1” (high level), the switches SW 1 , SW 2  and SW 4   a  are turned OFF while the switches SW 3  and SW 4   b  are turned ON, so that the power supply voltage V DD  is superposed onto the charged voltage of the step-up capacitor C 1  at a large time constant determined by the ON-resistance of the switch SW 4   b , the resistance of the resistor R 3  and the capacitance of the smoothing capacitor C 2 . Thus, the stand-by state and the fast and slow step-up states are alternately repeated, so that a voltage at the smoothing capacitor C 2  becomes higher than the power supply voltage V DD . 
         [0058]    In  FIG. 6 , which illustrates a detailed circuit diagram of the step-up circuit  10 ′ of  FIG. 5 , the switch SW 1  is formed by a p-channel MOS transistor whose gate is controlled by the clock signal CLK 2 , the switch SW 2  is formed by an n-channel MOS transistor whose gate is controlled by an inverted signal /CLK 2  of the clock signal CLK 2 , the switch SW 3  is formed by a p-channel MOS transistor whose gate is controlled by the signal /CLK 2 , the switch SW 4   a  is formed by a p-channel MOS transistor whose gate is controlled by an inverted signal /CLK 3  of the clock signal CLK 3  and the switch SW 4   b  is formed by a p-channel MOS transistor whose gate is controlled by an inverted signal /CLK 4  of the clock signal CLK 4 . 
         [0059]    In  FIG. 6 , the resistor R 3  can be a variable resistor. For example, the resistor R 3  is constructed by an n-channel depletion-type MOS transistor whose gate is grounded. Alternatively, the resistor R 3  can be variable in accordance with the difference between the target voltage V t  and the output voltage V out . 
         [0060]    A first operation of the power supply apparatus of  FIG. 5  is explained next with reference to  FIG. 7  where the load L to which the output voltage V out  is applied relatively large. 
         [0061]    First, at time t 1 , the clock signal CLK 1  is low so that the clock signal CLK 2  is also low. Therefore, the step-up circuit  10 ′ is in a stand-by state where the switches SW 1  and SW 2  are turned ON and the switches SW 3 , SW 4   a  and SW 4   b  are turned OFF. 
         [0062]    Next, at time t 2 , since V out &lt;V s &lt;V t , the comparison output signals CPS 1  and CPS 2  of the comparators  23  and  25   a  are both “1” (high level). Therefore, when the clock signal CLK 1  is switched from “0” (low level) to “1” (high level), the clock signal CLK 2  (=CLK 1 ·CPS 1 ) is switched from “0” (low level) to “1” (high level). Also, the clock signal CLK 3  (=CLK 2 ·CPS 2 ) is switched from “0” (low level) to “1” (high level) while the clock signal CLK 4  (=CLK 2 ·/CPS 2 ) remains at “0” (low level). Therefore, the step-up circuit  10 ′ enters a fast step-up state where the switches SW 1 , SW 2  and SW 4   b  are turned OFF and the switches SW 3  and SW 4   a  are turned ON. As a result, the output voltage V out  of the step-up circuit  10 ′ increases to the selection voltage V s . 
         [0063]    At time t 41 , when the output voltage V out  of the step-up circuit  10 ′ crosses the selection voltage V s , the comparison output signal CPS 2  of the comparator  25  is switched from “1” (high level) to “0” (low level), so that the clock signal CLK 3  (=CLK 2 ·CPS 2 ) is switched from “1” (high level) to “0” (low level) while the clock signal CLK 4  (=CLK 2 ·/CPS 2 ) is switched from “0” (low level) to “1” (high level). Therefore, the step-up circuit  10 ′ enters a slow step-up state where the switches SW 1 , SW 2  and SW 4   a  are turned OFF and the switches SW 3  and SW 4   b  are turned ON. As a result, the output voltage V out  of the step-up circuit  10 ′ approaches the target voltage V t . Additionally, since the load L is relatively large, the output voltage V out  would not reach the target voltage V t  even at time t 3 , so that the comparison output signal CPS 1  of the comparator  23  still remains at “1” (high level). 
         [0064]    Next, at time t 3 , when the clock signal CLK 1  is switched from “1” (high level) to “0” (low level), the clock signal CLK 2  is also switched from “1” (high level) to “0” (low level). Therefore, the step-up circuit  10 ′ enters another stand-by state. 
         [0065]    After time t 4 , similar fast and slow step-up states to those from time t 2  to time t 3  and a similar stand-by state to that from time t 3  to time t 4  are alternately repeated. 
         [0066]    Thus, there is no problem in the first operation as shown in  FIG. 7 . 
         [0067]    A second operation of the power supply apparatus of  FIG. 5  is explained next with reference to  FIG. 8  where the load L to which the output voltage V out  is applied is relatively small and the response characteristics of the comparator  23  are relatively high. 
         [0068]    First, at time t 1 , the clock signal CLK 1  is low so that the clock signal CLK 2  is also low. Therefore, the step-up circuit  10 ′ is in a stand-by state where the switches SW 1  and SW 2  are turned ON and the switches SW 3 , SW 4   a  and SW 4   b  are turned OFF. 
         [0069]    Next, at time t 2 , since V out &lt;V s &lt;V t , the comparison output signals CPS 1  and CPS 2  of the comparators  23  and  25   a  are both “1” (high level). Therefore, when the clock signal CLK 1  is switched from “0” (low level) to “1” (high level), the clock signal CLK 2  (=CLK 1 ·CPS 1 ) is switched from “0” (low level) to “1” (high level). Also, the clock signal CLK 3  (=CLK 2 ·CPS 2 ) is switched from “0” (low level) to “1” (high level) while the clock signal CLK 4  (=CLK 2 ·/CPS 2 ) remains at “0” (low level). Therefore, the step-up circuit  10 ′ enters a fast step-up state where the switches SW 1 , SW 2  and SW 4   b  are turned OFF and the switches SW 3  and SW 4   a  are turned ON. As a result, the output voltage V out  of the step-up circuit  10 ′ increases to the selection voltage V s . 
         [0070]    At time t 51 , when the output voltage V out  of the step-up circuit  10 ′ crosses the selection voltage VS) the comparison output signal CPS 2  of the comparator  25  is switched from “1” (high level) to “0” (low level), so that the clock signal CLK 3  (=CLK 2 ·CPS 2 ) is switched from “1” (high level) to “0” (low level) while the clock signal CLK 4  (=CLK 2 ·/CPS 2 ) is switched from “0” (low level) to “1” (high level). Therefore, the step-up circuit  10 ′ enters a slow step-up state where the switches SW 1 , SW 2  and SW 4   a  are turned OFF and the switches SW 3  and SW 4   b  are turned ON. In this case, since the load L is relatively small, the output voltage V out  would relatively slowly reach the target voltage V t  at time t 52  before at time t 3 . Between time t 52  to time t 3 , since the response characteristics of the comparator  23  are relatively high, the comparison output signal CPS 1  of the comparator  23  would be quickly reversed. Therefore, step-up states and stand-by states are alternately and quickly repeated to have a small amplitude of the output voltage V out  until time t 3  when the clock signal CLK 1  becomes “0” (low level). 
         [0071]    Next, at time t 3 , when the clock signal CLK 1  is switched from “1” (high level) to “0” (low level), the clock signal CLK 2  is also switched from “1” (high level) to “0” (low level). Therefore, the step-up circuit  10 ′ enters another stand-by state. 
         [0072]    After time t 4 , similar fast and slow step-up/stand-by states to those from time t 2  to time t 3  and a similar stand-by state to that from time t 3  to time t 4  are alternately repeated. 
         [0073]    In the second operation as shown in  FIG. 8 , since the clock signal CLK 2  repeats “0” (low level) and “1” (high level) relatively slowly when the clock signal CLK 1  is “1” (high level), the power consumption would be decreased as compared with the second operation as illustrated in  FIG. 3 . 
         [0074]    A third operation of the power supply apparatus of  FIG. 5  is explained next with reference to  FIG. 9  where the load L to which the output voltage V out  is applied is relatively small and the response characteristics of the comparator  23  are relatively low. 
         [0075]    First, at time t 1 , the clock signal CLK 1  is low so that the clock signal CLK 2  is also low. Therefore, the step-up circuit  10 ′ is in a stand-by state where the switches SW 1  and SW 2  are turned ON and the switches SW 3 , SW 4   a  and SW 4   b  are turned OFF. 
         [0076]    Next, at time t 2 , since V out &lt;V s &lt;V t , the comparison output signals CPS 1  and CPS 2  of the comparators  23  and  25   a  are both “1” (high level). Therefore, when the clock signal CLK 1  is switched from “0” (low level) to “1” (high level), the clock signal CLK 2  (=CLK 1  CPS 1 ) is switched from “0” (low level) to “1” (high level). Also, the clock signal CLK 3  (=CLK 2 ·CPS 2 ) is switched from “0” (low level) to “1” (high level) while the clock signal CLK 4  (=CLK 2 ·/CPS 2 ) remains at “0” (low level). Therefore, the step-up circuit  10 ′ enters a fast step-up state where the switches SW 1 , SW 2  and SW 4   b  are turned OFF and the switches SW 3  and SW 4   a  are turned ON. As a result, the output voltage V out  of the step-up circuit  10 ′ increases to the selection voltage V s . 
         [0077]    At time t 61 , when the output voltage V out  of the step-up circuit  10 ′ crosses the selection voltage V s , the comparison output signal CPS 2  of the comparator  25  is switched from “1” (high level) to “0” (low level), so that the clock signal CLK 3  (=CLK 2 ·CPS 2 ) is switched from “1” (high level) to “0” (low level) while the clock signal CLK 4  (=CLK 2 ·/CPS 2 ) is switched from “0” (low level) to “1” (high level). Therefore, the step-up circuit  10 ′ enters a slow step-up state where the switches SW 1 , SW 2  and SW 4   a  are turned OFF and the switches SW 3  and SW 4   b  are turned ON. In this case, however, although the response characteristics of the comparator  23  are relatively low, since the load L is relatively small, the output voltage V out  of the step-up circuit  10 ′ approaches the target voltage V t . Thus, the output voltage V out  would relatively slowly reach the target voltage V t  at time t 62  before at time t 3 . At time t 63 , the step-up circuit  10 ′ enters another stand-by state which continues for just a small period. Therefore, the comparison output signal CPS 1  of the comparator  23  would be also slowly reversed with small period stand-by states. Therefore, fast and slow step-up states and stand-by states are alternately and slowly repeated to have a small amplitude of the output voltage V out  of the step-up circuit  10 ′ until time t 3  when the clock signal CLK 1  becomes “0” (low level). 
         [0078]    Next, at time t 3 , when the clock signal CLK 1  is switched from “1” (high level) to “0” (low level), the clock signal CLK 2  is also switched from “1” (high level) to “0” (low level). Therefore, the step-up circuit  10 ′ enters another stand-by state. 
         [0079]    After time t 4 , similar fast and slow step-up/stand-by states to those from time t 2  to time t 3  and a similar stand-by state to that from time t 3  to time t 4  are alternately repeated. 
         [0080]    In the third operation as shown in  FIG. 9 , the output voltage V out  of the step-up circuit is not so small as to generate small overshoots, which would remarkably decrease the output voltage V out  of the step-up circuit  10 . Thus, since the output voltage V out  hardly exceeds a rated value, the elements within the power supply apparatus of  FIG. 5  would not deteriorate. Simultaneously, the ripple of the output voltage V out  would be decreased. 
         [0081]    Also, in the third operation as shown in  FIG. 9 , since the clock signal CLK 2  repeats “0” (low level) and “1” (high level) relatively slowly when the clock signal CLK 1  is “1” (high level), the power consumption would be decreased as compared with the second operation as illustrated in  FIG. 3 . 
         [0082]    Further, in the operation as shown in  FIG. 9 , assume that the delay time of the comparator  23  is 1 μsec. In this case, the overshoot value is 0.1V/μ sec. Contrary to this, in the prior art third operation as shown in  FIG. 4 , the over shoot value is 0.5V/μ sec under the same condition that the delay time of the comparator  23  is 1 μsec. Thus, the overshoot value can be decreased. 
         [0083]    In  FIG. 5 , the comparators  23  and  25  can be hysteresis-type comparators.