Abstract:
A local nonlinear feedback loop (LNFL) technique and a sigma-delta modulator (SDM) for promoting highly stable oversampling using the LNFL technique. Not only can gain mismatch of the sigma-delta modulator be minimized, but the overload of the later stage sigma-delta modulator can also be resolved without sacrificing the signal noise ratios (SNR) of the overall system. Moreover, using the local nonlinear feedback loop technique of this invention attenuates the voltage signal of the sigma-delta modulator, therefore decreasing the power consumption of the overall sigma-delta modulator system.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a sigma-delta modulator (SDM), particularly to a highly stabilized sigma-delta modulator using a LNFL (Local Nonlinear Feedback Loop) technique for resolving overload problems. 
     2. Description of the Related Art 
     A variety of sigma-delta modulators (SDMs), such as a so-called oversampled SDM, are used for fabricating analog-to-digital converters (ADC). The ADC comprising an oversampled SDM mainly employs oversampling and noise shaping techniques of the SDM for reducing quantization noise and shaping it to a higher frequency. Then the high frequency noise is filtered out with a decimator and a digital lowpass filter to enhance the signal-to-noise ratio (SNR) and to obtain high resolution. Further, the SDM has the following advantages: simple construction, no need for an additional trimming circuit, and high tolerance of variation in circuit components. Consequently, the SDM is used widely in situations where SNR needs to be enhanced. 
     The architecture of SDMs falls into two categories: classical and cascaded SDMs. 
     FIGS. 1A-1C illustrate the architecture of a classical SDM. In the Figures, the order of the noise shaping factor of the SDM is determined by the number of the cascaded integrators in the SDM. FIG. 1A illustrates a one-ordered SDM with an integrator Z −1    10 ; FIG. 1B illustrates a two-ordered SDM with two integrators  11  and  12  connected in serial; and FIG. 1C illustrates a multi-ordered (at least three orders) SDM with plural integrators  13 ,  14 , and  15 . 
     Though the integrator with high-order noise shaping function can provide a higher resolution, the SDM becomes unstable when the number of integrators (orders) exceeds two. This is due to signal overload accumulated in the integrator in the later stage. 
     The architecture of the cascaded SDM realizes high-ordered noise shaping with multiple low-ordered SDMs. Multi-stage noise shaping (MASH) architecture of this type is shown in FIGS. 2A-2B. In FIG. 2A, high-ordered noise shaping is realized with two cascaded low-ordered SDMs  20  and  21 ; whereas in FIG. 2B, high-ordered noise shaping is realized with three cascaded low-ordered SDMs  22 ,  23 , and  24 . However, cascaded SDMs are still troubled with overloads. 
     The output SNR will degrade due to restraints imposed by non-ideal conditions (values) of the analog components. This is due to the gain mismatch effect of the cascaded SDM. An alternative solution is to provide an improved cascaded SDM, that is, the second-ordered SDM cascaded by a first-ordered SDM (Second-Ordered First-Ordered Cascaded architecture; SOFOC), as shown in FIG.  3 . 
     The architecture shown in FIG. 3 basically converts a MASH architecture cascaded with three-stage first ordered SDMs  22 ,  23 , and  24  as shown in FIG. 2B, into a MASH architecture having second-ordered SDM  30  in the preceding stage and a first-ordered SDM  32  in the succeeding stage to realize a cascaded SDM. The input of the SDM of the stage  32  receives a quantization noise −Q 1  of the SDM of the preceding stage  30 . The conversion function is as follows: 
     
       
         Y 1 =X+(1−Z −1 ) 2 Q 1   
       
     
     
       
         Y 2 =−Q 1 +(1−Z −1 ) Q 2    
       
     
     
       
         Y=Y 1 +(1−Z −1 ) 2  Y 2 =X+(1−Z −1 ) 3 Q 2   
       
     
     where Y 1  is a first-stage digital output, and Y 2  is a second-stage digital output; −Q 1  is a first-stage quantization noise, −Q 2  (not shown in FIG. 3) is a second-stage quantization noise, Y is an overall digital output signal, and X is an analog input signal. 
     Refer to FIG. 2B for a comparison with the MASH architecture. When the quantization noise of the preceding stage cannot be fully eliminated due to a gain mismatch effect, the overall digital output signal of the MASH architecture is as follows:                Y        (   MASH   )       =                  α                   Y   1       +       β        (     1   -     Z     -   1         )            Y   2       +         γ        (     1   -     Z     -   1         )       2          Y   3                     =                  α                 X     +           (     α   -   β     )          (     1   -     Z     -   1         )          Q   1       +       (     β   -   γ     )            (     1   -     Z     -   1         )     2          Q   2       +     _                                      γ        (     1   -     Z     -   1         )       3          Q   3       _                                  
     where Y 3  is a third-stage digital output, and −Q 3  is a third-stage quantization noise; and α≠β≠γ due to gain mismatch, whereas α=β=γ when the gains of the preceding and succeeding stages match. 
     In the SOFOC architecture, when the quantization noise of the preceding stage cannot be fully eliminated due to gain mismatch effect, the overall digital output signal of the SOFOC architecture is as follows:                Y        (   SOFOC   )       =       α                   Y   1       +         β        (     1   -     Z     -   1         )       2          Y   2                     =       α                 X     +           (     α   -   β     )            (     1   -     Z     -   1         )     2          Q   1       +         β        (     1   -     Z     -   1         )       3          Q   2         _                                    
     If in gain match, then α=α=γ; and assume α=1, then Y(SOFOC)=Y, being the optimal status for analog components. Under the gain mismatch effect, after the processing of the second-order noise shaping factor, that is, (1−Z −1 ) 2 , the leaking noise generated in an SOFOC architecture becomes smaller than the first-order leaking noise generated in a MASH architecture. Therefore, the SDM in the SOFOC architecture demonstrates better resistance to the sensitivity (gain mismatch) of analog components. That is to say, the performance of the SDM in the SOFOC has lower dependency upon the idealization of analog components. 
     However, since the preceding stage of an SOFOC SDM is a second-ordered SDM rather than a highly stable first-ordered SDM, and the input of the succeeding stage of the SDM is the quantized noise of the preceding stage of the SDM, the cascaded second stage integrator still suffer from overload due to significant input signals. 
     It is known from the above that an oversampled SDM, both of a classical and cascaded architecture, is subject to instability. Therefore, it becomes essential to enhance the stabilization of the oversampled SDM. 
     The following three techniques have been proposed to resolve overload problems: (1) limiting an input dynamic range; (2) inserting a gain scaling means into an SDM, for reducing linear-proportionally of the dynamic range of the system signal as shown in FIG. 4; and (3) using automatic gain control (AGC), for linear-proportionally adjusting of the dynamic range of the system signal with the input signal magnitude. 
     The aforementioned three conventional techniques all linearly reduce the operating signal swing range of the modulators to protect the integrator from instability due to significant signal accumulation. But a limiting input dynamic range technique will limit the applicable range of the modulator; whereas the AGC technique or gain scaling insertion technique will reduce the overall system SNR, because the output end of the system has to compensate the previous gain scaling (or signal reduction). 
     In the SOFOC architecture of FIG. 4, a signal gain scaling apparatus  40  is further arranged between a second-ordered SDM  30  and a first-order SDM  32  for linearly reducing the amplitude of the error quantization signal −Q 1 ; and a linear gain recovering device  42  is arranged at the output of the first-order SDM  32 . The conversion function is represented as: 
     
       
         Y 1 =X+(1−Z −1 ) 2 Q 1   
       
     
     
       
         Y 2 =−jQ 1 +(1−Z −1 ) Q 2   
       
     
     
       
         Y=Y 1 +1/j (1−Z −1 ) 2  Y 2 =X+1/j (1−Z −1 ) 3 Q 2   
       
     
     where j&lt;1. It is known from the architecture of FIG. 4 that the input signal −jQ 1  of the second-stage modulation unit becomes smaller, because of the linear signal scaling apparatus  40 , to prevent the second-stage modulation unit from integrator overload. Thus, the quantized noise of the overall output function is compensated by the gain recovering device  42 , and is amplified, thus becoming the greater quantized noise 1/j (1−Z −1 ) 3 Q 2 ). Therefore, the overall SNR is reduced. 
     SUMMARY OF THE INVENTION 
     Accordingly, this invention proposes a local non-linear feedback loop (LNFL) technique to enable high stability of the SDM. This invention adopts SDM by the LNFL architecture to minimize gain mismatch and eliminate overload without reducing overall system SNR. Moreover, the overall system voltage signal scaling can be realized by using the LNFL technique of this invention; therefore, the overall system power consumption of the SDM can be reduced. 
     To realize the above object, the LNFL technique for SDMs according this invention basically comprises selectively arranging input-signal adjusting devices in front of respective input ends of the various stage integrator modulation units in the SDM, for controlling respectively the magnitude of the input signal of the various stage integrator modulation units. When the input signal of the coupled integrator modulation units is greater than a first specified value, then its corresponding input signal adjustment device will subtract a second specified value from the input signal, then output it to the coupled integrator modulation unit, and further add the second specified value to the output signal of the coupled integrator modulation unit. When the input signal of the coupled integrator modulation units is smaller than the first specified value, then the input signal adjustment device will add the second specified value to the input signal, further output it to the coupled integrator modulation unit, and subtract the second specified value from the output signal of the integrator modulation unit. 
     Further, to realize a highly stable SDM, this invention provides an SDM by the LNFL comprising: plural modulation units connected in series S 1 -S n , for generating plural modulated signals Y 1 -Y n  and plural quantized error signals −Q 1 -−Q n , wherein the input end of the modulation unit S 1  is coupled to an analog input signal X, and the input ends of the other modulation units S 2 -S n  are coupled to the quantized error signals −Q 1 -−Q n−1 , respectively; a level adjustment unit M j  selectively arranged at the input end of the modulation unit S j+1 , determining whether the addition (or subtraction) of a specified value Δ will be performed on the quantized error signal −Q 1  in accordance with the signal value of the quantized error signal −Q j  of the modulation unit S j , and performing in accordance with the determined result a subtraction (or an addition) of the specified value Δ from (to) the modulated signal Y j+1  of the modulation unit S j+1 , where 1≦j≦n−1 and at least one of the level adjustment units is arranged in the SDM; and an adder-synthesizer unit coupled to the plural modulation signals Y 1 -Y n  generated by the plural modulation units S 1 -S n  for generating an output signal Y of the SDM. 
     The LNFL technique can also be applied to improve the stability of high-ordered classical SDMs. This invention provides an SDM architecture applicable to classical local non-linear feedback techniques comprising: a modulation unit S for generating a modulation signal Y and a quantized error signal −Q, respectively; a level adjustment unit M for receiving an analog input signal X, determining whether to perform an addition to (or a subtraction from) the signal X of a specified amount Δ in accordance with the magnitude of the analog input signal X, for limiting the range of the analog input signal X and outputting the result to the modulation unit S; and a synthesis operator for receiving the signal Y and a compensation signal to obtain an output signal Y′ for the SDM. Therein, the compensation signal is outputted by the level adjustment unit M, the signal amplitude is the same as the specified amount Δ. 
     Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned objects, features and advantages of this invention will become apparent by referring to the following detailed description of a preferred embodiment with reference to the accompanying drawings, wherein: 
     FIGS. 1A-1C illustrate the architecture of a conventional SDM; 
     FIGS. 2A-2B illustrate the architecture of a conventional cascaded SDM; 
     FIG. 3 illustrates a conventional SDM with SOFOC architecture; 
     FIG. 4 illustrates an SDM architecture, with signal gain scaling means, for reducing linear-proportionally of the dynamic range of the system signal in a conventional architecture; 
     FIG. 5 illustrates an SOFOC by the LNFL architecture; 
     FIGS. 6A-6D illustrate a comparison of stabilization between the conventional SOFOC architecture and the SOFOC by the LNFL architecture of this invention; 
     FIG. 7 illustrates a performance chart of the SNR of the conventional SOFOC architecture and the SOFOC by the LNFL architecture of this invention; 
     FIG. 8 illustrates a performance chart of the SOFOC by the LNFL architecture of this invention; when the analog components incurred with an inaccuracy (+10% mismatch); 
     FIG. 9 illustrates a performance chart of the SOFOC by the LNFL architecture of this invention; when the analog components incurred with an inaccuracy (−10% mismatch); 
     FIG. 10 illustrates the LNFL technique integrated with a conventional SDM; 
     FIG. 11 illustrates a circuit diagram of an SDM applying SOFOC by the LNFL; 
     FIG. 12 illustrates a circuit diagram of a conventional SDM applying the “LNFL” technique; 
     FIG. 13 illustrates the conventional architecture of an SOFOC by “multi-bit quantization operation”; 
     FIG. 14 illustrates the conventional architecture of an SOFOC by “internal linear feedback loop”; and 
     FIGS. 15A-15D illustrate a comparison chart of the stability between the SOFOC by the LNFL architecture. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     For convenience and simplicity, the LNFL technique for improving stability is described as applied to SOFOC architecture only. However, the technique could be applied to other architectures, for example architectures having various order levels less than or greater than the SOFOC architecture disclosed herein. In the following, refer to FIG. 5, a diagram illustrating an architecture of the SOFOC by the LNFL. 
     First, referring to FIG. 5, the principle of SOFOC by the LNFL is briefly described as follows. 
     In a cascaded (or conventional) SDM, a level adjustment device (VADJ), in front of the input end of the second-stage modulation device S 2 , is used for controlling the magnitude of the input signal. 
     When the output −Q 1  of the first-stage modulation unit S 1  is greater than {fraction (Δ/2+L )}, the output of the level adjustment device is −Q 1 −Δ; then the digital quantity of +Δ is added to the output of the second-stage modulation unit S 2 . When the output −Q 1  of the first-stage modulation unit S 1  is smaller than {fraction (Δ/2+L )}, the output of the level adjustment device is −Q 1 +Δ; then the digital quantity of −Δ is added to the output of the second-stage modulation unit S 2  Where the specific value of Δ equals the analog quantity corresponding to the value of one bit level of a digital value. 
     In accordance with the aforementioned principle, the dynamic range of the input signal of the second-stage modulation unit S 2  is adjusted to a range within |{fraction (Δ/2+L )}|, so the overload of integrators of the second-stage modulation unit can be prevented. Likewise, if the level adjustment device VADJ is added in front of various stage modulation units, then the overload of integrators of the various stage modulation units can be prevented, thus, effectively maintain the stability of the SDM. 
     Referring to FIG. 5, a highly stable SDM improved with the application of the LNFL technique of this embodiment comprises the following units: two modulation units S 1 -S 2  connected in series, for generating plural modulation signals Y 1  to Y 2  and two quantized error signals −Q 1  and −Q 2 ; a level adjustment device VADJ, arranged between the modulation units S 1  and S 2 , for adjusting the dynamic range of the quantized error signal −Q 1  and outputting a compensative signal (quantity); where the input end of the modulation units S 1  is coupled to the input of an analog signal X, and the input end of the modulation units S 2  is coupled to the quantized error signal −Q 1  through the level adjustment device VADJ; and an adder-synthesizer unit  70 , wherein the modulation signal Y 2  generated by the modulation unit S 2  and the compensative signal ±Δ or  0  are accumulated through the adder  68 , and then outputted to the adder-synthesizer unit  70  after being processed by the two-stage differentiators D 1  and D 2 , and then synthesized into a sigma-delta modulation output signal Y with the modulated signal Y 1  generated by the modulation unit S 1.    
     The modulation unit S 1  includes a second-order integration module  50  formed with two integration units, each of the integration units having a synthesizer (adder  501  or  503 ) connected in series with an integrator  502  or  503 ; a one-bit quantizer  52  for coupling the output signal intl of the two-stage integration module to quantize the signal intl and obtain the modulated signal Y 1 ; a synthesis operator  54  for obtaining the difference between the output signal intl of the second-order SDM and the modulated signal Y 1  as the quantized error signal −Q 1 (=int 1 −Y 1 ); and a delay unit  56  connected in serial to a one-bit digital-to-analog converter (DAC)  58  for forming a feedback loop path to feed back the modulated signals Y 1  to the adders ( 501  and  503 ) of the two integrator units  502  and  504 , respectively. 
     The modulation unit S 2  includes a synthesizer (adder)  61  connected in serial to an integrator  62  for forming a first-order integration unit; a one-bit quantizer  63  for coupling to the output signal int 2  of the first-order integration module for quantizing the signal int 2 , and then outputting the modulated signal Y 2 ; a synthesis operator (not shown) for obtaining the difference between the output signal int 2  of the first-order integration unit and the modulated signal Y 2  as the quantized error signal −Q 2 ; and a delay unit  64  connected in serial to a one-bit digital-to-analog converter  65  for forming a respective feedback loop path to feed back the modulated signals Y 2  to the synthesizer  61  of the first-order integrator unit. 
     In the SDM of SOFOC by the LNFL in compliance with the feedback principle, when the quantized error output −Q 1  of the first-stage modulation unit S 1  is greater than {fraction (Δ/2+L )}, the output of the level adjustment device (VADJ) is −Q 1 −Δ, then a digital quantity +Δ is compensated to the output signal Y 2  of the second-stage modulation unit S 2 ; or when the quantized error output −Q 1  of the first-stage modulation unit S 1  is smaller than {fraction (Δ/2+L )}, the output of the level adjustment device (VADJ) is −Q 1 +Δ, then a digital quantity −Δ is compensated to the output signal Y 2  of the second-stage modulation unit S 2 , and when −Q 1  is (−{fraction (Δ/2+L )})≦(−Q 1 )≦(+{fraction (Δ/2+L )}), then the output of the level adjustment device (VADJ) is −Q 1 ; while the quantized output of the second-stage modulation unit S 2  remains Y 2 . 
     The actual operation of the conversion function is represented as follows:                Y   1     =     X   +         (     1   -     Z     -   1         )     2          Q   1                       Y   2     =       (       -     Q   1       ±   Δ     )     +       (     1   -     Z     -   1         )          Q   2                     Y   =       Y   1     +         (     1   -     Z     -   1         )     2          (       Y   2     ∓   Δ     )                     =     X   +         (     1   -     Z     -   1         )     2          Q   1       -           (     1   -     Z     -   1         )     2          Q   1       ±         (     1   -     Z     -   1         )     2        Δ       +                                 (     1   -     Z     -   1         )     3          Q   2       ±         (     1   -     Z     -   1         )     2        Δ                     =       X   +         (     1   -     Z     -   1         )     3          Q   2         _                                  
     As can be seen from above, the output conversion function of the SOFOC by the LNFL architecture of this invention remain unaffected, the same as that of conventional SDM in SOFOC architecture. 
     FIG. 6 illustrates a comparison of stability between the conventional SOFOC architecture (FIG. 3) and the SOFOC by the LNFL architecture (FIG. 5) of this invention; where (A) and (B) are simulation results of the conventional SOFOC architecture; while (C) and (D) are simulated results of SOFOC by the LNFL. 
     As can be seen from FIGS.  6 (A) and  6 (C), the SOFOC by the LNFL architecture of this invention restricts the quantized noise (−Q 1 ) inputted to the second-stage modulation unit S 2  to a range between −1 and +1 (in this case Δ=2) using the level adjustment device VADJ, whereas conventional SOFOC architecture does not have such a process. 
     As can be seen from FIGS.  6 (B) and  6 (D), the second-stage modulation unit  32  of conventional SOFOC architecture demonstrates significantly greater dynamic range than that of the SOFOC by the LNFL architecture of this invention. Therefore, the SOFOC by the LNFL architecture of this invention demonstrates a greater stability than the conventional SOFOC architecture. 
     FIG. 7 illustrates for a performance chart of the SNR of the conventional SOFOC architecture and the SOFOC by the LNFL architecture of this invention. Evidently, the SOFOC by the LNFL architecture of this invention has better performance than the conventional SOFOC architecture. This is because the transfer function of the SDMs performance is never affected by the nonlinear operation of the LNFL technique, and the quantization noise of the last-stage SDM in SOFOC architecture is further suppressed simultaneously. 
     Further, as seen in FIGS. 8 and 9, performance charts of the SOFOC by the LNFL architecture of this invention when the analog components incurred with an inaccuracy (±10% mismatch) are shown. The inaccuracy of the components (such as switches for controlling the signal scaling) in the feedback loop have almost no effect on the stability control of the overall system, since the quantized noise of the second-stage modulation unit is controlled to be within the range between −2V and +2V, and the stability and the SNR are not affected. Consequently, the LNFL technique is resistant to errors or disturbance generated from the inaccuracy of the components. 
     The LNFL technique can also be applied for improving stability of conventional high-order SDMs; and this invention also provides an LNFL technique applicable to a conventional SDM, as shown in FIG. 10, where a level adjustment device VADJ is added to the input end of the N th -order SDM  100  in accordance with the LNFL technique of this invention, for adjusting the magnitude of the input signal X. 
     When the input signal X is greater (or smaller) than a specific value such as {fraction (Δ/2+L )}, then signal X is subtracted from (or added to) Δ, for inputting X−Δ (or X+Δ) to the N th -order SDM  100 ; and the compensative amount +Δ (or −Δ) is added to the output signal Y of the N th -order SDM  100  for obtaining the output Y′ of the SDM. The conversion function is represented as follows:              Y   =     X   +         (     1   -     Z     -   1         )     N        Q                     Y   ′     =       (     X   -   Δ     )     +         (     1   -     Z     -   1         )     N        Q     +   Δ                 =     X   +         (     1   -     Z     -   1         )     N        Q                                    
     where N≧1, and errors due to inaccuracy of components can be prevented without affecting the SNR or resulting in overload of the integrators. 
     Moreover, in a new architecture applying the local nonlinear feedback loop (LNFL) technique, the signal at the output end is the original quantized output signal plus or minus a compensative amount (digital signal) to form a multi-bit level signal of the SDM. Though the “LNFL” technique of this invention, the “multi-bit quantization” technique of the conventional, and the “internal linear feedback loop” technique of the conventional art is somewhat similar, the relevant factors for the prior art and this invention are considerably different, and the performance of the techniques of the conventional art is not as robust as that of the technique provided with this invention. 
     The “multi-bit quantization” technique of the prior art basically adopts a multi-bit quantizer for replacing the original single-bit quantizer in the SDM architecture, as shown in FIG.  13 . The “internal linear feedback loop” technique of prior art, as shown in FIG. 14, places an overload detector (OLD) at the output end of the integrators of the SDM for detecting whether integrators are overloaded, then further determines whether the local feedback loop is activated to attenuate the input signal swing in the integrator, or if the internal switch of the integrator is turned off to prevent instability due to excessive signal accumulation in the integrator. 
     The “multi-bit quantization” technique and “internal linear feedback loop” technique attempt to resolve overload problems. Although they desire to reduce the overload problem of the SDM as does the LNFL technique, the SNR of the overall system will not be reduced in the compensation. In addition, the control of the above two techniques of conventional art is based upon whether the signal magnitude at the input end of the quantizer of the SDM (that is, the output signal of the integrator) is overloaded. 
     In contrast, the principle of the LNFL technique of this invention takes the control of the signal magnitude at the input end of the SDM (that is, the input signal of the integrator) into consideration; therefore, maintaining the input signal of the integrator within a particular dynamic range, regardless of the overload at the input end of the integrator in the SDM. Therefore, the SDM employing the LNFL technique of this invention is less likely to be overloaded. 
     In the SOFOC architecture for example, the results of a comparative simulation of stability employing the LNFL (refer to FIG. 5) and multi-bit quantization (refer to FIG. 13) respectively are shown in FIG.  15 . 
     FIG. 15 illustrates a comparison chart of the stability between the SOFOC by “multi-bit quantization” architecture (FIG. 13) and the SOFOC by the LNFL architecture of this invention (FIG.  5 ); where (A) and (B) show the simulated results of the SOFOC by the LNFL architecture; and (C) and (D) illustrate the simulated results of the multi-bit quantization. 
     As can be seen from FIGS.  15 (A) and  15 (C), the SOFOC by the LNFL architecture restricts the quantized noise −Q 1  inputted to second-stage modulation unit within the range of −1 to +1 (Δ=2) with the control of the level adjustment device VADJ; such processing is not done in the multi-bit quantization of the SOFOC architecture. 
     As can be seen from FIGS.  15 (B) and  15 (D), the dynamic range of the signal is significantly smaller in the SOFOC by the LNFL architecture of this invention than in the second-stage modulation unit of the SOFOC by multi-bit quantization architecture. Therefore, the SOFOC by the LNFL architecture is better than the SOFOC by multi-bit quantization architecture in terms of stability. 
     Referring to FIG. 11, the circuit configuration of the SOFOC by the LNFL of this invention comprises the following units: 
     (1) Plural modulation units S 1 -S n  connected in series for generating plural modulated signals Y 1 -Y n  and plural quantized error signals −Q 1 -−Q n . For convenience, only two modulation units (S 1 , S 2 ) connected in series are shown in FIG. 11, wherein the input end of the modulation unit S 1  is coupled to the input of an analog signal X, and the input of the modulation unit S 2  is coupled to the quantized error signal −Q 1  outputted by the first modulation unit S 1 , respectively. 
     (2) A level adjustment unit M 2  being selectively arranged at the input end of the modulation unit S 2 . 
     (3) An adder-synthesizer unit, coupled to plural modulated signals Y 1 -Y 2  of the two modulation units S 1 -S 2 , for generating an output signal Y of the SDM. 
     Herein, the modulation unit S 1  includes: a two-order integration module, formed by two sets of integrators A 11  and A 12 ) connected in series, for outputting the quantized error signal −Q 1 ; a quantizer, formed by a comparator compl, for quantizing the quantized error signal −Q 1  and outputting the modulation signal Y 1 ; a feedback capacitor switch CS 1 , formed with the switches S 1 , S 2 , φ, {overscore (φ)} and a capacitor C d1  as shown in FIG. 11, where its output is coupled to the input of the two-order integration module; and a switch control unit SC 1  for controlling the conduction (on/off) of the switch S 1  or S 2  in accordance with the magnitude of the modulated signal Y 1 , and for enabling the coupling of the voltage signal Vref or 0 to the input ends of each of the integrators A 11  and A 12  of the two-order integration module. 
     The modulation unit S 2  comprises a one-order integrator module, formed with an integrator A 21 , for outputting a quantized error signal −Q 2  (not shown); a quantizer, formed with a comparator comp 2 , for quantizing the quantized error signal −Q 2  and outputting the modulated signal Y 2 ; a feedback capacitor switch device CS 2 , formed with switches S 3 , S 4 , S 5 , S 6 , φ, {overscore (φ)} and a capacitor C d2  as shown in FIG. 11, with its output coupled with the input of the one-order integrator module; and a switch control unit SC 2 . 
     When the output quantized error signal −Q 1  of the modulation unit S 1  is detected by the level adjustment device M 2  to be smaller than −{fraction (Δ/2+L )} and when the modulation signal Y 1  is at a low voltage level L, the level adjustment unit M 2 , in conjunction with the switch control unit SC 2 , turns on the switch S 3  for inputting the voltage signal 2Vref to the feedback capacitor switch device CS 2 , thereby subtracting the specific amount Δ from the modulation signal Y 2  of the modulation unit S 2 . In addition, when the output quantized error signal −Q 1  of the modulation unit S 1  is detected by the level adjustment device M 2  to be smaller than the first value −{fraction (Δ/2+L )}, and when the modulation signal Y 1  is at a high voltage level H, the level adjustment unit M 2 , in conjunction with the switch control unit SC 2 , turns on the switch S 4  for outputting the voltage signal Vref to the feedback capacitor switch device CS 2 , thereby substracting the specific amount Δ from the modulation signal Y 2  of the modulation unit S 2 . 
     When the output quantized error signal −Q 1  of the modulation unit S 1  is detected by the level adjustment device M 2  to be greater than {fraction (Δ/2+L )}, and when the modulation signal Y 1  is at the low voltage level L, the level adjustment unit M 2 , in conjunction with switch control unit SC 2 , turns on the switch S 5  for inputting the voltage signal  0  to the feedback capacitor switch device CS 2 , thereby adding the specific amount Δ to the modulation signal Y 2  of the modulation unit S 2 . In addition, when the output quantized error signal −Q 1  of the modulation unit S 1  is detected by the level adjustment device M 2  to be greater than {fraction (Δ/2+L )}, and when the modulation signal Y 1  is at the high voltage level H, the level adjustment unit M 2 , in conjunction with switch control unit SC 2 , turns on the switch S 6  for inputting the voltage signal −Vref to the feedback capacitor switch device CS 2 , thereby adding the specific amount Δ to the modulation signal Y 2  of the modulation unit S 2 . 
     When the output quantized error signal −Q 1  of the modulation unit S 1  is detected by the level adjustment device M 2  to be between {fraction (Δ/2+L )} and −{fraction (Δ/2+L )}, and when the modulation signal Y 1  is at the low voltage level L, the level adjustment unit M 2 , in conjunction with switch control unit SC 2 , turns on the switch S 4  for inputting the voltage signal Vref to the feedback capacitor switch device CS 2 , thereby maintaining the modulation signal Y 2  of the modulation unit S 2  unchanged. 
     In addition, when the output quantized error signal −Q 1  of the modulation unit S 1  is detected by the level adjustment device M 2  to be between {fraction (Δ/2+L )} and −{fraction (Δ/2+L )}, and when the modulation signal Y 1  is at the high voltage level H, the level adjustment unit M 2 , in combination with switch control unit SC 2 , turns on the switch S 5  for inputting the voltage signal  0  to the feedback capacitor switch device CS 2 , thereby maintaining the modulation signal Y 2  of the modulation unit S 2  unchanged. 
     In the SOFOC SDM, the input end of the modulation unit S 1  is further coupled with a switch capacitor device CSD 1 , formed with four sets of switches (two pairs of φ and {overscore (φ)} each) and a capacitor C S1 ; the input end of the modulation unit S 2  is also coupled with an electrical switch capacitor device CSD 2 , formed with four sets of switches (two pairs of φ and {overscore (φ)} each) and a capacitor C S2 , as shown in FIG.  11 . In the SDM, a middle device formed with switches φ, {overscore (φ)} and a capacitor C temp  is coupled between the two integrators A 11  and A 12  of the two-order integration module. The switches φ and {overscore (φ)} are all periodically turned on alternately. 
     The LNFL technique can also be applied to high-order SDM with classical architecture for improving stability; this invention also provides a classical SDM implemented in conjunction with the LNFL technique, with its circuit diagram being shown in FIG.  12 . Referring to FIG. 12, the circuit configuration of the SDM with classical architecture comprises the following units: 
     (1) a modulation unit S, for generating a modulation signal Y and a quantized error signal −Q, respectively. 
     (2) a level adjustment unit M, for receiving an analog input signal X and selecting one signal from the voltage signals 2Vref, Vref,  0 , and −Vref in accordance with the magnitude of the modulation signal Y to couple the selected signal to the input of the modulation unit S, and generating a compensation signal in accordance with the result. 
     (3) a synthesizer for receiving the modulation signal Y and the compensation signal and obtaining an output signal Y′ for the SDM, wherein the level adjustment unit M outputs the compensation signal, when the signal magnitude equals a specific amount Δ, −Δ or 0. 
     The modulation unit S comprises: a k-order integration module formed with plural integrators connected in series (however, for convenience, only two integrators B 1 , B 2  are shown in FIG.  12 ); a quantizer, formed with a comparator comp, for coupling the output signal −Q of the integration module, and quantizing and outputting the modulated signal Y; and a first feedback capacitor switch device CS f , formed with switches S 3 , S 4 , S 5 , S 6 , φ, {overscore (φ)} and a capacitor C d , with its output coupled with the input of the k-order integration module, its input selecting one signal of the voltage signals 2Vref, Vref,  0 , and −Vref through the level adjustment unit M. 
     The SDM further includes a switch control unit SWC, for selecting a voltage signal of Vref or  0  through a second feedback capacitor switch device, coupled with the input end of the second stage through the k th -stage of the k integrators. A second capacitor switch device CS S  is formed with switches S 1 , S 2 , φ, {overscore (φ)} and a capacitor C dd , as shown in FIG.  12 . 
     The operation of switches S 3 , S 4 , S 5  and S 6  is specified as follows. 
     When the input signal X of the modulation unit S is detected by the level adjustment unit M to be smaller than −{fraction (Δ/2+L )}, and when the modulation signal Y is at the low voltage level L, the level adjustment unit M, in combination with switch control unit SWC, turns on the switch S 3  for inputting the voltage signal 2Vref to the feedback capacitor switch device CS f , thereby subtracting the specific amount Δ from the modulation signal Y of the modulation unit S. In addition, when the input signal X of the modulation unit S is detected by the level adjustment device M to be smaller than the first value −{fraction (Δ/2+L )}, and when the modulation signal Y is at the high voltage level H, the level adjustment unit M, in combination with switch control unit SWC, turns on the switch S 4  for inputting the voltage signal Vref to the feedback capacitor switch device CS f , thereby subtracting the specific amount Δ from the modulation signal Y of the modulation unit S. 
     When the input signal X of the modulation unit S is detected by the level adjustment device M to be greater than {fraction (Δ/2+L )}, and when the modulation signal Y is at the low voltage level L, the level adjustment unit M, in combination with switch control unit SWC, turns on the switch S 5  for inputting the voltage signal  0  to the feedback capacitor switch device CS f , thereby adding the specific amount Δ to the modulation signal Y of the modulation unit S 2 , In addition, when the input signal X of the modulation unit S is detected by the level adjustment device M to be greater than {fraction (Δ/2+L )}, and when the modulation signal Y is at the high voltage level H, the level adjustment unit M, in combination with switch control unit SWC, turns on the switch S 6  for inputting the voltage signal −Vref to the feedback capacitor switch device CS f , thereby adding the specific amount Δ to the modulation signal Y of the modulation unit S. 
     When the input signal X of the modulation unit S is detected by the level adjustment device M to be between −{fraction (Δ/2+L )} and {fraction (Δ/2+L )}, and when the modulation signal Y 1  is at the low voltage level L, the level adjustment unit M 2 , in combination with switch control unit SWC, turns on the switch S 4  for inputting the voltage signal Vref to the feedback capacitor switch device CS f , thereby maintaining the modulation signal Y 2  of the modulation unit S 2  unchanged. In addition, when the input signal X of the modulation unit S is detected by the level adjustment device M to be between {fraction (Δ/2+L )} and −{fraction (Δ/2+L )}, and when the modulation signal Y is at the high voltage level H, the level adjustment unit M, in combination with switch control unit SWC, turns on the switch S 5 , for inputting the voltage signal  0  to the feedback capacitor switch device CS f  thereby maintaining the modulation signal Y of the modulation unit S unchanged. 
     Also, when the modulation signal Y is at the high voltage level H, the switch S 2  must be turned on, and when the modulation signal Y is at the high voltage level H, the switch S 1  must be turned on. In the conventional SDM, the input end of the modulation unit S is coupled with an electrical switch capacitor device formed with four sets of switches (two pairs of φ and {overscore (φ)} each) and a capacitor C S ; the input end of the modulation unit S is also coupled with an electrical switch capacitor device formed with four sets of switches (two pairs of φ and {overscore (φ)} each) and a capacitor C S3 , as shown in FIG.  12 . In the SDM, a middle device formed with switches φ, {overscore (φ)} and a capacitor C temp  is coupled between any two integrators of the k-order integration module. The switches φ and {overscore (φ)} are all periodically inter-conductive. 
     As can be seen from above, the LNFL technique can be applied to every stage of the classical SDMs or the cascaded SDMs. The extra cost of applying the LNFL technique in terms of hardware circuit configuration is limited to a level adjustment device (such as a multiplexer) selectively arranged at the input end of the modulation unit in the circuit framework. 
     The innovation of our circuit design using a level adjustment device lies in moving the operating framework of the voltage selector (or the multiplexer) to the feedback loop of the stage SDM for stabilization control; and the level adjustment device being formed with an extra digital switch control (Sw Ctrl), the swing detector, and the local feedback compensative loop, as shown in FIG.  11 . Moreover, the principle of this new technique for improving levels of reference voltage by increasing the feedback capacitance (C d2  of FIG. 11) can be achieved through switch capacitor CS 2 . That is, the dynamic range of the SDM is restricted to prevent overload of later stages of the SDMs. The swing detector is for monitoring whether the dynamic range is exceeded (|{fraction (Δ/2+L )}, Δ: a multiple of digital bit level); whereas the local feedback compensative loop uses compensative operations at the digital ends for preventing additional error in the previous variation; and the digital switch controller is for controlling the logical timing if the switch controller on the feedback loop. 
     Although the present invention has been described in its preferred embodiment, it is not intended to limit the invention to the precise embodiment disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.