Abstract:
In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of differential voltages (N≧1), to cause the digital-analog converter to generate an (N+1) th  pair of differential voltages by causing one of a positive side and a negative side of the digital-analog converter to output an (N+1) th  differential voltage and causing the other of the positive side and the negative side to output a differential voltage equal to the N th  differential voltage as an (N+1) th  differential voltage, and to output a digital signal corresponding to a comparison signal having a smallest voltage among (N+1) comparison signals.

Description:
PRIORITY 
       [0001]    This application claims the priority and benefit of U.S. Provisional Application No. 62/180,837, filed on Jun. 17, 2015, the entire content of which is incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    This disclosure relates to an analog-digital converter and a control method. 
       BACKGROUND 
       [0003]    A successive approximation analog-digital converter (ADC) generates different reference voltages with an internal digital-analog converter (DAC) and compares the voltage of an analog signal to be converted with the reference voltages in order to generate a digital signal corresponding to the voltage of the analog signal to be converted. An example of a successive approximation ADC has a resolution corresponding to the number of passive components in the internal DAC, i.e. a resolution of N bits for 2 N  passive components (where N is a natural number). 
         [0004]    In order to increase the resolution of such successive approximation ADC, a greater number of passive components needs to be provided in the internal DAC. Increasing the number of passive components in the DAC, however, raises manufacturing costs. Furthermore, conversion speed decreases and power consumption increases due to the increased time constant during analog-digital conversion. 
       SUMMARY 
       [0005]    It would therefore be helpful to provide a more efficient analog-digital converter and control method therefor. 
         [0006]    An analog-digital converter according to one aspect of this disclosure includes a digital-analog converter configured to output a differential voltage between a reference voltage and a voltage of an analog signal; a comparator configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter; and a register configured to cause the digital-analog converter to generate N pairs of differential voltages, where N is an integer greater than or equal to one, to cause the digital-analog converter to generate an (N+1) th  pair of differential voltages by causing one of a positive side and a negative side of the digital-analog converter to output an (N+1) th  differential voltage and causing the other of the positive side and the negative side to output a differential voltage equal to an N th  differential voltage as an (N+1) th  differential voltage, and to output a digital signal corresponding to a smallest comparison signal having a smallest voltage among (N+1) of the comparison signals. It is noted that as used in this disclosure, “register” refers to a circuit with storage elements used to control a converter. 
         [0007]    In the above aspect, the digital-analog converter may be a differential digital-analog converter comprising a pair of converters that each include (N+1) passive components, input the reference voltage and the voltage of the analog signal into the passive components, and generate N differential voltages between the reference voltage and the voltage of the analog signal. 
         [0008]    In the above aspect, the register may cause one passive component in one converter of the pair of converters to connect to the reference voltage and output the (N+1) th  differential voltage. 
         [0009]    The above aspect may further include a decoder configured to input a digital signal into the digital-analog converter based on a signal acquired from the register. 
         [0010]    In the above aspect, the passive components in the pair of converters may be capacitors, resistors, or a combination of capacitors and resistors. 
         [0011]    In the above aspect, the passive components in the pair of converters may be configured with a binary system or a segmented system. 
         [0012]    In the above aspect, the analog signal may be a differential signal or a single end signal. 
         [0013]    In the above aspect, the analog-digital converter may include a plurality of the comparators. 
         [0014]    In the above aspect, two reference voltages with different voltage levels may be connected via a switch to an input terminal on one of a positive side and a negative side in the comparators. 
         [0015]    In the above aspect, the register may switch the reference voltage connected to the input terminal by controlling the switch when causing the digital-analog converter to output the (N+1) th  differential voltage. 
         [0016]    A control method according to one aspect of this disclosure is a control method used in an analog-digital converter including a digital-analog converter, a comparator, and a register, the control method including the digital-analog converter outputting a differential voltage between a reference voltage and a voltage of an analog signal; the comparator outputting a comparison signal corresponding to the differential voltage output by the digital-analog converter; the register causing the digital-analog converter to generate N pairs of differential voltages, where N is an integer greater than or equal to one; the register causing the digital-analog converter to generate an (N+1) th  pair of differential voltages by causing one of a positive side and a negative side of the digital-analog converter to output an (N+1) th  differential voltage and causing the other of the positive side and the negative side to output a differential voltage equal to an N th  differential voltage as an (N+1) th  differential voltage; and the register outputting a digital signal corresponding to a smallest comparison signal having a smallest voltage among (N+1) of the comparison signals. 
         [0017]    In the above aspect, the digital-analog converter may include a pair of converters that each include (N+1) passive components, and the above aspect may further include the converters each inputting the reference voltage and the voltage of the analog signal into the passive components and generating N differential voltages between the reference voltage and the voltage of the analog signal. 
         [0018]    The above aspect may further include the register causing one passive component in one converter of the pair of converters to connect to the reference voltage and output the (N+1) th  differential voltage. 
         [0019]    In the above aspect, the analog-digital converter may include a decoder, and the control method may further include the decoder inputting a digital signal into the digital-analog converter based on a signal acquired from the register. 
         [0020]    In the above aspect, the passive components in the pair of converters may be capacitors, resistors, or a combination of capacitors and resistors. 
         [0021]    In the above aspect, the passive components in the pair of converters may be configured with a binary system or a segmented system. 
         [0022]    In the above aspect, the analog signal may be a differential signal or a single end signal. 
         [0023]    In the above aspect, the analog-digital converter may include a plurality of the comparators. 
         [0024]    In the above aspect, two reference voltages with different voltage levels may be connected via a switch to an input terminal on one of a positive side and a negative side in the comparators. 
         [0025]    The above aspect may futher include the register switching the reference voltage connected to the input terminal by controlling the switch when causing the digital-analog converter to output the (N+1) th  differential voltage. 
         [0026]    The analog-digital converter and control method according to the embodiments below are more efficient by using fewer passive components to improve accuracy, while reducing manufacturing costs, increasing conversion speed, and reducing power consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]    In the accompanying drawings: 
           [0028]      FIG. 1  is a functional block diagram illustrating an example of a 4-bit successive approximation ADC according to Embodiment 1; 
           [0029]      FIG. 2  is a functional block diagram illustrating an example of a differential 4-bit DAC provided with 4-bit DACs; 
           [0030]      FIG. 3  illustrates analog voltage output by the differential 4-bit DAC of  FIG. 2 ; 
           [0031]      FIG. 4  illustrates the positive analog output voltage and negative analog output voltage output by the differential 4-bit DAC of  FIG. 1 ; 
           [0032]      FIG. 5  is a flowchart illustrating an example control method executed by the differential 4-bit DAC of  FIG. 1 ; 
           [0033]      FIG. 6  illustrates an example of the circuit structure of the differential 4-bit DAC of  FIG. 2 ; 
           [0034]      FIG. 7  illustrates an example of the circuit structure of the differential 4-bit DAC of  FIG. 1 ; 
           [0035]      FIGS. 8A and 8B  illustrate the results of an experiment performed using a 13-bit successive approximation ADC provided with a differential 13-bit DAC configured using 12-bit DACs; 
           [0036]      FIG. 9  is a functional block diagram illustrating an example of a successive approximation ADC; 
           [0037]      FIG. 10  illustrates an example of the circuit structure of the differential 2-bit DAC of  FIG. 9 ; 
           [0038]      FIG. 11  illustrates signals input into the differential 2-bit DAC of  FIG. 9 ; 
           [0039]      FIG. 12  illustrates an example of digital output by the successive approximation ADC of  FIG. 9 ; 
           [0040]      FIG. 13  is a functional block diagram illustrating an example of a 3-bit successive approximation ADC according to Embodiment 2; 
           [0041]      FIG. 14  is a functional block diagram illustrating an example of the differential 3-bit DAC in  FIG. 13 ; 
           [0042]      FIG. 15  illustrates signals input into the differential 3-bit DAC of  FIG. 13 ; 
           [0043]      FIG. 16  illustrates an example of digital output by the successive approximation ADC of  FIG. 13 ; 
           [0044]      FIG. 17  is a functional block diagram illustrating an example of a successive approximation ADC; 
           [0045]      FIG. 18  illustrates an example of the circuit structure of the differential 3-bit DAC of  FIG. 17 ; 
           [0046]      FIG. 19  is a functional block diagram illustrating an example of a 4-bit successive approximation ADC according to Embodiment 3; 
           [0047]      FIG. 20  illustrates an example of the circuit structure of the differential 4-bit DAC of  FIG. 19 ; 
           [0048]      FIG. 21  illustrates signals input into the 1-bit capacitive DAC of  FIG. 19 ; 
           [0049]      FIG. 22  illustrates signals input to and output from the 3-bit resistive DAC of  FIG. 19 ; 
           [0050]      FIG. 23  illustrates an example of digital output by the successive approximation ADC of  FIG. 19  in the case of inputting a single end signal; 
           [0051]      FIG. 24  illustrates an example of digital output by the successive approximation ADC of  FIG. 19  in the case of inputting a differential signal; 
           [0052]      FIG. 25  illustrates an example of the circuit structure of a differential comparator circuit provided in a flash ADC according to this disclosure; 
           [0053]      FIG. 26  illustrates an example of the control state of each switch in the differential comparator circuit illustrated in  FIG. 25 ; and 
           [0054]      FIG. 27  illustrates an example of digital output of a 3-bit flash ADC. 
       
    
    
     DETAILED DESCRIPTION 
       [0055]    The following describes the disclosed embodiments with reference to the drawings. 
       Embodiment 1 
       [0056]      FIG. 1  is a functional block diagram illustrating an example of a successive approximation ADC according to one of the disclosed embodiments. The successive approximation ADC of this embodiment is a 4-bit successive approximation ADC having a resolution of four bits. A 4-bit successive approximation ADC  10  includes a decoder  11 , a differential 4-bit DAC  12 , a comparator  13 , and a successive approximation register (SAR)  14 . Under the control of the SAR  14 , the 4-bit successive approximation ADC  10  generates the differential voltage between the input analog voltage to be converted and a 4-bit resolution reference voltage with the differential 4-bit DAC  12  and the comparator  13  and tests whether the differential voltage is minimized, thereby generating and outputting a digital signal corresponding to the analog voltage. At this time, the differential 4-bit DAC  12  and the comparator  13  pass through a sampling phase and a trial phase with at least two trials. In this embodiment, the input analog signal to be converted is a differential signal having a voltage corresponding to the difference in potential between a positive analog signal VIP and a negative analog signal VIM. The reference voltage is the differential voltage between a high-voltage reference voltage VRH and a low-voltage reference voltage VRL supplied by a non-illustrated power source. Furthermore, the differential voltage to be tested (trial voltage), i.e. the difference between the analog voltage to be converted and the reference voltage, is the differential voltage between a positive analog output voltage VOP and a negative analog output voltage VOM, which are input into the comparator  13  from the differential 4-bit DAC  12 . 
         [0057]    The SAR  14  controls the overall analog-digital conversion processing by the 4-bit successive approximation ADC  10 . A clock signal and a sample signal are input into the SAR  14 . The sample signal is a signal that controls sampling. When the sample signal is on, the SAR  14  executes processing for the sampling phase in the differential 4-bit DAC  12 , and when the sample signal is off, the SAR  14  executes processing for the trial phase in the differential 4-bit DAC  12 . The SAR  14  generates a signal for controlling processing for successive approximation in the differential 4-bit DAC  12  and the comparator  13  and outputs the signal to the decoder  11 . The signal output by the SAR  14  is referred to below as a control signal for successive approximation processing. 
         [0058]    Based on the control signal for successive approximation processing obtained from the SAR  14 , the decoder  11  inputs, into the differential 4-bit DAC  12 , signals for controlling the on/off operation of each switch provided in the differential 4-bit DAC  12 . 
         [0059]    In response to the switch control signals input from the decoder  11  as digital signals, the differential 4-bit DAC  12  generates the positive analog output voltage VOP and the negative analog output voltage VOM based on a positive analog input voltage VIP and a negative analog input voltage VIM input into the differential 4-bit DAC  12  and on the high-voltage reference voltage VRH and the low-voltage reference voltage VRL input into the differential 4-bit DAC  12 . The positive analog output voltage VOP and the negative analog output voltage VOM respectively represent the differential voltage between the high-voltage reference voltage VRH and the positive analog input voltage VIP and the differential voltage between the low-voltage reference voltage VRL and the negative analog input voltage VIM in each trial of the trial phase. 
         [0060]    In this embodiment, the positive analog output voltage VOP and the negative analog output voltage VOM output by the differential 4-bit DAC  12  are respectively generated by a positive 3-bit DAC  15  and a negative 3-bit DAC  16  included in the differential 4-bit DAC  12 . In response to the switch control signal input from the decoder  11 , the positive 3-bit DAC  15  generates the positive analog output voltage VOP from the high-voltage reference voltage VRH and the positive analog input voltage VIP. In response to the switch control signal input from the decoder  11 , the negative 3-bit DAC  16  generates the negative analog output voltage VOM from the low-voltage reference voltage VRL and the negative analog input voltage VIM. In this embodiment, the positive 3-bit DAC  15  and the negative 3-bit DAC  16  execute 4-bit processing to convert the switch control signal into the analog output voltage. 
         [0061]    As an example related to this embodiment, an example using a 4-bit DAC to output analog voltage with 4-bit resolution is described using  FIGS. 2 and 3 .  FIGS. 2 and 3  illustrate output of analog voltage with 4-bit resolution by a differential 4-bit DAC that includes 4-bit DACs. The differential 4-bit DAC  22  illustrated in  FIG. 2  includes a positive 4-bit DAC  25  and a negative 4-bit DAC  26 . 
         [0062]      FIG. 3  illustrates trial voltage output by the differential 4-bit DAC  22  illustrated in  FIG. 2 . In  FIG. 3 , the vertical axis represents the voltage level of the analog output voltages VOP and VOM output by the differential 4-bit DAC  22 , and the horizontal axis represents the passage of time by processing phases executed by the differential 4-bit DAC  22 . As illustrated in  FIG. 3 , the differential 4-bit DAC  22  first samples the analog input signal that is input into the differential 4-bit DAC  22  (sampling phase) and then performs trials from the first bit trial to the fourth (last) bit trial (trial phase). By performing these four trials, the differential 4-bit DAC  22  outputs the positive analog output voltage VOP and negative analog output voltage VOM with 4-bit resolution. In this example, the trial voltage that is the differential voltage between the positive analog output voltage VOP and the negative analog output voltage VOM is shown changing from nearly 0 V to 4 V, 2 V, and 1 V from the first bit trial to the last (fourth) bit trial. In this way, analog-digital conversion is achieved by performing trials at the resolution corresponding to the number of bits and using the digital value corresponding to the reference voltage when the trial voltage is minimized, i.e. when the difference between the analog input voltage and the reference voltage is minimized. 
         [0063]      FIG. 4  illustrates the positive analog output voltage VOP and negative analog output voltage VOM output by the differential 4-bit DAC  12  (of  FIG. 1 ) in this embodiment. In  FIG. 4 , the vertical axis represents the voltage level of the analog output voltages output by the differential 4-bit DAC  12 , and the horizontal axis represents the passage of time by processing phases executed by the differential 4-bit DAC  12 . As illustrated in  FIG. 4 , the differential 4-bit DAC  12  first samples the analog input signal. The differential 4-bit DAC  12  then performs the first through third bit trails by symmetrically controlling the positive 3-bit DAC  15  and the negative 3-bit DAC  16 . 
         [0064]    Finally, the differential 4-bit DAC  12  performs the last bit trial. In the last bit trial, asymmetrical control is performed on the positive 3-bit DAC  15  and the negative 3-bit DAC  16 . In greater detail, in the last bit trial, similar control to the control in the third bit trial is performed on the negative 3-bit DAC  16 , whereas control differing from the control in the third bit trial is performed on the positive 3-bit DAC  15 . In other words, control is only performed on the positive side in the last bit trial, unlike the first through the third bit trials in which control is performed on both the positive and negative sides. By performing such asymmetrical control, the differential 4-bit DAC  12  generates a positive analog output voltage VOP and negative analog output voltage VOM that are asymmetrical in the last bit trial, unlike the symmetrical positive analog output voltage VOP and negative analog output voltage VOM output in the first to third trials. In this way, with the positive 3-bit DAC  15  and negative 3-bit DAC  16  that have 3-bit resolution, the differential 4-bit DAC  12  achieves conversion to a 4-bit resolution digital signal in the ADC. In other words, the trial voltage that is the differential voltage between the positive analog output voltage VOP and the negative analog output voltage VOM is shown changing from the first bit trial to the last (fourth) bit trial. Analog-digital conversion is performed by using the digital value corresponding to the reference voltage when the trial voltage is minimized, i.e. when the difference between the analog input voltage and the reference voltage is minimized. 
         [0065]    The circuit structure of the positive 3-bit DAC  15  and the negative 3-bit DAC  16  that achieve the above-described asymmetrical control during the last bit trial is described below. 
         [0066]    Referring again to  FIG. 1 , the comparator  13  compares the positive analog output voltage VOP and the negative analog output voltage VOM obtained from the differential 4-bit DAC  12  and outputs a signal corresponding to the result of comparison (also referred to below simply as a “comparison signal”). In greater detail, the comparator  13  outputs a comparison signal corresponding to the trial voltage that is the difference between the positive analog output voltage VOP and the negative analog output voltage VOM. 
         [0067]    The SAR  14  stores the comparison signal output from the comparator  13 . Upon obtaining the comparison signal with 4-bit resolution from the comparator  13  and storing the comparison signal, based on the comparison signal the SAR  14  outputs a digital signal of the value corresponding to the reference voltage when the trial voltage is minimized, i.e. when the difference between the analog input voltage and the reference voltage is minimized. 
         [0068]      FIG. 5  is a flowchart illustrating an example of control method executed by the differential 4-bit DAC  12  of  FIG. 1 . 
         [0069]    First, the differential 4-bit DAC  12  symmetrically controls the positive 3-bit DAC  15  and the negative 3-bit DAC  16  (step S 11 ). 
         [0070]    Next, the differential 4-bit DAC  12  determines whether three bit trials have been performed (step S 12 ). The differential 4-bit DAC  12  determines whether three bit trials have been performed for example based on whether the below-described signal CTL has been input into the differential 4-bit DAC  12  from the decoder  11 . 
         [0071]    When determining that three bit trials have not been performed (step S 12 : No), then the differential 4-bit DAC  12  repeats step S 11  and step S 12  until determining in step S 12  that three bit trials have been performed. 
         [0072]    When determining that three bit trials have been performed (step S 12 : Yes), the differential 4-bit DAC  12  asymmetrically controls the positive 3-bit DAC  15  and the negative 3-bit DAC  16  as the last bit trial (step S 13 ). The processing then terminates. 
         [0073]    Since the above description of  FIG. 5  is based on the differential 4-bit DAC  12  illustrated in  FIG. 1 , the differential 4-bit DAC  12  has been described as determining in step S 12  whether three bit trials have been performed. For example, a differential (N+1)-bit DAC, however, would determine in step S 12  whether N bit trials have been performed, where N is an integer greater than or equal to one. 
         [0074]    Next, the circuit structure of the differential 4-bit DAC is described. First, with reference to  FIG. 6 , the circuit structure of the differential 4-bit DAC  22  illustrated in  FIG. 2  is described. 
         [0075]    In the example illustrated in  FIG. 6 , in the differential 4-bit DAC  22 , the positive 4-bit DAC  25  and the negative 4-bit DAC  26  each include five capacitors as passive components. In  FIG. 6 , the 10 capacitors are indicated as capacitors with capacitances of C, C, 2C, 4C, and 8C. Below, the capacitors C P1 , C P2 , C P3 , C P4 , and C P5  in the positive 4-bit DAC  25  respectively have capacitances of C, C, 2C, 4C, and 8C. The capacitors C M1 , C M2 , C M3 , C M4 , and C M5  in the negative 4-bit DAC  26  respectively have capacitances of C, C, 2C, 4C, and 8C. 
         [0076]    In the positive 4-bit DAC  25 , the capacitor C P1  is connected to the positive analog input voltage VIP and the low-voltage reference voltage VRL respectively via the switches S A  and S A ′. The capacitors C P2 , C P3 , C P4 , and C P5  are connected in parallel to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL. The capacitors C P2 , C P3 , C P4 , and C P5  are connected to the positive analog input voltage VIP via respective switches S A . The capacitors C P2 , C P3 , C P4 , and C P5  are connected to the high-voltage reference voltage VRH respectively via the switches S H0 , S H1 , S H2 , and S H3 . The capacitors C P2 , C P3 , C P4 , and C P5  are connected to the low-voltage reference voltage VRL respectively via the switches S L0 , S L1 , S L2 , and S L3 . The capacitors C P1 , C P2 , C P3 , C P4 , and C P5  are connected to an input common voltage VCM of the comparator via the switch S A . 
         [0077]    In the negative 4-bit DAC  26  as well, so as to be symmetrical with the positive 4-bit DAC  25 , the capacitor C M1  is connected to the negative analog input voltage VIM and the high-voltage reference voltage VRH respectively via the switches S A  and S A ′. The capacitors C M2 , C M3 , C M4 , and C M5  are connected in parallel to the negative analog input voltage VIM, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL. The capacitors C M2 , C M3 , C M4 , and C M5  are connected to the negative analog input voltage VIM via respective switches S A . The capacitors C M2 , C M3 , C M4 , and C M5  are connected to the high-voltage reference voltage VRH respectively via the switches S L0 , S L1 , S L2 , and S L3 . The capacitors C M2 , C M3 , C M4 , and C M5  are connected to the low-voltage reference voltage VRL respectively via the switches S H0 , S H1 , S H2 , and S H3 . The capacitors C M1 , C M2 , C M3 , C M4 , and C M5  are connected to the input common voltage VCM of the comparator via the switch S A . 
         [0078]    In the differential 4-bit DAC  22 , switches labeled with the same reference sign perform the same on/off operation. 
         [0079]    In the differential 4-bit DAC  22  illustrated in  FIG. 6 , when sampling, the switches S A  in the positive 4-bit DAC  25  and the negative 4-bit DAC  26  are controlled to be in a closed state, i.e. on state (referred to below simply as “on”), whereas the other switches are controlled to be in a closed state, i.e. off state (referred to below simply as “off”). When the switches S A  are on, a charge corresponding to the positive analog input voltage VIP accumulates in all of the capacitors C P1 , C P2 , C P3 , C P4 , and C P5  in the positive 4-bit DAC  25 , and a charge corresponding to the negative analog input voltage VIM accumulates in all of the capacitors C M1 , C M2 , C M3 , C M4 , and C M5  in the negative 4-bit DAC  26 . 
         [0080]    Next, when the differential 4-bit DAC  22  performs the first bit trial, the switches S A ′, S L0 , S L1 , S L2 , and S H3  are turned on, and the other switches are turned off. By the switches S A ′ turning on, the capacitor C P1  is connected to the low-voltage reference voltage VRL, and the capacitor C M1  is connected to the high-voltage reference voltage VRH. By the switches S L0 , S L1 , and S L2  turning on, the capacitors C P2 , C P3 , and C P4  are connected to the low-voltage reference voltage VRL, and the capacitors C M2 , C M3 , and C M4  are connected to the high-voltage reference voltage VRH. By the switches S H3  turning on, the capacitor C P5  is connected to the high-voltage reference voltage VRH, and the capacitor C M5  is connected to the low-voltage reference voltage VRL. By the switches S A  turning off, the capacitors C P1 , C P2 , C P3 , C P4 , and C P5  in the positive 4-bit DAC  25  are disconnected from the positive analog input voltage VIP, and the capacitors C M1 , C M2 , C M3 , C M4 , and C M5  in the negative 4-bit DAC  26  are disconnected from the negative analog input voltage VIM. 
         [0081]    In the first bit trial, as a result of the above-described on/off control of the switches, the positive analog output voltage VOP that is output is the difference in potential between the positive analog input voltage VIP and the reference voltage that is determined by the capacitors C P1 , C P2 , C P3 , C P4 , and C P5  and the connection with the high-voltage reference voltage VRH or the low-voltage reference voltage VRL. 
         [0082]    Similarly on the negative side, the negative analog output voltage VOM that is output is the difference in potential between the negative analog input voltage VIM and the reference voltage that is determined by the capacitors C M1 , C M2 , C M3 , C M4 , and C M5  and the connection with the high-voltage reference voltage VRH or the low-voltage reference voltage VRL. 
         [0083]    Next, when the differential 4-bit DAC  22  performs the second bit trial, based on the result of the first bit trial, either the switches S H3  are turned on and the switches S L3  are turned off, or vice-versa. Furthermore, the switches S L2  are turned off, and the switches S H2  are turned on. In other words, in the second bit trial, the capacitor C P4  is disconnected from the low-voltage reference voltage VRL and is electrically connected to the high-voltage reference voltage VRH. In the second bit trial, the capacitor C M4  is electrically disconnected from the high-voltage reference voltage VRH and connected to the low-voltage reference voltage VRL. In the second bit trial as well, as in the first bit trial, the difference in potential between the reference voltage and the positive analog input voltage VIP is output as the positive analog output voltage VOP, and the difference in potential between the reference voltage and the negative analog input voltage VIM is output as the negative analog output voltage VOM. 
         [0084]    Next, when the differential 4-bit DAC  22  performs the third bit trial, based on the result of the second bit trial, either the switches S H2  are turned on and the switches S L2  are turned off, or vice-versa. Furthermore, the switches S L1  are turned off, and the switches S H1  are turned on. In other words, in the third bit trial, the capacitor C P3  is disconnected from the low-voltage reference voltage VRL and is connected to the high-voltage reference voltage VRH. In the third bit trial, the capacitor C M3  is disconnected from the high-voltage reference voltage VRH and connected to the low-voltage reference voltage VRL. In the third bit trial as well, as in the first bit trial, the difference in potential between the reference voltage and the positive analog input voltage VIP is output as the positive analog output voltage VOP, and the difference in potential between the reference voltage and the negative analog input voltage VIM is output as the negative analog output voltage VOM. 
         [0085]    Finally, when the differential 4-bit DAC  22  performs the fourth bit trial, based on the result of the third bit trial, either the switches S H1  are turned on and the switches S L1  are turned off, or vice-versa. Furthermore, the switches S L0  are turned off, and the switches S H0  are turned on. In other words, in the fourth bit trial, the capacitor C P2  is disconnected from the low-voltage reference voltage VRL and is connected to the high-voltage reference voltage VRH. In the fourth bit trial, the capacitor C M2  is disconnected from the high-voltage reference voltage VRH and electrically connected to the low-voltage reference voltage VRL. In the fourth bit trial as well, as in the first bit trial, the difference in potential between the reference voltage and the positive analog input voltage VIP is output as the positive analog output voltage VOP, and the difference in potential between the reference voltage and the negative analog input voltage VIM is output as the negative analog output voltage VOM. 
         [0086]    By performing the first through fourth bit trials with the above-described on/off operations of the switches, the differential 4-bit DAC  22  outputs the positive analog output voltage VOP and negative analog output voltage VOM with 4-bit resolution. 
         [0087]    The positive analog output voltage VOP and negative analog output voltage VOM output from the differential 4-bit DAC  22  are then compared in the comparator  13 . In greater detail, the comparator  13  amplifies and outputs the differential voltage between the positive analog output voltage VOP and the negative analog output voltage VOM. The trial voltage corresponding to the difference between the positive analog output voltage VOP and the negative analog output voltage VOM corresponds to the difference between the differential voltage between the high-voltage reference voltage VRH and the low-voltage reference voltage VRL (VRH−VRL) and the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM (VIP−VIM). The digital signal corresponding to the reference voltage for which this difference is closest to zero is output from the ADC. 
         [0088]    By contrast, the circuit in the differential 4-bit DAC  12  of this embodiment is structured as illustrated in  FIG. 7 . In the example illustrated in  FIG. 7 , as in the example illustrated in  FIG. 6 , the passive components are capacitors and are structured according to a binary system. In greater detail, the positive 3-bit DAC  15  and negative 3-bit DAC  16  each include four capacitors as passive components. The capacitors C P11 , C P12 , C P13 , and C P14  in the positive 3-bit DAC  15  respectively have capacitances of C, C, 2C, and 4C. The capacitors C M11 , C M12 , C M13 , and C M14  in the negative 3-bit DAC  16  respectively have capacitances of C, C, 2C, and 4C. The passive components may be structured according to a system other than the binary system. For example, individual passive components may be connected in parallel in a segmented system or may be structured according to any other system. The DAC may also be structured using resistors as the passive components. 
         [0089]    In the positive 3-bit DAC  15 , the capacitor C P11  is connected to the positive analog input voltage VIP and the low-voltage reference voltage VRL respectively via the switches S A  and S A ′. The capacitor C P11  is further connected to the high-voltage reference voltage VRH via a switch S HX . The capacitors C P12 , C P13 , and C P14  are connected in parallel to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL. The capacitors C P12 , C P13 , and C P14  are connected to the positive analog input voltage VIP via respective switches S A . The capacitors C P12 , C P13 , and C P14  are connected to the high-voltage reference voltage VRH respectively via the switches S H0 , S H1 , and S H2 . The capacitors C P12 , C P13 , and C P14  are connected to the low-voltage reference voltage VRL respectively via the switches S L0 , S L1 , and S L2 . The capacitors C P11 , C P12 , C P13 , and C P14  are connected to the input common voltage VCM of the comparator via the switch S A . 
         [0090]    On the other hand, in the negative 3-bit DAC  16 , the capacitor C M11  is connected to the negative analog input voltage VIM and the high-voltage reference voltage VRH respectively via the switches S A  and S A ′. The capacitors C M12 , C M13 , and C M14  are connected in parallel to the negative analog input voltage VIM, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL. The capacitors C M12 , C M13 , and C M14  are connected to the negative analog input voltage VIM via respective switches S A . The capacitors C M12 , C M13 , and C M14  are connected to the high-voltage reference voltage VRH respectively via the switches S L0 , S L1 , and S L2 . The capacitors C M12 , C M13 , and C M14  are connected to the low-voltage reference voltage VRL respectively via the switches S H0 , S H1 , and S H2 . The capacitors C M11 , C M12 , C M13 , and C M14  are connected to the input common voltage VCM of the comparator via the switch S A . 
         [0091]    In the differential 4-bit DAC  12 , switches labeled with the same reference sign perform the same on/off operation, as in the differential 4-bit DAC  22 . 
         [0092]    In the differential 4-bit DAC  12  illustrated in  FIG. 7 , when sampling, the switches S A  in the positive 3-bit DAC  15  and the negative 3-bit DAC  16  are controlled to be on, whereas the other switches are controlled to be off. In other words, by connection of the switches S A , a charge corresponding to the positive analog input voltage VIP accumulates in all of the capacitors C P11 , C P12 , C P13 , and C P14  in the positive 3-bit DAC  15 . Furthermore, a charge corresponding to the negative analog input voltage VIM accumulates in all of the capacitors C M11 , C M12 , C M13 , and C M14  in the negative 3-bit DAC  16 . 
         [0093]    Next, when the differential 4-bit DAC  12  performs the first bit trial, the switches S A ′, S L0 , S L1 , and S H2  are turned on, and the other switches are turned off. By the switches S A ′ turning on, the capacitor C P11  is connected to the low-voltage reference voltage VRL, and the capacitor C M11  is connected to the high-voltage reference voltage VRH. By the switches S L0  and S L1  turning on, the capacitors C P12  and C P13  are connected to the low-voltage reference voltage VRL, and the capacitors C M12  and C M13  are connected to the high-voltage reference voltage VRH. By the switches S H2  turning on, the capacitor C P14  is connected to the high-voltage reference voltage VRH, and the capacitor C M14  is connected to the low-voltage reference voltage VRL. By the switches S A  turning off, the capacitors C P11 , C P12 , C P13 , and C P14  in the positive 3-bit DAC  15  are disconnected from the positive analog input voltage VIP, and the capacitors C M11 , C M12 , C M13 , and C M14  in the negative 3-bit DAC  16  are disconnected from the negative analog input voltage VIM. 
         [0094]    In the first bit trial, the on/off operation of each switch is controlled as described above. As a result, the positive analog output voltage VOP that is output is the difference in potential between the positive analog input voltage VIP and the reference voltage that is determined by the capacitors C P11 , C P12 , C P13 , and C P14  and the connection with the high-voltage reference voltage VRH or the low-voltage reference voltage VRL. In this way, the positive 3-bit DAC  15  converts the digital signal input from the decoder  11  (switch control signal) into an analog signal (positive analog output voltage VOP). 
         [0095]    Similarly on the negative side, the negative analog output voltage VOM that is output is the difference in potential between the negative analog input voltage VIM and the reference voltage that is determined by the capacitors C M11 , C M12 , C M13 , and C M14  and the connection with the high-voltage reference voltage VRH or the low-voltage reference voltage VRL. In this way, the negative 3-bit DAC  16  converts the digital signal input from the decoder  11  (switch control signal) into an analog signal (negative analog output voltage VOM). 
         [0096]    Next, when the differential 4-bit DAC  12  performs the second bit trial, based on the result of the first bit trial, either the switches S H2  are turned on and the switches S L2  are turned off, or vice-versa. Furthermore, the switches S L1  are turned off, and the switches S H1  are turned on. In other words, in the second bit trial, the capacitor C P13  is disconnected from the low-voltage reference voltage VRL and is connected to the high-voltage reference voltage VRH. In the second bit trial, the capacitor C M13  is disconnected from the high-voltage reference voltage VRH and connected to the low-voltage reference voltage VRL. In the second bit trial as well, as in the first bit trial, the difference in potential between the reference voltage and the positive analog input voltage VIP is output as the positive analog output voltage VOP, and the difference in potential between the reference voltage and the negative analog input voltage VIM is output as the negative analog output voltage VOM. 
         [0097]    Next, when the differential 4-bit DAC  12  performs the third bit trial, based on the result of the second bit trial, either the switches S H1  are turned on and the switches S L1  are turned off, or vice-versa. Furthermore, the switches S L0  are turned off, and the switches S H0  are turned on. In other words, in the third bit trial, the capacitor C P12  is disconnected from the low-voltage reference voltage VRL and is connected to the high-voltage reference voltage VRH. In the third bit trial, the capacitor C M12  is disconnected from the high-voltage reference voltage VRH and connected to the low-voltage reference voltage VRL. In the third bit trial as well, as in the first bit trial, the difference in potential between the reference voltage and the positive analog input voltage VIP is output as the positive analog output voltage VOP, and the difference in potential between the reference voltage and the negative analog input voltage VIM is output as the negative analog output voltage VOM. 
         [0098]    Finally, the differential 4-bit DAC  12  performs an additional last bit trial. During the last bit trial, based on the result of the third bit trial, either the switches S H0  are turned on and the switches S L0  are turned off, or vice-versa. Furthermore, in the circuit of the positive 3-bit DAC  15  illustrated in  FIG. 7 , the switch S HX  is turned on. In other words, in the last bit trial, the capacitor C P11  is connected to the high-voltage reference voltage VRH. On the other hand, the negative 3-bit DAC  16  does not change from the third bit trial. In this way, since the on/off state of the switches in the negative 3-bit DAC  16  does not change in the last bit trial as compared to the third bit trial, the negative analog output voltage VOM does not change. On the other hand, by the switch S HX  in the positive 3-bit DAC  15  turning on, the positive analog output voltage VOP is changed. In this way, by the positive 3-bit DAC  15  and the negative 3-bit DAC  16  operating asymmetrically, in the last bit trial the trial voltage that is the difference between the negative analog output voltage VOM and the positive analog output voltage VOP can be reduced from the trial voltage during the third bit trial, even though 3-bit DACs are used. 
         [0099]    The positive analog output voltage VOP and negative analog output voltage VOM output from the differential 4-bit DAC  12  are then compared in the comparator  13 . In greater detail, the comparator  13  amplifies and outputs the trial voltage that is the difference between the positive analog output voltage VOP and the negative analog output voltage VOM. The differential voltage between the positive analog output voltage VOP and the negative analog output voltage VOM corresponds to the difference between the differential voltage between the high-voltage reference voltage VRH and the low-voltage reference voltage VRL (VRH−VRL) and the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM (VIP−VIM). The digital signal corresponding to the reference voltage when this difference is closest to zero is output from the 4-bit successive approximation ADC  10 . 
         [0100]    By the differential 4-bit DAC  12  controlling the positive 3-bit DAC  15  and the negative 3-bit DAC  16  asymmetrically during the last bit trial, the 4-bit successive approximation ADC  10  of this embodiment can convert an analog signal into a digital signal with 4-bit resolution. Therefore, as compared to the differential 4-bit DAC  22  that includes the positive 4-bit DAC  25  and the negative 4-bit DAC  26 , the differential 4-bit DAC  12  can achieve output as a digital signal with 4-bit resolution using fewer passive components. By reducing the number of components in this way, the 4-bit successive approximation ADC  10  according to this embodiment can reduce manufacturing costs. Furthermore, by reducing the number of components, the time constant during analog-digital conversion is decreased, thereby increasing conversion speed. By reducing the number of components, the power consumption in the 4-bit successive approximation ADC  10  also decreases. 
         [0101]    In this embodiment, a 4-bit successive approximation ADC that outputs a digital signal with 4-bit resolution using 3-bit DACs has been described, but this disclosure is not limited to this embodiment. According to this disclosure, based on the above-described principle, a successive approximation ADC that outputs a digital signal with N-bit resolution (N being an integer greater than or equal to two), i.e. an N-bit successive approximation ADC, can be achieved using (N−1)-bit DACs. In this case, the N-bit successive approximation ADC can output a digital signal with N-bit resolution by controlling a positive (N−1)-bit DAC and a negative (N−1)-bit DAC symmetrically until the (N−1) th  bit trial and asymmetrically during the N th  (last) bit trial. In other words, according to this embodiment, in a successive approximation ADC configured using the same number of passive components as a typical successive approximation ADC, one bit can be added to the resolution of the successive approximation ADC by adding one switch. 
         [0102]      FIGS. 8A and 8B  illustrate the results of an experiment performed using a 13-bit successive approximation ADC provided with a differential 13-bit DAC configured using 12-bit DACs, illustrating the positive analog output voltage VOP and the negative analog output voltage VOM from the differential 13-bit DAC. As illustrated in  FIG. 8A , in the bit trials after sampling, the differential 13-bit DAC outputs the positive analog output voltage VOP and the negative analog output voltage VOM.  FIG. 8B  is an expanded view of area D in  FIG. 8A . As illustrated in  FIGS. 8A and 8B , from the first bit trial through the twelfth bit trial, positive analog output voltage VOP and negative analog output voltage VOM that are symmetrical are output. For the voltage that is output during the thirteenth (last) trial, the negative analog output voltage VOM is the same as the voltage output in the twelfth trial, whereas the positive analog output voltage VOP is higher than the voltage output in the twelfth trial and approaches the negative analog output voltage VOM. 
       Embodiment 2 
       [0103]    In Embodiment 1, the positive analog input voltage VIP and the negative analog input voltage VIM are described as being differential signals, but the positive analog input voltage VIP and the negative analog input voltage VIM need not be differential signals. The positive analog input voltage VIP and the negative analog input voltage VIM may, for example, be single end signals. An example of the positive analog input voltage VIP and the negative analog input voltage VIM being single end signals is described as Embodiment 2 with comparison to a typical successive approximation ADC. 
         [0104]      FIG. 9  illustrates an example of a typical successive approximation ADC, namely a 2-bit successive approximation ADC that converts an analog signal to a digital signal with 2-bit resolution. The 2-bit successive approximation ADC  30  illustrated in  FIG. 9  includes a decoder  31 , a differential 2-bit DAC  32 , a comparator  33 , and a SAR  34 . The functions of the decoder  31 , differential 2-bit DAC  32 , comparator  33 , and SAR  34  are similar to those of the decoder  11 , differential 4-bit DAC  12 , comparator  13 , and SAR  14  of Embodiment 1, and therefore a description thereof is omitted. The differential 2-bit DAC  32 , however, differs from the differential 4-bit DAC  12  by outputting analog output voltage with 2-bit resolution. 
         [0105]    The SAR  34  generates IN 0  and IN 1  as control signals for successive approximation processing and outputs the generated control signals for successive approximation processing to the decoder  31 . The SAR  34  generates a signal S A  and outputs the generated signal S A  to the differential 2-bit DAC  32 . The signal S A  is a signal for performing on/off control of the switches S A  illustrated in  FIG. 10 . 
         [0106]    Based on the signals IN 0  and IN 1  input from the SAR  34 , the decoder  31  generates signals S H0 , S H1 , S L1 , and S L0  and outputs the generated signals to the differential 2-bit DAC  32 . The signals S H0 , S H1 , S L1 , and S L0  are signals for performing on/off control of the switches S H0 , S H1 , S L1 , and S L0  illustrated in  FIG. 10 . 
         [0107]    The comparison signal output by the comparator  33  is referred to as CMP. 
         [0108]    The signals S A , S A ′, S H0 , S H1 , S L1 , and S L0  are each output as either “1” indicating “on” or “0” indicating “off”. The signals S A  and S A ′ perform mutually inverse on/off operations. In other words, when the signal S A  is on, the signal S A ′ is off, and when the signal S A  is off, the signal S A ′ is on. 
         [0109]    The digital signal output from the 2-bit successive approximation ADC  30  is referred to as D out . 
         [0110]      FIG. 10  illustrates an example of the circuit structure of the differential 2-bit DAC  32  of  FIG. 9 . As illustrated in  FIG. 10 , the differential 2-bit DAC  32  includes a positive 2-bit DAC  35  and a negative 2-bit DAC  36 . The positive 2-bit DAC  35  and the negative 2-bit DAC  36  each include five capacitors as passive components. The capacitors C P21 , C P22 , C P23 , C P24 , and C P25  in the positive 2-bit DAC  35  respectively have capacitances of C, C, 2C, 2C, and 2C. The capacitors C M21 , C M22 , C M23 , C M24 , and C M25  in the negative 2-bit DAC  36  respectively have capacitances of C, C, 2C, 2C, and 2C. 
         [0111]    In the positive 2-bit DAC  35 , the capacitor C P21  is connected to the positive analog input voltage VIP and the low-voltage reference voltage VRL respectively via the switches S A  and S A ′. The capacitor C P22  is connected in parallel to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL respectively via the switches S A , S H0 , and S L0 . The capacitor C P23  is connected in parallel to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL respectively via the switches S A , S H1 , and S L1 . 
         [0112]    The capacitors C P24  and C P25  are connected to the positive analog input voltage VIP via respective switches S A . The capacitor C P24  is connected to the high-voltage reference voltage VRH via the switch S A ′, and the capacitor C P25  is connected to the low-voltage reference voltage VRL via the switch S A ′. The capacitors C P21 , C P22 , C P23 , C P24 , and C P25  are connected to a fixed voltage via the switch S A . The common voltage of the comparator input is fixed at VRH/2. 
         [0113]    In the negative 2-bit DAC  36 , the capacitor C M21  is connected to the negative analog input voltage VIM and the high-voltage reference voltage VRH respectively via the switches S A  and S A ′. The capacitor C M22  is connected in parallel to the negative analog input voltage VIM, the low-voltage reference voltage VRL, and the high-voltage reference voltage VRH respectively via the switches S A , S H0 , and S L0 . The capacitor C M23  is connected in parallel to the negative analog input voltage VIM, the low-voltage reference voltage VRL, and the high-voltage reference voltage VRH respectively via the switches S A , S H1 , and S L1 . 
         [0114]    The capacitors C M24  and C M25  are connected to the negative analog input voltage VIM via respective switches S A . The capacitor C M24  is connected to the low-voltage reference voltage VRL via the switch S A ′, and the capacitor C M25  is connected to the high-voltage reference voltage VRH via the switch S A ′. The capacitors C M21 , C M22 , C M23 , C M24 , and C M25  are connected to the fixed voltage VRH/2 via the switch S A . 
         [0115]    In the differential 2-bit DAC  32 , the capacitors C P24 , C P25 , C M24 , and C M25  are provided in order to match the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM, which are single end signals, to the differential voltage between the high-voltage reference voltage VRH and the low-voltage reference voltage VRL. In other words, with the capacitors C P24 , C P25 , C M24 , and C M25 , even when the input voltage is a single end signal, the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM becomes the same differential voltage as when the input voltage is a differential signal. Therefore, the resolution in the differential 2-bit DAC  32  can be maintained without any reduction. 
         [0116]    Next, with reference to  FIGS. 11 and 12 , an example of each signal and of digital output in the 2-bit successive approximation ADC  30  is described. In  FIGS. 11 and 12 , the logic level of the signals IN 0 , IN 1 , and CMP is indicated as “0” or “1”. 
         [0117]      FIG. 11  illustrates signals input into the differential 2-bit DAC  32  of  FIG. 9 . In  FIG. 11 , the on/off states of the signals S A , IN 1 , IN 0 , S H1 , S H0 , S L1 , and S L0  in the sampling phase and the trial phase are indicated in table form. As illustrated in  FIG. 11 , in the sampling phase, only the signal S A  is on, i.e. the switches S A  in  FIG. 10  are on. As a result, a charge corresponding to the positive analog input voltage VIP accumulates in the capacitors C P21 , C P22 , C P23 , C P24 , and C P25  of the positive 2-bit DAC  35 , and a charge corresponding to the negative analog input voltage VIM accumulates in the capacitors C M21 , C M22 , C M23 , C M24 , and C M25  of the negative 2-bit DAC  36 . In the trial phase, the signals S L1  and S L0  are controlled to be on/off inversely from the signals S H1  and S H0  respectively. Therefore, the switches S L1  and S L0  are controlled to be on/off inversely from the switches S H1  and S H0  respectively. 
         [0118]    As can be seen from  FIGS. 10 and 11 , the positive 2-bit DAC  35  and negative 2-bit DAC  36  are controlled symmetrically by respectively inputting the same signals S H1 , S H0 , S L1 , and S L0 . 
         [0119]      FIG. 12  illustrates an example of digital output by the successive approximation ADC  30  of  FIG. 9 . In this case, as an example of single end signals,  FIG. 12  illustrates the digital output D out  that is output in accordance with the value of the positive analog input voltage VIP when the high-voltage reference voltage VRH is 8 V, the low-voltage reference voltage VRL is 0 V, and the negative analog input voltage VIM is fixed at VRH/2.  FIG. 12  illustrates the results for when the value of the positive analog input voltage VIP is 1 V, 3 V, 5 V, and 7 V. 
         [0120]    In  FIG. 12 , the positive analog output voltage VOP and the negative analog output voltage VOM are calculated by Equations (1) and (2) below, which are derived from the law of conservation of charge. 
         [0000]        VOP=VRH/ 2− VIP +(⅛)* VRH *(2* S   H1   +S   H0 +2)  (1)
 
         [0000]        VOM=VRH/ 2− VIM +(⅛)* VRH *(2* S   L1   +S   L0 +2)  (2)
 
         [0121]    In  FIG. 12 , the signals D 1  and D 0  are the comparison signal CMP in the first bit trial and the second bit trial respectively. 
         [0122]    As illustrated in  FIG. 12 , when the positive analog input voltage VIP is 1 V, 3 V, 5 V, and 7 V, then based on the signals D 1  and D 0  output by the first bit trial and the second bit trial, D out  takes the values of 0, 1, 2, and 3 respectively. In this way, the 2-bit successive approximation ADC  30  converts an analog signal to 2-bit digital output. 
         [0123]      FIG. 13  is a functional block diagram illustrating an example of a 3-bit successive approximation ADC according to Embodiment 2. A 3-bit successive approximation ADC  40  includes a decoder  41 , a differential 3-bit DAC  42 , a comparator  43 , and a SAR  44  and operates with single end signals. The functions of the decoder  41 , differential 3-bit DAC  42 , comparator  43 , and SAR  44  are similar to those of the decoder  11 , differential 4-bit DAC  12 , comparator  13 , and SAR  14  of Embodiment 1, and therefore a description thereof is omitted. The differential 3-bit DAC  42 , however, differs from the differential 4-bit DAC  12  by outputting analog output voltage with 3-bit resolution. 
         [0124]    In addition to the control signals for successive approximation processing IN 0  and IN 1  and the signal S A  described in the SAR  34 , the SAR  44  outputs a signal CTL. The signal CTL is an input signal for controlling the positive 3-bit DAC and the negative 3-bit DAC asymmetrically during the last bit trial. Accordingly, when performing the last bit trial, the signal CTL is output from the SAR  44  to the decoder  41 . 
         [0125]    Based on the signals IN 0 , IN 1 , and CTL input from the SAR  44 , the decoder  41  generates signals S HP1 , S HP0 , S HPC , S LP1 , S LP0 , S LPC , S HM1 , S HM0 , S LM1 , and S LM0  and outputs the generated signals to the differential 3-bit DAC  42 . The signals S HP1 , S HP0 , S HPC , S LP1 , S LP0 , S LPC , S HM1 , S HM0 , S LM1 , and S LM0  are signals for performing on/off control of the respective switches S HP1 , S HP0 , S HPC , S LP1 , S LP0 , S LPC , S HM1 , S HM0 , S LM1 , and S LM0  illustrated in  FIG. 14 . 
         [0126]    The signals S A , S A ′, S HP1 , S HP0 , S HPC , S LP1 , S LP0 , S LPC , S HM1 , S HM0 , S LM1 , and S LM0  are each output as either “1” indicating “on” or “0” indicating “off”. The signals S A  and S A ′ perform mutually inverse on/off control. The digital signal output from the 3-bit successive approximation ADC  40  is referred to as D out . 
         [0127]      FIG. 14  illustrates an example of the circuit structure of the differential 3-bit DAC  42  of  FIG. 13 . As illustrated in  FIG. 14 , the differential 3-bit DAC  42  includes a positive 3-bit DAC  45  and a negative 3-bit DAC  46 . The positive 3-bit DAC  45  and the negative 3-bit DAC  46  each include five capacitors as passive components. In other words, the positive 3-bit DAC  45  and the negative 3-bit DAC  46  in this embodiment are structured with the same number of passive components as the positive 2-bit DAC  35  and negative 2-bit DAC  36  illustrated in  FIG. 10 . 
         [0128]    In  FIG. 14 , the capacitors C P31 , C P32 , C P33 , C P34 , and C P35  in the positive 3-bit DAC  45  respectively have capacitances of C, C, 2C, 2C, and 2C. The capacitors C M31 , C M32 , C M33 , C M34 , and C M35  in the negative 3-bit DAC  46  respectively have capacitances of C, C, 2C, 2C, and 2C. 
         [0129]    In the positive 3-bit DAC  45 , the capacitor C P31  is connected to the positive analog input voltage VIP and the low-voltage reference voltage VRL respectively via the switches S A  and S LPC . The capacitor C P31  is further connected to the high-voltage reference voltage VRH via the switch S HPC . The capacitor C P32  is connected in parallel to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL respectively via the switches S A , S HP0 , and S LP0 . The capacitor C P33  is connected in parallel to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL respectively via the switches S A , S HP1 , and S LP1 . 
         [0130]    The capacitors C P34  and C P35  are connected to the positive analog input voltage VIP via respective switches S A . The capacitor C P34  is connected to the high-voltage reference voltage VRH via the switch S A ′, and the capacitor C P35  is connected to the low-voltage reference voltage VRL via the switch S A ′. The capacitors C P31 , C P32 , C P33 , C P34 , and C P35  are connected to a common voltage of the comparator input via the switch S A . The common voltage is fixed at VRH/2. 
         [0131]    In the negative 3-bit DAC  46 , the capacitor C M31  is connected to the negative analog input voltage VIM and the high-voltage reference voltage VRH respectively via the switches S A  and S A ′. The capacitor C M32  is connected in parallel to the negative analog input voltage VIM, the low-voltage reference voltage VRL, and the high-voltage reference voltage VRH respectively via the switches S A , S HM0 , and S LM0 . The capacitor C M33  is connected in parallel to the negative analog input voltage VIM, the low-voltage reference voltage VRL, and the high-voltage reference voltage VRH respectively via the switches S A , S HM1 , and S LM1 . 
         [0132]    The capacitors C M34  and C M35  are connected to the negative analog input voltage VIM via respective switches S A . The capacitor C M34  is connected to the low-voltage reference voltage VRL via the switch S A ′, and the capacitor C M35  is connected to the high-voltage reference voltage VRH via the switch S A ′. The capacitors C M31 , C M32 , C M33 , C M34 , and C M35  are connected to the fixed voltage VRH/2 via the switch S A . 
         [0133]    In the differential 3-bit DAC  42 , the capacitors C P34 , C P35 , C M34 , and C M35  are provided in order to match the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM, which are single end signals, to the differential voltage between the high-voltage reference voltage VRH and the low-voltage reference voltage VRL. In other words, with the capacitors C P34 , C P35 , C M34 , and C M35 , even when the input voltage is a single end signal, the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM becomes the same differential voltage as when the input voltage is a differential signal. Therefore, the resolution in the differential 3-bit DAC  42  can be maintained without any reduction. 
         [0134]    Next, with reference to  FIGS. 15 and 16 , an example of each signal and of digital output in the 3-bit successive approximation ADC  40  is described. In  FIGS. 15 and 16 , the logic level of the signals IN 0 , IN 1 , and CMP is indicated as “0” or “1”. 
         [0135]      FIG. 15  illustrates signals input into the differential 3-bit DAC  42  of  FIG. 13 . In  FIG. 15 , the on/off states of the signals S A , IN 1 , IN 0 , CTL, S HP1 , S HP0 , S HPC , S LP1 , S LP0 , S LPC , S HM1 , S HM0 , S LM1 , and S LM0  in the sampling phase and the trial phase are indicated in table form. As illustrated in  FIG. 15 , in the sampling phase, only the signal S A  is on, i.e. the switches S A  in  FIG. 14  are on. As a result, a charge corresponding to the positive analog input voltage VIP accumulates in the capacitors C P31 , C P32 , C P33 , C P34 , and C P35  of the positive 3-bit DAC  45 , and a charge corresponding to the negative analog input voltage VIM accumulates in the capacitors C M31 , C M32 , C M33 , C M34 , and C M35  of the negative 3-bit DAC  46 . In the trial phase, the signals S LP1 , S LP0 , S LPC , S LM1 , and S LM0  are controlled to be on/off inversely from the signals S HP1 , S HP0 , S HPC , S HM1 , and S HM0  respectively. Therefore, the switches S LP1 , S LP0 , S LPC , S LM1 , and S LM0  are controlled to be on/off inversely from the switches S HP1 , S HP0 , S HPC , S HM1 , and S HM0  respectively. 
         [0136]    As can be seen from  FIGS. 14 and 15 , in the differential 3-bit DAC  42 , unlike the differential 2-bit DAC  32  described in  FIGS. 10 and 11 , different signals S HP1 , S HP0 , S HPC , S LP1 , S LP0 , S LPC , S HM1 , S HM0 , S LM1 , and S LM0  are input into the positive 3-bit DAC  45  and negative 3-bit DAC  46 . As a result, the positive 3-bit DAC  45  and negative 3-bit DAC  46  are controlled individually. 
         [0137]    As can be seen from  FIG. 15 , in the case that the signals IN 1  and IN 0  are both “0”, if the signal CTL is “0”, then the signals S HP1  and S HP0  are both “0”, whereas if the signal CTL is “1”, then the signal S HP1  is “0” and the signal S HP0  is “1”. In the case that the signal IN 1  is “0” and the signal IN 0  is “1”, if the signal CTL is “0”, then the signal S HP1  is “0” and the signal S HP0  is “1”, whereas if the signal CTL is “1”, then the signal S HP1  is “1” and the signal S HP0  is “0”. In the case that the signal IN 1  is “1” and the signal IN 0  is “0”, if the signal CTL is “0”, then the signal S HP1  is “1” and the signal S HP0  is “0”, whereas if the signal CTL is “1”, then the signal S HP1  and the signal S HP0  are both “1”. In the case that the signals IN 1  and IN 0  are both “1”, the signals S HP1  and S HP0  are both “1”. However, if the signal CTL is “0”, then the signal S HPC  is “0”, whereas if the signal CTL is “1”, then the signal S HPC  is “1”. 
         [0138]      FIG. 16  illustrates an example of digital output by the successive approximation ADC  40  of  FIG. 13 . Here, it is assumed that the high-voltage reference voltage VRH is 8 V and the low-voltage reference voltage VRL is 0 V.  FIG. 16  illustrates the digital output D out  that is output in accordance with the value of the positive analog input voltage VIP in the case that the negative analog input voltage VIM is a fixed value. In this case,  FIG. 16  illustrates the results for when the negative analog input voltage VIM is VRH/2.  FIG. 16  also illustrates the results for when voltages in 1 V increments from 0.5 V to 7.5 V are input as the value of the positive analog input voltage VIP. 
         [0139]    In  FIG. 16 , the positive analog output voltage VOP and the negative analog output voltage VOM are calculated by Equations (3) and (4) below, which are derived from the law of conservation of charge. 
         [0000]        VOP=VRH/ 2− VIP +(⅛)* VRH *(2* S   HP1   +S   HP0   +S   HPC +2)  (3)
 
         [0000]        VOM=VRH/ 2− VIM +(⅛)* VRH *(2* S   LM1   +S   LM0 +2)  (4)
 
         [0140]    In  FIG. 16 , the signals D 2 , D 1 , and D 0  are the comparison signal CMP in the first bit trial, second bit trial, and last bit trial respectively. In the last bit trial, the signal CTL is “1”. 
         [0141]    As illustrated in  FIG. 16 , D out  is output at eight levels from 0 to 7 based on the signals D 2 , D 1 , and D 0  output by the first bit trial, second bit trial, and last bit trial in accordance with the value of the positive analog input voltage VIP. In this way, as compared to the 2-bit successive approximation ADC  30 , the 3-bit successive approximation ADC  40  can increase resolution by one bit with a simple structure that only adds one switch S HPC , without increasing the number of passive components. 
       Embodiment 3 
       [0142]    While the differential DACs in Embodiment 1 and Embodiment 2 (differential 4-bit DAC  12  and differential 3-bit DAC  32 ) have been described as including capacitors as passive components, the passive components in the differential DAC are not limited to capacitors. The passive components in the differential DAC may be configured using resistors. The passive components in the differential DAC may also be configured using a combination of resistors and capacitors. An example of configuring a differential DAC using a combination of resistors and capacitors is described as Embodiment 3. 
         [0143]      FIG. 17  illustrates an example of a successive approximation ADC related to this embodiment, namely a 3-bit successive approximation ADC that includes differential 3-bit DACs configured using a combination of resistors and capacitors as passive components. The 3-bit successive approximation ADC  50  illustrated in  FIG. 17  includes a decoder  51 , a differential 3-bit DAC  52 , a comparator  53 , and a SAR  54 . The functions of the decoder  51 , comparator  53 , and SAR  54  are similar to those of the decoder  11 , comparator  13 , and SAR  14  of Embodiment 1, and therefore a description thereof is omitted. 
         [0144]    As illustrated in  FIG. 17 , the differential 3-bit DAC  52  includes a 1-bit capacitive DAC  55  and a 2-bit resistive DAC  56 . The differential 3-bit DAC  52  outputs analog output voltage with a total of 3-bit resolution using the 1-bit capacitive DAC  55  and the 2-bit resistive DAC  56 . 
         [0145]    The SAR  54  generates IN 0 , IN 1 , and IN 2  as control signals for successive approximation processing and outputs the generated control signals for successive approximation processing to the decoder  51 . The SAR  54  generates a signal S A  and outputs the generated signal S A  to the differential 3-bit DAC  52 . 
         [0146]    Based on the signals IN 0 , IN 1 , and IN 2  input from the SAR  54 , the decoder  51  generates signals S H  and S L , outputting the generated signals S H  and S L  to the 1-bit capacitive DAC  55 , and also generates signals S R0 , S R1 , S R2 , and S R3 , outputting the generated signals S R0 , S R1 , S R2 , and S R3  to the 2-bit resistive DAC  56 . The signals S H , S L , S R0 , S R1 , S R2 , and S R3  are signals for performing on/off control of the respective switches S H , S L , S R0 , S R1 , S R2 , and S R3  illustrated in  FIG. 18 . The signals S H , S L , S R0 , S R1 , S R2 , and S R3  are each output as either “1” indicating “on” or “0” indicating “off”. 
         [0147]      FIG. 18  illustrates an example of the circuit structure of the differential 3-bit DAC  52  of  FIG. 17 . As illustrated in  FIG. 18 , the 2-bit resistive DAC  56  includes a resistor string  57  with four resistors R connected in series as passive components. The high-voltage reference voltage VRH is supplied from one end  57   a  of the resistor string  57 , and the low-voltage reference voltage VRL is supplied from the other end  57   b . The voltage between resistors R is set to V 3 , V 2 , and V 1  in order from the end  57   a  at which the high-voltage reference voltage VRH is supplied. 
         [0148]    In the resistor string  57 , a switch S R0  is connected to the end  57   a , and in order from the end  57   a , switches S R1 , S R2 , and S R3  are connected between the resistors R. In other words, in the resistor string  57 , the switch S R1  is connected to the node of the voltage V 3 , the switch S R2  is connected to the node of the voltage V 2 , and the switch S R3  is connected to the node of the voltage V 1 . These switches S R0 , S R1 , S R2 , and S R3  are connected in parallel, and a negative reference voltage VRM is output from the other side of these switches that is not connected to the resistor string  57 . 
         [0149]    In the resistor string  57 , a switch S R0  is connected to the other end  57   b , and in order from the other end  57   b , switches S R1 , S R2 , and S R3  are connected between the resistors R. In other words, in the resistor string  57 , the switch S R1  is connected to the node of the voltage V 1 , the switch S R2  is connected to the node of the voltage V 2 , and the switch S R3  is connected to the node of the voltage V 3 . These switches S R0 , S R1 , S R2 , and S R3  are connected in parallel, and a positive reference voltage VRP is output from the other side of these switches that is not connected to the resistor string  57 . 
         [0150]    The 1-bit capacitive DAC  55  includes a positive 1-bit DAC  58  and a negative 1-bit DAC  59 . The positive 1-bit DAC  58  and the negative 1-bit DAC  59  each include four capacitors as passive components. For example, the capacitors C P41 , C P42 , C P43 , and C P44  are disposed in the positive 1-bit DAC  58 , and the capacitors C M41 , C M42 , C M43 , and C M44  are disposed in the negative 1-bit DAC  59 . 
         [0151]    In the positive 1-bit DAC  58 , the capacitor C P41  is connected to the positive analog input voltage VIP via the switch S A . The capacitor C P41  is also connected to the positive reference voltage VRP output by the 2-bit resistive DAC  56  via the switch S A ′. The capacitor C P42  is connected to the positive analog input voltage VIP, the high-voltage reference voltage VRH, and the low-voltage reference voltage VRL respectively via the switches S A , S H , and S L . 
         [0152]    The capacitors C P43  and C P44  are connected to the positive analog input voltage VIP via respective switches S A . The capacitor C P43  is connected to the high-voltage reference voltage VRH via the switch S A ′, and the capacitor C P44  is connected to the low-voltage reference voltage VRL via the switch S A ′. The capacitors C P41 , C P42 , C P43 , and C P44  are connected to the output voltage V 2  of the 2-bit resistive DAC  56  via the switch S A . 
         [0153]    In the negative 1-bit DAC  59 , the capacitor C M41  is connected to the negative analog input voltage VIM via the switch S A . The capacitor C M41  is also connected to the negative reference voltage VRM output by the 2-bit resistive DAC  56  via the switch S A ′. The capacitor C M42  is connected to the negative analog input voltage VIM, the low-voltage reference voltage VRL, and the high-voltage reference voltage VRH respectively via the switches S A , S H , and S L . 
         [0154]    The capacitors C M43  and C M44  are connected to the negative analog input voltage VIM via respective switches S A . The capacitor C M43  is connected to the high-voltage reference voltage VRH via the switch S A ′, and the capacitor C M44  is connected to the low-voltage reference voltage VRL via the switch S A ′. The capacitors C M41 , C M42 , C M43 , and C M44  are connected to the node of the output voltage V 2  of the 2-bit resistive DAC  56  via the switch S A . 
         [0155]    In the differential 3-bit DAC  52 , the capacitors C P43 , C P44 , C M43 , and C M44  are provided in order to match the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM, which are single end signals, to the differential voltage between the high-voltage reference voltage VRH and the low-voltage reference voltage VRL. In other words, with the capacitors C P43 , C P44 , C M43 , and C M44 , even when the input voltage is a single end signal, the differential voltage between the positive analog input voltage VIP and the negative analog input voltage VIM becomes the same differential voltage as when the input voltage is a differential signal. Therefore, the resolution in the differential 3-bit DAC  52  can be maintained without any reduction. 
         [0156]    In the differential 3-bit DAC  52 , the switches are controlled based on the signals input from the decoder  51 , and the positive analog output voltage VOP and negative analog output voltage VOM with a total of 3-bit resolution are output. 
         [0157]    The differential 3-bit DAC  52  uses the same signals S R0 , S R1 , S R2 , and S R3  to control the circuit that outputs the positive reference voltage VRP and the negative reference voltage VRM. Therefore, synchronous control is executed in these circuits. 
         [0158]      FIG. 19  is a functional block diagram illustrating an example of a 4-bit successive approximation ADC according to Embodiment 3. The 4-bit successive approximation ADC  60  illustrated in  FIG. 19  includes a decoder  61 , a differential 4-bit DAC  62 , a comparator  63 , and a SAR  64 . The functions of the decoder  61 , comparator  63 , and SAR  64  are similar to those of the decoder  11 , comparator  13 , and SAR  14  of Embodiment 1, and therefore a description thereof is omitted. 
         [0159]    As illustrated in  FIG. 19 , the differential 4-bit DAC  62  includes a 1-bit capacitive DAC  65  and a 3-bit resistive DAC  66 . The differential 4-bit DAC  62  outputs analog output voltage with a total of 4-bit resolution using the 1-bit capacitive DAC  65  and the 3-bit resistive DAC  66 . 
         [0160]    The SAR  64  generates IN 0 , IN 1 , and IN 2  as control signals for successive approximation processing and outputs the generated control signals for successive approximation processing to the decoder  61 . The SAR  64  generates a signal S A  and outputs the generated signal S A  to the differential 4-bit DAC  62 . The SAR  64  also generates an input signal CTL for executing asynchronous control in the last bit trial and outputs the signal CTL to the decoder  61 . 
         [0161]    Based on the signals IN 0 , IN 1 , and IN 2  input from the SAR  64 , the decoder  61  generates signals S H  and S L , outputting the generated signals S H  and S L  to the 1-bit capacitive DAC  55 , and also generates signals S RP0 , S RP1 , S RP2 , S RP3 , S RP4 , S RM0 , S RM1 , S RM2 , and S RM3 , outputting the generated signals S RP0 , S RP1 , S RP2 , S RP3 , S RP4 , S RM0 , S RM1 , S RM2 , and S RM3  to the 3-bit resistive DAC  66 . The signals S RP0 , S RP1 , S RP2 , S RP3 , S RP4 , S RM0 , S RM1 , S RM2 , and S RM3  are signals for performing on/off control of the respective switches S RP0 , S RP1 , S RP2 , S RP3 , S RP4 , S RM0 , S RM1 , S RM2 , and S RM3  illustrated in  FIG. 20 . The signals S H , S L , S RP0 , S RP1 , S RP2 , S RP3 , S RP4 , S RM0 , S RM1 , S RM2 , and S RM3  are each output as either “1” indicating “on” or “0” indicating “off”. 
         [0162]      FIG. 20  illustrates an example of the circuit structure of the differential 4-bit DAC  62  of  FIG. 19 . As illustrated in  FIG. 20 , the 3-bit resistive DAC  66  includes a resistor string  67  with four resistors R connected in series as passive components. The high-voltage reference voltage VRH is supplied from one end  67   a  of the resistor string  67 , and the low-voltage reference voltage VRL is supplied from the other end  67   b . The voltage between resistors R is set to V 3 , V 2 , and V 1  in order from the end  67   a  at which the high-voltage reference voltage VRH is supplied. 
         [0163]    In the resistor string  67 , a switch S RM0  is connected to the end  67   a , and in order from the end  67   a , switches S RM1 , S RM2 , and S RM3  are connected between the resistors R. In other words, in the resistor string  67 , the switch S RM1  is connected to the node of the voltage V 3 , the switch S RM2  is connected to the node of the voltage V 2 , and the switch S RM3  is connected to the node of the voltage V 1 . These switches S RM0 , S RM1 , S RM2 , and S RM3  are connected in parallel, and a negative reference voltage VRM is output from the other side of these switches that is not connected to the resistor string  67 . 
         [0164]    In the resistor string  67 , a switch S RP0  is connected to the other end  67   b , and in order from the other end  67   b , switches S RP1 , S RP2 , S RP3 , and S RP4  are connected between the resistors R. In other words, in the resistor string  67 , the switch S RP1  is connected to the node of the voltage V 1 , the switch S RP2  is connected to the node of the voltage V 2 , the switch S RP3  is connected to the node of the voltage V 3 , and the switch S RP4  is connected to the node of the high-voltage reference voltage VRH. These switches S RP0 , S RP1 , S RP2 , S RP3 , and S RP4  are connected in parallel, and a positive reference voltage VRP is output from the other side of these switches that is not connected to the resistor string  67 . 
         [0165]    The 1-bit capacitive DAC  65  includes a positive 1-bit DAC  68  and a negative 1-bit DAC  69 . The structure of the 1-bit capacitive DAC  65  is similar to that of the above-described 1-bit capacitive DAC  55 , and therefore a description thereof is omitted. 
         [0166]    Next, with reference to  FIGS. 21 to 24 , an example of each signal and of digital output in the 4-bit successive approximation ADC  60  is described. 
         [0167]      FIG. 21  illustrates signals input into the 1-bit capacitive DAC  65  of  FIG. 19 . In  FIG. 21 , the on/off states of the signals S A , S H , and S L  and the logic level of the signal IN 2  in the sampling phase and the trial phase are indicated in table form. As illustrated in  FIG. 21 , in the sampling phase, the signal S A  is on, i.e. the switches S A  in  FIG. 20  are on. As a result, a charge corresponding to the positive analog input voltage VIP accumulates in the capacitors C P51 , C P52 , C P53 , and C P54  of the positive 1-bit DAC  68 , and a charge corresponding to the negative analog input voltage VIM accumulates in the capacitors C M51 , C M52 , C M53 , and C M54  of the negative 1-bit DAC  69 . 
         [0168]      FIG. 22  illustrates signals input to and output from the 3-bit resistive DAC of  FIG. 19 . Here, it is assumed that the high-voltage reference voltage VRH is 16 V, the low-voltage reference voltage VRL is 0 V, the voltage V 3  is 12 V, the voltage V 2  is 8 V, and the voltage V 1  is 4 V. In  FIG. 22 , the signals IN 1 , IN 0 , and CTL input into the decoder  61 , the signals S RP0 , S RP1 , S RP2 , S RP3 , S RP4 , S RM0 , S RM1 , S RM2 , and S RM3  output by the decoder  61  to the 3-bit resistive DAC  66  based on the signals IN 1 , IN 0 , and CTL, and the positive reference voltage VRP and negative reference voltage VRM output by the 3-bit resistive DAC  66  are indicated in table form. 
         [0169]    As illustrated in  FIG. 22 , the signals S RM0 , S RM1 , S RM2 , and S RM3  do not change regardless of whether the signal CTL is “0” or “1”. Therefore, the switches S RM0 , S RM1 , S RM2 , and S RM3  perform the same on/off operations, regardless of whether the last bit trial is being performed. Conversely, when the signal CTL is “1”, the on/off state of the signals S RP0 , S RP1 , S RP2 , S RP3 , and S RP4  changes as compared to when the signal CTL is “0”. Therefore, the on/off operations of the switches S RP0 , S RP1 , S RP2 , S RP3 , and S RP4  change between when the signal CTL is “1” and when the signal CTL is “0”. In this way, the 3-bit resistive DAC  66  achieves asymmetrical control during the last bit test. 
         [0170]    By performing asymmetrical control, the 3-bit resistive DAC  66  can output the positive reference voltage VRP and the negative reference voltage VRM with 3-bit resolution. In this way, the differential 4-bit DAC  62  outputs analog voltage with 4-bit resolution. 
         [0171]      FIG. 23  illustrates an example of digital output by the successive approximation ADC  60  of  FIG. 19 .  FIG. 23  illustrates the digital output D out  in the case of a single end signal being input into the differential 4-bit DAC  62 . In other words, the negative analog input voltage VIM is V 2  (8 V).  FIG. 23  illustrates the results for when voltages in 1 V increments from 0.5 V to 15.5 V are input as the value of the positive analog input voltage VIP. 
         [0172]    In  FIG. 23 , the positive analog output voltage VOP and the negative analog output voltage VOM are calculated by Equations (5) and (6) below, which are derived from the law of conservation of charge. 
         [0000]        VOP=VRH/ 2− VIP +(¼)*( VRP+VRH *( S   H +1))  (5)
 
         [0000]        VOM=VRH/ 2− VIM +(¼)*( VRM+VRH *( S   L +1))  (6)
 
         [0173]    In  FIG. 23 , the signals D 3 , D 2 , D 1 , and D 0  are the comparison signal CMP in the first bit trial, second bit trial, third bit trial, and last bit trial respectively. In the last bit trial, the signal CTL is “1”. 
         [0174]      FIG. 24  illustrates another example of digital output by the successive approximation ADC  60  of  FIG. 19 .  FIG. 24  illustrates the digital output D out  in the case of a differential signal being input into the differential 4-bit DAC  62 . Letting the difference between the positive analog input voltage VIP and the negative analog input voltage VIM be ΔVI,  FIG. 23  illustrates the results for when voltages in 1 V increments from −7.5 V to 7.5 V are input as ΔVI. 
         [0175]    As illustrated in  FIGS. 23 and 24 , D out  is output at 16 levels from 0 to 15 based on the signals D 3 , D 2 , D 1 , and D 0  output by the first bit trial, second bit trial, third bit trial, and last bit trial. In this way, as compared to the 3-bit successive approximation ADC  50 , the 4-bit successive approximation ADC  60  can increase resolution by one bit with a simple structure that only adds one switch S RP4 , without increasing the number of passive components. 
         [0176]    Although embodiments have been described based on examples and on the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art based on this disclosure. Therefore, such changes and modifications are to be understood as included within the scope of this disclosure. For example, the functions and the like included in the components may be reordered in any logically coherent way. Furthermore, units, steps, and the like may be combined into one or divided, and/or additional units, steps and the like may be used within the scope of this disclosure. 
         [0177]    For example, whereas only the positive side is controlled in the last bit trial in the above embodiments, control of the last bit trial is not limited in this way. For example, the effects of this disclosure can be obtained by controlling only the negative side in the last bit trial. In another example, the effects of this disclosure may be obtained by alternating control between the positive side and the negative side of the last bit trial in different/subsequent conversion operations, where such alternating control may be based on a bit (e.g., stored in a register) that is set by an outside control signal provided to the SAR. 
         [0178]    For example, in Embodiments 1 to 3, a successive approximation ADC that includes a differential DAC (differential 4-bit DAC  12 , differential 3-bit DAC  42 , and differential 4-bit DAC  62 ) and a comparator (comparator  13 ,  43 , and  63 ) has been described, but this disclosure is not limited to these examples. For example, instead of the differential DAC and comparator, this disclosure may be applied to a configuration with a parallel (flash) ADC that includes a differential comparator circuit. 
         [0179]      FIG. 25  illustrates an example of the circuit structure of a differential comparator circuit provided in a flash ADC according to this disclosure. The differential comparator circuit includes a capacitor C P  connected to the positive input terminal and a capacitor C M  connected to the negative input terminal of a comparator  73 . An input common voltage VCM is connected to the positive and negative input terminals of the comparator  73  via respective switches S A . 
         [0180]    The capacitor C P  is connected to a positive analog input voltage VIP and a positive reference voltage VRP respectively via the switches S A  and S R . The capacitor C M  is connected to a negative analog input voltage VIM, a first negative reference voltage VRM 1 , and a second negative reference voltage VRM 2  respectively via the switches S A , S R1 , and S R2 . These switches S A , S R , S R1 , and S R2  are controlled to be on/off based on signals provided from the decoder. By including a plurality (for example, 2 N  (N being an integer greater than or equal to one)) of the differential comparator circuits illustrated in  FIG. 25  the flash ADC according to this disclosure converts an analog signal into a digital signal with (N+1)-bit resolution. 
         [0181]      FIG. 26  illustrates an example of the control state of each switch in the differential comparator circuit illustrated in  FIG. 25 . In  FIG. 26 , the “on” and “off” states of each switch are illustrated respectively as “1” and “0”. The differential comparator circuit performs analog-digital conversion in three steps: sampling, coarse control, and fine control. 
         [0182]    As illustrated in  FIG. 26 , during sampling, the switches S A  are on, and a charge accumulates in the capacitors C P  and C M . Next, during coarse ADC processing, the switch S R  on the positive side and the switch S R1  on the negative side turn on. During fine ADC processing, the switch S R  on the positive side remains on, while on the negative side, the switch S R1  turns off, and the switch S R2  turns on. In other words, in the coarse ADC processing and fine ADC processing, only the reference voltage supplied to the capacitor C M  on the negative side changes. In a typical differential comparator circuit, as compared to the differential comparator circuit illustrated in  FIG. 25 , since there is only one input of reference voltage on the negative side, symmetrical control is performed on the positive side and the negative side during ADC processing. By contrast, asymmetrical control is performed as described above in the differential comparator circuit provided with the flash ADC according to this disclosure. 
         [0183]      FIG. 27  illustrates an example of digital output by a 3-bit parallel ADC that includes four of the differential comparator circuits illustrated in  FIG. 25 .  FIG. 27  illustrates an example of the case in which the difference in potential between the positive reference voltage VRP and the first negative reference voltage VRM 1  is 8 V. In the 3-bit parallel ADC, coarse 2-bit ADC processing executed when the switch S R1  is on and fine 1-bit ADC processing executed when the switch S R2  is on are executed. 
         [0184]    In  FIG. 27 , the CMP# indicates the ID number of the four comparators included in the 3-bit parallel ADC. The four comparators are indicated below as CMP#1, CMP#2, CMP#3, and CMP#4. The positive analog input voltage VIP and negative analog input voltage VIM are input into the four comparators CMP#1, CMP#2, CMP#3, and CMP#4. 
         [0185]    In  FIG. 27 , ΔVIN is the differential voltage (analog input differential voltage) between the positive analog input voltage VIP and the negative analog input voltage VIM and is calculated as VIP−VIM. Furthermore, ΔVREF is the differential voltage (reference differential voltage) between the positive reference voltage VRP and either of the negative reference voltages VRM 1  or VRM 2  and is calculated as VRP−VRM 1  or VRP−VRM 2 . 
         [0186]    In the comparators CMP#1, CMP#2, CMP#3, and CMP#4, ΔVREF in the fine 1-bit ADC processing is increased by 2 V over the ΔVREF in the coarse 2-bit ADC processing. This difference is the difference between the first negative reference voltage VRM 1  and the second negative reference voltage VRM 2 . 
         [0187]    In  FIG. 27 , CMPO is the output logic of the comparator as a result of judging the magnitude relationship between ΔVIN and ΔVREF. In this example, when ΔVIN is greater than ΔVREF (ΔVIN&gt;ΔVREF), a “1” is output, whereas when ΔVIN is less than ΔVREF (ΔVIN&lt;ΔVREF), a “0” is output. 
         [0188]    During the coarse 2-bit ADC processing, a 2-bit analog-digital output result D out1  is calculated by converting a thermometer code, which is derived based on the output from the comparators CMP#1, CMP#2, CMP#3, and CMP#4, to a digital value. 
         [0189]    During the fine 1-bit ADC processing, a 1-bit analog-digital output result D out2  is calculated by converting a thermometer code, which is derived based on the output from the comparators CMP#1, CMP#2, CMP#3, and CMP#4, to a digital value. 
         [0190]    Based on the analog-digital output result D out1  and the analog-digital output result D out2 , the 3-bit parallel ADC calculates a 3-bit digital output D out . 
         [0191]    In this way, whereas an analog signal is converted to a digital signal with N-bit resolution by 2 N  (N=2 in the above example) comparators in a typical flash ADC, an analog signal is converted to an (N+1)-bit digital signal by 2 N  comparators in the flash ADC according to this disclosure.