Abstract:
A system and method for calculating an output value from a plurality of input sample values contributing to the output value in accordance with a respective weight value. A first intermediate value is interpolated for a first offset value from a first plurality of the input sample values and a second intermediate value is interpolated for a second offset value from a second plurality of the input sample values. The offset values are representative of the weight values of the input samples of the respective plurality of the input samples. The first and second intermediate values are combined to produce a resultant value which is subsequently blended with the remaining input sample values of the plurality in accordance with respective scaling values assigned to the resultant value and the remaining input sample values.

Description:
TECHNICAL FIELD  
       [0001]     The present invention is related generally to the field of computer graphics, and more particularly, a system and method for resampling graphics data of a source image to produce a destination image.  
       BACKGROUND OF THE INVENTION  
       [0002]     As visual output devices, such as computer monitors, printers, and the like, of various sizes and resolutions have been developed, and the demand for them have increased, the ability for a graphics processing system to resize and resample source images and create destination images to take advantage of the various sized and available resolutions of devices is a desirable operation. In an electronic display system, color at each pixel is typically represented by a set of color components, and each color component is represented by a sample value. Color components such as red, green, blue (RGB) or other representations such as YC b C r  are well known in the art. Whichever representation is chosen, each color component can be interpreted as a two dimensional array of samples, so three such arrays can represent images on display systems. Conceptually, resampling can be viewed as a spatial process, working on discrete input samples, represented by pixels of the source image arranged in a two-dimensional bitmap. The output samples of the destination image are spatially located at fractional sample positions within the input sample grid.  
         [0003]     The resulting destination image, however, should retain an acceptable image quality with respect to the source image. That is, the destination image should appear to retain similar visual qualities of the source image, such as having nearly the same color balance, contrast, and brightness as the original source image. Otherwise, rather than accurately reproducing a resized graphics image of the source image, the rescaling operation will compromise image quality by introducing image distortion. To this end, various interpolation and filtering circuits and methods have been developed in order to create high quality destination graphics images.  
         [0004]     In many conventional filtering algorithms where the resolution of a source image is reduced, a plurality of source samples are combined to yield a destination sample value. The method by which the source sample values are combined can be rather complicated. For example, the contribution of each of the source samples is typically weighted such that source samples that are more distant from the location of the destination relative to the position of the source samples contribute less to the resulting destination sample value. Moreover, the algorithm applied to combine the source sample values may include linear and non-linear models. Additionally, the number of source samples that are used in calculating the resulting destination value affects the quality of the resulting resized image.  
         [0005]     Implementation of these conventional filtering algorithms generally require additional circuitry to be included in the graphics processing system to facilitate the filtering operation. The space consumed by such additional circuitry may also depend on the number of source samples used in calculating the destination value, that is, the number of “taps” required to sample the source sample values. The more taps filter circuitry requires, the more complicated the circuitry becomes and the more space that is necessary to accommodate the circuitry. Although dedicated filtering circuitry improves processing throughput, where space is limited or miniature device size is desired, the inclusion of the additional dedicated filtering circuitry may not be an acceptable alternative. An alternative approach to implementing conventional multi-sample filtering algorithms is to include minimal additional dedicated filtering circuitry, but repeat certain processes through the same circuitry to yield a final output destination value. In effect, performance of the filtering operation requires multiple passes through the filtering circuitry. Although the space consumed by the circuitry is minimized, graphics processing throughput may suffer because of the bottleneck the multiple pass filtering process creates.  
         [0006]     Therefore, there is a need for an alternative system and method for implementing a multi-tap filter in a graphics processing system.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention relates to a system and method for calculating an output value from a plurality of input sample values. Each of the input sample values contributing to the output value according to a respective weight value. A first intermediate value is interpolated for a first offset value from a first plurality of the input sample values and a second intermediate value is interpolated for a second offset value from a second plurality of the input sample values. The offset values are representative of the weight values of the input samples of the respective plurality of the input samples. The first and second intermediate values are combined to produce a resultant value which is subsequently blended with the remaining input sample values of the plurality in accordance with respective scaling values assigned to the resultant value and the remaining input sample values. The 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is a block diagram of a computer system in which embodiments of the present invention are implemented.  
         [0009]      FIG. 2  is a block diagram of a graphics processing system in the computer system of  FIG. 1 .  
         [0010]      FIG. 3  is a block diagram of a portion of a pixel pipeline of the graphics processing system of  FIG. 2  according to an embodiment of the present invention.  
         [0011]      FIG. 4  is a block diagram of a bilinear filter stage of the pixel pipeline of  FIG. 3 .  
         [0012]      FIG. 5  is a block diagram of a combining stage of the pixel pipeline of  FIG. 3 .  
         [0013]      FIG. 6  is a block diagram of a blending stage of the pixel pipeline of  FIG. 3 .  
         [0014]      FIG. 7  is a flow diagram illustrating an embodiment of the present invention.  
         [0015]      FIG. 8  is a conceptual representation of a filtering application of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     Embodiments of the present invention provide a single-pass five-tap filter for generating an output sample value based on five input sample values applied with different weighting factors. Embodiments of the present invention can be implemented using existing processing stages of a graphics processing system, thus, reducing the need for additional processing circuitry to carry out the five-tap filtering process. Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.  
         [0017]      FIG. 1  illustrates a computer system  100  in which embodiments of the present invention are implemented. The computer system  100  includes a processor  104  coupled to a host memory  108  through a memory/bus interface  112 . The memory/bus interface  112  is coupled to an expansion bus  116 , such as an industry standard architecture (ISA) bus or a peripheral component interconnect (PCI) bus. The computer system  100  also includes one or more input devices  120 , such as a keypad or a mouse, coupled to the processor  104  through the expansion bus  116  and the memory/bus interface  112 . The input devices  120  allow an operator or an electronic device to input data to the computer system  100 . One or more output devices  120  are coupled to the processor  104  to provide output data generated by the processor  104 . The output devices  124  are coupled to the processor  104  through the expansion bus  116  and memory/bus interface  112 . Examples of output devices  124  include printers and a sound card driving audio speakers. One or more data storage devices  128  are coupled to the processor  104  through the memory/bus interface  112  and the expansion bus  116  to store data in, or retrieve data from, storage media (not shown). Examples of storage devices  128  and storage media include fixed disk drives, floppy disk drives, tape cassettes and compact-disc read-only memory drives.  
         [0018]     The computer system  100  further includes a graphics processing system  132  coupled to the processor  104  through the expansion bus  116  and memory/bus interface  112 . Optionally, the graphics processing system  132  may be coupled to the processor  104  and the host memory  108  through other types of architectures. For example, the graphics processing system  132  may be coupled through the memory/bus interface  112  and a high speed bus  136 , such as an accelerated graphics port (AGP), to provide the graphics processing system  132  with direct memory access (DMA) to the host memory  108 . That is, the high speed bus  136  and memory bus interface  112  allow the graphics processing system  132  to read and write host memory  108  without the intervention of the processor  104 . Thus, data may be transferred to, and from, the host memory  108  at transfer rates much greater than over the expansion bus  116 . A display  140  is coupled to the graphics processing system  132  to display graphics images. The display  140  may be any type of display, such as a cathode ray tube (CRT), a field emission display (FED), a liquid crystal display (LCD), or the like, which are commonly used for desktop computers, portable computers, and workstation or server applications.  
         [0019]      FIG. 2  illustrates circuitry included within the graphics processing system  132  for performing various three-dimensional (3D) graphics functions. It will be appreciated that the graphics processing system  132  illustrated in  FIG. 2  may include additional circuitry not specifically shown therein, and that the description is provided merely for the purposes of illustration. The following description of the particular functionality and operation of the graphics processing system  132  is not intended to limit the scope of the present invention to the specific embodiments discussed below. As shown in  FIG. 2 , a bus interface  200  couples the graphics processing system  132  to the expansion bus  116 . In the case where the graphics processing system  132  is coupled to the processor  104  and the host memory  108  through the high speed data bus  136  and the memory/bus interface  112 , the bus interface  200  will include a DMA controller (not shown) to coordinate transfer of data to and from the host memory  108  and the processor  104 . A graphics processor  204  is coupled to the bus interface  200  and is designed to perform various graphics and video processing functions, such as, but not limited to, generating vertex data and performing vertex transformations for polygon graphics primitives that are used to model 3D objects. The graphics processor  204  is coupled to a triangle engine  208 , which includes circuitry for performing various graphics functions, such as attribute transformations, calculating texel coordinates of a texture map, and rendering of graphics primitives.  
         [0020]     A pixel engine  212  is coupled to receive the graphics data generated by the triangle engine  208 . The pixel engine  212  contains circuitry for performing various graphics functions, such as, but not limited to, clipping, texture application or mapping, bilinear filtering, fog, blending, and color space conversion. The graphics functions are performed by a pixel processing pipeline  214  that is included in the pixel engine  212 .  
         [0021]     A memory controller  216  coupled to the pixel engine  212  and the graphics processor  204  handles memory requests to and from an local memory  220 . The local memory  220  stores graphics data, such as source pixel color values and destination pixel color values. A display controller  224  is coupled to the memory controller  216  to receive processed destination color values for pixels that are to be rendered. The destination color values are subsequently provided to a display driver  232  that includes circuitry to provide digital color signals, or convert digital color signals to red, green, and blue analog color signals, to drive the display  140  ( FIG. 1 ).  
         [0022]      FIG. 3  illustrates a portion of a pixel pipeline  300  that may be included in the pixel engine  212  ( FIG. 2 ). The pixel pipeline  300  includes a texture filtering unit  304 , a texture combine unit  308 , and a blending unit  312 . Pixel processing through the pixel pipeline  300  is made in a “single-pass.” That is, pixel attributes such as color and opacity, or alpha, values are calculated in a pipeline fashion, where processing begins with the texture filtering unit  304  and proceeds through the texture combine unit  308  and the blending unit  312  to produce output values of a pixel in a single-pass through the pipeline  300 . As will be explained in more detail below, in operation, the texture filtering unit  304 , texture combine unit  308 , and the blending unit  312  are used to implement a single-pass five-tap filter, unlike conventional five-tap filters that perform the filtering operation in multiple passes. The texture filtering unit  304 , texture combine unit  308  and the blending unit  312  will be described with respect to  FIGS. 3-6 , and will be followed by a description of a single-pass five-tap filtering operation implemented therein.  
         [0023]     The texture filter unit  304  performs filter functions on texture data. The texture filter unit  304  includes circuitry for performing filter functions for a plurality of textures. As briefly mentioned above, the triangle engine  208  provides the pixel engine  212  information such as pixel addresses and corresponding texel addresses. The texture filter unit  304  uses the information to generate attributes of a pixel, such as its color, opacity, and the like, through a filter process. One filtering method that may be used by the texture filtering unit  304  in calculating the attributes of a pixel is bilinear interpolation. As is well known in the art, bilinear interpolation applies a linear function in calculating a weighting value for each color of four adjacent texels C t0 -C t3  based on the “location” of the pixel relative to the four texels. The resulting pixel color C t  is the sum of the color values of the four source pixels, weighted by the appropriate weighting value. Bilinear interpolation, as well as conventional filtering methods that may be implemented in the texture filtering unit  304 , are well known in the art. Coupled to the texture filtering unit  304  to receive the calculated attributes for the pixels, such as color value C t  and opacity or alpha value A t  is the texture combine unit  308 . The texture combine unit  308  is capable of combining the color values received from the texture filtering unit with constant color and alpha values C c  and A c , or the attributes of other pixels having different textures applied to them. The resulting fragment attributes C f  and A f  are provided by the texture combine unit  308  to the blending unit  312 . The blending unit  312  performs blending operations, such as determining output color and alpha values C p  and A p  for pixels based on the opacity and color of two or more pixels that will be overlaid in the final image.  
         [0024]     It will be appreciated that the texture filtering unit  304 , the texture combine unit  308 , and the blending unit  312  may further perform other conventional graphics processing and operations in addition to those previously described. For example, the stages previously discussed may also perform operations to combine opacity values for pixels, mipmapping and dithering operations, as well as performing fog effect or level-or-detail calculations. Moreover, as previously mentioned,  FIG. 3  illustrates a portion of a pixel pipeline. It will be further appreciated that additional stages or circuitry may be included as well, such as cache memory for temporary storage of texture and pixel data, a lighting unit to perform lighting calculations, and the like. In the interest of brevity, a more detailed description has been omitted from herein.  
         [0025]     Shown in  FIG. 4  is a bilinear filter stage  400  that may be included in the texture filter unit  304  ( FIG. 3 ). The bilinear filter stage  400  includes a first bilinear filter stage  404  and a second bilinear filter stage  408 . Each bilinear filter stage can apply a different texture, namely a first texture C T0  and a second texture C T2 . Each filter stage performs a conventional bilinear interpolation operation from the four respective texel color values C t0 -C t3  to calculate a respective pixel color value C t . That is,
 
 C   t =Weight 0   ·C   t0 +Weight 1   ·C   t1 +Weight 2   ·C   t2 +Weight 3   ·C   t3 
 
 where
 
Weight 0 =(1 −rU )·(1 −rV ), Weight 1 =( rU )·(1 −rV ),
 
Weight 2 =(1 −rU )·( rV ), and Weight 3 =( rU )·( rV ),
 
 where rU and rV are the fractional coordinates of the pixel for which the pixel color value C t  is being calculated. 
 
         [0028]     Shown in  FIG. 5  are a texture pre-combine stage  504  and a texture post-combine stage  508  that are included in the texture combine unit  308  ( FIG. 3 ). Both the texture pre-combine stage  504  and the post-combine stage  508  perform pixel attribute combination operations. As illustrated in  FIG. 5 , the texture pre-combine stage  504  receives up to four different input color and alpha values C 0 -C 3  and A 0 -A 3 . The input values can be selected from several different values, for example, constant color and alpha values C c  and A c , a constant value such as zero, or the output of the bilinear filter stages  404  and  408  ( FIG. 4 ) C t0 , A t0  and C t1 , A t1 . Selection of the input values can be made programmatically. Although not shown in  FIG. 4 , it will be appreciated that the values from which the input values C 0 -C 3  can be selected may include other values as well.  
         [0029]     As mentioned previously, the texture pre-combine stage  504  can perform various pixel attribute combination operations to generate output values C op  and A op . Typical combine operations that the texture pre-combine stage  504  can perform include various Boolean logic operations, such as
 
C op =C0 AND C3, C op =C0 OR C3, and C op =C0 XOR C3,
 
 as well as more sophisticated combine operations, such as
 
 C   op   =C 0*( C 1 −C 2)+ C 3.
 
 Selection of the particular operation that is performed by the texture pre-combine stage  504  is made programmatically. 
 
         [0032]     The texture post-combine stage  508  receives the output values C op  and A op  from the texture pre-combine stage  504  and can perform a variety of additional operations to calculate output values C out  and A out  therefrom. Examples of the types of operations that can be performed by the texture post-combine stage  508  include: 
        no operation C out =C op       modulate 2× Cout=Cop&lt;&lt;1     demodulate 2× Cout=Cop&gt;&gt;1     sum Cout=Cr+Cg+Cb, RGB color components 
 
 As with the texture pre-combine stage  504 , the selection of the operation can be made programmatically. 
       
 
         [0038]      FIG. 6  illustrates blending stages  604 - 606  that are included in the blending unit  312 . The source blending stage  604  blends source color and alpha values C s  and A s  with destination color and alpha values C d  and A d , or constant color and alpha values C c  and A c  to produce blended output values C src  and A src . Similarly, the destination blending stage  605  blends the destination color and alpha values C d  and A d  with the source color and alpha values C s  and A s  or the constant color and alpha values C c  and A c  to produce blended output values C dst  and A dst . For example, with respect to the source blending stage  604 , some of the source blend operations that can be performed include:  
                                                       Operation   RGB   Alpha                           BlendDstColor   C s *C d     A s *A d             BlendDstAlpha   C s *A d     A s *A d             BlendSrcColor   C s *C s     A s *A s             BlendSrcAlpha   C s *A s     A s *A s             BlendConstColor   C s *C c     A s *A c             BlendConstAlpha   C s *A c     A s *A c             Blend0   0   0           Blend1   C s     A s                          
         [0039]     Similarly, the destination blending stage  605 , the destination blend operations can include:  
                                                       Operation   RGB   Alpha                           BlendSrcColor   C d *C s     A d *A s             BlendSrdAlpha   C d *A s     A d *A s             BlendDestColor   C d *C d     A d *A d             BlendDestAlpha   C d *A d     A d *A d             BlendConstColor   C d *C c     A d *A c             BlendConstAlpha   C d *A c     A d *A c             Blend0   0   0           Blend1   C d     A d                        
 
         [0040]     The final blend stage  606  receives the output C src , A src , C dst  and A dst  of the source and destination blending stages  604  and  605 , respectively, and performs a final blending operation to produce output color and alpha values C p  and A p . Examples of the types of final blending operations included are:
 
 C   p   =C   src   +C   dst ,
 
 C   p   =C   src   −C   dst , and 
 
 C   p   =C   dst   −C   src .
 
 The blending operations of the source and destination blending stages  604  and  605 , respectively, and the final blending stage  606  are selected programmatically. 
 
         [0042]     It will be appreciated that the various processing stages shown in and described with respect to  FIGS. 4-6  are conventional in design and functionality. Those of ordinary skill in the art have sufficient understanding to practice the present invention based on the description provided herein. For example, the programmability of the various processing stages and the selection of the particular values for processing is well known in the art. Consequently, in order to avoid unnecessarily obscuring the invention, further description has been omitted from herein. It will be further appreciated that the color values may consist of several different components. For example, the color value may represent pixel colors which are the combination of red, green, and blue color components. Another example includes color values representing pixel colors which are the combination of luma and chroma components. Consequently, because it is well understood in the art, although circuitry to perform graphics operation for each of the components is not expressly shown or described herein, embodiments of the present invention include circuitry, control signals, and the like necessary to perform processing on each component for multi-component color values.  
         [0043]     Operation of the single-pass five-tap filter will be described with respect to  FIGS. 7 and 8 . As mentioned previously, the five-tap filtering operation is performed in a single pass through the pixel pipeline  300  ( FIG. 3 ). The flow diagram of  FIG. 7  describes the single-pass process and  FIG. 8  illustrates a particular application of the single-pass process. In  FIG. 8   a , five scanlines A−2, A−1, A, A+1, and A+2 of pixels arranged in the manner shown, will be reduced to a single scanline A′ in a single-pass. The color values of the pixels of the scanlines A−2, A−1, A, A+1, and A+2 will contribute to the color value of the pixels of the final scanline A′ according to the weights 10%, 20%, 40%, 20%, and 10%, respectively. It will be appreciated that the scanlines are composed of individual pixels arranged in succession along the respective scanline. The five color samples C A−2 , C A−1 , C A , C A+1 , and C A+2  for the filtering process are taken from the location of a pixel from in each of the five scanlines where the pixels are aligned in a common column, such as pixels P A−2 , P A−1 , P A , P A+1 , and P A+2 . The result of the filter process is to provide a destination pixel P A ′ having a color value C A ′ that is the combination of the color values C A−2 , C A−1 , C A , C A+1 , and C A+2  of the five pixels sampled from each scanline. As the filtering process proceeds to subsequent pixels along each scanline, a destination scanline A′ will be generated.  
         [0044]     The five-tap filtering process begins with performing bilinear interpolation of a pixels P A−2  and P A−1  from scanlines A−2 and A−1, respectively (step  702 ,  FIG. 7 ). Note that the destination pixel P A ′ is aligned in the same column as the pixels P A−2  and P A−1 . That is, the fractional horizontal position rU with respect to the pixels P A−2  and P A−1  is zero, and consequently, the “bilinear” operation is reduced to a linear interpolation between the pixels P A−2  and P A−1 . Additionally, as shown in  FIG. 8   a , the contribution of scanlines A−2 and A−1 to the final scanline A′ are 10% and 20% respectively. By determining and providing appropriate coordinate values, a conventional bilinear filter stage can be used to perform the interpolation process of step  702 . For example, a vertical offset value V 0 , which is measured relative to the scanline A−2, is calculated and provided to the bilinear filter stage  404  ( FIG. 4 ) such that the contribution of the pixel P A−1  carries twice the weight of the contribution of the pixel P A−2  to the color value C A−1 ′ of an output pixel P A−1 ′. As mentioned previously, for the interpolation operation of step  702 , the fractional horizontal position is zero. Thus, the coordinates that are provided to the bilinear filter stage  404  are (0, 2/3), that is, the output pixel P A−1 ′ is in the same column as P A−1  and P A−2 , and the vertical offset V 0  from the scanline A−2 is equal to two-thirds. As a result, the bilinear interpolation equation reduces to (1/3 C A−1 +2/3 C A−2 ), and the output C t0  of the bilinear filter stage  404  is the color value C A−1 ′ for the pixel P A−1 ′.  
         [0045]     The pixels P A+1  and P A+2 , from scanlines A+1 and A+2, respectively, are also interpolated (step  704 ) in a manner similar to that previously described with respect to pixels P A−2  and P A−1 . However, the vertical offset V 1  for the interpolation of pixels P A+1  and P A+2  is adjusted such that when measured from the scanline A−2, the contribution of P A+1  is twice that of the contribution by P A+2  to the color value C A+1 ′ of an output pixel P A+1 ′. The horizontal offset is still zero. Thus, the coordinates that are provided to the bilinear filter stage  408  are (0, 3 1/3). As a result, the bilinear interpolation equation reduces to (2/3 P A+1 +1/3 P A+2 ) and the output C t1  of the bilinear filter stage  408  is the color value C A+1 ′ for P A+1 ′. Although interpolation steps  702  and  704  are shown in  FIG. 7 , and described with respect bilinear filter stages  404  and  408 , as being performed in parallel, it will be appreciated that the interpolation process may be performed sequentially instead.  
         [0046]     Following the interpolation of pixels P A−2  and P A−1 , and P A+1  and P A+2 , the two interpolated color values C A−1 ′ and C A+1 ′ for output pixels P A−1 ′ and P A+1 ′, respectively, are averaged (step  708 ). By programming the texture pre-combine stage  504  and a texture post-combine stage  508 , shown in  FIG. 5 , to perform the appropriate calculations on selected input values, the stages  504  and  508  can be used to perform the averaging operation of step  708 . That is, as mentioned previously, the texture pre-combine stage  504  can be programmed to calculate an output value C op  from the equation:
 
 C   op   =C 0*( C 1 −C 2)+ C 3,
 
 and the texture post-combine stage  508  can be programmed to perform a demodulate-by-two operation such that:
 
 C   out   =C   op &lt;&lt;1.
 
 By selecting the input values C0-C3 to the texture pre-combine stage  504  to be:
 
C0=C t0 , C1=C c =1, C 2 =0, and C 3 =C t1 ,
 
 the color values for the output pixels P A−1 ′ and P A+1 ′ are averaged, that is:
 
 C   out   =[C   t0 *(1−0)+ C   t1 ]&gt;&gt;1, or
 
 C   out   =[C   t0   +C   t1 ]&gt;&gt;1,
 
 where C out  is the averaged color value of C t0  and C t1 . 
 
         [0051]     The averaged color value C out  is then blended with the color value C A  of a pixel P A  (step  714 ), a pixel from the scanline A in the same column as pixels P A−2 , P A−1 , P A+1 , and P A+2 . The color values are alpha blended using alpha values programmed corresponding to the weights defined in  FIG. 8  (steps  710 ,  712 ). The alpha value A A  assigned to the pixel P A  is selected such that it corresponds to the 40% weight the color value C A  contributes to the output color value C A ′ of the output pixel P A ′. Accordingly, the alpha value A out  for the averaged color value C out  is assigned a value 60%, such that the total contribution of the C A ′ and C out  are equal to 100%.  
         [0052]     The blending operation is performed in the blending stages  604 - 606  ( FIG. 6 ). As previously discussed, the source blending stage  604  and the destination blending stage  605  can be programmed to perform a select blending operation with various input color and alpha values. The source blending stage  604  is programmed to perform the blending operation:
 
 C   src   =C   s   *A   c ,
 
 and the destination blending stage  605  is programmed to perform the blending operation:
 
 C   dst   =C   d   *C   c .
 
 The final blending stage  606  is programmed to perform a final blend operation:
 
 C   p   =C   ssrc   +C   dst .
 
         [0055]     A value is programmed for constant color and alpha values C c  and A c  such that the source and destination blending operations will weight the contribution of the color values C out  and C A  accordingly, when the final blend stage  606  blends C src  and C dst  to produce the color value C A ′ of the output pixel P A ′. That is, the effective alpha value A out  is equal to A c  and the effective alpha value A A  is equal to C c . Where actual percentage values cannot be programmed, it may be necessary to program equivalent values for A c  (=A out ) and C c  (=A A ), that are representative of the respective alpha percentages. For example, where a 32-bit number is used for C c  and A c , such that the eight most significant bits represent A c  and the 24 least significant bits represent C c , the appropriate value for a 40%/60% weighting is 99666666H. Thus, to have the blending stages  604 - 606  perform the blending operation of step  714 :
 
 C   s   =C   out   , C   d   =C   0   , A   c   ·C   c =99666666 H, 
 
 resulting in:
 
 C   p =( C   s   *A   c )+( C   d   *C   c ), or
 
 C   p =( C   s *60%)+( C   d *40%).
 
 The color value C p  is the final color value C A ′ for the output pixel P A ′. It can be shown, as follows, that the process previously described yields a color value having the correct weighting as defined in  FIG. 8   a .  
         C     A   ′       =         6   10     ·     [         (         1   3     ⁢     C     A   -   2         +       2   3     ⁢     C     A   -   1           )     +     (         2   3     ⁢     C     A   +   1         +       1   3     ⁢     C     A   +   2           )       2     ]       +       4   10     ⁢     C   A             
         C     A   ′       =         6   10     ·     [       (         1   6     ⁢     C     A   -   2         +       2   6     ⁢     C     A   -   1           )     +     (         2   6     ⁢     C     A   +   1         +       1   6     ⁢     C     A   +   2           )       ]       +       4   10     ⁢     C   A             
         C     A   ′       =         1   10     ⁢     C     A   -   2         +       2   10     ⁢     C     A   -   1         +       4   10     ⁢     C   A       +       2   10     ⁢     C     A   +   1         +       1   10     ⁢     C     A   +   2               
 
         [0058]     +It will be appreciated that the weights shown in  FIG. 8  and the corresponding values described with respect thereto are exemplary, and that other weights can be used as well. To accommodate different weights used in the single-pass five-tap filtering process may need to be adjusted. For example, the vertical offsets used in interpolating between pixels P A−2  and P A−1  and pixels P A+1  and P A+2  may need to be adjusted, as well as the constant color and alpha values C c  and A c  used in the blending operation.  
         [0059]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.