Abstract:
To solve a problem in that, even after a charge inhibition signal is input from an input terminal and a charge control transistor is turned OFF, if a load is connected between external terminals (EB+, EB−), a discharge current flows, and to solve another problem of power consumption of a charge/discharge control circuit ( 22 ), provided is a charge/discharge control circuit for controlling charge/discharge of a secondary battery, the charge/discharge control circuit including: a switch circuit for controlling a current that flows through the charge/discharge control circuit; a control circuit for controlling an operation of the switch circuit; and an input terminal to which a signal for controlling an operation of the charge/discharge control circuit is input from outside. In this way, when a signal is input to the input terminal from outside, the discharge current is interrupted, thereby reducing current consumption of the charge/discharge control circuit.

Description:
RELATED APPLICATIONS  
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2011-129398 filed on Jun. 9, 2011, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION  
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a charge/discharge control circuit for detecting a voltage and an abnormality of a secondary battery and to a battery device including the charge/discharge control circuit, and more particularly, to a charge/discharge control circuit, which is powered down in response to a signal input from an external terminal and to a battery device including the charge/discharge control circuit. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 3  illustrates a circuit diagram of a battery device including a conventional charge/discharge control circuit. The battery device including the conventional charge/discharge control circuit includes secondary batteries  1  to  4  (such as lithium ion secondary battery cells), a charge control transistor  14  and a discharge control transistor  16  each formed of an FET or the like, a charge/discharge control circuit  22 , a microcomputer  21 , and external terminals EB+ and EB−. 
         [0006]    In the secondary batteries  1  to  4 , a positive terminal of the secondary battery  1  is connected to the discharge control transistor  16 , and a negative terminal of the secondary battery  4  is connected to the external terminal EB−. The discharge control transistor  16  and the charge control transistor  14  are connected in series. The charge control transistor  14  is connected to the external terminal EB+. 
         [0007]    The charge control transistor  14  is a switch element for controlling charge to the secondary batteries  1  to  4  from a charger  20 . The discharge control transistor  16  is a switch element for controlling discharge from the secondary batteries  1  to  4  to a load  19 . When the charge/discharge control circuit  22  inhibits the charge to the secondary batteries  1  to  4 , the charge/discharge control circuit  22  turns OFF the charge control transistor  14 . When the charge/discharge control circuit  22  inhibits the discharge from the secondary batteries  1  to  4 , the charge/discharge control circuit  22  turns OFF the discharge control transistor  16 . 
         [0008]    When a charge inhibition signal is input to a CTL terminal  13 , the charge/discharge control circuit  22  turns OFF the charge control transistor  14  and turns ON the discharge control transistor  16 . Then, even when the charge inhibition signal is input to the CTL terminal  13 , if a VMP terminal  12  has an overcurrent detection voltage, the charge/discharge control circuit  22  cancels the charge inhibition signal of the CTL terminal  13 . 
         [0009]    In this way, in the case where the load  19  is connected between the external terminal EB+ and the external terminal EB−, even when the charge inhibition signal is input from the CTL terminal  13 , both the charge control transistor  14  and the discharge control transistor  16  are not turned OFF, and hence it is possible to prevent a lock mode in which a voltage cannot be supplied to the load  19  (see, for example, Japanese Patent Application Laid-open No. 2002-320324 (FIG. 1)). 
         [0010]    However, the conventional technology has a problem in that, when a charge inhibition signal is input from the CTL terminal  13  in order to prevent power consumption of the secondary battery at the time of shipment of the battery device, if a load is connected between the external terminal EB+ and the external terminal EB−, a discharge current flows via a parasitic diode  15 , resulting in power consumption of the secondary battery. Further, the conventional technology has another problem of power consumption of the charge/discharge control circuit  22 . 
       SUMMARY OF THE INVENTION  
       [0011]    The present invention has been made for solving the above-mentioned problems, and provides a charge/discharge control circuit capable of preventing power consumption of a secondary battery and reducing current consumption of a charge/discharge control circuit at the time of shipment of a battery device, and also provides a battery device including the charge/discharge control circuit. 
         [0012]    In order to solve the conventional problems, a charge/discharge control circuit according to an exemplary embodiment of the present invention has the following configuration. 
         [0013]    A charge/discharge control circuit for controlling charge/discharge of a secondary battery includes: a switch circuit for controlling a current that flows through the charge/discharge control circuit; a control circuit for controlling an operation of the switch circuit; and an input terminal to which a signal for controlling an operation of the charge/discharge control circuit is input from outside. 
         [0014]    According to the charge/discharge control circuit of the exemplary embodiment of the present invention, after a signal is input from the input terminal, a discharge control transistor is turned OFF to interrupt a discharge current flowing to an external load, to thereby power down the charge/discharge control circuit to reduce current consumption. Therefore, there is an effect that power consumption of the secondary battery can be prevented at the time of shipment of a battery device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0015]    In the accompanying drawings: 
           [0016]      FIG. 1  is a circuit diagram of a battery device including a charge/discharge control circuit according to a first embodiment of the present invention; 
           [0017]      FIG. 2  is a circuit diagram of a battery device including a charge/discharge control circuit according to a second embodiment of the present invention; and 
           [0018]      FIG. 3  is a circuit diagram of a battery device including a conventional charge/discharge control circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]      FIG. 1  is a circuit diagram of a battery device including a charge/discharge control circuit according to a first embodiment of the present invention. 
         [0020]    The battery device including the charge/discharge control circuit of the first embodiment includes a secondary battery  101 , resistors  102  and  104 , a capacitor  103 , external terminals  157  and  158  to which a charger  106  and a load  105  are to be connected, an N-channel discharge FET  107 , an N-channel charge FET  108 , and a charge/discharge control circuit  121 . The charge/discharge control circuit  121  includes a charge/discharge monitoring circuit  111 , a control circuit  113 , an external signal detection circuit  115 , switch circuits  112  and  114 , and terminals  151 ,  152 ,  153 ,  154 ,  156 , and  159 . 
         [0021]    A positive terminal of the secondary battery  101  is connected to one terminal of the resistor  102  and the external terminal  157 , and a negative terminal thereof is connected to one terminal of the capacitor  103 , the terminal  152  of the charge/discharge control circuit  121 , and a source of the N-channel discharge FET  107 . The other terminal of the resistor  102  is connected to the other terminal of the capacitor  103  and the terminal  151  of the charge/discharge control circuit  121 . The terminal  151  of the charge/discharge control circuit  121  is connected to one terminal of the switch circuit  112 , the control circuit  113 , and one terminal of the switch circuit  114 . The terminal  152  of the charge/discharge control circuit  121  is connected to the charge/discharge monitoring circuit  111 , the control circuit  113 , and the external signal detection circuit  115 . The other terminal of the switch circuit  112  is connected to the charge/discharge monitoring circuit  111 . The other terminal of the switch circuit  114  is connected to the external signal detection circuit  115 . The charge/discharge monitoring circuit  111  is connected to the control circuit  113  and the terminal  156 . The external signal detection circuit  115  is connected to the control circuit  113  and the terminal  159 . The control circuit  113  is connected to the terminal  153  and the terminal  154 , and outputs a control signal to the switch circuits  112  and  114 . A drain of the N-channel discharge FET  107  is connected to a drain of the N-channel charge FET  108 , and a gate of the N-channel discharge FET  107  is connected to the terminal  153 . A source of the N-channel charge FET  108  is connected to the external terminal  158  and a gate thereof is connected to the terminal  154 . One terminal of the resistor  104  is connected to the terminal  156  and the other terminal thereof is connected to the external terminal  158 . 
         [0022]    Next, the operation of the battery device including the charge/discharge control circuit of the first embodiment is described. 
         [0023]    When the secondary battery  101  is connected, the control circuit  113  outputs a signal to turn ON the switch circuit  112  and the switch circuit  114 , thereby enabling the charge/discharge monitoring circuit  111  and the external signal detection circuit  115 . When the charger  106  is connected between the external terminals  157  and  158  and when the secondary battery  101  becomes an overcharged state, the charge/discharge monitoring circuit  111  detects the overcharge and outputs an overcharge inhibition signal to the control circuit  113 . In response to the overcharge inhibition signal, the control circuit  113  outputs Lo to the terminal  154  to turn OFF the N-channel charge FET  108 , thereby providing protection. When the load  105  is connected between the external terminals  157  and  158  and when the secondary battery  101  becomes an overdischarged state, the charge/discharge monitoring circuit  111  detects the overdischarge and outputs an overdischarge inhibition signal to the control circuit  113 . In response to the overdischarge inhibition signal, the control circuit  113  outputs Lo to the terminal  153  to turn OFF the N-channel discharge FET  107 , thereby providing protection. When the external terminals  157  and  158  are short-circuited and when the secondary battery  101  becomes an overcurrent state, the charge/discharge monitoring circuit  111  detects an increase in voltage of the terminal  156  and outputs an overcurrent inhibition signal to the control circuit  113 . In response to the overcurrent inhibition signal, the control circuit  113  outputs Lo to the terminal  154  to turn OFF the N-channel charge FET  108 , thereby providing protection. 
         [0024]    When a signal is input to the terminal  159 , the external signal detection circuit  115  detects the signal and outputs an external signal detection signal to the control circuit  113 . In response to the external signal detection signal, the control circuit  113  outputs Lo to the terminal  153 , Hi to the terminal  154 , and a turn-OFF signal to the switch circuits  112  and  114 . In this manner, the N-channel discharge FET  107  is turned OFF and the N-channel charge FET  108  is turned ON so that the charge/discharge control circuit  121  becomes a power-down state in which the operations of the charge/discharge monitoring circuit  111  and the external signal detection circuit  115  are suspended. Thus, power consumption can be reduced. In order to release the power-down state, it is necessary to connect the charger  106  between the external terminals  157  and  158 . Therefore, through the input of a signal from the terminal  159  at the time of shipment of the battery device, a storage period of the secondary battery  101  can be prolonged. 
         [0025]    Note that, the switch circuits  112  and  114  are used to suspend the operations of the charge/discharge monitoring circuit  111  and the external signal detection circuit  115 , but those operations may be suspended by another method. 
         [0026]    As described above, according to the battery device including the charge/discharge control circuit of the first embodiment, through the input of a signal to the terminal  159 , the N-channel discharge FET  107  is turned OFF and the N-channel charge FET  108  is turned ON so that the charge/discharge control circuit  121  becomes the power-down state. Thus, power consumption can be reduced. Then, a signal is input from the terminal  159  at the time of shipment of the battery device. In this way, a storage period of the secondary battery  101  can be prolonged. 
         [0027]      FIG. 2  is a circuit diagram of a battery device including a charge/discharge control circuit  221  that includes an overcurrent protection circuit according to a second embodiment of the present invention. The difference from  FIG. 1  is that the N-channel discharge FET  107  is changed to a P-channel discharge FET  207  and the N-channel charge FET  108  is changed to a P-channel discharge FET  208 . 
         [0028]    Connections are described. The P-channel discharge FET  207  has a source connected to the positive terminal of the secondary battery  101 , a drain connected to a drain of the P-channel charge FET  208 , and a gate connected to the terminal  153 . The P-channel charge FET  208  has a source connected to the external terminal  157  and a gate connected to the terminal  154 . Other connections are the same as those in the first embodiment. 
         [0029]    Next, the operation of the battery device including the charge/discharge control circuit of the second embodiment is described. 
         [0030]    When the secondary battery  101  is connected, the control circuit  113  outputs a signal to turn ON the switch circuit  112  and the switch circuit  114 , thereby enabling the charge/discharge monitoring circuit  111  and the external signal detection circuit  115 . When the charger  106  is connected between the external terminals  157  and  158  and when the secondary battery  101  becomes an overcharged state, the charge/discharge monitoring circuit  111  detects the overcharge and outputs an overcharge inhibition signal to the control circuit  113 . In response to the overcharge inhibition signal, the control circuit  113  outputs Hi to the terminal  154  to turn OFF the P-channel charge FET  208 , thereby providing protection. When the load  105  is connected between the external terminals  157  and  158  and when the secondary battery  101  becomes an overdischarged state, the charge/discharge monitoring circuit  111  detects the overdischarge and outputs an overdischarge inhibition signal to the control circuit  113 . In response to the overdischarge inhibition signal, the control circuit  113  outputs Hi to the terminal  153  to turn OFF the P-channel discharge FET  207 , thereby providing protection. When the external terminals  157  and  158  are short-circuited and when the secondary battery  101  becomes an overcurrent state, the charge/discharge monitoring circuit  111  detects an increase in voltage of the terminal  156  and outputs an overcurrent inhibition signal to the control circuit  113 . In response to the overcurrent inhibition signal, the control circuit  113  outputs Hi to the terminal  154  to turn OFF the P-channel charge FET  208 , thereby providing protection. 
         [0031]    When a signal is input to the terminal  159 , the external signal detection circuit  115  detects the signal and outputs an external signal detection signal to the control circuit  113 . In response to the external signal detection signal, the control circuit  113  outputs Hi to the terminal  153 , Lo to the terminal  154 , and a turn-OFF signal to the switch circuits  112  and  114 . In this manner, the P-channel discharge FET  207  is turned OFF and the P-channel charge FET  208  is turned ON so that the charge/discharge control circuit  221  becomes a power-down state in which the operations of the charge/discharge monitoring circuit  111  and the external signal detection circuit  115  are suspended. Thus, power consumption can be reduced. In order to release the power-down state, it is necessary to connect the charger  106  between the external terminals  157  and  158 . Therefore, through the input of a signal from the terminal  159  at the time of shipment of the battery device, a storage period of the secondary battery  101  can be prolonged. 
         [0032]    Note that, the switch circuits  112  and  114  are used to suspend the operations of the charge/discharge monitoring circuit  111  and the external signal detection circuit  115 , but those operations may be suspended by another method. 
         [0033]    As described above, according to the battery device including the charge/discharge control circuit that includes the overcurrent protection circuit of the second embodiment, through the input of a signal to the terminal  159 , the P-channel discharge FET  207  is turned OFF and the P-channel charge FET  208  is turned ON so that the charge/discharge control circuit  221  becomes the power-down state. Thus, power consumption can be reduced. Then, a signal is input from the terminal  159  at the time of shipment of the battery device. In this way, a storage period of the secondary battery  101  can be prolonged.