Abstract:
A cascode amplifier circuit having substantial linearity, while maintaining other advantages of cascode amplifiers such as relatively high input-to-output isolation and relatively high gain. The cascode amplifier circuit also provides substantially matched impedance between input and output, at least within a selected frequency band, with the effect of providing a circuit that is well-suited for use in a communication system. The cascode amplifier circuit includes feedback loops, such as for example DC feedback loops and AC feedback loops, and bias optimization, with the effect of improving linearity, maintaining gain, minimizing return loss, and providing a relatively high dynamic range.

Description:
BACKGROUND 
     In RF communications, interference between differing carrier frequencies is undesirable, even when the information is coded in FM or more sophisticated systems such as CDMA, which are generally more immune to interference compared to classical AM systems. For instance, when using CDMA, different carrier frequencies are often spaced closely together, which can result in leakage of signals between carriers, which can corrupt the coding contained in the carrier. The carriers should be amplified before being transmitted at the power level dictated by the communication channel. In that process, interference can arise due to the non-linearity of RF power amplifiers. Nonlinearity can result in generation of harmonics of the carrier frequencies and can cause damaging intermodulation between carriers. This is demonstrated by the amplifier output voltage expressed by equation (1), showing it is composed by an amplification of input voltage, a 1 , plus additional (undesirable) components, a 2  and a 3 . Of these additional undesirable components, the most problematic is a 3 , which creates the so-called third order intermodulation component.
 
 V   out   =a   1   V   in   +a   2   V   in   2   +a   3   V   in   3 +  (1)
 
     A first value P out  represents a desired output signal for an amplifier, proportional to the input signal by an amplification constant a 1 , as described in equation (1) above. A second value IMD 3  represents an undesired signal contributed to an output of an amplifier proportional to the input signal by an third-order intermodulation component a 3 . A linearity parameter P 1 dB  indicates an output power level when the gain of the amplifier is reduced by 1 dB from P out . Another linearity parameter OIP 3  (Output Intercept Point of 3 rd  order) indicates a extrapolated intersection of the linear contribution of P out  and the undesired contribution from IMD 3 . 
     In communication systems such as WCDMA, WiMax, or LTE systems, it is desirable to have the ratio IMD 3 /P out  be as low as possible, which is directly related to the ratio a 3 /a 1 , so that the undesired signals are low enough to not affect recovery of information at the receiver. One known amplification topology used in RF communication is the cascode amplifier, in which two amplifiers are coupled in series, with the effect of having the same current circulating in each device. While these known amplification circuits generally achieve the effect of relatively high input-to-output isolation and relatively high gain, they have drawbacks, among which are inferior linearity when compared with conventional single-ended amplifiers operating at the same power supply voltage, such as about +5 volts. 
     Some publications which might have bearing on the known art include:
     “High Linearity Cascode Low Noise Amplifier”, U.S. Pat. No. 6,392,492 Bi (May 21, 2002), Xiaojuen Yuan.   ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS (John Wiley &amp; Sons, 2001), Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer.   

     SUMMARY OF THE DESCRIPTION 
     We provide techniques for signal amplification with a cascode amplifier circuit having relatively superior linearity, while maintaining other advantages of cascode amplifiers such as relatively high input-to-output isolation and relatively high gain. In one embodiment, a cascode amplifier circuit includes feedback loops, such as for example DC feedback loops and AC feedback loops, and dynamic bias, with the effect of improving linearity, maintaining gain, minimizing return loss, and providing a relatively high dynamic range. In one embodiment, the cascode amplifier circuit operates over the frequency band of about 0.1 GHz to about 4 GHz, with a maximum noise figure of about 2 dB. In such embodiments, a cascode amplifier circuit substantially improves OIP 3  better than about 15 dB above P 1 dB , that is, a improvement of at least about 5 dB compared to conventional amplifiers. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1  shows a circuit, having elements shown in the figure. 
         FIG. 2  shows a chart of the voltage at the gate of the transistor M 13  in response to an amount of gain applied to the signal RF in . 
         FIG. 3  shows a chart of amplifier gain in response to signal frequency of RF in . 
         FIG. 4  shows a chart of an amplifier performance in response to an amount of RF driving power. 
         FIGS. 5-6  show charts comparing a third order intermodulation component for a conventional cascode amplifier with an embodiment of the invention. 
         FIG. 7  shows a second embodiment of a circuit, having elements shown in the figure. 
     
    
    
     DESCRIPTION 
     Generality of the References 
     This application should be read in the most general possible form. This includes, without limitation, the following: 
     References to contemplated causes and effects for some implementations do not preclude other causes or effects that might occur in other implementations. 
     References to one embodiment or to particular embodiments do not preclude alternative embodiments or other embodiments, even if completely contrary, where circumstances would indicate that such alternative embodiments or other embodiments would also be workable. 
     References to particular reasons or to particular techniques do not preclude other reasons or techniques, even if completely contrary, where circumstances would indicate that the stated reasons or techniques are not as applicable. 
     References to “preferred” techniques generally mean that the inventors contemplate using those techniques, and think they are best for the intended application. This does not exclude other techniques for the invention, and does not mean that those techniques are necessarily essential or would be preferred in all circumstances. 
     References to specific techniques include alternative and more general techniques, especially when discussing aspects of the invention, or how the invention might be made or used. 
     Generality of the Techniques 
     Technologies shown or suggested by this description should also be thought of in their most general possible form. This includes, without limitation, the following: 
     The phrases and terms “constantly,” “continually,” “from time to time,” “occasionally,” “periodically” (and similar phrases and terms) generally indicate any case in which a method or technique, or an apparatus or system, operates over a duration of time, including without limitation any case in which that operation occurs only part of that duration of time. For example and without limitation, these terms would include, without limitation, methods which perform an operation as frequently as feasible, on a periodic schedule such as once per second or once per day, in response to an alarm or trigger such as a value reaching a threshold, in response to a request or an implication of a request, in response to operator intervention, otherwise, and to combinations and conjunctions thereof. 
     The phrases and terms “methods, physical articles, and systems,” “techniques” (and similar phrases and terms) generally indicate any material suitable for description, including without limitation all such material within the scope of patentable subject matter, or having ever been considered within the scope of patentable subject matter, or which might colorably be within the scope of patentable subject matter, notwithstanding most recent precedent. 
     The term “relatively” (and similar phrases and terms) generally indicates any relationship in which a comparison is possible, including without limitation “relatively less,” “relatively more,” and the like. In the context of the invention, where a measure or value is indicated to have a relationship “relatively,” that relationship need not be precise, need not be well-defined, need not be by comparison with any particular or specific other measure or value. For example and without limitation, in cases in which a measure or value is “relatively increased” or “relatively more,” that comparison need not be with respect to any known measure or value, but might be with respect to a measure or value held by that measurement or value at another place or time. 
     The term “substantially” (and similar phrases and terms) generally indicates any case or circumstance in which a determination, measure, value, or otherwise, is equal, equivalent, nearly equal, nearly equivalent, or approximately, what the measure or value is recited. The terms “substantially all” and “substantially none” (and similar phrases and terms) generally indicate any case or circumstance in which all but a relatively minor amount or number (for “substantially all”) or none but a relatively minor amount or number (for “substantially none”) have the stated property. The terms “substantial effect” (and similar phrases and terms) generally indicate any case or circumstance in which an effect might be detected or determined. 
     The phrases “this application,” “this description” (and similar phrases and terms) generally indicate any material shown or suggested by any portions of this application, individually or collectively, including all documents incorporated by reference or to which a claim of priority can be made or is made, and include all reasonable conclusions that might be drawn by those skilled in the art when this application is reviewed, even if those conclusions would not have been apparent at the time this application is originally filed. 
     The invention is not in any way limited to the specifics of any particular examples disclosed herein. After reading this application, many other variations are possible which remain within the content, scope and spirit of the invention; these variations would be clear to those skilled in the art, without undue experiment or new invention. 
     FIGURES AND TEXT 
     
       FIG. 1 
     
       FIG. 1  shows a circuit, having elements shown in the figure, including at least a packaging element  1  (such as for example a plastic or ceramic package) enclosing an IC die  2  (such as for example a substantially monolithic GaAs semiconductor die). In one embodiment, the circuit uses E-PHEMT (enhancement gallium arsenide pseudo-morphic high electron mobility) technologies. However, while this Application primarily describes a circuit using E-PHEMT technology, in the context of the invention, there is no reason for any such limitation. For example, the circuit could also work with any other E type technology FET, such as for example E-MESFET and NMOS technologies. As shown below, the circuit provides substantially improved dynamic range for linearity. 
     An input signal RF in  is coupled to the package  1  at a package input element (such as for example a first conductive package terminal), represented in the figure as a series parasitic inductance L 3  coupled to a parallel parasitic capacitance C 5 . The die  2  is attached to the package input element using wire bonds, represented in the figure as a series parasitic inductance L 4  and coupled to a node N in at the die  2 . Similarly, an output signal RF out  is coupled to the package  1  at a package output element (such as for example a second conductive package terminal), represented in the figure as a series parasitic inductance L 7  coupled to a parallel parasitic capacitance C 8 . The die  2  is attached to the package output element using wire bonds, represented in the figure as a series parasitic inductance L 6  and coupled to a node N out  at the die  2 . The output is also coupled to a voltage V + , whose DC component is substantially larger than either the (time-varying) input signal RF in  and the output signal voltage swings around the DC component, and has the effect of providing power for amplification by the circuit. 
     A cascode amplifier includes a first transistor M 13  and a second transistor M 14 , with a drain of the first transistor M 13  is coupled to a source of the second transistor M 14 , with the effect that first and second transistors M 13  and M 14  share a drain current. 
     The DC voltage V +  is coupled to a source for the second transistor M 14 , whose terminal also contains an amplified replica of the input signal RF in . After reading this application, those skilled in the art will realize that there is a time-varying signal at input, RF in , along with an input DC component, a substantially higher time-varying signal at output, RF out , with an output DC component, plus distortion signals generated by the device as described above with respect to equation (1). The input signal RF in  is not substantially affected by the output signal RF out . 
     After reading this Application, those skilled in the art would recognize that the DC voltage available for amplifier power remains relatively constant despite the time-varying component of the input signal RF in , and the DC current available for amplifier power remains relatively constant so long as the maximum DC power made available to the amplifier is below the P 1 dB  point by at least about 10 dB. 
     A feedback inductor L 9  is coupled in series between a grounding element and a node V G , the latter having a voltage substantially equal to the grounding element. This has the effect of providing substantial impedance matching, with relatively minimal sacrifice in amplifier gain at relatively high frequencies. The node N in  is coupled in parallel to a capacitor C 11 , which is coupled to the node V G , and in series to an inductor L 12 , which is coupled to a gate of the first transistor M 13 . This has the effect of matching the gate impedance of the first transistor M 13  to an industry-standard 50 ohm impedance value. 
     A source of the first transistor M 13  is coupled to an inductor L 10 , which is also coupled to the node V G . The voltage V +  is also coupled to the gate of transistor M 13  by a branch including capacitor C 15  in series with resistor R 16 , with the effect of providing RF feedback from output drain of transistor M 14  to the input gate of transistor M 13 . After reading this application, those skilled in the art would recognize that impedance at the device terminals would be better matched due to feedback action, with the effect of better linearity in amplification. 
     The node is coupled in series to a first capacitor C 17 , which is coupled to a node V bias , which is coupled to a second capacitor C 18 , which is coupled to the node V G . The node V bias  is coupled to a gate of the second transistor M 14 , with the effect of biasing the second transistor M 14 . After reading this application, those skilled in the art will realize that the capacitors C 17  and C 18  form a capacitive RF voltage divider, which provides a second feedback action from the output to the gate of the second transistor M 14  in response to the input signal RF in . 
     The node V +  is also coupled in series to a resistor R 19 , which is coupled to the drain of transistor M 23 . The source of transistor M 23  is coupled to the resistor R 24  which is connected to node V G . The bias of transistor M 23  is determined by the resistive divider composed of resistors R 20  and R 21 , which selects a fraction of the voltage difference between the node and the node V G  to be coupled to the gate of transistor M 23 . The drain current of transistor M 23  develops a voltage on resistor R 19 , which determines the DC voltage of node Vbias and the bias for transistor M 14 . 
     A transistor M 23  has its drain coupled to the node V bias , its gate coupled to the node V a , and its source coupled to the gate of a transistor M 22 . The transistor M 22  has its source coupled to the node V G , and its drain coupled in series to a resistor R 21 , which is coupled to the gate of the transistor M 23 . The gate of transistor M 22  and the source of transistor M 23  are coupled in parallel to a resistor R 24 , which is coupled to V G , and to a resistor R 25 , which is coupled to N in . This has a first effect of biasing of the gate of the transistor M 13  provided by the DC voltage generated by the current flowing through the resistor R 24  and the node V G . This also has a second effect that the resistor R 24  and the resistor R 25  collectively form a voltage divider, which selects a fraction of the voltage difference between the node V G  and the gate of the transistor M 13 , to be coupled to the gate of transistor M 22 . 
     After reading this application, those skilled in the art would realize that the transistor M 22  and the transistor M 23  collectively provide a response to variations in the time-varying input signal RF in . As the input signal RF in  varies, about the P 1 dB  power level, the voltage at the gate of the transistor M 22  (and at what is the same node, the source of the transistor M 23 ), also varies in response to the input signal RF in . This has the effect that the bias voltage applied to the first transistor M 13  is varied in response the input signal RF in , providing improved linearity for the cascode amplifier. A measure of this effect is shown below with respect to the  FIG. 3 . 
     The transistor M 22  and the transistor M 23  collectively provide a threshold voltage source, capable of stabilizing the current of M 13  over temperature and V threshold  process variations. The transistor M 22  and the transistor M 23  also collectively provide a peak rectifier of the input signal RF in , which has the effect of correcting the bias voltage at the gate of the transistor M 13 , particularly near the P 1 dB  power compression point, which in has the effect of correcting nonlinearities of the amplifier. The value of capacitor C 32  partially controls the degree of this rectifier effect. 
     
       FIG. 2 
     
       FIG. 2  shows a chart of the voltage at the gate (a gate bias voltage) of the transistor M 13  in response to an amount of gain applied to the signal RF in . An X axis shows an amount of RF driving power. A Y axis shows an amount of bias voltage. A first graphic  201  shows, without use of the transistor M 22  and the transistor M 23 , a relatively sharp drop in bias voltage in response to increased RF power. A second graphic  202  shows, in one embodiment, with use of the transistor M 22  and the transistor M 23 , a substantial bump at a relatively higher RF power, starting approximately at a P 1 dB  point, with the effect substantially correcting any dropoff in linearity at relatively higher gain (which would provide relatively higher RF power). 
     Transistor M 23  has a function to partially amplify the distortion voltage and to feedforward that distortion voltage from the drain of transistor M 23  to the gate of transistor M 14 . This has the effect of improving OIP 3  from about 3 dB to about 6 dB. As noted above, in one embodiment, the capacitors C 17  and C 18  form a capacitive RF voltage divider, which allows the circuit to control signal feedback to the gate of transistor M 14 . This has the effect of further improving OIP 3  from about 4 dB to about 5 dB, providing a cumulative improvement of more than about 10 dB. 
     
       FIG. 3 
     
       FIG. 3  shows a chart of amplifier gain in response to signal frequency of RF in . An X axis shows an input signal frequency. A Y axis shows an amplifier gain. A graphic  301  shows, in one embodiment, a relationship between amplifier gain in response to input signal frequency, showing a minimum gain of 10 dB at the high of frequency band and 20 dB at the low end of the band, with the relative effect of use in several communication bands. 
     
       FIG. 4 
     
       FIG. 4  shows a chart of an amplifier performance in response to an amount of RF driving power. An X axis shows an amount of RF driving power, in dBm (that is, from 10 −5  milliwatts to 10 1  milliwatts). A Y axis shows an amplifier performance gain, in dB (that is, a gain of between 10 1.25  and 10 1.60 ). A first graphic  401  shows, using a conventional cascade amplifier, a relatively sharp drop in amplifier performance from about 15.5 dB, starting at an X axis value between about −10 dBm. A second graphic  402  shows, using the circuit shown with respect to an embodiment of the invention, a significantly better amplifier performance, again with the effect of relative superiority for use in communication systems. 
     An embodiment of the invention is able to achieve a 22 dBm output power at the P 1 dB  compression point. Thus, the second graphic  402  crosses the Y value at 14.5 dB, that is, a 1.0 dB reduction from the ordinary amplifier gain of 15.5 dB, when the X value is about 9.0 dBm, for a total exceeding  22  dBm. Even so, the value of OIP 3  is above 45 dBm. Thus, the value of IMD 3  rises very slowly with respect to the amplifier output P out . This is more than 20 dB improvement over a conventional amplifier, while still operating over a relatively broadband selection of frequencies. The inventors have found that an embodiment of the invention operates with approximately this degree of improvement between about 0.1 GHz to 4.0 GHz. 
     
       FIGS. 5-6 
     
       FIGS. 5-6  show charts comparing a third order intermodulation component for a conventional cascode amplifier ( FIG. 5 ) with an embodiment of the invention ( FIG. 6 ). A third order intermodulation component (m 13 ) in a conventional cascode amplifier ( FIG. 6 ) is significantly closer to the amplifier output (m 12 ), than the third order intermodulation component (m 13 ) is to the amplifier output (m 12 ) in an embodiment of the invention ( FIG. 6 ). 
     
       FIG. 7 
     
       FIG. 7  shows a second embodiment of a circuit, having elements shown in the figure, similar to elements as shown in the  FIG. 1 . 
     The circuit includes a similar packaging element  1 , IC die  2 , node N in , output signal RF out , node N out , voltage V + , node V G , node V bias , and circuit components including at least inductor L 9 , inductor L 10 , capacitor C 11 , inductor L 12 , transistor M 13 , transistor M 14 , capacitor C 15 , resistor R 16 , capacitor C 17 , capacitor C 18 , resistor R 19 , resistor R 20 , resistor R 21 , transistor M 22 , transistor M 23 , resistor R 24 , and resistor R 25 . 
     In this second embodiment of a circuit, the transistor M 22  has an effect of being a current mirror, controlling the current of transistors M 13  and M 14 , rather than allowing them to vary in response to temperature variations and process variations. Similar to the first embodiment of the circuit, the transistor M 22  also has the effect of a rectifier of the RF peak voltage (which would otherwise generate distortion), and has the effect of correcting the DC voltage at transistor M 13 . The DC voltage and distortion voltage are also applied to the transistor M 23 , with the effect of applying them to the gate of the transistor M 14 . 
     Alternative Embodiments 
     The invention has applicability and generality to other aspects of amplifier devices and communication systems, including power or driver amplifiers for communication systems operating in WCDMA, WiMax and LTE communication systems.