Abstract:
A DC-coupled differential amplifier has an output common-mode voltage near the ground reference. A feedback circuit superimposed on a trans-linear loop improves linearity and extends the bandwidth of the basic PNP differential pair.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to analog circuit design. In particular, the present invention relates to a linear broadband PNP amplifier with a low output common mode voltage. 
     2. Discussion of the Related Art 
     There is a need for a DC-coupled differential amplifier with an output common-mode voltage that is below 1 V. Fast and linear pipe-lined analog-to-digital converters (ADCs) built with fine-line CMOS technologies operate at low power supplies (e.g., V dd =1.8 V). For best dynamic range, the input voltage to such an ADC should be set at half supply (i.e., 0.5×V dd  or 0.9 V). Differential amplifiers used as ADC drivers are generally built using SiGe technology and typically use only NPN transistors as their active elements. In its linear region, such a transistor requires a base-to-emitter voltage (V be ) of 0.9 V across its base-emitter junction at room temperature. A 0.9 V output common-mode voltage therefore will not support even a simple current source, let alone an amplifier. 
       FIG. 1  shows PNP differential pair  100  in the prior art, which includes current sources  101 - 1  and  101 - 2 , PNP transistors Q 2 B and Q 2 D, load resistors  102 - 1  and  102 - 2  (each having resistance value R 2 ) and resistors  103 - 1  and  103 - 2  (each having resistance value R 1 ). The gain in PNP differential pair  100  is set by the resistance values R 1  and R 2 . PNP differential pair  100  provides an output differential signal across terminals  104 - 1  and  104 - 2 . While PNP differential pair  100  can support an output common-mode voltage near the ground reference, a lower transistor frequency (f T ) and a lower common-emitter current gain (β), as compared to an NPN transistor, limit both bandwidth and linearity. 
     U.S. Pat. No. 4,731,588, to Addis et al., entitled “Gain Selectable Amplifier with Resonance Compensation,” issued on Mar. 15, 1988, and U.S. Pat. No. 5,307,024 to Metz et al., entitled “Linearized level-shifting amplifier,” issued on Apr. 26, 1994, disclose voltage feedback linearization techniques. However, these feedback linearization techniques are not applicable to PNP differential amplifiers when its linearity is limited by the lower current gain (β). The textbook “ Analogue IC Design: The Current - mode Approach ,” by C. Toumazou, F. J. Lidgey, and D. Haigh, Circuits, Devices and Systems, Peregrinus, 1993, pp. 11-21, suggests current-mode techniques which overcome this limitation. 
     SUMMARY 
     According to one embodiment of the present invention, a differential amplifier includes a differential pair, and a trans-linear loop and a feedback loop on each side of the differential pair. Each trans-linear loop includes transistors that, together with the corresponding input transistor of the differential pair, form a closed loop of base-emitter junctions. In addition, each trans-linear loop also includes a current source designed such that the ratio of the currents carried in that current source and in a corresponding current source of the differential pair are substantially the same as the ratio of the emitter area of one of the transistors in the trans-linear loop and the emitter area of the corresponding input transistor of the differential pair. The trans-linear loops allow the differential amplifier to operate at a common mode voltage that is close to the ground reference. Each feedback loop compensates the corresponding trans-linear loop for changes in the base current in the corresponding input transistor of the differential pair to ensure linearity in the differential amplifier over a wide bandwidth. 
     The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows PNP differential pair  100  in the prior art. 
         FIG. 2  shows DC-coupled differential amplifier  200 , in accordance with one embodiment of the present invention. 
         FIG. 3  shows trans-linear loop  300 , comprising the elements of the trans-linear loop on the side of PNP transistor Q 2 B of PNP differential pair  100 . 
         FIG. 4  shows feedback loop  400 , comprising the elements of the feedback loop on the side of PNP transistor Q 2 B of PNP differential pair  100 . 
     
    
    
     To facilitate cross-referencing among the figures, like elements are assigned like reference numerals in the figures. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 2  shows DC-coupled differential amplifier  200 , in accordance with one embodiment of the present invention. DC-coupled differential amplifier  200  has an output common-mode voltage near the ground reference. As shown in  FIG. 2 , differential amplifier  200  includes PNP differential pair  100 , and additional components. The gain in DC-coupled differential amplifier  200  is also set by the resistance values R 1  and R 2  of resistors  102 - 1 ,  102 - 2 ,  103 - 1  and  103 - 3 , respectively. The additional components form a trans-linear loop and a feedback loop on each side of PNP differential pair  100 . 
       FIG. 3  shows trans-linear loop  300 , comprising the elements of the trans-linear loop on the side of PNP transistor Q 2 B of PNP differential pair  100 . As shown in  FIG. 3 , NPN transistor Q 1A , PNP transistor Q 2 A, PNP transistor Q 2 B, and NPN transistor Q 1 B form a closed loop of base-to-emitter junctions. By design, transistor Q 2 A has an emitter area e and transistor Q 2 B has an emitter area Ne, where N is an integer (e.g., 5). Current sources  101 - 1  and  201 - 1  are designed to provide currents of values I 0  and (N+1)I 0 , respectively, so as maintain the current densities of transistors Q 2 A and Q 2 B substantially the same. Thus, trans-linear loop  300  imposes the following constraints on DC-coupled differential amplifier  200 :
 
 V   be,1A   +V   be,2A   =V   be,2B   +V   be,1B  
 
 J   1A   ×J   2A   =J   1B   ×J   2B  
 
where V be,1A , V be,2A , V be,2B , and V be,1B  are the base-emitter voltage in transistors Q 1 A, Q 2 A, Q 2 B and Q 1 B, respectively; J 1A , J 2A , J 1B , and J 2B  are the current densities in the emitters of transistors Q 1 A, Q 2 A, Q 1 B, and Q 2 B, respectively. The emitter current density is given by the ratio of emitter current I E  to emitter area A. The same operation is expected of the trans-linear loop on the side of PNP transistor Q 2 D of PNP differential pair  100 .
 
       FIG. 4  shows feedback loop  400 , comprising the elements of the feedback loop on the side of PNP transistor Q 2 B of PNP differential pair  100 . As shown in  FIG. 4 , feedback loop  400  comprises PNP transistor Q 2 A, current source  201 - 1 , PNP transistor Q 2 B, and NPN Q 3 A. Transistor Q 3 A compensates for any changes in the base current in transistor Q 2 B, which tracks changes in the load current. If changes in the base current of transistor Q 2 B are not compensated, the linearity of DC-coupled differential amplifier  200  would be limited. The same operation is expected of the feedback loop on the side of PNP transistor Q 2 D of PNP differential pair  100 . 
     The above detailed description is provided to illustrate the specific embodiment of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.