Abstract:
Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less capable interconnection paths within standard interconnection substrates.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation-in-part and incorporates by reference in its entirety, U.S. patent application Ser. No. 10/426,930, filed Apr. 29, 2003, and now U.S. Pat. No. 7,307,293, issued on Dec. 12, 2007, which claims benefit of U.S. Provisional Applications 60/376,482, filed Apr. 29, 2002, and U.S. Provisional Application 60/400,180 filed Jul. 31, 2002; all of which are incorporated by reference herein. The present application also claims benefit of and incorporates by reference in its entirety, U.S. Provisional Application No. 60/588,312, filed Jul. 14, 2004. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of integrated circuit packaging and interconnection. 
     BACKGROUND 
     Electronic packaging and specifically integrated circuit packaging and the interconnection between such devices have become a significant performance limiting elements of electronic circuits. Presently, semiconductors operate at internal clock speeds that surpass the current electronic interconnection infrastructure&#39;s ability to carry signals between semiconductors. 
     Copper (and other conductive metal) interconnect elements, including but not limited to semiconductor substrates (packages), connectors, and printed circuit boards have not followed the historical curve of semiconductor speed improvement; although arguably it has not been until recently that the copper interconnect represented a significant performance barrier in chip-to-chip systems. A well designed interconnection channel would allow two or more IC chips in close proximity to one another to communicate at their native speeds, as if they were a single chip. 
     Copper is in fact capable of transmitting signals at near the speed of light in a vacuum or air. However, in practice electrical circuits cannot be practically established in vacuums, and are typically composed of several components that must connect at points of potential discontinuity. The electrical circuits must be held in place physically by structures made of an insulating material, which normally impedes the signal propagation. 
     Copper interconnect systems typically incorporate several sources of signal discontinuity and disturbance, which degrade signal integrity and reduce speed. These include variances in metal conductor path height, width, length, and materials, proximity to other circuit paths, through-hole vias, connector and solder joints, and capacitive stubs. 
     One fundamental design objective for high speed circuits is to incorporate the shortest signal path between two objects, which geometry teaches is a straight line. Typically the signal path from chip-to-chip in an electronic system travels from the semiconductor, through the package, into the circuit board, through another package and to the second semiconductor. This approach involves a relatively tortuous circuit route that does not closely track the straight line design objective. However, by routing some or all signals through structures that create signal paths that do not traverse the package or the printed circuit board, a more straight line path can be accomplished. A path that avoids the printed circuit board and the package may also avoid common elements of those structures, such as vias and stubs, as well as other signal disruptors. 
     New interconnect elements may facilitate the creation of a more direct path for some or all signals. Structures that establish an electrical path directly from one chip to another chip may create performance advantages. 
     It is believed that such innovations and future products based on them will meet or exceed all cost and performance design requirements with minimal disruption to the manufacturing infrastructure. At the same time, it will remove most current roadblocks to high speed signal transmission from chip to chip. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
         FIG. 1  provides an example of related prior art showing terminations on the surface of an IC package disposed for interconnection at the edge. 
         FIG. 2  provides an illustration of an embodiment wherein a separate circuit is bonded to an IC package to provide alternative interconnection pathways for signals exiting an IC and further illustrating, in cross section, two prospective embodiments for making such interconnections from the chip, either from the top or from the bottom of the package. 
         FIG. 3  provides an exploded perspective view of another embodiment illustrating major constituent elements of the construction. 
         FIG. 4  provides perspective views of the elements shown in  FIG. 3  in a partially assembled form and an enlargement of a section, to show greater detail. 
         FIG. 5  illustrates, in a perspective view, an embodiment of the invention wherein more than 1 chip is interconnected within the package. 
         FIG. 6  illustrates, in a perspective view, an embodiment of the invention wherein the assembly is encapsulated and having contacts disposed for connection, both at the edge of the package and extending beyond the edge of the package on a length of circuit greater than the other lengths. 
         FIGS. 7A and 7B  provide perspective views of partially assembled embodiments having circuits on the upper surface which egress at differing angles and directions. 
         FIG. 8  illustrates an embodiment in cross section showing prospective elements of construction and having wire bonds made directly to a stripline circuit construction which exits the package on the edge. 
         FIG. 9  illustrates an embodiment wherein more than one cable is mounted and interconnected to a surface opposite of the IC in a package. 
         FIG. 10  illustrates an embodiment wherein the separate circuit is extended, folded back and bonded to the encapsulation which protects the IC chip. 
         FIG. 11  illustrates an embodiment wherein the separate circuit is extended, folded back and bonded to the encapsulation, which protects the IC chip and having also a second IC chip interconnect to the circuit, and the circuit then extending to make interconnection to another electronic device or element. 
         FIG. 12  provides an example of embodiment wherein multiple devices of varying embodiments are in process of assembly to a substrate and have interconnections to another element such as a cable or data bus. 
         FIG. 13  provides a perspective view of an assembly comprised of various component embodiments, circuit elements and interconnection support pedestals which serve as separable or permanent connectors. 
         FIG. 14  provides a perspective view of an embodiment disposed to having a connector on IC package before being provided with a locking lever and an enlarged area providing detail of the contacts. 
         FIG. 15  provides the perspective view of an embodiment having a connector on IC package with a locking lever and a circuit assembly disposed for mating with the IC package connector. 
         FIG. 16  is an illustration of a cross sectioned view through the middle of the IC package and the circuit assembly. 
         FIGS. 17A-17C  are a close up series of images illustrating the operation of the connector mechanism. 
         FIG. 18  illustrates gold bumps viewed through the flexible circuit assembly. 
         FIG. 19  is an illustration of the back of the locking lever in a perspective view. 
         FIG. 20  provides a perspective view of a partially assembled pedestal connector with one side engaged to a circuit and the second side disposed for interconnection. 
         FIG. 21  provides a perspective view of a partially assembled pedestal connector of  FIG. 20  from the opposite side, showing circuits and having an enlarged area to provide greater detail of the contact area. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. The interconnecting structures may be microstrip or stripline and the signal lines may be either shielded or unshielded. 
     The present invention expands on concepts disclosed in pending U.S. patent application Ser. No. 10/426,930 entitled “Direct Connect Signaling System”, filed Apr. 29, 2003, which is incorporated herein by reference and which describes various embodiments of high-speed signaling systems implemented by connecting electric signal conductors directly between integrated circuit packages so that high-speed signals are transmitted without passing through traces or other conductive structures on or within a printed circuit board. Among the various embodiments described therein, the application describes embodiments that facilitate interconnection of two or more integrated circuit packages which are mounted to a printed circuit board and coupled to one another, either permanently or removably via a circuit or cable, which is suspended, positioned or fixed above the printed circuit board. Some or all high-speed signals, low-speed signals, power or ground may be routed from one integrated circuit package to the other via the circuit or cable, while other signals, power or ground may be routed to the integrated circuit packages via traces and conductive structures that route through the printed circuit board. 
     Where packaged IC die or chips are interconnected in a typical system all signals leave the first chip, transition through the IC package and exit the IC package, travel through solder connections into the PCB substrate, emerge from the PCB substrate, travel through a second set of soldered connections into another IC package to the IC chip or die contained therein. This signal path typically contains discontinuities which distort and/or reduce the quality and strength of the transmitted signal. 
     The embodiments in U.S. patent application Ser. No. 10/426,930 set forth alternatives that allow signals to be transmitted “off-the-top” directly between chips by routing signals from one package to another package without traversing the printed circuit board. In one embodiment, signals are launched from the surface of one chip package, through a controlled impedance cable or circuit structure, to a second chip package of similar construction. 
     Within the embodiments set forth in the present patent application, I/O drivers are connected directly to those signal lines and transmitted through the cable or circuit to the surface of the second chip package. 
     It is also possible to modify existing packages to convert them into off the top structures by the addition of a top circuit layer structure designed to carry high speed signals. This allows a user of the technology to bond a circuit directly to the top of an existing IC package circuit with limited modifications. In such an embodiment, the chosen I/O terminals formerly needed for IC interconnection to the package and PCB are bypassed and interconnection is instead made directly to the terminals on the cable or circuit mounted onto the package using an electrical connection technology, such as wire bonding or flip chip. Such added cable or circuit structures would provide the paths for some or all high speed signals either proximate to the edge of the body of the package or beyond the edge of the package to a location intermediate between the edge of the package and the chip where interconnections can be made to a terminal block or connector of a design which does not degrade the signal quality. 
     Alternatively, an embodiment could also provide a top circuit layer structure directly from the chip, off of and away from, the perimeter of the package. Some embodiments may carry the signal away from the chip starting at the chip itself, the bond wire, or the bond pad on the package. 
     The top circuit layer structure could be made of reinforced materials or non-reinforced materials (i.e., rigid to flexible) and could be made of various materials matching the electrical needs of the application. 
     These and other embodiments of the invention are disclosed in further detail below with the aid of figures. 
       FIGS. 1A and 1B  depict a prior-art embodiment of an IC package  3  including an IC die  15  mounted in the center of an IC package substrate  10 . The IC Package of  FIGS. 1A and 1B  has been modified in accordance with an embodiment of the invention described in U.S. patent application Ser. No. 10/426,930, which is incorporated by reference herein. As shown in  FIG. 1A , selected circuit traces  13  are disposed on the top surface of the package substrate. The circuit traces  13  terminate in first and second ends. The terminations at the first end are positioned near the center of the IC package, for connection to an IC die. The second end of each circuit trace terminates somewhere between the IC die  15  and the edge of the substrate  10 . Circuits  11  terminating on the outer edge of the package  3  include terminations for connection to another circuit element such as a controlled impedance flexible cable.  FIG. 1B  depicts a cross sectional view of the IC package  3  of  FIG. 1A , and illustrates a prospective construction, where a flexible or rigid circuit structure  10 , such as an IC package substrate, comprises an insulating dielectric base material  12  which has conductive circuit traces  13  with corresponding first and second ends. The circuit traces are, partially protected by a second insulating dielectric material  14  of suitable properties. An IC die  15  is attached to the base circuit structure  10 , which can have one or more layers of interconnection wiring comprising internal layers (not shown) and interconnected to traces thereon by means of wire bonds  16 . Alternatively, the IC die can be mounted directly to an IC package substrate by flip chip technology that utilizes conductive “bumps,” thereby eliminating the need for bond wires  16 . In an embodiment utilizing bond wires, IC die and bond wires are protected by an encapsulant  17 . Next level connection from the IC package to a structure such as a PCB can be accomplished by a variety of contacts, such as solder balls  18  depicted in FIG.  1 B., Within  FIGS. 1A and 1B , a second circuit  19 , such as a flexible circuit or cable, is attached to the opposite (e.g. upper) surface using a suitable means such as solder or conductive adhesive or by a separable connection (not shown). The circuit  19  can be, but is not limited to, a microstrip or stripline construction and can also be of unshielded differential pairs or single ended or coaxial connections if so desired. One or more of the separate circuits  19  can be mounted on the otherwise unmodified IC package substrate on one or both sides if desired. 
       FIG. 2A  illustrates top plan view of an embodiment of an otherwise unmodified IC package structure  25  that includes a substrate  20 , an IC die  41  disposed in the center of the substrate, and a circuit structure  21  coupled with the substrate. In the embodiment of  FIG. 2  the circuit structure  21  is comprised of three circuit arms (e.g., flexible circuits). Each circuit arm has a proximal end disposed proximate the IC die  41  and a distal end extending beyond the outer edge of the substrate  20 . Each circuit arm  21  has at least one circuit trace, which extends the length of the arm on which it is located, from a first termination site  22  at the distal end of its arm, to a second termination site  23  at the proximal end of its arm.  FIG. 2A  depicts a circuit structure  21  comprised of three flexible circuit arms. However, the circuit structure could be comprised of a single circuit arm or a plurality of circuit arms. 
       FIGS. 2B and 2C  depict cross sectional views of alternative embodiments of the IC package structure  25  depicted in  FIG. 2A . Within  FIG. 2B , the IC package structure  25 ( b ) has IC package terminations  18  (e.g. solder balls  18 ) on the same side of the package as the circuit structure(s)  21 . The circuit structures  21  are coupled to corresponding IC die-terminals  43  by bond wires  42 . 
       FIG. 2C  depicts a cross sectional view of an embodiment  25 ( c ) of the IC package structure  25  of  FIG. 2A , wherein IC die terminations  43  are on one surface (e.g. top surface) of the IC die  41 , and package terminations  18  are on the side opposite of the IC die, which, in  FIG. 2C , is the bottom surface of the IC package substrate). Interconnection between the top and bottom surfaces of the IC package substrate  20  is achieved by conductive pathways such as plated through holes. Circuit structure  21  is attached to the IC package on the same side as the IC die terminals  43 . The conductive path(s) of circuit structure  21  are interconnected to the IC die or chip terminals by means of bond wires  42 . 
       FIG. 3  provides a perspective view of an IC package substrate  20  and a circuit structure  30  configured for attachment to the IC package substrate. The substrate has a center region configured to accommodate at least one IC die. The separately constructed circuit structure  30  has four arms  31   a ,  31   b ,  31   c ,  31   d , each arm having an proximal end and distal end. Each arm contains conductive circuit traces extending from its proximal end to its distal end. The circuit structure is configured such that, when attached to the package substrate  20 , the proximal end of each arm is disposed near the IC die. The distal end of arms  31   a - 31   c  are routed toward the a distal edge of the IC package, with the fourth arm  31   d  extending beyond the edge of the package. However, the length of each arm, and its conductive circuit traces, could be of any chosen length required for the design application, extending off of, to the edge of, or to a point on the IC package substrate  20 . Though not shown, multiple layers of separate circuits may be placed one atop another to create multiple signal pathways. Access to each separately constructed circuit structure may be achieved by making successively wider openings in the central aperture in each successive separate circuit. Each arm  31   a - 31   d  includes one or more conductive circuit traces  32 ,  34 . Each circuit trace has a first termination near the proximal end of its respective arm, and a second termination near the distal end of its respective arm. 
       FIG. 4  illustrates a perspective view of an embodiment in which the assembly of the IC package and the circuit structure shown in  FIG. 3 , comprises an IC die  41  wired bonded to the circuit structure  30  to create a partially completed assembly  40 . An enlarged detail section shows contacts being made by wires  42  directly from first terminations on the chip  43  to second terminations  34  on the attached circuit structure  30 . Though only one die is shown, stacking of additional IC die atop the first is also possible and can be used in combination with the stacking of additional circuit layer if so desired. Such additional circuit layers could also include coiled inductors and wireless antenna. 
       FIG. 5  illustrates an assembly embodiment  50  with separate circuit structure  30  having additional IC chips  51  mounted and interconnected to it using a suitable method (e.g. flip chip interconnection) and positioned between the IC  41  and the circuit paths with their terminations. Such chips could provide extra functionality or improve signal performance with external drivers. Again, stacking of IC chips one atop another and then interconnected to the combined structure package (not shown) is also possible to provide extra functionality. 
       FIG. 6  illustrates the embodiment illustrated in  FIG. 5  further processed to create a more complete assembly  60 , having an encapsulant or overmold material  61  applied over the assembly to protect the IC chip mounted on and interconnected to both the unmodified IC package substrate and separate circuit  30 , and leaving terminal locations  62  for the circuits open and free of encapsulant. 
       FIG. 7A  depicts a prospective view of an alternative embodiment for an assembly comprising a circuit structure  74  disposed on a surface of an integrated circuit package substrate  70 . Circuit structure  74  includes features such as generally described in the foregoing  FIGS. 2-6 , but includes eight arms  72  extending away from the location of the central IC die in varying discrete directions, allowing for circuit paths to be routed at any desired angle. The distal end of some of the arms  72  of  FIG. 7  extend to the edge of the IC package substrate  70 . Other arms  72  terminate before reaching the edge of the IC package substrate. 
       FIG. 7B , depicts an alternative embodiment of a circuit structure  73  in assembly with an IC package. The circuit structure is a monolithic structure  73  having no individual arms extending from a center area. The circuit structure  73  has circuits routable along any desired path on its surface. The circuit structure  73  of  FIG. 7B  could also serve as a foundation for a coil or like structures. Any of the separate circuits could be constructed with perforations in them (not shown) that may improve bonding to the IC package and the flow and fill of any adhesives that might be used in the bonding process. Perforations may also facilitate and/or improve bonding of the overmolding or encapsulating material used to protect the IC and its interconnections. 
       FIG. 8  illustrates an embodiment comprising an unmodified IC package substrate  80  comprising an insulating dielectric base material  82 , with an IC chip  81  mounted thereon. Circuit paths  86  on the base material of the package, terminate on the package at a solder ball terminal  88 , and the IC chip  81  is interconnected to the circuit paths on the package by means of wire bonds  83 . The mounted and bonded separate circuit  89 , shown in the image has a three metal conductor layer stripline circuit. The separate circuit  89  has a first end disposed on the substrate surface proximate the IC chip  81 , and extends beyond the perimeter of the IC package interconnection substrate. The separate circuit  89  is also interconnected to the chip by means of a separate wire bond  84 . The chip, bonded separate circuit and the interconnections are protected by an encapsulant  87 . 
       FIG. 9  illustrates an embodiment wherein the separate circuits  95 , shown in the figure as stripline circuits, are bonded and interconnected circuit paths  92   b  using an interconnection material such as solder or conductive adhesive  94 . An interconnection path is made to the flip chip IC  91  on the opposite side of the package substrate by way of vias  93  passing through the IC package to the surface opposite the strip line circuits. The side having the flip chip also has circuit paths  92   a  to be mounted to a next level interconnection substrate. 
       FIG. 10  illustrates an embodiment wherein the separate circuit  100  is extended, folded back and bonded to the encapsulated chip and circuit using an adhesive  101  and having terminals  102  to provide a larger or more stable platform for interconnecting to and routing signals to one or more other IC chip packages distant or proximate to the first IC chip package. 
       FIG. 11  illustrates an embodiment wherein a bonded separate circuit (e.g., a stripline circuit)  100  has an extended length separate circuit and a separate IC chip or package  111  mounted on the separate circuit to provide either greater functionality or performance. The extended length separate circuit is bonded to the top of the encapsulated package using an adhesive  101 . 
       FIG. 12  illustrates a partially assembled embodiment showing potential interconnection methods for some of the various described embodiments of finished parts. A base interconnection structure or printed circuit  121  has disposed for interconnection four package structures  120   a ,  120   b ,  120   c  and  120   d , each having integral separate circuit extensions  30  and openings  61  allowing interconnections to be made either to one another or to other separate interconnecting structures, such as a common bus cable  122  or other interconnecting structure. 
       FIG. 13  shows a perspective view of another assembly embodiment  130  comprised of a base circuit structure  131  and four interconnected package structures  132   a ,  132   b ,  132   c  and  132   d . While only four packages are shown, it will be readily appreciated that many packages are possible. The packages are interconnected by means of discrete circuit elements  133 ,  134 ,  135  of varying shapes and lengths. For example, section  133  is straight,  134  is curved and  135  is bifurcated. Also show are pedestals  136  which serve to support and interconnect the partial circuits. The pedestals can be of insulating material (e.g., polymer ceramic or glass), conductive material (e.g., metal or metal filled polymers), semi-conductive materials (e.g., silicon) or combinations thereof. The pedestals serve to support and can also align circuits they interconnect and can be used to make either permanent or temporary/separable connections. 
       FIG. 14  shows a perspective view of an embodiment of an IC package assembly  140  comprising a base circuit  141  and a central die  142  and encapsulated with a suitable material  143 , but having at least one open area  145  with exposed electrical contacts  146 . An enlarged detail view  147  shows the contacts provided with conductive bumps  148  if desired. The encapsulating material  143  is disposed with a hinge position  144 . 
       FIG. 15  shows assembly  140  with a locking lever  155  in place and in an open position. Also shown is a partial view of a circuit assembly  150  disposed for mating to the IC package. Circuit assembly  150  has a base circuit  151  which may be a flexible circuit and has a stiffener  152  affixed to the base circuit. The stiffener can also serve as an alignment mechanism, such as providing a slot thereon which would capture a pin on the mating assembly (not shown). 
       FIG. 16  illustrates a cross sectioned view through the middle of assembly  140  and the circuit assembly  150 . The circuit assembly  150  has been inserted under locking lever  155 . When notch  153  in stiffener  152  (shown in  FIG. 15 ) touches stop  161 , the circuit assembly  150  is in position for the next operation. 
       FIGS. 17A-17C  illustrate, in close-up cross section views, selected elements of  FIG. 16  showing detail of the operation. 
       FIG. 17A  shows of the locking lever  155  of the assembly  140  disposed above the stiffener  152  of circuit assembly  150 . The locking lever comprises a stop  161  which, according to the position of  FIG. 17A , extends into a notch  153  formed at the distal end of the stiffener. The horizontal surface of the notch terminates at a vertical surface of the stiffener  152 , which is abutted against the locking lever stop  161 . 
       FIG. 17B  shows the locking lever  155  partially rotated toward the fully locked position. The pulls  173  are just beginning to engage the notches  174 . 
       FIG. 17C  shows the locking lever  155  in the fully locked position. The pulls  173  have pulled the flexible circuit assembly into the IC package. As the locking lever rotates into the locked position, the cam surface  175  on the locking lever  155  pushes down on the top of the sitffener  152 , thus forcing the flexible circuit&#39;s contact pads downward. These two actions create contact force and contact wipe, thus increasing contact reliability. 
       FIG. 18  shows a hidden section view through the top of assembly  140  and circuit assembly  150 . The section enables us to view the locations of the electrical contacts  148  on assembly  140 , and the electrical contacts  171  on the circuit assembly  150 . The electrical contacts provide more than one contact per signal interconnection and are designed to eliminate the capacitive stub common when only one electrical contact is present per signal interconnection. The electrical contacts may be conductive dots or bumps of gold or other suitable corrosion resistant contact metal. The dots or bumps serve to connect with electrical contact pads.  FIGS. 17A-17C  illustrate how the contacts on each side of the interconnection interface move with respect to each other to provide contact wipe. 
       FIG. 19  provides a rear view of the locking lever  155 . The stop  161 , pulls  173 , and cam surface  175  of the locking lever  155  are shown. While members of the locking lever are shown as having defined dimensions for the illustration, they are not limited in size, shape or location on the locking lever nor are the size, shape or location of corresponding mating notches on the stiffener  152  with the major concern being that their primary functions are fulfilled. 
       FIG. 20  illustrates a partially assembled embodiment  200  of the pedestal interconnection devices  136  shown in  FIG. 13 . A pedestal connector  136  serves to electrically interconnect circuit assemblies  150 , which are disposed to be positioned within the saddle of the body of the pedestal. Locking levers  155   a ,  155   b  are positioned back to back and have the same basic functions and configurations as locking lever  155  shown in  FIGS. 15 ,  16 ,  17 A-C and  19 . In the figure, locking lever  155   a  is shown in the open position and disposed for connecting to circuit assembly  150 A, while locking lever  155   b  is shown in the closed position with the circuit assembly  150 B connected and locked into position. Circuit substrate  203 , resides inside connector housing  206 , and has a set of exposed electrical contacts  204  with conductive bumps  205  at or proximate to the end of the conductors. Conductive bumps  205  are similar to those items  146 ,  148  respectively shown in  FIG. 14 . There is an unseen, mirror image of electrical contacts with conductive bumps under locking lever  155   b . The locking levers  155   a ,  155   b  provide the force required to electrically interconnect circuit assemblies  150  through circuit substrate  203 . Either or both circuit assemblies  150  may be electrically attached to IC packages or other electrical components and provide electrical function such as a ground function. Circuit assemblies  150  can also be provided with alignment features such as slots which would capture pins on the pedestal (not shown). 
       FIG. 21  illustrates an isometric view from the bottom of the partially assembled structure  200 . In the figure, pedestal electrical connector  136  is coupled with circuit assemblies  150  A,  150 B. Conductive bumps  171  are at the ends of the circuit assemblies&#39; electrical contact pads. Posts  210  may be integral with the connector housing  206  may be positioned into holes in a printed circuit board or the like (not shown). These posts or additional posts on the bottom of the connector housing may be conductive and electrically connect electronic signals, ground or power, originating in the printed circuit board to the conductors in the circuit assemblies  150  and/or pedestal connector  136  or to conductors in the circuit substrate  203 . 
     While much discussion has be given to the use of circuits bonded into the saddle of a pedestal, it should be clear to those of average skill in the art that the circuit conductors could be molded into the body of the pedestal and that the shoulders which define the saddle are not a mandatory requirement. 
     The locking lever, when operated, may provide the contact force necessary for low contact resistance while simultaneously moving the contact with respect to the contact pad to produce contact wipe. Present known art relative to locking levers provide no purposeful contact wipe, but instead commonly produce a butt contact which normally offers no contact wipe. Moreover, butt contact requires much larger contact forces than a contact with wiping action. Thus the embodiments illustrated may not require as much contact force as prior art. When the contact forces of all the interconnections in the embodiments are added, the necessary connector clamping force may thus be lower. 
     In  FIG. 18  conductive bumps or conductive dots are placed at the ends of the contact pads in each circuit element. When the contacts are overlapped and electrically interconnected, they may fully or partially eliminate the capacitive stub that is typically created when only one conductive bump is present in the signal interconnection.  FIG. 18  illustrates contact redundancy for each signal interconnection.  FIG. 18  also illustrates alignment between the contacts in the direction defined by a line between the redundant contacts in the signal interconnection. In this embodiment, if one contact is farther away from or closer to the redundant contact in the signal interconnection, contact and signal integrity are still generally retained. 
     Although the invention has been described with reference to specific exemplary embodiments, modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.