Abstract:
Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.

Description:
BACKGROUND 
   1. Field of the Invention 
   Embodiments of the invention generally relate to electronics. In particular, embodiments of the invention relate to analog integrated circuits. 
   2. Description of the Related Art 
   Analog amplifiers are widely use in electronic devices. Applications include, but are not limited to: buffers, attenuators, gain amplifiers, current amplifiers, filters, drivers, interface circuits between digital and analog domains, and the like. One type of amplifier is known as an operational transconductance amplifier (OTA). An OTA receives a differential input voltage and generates an output current. OTAs are commonly used in, for example, variable frequency oscillators, filters, variable gain amplifiers, and the like. 
   It is desirable for an analog amplifier to have relatively good performance, to be inexpensive to manufacture, to be usable in a wide range of power supply voltages, to be able to swing relatively large output voltages, and the like. For example, in a mobile battery-powered application with a relatively low-voltage power supply, analog amplifiers preferably efficiently utilize the available supply voltage. 
   In the context of a switched-capacitor filter, an operational transconductance amplifier (OTA) is described by Rinaldo Castello, et al., in “ A  500- nA Sixth - Order Bandpass SC Filter ,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 25, No. 3, June 1990, pp. 669-676. However, the application of the foregoing amplifier appears to be prone to relatively severe mismatches for the drain-to-source voltages of the mirror transistors. For example, with reference to Castello, ibid, the drain-to-source voltages for the following three current mirrors: M 7 /M 9 , M 8 /M 11  and M 13 /M 15  all appear to be mismatched. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawings and the associated description herein are provided to illustrate specific embodiments of the invention and are not intended to be limiting. 
       FIG. 1  is a schematic generally illustrating a current-mirror (symmetrical) operational transconductance amplifier with self-biased cascode current mirrors. 
       FIG. 2  is a schematic generally illustrating a folded-cascode operational transconductance amplifier with self-biased cascode current mirrors. 
       FIG. 3  is a schematic generally illustrating a folded-cascode operational transconductance amplifier with additional low-threshold voltage transistors. 
   

   DETAILED DESCRIPTION OF EMBODIMENTS 
   Circuit topologies are disclosed that provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. An OTA is found in many analog circuits. Applications include, but are not limited to: buffers, attenuators, gain amplifiers, current amplifiers, filters, drivers, sensors, interface circuits between digital and analog domains, and the like. 
   One advantage of the self-biased cascode current mirror is that it saves extra bias voltages from having to be provided. This advantageously reduces power consumption, size, and cost. Although particular embodiments are described herein, other embodiments of the invention, including embodiments that do not provide all of the benefits and features set forth herein, will be apparent to those of ordinary skill in the art. For example, while the self-biased cascode current mirror is illustrated in the examples implemented in NMOS, the principles and advantages described herein are also applicable to PMOS. 
     FIG. 1  is a schematic generally illustrating a current-mirror (symmetrical) operational transconductance amplifier with self-biased cascode current mirror circuits. In the illustrated embodiment, all three of the cascode current mirror circuits are self biased. However, in an alternative embodiment, fewer than all of the cascode current mirror circuits are self biased. 
   In  FIG. 1 , VAA and AGND indicates voltage references, e.g., a positive voltage for FAA and analog ground for AGND. Transistors MN 0  and MN 1  form a differential input circuit. Transistors MP 0 -MP 3 , MP 4 -MP 7 , and MN 2 -MN 5  form self-biased cascode current mirror circuits. A current reference I bias  biases the differential input circuit. For example the current reference I bias  can be embodied by a drain terminal of a transistor having a voltage-biased gate terminal. For the purposes of illustration, the transistors will be described as having the same size or width-to-length ratio (W/L). However, it will be understood that scaled devices can be used and that with respect to current-mirroring, mirrored currents typically scale in proportion with the scaling of the transistors. 
   In the illustrated examples, the cascode transistors MP 1 , MP 3 , MP 5 , MP 7 , MN 2 , and MN 4  have a lower threshold voltage than the mirror transistors MP 0 , MP 2 , MP 4 , MP 6 , MN 3 , and MN 5 . This permits the gate terminals of each of the transistors of the cascode current mirror circuits to be tied together and obviates the need for a biasing circuit specifically for the cascode transistors and avoids an undesirable offset as found in Castello&#39;s implementation. 
   Operation of the current-mirror operational transconductance amplifier will now be described. A gate terminal of transistor MN 1  is coupled to a non-inverting input V inp . A gate terminal of transistor MN 0  is coupled to an inverting input V inn . Source terminals of transistors MN 0  and MN 1  are coupled to each other and to the current reference I bias . 
   The operation of the self-biased cascode current mirror circuit of transistors MP 4 -MP 7  will now be described. The other self-biased cascode current mirror circuits (MP 0 -MP 3  and MN 2 -MN 5 ) operate in the same manner. Transistors MP 4  and MP 5  form a reference portion of the self-biased cascode current mirror circuit. Transistors MP 6  and MP 7  form a mirror portion of the self-biased cascode current mirror circuit. Transistors MP 5  and MP 7  are cascode transistors. Transistors MP 4  and MP 6  are mirror transistors. 
   The drain current of transistor MN 1  also flows through transistors MP 4  and MP 5 . The current establishes a gate-to-source voltage across transistor MP 4 , which is applied as a gate-to-source control voltage across transistor MP 6  so that the current of transistor MP 6  mirrors the current of transistor MP 4 . Due to the series connection, the current of transistor MP 7  is the same as the current of transistor MP 6 . The resulting current flowing out of the drain terminal of transistor MP 7  then mirrors the current flowing out of the drain terminal of transistor MP 5  and into the drain terminal of transistor MN 1 . It will be understood that transistors MP 6  and MP 7  can be scaled relative to transistors MP 4  and MP 5 , and that if scaled, the current will typically similarly scale. The use of the term “mirror” herein does not imply that the scaling is necessarily 1:1. The mirrored current from transistor MP 7  provides current to the output node V out . 
   The inequality expressed in Equation 1 should be satisfied to bias the self-biased cascode current mirror circuit in the desirable saturation region for analog operation.
 
(| V   GS     —     MIRR   |−|V   GS     —     CASC |)=| V   DS     —     MIRR   |&gt;|V   DSAT     —     MIRR |  Eq. 1
 
   In Equation 1, V GS     —     CASC  is the gate-to-source voltage for a cascode transistor (e.g., transistor MP 5 ); V GS     —     MIRR  is the gate-to-source voltage for a mirror transistor (e.g., transistor MP 4 ); V DS     —     MIRR  is the drain-to-source voltage for a mirror transistor; and V DSAT     —     MIRR  is drain-to-source saturation voltage for a mirror transistor. 
   The self-biased cascode current mirror circuit of transistors MP 0 -MP 3  generates a mirror current flowing out of the drain terminal of transistor MP 1  that is a mirror of the current flowing into the drain terminal of transistor MN 0 . The mirrored current from the drain terminal of transistor MP 1  flows into the drain terminal of transistor MN 2  of the self-biased cascode current mirror circuit of transistors MN 2 -MN 5 . The mirrored current from transistor MP 1  flows through transistors MN 2  and MN 3 . The self-biased cascode current mirror circuit of transistors MN 2 -MN 5  generates a mirror current flowing into the drain terminal of transistor MN 4  and through transistors MN 4  and MN 5 . This mirror current sinks current from the output node V out . 
     FIGS. 2 and 3  are schematics generally illustrating a folded-cascode operational transconductance amplifier with self-biased cascode current mirrors. Transistors MN 9  and MN 10  form a differential input circuit. Transistor MN 15  forms a current source (sink) that biases the differential input circuit. Transistors MP 8 -MP 11  form fixed and variable current references. Transistors MN 11 -MN 14  form a self-biased cascode current mirror. 
   A gate terminal of transistor MN 15  is coupled to a bias voltage V bias1 . In the illustrated embodiment of  FIG. 2 , gate terminals of transistors MP 9  and MP 11  are coupled to a bias voltage V bias2 , and gate terminals of transistors MP 8  and MP 10  are coupled to a bias voltage V bias3 . In an alternative embodiment illustrated in  FIG. 3 , transistors MP 9  and MP 11  have a lower threshold voltage than transistors MP 8  and MP 10 , and the bias voltage V bias2  is not needed, further reducing the number of voltage biases used. In one embodiment, the self-biasing feature of the cascode current mirror circuit for the embodiment of  FIG. 3  is optional, e.g., a conventional cascode current mirror circuit can be used. A source terminal of transistor MN 15  is coupled to a voltage reference (AGND). The drain terminal of transistor MN 15  is coupled to source terminals of transistors MN 9  and MN 10  of the differential input circuit. 
   A gate terminal of transistor MN 10  is coupled to an inverting input V inn , and a gate terminal of transistor MN 9  is coupled to a non-inverting input V inp . 
   A drain terminal of transistor MN 10  is coupled to a drain terminal of transistor MP 10  and to a source terminal of transistor MP 11 . A drain terminal of transistor MN 9  is coupled to a drain terminal of transistor MP 8  and to a source terminal of transistor MP 9 . Source terminals of transistors MP 8  and MP 10  are coupled to a voltage reference (VAA). A drain terminal of transistor MP 11  is coupled to an output node V out . A drain terminal of transistor MP 9  is coupled to the drain terminal of transistor MN 11  of the self-biased cascode current mirror circuit. 
   Transistors MN 11  and MN 13  of the self-biased cascode current mirror circuit have a lower-threshold voltage than transistors MN 12  and MN 14 . The drain terminal of transistor MN 11  is coupled to the gate terminals of transistors MN 11 -MN 14 . The source terminal of transistor MN 11  is coupled to the drain terminal of transistor MN 12 . The source terminals of transistors MN 12  and MN 14  are coupled to a voltage reference (AGND). The drain terminal of transistor MN 14  is coupled to the source terminal of transistor MN 13 . The drain terminal of transistor MN 13  is coupled to the output node V out . 
   The folded cascode OTA circuit generally operates as follows. For the purposes of explanation, current flow due to parasitic capacitance at high speeds is ignored. Transistors MP 8  and MP 10  generate relatively constant currents at their drain terminals. With respect to transistor MP 10 , a portion of the current from the drain terminal of transistor MP 10  flows through the drain terminal of transistor MN 10  and another portion flows through the source terminal of transistor MP 11 . The differential input voltage V inp , V inn  determines how the current from transistor MP 10  is allocated between transistor MN 10  and transistor MP 11 . The current flowing from the drain terminal of transistor MP 11  flows into the output node V out . 
   Similarly, the current flowing from the drain terminal of transistor MP 9  flows into the drain terminal of transistor MN 11 . The same current flowing through transistor MN 11  flows through transistor MN 12 . The gate-to-source voltage of transistor MN 14  is the same as the gate-to-source voltage of transistor MN 12 , and the current through transistors MN 13  and MN 14  should then mirror the current flowing through transistors MN 11  and MN 12 , which in turn, mirror the current flowing through transistor MP 9 . The drain terminal of transistor MN 13  is coupled to the output node V out  to sink current from that node. 
   Various embodiments have been described above. Although described with reference to these specific embodiments, the descriptions are intended to be illustrative and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.