Abstract:
A jittering frequency control circuit and method for a switching mode power supply enlarge the uttering frequency range of the switching frequency of the switching mode power supply when the switching mode power supplier enters a frequency reduction mode, to improve the electro-magnetic interference of the switching mode power supply operating with the frequency reduction mode.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention is related generally to a switching mode power supply and, more particularly, to a jittering frequency control circuit and method for a switching mode power supply. 
       BACKGROUND OF THE INVENTION 
       [0002]    Pulse width modulation (PWM) has been extensively applied to various electronic devices. For example, PWM controllers are used in switching mode power supplies to modulate duty cycles or switching frequencies of power switches and thereby modulate output voltages. 
         [0003]    Recently, due to energy shortages and the rising awareness of environmental protection, the energy saving feature of switching mode power supplies has drawn more and more attention. At the same time, laws and regulations were passed to impose stricter requirements on the power conversion efficiency of switching mode power supplies at light load and in standby mode. When a switching mode power supply is working at light load or in standby mode, the switching loss of its power switches accounts for a significant proportion of the overall power consumption. To increase the light loading and standby power conversion efficiency of switching mode power supplies, some power management integrated circuits (ICs) on the market are designed to lower the switching frequencies of power switches so that switching loss can be significantly reduced. Moreover, switching mode power supplies, though advantageously more compact than conventional linear power supplies, have another problem that electro-magnetic interference (EMI) caused by the switching elements. Jittering frequency technique is typically used to improve EMI problem in existing power management ICs. 
         [0004]    Switching mode power supplies have a variety of types. While the feedback loop and PWM loop designs vary from one type to another, the PWM controllers in all such power supplies generate and control their PWM signals according to output feedback signals, which may be either voltages or currents. For instance, the switching mode power supply shown in  FIG. 1  has a flyback configuration in which the PWM controller  10  needs the output information provided by an isolated feedback circuit that includes an optical coupler  12  and a shunt regulator  14 . The shunt regulator  14  detects the output voltage Vo of the flyback power supply and controls the feedback current Icomp on the pin COMP of the PWM controller  10  accordingly. Based on the feedback current Icomp, a circuit in the PWM controller  10  generates a feedback voltage Vcomp which is proportional to the output voltage Vo. From the feedback voltage Vcomp, the PWM controller  10  can identify whether the flyback power supply is operating at light load or heavy load. 
         [0005]    The flyback power supply shown in  FIG. 1  provides the output power 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
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         [0000]    where Lp is the magnetizing inductance of the transformer T 1 , Rcs is the current sense resistor, Vcs is the voltage across the current sense resistor Rcs, fs is the switching frequency of the power switch M 1 , η is the conversion efficiency of the transformer T 1 , and X 1  and X 2  are constant coefficients. 
         [0006]    The switching frequency of a conventional constant frequency switching mode power supply with jittering frequency is not affected by the output feedback signal. Taking the flyback power supply shown in  FIG. 1  for example, the equation Eq-1 shows that, if the output power Po is fixed, the feedback voltage Vcomp will vary with the jittered switching frequency fs. Referring to  FIG. 2 , the waveform  20  represents the switching frequency fs having a fixed jittering frequency range Δfs, and the waveform  22  represents the feedback voltage Vcomp. The feedback voltage Vcomp decreases as the switching frequency fs increases. However, when working at light load or in standby mode, this type of PWM controller cannot reduce the switching frequency fs according to the feedback voltage Vcomp to reduce switching loss. 
         [0007]    On the other hand, the switching frequency of a conventional variable frequency switching mode power supply with jittering frequency is adjustable by an output feedback signal; that is to say, the light-load or standby-mode switching frequency can be reduced according to the output feedback signal. Taking the flyback power supply shown in  FIG. 1  for example, after entering the light-load (frequency reduction) mode, under a constant output power Po, the variable frequency PWM controller  10  with jittering frequency will lower the switching frequency fs according to the feedback voltage Vcomp. At the same time, however, the feedback voltage Vcomp changes with the jittered switching frequency fs. Thus, a relationship is formed between the feedback voltage Vcomp and the switching frequency fs, and a new stable equilibrium point is eventually reached after back-and-forth adjustments. Referring to  FIG. 3 , the waveforms of the switching frequency fs and of the feedback voltage Vcomp are changed from the waveforms  30  and  32  to the waveforms  34  and  36 , respectively. Because of that, the jittering frequency range of the switching frequency fs is narrowed down from Δfs 1  to Δfs 2 , which nevertheless results in increased EMI during the frequency reduction mode. 
       SUMMARY OF THE INVENTION 
       [0008]    An objective of the present invention is to provide a jittering frequency control circuit and method for a switching mode power supply. 
         [0009]    Another objective of the present invention is to provide a jittering frequency control circuit and method for adjusting a jittering frequency range of a switching mode power supply. 
         [0010]    A further objective of the present invention is to provide a jittering frequency control circuit and method for improving EMI of a switching mode power supply in a frequency reduction mode. 
         [0011]    According to the present invention, a jittering frequency control circuit for a switching mode power supply includes an oscillator and a jittering frequency modulator. The oscillator provides a frequency jittered clock whose frequency determines the switching frequency of the switching mode power supply. The jittering frequency modulator generates a jittering frequency adjust signal according to an output feedback signal and a reference signal and thereby adjusts the range of the jittering frequency. Preferably, when the switching mode power supply enters a frequency reduction mode, the jittering frequency modulator adjusts at least one of the upper limit and the lower limit of the jittering frequency adjust signal, to expand the range of the jittering frequency and thereby improve EMI of the switching mode power supply in the frequency reduction mode. 
         [0012]    According to the present invention, a jittering frequency control method for a switching mode power supply provides a clock having a jittering frequency to determine the switching frequency of the switching mode power supply, and generates a jittering frequency adjust signal according to an output feedback signal and a reference signal to adjust the range of the jittering frequency. Preferably, when the switching mode power supply enters a frequency reduction mode, at least one of the upper limit and the lower limit of the jittering frequency adjust signal is adjusted to expand the range of the jittering frequency and thereby improve EMI of the switching mode power supply in the frequency reduction mode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
           [0014]      FIG. 1  is a circuit diagram of a conventional flyback power supply; 
           [0015]      FIG. 2  shows a relationship between the switching frequency and the feedback voltage of a constant frequency switching mode power supply with jittering frequency; 
           [0016]      FIG. 3  shows a relationship between the switching frequency and the feedback voltage of a variable frequency switching mode power supply with jittering frequency; 
           [0017]      FIG. 4  is a circuit diagram of a PWM controller using a jittering frequency control circuit according to the present invention; 
           [0018]      FIG. 5  is a waveform diagram of a jittering frequency adjust signal and a jittering frequency range; 
           [0019]      FIG. 6  is a circuit diagram of a first embodiment for the jittering frequency modulator shown in  FIG. 4 ; and 
           [0020]      FIG. 7  is a circuit diagram of a second embodiment for the jittering frequency modulator shown in  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Referring to  FIG. 4 , in a PWM controller  10 , the clock CLK needed by the pulse width modulator  38  is provided by a jittering frequency control circuit  40  according to the present invention, to adjust the jittering frequency range of the switching frequency of the PWM signal Vgate. This PWM controller  10  can be applied to a flyback power supply as shown in  FIG. 1  to improve EMI thereof in a frequency reduction mode. As in the known PWM loops, a current limit circuit  42  generates a current limit signal Vc 1  according to the clock CLK, a leading-edge blanking circuit  44  generates a signal Vcs_LEB according to the voltage Vcs received by the pin CS, a multiplier  46  generates a signal Vcs_m according to the signal Vcs_LEB, a slope compensator  48  generates a compensate signal Vs according to the clock CLK, an adder  50  generates a signal Vcs_s according to the signal Vcs_m and the compensate signal Vs, a comparator  52  generates a signal Sc according to the current limit signal Vc 1 , a feedback voltage Vcomp from the pin COMP and the signal Vcs_s, an SR flip-flop  54  generates an output Q according to the clock CLK and the signal Sc, and according to the output Q of the SR flip-flop  54 , a gate driver  56  generates the PWM signal Vgate supplied to the pin GATE to switch the power switch M 1 . The SR flip-flop  54  is triggered by the clock CLK and reset by the signal Sc. The switching frequencies of the PWM signal Vgate and of the power switch M 1  are equal to the frequency fs of the clock CLK. 
         [0022]    In the jittering frequency control circuit  40 , a counter  58  counts the clock CLK to generate a count value CT, a jittering frequency modulator  60  receives the count value CT, the feedback voltage Vcomp and a reference signal Iref provided by the oscillator  62 , and supplies a jittering frequency adjust signal Vm to the oscillator  62 . The oscillator  62  determines the frequency fs of the clock CLK according to the jittering frequency adjust signal Vm and the feedback voltage Vcomp, and the jittering frequency adjust signal Vm controls the jittering frequency range of the clock CLK. 
         [0023]    Referring to  FIGS. 4 and 5 , in the normal operation mode of the flyback power supply, the uttering frequency adjust signal Vm provided by the jittering frequency modulator  60  has an upper limit Vref 3  and a lower limit Vref 5 , as shown by the waveform  66 , and the oscillator  62  compares an internal oscillating signal Vosc with the jittering frequency adjust signal Vm to generate the clock CLK, as shown by the waveform  68 . The oscillating signal Vosc has a constant increasing slope, and thus the frequency fs of the clock CLK decreases or increases as the jittering frequency adjust signal Vm increases or decreases, and a jittering frequency is generated. The upper limit Vref 3  and the lower limit Vref 5  of the jittering frequency adjust signal Vm determine the jittering frequency range Δfs 1  of the frequency fs, as shown by the waveform  64 . Once the flyback power supply enters the frequency reduction mode, the jittering frequency modulator  60  raises the upper limit of the jittering frequency adjust signal Vm from Vref 3  to Vref 4 , and lowers the lower limit from Vref 5  to Vref 6 . As a result, the jittering frequency range is expanded from Δfs 1  to Δfs 3 . Meanwhile, the oscillator  62  lowers the frequency fs of the clock CLK according to the feedback voltage Vcomp, for example, by changing the increasing slope or the starting level of the oscillating signal Vosc according to the feedback voltage Vcomp. As shown in  FIG. 3 , due to the relationship between the feedback voltage Vcomp and the frequency fs, the jittering frequency range Δfs 3  of the frequency fs in the frequency reduction mode will be reduced; however, with Δfs 3  being greater than Δfs 1 , the reduced jittering frequency range Δfs 3  is greater than Δfs 2 . Thus, the EMI problem is improved. The reduced jittering frequency range Δfs 3  is preferably greater than or equal to Δfs 1 . 
         [0024]      FIG. 6  is a circuit diagram of a first embodiment for the jittering frequency modulator  60  shown in  FIG. 4 . In this embodiment, the jittering frequency adjust signal Vm is a voltage provided by a capacitor Cm, the reference signal Iref is a current, a current mirror circuit  76  mirrors the current Iref to generate a charge current I 1  and a discharge current I 2 , an AND gate  72  generates a signal S 3  according to the count value CT and a signal S 2 , an AND gate  74  generates a signal S 4  according to the count value CT and a signal S 1 , a switch SW 1  is connected between the current mirror circuit  76  and the capacitor Cm and, in response to the signal S 3 , switches the charge current I 1  to charge the capacitor Cm, a switch SW 2  is connected between the current mirror circuit  76  and the capacitor Cm and, in response to the signal S 4 , switches the discharge current I 2  to discharge the capacitor Cm, a comparator  70  compares the feedback voltage Vcomp with a threshold Vref 2  to generate a comparison signal VFR, based on the comparison signal VFR, a selector  78  selects one of the normal upper limit Vref 3  and the frequency reduction upper limit Vref 4  to supply to a positive input terminal of the comparator  82 , whose negative input terminal is connected to the capacitor Cm, the comparator  82  compares the voltages at its two input terminals to generate a signal S 5 , based on the comparison signal VFR, a selector  80  selects one of the normal lower limit Vref 5  and the frequency reduction lower limit Vref 6  to supply to the negative input terminal of a comparator  84 , whose positive input terminal is connected to the capacitor Cm, a comparator  84  compares the voltages at its two input terminals to generate a signal S 6 , an SR flip-flop  86  includes NAND gates  88  and  90 , the NAND gate  88  generates the signal S 1  according to the signals S 2  and S 5 , and the NAND gate  90  generates the signal S 2  according to the signals S 1  and S 6 . 
         [0025]    Counters are well known in the art, and the techniques for generating clock signals having a jittering frequency and reducing the frequency of a clock according to an output feedback signal are also well known in the art. Therefore, the internal circuits and operations of the counter  58  and of the oscillator  62  are not detailed herein. 
         [0026]    Referring to  FIGS. 5 and 6 , while the flyback power supply operates in the normal operation mode, the feedback voltage Vcomp is greater than the threshold Vref 2 , the comparison signal VFR generated by the comparator  70  is high, and consequently, the selector  78  selects the normal upper limit Vref 3  for the positive input terminal of the comparator  82  as the upper limit of the jittering frequency adjust signal Vm, and the selector  80  selects the normal lower limit Vref 5  for the negative input terminal of the comparator  84  as the lower limit of the jittering frequency adjust signal Vm. Once the flyback power supply enters the frequency reduction mode, the feedback voltage Vcomp is lower than the threshold Vref 2 , so the comparison signal VFR generated by the comparator  70  is low. As a result, the selectors  78  and  80  select the frequency reduction upper limit Vref 4  and the frequency reduction lower limit Vref 6  as the upper and lower limits of the jittering frequency adjust signal Vm, respectively. 
         [0027]    In the embodiment shown in  FIG. 6 , the jittering frequency modulator  60  expands the jittering frequency range of the clock CLK by adjusting the upper and lower limits of the jittering frequency adjust signal Vm. In other embodiments, however, it is feasible to adjust only the upper or lower limit of the jittering frequency adjust signal Vm to expand the jittering frequency range of the clock CLK. 
         [0028]      FIG. 7  is a circuit diagram of a second embodiment for the jittering frequency modulator  60  shown in  FIG. 4 . As in the circuit of  FIG. 6 , the comparator  70  compares the feedback voltage Vcomp with the threshold Vref 2  to generate the comparison signal VFR. A current-to-voltage converter  96  has an input terminal to receive the reference current Iref. A current source  92  provides an adjust current IFR, and a switch  94  is connected between a current source  92  and the input terminal of the current-to-voltage converter  96  and is controlled by the comparison signal VFR. A voltage Vcv generated by the current-to-voltage converter  96  is converted by voltage-to-current converters  98 - 106  into currents I 3 -I 7 , respectively, a switch  108  is connected between an output terminal of a voltage-to-current converter  98  and an input terminal of the current-to-voltage converter  118 , a switch  110  is connected between an output terminal of the voltage-to-current converter  100  and the input terminal of the current-to-voltage converter  118 , a switch  112  is connected between an output terminal of the voltage-to-current converter  102  and the input terminal of the current-to-voltage converter  118 , a switch  114  is connected between an output terminal of the voltage-to-current converter  104  and the input terminal of the current-to-voltage converter  118 , a switch  116  is connected between an output terminal of the voltage-to-current converter  106  and the input terminal of the current-to-voltage converter  118 . The count value CT coming from the counter  58  includes bits B 0 -B 4  to control the switches  108 - 116  and thereby turn on or off the voltage-to-current converters  98 - 106 , respectively, the total current Isum to the input terminal of the current-to-voltage converter  118  is thus determined, and the current-to-voltage converter  118  converts this total current Isum into the jittering frequency adjust signal Vm. When the flyback power supply enters the frequency reduction mode, the comparison signal VFR turns on the switch  94  and thereby turns on the current source  92 , allowing an adjust current IFR to flow to the input terminal of the current-to-voltage converter  96 , so that the output voltage Vcv of the current-to-voltage converter  96  increases, and the currents I 3 -I 7  provided by the voltage-to-current converters  98 - 106  increase with the voltage Vcv. This increases the maximum value of the total current Isum and raises the upper limit of the jittering frequency adjust signal Vm; as a result, the jittering frequency range of the frequency fs of the clock CLK is enlarged. While the embodiment of  FIG. 7  expands the jittering frequency range of the clock CLK by adjusting the upper limit of the jittering frequency adjust signal Vm, it is feasible in other embodiments to expand the jittering frequency range of the clock CLK by adjusting the lower limit of the jittering frequency adjust signal Vm instead. 
         [0029]    The embodiment shown in  FIG. 4  is a circuit designed only to illustrate the principles of the present invention; therefore, the present invention is by no means limited to that particular circuit alone. As shown by the embodiment of  FIG. 4 , the present invention uses the jittering frequency control circuit  40  to replace the conventional clock generator, and the jittering frequency control circuit  40  controls the jittering frequency range of the clock CLK according to the feedback voltage Vcomp for achieving the purpose of the present invention. Hence, there is no need to modify the other circuits of the PWM controller  10  when adopting the jittering frequency control circuit  40 . This also means that the solution proposed by the present invention is equally applicable to other types of switching mode power supplies and a variety of PWM controllers. In other embodiments, the output feedback signal used by the jittering frequency control circuit  40  can be either a voltage or a current, and the reference signal can also be a voltage or a current. 
         [0030]    While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.