Abstract:
Recovery of eight-bit data characters imbedded in the time slots of a train of data bytes individually having six slots available is implemented by a process which locates the bit alignment of a first one of the characters and executes a sequence of assembly procedures to appropriately form this and subsequent characters. The data characters are available as bursts of data characters preceded by synchronizing words having a predetermined bit sequence to create data blocks, the sequential bits of the block being inserted in sequential available slots of the byte train. Recovery is accomplished by comparing the bits of each byte with stored patterns corresponding to overlapping portions of the synchronizing word. A comparison match identifies the bit location of the first character in the burst to thereby define one of a plurality of assembly procedures which process the bits in the identified locations to form the character. The assembly procedure then defines the next subsequent assembly procedure to be executed.

Description:
TECHNICAL FIELD 
     This invention relates to the recovery of data characters and, more particularly, to recovering a block of message data characters whose character bits have been imbedded in a date byte train. 
     BACKGROUND OF THE INVENTION 
     Common carriers now provide all-digital central office facilities for data subscribers. In conjunction with one type of digital facility, the date customer provides a synchronous data bit stream at certain ones of different signaling rates and code formats, the digital facility imbeds this data stream into data bytes which are conveyed with the data of other subscribers through the use of, for example, multiplexers to remote carrier offices and the customer data is there reconverted to the original synchronous data bit stream for transmission to a terminating data terminal or base. A common carrier office facility of this type is shown in Reissue U.S. Pat. No. Re 29,215, issued May 10, 1977 to A. C. Carney et al. 
     The message data information that the subscriber intends to convey to the terminating data terminal (or data base) may take the form of a burst of message data characters. The initial portion of the data burst customarily includes a control or synchronizing code word having a predetermined bit sequence. This code word indicates that a stream of data characters immediately follow, the code word and following characters forming a data block. This date block is transmitted by the subscriber as a sychronous data stream at the appropriate signaling rate to the common carrier facility of the type described above. The common carrier facility imbeds the code word and data character bits of the customer&#39;s data into the &#34;character&#34; bit time slots of the byte train (other bits or time slots of each byte being reserved for housekeeping and control purposes). This is advantageously accomplished by reading successive groups having a fixed number of bits (six in the Carney et al reissue patent) from the synchronous data stream and inserting the bits of each group into time slots of each of successive bytes of the byte train. Since the customer code format customarily provides data characters having a different fixed number of bits (in excess of six) and code words that consist of two characters, it is apparent that each of the message characters will be imbedded into two, and sometimes three, successive bytes in the train, each of the code words will be imbedded in three or more successive bytes and corresponding bits of the several characters will be imbedded in different locations in the several bytes. 
     The bytes with the imbedded bits are multiplexed with bytes containing data from other customers for transmission to a remote carrier office which demultiplexes the multiplexed bytes and recovers the synchronous stream for transmission to the terminating subscriber. This latter subscriber looks for the synchronizing code word and, upon its detection, recognizes that the first data character in the burst is located immediately thereafter, enabling the reassembling of the characters in the original data burst. 
     It is sometimes necessary for a remote digital facility to reassemble a data burst from an incoming byte train. This may be necessary when the remote facility is the recipient of the message information, requires addressing information in the burst to properly direct the message or for other similar reasons. The remote facility, of course, may recover the original synchronous stream and, thereafter, look for the synchronizing code word whereupon, upon detection of the code word, the facility may initiate the reassembling of the data characters in the burst. This, however, requires two sequential operations before the assembling operation can take place. 
     It is an object of this invention to determine the location of bits of data characters imbedded in a data byte train. It is a more specific object of this invention to use fewer and simpler operations to determine the locations of the character bits. 
     SUMMARY OF THE INVENTION 
     This invention accomplishes the above-stated objects by detecting one of a plurality of bit patterns in the character bits of a byte, the bit patterns comprising different overlapping portions of the synchronizing word and by thereby identifying the bit locations in the byte train of imbedded bits of at least one (and advantageously the first) character in the data burst. 
     In the illustrative embodiment of this invention, described in detail hereinafter, bit patterns corresponding to the different overlapping synchronizing word portions are stored, noncharacter bits of each byte are masked and the unmasked character bits of each byte are compared with the bits of each stored pattern until a match is detected. The bits of the next byte are then compared with bits of stored patterns corresponding to synchronizing portions that follow the overlapping portion to confirm that a synchronizing word has been detected. 
     In accordance with a feature of this invention, the imbedded bits in the identified locations are assembled into data characters. More particularly, one of a plurality of assembly procedures is executed, the one procedure being defined in accordance with the bit location alignment that has been defined. In general, execution of the assembly procedure involves the processing of bits of subsequent bytes in the byte train to form the one character in the burst (which is advantageously the first character). 
     In accordance with a further feature of this invention, the execution of the assembly procedure for each data character includes the defining of the assembly procedure for the next data character. 
     The foregoing and other objects and features of this invention will be more fully understood from the following description of an illustrative embodiment taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 discloses, in block form, the arrangement of various equipment including a processor which may be used in a central office facility to recover data characters from a byte train in accordance with this invention; 
     FIGS. 2 and 3, when arranged side-by-side, depict a flow diagram of a process followed by the processor for detecting bit patterns and identifying bit locations in the byte train; 
     FIGS. 4 and 5 show individual subroutines which are used in the detecting and identifying process; and 
     FIGS. 6, 7 and 8 depict instructions and accompanying remarks for various routines of a process followed by the processor for assembling data characters. 
    
    
     DETAILED DESCRIPTION 
     The incoming byte stream to be processed appears on lead pair 101 in FIG. 1 and is applied to data terminator 102. This byte stream is of the type described in Reissue U.S. Pat. No. Re 29,215, as described in the reissue patent, the byte stream constitutes a stream or train of 8-bytes. The particular format of each 8-bit byte involves an initial control bit, a final housekeeping bit and six intermediate bits which contain customer message data. As is further described in the reissue patent, the customer message data may be comprised of an 8-bit synchronous data stream, successive 6-bit portions of the stream being imbedded into successive bytes. 
     When the customer sends a message, the initial portion constitutes a synchronizing word comprising two 8-bit characters having a predetermined bit pattern followed by a stream of 8-bit message data characters and terminated by an end-of-message (EOM) word. The transmission network inserts the bits of this message data stream, six bits at a time, into each of the above-described bytes. This stream is eventually applied to data terminator 102 and serially applied to the D input of shift register 106. 
     The transmission network office described in the reissue patent includes therein a 64 kbs clock and an 8 kbs byte clock. The 64 kbs and 8 kbs clock signals are conveyed on leads 103 and 104 and are passed to clock terminator circuit 105. Clock terminator circuit 105 derives a bit clocking pulse from the 64 kbs bit clock signal and this clocking pulse is passed to the &#34;T&#34; input of shift register 106. The bits in the byte stream are thereby passed from data terminator 101 into shift register 106 and shifted through. 
     The processing of the data stream is provided by a microcomputer which includes in/out chip circuit 107, processor (CPU) 108, random access memory (RAM) 109 and read-only memory (ROM) 110. CPU 108 is a processor which may advantageously comprise the Motorola 6800 microprocessor, which microprocessor communicates data signals by way of a two-way data bus generally indicated by bus 111 and sends address signals over an address and control bus generally indicated by bus 112. Associated with CPU 108 and connected to data and address buses 111 and 112 are the above-described in/out circuit 107 and the RAM 109 and ROM 110. 
     The ROM 110 is a conventional read-only memory having eight rows of 1024 bits of storage, which storage includes predetermined portions of the known bit pattern of the synchronizing word of the customer message and further includes various instructions for algorithms for processing data received by in/out circuit 107. These algorithms include a first &#34;synchronizing&#34; routine providing instructions for determining the alignment of the bits of the message characters in the customer&#39;s message imbedded in the incoming bytes and a second &#34;assembling&#34; routine providing instructions for assembling the bits into message characters and storing the assembled message characters. The RAM 109 is a conventional random access memory capable of storing eight rows of 256 bits. A function of the RAM 109 is to provide temporary storage of message data characters which have been assembled by the CPU 108 in accordance with the instructions stored in ROM 110. 
     The algorithm which defines the synchronizing process for determining the alignment of the imbedded bits of the message character words can be more readily understood by one having reasonable skill in the art by referring to the flow chart in FIGS. 2-5. This process may be started or initiated after the termination of a previously received message, as described hereinafter. When this situation is ascertained by the CPU 108, it addresses the ROM 110 to obtain a sequence of instructions defining an initial subroutine symbolically shown as block 200. In accordance with these instructions, CPU 108 obtains a first number N1 defining the maximum number of message characters for a message and inserts this number in a register (NOCHRS) and obtains a second number defining an address in RAM 109 for loading assembled characters. After executing subroutine 200, the process advances to the subroutine &#34;GET&#34; which is symbolically shown by block 201 in FIG. 2 and disclosed in detail in FIG. 4. In accordance with these subroutine instructions, as shown in FIG. 4, the microprocessor awaits the reception of an incoming byte and the insertion of the byte into in/out circuit 107, which insertion is defined by the ready read signal applied to the in/out circuit. Upon recognition of the ready read signal, the CPU sequentially addresses the in/out circuit to read the byte stored therein, stores the byte read from in/out circuit 107 into an 8-bit accumulator (designated register &#34;A&#34;) in the CPU 108 (see FIG. 1) and masks the first and last bits of the byte whereby the six intermediate bits are stored in CPU register &#34;A&#34;. 
     Upon the completion of subroutine &#34;GET&#34;, the microprocessor returns to the synchronization process and, more specifically, to decision 202. The instructions in ROM 110 for decision 202 instructs CPU 108 to examine the final or housekeeping bit of the byte read from in/out circuit 107 to determine if this is a control byte or a data byte. If this byte is a control byte, decision 202 returns the process back to subroutine 201. If this byte is a data byte, the process advances to decision 203. 
     In accordance with the instruction obtained from the ROM 110 for decision 203, the CPU 108 obtains from the ROM 110 a 6-bit pattern, which 6-bit pattern corresponds to a specific sequential 6-bit portion of the synchronizing character word pair. As seen in decision 203, this sequential bit portion constitutes the final two bits (G and H) of a synchronizing character and the initial four bits (A, B, C and D) of the next subsequent synchronizing character. A match of this bit portion thus obtained from the ROM is made with the six bits in register &#34;A&#34;. If there is a mismatch, the process then proceeds to decision 204. Alternatively, if this is a match, the process jumps to subroutine 210 which constitutes subroutine &#34;GET&#34; shown in FIG. 4. This match confirms that the byte contains a portion of the synchronizing word and, more specifically, a specific one of the different bit portions of a synchronizing word. This will lead to the defining of the alignment of the bits of the subsequent message characters and, more specifically, to the determination of the locations of the various message character bits in the following incoming bytes to enable the subseqent assembling of the characters. 
     Assume now that there is a match and the process has jumped to subroutine 210. Subroutine 210 constitutes the series of instructions which constitute subroutine &#34;GET&#34;. Accordingly, CPU 108 proceeds to execute the instructions, described above, to wait for the ready read signal and, upon the signal being obtained from clock terminator 105, to read out the new incoming byte in in/out circuit 107, storing this byte in register &#34;A&#34; and masking out the initial and final bits (bits 1 and 8) of the byte. This completes the subroutine &#34;GET&#34; and the CPU 108 returns to the synchronizing process, advancing to decision 221. 
     For decision 221 the CPU 108 is instructed to obtain from ROM 110 a 4-bit pattern which corresponds to the final four bits (E, F, G, H) of a synchronizing character. A match of this bit portion obtained from the ROM is made with the bits in the first four unmasked stages of register &#34;A&#34;, which bits constitute the last four bits of the byte obtained, in time, from the customer data. If there is a mismatch, the process then proceeds back to decision 202. Alternatively, if there is a match, the presence of the synchronizing word leading to the defined alignment is confirmed and the process advances to subroutine 301 (FIG. 3). 
     Subroutine 301 comprises the instructions of subroutine &#34;GET 2&#34; which is disclosed in detail in FIG. 5. In accordance with the instructions in subroutine &#34;GET 2&#34;, as shown in FIG. 5, CPU 108 awaits the reception of the next incoming byte and its insertion into in/out circuit 107, as indicated by the application of the ready read signal to the in/out circuit by clock terminator 105. Upon recogition of this ready read signal, the CPU 108 sequentially addresses the in/out circuit 107 to read the byte stored therein and to store the byte in a CPU 108 register hereinafter designated as register &#34;B&#34; as shown in FIG. 1. The byte is also stored in register &#34;HBYTE&#34;, for reasons discussed hereinafter. This completes subroutine &#34;GET 2&#34; and the process returns to the &#34;synchronizing&#34; routine and advances to &#34;load index&#34; routine 321. More specifically, CPU 108 loads the address of &#34;SPOKE 6&#34; of the assembly routine into its index register and the process advances to exit point 331 which jumps to entry points of the assembly routine, described hereinafter. 
     Assume now that the CPU 108 finds a mismatch in decision 203 and proceeds to decision 204 as described above. In this event the CPU obtains from the ROM 110 a 6-bit pattern which corresponds to a different sequential 6-bit portion of the synchronizing character word pair. Specifically, as seen in decision 204, this sequential bit portion constitutes the final three bits (F, G, H) of a synchronizing character and the initial three bits (A, B, C) of the next subsequent synchronizing character. A comparison of this bit portion is now made with the six bits in register &#34;A&#34;. If there is a mismatch, the process proceeds to decision 205. Alternatively, if there is a match, the process jumps to subroutine 211. 
     Assume now that the decision 204 finds a bit portion match and the process advances to subroutine 211. Subroutine 211 contains the instructions of subroutine GET. Accordingly, CPU 108 now proceeds to wait for the ready read signal from clock terminator 105 and thereupon reads the next incoming byte out of in/out circuit 107, storing the byte in register &#34;A&#34; and masking the initial and final bits of the byte. The process then returns to the &#34;synchronizing&#34; routine, advancing to decision 222. The CPU 108 for this decision is instructed by ROM 110 to obtain a 4-bit pattern in the ROM which constitutes the fourth through seventh bits (D, E, F, G) of a synchronizing character. This 4-bit pattern is then compared with the bits in the first four unmasked stages of register &#34;A&#34;. If there is a mismatch, the process returned to decision 202. Alternatively, if there is a match, the process jumps to subroutine 302. 
     The instructions for subroutine 303 constitute the instructions for subroutine &#34;GET 2&#34;. Accordingly, the next incoming byte is read out of in/out circuit 107 and inserted into register &#34;B&#34; and register &#34;HBYTE&#34;. The process then goes to routine 322 wherein CPU 108 loads the address of &#34;SPOKE 7&#34; of the assembly routine into the index register. The process thereafter advances to exit point 332 wherein the process jumps to an appropriate entry point of the assembly routine. 
     In the event that when the process is in decision 204 CPU 108 finds a mismatch, the process proceeds to decision 205 as described above. In this event, CPU 108 obtains from ROM 110 a 6-bit pattern constituting a final four bits (E, F, G, H) of the synchronizing character followed by the initial two bits (A, B) of the (next subsequent) synchronizing character. A match of this bit portion pattern is made with the the six bits in register &#34;A&#34;. If there is a mismatch, the process proceeds to decision 206. Alternatively, if there is a match, the process jumps to subroutine 212. 
     Assume now that there is a match and the process has jumped to subroutine 212. The instructions for subroutine 212 constitutes the instructions of subroutine &#34;GET&#34;. Accordingly, CPU 108 executes the subroutine instructions described above, waiting for the ready read signal and, upon the signal being obtained from the clock terminator 105, reading out the new incoming byte from in/out circuit 107, storing this byte in register &#34;A&#34; and masking out the initial and final bits of the byte. Upon the completion of this subroutine 212, CPU 108 returns to the synchronizing routine whereby the process advances to decision 223. In decision 223 CPU 108 is instructed to obtain from ROM 110 a 4-bit pattern which corresponds to the third through sixth bits (C, D, E, F) of the synchronizing character. This 4-bit sequence is then compared with the bits in the first four unmasked stages of register &#34;A&#34;. If there is a mismatch, the process returns to decision 202. Alternatively, if there is a match, the process jumps to subroutine 303. 
     The instructions for subroutine 303 constitutes the instructions of the subroutine &#34;GET&#34;. CPU 108 thereupon proceeds to wait for the ready read signal and, upon detecting the signal, reads the next subsequent incoming byte now stored in in/out circuit 107 and stores the byte in register &#34;A&#34;, masking the initial and final bits of the byte. The process then returns to the synchronizing routine advancing to subroutine 310. Subroutine 310 comprises the instructions of subroutine &#34;GET 2&#34;. With the process in subroutine &#34;GET 2&#34;, CPU 108, as described above, awaits the next ready read signal and thereupon addresses the in/out circuit to read out the next subsequent incoming byte stored in in/out circuit 107, loading the byte into register &#34;B&#34; and register &#34;HBYTE&#34;. This completes subroutine &#34;GET 2&#34;, whereupon the process returns to the synchronizing routine and, more specifically, to subroutine 310 wherein CPU 108 loads the &#34;SPOKE 2&#34; address into the index register. The process then advances to the exit point 333 which jumps to an appropriate entry point of the assembly routine and, more specifically, to &#34;SPOKE 2&#34; of the assembly routine. 
     In the event that when the process is in decision 205 CPU 108 finds a mismatch, the process advances to decision 206. CPU 108 obtains from ROM 110 the sequential 6-bit portion of the synchronizing character word pair constituting the final five bits (D, E, F, G, H) of the synchronizing character followed by the initial bit (A) of the (next subsequent) synchronizing character. If there is a mismatch with the six bits in register &#34;A&#34;, the process proceeds to decision 207. Alternatively, if there is a match, the process jumps to subroutine 213. 
     Subroutine 213 constitutes the instructions for subroutine &#34;GET&#34; and CPU 108 thereupon obtains the next incoming byte for insertion into register &#34;A&#34;, masking the initial and final bits of the byte. The process returns to the synchronizing routine advancing to decision 224. CPU 108 obtains a 4-bit pattern which constitutes the second through fifth bits (B, C, D, E) of the synchronizing character. If this 4-bit sequence does not match with the first four unmasked stages of register &#34;A&#34;, the process returns to decision 202. Alternatively, if there is a match, the process jumps to subroutine 304. 
     Subroutine 304 constitutes the instructions of subroutine &#34;GET&#34; and CPU 108 thereupon obtains the next incoming byte for storage in register &#34;A&#34;, masking out the initial and final bits of the byte. The process then proceeds to subroutine 311 which constitutes the instructions for subroutine &#34;GET 2&#34;. CPU 108 then proceeds to obtain the next subsequent incoming byte from in/out circuit 107 storing this byte in register &#34;B&#34; and register &#34;HBYTE&#34;. The process then returns to the synchronizing routine, and, more specifically, to subroutine 324, storing the address of &#34;SPOKE 3&#34; in the index register and then advancing to exit point 334 which leads to an appropriate entry point of the assembly routine and, more specifically, to &#34;SPOKE 3&#34; of the assembly routine. 
     If the result of decision 206 is a mismatch, the process advances to decision 207, CPU 108 obtains from ROM 111 a 6-bit portion pattern of the synchronizing character word pair constituting the final six bits (C, D, E, F, G, H) of a synchronizing character. A comparision of this bit portion is made with the six bits in register &#34;A&#34;. If there is a mismatch, the process proceeds to decision 208. If there is a match, the process jumps to subroutine 214. 
     Subroutine 214 provides the instructions of subroutine &#34;GET&#34; and CPU 108 thereupon obtains the next incoming byte from in/out circuit 107 and stores this byte into register &#34;A&#34;, masking the initial and final bits of the byte. The process then returns to the synchronizing routine advancing to decision 225. CPU 108 obtains a 4-bit pattern which constitutes the first through fourth bits (A, B, C, D) of a synchronizing character. This 4-bit sequence is compared with the first four unmasked stages of register &#34;A&#34;. If there is a mismatch, the process returns to decision 202. If there is a match, the process jumps to subroutine 305. 
     Subroutine 305 constitutes the instructions of subroutine &#34;GET&#34; whereupon CPU 108 obtains the next incoming byte and inserts this byte into register &#34;A&#34;, masking the initial and final bits of the byte. The process then returns to the synchronizing routine advancing to subroutine 312. Subroutine 312 constitutes the instructions of subroutine &#34;GET 2&#34;. CPU 108 therefore obtains the next subsequent incoming byte, inserting the byte into register &#34;B&#34; and register &#34;HBYTE&#34;. The process now returns to subroutine 325 of the synchronizing routine, loading the address of &#34;SPOKE 4&#34; into the index register and advancing to exit point 335 which leads to the assembly routine and, more specifically, to &#34;SPOKE 4&#34; of the assembly routine. 
     Assume now that decision 207 results in a mismatch and the process advances to decision 208, as previously described. CPU 108 obtains from the ROM 110 a 6-bit pattern which corresponds to the second through seventh bits (B, C, D, E, F, G) of a synchronizing character and matches this bit portion with the six bits in register &#34;A&#34;. If there is a mismatch, the process proceeds back to subroutine 201. Alternatively, if there is a match, the process jumps to subroutine 215. 
     In subroutine 215, CPU 108 obtains the next subsequent incoming byte and inserts into register &#34;A&#34; masking the initial and final bits of the byte. The process then returns to the synchronizing routine advancing to decision 226. CPU 108 obtains a 4-bit pattern which constitutes the final bit (H) of a synchronizing character followed by the initial three bits (A, B, C) of a next synchronizing character. This 4-bit sequence is compared with the bits in the first four unmasked stages of register &#34;A&#34;. If there is a mismatch, the process returns to decision 202. Alternatively, if there is a match, the process jumps to subroutine 306 which constitutes the instructions for subroutine &#34;GET&#34;. CPU 108 thereupon obtains the next subsequent byte from in/out circuit 107 and then inserts the byte into register &#34;A&#34; masking the initial and final bits of the byte. The process then returns to the synchronizing routine advancing to subroutine &#34;GET 2&#34;. CPU 108 obtains the next subsequent incoming byte and inserts this byte into register &#34;B&#34; and register &#34;HBYTE&#34;. The process then returns to subroutine 326 of the synchronizing routine, loading the address of &#34;SPOKE 5&#34; into the index register and advancing to exit point 336 which leads to the assembly routine and, more specifically, to &#34;SPOKE 5&#34; of the assembly routine. 
     The instructions and remarks of the various portions of the assembly routine are shown in FIGS. 6-8. The instructions and remarks for the even numbered &#34;SPOKES&#34; of the assembly routine are shown in FIG. 6 while the instructions and remarks for the odd numbered &#34;SPOKES&#34; are shown in FIG. 7. With these instructions and remarks, there is also shown the various storage conditions of register &#34;A&#34; and register &#34;B&#34; and the conditions of a 1-bit carry register. 
     Assume now that CPU 108, when performing decisions 205 in the synchronizing routine, found a match and subsequently, when performing decisions 223, also found a match with the bits in register &#34;A&#34;. The next incoming byte is then placed in register &#34;A&#34; and the following byte is placed in register &#34;HBYTE&#34; and in register &#34;B&#34; by subroutines 303 and 310, as previously described and the address of &#34;SPOKE 2&#34; is loaded into the index register. Under this condition the first six bits of the first data character in the message following the synchronizing character pair word are stored in register &#34;A&#34; and the last two bits are stored in register &#34;B&#34;. This storage condition is depicted for the several registers in FIG. 6 remarks for the instructions associated with the &#34;SPOKE 2&#34; entry point. 
     In accordance with the first set of instructions (1. ROL A) for the &#34;SPOKE 2&#34; subroutine of the assembly routine, the bits in register &#34;A&#34; are rotated to the left. As indicated in the corresponding remarks, this shifts the first six bits of the data character into the leftmost stages of register &#34;A&#34;. For the next two sets of instructions (2. ROR B and 3. ROR B) of the &#34;SPOKE 2&#34; subroutine, the bits in register &#34;B&#34; are twice rotated to the right and this results in first shifting the last two bits of the character into the two rightmost stages of register &#34;B&#34; and then shifting the next to last (G) bit into the carry register and shifting the last (H) bit into the rightmost stage of register &#34;B&#34;. 
     The next instruction (4. ROR A) rotates register &#34;A&#34; to the right, thereby shifting all of the bits in register &#34;A&#34; one stage and, in addition, shifting the G bit from the carry register into the leftmost stage of register &#34;A&#34;. The following two sets of instructions (5. ROR B and 6. ROR A) rotate the bits in register &#34;B&#34; to the right to shift the final bit (H) into the carry register and rotate the bits in register &#34;A&#34; to the right to shift the final bit (H) into the leftmost stage of register &#34;A&#34;, shift the first bit (A) into the rightmost stage of register &#34;A&#34; and shift the remaining bits into the corresponding intermediate stages. It is apparent at this time that the first data character is now fully assembled in register &#34;A&#34;. The next set of instructions (7. LDX#LSP4) in the process then loads the address of the next &#34;SPOKE&#34; into the index register, which next address defines &#34;SPOKE 4&#34;. The next instruction (8. JMP CHKWRD) then advances the process to the check word (CHKWRD) subroutine which will check the assembled character in register &#34;A&#34; and store the character, if appropriate, or provide any other appropriate action. 
     The instructions and remarks for the &#34;CHKWRD&#34; subroutine are shown in FIG. 8. In accordance with the first set of instructions (1. CMP A) of the subroutine, a comparison is made between the data character now assembled in register &#34;A&#34; and an end-of-message (EOM) character stored in a predetermined location in ROM 110. If there is a mismatch, the process advances to the set of instructions (3. CMP A). In the event, however, that there is a match, the process terminates the assembling of the message characters and proceeds to process the message previously stored in a character stack or queue in RAM 109. This message processing may comprise any conventional routine for delivering the message. For example, ROM 110 might contain a routine instructing CPU 108 to remove the data characters of the message stored in the queue or stack, one at a time and sequentially pass the characters to in/out circuit 107 which then transmits the message onto output lead 115. 
     At the termination of the delivery routine, the process goes to &#34;START&#34; in the synchronizing routine where, as previously described, the process is initialized by placing the appropriate number (N1) corresponding to the maximum number of data characters of a message into a first predetermined temporary store (NOCHRS) in RAM 109 and by placing a second number (N2) defining the address pointer to the input stage of the message stack in a second predetermined temporary store (SP) in RAM 109. The synchronizing routine then re-resumes as previously described. 
     Assume now that CPU 108 has determined that the first check instruction (1. CMP A) of the character in register &#34;A&#34; for an end-of-message character does not find a match and that the character is not EOM. The &#34;CHKWRD&#34; subroutine then proceeds to the second check or comparison instruction set (3. CMP A) to determine if the character is a &#34;FILL&#34; character. If CPU 108 finds a match, the routine proceeds directly to subroutine &#34;NXBYTE&#34;, described hereinafter. This has the effect of not storing the &#34;FILL&#34; character in the RAM buffer stack. 
     In the event that the (3. CMP A) instructions that check for a &#34;FILL &#34; character do not find a match, the &#34;CHKWRD&#34; subroutine proceeds to set of instructions (5. DEC). In accordance with these instructions, the number loaded into the &#34;NOCHRS&#34; store by the initializing subroutine of the synchronizing routine is decremented and CPU 108 checks the new number to be sure that it is not a negative number indicating that the buffer stack is full. In the event that the number is negative, the routine goes to instructions (6. BMI) which provides a conventional error routine wherein CPU 108 advantageously obtains an error message from ROM 110, passing the error message to I/O circuit 107 to thereby send the message over line 115. After the error routine is completed, the process returns to &#34;START&#34; in the synchronizing routine to re-initiate the process and re-resume the routine as previously described. 
     If the &#34;NOCHRS &#34; number is not negative indicating available storage in the buffer stack, the routine goes to instructions (7. PSH A). These constitute conventional instructions for obtaining the data bits in register &#34;A&#34; and loading them into the input or initial stage of the RAM buffer stack, which stage is defined by the address (N2) previously placed in register SP as part of the initializing subroutine 200 of the synchronizing routine. At the conclusion of this storing of the assembled data character into the stack, the process proceeds to subroutine &#34;NXBYTE&#34;. 
     The initial instructions of subroutine &#34;NXBYTE&#34; constitute instructions (1. LDA B and 2. BPL) which form a loop that checks for the ready read signal applied by terminator 105 to I/O circuit 107. The exit from this loop occurs when the ready read signal is detected, whereupon the process exits at instruction (3. LDA B). Instruction (3. LDA B) now obtains the new incoming byte from I/O circuit 107, inserting this byte into register &#34;B&#34;. The next instruction (4. LDA A) loads into register &#34;A&#34; the byte presently stored in register &#34;HBYTE&#34;, which byte as previously described was stored therein by the &#34;GET 2&#34; subroutine 210 and constitutes the byte stored in register &#34;B&#34; during the &#34;SPOKE 2&#34; subroutine. Accordingly, the byte now in register &#34;A&#34; contains the first part of the next subsequent message character and the byte stored in register &#34;B&#34; contains the second or final part of the next message character. The next instruction (5. STA B) obtains the byte now stored in register &#34;B&#34; and stores this byte into the &#34;HBYTE&#34; register of RAM 109. The subroutine now terminates with instruction (6. JMP X), the appropriate &#34;SPOKE&#34; subroutine, which subroutine is defined by the address stored in the index register. This address, as previously described, presently being the address for &#34;SPOKE 4&#34;. 
     The &#34;SPOKE 4&#34; subroutine of the assembly routine may be entered from the (6. JMP X) instruction in the &#34;NXBYTE&#34; subroutine, as described above, or from exit point 335 in the synchronizing routine, as previously described. In either event, the first four bits of the next subsequent data character in the message are stored in register &#34;A&#34; and the last four bits are stored in register &#34;B&#34;, the bits of the byte stored in register &#34;B&#34; being also stored in register &#34;HBYTE&#34;. The storage condition for registers &#34;A&#34; and &#34;B&#34; is depicted in FIG. 6 under the remarks for the instructions associated with the &#34;SPOKE 4&#34; entry point. 
     In accordance with the initial ten instructions for the &#34;SPOKE 4&#34; subroutine of the assembly routine, the bits in registers &#34;A&#34; and &#34;B&#34; are rotated until all of the bits of the data character are appropriately aligned in register &#34;A&#34;. The next set of instructions (11. LDX#LSP6) in the subroutine then loads the address of the next &#34;SPOKE&#34; into the index register, which next address defines &#34;SPOKE 6&#34;. The next instruction (12. JMP CHKWRD) then advances the process to the check word (CHKWRD) subroutine which will check the assembled character in register &#34;A&#34; and store the character, if appropriate, or provide any other appropriate action as described above. 
     The instructions and remarks for the &#34;CHKWRD&#34; routine are shown in FIG. 8 and, as previously described, checks to see whether the data character is an EOM character, in which event, the message in the buffer stack is delivered to lead 115 and the process goes to &#34;START&#34; in the synchronizing routine, checks to see if the character is a &#34;FILL&#34; character whereupon the process goes directly to subroutine &#34;NXBYTE&#34; without storing the character in the buffer queue and checks to see if the buffer is full, in which event, an error message is sent to lead 115 and the process returns to &#34;START&#34;. Assuming none of the above conditions exists, the character in register &#34;A&#34; is loaded into the buffer stack and the process proceeds to subroutine &#34;NXBYTE&#34;. In this subroutine, the next incoming byte is loaded into register &#34;B&#34;, the byte in register &#34;HBYTE&#34; is loaded into register &#34;A&#34; and the byte in register &#34;B&#34; is loaded into register &#34;HBYTE&#34;. The first two bits of the next character is therefore now in register &#34;A&#34; and the last six bits are in register &#34;B&#34;. At this point the process jumps to the next &#34;SPOKE&#34; subroutine which comprises &#34;SPOKE 6&#34;. 
     The &#34;SPOKE 6&#34; subroutine can be entered from the &#34;NXBYTE&#34; subroutine, as described above, or from exit point 331 in the synchronizing routine, as previously described. The first six instructions of the &#34;SPOKE 6&#34; subroutine rotates the bits in registers &#34;A&#34; and &#34;B&#34; until all of the bits of the data character are in register &#34;B&#34;. The next instruction set (7. TBA) transfers the bits in register &#34;B&#34; to register &#34;A&#34; whereby the latter register contains all of the bits of the data character. At this point, the address of the &#34;EVEN SPOKE&#34; is entered into the index register by instruction 8. LDX#EVEND and instruction 9. JMP CHKWRD jumps the process to subroutine &#34;CHKWRD&#34;. As previously described, with the process in subroutine &#34;CHKWRD&#34;, the data character is checked as to whether or not it is an EOM character or a &#34;FILL&#34; character and the &#34;NOCHR&#34; number is decremented and checked to indicate if the buffer is full. If none of these conditions exist, the character is loaded into the buffer stack and the process advances to subroutine &#34;NXBYTE&#34;. In this subroutine, the next incoming byte is loaded into register &#34;B&#34; and the byte in register &#34;HBYTE&#34; is loaded into register &#34;A&#34; while the byte now in register &#34;B&#34; is transferred to register &#34;HBYTE&#34;, as previously described. The process then jumps back to the appropriate &#34;SPOKE&#34;, which in this case is the &#34;EVEND&#34; spoke. 
     It is to be noted at this time that the final six bits of the last data character in the message are in register &#34;A&#34; while the first six bits of the next character are in register &#34;B&#34;. Accordingly, at this time, the process can pause until the next byte is received by in/out circuit 107. The first instruction for the &#34;EVEND&#34; spoke is thus the first instruction (1. JSR TIMER) to time a delay interval, which interval may be fruitfully employed to provide any housekeeping chores. After this timed interval, the process advances to instruction (2. LDX#LSP2) which advises CPU 108 to load the address of &#34;SPOKE 2&#34; into the index register. The process then advances to instruction (3. JMP NXBYTE) to jump the process to subroutine &#34;NXBYTE&#34;. As previously described, the subroutine &#34;NXBYTE&#34; obtains the next incoming byte from I/O circuit 107 for insertion into register &#34;B&#34;, loads the byte presently in register &#34;HBYTE&#34; into register &#34;A&#34; and stores the byte now in register &#34;B&#34; into register &#34;HBYTE&#34;. Under this condition, the first six bits of the next message character are now in register &#34;A&#34; and the final two bits of this next character are in register &#34;B&#34;. These storage conditions of registers &#34;A&#34; and &#34;B&#34; are the initial conditions appropriate for the &#34;SPOKE 2&#34; subroutine. The last instruction (6. JMP X) of subroutine &#34;NXBYTE&#34; now jumps the process back to the &#34;SPOKE&#34; process and, more specifically, to the &#34;SPOKE 2&#34; process, since this address is presently stored in the index register. Subsequent assembling is therefore identical to the priorly described processing of the data characters. 
     The instructions for the subroutines of the odd spokes together with the remarks thereof are shown in FIG. 7, Assume, for example, that the synchronizing routine exits at exit point 334. In this event the process, as described above, advances to the entry point of &#34;SPOKE 3&#34;. At the same time, the first five bits of the data character are in register &#34;A&#34; and the last three bits are in register &#34;B&#34;. The instructions for &#34;SPOKE 3&#34; are similar to the instructions for previously described even &#34;SPOKES&#34;. With respect to &#34;SPOKE 3&#34;, the bits in registers &#34;A&#34; and &#34;B&#34; are rotated through carry register &#34;C&#34; until all of the data characters are in register &#34;A&#34;. The address of the next successive &#34;SPOKE&#34;, namely, &#34;SPOKE 5&#34;, is entered into the index register and the process jumps to the &#34;CHKWRD&#34; subroutine described above. The data character is thus checked for an EOM or &#34;FILL&#34; character and the buffer is checked to see if it is full. If none of these conditions exist, the character assembled in register &#34;A&#34; is pushed into the stack and the process advances to the &#34;NXBYTE&#34; subroutine wherein the new incoming byte is inserted into register &#34;B&#34;, the byte in register &#34;HBYTE&#34; is transferred to register &#34;A&#34; and the byte newly stored in register &#34;B&#34; is stored in register &#34;HBYTE&#34;. At this point, the first three bits of the new data character are in register &#34;A&#34; and the next five bits are in register &#34;B&#34;. The &#34;NXBYTE&#34; subroutine is then terminated by the process jumping to the &#34;SPOKE 5&#34; subroutine. 
     The &#34;SPOKE 5&#34; subroutine may be entered from the &#34;NXBYTE&#34; subroutine, as described above, or from exit point 336 of the synchronizing routine. The instructions of the &#34;SPOKE 5&#34; subroutine enables CPU 108 to rotate the bits in registers &#34;A&#34; and &#34;B&#34; and through register &#34;C&#34; until all of the bits of the characters are in register &#34;B&#34;. The bits in register &#34;B&#34; are then transferred to register &#34;A&#34; by the (7. TBA) instruction and the address of the &#34;SPOKE 7&#34; routine is inserted into the index register whereupon the process jumps to the &#34;CHKWRD&#34; subroutine. The assembled character is thereupon then checked and the message buffer is examined and, if appropriate, the assembled character is then inserted into the buffer stack. The process proceeds to subroutine &#34;NXBYTE&#34; where the next incoming byte is inserted into register &#34;B&#34;, the last incoming byte in register&#34;HBYTE&#34; is passed to register &#34;A&#34; and the new byte in register &#34;B&#34; is stored in register &#34;HBYTE&#34;. At this time, the first bit of the new message data character is in register &#34;A&#34; and the second through seventh bits are in register &#34;B&#34;. It is to be noted that the final bit has not been received as this bit is in the byte which will be received next. 
     At this point, the process jumps to the &#34;SPOKE 7&#34; entry point which also can be entered from exit point 332 of the synchronizing routine. CPU 108 now proceeds to rotate the bits in registers &#34;A&#34; and &#34;B&#34; through carry register &#34;C&#34; until the first seven bits priorly stored are all in register &#34;B&#34;. In accordance with the first instructions for &#34;SPOKE 7&#34;, the bits in register &#34;B&#34; are then stored in register &#34;HBYTE&#34; and after an appropriate timing delay the address of the &#34;end-of-odd&#34; wheel spoke is inserted into the index register and the process jumps to the &#34;NXBYTE&#34; subroutine. In accordane with this subroutine, the new incoming byte is inserted into register &#34;B&#34; and the seven assembled bits of the data character in register &#34;HBYTE&#34; are stored in register &#34;A&#34;. The new incoming byte in register &#34;B&#34; is now inserted into register &#34;HBYTE&#34; and, in accordance with instruction 6. JMP X of the &#34;NXBYTE&#34; subroutine, the process jumps to the &#34;ODEND&#34; subroutine which is the end-of-odd wheel spoke subroutine. In this subroutine, the seven character bits in register &#34;A&#34; and the one final character bit in register &#34;B&#34; are rotated until all of the character bits are in register &#34;A&#34;. The address of the &#34;SPOKE 3&#34; subroutine is then inserted into the index register and the process jumps to the &#34;CHKWRD&#34; subroutine to assemble the character now fully stored in register &#34;A&#34;, storing this character if appropriate in the buffer stack. Thereafter, the process goes to subroutine &#34;NXBYTE&#34; to obtain the new incoming byte, transferring the byte in register &#34;HBYTE&#34; into register &#34;A&#34; and storing the new incoming byte in register &#34;B&#34; into register &#34;HBYTE&#34;. At this time, the first five bits of the new message character are in register &#34;A&#34; and the last three bits are in register &#34;B&#34;, which condition is appropriate for &#34;SPOKE 3&#34;. The last instruction of subroutine &#34;ODEND&#34; then jumps the process to the &#34;SPOKE 3&#34; entry point and the above-described assembly process for the various odd &#34;SPOKES&#34; is then repeated. 
     Although a specific embodiment of this invention has been shown and described, it will be understood that various modifications may be made without departing from the spirit of this invention.