Abstract:
A CCD signal processing channel with input and output offset correction is offered. Integrators are positioned to provide correction at the input to a correlated double sampling circuit and at the output of a programmable gain amplifier. Gain control is provided for the programmable gain amplifier. The second integrator may be all digital or may combine analog and digital signals. The channel may also be constructed using a digital programmable gain amplifier. The digital programmable gain amplifier can be combined with an analog programmable gain amplifier in the signal processing channel.

Description:
RELATED APPLICATION 
     This application claims the benefit, under 35 U.S.C. §119(e), of the filing date of provisional application Ser. No. 60/139,165, filed Jun. 15, 1999. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a variable gain amplifier. 
     BACKGROUND 
     Charge-coupled device (CCD) is the sensor of choice in modem imaging to convert photons into electrons, hence enabling the use of electronics for image processing. FIG. 1 shows typical analog front-end building blocks for a CCD signal processing channel. The CCD input signal  100  is received by a correlated double sampling circuit (CDS)  102  whose function is to extract the image content from the CCD signal  100  and remove the unwanted correlated noise component. A programmable gain amplifier (PGA)  104  amplifies the output of the CDS  102  before it gets converted to digital data by an analog-to-digital converter (ADC)  106 . The gain of the PGA  104  can be programmed by providing a gain input  110  to the gain control circuit  112 . 
     In reality, the circuit building blocks have offset, and such offset can reduce the dynamic range of the processing channel. In particular, any signal offset upstream of the PGA gets amplified by the PGA to a level related to the gain of the PGA, and hence seriously reduces the useful dynamic range of the PGA output and ADC. Such offset can come from the CCD signal, the CDS, or the input-referred offset of the PGA. For example, for an offset of 10 mV with a gain of 50× in the PGA, the output-referred offset at the output of the PGA becomes 0.5V. This reduces the dynamic range of the PGA output and ADC by 0.5V, which is not acceptable in most integrated circuit design applications. 
     In order to address this problem, an offset correction is typically used. One way to provide an offset correction is to integrate the output of the PGA during the calibration interval (e.g., black pixel period) and subtract the accumulated error from the input of the PGA in a feedback fashion. The feedback adjusts the input of the PGA such that the output of the PGA is equal to the system&#39;s “zero” reference during CCD&#39;s black pixels. This scheme is shown in FIG.  2 . In this figure, INT  200  refers to an integrator. 
     One problem with the scheme of FIG. 2 is that the time constant of the loop (PGA  104  and INT  200  loop) depends on the gain of the PGA  104 . To keep the feedback loop stable and the noise of the “zero” reference low, the bandwidth of the loop must be kept low and constant, keeping the loop gain constant with the varying PGA gain. This can be accomplished by inserting another PGA in the feedback path with a reciprocal gain characteristic of the PGA in the forward path. We call this a reverse PGA (RPGA)  300 , which is shown in FIG.  3 . 
     The gain characteristics of the PGA, the RPGA and the loop are shown in the diagrams of FIG.  4 . The PGA gain, the RPGA gain and the loop gain are each shown with respect to input gain. In terms of the dynamics of the loop, the order of RPGA  300  and INT  200  in the feedback path does not matter. The RPGA  300  can come before the INT  200  in the feedback path of the loop. There are, however, circuit level consequences that make the implementation of FIG. 3 a preferred embodiment. 
     SUMMARY 
     There are two limitations with the implementations of FIGS. 2-3. First, INT  200  must have a large enough output range to handle any offset before PGA  104 . Note that the offset correction removes the offset from the output of the PGA  104 ; this correction is accomplished by INT&#39;s  200  providing the same offset (with opposite polarity) in the feedback loop. This can be a problem in a low supply (e.g., &lt;3.0V) voltage environment. Second, PGA  104  must have a wide gain control range. Many CCD camera applications require a gain range of up to 40 dB (100×) with a maximum gain of 40 dB. This requires the PGA  104  to have an adequate bandwidth at the maximum gain, which increases the circuit&#39;s size and power consumption. The circuit of FIG. 3 is particularly vulnerable to size and power consumption increases due to its use of two PGA blocks. 
     To avoid the limitations of the prior art, a CCD signal processing channel with split offset correction is offered. Dual integrators are used to correct offset from the CCD input to the digital output. One integrator is placed at the correlated double sampling circuit to remove the CCD&#39;s offset as well as the CDS&#39;s offset. A second integrator is placed after the PGA to remove the PGA&#39;s offset as well as any uncorrected offset from the first offset correction. In an alternate embodiment, the second integrator can be placed after an analog digital converter (ADC) so that the integrator can operate entirely digitally. Alternatively, a digital PGA can be used in the channel. The signal from the CDS is converted by the ADC before it reaches the PGA and a digital PGA (DPGA) is used to produce a digital output. In an alternate embodiment, an analog PGA is used in combination with a DPGA. An ADC is placed at the output of the PGA which then provides the input for the digital DPGA. In this embodiment, gain control is offered for both the PGA and DPGA. 
     In the dual PGA, dual offset correction embodiment the first integrator is positioned at the correlated double sampling circuit and the second integrator is either positioned at the output of the PGA or at the output of the analog to digital converter. 
     In one embodiment, a pixel gain amplifier is used in combination with the CDS. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a CCD signal processing channel according to the prior art; 
     FIG. 2 shows a block diagram of a CCD signal processing channel with offset correction according to the prior art; 
     FIG. 3 shows a block diagram of a CCD signal processing channel with offset correction and constant loop gain according to the prior art; 
     FIG. 4 shows the PGA, RPGA, and loop gain characteristic of the circuit shown in FIG. 3 according to the prior art; 
     FIG. 5 shows a block diagram of a CCD signal processing channel with input and output offset corrections; 
     FIG. 6 shows a block diagram of one embodiment of a CCD signal processing channel with input and output offset correction; 
     FIG. 7 shows a block diagram of a CCD signal processing channel using a digital PGA; 
     FIG. 8 shows a block diagram of a CCD signal processing channel using analog PGA and digital PGA; 
     FIG. 9 shows the PGA and DPGA gain characteristics of the circuit shown in FIG. 8; 
     FIG. 10 shows a block diagram of a CCD signal processing channel using analog PGA and digital PGA with offset correction; 
     FIG. 11 shows a block diagram of one embodiment of a CCD signal processing channel using analog PGA and digital PGA with offset correction; 
     FIG. 12 shows a block diagram of a CCD signal processing channel using analog PGA, digital PGA and a pixel gain amplifier with offset correction; 
     FIG. 13 shows a block diagram of one embodiment of a CCD signal processing channel using analog PGA, digital PGA and a pixel gain amplifier with offset correction; and 
     FIG. 14 shows the output level of the pixel gain amplifier as shown in FIG.  13 . 
    
    
     DETAILED DESCRIPTION 
     FIG. 5 shows a scheme to address the INT&#39;s output range limitation. In this scheme, two offset correction loops are applied: one to the input  500  and the other to the output  502  of the PGA block  104 . The input offset correction removes the CCD&#39;s offset as well as the CDS&#39;s offset. The output offset-correction then removes the PGA&#39;s input offset plus the uncorrected offset from the first offset correction, referred to the PGA&#39;s output. Since most of the offset contributions are removed before the PGA, the offset that the output offset loop must correct for becomes significantly less compared to the prior art implementations of FIGS. 2 and 3. This is advantageous since it lends to circuit simplification. The input offset correction is accomplished by integrating the output of the CDS  102  during a calibration interval (e.g., black pixel period) and subtracting the accumulated error from the input of the CDS  102  in a feedback. The feedback adjusts the input of the CDS  102  such that the output of the CDS  102  is equal to the “zero” signal level during CCD&#39;s black pixels. The output offset-correction is accomplished by integrating the output of the ADC and subtracting the accumulated error from the output of the PGA  104  in a feedback. The feedback adjusts the output of the PGA  104  such that the output of the ADC  106  is equal to the system&#39;s “zero” reference during CCD&#39;s black pixels. 
     FIG. 6 shows another embodiment of the concept of FIG.  5 . In this implementation, the output offset correction is done digitally. The correction loop integrates the output of the ADC  106  and subtracts the error from the output of the ADC  106 . The difference between the implementations of FIG.  5  and FIG. 6 is that the input of INT  2   502  in FIG. 5 must be the digital output of the ADC  106 , but the output of INT  502  must be an analog level. In a real implementation of FIG. 5, there must be a digital to analog converter (DAC) with an appropriate level of resolution in the feedback with an INT  2   502 . Because INT  2   600  in FIG. 6 deals only with digital signals, no converters need to be added to its implementation. 
     FIG. 7 shows a scheme to address the limitation with the large gain range of PGAs. In this scheme, the PGA stage  700  is moved to after the ADC  106 . By doing so, the implementation of the PGA becomes digital (i.e., digital multiplier), hence resulting in circuit simplification. We also refer to this as digital-PGA or simply DPGA  700 . The drawback of the DPGA  700  is a loss in the signal&#39;s dynamic range with digital gain due to the truncation inherent in a digital multiplier. For example, an increase in digital gain by 2× (or 6 dB) is accompanied by a reduction in the dynamic range by 2× (or 6 dB). To offset this effect, the resolution of the ADC  106  needs to be increased by the gain range used in the DPGA  700 . For example, to obtain the same dynamic range as the analog PGA with 36 dB gain-range, the resolution of the ADC must be increased by 6 bits using a DPGA with the same gain range. Such an increase in resolution can be a more costly solution due to the difficulty of achieving 6 additional bits in the ADC. 
     FIG. 8 shows another embodiment using DPGA. In the scheme of FIG. 8, a DPGA  700  is used in conjunction with an analog PGA  104  to achieve the required gain range. The PGA  104  provides the lower gain range where the channel noise is limited by the ADC  106  (or noise after the gain of the PGA), and the DPGA  700  provides the higher gain range where the channel noise is limited by the input noise (or, noise before the gain of the PGA). 
     FIG. 9 shows the gain curves of PGA, DPGA, and overall gains. As shown, the gain range covered by the PGA is smaller compared to the all-analog implementation with the same total gain range (FIG.  1 ), hence lending to a simpler PGA design. By the same token, the DPGA covers a smaller gain range compared to the full digital implementation (FIG.  7 ). Here, the required resolution of the ADC can be less, and again simplifies the ADC design compared to that of FIG.  7 . This hybrid analog-digital PGA solution has the most potential for achieving the overall design simplification compared to FIG.  1  and FIG.  7 . 
     FIGS. 10-11 shows how input and output offset correction can be used with the embodiment of FIG.  8 . FIG. 10 shows the signal processing channel of FIG. 8 with two integrators,  500  and  502 . The first integrator  500  removes the CCD&#39;s offset as well as the CDS&#39;s offset. The second integrator  502  removes the PGA&#39;s input offset plus the uncorrected offset from the first offset correction, referred to the PGA&#39;s output. The channel of FIG. 11 moves the second integrator  600  past the ADC in the channel, thereby performing all corrections in the digital domain as described above for FIG.  6 . 
     FIGS. 12-13 show two embodiments using a pixel-gain-amplifier (P×GA)  1204 . P×GA  1204  provides gains switchable from sample to sample, and the concept is illustrated in FIG.  14 . The idea behind P×GA is to provide gains based on pixels in order to equalize the responsiveness of different samples corresponding to different colors produced by CCD sensors. FIGS. 12-13 show how the P×GA block  1200  can be implemented in the signal processing chain with input and output offset correction, and PGA  104  and DPGA  700 . The invention of the P×GA is disclosed separately in a concurrently filed application. This application, entitled “Pixel Gain Amplifier,” was filed on even date herewith and claims priority to provisional application Ser. No. 60/138,960, filed Jun. 11, 1999. Provisional application Ser. No. 60/138,960 is herein incorporated by reference in its entirety, and a copy of the corresponding non-provisional application is enclosed herewith. 
     This invention can be applied to processing of other types of signals, and is not limited to the processing of CCD signal. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements are intended to be within the spirit of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.