Abstract:
A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.

Description:
BACKGROUND 
     This application claims the priority of Korean Patent Application No. 10-2004-0072470, filed on Sep. 10, 2004, in the Korean Intellectual Property Office. The entire content of Korean Patent Application No. 10-2004-0072470, filed on Sep. 10, 2004 is hereby incorporated herein by reference. 
     1. Field 
     The present application relates to electronic circuitry and more particularly to level shifting circuitry. 
     2. Background Discussion 
     Level shifting circuitry is commonly used in semiconductor integrated circuits to transfer signals between two logic circuits having different operating voltages.  FIG. 1  is a circuit diagram of a simple level shifting circuit  120  that changes the signal level between logic circuit  110  and logic circuit  130 . Logic circuits  110  and  130  have different operating voltages. Referring to  FIG. 1 , the first logic circuit  110  operates at a voltage levels VCC and VSS 1 . Level VCC is a logic high level and level VSS 1  is a logic low level. The second logic circuit  130  operates at voltage levels VCC and VSS 2 . In circuit  130 , voltage level VCC is a logic high level and voltage level VSS 2  is a logic low level. The level shifting circuit  120  receives an output signal from the first logic circuit  110 , changes the level of the received signal, and transfers the changed signal to the second logic circuit  130 . The logic high voltage level of logic circuits  110  and  130  is VCC and the logic low levels of logic circuits  110  and  130  are VSS 1  and VSS 2 , respectively. 
     The level shifting circuit  120  operates as an inverter. Circuit  120  includes a P-type metal-oxide-semiconductor field effect transistor (MOSFET) P 1 , and an N-type MOSFET N 1 . The level shifting circuit  120  changes the level of the signal output from the first logic circuit  110  from VCC to VSS 2 , or from VSS 1  to VCC and sends the changed signals to the second logic circuit  130 . 
     When the level of a signal input to the level shifting circuit  120  is VSS 1 , the voltage VSS 1  is applied to a gate terminal of the N-type MOSFET N 1 , and the voltage between the gate and source of the N-type MOSFET N 1  is VSS 1 -VSS 2 . When VSS 1 -VSS 2  is less than a threshold voltage of the N-type MOSFET N 1 , the N-type MOSFET N 1  is not turned on. However, leakages occur due to a sub-threshold current in the N-type MOSFET N 1 , and hence power may be wasted. Such leakage current can be reduced to a few amps or less by implanting ions into a channel of the N-type MOSFET N 1  to raise the threshold voltage. However, in order to implant ions into a channel, an additional ion-implanting process step is necessary. Further, an additional mask is required for the ion-implanting process. Thus, the cost of production is increased. Also, it is difficult to optimize a design for controlling the threshold voltage of the N-type MOSFET N 1 . Finally, the reliability of such circuitry is not particularly high. 
     Leakage current can be reduced by using the level shifting circuit  220  shown in  FIG. 2 . Circuit  220  changes signal level between two logic circuits  210  and  220  that have different operating voltages. 
     The level shifting circuit  220  shown in  FIG. 2  changes the level of the signal output from the first logic circuit  210  from VCC to VSS 2  and from VSS 1  to VCC. The level shifting circuit  220  has a cross-coupled latch structure including P-type MOSFETs P 2  and P 3  and N-type MOSFETs N 2  and N 3 . 
     When the level of the signal applied to the gate of the P-type MOSFET P 2  is VSS 1 , the N-type MOSFET N 3  is turned on and the voltage level VSS 2  is applied to a gate terminal of the N-type MOSFET N 2 . In like manner, when the level of the signal at the input P-type MOSFET P 3  is VSS 1 , the voltage level VSS 2  is applied to a gate terminal of the N-type MOSFET N 3 . 
     In the level shifting circuit  220 , the voltage between the gate and source of each of the N-type MOSFETs N 2  and N 3  is constant at zero volts, and therefore the leakage current is reduced. However, since the voltage is applied to the gate of the N-type MOSFET N 2  or N 3  through the P-type MOSFET P 2  or P 3 , during the time period in which the voltage of the gate of the N-type MOSFET N 2  or N 3  goes from VCC to VSS 2 , a transient current may flow between the P-type MOSFETs P 2  and P 3  and in the N-type MOSFETs N 2  and N 3 . The larger the difference between VSS 1  and VSS 2 , the larger the transient current. 
     SUMMARY 
     The circuit described herein is a level shifting circuit capable of reducing leakage current without the use of an additional ion-implanting process during manufacturing. Also described herein is a level shifting method capable of reducing leakage current. 
     The level shifting circuits described herein include a plurality of metal-oxide-semiconductor field effect transistors (MOSFETs) connected in series between an output terminal and a voltage source. One of the MOSFETs is controlled by the input signal and one of the MOSFETs is controlled by a feedback signal. The feedback signal is generated in response to the output signal. 
     A method for shifting the level of voltages is also described. In the method of shifting voltages a plurality of MOSFETs connected in series between an output terminal and a source. One of the MOSFETs is controlled by an input signal and a second MOSFET is controlled by a feedback voltage. The feedback signal is generated in response to the output signal. 
     Several different embodiments of the invention are specifically described herein; however, those skilled in the art will understand that many other similar embodiments are possible. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a prior art level shifting circuit for changing a signal level between two logic circuits having different operating voltages; 
         FIG. 2  is a circuit diagram of another prior art level shifting circuit for changing a signal level between two logic circuits having different operating voltages; 
         FIG. 3  is a circuit diagram of a level shifting circuit for changing a signal level between two logic circuits having different operating voltages according to an exemplary first embodiment of the present invention; 
         FIG. 4  is a circuit diagram of the first logic circuit and the level shifting circuit of  FIG. 3  according to an embodiment of the present invention; 
         FIG. 5  is a circuit diagram of a general inverter shown in  FIG. 4 ; 
         FIG. 6  is a circuit diagram of the first logic circuit and the level shifting circuit of  FIG. 3  according to another embodiment of the present invention; 
         FIG. 7  is a circuit diagram of the first logic circuit and the level shifting circuit of  FIG. 3  according to another embodiment of the present invention; 
         FIG. 8  is a circuit diagram of the first logic circuit and the level shifting circuit of  FIG. 3  according to another embodiment of the present invention; 
         FIG. 9  is a circuit diagram of a level shifting circuit for changing a signal level of a first logic circuit from VCC 1 /VSS 1  to VCC 2 /VSS 2  according to an embodiment of the present invention; 
         FIG. 10  is a circuit diagram of the logic circuit of  FIG. 9 ; and 
         FIG. 11  is a circuit diagram of a level shifting circuit for selectively changing an input signal level to VCC/VSS 1  or VCC/VSS 2  according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The attached drawings illustrate various embodiments of the present invention. Hereinafter, these embodiments will be described in detail with reference to the attached drawings. Like reference numerals in the drawings denote like elements. 
     A first embodiment is shown in  FIG. 3 . In this embodiment, a level shifting circuit  320  is connected between two logic circuits  310  and  330 . The circuits  310  and  330  have different operating voltages. Level shifting circuit  320  changes the signal levels as signals are transmitted between the first logic circuit  310  and the second logic circuit  330 . 
     The first logic circuit  310  operates at a logic high level VCC and a logic low level VSS 1 . The second logic circuit  330  operates at a logic high level VCC and a logic low level VSS 2 . The level shifting circuit  320  changes the level of the output from the first logic circuit  310  from VCC to VSS 2  and from VSS 1  to VCC. The changed levels are transferred to the second logic circuit  330 . 
     It is noted that in this first embodiment (and in certain of the other embodiments shown herein) the logic low levels in circuit  310  and circuit  330  are different. The logic high level of both circuits is the same. However, in other embodiments the logic high levels of the two logic circuits  310  and  320  may be different, or both the logic high levels and the logic low levels may be different. Such embodiments are only slightly different from the level shifting circuits described herein and the differences will be easily understood by those skilled in the art. 
     Referring to  FIG. 3 , the level shifting circuit  320  includes a logic circuit  321  and a feedback circuit  322 . The logic circuit  321  includes MOSFETs N 5  and N 6  (which are collectively referred to as a circuit  326 ) and a logic unit  325 . The MOSFETs N 5  and N 6  are connected in series between a VSS 2  voltage source and the logic unit  325 . The feedback circuit  322  generates a feedback signal FED based on the output signal OUT. 
     The logic circuit  321  receives a first signal IN which has values of VCC and VSS 1 . Logic circuit  321  also receives a second input signal INB which is the inverse of the first signal IN. The first input signal IN is changed from VCC and VSS 1  to VSS 2  and VCC by using the feedback signal FED applied to one of the MOSFETs in the circuit  326 . When the logic circuit  321  receives the signals IN and INB, the logic circuit  321  generates the output signal OUT. The signal OUT is generated converting the signal IN to a signal with voltage levels VCC and VSS 2 . 
     As shown in  FIG. 3 , the signal at the input to the buffering inverter  311  in circuit  310  is used as the second signal INB. Alternatively, an inverter can be included in the logic unit  325  to invert the first signal IN and thereby produce the signal INB. 
     A second embodiment is shown in  FIGS. 4 and 5 . As shown in  FIG. 4 , a level shifting circuit  320 - 4  includes a logic circuit  410  and a NAND circuit  420 . The NAND circuit  420  forms a part of a feedback path. The INB signal forms one input to the NAND circuit  420  and the OUT signal is the second input. 
     The logic circuit  410  (which performs a function similar to circuit  321  in  FIG. 3 ) includes an inverter  411  and an N-type MOSFET transistor N 6 . The inverter  411  includes a P-type MOSFET transistor P 5  and an N-type MOSFET transistor N 5  as shown in  FIG. 5 . The N-type MOSFET N 6  is connected in series with the source terminal of the N-type MOSFET N 5 . The logic circuit  410  therefore includes in a series connection P-type MOSFET P 5 , N-type MOSFET N 5 , and N-type MOSFET N 6 . The three MOSFETs P 5 , N 5  and N 6 , are connected in series between a VCC source and a VSS 2  source. 
     As shown in  FIG. 5 , the gate terminals of the first P-type MOSFET P 5  and the N-type MOSFET N 5  receive the input signal IN, and the gate terminal of the N-type MOSFET N 6  receives the feedback signal FED. The output signal OUT is generated by the inverter  411  which includes the P-type MOSFET P 5  and the N-type MOSFET N 5 . The feedback path includes NAND circuit  420 . It is noted that a NAND circuit is a (Not AND) logic block. NAND logic circuit  420  receives the output signal OUT and the signal INB as inputs and it generates the feedback signal FED. The NAND circuit  420  operates at voltages of VCC and VSS 2 , and thus it outputs a signal at VCC and VSS 2  voltage levels. 
     When the level of the first signal IN changes from VCC to VSS 1 , the level of the output signal OUT goes to VCC because the P-type MOSFET P 5  is turned on, and the N-type MOSFET N 5  is turned off. The reason for this is that the voltage between the gate and the source of the N-type MOSFET N 5  is less than VSS 1 . Further, since the gate voltage of the third N-type MOSFET N 6  is VSS 2 , due to a NAND logic operation of the feedback circuit  420 , the third N-type MOSFET N 6  is turned off. Hence, because both the N-type MOSFETs N 5  and N 6  are turned off, there is little leakage current flowing between the VCC source and the VSS 2  source during the transition of the gate of the third N-type MOSFET N 6  from VCC to VSS 2 . The voltage levels and components in circuit  320  should be chosen so that the voltage VSS 1 -VSS 2  should be smaller than the threshold voltage of the N-type MOSFETs N 5  and N 6 . 
     A third embodiment is shown in  FIG. 6 .  FIG. 6  shows the first logic circuit  310  and a level shifting circuit  320 - 6 . An output signal OUT from circuit  320 - 6  goes to a second logic circuit (not shown in the Figure). Circuit  320 - 6  is a modification of the circuit  320  shown in  FIG. 4 . The level shifting circuit  320 - 6  includes NAND logic circuits  510  and  520 . The logic circuit  510  performs a NAND logic operation on the input first signal IN and the feedback signal FED to generate the output signal OUT. The OUT signal also serves as a feedback signal to the circuit  520 . The logic circuits  510  and  520  are NAND logic circuits, which operate at voltages VCC and VSS 2 , respectively. The logic and feedback circuits  510  and  520  output signals at VCC and VSS 2 . The level shifting circuit  320 - 6  includes a P-type MOSFET and N-type MOSFETs connected as shown in  FIG. 4  and leakage current is reduced as in the level shifting circuit shown in  FIG. 4 . 
     A fourth embodiment of the invention is shown in  FIG. 7 .  FIG. 7  shows the first logic circuit  310  and the level shifting circuit  320 - 7 . The level shifting circuit  320 - 7  generates an output signal OUT that goes to a second logical circuit (not shown in the drawing). Similar to the logic circuit  321  of  FIG. 4 , a logic circuit  610  of  FIG. 7  includes an N-type MOSFET N 6  connected in series with a source terminal of an N-type MOSFET that is in inverter  611 . The feedback circuit  620  shown in  FIG. 7  includes an N-type MOSFET N 7  connected in series to a source terminal of an N-type MOSFET that is in inverter  621 . 
     The inverter  611  receives the input signal IN. The gate terminal of the N-type MOSFET N 6  receives the feedback signal FED. The output signal OUT is generated by inverter  611 . The inverter  611  includes a P-type MOSFET and an N-type MOSFET (not specifically shown in the drawings). 
     The feedback circuit  620  receive the second input signal INB. The gate terminal of the N-type MOSFET N 7  is connected to the output signal OUT. The inverter  621  includes a P-type MOSFET and an N-type MOSFET (not specifically shown in the Drawing). The feedback signal FED is generated by inverter  621 . The sizes of the MOSFETs included in the feedback circuit  620  can be smaller than the sizes of the corresponding MOSFETs included in the logic circuit  610 . 
     The logic circuit  610  has a configuration similar to the logic circuit  321  shown in  FIG. 5  and it includes two N-type MOSFETs connected in series to a VSS 2  source. Therefore, the logic circuit  610  operates stably and a leakage current is not generated during transition of the gate of the N-type MOSFET N 6  from VCC to VSS 2 . 
     A fifth embodiment is shown in  FIG. 8 . As illustrated in  FIG. 8 , the embodiment includes a first logic circuit  310  and the level shifting circuit  320 - 8 . Two output signals OUT 1  and OUT 2  are generated by the circuit  320 - 8 . The level shifting circuit  320 - 8  of  FIG. 8  is a modification of the level shifting circuit  320 - 6  shown in  FIG. 6 . Level shifting circuit  320 - 8  receives signals A and B from the first logic circuit  310  in addition to an output from the NAND logic circuit  312 . Circuit  320 - 8  performs level-shifting to generate a first output signal OUT 1  and a second output signal OUT 2 . The signals A and B and the output of the NAND logic circuit  312  are at voltage levels VCC and VSS 1 . The logic circuit  710  and a feedback circuit  720  included in the level shifting circuit  320 - 8  are NAND logic circuits which operate at VCC and VSS 2 , and therefore the circuits  710  and  720  output signals at VCC and VSS 2 . 
     A sixth embodiment is illustrated in  FIGS. 9 and 10 .  FIG. 9  shows a level shifting circuit  820  for changing a signal level of a first logic circuit  810  from VCC 1 /VSS 1  to VCC 2 /VSS 2 . Referring to  FIG. 9 , the level shifting circuit  820  includes a logic circuit  821 , a first feedback circuit  822 , and a second feedback circuit  823 .  FIG. 10  is a detailed circuit diagram of the logic circuit  821  of  FIG. 9 . The logic circuit  821  includes an N-type MOSFET N 6  connected in series to a source terminal of an N-type MOSFET of a general inverter  841 , and a P-type MOSFET P 6  connected in series to a source terminal of a P-type MOSFET of the inverter  841 . Similar to the logic circuit  321  shown in  FIG. 5 , the configuration of the first feedback circuit  822  includes an N-type MOSFET N 7  connected in series to a source terminal of an N-type MOSFET of a general inverter  842 . Similarly, the second feedback circuit  823  includes a P-type MOSFET P 7  connected in series to a source terminal of a P-type MOSFET of a general inverter  843 . The logic circuit  821  operates at an operating voltage of VCC 2  and VSS 2 , the first feedback circuit  822  operates at an operating voltage of VCC 1  and VSS 2 , and the second feedback circuit  823  operates at an operating voltage of VCC 2  and VSS 1 . 
     Referring to  FIG. 10 , the logic circuit  821  includes, between a VCC source and a VSS 2  source, an N-type MOSFET N 5  with a source terminal connected in series to a drain terminal of an N-type MOSFET N 6  between an output signal OUT terminal and a VSS 2  source, and a P-type second MOSFET P 5  with a source terminal connected in series to a drain terminal of a P-type MOSFET P 6  between the output signal OUT terminal and a VCC 2  source. The gate terminals of the N-type MOSFET N 5  and the P-type MOSFET P 5  receive a first feedback signal FED 2 , and the gate terminal of the P-type MOSFET P 6  receives a second feedback signal FED 3 . The output signal OUT is output from a terminal to which drains of the P-type MOSFET P 5  and the N-type MOSFET N 5  are connected. The first feedback circuit  822  generates the first feedback signal FED 2  in response to the output signal OUT. The second feedback circuit  823  generates the second feedback signal FED  3  in response to the output signal OUT. A second signal INB from circuit  810  also contributes to the generation of the first feedback signal FED 2  and the second feedback signal FED 3 . 
     The logic circuit  821  receives an input signal IN with voltage levels VCC 1  and VSS 1 . The logic circuit  821  changes the input first signal IN into a signal with a voltage of VCC 2  and VSS 2  using the first feedback signal FED 2  supplied to the N-type MOSFET N 6  and the second feedback signal FED 3  supplied to the P-type MOSFET P 6  and outputs the changed signal as the output signal OUT. 
     A seventh alternative embodiment is illustrated in  FIG. 11 . The embodiment shown in  FIG. 11  includes a level shifting circuit  1020  for selectively changing an input signal level of a first logic circuit  1010  to VCC/VSS 1  or VCC/VSS 2 . Referring to  FIG. 11 , the level shifting circuit  1020  includes a logic circuit  1030 , a feedback circuit  1040 , and a control circuit  1080 . 
     The control circuit  1080  includes an inverter  1070 , a first circuit  1060 , and a second circuit  1050 . Each of the first circuit  1060  and the second circuit  1050  has a configuration similar to the logic circuit of  FIG. 5 , and performs an operation similar to the operation of the level shifting circuit  320  of  FIG. 7 . The inverter  1070  operates at VCC and VSS 1 . The control circuit  1080  receives a level select control signal CON at a level of VCC and VSS 1 , changes the received level select control signal to a signal at a level of VCC and VSS 2 , and outputs the changed signal as a select signal SEL. 
     Referring to  FIG. 11 , the logic circuit  1030  includes N-type MOSFETs N 11  and N 12  connected in series to a source terminal of an N-type MOSFET of a general inverter  1021 , and the operation of the N-type MOSFET N 12  is controlled by an N-type MOSFET N 13  controlled by the select signal SEL. That is, when the select signal SEL is at a logic high state, the logic circuit  1030  receives a first signal IN having a level of VCC and VSS 1 , changes the input first signal IN to a signal which has a voltage of VCC and VSS 1  using the select signal SEL, which is supplied to the N-type MOSFET N 1   1 , which is connected in series between a terminal of the output signal OUT and a VSS 1  source, and outputs the changed signal as a first output signal OUT 3 . When the select signal is at a logic low state, the logic circuit  1030  receives the input first signal IN, which has a voltage of VCC and VSS, changes the input first signal IN to a signal with a voltage of VCC and VSS 2  using a feedback signal FED supplied to the N-type MOSFET N 12  connected in series between the terminal of the output signal OUT and a VSS 2  source, and outputs the changed signal as a second output signal OUT 4 . 
     The configuration of the feedback circuit  1040  is identical to the configuration of the logic circuit  821  of  FIG. 10 . The feedback circuit  1040  generates the feedback signal FED using the second output signal OUT 4  when the select signal SEL is at a logic low state. When the select signal SEL is at a logic high state, the P-type MOSFET P 11  of the feedback circuit  1040  is turned off, and therefore the feedback circuit  1040  does not generate the feedback signal FED. 
     As describe above, according to the present invention, a level shifting circuit  320 ,  320 - 4 ,  320 - 6 ,  320 - 7 ,  320 - 8 ,  820  and  1020  includes a logic circuit including two MOSFETs connected in series between an output terminal and a source, and a feedback circuit controls one of the two MOSFETs. Further, as described above, leakage current is reduced in the level shifting circuit without an additional ion-implanting process by turning off the two MOSFETs connected in series between the output terminal and the source. 
     It is noted that in the description of some of the embodiments and in  FIGS. 4 ,  6 ,  7 ,  8 ,  9 , and  11 , a first logic circuits  310  is shown and described along with a level shifting circuit. In the above listed figures, a second logic circuit  330  which receives the output of the level shifting circuit is not explicitly shown. It should be understood that in each embodiment, the level shifting circuit can provide signals to a second circuit. 
     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.