Abstract:
A flash memory system comprises a logic block interface operable to receive a write command to store data from a host computer, a flash memory device operable to store the data in response to the write command, and a non-volatile memory communicatively coupled to the flash memory device and the logic block interface operable to temporarily store the data, and to provide the stored data to be written to the flash memory device in the event of a disruption during execution of the write command.

Description:
RELATED APPLICATION 
       [0001]    The present application claims the benefit of U.S. Provisional Patent Applications Nos. 61/719,986; 61/719,994; and 61/720,000, all filed on Oct. 30, 2012, which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The present disclosure relates to data storage devices, and in particular to using a Magnetic Random Access Memory (MRAM) journal for data backup for a flash memory device. 
       BACKGROUND 
       [0003]    Flash memory devices have been recognized as an attractive non-volatile data storage option for mobile computers and smartphone devices because of their small size, light-weight, shock resistance, fast access speed, and low power consumption. It is anticipated that with further advances in flash memory technology, its popularity may rival or even outpace hard disks. However, due to the different construction of flash memory as compared with a hard disk device, there are special considerations that have to be addressed in order to take advantage of the flash memory device. 
         [0004]    In a flash memory device, a write operation has to be preceded by an erase operation, which takes much longer than the write operation itself. Further, the smallest addressable unit for read and write operations is a page, but the smallest erasable unit is a block. This means that to even write a single byte of data into a flash memory requires the erase and restoration of a block of data. In the unexpected event of power loss after the data is erased but before the data is restored and written into the flash memory, data would be lost if no precaution has been taken to address this issue. 
         [0005]    In some conventional flash memory devices, capacitive devices have been used to keep supplying power to the flash memory so that the write operation may be completed. Such implementations not only have large component costs, but may be inadequate as the completion time for the write operation is unpredictable. The power in the capacitive device may still be insufficient to complete the write. 
       SUMMARY 
       [0006]    A flash memory system comprises a logic block interface operable to receive a write command to store data from a host computer, a flash memory device operable to store the data in response to the write command, and a non-volatile memory communicatively coupled to the flash memory device and the logic block interface operable to temporarily store the data, and to provide the stored data to be written to the flash memory device in the event of a disruption during execution of the write command. 
         [0007]    A method comprises receiving a write command to store data in a flash memory device from a host computer, storing the data in a non-volatile memory, in the event of a disrupted write operation to the flash memory device: reading the data from the non-volatile memory, verifying the validity of the data, and writing the valid data read from the non-volatile memory to the flash memory device. 
         [0008]    A computer readable medium having encoded thereon a method comprising receiving a write command to store data in a flash memory device from a host computer, storing the data in a MRAM journal. in the event of a disrupted write operation to the flash memory device: reading the data from the MRAM journal, verifying the validity of the data, and writing the valid data read from the MRAM journal to the flash memory device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a simplified block diagram of an exemplary embodiment of a flash memory device according to the present disclosure; and 
           [0010]      FIG. 2  is a simplified flowchart of an exemplary embodiment of a flash memory boot procedure according to the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    A flash memory has a very different construction than a hard disk device, which is generally organized in sectors. A flash memory device is organized into multiple planes, which are in turn organized into multiple blocks. The blocks are divided into multiple pages. In a flash memory device, a write operation is preceded by an erase operation, which takes much longer than the write operation itself. Further, the smallest addressable unit for read and write operations is a page, but the smallest erasable unit is a block. This means that to even write a single byte of data into a flash memory requires the erase and restoration of a block of data. In the unexpected event of power loss after the data is erased but before the data is restored and written into the flash memory, data would be lost if no precaution has been taken to address this issue. 
         [0012]      FIG. 1  is a simplified block diagram of an exemplary embodiment of a flash memory device  10  according to the present disclosure. The flash memory device  10  includes a logic block interface  12  that serves as an interface to a host computer or host device (not shown). The logic block interface  12  may include Flash Translation Layer (FTL) functionality to provide a translation between the logical block addresses used in the read and write commands issued by the host computer, and the physical block or page addresses in a flash memory device  16 . FTL typically stores address mapping data in one or more mapping tables. RAM (Random Access Memory) buffers  14  are communicatively coupled between the logic block interface  12  and the flash memory device  16 . The RAM buffers  14  are used to buffer or temporarily hold data to be written to the flash device  16  as well as the translated physical address of the location for the write operation. A MRAM (Magnetic Random Access Memory) journal  18  is further communicatively coupled with the logical block interface  12  and the RAM buffers  14 . The MRAM technology is a non-volatile memory device that does not rely on a power source to retain the stored data, and can maintain the data nearly permanently. MRAM technology also has better write/read performance characteristics than most other non-volatile memory technologies. 
         [0013]    In a write operation, data to be written into the flash device  16  are written into the RAM buffers  14  as well as the MRAM journal  18 . Additionally, the address location to which the data are to be written in the flash device  16  is also retained in the MRAM journal  18 . After data is written to the MRAM journal  18 , a write completion signal is generated and sent up the storage stack. The write from the RAM buffers  14  to the flash memory device itself may take any amount of time or not occur at all in the event of an unforeseen event, such as unplanned power loss. If the write operation is disrupted due to, for example, power loss or a write error, the data retained in the MRAM journal  18  are used to restore data to the flash memory device  16  and complete the write operation upon power up. 
         [0014]      FIG. 2  is a simplified flowchart of an exemplary embodiment of a flash memory boot procedure  20  according to the present disclosure. The boot procedure  20  is performed upon power up after unexpected power loss, for example. In block  21 , the “next” data (as specified by a “next” pointer, for example) in the MRAM journal  18  are read. In block  22 , the cyclic redundancy check (CRC) is verified to determine whether the data read from the MRAM journal are valid. It is contemplated that other methods of verifying the validity of the data may be used. If the CRC indicates that the data are not valid, then the process returns to block  21  to read the next data in the MRAM journal  18 . If the CRC indicates that the data read from the MRAM journal  18  are valid, then in block  23  the data are logged or stored into the Flash Translation Layer (FTL) of the logic block interface  12  that is operable to perform functions such as address translation, for example. The process then returns to block  21  to read the next data in the MRAM journal  18 . Once all the data associated with the current write operation are read from the MRAM journal  18 , the FTL mapping tables are accessed to perform address translation and used to write the data to the proper addresses in the flash memory device  16  in block  24 . In block  25 , the restore part of the boot process ends. 
         [0015]    In this manner, as long as the data have not been properly written to the flash memory device, i.e., due to a write error or power-loss, the data are retained in the MRAM journal and can be accessed upon power-up. Additionally, subsequent read operations to the same blocks of data can be read directly from the MRAM journal for as long as the data have not been placed into the flash memory device. One advantage of such an approach is that very high data rates may be achievable since the MRAMs are used only for data write during bulk I/O operations. 
         [0016]    The features of the present invention which are believed to be novel are set forth below with particularity in the appended claims. However, modifications, variations, and changes to the exemplary embodiments described above will be apparent to those skilled in the art, and the system and method described herein thus encompasses such modifications, variations, and changes and are not limited to the specific embodiments described herein.