Abstract:
A method of production of a multilayer circuit board comprised of a multilayer structure circuit formed by a plurality of interconnect layers and insulation layers stacked together and a semiconductor chip included therein, including the steps of placing a semiconductor chip having a polished back surface, with its active surface facing downward, on an already formed lower interconnect layer and forming an insulation layer over the layer on which the semiconductor chip has been placed, the method further including the step of treating the polished back surface of the semiconductor chip to improve its bondability with the insulation layer before the step for formation of the insulation layer.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method of production of a multilayer circuit board comprised of a multilayer structure circuit formed by a plurality of interconnect layers and insulation layers stacked together and a semiconductor chip included therein.  
           [0003]    2. Description of the Related Art  
           [0004]    Multilayer circuit boards with built-in semiconductor chips are being widely used as thin boards. The built-in semiconductor chips have to be made as thin as possible in order for them to fit in the limited board thickness. As means for this, the practice has been to polish the back surfaces so as to reduce the thickness of the semiconductor chips (for example, see US 2001/0008794A1, [00103] to [0110]). Such a semiconductor chip polished on its back surface, however, creates the following problem in the process of production of a multilayer circuit board.  
           [0005]    That is, when placing the semiconductor chip to be built in, with its active surface facing down, on a lower interconnect layer and then forming an insulating film over it, sometimes the smoothly polished back surface will have insufficient bondability with the insulating film laid over it. As a result, when performing reflow as part of the process of production of the multilayer circuit board or running an environment test as a test of the finished multilayer circuit board, the problem has arisen of the insulating film ending up being peeled off from the semiconductor chip due to the shrinkage stress of the resin.  
         SUMMARY OF THE INVENTION  
         [0006]    An object of the present invention is to provide a method of production of a multilayer circuit board incorporating a semiconductor chip which enhances the bondability between a semiconductor chip with a smoothly polished back surface and an insulating film forming an insulation layer.  
           [0007]    To attain the above object, according to the present invention, there is provided a method of production of a multilayer circuit board comprised of a multilayer structure circuit formed by a plurality of interconnect layers and insulation layers stacked together and a semiconductor chip included therein, including the steps of placing a semiconductor chip having a polished back surface, with its active surface facing downward, on an already formed lower interconnect layer and forming an insulation layer over the layer on which the semiconductor chip has been placed, the method further including the step of treating the polished back surface of the semiconductor chip to improve its bondability with the insulation layer before the step for formation of the insulation layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, wherein:  
         [0009]    [0009]FIGS. 1A to  1 H are cross-sectional views showing an example of the procedure for treatment for improving bondability by coating the back surface of a semiconductor chip by a coupling agent according to a first embodiment of the present invention;  
         [0010]    [0010]FIGS. 2A to  2 H are cross-sectional views showing an example of the procedure for treatment for improving bondability by forming a bonding layer on the back surface of a semiconductor chip according to a second embodiment of the present invention;  
         [0011]    [0011]FIGS. 3A to  3 H are cross-sectional views showing an example of the procedure for treatment for improving bondability by roughening the back surface of a semiconductor chip according to a third embodiment of the present invention;  
         [0012]    [0012]FIGS. 4A to  4 I are cross-sectional views showing an example of the procedure for treatment for improving bondability by forming a metal layer on the back surface of a semiconductor chip, then roughening the surface of that metal layer according to a fourth embodiment of the present invention; and  
         [0013]    [0013]FIGS. 5A to  5 N are cross-sectional views showing first to 14th steps in an example of a process of production of a built-in semiconductor chip multilayer circuit board and semiconductor module using treatment for improving bondability of the back surface of a semiconductor chip according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0014]    Preferred embodiments of the present invention will be described in detail below while referring to the attached figures.  
         [0015]    The treatment for improving the bondability can be performed by any of the following (1) to (4). Note that in the present invention, the semiconductor chip is generally a silicon chip.  
         [0016]    (1) Coating the back surface of the semiconductor chip by a coupling agent before or after the placement step: The coupling agent has the action of increasing the chemical bonding force between the semiconductor chip and the insulating film. Typically, a silane-based, titanate-based, aluminum-based, or other material can be used. It is possible to perform the treatment when polishing the back surface in the state with the formation of a large number of semiconductor chips in a wafer and then perform the dicing. As another example, it is possible to perform the treatment after placing a semiconductor chip on a lower interconnect layer. The method of treatment allows the timing of treatment to be selected and is inexpensive.  
         [0017]    (2) Formation of a bonding layer at the back surface of the semiconductor chip before the placement step: The bonding layer is comprised of a material having bondability with both of the semiconductor chip and the insulating film. Typically, it is formed by adhering or coating a diattach film (epoxy-based), dicing tape bonding material (acrylic-based), or polyimide resin (liquid or film state). These can be applied by materials and facilities which have been used in the past.  
         [0018]    (3) Roughening of the back surface of the semiconductor chip before the placement step: The roughening is performed by wet etching or dry etching. The wet etching can be performed by HF/HNO 3  etc., while the dry etching can be performed by SF 6 , CF 4 , Cl 2 , etc. Plasma etching and remote plasma are also possible. According to this treatment, the mechanical bonding force is enhanced by the anchor action of the roughened surface. Since the back surface is not given any other additional layer, the thickness of the semiconductor chip made thinner by the polishing is never increased.  
         [0019]    (4) Formation of a metal film on the back surface of the semiconductor chip, then roughening the surface of the metal film before the placement step: Sputtering, electroless plating, etc. is used to form a Cu, Ni, Au, Al, or other metal film and then plasma treatment, permanganic acid wet treatment, etc. is used to roughen the surface of the metal film. Roughening of the metal film is easier than roughening of a semiconductor. The mechanical bonding force is enhanced by the anchor action of the roughened surface. Further, as a secondary action, the heat dissipating ability of the semiconductor chip is enhanced by the heat conduction of the metal film.  
         [0020]    The treatment for improvement of the bondability can all be executed by the facilities and materials used in the past, so a lot of time and cost are not required for development.  
         [0021]    First Embodiment  
         [0022]    Referring to FIGS. 1A to  1 H, an explanation will be made of an example of coating a coupling agent on the back surface of a semiconductor chip according to a first embodiment of the present invention.  
         [0023]    A silicon wafer  100  shown in FIG. 1A is formed with a large number of semiconductor chips at its semiconductor chip forming surface  102 . The wafer  100  is for example a thickness of 725 μm or so.  
         [0024]    As shown in FIG. 1B, a surface protective tape  106  is adhered to the semiconductor chip formation surface  102 . This is performed using a laminator at ordinary temperature by rolling.  
         [0025]    As shown in FIG. 1C, the back surface  104 ′ of the silicon wafer  100  is polished to obtain the polished back surface  104 . This polishing is performed using a back grinder at 4000 rpm at 1 μm/sec. The thickness of the wafer  100  is reduced to about 20 to 100 μm or so.  
         [0026]    As shown in FIG. 1D, the characterizing feature of the first embodiment of the present invention is the formation of the layer  108  of the coupling agent on the polished back surface  104 . As an example, this is performed by dipping in a dispersion comprised of a silane-based coupling agent dispersed in an IPA aqueous solution.  
         [0027]    As shown in FIG. 1E, a dicing tape  110  is adhered on the layer  108  of the coupling agent. This is performed by a laminator at ordinary temperature by rolling.  
         [0028]    As shown in FIG. 1F, the surface protective tape  106  is removed. This is performed by peeling using a tape remover.  
         [0029]    As shown in FIG. 1G, the wafer is diced to cut it into individual semiconductor chips. This cutting is performed using a dicer at a dicing blade speed of 40,000 rpm and cutting speed of 50 mm/sec.  
         [0030]    As shown in FIG. 1H, each diced semiconductor chip  112  has an active surface  102  and a back surface  104 . The back surface  104  is formed with a layer  108  of the coupling agent.  
         [0031]    Note that in this example, a silane-based coupling agent was used, but there is no need to limit the invention to this. Any material having an action increasing the chemical bonding force between a semiconductor chip and insulating film may be used. In addition to a silane-based one, a titanate-based, aluminum-based, or other material may be used.  
         [0032]    Regarding the timing of treatment by the coupling agent, as in the present embodiment, it is possible to polish the back surface in the state with a large number of semiconductor chips formed at the wafer, treat it by a coupling agent in that state, then dice the wafer. As another treatment timing, it is possible to place a semiconductor chip on a lower interconnect layer, then treat it by a coupling agent.  
         [0033]    The method of treatment by a coupling agent has the advantages that it enables the timing of treatment to be selected and is low in cost.  
         [0034]    Second Embodiment  
         [0035]    Next, an explanation will be made of an example of bonding a bonding film on the back surface of a semiconductor chip according to a second embodiment of the present invention.  
         [0036]    In the same way as the steps of FIG. 1A to FIG. 1C of the first embodiment, the steps of FIG. 2A to FIG. 2C are performed to polish the back surface  104 ′ of the silicon wafer  100  to the polished back surface  104 .  
         [0037]    Next, as shown in FIG. 2D, the second embodiment of the present invention is characterized by bonding a bonding film  114  on the polished back surface  104 . This is performed for example by using a laminator to bond a die attach film (thickness 25 μm) comprised of an epoxy-based curing resin under conditions of a heating temperature of 140° C., a heating time of 10 sec, and a pressing force of 1 MPa.  
         [0038]    After this, in the same way as the steps of FIG. 1E to FIG. 1H of the first embodiment, the steps of FIG. 2E to FIG. 2H are performed. Each diced semiconductor chip  116  has an active surface  102  and a back surface  104 . A bonding film  114  is bonded to the back surface  104 .  
         [0039]    Note that in the present embodiment, an epoxy-based bonding film  114  was used, but the invention does not have to be limited to it. Any material having bondability with respect to both a semiconductor chip and insulating film is possible. Typically, in addition to the die attach film used in the present embodiment (epoxy-based), it is formed by bonding or coating a dicing tape bonding material (acrylic-based) and polyimide resin (liquid or film state). Both can be executed by materials and facilities used since the past.  
         [0040]    Third Embodiment  
         [0041]    Next, an explanation will be made of an example of roughening a polished back surface of a silicon chip according to a third embodiment of the present invention.  
         [0042]    In the same way as the steps of FIG. 1A to FIG. 1C of the first embodiment, the steps of FIG. 3A to FIG. 3C are performed to polish the back surface  104 ′ of the silicon wafer  100  to the polished back surface  104 .  
         [0043]    Next, as shown in FIG. 3D, the third embodiment of the present invention is characterized by roughening the polished back surface  104  to obtain the roughened back surface  104 R. This is performed for example by using a plasma etcher for isotropic dry etching by an SF 6 /Ar mixed gas under conditions of a gas pressure of 100 Pa to give a roughness of 0.1 μm.  
         [0044]    After this, in the same way as the steps of FIG. 1E to FIG. 1H of the first embodiment, the steps of FIG. 3E to FIG. 3H are performed. Each diced semiconductor chip  118  has an active surface  102  and a back surface  104 R. The back surface  104 R is roughened.  
         [0045]    Note that in the present embodiment, the means for roughening the back surface of the silicon chip was isotropic dry etching, but the invention does not have to be limited to it. The roughening may also be performed by wet etching or dry etching. The wet etching can be performed by HF/HNO 3  etc., while the dry etching can be performed by SF 6 , CF 4 , Cl 2 , etc. Plasma etching and remote plasma are also possible.  
         [0046]    The roughening treatment enhances the mechanical bonding force due to the anchor action of the roughened surface. Since the back surface is not given any other additional layer, the thickness of the semiconductor chip made thinner by the polishing is never increased.  
         [0047]    Fourth Embodiment  
         [0048]    Next, an explanation will be made of an example of forming a metal film on a polished back surface of a silicon chip and roughening the surface of the metal film according to a fourth embodiment of the present invention.  
         [0049]    In the same way as the steps of FIG. 1A to FIG. 1C of the first embodiment, the steps of FIG. 4A to FIG. 4C are performed to polish the back surface  104 ′ of the silicon wafer  100  to the polished back surface  104 .  
         [0050]    Next, as shown in FIG. 4D, the fourth embodiment of the present invention is characterized by forming a metal film  120  comprised of Cu on the polished back surface  104  using a sputtering apparatus under conditions of a vacuum of 10 −4  Pa, a sputtering output of 500 W, and a substrate temperature of 70° C.  
         [0051]    Next, as shown in FIG. 4E, the surface of the Cu metal film  120  is roughened to obtain the roughened surface  120 R. This is performed for example by dipping in 80° C. potassium permanganate.  
         [0052]    After this, in the same way as the steps of FIG. 1E to FIG. 1H of the first embodiment, the steps of FIG. 4F to FIG. 4I are performed. Each diced semiconductor chip  122  has an active surface  102  and a back surface  104 . The surface of the Cu metal film  120  formed on the back surface  104  is roughened to form the surface  120 R.  
         [0053]    Note that in the present embodiment, the metal film was formed by sputtering, but the invention does not have to be limited to it. Electroless plating or another metal thin film forming method may also be used. Further, in this embodiment, a metal film of Cu was used, but it is also possible to use a metal film of Ni, Au, Al, or other metal film in addition to Cu. The roughening of the metal film does not have to be limited to permanganic acid wet treatment. For example, plasma treatment etc. may also be used.  
         [0054]    The advantage of this embodiment is that roughening of a metal film is easier than roughening of silicon. Further, as a secondary action in addition to the action of enhancing the mechanical bonding force by the anchor action of the roughened surface, the heat dissipating ability of the semiconductor chip is enhanced by the heat conduction of the metal film.  
         [0055]    Fifth Embodiment  
         [0056]    Next, an explanation will be given of an example of production of a built-in semiconductor chip multilayer circuit board using a semiconductor chip (silicon chip) treated to improve the bondability of the back surface by any of the first to fourth embodiments.  
         [0057]    (Step 1) (FIG. 5A)  
         [0058]    A two-sided copper clad substrate  12  comprised of a core material  10  made of an insulating resin clad on its two surfaces with copper foil is used and formed with core layer interconnect patterns  14  obtained by patterning the two copper foils, through holes  16  passing through the core material  10 , insulation layers  18 , interconnect patterns  20  on the insulation layers  18 , and vias  22  passing through the insulation layers  18  and connecting the interconnect patterns  14  and interconnect patterns  20 .  
         [0059]    (Step 2) (FIG. 5B)  
         [0060]    A resist layer  24  is formed on the interconnect patterns  20  and its opening  26  used to determine the chip embedding position. The opening  26  is larger than the size of the embedded chip by about 1 mm to several mm. The thickness of the resist layer  24  is made one equal to that of the thickness of the embedded chip (including the bump heights and thickness of the layer for improving bondability) (for example, about 30 to 70 μm). The resist layer  24  is formed by laminating a resist resin sheet or coating a resist resin, then performing usual lithography for patterning this by exposure and development.  
         [0061]    (Step 3) (FIG. 5C)  
         [0062]    The Cu interconnect pattern  20  exposed in the opening  26  of the resist layer  24  is electrolessly plated by Au  28  to a thickness of 0.1 to 1 μm or so. Therefore, a resist resin able to withstand the electroless Au plating for formation of the resist layer  24  is selected. Electroless Au plating can handle narrow pitches of less than 150 μm.  
         [0063]    (Step 4) (FIG. 5D)  
         [0064]    A silicon chip  30  serving as the semiconductor chip to be embedded is polished on its back surface and treated on its back surface to improve bondability by one of the methods of the first to fourth embodiments. That is, the bondability improvement layer  32  formed by this is any of the coupling agent layer  108  illustrated in the first embodiment, the bonding layer  114  illustrated in the second embodiment, the roughened surface  104 R illustrated in the third embodiment, and the roughened metal film  120  illustrated in the fourth embodiment.  
         [0065]    The active surface (lower surface in the figure) of the chip  30  is formed with Au electrode bumps  34 . The thickness of the chip  30  including the height of the bumps  34  and the thickness of the bondability improvement layer  32  is about 30 to 70 μm. As explained above, this matches with the thickness of the resist layer  24 . The clearance “t” between the outer circumference of the chip  30  and the side walls of the opening  26  of the resist layer  24  is about 0.5 mm to 2 mm.  
         [0066]    (Step 5) (FIG. 5E)  
         [0067]    Underfill  36  is injected from the clearance “t” between the chip  30  and the opening  26  to completely fill the clearance between the chip  30  and the upper surface of the substrate and side walls of the opening  26 . The upper surface of the underfill  36  is substantially in the same plane as the upper surface of the bondability improvement layer  32  and the upper surface of the resist layer  24  at the back surface of the chip  30 .  
         [0068]    (Step 6) (FIG. 5F)  
         [0069]    An insulation layer  38  is formed to cover all of the upper surface of the bondability improvement layer  32  of the chip  30 , the upper surface of the underfill  36 , and the upper surface of the resist layer  24 . This is done by laminating an insulating film or spin coating a liquid insulating resin. The thickness of the insulation layer  38  is about 20 to 30 μm.  
         [0070]    (Step 7) (FIG. 5G)  
         [0071]    Via holes  40 ′, are formed passing through the insulation layer  38  and the resist layer  24  underneath it and reach the interconnect pattern  20 . This is performed by lasering by a YAG laser, CO 2  laser, etc. or by reactive ion etching (RIE).  
         [0072]    (Step 8) (FIG. 5H)  
         [0073]    A Cu electroless plating layer  42  is formed so as to cover the entire upper surface of the insulation layer  38  and the entire inside surfaces of the via holes  40 ′ and is made the electroplating power feed layer.  
         [0074]    (Step 9) (FIG. 5I)  
         [0075]    The Cu electroless plating layer  42  is formed with a resist layer  44  by ordinary lithography.  
         [0076]    (Step 10) (FIG. 5J)  
         [0077]    The Cu electroless plating layer  42  is used as a power feed layer for Cu electroplating to form the connection pads  46  and vias  40  all together.  
         [0078]    (Step 11) (FIG. 5K)  
         [0079]    The resist layer  44  is peeled off, then the parts of the Cu electroless plating layer  42  exposed from below are removed by etching to electrically separate the individual connection pads  46 .  
         [0080]    (Step 12) (FIG. 5L)  
         [0081]    A solder resist layer  48  is formed to define the actual areas of the connection pads  46 . This is formed by laminating a solder resist sheet on the entire upper surface, then exposing, development, and curing the same. Due to this, only the effective areas of the connection pads  46  are exposed from the openings  50  of the solder resist layer  48 .  
         [0082]    (Step 13) (FIG. 5M)  
         [0083]    The surface of the effective region of the connection pads  46  exposed at the insides of the openings  50  of the solder resist layer  48  is covered by an Ni/Au electroless plating layer  52 . Due to this, a built-in semiconductor chip type multilayer circuit board  60  is completed.  
         [0084]    (Step 14) (FIG. 5N)  
         [0085]    A separate silicon chip  54  is placed on the upper surface. This is done by bonding the electrode bumps  56  provided at the active surface (lower surface in the figure) of the chip  54  to the Ni/Au plating connection pads  46 . After placement, underfill  58  is filled between the chip  54  and the substrate upper surface below the same. Due to this, a semiconductor module  70  comprised of a built-in semiconductor chip type multilayer circuit board  60  carrying a semiconductor chip  54  is obtained.  
         [0086]    Summarizing the effects of the invention, according to the present invention, there is provided a method of production of a multilayer circuit board incorporating a semiconductor chip which enhances the bondability between a semiconductor chip with a smoothly polished back surface and an insulating film forming an insulation layer.  
         [0087]    While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.