Abstract:
An improved switch input arrangement for a system that remotely controls distributed electrical loads. The switch input arrangement is part of a transceiver decoder that receives commands from central controller for controlling the state of latching relays for controlling the power circuits of the loads. The improvements include: monitoring the state of contact closure inputs to the transceiver decoder, selectively enabling/disabling specific contact closures to control the masking of switch inputs, inclusion of an accumulated switch buffer to store the last actuation state of all relays, an answerback to insure that action occurs responsive to a switch input, a shifting threshold and multiplexing technique for more accurate reading of contact closure switch inputs, and the inclusion of a power-up reset message annunciated to the central controller to alert it that certain commands may have to be issued in order to reestablish the desired states of the transceiver.

Description:
BACKGROUND OF THE INVENTION 
     There has been developed a system for remotely controlling electrical loads distributed over a wide area (such as a large office building or factory) from a microprocessor based central controller. That system is disclosed in U.S. Pat. No. 4,367,414--Miller et al, issued Jan. 4, 1983. The information disclosed in that patent is incorporated by reference thereto as if fully set forth herein. In the Miller &#39;414 system, control instructions are issued by the central controller 50 and are tarnsmitted to various transceiver-decoders 56 via a twisted pair cable 58 constituting a bidirectional communications channel. A particular transceiver-decoder that is &#34;addressed&#34; carriers out the command by actuating one or more particular relays to make or break an electrical connection as desired. The central controller issues its control instructions in accordance with a predetermined schedule, in response to a measured parameter (such as light level or temperature) or in response to a user switch actuation sensed by a switch processor in the transceiver decoder and transmitted to the central controller over the bi-directional communications link, or in response to a user command telephonically transmitted to the central controller. 
     Although the Miller &#39;414 system operates effectively as disclosed, further enhancements are now possible. This patent is directed to improvements in the transceiver-decoder, particularly to a switch input arrangement for processing various binary closure inputs to the transceiver decoder to be transmitted to the central controller to give it information or request a relay state change. 
     The enhanced transceiver-decoder is configured in a modular fashion. Separate switch and relay &#34;modules&#34; are provided to allow a user of the product to configure a remote control panel to meet his specific application needs. This modular construction is field adaptable allowing an electrician who has no electronic expertise to easily install, replace and service the panels. To do this, small modules are developed so that they can be easily handled and configured in the field. 
     It is now possible to further enhance means for sensing the ON/OFF condition of binary contacts to make appropriate control decisions. In the system depicted in FIG. 1 of Miller &#39;414, central controller 50 could interrogate binary inputs located on a remotely located transceiver and determine the proper control output needed in response to the condition of those binary sensors. This is particularly useful where a thermostat is employed as a binary input to the central controller which would turn ON and Off or cycle heating ventilation air conditioning systems according to the ON/OFF condition of the thermostat switch which would be preset to a predetermined temperature threshold. Additionally, a photo relay or switch can be connected to these binary inputs to determine which lights are to go ON and OFF within a perimeter office in response to the amount of sunlight entering the area. 
     It is desirable to be able to selectively disable the response to certain or specified individual switch inputs thereby allowing certain switch inputs to be masked out. As previously disclosed in Miller &#39;414, the actuation (either opening or closing) of a contact causes immediate transmission back to the controller so that appropriate control information can be transmitted forcing the proper load state. It may be desired at certain times of day, however, to disable selected switches so that no action occurs ignoring its ON/OFF condition. A typical application would include night setback thermostats where two thermostats would be connected to two binary inputs such that one thermostat would be enabled and so set for normal working periods while the second thermostat would be set and enabled during off hours providing the night setback function. This selective enabling and disabling of contact closure or binary sensors are achieved by commands from the central facility means. 
     It is also desirable to provide a positive acknowledgement from the central facility means to the remote input transceiver verifying the action of the change of state of binary contact closures. In the prior art, a transmission would be immediately initiated by the transceiver to the central controller means upon the enabling of a binary input. Only one transmission was made such that if the central controlled means missed the message no action would take place. Since this is undesirable for use with critical inputs such as alarms, demand, security and other binary input functions, an answer back function was added. This answer back scheme would result in the input transceiver to periodically transmit to the central controller the action of the binary sensor until the reception of a positive acknowledge that the message was received from the central controller means. 
     It is also desirable to provide improved self diagnostics such that the central controller can detect the erroneous resetting or subsequent application of power to remotely located transceivers. This power-up and reset annunciation will insure the integrity of the distributed data base while providing a diagnostic means to trace failed devices. 
     SUMMARY OF THE INVENTION 
     This invention relates to improvements in transceiver-decoders 56 shown in FIG. 1 of Miller &#39;414. Now, each transceiver-decoder has separate processors for carrying out switch functions (sensing a condition change or a user initiated contact closure and sending a message to central controller 50) and receiving a command from central controller 50 and controlling in response to that command, one or more relays in the power circuits of electrical loads to be controlled. 
     The transceivers according to this invention have some physical and functional differences from those of the Miller &#39;414 patent. These differences are upward compatible with the Miller &#39;414 design and therefore, interchangeable in the field. The notable physical and functional improvements are: 
     New reset button function which would cycle loads both on and off. 
     Built-in installation test scenario. 
     New built-in functions for future product offerings. 
     Smaller enclosure and plus-in modular design. 
     No switch inputs--allow add ON switch input modules. 
     Switch-Only-Transceivers 
     A switch-only-transceiver can be configured as an add-on plug in module. It can be a &#34;piggyback&#34; module for any new transceiver. 
     Pulse-Output Transceiver 
     This transceiver provides a means to pulse high current contactors or motor starters. This product has solid-state outputs capable of driving a maximum of 1 amp at 120 VAC for 100 msec&#39;s. In the alternative, this function can be carried out as a relay output function. The product is configured in 8 outputs and should fit into the same case as the stand alone switch-only-transceiver. 
     All of the above products are configures to operate at 115 V, 230 V, and 277 V AC (50/60 Hz) desirable to have these multiplicity of input voltages be compatible with every product so there is no distinction due to input voltage. 
     Power Supply 
     A universal power input circuit is provided for all products rated for an input voltage range of 100 VAC to 320 VAC (RMS) at 47 to 100 Hz. 
     The power dissipation of the transceiver is kept as low as possible to eliminate the need of costly cooling techniques. The maximum steadystate power (not pulsing relays) does not exceed 700 mW per transceiver. 
     Watchdog Reset 
     A watchdog reset circuit is provided to reset the microcomputer chip in the unlikely event noise causes it to adversely execute erroneous instructions and latchings in a closed loop. The watchdog reset physically resets the computer causing it to execute a power-up sequence described below. 
     Switch Input Processing 
     A switch input interface for both a standard 3 wire momentary and 2 wire maintain with a user selectable jumper is to be provided in the same fashion as the Miller &#39;414 transceiver. The switch connects to the transceiver over number 20 AWG wires of up to 250 feet in length. The switch interface circuitry on the transceiver must provide a high enough voltage, typically greater than 20 VDC, so as to breakdown typical oxides that form on the switch contacts. 
     
         ______________________________________Switch Interface SpecificationsDescription   Notes*  Min.    Max. Typ.  Units______________________________________ElectricalSwitch Closed 1               700        OhmsContact ResistanceOpen Contact Voltage         2,5     20       40  30    VDCCurrent Supply         3,5     1.8      5    2    maAt 18 VDCSwitch Input  4,5,6   8        12  10    VoltsThresholdFunctional TimingResponse To Valid         7       40      110  50    msecSwitch Closure(Debounce Period)Switch Input  8                    10    KHzNoise Filtering(Cut Off Frequency)Special Function DeviceLoading With 18 vdc   3        10k       OhmsMinimum______________________________________ *See the following notes for a description of the specification. 
    
     Switch Specification Notes 
     1. The switch contact resistance is the maximum impedance that a switch device can have and properly be interpreted as a switch closure. This specification is particularly important for electronic switching means connected to the transceiver. 
     2. The open contact voltage is a specification to ensure that a minimum voltage is provided or impressed by the transceiver on the switching device to break down oxides that typically form on switch contacts. Furthermore, it is also necessary to ensure a wide noise margin with a large voltage swing. The maximum spec. of 40 VDC is limited by NEC Class 2 circuit requirements. 
     3. The current supply specification is for special function devices that derive its power from the switch inputs of the transceiver. For example, the BPHOTO-4 photoswitch is a low current device that can derive its operating power from the signal inputs. Therefore, to ensure proper noise immunity, an 18 VDC minimum must be maintained at 1.8 ma current to supply power to the special function device so as not to be mistakenly read as a switch closure. Therefore, the maximum DC operating impedance or load on a switch input cannot be less than 10K Ohms. If the special function peripheral device is less than 10K Ohms, an external power supply is needed for it to derive its power. This spec. also indicates the current limiting required on the switch input circuitry at 0 volts or in the closed contact condition. 
     4. The switch input threshold is the minimum voltage below which a switch is considered closed or in the &#34;make&#34; condition. Similarly if a switch input is above its maximum voltage it is considered open or in the &#34;break&#34; condition. More significant is the DC impedance on the contact device itself needed to cause this maximum voltage on the switch input terminals. 
     5. All voltages are referenced to the circuit common. 
     6. Power to the switches is solely supplied by the transceiver. At no time can a switching device impress a voltage on or power to a switch input of a transceiver. All current notations indicate the positive flow from the transceiver switch terminals to the switching device. 
     7. Switch debouncing of more than 40 msec&#39;s should be provided to guard against multiple switch closures. The debounce period simply means that a switch reading must take place between 40 and 110 msec&#39;s. It is not required to have the switch be enabled for two or more switch periods before a reading is taken. 
     8. During a switch reading sequence appropriate noise rejection and filtering is needed to guard against spurious signals coupled into the switch wire affecting it&#39;s reading. To insure the reading of a DC level and not the affects of noise, appropriate low pass filtering is needed (both digital and analog). After the debounce timeout a switch reading is taken. During the switch reading protocol noise filtering can be achieved by sampling the switch closure continuously for 100 microseconds. If the switch changes state or is not stable during the switch reading interval then it is to be rejected and read again after the next debounce period. 
     Special Switch Only Transceiver Function 
     In order to improve the systems switch input processing capabilities, a special extension feature is to be provided in the switch only transceiver products. A user selectable switch input enable mask is provided. When a switch is disabled no state change is recorded or can cause a transmission. However, when the switch input is subsequently enabled the state of the switch is to be transmitted to the controller it is in any of its known steady states. Therefore, the enabling of a switch is equivalent to a switch state change which causes the appropriate transmission as if it were actually mechanically actuated. 
     Specifically: 
     If in the maintained switch mode, a transmission will be made indicating the ON/OFF state of the switch after the switch input is enabled by the controller. 
     If in the momentary switch mode the switch is enabled, a transmission is to take place if and only if the switch input is in any one of its &#34;make&#34; contact states, i.e. on or off. 
     The enabling and disabling of switch inputs adds a powerful dimension to our energy management control system. They can be used in our scheduling, telephone and switch input control scenarios. For example, scheduling of night set back thermostats and improved demand control scenarios are possible. 
     Special Switch Transmission Feature 
     Two forms of switch transmissions are to be provided selected by a factory installed jumper. They are the regular and secure mode of switch transmissions. 
     The regular switch transmission mode is similar to the Miller &#39;414 configuration such that a switch activation causes an open loop transmission. If the controller is in the manual or &#34;down&#34; mode this transmission will be missed and therefore not acted upon. For wall switches this is apparently not a significant problem and is probably the desired scenario. The user may simply try activating the switch again. However, when connected to demand control equipment or special purpose devices, it is desirable to have the system catch up to these command inputs once returning to the automatic mode. 
     Therefore, a secure mode of switch transmission is defined whereby a transceiver would transmit a switch action at 1 second intervals until receiving a switch acknowledgement from the central controller. This will provide a secure and fully closed loop system. 
     Only a reset command, switch acknowledgement, or a power-up can abort this answer back switch protocol. This feature will again provide the most secure system while maintaining system throughout. 
     Power-Up Sequence 
     When power is first applied, the transceiver is to enter a &#34;power-up&#34; sequence. The power-up sequence consists of an internal reset protocol plus special functions. 
     The reset protocol has the folllwing functions. 
     Delay 100 msec&#39;s to allow power supplies and external circuits to precharge. This must be the first function performed after initializing I/O lines. 
     Disable any relay processing action or pending action (do not change the state of relays). 
     Disable switchleg activation. 
     Clear any switchleg mask words. Enable all switchleg input circuits. 
     Clear any transmission requests. 
     Reset the receiver section to wait for a line free. 
     Do not alter the internal memory containing the states of the relays. Many times a power-up due to a watchdog reset will not affect the validity of the relay state work stored in its internal memory. 
     Initialize the switch input section so as not to cause the transmission of the present switch states. It should be noted the action on switches are taken only when there is a change of state or condition. The switch enable mode and switch read command are the only exceptions. 
     In addition to the above reset protocol the following two special functions are included during a power-up sequence. 
     Set an Internal Reset Bit which is used the central controller to indicate there has been a power-up sequence. This internal bit can be read by a controller for self clearing system functions. This internal reset bit is cleared only after a command is received affecting either relays or switchleg functions. It can be used to cause a transmission upon a command to the central controller (see the central control interface section for details). 
     Set-up to cause a single transmission indicating a power-up sequence took place. This is random access unsolicited transmission to the central controller who could decide to take command action. Only one transmission of this message is allowed. The Internal Reset Bit is not to be cleared after this transmission. 
     Note: There is a distinction between the &#34;reset protocol&#34; and power-up sequence. The reset protocol although a subset of the power-up sequence can be activated by a command from the central controller. When invoked by the controller the internal reset bit is to be cleared since it is only associated with a physical reset of the microcomputer. 
     A power-up sequence can only be executed either by a true power-up, watchdog reset trip, or by activating the reset button. A reset protocol sequence can be executed by either a power-up sequence or on command from the central controller. 
     Addressing 
     The transceiver product will have a 10 bit address similar to the existing product configurations. However, the address scheme will support the following extensions: 
     Hardware 
     The hardware for the enhanced transceiver according to the present invention includes the following: 
     A. Data line transmitter/receiver circuit 
     B. Watchdog reset &amp; voltage monitoring circuit 
     C. Jumper selection circuit 
     D. Address decode circuit 
     E. Switch input module circuit 
     The following is a list of particular objectives of the present invention: 
     A first object of the invention is to provide the ability to monitor binary input sensors upon command from a central facility over a shared or common data communications link. 
     Another object of the invention is to provide a means to selectively disable individual switch inputs so that they can be ignored and no action take place during certain conditions defined by the central facility means. When a switch input is masked, no transmission or any action will take place upon the subsequent change of state of said masked input. 
     A further object of the invention is to provide a novel switch threshold multiplexing apparatus with improved input filtering. The multiplexing scheme is achieved by shifting the input threshold to comparators so that a multiplicity of switch input lines can be multiplexed into a microprocessor for subsequent processing. This threshold shifting means as a technique for multiplexing is distinguishable over Tri-State devices previously used in OR-TYING inputs onto a common bus. 
     A still further object of the invention is to provide the ability to read an accumulated last state transmitted for each individual switch monitored by the input transceiver. This accumulated state memory would not only contain the actual state of two wire maintained contacts but also the last state of actuation of previously actuated three wire momentary contacts. Since a momentary contact input disappears, its ON/OFF condition is lost unless it is remembered. The apparatus has been provided to remember such changes in state and allow it to be interrogated upon command by a central controller means. 
     An even still further object of the invention is to provide a secure or answer back response to binary input actuations. This will insure that the responding device will have read and acknowledged the switch actuation. This is needed to verify the response due to critical inputs, such as alarms, demand, light levels, and temperature changes. 
     Another object of the invention is to provide for the annunciation of input module powerup or erroneous reset. This annunciation will insure the integrity of the distributed data base while enhancing the system&#39;s diagnostics and self correction capabilities. 
     To accomplish these and other objects, a separate input transceiver module was developed extending the capabilities of the Miller &#39;414 system. The switch input or binary input transceiver module is configured to plug into a mother board similar to that of the relay transceiver Ser. No. 547,619, filed 11-1-83. It can be housed in a panel where there are both binary inputs and relay outputs provided. As in the prior art, this input transceiver connects to the low voltage twisted pair data communications link connecting all remotely located transceivers or load control processors to the central controller means. The binary input transceiver is responsible for providing a simple contact closure input port for control override commands to the central controller means. Upon the actuation (change of state) of any of the monitored binary inputs, an automatic transmission back to the controller is initiated by the transceiver. The specific improvements in this invention allow the central controller to monitor binary sensor inputs to determine appropriate control action. These binary inputs are read on command from the controller but further improvement was made to allow for the masking of certain switches disabling them in accordance with commands from the central facility. 
     An additional feature was provided to insure the actuation in response to binary inputs. This feature is known as the answer back or secure mode switch transceiver which periodically transmits the actuation of the binary input until receiving a positive acknowledgement from the central controller means that the sensor was read. Additional diagnostic capability was provided to interrogate the last state accumulated of all momentary and maintained binary input sensors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the switch input module according to the present invention; 
     FIG. 2 (including FIGS. 2A-2C) is a schematic diagram of the switch module with the data line transceiver omitted. A schematic diagram of the data line transceiver portion of the relay module can be found in the Miller &#39;414 patent, FIG. 8, incorporated by reference into this application; 
     FIG. 3 is a block diagram showing the various functional blocks of the firmware associated with the switch processor (microcomputer) shown in FIG. 1; 
     FIG. 4 is a further block diagram illustrating the function of firmware associated with the switch processor (microcomputer) shown in FIG. 1; 
     FIGS. 5-38 are detailed flow charts illustrating the functions carried out by firmware associated with the relay processor; and 
     APPENDIX 1 is a complete listing of the object code associated with the switch processor which carries the functions illustrated in FIGS. 3-38. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1 there is shown a block diagram of the switch module, according to the present invention. 
     The central controller (Reference numeral 50 shown in FIG. 1 of the Miller &#39;414 patent) communicates with a plurality of transceiver decoders via bi-directional communication link. In the preferred embodiment, this bi-direction communication link is constituted by a twisted pair 58 (correspondong to twisted pair 58 shown in FIG. 1 of the Miller &#39;414 patent). A switch processor 300, preferably an 8049 microcomputer, receives commands from twisted pair 58 and sends information to the twisted pair via a data line transceiver 400. Data line transceiver 400 was shown in detail in FIG. 8 of the Miller &#39;414 patent and therefore will not be detailed in schematic form. 
     Data line transceiver 400 couples relay processor 300 to the common communication link (twisted pair 58) used to transmit serial data to and from the central controller (not shown but corresponding to central controller 50 in the Miller &#39;414 patent). Data line transceiver 400 contains both a receiver and a transmitter to facilitate bidirectional data communication. Both the transmitter and receiver are optically isolated from any ground reference thereby providing a noise immune balanced driver capable of rejecting common mode disturbances and receiving differential signals. Serial data is transmitted in a similar fashion as described in the Miller &#39;414 patent and is received from the data line over the SOD line. Transmitted, output data such as for example information related to switch contact closures is impressed onto the data line via the SID line. 
     Associated with processor 300 is a watchdog reset circuit 500 including a watchdog timer 500 and associated circuitry. Watchdog reset circuit 500 is responsible for causing or generating a reset pulse to processor 300 under the following conditions: 
     A. Power on; when power to the system is first applied. 
     B. Low power; when the power to the system falls below a predetermined operating voltage. 
     C. Watchdog Time-out which results when the processor 300 fails to retrigger the watchdog timer 500 within a predetermined time interval. The trigger to the watchdog timer is reset every time processor 300 causes a pulse on the watchdog out line. This line is AC coupled to the watchdog circuit to insure only transitions cause a reset. By forcing processor 300 to pulse its watchdog output line, it is insured that the system will remain in a deterministic state. If for any reason processor 300 fails to reset the watchdog timer within a predetermined time interval, timer 440 will force a reset on the reset line of processor 300 in an attempt to restart it. This will self correct the system to a deterministic state reducing the systems vulnerability to spurious signals. A reset pulse is generated periodically until the watchdog reset signal appears acknowledging the proper operation of processor 300. After a reset, processor 300 will annunciate the occurrence on the data line. 
     A jumper selection matrix 600 is used to select an operating mode of a relay module. This allows a multiplicity of functions to be achieved with essentially one apparatus configuration. By the use of the jumper selection matrix 600, the apparatus can be particularly configured for a special application. The jumpers are: 
     W1: (selects normal or answerback switch inputs), 
     W2: (not applicable), 
     W3: (not applicable), 
     W4: (8 or 16 switch input select), 
     W5: (communcation, new or old format), 
     W6: (3 wire or 2 wire (momentary or maintained, respectively) switch configuration). 
     An address input multiplexer 700 provides for the multiplexing of address bits into processor 300. This allows the multiple use of a common set of input/output lines to processor 300. 
     A switch input circuit 800 couples external contact closures or switch inputs to processor 300. The circuit provides the necessary buffering and protection against transients that can couple on to externally routed switch cables. There are 4 banks 850 of 4 3 wire inputs that are multiplexed into the microcomputer. Each switch input (3 wire) has a red (ON) and black (OFF) and a common wire. Therefore, three (3) lines are required for each switch to read an ON/OFF contact closure into the microcomputer. In the 2 wire configuration only the red (ON) wire or line is utilized to determine the state of a switch contact. 
     A switch power supply circuit 900 provides two power outputs, the switchleg power V SL  and the reference power V30. The VSL will to breakdown oxides that may form on switch contacts while providing the necessary noise immunity. The V30 supply acts as a reference to the switch enable input for each bank. When a bank is enabled V30 is divided by 2 to provide a reference threshold voltages used to read the switch input. When the bank is disabled the enable lines are pulled to V30 thereby disabling the switch bank. This enabling/disabling requires that V30&gt;VSL+1 volt. 
     There is further provided a five volt regulator 950 for supplying power to the logic circuits. 
     Switch processor 300 functions as a sequential logic machine that is configured by firmware to perform all the control and communication processes discussed above. 
     A detailed schematic diagram of the switch module is shown in FIG. 2, including FIGS. 2A-2C. 
     The Watchdog circuit 500 has several functions. The first function is a power-on reset function. The second function is a voltage monitoring function that holds the microprocessor in reset whenever the microprocessor power goes below limits. The third function is to act as a watchdog for the microprocessor. In normal operation the microprocessor will send a string of signals through Pin 25, the Prog pin, to constantly reset an RC combination. Should the microprocessor get hung up in an endless loop, or get &#34;lost&#34; in its program, the RC combination will time out and provide a series of reset pulses to the microprocessor, allowing the system to restart without manual intervention by the customer. The watchdog sequence starts with pulses appearing on Pin 25 of the microprocessor. This pin is under software control in the microprocessor. It is directly connected to Pin 9 of U-2 which is an inverter. The inverter in this case is used as a buffer. This buffer drives C-10, a 470 picofarad capacitor which in turn drives the base of Q-10 a 2N2907. When microprocessor signal goes high causing the inverted buffered signal to go low, the base of Q-10 conducts current pushing a pulse of current into C-7 through the collector of Q-10 and charging C-7. R-15 is the time constant determining resistor. The combination of R-15 and C-7 determine how often the pulses must come from the microprocessor to prevent a watchdog reset. In this case, the time constant is 100 milliseconds. R-14 is connected across the base emitter junction of Q-10 and serves to turn off Q-10. CR-2 provides a current path to the current on C-10 when the signal from the buffer inverter is a high level going signal. The primary purpose of C-10 is to provide DC isolation of the reset signals from the microprocessor. In this type of coupling it is not the absolute level of the signal from the microprocessor that determines when a watchdog reset occurs, rather it is the period between transistions of the microprocessor signal that determins when a watchdog reset will occur. Assuming a high level voltage on C-7, R-15, this high level voltage appears on the minus input Pin 8 of the comparator U-6. Since the minus input is at a higher voltage than the position input, then the output of this comparator on Pin 14 will be low. This low level signal is directly connected to the minus input of comparator input Pin 10, another section of U-6, and since in this case the minus input is less than the positive input, the output of this comparator section on Pin 13 will go into the high impedance state allowing R-13 to pull up the reset line, although delayed by C-18. C-18&#39;s prime function is to provide a power-on reset. It will hold the microprocessor in reset upon the event of power-on for approximately 500 milliseconds. Should the watchdog pulses cease to occur, Q-10 will stop charging C-7; C-7 will discharge thru R-15 and the voltage on Pin 8 will drop below the voltage on Pin 9 of the comparator, forcing Pin 14 into a high impedance state. R-12 will charge C-6 until the point that the voltage on Pin 10, the minus input of the comparator, will exceed that of Pin 11, the position input of the comparator. The comparator will then clamp low on the output Pin 13 and put the microprocessor into a reset state. It will be held in that reset state until R-12 discharges C-6. This time constant is approximately 20 milliseconds. Thus when the microprocessor fails to give watchdog pulses, the reset line will be given a series of 20 millisecond reset pulses. The rise time on this reset pulse will be determined by R-13 and C-18 and will be very slow as a result. This is of no consequence to the processor which has built in reset hysteresis. R-10 and R-11 provide hysteresis in the comparator circuit for the RC time constant just as R-9 and R-13 provide the hysteresis for the oscillator function. The savings of two resistors was achieved by using R-7 and R-5 combination as a voltage reference. This provides the voltage reference of approximately 2.5 volts and is used in several instances. The low voltage reset circuit operates using R-20 and CR-4 as a 4.3 volt reference into the comparator U-9. This voltage reference is fed into a minus input Pin 10 and is compared to the 5 volt supply of the microprocessor on Pin 11, the positive input. When the microprocessor supply drops below 4.3 volts, the microprocessor is held in reset through this comparator output Pin 13. The jumpers in jumper selectin matrix 600 use the internal pullups of the 8049 and are activated by coupling jumpers to ground. The first jumper, W-1, is called the feature jumper. The second jumper W-2 is not used. The third jumper, W-3, is the type jumper. The fourth jumper, W-4 selects the size. The fifth jumper W-5 is the communications mode jumper. C-8 and C-9 are the start-up and harmonic filter for the crystals Y-1. 
     Address Decode Circuitry of the Switch Module 
     Address decoder 700 decodes the address bits one at a time using a 74LS156 as a decode mechanism. The 74LS156 is used in the dual two-line to four-line decoding mode. This is necessary because it shares control lines with the switch multiplexing circuits. Pins 3 and 13 are used as the data input while Pin 15, Pin 1, and Pin 2, Pin 14 connected together are used as enable lines. Using these three lines of control enable allows the multiplexing of control information and address information. The combination of Pin 2 and 14 can be viewed as an overall chip enable. It is active low. Pin 1 can be viewed as the enable pin for the first two-line-to-four-line converter. It is active high and enable the outputs on pin 7 through 4. The second two-to-four converter enable pin is Pin 15 and is active low. In order to determine which address lines are set on the dip switch pull Pin 2 and 14 low and then choose one of the two banks of two-to-four converters. For example, one might put Pin 1 high enabling the first bank of two-to-four conversion. If then both Pins 2 and 13 were zeroes, that is low levels, then Pin 7 would be activated by a low on the output. If the address line zero dip switch is closed, the output of the LS 156 pulls the input line going to port 1, data bit 4, low. If that address line dip switch is open, the pull-up resistor connected in conjunction with this dip switch pulls the line high and a high-level signal would be read. If one now wanted to read the next address bit location, one again pulls Pin 2 and 14 low as a chip enable, put Pin 1 high as the first bank of two-to-four selector enable while leaving Pin 15 high to disable the second bank of two-to-four conversion, set Pin 3 address 1 input low and set Pin 13 a zero input high. This wouild enable Pin 6 low on the output side which is connected through the address switch selector to port 1, data bit 4, input. Similarly, the other address lines may be read when using the second two-line to four-line converter. Pin 1 is put in a low state, Pin 2 and 14 are enabled and Pin 15 is put into a low state to enable the second bank, that is, outputs 9 through 12. Pin 1 and 15 could not be tied together and Pin 2 and 14 used as the enable lines because when 1 and 15 are tied together, one of the two decoders will always be enabled. When a relay is being pulsed, this output could interfere with proper pulsing of the relays. 
     The 5 volt regulator consists of a 3 terminal regulator, a 78MO5, which is designated Q-6, and its associated decoupling capacitors. Worse case power dissipation occurs with a 20% error on the high side of the 9 volt source. The power dissipation in a worse case current draw of 150 milliamperes is 0.7 watt. This would mean that without a heat sink this regulator will have a 43 degree C. rise in temperature. This is acceptable given that the ambient environment will not exceed 60 degrees C. and the rated junction operating temperature is 150 degrees C. We will safely be at 100 degrees C. worse case operating temperature. 
     When jumper W-3 is inserted as a jumper on port 2, data bit 4 of the microprocessor, it indicates to the processor that it is an input type of module. In this case, input mode will be switchlegs. In a switchleg module all circuits are the same as in the relay module with the exception of the relay driver section, which is an output section. That section is transformed into an input section. 
     A switch is read using a comparator which compares the switch input voltage to a 12 volt reference. If the switch input voltage is greater than 12 volts, the switch is considered in the open connection. If the switch voltage is less than 12 volts, the switch is considered in the closed position. The output of the comparator is fed directly to a data bus input line. A typical input starts with a 3.9K pull-up resistor to 24 volts connected to one of the switch contacts and the other switch contact connected to ground. A switch closure then connects the two contacts. The connection of the contact with the pull-up resistor is brought through a 10K resistor to the comparator input. In Switch Number 1, the comparator input would be Pin 6 of U-8 the negative input. This input also has a 0.1 microfarad capacitor connected to ground. The 10K resistor and the 0.1 capacitor form a RC noise filter with a 1 millisecond time constant. Further filtering of the signal is done in software. This signal is compared to the positive input terminal, Pin 7 in this case of U-8. Normally this pin is pulled up to approximately 30 volts. This makes the comparator output a high impedance state. When the microprocessor wishes to read this comparator, the microprocessor activates port 1, data bit 7. This pin is connected also to a comparator, Pin 8 of U-12, the inverting input. When this comparator input is activated, low, its output goes low and the voltage on U-8, Pin 7 is cut in half through R-23. This makes the voltage at Pin 7 of U-8 approximately 12 to 15 volts as opposed to the previous 30 volts. The microprocessor can now read the data bus port as an input and this switch #1 will appear on D-0 Pin 12 of the microprocessor, which is pulled up by a 4.7K resistor. When the switch is not active the DB0 will be low. When the switch is active, that is grounded, the DB0 will then go high. To use the processor efficiently, eight switch inputs are read at a time. That is port 1, data bit 7 enables eight comparators at one time. In this case, it was convenient for software processing to read eight switch inputs of the same indication, that is, ON or OFF. For example, when port 1, data bit 7 isenabled, we read the &#34;NON&#34; input of switch 1, 2, 3, 4, 5, 6, 7 and 8 of the low address transceiver. When port 1, data bit 6 is enabled, we read the &#34;OFF&#34; switch input of switch 1, 2, 3, 4, 5, 6, 7 and 8 of the lower address. The optional high order address switch inputs work in the same manner except that the &#34;ON&#34; switch bank select is port 1, data bit 4 and the &#34;OFF&#34; switch bank select is port 1, data bit 5. 
     In the switch power supply circuit 900, a 34 volt source is fed into the daughter board. Noise is decoupled by C54 0.01 microfarad capacitor. Q-5 in conjunction with R-30 and CR-7 form a voltage regulator regulating the input voltage down to approximately 31 volts. This is necessary to protect the LM339 which have a maximum operating voltage of 36 volts. Should something happen to the power supply, and the nominal 34 volts go above specification, this regulator will protect the 339&#39;s. Furthermore, in ordinary operation this regulator will reduce the stress on the 339&#39;s increasing the MTBF. C-55, a 150 microfarad capacitor, is a filter capacitor to hold up the 30 volt lines while relays are pulsing. The 30 volt supply is used for the 339 positive input and for the bank select of the comparators. The 30 volts also feeds a 24 volt 3 terminal regulator. 
     The 24 volt supply supplies the reference voltaqe and pull-up voltage for the switch inputs. Each switch input is connected to this 24 volt supply via a 3.9K pull-up resistor. Worse case power dissipation in Q-4 occurs if all switch inputs were activated to some state. In this case Q-4 would dissipate approximately 1.4 watt, caused by a 200 milliamp current drain and a 7 volt differential. This would cause an 84 degree C. rise in Q-4, where the allowable junction temperature in 150 degrees C. 
     When a switch is activated it causes a current of 6.15 milliamps to flow through its corresponding pull-up resistor. The power dissipated in this 10K resistor is 0.15 watts; maximum power allowable dissipated by a single resistor is 0.2 watts in this type of single inline packaged resistor network. This represents a 25% power margin. However, at the package level, the networks have been wired such that red and blacks were on and offs of same switches are connected to the same SIP. This means that at any given time only one-half of the resistors in a network can be activated so that the power dissipated at a package level is less than 50% of the allowable power. Using this type of margin insures a long life for the resistor packages. With the same life consideration reasons, the decoupling capacitors and filtering capacitors are 50 volt capacitors with 24 volts applied. This type of derating insures long life for the product. 
     The following table sets forth a pin-out of processor 300. 
     
         ______________________________________Pin      Function Pin        Function______________________________________ 1       N.C.     21         ADDR8 2       XTAL2    22         MODE 3       XTAL2    23         COMM 4       RESET    24         SIZE 5       N.C.     25         WDSTB 6       Vcc      26         Vcc 7       GND      27         G2ADRS 8       N.C.     28         ADRIN1 9       N.C.     29         ADRIN010       N.C.     30         ADRSEN11       N.C.     31         ADRINP/G2ON112       SLINP1   32         G1ADRS/G3OFF113       SLINP2   33         G0ON014       SLINP3   34         G1OFF015       SLINP4   35         GND16       SLINP5   36         N.C.17       SLINP6   37         FEATURE18       SLINP7   38         SOD19       SLINP8   39         SID20       GND      40         VccSLINPx    1 = MAKE,       0 = BREAKMODE      0 = MOMENTARY,  1 = MAINTAINEDFEATURE   0 = SECURE,     1 = NORMALSIZE      0 = ONE ADDR    1 = TWO ADDRCOMM      0 = NEW         1 = NEW &amp; OLD______________________________________ 
    
     The following table sets forth switch group selector. 
     
         ______________________________________ON SLINP1-SLINP8     G0ON0     G1OFF0   G2ON1   G3OOF1______________________________________BANK 0 RED 1         0        0       0BANK 0 BLACK      0         1        0       0BANK 1 RED 0         0        1       0BANK 1 BLACK      0         0        0       1NO SWITCHES      0         0        0       0______________________________________ BREAK is a &#34;0&#34; or low impedance on SLINPx. MAKE is a &#34;1&#34; or high impedance on SLINPx. 
    
     Referring now to FIGS. 3 and 4 there are shown block diagrams of the functions performed by the firmware associated with the switchleg processor. 
     The Switch Transceiver comprises the previously described hardware apparatus and several software or firmware procedures and processes described below. The block diagram of the Switch Transceiver is depicted in FIGS. 3 and 4, and provides a functional description of each of the software process blocks. The firmware is embodied in the object code listing set forth in complete form in Appendix I. 
     Referring to FIG. 3, the sequential control unit is formed by the TIMINT (timer interrupt service routine) and the Executive (EXEC) routines. The purpose of this section is to provide the 6 msec timing signal and monitor the status of the various other processes. It is further responsible for the task dispatching to all process functions. 
     The address input sequencer and address and jumper buffer holding registers described in the MODIDN process provides a means of uniquely identifying a switch transceiver, as well as configuring the product via user or manufacturing installed jumpers to support various selectable features. 
     The command decoder operates upon data contained in the memory buffer area consisting of messages received from the data line receiver. The DECODE process checks the validity of the messages (through parity or checksum calculations), the proper address (ADRCHK process) and the command type. The command decoder will place the proper data into the memory buffer area and status registers of the sequential control unit for subsequent dispatching to the proper task to perform the desired action. The decoding of a valid message results in the incrementing of a good message count register used for internal system diagnostics. (description of RCUSRV &amp; XMTSRV) 
     A receiver means (RCVSRV) similar to that described in Miller &#39;414 can be utilized in order to convert the incoming serial data stream into a parallel form in the memory buffer area suitable for command decoding. 
     In addition, a transmitting means (XMTSRV) similar to that described in Miller &#39;414 can be utilized in order to convert parallel data from the memory buffer area to the serial format of the common data line. 
     FIG. 4 describes the processes associated with the sensing of binary inputs. The switchleg input sequencer (SLSRV) works in conjunctin with the switchleg 48 ms timer (TIMINT) to control the reading and subsequent transmission of switch or input actuations or states. 
     Upon command from the switchable input sequencer the switch input buffer (READSL) will input the proper bank of switches through a 100 microsecond digital noise filter from the multiplexing apparatus. 
     A comparator function compares the original switch reading register (from the previous reading) to the current input value, and places those inputs whose state have changed into a switch change register (GETSWT). 
     The switch mask processor will eliminate any non-enabled switch changes from the switch state word indicated by the switch mask register (user programmable). 
     The switchleg output processor (UPDSL) will operate on the generated switch state word and place it into the memory buffer for subsequent transmission. In addition, an accumulated switch register which is user interrogatable, is formed and contains the last state values of all switches that have been actuated. 
     Finally, a 1 second acknowledgement retransmission timer in conjunction with the switch acknowledgement register (from the UPDSL process) allows for a switch to be retransmitted repeatedly until it is confirmed and removed from the switch acknowledgement register. This provides for a more secure means of transmitting a switch actuation, and guarantees that it will be received. 
     FIGS. 5-38 detail in flow chart form the specific functions of the switch module. 
     Switch Input Processing 
     The purpose of the switch input processing section is to read contact closures or switchleg inputs. During this process, the switch inputs are filtered, interpreted and are appropriately setup for transmission onto the data line. This includes specifically the handling of both maintained (2 wire) and momentary (3 wire) switches and maintaining a queue of swtiches that have been activating for subsequent transmission out over the data line to be received by appropriate sensing or controlling devices. 
     The transmission of these switch inputs (which may or may not involve a special answer-back or secured mode transmission sequence) is also handled in this section. If the transceiver is in the answer-back mode, then a process is established which will keep transmitting actuated switches until an acknowledgement is received back from the controlling or sensing device indicating its reception of valid switch data. This answer-back or secured transmission process involves waiting for a period of approximately one second for an acknowledgement after a transmission of actuated switches were made. If after this one second interval an acknowledgement has not been received by this transceiver the switch actuation message will be repeated and retransmitted back over the common communication link (or the data line). It should be noted that during this subsequent transmission that if there are any new switch actuations that have occurred since the first (or previous) transmission, that these new switch actuations will be included and thereby queued in the switch actuation message that is transmitted over the data line. Furthermore, when a new switch position has been activated while waiting this one second interval for a previous switch acknowledgement the switch information which includes the past transmission plus the new switch will be transmitted immediately upon the actuation of this new switch even if it occurred before the one second period for the acknowledgement has elapsed. 
     The switch acknowledge, or secured mode switch process, is a selectable feature which is invoked by a jumper inserted in the printedcircuit board during manufacture. This feature, which could have been programmable through commands over the communications link, was implemented as hardware invokable so as to avoid any possibility of spurious signals causing the complex electronic circuits to assume this answer-back function. It was desired to provide this feature for future applications that may involve interfacing to external machine, computing devices or threshold responsive sensors to insure that no data is lost during the normal action in a centralized control system. However, other devices such as normal wall-mounted switchlegs for purposes of turning ON and OFF lighting and other loads, which are typically human actuated, are not desired to continuously transmit until an acknowledgement is received. This is to avoid taking deferred action on human actuated devices when, in fact those actions are no longer needed when the system returns to its normal operation state after a long period of down time which may occur in a centralized control system. In summary, this answer-back feature provides an extra degree of security in the response to contact closure inputs to our central control system. This security is jumper selectable so that it can be applied selectively to loads which need and desire such security. 
     The processing of switch inputs is performed in the following sequence: 1. switch readings are made at no less than 48 millisecond intervals; 2. during the reading of switches they are appropriately filtered; 3.  the switch inputs are then interpreted by considering it to be of either the 2 or 3 wire type; 4.  a determination is made as to whether the switch is indeed allowed to be active and cause transmissions to take place over the common communication link. The resultant of this process, on a valid switch actuation, causes an appropriate transmission word indicating which switch and the state (ON/OFF) that has been actuated to be transmitted on the common communication link for further control or sensing processes by other devices. 
     A switch reading period takes place at no less than every 48 milliseconds. This is to avoid multiple readings of the ON/OFF state of contact closures (switches) due to excessive mechanical bounce which are typical properties of both human actuated mechanical devices and electromechanical devices. 48 milliseconds was chosen to insure that the reading or measurement interval would be greater than this bounce period to reject erroneous multiple actions. Compensating for mechanical bounce of contacts using this period measurement interval method will result in a switch reading that is said to be debounced. The maximum switch interval reading is nominally 100 milliseconds. Since this was determined to faster than multiple actions on a human actuated push button switch, this will insure that no switch request is lost since the measurement interval will always be faster than human inputs. 
     After the 48 millisecond switch reading interval, switches are then read for a period of 100 microseconds sampled at a high rate. This is to utilize digital filtering techniques, rejecting switch actuations caused by spurious signals. This 100 microsecond sampling period for switch readings yields a 10 kilohertz cutoff frequency low pass filter. It should be noted that in addition to the digital filtering techniques, hardware signal filtering is provided with appropriate lumped elements. This further insures the integrity and validity of any contact closure or switch inputs. 
     After the switch is read, a determination is made whether to process the contact closure inputs as either 2 or 3 wire devices. This determination is made by a customer selection provided on the transceiver. The 2 wire switch, organized as a single-pole, single-throw device, operates such that an ON condition is considered the make of the contacts while an OFF condition is considered the break of the contacts. The 3 wire switch conforms to the single-pole, double-throw contact arrangement. In this arrangement, an ON condition is considered when one side of the contacts are in the make condition. An OFF condition, or state, is actuated when the other side, or contact, is in the make condition. Any break actions from either contact is considered no action, or change of previous state. This would allow applications of push-button momentary switches. It should be noted that the 3 wire single-pole double-throw switch arrangement is rejected if both contacts are actuated or in the make condition simultaneously. This is to avoid erroneous assumptions of the conditions of these switches since the simultaneous make states is defined by convention as a forbidden state. 
     After the determination of 2 or 3 wire switches, the switch actuation is compared to a predetermined switch mask which specifies the switch positions that are enabled, that is, that are allowed to be actuated and cause subsequent communication to occur on the common communication link. The switch mask provides the capability to define selectively which switch is enabled. This selective definition is programmed via the common communication link by external devices. The setting of this switch mask is described in the command decoder section of this description. 
     After a switch is read and the appropriate state is determined (that is, whether it is ON or OFF), it is compared to its last valid state read in the previous 48 millisecond interval. If, and only if, there is a change of state (that is an ON to an OFF or an OFF to an ON condition), an automatic transmission will take place over the communication link to inform remotely located devices of the switch change. This will effectively broadcast the switch actuation immediately so that appropriate control or sensing functions can take place. If there is a message from the previous 48 millisecond interval that is still awaiting transmission due to a busy communications link, the new switch actuation message will be queued and added to the pending outgoing message so that it can be included for transmission in the first free communication opportunity. 
     In addition to establishing a message to be transmitted over the communications link, the new switchleg input states are merged into the accumulated switchleg buffer. This buffer contains the accumulated history of all switch inputs since resetting this buffer. This historical information recording the last ON/OFF condition of all contact closure inputs provides the ability to maintain a record of said states even when applied momentary contact or switch devices; that is, although a momentary contact is only in a temporary make condition indicating its ON/OFF state this accumulated buffer will hold this state for subsequent interrogation by other devices over the common communication link. 
     The process that performs the entire switch handling function is called switchleg service and is designated as &#34;SLSRV&#34;. The process flow for the switchleg service function is described in FIG. 5. This process is performed on-command by the main process executive. Referring now to FIG. 5 upon entering the switchleg service process a check is made to see if this transceiver has been defined to have switchleg capability. If not, it aborts and returns back to the exec for further processing. If it does, the interval timers for the switchleg reading and for the retransmitting of non-acknowledged switch transmissions are updated. The updating of these timers includes the time elapsed from the last update or service which can occur any time. Using an internal 6 millisecond timer, the switchleg reading interval timer and the acknowledge retransmission timer are updated to reflect the time lapse, if any, from this last reading. This will insure when long messages are being received over the communications link that these timers will not be unduly neglected and can thereby be updated compensating for any lag due to alternate processing activity. After updating the timers, a check is made to determine if the unit has been selected to be in the answer-back mode. If the system is in the answer-back mode, a check is made to determine if the retransmission acknowledgement timer has timed out. If it has, a further check is made to see if there is still a message that needs to be transmitted over the common communication link. lf there is, that message is moved to the appropriate output buffer for subsequent transmission and the acknowledge retransmission timer is reset followed by a return to the system executive. It should be noted that this acknowledge retransmission timer is set to cause a retransmission of switch actuation at one second intervals if they have not been acknowledged. This will insure the integrity of the actuated switch inputs by proividing a hand shake with the external receiving device. If the system is not in an answer-back mode, or if it is in an answer-back mode and the one second timer has not timed out, a check is made to see if the debounce interval timer has timed out. If it has not, further processing is aborted and the system returns back to the system exec. If this timer has timed out, the system assumes it&#39;s now time to read switches for further processing. It should be noted that this timer is set for a minimum interval of 48 milliseconds to compensate for the worst case of mechanical bounce that may be associated with devices connected to the contact closure or switch inputs. 
     The system continues by reading the switch inputs by transferring control to a process titled &#34;READSL&#34;. Continuing, after reading the switch inputs, a process called &#34;GETSWT&#34; takes control which is responsible for processing switch inputs and sets up any messages that are needed to be transmitted over the data line in response to switch actuations. After processing the switch inputs and determining its type, various modes and effects of any switchleg mask that might have been defined, the system resets the debounce interval timer to set up for the next switch reading and returns back to the system exec. 
     The reading of the switch inputs is handled by the process called &#34;READSL&#34;. The read switchleg process reads 4 groups of 8 switch lines each at a time. These 4 banks are multiplexed in order to make use of an 8 bit bus structure. Each group is read and processed separately. The read switchleg process results in an accurate reading of the state of the contact closures in each of the 4 groups stored in appropriate registers along with a register indicating whether noise was discovered in any of those switch positions. 
     Referring now to FIG. 6. When entering the read switchleg process, the switch input apparatus, which contains the multiplexing hardware, is initialized along with the resetting of the switch noise indication registers and a register pointing to the first group. 
     It should be noted that two out of four groups are associated together within a bank, and that there are two banks. Bank 0 is associated with groups 0 and 1, and Bank 1 is associated with groups 2 and 3. The association of two groups to a bank provides for the reading of 3 wire switches with their ON and OFF contact arrangement. Furthermore, the two banks, 0 and 1, correspond to the multiple addresses allowed for the switch transceiver. Although, as previously described, the switch input block is in a logical 8 position group, two blocks have been defined in one device allowing it to respond to two separate address locations for the purposes of communicating over the common communication link. In other words, due to the method in which switches are handled by 8 switch input groups, a 16 switch input module was achieved by having it respond to two independent addresses. It should be further noted that this 8 position switch group was arbitrary and is, in fact, independent of this design. 
     After the initialization of registers and the apparatus, a group is now enabled for input (initially group 0). The 8 switch positions are now read and are taken as the first reading and saved as the actual switch state. After the first reading, the group is now sampled again and a check is made to see if it differed from the first reading. If it did, an indication of the bit position corresponding to the changed switch will be set and saved in a noise register for later processing. This process of reading a group, comparing it with the first reading, and building a noise register based on any differences in the first reading and subsequent readings continues for a period of 100 microseconds. This 100 microsecond sampling loop, as indicated in FIG. 6, provides the digital filtering needed to reject any high frequency noise. After this 100 microsecond group read loop has completed, the process continues by updating the group pointer to the next group (that is, the pointer will now point to group 1 if it previously pointed to group 0) in order to read the next 8 switch input or contacts. A check is made to see if there are any more groups to read. If so, the system loops back and enables the group for input and repeats the filtering process for the next group as indicated in the figure. After all the groups are read in, the actual switch state from all the groups (which represent the first reading) are stored in appropriate switch state registers and the noise registers are set as a result of subsequent readings being different from the first, the system exits back to the supervisory process. 
     The actual processing of the switchleg inputs and recognition of valid switch changes is performed by the process called &#34;GETSWT&#34;. This GETSWT process is depicted in FIG. 7. Upon entering the process, it assumes that switch information has been read in and stored in the actual switch state register and noise register as described above. The output of this GETSWT process will result in the transmitter output buffer being loaded with a valid switch change word (indicating secured switches or one of the two formats for standard switches) for subsequent transmission over the common communication link, if it has determined that, in fact, a switch change took place references to the previous valid switch reading. 
     Referring now to FIG. 7, the first group of the Bank is processed by the &#34;CHGBIT&#34; proces of FIG. 9. This process takes the noise register, the previous valid switch or reading (or original switch register) and the new actual switch state reading and creates a register of valid switch changes indicating which switch positions actually changed and a register indicating the ON/OFF state of those switches with respect to the group being processed. A make is defined as an ON or a logic 1 and a break is defined as a logic 0 or OFF. It should be further noted that in a 3 wire configuration this process is repeated for the other group and later further processed to determine the ON/OFF state based on make/make switch action. 
     After this switch is preprocessed, as was described above for the &#34;CHGBIT&#34; process routine, the system continues by checking if the switch inputs are configured as 2 wire or 3 wire. For 2 wire inputs, a state change word for the ON condition is determined. This word is taken from the ON/OFF state word returned from the &#34;CHGBIT&#34; process which is then masked with the switch enable mask to eliminate disabled ON switches. The result of this operation is then saved in the valid ON change register. The above three steps are repeated for the OFF condition. This time the OFF state is determined from the inverted ON/OFF state word return from &#34;CHGBIT&#34; and the disabled OFF switches are masked out with the ersults saved in a valid OFF change register. The process then creates an effected switch word by ORing the valid ON change register with the valid OFF change register established above. This will yield an effected switch register such that a logic 1 represents an effected switch that had changed from the previous valid state and the logic 0 would indicate no change. Furthermore, the ON/OFF state word is defined to equal the valid ON change register, such that a logic level 1 is equal to the ON condition and 0 to the OFF. It should be noted, however, that the respective bit positions starting from bit position 0 to bit position 7 in both the effected switch word and state word correspond to switch numbers 1 through 8 respectively. 
     Referring back to FIG. 7 for the 3 wire switch configuration a state change word for the ON condition is similarly determined and masked with the disabled ON switches which is then saved as the valid ON change register. However, the process then calls the &#34;CHGBIT&#34; process (FIG. 9) for the second group in order to process the OFF state condition. Similarly, as with the ON, a valid OFF change register is formed by masking out the disabled OFF switch positions. After this step, the process merges both the ON and OFF valid change registers togehter, eliminates simultaneous ON/OFF positions in those registers, and forms the effected switch registers which is then saved. The ON/OFF state word is further formed by ANDing the previous valid ON change register and the effective switch register to yield an ON/OFF state word suitable for transmission. After either the 2 wire or 3 wire configuration creates the effected switch word and appropriate state word, a check is made to see if there are any switches that have been affected or changed as indicated by FIG. 8. If there is not, the process aborts and returns back to the calling supervisor. If there is a change called for, the process updates and builds a queue and resolves the accumulated switch buffer (performed by the process called &#34;UPDSL&#34;). The proper transmit flag word is selected to indicate secured switches or one of the two formats for non-secured switches. Finally, the process then takes these valid switch change messages and establishses the appropriate transmit buffer through the utility called &#34;BLDTBF&#34; which readies the information for subsequent transmission onto the common communication link. After this, the process is complete and control returns back to the requesting supervisor. 
     The procedure Get Switch, &#34;GETSWT&#34;, described above invokes another procedure called Change Bit, &#34;CHGBIT&#34;. The purpose of Change Bit is to combine the switch state and noise registers generated by the &#34;READSL&#34; procedure with the original reading of the switchlegs taken during the previous debounce interval. This process will result in the change register having a &#34;1&#34; value set into a position corresponding to a switchleg that has changed state and a bit set within the new state register which indicates the new state of the switchleg (a 1 is a make or ON condition while a 0  is a break or OFF condition). In addition, the previous original reading is replaced by an updated value reflecting the integration of the switch state and noise registers with the original switch register. 
     Referring to FIG. 9, describing the Changing Bit, &#34;CHGBIT&#34;, routine, the process beings by logically ANDing the original group reading with the noise register to form the bits to keep of the original switch register. Next the noise register is inverted and then logically ANDed with the switch register. This forms the bits to keep of the switch register. The bits to keep of the original switch register are logically ORed together with the bits to keep of the switch register resulting in the new switch register. The process continues by forming the Change Bit register which is equal to the exclusive OR of the new switch register with the original switch register. The Change Bit register will contain a &#34;1&#34; in each position corresponding to a switchleg changed its state. A 0 value will indicate no change of state from the original reading. At this point, the original switch register is updated and set equal to the new switch register completing the process which then exists to the calling supervisor. 
     The update switchleg routine &#34;UPDSL&#34;, whose use was described above for the &#34;GETSWT&#34; routine, is responsible for the building the transmit switch mask and state register as well as merging the new switchleg information into the accumulated switch register. It should be noted that the accumulated switch register contains a history of all switchleg actions transmitted over the common data line and is constantly updated with more recent actions. It should be further noted that the update switchleg routine will also combine the new switchleg actions with any recent actions that are pending transmission due to a busy common data line. In addition, the update switchleg routine will combine the new switch actions with any secured switches that have not been previously acknowledged. FIG. 10 indicates that on entry to the UPDSL process a test is made to determine if the transceiver is an answer-back type. If so, then any secured switches pending transmission and the new switch information are combined by the &#34;MERGE&#34; routine. This merging will also occur even if the transceiver is not an answer-back type; if there is switch data pending transmission in the output buffer. If no data is pending, then the new data replaces the old. Continuing with FIG. 10, the new switch information is then combined with the historical information of, and saved as, the accumulated switch register; completing the process. 
     The merge routine, &#34;MERGE&#34; is a process used by the &#34;UPDSL&#34; routine to combine existing switchleg information in the form of a mask and state register with new switchleg information. This process is carried out in such a manner as to keep any uneffected old information and replace any old information that has been changed. 
     Referring to FIG. 11, the process of flow for the &#34;MERGE&#34; routine, an updated switch mask is formed by logically Oring the old mask with the new mask. This new updated mask is then saved in the appropriate register. The bits to keep of the old state is formed by logically ANDing the old state register with the logical complement of the new switch mask register. Continuing with the flow description, an updated state register is then formed by logically ORing the bits to keep of the old state register with the new state register. This updated state is then saved in the appropriate register completing the process which then exits to the calling supervisor. 
     This concludes the description of the switchleg handler which provides: 1. A means of inputting sixteen 2-wire or 3-wire switch contact closures over a multiplexed data bus; 2.  A means of high frequency noise filtering for the contact closures; 3.  A means of avoiding multiple actions due to mechanical bouncing of contact closures; 4.  A means of processing these contact closures and generating effected switch mask and switch state information for subsequent transmission on the common data line; 5.  A means for restricting undesired switch actions from transmission over the common data line; 6.  A means of queuing a plurality of switch actions for transmission over the common data line; 7.  A means of providing multiple transmissions of the same switch action to allow an answer-back acknowledgement of that switch action; 8.  A means of queuing a plurality of new switch actions with previous switch actions that have yet to be acknowledged; 9.  A means of providing an accumulated switch register which will contain the latest switch actions for all contact closure that have occurred (since the time that the accumulated switch register was last reset); 10.  A means of formating the information for transmission in such a manner as to distinguish an answer-back switch action from a normal switch action; 11.  A means of transmitting normal switch actions in two different formats. 
     Decoder Handler 
     The purpose of the decoder handler is to monitor the receiver buffer and determine when a valid message has been received for decoding. When it is determined that a message is awaiting decoding, the message is verified for correctness of format, proper address and the proper check or parity word at the end of the message. Once the validity of the message has been determined, the decoder will recognize various commands for the device in question. The desired actions are then performed which might includes the manipulation of internal data buffers and possible transmission of a reply message to the controlling device via the common data line. 
     The Decoder Handler includes three main routines: the DECODE routine, responsible for decoding the flag portion of the messages as well as performing other supervisory tasks; the Address Check routine, ADRCHK, responsible for verifying the proper address and checksum or parity word; and the Transmission routine, SENDIT, which is responsible for the transmission of data requiring immediate or interactive transmission. 
     The Decode, DECODE, routine is invoked by the executive and is described in FIG. 12. Beginning with the entry point, a test is made of the RVSTAT register to determine if the RCVFLG is set indicating the presence of a message in the receiver buffer. If not, then control continues to Connector B or DECODE2 with is an abort from the Decode utility that will clear the RCVFLG bank indicators and new/old mode bits from RVSTAT and then return to the executive. If it is determined that there is a message to be decoded in the Receiver Buffer, then the utility ADRCHK is invoked in order to check the address and parity or checksum word of the message and build the flag, DF0 and DFl storage register as required. At Connector A, DECOD0, a test is performed on the RVSTAT register to determine if there is a message waiting decoding for either bank 0 or bank 1. If not, then the routine aborts through Connector B. Otherwise, the proper bank, either 0 or 1, is indicated (by setting or resetting F0). A test is then made to determine if the message is in a new format. If so, the control continues at Connector D of FIG. 13. Otherwise, the process completes at connector B. 
     FIG. 13 describes the decoding used for new type commands. Beginning with Connector D, the received flag is shifted two positions to the right in order to skip over the FAFB bits. A test is then performed to determine if the adjusted flag is equal to a value of 0. If so, then a reset command has been issued and the procedure continues with the reset process as shown in FIG. 33. Otherwise, a test is made to determine if flag is equal to 1 indicating a desire to read data with an immediate or interactive transmission (continuing at Connector N of FIG. 14). If the flag is equal to a value of 2, then a command requiring data to be read and transmitted in a deferred method is indicated and control continues at Connector O of FIG. 14. A flag value of &#34;5&#34; will perform the set switch mask process at connector ZZ on FIG. 21. A flag value of &#34;18&#34; will perform the acknowledge answerback (secure) switch process at connector Z (FIG. 20). If it is not possible to decode a new type flag, then the procedure aborts connector B of FIG. 12. 
     At connector F of FIG. 15 the good message counter is incremented to indicate the decoding of a proper command and the bank indicator corresponding to the command just decoded is cleared in RVSTAT. Control then continues at Connector A of FIG. 12 in order to process any information for the other bank. 
     The read status in new format command is described in FIG. 16 at Connector Q. The TEMP1 register is set equal to the A9JUMP value containing address bit A8 and the jumper definition for the TRD. TEMP1 is equal to the STATUS register of the TRD. The flag register is then set to a value of 4CH anda pointer to TEMP0 is established. Continuing at Connector L, an indication is made that two bytes of data are to be transmitted and the process continues at Connector M. 
     Connector R describes the read threshold in new format process. The IBGTHR register is pointed to and the flag is set equal to a value of 50/H. Continuing through Connector U, four bytes of data are indicated to be sent. At Connector M, the previously determined line free requirement and the number of bytes to send are merged together. The process continues with the SENDIT routine described in FIG. 24. 
     Connector N of FIG. 14 is entered whenever there is an immediate or interactive request for data. A collision line free requirement is indicated and control continues at Connector P (FIG. 17). Connector O is entered whenever there is a deferred request for data and a deferred line free requirement is indicated with control continuing at Connector P. 
     Connector P of FIG. 17 describes the decoding performed on the auxiliary flags for the read data request. Data Field DF0 is pointed to and a test is made of the auxiliary flag in that position to determine if it&#39;s equal to 0. If so, then a request for system status is indicated and control continues at Connector Q of FIG. 16. If the auxiliary flag is equal to 1, then receiver thresholds are being requested and control continues at Connector R of FIG. 16. An auxiliary flag value of 2 indicates a desire to return the data line counters (good or bad message counts) and control continues at Connector T of FIG. 18. An auxiliary flag value of 3 indicates a request for ROM code version handled at Connector V of FIG. 18. An auxiliary flag value of &#34;5&#34; will perform the return switch mask function at connector W of FIG. 19. An auxiliary flag value of &#34;6&#34; will perform the return actual switch contact state function at connector X of FIG. 19. An auxiliary flag value of &#34;7&#34;  will perform the return accumulated switch buffer function at connector Y of FIG. 20. 
     FIG. 18, Connector T describes the process for returning the data line counters. The GODMSG register is pointed to and the flag is set to a value of 58H with control continuing at Connector U of FIG. 16. 
     The return ROM code version request is handled at Connector V. A pointer to TEMP0 is established and TEMP0 is then set equal to the ROM code version number. One byte of data to be sent is indicated, and the flag is set to a value of 5CH. Control continues at Connector M of FIG. 16. 
     FIG. 19 lists the actions necessary to return a switchleg mask RSLMSK at Connector W. The red switchleg mask for the proper bank is selected and the TEMP0 register is set equal to that value. Next the black switchleg mask for the proper bank is selected and TEMP1 is set equal to that value. the value of 30H. Control continuesd at Connector L of FIG. 16. 
     Connector X (FIG. 19) is invoked in order to return the actual switch contacts RSLCON. The original reading for the red switchlegs is pointed to and TEMP0 is set equal to that value. Next, the original reading for the black switchlegs is pointed to and TEMP1 is set equal to that value. Finally, a pointer to TEMP0 is established, the flag is set equal to a value of 34H, and control continues at Connector L of FIG. 16. 
     The return accumulated switch buffers RACUSL procedure is described at Connector Y of FIG. 20. The accumulated switch register for the proper bank is pointed to and the flag is set equal to a value of 3CH with control continuing at Connector L of FIG. 16. 
     A command to acknowledge a secured switchleg transmission is handled at Connector Z of FIG. 20 (ACKSLM). The acknowledgement message contained in data field 0 is pointed to and the proper transmit mask corresponding to the desired bank is pointed to. Data field 0 is then inverted and ANDed with the transmit mask in order to clear the desired positions. This updated transmit mask is then saved. The updated mask is then ANDed with the transmit switch states in order to clear the desired states. This updated transmit switch states is then saved and the process continues at Connector F of FIG. 15. 
     The set switchleg mask procedure is described in FIG. 21 beginning with the Connector ZZ. This process is invoked whenever a change to the current switchleg mask is desired and is responsible for updating the switchleg mask and generating any resultant switchleg transmission that might be caused by a disabled to enabled transition of a switchleg mask. The STATUS register for the TRD is cleared and a pointer to the proper red switch mask for the desired bank is established. The new mask conta1ned 1n data field 0 of the receiver buffer is exclusively ORed with the original switch mask in order to form a change value. This change value is then ANDed with the new mask in order to yield those 0 to 1 (disabled to enabled) changes for the red or ON switch contacts. Next, the original red switch mask is set equal to the new red switch mask contained in data field 0 of the receiver buffer. The black switch mask for the desired bank is then pointed to. The new mask contained in data field 1 of the receiver buffer is then exclusively ORed with the original switch mask in order to form the change information. This information is then ANDed with the new mask in order to yield those 0 to 1 (disabled to enabled) changes for black. The original black switchleg mask is then set equal to the new black switchleg mask value contained in the receiver buffer and a pointer to the original red switch reading for the proper bank is established. By ANDing the original red switch reading with the red 0 to 1 changes the ON part of the transmit switch mask is determined. For momentary type switches control continues at Connector ZB of FIG. 23. Otherwise, for maintained switches control continues at Connector ZA of FIG. 22. 
     For maintained type switches, at FIG. 22 Connector ZA, the set switchleg mask process continues by restoring the original red switch reading. This reading is them complemented in order to have &#34;1&#34; values in OFF positions. This complemented value is then ANDed with the black 0 to 1 changes in order to yield the OFF portion of the transmit switch mask. The new transmit switch mask is then defined to be equal to the ON part ORed with the OFF part of the transmit switch mask with control continuing at Connector ZC (FIG. 22). The new transmit switch state is defined to be equal to the new transmit switch mask ANDed with the original red reading. The new transmit mask is then restored and a test is performed to determine if anything is available for transmission. (If the transmit mask equals to 0 then nothing is available for transmission.) If nothing is available, then the procedure continues at Connector F of FIG. 15. Otherwise, the original transmit switch mask and states are updated with the new values and the output buffer is formed with the required information for new or old and normal or secured type transmissions by the GETSW1 procedure described above. Upon completion of this, the process continues at Connector F of FIG. 15. 
     The required handling for momentary switches is described at Connector ZB of FIG. 23. The original black switchleg reading is pointed to and then ANDed together with the black 0 to 1 changes in order to yield the OFF portion of the transmit switch mask. Any duplicate &#34;Make&#34; conditions are then located by ANDing the OFF and ON parts of the transmit switch mask (any duplicate switch closure will show as a &#34;1&#34; after this process). The resultant value is then complemented so that there will be &#34;1&#34; values in any valid positions. The complemented value is then saved. The complete mask is formed by ORing together the OFF and ON part and then duplicate makes are eliminated by ANDing the duplicate mask with the complemented mask. The result is saved as the new transmit switch mask and control continues at Connector ZC of FIG. 22. 
     The SENDIT routine described in FIG. 24 is responsible for placing data required for transmission into the output buffers and then determining if immediate transmission requirements are needed. If SENDIT performs the actual transmission of a message in an interactive data transmission then it will test the line free requirements in order to clear out previously established receiver thresholds if the line goes free upon successful transmission of the data. 
     SENDIT places the data being pointed to into the proper output buffer using the flag, line free request, and number of bytes to send by invoking the BLDTBF routine. A test is then performed in order to determine if a deferred line free requirement is needed. If so, then the process CLRBNK is invoked, which is described in FIG. 15 at Connector F. Otherwise, if an immediate transmission is required, then a test is performed in order to determine if both banks are being requested. If so, then the immediate transmission of the first bank is postponed and the process continues with the CLRBNK routine. If only one bank of information is to be transmitted, then the line low timeout is set equal to the maximum interblock gap time and the line high timer is set to the minimum. The BITIMP routine is then invoked in order to wait for the final IBG of the interactive transmission message to complete; at which point the transmit process (similar to that disclosed in Miller &#39;414) is invoked in order to transmit out the required data. If at any time during the transmission a collision is detected, then the process will continue as indicated on the diagram. Otherwise, a delay will be invoked in order to allow the line to go from its low impedance state (from the final IBG) to the high impedance state (50 microseconds). The line high timeout is then set equal to the line free threshold value and the process BITIN4 is invoked in order to determine if the line is active. If the line does not go active, then RVSTAT is cleared indicating a line free condition and the process continues as indicated. If the line did go active then the controlling device has reestablished control of the data line. Therefore, the receiver thresholds are not be cleared. The good message counter is incremented and the process continues at the DECOD2, FIG. 12 Connector B. 
     The address check routine ADRCHK is described in FIG. 25. It is responsible for verifying that a message in the receiver buffer is, in fact, addressed to the proper transceiver decoder. In addition, it will verify the correctness of the message by performing a nibble parity check or checksum verification of the message. If both the address and check portions of the message are correct, then three registers will be set to the proper values for the flag, data field 0, and data field 1. 
     The description of ADRCHK begins with FIG. 25. The proper receiver buffer is pointed to for the desired bank along with the A8JUMP register. The head of the buffer is fetched in order to get the flag. A test is then performed to determine if this is a possible new mode message by examining the FA bit (or bit DB1) of the flag to see if it is set. If so, then control continues at Connector G of FIG. 27. Otherwise, address bit A8 of the transceiver decoder is compared with that received. If there is not an A8 match, then continuing the Connector A, the RCVFLG bank and mode indication are cleared from RVSTAT and the address check routine returns. Otherwise, if there is an address A8 match, then a further test is performed to determine if it is a two address TRD. If so, then control continues at Connector E of FIG. 26. If the transceiver decoder is a single address device, then the address field is pointed to and compared with the TRD ADRLOW register by the ADRCHD procedure. If there is not a low address match, then the process aborts through Connector A (FIG. 25). Otherwise, continuing through Connector B (FIG. 25), an old mode bank 0 message is indicated. At Connector C (FIG. 25), the parity word in the receiver buffer is pointed to and saved for later comparison. Next a nibble parity check is performed by the PARITY routine and a test is performed to determine if the received and calculated parity agree. If not, then ADRCHD aborts and clears the receiver flag RCVFLG at at Connector A (FIG. 25). Otherwise, the process continues at Connector D of FIG. 26. 
     Continuing with the description of the ADRCHK process at Connector D of FIG. 26, the valid flag from the receiver buffer is saved and data field 0 in the buffer is pointed to along with DF0 storage by the ADRCHC procedure. At Connector F (FIG. 26), the copy routine is invoked in order to copy the received data (0, 1 or 2 bytes) from the receiver buffer to the DF0 and DF1 storage registers as required. The desired mode bits and bank bits are then set within RVSTAT, which completes the process. 
     Connector E (FIG. 26) is entered whenever an old mode two address TRD is to be verified. The process ADRCHD is invoked in order to point to the address field in the buffer and compare this with the TRD ADRLOW. Data bits DB0 of the result is then masked out. (This least significant bit determines the bank that the message was intended for in a two address TRD. DB0 equals to 0 corresponds to bank 0 and DB0 equals to 1 corresponds to bank 1.) If there is no address match then the process aborts at Connector A of FIG. 25. Otherwise, the old mode type message for bank 1 is indicated. A test is then performed to determine if the message in fact was to bank 1 by testing at DB0 of the received address field. If it was to bank 1, then the process continues at Connector C of FIG. 25. Otherwise, the process continues at Connector B of FIG. 25. 
     Connector G of FIG. 27 is entered whenever there is a possible new mode message. A test is performed on Bit FB (DB0 of the flag word) to determine if it is a 1. If so, then new mode addressing is not being used and the process aborts via Connector A of FIG. 25. Otherwise, a test is performed of the universal address bit U within the high address word. If U is equal to 1, then the process continues at Connector I of FIG. 29. Otherwise, universal addressing is not being used. The high address word is fetched from the buffer and it is compared with address bit A8 of the TRD. If there is not a match, then the process aborts at Connector A (FIG. 25). Otherwise, the low address field is pointed to in the buffer and compared to the ADRLOW storage register by the routine ADRCHD. A test is then performed to determine if the transceiver is a single address type. If so, then a test is made to determine if the low address received and that contained in the ADRLOW register compare. If not, the process aborts at Connector A. Otherwise, it continues as indicated on the diagram. If the device was a two address TRD, then Bit DB0 of the result of the comparison of ADRLOW and the received low address field is masked off. If the remaining address bits do not compare then the process aborts at Connector A. Otherwise, a new mode message for bank 1 is indicated and a test is performed on address bit A0 to see it it&#39;s set to 0 indicating a bank 0 message. If so, then the indication is changed to a new mode bank 0 message. Otherwise, it is left as a new mode bank 1 message and control continues at Connector H of FIG. 28. 
     Continuing with the description of the new mode address checking at Connector H of FIG. 28, the head of the receiver buffer is pointed to. Following this, the number of bytes received is calculated by taking the 1&#39;s complement of the sum of the byte counter register plus the 1&#39;s complement of 7. The number of data fields received is calculated by subtracting 4 from the total number of bytes received. Next the checksum register is initialized to a value of 80H. A byte from the receiver buffer is then summed into the checksum register and the pointer to the receiver buffer is incremented to the next byte. The number of bytes received is decremented and a test is made to determine if there are any additional bytes to sum into the checksum. If so, then the process of summing the bytes incrmented the pointer, and decrementing the byte count continues until all bytes have been summed into the checksum. When all bytes have been checked, then a test is made to determine if the final checksum value is equal to 0. If not, then the process aborts at Connector A of FIG. 25. Otherwise, the head of the buffer is saved as a valid flag, the low address field is pointed to and data field storage register is pointed to by the process ADRCHC. Data field 0 is then pointed to in the receiver buffer by incrementing the buffer pointer and control continues at Connector F of FIG. 26. 
     Whenever it is determined that universal addressing is being used within a new mode, Connector I of FIG. 29 is entered. A test is performed in order to determine if all bits other than the U (or DB7) bit of the high address field is equal to 0. If so, then a Family universal address is being used and control continues at Connector K of FIG. 30. Otherwise, a test is made of the high address field to determine if all of the bits are equal to 1. If not, and an improper address has been received then the routine aborts at Connector A of FIG. 25. Otherwise, the low address field is pointed to and a further test is performed to insure that it also is equal to all 1&#39;s. If not, the process aborts. Otherwise, it continues at Connector J (FIG. 29). A new mode transmission for bank 0 is indicated and a test is performed to determine if the device is a single address TRD. If so, then control continues at Connector H of FIG. 28. Otherwise, the indicator is updated to reflect a new mode transmission for both banks 0 and 1. (A universally addressed message transmitted to a two bank TRD will result in actions being performed on both banks of that transceiver decoder). 
     FIG. 30, connector K, describes the tests required to determine if a family address to a switch transceiver decoder (TRD) is being used. The low address field is pointed to and checked to see if it is equal to &#34;1&#34;. If so, then the process continues at connector J of FIG. 29. Otherwise it continues at connector A of FIG. 25. 
     FIG. 31 describes the two subroutines required by the ADRCHK process. ADRCHC points to the head of the receiver buffer, gets the receive flag word, masks out the two least significant bits FAFB and saves the result as the flag. Next, DRO storage register is pointed to. Finally a value of 2 is added to the receiver buffer pointer such that i will point to data field 0 if an old type message or the low address field if it is a new type message. This completes the subroutine which then returns. ADRCHD is used in order to point to the ADRLOW storage register of the transceiver decoder, point to the low address field by incrementing the receiver buffer pointer and to compare the low address in the buffer with the ADRLOW storage register. This completes the routine which then returns to the invoking procedure. 
     This completes the description of the Decoder Handler Module which provides a means of verifying the address of a message received; a means of distinguishing between one of two banks for a message received; a means of recognizing two formats of messages (old and new); a means of aborting the decode of a message if an invalid format is used; a means of decoding multiple flag words; a means of eliminating the response to old format commands by evaluating the presence or absence of a COMM jumper which can be Manufacturing installed; a means of allowing multiple number of data bytes to be input from the common data line; a means for decoding auxiliary flag commands for various types of devices which may or may not be jumper selectable; a means for indicating immediate or deferred response to requests for data transmission; a means of passing control of the data line from one device to the transceiver decoder in an immediate mode of transmission; a means of determining if the controlling device desires to regain control of the data line upon completion of an immediate transmission of data from the transceiver decoder; a means of deferring an immediate request for data if that request is to both banks simultaneously (as would be the case if a universal address command was used); a means for performing a modified checksum against the received message with an initial value of 80H in order to avoid the proper decoding of a message with all 0 or all 1 values (homogenous message) a means of performing a nibble parity check as required for the old format message; a means for providing the proper setup of the switchleg mask buffer; a means of generating a switchleg actuation message if the enabling of a previously disabled switchleg results in the detection of a switch contact closure; a means of reading the following TRD data registers: the switchleg mask register, the accumulated switchleg buffer, the actual switchleg contact closures, the transceiver status, the receiver threshold register, the data line counter register, and the ROM code version; a means of counting the number of properly decoded messages by incrementing a good message counter; a means of automatically clearing the status register of the transceiver decoder upon reception of a command to reestablish the switchleg mask; and a means of allowing the acknowledgement of secure or answer-back type switches. 
     Powerup Executive and Miscellaneous Modules 
     Switchleg processor 300, on Powerup, begins to execute its internal ROM memory code beginning with Address 0 (which corresponds to the PWRUP routine). The powerup routine is responsible for proper initialization of the microprocessor and associated external hardware and for placing a powerup-reset message into the transmitter output buffer for subsequent transmission over the common data line. 
     The powerup routine for the switchleg transceiver decoder is described in FIG. 32. The external interrupts are disabled since none exist for the switch transceiver decoder and the stack and registers are reset. Following this the watchdog is strobed with 50 watchdog pulses and the RESET procedure is invoked in order to initialize the I/O internal registers and identify the module. A powerup reset is indicated in the TRD status and a 25 second delay is invoked in order to allow the system to reach equilibrium. Following this, the powerup status message is placed into the output buffer. A flag value of 4CH is used. 
     FIG. 33 indicates the reset process used by the switch transceiver decoder. This process in addition to other tasks will input the current switchleg reading and place it into the data structures in such a manner as to avoid transmission of any switch closure that might be in a &#34;Make&#34; position on entry to the reset procedure. On entry to the RESET routine, the address multiplexer and switch strobes are disabled along with the jumper input. All internal RAM is then cleared to a 0 value. MODIDN is invoked in order to establish the address of the transceiver decoder (ADRLOW and A8JUMP) along with the flag indicating the number of the address to which the TRD will respond. The process continues as indicated in the figure. Bank 0 switchleg mask is set to all 1&#39;s in order to enable all switchlegs (this is done for both the black and red switch mask). A test is then made to determine if the device is a single address TRD. If not, then the Bank 1 switch masks will be enabled in a similar fashion. READSL is then invoked in order to read the current switch contact positions. The original switch readings are set equal to the new switch readings obtained by the READSL routine. Following this, RVSTAT is set equal to a line free error condition in order to require resynchronism of the receiver. Timer 0 is initialized and started (this is the 48 millisecond switch reading timer) followed by Timer 1 (this is the answerback or secured switch retransmission timer), completing the reset procedure which then returns to the supervisory function. 
     The executive is the main working procedure of the transceiver decoder. It is entered upon completion of the powerup procedure. Once the executive has been invoked, the only exit from the endless loop of the executive is via a reset (which would occur on powerup). However, it is possible for the activity controlled by the executive to be suspended for a brief interval of time in order to service the internal timer interrupt. It should be noted that the internal timer is set for a 6 millisecond internval and is always active. 
     FIG. 34 describes the EXEC executive routine used by the relay transceiver. The stack is reset and the working set of registers selected. Following this, the watchdog timer is recharged by issuing 10 strobes to the appropriate hardware. At this point, a receiver service is performed in order to input any possible data from the data line by involing the RCVSRV routine (similar to that disclosed in Miller &#39;414). On completion of this task, the DECODE process is invoked in order to decode any received data and to perform the desired actions. Following the decode of data a transmitter service is performed in order to output any possible data to the data line by calling the routine XMTSRV (similar to that disclosed in Miller &#39;414). Next a switchleg service is invoked in order to determine switch actions. Finally, the module is reidentified in order to keep the transceiver address and jumper registers set to the most current position (it is possible to change the jumper or address configuration at any time). On completion Of the MODIDN process, the executive continues to recharge the watchdog timer and invoke the 5  main subroutines until such time that the microprocessor is reset due to a powerup, or watchdog. 
     FIG. 35 describes the module identification routine used by the switch TRD. Since each transceiver decoder has a user selectable address to which it will respond as well as user and manufacturing installed jumpers which configure the method in which the transceiver decoder operates, the module identification routine is necessary in order to input the desired address and jumper configuration for subsequent later action and processing by the TRD. On entry to the MODIDN procedure, a test is performed to determine if the data line is active. If so, then the MODIDN process aborts as indicated. (It would not be desirable to reidentify the module due to the lengthy process involved if the data line was active.) If, on the other hand, no current data line activity was indicated, then the jumper hardware would be enabled for input and the A8JUMP register would be set to the value obtained by inputting the jumper configuration. The jumper input hardware is then disabled in order to reduce power consumption and a flag is set indicating a one or two address TRD based on the configuration of the size jumper. A temporary register is then established and cleared and an indication is made to input 8 bits of address data. Beginning with the loop on FIG. 35, the temporary register is rotated one bit position to the left in order to position its contents for the next address bit to be input. Following this an output word is fetched from a table of values based on the current bit number. The address multiplexer hardware is then enabled and a single bit of address data is input. This address bit is isolated and &#34;ORed&#34; with the bits in the temporary register. The updated temporary is then saved and a test is performed to determine if all bits have been input. This procedure of rotating the temporary, selecting an output word to enable the proper address multiplexer, inputting the bit and merging it with a temporary continues until such time that all bits have been input. Once all addres bits are in, a test is made to determine if the device is a single address TRD. If not, then bit DB0 of the temporary is cleared. (A two address device will respond to two addresses. The even address, i.e., when DB0 equals 0 corresponds to Bank 0; the odd address when DB1 equals 1 corresponds to Bank 1.) On the other hand, if the device was a single address TRD, then DB0 would not be altered and the resulting address could be either even or odd. ADRLOW is then set equal to the 8 least significant address bits contained in the temporary and then the address multiplex hardware is turned off. This completes the module identification process which then returns to the invoking utility. 
     As discussed above, the transceiver decoder has a continuously running internal 6 millisecond timer which is used to sequence desired actions. This timer is an internal programmable device which generates a timer interrupt whenever a programmed register has been incremented to a 0 value. This timer runs continuously and is disabled only when being serviced or updated. 
     FIG. 36 describes the timer interrupt service routine TIMINT. The purpose of this routine is to service a timer interrupt which occurs every 6 milliseconds and to increment by 1 an elapsed timer counter. On detection of a timer interrupt, the timer is stopped and the timer registers are selected (this is Register Set 1 of the 8049 microprocessor, constituting the presently preferred embodiment of switch processor 300). The current accumulator value is saved in order to free the accumulator for other usages and the six (6) millisecond timer value is fetched. Following this, the timer is initialized for the next 5 millisecond interrupt and the accumulator is restored to its value on entry to the TIMINT procedure. The elapsed timer counter is then incremented by 1 and the internal hardware timer flag is cleared in case it remains set. Upon exit from the timer interrupt service procedure, the currently active working register bank is stored (this is the standard register bank or register bank 0). 
     The elapsed timer is continuously updated by the 6 millisecond timer interrupts. Two additional timers can be driven off of this elapsed time counter in such a way that they may be maintained current by summing in the elapsed time counts. This is the responsibility of the TIMSRV procedure described in FIG. 37. On entry to the TIMSRV process the timer interrupt is disabled and the bank of timer registers are selected. Timer 0 is then set equal to the initial value of timer 0 plus the elapsed timer counter. Timer 1 is then set equal to the initial value of timer 1 plus the elapsed timer counter. The elapsed timer counter is then cleared and a test is made of the internal hardware timer flag to determine if it was set. If so, an immediate branch is taken to the TIMINT procedure (the internal timer flag would be set if a timer interrupt occurred coincidentially with the entry to the TIMSRV process). If the timer interrupt flag was not set, then the working register bank would be restored and the procedure would complete and return to the invoking process. It should be noted that the TIMSRV process is asynchronous of the timer interrupts and could be entered at any time. A maximum delay of up 256 of the 6 millisecond timer counts could expire before losing accuracy in the timer 0 counter and timer counter. 
     A process exists, described in FIG. 38, called CLRST0 for initializing and starting the timer 0 counter. The timer bank of registers is selected and the counts needed for the 6 millisecond interrupt duration are initialized. Following this, the timer is started by calling the TIMINT process. Next the elapsed timer and timer 0 are both cleared and set equal to 0. Finally, the timer interrupt is enabled and on exit from the routine the working bank of registers is restored. 
     FIG. 38 also indicates an additional routine present in the switch TRD called CLRSTl or Clear and Start Timer 1. The timer bank of registers is selected and timer 1 counter is set equal to 0. On exit from the CLRSTl process, the original bank of working registers is restored. (In the switch transceiver timer 0 is utilized as the 48 millisecond switch reading internval timers while timer 1 is utilized as the 1 second answer-back acknowledge timer as described in the switchleg handler module.) 
     The Powerup routine provides for the following: a means of generating a Powerup/Status message for subsequent transmission to a monitoring or controlling device; a means of invoking a reset procedure to initialize I/O devices and internal registers; a means of initializing the watchdog reset hardware; a means of initializing the machine to a known internal state. 
     The executive provides for: a means of periodically strobing a watchdog timer in order to indicate normal operation; a means of resetting the stack and working register bank in order to counteract any possible incorrect action due to spurious signals which may have altered the machine state; and a means of providing the functionality of the transceiver decoder by executing an executive loop of the desired functions forever. 
     The reset process provides for: a means of initializing I/O to a known condition; a means of initializing all desired memory registers to 0; a means of causing the receiver to resynchronize on a maximum line free timeout; a means of clearing the good and bad message counter to 0 values; a means of clearing the accumulated switchleg buffer; a means of reading any current swtich contact closures and establishing internal registers in such a way that any switches that are in the &#34;make&#34; condition will not cause subsequent transmission over the data line due to the reset procedure being invoked; a means of enabling all switchleg mask positions; a means of starting and clearing the proper timer counters; and a means of halting any current actions that might be pending in the transceiver decoder (such as messages awaiting decoding in the receiver buffer). 
     The timer routines provide for: a means of establishing a periodic 6 millisecond internval timer; a means for counting the timer interrupts and retaining a sum of the number of times the interrupt has occurred in an 8 bit elapsed timer counter; a means of providing one or more counters to which the elapsed time counter is added in order to provide for long intervals to be timed; a means of clearing to 0 and restarting one or more timer counters; and a means of deferring until a convenient time the servicing of the elapsed time counter. 
     The module identifier provides for: a means of inputting a set of 8 user or manufacturing installed jumpers to dynamically or statically configure the transceiver decoder; a means of operating a multiplexer circuit in order to allow the inputting of 8 user selectable address lines; a means of identifying via a flag a one or two address transceiver decoder; a means of disabling the jumper input hardware in order to reduce power consumption; a means of detecting and avoiding a conflict with the operation of the address multiplexer circuit and other external hardware; and a means of allowing the address inputs or mode selector jumpers to be dynamically varied by the user and detected and acted upon the transceiver decoder. 
     While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures. 
     
         ______________________________________ENHANCED TRD SWITCH MODULE ROM CODE - VERI.E - GEC PROPRIETARYALL DATA VALUES ARE IN HEXADECIMAL FORMATADDRESS   DATA         ADDRESS   DATA______________________________________.0..0..0..0.     15           .0..0..0.1                            27.0..0..0.2     D7           .0..0..0.3                            BC.0..0..0.4     32           .0..0..0.5                            E4.0..0..0.6     .0.C         .0..0..0.7                            D5.0..0..0.8     65           .0..0..0.9                            2F.0..0..0.A     62           .0..0..0.B                            55.0..0..0.C     2F           .0..0..0.D                            1E.0..0..0.E     16           .0..0..0.F                            1.0..0..0.1.0.     93           .0..0.11  35.0..0.12  D5           .0..0.13  FD.0..0.14  6E           .0..0.15  AD.0..0.16  FC           .0..0.17  6E.0..0.18  AC           .0..0.19  BE.0..0.1A  .0..0.       .0..0.1B  25.0..0.1C  16           .0..0.1D  .0.7.0..0.1E  93           .0..0.1F  F4.0..0.2.0.     E6           .0..0.21  F1.0..0.22  D2           .0..0.23  8C.0..0.24  FB           .0..0.25  53.0..0.26  8F           .0..0.27  A1.0..0.28  B9           .0..0.29  59.0..0.2A  B6           .0..0.2B  2E.0..0.2C  B9           .0..0.2D  61.0..0.2E  FA           .0..0.2F  12.0..0.3.0.     32           .0..0.31  19.0..0.32  FB           .0..0.33  47.0..0.34  53           .0..0.35  .0.7.0..0.36  AD           .0..0.37  14.0..0.38  D7           .0..0.39  B9.0..0.3A  57           .0..0.3B  B6.0..0.3C  3F           .0..0.3D  B9.0..0.3E  5F           .0..0.3F  B8.0..0.40  51           .0..0.41  FA.0..0.42  12           .0..0.43  48.0..0.44  23           .0..0.45  .0.2.0..0.46  .0.4         .0..0.47  4B.0..0.48  F.0.         .0..0.49  53.0..0.4A  .0.1         .0..0.4B  AF.0..0.4C  FA           .0..0.4D  53.0..0.4E  FC           .0..0.4F  4F.0..0.5.0.     A1           .0..0.51  19.0..0.52  FA           .0. .0.53 12.0..0.54  5A           .0..0.55  F.0..0..0.56  53           .0..0.57  .0.1.0..0.58  A1           .0..0.59  19.0..0.5A  C8           .0..0.5B  B6.0..0.5C  62           .0..0.5D  F.0..0..0.5E  43           .0..0.5F  .0.1.0..0.6.0.     .0.4         .0..0.61  63.0..0.62  F.0.         .0..0.63  A1.0..0.64  FA           .0..0.65  12.0..0.66  6C           .0..0.67  FD.0..0.68  69           .0..0.69  17.0..0.6A  .0.4         .0..0.6B  6F.0..0.6C  F9           .0..0.6D  .0.3.0..0.6E  .0.3         .0..0.6F  A8.0..0.7.0.     A9           .0..0.71  FA.0..0.72  12           .0..0.73  8D.0..0.74  FD           .0..0.75  .0.3.0..0.76  .0.3         .0..0.77  AE.0..0.78  23           .0..0.79  8.0..0..0.7A  C8           .0..0.7B  6.0..0..0.7C  EE           .0..0.7D  7A.0..0.7E  37           .0..0.7F  17.0..0.8.0.     A1           .0. .0.81 F8.0..0.82  37           .0..0.83  17.0..0.84  69           .0..0.85  17.0..0.86  B8           .0..0.87  52.0..0.88  B6           .0..0.89  8B.0..0.8A  18           .0..0.8B  A.0..0..0.8C  83           .0..0.8D  14.0..0.8E  92           .0..0.8F  FF.0..0.9.0.     .0.4         .0..0.91  8.0..0..0.92  BF           .0..0.93  .0..0..0..0.94  BE           .0..0.95  .0.4.0..0.96  C8           .0..0.97  F.0..0..0.98  47           .0..0.99  14.0..0.9A  A1           .0..0.9B  F.0..0..0.9C  14           .0..0.9D  A1.0..0.9E  EE           .0..0.9F  96.0..0.A.0.     83           .0..0.A1  53.0..0.A2  .0.F         .0..0.A3  .0.3.0..0.A4  AB           .0..0.A5  A3.0..0.A6  2F           .0..0.A7  E7.0..0.A8  4F           .0..0.A9  2F.0..0.AA  83           .0..0.AB  .0..0..0..0.AC  .0.1         .0..0.AD  .0.1.0..0.AE  .0..0.       .0..0.AF  .0.1.0..0.B.0.     .0..0.       .0..0.B1  .0..0..0..0.B2  .0.1         .0..0.B3  .0.1.0..0.B4  .0..0.       .0..0.B5  .0..0..0..0.B6  .0.1         .0..0.B7  .0..0..0..0.B8  .0.1         .0..0.B9  .0.1.0..0.BA  .0..0.       .0..0.BB  F.0..0..0.BC  C6           .0..0.BD  C8.0..0.BE  37           .0..0.BF  17.0..0.C.0.     6A           .0..0.C1  A.0..0..0.C2  18           .0..0.C3  F.0..0..0.C4  37           .0..0.C5  7B.0..0.C6  A.0.         .0..0.C7  83.0..0.C8  6A           .0..0.C9  A7.0..0.CA  .0.4         .0..0.CB  C1.0..0.CC  97           .0..0.CD  F.0..0..0.CE  67           .0..0.CF  AB.0..0.D.0.     A.0.         .0..0.D1  C8.0..0.D2  F.0.         .0..0.D3  67.0..0.D4  AA           .0..0.D5  A.0..0..0.D6  83           .0..0.D7  C6.0..0.D8  E.0.         .0..0.D9  AC.0..0.DA  F.0.         .0..0.DB  A1.0..0.DC  18           .0..0.DD  19.0..0.DE  EC           .0..0.DF  DA.0..0.E.0.     83           .0..0.E1  B8.0..0.E2  4B           .0..0.E3  .0.4.0..0.E4  E7           .0..0.E5  B8.0..0.E6  49           .0..0.E7  F.0..0..0.E8  .0.3         .0..0.E9  .0.1.0..0.EA  A.0.         .0..0.EB  18.0..0.EC  F.0.         .0..0.ED  13.0..0.EE  .0..0.       .0..0.EF  A.0..0..0.F.0.     83           .0..0.F1  BA.0..0.F2  4D           .0..0.F3  BB.0..0.F4  .0.2         .0..0.F5  BC.0..0.F6  .0.A         .0..0.F7  BD.0..0.F8  .0.2         .0..0.F9  44.0..0.FA  BB           .0.1.0..0.                            B8.0.1.0.1  43           .0.1.0.2  B9.0.1.0.3  51           .0.1.0.4  F.0..0.1.0.5  32           .0.1.0.6  38.0.1.0.7  D1           .0.1.0.8  12.0.1.0.9  29           .0.1.0.A  F1.0.1.0.B  72           .0.1.0.C  2B.0.1.0.D  37           .0.1.0.E  52.0.1.0.F  29           .0.11.0.  34.0.111    9E           .0.112    96.0.113    29           .0.114    BB.0.115    6.0.         .0.116    B8.0.117    47           .0.118    F.0..0.119    AD           .0.11A    14.0.11B    92           .0.11C    FD.0.11D    DF           .0.11E    96.0.11F    29           .0.12.0.  34.0.121    92           .0.122    23.0.123    .0.2         .0.124    14.0.125    D7           .0.126    FB.0.127    44           .0.128    A3.0.129    C4           .0.12A    2D.0.12B    34           .0.12C    9E.0.12D    53           .0.12E    FE.0.12F    96           .0.13.0.  29.0.131    BB           .0.132    A.0..0.133    F.0.         .0.134    12.0.135    16           .0.136    24.0.137    14           .0.138    12.0.139    29           .0.13A    18.0.13B    F.0.         .0.13C    F2.0.13D    6F           .0.13E    F1.0.13F    D.0.         .0.14.0.  12.0.141    29           .0.142    34.0.143    9E           .0.144    76.0.145    6B           .0.146    53.0.147    FE           .0.148    96.0. 149   29           .0.14A    BB.0.14B    8.0.         .0.14C    F.0..0.14D    12           .0.14E    51.0.14F    BB           .0.15.0.  4.0..0.151    B8           .0.152    43.0.153    23           .0.154    F8.0.155    6E           .0.156    37.0.157    AE           .0.158    .0.3.0.159    FC           .0.15A    E6.0.15B    29           .0.15C    AA.0.15D    23           .0.15E    8.0..0.15F    6.0.         .0.16.0.  18.0.161    EE           .0.162    5F.0.163    96           .0.164    29.0.165    34           .0.166    92.0.167    18           .0.168    FA.0.169    24           .0.16A    24.0.16B    96           .0.16C    29.0.16D    24           .0.16E    4F.0.16F    53           .0.17.0.  7E.0.171    C6           .0.172    84.0.173    F.0.         .0.174    17.0.175    96           .0.176    29.0.177    18           .0.178    F.0..0.179    17           .0.17A    96.0.17B    29           .0.17C    BB.0.17D    4.0.         .0.17E    76.0.17F    51           .0.18.0.  BB.0.181    C.0.         .0.182    24.0.183    51           .0.184    18.0.185    F1           .0.186    92.0.187    8E           .0.188    F.0..0.189    .0.7         .0.18A    96.0.18B    29           .0.18C    24.0.18D    7C           .0.18E    F.0..0.18F    .0.7         .0.19.0.  24.0.191    89           .0.192    B8.0.193    43           .0.194    B9.0.195    4D           .0.196    F.0..0.197    53           .0.198    FC.0.199    A1           .0.19A    18.0.19B    18           .0.19C    19.0.19D    83           .0.19E    C9.0.19F    18           .0.1A.0.  F.0..0.1A1    D1           .0.1A2    83.0.1A3    B8           .0.1A4    3C.0.1A5    F.0.         .0.1A6    96.0.1A7    D.0.         .0.1A8    91.0.1A9    8A           .0.1AA    FF.0.1AB    .0.A         .0.1AC    B8.0.1AD    51           .0.1AE    A.0..0.1AF    9A           .0.1B.0.  A.0..0.1B1    A5           .0.1B2    72.0.1B3    B5           .0.1B4    B5.0.1B5    BF           .0.1B6    .0..0..0.1B7    BE           .0.1B8    .0.8.0.1B9    FF           .0.1BA    E7.0.1BB    AF           .0.1BC    23.0.1BD    D.0.         .0.1BE    6E.0.1BF    A3           .0.1C.0.  39.0.1C1    .0.9         .0.1C2    53.0.1C3    1.0.         .0.1C4    4F.0.1C5    AF           .0.1C6    EE.0.1C7    B9           .0.1C8    76.0.1C9    CC           .0.1CA    53.0.1CB    FE           .0.1CC    C8.0.1CD    A.0.         .0.1CE    89.0.1CF    FF           .0.1D.0.  83.0.1D1    F.0.         .0.1D2    F4.0.1D3    F2           .0.1D4    F6.0.1D5    D1           .0.1D6    D5.0.1D7    D3           .0.1D8    D7.0.1D9    EF           .0.1DA    D9.0.1DB    EE           .0.1DC    D9.0.1DD    83           .0.1DE    23.0.1DF    FF           .0.1E.0.  39.0.1E1    91           .0.1E2    23.0.1E3    A.0.         .0.1E4    3A.0.1E5    B8           .0.1E6    2.0..0.1E7    BC           .0.1E8    4A.0.1E9    B4           .0.1EA    98.0.1EB    34           .0.1EC    A3.0.1ED    B8           .0.1EE    51.0.1EF    F.0.         .0.1F.0.  B9.0.1F1    3C           .0.1F2    B1.0.1F3    4.0.         .0.1F4    E4.0.1F5    A5           .0.1FA    8A.0.1FB    A.0.         .0.1FC    BB.0.1FD    .0.F         .0.1FE    EB.0.1FF    FE           .0.2.0..0.                            56.0.2.0.1  .0.A         .0.2.0.2  EE.0.2.0.3  .0..0.       .0.2.0.4  9A.0.2.0.5  2.0.         .0.2.0.6  EF.0.2.0.7  .0.4         .0.2.0.8  97.0.2.0.9  83           .0.2.0.A  BB.0.2.0.B  .0.3         .0.2.0.C  46.0.2.0.D  .0..0.       .0.2.0.E  EB.0.2.0.F  .0.C         .0.21.0.  97.0.211    A7           .0.212    83.0.213    BE           .0.214    .0.4.0.215    BF           .0.216    3F.0.217    34           .0.218    D9.0.219    8A           .0.21A    A.0..0.21B    83           .0.21C    B8.0.21D    3C           .0.21E    F.0..0.21F    12           .0.22.0.  2D.0.221    46           .0.222    2C.0.223    B9           .0.224    .0.3.0.225    46           .0.226    2C.0.227    E9           .0.228    25.0.229    43           .0.22A    .0.1.0.22B    A.0.         .0.22C    83.0.22D    32           .0.22E    43.0.22F    52           .0.23.0.  33.0.231    44           .0.232    51.0.233    72           .0.234    41.0.235    54           .0.236    AE.0.237    E6           .0.238    2C.0.239    32           .0.23A    3F.0.23B    23           .0.23C    .0.8.0.23D    44           .0.23E    A3.0.23F    54           .0.24.0.  A8.0.241    44           .0.242    EC.0.243    8A           .0.244    A.0..0.245    56           .0.246    2C.0.247    BC           .0.248    14.0.249    BD           .0.24A    .0.3.0.24B    54           .0.24C    D3.0.24D    E6           .0.24E    2C.0.24F    44           .0.25.0.  A8.0.251    BC           .0.252    .0.C.0.253    B8           .0.254    3D.0.255    B4           .0.256    98.0.257    BA           .0.258    C8.0.259    BB           .0.25A    2.0..0.25B    14           .0.25C    F5.0.25D    F6           .0.25E    A1.0.25F    BE           .0.26.0.  .0.4.0.261    14           .0.262    F1.0.263    F6           .0.264    A1.0.265    B8           .0.266    3D.0.267    F.0.         .0.268    6A.0.269    A.0.         .0.26A    18.0.26B    F.0.         .0.26C    7B.0.26D    A.0.         .0.26E    18.0.26F    F.0.         .0.27.0.  6C.0.271    A.0.         .0.272    18.0.273    F.0.         .0.274    7D.0.275    A.0.         .0.276    EE.0.277    61           .0.278    B8.0.279    3D           .0.27A    BA.0.27B    4A           .0.27C    BB.0.27D    .0.9         .0.27E    14.0.27F    BB           .0.28.0.  14.0.281    CC           .0.282    B8.0.283    3F           .0.284    BA.0.285    28           .0.286    BB.0.287    .0.8         .0.288    14.0.289    BB           .0.28A    14.0.28B    CC           .0.28C    B8.0.28D    41           .0.28E    FA.0.28F    A.0.         .0.29.0.  18.0.291    FB           .0.292    A.0..0.293    14           .0.294    CC.0.295    18           .0.296    1.0..0.297    B8           .0.298    3E.0.299    1.0.         .0.29A    B8.0.29B    4.0.         .0.29C    1.0..0.29D    23           .0.29E    .0.4.0.29F    44           .0.2A.0.  A3.0.2A1    23           .0.2A2    .0.2.0.2A3    B8           .0.2A4    3C.0.2A5    4.0.         .0.2A6    A.0..0.2A7    83           .0.2A8    27.0.2A9    B8           .0.2AA    3C.0.2AB    5.0.         .0.2AC    A.0..0.2AD    83           .0.2AE    B8.0.2AF    3D           .0.2B.0.  F.0..0.2B1    AA           .0.2B2    18.0.2B3    F.0.         .0.2B4    AB.0.2B5    18           .0.2B6    F.0..0.2B7    AC           .0.2B8    18.0.2B9    F.0.         .0.2BA    AD.0.2BB    FA           .0.2BC    C6.0.2BD    C2           .0.2BE    46.0.2BF    C9           .0.2C.0.  EA.0.2C1    BE           .0.2C2    EB.0.2C3    BE           .0.2C4    23.0.2C5    .0.1         .0.2C6    97.0.2C7    A7           .0.2C8    83.0.2C9    B8           .0.2CA    .0.C.0.2CB    56           .0.2CC    BE.0.2CD    E8           .0.2CE    CB.0.2CF    FA           .0.2D.0.  96.0.2D1    D3           .0.2D2    1B.0.2D3    FC           .0.2D4    C6.0.2D5    DA           .0.2D6    56.0.2D7    E.0.         .0.2D8    EC.0.2D9    D6           .0.2DA    ED.0.2DB    D6           .0.2DC    23.0.2DD    .0.2         .0.2DE    44.0.2DF    C6           .0.2E.0.  B8.0.2E1    .0.3         .0.2E2    46.0.2E3    D6           .0.2E4    E8.0.2E5    E2           .0.2E6    FC.0.2E7    96           .0.2E8    EA.0.2E9    1D           .0.2EA    97.0.2EB    83           .0.2EC    B9.0.2ED    43           .0.2EE    BE.0.2EF    .0.6         .0.2F.0.  BF.0.2F1    8.0.         .0.2F2    BA.0.2F3    C8           .0.2F4    BB.0.2F5    2.0.         .0.2F6    B8.0.2F7    3F           .0.2F8    F.0..0.2F9    AC           .0.2FA    18.0.2FB    F.0.         .0.2FC    AD.0.2FD    54           .0.2FE    BB.0.2FF    E6           .0.3.0..0.                            .0.7.0.3.0.1  64           .0.3.0.2  3F.0.3.0.3  54           .0.3.0.4  AE.0.3.0.5  F6           .0.3.0.6  3B.0.3.0.7  B8           .0.3.0.8  41.0.3.0.9  FC           .0.3.0.A  C6.0.3.0.B  28           .0.3.0.C  37.0.3.0.D  17           .0.3.0.E  6.0..0.3.0.F  18           .0.31.0.  FD.0.311    37           .0.312    7.0..0.313    FF           .0.314    67.0.315    AF           .0.316    E6.0.317    .0.3         .0.318    A1.0.319    19           .0.31A    BF.0.31B    8.0.         .0.31C    54.0.31D    AE           .0.31E    F6.0.31F    2C           .0.32.0.  EE.0.321    .0.7         .0.322    23.0.323    F7           .0.324    54.0.325    A9           .0.326    .0.4.0.327    E1           .0.328    6.0..0.329    A7           .0.32A    64.0.32B    .0.F         .0.32C    12.0.32D    32           .0.32E    14.0.32F    E1           .0.33.0.  44.0.331    A8           .0.332    23.0.333    FC           .0.334    6E.0.335    F6           .0.336    26.0.337    23           .0.338    1.0..0.339    44           .0.33A    A3.0.33B    32           .0.33C    2E.0.33D    .0.4         .0.33E    E1.0.33F    32           .0.34.0.  3.0..0.341    23           .0.342    .0.2.0.343    54           .0.344    A3.0.345    .0.4         .0.346    E1.0.347    B8           .0.348    54.0.349    B9           .0.34A    3C.0.34B    F1           .0.34C    C6.0.34D    54           .0.34E    B.0..0.34F    .0..0.       .0.35.0.  23.0.351    .0.1         .0.352    44.0.353    A3           .0.354    74.0.355    AD           .0.356    96.0.357    92           .0.358    F.0..0.359    52           .0.35A    BA.0.35B    32           .0.35C    7F.0.35D    12           .0.35E    77.0.35F    B8           .0.36.0.  .0.4.0.361    B9           .0.362    4.0..0.363    27           .0.364    21.0.365    AD           .0.366    C6.0.367    69           .0.368    CD.0.369    C9           .0.36A    27.0.36B    21           .0.36C    AC.0.36D    BA           .0.36E    CA.0.36F    BB           .0.37.0.  .0.8.0.371    14           .0.372    BB.0.373    BA           .0.374    .0.1.0.375    64           .0.376    85.0.377    BC           .0.378    F4.0.379    BD           .0.37A    .0.2.0.37B    BA           .0.37C    .0.3.0.37D    64           .0.37E    85.0.37F    BC           .0.38.0.  3F.0.381    BD           .0.382    .0.4.0.383    BA           .0.384    .0.7.0.385    54           .0.386    D3.0.387    E6           .0.388    4E.0.389    B8           .0.38A    54.0.38B    F.0.         .0.38C    4A.0.38D    A.0.         .0.38E    74.0.38F    AD           .0.39.0.  C6.0.391    BA           .0.392    9A.0.393    2.0.         .0.394    F4.0.395    E6           .0.396    74.0.397    DE           .0.398    F6.0.399    A1           .0.39A    B8.0.39B    54           .0.39C    27.0.39D    A.0.         .0.39E    A1.0.39F    44           .0.3A.0.  13.0.3A1    B8           .0.3A2    54.0.3A3    F1           .0.3A4    F2.0.3A5    A8           .0.3A6    64.0.3A7    4E           .0.3A8    43.0.3A9    .0. 1        .0.3AA    A1.0.3AB    64           .0.3AC    4E.0.3AD    F.0.         .0.3AE    B9.0.3AF    56           .0.3B.0.  85.0.3B1    76           .0.3B2    B6.0.3B3    51           .0.3B4    96.0.3B5    BB           .0.3B6    95.0.3B7    C9           .0.3B8    F.0..0.3B9    51           .0.3BA    83.0.3BB    12           .0.3BC    BA.0.3BD    C9           .0.3BE    F1.0.3BF    19           .0.3C.0.  12.0.3C1    B6           .0.3C2    F1.0.3C3    32           .0.3C4    BA.0.3C5    C9           .0.3C6    F1.0.3C7    19           .0.3C8    32.0.3C9    B6           .0.3CA    F1.0.3CB    83           .0.3DE    BD.0.3DF    .0.7         .0.3E.0.  BE.0.3E1    .0.8         .0.3E2    BF.0.3E3    CA           .0.3E4    34.0.3E5    D9           .0.3E6    BE.0.3E7    29           .0.3E8    BF.0.3E9    29           .0.3EA    34.0.3EB    FA           .0.3EC    F6.0.3ED    BA           .0.3EE    ED.0.3EF    E6           .0.3F.0.  BE.0.3F1    .0.4         .0.3F2    BF.0.3F3    3F           .0.3F4    34.0.3F5    D9           .0.3F6    B8.0.3F7    52           .0.3F8    B6.0.3F9    FB           .0.3FA    18.0. 3FB   F.0.         .0.3FC    AD.0.3FD    B8           .0.3FE    57.0.3FF    B6           .0.4.0..0.                            .0.3.0.4.0.1  B8           .0.4.0.2  5F.0.4.0.3  BC           .0.4.0.4  .0.8.0.4.0.5  F.0.         .0.4.0.6  AA.0.4.0.7  FA           .0.4.0.8  77.0.4.0.9  AA           .0.4.0.A  F2.0.4.0.B  12           .0.4.0.C  BE.0.4.0.D  1B           .0.4.0.E  BF.0.4.0.F  29           .0.41.0.  84.0.411    16           .0.412    BE.0.413    37           .0.414    BF.0.415    29           .0.416    34.0.417    FA           .0.418    F6.0.419    2.0.         .0.41A    EC.0.41B    .0.7         .0.41C    18.0.41D    ED           .0.41E    .0.3.0.41F    97           .0.42.0.  83.0.421    D5           .0.422    BF.0.423    83           .0.424    14.0.425    .0.7         .0.426    BD.0.427    .0..0.       .0.428    BE.0.429    .0..0.       .0.42A    25.0.42B    93           .0.42C    D5.0.42D    BC           .0.42E    .0..0..0.42F    93           .0.43.0.  .0.1.0.431    .0.2         .0.432    .0.4.0.433    .0.8         .0.434    1.0..0.435    2.0.         .0.436    4.0..0.437    8.0.         .0.438    72.0.439    3C           .0.43A    84.0.43B    3D           .0.43C    18.0.43D    53           .0.43E    .0.7.0.43F    .0.3         .0.44.0.  3.0..0.441    A3           .0.442    83.0.443    94           .0.444    38.0.445    4.0.         .0.446    A.0..0.447    83           .0.448    94.0.449    38           .0.44A    37.0.44B    5.0.         .0.44C    A.0..0.44D    83           .0.44E    B8.0.44F    51           .0.45.0.  F.0..0.451    92           .0.452    A7.0.453    D2           .0.454    7D.0.455    14           .0.456    11.0.457    B9           .0.458    1C.0.459    23           .0.45A    59.0.45B    61           .0.45C    E6.0.45D    7F           .0.45E    85.0.45F    76           .0.46.0.  68.0.461    B8           .0.462    38.0.463    F.0.         .0.464    C6.0.465    68           .0.466    94.0.467    E8           .0.468    95.0.469    B8           .0.46A    30.0.46B    F.0.         .0.46C    C6.0.46D    7.0.         .0.46E    94.0.46F    E8           .0.47.0.  35.0.471    14           .0.472    .0.7.0.473    25           .0.474    B8.0.475    1C           .0.476    B.0..0.477    .0..0.       .0.478    B8.0.479    1E           .0.47A    B.0..0.47B    .0..0.       .0.47C    83.0.47D    14           .0.47E    11.0.47F    B9           .0.48.0.  1D.0.481    23           .0.482    F8.0.483    61           .0.484    E6.0.485    A7           .0.486    B4.0.487    .0.5         .0.488    85.0.489    94           .0.48A    A8.0.48B    76           .0.48C    93.0.48D    B9           .0.48E    34.0.48F    B8           .0.49.0.  28.0.491    94           .0.492    BF.0.493    95           .0.494    94.0.495    A8           .0.496    B9.0.497    2C           .0.498    B8.0.499    24           .0.49A    94.0.49B    BF           .0.49C    35.0.49D    14           .0.49E    .0.7.0.49F    25           .0.4A.0.  B8.0.4A1    1D           .0.4A2    B.0..0.4A3    .0..0.       .0.4A4    18.0.4A5    B.0.         .0.4A6    .0..0..0.4A7    83           .0.4A8    B8.0.4A9    51           .0. 4AA   F.0..0.4AB    97           .0.4AC    32.0.4AD    AF           .0.4AE    A7.0.4AF    83           .0.4B.0.  F1.0.4B1    5.0.         .0.4B2    AA.0.4B3    F.0.         .0.4B4    37.0.4B5    18           .0.4B6    5.0..0.4B7    4A           .0.4B8    AA.0.4B9    D1           .0.4BA    2A.0.4BB    A1           .0.4BC    2A.0.4BD    19           .0.4BE    83.0.4BF    94           .0.4C.0.  B.0..0.4C1    F6           .0.4C2    F.0..0.4C3    AB           .0.4C4    5A.0.4C5    51           .0.4C6    AC.0.4C7    19           .0.4C8    19.0.4C9    FA           .0.4CA    37.0.4CB    5B           .0.4CC    51.0.4CD    4C           .0.4CE    AB.0.4CF    5A           .0.4D.0.  AA.0.4D1    FB           .0.4D2    96.0.4D3    D5           .0.4D4    83.0.4D5    B4           .0.4D6    26.0.4D7    B4           .0.4D8    46.0.4D9    B9           .0.4DA    51.0.4DB    F1           .0.4DC    37.0.4DD    D2           .0.4DE    E8.0.4DF    52           .0.4E.0.  EC.0.4E1    BA           .0.4E2    C5.0.4E3    BB           .0.4E4    AA.0.4E5    14           .0.4E6    1F.0.4E7    83           .0.4E8    BA.0.4E9    4.0.         .0.4EA    84.0.4EB    E3           .0.4EC    BA.0.4ED    44           .0.4EE    84.0.4EF    E3           .0.4F.0.  5A.0.4F1    51           .0.4F2    AB.0.4F3    FA           .0.4F4    AC.0.4F5    18           .0.4F6    19.0.4F7    94           .0.4F8    B.0..0.4F9    5A           .0.4FA    51.0.4FB    4B           .0.4FC    AB.0.4FD    FA           .0.4FE    5C.0.4FF    37           .0.5.0..0.                            5B.0.5.0.1  AB           .0.5.0.2  5C.0.5.0.3  84           .0.5.0.4  D.0..0.5.0.5  B8           .0.5.0.6  24.0.5.0.7  BE           .0.5.0.8  .0.4.0.5.0.9  91           .0.5.0.A  FE.0.5.0.B  .0.3         .0.5.0.C  21.0.5.0.D  A3           .0.5.0.E  39.0.5.0.F  BC           .0.51.0.  .0.9.0.511    B.0.         .0.512    .0..0..0.513    .0.8         .0.514    AF.0.515    .0.8         .0.516    DF.0.517    4.0.         .0.518    A.0..0.519    EC           .0.51A    15.0.51B    18           .0.51C    FF.0.51D    A.0.         .0.51E    18.0.51F    EE           .0.520    .0. A.0.521    83           .0.522    2F.0.523    1F           .0.524    8F.0.525    4F           .0.526    B4.0.527    46           .0.528    B9.0.529    51           .0.52A    F1.0.52B    37           .0.52C    D2.0.52D    42           .0.52E    F4.0.52F    E6           .0.53.0.  F2.0.531    42           .0.532    FB.0.533    A.0.         .0.534    18.0.535    FA           .0.536    A.0..0.537    18           .0.538    F.0..0.539    4B           .0.53A    A.0..0.53B    18           .0.53C    FB.0.53D    37           .0.53E    5.0..0.53F    4A           .0.54.0.  A.0..0.541    83           .0.542    B4.0.543    38           .0.544    A4.0.545    37           .0.546    B8.0.547    3.0.         .0.548    B6.0.549    4C           .0.54A    B8.0.54B    38           .0.54C    83.0.54D    B8           .0.54E    67.0.54F    B.0.         .0.55.0.  9E.0.551    BA           .0.552    5C.0.553    23           .0.554    1.0..0.555    C4           .0.556    DD.0.557    BA           .0.558    2C.0.559    B4           .0.55A    DB.0.55B    C4           .0.55C    D3.0.55D    F4           .0.55E    E6.0. 55F   F2           .0.56.0.  96.0.561    14           .0.562    1F.0.563    FB           .0.564    52.0.565    96           .0.566    B8.0.567    3C           .0.568    F.0..0.569    53           .0.56A    C.0..0.56B    D3           .0.56C    C.0..0.56D    C6           .0.56E    96.0.56F    BA           .0.57.0.  C8.0.571    BB           .0.572    2.0..0.573    BC           .0.574    .0.1.0.575    BC           .0.576    .0.1.0.577    54           .0.578    BB.0.579    74           .0.57A    92.0.57B    F6           .0.57C    9.0..0.57D    46           .0.57E    83.0.57F    BB           .0.58.0.  .0.F.0.581    EB           .0.582    81.0.583    B8           .0.584    3F.0.585    F.0.         .0.586    AC.0.587    18           .0.588    F.0..0.589    AD           .0.58A    54.0.58B    D3           .0.58C    E6.0.58D    9.0.         .0.58E    54.0.58F    A8           .0.59.0.  14.0.591    E5           .0.592    B8.0.593    3C           .0.594    C4.0.595    2D           .0.596    C4.0.597    C1           .0.598    B.0..0.599    .0..0.       .0.59A    18.0.59B    EC           .0.59C    98.0.59D    83           .0.59E    B4.0.59F    DB           .0.5A.0.  FA.0.5A1    F2           .0.5A2    A7.0.5A3    94           .0.5A4    48.0.5A5    A4           .0.5A6    A9.0.5A7    94           .0.5A8    43.0.5A9    B4           .0.5AA    C7.0.5AB    F4           .0.5AC    E6.0.5AD    96           .0.5AE    B7.0.5AF    BA           .0.5B.0.  2C.0.5B1    BB           .0.5B2    24.0.5B3    B4           .0.5B4    DB.0.5B5    14           .0.5B6    1F.0.5B7    C4           .0.5B8    C1.0.5B9    F.0.         .0.5BA    .0.2.0.5BB    23           .0.5BC    BF.0.5BD    39           .0.5BE    89.0.5BF    FF           .0.5C.0.  18.0.5C1    F.0.         .0.5C2    .0.2.0.5C3    23           .0.5C4    7F.0.5C5    A4           .0.5C6    D7.0.5C7    B4           .0.5C8    DB.0.5C9    B6           .0.5CA    B9.0.5CB    F.0.         .0.5CC    .0.2.0.5CD    23           .0.5CE    8.0..0.5CF    3A           .0.5D.0.  8A.0.5D1    A.0.         .0.5D2    18.0.5D3    F.0.         .0.5D4    .0.2.0.5D5    23           .0.5D6    EF.0.5D7    39           .0.5D8    89.0.5D9    FF           .0.5DA    83.0.5DB    B8           .0.5DC    2.0..0.5DD    B6           .0.5DE    E1.0.5DF    B8           .0.5E.0.  22.0.5E1    83           .0.6.0..0.                            B8.0.6.0.1  3C           .0.6.0.2  F.0..0.6.0.3  53           .0.6.0.4  1.0..0.6.0.5  C6           .0.6.0.6  2D.0.6.0.7  34           .0.6.0.8  .0..0..0.6.0.9  B9           .0.6.0.A  51.0.6.0.B  F1           .0.6.0.C  37.0.6.0.D  AF           .0.6.0.E  B9.0.6.0.F  4D           .0.61.0.  F.0..0.611    53           .0.612    C.0..0.613    C6           .0.614    2D.0.615    85           .0.616    F2.0.617    19           .0.618    95.0.619    F.0.         .0.61A    53.0.61B    2.0.         .0.61C    C6.0.61D    48           .0.61E    FF.0.61F    92           .0.62.0.  2D.0.621    52           .0.622    2D.0.623    F1           .0.624    D3.0.625    1C           .0.626    C6.0.627    B1           .0.628    F1.0.629    D3           .0.62A    8C.0.62B    C6           .0.62C    31.0.62D    23           .0.62E    .0.F.0.62F    44           .0. 63.0. A9.0.631    19           .0.632    F1.0.633    D3           .0.634    F.0..0.635    C6           .0.636    77.0.637    F1           .0.638    D3.0.639    E1           .0.63A    C6.0.63B    7B           .0.63C    F1.0.63D    D3           .0.63E    B4.0.63F    C6           .0.64.0.  87.0.641    F1           .0.642    D3.0.643    69           .0.644    C6.0.645    87           .0.646    C4.0.647    2D           .0.648    F1.0.649    77           .0.64A    77.0.64B    C6           .0.64C    F7.0.64D    .0.7         .0.64E    C6.0.64F    5D           .0.65.0.  .0.7.0.651    C6           .0.652    61.0.653    .0.7         .0.654    F6.0.655    8D           .0.656    C6.0.657    B1           .0.658    .0.7.0.659    96           .0.65A    2D.0.65B    C4           .0.65C    83.0.65D    BB           .0.65E    .0.1.0.65F    C4           .0.66.0.  63.0.661    BB           .0.662    .0.4.0.663    19           .0.664    F1.0.665    C6           .0.666    D1.0.667    .0.7         .0.668    C6.0.669    D7           .0.66A    .0.7.0.66B    C6           .0.66C    E1.0.66D    .0.7         .0. 66E   C6.0.66F    F5           .0.67.0.  .0.7.0.671    F6           .0.672    9A.0.673    96           .0.674    2D.0.675    A4           .0.676    57.0.677    19           .0.678    F1.0.679    C4           .0.67A    7F.0.67B    19           .0.67C    F1.0.67D    43           .0.67E    8.0..0.67F    .0.7         .0.68.0.  AA.0.681    A4           .0.682    9E.0.683    19           .0.684    F1.0.685    C4           .0.686    8.0..0.687    B8           .0.688    21.0.689    BA           .0.68A    A9.0.68B    A4           .0.68C    59.0.68D    .0.7         .0.68E    .0.7.0.68F    96           .0.69.0.  93.0.691    E4           .0.692    3A.0.693    F1           .0.694    D3.0.695    48           .0.696    96.0.697    2D           .0.698    C4.0.699    A5           .0.69A    .0.7.0.69B    C6           .0.69C    F9.0.69D    .0.7         .0.69E    C6.0.69F    FB           .0.6A.0.  .0.7.0.6A1    96           .0.6A2    2D.0.6A3    E4           .0.6A4    9B.0.6A5    19           .0.6A6    B4.0.6A7    46           .0.6A8    F1.0.6A9    37           .0.6AA    5.0..0.6AB    A.0.         .0.6AC    18.0.6AD    5.0.         .0.6AE    A.0..0.6AF    C4           .0.6B.0.  C1.0.6B1    B8           .0.6B2    69.0.6B3    B.0.         .0.6B4    .0..0..0.6B5    19           .0.6B6    B4.0.6B7    BD           .0.6B8    F8.0.6B9    29           .0.6BA    A8.0.6BB    23           .0.6BC    .0.2.0.6BD    14           .0.6BE    D7.0.6BF    A4           .0.6C.0.  A9.0.6C1    14           .0.6C2    E5.0.6C3    B8           .0.6C4    3C.0.6C5    F.0.         .0.6C6    B6.0.6C7    CC           .0.6C8    53.0.6C9    7F           .0.6CA    C4.0.6CB    CE           .0.6CC    53.0.6CD    BF           .0.6CE    A.0..0.6CF    C4           .0.6D.0.  .0.9.0.6D1    D4           .0.6D2    E7.0.6D3    23           .0.6D4    2.0..0.6D5    C4           .0.6D6    DD.0.6D7    B8           .0.6D8    3D.0.6D9    BA           .0.6DA    5.0..0.6DB    23           .0.6DC    4.0..0.6DD    4B           .0.6DE    AB.0.6DF    A4           .0.6E.0.  5D.0.6E1    B8           .0.6E2    49.0.6E3    BA           .0.6E4    58.0.6E5    C4           .0.6E6    DB.0.6E7    BA           .0.6E8    4C.0. 6E9   B8           .0.6EA    68.0.6EB    B9           .0.6EC    69.0.6ED    F1           .0.6EE    A.0..0.6EF    C8           .0.6F.0.  B9.0.6F1    51           .0.6F2    F1.0.6F3    A.0.         .0.6F4    83.0.6F5    A4           .0.6F6    4D.0.6F7    24           .0.6F8    DE.0.6F9    E4           .0.6FA    7D.0.6FB    E4           .0.6FC    91.0.7.0..0.     BB           .0.7.0.1  64.0.7.0.2  BA           .0.7.0.3  A6.0.7.0.4  8C           .0.7.0.5  EA.0.7.0.6  .0.4         .0.7.0.7  EB.0.7.0.8  .0.2         .0.7.0.9  EC.0.7.0.A  .0..0.       .0.7.0.B  83.0.7.0.C  8C           .0.7.0.D  EC.0.7.0.E  .0.C         .0.7.0.F  34.0.71.0.  DE           .0.711    BC.0.712    FA           .0.713    F4.0.714    .0..0.       .0.715    B8.0.716    69           .0.717    B.0..0.718    .0.1         .0.719    D4.0.71A    E7           .0.71B    BB.0.71C    21           .0.71D    85.0.71E    95           .0.71F    14.0.72.0.  1F           .0.721    F4.0.722    E6           .0.723    43.0.724    4.0.         .0.725    A1.0.726    15           .0.727    27.0.728    D7           .0.729    BA.0.72A    .0.A         .0.72B    8C.0.72C    EA           .0.72D    2B.0.72E    54           .0.72F    1C.0.73.0.  D4           .0.731    .0..0..0.732    74           .0.733    47.0.734    94           .0.735    4E.0.736    34           .0.737    A3.0.738    E4           .0.739    26.0.73A    B8           .0.73B    69.0.73C    B.0.         .0.73D    .0..0..0.73E    19           .0.73F    B8.0.74.0.  2D           .0.741    B6.0.742    45           .0.743    B8.0.744    35           .0.745    F.0..0.746    D1           .0.747    51.0.748    AA           .0.749    F1.0.74A    A.0.         .0.74B    18.0.74C    18           .0.74D    19.0.74E    F.0.         .0.74F    D1.0.75.0.  51           .0.751    AB.0.752    F1           .0.753    A.0..0.754    94           .0.755    A8.0.756    B8           .0.757    2C.0.758    B6           .0.759    5C.0.75A    B8           .0.75B    34.0.75C    F.0.         .0.75D    AC.0.75E    5A           .0.75F    AA.0.76.0.  F6           .0.761    7.0..0.762    FC           .0.763    37.0.764    5B           .0.765    4A.0.766    AB           .0.767    5C.0.768    AA           .0.769    FB.0.76A    C6           .0.76B    6E.0.76C    94           .0.76D    D5.0.76E    C4           .0.76F    C1.0.77.0.  18           .0.771    18.0.772    F.0.         .0.773    5B.0.774    AB           .0.775    5A.0.776    37           .0.777    AD.0.778    FA           .0.779    4B.0.77A    5D           .0.77B    E4.0.77C    66           .0.77D    B9.0.77E    2D           .0.77F    B6.0.78.0.  83           .0.781    B9.0.782    35           .0.783    BA.0.784    3.0.         .0.785    B8.0.786    67           .0.787    F1.0.788    A.0.         .0.789    19.0.78A    19           .0.78B    18.0.78C    F1           .0.78D    A.0..0.78E    C8           .0.78F    C4.0.79.0.  D3           .0.791    B9.0.792    2C           .0.793    B6.0.794    97           .0.795    B9.0.796    34           .0.797    BA.0.798    34           .0.799    E4.0.79A    85           .0.79B    B8.0.79C    32           .0.79D    B6.0.79E    A1           .0.79F    B8.0.7A.0.  3A           .0.7A1    BA.0.7A2    3C           .0.7A3    C4.0.7A4    D3           .0.7A5    76.0.7A6    A9           .0.7A7    B1.0.7A8    C.0.         .0.7A9    92.0.7AA    D3           .0.7AB    23.0.7AC    FF           .0.7AD    B8.0.7AE    2D           .0.7AF    A.0..0.7B.0.  B8           .0.7B1    2F.0.7B2    A.0.         .0.7B3    76.0.7B4    BB           .0.7B5    B8.0.7B6    35           .0.7B7    A.0..0.7B8    B8           .0.7B9    37.0.7BA    A.0.         .0.7BB    B4.0.7BC    .0.5         .0.7BD    B8.0.7BE    25           .0.7BF    B9.0.7C.0.  2C           .0.7C1    F4.0.7C2    DD           .0.7C3    76.0.7C4    CB           .0.7C5    B8.0.7C6    29           .0.7C7    B9.0.7C8    34           .0.7C9    F4.0.7CA    DD           .0.7CB    B8.0.7CC    3C           .0.7CD    B.0..0.7CE    .0.3         .0.7CF    94.0.7D.0.  21           .0.7D1    84.0.7D2    2C           .0.7D3    85.0.7D4    B4           .0.7D5    C7.0.7D6    76           .0.7D7    CB.0.7D8    95           .0.7D9    B4.0.7DA    C7           .0.7DB    E4.0.7DC    CB           .0.7DD    F.0..0.7DE    A1           .0.7DF    18.0. 7E.0. 18           .0.7E1    19.0.7E2    19           .0.7E3    F.0..0.7E4    A1           .0.7E5    83.0.7E6    B9           .0.7E7    55.0.7E8    B6           .0.7E9    EB.0.7EA    19           .0.7EB    F1.0.7EC    83           .0.7ED    28.0.7EE    43           .0.7EF    29.0.7F.0.  2.0.         .0.7F1    47.0.7F2    45           .0.7F3    2.0..0.7F4    31           .0.7F5    39.0.7F6    38           .0.7F7    32______________________________________ NOTE: ALL UNSPECIFIED ADDRESSES FROM 0 TO 7FFH ARE FILLED WITH DATA BYTE=00