Abstract:
In one embodiment, an electronic switch selectively passes an input signal from an input node to an output node based on a switch-control signal. The bulk of at least one transistor in the switch is connected to either the input node or the output node. The switch has two series-connected PMOS transistors connected in parallel with an NMOS transistor. The bulk and source of the first PMOS transistor are connected to the input node, while the bulk and source of the second PMOS transistor are connected to the output node. First and second level shifters ensure that the gates of the first and second PMOS transistors track the voltages at the input and output nodes, respectively. This configuration improves the ability of the switch to receive input voltages outside of the switch&#39;s power supply range without adversely affecting operations of the switch.

Description:
TECHNICAL FIELD 
   The present invention relates to electronics, and, in particular, to the electronic switches, such as complementary metal-oxide semiconductor (CMOS) switches. 
   BACKGROUND 
   A conventional CMOS switch comprises one or more CMOS transistors, each with its bulk (e.g., substrate or well) connected to one of the power supply rails (i.e., Vdd or Vss). For example, a single N-type CMOS (NMOS) transistor, with its drain connected to the input node Vin, its source connected to the output node Vout, its gate connected to receive a switch-control signal, and its bulk connected to Vss, can function as a CMOS switch that selectively presents an input voltage appearing at node Vin as an output voltage at node Vout, where the value of the switch-control signal applied to the transistor gate determines whether the switch passes or holds off the input signal. 
   Another example of a conventional CMOS switch is formed from an NMOS transistor connected in parallel to a P-type CMOS (i.e., PMOS) transistor, where the NMOS transistor is configured as before, and the PMOS transistor has its source connected to node Vin, its drain connected to node Vout, its gate connected to receive an inverted version of the switch-control signal, and its bulk connected to Vdd. 
   The ranges of voltages that can be applied to such conventional CMOS switches are often limited due to finite N-channel and/or P-channel thresholds. In some situations, the allowable input range spans only a portion of the available supply voltage range (e.g., Vdd-Vss). Moreover, any voltage beyond the supply voltage range is usually not allowed, since it may interfere with the proper operation of the switch in its open (i.e., off) mode. 
   To accommodate an input voltage range beyond the supply voltage range, some prior-art implementations rely on a boosted supply. This more-positive and/or more-negative supply is often locally generated and used instead of the PC board power supply, in effect operating the switch from a new power supply that now includes the desired expanded range. 
   Another prior-art implementation relies on attenuation of all input voltages to ensure that the input voltage levels remain within the allowable range. 
   SUMMARY 
   In one embodiment, the present invention includes a switch circuit for selectively presenting an input signal appearing at an input node of the switch circuit as an output signal at an output node of the switch circuit. The switch circuit comprises a switch block and switch-control circuitry. The switch-control circuitry is adapted to selectively open and close the switch block based on a switch-control signal. The switch block is connected between the input node and the output node and comprises one or more interconnected transistors, wherein a bulk of at least one transistor in the switch block is connected to one of the input node and the output node. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
       FIG. 1  shows a schematic circuit diagram of a switch circuit, according to one embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows a schematic circuit diagram of a switch circuit  100 , according to one embodiment of the present invention. Based on a switch-control signal applied at node Select, switch circuit  100  selectively presents an input voltage applied at node Vin as an output voltage at node Vout. 
   Switch circuit  100  comprises control-signal buffer  102 , switch block  104 , and first and second level shifters  106  and  108 . Control-signal buffer  102  buffers the switch-control signal applied at the Select node and provides buffered (inverted and non-inverted) versions of the switch-control signal to switch block  104  and level shifters  106  and  108 . Level shifters  106  and  108  shift the levels of the buffered switch-control signals from buffer  102  (from the range (Vss,Vdd) to the ranges (Vss,Vin/Vout)) and apply level-shifted versions of the buffered switch-control signals to switch block  104 . The buffered switch-control signal from buffer  102  and the level-shifted switch-control signals from level shifters  106  and  108  determine whether switch block  104  in an open (i.e., off) mode or a closed (i.e., on) mode. 
   If switch block  104  is in its open mode, then switch block  104  holds off the input voltage applied at node Vin (i.e., the input voltage is not presented as an output voltage at node Vout). In its open mode, switch block  104  also holds off the high voltages applied at node Vout from reaching node Vin. If switch block  104  is in its closed mode, then switch block  104  passes the input voltage applied at node Vin to the node Vout (i.e., the input voltage is presented as an output voltage at node Vout). Together, control-signal buffer  102  and level shifters  106  and  108  form switch-control circuitry for switch circuit  100 . 
   Physical Description 
   Switch block  104  comprises two sets of one or more transistors connected in parallel, where the first set has PMOS transistor P 23  connected in series with PMOS transistor P 2  (i.e., at their drains) and the second set has just NMOS transistor N 2 . As shown in  FIG. 1 , the source and bulk of P 23  and the drain of N 2  are all connected to node Vin. Similarly, the source and bulk of P 2  and the source of N 2  are all connected to node Vout. The bulk of N 2  is connected to Vss (e.g., ground). 
   Control-signal buffer  102  comprises inverters I 4  and I 2  connected in series, such that the output of I 4  is connected to the input of I 2 . The output of I 2  is connected to the gate of N 2 . 
   First level shifter  106  comprises a pair of cross-connected (i.e., gate to drain) PMOS transistors P 0  and P 1  connected in series with a pair of NMOS transistors N 3  and N 1 , respectively (at their drains). Similarly, second level shifter  108  comprises a pair of cross-connected PMOS transistors P 4  and P 5  connected in series with a pair of NMOS transistors N 5  and N 6 , respectively (at their drains). The output of inverter I 4  is connected to the gates of N 1  and N 6 , while the output of inverter I 2  is connected to the gates of N 3  and N 5 . The sources and bulks of P 0  and P 1  are both connected to node Vin, and the sources and bulks of P 4  and P 5  are both connected to node Vout. The sources and bulks of N 1 , N 3 , N 5 , and N 6  are all connected to Vss. 
   Functional Description 
   Low Switch-Control Signal 
   Functionally, if the switch-control signal applied at the Select node is low (e.g., Vss), then the output of inverter I 4  is high (i.e., Vdd) and the output of inverter I 2  is low (i.e., Vss). 
   If the output of I 2  is low, then N 2  is off and N 2  prevents the input voltage applied to node Vin from reaching Vout and also prevents a voltage applied at node Vout from reaching Vin. 
   If (i) the output of I 4  is high and (ii) the output of I 2  is low, then (a) N 1  and N 6  are both on and (b) N 3  and N 5  are both off. 
   In first level shifter  106 , if N 1  is on, then the gate of P 0  is driven towards Vss, which turns P 0  on. If P 0  is on and N 3  is off, then the gate of P 23  tracks the input voltage applied to node Vin. If the input voltage at Vin is low, then P 23  is on. If the input voltage at Vin is high, then P 23  is off. 
   Similarly, in second level shifter  108 , if N 6  is on, then the gate of P 4  is driven towards Vss, which turns P 4  on. If P 4  is on and N 5  is off, then the gate of P 2  tracks the voltage applied to node Vout. If the voltage at Vout is low, then P 2  is on. If the voltage at Vout is high, then P 2  is off. 
   Thus, if the voltages at Vin and Vout are both low, then P 23  and P 2  are both on, but, since, Vin and Vout are both low, it is functionally the same as if Vin and Vout were held off from each other. If (i) the input voltage at Vin is low and (ii) the voltage at Vout is high, then (a) P 23  is on and (b) P 2  is off, and the voltages at Vin and Vout are held off from each other. Similarly, if (i) the input voltage at Vin is high and (ii) the output voltage at Vout is low, then (a) P 23  is off and (b) P 2  is on, and the voltages at Vin and Vout are held off from each other. Lastly, if the voltages at nodes Vin and Vout are both high, then P 23  and P 2  are both off and the voltages at Vin and Vout are held off from each other. 
   As such, if the switch-control signal is low, then switch block  104  is functionally open (i.e., off), no matter whether the voltages applied at Vin and Vout are high or low. 
   High Switch-Control Signal 
   If, on the other hand, the switch-control signal applied at the Select node is high (e.g., Vdd), then the output of inverter I 4  is low (i.e., Vss) and the output of inverter I 2  is high (i.e., Vdd). 
   If the output of I 2  is high, then N 2  is on and N 2  enables the input voltage applied to node Vin to reach Vout. 
   If (i) the output of I 4  is low and (ii) the output of I 2  is high, then (a) N 1  and N 6  are both off and (b) N 3  and N 5  are both on. 
   In first level shifter  106 , if N 3  is on, then the gate of P 1  is driven towards Vss, which turns P 1  on. If P 1  is on and N 1  is off, then the gate of P 0  tracks the input voltage applied to node Vin. If the input voltage at Vin is low, then P 0  is on. If P 0  and N 3  are both on, then the gate of P 23  also tracks the low input voltage applied to node Vin and P 23  is on. If the input voltage at Vin is high, then P 0  is off. If P 0  is off and N 3  is on, then the gate of P 23  is driven towards Vss, which turns P 23  on. 
   Similarly, in second level shifter  108 , if N 5  is on, then the gate of P 5  is driven towards Vss, which turns P 5  on. If P 5  is on and N 6  is off, then the gate of P 4  tracks the voltage applied to node Vout. If the voltage at Vout is low, then P 4  is on. If P 4  and N 5  are both on, then the gate of P 2  also tracks the low voltage applied to node Vout and P 2  is on. If the voltage at Vout is high, then P 4  is off. If P 4  is off and N 5  is on, then the gate of P 2  is driven towards Vss, which turns P 2  on. 
   Thus, if the switch-control signal is high, then the P 23  and P 2  are both on, no matter whether the voltages applied at Vin and Vout are high or low. As such, if the switch-control signal is high, then switch block  104  is functionally closed (i.e., on). 
   Application of High Input/Output Voltages 
   The two sets of transistors in switch block  104  form two switch paths: one path containing P 23  and P 2  and the other path containing N 2 . Each path, when selected, passes signals over a portion of the supply range (Vdd-Vss). 
   Moreover, since the bulk of P 23  is connected to Vin, if an input voltage greater than Vdd is applied to Vin, then the bulk voltage and the source voltage of P 23  will both track the input voltage at Vin. This reduces the chances of breakdown or other adverse effects at P 23  due to high input voltages compared to a prior-art configuration in which the bulk of a PMOS transistor would be connected to Vdd. Moreover, first level shifter  106  ensures that the gate of P 23  also tracks the input voltage at Vin, which further reduces the chances of problems at P 23  due to input voltages greater than Vdd. 
   Similarly, since the bulk of P 2  is connected to Vout, if a voltage greater than Vdd is applied to Vout, then the bulk voltage and the source voltage of P 2  will both track the voltage at Vout. This reduces the chances of breakdown or other adverse effects at P 2  due to high voltages at Vout compared to a prior-art configuration in which the bulk of a PMOS transistor would be connected to Vdd. Moreover, second level shifter  108  ensures that the gate of P 2  also tracks the voltage at Vout, which further reduces the chances of problems at P 2  due to voltages at Vout greater than Vdd. 
   Thus, switch circuit  100  is capable of passing or holding off in either direction (i.e., Vout to Vin as well as Vin to Vout). The input signal range includes the entire power supply range. The input signal range also includes signals within one threshold voltage below the negative supply. On the positive side, the input signal can be substantially higher than the positive supply so long as no device breakdown level is exceeded. This extended input signal range is achieved without requiring either a boosted power supply or attenuation of the input signals. Also switch drivers require no stand-by DC current from either input or output. 
   ALTERNATIVE EMBODIMENTS 
   The present invention has been described in the context of switch circuit  100  in which switch block  104  has two transistor sets connected in parallel, where the first set has two PMOS transistors (P 23  and P 2 ) and the second set has only one NMOS transistor (N 2 ). The present invention is not necessarily limited to this embodiment. For example, in an alternative embodiment, the first set could have a single PMOS transistor and the second set could have two NMOS transistors, where the bulk of the PMOS transistor is connected to Vdd and the bulk of each NMOS transistor is appropriately connected to either the input node or the output node. Such an embodiment would have a negative voltage range. In another alternative embodiment, the first set could have two PMOS transistors and the second set could have two NMOS transistors, where the bulk of each NMOS and PMOS transistor is appropriately connected to either the input node or the output node. Such an embodiment would have a voltage range that spans beyond both positive and negative supply voltages. 
   The present invention can be implemented in the context of any CMOS technology, such as N-well, P-well, or multiple-well technologies. As used in the following claims, the term “channel terminal” refers generically to either the source or the drain of a CMOS transistor. 
   The present invention may, but does not have to, be implemented in a single integrated circuit, such as application-specific integrated circuit (ASIC) or a programmable device such as a field-programmable gate array (FPGA). 
   Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. 
   It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
   The use of FIGURE numbers and/or FIGURE reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.