Abstract:
An efficient back bias (V BB ) detection and control circuit make possible a low voltage memory device and includes an on-chip V BB  level sensor ( 38 ) that includes a dynamic voltage reference shift circuit ( 40, 42, 44, 46 ) for establishing a first voltage level (−(|2VTP|+VTN)) during power-up and a second voltage level (−|2VTP| during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.

Description:
This is a divisional of application Ser. No. 08/993,798 filed Dec. 18, 1997, which claims priority to India application, Serial No. 1714/MAS/97 of inventor Surelkar, et al., filed Jul. 31, 1997. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to integrated circuits systems that include integrated circuits and, more particularly, to memory circuits such as dynamic random access memory (DRAM) circuits and, even more particularly, to back bias (V BB ) detection and control schemes for low voltage DRAM circuits. 
     BACKGROUND OF THE INVENTION 
     Achieving proper operation of a memory circuit, such as a DRAM, typically requires an initial pause of 200 μsec followed by a minimum of eight initialization cycles after reaching the full V CC  level. Within the generally specified power-up pause of 200 μsec, reliable DRAM operation demands on-chip generated back bias voltage (V BB ). Providing the needed V BB  reduces junction capacitance, reduces substrate leakage and prevents forward biasing of junctions. Generating a deep V BB  level within the specified power-up, however, becomes difficult at low operating voltages (e.g., approximately 3.3 V). This is particularly true if the V BB  load capacitance is high, such as is the case for sub-micron technologies and higher DRAM densities. For instance, the typical V BB  load capacitance of a 16 Mb DRAM employing trench capacitor cells as storage elements is about 240 nf. 
     One type of circuit design for initializing and enabling peripheral circuits on a memory chip generates internally a positive pulse RID(RAS_ Input Disable). In this circuit, RID is designed to go positive as soon as power-on conditions are detected and reset when V BB  reaches a preset level. The resetting is usually accomplished by means of an analog sensor, which detects when the V BB  level is 2Vtn below ground. For example, TABLE 1 documents RID trip points for the 16 Mb shrink (16 MS) low voltage (3.3 V) DRAM fabricated using 0.5 μm technology. As TABLE 1 shows, RID reset is marginal to the power-up specification of 200 μs at 2.6 V, 100° C. and using a MSIG (minus sigma) process model. 
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 16 MS SIMULATION RESULTS 
               
             
          
           
               
                   
                 SIMULATION 
                   
                   
               
               
                   
                 CONDITIONS/MODEL 
                 RID TRIP POINT 
                 VBB @ RID 
               
               
                   
                   
               
               
                   
                 2.6 V, 100 C.|MSIG 
                 203 us 
                 −0.89 V 
               
               
                   
                 4.0 V, −10 C.|PSIG 
                  45 us 
                 −1.12 V 
               
               
                   
                   
               
             
          
         
       
     
     Of particular importance is the fact that if RID is not reset within the power-up spec time, then the device operation cannot be guaranteed. 
     In other words, this method uses RID to manipulate V BB  pumping during power-up in the memory device. RID is made a function of V BB , through a predetermined level sensor. V BB  pumping starts as soon as power-on is detected and stops after RID is reset. Such a scheme may be inadequate for low voltage operations, because at 16 MB densities, higher substrate capacitances result. Thus, V BB  may not reach a deep enough level to reset RID. This will keep the device in initialization mode, and prohibit normal memory device operation. 
     One method to reset RID expeditiously is to pump harder the V BB , so that RID reset is not marginal to spec. Usually, V BB  pumping during power-up is stopped after RID is reset. This method extends pumping beyond RID reset so that the V BB  level is deep on power-up. As the process models/operating conditions change, if pumping is extended uncontrolled, V BB  becomes too deep and may adversely affect memory device operation. 
     SUMMARY OF THE INVENTION 
     In light of the above limitations, there is a need for an improved memory device initialization circuit that avoids the limitations by providing a sufficiently deep and prompt back bias supply for a memory device during power-up, but which back bias supply is not too deep for normal low voltage operation. 
     The present invention, therefore, provides a back bias control circuit for a memory device, such as a DRAM, that eliminates or substantially reduces the slow and low voltage power-up problems affecting known back bias supply circuits. 
     According to one aspect of the invention, there is provided an efficient back bias (V BB ) detection and control circuit that makes possible a low voltage memory device and thus includes an on-chip V BB  level sensor having a dynamic voltage reference shift circuit for establishing a first voltage level during power-up and a second voltage level during normal operation. The first voltage is of a deeper level to achieve a short power-up interval. The second voltage level is of a level less deep than the first voltage for achieving low power operation. 
     According to another aspect of the invention, there is provided an on-chip V BB  level sensor that chooses a −(|2VTP|+VTN) reference during power-up and a −(|2VTP|) reference after power-up. A power-up complete signal is combined with the sensor output to conditionally bypass the extra N-channel transistor in the sensor circuit, thus changing the sensing level from −(|2VTP|+VTN) to −(|2VTP|) dynamically. The sensor output is used to keep the pumps, including a booster pump, a high power pump, and a low power pump, for example, enabled until a deep V BB  condition is detected. This quickens the substrate pumping enabling us to achieve deeper V BB  level in a shorter time interval. The feedback path ensures that until the power-up condition is reached, −(|2VTP|+VTN) sensing is enabled. The on-chip V BB  detection and control circuit cuts off all extra pumping once deep V BB  is sensed by the sensor. Once the memory device reaches the powered-up condition, the present invention enables the feedback path to N-channel transistor. This results in bypassing the N-channel transistor. From this point onward, only the −(|2VTP|) reference level appears in the sensor input path. 
     A technical advantage of the present invention is its use of an on-chip oscillator that helps low power operation. The on-chip oscillator makes use of the dynamically reconfigured −(2VTP) level sensor (described above), during normal operation. 
     A technical advantage of the present invention is that it provides for RID resetting at a relatively shallow V BB  level. The present invention, therefore, allows the device to initialize within the specified time for the DRAM and pumps are not cut off. This allows V BB  to reach a deep level. 
     Other technical advantages that the present invention provides is achieving desired (deep) V BB  level with shorter power-up interval, and reconfiguring of the same sensor for low power operation once the sensor circuit detects the powered-up condition. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description which is to be taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein: 
     FIG. 1 is a block diagram of a V BB  generation system of the present invention; and 
     FIG. 2 is a schematic diagram of a sensor circuit used in the low power oscillator of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Preferred embodiments of the present invention are illustrated in the figures like numerals being used to refer to like and corresponding parts of the various drawings. 
     FIG. 1 shows V BB  control circuit  10  of the present invention for generating and regulating the back bias voltage level for an associated memory device, such as a DRAM. In V BB  control circuit  10 , the V BB  voltage level output  12  is controlled by the combined outputs of low power pump circuit  14 , high power pump circuit  16 , and booster pump circuit  18 . Low power oscillator  20  receives input from counter circuit  22  and V BB  control logic circuit  24 , which receives input from V BB  level detector circuit  26  and power-up detector circuit  28 . V BB  control logic circuit  24  also feeds high power oscillator circuit  30  and booster oscillator circuit  32 . High power oscillator circuit  30  provides input to high power pump  16 , while booster pump circuit  18  receives input from booster oscillator circuit  32 . 
     Low power pump circuit  14  supplies current that is generally consumed by substrate leakage, when the device is in the standby mode of operation. High power pump circuit  16  supplies substrate current during the active cycle of V BB  control circuit  10 . Booster pump circuit  18  provides a boost voltage during initial power-up, as well as in the event that V BB  goes shallow. Variable frequency, low power oscillator  20  pumps low power pump circuit  14 . High frequency, high power oscillator  30  pumps high power pump circuit  16 , while booster oscillator circuit  32  pumps booster pump circuit  18 . Low power pump circuit  14  and high power pump circuit  16  also pump V BB  during initial power-up. 
     Variable frequency, low power oscillator circuit  20  provides low power operation, with its frequency varying according to the V BB  level. The deeper the V BB  level, the lower the oscillator frequency and, therefore, the lower the power consumption. The low power oscillator works off a −2Vtp V BB  level sensor to control its frequency. 
     Counter circuit  22  counts a fixed time interval after RID reset. The counter count output from counter circuit  22  determines the amount of time for which pumping is to be extended. FIG. 2 shows one embodiment of level sensor circuit  38  of the present invention, which is part of low power oscillator circuit  20 . Level sensor circuit  38  includes N-channel transistor  40  that receives a power-up complete signal at line  42 . Level sensor circuit  38  also includes P-channel transistors  44  and  46 . After the memory device power supply is turned on, power up complete (PUC) signal on line  42  is low and the level sensor circuit  38  is configured for sensing a level of −(2Vtp+Vtn). 
     The PUC signal can go high under two conditions. One condition is when RID goes low and the counter circuit  22  preset count is complete. The other condition is when V BB  value goes below −(2Vtp+Vtn). In the first condition, PUC signal  42  goes high and N-channel transistor  40  is fully turned on. At this point, the sensor is configured for −2Vtp detection. In the second case, a V BB  level below −(2Vtp+Vtn) is detected which, in turn, causes PUC signal  42  to go high and configures level sensor circuit  38  for −2Vtp detection. While the first case occurs at the slow corner (low voltage and slow process parameters) of the circuit characteristic curve, the second case occurs at the fast corner (high voltage and fast process parameters) of the circuit characteristic curve. 
     For level sensing circuit  38 , the sensing level of −(2Vtp+Vtn) keeps an upper bound on the V BB . This avoids the problem of V BB  going too deep at the fast corner. After power-up is complete, the sensing level of −(2Vtp+Vtn) is no longer necessary and a sensing level of −2Vtp is sufficient to control the low power oscillator  20 . 
     After power-up, N-channel transistor  40  fully turns on and the sensing level dynamically changes from −(2Vtp+Vtn) to −2Vtp. The dynamic reconfiguration of the −(2Vtp+Vtn) sensor allows using the same sensor both during power-up and during normal operation. This eliminates the need for two different sensors, thereby saving leakage current, and ultimately lowering power operation. 
     TABLE 2 shows the simulation results for one embodiment of the present invention to illustrate the effect of the present invention with a 16 MB shrink low voltage (3.3 V) DRAM. 
     
       
         
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
             
             
               
                   
                   
               
               
                   
                 Simulation Results of Invention 
               
             
          
           
               
                 SIMULATION 
                 RID TRIP 
                   
                   
               
               
                 CONDITIONS/MODEL 
                 POINT 
                 V BB  @ RID 
                 V BB  @ PUC 
               
               
                   
               
               
                 2.6 V, 100 C.|MSIG 
                 123 us 
                 −0.95 V 
                 −1.22 V 
               
               
                 3.3 V, 27 C.|MEAN 
                  60 us 
                 −1.15 V 
                 −1.54 V 
               
               
                 4.0 V, −10 C.|PSIG 
                  32 us 
                 −1.20 V 
                 −1.78 V 
               
               
                   
               
             
          
         
       
     
     To summarize, the present invention provides an on-chip V BB  level sensor that chooses a −(|2VTP|+VTN) reference during power-up and a −(|2VTP|) reference after power-up. With the present invention, a power-up complete signal is combined with the sensor output to conditionally bypass the extra N-channel transistor in the sensor circuit. This dynamically changes the sensing level from −(|2VTP|+VTN) to −(|2VTP|). Sensor circuit  38  of the preferred embodiment provides output that keeps the pump circuits  14 ,  16 , and  18  enabled during power-up until it detects a deep V BB  condition. This makes substrate pumping faster, thereby permitting a deeper V BB  level in a shorter time interval. The feedback path that the present invention provides ensures that until the memory device reaches the powered-up condition −(|2VTP|+VTN) sensing is enabled. The present invention cuts off extra pumping once sensor circuit  38  senses deep V BB . Once the memory device reaches powered-up condition, the feedback path to N-channel transistor is permanently enabled, and thereby bypassed. From this point onward, only the −(|2VTP|) reference level appears in the sensor path. Sensor circuit  38  preferably resides on-chip in low power oscillator and helps low power operation. Thus V BB  is pumped deeper during power-up. 
     Although the invention has been described in detail herein with reference to the illustrative embodiments, it is to be understood that this description is by way of example only and is not to be construed in a limiting sense. It is to be further understood, therefore, that numerous changes in the details of the embodiments of the invention and additional embodiments of the invention, will be apparent to, and may be made by, persons of ordinary skill in the art having reference to this description. It is contemplated that all such changes and additional embodiments are within the spirit and true scope of the invention as claimed below.