Abstract:
A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions.

Description:
RELATED APPLICATIONS 
     The present Application is a division of U.S. patent application Ser. No. 12/949,888filed on Nov. 19, 2010, now U.S. Pat. No. 8,569,131, issued Oct. 29, 2013. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of semiconductor devices; more specifically, it relates to MOSFET source/drain-to-source/drain interconnections and methods of fabricating MOSFET source/drain-to-source/drain interconnections. 
     BACKGROUND 
     As the dimensions of integrated circuits decrease, lithographic constraints are tending toward the gates of field effect transistors (FETs) to be orientated in a single direction on a fixed pitch. This adds to an increase in the density of the wiring at the next level used to interconnect source/drains of two or more FETs which are also constrained by lithography. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
     SUMMARY 
     A first aspect of the present invention is a structure, comprising: first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions. 
     A second aspect of the present invention is a method, comprising: forming trench isolation in a semiconductor substrate, the trench isolation separating first and second semiconductor regions in the semiconductor substrate; forming a trench in a region of the trench isolation and between and abutting the first and second semiconductor regions; and simultaneously forming a first gate electrode extending over the first semiconductor region, a second gate electrode extending over the second semiconductor region, and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions. 
     These and other aspects of the invention are described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1 through 11  illustrate a first method of fabricating a gate-to-gate strap according to an embodiment of the present invention; 
         FIG. 12  illustrates the result of adding an additional process step after the step illustrated in  FIG. 9 ; and 
         FIGS. 13-15  illustrate fabrication of and an alternative strap configuration according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 through 11  illustrate a first method of fabricating a gate-to-gate strap according to an embodiment of the present invention.  FIG. 1  is a plan view and  FIGS. 1A and 1B  are cross-sectional views through lines  1 A- 1 A and  1 B- 1 B respectively of  FIG. 1 . A section though line  1 C- 1 C would be similar to section  1 A- 1 A. In  FIGS. 1 ,  1 A and  1 B, formed in a semiconductor substrate  100  (or a semiconductor layer of semiconductor-on-insulator (SOI) substrate) is trench isolation  105  surrounding the perimeters of substrate regions  110 A and  110 B. In one example, semiconductor substrate is a single-crystal silicon substrate (or semiconductor layer is a single-crystal silicon layer of an SOI substrate). Trench isolation may be formed by etching a trench into the substrate, depositing a dielectric material (e.g., silicon dioxide (SiO 2 )) to overfill the trench and cover the surface of substrate, followed by a chemical-mechanical-polish (CMP) to coplanarize the top surfaces of the substrate and the dielectric material in the trench. 
       FIG. 2  is a plan view and  FIGS. 2A and 2B  are cross-sectional views through lines  2 A- 2 A and  2 B- 2 B respectively of  FIG. 2 . A section though line  2 C- 2 C would be similar to section  2 A- 2 A. In  FIGS. 2 ,  2 A and  2 B a gate dielectric layer  115  is formed on trench isolation  105  and substrate regions  110 A and  110 B. In one example, gate dielectric layer  115  comprises SiO 2 , silicon nitride (Si 3 N 4 ) or combinations of layers thereof. In one example gate dielectric layer  115  is a high-K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y or HfSi x O y N z or combinations of layers thereof. A high-K dielectric material has a relative permittivity above about 10.In one example, gate dielectric layer  115  is about 0.5nm to about 20nm thick. 
       FIG. 3  is a plan view and  FIGS. 3A and 3B  are cross-sectional views through lines  3 A- 3 A and  3 B- 3 B respectively of  FIG. 3 . A section though line  3 C- 3 C would be similar to section  3 A- 3 A. In  FIGS. 3 ,  3 A and  3 B a patterned photoresist layer  120  is formed and a trench  125  is etched (e.g., by reactive ion etch (RIE) in gate dielectric layer  115 . Trench  125  extends over substrate regions  110 A and  110 B as well as a region of trench isolation  105  between substrate regions  110 A and  110 B. 
       FIG. 4  is a plan view and  FIGS. 4A and 4B  are cross-sectional views through lines  4 A- 4 A and  4 B- 4 B respectively of  FIG. 4 . A section though line  4 C- 4 C would be similar to section  4 A- 4 A. In  FIGS. 4 ,  4 A and  4 B trenches  130  are etched in substrate regions  110 A and  110 B where substrate regions  110 A and  110 B are exposed in trench  125 . In one example, trenches  130  are etched using a RIE etch selective to substrate  100  (e.g., silicon) over trench isolation (e.g., silicon oxide). Trenches  130  extend from a top surface  127  of substrate into substrate  100 . Though illustrated as still present, patterned photoresist layer  120  may be removed prior to etching trenches  130 . 
       FIG. 5  is a plan view and  FIGS. 5A and 5B  are cross-sectional views through lines  5 A- 5 A and  5 B- 5 B respectively of  FIG. 5 . A section though line  5 C- 5 C would be similar to section  5 A- 5 A. In  FIGS. 5 ,  5 A and  5 B a trench  135  is etched in trench isolation  115  where trench isolation  105  is exposed in trench  125 . In one example, trench  135  is etched using a RIE etch selective to trench isolation  105  (e.g., silicon oxide) over substrate  100 (e.g., silicon). Though illustrated as still present, patterned photoresist layer  120  may be removed prior to etching trench  135  if not already removed previously. Trench  135  extends from a top surface  137  of trench isolation  105  into trench isolation  105 . Trench  135  does not extend through trench isolation  105  to underlying substrate  100 . 
       FIG. 6  is a plan view and  FIGS. 6A and 6B  are cross-sectional views through lines  6 A- 6 A and  6 B- 6 B respectively of  FIG. 6 . A section though line  6 C- 6 C would be similar to section  6 A- 6 B. In  FIGS. 6 ,  6 A and  6 B patterned photoresist layer  120  (see, for example  FIGS. 3 ,  3 A and  3 B) is removed if not removed previously. A completed trench  140  includes trenches  130  and trench  135 . Trench  135  is open within trench  140  to trenches  130 . The depth of trench  130  is D 1  and the depth of trench  135  is D 2 . In one example, D 1  is equal to D 2 . In one example, D 1  is greater than D 2 . In one example, D 2  is greater than D 2 . 
       FIG. 7  is a plan view and  FIGS. 7A and 7B  are cross-sectional views through lines  7 A- 7 A and  7 B- 7 B respectively of  FIG. 7 . A section though line  7 C- 7 C would be similar to section  7 A- 7 A. In  FIGS. 7 ,  7 A and  7 B an electrically conductive layer  145  is deposited on substrate  100  and in trench  140 . In one example, electrically conductive layer  145  is polysilicon formed by chemical vapor deposition (CVD). 
       FIG. 8  is a plan view and  FIGS. 8A and 8B  are cross-sectional views through lines  8 A- 8 A and  8 B- 8 B respectively of  FIG. 8 . A section though line  8 C- 8 C would be similar to section  8 A- 8 A. In  FIGS. 8 ,  8 A and  8 B, a gate electrode  150  and a strap  155  are formed. Gate electrodes  150 A and  150 B and strap  155  are simultaneously formed. In one example gate electrodes  150 A and  150 B and strap  155  are formed by a photolithographic process that forms a patterned photoresist layer on polysilicon layer  145  (see  FIGS. 7 ,  7 A and  7 B) only over the region of the polysilicon layer that is to become the gate electrodes, followed by an RIE, followed by removal of the patterned photoresist layer. Strap  155  is recessed into trench  140 . In a preferred embodiment, a top surface  157  of strap  155  is recessed below top surface  127  of substrate  100  and a top surface  158  of strap  155  is recessed below top surface  137  of trench isolation  105 . Alternatively, at least regions of top surfaces  157  and  158  may be may extend above top surfaces  127  and  137  respectively. 
     In  FIG. 8 , first major axes A 1  of gate electrode  150 A, A 2  of second gate electrode  150 B and A 3  of strap  155  are parallel. Second major axes A 4  of first semiconductor region  110 A and A 5  of second semiconductor region  110 B are parallel. Major axes A 1 , A 2  and A 3  are perpendicular to major axes A 4  and A 5 . Strap  155  does not extend vertically through trench isolation  105  into substrate  100 . 
       FIG. 9  is a plan view and  FIGS. 9A and 9B  are cross-sectional views through lines  9 A- 9 A and  9 B- 9 B respectively of  FIG. 9 . A section though line  9 C- 9 C would be similar to section  9 A- 9 A. In  FIGS. 9 and 9B  source/drain extensions  160  are formed in substrate regions  110 A and  110 B. Source/drain extensions may be formed by an angled (at an acute angle relative to the top surface of substrate  100 ) ion implantation while substrate  100  is rotating about an axis perpendicular to the top surface of the substrate. The source/drain ion implantation also implants dopant into an upper region  165  of strap  155 . 
       FIG. 10  is a plan view and  FIGS. 10A and 10B  are cross-sectional views through lines  10 A- 10 A and  10 B- 10 B respectively of  FIG. 10 . A section though line  10 C- 10 C would be similar to section  10 A- 10 A. In  FIGS. 10 ,  10 A and  10 B dielectric sidewall spacers  170  are formed on the sidewalls of gate electrodes  150 A and  150 B and sidewall spacers  170 A are formed on the sidewalls of trench  140 . In one example, sidewall spacers  170  and  170 A comprise Si 3 N 4 . Sidewall spacers  170  and  170 A may be formed simultaneously by a blanket deposition of a conformal dielectric layer followed by an RIE to remove the dielectric material from horizontal surfaces (surfaces parallel to the top surface of substrate  100 ). 
     After sidewall spacer formation, source/drains  180  are formed in substrate regions  110 A and  110 B, for example, by ion implantation where substrate regions  110 A and  110 B are not protected by gate electrodes  150 A and  150 B or sidewall spacers  170 . Source/drains  180  include integral source/drain extensions  160 . Channel regions  182  of substrate region  110 A (and  110 B) are defined between source/drain extensions  160  under gate electrode  150 A (and  150 B, not shown). In one example, gate dielectric layer  115  is also removed by the spacer RIE process where the gate dielectric layer is not protected by gate electrodes  150 A and  150 B or sidewall spacers  170  (as they are formed). The source/drain ion implantation also implants dopant into an upper region of strap  155 . 
     Although, strap  155  is illustrated in  FIG. 10A  as extending vertically all the way through source/drains  180 , into substrate region  110 A, alternatively, strap  155  may not extend vertically through source/drains  180  into substrate region  110 A. 
       FIG. 11  is a plan view and  FIGS. 11A and 11B  are cross-sectional views through lines  11 A- 11 A and  11 B- 11 B respectively of  FIG. 11 . A section though line  11 C- 11 C would be similar to section  11 A- 11 A. In  FIGS. 11A and 11B  optional metal silicide layers  185  (when semiconductor regions  110 A and  110 B include or are silicon) are formed on exposed surfaces of source/drains  180 , gate electrodes  150 A and  150 B and strap  155 . Metal silicide layers  185  may be formed by depositing a thin metal layer, followed by high temperature heating in an inert or reducing atmosphere at a temperature that will cause the metal to react with silicon followed by an etch to remove un-reacted metal. Because of sidewall spacers  170 A silicide layer  185  does not cover the entire top surface of strap  155 , but is continuous from source/drain  180  in substrate region  110 A to source/drain  180  in substrate region  110 B. 
       FIG. 12  illustrates the result of adding an additional process step after the step illustrated in  FIG. 9 .  FIG. 12  is a plan view and  FIGS. 12A and 12B  are cross-sectional views through lines  12 A- 12 A and  12 B- 12 B respectively of  FIG. 12 . A section though line  12 C- 12 C would be similar to section  12 A- 12 A. In  FIGS. 12A and 12B  sidewall spacers  170 A are removed prior to silicide formation (either before or after source/drain formation) so silicide layer  185  covers all of a top surface  187  of strap  155 . 
       FIGS. 13-15  illustrate fabrication of and an alternative strap configuration according to an embodiment of the present invention.  FIG. 13  is a plan view and  FIGS. 13A and 13B  are cross-sectional views through lines  13 A- 13 A and  13 B- 13 B respectively of  FIG. 13 . A section though line  13 C- 13 C would be similar to section  13 A- 13 A.  FIGS. 13 ,  13 A and  13 B are similar to respective  FIGS. 5A ,  5 B and  5 C. The steps illustrated in  FIGS. 1 and 2  are performed the steps in  FIG. 13 . In  FIGS. 13A and 13B  trench  135  is formed only in trench isolation  105 . Gate dielectric layer  115  is removed from over substrate regions  110 A and  110 B where the dielectric layer is not covered by patterned photoresist layer  120  and an etch selective to trench isolation  105  over substrate regions  110 A and  110 B is performed so essentially no trench is formed in substrate regions  110 A and  110 B while a trench  140 A is formed in trench isolation  105 . Trench  125  does not extend into substrate regions  110 A and  110 B but abuts them. 
       FIG. 14  is a plan view and  FIGS. 14A and 14B  are cross-sectional views through lines  14 A- 14 A and  14 B- 14 B respectively of  FIG. 14 . A section though line  14 C- 14 C would be similar to section  14 A- 14 A. In  FIGS. 14A and 14B  patterned photoresist layer  120  (see  FIG. 13 ) is removed. Trench  140 A does not extend vertically through trench isolation  105 . Trench  140 A extends from substrate region  110 A to substrate region  110 B. 
       FIG. 15  is a plan view and  FIGS. 15A ,  15 B and  15 D are cross-sectional views through lines  15 A- 15 A,  15 B- 15 B and  15 D- 15 D respectively of  FIG. 15 . A section though line  15 C- 15 C would be similar to section  15 A- 15 A. In  FIGS. 15A and 15B  the steps illustrated in  FIGS. 7 through 10  and  12  are performed resulting in the structures of  FIGS. 15 ,  55 A,  15 B, and  15 D. Strap  155 A abuts sidewalls of source/drains  180  as illustrated by the dashed lines of  FIG. 15A . Silicide layer  185  forms a continuous layer over source drains  180  that abut strap  155 A and over strap  155 A as illustrated in  FIG. 15D . Thus there is an electrical connection between the source/drains abutting strap  155 A through strap  155 A as well as through silicide layer  185 . 
     Thus the embodiments of the present invention provide a recessed strap for interconnecting two or more source/drains of adjacent MOSFETs, reducing the need for interconnecting the source/drains at a higher interconnect level. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.