Abstract:
The present invention includes the steps of preparing a core substrate having a through hole therein, arranging the conductive parts in the through hole in a state that a top end side of the conductive parts forms a projected portion projected from the core substrate, by inserting a conductive parts having a length, which is longer than a thickness of the core substrate, into the through hole of the core substrate, forming an insulating film on the core substrate to coat the projected portion of the conductive parts, and planarizing the insulating film by grinding the insulating film.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a wiring substrate manufacturing method and, more particularly, a method of manufacturing a wiring substrate having a structure capable of getting conductivity between both surface sides of a core substrate via through holes provided in the core substrate.  
           [0003]    2. Description of the Related Art  
           [0004]    Conventionally there is the wiring substrate having the structure in which wiring patterns formed on both surface sides of the core substrate are connected mutually via through holes in the core substrate. In such wiring substrate, a copper plating layer, a conductive paste, a metal pillar (a metal pin or a metal wire), or the like is filled in the through holes in the core substrate. In order to fill the conductive material in the through holes with a high aspect ratio at a low cost and with good reliability, sometimes a method of inserting the metal pillar into the through holes is more favorable than a method of filling the through holes with the copper plating layer or the conductive paste.  
           [0005]    The wiring substrate having the structure in which the metal pillar is inserted into the through holes provided in the core substrate is set forth in Patent Literature 1 (Patent Application Publication (KOKAI) Sho 62-98694) and Patent Literature 2 (Patent Application Publication (KOKAI) 2002-289999), for example.  
           [0006]    In the method of inserting the metal pillar into the through holes, in order to assure the conduction between both surface sides of the core substrate, normally the metal pillar whose length is set longer than a thickness of the core substrate (a depth of the through hole) is inserted into the through holes. Hence, the metal pillar is arranged in the through holes in a state that such metal pillar has its projected portions projected from both surfaces of the core substrate.  
           [0007]    Also, in case the core substrate having the wiring patterns thereon is employed, in order to assure reliability of electrical connections between the metal pillars and the wiring patterns, sometimes the projected portions of the metal pillars are crashed by the caulking process and then the plating is applied to these connection portions after the metal pillar is inserted into the through holes.  
           [0008]    In this manner, when the metal pillar is inserted into the through holes of the core substrate, level differences are generated by the projected portions of the metal pillars on both surfaces of the core substrate. Therefore, such a problem exists that, upon laminating the interlayer insulating films and the wiring patterns on the core substrate, it becomes difficult to form fine multi-layered wirings at a high density because of the influence of the level differences.  
           [0009]    In order to avoid such problem, in Patent Literature 3 (Patent Application Publication (KOKAI) 2001-352166), it is set forth that the through-hole parts in which outer peripheral portions of core wires (metal pillars) are covered with the resin is inserted into the through holes of the core substrate, and then top end surfaces of the through-hole parts and surfaces of the core substrate are planarized by polishing the core wires of the through-hole parts (metal pillars) and the resin at the same time so as to get a coplanar surface.  
           [0010]    However, according to the method in Patent Literature 3, such an effect can be achieved that the level differences caused by the through-hole parts can be dissolved, nevertheless it is possible to deform the metal pillars or extend the polished metal piece onto the polished surface since the resin of the through-hole parts and the metal pillars are polished simultaneously to planarize. As a result, it is supposed that the metal pillars cannot be polished with good reliability.  
         SUMMARY OF THE INVENTION  
         [0011]    It is an object of the present invention to provide a wiring substrate manufacturing method capable of planarizing level differences caused by projections of metal pillars without any trouble in a wiring substrate having a structure in which conductive parts having projected portions projected from a core substrate are inserted into through holes of the core substrate.  
           [0012]    The present invention is related to a wiring substrate manufacturing method which comprises the steps of preparing a core substrate having a through hole therein; arranging the conductive parts in the through hole in a state that a top end side of the conductive parts forms a projected portion projected from the core substrate, by inserting a conductive parts having a length, which is longer than a thickness of the core substrate, into the through hole of the core substrate; forming an insulating film on the core substrate to coat the projected portion of the conductive parts; and planarizing the insulating film by plating the insulating film.  
           [0013]    In the present invention, the conductive parts (metal pillar, or the like) whose length is longer than a thickness of the insulating substrate is inserted into the through holes of the insulating substrate, and then the conductive parts is arranged in the through holes of the insulating substrate in a state that such conductive parts has its projected portions projected from the insulating substrate. Then, the insulating layer for coating the projected portions of the conductive parts is formed on the insulating substrate, and then the insulating layer is planarized by the polishing or the grinding.  
           [0014]    In the present invention, the level differences due to the projected portions of the conductive parts are eliminated not by polishing the projected portions themselves of the conductive parts to planarize but by polishing merely the insulating layers in the condition that the projected portions of the conductive parts are covered/held with the insulating layers. Therefore, it is not possible to generate disadvantages such as deformation of the conductive parts in the polishing step, and thus the level differences due to the projected portions of the conductive parts can be eliminated by planarizing the insulating layers with good reliability.  
           [0015]    As a result, since the level differences due to the projected portions of the conductive parts are eliminated when the wiring patterns connected to the conductive parts are formed over the conductive parts, a precision in the photolithography can be improved. Therefore, the fine multi-layered wiring patterns can be formed with good precision and also the high-density wiring substrate can be manufactured easily.  
           [0016]    In one preferred mode of the present invention, in the step of planarizing the insulating film, the insulating film may be left on the conductive parts, or the insulating film may be polished until a top end surface of the conductive parts is exposed. Alternately, an upper insulating film for coat the conductive parts may be formed further after the insulating film is polished until a top end surface of the conductive parts is exposed.  
           [0017]    Also, the insulating substrate, the metal plate, or the metal base substrate having the laminated structure of a metal plate and an insulating layer is used as the core substrate. When the metal plate or the metal base substrate is used, the generation of the electric short-circuit between the conductive parts can be prevented by using the conductive parts having the coaxial structure, which is formed by coating the insulating member on the outer peripheral portion of the metal pillar, as the conductive parts.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIGS. 1A to  1 I are sectional views showing a wiring substrate manufacturing method according to a first embodiment of the present invention;  
         [0019]    [0019]FIGS. 2A to  2 D are sectional views showing a variation of the wiring substrate manufacturing method according to the first embodiment;  
         [0020]    [0020]FIGS. 3A to  3 D are sectional views showing a wiring substrate manufacturing method according to a second embodiment of the present invention;  
         [0021]    [0021]FIGS. 4A to  4 D are sectional views showing a wiring substrate manufacturing method according to a third embodiment of the present invention;  
         [0022]    [0022]FIGS. 5A to  5 F are sectional views showing a wiring substrate manufacturing method according to a fourth embodiment of the present invention; and  
         [0023]    [0023]FIGS. 6A to  6 F are sectional views showing a wiring substrate manufacturing method according to a fifth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]    Embodiments of the present invention will be explained with reference to the drawings hereinafter.  
       First Embodiment  
       [0025]    [0025]FIGS. 1A to  1 I are sectional views showing a wiring substrate manufacturing method according to a first embodiment of the present invention, and FIGS. 2A to  2 D are sectional views showing a variation of the wiring substrate manufacturing method according to the first embodiment.  
         [0026]    In the wiring substrate manufacturing method according to the present embodiment, as shown in FIG. 1A, first an insulating substrate  10  is prepared as a core substrate, and then through holes  10   a  are formed in the insulating substrate  10  by drilling, punching, or the like. For example, a thickness of the insulating substrate is 300 to 500 μm, and a diameter of the through hole  10   a  is set to 100 to 300 μm. As the insulating substrate  10 , either a rigid substrate such as a glass epoxy substrate, or the like or a flexible substrate is employed.  
         [0027]    Then, as shown in FIG. 1B, conductive parts  20  that are inserted into the through holes  10   a  of the insulating substrate  10  are prepared. In this conductive parts  20 , its diameter corresponds to the diameter of the through hole  10   a  of the insulating substrate  10 , and its length is set longer than a thickness of the insulating substrate  10 . Then, the conductive parts  20  are inserted into the through holes  10   a  of the insulating substrate  10  and then fixed. As the conductive parts  20 , a metal pillar prepared by cutting a metal wire made of copper (Cu), Cu alloy, solder, or the like to a predetermined length is employed.  
         [0028]    At this time, the conductive parts  20  are fitted into the through holes  10   a  in a state that their projected portions  20   a ,  20   b  are projected from both surfaces of the insulating substrate  10  respectively. For example, a height h of the projected portions  20   a ,  20   b  from the insulating substrate  10  is set to 20 to 60 μm.  
         [0029]    Then, as shown in FIG. 1C, the projected portions  20   a ,  20   b  of the conductive parts  20  are coated by forming insulating layers  12   a ,  12   b  on both surfaces of the insulating substrate  10  respectively. Preferably a thickness of the insulating layer  12   a  should be set thicker than a height h of the projected portions  20   a ,  20   b  of the conductive parts  20 . As an example of the insulating layers  12   a ,  12   b , a resin film made of epoxy resin, polyphenylene ether resin, phenol resin, fluororesin, or the like is employed. The resin film is laminated or pressed on both surfaces of the insulating substrate  10  respectively, and then cured by the heating process. Alternately, a resin coating liquid may be coated on both surfaces of the insulating substrate  10  by screen printing, roller coating, or the like, and then cured by the heating process. At this time, the insulating layers  12   a ,  12   b  are formed to have the unevenness due to the influence of level differences of the projected portions  20   a ,  20   b  of the conductive parts  20 .  
         [0030]    Then, as shown in FIG. 1D, the insulating layers  12   a ,  12   b  on both surface sides of the insulating substrate  10  are ground by a predetermined film thickness respectively. Thus, the level differences due to the projected portions  20   a ,  20   b  of the conductive parts  20  are eliminated, and exposed surfaces of the insulating layers  12   a ,  12   b  are made flat. Then, remaining insulating layers  12   a ,  12   b  constitute first interlayer insulating films  14   a ,  14   b  that are flattened respectively. This step is carried out by buff polishing, belt polishing, or tape polishing, for example. The insulating layers  12   a ,  12   b  on both surface sides of the insulating substrate  10  are polished simultaneously by this step. Alternately, the insulating layers  12   a ,  12   b  may be ground by a grinder.  
         [0031]    At this time, in the first embodiment, the insulating layers  12   a ,  12   b  are polished to planarize such that the insulating layers  12   a ,  12   b  still remain on the conductive parts  20  not to expose top end surfaces of the conductive parts  20 .  
         [0032]    In the present embodiment, the conductive parts  20  itself is not polished, but merely the insulating layers  12   a ,  12   b  are polished to execute the planarization in a state that the projected portions  20   a ,  20   b  of the conductive parts  20  are covered/held with the insulating layers  12   a ,  12   b . Therefore, unlike the prior art, there is no possibility to deform the conductive parts (metal pillars)  20  or to extend the polished metal piece onto the polished surface.  
         [0033]    In case the rigid substrate such as the glass epoxy substrate, or the like is employed as the insulating substrate  10 , it is extremely difficult to planarize the insulating substrate  10  by the polishing since glass cloths are present in the substrate. However, in the present embodiment, as described above, it is not required to polish the insulating substrate  10 . Therefore, even though the glass epoxy substrate, or the like is employed, the flat surface can be obtained not to generate any trouble.  
         [0034]    As a variation of the first embodiment, as shown in FIG. 2A, a substrate having wiring layers  17   a ,  17   b  formed of a copper foil on both surfaces (or a single surface) may be employed as the insulating substrate  10 . Then, the through holes  10   a  are formed in the insulating substrate  10 .  
         [0035]    Then, as shown in FIG. 2B, in compliance with the same method as the foregoing method, the conductive parts  20  are inserted into the through holes  10   a  of the insulating substrate  10  and then fixed. At this time, the conductive parts  20  are connected electrically to the wiring layers  17   a ,  17   b  of the insulating substrate  10 . In the event that reliability of the jointing between the conductive parts  20  and the wiring layers  17   a ,  17   b  should be improved, contact areas between the conductive parts  20  and the wiring layers  17   a ,  17   b  may be increased by crashing the conductive parts  20  by means of the caulking process.  
         [0036]    Then, as shown in FIGS. 2C and 2D, the flat interlayer insulating films  14   a ,  14   b  are obtained by forming the insulating layers  12   a ,  12   b  on both surfaces of the insulating substrate  10  respectively and then polishing such insulating layers  12   a ,  12   b.    
         [0037]    In case the insulating substrate  10  having the wiring layers  17   a ,  17   b  thereon as described above is employed, the wiring layers  17   a ,  17   b  are protected by the insulating layers  12   a ,  12   b . Therefore, the wiring layers  17   a ,  17   b  are in no way damaged when such insulating layers  12   a ,  12   b  are polished to get the flat surface.  
         [0038]    After the flat first interlayer insulating films  14   a ,  14   b  are obtained as described above, as shown in FIG. 1E, portions of the first interlayer insulating films  14   a ,  14   b  on the conductive parts  20  on both surface sides of the insulating substrate  10  are worked by a laser, a plasma etching, or the like. Thus, first via holes  14   x ,  14   y  having a depth that reaches the top end surface of the conductive parts  20  are formed respectively.  
         [0039]    Then, as shown in FIG. 1F, first wiring patterns  16   a ,  16   b  connected to the conductive parts  20  respectively are formed on the first interlayer insulating films  14   a ,  14   b  on both surface sides of the insulating substrate  10  via the first via holes  14   x ,  14   y  respectively. The first wiring patterns  16   a ,  16   b  are formed by the semi-additive process, for example. In more detail, a seed Cu layer is formed on inner surfaces of the first via holes  14   x ,  14   y  on both surface sides of the insulating substrate  10  and on the first interlayer insulating films  14   a ,  14   b  by the electroless plating or the sputter respectively. Then, a resist film (not shown) having predetermined opening portions corresponding to the first wiring patterns  16   a ,  16   b  is formed by the photolithography.  
         [0040]    Then, Cu film patterns are formed in the opening portions of the resist film by the electroless plating using the seed Cu film as a plating power-supplying layer. Then, the resist film is removed, and then the seed Cu film is etched while using the Cu film patterns as a mask. Thus, the first wiring patterns  16   a ,  16   b  connected to the conductive parts  20  via the first via holes  14   x ,  14   y  are formed on the first interlayer insulating films  14   a ,  14   b  on both surface sides of the insulating substrate  10  respectively.  
         [0041]    In this case, the first wiring patterns  16   a ,  16   b  may be formed by the subtractive process, the full additive process, or the like in place of the semi-additive process.  
         [0042]    In the present embodiment, since the first interlayer insulating films  14   a ,  14   b  are made flat in the step of forming the first wiring patterns  16   a ,  16   b , a focal depth in the photolithography can be set small. Therefore, since there is no possibility to generate the defocus in the photolithography step, the first wiring patterns  16   a ,  16   b  can be formed stably with good precision.  
         [0043]    Then, as shown in FIG. 1G, second interlayer insulating films  18   a ,  18   b  are formed on both surface sides of the insulating substrate  10  respectively. Then, second via holes  18   x ,  18   y  are formed in portions of the second interlayer insulating films  18   a ,  18   b  on the first wiring patterns  16   a ,  16   b  respectively.  
         [0044]    Then, second wiring patterns  22   a ,  22   b  connected to the first wiring patterns  16   a ,  16   b  via the second via holes  18   x ,  18   y  are formed on the second interlayer insulating films  18   a ,  18   b  respectively. The second wiring patterns  22   a ,  22   b  are formed by the same method as the foregoing method used to form first wiring patterns  16   a ,  16   b.    
         [0045]    Then, as shown in FIG. 1H, solder resist films  24   a ,  24   b  in which opening portions are provided on connection portions  22   x  of the second wiring patterns  22   a ,  22   b  are formed on both surface sides of the insulating substrate  10  respectively. Then, the Ni/Au plating is applied to the connection portions  22   x  of the second wiring patterns  22   a ,  22   b . Then, when a large-size insulating substrate  10  is employed to get a plurality of wiring substrates, individual wiring substrates  1  are obtained by cutting this insulating substrate  10 .  
         [0046]    With the above, the wiring substrate  1  manufactured by the wiring substrate manufacturing method according to the first embodiment is obtained.  
         [0047]    In this case, in the present embodiment, a mode where double-layered wiring patterns are laminated on both surface sides of the insulating substrate  10  respectively is exemplified. It is of course that the present invention can be applied to various modes where n-layered (n is an integer of 1 or more) wiring patterns are laminated. In such case, since each interlayer insulating film is formed to planarize respectively, laminated wiring patterns can be formed without any trouble. Also, the wiring patterns may be laminated on one surface of the insulating substrate  10 .  
         [0048]    In the wiring substrate  1  of the present embodiment, as shown in FIG. 1I, for example, bumps  26  of a semiconductor chip  30  having the bumps  26  thereon are bonded to the connection portions  22   x  of the upper second wiring patterns  22   a . Then, the connection portions  22   x  of the lower second wiring patterns  22   b  are connected to connection terminals of a mounting substrate (mother board) via the bumps.  
         [0049]    As described above, in the wiring substrate manufacturing method according to the present embodiment, first the conductive parts  20  is inserted into the through holes  10   a  of the insulating substrate  10  in a state that such conductive parts  20  has the projected portions  20   a ,  20   b  projected from both surfaces of the insulating substrate  10 . Then, the insulating layers  12   a ,  12   b  for covering the projected portions  20   a ,  20   b  of the conductive parts  20  are formed on both surfaces of the insulating substrate  10 , and then such insulating layers  12   a ,  12   b  are polished. Thus, the first interlayer insulating films  14   a ,  14   b  whose surfaces are made flat are obtained.  
         [0050]    In the present embodiment, the projected portions  20   a ,  20   b  themselves of the conductive parts  20  are not ground to planarize, but merely the insulating layers  12   a ,  12   b  are polished in the condition that the projected portions  20   a ,  20   b  of the conductive parts  20  are covered/held with the insulating layers  12   a ,  12   b . As a result, in the step of polishing the insulating layers  12   a ,  12   b , disadvantages such as the deformation of the conductive parts (metal pillar)  20 , etc. are by no means generated, and thus the level differences due to the projected portions  20   a ,  20   b  of the conductive parts  20  can be eliminated to get the planarization.  
         [0051]    Accordingly, a precision in the photolithography can be improved when the first wiring patterns  16   a ,  16   b  connected to the conductive parts  20  are formed over the conductive parts  20 . Therefore, the fine wiring patterns can be formed with good precision and also the high-density wiring substrate can be manufactured easily.  
         [0052]    Also, since the conductive parts (metal pillar) is inserted into the through holes of the core substrate respectively, even the through holes with a high aspect ratio, that the plating or the conductive paste are difficult to fill, can make conductive both surfaces of the substrate to have a low resistance. In addition to this, since the multi-layered wiring having a stacked via structure can be formed easily by arranging via holes on the conductive parts, not only the higher density of the wirings can be easily attained but also reduction in the wiring inductance can be attained because of shorter wiring routes.  
       Second Embodiment  
       [0053]    [0053]FIGS. 3A to  3 D are sectional views showing a wiring substrate manufacturing method according to a second embodiment of the present invention. A difference of the second embodiment from the first embodiment resides in that, in the step of polishing the insulating layer, the insulating layer is polished until the top end surfaces of the conductive parts are exposed. In the second embodiment, detailed explanation of the same steps as those in the first embodiment will be omitted hereunder.  
         [0054]    In the second embodiment, first the same structure as that shown in FIG. 1C in the first embodiment is formed. In the second embodiment, in addition to the metal pillar, a conductive parts having a coaxial structure in which an insulating member is coated on an outer peripheral portion of the metal pillar, as described later in a fourth embodiment, may be employed as the conductive parts  20 . Then, the insulating layers  12   a ,  12   b  on both surface sides of the insulating substrate  10  are polished by the similar method to the first embodiment. At this time, in the second embodiment, as shown in FIG. 3A, the insulating layers  12   a ,  12   b  are polished until top end surfaces  20   c  of the conductive parts  20  are exposed. In the second embodiment, the insulating layers  12   a ,  12   b  remaining in the lateral direction of the projected portions  20   a ,  20   b  of the conductive parts  20  serve as the first interlayer insulating films  14   a ,  14   b  respectively. At this time, when metal powders are left on the first interlayer insulating films  14   a ,  14   b  by the polishing, such metal powders are removed by an etchant. Also, like the variation of the first embodiment, when the insulating substrate  10  having wiring layers (portions indicated with a broken line in FIG. 3A) is employed, there is no possibility that the wiring layers are damaged upon the polishing.  
         [0055]    Then, as shown in FIG. 3B, according to the same method as that in the first embodiment, the first wiring patterns  16   a ,  16   b  connected to the conductive parts  20  on both surface sides of the insulating substrate  10  are formed on the first interlayer insulating films  14   a ,  14   b  respectively.  
         [0056]    Then, as shown in FIG. 3C, according to the same method as that in the first embodiment, a structure in which the second wiring patterns  22   a ,  22   b  are connected to the first wiring patterns  16   a ,  16   b  via the second via holes  18   x ,  18   y  provided in the second interlayer insulating films  18   a ,  18   b  is formed.  
         [0057]    Then, as shown in FIG. 3D, the solder resist films  24   a ,  24   b  in which the opening portions are provided on the connection portions  22   x  of the second wiring patterns  22   a ,  22   b  are formed respectively. Then, the Ni/Au plating is applied to the connection portions  22   x  of the second wiring patterns  22   a ,  22   b.    
         [0058]    With the above, a wiring substrate  1   a  according to the second embodiment is obtained. The second embodiment can achieve the same advantage as the first embodiment, and can simplify manufacturing steps rather than the first embodiment and reduce a production cost because the step of forming the first via holes  14   x ,  14   y  in the first embodiment is unnecessary.  
       Third Embodiment  
       [0059]    [0059]FIGS. 4A to  4 D are sectional views showing a wiring substrate manufacturing method according to a third embodiment of the present invention. A difference of the third embodiment from the second embodiment resides in that the conductive parts are covered further with the insulating layer after the top end surfaces of the conductive parts are exposed by polishing the insulating layer. In the third embodiment, detailed explanation of the same steps as those in the first embodiment will be omitted hereunder.  
         [0060]    First, as shown in FIG. 4A, like the second embodiment, the insulating layers  12   a ,  12   b  of the structure shown in FIG. 1C are polished to expose the top end surfaces  20   c  of the conductive parts  20  in such a manner that first insulating layer  13   a ,  13   b  are left in the lateral direction of the projected portions  20   a ,  20   b  of the conductive parts  20  on both surface sides of the insulating substrate  10  respectively. In the third embodiment, in addition to the metal pillar, the conductive parts having the coaxial structure in which the insulating member is coated on the outer peripheral portion of the metal pillar may also be employed as the conductive parts  20 .  
         [0061]    Then, in the third embodiment, as shown in FIG. 4B, second insulating layers  15   a ,  15   b  (upper insulating layers) for coating the top end surfaces  20   c  of the conductive parts  20  on both surface sides of the insulating substrate  10  are formed respectively. Thus, the first interlayer insulating films  14   a ,  14   b  composed of the first insulating layers  13   a ,  13   b  and the second insulating layers  15   a ,  15   b  respectively are formed on both surface sides of the insulating substrate  10  respectively.  
         [0062]    Then, first via holes  15   x ,  15   y  are formed in portions of the second insulating layers  15   a ,  15   b  on the conductive parts  20  on both surface sides of the insulating substrate  10  respectively. Then, the first wiring patterns  16   a ,  16   b  connected to the conductive parts  20  via the first via holes  15   x ,  15   y  respectively are formed on the first interlayer insulating films  14   a ,  14   b  respectively.  
         [0063]    Then, as shown in FIG. 4C, according to the same method in the first embodiment, the structure in which the second wiring patterns  22   a ,  22   b  are connected to the first wiring patterns  16   a ,  16   b  via the second via holes  18   x ,  18   y  provided in the second interlayer insulating films  18   a ,  18   b  is formed.  
         [0064]    Then, as shown in FIG. 4D, like the first embodiment, the solder resist films  24   a ,  24   b  in which the opening portions are provided on the connection portions  22   x  of the second wiring patterns  22   a ,  22   b  are formed respectively. Then, the Ni/Au plating is applied to the connection portions  22   x  of the second wiring patterns  22   a ,  22   b.    
         [0065]    With the above, a wiring substrate  1   b  according to the third embodiment is obtained. The third embodiment can attain the similar advantages to those in the first embodiment.  
       Fourth Embodiment  
       [0066]    [0066]FIGS. 5A to  5 F are sectional views showing a wiring substrate manufacturing method according to a fourth embodiment of the present invention. A difference of the fourth embodiment from the first embodiment resides in that the conductive parts having the coaxial structure in which the insulating member is coated on the outer peripheral portion of the metal pillar may also be employed as the conductive parts.  
         [0067]    First, as shown in FIG. 5A, like the first embodiment, the insulating substrate  10  is prepared as a core substrate, and then the through holes  10   a  are formed in the insulating substrate  10 . Then, as shown in FIG. 5B, coaxial conductive parts  21  composed of a metal pillar  21   x  and an insulating member  21   y  that coats an outer peripheral portion of the metal pillar  21   x  are prepared.  
         [0068]    A length of the coaxial conductive parts  21  is set longer than a thickness of the insulating substrate  10 , like the first embodiment. Also, a diameter of the coaxial conductive parts  21  is set to respond to the through hole  10   a  in the insulating substrate  10 , a diameter of the metal pillar  21   x  is 100 to 150 μm, for example, and a thickness of the insulating member  21   y  is 40 to 60 μm, for example. The insulating member  21   y  of the coaxial conductive parts  21  is made of epoxy resin, polyimide resin, polyamide/imide resin, fluororesin, polyethylene resin, or the like. Either a single-layer insulating layer or an insulating layer formed by laminating two different insulating layers or more may be employed.  
         [0069]    Then, the coaxial conductive parts  21  is inserted into the through holes  10   a  of the insulating substrate  10  and then fixed. At this time, like the first embodiment, the coaxial conductive parts  21  is fitted into the through holes  10   a  in a state that projected portions  21   a ,  21   b  are projected to both surface sides of the insulating substrate  10 . Since the insulating member  21   y  is coated on the outer peripheral portion, the electric short-circuit can be prevented in the coaxial conductive parts  21  even though the coaxial conductive parts  21  are arranged mutually closely. Therefore, a pitch between the through holes  10   a  of the insulating substrate  10  can be set narrower than the case the conductive parts  20  made of a single body of the metal pillar are employed in the first embodiment. In this manner, the present embodiment can deal easily with the higher density of the wiring substrate by employing the coaxial conductive parts  21 .  
         [0070]    Then, as shown in FIGS. 5C and 5D, the insulating layers  12   a ,  12   b  that are formed to coat the projected portions.  21   a ,  21   b  of the coaxial conductive parts  21  on both surface sides of the insulating substrate  10  are polished by the same method as the first embodiment. Thus, the planarized first interlayer insulating films  14   a ,  14   b  are obtained.  
         [0071]    Then, as shown in FIG. 5E, the structure in which the first wiring patterns  16   a ,  16   b  are connected to the coaxial conductive parts  21  via the first via holes  14   x ,  14   y  provided in the first interlayer insulating films  14   a ,  14   b  is formed by the same method as the first embodiment.  
         [0072]    Then, as shown in FIG. 5F, the structure in which the second wiring patterns  22   a ,  22   b  are connected to the first wiring patterns  16   a ,  16   b  via the second via holes  18   x ,  18   y  provided in the second interlayer insulating films  18   a ,  18   b  is formed by the same method as the first embodiment.  
         [0073]    Then, like the first embodiment, the solder resist films  24   a ,  24   b  in which the opening portions are provided on the connection portions  22   x  of the second wiring patterns  22   a ,  22   b  are formed respectively. Then, the Ni/Au plating is applied to the connection portions  22   x  of the second wiring patterns  22   a ,  22   b.    
         [0074]    With the above, a wiring substrate  1   c  according to the fourth embodiment is obtained. The fourth embodiment can attain the same advantages as the first embodiment and also can deal easily with the higher density of the wiring substrate since the coaxial conductive parts  21  is employed as above.  
       Fifth Embodiment  
       [0075]    [0075]FIGS. 6A to  6 F are sectional views showing a wiring substrate manufacturing method according to a fifth embodiment of the present invention. A difference of the fifth embodiment from the first embodiment resides in that the same coaxial conductive parts as that in the fourth embodiment is employed and a substrate using a metal plate as a base is employed as the core substrate.  
         [0076]    First, as shown in FIG. 6A, a metal base substrate  11  consisting of a lower insulating layer  11   x , a metal plate  11   y , and an upper insulating layer  11   z  is prepared, and then through holes  11   a  are formed in the metal base substrate  11 . For example, thicknesses of the lower insulating layer  11   x  and the upper insulating layer  11   z  are set to about 100 μm respectively, and a thickness of the metal plate  11   y  is set to about 200 μm. A resin film, or the like is employed as the lower insulating layer  11   x  and the upper insulating layer  11   z,  and a copper plate, an alloy plate consisting of iron (Fe)-nickel (Ni), or the like is employed as the metal plate  11   y.  In this case, a single body of the metal plate onto which the insulating layer is not pasted may be employed instead of the metal base substrate  11 .  
         [0077]    Then, as shown in FIG. 6B, like the fourth embodiment, the coaxial conductive parts  21  composed of the metal pillar  21   x  and the insulating member  21   y  that coats the outer peripheral portion of the metal pillar  21   x  are prepared. A length of the coaxial conductive parts  21  is set longer than a thickness of the metal base substrate  11 .  
         [0078]    Then, the coaxial conductive parts  21  is inserted into the through holes  11   a  of metal base substrate  11  and then fixed. At this time, the coaxial conductive parts  21  is fitted into the through holes  11   a  in a state that the projected portions  21   a ,  21   b  are protruded from both surface sides of the metal base substrate  11 . Also at this time, since the coaxial conductive parts  21  has the insulating member  21   y  on the outer peripheral portion, a plurality of coaxial conductive parts  21  are never short-circuited electrically mutually via the metal plate  11   y  of the metal base substrate  11 , and plural coaxial conductive parts  21  are isolated mutually.  
         [0079]    Then, as shown in FIGS. 6C and 6D, the insulating layers  12   a ,  12   b  formed to coat the projected portions  21   a ,  21   b  of the coaxial conductive parts  21  on both surface sides of the metal base substrate  11  are polished by the same method as the first embodiment. Thus, the first interlayer insulating films  14   a ,  14   b  whose surfaces are planarized are obtained.  
         [0080]    Then, as shown in FIG. 6E, the structure in which the first wiring patterns  16   a ,  16   b  are connected to the coaxial conductive parts  21  via the first via holes  14   x ,  14   y  provided in the first interlayer insulating films  14   a ,  14   b  is formed by the same method as the first embodiment.  
         [0081]    Then, as shown in FIG. 6F, the structure in which the second wiring patterns  22   a ,  22   b  are connected to the first wiring patterns  16   a ,  16   b  via the second via holes  18   x ,  18   y  provided in the second interlayer insulating films  18   a ,  18   b  is formed by the same method as the first embodiment.  
         [0082]    Then, like the first embodiment, the solder resist films  24   a ,  24   b  in which the opening portions are provided on the connection portions  22   x  of the second wiring patterns  22   a ,  22   b  are formed respectively. Then, the Ni/Au plating is applied to the connection portions  22   x  of the second wiring patterns  22   a ,  22   b.    
         [0083]    With the above, a wiring substrate  1   d  according to the fifth embodiment is obtained. The fifth embodiment can achieve the same advantages as the first and fourth embodiments. In addition to this, since the metal base substrate (or the metal substrate) can be employed as the core substrate by employing the coaxial conductive parts  21 , such metal base substrate can improve various characteristics such as rigidity, thermal conductance, electromagnetic shielding, workability, etc. more advantageously than the insulating substrate.