Abstract:
A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention is directed to semiconductor device assembly and, more particularly, to a lead frame with corner tie bars used in the assembly process. 
         [0002]    Semiconductor device packaging fulfills basic functions such as providing electric connections and protecting the die against mechanical and environmental stresses. An assembled semiconductor device has exposed electrical contacts and may be mounted on a support, such as a printed circuit board (PCB), for example, where the exposed electrical contacts are connected to external electronic circuits on the support. Using surface mount technology, the exposed electrical contacts of the device can be soldered directly to corresponding electrical contact pads on the support, providing mechanical attachment as well as electrical connections. 
         [0003]    Semiconductor devices are commonly packaged for surface mounting by encapsulating one or more semiconductor dies in a mold compound. The encapsulation process embeds the die or dies within the molding compound. Various techniques are available for connecting the exposed electrical contacts of the device internally with electrical contact pads on the embedded semiconductor die, e.g., wire bonding. 
         [0004]    The semiconductor device commonly has an electrically and thermally conductive metal flag (also called a die pad or paddle), which assists in cooling the device when it is being used (i.e., in operation), whether or not the flag is exposed at the surface of the encapsulation, The flag also may provide an electrical ground connection to the semiconductor die. It is common to facilitate manufacturing operations by performing many of the operations on an array of the semiconductor dies mounted on an array of flags that are linked together, the links being severed during a singulation operation. The links are typically provided by a frame structure, i.e., a lead frame array, which has an array of the flags connected by tie bars to frame members that are removed by being cut off and discarded during the singulation process. The frame structure also includes sets of the exposed electrical contacts that are supported by and integral with the frame members, until the devices are encapsulated and the frame members removed during singulation to isolate the electrical contact surfaces or leads from each other. This technique is applicable to devices where the sets of electrical contacts are disposed at the periphery of the flag and the semiconductor die, on two opposite sides or around all four sides. 
         [0005]    In one type of surface mount semiconductor device, the flag is exposed at its bottom face but in another type the flag as well as the die are embedded in the encapsulation. In one type of package, known as Quad Flat No-lead (QFN), the exposed contacts are positioned in the bottom face of the encapsulation at its edge surface. In another type of package, known as Quad Flat Package (QFP), the exposed contacts are leads that project outward from the edge surface of the encapsulation. 
         [0006]    In a wire bond package, the back face of the semiconductor die is mounted on a flag and the contact pads of the semiconductor die on its active face are connected to the exposed electrical contacts of the package with bond wires. A concern is to reduce movement of the bond wires due to flow of the liquid or semi-liquid molding compound during encapsulation (known as wire sweep). Such movement can result in excessive proximity of adjacent bond wires, resulting in excessive or variable mutual inductance, or even short circuits between two bond wires. 
         [0007]    Continued reduction in the size of semiconductor devices and increases in their complexity results in an increase in the number of exposed electrical contacts of the devices and a reduction in the spacing between the electrical contacts and the spacing between the bond wires. It would be desirable to have more exposed electrical contacts, yet also to reduce the effects of wire sweep. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The present invention is illustrated by way of example and is not limited by embodiments thereof shown in the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
           [0009]      FIG. 1  is a schematic plan view of a conventional quad flat package semiconductor device; 
           [0010]      FIG. 2  is a schematic plan view of a quad flat package semiconductor device in accordance with an embodiment of the invention, given by way of example; 
           [0011]      FIG. 3  is a schematic section of the semiconductor device of  FIG. 2  along the line  3 - 3 ; 
           [0012]      FIG. 4  is a schematic section similar to  FIG. 3  along the line  3 - 3  of the semiconductor device of  FIG. 2  mounted on a printed circuit board; 
           [0013]      FIG. 5  is a schematic section of the semiconductor device of  FIG. 2  along the line  5 - 5 ; 
           [0014]      FIG. 6  is a schematic section similar to  FIG. 5  along the line  5 - 5  of  FIG. 2  of the semiconductor device of  FIG. 2  mounted on a printed circuit board; 
           [0015]      FIG. 7  is a plan view of part of a lead frame structure with encapsulated semiconductor devices used in making the semiconductor device of  FIG. 2 ; and 
           [0016]      FIG. 8  is a flow chart of a method in accordance with an embodiment of the invention of making a quad flat package semiconductor device such as the semiconductor device of  FIGS. 2 to 6 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]      FIG. 1  illustrates a conventional quad flat package (QFP) semiconductor device  100 . The semiconductor device  100  comprises one or more semiconductor dies  102  mounted on an electrically and thermally conductive flag (or die pad or paddle)  104 . The die  102  and the flag  104  are embedded in a molding compound or encapsulation  106  having top and bottom faces and an edge surface. The die  102  and flag  104  are shown in dashed lines. A set of exposed electrical leads  108  are connected with internal electrical contacts (not shown) on an active face of the die  102 , the electrical leads  108  being supported by the encapsulation  106  and projecting from the edge surface for connection to an external electrical circuit. 
         [0018]    The semiconductor device  100  is of the non-exposed pad type, in which the flag  104  is embedded in the encapsulation  106  and is not exposed in the bottom face of the encapsulation  106 . Accordingly, power ground connections cannot be made directly to the flag  104  and one or more of the leads  108  are used for the power ground connection between the die  102  and the external circuit to which it will be connected. This reduces the number of the leads  108  available for signal connections. Moreover, the resistance of the power ground connection between the die  102  and the external circuit through the lead  102  and the internal connection produces an undesirable voltage drop due to the power current flowing. 
         [0019]      FIGS. 2 to 6  illustrate a surface mount semiconductor device  200  in accordance with an embodiment of the present invention, given by way of example. The semiconductor device  200  comprises an electrically and thermally conductive flag  202  having corners and tie bars  204  extending from the corners. The semiconductor device  200  also comprises at least one semiconductor die  102  having an active face with internal electrical contacts (not shown), and a back face opposite the active face mounted on the flag  202 , the die and flag again being shown in dashed lines. The die  102  and the flag  202  are embedded in an encapsulation  106  having top and bottom faces  300  and  302  and an edge surface  304  (shown in  FIGS. 3 to 6 ). A set of exposed electrical leads  108  are connected with the internal electrical contacts. The electrical leads  108  are supported by the encapsulation  106  and project from the edge surface  304  for connection to an external electrical circuit  400  (shown in  FIGS. 4 and 6 ). The semiconductor die  102  has a power ground connection through at least one of the tie bars  204 , which is exposed as a power ground lead for the semiconductor die  102  and projects from the edge surface  204  for connection to the external electrical circuit  400 . 
         [0020]    Using the tie bars  204  as a power ground lead for the flag  202  and the semiconductor die  102  frees all the leads  108  for signal connections and the power voltage supply. The resistance of the power ground connection can be reduced, since the tie bars  204  can have a greater width than the leads  108 , and since more than one of the tie bars  204  can be used as a power ground lead. 
         [0021]    The internal electrical contacts and the electrical leads  108  may be connected by bond wires  306  bonded to the internal contacts and to the leads. In one example of an embodiment of the invention, the power ground connection includes at least one bond wire  206  connecting at least mechanically the semiconductor die  102  with the tie bar  204  which is exposed as a power ground lead. The tie bar  204  of the power connection and the bond wire  206  connected thereto extend diagonally out from the flag  202  and from the semiconductor die  102 . In another example of an embodiment of the invention, the power ground connection includes at least one bond wire  208  connecting the semiconductor die  102  with the flag  104 , the flag  104  connecting with at least one of the tie bars  204 , which is exposed as a power ground lead. Bond wires  206  connect the tie bar  204  of the power connection at least mechanically with the semiconductor die  102 , the tie bar  204  of the power connection and the bond wires  206  connected thereto extending diagonally out from the flag  104  and from the semiconductor die  102 . 
         [0022]    The edge surface  304  of the encapsulation  106  may be generally rectangular and have four corners, and the tie bar  204 , which is exposed as a power ground lead may project from a corner of the edge surface  304  of the encapsulation  106 . The edge surface  304  of the encapsulation  106  may be generally rectangular and have four corners with four of the tie bars  204  projecting from each of the corners of the edge surface  304  respectively as an electrical lead for the flag, and the power ground connection for the semiconductor die may include all four of the tie bars. 
         [0023]    The electrical leads  108  and the tie bar  204 , which is exposed as an electrical lead, may extend out from an intermediate level of the edge surface  304  and down to the level of the bottom face  302 . The semiconductor device  100  illustrated is a QFP device in which the exposed electrical leads  108  are of gull-wing shape. It will be appreciated that this example of an embodiment of the invention is also applicable to other types of semiconductor device such as small outline integrated circuits (SOICs), thin small outline packages (TSOP), plastic leaded chip package (PLCC) devices, and small outline J-lead (SOJ) devices. 
         [0024]      FIG. 8  illustrates steps in a method  800  in accordance with an embodiment of the invention, given by way of example, of making a surface mount semiconductor devices, such as the semiconductor devices  200  of  FIGS. 2 to 6 . The method  800  comprises providing a frame structure  700  (shown in  FIG. 7 ) including frame members  702 , an array of electrically and thermally conductive flags  202  having corners, and tie bars  204  extending from the corners supporting the flags  202  from the frame members  702 . Sets of electrical leads  108  are provided. An array of semiconductor dies  102  each having an active face with internal electrical contacts, and a back face opposite the active face are mounted with the back faces of the semiconductor dies on the array of flags  202 . The internal electrical contacts are connected electrically with the electrical leads  108 . Power ground connections are provided for the semiconductor dies  102  through the tie bars  204 . Encapsulations  106  having top and bottom faces  300  and  302  and edge surfaces  304  are formed, the semiconductor dies  102  and the flags  202  being embedded within the encapsulations  106 , and the electrical leads  108  and at the tie bars  204  of the power ground connections projecting from the edge surfaces  304  and being exposed for connection to external electrical circuits  400 . Singulating the semiconductor devices  200 , includes removing the frame members  702 . 
         [0025]    Providing the frame structure  700  may include providing the external electrical leads  108  supported by the frame members  702 . Connecting the internal electrical contacts electrically with the electrical leads  108  may include electrically connecting sets of bond wires  306  between the internal electrical contacts and the electrical leads  108 . 
         [0026]    Bond wires  206  may be connected at least mechanically between the semiconductor dies  102  and the tie bars  204  of the power ground connections. The tie bars  204  of the power ground connections and the bond wires  206  connected thereto may extend diagonally out from the flags  202  and from the semiconductor dies  102 , and forming the encapsulations  106  may include injecting molding compound into a mold from positions in central parts of the top and/or bottom faces  300 ,  302 . In one example, the edge surfaces  304  of the encapsulations  106  are generally rectangular and each present four corners with four of the tie bars  204  projecting from the corners of the edge surfaces  304  as power ground leads for the semiconductor dies  102 , and bond wires  206  are connected at least mechanically between the semiconductor dies  102  and each of the four tie bars  204 . Injection of the molding compound produces less wire sweep of the bond wires  206  because the flow of the molding compound from its central injection position is along the bond wires in the corners, rather than being across the bond wires. 
         [0027]    In another example, the tie bars  204  of the power connections and the bond wires  206  connected thereto extend diagonally out from the flags  202  and from the semiconductor dies  102 , the edge surfaces of the encapsulations  106  are generally rectangular and each presents a first corner and three further corners, with the tie bars  204  projecting from each of the three further corners of the edge surfaces  304  as power ground leads for the flags  202 , bond wires  206  are connected at least mechanically between the semiconductor dies  102  and the three tie bars  204  respectively, and forming the encapsulations  106  includes injecting molding compound into a mold from positions adjacent the first corners in the top and/or bottom faces  300 ,  302 . Again, wire sweep of the bond wires  206  is limited because the flow of the molding compound from its injection position in the first corner is remote from the bond wires in the further corners, and not directly across the bond wires. 
         [0028]    The power ground connections may include bond wires  208  connecting the semiconductor dies  102  with the flags  104 , the flags  104  connecting with at least one of the tie bars  204  of the power ground connections. The tie bars  204  of the power ground connections and the bond wires  206  connected thereto may extend diagonally out from the flag  104  and from the semiconductor die  102 . Wire sweep of the bond wires  208  is less than the bond wires connecting to the leads  108 , since they are shorter, only extending as far as the sides of the flags  104 . In another example of an embodiment of the invention, the bond wires  206  connecting to the tie bars  204  are omitted and, in use, all the power ground current passes through the bond wires  208 , the flag  104  and the tie bars  204 . 
         [0029]    However, it has been found that flow of the molding compound at the corners of the die  102 , the flag  104  and the mold during encapsulation is less irregular, and less likely to jerk the bond wires  306  when the corner bond wires  206  are present. In yet another example of an embodiment of the invention, the bond wires  206  connect at least mechanically to the tie bars  204  in addition to the bond wires  208  connecting the semiconductor dies  102  electrically with the flags  104 . It is not always convenient to make internal power ground connections within the semiconductor die  102  to bond pads located at the corners of the die. In a variant of this example of an embodiment of the invention, the bond wires  206  are bonded to dummy bond pads, which do not carry power ground current, at the corners of the dies  102  and to the tie bars  204 , but reduce the impact of the force from mold compound flow at the corners on the bond wires  306 . 
         [0030]    The method  800  may include shaping the electrical leads  108  and the tie bars  204  which are exposed for connection to the external electrical circuits  400  to extend out from an intermediate level of the edge surfaces  304  and down to the level of the bottom faces  302 . 
         [0031]    In more detail, as shown in  FIGS. 4 and 6 , the completed device, as shown in  FIGS. 2 ,  3  and  5  may be mounted in use on the external PCB  400 . The leads  108  are soldered to contacts  402  on the PCB  400  and the tie bars  204  are soldered to contacts  404  on the PCB  400  as power ground leads. 
         [0032]      FIG. 7  illustrates a stage in the production of an array of the semiconductor devices  200  after encapsulation, but before trim and form operations result in singulation. The tie bars  204  extend between the corners of the flags  202  and the adjacent corners between two frame members  702  of the lead frame structure  700  and support the array of flags and of semiconductor dies during manufacturing manipulations until and including encapsulation. The tie bars  204  are shaped as elongate leads of greater width than the leads  108 , to reduce their electrical resistance. The support that the tie bars  204  provide is reinforced by lateral supports, in this example in the shape of fingers such as  704 , which supplement the mechanical connection of the tie bars to the frame members  702 . During singulation, the frame members  702  of the lead frame structure  700  are cut off along singulation streets  706  (shown in chain-dotted lines), for example by sawing, punching or selectively etching, and are discarded. The tie bars  204  are not cut off, as they are in the conventional semiconductor devices  100 , but the reinforcement fingers  704  are cut off as indicated at  708  (in chain-dotted lines) and discarded. Dam bars (or rails)  710  connect the leads  108  to reinforce the frame structure and reduce movement of the inner ends of the leads  108  before and during encapsulation. The dam bars  710  are trimmed off in the same operations as the frame members  702  and the lateral fingers  704 . After singulation, while the semiconductor devices  200  are still positioned in array, the leads  108  and the tie bars  204  are formed into gull-wing shape by a press tool. 
         [0033]      FIG. 8  illustrates a summary of the method  800 . The method starts at  802 . At  804 , the frame structure  700  is provided, including the frame members  702  supporting the array of electrically and thermally conductive flags  202 . The sets of electrical leads  108  are provided at  806 , integral with, and supported by the frame members  702  in the example illustrated of the frame structure  700 . At  808 , the array of semiconductor dies  102  is mounted on the array of flags  202 . The internal contacts on the active faces of the dies  102  are connected by the bond wires  306  to the leads  108  at  810 . At  812 , power ground connections are made from the semiconductor dies  102  to the tie bars  204  by bond wires  206 . 
         [0034]    At  814 , the individual semiconductor devices  200  are encapsulated, with the semiconductor dies  102 , the flags  202  and the bond wires  206  and  306  embedded within the encapsulations  106 , and with the electrical leads  108  and the tie bars  204  projecting from the edge surfaces  304  and exposed for connection to external electrical circuits  400 . Singulating the semiconductor devices  200  is performed at  816 , including removing the frame members  702  and the fingers  704  but leaving the tie bars  204  as power ground connections. The method ends at  818 , with the resulting semiconductor devices  200  ready for use. 
         [0035]    In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. 
         [0036]    For example, the semiconductor die described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. 
         [0037]    Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. 
         [0038]    The connections as discussed herein may be any type of connection suitable to transfer signals or power from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, a plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. 
         [0039]    Furthermore, those skilled in the art will recognize that boundaries between the above described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. 
         [0040]    In the claims, the word ‘comprising’ or ‘having’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.