Abstract:
Apparatus and methods for wave reversing in a travelling wave oscillator are disclosed. The travelling wave oscillator includes a differential transmission line and regeneration elements connected along the differential transmission line. The differential transmission line can be used to propagate a wave traveling in either a counterclockwise or a clockwise direction. Each of the regeneration elements includes a first gain portion operable to degenerate a wave travelling in the counterclockwise direction and to regenerate a wave travelling the clockwise direction, and a second gain portion operable to degenerate a wave travelling in a clockwise direction and to regenerate a wave travelling in a counterclockwise direction.

Description:
BACKGROUND 
       [0001]    A rotary traveling wave oscillator is described in U.S. Pat. No. 6,556,089, which is incorporated by reference into the present application. In that patent, a wavefront moves around a closed, differential loop, reversing its polarity in each transit of the loop. The wavefront traveling on the loop is established and maintained by a plurality of regeneration elements, such as back-to-back inverters, distributed about the entire loop, in one embodiment.  FIG. 1  shows an embodiment  10  of a back-to-back inverter  12 ,  14 . The result of this arrangement is that at any point on the differential loop, a differential clock signal is available. The frequency of the clock signal is determined by the electrical size of the loop, by which is meant the time it takes to make a lapse around the loop, given the loop&#39;s loaded transmission line characteristics. 
         [0002]    PCT/GB01/02069, which is incorporated by reference into the present application, describes an embodiment, shown in  FIG. 12B , in which circuitry biases the wave so that it travels in a preferred direction, either clockwise or counter clockwise. According to this application, the direction of the traveling wave is not changeable once the wave had been established on the loop. See PCT/GB01/02069, page 7, lines 24-25. That is, to change the direction of the wave, one would have to cycle power the loop and re-start the wave in the opposite direction. While this startup circuitry accomplishes the function of assuring that the traveling wave moves in a preferred direction, it would be desirable to establish the direction of the traveling wave without cycling power the loop, i.e., to change the direction of the wave in real time. 
       SUMMARY OF INVENTION 
       [0003]    The present invention, in one embodiment, is directed towards circuitry that can change the direction of the traveling wave on the rotary oscillator without having to power down the loop, in effect, changing the direction of the wave in real time, i.e., while the wave is traveling in either one of the directions. The present invention includes one or more regeneration/degeneration elements, each of which includes circuitry for regenerating or degenerating a wave traveling in a particular direction. The new regeneration/degeneration elements employ a positive resistance to degenerate a wave traveling in a particular direction and negative resistance to establish and maintain the wave in the opposite direction. 
         [0004]    The present invention in another embodiment is directed towards circuitry that can establish a wave on a rotary oscillator traveling in a preferred direction. The present invention includes one or more regeneration/degeneration elements, each of which includes circuitry for regenerating a wave traveling in the preferred direction and degenerating a wave traveling opposite to the preferred direction. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0005]    These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
           [0006]      FIG. 1  shows a prior art circuit for a regeneration device; 
           [0007]      FIG. 2A  shows a simplified diagram of the rotary traveling wave oscillator; 
           [0008]      FIGS. 2B and 2C  are timing diagrams that illustrate cases of regeneration and degeneration of a traveling wave; 
           [0009]      FIG. 3  shows a simplified diagram of an embodiment of the present invention; 
           [0010]      FIG. 4  shows a more detailed schematic of an embodiment of the present invention; 
           [0011]      FIG. 5  is an outline diagram for a transmission-line structure hereof; 
           [0012]      FIG. 6  shows a Moebius strip; 
           [0013]      FIG. 7  is an outline circuit diagram for a traveling wave oscillator hereof; 
           [0014]      FIG. 8  is another outline circuit diagram for a traveling wave oscillator hereof; and 
           [0015]      FIGS. 9   a  and  9   b  are equivalent circuits for distributed electrical models of a portion of a transmission-line hereof; 
           [0016]      FIG. 10  shows a pair of back-to-back inverters connected across part of a transmission-line; and 
           [0017]      FIGS. 11   a  and  11   b  are outline and equivalent circuit diagrams of CMOS back-to-back inverters. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]      FIG. 2A  shows a simplified diagram of the rotary traveling wave oscillator  20 . The oscillator  20  includes one or more regeneration/degeneration elements (shown in  FIG. 7 ) and a crossover CO  22 , which reverses the polarity of a differential wave traveling on the conductors of the oscillator. The figure also shows two points T 1   24  and T 2   26  at which the conductors of the oscillator are tapped by a representative regeneration/degeneration element (“redegen” element). 
         [0019]    In the discussion that follows, a convention for naming the wavefront is helpful. The relatively more positive wavefront is named the 0 degree wavefront, so that 180 degrees is the relatively more negative wavefront. A traveling wave thus has the following wavefronts that travel past a specific point, 0, 90, 180, 270, 360. 
         [0020]      FIGS. 2B and 2C  are timing diagrams that illustrate the cases in which regeneration or degeneration of a wave occurs.  FIG. 2B  shows the cases where there is regeneration and  FIG. 2C  shows the cases where there is degeneration. 
         [0021]    Regeneration occurs, as illustrated in  FIG. 2B , when the wave at Ti is  180  degrees out of phase with the wave at T 2 . There are two cases. The first case occurs when a 0 degree T 2  wavefront at T 2  has traveled 90 degrees from the 0 degree wavefront at T 1 , and a 90 degree external delay is added. The second case occurs when a 180 degree wavefront at T 2  wave has traveled 270 degrees from the 180 degree wavefront at T 1  wave, and a 90 degrees external delay is added. These two conditions, R 1  and R 2  in  FIG. 2B , are expressed as follows, R 1 (0+{right arrow over (90)},+90), R 2 (180+{right arrow over (270)},+90), where the arrow indicates a delay caused by the travel of the wave and the +90 indicate a delay caused by delay external to the oscillator. 
         [0022]    Degeneration occurs, as illustrated in  FIG. 2C , when the wave at T 1  is in phase with the wave at T 2 . Again, there are two cases to consider. In the first case, a 0 degree wavefront at T 2  wave has traveled 270 degrees from the 0 degree wavefront at T 1  wave, and a 90 degree delay is added. In the second case, the 180 degree wavefront at T 2  has traveled 90 degrees from the 180 degree wavefront at T 1 , and a 90 degree delay is added. These two conditions D 1 , D 2 , are expressed as D 1 (0+{right arrow over (270)},+90), D 2 (180+{right arrow over (90)},+90). 
         [0023]      FIG. 3  shows a simplified diagram of a representative regeneration/degeneration element  30  of the present invention. In this element, there is a pair of load devices  32 , such as PFETs P 1   34  and P 2   36  that are cross-coupled to each other, and two pairs  38 ,  40  of transistors on either side of the load devices  32 . Alternatively, the load devices  32  can be resistors, NMOS devices with resistive loading, or NMOS devices with PMOS diodes. Active load devices need only to provide a gain over a phase range of 0 to 180 degrees. The transistor pairs  38 ,  40  are connected to the A and B conductors at the same tap point (T 1 )  42  as the load devices. 
         [0024]    The right side transistor pair  40  is configured to supply energy to a wave traveling in the clockwise direction (to the right in the figure), and to remove energy from a wave traveling in the counter clockwise direction (to the left in the figure). The left side transistor pair  38  is configured to supply energy to a wave traveling in the counter clockwise direction (to the left in the figure) and to remove energy from a wave traveling in the clockwise direction. The operation of each pair is selectable by an enable signal EN  44 ,  46 . Only one pair is operative at a time. 
         [0025]    The right side pair of transistors includes two NFETs N 1 A  48  and N 2 A  50 . The first NFET N 1 A  48  has its gate connected to T 1 A, which is the A conductor at tap point T 1   42 , and its drain connected to T 1 B, the B conductor at the T 1   42  tap point. The second NFET N 2 A  50  has its drain connected to T 1 A and its gate connected to T 2 A. When the wave travels to the right, the T 2 A point is 90 degrees away (later) from the T 1 A point and when the wave travels to the left, the T 2 A point is  270  degrees away from the T 1 A point. The sources of N 1 A  48  and N 2 A  50  are connected to a switch SWA  52  that connects, when closed, each of the drains to a current source, I 1 A  54 , I 2 A  56 . The switch SWA  52  has an enable input ENA  46  that makes the right side pair  40  operative. A capacitor CA  58  is connected between the two current sources  54 ,  56  and, in combination with the transistors N 1 A  48  and N 2 A  50 , creates a 90 degree delay to full conduction of the N 2 A  50  FET. The capacitor  58  itself provides a 45 degree delay and the timing of the signals connected to the gates of T 1 A and T 2 A provides an additional 45 degrees, for a total of 90 degrees. 
         [0026]    The left side pair  38  includes two NFETS N 1 B  62 , N 2 B  64 . The first NFET N 1 B  64  has its gate connected to T 1 B conductor and its drain connected to the T 1 A conductor. The second NFET N 2 B  62  has its drain connected to T 1 B conductor and its gate connected to the T 2 B conductor. When the wave travels to the left, the T 2 B point is  270  degrees delayed from the T 1 B point, because it travels past the crossover CO  22  in  FIG. 2A . When the wave travels to the right, the T 2 B point is 90 degrees delayed from the T 1 B point. The sources of the NFETS are connected to a switch SWB  66  that connects, when closed, each of the drains to a current source I 1 B  68 , I 2 B  70 . The switch SWB  66  has an enable input ENB  44  that makes the left side pair  38  operative. A capacitor CB  72  is connected between the two current sources  68 ,  70  and in combination with the transistors N 1 B  64  and N 2 B  62  creates a 90 degree delay to full conduction of the N 2 B  62  FET. The capacitor  72  itself provides a 45 degree delay and the timing of the gate signals provides an additional 45 degrees, for a total of 90 degrees. 
         [0027]    For the operation of the right side pair  40  of transistors, there are two cases to consider, R 1 (0+{right arrow over (90)},+90) and D 1 (0+{right arrow over (270)},+90). For the operation of the left side pair  38  of transistors, the two cases are R 2 (180+{right arrow over (270)},+90) and D 2 (180+{right arrow over (90)},+90). 
         [0028]    In the R 1 (0+{right arrow over (90)},+90) case, with the 0 degree wavefront traveling clockwise (not passing the crossover), the N 2 A  50  transistor provides energy to the traveling wave. This occurs because the drain of the N 2 A transistor is connected to T 1  while the gate is connected to T 2 , thereby making the drain relatively more negative than the gate. The current source I 2 A  56  is thus connected via N 2 A to the negative side of the wave so that it makes the negative side more negative, thereby adding to the energy of the wave. 
         [0029]    In the D 1 (0+{right arrow over (270)},+90) case, with the 0 degree wavefront traveling counter clockwise (passing the crossover), the N 2 A  50  transistor takes energy from the traveling wave. This occurs because the drain and gate are at the same potential. The current source I 2 A  56  is thus connected via N 2 A  50  to the more positive side of the wave so that it makes the positive side more negative, thereby removing energy from the wave. 
         [0030]    In the R 2 (180+{right arrow over (270)},+90) case, with the 180 degree wavefront traveling counter clockwise (passing the crossover), the N 2 B transistor  62  provides energy to the traveling wave. This occurs because the drain of N 2 B  62  is connected to T 1  while the gate is connected to T 2 , thereby making the drain relatively more negative than the gate. The I 2 B current source  68  is thus connected via N 2 B  62  to the relatively more negative side of the wave, so that it adds energy to the wave. 
         [0031]    In D 2 (180+{right arrow over (90)},+90) case, with the 180 degree wavefront traveling clockwise, the N 2 B  62  transistor removes energy from the traveling wave. This occurs because the drain and gate of N 2 B  62  are at the same potential (both relatively positive). The current source  12 B  68  is connected via N 2 B  62  to the more positive side of the wave so that it makes this side of the wave more negative, thereby removing energy from the wave. 
         [0032]    In the D 1  and D 2  cases, the degeneration of the wave is greater than any regeneration of the wave provided by the load devices and the wave thus decays to the point where no wave traveling in the direction for which degeneration occurs. As mentioned above, the degeneration is greater because the NMOS transistor N 1 B  64  or N 2 B  62  is stronger than either of the PMOS transistors  34 ,  36 . 
         [0033]    A wave traveling on the rotary traveling wave oscillator may be reversed. If a wave is traveling in the clockwise direction, according to R 1 , and it is desired to have the wave travel in the counter clockwise direction, then the right side pair  40  is turned off and the left side pair  38  is turned on. This, in effect, causes a change from the R 1  case to the D 2  case, and then to the R 2  case. The wave traveling in the clockwise direction is degenerated according to the D 2  case, and a new wave starts in the counter clockwise direction according to case R 2 . 
         [0034]    Alternatively, if the wave is traveling in the counter clockwise direction, according to the R 2  case and it is desired to have the wave travel in the clockwise direction, then the left side pair  38  is turned off and the right side pair  40  is turned on. This causes a change from the R 2  to the D 1  case, and then to the R 1  case. The change from the R 2  case to the D 1  case degenerates the wave and a new wave starts in the clockwise direction according to the R 1  case. 
         [0035]    Alternatively, it is possible to establish a wave traveling in a preferred direction. 
         [0036]    If only one of the transistor pairs is present, a wave can be established in a preferred direction by the pair that is present. If the right side pair  40  is present, the pair  40  establishes a traveling wave in the clockwise direction. If the left side pair  38  is present, the pair  38  establishes a traveling wave in the counterclockwise direction. 
         [0037]      FIG. 4  shows a more detailed diagram of the new wave reversing elements. In this figure, the rotary clock has an exemplary gain stage connected between the T 1  point and the T 2  point. The rotary clock has a single crossover shown between T 1  and T 2 . The T 2  A and B points may be slightly different from 90/270 degrees to compensate for any parasitic capacitances in the circuit. 
         [0038]    The exemplary gain stage  80  shown in the figure represents one or more gain stages connected in a similar fashion to the rotary oscillator. The exemplary gain stage  80  has an expanded version shown in the inset  82  and includes the P 1   84  and P 2   86  FETs, a gain stage portion G 1   88  connected to the A and B conductors of the T 1  tap  90  and to the A conductor of the T 2  tap  92 , a gain stage portion G 2   94  connected to the Ti tap  90  and to the B conductor of the T 2  tap  92 , and a pair of varactors  96 ,  98  connected to the T 1 A and T 1 B points for tuning the oscillator. The P 1   84  and P 2   86  FETs are connected in a cross-coupled fashion and switch when the traveling wave arrives at the T 1  tap  90 . The G 1  stage  88  includes N 1 A  100  and N 2 A  102  transistors, an enabling switch SWA  104 , the HA  106  and I 2 A  108  current sources and the capacitor C 3 A  110 . The G 2  stage  94  includes N 1 B  112  and NIB  114  transistors, an enabling switch SWB  116 , the I 1 B  118  and I 2 B  120  current sources, and the capacitor C 3 B  122 . The P 1  and P 2   84 ,  86  transistors are weaker than the N 1 B  114  and N 2 B  112  transistors, so that the degeneration of an existing wave is possible. In one embodiment, the transistors are ⅓ weaker than the NIB  114  and N 2 B  112  transistors. 
         [0039]    The SWA  104  and SWB  116  switches include a pair of NFET transistors whose gates are connected to enable signals, ENA  126  and ENB  124 , respectively. In one embodiment, the enable signal ENA  126  of the SWA  104  switch is the inversion of the enable signal ENB  124  of the SWB  116  switch. The current sources  106 ,  108 ,  118 ,  120  are implemented with NFETs and a voltage vb 2 , vb 3  biases these NFETs for constant current. The capacitors C 3 A  110  and C 3 B  122  are sized to delay the turning on of either the N 2 A  100  and N 2 B  112  transistors by 45 degrees in addition to the  45  degree delay caused by the gates being out of phase by 90 degrees. The varactors  96 ,  98  connected at the T 1  tap point are both connected to a V TUNE  voltage  130 . This helps to adjust the frequency of the rotary oscillator. Operation of  FIG. 4  is substantially the same as that described in relation to  FIG. 3 . 
       Rotary Traveling Wave Oscillator 
       [0040]      FIG. 5  shows such a transmission-line  15  as a structure that is further seen as physically endless, specifically comprising a single continuous “originating” conductor formation  217  shown forming two appropriately spaced generally parallel traces as loops  215   a ,  215   b  with a cross-over at  219  that does not involve any local electrical connection of the conductor  217 . Herein, the length of the originating conductor  217  is taken as S, and corresponds to two ‘laps’ of the transmission-line  215  as defined between the spaced loop traces  215   a ,  215   b  and through the cross-over  219 . 
         [0041]    This structure of the transmission-line  215  has a planar equivalence to a Moebius strip, see  FIG. 6 , where an endless strip with a single twist through 180° has the remarkable topology of effectively converting a two-sided and two-edged, but twisted and ends-joined, originating strip to have only one side and one edge, see arrows endlessly tracking the centre line of the strip. From any position along the strip, return will be with originally left- and right-hand edges reversed, inverted or transposed. The same would be true for any odd number of such twists along the length of the strip. Such a strip of conductive material would perform as required for signal paths of embodiments of this invention, and constitutes another structural aspect of invention. A flexible substrate would allow implementing a true Mobius strip transmission-line structure, i.e. with graduality of twist that could be advantageous compared with planar equivalent cross-over  19 . A flexible printed circuit board so formed and with its ICs mounted is seen as a feasible proposition. 
         [0042]      FIG. 7  is a circuit diagram for a pulse generator, actually an oscillator, using the transmission-line  215  of  FIG. 5 , specifically further having plural spaced regenerative active means conveniently as bi-directional inverting switching/amplifying circuitry  221  connected between the conductive loop traces  215   a ,  215   b . The circuitry  221  is further illustrated in this particular embodiment as comprising two inverters  223   a ,  223   b  that are connected back-to-back. Alternatives regenerative means that rely on negative resistance, negative capacitance or are otherwise suitably non-linear, and regenerative (such as Gunn diodes) or are of transmission-line nature. It is preferred that the circuitry  221  is plural and distributed along the transmission-line  215 , further preferably evenly, or substantially evenly; also in large numbers say up to  100  or more, further preferably as many and each as small as reasonably practical. 
         [0043]    Inverters  223   a ,  223   b  of each switching amplifier  221  will have the usual operative connections to relatively positive and negative supply rails, usually V+ and GND, respectively. Respective input/output terminals of each circuit  221  are shown connected to the transmission-line  215  between the loops  215   a ,  215   b  at substantially maximum spacing apart along the effectively single conductor  217 , thus each at substantially halfway around the transmission-line  215  relative to the other. 
         [0044]      FIG. 8  is another circuit diagram for an oscillator using a transmission-line structure hereof, but with three cross-overs  219   1 ,  219   2  and  219   3 , thus the same Moebius strip-like reversing/inverting/transposing property as applies in  FIG. 7 . 
         [0045]    The rectangular and circular shapes shown for the transmission-line  215  are for convenience of illustration. They can be any shape, including geometrically irregular, so long as they have a length appropriate to the desired operating frequency, i.e. so that a signal leaving an amplifier  221  arrives back inverted after a full ‘lap’ of the transmission-line  215 , i.e. effectively the spacing between the loops  215   a, b  plus the crossover  219 , traversed in a time Tp effectively defining a pulse width or half-cycle oscillation time of the operating frequency. 
         [0046]    Advantages of evenly distributing the amplifiers  221  along the transmission-line  215  are twofold. Firstly, spreading stray capacitance effectively lumped at associated amplifiers  221  for better and easier absorbing into the transmission-line characteristic impedance Zo thus reducing and signal reflection effects and improving poor waveshape definition. Secondly, the signal amplitude determined by the supply voltages V+ and GND will be more substantially constant over the entire transmission-line  215  better to compensate for losses associated with the transmission-lines dielectric and conductor materials. A continuous closed-loop transmission-line  215  with regenerative switching means  221  substantially evenly distributed and connected can closely resemble a substantially uniform structure that appears the same at any point. 
         [0047]    A good rule is for elementary capacitance and inductance (Ce and Le) associated with each regenerative switching means and forming a resonant shunt tank LC circuit to have a resonant frequency of 1/(2α√{square root over (L e C e )} ) that is greater than the self-sustaining oscillating frequency F (F 3 , F 5  etc.) of the transmission-line  215 . 
         [0048]      FIG. 9   a  is a distributed electrical equivalent circuit or model of a portion of a transmission-line  215  hereof. It shows alternate distributed resistive (R) and inductive (L) elements connected in series, i.e. R 0  connected in series with L 1  in turn connected in series with R 2  and so on for a portion of loop  215   a , and registering L 0  connected in series with R 1  in turn connected in series with L 2  and so on for the adjacent portion of loop  215   b ; and distributed capacitive elements C 0  and C 1  shown connected in parallel across the transmission-line  15  thus to the loops  215   a  and  215   b  between the resistive/inductive elements R 0 /L 1  and the inductive/resistive elements L 0 /R 1 , respectively for C 0  and between the inductive/resistive elements L 1 /R 2  and the resistive/inductive elements R 1 /L 2 , respectively for C 1 : where the identities R 0 =R 1 =R 2 , L 0 =L 1 =L 2  and C 0 =C 1  substantially hold and the illustrated distributed RLC model extends over the whole length of the transmission-line  215 . Although not shown, there will actually be a parasitic resistive element in parallel with each capacitive element C, specifically its dielectric material. 
         [0049]      FIG. 9   b  is a further simplified alternative distributed electrical equivalent circuit or model that ignores resistance, see replacement of those of  FIG. 9   a  by further distribution of inductive elements in series at half (L/2) their value (L) in  FIG. 9   a . This model is useful for understanding basic principles of operation of transmission-lines embodying the invention. 
         [0050]    During a ‘start-up’ phase, i.e. after power is first applied to the amplifiers  221 , oscillation will get initiated from amplification of inherent noise within the amplifiers  221 , thus begin substantially chaotically though it will quickly settle to oscillation at a fundamental frequency F, typically within nano-seconds. For each amplifier  221 , respective signals from its inverters  223   a  and  223   b  arrive back inverted after experiencing a propagation delay Tp around the transmission-line  215 . This propagation delay Tp is a function of the inductive and capacitive parameters of the transmission-line  215 ; which, as expressed in henrys per meter (L) and in farads per meter (C) to include all capacitive loading of the transmission-line, lead to a characteristic impedance Zo=SQR (L/C) and a line traverse or propagation or phase velocity−Pv=1/SQRT(L/C). Reinforcement, i.e. selective amplification, of those frequencies for which the delay Tp is an integer sub-divisor of a half-cycle time gives rise to the dominant lowest frequency, i.e. the fundamental frequency F=1/(2·Tp), for which the sub-divisor condition is satisfied. All other integer multiples of this frequency also satisfy this sub-divisor condition, but gain of the amplifiers  21  ‘falls off’, i.e. decreases, for higher frequencies, so the transmission-line  215  will quickly settle to fundamental oscillation at the frequency F. 
         [0051]    The transmission-line  215  has endless electromagnetic continuity, which, along with fast switching times of preferred transistors in the inverters  223   a  and  223   b , leads to a strongly square wave-form containing odd harmonics of the fundamental frequency F in effectively reinforced oscillation. At the fundamental oscillating frequency F, including the odd harmonic frequencies, the terminals of the amplifiers  221  appear substantially unloaded, due to the transmission-line  215  being ‘closed-loop’ without any form of termination, which results very desirably in low power dissipation and low drive requirements. The inductance and capacitance per unit length of the transmission-line  215  can be altered independently, as can also be desirable and advantageous. 
         [0052]      FIG. 10  shows a pair of back-to-back inverters  223   a ,  223   b  with supply line connectors and indications of distributed inductive (L/2) and capacitive (C) elements of a transmission-line as per  FIG. 9   b.    
         [0053]      FIG. 11   a  shows N-channel and P-channel Mosfet implementation of the back-to-back inverters  223   a  and  223   b , see out of NMOS and PMOS transistors. 
         [0054]      FIG. 11   b  shows an equivalent circuit diagram for NMOS (N 1 , N 2 ) and PMOS (P 1 , P 2 ) transistors, together with their parasitic capacitances. The gate terminals of transistors P 1  and N 1  are connected to the conductive trace  215   a  and to the drain terminals of transistors P 2  and N 2 . Similarly, the gate terminals of transistors P 2  and N 2  are connected to the conductive trace  215   b  and to the drain terminals of transistors P 1  and N 1 . The PMOS gate-source capacitances CgsP 1  and CgsP 2 , the PMOS gate-drain capacitances CgdP 1  and CgdP 2 , and the PMOS drain-source and substrate capacitances CdbP 1  and CdbP 2 , also the NMOS gate-source capacitances CgsN 1  and CgsN 2 , the NMOS gate-drain capacitances CgdN 1  and CgdN 2 , and the NMOS drain-source and substrate capacitances CdbN 1  and CdbN 2  are effectively absorbed into the characteristic impedance Zo of the transmission-line, so have much less effect upon transit times of the individual NMOS and PMOS transistors. The rise and fall times of the waveforms Φ 1  and Φ 2  are thus much faster than for prior circuits. 
         [0055]    Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.