Abstract:
A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to an integrated circuit package structure, more particularly, is related to an integrated circuit package structure implemented by lead on chip (LOC) and chip on lead (COL) technique. 
         [0003]    2. Description of the Prior Art 
         [0004]    In recent years, the back end process of the semiconductor package is 3-dimension (3D) package process in order to use less area with higher density or higher memory storage volume. In order to achieve this object, the multi-chips stacked are used in 3D package process. 
         [0005]    In prior art, such as U.S. Pat. No. 6,744,121, it is a multi-chips stacked package structure with lead frame, as shown in  FIG. 1   a.  Obviously, the lead frame in the package structure of  FIG. 1   a  is bent several times to avoid the metal wires on the bottom chip are contacted to the bottom of the top chip. The metal wires of the bottom chip are protected in accordance with the formation of the height difference by bending the lead frame. However, the lead frame is bent several times and is easy to be deformed. The rest of the chips are hard to stack correctly. Besides, the bent lead frame is easy to loose the package structure so as the package structure can be reduced. Besides, because the lead frame is bent several times, the adhesive area between the chips and the lead frame is not enough and the chips are easy to be loosed during the molding process. 
         [0006]    Besides, other multi-chips stacked package structure by using lead frame is disclosed in U.S. Pat. No. 6,838,754 and 6,977,427, as shown in  FIG. 1   b  and  FIG. 1   c.  During the connection between the top chip and the bottom chip, the bottom of the top chip is easy to contact to the metal wires of the bottom chip and cause the short circuit or the metal wires loosed in the embodiments shown in  FIG. 1   b  and  FIG. 1   c.    
         [0007]    Besides, multi-chips stacked in a package structure are easy to cause the heat effect when the multi-chips are operated. When the heat is hard to release from the multi-chips stacked package structure, the reliability of the chips are decreased. 
       SUMMARY OF THE INVENTION 
       [0008]    According to the problems described above, the object of the present invention is to provide a package structure by using an insulation layer to isolate the top chip and the bottom chip to protect the metal wires of the bottom chip. 
         [0009]    The other object of the present invention is to provide a package method of the multi-chips stacked package structure by using the lead frame as the substrate and let the metal spacer connect to the thermal fin of the lead frame. The heat generated by operating the multi-chips package structure is released out of the package structure according to the thermal fin of the lead frame and the reliability of the chip is enhanced. 
         [0010]    According to above objects, the present invention provides a multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, which composed of a plurality of inner leads and a plurality of outer leads, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel, the end of the first inner leads and the end of second inner leads being arranged in rows facing each other at a distance, wherein two thermal fins adjacent to the central area of the first inner leads and the second inner leads; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame and contacted to a back surface correspond to the active surface of the second chip; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
           [0012]      FIG. 1   a  is a sectional view of the multi-chips stacked package structure in prior art. 
           [0013]      FIG. 1   b  is a sectional view of another multi-chips stacked package structure in prior art. 
           [0014]      FIG. 1   c  is a sectional view of one another multi-chips stacked package structure in prior art. 
           [0015]      FIG. 2  is a top view of the multi-chips stacked package structure according to one embodiment of the present invention. 
           [0016]      FIG. 3  is a view of the multi-chips stacked package structure according to one embodiment of the present invention. 
           [0017]      FIG. 4  is a view of the multi-chips stacked package structure according to another embodiment of the present invention. 
           [0018]      FIG. 5  is a view of the multi-chips stacked package structure with a bus bar according to one embodiment of the present invention. 
           [0019]      FIG. 6  is a view of the multi-chips stacked package structure according to one another embodiment of the present invention. 
           [0020]      FIG. 7  is a view of the multi-chips stacked package structure according to one another embodiment of the present invention. 
           [0021]      FIG. 8  is a view of the multi-chips stacked package structure with a bus bar according to one embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0022]    The detailed description of the present invention will be discussed in the following embodiments, which are not intended to limit the scope of the present invention, but can be adapted for other applications. While drawings are illustrated in details, it is appreciated that the quantity of the disclosed components may be greater or less than that disclosed, except expressly restricting the amount of the components. 
         [0023]    In the semiconductor package process, the wafer is doing a thinning process after the front end process to thin the size of the chip between 2˜20 mils. A coating or printing process is used to coat or print a polymer on the bottom of the chip. The polymer is made by a resin or a B-Stage resin. A baking or photo-lighting process is used to let the polymer be a semi-glue material. Then a removable tape is used to stick on the polymer and the wafer sawing process is used to saw the wafer into several dies. Therefore, each of the dies is connected to the substrate and stacked to each other.  FIG. 2  is a bottom view showing a lead frame structure according to the present invention. As shown in  FIG. 2 , the reference number  100  is the lead frame structure, the reference number  110  is a bus bar, the reference number  120  is a lead of the lead frame and the reference number  130  is a thermal fin of the lead frame. The following description and the corresponding drawings are according to the sectional view of the A and B line segment. 
         [0024]    At first, as shown in  FIG. 2 , the lead frame  100  includes a top surface and a reverse surface and the leads  120  of the lead frame are composed by a plurality of inner leads and a plurality of outer leads. The line segment  10  is used to be the boarder line between the inner leads and the outer leads. The inner leads are composed by a plurality of first inner leads  1201  and a plurality of second inner leads  1203 . The ends of the first inner leads  1201  and the ends of the second inner leads  1203  are relatively arranged by an interval. 
         [0025]    The first inner leads  1201  and the second inner leads  1203  closed to the central region respectively include a thermal fin in the leads  120  of the lead frame  100 . The width of the thermal fin  130  is wider than the inner leads thereof and the thermal fin  130  is able to form a fan-shape closed to the inner leads. Besides, the external of the first inner leads  1201  and the second inner leads  1203  further respectively include a bus bar  110  in the lead frame  100  of the present invention. The bus bar  110  can be the power connective point, the grounded point or the signal connective point. 
         [0026]    Now,  FIG. 3  is a sectional view showing the multi-chips stacked package structure in the AA line segment according to the present invention. The multi-chips package structure  200  in the AA segment of the lead frame  100  includes: the lead  120  of the lead frame  100 , the first chip (also called the bottom chip)  10 , the second chip (or called the top chip)  20 , a plurality of first metal wires  50  and a plurality of second metal wires  60 . 
         [0027]    As shown in  FIG. 3 , at first, the first chip  10  is provided and a plurality of first pads  102  is disposed near the central region of the active surface of the first chip  10 . And an adhesive layer  40  is formed on a portion of the active surface of the first chip  10  and the adhesive layer  40  is a tape or a die attached film, it is not limited herein. Therefore, the adhesive material with sticking ability is included in the present invention. In addition, the adhesive layer  40  is able to form on the reverse surface of the lead frame  100  first and it is also not limited herein. And then, the first chip  10  is stuck on the reverse surface of the lead frame  100  to form a lead on chip (LOC) structure. The first pads  102  of the first chip  10  are exposed at the interval between the first inner leads  1201  and the second inner leads  1203 . Therefore, a wire bonding process is executed to electrically connect the first metal wires  50  on the first inner leads  1201  and the second inner leads  1203 . During the wire bonding process, the wire bonding machine (not shown) will form a metal spacer  30  on the thermal fin  130  of the lead frame  100 . The height of the metal spacer  30  is higher than the curved height of the first metal wire  50 . The metal spacer  30  is made by stacking a plurality of solder balls or metal bumps. 
         [0028]    There is a sticky polymer material  70  coating near the interval between the ends of the first inner leads  1201  and the second leads. The polymer material  70  covers the first pads  102  of the first chip  10  and the first metal wires  50 . Then, a second chip  20  is provided and the bottom portion of the second chip  20  is stuck on the polymer material  70  to fix the second chip  20  on the top surface of the lead frame  70  to form a Chip on Lead (COL) structure. The polymer material  70  is a resin, such as a B-stage resin. 
         [0029]    Now, there is a metal spacer  30  formed on the top surface of the thermal fin  130  of the lead frame  100 , as shown in  FIG. 4  ( FIG. 4  is a sectional view showing the multi-chips stacked structure of the present invention in the BB line segment). 
         [0030]    Therefore, when the bottom of the second chip  20  is stuck on the polymer material  70 , the bottom of the second chip  20  is contacted to the metal spacer  30 . Because the height of the metal spacer  30  is higher than the curved height of the first metal wire  50 , the metal spacer  30  isolates the first metal wires of the first chip  10  and the bottom of the second chip  20  when the bottom of the second chip  20  is contacted to the metal spacer  30 . 
         [0031]    After connecting the second chip  20  on the top surface of the lead frame  100 , there is an optional baking process used to solidify the polymer material  70 . 
         [0032]    Then, a second wire bonding is used to electrically connect the second pads  202  of the second chip  20  on the first inner leads  1201  and the second inner leads  1203  by the reverse wire bonding of the second metal wires  60 . An encapsulated material  80  made by a molding process covers the first chip  10 , the second chip  20  and the inner leads  1201  ( 1203 ) of the lead frame  100  and expose the outer leads  1202  ( 1204 ) out of the encapsulated material  80 . At final, a sawing or stamping process is used to bend the outer leads  1202  ( 1204 ) of the lead frame  100 , as shown in  FIG. 3 . Besides, it should be noted that the method of bending the thermal fin  130  the lead frame  100  of the present invention is same as the method used in outer leads  1202 ( 1204 ) or bending forward to the two sides of the encapsulated material  80 , as shown the dot lines in  FIG. 4 . Therefore, when the package structure of the present invention is electrically connected to a circuit board (not shown), the bottom of the thermal fin  130  bent by the two methods is contacted to the circuit board to be the suitable wire layout of the circuit board. Of course, it is obviously that the thermal fin  130  is bent upward (not shown) and hung in the air to release the heat included in one of the embodiment of the present invention. 
         [0033]    Besides,  FIG. 5  is a section view showing another embodiment of the multi-chips stacked package structure in the BB line segment of the lead frame  100 . It is obviously that the different between  FIG. 5  and  FIG. 3  is the lead frame  100  in  FIG. 5  with bus bar  100  structure. The bus bar  110  is used to be a power connective point, a grounded point or a signal connective point. Because the process of the stacked package structure in  FIG. 5  is similar to the structure in  FIG. 3 , the description of the package process is omitted. 
         [0034]    Now,  FIG. 6  and  FIG. 7  are another embodiment of the multi-chips stacked package structure in the present invention. As shown in  FIG. 6 , the lead frame  100  of this embodiment is similar to the structure shown in  FIG. 2 , the description is not repeated. 
         [0035]    As shown in  FIG. 6 , the first chip is provided and a plurality of first pads  102  is disposed near the active surface of the first chip  10 . An adhesive layer  40  is formed on a portion of the active surface of the first chip  10 . The adhesive layer  40  is a tape or a die attached film. The adhesive layer  40  is formed on the bottom of the lead frame  100  first; it is not limited in the present invention. The first chip  10  is stuck on the bottom of the lead frame  100  to form a lead on chip (LOC) structure. The first pads  102  of the first chip  10  are exposed at the interval between the ends of the first inner leads  1201  and the second inner leads  1203 . And then, a wire bonding process is used to electrically connect the first pads  102  on the first inner leads  1201  and the second inner leads  1203  by the first wires  50 . During the wire bonding process, the wire bonding machine (not shown) will form a metal spacer  30  on the thermal fin  130  of the lead frame  100 . The height of the metal spacer  30  is higher than the curved height of the first metal wires  50 . The metal spacer  30  is made by stacking a plurality of solder balls or metal bumps. 
         [0036]    A sticky polymer material  70  is coating near the interval between the ends of the first inner leads  1201  and the second inner leads  1203 . The polymer material  70  is covering the first pads  102  of the first chip  10  and the first metal wires  50 . 
         [0037]    And then, a second chip  20  is provided and an adhesive layer  90  is formed on the bottom of the second chip  20 . The adhesive layer  90  is stuck on the bottom of the second chip  20  or the adhesive layer  90  is stuck near two sides of the second chip  20 . Besides, the adhesive layer  90  is a polymer material, such as a resin or a B-Stage resin. Besides, the adhesive layer  90  can be a glue film, too. The second chip  20  is fixed on the top surface of the inner leads  1201  ( 1203 ) of the lead frame  100  by the adhesive layer  90 . The adhesive layer  90  of the bottom of the second chip  20  cover the first metal wire  50 . 
         [0038]    Because of the wire bonding process described above, an metal spacer  30  is formed on the top surface of the thermal fin  130  of the lead frame  100 , as shown in  FIG. 7  ( FIG. 7  is a sectional view showing the multi-chips stacked structure of the present invention in the BB line segment). Therefore, the bottom of the second chip  20  is contacted to the metal spacer  30  when the bottom of the second chip  20  is stuck on the polymer material  70 . Because the height of the metal spacer  30  is higher than the curved height of the first metal wires  50 , the metal spacer  30  isolates the first metal wires  50  of the first chip  10  and the bottom of the second chip  20 . 
         [0039]    Then, a second wire bonding is used to electrically connect the second pads  202  of the second chip  20  on the first inner leads  1201  and the second inner leads  1203  by the reverse wire bonding of the second metal wires  60 . An encapsulated material  80  made by a molding process covers the first chip  10 , the second chip  20  and the inner leads  1201  ( 1203 ) of the lead frame  100  and expose the outer leads  1202  ( 1204 ) out of the encapsulated material  80 . At final, a sawing or stamping process is used to bend the outer leads  1202  ( 1204 ) of the lead frame  100 , as shown in  FIG. 6 . Besides, it should be noted that the method of bending the thermal fin  130  the lead frame  100  of the present invention is the same as the method used in outer leads  1202 ( 1204 ) or bending forward to the two sides of the encapsulated material  80 , as shown the dot lines in  FIG. 7 . 
         [0040]    When the thermal fin  130  is bent by the two method described above, the bottom of the thermal fin  130  and the outer leads  1202  ( 1204 ) are at the same horizontal surface. Therefore, when the package structure of the present invention is electrically connected to a circuit board (not shown), the bottom of the thermal fin  130  bent by the two methods is contacted to the circuit board to be the suitable wire layout of the circuit board. The heat effect of the package structure is passing from the metal spacer  30  to the thermal fin  130  and the heat is passing from the wider thermal fin  130  to the circuit board. Therefore, the heat is efficiently passing out of the package structure. Of course, it is obviously that the thermal fin  130  is bent upward (not shown) and hung in the air to release the heat included in one of the embodiment of the present invention. 
         [0041]    Besides,  FIG. 8  is a section view showing another embodiment of the multi-chips stacked package structure in the BB line segment of the lead frame  100 . It is obviously that the different between  FIG. 8  and  FIG. 6  is the lead frame  100  in  FIG. 8  including a bus bar  100  structure. The bus bar  110  is used to be a power connective point, a grounded point or a signal connective point. Because the process of the stacked package structure in  FIG. 8  is similar to the structure in  FIG. 6 , the description of the package process is omitted. 
         [0042]    According to the description above, the multi-chips stacked package structure disclosed in the present invention is used to solve the problem that the lead frame was bent too many times in the prior art. In the embodiments of the present invention, the lead frame can be used in multi-chips stacking without several times&#39; bending. Because the connective element between the chips and the lead frame is sued to shorten the size of the multi-chips stacked package structure, the problem that the connection of the metal wires is shorted or released is avoided. 
         [0043]    The foregoing description is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obvious modifications or variations are possible in light of the above teachings. In this regard, the embodiment or embodiments discussed were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly and legally entitled.