Abstract:
A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a pluality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a divisional application of U.S. Ser. No. 10/903,371 filed Jul. 30, 2004, the contents of which are incorporated by reference herein in their entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The invention relates to computer memory subsystems and, more particularly, to a buffered memory module having enhanced fault tolerance.  
         [0003]     Computer memory subsystems have evolved over the years, but continue to retain many consistent attributes. Computer memory subsystems from the early 1980&#39;s, such as the one disclosed in U.S. Pat. No. 4,475,194 to LeVallee et al, of common assignment herewith, included a memory controller, a memory assembly (contemporarily called a basic storage module (BSM) by the inventors) with array devices, buffers, terminators and ancillary timing and control functions, as well as several point-to-point busses to permit each memory assembly to communicate with the memory controller via its own point-to-point address and data bus.  FIG. 1  depicts an example of this early 1980 computer memory subsystem with two BSMs, a memory controller, a maintenance console, and point-to-point address and data busses connecting the BSMs and the memory controller.  
         [0004]      FIG. 2 , from U.S. Pat. No. 5,513,135 to Dell et al, of common assignment herewith, depicts an early synchronous memory module, which includes synchronous dynamic random access memories (DRAMs)  8 , buffer devices  12 , an optimized pinout, an interconnect and a capacitive decoupling method to facilitate operation. The patent also describes the use of clock re-drive on the module, using such devices as phase lock loops (PLLs).  
         [0005]      FIG. 3 , from U.S. Pat. No. 6,510,100 to Grundon et al, of common assignment herewith, depicts a simplified diagram and description of a memory subsystem  10  that includes up to four registered dual inline memory modules (DIMMs)  40  on a traditional multi-drop stub bus channel. The subsystem includes a memory controller  20 , an external clock buffer  30 , registered DIMMs  40 , address bus  50 , control bus  60  and a data bus  70  with terminators  95  on the address bus  50  and data bus  70 .  
         [0006]      FIG. 4  depicts a 1990&#39;s memory subsystem which evolved from the structure in  FIG. 1  and included a memory controller  402 , one or more high-speed point-to-point channels  404 , each connected to a bus-to-bus converter chip  406 , and each having a synchronous memory interface  408  that enables connection to one or more registered DIMMs  410 . In this implementation, the high-speed, point-to-point channel  404  operated at twice the DRAM data rate, allowing the bus-to-bus converter chip  406  to operate one or two registered DIMM memory channels at the full DRAM data rate. Each registered DIMM included a PLL, registers, DRAMs, an electrically erasable programmable read-only memory (EEPROM) and terminators, in addition to other passive components.  
         [0007]     As shown in  FIG. 5 , memory subsystems were often constricted with a memory controller connected either to a single memory module, or to two or more memory modules interconnected on a ‘stub’ bus.  FIG. 5  is a simplified example of a multi-drop stub bus memory structure, similar to the one shown in  FIG. 3 . This structure offers a reasonable trade-off between cost, performance, reliability and upgrade capability, but has inherent limits on the number of modules that may be attached to the stub bus. The limit on the number of modules that may be attached to the stub bus is directly related to the data rate of the information transferred over the bus. As data rates increase, the number and length of the stubs must be reduced to ensure robust memory operation. Increasing the speed of the bus generally results in a reduction in modules on the bus, with the optimal electrical interface being one in which a single module is directly connected to a single controller, or a point-to-point interface with few, if any, stubs that will result in reflections and impedance discontinuities. As most memory modules are sixty-four or seventy-two bits in data width, this structure also requires a large number of pins to transfer address, command, and data. One hundred and twenty pins are identified in  FIG. 5  as being a representative pincount.  
         [0008]      FIG. 6 , from U.S. Pat. No. 4,723,120 to Petty, of common assignment herewith, is related to the application of a daisy chain structure in a multipoint communication structure that would otherwise require multiple ports, each connected via point-to-point interfaces to separate devices. By adopting a daisy chain structure, the controlling station call be produced with fewer ports (or channels), and each device on the channel can utilize standard upstream and downstream protocols, independent of their location in the daisy chain structure.  
         [0009]      FIG. 7  represents a daisy chained memory bus, implemented consistent with the teachings in U.S. Pat. No. 4,723,120. The memory controller is connected to a memory bus  315 , which further connects to module  310   a . The information on bus  315  is re-driven by the buffer on module  310   a  to the next module,  310   b , which further re-drives the bus  315  to module positions denoted as  310   n . Each module  310   a  includes a DRAM  311   a  and a buffer  320   a . The bus  315  may be described as having a daisy chain structure, with each bus being point-to-point in nature.  
         [0010]     As new systems emerge which offer enhanced performance, improved reliability and/or reduced power consumption, customers will often replace existing systems with these new systems. To reduce total purchase cost, however, many may wish to re-use many or all of their storage devices in the new system—often in conjunction with the new storage technology of that system, in order to take advantage of the increased speed and density. At the same time, it is also desirable to be able to provide the high-speed, high-density storage capability in a reliable maimer that is resistant to faults such as pin discontinuity, single points-of-failure, and other related faults, as well as supporting increased DRAM body widths therein.  
       BRIEF SUMMARY OF THE INVENTION  
       [0011]     Exemplary embodiments of the present invention include a dual inline memory module (DIMM) including a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.  
         [0012]     Further exemplary embodiments include a dual inline memory module (DIMM), including a card having a length of about 151.35 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card. The buffer device is configured to re-drive information to one or more external memory modules in a cascaded manner, and at least one positioning key is formed on the card.  
         [0013]     Further exemplary embodiments include a computer memory system, including a memory controller device, a first dual inline memory module (DIMM) coupled to the memory controller device through a set of at least two single-ended busses, the first DIMM including a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card. The buffer device is configured for converting a packetized memory interface. En-or code connection (ECC) logic is further included for identifying and correcting bus faults, and a set of at least two high-speed busses connects the first DIMM to at least one of the memory controller device and a second DIMM.  
         [0014]     Additional exemplary embodiments include a computer memory system, including a dual inline memory module (DIMM) including a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. A plurality of high-speed busses are in communication with the DIMM for implementing a cascade connection to upstream and downstream devices with respect to the DIMM. The DIMM further includes a plurality of high-speed bus interface pins arranged on the card, such that for a given high-speed bus, a first portion of the high-speed bus interface pins associated therewith is located one side of the card, with respect to a midpoint of the length, and a second portion of said high-speed bus interface pins associated therewith is located on the opposite side of the card, with respect to the midpoint.  
         [0015]     Additional exemplary embodiments include a dual inline memory module (DIMM), including a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon, wherein a first portion of the pins is configured to operate at a first supply voltage, and a second portion of the pins is configured to operate at a second supply voltage. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:  
         [0017]      FIG. 1  depicts a prior art memory controller connected to two buffered memory assemblies via separate point-to-point links;  
         [0018]      FIG. 2  depicts a prior art synchronous memory module with a buffer device;  
         [0019]      FIG. 3  depicts a prior art memory subsystem using registered DIMMs;  
         [0020]      FIG. 4  depicts a prior art memory subsystem with point-to-point channels, registered DIMMs, and a 2:1 bus speed multiplier  
         [0021]      FIG. 5  depicts a prior art memory structure that utilizes a multidrop memory ‘stub’ bus;  
         [0022]      FIG. 6  depicts a prior art daisy chain structure in a multipoint communication structure that would otherwise require multiple ports;  
         [0023]      FIG. 7  depicts a prior art daisy chain connection between a memory controller and memory modules;  
         [0024]      FIG. 8  depicts a cascaded memory structure that is utilized by exemplary embodiments of the present invention;  
         [0025]      FIG. 9  depicts a memory structure with cascaded memory modules and unidirectional busses that is utilized by exemplary embodiments of the present invention;  
         [0026]      FIG. 10  is a front view of a 276-pin, buffered memory module (DIMM) that is utilized by exemplary embodiments of the present invention;  
         [0027]      FIG. 11  is a block diagram of a multi-mode buffer device high level logic flow as utilized by exemplary embodiments of the present invention;  
         [0028]      FIG. 12  is a table that includes typical applications and operating modes of exemplary buffer devices;  
         [0029]      FIG. 13  is a simplified block diagram of a buffered DIMM produced with a multi-mode buffer device that may be utilized by exemplary embodiments of the present invention;  
         [0030]      FIG. 14  is a simplified block diagram of a buffered DIMM produced with a multi-mode buffer device that may be utilized by exemplary embodiments of the present invention; and  
         [0031]      FIG. 15  is a table illustrating a functional pin layout of the exemplary 276-pin DIMM of  FIG. 10 , in accordance with a further embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     Exemplary embodiments of the present invention include a flexible, high-speed and high reliability memory system architecture and interconnect structure that includes a single-ended point-to-point interconnection between any two high-speed communication interfaces. The memory subsystem may be implemented in one of several structures, depending on desired attributes such as reliability, performance, density, space, cost, component re-use and other elements. A bus-to-bus converter chip enables this flexibility through the inclusion of multiple, selectable memory interface modes. This maximizes the flexibility of the system designers in defining optimal solutions for each installation, while minimizing product development costs and maximizing economies of scale through the use of a common device. In addition, exemplary embodiments of the present invention provide a migration path that allows an installation to implement a mix of buffered memory modules and unbuffered and/or registered memory modules from a common buffer device.  
         [0033]     Memory subsystems may utilize a buffer device to support buffered memory modules (directly connected to a memory controller via a packetized, multi-transfer interface with enhanced reliability features) and/or existing unbuffered or registered memory modules (in conjunction with the identical buffer device, on an equivalent but, programmed to operate in a manner consistent with the memory interface defined for those module types). A memory subsystem may communicate with buffered memory modules at one speed and with unbuffered and registered memory modules at another speed (typically a slower speed). Many attributes associated with the buffered module structure are maintained, including the enhanced high-speed bus error detection and connection features and the memory cascade function. However, overall performance may be reduced when communicating with most registered and unbuffered DIMMs due to the net topologies and loadings associated with them.  
         [0034]      FIG. 8  depicts a cascaded memory structure that may be utilized by exemplary embodiments of the present invention when buffered memory modules  806  (e.g., the buffer device is included within the memory module  806 ) are in communication with the memory controller  802 . This memory structure includes a memory controller  802  in communication with one or more memory modules  806  via a high-speed point-to-point bus  804 . Each bus  804  in the exemplary embodiment depicted in  FIG. 8  includes approximately fifty high-speed wires for the transfer of address, command, data and clocks. By using point-to-point busses as described in the aforementioned prior art, it is possible to optimize the bus design to pen-nit significantly increased data rates, as well as to reduce the bus pincount by transferring data over multiple cycles. Whereas  FIG. 4  depicts a memory subsystem with a two to one ratio between the data rate on any one of the busses connecting the memory controller to one of the bus converters (e.g., to 1,066 Mb/s per pin) versus any one of the busses between the bus converter and one or more memory modules (e.g., to 533 Mb/s per pin), an exemplary embodiment of the present invention, as depicted in  FIG. 8 , provides a four to one bus speed ratio to maximize bus efficiency and minimize pincount.  
         [0035]     Although point-to-point interconnects permit higher data rates, overall memory subsystem efficiency must be achieved by maintaining a reasonable number of memory modules  806  and memory devices per channel (historically four memory modules with four to thirty-six chips per memory module, but as high as eight memory modules per channel and as few as one memory module per channel). Using a point-to-point bus necessitates a bus re-drive function on each memory module, to permit memory modules to be cascaded such that each memory module is interconnected to other memory modules as well as to the memory controller  802 .  
         [0036]      FIG. 9  depicts a memory structure with cascaded memory modules and unidirectional busses that are utilized by exemplary embodiments of the present invention if all of the memory modules  806  are buffered memory modules  806 . One of the functions provided by the memory modules  806  in the cascade structure is a redrive function to send signals on the memory bus to other memory modules  806  or to a memory controller  802 .  FIG. 9  includes a memory controller  802  and four memory modules  806   a ,  806   b ,  806   c  and  806   d , on each of two memory busses (a downstream memory bus  904  and an upstream memory bus  902 ), connected to the memory controller  802  in either a direct or cascaded maimer. Memory module  806   a  is connected to the memory controller  802  in a direct maimer. Memory modules  806   b ,  806   c  and  806   d  are connected to the controller  802  in a cascaded maimer.  
         [0037]     An exemplary embodiment of the present invention includes two uni-directional busses between the memory controller  802  and memory module  806   a  (“DIMM #1”) as well as between each successive memory module  806   b - d  (“DIMM #2”, “DIMM #3” and “DIMM #4”) in the cascaded memory structure. The downstream memory bus  904  is comprised of twenty-two single-ended signals and a differential clock pair. The downstream memory bus  904  is used to transfer address, control, data and error code correction (ECC) bits downstream from the memory controller  802 , over several clock cycles, to one or more of the memory modules  806  installed on the cascaded memory channel. The upstream memory bus  902  is comprised of twenty-three single-ended signals and a differential clock pair, and is used to transfer bus-level data and ECC bits upstream from the sourcing memory module  806  to the memory controller  802 . Using this memory structure, and a four to one data rate multiplier between the DRAM data rate (e.g., 400 to 800 Mb/s per pin) and the unidirectional memory bus data rate (e.g., 1.6 to 3.2 Gb/s per pin), the memory controller  802  signal pincount, per memory channel, is reduced from approximately one hundred and twenty pins to about fifty pins.  
         [0038]      FIG. 10  depicts a front view of a buffered memory module  806  that is utilized by exemplary embodiments of the present invention. In exemplary embodiments of the present invention, each memory module  806  includes a blank card having dimensions of approximately six inches long by one and a half inches tall, eighteen DRAM positions, a multi-mode buffer device  1002 , and numerous small components as known in the art that are not shown (e.g., capacitors, resistors, EEPROM.) In an exemplary embodiment of the present invention, the dimension of the card is 5.97 inches long by 1.2 inches tall. In an exemplary embodiment of the present invention, the multi-mode buffer device  1002  is located in the center region of the front side of the memory module  806 , as depicted in  FIG. 10 . The synchronous DRAMS (SDRAMS)  1004  are located on either side of the multi-mode buffer device  1002 , as well as on the backside of the memory module  806 , as depicted in  FIG. 10 . The configuration may be utilized to facilitate high-speed wiring to the multi-mode buffer device  1002  as well as signals from the buffer device to the SDRAMs  1004 .  
         [0039]     The DRAM package outline is a combination of a tall/narrow (i.e., rectangular) DRAM package and a short/wide (i.e., squarish) DRAM package. Thus configured, a single card design may accommodate either “tall” or “wide” DRAM device/package combinations, consistent with historical and projected device trends. Moreover, the buffer device  1002  is rectangular in shape, thereby permitting a minimum distance between high-speed package interconnects and the DIMM tab pins, as well as reducing the distance the high-speed signals must travel under the package to reach an available high-speed pin, when an optimal ground referencing stricture is used.  
         [0040]     As is also shown in  FIG. 10 , the location of a positioning key  810  (notch) is specifically shifted from the midpoint of the length,  1 , of the card  808  (with respect to prior generation models) in order to ensure the DIMM cannot be fully inserted into a connector intended for a different module type. In addition, the positioning key location also prevents reverse insertion of the DIMM, and allows for a visual aid to the end-user regarding proper DIMM insertion. In the example illustrated, the positioning key  810  is located between pins  80 / 218  and  81 / 219 . As such, the distance d, along the length, l, of the card  808  is larger than the distance d 2 .  
         [0041]      FIG. 11  is a block diagram of the high level logic flow of a multi-mode buffer device  1002  utilized by exemplary embodiments of the present invention. The multi-mode multi-mode buffer device  1002  may be located on a memory module  806  as described previously and/or located on a system board or card to communicate with unbuffered and registered memory modules. The blocks in the lower left and right portions of the drawing ( 1124 ,  1128 ,  1130 ,  1134 ) are associated with receiving or driving the high-speed bus  804 . “Upstream” refers to the bus  902  passing information in the direction of the memory controller  802 , and “downstream” refers to the bus  904  passing information away from the memory controller  802 .  
         [0042]     Referring to  FIG. 11 , data, command, address, ECC, and clock signals from an upstream memory assembly (i.e., a memory module  806 ) or a memory controller  802  are received from the downstream memory bus  904  into a receiver module  1124 . The receiver functional block  1124  provides macros and support logic for the downstream memory bus  904  and, in an exemplary embodiment of the present invention includes support for a twenty-two bit, high-speed, slave receiver bus. The receiver functional block  1124  transmits the clock signals to a clock logic and distribution functional block  1118  (e.g., to generate the foul to one clock signals). The clock logic and distribution frictional block  1118  also receives data input from the pervasive and miscellaneous signals  1110 . These signals typically include control and setup information for the clock distribution PLL&#39;s, test inputs for BIST (built-ill self-test) modes, programmable timing settings, etc. The receiver functional block  1124  transfers the data, command, ECC and address signals to a bus sparing logic block  1126  to reposition, when applicable, the bit placement of the data in the event that a spare wire utilized during the transmission from the previous memory assembly. In an exemplary embodiment of the present invention, the bus sparing logic block  1126  is implemented by a multiplexor to shift the signal positions, if needed. Next, the original or re-ordered signals are input to another bus sparing logic block  1136  to modify, or reorder if necessary, the signal placement to account for any defective interconnect that may exist between the current memory assembly and a downstream memory assembly. The original or re-ordered signals are then input to a driver functional block  1128  for transmission, via the downstream memory bus  904 , to the next memory module  806  in the chain. In an exemplary embodiment of the present invention, the bus sparing logic  1136  is implemented using a multiplexor. The driver functional block  1128  provides macros and support logic for the downstream memory bus  904  and, in an exemplary embodiment of the present invention, includes support for the twenty-two bit, high-speed, low latency cascade bus drivers.  
         [0043]     In addition to inputting the original or re-ordered signals to the bus sparing logic  1136 , the bus sparing logic  1126  also inputs the original or re-ordered signals into a downstream bus ECC functional block  1120  to perform en-or detection and correction for the frame. The downstream bus ECC functional block  1120  operates on any information received or passed through the multi-mode buffer device  1002  from the downstream memory bus  904  to determine if a bus error is present. The downstream bus ECC functional block  1120  analyzes the bus signals to determine if it they are valid. Next, the downstream bus ECC functional block  1120  transfers the connected signals to a command state machine  1114 . The command state machine  1114  inputs the error flags associated with command decodes or conflicts to a pervasive and miscellaneous functional block  1110 . The downstream and upstream modules also present error flags and/or error data (if any) to the pervasive and miscellaneous functional block  1110  to enable reporting of these errors to the memory controller, processor, service processor or other en-or management unit.  
         [0044]     Referring to  FIG. 11 , the pervasive and miscellaneous functional block  1110  transmits error flags and/or error data to the memory controller  802 . By collecting error flags and/or error data from each memory module  806  in the chain, the memory controller  802  will be able to identify the failing segment(s), without having to initiate further diagnostics, though additional diagnostics may be completed in some embodiments of the design. In addition, once an installation selected threshold (e.g., one, two, ten, or twenty) for the number of failures or type of failures has been reached, the pervasive and miscellaneous functional block  1110 , generally in response to inputs from the memory controller  802 , may substitute the spare wire for the segment that is failing. In an exemplary embodiment of the present invention, error detection and correction is performed for every group of four transfers, thereby permitting operations to be decoded and initiated after half of the eight transfers, comprising a frame, are received. The en-or detection and correction is performed for all signals that pass through the memory module  806  from the downstream memory bus  904 , regardless of whether the signals are to be processed by the particular memory module  806 . The data bits from the connected signals are input to the write data buffers  1112  by the downstream bus ECC functional block  1120 .  
         [0045]     The command state machine  1114  also determines if the connected signals (including data, command and address signals) are directed to and should be processed by the memory module  806 . If the collected signals are directed to the memory module  806 , then the command state machine  1114  determines what actions to talk and may initiate DRAM action, write buffer actions, read buffer actions or a combination thereof. Depending on the type of memory module  806  (buffered, unbuffered, registered), the command state machine  1114  selects the appropriate drive characteristics, timings and timing relationships. The write data buffers  1112  transmit the data signals to a memory data interface  1106  and the command state machine  1114  transmits the associated addresses and command signals to a memory command interface  1108 , consistent with the DRAM specification. The memory data interface  1106  reads from and writes memory data  1142  to a memory device.  
         [0046]     Data signals to be transmitted to the memory controller  802  may be temporarily stored in the read data buffers  1116  after a command, such as a read command, has been executed by the memory module  806 , consistent with the memory device ‘read’ timings. The read data buffers  1116  transfer the read data into an upstream bus ECC functional block  1122 . The upstream bus ECC functional block  1122  generates check bits for the signals in the read data buffers  1116 . The check bits and signals from the read data buffers  1116  are input to the upstream data multiplexing functional block  1132 . The upstream data multiplexing functional block  1132  merges the data on to the upstream memory bus  902  via the bus sparing logic  1138  and the driver functional block  1130 . If needed, the bus sparing logic  1138  may re-direct the signals to account for a defective segment between the current memory module  806  and the upstream receiving module (or memory controller). The driver functional block  1130  transmits the original or re-ordered signals, via the upstream memory bus  902 , to the next memory assembly (i.e., memory module  806 ) or memory controller  802  in the chain. In an exemplary embodiment of the present invention, the bus sparing logic  1138  is implemented using a multiplexor to shift the signals. The driver functional block  1130  provides macros and support logic for the upstream memory bus  902  and, in an exemplary embodiment of the present invention, includes support for a twenty-three bit, high-speed, low latency cascade driver bus.  
         [0047]     Data, clock and ECC signals from the upstream memory bus  902  are also received by any upstream multi-mode buffer device  1002  in any upstream memory module  806 . These signals need to be passed upstream to the next memory module  806  or to the memory controller  802 . Referring to  FIG. 11 , data, ECC and clock signals from a downstream memory assembly (i.e., a memory module  806 ) are received on the upstream memory bus  902  into a receiver functional block  1134 . The receiver functional block  1134  provides macros and support logic for the upstream memory bus  902  and, in an exemplary embodiment of the present invention includes support for a twenty-three bit, high-speed, slave receiver bus. The receiver functional block  1134  passes the data and ECC signals, through the bus sparing functional block  1140 , to the upstream data multiplexing functional block  1132  and then to the bus sparing logic block  1138 . The signals are transmitted to the upstream memory bus  902  via the driver functional block  1130 .  
         [0048]     In addition to passing the data and ECC signals to the upstream data multiplexing functional block  1132 , the bus sparing functional block  1140  also inputs the original or re-ordered data and ECC signals to the upstream bus ECC functional block  1122  to perform error detection and correction for the frame. The upstream bus ECC functional block  1122  operates on any information received or passed through the multi-mode buffer device  1002  from the upstream memory bus  902  to determine if a bus en-or is present. The upstream bus ECC functional block  1122  analyzes the data and ECC signals to determine if they are valid. Next, the upstream bus ECC functional block  1122  transfers any error flags and/or error data to the pervasive and miscellaneous functional block  1110  for transmission to the memory controller  802 . In addition, once a pre-defined threshold for the number or type of failures has been reached, the pervasive and miscellaneous functional block  1110 , generally in response to direction of the memory controller  802 , may substitute the spare segment for a failing segment.  
         [0049]     The block diagram in  FIG. 11  is one implementation of a multi-mode buffer device  1002  that may be utilized by exemplary embodiments of the present invention. Other implementations are possible without departing from the scope of the present invention.  
         [0050]      FIG. 12  is a table that includes typical applications and operating modes of exemplary buffer devices. Three types of buffer modes  1208  are described: buffered DIMM  1202 ; registered DIMM  1204 ; and unbuffered DIMM  1206 . The “a” and “b” bus that are output from the memory command interface  1108  can be logically configured to operate in one or more of these modes depending on the application. The table includes: a ranks column  1210  that contains the number of ranks per DIMM; a chip select (CS) column that contains the number of buffer CS outputs used, in addition to the loads per CS; a clock column  1214  that contains the number of buffer clock pairs used and the loads per clock pair; and a miscellaneous column  1216  that includes wiring topology information. A load refers to a receiver input to a DRAM, register, buffer, PLL or appropriate device on the memory module  806 .  
         [0051]     As indicated in  FIG. 12 , the buffered DIMM implementation supports up to nine memory devices per rank, with each device having an eight bit interface (seventy-two bits total). If all eight ranks are populated on a given module constructed of current one gigabit devices, the total memory density of the module will be eight gigabytes. As evident by the table entries *under the CS column  1212  (the CS is generally utilized on DIMMs as a rank select to activate all the memory devices in the rank) and the clock column  1214 , the varying loads and net structures require different driver characteristics (e.g., drive strength) for the multi-mode buffer device  1002 . In addition, as the registered DIMMs generally add a single clock delay on all inputs that pass through the register on the DIMM (address and command inputs), the multi-mode buffer device  1002  needs to accommodate the extra clock of latency by ensuring accurate address and command-to-data timings. Further, the unbuffered DIMMs, as well as the heavily loaded buffered DIMM applications often require two-transition ( 2 T) addressing, due to heavy loading on address and certain command lines (such as row address strobe (RAS), column address strobe (CAS) and write enable (WE)). In the latter case, the buffer operates such that these outputs are allowed two clock cycles to achieve and maintain a valid level prior to the CS pin being driven low to capture these DRAM inputs and initiate a new action.  
         [0052]     The terms “net topology” in  FIG. 12  refer to a drawing and/or textual description of a wiling interconnect structure between two or more devices. A “fly-by-topology” is a wiring interconnect structure in which the source (driver) is connected to two or more devices that are connected along the length of a wire, that is generally terminated at the far end, where the devices along the wire receive the signal from the source at a time that is based on the flight time through the wire and the distance from the source. A “T” net topology is a wiring interconnect structure that includes a source (driver) that is connected to two or more devices through a wire that branches or splits. Each branch or split is intended to contain similar wire length and loading. In general, a single wire will split into two branches from a single branch point, with each branch containing similar line length and loading. Inputs wired to a single register or clock are generally considered to be point-to-point. Inputs wired to multiple registers or PLLs are generally wired in a “T” net structure so that each receiver receives the input at approximately the same time, with a similar waveform. The “T” nets defined above are typically not end-terminated, but generally include a series resistor termination in the wire segment prior to the branch point.  
         [0053]      FIG. 13  is a simplified block diagram of a buffered DIMM memory module with the multi-mode buffer device  1002  that may be utilized by exemplary embodiments of the present invention. It provides ail example of the net structures and loading associated with a two rank buffered DIMM produced with eighteen DDR 2  eight bit memory devices, consistent with the information in the table in  FIG. 12 . The CS and clock signals are wired in a fly-by structure, the lines shown in the drawing from the mainline wire to each memory device appear to be long only to simplify the drawing. The fly-by net end-termination is not shown, but is included in the exemplary embodiment.  
         [0054]      FIG. 14  is a simplified block diagram of a buffered DIMM memory module  806  produced with a multi-mode buffer device  1002  that may be utilized by exemplary embodiments of the present invention. It provides an example of the net structures and loading associated with ail eight rank buffered DIMM memory module  806  produced with eight bit memory devices, consistent with the information in the table in  FIG. 12 . Each CS output controls nine memory devices (seventy-two bits) in this example, whereas each CS controls four or five (thirty-two to forty bits) in  FIG. 13 .  
         [0055]     Finally,  FIG. 15  is a table illustrating a functional pin layout of the exemplary 276-pin DIMM of  FIG. 10 , in accordance with a further embodiment of the invention. In addition to the layout and approximate distance (millimeters) from the key of each pin,  FIG. 15  also provides a functional description of each of the pins, including those used as redundant pins and those used for special control functions. Those pins that are used as redundant pins are designated in  FIG. 15  using the suffix “_r”. As indicated previously, designated pins  1 - 138  run from left to right on the front side of the DIMM, with pins  139 - 276  located behind pins  1 - 138  when viewing the front side of the DIMM.  
         [0056]     In an exemplary embodiment, each of the redundant pins is located behind the respective primary function pin for which it is redundant. For example, redundant service pins selv_ifc( 1 )_r and serv_ifc( 2 )_r (pins  142 ,  143 ) are located directly behind service pins selv_ifc( 1 ) and serv_ifc( 2 ) (pins  4 ,  5 ), respectively. In this manner, the DIMM is resistant to single point-of-fail memory outage (e.g., such as if the DIMM were warped or tilted toward one side or the other).  
         [0057]     Among the various functions included within the 276-pin layout are a pair of continuity pins ( 1 ,  138 ) and scope trigger pins ( 3 ,  141 ). As will be appreciated from an inspection of the pin assignment table in  FIG. 15 , as opposed to arranging the pins in a conventional layout (where each group of similarly functioning pins are located in the same section of the DIMM), the present embodiment uses an innovative placement wherein the center region is used for two of the four high-speed busses (s 3 _us, Output: DIMM to upstream DIMM or to Memory Controller) and (ds_s 3 , DIMM to upstream DIMM (input)). The other two high-speed busses are each split in half, wherein half of each bus (us_s 3 , controller or DIMM to DIMM (input) and s 3 _ds, DIMM to downstream DIMM (output)), with approximately half the signals for each bus placed on either end of the center region pin locations. With the buffer device placed close to the center of the module, the variability in wiling length for each pin in both the center and outer regions may be reduced.  
         [0058]     As will also be noted from  FIG. 15 , the pin layout provides for power at both a first voltage level (e.g., 1.8 volts) and a second voltage level (e.g., 1.2 volts, as shown at pins  75 ,  213 ,  79 ,  217 ). In this manner, the logic portion of the system may be operated independent of and/or prior to powering up the main memory portion of the system, thereby providing additional system memory usage flexibility and/or power savings.  
         [0059]     As described above, the embodiments of the invention may be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. Embodiments of the invention may also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiling or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits.  
         [0060]     While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, the use of the terms first, second, etc. do not denote any order or importance, but rather the ten-s first, second, etc. are used to distinguish one element from another.