Abstract:
A fast, parallel modular multiplier is presented which is scalable according to available hardware resources. Linear throughput increases with respect to consumed resources is achieved. Multiple independent data streams may be processed simultaneously, and optimal clock rates are attained by virtue of limited fan-out of all signal paths and nearest neighbor interconnections. Integrated circuit implementation is benefited by the potential for signal sharing among input and output busses and a common control interface for all independent data streams.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     Not applicable. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the processing of digital signals to render modular multiplication. 
     2. Description of Related Art 
     Modular multiplication, which is the computation of A·B modulo M where A, B, and M are integer values, is a fundamental mathematical operation in applications based on number-theoretic arithmetic. A central application area is cryptography, where techniques such as the popular RSA and DSS methods utilize modular multiplication as the elemental computation. Since large word lengths on the order of thousands of bits are typically processed, hardware approaches to modular multiplication are typically very slow. Existing art attempts to address this deficiency through a handful of approaches. 
     Linear systolic array approaches dominate the art, with the article C. Walter, “Systolic modular multiplication,” IEEE Transactions on Computers, v. 42, no. 3, pp. 376-378, 1993, being representative. In such an approach, a linear array of processing elements is connected so that all signal paths are formed between adjoining elements only. Thus, signal path lengths are minimized. Accordingly, all signal paths only connect two adjoining elements, guaranteeing unit fan out. The forgoing properties of systolic arrays ensure that the clock rate is determined solely by the processing element delay. However, efforts to scale the performance beyond the level offered by a single linear array have encountered very limited success. Cell optimization is the commonly applied technique to gain performance. However, performance scales only logarithmically with respect to consumed integrated circuit area. 
     Another method which attempts to provide a performance-area tradeoff is the digit-serial array. In the paper, J. Guo and C. Wang, “A novel digit-serial systolic array for modular multiplication,” in Proc. of the 1998 IEEE International Symposium on Circuits and Systems, v. 2, pp. 177-180, 1998, a digit-serial modular multiplier methodology was presented. However, the arrays were not pipelined, and thus the clock period of the digit-serial cells grows proportionally with digit size. Therefore, performance scaling occurs in a sub-linear fashion for small digit sizes and quickly saturates to yield negligible performance gains for large digit sizes. 
     A non-systolic array was presented in the article H. Orup, “Simplifying quotient digit determination in high-radix modular multiplication,” in Proc. of the 12th Symposium on Computer Arithmetic, pp. 193-199, 1995. A roughly linear performance-area tradeoff was achieved through retiming of the modular correction loop within the modular multiplication algorithm. However, the clock rate is severely limited by the required full-word-length signal broadcasts of the modular correction selection bit. Thus, the fan out of the aforementioned signal is the complete word length. Implementational efforts to increase the signal drive through transistor sizing destroys the linear performance-area trade off and only provide minor mitigation of the slow-clock-rate obstacle plaguing this methodology. 
     SUMMARY OF THE INVENTION 
     The present invention describes a method for parallel modular multiplication capable of processing multiple independent data streams simultaneously. 
     An implementation realizing this method consists of a cascade of full-word-length linear arrays of processing elements which each accept and generate bit-level data. Each processing element performs bit-wise partial product formation, modular correction formation, and summation of the generated partial product and modular correction bits with the right-single-bit-shifted result of the previous algorithmic iteration. The number of rows of the array cascade is determined in accordance with the available integrated circuit implementation area and the desired throughput performance, which scales linearly with row count. Data propagates in a feed-forward manner from row to row upon completion of the segment of iterations assigned to each row. 
     The data stream capacity and operational throughput are directly scalable with the available integrated circuit implementation area. This performance scalability is accomplished while maintaining a systolic paradigm, such that all interconnection paths are locally connected to neighboring processing elements and entail minimal fan out. Thus, the achievable clock rate is maximized and is dictated by the processing element delay rather than by long interconnect paths or loading due to multiple-gate fan out. Moreover, in contrast to isolated parallel modular multiplication arrays, the unified array structure of the present invention incorporates single input and output data buses, thereby reducing global integrated circuit wiring overhead. Additionally, the unified array permits a single controller to be utilized when the modular multiplier is utilized as a component in a higher-level functional unit such as a modular exponentiator. 
     OBJECTS AND ADVANTAGES OF THE INVENTION 
     The primary object of this invention is fast parallel processing of modular multiplication. 
     It is an advantage of this invention that multiple independent data streams may be simultaneously processed. The number of data streams is arbitrary, limited only by implementation area. 
     It is a primary advantage of this method that throughput performance scales linearly with the area of the integrated circuit implementation while maintaining the optimal systolic clock rate. The latter is attained through guaranteeing properties of purely nearest neighbor interconnections between processing elements and unit signal fan out. 
     It is an advantage of this invention that input and output data share signal lines such that the number of internal signal buses in an integrated circuit implementation are reduced. 
     It is an advantage of this invention that a unified control unit may be utilized when the modular multiplier unit is used in a modular exponentiator. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates the modular multiplier with its connections. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The preferred embodiment is delineated in FIG.  1 . It consists of a cascade of K linear systolic arrays of bit-wise processing cells, where K is chosen according to the amount of integrated circuit area available for the implementation. The value of K directly relates to the amount of parallelism implemented in the system. Each array is composed of N+1 cells, where N represents the word length of the modulus value in bits. 
     Each cell possesses a set of bit-wise inputs corresponding to the multiplicand, multiplier, modular correction, modular selection, partial sum, and two previous carry signals. Each cell also possesses a set of bit-wise outputs corresponding to the multiplicand, multiplier, modular correction, modular selection, generated partial sum, and two generated carry signals. Each inner cell  1  excluding the leftmost and rightmost peripheral cells in each array and all cells in the bottommost array, is interconnected within the structure in the following manner. The multiplicand output is delivered to input PRI of a multiplexed dual-delay element, whose output is connected to the multiplicand input of the cell under consideration. The multiplicand output also connects to the input SEC of a multiplexed dual-delay element whose output connects to the corresponding cell in the below-adjacent array. The multiplier output delayed by one cycle is connected to the left-adjacent cell&#39;s multiplier input. The modular correction output connects to input PRI of a multiplexed dual-delay element, whose output is connected to the modular correction input of the cell under consideration. The modular correction output also connects to the SEC input of a multiplexed dual-delay element, whose output connects to the modular correction input of the corresponding cell in the below-adjacent array. The modular selection output delayed by one cycle is connected to the left-adjacent cell&#39;s modular selection input. The generated partial sum output is connected to the PRI input of a multiplexed delay element whose output connects to the right-adjacent cell&#39;s partial sum input. The generated partial sum output also connects to the SEC input of a multiplexed delay element whose output connects to the partial sum input of the right-adjacent cell in the below-adjacent array. Finally, each of the two carry outputs delayed by one cycle is connected to the corresponding carry inputs of the left-adjacent cell. 
     Rightmost, least-significant cell  2  connections for the multiplicand and modular correction outputs are identical to the above description for the inner cells. However, the partial sum output connections differ. The partial sum output is connected to the PRI input of a multiplexed dual-delay element whose output is connected to the modular selection input. The partial sum output is also connected to the SEC input of a multiplexed dual-delay element associated with the below-adjacent array, whose output connects to the modular selection input of the corresponding cell. The multiplier input of a rightmost cell is supplied externally in the form of a serial, least-significant-bit first stream. Both carry inputs are connected to ground. 
     Leftmost, most-significant  3  cell connections for the multiplicand, modular correction, and partial sum outputs are identical to the inner cell description. The single carry output is connected to the PRI input of a multiplexed dual-delay element, whose output is connected to the partial sum input. The single carry output is also connected to the SEC input of a multiplexed dual-delay element, whose output is connected to the partial sum input of the corresponding cell in the below-adjacent array. 
     In the bottommost array  4 , modular selection and multiplier outputs are connected identically to the aforementioned inner cell description. The modular correction output is connected to the PRI input of a multiplexed dual-delay element, whose output is connected to the modular correction input. The multiplicand output is connected to the PRI input of a multiplexed dual-delay element, whose output is connected to the multiplicand input. The partial sum output is connected to the PRI input of a multiplexed delay element, whose output is connected to the partial sum input of the right-adjacent cell. 
     Each cell performs a computation which, for the purposes of illustration, may be decomposed into the following sequence of bit-wise operations. The multiplicand input bit is ANDed with the multiplier input bit. Similarly, the modular correction input bit is ANDed with the modular selection input bit. The outputs of the two aforementioned computations are added with the partial sum input and the two carry inputs. The least significant bit of the latter sum is connected to the cell&#39;s partial sum output, while the two bits generated in the most significant position are connected to the two carry outputs. The multiplicand, modular correction, multiplier, and modular selection inputs are also passed to the multiplicand, modular correction, multiplier, and modular selection outputs, respectively. Within each rightmost cell, all aspects of the above description remain valid except that only a single bit in the most significant position is generated. Thus, each rightmost cell possesses a single carry output. 
     A delay element  9  receives a single input and delays the signal presented in the current clock cycle until the subsequent clock cycle, and presents the delayed single to the output. 
     The multiplexed dual-delay element  5  takes in two data inputs, labeled PRI and SEC. An additional input SEL is used to multiplex data at the PRI and SEC inputs to the input of a delay register. De-assertion of the SEL input selects the PRI input, while assertion selects the SEC input. The output of the delay register is connected to another delay register, whose output is identically the output of the multiplexed dual-delay element. 
     Similarly, the multiplexed delay element  6  takes in two data inputs, labeled PRI and SEC. An additional input SEL is used to multiplex data at the PRI and SEC inputs to the input of a delay register. De-assertion of the SEL input selects the PRI input, while assertion selects the SEC input. The output of the delay register constitutes the output of the multiplexed delay element. 
     A counter  7  asserts the signal PASS_DATA  8  for two clock cycles every [(N+2)/K] clock cycles, where [ARGUMENT] denotes the next highest integer when the ARGUMENT is not an integer, otherwise [ARGUMENT]=ARGUMENT. The signal PASS_DATA is connected to the SEL input of each multiplexed delay element associated with each rightmost cell. De-assertion of the PASS_DATA signal selects the PRI input to the multiplexed delay element, whereas assertion selects the SEC input. Within each linear array, the PASS_DATA signal is also connected to a delay element associated with the rightmost cell, whose output connects to a corresponding delay element associated with the left-adjacent cell. Likewise, each inner cell accepts the PASS_DATA signal from the delay associated with the right-adjacent cell and outputs the signal to a delay element associated with the left-adjacent cell. 
     Initial data is supplied externally to the unit such that two new independent data sets commence processing every [(N+2)/K] clock cycles, coincident with the assertion of the PASS_DATA signal. Multiplicand and modular correction data bits are entered into the topmost array in the following manner. The rightmost cell receives the modular correction, multiplicand and multiplier bits associated with the first of the two currently entering data streams upon the first clock cycle wherein PASS_DATA is asserted. Upon the next clock cycle, the modular correction multiplicand and multiplier bits associated with the second of two currently entering data streams are received. In subsequent cycles, the rightmost cell receives the next most significant multiplier bit associated with the first data stream if the clock cycle number is even, and with the second stream if the clock cycle number is odd. Multiplicand and modular correction bits are no longer externally entered into the array in the rightmost cell position until the next assertion of the PASS_DATA signal, at which point two new data streams are commenced. An arbitrary cell in column J of the topmost array externally receives the corresponding modular correction and multiplicand bits associated with the first data stream J clock cycles after PASS_DATA is asserted. Modular correction and multiplicand bits associated with the second data stream are received J+1 cycles after the assertion of the PASS_DATA signal. The leftmost cell of the topmost array receives the corresponding multiplicand bit associated with the first data stream N cycles after the assertion of PASS_DATA. Similarly, the leftmost cell receives the multiplicand bit associated with the second stream N+1 cycles after the assertion of PASS_DATA. The modular correction input associated with the leftmost cell of the topmost array is grounded. 
     An illustration of the modular multiplier array cascade for the K=4, N=5 case is shown in FIG.  1 . Arrays for other parameterizations should be evident to an individual in the field with a grasp of the above description.