Abstract:
Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to the field of micro-electronics that include fin formations (for example, FINFETs (“Fin field effect transistors”)). 
     A FINFET is a nonplanar, double-gate transistor built on an SOI (silicon on insulator) substrate. The distinguishing characteristic of the FINFET is that the conducting channel passes orthogonally through an elongated, relatively high, relatively thin, fin structure. Typically, the fin structure is made of silicon, although Silicon-Germanium (SiGe) fins are also known. This fin structure forms the body of the device. The thickness of the fin (measured in the direction from source to drain) determines the effective “channel length” of the device. FINFETs can provide better electrical control over the channel, reduce the leakage current and avoid certain unfavorable short-channel effects associated with non-FINFET devices. As used herein, the term “FINFET” means any transistor device with a fin structure located between its source(s) and drain(s), regardless of the number of gates. 
     It is currently conventional to form SiGe fins by growing a blanket layer (or block) of SiGe and then cutting away material to form the fin structures by SIT (sidewall image transfer). 
     SUMMARY 
     According to an aspect of the present invention, a method of refining a semiconductor device under construction includes the following operations (not necessarily in the following order and it is noted that operations may overlap in time): (i) providing an uncovered intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer, with the base layer including a top surface and the first fin structure including a first lateral surface and a second lateral surface; (ii) refining the uncovered intermediate sub-assembly into a covered intermediate sub-assembly by covering at least a portion of the top surface of the base layer of the uncovered intermediate sub-assembly and at least a portion of the first and second lateral surfaces of the first fin structure of the uncovered intermediate sub-assembly with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) refining the covered intermediate sub-assembly into a thermally-oxidized intermediate sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of the first fin structure, thereby changing the pre-thermal oxidation layer into a post-thermal oxidation layer. 
     According to a further aspect of the present invention, a method of refining a semiconductor device under construction includes the following operations (not necessarily in the following order and it is noted that operations may overlap in time): (i) providing an uncovered intermediate sub-assembly including a silicon-containing base layer and a plurality of parallel silicon-containing fin structures each extending in an upwards direction from the base layer, with the base layer including a top surface and each fin structure, of the plurality of fin structures, including a first lateral surface and a second lateral surface; (ii) refining the uncovered intermediate sub-assembly into a covered intermediate sub-assembly by covering at least a portion of the top surface of the base layer of the uncovered intermediate sub-assembly and at least a portion of the first and second lateral surfaces of each fin structure, of the plurality of fin structures of the uncovered intermediate sub-assembly with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) refining the covered intermediate sub-assembly into a thermally-oxidized intermediate sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of each fin structure, of the plurality of fin structures, thereby changing the pre-thermal oxidation layer into a post-thermal oxidation layer. 
     According to a further aspect of the present invention, a semiconductor device under construction includes: a substrate layer; a buried oxide layer; and a first fin structure. The buried oxide layer is located over at least a portion of the substrate layer. The first fin structure is located over a portion of the buried oxide layer. The first fin structure includes Silicon-Germanium (SiGe). The first fin structure is at least 40 nanometers in height. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a cross-sectional view of a first embodiment of a semi-conductor device according to the present invention as it is being fabricated; 
         FIG. 1B  is another cross-sectional view of the first embodiment of a two fin semi-conductor device as it is being fabricated; 
         FIG. 1C  is another cross-sectional view of the first embodiment of a two fin semi-conductor device as it is being fabricated; 
         FIG. 1D  is another cross-sectional view of the first embodiment of a two fin semi-conductor device as it is being fabricated; 
         FIG. 1E  is another cross-sectional view of the first embodiment of a two fin semi-conductor device as it is being fabricated; 
         FIG. 1F  is another cross-sectional view of the first embodiment of a two fin semi-conductor device as it is being fabricated; 
         FIG. 1G  is another cross-sectional view of the first embodiment of a two fin semi-conductor device as it is being fabricated; 
         FIG. 2  is cross-sectional view of a semi-conductor device helpful in understanding the present invention; and 
         FIG. 3  is a cross-sectional view of a semi-conductor device helpful in understanding the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Some embodiments of the present invention are directed to SiGe (silicon germanium) fins for 10 nm (nanometer) technology node FINFETs (fin field effect transistors) to boost pFET (p-type field effect transistor) performance. Some embodiments of the present invention provide a way to robustly form a device with high aspect ratio gate. 
     Some embodiments of the present invention recognize several challenges for forming SiGe fins: (i) the critical thickness of 25% Ge (germanium) is about 30 nm, less than the fin height requirement for 10 nm (50 nm Hfin (fin height) is needed); (ii) designs that epitaxy SiGe on Si (silicon) fin sidewalls and then perform thermal condensation are subject to the following potential problems: (a) after cladding the oxide on SiGe fin sidewalls has to be removed, but removing oxide from fin sidewalls inevitably attacks BOX (buried oxide layer), causing fin liftoff, and (b) faceted epi (epitaxy) at bottom of Si fin results in non-uniform SiGe fin width, which, in turn, can lead to barrel-shaped SiGe fins. Some embodiments of the present invention recognize one, or more, of the following problems with respect to currently conventional ways of forming SiGe fins: (i) some problems are related to a critical thickness of SiGe grown on Si; (ii) fabrication of silicon germanium alloy fins having 25 atomic percent or greater of germanium is challenging due to the critical thickness of the silicon germanium alloy films with increasing germanium content; and (iii) as an example of the previous item on this list, silicon germanium alloys containing 25 atomic percent to 60 atomic percent germanium have a critical thickness of from 25 nm (nanometers) to 35 nm, and above this critical thickness, defects form to partially relieve the strain in the silicon germanium alloy. 
     Some embodiments of the present application provides a method for forming silicon germanium alloy fins containing 25 atomic percent or greater germanium. Such silicon germanium alloy fins containing 25 atomic percent or greater germanium are referred to herein as “high percentage silicon germanium (SiGe) fins.” 
     Some embodiments of the present invention may include one, or more, of the following features, characteristics and/or advantages: (i) high Ge % SiGe fins (that is, fins made of SiGe with a relatively large proportion of Ge) can be formed with the fin height exceeding the critical thickness of SiGe of SiGe fins form by prior art methods (cut out of block); (ii) no BOX undercut; and/or (iii) more uniform SiGe fins. 
     A method of fabricating a fin-based micro electronics device, according to the present invention, will now be discussed with reference to  FIG. 1A to 1G  (respectively showing intermediate assemblies  100   a  to  100   g ). 
     As shown in  FIG. 1A , assembly  100   a  is first provided, including: oxide (also called hardmask) layer  102   a ; silicon nitride (SiN) layer  104   a ; silicon-on-insulator (SOI) layer  106   a  (in this example, the SOI layer is ˜50 nm in thickness); buried oxide (BOX) layer  108   a ; and substrate layer  110   a . SiN layer  104   a  is a pad film. Hardmask layer  102   a ,  103   a  is formed by any fin patterning method now known (for example, SIT (sidewall image transfer (lithography fin patterning method)) or to be developed in the future. Intermediate sub-assembly  100   a  is an example of a type of sub-assembly sometimes referred to herein as a “finless intermediate sub-assembly.” 
     As shown by comparing  FIGS. 1A and 1B , intermediate assembly  100   a  is transformed into intermediate assembly  100   b , including: SiN layer  104   b ; SOI layer  106   b  (including flat portion  105   b  and upstanding portions  107   b ); BOX layer  108   b ; and substrate layer  110   b . More specifically, intermediate assembly  100   a  is transformed into intermediate assembly  100   b  by: (i) removing exposed areas of the SiN layer and part of the exposed areas of the SOI layers by reactive ion etching; and (ii) removing hardmask layer  102   a  by wet etch stripping using HF (aqueous hydrofluoric acid). More specifically, in this example, the reactive ion etching process is controlled so that exposed areas of the SOI layer are reduced from about 50 nm to about 10 nm in thickness. Intermediate sub-assembly  100   b  is an example of a type of sub-assembly sometimes herein referred to as an “uncovered intermediate sub-assembly.” 
     As shown by comparing  FIGS. 1B and 1C , intermediate assembly  100   b  is transformed into intermediate assembly  100   c , including: SiN layer  104   c ; SOI layer  106   c  (including flat portion (no separate reference numeral) and upstanding portions  107   c ); BOX layer  108   c ; substrate layer  110   c ; and pre-thermal oxidation SiGe layer  112   c . More specifically, intermediate assembly  100   b  is transformed into intermediate assembly  100   c  by epitaxially growing SiGe layer  112   c  over the exposed surfaces of SOI layer  106   c . The SiGe growth is like eSiGe (embedded silicon-germanium) growth so that the fin bottom is not faceted. Intermediate sub-assembly  100   c  is an example of a type of sub-assembly sometimes referred to herein as a “covered intermediate sub-assembly.” 
     Some sample profiles of the SiGe layer are shown at  FIG. 2  (assembly  400  including SOI layer  406 , pre-thermal oxidation SiGe layer  412 , gate  414 , and gate spacer  416 ) and  FIG. 3  (intermediate assembly  500 ). 
     As shown by comparing  FIGS. 1C and 1D , intermediate assembly  100   c  is transformed into intermediate assembly  100   d , including: SiN layer  104   d ; BOX layer  108   d ; substrate layer  110   d ; silicon dioxide layer  150   d ; and post-thermal oxidation SiGe layer  152   d . Sub-assembly  100   d  is an example of a type of sub-assembly sometimes referred to herein as a “thermally-oxidized intermediate sub-assembly.” 
     More specifically, intermediate assembly  100   c  is transformed into intermediate assembly  100   d  by performing thermal oxidation (that is, SiGe condensation) so that some of the Ge atoms of pre-thermal oxidation SiGe layer  112   c  diffuse: (i) out of pre-thermal oxidation SiGe layer  112   c  to form silicon dioxide layer  150   d  (because oxygen atoms displace Ge atoms in layer  150   d  as a result of the condensation; and (ii) into SOI layer  106   c  to form post-thermal oxidation SiGe layer  152   d  (while post-thermal oxidation SiGe layer  152   d  is referred to here as a “layer,” as can be seen in  FIG. 1D , this “layer” includes tall, thin fin structure portions). To explain item (i) on the foregoing list in fuller and more precise terms, oxidation and condensation happens at the same time. Once the semiconductor fabrication process anneals the structure, the Ge diffuses into the Si-fin. At the same time the Si oxidizes at the fin surface, forming silicon oxide. Silicon gets preferably oxidized compared to the Ge due to the electronegativity (this can be seen from the Periodic Table Of The Elements). So, while the Si oxidizes, it gets consumed, increasing the Ge at the surface. Due to the Ge gradient, the Ge has a tendency to diffuse into a region of lower Ge concentration. Similarly, the Si tends to diffuse towards a region of lower Si concentration. Accordingly, the Ge goes toward the fin center, whereas the Si goes to the fin surface, where it is consumed by oxidation. 
     An example of a thermal oxidation process, of a type that can be used in conjunction with some embodiments of the present invention, will now be discussed. The thermal condensation is a thermal oxidation process that is performed at temperature sufficient enough to cause diffusion of germanium out of an epitaxial SiGe layer and into a pure silicon (or SiGe) layer. In this example, the thermal condensation is performed at a temperature from 700° C. to 1300° C. In another example, the thermal condensation is performed at a temperature from 1000° C. to 1200° C. In this example, the thermal condensation is performed in an oxidizing ambient which includes at least one oxygen-containing gas such as O2, NO, N2O, ozone, air and other like oxygen-containing gases. The oxygen-containing gas may be admixed with each other (such as an admixture of O2 and NO), or the gas may be diluted with an inert gas such as He, Ar, N 2 , Xe, Kr, or Ne. In this example, the thermal condensation process may be carried out for a variable period of time. Typically, the thermal condensation process is carried out for a time period from 5 seconds to about 5 hours, depending on thermal oxidation temperature and oxidation species. The thermal condensation process may be carried out at a single targeted temperature, or various ramp and soak cycles using various ramp rates and soak times can be employed. 
     As shown by comparing  FIGS. 1D and 1E , intermediate assembly  100   d  is transformed into intermediate assembly  100   e , including: SiN layer  104   e ; BOX layer  108   e ; substrate layer  110   e ; and post-thermal oxidation SiGe layer  152   e . More specifically, intermediate assembly  100   d  is transformed into intermediate assembly  100   e  by wet etch stripping silicon dioxide layer  150   d  using HF. Note that BOX layer  108   e  is protected by post-thermal oxidation SiGe  152   e  layer during this oxide strip process, so no BOX undercut occurs in this example. Intermediate sub-assembly  100   e  is an example of a type of sub-assembly sometimes herein referred to as an “oxidation-by-product-free intermediate sub-assembly.” 
     As shown by comparing  FIGS. 1E and 1F , intermediate assembly  100   e  is transformed into intermediate assembly  100   f , including: SiN layer  104   f ; BOX layer  108   f ; substrate layer  110   f ; and post-thermal oxidation SiGe layer  152   f . More specifically, exposed areas of post-thermal oxidation SiGe layer  152   e  are removed by reactive ion etching (RIE) so that only the upstanding portions (that is, the fin structures) remain in post-thermal oxidation SiGe layer  152   f . As can be seen by comparing  FIGS. 1E and 1F , SiN layer  104   e  is used as a mask during the RIE. Intermediate sub-assembly  100   f  is an example of a type of sub-assembly sometimes herein referred to as a “base-layer-free intermediate sub-assembly.” 
     As shown by comparing  FIGS. 1F and 1G , intermediate assembly  100   f  is transformed into intermediate assembly  100   g , including: BOX layer  108   g ; substrate layer  110   g ; and post-thermal oxidation SiGe layer  152   g  (also referred to as “SiGe fins”). More specifically, SiN layer  104   f  is wet etch stripped away using hot phosphoric acid to expose the top surfaces of SiGe fins  152   g . Intermediate sub-assembly  100   g  is an example of a type of intermediate sub-assembly sometimes herein referred to as an “unmasked-SiGe-fin intermediate sub-assembly.” 
     Some embodiments of the present invention may include one, or more, of the following features, characteristics and/or advantages: (i) no BOX undercut; (ii) more uniform SiGe fins; (iii) enable tall SiGe fins with high Ge %; (iv) method and structure for tall uniform SiGe fins without BOX gauging; and/or (v) formation of a SiGe FINFET on SOI. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 
     The following paragraphs set forth some definitions for certain words or terms for purposes of understanding and/or interpreting this document. 
     Present invention: should not be taken as an absolute indication that the subject matter described by the term “present invention” is covered by either the claims as they are filed, or by the claims that may eventually issue after patent prosecution; while the term “present invention” is used to help the reader to get a general feel for which disclosures herein are believed to potentially be new, this understanding, as indicated by use of the term “present invention,” is tentative and provisional and subject to change over the course of patent prosecution as relevant information is developed and as the claims are potentially amended. 
     Embodiment: see definition of “present invention” above—similar cautions apply to the term “embodiment.” 
     and/or: inclusive or; for example, A, B “and/or” C means that at least one of A or B or C is true and applicable.