Abstract:
Embodiments of the invention provide a radiation detector comprising a pixel element, the pixel element comprising: a first diode element having a node capacitance associated therewith, the element being operable to pass electrical charge therethrough between terminals thereof in response to incident radiation; and an auxiliary charge storage reservoir, wherein the detector is operable by means of charge transfer between the auxiliary charge storage reservoir and a first terminal of the first diode element to reduce a rate at which an electrical potential V X  of the first terminal changes in response to a cumulative amount of incident radiation.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to radiation detectors and to a method of detecting radiation. In particular but not exclusively the invention relates to radiation detectors for imaging devices where an array of radiation detectors is arranged to capture an image of a subject. 
       BACKGROUND 
       [0002]    It is known to provide an imaging device having a radiation detector in the form of a two dimensional array of pixels or pixel elements, each pixel element having a radiation sensor element for detecting radiation incident thereon. An image of a subject may be obtained by the device by projecting radiation onto the detector and determining the relative amounts of radiation incident upon each pixel element over a prescribed time period. 
         [0003]    Known detectors include CMOS (complementary metal oxide semiconductor) detectors, CCD (charge coupled device) detectors, image intensifiers and the like. CMOS and CCD detectors are commonly used in domestic hand-held electronic devices such as mobile telephones and video cameras. 
         [0004]    Such devices also find application in scientific instrumentation apparatus such as medical imaging systems, electron microscopes including transmission electron microscopes, medical and biological imaging applications, space imaging applications and security applications. 
         [0005]      FIG. 1  is a schematic circuit diagram of a known CMOS active pixel element  100  also referred to as a 3T (three transistor) active pixel. The pixel element  100  has a radiation sensor element in the form of a photodiode  110  and three MOS transistors: a reset transistor  121 , a source-follower input transistor  131  and a selection (‘select’) transistor  141 . Source-follower input transistor  131  forms a source follower arrangement with current bias portion  150  which comprises a current mirror arrangement. The source-follower input transistor  131  may also be referred to as a source follower transistor  131 . 
         [0006]    Each of the transistors  121 ,  131 ,  141  has a source, a gate and a drain terminal. 
         [0007]    The source of the reset transistor  121  is connected to a node X whilst the drain is connected to a supply of potential V RST . The gate of the reset transistor  121  is connected to a reset signal line RST. The gate, source and drain of the source-follower input transistor  131  are respectively connected to the node X, the drain of the selection transistor  141  and a supply of reference voltage V DD . The gate of the selection transistor  141  is connected to a row select line ROW and the source of the selection transistor  141  is connected to a column readout line COL. 
         [0008]    It is to be understood that the source-follower input transistor  131  is arranged to act as a buffer of the signal applied to the gate thereof. When the current flow through the source-follower input transistor  131  is kept constant by an appropriate bias applied by the current bias portion  150  then, neglecting the second order effect of the activated selection transistor  141 , the output voltage on the column readout line COL at terminal T is proportional to the potential applied to the gate of the source-follower input transistor  131  but with a much lower equivalent output impedance. 
         [0009]    In operation, reset signal line RST is set HIGH (i.e. assumes a logical 1 condition) causing the reset transistor  121  to turn ON (i.e. the channel of the reset transistor  121  becomes conducting) and a potential V x  of the floating node ‘X’ is set to V RST . When the potential at V x  is set to V RST , the photodiode  110  stores charge therein due to the node capacitance of the photodiode  110 , a region of space charge associated with the photodiode  110  being increased. 
         [0010]    The reset signal line RST is then set LOW (i.e. controlled to assume a logical 0 condition) causing reset transistor  121  to turn OFF. 
         [0011]    Radiation incident on the diode  110  is converted to mobile electron-hole pairs within the diode  110  causing a current to flow through the diode, discharging the charge accumulated by the photodiode  110  when the reset signal was applied. This in turn causes a change in V x . 
         [0012]    When it is required to read out V x  the row of the pixel  100  of  FIG. 1  is selected by turning ON the selection transistor  141  (i.e. row line ROW is set HIGH). A signal corresponding to V x  is then applied by the selection transistor  141  to the column line COL which may also be referred to as an output line OUTP. The column line COL is in turn connected to signal processing electronics which reads out the potential at an output terminal T of the column line COL. 
         [0013]    Periodically, reset signal line RST is set HIGH, connecting floating node X to V RST  via reset transistor  121  and refreshing the amount of charge stored by the photodiode  110  due to its node capacitance. The potential at node X is thereby reset to V RST . 
         [0014]    Applying V RST  to the diode  110  biases the diode  110  and therefore V RST  may be referred to as a bias voltage. In the embodiment of  FIG. 1  V RST  is arranged to reverse bias the diode  110  to increase the width of the depletion layer and improve detection response time. Furthermore it should be noted that the higher the reset voltage the more charge may be collected by the photodiode  110  before saturation. 
         [0015]    It is to be understood that in the arrangement of  FIG. 1  V X  is monotonically dependant on the cumulative number of photo-generated electrons collected by the diode  110 , which is in turn typically monotonically dependant on the level of illumination, specifically the illuminance (the total incident luminous flux, per unit area). 
         [0016]    When the amount of accumulated charge at the diode  110  falls to a sufficiently low value V X  ceases to change with further illumination and the diode  110  may be considered to be ‘saturated’. 
         [0017]    It is to be understood that the amount of charge passed by the diode before reaching saturation depends on the node capacitance of the diode  110 . The larger the node capacitance, the more charge can be passed by the diode  110  before saturation conditions are reached, and the greater the dynamic range of the pixel element  100 . However, increasing the node capacitance causes an increase in the sampling noise (reset noise on node X) in the output signal of the pixel element  100  (i.e. the total potential read out at column line COL) reducing the signal to noise ratio (SNR). Therefore, in the device shown in  FIG. 1  there is a trade-off between dynamic range and noise. 
         [0018]    It is desirable to improve the dynamic range of pixels of radiation detectors to reduce a risk of saturation of the pixels  100  under high intensity illumination conditions without reducing the SNR. 
         [0019]    Furthermore it is also desirable to reduce a problem of image gradient effects due to a drop in potential across output signal lines of pixel element arrays. 
         [0020]    It is also desirable to enhance operational functionality of a radiation detector comprising a pixel element array. 
         [0021]    Embodiments of the invention endeavour to mitigate at least one of the disadvantages of known radiation detectors. 
       STATEMENT OF THE INVENTION 
       [0022]    Embodiments of the invention may be understood by reference to the appended claims. 
         [0023]    Aspects of the invention provide a detector and a method as claimed in the appended claims. 
         [0024]    In another aspect of the invention for which protection is sought there is provided a radiation detector comprising a pixel, the pixel comprising:
       a first diode element operable to pass electrical charge therethrough between terminals thereof in response to incident radiation; and   an auxiliary charge storage reservoir,   wherein the detector is operable to transfer charge between the auxiliary charge storage reservoir and a first terminal of the first diode element thereby to reduce a rate at which an electrical potential V X  of the first terminal changes in response to the cumulative amount of radiation incident thereon.       
 
         [0028]    Embodiments of the invention have the advantage that a dynamic range of a detector may be increased by the addition of an auxiliary charge storage reservoir. 
         [0029]    The first diode element may have a diode (or node) capacitance associated therewith. 
         [0030]    In a further aspect of the invention for which protection is sought there is provided a radiation detector comprising a pixel element, the pixel element comprising:
       a first diode element having a node capacitance associated therewith, the element being operable to pass electrical charge therethrough between terminals thereof in response to incident radiation; and   an auxiliary charge storage reservoir,   wherein the detector is operable by means of charge transfer between the auxiliary charge storage reservoir and a first terminal of the first diode element to reduce a rate at which an electrical potential V X  of the first terminal changes in response to a cumulative amount of incident radiation.       
 
         [0034]    Advantageously the pixel element is arranged such that V X  is responsive to the amount of charge stored by the node capacitance of the first diode element. 
         [0035]    V X  may be responsive to the amount of charge in stored in the first diode element due to the node capacitance thereof and the amount of charge stored in the auxiliary charge storage reservoir, which may advantageously be a capacitor. 
         [0036]    Further advantageously the detector is operable to couple a first terminal of the auxiliary charge storage reservoir to the first terminal of the diode element when V X  falls below a potential V F  of the first terminal of the charge storage reservoir. 
         [0037]    The detector may be operable to set V X  to one of a first reset value and a second reset value. 
         [0038]    The detector may be operable to set V F  to one of a first reset value and a second reset value. 
         [0039]    The detector may be operable to set V X  to a first reset value and V F  to a second reset value. 
         [0040]    Optionally the first reset value is greater than the second reset value. 
         [0041]    Alternatively the first reset value may be substantially equal to the second reset value. 
         [0042]    In a further alternative the first reset value may be less than the second reset value. 
         [0043]    Advantageously the auxiliary charge reservoir is coupled to the first diode element by means of a second diode element. 
         [0044]    The second diode element may comprise a transistor device. 
         [0045]    The detector may be operable to couple the auxiliary charge reservoir to the first diode element by means of a second diode element. 
         [0046]    This has the advantage that the detector may be decoupled from the auxiliary charge reservoir. 
         [0047]    The detector may be operable to couple the auxiliary charge reservoir to the first diode element thereby to permit bidirectional current flow therebetween. 
         [0048]    Advantageously the detector comprises an array of pixel elements, the array comprising at least one column comprising a plurality of pixel elements, each pixel element comprising a source follower input transistor having a gate terminal coupled to the first terminal of the first diode element thereof whereby a potential may be applied to the gate terminal of the source follower input transistor, the potential being responsive to the cumulative amount of incident radiation incident on the pixel element. 
         [0049]    Whilst the pixel elements have been described as being in the form of a column, it is to be understood that in some arrangements the pixel elements may be described as being in a row, being equivalent to a column, whilst still falling within the scope of the present invention for which protection is sought. A column or row of pixel elements need not be a straight column or row, but may be non-linear, for example curved, or any other suitable arrangement or distribution. 
         [0050]    Advantageously a source of each input transistor of the at least one column is connectable by means of a respective bias line select transistor to a bias current signal line having a bias current portion connected thereto, the bias current portion being configured to apply a bias current to the bias current signal line, wherein the source follower input transistor and bias current portion form a source follower arrangement via the bias line select transistor,
       the source of the source follower input transistor of each pixel element being further connectable by means of a respective output line select transistor to an output signal line separate from the bias signal line.       
 
         [0052]    The bias current signal line may be a common bias current signal line of a given column. The output signal line may be a common output signal line of a given column. 
         [0053]    It is to be understood that by connecting the source of the source follower input transistor to the bias current signal line and the output signal line, the potential of the output signal line may be caused to follow that of the potential applied to the gate terminal of the source follower input transistor. 
         [0054]    Embodiments of the invention have the advantage that an output potential at an output terminal T of the output signal line, having a potential responsive to the amount of radiation incident on a given pixel element of a column, is not modified due to a line resistance associated with the output line. This is because a potential of the output line may be measured without drawing current through the output signal line. 
         [0055]    It is to be understood that in prior art circuits where current is drawn through the output signal line, a drop in potential between the source of a given source follower input transistor and an output terminal of the output signal line may occur due to the line resistance associated with the output signal line. This reduces the value of the potential measured at the output terminal. In the case of a 2D array of pixel elements used to capture a 2D image associated with incident radiation, a gradient in image intensity may be found to be superimposed on captured image data due to line resistance. It is to be understood that the longer the length of line between a given source follower input transistor and the output terminal of the corresponding output signal line, the greater the drop in potential suffered at the output terminal. This drop in potential may result in the introduction of artefacts into captured images, such as the intensity gradient referred to above. 
         [0056]    Advantageously the detector comprises a plurality of columns of pixel elements, each column having: a respective bias signal line having a bias portion; and a respective output signal line. 
         [0057]    It is to be understood that the detector may be considered to comprise rows of pixel elements forming a row of columns of pixel elements. The detector may be operable to read out the potential at the source of a source follower input transistor of each pixel element of a row of pixel elements to a respective column output signal line, i.e. one pixel element per column. The detector may be operable to read out the potentials row by row in sequence thereby to read out the potential at the source of each source follower input transistor of an array. 
         [0058]    Advantageously the column comprises respective first and second bias current signal lines connectable by means of respective first and second bias line select transistors to the source of the source follower. 
         [0059]    This feature has the advantage for example that respective different bias current signals may be applied to a source follower input transistor of a given pixel element at different moments in time. 
         [0060]    Optionally each bias current signal line has a respective bias current portion. 
         [0061]    Advantageously the column comprises respective first and second output signal lines connectable by means of respective first and second output line select transistors to the source of the source follower. 
         [0062]    Thus the detector may be operable to read out a potential corresponding to a cumulative amount of incident radiation on a pixel element to two different output signal lines. 
         [0063]    Advantageously the detector is operable to apply the potential at the source of the source follower input transistor of a given pixel element of a column to both the first and second output lines at the same moment in time. 
         [0064]    Thus the potential at the source of the source follower input transistor may be applied to both output lines substantially simultaneously. 
         [0065]    Advantageously the detector is operable to connect only one bias current signal line to the source of the source follower when more than one output signal line is connected to the source of the source follower input transistor. 
         [0066]    It is to be understood that if both bias current signal lines are coupled to the source of the source follower transistor the current flow through the source follower will be substantially equal to the sum of the currents flowing through the respective bias current portions of the bias current lines, resulting in an erroneous measure of the amount of radiation detected by a given pixel element. 
         [0067]    Advantageously the or each bias current portion comprises a constant current source. 
         [0068]    Optionally each pixel element comprises a plurality of source follower input transistors coupled to the first terminal of the first diode, the circuit being operable to cause a bias current to flow through each source follower input transistor via a bias current portion thereby to provide a plurality of respective source follower arrangements. 
         [0069]    Embodiments of the present invention allow a plurality of output terminals to be provided for a single pixel element in a convenient manner. 
         [0070]    The bias current portion may comprise a current mirror arrangement. 
         [0071]    Advantageously the source of each source follower input transistor is coupled to a bias current signal line whereby the bias current may be provided. 
         [0072]    Optionally the source of each source follower input transistor is coupled to the bias current signal line by means of a select transistor operable to connect and disconnect the input transistor from the bias current signal line. 
         [0073]    Advantageously the source of each source follower is coupled to a respective different bias current signal line by means of a respective different bias current signal line select transistor. 
         [0074]    Advantageously the detector comprises a column of pixel elements, the source of each of the plurality of source follower input transistors of each pixel element of the column being connectable to a respective output signal line by means of a respective output signal line select transistor. 
         [0075]    Advantageously corresponding source follower input transistors of respective pixels of a column of pixels share a common output signal line. 
         [0076]    That is, first source follower input transistors of each pixel element of a column share a common first output signal line whilst second source follower input transistors of each pixel element of a column share a second common output signal line different from the first, and so forth if there are more than two source follower input transistors per pixel element. 
         [0077]    Advantageously electrical connections to each of the bias signal lines and each of the output signal lines of the detector are provided along a single common side of the detector. 
         [0078]    Thus electrical connection may be made to the bias current signal lines and output signal lines along a single common side (or edge) of the detector. 
         [0079]    In a further aspect of the invention there is provided a detector assembly comprising a plurality of detectors according to the preceding aspect. 
         [0080]    Advantageously the assembly comprises first, second, third and fourth detectors each having four sides, the first detector having the second to fourth detectors arranged to abut three respective sides thereof, wherein electrical connection to the bias current signal lines and output signal lines of the first detector is provided along a free edge of the first detector being the edge not having any one of the second to fourth detectors in abutment therewith. 
         [0081]    In another aspect of the invention for which protection is sought there is provided a method of detecting radiation comprising:
       passing electrical charge through a first diode element having a node capacitance associated therewith between terminals thereof in response to incident radiation; and   transferring charge between an auxiliary charge storage reservoir and a first terminal of the first diode element thereby to reduce a rate at which an electrical potential V X  of the first terminal changes in response to a cumulative amount of radiation incident thereon.       
 
         [0084]    Advantageously the method comprises the step of storing charge within the first diode element by means of the node capacitance thereof, the step of passing electrical charge through the first diode element comprising the step of charge stored within the first diode element through the first diode element thereby to discharge the stored charge. 
         [0085]    In a further aspect of the invention for which protection is sought there is provided a method of detecting radiation comprising:
       passing electrical charge through a first diode element between terminals thereof in response to incident radiation; and   transferring charge between an auxiliary charge storage reservoir and a first terminal of the first diode element thereby to reduce a rate at which an electrical potential V X  of the first terminal changes in response to the amount of radiation incident thereon.       
 
         [0088]    Advantageously the method may comprise the step of storing charge in charge storage means within the first diode element. 
         [0089]    Further advantageously V X  is responsive to the amount of charge in stored in the first diode element due to the charge storage means and the amount of charge stored in the auxiliary charge storage reservoir. 
         [0090]    Still further advantageously the method may comprise the step of coupling a first terminal of the auxiliary charge storage reservoir to the first terminal of the diode element when V X  falls below a potential V F  of the first terminal of the charge storage reservoir. 
         [0091]    In one aspect of the invention for which protection is sought there is provided a detector comprising an array of pixel elements, the array comprising a column of pixel elements, each pixel element comprising a source follower input transistor,
       wherein each pixel element is operable to apply a potential to a gate terminal of the source follower input transistor thereof, the potential having a value responsive to a cumulative amount of charge carriers generated by the pixel element responsive to incident radiation, a source of each source follower input transistor being connectable by means of a respective bias line select transistor to a bias current signal line of the column having a bias current portion connected thereto, wherein the source follower input transistor and bias current portion form a source follower arrangement via the bias line select transistor,   the source of the source follower input transistor of each pixel element being further connectable by means of a respective output line select transistor to an output signal line of the column separate from the bias signal line.       
 
         [0094]    It is to be understood that by connecting the source of the source follower input transistor to the bias current signal line and the output signal line, the potential of the output signal line may be caused to follow that of the potential applied to the gate terminal of the source follower input transistor. 
         [0095]    Embodiments of the invention have the advantage that an output potential at an output terminal T of the output signal line, having a potential responsive to the amount of radiation incident on a given pixel element, is not modified due to a line resistance associated with the output line. This is because a potential of the output line may be measured without drawing current through the output signal line. 
         [0096]    It is to be understood that in prior art detectors where current is drawn through the output signal line, a drop in potential between the source of a given source follower input transistor and an output terminal of the output signal line may occur due to the line resistance associated with the output signal line. This reduces the value of the potential measured at the output terminal. In the case of a 2D array of pixel elements used to capture a 2D image associated with incident radiation, a gradient in image intensity may be found to be superimposed on captured image data due to line resistance. It is to be understood that the longer the length of line between a given source follower input transistor and the output terminal of the corresponding output signal line, the greater the drop in potential suffered at the output terminal. This drop in potential results in the introduction of artefacts into captured images, such as the intensity gradient referred to above. 
         [0097]    Advantageously the detector comprises a plurality of columns of pixel elements, each column having: a respective bias signal line having a bias portion; and a respective output signal line. 
         [0098]    Advantageously the column comprises respective first and second bias current signal lines connectable by means of respective first and second bias line select transistors to the source of the source follower. 
         [0099]    Optionally each bias current signal line has a respective bias current portion. 
         [0100]    Advantageously the column comprises respective first and second output signal lines connectable by means of respective first and second output line select transistors to the source of the source follower. 
         [0101]    Advantageously the detector is operable to apply the potential at the source of the source follower input transistor to both the first and second output lines at the same moment in time. 
         [0102]    Thus the potential at the source of the source follower input transistor may be applied to both output lines substantially simultaneously. 
         [0103]    Advantageously the detector is operable to connect only one bias current signal line to the source of the source follower when more than one output signal line is connected to the source of the source follower input transistor. 
         [0104]    It is to be understood that if both bias current signal lines are coupled to the source of the source follower transistor the current flow through the source follower will be substantially equal to the sum of the currents flowing through the respective bias current portions of the bias current lines, resulting in an erroneous measure of the amount of radiation detected by a given pixel element. 
         [0105]    Optionally the or each bias current portion comprises a constant current source. 
         [0106]    Advantageously electrical connections to each of the bias signal lines and each of the output signal lines of the detector are provided along a single common side of the detector. 
         [0107]    In a further aspect of the invention there is provided a detector assembly comprising a plurality of detectors according to a preceding aspect. 
         [0108]    Advantageously the assembly comprises first, second, third and fourth detectors each having four sides, the first detector having the second to fourth detectors arranged to abut three respective sides thereof, wherein electrical connection to the bias current signal lines and output signal lines of the first detector is provided along a free edge of the detector not having any one of the second to fourth detectors in abutment therewith. 
         [0109]    In one aspect of the invention for which protection is sought there is provided a detector comprising a pixel element comprising a plurality of source follower input transistors, the pixel element being operable to apply a potential to a gate terminal of each source follower input transistor corresponding to a cumulative amount of radiation incident upon the pixel element, the detector being operable to cause a bias current to flow through each source follower input transistor thereby to provide respective source follower arrangements. 
         [0110]    Embodiments of the present invention allow a plurality of output terminals to be provided for a single pixel element in a convenient manner. 
         [0111]    Advantageously the source of each source follower transistor is coupled to a bias current signal line whereby the bias current may flow through the source follower input transistors. 
         [0112]    Further advantageously the source of each source follower transistor is coupled to the bias current signal line by means of a select transistor. 
         [0113]    Advantageously the source of each source follower is coupled to a respective different bias current signal line by means of a respective different bias current signal line select transistor. 
         [0114]    That is, the sources of corresponding source follower input transistors of respective pixels are coupled to a common bias current signal line by means of respective bias current signal line select transistors. 
         [0115]    That is, first source follower input transistors of each pixel element of a column have sources that share a first common bias current signal line whilst second source follower input transistors of each pixel element of a column share a second common output signal line, and so forth where there are more than two source follower input transistors per pixel element. 
         [0116]    Advantageously the sources of corresponding source follower input transistors of respective pixels of a column are coupled to a common output signal line by means of respective output signal line select transistors. 
         [0117]    That is, first source follower input transistors of each pixel element of a column have sources that share a first common output signal line whilst second source follower input transistors of each pixel element of a column share a second common output signal line, and so forth where there are more than two source follower input transistors per pixel element. 
         [0118]    In another aspect of the invention for which protection is sought there is provided a method of detecting radiation comprising:
       providing a detector comprising an array of pixel elements, the array comprising a column of pixel elements, each pixel element comprising a source follower input transistor;   applying a potential to a gate terminal of the source follower input transistor of a pixel element, the value of the potential being responsive to a cumulative amount of charge carriers generated by the pixel element responsive to incident radiation;   connecting a source of each source follower input transistor by means of a respective bias line select transistor to a bias current signal line thereby to apply a bias current to the source follower input transistor thereby to form a source follower arrangement;   further connecting the source of the source follower input transistor by means of a respective output line select transistor to an output signal line separate from the bias signal line.       
 
         [0123]    In a further aspect of the invention for which protection is sought there is provided a method of detecting radiation comprising:
       providing a detector comprising an array of pixel elements, the array comprising a column of pixel elements, each pixel element comprising a plurality of source follower input transistor;   applying a potential to a gate terminal of each of the plurality of source follower input transistors of a pixel element, the value of the potential being responsive to a cumulative amount of charge carriers generated by the pixel element responsive to incident radiation; and   causing a bias current to flow through each of the plurality of source follower input transistors of the pixel element thereby to provide respective source follower arrangements.       
 
         [0127]    In a further aspect of the invention for which protection is sought there is provided a radiation detector comprising a pixel, the pixel comprising:
       a sensor element operable to pass charge therethrough between terminals thereof in response to incident radiation, the sensor element having a first charge storage reservoir associated therewith; and   a second charge storage reservoir, the pixel being operable to allow transfer of charge between a first one of the terminals of the sensor element and a terminal of the second charge storage reservoir,   the detector being operable wherein an electrical potential of the first terminal of the sensor element is responsive to an amount of charge stored in the first and second charge storage reservoirs, the detector being arranged to allow an amount of radiation incident upon the sensor element over a prescribed period of time to be determined.       
 
         [0131]    The first charge storage reservoir may be the capacitance of the sensor element which may be a diode. 
         [0132]    In further aspects of the invention there is provided: 
         [0000]    1. A detector for performing non destructive readout and arranged to read the same row of pixels at different exposure times.
 
2. A detector for which data at the output stage thereof is delivered separately for each of the frames achieved with the non destructive methods/architecture.
 
3. A method in which the in pixel source follower input transistor is biased in such a way that gradient problems are avoided when one or two or three side buttable detectors are implemented.
 
4. A method of layout of large pixel arrays to avoid electrostatic discharge (ESD) problems during handling of the detector comprising attaching one or more scintillators or any other materials on top of the pixel array/detector.
 
         [0133]    Embodiments of the present invention provide a method of making a  3  side buttable detector and providing the bias current in the in pixel source follower in a way that the resistance of the output lines (long metal tracks) will not provide any gradient effect and increase in fixed pattern noise. 
         [0134]    A non-destructive readout architecture which can perform multiple sampling for regions of interest while we are reading out the full frame independently. Data management (outputs) are control separately. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0135]    Embodiments of the invention will now be described with reference to the accompanying figures in which: 
           [0136]      FIG. 1  is a schematic illustration of a known active pixel of a CMOS radiation detector; 
           [0137]      FIG. 2  is a schematic illustration of an active pixel of a CMOS radiation detector according to an embodiment of the invention in which (a) a transistor diode is employed between a charge storage device and a photodiode and (b) a diode device is employed between the charge storage device and the photodiode; 
           [0138]      FIG. 3  is a plot of a potential as measured at node X of the circuit of  FIG. 1  and  FIG. 2  as a function of time under constant illumination conditions; 
           [0139]      FIG. 4  is a schematic illustration of an active pixel of a CMOS radiation detector according to a further embodiment of the invention; 
           [0140]      FIG. 5  is a schematic illustration of an active pixel of a CMOS radiation detector according to a still further embodiment of the invention; 
           [0141]      FIG. 6  is a plot of a potential as measured at node X of the circuit of  FIG. 5  under constant illumination conditions for different modes of operation of the circuit; 
           [0142]      FIG. 7  shows a circuit according to a further embodiment of the invention illustrating a non-destructive readout architecture and taking into consideration biasing of an in pixel source follower to avoid image gradient effects; 
           [0143]      FIG. 8  shows a circuit according to a further embodiment of the invention having two bias current lines and two output lines; 
           [0144]      FIG. 9  is a timing diagram for operation of the circuit of  FIG. 8  and illustrating non-destructive operation thereof; and 
           [0145]      FIG. 10  shows a pixel array in which region of interest ROI is highlighted; 
           [0146]      FIG. 11  shows a circuit in which a pixel element as two source follower input transistors connected to respective different output lines; and 
           [0147]      FIG. 12  shows a pixel element array according to an embodiment of the invention in which electrical connection to the array is made along a single side of the array. 
       
    
    
     DETAILED DESCRIPTION 
       [0148]      FIG. 2(   a ) shows an active pixel element  200  according to an embodiment of the invention. Like features of the pixel element  200  of  FIG. 2(   a ) to those of the prior art pixel element  100  of  FIG. 1  are provided with like reference signs prefixed numeral  2  instead of numeral  1 . 
         [0149]    The pixel element  200  has a photodiode  210  coupled to a source of a first reset transistor  221  and a gate of a source follower input transistor  231  at a floating node X in a similar manner to the pixel element  100  of  FIG. 1 . 
         [0150]    The drain of the first reset transistor  221  is connected to a first supply of potential V RST1 , whilst the gate is connected to a reset signal line RST. 
         [0151]    The source and drain of the source-follower input transistor  231  are respectively connected to the drain of a selection transistor  241  and a supply of reference voltage V DD . The gate of the selection transistor  241  is connected to a row select line ROW and the source of the selection transistor  241  is connected a column readout line COL. It is to be understood that the potential V X  at node X may be read out via the column readout line COL by turning ON the selection transistor  241  by means of the row select line ROW. 
         [0152]    The pixel element  200  is further provided with a capacitor  265  coupled between the floating node X and ground by means of a diode element  260 . In the embodiment of  FIG. 2(   a ) the diode element  260  is provided by a transistor  261  having its gate connected to node F between the capacitor  265  and the diode element  260 . It is to be understood that in some embodiments the diode element  260  may alternatively or in addition be provided by a diode instead of a transistor. An example of such a configuration is shown in  FIG. 2(   b ) where the transistor diode  261  of  FIG. 2(   a ) has been replaced by a p-n junction diode device  261 ′. 
         [0153]    In some other embodiments the gate of transistor  261  may be connected to an inverter or amplifier or comparator or any other pixel element internal or external potential to control the switching point and the behaviour of the transistor  261 . Devices other than a transistor  261  may also be used such as a diode as noted above or any other suitable device. 
         [0154]    Node F is coupled to a source of a second reset transistor  251  with its drain connected to a second supply of potential V RST2 . The gate of the second reset transistor  251  is connected to the reset signal line RST. In some embodiments separate reset signal lines are provided for applying respective potentials to the gates of the first and second reset transistors  221 ,  251  independently of one another. 
         [0155]    In operation the potential of the first supply V RST1  is set to a value greater than that of the second supply V RST2 . The reset signal line RST is set HIGH turning ON the first and second reset transistors  221 ,  251 . This causes the potential V X  of the floating node ‘X’ to be set to a value V RST1  as charge accumulates in the photodiode  210  and the potential V F  of node F to be set to a value V RST2  as charge accumulates in capacitor  265 . 
         [0156]    The reset signal line RST is then set LOW, turning OFF the first and second reset transistors  221 ,  251 . 
         [0157]    It is to be understood that the value of V RST1  is arranged to cause the photodiode  210  to be placed under a reverse bias condition. Thus, radiation incident upon the “photodiode”  210  will cause accumulated charge due to the junction capacitance of the photodiode  210  to be discharged to ground reducing the potential V X . 
         [0158]    As charge is conducted through the photodiode  210  V X  falls at a relatively high rate due to the relatively low capacitance of the photodiode  210 . 
         [0159]    It is to be understood that because V RST2  is less than V RST1 , V X  will eventually fall below V F  causing the diode element  260  to start conducting thereby connecting capacitor  265  in parallel with photodiode  210 . This causes the capacitor  265  to discharge through the photodiode  210 . Due to the presence of a relatively large amount of charge in capacitor  265 , the rate of change of V X  as a function of the amount of charge that has flowed through the diode  210  decreases substantially as V X  falls below V F . 
         [0160]    It is to be understood that the rate at which V F  decays will depend upon the capacitance of the capacitor  265 . Higher values of capacitance will typically result in a reduced rate of decay of V F  compared with lower values. 
         [0161]    It is to be understood that reset transistors  221  and  251  may be PMOS or NMOS transistors without affecting operation of the pixel element  200 . Use of NMOS devices has the advantage that KTC noise may be reduced at nodes X and F after resetting the nodes by means of the reset transistors  221 ,  251 . 
         [0162]      FIG. 3  is a plot of V X  as a function of the amount of charge conducted through the photodiode  110  of the pixel element  100  of  FIG. 1  (trace A) and the photodiode  210  of  FIG. 2  (trace B) under constant illumination (obtained by simulation). 
         [0163]    It can be seen that in the absence of the capacitor  265  V X  falls at a relatively rapid rate towards zero (trace A). 
         [0164]    In contrast, in the embodiment of  FIG. 2(   a ) the rate of change of V X  as a function of the amount of charge passing through the diode  210  is different when V X  is above V RST2  (portion B 1  of trace B) compared with that when V X  is below V RST2  (portion B 2  of trace B) ( FIG. 3) . It can be seen that pixel element  200  behaves in a very similar manner over portion B 1  of trace B to pixel element  100  (trace A). A slight difference in signal slope can be seen due to the small capacitance overhead of diode device  261 . This capacitance contribution could be reduced by resizing the diode capacitance to compensate if required, without loss of performance. 
         [0165]    It is to be understood that embodiments of the invention have the advantage that where a pixel element  200  is exposed to relatively small amounts of incident radiation the response (“gain”) of the pixel element  200  (change in V X  as a function of the amount of incident radiation) will be relatively large provided V X  remains above V F . 
         [0166]    However, for relatively large amounts of incident radiation, where V X  is expected to fall below V F , V X  falls at a reduced rate as a function of the amount of incident radiation when V X  falls below V F . This has the advantage of reducing a risk that V X  stops changing as a function of further incident radiation (i.e. saturation conditions are achieved) before V X  is read out at the column signal line COL. 
         [0167]    It is to be understood that in some embodiments the value of V RST2  (and therefore V F ) may be adjusted according to the anticipated illumination level of the pixel element  200 . In some embodiments the value of V RST2  may be a ‘factory preset’ value. In some embodiments a user may be able to set the value of V RST2 . 
         [0168]    It is to be understood that the value of V RST2  (and of the capacitance of capacitor  265 ) may be chosen so as to obtain a suitable trade off between dynamic range (obtained by employing higher values of capacitance and/or higher values of V RST2 , i.e. values of V RST2  closer to that of V RST1 ) and sensitivity to incident radiation levels (by employing lower levels of capacitance and/or lower levels of V RST2 ). 
         [0169]    It is to be understood that sensitivity to incident radiation levels is determined at least in part by the rate of change of V X  as a function of incident radiation. 
         [0170]    In the embodiment of  FIG. 2(   a ) the first and second reset transistors  221 ,  251  are both nMOS transistor devices. It is to be understood that pMOS transistor devices may be used instead.  FIG. 4  shows an active pixel element  300  according to a further embodiment of the invention substantially identical to the active pixel element  200  of  FIG. 2(   a ) except that the first and second reset transistors  321 ,  351  are pMOS devices. 
         [0171]    It is also to be understood that a mixture of pMOS and nMOS devices may be used in some embodiments by correcting the polarity of each RST line driving the gates according to the device type. 
         [0172]    This may be an advantage when soft reset is desired on the photodiode  210  but hard reset can be accepted on the capacitor  265 , to provide predictable pixel element behaviour and fast settling. Device  221  would then be an nMOS device while device  251  would be exchanged for a pMOS device. Alternatively, a hard reset may be desirable for the photodiode  210  (higher voltage) which can be better performed by means of a pMOS device as device  221 . A hard reset could be performed of the capacitor  265  using an nMOS device as device  251  since the voltage can be lower (V RST2 ) than the gate voltage of device  251 . 
         [0173]    Like features of the pixel element  300  of  FIG. 4  to those of the pixel element  200  of the embodiment of  FIG. 2(   a ) are provided with like reference signs prefixed numeral  3  instead of numeral  2 . 
         [0174]    It is to be understood that the pixel element  300  is arranged to operate in a corresponding manner to the pixel element  200  of  FIG. 2(   a ) and its operation will not be described further herein. 
         [0175]    It is to be understood that in some embodiments a cathode of the photodiode  210  may be connected to a supply having a suitable potential above ground, and an anode of the photodiode  210  may be connected to a diode element  260  of opposite polarity, specifically a PMOS device. Thus the value of V X  will increase as the cumulative amount of incident radiation increases and charge is conducted through the photodiode  210  from the supply. 
         [0176]    In some arrangements the pixel element  200 ,  300  is operable to apply reset pulses to the first and second reset transistors substantially independently of one another. This has the advantage that is may be ensured that the reset phase of the first reset transistor  251 ,  351  will not cause charge injection to the photodiode  210 ,  310 . 
         [0177]    It is to be understood that reset signals may be applied to the transistors in any suitable order. 
         [0178]      FIG. 5  shows a pixel element  400  according to a further embodiment of the invention. The pixel element has a photodiode  410  coupled between ground and a floating node X in a similar manner to the embodiments of  FIG. 2  and  FIG. 4 . The pixel element  400  has a reset signal line RST connected to the gate of a master reset transistor  471  via switch  463 . The source of the master reset transistor  471  is connected to the floating node X whilst the drain is connected to a floating node F. Drain terminals of first and second reset transistors  421 ,  451  (being pMOS transistors) are connected to floating node F whilst source terminals of the transistors  421 ,  451  are connected to first and second supply potentials V RST1 , V RST2  respectively. Gate terminals of the first and second reset transistors  421 ,  451  are connected to first and second reset signal lines RSTV 1 , RSTV 2  respectively. 
         [0179]    In the embodiment of  FIG. 5  the pixel element  400  is operable to connect the gate and drain terminals of the master reset transistor  471  to one another by means of an enable switch  462  which is operable to close when an enable signal line EN is HIGH. 
         [0180]    It is to be understood that when the enable signal line EN is HIGH and the enable switch  462  is closed, master reset transistor  471  functions as a diode element allowing current to flow from floating node F to floating node X when the potential V F  at node F is greater than the potential V X  at node X. 
         [0181]    It is to be understood that the pixel element  400  of the embodiment of  FIG. 5  is operable according to a number of different modes each having a different response characteristic in respect of V X  as a function of the amount of incident illumination. 
         [0182]    In a first mode of operation the potential at V X  is arranged to vary in a similar manner to that of the corresponding floating node X of the prior art pixel element  100 . Thus, with enable signal line EN LOW and enable switch  462  open while switch  463  is closed, the first reset transistor  421  is turned ON by means of first reset signal line RSTV 1 . 
         [0183]    Similarly, the master reset transistor  471  is turned ON by means of master reset signal line RST. V X  is thereby set to V RST1 . 
         [0184]    The first and second reset transistors  421 ,  471  are then turned OFF thereby isolating node X from V RST1  and node F. In some embodiments the first reset transistor  421  is maintained in the ON condition in this mode of operation of the pixel element  400 . 
         [0185]      FIG. 6  is a plot of the potential V X  as a function of the amount of charge transported through the photodiode  410 . It is to be understood that V X  will fall as a function of the amount of incident radiation according to trace A of  FIG. 6 , being similar to trace A of  FIG. 3 . 
         [0186]    Furthermore, it is to be understood that in a second mode of operation similar to the first mode the potential V X  at floating node X may be arranged to change according to trace C by applying a potential V RST2  to floating node X instead of V RST1  by controlling the second reset transistor  451  in a similar manner to (and instead of) the first reset transistor  421 . 
         [0187]    In a third mode of operation the pixel element  400  is controlled such that the potential V X  varies according to trace B of  FIG. 6  as a function of the amount of incident illumination. It is to be understood that trace B is similar to trace B of  FIG. 3 . Thus the third mode of operation corresponds to the manner of operation of a pixel element  200  according to the first embodiment. 
         [0188]    In the third mode of operation the first reset transistor  421  and the master reset transistor  471  are controlled by means of the master reset signal line RST and first reset signal line RSTV 1  so as to set V X  to a potential V RST1 . 
         [0189]    It is to be understood that if nMOS reset devices are employed V X  will be set to a potential close to V RST1  but relatively slowly due to soft reset. In contrast, pMOS devices give a hard reset and fast settling of V X  to a potential very close to V RST1 . 
         [0190]    It is to be understood that the term ‘soft reset’ refers to a situation where the reset transistor is operating in the (deep) subthreshold regime at the end of the reset period. This situation arises from the combination of the applied reset gate voltage and reset drain voltage. 
         [0191]    Often the reset gate ‘on’ voltage and the drain voltage are both Vdd and this leads to soft reset. Under soft reset, the photodiode and the reset drain do not reach thermal equilibrium. Carriers are emitted from the photodiode, over the effective barrier under the reset gate to the reset drain. 
         [0192]    In the pixel  400  of  FIG. 5  the reset will be soft due to nMOS transistor  471  in series with the first reset transistor  421  which is a pMOS device. 
         [0193]    It is to be understood that whether a reset is a hard or soft reset will of course depend on the value of the reset voltage. Thus the reset voltage could be lowered in order to achieve a hard reset using an nMOS transistor. Alternatively the gate voltage may be increased. 
         [0194]    The master reset signal line RST is then held LOW, turning OFF master reset transistor  471 . 
         [0195]    V F  is then controlled to assume a value V RST2  by means of the second reset transistor  451  which is then controlled to isolate the floating node F from the second supply potential VRST 2 . The enable signal line EN is then controlled so as to close enable switch  462  and open switch  463 . As described above, the master reset transistor  471  subsequently functions as a diode. 
         [0196]    As shown in trace B of  FIG. 6 , as the photodiode  410  conducts charge to ground under illumination V X  falls from a value V RST1  to a value V RST2  (corresponding to portion B 1  of trace B). 
         [0197]    As V X  falls below V RST2  the master reset transistor  471  allows charge to flow from floating node F to the photodiode  410  reducing the rate of change of V X  as a function of the amount of charge conducted through the photodiode  410 . This allows the collection of a larger amount of charge before saturation of the photodiode  410  is reached. 
         [0198]    In a fourth mode of operation V X  is initially set to a value V RST1  by means of first reset transistor  421  and master reset transistor  471 . The master reset transistor  471  is then controlled to behave as a diode by closing switch  462  and opening switch  463 , with V F  remaining at a potential V RST1 . 
         [0199]    It is to be understood that under these conditions as the photodiode  410  conducts current the rate of change of V X  as a function of the amount of charge will be reduced compared with the case where the master reset transistor  471  is OFF and not conducting charge, as shown by trace D of  FIG. 6 . This is because capacitor  465  begins to discharge through the master reset transistor  471  as V X  falls below V RST1 . 
         [0200]    In a fifth mode of operation similar to the fourth mode V X  is set initially to a value V RST2  instead of V RST1  by means of second reset transistor  451  and master reset transistor  471 . 
         [0201]    With the second reset transistor  451  also isolated from the second supply potential V RST2  and master reset transistor  4710 N, the change in V X  as a function of the amount of charge Q passed through the photodiode  410  is substantially as shown in trace E of  FIG. 6 . 
         [0202]    Other arrangements are also useful. 
         [0203]    It is to be understood that in some embodiments a one dimensional array of pixel elements  200 ,  300 ,  400  is provided. In some other embodiments a two dimensional array of pixel elements  200 ,  300 ,  400  is provided. The pixel elements may be formed on a semiconductor substrate such as a silicon substrate. 
         [0204]    In some embodiments a conducting layer such as a top metal conducting layer is formed over the pixel element array which is typically formed in a silicon wafer. The conducting layer is not connected to any circuit within the pixel element but is connected directly to one or more input/output pads of the array. Such pads are dedicated to discharging any external current that could be produced within the wafer surface due to contact, accumulation or field induction. 
         [0205]    The input/output pads include supply or ground connections which are typically low impedance nodes to the substrate potential. 
         [0206]    The presence of this conducting layer ensures that any electrostatic discharge (ESD) is routed to the interface pads (which are typically of low impedance as noted above) thereby protecting the pixel element circuits from damage. 
         [0207]    It is to be understood that this may be important in some applications. For example, in some applications scintillators may be bonded on top of the pixel element array. A danger exists that the scintillator may cause an electrostatic discharge, destroying circuits of the array. 
         [0208]    Embodiments of the present invention have considerably increased storage well capacities. Larger or smaller well capacities may also be obtained depending on the sizes of diode and capacitors used 
         [0209]    It is to be understood that the description and claims are not limited to a pixel element structure including only one charge storage device. In some embodiments of the invention a plurality of charge storage devices may be connected to node F. Furthermore any number of reset transistors and any number of different reset voltages may be employed. 
         [0210]    Furthermore, the order in which control signals are provided to the transistors and any other switching devices for proper operation of a circuit as described herein may be modified. Thus control signals may be provided in a different order to that described or two or more control signals that are described as provided separately may be provided substantially simultaneously. Furthermore where two signals are described as provided simultaneously, in some embodiments the signals may be provided sequentially, one following the other substantially immediately. 
         [0211]      FIG. 7  shows a circuit  501  according to a further embodiment of the invention. The circuit  501  has a pixel element  500  for which the potential at node X thereof is responsive to an amount of radiation to which the pixel element  500  has been exposed since the pixel element  500  was last reset by means of reset transistor  521  of the element  500 . 
         [0212]    The pixel element  500  is coupled to a pixel readout arrangement that has a current bias line BIAS 1  and a pixel readout output line OUTP 1 . The current bias line BIAS 1  is connected to a bias current source portion  550 . Each pixel element  500  has a source follower input transistor  531  that may be coupled to the bias current source portion  550  to form a source follower arrangement when a bias line select transistor  531 S 1  is enabled as described below. 
         [0213]    The bias current source portion  550  comprises a current mirror arrangement in the embodiment shown and is coupled to the current bias line BIAS 1 . The current bias line BIAS 1  may in turn be coupled to the source terminal S of the source follower input transistor  531  by means of a bias line select transistor  531 S 1  when a row select signal Row_Select_P 1  is enabled. The source terminal S is also connectable to the output line OUTP 1  by means of an output line row select transistor  532 S 1  when Row_Select_P 1  is enabled. Thus, when it is required to read out the potential at node X, Row_Select_P 1  is enabled, causing a bias current to flow through source follower input transistor  531  and a potential to be presented at an output terminal T 1  of output signal line OUTP 1  corresponding to the potential at node X. 
         [0214]    It is to be understood that providing a circuit having a separate bias line BIAS 1  and output line OUTP 1  is advantageous in some applications. This is because a potential corresponding to that of the source S may be read from an output terminal T 1  of the output signal line OUTP 1  without a requirement for current to flow through the output signal line OUTP 1 . This is because a bias current applied by bias portion  550  flows through bias line BIAS 1  rather than through the output signal line OUTP 1 . 
         [0215]    This feature has the advantage in turn that an amount of a drop in potential across the output signal line OUTP 1  between the output line row select transistor  532 S 1  associated with a given pixel element and the output terminal T 1  is substantially reduced (or substantially zero). This allows image gradient effects suffered in images captured by known pixel arrays (due to increased potential drops across output lines as a function of distance of a row of pixel elements from an output terminal) to be reduced (or substantially eliminated). 
         [0216]    It is to be understood that relatively long lengths of output line OUTP 1  may be required in certain applications (e.g. up to 15 cm for 8 inch wafers and longer distances for 12 inch wafers). Embodiments of the present invention may be particularly advantageous in such applications. 
         [0217]    Where relatively long lengths of output line are required, embodiments of the invention have the advantage that captured images do not suffer from image gradient effects. 
         [0218]    Embodiments of the invention find particularly advantageous use in applications where circuit architecture is constrained such that connections to a wafer or other substrate bearing the array of pixels is allowable from one side of the wafer only. 
         [0219]    For example, in some applications an array of pixel elements  500  such as a 2D array comprising a plurality of rows of pixel elements  500  may be formed on a silicon wafer which is subsequently bonded to a well package substrate or ‘well package’. Multiple wafers may be bonded to the same well package and arranged side by side in an abutting manner. In some arrangements a given wafer may have three wafers lying adjacent to it on each of three sides. The proximity of the other wafers may impose connectivity constraints such that electrical connection to the wafer may only be made along a single side of the wafer. Accordingly, readout signal lines may be required to cross substantially the entire width of a wafer in order to allow output of signals from pixels located away from the side of the wafer bearing the signal line outputs. It is to be understood that the bias portions  550 , and bond pads associated with output terminals T 1  and control electronics may be provided along a common edge in the embodiment of  FIG. 7 . 
         [0220]    Thus, correct biasing of the source follower input transistor  531  of each pixel element  500  can be achieved without a requirement to include biasing or other electronics within the pixel element  500  itself in order to overcome this problem. 
         [0221]      FIG. 8  shows an embodiment similar to that of the circuit of  FIG. 7  having two bias current lines BIAS 1 , BIAS 2 , each having an associated bias current portion  650 B 1 ,  650 B 2 . In some embodiments the bias current portions  650 B 1 ,  650 B 2  are formed in the same substrate of wafer as the pixel elements  600  although in some alternative embodiments the bias current portions  650 B 1 ,  650 B 2  are provided on a separate substrate such as a well package substrate bearing the substrates in which the pixel elements  600  are formed. 
         [0222]    The circuit  601  is operable to apply a potential to a selected one of the output lines OUTP 1 , OUTP 2  that is responsive to a potential at node X of the pixel element  600 . 
         [0223]    The architecture shown allows two different row select signals (Row_Select_P 1  and Row_Select_P 2 ) to be used to read out the potential at source S of the source follower transistor  631  (corresponding to the potential at nodes M). The row select signals are controlled independently of one another. 
         [0224]    As described above, current bias lines BIAS 1 , BIAS 2  are arranged to apply respective bias currents to the source follower input transistor  631  enabling readout of the potential at node M to output lines OUTP 1  or OUTP 2  via row select transistor  632 S 1  and  632 S 2  respectively. 
         [0225]    If Row_Select_P 1  is enabled, source follower input transistor  631  is connected to bias line BIAS 1  by means of bias line select transistor  631 S 1  whereby bias current portion  650 B 1  provides a bias current I 1  thereto. At the same time, output line row select transistor  632 S 1  connects output line OUTP 1  to node M whereby the potential at node M is applied to an output terminal T 1  of the output line OUTP 1 . The potential at the output terminal T 1  may be sampled by output electronics which may be external to the pixel array. 
         [0226]    Similarly, if Row_Select_P 2  is enabled, source follower input transistor  631  is connected to bias line BIAS 2  by means of bias line select transistor  631 S 2  whereby bias current portion  650 B 2  provides a bias current I 2  thereto. Output line row select transistor  632 S 2  connects output line OUTP 2  to node M whereby the potential at node M is applied to an output terminal T 2  of the output line OUTP 2  where it may also be sampled by output electronics. 
         [0227]    In some embodiments of the invention bias currents I 1  and I 2  are typically in the range of from around 5 microamps to around 20 microamps although any suitable current may be used. In some arrangements the bias currents I 1 , I 2  are substantially the same although in some embodiments the currents I 1 , I 2  may be different. 
         [0228]    As shown in  FIG. 8  bias line select transistor  631 S 2  is connected to current bias line BIAS 2  by means of a further bias line select transistor  633 S 2 . A signal Row_Select_P 1 _B being the inverse of signal Row_Select_P 1  is applied to the gate of the further bias line select transistor  633 S 2 . It is to be understood that the further bias line select transistor  633 S 2  is arranged to isolate bias line BIAS 2  from node M whenever node M is connected to bias line BIAS 1 . This feature prevents node M (and therefore the source S of source follower input transistor  631 ) from being connected to both bias lines BIAS 1 , BIAS 2  if row select signals Row_Select_P 1  and Row_Select_P 2  are both enabled simultaneously. If this situation were to occur the current drawn through the source follower input transistor  631  would be the sum of that through bias lines BIAS 1 , BIAS 2  and the potential at node M might provide a misleading indication of the potential at node X. It is to be understood that the presence of further bias line select transistor  633 S 2  may be particularly useful in rolling shutter image capture applications. 
         [0229]    However, it is to be understood that if row select signals Row_Select_P 1  and Row_Select_P 2  are both enabled simultaneously, the potential at node M may be read out simultaneously to output signal lines OUTP 1 , OUTP 2 . This feature allows simultaneous readout of the potential at node M to output terminals T 1 , T 2 . 
         [0230]    A readout arrangement according to an embodiment of the present invention as described above has the advantage that a potential corresponding to that at node X may be effectively read out at respective output terminals T 1 , T 2  of output lines OUTP 1  and/or OUTP 2  without a requirement for current to flow through either of the output lines OUTP 1 , OUTP 2 . This has the advantage that readout of the potential at node X may be performed in a reliable and accurate manner substantially independently of the length and therefore resistance of the output lines OUTP 1 , OUTP 2 . 
         [0231]    In contrast, in the circuits of  FIGS. 1 ,  2 ,  4  and  5  a current flow through the column output lines COL is required in order to allow readout of the potential at node X. 
         [0232]    It is to be understood that by providing two output lines OUTP 1 , OUTP 2  that are addressable substantially independently of one another, the potential at node X may be read out to different image capture circuits. In some embodiments the potential at node X may be read out at different rates by different circuits. 
         [0233]    For example, a first circuit coupled to (say) output line OUTP 1  may read out the potential at node M immediately before a reset signal is applied to reset transistor  621 , allowing the potential at node M to be monitored following substantially maximum exposure of the pixel element  600  to radiation before the pixel element  600  is reset. Thus signal line Row_Select_P 1  may be set high thereby to read out the potential at node M to output line OUTP 1  once for every time a reset signal is applied to reset transistor  621  (and typically substantially immediately prior to the application of a reset signal to reset transistor  621 ). 
         [0234]    A second circuit coupled to output line OUTP 2  may read out the potential at node M more than once for every time a reset signal is applied to reset transistor  621 . Thus signal line Row_Select_P 2  may be set high thereby to read out the potential at node M to output line OUTP 2  a plurality of times between successive applications of a reset signal to reset transistor  621 . 
         [0235]    This feature has the advantage that if a particular pixel element  600  or group of elements  600  becomes saturated between the application of one reset signal to reset transistor  621  and the next, it may be possible still to obtain an unsaturated signal. This is achieved by reading out the potential at node M via output signal line OUTP 2  before the potential at node M is next read out to output line OUTP 1 . In some embodiments the second circuit may read out the potential at node M ten times for every reset signal applied to reset transistor  621 . Other numbers and ratios of read out signals applied by the circuits between reset signals are also useful. 
         [0236]    In some arrangements the first circuit may read out the potential at node M of each pixel element  600  (i.e. read out one frame of the array of elements  600 ) once every second whilst the second circuit may read out the potential ten times per second, i.e. read out or output 10 frames per second. 
         [0237]    The circuits coupled to OUTP 1  and OUTP 2  may themselves be operable to select pixel elements  600  for which the potential at node M thereof is to be output. The circuits may be arranged to buffer data acquired thereby and to reset their buffers according to a control methodology. 
         [0238]      FIG. 9  is a plot of the potential V X  at node X as a function of time for one particular pixel element  600  of the embodiment of  FIG. 8 . It can be seen that at time t 1  a reset signal is applied to reset transistor  621 , and V X  is reset to reset potential V RST . 
         [0239]    At time t 2  signal line Row_Select_P 2  is set HIGH momentarily, allowing the potential at node M (corresponding to that at node X) to be read out to line OUTP 2 . Once the potential has been read the signal line Row_Select_P 2  returns to logical LOW. 
         [0240]    At time t 3  signal line Row_Select_P 2  is again momentarily set HIGH before being set back to LOW, allowing the potential at node M to be again read out to line OUTP 2 . This process is repeated at times t 4 , . . . t n , . . . t T-1 . At time t T  signal line Row_Select_P 1  is momentarily set HIGH before being set back to LOW. This allows the potential at node M to be read out to output signal line OUTP 1 . 
         [0241]    At time t R  a reset potential is applied to the input of reset transistor  621  causing the potential at node M to be reset to V RST . The process of reading out the potential at node M to output signal line OUTP 2  at successive time intervals, followed finally by reading out the potential at node M to output signal line OUTP 1 , then repeats. 
         [0242]    It is to be understood that the reset potential may be applied to the input of reset transistor  621  after the process of outputting the potential at node M to output signal line OUTP 2 . However in the embodiment shown this would reset all of the pixel elements  600  of a given row. Of course, in some embodiments resetting of individual pixel elements  600  or groups of pixel elements  600  may be possible. 
         [0243]    It is to be understood that embodiments of the invention have the advantage that non-destructive readout of a potential corresponding to that of node X may be performed allowing output of a signal corresponding to the potential at node X to a plurality of different output signal lines OUTP 1 , OUTP 2 . In some embodiments the potential is not read out in a non-destructive manner, since the act of reading out the potential at node X results in a change in the potential at node X. 
         [0244]      FIG. 10  shows a plan view of a pixel array  600 A consisting of an array of 1000×1000 pixel elements  600 . In the arrangement shown a user has identified a region of interest ROI comprising 100×100 pixels. 
         [0245]    A controller of the array (not shown) controls the array such that the potential at node X of each of the pixel elements  600  comprised by the ROI is read out at a rate that exceeds that at which the potential at node X of the remaining (non-ROI) pixel elements  600  is read out. 
         [0246]    Thus a first circuit may read out all of the pixels of the array at one frame rate (to output lines OUTP 1 ) whilst a second circuit may read out the pixels of the ROI at another frame rate, to output lines OUTP 2 . The frame rate of the second circuit may be greater than that of the first circuit. Alternatively the frame rate of the first circuit may be greater than that of the second circuit 
         [0247]    In some embodiments the potential at node X of each of the pixel elements comprised by the ROI may be read out at a rate of 700 frames per second or any other suitable number. 
         [0248]    The rate at which frames are read out from the non-ROI pixel elements  500  may be any suitable rate, optionally one frame per reset signal applied to reset transistors  621  of each element, just before the reset signal is applied. Other arrangements are also useful. 
         [0249]    It is to be understood that one of the first or second circuits may be operable to reset the pixel elements  600  in each row by means of a reset signal applied to reset transistors  621 . Advantageously the circuit operating at the lower frame rate is configured to accomplish this task, for example immediately after outputting a frame. 
         [0250]    Embodiments of the invention have the advantage that a single pixel array may be controlled to act in a manner effectively simulating two pixel arrays because a potential corresponding to that at node X may be read out to two different sets of output signal lines OUTP 1 , OUTP 2 . A multiplexing circuit arrangement that might otherwise be required if only a single set of output lines OUTP 1  were provided is therefore not required. 
         [0251]    In some systems according to the present invention, respective first and second circuits are arranged to read out the potential at node X of respective different pixel elements  600  of the embodiment of  FIG. 8  to respective different output lines OUTP 1 , OUTP 2 . Thus, the circuits may be arranged to output a signal corresponding to the potential at node X of one set of pixel elements  600  to one set out output lines OUTP 1  and a signal corresponding to the potential at node X of the remaining pixel elements  600  to another set out output lines OUTP 2 . Thus the first and second circuits read out signals corresponding to Vx in different pixel elements  600 . 
         [0252]    It is to be understood that in some arrangements more than two sets of output lines OUTP 1 , OUTP 2  are also useful, such as three, four, five or more. 
         [0253]    A system incorporating a pixel array according to an embodiment of the present invention may therefore effectively be used to provide two imaging cameras having respective image capture and image data management electronics but a common pixel element array. Node potentials of pixel elements of the array may be read out separately to the electronics associated with the respective cameras as required. 
         [0254]    In some embodiments, correlated double sampling (CDS) is employed to improve signal to noise ratio of signals output by the circuit  601 . 
         [0255]    It is to be understood that the reset transistor described with respect to embodiments of the present invention such as transistor  521 ,  621  can be either a PMOS or an NMOS transistor device. 
         [0256]    A further advantage of the architecture shown in  FIG. 7  and  FIG. 8  is that respective output and biasing lines are separated. As indicated above, this gives the advantage that the bias current portions  550 ,  650  can be placed either at the ‘top’ or at the ‘bottom’ of the pixel array. This allows a true one or two or three side buttable detector to be provided without the introduction of an artificial gradient into a sampled (or captured) image as described above. 
         [0257]    In conventional 3T pixel architecture it is considered good practice to place the current bias portion providing bias current on an opposite side of the pixel array from output terminals of the array at which the potential of the source of the source follower input transistor is being read out. In this way it is ensured that the bias current is flowing in the opposite direction to that from which sampling is taking place so that line resistance does not affect the sampled output value. However, if wafers on which pixels are formed are butted one against another on a substrate, it is difficult to connect the bias current portions (or output line terminals) to the substrate. Accordingly, the present applicant has recognised that if separate output and bias current lines are provided, both the current bias portions and output terminals may be provided along a common side of the array. 
         [0258]    It is to be understood that some embodiments of the present invention have the advantage that gradients in output potential due to output line resistance, resulting in potential variations from the top to the bottom of the pixel array may be reduced or substantially eliminated whilst at the same time allowing power and control signals to be applied to the pixel element array from only one side of the array. 
         [0259]      FIG. 11  shows a circuit according to a further embodiment of the invention. Corresponding features of the embodiment of  FIG. 11  to those of the embodiment of  FIG. 7  are shown with like reference signs prefixed numeral  7  instead of numeral  5 . 
         [0260]    In the embodiment of  FIG. 11  a circuit  701  is provided in which a pixel element  700  has two source follower input transistors  731 A,  731 B each connected to a node X of the pixel element  700 . Node X is a potential at a terminal of photodetector  710 , the potential corresponding to an amount of charge carriers generated in photodetector  710  by incident radiation. 
         [0261]    The circuit  700  has two output lines OUTP 1 , OUTP 2  having bias current portions  750 A,  750 B connected thereto. Each bias current portion  750 A,  750 B comprises a current mirror circuit arranged to form a source follower circuit arrangement with the source follower input transistors  731 A,  731 B. Respective row select transistors  731 AS,  731 BS are operable to apply the potential at the source S of each source follower input transistor  731 A,  731 B to a respective output line OUTP 1 , OUTP 2  when required. 
         [0262]    The circuit  701  has the feature that two output lines OUTP 1 , OUTP 2  may be provided simultaneously with an output potential corresponding to that of node X of the same pixel element  700 . Thus in some embodiments two entirely separate and independent circuits external to the circuit  701  may be provided with signals corresponding to the potential at node X of the same pixel element  700 . 
         [0263]    Embodiments such as that of  FIG. 11  having two or more source follower input transistors  731 A,  731 B connected to respective output lines OUTP 1 , OUTP 2  may be implemented with a corresponding two or more respective bias lines BIAS 1 , BIAS 2  as described above with respect to the embodiment of  FIG. 8 . It is to be understood that each source follower transistor may be provided with a respective one or more bias lines BIAS 1  in addition to output lines OUTP 1 , OUTP 2 . Such embodiments have advantages similar to those of the embodiment of  FIG. 7  in that current bias portions  750 A,  750 B may be provided on the same side of a pixel element array as output terminals T without the introduction of the image gradient effects described above. 
         [0264]      FIG. 12  shows a pixel element array  500 A comprising pixel elements  500  according to the embodiment of  FIG. 7  although the array may also comprise pixel elements according to other embodiments of the invention. The array  500 A is formed on a substrate  500 AS and comprises three columns C 1 , C 2 , C 3  of pixel elements  500 , each column having three pixel elements  500 . It can be seen that the pixel element array may also be considered to be formed from three rows R 1 , R 2 , R 3  each of three pixel elements  500 . 
         [0265]    Electrical connection to the array  500 A is made along a single side of the array  51  as shown. Along side  51  each of the bias current signal lines BIAS 1  and output signal lines OUTP 1  are provided with terminals allowing electrical connection thereto. 
         [0266]    Other terminals are also provided to allow power to be supplied to the pixel elements. In addition, terminals for allowing connection of other control signal lines to external control circuits are provided such as select signal lines, reset signal lines and the like. 
         [0267]    The arrangement of  FIG. 12  has the advantage that the substrate  500 AS may be surrounded on each of three sides S 2 , S 3 , S 4  by other substrates and yet still allow electrical connection to be made thereto along side S 1  without the problem of the introduction of image gradient effects into captured image data as described above. 
         [0268]    It is to be understood that where embodiments of the present invention have been described with respect to image capture, the embodiments are equally suitable for measuring radiation intensity without forming images and such descriptions are merely by way of example. They are not to be construed as limiting the scope or application of the claimed invention. 
         [0269]    Throughout the description and claims of this specification, the words “comprise” and “contain” and variations of the words, for example “comprising” and “comprises”, means “including but not limited to”, and is not intended to (and does not) exclude other moieties, additives, components, integers or steps. 
         [0270]    Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise. 
         [0271]    Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith.