Abstract:
A Global Positioning System (GPS) commercial receiver includes programmable logic that utilizes P-code modulated L1 and L2 GPS signals to derive estimates of in-phase and quadrature-phase components of both L1 and L2 signals, a programmable processor that calculates pseudoranges and pseudo-Doppler phases, and derives navigation solutions. A resulting complex accumulated L2 signal comprises near-ML estimates of desired L2 amplitude and pseudo- Doppler phase.

Description:
BACKGROUND 
       [0001]    This disclosure relates generally to global positioning system (GPS) satellite receivers, and more particularly, to an overall architecture thereof and to specific digital signal processing sections within such receivers. 
         [0002]    GPS satellites transmit spread spectrum signals on L1 and L2 frequency bands at 154fo and 120fo respectively, where fo=10.23 MHz. Each of L1 signals is modulated by C/A code and P-code, which are unique for each satellite. Both codes are publicly known. Each of L2 signals is modulated by P-code only. Although both the C/A code and P-code sequences are known, each GPS satellite is provided with the capability of modulating its P-code with a secret signal generally referred to as W-code. This “anti-spoofing” (A/S) allows the GPS system to be used for military applications by preventing jamming signals based on known P-codes from being interpreted as actual GPS signals. The combination of the P-code and the W-code is typically referred to as the Y-code. 
         [0003]    There are important advantages to obtaining access to both L1 and L2 signals. First, ionospheric refraction can be measured and removed by co-processing the L1 and L2 pseudorange, which allows achieving higher accuracy in stand-alone applications. Second, for survey applications, there is a significant advantage with the use of carrier-phase measurements of both L1 and L2 signals in phase-differential systems. L2 carrier-phase measurements supplemental to those of L1 redouble the total number of observables, and make it possible to arrange so-called “wide lane” observables that significantly improve performance of phase ambiguity resolution. 
         [0004]    However, existing systems and methods for handling L1 and L2 signal have disadvantages. In particular, for example, existing techniques of recovering L2 carrier phase from the Y-code are becoming obsolete as GPS systems evolve. For example, known receiver structures are unable to exploit the possibilities of the new, more robust L2c code which will become available to civilian users. Known receiver structures are typically difficult or impossible to adapt to new applications because they are implemented by application specific integrated circuits (ASICs). Further, such ASICs can be costly. 
         [0005]    Additionally, known receiver structures typically consume power and other resources at a high level in order to process L1 and L2 signals in an acceptable manner. Accordingly, there is a need for a processing method and system that retains high quality while reducing hardware complexity. 
       SUMMARY 
       [0006]    Embodiments of the present invention address the above-noted concerns. The embodiments may comprise a receiver for processing L1 and L2 signals, where the receiver is readily configurable to process other kinds of signals, such as the more robust L2c signal. To this end, the receiver may comprise programmable logic able to be configured and/or reconfigured by, for example, a configuration file in the form of electronic data, such as software or firmware. The programmable logic may receive the configuration file from a memory under the control a central processing unit (CPU), for example during power-up of the receiver. Because the receiver is easily reconfigurable via the electronic data of the configuration file, the inflexibility and cost of ASICs is avoided. 
         [0007]    Further, the embodiments may implement an efficient method that retains high quality while allowing hardware complexity to be significantly reduced. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  shows a system of a dual frequency GPS receiver according to embodiments of the present invention; 
           [0009]      FIG. 2  shows a piece-wise approximation of the Ln cosh( ) function according to embodiments of the present invention; 
           [0010]      FIG. 3  shows an embodiment of a circuit configuration of the RF front-end block of the system of  FIG. 1 ; 
           [0011]      FIG. 4  is a block diagram of an embodiment of schematics implemented in the system of  FIG. 1 ; 
           [0012]      FIG. 5  shows details of an embodiment of phase shift circuits of  FIG. 4 ; 
           [0013]      FIG. 6  shows details of an embodiment of a weighted sum circuit of  FIG. 4 ; and 
           [0014]      FIG. 7  illustrates process steps controlled by a central processing unit (CPU) according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0015]    As discussed above, because GPS systems are evolving, new signals are emerging at the L2 frequency range, and new signals are planned for L1. Consumers would benefit from a versatile receiver capable of processing signals of various structures. 
         [0016]    Accordingly, embodiments of the present invention include a GPS receiver that may utilize programmable logic, such as a Field Programmable Gate Array (FPGA), to perform functions such as multi-channel digital processing of navigation signals, in contrast to the past approach of developing an application-specific integrated circuit (ASIC) for such functions. The programmable logic may be connected to a programmable central processing unit (CPU) by means of conventional buses and control signals, and be able to receive an operational configuration file from the CPU at each power-up initiation and be able to be reconfigured at any time. The configuration file may be stored in a programmable read-only memory (PROM). The CPU may be connected to the PROM by conventional buses and control signals. The CPU may read the configuration file from the PROM and write it into the programmable logic at power-up. 
         [0017]    The receiver may further comprise a radio frequency front-end block for amplifying, filtering, down-converting and digitizing received L1/L2 navigation signals, a PROM, and CPU performing further data processing, navigation solution, and communicating to an external host system. 
         [0018]    The advantages of such a receiver architecture include an ability to be adapted to existing Y-coded L2 signal as well as to the new L2c signal and other future L1 or L2 signals without any hardware modification, which is difficult or impossible with traditional ASIC-based receivers. According to embodiments of the present invention, a configuration file may simply be created for a new signal. The configuration file may be sent to an end user. The user can easily communicate the configuration file to the receiver&#39;s CPU which, in turn, may update PROM content correspondingly. 
         [0019]    Another advantage a receiver architecture according to embodiments of the present invention is that there could be several configuration files in the receiver&#39;s PROM that are interchangeably and dynamically reloaded into the programmable logic (e.g., FPGA) in order to adapt to different situations during operation of the receiver. 
         [0020]    Yet another advantage of such a receiver architecture is that it eliminates high cost of ASIC development. 
         [0021]    A GPS receiver according to embodiments of the invention may be used, for example, in survey and high-precision navigation (kinematic) applications in which access to both L1 and L2 carrier signals is needed. Measuring the pseudorange and pseudo-Doppler phase of both signals makes it possible to compensate for ionospheric refraction of the GPS signals, and ensures fast phase ambiguity resolution in survey (kinematic) applications. 
         [0022]    As noted previously, embodiments of the present invention may implement an efficient method that retains high quality while allowing hardware complexity to be significantly reduced. The method may perform operations associated with, for example, an approximation of a likelihood function as described below. 
         [0023]    Complex input L1 and L2 signals can be represented in continuous time as: 
         [0000]        S   1 ( t )= a   1   P ( t ) W ( t ) e   j(ω     1     t+φ     1     ) +ξ 1 ( t )   complex L1 signal
 
         [0000]        S   2 ( t )= a   2   P ( t ) W ( t ) e   j(ω     2     t+φ     2     ) +ξ 2 ( t )   complex L2 signal (1)
 
         [0024]    where:
       a 1 , a 2 , are real amplitudes of L1 and L2 signal correspondingly,   P(t) is a known P-code,   W(t) is an unknown W-code,   ω 1 , ω 2  are pseudo-Doppler frequencies at L1 and L2 correspondingly, ω 2 =60/77 ω 1 ,   φ 1 , φ 2  are initial phases at L1 and L2 changing slowly due to ionosphere effects, and   ξ 1 , ξ 2  are zero mean complex Gaussian noises.       
 
         [0031]    The input signals are multiplied by corresponding replicas, and integrated over the W-bit interval. The complex replica signals are: 
         [0000]        r   1 ( t )= P ( t ) e   −j(ω     1     t+φ     2     )    complex L1 replica
 
         [0000]        r   2 ( t )= P ( t ) e   −j(ω     2     t+ψ)    complex L2 replica (2)
 
         [0032]    In (2) it is assumed that tracking on the L1 C/A code and phase allows for aligning the replica P-code with that of the input signal, to set the replica&#39;s frequencies equal to the signal frequencies, and to set the replica&#39;s L1 phase equal to the signal phase φ 1 . The latter condition cannot be implemented for L2, which is why L2 replica phase ψ differs from φ 2 . The complex W-bit integrator outputs can be expressed from (1) and (2) as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       X 
                       
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                    
                   
                     
 
                   
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                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0033]    where:
       ζ 1 , ζ 2  are zero mean complex Gaussian variables,   θ=φ 2 −ψ is an unknown phase difference to be estimated,   T w  is a duration of a W-bit interval, and   w i =±1 is an unknown W-bit value over the integration interval.       
 
         [0038]    Denoting: 
         [0000]      x i =Re X 1i    
         [0000]      y i =Re X 2i    
         [0000]      z i =Im X 2i,    (4)
 
         [0039]    the joint probability density function on condition of θ, a 2 , and w i  is: 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                       indicates text missing or illegible when filed 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0040]    Assuming that the W-code is statistically bit-by-bit independent, and the probabilities of +1 and −1 are 0.5 each yields the following unconditioned (by w i ) probability density function: 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                       ( 
                       
                         
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                       indicates text missing or illegible when filed 
                     
                   
                 
               
               
                 
                   ( 
                   6 
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         [0041]    From (6), a logarithm of a likelihood function for the i-th W-bit interval follows as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           
                             
                               L 
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                       indicates text missing or illegible when filed 
                     
                   
                 
               
               
                 
                   ( 
                   7 
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         [0000]    and for a whole estimation period including m W-bit intervals: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           
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                       indicates text missing or illegible when filed 
                     
                   
                 
               
               
                 
                   ( 
                   8 
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         [0042]    In an operation absent from known techniques, the method of approximation uses a piecewise-linear approximation of the Ln cosh( ) function. Turning to  FIG. 2 , there is shown Ln cosh( ) function and its approximation, represented as: 
         [0000]    
       
         
           
             
               
                 
                   
                     ln 
                      
                     
                         
                     
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                         u 
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                   ( 
                   9 
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         [0000]    It follows from (8), (9): 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                   ( 
                   10 
                   ) 
                 
               
             
             
               
                 
                   
                       
                   
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                     where 
                      
                     
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                                     i 
                                   
                                 
                                 + 
                                 
                                   
                                     a 
                                     2 
                                   
                                    
                                   
                                     y 
                                     i 
                                   
                                    
                                   cos 
                                    
                                   
                                       
                                   
                                    
                                   θ 
                                 
                                 + 
                                 
                                   
                                     a 
                                     2 
                                   
                                    
                                   
                                     z 
                                     i 
                                   
                                    
                                   sin 
                                    
                                   
                                       
                                   
                                    
                                   θ 
                                 
                               
                               
                                 σ 
                                 2 
                               
                             
                           
                           &gt; 
                           0.69 
                         
                       
                     
                     
                       
                         
                           
                             
                               
                                 x 
                                 _ 
                               
                               i 
                             
                             = 
                             0 
                           
                           , 
                           
                             
                               
                                 y 
                                 _ 
                               
                               i 
                             
                             = 
                             0 
                           
                           , 
                           
                             
                               
                                 z 
                                 _ 
                               
                               i 
                             
                             = 
                             0 
                           
                           , 
                         
                       
                       
                         
                           
                             if 
                              
                             
                                 
                             
                              
                             
                                
                               
                                 
                                   
                                     
                                       a 
                                       1 
                                     
                                      
                                     
                                       x 
                                       i 
                                     
                                   
                                   + 
                                   
                                     
                                       a 
                                       2 
                                     
                                      
                                     
                                       y 
                                       i 
                                     
                                      
                                     cos 
                                      
                                     
                                         
                                     
                                      
                                     θ 
                                   
                                   + 
                                   
                                     
                                       a 
                                       2 
                                     
                                      
                                     
                                       z 
                                       i 
                                     
                                      
                                     sin 
                                      
                                     
                                         
                                     
                                      
                                     θ 
                                   
                                 
                                 
                                   σ 
                                   2 
                                 
                               
                                
                             
                           
                           ≤ 
                           0.69 
                         
                       
                     
                     
                       
                         
                           
                             
                               
                                 x 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               - 
                               
                                 x 
                                 i 
                               
                             
                           
                           , 
                           
                             
                               
                                 y 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               - 
                               
                                 y 
                                 i 
                               
                             
                           
                           , 
                           
                             
                               
                                 z 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               - 
                               
                                 z 
                                 i 
                               
                             
                           
                           , 
                         
                       
                       
                         
                           
                             if 
                              
                             
                                 
                             
                              
                             
                               
                                 
                                   
                                     a 
                                     1 
                                   
                                    
                                   
                                     x 
                                     i 
                                   
                                 
                                 + 
                                 
                                   
                                     a 
                                     2 
                                   
                                    
                                   
                                     y 
                                     i 
                                   
                                    
                                   cos 
                                    
                                   
                                       
                                   
                                    
                                   θ 
                                 
                                 + 
                                 
                                   
                                     a 
                                     2 
                                   
                                    
                                   
                                     z 
                                     i 
                                   
                                    
                                   sin 
                                    
                                   
                                       
                                   
                                    
                                   θ 
                                 
                               
                               
                                 σ 
                                 2 
                               
                             
                           
                           &lt; 
                           0.69 
                         
                       
                     
                   
                   , 
                   
                     
 
                   
                    
                   
                     
                       ? 
                     
                      
                     
                       indicates text missing or illegible when filed 
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0000]    and m 1  is number of items with non-zero  x   i . 
         [0043]    The maximum likelihood estimate of θ follows from (10): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       θ 
                       ML 
                     
                     = 
                     
                       arctan 
                       ( 
                       
                         
                           
                             ∑ 
                             
                               i 
                               = 
                               1 
                             
                             m 
                           
                            
                           
                             
                               z 
                               _ 
                             
                             i 
                           
                         
                         
                           
                             ∑ 
                             
                               i 
                               = 
                               1 
                             
                             m 
                           
                            
                           
                             
                               y 
                               _ 
                             
                             i 
                           
                         
                       
                       ) 
                     
                   
                    
                   
                     
 
                   
                    
                   
                     
                       a 
                       
                         2 
                          
                         
                             
                         
                          
                         ML 
                       
                     
                     = 
                     
                       
                         1 
                         m 
                       
                        
                       
                         
                           
                             
                               ( 
                               
                                 
                                   ∑ 
                                   
                                     i 
                                     = 
                                     1 
                                   
                                   m 
                                 
                                  
                                 
                                   
                                     y 
                                     _ 
                                   
                                   i 
                                 
                               
                               ) 
                             
                             2 
                           
                           + 
                           
                             
                               ( 
                               
                                 
                                   ∑ 
                                   
                                     i 
                                     = 
                                     1 
                                   
                                   m 
                                 
                                  
                                 
                                   
                                     z 
                                     _ 
                                   
                                   i 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0044]    In a steady-state tracking mode the value of θ is close to zero, so (11) becomes: 
         [0000]          x     i   =x   i   ,  y     i   =y   i   ,  z     i   =z   i , if  a   1   x   i   +a   2   y   i &gt;0.69σ 2  
 
         [0000]          x     i =0,    y     i =0,    z     i =0, if | a   1   x   i   +a   2   y   i |≦0.69σ 2  
 
         [0000]          x     i   =−x   i   ,  y     i   =−y   i   ,  z     i   =−z   i , if  a   1   x   i   +a   2   y   i &lt;0.69σ 2    (13)
 
         [0045]    On the other hand, in the initialization mode the value of θ is fully unknown, so better results are achieved if no L2 data included into eq. (11), i.e.: 
         [0000]          x     i   =x   i   ,  y     i   =y   i   ,  z     i   =z   i , if  a   1   x   i &gt;0.69σ 2  
 
         [0000]          x     i =0,    y     i =0,    z     i =0, if | a   1   x   i |≦0.69σ 2  
 
         [0000]          x     i   =−x   i   ,  y     i   =−y   i   ,  z     i   =−z   i , if  a   1   x   i &lt;0.69σ 2    (14)
 
         [0046]    One advantage of expression (12), which may be characterized as an “estimator,” is that it is a direct estimator, and does not require a gradient or closed loop system for implementation. 
         [0047]    Another advantage of the estimator (12) is that it does not include any multiplication operation during accumulation of sums in the numerator and denominator of (12). 
         [0048]    Referring to  FIG. 1 , an embodiment of a system which may be included in a receiver according to embodiments of the invention is illustrated. In the system, a signal received from an antenna is initially applied via a transmission line, such as an RF cable  1 , to a radio-frequency (RF) front-end block  10 . The front-end block  10  may amplify, down-convert, filter and digitize L1 and L2 signal in the received signal. The RF front-end block  10  may, for example, be arranged so that its output signals on the lines  18  and  20  are of video frequency (VF) in order to alleviate further digital processing. The actual frequency of the signals at lines  18  and  20  may be a pseudo-Doppler frequency. The RF front-end block output signals S 1  and S 2  may be complex to prevent losing important data, so each of lines  18  and  20  may comprise two sub-lines for real and imaginary signal components. 
         [0049]    Digital signal processing may be implemented in programmable logic, such as a field-programmable gate array (FPGA)  40 , which receives complex L1 and L2 signals by the lines  18  and  20 , performs multi-channel correlation processing, and provides correlation data to a central processing unit (CPU)  50 . The CPU  50  may read the correlation data with the use of a data bus  45  before setting the address bus  46  to an address of a channel and an item of interest, and setting a read control signal at line  48  to an enable state. 
         [0050]    The CPU  50  may perform post-correlation processing of data read from FPGA  40 . The processing may include phase locked loop (PLL) and delay locked loop (DLL) operations, as well as generating control data to correlation channels of the FPGA such as code delay, pseudo-Doppler phase and frequency, as will be explained below in more detail. To send control data, the CPU  50  may put the data into the data bus  45 , setting the address bus  46  to an address of a channel and item of interest, and setting the write control signal at the line  47  to enable state. CPU  50  may communicate with an external host system via communication line  61 , sending measured position, velocity and timing data to the host, and receiving various control data from it for adaptation of the receiver&#39;s parameters to a user&#39;s requests. 
         [0051]    A programmable read-only memory (PROM)  60  may contain executable code for CPU  50 . At receiver power up, the CPU  50  may fetch bootstrap instructions from the PROM  60 , and execute them so as to load the executable code into the CPU&#39;s internal random access memory (RAM) by means of the data bus  45  and address bus  46 . After loading, the CPU  60  may start to execute instructions from its internal RAM. 
         [0052]    Operations following receiver power up may include loading a configuration file to the FPGA  40 . The FPGA configuration file may define functionality of each of the FPGA&#39;s configurable logic blocks (CLBs), and interconnections between them, in that way obtaining desired processing functionality of the whole of the FPGA schematics. The FPGA&#39;s configuration file may be stored in the PROM  60  along with CPU&#39;s executable code. The CPU  50  may read the FPGA&#39;s configuration file from the PROM  60  with the use of the data bus  45  and address bus  46 , and write it to the FPGA  40  by means of the same buses  45  and  46 . Supplementary signals may be applied to the FPGA  40  by the line  49  to control the process of loading of the configuration file. 
         [0053]    The PROM  60  may be capable of storing several configuration files adapted to different operational conditions of the receiver. CPU  50  may choose one of them for loading at receiver power up in accordance to a user&#39;s preference, which may also be stored in the PROM  60 . Additionally, the user may issue a command via communication line  61  to switch to a different FPGA configuration during normal operation of the receiver. In such an event, the CPU  50  may read a desired configuration file from the PROM  60 , and load it to FPGA  40  the same way as was described above for power up mode. In this manner, a high degree and quickness of adaptability is achieved. 
         [0054]    When the new L2c signal becomes available and a schematic design is ready for its processing, the corresponding configuration file may be loaded from the host system via communication line  61  to the CPU  50 , which will write it into the PROM  60 . Following this, the CPU may load a new configuration file at each receiver power up the same way as described above. In embodiments, a part of the correlation channels in the programmable logic (e.g., FPGA) may be configured to process the L2c signals, while another part may be configured to process old L2 signals. Accordingly, a receiver architecture according to embodiments of the present invention is ready for the new L2c signal, and will further be easily updated from time to time with L2c capability as more GPS satellites with L2c capability are launched to orbit. 
         [0055]    Turning now to  FIG. 3 , the RF Front-End Block  10  is depicted in more detail. The signals received by the antenna may be applied by the cable  1 , which may be a high frequency transmission line, to a low noise amplifier  11 , the output of which is applied to the inputs of L1 and L2 channels. The L1 channel may include first stage  12  and second stage  13  while L2 channel may include first stage  14  and second stage  15 . In the first L1 stage  12  the signal may be filtered, amplified, and downconverted to an intermediate frequency IF 1  signal  25 . Similarly, in the first L2 stage  14  the signal may be filtered, amplified, and downconverted to an intermediate frequency IF 2  signal  26 . The IF 1  signal  25  may be further filtered, amplified, and downconverted to video frequency in-phase and quadrature-phase components, and digitized in the second stage block  13 . The output  18  of block  13  may include two lines: a first line for a digital in-phase L1 signal, and a second line for a digital quadrature-phase L1 signal. Similarly, the IF 2  signal  26  may be further filtered, amplified, and downconverted to video frequency in-phase and quadrature-phase components, and digitized in the second stage block  15 , having an output  20  which may include two lines: a first line for a digital in-phase L2 signal, and a second line for a digital quadrature-phase L2 signal. The circuitry of blocks  12 - 15  comprises amplifiers, mixers, filters, and analog-to-digital converters operating in a conventional manner to perform abovementioned signal transformations. In an exemplary embodiment, each of two lines of output  18  is a one-bit line, and each of two lines of output  20  is also a one-bit line, so analog-to-digital converters of the second stages  18  and  20  may be simple comparators with zero threshold. 
         [0056]    A Temperature Compensated Crystal Oscillator (TXCO)  17  supplies a reference frequency on line  24 , which is used in the timing circuitry  16  to generate local oscillator signals on the lines  21 ,  22 , and  23 , as well as a clock signal on line  19 . To this end, the timing circuitry  16  comprises conventional frequency synthesizers. The output signal  19  is used for clocking all other blocks of the receiver. 
         [0057]    Turning to  FIG. 4 , the FPGA  40  schematics are shown. Complex input signals S 1  and S 2  may be supplied to a plurality of identical baseband processing channels  41 - 43 , each of which may be associated with a separate satellite from which a signal is received. The number of baseband channels provided may be sufficient to ensure that a baseband channel is available for each received satellite signal. In an exemplary embodiment, signals from four or more satellites are utilized to make a determination of the desired parameter (e.g., position, velocity and time). Each of the baseband channels  41 - 43  may be capable of recognizing the digitized outputs from the RF Front-End Block  10  on lines  18 ,  20  corresponding to a particular satellite by decorrelating the S 1  and S 2  signals using locally generated replicas of the C/A and P codes unique to a given satellite. 
         [0058]    As illustrated in  FIG. 4 , each baseband channel  41 - 43  may communicate Y 1  and Y 2  data derived from the digital S 1  and S 2  signals to the CPU  50  via interface circuitry  44 , which may connect one of the lines  501 - 506  to the data bus  45  in accordance with a desired channel and its data item Y 1  or Y 2  as defined by the CPU  50  by setting a corresponding address on the address bus  46 . The interface circuitry  44  may also be used to relay control data from the CPU  50  to the baseband channels  41 - 43 . The CPU  50  may control satellite ID number, C/A code phase, P-code phase, pseudo-Doppler frequencies f 1  and f 2 , and initial pseudo-Doppler phases phi01, phi02 in order to match generated L1 and L2 replicas to the received satellite signal. To this end, the CPU  50  may set the address bus  46  in accordance with a destination channel and control item, and put the control data to the data bus  45 . By the control lines  47 , 48  the CPU may indicate read mode (RD) when it receives channel data Y 1  or Y 2 , or may indicate write mode (WR) when it transfers control data to a channel. 
         [0059]    As illustrated in  FIG. 4 , the complex signal S 1  may be mixed in the mixer  413  with a P-code replica generated by P-code generator  420  thereby providing a demodulated output  432 . The structure and organization of the P-code generator  420  may be in conformity with “Interface Control Document ICD-GPS-200C,” by Arine Research Corporation (1993), FIGS. 3.3 . . . 3.7, for example. Similarly, the complex signal S 2  may be mixed in the mixer  414  with the same P-code replica but delayed by a controllable delay line  415  thereby providing a demodulated output  433 . The mixers  413 ,  414  may invert the signs of both in-phase and quadrature-phase components of S 1  or S 2 , correspondingly, if current P-code or delayed P-code value is 1, and let them pass unchanged otherwise. 
         [0060]    Each of the partially demodulated signals  432  and  433  may then be applied to respective phase shifters  418  and  419 , which compensate pseudo-Doppler phases. To this end, an L1 phase generator  421  may generate a phase value phi1 in the line  435  in accordance with initial phase phi01 and frequency f 1 , and an L2 phase generator  424  generates a phase value phi2 in the line  436  in accordance with initial phase phi02 and frequency f 2 . The CPU  50 , via the interface circuitry  44 , may set the values of phi01 phi02, fi f2 before the start of current accumulation period T 2 . The phase shifters  418  and  419  may virtually rotate vectors represented by complex S 1  and S 2  signals by the angle phi1 on the line  435 , and phi2 on the line  436 , correspondingly. 
         [0061]    An in-phase component of the demodulated and Doppler-compensated L1 signal on the line  438  may be applied to accumulator  422  that integrates the signal over time period corresponding to W-bit duration. Simultaneously, both in-phase and quadrature-phase components of the demodulated and Doppler-compensated L2 signal on the line  439  may be applied to accumulators  423  that integrate the signals over time period corresponding to the same W-bit duration. The accumulated L1 in-phase component may be latched in circuitry or a line represented by  440  while both in-phase and quadrature-phase L2 components may be latched in circuitry or a line represented by  441 . 
         [0062]    Accumulated in-phase L2 component may then be separated from the circuit  441  to circuit  442 , and applied to a weighted summator  425  through a controllable switch  426 . Simultaneously, an accumulated in-phase L1 component in the circuit  440  may be applied to another input of the weighted summator  425 . CPU  50  may close or open the switch  426  before the start of current accumulation period T 2  by a command that is routed by the interface circuitry  44  to the switch  426 . The output signal of the weighted summator in circuitry or a line represented by  443  may be applied to a threshold circuit  429 , which extracts the sign of the signal  443  into the line  444 , and compares the magnitude of the signal in circuitry or a line  443  to a threshold. The CPU  50 , via the interface circuitry  44 , may set a threshold value before the start of current accumulation period T 2 . If the signal magnitude exceeds the threshold, the circuit  429  may set its output  445  to 1, otherwise, it may set it to 0. This way conditions indicated in eq. (13) may be checked when the switch  426  is closed, and conditions indicated in eq. (14) may be checked when the switch  426  is open. 
         [0063]    Accumulated complex L2 signal in circuitry or a line represented by  441  may also be mixed in a mixer  427  with the sign delivered by the line  444 . The mixer  427  may simply invert the signs of both in-phase and quadrature-phase components of the complex signal in the circuit  441  if current sign value is 1, and let them pass unchanged otherwise. The mixer output in the circuit  446  may be applied to accumulator  430 , which integrates the signal  446  over a time period (T 2 ). Then, the signal in the line  445  may be used as a clock enable (CE) signal so that the accumulator  430  adds its input in the circuit  446  to a previously accumulated value, only if the CE signal in the line  445  is 1. In this manner, a desired complex L2 signal Y2 may be developed in the line  502  in accordance with eq. (12). 
         [0064]    As also indicated by  FIG. 4 , the complex signal S 1  may be mixed in the mixer  412  with a C/A code replica generated by C/A code generator  411 , thereby providing a demodulated output in the circuit  431 . The structure and organization of the C/A code generator  411  may be in conformity with “Interface Control Document ICD-GPS-200C”. The mixer  412  may simply invert the signs of both in-phase and quadrature-phase components of S 1  if the current C/A code value is 1, and let them pass unchanged otherwise. 
         [0065]    The C/A demodulated signal  431  may then be applied to a phase shifter  417 , which compensates pseudo-Doppler phase. For this operation, the phase value phi1 in the line  435  generated by L1 phase generator  421  in accordance with initial phase phi01 and frequency f 1  may be shifted by π/2 in the phase shifter  416 . The CPU  50 , via the interface circuitry  44 , may set the values of phi01 and f 1  before the start of a current accumulation period T 1 . The phase shifter  417  may virtually rotate the vector represented by complex S 1  signal by the angle phi1=Tr/2 on the line  434 . The phase shifter output in the circuit  437  may be applied to accumulator  428 , which integrates the complex signal  437  over a time period (T 1 ). In this manner, the desired complex L1 signal Y1 may be developed in the line  501 . 
         [0066]      FIG. 5  shows how phase shifters  417 - 419  may be arranged in order to rotate its input vector represented by in phase component I in  in circuitry or a line represented by  481  and quadrature-phase component Q in  in the circuit  482  by the angle phi in circuitry or a line represented by  480 . The circuits  480 - 482  may be merged into one combined circuit  483  that is applied as an address bus to a read-only memory (ROM)  484 . The ROM  484  may store predefined values of shifted complex signal that appear in the data bus  485  in response to address A. Content of ROM  484  may be pre-calculated in such a way that one part of the data bus  485  delivers in-phase component I out  of the phase-shifted signal in the circuit  486  while another part delivers its quadrature-phase component Q out  in the circuit  487 . In this manner, a desired complex output (I out , Q out ) may be generated for each and every combination of input signals (I in , Q in ) and phi. 
         [0067]    To simplify the weighted sum block  425 , equations (13), (14) may be correspondingly approximated by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           
                             
                               
                                 x 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               x 
                               i 
                             
                           
                           , 
                           
                             
                               
                                 y 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               y 
                               i 
                             
                           
                           , 
                           
                             
                               
                                 z 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               z 
                               i 
                             
                           
                           , 
                         
                       
                       
                         
                           
                             
                               if 
                                
                               
                                   
                               
                                
                               4 
                                
                               
                                 x 
                                 i 
                               
                             
                             + 
                             
                               3 
                                
                               
                                   
                               
                                
                               
                                 y 
                                 i 
                               
                             
                           
                           &gt; 
                           
                             
                               0.69 
                                
                               
                                   
                               
                                
                               
                                 σ 
                                 2 
                               
                             
                             
                               a 
                               1 
                             
                           
                         
                       
                     
                     
                       
                         
                           
                             
                               
                                 x 
                                 _ 
                               
                               i 
                             
                             = 
                             0 
                           
                           , 
                           
                             
                               
                                 y 
                                 _ 
                               
                               i 
                             
                             = 
                             0 
                           
                           , 
                           
                             
                               
                                 z 
                                 _ 
                               
                               i 
                             
                             = 
                             0 
                           
                           , 
                         
                       
                       
                         
                           
                             if 
                              
                             
                                 
                             
                              
                             
                                
                               
                                 
                                   4 
                                    
                                   
                                       
                                   
                                    
                                   
                                     x 
                                     i 
                                   
                                 
                                 + 
                                 
                                   3 
                                    
                                   
                                       
                                   
                                    
                                   
                                     y 
                                     i 
                                   
                                 
                               
                                
                             
                           
                           ≤ 
                           
                             
                               0.69 
                                
                               
                                 σ 
                                 2 
                               
                             
                             
                               a 
                               1 
                             
                           
                         
                       
                     
                     
                       
                         
                           
                             
                               
                                 x 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               - 
                               
                                 x 
                                 i 
                               
                             
                           
                           , 
                           
                             
                               
                                 y 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               - 
                               
                                 y 
                                 i 
                               
                             
                           
                           , 
                           
                             
                               
                                 z 
                                 _ 
                               
                               i 
                             
                             = 
                             
                               - 
                               
                                 z 
                                 i 
                               
                             
                           
                           , 
                         
                       
                       
                         
                           
                             
                               if 
                                
                               
                                   
                               
                                
                               4 
                                
                               
                                   
                               
                                
                               
                                 x 
                                 i 
                               
                             
                             + 
                             
                               3 
                                
                               
                                   
                               
                                
                               
                                 y 
                                 i 
                               
                             
                           
                           &lt; 
                           
                             
                               0.69 
                                
                               
                                 σ 
                                 2 
                               
                             
                             
                               a 
                               1 
                             
                           
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   and 
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         
                           
                             
                               x 
                               _ 
                             
                             i 
                           
                           = 
                           
                             x 
                             i 
                           
                         
                         , 
                         
                           
                             
                               y 
                               _ 
                             
                             i 
                           
                           = 
                           
                             y 
                             i 
                           
                         
                         , 
                         
                           
                             
                               z 
                               _ 
                             
                             i 
                           
                           = 
                           
                             z 
                             i 
                           
                         
                         , 
                       
                     
                     
                       
                         
                           if 
                            
                           
                               
                           
                            
                           4 
                            
                           
                               
                           
                            
                           
                             x 
                             i 
                           
                         
                         &gt; 
                         
                           
                             0.69 
                              
                             
                               σ 
                               2 
                             
                           
                           
                             a 
                             1 
                           
                         
                       
                     
                   
                   
                     
                       
                         
                           
                             
                               x 
                               _ 
                             
                             i 
                           
                           = 
                           0 
                         
                         , 
                         
                           
                             
                               y 
                               _ 
                             
                             i 
                           
                           = 
                           0 
                         
                         , 
                         
                           
                             
                               z 
                               _ 
                             
                             i 
                           
                           = 
                           0 
                         
                         , 
                       
                     
                     
                       
                         
                           if 
                            
                           
                               
                           
                            
                           
                              
                             
                               4 
                                
                               
                                   
                               
                                
                               
                                 x 
                                 i 
                               
                             
                              
                           
                         
                         ≤ 
                         
                           
                             0.69 
                              
                             
                                 
                             
                              
                             
                               σ 
                               2 
                             
                           
                           
                             a 
                             1 
                           
                         
                       
                     
                   
                   
                     
                       
                         
                           
                             
                               x 
                               _ 
                             
                             i 
                           
                           = 
                           
                             - 
                             
                               x 
                               i 
                             
                           
                         
                         , 
                         
                           
                             
                               y 
                               _ 
                             
                             i 
                           
                           = 
                           
                             - 
                             
                               y 
                               i 
                             
                           
                         
                         , 
                         
                           
                             
                               z 
                               _ 
                             
                             i 
                           
                           = 
                           
                             - 
                             
                               z 
                               i 
                             
                           
                         
                         , 
                       
                     
                     
                       
                         
                           if 
                            
                           
                               
                           
                            
                           4 
                            
                           
                               
                           
                            
                           
                             x 
                             i 
                           
                         
                         &lt; 
                         
                           
                             0.69 
                              
                             
                               σ 
                               2 
                             
                           
                           
                             a 
                             1 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
         [0068]    Equations (15), (16) are based on an amplitude ratio a 2 /a 1 =1/sqrt(2)≈0.707 in accordance with “Interface Control Document ICD-GPS-200C”, and the amplitude ratio a 2 /a 1  is approximated by ¾ with accuracy of about 6%.  FIG. 6  illustrates an embodiment of the weighted sum block  425 . The input multi-bit x value  425 . 11  in the circuit  440  may be shifted by 2 bits to the left with zeroing the released LSB bits as indicated in  FIG. 6(   b ). In this manner, the quadruplicate 4x value  425 . 12  may be delivered to the circuit  425 . 7 . Similarly, the input multi-bit y value  425 . 21  in the circuit  442  may be shifted by 1 bit to the left with zeroing the released LSB bit and empty MSB bit as also indicated in  FIG. 6(   b ). This way the doubled 2x value  425 . 22  may be delivered to the circuit  425 . 6 . Then y and 2y values may be added in a summator  425 . 3  yielding the 3y signal in the circuit  425 . 8 , which may be further added to the 4x value in another summator  425 . 4 , yielding a desired 4x+3y signal in the circuitry or line  443 . In this manner, a desired weighted sum may be obtained without complicated multiplication operations. 
         [0069]    Referring to  FIG. 7 , a preferred technique is shown for adjusting and locking the carrier and code generators into phase with the carrier and code of the satellite signals being processed. In a first step  511 , the CPU  50  may adjust C/A code phase in the C/A generator  411  and the replica&#39;s frequency in the phase generator  421  in each of processing channels  41 - 43  to maximize the magnitude of the vector Y1 in circuitry or lines represented by  501 - 505 . Because all processing channels may be of identical structure, further description of  FIG. 7  will be provided for only one channel  41 . 
         [0070]    When Y1 magnitude reaches maximum, the nominal C/A-code at the output of C/A generator  411  is in phase with the L1 signal being processed, and CPU  50  calculates L1 signal amplitude as a 1 =[Y1]. Then, in a step  512 , the CPU  50  may set the threshold in the circuit  429  to 0.69σ 2 /a 1 ) in accordance with equations (15), (16). 
         [0071]    A next step  513  is for the CPU  50  to adjust the initial phase phi1 in circuit  435  and, correspondingly, the phase in circuit  434  in order to minimize absolute value of the quadrature-phase component of Y1 in the circuitry or line  501 . When this occurs, the nominal L1 phase in circuit  434  is then known to be in phase with that of the L1 signal being processed. This provides an unambiguous reference for the L1 C/A carrier, and thus also for L1 P-code carrier that is shifted by ninety degrees from it. Then, a time difference of phi1 yields an accurate estimate of pseudo-Doppler frequency f 1  that is used in further steps. 
         [0072]    In a step  514 , the CPU  50  may begin estimating L2 signal parameters by setting a reference frequency f 2 =60/77 f 1  in the L2 phase generator  424 , adjusting P-code phase in the P-code generator  420 , and adjusting L2 delay in the controllable delay line  415  in order to maximize the magnitude of Y2 in the circuit  502 . When this occurs, the P-code phase at the output of the P-code generator  420  is known to be in phase of that of L1 signal being processed, and the P-code phase at the output of the delay line  415  is known to be in phase of that of L2 signal being processed. At this moment, the phase of vector Y2 contains information about L2 pseudo-Doppler phase. 
         [0073]    In a step  515 , the CPU  50  may calculate L2 pseudo-Doppler phase by (12), and adjust correspondingly the initial phase phi02 in the phase generator  424 . This provides the phi2 value in the circuit  436  that ensures compensation of the signal L2 pseudo-Doppler phase in the shifter  419 . In turn, this compensation ensures that the angle θ in (11) is near zero, so it is expedient to use (15) instead of (16) in the process of generating Y2 value. Therefore, the CPU  50  may close the switch  426  to apply the in-phase component of the L2 signal in the circuit  442  to the input of the weighted summator  425 . 
         [0074]    In a step  516 , CPU  50  adjusts the initial phase phi02 in the phase generator  424  in order to minimize absolute value of the quadrature-phase component of Y2 in the circuit  502 . The phi02 value is in fact the desired L2 pseudo-Doppler phase. 
         [0075]    It is noted that embodiments of the present invention may be applied the new L3-L5 signals. Additionally, the embodiments may be used in GPS, GNSS, or any other similar or compatible system. 
         [0076]    According to embodiments of the present invention, a configuration file may simply be created for a new signal. The configuration file may be sent to an end user. The user can communicate the configuration file to the receiver&#39;s CPU which, in turn, may update PROM content correspondingly. 
         [0077]    A receiver architecture according to embodiments of the present invention could have several configuration files in the receiver&#39;s PROM or these files that are interchangeably and dynamically reloaded into the programmable logic (e.g., FPGA) in order to adapt to different situations during operation of the receiver could be generated or modified as needed. 
         [0078]    It will be appreciated that various of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. Also, various presently unforeseen or unanticipated alternatives, modifications, variations or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.