Abstract:
Provided are a communication processing device and a communication system, capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication. A communication processing device, which is connected to a communication network, includes a programmable logic device in which partial rewriting of a logic circuit is possible, during an operation of a host device in the communication network, in which the programmable logic device includes at least two communication processing circuits of which each performs a communication protocol process, and in which one communication processing circuit is operable due to switching, a first communication processing circuit performs communication, and a second communication processing circuit is on standby, updating means for downloading logic circuit data of an updated communication protocol process, from the communication network, and performing a circuit configuration for the second communication processing circuit, a flag that indicates whether or not the circuit configuration for the second communication processing circuit is finished, and by which a circuit configuration state is able to be read to the host device side through communication, and a register that is intended for switching to any one communication processing circuit to be used, and is writable from the host device side through communication.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a communication processing device, a communication method, and a communication system, which are used in various types of communication networks. 
       BACKGROUND ART 
       [0002]    As various types of communication networks, for example, since a host device and a plurality of control devices perform communication through local area network (LAN) ports, and various control devices and the like perform communication with each other, in power systems or industrial systems, a communication network is configured with a communication cable and a communication processing device (for example, a switch). 
         [0003]    In this case, communication is performed according to the communication protocol that defines the terms related to communication on a communication network. Further, data to be communicated is not transmitted all at once, but rather the data is transmitted by being divided into units called packets. A header including a destination address and a source address is added to the packets, in addition to the data to be transmitted. 
         [0004]    The communication processing device that connects the host device and the control device to the communication network includes a plurality of ports, checks the header of the received packet, selects a port for transmission to the destination address, and transmits a packet. A communication process is likely to be performed in combination with a central processing unit (CPU) and dedicated large scale integration (LSI). Examples of the dedicated LSI include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like. Since the dedicated LSI is used, the speed of the communication process can be increased. 
         [0005]    Among these, while the logic circuit in the ASIC is fixed, the FPGA is characterized in that the user can define or change the logic circuit. Although the FPGA has logic circuit information in a configuration random access memory (CRAM) in the inside, the FPGA in which the CRAM is formed with a static random access memory (SRAM) is referred to as an SRAM-type FPGA. The SRAM-type FPGA starts an operation after the logic circuit is configured by reading logic circuit information which is stored in the external flash memory after power is turned on, and writing the logic circuit information to a CRAM. Among the SRAM-type FPGAs, a dynamic partial reconfigurable FPGA can be referred to as a programmable logic device in which the logic circuit can be partially rewritten during an operation. 
         [0006]    Meanwhile, recent power systems and industrial systems are configured such that an internet protocol (IP) communication network has been used for the communication network of the system. As a result, in the power systems and industrial systems, there is a concern about the threat of cyberattacks in the future, and thus it is considered that it is necessary to strengthen the security of the communication network. 
         [0007]    As a countermeasure against such cyberattacks, in a case where a communication packet is determined to be due to cyberattacks, it is necessary to discard the packet and inform the host system of this fact. Since the above operations are performed by the communication protocol process, it is possible to prepare the processing function for threats which have been found in advance, but an additional function is required in the communication protocol process, with respect to new threats. 
         [0008]    As a solution for the problem, PTL 1 describes a configuration method for a communication processing device which rewrites the control circuit of the FPGA depending on the communication contents at any time, and updates the control circuit dynamically without interrupting communication. 
       CITATION LIST 
     Patent Literature 
       [0000]    
       
         PTL 1: JP-A-2000-174844 
       
     
       SUMMARY OF INVENTION 
     Technical Problem 
       [0010]    According to PTL 1, communication control circuits are provided in two FPGAs, network communication is performed by a switching circuit switching the outputs thereof, a new communication function is configured in the other FPGA, while one FPGA performs communication, and thus the switching circuit is configured to switch the outputs of the FPGAs. 
         [0011]    The technology of PTL 1 describes a method by which the communication processing device by itself performs switching between the FPGAs, but there is no disclosure about synchronizing and switching all of the communication processing devices constituting the communication network. If the communication processing devices discretely perform the switching between the FPGAs, the protocol processes are different at the transmitting side and the receiving side, such that there is a problem that communication cannot be performed correctly. 
         [0012]    In addition, in PTL 1, since a plurality of FPGAs are provided, the communication processing device is unavoidably expensive. 
         [0013]    From the above, according to the present invention, it is possible to provide a communication processing device, a communication method, and a communication system capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication. 
       Solution to Problem 
       [0014]    In order to solve the above problem, according to an aspect of the present invention, there is provided a communication processing device which is connected to a communication network, and includes a programmable logic device in which partial rewriting of a logic circuit is possible, during an operation of a host device in the communication network, in which the programmable logic device includes at least two communication processing circuits of which each performs a communication protocol process, and in which one communication processing circuit is operable due to switching, a first communication processing circuit performs communication, and a second communication processing circuit is on standby, updating means for downloading logic circuit data of an updated communication protocol process, from the communication network, and performing a circuit configuration for the second communication processing circuit, a flag that indicates whether or not the circuit configuration for the second communication processing circuit is finished, and by which a circuit configuration state is able to be read to the host device side through communication, and a register that is intended for switching to any one communication processing circuit to be used, and is writable from the host device side through communication. 
         [0015]    Further, according to another aspect of the present invention, there is provided a communication method of a communication system including a plurality of communication processing devices which are connected to a communication network, in which a host device which is connected to one of the communication processing devices, and controls a communication protocol process change of the communication processing circuit transmits logic circuit data of an updated communication protocol process, to another communication processing device, transmits a partial rewriting instruction of logic circuit data which is transmitted to the programmable logic device, reads a flag indicating whether partial rewriting is finished, from the programmable logic device, and checks that the partial rewriting is finished in all of the programmable logic devices, and performs a setting of using an updated communication protocol processing circuit, for all of the programmable logic devices, through communication. 
         [0016]    Further, according to still another aspect of the present invention, there is provided a communication system in which a host device and a control device are connected to a communication network through a communication processing device, in which the communication processing device includes a programmable logic device in which partial rewriting of a logic circuit is possible, during an operation of the host device, and the programmable logic device includes at least two communication processing circuits of which each performs a communication protocol process, and in which one communication processing circuit is operable due to switching, a first communication processing circuit performs communication, and a second communication processing circuit is on standby, updating means for downloading logic circuit data of an updated communication protocol process, from the communication network, and performing a circuit configuration for the second communication processing circuit, a flag that indicates whether or not the circuit configuration for the second communication processing circuit is finished, and by which a circuit configuration state is able to be read to the host device side through communication, and a register that is intended for switching to any one communication processing circuit to be used, and is writable from the host device side through communication. 
       Advantageous Effects of Invention 
       [0017]    According to the present invention, it is possible to securely update a communication protocol process with a simple configuration and technique, while continuing communication. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0018]      FIG. 1  is a diagram illustrating an entire configuration of a communication system in which a host device  1  and a control device  4  perform network communication through a communication processing device  2 . 
           [0019]      FIG. 2  is a block diagram illustrating a schematic configuration of the communication processing device  2 . 
           [0020]      FIG. 3  is a block diagram illustrating a configuration of an FPGA  22  which is a configuration component of the communication processing device  2 . 
           [0021]      FIG. 4  is a block diagram illustrating an internal configuration of a register  22   d.    
           [0022]      FIG. 5  is a diagram illustrating the process of a host device in the update of a communication protocol process. 
           [0023]      FIG. 6  is a flowchart of treatment  1  of the communication processing device in the update of the communication protocol process. 
           [0024]      FIG. 7  is a flowchart of treatment  2  of the communication processing device in the update of the communication protocol process. 
           [0025]      FIG. 8  is a flowchart of treatment  3  of the communication processing device in the update of the communication protocol process. 
           [0026]      FIG. 9  is a flowchart of treatment  4  of the communication processing device in the update of the communication protocol process. 
           [0027]      FIG. 10  is a timing chart between the host device and the communication processing device at the time of update of the communication protocol process. 
           [0028]      FIG. 11  is a block diagram of an FPGA provided with a diagnostic circuit, which is a configuration component of the communication processing device. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0029]    Hereinafter, embodiments of the present invention will be described with reference to the drawings. 
       Embodiment 
       [0030]      FIG. 1  is an entire configuration diagram of a communication system in which a host device and a control device perform network communication through a communication processing device. 
         [0031]    In the communication system of  FIG. 1 , a host device  1  provided in the center and a plurality of control devices  4  provided in a plant site or the like are connected to a communication network  3  through respective communication processing devices  2 , and perform communication. A sensor S present in the plant site, which is provided on the control device  4  side, measures quantities in a process such as a voltage, a current, a temperature, and vibration, which are not illustrated. An actuator A is a relay or a motor as the operation end of the field device. 
         [0032]    The control device  4  in the field converts an analog output that is detected by the sensor S into a digital output, based on a predetermined cycle, and stores the digital output therein. The host device  1  in the center reads data of the sensor S from the control device  4  through communication, determines the control details for the entire system, and forwards the control details for the actuator A to the control device  4 . 
         [0033]    The communication is performed between the host device  1  and the control device  4 , and between the control devices  4  with each other. The communication processing device  2  is connected to the host device  1 , the control devices  4 , and other communication processing devices  2 , over a communication network  3 . If a packet is received from the communication network  3 , each communication processing device  2  checks the header in the packet and determines whether or not the communication is addressed to itself, acquires the packet if it is addressed to itself, and transfers the packet from the port for transmission or discards the packet if it is not addressed to itself. 
         [0034]    Incidentally, although the example of  FIG. 1  illustrates a case where the host device  1  and the control device  4  are connected to the communication network through respective communication processing devices, a plurality of control devices may be connected to the communication network in a wide sense. The host device is also a control device, and is referred to as a control device having a function as a host device. 
         [0035]      FIG. 2  is a block diagram illustrating a schematic configuration of the communication processing device. The communication processing device  2  includes a plurality of ports  20  and  21 , and performs network communication through the communication network  3 .  200  is a network interface of the port  20 , and  210  is a network interface of the port  21 . 
         [0036]    A field programmable gate array (FPGA)  22  receives a packet from an input interface  201  of the port  20 , and transmits a packet to the output interface  202  of the port  20 . Similarly, a packet is received from an input interface  211  of the port  21 , and transmitted to an output interface  212  of the port  21 . In addition, since the FPGA  22  is an LSI in which the user can freely execute a programming job and rewriting is possible, the FPGA  22  has a characteristic in which circuits can be easily changed. 
         [0037]    A flash memory  23  stores the logic circuit information of the FPGA  22 . After power is turned on, the FPGA  22  reads logic circuit information from the flash memory  23  and writes the information to a CRAM in the FPGA  22 , and the FPGA  22  starts an operation after the logic circuit is configured. This means that the processing content of the FPGA  22  is determined by the logic circuit information stored in the flash memory  23  and can be appropriately changed. 
         [0038]    A CPU  24  executes the software process of the communication processing device  2 . A memory  25  stores the program and data which are executed and processed by the CPU  24 , and stores the data processed by the FPGA  22 . The FPGA  22 , the CPU  24 , and the memory  25  are connected through a bus  26 . 
         [0039]    Although it is not illustrated in  FIG. 2 , the control device  4  is connected to the communication processing device  2  through an appropriate communication path, transmits the command of the host device  1  to the control device  4 , and transmits the measurement results in the field of the control device  4  to the host device  1 . The communication path between the communication processing device  2  and the control device  4  is established by, for example, the bus  26 . 
         [0040]      FIG. 3  is a block diagram of an FPGA which is a configuration component of the communication processing device. A region  22 R which is present in the inside of the FPGA  22  is referred to as a variable region, and is a region that is set so as to be dynamically reconfigurable. The region other than the variable region  22 R is referred to as a fixed region, and is a region which is set so as not to be dynamically reconfigurable. In the embodiment of the present invention, it is assumed that a communication processing circuit  22   i  and a communication processing circuit  22   j  are provided in the variable region  22 R, but the number of communication processing circuits that are provided in the variable region  22 R is not limited thereto. Switching circuits  22   b  and  22   h , an interface  22   a , a switching control circuit  22   c , a register  22   d , a memory  22   g , a partial reconfiguration control circuit  22   e , and a CRAM  22   f  are provided in the fixed region of the FPGA  22 . 
         [0041]    In the communication processing device including the FPGA in  FIG. 3 , communication based on the communication protocol that is provided in the communication processing circuit  22   i  in the variable region  22 R is executed at present. The communication protocol that is provided in the communication processing circuit  22   i  is the existing communication protocol which is vulnerable to attacks from external internet sources. In the present invention, communication reinforcement is intended by transmitting information containing a new communication protocol, in which vulnerability is eliminated, to a plurality of communication processing devices from the host device  1 . The configuration and procedures will be described below. 
         [0042]    Among these, the interface  22   a  receives the packet from the input interfaces  201  and  211  of the ports  20  and  21 , and forwards the packet to the switching circuit  22   b  on the inlet side of the variable region  22 R, as the output S 1 . In addition, a packet that is output by the switching circuit  22   h  on the outlet side of the variable region  22 R is received as the input S 10 , and is transmitted to the output interfaces  202  and  212  of the ports  20  and  21 . 
         [0043]    The switching circuit  22   b  on the inlet side of the variable region  22 R receives the output S 2  of the bus  26  of the communication processing device  2 , the output S 3  of the memory  22   g , and the output S 4  of the register  22   d , in addition to the output S 1  of the interface  22   a , and is connected to the input  55  of the communication processing circuit  22   i  or the input S 6  of the communication processing circuit  22   j  in a switchable manner. The switching is performed by using the switching control signal S 7  that is output by the switching control circuit  22   c.    
         [0044]    In contrast, the switching circuit  22   h  on the outlet side of the variable region  22 R selects either the output S 8  of the communication processing circuit  22   i  or the output S 9  of the communication processing circuit  22   j , and is connected to the input S 10  of the interface  22   a , the input S 11  of the bus  26  of the communication processing device  2 , the input S 13  of the register  22   d , and the input S 12  of the memory  22   g , in a switchable manner. The switching by the switching circuit  22   h  on the outlet side of the variable region  22 R is performed by using the switching control signal S 14  that is output by the switching control circuit  22   c.    
         [0045]    The switching control circuit  22   c  outputs the switching control signal S 7  of the switching circuit  22   b  on the inlet side and the switching control signal S 14  of the switching circuit  22   h  on the outlet side, in response to the switching control signal S 15  that is output by the register  22   d.    
         [0046]    The register  22   d  includes a register for temporarily storing and controlling the data that is processed by the communication processing circuit  22   i  or the communication processing circuit  22   j . The register input S 13  of the register  22   d  includes a read/write command, the register address, and the write data of the register  22   d . The register output S 4  of the register  22   d  includes the read data of the register  22   d.    
         [0047]    The memory  22   g  temporarily stores the data that is processed by the communication processing circuit  22   i  or the communication processing circuit  22   j . The memory input S 12  of the memory  22   g  includes the read/write command, the memory address, and the write data of the memory  22   g . The memory output S 3  of the memory  22   g  includes the read data of the memory  22   g.    
         [0048]    The partial reconfiguration control circuit  22   e  performs control for forming a circuit, in the variable region  22 R of the FPGA  22 . If the reconfiguration instruction signal S 16  is received from the register  22   d , the partial reconfiguration control circuit  22   e  outputs a read command and a memory address as the output S 18  to the external flash memory  23 . The logic circuit information is read from the flash memory  23  as an input S 19  in response thereto, and is recorded in the CRAM  22   f . The partial reconfiguration control circuit  22   e  gives the output signal S 20  to the CRAM  22   f , and transmits the logic circuit information that is recorded in the CRAM  22   f  to the variable region  22 R of the FPGA  22 , as the output S 21 . 
         [0049]    In the configuration of the FPGA of  FIG. 3 , the communication processing circuit  22   i  and the communication processing circuit  22   j  which are formed in the variable region  22 R designate a processing destination that processes the received signal the next time, or determine a transmission source of a signal to be transmitted to the outside, in addition to checking the address of the received signal. These functions are executed, for example, by using the communication processing circuit  22   i  as a main system, and the communication processing circuit  22   j  as a standby system, and thus, the logic circuit information is configured in the communication processing circuit  22   i  which is the main system, and the logic circuit information is not configured in the communication processing circuit  22   j.    
         [0050]    The data which is a processing result by the communication processing circuit  22   i  that is the main system is switched and transmitted to the interface  22   a , the bus  26 , the memory  22   g , and the register  22   d  as the output signals S 10 , S 11 , S 12 , and S 13 , by the switching circuit  22   h . Further, the input data pieces that are given to the communication processing circuit  22   i  which is the main system are S 1 , S 2 , S 3 , and S 4 , and are transmitted from the interface  22   a , the bus  26 , the memory  22   g , and the register  22   d , which are respective transmission sources, are switched by the switching circuit  22   b , and are retrieved to the communication processing circuit  22   i.    
         [0051]    The switching control circuit  22   c  uses the communication processing circuit  22   i  as a main system and the communication processing circuit  22   j  as a standby system at a normal time, and when the switching condition is satisfied, the switching control circuit  22   c  gives the outputs S 7  and S 14  for commanding the switching to the switching circuit  22   b  on the inlet side and the switching circuit  22   h  on the outlet side, in order to perform switching to use the communication processing circuit  22   i  as the standby system and the communication processing circuit  22   j  as the main system. 
         [0052]      FIG. 4  is a block diagram illustrating an internal configuration of the register  22   d . The register  22   d  includes a write control circuit  22   d   1 , a read control circuit  22   d   2 , and a plurality of registers. The plurality of registers are configured with a switching setting register  22   d   3 , a reconfiguration setting register  22   d   5 , a reconfiguration end flag register  22   d   6 , and other registers  22   d   4 . 
         [0053]    Among these, the switching setting register  22   d   3  is intended for setting which one of the communication processing circuit  22   i  and the communication processing circuit  22   j  that constitute the variable region  22 R of the FPGA  22  is used to perform a communication process. The reconfiguration setting register  22   d   5  is intended for setting the partial reconfiguration of the FPGA  22 . Specifically, the reconfiguration setting register  22   d   5  sets the start of the partial reconfiguration, the address of the flash memory  23  in which the logic circuit information for partial reconfiguration is stored, and the address of the CRAM  22   f  on which logic circuit information is written. The reconfiguration end flag register  22   d   6  is a register that indicates whether or not the reconfiguration is finished. A plurality of other registers  22   d   4  which are provided are registers that temporarily store the data pieces which are processed by the communication processing circuits  22   i  and  22   j.    
         [0054]    The write control circuit  22   d   1  decodes the input signal S 13 , and writes the input signal to the registers  22   d   3  to  22   d   6 . S 13 W 3  to S 13 W 6  are signals to be written to the respective registers  22   d   3  to  22   d   6 , and D 13  is write data. The read control circuit  22   d   2  decodes the input signal S 13 , selects the read data of the registers  22   d   3  to  22   d   6 , and outputs the read data to the switching circuit  22   b  as the register output. 
         [0055]    The output of the switching setting register  22   d   3  is the switching output S 15  that is given to the switching control circuit  22   c , and the output of the reconfiguration setting register  22   d   5  is the output S 16  that is given to the partial reconfiguration control circuit  22   e . Further, the reconfiguration end flag register  22   d   6  indicates the end of the reconfiguration, with the output S 17  from the partial reconfiguration control circuit  22   e.    
         [0056]    Next, the procedure of changing work for the communication protocol process, which is performed between the host device  1  and the communication processing device  2 , will be described with reference to the processing flowcharts of  FIG. 5  to  FIG. 9 . In addition,  FIG. 5  is a diagram mainly illustrating the processing contents by the host device  1  which instructs the change of the communication protocol process, and  FIGS. 6 to 9  respectively illustrate corresponding processes that are performed by the communication processing device  2  in response to sequential processing requests from the host device  1 . 
         [0057]    In  FIG. 5 , the processing content by the host device  1  is illustrated on the right side, and the processing content by the communication processing device  2  is illustrated on the left side in contrast. Among these, the outline of the processing content by the host device  1  illustrated on the right side is as follows. First, in the first processing step S 100 , the FPGA circuit data of the communication protocol process to be updated is transmitted to the communication processing device  2 . In the processing step S 101 , the reconfiguration of the FPGA circuit is instructed to the communication processing device  2 . In the processing step S 102 , the reconfiguration end flag of the FPGA circuit is read from the communication processing device. In the processing step S 103 , it is checked whether or not the reconfiguration end flag indicates the end. Until the reconfiguration end flags of all of the communication processing devices indicate the end, the process of S 102  is continued for the communication process which is not finished. In  103 , if the reconfiguration end flags of all of the communication processing devices indicate the end, the process proceeds to S 104 , and the switching between the communication protocol processing circuits is instructed to the communication processing device. 
         [0058]    In contrast, each communication processing device  2  responds as follows. 
         [0059]    First, in the processing step S 100  of the host device  1 , the communication processing device  2  performs the processing step S 200  of  FIG. 6 .  FIG. 6  is a flowchart of treatment  1  of the communication processing device, in the updating of the communication protocol process. In the processing step S 2001  of  FIG. 6 , the FPGA circuit data of the communication protocol process to be updated is received from the host device  1 . In the next processing step S 2002 , the FPGA circuit data is written to the flash memory  23 . If the flow of signals up to the writing of the FPGA circuit data to the flash memory  23  is described, the flow is S 1 →S 8 →S 13 →S 16 →S 18 , in  FIGS. 3 and 4 . 
         [0060]    The communication processing device  2  performs the processing step S 201  of  FIG. 7 , with respect to the processing step S 101  of the host device  1 .  FIG. 7  is a flowchart of treatment  2  of the communication processing device, in the updating of the communication protocol process. In the processing step S 2011  of  FIG. 7 , the reconfiguration of the FPGA circuit is instructed by the host device  1 . In the processing step S 2012 , the FPGA circuit data is read from the flash memory  23 , and is written to the CRAM  22   f . Further, the partial reconfiguration control circuit  22   e  gives the output signal S 20  to the CRAM  22   f , transmits logic circuit information that is recorded in the CRAM  22   f  as an output S 21  to the variable region  22 R of the FPGA  22 , and transmits and writes the logic circuit information to the communication processing circuit  22   j  on the standby side in the variable region  22 R. Further, the partial reconfiguration control circuit  22   e  gives an output S 17  that means the end at the time when the reconfiguration is finished. If the flow of the signals to be written to the CRAM  22   f  and the like is described, S 19 , S 20 , S 21 , and S 17  in  FIG. 3  correspond thereto. 
         [0061]    The communication processing device  2  performs the processing step S 202  of  FIG. 8 , with respect to the processing step S 102  of the host device  1 .  FIG. 8  is a flowchart of treatment  3  of the communication processing device, in the updating of the communication protocol process. In the processing step S 2021  of  FIG. 8 , the read reconfiguration end flag S 17  of the FPGA circuit is received from the host device  1 . In the processing step S 2012 , the reconfiguration end flag  22   d   6  of the FPGA circuit is transmitted to the host device  1 . If the flow of signals up to the transmission of the reconfiguration end flag  22   d   6  to the host device  1  is described, the flow is  22   d   6 →S 4 →S 8 →S 10 , in  FIGS. 3 and 4 . 
         [0062]    The communication processing device  2  performs the processing step S 204  of  FIG. 9 , with respect to the processing step S 104  of the host device  1 .  FIG. 9  is a flowchart of treatment  4  of the communication processing device, in the updating of the communication protocol process. In the processing step S 2041  of  FIG. 9 , a switching instruction of the communication protocol processing circuit is received from the host device  1 . In the processing step S 2042 , the communication processing device is on standby for the switching timing of the communication protocol processing circuit. In the processing step S 2043 , the switching between the communication protocol circuits is performed. This flow is executed by the output S 15  of the register  22   d  of  FIG. 3  acting as a switching timing signal, the switching control circuit  22   c  giving the output S 7  to the switching circuit  22   b  on the input side, and the switching control circuit  22   c  giving the output S 14  to the switching circuit  22   h  on the output side, and the subsequent process in the variable region  22 R of the FPGA  22  is executed by using the communication processing circuit  22   j  which was a standby side as a main system, and with the communication processing circuit  22   i  which was the main system as a standby system. In this case, the communication protocol of the communication processing circuit  22   j  which was the standby side is replaced with the latest communication protocol from the host device  1 , and it is assumed that the subsequent communication is performed by being reflected from the latest situation. 
         [0063]      FIG. 10  is a timing chart between the host device  1  and the communication processing device  2 , in the updating of the communication protocol process. The reference numerals in the drawing correspond to the symbols of the processing steps of the flowchart of  FIG. 5  to  FIG. 9 . Since there are a plurality of communication processing devices  2 , the respective processes for three communication processing devices  2 I,  2 J, and  2 K will be described. 
         [0064]    In  FIG. 10 , the states of the host device  1  and the communication processing devices  2 I,  2 J, and  2 K are illustrated in order from the top. Further, in  FIG. 10 , the execution periods of the processing steps of the flowcharts of  FIG. 5  to  FIG. 9 , the flags, and the switching states are illustrated. 
         [0065]    Here, flag “0” means a state in which the communication protocol of the communication processing circuit  22   j  which is the standby system is the initial value, here, a state of no information. Therefore, flag “1” means a state in which the communication protocol of the communication processing circuit  22   j  which is the standby system is updated. Further, switching “A” means the communication by the communication processing circuit  22   i  which is the standby system, and switching “B” means the communication by the communication processing circuit  22   j  which is the standby system. Further, in the state before changing work of the communication protocol is started, in a state in which the host device  1  and the communication processing devices  2 I,  2 J, and  2 K are placed, the flag is “0”, and switching is “A”. After the flags of the communication processing devices  2 I,  2 J and  2 K are recognized as “0”, the host device  1  tries to perform the switching from the present. 
         [0066]    First, the host device  1  transmits the FPGA circuit data of the communication protocol process to be updated to the communication processing devices  2 I,  2 J, and  2 K in the processing step S 100 . 
         [0067]    The communication processing devices  2 I,  2 J, and  2 K each receive the FPGA circuit data of the communication protocol process to be updated from the host device  1  in the processing step S 200 , and write the FPGA circuit data to the flash memory in the processing step S 2002 . 
         [0068]    The host device  1  instructs the communication processing devices  2 I,  2 J, and  2 K to reconfigure the FPGA circuit in the processing step S 101 . The communication processing devices  21 ,  2 J, and  2 K are instructed to reconfigure the FPGA circuit from the host device  1  in the processing step S 201 , read the FPGA circuit data from the flash memory  23  in the processing step S 2012 , and write the FPGA circuit data to the CRAM  22   f . Further, subsequently, the logic circuit information is transmitted to the variable region  22 R of the FPGA  22  as the output S 21 , is forwarded to the communication processing circuit  22   j  on the standby side in the variable region  22 R, and is subjected to a writing process. In  FIG. 10 , the processing step S 2012  is represented in a wide way, and this indicates that it takes time for this process. 
         [0069]    Next, the host device  1  instructs the individual communication processing devices to perform work of reading the reconfiguration end flag of the FPGA circuit in the communication processing device in the processing step S 102 .  FIG. 10  means that the communication processing device  2 I is first instructed, and since this case is the timing when the process of the processing step S 2012  has not been completed, the flag from the communication processing device  2 I indicates “0”. In addition, next, the flag “1” can be recognized in the process that is performed on the communication processing device  2 J, and the flag “1” is also received from the communication processing device  2 K in the same manner. The communication processing device  2 I, which failed the first time, is successful in the subsequent second trial. In this manner, the communication processing devices  2 I,  2 J, and  2 K receive the read reconfiguration end flag of the FPGA circuit from the host device  1  in the processing step S 202 , and transmit the flag to the host device  1  in the processing step S 2002 . 
         [0070]    If all of the reconfiguration end flags that are read from the communication processing devices  2 I,  2 J, and  2 K indicate end (the value is 1), the host device  1  instructs communication processing devices  2 I,  2 J, and  2 K to switch the communication protocol processing circuit in the processing step S 104 . The communication processing devices  2 I,  2 J, and  2 K receive the switching instruction of the communication protocol processing circuit from the host device  1  in the processing step S 2041 , are on standby for the switching timing of the communication protocol processing circuit in the processing step S 2042 , and rewrite the switching setting register from “A” to “B” in the processing step S 2043 . 
         [0071]      FIG. 11  illustrates a modification example of the present invention. Here, the FPGA  22  in  FIG. 3  is configured to include a diagnostic circuit. 
         [0072]    The diagnostic circuit  22   k  receives a part of the input of the communication processing circuit  22   i  or  22   j  that is in communication as a first diagnostic input S 30  from the switching circuit  22   b  on the input side, receives a part of the output of the communication processing circuit  22   i  or  22   j  that is in communication as a second diagnostic input S 32  from the switching circuit  22   h  on the output side, executes a diagnosis as to whether or not a communication process is performed correctly, and outputs the diagnosis result signal S 33 . 
       REFERENCE SIGNS LIST 
       [0000]    
       
         
           
               1 : HOST DEVICE 
               2 : COMMUNICATION PROCESSING DEVICE 
               3 : COMMUNICATION NETWORK 
               4 : CONTROL DEVICE 
             S: SENSOR 
             A: ACTUATOR 
               20 ,  21 : PORT 
               22 : FPGA 
               22 R: VARIABLE REGION 
               22   i ,  22   j : COMMUNICATION PROCESSING CIRCUIT 
               22   b ,  22   h : SWITCHING CIRCUIT 
               22   a : INTERFACE 
               22   c : SWITCHING CONTROL CIRCUIT 
               22   d : REGISTER 
               22   e : PARTIAL RECONFIGURATION CONTROL CIRCUIT 
               22   f : CRAM 
               22   g : MEMORY 
               23 : FLASH MEMORY 
               24 : CPU 
               25 : MEMORY 
               26 : BUS 
               200 ,  210 : NETWORK INTERFACE 
               201 ,  211 : INPUT INTERFACE