Abstract:
A nonvolatile memory includes a memory cell allay including a plurality of memory cells, each of the memory cells capable of storing electric charges nonvolatilly, a first sense amplifier for comparing a voltage produced by one of the selected memory cells to be read out with a first threshold value for distinguishing between a write state and an erase state of the selected memory cell, a second sense amplifier for comparing the voltage produced by one of the selected memory cell with a second threshold value having a greater voltage than the first threshold voltage, and a write unit for rewriting data of the selected memory cell when the first and the second sense amplifiers produce different sense outputs from each other.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-311999 filed on Dec. 8, 2008, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    An aspect of the embodiments discussed herein is directed to a nonvolatile memory. 
       BACKGROUND 
       [0003]    In recent years, memory devices with a USB (Universal Serial Bus) memory, a flash memory card, or other such nonvolatile memories have been widely used for reasons of large capacity, nonvolatile property, and low power consumption. 
         [0004]    A reliability of long-term data storage is required of these memory devices. In addition, demands for memory devices of larger capacity grow along with an increase in data size such as an image or a moving picture. Then, reduction of a process for a nonvolatile memory has been actively performed. 
         [0005]      FIG. 33  is a circuit diagram illustrating the basic cell structure of a NAND nonvolatile memory. A nonvolatile memory (Nonvolatile memory)  90  has plural NAND cells (Cells) (memory transistors)  92  in a NAND cell group  91  connected in series. 
         [0006]    Any NAND cell  92  is selected by a select gate (Select Gate)  93 . Further, erasing is carried out for each NAND cell group  91 . Each NAND cell  92  includes a control gate (Control Gate)  92   a  and a floating gate (Floating Gate)  92   b.    
         [0007]      FIG. 34A  and  FIG. 34B  illustrate how data is written/erased to/from a nonvolatile memory.  FIG. 34A  illustrates how data is written to the nonvolatile memory. The floating gate  92   b  is insulated from the control gate  92   a  and a substrate (Substrate)  92   c  through a gate oxide film (Gate oxide)  92   d  and assumed electrically floating. 
         [0008]    However, if a high voltage is applied between the control gate  92   a  and the substrate  92   c , charges may be injected to the floating gate  92   b  from the substrate  92   c  through the gate oxide film  92   d  due to FN (Fowler-Nordheim) tunnel phenomenon. 
         [0009]    Since the floating gate  92   b  is in an electrically floating state, charges may be held even when the power is turned off. The injection of charges is generally called “write” or “program (Program)”. 
         [0010]    Further, as illustrated in  FIG. 34B , if a high-voltage is applied in an opposite direction to the write direction, the charges injected into the floating gate  92   b  may be similarly released to the substrate  92   c  through the gate oxide film  92   d  due to the FN tunnel phenomenon. The release of charges is generally called “clear” or “erase (Erase)”. 
         [0011]    In general, the NAND nonvolatile memory is assumed in write state (logic “0”) when charges are injected and in erase state when charges are released (logic “1”). Accordingly, Japanese Laid-open Patent Publication No. 2007-164937 discusses a technique that a memory cell of nonvolatile semiconductor memory device stores one data value selected from the same number of data values as programming distribution ranges, the one data value being associated with the electrical attribute belonging to any one of the more than one programming distribution ranges. 
       SUMMARY 
       [0012]    According to an aspect of an embodiment, a nonvolatile memory includes a memory cell allay including a plurality of memory cells, each of the memory cells capable of storing electric charges nonvolatilly, a first sense amplifier for comparing a voltage produced by one of the selected memory cells to be read out with a first threshold value for distinguishing between a write state and an erase state of the selected memory cell, a second sense amplifier for comparing the voltage produced by one of the selected memory cell with a second threshold value having a greater voltage than the first threshold voltage, and a write unit for rewriting data of the selected memory cell when the first and the second sense amplifiers produce different sense outputs from each other. 
         [0013]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0014]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  schematically illustrates a nonvolatile memory according to an embodiment; 
           [0016]      FIG. 2  illustrates a hardware structure example of a module according to the embodiment; 
           [0017]      FIG. 3  is a block diagram illustrating the configuration of a NAND controller; 
           [0018]      FIG. 4  is a block diagram illustrating the configuration of a nonvolatile memory; 
           [0019]      FIG. 5  is a block diagram illustrating the configuration of a sense amplifier circuit; 
           [0020]      FIG. 6  illustrates a configuration example of a status register; 
           [0021]      FIG. 7  illustrates the page structure; 
           [0022]      FIG. 8  illustrates the page structure; 
           [0023]      FIG. 9  illustrates a command function supplied to a nonvolatile memory; 
           [0024]      FIG. 10  is a flowchart illustrating processing for determining whether to execute refresh processing; 
           [0025]      FIG. 11  is a flowchart illustrating refresh processing; 
           [0026]      FIG. 12  is a flowchart illustrating refresh processing; 
           [0027]      FIG. 13  illustrates effects of refresh processing; 
           [0028]      FIG. 14  is a flowchart of processing for displaying information representing that refresh processing is being executed on a display; 
           [0029]      FIG. 15  is a flowchart of processing performed at the time of displaying a screen for prompting a user to replace a nonvolatile memory; 
           [0030]      FIG. 16  is a block diagram illustrating the configuration of a sense amplifier circuit according to a second embodiment; 
           [0031]      FIG. 17  is a block diagram illustrating a nonvolatile memory according to a third embodiment; 
           [0032]      FIG. 18  illustrates a command function of the nonvolatile memory of the third embodiment; 
           [0033]      FIG. 19  is a flowchart of the refresh processing of the third embodiment; 
           [0034]      FIG. 20  is a flowchart of the rewrite processing; 
           [0035]      FIG. 21  is a block diagram of a nonvolatile memory according to a fourth embodiment; 
           [0036]      FIG. 22  illustrates a command function of the nonvolatile memory of the fourth embodiment; 
           [0037]      FIG. 23  is a flowchart illustrating the rewrite processing of the fourth embodiment; 
           [0038]      FIG. 24  is a flowchart illustrating the processing for updating a mapping table; 
           [0039]      FIG. 25  is a block diagram illustrating the configuration of a NAND controller according to a fifth embodiment; 
           [0040]      FIG. 26  illustrates an example of information about the preset number of accesses; 
           [0041]      FIG. 27  is a flowchart of the processing for determining whether to execute refresh processing of the fifth embodiment; 
           [0042]      FIG. 28  is a flowchart illustrating the refresh interval change processing; 
           [0043]      FIG. 29  illustrates effects of the refresh interval change processing; 
           [0044]      FIG. 30  is a block diagram illustrating the configuration of a NAND controller according to a seventh embodiment; 
           [0045]      FIG. 31  illustrates current date and time information set in a nonvolatile memory; 
           [0046]      FIG. 32  is a flowchart illustrating the processing for determining whether to execute refresh processing of the seventh embodiment; 
           [0047]      FIG. 33  is a circuit diagram illustrating the basic cell structure of a NAND nonvolatile memory; 
           [0048]      FIG. 34A  and  FIG. 34B  illustrate how data is written to or erased from a nonvolatile memory; 
           [0049]      FIG. 35A  and  FIG. 35B  illustrate how a gate oxide film degrades due to a FN tunnel phenomenon; 
           [0050]      FIG. 36  is a graph illustrating a relationship between an elapsed time and a voltage change of a floating gate; and 
           [0051]      FIG. 37  is a graph illustrating a relationship between the number of write operations and data storage time. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0052]    As described previously, since data is written/erased to/from the NAND nonvolatile memory utilizing a FN tunnel current, memory cells are degraded upon each write and erase.  FIG. 35A  and  FIG. 35B  illustrate how a gate oxide film degrades due to the FN tunnel phenomenon. 
         [0053]    The FN tunnel phenomenon may induce movement of charges through the gate oxide film  92   d  by applying a high voltage but a small amount of charges are sometimes trapped into the gate oxide film  92   d . The number of write operations increases thereby, resulting in degradation of the gate oxide film  92   d  and increase of a leak current (Increase of Leak Current). 
         [0054]    An amount of leak current flowing between the floating gate  92   b  and the substrate  92   c  increases due to the degradation of the gate oxide film  92   d , and charges may not be held. This phenomenon imposes a limitation on the number of times data is written/erased to/from a nonvolatile memory (hereinafter referred to as the number of write operations) as a general rule. Then, data storage capacity is reduced in proportion to the number of write operations. 
         [0055]    Embodiments of the present invention will be illustrated below in detail with reference to the accompanying drawings. 
         [0056]      FIG. 36  is a graph illustrating a relationship between an elapsed time and a voltage change of a floating gate. It is assumed that a voltage level of the floating gate in the erase state of the NAND nonvolatile memory is 4 V, and a preset value of a sense amplifier (SA) for distinguishing between the write state and the erase state is 1 V by way of example. 
         [0057]    As described above, a voltage level of the floating gate is gradually reduced over time due to a leak current between the floating gate and the substrate. In  FIG. 36 , the sense amplifier determines whether the data logic is “1” or “0” based on whether the voltage of the floating gate is 1 V or more. Accordingly, the logic of the NAND cell is inverted with time, leading to a read error. 
         [0058]      FIG. 37  is a graph illustrating a relationship between the number of write operations and data storage time. At 10,000 th  write operation, data may be held for about 20 years. After that, however, the data storage time is reduced in proportion to the number of write operations. After 100,000 write operations, data may be held for 10 years. At 1,000,000 th  write operation, data may be held for only 0.5 years. 
         [0059]    A manufacturing process is proceeding to finer ones with an aim to reducing costs and increasing a capacity. However, the thickness of the gate oxide film is not largely changed, and a voltage necessary for write or erase is not largely changed as well. Thus, a voltage applied to the gate oxide film is relatively increased, which causes problems that degradation occurs more obviously as the process proceeds to finer ones, and data storage capacity is accordingly reduced. 
         [0060]    Therefore, a nonvolatile memory requested to store data at low price in large amounts, and for a long time needs to be prevented from reducing data storage capacity due to a finer manufacturing process. Next, a nonvolatile memory of the embodiment is described. Then, the embodiment is described in more detail. 
         [0061]      FIG. 1  schematically illustrates a nonvolatile memory of the embodiment. A nonvolatile memory  1  includes a memory cell array  2 , a first sense amplifier  3 , a second sense amplifier  4 , and a write unit  5 . 
         [0062]    The memory cell array  2  includes plural memory cells with a floating gate. The first sense amplifier  3  compares a voltage value of a floating gate with a threshold value for distinguishing between a write state and erase state of each memory cell. 
         [0063]    The second sense amplifier  4  compares a voltage value of a floating gate with a threshold value for distinguishing between a write state and erase state of each memory cell. Here, as illustrated in  FIG. 1 , the first threshold value and the second threshold value may be externally input or generated in the nonvolatile memory  1 . 
         [0064]    The write unit  5  rewrites data of a memory cell with a floating gate a voltage value of which is smaller than the second threshold value as a result of determination with the second sense amplifier  4 . 
         [0065]    Since the thus-structured nonvolatile memory  1  keeps a write state of a memory cell having a voltage value lower than the second threshold value, a reliability of data may be improved. The embodiment is described in more detail below. 
         [0066]      FIG. 2  illustrates a hardware structure example of a module of the embodiment. A module (Module)  10  is entirely controlled by a CPU (Central Processing Unit)  11 . The CPU  11  is connected to a chipset (Chipset)  12 . 
         [0067]    The chipset  12  includes a north bridge (North Bridge)  12   a  and a south bridge (South Bridge)  12   b . The north bridge  12   a  is connected to peripheral devices operating at relatively high speed and designed to exchange data with the devices. In  FIG. 2 , a memory (Memory)  13 , a PCI Express  14 , and a display (Display)  15  are connected thereto. 
         [0068]    The memory  13  temporarily stores at least a part of programs of an OS (Operating System) and application programs executed on the CPU  11 . In addition, the memory  13  stores various kinds of data necessary for processing on the CPU  11 . 
         [0069]    The north bridge  12   a  displays an image on a screen of the display  15  in accordance with a command from the CPU  11 . The south bridge  12   b  is connected to peripheral devices operating at relatively low speed. In  FIG. 2 , an audio interface (Audio I/F)  16 , a USB/PCI  17 , a BIOS  18 , a LAN interface  19 , and a nonvolatile module (Nonvolatile module)  20  are connected thereto. 
         [0070]    The nonvolatile module  20  includes a NAND controller (NAND Controller)  21 , and a NAND nonvolatile memory (NAND Flash Memory IC)  22  (hereinafter simply referred to as “nonvolatile memory”) connected to the NAND controller  21 . 
         [0071]    The NAND controller  21  selects any area in the nonvolatile memory  22  and validates data in the selected area. The data is validated based on ECC information in data of a management area associated with the selected area. 
         [0072]    The nonvolatile memory  22  stores an OS or application programs. The nonvolatile memory  22  further stores program files. Here, the present invention is not limited to the configuration in  FIG. 22 , and the north bridge  12   a  and the south bridge  12   b  may be integrated into one chip. Further, the NAND controller  21  and the nonvolatile memory  22  may be independently provided. 
         [0073]    Further, a not-illustrated HDD (Hard Disk Drive) may be provided independently of the nonvolatile module  20 . A processing function of this embodiment is realized by the above hardware structure. 
         [0074]      FIG. 3  is a block diagram illustrating the configuration of the NAND controller. The NAND controller  21  includes a host interface unit (Host Interface Unit)  211 , a control register (Control Register)  212 , a power management unit (Power Management Unit)  213 , a buffer (Buffer)  214 , an ECC processing unit  215 , and a NAND interface unit (NAND Interface Unit)  216 . 
         [0075]    The host interface unit  211  communicates with the CPU  11 . The control register  212  stores a command from the CPU  11  and illustrates a state of the NAND controller  21 . 
         [0076]    The power management unit  213  supplies power to the entire NAND controller  21 . The buffer  214  temporarily stores data exchanged between the CPU  11  and the nonvolatile memory  22 . 
         [0077]    The ECC processing unit  215  generates an ECC from data, and performs encoding/decoding with the ECC and error correction processing. The NAND interface unit  216  communicates with the nonvolatile memory  22 . 
         [0078]      FIG. 4  is a block diagram illustrating the structure of the nonvolatile memory. The nonvolatile memory  22  includes an I/O buffer circuit (I/O Buffer Circuit)  221 , a command register (Command Register)  222 , a control unit (Control Logic)  223 , an address register (Address Register)  224 , a NAND flash array (NAND Flash Array)  225 , an X decoder (X Decoder)  226 , a Y decoder (Y Decoder)  227 , and a sense amplifier circuit (Sense Amplifier Circuit)  228 . 
         [0079]    The I/O buffer circuit  221  receives various commands and address signals, and data to be written to the NAND flash array  225 , and outputs data read from the NAND flash array  225  and then latched. 
         [0080]    The command register  222  latches an input command and determines an internal operation based on data of the input signal. As for “Lo active” signals, “/” is prefixed to a signal name. 
         [0081]    “/CL” denotes a signal for selecting the command register  222  or the control unit  223 . “/AL” denotes a signal for selecting an address register or data register of the nonvolatile memory  22 . 
         [0082]    “/CE” denotes a signal for selecting an active mode or standby mode of the nonvolatile memory  22 . “/RE” denotes a signal for prompting data output. 
         [0083]    “/WE” denotes a read/write instruction signal, which is shifted to a write mode when in active state. “/WP” denotes a signal for forcedly inhibiting write and erase operations. “/SES” denotes a control signal for selecting one of a main sense amplifier and a sub sense amplifier as described below to allow output of the selected amplifier. 
         [0084]    The control unit  223  reads data from, writes data to, and erases data from each memory cell in the nonvolatile memory  22  based on input signals. In addition, the control unit  223  includes a high voltage generator (High voltage generator)  223   a . The high voltage generator  223   a  applies a drive voltage to the X decoder  226  and the NAND flash array  225 . 
         [0085]    Further, the control unit  223  outputs an R/B signal for notifying any external unit of an internal operation of the control unit  223 . The address register  224  generates a row address and column address at which data is to be read, written, and erased, based on the input address signal, and when in page mode, automatically increments the address. 
         [0086]    The X decoder  226  decodes the row address output from the address register  224  and selects a word line (not illustrated) of the memory cell in the NAND flash array  225 . The Y decoder  227  decodes the column address output from the address register  224  and reads/writes data from/to the memory cell through the selected data line (not illustrated). 
         [0087]    The sense amplifier circuit  228  uses a main sense amplifier as described below to receive data in a memory cell selected through column selection and positioned at an intersection with a word line selected through row selection, and sends the data to the I/O buffer circuit  221 . In the case of writing data, a word line in a row selected in the same manner as above and a memory cell connected to the sense amplifier circuit  228  selected by the X decoder  226  are used, and information input from the data line through a data input circuit is written to the memory cell of the NAND flash array  225 . 
         [0088]      FIG. 5  is a block diagram illustrating the configuration of the sense amplifier circuit. The sense amplifier circuit  228  includes a main reference cell (Main Reference Cell)  2281 , a sub reference cell (Sub Reference Cell)  2282 , a main sense amplifier (first sense amplifier)  2283 , a sub sense amplifier (second sense amplifier)  2284 , and a logic circuit (Logic Circuit)  2285 . 
         [0089]    The main reference cell  2281  applies a voltage of 1 V to the main sense amplifier  2283 . The sub reference cell  2282  applies a voltage of 2 V (a voltage higher than the voltage applied with the main reference cell  2281 ) to the sub sense amplifier  2284 . 
         [0090]    The main sense amplifier  2283  is a current detection type sense amplifier, which is used to read/write/erase data from/to/from the NAND flash array  225 . For example, during a data read operation, an output current of the NAND flash array  225  is compared with a current flowing through the main reference cell  2281  to output logic of the comparison result to the logic circuit  2285 . More specifically, if the output current of the NAND flash array  225  is larger than or equal to the target current, the logic “1” is output. If the current flowing through the main reference cell  2281  is larger, the logic “0” is output. 
         [0091]    The sub sense amplifier  2284  is a current detection type sense amplifier, which is used to measure a margin. The sub sense amplifier  2284  compares an output current of the NAND flash array  225  with a current flowing through the sub reference cell  2282  and outputs logic of the comparison result to the logic circuit  2285 . To be specific, if the output current of the NAND flash array  225  is larger than or equal to the target current, the logic “1” is output. If the current flowing through the sub reference cell  2282  is larger, the logic “0” is output. 
         [0092]    The logic circuit  2285  selects one of an output signal of the main sense amplifier  2283  and an output signal of the sub sense amplifier  2284  in response to input of the “/SES” signal, and outputs the selected signal Data- 0 . As a result, general reading/writing/erasing operations and a margin measuring operation may be switched. In other words, the main sense amplifier  2283  is selected for the general reading/writing/erasing operations, and the sub sense amplifier  2284  is periodically selected to check a voltage level of a floating gate. 
         [0093]    Then, if the voltage level of the floating gate is below the voltage of 2 V applied by the sub reference cell  2282 , data is held through rewriting. Here, such processing of the sub sense amplifier  2284  is performed through refresh processing as described below. 
         [0094]    Next, a configuration example of a status register in the NAND controller  21  is described.  FIG. 6  illustrates a configuration example of a status register. A status register  30  is an 8-bit register. In  FIG. 6 , a value indicating that refresh processing is being executed is set (set) in the first bit (REFR) of the first sense amplifier  30 . For example, if “1” is set in REFR, refresh processing is being executed. If “0” is set, no refresh processing is executed. 
         [0095]    Further, “1” is set in the fifth bit (DWF) when a write error occurs in the nonvolatile memory  22 . Next, the data structure of the NAND flash array  225  is described. 
         [0096]    The inside of the NAND flash array  225  is managed on the basis of plural blocks. One block includes plural pages.  FIGS. 7 and 8  illustrate the page structure. 
         [0097]    The write unit in the nonvolatile memory  22  is 2 KByte. The write unit includes four pages each set to 528 bytes. One page includes a sector (Sector) of 512 bytes and a spare (Spare) of 16 bytes. 
         [0098]    Four sectors A, B, C, and D constitute a data field (Data Field) of 2 Kbytes. Further, four spares a, b, c, and d constitute a spare field (Spare Field) of 64 bytes. 
         [0099]    The spare a is a spare area of the sector A, the spare b is a spare area of the sector B, the spare c is a spare area of the sector C, and the spare d is a spare area of the sector D. 
         [0100]    Here, at the time of writing data, data is written such that the logic of the first byte of the sector A is fixed to “0”. As for the second byte to 512 th  byte, user data is written. Refresh processing is performed by checking a voltage value of the first byte of the sector A. 
         [0101]    By fixing the logic of the first byte to “0” as above, a corresponding cell is degraded stably (at a constant speed). Thus, a margin may be measured with high accuracy. As illustrated in  FIG. 8 , each spare (in  FIG. 8 , spare E) includes preset areas such as LSN (Logical Sector Number), DV (Data validity), BBI (Bad Block Information), ECC (ECC Code for Data Field), ECCS (ECC Code for Spare Field), RSV (Reserved Area), and RC (Refresh Counter). 
         [0102]    Among those, a refresh counter of 8 th  byte, the number of times refresh processing is performed is stored.  FIG. 9  illustrated a command function supplied to the nonvolatile memory. 
         [0103]    In a command function table  40 , columns of function (Function), a first cycle (1 st  cycle), and a second cycle (2 nd  cycle) are set. Information in each record are associated with one another. 
         [0104]    A command is input in two steps, the first cycle and the second cycle, to the I/O buffer circuit  221  in a serial manner. The command input in the serial manner is transferred to the command register  222 . Thus, the main sense amplifier  2283  or the sub sense amplifier  2284  may be selected without adding an input terminal to an external terminal. 
         [0105]    To be specific, a read operation (Read with Main SA) of the main sense amplifier  2283  is performed by sending a command code “00h” at the first cycle and a command code “30h” at the second cycle. 
         [0106]    Further, a read operation (Read with Sub SA) of the sub sense amplifier  2284  is performed by sending a command code “00h” at the first cycle and a command code “31h” at the second cycle. 
         [0107]    Further, the command codes “30h” and “31h” are given for illustrative purposes, and another code may be assigned. Next, a description is made of refresh processing performed with the nonvolatile memory  22  in response to an instruction from the NAND controller  21 . 
         [0108]      FIG. 10  is a flowchart illustrating processing for determining whether to execute refresh processing. First, the NAND controller  21  measures an elapsed time with a clock of the CPU  11  (step S 1 ). 
         [0109]    Then, it is determined whether the elapsed time reaches a preset time (whether to execute refresh processing) (step S 2 ). The elapsed time is a time from previous refresh processing. 
         [0110]    If the elapsed time does not reach a preset time (No in step S 2 ), the processing shifts to step S 1 , and step S 1  and subsequent steps are performed. On the other hand, if the elapsed time reaches a preset time (YES in step S 2 ), “1” is set in “REFR” of the status register  30  (step S 3 ). 
         [0111]    Next, refresh processing is performed (step S 4 ). After the completion of refresh processing, “0” is set in “REFR” of the status register  30  (step S 5 ). 
         [0112]    That is the end for the description about the processing for determining whether to execute refresh processing. Here, an instruction may be issued to prompt the CPU  11  to execute refresh processing at a predetermined timing instead of the above processing. 
         [0113]      FIGS. 11 and 12  are flowcharts of refresh processing. First, data of the NAND flash array  225  (for example, data of the data structure illustrated in  FIG. 7  or  8 ) is read with the main sense amplifier  2283  (step S 11 ). 
         [0114]    Subsequently, an ECC is generated from read data (step S 12 ). Next, it is determined whether an ECC error occurs (step S 13 ). If any ECC error occurs (Yes in step S 13 ), a read error signal is sent to the PCU  11  (step S 14 ). At this point, the processing is terminated. 
         [0115]    On the other hand, if no error occurs (No in step S 13 ), data of the NAND flash array  225  is read using the sub sense amplifier  2284  (step S 15 ). 
         [0116]    Next, an ECC is generated from the read data (step S 16 ). Subsequently, it is determined whether an ECC error occurs (step S 17 ). If no ECC error occurs (No in step S 17 ), (since it is determined that a voltage margin for the floating gate is secured enough), the processing is terminated. 
         [0117]    If an ECC error occurs (Yes in step S 17 ), (since it is determined that a margin is insufficient), data in the NAND flash array  225  is read again using the main sense amplifier  2283  (step S 18 ). 
         [0118]    Then, an ECC is generated from the read data (step S 19 ). Next, it is determined whether an ECC error occurs (step S 20 ). If an ECC error occurs (Yes in step S 20 ), the processing shifts to step S 14 , and a read error signal is sent to the CPU  11  (step S 14 ). At this point, the processing is terminated. 
         [0119]    If no ECC error occurs (No in step S 20 ), data read with the main sense amplifier  2283  is written to a block at the target address of the NAND flash array  225  again (step S 21 ). 
         [0120]    Next, a value of “DWF” in the status register  30  of the NAND flash array  225  is read (step S 22 ). Then, it is determined whether a write error occurs (step S 23 ). 
         [0121]    If no write error occurs (No in step S 23 ), the processing is terminated. If a write error occurs (Yes in step S 23 ), a write error signal is sent to the CPU  11  (step S 24 ). At this point, the processing is terminated. 
         [0122]    That is the end for the description about the refresh processing. In this embodiment, the processing in step S 3  follows the processing in step S 2 . However, the processing in step S 2  follows the processing in step S 3 . 
         [0123]      FIG. 13  illustrates an effect of the refresh processing. The horizontal axis in a graph in  FIG. 13  represents an elapsed time or the number of read/write cycles, and the vertical axis represents a voltage value of the floating gate. 
         [0124]    In  FIG. 13 , “refresh processing” represents a timing of determination as to whether to rewrite data. If a voltage level of the floating gate is 2 V or more, a sufficient margin is secured, and data is not rewritten. 
         [0125]    On the other hand, if a voltage level of the floating gate is 2 V or less, a margin is insufficient. Thus, data is held through the rewrite operation. In this way, if a voltage value of the floating gate is between the voltage of 1 V applied by the main reference cell  2281  and the voltage of 2V applied by the sub reference cell  2282 , refresh processing is performed to rewrite data, making it possible to rewrite data when a voltage margin of the floating gate is secured enough. 
         [0126]    Here, a voltage value of the sub reference cell  2282  is preferably set closer to a voltage value of the main reference cell  2281  than a value of write voltage although not particularly limited. If the voltage value is set in this way, the number of rewrite operations may be reduced, and the life of the nonvolatile memory  22  may be elongated. 
         [0127]    As described above, according to the module  10 , even if data storage performance of the NAND flash array  225  is lowered due to deterioration of an insulating film, data may be kept by rewriting data through refresh processing. 
         [0128]    Further, at the first byte of the sector A, such byte as keeps a write state all the time is set and used for measuring a margin. As a result, a margin may be measured with high accuracy. Thus, a reliability of data may be enhanced. 
         [0129]    Needless to say, the structure of this embodiment may be easily applied to any nonvolatile memory equipped with plural sense amplifiers. Here, information representing that refresh processing is being executed may be displayed on the display  15 . 
         [0130]      FIG. 14  is a flowchart of processing for displaying information representing that refresh processing is being executed on a display. The CPU  11  references “REFR” of the status register  30  of the NAND controller  21  (step S 31 ). 
         [0131]    Then, it is determined whether “1” is set in “REFR” (step S 32 ). If “0” is set in “REFR” (no in step S 32 ), the processing is terminated. On the other hand, “1” is set in “REFR” (Yes in step S 32 ), it is determined that refresh processing is being executed. Thus, the notification is sent to the CPU  11 . The CPU  11  displays a message that refresh processing is being performed on the display  15  (step S 33 ). At this point, the processing is terminated. 
         [0132]    With this message, a user may easily determine whether refresh processing is being executed. Further, a screen for prompting a user to replace the nonvolatile memory  22  may be displayed on the display  15 . 
         [0133]      FIG. 15  is a flowchart of processing performed at the time of displaying a screen for prompting a user to replace the nonvolatile memory. The CPU  11  references a value “C” of a refresh counter of the nonvolatile memory  22  (step S 41 ). 
         [0134]    Then, the value “C” of the refresh counter is compared with a preset value “M” (for example, M=100) to determine whether the value “C” is larger than the value “M” (step S 42 ). If the value “C” is smaller than the value “M” (No in step S 42 ), the processing is terminated. 
         [0135]    On the other hand, if the value “C” is larger than the value “M” (Yes in step S 42 ), it is determined that the nonvolatile memory  22  needs to be replaced, and the notification is sent to the CPU  11 . The CPU  11  displays a message that the nonvolatile memory  22  needs to be replaced on the display  15  (step S 43 ). At this point, the processing is terminated. 
         [0136]    With this message, a user may easily know the time for replacement of the nonvolatile memory  22 . Next, a system according to a second embodiment is described. 
         [0137]    The following description is focused on a difference between the system of the second embodiment and the foregoing first embodiment, and similar components are not described. The system of the second embodiment is the same as the first embodiment except for the configuration of the sense amplifier circuit  228  of the first embodiment. 
         [0138]      FIG. 16  is a block diagram illustrating the configuration of the sense amplifier circuit of the second embodiment. A sense amplifier circuit  228   a  is not provided with the logic circuit  2285 . Instead, the “/SES” signal for specifying a sense amplifier for outputting the signal Data- 0  is directly input to the main sense amplifier  2283  and the sub sense amplifier  2286 . 
         [0139]    Further, the sub sense amplifier  2286  is provided with an inversion input terminal to which the “/SES” signal is input with the logic being inverted. Thus, a signal having the logic of “1” is input to one amplifier, and a signal having the logic of “0” is input to the other amplifier. As a result, the signal of the selected one of the sense amplifiers is output as Data- 0 . 
         [0140]    According to the system of the second embodiment, the same effect as the system of the first embodiment is obtained. Next, a system according to a third embodiment is described. 
         [0141]    The following description is focused on a difference between the system of the third embodiment and the foregoing first embodiment, and similar components are not described. The system of the second embodiment is the same as the first embodiment except for the configuration of a nonvolatile memory. 
         [0142]      FIG. 17  is a block diagram illustrating a nonvolatile memory of the third embodiment. The control unit  223  of a nonvolatile memory  22   a  of the third embodiment reads data of a block at an externally designated address (hereinafter referred to as “rewrite address”) and stores the data in the I/O buffer circuit  221 . The control unit  223  includes a rewrite circuit (Rewrite Circuit)  223   b  for rewriting data stored in the I/O buffer circuit  221  in the block at the address after erasing the data of the bock at the address. 
         [0143]      FIG. 18  illustrates a command function of the nonvolatile memory of the third embodiment. In a command function table  40   a , a command (rewrite command) for rewriting data to a block at a rewrite address (Rewrite to Current block) is added. 
         [0144]    An operation of rewriting data to the block at the rewrite address is performed by sending a command code “50h” at the first cycle and sending a command code “10h” at the second cycle. 
         [0145]    Next, refresh processing of the third embodiment is described.  FIG. 19  is a flowchart of the refresh processing of the third embodiment. The following description is focused on a difference from the refresh processing of the first embodiment. 
         [0146]    If an ECC error occurs (Yes in step S 17 ), (since it is determined that a margin is insufficient), a rewrite command is sent to the nonvolatile memory  22 . As a result, the rewrite circuit  223   b  of the nonvolatile memory  22  performs the rewrite processing (step S 18   a ). 
         [0147]    After that, the processing shifts to step S 22 , and step S 22  and subsequent steps are performed. Next, rewrite processing in step S 18   a  is described.  FIG. 20  is a flowchart of the rewrite processing. 
         [0148]    First, the command register  222  accepts a refresh command ( 81   h ) issued at the first cycle from the NAND controller  21  (step S 51 ). Next, the address register  224  accepts a rewrite address from the NAND controller  21  (step S 52 ). 
         [0149]    Next, the command register  222  accepts a refresh command ( 10   h ) issued at the first cycle from the NAND controller  21  (step S 53 ). Next, data is read to the I/O buffer circuit  221  from the NAND flash array  225  (step S 54 ). 
         [0150]    Subsequently, data of a block at the address is erased while the data is held in the I/O buffer circuit  221  (step S 55 ). Next, it is determined whether an erase error occurs (step S 56 ). 
         [0151]    If the erase error occurs (Yes in step S 56 ), a flag indicating the occurrence of the error is set in “DWF” of the status register  30  (step S 57 ). At this point, the processing is terminated. 
         [0152]    On the other hand, if no erase error occurs (No in step S 56 ), data stored in the I/O buffer circuit  221  is written to a block at the rewrite address (step S 58 ). 
         [0153]    Next, it is determined whether a write error occurs (step S 59 ). If a write error occurs (Yes in step S 59 ), the processing shifts to step S 57 , and step S 57  and subsequent steps are performed. 
         [0154]    If no write error occurs (No in step S 59 ), the processing is terminated. In this embodiment, the processing in step S 53  follows the processing in step S 52 . However, the processing in step S 52  follows the processing in step S 53 . 
         [0155]    According to the system of the third embodiment, the same effect as the system of the first embodiment is obtained. Next, a system according to a fourth embodiment is described. 
         [0156]    The following description is focused on a difference between the system of the fourth embodiment and the foregoing third embodiment, and similar components are not described. The system of the fourth embodiment is the same as the third embodiment except for the configuration of the nonvolatile memory. 
         [0157]      FIG. 21  is a block diagram of a nonvolatile memory of the fourth embodiment. The nonvolatile memory  22   b  reads data of a block at a rewrite address and stores the data in the I/O buffer circuit  221 . The nonvolatile memory  22   b  includes a replace register (Replace Register)  229  for rewriting data of a block at an address (hereinafter referred to as “replacement address”) different from the externally designated address independently of the I/O buffer circuit  221 . 
         [0158]      FIG. 22  illustrates a command function of the nonvolatile memory of the fourth embodiment. In a command function table  40   b , a command to rewrite data to a block at the replacement address (Rewrite to Replacement Block) (replace command) is added. 
         [0159]    An operation of rewriting data to the block at the replacement address is performed by sending a command code “83h” at the first cycle and sending a command code “10h” at the second cycle. 
         [0160]    Next, refresh processing of the fourth embodiment is described. The refresh processing of the fourth embodiment differs from the third embodiment in step S 18   a  in  FIG. 19 . 
         [0161]    The rewrite processing of the fourth embodiment is described below.  FIG. 23  is a flowchart illustrating the rewrite processing of the fourth embodiment. First, the command register  222  accepts a replace command ( 83   h ) issued at the first cycle from the NAND controller  21  (step S 61 ). 
         [0162]    Next, the address register  224  accepts a rewrite address from the NAND controller  21  (step S 62 ). Next, the replace register  229  accepts a replacement address from the NAND controller  21  (step S 63 ). 
         [0163]    Subsequently, the command register  222  accepts a replace command ( 10   h ) issued at the second cycle from the NAND controller  21  (step S 64 ). Next, data is read to the I/O buffer circuit  221  from the block at the designated rewrite address in the NAND flash array  225  and stores the data in the I/O buffer circuit  221  (step S 65 ). 
         [0164]    Next, the control unit  223  switches the address to the replacement address and writes the data stored in the I/O buffer circuit  221  to the block at the replacement address (step S 66 ). 
         [0165]    Next, it is determined whether a write error occurs (step S 67 ). If a write error occurs (Yes in step S 67 ), a flag indicating the occurrence of the error is set in “DWF” of the status register  30  (step S 68 ). After that, the processing is terminated. 
         [0166]    On the other hand, if no write error occurs (No in step S 67 ), data in the block at the rewrite address is erased (step S 69 ). Next, it is determined whether an erase error occurs (step S 70 ). 
         [0167]    If the erase error occurs (Yes in step S 70 ), the processing shifts to step S 68 , and step S 68  and subsequent steps have been performed. On the other hand, if no erase error occurs (No in step S 70 ), a mapping table describing a relationship between a logical address and a physical address is updated in accordance with an instruction from the NAND controller  21  (step S 71 ). At this point, the processing is terminated. 
         [0168]    The processing for updating the mapping table with the NAND controller  21  is described below.  FIG. 24  is a flowchart illustrating the processing for updating the mapping table. 
         [0169]    First, a replace command is sent to the nonvolatile memory  22  to read bit data of the first sense amplifier  30  (step S 81 ). Next, it is determined whether a write error occurs (step S 82 ). 
         [0170]    If a write error occurs (Yes in step S 82 ), the write error is sent to the CPU  11  (step S 83 ). At this point, the processing is terminated. If no write error occurs (No in step S 82 ), the mapping table is updated (step S 84 ). To be specific, the physical address corresponding to the logical address is replaced to the replace address from the address at which the data was read. At this point, the processing is terminated. 
         [0171]    According to the system of the fourth embodiment, the same effects as the system of the third embodiment are obtained. Moreover, since the nonvolatile memory  22  rapidly degrades if data is written to and erased from the block at the same address, it is preferred to uniformly perform rewrite to all addresses. 
         [0172]    According to the system of the fourth embodiment, the number of rewrite operations may be averaged by rewriting data to a block at an address different from the address from which data was read. As a result, the life of the nonvolatile memory  22  is elongated, and a reliability of data may be further enhanced. 
         [0173]    Next, a system according to a fifth embodiment is described. The following description is focused on a difference between the system of the fifth embodiment and the foregoing first embodiment, and similar components are not described. 
         [0174]    The system of the fifth embodiment is the same as the first embodiment except for the configuration of a NAND controller.  FIG. 25  is a block diagram illustrating the configuration of a NAND controller of the fifth embodiment. 
         [0175]    A NAND controller  21   a  includes a refresh interval register (Refresh Interval Register)  217  with a threshold value for determining whether a target value exceeds a predetermined number of times, which may be set by the CPU  11 . 
         [0176]    Further, the NAND controller  21   a  writes the number of times data is read from, erased from, or written to a predetermined position (as described below) of a nonvolatile memory as information about the number of accesses. 
         [0177]    Then, the NAND controller  21   a  performs refresh processing if the information about the number of accesses read from the nonvolatile memory  22  exceeds a numerical value set in a refresh interval register  217 . 
         [0178]      FIG. 26  illustrates an example of information about the preset number of accesses. An access counter (AC: Access counter) to which the number of accesses is to be written is set in the 15 th  byte and 16 th  byte of the spares a, b, c, and d. In  FIG. 21 , a preset example of the spare a is illustrated by way of example. 
         [0179]    Next, processing for determining whether to execute refresh processing of the fifth embodiment is described.  FIG. 27  is a flowchart of the processing for determining whether to execute refresh processing of the fifth embodiment. 
         [0180]    First, an access counter of the NAND flash array  225  is referenced, and the information about the number of accesses is read (step S 91 ). Next, a value “A” indicating the number of accesses and a preset value “N” (for example, N=1000) are compared to determine whether the value “A” indicating the number of accesses is larger than the value “N” (step S 92 ). 
         [0181]    If the value “A” is smaller than the value “N” (No in step S 92 ), the processing is terminated. On the other hand, if the value “A” is larger than the value “N” (Yes in step S 92 ), “1” is set to “REFR” of the status register  30  (step S 93 ). 
         [0182]    Next, the refresh processing is performed (step S 94 ). This refresh processing is similar to that illustrated in  FIG. 11 . After the completion of the refresh processing, “0” is set to “REFR” of the status register  30  (step S 95 ). 
         [0183]    At this point, the processing is terminated. That is the end for the description about the processing for determining whether to execute refresh processing. According to the system of the fifth embodiment, the same effects as the first embodiment may be obtained. 
         [0184]    According to the system of the fifth embodiment, the refresh processing is performed based on the number of actual accesses. Thus, a reliability of data may be further enhanced. Next, a system according to a sixth embodiment is described. 
         [0185]    The following description is focused on a difference between the system of the sixth embodiment and the foregoing fifth embodiment, and similar components are not described. The system of the sixth embodiment is the same as the fifth embodiment except for the function of the CPU  11 . 
         [0186]    The CPU  11  of the sixth embodiment reads a counter value of a refresh counter from the nonvolatile memory  22 . If the read value is larger than a predetermined value, the CPU changes a value of the refresh interval register  217  in the NAND controller  21   a.    
         [0187]      FIG. 28  is a flowchart illustrating the refresh interval change processing. First, the refresh counter of the NAND flash array  225  is referenced to read a counter value (step S 101 ). 
         [0188]    Next, a counter value “Co” of the refresh counter is compared with a preset value “P” (for example, P=10) to determine whether the counter value “Co” is larger than the value “P” (step S 102 ). 
         [0189]    If the counter value “Co” is smaller than the value “P” (No in step S 102 ), the processing is terminated. On the other hand, if the counter value “Co” is larger than the value “P” (Yes in step S 102 ), a value “I” of the refresh interval register  217  of the NAND controller  21  is read (step S 103 ). 
         [0190]    Next, the refresh interval is changed (step S 104 ). To be specific, for example, “X=0.5” is set to thereby reduce by half the value “I”. Next, the register value changed in step S 104  is written to the refresh interval register  217  (step S 1015 ). At this point, the processing is terminated. 
         [0191]      FIG. 29  illustrates effects of the refresh interval change processing. As a result of the refresh interval change processing, a refresh processing interval set to two or three processings and three or four processings is reduced by half to one or two processings. 
         [0192]    According to the system of the sixth embodiment, the same effects as the system of the fifth embodiment may be obtained. In addition, according to the system of the sixth embodiment, even if the number of write operations increases and a data storage period is reduced due to deterioration of an insulating film, a reliability of data may be further enhanced by reducing an interval of refresh processing. 
         [0193]    Next, a system according to a seventh embodiment is described. The following description is focused on a difference between the system of the seventh embodiment and the foregoing first embodiment, and similar components are not described. 
         [0194]    The system of the seventh embodiment is the same as the first embodiment except for the configuration of a NAND controller.  FIG. 30  is a block diagram illustrating the configuration of a NAND controller of the seventh embodiment. 
         [0195]    The NAND controller  21   b  further includes an I2C interface unit (I2C Interface Unit)  218  for obtaining current date and time information from a real time clock IC (not illustrated) in the module  10 . 
         [0196]    The NAND interface unit  216  sets the current date and time information obtained with the I2C interface unit  218  in a predetermined area of the nonvolatile memory  22 .  FIG. 31  illustrates the current date and time information set in the nonvolatile memory. 
         [0197]    An LRD (Latest Refresh Date) indicating the date and time of the last refresh processing is set in the 15 th  bit and 16 th  bit of the spares a, b, c, and d. In  FIG. 31 , the set example of the spare a is illustrated by way of example. 
         [0198]    Next, the processing for determining whether to execute refresh processing of the seventh embodiment is described.  FIG. 32  is a flowchart illustrating the processing for determining whether to execute refresh processing of the seventh embodiment. 
         [0199]    First, the I2C interface unit  218  reads current date and time information “Cu” from the real time clock IC (step S 111 ). Next, the date and time information “L” stored in the LRD is read (step S 112 ). 
         [0200]    Then, a value “Cu−L” obtained by subtracting the date and time information “L” from the current date and time information “Cu” is compared with a preset value “Q” (for example, Q=7 days) to determine whether the value “Cu−L” is larger than the value “Q” (step S 113 ). 
         [0201]    If the value “Cu−L” is smaller than the value “Q” (No in step S 113 ), the processing is terminated. On the other hand, if the value “Cu−L” is larger than the value “Q” (Yes in step S 113 ), “1” is set to “REFR” of the status register  30  (step S 114 ). 
         [0202]    Next, refresh processing is performed (step S 115 ). The steps of the refresh processing are the same as the refresh processing in  FIG. 11 . After the completion of the refresh processing, “0” is set to “REFR” of the status register  30  (step S 116 ). 
         [0203]    At this point, the processing is terminated. That is the end for the description about the processing for determining whether to execute refresh processing. According to the system of the seventh embodiment, the same effects as the system of the first embodiment may be obtained. 
         [0204]    In addition, according to the system of the seventh embodiment, it is possible to certainly prevent such a situation that a potential level is lowered and the logic is inverted over time even if no data access is made. Hence, a reliability may be further enhanced. 
         [0205]    The nonvolatile memory, the memory control unit, the memory control system, the nonvolatile memory control method of the present invention are described above by way of the illustrated embodiments. However, the present invention is not limited thereto. The structure of each component may be replaced with any structure having the same function. Further, any other structure or step may be added to the present invention. 
         [0206]    Further, the present invention is applicable to a combination of any two or more constructions (features) in the above embodiments. Further, although the above embodiments are described based on the computer system, the present invention is applicable to a cell phone or an information processing unit such as a PDA. 
         [0207]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the embodiment. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.