Abstract:
A simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit includes a diode-connected transistor, a cascode-connected transistor, as well as first and second resistors coupled between ground and a ramped power supply voltage. The diode-connected transistor exhibits a negative temperature coefficient. The on resistance of the cascode-connected transistor increases with temperature and thus the voltage dropped across the cascode-connected transistor also increases with temperature. By correctly sizing the cascode-connected device, the negative and positive temperature coefficients of the diode-connected and cascode-connected devices can be substantially cancelled out.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     Voltage detection circuits, and particularly CMOS voltage detection circuits, that have the ability to provide an output signal once an input voltage has passed a certain voltage threshold are known in the art. Voltage detection circuits are important building blocks used in the design of many types of analog and mixed analog/digital integrated circuits. Current comparators are widely used, for example, in POR (“Power On Reset”) circuits.  
         [0002]     A POR circuit typically detects when the supply voltage for an integrated circuit reaches a predetermined acceptable level, and sends an output signal to reset internal memory elements on the integrated circuit. Voltage detection circuits, which compare the supply voltage against a known reference voltage, are often included in POR circuits to determine when a safe operating voltage is reached. The difficulty in designing POR circuits is threefold: first, the reference voltage must be generated from the same supply voltage that is ramped up to a final supply voltage; second, the reference voltage must not vary excessively over process, voltage and temperature (“PVT”) conditions, or else the POR circuit sends out a signal prematurely, or not at all; and third, in the case of low voltage processes, the reference voltage used must be small (in the one volt range).  
         [0003]     Typically, diode clamp and band-gap circuits have been used to generate a low voltage reference. However, because the voltage across a diode is very sensitive to temperature, diode clamp circuits cannot meet the strict voltage detection tolerances needed in some applications. Additionally, bandgap circuit, which provide a temperature-insensitive output voltage, usually contain too many components to be cost-effective when used in an integrated circuit application.  
         [0004]     Referring now to  FIG. 1 , a typical diode clamp voltage detect circuit  10  is shown for generating an output voltage as the VDD voltage supply ramps up to a final supply voltage level. The VOUT voltage in detect circuit  10  tracks the VDD voltage, but at a lower voltage level determined by the ratio of the value of resistors R 1  and R 2 , as well as the voltage drop across diode-connected transistor P 1 . Circuit  10  is not a good candidate for use in a POR circuit due to the temperature sensitivity of drain-to-source voltage drop across transistor P 1 .  
         [0005]     Referring now to  FIG. 2 , another typical diode clamp voltage detect circuit  20  is shown for generating an output voltage as the VDD voltage supply ramps up to a final supply voltage level. The VOUT voltage in detect circuit  10  initially tracks the VDD voltage, but quickly levels out to a reference voltage level determined by the ratio of the value of resistors R 1  and R 2 , as well as the voltage drop across diode-connected transistor N 1 . Circuit  20  is also not a good candidate for use in a POR circuit due to the temperature sensitivity of drain-to-source voltage drop across transistor N 1 .  
         [0006]     Referring now to  FIG. 3 , a bandgap circuit is shown for generating an output voltage as the VDD voltage supply ramps up to a final supply voltage level. The VOUT voltage in detect circuit  30  also initially tracks the VDD voltage, but quickly levels out to a reference voltage level determined a bandgap circuit including a first transistor in parallel with the combination of a second transistor in series with a resistor, as well as a feedback circuit (not shown in  FIG. 3 ). While circuit  30  is a good candidate for use in a POR circuit from a performance standpoint, it is not a good candidate for low voltage operation (bandgap of silicon, which is typically used is 1.1 volts) or from a cost standpoint due to the number of devices that must be used in the circuit.  
         [0007]     What is desired, therefore, is a voltage detection circuit for providing a temperature-insensitive output voltage, but is realized with a design that can be economically implemented in an integrated circuit.  
       SUMMARY OF THE INVENTION  
       [0008]     According to the present invention, a simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit of the present invention includes a diode-connected transistor, a cascode-connected transistor, as well as first and second resistors coupled between ground and a ramped power supply voltage. The output voltage of the detection circuit is provided at the junction of the first and second resistors. The diode-connected transistor exhibits a negative temperature coefficient, i.e. the hotter the device becomes, the lower the NMOS threshold voltage becomes. However, the cascode-connected transistor is also placed in series with the diode-connected transistor. The on resistance of the cascode-connected transistor increases with temperature and thus the voltage dropped across the cascode-connected transistor also increases with temperature. By varying the size of the cascode device, the overall resistance of the device is varied, and thus the net change in voltage drop for high and lower temperature can be varied. Therefore, if the cascode-connected device is correctly sized, the negative and positive temperature coefficients of the diode-connected and cascode-connected devices can be substantially cancelled out. A graphical analysis can be used to properly select devices sizes for optimum operation. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:  
         [0010]      FIG. 1  is schematic diagram of prior art reference voltage circuit for use in a detection circuit using a P-channel transistor and a resistor divider that has temperature-sensitive output voltage;  
         [0011]      FIG. 2  is schematic diagram of prior art reference voltage circuit for use in a voltage detection circuit using an N-channel transistor and a resistor divider that also has temperature-sensitive output voltage;  
         [0012]      FIG. 3  is a schematic diagram of a prior art bandgap reference voltage circuit for use in a voltage detection circuit;  
         [0013]      FIG. 4  is a schematic diagram of a reference voltage circuit according to the present invention for use in a voltage detection that has a substantially temperature-insensitive output voltage;  
         [0014]      FIG. 5  is a plot of reference voltage versus ramped Vdd voltage in the voltage detection circuit of the present invention shown in  FIG. 4  using a first trace determined by a first set of process conditions, and a second trace determined by a second set of process conditions;  
         [0015]      FIG. 6  is a schematic diagram of a POR circuit using a reference circuit according to the present invention; and  
         [0016]      FIG. 7  is a plot of two voltages taken from the POR circuit of  FIG. 6  showing little change in the output reference voltage at first and second operating temperatures, and first and second process conditions. 
     
    
     DETAILED DESCRIPTION  
       [0017]     Referring now to  FIG. 4 , a schematic diagram of a reference circuit  40  used in a voltage detection circuit  40  according to the present invention that has a substantially temperature-insensitive output voltage is shown. Voltage detection circuit includes resistors R 1  and R 2 , and transistors N 1  and N 2 . Resistors R 1  and R 2 , and the current paths of transistors N 1  and N 2  are serially coupled, and in turn coupled between VDD and ground. Transistor N 1  is diode-connected, and transistor N 2  is cascode-connected. In other words, the gate of transistor N 1  is coupled to the drain of transistor N 1 , and the gate of transistor N 2  is coupled to VDD. The VDD power supply ramps up to a final value such as 3.3 volts, or the like. The ground connection could also be a negative VSS supply. In  FIG. 4 , the value of resistor R 1  is 10K ohms, and the value of resistor R 2  is 1K ohms, but of course the values can be changed as required for a given application. The sizes of transistors N 1  and N 2  can be determined as set forth below.  
         [0018]     In operation, the VOUT voltage is taken at the junction between resistor R 1  and R 2 , and has a final voltage of about 0.8 volts. The function of detection circuit  40  is to provide a temperature invariant detection voltage VOUT. This is accomplished by the relative sizing of transistors N 1  and N 2  so that the positive and negative temperature coefficients are effectively cancelled for the given detection voltage.  
         [0019]     The manner of sizing transistors N 1  and N 2  is as follows. In a first analytical method of sizing the transistors, an expression is created for VOUT (can also be referred to as VREF) in terms of the lengths (L) and widths (W) of transistors N 1  and N 2 .  
             Vref   =         I   D     ⁢     R   2       +     V     DS   1       +       I   D     ⁢     r     ds   2                   [   1   ]               Vref   =     Vdd   -       I   D     ⁢     R   1                 [   2   ]                 V     DS   1       =       V   T     +           L   1       W   1         ⁢         I   D           2         K                   [   3   ]                 r     ds   2       =     1     K   ⁢     W   L     ⁢     (     Vdd   -     V   T       )                 [   4   ]                   V   T     =       V   TO     +     T   ⁡     (       ∂       V   T     ⁡     (   T   )           ∂   T       )           ⁢     
     ⁢     where   ⁢           ⁢     (       ∂       V   T     ⁡     (   T   )           ∂   T       )               [   5   ]             
 
 is process dependent 
 
         [0020]     Next, arbitrary values for L 1 , W 1 , L 2 , R 1 , and R 2  are selected. These values can be set to meet other design goals such as static current in the reference leg, and area requirements. Note that R 2 &lt;&lt;R 1 . Next, obtain VT0+T[∂VT(T)/∂T] from design rules. Then, select the desired VOUT and targeted VDD and determine I D  from equation [2]. Then, using equations [3] and [5], determine ΔV DS1  at the extremes of the temperature range for the circuit. Finally, using equation [4] and ΔV DS1 , create the equation: 
 
Δ V   DS1   =ID[rds HOT− rds COLD], 
 
 and solve for W 2 . 
 
         [0021]     In a second method, the sizing of transistors N 1  and N 2  can be determined numerically. In many circuit simulators (such as HSPICE) there are numerical equation solving utilities. They are typically of the following form: 
    parameter definition: .param w=opt1 (seed, low, high, step)     model definition: .model optmod opt1 cendif=1 . . .     simulation definition: .dc sweep optimize=op1  
       measure   ⁢           ⁢     goal   :             +   model     ⁢           ⁢     optmod   ·                   meas   ⁢           ⁢   dc   ⁢           ⁢   w   ⁢           ⁢   find   ⁢           ⁢   VDD     +                 when   ⁢           ⁢   VREF   ⁢           ⁢   1     =       VREF   ⁢           ⁢   2     +                   goal   =   VDDtarget     ⁢                         
   
 
         [0025]     A numerical solver of the above form can be configured to calculate the widths and lengths for two circuits simultaneously running at two different temperature extremes, thus determining the transistor sizes needed to make the reference (VOUT) voltage substantially insensitive to temperature.  
         [0026]     Referring now to  FIG. 5 , a targeted reference voltage is required when VDD=1.2 volts. The value of the targeted reference voltage is 0.85 volts. It can be seen that the reference is substantially insensitive to temperatures ranging from −55° C. to 125° C. at the targeted reference voltage, because the curves from the −55° C. simulation and the 125° C. simulation intersect at the target reference voltage point.  
         [0027]     Referring now to  FIG. 6 , a POR circuit  60  is shown using the reference generator of the present invention. The reference of the POR circuit  60  includes resistors R 5  and R 6 , diode-connected transistor N 2  and cascode-connected transistor N 3  as previously described. In addition, the POR circuit  60  uses a voltage that is proportional to the VDD, which includes resistors R 1  and R 2 , diode-connected transistor N 1 , resistors R 3  and R 4 , and transistor P 1 . The temperature-stabilized reference voltage and the voltage proportional to VDD are compared by comparator  62  and an output voltage VOUT is provided when the VDD voltage passes a predetermined threshold.  
         [0028]     Referring to  FIG. 7 , a resistor divider is added to the temperature insensitive reference to demonstrate how the reference can be used to detect the point at which VDD reaches a targeted value.  
         [0029]     While there have been described above the principles of the present invention in conjunction with specific memory architectures and methods of operation, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.