Abstract:
An active centerpoint bus balancing system which actively maintains centerpoint voltage balance of the output capacitors in a power supply having a multi-level voltage output. The centerpoint voltage balance is maintained by a novel control circuit which efficiently transfers charge from one capacitor to the other capacitor so as to maintain the same voltage on each output capacitor. The centerpoint voltage balance minimizes the effect of loading conditions. It operates even with no load, and allows severe load unbalance on the two output capacitors without creating voltage unbalance.

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application claims one or more inventions which were disclosed in Provisional Application No. 61/175,110, filed May 4, 2009, entitled “ACTIVE CENTERPOINT POWER BUS BALANCING SYSTEM”. The benefit under 35 USC §119(e) of the United States provisional application is hereby claimed, and the aforementioned application is hereby incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention pertains to the field of active rectifiers. More particularly, the invention pertains to an active rectifier with an active centerpoint power bus balancing system. 
     2. Description of Related Art 
     Many types of three phase AC to DC active rectifiers are in use today. These systems convert three phase AC inputs to a DC output, while controlling the input current waveforms so as to maintain a high power factor, which reduces the cost of electrical power. 
     Some of the most efficient (most cost effective) active rectifiers utilize a three voltage level output. The output is split between two series connected capacitors. This capacitor centerpoint is needed as a return for power semiconductors, and its voltage must be kept centered between the two capacitors in order for efficient system operation, as well as to maintain low voltage stress on the power semiconductors. 
     A number of control schemes exist for maintaining centerpoint balance, but all have their limitations. Most will not work well under lightly loaded conditions, and will not maintain voltage balance when one capacitor load is much higher than the other capacitor load. 
     Every active rectifier system contains a housekeeping power supply, which is used to operate its control and power circuits. 
     SUMMARY OF THE INVENTION 
     An active centerpoint bus balancing system is provided which actively maintains centerpoint voltage balance of the output capacitors in a power supply having a multi-level voltage output. 
     The centerpoint voltage balance is maintained by a novel control circuit which efficiently transfers charge from one capacitor to the other capacitor so as to maintain the same voltage on each output capacitor. 
     The centerpoint voltage balance minimizes the effect of loading conditions. It operates even with no load, and allows severe load unbalance on the two output capacitors without creating voltage unbalance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         FIG. 1  shows a circuit diagram of a system according to the teachings of the present invention. 
         FIGS. 2   a - 2   c  show graphs of the triangle wave, comparator thresholds and drive voltages over time for different relationships of the upper capacitor voltage vs. the lower capacitor voltage. 
         FIG. 3  shows a circuit diagram of an alternative use as a standalone DC/DC converter in box  10  of  FIG. 1 , for use when Vpos is higher than Vcp. 
         FIG. 4  shows a circuit diagram of an alternative use as a standalone DC/DC converter in box  10  of  FIG. 1 , for use when Vpos is higher or lower than Vcp. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The disclosed invention modifies the housekeeping power supply in an active rectifier system, so that in addition to operating the Rectifier System control and power circuits, it also actively maintains centerpoint voltage balance of the output capacitors. 
     The housekeeping supply described in this invention can also be used as a standalone DC to DC converter which will transfer charge between two capacitive sources, not necessarily in series, so as to maintain any voltage ratio between the two capacitors. Power will be transferred dynamically from one source to the other, maintaining proper voltage balance. 
     A basic circuit diagram according to the teachings of the invention is shown in  FIG. 1 . It will be understood by one skilled in the art that the circuit diagram in the figure is intended to illustrate the novel features of the invention, and conventional features have been omitted for clarity. 
     Referring to that diagram, Capacitors C 1  and C 2  form the series connection output of a three level active rectifier  15 , fed by an AC source. These outputs are a first output Vpos, a centerpoint output Vcp, and a second output Vneg. The Vneg output may also be the ground reference. The active rectifier  15  itself does not form part of the invention, and can be of a design known to one skilled in the art. 
     The circuit of  FIG. 1  continually adjusts the centerpoint voltage Vcp so it is centered between Vpos and Vneg. 
     If the voltage on capacitor C 1  is higher than the voltage on capacitor C 2 , the control circuit, which is described below, causes a pulse width modulated output, A, from upper PWM comparator U 1  to pulse width modulate the signal input of the high side switch, Q 1 , which causes a current flow between the first terminal and the second terminal of Q 1 , from capacitor C 1  into inductor L 1 . A driver may be provided, as shown, to provide the proper levels to drive a switching input of first switch Q 1  from output A. Charge is thus removed from C 1  when Q 1  is on, lowering the voltage across C 1 . When Q 1  shuts off, the current built up in inductor L 1  charges capacitor C 2  through diode D 2 , depositing a charge into capacitor C 2 , raising the voltage on C 2 . 
     If the voltage on capacitor C 2  is higher than the voltage on capacitor C 1 , the control circuit, which is described below, causes a pulse width modulated output B, from the lower pulse-width modulated (PWM) comparator U 2  to pulse width modulate the switching input of the low side switch, Q 2 , which causes a current flow between the first terminal and the second terminal of Q 2 , from capacitor C 2  into inductor L 1 . As above, a driver may be provided, as shown, to provide the proper levels to drive second switch Q 2  from output B. Charge is thus removed from C 2  when Q 2  is on, lowering the voltage across C 2 . When Q 2  shuts off, the current built up in inductor L 1  charges capacitor C 1  through diode D 1 , depositing a charge into capacitor C 1 , raising the voltage on C 1 . 
     Current sense transformer CS 1  measures the current flowing through Q 1  and current sense transformer CS 2  measures the current flowing through Q 2 . These are used for control purposes, as will be described below. 
     The voltage across L 1  is equal to the voltage on C 1  when Q 1  is on, and equal to the voltage on C 2  when Q 2  is on. As shown at “Housekeeping Outputs” in  FIG. 1 , secondary windings of L 1  can be rectified in order to generate regulated DC voltages which can be used for housekeeping purposes, and to operate these control circuits. The output Vbias is referenced to Vneg and is used to operate these circuits. The output Vhouse and RTN is shown as a general purpose housekeeping output, which can be referenced to any voltage, and can be used to operate active rectifier circuits. It will be recognized that additional housekeeping outputs can also be provided using additional windings on L 1 . 
     A reference generator circuit U 3  is used to generate a voltage Vref from Vbias. Vref is approximately half of Vbias. This voltage is used for some of the control functions. 
     U 4  is a difference amp which translates the voltage across C 1  to a ground referenced voltage so that it can be compared to the voltage across C 2 , which is already ground referenced. 
     U 5  is the voltage error amp which compares the translated C 1  voltage from U 4  to the voltage Vcp from C 2 . The output of U 5  adjusts until it allows just the right amount of current to flow in CS 1  or CS 2  so that the voltage on C 1  equals the voltage on C 2 . 
     U 6  is the current error amp. Its output adjusts so as to maintain a balance between the sensed current CS 1  or CS 2 , and output of the voltage error amp U 5 . 
     Output of the current error amp U 6  drives two voltage regulator diodes VR 1  and VR 2 . These regulator diodes present a threshold to one leg of the upper PWM comparator, U 1 , and one leg of the lower PWM comparator, U 2 . 
     The other comparator leg of U 1  and U 2  is fed by a triangle waveform centered about Vref generated by U 7  and U 8 . 
     The following discussion is in reference to the voltage graphs in  FIGS. 2   a - 2   c , in which the triangle wave is graphed as line  20 , the upper comparator U 1  threshold voltage is shown as line  21 , the lower comparator U 2  threshold voltage is shown as line  22 , the low side drive B is shown at  23  and the high side drive A is shown at  24 . Reference numbers  25  through  40  refer to specific points in time along time axis t. 
       FIG. 2   a  shows the graph for the situation where C 1  voltage is exactly equal to C 2  voltage. In this case, upper and lower peaks of the triangle waveform  20  are slightly higher than the upper  21  and lower  22  thresholds. Thus, the triangle wave  20  reaches slightly above the upper comparator threshold  21  at times  31  to  32  and  35  to  36 , and slightly below the lower comparator threshold  22  at times  29  to  30  and  33  to  34 , generating a narrow high side drive  24  pulse at times  31  to  32  and  35  to  36  and a narrow low side drive  23  pulse of equal pulse width at times  29  to  30  and  33  to  34 . This alternately pulses Q 1 , and then Q 2 , and does not change the voltage on C 1  or C 2 . 
       FIG. 2   b  shows the graph for the situation where C 1  voltage is greater than C 2  voltage. In this case, the current error amp U 6  output drops, and the relationship between upper threshold  21 , lower threshold  22  and triangle wave  20  is as shown in  FIG. 2   b . The peaks of the triangle wave  20  extend well above the upper comparator threshold  21  from time  37  to  38  and  39  to  40 , but the lower peaks do not drop below the lower comparator threshold  22  at any point. This generates a wide high side drive  24  pulse from  37  to  38  and  39  to  40 , but no low side drive  23  pulse. In turn, this pulses Q 1  and not Q 2 , decreasing the voltage on C 1  and increasing the voltage on C 2 , returning Vcp to the centerpoint. 
       FIG. 2   c  shows the graph for the situation where C 2  voltage is greater than C 1  voltage. In this case, the current error amp U 6  output rises, and the relationship between upper threshold  21 , lower threshold  22  and triangle wave  20  is as shown in  FIG. 2   c . The lower peaks of triangle wave  20  extend well below the lower comparator threshold  22  from time  25  to  26  and  27  to  28 , but the upper peaks do not reach above the upper comparator threshold  21 . This generates a wide low side drive  23  pulse from  25  to  26  and  27  to  28 , but no high side drive  24  pulse. In turn, this pulses Q 2 , and not Q 1 , decreasing the voltage on C 2  and increasing the voltage on C 1 , to once again return Vcp to the centerpoint. 
     Alternate Use 
     The supply described above can also be used as a standalone DC to DC converter which will transfer charge between two capacitive sources, not necessarily in series, so as to maintain any voltage ratio between the two capacitors. Power will be transferred dynamically from one source to the other, maintaining proper voltage balance. 
     The control circuit of  FIG. 1  can be used as a standalone DC/DC converter, so as to maintain a fixed relationship between Vpos and Vcp, or a fixed output voltage on Vpos or Vcp. 
       FIG. 3  shows an alternative use output circuit, replacing the circuit in box  10  of  FIG. 1 , which is useful for Vpos greater than Vcp. In this embodiment, the capacitor on Vpos is coupled between Vpos and ground, rather than between Vpos and Vcp. Power flows from Vpos to Vcp when A is pulsed, and power flows from Vcp to Vpos when B is pulsed. 
     If Vpos needs to be higher or lower than Vcp, then a third switch Q 3  and fourth switch Q 4  can be added, resulting in the alternative use output circuit as shown in  FIG. 4 . As with  FIG. 3 , this circuit would replace the output circuit of  FIG. 1 , box  10 . 
     The operation of this embodiment of the output circuit of  FIG. 4 , assuming Vpos is to be equal to Vcp, is as follows: 
     Signal A is connected through driver  45  to the switching input of second switch Q 2 , which turns on Q 2  when A is pulsed, allowing current flow between the first terminal and the second terminal of Q 2 . Signal A is also connected through an inverted driver  44  to the switching input of first switch Q 1 , which turns off Q 1  when A is pulsed, blocking current flow between the first terminal and the second terminal of Q 1 . 
     Signal B is connected through driver  46  to the switching input of fourth switch Q 4 , which turns on Q 4  when B is pulsed, allowing current flow between the first terminal and the second terminal of Q 4 . Signal B is also connected through an inverted driver  47  to the switching input of third switch Q 3  which turns off Q 3  when A is pulsed, blocking current flow between the first terminal and the second terminal of Q 3 . 
     The following discussion is in reference to the voltage graphs in  FIGS. 2   a - 2   c , in which the triangle wave is graphed as line  20 , the upper comparator U 1  threshold voltage is shown as line  21 , the lower comparator U 2  threshold voltage is shown as line  22 , the drive B, is shown at  23 , and drive A is shown at  24 . Reference numbers  25  through  40  refer to specific points in time along time axis t. 
       FIG. 2   a  shows the graph for the situation where C 1  voltage is exactly equal to C 2  voltage. In this case, upper and lower peaks of the triangle waveform  20  are slightly higher than the upper  21  and lower  22  thresholds. Thus, the triangle wave  20  reaches slightly above the upper comparator threshold  21  at times  31  to  32  and  35  to  36 , and slightly below the lower comparator threshold  22  at times  29  to  30  and  33  to  34 , generating a narrow A drive  24  pulse at times  31  to  32  and  35  to  36  and a narrow B drive  23  pulse of equal pulse width at times  29  to  30  and  33  to  34 . This alternately pulses Q 2  (and its inverse Q 1 ), and then Q 4  (and its inverse Q 3 ), and does not change the voltage on C 1  or C 2 . 
       FIG. 2   b  shows the graph for the situation where C 1  voltage is greater than C 2  voltage. In this case, the current error amp U 6  output drops, and the relationship between upper threshold  21 , lower threshold  22  and triangle wave  20  is as shown in  FIG. 2   b . The peaks of the triangle wave  20  extend well above the upper comparator threshold  21  from time  37  to  38  and  39  to  40 , but the lower peaks do not drop below the lower comparator threshold  22  at any point. This generates a wide A drive  24  pulse from  37  to  38  and  39  to  40 , but no B drive  23  pulse. In turn, this pulses Q 2  (and its inverse Q 1 ) and does not pulse Q 4  (and its inverse Q 3 ), decreasing the voltage on C 1  and increasing the voltage on C 2 , returning Vcp to be equal to Vpos. Note that switch Q 3  is fully on, acting to connect inductor L 1  to C 2 , and its inverse switch Q 4  is off. 
       FIG. 2   c  shows the graph for the situation where C 2  voltage is greater than C 1  voltage. In this case, the current error amp U 6  output rises, and the relationship between upper threshold  21 , lower threshold  22  and triangle wave  20  is as shown in  FIG. 2   c . The lower peaks of triangle wave  20  extend well below the lower comparator threshold  22  from time  25  to  26  and  27  to  28 , but the upper peaks do not reach above the upper comparator threshold  21 . This generates a wide B drive  23  pulse from  25  to  26  and  27  to  28 , but no A drive  24  pulse. In turn, this pulses Q 4  (and its inverse Q 3 ), and does not pulse Q 2  (and its inverse Q 1 ), decreasing the voltage on C 2  and increasing the voltage on C 1 , to once again return Vcp to equal Vpos. Note that switch Q 1  is fully on, acting to connect inductor L 1  to C 1 , and its inverse switch Q 2  is off. 
     It is known to those skilled in the art that Vpos and Vcp can be set to any ratio other than 1 by the choice of resistors around difference amp U 4  and voltage error amp U 5 . 
     Vcp can also be set as a fixed voltage output, while Vpos can be set as an input that can be higher or lower than Vcp. Likewise, Vpos can be set as a fixed voltage output while Vcp is an input that can be higher or lower than Vpos. 
     The capacitor voltage balance can be dynamically altered by a control voltage which can be derived from a logic device such as a microcontroller. This can be done by replacing the Vref block U 3  of  FIG. 1  with a microcontroller block that can dynamically alter the voltage Vref 
     It will be understood by one skilled in the art that analog functional blocks can be replaced by digital functionally equivalent blocks or incorporated into an integrated circuit. Circuits can also be used for DC/DC power conversion where power flow can be bidirectional. Either side can provide power and either side can be the load. 
     Accordingly, it is to be understood that the embodiments of the invention herein described are merely illustrative of the application of the principles of the invention. Reference herein to details of the illustrated embodiments is not intended to limit the scope of the claims, which themselves recite those features regarded as essential to the invention.