Abstract:
A search tuning type channel detector system for television receivers. When AFC voltage of a tuner has attained a first predetermined voltage level, frequency sweeping direction for tuning is reversed and stopped thereby to tune the tuner at an optimum tuning frequency. Means are provided to allow the inversion as well as stoppage of the frequency sweeping only when AFC voltage has attained a second predetermined voltage level, thereby to exclude possible erroneous operation due to noise or the like spurious signal components.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a channel selector apparatus suited to be used for an electronic tuner having a search function in a television receiver. 
     2. Description of the Prior Art 
     For the channel selector of television receivers, there have been hitherto known and widely used search type channel selectors and preset search type channel selection apparatus. In the former case, tuning voltage applied to the electronic tuner is swept or scanned to seach a desired television or TV signal. Upon reception of the TV signal of a desired channel, the sweeping operation is stopped. On the other hand, in the case of the preset search type channel selector, a ditigal signal is converted into an analog signal for sweeping the tuning voltage applied to the tuner. When the desired signal has been found, optimum tuning point for the reception of the signal is detected, whereupon the supply of the digital signal is interrupted. The channel selection apparatus of the prior art are, however, disadvantageous in that erroneous operations will be often involved particularly when the signal in concern is of a feeble intensity or when unfavorable conditions exist for the signal reception. 
     More specifically, it is common in the channel selector apparatus that the identity of a desired signal is discriminated by making use of variation in an automatic frequency control or AFC voltage applied to the tuner. For example, referring to FIG. 1 which graphically illustrates variation in AFC voltage in a form of so-called S-like curve, the tuning frequency is taken along the abscissa, while the AFC voltage is taken along the ordinate. As the tuning frequency is swept from a low to high frequency with the tuning voltage being correspondingly swept, an abrupt variation or change in the AFC voltage occurs upon reception of signal. That is, the AFC voltage which is at a high level in the quiescent state is lowered remarkably in response to the signal reception. Subsequent increase in the tuning frequency will result in increasing again the AFC voltage. In the hitherto known channel selectors described above, the sweeping direction of the tuning frequency is inverted when the AFC voltage has attained a predetermined voltage E o  at a frequency f 2  as indicated by a point P after having passed through a point Q at a frequency of f 1  , whereby the sweeping of the tuning frequency is made toward a low frequency. Consequently, the AFC voltage goes once below the voltage level E o  and subsequently rises up again. When the AFC voltage has attained in the course of the reversed sweeping the predetermined voltage level E o  at the frequency f 1  as indicated by the point Q, the sweeping of the tuning voltage is then stopped. In other words, the frequency f 1  at the point Q in the graph of FIG. 1 is selected as the optimum tuning frequency, the reason for which can be explained by the fact that the tuner is capable of receiving the signal in the most stabilized state at the frequency f 1  at the point Q. The frequency sweep is carried out slowly after the inversion of the sweeping direction. 
     Assuming that the behavior of the AFC voltage is digitalized and the level of AFC voltage higher than the reference E o  is represented by logic &#34;1&#34;, while the AFC level lower than E o  is represented by logic &#34;0&#34;, the corresponding changes in the logic value during the sweeping of the tuning frequency will be such as shown in FIG. 2(a), in which time is scaled along the abscissa. As can be seen from FIG. 2(a), the logic value of the AFC voltage will change over from &#34;1&#34; to &#34;0&#34; at a time point t 1  at which the tuning frequency has attained the frequency f 1 . Subsequentyly, at time t 2  corresponding to the frequency f 2 , the logic level of the AFC voltage will restore to &#34;1&#34;. In the course of the inverted sweeping, when the tuning frequency is decreased below the frequency f 2  at time t 3 , the logic level of the AFC voltage will be reset to &#34;0&#34;.  When the tuning frequency is further decreased until the frequency f 1  has been attained again at time t 4 , the logic level &#34;1&#34; of AFC voltage will be then re-established. At this time, the sweeping operation is stopped. 
     In conjunction with the above description, it should be noted that the AFC circuit is in general a high impedance circuit and that noise is frequently superposed on the AFC voltage. Accordingly, there will arise such situation that the AFC voltage which has taken the logic &#34;1&#34; level at the time point t 2  will undergo variation in respect of the magnitude and hence the logic value due to noise, as illustrated in FIG. 2(b). Under such circumstance, the AFC voltage could not regain the point Q. Nevertheless, the sweeping of the tuning frequency is interrupted at time t 5 , which means that the correct or optimum tuning can not be established. Of course, the noise components superposed on the AFC voltage may be removed by means of a capacitor. However, connection of such filter capacitor will in turn result in an unacceptably increased time constant, to involve slower variation in the AFC voltage as well as a low sweeping rate. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the invention is to provide a channel selector apparatus which is essentially immune to erroneous operations and is capable of stopping positively the sweeping operation at the optimum frequency. 
     In view of the above and other objects which will become apparent as description proceeds, the invention teaches with a view to suppressing any erroneous operation due to noise components superposed on AFC voltage that a first voltage corresponding to a first and a fourth frequency values are utilized in combination with a second voltage which corresponds to a second and a third frequency values and has a magnitude different from that of the first voltage, wherein the optimum tuning frequency is selected at the first frequency value for the first voltage through the detection of AFC voltage, thereby to allow the sweeping of the tuning frequency to be stopped, so far as the sweeping of the tuning frequency is allowed to be stopped also at the third frequency value for the second voltage. 
     In a preferred embodiment of the invention, although the sweeping direction of the tuning frequency is inverted at the fourth frequency value for the first voltage, it is prerequisite that the sweeping inversion at the second frequency value for the second voltage must be permitted. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates graphically relation between AFC voltage and a tuning frequency. 
     FIG. 2 shows signal-time diagrams to illustrate behaviors of AFC voltage in terms of logical values. 
     FIG. 3 is a block diagram illustrating a general arrangement of the channel selector apparatus according to an embodiment of the invention. 
     FIG. 4 illustrates graphically behaviors of the AFC voltage in terms of digital and analog quantities. 
     FIG. 5 is a circuit diagram showing a main portion of the channel selector apparatus according to an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3 which shows in a block diagram a general arrangement of a channel selector apparatus according to the invention, an electronic tuner 1 is connected to a sweep voltage generator 2 which in turn is connected to a sweep control circuit 3 serving for controlling the sweep voltage generator 2 to effect the sweeping of a tuning voltage in the increasing and decreasing directions as well as the stopping and starting of the sweeping operation. First and second voltage detectors 4 and 5 are connected to the sweep control circuit 3. The first detector 4 serves to detect when the AFC voltage has attained a first preset value, while the second voltage detector 5 serves to detect that the AFC voltage has attained a second predetermined value or level. The AFC voltage is applied at a terminal 6. 
     As the tuning voltage supplied to the tuner 1 from the sweep voltage generator 2 is increased, the tuning frequency of the electronic tuner 1 is correspondingly increased. In the meantime, when a signal is received, the AFC voltage will undergo variation such as shown at (a) in FIG. 4. So long as the AFC voltage is at a level higher than a threshold level E o , the first voltage detector 4 produces logic &#34;1&#34; output. When AFC voltage is lowered below the voltage level E o ,the detector 4 produces logic &#34;0&#34;. On the other hand, the output from the second voltage detector 5 is either logic &#34;1&#34; or &#34;0&#34; in dependence on whether the AFC voltage is higher or lower than the threshold voltage E 1 . The signal waveform output from the first voltage detector 4 is illustrated at (b) in FIG. 4, while that of the second voltage detector 5 is shown at (c) in the same figure. It is to be mentioned that frequency is taken along the abscissa with the output level being taken along the ordinate in all the graphs (a), (b) and (c). According to the teaching of the invention, the preset threshold voltage level of the first voltage detector 4 differs from that of the second voltage detector 5. Thus, the frequency at which the output siganl state from the first voltage detector 4 changes over is different from the frequency at which the output signal state from the second voltage detector 5 is caused to change. Consequently, when the tuning frequency of the electronic tuner 1 is swept from a low frequency to a high frequency, the output signal from the first voltage detector circuit 4 will become logic &#34;0&#34; at a frequency value f 1  in the first place and subsequently the output signal from the second voltage detector circuit 5 will be logic &#34;0&#34;  at a frequency value f 3 . When the tuning frequency is further increased and has attained a frequency value f 4 , the output signal state of the second voltage detector 5 will be restored to logic &#34;1&#34;, which is followed by restoration to logic &#34;1&#34; of the output signal from the first voltage detector circuit 4, whereupon the sweeping direction of the tuning frequency is inverted. In other words, the inversion of the sweeping direction is permitted when the output signal from the first voltage detector circuit 4 is restored to logic &#34;1&#34; after the output signal from the second voltage detector circuit 5 has once taken the logic &#34;0&#34; level. At this time, the sweeping is inhibited from being stopped. In this manner, even when the output signal from the first voltage detector circuit 4 alternates repeatedly between the logic levels &#34;1&#34; and &#34;0&#34; due to influence of the superposed noise, the sweeping operation is never interrupted. In the course of the inverted sweeping, when the timing frequency becomes lower than the value f 2 , the output signal from the first voltage detector circuit 4 will be changed over to logic &#34;0&#34; state. Further decrease of the tuning frequency below f 4  will cause the output signal from the second voltage detector circuit 5 to be changed to logic &#34;0&#34;. At the frequence f 3  in the course of the inverted sweeping, the output signal from the second voltage detector 5 is restored to logic &#34;1&#34;, which is followed by restoration to logic &#34;1&#34;  of the output signal from the first voltage detector circuit 4, whereupon the sweeping operation is caused to stop. In other words, the inverted frequency sweeping is caused to stop at the time when the output signal from the first voltage detector circuit 4 is changed to logic &#34;1&#34; after the output signal from the second voltage detector circuit 5 has been restored to the logic &#34;0&#34; state. By selecting the optimum tuning frequency at f 1 , the electronic tuner can receive the signal of the selected channel in a stabilized manner. 
     FIG. 5 shows typical embodiments of circuit arrangements for the first and second voltage detector circuits as well as the sweep control circuit described above. The first voltage detector circuit 4 is composed of resistors 30, 31, a Zener diode 7 and a transistor 9, while the second voltage detector circuit 5 is constituted by resistors 32, 33, a Zener diode 8 and a transistor 10. It is to be mentioned that the first and second voltage detectors 4 an 5 shown in FIG. 5 are so implemented that the logical values of the outputs therefrom are complementary to those described above in conjunction with FIG. 4. The sweep control circuit 3 includes NAND gates 11 to 18, OR gates 35 to 37, an NOR gate 19 and an inverter 34. AFC voltage is applied to a terminal 36, while power source voltage is supplied to a terminal 24. Numeral 20 denotes a reset terminal to which a reset signal is applied from a channel selection button array (not shown), 21 denotes an output terminal for producing an output signal for sweeping the tuning frequency from a low to a high frequency (i.e. in the increasing direction), 22 denotes an output terminal for producing output signal for sweeping the tuning frequency in the decreasing direction, and 23 designates a terminal for producing a signal for stopping the frequency sweeping. It will be noted that pairs of NAND gates 11, 12; 13, 14; 15, 16; and 17, 18 constitute flip-flops 40, 41, 42 and 43, respectively. 
     Before starting the frequency sweeping, a reset pulse signal varying the logic state thereof from &#34;1&#34; to &#34;0&#34; for signal reception of a certain channel is applied to the reset input terminal 20. In the quiescent state (i.e. in the absence of input signal), the AFC voltage is at a level higher than the first and the second threshold voltages E o  and E 1 , so that both of the transistors 9 and 10 are in the conductive state. Upon reception of a television signal, the AFC voltage is lowered below the first and the second voltages E o  and E 1 , whereby the Zener diodes 7 and 8 as well as the transistors 9 and 10 become non-conductive. 
     Assuming that the transistors 9 and 10 are conductive, the output signals from the first and second voltage detector circuits 4 and 5 are logic &#34;0&#39;s&#34;. All of the flip-flops 40 to 43 are reset through the reset pulse signal applied to the NAND gates 12, 14, 16 and 18. Under the condition, the output signals from the flip-flops 40, 41 and 42 are logic &#34;1&#39;s&#34;, while the output from the flip-flop 43 is logic &#34;0&#34;. In response to the resetting of the flip-flop 41, the logic &#34;1&#34; signal appears at the terminal 21 to start the frequency sweeping. At that time, the output signals at the terminals 22 and 23 are both logic &#34;0&#39;s&#34;. When the AFC voltage becomes lower than the first voltage E o  as the tuning frequency is increased, the Zener diode 7 is turned off to make the transistor 9 to be non-conductive. As a result, the output signal from the first voltage detector circuit 4 becomes logic &#34;1&#34;. In this case, no change occurs in the operating state of the sweep control circuit 3. Further decreasing of the AFC voltage below the second threshold voltage E 1 , the transistor 10 is also turned off, resulting in the logic &#34;1&#34; signal output from the second voltage detector circuit 5. This signal is inverted through the inverter 34 and applied to the flip-flop 40, whereby the latter is set. Under the condition, the signal supplied to the OR gate 35 from the NAND gate 12 is at the logic &#34;0&#34; level. In the meantime, no variation occurs in the logic values of the output signals at the terminals 21 to 23. The lowering of the AFC voltage below the second threshold voltage E 1  is stored by the flip-flop 40 set as described above. When the tuning frequency is further increased, the AFC voltage is again increased to turn on the transistor 10 again, whereby the output signal from the second voltage detector circuit 5 becomes logic &#34;0&#34;. During this period, the operation of the sweep control circuit 3 undergoes no variation. Further increase of AFC voltage brings about the turning-on of the transistor 9, which is turn results in the logic &#34;0&#34; signal output from the first voltage detector circuit once again. Then, both inputs to the OR gate 35 become logic &#34;0&#39;s&#34;  and thus the flip-flop 41 is set. The signal supplied to the OR gate 36 and the terminal 21 from NAND gate 14 becomes logic &#34;0&#34;. Since the output voltage at the terminal 23 is then also logic &#34;0&#34;, the output signal from the terminal 22 is logic &#34;1&#34;, whereby the sweeping direction is inverted. In the inverted sweeping, the AFC voltage is initially decreased to a level below the second voltage E 1 , as a result of which the transmitter 10 is turned off and thus the output signal from the second voltage detector circuit 5 becomes logic &#34;1&#34;. This output signal is inverted by the inverter 34 and applied to the OR gate 36. Thus, the two inputs to OR gate 36 are both logic &#34;0&#39;s&#34; thereby to set the flip-flop 42. The signal transferred from the NAND gate 16 to OR gate 37 is then logic &#34;0&#34;. The output from the inverter 34 is also supplied to the flip-flop 40, the state of which remains however unchanged. The lowering of the AFC voltage below the second threshold voltage E 1  at the second time is stored or memorized by the flip-flop 42. When the AFC voltage is once again increased in the inverted sweeping phase, thereby to turn on the transistors 10 and 9 sequentially, the output voltage from the first voltage detector circuit 4 will become logic &#34;0&#34;. Consequently, the logic &#34;0&#34; output from the OR gate 37 will set the flip-flop 43. The signal supplied to the terminal 23 from the NAND gate 17 thus becomes logic &#34;1&#34; and brings about the stoppage of the frequency sweeping. 
     For serching another channel, pulse signal having logic level varying from logic &#34;0&#34; to &#34;1&#34; in this order is applied to the input terminal 20. Upon application of the logic &#34;0&#34; signal at the terminal 20, the flip-flops 40 to 43 are reset and thus the output signal at the terminal 21 becomes logic &#34;1&#34;. So long as the signal supplied to the terminal 20 is held at logic &#34;0&#34; level, the output signals at the terminals 22 and 23 are maintained at logic &#34;0&#34; level, whereby the sweeping can be continued without inversion or interruption. When the state is attained for receiving the signal of a desired channel, the signal supplied to the terminal 20 is changed over to the logic &#34;1&#34; level and the selection of the optimum tuning frequency for the selected channel can be accomplished in the manner described above. 
     The sweep voltage generator used in the channel selector apparatus according to the invention may be composed of any conventional sweep voltage generator such as a digital-to-analog converter or the one in which charging and discharging of a capacitor is made use of. 
     In the case where the S-like curve such as shown in FIG. 4, (a) is upset, the voltage E 1  may be selected higher than the voltage E o . 
     From the foregoing description, it will be appreciated that the channel selector apparatus according to the invention is essentially immune to erroneous operation due to noise component superposed on the AFC voltage and assures that the tuner can receive the TV signal at selected channel in a much stabilized state at the optimum tuning frequency. Further, because a filtering capacitor need not be connected to the input terminal for AFC voltage, the frequency sweeping rate can be enhanced.