Abstract:
A method of controlling a laser driver includes determining a set of timing parameters in response to contents of a received bit stream. The method further includes creating a plurality of sets of pulse defining parameters in response to the set of timing parameters, and generating a plurality of generic pulses in response to the plurality of sets of pulse defining parameters. The method also includes combining the plurality of generic pulses into a plurality of enable signals, and creating a plurality of adapted enable signals by selectively replacing one of the plurality of enable signals with an alternative signal. The method further includes outputting the plurality of adapted enable signals to the laser driver.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 13/019,011, filed Feb. 1, 2011, which is a continuation of U.S. application Ser. No. 12/853,337 (now U.S. Pat. No. 7,881,172), filed Aug. 10, 2010, which is a continuation of U.S. application Ser. No. 11/455,533 (now U.S. Pat. No. 7,773,479), filed Jun. 19, 2006, which claims the benefit of U.S. Provisional Application No. 60/798,598, filed May 8, 2006, and U.S. Provisional Application No. 60/725,968, filed Oct. 12, 2005. The disclosures of the applications referenced above are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to flexible waveform generation, and more particularly to flexible waveform generation for optical systems. 
     BACKGROUND 
     Optical media such as CDs (compact discs) and DVDs (originally, digital versatile discs) are read and written by way of a laser. The laser is driven by a laser driver, which receives waveforms that differ based upon the bit stream to be written and the type and specifications of the optical media. In order to support writing to a wide variety of media, including CD-R, CD-RW, DVD-R, DVD+R, DVD-RW, DVD+RW, and DVD-RAM, a flexible waveform generation scheme is needed. 
     SUMMARY 
     A driver comprising: a pattern module configured to generate a plurality of timing parameters in response to a received bit stream; a timing module configured to determine a plurality of multi-bit parameters in response to the timing parameters; and a pulse module configured to (i) generate each of a plurality of pulses in response to a different one of the plurality of multi-bit parameters, (ii) generate each of a plurality of enable signals in response to a variable combination of the plurality of pulses, and (iii) output the plurality of enable signals to a laser driver. 
     In still other features, the methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage and/or other suitable tangible storage mediums. 
     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. The detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is an exemplary bit stream of write channel data and a corresponding laser driver pulse; 
         FIG. 2  is an exemplary set of enable pulses that can be used to form the driver output waveform; 
         FIG. 3  is a functional block diagram of an exemplary laser driver; 
         FIG. 4  is a timing diagram depicting an exemplary scheme for generating the enable signals of  FIG. 2 ; 
         FIG. 5  is a block diagram of an exemplary implementation of an optical media writing system; 
         FIG. 6  is a functional block diagram of an exemplary implementation of the write strategy module; 
         FIG. 7  is an exemplary depiction of the contents of the lookup table; 
         FIG. 8A  is an exemplary implementation of parameter tables, such as might be used for groove tables or land tables; 
         FIG. 8B  is an alternative implementation of parameter tables; 
         FIG. 9  is a detailed functional block diagram of an exemplary implementation of the write strategy module of  FIG. 5 ; 
         FIG. 10A  is a functional block diagram of a group of edge generators; 
         FIG. 10B  is a functional block diagram of an exemplary implementation of the pulse combining logic; 
         FIG. 11  is a functional block diagram of an exemplary implementation of the write strategy timing encoding module; 
         FIG. 12  is a graphical depiction of operation of an exemplary write strategy timing encoding module; 
         FIG. 13A  is a functional block diagram of an exemplary implementation of an edge generator of type A; 
         FIG. 13B  is a functional block diagram of an exemplary implementation of an edge generator of type B; 
         FIG. 14  is a graphical depiction of operation of an exemplary coarse timing generator; 
         FIG. 15A  is a functional block diagram of an exemplary implementation of a coarse timing generator of type A; 
         FIG. 15B  is a functional block diagram of an exemplary implementation of a coarse timing generator of type B; 
         FIG. 16A  is a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 3, MTW of 1, and N of 4; 
         FIG. 16B  is a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 4, MTW of 1, and N of 4; 
         FIG. 16C  is a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 2, MTW of 2, and N of 4; 
         FIG. 16D  is a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 2, MTW of 3, and N of 4; 
         FIG. 17A  is a timing diagram for an exemplary mark writing waveform for single-power pulse writing; 
         FIG. 17B  is a timing diagram for an exemplary mark writing waveform for two-power pulse writing; 
         FIG. 17C  is a timing diagram for an exemplary mark writing waveform for three-power pulse writing; 
         FIG. 17D  is a timing diagram for an exemplary mark writing waveform for single-power pulse writing with cooling; 
         FIG. 17E  is a timing diagram for an exemplary mark writing waveform for two-power pulse writing with cooling; 
         FIG. 17F  is a timing diagram for an exemplary mark writing waveform for single-power level writing; 
         FIG. 17G  is a timing diagram for an exemplary mark writing waveform for two-power level writing; 
         FIG. 17H  is a timing diagram for an exemplary mark writing waveform for three-power level writing; 
         FIG. 17I  is a timing diagram for an exemplary mark writing waveform for single-power level writing with cooling; 
         FIG. 17J  is a timing diagram for an exemplary mark writing waveform for two-power level writing with cooling; 
         FIG. 17K  is a timing diagram for an exemplary mark writing waveform for three-power level writing with cooling; 
         FIG. 17L  is a timing diagram for an exemplary mark writing waveform for single-power pulse writing with cooling and pulsed erase; 
         FIG. 17M  is a timing diagram for an exemplary mark writing waveform for variable-power level writing; 
         FIG. 18  is a functional block diagram of an exemplary optical media system incorporating a write strategy implementation according to the principles of the present invention; 
         FIG. 19A  is a functional block diagram of a digital versatile disk (DVD); 
         FIG. 19B  is a functional block diagram of a high definition television; 
         FIG. 19C  is a functional block diagram of a set top box; and 
         FIG. 19D  is a functional block diagram of a media player. 
     
    
    
     DETAILED DESCRIPTION 
     The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present invention. 
     Referring now to  FIG. 1 , an exemplary bit stream of write channel data and a corresponding laser driver pulse are presented. Data that is to be written to optical media may first be encoded using techniques such as CRC (cyclic redundancy check), ECC (error-correcting code), Reed-Solomon coding, and/or interleaving. The encoded data is often then transformed using an 8-to-16 conversion. The 8-to-16 conversion ensures that one values in the bit stream are separated by at least two zero values, and that there are at most 14 consecutive zeros. The resulting channel bit stream is written to the optical media using NRZI (non-return-to-zero inverted) encoding. In NRZI encoding, a one value will cause a transition (either high to low or low to high) while a zero value will cause the waveform to remain constant. 
     An exemplary channel bit stream is represented as waveform  102 . The waveform  102  contains one bit for every time period T. The portion of the waveform  102  shown in  FIG. 1  contains two transitions, one from low to high, and one from high to low. These transitions correspond to one values at  104 - 1  and  104 - 2 ; the binary values communicated by waveform  102  at all other times T in  FIG. 1  are zero. The interval where the waveform  102  is high is referred to as a mark  106 , while the intervals where the waveform  102  is low are referred to as spaces  108 - 1  and  108 - 2 . 
     Marks may be represented on the optical media as areas of low reflectivity (pits), amorphous domains, or any other type or form that can be sensed by the optical system, while spaces may be represented as areas of high reflectivity between marks. These reflectivities may be created by a laser beam that heats the optical media to different temperatures. Heating above a melting temperature disrupts the ordered structure of the optical media, leaving it in an amorphous, low-reflectivity state. Heating the media above a crystallization temperature, but below the melting temperature, allows the media to revert back to an orderly crystal structure that has high reflectivity. Reverting portions of the media back to high reflectivity is termed erasing. 
     Depending upon the parameters of the optical media, and the binary encoding scheme employed, the length of marks and spaces may be constrained. For example, marks may be no shorter than 2 T and no longer than 14 T, while spaces may be no shorter than 3 T and no longer than 14 T. The above-described 8-to-16 conversion produces at least two zeros after a one, and thus the minimum length of a certain state (either mark or space) is 3 T. The mark depicted in waveform  102  is 9 T long, and is preceded by a space greater than 1 T in length and followed by a space greater than 2 T in length. 
     A laser driver sends a waveform to the laser to write the 9 T mark  106  to the optical media; an exemplary waveform is depicted at  110 . Waveform  110  includes various power levels with respect to zero power level  112 . Waveform  110  begins with a first power level P c , the erase power. Waveform  110  then increases in power for a first pulse at power P p1 . At the end of the first pulse, waveform  110  drops to a base power, P b . Waveform  110  then contains four 50%-duty-cycle middle pulses, each having a period equal to the bit time T and having a power equal to P p2 . The low times of the middle pulses have power P b . After the four middle pulses, the waveform  102  contains a last pulse at power P p3 . Waveform  110  then decreases in power to P c1 , the cooling power, which may be greater than or equal to P b . In this example, however, P c , is less than P b . Waveform  110  then returns to the erase power P c . As further demonstrated below, many other waveforms are possible, and can vary in such features as number and duty cycle of middle pulses, power levels, and presence and number of first or cooling pulses. 
     Referring now to  FIG. 2 , an exemplary set of enable pulses that can be used to form the driver output waveform is pictorially represented. This set of enable pulses is combined as shown below with respect to  FIG. 3 . A first enable signal EN 1   120  may always be high, corresponding to a constant bias power level. Maintaining a bias power level greater than zero allows the laser to more quickly begin writing. In the example of  FIG. 2 , the lowest power level is P c1 , and so EN 1   120  causes P c1  to be constantly asserted as a bias power. If the laser were reading instead of writing from the optical media, the power associated with EN 1   120  may be a constant read power level, P read . In future figures, the first enable signal EN 1  is not shown because it is constant. 
     The second enable signal EN 2   122  corresponds to the first pulse, and is associated with power P p1 -P b . The third enable EN 3   124  corresponds to the four middle pulses, and is associated with power P p2 -P b . The fourth enable EN 4   126  corresponds to the last pulse and is associated with power P p3 -P b . The fifth enable EN 5   128  corresponds to the inverse of the cooling pulse and has an associated power level of P b -P c1 . Lastly, the sixth enable EN 6   130  corresponds to the erase portions of the waveform  110  and has an associated power level of P c -P b . 
     The waveform  110  depicted in  FIG. 2  has a cooling power, P c1 , that is less than the base power P b . The fifth enable EN 5   130  therefore is an inverted pulse; EN 5  is low only for the cooling pulse. This creates a base power of P b  for all portions of the waveform except the cooling pulse. If the cooling power were instead greater than the base power, the polarity of EN 5   128  would be reversed, the associated power level would be P c1 -P b , and the power level associated with EN 1   120  would be P b , not P c1 . 
     Referring now to  FIG. 3 , a functional block diagram of an exemplary laser driver is presented. The laser driver  140  is able to combine the enable signals of  FIG. 2  to produce the driver output  110  of  FIG. 2 . The laser driver  140  receives enable signals from a write strategy pulse generation module  142 ; examples of these enable signals are depicted in  FIG. 2  at  122 ,  124 ,  126 ,  128 , and  130 . A group  144  of digital to analog converters (DACs) provides voltages and/or currents to the laser driver  140 , each of which determines the power level associated with one of the enable signals. The laser driver  140  also receives a read enable signal (such as EN 1   120  in  FIG. 1 ), which indicates a constant read power, or a constant writing bias power. 
     The laser driver  140  includes six switches  150 , six multipliers  152 , and a summing module  154 . The first switch  150 - 1  receives a first voltage or current from the DACs  144 , and also receives the read enable signal. When the read enable signal is high (alternately, the laser driver could work with active low logic), the first switch  150 - 1  passes the first voltage or current through to the first multiplier  152 - 1 . The first multiplier  152 - 1  multiplies the incoming voltage or current by a constant K 1 . The first multiplier  152 - 1  then communicates that amplified voltage or current to the summing module  154 . 
     The second switch  150 - 2  receives an enable signal from the write strategy pulse generation module  142  and a second voltage or current from the DACs  144 . When the enable signal is high, the switch  150 - 2  communicates the incoming voltage or current to the second multiplier  152 - 2 . The second multiplier  152 - 2  multiplies the incoming voltage or current by a constant K 2  before passing the signal to the summing module  154 . This functionality is repeated by the remaining switches  150 - 3 ,  150 - 4 ,  150 - 5 , and  150 - 6 , and multipliers  152 - 3 ,  152 - 4 ,  152 - 5 , and  152 - 6 . 
     The summing module  154  sums the six amplified inputs, and outputs the result to a laser  156 . In this way, the enable signals shown in  FIG. 2  are superimposed onto each other at appropriate power levels to create the desired laser driver output. The exemplary laser driver  140  is shown with six inputs, though more or fewer inputs are possible. In various implementations of the laser driver  140 , the signal shown as read enable may be a global enable for the laser driver; i.e., when the read enable signal is low, all switches  150  are turned off and the output of the laser driver  140  is zero. 
     The write strategy pulse generation module  142  and DACs  144  may be implemented to match the number of inputs of the laser driver  140 . However, it is possible for more enable signals to be generated by the write strategy pulse generation module  142  than can be received by the laser driver  140 . Alternately, the laser driver  140  may have more inputs than the write strategy pulse generation module  142  provides. 
     Referring now to  FIG. 4 , a timing diagram depicts an exemplary scheme for generating the enable signals of  FIG. 2 . The enable signals  122 ,  124 ,  126 ,  128 , and  130  are combined by the laser driver as shown in  FIG. 3  to create the desired driver output waveform  110 . The driver output waveform  110  is used by the laser to store the channel bits  102  to the optical media. The enable signals are created by combinations of generic pulses. 
     The second enable signal EN 2   122 , which defines the first pulse of the driver output waveform  110 , is created by a logical XOR of two generic pulses, pulse 1 _r  160  and pulse 1 _f  162 . The logical XOR operation means that the rising edge of pulse 1 _r  160  creates the rising edge of EN 2 , while the rising edge of pulse 1 _f  162  creates the falling edge of EN 2 . The time delay from the beginning of the mark, shown as the rising edge in the channel bit stream  102 , to the rising edge of pulse 1 _r  160 , is defined by a parameter named dtop. If dtop is negative, the rising edge of pulse 1 _r will occur prior to the beginning of the mark. The rising edge of pulse 1 _f  162  is defined to occur a specified period of time, ttop, after the rising edge of pulse 1 _r  160 . The parameter ttop therefore defines the width of the first pulse. 
     The third enable signal EN 3   124  is created from a logical XOR of two generic pulses, pulse 2 _r  164  and pulse 2 _f  166 . The rising edge of pulse 2 _r  164  occurs a specified time, dtmp, after the rising edge of pulse 1 _f  162 . Because four middle pulses are desired in EN 3   124 , pulse 2 _r and pulse 2 _f are programmed to have four edge transitions. If, for example, two middle pulses were instead desired, pulse 2 _r and pulse 2 _f would each have two edge transitions. After the initial rising edge of pulse 2 _r  164 , a falling edge follows at a time equal to a multiple of T, the bit clock period. The third transition, which is now a rising edge, occurs at another increment of T, while the fourth transition, a falling edge, occurs at a further increment of T. 
     The first rising edge of pulse 2 _f occurs a specified time, ttmp, after the first rising edge of pulse 2 _r  164 . The remaining edges of pulse 2 _f are also spaced in increments of T. The third enable will thus produce pulses with period T, while the duty cycle is determined by ttmp. When ttmp is greater than T/2, the duty cycle of the middle pulses will be greater than 50%. For other optical media, the pulses within pulse 2 _r 164  and pulse 2 _f 166  may have a period that is a multiple of T, such as 2 T or 3 T. 
     The fourth enable EN 4   126 , corresponding to the last pulse of waveform  110 , is formed by a logical XOR of pulse 3 _r  168  and pulse 3 _f  170 . The rising edge of pulse 3 _r  168  occurs a specified time, dlast, after the final transition of pulse 2 _f  166 . The rising edge of pulse 3 _f  170  occurs a specified time, tlast, after the rising edge of pulse 3 _r  168 . The fifth enable EN 5   128 , corresponding to erase power, is formed by the inverse of the logical XOR (XNOR) of erase_r  172  and erase_f  174 . 
     The rising edge of erase_r  172  occurs a specified time, tcool, after the rising edge of pulse 3 _f  170 . The rising edge of erase_f  174  occurs a specified time, derfl, relative to the beginning of the mark (shown as the rising edge in channel bit stream  102 ). If derfl is negative, the rising edge of erase_f  174  will occur before the beginning of the mark. The sixth enable EN 6   130 , corresponding to the cool pulse, is formed by the inverse of the logical XOR (XNOR) of pulse 3 _f  170  and erase_r  172 . Finally, a reset pulse  176  occurs after the end of the mark. The falling edge of the reset pulse  176  synchronously resets all of the generic pulses  160 ,  162 ,  164 ,  166 ,  168 ,  170 ,  172 , and  174 . 
     Referring now to  FIG. 5 , a block diagram of an exemplary implementation of an optical media writing system is presented. A control module  190  communicates with a read/write channel, with a group of DACs (digital to analog converters)  192 , and with a write strategy module  194 . The write strategy module  194  receives a write data bit stream. The write strategy module  194  converts this bit stream into timing information in the form of enable signals, which are communicated to a laser driver  196 . 
     The laser driver  196  also receives a read enable signal from the control module  190  and power level information in the form of voltage and/or current signals from the DACs  192 . The laser driver  196  combines the power levels based upon the enable signals and transmits the result to a laser  198 . The control module  190  performs a variety of functions, including determining when the laser driver  196  should be reading or writing to the optical media, and coordinating calibration of power level and timing information for the current optical media. 
     An optical sensor  202  gathers information from the laser  198  as reflected by the optical media. This information is communicated to a preamplifier  204 , which communicates an amplified form of the information to the control module  190 . The control module  190  may calibrate the power level information and/or the timing information. This can be done, for example, upon system power-on, at the time of manufacturing, at periodic intervals, when parameters of interest (such as temperature) change, and/or when a new type or instance of optical media is introduced. The control module  190  may write test patterns to a portion of the optical media and read them back to determine the efficacy of calibration parameters. The control module  190  may begin calibration using a default set of parameters stored for each type of optical media or from previously determined values. 
     Referring now to  FIG. 6 , a functional block diagram of an exemplary implementation of the write strategy module is presented. The laser driver  196  receives power level information from the DACs  192  and a read enable signal, and communicates the result to the laser  198 . Within the write strategy module  194  is a write pulse pattern lookup table  210 , a PLL (phase-locked loop) and clock recovery module  212 , a write strategy timing encoding module  214 , and a write strategy pulse generation module  216 . The lookup table  210  contains parameters for pre-defined write pulse patterns, which it selects based upon the received write data bit stream. 
     The PLL and clock recovery module  212  generates a stable clock signal, as well as divided clocks to accommodate slower writing speeds. Clock information is communicated to the lookup table  210 , the timing encoding module  214 , and the pulse generation module  216 . The timing encoding module  214  receives parameters from the lookup table  210  and encodes these parameters into precise timing instructions that are communicated to the pulse generation module  216 . The lookup table  210  may be implemented as a table that looks up parameters based upon characteristics of the write data bit stream, a set of calculations performed on the characteristics, or a combination of both approaches. A combined approach may involve a set of base parameters stored in a table that are altered programmatically by mathematical operations. The pulse generation module  216  generates edges based on the commands from the timing encoding module  214  and combines these pulses to create the enable pulses, which are communicated to the laser driver  196 . 
     Referring now to  FIG. 7 , exemplary depiction of the contents of the lookup table are depicted. Because DVD-RAM writes data on both the land and the groove of optical media, separate tables for groove  220  and land  222  are provided. Within each group of tables  220  and  222  is a table for the derfl, dtop, ttop, dtmp, and ttmp parameters  224 . There is also a table for the number of middle pulses (mpcount)  226 . There is also a table for the dlast, tlast, and tcool parameters  228 . Other groupings of tables are possible, allowing for greater or lesser flexibility in choosing parameters. These parameters may be calibrated at the factory or may have starting values initially calibrated at the factory that can be adjusted in a user&#39;s system based upon operating parameters and/or parameters of inserted optical media. 
     Selections are made from the tables  220  and  222  based upon parameters such as mark length (in units of the channel bit clock T), leading space length (i.e., the length of the space prior to the current mark) and following space length (i.e., the length of the space following the current mark). The lookup table  210  includes a control module  234  that receives the write data bit stream. The control module  234  analyzes the incoming bit stream to determine when marks and spaces will need to be written. 
     Before the length of a mark can be determined and a table entry chosen, the control module  234  must receive the end of the mark. Further, if the table entry depends upon the length of the following space, the control module  234  must wait until the current mark ends, and the next begins (thus demarcating the end of the following space). The original incoming bit stream may be in raw 0s and 1s (NRZ), or may already have been converted to NRZI. If not converted to NRZI, the control module  234  may perform this function—conversion can entail ending the current mark or space (and thus starting the next space or mark, respectively) for each one value in the NRZ bit stream. Data is typically written to optical media in NRZI format, and thus the waveforms depicted are NRZI, though the write strategy according to the principles of the present invention is not limited to NRZI waveforms. 
     Referring now to  FIG. 8A , an exemplary group of parameter tables  238 , such as might be used for groove tables  220  or land tables  222 , is depicted. Each table of the group of tables  238  contains various entries for pulse parameters based upon characteristics of the incoming data stream, such as leading space length, following space length, and mark length. Parameters can be stored in groups within a single table. For instance, an exemplary first table  240  contains 24 entries, with each entry containing values for the parameters derfl, dtop, ttop, dtmp, and ttmp. The mark length and leading space length of the current mark specify which entry to choose. In various implementations, table  240  can include table entries for mark lengths from 2 T to 7 T. If the mark is longer than 7 T, the 7 T entry can be used. 
     Likewise, table  240  can include table entries for leading space lengths of 3 T through 6 T, and the 6 T entry is used if the leading space is longer than 6 T. If, for instance, the leading space length is 4 T and the mark length is 10 T, table entry x 12  is used. Table entry x 12  corresponds to a specific set of values for parameters derfl, dtop, ttop, dtmp, and ttmp. Similarly, for a mark length of 3 T and a leading space length of 5 T, the values stored at table entry x 14  will be used. 
     A second exemplary table  242  contains values for the mpcount parameter. Table  242  includes entries for mark lengths (depicted as columns) from 2 T to 14 T, and the 14 T entry will be used if the mark length is greater than 14 T. Table  242  includes entries for leading space lengths (depicted as rows) from 3 T to 6 T, and the 6 T entry will be used if the leading space length is greater than 6 T. For instance, with a mark length of 7 T and a leading space length of 7 T, the value of mpcount at table entry y 45  will be used. 
     A third exemplary table  244  contains values for dlast, tlast, and tcool parameters. Table  244  includes entries for mark lengths from 2 T to 14 T, with mark lengths greater than 14 T using the 14 T entry. Table  244  includes entries for following space lengths from 3 T to 6 T, with space lengths greater than 6 T using the 6 T entry. For a mark length of 7 T and a following space length of 5 T, for example, the values of dlast, tlast, and tcool stored at table entry z 32  will be used. If any of the tables within the group  238  is desired to have entries for space length of 2 T instead of 3 T, the table can be modified so that the space length entries are for 2 T, 3 T, 4 T, and 5 T+. Alternately, the table entries can be adapted for spaces of 2/3, 4, 5, and 6 T+ where 2/3 means that the same entry is used whether the space length is 2 T or 3 T. Further, as described more fully below, whether the tables within the group  238  are indexed by following space length or by leading space length can be made programmable. 
     Referring now to  FIG. 8B , an alternative implementation of parameter tables is depicted. While table  240  of  FIG. 8A  contains values for five different parameters within each table entry, more or fewer parameters can be stored within each table. For example, pairs of parameters may be defined by a table. In addition, parameters may be defined by their own individual table, as in  FIG. 8B . Individual tables  250 ,  252 ,  254 ,  256 , and  258  store parameters for parameters derfl, dtop, ttop, dtmp, and ttmp, respectively. 
     A table index register  260  can define how tables  250 ,  252 ,  254 ,  256 , and  258  are indexed to select a parameter. For instance, each table  250 ,  252 ,  254 ,  256 , and  258  may correspond to a bit within the table index register  260 . Each bit in the table index register  260  can determine whether the corresponding table indexes based upon following space length or leading space length. This increases the flexibility of the write strategy by allowing the indexing of each parameter or group of parameters to be altered programmatically. Bits within the table index register  260  may also control which length values correspond to which table entries. For instance, a bit may specify whether the rows of the table correspond to space lengths of 2 T, 3 T, 4 T, and 5 T+, respectively, or to 3, 4, 5, and 6 T+, respectively. 
     Referring now to  FIG. 9 , a detailed functional block diagram of an exemplary implementation of the write strategy module of  FIG. 5  is depicted. The write strategy system  194  includes a PLL (phase-locked loop) and clock recovery module  212 , a write pulse pattern lookup table  210 , a write strategy timing encoding module  214 , and a write strategy pulse generation module  216 . The PLL and clock recovery module  212  includes an analog PLL  300 , which further includes a voltage controlled oscillator (VCO)  302 . 
     The analog PLL VCO  302  generates multi-phase clocks that are separated by 45 degrees: vclk 0 , vclk 45 , vclk 90 , vclk 135 , vclk 180 , vclk 225 , vclk 270 , and vclk 315 . The clock with zero-degree phase shift, vclk 0 , is communicated to an N divider module  304 . The N divider module  304  divides vclk 0  by an integer N, where N is often a power of two. Dividing a clock by N means dividing its frequency by N, while its period is multiplied by N. vclk 0 /N is the channel bit clock; in other words, the frequency of vclk 0 /N is the same frequency as the channel data rate. 
     The N divider module  304  is used so that the voltage-controlled oscillator  302  does not have to vary across a wide range. The frequency variation of the VCO  302  can be limited because large changes in frequency are accomplished through dividing the frequency produced by the VCO  302 . An exemplary mapping between data rate and divisor N may be used as follows: 
     
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                    Data Rate 
                 N 
               
               
                   
                   
               
             
             
               
                   
                   8 MHz to 16 MHz 
                 32 
               
               
                   
                  16 MHz to 32 MHz 
                 16 
               
               
                   
                  32 MHz to 64 MHz 
                  8 
               
               
                   
                  64 MHz to 128 MHz  
                  4 
               
               
                   
                 128 MHz to 256 MHz 
                  2 
               
               
                   
                 256 MHz to 620 MHz  
                  1 
               
               
                   
                   
               
             
          
         
       
     
     The N divider module  304  may provide one or more divided clocks to a retiming module  306 . In the exemplary implementation of  FIG. 9 , the N divider module  304  receives instructions dictating the value of the divisor, N, and produces vclk 0 /N. The N divider module  304  communicates vclk 0 /N to the retiming module  306 , which removes jitter using vclk 0 , and outputs the retimed vclk 0 /N. The retimed vclk 0 /N is indicated with reference numeral  308 . The channel bit clock, vclk 0 /N, is communicated to a digital PLL module  310 . The digital PLL  310  also receives a wobble signal. An output of the digital PLL module  310  is communicated to the analog PLL module  300 . The N divider module  304  and retiming module  306  can also be included within the PLL and clock recovery module  212 . 
     The write pulse pattern lookup table  210  receives a bit stream of the data to be written to the optical media. The lookup table  210  also receives the channel bit clock vclk 0 /N. The appropriate pulse parameters, such as those depicted in the lookup table of  FIG. 7 , are selected and communicated to the write strategy timing encoding module  214 . The write strategy timing encoding module  214  receives vclk 0 /N and the undivided vclk 0 . The write strategy timing encoding module  214  communicates pulse parameters to a group of edge generators  312  within the write strategy pulse generation module  216 . 
     The edge generators  312  receive the multiple phases from the analog VCO  302  and the divided clocks  308 . The edge generators  312  each generate a generic pulse. These pulses are all communicated in parallel to pulse combining logic  314 , which combines the generic pulses into enable signals used to drive the laser driver shown in  FIG. 6  at  196 . The pulse combining logic  314  may use multiple phases from the analog VCO  302 , or it may use only vclk 0 . Clock phases not used by the pulse combining logic  314  do not need to be communicated to the pulse combining logic  314 . Operation of the pulse combining logic  314  was alluded to in  FIG. 4 , where various generic pulses were combined with logical XORs to create enable signals, and is described in more detail with respect to  FIGS. 10A and 10B . 
     Referring now to  FIG. 10A , a functional block diagram of the group of edge generators is depicted. In this exemplary implementation, there are eight edge generators  320 - 1 ,  320 - 2 ,  320 - 3 ,  320 - 4 ,  320 - 5 ,  320 - 6 ,  320 - 7 , and  320 - 8 . Edge generators  320 - 3  and  320 - 4  are edge generators of type B, while the remaining edge generators  320  are of type A. Type A generators generate an edge, in one implementation a rising edge, at a certain time dictated by incoming coarse and fine timing controls, P_CCTL[3:0] and P_INT[6:0], respectively. Generators of type A produce generic pulses such as pulse 1 _r  160  and pulse 1 _f  162 , shown in  FIG. 4 . The job of the timing encoding module  214  is then to translate the timing parameters, such as dtop and ttop, into coarse and fine timing controls that define where the rising edges of pulse 1 _r and pulse 1 _f will occur. 
     Generators of type B produce generic pulses such as pulse 2 _r  164  and pulse 2 _f  166  in  FIG. 4 . The coarse and fine timing controls, which the edge generator  320  receives from the timing encoding module  214 , define when the initial rising edge of the pulse will occur. The edge generator may then produce a falling edge after a time delay that is a multiple of T (the channel bit clock period). After another period T, the edge generator of type B may create a further rising edge, and after another time period T, a further falling edge. The number of edges created periodically by edge generators of type B is defined by mpcount. For instance, in  FIG. 4 , mpcount is four and so the edge generator producing pulse 2 _r and the edge generator producing pulse 2 _f each produce four periodic edges: two rising and two falling. 
     Each edge generator  320  receives the multiple phases of the voltage-controlled oscillator and also receives a pulse reset signal (pulse_rst). Operation of the pulse reset signal is depicted in  FIG. 4 . On the falling edge of pulse_rst  176 , each generic pulse returns back to zero level. In this implementation, pulse_rst  176  operates as a falling-edge-synchronized reset signal for each of the generic pulses. 
     Each edge generator  320  outputs its created generic pulse (denoted P 1  through P 8 ) to the pulse combining logic module  314 . The pulse combining logic module  314  then combines the generic pulses from the edge generators  320  into enable signals that are communicated to the laser driver. In this implementation, six enable signals, EN 2  through EN 7 , are depicted. The pulse combining logic  314  may include combinational and/or sequential circuitry. Greater or fewer number of enable signals may be created, and the pulse combining logic  314  may be programmable to allow creation of combinations of various numbers of generic pulses using various logic functions and/or transformations such as delays. 
     In one implementation, there are six intermediate values whose calculation can be programmed via six two-bit registers. These six intermediate values are named enable XORs. EN 2 _X 0 R, EN 3 _XOR, EN 4 _XOR, EN 5 _XOR, EN 6 _XOR, and EN 7 _XOR. Formation of each of the intermediate values is determined by the contents of a two-bit selection register. The following is an exemplary implementation, though more or less flexibility may be provided for. Generic pulses P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , P 7 , and P 8  may correspond to pulse 1   2    160 , pulse 1 _f  162 , pulse 2 _r  164 , pulse 2 _f  166 , pulse 3 _r  168 , pulse 3 _f  170 , erase_r  172 , and erase_f  174 , respectively, of  FIG. 4 . 
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 EN2_XOR_SEL[1:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 00 
                 P1 XOR P2 
               
               
                 01 
                 P7 XOR P2 
               
               
                 10 
                 P1 XOR P5 
               
               
                 11 
                 P7 XOR P5 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 EN3_XOR_SEL[1:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 00 
                 P3 XOR P4 
               
               
                 01 
                 P1 XOR P4 
               
               
                 10 
                 P3 XOR P6 
               
               
                 11 
                 P1 XOR P6 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 EN4_XOR_SEL[1:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 00 
                 P5 XOR P6 
               
               
                 01 
                 P7 XOR P6 
               
               
                 10 
                 P5 XOR P2 
               
               
                 11 
                 P7 XOR P2 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 EN5_XOR_SEL[1:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 00 
                 P7 XOR P8 
               
               
                 01 
                 P6 XOR P8 
               
               
                 10 
                 P7 XOR P1 
               
               
                 11 
                 P6 XOR P1 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 EN6_XOR_SEL[1:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 00 
                 P6 XOR P7 
               
               
                 01 
                 P5 XOR P7 
               
               
                 10 
                 P6 XOR P2 
               
               
                 11 
                 P5 XOR P2 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 EN7_XOR_SEL[1:0] 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 00 
                 (CK0_div2 XOR P8_div2 + NRZI * !P1) * !(P1 XOR P7) * 
               
               
                   
                 !(P7 * NRZI_DLY_1T) 
               
               
                 01 
                 (CK0_div2 XOR P8_div2 + NRZI * !P1 + P7 * 
               
               
                   
                 NRZI_DLY_1T) * !(PI XOR P7) 
               
               
                 10 
                 (CK0_div2 XOR P8_div2) * !NRZI * !NRZI_DLY_1T 
               
               
                 11 
                 (CK0_div2 XOR P8_div2) * !NRZI * !NRZI_DLY_1T +  
               
               
                   
                 P7 * NRZI_DLY_1T 
               
               
                   
               
             
          
         
       
     
     Based upon the above programming, EN 2 _XOR, for example, can be formed from one of four choices. If the selection bits are 00, EN 2 _XOR will be formed from the logical XOR of P 1  and P 2 , which are the generic pulses arriving from edge generators  320 - 1  and  320 - 2 , respectively. If the selection bits are 01, EN 2 _XOR will be formed from a logical XOR of P 7  and P 2 . Likewise, selection bits  10  create the logical XOR of P 1  and P 5 , while selection bits  11  select the XOR of P 7  and P 5 . Intermediate values EN 3 _XOR through EN 6 _XOR operate similarly. 
     The last intermediate value, EN 7 _XOR, is formed from more complicated logical expressions, which allows for the creation of more complex waveforms, such as pulsed erase waveforms. CK 0  is the channel bit clock, and CK 0 _Div 2  is the bit clock divided by two; i.e., half the frequency of CK 0 . P 8 _Div 2  is P 8  divided in frequency by two. In various implementations, P 8  can be generated as CK 0  with a programmable phase shift. In this way, when a divided P 8  is XOR&#39;d with a divided CK 0 , a square wave can be created. The duty cycle of the square wave is controlled by the amount of phase shift between P 8  and CK 0 . NRZI represents the incoming non-return-to-zero-inverted channel write bit stream. The exclamation point indicates a logical not, while _DLY — 1 T signifies a delay by a time of 1 T (one channel bit period). A graphical depiction of these waveforms is presented in  FIG. 17L . 
     Outputs of the pulse combining logic module  314  may be created from combinations of the intermediate values. In one implementation, there is a six-input summing module for each enable output. A crossbar switch can be placed between the intermediate values and the inputs of the six-input summing modules. Each six-input summing module is programmable to add any combination of its six inputs together. There may be an additional stage of logic that can invert the outputs prior to leaving the pulse combining logic module  314 . For example, in  FIG. 4 , polarity was reversed to produce the cooling enable, EN 5   128 . The pulse combining logic module  314  may also be programmable to output directly the non-return-to-zero-inverted input bit stream or the channel bit clock on any one of the enable outputs. 
     Referring now to  FIG. 10B , a functional block diagram of an exemplary implementation of the pulse combining logic  314  is presented. The pulse combining logic module  314  includes multiplexers  321 , XOR gates  322 , a cross-bar switch  323 , selective addition modules  324 , polarity inversion modules  325 , and output switching modules  326 . The pulse combining logic module  314  also includes a complex combination logic module  327 , which receives the non-return-to-zero-inverted write channel data stream and the channel bit clock (vclk 0 /N). In various implementations, the pulse combining logic module  314  receives eight generic pulse inputs and outputs six enable signals—greater or fewer numbers of inputs and outputs are possible. 
     The complex combination logic module  327  receives pulse  1 , pulse  7 , and pulse  8 , as indicated by the choices above for EN 7 _XOR_SEL[1:0]. The combination that the complex combination logic module  327  performs is determined by EN 7 _XOR_SEL. The output of the complex combination logic module  327  is communicated to the cross-bar switch  323 . Each multiplexer  321  has two inputs and communicates its output to a corresponding XOR module  322 . Outputs of the XOR modules  322  are communicated to inputs of the switch  323 . 
     The inputs to the multiplexers  321  are derived from the generic pulses arriving at the pulse combining logic module  314 . In this implementation, inputs of the multiplexers  321  match up with the enable select bits shown above. For example, EN 2 _XOR_SEL[1:0] selects whether P 1  or P 7  is XOR&#39;d with P 2  or P 5 . Therefore, one multiplexer  321  will have inputs of P 1  and P 7 , while the other multiplexer corresponding to that XOR gate  322  will have inputs of P 2  and P 5 . This pattern is repeated for the remaining multiplexers  321  and XOR gates  322 . The cross-bar switch  323  has six inputs and 36 outputs, six for each selective addition module  324 . The cross-bar switch  323  can route any input to any output. 
     Each selective addition module  324  can add any combination of its inputs, and the output is communicated to a polarity inversion module  325 . With binary values, addition is the equivalent of a logical OR operation. The polarity inversion module selectively inverts the polarity of the signal (useful for such enable signals as EN 5   128  in  FIG. 4 ). Polarity inversion is the equivalent of a logical NOT operation. The output of each polarity inversion module  325  is communicated to a corresponding output module  326 . The output module  326  may include an amplifier, and may also route some signal other than that received from the corresponding polarity inversion module  325 . For instance, an output module  326  may be programmed to output the bit clock (vclk 0 /N) or the write channel bit stream. 
     Referring now to  FIG. 11 , a functional block diagram of an exemplary implementation of the write strategy timing encoding module is presented. The purpose of the write strategy timing encoding module  214  is to produce coarse and fine timing controls for a set of edge generators (depicted in  FIG. 10A  at  312 ) from the parameters delivered by the lookup table  210 . In this exemplary implementation, there are eight edge generators and, therefore, eight sets of coarse and fine timing controls. Each set of coarse and fine timing controls may correspond to one of the generic pulses depicted in  FIG. 4  as pulse 1 _r, pulse 1 _f, pulse 2 _r, pulse 2 _f, pulse 3 _r, pulse 3 _f, erase_r, and erase_f. These eight generic pulses may be combined by the pulse combining logic  314  into a number of enable signals. 
     The write strategy timing encoding module  214  contains three encoders, encoder  1   330 , encoder  2   332 , and encoder  3   334 . Encoder  1   330  receives pulse parameters from the lookup table  210 , and transmits eight sets of parameters to encoder  2   332 , which transmits eight sets of parameters to encoder  3   334 . Encoder  3   334  outputs eight sets of coarse and fine timing controls to the eight edge generators  312  of  FIG. 10A . In this implementation, each of the encoders  330 ,  332 , and  334 , processes each set of parameters independently. In other words, encoder  1   330 , encoder  2   332 , and encoder  3   334  could each be represented as eight separate encoders, each responsible only for a single generated pulse. Because of this, operation of the encoders will be discussed with respect to a single set of timing controls, and operation will be substantially similar for the other seven sets. 
     The write strategy timing encoding module  214  converts the parameters from the lookup table  210  into coarse and fine timing parameters. For example, the time dtop (measured in units of T, the channel bit clock period) will be converted into coarse and fine timing parameters (such as P_CCTL 1  and P_INT 1 ) that define the rising edge of pulse 1 _r  160 , depicted in  FIG. 4 . A second set of coarse and fine timing parameters (such as P_CCTL 2  and P_INT 2 ) will define the rising edge of pulse 1 _f  162 . The rising edge of pulse 1 _f is determined by the sum of dtop and ttop. Encoder  1   330  is responsible for converting these parameters from the lookup table  210  into an initial set of timing parameters. 
     Encoder  1   330  operates in the channel bit clock domain and therefore receives vclk 0 /N. At each incoming clock cycle, encoder  1  will output a single enable bit, TD 1 , and a seven-bit phase group P — 1[6:0]. These signals refer to the edge that will be generated for pulse 1 _r  160 . If the rising edge of pulse 1 _r is to occur in the current clock cycle, TDI will have the value one for the current clock cycle. If the rising edge of pulse 1 _r  160  is not to occur in this clock cycle, TD 1  will be zero. The value of P — 1 determines when within this clock cycle the rising edge of pulse 1 _r will occur. 
     Encoder  2   332  receives information from encoder  1  in the channel bit clock domain and receives vclk 0 /N. Encoder  2  outputs data in the vclk 0  domain, which is at a frequency N times higher than the channel bit clock. Encoder  2   332  outputs a single enable bit TVCO_TD 1  and a seven-bit phase value P_INT 1 [6:0]. TVCO denominates that this signal is in the VCO clock domain (vclk 0 ), as opposed to the channel bit clock domain (vclk 0 /N). INT is an abbreviation for interpolator because the seven-bit P_INT 1  value will be used by a phase interpolator to place the edge. 
     Because TVCO_TD 1  is in the vclk 0  domain, encoder  2   332  will output a one on TVCO_TD 1  when an edge should occur during this vclk 0  cycle, and a zero otherwise. The P_INT 1  value determines where within the current vclk 0  cycle the edge should occur. Because there are N vclk 0  cycles within each bit clock cycle, the phase information P — 1 from encoder  1  is multiplied by N. This is discussed in more detail with respect to  FIG. 12 . 
     Encoder  3  operates in the vclk 0  domain, and, therefore, receives vclk 0 . Encoder  3   334  transmits P_INT 1  from encoder  2   332  unchanged. Encoder  3   334  also generates a coarse timing control value P_CCTL 1 [3:0]. The coarse timing control value selects one of four phases of the vclk signal, specifically, vclk 0 , vclk 90 , vclk 180 , and vclk 270 . The coarse timing control signal serves to gate the output of the phase interpolator because the phase interpolator may experience glitches as the fine timing control information changes from one setting to the next (the fine timing control settings can change for each mark written). In various implementations, P_CCTL 1 [3:0] may be formed from the binary decoding of P_INT 1 [6:5]. 
     Referring now to  FIG. 12 , a graphical depiction of operation of an exemplary write strategy timing encoding module is depicted. Four channel bit periods are shown in  FIG. 12 , the third being indicated by  360 . Within each bit period T are a number N of VCO clock cycles T VCO    362 . In this graphical depiction, the clock divider N is four. Therefore, there are four VCO cycles within each channel bit period T. A representative TD signal, as output from Encoder  1   330 , is shown at  364 . TD is zero for all channel periods but one, the channel period when the edge is desired. 
     Exemplary phase information output from Encoder  1  is depicted at  366 . The fine timing information  366  is asserted in the cycle  367  in which the edge is desired to be generated. The fine information may be sent starting in the first bit period so that the phase interpolator can receive the fine timing information as soon as possible to stabilize. In this example, the fine timing information is seven bits long, with the most significant bits being 01. 
     The single enable bit, TVCO_TD, output from Encoder  2  is depicted at  368 . TVCO_TD will be zero in all cycles except for the VCO clock cycle where the edge is desired. In VCO clock cycles when TD is zero, TVCO_TD must also be zero. Only in the channel bit clock cycle  360  where the edge is desired can TVCO_TD be one. Because there are four (2 2 ) T VCO  cycles in one bit period, the two most significant bits of the fine pulse information P — [6:0] determine in which T VCO  cycle the edge will occur within the chosen bit period. In this example, the two most significant bits are 01, the decimal value of one, which means that T VCO  cycle number one  367  will contain the edge (with T VCO  cycles 0, 1, 2 and 3). 
     The second encoder outputs fine phase interpolator information P_INT[6:0]. This phase information determines where within the T VCO  clock cycle  360  the edge will fall. Because the two most significant bits were used in selecting the T VCO  cycle, those digits are removed and the remaining bits are left-shifted by two. Therefore, the five least significant bits of P — [6:0] are now the five most significant bits of P_INT[6:0], and the two least significant bits are zero. The phase information P_INT[6:0] may be asserted as soon as the corresponding P — [6:0] phase information is received (the first T VCO  cycle), as shown in  FIG. 12 . 
     P_INT[6:0] is depicted in  FIG. 12  at  370  and is the same value when output from Encoder  2  or when output from Encoder  3 . The coarse timing control P_CCTL[3:0] output from Encoder  3  is depicted at  372 . In various implementations, this value is zero in all clock cycles except for either the clock cycle in which the edge will be generated or the clock cycle one before or after. The significance of P_CCTL is discussed in more detail with respect to  FIGS. 13 through 16 . 
     The edge generator receiving P_CCTL[3:0] generates a coarse timing control signal CTCTL. This signal has a rising edge at the appropriate phase clock, as determined by P_CCTL. The CTCTL  374  generated by an edge generator of type A may have a falling edge after a time of at least T VCO . The CTCTL  376  generated by an edge generator of type B will have additional edges, as determined by mpcount. Mpcount determines the total number of edges, including the initial rising edge. The edges are spaced apart by the period of the middle pulses. In the example shown in  FIG. 12 , this period is T, though other periods are possible, such as 2 T, 2.5 T, or 3 T. 
     The phase interpolator information P_INT[6:0] determines where within the CTCTL pulse the rising edge will occur. The rising edge will occur at the same time whether a generated pulse  378  is created by Edge Generator A or a generated pulse  380  is created by Edge Generator B. However, if Edge Generator B is used, further edges may be created as dictated by the corresponding CTCTL signal  376 . The rising edge generated in pulse  378  or  380  occurs at the next interpolated clock edge (as specified by P_INT[6:0]) after the corresponding CTCTL changes. 
     For a more detailed understanding of how Encoder  2  operates, a description is provided for each clock divider N selected from 1, 2, 4, 8, 16, and 32. If N is 1, then T=T VCO . Because T and T VCO  are the same, TVCO_TD=TD and P_INT[6:0]=P — [6:0]. If N is greater than 1, there are N T VCO  for each T, and T=N*T VCO . When an edge is desired within a bit clock period, TD=1 for that period. If N=2 p , P — [6, 5, . . . , (6−(p−1)}] is binary decoded to determine to which T VCO  cycle the edge belongs within the chosen bit clock period. The fine timing information is then P_INT[6:0]={P — [6−p], P — [6−(p+1)], . . . , P — [0], 0, . . . , 0]. In essence, the second encoder left-shifts the fine pulse timing information by log base  2  of the clock divider (filling shifted least significant bits with zeros), and outputs  1  (on TVCO_TD) during the appropriate T VCO  cycle period. 
     If N=2, T=2 T VCO . When an edge is desired within a particular clock cycle T, P — [6] is binary decoded to determine to which T VCO  the edge belongs within that T. For example, if the sequence of TD in five T cycles is 00100, there is an edge in the third T cycle. If P — [6] is 1, the edge will be generated in the second of the two T VCO  periods, and the TVCO_TD sequence for ten T VCO  cycles (five T cycles) should be 0000010000. If P —[ 6] is 0, the TVCO_TD sequence for ten T VCO  cycles should be 0000100000. The mapping from P — [6:0] to P_INT[6:0] is P_INT[6:0]={P — [5], P — [4], P — [3], P — [2], P — [1], 0}. 
     If N=4, T=4 T VCO . When an edge is desired within a particular T, P — [6, 5] is binary decoded to determine to which T VCO  the edge belongs within that T. The mapping is P_INT[6:0]={P — [4], P — [3], P — [2], P — [1], P — [0], 0, 0}. For example, if the sequence for TD in five T cycles is 00100, the twenty T VCO  cycles of TVCO_TD are determined by the decoding of binary P — [6, 5] according to the following table: 
     
       
         
               
               
             
           
               
                   
               
               
                 P_[6, 5] 
                 TVCO_TD sequence 
               
               
                   
               
             
             
               
                 00 
                 00000000100000000000 
               
               
                 01 
                 00000000010000000000 
               
               
                 10 
                 00000000001000000000 
               
               
                 11 
                 00000000000100000000 
               
               
                   
               
             
          
         
       
     
     If N=8, T=8 T VCO . When an edge is desired within a particular T, P — [6, 5, 4] is binary decoded to determine which T VCO  the edge belongs to within that T. The mapping is P_INT[6:0]={P — [3], P — [2], P — [1], P — [0], 0, 0, 0}. If N=16, T=16 T VCO . When an edge is desired within a particular T, P — [6, 5, 4, 3] is binary decoded to determine to which T VCO  the edge belongs within that T. The mapping is P_INT[6:0]={P — [2], P — [1], P — [0], 0, 0, 0, 0}. If N=32, T=32 T VCO  and the mapping is P_INT[6:0]={P — [1], P — [0], 0, 0. 0. 0.0}. 
     An exemplary implementation of Encoder  3  is explained in detail here. Assume that TVCO_TD has a sequence of 010 in three T VCO  cycles. If these cycles are named T VCO (i−1), T VCO (i), and T VCO (i+1), the TVCO_TD of 1 in cycle T VCO (i) indicates an edge should be generated in cycle T VCO (i). The operation of Encoder  3  is then described by the following exemplary table, which gives P_CCTL[3:0] for the three TVCO cycles (P_CCTL[3:0] is zero for all other cycles) based upon the value of P_INT[6:0]: 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
               
               
                   
                 T VCO    
                 T VCO   
                 T VCO   
               
               
                   
                 (i − 1) 
                 (i)  
                 (i + 1) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1110000 &lt; P_INT[6:0] ≦  
                 P_CCTL[3:0]: 
                 0000 
                 0100 
                 0000 
               
               
                 1111111 
                   
                   
                   
                   
               
               
                 1010000 &lt; P_INT[6:0] ≦  
                 P_CCTL[3:0]: 
                 0000 
                 0010 
                 0000 
               
               
                 1110000 
                   
                   
                   
                   
               
               
                 0110000 &lt; P_INT[6:0] ≦  
                 P_CCTL[3:0]: 
                 0001 
                 0000 
                 0000 
               
               
                 1010000 
                   
                   
                   
                   
               
               
                 0010000 &lt; P_INT[6:0] ≦  
                 P_CCTL[3:0]: 
                 1000 
                 0000 
                 0000 
               
               
                 0110000 
                   
                   
                   
                   
               
               
                 0000000 ≦ P_INT[6:0] ≦  
                 P_CCTL[3:0]: 
                 0100 
                 0000 
                 0000 
               
               
                 0010000 
               
               
                   
               
             
          
         
       
     
     Referring now to  FIG. 13A , a functional block diagram of an exemplary implementation of an edge generator of type A is depicted. The edge generator  420  includes a coarse timing generator of type A  422 , a phase interpolator  424 , an OR gate  426 , and a D flip-flop with synchronous reset  428 . The coarse timing generator  422  receives P_CCTL[3:0] from the write strategy timing encoding module. The coarse timing generator  422  also receives four voltage-controlled oscillator (VCO) clock phases; vclk 0 , vclk 90 , vclk 180 , and vclk 270 . P_CCTL[3:0] instructs the coarse timing generator  422  which clock phase to base its pulse upon. This pulse, the CTCTL (coarse timing control), is communicated to the OR gate  426 . 
     The OR gate  426  also receives an output of the D flip-flop  428 . In this way, once the output of the D flip-flop  428  has gone high, the OR gate  426  will cause the input of the D flip-flop  428  to always remain high. In order to reset the D flip-flop  428 , a pulse reset signal (pulse_rst) is provided and the D flip-flop  428  resets to zero upon the falling edge of the pulse_rst signal. The phase interpolator  424  receives the fine pulse timing information, P_INT[6:0], and the multiple phases of the VCO. The phase interpolator interpolates a clock, based upon P_INT[6:0], in between the multiple phases of the VCO, and outputs this fine clock signal to the clock input of the D flip-flop  428 . In this way, once CTCTL is high, the incoming rising edge of the next fine clock from the phase interpolator  424  will cause the output of the D flip-flop  428  to go high. 
     Referring now to  FIG. 13B , a functional block diagram of an exemplary implementation of an edge generator of type B is depicted. The edge generator  440  includes a coarse timing generator of type B  442 , a phase interpolator  444 , and a D flip-flop  446 . The coarse timing generator of type B  442  receives P_CCTL[3:0] from the write strategy timing encoding module. The coarse timing generator  442  also receives four VCO clock phases; vclk 0 , vclk 90 , vclk 180 , vclk 270 . P_CCTL[3:0] determines when a coarse timing control (CTCTL) signal will be communicated to the input of the D flip-flop  446 . 
     Once CTCTL is asserted by the coarse timing generator  442 , the next clock edge received by the D flip-flop  446  will cause the high CTCTL signal to be propagated to the output of the flip-flop  446 . The clock is communicated to the flip-flop  446  by the phase interpolator  444 . The phase interpolator  444  receives multiple phases of the VCO (such as the 45 degree separated phases described with respect to  FIG. 9 ). The phase interpolator  444  interpolates the output Fine_clk between the VCO phases received based upon interpolator information P_INT[6:0] received from the write strategy timing encoding module. 
     Referring now to  FIG. 14 , a graphical depiction of operation of an exemplary coarse timing generator is presented. The four phases of the voltage-controlled oscillator that are input to the coarse timing generator  422  are shown as vclk 0   480 , vclk 90   482 , vclk 180   484 , and vclk 270   486 . Coarse timing control signals CTCTL can be pulses with widths equal to the period of vclk 0 . The coarse timing control signal CTCTL  488  corresponding to vclk 0   480  is a pulse having a rising edge coincident with a rising edge of vclk 0 . Similarly. CTCTL  490  corresponding to vclk 90  has a rising edge coincident with a rising edge of vclk 90   490 . CTCTL  492  and CTCTL  493  correspond to vclk 180   492 , and CTCTL  494  corresponds to vclk 270   494 . 
     The desired CTCTL is chosen based upon when the pulse edge is desired. Because the CTCTL signal serves as the input to the D flip-flop  428  in  FIGS. 13 and 14 , the longer CTCTL is high before the desired edge (set-up time), and the longer it is high after the desired edge (hold time), the better the signal quality will be at the D flip-flop  428 . A CTCTL that straddles the desired edge equally on either side allows for equal setup and hold times. Depending on setup and hold time needs (if more setup time is needed than hold time, for example) of the D flip-flop  428 , and propagation delays to the inputs of the D flip-flop  428 , a CTCTL may be desired wherein the desired edge falls somewhere other than the middle of the CTCTL. 
     For equal setup and hold times, if the generic pulse edge is desired within an interval A demarcated in  FIG. 15  as  496 , a CTCTL based upon vclk 0  is desired. CTCTL  488 , based upon vclk 0 , corresponds to a P_CCTL of 0001. The value of P_CCTL may be asserted in the previous cycle to account for a synchronous latching delay of one clock cycle in implementations of the coarse timing generator such as is shown in  FIG. 15A . In other words, if the edge is desired in T VCO  cycle i, P_CCTL can be set to 0001 in T VCO  cycle i−1 (P_CCTL will be 0 in T VCO  cycle i). 
     If an edge is desired during time interval B, the CTCTL corresponding to vclk 90  can be selected using a P_CCTL of 0010. Likewise, a P_CCTL of 0100 will select the CTCTL corresponding to vclk  180 , beneficial for an edge in time period C 2 . If a P_CCTL of 0100 is asserted in the previous cycle, the CTCTL  492  is beneficial for an edge in time period C 1 . A P_CCTL of 1000 in the previous cycle will select the CTCTL  494  corresponding to vclk 270 , useful for an edge occurring in time period D. The CTCTLs depicted in  FIG. 14  are shown with two edges, corresponding to a CTCTL generated by coarse timing generator A or by a CTCTL generated by coarse timing generator B where mpcount is equal to two and the number of VCO clock cycles in one bit clock cycle is one. 
     Referring now to  FIG. 15A , a functional block diagram of an exemplary implementation of a coarse timing generator of type A is depicted. The coarse timing generator  520  receives vclk 0 , vclk 90 , vclk  180 , and vclk 270  from the voltage controlled oscillator (VCO)  300 . The coarse timing generator  520  includes a four-bit register  522 , four D flip-flops  524 , and a four-input OR gate  526 . The register  522  is clocked by vclk 0  and receives P_CCTL[3:0] from the write strategy timing encoding module  214 . Once the value of P_CCTL[3:0] is clocked into the register  522 , it is distributed to the D flip-flops  524 , with flip-flop  524 - 1  receiving the least significant bit,  524 - 2  receiving the second least significant bit,  524 - 3  receiving the second most significant bit, and  524 - 4  receiving the most significant bit. 
     The outputs of the D flip-flops  524  are communicated to the OR gate  526 . An output of the OR gate  526  is output from the coarse timing generator as the coarse timing control (CTCTL) signal. By definition, only one bit of P_CCTL[3:0] will be high at any one time, and therefore, only one output of the D flip-flops  524  will be high at a time. As soon as the output of one of the D flip-flops  524  goes high, the OR gate causes the output CTCTL to go high. Once the next value of P_CCTL[3:0] is clocked into the register  522 , it will be all zeros (by definition, only one value of P_CCTL[3:0] will be nonzero for each generated edge) and, therefore, the D flip-flop  524  that was responsible for the high value output from the OR gate  526  will fall to zero once the new zero value is clocked into the D flip-flop by its corresponding vclk phase. Because the vclk phases operate at a period of T VCO , the initial rising edge and falling edge will be separated by T VCO  as depicted in  FIG. 12  at  374 . 
     Referring now to  FIG. 15B , a functional block diagram of an exemplary implementation of a coarse timing generator of type B is depicted. The coarse timing generator  560  includes four D flip-flops  562 - 1 ,  562 - 2 ,  562 - 3 , and  562 - 4 , which receive vclk 0 , vclk 90 , vclk  180 , vclk 270  from the voltage controlled oscillator (VCO)  300 , respectively. Data inputs of the flip-flops  562 - 1 ,  562 - 2 ,  562 - 3 , and  562 - 4  are received from a register  564  as the zeroth, first, second, and third bits of the output of the register  564 , respectively. Outputs of each of the flip-flops  562  are communicated to a logical OR gate  566  whose output is CTCTL. 
     The coarse timing generator  560  also includes an OR gate  570 , an MTW counter  572 , an MP counter  574 , and three multiplexers, multiplexer A  576 , multiplexer B  578 , and multiplexer C  580 . The OR gate  570  has four inputs, each receiving one of the bits of P_CCTL[3:0] from the write strategy timing encoding module  214 . The output of the OR gate  570  is communicated to a selection input of multiplexer C  580 , a start input of MTW counter  572 , and a start input of MP counter  574 . WO serves as the clock for the register  564 , the write strategy timing encoding module  214 , and the MTW counter  572 . 
     The MTW counter  572  counts the number of VCO cycles in between each edge asserted on CTCTL. If there are N VCO clock cycles within each channel bit clock cycle, the value the MTW counter  572  would count to would be N, or starting from zero, would be N−1. For different write strategies, however, the CTCTL edges may be spaced at multiples of the channel bit period T, such as 2 T or 3 T. 
     This multiplier is called MTW, and the value the MTW counter must reach is N times MTW minus one (count starts from zero). Once two abstract pulses created from similar CTCTLs are XOR&#39;d, the multiple of T spacing of pulse edges will translate into the same multiple of T period for the generated middle pulses. To create a middle pulse period of 1 T, the waveform generated at CTCTL should have a period equal to 2 T. Once the MTW counter  572  reaches MTW*N-1, an output of the MTW counter  572  is asserted and the MTW counter  572  returns to zero and resumes counting. 
     The output of the MTW counter  572  serves as the clock of the MP counter  574  and as a selection input of multiplexer A  576 . MP counter  574  counts the number of edges in CTCTL which, once combined with a similar pulse, will create 2*mpcount edges (mpcount pulses). The value MP counter  574  counts to is therefore mpcount. The MTW counter  572  returns to zero in the clock cycle after the start signal is received, and begins counting from zero. MP counter  574  is a saturation counter, and once it reaches its target value, it remains at that value. An output of MP counter  574  is high once the target value has been reached. The output of MP counter  574  serves as a selection input of multiplexer B  578 , and as a stop signal for the MTW counter  572 . 
     The stop signal freezes the MTW counter  572  at the current count value, or alternately could return the count to zero. The stop signal is asserted once the number of pulses counted by MP counter  574  has reached the final value. Once this value is reached, power can be saved by preventing the MTW counter  572  from continuing to count and continuing to switch multiplexer A  576 . Multiplexer A  576  alternates between passing the current value of the register  564  and an inverted value of the register  564 . Input zero of multiplexer A  576  is received from the output of the register  564 , and input one of multiplexer A  576  is the bitwise inverse of the output of the register  564 . An output of multiplexer A  576  is received by multiplexer B  578  at input zero. Input one of multiplexer B  578  is the output of the register  564 . Multiplexer C  580  receives an output of multiplexer B  578  at input zero. Input one of multiplexer C  580  is P_CCTL[3:0], received from the write strategy timing encoding module  214 . 
     Multiplexer C  580  passes through the value selected by multiplexer B  578  unless one of the bits of P_CCTL[3:0] is asserted, in which case multiplexer C  580  passes the value of P_CCTL[3:0]. Multiplexer B  578  usually passes the output of multiplexer A  576 . Once the target value of the MP counter  574  is reached (meaning that all edges have been produced and the value of CTCTL should remain steady), multiplexer B  578  then passes the current value of the register  564 . This means that the value sorted in the register  564  will remain constant once the output of MP counter  574  has gone high; this will last until the next mark is generated, and a new non-zero P_CCTL[3:0] is received. 
     Multiplexer A  576  passes the current value of the register  564  unless the value of MTW counter  572  has reached its target count. MTW counter  572  reaches its target count after MTW*N clock cycles. This corresponds to the spacing desired for the edges of CTCTL. When the MTW counter  572  reaches its target count, and the output of the counter  572  selects the inverted input of multiplexer A  576 , the value in the register  564  is inverted. The MTW counter  572  then resumes counting at zero and its output, now low, selects the non-inverted input of multiplexer A  576 . In this way, the value in the register  564  is inverted each time MTW counter  572  reaches its target count. Because the multiplexer  566  only selects one flip flop, the inversion of the register  564  is seen as an edge on CTCTL. 
     Referring now to  FIG. 16A , a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 3, MTW of 1, and N of 4 is presented. The table  600  includes column  610 - 1 , containing consecutive VCO clock cycle numbers, displayed for reference. The table  600  also includes column  610 - 2 , which lists exemplary values of P_CCTL received from the write strategy timing encoding module  214 . These values are only representative and may be different based upon the output of the write strategy timing encoding module. In this implementation, however, P_CCTL will only be non-zero during one VCO clock cycle for any given mark, and only one bit of P_CCTL will be asserted in that non-zero clock cycle. 
     The first two rows of the table  600 , VCO cycles  1  and  2  show the coarse timing generator  560  at steady state. Column  610 - 3  contains the value of the register  564 . Column  610 - 4  is a representation of the value of CTCTL. CTCTL may not have the same clock phase as the other values shown in table  600 . Depending upon which bit of P_CCTL is set, the CTCTL may have a phase shift from vclk 0 . Column  610 - 4  depicts CTCTL. the output of the coarse timing generator  560 . Because MP count is 3, there should be three edge transitions, shown here at VCO cycles  4 ,  8 , and  12 . Because MTW is 1 and N is 4, there should be 4×1 clock cycles at each value. This is the case as clock cycles  4  through  7  are one, and clock cycles  8  through  11  are zero. Column  610 - 5  lists the start signal. This signal is output by the OR gate  570  and communicated to the start inputs of the counters  572  and  574 . 
     Column  610 - 6  includes two sub-columns, the internal count value of the MTW counter  572  and the output of the MTW counter  572 . It can be seen that the output of the MTW counter  572  is one once the target value of three is reached (cycles  7 ,  11 ,  15 , etc.), and zero otherwise. The count value begins at zero, continues to three and returns to zero until cycle  15 , when the stop signal is received. The stop signal is received from the output of MP counter  574 . At this point, the internal count value remains constant. 
     Column  610 - 6  includes two sub-columns, the internal count value of the MP counter  574  and the output of MP counter  574 . The count value of MP counter  574  increases by one each time the output of the MTW counter  572  goes high. Once the MP counter reaches its target value (in this case  3 , reached at cycle  15 ), the count value remains constant and the output goes high. Column  610 - 7  includes three sub-columns, the zero input, the one input, and the output of multiplexer A  576 . Column  610 - 8  includes three sub-columns, the zero input, the one input, and the output of multiplexer B  578 . Column  610 - 9  includes three sub-columns, the zero input, the one input, and the output of multiplexer C  580 . 
     Referring now to  FIG. 16B , a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 4, MTW of 1, and N of 4 is presented. Referring now to  FIG. 16C , a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 2, MTW of 2, and N of 4 is presented. Referring now to  FIG. 16D , a table depicting exemplary operation of the coarse timing generator of  FIG. 15B  for mpcount of 1 MTW of 3, and N of 4 is presented. It can be seen that MTW*N equals 12 and there are, therefore, 12 clock cycles in between edges, namely clock cycles  4  and  16 . 
     Referring now to  FIG. 17A , a timing diagram for an exemplary mark writing waveform for single-power pulse writing is depicted. A channel bit stream to be written to the optical media is depicted at  700 . A corresponding laser driver output waveform is depicted at  702 , and contains an erase power, P c , a first pulse power, P p1 , and a base power, P b . The laser driver output  702  may be formed from two incoming enable signals, EN 2   704  and EN 3   706 . The power level associated with EN 2   704  is P p1 -P b , while the power associated with EN 3  is P c -P b . 
     Referring now to  FIG. 17B , a timing diagram for an exemplary mark writing waveform for two-power pulse writing is depicted. A channel bit stream to be written to the optical media is depicted at  720 . A corresponding laser driver output waveform is depicted at  722 , and includes an erase power level, P c , a first pulse power, P p1 , a base power, P b , and a second pulse power, P p2 . The laser driver output  722  may be formed by three enable signals. EN 2   724 , EN 3   726 , and EN 4   728 . The power level associated with EN 2  is P p1 -P b . EN 3  is P p2 -P b , and EN 4  is P c -P b . 
     Referring now to  FIG. 17C , a timing diagram for an exemplary mark writing waveform for three-power pulse writing is depicted. A channel bit stream to be written to the optical media is depicted at  740 . A corresponding laser driver output waveform is depicted at  742 , and includes an erase power P c , a first pulse power P p1 , a base power P b , a second pulse power P P2 , and a third pulse power P p3 . The laser driver output  742  may be formed from a combination of enable signals: EN 2   744 , EN 3   746 , EN 4   748 , and EN 5   750 . The power level associated with EN 2  is P p1 -P b , EN 3  is P p2 -P b , EN 4  is P p3 -P b , and EN 5  is P c -P b . 
     Referring now to  FIG. 17D , a timing diagram for an exemplary mark writing waveform for single-power pulse writing with cooling is depicted. A channel bit stream to be written to the optical media is depicted at  760 . A corresponding laser driver output waveform is depicted at  762 , and includes an erase power, P c , a first pulse power, P p1 , a base power. P b , and a cooling power, P c1 . The laser driver output  762  may be formed by a combination of enable signals EN 2   764 , EN 3   766 , and EN 4   768 . The power level associated with EN 2  is P p1 -P b , EN 3  is P c -P b , and EN 4  is P b -P c1 . If the cooling power were greater than the base power, the power associated with EN 4  would be P c1 -P b , and the waveform of EN 4   768  would be inverted from that shown in  FIG. 17D . 
     Referring now to  FIG. 17E , a timing diagram for an exemplary mark writing waveform for two-power pulse writing with cooling is depicted. A channel bit stream to be written to the optical media is depicted at  780 . A corresponding laser driver output waveform is depicted at  782 , including an error power, P c , a first pulse power, P p1 , a base power. P b , a second pulse power, P p2 , and a cooling power, P c1 . The laser driver output  782  may be formed from a combination of enable signals EN 2   784 , EN 3   786 , EN 4   788 , and EN 5   790 . EN 2   784  may be formed by the logical addition of two pulses, and is associated with power P p1 -P b . EN 3   786  is associated with P p2 -P b , EN 4   788  with P b  P c1 , and EN 5  with P c -P b . If the cooling power were greater than the base power, the power level associated with EN 4  would be P c1 -P b , and the waveform  788  would be inverted. 
     Referring now to  FIG. 17F , a timing diagram for an exemplary mark writing waveform for single-power level writing is depicted. A channel bit stream to be written to the optical media is depicted at  800 . A corresponding laser driver output waveform is depicted at  802 , and includes a base power level, P b , and a first pulse power, P p1 . The laser driver output  802  may be produced from an enable signal EN 2   804 , which is associated with power P p1 -P b . 
     Referring now to  FIG. 17G , a timing diagram for an exemplary mark writing waveform for two-power level writing is depicted. A channel bit stream to be written to the optical media is depicted at  820 . A corresponding laser driver output waveform is depicted at  822 , and includes a base power level, P b , a first pulse power, P p1 , and a second pulse power, P p2 . The laser driver output  822  may be created from enable signals EN 2   824  and EN 3   826 . The power level associated with EN 2  is P p2 -P p1 , while the power level associated with EN 3  is P p1 -P b . 
     Referring now to  FIG. 17H , a timing diagram for an exemplary mark writing waveform for three-power level writing is depicted. A channel bit stream to be written to the optical media is depicted at  840 . A corresponding laser driver output waveform is depicted at  842  and includes a base power, P b , a first pulse power, P p1 , a second pulse power, P p2 , and a third pulse power, P p3 . The laser driver output  842  may be formed from enable signals EN 2   844 , EN 3   846 , and EN 4   848 . The power level corresponding to EN 2  is P p2 -P p1 , EN 3  with P p3 -P p1 , and EN 4  with P p1 -P b . 
     Referring now to  FIG. 17I , a timing diagram for an exemplary mark writing waveform for single-power level writing with cooling is depicted. A channel bit stream to be written to the optical media is depicted at  860 . A corresponding laser driver output waveform is depicted at  862 , and includes a base power, P b , a first pulse power, P p1 , and a cooling power, P c1 . The base power may or may not be equal to the read power, P read . The laser driver output  862  may be formed from enable signals EN 2   864  and EN 3   866 . The power level associated with EN 2  is P p1 -P b , while the power level associated with EN 3  is P b -P c1 . If the cooling power were greater than the base power, then the power level associated with EN 3  could be P p1 -P b , and the waveform  866  would be inverted from that shown in  FIG. 17I . 
     Referring now to  FIG. 17J , a timing diagram for an exemplary mark writing waveform for two-power level writing with cooling is depicted. A channel bit stream to be written to the optical media is depicted at  880 . A corresponding laser driver output waveform is depicted at  882 , and includes a base power, P b , a first pulse power, P p1 , a second pulse power. P p2 , and a cooling power, P p1 . The laser driver output  882  may be formed from enable signals EN 2   884 , EN 3   886 , and EN 4   888 . The power level associated with EN 2  is P p1 -P p1 , EN 3  is P p1 -P b , and EN 4  is P b -P c1 . Again, if P p1  is greater than P b , the power level associated with EN 4  would be P p1 -P b , and the waveform  888  would be inverted. 
     Referring now to  FIG. 17K , a timing diagram for an exemplary mark writing waveform for three-power level writing with cooling is depicted. A channel bit stream to be written to the optical media is depicted at  900 . A corresponding laser driver output waveform is depicted at  902 . The laser driver output  902  includes a base power, P b , a first pulse power, P p1 , a second pulse power, P p1 , a third pulse power, P p3 , and a cooling power. P c1 . The laser driver output  902  may be formed from enable signals EN 2   904 , EN 3   906 . EN 4   908 , and EN 5   910 . The power level associated with EN 2  is P p1 -P p , EN 3  is P p3 -P p1 , EN 4  is P p1 -P b , and EN 5  is P b -P c1 . 
     Referring now to  FIG. 17L , a timing diagram for an exemplary mark writing waveform for single-power pulse writing with cooling and pulsed erase is depicted. A channel bit stream to be written to the optical media is depicted at  920 . A corresponding laser driver output waveform is depicted at  921 . The shaded areas  922 - 1  and  922 - 2  indicate that the laser driver output  921  may or may not include the shaded area. The laser driver output  921  includes a base power, P b , a first pulse power, P p1 , a cooling power, P p1 , a first erase power, P c1 , and a second erase power, P c2 . The laser driver output  921  may be created from enable signals EN 2   923 , EN 3   924 , EN 4   925 , and EN 5   934 . 
     EN 2   923  can be formed from the logical sum of three generic pulses, and is associated with power P p1 -P b . EN 3   924  is associated with P c1 -P b , EN 4   925  with P b -P c1 , and EN 5   934  with P p1 -P. Based upon register settings, one of four EN 5 s may be chosen:  934 - 1 ,  934 - 2 ,  934 - 3 , and  934 - 4 . Enable choices  934 - 1  and  934 - 2  each have a third pulse that creates the shaded portion  922 - 1  in the laser driver output  921 . The second and fourth choices of EN 5 ,  934 - 2  and  934 - 4 , have a second to last pulse that is wider, corresponding to the shaded portion  922 - 2  of the laser driver output  921 . The choice between EN 5 s  934  may be made based upon the type of optical media, and can be determined during calibration. 
     To visually demonstrate an exemplary calculation of EN 5 s  934  based on expressions given above, various waveforms are presented. CK 0 _div 2   926  is the channel bit clock divided in frequency by 2. P 8 _div 2   927  is the eighth generic pulse, P 8 , divided in frequency by 2. In various implementations, P 8  is programmed to include a phase-shifted version of the channel bit clock. The logical XOR of CK 0 _div 2  and  926  P 8 _div 2   927  is represented at  928 . The NRZI channel bit stream, delayed by one bit time period is depicted at  929 . The inverse of the NRZI channel bit stream is depicted at  930 . The first generic pulse, P 1 , is depicted at  931 . P 1   931  may correspond to pulse 1 _r  160  of  FIG. 4 . The seventh generic pulse, P 7 , is depicted at  932 . P 7  may correspond to eraser  172  of  FIG. 4 . 
     Referring now to  FIG. 17M , a timing diagram for an exemplary mark writing waveform for variable-power level writing is depicted. A channel bit stream to be written to the optical media is depicted at  940 . A corresponding laser driver output waveform is depicted at  942 . Laser driver output  942  includes a shaded region  944  to indicate that the shaded region may or may not be present in a given laser driver output waveform. The laser driver  942  may be created from enable signals EN 2   946 , EN 3   948 , and EN 4   950 . The laser driver output  942  includes a base power, P b , a first pulse power, P p1 , a cooling power. P c1 , and a 3 T width power increment, dPw 3 . 
     EN 3   948  may be created from the logical addition of two generic pulses, and is associated with power P p1 -P b . EN 4   950  can be formed from the inversion of the logical sum of two generic pulses, and is associated with power P b -P c1 . If the cooling power were greater than the base power, the waveform of EN 4   950  would be inverted from that shown, and could be formed from the logical addition of two generic pulses. EN 2   946  is associated with power dPw 3 . The pulse EN 2   946  can be programmed so that it is only present when writing a mark of width 3 T. When present, EN 2   946  causes the shaded area  944  of the laser driver output to be asserted, and, therefore, the first pulse power will be P p1 +dPw 3 , not P p1 . Similar provision can be made for different power levels required by different mark widths, different space widths, or other suitable factors. 
     Referring now to  FIG. 18 , a functional block diagram of an exemplary optical media system incorporating a write strategy implementation according to the principles of the present invention is presented. The system  970  includes a wired or wireless host  972  that communicates with a control module  974  via an interface  976 . The controller  974  communicates with an optical media assembly  978 . The controller  974  includes a control module  980  that communicates with the interface  976 , a volatile memory  981 , a non-volatile memory  982 , a processor  983 , a scrambler  984 , a timer  985 , a codec processor  986 , a video DSP (Digital Signal Processor)  987 , an audio DSP  988 , a spindle/FM (Feed Motor) driver  989 , and a read/write channel module  990 . 
     The read/write channel module  990  includes a write strategy implementation according to the principles of the present invention, and a series of DACs (Digital to Analog Converters) that communicate signals to a laser driver  991  within the optical media assembly  978 . The read/write channel module  990  receives signals from a preamplifier  992  within the optical media assembly  978 . The spindle/FM driver  989  controls a spindle motor  993  and a feed motor  994  within the optical media assembly  978 . An optical read/write device  996  receives signals from the feed motor  994  and the laser driver  991 , and communicates signals to the preamplifier  992 . 
     The optical media assembly  978  also includes an optical media platter  998  that stores data optically. The platter  998  is rotated by the spindle motor, schematically shown at  993 . The spindle motor  993  rotates the optical media platter  998  at a controlled and/or variable speed during read/write operations. The optical read/write device  996  moves relative to the optical media platter  998  to read and/or write data to/from the optical media platter  998 . The optical read/write device  996  typically includes a laser and an optical sensor. 
     Volatile memory  981  functions as a buffer, and may employ SDRAM (Synchronous Dynamic Random Access Memory) or other types of low-latency memory. Non-volatile memory  982 , such as flash memory, can be used for data relating to optical media write formats and/or other non-volatile control code. Additionally, the non-volatile memory  982  may include write pulse pattern constants that serve as a starting point when calibrating the look-up table used by the write strategy implementation. The processor  983  performs data and/or control processing related to the operation of the optical media system  970 . The processor  983  may also perform decoding of copy protection and/or compression/decompression as needed. 
     During write operations, the read/write channel module  990  encodes the data to be written by the optical read/write device  996 . The read/write channel module  990  processes the signals for reliability purposes and may apply, for example, ECC (Error-Correcting Code), RLL (Run Length Limited) encoding, and the like. During read operations, the read/write channel module  990  converts an analog output of the optical read/write device  996  to a digital signal. A converted signal is then detected and decoded by known techniques to recover the data that was written on the optical media. 
     The codec module  986  encodes and/or decodes video, such as MPEG formats. Audio and/or video DSPs  242  and  244  perform audio and video signal processing, respectively. The optical read/write device  996  is directed at grooves and/or lands containing marks and spaces. During write operations, the optical read/write device  996  may use a laser to heat a die layer on the optical media platter  998 . If the die is heated to one temperature, the die is transparent and represents one binary digital value. If the die is heated to another temperature, the die is opaque and represents the other binary digital value. Other techniques for writing optical media may also be employed. 
     The spindle/FM driver  989  controls the spindle motor  993 , which controllably rotates the optical media platter  998 . The spindle/FM driver  989  also generates control signals that position the feed motor  994 , for example, using a voice coil actuator, a separate motor, or any other suitable actuator. The feed motor  994  typically moves the optical read/write device  996  radially relative to the optical media platter  998 . The preamplifier  992  amplifies analog read signals from the optical read/write device  996 . 
     Portions of the optical media system  970  may be implemented by one or more integrated circuits (IC) or chips. For example, the processor  983  and control module  980  may be implemented by a single chip. The spindle/FM driver  989  and/or the read/write channel module  990  may also be implemented by the same chip as the processor  983  control module  980 , and/or by additional chips. Most of the optical media system  970 , other than the optical media assembly  978 , may alternatively be implemented as a system-on-chip (SOC). 
     Referring now to  FIGS. 19A-19D , various exemplary implementations of the present invention are shown. Referring now to  FIG. 19A , the present invention can be implemented in a digital versatile disc (DVD) drive  1000 . A signal processing and/or control circuit  1002  and/or other circuits (not shown) in the DVD drive  1000  may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium  1006 . The present invention may be used to control a laser used in reading and writing from optical media of the optical storage medium  1006 . In some implementations, the signal processing and/or control circuit  1002  and/or other circuits (not shown) in the DVD drive  1000  can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive. 
     The DVD drive  1000  may communicate with an output device (not shown) such as a computer, television, or other device via one or more wired or wireless communication links  1007 . The DVD drive  1000  may communicate with mass data storage  1008  that stores data in a nonvolatile manner. The mass data storage  1008  may include a hard disk drive (HDD). The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The DVD drive  1000  may communicate with memory  1009  such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. 
     Referring now to  FIG. 19B , the present invention can be implemented in a high definition television (HDTV)  1020 . The HDTV  1020  receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display  1026 . In some implementations, a signal processing circuit and/or control circuit  1022  and/or other circuits (not shown) of the HDTV  1020  may process data, perform coding and/or encryption, perform calculations, format data, and/or perform any other type of HDTV processing that may be required. 
     The HDTV  1020  may communicate with mass data storage  1027 , which stores data in a nonvolatile manner such as optical and/or magnetic storage devices. The present invention may be implemented in an optical storage device of the mass data storage  1027 . The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The HDTV  1020  may be connected to memory  1028  such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV  1020  also may support connections with a WLAN via a WLAN network interface  1029 . 
     Referring now to  FIG. 19C , the present invention can be implemented in a set top box  1040 . The set top box  1040  receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display  1046  such as a television and/or monitor and/or other video and/or audio output devices. Signal processing and/or control circuits  1044  and/or other circuits (not shown) of the set top box  1040  may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function. 
     The set top box  1040  may communicate with mass data storage  1048 , which stores data in a nonvolatile manner. The mass data storage  1048  may include optical and/or magnetic storage devices; for example, hard disk drives HDD and/or DVDs. The present invention may be implemented in a DVD storage device. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The set top box  1040  may communicate with memory  1050  such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The set top box  1040  also may support connections with a WLAN via a WLAN network interface  1052 . 
     Referring now to  FIG. 19D , the present invention can be implemented in a media player  1060 . [ADAPT THIS SENTENCE TO DESCRIBE HOW THE INVENTION IS IMPLEMENTED IN THE HDD . . . The present invention may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified in  FIG. 9G  at  1062 , a WLAN interface, mass data storage of the media player  1060  and/or a power supply  503 .] In some implementations, the media player  1060  includes a display  1064  and/or a user input  1066  such as a keypad, touchpad, and the like. In some implementations, the media player  1060  may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons, and/or a point-and-click interface via the display  1064  and/or user input  1066 . The media player  1060  further includes an audio output  1068  such as a speaker and/or audio output jack. Signal processing and/or control circuits  1062  and/or other circuits (not shown) of the media player  1060  may process data, perform coding and/or encryption, perform calculations, format data, and/or perform any other media player function. 
     The media player  1060  may communicate with mass data storage  1070  that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. The present invention may be implemented in an optical storage device. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The media player  1060  may be connected to memory  1074  such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The media player  1060  also may support connections with a WLAN via a WLAN network interface  1076 . Still other implementations in addition to those described above are contemplated. 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.