Abstract:
A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an i th  sense amplifier layout region among the sense amplifier layout regions. An i th  bit line among the (N+1−i) bit lines and an i th  complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the i th  sense amplifier layout region. The values N and i are natural numbers and i&gt;=1 and &lt;=N.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0081061 filed on Aug. 20, 2010, the disclosure of which is incorporated by reference in its entirety herein. 
     
    
     BACKGROUND 
       [0002]    Embodiments of the present inventive concept relate to a bit line sense amplifier, and more particularly, to a bit line sense amplifier layout array, a layout method and apparatuses having the array. 
         [0003]    In a memory device, data stored in a memory cell can be sensed and amplified by using a bit line sense amplifier. Pitch is a measure of the space in between bit lines connecting adjacent memory cells. The pitch of bit lines of the memory cells is reduced as the size of the memory device is reduced. 
         [0004]    However, when the pitch of the bit line has been reduced significantly, it can be difficult to design a layout for a bit line sense amplifier. 
       SUMMARY 
       [0005]    According to an exemplary embodiment of the present inventive concept, a bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. In an i th (1≦i≦N) sense amplifier layout region among the sense amplifier layout regions, (N+1−i) bit lines and i complementary bit lines are arranged. The i th  bit line among the (N+1−i) bit lines and an i th  complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the i th  sense amplifier layout region. In at least one exemplary embodiment, N is 4. 
         [0006]    The i th  bit line may be arranged from a first sense amplifier layout region among the sense amplifier layout regions to the i th  sense amplifier layout region, and the i th  complementary bit line may be arranged from a N th  sense amplifier layout region among the sense amplifier layout regions to the i th  sense amplifier layout region. 
         [0007]    The bit line sense amplifier layout array may be an open bit line type. Each of the bit lines and each of the complementary bit lines may be arranged in zigzag. Each of the N sense amplifier layout regions may be formed in a word line direction. 
         [0008]    An exemplary embodiment of the present inventive concept provides a method for manufacturing a bit line sense amplifier layout, including forming N sense amplifier layout regions each lying adjacent each other, forming a sense amplifier in each of the N sense amplifier layout regions, forming (N+1−i) bit lines and i complementary bit lines in an i(1≦i≦N) th  sense amplifier layout region among the (1*N) sense amplifier layout regions, and connecting an i th  bit line among the (N+1−i) bit lines and an i th  complementary bit line among the i complementary bit lines to a sense amplifier formed in the i th  sense amplifier layout region. 
         [0009]    According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a first memory cell array, a second memory cell array, and a bit line sense amplifier block arranged between the first memory cell array and the second memory cell array. 
         [0010]    The bit line sense amplifier block may include a bit line sense amplifier array including N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. In an i(1≦i≦N) th  sense amplifier layout region among the sense amplifier layout regions, (N+1−i) bit lines extended from the first memory cell array and i complementary bit lines extended from the second memory cell array are arranged. An i th  bit line among the (N+1−i) bit lines and an i th  complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the i th  sense amplifier layout region. 
         [0011]    An exemplary embodiment of the present inventive concept is directed to a semiconductor system, including the said semiconductor device and a processor for controlling an operation of the semiconductor device. 
         [0012]    The semiconductor system may be embodied in a mobile communication device such as a cellular phone, a smart phone, a laptop computer, a tablet PC, etc. 
         [0013]    An exemplary embodiment of the present inventive concept is directed to a memory module, including the said semiconductor device and a semiconductor substrate where the semiconductor device is mounted. 
         [0014]    An exemplary embodiment of the present inventive concept is directed to a semiconductor system, including a memory module where the said semiconductor device is mounted, a socket where the memory module may be inserted, and a processor for controlling an operation of the semiconductor device mounted on the memory module through the socket. 
         [0015]    The memory module may be a Single In-Line memory module (SIMM) or a Dual In-Line memory module (DIMM). As an example, the semiconductor system may be a personal computer. 
         [0016]    According to an exemplary embodiment of the inventive concept, a bit line sense amplifier array includes a plurality of adjacent sense amplifier layout regions, where each region includes a sense amplifier and a plurality of bit lines and a plurality of complementary bit lines. Distinct pairs of the bit lines and complementary bit lines are connected to a sense amplifier of a corresponding one of the regions. A total count of the bit lines located in each region is less than a total count of the bit lines located in a preceding region and a total count of the complementary bit lines located each region is greater than a total count of the bit lines in a preceding region. 
         [0017]    One of a bit line and a complementary bit line of a corresponding one of the pairs may include a zigzag shaped part that connects to the corresponding sense amplifier. The regions, the bit lines, and the complimentary bit lines may number  4 . 
         [0018]    A part of one of the complementary bit lines may be located in the first region adjacent two of the bit lines, and a part of another complementary bit line may be located adjacent only one of the bit lines in the last region. A part of one of the bit lines may be located in the second region adjacent another bit line and a complementary bit line, and another part of the one bit line located in the third region may be adjacent the complementary bit line and another complementary bit line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    The present inventive concept will become apparent and more readily appreciated from the following description of the exemplary embodiments, taken in conjunction with the accompanying drawings of which: 
           [0020]      FIG. 1  shows a block diagram of a memory device including a bit line sense amplifier layout array according to an exemplary embodiment of the inventive concept; 
           [0021]      FIG. 2  shows layout patterns of the bit line sense amplifier array illustrated in  FIG. 1  according to an exemplary embodiment of the inventive concept; 
           [0022]      FIG. 3  shows a detailed diagram of layout patterns of the bit line sense amplifier array illustrated in  FIG. 2  according to an exemplary embodiment of the inventive concept; 
           [0023]      FIG. 4  shows a plurality of bit line sense amplifiers arranged in a layout of the bit line sense amplifier array illustrated in  FIG. 2  according to an exemplary embodiment of the inventive concept; 
           [0024]      FIG. 5  shows a circuit diagram of a bit line sense amplifier illustrated in  FIG. 4  according to an exemplary embodiment of the inventive concept; 
           [0025]      FIG. 6  shows a plurality of bit line sense amplifiers arranged in a layout of the bit line sense amplifier array illustrated in  FIG. 2  according to an exemplary embodiment of the inventive concept; 
           [0026]      FIG. 7  shows an exemplary memory module including a memory device illustrated in  FIG. 1 ; 
           [0027]      FIG. 8  shows a block diagram of an exemplary memory system including the memory module illustrated in  FIG. 7 ; 
           [0028]      FIG. 9  shows an exemplary embodiment of a memory system including the memory device illustrated in  FIG. 1 ; 
           [0029]      FIG. 10  shows an exemplary embodiment of a memory system including the memory device illustrated in  FIG. 1 ; and 
           [0030]      FIG. 11  is a flowchart for a method of manufacturing a bit line sense amplifier layout according to an exemplary embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    Reference will now be made in detail to exemplary embodiments of the present inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. 
         [0032]      FIG. 1  shows a block diagram of a memory device including a bit line sense amplifier layout array according to an exemplary embodiment of the inventive concept, and  FIG. 2  shows layout patterns of the bit line sense amplifier array illustrated in  FIG. 1  according to an exemplary embodiment of the inventive concept. 
         [0033]    Referring to  FIGS. 1 and 2 , the memory device  10  includes a plurality of memory cell arrays  30  and  40 , a row decoder  50 , a bit line sense amplifier block  60 , and an input/output buffer  120 . 
         [0034]    The bit line sense amplifier layout array  100  according to an exemplary embodiment of the present inventive concept may be applied to a volatile memory device or a non-volatile memory device. The array  100  may be applied to memory devices, which use an open bit line sense amplification scheme. 
         [0035]    For convenience of explanation, a layout of four bit lines BL 1  to BL 4  and four complementary bit lines BL 1 B to BL 4 B is discussed below with reference to  FIGS. 1 and 2 . 
         [0036]    The first memory cell array  30  includes a plurality of memory cells MC each connected to each of a plurality of word lines WL 11  to WL 1   n  and each of a plurality of bit lines. 
         [0037]    The second memory cell array  40  includes a plurality of memory cells MC each connected to a plurality of word lines WL 21  to WL 2   n  and a plurality of bit lines. 
         [0038]    The row decoder  50  may decode row addresses and drive at least one of a plurality of the word lines WL 11  to WL 1   n  of the first memory cell array  30  selectively according to a decoding result. 
         [0039]    Further, the row decoder  50  may decode row addresses and drive at least one of a plurality of word lines WL 21  to WL 2   n  of the second memory cell array  40  selectively according to a decoding result. 
         [0040]    The bit line sense amplifier block  60  is located between the first memory cell array  30  and the second memory cell array  40 . The bit line sense amplifier block  60  includes a plurality of bit line sense amplifier layout arrays  100 . 
         [0041]    During a read operation, the input/output buffer  120  outputs read data output from the bit line sense amplifier block  60  to an input/output data bus. 
         [0042]    Referring to  FIGS. 1 and 2  again, since each unit bit line sense amplifier layout array (Unit BLSA Array) has the same structure, only an operation of a first bit line sense amplifier array  100  is discussed below. 
         [0043]    The bit line sense amplifier layout array  100  includes (1*N) bit line sense amplifier layout regions SR 1  to SR 4  each arranged adjacently in the same direction. It is assumed that N is 4 in the following example merely for ease of discussion. For example, in alternate embodiments of the present inventive concept, N may be less than 4 or greater than 4. 
         [0044]    Each of the bit line sense amplifier layout regions SR 1  to SR 4  includes a corresponding one of sense amplifiers BLSA 1  to BLSA 4 . A circuit that forms each of the sense amplifiers BLSA 1  to BLSA 4  may be modified variously. Each of the sense amplifiers BLSA 1  to BLSA 4  is connected to a pair of corresponding bit lines (e.g., a bit line and a complementary bit line). 
         [0045]    In the first sense amplifier layout region SR 1 , a first bit line BL 1 , a first complementary bit line BL 1 B, a second bit line BL 2 , a third bit line BL 3 , and a fourth bit line BL 4  are arranged. For example, part of the bit line BL 1 , part of the first complementary bit line BL 1 B, part of the second bit line BL 2 , part of the third bit line BL 3 , and part of the fourth bit line BL 4  may be located within region SR 1 . 
         [0046]    The first bit line BL 1  is connected to one of two nodes of a first sense amplifier BLSA 1  through a first contact CT 1 , and a first complementary bit line BL 1 B is connected to the other of the two nodes of the first sense amplifier BLSA 1  through a second contact CT 1 B. Accordingly, during a sense amplification operation, the first sense amplifier BLSA 1  may sense and amplify a voltage difference between the first bit line BL 1  and the first complementary bit line BL 1 B. 
         [0047]    In the second sense amplifier layout region SR 2 , a first complementary bit line BL 1 B, a second bit line BL 2 , a second complementary bit line BL 2 B, a third bit line BL 3 , and a fourth bit line BL 4  are arranged. For example, part of the first complementary bit line BL 1 B, part of the second bit line BL 2 , part of the second complementary bit line BL 2 B, part of the third bit line BL 3 , and part of the fourth bit line BL 4  may be located within the region SR 2 . 
         [0048]    The second bit line BL 2  is connected to one of two nodes of a second sense amplifier BLSA 2  through a third contact CT 2 , and a second complementary bit line BL 2 B is connected to the other of the two nodes of the second sense amplifier BLSA 2  through a fourth contact CT 2 B. Accordingly, during a sense amplification operation, the second sense amplifier BLSA 2  may sense and amplify a voltage difference between the second bit line BL 2  and the second complementary bit line BL 2 B. 
         [0049]    In the third sense amplifier layout region SR 3 , a first complementary bit line BL 1 B, a second complementary bit line BL 2 B, a third bit line BL 3 , a third complementary bit line BL 3 B, and a fourth bit line BL 4  are arranged. For example, part of the first complementary bit line BL 1 B, part of the second complementary bit line BL 2 B, part of the third bit line BL 3 , part of the third complementary bit line BL 3 B, and part of the fourth bit line BL 4  may be located within the SR 3  region. 
         [0050]    The third bit line BL 3  is connected to one of two nodes of a third sense amplifier BLSA 3  through a fifth contact CT 3 , and a third complementary bit line BL 3 B is connected to the other of the two nodes of the third sense amplifier BLSA 3  through a sixth contact CT 3 B. Accordingly, during a sense amplification operation, the third sense amplifier BLSA 3  may sense and amplify a voltage difference between the third bit line BL 3  and the third complementary bit line BL 3 B. 
         [0051]    In the fourth sense amplifier layout region SR 4 , a first complementary bit line BL 1 B, a second complementary bit line BL 2 B, a third complementary bit line BL 3 B, a fourth bit line BL 4 , and a fourth complementary bit line BL 4 B are arranged. For example, part of the first complementary bit line BL 1 B, part of the second complementary bit line BL 2 B, part of the third complementary bit line BL 3 B, part of the fourth bit line BL 4 , and part of the fourth complementary bit line BL 4 B may be located within the SR 4  region. 
         [0052]    The fourth bit line BL 4  is connected to one of two nodes of a fourth sense amplifier BLSA 4  through a seventh contact CT 4 , and a fourth complementary bit line BL 4 B is connected to the other of the two nodes of the fourth sense amplifier BLSA 4  through an eighth contact CT 4 B. Accordingly, during a sense amplification operation, the fourth sense amplifier BLSA 4  may sense and amplify a voltage difference between the fourth bit line BL 4  and the fourth complementary bit line BL 4 B. 
         [0053]    For example, the sense amplifier layout array  100  includes  4  sense amplifier layout regions SR 1  to SR 4 , which are arranged adjacent each other and include each sense amplifier BLSA 1  to BLSA 4 , respectively when N is 4. 
         [0054]    In an i(1≦i≦4) th  sense amplifier layout region among sense amplifier layout regions SR 1  to SR 4 , (5−i) bit lines and i complementary bit line(s) are arranged, and an i th  bit line among the (5−i) bit lines and an i th  complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the i th  sense amplifier layout region. 
         [0055]    The first bit line BL 1  is for transmitting data of a first memory cell in a first memory cell array  30  from the first memory cell array  30  to the first sense amplifier layout region SR 1 . The first complementary bit line BL 1 B is for transmitting data of a second memory cell in a second memory cell array  40  from the second memory cell array  40  to the first sense amplifier layout region SR 1 . 
         [0056]    The second bit line BL 2  is for transmitting data of a third memory cell in the first memory cell array  30  from the first memory cell array  30  to the second sense amplifier layout region SR 2 . The second complementary bit line BL 2 B is for transmitting data of a fourth memory cell in the second memory cell array  40  from the second memory cell array  40  to the second sense amplifier layout region SR 2 . 
         [0057]    The third bit line BL 3  is for transmitting data of a fifth memory cell in the first memory cell array  30  from the first memory cell array  30  to the third sense amplifier layout region SR 3 . The third complementary bit line BL 3 B is for transmitting data of a sixth memory cell in a second memory cell array  40  from the second memory cell array  40  to the third sense amplifier layout region SR 3 . 
         [0058]    The fourth bit line BL 4  is for transmitting data of a seventh memory cell in the first memory cell array  30  from the first memory cell array  30  to the fourth sense amplifier layout region SR 4 . The fourth complementary bit line BL 4 B is for transmitting data of an eighth memory cell in the second memory cell array  40  from the second memory cell array  40  to the fourth sense amplifier layout region SR 4 . 
         [0059]    Pairs of a corresponding bit line and complementary bit line BL 1  and BL 1 B, BL 2  and BL 2 B, BL 3  and BL 3 B and BL 4  and BL 4 B may be arranged in a zigzag pattern. 
         [0060]    Referring to  FIG. 2 , when four sense amplifier layout regions SR 1  to SR 4  are included in the sense amplifier layout array  100 , a sum of the number of bit lines and complementary bit lines included in each of the four sense amplifier layout regions SR 1  to SR 4  is 5. For example, a sense amplifier layout region includes portions of bit lines and complementary bit lines that sum to 5 when there are 4 such regions. 
         [0061]    By layout of a bit line and a complementary bit line as illustrated in  FIG. 2 , bit line sense amplifiers may be constructed even though pitch of a memory cell and a bit line or a complementary bit line decreases. 
         [0062]    As shown in  FIG. 2 , selection transistors may transmit a voltage of a corresponding one of bit lines BL 1 , BL 2 , BL 3 , BL 4 , BL 1 B, BL 2 B, BL 3 B or BL 4 B to a corresponding one of data input/output lines I 01 , I 02 , I 03 , I 04 , I 01 B, I 02 B, I 03 B and I 04 B in response to a corresponding one of selection signals CSL 1 , CSL 2 , CSL 3 , CSL 4 , CSL 1 B, CSL 2 B, CSL 3 B and CSL 4 B. 
         [0063]      FIG. 3  shows a detailed diagram of layout patterns of the bit line sense amplifier array illustrated in  FIG. 2  according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 2 and 3 , a solid line in  FIG. 3  means a metal pattern is formed on the same layer and a dotted line means a metal pattern connects different layers to each other. The metal pattern formed to connect different layers to each other may be accomplished using an electrical connection means (e.g., a via, a through silicon via (TSV), a jumper, etc.). For example, a TSV is a vertical electrical connection that passes completely through a silicon wafer or die. 
         [0064]    In the first sense amplifier layout region SR 1 , a first bit line BL 1 , a first complementary bit line BL 1 B, a second bit line BL 2 , a third bit line BL 3  and a fourth bit line BL 4  are arranged. The first bit line BL 1  is connected to one of two nodes of a first sense amplifier BLSA 1  through a first contact CT 1 , and a first complementary bit line BL 1 B is connected to the other of the two nodes of the first sense amplifier BLSA 1  through a second contact CT 1 B. 
         [0065]    In the second sense amplifier layout region SR 2 , a first complementary bit line BL 1 B, a second bit line BL 2 , a second complementary bit line BL 2 B, a third bit line BL 3  and a fourth bit line BL 4  are arranged. The second bit line BL 2  is connected to one of two nodes of a second sense amplifier BLSA 2  through a third contact CT 2 , and a second complementary bit line BL 2 B is connected to the other of the two nodes of the second sense amplifier BLSA 2  through a fourth contact CT 2 B. 
         [0066]    In the third sense amplifier layout region SR 3 , a first complementary bit line BL 1 B, a second complementary bit line BL 2 B, a third bit line BL 3 , a third complementary bit line BL 3 B and a fourth bit line BL 4  are arranged. The third bit line BL 3  is connected to one of two nodes of a third sense amplifier BLSA 3  through a fifth contact CT 3 , and a third complementary bit line BL 3 B is connected to the other of the two nodes of the third sense amplifier BLSA 3  through a sixth contact CT 3 B. 
         [0067]    In the fourth sense amplifier layout region SR 4 , a first complementary bit line BL 1 B, a second complementary bit line BL 2 B, a third complementary bit line BL 3 B, a fourth bit line BL 4  and a fourth complementary bit line BL 4 B are arranged. The fourth bit line BL 4  is connected to one of two nodes of a fourth sense amplifier BLSA 4  through a seventh contact CT 4 , and a fourth complementary bit line BL 4 B is connected to the other of the two nodes of the fourth sense amplifier BLSA 4  through an eighth contact CT 4 B. 
         [0068]      FIG. 4  shows an exemplary embodiment where a plurality of bit line sense amplifiers are arranged in the bit line sense amplifier array layout illustrated in  FIG. 2 , and  FIG. 5  shows a circuit diagram of a first bit line sense amplifier BLSA 1  illustrated in  FIG. 4  according to an exemplary embodiment of the inventive concept. 
         [0069]    Referring to  FIGS. 2 to 5 , a first sense amplifier BLSA 1  is arranged in a first sense amplifier layout region SR 1 . Internal circuits of the first sense amplifier BLSA 1  include a first sensing unit PSA 1  and PSA 1 B, an equalizer EQ 1 , and a second sensing unit NSA 1 B and NSA 1 . The first sensing unit PSA 1  and PSA 1 B, the equalizer EQ 1 , and the second sensing unit NSA 1 B and NSA 1  may be arranged sequentially within the first sense amplifier BLSA 1 . 
         [0070]    In the second sense amplifier layout region SR 2 , a second sense amplifier BLSA 2  is arranged. Internal circuits of the second sense amplifier BLSA 2  include a second sensing unit NSA 2 B and NSA 2 , an equalizer EQ 2 , and a first sensing unit PSA 2 B and PSA 2 . The second sensing unit NSA 2 B and NSA 2 , the equalizer EQ 2 , and the first sensing unit PSA 2 B and PSA 2  may be arranged sequentially within the second sense amplifier BLSA 2 . 
         [0071]    In the third sense amplifier layout region SR 3 , a third sense amplifier BLSA 3  is arranged. Internal circuits of the third sense amplifier BLSA 3  include a first sensing unit PSA 3  and PSA 3 B, an equalizer EQ 3 , and a second sensing unit NSA 3  and NSA 3 B. The first sensing unit PSA 3  and PSA 3 B, the equalizer EQ 3 , and a second sensing unit NSA 3  and NSA 3 B may be arranged sequentially within the third sense amplifier BLSA 3 . 
         [0072]    In the fourth sense amplifier layout region SR 4 , a fourth sense amplifier BLSA 4  is arranged. Internal circuits of the fourth sense amplifier BLSA 4  include a second sensing unit NSA 4 B and NSA 4 , an equalizer EQ 4 , and a first sensing unit PSA 4 B and PSA 4 . The second sensing unit NSA 4 B and NSA 4 , the equalizer EQ 4 , and the first sensing unit PSA 4 B and PSA 4  may be arranged sequentially within the fourth sense amplifier BLSA 4 . 
         [0073]    Since the bit line sense amplifiers BLSA 1 , BLSA 2 , BLSA 3  and BLSA 4  have substantially the same structure, respectively, only a first sense amplifier BLSA 1  is illustrated in  FIG. 5  for convenience of explanation. 
         [0074]    Referring to  FIG. 5  again, a first sense amplifier BLSA 1  includes a first sensing unit PSA 1  and PSA 1 B, an equalizer EQ 1  and a second sensing unit NSA 1  and NSA 1 B. 
         [0075]    According to an exemplary embodiment of the inventive concept, the first sensing unit PSA 1  and PSA 1 B includes a pair of PMOS transistors and the second sensing unit NSA 1  and NSA 1 B includes a pair of NMOS transistors. 
         [0076]    The equalizer EQ 1  pre-charges a first bit line BL 1  and a first complementary bit line BL 1 B with a pre-charge voltage VBL in response to an equalizing signal PEQ. 
         [0077]    In  FIG. 5 , the equalizer EQ 1  is arranged between the first sensing unit PSA 1  and PSA 1 B and the second sensing unit NSA 1  and NSA 1 B. However, in alternate embodiments, the equalizer EQ 1  may be arranged at the left end of the first sensing unit PSA 1  and PSA 1 B or at the right side of the second sensing unit NSA 1  and NSA 1 B. For example, the equalizer EQ 1  may be located to the left of the first sensing unit PSA 1  and PSA 1 B or to the right of the second sensing unit NSA 1 B and NSA 1 . 
         [0078]      FIG. 6  shows an embodiment where a plurality of bit line sense amplifiers are arranged in a layout of the bit line sense amplifier array illustrated in  FIG. 2 . 
         [0079]    Referring to  FIGS. 2 ,  3 , and  6 , a first sense amplifier BLSA 1  is arranged in a first sense amplifier layout region SR 1 . Internal circuits of the first sense amplifier BLSA 1  are arranged in order of a second sensing unit NSA 1  and NSA 1 B, an equalizer EQ 1  and a first sensing unit PSA 1  and PSA 1 B. 
         [0080]    In the second sense amplifier layout region SR 2 , a second sense amplifier BLSA 2  is arranged. Internal circuits of the second sense amplifier BLSA 2  are arranged in order of a first sensing unit PSA 2 B and PSA 2 , an equalizer EQ 2  and a second sensing unit NSA 2 B and NSA 2 . 
         [0081]    In the third sense amplifier layout region SR 3 , a third sense amplifier BLSA 3  is arranged. Internal circuits of the third sense amplifier BLSA 3  are arranged in order of a second sensing unit NSA 3  and NSA 3 B, an equalizer EQ 3  and a first sensing unit PSA 3  and PSA 3 B. 
         [0082]    In the fourth sense amplifier layout region SR 4 , a fourth sense amplifier BLSA 4  is arranged. Internal circuits of the fourth sense amplifier BLSA 4  are arranged in order of a first sensing unit PSA 4 B and PSA 4 , an equalizer EQ 4  and a second sensing unit NSA 4 B and NSA 4 . 
         [0083]    The structure of the other bit line sense amplifiers BLSA 2 , BLSA 3  and BLSA 4  may be the same as described above for the first bit line sense amplifier BLSA 1  shown in  FIG. 5 . 
         [0084]      FIG. 7  shows a memory module including a memory device illustrated in  FIG. 1  according to an exemplary embodiment of the inventive concept. 
         [0085]    Referring to  FIG. 7 , a memory module  200  includes a semiconductor substrate  210  and a plurality of memory devices  10  mounted on the semiconductor substrate  210 . 
         [0086]    The structure and operation of the plurality of memory devices  10  is substantially the same as a structure and an operation of the semiconductor memory device  10  described above with reference to  FIGS. 1 to 3 . 
         [0087]    The memory module  200  may further include a controller  230  for controlling operations of the plurality of memory devices  10 . 
         [0088]    The memory module  200  may be embodied in a Single In-Line Memory Module (SIMM) or a Dual In-Line Memory Module (DIMM). 
         [0089]      FIG. 8  shows a block diagram of a memory system  300  including the memory module  10  illustrated in  FIG. 7  according to an exemplary embodiment of the inventive concept. The memory system  300  may be included in a computer system. The memory system  300  includes a main board  240 , a slot  250  mounted on the main board  240 , a memory module  200  and a processor  270  (e.g., a chip-set), which may control operations of the plurality of memory devices  10 . The memory module  200  may be inserted into the slot  250 . 
         [0090]    The chip set  270  may transmit or receive data to/from each of the plurality of memory devices  10  through a data bus. As an example, the memory system  300  may be included in a personal computer (PC), a tablet PC, a laptop computer, etc. 
         [0091]      FIG. 9  shows an exemplary embodiment of a memory system  400  including a memory device illustrated in  FIG. 1 . Referring to  FIG. 9 , the memory system  400  includes a memory device  10  and a processor  410  controlling a data processing operation of the memory device  10 . As an example, the memory system  400  may be included in a cellular phone, a smart phone, a wireless internet device, etc. 
         [0092]    Data stored in the memory device  10  may be displayed through a display  420  under a control of the processor  410 . 
         [0093]    A wireless transceiver  430  may transmit or receive wireless signals through an antenna ANT. For example, the wireless transceiver  430  may change wireless signals received through the antenna ANT into signals, which the processor  410  may process. Accordingly, the processor  410  may process signals output from the wireless transceiver  430  and store processed signals in the memory device  10  or display them through a display  420 . In addition, the wireless transceiver  430  may convert signals output from the processor  410  into wireless signals and output the wireless signals through the antenna ANT. 
         [0094]    An input device  440  may input control signals for controlling an operation of the processor  410  or data to be processed by the processor  410 . As an example, the input device may be a pointing device such as a touch pad or a computer mouse, a keypad, a keyboard, etc. 
         [0095]    The processor  410  may control an operation of the display  420  so that data output from the memory device  10 , the wireless transceiver  430  or the input device  440  may be displayed through the display  420 . 
         [0096]      FIG. 10  shows an exemplary embodiment of a memory system  500  including a memory device illustrated in  FIG. 1 . Referring to  FIG. 10 , the memory system  500  includes a memory device  10  and a processor  510  controlling a data processing operation of the memory device  10 . As an example, the memory system  500  may be included in data processing device such as a tablet computer, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), a MP3 player or a MP4 player, etc. 
         [0097]    The processor  510  may display data stored in the memory device  10  through a display  530  according to an input signal input by an input device  520 . For example, the input device  520  may be a pointing device such as a touch pad or a computer mouse, a keypad, a keyboard, etc. 
         [0098]      FIG. 11  is a flowchart for a method of manufacturing a bit line sense amplifier layout illustrated in  FIG. 1 . Referring to  FIGS. 1 to 3 , and  11 , the method for forming a sense amplifier layout array  100  is discussed below. 
         [0099]    The method includes forming (1*N) neighboring sense amplifier layout regions SR 1  to SR 4  on a semiconductor substrate (S 10 ) and forming a sense amplifier in each of the (1*N) sense amplifier layout regions SR 1  to SR 4  (S 20 ). 
         [0100]    The method further includes forming (N+1−i) bit lines and i complementary bit lines in an i(1≦i≦N) th  sense amplifier layout region among the (1*N) sense amplifier layout regions SR 1  to SR 4  (S 30 ). 
         [0101]    An i th  bit line among the (N+1−i) bit lines and an i th  complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the i th  sense amplifier layout region by contact, respectively. Each of the (N+1−i) bit lines and each of the i complementary bit lines may be arranged in a zigzag pattern. 
         [0102]    Even though memory cell pitch and bit line pitch have been severely reduced, at least one embodiment of the inventive concept enables a bit line sense amplifier layout array to be constructed. 
         [0103]    While exemplary embodiments of the present inventive concept have been shown and described, it will be appreciated that various changes may be made in these embodiments without departing from the spirit and scope of the inventive concept.