Abstract:
Apparatus and methods are provided for receiving differential phase-shift keyed (DPSK) optical signals subjected to tight optical filtering, such as may be experienced by 40 Gb/s and 100 Gb/s channels in a dense wavelength division multiplexing (DWDM) communications system with 50 GHz channel spacing. An optical DPSK receiver is described which employs an optical delay interferometer (ODI) demodulator having a free spectral range (FSR) that is larger than the symbol rate (SR) of the DPSK signal to be demodulated. The receiver includes means for introducing an additional power imbalance between the outputs of the ODI demodulator, and the additional power imbalance may be related to the ratio of FSR to SR. The additional power imbalance increases the signal tolerance to tight optical filtering, thereby achieving high spectral efficiency in applications such as DWDM.

Description:
FIELD OF THE INVENTION  
       [0001]    The present invention relates to the field of optical communications, and more specifically to apparatus and methods related to the reception of differential phase shift keyed optical signals transmitted with high spectral efficiency. 
       BACKGROUND INFORMATION  
       [0002]    Optical differential phase-shift keying (DPSK) is a promising modulation format that offers high receiver sensitivity, high tolerance to major nonlinear effects in high-speed transmissions, and high tolerance to coherent crosstalk. In optical DPSK transmission, data information is conveyed by the optical phase difference between adjacent bits. Optical DPSK modulation includes differential binary phase shift keying (DBPSK), differential quadrature phase shift keying (DQPSK), and other related format variants. 
         [0003]    To increase the capacity of optical transport networks, 40-Gb/s channels are being considered to replace the 10-Gb/s channels currently carried on these networks. Most of the core transport networks_are based on dense wavelength-division multiplexing (DWDM) with a channel spacing of 50 GHz, as specified by the International Telecommunication Union (ITU). This spacing is illustrated schematically in  FIG. 1A , with Δf min =50 GHz. Due to the much wider optical spectrum of a 40-Gb/s DBPSK signal, as compared to that of a typical 10-Gb/s signal, there is a severe penalty due to the tight optical filtering when transmitting the 40-Gb/s binary signals over the 50-GHz channel grid. This filtering penalty becomes even larger when multiple reconfigurable optical add/drop multiplexers (ROADMs) incorporating elements such as wavelength selective switches (WSS) are also inserted in the transmission system, as is common in most of today&#39;s transparent optical networks, such as that schematically depicted in  FIG. 1B . For example, in the network  10  illustrated, a signal may be routed via multiple ROADM/WSS  11 - 14  between its origin  21  and its destination  22 . This makes it difficult to transmit, with high spectral efficiency, such high-speed DPSK signals in a typical DWDM system. 
         [0004]    An existing approach to achieve high spectral efficiency is to use bandwidth-efficient modulation formats such as DQPSK and duobinary. DQPSK, however, requires more complex and expensive transmitters and receivers, and duobinary has poorer receiver sensitivity than DBPSK and DQPSK. 
       SUMMARY OF THE INVENTION  
       [0005]    In an exemplary embodiment, the present invention provides an optical differential phase-shift keying (DPSK) receiver which employs an optical delay interferometer (ODI) to demodulate a received optical DPSK signal. In accordance with the present invention, the ODI demodulator has a free spectral range (FSR) that is larger than the symbol rate (SR) of the DPSK signal to be demodulated. Moreover, the receiver includes means for introducing an additional power imbalance between the signals corresponding to the two outputs of the ODI demodulator, wherein the additional power imbalance is related to the ratio of FSR to SR. When judiciously chosen, the additional power imbalance increases the signal tolerance to tight optical filtering, thereby achieving high spectral efficiency in applications such as dense wavelength-division multiplexing (DWDM). The additional power imbalance can be implemented electrically, using electrical attenuation or amplification circuitry, or optically, using optical attenuation. The introduced power imbalance can be fixed or adjustable. In order to accommodate the potential ambiguity in the polarity of the received data, polarity detection and recovery circuitry may also be used. 
         [0006]    Embodiments of the present invention can be applied, for example, to the transmission of 40-Gb/s differential binary phase shift keying (DBPSK) signals over a 50-GHz DWDM grid, as well as 100-Gb/s differential quadrature phase-shift keying (DQPSK) signals over a 50-GHz grid. Such embodiments enable 40-Gb/s DBPSK and 100-Gb/s DQPSK signals to be carried over DWDM systems having a 50-GHz minimum channel spacing with improved performance in terms of system reach and ROADM support. 
         [0007]    Further embodiments of the present invention also provide other benefits such as adaptively optimizing the performance of the signal reception under different filtering conditions by adjusting the power ratio without changing the delay or FSR of the ODI, thereby making the signal reception hitless or free of interruption. 
         [0008]    The aforementioned and other features and aspects of the present invention are described in greater detail below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0009]      FIG. 1A  illustrates the channel spacing in a dense wavelength-division multiplexing (DWDM) scheme; and  FIG. 1B  is a schematic representation of a typical optical network with multiple reconfigurable optical add/drop multiplexers (ROADMs) and wavelength selective switches (WSS). 
           [0010]      FIG. 2  is a block diagram of an exemplary embodiment of a differential binary phase shift keying (DBPSK) receiver comprising an optical power imbalance module. 
           [0011]      FIG. 3  is a block diagram of an exemplary embodiment of a DBPSK receiver comprising an electrical power imbalance module. 
           [0012]      FIG. 4  is a block diagram of a further exemplary embodiment of a DBPSK receiver. 
           [0013]      FIG. 5  is a block diagram of an exemplary embodiment of a differential quadrature phase shift keying (DQPSK) receiver. 
       
    
    
     DETAILED DESCRIPTION  
       [0014]      FIG. 2  is a block diagram of an exemplary embodiment of a differential binary phase shift keying (DBPSK) receiver  100  in accordance with the present invention. It is contemplated that the receiver  100  can be used, for example, to receive DBPSK signals, whose data rate is nominally 43 Gb/s and can range from about 40 Gb/s to 50 Gb/s, transmitted over a dense wavelength-division multiplexing DWDM system ( FIG. 1B ) with 50-GHz minimum channel spacing Δf min =50 GHz ( FIG. 1A ). 
         [0015]    The receiver  100  comprises an optical delay interferometer (ODI)  110  for demodulating a received optical DBPSK signal at its input. In general, an ODI has two optical paths with different lengths. The length difference between the two paths causes a time delay T d  between the optical signals traveling along the two paths, and the delay equals the reciprocal of the free spectral range (FSR) of the ODI, i.e., FSR=1/T d . In accordance with the present invention, the ODI  110  has an FSR that is greater than the symbol rate (SR) of the DBPSK signal to be demodulated. In a exemplary embodiment in accordance with the present invention, the FSR is preferably in a range of: 
         [0000]      1.15 SR≦FSR≦2.5 SR,   (1) 
         [0000]    where FSR is in units of GHz and SR is in units of Gbaud. 
         [0016]    The constructive output port of the ODI  110  is coupled via an optical attenuator  115  to a first input of a balanced detector  120 , whereas the destructive output port of the ODI  110  is coupled via a second optical attenuator  116  to a second input of the balanced detector  120 . The optical attenuators  115  and  116 , with variable attenuation α 1  and α 2  respectively, are controlled by a control unit  125  to adjust the ratio of signal powers associated with the ODI constructive and destructive ports, P con  and P des , respectively. The attenuators  115  and  116  introduce an incremental power imbalance, or change in the power ratio between the signals which is additional to the natural power ratio when the powers of the two signals are not thusly modified. For example, the additional adjustment of the power ratio P con /P des  introduced by the attenuators  115  and  116  may be between −6 dB and 2 dB, depending on the degree of optical filtering to which the received DBPSK signal has been subjected, with more attenuation preferably introduced for less filtering. Here, an adjustment of 2 dB of the power ratio P con /P des  means a relative increase of P con  over P des  by 2 dB, or by about 58%. As such, signal performance can be optimized under different filtering conditions adaptively (without changing the delay or FSR of the ODI) by adjusting the power ratio. 
         [0017]    Although the exemplary embodiment of  FIG. 2  shows an optical attenuator coupled to each of the constructive and destructive ports of the ODI  110 , it is possible in accordance with the present invention to have alternative embodiments with an attenuator coupled to only one of the ODI ports. For instance, if the additional adjustment of the power ratio P con /P des  is to be less than zero (i.e., only the signal of the constructive port need be attenuated), the attenuator  116  can be eliminated. 
         [0018]    Moreover, for applications in which it is not necessary to vary the attenuation (e.g., the filtering conditions are substantially constant), attenuation can be realized, for example, with a fixed attenuator or by imperfect optical coupling in at least one of the output ports of the ODI  110 . Using well known techniques, the optical coupling can be set upon fabrication to provide the desired degree of attenuation. 
         [0019]    The output of the balanced detector  120  is provided to a clock and data recovery (CDR) circuit  130 , which recovers the data encoded in the received signal and a clock at the symbol rate (SR). In order to accommodate the potential ambiguity in the polarity of the received data, a data inversion circuit  140  may also be included to invert the data recovered by the CDR circuit  130 . The CDR and data inversion circuits can be implemented in known ways. 
         [0020]    As a further alternative in accordance with the present invention, the power ratio adjustment can be achieved with electrical means.  FIG. 3  shows a further exemplary embodiment of a receiver  200  in which the power ratio adjustment is carried out using electronic amplifier and/or attenuator circuitry. The receiver  200  comprises electronic amplifiers (and/or attenuators)  221  and  222  which amplify and/or attenuate the constructive and destructive outputs, respectively, of the ODI  210  after they have been detected and converted to electrical signals. The amplification and/or attenuation (g 1 , g 2 ) provided by the amplifiers (and/or attenuators)  221  and  222  can be varied under the control of a control unit  225 . A clock and data recovery (CDR) circuit  230  and an optional data inversion circuit  240 , as described above, recover the original data. 
         [0021]    Although the exemplary embodiment of  FIG. 3  shows an electronic amplifier (and/or attenuator) for each of the constructive and destructive ports of the ODI  210 , it is possible in accordance with the present invention to have alternative embodiments with an amplifier (attenuator) for only one of the ODI ports. 
         [0022]    In an exemplary embodiment, the power adjustment can be set in accordance with the following relation: 
         [0000]      Δ( P   con   /P   des )≈( SR/FSR− 0.75)×15 dB.   (2) 
         [0023]    For example, for a symbol rate (SR) of 43 Gb/s, the additional power ratio adjustments on (P con /P des ) would be approximately 1.7 dB, −1.6 dB, and −4.8 dB for FSRs of 50 GHz, 67 GHz, and 100 GHz, respectively. If the FSR and SR obey the relationship (1), the additional power ratio adjustment Δ(P con /P des ) would have a range of approximately −5.25 dB to 1.8 dB. 
         [0024]      FIG. 4  is a block diagram of a further exemplary embodiment of a receiver  300  in accordance with the present invention. The receiver  300  comprises an ODI  310  demodulator with an FSR that is equal to the WDM channel spacing, Δf min . Thus, in the case of 50 GHz channel spacing, the FSR of the ODI  310  would be 50 GHz, and T d  would be 20 ps. As such, the FSR of the ODI  310  would be about 16% larger than the symbol rate of a 43 Gb/s DBPSK signal. According to the relationship (2), the desired power adjustment would be 1.65 dB, or P des  would be decreased relative to P con  by 1.65 dB, or by about 32%. 
         [0025]    In the exemplary embodiment of  FIG. 4 , the additional power imbalance is introduced by a fixed optical attenuation  315  between the destructive output port of the ODI  310  and the balanced detector  320 . The attenuation  315  can be implemented, for example, by imperfectly coupling the destructive port of the ODI  310  to the detector  320  to provide a fixed optical attenuation  315  to the corresponding signal. Alternatively, the attenuation  315  can be implemented with a discrete power imbalance module or block, as described above. 
         [0026]    A CDR circuit  330 , as described above, is shown for recovering the original data. A feature of the embodiment of  FIG. 4  is that the optional data inversion circuit may no longer be needed since the ODI  310 , whose FSR equals the WDM channel spacing Δf min , may be configured to demodulate any one of the WDM channels with a fixed nominal condition. This feature can also be exploited to realize colorless operation where no change in ODI settings is needed when the wavelength of the received WDM signal changes. 
         [0027]      FIG. 5  is a block diagram of yet a further exemplary embodiment of a receiver  400  in accordance with the present invention. The receiver  400  can demodulate differential quadrature phase-shift keying (DQPSK) signals, such as may be transmitted over a DWDM system with 50-GHz minimum channel spacing. For a DQPSK signal with a net data rate of 100 Gb/s, for example, the raw data rate is nominally 113 Gb/s and can range from about 107 Gb/s to about 125 Gb/s when the overhead for processes such as forward error correction (FEC) is included. 
         [0028]    The receiver  400  comprises a DQPSK demodulator including a pair of ODIs  410  and  411  for demodulation of the in-phase and quadrature-phase components of the DQPSK signal. In an exemplary embodiment, the FSR of the DQPSK demodulator is 100 GHz. As such, the FSR of the ODIs  410  and  411  is about 77% larger than the symbol rate of a 113 Gb/s DQPSK signal. According to the relationship (2), the desired power adjustment would be −2.8 dB, or in other words, P con  (of each ODI) would be decreased relative to P des  (of each ODI) by 2.8 dB, or by about 48%. 
         [0029]    The outputs of the ODIs  410  and  411  are provided to a power imbalance module  415 . The in-phase and quadrature-phase outputs of the power imbalance module  415  are coupled to balanced detectors  421  and  422 , respectively. The power imbalance module  415  can be implemented as described above by subjecting the signals at the constructive and/or destructive ports of the ODIs  410  and  411  to optical attenuation, such as by an optical attenuator or by providing imperfect optical coupling. Alternatively, as described above, an electrical implementation of a power imbalance module arranged after the conversion of the optical signals to electrical form can be used. Moreover, the power imbalance module  415  may provide a fixed power imbalance or a variable power imbalance under the control of a control unit  425 . 
         [0030]    CDR circuits  431  and  432  and optional data inversion circuits  441  and  442 , as described above, follow the detectors  421  and  422 , respectively, for recovering the original in-phase and quadrature-phase data tributaries. 
         [0031]    As disclosed herein, the present invention offers good signal performance when receiving high spectral efficiency DPSK signals transmitted over conventional DWDM systems. Moreover, further embodiments of the present invention also provide other benefits such as a mechanism for optimizing the signal performance under different filtering conditions adaptively (without changing the delay of the ODI) by adjusting the power ratio, and allowing hitless receiver operation. Such embodiments of the present invention thereby provides overall system performance improvement and easy implementation when transmitting DPSK signals in high spectral efficiency systems. 
         [0032]    It is understood that the above-described embodiments are illustrative of only a few of the possible specific embodiments which can represent applications of the invention. Numerous and varied other arrangements can be made by those skilled in the art without departing from the spirit and scope of the invention.