Abstract:
In an input buffer circuit arrangement, a comparator compares a filtered input signal applied to one input with each of a first and a second reference value preset at the other input by a first setting circuit to produce a comparison output signal. According to the comparison output signal, a second setting circuit provides a third and a fourth reference value to one input of the comparator to obtain a noise-resistive characteristic.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an input buffer circuit for detecting the frequency or angular information of an electromagnetic pickup coil in terms of a voltage. 
     In a known input buffer circuit of the above type, the voltage signal from a pickup coil is reshaped through a CR filter and then subjected to voltage comparison by a comparator. The CR filter circuit is an essential circuit element for the purpose of eliminating any noise signal superposed on the signal line of the pickup coil. However, where the time constant of the CR filter circuit is increased, if the signal frequency is high, the signal voltage from the pickup coil will be delayed in phase, thus making it impossible to obtain an accurate angular information. In other words, there is a disadvantage that if the time constant of the noise suppressing CR filter circuit is increased so as to improve the antinoise characteristic, the resulting angular information and detection response characteristic will be deteriorated. 
     SUMMARY OF THE INVENTION 
     With a view to overcoming the foregoing deficiencies of the prior art circuit, it is the object of the present invention to provide an improved input buffer circuit so designed that when the first and second threshold levels of a comparator are respectively crossed from predetermined directions by the input signal, the threshold levels are respectively set again to new third and fourth threshold levels, respectively, for a predetermined period thus improving the antinoise and response characteristics. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a prior art input buffer circuit. 
     FIG. 2 shows various waveforms useful for explaining the operation of the prior art input buffer circuit. 
     FIG. 3 is a circuit diagram showing an input buffer circuit according to the present invention. 
     FIG. 4 shows various waveforms useful for explaining the operation of the circuit according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention will now be described with reference to the accompanying drawings. FIG. 1 illustrates a circuit diagram of a prior art input buffer circuit. FIG. 2 illustrates various waveforms useful for explaining the operation of the prior art circuit. In the Figures, numeral 1 designates an input signal source. Symbol A designates a filter circuit comprising a resistor 2, a capacitor 3 and a resistor 4. Symbol B designates a setting circuit for establishing a first preset voltage V TH1  and a second preset voltage V TL1  and the circuit comprises resistors 9, 10 and 11 and a transistor 12. Numeral 13 designates an input signal detecting comparator whose (+) terminal is supplied with the input signal via the filter circuit and whose (-) terminal is supplied with the first and second preset voltages V TH1  and V TL1  set by the setting circuit. Numeral 15 designates an output amplifier, and 27 a power source. 
     FIG. 3 is a circuit diagram showing an input buffer circuit according to the present invention. The same reference numerals as used in FIG. 1 designate the identical component parts. Numerals 5 and 6 designate constant current sources for respectively supplying fourth and third preset voltages V TH2  and V TL2  to the comparator 13 via diodes 7 and 8, respectively. Numeral 14 designates the base resistor of the transistor 12. Symbol C designates a time setting circuit for determining a holding time of the third and fourth preset voltages V TL2  and V TH2 . Symbol C-1 designates a current mirror circuit operable in synchronism with the input signal so as to control the charge and discharge times of a capacitor 19 in accordance with the amount of output current of a frequency-to-current converter circuit D. Symbol C-2 designates a voltage setting circuit for a comparator 23 for detecting the voltage on the capacitor 19 and the circuit comprises resistors 20, 21 and 22. Numeral 24 designates an output amplifier for the comparator 23. The frequency-to-current converter circuit D comprises a frequency-to-voltage converter and a voltage-to-current converter. The comparison output of the comparator 13 is applied to the current mirror circuit C-1 via an amplifier 16 and a diode 18 and to the voltage setting circuit C-2 via an amplifier 17. Numerals 25 and 26 designate flip-flops adapted to be set by the output of the comparator 13 and reset by the output of the comparator 23. Numeral 28 designates an output amplifier for the comparator 13. 
     Next, the operation of the buffer circuit according to the present invention will be described with reference to FIGS. 3 and 4. The signal generating voltage V in  of the signal source 1 is compared and detected by the comparator 13 via the filter circuit A and the operating preset voltage at a point V a  of the comparator 13 (herein- after referred to as a threshold voltage V TH ) is determined by the V TH1  /V TL1  setting circuit B. In this case, if the voltage of the input signal V in  is a positive-going voltage signal exceeding the first preset voltage V TH1 , the output of the comparator 13 goes to a high level or &#34;H&#34; and the output of the buffer circuit also goes to &#34;H&#34;. Simultaneously, the transistor 12 is turned on and the preset voltage at the point V a  is changed to the second preset voltage V TL1 . On the other hand, the &#34;H&#34; output of the comparator 13 sets the flip-flop 25 (hereinafter referred to as an FF1) and the output of the FF1 causes a constant current I 3  to flow from the constant current source 6 toward a point V b . As a result, the voltage at the point V b  becomes V in  +{resistor 4 ×I 3  } (here it is referred to as the resistor 4×I 3  =V JAMP  =V J ). The holding time T 1  of the voltage V J  is determined by the frequency-to-current converter circuit or F-1 converter circuit D whose output current varies with the input frequency and the FF1 setting circuit C. In other words, the holding time T 1  is set such that lower the input frequency is, longer the time T 1  becomes, while higher the input frequency is, shorter the time T 1  becomes. The voltage waveform of the input V in  is shown in (a) of FIG. 4 and the voltage waveform at the point V b  is shown in (b) of FIG. 4. When the voltage V in  decreases from its positive value toward a negative value so that it becomes lower than the second preset voltage V TL1 , the output voltage of the comparator 13 goes to a low level or &#34;L&#34;. Consequently, the output of the buffer circuit also goes to &#34;L&#34;. Simultaneously, the transistor 12 is turned off so that not only the voltage at the point V a  is set to V TH1  but also the flip-flop 26 or FF2 is set, thus causing a constant current I 4  to flow from the constant current source 5 toward the point V a . As a result, the voltage at the point V a  becomes V TH1  +{resistor 10+resistor 11}. I 4  =V TH2 . This condition is shown in (c) of FIG. 4. Its holding time T 2  is also made dependent on the input frequency by the F-1 converter circuit D and the FF2 setting circuit C as in the case of the holding time T 1 . Thus, when the FF2 is reset, the preset voltage is returned to V TH1  and the circuit is placed in condition for the next input signal. 
     The relationship between the input voltage and the preset voltage in dependence on the relationship among the V TH1 , V TH2  , V TL1  and V J  is shown in (e) of FIG. 4. The V TH1 , V TL1  and V TH2  show the preset voltages or the actual voltages at the point V a  in FIG. 3. The voltage V TL2  shows a condition which is the same as if the preset voltage V TL1  at the point V a  is apparently decreased by the amount of V J  due to the application of the superposing voltage V J  on the input voltage V in . 
     By virtue of the construction described above, when the comparator operates in response to the first and second preset voltages V TH1  and V TL1 , respectively, they are immediately set again to the third and fourth preset voltages V TL2  and V TH2 , respectively, for a period of time corresponding to the input frequency, thus preventing any erroneous on-off operation during a transitional period due to an external noise. Also, since the re-setting time T s  is selected smaller than the input period T, |Vin|  is smaller than V TL2  and V TH2 . Even if any input voltage irregularity occurs, there is a certain time domain in which the comparator is operated and consequently the occurrence of any fatal erroneous operation is prevented. Thus, the input buffer circuit of this invention has an increased response speed and an improved antinoise characteristic.