Abstract:
Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a speed control section configured to control a speed of the decoding on the basis of a reception interval of the low density parity check code.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a receiving apparatus, a receiving method and program, and a receiving system and, more particularly, to a receiving apparatus, a receiving method and program, and a receiving system that are configured to hold down a drastic change in power consumption. 
         [0003]    2. Description of the Related Art 
         [0004]    Having strong error correction capabilities, LDPC codes are employed the DVB-S2 (Digital Video Broadcasting—Satellite—Second Generation) standard and the DVB-T2 (Digital Video Broadcasting—Terrestrial 2) standard for use in digital television systems based on these broadcasting standards for example. 
         [0005]    An LDPC code is repetitively decoded to provide high error correction capabilities. However, the repetition of decoding results in increasing the power consumption of digital television systems. Besides, the data amount per code word of LLR (Log-Likelihood Ratio) that is entered in a reception apparatus as an LDPC code depends on a symbol rate and so on. Consequently, the number of repetitions of decoding that can be executed in a given period of time varies. Further, if there is a variation in the data amount per code word of LDPC code, a deviation occurs in the timing of decoding, thereby causing a large variation in power consumption. 
         [0006]    Now, referring to  FIG. 1 , there is shown a block diagram illustrating a receiving apparatus configured to receive LDPC codes. 
         [0007]    A receiving apparatus  10  shown in  FIG. 1  is composed of an LDPC decoding block  11  and a repetition count control block  12 . 
         [0008]    The LDPC decode block  11  receives a log-likelihood ratio as an LDPC code for each frame entered from the outside in response to a decode enable signal for enabling the reception of LLR supplied from the repetition count control block  12 . The LDPC decode block  11  executes LDPC decoding by use of the received log-likelihood ratio. The LDPC decode block  11  determines on the basis of a decoding result whether the LDPC decoding has been successful or not. Then, depending on the determination result, the LDPC decode block  11  supplies a decode successful flag indicative of successful LDPC decoding or a decode unsuccessful flag indicative of unsuccessful LDPC decoding to the repetition count control block  12 . In addition, as specified by the repetition count control block  12 , the LDPC decode block  11  outputs a decode result. 
         [0009]    A frame start signal indicative of a frame start timing is entered in the repetition count control block  12 . In response to the frame start signal, the repetition count control block  12  enters a decode enable signal into the LDPC decode block  11 . It should be noted that, if the level of a decode enable signal is H (High) level, the reception of log-likelihood ratio is enabled; if the level of a decode enable signal is L (Low) level, the reception of log-likelihood ratio is disabled. 
         [0010]    If a decode successful flag is supplied from the LDPC decode block  11 , the repetition count control block  12  instructs the LDPC decode block  11  to output the decoding result. On the other hand, if a decode unsuccessful signal is supplied from the LDPC decode block  11 , the repetition count control block  12  instructs the LDPC decode block  11  to executing decoding again before the frame start signal of a next frame is received and, when the frame start signal of a next frame is received, instructs the LDPC decode block  11  to output a decoding result. 
         [0011]    Referring to  FIG. 2 , there is shown a flowchart indicative of the decode processing that is executed by the receiving apparatus  10 . This processing starts when a decode enable signal of H level is entered from the repetition count control block  12  into the LDPC decode block  11  in response to the frame start signal of a start frame. 
         [0012]    In step S 11 , the LDPC decode block  11  receives a log-likelihood ratio for each frame from the outside. Upon reception of the log-likelihood ratio, the decode enable signal goes L level. In step S 12 , the LDPC decode block  11  executes LDPC decoding by use of the received log-likelihood ratio. In step S 13 , the LDPC decode block  11  determines on the basis of a decoding result whether the LDPC decoding has been successful or not. 
         [0013]    If the LDPC decoding is found successful in step S 13 , then the LDPC decode block  11  supplies a decode successful flag to the repetition count control block  12 . In response, the repetition count control block  12  instructs the LDPC decode block  11  to output a decoding result. Next, in step S 14 , the LDPC decode block  11  outputs a decoding result. 
         [0014]    In step S 15 , the repetition count control block  12  determines whether a new frame start signal has been entered or not. If no new frame start signal is found entered in step S 15 , the repetition count control block  12  waits until a new frame start signal is entered. 
         [0015]    On the other hand, if a new frame start signal is found entered in step S 15 , then the repetition count control block  12  enters a decode enable signal of H level into the LDPC decode block  11 , returning the processing procedure to step S 11 . Consequently, the LDPC decoding for log-likelihood ratio of a frame next to the frame subject to the previous decoding. 
         [0016]    If the LDPC decoding is found unsuccessful in step S 13 , the LDPC decode block  11  supplies a decode unsuccessful flag to the repetition count control block  12 . Next, in step S 16 , the repetition count control block  12  determines whether a new frame start signal has been entered or not. 
         [0017]    If no new frame start signal is found entered in step S 16 , then the repetition count control block  12  instructs the LDPC decode block  11  to execute decoding and returns the processing procedure to step S 12 . Then, the processing operations of steps S 12 , S 13 , and S 16  are repeated until LDPC decoding is found successful or a new frame start signal is entered. 
         [0018]    On the other hand, if a new frame start signal is found entered in step S 16 , then the repetition count control block  12  enters a decode enable signal of H level. 
         [0019]    Next, in step S 17 , the LDPC decode block  11  outputs a decoding result in response to the instruction supplied by the repetition count control block  12 . Thus, the receiving apparatus  10  is able to repeat the LDPC decoding until the LDPC decoding is successful in a period of time up to the input of a frame start signal of the frame next to the current frame subject to decoding. After the processing of step S 17 , the processing procedure returns to step S 11  to execute the LDPC decoding for the log-likelihood ratio of the frame next to the frame subject to the previous decoding. 
         [0020]    Referring to  FIG. 3 , there is shown a timing chart indicative of operation timings of the receiving apparatus  10  in a condition where the BER (Bit Error Rate) of a decoding result is relatively low.  FIG. 4  shows a timing chart indicative of operation timings of the receiving apparatus  10  in a condition where the BER of a decoding result is relatively high. 
         [0021]    As shown in  FIG. 3 , in the condition where the BER of a decoding result is relatively low, error correction converges with a relatively small repetitive decoding count, so that the power consumption is held down by stopping the LDPC decoding if the LDPC decoding is successful. 
         [0022]    On the other hand, as shown in  FIG. 4 , in the condition where the BER of a decoding result is relatively high, the repetitive execution of decoding cannot sufficiently execute the error correction, so that the decoding is repeated until the input of a next frame start signal. This keeps the power consumption always at a high level. 
         [0023]    So, techniques were proposed that, if the repetitive execution of decoding cannot achieve the sufficient error correction, the repetitive decoding is stopped by detecting the insufficient error correction, thereby holding down the power consumption (refer to JP-T-2008-544692 and Japanese Patent Laid-open No. 2007-81640). 
         [0024]    Further, a technique was proposed that the repetitive decoding count is controlled on the basis of communication path conditions, such as signal-to-noise ratio (SNR), noise power, noise quantity, and so on (refer to Japanese Patent Laid-open No. 2009-38707). 
       SUMMARY OF THE INVENTION 
       [0025]    It should be noted here that, with the receiving apparatus  10 , LDPC decoding is stopped when LDPC decoding has been succeeded, so that LDPC decoding is repetitively executed and stopped. This causes drastic variations in the power consumption, thereby significantly increasing the power supply load. 
         [0026]    Therefore, the present invention addresses the above-identified and other problems associated with related-art methods and apparatuses and solves the addressed problems by providing a receiving apparatus, a receiving method and program, and a receiving system that are configured to hold down drastic variations in the power consumption. 
         [0027]    In carrying out the invention and according to a first embodiment thereof, there is provided a receiving apparatus. This receiving apparatus includes: decoding means for receiving and decoding a low density parity check code; and speed control means for controlling a speed of the decoding on the basis of a reception interval of the low density parity check code. 
         [0028]    A receiving method and a program of the first embodiment of the invention correspond to the above-mentioned receiving apparatus of the first embodiment of the invention. 
         [0029]    In the first embodiment of the invention, a received LDPC code is decoded and the speed of the decoding is controlled on the basis of a reception interval of the LDPC code. 
         [0030]    In carrying out the invention and according to a second embodiment thereof, there is provided a receiving system. This receiving system includes: acquisition means for acquiring a signal from a transmission path; and transmission path decode processing means for executing transmission path decode processing on a signal acquired by the acquisition means. This transmission path decode processing means has decoding means for decoding a low density parity check code of the signal, and speed control means for controlling a speed of the decoding on the basis of a reception interval of the low density parity check code. 
         [0031]    In the second embodiment of the invention, a signal is acquired from the transmission path and transmission path decode processing is executed on the acquired signal. In the transmission path decode processing, the LDPC code is decoded and the speed of the decoding is controlled on the basis of a reception interval of the LDPC code. 
         [0032]    In carrying out the invention and according to a third embodiment thereof, there is provided a receiving system. This receiving system includes: transmission path decode processing means for executing transmission path decode processing on a signal acquired from a transmission path; and information source decode processing means for executing information source decode processing on the signal on which the transmission path decoding processing has been executed by the transmission path decode processing means. This transmission path decode processing means has decoding means for decoding a low density parity check code of the signal, and speed control means for controlling the speed of the decoding on the basis of a reception interval of the low density parity check code. 
         [0033]    In the third embodiment of the invention, transmission path decode processing is executed on the signal acquired from the transmission path and information source decode processing is executed on the signal on which the transmission path decode processing has been executed. In the transmission path decode processing, the LDPC code of the signal is decoded and the speed of the decoding is controlled on the basis of a reception interval of the LDPC code. 
         [0034]    In carrying out the invention and according to a fourth embodiment thereof, there is provided a receiving system. This receiving system includes: transmission path decode processing means for executing transmission path decode processing on a signal acquired from a transmission path; and output means for outputting at least one of image data and audio data on the basis of the signal on which the transmission path decode processing has been executed by the transmission path decode processing means. This transmission path decode processing means has decoding means for decoding a low density parity check code of the signal, and speed control means for controlling a speed of the decoding on the basis of a reception interval of the low density parity check code. 
         [0035]    In the fourth embodiment of the invention, transmission path decode processing is executed on the signal acquired from the transmission path and image data or audio data is outputted on the basis of the signal on which the transmission path decode processing has been executed. In the transmission path decode processing, the LDPC code of the signal is decoded and the speed of the decoding is controlled on the basis of a reception interval of the LDPC code. 
         [0036]    In carrying out the invention and according to a fifth embodiment thereof, there is provided a receiving system. This receiving system includes: transmission path decode processing means for executing transmission path decode processing on a signal acquired from a transmission path; and recording control means for controlling recording of the signal on which transmission path decode processing has been executed by the transmission path decode processing means. This transmission path decode processing means has decoding means for decoding a low density parity check code of the signal, and speed control means for controlling a speed of the decoding on the basis of a reception interval of the low density parity check code. 
         [0037]    In the fifth embodiment of the invention, transmission path decode processing is executed on the signal acquired from the transmission path and the recording of the signal on which the transmission path decode processing has been executed is controlled. In the transmission path decode processing, the LDPC code of the signal is decoded and the speed of the decoding is controlled on the basis of a reception interval of the LDPC code. 
         [0038]    As described above and according to the invention, drastic variations in power consumption can be held down. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0039]      FIG. 1  is a block diagram illustrating a related-art receiving apparatus; 
           [0040]      FIG. 2  is a flowchart indicative of the decode processing to be executed by the receiving apparatus shown in  FIG. 1 ; 
           [0041]      FIG. 3  is a timing chart indicative of operation timings of the receiving apparatus shown in  FIG. 1  in a condition where BER is low; 
           [0042]      FIG. 4  is a timing chart indicative of operation timings of the receiving apparatus shown in  FIG. 1  in a condition where BER is high; 
           [0043]      FIG. 5  is a block diagram illustrating an exemplary configuration of a receiving apparatus practiced as a first embodiment of the invention; 
           [0044]      FIG. 6  is a flowchart indicative of the decode processing to be executed by the receiving apparatus shown in  FIG. 5 ; 
           [0045]      FIG. 7  is a timing chart indicative of operation timings of the receiving apparatus shown in  FIG. 5  when BER is high; 
           [0046]      FIG. 8  is a graph indicative of relationships of power consumption and BER; 
           [0047]      FIG. 9  is a block diagram illustrating an exemplary configuration of a receiving apparatus practiced as a second embodiment of the invention; 
           [0048]      FIG. 10  is a flowchart indicative of the decode processing to be executed by the receiving apparatus shown in  FIG. 9 ; 
           [0049]      FIG. 11  to  FIG. 13  are timing charts indicative of operation timings of the receiving apparatus shown in  FIG. 9 ; 
           [0050]      FIG. 14  and  FIG. 15  are timing charts indicative of other operation timings of the receiving apparatus shown in  FIG. 9 ; 
           [0051]      FIG. 16  is a block diagram illustrating an exemplary configuration of a receiving apparatus practiced as a third embodiment of the invention; 
           [0052]      FIG. 17  is a flowchart indicative of decoding speed control processing to be executed by the receiving apparatus shown in  FIG. 16 ; 
           [0053]      FIG. 18  and  FIG. 19  are timing charts indicative of effects brought by the receiving apparatus shown in  FIG. 16 ; 
           [0054]      FIG. 20  is a block diagram illustrating a first exemplary configuration of a receiving system applicable to receiving apparatuses; 
           [0055]      FIG. 21  is a block diagram illustrating a second exemplary configuration of a receiving system applicable to receiving apparatuses; 
           [0056]      FIG. 22  is a block diagram illustrating a third exemplary configuration of a receiving system applicable to receiving apparatuses; and 
           [0057]      FIG. 23  is a block diagram illustrating an exemplary configuration of a computer. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
     Exemplary Configuration of Receiving Apparatus Practiced as First Embodiment 
       [0058]    This invention will be described in further detail by way of embodiments thereof with reference to the accompanying drawings. Now, with reference to  FIG. 5 , there is shown a block diagram illustrating an exemplary configuration of a receiving apparatus practiced as the first embodiment of the present invention. 
         [0059]    With reference to  FIG. 5 , components similar to those previously described with reference to  FIG. 1  are denoted by the same reference numerals. The description duplicate with that made with reference to  FIG. 1  is skipped appropriately. 
         [0060]    The configuration of a receiving apparatus  30  shown in  FIG. 5  differs from that shown in  FIG. 1  mainly in that a repetition count control block  31  is arranged in place of the repetition count control block  12  and a BER computation block  32  is newly arranged. The receiving apparatus  30  controls the frequency of LDPC decoding by using, as an index, BER that is conditional information providing an index indicative of communication conditions affecting the power consumption at the time of decoding. 
         [0061]    To be more specific, the repetition count control block  31  is composed of a control block  41  and a frame start counter  42 . In the repetition count control block  31 , a frame start signal is entered. 
         [0062]    The control block  41  enters a decode enable signal into an LDPC decode block  11  on the basis of a BER supplied from the BER computation block  32  and a count value supplied from the frame start counter  42 , there by controlling the frequency of LDPC decoding. 
         [0063]    In addition, if a decode successful flag is supplied from the LDPC decode block  11 , the control block  41  instructs the LDPC decode block  11  to output a decoding result. On the other hand, if a decode unsuccessful flag is supplied from the LDPC decode block  11 , the control block  41  instructs the LDPC decode block  11  to execute decoding again before a log-likelihood ratio of a next frame is received; after a log-likelihood ratio of a next frame is received, the control block  41  instructs the LDPC decode block  11  to output a decoding result. Further, on the basis of the a BER supplied from the BER computation block  32 , the control block  41  controls the frame start counter  42 . 
         [0064]    The frame start counter  42  counts the number of times the frame start signal has been entered under the control of the control block  41 . 
         [0065]    The BER computation block  32  computes a BER on the basis of a decoding result supplied from the LDPC decode block  11  and a log-likelihood ratio entered from the outside, supplying a computed BER to the control block  41  of the repetition count control block  31 . 
       [Processing by the Receiving Apparatus] 
       [0066]    Referring to  FIG. 6 , there is shown a flowchart indicative of the decode processing that is executed by the receiving apparatus  30 . This decode processing starts when a decode enable signal of H level is entered in the LDPC decode block  11  in response to a frame start signal of a start frame, for example. 
         [0067]    In step S 31 , the LDPC decode block  11  receives a log-likelihood ratio for each frame from the outside. Upon reception of the log-likelihood ratio, the decode enable signal goes L level. In step S 32 , the LDPC decode block  11  executes LDPC decoding by use of the received log-likelihood ratio. In step S 33 , the LDPC decode block  11  determines on the basis of a decoding result whether the LDPC decoding is successful or not. 
         [0068]    If the LDPC decoding is found successful in step S 33 , then the LDPC decode block  11  supplies a decode successful flag to the control block  41 . Consequently, the control block  41  instructs the LDPC decode block  11  to output the decoding result. Next, in step S 34 , the LDPC decode block  11  outputs the decoding result. 
         [0069]    In step S 35 , the BER computation block  32  computes a BER on the basis of the log-likelihood ratio of the frame subject to the previous decoding and the decoding result supplied from the LDPC decode block  11  and supplies the obtained BER to the control block  41 . 
         [0070]    In step S 36 , the control block  41  determines whether the BER supplied from the BER computation block  32  is higher than a predetermined setting value that is preset. If the BER is found to be higher than the predetermined setting value in step S 36 , then the control block  41  determines whether a new frame start signal has been entered or not in step S 37 . 
         [0071]    If no new frame start signal is found entered in step S 37 , then the control block  41  waits until a new frame start signal is entered. 
         [0072]    On the other hand, if a new frame start signal is found entered in step S 37 , then the frame start counter  42  increments the count value by 1 under the control of the control block  41  in step S 38 . It should be noted that the initial value of the count value is 1. 
         [0073]    In step S 39 , the control block  41  determines whether the count value is equal to the predetermined setting value or not. If the count value is found to be not equal to the predetermined setting value, the processing procedure is returned to step S 37 . Then, until the count value becomes the predetermined setting value, the processing operations of step S 37  through step S 39  are repeated. 
         [0074]    On the other hand, if the count value is found to be equal to the predetermined setting value in step S 39 , then the frame start counter  42  initializes the count value to 1 under the control of the control block  41  in step S 40 . Next, the control block  41  supplies a decode enable signal of H level to the LDPC decode block  11 , returning the processing procedure to step S 31 . Consequently, the LDPC decoding for the log-likelihood ratio of a frame that is the (setting value−1)th frame from the frame subject to the previous decoding is executed. 
         [0075]    If the BER is found to be below a predetermined setting value in step S 36 , then the control block  41  determines in step S 41  whether a new frame start signal has been entered or not. If no new frame start signal is found entered in step S 41 , then the control block  41  waits until a new frame start signal is entered. 
         [0076]    On the other hand, if a new frame start signal is found entered in step S 41 , then the control block  41  supplies a decode enable signal of H level to the LDPC decode block  11 . The processing procedure is returned to step S 31 . Thus, the LDPC decoding for the log-likelihood ratio of a frame next to the frame subject to the previous decoding is executed. 
         [0077]    If the LDPC decoding is found unsuccessful in step S 33 , then the LDPC decode block  11  supplies a decode unsuccessful signal to the control block  41 . In step S 42 , the control block  41  determines whether a new frame start signal has been entered or not. 
         [0078]    If no new frame start signal is found entered in step S 42 , then the control block  41  instructs the LDPC decode block  11  to execute decoding and returns the processing procedure to step S 32 . Next, the processing operations of steps S 32 , S 33 , and S 42  are repeated until the LDPC decoding is successful or a new frame start signal is entered. 
         [0079]    On the other hand, if a new frame start signal is found entered in step S 42 , then the control block  41  instructs the LDPC decode block  11  to output a decoding result. Next, in step S 43 , the LDPC decode block  11  outputs a decoding result in response to the instruction supplied from the control block  41 . 
         [0080]    Thus, the receiving apparatus  30  is able to repeat the LDPC decoding until the LDPC decoding is successful during a period of time where a frame start signal of a frame next to the frame subject to the current decoding. 
         [0081]    In step S 44 , the BER computation block  32  computes a BER on the basis of the log-likelihood ratio of the frame subject to the previous decoding and the decoding result supplied from the LDPC decode block  11  and supplies the obtained BER to the control block  41 . 
         [0082]    In step S 45 , the control block  41  determines whether the BER supplied from the BER computation block  32  is higher than a preset predetermined setting value. If the BER is found to be higher than the preset determined setting value in step S 45 , then the processing procedure goes to step S 38  to execute the subsequent processing. 
         [0083]    On the other hand, if the BER is found to be below the predetermined setting value in step S 45 , the control block  41  enters a decode enable signal of H level into the LDPC decode block  11 , returning the processing procedure to step S 31 . Thus, the LDPC decoding for the log-likelihood ratio of a frame next to the frame subject to the previous decoding is executed. 
         [0084]    Referring to  FIG. 7 , there is shown a timing chart indicative of operations timings of the receiving apparatus  30  in the case where the BER is higher than a predetermined setting value. 
         [0085]    As shown in  FIG. 7 , first, when a frame start signal of a first frame is entered, the control block  41  enters a decode enable signal of H level into the LDPC decode block  11 . This causes the LDPC decode block  11  to receive the log-likelihood ratio of the first frame and executes the LDPC decoding on this log-likelihood ratio. At this time, the count value of the frame start counter  42  is 1 as initial value. It should be noted that, when the reception of the log-likelihood ratio of the first frame has been completed, the decode enable signal goes L level. 
         [0086]    In the example shown in  FIG. 7 , the LDPC decoding of the first frame is unsuccessfully repeated until the reception of the log-likelihood ratio of a second frame next to the first frame and a decoding result is outputted. Also, in the example shown in  FIG. 7 , the BER is higher than the setting value, so that, when the frame start signal of the second frame is entered, the count value is incremented to 2. 
         [0087]    If the setting value for use in count value determination is 4 for example, the log-likelihood ratio of the second frame is received as shown in  FIG. 7  but no LDPC decoding is executed because the count value is 2. Then, when the log-likelihood ratio of a third frame is entered, the log-likelihood ratio of the third frame is received and the count value is incremented by 1 to 3. In this case, too, the count value is not 4, so that the LDPC decoding of the third frame is not executed. 
         [0088]    Next, when a frame start signal of a fourth frame is entered, the log-likelihood ratio of the fourth frame is received and the count value is incremented by 1 to 4. In this case, because the count value is 4, the decode enable signal goes H level and, at the same time, the count value is initialized to 1, thereby executing the LDPC decoding of the fourth frame. 
         [0089]    Subsequently, the LDPC decoding is executed on every three frames until the BER goes below a predetermined setting value as described above. That is, the LDPC decoding of the first frame, the fourth frame, . . . , (3n+1)th frame (n being an integer greater than or equal to 0) is executed. 
         [0090]    The power consumption of the receiving apparatus is dominant at the time of LDPC decoding, so that the receiving apparatus  30  executes the LDPC decoding on every three frames, thereby reducing the power consumption to 1/3 of a situation in which the LDPC decoding is executed on every frame. 
         [0091]    In addition, if the BER is higher than a predetermined setting value, the receiving apparatus  30  executes the LDPC decoding at predetermined intervals, so that the receiving apparatus  30  is able to compute the BER at predetermined intervals. As a result, if the BER goes below a predetermined threshold value, the LDPC decoding can be restarted. Therefore, the receiving apparatus  30  is able to hold down the power consumption in bad conditions when the BER is in a low condition, namely, while LDPC codes in good conditions are LDPC-decoded. 
         [0092]    It should be noted that the frequency of LDPC codes in the case where the BER is higher than a predetermined setting value is not obviously limited to the frequency of every three frames. For example, if the frequency of LDPC decoding is every 10 frames, the power consumption is reduced to 1/10 of the case shown in  FIG. 4 . 
       [Relation Between Power Consumption and Ber] 
       [0093]    Referring to  FIG. 8 , there is shown a relation between power consumption and BER. 
         [0094]    In  FIG. 8 , the horizontal axis is representative of C/N (Carrier to Noise ratio) (dB) of transmission path and the vertical axis is representative of the power consumption and BER at the time of LDPC decoding of the log-likelihood ratio. 
         [0095]    As shown in  FIG. 8 , it is seen that there is a strong correlation between BER and power consumption. To be more specific, as the BER gets higher, the power consumption at the time of LDPC decoding gets higher and, as the BER gets lower, the power consumption at the time of LDPC decoding gets lower. Therefore, the employment of BER an the index of frequency control of the LDPC decoding provides large power consumption reduction effects. 
         [0096]    As described above, the receiving apparatus  30  receives an LDPC code, decodes the received LDPC code, and, on the basis of the BER that is conditional information, controls the frequency of the LDPC decoding, so that the receiving apparatus  30  is able to hold down the power consumption in bad conditions while decoding LDPC codes in good conditions. 
         [0097]    It should be noted that, for the conditional information by which the frequency of LDPC decoding is controlled, noise information, such as signal-to-noise ratio (SNR), C/N, noise power, and noise amount, that can be computed by a demodulator (not shown) arranged on the preceding stage of the receiving apparatus  30  can be used. 
         [0098]    However, the correlation between noise information and BER may not be constant depending on modulation scheme, code rate, and type of external disturbance, for example. For example, in a phase noise environment, there occurs a situation in which C/N is good but BER is bad. Therefore, in order to reduce the power consumption more effectively, it is required to set setting values for use in noise information determination by considering the correlation between noise information and BER for each case. 
       Second Embodiment 
     Exemplary Configuration of Receiving Apparatus Practiced as Second Embodiment 
       [0099]    Referring to  FIG. 9 , there is shown a block diagram illustrating an exemplary configuration of a receiving apparatus practiced as the second embodiment of the invention. 
         [0100]    With reference to  FIG. 9 , components similar to those previously described with reference to  FIG. 1  are denoted the same reference numerals. The description duplicate with that made with reference to  FIG. 1  is skipped appropriately. 
         [0101]    The configuration of a receiving apparatus  50  shown in  FIG. 9  differs from that shown in  FIG. 1  mainly in that a repetition count control block  51  is arranged in place of the repetition count control block  12 . The receiving apparatus  50  uses the count of unsuccessful LDPC decoding until a new log-likelihood ratio is received (this count is hereafter referred to as a decode unsuccessful count) as conditional information that provides an index of frequency control. The decode unsuccessful count increases as the error in decoding results increases, so that there is a correlation between the decode unsuccessful count and BER. 
         [0102]    The repetition count control block  51  shown in  FIG. 9  is composed of a control block  61 , frame start counters  62  and  63 , and a decode unsuccessful counter  64 . In the repetition count control block  51 , a frame start signal is entered. 
         [0103]    The control block  61  controls the frequency of decoding by entering a decode enable signal into an LDPC decode block  11  on the basis of the count values of the frame start counters  62  and  63 , and the decode unsuccessful counter  64 . 
         [0104]    If a decode successful flag is supplied from the LDPC decode block  11 , the control block  61  instructs the LDPC decode block  11  to output a decoding result. On the other hand, if a decode unsuccessful flag is supplied from the LDPC decode block  11 , the control block  61  instructs the LDPC decode block  11  to execute decoding again before the log-likelihood ratio of a next frame is received; when the log-likelihood ratio of the next frame is received, the control block  61  instructs the LDPC decode block  11  to output a decoding result. 
         [0105]    Further, the control block  61  controls the frame start counter  63  on the basis of a count value of the frame start counter  62  and a decode suppression enable signal indicative of the suppression or non-suppression of decode frequency supplied from the decode unsuccessful counter  64 . In addition, the control block  61  controls the decode unsuccessful counter  64  on the basis of a count value of the frame start counter  62 . 
         [0106]    The frame start counter  62  counts the input count of frame start signals. The frame start counter  63  counts the input count of a frame start signal under the control of the control block  61 . The decode unsuccessful counter  64  counts a count of decode unsuccessful flags supplied from the LDPC decode block  11  under the control of the control block  61 . The decode unsuccessful counter  64  supplies a decode suppression enable signal to the control block  61  on the basis of the count value. 
       [Processing by the Receiving Apparatus] 
       [0107]    Referring to  FIG. 10 , there is shown a flowchart indicative of the decode processing to be executed by the receiving apparatus  50 . This decode processing starts when a decode enable signal of H level is entered in the LDPC decode block  11  in response to a frame start signal of the start frame, for example. 
         [0108]    In step S 61 , the LDPC decode block  11  receives the log-likelihood ratio for each frame from the outside. After the reception, a decode enable signal goes L level. In step S 62 , the LDPC decode block  11  executes the LDPC decoding by use of the received log-likelihood ratio. In step S 63 , the LDPC decode block  11  determines on the basis of a decoding result whether the LDPC decoding is successful or not. 
         [0109]    If the LDPC decoding is found successful in step  63 , the LDPC decode block  11  supplies a decode successful flag to the control block  61 . In response, the control block  61  instructs the LDPC decode block  11  to output a decoding result. Next, in step S 64 , the LDPC decode block  11  outputs the decoding result. 
         [0110]    In step S 65 , the control block  61  determines whether a new frame start signal has been entered or not. If no new frame start signal is found entered in step S 65 , then the control block  61  waits until a new frame start signal is entered. 
         [0111]    On the other hand, if a new frame start signal is found entered in step S 65 , then the frame start counter  62  increments count value A by 1 in step S 66 , upon which the processing procedure goes to step S 71 . It should be noted that the initial value of count value A is 1. 
         [0112]    If the LDPC decoding is found unsuccessful in step S 63 , then the LDPC decode block  11  supplies a decode unsuccessful flag to the control block  61 . Next, in step S 67 , the control block  61  determines whether a new frame start signal has been entered or not. If no new frame start signal is found entered in step S 67 , the processing procedure returns to step S 62 , in which the processing operations of steps S 62 , S 63 , and S 67  are repeated until the LDPC decoding is successful or a new frame start signal is entered. 
         [0113]    If a new frame start signal is found entered in step S 67 , then the LDPC decode block  11  outputs a decoding result in step S 68 . In step S 69 , the decode unsuccessful counter  64  increments count value B by 1. It should be noted that the initial value of count value B is 0. In step S 70 , the frame start counter  62  increments count value A by 1, upon which the processing procedure goes to step S 71 . 
         [0114]    In step S 71 , the frame start counter  62  determines whether count value A is preset predetermined setting value or not. If count value A is found to be a predetermined setting value in step S 71 , then the frame start counter  62  initializes count value A to 1 in step S 72 . 
         [0115]    In step S 73 , the decode unsuccessful counter  64  determines count value B is higher than a preset predetermined setting value or not. If count value B is found to be higher than the predetermined setting value in step S 73 , then the decode unsuccessful counter  64  sets the level of a decode suppression enable signal to H level indicative of the suppression of signal frequency in step S 74 . This decode suppression enable signal is entered in the control block  61 . 
         [0116]    In step S 75 , the decode unsuccessful counter  64  initializes count value B to 0. In step S 76 , the control block  61  determines whether a new frame start signal has been entered or not. If no new frame start signal is found entered in step S 76 , the control block  61  waits until a new frame start signal is entered. 
         [0117]    On the other hand, if a new frame start signal is found entered in step S 76 , then the frame start counter  63  increments count value C by 1 in step S 77 . It should be noted that the initial value of count value C is 1. 
         [0118]    In step S 78 , the frame start counter  63  determines whether count value C is a preset predetermined setting value. If count value C is found not to be the predetermined setting value in step  78 , the processing procedure returns to step S 76 , in which the processing operations of steps S 76  through S 78  are repeated until count value C becomes the predetermined setting value. 
         [0119]    On the other hand, if count value C is found to be the predetermined setting value in step S 78 , then the frame start counter  63  initializes count value C to 1 in step S 79 , upon which the processing procedure returns to step S 61 . Consequently, the LDPC decoding for the log-likelihood ratio of a frame that is the (setting value−1)th frame from the frame subject to the previous decoding is executed. 
         [0120]    As described above, in the receiving apparatus  50 , if a ratio of decode unsuccessful frames to a predetermined number of frames is higher than a predetermined ratio, the frequency of LDPC decoding is controlled such that the LDPC decoding is executed on every (setting value−1) frames. 
         [0121]    On the other hand, if count value B is found to be lower than the predetermined setting value in step S 73 , then the decode unsuccessful counter  64  sets the level of a decode suppression enable signal to be entered into the control block  61  to L level indicative of non-suppression of decode frequency. 
         [0122]    In step S 81 , the decode unsuccessful counter  64  initializes count value B to 0, upon which the processing procedure returns to step S 61 . Consequently, the LDPC decoding for the log-likelihood ratio of a frame next to the frame subject to the previous decoding. That is, in the receiving apparatus  50 , if a ratio of decode unsuccessful frames to a predetermined number of frames is lower than a predetermined ratio, the LDPC decoding is executed on every frame. 
         [0123]    If count value A is found to be not the setting value in step S 71 , then the control block  61  determines in step S 82  whether the level of a decode suppression enable signal entered from the decode unsuccessful counter  64  is H level or not. If the level of a decode suppression enable signal is found to be H level in step S 82 , the procedure goes to step S 76 , in which the subsequent processing operations are executed therefrom. That is, the frequency of the LDPC decoding is controlled such that the LDPC decoding is executed on every (setting value−1) frames. 
         [0124]    On the other hand, if the level of a decode suppression enable signal is found to be L level in step S 82 , then the processing procedure returns to step S 61 , in which the subsequent processing operations are executed therefrom. That is, the LDPC decoding is executed on every frame. 
         [0125]    Thus, the frequency of LDPC decoding is controlled for each of the predetermined number of frames in the receiving apparatus  50 . 
         [0126]    Referring to  FIG. 11 , there is shown a timing chart indicative of operation timings of the frame start counters  62  and  63  and the decode unsuccessful counter  64  in the receiving apparatus  50 . 
         [0127]    In the example shown in  FIG. 11 , the receiving apparatus  50  failed executing the LDPC decoding of the first through third frames. It is assumed that the setting value for use in the determination of a count value of the frame start counter  62  be 4 and the setting value for use in the determination of a count value of the decode unsuccessful counter  64  be 2. 
         [0128]    In this case, as shown in  FIG. 11 , every time a frame start signal is entered, the frame start counter  62  increments count value A by 1 from initial value 1 to setting value 4 and initializes count value A to 1 when count value A has reached setting value 4. In addition, every time a decode unsuccessful flag is entered during a period in which count value A reaches setting value 4, the decode unsuccessful counter  64  increments count value B by 1 from initial value 0. In the example shown in  FIG. 11 , the decoding of the first through third frames was unsuccessful, so that the count value B is incremented up to 3 and initialized to 0 when count value A has reached 4. 
         [0129]    When count value A has reached 4, count value B is 3, higher than setting value 2, so that the level of the decode suppression enable signal goes H level. It should be noted that, in the example shown in  FIG. 11 , the initial level of the decode suppression enable signal is L level. 
         [0130]    When the level of the decode suppression enable signal goes H level, the frame start counter  63  increments count value C by 1 from initial value 1 every time a frame start signal is entered. At this moment, count value A of the frame start counter  62  and count value B of the decode unsuccessful counter  64  remain unchanged at the initial values. 
         [0131]    Next, when count value C of the frame start counter  63  has reached a predetermined value, the frame start counter  62  and the decode unsuccessful counter  64  restart counting, repeating the above-mentioned processing operations. 
         [0132]      FIG. 12  and  FIG. 13  are timing charts indicative of operation timings of the control block  61  of the receiving apparatus  50 . 
         [0133]      FIG. 12  shows operation timings at the time when the level of a decode suppression enable signal goes from L level to H level.  FIG. 13  shows operation timings at the time when the level of the decode suppression enable signal goes from H level to L level. 
         [0134]    As shown in  FIG. 12 , when the level of the decode suppression enable signal goes from H level to L level, the frequency of decoding changes from (1/1) to 1/(setting value−1) (1/10 in the example shown in FIG.  12 ) for each frame. As shown in  FIG. 13 , when the level of the decode suppression enable signal goes from L level to H level, the frequency of decoding is changed from 1/(setting value−1) (1/10 in the example shown in  FIG. 13 ) to (1/1) for each frame. 
         [0135]    It should be noted that a predetermined setting value for use in the determination of count value C may be changed from time to time and the frequency of decoding may be changed stepwise. In this case, when the frequency of decoding is gradually changed to 1/1 to 1/2 to 1/4 to 1/10 in this order as shown in  FIG. 14 , for example. When the level of the decode suppression enable signal is changed from H level to L level, the frequency of decoding is gradually changed to 1/10 to 1/4 to 1/2 to 1/1 in this order as shown in  FIG. 15 , for example. Therefore, in this case, an abrupt power supply variation can be suppressed. This technique of gradually changing the frequency of decoding is applicable to the first embodiment of the invention. 
         [0136]    It should be noted that the receiving apparatus  50  described above uses the unsuccessful count of LDPC decoding as conditional information; it is also practicable to use, as the conditional information, such statistical values as decoding count and integrated value of decoding counts that are correlated with BER. 
       Third Embodiment 
     Exemplary Configuration of Receiving Apparatus Practiced as Third Embodiment 
       [0137]    Referring to  FIG. 16 , there is shown a block diagram illustrating an exemplary configuration of a receiving apparatus practiced as the third embodiment of the invention. 
         [0138]    With reference to  FIG. 16 , components similar to those previously described with reference to  FIG. 5  are denoted the same reference numerals. The description duplicate with that made with reference to  FIG. 5  is skipped appropriately. 
         [0139]    The configuration of a receiving apparatus  70  shown in  FIG. 16  differs from that shown in  FIG. 5  mainly in that a repetition count control block  71  is arranged in place of the repetition count control block  31 . The receiving apparatus  70  controls the speed of LDPC decoding on the basis of a free time in which LDPC decoding is not executed, from the output of a decoding result of a predetermined frame to the reception of a log-likelihood ratio of a next frame. 
         [0140]    To be more specific, the repetition count control block  71  is composed of a control block  81  and a frame start counter  42 . In the repetition count control block  71 , a frame start signal is entered. 
         [0141]    On the basis of a BER supplied from a BER computation block  32  and a count value of the frame start counter  42 , the control block  81  enters a decode enable signal into an LDPC decode block  11  to control the frequency of decoding. 
         [0142]    If a decode success flag is supplied from the LDPC decode block  11 , the control block  81  instructs the LDPC decode block  11  to output a decoding result. On the other hand, if a decode unsuccessful flag is supplied from the LDPC decode block  11 , the control block  81  instructs the LDPC decode block  11  to execute decoding again before the log-likelihood ratio of a next frame is received and further instructs the LDPC decode block  11  to output a decoding result when the log-likelihood ratio of the next frame is received. 
         [0143]    Further, the control block  81  computes a free time on the basis of a reception interval of the log-likelihood ratio, namely, an input interval of a frame start signal, and the output timing of a decoding result. On the basis of the obtained free time, the control block  81  controls the frequency of an operation clock of an LDPC decode, thereby controlling decoding speed. 
       [Processing by the Receiving Apparatus] 
       [0144]    Referring to  FIG. 17 , there is shown a flowchart indicative of decoding speed control processing to be executed by the receiving apparatus  70 . This decoding speed control processing starts when the frame start signal of a start frame is entered in the receiving apparatus  70 . 
         [0145]    In step S 101 , the control block  81  determines whether the LDPC decode block  11  has been instructed to output a decoding result. If the LDPC decode block  11  is found not instructed to output a decoding result in step S 101 , then the control block  81  waits until the LDPC decode block  11  is instructed to output a decoding result. 
         [0146]    On the other hand, if the LDPC decode block  11  is found instructed to output a decoding result in step S 101 , then the control block  81  determines in step S 102  whether the reception by the LDPC decode block  11  of the log-likelihood ratio of a frame next to the frame subject to the previous decoding has ended or not. If the reception is found not ended in step S 102 , then the control block  81  waits until the reception ends. 
         [0147]    If the reception is found ended in step S 102 , then, in step S 103 , the control block  81  computes, as a free time, a period of time from instructing the LDPC decode block  11  to output a decoding result to the end of reception of the log-likelihood ratio of a frame next to the frame subject to the previous decoding. 
         [0148]    In step S 104 , the control block  81  determines whether the computed free time is within a predetermined range set in advance. If the free time is found within a predetermined range in step S 104 , the control block  81  determines that the decoding speed is optimum, upon which the processing procedure returns to step S 101 . 
         [0149]    On the other hand, if the free time is found not within a predetermined range in step S 104 , then the control block  81  determines in step S 105  whether the free time is smaller than the predetermined range or not. If the free time is found smaller than the predetermined range in step S 105 , then the control block  81  determines that the decoding speed is slow and, in step S 106 , raises the frequency of the operation clock of the LDPC decoding to be executed by the LDPC decode block  11 . Next, the processing procedure returns to step S 101  to repeat the above-mentioned processing operations therefrom. 
         [0150]    If the free time is found greater than the predetermined range in step S 105 , then the control block  81  determines that the decoding speed is fast and, in step S 107 , lowers the frequency of the operation clock of the LDPC decode block  11 . Next, the processing procedure returns to step S 101  to repeat the processing operations therefrom. 
         [0151]    It should be noted that the decoding processing by the receiving apparatus  70  is substantially the same as that by the receiving apparatus  30  shown in  FIG. 6 , so that the description of the decoding processing by the receiving apparatus  70  is skipped. 
       [Description of Effects] 
       [0152]      FIG. 18  and  FIG. 19  illustrate the effects to be achieved by the receiving apparatus  70 . 
         [0153]    Referring to  FIG. 18 , there is shown a timing chart indicative of operation timings of the receiving apparatus that does not control the speed of LDPC decoding. Referring to  FIG. 19 , there is shown a timing chart indicative of operation timings of the receiving apparatus  70  that controls the speed of LDPC decoding. 
         [0154]    As shown in  FIG. 18 , in the receiving apparatus that does not control the speed of LDPC decoding, LDPC decoding is executed immediately after the end of reception of the log-likelihood ratio, thereby increasing the power consumption; however, LDPC decoding is not executed during a period from a successful decoding to the capture of the log-likelihood ratio of a next frame, thereby causing the power consumption to be low. For example, as shown in  FIG. 18 , a difference of the power consumption is P between the power consumption during time t from the reception of the log-likelihood ratio of the first frame and the power consumption during a period from a successful decoding to the reception of the log-likelihood ratio of a next frame. 
         [0155]    By contrast, as shown in  FIG. 19 , on the basis of the free time of a frame subject to the previous decoding, the receiving apparatus  70  that controls the speed of LDPC decoding changes the frequency of the operation clock of the LDPC decode block  11  such that the free time of the frame subject to the current decoding gets within a predetermined range. That is, the receiving apparatus  70  averages the operations of LDPC decoding by use of a time obtained by subtracting the time in a predetermined range from the free time. 
         [0156]    In the example shown in  FIG. 19 , the frequency of the operation clock is made 1/4 times the frequency of the operation clock in the case shown in  FIG. 18 . Consequently, a time from the reception of the log-likelihood ratio of the first frame to the output of a decoding result is 4t, thereby averaging the power consumption within 4t time to P/4. As a result, the peak value of the power consumption can be lowered while a total amount of the power consumption remains unchanged and, at the same time, the variation in power supply can be held down. 
         [0157]    As described above, the receiving apparatus  70  is able to receive a log-likelihood ratio to LDPC-decode the received log-likelihood ratio and, on the basis of the reception interval of this log-likelihood ratio, control the speed of LDPC decoding, thereby suppressing the drastic change in power consumption. 
         [0158]    It should be noted that, in the receiving apparatus  70 , the speed of LDPC decoding is controlled on the basis of the free time of the frame subject to the previous decoding; however, it is also practicable to control the speed of LDPC decoding on the basis of a log-likelihood ratio receiving interval of each frame. This receiving interval can be computed trough a demodulator, not shown, arranged in the preceding stage of the receiving apparatus  70  from the number of symbols per frame and a symbol rate. 
         [0159]    Also, the receiving apparatus  70  suppresses power supply variation by controlling the decoding speed by controlling the frequency of the operation clock of the LDPC decode block  11 ; however, the method of suppressing power supply variation is not limited thereto. For example, power supply variations may be suppressed by controlling the power supply voltage of the LDPC decode block  11  or controlling the voltage to be applied to a substrate terminal of a transistor making up the LDPC decode block  11 . 
         [0160]    In addition, the method of controlling the decoding speed described with respect to the third embodiment of the invention is also applicable to a receiving apparatus that does not control the frequency of decoding. 
         [0161]    Further, the speed of decoding may be changed stepwise like the frequency of decoding described above. In this case, if the frequency of the operation clock is changed from the normal frequency to 1/4 times thereof, the frequency of the operation clock is changed stepwise to 1, 1/2, and 1/4 times the normal frequency in this order. If the frequency of the operation clock is changed from 1/4 times the normal frequency to the normal frequency, the frequency of the operation clock is changed stepwise to 1/4, 1/2, and 1 times the normal frequency in this order. 
       [Configuration of a Receiving System] 
       [0162]    Referring to  FIG. 20 , there is shown a block diagram illustrating an exemplary first configuration of a receiving system applicable to the receiving apparatuses  30 ,  50 , and  70  described above. 
         [0163]    In  FIG. 20 , the receiving system is composed of an acquisition block  201 , a transmission path decode processing block  202 , and an information source decode processing block  203 . 
         [0164]    The acquisition block  201  acquires a signal that at least includes an LDPC code obtained by LDPC-decoding subject data, such as program&#39;s image data and audio data. For example, the acquisition block  201  acquires the signal via a transmission path, not shown, such as terrestrial digital broadcasting, satellite broadcasting, CATV (Cable Television) network, the Internet, or other networks and supplies the acquired signal to the transmission path decode processing block  202 . 
         [0165]    If the signal to be acquired by the acquisition block  201  is broadcast via a broadcasting station, terrestrial wave, satellite wave, CATV network, or the like, for example, the acquisition block  201  is configured by a tuner or STB (Set Top Box), for example. If the signal to be acquired by the acquisition block  201  is transmitted in a multicast manner as with IPTV (Internet Protocol Television) from a Web server, for example, the acquisition block  201  is configured by a network interface, such as NIC (Network Interface Card), for example. 
         [0166]    The transmission path decode processing block  202  executes transmission path decode processing at least including the processing of correcting an error caused on the transmission path on the signal acquired by the acquisition block  201  via transmission path and supplies a resultant signal to the information source decode processing block  203 . 
         [0167]    To be more specific, the signal acquired by the acquisition block  201  via transmission path is a signal obtained by at least executing error correction coding for correcting an error caused on the transmission path. So, the transmission path decode processing block  202  executes transmission path decode processing, such as error correction processing for example, on this signal. 
         [0168]    The error correction coding includes LDPC coding and Reed-Solomon coding, for example. Here, for the error correction code, at least LDPC coding is executed. 
         [0169]    Also, the transmission path decode processing may include the demodulation of modulated signals, for example. 
         [0170]    The information source decode processing block  203  executes information source decode processing including at least the processing of decompressing compressed information to the original information onto the signal with the transmission path decode signal executed. 
         [0171]    That is, the signal acquired by the acquisition block  201  via transmission path may have been executed with compression coding for compression information to reduce the amount of data i.e. image and audio data. If the signal is compressed, the information source decode processing block  203  executes information source decoding processing, such as decompression processing for decompressing the compressed information to the original information, onto the signal executed with transmission path decode processing. 
         [0172]    It should be noted that if the signal acquired by the acquisition block  201  via transmission path is not executed with compression coding, the information source decode processing block  203  does not execute the decompression processing for decompressing the compressed information to the original information. 
         [0173]    The decompression processing includes MPEG (Moving Picture Experts Group phase) decoding for example. The information source decode processing includes descrambling, for example, in addition to the decompression processing. 
         [0174]    In the receiving system configured as described above, the acquisition block  201  acquires, via transmission path, a signal compressed by MPEG coding for example in image and audio data for example, this signal further being executed with error correction processing such as LDPC coding for example, and supplies the compressed and error-corrected signal to the transmission path decode processing block  202 . 
         [0175]    The transmission path decode processing block  202  executes, as transmission decode processing, the processing similar to that of the receiving apparatuses  30 ,  50 , and  70  onto the LDPC code supplied from the acquisition block  201 , for example. The signal obtained as a result of the transmission path decode processing is supplied to the information source decode processing block  203 . 
         [0176]    The information source decode processing block  203  executes information source decode processing, such as MPEG decoding, on the signal supplied from the transmission path decode processing block  202  and outputs a resultant image or audio. 
         [0177]    The receiving system configured as described above is applicable to a television tuner for receiving television broadcasting as digital broadcasting, for example. 
         [0178]    It should be noted that the acquisition block  201 , the transmission path decode processing block  202 , and the information source decode processing block  203  may be each configured as a discrete device (a hardware device such as an IC (Integrated Circuit) for example or a software module). 
         [0179]    In addition, it is practicable to configure a set of two or all of the acquisition block  201 , the transmission path decode processing block  202 , and the information source decode processing block  203  as one independent apparatus. Such a set may include one composed of the acquisition block  201  and the transmission path decode processing block  202 , another composed of the transmission path decode processing block  202  and the information source decode processing block  203 , and still another composed of acquisition block  201  and the transmission path decode processing block  202 , and the information source decode processing block  203 , for example. 
         [0180]    Referring to  FIG. 21 , there is shown a block diagram illustrating a second exemplary configuration of a receiving system applicable to the receiving apparatuses  30 ,  50 , and  70  described above. 
         [0181]    With reference to  FIG. 21 , components similar to those previous described with reference to  FIG. 20  are denoted by the same reference numerals and the description of the duplicate components is skipped. 
         [0182]    The receiving system shown in  FIG. 21  is substantially common to the receiving system shown in  FIG. 20  in having the acquisition block  201 , the transmission path decode processing block  202 , and information source decode processing block  203  and is different from the receiving system shown in  FIG. 20  in an output block  204 . 
         [0183]    The output block  204  is a display apparatus for displaying images or a loudspeaker for sounding audio data, outputting image and audio data as a signal outputted from the information source decode processing block  203 . That is, the output block  204  displays images or outputs audio data. 
         [0184]    The receiving system shown in  FIG. 21  configured as described above is applicable to television receivers for receiving television broadcasting as digital broadcasting and radio receivers for receiving radio broadcasting. 
         [0185]    It should be noted that, if the signal acquired by the acquisition block  201  is not compressed, the signal outputted from the transmission path decode processing block  202  is supplied to the output block  204 . 
         [0186]    Referring to  FIG. 22 , there is shown a block diagram illustrating a third exemplary configuration of a receiving system applicable to the receiving apparatuses  30 ,  50 , and  70  described above. 
         [0187]    With reference to  FIG. 22 , components similar to those previously described with reference to  FIG. 20  are denoted by the same reference numerals and the description of the duplicate components is skipped. 
         [0188]    The receiving system shown in  FIG. 22  is substantially common to the receiving system shown in  FIG. 21  in having the acquisition block  201  and the transmission path decode processing block  202 . 
         [0189]    However, the receiving system shown in  FIG. 22  does not have the information source decode processing block  203  but has a recording control block  205  and a recording media  206 , which is a difference from the receiving system shown in  FIG. 21 . 
         [0190]    The recording control block  205  controls the recording of a signal (a TS packet of MPEG TS (Transport Stream) for example) outputted from the transmission path decode processing block  202  onto the recording media  206 , such as an optical disk, a hard disk (or a magnetic disk), or a flash memory. 
         [0191]    The receiving system configured as described above is applicable to recorders and the like for recording television broadcasting. 
         [0192]    It should be noted that, in  FIG. 22 , the receiving system can be configured by the information source decode processing block  203 , which can make the recording control block  205  record a signal with the information source decode processing executed, namely, image and audio data obtained by decoding, onto the recording media  206 . 
       [Application of the Present Invention to Programs] 
       [0193]    It should be noted that above-mentioned sequence of processing operations may be executed by software as well as hardware. 
         [0194]    In this case, a computer shown in  FIG. 23  can be used for at least a part of the receiving system that includes the receiving apparatuses  30 ,  50 , and  70  described above. 
         [0195]    In  FIG. 23 , a CPU (Central Processing Unit)  301  executes various processing operations as instructed by programs recorded to a ROM (Read Only Memory)  302 . The CPU  301  also executes various processing operations as instructed by programs stored in a storage block  308  and loaded into a RAM (Random Access Memory)  303 . The RAM  303  also stores data and so on necessary for the CPU  301  to execute various processing operations. 
         [0196]    The CPU  301 , the ROM  302 , and the RAM  303  are interconnected through a bus  304 . This bus  304  is also connected with an input/output interface  305 . 
         [0197]    The input/output interface  305  is connected with an input block  306  composed of a keyboard and a mouse for example, and an output block  307  composed of a display monitor for example. The input/output interface  305  is also connected with a storage block  308  composed of a hard disk drive for example and a communication block  309  composed of a modem and a terminal adaptor for example. The communication block  309  controls communication that is executed between other apparatuses, not shown, via a network including the Internet. 
         [0198]    The input/output interface  305  is also connected with a drive  310  as required, on which a removable media  311 , such as a magnetic disk, an optical disk, a magneto-optical disk or a semiconductor device, is appropriately loaded. Then, computer programs read from the removal media  311  are installed in the storage block  308  as required. 
         [0199]    When the above-mentioned sequence of processing operations is executed by software, the programs constituting the software are installed in a computer which is built in dedicated hardware equipment or installed, from a network or recording media, into a general-purpose personal computer for example in which various programs may be installed for the execution of various functions. 
         [0200]    The above-mentioned recording media is configured not only by the removable media  311  such as a magnetic disk (including a floppy disk), an optical disk (including CD-ROM (Compact Disk Read Only Memory), DVD (Digital Versatile Disk), a magneto-optical disk (including MD (Mini Disk) (trademark)), or a semiconductor memory recorded with programs for distribution of programs to users separately from the apparatus main, but also by the ROM  302  recorded with programs and a hard disk drive recorded with programs and included in the storage block  308  that are provided to users as incorporated in the apparatus main as shown in  FIG. 23 . 
         [0201]    It should be noted herein that the steps for describing each program recorded in recording media include not only the processing operations which are sequentially executed in a time-dependent manner but also the processing operations which are executed concurrently or discretely. 
         [0202]    It should also be noted that term “system” as used herein denotes an entire apparatus configured by a plurality of component units. 
         [0203]    While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purpose only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims. 
         [0204]    The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2009-131260 filed with the Japan Patent Office on May 29, 2009, the entire content of which is hereby incorporated by reference.