Abstract:
A method for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix includes generating an LDPC codeword by encoding information data bits, interleaving the LDPC codeword, mapping the interleaved LDPC codeword to a modulation signal, and generating a mapped signal by mapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part of said modulation signal, among bits constituting the modulation signal, generating a modulation signal by high-order-modulating the mapped signal and Radio Frequency (RF)-processing the modulation signal, and transmitting the RF-processed signal via a transmission antenna.

Description:
CLAIM OF PRIORITY  
       [0001]    This application claims the benefit of the earlier filing date, pursuant to 35 U.S.C. §119(a), to that Korean Patent Application filed in the Korean Intellectual Property Office on Nov. 8, 2007 and assigned Serial No. 2007-113641, the disclosures of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates wireless communication systems, and in particular, to an apparatus and method for transmitting and receiving data in a communication system using Low Density Parity Check (LDPC) codes. 
         [0004]    2. Description of the Related Art 
         [0005]    Generally, in communication systems, a data transmission/reception process can be outlined as: data generated in a source of a transmission side is wirelessly transmitted over a channel after undergoing source coding, channel coding, interleaving, and modulation and after receiving the wirelessly transmitted signal at the reception side, the reception side performs demodulation, deinterleaving, channel decoding, and source decoding on the received signal. 
         [0006]    However, in communication systems, distortion of signals occurs due to various noises, fading phenomena and Inter-Symbol Interference (ISI) of within and among the different transmission channels. In the high-speed digital communication system requiring high data throughput and high reliability, such as next-generation mobile communication, digital broadcasting and portable internet, a technology for coping with signal distortion caused by the noises, fading and ISI is indispensable. The channel coding and interleaving are typical of technologies that are used to mitigate the effects of noise fading and ISI in distorting transmitted signals. 
         [0007]    Interleaving is used for minimizing a data transmission loss and increasing a channel coding effect, as is more fully described below, by distributing a damaged portion of desired transmission bits over several places without concentrating the damaged portion on a single spot. The concentration of distorted bits is known in the art as a burst error which frequently occurs while a signal passes through a fading channel, and the distribution of the damaged portion over several places is used reduce the occurrence of a burst error within the transmission stream 
         [0008]    Channel coding is popularly used as a method for allowing a reception side to check signal distortion caused by noises, fading and ISI, and to efficiently restore the distorted signal, thereby increasing communication reliability. Codes used for channel coding are called Error-Correcting Codes (ECCs) as they enable the reception side to correct errors that have been detected. Intensive research is being conducted on various types of error-correcting codes. 
         [0009]    The well-known error-correcting codes include block codes, convolutional codes, turbo codes, and LDPC codes. Since the present invention is directed to a communication system using LDPC codes, a brief description of the LDPC codes is provided. 
         [0010]    The LDPC code is known as a code that can minimize information loss probability though it cannot guarantee perfect transmission of signals. The LDPC code, which was first proposed in 1960s, is the first channel coding code capable of transmitting signals at a rate approximating the maximum data rate (i.e., the Shannon limit) which is known in Shannon&#39;s channel coding theory. The LDPC code could not be substantially used since the -technology level in the 1960s was not sufficiently advanced to realize the LDPC code. However, as the LDPC code was rediscovered around 1996 owing to the succeeding information theory and the progress of technologies, a study is being made of characteristics of the LDPC code showing that its complexity does not considerably increase even though it uses iterative decoding, and a study is also being made of a method for generating the LDPC code. The LDPC code, together with the turbo code, is being suggested as a very superior error-correcting code useful for the next-generation mobile communication system. The LDPC code is commonly expressed using a graph representation, and its many characteristics can be analyzed using methods based on graph theory, algebra, and probability theory. Generally, a graph model of channel codes is useful for descriptions of codes, and if information on each coded bit corresponds to a vertex in the graph and relationships between the coded bits correspond to edges in the graph, the vertexes can be considered as communication networks that exchange predetermined messages through the edges, making it possible to derive a natural decoding algorithm. For example, decoding algorithms induced from the trellis that can be regarded as a kind of graph can include the well-known Viterbi algorithm and Bahl, Cocke, Jelinek and Raviv (BCJR) algorithm. As such codes are well known in the art, a discussion of same need not be provided herein. 
         [0011]    The LDPC code is generally defined as a parity-check matrix, and can be represented using a bipartite graph, commonly referred to as a Tanner graph. The bipartite graph means that vertexes constituting the graph are divided into two different types, and for the LDPC code, the vertexes of two different types are variable nodes and check nodes. The variable nodes one-to-one correspond to coded bits. 
         [0012]    With reference to  FIGS. 1 and 2 , a description is illustrated of an exemplary graphical representation of the LDPC code. 
         [0013]      FIG. 1  is a diagram illustrating a parity-check matrix H 1  of an LDPC code. In  FIG. 1 , a parity-check matrix of an LDPC code, composed of 4 rows and 8 columns, is considered. The matrix of  FIG. 1  represents an LI)PC code for generating a length-8 codeword, as it has 8 columns. That is, the columns correspond to 8 coded bits. Although, the number of columns shown herein of length eight (8), it would be recognized by those skilled in the art that the number of columns may be increased or decreased without altering the scope of the invention. 
         [0014]      FIG. 2  illustrates a graphical representation for a parity-check matrix H 1  of an LDPC code. That is,  FIG. 2  is a diagram illustrating a Tanner graph corresponding to check matrix H 1  of  FIG. 1 . Referring to  FIG. 2 , the Tanner graph of the LDPC code is composed of 8 variable nodes x 1  ( 202 ), x 2  ( 204 ), x 3  ( 206 ), x 4  ( 208 ), x 5  ( 210 ), x 6  ( 212 ), x 7  ( 214 ) and x 8  ( 216 ), and 4 check nodes  218 ,  220 ,  222  and  224 . Here, an i th  column and a j th  row of the parity-check matrix H 1  of the LDPC code corresponds to a variable node x i  and a j th  check node, respectively. A value of 1, or a non-zero value, at the point where an i th  column and a j th  row of the parity-check matrix H 1  of the LDPC code intersect infers that an edge exists between the variable node x i  and the j th  check node on the Tanner graph as shown in  FIG. 2 . 
         [0015]    In the Tanner graph of the LDPC code, degrees of variable nodes and check nodes refers to the number of edges connected to the corresponding nodes, and the degree is equal to the number of non-zero entries in a column or row associated with the corresponding node in the parity-check matrix of the LDPC code. For example, in  FIG. 2 , degrees of the variable nodes x 1  ( 202 ), x 2  ( 204 ), x 3  ( 206 ), x 4  ( 208 ), x 5  ( 210 ), x 6  ( 212 ), x 7  ( 214 ) and x 8  ( 216 ) are 4, 3, 3, 3, 2, 2, 2 and 2, respectively, and degrees of the check nodes  218 ,  220 ,  222  and  224  are 6, 5, 5 and 5, respectively. In addition, the number of non-zero entries in the columns of the parity-check matrix H 1  of  FIG. 1 , corresponding to the variable nodes of  FIG. 2 , are coincident with the degrees 4, 3, 3, 3, 2, 2, 2 and 2 in that order, and the number of non-zero entries in the rows of the parity-check matrix H 1  of  FIG. 1 , corresponding to the check nodes of  FIG. 2 , are coincident with the degrees 6, 5, 5 and 5 in that order. 
         [0016]    As described above, coded bits are in a one-to-one correspondence with columns of the parity-check matrix, and a one-to-one correspondence to variable nodes on the Tanner graph. In addition, degrees of variable nodes that in a one-to-one correspondence to the coded bits are referred to as degrees of coded bits. 
         [0017]    For the LDPC code, it is known that higher-degree codeword bits are superior in decoding performance to lower-degree codeword bits. This is because compared with lower-degree variable nodes, higher-degree variable nodes acquire more information through iterative decoding, contributing to improvement of decoding performance. 
         [0018]    The LDPC code has been described so far. A description will now be made of a signal constellation to which Quadrature Amplitude Modulation (QAM) is applied, QAM is a high-order modulation scheme commonly used in communication systems. A QAM-modulated symbol is composed of a real part and an imaginary part, and various modulation symbols can be formed by differentiating magnitude and sign of the real part and the imaginary part. To find out characteristics of QAM, QAM will be described together with Quadrature Phase Shift Keying (QPSK) modulation. 
         [0019]      FIG. 3A  is a schematic diagram of a signal constellation for a general QPSK modulation scheme. In the constellation, y 0  determines a sign of a real part, and y 1  determines a sign of an imaginary part. That is, when y 0 =0, a sign of the real part is plus (+), and when y 0 =1, a sign of the real part is minus (−). In addition, when y 1 =0, a sign of the imaginary part is plus (+), and when y 1 =1, a sign of the imaginary part is minus (−). Since y 0  and y 1  are sign indication bits indicating signs of the real part and the imaginary part, respectively, they are equal in error occurrence probability. Thus, for QPSK modulation, constituent bits of (y 0 , y 1 ) corresponding to one modulation signal are equal in reliability. For y 0,q  and y 1,q , the second index ‘q’ refers to a q th  output of a modulation signal-constituting bit. 
         [0020]      FIG. 3B  is a schematic diagram of a signal constellation for a general 16-QAM modulation scheme. Constituent bits of (y 0 , y i , y 2 , y 3 ) corresponding to one modulation signal have the following definitions. Constituent bit y 0  and y 2  determine sign and magnitude of a real part, respectively, and constituent bit y 1  and y 3  determine sign and magnitude of an imaginary part, respectively. In other words, y 0  and y 1  determine signs of a real part and an imaginary part of a signal, and y 2  and y 3  determine magnitudes of a real part and an imaginary part of a signal. Since distinguishing sign of a modulated signal is easier than distinguishing magnitude, error occurrence probability for y 2  and y 3  is higher than error occurrence probability at y 0  and y 1 . Therefore, no-error probabilities, or reliabilities, of constituent bits, are R(y 0 )=R(y 1 )&gt;R(y 2 ) R(y 3 ). Here, R(y) represents reliability for a constituent bit y k , where k=0-3. Unlike the QPSK modulation signal, the QAM modulation signal (y 0 , y 1 , y 2 , y 3 ) has a characteristic that constituent bits are different in reliability. 
         [0021]    In 16-QAM modulation, wherein 4 bits constitute a signal, 2 bits determine signs of a real part and an imaginary part of the signal, and 2 bits only need to represent magnitudes of the real part and the imaginary part of the signal, so an order of (y 0 , y 1 , y 2 , y 3 ) and a role of each constituent bit are subject to change. 
         [0022]      FIG. 3C  is a schematic diagram of a signal constellation for a general 64-QAM modulation scheme. In this case, constituent bits of (y 0 , y 1 , y 2 , y 3 , y 4 , y 5 ) corresponding to one modulation signal, wherein bits y 0 , y 2  and y 4  determine sign and magnitude of a real part, and bits y 1 , y 3  and y 5  determine sign and magnitude of an imaginary part. Here, y 0  and y 1  determine signs of the real part and the imaginary part, respectively, and y 2 , y 3 , y 4  and y 5  determine magnitudes of the real part and the imaginary part, respectively. Since distinguishing sign of a modulated signal is easier than distinguishing magnitude, reliabilities of y 0  and y 1  are higher than reliabilities of y 2 , y 3 , y 4  and y 5 . For example, y 2  and y 3  are determined according to whether magnitude of a modulated symbol is greater or less than 4, and y 4  and y 5  are determined according to whether magnitude of a modulated symbol is closer to 4 or 0, centering on 2, or determined according to whether magnitude of a modulated symbol is closer 4 or 8, centering on 6. Therefore, a determining range of y 2  and y 3  is 4, and a determining range of y 4  and y 5  is 2. Thus, reliabilities of y 2  and y 3  are higher than reliabilities of y 4  and y 5 . In sum, no-error probabilities, or reliabilities, of constituent bits of a modulation signal are R(y 0 )=R(y 1 )&gt;R(y 2 )=R(y 3 )&gt;R(y 4 )=R(y 5 ). 
         [0023]    In 64-QAM modulation, wherein 6 bits constitute a signal, 2 bits determine signs of a real part and an imaginary part of the signal, and 4 bits represent magnitudes of the real part and the imaginary part of the signal. Therefore, order of modulation signal (y 0 , y 1 , y 2 , y 3 , y 4 , y 5 ) and roles of the constituent bits are subject to change. Even for a signal constellation of 256-QAM or higher, roles and reliabilities of modulation signal-constituting bits are changed in the same manner as above. That is, if one modulation signal is defined as (y 0 , y 1 , y 2 , y 3 , y 4 , y 5 , y 6 , y 7 ), then R(y 0 )=R(y 1 )&gt;R(y 2 )−R(y 3 )&gt;R(y 4 )=R(y 5 )&gt;R(y 6 )=R(y 7 ). 
         [0024]    Conventionally, however, when the communication system using LDPC codes performs interleaving/deinterleaving, the system uses an arbitrary interleaving/deinterleaving scheme regardless of the LDPC code or reliability characteristics of constituent bits of a high-order modulation signal, or uses an interleaving/deinterleaving scheme where only degrees of variable nodes or check nodes of the LDPC code are considered, thereby failing to minimize distortion of signals transmitted over a channel. In addition, as reliabilities of two consecutive constituent bits y 2i  and y 2i+1  in a modulation signal are equal, the system recognizes the two bits as one bit group rather than recognizing them as two separate bits for a real part and an imaginary part. The limitation on recognition prevents maximization of the LDPC code&#39;s performance. 
       SUMMARY OF THE INVENTION 
       [0025]    An aspect of the present invention provides a transmission/reception apparatus and method for reducing signal distortion in a communication system using an LDPC codeword. 
         [0026]    Further; the present invention provides an interleaving apparatus and method for improving performance of an LDPC codeword in a communication system using an LDPC codeword. 
         [0027]    Further, the present invention provides an apparatus and method for mapping modulation signal-constituting bits to improve performance of an LDPC codeword in a communication system using an LDPC codeword. 
         [0028]    According to one aspect of the present invention, there is provided a method for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix. The method includes generating an LDPC codeword by encoding information data bits, interleaving the LDPC codeword, mapping the interleaved LDPC codeword to a modulation signal, and generating a mapped signal by mapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part, among bits constituting the modulation signal, generating a modulation signal by high-order-modulating the mapped signal, and Radio Frequency (RF)-processing the modulation signal, and transmitting the RF-processed signal via a transmission antenna. 
         [0029]    According to another aspect of the present invention, there is provided an apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix. The apparatus includes an encoder for encoding information data bits and outputting an LDPC codeword, an interleaver for interleaving the LDPC codeword, a bit mapper for mapping the interleaved LDPC codeword to a modulation signal, and outputting a mapped signal by mapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part, among bits constituting the modulation signal; a modulator for high-order-modulating the mapped signal, and outputting a modulation signal, and a Radio Frequency (RF) processor for RF-processing the modulation signal, and transmitting the RF-processed signal via a transmission antenna. 
         [0030]    According to further another aspect of the present invention, a method for receiving data in a communication system using a Low Density Parity Check (LDPC) matrix includes: Radio Frequency (RF)-processing a signal received through a reception antenna, generating a demodulation signal by demodulating the RF-processed signal, demapping an LDPC codeword mapped to the demodulation signal, and generating a demapped signal by demapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part among the bits constituting the demodulation signal; deinterleaving the demapped LDPC codeword and decoding the deinterleaved LDPC codeword. 
         [0031]    According to yet another aspect of the present invention, an apparatus for receiving data in a communication system using a Low Density Parity Check (LDPC) matrix includes a Radio Frequency (RF) processor for RF-processing a signal received through a reception antenna, a demodulator for demodulating the RF-processed signal and outputting a demodulation signal, a bit demapper for demapping an LDPC codeword mapped to the demodulation signal, and outputting a demapped signal by demapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part among the bits constituting the demodulation signal, a deinterleaver for deinterleaving the bit-demapped LDPC codeword and a decoder for decoding the deinterleaved LDPC codeword. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]    The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which: 
           [0033]      FIG. 1  is a diagram illustrating an exemplary parity-check matrix H 1  of an LDPC code; 
           [0034]      FIG. 2  is a graph representation for an exemplary parity-check matrix H 1  of an LDPC code; 
           [0035]      FIG. 3A  is a schematic diagram of a conventional signal constellation for a general QPSK modulation scheme; 
           [0036]      FIG. 3B  is a schematic diagram of a conventional signal constellation for a general 16-QAM modulation scheme; 
           [0037]      FIG. 3C  is a schematic diagram of a conventional signal constellation for a general 64-QAM modulation scheme; 
           [0038]      FIG. 4  is a diagram illustrating a structure of a communication system using an LDPC code according to an embodiment of the present invention; 
           [0039]      FIG. 5  is a diagram illustrating structures of an interleaver and a bit mapper according to an embodiment of the present invention; 
           [0040]      FIGS. 6A and 6B  are diagrams illustrating an operation of an interleaver according to an embodiment of the present invention; 
           [0041]      FIGS. 7A and 7B  are diagrams illustrating interleaving and bit mapping method according to an embodiment of the present invention; and 
           [0042]      FIG. 8  is a diagram illustrating performance improvement based on a data transmission scheme according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0043]    Embodiments of the present invention are now described in detail with reference to the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein has been omitted for clarity and conciseness. Terms used herein are defined based on functions in the present invention and may vary according to users, operators&#39; intention or usual practices. Therefore, the definition of the terms should be made based on contents throughout the specification. 
         [0044]      FIG. 4  is a block diagram illustrating a structure of a communication system using an LDPC code according to an embodiment of the present invention. With reference to  FIG. 4 , a description will now be made of a structure of a communication system using an LDPC code according to an embodiment of the present invention. 
         [0045]    A transmitter  400  according to the present invention includes an encoder  411 , an interleaver  413 , a bit mapping into constellation or signal constellation bit mapper (hereinafter ‘bit mapper’ for short)  415 , and a modulator  417 . 
         [0046]    A receiver  450  according to the present invention includes a demodulator  457 , a signal constellation bit demapper (hereinafter ‘bit demapper’ for short)  455 , a deinterleaver  453 , and a decoder  451 . 
         [0047]    After operations of a transmitter and a receiver of the present invention are first described in brief with reference to  FIG. 4 , more detailed information regarding structures and operations of interleaver  413  and bit mapper  415  of the present invention will be described with reference to  FIG. 5 . 
         [0048]    According, in the communication system shown in  FIG. 4 , when an information data bit stream i is input to the transmitter  400 , the encoder  411  encodes the information data bit stream i using a predetermined scheme, and generates a codeword x. The codeword x represents and encoding of the data bit stream either with an error coding code type code or an encryption type code or combinations thereof As the encoder  411  is an LDPC encoder, the codeword generated by the encoder  411  is an LDPC codeword of the input data bit stream i or a representation thereof. 
         [0049]    The interleaver  413  interleaves the LDPC codeword x output from the encoder  411  using a predetermined scheme, and outputs an interleaved LDPC codeword b. An interleaving operation of the interleaver  413  is performed according to an interleaving scheme as described in further detail below. 
         [0050]    The bit mapper  415  performs signal constellation bit mapping on the bits output from the interleaver  413 , i.e., the interleaved LDPC codeword b, using a predetermined scheme. The bit mapper  415  performs mapping according to a mapping scheme in accordance with the principles of the present invention. The mapping scheme maps input bits to bits constituting a modulation symbol according to a degree characteristic of the LDPC codeword b, as is described in further detail below. 
         [0051]    The modulator  417  modulates the signal output from the bit mapper  415  using a predetermined scheme, and transmits the modulated signal via a transmission antenna (.ANT). 
         [0052]    The interleaver  413  and the bit mapper  415  of the present invention perform interleaving and bit mapping so as to minimize a Bit Error Rate (BER) or a codeword error rate (or Frame Error Rate (FER)) when the modulator  417  modulates the interleaved LDPC codeword b, thereby increasing the performance. 
         [0053]    Herein, the interleaver  413  and the bit mapper  415  are designed in such a manner that a relationship between codeword bits, which are an input signal to an interleaver, and modulation signal-constituting bits, which are an output signal of the bit mapper, satisfies the following rules. For purposes of illustrating the rules described herein, it is assumed that the number of bits of an LDPC codeword is N and 256-QAM modulation is used. However, it would be understood by those skilled in the art that the modulation scheme may be changed without altering the scope of the invention. 
         [0054]    In accordance with the principles of the invention, the LDPC codewords are ordered in descending order of degree, and divided into a plurality of groups. In this illustrated example, the number of groups is chosen as 8. But it would be recognized that this number may be increased or decreased with changing the scope of the invention. Thus, the LDPC codewords can be expressed such that codeword c=[G 0 , G 1 , G 2 , G 3 , G 4 , G 5 , G 6 , G 7 ], where G 0 =[c 1  c 2  c 3  . . . c N/8 ], G 1 =[c N/8+1  c N/8+2  c N/8+3  . . . c 2N/8 ], and G 7 =[c 7N/8+1  c 7N/8+2  c 7N/8+3  . . . c N ]. 
         [0055]    Rule 1) maps those bits belonging to the highest-degree group G 0  among the LDPC codeword bits to the highest-reliability bit y 0  or y 1  among the modulation signal-constituting bits. 
         [0056]    Rule 2) maps those N/8 bits belonging to G 1  among the LDPC codeword bits to the medium-reliability bit y 5  or y 4  among the modulation signal-constituting bits. 
         [0057]    Rule 3) maps those N/8 bits belonging to G 2  among the LDPC codeword bits to the lowest-reliability bit y 0  or y 7  among the modulation signal-constituting bits. 
         [0058]    Rule 4) maps those N/8 bits belonging to G 3  among the LDPC codeword bits to the lowest-reliability bit y 7  or y 6  among the modulation signal-constituting bits. If the LDPC codeword bits belonging to G 2  are mapped to y 6  in Rule 3), Rule 4) maps the LDPC codeword bits belonging to G 3  to y 7 , and if the LDPC codeword bits belonging to G 2  are mapped to y 7  in Rule 3), the LDPC codeword bits belonging to G 3  are mapped to y 6 . 
         [0059]    Rule 5) maps bits belonging to the remaining groups (G 4 , G 5 , G 6  and G 7 ) among the LDPC codeword bits to modulation signal-constituting bits which are not mapped to G 0 , G 1 , G 2  and G 3  by Rule 1) to Rule 4). 
         [0060]    A detailed description will now be made of methods in which bits are mapped according to the above rules. 
         [0061]    An example of Rule 1) maps N/8 bits corresponding to [c 1  c 2  c 3  . . . c N/8 ] in a codeword c=[c 1  c 2  c 3  . . . c N ] which are ordered in descending order of degree, to the highest-reliability bits among the modulation signal-constituting bits. For example, the N/8 bits are mapped to the highest-reliability bits y 0  in a modulation signal-constituting symbol. 
         [0062]    An example of Rule 2) maps N/8 bits corresponding to c=[c N/8+1  c N/8+2  c N/8+3  . . . c 2N/8 ] to the medium-reliability bits among the modulation signal-constituting bits. For example, the N/8 bits are mapped to bits y 5  when 256 QAM is used as a modulation scheme. 
         [0063]    An example of Rule 3) maps N/8 bits corresponding to c=[c 2N/8+1  c 2N/8+2  c 2N/8+3  . . . c 3N/8 ] to the lowest-reliability bits among the modulation signal-constituting bits. For example, the N/8 bits are mapped to bits y 6  when 256 QAM is used as a modulation scheme. 
         [0064]    An example of Rule 4) maps N/8 bits corresponding to c=[c 3N/8+1  c 3N/8+2  c 3N/8+3  . . . c 4N/8 ] to the lowest-reliability bits among the modulation signal-constituting bits. For example, the N/8 bits are mapped to bits y 7  when 256 QAM is used as a modulation scheme. 
         [0065]    When the relationship between the LDPC codeword bits and the modulation signal-constituting bits is established as stated above, it is possible to improve decoding performance of the LDPC codeword. Compared to the existing scheme, the key feature of the above rules is to divide more than two bits constituting a modulation signal into a real part and an imaginary part even though they are equal in reliability, regarding them as different bits. 
         [0066]    Although the conventional art finds an excellent mapping method by simply distinguishing only the error correction capabilities based on degrees and the reliabilities based on modulation signal-constituting bits, the present invention includes a mapping method by subdividing even the bits having the same reliability into a real part and an imaginary part. The reason why the mapping scheme to which the above rules are applied can obtain superior performance will be described in detail below. 
         [0067]    In the LDPC codeword, the higher-degree bits can obtain superior performance compared with the lower-degree bits. Thus, even though the higher-degree bits are mapped to the modulation signal-constituting bits having lower reliability, they can be sufficiently restored to the original signal in the decoding process. However, when a ratio of higher-degree bits among the codeword bits is higher, influence of the higher-degree bits increases in the decoding process. Thus, as many higher-degree bits are mapped to lower-reliability bits, the influencing power of the lower-reliability bits increases undesirably. Therefore, properly mixed-mapping modulation signal-constituting bits having higher reliability and modulation signal-constituting bits having lower reliability to higher-degree coded bits contributes to performance improvement rather than mapping modulation signal-constituting bits having lower reliability to all higher-degree coded bits. 
         [0068]    Further, as for lower-degree bits in the LDPC codeword, their performance can be improved by mapping the lower-degree bits to modulation signal-constituting bits that have higher reliability though their error correction capability is lower in the decoding process. However, if all of the lower-degree codeword bits are mapped to the higher-reliability modulation signal-constituting bits, all higher-degree codeword bits are mapped to lower-reliability modulation signal-constituting bits, causing an increase in influencing power of the lower-reliability bits. Further, if only the lower-reliability modulation signal-constituting bits are mapped to the lower-degree codeword bits, error correction capability of the lower-degree codeword bits suffers significant degradation, causing an error floor. Preferably, therefore, the lower-degree codeword bits are mapped to medium-reliability modulation signal-constituting bits. 
         [0069]    In order to obtain high quality performance when the mapping is performed as stated above, the mapping method can be properly applied when the number of higher-degree codeword bits is relatively large. 
         [0070]    Meanwhile, the receiver  450  receives the signal transmitted from the transmitter  400 , and outputs a signal through a reverse process of the transmitter  400 . That is, a signal received at the receiver  450  through a reception antenna ANT, is delivered to the demodulator  457 . The demodulator  457  demodulates the received signal using a demodulation scheme corresponding to the modulation scheme of the modulator  417  in the transmitter  400 , and outputs the demodulated signal to the bit demapper  455 . The bit demapper  455  bit-demaps the signal output from the demodulator  457  according to the mapping scheme carried out in the bit mapper  415  of the transmitter  400 , and then outputs the resulting signal to the deinterleaver  453 . The deinterleaver  453  deinterleaves the signal output from the bit demapper  455  according to the interleaving scheme applied by the interleaver  413  in the transmitter  400 , and outputs the resulting signal to the decoder  451 . The decoder  451  decodes the deinterleaved signal using a decoding scheme corresponding to the coding scheme applied in the encoder  411  of the transmitter  400 , restoring the final information data bits. 
         [0071]    Meanwhile, in  FIG. 4 , the signal output from the modulator  417  is transmitted via the transmission antenna after undergoing Radio Frequency (RF) processing in a separate RF transmitter (not shown) for RF signal transmission processing. Similarly, the signal received at the reception antenna is input to the demodulator  457  after undergoing RF processing in an RF receiver (not shown) for RF signal reception processing. 
         [0072]    The transmitter of the present invention is featured by the interleaver  413  and the bit mapper  415  that use the unequal reliability characteristics of the high-order modulation scheme, and the receiver of the present invention is featured by the deinterleaver  453  and the bit demapper  455  that use the unequal reliability characteristics of the high-order modulation scheme. 
         [0073]    With reference to  FIG. 5 , a detailed description will now be made of the operation of an interleaver and a bit mapper in accordance with the principals of the present invention.  FIG. 5  is a block diagram illustrating structures of an interleaver and a bit mapper according to an embodiment of the present invention. 
         [0074]    As illustrated in  FIG. 5 , the bit mapper  415  of  FIG. 4  is comprised of a demultiplexer (DEMUX)  521 . The mapping scheme shown in  FIG. 5  uses 256-QAM modulation signals. 
         [0075]    When a coded signal x is input to an interleaver  501 , the interleaver  501  interleaves the coded signal, and outputs a signal b. The interleaved signal b is input to the demultiplexer  521  where it is separated into a plurality of streams. That is, for 256-QAM, the interleaved signal b is separated into 8 streams, for example. In other words, the signals received through the structure of  FIG. 5  are demultiplexed into a plurality of streams after being interleaved according to the corresponding modulation scheme. 
         [0076]    The demultiplexer  521  generates modulation signal-constituting bits by separating a received stream (b 0 , b 1 , b 2  . . . ) into a plurality of streams, and in the present invention, determining which of the modulation signal-constituting bits the interleaved codeword bits constitute is important. First, LDPC codeword bits x 0 , x 1 , . . . , x N-2 , x N-1  are input to the interleaver  501 . An interleaving scheme is determined taking into account all of a bit mapping scheme for each modulation signal, degree distribution for each bit of the LDPC code, and reliability for each bit of the signal constellation. A detailed description thereof will be given below. 
         [0077]    Output bits b 0 , b 1 , . . . b N-2 , b N-1  of the interleaver  501  are input to the demultiplexer  521  where they are demultiplexed into bits constituting a modulation signal. That is, for 256-QAM, since a modulation signal is composed of 8 bits, input bits of the demultiplexer  521  are demultiplexed into 8 bits. Here, the bit mapping method is determined according to the mapping relation between the consecutively-received  8  bits b 0 , b 1 , b 2 , b 3 , b 4 , b 5 , b 6 , b 7  and the bits y 0 , y 1 , y 2 , y 3 , y 4 , y 5 , y 6 , y 7  constituting a signal. A detailed description will now be made of an interleaving scheme and a bit mapping method according to the present invention. The interleaver and bit mapper proposed by the present invention are designed by the above-stated rules. 
         [0078]    It can be understood in  FIG. 5  that y 0 , y 2 , y 4 , y 6  among the modulation signal-constituting bits y 0 , y 1 , y 2 , y 3 , y 4 , y 5 , y 6 , y 7  which are an output signal of the demultiplexer  521 , constitute a real part, and y 1 , y 3 , y 5 , y 7  constitute an imaginary part. A description will now be made of a design process for an interleaver according to an embodiment of the present invention. The design process for an interleaver according to the present invention follows the following steps. 
         [0079]    Step 1: The number of columns of an interleaver is determined so that it is equal to the number of bits used in a modulation symbol, i.e., the number of modulation signal-constituting bits. 
         [0080]    Step 2: A value determined by dividing a length of a codeword by the number of columns, determined in Step 1, is determined as the number of interleave rows. 
         [0081]    Step 3: LDPC codeword bits are written in the size-determined interleaver column by column. 
         [0082]    Step 4: One bit is read from each column in which codeword bits are written. 
         [0083]    Table 1 shows sizes of rows and columns of an interleaver based on each modulation scheme for the exemplary cases where a length of the codeword is 16200 and 64800. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 Number of rows 
                   
               
             
          
           
               
                 Modulation 
                 N = 648000 
                 N = 162000 
                 Number of columns 
               
               
                   
               
             
          
           
               
                 QPSK 
                 324000 
                 8100 
                 2 
               
               
                 16QAM 
                 162000 
                 4050 
                 4 
               
               
                 64QAM 
                 108000 
                 2700 
                 6 
               
               
                 256QAM  
                 8100 
                 2025 
                 8 
               
               
                   
               
             
          
         
       
     
         [0084]    With reference to  FIGS. 6A and 6B , a description will now be made of design and operation of the interleaver, with regard to a particular modulation scheme. In the following description, it is assumed that an LDPC matrix is sequentially ordered in the order of higher-degree rows. The reason for this ordering has been previously described above, as a degree of a codeword bit corresponding to a variable node of the LDPC matrix is higher, the decoding performance is superior. Therefore, corresponding bits of a codeword generated considering the descending-ordered LDPC matrix are also descending-ordered, and the descending-ordered codeword bits refers to an order of decoding performance of the bits. 
         [0085]      FIGS. 6A and 6B  are diagrams illustrating an operation of an interleaver according to an embodiment of the present invention. It is assumed that the interleaver of  FIGS. 6A and 6B  uses 256-QAM modulation and a length of an LDPC codeword is 64800. Design and operation of the interleaver will be described according to 4 steps. 
         [0086]    Referring to step 1, 8 columns are formed, the number of which is equal to the number of modulation signal-constituting bits used in 256-QAM. In Step 2, the number of interleave rows are determined as 64800/8=8100. In Step 3, LDPC codeword bits are sequentially written in each column. When the writing in each column is completed, writing in the next column is carried out as shown in the drawings. In this case, the number of bits written in each column is 8100, which is the number of rows, calculated above. In Step 4, bits are sequentially read from each column one by one. In  FIG. 6A , bits are sequentially read from the first bit of a column number  1  to the first bit of a column number  8 , and then, bits are sequentially read from the second bit of the column number  1  to the second bit of the column number  8 . This process is repeated 8100 times, which is equal to the number of interleave rows. 
         [0087]    Through the above process, the LDPC codeword is interleaved. In addition, in order to additionally increase interleaving performance, arbitrary interleaving can be performed even within each column. If there is correlation between adjacent codeword bits, they can undergo interleaving to be more robust against a burst error. 
         [0088]    The interleaving scheme has been described so far. A description will now be made of a bit mapping scheme proposed by the present invention. The bit mapping scheme described below maps the highest-degree codeword bit to one of the highest-reliability bits among modulation signal-constituting bits, based on reading of one row during interleaving reading of an LDPC codeword, and then, maps the second highest-degree codeword bit to one of the lower-reliability bits among the modulation signal-constituting bits, thereby minimizing the total BER. 
         [0089]    Of the output values of the interleaver described in  FIGS. 6A and 6B , codeword bits read from a column number  1  are allocated to the highest-reliability bits among the modulation signal-constituting bits, and codeword bits read from a column # 3  and a column # 4  are allocated to a lowest reliability bits among the modulation signal-constituting bits. When an interleaver is considered that sequentially reads bits from the bit of the column number  1  to the bit of the column number  8  as shown in  FIG. 6A , (right side) an embodiment of the scheme in which output bits of the interleaver are allocated to modulation signal-constituting bits according to 256 QAM modulation, is illustrated in Table 2. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
             
             
               
                   
                 &lt;256 QAM - Method 1&gt; 
                 b 8k+0  mapped to y 0,k   
               
               
                   
                   
                 b 8k+1  mapped to y 5,k   
               
               
                   
                   
                 b 8k+2  mapped to y 6,k   
               
               
                   
                   
                 b 8k+3  mapped to y 7,k   
               
               
                   
                   
                 b 8k+4  mapped to y 1,k   
               
               
                   
                   
                 b 8k+5  mapped to y 4,k   
               
               
                   
                   
                 b 8k+6  mapped to y 2,k   
               
               
                   
                   
                 b 8k+7  mapped to y 3,k   
               
               
                   
                 &lt;256 QAM - Method 2&gt; 
                 b 8k+0  mapped to y 0,k   
               
               
                   
                   
                 b 8k+1  mapped to y 5,k   
               
               
                   
                   
                 b 8k+2  mapped to y 6,k   
               
               
                   
                   
                 b 8k+3  mapped to y 7,k   
               
               
                   
                   
                 b 8k+4  mapped to y 1,k   
               
               
                   
                   
                 b 8k+5  mapped to y 2,k   
               
               
                   
                   
                 b 8k+6  mapped to y 4,k   
               
               
                   
                   
                 b 8k+7  mapped to y 3,k   
               
               
                   
                   
               
             
          
         
       
     
         [0090]    In the above, when the number of codeword hits is N, output bits of the interleaver are expressed as b=b 0 , b 1 , b 2 , b 3 , b 4 , b 5 , b 6 , . . . , b N . In addition, k th  read modulation signal-constituting hits among the modulation signal-constituting bits are represented as y 0,k . For 256 QAM, the k th  read modulation signal-constituting bits are expressed as (y 0,k , y 1,k , y 2,k , y 3,k , y 4,k , y 5,k , y 6,k , y 7,k ), where k=0, 1, . . . , N/8-1. 
         [0091]    It can be understood from Table  2  that the bits corresponding to b 0  to b 7  satisfy all of Rules 1-4, recited above. In 256 QAM of Table 2, a modulation signal is composed of 8 bits, the number of the highest-reliability modulation signal-constituting bits is 2, the medium-reliability modulation signal-constituting bits is 4, and the lowest-reliability modulation signal-constituting bits is 2. Therefore, for 256 QAM, there are various possible interleavers that can be constructed according to the design rules of the present invention. That is, modifications of interleavers, that are conceptually equal to the two methods (i.e., &lt;256 QAM—Method 1&gt; and &lt;256 QAM—Method 2&gt;) shown in Table 2 are shown in Table 3. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
             
             
               
                   
                 &lt;256 QAM - Method 1, Modification&gt; 
                 b 8k+0  mapped to y 1,k   
               
               
                   
                   
                 b 8k+1  mapped to y 4,k   
               
               
                   
                   
                 b 8k+2  mapped to y 7,k   
               
               
                   
                   
                 b 8k+3  mapped to y 6,k   
               
               
                   
                   
                 b 8k+4  mapped to y 0,k   
               
               
                   
                   
                 b 8k+5  mapped to y 5,k   
               
               
                   
                   
                 b 8k+6  mapped to y 3,k   
               
               
                   
                   
                 b 8k+7  mapped to y 2,k   
               
               
                   
                 &lt;256 QAM - Method 2, Modification&gt; 
                 b 8k+0  mapped to y 1,k   
               
               
                   
                   
                 b 8k+1  mapped to y 4,k   
               
               
                   
                   
                 b 8k+2  mapped to y 7,k   
               
               
                   
                   
                 b 8k+3  mapped to y 6,k   
               
               
                   
                   
                 b 8k+4  mapped to y 0,k   
               
               
                   
                   
                 b 8k+5  mapped to y 3,k   
               
               
                   
                   
                 b 8k+6  mapped to y 5,k   
               
               
                   
                   
                 b 8k+7  mapped to y 2,k   
               
               
                   
                   
               
             
          
         
       
     
         [0092]    For a better understanding, writing/reading of a signal according to the interleaving and bit mapping scheme according to the present invention will be described with reference to  FIGS. 7A and 7B . 
         [0093]      FIGS. 7A and 7B  are illustrat4 interleaving and bit mapping method according to another embodiment of the present invention. For purposes of illustrating this embodiment of the invention, a the modulation scheme is selected as being 256-QAM and a length of a codeword is 24 bits, a size of columns of the interleaver is selected as 8, and a size of rows is selected as 3. Assuming that the bit mapping method is similar to one described in Table 2, (i.e., &lt;256 QAM—Method 1&gt;).i. 
         [0094]    A codeword output from an LDPC encoder is represented as x=[x 0 , x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , x 8 , x 9 , x 10 , x 11 , x 12 , x 13 , x 14 , x 15 , x 16 , x 17 , x 18 , x 19 , x 20 , x 21 , x 22 , x 23 ], and degrees of codeword bits are [8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2]. When the codeword bits are written in the interleaver  501  column by column, x 0 , x 1 , x 2  are written in a column # 1 ; x 3 , x 4 , x 5  are written in a column # 2 ; x 6 , x 7 , x 9  are written in a column # 3 ; x 9 , x 10 , x 11  are written in a column # 4 ; x 12 , x 13 , x 14  are written in a column # 5 ; x 15 , x 16 , x 17  are written in a column # 6 ; x 18 , x 19 , x 20  are written in a column # 7 ; and x 21 , x 22 , x 23  are written in a column # 8 . Bits read from each of the columns row by row, i.e., a signal being output after undergoing interleaving, are b=[b 0 , b 1 , b 2 , b 3 , b 4 , b 5 , b 6 , b 7 ]=[x 0 , x 3 , x 6 , x 9 , x 12 , x 15 , x 18 , x 21 ]. 
         [0095]    When b is input to the demultiplexer  521 , since it is subjected to mapping according to the mapping rule, y=y 0,0 , y 1,0 , y 2,0 , y 3,0 , y 4,0 , y 5,0 , y 6,0 , y 7,0 =b 0 , b 4 , b 6 , b 7 , b 5 , b 1 , b 2 , b 3 =x 0 , x 12 , x 18 , x 21 , x 15 , x 3 , x 6 , x 9 . That is, the codeword bits mapped to the highest-reliability sign-determining bits y 0,0  and y 1,0  are x 0  and x 12 . In addition, the codeword bits mapped to the lowest-reliability magnitude-determining bits y 6,0  and y 7,0  are x 6  and x 9 . 
         [0096]    In the interleaving and bit mapping scheme described up to now, outputs of the interleaver  501  are read in the direction of a column number  1  to a column number  8 , and subjected to bit mapping according thereto. Such interleaving scheme and bit mapping scheme are defined as ‘forward interleaving’ and ‘forward bit mapping’, respectively. Although the forward direction is defined herein as a direction from the column number  1  to the column number  8 , the forward direction can be defined as a direction from the column number  8  to the column number  1 , when necessary. 
         [0097]    However, it is not always that the interleaver  501  should read codeword bits in the forward direction as shown in  FIG. 6A . Therefore, if the interleaver  501  reads codeword bits in the order shown  FIG. 6B , i.e., in the opposite direction of  FIG. 6A , (right side) or reverse direction, a mapping scheme of a bit mapper  560  can be changed to the schemes shown in Table 4. Such schemes are defined as ‘reverse interleaving’ and ‘reverse bit mapping’. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                 TABLE 4 
               
               
                   
                   
               
             
             
               
                   
                 &lt;256 QAM Method 1, Modification 2&gt; 
                 b 8k+0  mapped to y 3,k   
               
               
                   
                   
                 b 8k+1  mapped to y 2,k   
               
               
                   
                   
                 b 8k+2  mapped to y 4,k   
               
               
                   
                   
                 b 8k+3  mapped to y 1,k   
               
               
                   
                   
                 b 8k+4  mapped to y 7,k   
               
               
                   
                   
                 b 8k+5  mapped to y 6,k   
               
               
                   
                   
                 b 8k+6  mapped to y 5,k   
               
               
                   
                   
                 b 8k+7  mapped to y 0,k   
               
               
                   
                 &lt;256 QAM - Method 2, Modification 2&gt; 
                 b 8k+0  mapped to y 3,k   
               
               
                   
                   
                 b 8k+1  mapped to y 4,k   
               
               
                   
                   
                 b 8k+2  mapped to y 2,k   
               
               
                   
                   
                 b 8k+3  mapped to y 1,k   
               
               
                   
                   
                 b 8k+4  mapped to y 7,k   
               
               
                   
                   
                 b 8k+5  mapped to y 6,k   
               
               
                   
                   
                 b 8k+6  mapped to y 5,k   
               
               
                   
                   
                 b 8k+7  mapped to y 0,k   
               
               
                   
                   
               
             
          
         
       
     
         [0098]    An example of mapping by the reverse bit mapping scheme according to the reverse interleaving shown in  FIG. 6B  is shown in  FIG. 7B . 
         [0099]    Outputs of  FIG. 7B  are as follows. 
         [0000]    
       
         
           
             
               
                 
                   
                     y 
                     = 
                     
                       y 
                       
                         0 
                         , 
                         0 
                       
                     
                   
                   , 
                   
                     y 
                     
                       1 
                       , 
                       0 
                     
                   
                   , 
                   
                     y 
                     
                       2 
                       , 
                       0 
                     
                   
                   , 
                   
                     y 
                     
                       3 
                       , 
                       0 
                     
                   
                   , 
                   
                     y 
                     
                       4 
                       , 
                       0 
                     
                   
                   , 
                   
                     y 
                     
                       5 
                       , 
                       0 
                     
                   
                   , 
                   
                     y 
                     
                       6 
                       , 
                       0 
                     
                   
                   , 
                   
                     y 
                     
                       7 
                       , 
                       0 
                     
                   
                 
               
             
             
               
                 
                   
                     = 
                     
                       b 
                       7 
                     
                   
                   , 
                   
                     b 
                     3 
                   
                   , 
                   
                     b 
                     1 
                   
                   , 
                   
                     b 
                     0 
                   
                   , 
                   
                     b 
                     2 
                   
                   , 
                   
                     b 
                     6 
                   
                   , 
                   
                     b 
                     5 
                   
                   , 
                   
                     b 
                     4 
                   
                 
               
             
             
               
                 
                   
                     = 
                     
                       x 
                       0 
                     
                   
                   , 
                   
                     x 
                     12 
                   
                   , 
                   
                     x 
                     18 
                   
                   , 
                   
                     x 
                     21 
                   
                   , 
                   
                     x 
                     15 
                   
                   , 
                   
                     x 
                     3 
                   
                   , 
                   
                     x 
                     6 
                   
                   , 
                   
                     x 
                     9 
                   
                 
               
             
           
         
       
     
         [0100]    In the present invention, a bit mapper composed of an interleaver and a demultiplexer is illustrated and referred to in describing the processing herein. However, the mapper and interleaver, rather than being realized by hardware, can be realized by software like in the case wherein the interleaver based on the above mapping scheme is stored in a memory. In some cases, the bit mapper can be realized with a scheme of directly mapping the codeword bits to the modulation signal-constituting bits. 
         [0101]    A description will now be made of performance improvement during data transmission by the interleaving and bit mapping scheme of the present invention. 
         [0102]      FIG. 8  is a diagram illustrating performance improvement based on a data transmission scheme according to an embodiment of the present invention. Shown in  FIG. 8  is BER for an LDPC codeword with length=64800. The simulation results were obtained in the AWGN channel when a 256-QAM modulation signal was used. The dotted line represents FER of an interleaver designed using a random scheme, and the solid line represents FER when an interleaver and bit mapping scheme according to the present invention are used. It can be appreciated that the present invention can obtain performance gain of about 0.08 dB at BER=0.0001. 
         [0103]    Referring back to  FIG. 4 , the interleaving scheme and bit mapping scheme in the transmitter  400  have been described so far. A description will now be made of the deinterleaving and bit demapping scheme used in the receiver  450 . Since it would be obvious to those skilled in the art that the receiver  450  corresponds to the transmitter  400  in structure, a brief description of the de-interleaving scheme and de-bit-mapping scheme will thus be presented. That is, the demodulator  457  in the receiver  450  performs high-order demodulation on the received signal, and outputs modulation signal-constituting bits, and the signal constellation bit de-mapper  455  bit-de-maps the output modulation signal-constituting bits, and outputs a de-mapped signal. A de-mapping method used in this case corresponds to the bit mapping scheme of the transmitter  400 . That is, the de-mapping method de-maps two higher-reliability bits among the modulation signal-constituting bits to a higher-degree LDPC codeword bit and a lower-degree LDPC codeword, and de-maps two lower-reliability bits to a higher-degree LDPC codeword and a lower-degree LDPC codeword bit. Since the bit de-mapper  455  corresponds to the bit mapper  415  in the transmitter  400 , the bit de-mapper  455  is formed of a multiplexer (not shown). 
         [0104]    The bit-de-mapped output signal is input to the deinterleaver  453 . A size of the deinterleaver  453  is equal to the size of the interleaver  413  in the transmitter  400 . If the bit-demapped signals are sequentially written in the deinterleaver  453  row by row, and they are read in the forward direction (read beginning from a row number  1 ) column by column, the deinterleaved LDPC codeword bits are output. The output LDPC codewords are input to the decoder  451  where they are decoded. If interleaving of the transmitter  400  is reverse interleaving, deinterleaving of the receiver is also reverse deinterleaving. 
         [0105]    The above-described methods according to the present invention can be realized in hardware or as software or computer code that can be stored in a recording medium such as a CD ROM, an RAM, a floppy disk, a hard disk, or a magneto-optical disk or downloaded over a network, so that the methods described herein can be executed by such software using a general purpose computer, or a special processor or in programmable or dedicated hardware, such as an ASIC or FPGA. As would be understood in the art, the computer, the processor or the programmable hardware include memory components, e.g., RAM, ROM, Flash, etc. that may store or receive software or computer code that when accessed and executed by the computer, processor or hardware implement the processing methods described herein. As is apparent from the foregoing description, the use of the present invention can improve the performance of a communication system using an LDPC codeword encoding scheme. In addition, the use of the scheme disclosed herein improves decoding performance of the LDPC code. In particular, the present invention improves reliabilities of bits having lower error correction capability among the bits constituting the LDPC code. Further, the present invention increases link performance in a wireless channel environment where there is a high probability that the link performance will decrease due to noises, fading phenomenon and ISI, thereby contributing to improvement of reliability of data transmission/reception. In addition, according to the present invention, the reliable transmission/reception of the LDPC code reduces error probability of signals in the entire communication system, enabling high-speed communication. 
         [0106]    While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.