Abstract:
An oscillator with oscillator and voltage control circuitry for generating an oscillation signal having an amplitude that is automatically controlled for a selectively minimized phase noise. Automatic level control is used for controlling the amplitude of the oscillation signal such that the phase noise of the oscillation signal can be maintained at some selected level, e.g., minimized. The minimum signal voltage appearing across the oscillation circuit is monitored for controlling the bias of the circuit to prevent it from entering a saturation state, thereby avoiding adverse loading effects responsible for degraded phase noise performance.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to oscillator circuits, such as voltage controlled oscillator (VCO) circuits, and in particular, oscillator circuits having automatic level control for controlling the amplitude of the oscillator output signal so as to control the amount of phase noise within such signal. 
     2. Description of the Related Art 
     In oscillator circuit design, particularly when designing VCO circuits for use in a phase lock loop (PLL), a key design parameter is that of the phase noise performance of the oscillator. As is well known in the art, the term phase noise is generally used for. describing short term, random frequency fluctuations of a signal, such as that generated by an oscillator. The frequency stability of the oscillator circuit is a measure of the degree to which the oscillator maintains the same value of output signal frequency over a given interval of time. The ideal output signal from a sine wave oscillator is generally described as: 
     
       
           V ( t )= Vo * sin(2πft) 
       
     
     where: V(t)=oscillator output signal 
     Vo=nominal amplitude of oscillator output signal 
     f=frequency in Hertz (Hz) 
     t=time in seconds 
     while the instantaneous output signal of the oscillator is generally represented by: 
     
       
           V ( t )= Vo *{1 +A ( t )}*sin{2 πft +Δφ( t )} 
       
     
     where: A(t)=normalized amplitude fluctuations of oscillator output signal 
     Δφ(t)=phase fluctuations of oscillator output signal in radians 
     Amplitude fluctuations in an oscillator signal can be removed, at least partially, by using a limiting amplifier. However, the phase noise of such a signal cannot be filtered out by any conventional means, and must be minimized at the point of generation. The magnitude of an oscillator&#39;s phase noise close in to the carrier can be expressed by Leeson&#39;s equation, as follows: 
     
       
           L (Δω)=10*log[2 FkT/P sig*(ω o /2 Q Δω) 2 ] 
       
     
     where: L(Δω)=phase noise power spectral density of the oscillator in dBc/Hz 
     F=equivalent noise factor of the negative R cell 
     Psig=signal power in the oscillator 
     ω o =center frequency of the oscillator 
     Q=loaded Q (quality factor) of the oscillator tank 
     Δω=frequency offset from the center frequency 
     k=Boltzmann&#39;s constant 
     T=temperature in Kelvin 
     As predicted by Leeson&#39;s equation, phase noise can be reduced by increasing oscillation amplitude. Since Psig is proportional to Vo 2 , the phase noise decreases by a factor of 4 each time the oscillation voltage is doubled. However, most oscillators operate in a state of saturation. As a result, simply increasing the output signal level will cause adverse loading effects, such as those from increased base currents flowing through the bipolar transistors used for generating the output signal. These loading effects manifest themselves as a dramatic reduction in loaded Q of the tank circuit, degrading phase noise per the equation above. 
     The phase noise of the oscillator is often one of the more significant limiting factors in the performance capabilities of the host system, such as the ability of a radio receiver to reject undesired signals and preserve modulation fidelity of the frequency down converted signals. For example, in a radio transceiver, poor oscillator phase noise can lead to undesirable noise transmissions outside the desired bandwidth of the channel being transmitted. Hence, the phase noise of the oscillator circuit is one of the primary figures of merit used to determine the performance of the overall system. 
     Several factors play a role in the phase noise performance of the oscillator. The quality factor (“Q”) of the resonator, the noise factor of the negative impedance cell and the oscillation signal amplitude all affect the phase noise of the oscillator, as shown in Leeson&#39;s equation. 
     One conventional technique that has been used to address the effect of the oscillation signal amplitude upon the phase noise performance is to introduce automatic level control for establishing the amplitude of the oscillation signal at the appropriate level needed for achieving the desired phase noise. Such conventional automatic level control techniques have involved the detection of the oscillation signal (e.g., in terms of peak, peak-to-peak or RMS voltage) and comparing such detected voltage to a fixed voltage reference. 
     However, such automatic level control techniques do not allow the circuit to maintain the desired amount of control over the phase noise throughout significant variations in circuit operating temperature, power supply voltages and fabrication processes used to produce such circuit. Accordingly, it would be desirable to have a form of automatic level control for an oscillator circuit to optimize the amplitude performance of the oscillator in such a manner as to provide consistent control over its phase noise performance, and to maintain such control not withstanding variations in circuit operating temperature, power supply voltages and fabrication processes. 
     SUMMARY OF THE INVENTION 
     An oscillator in accordance with the presently claimed invention generates an oscillation signal having an amplitude that is automatically controlled for a selectively minimized phase noise. Automatic level control is used for controlling the amplitude of the oscillation signal such that the phase noise of the oscillation signal can be minimized or maintained at some selected level. 
     In accordance with one embodiment of the presently claimed invention, an oscillator with an oscillation signal amplitude that is automatically controlled for a selectively minimized oscillation signal phase noise includes oscillator circuitry and voltage control circuitry. The oscillator circuitry including first and second circuit terminals and an active circuit portion coupled between the first and second circuit terminals, responsive to an amplitude control signal, generates an oscillator signal, wherein the first and second circuit terminals are at first and second DC bias potentials, respectively, and the first DC bias potential is higher than the second DC bias potential. The voltage control circuitry, coupled to the oscillator circuitry and responsive to a comparison of a minimum signal voltage at the first circuit terminal and a maximum signal voltage at the second circuit terminal, generates the amplitude control signal such that a difference between the minimum and maximum signal voltages is maintained at a predetermined voltage amplitude. 
     In accordance with another embodiment of the presently claimed invention, a method for generating an oscillation signal amplitude that is automatically controlled for a selected oscillation signal phase noise includes the steps of 
     operating an active circuit between first and second circuit terminals, wherein the first and second circuit terminals are at first and second DC bias potentials, respectively, and the first DC bias potential is higher than the second DC bias potential; 
     receiving an amplitude control signal; 
     generating, in response to the amplitude control signal, an oscillator signal with a minimum signal voltage at the first circuit terminal and a maximum signal voltage at the second circuit terminal, wherein a difference between the minimum and maximum signal voltages is maintained at a predetermined voltage amplitude; 
     comparing the minimum and maximum signal voltages; and 
     generating the amplitude control signal in response to the voltage comparison. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of an oscillator circuit with automatic level control in accordance with one embodiment of the presently claimed invention. 
     FIG. 2 is a schematic diagram of one example embodiment of the circuit of FIG.  1 . 
     FIG. 3 is a schematic diagram of an oscillator with automatic level signal control in accordance with another embodiment of the presently claimed invention. 
     FIG. 4 is a schematic diagram of an alternate embodiment of the circuit of FIG.  3 . 
     FIG. 5 is a schematic diagram of an alternate embodiment of the circuit of FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, an oscillator circuit  10  in accordance with one embodiment of the presently claimed invention includes an oscillator circuit in the form of a differential amplifier implemented with NPN bipolar transistors Q 1 , Q 2  cross coupled with capacitors C 9 , C 10 . The reactive load elements L 5 , L 6 , C 11 , C 12  primarily determine the oscillation frequency of the circuit, while a current source  18  with a controllable current source circuit I 11  provides the tail current Itail for the differential transistor pair Q 1 , Q 2 . (All elements are biased between power supply terminals VCC and circuit ground GND.) 
     The collector voltages Vc 1 , Vc 2  of transistors Q 1  and Q 2  provide the oscillator output signal in the form of a differential output voltage Vc 1 -Vc 2 . These voltages, Vc 1 , Vc 2  are each detected by a voltage detector  12   n  in the form of a negative peak detector (discussed in more detail below). 
     Similarly, the emitter voltage Ve present at the commonly connected emitter terminals of the transistors Q 1 , Q 2  is detected by another voltage detector in the form of a positive peak detector  12   p  (discussed in more detail below). 
     The negative peak detector  12   n  detects the minimum collector voltage Vcmin for each of the transistor collector voltages Vc 1 , Vc 2 . Conversely, the positive peak detector  12   p  detects the maximum emitter voltage Vemax of the emitter voltage Ve at the commonly connected emitter terminals of the transistors Q 1 , Q 2 . The minimum detected collector voltage  13   n  is reduced by a voltage factor Vsat, generated by a voltage reference circuit  14 . The resulting voltage  15  is compared to the maximum detected emitter voltage  13   p  in an error amplifier  16  (e.g., an operational amplifier integrator circuit) to produce a control voltage  17 . 
     This control voltage  17  is an amplified version of the difference between the input voltages  15 ,  13   p . Normally, the gain of the amplifier  16  is quite high such that the voltage difference between the two input terminals is driven to zero. It is this feedback operation that ensures that the following equations are satisfied: 
       V cmin= V emax+ V sat 
     
       
           V cmin− V emax= V cemin= V sat 
       
     
     where: Vcmin=minimum detected collector voltage 
     Vemax=maximum detected emitter voltage 
     Vsat=collector-emitter saturation voltage (e.g., 0.4 volt) 
     Vcemin=minimum collector-emitter voltage 
     Based upon the foregoing, it can be seen that, in accordance with the presently claimed invention, two voltage detectors are used to detect the minimum collector voltage Vcmin and maximum emitter voltage Vemax of the main oscillator device (or devices). This voltage difference is then effectively compared to a desired voltage difference, such as the saturation voltage Vsat of such oscillator device. Based upon this voltage comparison, a control voltage is used to ensure that the voltage difference between the minimum collector voltage Vcmin and maximum emitter voltage Vemax is maintained at an amplitude that corresponds to the voltage factor Vsat. For example, by maintaining this voltage difference equal to the saturation voltage of the main oscillator device, the phase noise within the oscillation signal will be minimized. 
     By controlling the minimum collector voltage(s) Vcmin and maximum emitter voltage Vemax, the control voltage  17  thereby controls the minimum collector-emitter voltage Vcemin across the transistors Q 1 , Q 2 . This is accomplished by controlling the tail current Itail. Hence, the control voltage  17  is used to control, or modulate, the current generator circuit I 11  within the current source  18 . By controlling the tail current Itail, the individual device currents Iq 1 , Iq 2  through the transistors Q 1 , Q 2  are controlled, thereby controlling the amplitudes of the collector Vc and emitter Ve voltages potentially available at the collector and emitter terminals, respectively, of the transistors Q 1 , Q 2 . 
     Based upon the foregoing discussion, it: should be readily appreciated that this type of oscillation circuit is capable of tracking variations in circuit power supply voltages, operating temperature and fabrication processes since two voltages generated within the circuit are constantly monitored and compared against one another. Hence, any changes in these voltages due to such power supply voltage, operating temperature or fabrication process variations will become self canceling. 
     As depicted in FIG. 1, the voltage reference circuit  14  may be controlled by some form of bias control signal Vb so as to allow th e amplitude of the voltage factor Vsat to be selectively adjusted. For example, depending upon a given application for the circuit  10 , it. may be desirable to cause this voltage factor Vsat to be equal to some amplitude other than the saturation voltage of the oscillation transistors Q 1 , Q 2 . 
     Referring to FIG. 2, one example embodiment  10   a  of the circuit  10  of FIG. 1 includes a negative peak detector circuit  12   na  and a positive peak detector circuit  12   pa  implemented as shown. In the negative peak detector circuit  12   na , the minimum, or negative, signal peaks of the collector voltages Vc 1 , Vc 2  are detected by the diodes D 0 , D 1  and used to charge a shunt capacitor C 17 . The voltage across this capacitor C 17  biases the base of a voltage follower transistor Q 9 , which is maintained in a normally on state by a base current source I 26  and emitter current source I 23 . The emitter voltage of transistor Q 9  forms the output signal  13   n  of the negative peak detector circuit  12   na  and is equal to the minimum, or most negative, peak voltage of the transistor collector voltages VC 1 , VC 2  since the junction voltages of the diodes D 0 , D 1  are in series and polarity opposition to the base-emitter voltage of transistor Q 9 . 
     In the positive peak detector circuit  12   pa , the common emitter voltage Ve of the oscillation transistors Q 1 , Q 2  is detected by detecting the corresponding base voltages Vb 1 , Vb 2  which differ from the emitter voltage Ve by the well-known relationship of the base-emitter voltage Vbe of the transistors Q 1 , Q 2 . These base voltages Vb 1 , Vb 2  are detected by the base-emitter junctions of transistors Q 11  and Q 10 , respectively, to produce a combined detected voltage across the shunt current source  128  (used to bias transistors Q 10  and Q 11  in normally on states) and shunt capacitor C 18 . Shunt capacitor C 18  provides a positive peak hold function, provided that the discharge time of the capacitor C 18  through the current source I 28  is much longer than one period of the oscillation signal. Hence, the voltage of the output signal  13   p  is equal to the maximum, or most positive, peak of the emitter voltage Ve due to the self-canceling effects of the serially connected and polarity opposed base-emitter voltages of the oscillator transistors Q 1 , Q 2  and detector transistors Q 11 , Q 10 . 
     The current source  18   a  in this circuit  10   a  is implemented using NPN bipolar transistor Q 3  as the current source circuit to generate the tail current Itail for the differential transistor pair Q 1 , Q 2 . 
     Referring to FIG. 3, an alternative embodiment  10   b  of an oscillator circuit in accordance with the presently claimed invention generates a non-differential, or single-ended, oscillator output signal. In this circuit  10   b , a single oscillation transistor Q 1  biased by a resistor R 12  to the power supply VCC and the current source  18  to circuit ground GND, generates the oscillation signal Vc at its collector terminal, with the frequency determined by an inductor L 13  and capacitors C 26 , C 27 . The operation and functionality of the remaining circuitry, including the detector circuits  12   n ,  12   p , voltage reference circuit  14  and error amplifier circuit  16 , are in accordance with the discussion above. 
     Referring to FIG. 4, an alternative embodiment  10   c  of the circuit of FIG. 3 uses a crystal in place of the inductive circuit element L 13  (FIG. 3) to establish the oscillation frequency. (Additionally, as is well known in the art, the use of the crystal in place of the inductive element causes the oscillation frequency to be significantly more stable.) 
     Referring to FIG. 5, an alternative embodiment  10   d  of the circuit  10   a  of FIG. 2 has an oscillator circuit whose frequency is controlled by a frequency control voltage Vfc that controls the bias on varactor diodes D 6 , D 7  connected between the collector terminals of the oscillator transistors Q 1 , Q 2 . The remaining circuitry operates in accordance with the discussion above concerning FIG.  2 . 
     It should be noted and readily appreciated that although the discussion of the presently claimed invention has been in the context of an oscillation circuit using NPN transistors, the principles discussed herein are also applicable to oscillator circuits implemented with PNP transistors, with appropriate reversals of power supply polarities and connections of the tail current source  18  and reactive circuit elements in accordance with well known circuit design techniques. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.