Abstract:
A backplane for an electronic data communication system is disclosed. The backplane comprises at least one ultra-wideband transmitter configured to transmit data in the form of a plurality of pulses in a wireless manner and at least one ultra-wideband receiver configured to receive the plurality of pulses and decode the plurality of pulses to retrieve the data. The data is to be transmitted wirelessly from a first module comprising the at least one ultra-wideband transmitter to a second module comprising the ultra-wideband receiver within the electronic communication system, the first and second modules residing in the system housing.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   The present application claims the benefit of priority under 35 U.S.C. § 119 from U.S. Provisional Patent Application Ser. No. 60/370,994, entitled “ULTRA-WIDE BAND WIRELESS BACKPLANE” filed on Apr. 8, 2002, the disclosure of which is hereby incorporated by reference in its entirety for all purposes. 

   BACKGROUND OF THE INVENTION 
   The present invention generally relates to backplanes of electronic systems, and more specifically, to a backplane that is capable of handling wireless data transfers. 
   Complex electronic systems, like data communication systems, typically comprise multiple functional modules that are required to pass large amounts of data amongst each other. Such systems usually employ a dedicated common interconnection element into which all the functional modules plug in. This interconnection element is sometimes called backplane or motherboard. 
   The backplane of an electronic system provides, among other functions, one or more data buses for passing data between the functional modules. These data buses may be parallel or serial, point-to-point, point-to-multi-point, or multipoint-to-multipoint. These data buses usually include a number of electrical signal transmission lines. During their design, great efforts are made to come as close as possible to perfect uniformity and stability of their transmission parameters and to avoid undesirable reflections of the signal energy from the hard-to-avoid points of discontinuity along the lines and at their ends. 
   The higher the required data transfer rate, the more difficult it is to achieve the signal integrity required to guarantee the robustness of the data transfer. The high performance interconnect components, like connectors and printed circuit boards are progressively more expensive. Yet, despite their high price, these components continue to have problems reaching the desirable data transfer bandwidth. 
   Efforts have been made to develop interconnect elements based on data transfer by means other than electrical signal transmission lines. These interconnect elements include, for example, backplanes employing optical signals carrying data through elements of fiber optics and millimeter-wave based wireless interconnection of electronic components. While these interconnect elements have been somewhat successful in achieving higher data rates, they require either very high-precision components, like the fiber optic elements, or highly complex components, like the millimeter-wave transceivers. These high-precision and highly complex components are very expensive thus keeping the cost of developing and manufacturing of interconnect elements quite high. 
   The millimeter-wave wireless interconnect solution is based on the traditional carrier signal modulation and required complex and, therefore, expensive heterodyne receivers. Furthermore, using discrete frequency carrier signals with relatively high spectral power density made the requirement of low electromagnetic interference caused by such systems hard to satisfy. As a result, such systems never became wide spread. 
   Hence, it would be desirable to provide a backplane for electronic systems that is capable of achieving high data transfer rates and yet is low cost. 
   BRIEF SUMMARY OF THE INVENTION 
   In an exemplary embodiment, a backplane for an electronic data communication system is disclosed. The data is intended to be transmitted through the backplane from one module to another module within the system. The backplane function is performed by a number of wireless buses, each including an ultra-wideband transmitter configured to encode and transmit data in the form of a train of pulses and at least one associated ultra-wideband receiver configured to receive the train of pulses and decode the train of pulses to retrieve the data. 
   Each wireless bus uses a train of pulses with specific characteristic(s). Such characteristics include, for example, the shape of each pulse and the pulse&#39;s coarse and fine time positions. In an exemplary embodiment, a pico-second pulse generator produces the train of pulses having the required shape. The time position of each pulse is coarsely modulated according to a unique pseudo-random sequence. In addition, the time position of each pulse is also modulated in fine increments based on the data to be transmitted. 
   In the receiver, the shape of each pulse is identified by a shape discriminating filter. The filter is allowed to recognize the pulses only during limited time intervals determined by a pseudo-random sequence generator of the receiver. The pseudo-random sequences used by the ultra-wideband transmitters and the ultra-wideband receivers within the same bus are identical and synchronized by a common sequence sync generator. Operating in this manner, the receivers can only receive and identify the train of pulses transmitted by the transmitter that they are associated with. 
   In an exemplary embodiment, the pseudo-random sequences used by all ultra-wideband transmitters and all ultra-wideband receivers within one system are synchronized by a common sequence sync generator. 
   Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawings, like reference numbers indicate identical or functionally similar elements. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a simplified block diagram of an exemplary embodiment of the present invention; and 
       FIG. 2  is an illustrative timing diagram showing a timing sequence used by a timing control circuit to control generation of pulses by a pico-second pulse generator in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention in the form of one or more exemplary embodiments will now be described. The present invention utilizes time domain ultra-wideband (UWB) wireless data communication to achieve interconnect and data transfer functions in a backplane. Using UWB wireless data communication for the purpose of providing system interconnect function allows very high data transfer rates to be achieved in multiple channels without having to satisfy very stringent electrical, optical, and mechanical requirements and without using typically very expensive interconnect components of conventional electrical or optical backplanes. Furthermore, short propagation or transmission distances inside of the system housing make signal-to-noise requirements easy to satisfy and permit achieving very high data rates. 
   The time domain UWB wireless communication utilizing pseudo-random sequence of pulses to carry the data has an inherent spread-spectrum nature and very low spectral power density. Furthermore, using UWB wireless communication in a well controlled, enclosed environment of the system housing makes satisfying the requirement of low external interference easy. 
   Simplicity of its components and, hence, low cost, in comparison to the traditional millimeter-wave based wireless interconnect solutions, makes the time domain UWB wireless system interconnect solution feasible. 
   In one illustrative application, an exemplary embodiment of the present invention is used as an interconnect element to transfer data between different modules in a computer network switch, with the different modules residing in the same housing. This application includes several independent unidirectional point-to-point data transfers, as well as several point-to-multipoint data transfers. In this illustrative application, the interconnect element has independent and separate UWB transmitters and receivers. It should be understood that while the exemplary embodiment of the present invention is deployed in a computer network switch or router, a person of ordinary skill in the art will know of other ways and/or methods to deploy the present invention in other contexts and/or applications. 
     FIG. 1  is a simplified block diagram of an exemplary embodiment of a UWB wireless data bus  10  employed in a network switch (not shown) in accordance with the present invention. Referring to  FIG. 1 , the UWB wireless data bus  10  includes one transmitter  12 , at least one corresponding receiver  14  and a sequence sync generator  42 . The transmitter  10  further includes a timing control circuit  20 , a pico-second pulse generator  16 , an antenna element driver  18  and a transmitter antenna element  19 , collectively coupled in a sequential configuration. The timing control circuit  20  uses bus data  44  and a control signal from the sequence sync generator  42  to provide and control timing of pulse generation by the pico-second pulse generator  16 . Details of the timing control circuit  20  will be further described below. The pico-second pulse generator  16  generates a train of very short pulses based on input signals received from the timing control circuit  20 . These pulses have certain characteristic(s) that are matched to the receiver  14 , as further described below. The antenna element driver  18  applies the pulses to the transmitter antenna element  19  for transmission to the receiver  14 . In one exemplary implementation, the transmitter antenna element  19  is part of a printed circuit board (not shown) within the network switch. In its simplest form, the transmitter antenna element  19  is a stub of printed circuit trace, about one inch long. In its more sophisticated form, the transmitter antenna element  19  can have a more complex shape chosen according to the antenna design rules in order to optimize signal power coupling from the antenna element driver  18  to the transmitter antenna element  19 , and from the transmitter antenna element  19  to propagation space. The transmitted power level is chosen with consideration to the robustness of the transmission, as well as minimizing the interference between different buses inside and undesired radiation outside of the system. 
   As mentioned above, the generation and timing of each generated pico-second pulse is determined by the timing control circuit  20 . In one exemplary embodiment, the timing control circuit  20  includes a first pseudo-random sequence generator  22 , a forward error correction (FEC) encoder  28 , a coarse delay control  24  and a fine delay control  26 . 
     FIG. 2  is an illustrative timing diagram showing a timing sequence used by the timing control circuit  20  to control generation of pulses by the pico-second pulse generator  16 . The first pseudo-random generator  22  is responsible for providing a pseudo-random sequence of timing intervals  50   a - d . As will be further described below, the same pseudo-random sequence is shared between a transmitter/receiver(s) pairing. A pulse is to be generated between two adjacent timing intervals within the pseudo-random sequence. A window  52  within which the pulse is to be generated is controlled by the coarse delay control  24 . The location within the window  52  where the pulse is to be generated is controlled by the fine delay control  26 . More specifically, the fine delay control  26  is driven according to the bus data  44  to modulate the position of the to-be-generated pulse in small increments within the window  52 . Optionally, before being applied to the fine delay control  26 , the bus data  44  undergoes a forward error correction performed by the FEC encoder  28 , which adds redundancy to the data for an additional improvement of transfer robustness. The exemplary embodiment of the present invention as described herein uses binary signals for controlling the fine delay. Ternary, or other multi-level forms of controlling signals may also be used, dependent on the constraints of a particular application. Hence, the timing control circuit  20  and the pico-second pulse generator  16  collectively generate pulses with specific characteristic(s) and in a specific pseudo-random timing sequence. The significance of the specific pulse characteristic(s) and pseudo-random timing sequence will be further described below. 
   The UWB electro-magnetic field radiated by the transmitter antenna element  19  reaches the receiver  14  and induces an electrical signal therein. In an exemplary embodiment, the receiver  14  includes a receiver antenna element  30 , a second pseudo-random sequence generator  36 , a low-noise antenna amplifier  32 , a shape discriminating filter  34 , a phase detector  38  and a forward error correction decoder  40 . 
   The receiver antenna element  30  can, but does not have to, be similar to the transmitter antenna element  19 . The receiver antenna element  30  is used to receive the signals transmitted by the transmitter antenna element  19  and is coupled to the input of a low-noise antenna amplifier  32 . The signal from the low-noise antenna amplifier  32  then goes through the shape discriminating filter  34  designed to identify pulses with specific characteristic(s) and timing, such as, a particular shape and duration. These characteristic(s) correspond to those of pulses coming from the transmitter  12 . Operation of the filter  34  is controlled by the second pseudo-random sequence generator  36 , which synchronously generates exactly the same sequence as the one generated by the first pseudo-random sequence generator  22  in the transmitter  12  from which transmitted data is to be received. This control of the filter  34  allows it to pass only the pulses with specific characteristic(s) and in a specific pseudo-random timing sequence. In other words, only pulses from the transmitter  12  are identified and processed by the receiver  14 . Other pulses with different characteristic(s) and in different pseudo-random timing sequences are ignored. The filter  34  is designed in such a way as not to influence the fine modulation of the pulse timing which represents the bus data. 
   The modulating data is recovered in the next stage by the phase detector  38 . The phase detector  38  performs precise phase comparison between the received pulses and the pulses of the unmodulated pseudo-random sequence generated by the second pseudo-random sequence generator  36 . The output of the phase detector  38  is passed to the forward error correction (FEC) decoder  40  which uses redundancy added to the modulating signal to detect errors in the received data and to auto-correct some of the errors. The FEC decoder  40  then outputs the data that was originally sent from the transmitter  12 . 
   Each wireless bus within the same system uses a transmitter that generates a distinct pseudo-random sequence. This distinct pseudo-random is recognized only by receiver(s) associated with that bus. In the exemplary embodiment described above, this is accomplished by the use of the first and second pseudo-random sequence generators  22  and  36  respectively in the transmitter  12  and the receiver  14 . In order to simplify the synchronization of pseudo-random sequences in the transmitter  12  and the receiver  14  operating on the same bus, the transmitter  12  and the receiver  14  receive sequence synchronization pulses provided by a common sequence sync generator  42 . The function of the common sequence sync generator  42  is to initiate the generation of the distinct pseudo-random sequence by the first and second pseudo-random sequence generators  22  and  36  at the same time. This ensures that, from a timing perspective, pulses transmitted by the transmitter  12  can be properly identified by the receiver  14  for processing. The sync pulses are generated at a relatively low rate like, for example, 19.44 MHz and are distributed to all sub-systems using an appropriate number of drivers at the source and point-to-point electrical transmission lines through the backplane. 
   In the exemplary embodiment described above, the transmitter  12  has a corresponding receiver  14 . In an alternative exemplary embodiment, the transmitter  12  can have a number of corresponding receivers, each similar to the receiver  14  described above. In another alternative exemplary embodiment, a backplane can include a number of transmitters, each similar to the transmitter  12  described above and each having one or more corresponding receivers. In one exemplary embodiment, it is convenient to synchronize transmitters and receivers on buses to the same common sequence sync generator. 
   Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will know of ways and/or methods to implement the various components of the present invention with appropriate software and/or hardware circuit design. 
   It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. All publications, patents, and patent applications cited herein are hereby incorporated by reference for all purposes in their entirety.