Abstract:
A filter includes at least a pin diode, an inductive element, and a varactor diode coupled as a resonant circuit. The filter injects data dependent jitter into a digital data signal with a given data rate for testing a transceiver.

Description:
TECHNICAL FIELD 
     Embodiments of the present invention pertain to the field of automatic electrical test systems. More particularly, embodiments of the present invention relate to improvements in the ability of test systems to test bit processing capacities of transceivers. 
     BACKGROUND 
     A bit error rate, also known as a bit error ratio (BER), is a ratio of bits received, processed, and/or transmitted with errors to a total number of bits received, processed, and/or transmitted over a given period of time. A BER is typically expressed as ten to a negative power. If, for example, a transmission has 1 million bits and one of these bits is in error (e.g., a bit is in a first logic state instead of a second logic state), the transmission has a BER of 10 −6 . The BER is useful because it provides one measurement of the ability of a device to receive, process, and/or transmit bits. 
     Many devices are designed to receive, process, and then transmit a plurality of bits. An optoelectronic transceiver, for example, receives a plurality of bits in an electrical form and then transforms and transmits the bits in an optical form and/or receives a plurality of bits in an optical form and then transforms and transmits the bits in an electrical form. 
     To derive a BER for a device under test (DUT), bits transmitted to the DUT are compared to corresponding bits transmitted by the DUT or to corresponding bits in a pattern used to generate the bits transmitted to the DUT. In some applications, the BER of a DUT must be below a defined threshold for the DUT to pass a test. 
     A Bit Error Rate Test or Tester (“BERT”) is a procedure or device that establishes a BER for a DUT or to otherwise quantify a DUT&#39;s ability to receive, process, and/or transmit bits. More specifically, a BERT measures the BER of a transmission (e.g., bits transmitted, received, or processed) over a given period of time by a DUT. An example of a BERT includes, among other components, a serializer/deserializer (“SerDes”) and a clock source fixed to a host board, such as a printed circuit board (PCB), etc. SerDes devices convert parallel bit streams into serial bit streams that change at a multiple of the input, parallel data rate. They may also perform the reverse function of deserializing serial bit streams, by converting them into parallel bit streams that change at a fraction of the serial data rates. Typically, the SerDes produces serial encoded data (e.g., the bits) used to establish a BER for a DUT. More specifically, serial encoded data is transmitted from a SerDes to a DUT, which attempts to transmit the serial encoded data back to the SerDes. The SerDes compares the output of the DUT to the input to the DUT (or what the input should have been), to establish a BER. 
     High-speed input/output (I/O) interfaces embedded in communication devices approach Terabit bandwidth. The architecture allowing this bandwidth boost is based on a parallel arrangement of SerDes cells running at data rates of several Gigabit per second and performing an independent serial data transmission on each lane in parallel (SerDes multilane interface). Gigahertz SerDes devices have gained more and more applications. They are being implemented in devices from high end microprocessors, to high volume low end wireless base bands. 
     However, economic production testing of such interfaces and SerDes devices imposes a significant challenge. Instrument based solutions are typically costly and slow and the test approach of using a simple loop back between transmit and receive portion of the SerDes typically does not cover faults resulting from data signals exposed to intersymbol interference (ISI) while being transmitted via transmission lines or cables. 
     A SerDes lane is generally comprised of a Transmit-Receive (Tx-Rx) pair. Nearly all lanes have Built In Self Test (BIST) designs for looping back Tx to Rx with pseudo-random binary sequence (PRBS) and other repetitive patterns for production testing. However, internal or external loop back alone is typically not enough to screen poor performing devices. External signal conditioning, such as ISI injection, is typically required to verify Rx input eye and equalization. 
     The ability to inject ISI into the data stream is key to characterization and test of SerDes devices. ISI happens due to the low pass nature of transmission line. When alternate 1&#39;s and 0&#39;s are present in data, the received signal has a shorter time to reach the maximum level, as compared with the consecutive 1β or 0&#39;s, in which the received signal pattern can reach higher voltage levels. These changes of signal amplitudes may cause the Phase Lock Loop (PLL) to vary in frequency. Further, harmonics travel with different speeds over transmission line due to their frequencies and so reach the receiver at different moments. This is why pre-emphasis at driver and equalization at receiver is helpful to reduce ISI. 
     Timing jitter injection has been used by some Automatic Test Equipment (ATE) manufacturers to evaluate the ability of a device to compensate for the interconnect bandwidth, but the effects are typically totally different from using ISI injection. Proper shaping of the frequency response of input buffers can compensate for rolloff in interconnect but not for random jitter. Even if variable timing is induced to emulate the effects of interconnect rolloff, the effect is different from inducing both the phase and amplitude characteristics of the ISI filter. 
     One method for ISI injection is to use a set of traces in transmission line (such as FR4) and provide a means to select the desired length with a multiplexer. The market requirement is increments of 6 inches. The approach using FR4 transmission line requires considerable space, and it is typically prone to crosstalk and typically requires a large fan-out and multiplexer to realize. The varactor only approach reasonably covers only about 20 to 40 inches of FR4, and thus typically has a limited range of emulation. 
     SUMMARY 
     A filter includes a pin diode, an inductive element, and a varactor diode coupled as a resonance circuit. The filter injects data dependent jitter onto a digital data signal with a given data rate for testing a transceiver. 
     Other features and advantages of embodiments of the invention will be apparent from the accompanying figures and from the detailed description which follows below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which: 
         FIG. 1  is an illustration of amplitude characteristics of a transmission line made of FR4 material of different lengths over frequency; 
         FIG. 2  shows an embodiment of a filter arrangement with a filter structure for injecting ISI; 
         FIG. 3A  is an illustration of typical characteristics of a Pin diode; 
         FIG. 3B  is an illustration of typical characteristics of a varactor diode; 
         FIG. 4A  shows an embodiment of a filter structure consisting of a multi stage resonance circuit; 
         FIG. 4B  shows an embodiment of a three stage tunable filter that employs a D.C. balance circuit; 
         FIG. 4C  shows an embodiment of single stage filter; 
         FIG. 5  is an illustration of a filter according to an embodiment of the present invention tracking the attenuation of a signal over a 6 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz; 
         FIG. 6  is an illustration of the 6 inch filter eye diagram at 1 Gbps; 
         FIG. 7  is an illustration of a 6 inch transmission line eye diagram at 1 Gbps; 
         FIG. 8  is an illustration of a 6 inch filter eye diagram at 6.4 Gbps; 
         FIG. 9  is an illustration of a 6 inch transmission line eye diagram at 6.4 Gbps; 
         FIG. 10  is an illustration of a filter according to an embodiment of the present invention tracking the attenuation of a signal over a 30 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz; 
         FIG. 11  is an illustration of the 30 inch filter eye diagram at 1 Gbps; 
         FIG. 12  is an illustration of a 30 inch filter eye diagram at 6.4 Gbps; 
         FIG. 13  is an illustration of a 30 inch transmission line eye diagram at 6.4 Gbps; 
         FIG. 14  is an illustration of a filter according to an embodiment of the present invention tracking the attenuation of a signal over a 50 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz; 
         FIG. 15  is an illustration of the 50 inch filter eye diagram at 1 Gbps; 
         FIG. 16  is an illustration of the group delay of a 30 inch FR4 transmission line vs. a filter optimized to provide the same attenuation characteristic; 
         FIG. 17  is an illustration of a 50 inch filter eye diagram at 6.4 Gbps; 
         FIG. 18  is an illustration of a 50 inch transmission line eye diagram at 6.4 Gbps. 
         FIG. 19  is an illustration of a filter according to an embodiment of the present invention tracking the attenuation of a signal over a 90 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz; 
         FIG. 20  is an illustration of the 90 inch filter eye diagram at 1 Gbps; 
         FIG. 21  is an illustration of a 90 inch filter eye diagram at 6.4 Gbps; 
         FIG. 22  is an illustration of a 90 inch transmission line eye diagram at 6.4 Gbps. 
         FIG. 23  is an illustration of transmission line emulation by an embodiment of a one stage filter, a three stage filter with inductance=0.67 nH, and a three stage filter with inductance=3.3 nH; and 
         FIGS. 24-26  illustrate an example of the operation of the three stage filter and the one stage filter using eye diagram representation according to one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     An ISI filter that is highly adjustable and can be used for SerDes testing is described. The ISI filter can be adjusted for a range of transmission line or cable length and a range of transmission line frequency characteristics. According to some embodiments, the ISI filter is a multiple stage variable low pass filter that utilizes pin diodes in the filter structure to obtain large variations in attenuation characteristics and varactor diodes in the filter structure to obtain large variations in capacitance of the filter. The ISI filter can be used for SerDes testing to emulate ISI introduced by the transmission line, and further can be used to measure the ability of a SerDes device to reject the effects of ISI. A method described herein uses a combination of varactor diodes, pin diodes and inductors to emulate the filter response of a PCB. 
     According to some embodiments, the ISI filter is a three stage tunable low pass filter in a differential configuration consisting of varactor diodes, PIN diodes, and fixed inductors. Accordingly, the ISI filter can emulate a larger variation of transmission line length (approximately from 6 inch to 50 inch or from 30 inch to 90 inch based on simulation results) by using different inductor values. Eye closure up to 28% horizontal VI at 1 Gbps and 100% at 6.4 Gbps may be obtained. 
     According to some embodiments, the ISI filter is a single stage filter for higher bit rate ISI injection. The single stage filter provides from about zero ISI up to the minimum achievable by the three-stage ISI filter. 
       FIG. 1  shows an illustration of amplitude characteristics of a transmission line made of FR4 material of different lengths (from 10 inches to 90 inches) over frequency. As shown in  FIG. 1 , the loss of transmission line versus frequency for some length of FR4 (transmission line material) follows a similar curve for each length. Also,  FIG. 1  illustrates the concept that the longer the transmission line, the greater the attenuation over frequency. Thus, for instance, while a 10 inch FR4 transmission line experiences an attenuation of approximately 4.5 DBs (decibels) over frequency (from 10 to 7000 Megahertz (MHz)), a 90 inch FR4 transmission line experiences an attenuation of approximately 42.5 DBs over the same frequency. 
       FIG. 2  shows an embodiment of a filter arrangement with a filter structure  20  according to an embodiment of the present invention for injecting ISI. In the example of  FIG. 2 , the filter structure  20  is inserted between nodes A and B into a transmission line  30  carrying a data signal from a data source  40  to a data sink  50 . The arrangement of data source  40 , data sink  50 , and transmission line  30  is differential. Source impedances  60 A and  60 B are also shown. 
       FIG. 3A  is an illustration of typical characteristics of a pin diode. Pin diodes have resistance with forward current and behave like resistors for high frequencies.  FIG. 3B  is an illustration of typical characteristics of a varactor diode. Varactor diodes have capacitance that varies with reverse applied voltage, as shown. 
       FIG. 4A  shows an embodiment of the filter structure  600  consisting of a multi stage resonance circuit. The filter structure  20  is a tunable low pass filter in a differential configuration using varactor diodes (D 1 -D 6 ), pin diodes (D 11 -D 16 ) and fixed inductors (L 1 -L 4 ). The voltages VP 1  to VP 3  are PIN diode drivers, while Vc 1  to Vc 3  are varactor diode drivers, and Vb is the DC bias voltage. The differential filter  600  may operate at a signal level of approximately 400 mV peak to peak differential. The attenuation frequency is determined by the value of the varactor capacitors (D 1 -D 6 ) while the shape of the attenuation is controlled by the amount of damping provided by the pin diodes (D 11 -D 16 ). 
     The bandwidth of the filter  600  may be increased by lowering the capacitance of the varactor diodes D 1 -D 6 . This can be achieved by increasing the voltage on nodes  109 ,  111  and  112 . Vc 1 , Vc 2 , Vc 3  are Varactor control voltages. Changing the common mode voltage at nodes  109 ,  111  and  112  has the affect of changing the capacitance of varactor diode pairs D 1  and D 4 , D 2  and D 5 , D 3  and D 6  respectively. Increasing the capacitance of a varactor diode pair has the affect of emulating a transmission line that is longer. 
     The pin diodes D 11 -D 16  enable the lossiness of the filter  600  to be varied, such that a transmission line can be matched at a broad range of frequencies and transmission line lengths. The sharpness of the attenuation characteristic of the filter  600  is increased by lowering the resistance of the pin diodes (D 11 -D 16 ). This is achieved by increasing the current through the pin diodes D 11 -D 16 . 
     The current through each pair of pin diodes (D 11  and D 14 , D 12  and D 15 , D 13  and D 16 ) for each stage of the RLC circuit shown in filter  600  can be varied by using divider circuits. For instance, current through the pin diodes D 11  and D 14  can be varied by pulling current through resistors R 1  and R 4 . Similarly, current through the pin diodes D 12  and D 15  can be varied by pulling current through resistors R 2  and R 5 , and current through the pin diodes D 13  and D 16  can be varied by pulling current through resistors R 3  and R 6 . 
     The inductors L 1 -L 2  and capacitors control the frequency at which roll off begins and resistance of the pin diodes control the slope of that attenuation is controlled by the resistance of the pin diodes. 
     The filter structure can emulate the characteristics of transmission lines, including linear phase delay and a smooth attenuation vs. frequency curve. The use of pin diodes enables varying the amount of lossiness therefore matching transmission line characteristics across a broad range of frequencies and transmission line lengths. According to embodiments of the present invention, a single filter can create up to 50% eye closure at data rates of 1 billion bits per second (1 Gbps) (equivalent to about 50 inches of trace in FR4 transmission line) and less than 50% eye closure at 6.4 Gbps (equivalent to about 6 inches of trace in FR4 transmission line) by varying the reverse voltage on the varactors and the forward current through the pin diodes. The filter structure can also be repeated to emulate transmission lines that are even longer. The variable low pass filter emulates the characteristics of transmission line and thereby measures the ability of a device to compensate its effects. The filter also exhibits a linear phase characteristic, thus emulating a transmission line. 
     Varying the current through the PIN diodes D 12  and D 15  would shift the operating voltage across the filter  600  and the bias current of a buffer which drives it. To eliminate this effect, a D.C. balance circuit may be used. An embodiment of a three stage tunable filter that employs a D.C. balance circuit is shown in  FIG. 4B . 
     The embodiment of the three stage tunable filter  600  shown in  FIG. 4A  requires 6 voltage drivers. The varactor diodes D 1 -D 6  are reverse biased and will not conduct any DC current. As such, according to some embodiments of the present invention, varactor drivers VCI to VC 3  (not shown) provide voltage on the cathodes of the varactor diodes. In some embodiments, varactor drivers VCI to VC 3  are able to provide up to 25 volts (V) voltage on the cathodes of the varactor diodes. On the filter DC circuit  700  in  FIG. 4B , for the sake of simplicity, both varactors and the varactor drivers are not included. 
     Operational amplifier U 1  provides pull down current for the buffer which drives the filter  700 . It also sums the current through the PIN diodes and forces an equal and opposite current into the filter through resistors R 84  and R 85  so that varying the PIN diode current would not shift the operating voltage through the filter  700 . In one embodiment, the resistors R 84  and R 85  are 360 ohm (Ω) each. Note that this current compensation scheme is only approximate and valid when the change in voltage across the pin diodes is small compared to that of R 71 -R 76 . The pin diodes are never operated in reverse biased so this approximation works well for the function of keeping the pull down current of the filter buffer constant. 
     According to some embodiments of the present invention, the DC circuit is designed to have filter DC operating voltage around 1.5V and each pin diode is conducting at least 1 mA current. In some embodiments, the pin diode current is linearly increased to 12 mA as the PIN diode driver voltage VP 71 =VP 72 =VP 73  is sweeping from 1.5V to −5V, while the filter output voltage V(out) is almost constantly at 1.5V. 
     Resistance values for resistors R 81  to R 83  can be calculated using the following equations. For a voltage change ΔVP on a PIN diode driver, say VP 71 , considering the single-ended case, it causes 
                       Δ   ⁢           ⁢     I   PIN       =         Δ   ⁢           ⁢   VP       R   ⁢           ⁢   71       ⁢           ⁢   on   ⁢           ⁢   PIN   ⁢           ⁢   diode   ⁢           ⁢   D   ⁢           ⁢   1   ⁢           ⁢   current       ,           (   1   )                   Δ   ⁢           ⁢     V   b       =         R   ⁢           ⁢   80       R   ⁢           ⁢   81       ⁢           ⁢   Δ   ⁢           ⁢   VP   ⁢           ⁢   on   ⁢           ⁢   U   ⁢           ⁢   1   ⁢           ⁢   output   ⁢           ⁢   voltage       ,           ⁢   and           (   2   )                 Δ   ⁢           ⁢     I   b       =         Δ   ⁢           ⁢     V   b         R   ⁢           ⁢   84       ⁢           ⁢   on   ⁢           ⁢   current   ⁢           ⁢   through   ⁢           ⁢   R   ⁢           ⁢   84.             (   3   )               
To keep filter operating voltage constant, ΔI b  has to be equal to ΔI PIN , therefore R 81 ,
 
               R   ⁢           ⁢   82   ⁢           ⁢   and   ⁢           ⁢   R   ⁢           ⁢   83   ⁢           ⁢   are   ⁢           ⁢   R   ⁢           ⁢   81     =       R   ⁢           ⁢   82     =       R   ⁢           ⁢   83     =         R   ⁢           ⁢   71       R   ⁢           ⁢   84       ×   R   ⁢           ⁢   80.               
For R 71 =470Ω, R 80 =10 kΩ, and
 
                 R   ⁢           ⁢   84     =     360   ⁢           ⁢   Ω       ,       R   ⁢           ⁢   81     =       R   ⁢           ⁢   82     =       R   ⁢           ⁢   83     =         470   360     ×   10   ⁢   k     =     13.06   ⁢           ⁢   k   ⁢           ⁢     Ω   .                     
In one embodiment, R 71 =R 72 =R 73 =R 74 =R 75 =R 76 =470Ω, R 79 =24 kΩ, R 77 =R 78 =51Ω, V 1 =3.3V.
 
     While the filter  600  shown in  FIG. 4A  and the filter  700  shown in  FIG. 4B  is a Pi-equivalent of a transmission line, it can also be designed as a T-equivalent. 
     There may be active buffering before the filter  700 . It is assumed that the transmission line length between the buffer and the filter is electrically short, i.e., it is shorter than a quarter-wavelength of the highest frequency transmitted. So the termination before the filter is not considered. Because the filter will reflect signals, the termination is designed to be back-end termination so that the reflection will be absorbed by the driver. A typical driver, such as OnSemi NBSGII, may have about 7Ω output resistance. According to  FIG. 4B , the equivalent resistance of the back-end termination is: (7+R 77 ∥R 84 =(7+51)∥360=50 Ω. 
     The three stage filter shown in  FIG. 4A  can have minimum ISI injection by tuning the PIN diode resistance to the largest and the varactor diode capacitance to the smallest. However, for higher bit rates, component parasitic capacitance and inductance reduce the filter bandwidth to less than theoretical. Therefore, a single stage filter  800  is designed for higher bit rate applications, and an embodiment is illustrated in  FIG. 4C . 
     Instead of using inductor components that have parasitic capacitance from the part and pads, single stage filter  800  uses microstrip transmission lines to provide the required inductance L. Accordingly, if the transmission line trace width is W, the transmission line length x can be calculated by 
                   x   =     L     L   0               (   4   )               where, L 0 =C 0 β 0   2 ,  (5)
 
                       C   0     =         ɛ   γ     +   1.41       1   ⁢     n   ⁡     (       0.58   ⁢           ⁢   H         0.8   ⁢           ⁢   W     +   t       )             ,           (   6   )                 Z   0     =       87         ɛ   γ     +   1.41         ⁢           ⁢   1   ⁢   n   ⁢           ⁢     (       5.98   ⁢           ⁢   H         0.8   ⁢           ⁢   W     +   t       )               (   7   )               
∈ γ , H, t are dielectric constant of board material, board material height, and trace thickness, respectively.
 
     VP 81  is the pin diode driver, VC 91  is the varactor diode driver, and Vb is the DC bias voltage. D 81  and D 82  are the pin diodes and D 83  and D 84  are the varactor diodes. 
       FIGS. 5-22  show the operation of a three stage filter  600  having the following component values: R 1 =R 2 =R 3 =R 4 =R 5 =R 6 =470 Ohms (Ω), R 7 =R 8 =51Ω, R 10 =R 11 =360Ω, R 12 =R 13 =R 14 =10KΩ, R 15 =R 16 =0Ω, L 1 =L 2 =L 3 =L 4 =0.67 nano Henrys (nH) to have a FR4 transmission line emulation range from 6 inch to 40 inch long, or L 1 =L 2 =L 3 =L 4 =3.3 nH to have a emulation range from 30 inch to 90 inch long. In  FIG. 4A , D 1 =D 2 =D 3 =D 4 =D 5 =D 6  and D 11 =D 12 =D 13 =D 14 =D 15 =D 16 . Note that all eye diagrams are shown with 10% pre-emphasis applied to the first transition. 
       FIG. 5  illustrates how closely the filter  600  (L 1 =L 2 =L 3 =L 4 =0.67 nH) tracks the attenuation of a 6 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz.  FIG. 6  shows an illustration of the 6 inch filter eye diagram and  FIG. 7  shows an illustration of a 6 inch transmission line eye diagram at 1 Gbps.  FIG. 8  shows an illustration of a 6 inch filter eye diagram and  FIG. 9  shows an illustration of a 6 inch transmission line eye diagram at 6.4 Gbps.  FIGS. 6 and 7  illustrate the similarity between the eye closures of 6 inch filter and a 6 inch transmission line eye diagram at 1 Gbps, while  FIGS. 8 and 9  illustrate the similarity between the eye closures of 6 inch filter and a 6 inch transmission line eye diagram at 6.4 Gbps. 
       FIG. 10  illustrates how closely the filter  600  (L 1 =L 2 =L 3 =L 4 =3.3 nH) tracks the attenuation of a 30 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz.  FIG. 11  shows illustrations of a 30 inch filter at 1 Gbps.  FIGS. 12 and 13  show illustrations of a 30 inch filter and transmission line eye diagrams respectively at 6.4 Gbps.  FIGS. 12 and 13  illustrate the similarity between the eye closures of 30 inch filter and a 30 inch transmission line eye diagram at 6.4 Gbps. 
       FIG. 14  illustrates how closely the filter  600  (L 1 =L 2 =L 3 =L 4 =0.67 nH) tracks the attenuation of a 50 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz.  FIGS. 15 and 16  show illustrations of 50 inch filter and 50 inch transmission eye diagrams respectively at 1 Gbps.  FIGS. 17 and 18  show illustrations of 50 inch filter and 50 inch transmission eye diagrams respectively at 6.4 Gbps.  FIGS. 15 and 16  illustrate the similarity between the eye closures of 50 inch filter and a 50 inch transmission line eye diagram at 1 Gbps, while  FIGS. 17 and 18  illustrate the similarity between the eye closures of 50 inch filter and a 50 inch transmission line eye diagram at 6.4 Gbps. 
       FIG. 19  shows an illustrates how closely the filter  600  (L 1 =L 2 =L 3 =L 4 =3.3 nH) tracks the attenuation of a 90 inch FR4 transmission line over a frequency range of 1000 to 6400 MHz.  FIG. 20  illustrates the eye closure of 90 inch filter at 1 Gbps, while  FIGS. 21 and 22  illustrate the similarity between the eye closures of 90 inch filter and a 90 inch transmission line eye diagram at 6.4 Gbps. 
       FIG. 23  illustrates transmission line emulation by a one stage filter, a three stage filter with inductance=0.67 nH, and a three stage filter with inductance=3.3 nH. The one stage filter emulates a 3 inch through 20 inch transmission line successfully, the three stage filter with inductance=0.67 nH emulates a 20 inch, a 30 inch and a 50 inch transmission line successfully, and the three stage filter with inductance=3.3 nH emulates a 30 inch, a 50 inch and a 90 inch transmission line successfully. 
       FIGS. 24-26  illustrate the operation of the three stage filter and the one stage filter using eye diagram representation. In this example, the three stage filter is driven by one output of a NBSG11 buffer and the single stage filter is driven by the other output of the buffer. The three stage filter employs 3.3 nH inductors to inject ISI at lower bit rates. The single stage filter uses 1.4 millimeter long thin lines to serve as 0.7 nH inductance for the filter. It is more difficult to achieve significant eye closure at low bit rates than at high ones. 
     In  FIG. 24  waveforms (A) and (B) show that both filters, at I Gbps, work almost the same when they are tuned to have minimum ISI. This is because the PIN diodes, with zero DC current through them, have the highest resistance between the varactor capacitance and the signal paths, and at 1 Gbps parasitic capacitance and inductance are so small that there is no difference between the three stage and the single stage filters. Waveform (C) shows the maximum ISI injection by the three stage filter when it is tuned to have minimum PIN resistance and maximum varactor capacitance. For I Gbps, the maximum eye closure, 28% UI, is accomplished by this three stage filter. 
     In  FIG. 25 , waveforms (A) and (B) show both filters, at 6.4 Gbps, work differently even though they are tuned to have minimum ISI. This is because the inductance forms a filter with the 50 ohm termination impedance to provide a dominant pole at approximately 
             F   =       R     2   ⁢           ⁢   Π   ⁢           ⁢   L       .           
Parasitics lower this pole further. Waveform (C) shows the maximum ISI injection by the single stage filter. In this case, the filter gives a maximum eye closure of 48%. At 6.4 Gbps, the three stage filter provides eye closure from 35% to 100%, while the single stage filter provides eye closure under 48%.
 
     According to an embodiment of the invention, the filters are calibrated so as to closely match eye closure of real transmission lines. The problem solved by the calibration is illustrated in  FIG. 26 .  FIG. 26  illustrates that waveforms (A) and (8) are more like transmission line eye diagrams than waveform (C) for the three stage filter at 6.4 Gbps. In this example, for waveform (A), the varactor diode voltages are: VC 1 =25V, VC 2 =10V, VC 3 =4V, the pin diode voltages are: VP 1 =0V, VP 2 =−1V, VP 3 =−1V. For waveform (B), the varactor diode voltages are: VC 1 =25V, VC 2 =20V, VC 3 =4V, the pin diode voltages are: VP 1 =0V, VP 2 =−1.7V, VP 3 =−1V. For waveform (C), the varactor diode voltages are: VC 1 =VC 2 =VC 3 =25V, the pin diode voltages are: VP 1 =VP 2 =VP 3 =0V. 
     One method for calibration is to use simulation. For example, modeling software may be used to obtain the optimized tuning parameters for emulating a certain length of transmission line. The PIN resistors are converted to PIN control voltages using the PIN diode R-I curve (e.g., as shown in  FIG. 3A ). In terms of percentage of the eye closure, a lookup table, for which tuning parameters VCI-VC 3  and VPI-VP 3  are indexed, can be built. Accordingly, the desired eye can be achieved by checking the lookup table. 
     Another method for calibration is to measure the filter&#39;s eye that matches very well with the transmission line eye, as waveforms (A) and (B) in  FIG. 26 . The same lookup table using VCI-VC 3 , VPI-VP 3  as index can also be built. In this way, the tuning parameters can be set up to get the desired eye diagram based on the real measurement data of the filter. These tunable filters provide a method to achieve ISI for many applications. 
     Accordingly, two differential ISI injection filters are designed to work from 1 Gbps to 6.4 Gbps for SerDes device testing. By using PIN and varactor diodes, the filters can be made to match the characteristics of transmission lines over a larger range of lengths than the varactor only filter. The three stage filter may close an eye by almost 28% for 1 Gbps data stream and by up to 100% for 6.4 Gbps data stream. The single stage filter can be used as the baseline when it is tuned to have minimum ISI injection. It can also serve as a fine tune filter for higher bit rate ISI injection. 
     In the forgoing specification, the invention has been described with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are accordingly to be regarded in an illustrative sense rather than a restrictive sense.