Abstract:
A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Description:
Field of the INVENTION  
         [0001]    The present invention pertains to the field of electronic circuits. More particularly, the present invention relates to the design of flip-flop circuitry.  
         BACKGROUND OF THE INVENTION  
         [0002]    Flip-flop circuits are used to maintain an output state (Q) based upon the sampling of an input data signal (D) at a particular point in time determined by a clock signal (CLK). The sampling of the input data signal is activated either by the edge or the level of the clock signal. At all other times, the output of the flip-flop circuit will not respond to changes in the input data signal.  
           [0003]    Typical flip-flops have shortcomings. One such typical flip-flop is the master-slave flip-flop, which consists of two stages, the master and the slave. To change the output of the master-slave flip-flop, a signal must propagate through both the master and the slave stages. In fast circuits, this delay can pose problems.  
           [0004]    Additionally, the number of logic devices used to build both the master and the slave can be large. This large number of devices may consume more power than desirable.  
           [0005]    Also, the master-slave flip-flop requires that the data input be present and stable for a given time before the clock activates the sampling for the flip-flop to accurately respond to the data input. This is called the data “setup” time. Setup time affects the speed at which a flip-flop may operate. Thus, a setup time may pose a problem.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:  
         [0007]    [0007]FIG. 1 is a block diagram of a flip-flop;  
         [0008]    [0008]FIG. 2 is a block diagram of a computer system;  
         [0009]    [0009]FIG. 3 is a circuit diagram of an embodiment of a flip-flop;  
         [0010]    [0010]FIG. 4 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 3;  
         [0011]    [0011]FIG. 5 is a circuit diagram of another embodiment of a flip-flop;  
         [0012]    [0012]FIG. 6 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 5.  
     
    
     DETAILED DESCRIPTION  
       [0013]    A method and apparatus for a flip-flop are described. The invention has a clock-to-output delay of two inverters in one embodiment. In another embodiment the clock-to-output delay is an inverter and a pass transistor. Because of the reduced clock-to-output delay, the flip-flops are extremely fast. The flip-flops do not require any setup time. The output of the flip-flops is also buffered. This buffering isolates the keeper circuit from the load. The flip-flops require fewer transistors than conventional flip-flop implementations, so may be smaller in size and/or consume less power.  
         [0014]    [0014]FIG. 1 is a block diagram of a flip-flop. An input signal in the form of a clock is received  102 . The clock input signal is next checked to determine if it is requesting a data input sample  104 . If the input clock signal is not requesting a data input sample, then the input clock signal is checked again at  104 . If the input clock signal is requesting a data input sample, then the data input signal is sampled  106 . After the data input signal is sampled  106 , the data input signal sample is transferred to a storage element  108 . The storage element, representing the data input signal sample, is then buffered  110 , and the buffered signal is presented as the output  112 .  
         [0015]    [0015]FIG. 2 is a block diagram of a computer system. The block diagram is a high level conceptual representation and may be implemented in a variety of ways and by various architectures. Bus system  202  interconnects a Central Processing Unit (CPU)  204 , Read Only Memory (ROM)  206 , Random Access Memory (RAM)  208 , storage  210 , display  220 , audio,  222 , keyboard  224 , pointer  226 , miscellaneous inputloutput (I/O) devices  228 , and communications  230 . The bus system  202  may be for example, one or more of such buses as a system bus, Peripheral Component Interconnect (PCI), Advanced Graphics Port (AGP), Small Computer System Interface (SCSI), Institute of Electrical and Electronics Engineers (IEEE) standard number  1394  (FireWire), etc. The CPU  204  may be a single, multiple, or even a distributed computing resource. The ROM  206  may be any type of non-volatile memory, which may be programmable such as, mask programmable, flash, etc. RAM  208  may be, for example, static, dynamic, synchronous, asynchronous, or any combination. Storage  210 , may be Compact Disc (CD), Digital Versatile Disk (DVD), hard disks, optical disks, tape, flash, memory sticks, video recorders, etc. Display  220  might be, for example, a Cathode Ray Tube (CRT), Liquid Crystal Display (LCD), a projection system, Television (TV), etc. Audio  222  may be a monophonic, stereo, three dimensional sound card, etc. The keyboard  224  may be a keyboard, a musical keyboard, a keypad, a series of switches, etc. The pointer  226 , may be, for example, a mouse, a touchpad, a trackball, joystick, etc. I/O devices  228 , might be a voice command input device, a thumbprint input device, a smart card slot, a Personal Computer Card (PC Card) interface, virtual reality accessories, etc., which may optionally connect via an input/output port  229  to other devices or systems. An example of a miscellaneous I/O device  228  would be a Musical Instrument Digital Interface (MIDI) card. Communications device  230  might be, for example, an Ethernet adapter for local area network (LAN) connections, a satellite connection, a settop box adapter, a Digital Subscriber Line (xDSL) adapter, a wireless modem, a conventional telephone modem, a direct telephone connection, a Hybrid-Fiber Coax (HFC) connection, cable modem, etc. Note that depending upon the actual implementation of a computer system, the computer system may include some, all, more, or a rearrangement of components in the block diagram. For example, a thin client might consist of a wireless hand held device that lacks, for example, a traditional keyboard. Thus, many variations on the system of FIG. 2 are possible.  
         [0016]    The present invention is capable of being embodied in each of the blocks of the computer system described above. Flip-flop  205  in the CPU  204  may be used to store the results of processing. Flip-flop  205  may be used to latch the signals received from the bus system  202 . A flip-flop  207  used in ROM  206 , may store the results of an access for presentation as an output on bus system  202 . Likewise, the ROM  206  may embody the flip-flop  207  to latch an address that the bus system  202  presents to the ROM  206 . A flip-flop  209  used in RAM  208 , may store the results of an access for presentation as an output on bus system  202 . RAM  208  may embody the flip-flop  209  to latch an address that the bus system  202  presents to the RAM  208 . The RAM  208  may also use a flip-flop  209  as a storage element for either main storage, or cache storage. Storage  210  may for example, embody a flip-flop  211 , as an output storage device to present its output to the bus  202 . Flip-flop  211  may also store such things as user options for operation of the storage  210  which are received from the bus  202 . Display  220  might use flip-flop  221  to latch a display signal, for example, if display  220  is an LCD display, flip-flop  221  might be used in an active-matrix as the storage element for a pixel. If display  220  is a CRT, flip-flop  221 , might be used to store correction parameters, such as pin cushion correction. Audio  222  may use flip-flop  223  to store input and/or output signals received/sent to bus system  202 . The keyboard  224  may use flip-flop  225  to store the status of indicators such as the numeric lock, caps lock, scroll lock, etc. The pointer  226 , for example as a mouse, may use flip-flop  227  to store the status of a user click. An I/O device  228 , for example in a thumbprint input device, may use flip-flop  229  to store the results of a thumbprint scan. Communications device  230  might be, for example, an Ethernet adapter which may use flip-flop  231  to store the results of a received packet.  
         [0017]    [0017]FIG. 3 is a circuit diagram of an embodiment of a flip-flop. Flip-flop  300 , has a Data input  301  to receive data. The Data input  301  is connected to the gate of a P-type transistor  302  and the gate of an N-type transistor  312 . The source of transistor  302  is connected to a positive power supply Vcc. The source of transistor  312  is connected to a less positive power supply than Vcc, designated as ground by the ground symbol. The drain of transistor  302  is connected to the source of a P-type transistor  304 . The drain of transistor  304  is connected to the source of a P-type transistor  306 . The drain of transistor  306  is connected to the drain of a N-type transistor  308 . The source of transistor  308  is connected to the drain of a N-type transistor  310 . The source of transistor  310  it connected to the drain of transistor  312 . Flip-flop  300 , has a clock input  319 , denoted Clk, to receive a clock. The Clk input  319  is connected to the input of an inverter  320 , and the gate of transistor  306 . The output of inverter  320  is denoted as Clkb  321 , and is connected to the input of inverter  322 , and the gate of transistor  308 . The output of inverter  322 , denoted  323 , is coupled to the input of inverter  324 . The output of inverter  324 , denoted Clkbd  325 , is coupled to the input of inverter  326 , and the gate of transistor  304 . The output of inverter  326 , denoted Clkd  327 , id coupled to the gate of transistor  310 . The drain of transistor  306  and the drain of transistor  308  are coupled to the node  307 . Node  307  is coupled to the input of inverter  314 . The output of inverter  314 , denoted as  315 , is coupled to the input of inverter  316 . The output of inverter  316  is coupled to the input of inverter  314 . The node  307  is coupled to the input of the inverter  318 . The output of inverter  318 , denoted as Q  317 , is the output of the flip-flop  300 .  
         [0018]    [0018]FIG. 4 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 3. Operation is illustrated for the flip-flop  300  when the Data is in a binary high state at the sequence labeled  402 , and operation is illustrated for the flip-flop  300  when the Data is in a binary low state at the sequence labeled  404 .  
         [0019]    Sequence  402  begins when the Clk signal makes a high to low transition. This Clk high to low transition propagates through the flip-flop circuitry and causes the Clkb low to high transition, the Clkbd low to high transition, the Clkd high to low transition. The Clkb transition from low to high “samples” the Data, which in this example, is in a high state, the result is that the output Q is in a high state.  
         [0020]    Sequence  404  begins when the Clk signal makes a high to low transition. This Clk high to low transition propagates through the flip-flop circuitry and causes the Clkb low to high transition, the Clkbd low to high transition, the Clkd high to low transition. The Clk transition from high to low “samples” the Data, which in this example, is in a low state, the result is that the output Q is in a high low.  
         [0021]    Operation of the flip-flop  300  may be more easily understood by considering transistors  302 ,  304 ,  306 ,  308 ,  310 , and  312  as a “gated” inverter. When the inverter is “active,” a signal, dependent on the state of Data  301 , will be transferred at the “gated” output junction of  306  and  308 , denoted as node  307 . The signal at node  307  will be “kept” by the keeper circuit of  314  and  316 , and the signal at node  307  will be buffered by inverter  318  and output as Q  317 . When the “gated” inverter is not active, that is, it is no longer actively driving the node  307  and has entered a high impedance (Hi-Z) state, then the output Q  317  will be maintained because the keeper circuit has maintained the state when the “gated” inverter was actively driving node  307 .  
         [0022]    The “gated” inverter is actively driving node  307  toward a high state when the gates of transistors  302 ,  304 , and  306 , corresponding to the signals Data  301 , Clkbd  325  and Clk  319  respectively, are in a low state. Conversely, the “gated” inverter is actively driving node  307  toward a low state when the gates of transistors  308 ,  310 , and  312 , corresponding to the signals Clkb  321 , Clkd  327 , and Data  301  respectively, are in a high state.  
         [0023]    [0023]FIG. 5 is a circuit diagram of another embodiment of a flip-flop. Flip-flop  500 , has a Data input  501  to receive data. The Data input  501  is connected to the input of a transmission gate  530 . The output of transmission gate  530 , denoted by node  531 , is connected to the input of inverter  532 . The output of inverter  532 , is connected to the input of transmission gate  534 . The output of transmission gate  534  is coupled to the node  507 . Node  507  is coupled to the input of inverter  514 . The output of inverter  514 , denoted as  515 , is coupled to the input of inverter  516 . The output of inverter  516  is coupled to the input of inverter  514 . The node  507  is coupled to the input of the inverter  518 . The output of inverter  518 , denoted as Q  517 , is the output of the flip-flop  500 . Flip-flop  500 , has a clock input  519 , denoted Clk, to receive a clock. The Clk input  519  is connected to the input of an inverter  520 , and the N-type transistor control gate of transmission gate  534 . The output of inverter  520  is denoted as Clkb  521 , and is connected to the input of inverter  522 , and the P-type transistor control gate of transmission gate  534 . The output of inverter  522 , denoted Clkd  523 , is coupled to the P-type transistor control gate of transmission gate  530 . The output of inverter  524 , denoted  5  Clkbd  525 , is coupled to the N-type transistor control gate of transmission gate  530 .  
         [0024]    [0024]FIG. 6 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 5. Operation is illustrated for the flip-flop  500  when the Data is in a binary high state at the sequence labeled  602 , and operation is illustrated for the flip-flop  500  when the Data is in a binary low state at the sequence labeled  604 .  
         [0025]    Sequence  602  begins when the Clk signal makes a low to high transition. This Clk low to high transition propagates through the flip-flop circuitry and causes the Clkb high to low transition, the Clkd low to high transition, the Clkdb high to low transition.  
         [0026]    The Clk transition from low to high “samples” the Data, which in this example, is in a high state, the result is that the output Q is in a high state.  
         [0027]    Sequence  604  begins when the Clk signal makes a low to high transition. This Clk low to high transition propagates through the flip-flop circuitry and causes the Clkb high to low transition, the Clkd low to high transition, the Clkdb high to low transition.  
         [0028]    The Clk transition from low to high “samples” the Data, which in this example, is in a low state, the result is that the output Q is in a high low.  
         [0029]    Operation of the flip-flop  500  may be more easily understood by considering transmission gates  530  and  534  as sequentially “allowing” the Data input  501  signal to pass to inverter  532  and then onto node  507 . As used in this discussion, a transmission gate is considered to be “on” then the transmission gate has a low impedance between the input and output terminals of the transmission gate. Conversely, the transmission gate is considered “off” when there is a high impedance between the input and the output terminals of the transmission gate. The Data input signal  501  will propagate to the input of inverter  532 , denoted as node  531 , when the transmission gate  530  is on. The signal from the output of inverter  532  will propagate to node  507  when transmission gate  534  is on. The timing of when transmission gates  530  and  534  are on and off may be determined by the control gate signals Clk, Clkb, Clkd, and Clkbd as illustrated in FIG. 6.  
         [0030]    In instances where flip-flop  500  may be operated with a low speed clock signal (Clk) or where the clock signal (Clk) may be stopped or paused, it may be desirable to place a keeper circuit attached to node  531 . Such a keeper circuit may be one as is illustrated by the inverter  514 , node  515 , inverter  516 , and connection to node  507 . The purpose of such a keeper circuit attached to node  531  would be to maintain the signal transferred when transmission gate  530  was on but is now off.  
         [0031]    Thus, a method and apparatus for flip-flop have been described. Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.