Abstract:
A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase to the potentials, and that output data signals and inverted data signals; a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals; and a plurality of local signal lines extending parallel to the predetermined direction, to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals.

Description:
[0001]    This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-181299 filed on Aug. 13, 2010, the content of which is incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device having a plurality of memory elements. 
         [0004]    2. Description of Related Art 
         [0005]    The configuration of a DRAM (Dynamic Random Access Memory) as an example of a semiconductor device will be described below.  FIG. 1  of the accompanying drawings is a block diagram showing a configurational example of a semiconductor device according to the related art. 
         [0006]    As shown in  FIG. 1 , semiconductor device  10  has a plurality of memory cell blocks  20 - 1  through  20 - n  (n represents an integer of 1 or greater) each including a plurality of memory elements, CA pad  31  for inputting address signals and command signals, DQ pad  32  for sending data to and receiving data from an external circuit, column decoders  41  and row decoders  42  for specifying memory elements according to address signals, data input/output control circuit  51  for controlling the inputting and outputting of data, and data output circuit  52  and data input circuit  53  which are connected between data input/output control circuit  51  and DQ pad  32 . 
         [0007]    Data output circuit  52  has a data amplifier (not shown) and an output circuit (not shown). Each of memory cell blocks  20 - 1  through  20 - n  is combined with column decoder  41  and row decoder  42 . A memory cell block that is combined with column decoder  41  and row decoder  42  will be referred to as “bank”. 
         [0008]      FIG. 2  of the accompanying drawings is a block diagram showing a configurational example of each memory cell block of the semiconductor device shown in  FIG. 1 . In  FIG. 2 , a vertical-axis direction is referred to as a Y-axis direction and a horizontal-axis direction as an X-axis direction. 
         [0009]    As shown in  FIG. 2 , the memory cell block has a matrix of memory cell arrays  22  each including a plurality of memory elements. Each of the memory cell arrays will be referred to as “MAT”. Since the memory cell block includes a plurality of MATs  22 , each MAT serves as one of a plurality of units into which the memory elements in the memory cell block are divided. 
         [0010]    Word lines  21  are connected to row decoder  42 . Each of word lines  21  extends through a linear array of MATs  22  that are disposed along the X-axis direction. Though only one word line  21  is shown in  FIG. 2 , there are as many word lines  21  as the number of memory elements disposed along the Y-axis direction in each of MATs  22 . Word lines  21  are connected to the gate electrodes of respective select transistors of the memory elements in each MAT  22 . 
         [0011]    Sense amplifier sections (hereinafter referred to as “SAMPs”)  23  are disposed on the respective opposite sides of each MAT  22  which are spaced along the Y-axis direction. Subword drivers (hereinafter referred to as “SWDs”)  24  are disposed on the respective opposite sides of each MAT  22  which are spaced along the X-axis direction. 
         [0012]    Local input/output lines (hereinafter referred to as “LIO lines”) serving as signal lines for guiding the potentials of the bit lines of the select transistors of the memory elements to data output circuit  52  are connected to SAMPs  23 . The LIO lines extend parallel to the X-axis direction. The LIO lines are connected to main input/output lines (hereinafter referred to as “MIO lines”) which extend parallel to the Y-axis direction. Y switch lines (hereinafter referred to as “YS lines”) for transmitting signals to connect the bit lines of the select transistors of the memory elements to the LIO lines and the sense amplifiers (not shown) are connected to SAMPs  23 . The YS lines are connected to column decoders  41 . 
         [0013]    Regions where lines connected to SWDs  24  and the LIO lines cross each other three-dimensionally while being electrically isolated from each other are called subword crosses (hereinafter referred to as “SWCs”)  25 . Examples of semiconductor devices which have configurations similar to is the layout shown in  FIG. 2  are disclosed in JP2006-172577A and JP2006-253270A. 
         [0014]      FIG. 3  of the accompanying drawings is a block diagram showing a configurational example of a sense amplifier section according to the related art. SAMPs  23   a ,  23   b  shown in  FIG. 3  refer to sense amplifier sections that are compatible with an open bit line structure which is employed in a DRAM having a cell area 6F 2 . 
         [0015]    As shown in  FIG. 3 , YS lines YS 0  through YSn are disposed between the SAMPs. SAMP  23   a  is disposed between MAT 22   a  and MAT 22   b . SAMP  23   a  includes a plurality of sense amplifiers  26 , a plurality of bit lines equalizers  27 , and a pair of Y switch sections  28   a ,  28   b  disposed in sandwiching relation to sense amplifiers  26  and bit lines equalizers  27 . 
         [0016]    Four bit lines BLL 0 T through BLL 3 T that are connected respectively to the select transistors in MAT  22   a  and four bit lines BLR 0 B through BLR 3 B that are connected respectively to the select transistors in MAT  22   b  are connected to sense amplifiers  26  and bit lines equalizers  27 . 
         [0017]    The memory elements in MAT  22   a  which are connected to bit lines BLL 0 T through BLL 3 T store data entered from an external circuit, and the memory elements in MAT  22   b  which are connected to bit lines BLR 0 B through BLR 3 B store data in opposite phase entered from the external circuit. The memory elements in MAT  22   a  which are connected to bit lines BLL 0 T through BLL 3 T are called true cells. 
         [0018]    If the memory cell connected to bit line BLL 0 T stores a high signal, then the memory cell connected to bit line BLR 0 B stores a low signal. The memory elements connected to bit lines BLL 0 T through BLL 3 T will hereinafter be referred to as true memory elements, and the memory elements connected to bit lines BLR 0 B through BLR 3 B as bar memory elements. 
         [0019]    Sense amplifier  26  amplifies a potential that appears on bit line BLLkT (k represents an integer equal or greater than 0) that is selected by an address signal. A signal which represents the amplified potential will hereinafter be referred to as “data signal” because the amplified potential corresponds to data recorded in a memory element. Sense amplifier  26  also amplifies a potential that appears on bit line BLRkB which is in opposite phase to the potential that appears on bit line BLLkT. A signal which represents the amplified potential will hereinafter be referred to as “inverted data signal”. 
         [0020]    Y switch section  28   a  includes a plurality of MOS (Metal Oxide Semiconductor) transistors  211   a  through  211   d . MOS transistors  211   a  through  211   d  have respective gate electrodes connected to YS line YS 0 , respective drain electrodes connected respectively to bit lines BLL 0 T through BLL 3 T connected to MAT  22   a , and respective source electrodes connected respectively to LIO lines LIO 0 T through LIO 3 T. 
         [0021]    Y switch section  28   b  includes a plurality of MOS transistors  212   a  through  212   d . MOS transistors  212   a  through  212   d  have respective gate electrodes connected to YS line YS 0 , respective drain electrodes connected respectively to bit lines BLR 0 B through BLR 3 B which are connected to MAT  22   b , and respective source electrodes connected respectively to LIO lines LIO 0 B through LIO 3 B. 
         [0022]    The letter “T” in LIO 0 T through LIO 3 T means that LIO lines LIO 0 T through LIO 3 T are signal lines connected to true memory elements, and the numerals “0” through “3” therein represent numbers for identifying the four bit lines in MAT  22   a . The letter “B” in LIO 0 B through LIO 3 B means that LIO lines LIO 0 B through LIO 3 B are signal lines connected to bar memory elements, and the numerals “0” through “3” therein represent numbers for identifying the four bit lines in MAT  22   b.    
         [0023]    LIO lines LIO 0 T through LIO 3 T and LIO lines LIO 0 B through LIO 3 B are connected to LIO selector  220  which is connected to DQ pad  32  through data output circuit  52 . Depending on a selected address, LIO selector  220  selects two of LIO lines LIO 0 T through LIO 3 T and LIO lines LIO 0 B through LIO 3 B as a pair and connects the selected LIO lines to data output circuit  52 . 
         [0024]      FIG. 4  of the accompanying drawings is a schematic diagram showing an example of the layout of the Y switch sections shown in  FIG. 3 . 
         [0025]    Since Y switch sections  28   a ,  28   b  are identical in configuration to each other, only Y switch section  28   a  will be described below.  FIG. 4  also shows SAMP  23   a  and Y switch section  281  in SAMP  23   b  which is spaced from SAMP  23   a  in the X-axis direction with an SWC interposed therebetween. 
         [0026]    Y switch section  281  includes MOS transistors  221   a  through  221   d  which correspond to MOS transistors  211   a  through  211   d  of Y switch section  28   a . MOS transistors  221   a  through  221   d  are connected respectively to bit lines BL 4  through BL 7 . 
         [0027]    The active pattern of each MOS transistor is represented by a dotted rectangle, and the pattern of each contact plug that connects interconnection in an upper layer and interconnection in lower layer to each other is represented by a hatched circular dot. YS line YS 0  corresponds to the gate electrodes of MOS transistors  211   a  through  211   d , and controls MOS transistors  211   a  through  211   d  to be turned on and off. YS line YS 1  corresponds to the gate electrodes of MOS transistors  221   a  through  221   d , and controls MOS transistors  221   a  through  221   d  to be turned on and off. 
         [0028]    LIO line LIO 0 T is connected to MOS transistors  211   a ,  221   a , and LIO line LIO 2 T is connected to MOS transistors  211   c ,  221   c . LIO line LIO 1 T is connected to MOS transistors  211   b ,  221   b , and LIO line LIO 3 T is connected to MOS transistors  211   d ,  221   d . SAMPs are thus disposed one on each side of an SWC in the X-axis direction, and their Y switch sections are connected to each other by LIO lines. 
         [0029]    A process of reading memory cells of the DRAM which is constructed as described above will be briefly described below. 
         [0030]    When an address signal and a command signal are entered from an external circuit via CA pad  31 , the potential on word line  21  selected by row decoder  42  increases, and the potential which corresponds to the data stored in a memory element connected to word line  21  appears on bit line BLLkT, and the potential in opposite phase appears on bit line BLRkB. The potential that appears on bit line BLLkT and the potential that appears on bit line BLRkB are amplified by sense amplifier  26 . 
         [0031]    Signals which represent the potentials amplified by sense amplifier  26 , i.e., a data signal and an inverted data signal, are transmitted respectively to paired LIO lines LIOjT, LILjB (j represents an integer of 1 or greater) when the MOS transistors of the Y switch sections that are selected by column decoder  41  via a YS line, turn on. The data signal and the inverted data signal that are transferred along LIO lines LIOjT, LILjB are sent to data output circuit  52  via a pair of MIO lines. Data output circuit  52  outputs data represented by the data signal and the inverted data signal to an external circuit via DQ pad  32 . 
         [0032]    Coupling noise of four LIO lines in each of the Y switch sections of the sense amplifier sections that are connected to the true and bar cells will be described below. Of the four LIO lines in each of Y switch sections connected to the true and bar cells, each of two inner LIO lines LIO 2 , LIO 1  (see  FIG. 5  of the accompanying drawings) is spaced given distances from other LIO lines on the opposite sides thereof. Therefore, two inner LIO lines LIO 2 , LIO 1  are subject to coupling noise that is twice as large as the coupling noise that is applied to outer two LIO lines LIO 0 , LIO 3 . 
         [0033]      FIG. 6  of the accompanying drawings is a table that shows the operational states of the LIO lines of the switch sections shown in  FIG. 4  and that shows how coupling noise affects the operational states of the LIO lines. The table is shared by the LIO lines that are in the Y switch sections connected to the true and bar cells, so that letters indicating which of true cells and bar cells the LIO lines belong to are omitted from  FIG. 6 . 
         [0034]    As shown in  FIG. 6 , there are sixteen patterns depending on the operational states (hereinafter simply referred to as “states”) of the LIO lines. Each of the states shown in  FIG. 6  includes signals of Y switch section  281  on the left side of the SWC and signals of Y switch section  28   a  on the right side of the SWC for respective LIO lines L 100  through LIO 3 . The signals include high signals represented by “H” and low signals represented by “L”. 
         [0035]    In states  5 ,  6 ,  11 ,  12 , LIO line L 102  is positioned between LIO lines to which there is applied a potential that is in opposite phase to a potential applied to LIO line L 102 . In states  3 ,  6 ,  11 ,  14 , LIO line LIO 1  is positioned between LIO lines to which there is applied a potential that is in opposite phase to a potential applied to LIO line LIO 1 . It can be seen from  FIG. 6  that there are six states  3 ,  5 ,  6 ,  11 ,  12 ,  14  in which the coupling noise posed on LIO line LIO 1  or LIO line L 102  or both is maximum. In these six states, LIO line LIO 1  and LIO line L 102  tend to cause a delay in transition due to the effect of coupling noise, resulting in a longer data read time. 
       SUMMARY 
       [0036]    In one embodiment, there is provided a semiconductor device that includes a plurality of memory cell arrays arranged along a predetermined direction, each of the memory cell arrays including a memory elements, a plurality of bit lines associated with the memory cell arrays to read data stored in the memory elements, a plurality of sense amplifier sections associated with the memory cell arrays that amplify potentials which correspond to the data, appearing on selected ones of the bit lines, that amplify potentials in opposite phase to the potentials, that output data signals representing the amplified potentials corresponding to the data in a direction which is different from the predetermined direction, and that output inverted data signals which are in opposite phase to the data signals in a direction which is opposite to the direction in which the data signals are output, a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals, and a plurality of local signal lines extending parallel to the predetermined direction to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0037]    The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0038]      FIG. 1  is a block diagram showing a configurational example of a semiconductor device according to the related art; 
           [0039]      FIG. 2  is a block diagram showing a configurational example of each memory cell block of the semiconductor device shown in  FIG. 1 ; 
           [0040]      FIG. 3  is a block diagram showing a configurational example of a sense amplifier section according to the related art; 
           [0041]      FIG. 4  is a schematic diagram showing an example of the layout of the Y switch sections shown in  FIG. 3 ; 
           [0042]      FIG. 5  is a diagram illustrative of the effect of coupling noise between LIO lines of the switch sections shown in  FIG. 4 ; 
           [0043]      FIG. 6  is a table showing the operational states of the LIO lines of the switch sections shown in  FIG. 4  and how coupling noise affects the operational states of the LIO lines; 
           [0044]      FIG. 7  is a schematic diagram showing a configurational example of an essential portion of a semiconductor device according to a first exemplary embodiment of the present invention; 
           [0045]      FIG. 8  is a block diagram showing a configurational example of a memory cell block of the semiconductor device according to the first exemplary embodiment; 
           [0046]      FIG. 9  is a table showing the operational states of LIO lines and how coupling noise affects the operational states of the LIO lines in the semiconductor device according to the first exemplary embodiment; 
           [0047]      FIG. 10  is a diagram illustrative of the manner in which the effect of coupling noise between inner LIO lines is reduced; 
           [0048]      FIG. 11  is a block diagram showing another configurational example of the memory cell block of the semiconductor device according to the first exemplary embodiment; and 
           [0049]      FIG. 12  is a schematic diagram showing a configurational example of an essential portion of a semiconductor device according to a second exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0050]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0051]    Semiconductor devices according to exemplary embodiments of the present invention are different from the semiconductor device according to the related art shown in  FIG. 1  with respect to a portion of a memory cell block. Therefore, structural details other than the memory cell block will be omitted from illustration, and only details of the semiconductor devices according to the exemplary embodiments which are different from the semiconductor device shown in  FIGS. 1 through 4  will be described below. 
       First Exemplary Embodiment 
       [0052]    A semiconductor device according to a first exemplary embodiment of the present invention will be described below.  FIG. 7  is a schematic diagram showing a configurational example of an essential portion of the semiconductor device according to the first exemplary embodiment of the present invention. In  FIG. 7 , a horizontal-axis direction as an X-axis direction, and a vertical-axis direction is referred to as a Y-axis direction. 
         [0053]    In the present exemplary embodiment, the configuration of Y switch sections connected to true memory elements and the layout of LIO lines with respect thereto according to features of the present invention will be described above. The configuration of Y switch sections connected to bar memory elements and the layout of LIO lines with respect thereto according to features of the present invention are similar and will not be described in detail below. 
         [0054]    According to the present exemplary embodiment, Y switch section  110  shown in  FIG. 7  is included instead of Y switch section  28   a  in the sense amplifier section shown in  FIG. 3 , and Y switch section  111  shown in  FIG. 7  is included instead of Y switch section  281  in the sense amplifier section shown in  FIG. 3 . According to the present exemplary embodiment, furthermore, in the SWC between switch section  110  and switch section  111 , the first and second ones, i.e., LIO lines LIO 0 T, LIO 2 T, of the four LIO lines LIO 0 T through LIO 3 T cross each other (are twisted) in electrically insulated relation to each other, and the third and fourth ones, i.e., LIO lines LIO 1 T, LIO 3 T, of the four LIO lines LIO 0 T through LIO 3 T cross each other (are twisted) in electrically insulated relation to each other. 
         [0055]    In  FIG. 7 , LIO lines LIO 2 T, LIO 3 T are indicated by the dot-and-dash lines in order to make the crossing LIO lines more identifiable. 
         [0056]    In Y switch section  111 , LIO lines LIO 0 T, LIO 2 T extend parallel to the X-axis direction, with LIO line LIO 0 T being disposed above LIO line LIO 2 T. In the SWC between Y switch sections  110 ,  111 , LIO lines LIO 0 T, LIO 2 T are positionally switched around in the Y-axis direction. In Y switch section  110 , LIO lines LIO 0 T, LIO 2 T extend parallel to the X-axis direction, with LIO line LIO 2 T being disposed above LIO line LIO 0 T. LIO lines LIO 0 T, LIO 2 T are positionally switched around in the Y-axis direction alternately in the successive Y switch sections. 
         [0057]    In Y switch section  111 , LIO lines LIO 1 T, LIO 3 T extend parallel to the X-axis direction, with LIO line LIO 1 T being disposed above LIO line LIO 3 T. In the SWC between Y switch sections  110 ,  111 , LIO lines LIO 1 T, LIO 3 T are positionally switched around in the Y-axis direction. In Y switch section  110 , LIO lines LIO 1 T, LIO 3 T extend parallel to the X-axis direction, with LIO line LIO 3 T being disposed above LIO line LIO 1 T. LIO lines LIO 1 T, LIO 3 T are positionally switched around in the Y-axis direction alternately in the successive Y switch sections. 
         [0058]    According to the present exemplary embodiment, the first and second LIO lines, i.e., LIO lines LIO 0 T, LIO 2 T, are twisted in electrically insulated relation to each other, and the third and fourth LIO lines, i.e., LIO lines LIO 1 T, LIO 3 T, are twisted in electrically insulated relation to each other, is in the SWC. This arrangement is effective for reducing the effect of coupling noise between adjacent LIO lines for reasons to be described later. 
         [0059]    One example of a pattern in which two LIO lines are twisted in electrically insulated relation to each other will be described below. It is assumed that LIO lines LIO 0 T, LIO 2 T are twisted in electrically insulated relation. 
         [0060]    LIO lines LIO 0 T, LIO 2 T are formed of a first aluminum layer. In the twisted region in the SWC, LIO line LIO 0 T is formed of a second aluminum layer which is disposed above the first aluminum layer. LIO line LIO 0 T formed of the second aluminum layer is called “second aluminum layer LIO 0 T”. LIO line LIO 0 T which extends from Y switch section  111  is connected to one end of second aluminum layer LIO 0 T through a via plug, and the other end of second aluminum layer LIO 0 T is connected to LIO line LIO 0 T which extends from Y switch section  110  through a via plug. 
         [0061]    The above structure makes it possible to twist LIO lines LIO 0 T, LIO 2 T in electrically insulated relation to each other. In the twisted region in the SWC, LIO line LIO 2 T may be formed of the second aluminum layer. LIO lines LIO 1 T, LIO 3 T may be twisted in the same pattern as LIO lines LIO 0 T, LIO 2 T. 
         [0062]      FIG. 8  is a block diagram showing a configurational example of a memory cell block of the semiconductor device according to the first exemplary embodiment. As shown in  FIG. 8 , the memory cell block includes Y switch sections  110 ,  110  and LIO lines LIO 0 T through LIO 3 T shown in  FIG. 7 . 
         [0063]    The lengths of LIO lines are determined depending on the MAT configuration according to the specifications of the semiconductor device. Therefore, a single LIO line may extend over a plurality of SWCs. As shown in  FIG. 8 , two LIO lines may be twisted in each of the SWCs to change the coupling between two interconnections of one layer at small intervals. 
         [0064]    The reasons why the arrangement of the present exemplary embodiment is effective for reducing the effect of coupling noise between LIO lines will be described below. 
         [0065]      FIG. 9  is a table showing the operational states of LIO lines and how coupling noise affects the operational states of the LIO lines in the semiconductor device according to the first exemplary embodiment. The table is shared by the LIO lines that are in the Y switch sections connected to the true and bar cells, so that letters indicating which of true cells and bar cells the LIO lines belong to are omitted from  FIG. 9 . 
         [0066]    As shown in  FIG. 9 , there are sixteen patterns depending on the states of the LIO lines. Each of the states shown in  FIG. 9  includes signals of Y switch section  111  on the left side of the SWC and signals of Y switch section  110  on the right side of the SWC for respective LIO lines L 100  through LIO 3 . 
         [0067]    The reasons why noise from adjacent LIO lines is reduced depending on the potentials on the LIO lines will be described below.  FIG. 10  is a diagram illustrative of the effect of coupling noise between inner LIO lines in Y switch section  111  in state  4  in the table shown in  FIG. 9 . In  FIG. 10 , solid-line arrows represent noise due to a high signal, and broken-line arrows represent noise due to a low signal. 
         [0068]    In state  4 , a high potential is applied to LIO lines LIO 0 , LIO 2 , and a low potential is applied to LIO lines LIO 1 , LIO 3 . Since the high potential applied to LIO line LIO 0  is in opposite phase to the low potential applied to LIO line LIO 1 , noise imposed on LIO line LIO 2  by the high potential applied to LIO line LIO 0  and noise imposed on LIO line LIO 2  by the low potential applied to LIO line LIO 1  cancel each other out. Similarly, since the high potential applied to LIO line LIO 2  is in opposite phase to the low potential applied to LIO line LIO 3 , noise imposed on LIO line LIO 1  by the high potential applied to LIO line LIO 2  and noise imposed on LIO line LIO 1  by the low potential applied to LIO line LIO 3  cancel each other out. As a result, each of outer two LIO lines LIO 0 , LIO 3  is subject to noise from either one of two inner LIO lines LIO 1 , LIO 2 . 
         [0069]    In state  4  shown in  FIG. 10 , therefore, coupling noise is prevented from being applied to each of two inner LIO lines LIO 1 , LIO 2 . 
         [0070]    In six states  1 ,  4 ,  7 ,  10 ,  13 ,  16 , the potentials applied to the LIO lines on the opposite sides of the two inner LIO lines are in opposite phase to each other or the potential applied to each of the two inner LIO lines is in phase with the potentials applied to the LIO lines on the opposite sides of the two inner LIO lines. Therefore, no coupling noise causes problems on the two inner LIO lines. 
         [0071]    In state  2 , the signal on LIO line L 100  and the signal on LIO line L 102  are high, and hence the signals on LIO lines L 1 O 0 , L 1 O 2  that are twisted are in phase with each other. The signal on LIO line LIO 1  is high and the signal on LIO line LIO 3  is low, and hence the signals on LIO lines LIO 1 , LIO 3  that are twisted are in opposite phase to each other. 
         [0072]    In Y switch section  111  in state  2 , no coupling noise causes problems on two inner LIO lines L 102 , LIO 1 . In Y switch section  110  in state  2 , LIO line LIO 3  is subject to coupling noise because the signal on LIO line LIO 3  is low and the signals on LIO lines LIO 0 , LIO 1  on the opposite sides of LIO line LIO 3  are high. However, since LIO lines LIO 1 , LIO 3  are twisted, LIO line LIO 3  is not subject to coupling noise in Y switch section  111  though it is subject to coupling noise in Y switch section  110 . Therefore, the effect of coupling noise on LIO line LIO 3  is reduced by one half as a whole. 
         [0073]    States  8 ,  9 ,  15  are similar to state  2 . In states  8 ,  9 ,  15 , the effect of coupling noise on an inner LIO line is reduced by one half as a whole. 
         [0074]    In state  3 , the signal on LIO line L 100  and the signal on LIO line LIO 2  are high, and hence the signals on LIO lines LIO 0 , LIO 2  that are twisted are in phase with each other. The signal on LIO line LIO 1  is low and the signal on LIO line LIO 3  is high, and hence the signals on LIO lines LIO 1 , LIO 3  that are twisted are in opposite phase to each other. 
         [0075]    In Y switch section  110  in state  3 , no coupling noise causes problems on two inner LIO lines LIO 0 , LIO 3 . In Y switch section  111  in state  3 , LIO line LIO 1  is subject to coupling noise because the signal on LIO line LIO 1  is low and the signals on LIO lines L 102 , LIO 3  on the opposite sides of LIO line LIO 1  are high. However, since LIO lines LIO 1 , LIO 3  are twisted, LIO line LIO 1  is not subject to coupling noise in Y switch section  110  though it is subject to coupling noise in Y switch section  111 . Therefore, the effect of coupling noise on LIO line LIO 1  is reduced by one half as a whole. 
         [0076]    States  5 ,  12 ,  14  are similar to state  3 . In states  5 ,  12 ,  14 , the effect of coupling noise on an inner LIO line is reduced by one half as a whole. 
         [0077]    Consequently, it can be seen from  FIG. 9  that the effect of coupling noise imposed on the two inner LIO lines from LIO lines adjacent thereto are reduced by one half. 
         [0078]    In the table shown in  FIG. 9 , the coupling noise on the two inner LIO lines is maximum in state  6  and state  11 . Comparison between the table shown in  FIG. 6  and the table shown in  FIG. 9  indicates that the effect of coupling noise is reduced according to the first exemplary embodiment. 
         [0079]    According to the first exemplary embodiment, since two adjacent LIO lines are twisted in electrically insulated relation to each other in an SWC, an inner LIO line is positioned between LIO lines that are kept at potentials which are in opposite phase to a potential that is applied to the inner LIO line and is subject to noise from the LIO lines on the opposite sides thereof in SAMPs on both sides of the SWC, but is subject to noise from only one of the LIO lines on the opposite sides in the other SAMP. 
         [0080]    Stated otherwise, since two adjacent local signal lines are positionally switched around alternately at predetermined intervals, even if one of the local signal lines is subject to coupling noise from other local signal lines in a zone, it is subject to reduced coupling noise in another zone. Therefore, when data are read from memory elements, the data are subject to reduced coupling noise between the LIO lines, and hence the data read time required to read the data is prevented from increasing. 
         [0081]    If four LIO lines are grouped into two pairs of LIO lines including two adjacent LIO lines that are twisted, and signals that are transmitted through one of the pairs of LIO lines are in opposite phase to each other and signals that are transmitted through the other pair of LIO lines are in phase with each other, then coupling noise generated between the pair of LIO lines whose signals are in opposite phase to each other is reduced by one half. 
         [0082]    As shown in  FIG. 11 , a single LIO line may be twisted once as closely to its central portion as possible. In view of the total amount of coupling noise and increase in the contact resistance of the twisted portion of the LIO line, it is not necessary to twist two LIO lines at each SWC. A single LIO line that is twisted once as closely to its central portion as possible is effective for reducing coupling noise between adjacent LIO lines. 
       Second Exemplary Embodiment 
       [0083]    A semiconductor device according to a second exemplary embodiment of the present invention incorporates a shield line for protection against noise between LIO lines. 
         [0084]    The semiconductor device according to the second exemplary embodiment will be described below.  FIG. 12  is a schematic diagram showing a configurational example of the layout of Y switch sections of a sense amplifier section of the semiconductor device according to the second exemplary embodiment. In the second exemplary embodiment, the configuration of Y switch sections connected to true memory elements and the layout of LIO lines with respect thereto will be described above. The configuration of Y switch sections connected to bar memory elements and the layout of LIO lines with respect thereto are similar and will not be described in detail below. 
         [0085]    According to the present exemplary embodiment, Y switch is section  120  shown in  FIG. 12  is included instead of Y switch section  28   a  in the sense amplifier section shown in  FIG. 3 , and Y switch section  121  shown in  FIG. 12  is included instead of Y switch section  281  in the sense amplifier section shown in  FIG. 3 . According to the present exemplary embodiment, furthermore, four LIO lines extending through Y switch section  120  and Y switch section  121  are grouped into a pair of two upper LIO lines LIO 0 T, LIO 2 T and a pair of two lower LIO lines LIO 1 T, LIO 3 T, and shield line  310  is disposed between these pairs of LIO lines. Shield line  310  is formed of the same layer as the four LIO lines, and is connected to a power supply potential or a ground potential. 
         [0086]    LIO line LIO 2 T is protected against noise due to a potential on LIO line LIO 1 T by shield line  310 , and hence is subject to only noise from LIO line LIO 0 T. LIO line LIO 1 T is protected against noise due to a potential on LIO line LIO 2 T by shield line  310 , and hence is subject to only noise from LIO line LIO 3 T. 
         [0087]    According to the present exemplary embodiment, inasmuch as each of the two inner LIO lines is subject to only noise from an LIO line on one side thereof, the effect of noise on the LIO lines is reduced. Since the shield line is formed of the same layer as the four LIO lines, the semiconductor device can be fabricated without the need of additional fabrication steps. 
         [0088]    According to the present exemplary embodiment, the effect of coupling noise between LIO lines is reduced. As a result, a delay in transition due to the effect of coupling noise is reduced, preventing the data read time from increasing. 
         [0089]    Semiconductor memory devices having a plurality of memory is cell blocks have been described in the above exemplary embodiments. However, the present invention is also applicable to system LSI (Large Scale Integration) circuits including logic circuits as well as memory devices. 
         [0090]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.