Abstract:
A cyclic analog to digital converter (ADC) circuit operates to convert an analog input voltage into a digital output word. The ADC circuit includes an amplifier and capacitors configured as an integrator.

Description:
FIELD 
   The present invention relates generally to electronic circuits, and more specifically to analog to digital converter circuits. 
   BACKGROUND 
   Analog to digital converter (ADC) circuits convert analog voltages into digital words. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a single-ended analog to digital converter circuit; 
       FIG. 2  shows a differential analog to digital converter circuit; 
       FIG. 3  shows a flowchart in accordance with various embodiments of the present invention; and 
       FIG. 4  shows a system diagram in accordance with various embodiments of the present invention. 
   

   DESCRIPTION OF EMBODIMENTS 
   In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views. 
     FIG. 1  shows an analog to digital converter (ADC) circuit. ADC circuit  100  includes operational amplifier (opamp)  120 , comparator  190 , and capacitors  112  and  124 . ADC circuit  100  also includes switches  106 ,  108 ,  110 ,  114 ,  116 ,  126 ,  128 ,  132 ,  172 , and  174 . Switches  126 ,  128 ,  172 , and  174  are controlled by a reset signal shown as RST in  FIG. 1 . Further, switches  114  and  132  (the “P 1  switches”) are controlled by a first signal shown as P 1 , and switches  110  and  116  (the “P 2  switches”) are controlled by a second signal shown as P 2 . 
   The switches shown in  FIG. 1  represent switching elements that may be implemented using any suitable circuit element(s). For example, in some embodiments, one or more switches are implemented using isolated gate transistors such as metal oxide semiconductor field effect transistors (MOSFET). Further, in some embodiments, complementary MOSFETs are coupled in parallel to form pass gates. For example, an n-channel MOSFET may be coupled in parallel with a p-channel MOSFET as a pass gate to implement one or more switches in  FIG. 1 . 
   ADC  100  receives an analog voltage V IN  and produces a digital output word D OUT . D OUT  may be any number of bits long. V IN  may be any voltage value that falls between two reference voltages, shown as +V REF  and −V REF  in  FIG. 1 . 
   In operation, ADC  100  is reset, the input voltage V IN  is sampled, and then the P 1  and P 2  switches are alternately closed to produce a digital output word D OUT  on node  192 . ADC  100  is reset by asserting the RST signal to close switches  126  and  172 , and open switches  128  and  174 . In some embodiments, the P 1  switches and P 2  switches are also closed during a reset of ADC  100 . With switches  172  and  132  closed, the input voltage V IN  is sampled by capacitor  112 . After a reset, RST is de-asserted for the remainder of the conversion of the input voltage V IN  to a digital output word D OUT . When RST is de-asserted, switch  128  closes and switch  126  opens, to form a feedback circuit that includes capacitor  124  coupled between node  180  and input node  119 . Further, with RST de-asserted, switch  172  opens and switch  174  closes to remove the input voltage V IN  from the input. 
   After ADC  100  is reset as described in the above paragraph, the conversion process is started. During the conversion process, output bits are created on D OUT  most significant bit (MSB) first, and for each output bit, signals P 1  and P 2  are alternately asserted. The time period during which P 1  is asserted is referred to herein as “phase one” for a particular output bit, and the time period during which P 2  is asserted is referred to herein as “phase two” for the output bit. 
   In some embodiments, phases one and two do not overlap. For example, the switches that are closed during phase one are opened prior to the phase two switches closing during phase two. Likewise, the phase two switches are opened prior to the phase one switches closing. In some embodiments, P 1  and P 2  are opposite phases of a clock signal. 
   During phase one, switch  114  is closed to couple node  113  to a reference potential, and switch  132  is closed to provide a feedback path between node  180  and node  170 . During phase two, a positive or negative reference voltage (V REF ) is conditionally applied to the input capacitor  112  based on the value of the current output bit. Each output bit is used to control the application of either +V REF  or −V REF  to capacitor  112 . For example, when the current output bit is a “0,” switch  106  is closed and +V REF  is applied to the input capacitor  112 , and when the current output bit is a “1,” switch  108  is closed and −V REF  is applied to input capacitor  112 . In embodiments represented by  FIG. 1 , switches  106  and  108  represent an input switch network that is responsive to the digital output word. 
   During phase two, switch  116  is also closed, forming an integrating amplifier with input capacitor  112  having a capacitance C, opamp  120 , and feedback capacitor  124  having a capacitance of C. The change in voltage on node  170  is integrated, and the output voltage is changed by the change in the voltage on node  170 . This process is successively repeated until all output bits have been processed. 
   Comparator  190  generates an output bit by comparing a residue voltage V RES  on node  180  to a reference potential. The residue voltage on node  180  is generated as follows:
 
 V   RES ( n )= V   RES ( n− 1)+ V   RES ( n− 1)− b ( n ) V   REF ,  (1)
 
   where b(n)=sign[V RES (n)]. 
   In equation (1) above, the first term is realized with the integrator formed by opamp  120  and capacitors  112  and  124 , the second term is realized by sampling the output of opamp  120  on P 1 , and the third term is realized by applying either +V REF  or −V REF  to the sampling capacitor on the settling phase of P 2  depending on the result of the comparison in the previous cycle. 
     FIG. 2  shows a differential analog to digital converter. ADC  200  includes differential opamp  220 , capacitors  230 ,  236 ,  240 , and  246 , and switches  210 ,  212 ,  214 ,  216 ,  218 ,  222 ,  224 ,  232 ,  234 ,  242 ,  244 ,  282 ,  284 ,  286 , and  288 . Switches  232 ,  234 ,  242 ,  244 ,  282 ,  284 ,  286 , and  288  are reset switches as described above with reference to  FIG. 1 . Switches  212 ,  214 ,  216 , and  218  are P 1  switches, and switches  222  and  224  are P 2  switches. 
   The operation of ADC  200  is similar to the operation of ADC  100  ( FIG. 1 ). For example, during reset, switches  234 ,  244 ,  282 , and  286  are open, switches  232 ,  242 ,  284 , and  288  are closed, P 1  switches are closed, and P 2  switches are closed. Also during reset, +V IN  is sampled on capacitor  236  and −V IN  is sampled on capacitor  246 . After a reset, RST is de-asserted for the remainder of the conversion of the input voltage V IN  to a digital output word D OUT . When RST is de-asserted, switches  234  and  244  close and switches  232  and  242  open to form feedback circuits that include capacitors  230  and  240 . Further, with RST de-asserted, switches  284  and  288  open and switches  282  and  286  close to remove the input voltage V IN  from the input. After ADC  200  is reset, P 1  and P 2  alternate for each bit in the digital output word. 
   During P 1 , the output of opamp  220  is fed back with a unity gain by feeding each output of opamp  220  to an input capacitor. For example, the positive output of opamp  220  is fed back to capacitor  236 , and the negative output of opamp  220  is fed back to capacitor  246 . Also during P 1 , switches  216  and  218  close to remove any charge from nodes  237  and  247 . 
   During P 2 , switches  222  and  224  are closed to couple capacitors  236  and  246  to the input nodes of opamp  220 . In this configuration, opamp  220  and capacitors  236 ,  246 ,  230 , and  240  form a differential integrator, and the output voltage settles to equal the change in voltage on nodes  237  and  247  when switches  222  and  224  close. 
   Switches  210  combine the functionality of switches  106 ,  108 , and  110  ( FIG. 1 ). For example, two of the four switches  210  close during P 2  based on the value of the current output bit. Two switches are closed when b(n) is true, and two switches are closed when b(n) is false, where b( ) is the output bit value and n is the subscript of the current output bit. As shown in  FIG. 2 , +V REF  is applied to capacitors  236  and  246  when the current output bit is a “0,” and −V REF  is applied to capacitors  236  and  246  when the current output bit is a “1.” 
   In some embodiments, switches  210  represent an input switch network that is responsive to a digital output word. In other embodiments, switches  210  represent two input switch networks. For example, two switches form a first input switch network to provide a reference voltage to capacitor  236 , and two switches form a second input switch network to provide a reference voltage to capacitor  246 . 
   Additional output bits are generated by continuing to alternately assert P 1  and P 2 . Each time P 1  is asserted, the output of opamp  220  is fed back to capacitors  236  and  246 , and each time P 2  is asserted, an output bit is generated and either +V REF  or −V REF  is applied to capacitors  236  and  246 . 
     FIG. 3  shows a flowchart in accordance with various embodiments of the present invention. In some embodiments, method  300  is performed by a single-ended cyclic ADC circuit such as ADC  100  ( FIG. 1 ). In other embodiments, method  300  is performed by a differential ADC circuit such as ADC  200  ( FIG. 2 ). In some embodiments, method  300 , or portions thereof, is performed by an integrated circuit, embodiments of which are shown in the various figures. Method  300  is not limited by the particular type of apparatus or software element performing the method. The various actions in method  300  may be performed in the order presented, or may be performed in a different order. Further, in some embodiments, some actions listed in  FIG. 3  are omitted from method  300 . 
   Method  300  begins at  310  where an input voltage is sampled on an input capacitor of a cyclic analog to digital converter. In some embodiments, this may correspond to V IN  being sampled on capacitor  112  ( FIG. 1 ) during a reset of ADC  100 . In other embodiments, this may correspond to +V IN  being sampled on capacitor  246  and −V IN  being sampled on capacitor  236  ( FIG. 2 ) during a reset of ADC  200 . 
   At  320 , a voltage change on the input capacitor is integrated to modify a residue signal. This may correspond to opamp  120  ( FIG. 1 ) or opamp  220  ( FIG. 2 ) integrating the voltage change on the input capacitors to modify the opamp output voltage during P 2 . At  330 , the residue signal is fed back to the input capacitor during P 1 . At  340 , the residue signal is passed to a comparator to produce a digital output signal. For example, comparator  190  ( FIG. 1 ) produces a digital output bit, and comparator  290  ( FIG. 1 ) produces a digital output bit. 
   At  350 , a first reference voltage is applied to the input capacitor when the digital output signal has a first value, and a second reference voltage is applied to the input capacitor when the digital output signal has a second value. For example, the output of comparator  190  ( FIG. 1 ) controls switches  106  and  108 , and the output of comparator  290  ( FIG. 2 ) controls switches  210 . 
   In some embodiments, acts of blocks  320 ,  330 ,  340 , and  350  are successively repeated for each additional output bit. For example, if an ADC circuit is to produce a nine bit output word, then the blocks may be repeated eight times. When a new input voltage is to be converted to a digital word, method  300  begins again at  310 . 
     FIG. 4  shows a system diagram in accordance with various embodiments of the present invention.  FIG. 4  shows system  400  including integrated circuit  410 , baseband circuit  420 , radio frequency (RF) circuit  440 , and antennas  450 . In operation, system  400  processes a signal to be transmitted using baseband circuit  420 , further processes it using RF circuit  440 , and transmits it using antennas  450 . System  400  may also receive signals using antennas  450  and RF circuit  440 , and process the received signals using baseband circuit  420  and integrated circuit  410 . Antennas  450  may include directional antennas or omni-directional antennas. As used herein, the term omni-directional antenna refers to any antenna having a substantially uniform pattern in at least one plane. For example, in some embodiments, one or more of antennas  450  may be an omni-directional antenna such as a dipole antenna, or a quarter wave antenna. Also for example, in some embodiments, one or more of antennas  450  may be a directional antenna such as a parabolic dish antenna or a Yagi antenna. 
   Integrated circuit  410  includes port circuit  412  and ADC circuit  414 . Analog to digital converter (ADC) circuit  414  may be any of the ADC circuit embodiments described herein. For example, in some embodiments, ADC circuit  414  includes one or more of ADC circuit  100  ( FIG. 1 ), or one or more of ADC circuit  200  ( FIG. 2 ). 
   Integrated circuit  410  may be any type of integrated circuit capable of including one or more port circuits with an ADC circuit as shown. For example, integrated circuit  410  can be a processor such as a microprocessor, a digital signal processor, a microcontroller, or the like. Integrated circuit  410  can also be an integrated circuit other than a processor such as an application-specific integrated circuit (ASIC), a communications device, a memory controller, or a memory such as a dynamic random access memory (DRAM). For ease of illustration, portions of integrated circuit  410  are not shown. The integrated circuit may include much more circuitry than illustrated in  FIG. 4  without departing from the scope of the present invention. 
   In some embodiments, ADC  414  is part of a built-in self test circuit within port circuit  412  that validates link performance by capturing transmission line waveforms, eye diagrams, and noise and jitter distributions. ADC  414  may provide calibration of several functional blocks within port circuit  412  to overcome the effects of non-linearity, offset and gain error. For example, port circuit  412  may include a comparator (not shown) with a digitally programmable offset voltage. In some embodiments, ADC  412  may be utilized during a built-in self test and calibration of the comparator. 
   Baseband circuit  420  may be any type of circuit to provide digital baseband processing in a communications system. In some embodiments, baseband circuit  420  includes a processor such as a digital signal processor (DSP), and in other embodiments, baseband circuit  420  is implemented as a system on a chip (SOC) that includes many functional blocks. In some embodiments, baseband circuit  420  provides digital data to RF circuit  440 . 
   Radio frequency circuit  440  receives data from baseband circuit  420  and performs additional processing. For example, in some embodiments, RF circuit  440  performs modulation, filtering, frequency up-conversion, amplification, or the like. Further, in some embodiments, RF circuit also includes a receiver, and performs low noise amplification (LNA), frequency down-conversion, demodulation, or other functions. 
   Systems represented by the various foregoing figures can be any type of system that includes one more antennas. Examples of represented systems include computers with wireless functionality (e.g., desktops, laptops, handhelds, servers, tablets, web appliances, routers, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like. Many other system uses for ADC circuits exist. For example, ADC circuits may be used in systems without one or more antennas. 
   Analog to digital converter circuits, port circuits, integrated circuits, and other embodiments of the present invention can be implemented in many ways. In some embodiments, they are implemented in integrated circuits and systems. In some embodiments, design descriptions of the various embodiments of the present invention are included in libraries that enable designers to include them in custom or semi-custom designs. For example, any of the disclosed embodiments can be implemented in a synthesizable hardware design language, such as VHDL or Verilog, and distributed to designers for inclusion in standard cell designs, gate arrays, or the like. Likewise, any embodiment of the present invention can also be represented as a hard macro targeted to a specific manufacturing process. 
   Although the present invention has been described in conjunction with certain embodiments, it is to be understood that modifications and variations may be resorted to without departing from the spirit and scope of the invention as those skilled in the art readily understand. Such modifications and variations are considered to be within the scope of the invention and the appended claims.