Abstract:
An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

Description:
BACKGROUND  
         [0001]    Advances in semiconductor manufacturing technologies have allowed circuit designers to continually improve the clock performance of high-speed logic devices including, but not limited to, microprocessors. Thus, microprocessor core clock speeds have continued to increase. However, partly due to the difficulty of increasing data bus speeds, systems having a plurality high speed logic devices interconnected through a data bus have not experienced the same degree of improved performance.  
           [0002]    For purposes of discussion, FIG. 1 illustrates a system  10  comprising a data bus  12  electrically coupled to a plurality of high speed logic devices  14 ,  17 ,  19 . Each logic device  14 ,  17 ,  19  is electrically coupled to the data bus  12  through an exemplary bus interface circuit  16 . In order to coordinate the transfer of data between each of the logic devices  14 ,  17 ,  19 , the system  10  may use a common-clock timing scheme and a source synchronous timing scheme, both of which are well known in the art. Typically, the common-clock timing scheme is the critical timing path, slowing the speed of data transfers between logic devices  14 ,  17 ,  19  and, therefore, the overall speed of the system  10 .  
           [0003]    The exemplary interface circuit  16  comprises a driver  20  and a receiver  22  electrically coupled to the data bus  12 . The driver  20  is configured to receive a T_DATA signal from its corresponding logic device  14 ,  17 ,  19  and to transmit the T_DATA signal to the data bus  12 . Typically, the T_DATA signal is latched to the driver  20  through a register  24  controlled by a clock signal BCK. The driver  20  may also be configured to transmit the T_DATA signal to the data bus  20  only upon receiving an ENABLE signal. Like the T_DATA signal, the ENABLE signal may be latched to the driver  20  through a register  26  controlled by the clock signal BCK. As used herein, the term “driving path” refers to the driver  20  and the registers  24 ,  26 , collectively or individually. Similarly, the each of the registers  24  and  26  may be referred to as a “driving path register”. The receiver  22  is configured to receive an R_DATA signal from the data bus  12  and to transmit the R_DATA signal to a register  28 . The receiving path register  28  is also configured to pass the R_DATA signal to its corresponding logic device  14 ,  17 ,  19 . As used herein, the term “receiving path” refers to the receiver  22  and the register  28 , collectively or individually. Similarly the register  28  may be referred to as a “receiving path register”.  
           [0004]    In a common-clock timing scheme, a single clock is shared by the driving and receiving elements coupled to a data bus. As shown in FIG. 1, each exemplary interface circuit  16  employs a common-clock timing scheme wherein the driving path registers  24 ,  26  and the receiving path registers  28  are controlled by the same clock signal BCK. Sharing the clock signal BCK between the driving path registers  24 ,  26  and the receiving path registers  28  places a theoretical limit on the maximum frequency at which the common-clock data bus  12  can operate. The limitation stems from the total delay introduced between a driving path and a receiving path of the interface circuits  16 .  
           [0005]    To illustrate the maximum frequency limitation, FIG. 2 shows a timing diagram with two clock signals, BCK (slower) and BCK (faster), having different periods. FIG. 2 also shows a time line illustrating the times when a bit of data of the T_DATA signal is driven by a driver  20  and received by a receiver  22  in relation to the two clock signals. The elapsed time between the time when the bit is driven and the time when it is received is referred to herein as the “total delay” or “total delay time” of the signal. The driving path registers  24 ,  26  are configured to pass the a bit to the driver  20  upon a first positive transition of the clock signal BCK (slower) and the receiving path register  28  is configured to latch in the bit from the receiver  22  upon a second positive transition of the clock signal BCK (slower). To ensure correct latching, the receiver  22  may be configured with setup and hold requirements that define the minimum times that the received bit must be held in the receiving path register  28  before and after a positive transition of the clock signal BCK (slower).  
           [0006]    One skilled in the art will recognize that the bit driven at the first positive transition of the clock signal BCK (slower) must be received at the receiver before the second transition of the clock signal BCK (slower) in order to be latched into the receiving path register  28  correctly. Otherwise, a subsequent bit may be received at the receiver  22  before the bit is latched into the receiving path register  28  or a previous bit may be latched into the receiving path register  28  more than once. As used herein, the term “race” refers to the condition wherein a first bit is received at the receiver  22  but is not latched into the receiving path register  28  before a second bit is received at the receiver  22 . Thus, the total delay must remain less than the delay of one cycle of the clock signal BCK (slower). As shown in the example in FIG. 2, this requirement is met. However, if the registers  24 ,  26 ,  28  of FIG. 1 are controlled by the higher frequency clock signal BCK (faster), the total delay may be greater than the delay of one cycle of the clock signal BCK (faster), causing race or other timing problems. Therefore, the maximum frequency at which the common-clock data bus  12  can operate is limited to clock signals having periods greater than the total delay.  
           [0007]    Referring again to FIG. 1, to design a common-clock data bus  12 , each factor contributing to the total delay must be accounted for to determine a common-clock timing budget, or minimum allowable cycle for the clock signal BCK. The total delay of the T_DATA signal comprises the sum of the delays introduced by each element of the system through which the T_DATA signal passes. Thus, a T_DATA signal passing through fewer system elements will have less total delay than a T_DATA signal passing through more system elements. For example, the total delay of a T_DATA signal communicated between the driver  20  and the receiver  22  of the same logic device, such as logic device  14 , may include delays introduced by the driving path registers  24 ,  26 , the driver  20 , the receiver  22 , and the receiving path register  28  of logic device  14 . However, the total delay of a T_DATA signal communicated between logic device  14  and logic device  17  may include delays introduced by the driving path registers  24 ,  26  and the driver  20  of logic device  14 , the packaging (not shown) of logic device  14 , the length of printed circuit board traces (not shown) of the data bus  12 , the packaging (not shown) of logic device  17 , and the receiver  22  and receiving path register  28  of logic device  17 . Further, due to the delay introduced by the length of the printed circuit board traces of the data bus  12 , logic devices  14 ,  17 ,  19  that are the farthest away from each other on the data bus  12  will experience the greatest delay when communicating a T_DATA signal between each other.  
           [0008]    Once the common-clock timing budget is determined, it may be desirable to increase the maximum frequency at which the common-clock data bus  12  can operate by decreasing the total delay time along any given communication path. Thus, it may be advantageous to shorten the length of printed circuit board traces in the data bus  12  or to shorten packaging leads. However, the amount of delay eliminated from such measures may be minimal. It may also be advantageous to reduce the propagation delays of the registers  24 ,  26 ,  28 , the drivers  20 , and the receivers  22  in FIG. 1 by decreasing their switching times (e.g., reducing the finite delay between the application of an input pulse and an output response). However, reducing propagation delays may create noise problems due to the high frequencies associated with slew rates.  
         SUMMARY  
         [0009]    The present disclosure relates to increasing the speed of a common-clock data bus. An interface circuit configured to drive and receive data on a data bus according to an exemplary embodiment includes a common-clock provided to a driving path and a receiving path of the interface circuit and time borrowing circuitry electrically coupled to the receiving path. The time borrowing circuitry is configured to dynamically delay the common-clock before it is provided to the receiving path. In another embodiment, the time borrowing circuitry is configured to selectively provide the common-clock or the dynamically delayed common-clock to the receiving path. The time borrowing circuitry may be configured to provide the common clock, rather than the dynamically delayed common-clock, to the receiving path when the driving path is driving data onto the data bus. In yet another embodiment, the time borrowing circuitry is configured to selectively switch between providing the common-clock or the dynamically delayed common-clock only at select time intervals.  
           [0010]    In another embodiment, the interface circuit comprises at least one driving path register coupled to a driver, a receiving path register coupled to a receiver, and a delay line coupled between a common-clock signal and a clock input of the receiving path register. The interface circuit may further comprise a multiplexer having an output coupled to the clock input of the receiving path register, the multiplexer configured to switch its output between the common-clock and the output of the delay line. The interface may further comprise a NOR gate electrically coupled to the common-clock and the output of the delay line and a latch electrically coupled to the output of the NOR gate. The NOR gate and latch may be configured to provide a signal to the multiplexer only when the common-clock and the output of the delay line are both at a low logic level.  
           [0011]    A logic device according to another embodiment comprises an interface circuit including a driving path, a receiving path, and time borrowing circuitry. The time borrowing circuitry may be configured to dynamically delay a common-clock signal provided to the receiving path. A system according to another embodiment comprises a plurality of logic devices electrically coupled to a data bus, each logic device comprising a driving path, a receiving path, and a time borrowing circuitry. The time borrowing circuitry may be configured to provide a common-clock to the receiving path when a driving path of an external device is driving and to provide a dynamically delayed version of the common-clock signal to the receiving path when the driving path within the same logic device is driving.  
           [0012]    Other features and advantages will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 is a schematic diagram of a system employing a plurality of exemplary interface circuits;  
         [0014]    [0014]FIG. 2 is a timing diagram showing two clock signals in relation to a total delay time corresponding to the system of FIG. 1;  
         [0015]    [0015]FIG. 3 is a block diagram of the interface circuit of FIG. 1 electrically coupled to time borrowing circuitry, according to an embodiment of the present invention;  
         [0016]    [0016]FIG. 4 is a schematic diagram of the interface circuit of FIG. 1 electrically coupled to time borrowing circuitry comprising a delay line configured to dynamically shift a clock signal, according to an embodiment of the present invention;  
         [0017]    [0017]FIG. 5 is a timing diagram of various signals described in relation to FIG. 4;  
         [0018]    [0018]FIG. 6 is a block diagram of a logic device comprising an interface circuit having time borrowing circuitry, according to an embodiment of the present invention; and  
         [0019]    [0019]FIG. 7 is a block diagram of a computer system comprising a plurality of logic devices interconnected through a data bus, each logic device comprising an interface circuit having time borrowing circuitry, according to an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0020]    [0020]FIG. 3 shows a block diagram of an improved device interface circuit  30  according to one embodiment of the present invention. The device interface circuit  30  comprises an exemplary interface circuit  21 , electrically coupled to time borrowing circuitry  32 . The time borrowing circuitry  32  is configured to receive a clock signal BCK, borrow time from the clock signal BCK to create a receiver clock signal BCK_R, and output the receiver clock signal BCK_R to the interface circuit  21 . As discussed in greater detail below, the receiver clock signal BCK_R is configured to have a first positive transition corresponding to a first positive transition of the clock signal BCK and to have a second positive transition after a second positive transition of the clock signal BCK. In other words, the period of the receiver clock signal BCK_R is configured to end after the period of the clock signal BCK ends. The time difference between the end of the clock signal BCK period and the receiver clock signal BCK_R period is referred to as “time borrowed” from the clock signal BCK domain timing. The time borrowing circuitry  32  may be configured to create the time difference by dynamically delaying the clock signal BCK and outputting the delayed signal as the receiver clock signal BCK_R.  
         [0021]    The clock signal BCK may be an inner-device bus clock, which typically has large timing margins. As used herein, a “timing margin” is the difference between the common-clock timing budget and the total delay. Therefore, it is possible to borrow time from the inner-device bus clock domain timing without reducing the integrity of the overall common-clock timing scheme.  
         [0022]    The time borrowing circuitry  32  is configured to pass the receiver clock signal BCK_R to the clock input of a receiver path register (not shown), such as register  28  shown in FIG. 1. As will be discussed in greater detail below, the time borrowed allows the maximum frequency at which a common-clock data bus  12  can operate to be increased by allowing the time period of the clock signal BCK to be reduced to less than the common-clock timing budget. The time borrowing circuitry  32  may also be configured to pass a receiver clock signal BCK_R that is substantially identical to the clock signal BCK upon receipt of the ENABLE signal. Thus, the time borrowing circuitry  32  may be configured to selectively disable the time borrowing.  
         [0023]    [0023]FIG. 4 shows a schematic diagram of an improved device interface circuit  40  according to another embodiment of the present invention. The device interface circuit  40  comprises an exemplary interface circuit  21 , such as the interface circuit  21  shown in FIG. 3, electrically coupled to time borrowing circuitry  50 . The time borrowing circuitry  50  is configured to receive a clock signal BCK, borrow time from the clock signal BCK using dynamic clock shift to create a receiver clock signal BCK_R, and output the receiver clock signal BCK_R to the interface circuit  21 . The time borrowing circuitry  50  comprises a delay line  42  electrically coupled to a multiplexer  44  and a NOR gate  48 . The output of the NOR gate  48  is electrically coupled to the clock input of a latch  46  and the output of the latch is electrically coupled to the select line of the multiplexer  44 . An ENABLE signal is electrically coupled to an input of the latch  46  and the clock signal BCK is electrically coupled to the respective inputs of the NOR gate  48 , the delay line  42 , and the multiplexer  44 .  
         [0024]    Referring to FIGS. 4 and 5, a delay element or other appropriate delay circuit such as delay line  42  is configured to receive the clock signal BCK and to output a delayed clock signal BCK_D. When the multiplexer  44  receives a low logic level signal SEL from the latch  46 , the delayed clock signal BCK_D is passed to the clock input of the receiving path register  28  as receiver clock signal BCK_R. As illustrated in the timing diagram shown in FIG. 5, the amount of time by which the clock signal BCK is delayed by the delay line  42  is equal to the amount of time borrowed. As discussed previously, the receiving path register  28  is configured to latch a bit from the receiver  22  when the receiver clock signal BCK_R undergoes a positive transition. Thus, even if the total delay of the bit in arriving at the receiver  22  is more than the period of the clock signal BCK by an amount less than the time borrowed, the positive transition of the receiver clock signal BCK will latch the bit into the receiving path register  28 . Therefore, the common-clock timing budget may be increased from one clock signal BCK period to one clock signal BCK period plus the amount of time borrowed, allowing the maximum frequency at which the common-clock data bus  12  to be increased.  
         [0025]    To avoid race conditions, it may be advantageous to selectively disable the time borrowing. The receiver  22  may receive a T_DATA signal from the driver  20  that is internal to the same interface circuit  21  or from a driver (not shown) that is externally coupled to the receiver through the data bus  12 . This is especially true for a receiver  22  located within a front-side bus interface circuit  21 . As discussed previously, the total delay of a T_DATA signal communicated between a driver  20  and a receiver  22  of the same logic device, such as logic device  14  shown in FIG. 1, may be much smaller than the total delay of a T_DATA signal communicated between two different logic devices, such as between logic devices  14  and  19  shown in FIG. 1. If the total delay of the T_DATA signal communicated between the driver  20  and receiver  22  of the same interface circuit  21  is less than the time borrowed, a race condition will occur. For example, the driver  20  may be configured to drive a first bit at time zero and a second bit at time 1 BCK, as shown in FIG. 5. However, if the total delay is less than the time borrowed, the second bit will arrive at the receiver  22  before the first bit is latched into the receiving path register  28 . Therefore, it is advantageous to disable the time borrowing when the receiver  22  is receiving a T_DATA signal from an internal driver  20 .  
         [0026]    To prevent race, the time borrowing circuitry  50  is configured to disable the time borrowing using the ENABLE signal. When the driver  20  is driving, the ENABLE signal is at a high logic level, which causes the clock signal BCK to be passed through the multiplexer  44  as receiver clock signal BCK_R. Therefore, the receiver clock signal BCK_R will be identical to the clock signal BCK and no time borrowing will occur.  
         [0027]    The latch  46  and the NOR gate  48  are configured to prevent glitches on the receiver clock signal BCK_R when the ENABLE signal undergoes a positive transition too early, causing the multiplexer  44  to switch from the delayed clock signal BCK_D to the clock signal BCK. To prevent glitches, the multiplexer  44  is prevented from switching between its inputs until the delayed clock signal BCK_D and the clock signal BCK are both at low logic levels. When the delayed clock signal BCK_D and the clock signal BCK are both at low logic levels, the ENA_PASS signal at the output of the NOR gate  48  transitions to a high logic level. The ENA_PASS signal at a high logic level causes the latch  46  to latch the ENABLE signal at its input to the SEL signal at its output. Therefore, glitches on the receiver clock signal BCK_R are avoided by preventing the multiplexer  44  from switching its output from the delayed clock signal BCK_D to the clock signal BCK before both input signals are at a low logic level.  
         [0028]    [0028]FIG. 6 illustrates a block diagram of a logic device  70  employing a device interface circuit  72 . Device interface circuit  72  comprises time borrowing circuitry  74 , such as the time borrowing circuitry  50  shown in FIG. 4. Logic device  70  may be used to produce the signals described in connection with FIGS. 3 through 5. Logic device  70  may comprise, by way of example only and not by limitation, a high speed digital processor.  
         [0029]    [0029]FIG. 7 illustrates a block diagram of a computer system  78  according to an embodiment of the present invention. Computer system  78  comprises computer circuitry  80 , data storage devices  84 , output devices  86 , and input devices  88 . Computer circuitry  80  typically performs computer functions such as executing software to perform desired calculations and tasks. Computer circuitry  80  comprises a plurality of logic devices  70  (three shown), such as the logic device  70  shown in FIG. 6, coupled to a data bus  82 . Computer circuitry  80  may include additional elements (not shown) such as, for example, those used in configuring, controlling, or otherwise interacting with the plurality of logic devices and may further include a memory device (not shown) and one or more additional buses (not shown). Although not shown, one or more of the data storage devices  84 , output devices  86 , and input devices  88  may be electrically coupled to the data bus  82 .  
         [0030]    The data storage devices  84  may include, by way of example only, drives that accept hard and floppy discs, tape cassettes, CD-ROM, or DVD-ROM. The output devices may include, by way of example only, a printer or a video display device. The input devices may include, by way of example only, an Internet or other network connection, a mouse, a keypad, or any other device that allows an operator to enter data into the computer circuitry  80 .  
         [0031]    While the present invention has been disclosed in detail, those of ordinary skill in the art will recognize and appreciate that the invention is not so limited. Those of ordinary skill in the art will recognize and appreciate that many additions, deletions and modifications to the disclosed embodiment and its variations may be implemented without departing from the scope of the invention, which is limited only by the appended claims and their legal equivalents.