Abstract:
In a method for synchronization of a mobile radio receiver to a base station, in which a verification step or a plurality of verification steps is or are also carried out in addition to the synchronization steps and one or more identification step or steps which may be present, at least one of the verification steps is carried out in parallel with a synchronization step and/or with an identification step.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a continuation of copending International Application No. PCT/DE03/02561 filed Jul. 30, 2003 which designates the United States, and claims priority to German application no. 102 41 692.3 filed Sep. 9, 2002. 
     
    
     TECHNICAL FIELD OF THE INVENTION  
       [0002]     The present invention relates to a method for synchronization of a mobile radio receiver to a base station and to a corresponding device.  
       DESCRIPTION OF RELATED ART AND BACKGROUND OF THE INVENTION  
       [0003]     When a mobile radio receiver is switched on or when it enters a new cell, it must be synchronized to this cell or to potential cells. In order to associate the received data with the correct time, the data strem is organized in time flames and time slots. A frame contains a specific number of slots, and each slot contains a specific number of bits (data and/or control information). In particular, these cells must first of all be recognized and identified with respect to their timings (flame and slot start) and their base station codes. So-called synchronization sequences are generally used for this purpose, which have either global characteristics (which are the same throughout the network) or local characteristics (which differ for different base stations).  
         [0004]     Synchronization of a third generation mobile radio receiver, such as UMTS, to a corresponding base station, that is to say time synchronization and identification of the cell code and scrambling code, is achieved by correlating the received signal with the complex-conjugate signal for the correspondingly transmitted synchronization code.  
         [0005]     Since the synchronization sequences generally cannot be received without interference (AWGN), there is only a certain probability of the receiver system being synchronized to a corresponding cell. This synchronization probability depends essentially not only on the signal-to-noise ratio but also on the time interval available for the synchronization procedure. However, user-relevant and/or system-relevant aspects generally result in a link to specific timing requirements. If a synchronization process comprises N step elements (in the case of UMTS, three successive step elements are carried out: slot synchronization→frame synchronization+code group identification→scrambling code identification), then the detection probability after a step element n depends on that of the step element n−1 (n=2, . . . , N).  
         [0006]     This results in two conclusions: 
        a) the step element n−1 should achieve a significantly higher detection probability than the step element n in order to result in an overall procedure with an efficient usefulness/complexity ratio,     b) detection errors/results in a step element should be recognized/evaluated in order to carry out the overall synchronization process with a predetermined detection probability in a minimum time.        
 
         [0009]     As has already been mentioned above, the synchronization procedure for a UMTS mobile radio receiver essentially comprises three step elements: 
        a) slot synchronization     b) flame synchronization and code group identification     c) scrambling code identification        
 
         [0013]      FIG. 2  illustrates a basic flowchart of one such conventional synchronization process for UMTS UEs.  
         [0014]     Steps a) and b) in particular require a relatively long time since, in order to increase the detection probability, the received signal must be evaluated (averaged) over a total of two or more slots or even two or more frames. In order to further increase the detection reliability of a synchronization unit such as this, verification steps are normally inserted after one or more of the individual step elements, as is illustrated in  FIG. 2 . These verification steps must also be carried out over a relatively large number of slots or frames in order to obtain an appropriately reliable indication of the synchronization status of the receiver. This therefore means that additional time is required in order to improve the detection or synchronization probability.  
         [0015]     As has already been mentioned above, the 3G system requirements result in specific time restrictions, so that only a specific number of slots or frames are available for a given synchronization task. The detection probability thus depends directly on this restriction. The minimum total detection time or total synchronization time is thus the sum of the slot synchronization time T slot , of the slot boundary verification time T veri-slot , of the frame synchronization time T frame , of the frame verification time T veri-frame  and of the scrambling code identification time T scr-id . On the assumption that the same time T is required for each step element, this results in a total time of T min-sync =5T.  
         [0016]     Methods for synchronization with intermediate verification are also referred to as multi-dwell detectors. In this context, reference should be made to the book: Peterson, Ziemer, Borth: Introduction to Spread Spectrum Communication, page 255.  
       SUMMARY OF THE INVENTION  
       [0017]     The invention is based on the object of providing a method for synchronization of a mobile radio receiver to a base station in which, as in the prior art, a verification step or a plurality of verification steps also are carried out in addition to the synchronization steps and one or more identification step or steps which may be present, which, however, is faster than the known methods of this generic type. A further object of the invention is to provide a device for synchronization of a mobile radio receiver to a base station, which device, as in the prior art, is designed such that it also carries out a verification step or a plurality of verification steps in addition to the synchronization steps and, possibly, one or more identification step or steps, and which, however, operates more quickly than known devices of this generic type.  
         [0018]     According to the invention, this object can be achieved by a method for synchronization of a mobile radio receiver to a base station, comprising the step of carrying out a verification step or a plurality of verification steps in addition to synchronization steps, which are carried out in a synchronization unit, and one or more identification step or steps which may be present, wherein at least one of the verification steps is carried out in parallel with a synchronization step and/or with an identification step in a verification unit which is provided specifically for this purpose.  
         [0019]     Frame synchronization can be carried out after slot synchronization, and the slot synchronization can be verified in parallel with the frame synchronization. Scrambling code identification can be carried out after frame synchronization, and the frame synchronization can be verified in parallel with the scrambling code identification.  
         [0020]     The object can also be achieved by a device for synchronization of a mobile radio receiver to a base station, comprising a synchronization unit for carrying out synchronization steps, wherein the device has a dedicated verification unit for carrying out verification steps in parallel.  
         [0021]     The device may comprise a slot synchronization unit, a slot boundary verification unit and a frame synchronization unit which are designed such that potential slot boundaries identified by the slot synchronization unit are in each case transmitted to the frame synchronization unit and to the slot boundary verification unit at the same time. The slot boundary verification unit can be a correlator. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     Exemplary embodiments of the invention will be explained in the following text with reference to figures, in which:  
         [0023]      FIG. 1  shows a schematic block diagram of one exemplary embodiment of a synchronization unit according to the invention;  
         [0024]      FIG. 2  shows, schematically, the procedure for one synchronization method which is known from the prior art;  
         [0025]      FIG. 3  shows a more detailed section of the block diagram shown in  FIG. 1 , relating to one exemplary embodiment of a slot boundary verification unit, and of the arrangement of its circuitry with respect to a frame synchronization unit;  
         [0026]      FIG. 4  shows a more detailed block diagram of a first exemplary embodiment of the frame synchronization unit shown in  FIG. 3 ;  
         [0027]      FIG. 5  shows a more detailed block diagram of a second exemplary embodiment of the frame synchronization unit shown in  FIG. 3 ;  
         [0028]      FIG. 6  shows a block diagram as an exemplary embodiment of a combined verification mode; and  
         [0029]     FIGS.  7 / 8  show a comparison of the detection results for slot synchronization without verification and with verification. 
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0030]      FIG. 1  shows, schematically and in the form of a block diagram, the basic functionality and architecture of one exemplary embodiment of a synchronization unit according to the invention. With this approach, the step elements which have already been mentioned of slot synchronization, frame synchronization and scrambling code identification can once again be described as separate block elements. In contrast to the procedure which is known from the prior art, however, no extra verification steps are inserted between the last-mentioned step elements and, instead, the verification steps are carried out in parallel with the respective synchronization step elements. As can be seen from  FIG. 1 , the status of the slot synchronization, for example, is checked in parallel with the frame synchronization. For this purpose, an additional verification unit which, for example, is formed by a simple correlator is operated synchronously with the frame synchronization unit (see  FIG. 3 ).  
         [0031]     “Synchronously” in this case means that only those potential slot boundaries which have been identified by means of slot synchronization were in each case transmitted at the same time to the frame synchronization unit and to the slot boundary verification unit, and are processed in parallel. In consequence, both the verification results for the corresponding slot boundaries and the frame synchronization results are available after only 2T. Reference should be made to the statements relating to this further above with regard to the definition of T.  
         [0032]     As is indicated in  FIG. 1 , the verification information obtained in this way can be introduced at a number of points in the overall synchronization process. Three options will be described as exemplary embodiments in the following text. This analysis is based on an implementation of the verification unit as shown in  FIG. 3 . In this case, M denotes a multiplier, ADD an adder, REG a register, SQR a squarer, Σ a summation point, and COMP a comparator. An implementation such as this allows coherent and incoherent accumulation of the correlation results, and allows the verification results to be handed over as hard or soft values ( FIG. 3 ). For the implementation of the hard values, the accumulated correlation result is compared with a threshold value THRES_V1. If the accumulated correlation result exceeds the value of THRES_V1, then, by way of example, a “1” is emitted for a positive verification of the corresponding slot boundary (the slot boundary found by the slot synchronization process is confirmed). Otherwise, an “0” is emitted as the verification result, and the slot boundary is not confirmed.  
         [0033]     Option I:  
         [0034]     The basic architecture for this approach is illustrated in  FIG. 4 .  
         [0035]     In this exemplary embodiment, the results of the slot boundary verification process are passed directly to the frame synchronization unit. The input data is subjected to “preprocessing” in the frame synchronization unit, and this is in each case carried out in parallel with the verification of the corresponding slot boundary. This “preprocessing” comprises the correlation of the received data with a so-called “z sequence” (see 3GPP TS 25.213) and the generation of a presequence which comprises 16 values per slot and is temporarily buffer-stored in a RAM (TEMP RAM). A presequence such as this can be generated for each slot boundary that is found by the slot synchronization process. When a slot boundary is confirmed by the verification unit, the corresponding presequence is passed to a postprocessing stage in the frame synchronization unit, and the postprocessing of the frame synchronization and code group identification is carried out for the corresponding slot boundary. Unconfirmed slot boundaries are rejected, that is to say no postprocessing is carried out for them. In this case, it should be noted that the postprocessing does not result in any additional time restriction since only the preprocessing is linked to the received data clock rate, while the postprocessing can be carried out at any desired processing clock rate.  
         [0036]     Option II:  
         [0037]     The basic architecture of this approach is illustrated in  FIG. 5 .  
         [0038]     In contrast to option I above, the frame synchronization process is in this case not subdivided into “preprocessing” and “postprocessing”. A complete frame synchronization process is thus carried out in parallel with the verification of the corresponding slot boundary. Once the frame synchronization and code group identification have been carried out, the verification results are also available. Once again, confirmed slot boundaries are processed further, while unconfirmed slot boundaries are in contrast rejected.  
         [0039]     In contrast to option L as described above, both the Hadamard transformation and the code group identification are carried out first of all in the exemplary embodiment based on option II. The results of the slot boundary verification process are not considered until this has been done. Thus, according to option II, computation effort is also appended for unconfirmed slot boundaries.  
         [0040]     Option III:  
         [0041]     The basic architecture for this approach is illustrated in  FIG. 6 .  
         [0042]     In this implementation option, the results of the slot boundary verification are considered only in the third step element, that is to say only in the scrambling code identification.  
         [0043]     The object of scrambling code identification is to detect the valid scrambling code from the eight possible scrambling codes of a code group which has been identified in the “frame synchronization” step element. In this case, by way of example (as is illustrated in  FIG. 6 ), a group of eight rake fingers is loaded with the eight possible scrambling codes, and their outputs are evaluated over a specific number of slots.  
         [0044]     The scrambling code for the finger with the greatest output value is that with the highest probability corresponding to the applicable scrambling code. The magnitude of the maximum output value may also be used as a criterion for the reliability of this decision. If this output value is combined with the corresponding soft result from the slot boundary verification (see  FIG. 6 ), then this results in a new value which can be used as a criterion for the overall synchronization result with respect to a specific slot boundary.  
         [0045]     If this value is in turn compared with a predetermined threshold value THRESH_V2, then this results, for example, in confirmation of the synchronization result for a “1” and, in a corresponding manner, in rejection for a “0”.  
         [0046]     One significant advantage of this exemplary embodiment based on option III is the fact that the longer observation time period which is included in the verification result results in a better decision quality with regard to the synchronization status.  
         [0047]     The use of the architecture proposed here also makes it possible to verify the synchronization results or corresponding result elements without any additional time being required. In addition, it is even possible to shorten the mean synchronization time, since spurious synchronizations are identified during the synchronization procedure itself, and there is no need to wait for the final result. In contrast, very little additional hardware complexity is involved (a correlator with a corresponding code generator and registers).  
         [0048]     In particular, this approach differs from the prior art in that synchronization and verification steps are not carried out successively (serially) but in parallel and ideally synchronously, and the verification results can thus be included in the overall synchronization process in a highly flexible form.  
         [0049]     A further exemplary embodiment of the invention comprises a combination of option I, as described above, or of option II, as described above, with option III, as described above.  
         [0050]      FIGS. 7 and 8  show a comparison of the detection results for slot synchronization without verification and with verification.  
         [0051]     As can be seen from  FIG. 7 , the false alarm rate as well as the rate of incorrectly detected slot boundaries over the entire energy range E pSCH  of the first synchronization channel pSCH is significantly (that is to say by several orders of magnitude) higher without verification than with verification.  
         [0052]     As can be seen from  FIG. 8 , the probability of only a single slot synchronization run being required for slot synchronization is more than 50% for all the channel energy levels EPSCH (−22 dB, −21 dB, −20 dB, −19 dB). Four or more slot synchronization runs are required only for a few cases in which the channel energy is low.