Abstract:
The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. provisional patent application No. 61/693,040, filed Aug. 24, 2012, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure relates to a power device and packaging thereof and in particular to gallium nitride (GaN) power devices along with their packaging. 
       BACKGROUND 
       [0003]    The packaging of power devices is critical to device and system performance. Low resistance and low inductance connections are desirable for device terminals such as the source and drain terminals of a transistor or the anode and cathode terminals of a diode. 
         [0004]      FIG. 1  depicts a cross-section view of a prior art high-voltage transistor  10  having a vertical structure with an unpatterned backside metallization that serves as a drain pad  12 . Examples of such vertical devices include double-diffused metal oxide semiconductor (DMOS) transistors, insulated gate bipolar transistors (IGBTs), and junction field effect transistors (JFETs). These devices include a die  14  with a substrate  16  and an epitaxial layer  18  that are conductive. As a result, a through wafer via is not required. Moreover, a die attach process is provided with a large area, low resistance, and high current connection to the drain pad  12 . Further still, a gate bond pad  20  and a source bond pad  22  are located on a frontside  24 . A gate current is typically much less than a source current. Thus, the majority of the frontside  24  is usable for the source bond pad  22 . A resulting large pad area available to the source bond pad  22  enables a low-cost, high current connection using large diameter wires, ribbons, or clips. A further advantage of the large pad area is that only a few large area bonds to the source bond pad  22  are required to carry a maximum device current. Another advantage is that the die  14  is also in good thermal contact with the substrate, which assists with heat dissipation. 
         [0005]    In contrast to vertical power devices, gallium nitride (GaN) high electron mobility transistors (HEMTs) are lateral devices. As shown in  FIG. 2  depicting a bond pad layout for a GaN device  26 , GaN HEMTs can have a first gate pad  28 , a second gate pad  30  along with both a source pad  32  and a drain pad  34  on a die front surface  36 . To minimize die area, the source pad  32  and the drain pad  34  both have dimensions that are minimized. As a result of their minimized dimensions, the source pad  32  and the drain pad  34  of GaN HEMTs only provide enough space for small diameter bond wires such as source bond wires  38  and drain bond wires  40 . A typical diameter for a bond wire using gold (Au) is about 25.4 μm (1 mil). As such, a typical 1200 V class GaN device in a standard TO-247 package can require between  20  and  30  bond wires on both the source pad  32  and the drain pad  34 . Not only does this many bond wires add a significant packaging cost, but bond wires have significant inductance which can have a negative effect on the switching characteristics of the GaN device  26 . Larger diameter bond wires, ribbons, or clips typically require a relatively large landing area that undesirably and significantly increases total die area of the GaN device  26 . Another packaging option is a flip-chip process that attaches a die to a substrate using metallic bumps that are fabricated onto bond pads. However, in this case, the die is in poor thermal contact with the substrate, which results in a high thermal resistance and poor performance at elevated temperature. What is needed is an alternative structure for GaN devices such as transistors and diodes that reduces the cost and complexity of die assembly without introducing the aforementioned problems. 
       SUMMARY 
       [0006]    The present disclosure relates to a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Bond pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside. 
         [0007]    One embodiment includes a power module substrate adhered to the die backside. The power module substrate has an isolation region that electrically isolates patterned backmetals from each other. 
         [0008]    Another embodiment has a thermal shunt that is fabricated within the power module substrate between isolation regions. The thermal shunt conducts heat away from the semi-insulating substrate, and in turn away from the epitaxial layers. 
         [0009]    Yet another embodiment includes additional circuit element(s) coupled between the patterned backside metals. The additional circuit element(s) can be passive circuit elements or active circuit elements. The additional circuit element(s) can also be limiters and/or protectors for limiting current and overvoltage surges. 
         [0010]    Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
           [0012]      FIG. 1  is a cross-section view depicting a bond pad configuration for a prior art power transistor. 
           [0013]      FIG. 2  is a plan view of a prior art bond pad layout for gallium nitride GaN high electron mobility transistors (HEMTs). 
           [0014]      FIG. 3  is a cross-section view of an exemplary GaN device depicting source and drain connections on a backside of a die in accordance with the present disclosure. 
           [0015]      FIG. 4  is a cross-section view of the exemplary GaN device depicting a thermal shunt in addition to the source and drain connections. 
           [0016]      FIG. 5  is a cross-section view of the exemplary GaN device depicting an additional circuit element coupled between the drain, source, and/or gate. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0018]    It will be understood that when an element such as a layer, region, or substrate is referred to as being “over,” “on,” “in,” or extending “onto” another element, it can be directly over, directly on, directly in, or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over,” “directly on,” “directly in,” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0019]    Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. Moreover, the term high resistivity and the term semi-insulating are used interchangeably throughout the disclosure. It is also to be understood that semi-insulating means electrically semi-insulating. 
         [0020]      FIGS. 3 through 5  depict alternative structures for GaN devices such as transistors and diodes that reduce the cost and complexity of die assembly without introducing the aforementioned problems. Beginning with  FIG. 3 , a GaN device  42  includes a source pad  44  and a drain pad  46  disposed onto a die frontside  47  that includes GaN epitaxial layers  48 . A device active area  50  is located between the source pad  44  and the drain pad  46 . A semi-insulating substrate  52  supports the GaN epitaxial layers  48 . The semi-insulating substrate  52  has a bulk resistivity that ranges from around about 10 7  Ohm-cm to around about 10 12  Ohm-cm. 
         [0021]    A die backside  54  includes a first patterned backmetal  56  that is disposed within a source backside via  58 . The first patterned backmetal  56  couples the source pad  44  to a first die attach region  60  that adheres a power module substrate  62  to the die backside  54 . The die backside  54  also includes a second patterned backmetal  64  that is disposed within a drain backside via  66 . The second patterned backmetal  64  couples the drain pad  46  to a second die attach region  68  that adheres the power module substrate  62  to the die backside  54 . An isolation region  70  provides electrical isolation between the first patterned backmetal  56  and the second patterned backmetal  64 . 
         [0022]      FIG. 4  is a cross-section view of another embodiment of the present disclosure, wherein a GaN device  72  includes a thermal shunt  74  located within the power module substrate  62  and under the device active area  50  for shunting heat away from the semi-insulating substrate  52 . A third patterned backmetal  76  is disposed onto a third die attach region  78 , which in turn is disposed onto the thermal shunt  74 . A first isolation region  80  and a second isolation region  82  electrically isolate the third patterned backmetal  76 , the third die attach region  78 , and the thermal shunt  74  from the first patterned backmetal  56  and the second patterned backmetal  64 . 
         [0023]      FIG. 5  is a cross-section view of another embodiment of the present disclosure, wherein a GaN device  84  includes at least one circuit element  86  that is coupled between the source pad  44  and the drain pad  46  by a direct coupling of the circuit element  86  to the first patterned backmetal  56  and the second patterned backmetal  64 . Exemplary types of circuit elements for circuit element  86  include transistors, diodes, resistors, capacitors, and inductors. The circuit element  86  can also be a limiter or protector for preventing damage to the GaN device  84  due to overcurrent, overvoltage, and surge voltage and/or surge current. The circuit element  86  can also be coupled between either the first patterned backmetal  56  or the second patterned backmetal  64  to a feature such as a gate pad (not shown). Moreover, it is to be understood that the circuit element  86  can be also be coupled to other features of the GaN device  84  using other patterned backmetal features like the first patterned backmetal  56  and the second patterned backmetal  64 . 
         [0024]    Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.