Abstract:
A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a Voltage Controlled Oscillator (VCO), and more particularly, to a VCO that is not affected by the variations of the process and the bias voltage source. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional VCO  100 . The VCO  100  comprises a reference current source module  110  and a clock signal generating module  120 . The reference current source module  110  functions to generate reference currents I BIAS  and I 1 , as well as the voltages V A  and V B . The clock signal generating module  120  generates a clock signal CLK with a frequency corresponding to the level of the voltages V A  and V B . 
         [0005]    The reference current source module  110  comprises P-type Metal Oxide Semiconductor (PMOS) transistors Q P1  and Q P2 , and N-type Metal Oxide Semiconductor (NMOS) transistors Q N1  and Q N2 . The source (first end) of transistor Q P1  is coupled to the bias voltage source V DD ; the gate (control end) of the transistor Q P1  is coupled to the gate of the transistor Q P2 ; the drain (second end) of the transistor Q P1  is coupled to the drain of the transistor Q N1 . The source (first end) of the transistor Q P2  is coupled to the bias voltage source V DD ; the gate (control end) of transistor Q P2  is coupled to the gate of the transistor Q P1 ; the drain (second end) of the transistor Q P2  is coupled to the drain of the transistor Q N2 . The source (first end) of the transistor Q N1  is coupled to the bias voltage source V SS  (ground end); the gate (control end) of the transistor Q N1  is utilized to receive the reference voltage V REF ; the drain (second end) of transistor Q N1  is coupled to the drain of the transistor Q P1 . The source (first end) of the transistor Q N2  is coupled to the bias voltage source V SS ; the gate (control end) of transistor Q N2  is coupled to the drain of transistor Q P2 ; the drain (second end) of transistor Q N2  is coupled to the drain of transistor Q P2 . 
         [0006]    The transistor Q N1  receives the reference voltage V REF  and drains the current I BIAS , with the magnitude corresponding to the voltage level of the reference voltage V REF , from the transistor Q P1 . The transistors Q P2  and Q N2  form a current mirror for generating the current I 1  and the corresponding control voltages V A  and V B , where the current I 1  is a replica of the current I BIAS . Hence, the voltages V A  and V B  can then drive the current source of the clock signal generator  120  to generate a current with the same magnitude as the current I BIAS , and further generate the clock signal CLK with the frequency corresponding to the current generated by the current source of the clock signal generator  120 . 
         [0007]    However, the threshold voltage level of the Metal Oxide Semiconductor (MOS) transistor is influenced by the process variation. According to the current generating formula of the NMOS transistor: 
         [0000]        I=K ( V   GS   −V   TH ) 2    (1); 
         [0000]    where K represents a constant, V GS  represents the voltage difference between the gate and the source of the NMOS transistor, and V TH  represents the threshold voltage of the NMOS transistor, the current I BIAS  being drained by the transistor Q N1  of the reference current source module  110  can be calculated from the above formula as below: 
         [0000]        I   BIAS   =K ( V   REF   −V   SS   −V   TH ) 2    (2). 
         [0008]    From formula (2), it can be seen that even in the presence of constant reference voltage V REF , the reference current I BIAS  is still dependent on the threshold voltage V TH  and the bias voltage source V SS , consequently affecting the magnitude of the replicated current I 1  and the subsequently generated voltages V A  and V B . Therefore, since the current generated by the clock signal generating module  120  is controlled by the voltages V A  and V B , the frequency of the output clock signal CLK is inevitably affected, causing great inconvenience. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention provides a Voltage Controlled Oscillator (VCO) that is not affected by the process or the bias voltage source. The VCO generates a clock signal with a frequency corresponding to a reference voltage. The VCO comprises a reference current source generating module and a clock signal generating module. The reference current source generating module comprises an amplifier, a resistor and a first transistor. The amplifier comprises a positive input end for receiving the reference voltage, an negative end, and an output end coupled to the negative end of the amplifier. The resistor is coupled between the negative end of the amplifier and a ground end. The first transistor comprises a first end coupled to a bias voltage source, a control end coupled to the output end of the amplifier, and a second end. The first transistor generates a reference current according to the reference voltage. The clock signal generating module outputs the clock signal with the corresponding frequency according to the reference current. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating a conventional VCO. 
           [0012]      FIG. 2  is a diagram illustrating a VCO of the present invention. 
           [0013]      FIG. 3  is a diagram illustrating the main band-gap voltage reference circuit of the present invention. 
           [0014]      FIG. 4  is a diagram illustrating the temperature-rise-dependent current generating circuit of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a VCO  200  of the present invention. The VCO  200  comprises a reference current source module  210  and a clock signal generating module  220 . The reference current source module  210  functions to generate reference currents I BIAS  and I 2 , as well as voltages V A  and V B . The clock signal generating module  220  generates a clock signal CLK with a frequency corresponding to the levels of the voltages V A  and V B . 
         [0016]    The reference current source module  210  comprises two PMOS transistors Q P3  and Q P4 , an NMOS transistor Q N3 , a resistor R 1 , a main band-gap voltage reference circuit  211 , and an amplifier AMP 1 . The source (first end) of the transistor Q P3  is coupled to the bias voltage source V DD ; the gate (control end) of the transistor Q P3  is coupled to the output end of the amplifier AMP 1 ; the drain (second end) of the transistor Q P3  is coupled to the negative input end of the amplifier AMP 1  and the resistor R 1 . The resistor R 1  is coupled between the negative input end of the amplifier AMP 1  and the bias voltage source V SS . The positive input end of the amplifier AMP 1  is coupled to the main band-gap voltage reference circuit  211  for receiving the reference voltage V REF ; the negative input end of the amplifier AMP 1  is coupled between the resistor R 1  and the source of the transistor Q P3 ; the output end of the amplifier AMP 1  is coupled to the gate of the transistor Q P3 . The source (first end) of the transistor Q P4  is coupled to the bias voltage source V DD ; the gate (control end) of the transistor Q P4  is coupled to the gate of the transistor Q P3 ; the drain (second end) of the transistor Q P4  is coupled to the drain of the transistor Q N3 . The source (first end) of the transistor Q N3  is coupled to the bias voltage source V SS ; the gate (control end) of the transistor Q N3  is coupled to the drain of the transistor Q P4 ; the drain (second end) of the transistor Q N3  is coupled to the drain of the transistor Q P4 . 
         [0017]    The positive input end of the amplifier AMP 1  is coupled to the main band-gap voltage reference circuit  211  for receiving the reference voltage V REF . Hence, the negative input end of the amplifier AMP 1  is accordingly clamped to the level of the voltage V REF . As shown in  FIG. 2 , the current (which is equivalent to the reference current I BIAS ) flowing through the resistor R 1  is (V REF /R 1 ). Therefore, since the reference current I BIAS  is clamped to (V REF /R 1 ), varying the bias voltage source and/or the threshold voltage no longer affects the reference current I BIAS . The current I 2 , which is replicated from the current mirror formed by the transistors Q P4  and Q N3 , inherent the characteristics of the reference current I BIAS  and avoids being affected by the bias voltage and/or the threshold voltage. As a result, the current source generated by the clock signal generating module  220 , which is controlled by the voltages V A  and V B , is impervious to the bias voltage source and the threshold voltage. Hence, the clock signal CLK outputted from the clock signal generating module  220  can be generated with the accurate frequency corresponding to the voltage level of the reference voltage V REF . 
         [0018]    Please continue referring to  FIG. 2 . The clock signal generating module  220  comprises m inverting modules  221 ˜ 22   m.  The number of inverting modules (which is equivalent to m) in the clock signal generating module  220  must be odd, for being able to generate the clock signal (the clock signal cannot be generated with an even number of inverting modules). Each inverting module comprises an inverter, an NMOS transistor, a PMOS transistor, and a capacitor. The inverter of every inverting module is utilized to receive the signal generated from the inverting module of the previous stage, and the received signal is then inverted for outputting to the inverting module of the next stage. The outputted signal of the m th  inverting module is utilized as the final outputted clock signal CLK, and meanwhile the outputted signal of the m th  inverting module is fed back to the inverter of the 1 st  inverting module. For instance, the 1 st  inverting module  221  comprises an inverter INV 1 , a transistor Q N41 , a transistor Q P51 , and a capacitor C 1 . The transistors Q N41  and Q P51  form a current mirror for replicating the current I 2 , which is replicated from the current mirror formed by the transistor Q P4  and Q N3 . The source of the transistor Q P51  is coupled to the bias voltage source V DD ; the gate of the transistor Q P51  functions to receive the voltage V A ; the drain of the transistor Q P51  is utilized to output the current I 2 . The source of the transistor Q P41  is coupled to the bias voltage source V SS ; the gate of the transistor Q P41  functions to receive the voltage V B ; the drain of the transistor Q P41  is utilized to drain the current I 2 . 
         [0019]    The inverter INV 1  comprises two current ends, an input end, and an output end. The two current ends of the inverter INV 1  are coupled to the drain of the transistor Q P51  and the drain of the transistor Q N41  respectively, for receiving/draining current accordingly. In other words, the current flowing through the inverter INV 1  is equivalent to the current I 2 . The input end of the inverter INV 1  is coupled to the output end of the inverter INV m  of the inverting module  22   m,  for receiving the clock signal CLK; the output end of the inverter INV 1  is coupled to the capacitor C 1  and the input end of the inverter INV 2  of the inverting module  222  of the next stage. The capacitor C 1  is coupled between the output end of the inverter  221  and the bias voltage source V SS . Hence, the inverter  221  can adjust the duration of the inverted signal being outputted (due to the presence of capacitor C 1 , the time required for capacitor C 1  to charge/discharge depends on the magnitude of current I 2 ), according to the magnitude of the received current I 2 . For instance, when the inverter INV 1  receives an input signal with the low voltage level, if the current I 2  is at a relative higher level, the response time required for the inverter INV 1  to output an output signal with the high voltage level (inverted from the input signal with the low voltage level) is relatively shorter; and vice versa. The structure and operation principle of the inverter modules of other levels can be extrapolated from the discussion above and is omitted hereafter for brevity. 
         [0020]    The VCO of the present invention comprises a reference current source module which is unaffected by the variations of the process and the bias voltage source. Hence, the VCO of the present invention can generate a clock signal with a stable frequency. The frequency of the generated clock signal is adjusted according to the input reference voltage V REF  without being affected by the variations of the process and the bias voltage source. 
         [0021]    Furthermore, in the reference current source module  210  of the present invention, the reference voltage V REF  outputted from the main band-gap voltage reference circuit  211  can be designed to be temperature-related. For instance, when the temperature rises, the voltage level of the reference voltage V REF  also rises accordingly, and vice versa; when the temperature declines, the level of reference voltage V REF  decreases accordingly. The above relation can be formulated as below: 
         [0000]        V   REF   =V   REF     —     INI ×(1+ JT )   (3); or 
         [0000]        V   REF   =V   REF     —     INI ×(1− JT )   (4); 
         [0000]    where V REF  represents the reference voltage V REF , which is adjusted according to the temperature, outputted from the main band-gap voltage reference circuit  211 ; V REF     —     INI  represents the default reference voltage outputted from the main band-gap voltage reference circuit  211 ; T represents the level of temperature variation; J represents a temperature variable (positive value). Hence, through such design formulated in formula (3), when the temperature rises, the reference voltage V REF  also increases, resulting in an increase of the currents I BIAS  (I BIAS =V REF /R 1 ) and I 2 . Because of the current increase, the response speed of the inverting modules of the clock signal generating module  220  is accelerated, consequently affecting the frequency of the clock signal CLK to increase accordingly. In contrast, when the temperature declines, the reference voltage V REF  decreases, resulting in a decline of the currents I BIAS  (I BIAS =V REF /R 1 ) and I 2 . Because of the current drop, the response speed of the inverting modules of the clock signal generating module  220  is decelerated, consequently affecting the frequency of the clock signal CLK to decrease accordingly. 
         [0022]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating the main band-gap voltage reference circuit  211  of the present invention. As shown in  FIG. 3 , the main band-gap voltage reference circuit  211  comprises a temperature-rise-dependent current generating circuit  2111 , a temperature-drop-dependent current generating circuit  2112  and a resistor R REF . The temperature-rise-dependent current circuit  2111  functions to generate a temperature-rise-dependent current I T+ , which increases as the temperature rises. The temperature-drop-dependent current circuit  2112  functions to generate a temperature-drop-dependent current I T− , which increases as the temperature decreases. The resistor R REF  is coupled between the bias voltage source V SS  and the output ends of the temperature-rise-dependent current generating circuit  2111  and the temperature-drop-dependent current generating circuit  2112  for receiving the temperature-rise-dependent current I T+  and the temperature-drop-dependent current I T− . The voltage across the resistor R REF  is equivalent to the reference voltage V REF  [where V REF =R REF ×(I T+ +I T− )] outputted by the main band-gap voltage reference circuit  211 . 
         [0023]    Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating the temperature-rise-dependent current generating circuit  2111  of the present invention. As shown in  FIG. 4 , the temperature-rise-dependent current generating circuit  2111  comprises a temperature-rise-dependent band-gap voltage reference circuit  400 , an amplifier AMP 2 , a resister R X , six transistors Q 5 ˜Q 10 , and a switch SW 1 . The transistors Q 5 ˜Q 10  are PMOS transistors. The aspect ratios (width/length) of the transistors Q 5 ˜Q 10  are 1:6/4:5/4:4/4:3/4:2/4, respectively. Hence, with identical gate voltage supplies, the ratio of the current generated by the transistors Q 5 ˜Q 10  are also 1:6/4:5/4:4/4:3/4:2/4, respectively. 
         [0024]    The temperature-rise-dependent band-gap voltage reference circuit  400  functions to generate a temperature-rise-dependent reference voltage V REFT+ . The voltage level of the temperature-rise-dependent reference voltage V REFT+  increases with the temperature. The positive input end of the amplifier AMP 2  is coupled to the temperature-rise-dependent band-gap voltage reference circuit  400 , for receiving the reference voltage V REFT+ . Hence, the negative input end of the amplifier AMP 2  is inherently clamped to the voltage V REFT+ . The sources of the transistors Q 5 ˜Q 10  are coupled to the bias voltage source V DD ; the gates of the transistors Q 5 ˜Q 10  are coupled to the output end of the amplifier AMP 2 ; the drain of the transistor Q 5  is coupled to the negative input end of the amplifier AMP 2 . As shown in  FIG. 4 , the current I X  flowing pass the resistor R x  is equivalent to (V REFT+ /R X ). Hence, the gate of the transistor Q 5  is controlled by the amplifier AMP 2 , for ensuring the magnitude of the current I X  outputted is kept at (V REFT+ /R X ). Similarly, as controlled by the amplifier AMP 2 , the magnitudes of the currents outputted by the transistors Q 6 ˜Q 10  are (6/4)I X , (5/4)I X , (4/4)I X , (3/4)I X , (2/4)I X , respectively. The switch SW 1  comprises input ends I A , I B , I C , I D , and I E , an output end O, and a control end C. Each of input ends I A ˜I E  of the switch SW 1  is coupled to the drain of the transistors Q 6 ˜Q 10 , for receiving the currents (6/4)I X , (5/4)I X , (4/4)I X , (3/4)I X , (2/4)I X , respectively. A control signal S C  received by the control end C of the switch SW 1 , the switch SW 1  switches one of input ends I A ˜I E  of the switch SW 1  to couple to the output end O of the switch SW 1 , for directing the received current to output as the temperature-rise-dependent current I T+  of the temperature-rise-dependent current generating circuit  2111 . For instance, when the switch SW 1  switches the input end I E  of the switch SW 1  to couple to the output end O of the switch SW 1 , the temperature-rise-dependent current I T+  outputted is (2/4)I X , which is equivalent to (2/4)×(V REFT+ /R X ). The switch SW 1  can be realized with a set of fuses. For instance, the switch SW 1  can comprise five fuses, where one end of each fuse is coupled to the drain of the corresponding transistors Q 6 ˜Q 10  respectively and the other end of each fuse is coupled to the output end O of the switch SW 1 . The user can burn down fuses selectively to determine the magnitude of the outputted temperature-rise-dependent current I T+  of the temperature-rise-dependent current generating circuit  2111 . For instance, the user can burn down all fuses but the one coupled between the transistor Q 10  and the output end O of switch SW 1 , resulting in the temperature-rise-dependent current I T+  to be (2/4)I X . 
         [0025]    The structure and operation principle of the temperature-drop-dependent current generating circuit  2112  is similar to the temperature-rise-dependent current generating circuit  2111 , and the relative description is omitted hereafter for brevity. The only difference being that in the temperature-drop-dependent current generating circuit  2112  is: the band-gap voltage reference circuit being utilized is a temperature-drop-dependent band-gap voltage reference circuit (as opposed to the temperature-rise-dependent band-gap voltage reference circuit used in the temperature-rise-dependent current generating circuit  2111 ), where the voltage level of the generated reference voltage decreases as the temperature increases. 
         [0026]    To sum up, the present invention provides a VCO that is not only unaffected by the variations of the process and the bias voltage source, but is also able to adjust the frequency of the output clock signal according to the temperature variation, hence providing great convenience. 
         [0027]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.