Abstract:
Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to techniques for applying modulation constraints to interleaved data, and more particularly, to techniques for applying modulation constraints separately to even and odd bits in a data stream.  
         [0002]     A disk drive can write data bits onto a data storage disk such as a magnetic hard disk. The disk drive can also read data bits that have been stored on a data disk. Certain sequences of data bits are difficult to write onto a disk and often cause errors during read-back of the data.  
         [0003]     Long recorded data sequences of the same polarity are examples of data bit patterns that are prone to errors. These data sequences correspond to long sequences of binary zeros or binary ones in the NRZ (non return-to-zero) representation, or alternatively to long sequences of binary zeros in the NRZI or PR4 representations. Another example of error prone data bit patterns are long sequences of zeros in alternating positions (e.g., 0a0b0c0d0 . . . , where a, b, c, d may each be 0 or 1) in the PR4 representation  
         [0004]     Binary sequences are routinely transformed from one representation to another using precoders and inverse precoders, according to well known techniques. In the present application, binary sequences are represented as PR 4  sequences unless otherwise stated. A PR 4  representation can be transformed into an NRZI representation by a precoder which convolves with 1/(1+D) or into an NRZ representation by a precoder which convolves with 1/(1+D 2 ).  
         [0005]     It is desirable to eliminate error prone bit sequences in user input data. Eliminating error prone bit sequences ensures reliable operation of the detector and timing loops in a disk drive system. One way to eliminate error prone bit sequences is to substitute the error prone bit sequences with non-error prone bit patterns that are stored in memory in lookup tables. Lookup tables, however, are undesirable for performing substitutions of very long bit sequences, because they require a large amount of memory.  
         [0006]     Many disk drives have a modulation encoder. A modulation encoder uses modulation codes to eliminate sequences of bits that are prone to errors.  
         [0007]     Maximum transition run (MTR) constrained codes are one specific type of modulation code that are used in conjunction with a 1/(1+D) precoder. With respect to MTR codes, a j constraint refers to the maximum number of consecutive ones in an NRZI representation, a k constraint refers to the maximum number of consecutive zeros in an NRZI representation, and a t constraint refers to the maximum number of consecutive pairs of bits of the same value in an NRZI representation (e.g., AABBCCDDEE . . . ).  
         [0008]     Codes that constrain the longest run of zero digits in the PR4 representation of a sequence are said to enforce a G-constraint where G is the longest allowed run of consecutive zeros. A G constrained PR4 representation is mapped to a k-constrained NRZI representation by a 1/(1+D) precoder, where k=G+1.  
         [0009]     Codes that constrain the longest run of zero digits in alternate locations in the PR4 representation of a sequence are said to enforce an I-constraint, where I is the longest run of zeros in consecutive odd or even locations. An I-constrained sequence is necessarily G-constrained with G=2I. An I constrained PR4 representation is mapped to a t-constrained NRZI representation by a 1/(1+D) precoder, where t=I.  
         [0010]     Fibonacci codes are one example of modulation codes that are used by modulation encoders. Fibonacci codes provide an efficient way to impose modulation code constraints on recorded data to eliminate error prone bit sequences. A Fibonacci encoder maps an input number to an equivalent number representation in a Fibonacci base. A Fibonacci encoder maps an input vector with K bits to an output vector with N bits. A Fibonacci encoder uses a base with N vectors, which is stored as an N×K binary matrix. Successive application of Euclid&#39;s algorithm to the input vector with respect to the stored base gives an encoded vector of length N.  
         [0011]     Fibonacci codes are naturally constructed to eliminate long runs of consecutive one digits. This is expressed in the literature as the j constraint, where the parameter j enumerates the longest permitted run of ones. A trivial modification of the Fibonacci code is formed by inverting the encoded sequence. This inverted Fibonacci code eliminates long runs of consecutive zero digits. This constraint is expressed in the literature variously as the k constraint or G constraint, where the parameter k (or G) enumerates the longest permitted run of zeros. Fibonacci codes do not naturally enforce I constraints nor a combination of G and I constraints.  
         [0012]     It would therefore be desirable to extend the Fibonacci codes construction to encompass combined G and I constraints.  
       BRIEF SUMMARY OF THE INVENTION  
       [0013]     The present invention provides techniques for applying modulation constraints to data streams divided into two separate interleaved portions. Initially, the even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a modulation constraint for even bits. A second modulation encoder encodes the odd bits according to a modulation constraint for odd bits, which in general coincides with the modulation constraint for even bits. The two encoded data streams can be interleaved to form one data stream. According to one embodiment of the present invention, the modulation encoders encode the even and odd bits using Fibonacci encoding.  
         [0014]     In a preferred embodiment, odd and even sequences are encoded separately using a pair of Fibonacci encoders which enforce a G-constraint. The resulting interleaved data sequence satisfies both G and I constraints.  
         [0015]     Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1A  illustrates a modulation encoding scheme that applies modulation constraints to even and odd bits separately, according to an embodiment of the present invention.  
         [0017]      FIG. 1B  illustrates a specific example of the modulation encoding scheme shown in  FIG. 1A . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]      FIG. 1A  illustrates an embodiment of a modulation encoder that applies modulation constraints to an interleaved set of data. The modulation encoder of  FIG. 1A  (as well as the modulation encoder of  FIG. 1B ) can eliminate sequences of alternating zeros in user data.  
         [0019]     The modulation encoder of  FIG. 1A  has a demultiplexer  101  that separates out the even and odd bits in the user input data. For example, the first, third, fifth, seventh, ninth, eleventh, etc. bits can be designated as the odd bits, and the second, fourth, sixth, eighth, tenth, etc. bits can be designated as the even bits. The odd bits are represented as o 1  . . . o k , and the even bits are represented as e 1  . . . e k .  
         [0020]     Fibonacci encoder  102  encodes the even bits e 1  . . . e k , and Fibonacci encoder  103  encodes the odd bits o 1  . . . o k . Fibonacci encoder  102  applies a global modulation constraint Ge to the even bits, and Fibonacci encoder  103  applies a global modulation constraint Go to the odd bits. Normally, Go=Ge. Fibonacci encoders  102  and  103  encode the input bits to impose a maximum number of consecutive 0s by converting the k incoming data bits in each interleaved level into N encoded bits using a Fibonacci base conversion technique.  
         [0021]     Each encoder  102 / 103  receives an unconstrained input number that has k bits and generates a constrained output number that has n bits. Encoder  102  converts unconstrained even bits e 1  . . . e k  into constrained even bits E 1  . . . E n . Encoder  103  converts unconstrained even bits o 1  . . . o k  into constrained even bits O 1  . . . O n .  
         [0022]     Global constraints Ge and Go may be different constraints or the same constraint. For example, encoder  102  can limit the even bit input number to having no more than 5 consecutive zeros, while at the same time, encoder  103  can limit the odd bit input number to having no more than 4 consecutive zeros. Alternatively, the even and odds bit input numbers can both be limited to no more than 4 consecutive zeros.  
         [0023]     Multiplexer  104  interleaves the constrained even bits E 1  . . . E n  and the constrained odd bits O 1  . . . O n  to generate the interleaved constrained output data O 1 , E 1 , . . . O n , E n . The output data of multiplexer  104  is constrained according to formulae G=2×Ge, if Ge=Go; or G=1+2×min(Ge, Go), if Ge≠Go. For example, if Ge=4 and Go=6, then G=9.  
         [0024]     The output data of multiplexer  104  is also constrained according to the formula I=max (Ge, Go). This formula means that the maximum number of alternating zeros in the interleaved output data equals the greater constraint applied to the even or the odd bits. For example, if Ge=4 and Go=6, then I=6.  
         [0025]      FIG. 1B  illustrates a specific example of the generalized modulation encoder shown in  FIG. 1A . Demultiplexer  111  separates the user data bits into the even and odd bits, as discussed above. Fibonacci encoder  112  encodes an (N−1)-bit vector corresponding to the even bits into an N-bit vector using a Fibonacci base, while Fibonacci encoder  113  does the same with the (N−1) odd bits. Fibonacci encoder  112  forces a constraint of Ge to the input even bits, while Fibonacci encoder  113  forces a constraint of Go to the input odd bits, as with the generalized embodiment of  FIG. 1A .  
         [0026]     In the example shown in  FIG. 1B , Fibonacci encoders  112  and  113  each covert an input number with N−1 bits into an output number with N bits, using well known Fibonacci encoding techniques. Fibonacci encoders  112  and  113  can convert input numbers with any number of bits into the Fibonacci base. For example, encoders  112  and  113  can convert input numbers that have 199 bits into output numbers that have 200 bits in the Fibonacci base. The modulation rate of each encoder  112  and  113  is (N−1)/N. The overall modulation rate of the code in  FIG. 1B  is 2(N−1)/2N=(N−1)/N.  
         [0027]     Fibonacci encoders  112  and  113  each map N−1 input bits into N encoded bits. For example, Fibonacci encoders  112  and  113  can map 199 bits into 200 bits (N=200). A lookup table approach would require storing 2 199  input vectors. Fibonacci codes solve this problem by storing 200 base vectors, that each have a length of 199.  
         [0028]     While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes, and substitutions are intended in the present invention. In some instances, features of the invention can be employed without a corresponding use of other features, without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular configuration or method disclosed, without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.