Abstract:
A circuit for reading a semiconductor memory device includes at least one global circuit for generating a global reference signal for a respective plurality of cell-reading circuits disposed locally in the memory device. The circuit includes at least one circuit for replicating the reference signal locally in order to generate a local reference signal to be supplied to at least one respective cell-reading circuit.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of semiconductor memories, and more particularly, to circuits for reading the ROM, EPROM, EEPROM and Flash EEPROM type semiconductor memories. 
     BACKGROUND OF THE INVENTION 
     Semiconductor-memory reading circuits perform a comparison between two currents (or voltages) to read the data stored in memory cells. A current (or voltage) of a memory cell selected for reading is compared with a reference current (or voltage). The reference currents (or voltages) for the reading circuits are typically generated with the use of reference memory cells which are structurally identical to the memory cells and are programmed to predetermined levels, typically during the testing of the individual memory device. 
     There is a need to provide memories with ever larger bandwidths and ever lower energy consumption per individual bit. This need is imposed by the ever higher performance of electronic systems. On the other hand, the time required to perform reading cannot be reduced indefinitely since it is limited by physical constraints such as the charging time of the word lines of the memory. To achieve a greater bandwidth, it is therefore necessary to perform several cell readings in parallel. To be able to perform several readings in parallel, it is necessary to increase the number of cell-reading circuits and of respective circuits for generating reference currents (or voltages). This results in a significant increase in the area and energy consumption of the memory device. 
     To limit the increase in area and consumption, attempts have been made to limit the number of circuits for generating reference currents (or voltages). The same reference signal (current or voltage) generated at one point of the device is thus supplied to several cell-reading circuits by bringing the reference signal (current or voltage) to the various points of the device at which the reading circuits are arranged. The limiting of the number of reference-signal generating circuits brings advantages both in terms of area and in terms of consumption, and also in terms of the time required to test the individual device, since the number of reference cells to be programmed to the desired levels is reduced. 
     However, since the reference signal has to travel considerable distances inside the device, a large parasitic capacitance associated with the reference-signal distribution lines degrades the reference signal. It is also necessary to add the capacitances of the input nodes of the various cell-reading circuits which the reference signal supplies. The time required for the reference signal to reach the predetermined steady value therefore increases and the bandwidth of the memory device is limited. Moreover, since the various cell-reading circuits are coupled capacitively to the reference signal, the intrinsic imbalances in their operation in the course of the reading of the respective memory cells selected may cause errors in the reading, particularly when they are reading memory cells with large margins (distances between thresholds) involving large current or voltage ranges which alter the value of the reference signal. 
     SUMMARY OF THE INVENTION 
     In view of the prior art described, an object of the present invention is to provide a reading circuit for a memory device which solves the above-mentioned problems. 
     According to the present invention, this object is achieved by a circuit for reading semiconductor memory devices comprising at least one global circuit for generating a global reference signal for a respective plurality of cell-reading circuits disposed locally in the memory device. Specifically, the reading circuit comprises at least one circuit for replicating the reference signal locally to generate a local reference signal to be supplied to at least one respective cell-reading circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The characteristics and advantages of the present invention will become clearer from the following detailed description of a practical embodiment thereof, illustrated purely by way of non-limiting example in the appended drawings, in which: 
     FIG. 1 is a basic circuit diagram of a reading circuit for a memory device according to the present invention with a plurality of cell-reading circuits; 
     FIG. 2 is a more detailed circuit diagram of a cell-reading circuit, with respective equalization and precharging circuits; 
     FIGS. 3 and 4 show two different timing diagrams of the main signals during a reading of the memory device; 
     FIG. 5 is a circuit diagram of a preferred embodiment of an equalization switch for the cell-reading circuit of FIG. 2; and 
     FIG. 6 is a drawing explaining the operating principle of the equalization switch of FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIG. 1, a reading circuit for a memory device according to the present invention comprises a circuit  1  for generating a global reference signal RIFN for a plurality of cell-reading circuits SA 1 -SAn disposed locally. The circuit  1  is located at one point of the memory device. The cell-reading circuits SA 1 -SAn, however, are distributed at various points in the memory device. 
     The circuit  1  comprises a current mirror with a first branch  2   a  and a second branch  2   b . The branch  2   a  comprises a p-channel MOSFET P 1  connected as a diode with its source connected to a voltage VDD, which is typically, but not exclusively, the supply voltage of the memory device (for example, of 5 V or 3 V or less). Connected in cascade in series with the MOSFET P 1  are a circuit  3  for biasing the drains of the reference cells, a circuit  4  for selecting the columns of reference cells, and one or more reference cells RC, which are typically MOSFETs with floating gates but in any case are of the same type as the actual memory cells but are programmed to a predetermined level to conduct a known current when biased. The reference cells RC have their sources connected to ground and their control gates connected to a reading voltage Vread which can adopt different values depending on the mode of operation of the memory device (reading, verification, etc.). The second branch  2   b  comprises a p-channel MOSFET P 2  of which the source is connected to the supply VDD and the gate is connected to the gate of the MOSFET P 1  in the first branch  2   a , and in series with which an n-channel MOSFET N 1 , preferably of the so-called “natural” type, i.e. with a relatively low threshold voltage, is connected as a diode, with its source connected to ground. 
     Each cell-reading circuit SA 1 -SAn comprises a local current mirror with a first branch  5   a   1 - 5   a n and a second branch  5   b   1 - 5   b n. The first branch  5   a  comprises a p-channel MOSFET P 31 -P 3 n which has its source connected to the supply VDD and is in a diode configuration, and in series with which an n-channel MOSFET N 21 -N 2 n, preferably of the natural type is connected, with its source connected to ground and its gate connected to the global reference signal RIFN. It should be noted that the first branch  5 a 1 - 5 an of each local current mirror also forms the second branch of a further semi-local current mirror, the first branch of which is formed by the second branch  2   b  of the circuit  1 . 
     The second branch  5   b   1 - 5   b n of each local current mirror comprises a p-channel MOSFET P 41 -P 4 n with its source connected to the supply VDD and its gate connected to the gate of the MOSFET P 31 -P 3 n in the first branch  5   a   1 - 5   a n. Connected in cascade in series with the MOSFET P 41 -P 4 n are a circuit  31 - 3 n, similar to the circuit  3 , for biasing the drains of the memory cells, a circuit  41 - 4 n for selecting the columns of the matrix of memory cells and, finally, a memory cell MC 1 -MCn which, in the drawings, represents schematically the memory cell belonging to the column selected by the circuit  4  and to the line WL selected by a line-selection circuit which is not shown since it is of known type. 
     The gate of the MOSFET P 31  (the node MAT 11 -MAT 1 n) supplies a non-inverting input of a comparator  61 - 6 n, the inverting input of which is connected to the drain of the MOSFET P 41 -P 4 n. The output OUT 1 -OUTn of the comparator  61 - 6 n is supplied, by a circuit chain which may comprise one or more inverters and latches, to a respective output buffer, which is not shown since it is known. 
     The circuit of FIG. 1 operates as follows. If there is a single reference cell RC, a current I which flows in the branch  2   a  of the circuit  1  is the current absorbed by the reference cell biased with approximately 1 V at its drain (value set by the circuit  3 ) and the voltage Vread at its control gate. When there are several reference cells RC in parallel, the current I will be a whole multiple of the current absorbed by a single reference cell. The MOSFET P 1  mirrors the current I in the second branch  2   b  with a mirror coefficient a given by the aspect ratios (width/length) of the MOSFETs P 1  and P 2 . In the second branch  2   b , there is therefore a current aI proportional to the current I, preferably a whole multiple thereof. The current aI flowing in the MOSFET N 1  produces a global voltage reference signal RIFN which is brought to the various points of the memory device at which the cell-reading circuits SA 1 -SAn are situated. 
     With reference, for example, to the circuit SA 1 , the global reference signal RIFN imposes in the branch  5   a   1 , through the MOSFET N 21 , a current Ir 1  proportional to the current aI with a proportionality factor depending on the aspect ratios of the MOSFETs N 1  and N 21 . The current Ir 1  produces a local voltage reference signal MAT 11  which biases the gate of the MOSFET P 41  in the branch  5   b   1  and is also supplied to the non-inverting input of the comparator  61 . In the branch  5   b   1 , the signal MAT 11  tries to impose a current proportional to the current Ir 1 , whereas the memory cell MC 1  selected for reading, which is biased in similar conditions to the reference cells RC, that is, with its drain kept at approximately 1V by the circuit  31  and its control gate at the reading voltage Vread, absorbs a current Ic 1  which depends on its programming conditions. The difference between the current which the local reference signal MAT 11  tries to impose in the branch  5   b   1  and the current Ic 1  absorbed by the cell being read brings about an imbalance between the nodes MAT 11  and MATSIDE 1 , and hence in the inputs of the comparator  61 , the value of the output OUT 1  of which depends on this imbalance. The aspect ratios of the MOSFETs P 1 , P 2 , N 1 , N 21 , P 31  and P 41  are typically selected in a manner such that the current which is mirrored in the branch  5   b   1  is equal to a fraction of, for example, one half of, or is equal to, the current absorbed by a reference cell RC. 
     Clearly, the node MATSIDE 1 -MATSIDEn is coupled capacitively (via the respective MOSFET P 41 -P 4 n) to the signal MAT 11 -MAT 1 n, but is not coupled directly to the global reference signal RIFN. Thus although, in the reading circuit described, a single circuit  1  is used for generating the global reference signal RIFN which is supplied to a plurality of cell-reading circuits distributed in the memory device, the reference signal RIFN is not influenced by the imbalances which are brought about in the branches  5   b   1 - 5   b n (matrix branches) of the various reading circuits SA 1 -SAn. There is therefore no risk that the reading of a memory cell with a high margin will result in an incorrect reading of that cell or of the other memory cells, owing to the large imbalance which the reading brings about. 
     Moreover, since local mirroring is provided for by the branches  5   a   1 - 5   a n to derive locally, from the global reference signal RIFN, the local reference signal MAT 11 -MAT 1 n, from which a current signal is obtained in the branch  5   b   1 - 5   b n for comparison with the current absorbed by the memory cell, it is possible to start with a reference current I higher than that generated by a single reference cell. In other words, it is possible to use several reference cells in parallel and also to generate, by mirroring in the branch  2   b , a current aI such that the time required for the global reference signal RIFN to reach the steady value necessary for a correct reading to be taken can be reduced (a higher current aI permits quicker charging of the parasitic capacitances associated with the signal RIFN). 
     Although, in the foregoing description, a local mirror branch  5   a   1 - 5   a n for each cell-reading circuit SA 1 -SAn has been indicated, that is, a number of local mirror branches equal to the number of cell-reading circuits, it is also possible to provide a local mirror branch associated with a respective group of cell-reading circuits, thus reducing the number of local mirror branches. 
     FIG. 2 shows one of the cell-reading circuits of FIG. 1 in greater detail, complete with the respective precharging and equalization circuits. As well as being used for generating the reference current Ir 1  locally, the global reference signal RIFN also generates a signal MAT 21 -MAT 2 n by a further local mirror branch  71 - 7 n similar to the branch  5   a   1 - 5   a n. This signal can be connected to the node MATSIDE 1 -MATSIDEn, by a switch SW 11 -SW 1 n controlled by an equalization signal EQLZ. Moreover, the non-inverting input of the comparator  61 - 6 n is supplied by the signal MAT 21 -MAT 2 n instead of being supplied by the signal MAT 11 -MAT 1 n as shown in FIG.  1 . Alternatively, as also shown in FIG. 2, the non-inverting input of the comparator  61 - 6 n may be supplied by a further signal MAT 31 -MAT 3 n, also generated from the global reference signal RIFN, by a further mirror branch  81 - 8 n similar to the branch  7 a- 7 n. 
     Finally, FIG. 2 shows a MOSFET P 9 , controlled by the signal EQLZ, for enabling the comparator  61 - 6 n, and a circuit for precharging the output OUT 1 -OUTn of the comparator  61 - 6 n which can be connected, by a switch SW 21 -SW 2 n, controlled by a precharging signal PR, to a precharging signal VPR. The precharging signal VPR is typically equal to the triggering threshold of a first inverter in the circuit chain downstream of the comparator. 
     With reference also to FIG. 3, which shows a conventional timing scheme for reading in a memory device, the start of the reading operation is dictated by a signal START, which is activated, for example, upon the transition of the memory-addressing signals. The START signal brings about, among other things, the activation of the signal EQLZ which closes the switches SW 11 -SW 1 n, short-circuiting the nodes MATSIDE 1 -MATSIDEn to the nodes MAT 21 -MAT 2 n which are replicas of the signals MAT 11 -MAT 1 n. The two branches of each cell-reading circuit (the reference branch  5   a   1 - 5   a n and the matrix branch  5   b   1 - 5   b n) are thus equalized until the reference current and the current of the cell being read reach the steady value, that is, until the matrix line to which the matrix cell and the reference cell belong has been brought to the desired voltage. 
     At the same time, the precharging signal PR is activated and connects the outputs of the comparators  61 - 6 n to the precharging signal VPR. The signal EQLZ is then deactivated, the switches SW 11 -SW 1 n are opened, the equalization is interrupted and the nodes MATSIDE 1 -MATSIDEn are allowed to develop freely in dependence on the current absorbed by the respective cells being read. The precharging signal PR still remains active after the equalization has finished, and is then deactivated and the outputs OUT 1 -OUTn of the comparators are left free to adopt the value corresponding to the signals at their inputs. Finally, the activation of the signal EV brings about evaluation of the output of the comparators. 
     The local mirror branches  71 - 7 n for generating the signals MAT 21 -MAT 2 n are advantageously such that the current Ieq (the equalization current) which flows in them is greater than the current which flows in the branches  5   b   1 - 5   b n so that, although the signal MAT 21 -MAT 2 n is equal in value to the signal MAT 11 -MAT 1 n, it is sufficiently robust and stable not to be influenced by variations in the signal MATSIDE 1 -MATSIDEn. In other words, the p-channel MOSFET P 9  and the n-channel MOSFET N 6  have aspect ratios such that, although the signal MAT 21 -MAT 2 n has a value substantially equal to that of the signal MAT 11 -MAT 1 n, the mirror ratio of the current aI in the branches  71 - 7 n is greater than the mirror ratio of the current aI in the branches  5   b   1 - 5   b n. Thus, upon completion of the equalization stage, when the signal MAT 21 -MAT 2 n is no longer short-circuited to the signal MATSIDE 1 -MATSIDEn, the p-channel MOSFET P 8  (the input of the differential stage of the comparator  61 - 6 n) is still switched on. If the cell being read is a“ 0 ” with a high margin, the signal OUT 1 -OUTn starts to rise in voltage as soon as the equalization stage ends and does not have to wait for the resetting of the signal MAT 21 -MAT 2 n as would be necessary if the latter signal were influenced by the voltage value of the signal MATSIDE 1 -MATSIDEn. 
     The insertion of the further local mirror branch  81 - 8 n for generating the signal MAT 31 -MAT 3 n, which is independent of the signal MAT 21 -MAT 2 n, provides even greater certainty that the reference input (the non-inverting input) of the comparator  61 - 6 n is not influenced by the voltage of the signal MATSIDE 1 -MATSIDEn. It is noted that what is described above, in particular, the generation of the local signal MAT 21 -MAT 2 N by mirroring of the reference signal but with a higher mirror ratio, is not applicable exclusively to the reading circuit of FIG. 1, but may also be applied to conventional reading circuits. 
     FIG. 4 shows a reading timing scheme which is novel and particularly advantageous in comparison with that of FIG.  3 . In contrast with the conventional timing scheme, the signal PR for precharging the outputs of the comparators is not activated simultaneously with the activation of the equalization signal EQLZ but subsequently, but nevertheless before the end of the equalization stage (the deactivation of the signal EQLZ which also brings about enabling of the comparator  61 - 6 n by the MOSFET P 9 ). That is to say, the duration of the stage in which the outputs of the comparators are precharged is reduced, thus considerably reducing consumption. It is noted that this new and advantageous timing scheme is not exclusively usable in the reading circuit of FIG. 1 but may also be used in conventional reading circuits and, in any case, in all reading circuits in which an equalization of the comparator inputs and a precharging of the comparator outputs take place. 
     To return to FIG. 2, the switches SW 11 -SW 1 n are normally formed by a simple transfer gate, that is, an n-channel MOSFET and a p-channel MOSFET with their terminals connected to one another and their gates controlled by the signal EQLZ and EQLZN (the logic complement of EQLZ), respectively. However, since the capacitive coupling between the signal EQLZ and the node MATSIDE 1 -MATSIDEn is different from the capacitive coupling between this latter node and the signal EQLZN, upon completion of the equalization (when the switch SW 11 -SW 1 n is opened) the voltage value at the node MATSIDE 1 -MATSIDEn differs from that at the node MAT 11 -MAT 1 n. This introduces a dynamic offset at the input of the comparator and, since a certain time is required to compensate for this offset, the time required to complete the reading increases. 
     FIG. 5 shows in detail an embodiment of the switch SW 11 -SW 1 n which solves the problem just described. Instead of a simple transfer gate, the switch SW 11 -SW 1 N comprises a transfer gate formed by MOSFETs N 3  and P 5 , which are controlled by the signals EQLZ and EQLZN, respectively, and two further, false transfer gates, one upstream, formed by MOSFETs N 4  and P 6 , which are controlled by the signals EQLZN and EQLZ respectively, and one downstream, formed by MOSFETs N 5  and P 7 , which are also controlled by the signals EQLZN and EQLZ, respectively. In both of the two false transfer gates, the MOSFETs N 4 , P 6 , N 5 , P 7  have their respective drains and sources short-circuited so as not to alter the low-frequency behaviour of the reading circuit. 
     With reference to FIG. 6, which illustrates the operating principle of the circuit of FIG. 5, it will be noted that when, upon completion of the equalization stage, the signal EQLZ switches from the high state to the low state, the charge removed by division by the MOSFET N 3 , which is equal to QN/2 on the drain side towards MAT 11 -MAT 1 n and QN/2 on the source side towards MATSIDE 1 -MATSIDEn, is compensated for by the charge injected by the two MOSFETs N 4 , N 5  of the two false transfer gates disposed upstream and downstream, which is equal to QN/4 towards the drain and QN/4 towards the source for each of the two MOSFETs N 4  and N 5 . Similarly, the charge injected by the MOSFET P 5 , which is equal to QP/2 on the source side and QP/2 on the drain side, is compensated for by the charge extracted by the two MOSFETs P 6 , P 7  of the two false transfer gates disposed upstream and downstream, which is equal to QP/4 towards the drain and QP/4 towards the source for each of the two MOSFETs P 6 , P 7 . No dynamic offset is thus introduced and the time required to complete the reading operation is reduced. Naturally, similar considerations also apply to the switches SW 21 -SW 2 n of FIG.  2 . It is noted that the equalization switch of FIGS. 5 and 6 is not exclusively usable in the reading circuit of FIG. 1, but may also be used in reading circuits of other types, for example, in conventional or other circuits and, in general, in all circuits in which a stage of finite duration is provided for equalizing two nodes.