Abstract:
An output circuit includes first, second and third transistors. The first transistor includes first and second diffusion layers. The third transistor includes third and fourth diffusion layers. The first transistor shares the second diffusion layer with the second transistor and the third transistor shares the third diffusion layer with the second transistor. The second transistor is rendered conductive responsive to an activation of a first signal and non-conductive responsive to an inactivation of the first signal. The first and third transistors are rendered conductive responsive to an activation of a second signal that is different from the first signal and rendered non-conductive responsive to an in activation of the second signal.

Description:
PRIORITY 
       [0001]    This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-043172 filed on Mar. 5, 2014, the disclosure of which are incorporated herein in its entirely by reference. 
       TECHNICAL FIELD 
       [0002]    Embodiments of the present invention relate generally to an output circuit of a semiconductor device, more specifically, an impedance adjustable output circuit of a semiconductor device. 
       BACKGROUND 
       [0003]    A calibration circuit is provided in certain semiconductor devices in order to adjust the impedance of an output buffer resulting in adjusting the impedance of an output terminal. Japanese Patent Application Laid-Open No. 2011-61580 shows an example of such a calibration circuit. The output buffer includes multiple transistors coupled in parallel, and its impedance is adjusted by specifying the number of transistors to be activated through a selection signal generated by the calibration circuit. 
         [0004]    For example, when five transistors that are binary-weighted are coupled in parallel, 32 stages of impedance adjustment can be performed, which include a stage of deactivating all the transistors and a stage of activating all the transistors. However, because the lengths of respective interconnects between the transistors and the output terminal are different from one another, selection of a transistor results in a change in the interconnect resistance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a functional block diagram of a semiconductor device according to an embodiment of the present invention. 
           [0006]      FIG. 2  is a functional block diagram of an input/output circuit according to an embodiment of the present invention. 
           [0007]      FIG. 3  is a schematic diagram of a front-stage circuit according to an embodiment of the present invention. 
           [0008]      FIG. 4  is a schematic diagram of a unitary buffer according to an embodiment of the present invention. 
           [0009]      FIG. 5  shows the layout of a portion between a data terminal and an output circuit according to an embodiment of the present invention. 
           [0010]      FIG. 6  depicts a multi-level wiring structure included in the semiconductor device of the first embodiment according to an embodiment of the present invention. 
           [0011]      FIG. 7  is a view of a layout of a unitary buffer according to an embodiment of the present invention. 
           [0012]      FIG. 8  is a state diagram (state  1 ) of a unitary buffer as according to a comparative example. 
           [0013]      FIG. 9  is a state diagram (state  2 ) of a unitary buffer as according to a comparative example. 
           [0014]      FIG. 10  is a state diagram (state  1 ) of a unitary buffer according to an embodiment of the present invention. 
           [0015]      FIG. 11  is a state diagram (state  2 ) of a unitary buffer according to an embodiment of the present invention. 
           [0016]      FIG. 12  shows a detailed layout of diffusion layers and gate electrodes in a region where a unitary buffer is formed according to an embodiment of the present invention. 
           [0017]      FIG. 13  shows a detailed layout of first signal lines formed as a first wiring layer in a region where a unitary buffer is formed according to an embodiment of the present invention. 
           [0018]      FIG. 14  shows a detailed layout of first signal lines formed as a first wiring layer in a region where a unitary buffer is formed according to an embodiment of the present invention. 
           [0019]      FIG. 15  shows a detailed layout of second signal lines formed as a second wiring layer in a region where a unitary buffer is formed according to an embodiment of the present invention. 
           [0020]      FIG. 16  is a view of a unitary buffer according to an embodiment of the present invention. 
           [0021]      FIG. 17  is a (A-A′) sectional view of a vertical transistor according to an embodiment of the present invention; and 
           [0022]      FIG. 18  is a (B-B′) sectional view of a vertical transistor according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
         [0024]      FIG. 1  is a functional block diagram of a semiconductor device  10  according to a first embodiment of the present invention. 
         [0025]    The semiconductor device  10  of the first embodiment is a DRAM (Dynamic Random Access Memory) integrated into a single semiconductor chip and is mounted on an external board  2 . The external board  2  is a printed circuit board, such as a mother board, module board, and package board, and includes an external resistance Re, which has one end coupled to a calibration terminal ZQ of the semiconductor device  10 . In the first embodiment, the external resistance Re has a resistance value of, for example, 240Ω. A ground voltage VSS is supplied to the other end of the external resistance Re. 
         [0026]    The semiconductor device  10  includes a memory cell array  11 , which has multiple word lines WL, multiple bit lines BL, and memory cells MC disposed at the intersections of the word lines WL and bit lines BL. A word line WL is selected by a row decoder  12 , while a bit line BL is selected by a column decoder  13 . The semiconductor device  10  also includes clock terminals  23 , command address terminals  21 , a chip select terminal  22 , data terminals  24 , power supply terminals  25  and  26 , and the calibration terminal ZQ, which serve as external terminals of the semiconductor device  10 . 
         [0027]    External clock signals CK and /CK input to a clock input circuit  36  are supplied to a clock generating circuit  54 . Based on the external clock signals CK and /CK, the clock generating circuit  54  generates an internal clock signal ICLK. 
         [0028]    In synchronization with the internal clock ICLK, an address latching circuit  32  latches an address signal ADD. A row address indicated by the latched address signal ADD is supplied to the row decoder  12 , while a column address indicated by the latched address signal ADD is supplied to the column decoder  13 . When the semiconductor device  10  enters into a mode register set, the address signal ADD is supplied as a mode setting signal to a mode register  14 . Parameters indicative of operation modes of the semiconductor device  10  are set in the mode register  14 . In  FIG. 1 , a drive capability signal DS is shown, which is one of operation mode parameters indicated by the mode register. The drive capability signal DS specifies the number of unitary buffers to be activated when data is output, out of multiple unitary buffers in an input/output circuit  16 . The drive capability signal DS will be described in detail later. 
         [0029]    A command decoding circuit  34  holds, decodes, and counts command signals CMD in synchronization with the internal clock ICLK, and generates various internal commands, which include an active signal IACT, a column signal ICOL, a mode register set signal MRS, and a calibration signal ZQCOM. 
         [0030]    The calibration signal ZQCOM is activated when the command signal CMD indicates a calibration command. The calibration command is issued when the semiconductor device  10  is initialized and is also issued regularly when the semiconductor device  10  is in normal operation. The calibration signal ZQCOM activates the calibration circuit  100 . In response to the calibration signal ZQCOM, the calibration circuit  100  executes a calibration operation in synchronization with the internal clock ICLK, and adjusts the impedance of an output circuit  101  included in the input/output circuit  16 . The details of the output circuit  101  will be described later. 
         [0031]    The power supply terminals  25  are supplied with source voltages VDD and VSS, which are supplied to an internal power generating circuit  39  via the power supply terminals  25 . Based on the source voltages VDD and VSS, the internal power generating circuit  39  generates various internal voltages VPP, VOD, VARY, and VPERI. 
         [0032]    The power supply terminals  26  are supplied with source voltages VDDQ and VSSQ, which are supplied to the input/output circuit  16 , where the source voltages VDDQ and VSSQ are used as operating voltages for the output circuit  101  included in the input/output circuit  16 . The source voltage VDDQ is identical in potential with the source voltage VDD, and the source voltage VSSQ is identical in potential with the source voltage VSS. However, the power supply route for the source voltages VDDQ and VSSQ is separated from the power supply route for the source voltages VDD and VSS lest power noises generated by the operation of the output circuit  101  should propagate to other circuits. According to the present invention, however, such power supply route separation is not essential. 
         [0033]      FIG. 2  is a block diagram of a configuration of an input/output circuit  16  according to an embodiment of the invention. 
         [0034]    As shown in  FIG. 2 , the input/output circuit  16  includes the output circuit  101 , an input buffer  170 , front-stage circuits  141 ,  142 , and  143 , and an output control circuit  150 . The input/output circuit  16  further includes an electrostatic protection unit  160 . 
         [0035]    The output circuit  101  includes three output units  110 ,  120 , and  130 . The number of the output units of the present invention, however, is not limited to three. 
         [0036]    The output unit  110  includes four unitary buffers  111  to  114  and damping resistances R 11  and R 12  which have the same resistance value of, for example, 60Ω and are coupled in parallel to each other. The output unit  120  includes two unitary buffers  121  and  122  and a damping resistance R 13  having a resistance value of, for example, 60Ω The output unit  130  includes one unitary buffer  131  and a damping resistance R 14  having a resistance value of, for example, 120Ω (r1). A high-resistance wiring layer can be used for the damping resistances R 11  to R 14 , for example, a diffusion layer, tungsten (W), titanium nitride (TiN), etc. The number of the unitary buffers and damping resistances in the output units and the resistance values of the damping resistances according to the present invention are not limited to the number and resistance values indicated in  FIG. 2 . The unitary buffers  111  to  114 ,  121 ,  122 , and  131  are each impedance-adjustable. According to the first embodiment, the impedance of each of the unitary buffers  111  to  114 ,  121 ,  122 , and  131  is adjusted to, for example, 120Ω. This configuration allows a single calibration circuit to collectively adjust the impedances of multiple unitary buffers, thus simplifying a calibration operation. 
         [0037]    At the front stage to the output units  110  to  130  are the front-stage circuits  141  to  143 , respectively. The front-stage circuits  141  to  143  determine whether or not to activate the corresponding output units and adjust the impedances of unitary buffers included in the corresponding output units. As shown in  FIG. 2 , the front-stage circuits  141  to  143  are supplied with activating signals  151 P to  153 P (data) and activating signals  151 N to  153 N (data) from an output control circuit  150 , respectively, and are further supplied with a common impedance adjusting information DRZQ and common enable signals PUMAINB and PDMAIN from the calibration circuit  100 . Specifically, when instructed by the activating signals (data)  151 P to  153 P or activating signals (data)  151 N to  153 N to activate the corresponding output units, the front-stage circuits  141  to  143  specify which one of multiple output transistors (which will be described later) included in each of the unitary buffers  111  to  114 ,  121 ,  122 , and  131  in the corresponding output units is to be activated, according to the impedance adjusting information DRZQ and enable signals PUMAINB and PDMAIN. Activation of the output transistors are thus specified by the activating signals  141 P to  143 P and activating signals  141 N to  143 N. 
         [0038]    Enable signals PUEN and PDEN are signals that give an instruction to activate the output units  110 ,  120 , and  130 . The output control circuit  150  may supply test signals TSDN and TSDP (not depicted) that give an instruction to execute a test, to the output units  110 ,  120 , and  130 . 
         [0039]    The output control unit  150  specifies any one or ones of the multiple output units  110  to  130  as an output unit to be activated and also specifies the output logical level of a unitary buffer to be activated. The output control unit  150  specifies an output unit to be activated, based on the drive capability signal DS supplied from the mode register  14 . 
         [0040]    In this manner, the output control unit  150  selects one or more output units to be activated based on the drive capability signal DS, thereby changes the number of unitary buffers that drive the data terminal. A change in the number of unitary buffers to be activated results in a change in the (output) impedance of the output terminal. As shown in  FIG. 2 , according to the first embodiment, the unitary buffers  111  to  114 ,  121 ,  122 , and  131  are coupled in parallel between the output control circuit  150  and the data terminal  24 . As a result, an increase in the number of unitary buffers to be activated results in a decrease in the output impedance, and an decrease in the number of unitary buffers to be activated results in an increase in the output impedance. 
         [0041]      FIG. 3  is a circuit diagram of the front-stage circuit  143  according to an embodiment of the invention. 
         [0042]    Since the front-stage circuits  141  and  142  are identical in configuration with the front-stage circuit  143 , the front-stage circuit  143  will be described as a typical example of the front-stage circuits. The front-stage circuit  143  includes six OR circuits  301  to  306  and six AND circuits  311  to  316 . The OR circuits  301  to  305  are supplied with the common activating signal  153 P (read data) from the output control signal  150  and are also supplied with impedance adjusting information DRZQP 1  to DRZQP 5  from the calibration circuit  100 , respectively. The OR circuit  306  is supplied with the activating signal  153 P (read data) and with the enable signal PUMAINB. 
         [0043]    The AND circuits  311  to  315  are supplied with the common activating signal  153 N (read data) from the output control signal  150  and are also supplied with the impedance adjusting information DRZQN 1  to DRZQN 5  from the calibration circuit  100 , respectively. The AND circuit  316  is supplied with the activating signal  153 N (read data) and with the enable signal PDMAIN. 
         [0044]    The activating signals  153 P and  153 N (read data) are controlled according to the logical value of data to be output from the corresponding data terminal DQ. Specifically, when a high-voltage level signal is output from the corresponding data terminal DQ, the activating signals  153 P and  153 N are set to a low-voltage level. When a low-voltage level signal is output from the corresponding data terminal DQ, the activating signals  153 P and  153 N are set to a high-voltage level. When an ODT (On Die Termination) function is used, by which the output circuit  101  serves as a terminal resistance, the activating signal  153 P is set to a low-voltage level while the activating signal  153 N is set to a high-voltage level. 
         [0045]    Selection signals  143 P 1  to  143 P 5  (= 143 P) output from the OR circuits  301  to  305  and selection signals  143 N 1  to  143 N 5  (= 143 N) output from the AND circuits  311  to  315  are supplied to the output circuit  101 , as shown in  FIG. 2 . An enable signal PUEN output from the OR circuit  306  and an output signal PDEN from the AND circuit  316  are also supplied to the output circuit  101 . 
         [0046]      FIG. 4  is a circuit diagram of the unitary buffer  131  according to an embodiment of the invention. 
         [0047]    Since the other unitary buffers are identical in configuration with the unitary buffer  131 , the unitary buffer  131  will be described as a typical example of unitary buffers. 
         [0048]    As shown in  FIG. 4 , the unitary buffer  131  has multiple output PMOS transistors coupled in parallel between a power line (source voltage VDDQ) and a node B, and further has multiple output NMOS transistors coupled in parallel between a power line (source voltage VSSQ) and the node B. According to this embodiment, the output PMOS transistors have the same size as one another, that is, have the same width/length ratio as one another. Likewise, the output NMOS transistors have the same size as one another, that is, have the same width/length ratio as one another. However, the sizes of the output PMOS transistors are not limited to the same size but may be different from each other. Likewise, the sizes of the output NMOS transistors are not limited to the same size but may be different from each other. The node B is coupled to the data terminal  24  via the damping resistance R 14 . The part of unitary buffer  131  that includes the output PMOS transistors serves as a pull-up circuit  18 , while the part of unitary buffer  131  that includes of the output NMOS transistors serves as a pull-down circuit  19 . 
         [0049]    The gates of the output PMOS transistors of the pull-up circuit  18  are supplied with five selection signals  143 P 1  to  143 P 5  serving as the selection signal  143 P, and the gates of the output NMOS transistors of the pull-down circuit  19  are supplied with five selection signals  143 N 1  to  143 N 5  serving as the selection signal  143 N. The pull-up circuit  18  includes transistor groups TrGP 1  to TrGP 5  (adjusting unit  102 D) coupled in parallel. The transistor group TrGP 1  includes one output PMOS transistor that receives the selection signal  143 P 1  at the gate electrode thereof. The drive capability of the transistor group TrGP 1  is, therefore, one time (×1) the drive capability of one output PMOS transistor. The transistor group TrGP 2  includes two PMOS transistors that receive the selection signal  143  at the gate electrodes thereof. The drive capability of the transistor group TrGP 2  is, therefore, two times (×2) the drive capability of one output PMOS transistor. The drive capabilities of other transistor groups are determined in the same manner. For example, the transistor group TrGP 5  includes 16 output PMOS transistors that receive the selection signal  143 P 5  at the gate electrodes thereof. The drive capability of the transistor group TrGP 5  is, therefore, 16 times (×16) the drive capability of one output PMOS transistor. 
         [0050]    The pull-down circuit  19  includes transistor groups TrGN 1  to TrGN 5  (adjusting unit  102 N) coupled in parallel. The transistor group TrGN 1  includes one transistor that receives the selection signal  143 N 1  at the gate electrode thereof. The drive capability of the transistor group TrGN 1  is, therefore, one time (×1) the drive capability of one output NMOS transistor. The transistor group TrGN 2  includes two NMOS transistors that receive the selection signal  143 N 2  at the gate electrodes thereof. The drive capability of the transistor group TrGN 2  is, therefore, two times (×2) the drive capability of one output NMOS transistor. The drive capabilities of other transistor groups are determined in the same manner. For example, the transistor group TrGN 5  includes 16 transistors that receive the selection signal  143 N 5  at the gate electrodes thereof. The drive capability of the transistor group TrGN 5  is, therefore, 16 times (×16) the drive capability of one output NMOS transistor. 
         [0051]    The pull-up circuit  18  also includes a transistor group TrGPA and a transistor group TDP. The transistor group TrGPA includes six output PMOS transistors that receive the enable signal PUEN at the gate electrodes thereof. The drive capability of the transistor group TrGPA is, therefore, six times (×6) the drive capability of the unit transistor. The transistor group TrGPA is a circuit that upon activation of the output unit  110 , operates according to the activating signal  153 P, regardless of the impedance adjusting information DRZQP. 
         [0052]    The transistor group TDP includes two PMOS transistors that receive a test signal TSPD at gate electrodes thereof. The drive capability of the transistor group TDP is, therefore, two times (×2) the drive capability of the output PMOS transistor. The test signal TSDP is activated when a test is conducted. 
         [0053]    The pull-down circuit  19  also includes a transistor group TrGNA and a transistor group TDN. The transistor group TrGNA includes six output NMOS transistors that receive the enable signal PDEN at the gate electrodes thereof. The drive capability of the transistor group TrGNA is, therefore, six times (×6) the drive capability of the output NMOS transistor. The transistor group TrGNA is a circuit that upon activation of the output unit  110 , operates according to the activating signal  153 N, regardless of the impedance adjusting information DRZQN. 
         [0054]    The transistor group TDN includes two output NMOS transistors that receive a test signal TSDN at the gate electrodes thereof. The drive capability of the transistor group TDN is, therefore, two times (×2) the drive capability of the output NMOS transistor. The test signal TSDN is activated when a test is conducted. 
         [0055]    The pull-up circuit  18  and the pull-down circuit  19  are so designed that they each have a given impedance (120Ω in this embodiment) when supplied with current. However, the on-resistance of transistors varies depending on manufacturing conditions and changes according to environmental temperatures and source voltages during operation of the transistors. It is therefore not always possible for the pull-up circuit  18  and pull-down circuit  19  to achieve the desired impedance. For this reason, to achieve an actual target impedance, the number of transistors to be switched on must be adjusted. 
         [0056]      FIG. 5  shows the layout of a part between the data terminal  24  and the output circuit  101  according to an embodiment of the invention.  FIG. 6  depicts a multi-level wiring structure included in the semiconductor device  10  of the first embodiment. 
         [0057]    As shown in  FIG. 6 , the semiconductor device  10  of the first embodiment has a multi-level wiring structure in which diffusion layers DL are formed in a substrate SS, gate wiring layers GL are formed on the surface of the substrate SS. On the gate wiring layers GL, a first wiring layer L 1 , a second wiring layer L 2 , a third wiring layer L 3 , and a fourth wiring layer L 4  are overlaid in increasing order in which the first wiring layer L 1  is the closest to the surface of the substrate SS. The first wiring layer L 1  is, for example, a wiring layer containing tungsten, and each of the second to fourth wiring layers is a wiring layer containing aluminum, copper, etc. These wiring layers are insulated from one another via inter-layer insulating layers IL 1  to IL 4 . The upper surface of the uppermost fourth wiring layer L 4  is covered with a protective inter-layer insulating layer IL 5 . A thin gate insulating film GI is formed between the gate wiring layer GL and the surface of the substrate SS. The diffusion layer DL, the gate wiring layer GL, and the first wiring layer L 1  are electrically coupled at their necessary parts via through-hole electrodes TH 0  penetrating the first insulating layer IL 1 . In the same manner, the first wiring layer L 1  and the second wiring layer L 2  are electrically coupled at their necessary parts via through-hole electrodes TH 1  penetrating the second insulating layer IL 2 . The second wiring layer L 2  and the third wiring layer L 3  are electrically coupled at their necessary parts via through-hole electrodes TH 2  penetrating the third insulating layer IL 3 . The third wiring layer L 3  and the fourth wiring layer L 4  are electrically coupled at their necessary parts via through-hole electrodes TH 3  penetrating the fourth insulating layer IL 4 . 
         [0058]    As shown in  FIG. 5 , an area, which is between a data pad DQP (corresponding to the data terminal  24 ) formed as the fourth wiring layer L 4  and the output circuit  101 , includes an ESD element ESD 1  formed into an MOS transistor structure. Further included are damping resistances R 11  to R 14  each formed as the first wiring layer L 1 , a data line DQL 1 , which is formed as the second wiring layer L 2  and passes above the ESD element ESD 1  to connect the data pad DQP to respective one ends of the damping resistances R 11  to R 14 , and data lines DQL 2  each of which connects the other end of the corresponding damping resistance out of the damping resistances R 11  to R 14  to one or ones of unitary buffers corresponding to the data line DQL 2  out of the unitary buffers  111  to  114 ,  121 ,  122 , and  131 . The ESD element ESD 1  includes sources and drains formed as the diffusion layers DL in the substrate SS made of silicon, etc., and gate electrodes G formed on the substrate SS. One of the sources and drains of the ESD element ESD 1  are coupled to the data line DQL 1  via the through-holes TH 0  and TH 1  and the first wiring layer L 1  (which are not shown in  FIG. 5 ). The other of the sources and drains of the ESD element ESD 1  are coupled to a power line (source voltage VSS), which is not depicted. The data pad DQP is coupled to the data line DQL 1  via the through-holes TH 2  and TH 3  and the third wiring layer L 3  (which are not shown in  FIG. 5 ). The data line DQL 1  and respective one ends of the damping resistances R 11  to R 14  are coupled via the through-hole electrodes TH 1 . Similarly, the other ends of the damping resistances R 11  to R 14  and the data line DQL 2  are coupled via the corresponding through-hole electrodes TH 1 . The front-stage circuits  141  to  143  are disposed adjacent to the output circuit  101 , which is not shown in  FIG. 5 . 
         [0059]      FIG. 7  is a view of the layout of a part of the pull-up circuit  18  of  FIG. 4  according to an embodiment of the invention. Specifically,  FIG. 7  depicts the layout of the transistor groups TrGP 1  to TrGP 5 . To make the description of an operation principle clear, the transistor groups TrGPA and TDP are omitted from  FIG. 7 . 
         [0060]    In  FIG. 7 , transistors Tr 0  to Tr 30  correspond to the multiple output PMOS transistors of  FIG. 4 . Each of the transistors Tr 0  to Tr 30  includes a source diffusion layer S and a drain diffusion layer D, which are formed as the diffusion layers DS in the substrate SS, and a gate electrode G formed as the gate wiring layer GL. Under the gate electrode G, a channel region is formed as a region defined between the source diffusion layer S and the drain diffusion layer D. It is preferable that channel widths W (lengths of the channel regions in the x direction) of the transistors Tr 0  to Tr 30  be substantially equal to one another and that channel lengths (lengths of the channel regions in the y direction) of the same be substantially equal to one another. It is clearly understood from  FIG. 7  that transistors adjacent to each other in the y direction share the source diffusion layer or drain diffusion layer. For example, the transistor Tr 1  and the transistor Tr 2  share the source diffusion layer S 1 . 
         [0061]    The drain diffusion layers DO to D 15  of the transistors Tr 0  to Tr 30  are all coupled to the output terminal  24  via an interconnect  116 . The source diffusion layers S 0  to S 15  of the transistors Tr 0  to Tr 30  are supplied with the common source voltage VDDQ, which is not depicted in  FIG. 7 . 
         [0062]    16 transistors Tr 0 , Tr 2 , Tr 4 , Tr 6 , Tr 8 , Tr 10 , Tr 12 , Tr 14 , Tr 16 , Tr 18 , Tr 20 , Tr 22 , Tr 24 , Tr 26 , Tr 28 , and Tr 30  correspond to the output PMOS transistors included in the transistor group TrGP 5 . Likewise, eight transistors Tr 1 , Tr 5 , Tr 9 , Tr 13 , Tr 17 , Tr 21 , Tr 25 , and Tr 29  correspond to the transistors included in the transistor group TrGP 4 , four transistors Tr 3 , Tr 11 , Tr 19 , and Tr 27  correspond to the transistors included in the transistor group TrGP 3 , two transistors Tr 7  and Tr 23  correspond to the transistors included in the transistor group TrGP 2 , and a transistor Tr 15  corresponds to the transistor included in the transistor group TrGP 1 . 
         [0063]    As shown in  FIG. 7 , the gate electrodes G 0 , G 2 , G 4 , G 6 , G 8 , G 10 , G 12 , G 14 , G 16 , G 18 , G 20 , G 22 , G 24 , G 26 , G 28 , and G 30  of the transistors Tr 0 , Tr 2 , Tr 4 , Tr 6 , Tr 8 , Tr 10 , Tr 12 , Tr 14 , Tr 16 , Tr 18 , Tr 20 , Tr 22 , Tr 24 , Tr 26 , Tr 28 , and Tr 30  are all coupled to a signal line X 16  through which the selection signal  143 P 5  is transmitted. Likewise, gate electrodes G 1 , G 5 , G 9 , G 13 , G 17 , G 21 , G 25 , and G 29  are all coupled to a signal line X 8  through which the selection signal  143 P 4  is transmitted, gate electrodes G 3 , G 11 , G 19 , and G 27  are all coupled to a signal line X 4  through which the selection signal  143 P 3  is transmitted, gate electrodes G 7  and G 23  are all coupled to a signal line X 2  through which the selection signal  143 P 2  is transmitted, and a gate electrode G 15  is coupled to a signal line X 1  through which the selection signal  143 P 1  is transmitted. 
         [0064]    According to this embodiment, the transistors Tr 0  to Tr 30  are laid out based on the following method. 
         [0065]    First, a group  1  is made up by putting a set of two transistors from the transistor group TrGP 5  and one transistor from the transistor group TrGP 4  together. This process is repeated for all sets of two transistors from the transistor group TrGP 5  and all transistors from the transistor group TrGP 4  to create multiple groups  1 . In each group  1 , one transistor from the transistor group TrGP 4  is placed between two transistors from the transistor group TrGP 5 . For example, a group of the transistors Tr 0  to Tr 2  shown in  FIG. 7  constitutes a group  1 . As a result, eight groups  1  are created in  FIG. 7 . 
         [0066]    Then, two groups  1  out of the multiple groups  1  and one transistor from the transistor group TrGP 3  are put together to make up a group  2 . This process is repeated for all sets of two groups  1  out of the multiple groups  1  and all transistors from the transistor group TrGP 3  to create multiple groups  2 . In each group  2 , one transistor from the transistor group TrGP 3  is placed between two groups  1 . For example, a group of the transistors Tr 0  to Tr 6  shown in  FIG. 7  constitutes a group  2 . As a result, four groups  2  are created in  FIG. 7 . 
         [0067]    Subsequently, two groups  2  out of the multiple groups  2  and one transistor from the transistor group TrGP 2  are put together to make up a group  3 . This process is repeated for all sets of two groups  2  out of the multiple groups  2  and all transistors from the transistor group TrGP 2  to create multiple groups  3 . In each group  3 , one transistor from the transistor group TrGP 2  is placed between two groups  2 . For example, a group of the transistors Tr 0  to Tr 14  shown in  FIG. 7  constitutes a group  3 . As a result, two groups  3  are created in  FIG. 7 . 
         [0068]    Finally, the transistor of the transistor group TrGP 1  is placed between two groups  3  to complete the layout of  FIG. 7 . 
         [0069]    This layout of the transistors making up the transistor groups TrGP 1  to TrGP 5  suppresses impedance variances caused by interconnect resistance differences between impedance adjustment steps. 
         [0070]      FIGS. 8 and 9  are views of the layouts of the pull-up circuit as comparative examples. In the comparative examples, the transistor groups TrGP 1  to TrGP 5  are lined up in the y direction. Specifically,  FIG. 8  depicts a state  1  in which the selection signals  143 P 1  to  143 P 4  (X 1 , X 2 , X 4 , X 8 ) are at low-voltage level, i.e., active level, while the selection signal  143 P 5  (X 16 ) is at high-voltage level, i.e., inactive level.  FIG. 9  depicts a state  2  in which the selection signals  143 P 1  to  143 P 4  (X 1 , X 2 , X 4 , X 8 ) are at high-voltage level, i.e., inactive level, while the selection signal  143 P 5  (X 16 ) is at low-voltage level, i.e., active level. In the comparative examples, transition between the state  1  and the state  2  leads to a significant change in the actual resistance of the signal line  116 . 
         [0071]      FIGS. 10 and 11  are layout views of the state  1  and the state  2  of the pull-up circuit of the first embodiment is applied.  FIGS. 10 and 11  clearly indicate that a change in the interconnect resistance of the signal line  116  is reduced, compared to the comparative examples of  FIGS. 8 and 9 . 
         [0072]    While the pull-up circuit  18  has been described so far, the multiple output NMOS transistors included in the pull-down circuit  19  may also be laid out by virtually the same method as the layout method for the pull-up circuit  18 . In such a case, the pull-down circuit  19  offers virtually the same effect as the effect offered by the pull-up circuit  18 . 
         [0073]    The method of arranging the transistors Tr according to the first embodiment is generalized in the following manner. When the selection signal  143 P is of n-bit signals, each of which corresponds to a different one of binary-weighted transistor groups, a transistor A 1  that receives a selection signal X 1  (first digit) as a gate signal is disposed at the center of the diffusion region. Then, two transistors A 2  that receive a selection signal X 2  (second digit) as a gate signal are so disposed that the transistor A 1  is placed between the two transistors A 2 . Four transistors A 3  that receive a selection signal X 4  (third digit) as a gate signal are so disposed that the two transistors A 2  are placed between the four transistors A 3 . Eight transistors A 4  that receive a selection signal X 8  (fourth digit) as a gate signal are so disposed that the four transistors A 3  are placed between the eight transistors A 4 . In the same manner, transistors A(n) that receive a selection signal for the n-th digit as a gate signal are so disposed that transistors A (n−1) for the (n−1)-th digit are placed between the transistors A(n). 
         [0074]      FIG. 12  shows a detailed layout of diffusion layers and gate electrodes in a region where a unitary buffer is formed according to an embodiment of the present invention. In the first embodiment, each of the pull-down circuit  19  and the pull-up circuit  18  is provided with the 16-channel transistor, as shown in  FIG. 4 . Transistor groups TrGNA and TDN not involved in impedance adjustment are disposed next to the transistor groups TrGNA. On both ends of the diffusion layers DL, dummy lines are disposed. 
         [0075]      FIGS. 13 and 14  shows detailed layouts of first signal lines formed as the first wiring layer L 1  in the region where the unitary buffer  131  is formed according to an embodiment of the present invention.  FIGS. 13 and 14  depict the same wiring layers. A number of through-hole electrodes TH 0  shown in  FIG. 13  couple multiple first signal lines  103  formed as the first wiring layer L 1  to multiple signal lines (including gate electrodes) formed as diffusion layers DL and gate wiring layers GL of  FIG. 12 , respectively. A number of through-hole electrodes TH 1  shown in  FIG. 14  connect the multiple first signal lines to multiple second signal lines  104  formed as the second wiring layer L 2  of  FIG. 15  (which will be described later), respectively. 
         [0076]    As shown in  FIGS. 12 to 15 , the selection signals  143 P 3  to  143 P 5  and  143 N 3  to  143 N 5 , the enable signals PUEN and PDEN, and the test signals TSDP and TSDN are supplied from the front-stage circuit  143  through the second signal lines  104  to the region where the unitary buffer  131  is formed. These signals are transmitted from the second wiring layer L 2  through the through-hole electrodes TH 1  to the first wiring layer L 1 , i.e., first signal lines  103 . The first signal lines  103  are coupled to the signal lines making up the gate wiring layers GL (including the gate electrodes) under the first signal lines  103 , via the through-hole electrodes TH 0 . The selection signals  143 P 1 ,  143 P 2 ,  143 N 1 , and  143 N 2  are supplied from the front-stage circuit  143  through the first signal lines  103  to the region where the unitary buffer  131  is formed. 
         [0077]    A second embodiment of the present invention will now be described. According to the second embodiment, the multiple output PMOS transistors and NMOS transistors in the unitary buffer  131  are formed as vertical transistors. For simpler description, a unitary buffer not including the transistor groups TrGP 5  and TrGN 5  of  FIG. 4  will be described as an example. 
         [0078]      FIG. 16  is a view of a unitary buffer according to the second embodiment of the present invention. In the same manner as in  FIG. 9 , the transistor groups TrGPA and TDP are omitted from  FIG. 16  for clear description of the operation principle. 
         [0079]    In  FIG. 16 , vertical transistors VTr 0  to VTr 14  correspond to multiple output PMOS transistors. The structure of the vertical transistors will be described briefly by describing the structure of the vertical transistor VTr 0  as an example. 
         [0080]      FIG. 17  is an A-A′ sectional view of the vertical transistor VTr 0  of  FIG. 16  and  FIG. 18  is a B-B′ sectional view of the same. 
         [0081]    On the upper surface of a silicon substrate  701 , an element isolation region  702  made of an insulating film is formed. In an activation region  71 A made of the silicon substrate surrounded with the element isolation region  702 , a transistor pillar  705  serving as a semiconductor pillar is formed. On the side wall of the transistor pillar, a gate electrode  711   a  is so formed as to encircle the transistor pillar  705  with an intervention of a gate insulting film  710 , which is so formed as to encircle the transistor pillar  705  in the same manner as the gate electrode  711   a  does. On the upper end of the transistor pillar  705 , an upper diffusion layer  716  is formed as one of a source and a drain. On the lower end of the transistor pillar  705 , lower diffusion layers  709  are formed as the other of the source and the drain. The lower diffusion layers  709  are insulated from the gate electrode  711   a  via insulating layers  708 . In the vertical transistor of this configuration, a channel region is formed between the lower end and the upper end of the transistor pillar  705 . 
         [0082]    As shown in  FIG. 17 , a dummy pillar  706  is disposed adjacent to the transistor pillar  705 . The dummy pillar  706  includes a dummy silicon pillar  706 B and a dummy insulator pillar  706 A. On the side wall of the dummy pillar  706 , a gate electrode  711   b  is so formed as to encircle the dummy pillar  706 . The gate electrode  711   b  is electrically and physically coupled to the gate electrode  711   a . Signals, therefore, can be supplied to the gate electrode  711   a  via the gate electrode  711   b.    
         [0083]    On the element isolation region  702  and the dummy pillar  706 , an insulating film  703  and a mask film  704  are formed. On the periphery of the gate electrodes  711   a  and  711   b , a first inter-layer insulating film  712  is formed. On the mask film  704  and the first inter-layer insulating film  712 , a second inter-layer insulating film  720  is formed. 
         [0084]    A signal line  742  formed on the upper surface of the second inter-layer insulating film  720  is coupled to the signal line X 8  of  FIG. 16 , and is coupled to the gate electrode  711   b  via a contact  741 . A power line  733  formed on the upper surface of the second inter-layer insulating film  720  is coupled to the power line VDD of  FIG. 16 , and is coupled to a silicon plug  719  via a contact  730 . The silicon plug  719  is coupled to the upper diffusion layer  716 . On the side surface of the silicon plug  719 , a side wall film  718  and an insulating film  717  are disposed, so that the silicon plug  719  is insulated from the gate electrode  711   a  via the side wall film  718  and insulating film  717 . 
         [0085]    A signal line  734  formed on the upper surface of the second inter-layer insulating film  720  is coupled to the signal line OUT of  FIG. 16 , and is coupled to the lower diffusion layer  709  via a contact  735 . 
         [0086]    The vertical transistor VTr 0  is structured in the above manner. The other vertical transistors VTr 1  to VTr 14  are virtually identical in configuration with the vertical transistor VTr 0 . It is preferable that the vertical transistors VTr 0  to VTr 14  be virtually identical with each other in the widths of the pillar transistors  705 , that is, in their sectional areas along a cut plane parallel with the surface of the silicon substrate  701 . As shown in  FIGS. 16 and 18 , vertical transistors VTrn and VTrn+1 adjacent to each other may share one of the lower diffusion layers. 
         [0087]      FIG. 16  is referred to again. In  FIG. 16 , eight vertical transistors VTr 0 , VTr 2 , VTr 4 , VTr 6 , VTr 8 , VTr 10 , VTr 12 , and VTr 14  are included in the transistor group TrGP 4 , four vertical transistors VTr 1 , VTr 5 , VTr 8 , and VTr 13  are included in the transistor group TrGP 3 , two vertical transistors VTr 3  and VTr 11  are included in the transistor group TrGP 2 , and a transistor VTr 7  is included in the transistor group TrGP 1 . 
         [0088]    As shown in  FIG. 16 , the gate electrodes of the vertical transistors VTr 0 , VTr 2 , VTr 4 , VTr 6 , VTr 8 , VTr 10 , VTr 12 , and VTr 14  are all coupled to the signal line X 8  through which the selection signal  143 P 4  is transmitted. Likewise, the gate electrodes of the vertical transistors VTr 1 , VTr 5 , VTr 8 , and VTr 13  are all coupled to the signal line X 4  through which the selection signal  143 P 3  is transmitted, the gate electrodes of the vertical transistors VTr 3  and VTr 11  are all coupled to the signal line X 2  through which the selection signal  143 P 2  is transmitted, and the gate electrode of the vertical transistor Vtr 7  is coupled to the signal line X 1  through which the selection signal  143 P 1  is transmitted. 
         [0089]    In this manner, when vertical transistors are used as output PMOS transistors, the transistors can be arranged by the same method as described in the first embodiment, and therefore the same effect is achieved. As in the above case of providing the output PMOS transistors as the vertical transistors, multiple output NMOS transistors are provided as vertical transistors, in which case the output NMOS transistors are laid out by the same method and the effect virtually the same as the effect achieved in the case of the PMOS transistors can be achieved. 
         [0090]    Preferred embodiments of the present invention have been described above. The present invention is not limited to the above embodiments and may be modified into various forms on the condition that the modification does not deviate from the substance of the present invention. It is obvious that such modifications are also included in the scope of the invention. 
         [0091]    While the case of applying the present invention to a DRAM is described in the above embodiments, the present invention is not limited to this case. The present invention may be applied also to various semiconductor memories each having an output circuit including a parallel circuit composed of multiple transistors, such as SRAM, PRAM, ReRAM, MRAM, FeRAM, NAND-type flash memory, and NOR-type flash memory. The present invention is applied also to semiconductor devices other than semiconductor memories, such as logic IC, CPU, MPU, and ASIC.